commit f69754bccca24326482eba4b3de61ceb4bbf3936 Author: Olaf Rempel Date: Sun Jan 7 23:57:24 2024 +0100 u-boot 1.1.4 diff --git a/CHANGELOG b/CHANGELOG new file mode 100644 index 0000000..015932e --- /dev/null +++ b/CHANGELOG @@ -0,0 +1,4432 @@ +====================================================================== +Changes for U-Boot 1.1.4: +====================================================================== + +* Changes to Yellowstone & Yosemite 440EP/GR eval boards: + - Changed GPIO setup to enable another address line in order to + address 64M of FLASH. + - Added function sdram_tr1_set to auto calculate the tr1 value for + the DDR. + Patch by Steven Blakeslee, 12 Dec 2005 + +* MPC5200: Set PCI retry counter to 0 = infinite retry; + The default of 255 is too short for slow devices. + Patch by Martin Nykodym, 12 Dec 2005 + +* Change port configuration for O2DNT (CODEC1 on PSC1). + +* Fix register for PCI async mode on PPC440EP + Patch by Youngchul Bang, 08 Dec 2005 + +* Fix U-Boot linking problems (add .eh_frame segment to linker script) + This segment may be required by some libgcc.a functions + (like _udivdi3). + +* Fix DPRAM offset/size for MPC8541/8555. + Simplify TQM85xx Makefile handling. + +* Fix data overflow (typo?) in rtc/ds1302.c + +* Fix U-Boot compilation for MIPS boards using ELDK 4.0 + +* Add support for TQM8541/8555 boards, TQM85xx support reworked: + - Support for TQM8541/8555 boards added. + - Complete rework of TQM8540/8560 support. + - Common TQM85xx code now supports all current TQM85xx platforms + (TQM8540/8541/8555/8560). + - DDR SDRAM size detection added. + - CAS latency default values can be overwritten by setting "serial#" + to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used. + If problems are detected with this non default CAS latency, + the default values will be used instead. + - Flash size detection added. + - Moved FCC ethernet driver initialization behind TSEC driver init + -> TSEC is first device. + Patch by Stefan Roese, 30 Nov 2005 + +* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board. + Patch by John Otken, 23 Nov 2005 + +* Changed PPC44x startup message (cpu info, speed...) to common style: + On PPC44x platforms, the startup message generated in "cpu.c" only + comprised the ppc type and revision but not additional information + like speed etc. Those speed infos where printed in the board specific + code. This new implementation now prints all CPU infos in the common + cpu specific code. No board specific code is needed anymore and + therefore removed from all current 44x implementations. + Patch by Stefan Roese, 27 Nov 2005 + +* Adjust TQM834x PHY addresses for latest hardware revision. + +* Increase malloc arena on TQM5200 board to 256 kB. + With 64 kb uniform flash sector size the old value of 128 kB was + too small. + +* Fix miiphy global data initialization (problem on 4xx boards when + no ethaddr is assigned). Initialization moved from + miiphy_register() to eth_initialize(). + + Based on initial patch for 4xx platform by Matthias Fuchs. + +* Remove unnnecessary #include from include/asm-*/u-boot.h + +* Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code. + The COPYING file was extended to make clear that these files can be + used in non-GPL code, too. + Also, a corresponding note was placed in the headers of the affected files. + +* Add support for Prodrive P3P440 board: + - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c + - CFG_FLASH_QUIET_TEST added to use the common CFI driver + for bank autodetection + Patch by Stefan Roese, 22 Nov 2005 + +* Change all '$(...)' variable references into '${...}' + which makes the environment compatible with the hush shell. + WARNING: Support for the old '$(...)' syntax will be + discontinued in a later version. + +* Minor changes to init flags in TQM834x PCI. + +* Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM) + Patch by Stefan Roese, 15 Nov 2005 + +* New PPC 405EP board added: CMS700 + Added CONFIG_NET_MULTI for VOM405 board. + Added reset_phy() for VOM405 board. + Patch by Matthias Fuchs, 09 Nov 2005 + +* Updated PCI mapping for esd CPCI2DP board. + Add support for error LED. + Patch by Matthias Fuchs, 07 Nov 2005 + +* Fix MPC85xx PCI support (pci_register_hose() before pci config access) + Patch by Stefan Roese, 07 Nov 2005 + +* Correct PPC Timebase register definitions (SPRN_TBRL...) + Patch by Stefan Roese, 07 Nov 2005 + +* Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size + Patch by Stefan Roese, 05 Nov 2005 + +* Additional fix for external IRQ config on Yellowstone & Yosemite + Patch by Stefan Roese, 03 Nov 2005 + +* Add support for Ocotea pass 3 with 440GX Rev. F + Patch by Stefan Roese, 01 Nov 2005 + +* Fix external IRQ configuration on Yellowstone & Yosemite + Patch by Stefan Roese, 28 Oct 2005 + +* Add support for multiple PHYs. + Tested on the following boards: + cmcpu2 (at91rm9200/ether.c) + PPChameleon (ppc4xx/4xx_enet.c) + yukon (mpc8220/fec.c) + uc100 (mpc8xx/fec.c) + tqm834x (mpc834x/tsec.c) with EEPRO100 + lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c) + Main changes include: + common/miiphyutil.c + - miiphy_register routine was added to allow multiple PHYs to be registered + - miiphy_read and miiphy_write are now defined in this file, and + require additional argument (char *devname) + - other miiphy_* routines also require additional device name argument + ../lib_i386/board.c + ../lib_ppc/board.c + Calling reset_phy() was moved to be executed *after* eth_initialize(). + This is necessary as now some of the implementations of reset_phy() + may need to use miiphy_reset() which is not allowed before eth_initialize() + as eth_initialize registers all required miiphy_* routines. + Tested on IP860 and PHY initializes properly after this change. + +* Correct includes for flat tree builder. + +* Fix conflicting types (flash_write()) in trab auto_update.c. + +* Add PCI support for the TQM834x board. + +* Add missing 4xx board to MAKEALL + Patch by Stefan Roese, 20 Oct 2005 + +* Fix conflicting types (flash_write()) in esd auto_update.c + Patch by Stefan Roese, 20 Oct 2005 + +* Fix problem with sleep in NetConsole (use get_timer()) + Patch by Stefan Roese, 20 Oct 2005 + +* Add NetConsole Support for AMCC eval boards + Patch by Stefan Roese, 20 Oct 2005 + +* Fix NetConsole support on 4xx (only print eth link on 1st transfer) + Patch by Stefan Roese, 18 Oct 2005 + +* Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo. + Fix identation on ext2ls help entry. + Patch by Stefan Roese, 14 Oct 2005 + +* Add support for TQM834x boards. + Cleanup. + +* Cleanup for GCC-4.x + +* Add documentation for Open Firmware Flat Tree and usage. + Patch by Pantelis Antoniou, 13 Oct 2005 + +* Add missing files for Pantelis Antoniou's patch + Patch by Pantelis Antoniou, 04 Sep 2005 + +* Fix problem in ppc4xx eth-driver without ethaddr (only without + CONFIG_NET_MULTI set) + Patch by Stefan Roese, 10 Oct 2005 + +* Fix gzip bmp support (test if malloc fails, warning when truncated). + Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board. + Patch by Stefan Roese, 07 Oct 2005 + +* Add support for OF flat tree for the STXtc board. + Patch by Pantelis Antoniou, 04 Sep 2005 + +* Support passing of OF flat trees to the kernel. + Patch by Pantelis Antoniou, 04 Sep 2005 + +* Cleanup + +* Add support for NetSilicon NS7520 processor. + Patch by Art Shipkowski, 12 May 2005 + +* Add support for AP1000 board. + Patch by James MacAulay, 07 Oct 2005 + +* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200 + Patch by Anders Larsen, 07 Oct 2005 + + The Atmel errata #11 states that the transfer buffer descriptor + table must be aligned on a 16-word boundary. As it turned out, this + is insufficient - it seems the table must be aligned on a boundary + at least as large as the table itself (in Linux this is not an + issue - the table is aligned on a PAGE_SIZE (4096) boundary). + +* Fixed compilation for ARM when using a (standard) hard-FP toolchain + Patch by Anders Larsen, 07 Oct 2005 + +* Cleanup warnings for cpu/arm720t & cpu/arm1136 files. + sed the linker scripts, rather than pre-process them. + Patch by Peter Pearse, 07 Oct 2005 + +* Update make target for ARM supported boards. + Use lowlevel_init() instead of platformsetup() [rename]. + Patch by Peter Pearse, 06 Oct 2005 + +* Fix booting from serial dataflash on AT91RM9200 + Patch by Peter Menzebach, 29 Aug 2005 + +* Add JFFS2 support for TRAB board + Patch by Martin Krause, 25 Aug 2005 + +* Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI + Patch by Marcus Hall, 24 Aug 2005 + +* Fix the machine-id of the Cogent csb637 board + Patch by Anders Larsen, 05 Oct 2005 + +* Complete support for the KwikByte KB920x boards + Patch by Anders Larsen, 05 Oct 2005 + +* Set the AT91RM9200 clock to asynchronous mode + Patch by Anders Larsen, 03 May 2005 + +* Set the AT91RM9200 clock to synchronous mode + Patch by Anders Larsen, 29 Apr 2005 + +* Add support for Cogent csb637 + Patch by Anders Larsen, 29 Apr 2005 + +* Fix dm9161.c initialization + Patch by Anders Larsen, 29 Apr 2005 + +* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005 + (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5) + +* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200 + Patch by Anders Larsen, 29 Apr 2005 + +* Fix device partition intialization for SystemACE disks. + Patch by Stephen Williams, 28 Apr 2005 + +* Added support for KwikByte KB920x boards (based on AT91RM9200) + Patch by Matt ?? , 27 Apr 2005 + +* Add support for S29GL064M-R3 flash chip on xsengine board + Patch by Kurt Stremerch, 18 Apr 2005 + +* E500 update: repoint IVPR to RAM when code is relocated + Patch by Kylo Ginsberg, 13 Apr 2005 + +* Fix loop end test in lib_generic/string.c:strswab() + Patch by Andrew Dyer, October 10, 2005 + Signed-off-by: Andrew Dyer + +* Cleanup + +* Update ARM Integrator boards: + Correct addessing errors in platform files. + Split off common core module data from Integrator header files to + include/armcoremodule.h. + Patch by Peter Pearse, 04 Oct 2005 + +* Make sure only supported compiler options are used + Import "cc-option" shell function from kernel and + use it to get the correct ARM GCC options for individual CPUs + Patch by Peter Pearse, 30 Jun 2005 + +* Fix 440GR to print correct cpu revision + Patch by Stefan Roese, 04 Oct 2005 + +* Change board message on AMCC Yosemite & Yellowstone to common style + Patch by Stefan Roese, 03 Oct 2005 + +* Fix compiler warning + +* Fix FEC PHY addresses for TQM85xx boards + +* Fix uninitialized variable problem in hush shell + Patch by Lars Rostock, 26 Sep 2005 + +* Undo change of f6e20fc6ca... to include/configs/trab.h + (Must have been an accident?) + +* Add support for AT91RM9200 OHCI Controller. + Patch by Eric Benard, 07 Apr 2005 + +* Update ARM mach-types.h + Patch by Eric Benard, 07 Apr 2005 + +* Add support for MP2USB board. + Patch by Eric Benard, 07 Apr 2005 + +* Add board support for armadillo HT1070 + Patch by Rowel Atienza, 06 Apr 2005 + +* Second Ethernet address enabled for MPC885ADS and MPC8272ADS. + Patch by Vitaly Bordug, 30 Mar 2005 + +* Add iopset command on mpc8xx + Patch by Daniel Eisenhut, 25 Mar 2005 + +* Add support for MII in eepro100 driver. + Patch by Gleb Natapov, 21 Mar 2005 + +* Fixes to the Lubbock (PXA 25x) support: + - Resolve the FIXME with respect to saving the u-boot environment. + - Make the default load address land in real memory. + - Fix lan91c96 SMC_{in,out}{b,w,l}() macros + Patch by David Brownell, 10 Mar 2005 + +* Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board + Patch by Marc Leeman, 04 Mar 2005 + +* OMAP242x H4 board update + - fix for ES2 differences. + - switch to using the cfi_flash driver. + - fix SRAM build address. + - fix for GP device operation. + - unlock SRAM for GP devices. + - display more device information. + - fix potential deadlock in omap24xx_i2c driver. + - fix DLL load values to match dpllout*1 operation. + - fix 2nd chip select init for combo DDR device. + - add support for CFI Intel 28F256L18 on H4 board. + Patch by Richard Woodruff, 03 Mar 2005 + +* Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h + Patch by Steven Scholz, 02 Mar 2005 + +* Fix typo in eth.c + Patch by Ara Avanesyan, 24 Feb 2005 + +* Remove unneeded #include + Patch by Ladislav Michl, 22 Feb 2005 + +* Add cramfs support for m68k + Patch by Zachary Landau, 21 Feb 2005 + +* Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs + Patch by Jeff Angielski, 21 Feb 2005 + +* Fix au1x00_serial baud rate calculation: + remove hardcoded cpu clock divisor and use register instead; + round up instead of truncate + Patch by Andrew Dyer, 15 Feb 2005 + +* Add Xilinx Spartan3 family FPGA support + Patch by Kurt Stremerch, 14 Feb 2005 + +* Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET + Patch by Zachary Landau, 11 Feb 2005 + +* Fix VOH405 Support + Patch by Matthias Fuchs, 25 Sep 2005 + +* Added support for PCI bridge on MPC8272ADS + Patch by Vitaly Bordug, Feb 09 2005 + +* Update multicore CM9XX support for Integrator AP to allow booting from flash + Patch by Jean-Paul Saman, 8 Feb 2005 + +* Fix strswab() to reliably find end of string + Patch by Andrew Dyer, 08 Feb 2005 + +* Fix typos in include/ppc440.h + Patch by Andrew E Mileski, 04 Feb 2005 + +* Add Vibren (was Accelent) PXA255 IDP Support + Patch by Cliff Brake, 04 Feb 2005 + +* Fix tools/bmp_logo.c using incorrect offset to pixel data + Patch by Andrew Dyer, 31 Jan 2005 + +* Add ARM946E cpu and core module targets; remap memory to 0x00000000 + Patch by Peter Pearse, 2 Feb 2005 + +* Fix error handling in tools/env/fw_env.c + Patch by Ara Avanesyan, 01 Feb 2005 + +* Fix MGT5100 PSC baudrate calculation + Patch by Sebastian Schau, 27 Jan 2005 + +* OMAP242x fix for GP device booting + - Add SRAM unlock for GP devices. + - Change DDR DLL unlock value to allow DPLLout*1 operation. + Patches by Richard Woodruff, 21 Jan 2005: + +* Add support for AMD's Pb1x00 eval board; + add MII routines to the au1x00 ethernet driver; + add USB ohci driver (work in progress) + Patch by Thomas Sailer, 20 Jan 2005 + +* Update omap5912osk board + Use drivers/cfi_flash.c instead of private flash driver; + Remove hardcoded personalized settings from omap5912osk.h; + Fix spacing with (RO) marks in 'flinfo' output. + Patch by Michael Bendzick, 14 Jan 2005 + +* Fix warnings for PCI code on ixp + Patch by Joe , 13 Jan 2005 + +* virtex2 fix for bogus download error messages + The virtex2 FPGA download code watches for init going active during + a download of config data as an error condition. init also goes + active after a configuration is finished in concert with the done + signal. So far, the code does not check for done active until all + of the configuration data is sent. If configuration data has a few + extra pad bytes at the end, this would cause an error message even + though the download had suceeded. + NOTE: virtex2 slave serial and spartan2 versions may still have the + same problem. + Patch by Andrew Dyer, 12 Jan 2005 + +* Optimize flash_make_cmd in drivers/cfi_flash.c for little endian + Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode" + message when probing for nonexistent flash in little endian mode. + As a side effect more efficient and smaller code is generated, + which is always a Good Thing (TM). + Patch by Ladislav Michl, 24 Sep 2005 + +* Update for TFTP using a fixed UDP port + Use the approved environment variable names. Added "tftpdstp" to + allow ports other than 69 per Tolunay Orkun's recommendation. + Patch by Jerry Van Baren, 12 Jan 2005 + +* Allow to force TFTP to use a fixed UDP port + (Add a configuration option CONFIG_TFTP_PORT and optional env + variable tftpport) + Patch by Jerry Van Baren, 10 Jan 2005 + +* Fix ethernet timeouts on dbau1550 and other au1x00 systems + Patch by Leif Lindholm, 29 Dec 2004 + +* Cleanup: fix broken builds + +* Fix PHY address argument passing with mii info command + Patch by Andrew Dyer, 28 Dec 2004 + +* Cleanup (PPC4xx is AMCC now) + +* esd CPCI2DP board added + Patch by Matthias Fuchs, 22 Sep 2005 + +* esd PMC405 board updated + Patch by Matthias Fuchs, 22 Sep 2005 + +* Add SM501 support to HH405 board. + Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP). + Add support for eeprom write-enable (CFG_EEPROM_WREN). + Patch by Stefan Roese, 22 Sep 2005 + +* Fix autonegotiation in tsec ethernet driver + Patch by Stefan Roese, 21 Sep 2005 + +* Fix bug in auto_update (trab board) + Patch by Martin Krause, 16 Sep 2005 + +* Fix computation of framebuffer palette for 8bpp LCD bitmaps + Patch by Francesco Mandracci, 16 Sep 2005 + +* Update configuration for INKA4x0 board + +* Update configuration for PM854 board + Based on patch by R. Loeffl, 20 Jul 2005 + +* Add PCI support to TQM8540 and TQM8560 boards + Patch by Stefan Roese, 15 Sep 2005 + +* Update AMCC Yosemite to get a consistent setup for all AMCC eval + boards (baudrate, environment...). Flash driver fixed. + Patch by Stefan Roese, 15 Sep 2005 + +* Fix problem in 440GP ethernet driver (ebony). Add support for 2nd + ethernet port on ebony. + Patch by Stefan Roese, 7 Sep 2005 + +* Added support for mtddevnum and mtddevname variables (mtdparts command) + +* Change default console baud rate for stxxtc board + +* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT). + Patch by Stefan Roese, 31 Aug 2005 + +* Fix default command set (don't include CFG_CMD_DISPLAY command) + Patch by Pantelis Antoniou, 02 Sep 2005 + +* Cleanup + +* Enable SM712 driver support for HMI1001 board. + +* Fix problems with ld version 2.16 (dot outside sections problem) + Pointed out by Gerhard Jaeger, 31 Aug 2005; + cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html + +* Prepare U-Boot for gcc-4.x: fix global data pointer initialization + +* Adjust CS3 timings on HMI1001 board for dot matrix display under Linux + +* Add keyboard and dot matrix display support for HMI1001 board. + +* Prepare U-Boot for gcc-4.x + +* Fixed Bamboo port to enable running without DDR-DIMM + (Bamboo has also 64MB onboard DDR) + Patch by Stefan Roese, 24 Aug 2005 + +* Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c + now handling all 4xx cpu's + Patch by Stefan Roese, 16 Aug 2005 + +* Fix make dependencies for at91rm9200 and ks8695 cpus + Patch by Steven Scholz, 23 Aug 2005 + +* Add JFFS2 support for TQM5200 board + +* Add esd cpci5200 and pf5200 boards + Patch by Reinhard Arlt, 22 Aug 2005 + +* Fix sysclock for TQM8540 and TQM8560 boards + Patch by Martin Krause, 25 Jul 2005 + +* Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2 + Patch by Martin Krause, 08 Jun 2005 + +* Add new board specific commands for TQM5200/STK52XX + - Sound commands (beep, wav, sound) + - Test commands (led, can, backlight, rs232) + Patch by Martin Krause, 02 May 2005 + +* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz + because of a bug in the AT91RM9200 CPU PLL + Patch by Martin Krause, 22 Apr 2005 + +* Add automatic HW detection for another CMC_PU2 variant + Patch by Martin Krause, 20 Apr 2005 + +* Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration + Patch by Martin Krause, 19 Apr 2005 + +* Fix initialization problem on TQM5200 without SM501 + Patch by Martin Krause, 08 Apr 2005 + +* Add RTC support for STK52XX.200 + Patch by Martin Krause, 07 Apr 2005 + +* Add support for IFM o2dnt board + +* Enable PCI on hmi1001 board + +* Fix return values of the jffs2 commands ls/fsload/fsinfo, + so we can use them to, e.g., check the existence of a file with + "if ls foo; then this; else that; fi" in the hush shell + Patch by Andreas Engel, 16 August 2005 + +* Coding style cleanup + +* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board. + Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005 + +* Check return value of malloc in 440gx_enet.c + Patch by Travis B. Sawyer, 18 Jul 2005 + +* Add Sandburst Metrobox and Sandburst Karef board support packages. + Second serial port on 440GX now defined as a system device. + Add 'Short Etch' code for Cicada PHY within 440gx_enet.c + Patch by Travis B. Sawyer, 12 Jul 2005 + +====================================================================== +Changes for U-Boot 1.1.3: +====================================================================== + +* Minor code cleanup + +* Add forgotten new fils from latest VoiceBlue update + +* Make bootretry feature work with hush shell. + Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too. + Patch by Andreas Engel, 19 Jul 2005 + +* Update Hymod Board Database PHP code in "tools" directory + Patch by Murray Jensen, 01 Jul 2005 + +* Make "tr" command use POSIX compliant; export HOSTOS make variable + Patch by Murray Jensen, 30 Jun 2005 + +* Fix Murray Jensen's mail address. + Patch by Murray Jensen, 30 Jun 2005 + +* Preserve PHY_BMCR during a soft reset. + Patch by Carl Riechers, 24 Jun 2005 + +* VoiceBlue update: eeprom tool can also store firmware version now. + eeprom.bin is runable by jumping at load address. + Patch by Ladislav Michl, 23 May 2005 + +* Move the AT91RM9200DK to the ARM Systems list. + Patch by Anders Larsen, 26 Apr 2005 + +* Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3 + Patch by Anders Larsen, 26 Apr 2005 + +* measure_gclk() is needed when DEBUG is enabled + Patch by Bryan O'Donoghue, 25 Apr 2005 + +* Add UPD-Checksum code, fix problem in net.c (return instead of break) + Patch by Reinhard Arlt, 12 Aug 2005 + +* esd PCI405 board updated + Patch by Matthias Fuchs, 28 Jul 2005 + +* esd WUH405 and DU405 board updated + Patch by Matthias Fuchs, 27 Jul 2005 + +* Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I) + Patch by Matthias Fuchs, 4 May 2005 + +* Update AMCC Yosemite to get a consistent setup for all AMCC eval + boards (baudrate, environment...). Flash driver fixed. + Patch by Stefan Roese, 11 Aug 2005 + +* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port + Patch by Stefan Roese, 11 Aug 2005 + +* Add NAND FLASH support for AMCC Bamboo 440EP eval board + Patch by Stefan Roese, 11 Aug 2005 + +* Add configuration for IFM AEV FIFO board. + Minor coding style cleanup. + +* Add configuration for IFM SPI eval board + +* Fix CompactFlash problem on HMI1001 board + +* Make new "mtdparts" code build with older compilers + Patch by Andrea Scian, 09 Aug 2005 + +* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to + CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design + with the 405 defines and the linux kernel defines. + Patch by Stefan Roese, 08 Aug 2005 + +* Fix compiler warnings with older GCC versions + +* Add common (with Linux) MTD partition scheme and "mtdparts" command + + Old, obsolete and duplicated code was cleaned up and replace by the + new partitioning method. There are two possible approaches now: + + The first one is to define a single, static partition: + + #undef CONFIG_JFFS2_CMDLINE + #define CONFIG_JFFS2_DEV "nor0" + #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */ + #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */ + #define CONFIG_JFFS2_PART_OFFSET 0x00000000 + + The second method uses the mtdparts command line option and dynamic + partitioning: + + /* mtdparts command line support */ + #define CONFIG_JFFS2_CMDLINE + #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" + #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" + + Command line of course produces bigger images, and may be inappropriate + for some targets, so by default it's off. + +* Fix build problems for PM856 Board + +* Fix sign extension bug in 'fpga loadb' command; + make 'fpga loadb' always print the file header info + Patch by Andrew Dyer, 11 Jan 2005 + +* Fix errors that occur when accessing SystemACE CF + Patch by Jeff Angielski, 09 Jan 2005 + +* Document switching between U-Boot and PlanetCore on RPXlite + by Sam Song, 24 Dec 2004 + +* Fix PowerQUICC II mask detection. + Patch by Eugene Surovegin, 20 Dec 2004 + +* Add support for Altera NIOS DK1C20 board + Patch by Shlomo Kut, 13 Dec 2004 + +* Add support for ep8248 board + Patch by Yuli Barcohen, 12 Dec 2004 + + Minor code cleanup. + +* Fix baudrate setting for KGDB on MPC8260 + Patch by HoJin, 11 Dec 2004 + +* Fix 'mii help' text formatting + Patch by Cory Tusar, 10 Dec 2004 + +* Fix return code of NFS command + Patch by Hiroshi Ito, 11 Dec 2004 + +* Fix typo + +* Fix compiler warnings in cpu/ppc4xx/usbdev.c + Patch by Steven Blakeslee, 04 Aug 2005 + +* Add support for AMCC Bamboo PPC440EP eval board + Patch by Stefan Roese, 04 Aug 2005 + +* Patch by Jon Loeliger + Fix style issues primarily in 85xx and 83xx boards. + - C++ comments + - Trailing white space + - Indentation not by TAB + - Excessive amount of empty lines + - Trailing empty lines + +* Patch by Ron Alder, 11 Jul 2005 + Add Xianghua Xiao and Lunsheng Wang's support for the + GDA MPC8540 EVAL board. + +* Patch by Eran Liberty + Add support for the Freescale MPC8349ADS board. + +* Patch by Jon Loeliger, 25 Jul 2005 + Move the TSEC driver out of cpu/mpc85xx as it will be shared + by the upcoming mpc83xx family as well. + +* Patch by Jon Loeliger, 05 May 2005 + Implemented support for MPC8548CDS board. + Added DDR II support based on SPD values for MPC85xx boards. + This roll-up patch also includes bugfies for the previously + published patches: + DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O + +* Patch by Jon Loeliger, 10 Feb 2005 + Add config option CONFIG_HAS_FEC calling out 8540 FEC features. + +* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005 + For MPC85xxCDS: + Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow + for faster flash parts. + Add documentation for BR/OR for FLASH. + +* Patch by Jon Loeliger 08 Feb 2005 + Determine L2 Cache size dynamically on 85XX boards. + +* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005 + - Convert the CPM2 based functionality to use new CONFIG_CPM2 + option rather than a myriad of CONFIG_MPC8560-like variants. + Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560. + Eliminates the CONFIG_MPC8560 option entirely. Distributes the + new CONFIG_CPM2 option to each 8260 board. + +* Add support for MicroSys PM856 board + Patch by Josef Wagner, 03 Aug 2005 + +* Minor fixes to PM854 board + Patch by Josef Wagner, 03 Aug 2005 + +* Adjust configuration of XENIAX board + (chip select and GPIO required for USB operation) + +* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be + routed to the Watchdog handler + Patch by Eugene Surovegin, 18 Jun 2005 + +* (re)enabled scsi commands do_scsi() and do_scsiboot() + Patch by Denis Peter, 06 Dec 2004 + +* Fix endianess problem in TFTP / NFS default filenames + Patch by Hiroshi Ito, 06 Dec 2004 + +* Ignore broadcast status bit in received frames in 8260 FCC ethernet + loopback test code + Patch by Murray Jensen, 18 Jul 2005 + +* Fix typo in mkconfig script (used == instead of =) + Patch by Murray Jensen, 18 Jul 2005 + +* Cleanup build problems on 64 bit build hosts + +* Update MAINTAINERS file + +* Patch by Stefan Roese, 01 Aug 2005: + - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea + (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup" + for details. + - Sycamore (PPC405GPr) eval board added (Walnut port is extended + to run on both 405GP and 405GPr eval boards). + +* Patch by Steven Blakeslee, 27 Jul 2005: + - Add support for AMCC PPC440EP/GR. + - Add support for AMCC Yosemite PPC440EP eval board. + - Add support for AMCC Yellowstone PPC440GR eval board. + +* Minor fixes for PPChameleon Board: + - fix alignment of NAND size + - make code do what the comment says + +* Implement h/w sector protection status synchronization at boot. + The code is provided for, and was tested on, the Yukon/Alaska + and PM520 boards only. + + A bug in flash_real_protect() for the Yukon board was fixed by + adding a function that tells if two banks are on one flash chip. + +* Fix sysmon POST problem: check I2C error codes + This fixes a problem of displaying bogus voltages when the voltages + are so low that the I2C devices start failing while the rest of the + system keeps running. + +* Patch by Cedric Vincent, 6 Jul 2005: + Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c" + +* Patch by Jon Loeliger, 20 Jul 2005: + Add missing PCI IO port definitions. + +* Add CompactFlash support for HMI1001 board. + +* Adjust printed board ID for LWMON board. + +* Fix low-level OHCI transfers for ARM920t and MPC5xxx + +* Add new argument format for flash commands to allow for usage like + "erase $(addr) +$(filesize)", i. e. a size argument can be used and + U-Boot will automaticially find the end of the corresponding sector. + +* Patch by Stefan Roese, 5 Jul 2005: + Update uc100 board PHY setup + +* Patch by Stefan Roese, 1 Jul 2005: + Fix PHY address for CATcenter board (now correct!) + +* Patch by Stefan Roese, 30 Jun 2005: + Fix PHY addresses for PPChameleon and CATcenter boards + Change MAINTAINER for most esd boards + +* Patch by Detlev Zundel, 30 Jun 2005: + Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code + +* Fix baudrate calculation problem on MPC5200 systems + +* Add EEPROM and RTC support for HMI1001 board + +* Patch by Detlev Zundel, 20 Jun 2005: + Fix initialization of low active GPIO pins on inka4x0 board + +* Enable redundant environment, disable HW flash protection of + HMI1001 board + +* Patch by Travis Sawyer, 10 Jun 2005: + Initialize allocated dev and private hw structures + after their respective allocation in 440gx_enet.c + +* Patch by Steven Scholz, 10 Jun 2005: + Fix byteorder problems with second argument of "bootm" with + standalone images; + +* Add support for HMI1001 board + +* Disable "date" and "sntp" commands on TQM866M + +* Fix watchdog reset problems on LWMON board + +* Patch by Juergen Selent, 17 May 2005: + Add support for Funkwerk VoVPN gateway module. + +* Cleanup debug code for MPC8220 FEC driver + +* Extend burst mode RAM test program to take a loop count + (0 = infinite) + +* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on + those boards that use it. + +* Patches by Greg Ungerer, 19 May 2005: + - add support for the KS8695P (ARM 922 based) CPU + - add support for the OpenGear CM4008, CM4116 and CM4148 boards + +* Patch by Steven Scholz, 19 May 2005: + Add support for CONFIG_SERIAL_TAG on ARM boards + +* Add PCI support for Sorcery board. + Code cleanup (especially Sorcery / Alaska / Yukon serial driver). + +* Fix compile problems caused by new burst mode SDRAM test; + make port pins to trigger logic analyzer configurable + +* Fix timer handling on MPC85xx systems + +* Fix debug code in omap5912osk flash driver + +* Add support for MPC8247 based "IDS8247" board. + +* Add support for 2 x TSEC interfaces on the TQM8540 board. + +* On LWMON we must use the watchdog to reset the board as the CPU + genereated HRESET pulse is too short to reset the external + circuitry. + +* Add test tool to exercise SDRAM accesses in burst mode + (as standalone program, MPC8xx/PowerPC only) + +* Increase CFG_MONITOR_LEN for Rattler board to match actual code + size. + +* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of + March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI + added to support LZO and LZARI compression modes (undefined by + default). + +* Fix problem with symbolic links in JFFS2 code. + +* Use linker ASSERT statement to prevent undetected overlapping of + sections on PPChameleon board; other boards might use this, too. + +* Patch by Stefan Roese, 03 May 2005: + Update for P3G4 + Fix problems in cmd_universe.c + +* Patch by Matthias Fuchs, 03 May 2005: + Added missing variable declaration in cmd_nand.c + Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram + +* Fix INKA4x0: use CS1 as gpio_wkup_6 output + +* Fix bug in the SDRAM initialization code for canmb, IceCube and + PM520 boards. + Fix PHY address for canmb board. + +* Cleanup serial console baudrate calculation on AT91RM9200; + get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition + +* Patch by Matthias Fuchs, 18 Apr 2005: + Make PCI target address spaces on PMC405 and CPCI405 boards + configurable via environment variables + +* Auto-size RAM on canmb board. + +* Add support for canmb board + +* Patch by Stefan Roese, 13 Apr 2005: + Update for esd apc405 + +* Fixes for TQM8560 board: + - fix clock rates + - remove debug messages + - fix flash sector protection + +* Patch by Steven Scholz, 07 Apr 2005: + Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C + +* Patches by Steven Scholz, 07 Apr 2005: + Fix compiler warning in altera.c + Fix warning in cpu/arm920t/at91rm9200/i2c.c + +* Patch by Ladislav Michl, 06 Apr 2005: + Fix voiceblue configuration. + +* Patch by Stefan Roese, 06 Apr 2005: + Updates for OCOTEA board: + - Changed U-Boot size from 512kByte to 256kByte + - Fixed flash driver to support boot from soldered user flash + - Added README for switch from PIBS firmware to U-Boot + +* Patch by Travis Sawyer, 05 Apr 2005: + - Change timer frequency for ppc 440 from 10 ms to 1 ms. + Problem found by Andrew Wozniak. + +* Patch by Steven Scholz, 06 Apr 2005: + - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200 + - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200 + +* Patches by Robert Whaley, 29 Nov 2004: + - update the pxa-regs.h file for PXA27x chips + - add PXA27x based ADSVIX board + - add support for MMC on PXA27x processors + +* Patch by Andrew E. Mileski, 28 Nov 2004: + Fix PPC4xx SPD SDRAM detection bug + +* Patch by Hiroshi Ito, 26 Nov 2004: + Fix logic of "test -z" and "test -n" commands + +* Patch by Ladislav Michl, 05 Apr 2005: + Add support for VoiceBlue board. + +* Patch by Ladislav Michl, 05 Apr 2005: + Fix netboot_common() prototypes. + +* Patch by Steven Scholz, 05 Apr 2005: + Use i.MX watchdog timer for reset_cpu() + +* Patch by Steven Scholz, 05 Apr 2005: + Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific + subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/ + (now in interupts.c) + +* Add support for MPC8220 based "sorcery" board. + +* Add support for TQM8560 board. + +* Add FEC support for TQM8540 board. + Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC + +* Patch by Martin Krause, 04 Apr 2005: + Update default configuration for CMC_PU2 board. + +* Patch by Steven Scholz, 04 Apr 2005: + - remove all references to CONFIG_INIT_CRITICAL for ARM based boards + - introduce two new configuration options instead: + CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT + +* Patch by Steven Scholz, 04 Apr 2005: + Make sure that MDIO clock does not exceed 2.5 MHz on AT91 + +* Fix timer code for ARM systems: make sure that udelay() does not + reset timers so it's save to use udelay() in timeout code. + +* Patch by Mathias Küster, 23 Nov 2004: + add udelay support for the mcf5282 cpu + +* Patch by Tolunay Orkun, 16 November 2004: + fix incorrect onboard Xilinx CPLD base address + +* Patch by Jerry Van Baren, 08 Nov 2004: + - Add low-boot option for MPC8260ADS board (if lowboot is selected, + the jumper for the HRCW source should select flash. If lowboot is + not selected, the jumper for the HRCW source should select the + BCSR. + - change default load base address to 0x00400000 + +* Patch by Yuli Barcohen, 08 Nov 2004: + Add support for Analogue & Micro Rattler boards. + Tested on Rattler8248. + +* Patch by Andre Renaud, 08 Nov 2004: + Fix watchdog support in common/lcd.c + +* Patch by Marc Leeman, 05 Nov 2003: + Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU + bug only affects the XPC8245 processors + +* Patches by Josef Wagner, 29 Oct 2004: + - Add support for MicroSys CPU87 board + - Add support for MicroSys PM854 board + +* Patch by Jian Zhang, 02 Nov 2004: + Add 16-bit NAND support + +* Patch by Scott McNutt, 01 Nov 2004: + Add missing NIOS/NIOS2 support for "iminfo" command + +* Patch by Detlev Zundel, 29 Oct 2004: + Add missing NIOS/NIOS2 support for "mkimage" tool. + +* Patch by David Adair, 27 Oct 2004: + Add missing 440GX SDRAM Controller reset + +* Patch by Steven Scholz, 25 Oct 2004: + Declare reset_cpu() in include/common.h instead locally + +* Patch by Yusdi Santoso, 22 Oct 2004: + - Add support for HIDDEN_DRAGON board + - fix endianess problem in driver/rtl1839.c + +* Patch by Allen Curtis, 21 Oct 2004: + support multiple serial ports + +* Patch by Richard Klingler, 03 Apr 2005: + Add call to eth_halt() in net/net.c when called functions fail + after eth_init() has been called. + +* Patch by Sam Song, 3 April 2005: + - Update README.Netconsole + - Update README + +* Prepare for SoC rework of ARM code: + - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL + - rename memsetup into lowlevel_init (function name and source files) + Patch by Steven Scholz, 03 Apr 2005: + - create SoC specific directories include/asm-arm/arch-imx and + include/asm-arm/arch-s3c24x0 + +* Fix problems with SNTP support; + enable SNTP support in some boards. + +* Patches by Martin Krause, 01 Apr 2005: + - Fix flash erase timeout on CMC_PU2 + - Add automatic HW detection for CMC_PU2 and CMC_BASIC + +* Patch by Steven Scholz, 13 March 2005: + fix cache enabling for AT91RM9200 + +* Patch by Masami Komiya, 30 Mar 2005: + add SNTP support and expand time server and time offset fields of + DHCP support. See doc/README.SNTP + +* Patch by Steven Scholz, 13 Dec 2004: + Fix bug in at91rm920 ethernet driver + +* Patch by Steven Scholz, 13 Dec 2004: + Remove duplicated code by merging memsetup.S files for + at91rm9200 boards into one cpu/at91rm9200/lowlevel.S + +* Patch by Detlev Zundel, 31 Mar 2005: + Cleanup duplicate definition of overwrite_console() + +* Update TQM5200 configuration; + prepare for Rev. 200 starter kit boards + +* Patch by Scott McNutt, 21 Oct 2004: + Add support for Nios-II EPCS Controller core. + +* Patch by Scott McNutt, 20 Oct 2004: + Nios-II cleanups: + - Add sysid command (Nios-II only). + - Locate default exception trampoline at proper offset. + - Implement I/O routines (readb, writeb, etc) + - Implement do_bootm_linux + +* Patches by Martin Krause, 22 Mar 2005: + - use TQM5200_auto as MAKEALL target for TQM5200 systems + - add support for SM501 graphics controller + - add support for graphic console on TQM5200 + - add support for TQM5200 Rev 200 + - cleanup, fix typo in include/configs/TQM5200.h + +* Patch by Manfred Baral, 17 Mar 2005: + Fix typo + +* Fix RTC configuration for PPChameleon board + +* Cleanup, fix typo in include/configs/TQM5200.h + +* Patch by Stefan Roese, 16 Mar 2005: + Update for esd auto_update and hh405 board + +* Adapt for U-Boot image size (new features enabled) on TQM5200 + +* Update code for TQM8540 board (and 85xx in general): + - Change the name of the Ethernet driver: MOTO ENET -> ENET + - Reformat boot messages + - Enable redundant environment + - Replace the -O2 optimization flag with -mno-string + +* Patch by David Brownell, 10 Mar 2005: + Restore copyright statements in OHCI drivers. + +* Add support for TQM8540 board + +* Patch by Detlev Zundel, 14 Mar 2005: + NC650: changed NAND flash addressing to using UPMB + +* Patch by Stefan Roese, 14 Mar 2005: + Update for esd voh405 fpga image + +* INKA4x0: Allow initialization of LCD backlight dimming from + "brightness" environment variable. + +* Add port initialization for digital I/O on INKA4x0 + +* Patch by Stefan Roese, 01 Mar 2005: + Update for esd boards dp405 and hub405 + +* Fix get_partition_info() parameter error in all other calls + (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c). + +* Enable USB and IDE support for INKA4x0 board + +* Patch by Andrew Dyer, 28 Feb 2005: + fix ext2load passing an incorrect pointer to get_partition_info() + resulting in load failure for devices other than 0 + +* Add support for SRAM and 2 x Quad UARTs on INKA4x0 board + +* Cleanup USB and partition defines + +* Add support for ext2 filesystems and image timestamps to TQM5200 board + +* Add reset code for Coral-P on INKA4x0 board + +* Patch by Martin Krause, 28 Jun 2004: + Update for TRAB board. + +* Fix some missing "volatile"s in MPC5xxx FEC driver + +* Fix cirrus voltage detection (for CPC45) + +* Fix byteorder problem in usbboot and scsiboot commands. + +* Patch by Cajus Hahn, 04 Feb 2005: + - don't insist on leading '/' for filename in ext2load + - set default partition to useful value (1) in ext2load + +* Patch by Andrew Dyer, 08 Jan 2005: + fix wrong return codes in ext2 code + +* Removed '--no-warn-mismatch' option from Makefile. This option + makes 'ld' to overlook binary objects compatibility. + +* Moved $(PLATFORM_LIBS) from the library group (--start-group ... + --end-group) outside of the group. This will make 'ld' to do + _multiple_ search in the library group when resolving symbol + references and do only a _single_ seach in libgcc.a after the group + search. + +* Fix stability problems on CPC45 board again. + +* Make image detection for diskboot / usbboot / scsiboot more robust + (also check header checksum) + +* Update CPC45 board configuration. + +* Add USB and PCI support for INKA4x0 board + +* Fix IDE stability problems on CPC45 board (needs 2 x EIEIO). + +* Code cleanup + +* Patch by Robin Getz, 13 Oct 2004: + Add standalone application to change SMC91C111 MAC addresses, + see examples/README.smc91111_eeprom + +* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004: + Fix Flash support for ARM Integrator CP. + +* Patch by Richard Woodruff, 10 Jan 2005: + Update support for OMAP2420 (ARM11) and H4 board: + o clean up and add new types to H4 memory probe code. + o fix to work with internal boot. + o added PRCM config III operation. + o fix marginal flash timings. + o add revison ATAG usage. + o enable voltage scaling at power chip. + o fix compile error for i2c. + +* Fix network problem (error when receiving multiple ARP packets) + +* Patch by Daniel Poirot, 12 Oct 2004: + Add support for Wind River sbc405 board + +* Patch by Rainer Brestan, 12 Oct 2004: + Make examples/Makefile more robust + +* Patch by Sam Song, 11 October 2004: + - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board + - Adjust CPU:BUS frequency ratio 1:1 when core frequency + less than 50MHz + +* Patch by Sam Song, 10 Oct 2004: + Fix a parameter error in run_command() in main.c + +* Patch by Richard Woodruff, 01 Oct 2004: + add support for the TI OMAP2420 processor and its H4 reference + board + +* Patch by Christian Pellegrin, 24 Sep 2004: + Added support for NE2000 compatible (DP8390, DP83902) NICs. + +* Patch by Leif Lindholm, 23 Sep 2004: + add support for the AMD db1550 board + +* Patch by Travis Sawyer, 15 Sep 2004: + Add CONFIG_SERIAL_MULTI support for ppc4xx, + update README.serial_multi + +* Patches by David Snowdon, 07 Sep 2004: + - add u-boot.hex target in the top level Makefile + - add support for the UNSW/NICTA PLEB 2 board (pleb2) + - use -mtune=xscale and -march=armv5 options for PXA + +* Patch by Florian Schlote, 08 Sep 2004: + Add support for SenTec-COBRA5272-board (Coldfire). + +* Patch by Gleb Natapov, 07 Sep 2004: + mpc824x: set PCI latency timer to a sane value + (is 0 after reset). + +* Patch by Kurt Stremerch, 03 Sep 2004: + Add bitstream configuration option for fpga command (Xilinx only). + +* Patch by Kurt Stremerch, 03 Sep 2004: + Add Xilinx Spartan2E family FPGA support + +* Patch by Jeff Angielski, 02 Sep 2004: + Add Added support for H2 revision of the EP8260 board. + Fixed formatting for some of the EP8260 related source files. + +* Patch by Jon Loeliger, 02 Sep 2004: + Reset monitor size back to 256 so environment can be written + to flash on MPC85xx ADS and CDS releases. + +* Patch by Paolo Broggini, 02 Sep 2004: + Make BSS clearing on ARM systems more robust + +* Patch by Yue Hu and Joe, 01 Sep 2004: + - add PCI support for ixp425; + - add EEPRO100 suppor tfor ixdp425 board. + +* Fix problem with protected sector detection in driver/cfi_flash.c + +====================================================================== +Changes for U-Boot 1.1.2: +====================================================================== + +* Code cleanup, mostly for GCC-3.3.x + +* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to + pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for + additional ethernet addresses. + +* Cleanup drivers/i82365.c - avoid duplication of code + +* Fix bogus "cannot span across banks" flash error message + +* Code cleanup + +* Add support for CompactFlash for the CPC45 Board. + +* Fix problems with CMC_PU2 flash driver. + +* Cleanup: + - avoid trigraph warning in fs/ext2/ext2fs.c + - rename UC100 -> uc100 + +* Add support for UC100 board + +* Patch by Stefan Roese, 16 Dez 2004: + - ext2fs support added + - Tundra universe support added + - Coldfire MCF5249 support added (no preloader needed!) + - MCF5249 board TASREG added + - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405, + VOM405, WUH405 + - some esd boards updated + - memory commands "mdc" and "mwc" added for cyclic read/write + (CONFIG_MX_CYCLIC, see README for further description) + +* Add support for INKA4X0 board + +* Patch by Steven Scholz, 12 Dec 2004: + Fix typo in AT91 memory setup. + +* Patch by Martin Krause, 27 Oct 2004: + - add support for "STK52xx" board (including PS/2 multiplexer) + - add hardware detection for TQM5200 + +* Clean up CMC PU2 flash driver + +* Update MAINTAINERS file + +* Fix bug in MPC823 LCD driver + +* Fix udelay() on AT91RM9200 for delays < 1 ms. + +* Enable long help on CMC PU2 board; + fix reset issue; + increase CPU speed from 179 to 207 MHz. + +* Fix smc91111 ethernet driver for Xaeniax board (need to handle + unaligned tail part specially). + +* Update for AT91RM9200DK and CMC_PU2 boards: + - Enable booting directly from flash + - fix CMC_PU2 flash driver + +* Fix mkimage usage message + +* Map SRAM on NC650 board + +* Work around for Ethernet problems on Xaeniax board + +* Patch by TsiChung Liew, 23 Sep 2004: + - add support for MPC8220 CPU + - Add support for Alaska and Yukon boards + +* Fix configuration for ERIC board (needs more room) + +* Adjust MIPS compiler options at run-time depending on tools version + ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new, + "-mcpu=4kc" for old tools) + +* Add passing of the command line and memory size information to the + kernel on xaeniax board. + +* Enable NAND flash support for NC650 board. + +* Patch by Thomas Lange 07 Oct 2004: + Updated README for DBAu1x00 boards to match current status + +* Patch by Philippe Robin, 28 Sept 2004: + Fix Flash support for Versatile. + +* Patch by Roger Blofeld, 16 Sep 2004: + Fix timeout for DHCP command retry + +* Patch by Pantelis Antoniou, 14 Sep 2004: + Fix early serial hang when CONFIG_SERIAL_MULTI is defined. + +* Patch by Pantelis Antoniou, 14 Sep 2004: + Kick watchdog when bz-decompressing + +* Fix CFG_HZ problems on AT91RM9200 systems + [Remember: CFG_HZ should be 1000 on ALL systems!] + +* Patch by Gridish Shlomi, 30 Aug 2004: + - Add support to revA version of PQ27 and PQ27E. + - Reverted MPC8260ADS baudrate back to original 115200 + +* Patch by Hojin, 17 Sep 2004: + Fix typo in cfi_flash.c + +* Patch by Mark Jonas, 09 September 2004: + mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong + error message + +* Patch by Mark Jonas, 31 August 2004: + Added option CFG_XLB_PIPELINING to enable XLB pipelining. This + improves FTP performance for MPC5200 systems. Enabled for IceCube + by default. + +* Patch by Michael Bendzick, 30 Aug 2004: + - Improve platform.S code for omap1510inn that detects whether code + is running from SDRAM or not. Patch allows SDRAM to be configured + if code is running out of SRAM at 0x20000000. + +* Patch by Frederick Klatt, 30 Aug 2004: + Add support for the Wind River SBC8540/SBC8560 boards + +* Configure SX1 board to use drivers/cfi_flash.c + +* Patches by Michael Bendzick, 30 Aug 2004: + - Configure omap1510inn board to use drivers/cfi_flash.c + - Make drivers/cfi_flash.c protect environment and redundant + environment. + +* Patch by Steven Scholz, 23 Jun 2004: + - Add script (tools/img2brec.sh) to programm U-Boot into + (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L + +* Patches by Scott McNutt, 24 Aug 2004: + - Add support for Altera Nios-II processors. + - Add support for Psyent PCI-5441 board. + - Add support for Psyent PK1C20 board. + +* Patches by Jon Loeliger, 24 Aug 2004: + - Add support for the MPC8541 and MPC8555 CDS boards + - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR + - Convert MPC85xxADS to use common CFI flash driver + - Fix PCI window on MPC85xx; remove unneeded PCI initialization + from board_early_init_f() + - Provide SW workaround for PCI initialization on 85xx CDS + +* Patches by George G. Davis, 24 Aug 2004: + - Enable ramdisk/initrd tagged param support for omap1610h2_config + - Remove static network setup defaults from mx1ads_config + - update ARM boards to use constants from mach-types.h + +* Patch by Gary Jennejohn, 04 Oct 2004: + - fix I2C on at91rm9200 + - add support for Ricoh RS5C372A RTC + +* Patch by Gary Jennejohn, 01 Oct 2004: + - add support for CMC PU2 board + - add support for I2C on at91rm9200 + +* Patch by Gary Jennejohn, 28 Sep 2004: + fix baudrate handling on at91rm9200 + +* Patch by Yuli Barcohen, 22 Aug 2004: + - remove ZPC.1900 board-specific flash driver; + switch the port to generic CFI driver; + - port clean-up + +* Patch by Hinko Kocevar, 21 Aug 2004: + Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB + +* Clean up tools/bmp_logo.c to not add trailing white space + +* Patch by Hinko Kocevar, 21 Aug 2004: + - Group common framebuffer functions in common/lcd.c + - Group common framebuffer macros and #defines in include/lcd.h + - Provide calc_fbsize() for video ATAG + +* Patch by Sam Song, 21 August 2004: + - Fix a typo in README + - Align "(RO)" output for "flinfo" after "protect on" + - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency + ratio 1:1 when core frequency less than 50MHz + +* Patches by Hinko Kocevar, 21 Aug 2004: + - fix some "use of label at end of compound statement" warnings + - Define type of LCD panel on lubbock board if CONFIG_LCD is used + +* Patch by Steven Scholz, 16 Aug 2004: + - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)" + - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0 + - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/ + - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/ + into cpu/arm920t/$(SOC)/ + +* Patches by Sean Chang, 09 Aug 2004: + - Added support for both 8 and 16 bit mode access to System ACE CF + through MPU. + - Fixed missing System ACE CF device during get FAT partition info + in fat_register_device function. + - Enabled System ACE CF support on ML300. + +* Patch by Sean Chang, 09 Aug 2004: + Synch defines for saveenv and do_saveenv functions so they get + compiled under the same statement. + +* Patch by Sean Chang, 09 Aug 2004: + - Added I2C support for ML300. + - Added support for ML300 to read out its environment information + stored on the EEPROM. + - Added support to use board specific parameters as part of + U-Boot's environment information. + - Updated MLD files to support configuration for new features + above. + +* Patches by Travis Sawyer, 05 Aug 2004: + - Remove incorrect bridge settings for eth group 6 + - Add call to setup bridge in ppc_440x_eth_initialize + - Fix ppc_440x_eth_init to reset the phy only if its the + first time through, otherwise, just check the phy for the + autonegotiated speed/duplex. This allows the use of netconsole + - only print the speed/duplex the first time the phy is reset. + +* Patch by Shlomo Kut, 29 Mar 2004: + Add support for MKS Instruments "Quantum" board + +* Fix build problem with Cogent boards; + avoid using when using the host compiler + +* Patch by Ganapathi C, 04 Aug 2004: + Fix NFS timeout issue + +* Patch by Yuli Barcohen, 19 Jul 2004: + - Fix host tools building in Cygwin environment + - Fix header files search order for host tools + +* Patch by Tom Armistead, 19 Jul 2004: + Fix kgdb.S support for 74xx_75x cpu + +* Patch by Jon Loeliger, 15 Jul 2004: + Fix MPC85xx I2C driver + +* Fix problems with CDROM drive as slave device on Lite5200 IDE bus. + +* Patch by Stephen Williams, 15 July 2004 + Set the PCI class code for JSE board as part of PCI interface setup + +* Patch by Michael Bendzick, 15 Jul 2004: + Fix problem with writes with odd sizes in drivers/cfi_flash.c when + CFG_FLASH_USE_BUFFER_WRITE is set + +* Patch by Yuli Barcohen, 13 Jul 2004: + Allow clock setting on MPC866/MPC885 series chips according to + environment variable `cpuclk' + +* Patch by Yuli Barcohen, 20 Apr 2004: + Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x + +* Patch by Vincent Dubey, 24 Sep 2004: + Add support for xaeniax board + +* Add comment about non-GPL character of standalone applications to + COPYING file + +* Fix FEC ethernet problem on NSCU board. + +* Patch by Gary Jennejohn, 09 Sep 2004: + allow to use USART1 as console port on at91rm9200dk boards + +* Patch by Stefan Roese, 16 Sep 2004: + Update AR405 board. + +* Fix SysClk handling for PPChameleon and CATcenter boards + +* Patch by Detlev Zundel, 08 Sep 2004: + Update etags build target + +* Improve NetConsole support: add support for broadcast destination + address and buffered input. + +* Cleanup compiler warnings for GCC 3.3.x and later + +* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch + +* Add support for IDS "NC650" board + +* Add automatic update support for LWMON board + +* Clear Block Lock-Bits when erasing flash on LWMON board. + +* Fix return code of "fatload" command + +* Enable MSDOS/VFAT filesystem support for LWMON board + +* Patch by Martin Krause, 03 Aug 2004: + change timing for SM501 graphics controller on TQM5200 module + +* Patch by Mark Jonas, 13 July 2004: + - Total5200 LCD now run in little endian mode. Endianess conversion + is done in hardware. + - Removed last reference to "console" environment variable. + +* Patches by Lars Munch, 12 Jul 2004: + - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk + board specific + - split out the LXT971A PHY from ns_9750_eth.h + - split the dm9161 phy part out of at91rm9200_ether.c + +* Patch by Andreas Engel, 12 Jul 2004: + Replaced hardcoded PL011 clock frequency with config variable. + Fixed wrong CONFIG_CMD_DFL doc. + +* Patch by Thomas Viehweger, 09 Jun 2004: + make it possible to remove chpart when there is only one partition + +* Add support for console over UDP (compatible to Ingo Molnar's + netconsole patch under Linux) + +* Patch by Jon Loeliger, 16 Jul 2004: + - support larger DDR memories up to 2G on the PC8540/8560ADS and + STXGP3 boards + - Made MPC8540/8560ADS be 33Mhz PCI by default. + - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 + and CONFIG_L2_INIT_RAM options. + - Refactor Local Bus initialization out of SDRAM setup. + - Re-implement new version of LBC11/DDR11 errata workarounds. + - Moved board specific PCI init parts out of CPU directory. + - Added TLB entry for PCI-1 IO Memory + - Updated README.mpc85xxads + +* Patch by Sascha Hauer, 28 Jun: + - add generic support for Motorola i.MX architecture + - add support for mx1ads, mx1fs2 and scb9328 boards + +* Patches by Marc Leeman, 23 Jul 2004: + - Add define for the PCI/Memory Buffer Configuration Register + - corrected comments in cpu/mpc824x/cpu_init.c + +* Add support for multiple serial interfaces + (for example to allow modem dial-in / dial-out) + +* Patch by Stefan Roese, 15 Jul 2004: + cpu/ppc4xx/sdram.c rewritten now using get_ram_size() + +* Fix NSCU config; add ethernet wakeup code. + +* Add link for preloader for Motorola Coldfire to README.m68k + +* Patch by Michael Bendzick, 12 Jul 2004: + fix output formatting in drivers/cfi_flash.c + +* Patch by Mark Jonas, 02 Jul 2004: + Fix lowboot (again) on MPC5xxx + +* Patch by Curt Brune, 07 Jul 2004: + relocate exception vectors on arm720t if needed + +* Patch by George G. Davis, 06 Jul 2004: + - update mach-types.h to latest arm.linux.org.uk master list + - Set correct OMAP1610 bi_arch_number for build target + +* Patch by Curt Brune, 06 Jul 2004: + evb4510: add support for timer interrupt; cleanup + +* Patch by Dan Poirot, 06 Jul 2004: + Fix sbc8260 environment variables + +* Cleanup redundand "console" environment variable + +* Patch by Mark Jonas, 05 Jul 2004: + add support for the Total5100's and Total5200's LCD screen + +* Patches by Dan Eisenhut, 01 Jul 2004: + - README fixes. + - Move doc2000.h include to prevent compiler warning on some boards + +* Patch by Mark Jonas, 01 Jul 2004: + Added support for Total5100 and Total5200 (Rev.1 and Rev.2) + MGT5100 and MPC5200 based Freescale platforms. + +* Patch by Philippe Robin, 01 Jul 2004: + Add initialization for Integrator and versatile board files. + +* Patch by Hinko Kocevar, 01 Jun 2004: + Fix VFD FB allocation, add LCD FB allocation on ARM + +* Patch by Martin Krause, 30 Jun 2004: + Add support for TQM5200 board + +* Patch by Martin Krause, 29 Jun 2004: + Add loopw command: infinite write loop on address range + +* Patches by Yasushi Shoji, 29 Jun 2004: + - add empty include/asm-microblaze/processor.h + - add to CREDITS and MAINTAINERS + - add gd initialization + - add MicroBlaze and SUZAKU board to MAKEALL script + - add reset support for SUZAKU + - add flush_cache() for MicroBlaze + - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed + size flash memory on SUZAKU + +* Patch by Prakash Kumar, 27 Jun 2004: + Add support for the PXA250 based Intrinsyc Cerf board. + +* Patch by Yasushi Shoji, 27 Jun 2004: + fix comment in include/common.h + +* Rename SBC8560 into sbc8560 for consistency + +* Patch by Daniel Poirot, 24 Jun 2004: + Add support for Wind River's sbc8240 board + +* Patches by Yasushi Shoji, 26 Jun 2004: + - drivers/serial_xuartlite.c: fix "return 0" in void function + - add microblaze support to mkimage tool + +* Patch by Fred Klatt, 25 Jun 2004: + Add support for WindRiver's sbc8560 board + +* Patch by Nicolas Lacressonniere, 24 Jun 2004 + Small Bugs fixes for "at91rm9200dk" board: + - Timing modifications for SPI DataFlash access + - Fix NAND flash detection bug + +* Patch by Nicolas Lacressonniere, 24 Jun 2004: + Add Support for Flash AT49BV6416 for AT91RM9200DK board + +* Patch by Jon Loeliger, 17 June 2004: + Completion of the 8540ADS/8560ADS updates: + Fix some PCI and Rapid I/O memory maps, + Initialize both TSEC 1 and 2, + Initialize SDRAM + Update MAINTAINER for 85xx boards and README.mpc85xxads + +* Patch by Yuli Barcohen, 16 Jun 2004: + Remove obsolete AdderII port which was superseded by unified + AdderII/Adder87x port + +* Patch by Ladislav Michl, 16 Jun 2004: + Fix gcc-3.3.3 warnings for smc91111.c + +* Patch by Stefan Roese, 02 Jul 2004: + - Fix bug in 405 ethernet driver; allocated data not cleared! + - Fix problem in 405 i2c driver; don't try to print without console! + +* Patch by Paul Ruhland, 11 Jun 2004: + Remove debug code from 'board/lpd7a40x/flash.c' + +* Patch by Andrea Marson, 11 Jun 2004: + Update for PPChameleon board: + - support for SysClk @ 25MHz + - support for Silicon Motion SM712 VGA controller + - some clean ups + +* Patches by Richard Woodruff, 10 Jun 2004: + - fix problems with examples/stubs.c for GCC >= 3.4 + - fix problems with gd initialization + +* Patch by Curt Brune, 17 May 2004: + - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC) + - Add support for ESPD-Inc. EVB4510 Board + +* Patch by Marc Leeman, 11 May 2004: + Fix for MPC8245 - reading PPC Memory from another device with the + PPC as PCI target device corrupts data due to interenal hardware + buffering. + +* Fix "cls" command when used with splash screen + +* Increase NFS download timeout (now 1 min - 10 sec is to short for a + slow download of a big image) + +* Add "cls" function to MPC823 LCD driver so we can reinitialize the + display even after showing a bitmap + +* Patch by Josef Wagner, 04 Jun 2004: + - DDR Ram support for PM520 (MPC5200) + - support for different flash types (PM520) + - USB / IDE / CF-Card / DiskOnChip support for PM520 + - 8 bit boot rom support for PM520/CE520 + - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) + - I2C and RTC support for CPC45 + - support of new flash type (28F160C3T) for CPC45 + +* Fix flash parameters passed to Linux for PPChameleon board + +* Remove eth_init() from lib_arm/board.c; it's done in net.net.c. + +* Patch by Paul Ruhland, 10 Jun 2004: + fix support for Logic SDK-LH7A404 board and clean up the + LH7A404 register macros. + +* Patch by Matthew McClintock, 10 Jun 2004: + Modify code to select correct serial clock on Sandpoint8245 + +* Patch by Robert Schwebel, 10 Jun 2004: + Add support for Intel K3 strata flash. + +* Patch by Thomas Brand, 10 Jun 2004: + Fix "loads" command on DK1S10 board + +* Patch by Yuli Barcohen, 09 Jun 2004: + Add support for 8MB flash SIMM and JFFS2 file system on + Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS). + +* Patch by Yuli Barcohen, 09 Jun 2004: + Add support for Analogue&Micro Adder87x and the older AdderII board. + +* Patch by Ming-Len Wu, 09 Jun 2004: + Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board + +* Patch by Sam Song, 09 Jun 2004: + - Add support for RPXlite_DW board + - Update FLASH driver for 4*AM29DL323DB90VI + - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board + +* Patch by Mark Jonas, 08 June 2004: + - Make MPC5200 boards evaluate the SVR to print processor name and + version in checkcpu() (cpu/mpc5xxx/cpu.c). + +* Patch by Kai-Uwe Bloem, 06 May 2004: + Fix endianess problem in cramfs code + +* Patch by Tom Armistead, 04 Jun 2004: + Add support for MAX6900 RTC + +* Patches by Ladislav Michl, 03 Jun 2004: + - fix cfi_flash.c on LE systems + - let 'make mrproper' delete u-boot.img as well + - turn printf into debug in cfi_flash.c + +* Patch by Kurt Stremerch, 28 May 2004: + Add support for Exys XSEngine board + +* Patch by Martin Krause, 27 May 2004: + Fix a MPC5xxx I2C timing issue in i2c_probe(). + +* Patch by Leif Lindholm, 27 May 2004: + Fix board_init_f() for dbau1x00 board. + +* Patch by Imre Deak, 26 May 2004: + On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3). + Set flash base accordingly, and decide whether to do or skip board + specific setup steps. + +* Patch by Josef Baumgartner, 26 May 2004: + Add missing define in include/asm-m68k/global_data.h + +* Patch by Josef Baumgartner, 25 May 2004: + Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c + +* Patch by Paul Ruhland, 24 May 2004: + fix SDRAM initialization for LPD7A400 board. + +* Patch by Jian Zhang, 20 May 2004: + add support for environment in NAND flash + +* Patch by Yuli Barcohen, 20 May 2004: + Add support for Interphase iSPAN boards. + +* Patches by Paul Ruhland, 17 May 2004: + - Add I/O functions to the smc91111 ethernet driver to support the + Logic LPD7A40x boards. + - Add support for the Logic Zoom LH7A40x based SDK board(s), + specifically the LPD7A400. + +* Patches by Robert Schwebel, 15 May 2004: + - call MAC address reading code also for SMSC91C111; + - make SMSC91C111 timeout configurable, remove duplicate code + - fix get_timer() for PXA + - update doc/README.JFFS2 + - use "bootfile" env variable also for jffs2 + +* Patch by Tolunay Orkun, 14 May 2004: + Add support for Cogent CSB472 board (8MB Flash Rev) + +* Patch by Thomas Viehweger, 14 May 2004: + - flash.h: more flash types added + - immap_8260.h: some bits added (useful for RMII) + - cmd_coninfo.c: typo corrected, printf -> puts + - reduced size by replacing spaces with tab + +* Patch by Robert Schwebel, 13 May 2004: + Add 'imgextract' command: extract one part of a multi file image. + +* Patches by Jon Loeliger, 11 May 2004: + Dynamically handle REV1 and REV2 MPC85xx parts. + (Jon Loeliger, 10-May-2004). + New consistent memory map and Local Access Window across MPC85xx line. + New CCSRBAR at 0xE000_0000 now. + Add RAPID I/O memory map. + New memory map in README.MPC85xxads + (Kumar Gala, 10-May-2004) + Better board and CPU identification on MPC85xx boards at boot. + (Jon Loeliger, 10-May-2004) + SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. + Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. + (Jim Robertson, 10-May-2004) + Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. + Supports multiple PHYs. + (Andy Fleming, 10-May-2004) + Some README.MPC85xxads updates. + (Kumar Gala, 10-May-2004) + Copyright updates for "Freescale" + (Andy Fleming, 10-May-2004) + +* Patch by Stephen Williams, 11 May 2004: + Add flash support for ST M29W040B + Reduce JSE specific flash.c to remove dead code. + +* Patch by Markus Pietrek, 04 May 2004: + Fix clear_bss code for ARM systems (all except s3c44b0 which + doesn't clear BSS at all?) + +* Fix "ping" problem on INC-IP board. Strange problem: + Sometimes the store word instruction hangs while writing to one of + the Switch registers, but only if the next instruction is 16-byte + aligned. Moving the instruction into a separate function somehow + makes the problem go away. + +* Patch by Rishi Bhattacharya, 08 May 2004: + Add support for TI OMAP5912 OSK Board + +* Patch by Sam Song May, 07 May 2004: + Fix typo of UPM table for rmu board + +* Patch by Pantelis Antoniou, 05 May 2004: + - Intracom board update. + - Add Codec POST. + +* Add support for the second Ethernet interface for the 'PPChameleon' + board. + +* Patch by Dave Peverley, 30 Apr 2004: + Add support for OMAP730 Perseus2 Development board + +* Patch by Alan J. Luse, 29 Apr 2004: + Fix flash chip-select (OR0) option register setting on FADS boards. + +* Patch by Alan J. Luse, 29 Apr 2004: + Report MII network speed and duplex setting properly when + auto-negotiate is not enabled. + +* Patch by Jarrett Redd, 29 Apr 2004: + Fix hang on reset on Ocotea board due to flash in wrong mode. + +* Patch by Dave Peverley, 29 Apr 2004: + add MAC address detection to smc91111 driver + +* Patch by David Müller, 28 Apr 2004: + fix typo in lib_arm/board.c + +* Patch by Tolunay Orkun, 20 Apr 2004: + - README update: add CONFIG_CSB272 and csb272_config + - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and + i2cfast environment variable + +* Patch by Yuli Barcohen, 19 Apr 2004: + - Rename DUET_ADS to MPC885ADS + - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY + - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY + - Clean up FADS family port to use the new defines + +* Fix PCI support on CPC45 board + +* Patch by Scott McNutt, 25 Apr 2004: + Add Nios GDB/JTAG Console support: + - Add stubs to support gdb via JTAG. + - Add support for console over JTAG. + - Minor cleanup. + +* Add support for CATcenter board (based on PPChameleon ME module) + +* Patch by Klaus Heydeck, 12 May 2004: + Using external watchdog for KUP4 boards in mpc8xx/cpu.c; + load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c; + various changes to KUP4 board specific files + +* Fix minor network problem on MPC5200: need some delay between + resetting the PHY and sending the first packet. Implemented in a + "natural" way by invoking the PHY reset and initialization code + only once after power on vs. each time the interface is brought up. + +* Add some limited support for low-speed devices to SL811 USB controller + (at least "usb reset" now passes successfully and "usb info" displays + correct information) + +* Change init sequence for multiple network interfaces: initialize + on-chip interfaces before external cards. + +* Fix memory leak in the NAND-specific JFFS2 code + +* Fix SL811 USB controller when attached to a USB hub + +* Fix config option spelling in PM520 config file + +* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by + patches by Pantelis Antoniou, 30 Mar 2004) + +* Fix minor NAND JFFS2 related issue + +* Fixes for SL811 USB controller: + - implement workaround for broken memory stick + - improve error handling + +* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better + cope with congested networks. + +====================================================================== +Changes for U-Boot 1.1.1: +====================================================================== + +* Patch by Travis Sawyer, 23 Apr 2004: + Fix VSC/CIS 8201 phy descrambler interoperability timing due to + errata from Vitesse Semiconductor. + +* Patch by Philippe Robin, 22 Apr 2004: + Fix ethernet configuration for "versatile" board + +* Patch by Kshitij Gupta, 21 Apr 2004: + Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards + +* Patch by Steven Scholz, 24 Feb 2004: + Fix a bug in AT91RM9200 ethernet driver: + The MII interface is now initialized before accessing the PHY. + +* Patch by John Kerl, 19 Apr 2004: + Use U-boot's miiphy.h for PHY register names, rather than + introducing a new header file. + +* Update pci_ids.h from linux-2.4.26 + +* Patch by Masami Komiya, 19 Apr 2004: + Fix problem cause by VLAN function on little endian architecture + without VLAN environment + +* Clean up the TQM8xx_YYMHz configurations; allow to use the same + binary image for all clock frequencies. Implement run-time + optimization of flash access timing based on the actual bus + frequency. + +* Modify KUP4X board configuration to use SL811 driver for USB memory + sticks (including FAT / VFAT filesystem support) + +* Add SL811 Host Controller Interface driver for USB + +* Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README + +* Patch by Pantelis Antoniou, 19 Apr 2004: + Allow to use shell style syntax (i. e. ${var} ) with standard parser. + Minor patches for Intracom boards. + +* Patch by Christian Pell, 19 Apr 2004: + cleanup support for CF/IDE on PCMCIA for PXA25X + +* Temporarily disabled John Kerl's extended MII command code because + "miivals.h" is missing + +* Patches by Mark Jonas, 13 Apr 2004: + - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S + - Add sync instructions to IceCube SDRAM init code + - Move SDRAM chip constants into seperate include files + - Unify DDR and SDR initialization code + - Unify all IceCube (Lite5xxx) target names + +* Patch by John Kerl, 16 Apr 2004: + Enable ranges in mii command, e.g. mii read 0-1f 0 or + mii read 4-7 18-1a. Also add mii dump subcommand for + pretty-printing standard regs 0-5. + +* Patch by Stephen Williams, 16 April 2004: + fix typo in JSE.h; update MAINTAINERS + +* Patch by Matthew S. McClintock, 14 Apr 2004: + fix initdram function for utx8245 board + +* Patch by Markus Pietrek, 14 Apr 2004: + use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag + +* Patch by Reinhard Meyer, 18 Apr 2004: + provide the IDE Reset Function for EMK 5200 boards + +* Patch by Masami Komiya, 12 Apr 2004: + fix pci_hose_write_config_{byte,word}_via_dword problems + +* Patch by Sangmoon Kim, 12 Apr 2004: + Update max RAM size for debris board + +* Patch by Travis Sawyer, 08 Apr 2004: + Add TLB entry for second DIMM slot on ocotea + +* Patch by Masami Komiya, 08 Apr 2004: + add RTL8169 network driver + +* Patch by Dan Malek, 07 Apr 2004: + - Add support for RPC/STx GP3, Motorola 8560 board + - Update 85xx TSEC driver so it searches MII for first available PHY + and uses that one. + - Add functions to support console MII commands. + +* Patch by Tolunay Orkun, 07 Apr 2004: + Move initialization of bi_iic_fast[] + from board_init_f() to board_init_r() + +* Patch by Yasushi Shoji, 07 Apr 2004: + Cleanup microblaze port + +* Patch by Sangmoon Kim, 07 Apr 2004: + Add auto SDRAM module detection for Debris board + +* Patch by Rune Torgersen, 06 Apr 2004: + - Fix some PCI problems on the MPC8266ADS board + - Fix the location of some PCI entries in the immap structure + +* Patch by Yasushi Shoji, 07 Apr 2004: + - add support for microblaze processors + - add support for AtmarkTechno "suzaku" board + +* Configure PPChameleon board to use redundand environment in flash + +* Configure PPChameleon board to use JFFS2 NAND support. + +* Added support for JFFS2 filesystem (read-only) on top of NAND flash + +* Patch by Rune Torgersen, 16 Apr 2004: + LBA48 fixes + +* Patches by Pantelis Antoniou, 16 Apr 2004: + - add support for a new version of an Intracom board and fix + various other things on others. + - add verify support to the crc32 command (define + CONFIG_CRC32_VERIFY to enable it) + - fix FEC driver for MPC8xx systems: + 1. fix compilation problems for boards that use dynamic + allocation of DPRAM + 2. shut down FEC after network transfers + - HUSH parser fixes: + 1. A new test command was added. This is a simplified version of + the one in the bourne shell. + 2. A new exit command was added which terminates the current + executing script. + 3. Fixed handing of $? (exit code of last executed command) + - Fix some compile problems; + add "once" functionality for the netretry variable + +* Patch by George G. Davis, 02 Apr 2004: + add support for Intel Assabet board + +* Patch by Stephen Williams, 01 Apr 2004: + Add support for Picture Elements JSE board + +* Patch by Christian Pell, 01 Apr 2004: + Add CompactFlash support for PXA systems. + +* Patches by Pantelis Antoniou, 30 Mar 2004: + - add auto-complete support to the U-Boot CLI + - add support for NETTA and NETPHONE boards; fix NETVIA board + - add support for the Epson 156x series of graphical displays + (These displays are serial and not suitable for using a normal + framebuffer console on them) + - add infrastructure needed in order to POST any DSPs in a board + - improve and fix various things in the MPC8xx FEC driver: + 1. The new 87x and 88x series of processors have two FECs, + and the new driver supports them both. + 2. Another change in the 87x/88x series is support for + the RMII (Reduced MII) interface. However numerous + changes are needed to make it work since the PHYs + are connected to the same lines. That means that + you have to address them correctly over the MII + interface. + 3. We now correctly match the MII/RMII interface + configuration to what the PHY reports. + - Fix problem when readingthe MII status register. Due to the + internal design of many PHYs you have to read the register + twice. The problem is more apparent in 10Mbit mode. + - add new mode ".jffs2s" for reading from a NAND device: it just + skips over bad blocks. + - add networking support for VLANs (802.1q), and CDP (Cisco + Discovery Protocol) + - some minor patches / cleanup + +* Patch by Yuli Barcohen, 28 Mar 2004: + - Add support for MPC8272 family including MPC8247/8248/8271/8272 + - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS) + - Change configuration method for MPC8260ADS family + +* add startup code to clear the BSS of standalone applications + +* Fix if / elif handling bug in HUSH shell + +====================================================================== +Changes for U-Boot 1.1.0: +====================================================================== + +* Patch by Mark Jonas: Remove config.tmp files only when + unconfiguring the board + +* Adapt RMU board for bigger flash memory + +* Patch by Klaus Heydeck, 13 Mar 2003: + Add support for KUP4X Board + +* Patch by Pavel Bartusek, 21 Mar 2004 + Add Reiserfs support + +* Patch by Hinko Kocevar, 20 Mar 2004 + - Add auto-release for SMSC LAN91c111 driver + - Add save/restore of PTR and PNR regs as suggested in datasheet + +* Patch by Stephen Williams, 19 March 2004 + Increase speed of sector reads from SystemACE, + shorten poll timeout and remove a useless reset + +* Patch by Tolunay Orkun, 19 Mar 2004: + Make GigE PHY 1000Mbps Speed/Duplex detection conditional + (CONFIG_PHY_GIGE) + +* Patch by Brad Kemp, 18 Mar 2004: + prevent machine checks during a PCI scan + +* Patch by Pierre Aubert, 18 Mar 2004: + Fix string cleaning in IDE identification + +* Patch by Pierre Aubert, 18 Mar 2004: + - Unify video mode handling for Chips & Technologies 69000 Video + chip and Silicon Motion SMI 712/710/810 Video chip + - Add selection of the video output (CRT or LCD) via 'videoout' + environment variable for the Silicon Motion + - README update + +* Patch by Pierre Aubert, 18 Mar 2004: + include/common.h typo fix + +* Patches by Tolunay Orkun, 17 Mar 2004: + - Add support for bd->bi_iic_fast[] initialization via environment + variable "i2cfast" (CONFIG_I2CFAST) + - Add "i2cfast" u-boot environment variable support for csb272 + +* Patch by Carl Riechers, 17 Mar 2004: + Ignore '\0' characters in console input for use with telnet and + telco pads. + +* Patch by Leon Kukovec, 17 Mar 2004: + typo fix for strswab prototype #ifdef + +* Patches by Thomas Viehweger, 16 Mar 2004: + - show PCI clock frequency on MPC8260 systems + - add FCC_PSMR_RMII flag for HiP7 processors + - in do_jffs2_fsload(), take load address from load_addr if not set + explicit, update load_addr otherwise + - replaced printf by putc/puts when no formatting is needed + (smaller code size, faster execution) + +* Patch by Phillippe Robin, 16 Mar 2004: + avoid dereferencing NULL pointer in lib_arm/armlinux.c + +* Patch by Stephen Williams, 15 Mar 2004: + Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation + +* Patch by Tolunay Orkun, 15 Mar 2004: + Initialize bi_opbfreq to real OPB frequency via get_OPB_freq() + +* Patch by Travis Sawyer, 15 Mar 2004: + Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port + +* Add start-up delay to make sure power has stabilized before + attempting to switch on USB on SX1 board. + +* Patch by Josef Wagner, 18 Mar 2004: + - Add support for MicroSys XM250 board (PXA255) + - Add support for MicroSys PM828 board (MPC8280) + - Add support for 32 MB Flash on PM825/826 + - new SDRAM refresh rate for PM825/PM826 + - added support for MicroSys PM520 (MPC5200) + - replaced Query by Identify command in CPU86/flash.c + to support 28F160F3B + +* Fix wrap around problem with udelay() on ARM920T + +* Add support for Macronix flash on TRAB board + +* Patch by Pierre Aubert, 15 Mar 2004: + Fix buffer overflow in IDE identification + +* Fix power-off of LCD for out-of-band temperatures on LWMON board + +* Remove redundand #define in IceCube.h + +* Patch by Steven Scholz, 27 Feb 2004: + - Adding get_ticks() and get_tbclk() for AT91RM9200 + - Many white space fixes in cpu/at91rm9200/interrupts.c + +* Patches by Steven Scholz, 20 Feb 2004: + some cleanup in AT91RM9200 related code + +* Patches by Travis Sawyer, 12 Mar 2004: + - Fix Gigabit Ethernet support for 440GX + - Add Gigabit Ethernet Support to MII PHY utilities + +* Patch by Brad Kemp, 12 Mar 2004: + Fixes for drivers/cfi_flash.c: + - Better support for x8/x16 implementations + - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE + - Added defines for AMD command and address constants + +* Patch by Leon Kukovec, 12 Mar 2004: + Fix get_dentfromdir() to correctly handle deleted dentries + +* Patch by George G. Davis, 11 Mar 2004: + Remove hard coded network settings in TI OMAP1610 H2 + default board config + +* Patch by George G. Davis, 11 Mar 2004: + add support for ADS GraphicsClient+ board. + +* Patch by Pierre Aubert, 11 Mar 2004: + - add bitmap command and splash screen support in cfb console + - add [optional] origin in the bitmap display command + +* Patch by Travis Sawyer, 11 Mar 2004: + Fix ocotea board early init interrupt setup. + +* Patch by Thomas Viehweger, 11 Mar 2004: + Remove redundand code; add PCI-specific bits to include/mpc8260.h + +* Patch by Stephan Linz, 09 Mar 2004 + - Add support for the SSV ADNP/ESC1 (Nios Softcore) + +* Patch by George G. Davis, 9 Mar 2004: + fix recent build failure for SA1100 target + +* Patch by Travis Sawyer, 09 Mar 2004: + Support native interrupt mode for the IBM440GX. + Previously it was running in 440GP compatibility mode. + +* Patch by Philippe Robin, 09 Mar 2004: + Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference + Platform support. + +* Patch by Masami Komiya, 08 Mar 2004: + Don't overwrite server IP address or boot file name + when the boot server does not return values + +* Patch by Tolunay Orkun, 5 Mar 2004: + Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC + +* Patch by Tolunay Orkun, 5 Mar 2004: + Fix early board initialization for Cogent CSB272 board + +* Patch by Ed Okerson, 3 Mar 2004: + fix CFI flash writes for little endian systems + +* Patch by Reinhard Meyer, 01 Mar 2004: + generalize USB and IDE support for MPC5200 with according + changes to IceCube.h and TOP5200.h + add Am29LV256 256 MBit FLASH support for TOP5200 boards + add info about USB and IDE to README + +* Patch by Yuli Barcohen, 4 Mar 2004: + Fix problems with GCC 3.3.x which changed handling of global + variables explicitly initialized to zero (now in .bss instead of + .data as before). + +* Patch by Leon Kukovec, 02 Mar 2004: + add strswab() to fix IDE LBA capacity, firmware and model numbers + on little endian machines + +* Patch by Masami Komiya, 02 Mar 2004: + - Remove get_ticks() from NFS code + - Add verification of RPC transaction ID + +* Patch by Pierre Aubert, 02 Mar 2004: + cleanup for IDE and USB drivers for MPC5200 + +* Patch by Travis Sawyer, 01 Mar 2004: + Ocotea: + - Add IBM PPC440GX Ref Platform support (Ocotea) + Original code by Paul Reynolds + Adapted to U-Boot and 440GX port + 440gx_enet.c: + - Add gracious handling of all Ethernet Pin Selections for 440GX + - Add RGMII selection for Cicada CIS8201 Gigabit PHY + ppc440.h: + - Add needed bit definitions + - Fix formatting + +* Patch by Carl Riechers, 1 Mar 2004: + Add PPC440GX prbdv0 divider to fix memory clock calculation. + +* Patch by Stephan Linz, 27 Feb 2004 + - avoid problems for targets without NFS download support + +* Patch by Rune Torgersen, 27 Feb 2004: + - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA) + - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF) + - Added support for 64bit strtoul (CFG_64BIT_STRTOUL) + +* Patch by Masami Komiya, 27 Feb 2004: + Fix rarpboot: add autoload by NFS + +* Patch by Dan Eisenhut, 26 Feb 2004: + fix flash_write return value in saveenv + +* Patch by Stephan Linz, 11 Dec 2003 + expand config.mk to avoid trigraph warnings on NIOS + +* Rename "BMS2003" board into "HMI10" + +* SX1 patches: use "serial#" for USB serial #; use redundand environment + storage; auto-set console on USB port (using preboot command) + +* Add support for SX1 mobile phone; add support for USB-based console + (enable with "setenv stdout usbtty; setenv stdin usbtty") + +* Fix LOWBOOT configuration for MPC5200 with DDR memory + +* Fix SDRAM timings for LITE5200 / IceCube board + +* Handle Auti-MDIX / connection status for INCA-IP + +* Fix USB problems when attempting to read 0 bytes + +* Patch by Travis Sawyer, 26 Feb 2004: + Fix broken compile for XPEDITE1K target. + +* Patch by Stephan Linz, 26 Feb 2004: + Bug fix for NFS code on NIOS targets + +* Patch by Stephen Williams, 26 Feb 2004: + Break up SystemACE reads of large block counts + +* Patch by Pierre Aubert, 26 Feb 2004 + add IDE support for MPC5200 + +* Patch by Masami Komiya, 26 Feb 2004: + add autoload via NFS + +* Patch by Stephen Williams + Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses + elsewhere in the source. + +* Patch by Steven Scholz, 25 Feb 2004: + - Timeouts in FPGA code should be based on CFG_HZ + - Minor cleanup in code for Altera FPGA ACEX1K + +* Patch by Steven Scholz, 25 Feb 2004: + Changed "Directory Hierarchy" section in README + +* Patch by Masami Komiya, 25 Feb 2004: + Reduce copy count in nfs_read_reply() of NFS code + +* Patch by Markus Pietrek, 24 Feb 2004: + NS9750 DevBoard added + +* Patch by Pierre Aubert, 24 Feb 2004 + add USB support for MPC5200 + +* Patch by Steven Scholz, 24 Feb 2004: + - fix MII commands to use values from last command + +* Patch by Torsten Demke, 24 Feb 2004: + Add support for the eXalion platform (SPSW-8240, F-30, F-300) + +* Patch by Rahul Shanbhag, 19 Feb 2004: + Fixes for for OMAP1610 board: + - shift some IRQ specific code to platform.S file + - remove duplicatewatchdog reset code from start.S + +* Make Auto-MDIX Support configurable on INCA-IP board + +* Fix license for mkimage tool + +* Patch by Masami Komiya, 24 Feb 2004: + Update NetBootFileXferSize in NFS code + +* Patch by Scott McNutt, 24 Feb 2004: + fix packet length in NFS code + +* Patch by Masami Komiy, 22 Feb 2004: + Add support for NFS for file download + +* Patch by Andrea Scian, 17 Feb 2004: + Add support for S3C44B0 processor and DAVE B2 board + +* Patch by Steven Scholz, 20 Feb 2004: + - Add support for MII commands on AT91RM9200 boards + - some cleanup in AT91RM9200 ethernet code + +* Patch by Peter Ryser, 20 Feb 2004: + Add support for the Xilinx ML300 platform + +* Patch by Stephan Linz, 17 Feb 2004: + Fix watchdog support for NIOS + +* Patch by Josh Fryman, 16 Feb 2004: + Fix byte-swapping for cfi_flash.c for different bus widths + +* Patch by Jon Diekema, 14 Jeb 2004: + Remove duplicate "FPGA Support" notes from the README file + +* Patches by Reinhard Meyer, 14 Feb 2004: + - update board/emk tree; use common flash driver + - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c + [adapted for other PPC CPUs -- wd] + - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c + +* Patch by Jon Diekema, 13 Feb 2004: + Call show_boot_progress() whenever POST "FAILED" is printed. + +* Patch by Nishant Kamat, 13 Feb 2004: + Add support for TI OMAP1610 H2 Board + Fixes for cpu/arm926ejs/interrupt.c + (based on Richard Woodruff's patch for arm925, 16 Oct 03) + Fix for a timer bug in OMAP1610 Innovator + Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2 + +* Patches by Stephan Linz, 12 Feb 2004: + - add support for NIOS timer with variable period preload counter value + - prepare POST framework support for NIOS targets + +* Patch by Denis Peter, 11 Feb 2004: + add POST support for the MIP405 board + +* Patch by Laurent Mohin, 10 Feb 2004: + Fix buffer overflow in common/usb.c + +* Patch by Tolunay Orkun, 10 Feb 2004: + Add support for Cogent CSB272 board + +* Patch by Thomas Elste, 10 Feb 2004: + Add support for NET+50 CPU and ModNET50 board + +* Patch by Sam Song, 10 Feb 2004: + Fix typos in cfi_flash.c + +* Patch by Leon Kukovec, 10 Feb 2004 + Fixed long dir entry slot id calculation in get_vfatname + +* Patch by Robin Gilks, 10 Feb 2004: + add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==, + !=, <>, <, >, <=, >=) + +* Fix problem with side effects in macros in include/usb.h + +* Patch by David Benson, 13 Nov 2003: + bug 841358 - fix TFTP download size limit + +* Fixing bug 850768: + improper flush_cache() in load_serial() + +* Fixing bug 834943: + MPC8540 - missing volatile declarations + +* Patch by Stephen Williams, 09 Feb 2004: + Add support for Xilinx SystemACE chip: + - New files common/cmd_ace.c and include/systemace.h + - Hook systemace support into cmd_fat and the partition manager + +* Patch by Travis Sawyer, 09 Feb 2004: + Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux + +* Patch by Travis Sawyer, 09 Feb 2004: + o 440GX: + - Fix PCI Indirect access for type 1 config cycles with ppc440. + - Add phymode for 440 enet + - fix pci pre init + o XPedite1K: + - Change board_pre_init to board_early_init_f + - Add user flash to bus controller setup + - Fix pci pre init + - Fix is_pci_host to check GPIO for monarch bit + - Force xpedite1k to pci conventional mode (via #define option) + +* Patch by Brad Kemp, 4 Feb 2004: + - handle the machine check that is generated during the PCI scans + on 82xx processors. + - define the registers used in the IMMR by the PCI subsystem. + +* Patch by Pierre Aubert, 03 Feb 2004: + cpu/mpc5xxx/start.S: copy MBAR into SPR311 + +* Patch by Jeff Angielski, 03 Feb 2004: + Fix copy & paste error in cpu/mpc8260/pci.c + +* Patch by Reinhard Meyer, 24 Jan 2004: + Fix typo in cpu/mpc5xxx/pci_mpc5200.c + +* Add Auto-MDIX support for INCA-IP + +* Some code cleanup + +* Patch by Josef Baumgartner, 10 Feb 2004: + Fixes for Coldfire port + +* Patch by Brad Kemp, 11 Feb 2004: + Fix CFI flash driver problems + +* Make sure to use a bus clock divider of 2 only when running TQM8xxM + modules at CPU clock frequencies above 66 MHz. + +* Optimize flash programming speed for LWMON (by another 100% :-) + +* Patch by Jian Zhang, 3 Feb 2004: + - Changed the incorrect FAT12BUFSIZE + - data_begin in fsdata can be negative. Changed it to be short. + +* Patches by Stephan Linz, 30 Jan 2004: + 1: - board/altera/common/flash.c:flash_erase(): + o allow interrupts befor get_timer() call + o check-up each erased sector and avoid unexpected timeouts + - board/altera/dk1c20/dk1s10.c:board_early_init_f(): + o enclose sevenseg_set() in cpp condition + - remove the ASMI configuration for DK1S10_standard_32 (never present) + - fix some typed in mistakes in the NIOS documentation + 2: - split DK1C20 configuration into several header files: + o two new files for each NIOS CPU description + o U-Boot related part is remaining in DK1C20.h + 3: - split DK1S10 configuration into several header files: + o two new files for each NIOS CPU description + o U-Boot related part is remaining in DK1S10.h + 4: - Add support for the Microtronix Linux Development Kit + NIOS CPU configuration at the Altera Nios Development Kit, + Stratix Edition (DK-1S10) + 5: - Add documentation for the Altera Nios Development Kit, + Stratix Edition (DK-1S10) + 6: - Add support for the Nios Serial Peripharel Interface (SPI) + (master only) + 7: - Add support for the common U-Boot SPI framework at + RTC driver DS1306 + +* Patch by Rahul Shanbhag, 28 Jan 2004: + Fix flash protection/locking handling for OMAP1610 innovator board. + +* Patch by Rolf Peukert, 28 Jan 2004: + fix flash write problems on CSB226 board (write with 32 bit bus width) + +* Patches by Mark Jonas, 16 Jan 2004: + - fix rounding error when calculating baudrates for MPC5200 PSCs + - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same + time which is not supported + +* Patch by Yuli Barcohen, 26 Jan 2004: + Allow bzip2 compression for small memory footprint boards + +* Patch by Brad Kemp, 21 Jan 2004: + Add support for CFI flash driver for both the Intel and the AMD + command sets. + +* Patch by Travis Sawyer, 20 Jan 2004: + Fix pci bridge auto enumeration of sibling p2p bridges. + +* Patch by Tolunay Orkun, 12 Jan 2004: + Add some delays as needed for Intel LXT971A PHY support + +* Patches by Stephan Linz, 09 Jan 2004: + - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c + - make DK1C20 board configuration related to ASMI conform to + documentation + +* Patch by Anders Larsen, 09 Jan 2004: + + ARM memory layout fixes: the abort-stack is now set up in the + correct RAM area, and the BSS is zeroed out as it should be. + + Furthermore, the magic variables 'armboot_end' and 'armboot_end_data' + of the linker scripts are replaced by '__bss_start' and '_end', + resp., which is a further step to eliminate unnecessary differences + between the implementation of the CPU architectures. + +* Patch by liang a lei, 9 Jan 2004: + Fix Intel 28F128J3 ID in include/flash.h + +* Patch by Masami Komiya, 09 Jan 2004: + add support for TB0229 board (NEC VR4131 MIPS processor) + +* Patch by Leon Kukovec, 12 Dec 2003: + changed extern __inline__ into static __inline__ in + include/linux/byteorder/swab.h + +* Patch by Travis Sawyer, 30 Dec 2003: + Add support for IBM PPC440GX. Multiple EMAC Ethernet devices, + select MDI port based on enabled EMAC device. + Add support for XES Inc XPedite1000 440GX + base PrPMC board. + +* Patch by Wolter Kamphuis, 15 Dec 2003: + made CONFIG_SILENT_CONSOLE usable on all architectures + +* Disable date command on TQM866M - there is no RTC on MPC866 + +* Fix variable CPU clock for MPC859/866 systems for low CPU clocks + +* Implement adaptive SDRAM timing configuration based on actual CPU + clock frequency for INCA-IP; fix problem with board hanging when + switching from 150MHz to 100MHz + +* Add PCMCIA CS support for BMS2003 board + +* Add variable CPU clock for MPC859/866 systems (so far only TQM866M): + see doc/README.MPC866 for details; + implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866; + calculate CPU clock frequency from PLL register values. + +* Add support for 128 MB RAM on TQM8xxL/M modules + +* Fix PS/2 keyboard problem caused by statically initialized variable + pointing to a location in flash + +* Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130. + +* The PS/2 mux on the BMS2003 board needs 450 ms after power on + before we can access it; add delay in case we are faster (with no + CF card inserted) + +* Cleanup of some init functions + +* Make sure SCC Ethernet is always stopped by the time we boot Linux + to avoid Linux crashes by early packets coming in. + +* Accelerate flash accesses on LWMON board by using buffered writes + +* Fix typo in Makefile; + fix problem with PARTNUM detection + +* Patch by Reinhard Meyer, 09 Jan 2004: + - add RTC support for MPC5200 based boards (requires RTC_XTAL) + +* Add support for IDE LED on BMS2003 board + (exclusive with status LED!) + +* Add support for PS/2 keyboard (used with PS/2 multiplexor on + BMS2003 board) + +* Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004: + Add common files for "emk" boards + +* Add a common get_ram_size() function and modify the the + board-specific files to invoke that common implementation. + +====================================================================== +Changes for U-Boot 1.0.1: +====================================================================== + +* Set default clock for INCA-IP to 150 MHz + +* Make BMS2003 use a separate config file to avoid #ifdef mess; + add I2C support; add support for DS1337 RTC + +* Add CompactFlash support for BMS2003 board + +* Add support for status LED on BMS2003 board + +* Patch by Scott McNutt, 02 Jan 2004: + Add support for the Nios Active Serial Memory Interface (ASMI) + on Cyclone devices + +* Patch by Andrea Marson, 16 Dec 2003: + Add support for the PPChameleon ME and HI modules + +* Patch by Yuli Barcohen, 22 Dec 2003: + Add support for Motorola DUET ADS board (MPC87x/88x) + +* Patch by Robert Schwebel, 15 Dec 2003: + add support for cramfs (uses JFFS2 command interface) + +* Patches by Stephan Linz, 11 Dec 2003: + - more documentation for NIOS port + - new struct nios_pio_t, struct nios_spi_t + - Reconfiguration for NIOS Development Kit DK1C20: + o move board related code from board/dk1c20 + to board/altera/dk1c20 + o create a new common source path board/altera/common + and move generic flash access stuff into it + o change/expand configuration file DK1C20.h + - Add support for NIOS Development Kit DK1S10 + - Add status LED support for NIOS systems + - Add dual 7-segment LED support for Altera NIOS DevKits + +* Patch by Ronen Shitrit, 10 Dec 2003: + Add support for the Marvell DB64360 / DB64460 development boards + +* Patch by Detlev Zundel, 10 Dec 2003: + fix dependency problem in examples/Makefile + +* Patch by Denis Peter, 8 Dec 2003 + - add support for the PATI board (MPC555) + - add SPI support for the MPC5xx + +* Patch by Anders Larsen, 08 Dec 2003: + add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG + to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target; + cleanup some redundand #defines + +* Patch by André Schwarz, 8 Dec 2003: + fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM): + - TX and RX deskriptors must be quad-word aligned + - does not work with only one TX deskriptor + - standard reset method does not work + +* Patch by Masami Komiya, 08 Dec 2003: + add RTL8139 ethernet driver + +* Patches by Ed Okerson, 07 Dec 2003: + - fix ethernet for the AU1x00 processors in little-endian mode. + - extend memsetup.S for the AU1x00 processors in BE and LE modes + +* Minor code cleanup (coding style) + +* Patch by Reinhard Meyer, 30 Dec 2003: + - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE, + - added CONFIG_PHY_ADDR to include/configs/IceCube.h, + - turned debug print of PHY registers into a function (called in two places) + - added support for EMK MPC5200 based modules + +* Fix MPC8xx PLPRCR_MFD_SHIFT typo + +* Add support for TQM866M modules + +* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash) + +* Fix a few compiler warnings + +* Patch by Reinhard Meyer, 28 Dec 2003: + Add initial support for TOP5200 board + +* Make CPU clock on ICA-IP board controllable by a "cpuclk" + environment variable which can set to "100", "133", or "150". The + CPU clock will be configured accordingly upon next reboot. Other + values are ignored. In case of an invalid or undefined "cpuclk" + value, the compile-time default CPU clock speed will be used. + +* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory + window that is used to access the UART registers by the Linux driver) + +* Patch by Reinhard Meyer, 20 Dec 2003: + Fix clock calculation for the MPC5200 for higher clock frequencies + (above 2**32 / 10 = 429.5 MHz). + +* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration + +* Fix IceCube CLKIN configuration (it's 33.000000MHz) + +* Add new configuration for IceCube board with DDR memory + +* Update TRAB memory configurations + +* Add JFFS2 support for INCA-IP board + +* Patch by Bill Hargen, 09 Dec 2003: + - BUBINGA405EP: changed flash driver to protect top sector containing + first instruction. + - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM. + - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access). + - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1). + - 405EP: added/fixed support for "reginfo" command. + - 4xx: removed spurious MII error messages on "mii info" command. + +* Patch by Bernhard Kuhn, 28 Nov 2003: + add support for Coldfire CPU + add support for Motorola M5272C3 and M5282EVB boards + +* Patch by Pierre Aubert, 24 Nov 2003: + - add a return value for the fpga command + - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT + is defined. If ide_preinit fails, ide_init is aborted. + - fix an endianess problem in fat.h + +* Patch by Wolter Kamphuis, 05 Dec 2003: + Add support for SNMC's QS850/QS823/QS860T boards + +* Patch by Yuli Barcohen, 3 Dec 2003: + "revive" U-Boot support for old Motorola MPC860ADS board + +* Patch by Cam(ilo?), 03 Dec 2003: + make examples build even with broken Montavista objcopy + +* Patch by Pavel Bartusek, 27 Nov 2003: + fix conversion problem with "bootretry" evironment variable + +* Patch by Andre Schwarz, 24 Nov 2003: + add support for mvblue (mvBlueLYNX and mvBlueBOX) boards + +* Patch by Pavel Bartusek, 21 Nov 2003: + set ZMII bridge speed on 440 + +* Patch by Anders Larsen, 17 Nov 2003: + Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h + +* Patches by David Müller, 14 Nov 2003: + - board/mpl/common/common_util.c + * implement support for BZIP2 compressed images + * various cleanups (printf -> puts, ...) + - board/mpl/common/flash.c + * report correct errors to upper layers + * check the erase fail and VPP low bits in status reg + - board/mpl/vcma9/cmd_vcma9.c + - board/mpl/vcma9/flash.c + * various cleanups (printf -> puts, ...) + - common/cmd_usb.c + * fix typo in comment + - cpu/arm920t/usb_ohci.c + * support for S3C2410 is missing in #if line + - drivers/cs8900.c + * reinit some registers in case of error (cable missing, ...) + - fs/fat/fat.c + * support for USB/MMC devices is missing in #if line + - include/configs/MIP405.h + - include/configs/PIP405.h + * enable BZIP2 support + * enlarge malloc space to 1MiB because of BZIP2 support + - include/configs/VCMA9.h + * enable BZIP2 support + * enlarge malloc space to 1MiB because of BZIP2 support + * enable USB support + - lib_arm/armlinux.c + * change calling convention of ARM Linux kernel as + described on http://www.arm.linux.org.uk/developer/booting.php + +* Patch by Thomas Lange, 14 Nov 2003: + Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to + support all these AMD boards. + +* Patch by Thomas Lange, 14 Nov 2003: + Workaround for mips au1x00 physical memory accesses (the au1x00 + uses a 36 bit bus internally and cannot access physical memory + directly. Use the uncached SDRAM address instead of the physical + one.) + +* Patch by Xue Ligong (Joe), 13 Nov 2003: + add Realtek 8019 ethernet driver + +* Patch by Yuli Barcohen, 13 Nov 2003: + MPC826xADS/PQ2FADS cleanup + +* Patch by Anders Larsen, 12 Nov 2003: + Update README to mark the PORTIO commands non-standard + +* Patch by Nicolas Lacressonnière, 12 Nov 2003: + update for for Atmel AT91RM9200DK development kit: + - support for environment variables in DataFlash + - Atmel DataFlash AT45DB1282 support + +* Patch by Jeff Carr, 11 Nov 2003: + add support for new version of 8270 processors + +* Patches by George G. Davis, 05 Nov 2003: + - only pass the ARM linux initrd tag to the kernel when an initrd + is actually present + - update omap1510inn configuration file + +* Patches by Stephan Linz, 3 Nov 2003: + - more endianess fixes for LAN91C111 driver + - CFG_HZ configuration patch for NIOS Cyclone board + +* Patch by Stephan Linz, 28 Oct 2003: + fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c + +* Patch by Steven Scholz, 20 Oct 2003: + - make "mii info " show infor for PHY at "addr" only + - Endian fix for miiphy_info() + +* Patch by Gleb Natapov, 19 Sep 2003: + Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c + +* Patch by Anders Larsen, 17 Sep 2003: + Bring ARM memory layout in sync with the documentation: + stack and malloc-heap are now located _below_ the U-Boot code + +* Accelerate booting on TRAB board: read and check autoupdate image + headers first instead of always reading the whole images. + +* Fix type in MPC5XXX code (pointed out by Victor Wren) + +* Enabled password check on RMU board + +* Fix configuration problem with IceCube in LOWBOOT configuration: + envrionment got embedded, corrupting the image layout. + +* Fix NEC display names (it's 6440 [for 640x480], not 6640). + +* Added BMS2003 board + add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display + +* Fix flash driver for TRAB board (must use Unlock Bypass Reset + command to exit Unlock Bypass Mode); adjust timings for flash, SRAM + and CPLD + +* Use "-fPIC" instead of "-mrelocatable" to prevent problems with + recent tools + +* Add checksum verification to 'imls' command + +* Add bd_info fields needed for 4xx Linux I2C driver + +* Patch by Martin Krause, 4 Nov. 2003: + Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap) + +* Print used network interface when CONFIG_NET_MULTI is set + +* Patch by Bernhard Kuhn, 28 Oct 2003: + Add low boot support for MPC5200 + +* Fix problem with dual PCMCIA support (NSCU) + +* Fix MPC5200 I2C initialization function + +====================================================================== +Changes for U-Boot 1.0.0: +====================================================================== + +* Fix parameter passing to standalone images with bootm command + +* Patch by Kyle Harris, 30 Oct 2003: + Fix build errors for ixdp425 board + +* Patch by David M. Horn, 29 Oct 2003: + Fixes to build under CYGWIN + +* Get IceCube MGT5100 working (again) + +* Fix problems in memory test on some boards (which was not + non-destructive as intended) + +* Patch by Gary Jennejohn, 28 Oct 2003: + Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack + to prevent stack overflow on ARM systems + +* Patch by Stephan Linz, 28 Oct 2003: + fix init sequence error for NIOS port + +* Allow lowercase spelling for IceCube_5200; support MPC5200LITE name + +* Add CONFIG_VERSION_VARIABLE to TRAB configuration + +* Patch by Xiao Xianghua, 23 Oct 2003: + small patch for mpc85xx + +* Fix small problem in MPC5200 I2C driver + +* Fix FCC3 support on ATC board + +* Correct header printing for multi-image files in do_bootm() + +* Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED + +* Fix PCI problems on PPChameleon board + +* Patch by Steven Scholz, 18 Oct 2003: + Fix AT91RM9200 ethernet driver + +* Patch by Nye Liu, 17 Oct 2003: + Fix typo in include/mpc8xx.h + +* Patch by Richard Woodruff, 16 Oct 03: + Fixes for cpu/arm925/interrupt.c + - Initialize timestamp & lastdec vars. + - fix timestamp overflows. + - fix lastdec overflow. + - smarter normalization to allow udelay() below 1ms to work. + +* Patch by Scott McNutt, 16 Oct + add networking support for the Altera Nios Development Kit, + Cyclone Edition (DK-1C20) + +* Patch by Jon Diekema, 14 Oct 2003: + add hint about doc/README.silent to README file + +* Add CompactFlash support for NSCU + +* Fix PCI problems on PPChameleonEVB + +* TRAB auto-update: Base decision if we have to strip the image + header on image type as encoded in the header + (include image type patch by Martin Krause, 17 Oct 2003) + +* Patches by Xianghua Xiao, 15 Oct 2003: + + - Added Motorola CPU 8540/8560 support (cpu/85xx) + - Added Motorola MPC8540ADS board support (board/mpc8540ads) + - Added Motorola MPC8560ADS board support (board/mpc8560ads) + +* Fix flash timings on TRAB board + +* Make sure HUSH is initialized for running auto-update scripts + +* Make 5200 reset command _really_ reset the board, without running + any other code after it + +* Fix errors with flash erase when range spans across banks + that are mapped in reverse order + +* Fix flash mapping and display on P3G4 board + +* Patch by Kyle Harris, 15 Jul 2003: + - add support for Intel IXP425 CPU + - add support for IXDP425 eval board + +* Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent + for more information + +* Patch by Steven Scholz, 10 Oct 2003 + - Add support for Altera FPGA ACEX1K + +* Patches by Thomas Lange, 09 Oct 2003: + - fix cmd_ide.c for non ppc boards (read/write functions did not + add ATA base address) + - fix for shannon board + - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code + - Endian swap ATA identity for all big endian CPUs, not just PPC + - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize + args to linux + - add support for dbau1x00 board (MIPS32) + +* Patch by Sangmoon Kim, 07 Oct 2003: + add support for debris board + +* Patch by Martin Krause, 09 Oct 2003: + Fixes for TRAB board + - /board/trab/rs485.c: correct baudrate + - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in + udelay(); fix some timing problems with adc controller + - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power; + modify commands: touch and buzzer + +* Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE + (quick & dirty workaround for rogue pointer problem in get_vfatname()); + Use direct function calls for auto_update instead of hush commands + +* Patch by Scott McNutt, 04 Oct 2003: + - add support for Altera Nios-32 CPU + - add support for Nios Cyclone Development Kit (DK-1C20) + +* Patch by Steven Scholz, 29 Sep 2003: + - A second parameter for bootm overwrites the load address for + "Standalone Application" images. + - bootm sets environment variable "filesize" to the resulting + (uncompressed) data length for "Standalone Application" images + when autostart is set to "no". Now you can do something like + if bootm $fpgadata $some_free_ram ; then + fpga load 0 $some_free_ram $filesize + fi + +* Patch by Denis Peter, 25 Sept 2003: + add support for the MIP405 Rev. C board + +* Patch by Yuli Barcohen, 25 Sep 2003: + add support for Zephyr Engineering ZPC.1900 board + +* Patch by Anders Larsen, 23 Sep 2003: + add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only + implemented for the x86 architecture) + +* Patch by Sangmoon Kim, 23 Sep 2003: + fix pll_pci_to_mem_multiplier table for MPC8245 + +* Patch by Anders Larsen, 22 Sep 2003: + enable timed autoboot on PXA + +* Patch by David Müller, 22 Sep 2003: + - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver + returns correct libgcc file path + - "latency" reduction of busy-loop waiting to improve "U-Boot" boot + time on s3c24x0 systems + +* Patch by Jon Diekema, 19 Sep 2003: + - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet + link state to the fault LED. + - In NetLoop, make the Fault LED reflect the link status. The link + status gets updated on entry, and on timeouts. + +* Patch by Anders Larsen, 18 Sep 2003: + allow mkimage to build and run on Cygwin-hosted systems + +* Patch by Frank Müller, 18 Sep 2003: + use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in + cpu/mpc8xx/fec.c + +* Patch by Pantelis Antoniou, 16 Sep 2003: + add tool to compute fileds in the PLPRCR register for MPC86x + +* Use IH_TYPE_FILESYSTEM for TRAB "disk" images. + +* Fix build problems under FreeBSD + +* Add generic filesystem image type + +* Make fatload set filesize environment variable + +* enable basic / medium / high-end configurations for PPChameleonEVB + board; fix NAND code + +* enable TFTP client code to specify to the server the desired + timeout value (see RFC-2349) + +* Improve SDRAM setup for TRAB board + +* Suppress all output with splashscreen configured only if "splashimage" + is set + +* Fix problems with I2C support for mpc5200 + +* Adapt TRAB configuration and auto_update to new memory layout + +* Add configuration for wtk board + +* Add support for the Sharp LQ065T9DR51U LCD display + +* Patch by Rune Torgersen, 17 Sep 2003: + - Fixes for MPC8266 default config + - Allow eth_loopback_test() on 8260 to use a subset of the FCC's + +* Patches by Jon Diekema, 17 Sep 2003: + - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and + env_common.c) + - sbc8260 tweaks + - adjust "help" output + +* Patches by Anders Larsen, 17 Sep 2003: + - fix spelling errors + - set GD_FLG_DEVINIT flag only after device function pointers + are valid + - Allow CFG_ALT_MEMTEST on systems where address zero isn't + writeable + - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs + - trigger watchdog while waiting in serial driver + +* Add auto-update code for TRAB board using USB memory sticks, + support new configuration with more memory + +* disable MPC5200 bus pipelining as workaround for bus contention + +* Modify XLB arbiter priorities on MPC5200 so all devices use same + priority; configure critical interrupts to be handled like external + interrupts + +* Make IPB clock on MGT5100/MPC5200 configurable in board config file; + go back to 66 MHz for stability + +* Patches by Jon Diekema, 15 Sep 2003: + - add description for missing CFG_CMD_* entries in the README file + - sacsng tweaks + +* Patch by Gleb Natapov, 14 Sep 2003: + enable watchdog support for all MPC824x boards that have a watchdog + +* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the + "Non-octet Aligned Frame" errors we see at 100 Mbps + +* Patch by Sharad Gupta, 14 Sep 2003: + fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL]) + +* Patch by llandre, 11 Sep 2003: + update configuration for PPChameleonEVB board + +* Patch by David Müller, 13 Sep 2003: + various changes to VCMA9 board specific files + +* Add I2C support for MGT5100 / MPC5200 + +* Patch by Rune Torgersen, 11 Sep 2003: + Changed default memory option on MPC8266ADS to NOT be Page Based + Interleave, since this doesn't work very well with the standard + 16MB DIMM + +* Patch by George G. Davis, 12 Sep 2003: + fix Makefile settings for sk98 driver + +* Patch by Stefan Roese, 12 Sep 2003: + - new boards added: DP405, HUB405, PLU405, VOH405 + - some esd boards updated + - cpu/ppc4xx/sdram.c: disable memory controller before setting + first values + - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems + +* Patch by Martin Krause, 11 Sep 2003: + add burn-in tests for TRAB board + +* Enable instruction cache on MPC5200 board + +* Patch by Denis Peter, 11 Sep 2003: + - fix USB data pointer assignment for bulk only transfer. + - prevent to display erased directories in FAT filesystem. + +* Change output format for NAND flash - make it look like for other + memory, too + +====================================================================== +Changes for U-Boot 0.4.8: +====================================================================== + +* Add I2C and RTC support for RMU board + +* Patches by Denis Peter, 9 Sep 2003: + add FAT support for IDE, SCSI and USB + +* Patches by Gleb Natapov, 2 Sep 2003: + - cleanup of POST code for unsupported architectures + - MPC824x locks way0 of data cache for use as initial RAM; + this patch unlocks it after relocation to RAM and invalidates + the locked entries. + +* Patch by Gleb Natapov, 30 Aug 2003: + new I2C driver for mpc107 bridge. Now works from flash. + +* Patch by Dave Ellis, 11 Aug 2003: + - JFFS2: fix typo in common/cmd_jffs2.c + - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option + - JFFS2: remove node version 0 warning + - JFFS2: accept JFFS2 PADDING nodes + - SXNI855T: add AM29LV800 support + - SXNI855T: move environment from EEPROM to flash + - SXNI855T: boot from JFFS2 in NOR or NAND flash + +* Patch by Bill Hargen, 11 Aug 2003: + fixes for I2C on MPC8240 + - fix i2c_write routine + - fix iprobe command + - eliminates use of global variables, plus dead code, cleanup. + +* Add support for USB Mass Storage Devices (BBB) + (tested with USB memory sticks only) + +* Avoid flicker on TRAB's VFD + +* Add support for SK98xx driver + +* Add PCI support for SL8245 board + +* Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB) + or 1 x AM29LV652 (two LV065 in one chip = 16 MB); + Run IPB at 133 Mhz; adjust the MII clock frequency accordingly + +* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz) + to allow for more accurate baudrate settings + (error now 0.7% at 115 kbps, instead of 3.5% before) + +* Patch by Andreas Mohr, 4 Sep 2003: + Fix a lot of spelling errors + +* Add support for PPChameleon Eval Board + +* Add support for P3G4 board + +* Fix problem with MGT5100 FEC driver: add "early" MAC address + initialization + +* Patch by Yuli Barcohen, 7 Aug 2003: + check BCSR to detect if the board is configured in PCI mode + +====================================================================== +Changes for U-Boot 0.4.7: +====================================================================== + +* Patch by Raghu Krishnaprasad, 7 Aug 2003: + add support for Adder II MPC852T module + +* Patch by George G. Davis, 19 Aug 2003: + fix TI Innovator/OMAP1510 pin configs + +* Patches by Kshitij, 18 Aug 2003 + - add support for arm926ejs cpu core + - add support for TI OMAP 1610 Innovator Board + +* Patch by Yuli Barcohen, 14 Aug 2003: + add support for bzip2 uncompression + +* Add GCC library to examples/Makefile so GCC utility functions will + be resolved, too + +* Add I2C and RTC support for RMU board using software I2C driver + (because of better response to iprobe command); fix problem with + "reset" command + +* Patch by Matthias Fuchs, 28 Aug 2003: + Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to + CONFIG_BOOTP_MAKS (see README). + +* Fix ICU862 environment problem + +* Fix RAM size detection for RMU board + +* Implement "reset" for MGT5100/MPC5200 systems + +====================================================================== +Changes for U-Boot 0.4.6: +====================================================================== + +* Make Ethernet autonegotiation on INCA-IP work for all clock rates; + allow selection of clock frequency as "make" target + +* Implement memory autosizing code for IceCube boards + +* Configure network port on INCA-IP for autonegotiation + +* Fix overflow problem in network timeout code + +* Patch by Richard Woodruff, 8 Aug 2003: + Allow crc32 to be used at address 0x000 (crc32_no_comp, too). + +====================================================================== +Changes for U-Boot 0.4.5: +====================================================================== + +* Update for TQM board defaults: + disable clocks_in_mhz, enable boot count limit + +* Removed tools/gdb from "make all" target. Added make target "gdbtools" + in toplevel directory instead. Removed astest.c from tools/gdb because + it is no longer relevant. + +* Fix PCI support for MPC5200 / IceCube Board + +* Map ISP1362 USB OTG controller for NSCU board + +* Patch by Brad Parker, 02 Aug 2003: + fix sc520_cdp problems + +* Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements) + +* Allow erase command to cross flash bank boundaries + +* Patch by Scott McNutt, 21 Jul 2003: + Add support for LynuxWorks Kernel Downloadable Images (KDIs). + Both LynxOS and BlueCat linux KDIs are supported. + +* Patch by Richard Woodruff, 25 Jul 2003: + use more reliable reset for OMAP/925T + +* Patch by Nye Liu, 25 Jul 2003: + fix typo in mpc8xx.h + +* Patch by Richard Woodruff, 24 Jul 2003: + Fixes for cmd_nand.c: + - Fixed null dereferece which could result in incorrect ECC values. + - Added support for devices with no Ready/Busy signal hooked up. + - Added OMAP1510 read/write protect handling. + - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock + for non-JFFS2. + - Switched default ECC to be JFFS2. + +* Allow crc32 to be used at address 0x000 + +* Provide consistent interface to standalone applications to access + the 'global_data' structure + Provide a doc/README.standalone more useful to users/developers. + +* Make IceCube MGT5100 FEC driver work + +* Implement new mechanism to export U-Boot's functions to standalone + applications: instead of using (PPC-specific) system calls we now + use a jump table; please see doc/README.standalone for details + +* Patch by Dave Westwood, 24 Jul 2003: + added support for Unity OS (a proprietary OS) + +* Patch by Detlev Zundel, 23 Jul 2003: + add "imls" command to print flash table of contents + +* Fix cold boot detection for log buffer reset + +* Return error for invalid length specifiers with "cp.X" etc. + +* Fix startup problem on MIPS + +* Allow for CONFIG_SPLASH_SCREEN even when no explicit + bitmap support is configured + +* Patch by Bill Hargen, 18 Jul 2003: + - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c + +* Patch by Denis Peter, 18 Jul 2003: + - fix memory configuration for MIP405T + - fix printout of baudrate for "loadb " + +* Cleanup of TQM82xx configurations; use "official" board types + to make selection easier. + +* Patch by Martin Krause, 17 Jul 2003: + add delay to get I2C working with "imm" command and s3c24x0_i2c.c + +* Patch by Richard Woodruff, 17 July 03: + - Fixed bug in OMAP1510 baud rate divisor settings. + +* Patch by Nye Liu, 16 July 2003: + MPC860FADS fixes: + - add MPC86xADS support (uses MPC86xADS.h) + - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T) + o PLPRCR changes + o BRG changes (EXTAL/XTAL restricted to 10MHz) + o don't trust gclk() software measurement by default, depend on + CONFIG_8xx_GCLK_FREQ + - add DRAM SIMM not installed detection + - use more "correct" SDRAM initialization sequence + - allow different SDRAM sizes (8xxADS has 8M) + - default DER is 0 + - remove unused MAMR defines from FADS860T.h (all done in fads.c) + - rename MAMR/MBMR defines to be more consistent. Should eventually + be merged into MxMR to better reflect the PowerQUICC datasheet. + +* Patch by Yuli Barcohen, 16 Jul 2003: + support new Motorola PQ2FADS-ZU evaluation board which replaced + MPC8260ADS and MPC8266ADS + +====================================================================== +Changes for U-Boot 0.4.4: +====================================================================== + +* Add support for IceCube board (with MGT5100 and MPC5200 CPUs) + +* Add support for MGT5100 and MPC5200 processors + +* Patch by Lutz Dennig, 15 Jul 2003: + update for R360MPI board + +====================================================================== +Changes for U-Boot 0.4.3: +====================================================================== + +* Patches by Kshitij, 04 Jul 2003 + - added support for arm925t cpu core + - added support for TI OMAP 1510 Innovator Board + +* Patches by Martin Krause, 14 Jul 2003: + - add I2C support for s3c2400 systems (trab board) + - (re-) add "ping" to command table + +* Fix handling of "slow" POST routines + +* Patches by Yuli Barcohen, 13 Jul 2003: + - Correct flash and JFFS2 support for MPC8260ADS + - fix PVR values and clock generation for PowerQUICC II family + (8270/8275/8280) + +* Patch by Bernhard Kuhn, 08 Jul 2003: + - add support for M68K targets + +* Patch by Ken Chou, 3 Jul: + - Fix PCI config table for A3000 + - Fix iobase for natsemi.c + (PCI_BASE_ADDRESS_0 is the IO base register for DP83815) + +* Allow to enable "slow" POST routines by key press on power-on +* Fix temperature dependend switching of LCD backlight on LWMON +* Tweak output format for LWMON + +* Patch by Stefan Roese, 11 Jul 2003: + - Fix bug in CONFIG_VERSION_VARIABLE. + - AR405 config updated. + - OCRTC/ORSG: bsp command added. + - ASH405 bsp update. + +====================================================================== +Changes for U-Boot 0.4.2: +====================================================================== + +* Add support for NSCU board + +* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules + +* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML + mirror bit flash on TQM8xxM modules + +* Patch by Kenneth Johansson, 30 Jun 2003: + get rid of MK_CMD_ENTRY macro; update doc/README.command + +* Patch by Seb James, 30 Jun 2003: + Improve documentation of I2C configuration in README + +* Fix problems with previous log buffer "fixes" + +* Fix minor help text issues + +* "log append" did not append a newline + +====================================================================== +Changes for U-Boot 0.4.1: +====================================================================== + +* Fix some missing commands, cleanup header files + (autoscript, bmp, bsp, fat, mmc, nand, portio, ...) + +* Rewrite command lookup and help command (fix problems with bubble + sort when sorting command name list). Minor cleanup here and there. + +* Merge from "stable branch", tag LABEL_2003_06_28_1800-stable: + - Allow to call sysmon function interactively + - PIC on LWMON board needs delay after power-on + - Add missing RSR definitions for MPC8xx + - Improve log buffer handling: guarantee clean reset after power-on + - Add support for EXBITGEN board (aka "genie") + - Add support for SL8245 board + +* Code cleanup: + - remove trailing white space, trailing empty lines, C++ comments, etc. + - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) + +* Patches by Kenneth Johansson, 25 Jun 2003: + - major rework of command structure + (work done mostly by Michal Cendrowski and Joakim Kristiansen) + +====================================================================== +Changes for U-Boot 0.4.0: +====================================================================== + +* Patches by Robert Schwebel, 26 Jun 2003: + - csb226 configuration updated + - credits for logodl port updated + - innokom configuration updated + - logodl tree update, still with coding style inconsistencies + - added OCM for ppc405 warning to README + +* Patch by Pantelis Antoniou, 25 Jun 2003: + update NetVia with V2 board support + +* Header file cleanup for ARM + +* Patch by Murray Jensen, 24 Jun 2003: + - make sure to use only U-boot provided header files + - fix problems with ".rodata.str1.4" section as used by GCC-3.x + +* Patch by Stefan Roese, 24 Jun 2003: + - Update esd ASH405 board files. + - Update esd DASA_SIM config file. + - Add ping command to some esd boards. + +* Patch by Yuli Barcohen, 23 Jun 2003: + Update for MPC8260ADS board + +* Patch by Murray Jensen, 23 Jun 2003: + - cleanup of GCC 3.x compiler warnings + +* Patch by Rune Torgersen, 4 Jun 2003: + add large memory support for MPC8266ADS board + +* Patch by Richard Woodruff, 19 June 03: + - Enabled standard u-boot device abstraction for ARM + - Enabled console device for ARM + - Initilized bi_baudrate for ARM + +* Patch by Bill Hargen, 23 Apr 2003: + fix byte order for 824x I2C addresses (write op) + +* Patch by Murray Jensen, 20 Jun 2003: + - hymod update + - cleanup (especially for gcc-3.x compilers) + +* Patch by Tom Guilliams, 20 Jun 2003: + added CONFIG_750FX support for IBM 750FX processors + +* Patch by Devin Crumb, 02 Apr 2003: + Fix clock divider rounding problem in drivers/serial.c + +* Patch by Richard Woodruff, 19 June 03: + - Fixed smc91c111 driver to sync with the u-boot environment + (driver/smc91c111.c). + - Added eth_init error return check in NetLoop (net/net.c). + +* Patch by Ken Chou, 19 June 2003: + Added support for A3000 SBC board (Artis Microsystems Inc.) + +* Patches by Murray Jensen, 17 Jun 2003: + - Hymod board database mods: add "who" field and new xilinx chip types + - provide new "init_cmd_timeout()" function so code external to + "common/main.c" can use the "reset_cmd_timeout()" function before + entering the main loop + - add DTT support for adm1021 (new file dtt/adm1021.c; config + slightly different. see include/configs/hymod.h for an example + (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and + CFG_DTT_ADM1021 defined) + - add new "eeprom_probe()" function which has similar args and + behaves in a similar way to "eeprom_read()" etc. + - add 8260 FCC ethernet loopback code (new "eth_loopback_test()" + function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST) + - gdbtools copyright update + - ensure that set_msr() executes the "sync" and "isync" instructions + after the "mtmsr" instruction in cpu/mpc8260/interrupts.c + - 8260 I/O ports fix: Open Drain should be set last when configuring + - add SIU IRQ defines for 8260 + - allow LDSCRIPT override and OBJCFLAGS initialization: change to + config.mk to allow board configurations to override the GNU + linker script, selected via the LDSCRIPT, make variable, and to + give an initial value to the OBJCFLAGS make variable + - 8260 i2c enhancement: + o correctly extends the timeout depending on the size of all + queued messages for both transmit and receive + o will not continue with receive if transmit times out + o ensures that the error callback is done for all queued tx + and rx messages + o correctly detects both tx and rx timeouts, only delivers one to + the callback, and does not overwrite an earlier error + o logic in i2c_probe now correct + - add "vprintf()" function so that "panic()" function can be + technically correct + - many Hymod board changes + +* Patches by Robert Schwebel, 14 Jun 2003: + - add support for Logotronic DL datalogger board + - cleanup serial line after kermit binary download + - add debugX macro (debug level support) + - update mach-types.h to latest arm.linux.org.uk master list. + +* Patches by David Müller, 12 Jun 2003: + - rewrite of the S3C24X0 register definitions stuff + - "driver" for the built-in S3C24X0 RTC + +* Patches by Yuli Barcohen, 12 Jun 2003: + - Add MII support and Ethernet PHY initialization for MPC8260ADS board + - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset + configuration word supplied by FPGA on some MPC8260ADS boards + +* Patch by Pantelis Antoniou, 10 Jun 2003: + Unify status LED interface + +* Add support for DS12887 RTC; add RTC support for ATC board + +* Patch by Nicolas Lacressonniere, 11 Jun 2003: + Modifications for Atmel AT91RM9200DK ARM920T based development kit + - Add Atmel DataFlash support for reading and writing. + - Add possibility to boot a Linux from DataFlash with BOOTM command. + - Add Flash detection on Atmel AT91RM9200DK + (between Atmel AT49BV1614 and AT49BV1614A flashes) + - Replace old Ethernet PHY layer functions + - Change link address + +* Patch by Frank Smith, 9 Jun 2003: + use CRIT_EXCEPTION for machine check on 4xx + +* Patch by Detlev Zundel, 13 Jun 2003: + added implementation of the "carinfo" command in cmd_immap.c + +* Fix CONFIG_NET_MULTI support in include/net.h + +* Patches by Kyle Harris, 13 Mar 2003: + - Add FAT partition support + - Add command support for FAT + - Add command support for MMC + ---- + - Add Intel PXA support for video + - Add Intel PXA support for MMC + ---- + - Enable MMC and FAT for lubbock board + - Other misc changes for lubbock board + +* Patch by Robert Schwebel, April 02, 2003: + fix for SMSC91111 driver + +* Patch by Vladimir Gurevich, 04 Jun 2003: + make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option + +* Patch by Stefan Roese, 05 Jun 2003: + - PPC4xx: Fix bug for initial stack in data cache as pointed out by + Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in + data cache can be used even if the chip select is in use. + - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count + (see README for further description). + - Changed config files of CONFIG_EEPRO100 boards to use the + CFG_RX_ETH_BUFFER define. + +* Add support for RMU board + +* Add support for TQM862L at 100/50 MHz + +* Patch by Pantelis Antoniou, 02 Jun 2003: + major reconstruction of networking code; + add "ping" support (outgoing only!) + +* Patch by Denis Peter, 04 June 2003: + add support for the MIP405T board + +* Patches by Udi Finkelstein, 2 June 2003: + - Added support for custom keyboards, initialized by defining a + board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD . + - Added support for the RBC823 board. + - cpu/mpc8xx/lcd.c now automatically calculates the + Horizontal Pixel Count field. + +* Fix alignment problem in BOOTP (dhcp_leasetime option) + [pointed out by Nicolas Lacressonnière, 2 Jun 2003] + +* Patch by Mark Rakes, 14 May 2003: + add support for Intel e1000 gig cards. + +* Patch by Nye Liu, 3 Jun 2003: + fix critical typo in MAMR definition (include/mpc8xx.h) + +* Fix requirement to align U-Boot image on 16 kB boundaries on PPC. + +* Patch by Klaus Heydeck, 2 Jun 2003 + Minor changes for KUP4K configuration + +* Patch by Marc Singer, 29 May 2003: + Fixed rarp boot method for IA32 and other little-endian CPUs. + +* Patch by Marc Singer, 28 May 2003: + Added port I/O commands. + +* Patch by Matthew McClintock, 28 May 2003 + - cpu/mpc824x/start.S: fix relocation code when booting from RAM + - minor patches for utx8245 + +* Patch by Daniel Engström, 28 May 2003: + x86 update + +* Patch by Dave Ellis, 9 May 2003 + 27 May 2003: + add nand flash support to SXNI855T configuration + fix/extend nand flash support: + - fix 'nand erase' command so does not erase bad blocks + - fix 'nand write' command so does not write to bad blocks + - fix nand_probe() so handles no flash detected properly + - add doc/README.nand + - add .jffs2 and .oob options to nand read/write + - add 'nand bad' command to list bad blocks + - add 'clean' option to 'nand erase' to write JFFS2 clean markers + - make NAND read/write faster + +* Patch by Rune Torgersen, 23 May 2003: + Update for MPC8266ADS board + +* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length + instead CFG_MONITOR_LEN is now only used to determine _at_compile_ + _time_ (!) if the environment is embedded within the U-Boot image, + or in a separate flash sector. + +* Cleanup CFG_DER #defines in config files (wd maintained only) + +* Fix data abort exception handling for arm920t CPU + +* Fix alignment problems with flash driver for TRAB board + +* Patch by Donald White, 21 May 2003: + fix calculation of base address in pci_hose_config_device() + +* Fix bug in command line parsing: "cmd1;cmd2" is supposed to always + execute "cmd2", even if "cmd1" fails. Note that this is different + to "run var1 var2" where the contents of "var2" will NOT be + executed when a command in "var1" fails. + +* Add zero-copy ramdisk support (requires corresponding kernel support!) + +* Patch by Kyle Harris, 20 May 2003: + In preparation for an ixp port, rename cpu/xscale and arch-xscale + into cpu/pxa and arch-pxa. + +* Patch by Stefan Roese, 23 May 2003: + - IBM PPC405EP port added. + - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not + UART0) is used as default U-Boot console. PPC4xx only! + - esd ASH405 board added (PPC405EP based). + - BUBINGA405EP board added (PPC405EP based - IBM Eval Board). + - esd CPCI405AB board added. + - esd PMC405 board added. + - Update of some esd boards. + +* Patch by Denis Peter, 19 Mai 2003: + add support for the MIP405-3 board + +* Patch by Dave Ellis, 22 May 2003: + Fix problem with only partially cleared .bss segment + +* Patch by Rune Torgersen, 12 May 2003: + get PCI to work on a MPC8266ADS board; incorporate change to + cpu/mpc8260/pci.c to enable overrides of PCI memory parameters + +* Patch by Nye Liu, 1 May 2003: + minor patches for the FADS8xx + +* Patch by Thomas Schäfer, 28 Apr 2003: + Fix SPD handling for 256 ECC DIMM on Walnut + +* Add support for arbitrary bitmaps for TRAB's VFD command; + allow to pass boot bitmap addresses in environment variables; + allow for zero boot delay + +* Patch by Christian Geißinger, 19 May 2002: + On TRAB: wait until the dummy byte has been completely sent + +* Patch by David Updegraff, 22 Apr 2003: + update for CrayL1 board + +* Patch by Pantelis Antoniou, 21 Apr 2003: + add boot support for ARTOS (a proprietary OS) + +* Patch by Steven Scholz, 11 Apr 2003: + Add support for RTC DS1338 + +* Patch by Rod Boyce, 24 Jan 2003: + Fix counting of extended partitions in diskboot command + +* Patch by Christophe Lindheimer, 20 May 2003: + allow the use of CFG_LOADS when CFG_NO_FLASH is set + +* Fix SDRAM timing on Purple board + +* Add support for CompactFlash on ATC board + (includes support for Intel 82365 and compatible PC Card controllers, + and Yenta-compatible PCI-to-CardBus controllers) + +* Patch by Mathijs Haarman, 08 May 2003: + Add lan91c96 driver (tested on Lubbock and custom PXA250 board only) + +* Fix problem with usage of "true" (undefined in current versions of bfd.h) + +* Add support for Promess ATC board + +* Patch by Keith Outwater, 28 Apr 2003: + - Miscellaneous corrections and additions to GEN860T board specific code. + - Added GEN860_SC variant to GEN860T. + - Miscellaneous corrections to GEN860T documentation. + - Correct duplicate entry in U-Boot CREDITS file. + - Add GEN860T_SC entry in MAINTAINERS file. + - Update CREDITS file with GEN860T_SC info. + +* Update Smiths Aerospace addresses in MAINTAINERS file + +* Fix error handling in hush's version of "run" command + +* LWMON extensions: + - Splashscreen support + - modem support + - sysmon support + - temperature dependend enabling of LCD + +* Allow booting from old "PPCBoot" disk partitions + +* Add support for TQM8255 Board / MPC8255 CPU + +====================================================================== +Changes for U-Boot 0.3.1: +====================================================================== + +* Make sure Block Lock Bits get cleared in R360MPI flash driver + +* MPC823 LCD driver: Fill color map backwards, to allow for steady + display when Linux takes over + +* Patch by Erwin Rol, 27 Feb 2003: + Add support for RTEMS (this time for real). + +* Add support for "bmp info" and "bmp display" commands to load + bitmap images; this can be used (for example in a "preboot" + command) to display a splash screen very quickly after poweron. + +* Add support for 133 MHz clock on INCA-IP board + +* Patch by Lutz Dennig, 10 Apr 2003: + Update for R360MPI board + +* Add new meaning to "autostart" environment variable: + If set to "no", a standalone image passed to the + "bootm" command will be copied to the load address + (and eventually uncompressed), but NOT be started. + This can be used to load and uncompress arbitrary + data. + +* Patch by Stefan Roese, 10 Apr 2003: + Changed DHCP client to use IP address from server option field #54 + from the OFFER packet in the server option field #54 in the REQUEST + packet. This fixes a problem using a Windows 2000 DHCP server, + where the DHCP-server is not the TFTP-server. + +* Set max brightness for MN11236 displays on TRAB board + +* Add support for TQM862L modules + +====================================================================== +Changes for U-Boot 0.3.0: +====================================================================== + +* Patch by Arun Dharankar, 4 Apr 2003: + Add IDMA example code (tested on 8260 only) + +* Add support for Purple Board (MIPS64 5Kc) + +* Add support for MIPS64 5Kc CPUs + +* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS + +* Patch by Denis Peter, 04 Apr 2003: + - update MIP405-4 board + +* Patch by Stefan Roese, 4 Apr 2003: + - U-Boot version environment variable "ver" added + (CONFIG_VERSION_VARIABLE). + - Changed PPC405GPr version from A to B. + - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1. + +* Patches by Denis Peter, 03 April 2003: + - fix PCI IRQs on MPL boards + - fix two more un-relocated pointer problems + +* Fix behaviour of "run" command: + - print error message iv variable does not exist + - terminate processing of arguments in case of error + +* Patches by Peter Figuli, 10 Mar 2003 + - Add support for BTUART on PXA platform + - Add support for WEP EP250 (PXA) board + +* Fix flash problems on INCA-IP; add tool to allow bruning images to + flash using a BDI2000 + +* Implement fix for I2C Edge Conditions problem for all boards that + use the bit-banging driver (common/soft_i2c.c) + +* Patch by Martin Winistoerfer, 23 Mar 2003 + - Add port to MPC555/556 microcontrollers + - Add support for cmi customer board with + Intel 28F128J3A, 28F320J3A or 28F640J3A flash. + +* Patch by Rick Bronson, 28 Mar 2003: + - fix common/cmd_nand.c + +* Patch by Arun Dharankar, 24 Mar 2003: + - add threads / scheduler example code + +* Add patches by Robert Schwebel, 31 Mar 2003: + - add ctrl-c support for kermit download + - align bdinfo output on ARM + - csb226 board: bring in sync with innokom/memsetup.S + - csb226 board: fix MDREFR handling + - misc doc fixes / extensions + - innokom board: cleanup, MDREFR fix in memsetup.S, config update + - add BOOT_PROGRESS to armlinux.c + +* Add CPU ID, version, and clock speed for INCA-IP + +* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board: + - fix SRAM and SDRAM memory sizing + - add status LED support + - add MAC address for second (SCC1) ethernet port + +* Update default environment for TQM8260 board + +* Patch by Rick Bronson, 16 Mar 2003: + - Add NAND flash support for reading, writing, and erasing NAND + flash (certain forms of which are called SmartMedia). + - Add support for Atmel AT91RM9200DK ARM920T based development kit. + +* Patches by Robert Schwebel, 19 Mar 2003: + - use arm-linux-gcc as default compiler for ARM + - fix i2c fixup code + - fix missing baudrate setting + - added $loadaddr / CFG_LOAD_ADDR support to loadb + - moved "ignoring trailing characters" _before_ u-boot wants to + print out diagnostics messages; removes bogus characters at the + end of transmission + +* Patch by John Zhan, 18 Mar 2003: + Add support for SinoVee Microsystems SC8xx boards + +* Patch by Rolf Offermanns, 21 Mar 2003: + ported the dnp1110 related changes from the current armboot cvs to + current u-boot cvs. smc91111 does not work. problem marked in + smc91111.c, grep for "FIXME". + +* Patch by Brian Auld, 25 Mar 2003: + Add support for STM flash chips on ebony board + +* Add PCI support for MPC8250 Boards (PM825 module) + +* Patch by Stefan Roese, 25 Mar 2003: + - PCI405 update. + +* Patch by Stefan Roese, 20 Mar 2003: + - CPCI4052 update (support for revision 3). + - Set edge conditioning circuitry on PPC405GPr for compatibility + to existing PPC405GP designs. + - Clip udiv to 5 bits on PPC405 (serial.c). + +* Extend INCAIP board support: + - add automatic RAM size detection + - add "bdinfo" command + - pass flash address and size to Linux kernel + - switch to 150 MHz clock + +* Avoid flicker on the TRAB's VFD by synchronizing the enable with + the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100 + boards, version 153 for Rev. 200 boards). + +* Patch by Vladimir Gurevich, 12 Mar 2003: + Fix relocation problem of statically initialized string pointers + in common/cmd_pci.c + +* Patch by Kai-Uwe Blöm, 12 Mar 2003: + Cleanup & bug fixes for JFFS2 code: + - the memory mangement was broken. It caused havoc on malloc by + writing beyond the block boundaries. + - the length calculation for files was wrong, sometimes resulting + in short file reads. + - data copying now optionally takes fragment version numbers into + account, to avoid copying from older data. + See doc/README.JFFS2 for details. + +* Patch by Josef Wagner, 12 Mar 2003: + - 16/32 MB and 50/80 MHz support with auto-detection for IP860 + - ETH05 and BEDBUG support for CU824 + - added support for MicroSys CPC45 + - new BOOTROM/FLASH0 and DOC base for PM826 + +* Patch by Robert Schwebel, 12 Mar 2003: + Fix the chpart command on innokom board + +* Name cleanup: + mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h + s/PPCBoot/U-Boot/ in some files + s/pImage/uImage/ in some files + +* Patch by Detlev Zundel, 15 Jan 2003: + Fix '' command line quoting + +* Patch by The LEOX team, 19 Jan 2003: + - add support for the ELPT860 board + - add support for Dallas ds164x RTC + +* Patches by David Müller, 31 Jan 2003: + - minimal setup for CardBus bridges + - add EEPROM read/write support in the CS8900 driver + - add support for the builtin I2C controller in the Samsung s3c24x0 chips + - add support for MPL's VCMA9 (Samsung s3c2410 based) board + +* Patch by Steven Scholz, 04 Feb 2003: + add support for RTC DS1307 + +* Patch by Reinhard Meyer, 5 Feb 2003: + fix PLPRCR/SCCR init sequence on 8xx to allow for + changes of EBDF by software + +* Patch by Vladimir Gurevich, 07 Feb 2003: + "API-compatibility patch" for 4xx I2C driver + +* TRAB fixes / extensions: + - Restore VFD brightness as saved in environment + - add support for Fujitsu flashes + - make sure both buzzers are turned off (drive low level) + +* Patches by Robert Schwebel, 06 Mar 2003: + - fix bug in BOOTP code (must use NetCopyIP) + - update of CSB226 port + - clear BSS segment on XScale + - added support for i2c_init_board() function + - update to the Innokom plattform + +* Extend support for redundand environments for configurations where + environment size < sector size + +* Patch by Rune Torgersen, 13 Feb 2003: + Add support for Motorola MPC8266ADS board + +* Patch by Kyle Harris, 19 Feb 2003: + patches for the Intel lubbock board: + memsetup.S - general cleanup (based on Robert's csb226 code) + flash.c - overhaul, actually works now + lubbock.c - fix init funcs to return proper value + +* Patch by Kenneth Johansson, 26 Feb 2003: + - Fixed off by one in RFTA calculation. + - No need to abort when LDF is lower than we can program it's only + minimum timing so clamp it to what we can do. + - Takes function pointer to function for reading the spd_nvram. Usefull + for faking data or hardcode a module without the nvram. + - fix other user for above change + - fix some comments. + +* Patches by Brian Waite, 26 Feb 2003: + - fix port for evb64260 board + - fix PCI for evb64260 board + - fix PCI scan + +* Patch by Reinhard Meyer, 1 Mar 2003: + Add support for EMK TOP860 Module + +* Patch by Yuli Barcohen, 02 Mar 2003: + Add SPD EEPROM support for MPC8260ADS board + +* Patch by Robert Schwebel, 21 Jan 2003: + - Add support for Innokom board + - Don't complain if "install" fails + - README cleanup (remove duplicated lines) + - Update PXA header files + +* Add documentation for existing POST code (doc/README.POST) + +* Patch by Laudney Ren, 15 Jan 2003: + Fix handling of redundand environment in "tools/envcrc.c" + +* Patch by Detlev Zundel, 28 Feb 2003: + Add bedbug support for 824x systems + +* Add support for 16 MB flash configuration of TRAB board + +* Patch by Erwin Rol, 27 Feb 2003: + Add support for RTEMS + +* Add image information to README + +* Patch by Stefan Roese, 18 Feb 2003: + CPCIISER4 configuration updated. + +* Patch by Stefan Roese, 17 Feb 2003: + Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port). + +* Patch by Stefan Roese, 13 Feb 2003: + Add "pcidelay" environment variable (in ms, enabled via + CONFIG_PCI_BOOTDELAY). + PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after + RST# to respond to configuration cycles (33MHz -> 1s). + +* Fix dual PCMCIA slot support (when running with just one + slot populated) + +* Add VFD type detection to trab board + +* extend drivers/cs8900.c driver to synchronize ethaddr environment + variable with value in the EEPROM + +* Patch by Stefan Roese, 10 Feb 2003: + Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c) + +* Add support for MIPS32 4Kc CPUs + +* Add support for INCA-IP Board + +====================================================================== +Changes for U-Boot 0.2.2: +====================================================================== + +* Add dual ethernet support on PM826 + +* Add support for LXT971 PHY on PM826 + +* Patch by Tord Andersson, 16 Jan 2003: + Fix flash sector count for TQM8xxL + +* Fix I2C EEPROM problem on ICU862 board (would only write the first + 16 bytes out of each 32 byte block) + +====================================================================== +Changes for U-Boot 0.2.1: +====================================================================== + +* Add support for V37 board + (patch by Jón Benediktsson, 11 Dec 2002) + +* Update baudrate in bd_info when it gets changed + +* Add watchdog trigger points while waiting for serial port + (so far only 8xx -- needed on LWMON with 100ms watchdog) + +* Improve command line tool to access the U-Boot's environment + (figuration of the utility, using a config file) + +* Add single quote support for (old) command line parser + +* Switch LWMON board default config from FRAM to EEPROM; + in POST, EEPROM shows up on 8 addresses + +====================================================================== +Changes for U-Boot 0.2.0: +====================================================================== + +* Use 1-byte-read instead of -write for iprobe() function + Add i2c commands to PM826 config + +* extend I2C POST code: check for list on known addresses + +* Improve log buffer code; use "loglevel" to decide which messages + to log on the console, too (like in Linux); get rid of "logstart" + +* Add command line tool to access the U-Boot's environment + (board-specific for TRAB now, to be fixed later) + +* Patch by Hans-Joerg Frieden, 06 Dec 2002 + Fix misc problems with AmigaOne support + +* Patch by Chris Hallinan, 3 Dec 2002: + minor cleanup to the MPC8245 EPIC driver + +* Patch by Pierre Aubert , 28 Nov 2002 + Add support for external (SIU) interrupts on MPC8xx + +* Patch by Pierre Aubert , 28 Nov 2002 + Fix nested syscalls bug in standalone applications + +* Patch by David Müller, 27 Nov 2002: + fix output of "pciinfo" command for CardBus bridge devices. + +* Fix bug in TQM8260 board detection - boards got stuck when board ID + was not readable + +* Add LED indication for IDE activity on KUP4K board + +* Fix startup problems with VFD display on TRAB + +* Patch by Pierre Aubert, 20 Nov 2002 + Add driver for Epson SED13806 graphic controller. + Add support for BMP logos in cfb_console driver. + +* Added support for both PCMCIA slots (at the same time!) on MPC8xx + +* Patch by Rod Boyce, 21 Nov 2002: + fix PCMCIA on MBX8xx board + +* Patch by Pierre Aubert , 21 Nov 2002 + Add CFG_CPM_POST_WORD_ADDR to make the offset of the + bootmode word in DPRAM configurable + +* Patch by Daniel Engström, 18 Nov 2002: + Fixes for x86 port (mostly strings issues) + +* Patch by Ken Chou, 18 Nov 2002: + Fix for natsemi NIC cards (DP83815) + +* Patch by Pierre Aubert, 19 Nov 2002: + fix a bug for the MII configuration, and some warnings + +* Patch by Thomas Frieden, 13 Nov 2002: + Add code for AmigaOne board + (preliminary merge to U-Boot, still WIP) + +* Patch by Jon Diekema, 12 Nov 2002: + - Adding URL for IEEE OUI lookup + - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED + being defined. + - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and + root-on-nfs macros are designed to switch how the default boot + method gets defined. + +* Patch by Daniel Engström, 13 Nov 2002: + Add support for i386 architecture and AMD SC520 board + +* Patch by Pierre Aubert, 12 Nov 2002: + Add support for DOS filesystem and booting from DOS floppy disk + +* Patch by Jim Sandoz, 07 Nov 2002: + Increase number of network RX buffers (PKTBUFSRX in + "include/net.h") for EEPRO100 based boards (especially SP8240) + which showed "Receiver is not ready" errors when U-Boot was + processing the receive buffers slower than the network controller + was filling them. + +* Patch by Andreas Oberritter, 09 Nov 2002: + Change behaviour of NetLoop(): return -1 for errors, filesize + otherwise; return code 0 is valid an means no file loaded - in this + case the environment still gets updated! + +* Patches by Jon Diekema, 9 Nov 2002: + - improve ADC/DAC clocking on the SACSng board to align + the failing edges of LRCLK and SCLK + - sbc8260 configuration tweaks + - add status LED support for 82xx systems + - wire sspi/sspo commands into command handler; improved error + handlering + - add timestamp support and alternate memory test to the + SACSng configuration + +* Patch by Vince Husovsky, 7 Nov 2002: + Add "-n" to linker options to get rid of "Not enough room for + program headers" problem + +* Patch by David Müller, 05 Nov 2002 + Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ + so we can use an already existing name + +* Patch by Pierre Aubert, 05 Nov 2002 + Hardware relatied improvments in FDC boot code + +* Patch by Holger Schurig, 5 Nov 2002: + Make the PXA really change it's frequency + +* Patch by Pierre Aubert, 05 Nov 2002 + Add support for slave serial Spartan 2 FPGAs + +* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet + drivers + +* Add support for log buffer which can be passed to Linux kernel's + syslog mechanism; used especially for POST results. + +* Patch by Klaus Heydeck, 31 Oct 2002: + Add initial support for kup4k board + +* Patch by Robert Schwebel, 04 Nov 2002: + - use watchdog to reset PXA250 systems + - added progress callbacks to (some of the) ARM code + - update for Cogent CSB226 board + +* Add support for FPS860 board + +* Patch by Guillaume Alexandre,, 04 Nov 2002: + Improve PCI access on 32-bits Compact PCI bus + +* Fix mdelay() on TRAB - this was still the debugging version with + seconds instead of ms. + +* Patch by Robert Schwebel, 1 Nov 2002: + XScale related cleanup (affects all ARM boards) + +* Cleanup of names and README. + +====================================================================== +Notes for U-Boot 0.1.0: +====================================================================== + +This is the initial version of "Das U-Boot", the Universal Boot Loader. + +It is based on version 2.0.0 (the "Halloween Release") of PPCBoot. +For information about the history of the project please see the +PPCBoot project page at http://sourceforge.net/projects/ppcboot + +====================================================================== diff --git a/COPYING b/COPYING new file mode 100644 index 0000000..f616ab9 --- /dev/null +++ b/COPYING @@ -0,0 +1,298 @@ + NOTE! This copyright does *not* cover the so-called "standalone" +applications that use U-Boot services by means of the jump table +provided by U-Boot exactly for this purpose - this is merely +considered normal use of U-Boot, and does *not* fall under the +heading of "derived work". + + The header files "include/image.h" and "include/asm-*/u-boot.h" +define interfaces to U-Boot. Including these (unmodified) header +files in another file is considered normal use of U-Boot, and does +*not* fall under the heading of "derived work". + + Also note that the GPL below is copyrighted by the Free Software +Foundation, but the instance of code that it refers to (the U-Boot +source code) is copyrighted by me and others who actually wrote it. +-- Wolfgang Denk + +======================================================================= + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS diff --git a/CREDITS b/CREDITS new file mode 100644 index 0000000..f91fa3e --- /dev/null +++ b/CREDITS @@ -0,0 +1,458 @@ +# +# Parts of the development effort for this project have been +# sponsored by SIEMENS AG, Austria. Thanks to SIEMENS for +# supporting an Open Source project! +# +# +# This is at least a partial credits-file of individual people that +# have contributed to the U-Boot project. It is sorted by name and +# formatted to allow easy grepping and beautification by scripts. +# The fields are: name (N), email (E), web-address (W), PGP key ID +# and fingerprint (P), description (D), and snail-mail address (S). +# Thanks, +# +# Wolfgang Denk +#---------- + +N: Dr. Bruno Achauer +E: bruno@exet-ag.de +D: Support for NetBSD (both as host and target system) + +N: Guillaume Alexandre +E: guillaume.alexandre@gespac.ch +D: Add PCIPPC6 configuration + +N: Swen Anderson +E: sand@peppercon.de +D: ERIC Support + +N: Pantelis Antoniou +E: panto@intracom.gr +D: NETVIA & NETPHONE board support, ARTOS support. +D: Support for Silicon Turnkey eXpress XTc + +N: Pierre Aubert +E: +D: Support for RPXClassic board + +N: Yuli Barcohen +E: yuli@arabellasw.com +D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards. +D: Support for Zephyr Engineering ZPC.1900 board. +D: Support for Interphase iSPAN boards. +D: Support for Analogue&Micro Adder boards. +D: Support for Analogue&Micro Rattler boards. +W: http://www.arabellasw.com + +N: Jerry van Baren +E: +D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test. + +N: Pavel Bartusek +E: +D: Reiserfs support +W: http://www.elinos.com + +N: Andre Beaudin +E: +D: PCMCIA, Ethernet, TFTP + +N: Jon Benediktsson +E: jonb@marel.is +D: Support for Marel V37 board + +N: Raphael Bossek +E: raphael.bossek@solutions4linux.de +D: 8xxrom-0.3.0 + +N: Cliff Brake +E: cliff.brake@gmail.com +D: Port to Vibren PXA255 IDP platform +W: http://www.vibren.com +W: http://bec-systems.com + +N: Rick Bronson +E: rick@efn.org +D: Atmel AT91RM9200DK and NAND support + +N: David Brown +E: DBrown03@harris.com +D: Extensions to 8xxrom-0.3.0 + +N: Oliver Brown +E: obrown@adventnetworks.com +D: Port to the gw8260 board + +N: Curt Brune +E: curt@cucy.com +D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC) +D: Added support for ESPD-Inc. EVB4510 Board +W: http://www.cucy.com + +N: Jonathan De Bruyne +E: jonathan.debruyne@siemens.atea.be +D: Port to Siemens IAD210 board + +N: Ken Chou +E: kchou@ieee.org +D: Support for A3000 SBC board + +N: Conn Clark +E: clark@esteem.com +D: ESTEEM192E support + +N: Magnus Damm +E: damm@opensource.se +D: 8xxrom + +N: George G. Davis +E: gdavis@mvista.com +D: Board ports for ADS GraphicsClient+ and Intel Assabet + +N: Arun Dharankar +E: ADharankar@ATTBI.Com +D: threads / scheduler example code + +N: Kári Davísson +E: kd@flaga.is +D: FLAGA DM Support + +N: Wolfgang Denk +E: wd@denx.de +D: U-Boot initial version, continuing maintenance, ARMBoot merge +W: http://www.denx.de + +N: Dan A. Dickey +E: ddickey@charter.net +D: FADS Support + +N: James F. Dougherty +E: jfd@GigabitNetworks.COM +D: Port to the MOUSSE board + +N: Dave Ellis +E: DGE@sixnetio.com +D: EEPROM Speedup, SXNI855T port + +N: Thomas Elste +E: info@elste.org +D: Port for the ModNET50 Board, NET+50 CPU Port +W: http://www.imms.de + +N: Daniel Engström +E: daniel@omicron.se +D: x86 port, Support for sc520_cdp board + +N: Dr. Wolfgang Grandegger +E: wg@denx.de +D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards +W: www.denx.de + +N: Peter Figuli +E: peposh@etc.sk +D: Support for WEP EP250 (PXA) board + +N: Thomas Frieden +E: ThomasF@hyperion-entertainment.com +D: Support for AmigaOne + +N: Frank Gottschling +E: fgottschling@eltec.de +D: Support for ELTEC MHPC/BAB7xx/ELPPC boards, cfb-console, i8042, SMI LynxEM +W: www.eltec.de + +N: Marius Groeger +E: mgroeger@sysgo.de +D: MBX Support, board specific function interface, EST SBC8260 support; initial support for StrongARM (LART), ARM720TDMI (implementa A7) +W: www.elinos.com + +N: Kirk Haderlie +E: khaderlie@vividimage.com +D: Added TFTP to 8xxrom (-> 0.3.1) + +N: Chris Hallinan +E: clh@net1plus.com +D: DHCP Support + +N: Anne-Sophie Harnois +E: Anne-Sophie.Harnois@nextream.fr +D: Port to Walnut405 board + +N: Andreas Heppel +E: aheppel@sysgo.de +D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!] + +N: August Hoeraendl +E: august.hoerandl@gmx.at +D: Support for the logodl board (PXA2xx) + +N: Josh Huber +E: huber@alum.wpi.edu +D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series. +W: http://www.mclx.com/ + +H: Stuart Hughes +E: stuarth@lineo.com +D: Port to MPC8260ADS board + +H: Rich Ireland +E: r.ireland@computer.org +D: FPGA device configuration driver + +N: Gary Jennejohn +E: garyj@jennejohn.org, gj@denx.de +D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB" +W: www.denx.de + +N: Murray Jensen +E: Murray.Jensen@csiro.au +D: Initial 8260 support; GDB support +D: Port to Cogent+Hymod boards; Hymod Board Database + +N: Yoo. Jonghoon +E: yooth@ipone.co.kr +D: Added port to the RPXlite board + +N: Mark Jonas +E: mark.jonas@freescale.com +D: Support for Freescale Total5200 platform +W: http://www.mobilegt.com/ + +N: Sam Song +E: samsongshu@yahoo.com.cn +D: Port to the RPXlite_DW board + +N: Brad Kemp +E: Brad.Kemp@seranoa.com +D: Port to Windriver ppmc8260 board + +N: Sangmoon Kim +E: dogoil@etinsys.com +D: Support for debris board + +N: Frederick W. Klatt +E: fred.klatt@windriver.com +D: Support for Wind River SBC8540/SBC8560 boards + +N: Thomas Koeller +E: tkoeller@gmx.net +D: Port to Motorola Sandpoint 3 (MPC8240) + +N: Raghu Krishnaprasad +E: Raghu.Krishnaprasad@fci.com +D: Support for Adder-II MPC852T evaluation board +W: http://www.forcecomputers.com + +N: Bernhard Kuhn +E: bkuhn@metrowerks.com +D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards + +N: Prakash Kumar +E: prakash@embedx.com +D Support for Intrinsyc CERF PXA250 board. + +N: Thomas Lange +E: thomas@corelatus.se +D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes + +N: Marc Leeman +E: marc.leeman@barco.com +D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) +W: www.barco.com + +N: The LEOX team +E: team@leox.org +D: Support for LEOX boards, DS164x RTC +W: http://www.leox.org + +N: Leif Lindholm +E: leif.lindholm@i3micro.com +D: Support for AMD dbau1550 board. + +N: Stephan Linz +E: linz@li-pro.net +D: Support for Nios Stratix Development Kit (DK-1S10) +D: Support for SSV ADNP/ESC1 (Nios Cyclone) +W: http://www.li-pro.net + +N: Raymond Lo +E: lo@routefree.com +D: Support for DOS partitions + +N: Dan Malek +E: dan@embeddedalley.com +D: FADSROM, the grandfather of all of this +D: Support for Silicon Turnkey eXpress XTc + +N: Andrea "llandre" Marson +E: andrea.marson@dave-tech.it +D: Port to PPChameleonEVB board +W: www.dave-tech.it + +N: Reinhard Meyer +E: r.meyer@emk-elektronik.de +D: Port to EMK TOP860 Module + +N: Jay Monkman +E: jtm@smoothsmoothie.com +D: EST SBC8260 support + +N: Frank Morauf +E: frank.morauf@salzbrenner.com +D: Support for Embedded Planet RPX Super Board + +N: David Müller +E: d.mueller@elsoft.ch +D: Support for Samsung ARM920T SMDK2410 eval board + +N: Scott McNutt +E: smcnutt@psyent.com +D: Support for Altera Nios-32 CPU +D: Support for Altera Nios-II CPU +D: Support for Nios Cyclone Development Kit (DK-1C20) +W: http://www.psyent.com + +N: Rolf Offermanns +E: rof@sysgo.de +D: Initial support for SSV-DNP1110, SMC91111 driver +W: www.elinos.com + +N: John Otken +E: jotken@softadvances.com +D: Support for AMCC Luan 440SP board + +N: Tolunay Orkun +E: torkun@nextio.com +D: Support for Cogent CSB272 & CSB472 boards + +N: Keith Outwater +E: keith_outwater@mvis.com +D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC) + +N: Frank Panno +E: fpanno@delphintech.com +D: Support for Embedded Planet EP8260 Board + +N: Denis Peter +E: d.peter@mpl.ch +D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ... +D: Support for PIP405 board +D: Support for MIP405 board + +N: Dave Peverley +E: dpeverley@mpc-data.co.uk +W: http://www.mpc-data.co.uk +D: OMAP730 P2 board support + +N: Bill Pitts +E: wlp@mindspring.com +D: BedBug embedded debugger code + +N: Daniel Poirot +E: dan.poirot@windriver.com +D: Support for the Wind River sbc405, sbc8240 board +W: http://www.windriver.com + +N: Stefan Roese +E: stefan.roese@esd-electronics.com +D: AMCC PPC401/403/405GP Support; Windows environment support + +N: Erwin Rol +E: erwin@muffin.org +D: boot support for RTEMS + +N: Paul Ruhland +E: pruhland@rochester.rr.com +D: Port to Logic Zoom LH7A40x SDK board(s) + +N: Neil Russell +E: caret@c-side.com +D: Author of LiMon-1.4.2, which contributed some ideas + +N: Travis B. Sawyer +E: travis.sawyer@sandburst.com +D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board. AMCC 440gx Ref Platform (Ocotea) + +N: Paolo Scaffardi +E: arsenio@tin.it +D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more + +N: Robert Schwebel +E: r.schwebel@pengutronix.de +D: Support for csb226, logodl and innokom boards (PXA2xx) + +N: Art Shipkowski +E: art@videon-central.com +D: Support for NetSilicon NS7520 + +N: Yasushi Shoji +E: yashi@atmark-techno.com +D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board + +N: Kurt Stremerch +E: kurt@exys.be +D: Support for Exys XSEngine board + +N: Andrea Scian +E: andrea.scian@dave-tech.it +D: Port to B2 board +W: www.dave-tech.it + +N: Rob Taylor +E: robt@flyingpig.com +D: Port to MBX860T and Sandpoint8240 + +N: Erik Theisen +E: etheisen@mindspring.com +D: MBX8xx and many other patches + +N: Jim Thompson +E: jim@musenki.com +D: Support for MUSENKI board + +N: Rune Torgersen +E: +D: Support for Motorola MPC8266ADS board + +N: Greg Ungerer +E: greg.ungerer@opengear.com +D: Support for ks8695 CPU, and OpenGear cmXXXX boards + +N: David Updegraff +E: dave@cray.com +D: Port to Cray L1 board; DHCP vendor extensions + +N: Christian Vejlbo +E: christian.vejlbo@tellabs.com +D: FADS860T ethernet support + +N: Robert Whaley +E: rwhaley@applieddata.net +D: Port to ARM PXA27x adsvix SBC + +N: Martin Winistoerfer +E: martinwinistoerfer@gmx.ch +D: Port to MPC555/556 microcontrollers and support for cmi board + +N: Ming-Len Wu +E: minglen_wu@techware.com.tw +D: Motorola MX1ADS board support +W: http://www.techware.com.tw/ + +N: Xianghua Xiao +E: x.xiao@motorola.com +D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards. + +N: John Zhan +E: zhanz@sinovee.com +D: Support for SinoVee Microsystems SC8xx SBC + +N: Alex Zuepke +E: azu@sysgo.de +D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM +W: www.elinos.com + +N: James MacAulay +E: james.macaulay@amirix.com +D: Suppport for Amirix AP1000 +W: www.amirix.com diff --git a/MAINTAINERS b/MAINTAINERS new file mode 100644 index 0000000..0ef9e03 --- /dev/null +++ b/MAINTAINERS @@ -0,0 +1,539 @@ +######################################################################### +# # +# Regular Maintainers for U-Boot board support: # +# # +# For any board without permanent maintainer, please contact # +# Wolfgang Denk # +# and Cc: the mailing lists. # +# # +# Note: lists sorted by Maintainer Name # +######################################################################### + + +######################################################################### +# PowerPC Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Greg Allen + + UTX8245 MPC8245 + +Pantelis Antoniou + + NETVIA MPC8xx + +Reinhard Arlt + + cpci5200 MPC5200 + pf5200 MPC5200 + + CPCI750 PPC750FX/GX + +Yuli Barcohen + + Adder MPC87x/MPC852T + ep8248 MPC8248 + ISPAN MPC8260 + MPC8260ADS MPC826x/MPC827x/MPC8280 + Rattler MPC8248 + ZPC1900 MPC8265 + +Jerry Van Baren + + sacsng MPC8260 + +Oliver Brown + + gw8260 MPC8260 + +Conn Clark + + ESTEEM192E MPC8xx + +Kári Davísson + + FLAGADM MPC823 + +Torsten Demke + + eXalion MPC824x + +Wolfgang Denk + + IceCube_5100 MGT5100 + IceCube_5200 MPC5200 + + AMX860 MPC860 + ETX094 MPC850 + FPS850L MPC850 + FPS860L MPC860 + ICU862 MPC862 + IP860 MPC860 + IVML24 MPC860 + IVML24_128 MPC860 + IVML24_256 MPC860 + IVMS8 MPC860 + IVMS8_128 MPC860 + IVMS8_256 MPC860 + LANTEC MPC850 + LWMON MPC823 + NC650 MPC852 + R360MPI MPC823 + RMU MPC850 + RRvision MPC823 + SM850 MPC850 + SPD823TS MPC823 + TQM823L MPC823 + TQM823L_LCD MPC823 + TQM850L MPC850 + TQM855L MPC855 + TQM860L MPC860 + TQM860L_FEC MPC860 + c2mon MPC855 + hermes MPC860 + lwmon MPC823 + pcu_e MPC855 + + CU824 MPC8240 + Sandpoint8240 MPC8240 + SL8245 MPC8245 + + ATC MPC8250 + PM825 MPC8250 + + TQM8255 MPC8255 + + CPU86 MPC8260 + PM826 MPC8260 + TQM8260 MPC8260 + + P3G4 MPC7410 + + PCIPPC2 MPC750 + PCIPPC6 MPC750 + + EXBITGEN PPC405GP + +Jon Diekema + + sbc8260 MPC8260 + +Dave Ellis + + SXNI855T MPC8xx + +Thomas Frieden + + AmigaOneG3SE MPC7xx + +Matthias Fuchs + + ADCIOP IOP480 (PPC401) + APC405 PPC405GP + AR405 PPC405GP + ASH405 PPC405EP + CANBT PPC405CR + CPCI2DP PPC405GP + CPCI405 PPC405GP + CPCI4052 PPC405GP + CPCI405AB PPC405GP + CPCI405DT PPC405GP + CPCI440 PPC440GP + CPCIISER4 PPC405GP + DASA_SIM IOP480 (PPC401) + DP405 PPC405EP + DU405 PPC405GP + G2000 PPC405EP + HH405 PPC405EP + HUB405 PPC405EP + OCRTC PPC405GP + ORSG PPC405GP + PCI405 PPC405GP + PLU405 PPC405EP + PMC405 PPC405GP + VOH405 PPC405EP + VOM405 PPC405EP + WUH405 PPC405EP + CMS700 PPC405EP + +Frank Gottschling + + MHPC MPC8xx + + BAB7xx MPC740/MPC750 + +Wolfgang Grandegger + + CCM MPC855 + + PN62 MPC8240 + + IPHASE4539 MPC8260 + SCM MPC8260 + +Howard Gray + + MVS1 MPC823 + +Klaus Heydeck + + KUP4K MPC855 + KUP4X MPC859 + +Murray Jensen + + cogent_mpc8xx MPC8xx + + cogent_mpc8260 MPC8260 + hymod MPC8260 + +Brad Kemp + + ppmc8260 MPC8260 + +Sangmoon Kim + + debris MPC8245 + +Thomas Lange + + GTH MPC860 + +The LEOX team + + ELPT860 MPC860T + +Nye Liu + + ZUMA MPC7xx_74xx + +Jon Loeliger + + MPC8540ADS MPC8540 + MPC8560ADS MPC8560 + MPC8541CDS MPC8541 + MPC8555CDS MPC8555 + +Dan Malek + + STxGP3 MPC85xx + STxXTc MPC8xx + +Eran Man + + EVB64260_750CX MPC750CX + +Andrea "llandre" Marson + + PPChameleonEVB PPC405EP + +Reinhard Meyer + + TOP860 MPC860T + TOP5200 MPC5200 + +Tolunay Orkun + + csb272 PPC405GP + csb472 PPC405GP + +John Otken + + luan PPC440SP + +Keith Outwater + + GEN860T MPC860T + GEN860T_SC MPC860T + +Frank Panno + + ep8260 MPC8260 + +Peter Pearse + integratorcp All current ARM supplied & + supported core modules + - see http://www.arm.com + /products/DevTools + /Hardware_Platforms.html + versatile ARM926EJ-S + versatile ARM926EJ-S + +Denis Peter + + MIP405 PPC4xx + PIP405 PPC4xx + +Daniel Poirot + + sbc8240 MPC8240 + sbc405 PPC405GP + +Stefan Roese + + uc100 MPC857 + + TQM85xx MPC8540/8541/8555/8560 + + bamboo PPC440EP + bunbinga PPC405EP + ebony PPC440GP + ocotea PPC440GX + p3p440 PPC440GP + sycamore PPC405GPr + walnut PPC405GP + yellowstone PPC440GR + yosemite PPC440EP + +Yusdi Santoso + + HIDDEN_DRAGON MPC8241/MPC8245 + +Travis Sawyer (travis.sawyer@sandburst.com> + + KAREF PPC440GX + METROBOX PPC440GX + XPEDITE1K PPC440GX + +Peter De Schrijver + + ML2 PPC4xx + +Erik Theisen + + W7OLMC PPC4xx + W7OLMG PPC4xx + +Jim Thompson + + MUSENKI MPC8245/8241 + Sandpoint8245 MPC8245 + +Rune Torgersen + + MPC8266ADS MPC8266 + +Josef Wagner + + CPC45 MPC8245 + PM520 MPC5200 + +Stephen Williams + + JSE PPC405GPr + +John Zhan + + svm_sc8xx MPC8xx + +------------------------------------------------------------------------- + +Unknown / orphaned boards: + + ADS860 MPC8xx + FADS823 MPC8xx + FADS850SAR MPC8xx + FADS860T MPC8xx + GENIETV MPC8xx + IAD210 MPC8xx + MBX MPC8xx + MBX860T MPC8xx + NX823 MPC8xx + RPXClassic MPC8xx + RPXlite MPC8xx + + CRAYL1 PPC4xx + ERIC PPC4xx + + MOUSSE MPC824x + + RPXsuper MPC8260 + rsdproto MPC8260 + + EVB64260 MPC7xx_74xx + + +######################################################################### +# ARM Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Rowel Atienza + + armadillo ARM720T + +Rishi Bhattacharya + + omap5912osk ARM926EJS + +Cliff Brake + + pxa255_idp xscale + +Rick Bronson + + AT91RM9200DK at91rm9200 + +George G. Davis + + assabet SA1100 + gcplus SA1100 + +Thomas Elste + + modnet50 ARM720T (NET+50) + +Peter Figuli + + wepep250 xscale + +Marius Gröger + + impa7 ARM720T (EP7211) + ep7312 ARM720T (EP7312) + +Kshitij Gupta + + omap1510inn ARM925T + omap1610inn ARM926EJS + +Kyle Harris + + lubbock xscale + cradle xscale + ixdp425 xscale + +Gary Jennejohn + + smdk2400 ARM920T + trab ARM920T + +Nishant Kamat + + omap1610h2 ARM926EJS + +Prakash Kumar + + cerf250 xscale + +David Müller + + smdk2410 ARM920T + VCMA9 ARM920T + +Rolf Offermanns + + shannon SA1100 + +Dave Peverley + + omap730p2 ARM926EJS + +Robert Schwebel + + csb226 xscale + innokom xscale + +Andrea Scian + + B2 ARM7TDMI (S3C44B0X) + +Greg Ungerer + + cm4008 ks8695p + cm4116 ks8695p + cm4148 ks8695p + +Richard Woodruff + + omap2420h4 ARM1136EJS + +Alex Züpke + + lart SA1100 + dnp1110 SA1110 + +######################################################################### +# x86 Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Daniel Engström + + sc520_cdp x86 + +######################################################################### +# MIPS Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Wolfgang Denk + + incaip MIPS32 4Kc + purple MIPS64 5Kc + +Thomas Lange + dbau1x00 MIPS32 Au1000 + +######################################################################### +# Nios-32 Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Stephan Linz + + DK1S10 Nios-32 + ADNPESC1 Nios-32 + +Scott McNutt + + DK1C20 Nios-32 + +######################################################################### +# Nios-II Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Scott McNutt + + PCI5441 Nios-II + PK1C20 Nios-II + +######################################################################### +# MicroBlaze Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Yasushi Shoji + + SUZAKU MicroBlaze + +######################################################################### +# Coldfire Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Matthias Fuchs + + TASREG MCF5249 + +######################################################################### +# End of MAINTAINERS list # +######################################################################### diff --git a/MAKEALL b/MAKEALL new file mode 100755 index 0000000..fcbab47 --- /dev/null +++ b/MAKEALL @@ -0,0 +1,310 @@ +#!/bin/sh + +: ${JOBS:=} + +if [ "${CROSS_COMPILE}" ] ; then + MAKE="make CROSS_COMPILE=${CROSS_COMPILE}" +else + MAKE=make +fi + +[ -d LOG ] || mkdir LOG || exit 1 + +LIST="" + +######################################################################### +## MPC5xx Systems +######################################################################### + +LIST_5xx=" \ + cmi_mpc5xx \ +" + +######################################################################### +## MPC5xxx Systems +######################################################################### + +LIST_5xxx=" \ + cpci5200 icecube_5100 icecube_5200 EVAL5200 \ + pf5200 PM520 Total5100 Total5200 \ + Total5200_Rev2 TQM5200_auto o2dnt \ +" + +######################################################################### +## MPC8xx Systems +######################################################################### + +LIST_8xx=" \ + Adder87x GENIETV MBX860T R360MPI \ + AdderII GTH MHPC RBC823 \ + ADS860 hermes MPC86xADS rmu \ + AMX860 IAD210 MPC885ADS RPXClassic \ + c2mon ICU862_100MHz MVS1 RPXlite \ + CCM IP860 NETPHONE RPXlite_DW \ + cogent_mpc8xx IVML24 NETTA RRvision \ + ELPT860 IVML24_128 NETTA2 SM850 \ + ESTEEM192E IVML24_256 NETTA_ISDN SPD823TS \ + ETX094 IVMS8 NETVIA svm_sc8xx \ + FADS823 IVMS8_128 NETVIA_V2 SXNI855T \ + FADS850SAR IVMS8_256 NX823 TOP860 \ + FADS860T KUP4K pcu_e TQM823L \ + FLAGADM KUP4X QS823 TQM823L_LCD \ + FPS850L LANTEC QS850 TQM850L \ + GEN860T lwmon QS860T TQM855L \ + GEN860T_SC MBX quantum TQM860L \ + uc100 \ + v37 \ +" + +######################################################################### +## PPC4xx Systems +######################################################################### + +LIST_4xx=" \ + ADCIOP AP1000 AR405 ASH405 \ + bubinga CANBT CMS700 CPCI2DP \ + CPCI405 CPCI4052 CPCI405AB CPCI405DT \ + CPCI440 CPCIISER4 CRAYL1 csb272 \ + csb472 DASA_SIM DP405 DU405 \ + ebony ERIC EXBITGEN G2000 \ + HH405 HUB405 JSE KAREF \ + luan METROBOX MIP405 MIP405T \ + ML2 ml300 ocotea OCRTC \ + ORSG p3p440 PCI405 PIP405 \ + PLU405 PMC405 PPChameleonEVB sbc405 \ + VOH405 VOM405 W7OLMC W7OLMG \ + walnut WUH405 XPEDITE1K yellowstone \ + yosemite \ +" + +######################################################################### +## MPC8220 Systems +######################################################################### + +LIST_8220=" \ + Alaska8220 Yukon8220 \ +" + +######################################################################### +## MPC824x Systems +######################################################################### + +LIST_824x=" \ + A3000 barco BMW CPC45 \ + CU824 debris eXalion HIDDEN_DRAGON \ + MOUSSE MUSENKI MVBLUE OXC \ + PN62 Sandpoint8240 Sandpoint8245 sbc8240 \ + SL8245 utx8245 \ +" + +######################################################################### +## MPC8260 Systems (includes 8250, 8255 etc.) +######################################################################### + +LIST_8260=" \ + atc cogent_mpc8260 CPU86 CPU87 \ + ep8248 ep8260 gw8260 hymod \ + IPHASE4539 ISPAN MPC8260ADS MPC8266ADS \ + MPC8272ADS PM826 PM828 ppmc8260 \ + Rattler8248 RPXsuper rsdproto sacsng \ + sbc8260 SCM TQM8260_AC TQM8260_AD \ + TQM8260_AE ZPC1900 \ +" + +######################################################################### +## MPC83xx Systems (includes 8349, etc.) +######################################################################### + +LIST_83xx=" \ + MPC8349ADS TQM834x\ +" + + +######################################################################### +## MPC85xx Systems (includes 8540, 8560 etc.) +######################################################################### + +LIST_85xx=" \ + MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \ + MPC8555CDS MPC8560ADS PM854 PM856 \ + sbc8540 sbc8560 stxgp3 TQM8540 \ + TQM8541 TQM8555 TQM8560 \ +" + +######################################################################### +## 74xx/7xx Systems +######################################################################### + +LIST_74xx=" \ + DB64360 DB64460 EVB64260 P3G4 \ + PCIPPC2 PCIPPC6 ZUMA \ +" + +LIST_7xx=" \ + BAB7xx CPCI750 ELPPC \ +" + +LIST_ppc="${LIST_5xx} ${LIST_5xxx} \ + ${LIST_8xx} \ + ${LIST_8220} ${LIST_824x} ${LIST_8260} \ + ${LIST_83xx} \ + ${LIST_85xx} \ + ${LIST_4xx} \ + ${LIST_74xx} ${LIST_7xx}" + +######################################################################### +## StrongARM Systems +######################################################################### + +LIST_SA="assabet dnp1110 gcplus lart shannon" + +######################################################################### +## ARM7 Systems +######################################################################### + +LIST_ARM7=" \ + armadillo B2 ep7312 evb4510 \ + impa7 integratorap ap7 ap720t \ + modnet50 \ +" + +######################################################################### +## ARM9 Systems +######################################################################### + +LIST_ARM9=" \ + at91rm9200dk cmc_pu2 \ + ap920t ap922_XA10 ap926ejs ap946es \ + ap966 cp920t cp922_XA10 cp926ejs \ + cp946es cp966 lpd7a400 mp2usb \ + mx1ads mx1fs2 omap1510inn omap1610h2 \ + omap1610inn omap730p2 scb9328 smdk2400 \ + smdk2410 trab VCMA9 versatile \ + versatileab versatilepb voiceblue +" + +######################################################################### +## ARM10 Systems +######################################################################### +LIST_ARM10=" \ + integratorcp cp1026 \ +" + +######################################################################### +## ARM11 Systems +######################################################################### +LIST_ARM11=" \ + cp1136 omap2420h4 \ +" + +######################################################################### +## Xscale Systems +######################################################################### + +LIST_pxa=" \ + adsvix cerf250 cradle csb226 \ + innokom lubbock pxa255_idp wepep250 \ + xaeniax xm250 xsengine \ +" + +LIST_ixp="ixdp425" + + +LIST_arm=" \ + ${LIST_SA} \ + ${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11} \ + ${LIST_pxa} ${LIST_ixp} \ +" + +######################################################################### +## MIPS Systems (default = big endian) +######################################################################### + +LIST_mips4kc="incaip" + +LIST_mips5kc="purple" + +LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el" + +LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}" + +######################################################################### +## MIPS Systems (little endian) +######################################################################### + +LIST_mips4kc_el="" + +LIST_mips5kc_el="" + +LIST_au1xx0_el="dbau1550_el" + +LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}" + +######################################################################### +## i386 Systems +######################################################################### + +LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel" + +LIST_x86="${LIST_I486}" + +######################################################################### +## NIOS Systems +######################################################################### + +LIST_nios=" \ + ADNPESC1 ADNPESC1_base_32 \ + ADNPESC1_DNPEVA2_base_32 \ + DK1C20 DK1C20_standard_32 \ + DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \ +" + +######################################################################### +## Nios-II Systems +######################################################################### + +LIST_nios2="PCI5441 PK1C20" + +######################################################################### +## MicroBlaze Systems +######################################################################### + +LIST_microblaze="suzaku" + +#----------------------------------------------------------------------- + +#----- for now, just run PPC by default ----- +[ $# = 0 ] && set $LIST_ppc + +#----------------------------------------------------------------------- + +build_target() { + target=$1 + + ${MAKE} distclean >/dev/null + ${MAKE} ${target}_config + ${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR + ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG +} + +#----------------------------------------------------------------------- + + +for arg in $@ +do + case "$arg" in + ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \ + arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \ + microblaze| \ + mips|mips_el| \ + nios|nios2| \ + x86|I486) + for target in `eval echo '$LIST_'${arg}` + do + build_target ${target} + done + ;; + *) build_target ${arg} + ;; + esac +done diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..9305cab --- /dev/null +++ b/Makefile @@ -0,0 +1,1855 @@ +# +# (C) Copyright 2000-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +HOSTARCH := $(shell uname -m | \ + sed -e s/i.86/i386/ \ + -e s/sun4u/sparc64/ \ + -e s/arm.*/arm/ \ + -e s/sa110/arm/ \ + -e s/powerpc/ppc/ \ + -e s/macppc/ppc/) + +HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \ + sed -e 's/\(cygwin\).*/cygwin/') + +export HOSTARCH HOSTOS + +# Deal with colliding definitions from tcsh etc. +VENDOR= + +######################################################################### + +TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi) +export TOPDIR + +ifeq (include/config.mk,$(wildcard include/config.mk)) +# load ARCH, BOARD, and CPU configuration +include include/config.mk +export ARCH CPU BOARD VENDOR SOC +# load other configuration +include $(TOPDIR)/config.mk + +ifndef CROSS_COMPILE +ifeq ($(HOSTARCH),ppc) +CROSS_COMPILE = +else +ifeq ($(ARCH),ppc) +CROSS_COMPILE = powerpc-linux- +endif +ifeq ($(ARCH),arm) +CROSS_COMPILE = arm-linux- +endif +ifeq ($(ARCH),i386) +ifeq ($(HOSTARCH),i386) +CROSS_COMPILE = +else +CROSS_COMPILE = i386-linux- +endif +endif +ifeq ($(ARCH),mips) +CROSS_COMPILE = mips_4KC- +endif +ifeq ($(ARCH),nios) +CROSS_COMPILE = nios-elf- +endif +ifeq ($(ARCH),nios2) +CROSS_COMPILE = nios2-elf- +endif +ifeq ($(ARCH),m68k) +CROSS_COMPILE = m68k-elf- +endif +ifeq ($(ARCH),microblaze) +CROSS_COMPILE = mb- +endif +endif +endif + +export CROSS_COMPILE + +######################################################################### +# U-Boot objects....order is important (i.e. start must be first) + +OBJS = cpu/$(CPU)/start.o +ifeq ($(CPU),i386) +OBJS += cpu/$(CPU)/start16.o +OBJS += cpu/$(CPU)/reset.o +endif +ifeq ($(CPU),ppc4xx) +OBJS += cpu/$(CPU)/resetvec.o +endif +ifeq ($(CPU),mpc83xx) +OBJS += cpu/$(CPU)/resetvec.o +endif +ifeq ($(CPU),mpc85xx) +OBJS += cpu/$(CPU)/resetvec.o +endif + +LIBS = lib_generic/libgeneric.a +LIBS += board/$(BOARDDIR)/lib$(BOARD).a +LIBS += cpu/$(CPU)/lib$(CPU).a +ifdef SOC +LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a +endif +LIBS += lib_$(ARCH)/lib$(ARCH).a +LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \ + fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a +LIBS += net/libnet.a +LIBS += disk/libdisk.a +LIBS += rtc/librtc.a +LIBS += dtt/libdtt.a +LIBS += drivers/libdrivers.a +LIBS += drivers/sk98lin/libsk98lin.a +LIBS += post/libpost.a post/cpu/libcpu.a +LIBS += common/libcommon.a +.PHONY : $(LIBS) + +# Add GCC lib +PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc + + +# The "tools" are needed early, so put this first +# Don't include stuff already done in $(LIBS) +SUBDIRS = tools \ + examples \ + post \ + post/cpu +.PHONY : $(SUBDIRS) + +######################################################################### +######################################################################### + +ALL = u-boot.srec u-boot.bin System.map + +all: $(ALL) + +u-boot.hex: u-boot + $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ + +u-boot.srec: u-boot + $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ + +u-boot.bin: u-boot + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +u-boot.img: u-boot.bin + ./tools/mkimage -A $(ARCH) -T firmware -C none \ + -a $(TEXT_BASE) -e 0 \ + -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \ + sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ + -d $< $@ + +u-boot.dis: u-boot + $(OBJDUMP) -d $< > $@ + +u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) + UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ + $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \ + --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \ + -Map u-boot.map -o u-boot + +$(LIBS): + $(MAKE) -C `dirname $@` + +$(SUBDIRS): + $(MAKE) -C $@ all + +gdbtools: + $(MAKE) -C tools/gdb || exit 1 + +depend dep: + @for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir .depend ; done + +tags: + ctags -w `find $(SUBDIRS) include \ + lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \ + fs/cramfs fs/fat fs/fdos fs/jffs2 \ + net disk rtc dtt drivers drivers/sk98lin common \ + \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)` + +etags: + etags -a `find $(SUBDIRS) include \ + lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \ + fs/cramfs fs/fat fs/fdos fs/jffs2 \ + net disk rtc dtt drivers drivers/sk98lin common \ + \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)` + +System.map: u-boot + @$(NM) $< | \ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > System.map + +######################################################################### +else +all install u-boot u-boot.srec depend dep: + @echo "System not configured - see README" >&2 + @ exit 1 +endif + +######################################################################### + +unconfig: + @rm -f include/config.h include/config.mk board/*/config.tmp + +#======================================================================== +# PowerPC +#======================================================================== + +######################################################################### +## MPC5xx Systems +######################################################################### + +canmb_config: unconfig + @./mkconfig -a canmb ppc mpc5xxx canmb + +cmi_mpc5xx_config: unconfig + @./mkconfig $(@:_config=) ppc mpc5xx cmi + +PATI_config: unconfig + @./mkconfig $(@:_config=) ppc mpc5xx pati mpl + +######################################################################### +## MPC5xxx Systems +######################################################################### + +aev_config: unconfig + @./mkconfig -a aev ppc mpc5xxx tqm5200 + +cpci5200_config: unconfig + @./mkconfig -a cpci5200 ppc mpc5xxx cpci5200 esd + +hmi1001_config: unconfig + @./mkconfig hmi1001 ppc mpc5xxx hmi1001 + +Lite5200_config \ +Lite5200_LOWBOOT_config \ +Lite5200_LOWBOOT08_config \ +icecube_5200_config \ +icecube_5200_LOWBOOT_config \ +icecube_5200_LOWBOOT08_config \ +icecube_5200_DDR_config \ +icecube_5200_DDR_LOWBOOT_config \ +icecube_5200_DDR_LOWBOOT08_config \ +icecube_5100_config: unconfig + @ >include/config.h + @[ -z "$(findstring LOWBOOT_,$@)" ] || \ + { if [ "$(findstring DDR,$@)" ] ; \ + then echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \ + else echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \ + fi ; \ + echo "... with LOWBOOT configuration" ; \ + } + @[ -z "$(findstring LOWBOOT08,$@)" ] || \ + { echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \ + echo "... with 8 MB flash only" ; \ + echo "... with LOWBOOT configuration" ; \ + } + @[ -z "$(findstring DDR,$@)" ] || \ + { echo "#define CONFIG_MPC5200_DDR" >>include/config.h ; \ + echo "... DDR memory revision" ; \ + } + @[ -z "$(findstring 5200,$@)" ] || \ + { echo "#define CONFIG_MPC5200" >>include/config.h ; \ + echo "... with MPC5200 processor" ; \ + } + @[ -z "$(findstring 5100,$@)" ] || \ + { echo "#define CONFIG_MGT5100" >>include/config.h ; \ + echo "... with MGT5100 processor" ; \ + } + @./mkconfig -a IceCube ppc mpc5xxx icecube + +inka4x0_config: unconfig + @./mkconfig inka4x0 ppc mpc5xxx inka4x0 + +o2dnt_config: + @./mkconfig -a o2dnt ppc mpc5xxx o2dnt + +pf5200_config: unconfig + @./mkconfig -a pf5200 ppc mpc5xxx pf5200 esd + +PM520_config \ +PM520_DDR_config \ +PM520_ROMBOOT_config \ +PM520_ROMBOOT_DDR_config: unconfig + @ >include/config.h + @[ -z "$(findstring DDR,$@)" ] || \ + { echo "#define CONFIG_MPC5200_DDR" >>include/config.h ; \ + echo "... DDR memory revision" ; \ + } + @[ -z "$(findstring ROMBOOT,$@)" ] || \ + { echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \ + echo "... booting from 8-bit flash" ; \ + } + @./mkconfig -a PM520 ppc mpc5xxx pm520 + +MINI5200_config \ +EVAL5200_config \ +TOP5200_config: unconfig + @ echo "#define CONFIG_$(@:_config=) 1" >include/config.h + @./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk + +Total5100_config \ +Total5200_config \ +Total5200_lowboot_config \ +Total5200_Rev2_config \ +Total5200_Rev2_lowboot_config: unconfig + @ >include/config.h + @[ -z "$(findstring 5100,$@)" ] || \ + { echo "#define CONFIG_MGT5100" >>include/config.h ; \ + echo "... with MGT5100 processor" ; \ + } + @[ -z "$(findstring 5200,$@)" ] || \ + { echo "#define CONFIG_MPC5200" >>include/config.h ; \ + echo "... with MPC5200 processor" ; \ + } + @[ -n "$(findstring Rev,$@)" ] || \ + { echo "#define CONFIG_TOTAL5200_REV 1" >>include/config.h ; \ + echo "... revision 1 board" ; \ + } + @[ -z "$(findstring Rev2_,$@)" ] || \ + { echo "#define CONFIG_TOTAL5200_REV 2" >>include/config.h ; \ + echo "... revision 2 board" ; \ + } + @[ -z "$(findstring lowboot_,$@)" ] || \ + { echo "TEXT_BASE = 0xFE000000" >board/total5200/config.tmp ; \ + echo "... with lowboot configuration" ; \ + } + @./mkconfig -a Total5200 ppc mpc5xxx total5200 + +TQM5200_auto_config \ +TQM5200_AA_config \ +TQM5200_AB_config \ +TQM5200_AC_config \ +MiniFAP_config: unconfig + @ >include/config.h + @[ -z "$(findstring MiniFAP,$@)" ] || \ + { echo "#define CONFIG_MINIFAP" >>include/config.h ; \ + echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \ + echo "... TQM5200_AC on MiniFAP" ; \ + } + @[ -z "$(findstring AA,$@)" ] || \ + { echo "#define CONFIG_TQM5200_AA" >>include/config.h ; \ + echo "... with 4 MB Flash, 16 MB SDRAM, 32 kB EEPROM" ; \ + } + @[ -z "$(findstring AB,$@)" ] || \ + { echo "#define CONFIG_TQM5200_AB" >>include/config.h ; \ + echo "... with 64 MB Flash, 64 MB SDRAM, 32 kB EEPROM, 512 kB SRAM" ; \ + echo "... with Graphics Controller"; \ + } + @[ -z "$(findstring AC,$@)" ] || \ + { echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \ + echo "... with 4 MB Flash, 128 MB SDRAM" ; \ + echo "... with Graphics Controller"; \ + } + @[ -z "$(findstring auto,$@)" ] || \ + { echo "#define CONFIG_CS_AUTOCONF" >>include/config.h ; \ + echo "... with automatic CS configuration" ; \ + } + @./mkconfig -a TQM5200 ppc mpc5xxx tqm5200 + +spieval_config: unconfig + echo "#define CONFIG_CS_AUTOCONF">>include/config.h + echo "... with automatic CS configuration" + @./mkconfig -a spieval ppc mpc5xxx tqm5200 + +######################################################################### +## MPC8xx Systems +######################################################################### + +Adder_config \ +Adder87x_config \ +AdderII_config \ + : unconfig + $(if $(findstring AdderII,$@), \ + @echo "#define CONFIG_MPC852T" > include/config.h) + @./mkconfig -a Adder ppc mpc8xx adder + +ADS860_config \ +FADS823_config \ +FADS850SAR_config \ +MPC86xADS_config \ +MPC885ADS_config \ +FADS860T_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx fads + +AMX860_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx amx860 westel + +c2mon_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx c2mon + +CCM_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx CCM siemens + +cogent_mpc8xx_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx cogent + +ELPT860_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX + +ESTEEM192E_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx esteem192e + +ETX094_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx etx094 + +FLAGADM_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx flagadm + +xtract_GEN860T = $(subst _SC,,$(subst _config,,$1)) + +GEN860T_SC_config \ +GEN860T_config: unconfig + @ >include/config.h + @[ -z "$(findstring _SC,$@)" ] || \ + { echo "#define CONFIG_SC" >>include/config.h ; \ + echo "With reduced H/W feature set (SC)..." ; \ + } + @./mkconfig -a $(call xtract_GEN860T,$@) ppc mpc8xx gen860t + +GENIETV_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx genietv + +GTH_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx gth + +hermes_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx hermes + +HMI10_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx + +IAD210_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx IAD210 siemens + +xtract_ICU862 = $(subst _100MHz,,$(subst _config,,$1)) + +ICU862_100MHz_config \ +ICU862_config: unconfig + @ >include/config.h + @[ -z "$(findstring _100MHz,$@)" ] || \ + { echo "#define CONFIG_100MHz" >>include/config.h ; \ + echo "... with 100MHz system clock" ; \ + } + @./mkconfig -a $(call xtract_ICU862,$@) ppc mpc8xx icu862 + +IP860_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx ip860 + +IVML24_256_config \ +IVML24_128_config \ +IVML24_config: unconfig + @ >include/config.h + @[ -z "$(findstring IVML24_config,$@)" ] || \ + { echo "#define CONFIG_IVML24_16M" >>include/config.h ; \ + } + @[ -z "$(findstring IVML24_128_config,$@)" ] || \ + { echo "#define CONFIG_IVML24_32M" >>include/config.h ; \ + } + @[ -z "$(findstring IVML24_256_config,$@)" ] || \ + { echo "#define CONFIG_IVML24_64M" >>include/config.h ; \ + } + @./mkconfig -a IVML24 ppc mpc8xx ivm + +IVMS8_256_config \ +IVMS8_128_config \ +IVMS8_config: unconfig + @ >include/config.h + @[ -z "$(findstring IVMS8_config,$@)" ] || \ + { echo "#define CONFIG_IVMS8_16M" >>include/config.h ; \ + } + @[ -z "$(findstring IVMS8_128_config,$@)" ] || \ + { echo "#define CONFIG_IVMS8_32M" >>include/config.h ; \ + } + @[ -z "$(findstring IVMS8_256_config,$@)" ] || \ + { echo "#define CONFIG_IVMS8_64M" >>include/config.h ; \ + } + @./mkconfig -a IVMS8 ppc mpc8xx ivm + +KUP4K_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx kup4k kup + +KUP4X_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx kup4x kup + +LANTEC_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx lantec + +lwmon_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx lwmon + +MBX_config \ +MBX860T_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx mbx8xx + +MHPC_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx mhpc eltec + +MVS1_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx mvs1 + +xtract_NETVIA = $(subst _V2,,$(subst _config,,$1)) + +NETVIA_V2_config \ +NETVIA_config: unconfig + @ >include/config.h + @[ -z "$(findstring NETVIA_config,$@)" ] || \ + { echo "#define CONFIG_NETVIA_VERSION 1" >>include/config.h ; \ + echo "... Version 1" ; \ + } + @[ -z "$(findstring NETVIA_V2_config,$@)" ] || \ + { echo "#define CONFIG_NETVIA_VERSION 2" >>include/config.h ; \ + echo "... Version 2" ; \ + } + @./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia + +xtract_NETPHONE = $(subst _V2,,$(subst _config,,$1)) + +NETPHONE_V2_config \ +NETPHONE_config: unconfig + @ >include/config.h + @[ -z "$(findstring NETPHONE_config,$@)" ] || \ + { echo "#define CONFIG_NETPHONE_VERSION 1" >>include/config.h ; \ + } + @[ -z "$(findstring NETPHONE_V2_config,$@)" ] || \ + { echo "#define CONFIG_NETPHONE_VERSION 2" >>include/config.h ; \ + } + @./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone + +xtract_NETTA = $(subst _SWAPHOOK,,$(subst _6412,,$(subst _ISDN,,$(subst _config,,$1)))) + +NETTA_ISDN_6412_SWAPHOOK_config \ +NETTA_ISDN_SWAPHOOK_config \ +NETTA_6412_SWAPHOOK_config \ +NETTA_SWAPHOOK_config \ +NETTA_ISDN_6412_config \ +NETTA_ISDN_config \ +NETTA_6412_config \ +NETTA_config: unconfig + @ >include/config.h + @[ -z "$(findstring ISDN_,$@)" ] || \ + { echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \ + } + @[ -n "$(findstring ISDN_,$@)" ] || \ + { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \ + } + @[ -z "$(findstring 6412_,$@)" ] || \ + { echo "#define CONFIG_NETTA_6412 1" >>include/config.h ; \ + } + @[ -n "$(findstring 6412_,$@)" ] || \ + { echo "#undef CONFIG_NETTA_6412" >>include/config.h ; \ + } + @[ -z "$(findstring SWAPHOOK_,$@)" ] || \ + { echo "#define CONFIG_NETTA_SWAPHOOK 1" >>include/config.h ; \ + } + @[ -n "$(findstring SWAPHOOK_,$@)" ] || \ + { echo "#undef CONFIG_NETTA_SWAPHOOK" >>include/config.h ; \ + } + @./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta + +xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1)) + +NETTA2_V2_config \ +NETTA2_config: unconfig + @ >include/config.h + @[ -z "$(findstring NETTA2_config,$@)" ] || \ + { echo "#define CONFIG_NETTA2_VERSION 1" >>include/config.h ; \ + } + @[ -z "$(findstring NETTA2_V2_config,$@)" ] || \ + { echo "#define CONFIG_NETTA2_VERSION 2" >>include/config.h ; \ + } + @./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2 + +NC650_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx nc650 + +NX823_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx nx823 + +pcu_e_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx pcu_e siemens + +QS850_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc + +QS823_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc + +QS860T_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc + +quantum_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx quantum + +R360MPI_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx r360mpi + +RBC823_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx rbc823 + +RPXClassic_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx RPXClassic + +RPXlite_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx RPXlite + +RPXlite_DW_64_config \ +RPXlite_DW_LCD_config \ +RPXlite_DW_64_LCD_config \ +RPXlite_DW_NVRAM_config \ +RPXlite_DW_NVRAM_64_config \ +RPXlite_DW_NVRAM_LCD_config \ +RPXlite_DW_NVRAM_64_LCD_config \ +RPXlite_DW_config: unconfig + @ >include/config.h + @[ -z "$(findstring _64,$@)" ] || \ + { echo "#define RPXlite_64MHz" >>include/config.h ; \ + echo "... with 64MHz system clock ..."; \ + } + @[ -z "$(findstring _LCD,$@)" ] || \ + { echo "#define CONFIG_LCD" >>include/config.h ; \ + echo "#define CONFIG_NEC_NL6448BC20" >>include/config.h ; \ + echo "... with LCD display ..."; \ + } + @[ -z "$(findstring _NVRAM,$@)" ] || \ + { echo "#define CFG_ENV_IS_IN_NVRAM" >>include/config.h ; \ + echo "... with ENV in NVRAM ..."; \ + } + @./mkconfig -a RPXlite_DW ppc mpc8xx RPXlite_dw + +rmu_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx rmu + +RRvision_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx RRvision + +RRvision_LCD_config: unconfig + @echo "#define CONFIG_LCD" >include/config.h + @echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h + @./mkconfig -a RRvision ppc mpc8xx RRvision + +SM850_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx + +SPD823TS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx spd8xx + +stxxtc_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx stxxtc + +svm_sc8xx_config: unconfig + @ >include/config.h + @./mkconfig $(@:_config=) ppc mpc8xx svm_sc8xx + +SXNI855T_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx sixnet + +# EMK MPC8xx based modules +TOP860_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx top860 emk + +# Play some tricks for configuration selection +# Only 855 and 860 boards may come with FEC +# and only 823 boards may have LCD support +xtract_8xx = $(subst _LCD,,$(subst _config,,$1)) + +FPS850L_config \ +FPS860L_config \ +NSCU_config \ +TQM823L_config \ +TQM823L_LCD_config \ +TQM850L_config \ +TQM855L_config \ +TQM860L_config \ +TQM862L_config \ +TQM823M_config \ +TQM850M_config \ +TQM855M_config \ +TQM860M_config \ +TQM862M_config \ +TQM866M_config: unconfig + @ >include/config.h + @[ -z "$(findstring _LCD,$@)" ] || \ + { echo "#define CONFIG_LCD" >>include/config.h ; \ + echo "#define CONFIG_NEC_NL6448BC20" >>include/config.h ; \ + echo "... with LCD display" ; \ + } + @./mkconfig -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx + +TTTech_config: unconfig + @echo "#define CONFIG_LCD" >include/config.h + @echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h + @./mkconfig -a TQM823L ppc mpc8xx tqm8xx + +uc100_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx uc100 + +v37_config: unconfig + @echo "#define CONFIG_LCD" >include/config.h + @echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h + @./mkconfig $(@:_config=) ppc mpc8xx v37 + +wtk_config: unconfig + @echo "#define CONFIG_LCD" >include/config.h + @echo "#define CONFIG_SHARP_LQ065T9DR51U" >>include/config.h + @./mkconfig -a TQM823L ppc mpc8xx tqm8xx + +######################################################################### +## PPC4xx Systems +######################################################################### +xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1)))))) + +ADCIOP_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx adciop esd + +AP1000_config:unconfig + @./mkconfig $(@:_config=) ppc ppc4xx ap1000 amirix + +APC405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx apc405 esd + +AR405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx ar405 esd + +ASH405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx ash405 esd + +bamboo_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx bamboo amcc + +bubinga_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx bubinga amcc + +CANBT_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx canbt esd + +CATcenter_config \ +CATcenter_25_config \ +CATcenter_33_config: unconfig + @ echo "/* CATcenter uses PPChameleon Model ME */" > include/config.h + @ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h + @[ -z "$(findstring _25,$@)" ] || \ + { echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \ + echo "SysClk = 25MHz" ; \ + } + @[ -z "$(findstring _33,$@)" ] || \ + { echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \ + echo "SysClk = 33MHz" ; \ + } + @./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave + +CPCI2DP_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx cpci2dp esd + +CPCI405_config \ +CPCI4052_config \ +CPCI405DT_config \ +CPCI405AB_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx cpci405 esd + @echo "BOARD_REVISION = $(@:_config=)" >>include/config.mk + +CPCI440_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx cpci440 esd + +CPCIISER4_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx cpciiser4 esd + +CRAYL1_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx L1 cray + +csb272_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx csb272 + +csb472_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx csb472 + +DASA_SIM_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd + +DP405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx dp405 esd + +DU405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx du405 esd + +ebony_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx ebony amcc + +ERIC_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx eric + +EXBITGEN_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx exbitgen + +G2000_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx g2000 + +HH405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx hh405 esd + +HUB405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx hub405 esd + +JSE_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx jse + +KAREF_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx karef sandburst + +luan_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx luan amcc + +METROBOX_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx metrobox sandburst + +MIP405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl + +MIP405T_config: unconfig + @echo "#define CONFIG_MIP405T" >include/config.h + @echo "Enable subset config for MIP405T" + @./mkconfig -a MIP405 ppc ppc4xx mip405 mpl + +ML2_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx ml2 + +ml300_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx + +ocotea_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx ocotea amcc + +OCRTC_config \ +ORSG_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx ocrtc esd + +p3p440_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx p3p440 prodrive + +PCI405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx pci405 esd + +PIP405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl + +PLU405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx plu405 esd + +PMC405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd + +PPChameleonEVB_config \ +PPChameleonEVB_BA_25_config \ +PPChameleonEVB_ME_25_config \ +PPChameleonEVB_HI_25_config \ +PPChameleonEVB_BA_33_config \ +PPChameleonEVB_ME_33_config \ +PPChameleonEVB_HI_33_config: unconfig + @ >include/config.h + @[ -z "$(findstring EVB_BA,$@)" ] || \ + { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \ + echo "... BASIC model" ; \ + } + @[ -z "$(findstring EVB_ME,$@)" ] || \ + { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \ + echo "... MEDIUM model" ; \ + } + @[ -z "$(findstring EVB_HI,$@)" ] || \ + { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \ + echo "... HIGH-END model" ; \ + } + @[ -z "$(findstring _25,$@)" ] || \ + { echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \ + echo "SysClk = 25MHz" ; \ + } + @[ -z "$(findstring _33,$@)" ] || \ + { echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \ + echo "SysClk = 33MHz" ; \ + } + @./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave + +sbc405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx sbc405 + +sycamore_config: unconfig + @echo "Configuring for sycamore board as subset of walnut..." + @./mkconfig -a walnut ppc ppc4xx walnut amcc + +VOH405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx voh405 esd + +VOM405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx vom405 esd + +CMS700_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx cms700 esd + +W7OLMC_config \ +W7OLMG_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx w7o + +walnut_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx walnut amcc + +WUH405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd + +XPEDITE1K_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx xpedite1k + +yosemite_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx yosemite amcc + +yellowstone_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc + +######################################################################### +## MPC8220 Systems +######################################################################### + +Alaska8220_config \ +Yukon8220_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8220 alaska + +sorcery_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8220 sorcery + +######################################################################### +## MPC824x Systems +######################################################################### +xtract_82xx = $(subst _BIGFLASH,,$(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1)))))) + +A3000_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x a3000 + +barco_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x barco + +BMW_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x bmw + +CPC45_config \ +CPC45_ROMBOOT_config: unconfig + @./mkconfig $(call xtract_82xx,$@) ppc mpc824x cpc45 + @cd ./include ; \ + if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ + echo "CONFIG_BOOT_ROM = y" >> config.mk ; \ + echo "... booting from 8-bit flash" ; \ + else \ + echo "CONFIG_BOOT_ROM = n" >> config.mk ; \ + echo "... booting from 64-bit flash" ; \ + fi; \ + echo "export CONFIG_BOOT_ROM" >> config.mk; + +CU824_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x cu824 + +debris_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x debris etin + +eXalion_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x eXalion + +HIDDEN_DRAGON_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x hidden_dragon + +MOUSSE_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x mousse + +MUSENKI_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x musenki + +MVBLUE_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x mvblue + +OXC_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x oxc + +PN62_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x pn62 + +Sandpoint8240_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x sandpoint + +Sandpoint8245_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x sandpoint + +sbc8240_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x sbc8240 + +SL8245_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x sl8245 + +utx8245_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x utx8245 + +######################################################################### +## MPC8260 Systems +######################################################################### + +atc_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 atc + +cogent_mpc8260_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 cogent + +CPU86_config \ +CPU86_ROMBOOT_config: unconfig + @./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu86 + @cd ./include ; \ + if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ + echo "CONFIG_BOOT_ROM = y" >> config.mk ; \ + echo "... booting from 8-bit flash" ; \ + else \ + echo "CONFIG_BOOT_ROM = n" >> config.mk ; \ + echo "... booting from 64-bit flash" ; \ + fi; \ + echo "export CONFIG_BOOT_ROM" >> config.mk; + +CPU87_config \ +CPU87_ROMBOOT_config: unconfig + @./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu87 + @cd ./include ; \ + if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ + echo "CONFIG_BOOT_ROM = y" >> config.mk ; \ + echo "... booting from 8-bit flash" ; \ + else \ + echo "CONFIG_BOOT_ROM = n" >> config.mk ; \ + echo "... booting from 64-bit flash" ; \ + fi; \ + echo "export CONFIG_BOOT_ROM" >> config.mk; + +ep8248_config \ +ep8248E_config : unconfig + @./mkconfig ep8248 ppc mpc8260 ep8248 + +ep8260_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 ep8260 + +gw8260_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 gw8260 + +hymod_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 hymod + +IDS8247_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 ids8247 + +IPHASE4539_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 iphase4539 + +ISPAN_config \ +ISPAN_REVB_config: unconfig + @if [ "$(findstring _REVB_,$@)" ] ; then \ + echo "#define CFG_REV_B" > include/config.h ; \ + fi + @./mkconfig -a ISPAN ppc mpc8260 ispan + +MPC8260ADS_config \ +MPC8260ADS_lowboot_config \ +MPC8260ADS_33MHz_config \ +MPC8260ADS_33MHz_lowboot_config \ +MPC8260ADS_40MHz_config \ +MPC8260ADS_40MHz_lowboot_config \ +MPC8272ADS_config \ +MPC8272ADS_lowboot_config \ +PQ2FADS_config \ +PQ2FADS_lowboot_config \ +PQ2FADS-VR_config \ +PQ2FADS-VR_lowboot_config \ +PQ2FADS-ZU_config \ +PQ2FADS-ZU_lowboot_config \ +PQ2FADS-ZU_66MHz_config \ +PQ2FADS-ZU_66MHz_lowboot_config \ + : unconfig + $(if $(findstring PQ2FADS,$@), \ + @echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > include/config.h, \ + @echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > include/config.h) + $(if $(findstring MHz,$@), \ + @echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> include/config.h, \ + $(if $(findstring VR,$@), \ + @echo "#define CONFIG_8260_CLKIN 66000000" >> include/config.h)) + @[ -z "$(findstring lowboot_,$@)" ] || \ + { echo "TEXT_BASE = 0xFF800000" >board/mpc8260ads/config.tmp ; \ + echo "... with lowboot configuration" ; \ + } + @./mkconfig -a MPC8260ADS ppc mpc8260 mpc8260ads + +MPC8266ADS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 mpc8266ads + +# PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash +PM825_config \ +PM825_ROMBOOT_config \ +PM825_BIGFLASH_config \ +PM825_ROMBOOT_BIGFLASH_config \ +PM826_config \ +PM826_ROMBOOT_config \ +PM826_BIGFLASH_config \ +PM826_ROMBOOT_BIGFLASH_config: unconfig + @if [ "$(findstring PM825_,$@)" ] ; then \ + echo "#define CONFIG_PCI" >include/config.h ; \ + else \ + >include/config.h ; \ + fi + @if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ + echo "... booting from 8-bit flash" ; \ + echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \ + echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \ + if [ "$(findstring _BIGFLASH_,$@)" ] ; then \ + echo "... with 32 MB Flash" ; \ + echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \ + fi; \ + else \ + echo "... booting from 64-bit flash" ; \ + if [ "$(findstring _BIGFLASH_,$@)" ] ; then \ + echo "... with 32 MB Flash" ; \ + echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \ + echo "TEXT_BASE = 0x40000000" >board/pm826/config.tmp ; \ + else \ + echo "TEXT_BASE = 0xFF000000" >board/pm826/config.tmp ; \ + fi; \ + fi + @./mkconfig -a PM826 ppc mpc8260 pm826 + +PM828_config \ +PM828_PCI_config \ +PM828_ROMBOOT_config \ +PM828_ROMBOOT_PCI_config: unconfig + @if [ -z "$(findstring _PCI_,$@)" ] ; then \ + echo "#define CONFIG_PCI" >>include/config.h ; \ + echo "... with PCI enabled" ; \ + else \ + >include/config.h ; \ + fi + @if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ + echo "... booting from 8-bit flash" ; \ + echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \ + echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \ + fi + @./mkconfig -a PM828 ppc mpc8260 pm828 + +ppmc8260_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 ppmc8260 + +Rattler8248_config \ +Rattler_config: unconfig + $(if $(findstring 8248,$@), \ + @echo "#define CONFIG_MPC8248" > include/config.h) + @./mkconfig -a Rattler ppc mpc8260 rattler + +RPXsuper_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 rpxsuper + +rsdproto_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 rsdproto + +sacsng_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 sacsng + +sbc8260_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 sbc8260 + +SCM_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 SCM siemens + +TQM8255_AA_config \ +TQM8260_AA_config \ +TQM8260_AB_config \ +TQM8260_AC_config \ +TQM8260_AD_config \ +TQM8260_AE_config \ +TQM8260_AF_config \ +TQM8260_AG_config \ +TQM8260_AH_config \ +TQM8265_AA_config: unconfig + @case "$@" in \ + TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no; BMODE=8260;; \ + TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no; BMODE=8260;; \ + TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \ + TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \ + TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \ + TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no; BMODE=8260;; \ + TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \ + TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=8260;; \ + TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;; \ + TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no; BMODE=60x;; \ + esac; \ + >include/config.h ; \ + if [ "$${CTYPE}" != "MPC8260" ] ; then \ + echo "#define CONFIG_$${CTYPE}" >>include/config.h ; \ + fi; \ + echo "#define CONFIG_$${CFREQ}MHz" >>include/config.h ; \ + echo "... with $${CFREQ}MHz system clock" ; \ + if [ "$${CACHE}" == "yes" ] ; then \ + echo "#define CONFIG_L2_CACHE" >>include/config.h ; \ + echo "... with L2 Cache support" ; \ + else \ + echo "#undef CONFIG_L2_CACHE" >>include/config.h ; \ + echo "... without L2 Cache support" ; \ + fi; \ + if [ "$${BMODE}" == "60x" ] ; then \ + echo "#define CONFIG_BUSMODE_60x" >>include/config.h ; \ + echo "... with 60x Bus Mode" ; \ + else \ + echo "#undef CONFIG_BUSMODE_60x" >>include/config.h ; \ + echo "... without 60x Bus Mode" ; \ + fi + @./mkconfig -a TQM8260 ppc mpc8260 tqm8260 + +VoVPN-GW_66MHz_config \ +VoVPN-GW_100MHz_config: unconfig + @echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > include/config.h + @./mkconfig -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk + +ZPC1900_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8260 zpc1900 + +#======================================================================== +# M68K +#======================================================================== +######################################################################### +## Coldfire +######################################################################### + +cobra5272_config : unconfig + @./mkconfig $(@:_config=) m68k mcf52x2 cobra5272 + +M5272C3_config : unconfig + @./mkconfig $(@:_config=) m68k mcf52x2 m5272c3 + +M5282EVB_config : unconfig + @./mkconfig $(@:_config=) m68k mcf52x2 m5282evb + +TASREG_config : unconfig + @./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd + +######################################################################### +## MPC83xx Systems +######################################################################### + +MPC8349ADS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads + +TQM834x_config: unconfig + @./mkconfig $(@:_config=) ppc mpc83xx tqm834x + +######################################################################### +## MPC85xx Systems +######################################################################### + +MPC8540ADS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads + +MPC8540EVAL_config \ +MPC8540EVAL_33_config \ +MPC8540EVAL_66_config \ +MPC8540EVAL_33_slave_config \ +MPC8540EVAL_66_slave_config: unconfig + @echo "" >include/config.h ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + echo -n "... 33 MHz PCI" ; \ + else \ + echo "#define CONFIG_SYSCLK_66M" >>include/config.h ; \ + echo -n "... 66 MHz PCI" ; \ + fi ; \ + if [ "$(findstring _slave_,$@)" ] ; then \ + echo "#define CONFIG_PCI_SLAVE" >>include/config.h ; \ + echo " slave" ; \ + else \ + echo " host" ; \ + fi + @./mkconfig -a MPC8540EVAL ppc mpc85xx mpc8540eval + +MPC8560ADS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads + +MPC8541CDS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds + +MPC8548CDS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc85xx mpc8548cds cds + +MPC8555CDS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds + +PM854_config: unconfig + @./mkconfig $(@:_config=) ppc mpc85xx pm854 + +PM856_config: unconfig + @./mkconfig $(@:_config=) ppc mpc85xx pm856 + +sbc8540_config \ +sbc8540_33_config \ +sbc8540_66_config: unconfig + @if [ "$(findstring _66_,$@)" ] ; then \ + echo "#define CONFIG_PCI_66" >>include/config.h ; \ + echo "... 66 MHz PCI" ; \ + else \ + >include/config.h ; \ + echo "... 33 MHz PCI" ; \ + fi + @./mkconfig -a SBC8540 ppc mpc85xx sbc8560 + +sbc8560_config \ +sbc8560_33_config \ +sbc8560_66_config: unconfig + @if [ "$(findstring _66_,$@)" ] ; then \ + echo "#define CONFIG_PCI_66" >>include/config.h ; \ + echo "... 66 MHz PCI" ; \ + else \ + >include/config.h ; \ + echo "... 33 MHz PCI" ; \ + fi + @./mkconfig -a sbc8560 ppc mpc85xx sbc8560 + +stxgp3_config: unconfig + @./mkconfig $(@:_config=) ppc mpc85xx stxgp3 + +TQM8540_config \ +TQM8541_config \ +TQM8555_config \ +TQM8560_config: unconfig + @CTYPE=$(subst TQM,,$(@:_config=)); \ + >include/config.h ; \ + echo "... TQM"$${CTYPE}; \ + echo "#define CONFIG_MPC$${CTYPE}">>include/config.h; \ + echo "#define CONFIG_TQM$${CTYPE}">>include/config.h; \ + echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>include/config.h; \ + echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>include/config.h; \ + echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>include/config.h + @./mkconfig -a TQM85xx ppc mpc85xx tqm85xx + +######################################################################### +## 74xx/7xx Systems +######################################################################### + +AmigaOneG3SE_config: unconfig + @./mkconfig $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI + +BAB7xx_config: unconfig + @./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec + +CPCI750_config: unconfig + @./mkconfig CPCI750 ppc 74xx_7xx cpci750 esd + +DB64360_config: unconfig + @./mkconfig DB64360 ppc 74xx_7xx db64360 Marvell + +DB64460_config: unconfig + @./mkconfig DB64460 ppc 74xx_7xx db64460 Marvell + +ELPPC_config: unconfig + @./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec + +EVB64260_config \ +EVB64260_750CX_config: unconfig + @./mkconfig EVB64260 ppc 74xx_7xx evb64260 + +P3G4_config: unconfig + @./mkconfig $(@:_config=) ppc 74xx_7xx evb64260 + +PCIPPC2_config \ +PCIPPC6_config: unconfig + @./mkconfig $(@:_config=) ppc 74xx_7xx pcippc2 + +ZUMA_config: unconfig + @./mkconfig $(@:_config=) ppc 74xx_7xx evb64260 + +#======================================================================== +# ARM +#======================================================================== +######################################################################### +## StrongARM Systems +######################################################################### + +assabet_config : unconfig + @./mkconfig $(@:_config=) arm sa1100 assabet + +dnp1110_config : unconfig + @./mkconfig $(@:_config=) arm sa1100 dnp1110 + +gcplus_config : unconfig + @./mkconfig $(@:_config=) arm sa1100 gcplus + +lart_config : unconfig + @./mkconfig $(@:_config=) arm sa1100 lart + +shannon_config : unconfig + @./mkconfig $(@:_config=) arm sa1100 shannon + +######################################################################### +## ARM92xT Systems +######################################################################### + +xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1)))) + +xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1)))) + +xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1))) + +at91rm9200dk_config : unconfig + @./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200 + +cmc_pu2_config : unconfig + @./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200 + +csb637_config : unconfig + @./mkconfig $(@:_config=) arm arm920t csb637 NULL at91rm9200 + +mp2usb_config : unconfig + @./mkconfig $(@:_config=) arm arm920t mp2usb NULL at91rm9200 + + +######################################################################## +## ARM Integrator boards - see doc/README-integrator for more info. +integratorap_config \ +ap_config \ +ap966_config \ +ap922_config \ +ap922_XA10_config \ +ap7_config \ +ap720t_config \ +ap920t_config \ +ap926ejs_config \ +ap946es_config: unconfig + @board/integratorap/split_by_variant.sh $@ + +integratorcp_config \ +cp_config \ +cp920t_config \ +cp926ejs_config \ +cp946es_config \ +cp1136_config \ +cp966_config \ +cp922_config \ +cp922_XA10_config \ +cp1026_config: unconfig + @board/integratorcp/split_by_variant.sh $@ + +kb9202_config : unconfig + @./mkconfig $(@:_config=) arm arm920t kb9202 NULL at91rm9200 + +lpd7a400_config \ +lpd7a404_config: unconfig + @./mkconfig $(@:_config=) arm lh7a40x lpd7a40x + +mx1ads_config : unconfig + @./mkconfig $(@:_config=) arm arm920t mx1ads NULL imx + +mx1fs2_config : unconfig + @./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx + +omap1510inn_config : unconfig + @./mkconfig $(@:_config=) arm arm925t omap1510inn + +omap5912osk_config : unconfig + @./mkconfig $(@:_config=) arm arm926ejs omap5912osk + +omap1610inn_config \ +omap1610inn_cs0boot_config \ +omap1610inn_cs3boot_config \ +omap1610inn_cs_autoboot_config \ +omap1610h2_config \ +omap1610h2_cs0boot_config \ +omap1610h2_cs3boot_config \ +omap1610h2_cs_autoboot_config: unconfig + @if [ "$(findstring _cs0boot_, $@)" ] ; then \ + echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \ + echo "... configured for CS0 boot"; \ + elif [ "$(findstring _cs_autoboot_, $@)" ] ; then \ + echo "#define CONFIG_CS_AUTOBOOT" >> ./include/config.h ; \ + echo "... configured for CS_AUTO boot"; \ + else \ + echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \ + echo "... configured for CS3 boot"; \ + fi; + @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn + +omap730p2_config \ +omap730p2_cs0boot_config \ +omap730p2_cs3boot_config : unconfig + @if [ "$(findstring _cs0boot_, $@)" ] ; then \ + echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \ + echo "... configured for CS0 boot"; \ + else \ + echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \ + echo "... configured for CS3 boot"; \ + fi; + @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 + +scb9328_config : unconfig + @./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx + +smdk2400_config : unconfig + @./mkconfig $(@:_config=) arm arm920t smdk2400 NULL s3c24x0 + +smdk2410_config : unconfig + @./mkconfig $(@:_config=) arm arm920t smdk2410 NULL s3c24x0 + +SX1_config : unconfig + @./mkconfig $(@:_config=) arm arm925t sx1 + +# TRAB default configuration: 8 MB Flash, 32 MB RAM +trab_config \ +trab_bigram_config \ +trab_bigflash_config \ +trab_old_config: unconfig + @ >include/config.h + @[ -z "$(findstring _bigram,$@)" ] || \ + { echo "#define CONFIG_FLASH_8MB" >>include/config.h ; \ + echo "#define CONFIG_RAM_32MB" >>include/config.h ; \ + echo "... with 8 MB Flash, 32 MB RAM" ; \ + } + @[ -z "$(findstring _bigflash,$@)" ] || \ + { echo "#define CONFIG_FLASH_16MB" >>include/config.h ; \ + echo "#define CONFIG_RAM_16MB" >>include/config.h ; \ + echo "... with 16 MB Flash, 16 MB RAM" ; \ + echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \ + } + @[ -z "$(findstring _old,$@)" ] || \ + { echo "#define CONFIG_FLASH_8MB" >>include/config.h ; \ + echo "#define CONFIG_RAM_16MB" >>include/config.h ; \ + echo "... with 8 MB Flash, 16 MB RAM" ; \ + echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \ + } + @./mkconfig -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0 + +VCMA9_config : unconfig + @./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0 + +#======================================================================== +# ARM supplied Versatile development boards +#======================================================================== +versatile_config \ +versatileab_config \ +versatilepb_config : unconfig + @board/versatile/split_by_variant.sh $@ + +voiceblue_smallflash_config \ +voiceblue_config: unconfig + @if [ "$(findstring _smallflash_,$@)" ] ; then \ + echo "... boot from lower flash bank" ; \ + echo "#define VOICEBLUE_SMALL_FLASH" >>include/config.h ; \ + echo "VOICEBLUE_SMALL_FLASH=y" >board/voiceblue/config.tmp ; \ + else \ + echo "... boot from upper flash bank" ; \ + >include/config.h ; \ + echo "VOICEBLUE_SMALL_FLASH=n" >board/voiceblue/config.tmp ; \ + fi + @./mkconfig -a voiceblue arm arm925t voiceblue + +cm4008_config : unconfig + @./mkconfig $(@:_config=) arm arm920t cm4008 NULL ks8695 + +cm41xx_config : unconfig + @./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695 + +######################################################################### +## S3C44B0 Systems +######################################################################### + +B2_config : unconfig + @./mkconfig $(@:_config=) arm s3c44b0 B2 dave + +######################################################################### +## ARM720T Systems +######################################################################### + +armadillo_config: unconfig + @./mkconfig $(@:_config=) arm arm720t armadillo + +ep7312_config : unconfig + @./mkconfig $(@:_config=) arm arm720t ep7312 + +impa7_config : unconfig + @./mkconfig $(@:_config=) arm arm720t impa7 + +modnet50_config : unconfig + @./mkconfig $(@:_config=) arm arm720t modnet50 + +evb4510_config : unconfig + @./mkconfig $(@:_config=) arm arm720t evb4510 + +######################################################################### +## XScale Systems +######################################################################### + +adsvix_config : unconfig + @./mkconfig $(@:_config=) arm pxa adsvix + +cerf250_config : unconfig + @./mkconfig $(@:_config=) arm pxa cerf250 + +cradle_config : unconfig + @./mkconfig $(@:_config=) arm pxa cradle + +csb226_config : unconfig + @./mkconfig $(@:_config=) arm pxa csb226 + +innokom_config : unconfig + @./mkconfig $(@:_config=) arm pxa innokom + +ixdp425_config : unconfig + @./mkconfig $(@:_config=) arm ixp ixdp425 + +lubbock_config : unconfig + @./mkconfig $(@:_config=) arm pxa lubbock + +logodl_config : unconfig + @./mkconfig $(@:_config=) arm pxa logodl + +pxa255_idp_config: unconfig + @./mkconfig $(@:_config=) arm pxa pxa255_idp + +wepep250_config : unconfig + @./mkconfig $(@:_config=) arm pxa wepep250 + +xaeniax_config : unconfig + @./mkconfig $(@:_config=) arm pxa xaeniax + +xm250_config : unconfig + @./mkconfig $(@:_config=) arm pxa xm250 + +xsengine_config : unconfig + @./mkconfig $(@:_config=) arm pxa xsengine + +######################################################################### +## ARM1136 Systems +######################################################################### +omap2420h4_config : unconfig + @./mkconfig $(@:_config=) arm arm1136 omap2420h4 + +#======================================================================== +# i386 +#======================================================================== +######################################################################### +## AMD SC520 CDP +######################################################################### +sc520_cdp_config : unconfig + @./mkconfig $(@:_config=) i386 i386 sc520_cdp + +sc520_spunk_config : unconfig + @./mkconfig $(@:_config=) i386 i386 sc520_spunk + +sc520_spunk_rel_config : unconfig + @./mkconfig $(@:_config=) i386 i386 sc520_spunk + +#======================================================================== +# MIPS +#======================================================================== +######################################################################### +## MIPS32 4Kc +######################################################################### + +xtract_incaip = $(subst _100MHz,,$(subst _133MHz,,$(subst _150MHz,,$(subst _config,,$1)))) + +incaip_100MHz_config \ +incaip_133MHz_config \ +incaip_150MHz_config \ +incaip_config: unconfig + @ >include/config.h + @[ -z "$(findstring _100MHz,$@)" ] || \ + { echo "#define CPU_CLOCK_RATE 100000000" >>include/config.h ; \ + echo "... with 100MHz system clock" ; \ + } + @[ -z "$(findstring _133MHz,$@)" ] || \ + { echo "#define CPU_CLOCK_RATE 133000000" >>include/config.h ; \ + echo "... with 133MHz system clock" ; \ + } + @[ -z "$(findstring _150MHz,$@)" ] || \ + { echo "#define CPU_CLOCK_RATE 150000000" >>include/config.h ; \ + echo "... with 150MHz system clock" ; \ + } + @./mkconfig -a $(call xtract_incaip,$@) mips mips incaip + +tb0229_config: unconfig + @./mkconfig $(@:_config=) mips mips tb0229 + +######################################################################### +## MIPS32 AU1X00 +######################################################################### +dbau1000_config : unconfig + @ >include/config.h + @echo "#define CONFIG_DBAU1000 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 + +dbau1100_config : unconfig + @ >include/config.h + @echo "#define CONFIG_DBAU1100 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 + +dbau1500_config : unconfig + @ >include/config.h + @echo "#define CONFIG_DBAU1500 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 + +dbau1550_config : unconfig + @ >include/config.h + @echo "#define CONFIG_DBAU1550 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 + +dbau1550_el_config : unconfig + @ >include/config.h + @echo "#define CONFIG_DBAU1550 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 + +pb1000_config : unconfig + @ >include/config.h + @echo "#define CONFIG_PB1000 1" >>include/config.h + @./mkconfig -a pb1x00 mips mips pb1x00 + +######################################################################### +## MIPS64 5Kc +######################################################################### + +purple_config : unconfig + @./mkconfig $(@:_config=) mips mips purple + +#======================================================================== +# Nios +#======================================================================== +######################################################################### +## Nios32 +######################################################################### + +DK1C20_safe_32_config \ +DK1C20_standard_32_config \ +DK1C20_config: unconfig + @ >include/config.h + @[ -z "$(findstring _safe_32,$@)" ] || \ + { echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \ + echo "... NIOS 'safe_32' configuration" ; \ + } + @[ -z "$(findstring _standard_32,$@)" ] || \ + { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ + echo "... NIOS 'standard_32' configuration" ; \ + } + @[ -z "$(findstring DK1C20_config,$@)" ] || \ + { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ + echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \ + } + @./mkconfig -a DK1C20 nios nios dk1c20 altera + +DK1S10_safe_32_config \ +DK1S10_standard_32_config \ +DK1S10_mtx_ldk_20_config \ +DK1S10_config: unconfig + @ >include/config.h + @[ -z "$(findstring _safe_32,$@)" ] || \ + { echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \ + echo "... NIOS 'safe_32' configuration" ; \ + } + @[ -z "$(findstring _standard_32,$@)" ] || \ + { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ + echo "... NIOS 'standard_32' configuration" ; \ + } + @[ -z "$(findstring _mtx_ldk_20,$@)" ] || \ + { echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \ + echo "... NIOS 'mtx_ldk_20' configuration" ; \ + } + @[ -z "$(findstring DK1S10_config,$@)" ] || \ + { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ + echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \ + } + @./mkconfig -a DK1S10 nios nios dk1s10 altera + +ADNPESC1_DNPEVA2_base_32_config \ +ADNPESC1_base_32_config \ +ADNPESC1_config: unconfig + @ >include/config.h + @[ -z "$(findstring _DNPEVA2,$@)" ] || \ + { echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \ + echo "... DNP/EVA2 configuration" ; \ + } + @[ -z "$(findstring _base_32,$@)" ] || \ + { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \ + echo "... NIOS 'base_32' configuration" ; \ + } + @[ -z "$(findstring ADNPESC1_config,$@)" ] || \ + { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \ + echo "... NIOS 'base_32' configuration (DEFAULT)" ; \ + } + @./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv + +######################################################################### +## Nios-II +######################################################################### + +PK1C20_config : unconfig + @./mkconfig PK1C20 nios2 nios2 pk1c20 psyent + +PCI5441_config : unconfig + @./mkconfig PCI5441 nios2 nios2 pci5441 psyent + +#======================================================================== +# MicroBlaze +#======================================================================== +######################################################################### +## Microblaze +######################################################################### +suzaku_config: unconfig + @ >include/config.h + @echo "#define CONFIG_SUZAKU 1" >> include/config.h + @./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno + +######################################################################### +######################################################################### + +clean: + find . -type f \ + \( -name 'core' -o -name '*.bak' -o -name '*~' \ + -o -name '*.o' -o -name '*.a' \) -print \ + | xargs rm -f + rm -f examples/hello_world examples/timer \ + examples/eepro100_eeprom examples/sched \ + examples/mem_to_mem_idma2intr examples/82559_eeprom \ + examples/test_burst + rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr + rm -f tools/mpc86x_clk tools/ncb + rm -f tools/easylogo/easylogo tools/bmp_logo + rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend + rm -f tools/env/fw_printenv tools/env/fw_setenv + rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image + rm -f board/trab/trab_fkt board/voiceblue/eeprom + rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds + +clobber: clean + find . -type f \( -name .depend \ + -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \ + -print0 \ + | xargs -0 rm -f + rm -f $(OBJS) *.bak tags TAGS + rm -fr *.*~ + rm -f u-boot u-boot.map u-boot.hex $(ALL) + rm -f tools/crc32.c tools/environment.c tools/env/crc32.c + rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c + rm -f include/asm/proc include/asm/arch include/asm + +mrproper \ +distclean: clobber unconfig + +backup: + F=`basename $(TOPDIR)` ; cd .. ; \ + gtar --force-local -zcvf `date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F + +######################################################################### diff --git a/README b/README new file mode 100644 index 0000000..6f61008 --- /dev/null +++ b/README @@ -0,0 +1,3498 @@ +# +# (C) Copyright 2000 - 2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +Summary: +======== + +This directory contains the source code for U-Boot, a boot loader for +Embedded boards based on PowerPC, ARM, MIPS and several other +processors, which can be installed in a boot ROM and used to +initialize and test the hardware or to download and run application +code. + +The development of U-Boot is closely related to Linux: some parts of +the source code originate in the Linux source tree, we have some +header files in common, and special provision has been made to +support booting of Linux images. + +Some attention has been paid to make this software easily +configurable and extendable. For instance, all monitor commands are +implemented with the same call interface, so that it's very easy to +add new commands. Also, instead of permanently adding rarely used +code (for instance hardware test utilities) to the monitor, you can +load and run it dynamically. + + +Status: +======= + +In general, all boards for which a configuration option exists in the +Makefile have been tested to some extent and can be considered +"working". In fact, many of them are used in production systems. + +In case of problems see the CHANGELOG and CREDITS files to find out +who contributed the specific port. + + +Where to get help: +================== + +In case you have questions about, problems with or contributions for +U-Boot you should send a message to the U-Boot mailing list at +. There is also an archive of +previous traffic on the mailing list - please search the archive +before asking FAQ's. Please see +http://lists.sourceforge.net/lists/listinfo/u-boot-users/ + + +Where we come from: +=================== + +- start from 8xxrom sources +- create PPCBoot project (http://sourceforge.net/projects/ppcboot) +- clean up code +- make it easier to add custom boards +- make it possible to add other [PowerPC] CPUs +- extend functions, especially: + * Provide extended interface to Linux boot loader + * S-Record download + * network boot + * PCMCIA / CompactFLash / ATA disk / SCSI ... boot +- create ARMBoot project (http://sourceforge.net/projects/armboot) +- add other CPU families (starting with ARM) +- create U-Boot project (http://sourceforge.net/projects/u-boot) + + +Names and Spelling: +=================== + +The "official" name of this project is "Das U-Boot". The spelling +"U-Boot" shall be used in all written text (documentation, comments +in source files etc.). Example: + + This is the README file for the U-Boot project. + +File names etc. shall be based on the string "u-boot". Examples: + + include/asm-ppc/u-boot.h + + #include + +Variable names, preprocessor constants etc. shall be either based on +the string "u_boot" or on "U_BOOT". Example: + + U_BOOT_VERSION u_boot_logo + IH_OS_U_BOOT u_boot_hush_start + + +Versioning: +=========== + +U-Boot uses a 3 level version number containing a version, a +sub-version, and a patchlevel: "U-Boot-2.34.5" means version "2", +sub-version "34", and patchlevel "4". + +The patchlevel is used to indicate certain stages of development +between released versions, i. e. officially released versions of +U-Boot will always have a patchlevel of "0". + + +Directory Hierarchy: +==================== + +- board Board dependent files +- common Misc architecture independent functions +- cpu CPU specific files + - 74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs + - arm720t Files specific to ARM 720 CPUs + - arm920t Files specific to ARM 920 CPUs + - at91rm9200 Files specific to Atmel AT91RM9200 CPU + - imx Files specific to Freescale MC9328 i.MX CPUs + - s3c24x0 Files specific to Samsung S3C24X0 CPUs + - arm925t Files specific to ARM 925 CPUs + - arm926ejs Files specific to ARM 926 CPUs + - arm1136 Files specific to ARM 1136 CPUs + - i386 Files specific to i386 CPUs + - ixp Files specific to Intel XScale IXP CPUs + - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs + - mips Files specific to MIPS CPUs + - mpc5xx Files specific to Freescale MPC5xx CPUs + - mpc5xxx Files specific to Freescale MPC5xxx CPUs + - mpc8xx Files specific to Freescale MPC8xx CPUs + - mpc8220 Files specific to Freescale MPC8220 CPUs + - mpc824x Files specific to Freescale MPC824x CPUs + - mpc8260 Files specific to Freescale MPC8260 CPUs + - mpc85xx Files specific to Freescale MPC85xx CPUs + - nios Files specific to Altera NIOS CPUs + - nios2 Files specific to Altera Nios-II CPUs + - ppc4xx Files specific to AMCC PowerPC 4xx CPUs + - pxa Files specific to Intel XScale PXA CPUs + - s3c44b0 Files specific to Samsung S3C44B0 CPUs + - sa1100 Files specific to Intel StrongARM SA1100 CPUs +- disk Code for disk drive partition handling +- doc Documentation (don't expect too much) +- drivers Commonly used device drivers +- dtt Digital Thermometer and Thermostat drivers +- examples Example code for standalone applications, etc. +- include Header Files +- lib_arm Files generic to ARM architecture +- lib_generic Files generic to all architectures +- lib_i386 Files generic to i386 architecture +- lib_m68k Files generic to m68k architecture +- lib_mips Files generic to MIPS architecture +- lib_nios Files generic to NIOS architecture +- lib_ppc Files generic to PowerPC architecture +- net Networking code +- post Power On Self Test +- rtc Real Time Clock drivers +- tools Tools to build S-Record or U-Boot images, etc. + +Software Configuration: +======================= + +Configuration is usually done using C preprocessor defines; the +rationale behind that is to avoid dead code whenever possible. + +There are two classes of configuration variables: + +* Configuration _OPTIONS_: + These are selectable by the user and have names beginning with + "CONFIG_". + +* Configuration _SETTINGS_: + These depend on the hardware etc. and should not be meddled with if + you don't know what you're doing; they have names beginning with + "CFG_". + +Later we will add a configuration tool - probably similar to or even +identical to what's used for the Linux kernel. Right now, we have to +do the configuration by hand, which means creating some symbolic +links and editing some configuration files. We use the TQM8xxL boards +as an example here. + + +Selection of Processor Architecture and Board Type: +--------------------------------------------------- + +For all supported boards there are ready-to-use default +configurations available; just type "make _config". + +Example: For a TQM823L module type: + + cd u-boot + make TQM823L_config + +For the Cogent platform, you need to specify the cpu type as well; +e.g. "make cogent_mpc8xx_config". And also configure the cogent +directory according to the instructions in cogent/README. + + +Configuration Options: +---------------------- + +Configuration depends on the combination of board and CPU type; all +such information is kept in a configuration file +"include/configs/.h". + +Example: For a TQM823L module, all configuration settings are in +"include/configs/TQM823L.h". + + +Many of the options are named exactly as the corresponding Linux +kernel configuration options. The intention is to make it easier to +build a config tool - later. + + +The following options need to be configured: + +- CPU Type: Define exactly one of + + PowerPC based CPUs: + ------------------- + CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860 + or CONFIG_MPC5xx + or CONFIG_MPC8220 + or CONFIG_MPC824X, CONFIG_MPC8260 + or CONFIG_MPC85xx + or CONFIG_IOP480 + or CONFIG_405GP + or CONFIG_405EP + or CONFIG_440 + or CONFIG_MPC74xx + or CONFIG_750FX + + ARM based CPUs: + --------------- + CONFIG_SA1110 + CONFIG_ARM7 + CONFIG_PXA250 + + MicroBlaze based CPUs: + ---------------------- + CONFIG_MICROBLAZE + + Nios-2 based CPUs: + ---------------------- + CONFIG_NIOS2 + + +- Board Type: Define exactly one of + + PowerPC based boards: + --------------------- + + CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCIPPC2 + CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC6 + CONFIG_AMX860 CONFIG_GTH CONFIG_pcu_e + CONFIG_AP1000 CONFIG_gw8260 CONFIG_PIP405 + CONFIG_AR405 CONFIG_hermes CONFIG_PM826 + CONFIG_BAB7xx CONFIG_hymod CONFIG_ppmc8260 + CONFIG_c2mon CONFIG_IAD210 CONFIG_QS823 + CONFIG_CANBT CONFIG_ICU862 CONFIG_QS850 + CONFIG_CCM CONFIG_IP860 CONFIG_QS860T + CONFIG_CMI CONFIG_IPHASE4539 CONFIG_RBC823 + CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RPXClassic + CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXlite + CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXsuper + CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_rsdproto + CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_sacsng + CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_Sandpoint8240 + CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8245 + CONFIG_CSB272 CONFIG_LANTEC CONFIG_sbc8260 + CONFIG_CU824 CONFIG_lwmon CONFIG_sbc8560 + CONFIG_DASA_SIM CONFIG_MBX CONFIG_SM850 + CONFIG_DB64360 CONFIG_MBX860T CONFIG_SPD823TS + CONFIG_DB64460 CONFIG_MHPC CONFIG_STXGP3 + CONFIG_DU405 CONFIG_MIP405 CONFIG_SXNI855T + CONFIG_DUET_ADS CONFIG_MOUSSE CONFIG_TQM823L + CONFIG_EBONY CONFIG_MPC8260ADS CONFIG_TQM8260 + CONFIG_ELPPC CONFIG_MPC8540ADS CONFIG_TQM850L + CONFIG_ELPT860 CONFIG_MPC8540EVAL CONFIG_TQM855L + CONFIG_ep8260 CONFIG_MPC8560ADS CONFIG_TQM860L + CONFIG_ERIC CONFIG_MUSENKI CONFIG_TTTech + CONFIG_ESTEEM192E CONFIG_MVS1 CONFIG_UTX8245 + CONFIG_ETX094 CONFIG_NETPHONE CONFIG_V37 + CONFIG_EVB64260 CONFIG_NETTA CONFIG_W7OLMC + CONFIG_FADS823 CONFIG_NETVIA CONFIG_W7OLMG + CONFIG_FADS850SAR CONFIG_NX823 CONFIG_WALNUT + CONFIG_FADS860T CONFIG_OCRTC CONFIG_ZPC1900 + CONFIG_FLAGADM CONFIG_ORSG CONFIG_ZUMA + CONFIG_FPS850L CONFIG_OXC + CONFIG_FPS860L CONFIG_PCI405 + + ARM based boards: + ----------------- + + CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250, + CONFIG_CSB637, CONFIG_DNP1110, CONFIG_EP7312, + CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, CONFIG_IMPA7, + CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_KB9202, + CONFIG_LART, CONFIG_LPD7A400, CONFIG_LUBBOCK, + CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, CONFIG_SHANNON, + CONFIG_P2_OMAP730, CONFIG_SMDK2400, CONFIG_SMDK2410, + CONFIG_TRAB, CONFIG_VCMA9 + + MicroBlaze based boards: + ------------------------ + + CONFIG_SUZAKU + + Nios-2 based boards: + ------------------------ + + CONFIG_PCI5441 CONFIG_PK1C20 + + +- CPU Module Type: (if CONFIG_COGENT is defined) + Define exactly one of + CONFIG_CMA286_60_OLD +--- FIXME --- not tested yet: + CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P, + CONFIG_CMA287_23, CONFIG_CMA287_50 + +- Motherboard Type: (if CONFIG_COGENT is defined) + Define exactly one of + CONFIG_CMA101, CONFIG_CMA102 + +- Motherboard I/O Modules: (if CONFIG_COGENT is defined) + Define one or more of + CONFIG_CMA302 + +- Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined) + Define one or more of + CONFIG_LCD_HEARTBEAT - update a character position on + the lcd display every second with + a "rotator" |\-/|\-/ + +- Board flavour: (if CONFIG_MPC8260ADS is defined) + CONFIG_ADSTYPE + Possible values are: + CFG_8260ADS - original MPC8260ADS + CFG_8266ADS - MPC8266ADS + CFG_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR + CFG_8272ADS - MPC8272ADS + +- MPC824X Family Member (if CONFIG_MPC824X is defined) + Define exactly one of + CONFIG_MPC8240, CONFIG_MPC8245 + +- 8xx CPU Options: (if using an MPC8xx cpu) + CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if + get_gclk_freq() cannot work + e.g. if there is no 32KHz + reference PIT/RTC clock + CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK + or XTAL/EXTAL) + +- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU): + CFG_8xx_CPUCLK_MIN + CFG_8xx_CPUCLK_MAX + CONFIG_8xx_CPUCLK_DEFAULT + See doc/README.MPC866 + + CFG_MEASURE_CPUCLK + + Define this to measure the actual CPU clock instead + of relying on the correctness of the configured + values. Mostly useful for board bringup to make sure + the PLL is locked at the intended frequency. Note + that this requires a (stable) reference clock (32 kHz + RTC clock or CFG_8XX_XIN) + +- Linux Kernel Interface: + CONFIG_CLOCKS_IN_MHZ + + U-Boot stores all clock information in Hz + internally. For binary compatibility with older Linux + kernels (which expect the clocks passed in the + bd_info data to be in MHz) the environment variable + "clocks_in_mhz" can be defined so that U-Boot + converts clock data to MHZ before passing it to the + Linux kernel. + When CONFIG_CLOCKS_IN_MHZ is defined, a definition of + "clocks_in_mhz=1" is automatically included in the + default environment. + + CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only] + + When transfering memsize parameter to linux, some versions + expect it to be in bytes, others in MB. + Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. + + CONFIG_OF_FLAT_TREE + + New kernel versions are expecting firmware settings to be + passed using flat open firmware trees. + The environment variable "disable_of", when set, disables this + functionality. + + CONFIG_OF_FLAT_TREE_MAX_SIZE + + The maximum size of the constructed OF tree. + + OF_CPU - The proper name of the cpus node. + OF_TBCLK - The timebase frequency. + +- Serial Ports: + CFG_PL010_SERIAL + + Define this if you want support for Amba PrimeCell PL010 UARTs. + + CFG_PL011_SERIAL + + Define this if you want support for Amba PrimeCell PL011 UARTs. + + CONFIG_PL011_CLOCK + + If you have Amba PrimeCell PL011 UARTs, set this variable to + the clock speed of the UARTs. + + CONFIG_PL01x_PORTS + + If you have Amba PrimeCell PL010 or PL011 UARTs on your board, + define this to a list of base addresses for each (supported) + port. See e.g. include/configs/versatile.h + + +- Console Interface: + Depending on board, define exactly one serial port + (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, + CONFIG_8xx_CONS_SCC1, ...), or switch off the serial + console by defining CONFIG_8xx_CONS_NONE + + Note: if CONFIG_8xx_CONS_NONE is defined, the serial + port routines must be defined elsewhere + (i.e. serial_init(), serial_getc(), ...) + + CONFIG_CFB_CONSOLE + Enables console device for a color framebuffer. Needs following + defines (cf. smiLynxEM, i8042, board/eltec/bab7xx) + VIDEO_FB_LITTLE_ENDIAN graphic memory organisation + (default big endian) + VIDEO_HW_RECTFILL graphic chip supports + rectangle fill + (cf. smiLynxEM) + VIDEO_HW_BITBLT graphic chip supports + bit-blit (cf. smiLynxEM) + VIDEO_VISIBLE_COLS visible pixel columns + (cols=pitch) + VIDEO_VISIBLE_ROWS visible pixel rows + VIDEO_PIXEL_SIZE bytes per pixel + VIDEO_DATA_FORMAT graphic data format + (0-5, cf. cfb_console.c) + VIDEO_FB_ADRS framebuffer address + VIDEO_KBD_INIT_FCT keyboard int fct + (i.e. i8042_kbd_init()) + VIDEO_TSTC_FCT test char fct + (i.e. i8042_tstc) + VIDEO_GETC_FCT get char fct + (i.e. i8042_getc) + CONFIG_CONSOLE_CURSOR cursor drawing on/off + (requires blink timer + cf. i8042.c) + CFG_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c) + CONFIG_CONSOLE_TIME display time/date info in + upper right corner + (requires CFG_CMD_DATE) + CONFIG_VIDEO_LOGO display Linux logo in + upper left corner + CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of + linux_logo.h for logo. + Requires CONFIG_VIDEO_LOGO + CONFIG_CONSOLE_EXTRA_INFO + addional board info beside + the logo + + When CONFIG_CFB_CONSOLE is defined, video console is + default i/o. Serial console can be forced with + environment 'console=serial'. + + When CONFIG_SILENT_CONSOLE is defined, all console + messages (by U-Boot and Linux!) can be silenced with + the "silent" environment variable. See + doc/README.silent for more information. + +- Console Baudrate: + CONFIG_BAUDRATE - in bps + Select one of the baudrates listed in + CFG_BAUDRATE_TABLE, see below. + CFG_BRGCLK_PRESCALE, baudrate prescale + +- Interrupt driven serial port input: + CONFIG_SERIAL_SOFTWARE_FIFO + + PPC405GP only. + Use an interrupt handler for receiving data on the + serial port. It also enables using hardware handshake + (RTS/CTS) and UART's built-in FIFO. Set the number of + bytes the interrupt driven input buffer should have. + + Leave undefined to disable this feature, including + disable the buffer and hardware handshake. + +- Console UART Number: + CONFIG_UART1_CONSOLE + + AMCC PPC4xx only. + If defined internal UART1 (and not UART0) is used + as default U-Boot console. + +- Boot Delay: CONFIG_BOOTDELAY - in seconds + Delay before automatically booting the default image; + set to -1 to disable autoboot. + + See doc/README.autoboot for these options that + work with CONFIG_BOOTDELAY. None are required. + CONFIG_BOOT_RETRY_TIME + CONFIG_BOOT_RETRY_MIN + CONFIG_AUTOBOOT_KEYED + CONFIG_AUTOBOOT_PROMPT + CONFIG_AUTOBOOT_DELAY_STR + CONFIG_AUTOBOOT_STOP_STR + CONFIG_AUTOBOOT_DELAY_STR2 + CONFIG_AUTOBOOT_STOP_STR2 + CONFIG_ZERO_BOOTDELAY_CHECK + CONFIG_RESET_TO_RETRY + +- Autoboot Command: + CONFIG_BOOTCOMMAND + Only needed when CONFIG_BOOTDELAY is enabled; + define a command string that is automatically executed + when no character is read on the console interface + within "Boot Delay" after reset. + + CONFIG_BOOTARGS + This can be used to pass arguments to the bootm + command. The value of CONFIG_BOOTARGS goes into the + environment value "bootargs". + + CONFIG_RAMBOOT and CONFIG_NFSBOOT + The value of these goes into the environment as + "ramboot" and "nfsboot" respectively, and can be used + as a convenience, when switching between booting from + ram and nfs. + +- Pre-Boot Commands: + CONFIG_PREBOOT + + When this option is #defined, the existence of the + environment variable "preboot" will be checked + immediately before starting the CONFIG_BOOTDELAY + countdown and/or running the auto-boot command resp. + entering interactive mode. + + This feature is especially useful when "preboot" is + automatically generated or modified. For an example + see the LWMON board specific code: here "preboot" is + modified when the user holds down a certain + combination of keys on the (special) keyboard when + booting the systems + +- Serial Download Echo Mode: + CONFIG_LOADS_ECHO + If defined to 1, all characters received during a + serial download (using the "loads" command) are + echoed back. This might be needed by some terminal + emulations (like "cu"), but may as well just take + time on others. This setting #define's the initial + value of the "loads_echo" environment variable. + +- Kgdb Serial Baudrate: (if CFG_CMD_KGDB is defined) + CONFIG_KGDB_BAUDRATE + Select one of the baudrates listed in + CFG_BAUDRATE_TABLE, see below. + +- Monitor Functions: + CONFIG_COMMANDS + Most monitor functions can be selected (or + de-selected) by adjusting the definition of + CONFIG_COMMANDS; to select individual functions, + #define CONFIG_COMMANDS by "OR"ing any of the + following values: + + #define enables commands: + ------------------------- + CFG_CMD_ASKENV * ask for env variable + CFG_CMD_AUTOSCRIPT Autoscript Support + CFG_CMD_BDI bdinfo + CFG_CMD_BEDBUG * Include BedBug Debugger + CFG_CMD_BMP * BMP support + CFG_CMD_BSP * Board specific commands + CFG_CMD_BOOTD bootd + CFG_CMD_CACHE * icache, dcache + CFG_CMD_CONSOLE coninfo + CFG_CMD_DATE * support for RTC, date/time... + CFG_CMD_DHCP * DHCP support + CFG_CMD_DIAG * Diagnostics + CFG_CMD_DOC * Disk-On-Chip Support + CFG_CMD_DTT * Digital Therm and Thermostat + CFG_CMD_ECHO * echo arguments + CFG_CMD_EEPROM * EEPROM read/write support + CFG_CMD_ELF * bootelf, bootvx + CFG_CMD_ENV saveenv + CFG_CMD_FDC * Floppy Disk Support + CFG_CMD_FAT * FAT partition support + CFG_CMD_FDOS * Dos diskette Support + CFG_CMD_FLASH flinfo, erase, protect + CFG_CMD_FPGA FPGA device initialization support + CFG_CMD_HWFLOW * RTS/CTS hw flow control + CFG_CMD_I2C * I2C serial bus support + CFG_CMD_IDE * IDE harddisk support + CFG_CMD_IMI iminfo + CFG_CMD_IMLS List all found images + CFG_CMD_IMMAP * IMMR dump support + CFG_CMD_IRQ * irqinfo + CFG_CMD_ITEST Integer/string test of 2 values + CFG_CMD_JFFS2 * JFFS2 Support + CFG_CMD_KGDB * kgdb + CFG_CMD_LOADB loadb + CFG_CMD_LOADS loads + CFG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, + loop, loopw, mtest + CFG_CMD_MISC Misc functions like sleep etc + CFG_CMD_MMC * MMC memory mapped support + CFG_CMD_MII * MII utility commands + CFG_CMD_NAND * NAND support + CFG_CMD_NET bootp, tftpboot, rarpboot + CFG_CMD_PCI * pciinfo + CFG_CMD_PCMCIA * PCMCIA support + CFG_CMD_PING * send ICMP ECHO_REQUEST to network host + CFG_CMD_PORTIO * Port I/O + CFG_CMD_REGINFO * Register dump + CFG_CMD_RUN run command in env variable + CFG_CMD_SAVES * save S record dump + CFG_CMD_SCSI * SCSI Support + CFG_CMD_SDRAM * print SDRAM configuration information + (requires CFG_CMD_I2C) + CFG_CMD_SETGETDCR Support for DCR Register access (4xx only) + CFG_CMD_SPI * SPI serial bus support + CFG_CMD_USB * USB support + CFG_CMD_VFD * VFD support (TRAB) + CFG_CMD_BSP * Board SPecific functions + CFG_CMD_CDP * Cisco Discover Protocol support + ----------------------------------------------- + CFG_CMD_ALL all + + CONFIG_CMD_DFL Default configuration; at the moment + this is includes all commands, except + the ones marked with "*" in the list + above. + + If you don't define CONFIG_COMMANDS it defaults to + CONFIG_CMD_DFL in include/cmd_confdefs.h. A board can + override the default settings in the respective + include file. + + EXAMPLE: If you want all functions except of network + support you can write: + + #define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NET) + + + Note: Don't enable the "icache" and "dcache" commands + (configuration option CFG_CMD_CACHE) unless you know + what you (and your U-Boot users) are doing. Data + cache cannot be enabled on systems like the 8xx or + 8260 (where accesses to the IMMR region must be + uncached), and it cannot be disabled on all other + systems where we (mis-) use the data cache to hold an + initial stack and some data. + + + XXX - this list needs to get updated! + +- Watchdog: + CONFIG_WATCHDOG + If this variable is defined, it enables watchdog + support. There must be support in the platform specific + code for a watchdog. For the 8xx and 8260 CPUs, the + SIU Watchdog feature is enabled in the SYPCR + register. + +- U-Boot Version: + CONFIG_VERSION_VARIABLE + If this variable is defined, an environment variable + named "ver" is created by U-Boot showing the U-Boot + version as printed by the "version" command. + This variable is readonly. + +- Real-Time Clock: + + When CFG_CMD_DATE is selected, the type of the RTC + has to be selected, too. Define exactly one of the + following options: + + CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx + CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC + CONFIG_RTC_MC146818 - use MC146818 RTC + CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC + CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC + CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC + CONFIG_RTC_DS164x - use Dallas DS164x RTC + CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC + + Note that if the RTC uses I2C, then the I2C interface + must also be configured. See I2C Support, below. + +- Timestamp Support: + + When CONFIG_TIMESTAMP is selected, the timestamp + (date and time) of an image is printed by image + commands like bootm or iminfo. This option is + automatically enabled when you select CFG_CMD_DATE . + +- Partition Support: + CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION + and/or CONFIG_ISO_PARTITION + + If IDE or SCSI support is enabled (CFG_CMD_IDE or + CFG_CMD_SCSI) you must configure support for at least + one partition type as well. + +- IDE Reset method: + CONFIG_IDE_RESET_ROUTINE - this is defined in several + board configurations files but used nowhere! + + CONFIG_IDE_RESET - is this is defined, IDE Reset will + be performed by calling the function + ide_set_reset(int reset) + which has to be defined in a board specific file + +- ATAPI Support: + CONFIG_ATAPI + + Set this to enable ATAPI support. + +- LBA48 Support + CONFIG_LBA48 + + Set this to enable support for disks larger than 137GB + Also look at CFG_64BIT_LBA ,CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL + Whithout these , LBA48 support uses 32bit variables and will 'only' + support disks up to 2.1TB. + + CFG_64BIT_LBA: + When enabled, makes the IDE subsystem use 64bit sector addresses. + Default is 32bit. + +- SCSI Support: + At the moment only there is only support for the + SYM53C8XX SCSI controller; define + CONFIG_SCSI_SYM53C8XX to enable it. + + CFG_SCSI_MAX_LUN [8], CFG_SCSI_MAX_SCSI_ID [7] and + CFG_SCSI_MAX_DEVICE [CFG_SCSI_MAX_SCSI_ID * + CFG_SCSI_MAX_LUN] can be adjusted to define the + maximum numbers of LUNs, SCSI ID's and target + devices. + CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) + +- NETWORK Support (PCI): + CONFIG_E1000 + Support for Intel 8254x gigabit chips. + + CONFIG_EEPRO100 + Support for Intel 82557/82559/82559ER chips. + Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom + write routine for first time initialisation. + + CONFIG_TULIP + Support for Digital 2114x chips. + Optional CONFIG_TULIP_SELECT_MEDIA for board specific + modem chip initialisation (KS8761/QS6611). + + CONFIG_NATSEMI + Support for National dp83815 chips. + + CONFIG_NS8382X + Support for National dp8382[01] gigabit chips. + +- NETWORK Support (other): + + CONFIG_DRIVER_LAN91C96 + Support for SMSC's LAN91C96 chips. + + CONFIG_LAN91C96_BASE + Define this to hold the physical address + of the LAN91C96's I/O space + + CONFIG_LAN91C96_USE_32_BIT + Define this to enable 32 bit addressing + + CONFIG_DRIVER_SMC91111 + Support for SMSC's LAN91C111 chip + + CONFIG_SMC91111_BASE + Define this to hold the physical address + of the device (I/O space) + + CONFIG_SMC_USE_32_BIT + Define this if data bus is 32 bits + + CONFIG_SMC_USE_IOFUNCS + Define this to use i/o functions instead of macros + (some hardware wont work with macros) + +- USB Support: + At the moment only the UHCI host controller is + supported (PIP405, MIP405, MPC5200); define + CONFIG_USB_UHCI to enable it. + define CONFIG_USB_KEYBOARD to enable the USB Keyboard + and define CONFIG_USB_STORAGE to enable the USB + storage devices. + Note: + Supported are USB Keyboards and USB Floppy drives + (TEAC FD-05PUB). + MPC5200 USB requires additional defines: + CONFIG_USB_CLOCK + for 528 MHz Clock: 0x0001bbbb + CONFIG_USB_CONFIG + for differential drivers: 0x00001000 + for single ended drivers: 0x00005000 + + +- MMC Support: + The MMC controller on the Intel PXA is supported. To + enable this define CONFIG_MMC. The MMC can be + accessed from the boot prompt by mapping the device + to physical memory similar to flash. Command line is + enabled with CFG_CMD_MMC. The MMC driver also works with + the FAT fs. This is enabled with CFG_CMD_FAT. + +- Journaling Flash filesystem support: + CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, + CONFIG_JFFS2_NAND_DEV + Define these for a default partition on a NAND device + + CFG_JFFS2_FIRST_SECTOR, + CFG_JFFS2_FIRST_BANK, CFG_JFFS2_NUM_BANKS + Define these for a default partition on a NOR device + + CFG_JFFS_CUSTOM_PART + Define this to create an own partition. You have to provide a + function struct part_info* jffs2_part_info(int part_num) + + If you define only one JFFS2 partition you may also want to + #define CFG_JFFS_SINGLE_PART 1 + to disable the command chpart. This is the default when you + have not defined a custom partition + +- Keyboard Support: + CONFIG_ISA_KEYBOARD + + Define this to enable standard (PC-Style) keyboard + support + + CONFIG_I8042_KBD + Standard PC keyboard driver with US (is default) and + GERMAN key layout (switch via environment 'keymap=de') support. + Export function i8042_kbd_init, i8042_tstc and i8042_getc + for cfb_console. Supports cursor blinking. + +- Video support: + CONFIG_VIDEO + + Define this to enable video support (for output to + video). + + CONFIG_VIDEO_CT69000 + + Enable Chips & Technologies 69000 Video chip + + CONFIG_VIDEO_SMI_LYNXEM + Enable Silicon Motion SMI 712/710/810 Video chip. The + video output is selected via environment 'videoout' + (1 = LCD and 2 = CRT). If videoout is undefined, CRT is + assumed. + + For the CT69000 and SMI_LYNXEM drivers, videomode is + selected via environment 'videomode'. Two diferent ways + are possible: + - "videomode=num" 'num' is a standard LiLo mode numbers. + Following standard modes are supported (* is default): + + Colors 640x480 800x600 1024x768 1152x864 1280x1024 + -------------+--------------------------------------------- + 8 bits | 0x301* 0x303 0x305 0x161 0x307 + 15 bits | 0x310 0x313 0x316 0x162 0x319 + 16 bits | 0x311 0x314 0x317 0x163 0x31A + 24 bits | 0x312 0x315 0x318 ? 0x31B + -------------+--------------------------------------------- + (i.e. setenv videomode 317; saveenv; reset;) + + - "videomode=bootargs" all the video parameters are parsed + from the bootargs. (See drivers/videomodes.c) + + + CONFIG_VIDEO_SED13806 + Enable Epson SED13806 driver. This driver supports 8bpp + and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP + or CONFIG_VIDEO_SED13806_16BPP + +- Keyboard Support: + CONFIG_KEYBOARD + + Define this to enable a custom keyboard support. + This simply calls drv_keyboard_init() which must be + defined in your board-specific files. + The only board using this so far is RBC823. + +- LCD Support: CONFIG_LCD + + Define this to enable LCD support (for output to LCD + display); also select one of the supported displays + by defining one of these: + + CONFIG_NEC_NL6448AC33: + + NEC NL6448AC33-18. Active, color, single scan. + + CONFIG_NEC_NL6448BC20 + + NEC NL6448BC20-08. 6.5", 640x480. + Active, color, single scan. + + CONFIG_NEC_NL6448BC33_54 + + NEC NL6448BC33-54. 10.4", 640x480. + Active, color, single scan. + + CONFIG_SHARP_16x9 + + Sharp 320x240. Active, color, single scan. + It isn't 16x9, and I am not sure what it is. + + CONFIG_SHARP_LQ64D341 + + Sharp LQ64D341 display, 640x480. + Active, color, single scan. + + CONFIG_HLD1045 + + HLD1045 display, 640x480. + Active, color, single scan. + + CONFIG_OPTREX_BW + + Optrex CBL50840-2 NF-FW 99 22 M5 + or + Hitachi LMG6912RPFC-00T + or + Hitachi SP14Q002 + + 320x240. Black & white. + + Normally display is black on white background; define + CFG_WHITE_ON_BLACK to get it inverted. + +- Splash Screen Support: CONFIG_SPLASH_SCREEN + + If this option is set, the environment is checked for + a variable "splashimage". If found, the usual display + of logo, copyright and system information on the LCD + is suppressed and the BMP image at the address + specified in "splashimage" is loaded instead. The + console is redirected to the "nulldev", too. This + allows for a "silent" boot where a splash screen is + loaded very quickly after power-on. + +- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP + + If this option is set, additionally to standard BMP + images, gzipped BMP images can be displayed via the + splashscreen support or the bmp command. + +- Compression support: + CONFIG_BZIP2 + + If this option is set, support for bzip2 compressed + images is included. If not, only uncompressed and gzip + compressed images are supported. + + NOTE: the bzip2 algorithm requires a lot of RAM, so + the malloc area (as defined by CFG_MALLOC_LEN) should + be at least 4MB. + +- MII/PHY support: + CONFIG_PHY_ADDR + + The address of PHY on MII bus. + + CONFIG_PHY_CLOCK_FREQ (ppc4xx) + + The clock frequency of the MII bus + + CONFIG_PHY_GIGE + + If this option is set, support for speed/duplex + detection of Gigabit PHY is included. + + CONFIG_PHY_RESET_DELAY + + Some PHY like Intel LXT971A need extra delay after + reset before any MII register access is possible. + For such PHY, set this option to the usec delay + required. (minimum 300usec for LXT971A) + + CONFIG_PHY_CMD_DELAY (ppc4xx) + + Some PHY like Intel LXT971A need extra delay after + command issued before MII status register can be read + +- Ethernet address: + CONFIG_ETHADDR + CONFIG_ETH2ADDR + CONFIG_ETH3ADDR + + Define a default value for ethernet address to use + for the respective ethernet interface, in case this + is not determined automatically. + +- IP address: + CONFIG_IPADDR + + Define a default value for the IP address to use for + the default ethernet interface, in case this is not + determined through e.g. bootp. + +- Server IP address: + CONFIG_SERVERIP + + Defines a default value for theIP address of a TFTP + server to contact when using the "tftboot" command. + +- BOOTP Recovery Mode: + CONFIG_BOOTP_RANDOM_DELAY + + If you have many targets in a network that try to + boot using BOOTP, you may want to avoid that all + systems send out BOOTP requests at precisely the same + moment (which would happen for instance at recovery + from a power failure, when all systems will try to + boot, thus flooding the BOOTP server. Defining + CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be + inserted before sending out BOOTP requests. The + following delays are insterted then: + + 1st BOOTP request: delay 0 ... 1 sec + 2nd BOOTP request: delay 0 ... 2 sec + 3rd BOOTP request: delay 0 ... 4 sec + 4th and following + BOOTP requests: delay 0 ... 8 sec + +- DHCP Advanced Options: + CONFIG_BOOTP_MASK + + You can fine tune the DHCP functionality by adding + these flags to the CONFIG_BOOTP_MASK define: + + CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS + serverip from a DHCP server, it is possible that more + than one DNS serverip is offered to the client. + If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS + serverip will be stored in the additional environment + variable "dnsip2". The first DNS serverip is always + stored in the variable "dnsip", when CONFIG_BOOTP_DNS + is added to the CONFIG_BOOTP_MASK. + + CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable + to do a dynamic update of a DNS server. To do this, they + need the hostname of the DHCP requester. + If CONFIG_BOOP_SEND_HOSTNAME is added to the + CONFIG_BOOTP_MASK, the content of the "hostname" + environment variable is passed as option 12 to + the DHCP server. + + - CDP Options: + CONFIG_CDP_DEVICE_ID + + The device id used in CDP trigger frames. + + CONFIG_CDP_DEVICE_ID_PREFIX + + A two character string which is prefixed to the MAC address + of the device. + + CONFIG_CDP_PORT_ID + + A printf format string which contains the ascii name of + the port. Normally is set to "eth%d" which sets + eth0 for the first ethernet, eth1 for the second etc. + + CONFIG_CDP_CAPABILITIES + + A 32bit integer which indicates the device capabilities; + 0x00000010 for a normal host which does not forwards. + + CONFIG_CDP_VERSION + + An ascii string containing the version of the software. + + CONFIG_CDP_PLATFORM + + An ascii string containing the name of the platform. + + CONFIG_CDP_TRIGGER + + A 32bit integer sent on the trigger. + + CONFIG_CDP_POWER_CONSUMPTION + + A 16bit integer containing the power consumption of the + device in .1 of milliwatts. + + CONFIG_CDP_APPLIANCE_VLAN_TYPE + + A byte containing the id of the VLAN. + +- Status LED: CONFIG_STATUS_LED + + Several configurations allow to display the current + status using a LED. For instance, the LED will blink + fast while running U-Boot code, stop blinking as + soon as a reply to a BOOTP request was received, and + start blinking slow once the Linux kernel is running + (supported by a status LED driver in the Linux + kernel). Defining CONFIG_STATUS_LED enables this + feature in U-Boot. + +- CAN Support: CONFIG_CAN_DRIVER + + Defining CONFIG_CAN_DRIVER enables CAN driver support + on those systems that support this (optional) + feature, like the TQM8xxL modules. + +- I2C Support: CONFIG_HARD_I2C | CONFIG_SOFT_I2C + + These enable I2C serial bus commands. Defining either of + (but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will + include the appropriate I2C driver for the selected cpu. + + This will allow you to use i2c commands at the u-boot + command line (as long as you set CFG_CMD_I2C in + CONFIG_COMMANDS) and communicate with i2c based realtime + clock chips. See common/cmd_i2c.c for a description of the + command line interface. + + CONFIG_HARD_I2C selects the CPM hardware driver for I2C. + + CONFIG_SOFT_I2C configures u-boot to use a software (aka + bit-banging) driver instead of CPM or similar hardware + support for I2C. + + There are several other quantities that must also be + defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C. + + In both cases you will need to define CFG_I2C_SPEED + to be the frequency (in Hz) at which you wish your i2c bus + to run and CFG_I2C_SLAVE to be the address of this node (ie + the cpu's i2c node address). + + Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c) + sets the cpu up as a master node and so its address should + therefore be cleared to 0 (See, eg, MPC823e User's Manual + p.16-473). So, set CFG_I2C_SLAVE to 0. + + That's all that's required for CONFIG_HARD_I2C. + + If you use the software i2c interface (CONFIG_SOFT_I2C) + then the following macros need to be defined (examples are + from include/configs/lwmon.h): + + I2C_INIT + + (Optional). Any commands necessary to enable the I2C + controller or configure ports. + + eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) + + I2C_PORT + + (Only for MPC8260 CPU). The I/O port to use (the code + assumes both bits are on the same port). Valid values + are 0..3 for ports A..D. + + I2C_ACTIVE + + The code necessary to make the I2C data line active + (driven). If the data line is open collector, this + define can be null. + + eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) + + I2C_TRISTATE + + The code necessary to make the I2C data line tri-stated + (inactive). If the data line is open collector, this + define can be null. + + eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) + + I2C_READ + + Code that returns TRUE if the I2C data line is high, + FALSE if it is low. + + eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) + + I2C_SDA(bit) + + If is TRUE, sets the I2C data line high. If it + is FALSE, it clears it (low). + + eg: #define I2C_SDA(bit) \ + if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA + + I2C_SCL(bit) + + If is TRUE, sets the I2C clock line high. If it + is FALSE, it clears it (low). + + eg: #define I2C_SCL(bit) \ + if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL + + I2C_DELAY + + This delay is invoked four times per clock cycle so this + controls the rate of data transfer. The data rate thus + is 1 / (I2C_DELAY * 4). Often defined to be something + like: + + #define I2C_DELAY udelay(2) + + CFG_I2C_INIT_BOARD + + When a board is reset during an i2c bus transfer + chips might think that the current transfer is still + in progress. On some boards it is possible to access + the i2c SCLK line directly, either by using the + processor pin as a GPIO or by having a second pin + connected to the bus. If this option is defined a + custom i2c_init_board() routine in boards/xxx/board.c + is run early in the boot sequence. + + CONFIG_I2CFAST (PPC405GP|PPC405EP only) + + This option enables configuration of bi_iic_fast[] flags + in u-boot bd_info structure based on u-boot environment + variable "i2cfast". (see also i2cfast) + +- SPI Support: CONFIG_SPI + + Enables SPI driver (so far only tested with + SPI EEPROM, also an instance works with Crystal A/D and + D/As on the SACSng board) + + CONFIG_SPI_X + + Enables extended (16-bit) SPI EEPROM addressing. + (symmetrical to CONFIG_I2C_X) + + CONFIG_SOFT_SPI + + Enables a software (bit-bang) SPI driver rather than + using hardware support. This is a general purpose + driver that only requires three general I/O port pins + (two outputs, one input) to function. If this is + defined, the board configuration must define several + SPI configuration items (port pins to use, etc). For + an example, see include/configs/sacsng.h. + +- FPGA Support: CONFIG_FPGA_COUNT + + Specify the number of FPGA devices to support. + + CONFIG_FPGA + + Used to specify the types of FPGA devices. For example, + #define CONFIG_FPGA CFG_XILINX_VIRTEX2 + + CFG_FPGA_PROG_FEEDBACK + + Enable printing of hash marks during FPGA configuration. + + CFG_FPGA_CHECK_BUSY + + Enable checks on FPGA configuration interface busy + status by the configuration function. This option + will require a board or device specific function to + be written. + + CONFIG_FPGA_DELAY + + If defined, a function that provides delays in the FPGA + configuration driver. + + CFG_FPGA_CHECK_CTRLC + Allow Control-C to interrupt FPGA configuration + + CFG_FPGA_CHECK_ERROR + + Check for configuration errors during FPGA bitfile + loading. For example, abort during Virtex II + configuration if the INIT_B line goes low (which + indicated a CRC error). + + CFG_FPGA_WAIT_INIT + + Maximum time to wait for the INIT_B line to deassert + after PROB_B has been deasserted during a Virtex II + FPGA configuration sequence. The default time is 500 + mS. + + CFG_FPGA_WAIT_BUSY + + Maximum time to wait for BUSY to deassert during + Virtex II FPGA configuration. The default is 5 mS. + + CFG_FPGA_WAIT_CONFIG + + Time to wait after FPGA configuration. The default is + 200 mS. + +- Configuration Management: + CONFIG_IDENT_STRING + + If defined, this string will be added to the U-Boot + version information (U_BOOT_VERSION) + +- Vendor Parameter Protection: + + U-Boot considers the values of the environment + variables "serial#" (Board Serial Number) and + "ethaddr" (Ethernet Address) to be parameters that + are set once by the board vendor / manufacturer, and + protects these variables from casual modification by + the user. Once set, these variables are read-only, + and write or delete attempts are rejected. You can + change this behviour: + + If CONFIG_ENV_OVERWRITE is #defined in your config + file, the write protection for vendor parameters is + completely disabled. Anybody can change or delete + these parameters. + + Alternatively, if you #define _both_ CONFIG_ETHADDR + _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default + ethernet address is installed in the environment, + which can be changed exactly ONCE by the user. [The + serial# is unaffected by this, i. e. it remains + read-only.] + +- Protected RAM: + CONFIG_PRAM + + Define this variable to enable the reservation of + "protected RAM", i. e. RAM which is not overwritten + by U-Boot. Define CONFIG_PRAM to hold the number of + kB you want to reserve for pRAM. You can overwrite + this default value by defining an environment + variable "pram" to the number of kB you want to + reserve. Note that the board info structure will + still show the full amount of RAM. If pRAM is + reserved, a new environment variable "mem" will + automatically be defined to hold the amount of + remaining RAM in a form that can be passed as boot + argument to Linux, for instance like that: + + setenv bootargs ... mem=\${mem} + saveenv + + This way you can tell Linux not to use this memory, + either, which results in a memory region that will + not be affected by reboots. + + *WARNING* If your board configuration uses automatic + detection of the RAM size, you must make sure that + this memory test is non-destructive. So far, the + following board configurations are known to be + "pRAM-clean": + + ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL, + HERMES, IP860, RPXlite, LWMON, LANTEC, + PCU_E, FLAGADM, TQM8260 + +- Error Recovery: + CONFIG_PANIC_HANG + + Define this variable to stop the system in case of a + fatal error, so that you have to reset it manually. + This is probably NOT a good idea for an embedded + system where you want to system to reboot + automatically as fast as possible, but it may be + useful during development since you can try to debug + the conditions that lead to the situation. + + CONFIG_NET_RETRY_COUNT + + This variable defines the number of retries for + network operations like ARP, RARP, TFTP, or BOOTP + before giving up the operation. If not defined, a + default value of 5 is used. + +- Command Interpreter: + CFG_AUTO_COMPLETE + + Enable auto completion of commands using TAB. + + CFG_HUSH_PARSER + + Define this variable to enable the "hush" shell (from + Busybox) as command line interpreter, thus enabling + powerful command line syntax like + if...then...else...fi conditionals or `&&' and '||' + constructs ("shell scripts"). + + If undefined, you get the old, much simpler behaviour + with a somewhat smaller memory footprint. + + + CFG_PROMPT_HUSH_PS2 + + This defines the secondary prompt string, which is + printed when the command interpreter needs more input + to complete a command. Usually "> ". + + Note: + + In the current implementation, the local variables + space and global environment variables space are + separated. Local variables are those you define by + simply typing `name=value'. To access a local + variable later on, you have write `$name' or + `${name}'; to execute the contents of a variable + directly type `$name' at the command prompt. + + Global environment variables are those you use + setenv/printenv to work with. To run a command stored + in such a variable, you need to use the run command, + and you must not use the '$' sign to access them. + + To store commands and special characters in a + variable, please use double quotation marks + surrounding the whole text of the variable, instead + of the backslashes before semicolons and special + symbols. + +- Default Environment: + CONFIG_EXTRA_ENV_SETTINGS + + Define this to contain any number of null terminated + strings (variable = value pairs) that will be part of + the default environment compiled into the boot image. + + For example, place something like this in your + board's config file: + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "myvar1=value1\0" \ + "myvar2=value2\0" + + Warning: This method is based on knowledge about the + internal format how the environment is stored by the + U-Boot code. This is NOT an official, exported + interface! Although it is unlikely that this format + will change soon, there is no guarantee either. + You better know what you are doing here. + + Note: overly (ab)use of the default environment is + discouraged. Make sure to check other ways to preset + the environment like the autoscript function or the + boot command first. + +- DataFlash Support: + CONFIG_HAS_DATAFLASH + + Defining this option enables DataFlash features and + allows to read/write in Dataflash via the standard + commands cp, md... + +- SystemACE Support: + CONFIG_SYSTEMACE + + Adding this option adds support for Xilinx SystemACE + chips attached via some sort of local bus. The address + of the chip must alsh be defined in the + CFG_SYSTEMACE_BASE macro. For example: + + #define CONFIG_SYSTEMACE + #define CFG_SYSTEMACE_BASE 0xf0000000 + + When SystemACE support is added, the "ace" device type + becomes available to the fat commands, i.e. fatls. + +- TFTP Fixed UDP Port: + CONFIG_TFTP_PORT + + If this is defined, the environment variable tftpsrcp + is used to supply the TFTP UDP source port value. + If tftpsrcp isn't defined, the normal pseudo-random port + number generator is used. + + Also, the environment variable tftpdstp is used to supply + the TFTP UDP destination port value. If tftpdstp isn't + defined, the normal port 69 is used. + + The purpose for tftpsrcp is to allow a TFTP server to + blindly start the TFTP transfer using the pre-configured + target IP address and UDP port. This has the effect of + "punching through" the (Windows XP) firewall, allowing + the remainder of the TFTP transfer to proceed normally. + A better solution is to properly configure the firewall, + but sometimes that is not allowed. + +- Show boot progress: + CONFIG_SHOW_BOOT_PROGRESS + + Defining this option allows to add some board- + specific code (calling a user-provided function + "show_boot_progress(int)") that enables you to show + the system's boot progress on some display (for + example, some LED's) on your board. At the moment, + the following checkpoints are implemented: + + Arg Where When + 1 common/cmd_bootm.c before attempting to boot an image + -1 common/cmd_bootm.c Image header has bad magic number + 2 common/cmd_bootm.c Image header has correct magic number + -2 common/cmd_bootm.c Image header has bad checksum + 3 common/cmd_bootm.c Image header has correct checksum + -3 common/cmd_bootm.c Image data has bad checksum + 4 common/cmd_bootm.c Image data has correct checksum + -4 common/cmd_bootm.c Image is for unsupported architecture + 5 common/cmd_bootm.c Architecture check OK + -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi, standalone) + 6 common/cmd_bootm.c Image Type check OK + -6 common/cmd_bootm.c gunzip uncompression error + -7 common/cmd_bootm.c Unimplemented compression type + 7 common/cmd_bootm.c Uncompression OK + -8 common/cmd_bootm.c Wrong Image Type (not kernel, multi, standalone) + 8 common/cmd_bootm.c Image Type check OK + -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX) + 9 common/cmd_bootm.c Start initial ramdisk verification + -10 common/cmd_bootm.c Ramdisk header has bad magic number + -11 common/cmd_bootm.c Ramdisk header has bad checksum + 10 common/cmd_bootm.c Ramdisk header is OK + -12 common/cmd_bootm.c Ramdisk data has bad checksum + 11 common/cmd_bootm.c Ramdisk data has correct checksum + 12 common/cmd_bootm.c Ramdisk verification complete, start loading + -13 common/cmd_bootm.c Wrong Image Type (not PPC Linux Ramdisk) + 13 common/cmd_bootm.c Start multifile image verification + 14 common/cmd_bootm.c No initial ramdisk, no multifile, continue. + 15 common/cmd_bootm.c All preparation done, transferring control to OS + + -30 lib_ppc/board.c Fatal error, hang the system + -31 post/post.c POST test failed, detected by post_output_backlog() + -32 post/post.c POST test failed, detected by post_run_single() + + -1 common/cmd_doc.c Bad usage of "doc" command + -1 common/cmd_doc.c No boot device + -1 common/cmd_doc.c Unknown Chip ID on boot device + -1 common/cmd_doc.c Read Error on boot device + -1 common/cmd_doc.c Image header has bad magic number + + -1 common/cmd_ide.c Bad usage of "ide" command + -1 common/cmd_ide.c No boot device + -1 common/cmd_ide.c Unknown boot device + -1 common/cmd_ide.c Unknown partition table + -1 common/cmd_ide.c Invalid partition type + -1 common/cmd_ide.c Read Error on boot device + -1 common/cmd_ide.c Image header has bad magic number + + -1 common/cmd_nand.c Bad usage of "nand" command + -1 common/cmd_nand.c No boot device + -1 common/cmd_nand.c Unknown Chip ID on boot device + -1 common/cmd_nand.c Read Error on boot device + -1 common/cmd_nand.c Image header has bad magic number + + -1 common/env_common.c Environment has a bad CRC, using default + + +Modem Support: +-------------- + +[so far only for SMDK2400 and TRAB boards] + +- Modem support endable: + CONFIG_MODEM_SUPPORT + +- RTS/CTS Flow control enable: + CONFIG_HWFLOW + +- Modem debug support: + CONFIG_MODEM_SUPPORT_DEBUG + + Enables debugging stuff (char screen[1024], dbg()) + for modem support. Useful only with BDI2000. + +- Interrupt support (PPC): + + There are common interrupt_init() and timer_interrupt() + for all PPC archs. interrupt_init() calls interrupt_init_cpu() + for cpu specific initialization. interrupt_init_cpu() + should set decrementer_count to appropriate value. If + cpu resets decrementer automatically after interrupt + (ppc4xx) it should set decrementer_count to zero. + timer_interrupt() calls timer_interrupt_cpu() for cpu + specific handling. If board has watchdog / status_led + / other_activity_monitor it works automatically from + general timer_interrupt(). + +- General: + + In the target system modem support is enabled when a + specific key (key combination) is pressed during + power-on. Otherwise U-Boot will boot normally + (autoboot). The key_pressed() fuction is called from + board_init(). Currently key_pressed() is a dummy + function, returning 1 and thus enabling modem + initialization. + + If there are no modem init strings in the + environment, U-Boot proceed to autoboot; the + previous output (banner, info printfs) will be + supressed, though. + + See also: doc/README.Modem + + +Configuration Settings: +----------------------- + +- CFG_LONGHELP: Defined when you want long help messages included; + undefine this when you're short of memory. + +- CFG_PROMPT: This is what U-Boot prints on the console to + prompt for user input. + +- CFG_CBSIZE: Buffer size for input from the Console + +- CFG_PBSIZE: Buffer size for Console output + +- CFG_MAXARGS: max. Number of arguments accepted for monitor commands + +- CFG_BARGSIZE: Buffer size for Boot Arguments which are passed to + the application (usually a Linux kernel) when it is + booted + +- CFG_BAUDRATE_TABLE: + List of legal baudrate settings for this board. + +- CFG_CONSOLE_INFO_QUIET + Suppress display of console information at boot. + +- CFG_CONSOLE_IS_IN_ENV + If the board specific function + extern int overwrite_console (void); + returns 1, the stdin, stderr and stdout are switched to the + serial port, else the settings in the environment are used. + +- CFG_CONSOLE_OVERWRITE_ROUTINE + Enable the call to overwrite_console(). + +- CFG_CONSOLE_ENV_OVERWRITE + Enable overwrite of previous console environment settings. + +- CFG_MEMTEST_START, CFG_MEMTEST_END: + Begin and End addresses of the area used by the + simple memory test. + +- CFG_ALT_MEMTEST: + Enable an alternate, more extensive memory test. + +- CFG_MEMTEST_SCRATCH: + Scratch address used by the alternate memory test + You only need to set this if address zero isn't writeable + +- CFG_TFTP_LOADADDR: + Default load address for network file downloads + +- CFG_LOADS_BAUD_CHANGE: + Enable temporary baudrate change while serial download + +- CFG_SDRAM_BASE: + Physical start address of SDRAM. _Must_ be 0 here. + +- CFG_MBIO_BASE: + Physical start address of Motherboard I/O (if using a + Cogent motherboard) + +- CFG_FLASH_BASE: + Physical start address of Flash memory. + +- CFG_MONITOR_BASE: + Physical start address of boot monitor code (set by + make config files to be same as the text base address + (TEXT_BASE) used when linking) - same as + CFG_FLASH_BASE when booting from flash. + +- CFG_MONITOR_LEN: + Size of memory reserved for monitor code, used to + determine _at_compile_time_ (!) if the environment is + embedded within the U-Boot image, or in a separate + flash sector. + +- CFG_MALLOC_LEN: + Size of DRAM reserved for malloc() use. + +- CFG_BOOTMAPSZ: + Maximum size of memory mapped by the startup code of + the Linux kernel; all data that must be processed by + the Linux kernel (bd_info, boot arguments, eventually + initrd image) must be put below this limit. + +- CFG_MAX_FLASH_BANKS: + Max number of Flash memory banks + +- CFG_MAX_FLASH_SECT: + Max number of sectors on a Flash chip + +- CFG_FLASH_ERASE_TOUT: + Timeout for Flash erase operations (in ms) + +- CFG_FLASH_WRITE_TOUT: + Timeout for Flash write operations (in ms) + +- CFG_FLASH_LOCK_TOUT + Timeout for Flash set sector lock bit operation (in ms) + +- CFG_FLASH_UNLOCK_TOUT + Timeout for Flash clear lock bits operation (in ms) + +- CFG_FLASH_PROTECTION + If defined, hardware flash sectors protection is used + instead of U-Boot software protection. + +- CFG_DIRECT_FLASH_TFTP: + + Enable TFTP transfers directly to flash memory; + without this option such a download has to be + performed in two steps: (1) download to RAM, and (2) + copy from RAM to flash. + + The two-step approach is usually more reliable, since + you can check if the download worked before you erase + the flash, but in some situations (when sytem RAM is + too limited to allow for a tempory copy of the + downloaded image) this option may be very useful. + +- CFG_FLASH_CFI: + Define if the flash driver uses extra elements in the + common flash structure for storing flash geometry. + +- CFG_FLASH_CFI_DRIVER + This option also enables the building of the cfi_flash driver + in the drivers directory + +- CFG_FLASH_QUIET_TEST + If this option is defined, the common CFI flash doesn't + print it's warning upon not recognized FLASH banks. This + is useful, if some of the configured banks are only + optionally available. + +- CFG_RX_ETH_BUFFER: + Defines the number of ethernet receive buffers. On some + ethernet controllers it is recommended to set this value + to 8 or even higher (EEPRO100 or 405 EMAC), since all + buffers can be full shortly after enabling the interface + on high ethernet traffic. + Defaults to 4 if not defined. + +The following definitions that deal with the placement and management +of environment data (variable area); in general, we support the +following configurations: + +- CFG_ENV_IS_IN_FLASH: + + Define this if the environment is in flash memory. + + a) The environment occupies one whole flash sector, which is + "embedded" in the text segment with the U-Boot code. This + happens usually with "bottom boot sector" or "top boot + sector" type flash chips, which have several smaller + sectors at the start or the end. For instance, such a + layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In + such a case you would place the environment in one of the + 4 kB sectors - with U-Boot code before and after it. With + "top boot sector" type flash chips, you would put the + environment in one of the last sectors, leaving a gap + between U-Boot and the environment. + + - CFG_ENV_OFFSET: + + Offset of environment data (variable area) to the + beginning of flash memory; for instance, with bottom boot + type flash chips the second sector can be used: the offset + for this sector is given here. + + CFG_ENV_OFFSET is used relative to CFG_FLASH_BASE. + + - CFG_ENV_ADDR: + + This is just another way to specify the start address of + the flash sector containing the environment (instead of + CFG_ENV_OFFSET). + + - CFG_ENV_SECT_SIZE: + + Size of the sector containing the environment. + + + b) Sometimes flash chips have few, equal sized, BIG sectors. + In such a case you don't want to spend a whole sector for + the environment. + + - CFG_ENV_SIZE: + + If you use this in combination with CFG_ENV_IS_IN_FLASH + and CFG_ENV_SECT_SIZE, you can specify to use only a part + of this flash sector for the environment. This saves + memory for the RAM copy of the environment. + + It may also save flash memory if you decide to use this + when your environment is "embedded" within U-Boot code, + since then the remainder of the flash sector could be used + for U-Boot code. It should be pointed out that this is + STRONGLY DISCOURAGED from a robustness point of view: + updating the environment in flash makes it always + necessary to erase the WHOLE sector. If something goes + wrong before the contents has been restored from a copy in + RAM, your target system will be dead. + + - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND + + These settings describe a second storage area used to hold + a redundand copy of the environment data, so that there is + a valid backup copy in case there is a power failure during + a "saveenv" operation. + +BE CAREFUL! Any changes to the flash layout, and some changes to the +source code will make it necessary to adapt /u-boot.lds* +accordingly! + + +- CFG_ENV_IS_IN_NVRAM: + + Define this if you have some non-volatile memory device + (NVRAM, battery buffered SRAM) which you want to use for the + environment. + + - CFG_ENV_ADDR: + - CFG_ENV_SIZE: + + These two #defines are used to determin the memory area you + want to use for environment. It is assumed that this memory + can just be read and written to, without any special + provision. + +BE CAREFUL! The first access to the environment happens quite early +in U-Boot initalization (when we try to get the setting of for the +console baudrate). You *MUST* have mappend your NVRAM area then, or +U-Boot will hang. + +Please note that even with NVRAM we still use a copy of the +environment in RAM: we could work on NVRAM directly, but we want to +keep settings there always unmodified except somebody uses "saveenv" +to save the current settings. + + +- CFG_ENV_IS_IN_EEPROM: + + Use this if you have an EEPROM or similar serial access + device and a driver for it. + + - CFG_ENV_OFFSET: + - CFG_ENV_SIZE: + + These two #defines specify the offset and size of the + environment area within the total memory of your EEPROM. + + - CFG_I2C_EEPROM_ADDR: + If defined, specified the chip address of the EEPROM device. + The default address is zero. + + - CFG_EEPROM_PAGE_WRITE_BITS: + If defined, the number of bits used to address bytes in a + single page in the EEPROM device. A 64 byte page, for example + would require six bits. + + - CFG_EEPROM_PAGE_WRITE_DELAY_MS: + If defined, the number of milliseconds to delay between + page writes. The default is zero milliseconds. + + - CFG_I2C_EEPROM_ADDR_LEN: + The length in bytes of the EEPROM memory array address. Note + that this is NOT the chip address length! + + - CFG_I2C_EEPROM_ADDR_OVERFLOW: + EEPROM chips that implement "address overflow" are ones + like Catalyst 24WC04/08/16 which has 9/10/11 bits of + address and the extra bits end up in the "chip address" bit + slots. This makes a 24WC08 (1Kbyte) chip look like four 256 + byte chips. + + Note that we consider the length of the address field to + still be one byte because the extra address bits are hidden + in the chip address. + + - CFG_EEPROM_SIZE: + The size in bytes of the EEPROM device. + + +- CFG_ENV_IS_IN_DATAFLASH: + + Define this if you have a DataFlash memory device which you + want to use for the environment. + + - CFG_ENV_OFFSET: + - CFG_ENV_ADDR: + - CFG_ENV_SIZE: + + These three #defines specify the offset and size of the + environment area within the total memory of your DataFlash placed + at the specified address. + +- CFG_ENV_IS_IN_NAND: + + Define this if you have a NAND device which you want to use + for the environment. + + - CFG_ENV_OFFSET: + - CFG_ENV_SIZE: + + These two #defines specify the offset and size of the environment + area within the first NAND device. + +- CFG_SPI_INIT_OFFSET + + Defines offset to the initial SPI buffer area in DPRAM. The + area is used at an early stage (ROM part) if the environment + is configured to reside in the SPI EEPROM: We need a 520 byte + scratch DPRAM area. It is used between the two initialization + calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems + to be a good choice since it makes it far enough from the + start of the data area as well as from the stack pointer. + +Please note that the environment is read-only as long as the monitor +has been relocated to RAM and a RAM copy of the environment has been +created; also, when using EEPROM you will have to use getenv_r() +until then to read environment variables. + +The environment is protected by a CRC32 checksum. Before the monitor +is relocated into RAM, as a result of a bad CRC you will be working +with the compiled-in default environment - *silently*!!! [This is +necessary, because the first environment variable we need is the +"baudrate" setting for the console - if we have a bad CRC, we don't +have any device yet where we could complain.] + +Note: once the monitor has been relocated, then it will complain if +the default environment is used; a new CRC is computed as soon as you +use the "saveenv" command to store a valid environment. + +- CFG_FAULT_ECHO_LINK_DOWN: + Echo the inverted Ethernet link state to the fault LED. + + Note: If this option is active, then CFG_FAULT_MII_ADDR + also needs to be defined. + +- CFG_FAULT_MII_ADDR: + MII address of the PHY to check for the Ethernet link state. + +- CFG_64BIT_VSPRINTF: + Makes vsprintf (and all *printf functions) support printing + of 64bit values by using the L quantifier + +- CFG_64BIT_STRTOUL: + Adds simple_strtoull that returns a 64bit value + +Low Level (hardware related) configuration options: +--------------------------------------------------- + +- CFG_CACHELINE_SIZE: + Cache Line Size of the CPU. + +- CFG_DEFAULT_IMMR: + Default address of the IMMR after system reset. + + Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, + and RPXsuper) to be able to adjust the position of + the IMMR register after a reset. + +- Floppy Disk Support: + CFG_FDC_DRIVE_NUMBER + + the default drive number (default value 0) + + CFG_ISA_IO_STRIDE + + defines the spacing between fdc chipset registers + (default value 1) + + CFG_ISA_IO_OFFSET + + defines the offset of register from address. It + depends on which part of the data bus is connected to + the fdc chipset. (default value 0) + + If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and + CFG_FDC_DRIVE_NUMBER are undefined, they take their + default value. + + if CFG_FDC_HW_INIT is defined, then the function + fdc_hw_init() is called at the beginning of the FDC + setup. fdc_hw_init() must be provided by the board + source code. It is used to make hardware dependant + initializations. + +- CFG_IMMR: Physical address of the Internal Memory. + DO NOT CHANGE unless you know exactly what you're + doing! (11-4) [MPC8xx/82xx systems only] + +- CFG_INIT_RAM_ADDR: + + Start address of memory area that can be used for + initial data and stack; please note that this must be + writable memory that is working WITHOUT special + initialization, i. e. you CANNOT use normal RAM which + will become available only after programming the + memory controller and running certain initialization + sequences. + + U-Boot uses the following memory types: + - MPC8xx and MPC8260: IMMR (internal memory of the CPU) + - MPC824X: data cache + - PPC4xx: data cache + +- CFG_GBL_DATA_OFFSET: + + Offset of the initial data structure in the memory + area defined by CFG_INIT_RAM_ADDR. Usually + CFG_GBL_DATA_OFFSET is chosen such that the initial + data is located at the end of the available space + (sometimes written as (CFG_INIT_RAM_END - + CFG_INIT_DATA_SIZE), and the initial stack is just + below that area (growing from (CFG_INIT_RAM_ADDR + + CFG_GBL_DATA_OFFSET) downward. + + Note: + On the MPC824X (or other systems that use the data + cache for initial memory) the address chosen for + CFG_INIT_RAM_ADDR is basically arbitrary - it must + point to an otherwise UNUSED address space between + the top of RAM and the start of the PCI space. + +- CFG_SIUMCR: SIU Module Configuration (11-6) + +- CFG_SYPCR: System Protection Control (11-9) + +- CFG_TBSCR: Time Base Status and Control (11-26) + +- CFG_PISCR: Periodic Interrupt Status and Control (11-31) + +- CFG_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) + +- CFG_SCCR: System Clock and reset Control Register (15-27) + +- CFG_OR_TIMING_SDRAM: + SDRAM timing + +- CFG_MAMR_PTA: + periodic timer for refresh + +- CFG_DER: Debug Event Register (37-47) + +- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CFG_REMAP_OR_AM, + CFG_PRELIM_OR_AM, CFG_OR_TIMING_FLASH, CFG_OR0_REMAP, + CFG_OR0_PRELIM, CFG_BR0_PRELIM, CFG_OR1_REMAP, CFG_OR1_PRELIM, + CFG_BR1_PRELIM: + Memory Controller Definitions: BR0/1 and OR0/1 (FLASH) + +- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE, + CFG_OR_TIMING_SDRAM, CFG_OR2_PRELIM, CFG_BR2_PRELIM, + CFG_OR3_PRELIM, CFG_BR3_PRELIM: + Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM) + +- CFG_MAMR_PTA, CFG_MPTPR_2BK_4K, CFG_MPTPR_1BK_4K, CFG_MPTPR_2BK_8K, + CFG_MPTPR_1BK_8K, CFG_MAMR_8COL, CFG_MAMR_9COL: + Machine Mode Register and Memory Periodic Timer + Prescaler definitions (SDRAM timing) + +- CFG_I2C_UCODE_PATCH, CFG_I2C_DPMEM_OFFSET [0x1FC0]: + enable I2C microcode relocation patch (MPC8xx); + define relocation offset in DPRAM [DSP2] + +- CFG_SPI_UCODE_PATCH, CFG_SPI_DPMEM_OFFSET [0x1FC0]: + enable SPI microcode relocation patch (MPC8xx); + define relocation offset in DPRAM [SCC4] + +- CFG_USE_OSCCLK: + Use OSCM clock mode on MBX8xx board. Be careful, + wrong setting might damage your board. Read + doc/README.MBX before setting this variable! + +- CFG_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) + Offset of the bootmode word in DPRAM used by post + (Power On Self Tests). This definition overrides + #define'd default value in commproc.h resp. + cpm_8260.h. + +- CFG_PCI_SLV_MEM_LOCAL, CFG_PCI_SLV_MEM_BUS, CFG_PICMR0_MASK_ATTRIB, + CFG_PCI_MSTR0_LOCAL, CFG_PCIMSK0_MASK, CFG_PCI_MSTR1_LOCAL, + CFG_PCIMSK1_MASK, CFG_PCI_MSTR_MEM_LOCAL, CFG_PCI_MSTR_MEM_BUS, + CFG_CPU_PCI_MEM_START, CFG_PCI_MSTR_MEM_SIZE, CFG_POCMR0_MASK_ATTRIB, + CFG_PCI_MSTR_MEMIO_LOCAL, CFG_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START, + CFG_PCI_MSTR_MEMIO_SIZE, CFG_POCMR1_MASK_ATTRIB, CFG_PCI_MSTR_IO_LOCAL, + CFG_PCI_MSTR_IO_BUS, CFG_CPU_PCI_IO_START, CFG_PCI_MSTR_IO_SIZE, + CFG_POCMR2_MASK_ATTRIB: (MPC826x only) + Overrides the default PCI memory map in cpu/mpc8260/pci.c if set. + +- CONFIG_ETHER_ON_FEC[12] + Define to enable FEC[12] on a 8xx series processor. + +- CONFIG_FEC[12]_PHY + Define to the hardcoded PHY address which corresponds + to the given FEC; i. e. + #define CONFIG_FEC1_PHY 4 + means that the PHY with address 4 is connected to FEC1 + + When set to -1, means to probe for first available. + +- CONFIG_FEC[12]_PHY_NORXERR + The PHY does not have a RXERR line (RMII only). + (so program the FEC to ignore it). + +- CONFIG_RMII + Enable RMII mode for all FECs. + Note that this is a global option, we can't + have one FEC in standard MII mode and another in RMII mode. + +- CONFIG_CRC32_VERIFY + Add a verify option to the crc32 command. + The syntax is: + + => crc32 -v
+ + Where address/count indicate a memory area + and crc32 is the correct crc32 which the + area should have. + +- CONFIG_LOOPW + Add the "loopw" memory command. This only takes effect if + the memory commands are activated globally (CFG_CMD_MEM). + +- CONFIG_MX_CYCLIC + Add the "mdc" and "mwc" memory commands. These are cyclic + "md/mw" commands. + Examples: + + => mdc.b 10 4 500 + This command will print 4 bytes (10,11,12,13) each 500 ms. + + => mwc.l 100 12345678 10 + This command will write 12345678 to address 100 all 10 ms. + + This only takes effect if the memory commands are activated + globally (CFG_CMD_MEM). + +- CONFIG_SKIP_LOWLEVEL_INIT +- CONFIG_SKIP_RELOCATE_UBOOT + + [ARM only] If these variables are defined, then + certain low level initializations (like setting up + the memory controller) are omitted and/or U-Boot does + not relocate itself into RAM. + Normally these variables MUST NOT be defined. The + only exception is when U-Boot is loaded (to RAM) by + some other boot loader or by a debugger which + performs these intializations itself. + + +Building the Software: +====================== + +Building U-Boot has been tested in native PPC environments (on a +PowerBook G3 running LinuxPPC 2000) and in cross environments +(running RedHat 6.x and 7.x Linux on x86, Solaris 2.6 on a SPARC, and +NetBSD 1.5 on x86). + +If you are not using a native PPC environment, it is assumed that you +have the GNU cross compiling tools available in your path and named +with a prefix of "powerpc-linux-". If this is not the case, (e.g. if +you are using Monta Vista's Hard Hat Linux CDK 1.2) you must change +the definition of CROSS_COMPILE in Makefile. For HHL on a 4xx CPU, +change it to: + + CROSS_COMPILE = ppc_4xx- + + +U-Boot is intended to be simple to build. After installing the +sources you must configure U-Boot for one specific board type. This +is done by typing: + + make NAME_config + +where "NAME_config" is the name of one of the existing +configurations; the following names are supported: + + ADCIOP_config FPS860L_config omap730p2_config + ADS860_config GEN860T_config pcu_e_config + Alaska8220_config + AR405_config GENIETV_config PIP405_config + at91rm9200dk_config GTH_config QS823_config + CANBT_config hermes_config QS850_config + cmi_mpc5xx_config hymod_config QS860T_config + cogent_common_config IP860_config RPXlite_config + cogent_mpc8260_config IVML24_config RPXlite_DW_config + cogent_mpc8xx_config IVMS8_config RPXsuper_config + CPCI405_config JSE_config rsdproto_config + CPCIISER4_config LANTEC_config Sandpoint8240_config + csb272_config lwmon_config sbc8260_config + CU824_config MBX860T_config sbc8560_33_config + DUET_ADS_config MBX_config sbc8560_66_config + EBONY_config MPC8260ADS_config SM850_config + ELPT860_config MPC8540ADS_config SPD823TS_config + ESTEEM192E_config MPC8540EVAL_config stxgp3_config + ETX094_config MPC8560ADS_config SXNI855T_config + FADS823_config NETVIA_config TQM823L_config + FADS850SAR_config omap1510inn_config TQM850L_config + FADS860T_config omap1610h2_config TQM855L_config + FPS850L_config omap1610inn_config TQM860L_config + omap5912osk_config walnut_config + omap2420h4_config Yukon8220_config + ZPC1900_config + +Note: for some board special configuration names may exist; check if + additional information is available from the board vendor; for + instance, the TQM823L systems are available without (standard) + or with LCD support. You can select such additional "features" + when chosing the configuration, i. e. + + make TQM823L_config + - will configure for a plain TQM823L, i. e. no LCD support + + make TQM823L_LCD_config + - will configure for a TQM823L with U-Boot console on LCD + + etc. + + +Finally, type "make all", and you should get some working U-Boot +images ready for download to / installation on your system: + +- "u-boot.bin" is a raw binary image +- "u-boot" is an image in ELF binary format +- "u-boot.srec" is in Motorola S-Record format + + +Please be aware that the Makefiles assume you are using GNU make, so +for instance on NetBSD you might need to use "gmake" instead of +native "make". + + +If the system board that you have is not listed, then you will need +to port U-Boot to your hardware platform. To do this, follow these +steps: + +1. Add a new configuration option for your board to the toplevel + "Makefile" and to the "MAKEALL" script, using the existing + entries as examples. Note that here and at many other places + boards and other names are listed in alphabetical sort order. Please + keep this order. +2. Create a new directory to hold your board specific code. Add any + files you need. In your board directory, you will need at least + the "Makefile", a ".c", "flash.c" and "u-boot.lds". +3. Create a new configuration file "include/configs/.h" for + your board +3. If you're porting U-Boot to a new CPU, then also create a new + directory to hold your CPU specific code. Add any files you need. +4. Run "make _config" with your new name. +5. Type "make", and you should get a working "u-boot.srec" file + to be installed on your target system. +6. Debug and solve any problems that might arise. + [Of course, this last step is much harder than it sounds.] + + +Testing of U-Boot Modifications, Ports to New Hardware, etc.: +============================================================== + +If you have modified U-Boot sources (for instance added a new board +or support for new devices, a new CPU, etc.) you are expected to +provide feedback to the other developers. The feedback normally takes +the form of a "patch", i. e. a context diff against a certain (latest +official or latest in CVS) version of U-Boot sources. + +But before you submit such a patch, please verify that your modifi- +cation did not break existing code. At least make sure that *ALL* of +the supported boards compile WITHOUT ANY compiler warnings. To do so, +just run the "MAKEALL" script, which will configure and build U-Boot +for ALL supported system. Be warned, this will take a while. You can +select which (cross) compiler to use by passing a `CROSS_COMPILE' +environment variable to the script, i. e. to use the cross tools from +MontaVista's Hard Hat Linux you can type + + CROSS_COMPILE=ppc_8xx- MAKEALL + +or to build on a native PowerPC system you can type + + CROSS_COMPILE=' ' MAKEALL + +See also "U-Boot Porting Guide" below. + + +Monitor Commands - Overview: +============================ + +go - start application at address 'addr' +run - run commands in an environment variable +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +tftpboot- boot image via network using TFTP protocol + and env variables "ipaddr" and "serverip" + (and eventually "gatewayip") +rarpboot- boot image via network using RARP/TFTP protocol +diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd' +loads - load S-Record file over serial line +loadb - load binary file over serial line (kermit mode) +md - memory display +mm - memory modify (auto-incrementing) +nm - memory modify (constant address) +mw - memory write (fill) +cp - memory copy +cmp - memory compare +crc32 - checksum calculation +imd - i2c memory display +imm - i2c memory modify (auto-incrementing) +inm - i2c memory modify (constant address) +imw - i2c memory write (fill) +icrc32 - i2c checksum calculation +iprobe - probe to discover valid I2C chip addresses +iloop - infinite loop on address range +isdram - print SDRAM configuration information +sspi - SPI utility commands +base - print or set address offset +printenv- print environment variables +setenv - set environment variables +saveenv - save environment variables to persistent storage +protect - enable or disable FLASH write protection +erase - erase FLASH memory +flinfo - print FLASH memory information +bdinfo - print Board Info structure +iminfo - print header information for application image +coninfo - print console devices and informations +ide - IDE sub-system +loop - infinite loop on address range +loopw - infinite write loop on address range +mtest - simple RAM test +icache - enable or disable instruction cache +dcache - enable or disable data cache +reset - Perform RESET of the CPU +echo - echo args to console +version - print monitor version +help - print online help +? - alias for 'help' + + +Monitor Commands - Detailed Description: +======================================== + +TODO. + +For now: just type "help ". + + +Environment Variables: +====================== + +U-Boot supports user configuration using Environment Variables which +can be made persistent by saving to Flash memory. + +Environment Variables are set using "setenv", printed using +"printenv", and saved to Flash using "saveenv". Using "setenv" +without a value can be used to delete a variable from the +environment. As long as you don't save the environment you are +working with an in-memory copy. In case the Flash area containing the +environment is erased by accident, a default environment is provided. + +Some configuration options can be set using Environment Variables: + + baudrate - see CONFIG_BAUDRATE + + bootdelay - see CONFIG_BOOTDELAY + + bootcmd - see CONFIG_BOOTCOMMAND + + bootargs - Boot arguments when booting an RTOS image + + bootfile - Name of the image to load with TFTP + + autoload - if set to "no" (any string beginning with 'n'), + "bootp" will just load perform a lookup of the + configuration from the BOOTP server, but not try to + load any image using TFTP + + autostart - if set to "yes", an image loaded using the "bootp", + "rarpboot", "tftpboot" or "diskboot" commands will + be automatically started (by internally calling + "bootm") + + If set to "no", a standalone image passed to the + "bootm" command will be copied to the load address + (and eventually uncompressed), but NOT be started. + This can be used to load and uncompress arbitrary + data. + + i2cfast - (PPC405GP|PPC405EP only) + if set to 'y' configures Linux I2C driver for fast + mode (400kHZ). This environment variable is used in + initialization code. So, for changes to be effective + it must be saved and board must be reset. + + initrd_high - restrict positioning of initrd images: + If this variable is not set, initrd images will be + copied to the highest possible address in RAM; this + is usually what you want since it allows for + maximum initrd size. If for some reason you want to + make sure that the initrd image is loaded below the + CFG_BOOTMAPSZ limit, you can set this environment + variable to a value of "no" or "off" or "0". + Alternatively, you can set it to a maximum upper + address to use (U-Boot will still check that it + does not overwrite the U-Boot stack and data). + + For instance, when you have a system with 16 MB + RAM, and want to reserve 4 MB from use by Linux, + you can do this by adding "mem=12M" to the value of + the "bootargs" variable. However, now you must make + sure that the initrd image is placed in the first + 12 MB as well - this can be done with + + setenv initrd_high 00c00000 + + If you set initrd_high to 0xFFFFFFFF, this is an + indication to U-Boot that all addresses are legal + for the Linux kernel, including addresses in flash + memory. In this case U-Boot will NOT COPY the + ramdisk at all. This may be useful to reduce the + boot time on your system, but requires that this + feature is supported by your Linux kernel. + + ipaddr - IP address; needed for tftpboot command + + loadaddr - Default load address for commands like "bootp", + "rarpboot", "tftpboot", "loadb" or "diskboot" + + loads_echo - see CONFIG_LOADS_ECHO + + serverip - TFTP server IP address; needed for tftpboot command + + bootretry - see CONFIG_BOOT_RETRY_TIME + + bootdelaykey - see CONFIG_AUTOBOOT_DELAY_STR + + bootstopkey - see CONFIG_AUTOBOOT_STOP_STR + + ethprime - When CONFIG_NET_MULTI is enabled controls which + interface is used first. + + ethact - When CONFIG_NET_MULTI is enabled controls which + interface is currently active. For example you + can do the following + + => setenv ethact FEC ETHERNET + => ping 192.168.0.1 # traffic sent on FEC ETHERNET + => setenv ethact SCC ETHERNET + => ping 10.0.0.1 # traffic sent on SCC ETHERNET + + netretry - When set to "no" each network operation will + either succeed or fail without retrying. + When set to "once" the network operation will + fail when all the available network interfaces + are tried once without success. + Useful on scripts which control the retry operation + themselves. + + tftpsrcport - If this is set, the value is used for TFTP's + UDP source port. + + tftpdstport - If this is set, the value is used for TFTP's UDP + destination port instead of the Well Know Port 69. + + vlan - When set to a value < 4095 the traffic over + ethernet is encapsulated/received over 802.1q + VLAN tagged frames. + +The following environment variables may be used and automatically +updated by the network boot commands ("bootp" and "rarpboot"), +depending the information provided by your boot server: + + bootfile - see above + dnsip - IP address of your Domain Name Server + dnsip2 - IP address of your secondary Domain Name Server + gatewayip - IP address of the Gateway (Router) to use + hostname - Target hostname + ipaddr - see above + netmask - Subnet Mask + rootpath - Pathname of the root filesystem on the NFS server + serverip - see above + + +There are two special Environment Variables: + + serial# - contains hardware identification information such + as type string and/or serial number + ethaddr - Ethernet address + +These variables can be set only once (usually during manufacturing of +the board). U-Boot refuses to delete or overwrite these variables +once they have been set once. + + +Further special Environment Variables: + + ver - Contains the U-Boot version string as printed + with the "version" command. This variable is + readonly (see CONFIG_VERSION_VARIABLE). + + +Please note that changes to some configuration parameters may take +only effect after the next boot (yes, that's just like Windoze :-). + + +Command Line Parsing: +===================== + +There are two different command line parsers available with U-Boot: +the old "simple" one, and the much more powerful "hush" shell: + +Old, simple command line parser: +-------------------------------- + +- supports environment variables (through setenv / saveenv commands) +- several commands on one line, separated by ';' +- variable substitution using "... ${name} ..." syntax +- special characters ('$', ';') can be escaped by prefixing with '\', + for example: + setenv bootcmd bootm \${address} +- You can also escape text by enclosing in single apostrophes, for example: + setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off' + +Hush shell: +----------- + +- similar to Bourne shell, with control structures like + if...then...else...fi, for...do...done; while...do...done, + until...do...done, ... +- supports environment ("global") variables (through setenv / saveenv + commands) and local shell variables (through standard shell syntax + "name=value"); only environment variables can be used with "run" + command + +General rules: +-------------- + +(1) If a command line (or an environment variable executed by a "run" + command) contains several commands separated by semicolon, and + one of these commands fails, then the remaining commands will be + executed anyway. + +(2) If you execute several variables with one call to run (i. e. + calling run with a list af variables as arguments), any failing + command will cause "run" to terminate, i. e. the remaining + variables are not executed. + +Note for Redundant Ethernet Interfaces: +======================================= + +Some boards come with redundant ethernet interfaces; U-Boot supports +such configurations and is capable of automatic selection of a +"working" interface when needed. MAC assignment works as follows: + +Network interfaces are numbered eth0, eth1, eth2, ... Corresponding +MAC addresses can be stored in the environment as "ethaddr" (=>eth0), +"eth1addr" (=>eth1), "eth2addr", ... + +If the network interface stores some valid MAC address (for instance +in SROM), this is used as default address if there is NO correspon- +ding setting in the environment; if the corresponding environment +variable is set, this overrides the settings in the card; that means: + +o If the SROM has a valid MAC address, and there is no address in the + environment, the SROM's address is used. + +o If there is no valid address in the SROM, and a definition in the + environment exists, then the value from the environment variable is + used. + +o If both the SROM and the environment contain a MAC address, and + both addresses are the same, this MAC address is used. + +o If both the SROM and the environment contain a MAC address, and the + addresses differ, the value from the environment is used and a + warning is printed. + +o If neither SROM nor the environment contain a MAC address, an error + is raised. + + +Image Formats: +============== + +The "boot" commands of this monitor operate on "image" files which +can be basicly anything, preceeded by a special header; see the +definitions in include/image.h for details; basicly, the header +defines the following image properties: + +* Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD, + 4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks, + LynxOS, pSOS, QNX, RTEMS, ARTOS; + Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS). +* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86, + IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; + Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC). +* Compression Type (uncompressed, gzip, bzip2) +* Load Address +* Entry Point +* Image Name +* Image Timestamp + +The header is marked by a special Magic Number, and both the header +and the data portions of the image are secured against corruption by +CRC32 checksums. + + +Linux Support: +============== + +Although U-Boot should support any OS or standalone application +easily, the main focus has always been on Linux during the design of +U-Boot. + +U-Boot includes many features that so far have been part of some +special "boot loader" code within the Linux kernel. Also, any +"initrd" images to be used are no longer part of one big Linux image; +instead, kernel and "initrd" are separate images. This implementation +serves several purposes: + +- the same features can be used for other OS or standalone + applications (for instance: using compressed images to reduce the + Flash memory footprint) + +- it becomes much easier to port new Linux kernel versions because + lots of low-level, hardware dependent stuff are done by U-Boot + +- the same Linux kernel image can now be used with different "initrd" + images; of course this also means that different kernel images can + be run with the same "initrd". This makes testing easier (you don't + have to build a new "zImage.initrd" Linux image when you just + change a file in your "initrd"). Also, a field-upgrade of the + software is easier now. + + +Linux HOWTO: +============ + +Porting Linux to U-Boot based systems: +--------------------------------------- + +U-Boot cannot save you from doing all the necessary modifications to +configure the Linux device drivers for use with your target hardware +(no, we don't intend to provide a full virtual machine interface to +Linux :-). + +But now you can ignore ALL boot loader code (in arch/ppc/mbxboot). + +Just make sure your machine specific header file (for instance +include/asm-ppc/tqm8xx.h) includes the same definition of the Board +Information structure as we define in include/u-boot.h, and make +sure that your definition of IMAP_ADDR uses the same value as your +U-Boot configuration in CFG_IMMR. + + +Configuring the Linux kernel: +----------------------------- + +No specific requirements for U-Boot. Make sure you have some root +device (initial ramdisk, NFS) for your target system. + + +Building a Linux Image: +----------------------- + +With U-Boot, "normal" build targets like "zImage" or "bzImage" are +not used. If you use recent kernel source, a new build target +"uImage" will exist which automatically builds an image usable by +U-Boot. Most older kernels also have support for a "pImage" target, +which was introduced for our predecessor project PPCBoot and uses a +100% compatible format. + +Example: + + make TQM850L_config + make oldconfig + make dep + make uImage + +The "uImage" build target uses a special tool (in 'tools/mkimage') to +encapsulate a compressed Linux kernel image with header information, +CRC32 checksum etc. for use with U-Boot. This is what we are doing: + +* build a standard "vmlinux" kernel image (in ELF binary format): + +* convert the kernel into a raw binary image: + + ${CROSS_COMPILE}-objcopy -O binary \ + -R .note -R .comment \ + -S vmlinux linux.bin + +* compress the binary image: + + gzip -9 linux.bin + +* package compressed binary image for U-Boot: + + mkimage -A ppc -O linux -T kernel -C gzip \ + -a 0 -e 0 -n "Linux Kernel Image" \ + -d linux.bin.gz uImage + + +The "mkimage" tool can also be used to create ramdisk images for use +with U-Boot, either separated from the Linux kernel image, or +combined into one file. "mkimage" encapsulates the images with a 64 +byte header containing information about target architecture, +operating system, image type, compression method, entry points, time +stamp, CRC32 checksums, etc. + +"mkimage" can be called in two ways: to verify existing images and +print the header information, or to build new images. + +In the first form (with "-l" option) mkimage lists the information +contained in the header of an existing U-Boot image; this includes +checksum verification: + + tools/mkimage -l image + -l ==> list image header information + +The second form (with "-d" option) is used to build a U-Boot image +from a "data file" which is used as image payload: + + tools/mkimage -A arch -O os -T type -C comp -a addr -e ep \ + -n name -d data_file image + -A ==> set architecture to 'arch' + -O ==> set operating system to 'os' + -T ==> set image type to 'type' + -C ==> set compression type 'comp' + -a ==> set load address to 'addr' (hex) + -e ==> set entry point to 'ep' (hex) + -n ==> set image name to 'name' + -d ==> use image data from 'datafile' + +Right now, all Linux kernels for PowerPC systems use the same load +address (0x00000000), but the entry point address depends on the +kernel version: + +- 2.2.x kernels have the entry point at 0x0000000C, +- 2.3.x and later kernels have the entry point at 0x00000000. + +So a typical call to build a U-Boot image would read: + + -> tools/mkimage -n '2.4.4 kernel for TQM850L' \ + > -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \ + > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz \ + > examples/uImage.TQM850L + Image Name: 2.4.4 kernel for TQM850L + Created: Wed Jul 19 02:34:59 2000 + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327.86 kB = 0.32 MB + Load Address: 0x00000000 + Entry Point: 0x00000000 + +To verify the contents of the image (or check for corruption): + + -> tools/mkimage -l examples/uImage.TQM850L + Image Name: 2.4.4 kernel for TQM850L + Created: Wed Jul 19 02:34:59 2000 + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327.86 kB = 0.32 MB + Load Address: 0x00000000 + Entry Point: 0x00000000 + +NOTE: for embedded systems where boot time is critical you can trade +speed for memory and install an UNCOMPRESSED image instead: this +needs more space in Flash, but boots much faster since it does not +need to be uncompressed: + + -> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz + -> tools/mkimage -n '2.4.4 kernel for TQM850L' \ + > -A ppc -O linux -T kernel -C none -a 0 -e 0 \ + > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux \ + > examples/uImage.TQM850L-uncompressed + Image Name: 2.4.4 kernel for TQM850L + Created: Wed Jul 19 02:34:59 2000 + Image Type: PowerPC Linux Kernel Image (uncompressed) + Data Size: 792160 Bytes = 773.59 kB = 0.76 MB + Load Address: 0x00000000 + Entry Point: 0x00000000 + + +Similar you can build U-Boot images from a 'ramdisk.image.gz' file +when your kernel is intended to use an initial ramdisk: + + -> tools/mkimage -n 'Simple Ramdisk Image' \ + > -A ppc -O linux -T ramdisk -C gzip \ + > -d /LinuxPPC/images/SIMPLE-ramdisk.image.gz examples/simple-initrd + Image Name: Simple Ramdisk Image + Created: Wed Jan 12 14:01:50 2000 + Image Type: PowerPC Linux RAMDisk Image (gzip compressed) + Data Size: 566530 Bytes = 553.25 kB = 0.54 MB + Load Address: 0x00000000 + Entry Point: 0x00000000 + + +Installing a Linux Image: +------------------------- + +To downloading a U-Boot image over the serial (console) interface, +you must convert the image to S-Record format: + + objcopy -I binary -O srec examples/image examples/image.srec + +The 'objcopy' does not understand the information in the U-Boot +image header, so the resulting S-Record file will be relative to +address 0x00000000. To load it to a given address, you need to +specify the target address as 'offset' parameter with the 'loads' +command. + +Example: install the image to address 0x40100000 (which on the +TQM8xxL is in the first Flash bank): + + => erase 40100000 401FFFFF + + .......... done + Erased 8 sectors + + => loads 40100000 + ## Ready for S-Record download ... + ~>examples/image.srec + 1 2 3 4 5 6 7 8 9 10 11 12 13 ... + ... + 15989 15990 15991 15992 + [file transfer complete] + [connected] + ## Start Addr = 0x00000000 + + +You can check the success of the download using the 'iminfo' command; +this includes a checksum verification so you can be sure no data +corruption happened: + + => imi 40100000 + + ## Checking Image at 40100000 ... + Image Name: 2.2.13 for initrd on TQM850L + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327 kB = 0 MB + Load Address: 00000000 + Entry Point: 0000000c + Verifying Checksum ... OK + + +Boot Linux: +----------- + +The "bootm" command is used to boot an application that is stored in +memory (RAM or Flash). In case of a Linux kernel image, the contents +of the "bootargs" environment variable is passed to the kernel as +parameters. You can check and modify this variable using the +"printenv" and "setenv" commands: + + + => printenv bootargs + bootargs=root=/dev/ram + + => setenv bootargs root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2 + + => printenv bootargs + bootargs=root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2 + + => bootm 40020000 + ## Booting Linux kernel at 40020000 ... + Image Name: 2.2.13 for NFS on TQM850L + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 381681 Bytes = 372 kB = 0 MB + Load Address: 00000000 + Entry Point: 0000000c + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK + Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:35:17 MEST 2000 + Boot arguments: root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2 + time_init: decrementer frequency = 187500000/60 + Calibrating delay loop... 49.77 BogoMIPS + Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000] + ... + +If you want to boot a Linux kernel with initial ram disk, you pass +the memory addresses of both the kernel and the initrd image (PPBCOOT +format!) to the "bootm" command: + + => imi 40100000 40200000 + + ## Checking Image at 40100000 ... + Image Name: 2.2.13 for initrd on TQM850L + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327 kB = 0 MB + Load Address: 00000000 + Entry Point: 0000000c + Verifying Checksum ... OK + + ## Checking Image at 40200000 ... + Image Name: Simple Ramdisk Image + Image Type: PowerPC Linux RAMDisk Image (gzip compressed) + Data Size: 566530 Bytes = 553 kB = 0 MB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + + => bootm 40100000 40200000 + ## Booting Linux kernel at 40100000 ... + Image Name: 2.2.13 for initrd on TQM850L + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327 kB = 0 MB + Load Address: 00000000 + Entry Point: 0000000c + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK + ## Loading RAMDisk Image at 40200000 ... + Image Name: Simple Ramdisk Image + Image Type: PowerPC Linux RAMDisk Image (gzip compressed) + Data Size: 566530 Bytes = 553 kB = 0 MB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + Loading Ramdisk ... OK + Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:32:08 MEST 2000 + Boot arguments: root=/dev/ram + time_init: decrementer frequency = 187500000/60 + Calibrating delay loop... 49.77 BogoMIPS + ... + RAMDISK: Compressed image found at block 0 + VFS: Mounted root (ext2 filesystem). + + bash# + +More About U-Boot Image Types: +------------------------------ + +U-Boot supports the following image types: + + "Standalone Programs" are directly runnable in the environment + provided by U-Boot; it is expected that (if they behave + well) you can continue to work in U-Boot after return from + the Standalone Program. + "OS Kernel Images" are usually images of some Embedded OS which + will take over control completely. Usually these programs + will install their own set of exception handlers, device + drivers, set up the MMU, etc. - this means, that you cannot + expect to re-enter U-Boot except by resetting the CPU. + "RAMDisk Images" are more or less just data blocks, and their + parameters (address, size) are passed to an OS kernel that is + being started. + "Multi-File Images" contain several images, typically an OS + (Linux) kernel image and one or more data images like + RAMDisks. This construct is useful for instance when you want + to boot over the network using BOOTP etc., where the boot + server provides just a single image file, but you want to get + for instance an OS kernel and a RAMDisk image. + + "Multi-File Images" start with a list of image sizes, each + image size (in bytes) specified by an "uint32_t" in network + byte order. This list is terminated by an "(uint32_t)0". + Immediately after the terminating 0 follow the images, one by + one, all aligned on "uint32_t" boundaries (size rounded up to + a multiple of 4 bytes). + + "Firmware Images" are binary images containing firmware (like + U-Boot or FPGA images) which usually will be programmed to + flash memory. + + "Script files" are command sequences that will be executed by + U-Boot's command interpreter; this feature is especially + useful when you configure U-Boot to use a real shell (hush) + as command interpreter. + + +Standalone HOWTO: +================= + +One of the features of U-Boot is that you can dynamically load and +run "standalone" applications, which can use some resources of +U-Boot like console I/O functions or interrupt services. + +Two simple examples are included with the sources: + +"Hello World" Demo: +------------------- + +'examples/hello_world.c' contains a small "Hello World" Demo +application; it is automatically compiled when you build U-Boot. +It's configured to run at address 0x00040004, so you can play with it +like that: + + => loads + ## Ready for S-Record download ... + ~>examples/hello_world.srec + 1 2 3 4 5 6 7 8 9 10 11 ... + [file transfer complete] + [connected] + ## Start Addr = 0x00040004 + + => go 40004 Hello World! This is a test. + ## Starting application at 0x00040004 ... + Hello World + argc = 7 + argv[0] = "40004" + argv[1] = "Hello" + argv[2] = "World!" + argv[3] = "This" + argv[4] = "is" + argv[5] = "a" + argv[6] = "test." + argv[7] = "" + Hit any key to exit ... + + ## Application terminated, rc = 0x0 + +Another example, which demonstrates how to register a CPM interrupt +handler with the U-Boot code, can be found in 'examples/timer.c'. +Here, a CPM timer is set up to generate an interrupt every second. +The interrupt service routine is trivial, just printing a '.' +character, but this is just a demo program. The application can be +controlled by the following keys: + + ? - print current values og the CPM Timer registers + b - enable interrupts and start timer + e - stop timer and disable interrupts + q - quit application + + => loads + ## Ready for S-Record download ... + ~>examples/timer.srec + 1 2 3 4 5 6 7 8 9 10 11 ... + [file transfer complete] + [connected] + ## Start Addr = 0x00040004 + + => go 40004 + ## Starting application at 0x00040004 ... + TIMERS=0xfff00980 + Using timer 1 + tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0xfff009b0 + +Hit 'b': + [q, b, e, ?] Set interval 1000000 us + Enabling timer +Hit '?': + [q, b, e, ?] ........ + tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0 +Hit '?': + [q, b, e, ?] . + tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0 +Hit '?': + [q, b, e, ?] . + tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0 +Hit '?': + [q, b, e, ?] . + tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0 +Hit 'e': + [q, b, e, ?] ...Stopping timer +Hit 'q': + [q, b, e, ?] ## Application terminated, rc = 0x0 + + +Minicom warning: +================ + +Over time, many people have reported problems when trying to use the +"minicom" terminal emulation program for serial download. I (wd) +consider minicom to be broken, and recommend not to use it. Under +Unix, I recommend to use C-Kermit for general purpose use (and +especially for kermit binary protocol download ("loadb" command), and +use "cu" for S-Record download ("loads" command). + +Nevertheless, if you absolutely want to use it try adding this +configuration to your "File transfer protocols" section: + + Name Program Name U/D FullScr IO-Red. Multi + X kermit /usr/bin/kermit -i -l %l -s Y U Y N N + Y kermit /usr/bin/kermit -i -l %l -r N D Y N N + + +NetBSD Notes: +============= + +Starting at version 0.9.2, U-Boot supports NetBSD both as host +(build U-Boot) and target system (boots NetBSD/mpc8xx). + +Building requires a cross environment; it is known to work on +NetBSD/i386 with the cross-powerpc-netbsd-1.3 package (you will also +need gmake since the Makefiles are not compatible with BSD make). +Note that the cross-powerpc package does not install include files; +attempting to build U-Boot will fail because is +missing. This file has to be installed and patched manually: + + # cd /usr/pkg/cross/powerpc-netbsd/include + # mkdir powerpc + # ln -s powerpc machine + # cp /usr/src/sys/arch/powerpc/include/ansi.h powerpc/ansi.h + # ${EDIT} powerpc/ansi.h ## must remove __va_list, _BSD_VA_LIST + +Native builds *don't* work due to incompatibilities between native +and U-Boot include files. + +Booting assumes that (the first part of) the image booted is a +stage-2 loader which in turn loads and then invokes the kernel +proper. Loader sources will eventually appear in the NetBSD source +tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the +meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz + + +Implementation Internals: +========================= + +The following is not intended to be a complete description of every +implementation detail. However, it should help to understand the +inner workings of U-Boot and make it easier to port it to custom +hardware. + + +Initial Stack, Global Data: +--------------------------- + +The implementation of U-Boot is complicated by the fact that U-Boot +starts running out of ROM (flash memory), usually without access to +system RAM (because the memory controller is not initialized yet). +This means that we don't have writable Data or BSS segments, and BSS +is not initialized as zero. To be able to get a C environment working +at all, we have to allocate at least a minimal stack. Implementation +options for this are defined and restricted by the CPU used: Some CPU +models provide on-chip memory (like the IMMR area on MPC8xx and +MPC826x processors), on others (parts of) the data cache can be +locked as (mis-) used as memory, etc. + + Chris Hallinan posted a good summary of these issues to the + u-boot-users mailing list: + + Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)? + From: "Chris Hallinan" + Date: Mon, 10 Feb 2003 16:43:46 -0500 (22:43 MET) + ... + + Correct me if I'm wrong, folks, but the way I understand it + is this: Using DCACHE as initial RAM for Stack, etc, does not + require any physical RAM backing up the cache. The cleverness + is that the cache is being used as a temporary supply of + necessary storage before the SDRAM controller is setup. It's + beyond the scope of this list to expain the details, but you + can see how this works by studying the cache architecture and + operation in the architecture and processor-specific manuals. + + OCM is On Chip Memory, which I believe the 405GP has 4K. It + is another option for the system designer to use as an + initial stack/ram area prior to SDRAM being available. Either + option should work for you. Using CS 4 should be fine if your + board designers haven't used it for something that would + cause you grief during the initial boot! It is frequently not + used. + + CFG_INIT_RAM_ADDR should be somewhere that won't interfere + with your processor/board/system design. The default value + you will find in any recent u-boot distribution in + walnut.h should work for you. I'd set it to a value larger + than your SDRAM module. If you have a 64MB SDRAM module, set + it above 400_0000. Just make sure your board has no resources + that are supposed to respond to that address! That code in + start.S has been around a while and should work as is when + you get the config right. + + -Chris Hallinan + DS4.COM, Inc. + +It is essential to remember this, since it has some impact on the C +code for the initialization procedures: + +* Initialized global data (data segment) is read-only. Do not attempt + to write it. + +* Do not use any unitialized global data (or implicitely initialized + as zero data - BSS segment) at all - this is undefined, initiali- + zation is performed later (when relocating to RAM). + +* Stack space is very limited. Avoid big data buffers or things like + that. + +Having only the stack as writable memory limits means we cannot use +normal global data to share information beween the code. But it +turned out that the implementation of U-Boot can be greatly +simplified by making a global data structure (gd_t) available to all +functions. We could pass a pointer to this data as argument to _all_ +functions, but this would bloat the code. Instead we use a feature of +the GCC compiler (Global Register Variables) to share the data: we +place a pointer (gd) to the global data into a register which we +reserve for this purpose. + +When choosing a register for such a purpose we are restricted by the +relevant (E)ABI specifications for the current architecture, and by +GCC's implementation. + +For PowerPC, the following registers have specific use: + R1: stack pointer + R2: TOC pointer + R3-R4: parameter passing and return values + R5-R10: parameter passing + R13: small data area pointer + R30: GOT pointer + R31: frame pointer + + (U-Boot also uses R14 as internal GOT pointer.) + + ==> U-Boot will use R29 to hold a pointer to the global data + + Note: on PPC, we could use a static initializer (since the + address of the global data structure is known at compile time), + but it turned out that reserving a register results in somewhat + smaller code - although the code savings are not that big (on + average for all boards 752 bytes for the whole U-Boot image, + 624 text + 127 data). + +On ARM, the following registers are used: + + R0: function argument word/integer result + R1-R3: function argument word + R9: GOT pointer + R10: stack limit (used only if stack checking if enabled) + R11: argument (frame) pointer + R12: temporary workspace + R13: stack pointer + R14: link register + R15: program counter + + ==> U-Boot will use R8 to hold a pointer to the global data + + +Memory Management: +------------------ + +U-Boot runs in system state and uses physical addresses, i.e. the +MMU is not used either for address mapping nor for memory protection. + +The available memory is mapped to fixed addresses using the memory +controller. In this process, a contiguous block is formed for each +memory type (Flash, SDRAM, SRAM), even when it consists of several +physical memory banks. + +U-Boot is installed in the first 128 kB of the first Flash bank (on +TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After +booting and sizing and initializing DRAM, the code relocates itself +to the upper end of DRAM. Immediately below the U-Boot code some +memory is reserved for use by malloc() [see CFG_MALLOC_LEN +configuration setting]. Below that, a structure with global Board +Info data is placed, followed by the stack (growing downward). + +Additionally, some exception handler code is copied to the low 8 kB +of DRAM (0x00000000 ... 0x00001FFF). + +So a typical memory configuration with 16 MB of DRAM could look like +this: + + 0x0000 0000 Exception Vector code + : + 0x0000 1FFF + 0x0000 2000 Free for Application Use + : + : + + : + : + 0x00FB FF20 Monitor Stack (Growing downward) + 0x00FB FFAC Board Info Data and permanent copy of global data + 0x00FC 0000 Malloc Arena + : + 0x00FD FFFF + 0x00FE 0000 RAM Copy of Monitor Code + ... eventually: LCD or video framebuffer + ... eventually: pRAM (Protected RAM - unchanged by reset) + 0x00FF FFFF [End of RAM] + + +System Initialization: +---------------------- + +In the reset configuration, U-Boot starts at the reset entry point +(on most PowerPC systens at address 0x00000100). Because of the reset +configuration for CS0# this is a mirror of the onboard Flash memory. +To be able to re-map memory U-Boot then jumps to its link address. +To be able to implement the initialization code in C, a (small!) +initial stack is set up in the internal Dual Ported RAM (in case CPUs +which provide such a feature like MPC8xx or MPC8260), or in a locked +part of the data cache. After that, U-Boot initializes the CPU core, +the caches and the SIU. + +Next, all (potentially) available memory banks are mapped using a +preliminary mapping. For example, we put them on 512 MB boundaries +(multiples of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash +on 0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is +programmed for SDRAM access. Using the temporary configuration, a +simple memory test is run that determines the size of the SDRAM +banks. + +When there is more than one SDRAM bank, and the banks are of +different size, the largest is mapped first. For equal size, the first +bank (CS2#) is mapped first. The first mapping is always for address +0x00000000, with any additional banks following immediately to create +contiguous memory starting from 0. + +Then, the monitor installs itself at the upper end of the SDRAM area +and allocates memory for use by malloc() and for the global Board +Info data; also, the exception vector code is copied to the low RAM +pages, and the final stack is set up. + +Only after this relocation will you have a "normal" C environment; +until that you are restricted in several ways, mostly because you are +running from ROM, and because the code will have to be relocated to a +new address in RAM. + + +U-Boot Porting Guide: +---------------------- + +[Based on messages by Jerry Van Baren in the U-Boot-Users mailing +list, October 2002] + + +int main (int argc, char *argv[]) +{ + sighandler_t no_more_time; + + signal (SIGALRM, no_more_time); + alarm (PROJECT_DEADLINE - toSec (3 * WEEK)); + + if (available_money > available_manpower) { + pay consultant to port U-Boot; + return 0; + } + + Download latest U-Boot source; + + Subscribe to u-boot-users mailing list; + + if (clueless) { + email ("Hi, I am new to U-Boot, how do I get started?"); + } + + while (learning) { + Read the README file in the top level directory; + Read http://www.denx.de/twiki/bin/view/DULG/Manual ; + Read the source, Luke; + } + + if (available_money > toLocalCurrency ($2500)) { + Buy a BDI2000; + } else { + Add a lot of aggravation and time; + } + + Create your own board support subdirectory; + + Create your own board config file; + + while (!running) { + do { + Add / modify source code; + } until (compiles); + Debug; + if (clueless) + email ("Hi, I am having problems..."); + } + Send patch file to Wolfgang; + + return 0; +} + +void no_more_time (int sig) +{ + hire_a_guru(); +} + + +Coding Standards: +----------------- + +All contributions to U-Boot should conform to the Linux kernel +coding style; see the file "Documentation/CodingStyle" in your Linux +kernel source directory. + +Please note that U-Boot is implemented in C (and to some small parts +in Assembler); no C++ is used, so please do not use C++ style +comments (//) in your code. + +Please also stick to the following formatting rules: +- remove any trailing white space +- use TAB characters for indentation, not spaces +- make sure NOT to use DOS '\r\n' line feeds +- do not add more than 2 empty lines to source files +- do not add trailing empty lines to source files + +Submissions which do not conform to the standards may be returned +with a request to reformat the changes. + + +Submitting Patches: +------------------- + +Since the number of patches for U-Boot is growing, we need to +establish some rules. Submissions which do not conform to these rules +may be rejected, even when they contain important and valuable stuff. + +Patches shall be sent to the u-boot-users mailing list. + +When you send a patch, please include the following information with +it: + +* For bug fixes: a description of the bug and how your patch fixes + this bug. Please try to include a way of demonstrating that the + patch actually fixes something. + +* For new features: a description of the feature and your + implementation. + +* A CHANGELOG entry as plaintext (separate from the patch) + +* For major contributions, your entry to the CREDITS file + +* When you add support for a new board, don't forget to add this + board to the MAKEALL script, too. + +* If your patch adds new configuration options, don't forget to + document these in the README file. + +* The patch itself. If you are accessing the CVS repository use "cvs + update; cvs diff -puRN"; else, use "diff -purN OLD NEW". If your + version of diff does not support these options, then get the latest + version of GNU diff. + + The current directory when running this command shall be the top + level directory of the U-Boot source tree, or it's parent directory + (i. e. please make sure that your patch includes sufficient + directory information for the affected files). + + We accept patches as plain text, MIME attachments or as uuencoded + gzipped text. + +* If one logical set of modifications affects or creates several + files, all these changes shall be submitted in a SINGLE patch file. + +* Changesets that contain different, unrelated modifications shall be + submitted as SEPARATE patches, one patch per changeset. + + +Notes: + +* Before sending the patch, run the MAKEALL script on your patched + source tree and make sure that no errors or warnings are reported + for any of the boards. + +* Keep your modifications to the necessary minimum: A patch + containing several unrelated changes or arbitrary reformats will be + returned with a request to re-formatting / split it. + +* If you modify existing code, make sure that your new code does not + add to the memory footprint of the code ;-) Small is beautiful! + When adding new features, these should compile conditionally only + (using #ifdef), and the resulting code with the new feature + disabled must not need more memory than the old code without your + modification. + +* Remember that there is a size limit of 40 kB per message on the + u-boot-users mailing list. Compression may help. diff --git a/arm_config.mk b/arm_config.mk new file mode 100644 index 0000000..73d9625 --- /dev/null +++ b/arm_config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ diff --git a/board/AtmarkTechno/suzaku/Makefile b/board/AtmarkTechno/suzaku/Makefile new file mode 100644 index 0000000..7a17067 --- /dev/null +++ b/board/AtmarkTechno/suzaku/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/AtmarkTechno/suzaku/config.mk b/board/AtmarkTechno/suzaku/config.mk new file mode 100644 index 0000000..7bbf2b1 --- /dev/null +++ b/board/AtmarkTechno/suzaku/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2004 Atmark Techno, Inc. +# +# Yasushi SHOJI +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x80F00000 + +PLATFORM_CPPFLAGS += -mno-xl-soft-mul +PLATFORM_CPPFLAGS += -mno-xl-soft-div +PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/AtmarkTechno/suzaku/flash.c b/board/AtmarkTechno/suzaku/flash.c new file mode 100644 index 0000000..49a0673 --- /dev/null +++ b/board/AtmarkTechno/suzaku/flash.c @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +unsigned long flash_init(void) +{ + return 0; +} + +void flash_print_info(flash_info_t *info) +{ +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + return 0; +} + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + return 0; +} diff --git a/board/AtmarkTechno/suzaku/suzaku.c b/board/AtmarkTechno/suzaku/suzaku.c new file mode 100644 index 0000000..afe124a --- /dev/null +++ b/board/AtmarkTechno/suzaku/suzaku.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This is a board specific file. It's OK to include board specific + * header files */ +#include + +void do_reset(void) +{ + *((unsigned long *)(MICROBLAZE_SYSREG_BASE_ADDR)) = MICROBLAZE_SYSREG_RECONFIGURE; +} diff --git a/board/AtmarkTechno/suzaku/u-boot.lds b/board/AtmarkTechno/suzaku/u-boot.lds new file mode 100644 index 0000000..00a8ef7 --- /dev/null +++ b/board/AtmarkTechno/suzaku/u-boot.lds @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(microblaze) +ENTRY(_start) + +SECTIONS +{ + .text ALIGN(0x4): + { + __text_start = .; + cpu/microblaze/start.o (.text) + *(.text) + __text_end = .; + } + + .rodata ALIGN(0x4): + { + __rodata_start = .; + *(.rodata) + __rodata_end = .; + } + + .data ALIGN(0x4): + { + __data_start = .; + *(.data) + __data_end = .; + } + + .u_boot_cmd ALIGN(0x4): + { + . = .; + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } + + .bss ALIGN(0x4): + { + __bss_start = .; + *(.bss) + __bss_start = .; + } +} diff --git a/board/LEOX/elpt860/Makefile b/board/LEOX/elpt860/Makefile new file mode 100644 index 0000000..3e73163 --- /dev/null +++ b/board/LEOX/elpt860/Makefile @@ -0,0 +1,48 @@ + +####################################################################### +# +# Copyright (C) 2000, 2001, 2002, 2003 +# The LEOX team , http://www.leox.org +# +# LEOX.org is about the development of free hardware and software resources +# for system on chip. +# +# Description: U-Boot port on the LEOX's ELPT860 CPU board +# ~~~~~~~~~~~ +# +####################################################################### +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +####################################################################### + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/LEOX/elpt860/README.LEOX b/board/LEOX/elpt860/README.LEOX new file mode 100644 index 0000000..9052b09 --- /dev/null +++ b/board/LEOX/elpt860/README.LEOX @@ -0,0 +1,424 @@ +============================================================================= + + U-Boot port on the LEOX's ELPT860 CPU board + ------------------------------------------- + +LEOX.org is about the development of free hardware and software resources + for system on chip. + +For more information, contact The LEOX team + +References: +~~~~~~~~~~ + 1) Get the last stable release from denx.de: + o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2 + 2) Get the current CVS snapshot: + o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login + o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot + +============================================================================= + +The ELPT860 CPU board has the following features: + +Processor: - MPC860T @ 50MHz + - PowerPC Core + - 65 MIPS + - Caches: D->4KB, I->4KB + - CPM: 4 SCCs, 2 SMCs + - Ethernet 10/100 + - SPI, I2C, PCMCIA, Parallel + +CPU board: - DRAM: 16 MB + - FLASH: 512 KB + (2 * 4 MB) + - NVRAM: 128 KB + - 1 Serial link + - 2 Ethernet 10 BaseT Channels + +On power-up the processor jumps to the address of 0x02000100 + +Thus, U-Boot is configured to reside in flash starting at the address of +0x02001000. The environment space is located in NVRAM separately from +U-Boot, at the address of 0x03000000. + +============================================================================= + + U-Boot test results + +============================================================================= + + +################################################## +# Operation on the serial console (SMC1) +############################## + +U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) + +CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present + *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** +Board: ### No HW ID - assuming ELPT860 +DRAM: 16 MB +FLASH: 512 kB +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET + +Type "run nfsboot" to mount root filesystem over NFS + +Hit any key to stop autoboot: 0 +LEOX_elpt860: help +askenv - get environment variables from stdin +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootd - boot default, i.e., run 'bootcmd' +cmp - memory compare +coninfo - print console devices and informations +cp - memory copy +crc32 - checksum calculation +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +iminfo - print header information for application image +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loop - infinite loop on address range +md - memory display +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nm - memory modify (constant address) +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +tftpboot- boot image via network using TFTP protocol + and env variables ipaddr and serverip +version - print monitor version +? - alias for 'help' + +################################################## +# Environment Variables (CFG_ENV_IS_IN_NVRAM) +############################## + +LEOX_elpt860: printenv +bootdelay=5 +loads_echo=1 +baudrate=9600 +stdin=serial +stdout=serial +stderr=serial +ethaddr=00:03:ca:00:64:df +ipaddr=192.168.0.30 +netmask=255.255.255.0 +serverip=192.168.0.1 +nfsserverip=192.168.0.1 +preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo +gatewayip=192.168.0.1 +ramargs=setenv bootargs root=/dev/ram rw +rootargs=setenv rootpath /tftp/${ipaddr} +nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath} +addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0: +ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm +nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm +bootcmd=run ramboot +clocks_in_mhz=1 + +Environment size: 730/16380 bytes + +################################################## +# Flash Memory Information +############################## + +LEOX_elpt860: flinfo + +Bank # 1: AMD AM29F040 (4 Mbits) + Size: 512 KB in 8 Sectors + Sector Start Addresses: + 02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000 + 02050000 02060000 02070000 + +################################################## +# Board Information Structure +############################## + +LEOX_elpt860: bdinfo +memstart = 0x00000000 +memsize = 0x01000000 +flashstart = 0x02000000 +flashsize = 0x00080000 +flashoffset = 0x00030000 +sramstart = 0x00000000 +sramsize = 0x00000000 +immr_base = 0xFF000000 +bootflags = 0x00000001 +intfreq = 50 MHz +busfreq = 50 MHz +ethaddr = 00:03:ca:00:64:df +IP addr = 192.168.0.30 +baudrate = 9600 bps + +################################################## +# Image Download and run over serial port +# hello_world (S-Record image) +# ===> 1) Enter "loads" command into U-Boot monitor +# ===> 2) From TeraTerm's bar menu, Select 'File/Send file...' +# Then select 'hello_world.srec' with the file browser +############################## + +U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) + +CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present + *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** +Board: ### No HW ID - assuming ELPT860 +DRAM: 16 MB +FLASH: 512 kB +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET + +Type "run nfsboot" to mount root filesystem over NFS + +Hit any key to stop autoboot: 0 +LEOX_elpt860: loads +## Ready for S-Record download ... +S804040004F3050154000501709905014C000501388D +## First Load Addr = 0x00040000 +## Last Load Addr = 0x0005018B +## Total Size = 0x0001018C = 65932 Bytes +## Start Addr = 0x00040004 +LEOX_elpt860: go 40004 This is a test !!! +## Starting application at 0x00040004 ... +Hello World +argc = 6 +argv[0] = "40004" +argv[1] = "This" +argv[2] = "is" +argv[3] = "a" +argv[4] = "test" +argv[5] = "!!!" +argv[6] = "" +Hit any key to exit ... + +## Application terminated, rc = 0x0 + +################################################## +# Image download and run over ethernet interface +# Linux-2.4.4 (uImage) + Root filesystem mounted over NFS +############################## + +U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) + +CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present + *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** +Board: ### No HW ID - assuming ELPT860 +DRAM: 16 MB +FLASH: 512 kB +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET + +Type "run nfsboot" to mount root filesystem over NFS + +Hit any key to stop autoboot: 0 +LEOX_elpt860: run nfsboot +ARP broadcast 1 +TFTP from server 192.168.0.1; our IP address is 192.168.0.30 +Filename '/home/leox/uImage'. +Load address: 0x400000 +Loading: ################################################################# + ############################# +done +Bytes transferred = 477294 (7486e hex) +## Booting image at 00400000 ... + Image Name: Linux-2.4.4 + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 477230 Bytes = 466 kB = 0 MB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK +Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 +On node 0 totalpages: 4096 +zone(0): 4096 pages. +zone(1): 0 pages. +zone(2): 0 pages. +Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0: +rtsched version <20010618.1050.24> +Decrementer Frequency: 3125000 +Warning: real time clock seems stuck! +Calibrating delay loop... 49.76 BogoMIPS +Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem) +Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) +Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) +Page-cache hash table entries: 4096 (order: 2, 16384 bytes) +Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) +POSIX conformance testing by UNIFIX +Linux NET4.0 for Linux 2.4 +Based upon Swansea University Computer Society NET3.039 +Starting kswapd v1.8 +CPM UART driver version 0.03 +ttyS0 on SMC1 at 0x0280, BRG1 +block: queued sectors max/low 9701kB/3233kB, 64 slots per queue +RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df +NET4: Linux TCP/IP 1.0 for NET4.0 +IP Protocols: ICMP, UDP, TCP +IP: routing cache hash table of 512 buckets, 4Kbytes +TCP: Hash tables configured (established 1024 bind 1024) +NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. +Looking up port of RPC 100003/2 on 192.168.0.1 +Looking up port of RPC 100005/2 on 192.168.0.1 +VFS: Mounted root (nfs filesystem). +Freeing unused kernel memory: 44k init +INIT: version 2.78 booting + Welcome to DENX Embedded Linux Environment + Press 'I' to enter interactive startup. +Mounting proc filesystem: [ OK ] +Configuring kernel parameters: [ OK ] +Cannot access the Hardware Clock via any known method. +Use the --debug option to see the details of our search for an access method. +Setting clock : Wed Dec 31 19:00:11 EST 1969 [ OK ] +Activating swap partitions: [ OK ] +Setting hostname 192.168.0.30: [ OK ] +Finding module dependencies: +[ OK ] +Checking filesystems +Checking all file systems. +[ OK ] +Mounting local filesystems: [ OK ] +Enabling swap space: [ OK ] +INIT: Entering runlevel: 3 +Entering non-interactive startup +Starting system logger: [ OK ] +Starting kernel logger: [ OK ] +Starting xinetd: [ OK ] + +192 login: root +Last login: Wed Dec 31 19:00:41 on ttyS0 +bash-2.04# + +################################################## +# Image download and run over ethernet interface +# Linux-2.4.4 + Root filesystem mounted from RAM (pMulti) +############################## + +U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) + +CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present + *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** +Board: ### No HW ID - assuming ELPT860 +DRAM: 16 MB +FLASH: 512 kB +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET + +Type "run nfsboot" to mount root filesystem over NFS + +Hit any key to stop autoboot: 0 +LEOX_elpt860: run ramboot +ARP broadcast 1 +TFTP from server 192.168.0.1; our IP address is 192.168.0.30 +Filename '/home/leox/pMulti'. +Load address: 0x400000 +Loading: ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ######################################################## +done +Bytes transferred = 1947816 (1db8a8 hex) +## Booting image at 00400000 ... + Image Name: linux-2.4.4-2002-03-21 Multiboot + Image Type: PowerPC Linux Multi-File Image (gzip compressed) + Data Size: 1947752 Bytes = 1902 kB = 1 MB + Load Address: 00000000 + Entry Point: 00000000 + Contents: + Image 0: 477230 Bytes = 466 kB = 0 MB + Image 1: 1470508 Bytes = 1436 kB = 1 MB + Verifying Checksum ... OK + Uncompressing Multi-File Image ... OK + Loading Ramdisk to 00e44000, end 00fab02c ... OK +Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 +On node 0 totalpages: 4096 +zone(0): 4096 pages. +zone(1): 0 pages. +zone(2): 0 pages. +Kernel command line: root=/dev/ram rw +rtsched version <20010618.1050.24> +Decrementer Frequency: 3125000 +Warning: real time clock seems stuck! +Calibrating delay loop... 49.76 BogoMIPS +Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem) +Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) +Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) +Page-cache hash table entries: 4096 (order: 2, 16384 bytes) +Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) +POSIX conformance testing by UNIFIX +Linux NET4.0 for Linux 2.4 +Based upon Swansea University Computer Society NET3.039 +Starting kswapd v1.8 +CPM UART driver version 0.03 +ttyS0 on SMC1 at 0x0280, BRG1 +block: queued sectors max/low 8741kB/2913kB, 64 slots per queue +RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df +RAMDISK: Compressed image found at block 0 +Freeing initrd memory: 1436k freed +NET4: Linux TCP/IP 1.0 for NET4.0 +IP Protocols: ICMP, UDP, TCP +IP: routing cache hash table of 512 buckets, 4Kbytes +TCP: Hash tables configured (established 1024 bind 1024) +IP-Config: Incomplete network configuration information. +NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. +VFS: Mounted root (ext2 filesystem). +Freeing unused kernel memory: 44k iné +init started: BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname +Configuring lo... +Configuring eth0... +Configuring Gateway... + +Please press Enter to activate this console. + +ELPT860 login: root +Password: +Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz) + + a8888b. + d888888b. + 8P"YP"Y88 + _ _ 8|o||o|88 + | | |_| 8' .88 + | | _ ____ _ _ _ _ 8`._.' Y8. + | | | | _ \| | | |\ \/ / d/ `8b. + | |___ | | | | | |_| |/ \ .dP . Y8b. + |_____||_|_| |_|\____|\_/\_/ d8:' " `::88b. + d8" `Y88b + :8P ' :888 + 8a. : _a88P + ._/"Yaa_ : .| 88P| + \ YP" `| 8P `. + / \._____.d| .' + `--..__)888888P`._.' +login[21]: root login on `ttyS0' + + + +BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash) +Enter 'help' for a list of built-in commands. + +root@ELPT860:~ # diff --git a/board/LEOX/elpt860/config.mk b/board/LEOX/elpt860/config.mk new file mode 100644 index 0000000..defc360 --- /dev/null +++ b/board/LEOX/elpt860/config.mk @@ -0,0 +1,36 @@ +####################################################################### +# +# Copyright (C) 2000, 2001, 2002, 2003 +# The LEOX team , http://www.leox.org +# +# LEOX.org is about the development of free hardware and software resources +# for system on chip. +# +# Description: U-Boot port on the LEOX's ELPT860 CPU board +# ~~~~~~~~~~~ +# +####################################################################### +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +####################################################################### + +# +# ELPT860 board +# + +TEXT_BASE = 0x02000000 +#TEXT_BASE = 0x00FB0000 diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c new file mode 100644 index 0000000..775db73 --- /dev/null +++ b/board/LEOX/elpt860/elpt860.c @@ -0,0 +1,348 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team , http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +/* +** Note 1: In this file, you have to provide the following functions: +** ------ +** int board_early_init_f(void) +** int checkboard(void) +** long int initdram(int board_type) +** called from 'board_init_f()' into 'common/board.c' +** +** void reset_phy(void) +** called from 'board_init_r()' into 'common/board.c' +*/ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint init_sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, + 0xFFFFFC04, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */ + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, + 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */ + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34, + 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */ +}; + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, + 0xFF0FFC00, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, + 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00, + 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, + 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00, + 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */ + _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00, + 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04, + 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, + 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_, + 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */ +}; + +/* ------------------------------------------------------------------------- */ + +#define CFG_PC4 0x0800 + +#define CFG_DS1 CFG_PC4 + +/* + * Very early board init code (fpga boot, etc.) + */ +int board_early_init_f (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* + * Light up the red led on ELPT860 pcb (DS1) (PCDAT) + */ + immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */ + immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */ + immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */ + + return (0); /* success */ +} + +/* + * Check Board Identity: + * + * Test ELPT860 ID string + * + * Return 1 if no second DRAM bank, otherwise returns 0 + */ + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + if (!s || strncmp (s, "ELPT860", 7)) + printf ("### No HW ID - assuming ELPT860\n"); + + return (0); /* success */ +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size8, size9; + long int size_b0 = 0; + + /* + * This sequence initializes SDRAM chips on ELPT860 board + */ + upmconfig (UPMA, (uint *) init_sdram_table, + sizeof (init_sdram_table) / sizeof (uint)); + + memctl->memc_mptpr = 0x0200; + memctl->memc_mamr = 0x18002111; + + memctl->memc_mar = 0x00000088; + memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */ + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + /* + * The following value is used as an address (i.e. opcode) for + * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If + * the port size is 32bit the SDRAM does NOT "see" the lower two + * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for + * MICRON SDRAMs: + * -> 0 00 010 0 010 + * | | | | +- Burst Length = 4 + * | | | +----- Burst Type = Sequential + * | | +------- CAS Latency = 2 + * | +----------- Operating Mode = Standard + * +-------------- Write Burst Mode = Programmed Burst Length + */ + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, + SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, + SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size_b0 = size9; + /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); + /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if (size_b0 < 0x02000000) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping: map bigger bank first + */ + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + { + unsigned long reg; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + + udelay (10000); + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int +dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size (base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +#define CFG_PA1 0x4000 +#define CFG_PA2 0x2000 + +#define CFG_LBKs (CFG_PA2 | CFG_PA1) + +void reset_phy (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* + * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect + * and no AUI loopback + */ + immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */ + immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */ + immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */ +} diff --git a/board/LEOX/elpt860/flash.c b/board/LEOX/elpt860/flash.c new file mode 100644 index 0000000..c1b3b85 --- /dev/null +++ b/board/LEOX/elpt860/flash.c @@ -0,0 +1,615 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team , http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +/* +** Note 1: In this file, you have to provide the following variable: +** ------ +** flash_info_t flash_info[CFG_MAX_FLASH_BANKS] +** 'flash_info_t' structure is defined into 'include/flash.h' +** and defined as extern into 'common/cmd_flash.c' +** +** Note 2: In this file, you have to provide the following functions: +** ------ +** unsigned long flash_init(void) +** called from 'board_init_r()' into 'common/board.c' +** +** void flash_print_info(flash_info_t *info) +** called from 'do_flinfo()' into 'common/cmd_flash.c' +** +** int flash_erase(flash_info_t *info, +** int s_first, +** int s_last) +** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c' +** +** int write_buff (flash_info_t *info, +** uchar *src, +** ulong addr, +** ulong cnt) +** called from 'flash_write()' into 'common/cmd_flash.c' +*/ + +#include +#include + + +#ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Internal Functions + */ +static void flash_get_offsets (ulong base, flash_info_t *info); +static ulong flash_get_size (volatile unsigned char *addr, flash_info_t *info); + +static int write_word (flash_info_t *info, ulong dest, ulong data); +static int write_byte (flash_info_t *info, ulong dest, uchar data); + +/*----------------------------------------------------------------------- + */ + +unsigned long +flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE, + &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void +flash_get_offsets (ulong base, + flash_info_t *info) +{ + int i; + +#define SECTOR_64KB 0x00010000 + + /* set up sector start adress table */ + for (i = 0; i < info->sector_count; i++) + { + info->start[i] = base + (i * SECTOR_64KB); + } +} + +/*----------------------------------------------------------------------- + */ +void +flash_print_info (flash_info_t *info) +{ + int i; + + if ( info->flash_id == FLASH_UNKNOWN ) + { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ( info->flash_id & FLASH_VENDMASK ) + { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_STM: printf ("STM (Thomson) "); break; + default: printf ("Unknown Vendor "); break; + } + + switch ( info->flash_id & FLASH_TYPEMASK ) + { + case FLASH_AM040: printf ("AM29F040 (4 Mbits)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) + { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong +flash_get_size (volatile unsigned char *addr, + flash_info_t *info) +{ + short i; + uchar value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x90; + + value = addr[0]; + + switch ( value ) + { + /* case AMD_MANUFACT: */ + case 0x01: + info->flash_id = FLASH_MAN_AMD; + break; + /* case FUJ_MANUFACT: */ + case 0x04: + info->flash_id = FLASH_MAN_FUJ; + break; + /* case STM_MANUFACT: */ + case 0x20: + info->flash_id = FLASH_MAN_STM; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch ( value ) + { + case STM_ID_F040B: + case AMD_ID_F040B: + info->flash_id += FLASH_AM040; /* 4 Mbits = 512k * 8 */ + info->sector_count = 8; + info->size = 0x00080000; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start adress table */ + for (i = 0; i < info->sector_count; i++) + { + info->start[i] = base + (i * 0x00010000); + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) + { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if ( info->flash_id != FLASH_UNKNOWN ) + { + addr = (volatile unsigned char *)info->start[0]; + + *addr = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int +flash_erase (flash_info_t *info, + int s_first, + int s_last) +{ + volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ( (s_first < 0) || (s_first > s_last) ) + { + if ( info->flash_id == FLASH_UNKNOWN ) + { + printf ("- missing\n"); + } + else + { + printf ("- no sectors to erase\n"); + } + return ( 1 ); + } + + if ( (info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP) ) + { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return ( 1 ); + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) + { + if ( info->protect[sect] ) + { + prot++; + } + } + + if ( prot ) + { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } + else + { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) + { + if (info->protect[sect] == 0) /* not protected */ + { + addr = (volatile unsigned char *)(info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if ( flag ) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if ( l_sect < 0 ) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile unsigned char *)(info->start[l_sect]); + while ( (addr[0] & 0x80) != 0x80 ) + { + if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT ) + { + printf ("Timeout\n"); + return ( 1 ); + } + /* show that we're waiting */ + if ( (now - last) > 1000 ) /* every second */ + { + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf (" done\n"); + + return ( 0 ); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int +write_buff (flash_info_t *info, + uchar *src, + ulong addr, + ulong cnt) +{ + ulong cp, wp, data; + uchar bdata; + int i, l, rc; + + if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 ) + { + /* Width of the data bus: 8 bits */ + + wp = addr; + + while ( cnt ) + { + bdata = *src++; + + if ( (rc = write_byte(info, wp, bdata)) != 0 ) + { + return (rc); + } + + ++wp; + --cnt; + } + + return ( 0 ); + } + else + { + /* Width of the data bus: 32 bits */ + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ( (l = addr - wp) != 0 ) + { + data = 0; + for (i=0, cp=wp; i0; ++i) + { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) + { + data = (data << 8) | (*(uchar *)cp); + } + + if ( (rc = write_word(info, wp, data)) != 0 ) + { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while ( cnt >= 4 ) + { + data = 0; + for (i=0; i<4; ++i) + { + data = (data << 8) | *src++; + } + if ( (rc = write_word(info, wp, data)) != 0 ) + { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if ( cnt == 0 ) + { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) + { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) + { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); + } +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int +write_word (flash_info_t *info, + ulong dest, + ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ( (*((vu_long *)dest) & data) != data ) + { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if ( flag ) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) ) + { + if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) + { + return (1); + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a byte to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int +write_byte (flash_info_t *info, + ulong dest, + uchar data) +{ + volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ( (*((volatile unsigned char *)dest) & data) != data ) + { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((volatile unsigned char *)dest) = data; + + /* re-enable interrupts if necessary */ + if ( flag ) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) ) + { + if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) + { + return (1); + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds new file mode 100644 index 0000000..b09fc33 --- /dev/null +++ b/board/LEOX/elpt860/u-boot.lds @@ -0,0 +1,154 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team , http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_generic/string.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/extable.o (.text) + lib_ppc/time.o (.text) + lib_ppc/ticks.o (.text) + + . = env_offset; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug new file mode 100644 index 0000000..6f5af91 --- /dev/null +++ b/board/LEOX/elpt860/u-boot.lds.debug @@ -0,0 +1,141 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team , http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c new file mode 100644 index 0000000..0934e1b --- /dev/null +++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2002 + * Hyperion Entertainment, ThomasF@hyperion-entertainment.com + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "articiaS.h" +#include "memio.h" +#include "via686.h" + +__asm(" .globl send_kb \n + send_kb: \n + lis r9, 0xfe00 \n + \n + li r4, 0x10 # retries \n + mtctr r4 \n + \n + idle: \n + lbz r4, 0x64(r9) \n + andi. r4, r4, 0x02 \n + bne idle \n + \n + ready: \n + stb r3, 0x60(r9) \n + \n + check: \n + lbz r4, 0x64(r9) \n + andi. r4, r4, 0x01 \n + beq check \n + \n + lbz r4, 0x60(r9) \n + cmpwi r4, 0xfa \n + beq done \n + \n + bdnz idle \n + \n + li r3, 0 \n + blr \n + \n + done: \n + li r3, 1 \n + blr \n + \n + .globl test_kb \n + test_kb: \n + mflr r10 \n + li r3, 0xed \n + bl send_kb \n + li r3, 0x01 \n + bl send_kb \n + mtlr r10 \n + blr \n +"); + + +int checkboard (void) +{ + printf ("Board: AmigaOneG3SE\n"); + return 0; +} + +long initdram (int board_type) +{ + return articiaS_ram_init (); +} + + +void after_reloc (ulong dest_addr, gd_t *gd) +{ +/* HJF: DECLARE_GLOBAL_DATA_PTR; */ + + board_init_r (gd, dest_addr); +} + + +int misc_init_r (void) +{ + extern pci_dev_t video_dev; + extern void drv_video_init (void); + + if (video_dev != ~0) + drv_video_init (); + + return (0); +} + + +void pci_init_board (void) +{ +#ifndef CONFIG_RAMBOOT + articiaS_pci_init (); +#endif +} diff --git a/board/MAI/AmigaOneG3SE/Makefile b/board/MAI/AmigaOneG3SE/Makefile new file mode 100644 index 0000000..b1247fe --- /dev/null +++ b/board/MAI/AmigaOneG3SE/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \ + via686.o i8259.o ../bios_emulator/x86interface.o \ + ../bios_emulator/bios.o ../bios_emulator/glue.o \ + interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \ + ../menu/cmd_menu.o cmd_boota.o nvram.o + +AOBJS = board_asm_init.o memio.o + +OBJS = $(COBJS) $(AOBJS) + +EMUDIR = ../bios_emulator/scitech/src/x86emu/ +EMUOBJ = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \ + $(EMUDIR)ops.o $(EMUDIR)sys.o +EMUSRC = $(EMUOBJ:.o=.c) + +$(LIB): .depend $(OBJS) $(EMUSRC) + make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE) + -rm $(LIB) + $(AR) crv $@ $(OBJS) $(EMUOBJ) + + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/MAI/AmigaOneG3SE/articiaS.c b/board/MAI/AmigaOneG3SE/articiaS.c new file mode 100644 index 0000000..a4dad64 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/articiaS.c @@ -0,0 +1,705 @@ +/* + * (C) Copyright 2002 + * Hyperion Entertainment, ThomasF@hyperion-entertainment.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "memio.h" +#include "articiaS.h" +#include "smbus.h" +#include "via686.h" + +#undef DEBUG + +struct dimm_bank { + uint8 used; /* Bank is populated */ + uint32 rows; /* Number of row addresses */ + uint32 columns; /* Number of column addresses */ + uint8 registered; /* SIMM is registered */ + uint8 ecc; /* SIMM has ecc */ + uint8 burst_len; /* Supported burst lengths */ + uint32 cas_lat; /* Supported CAS latencies */ + uint32 cas_used; /* CAS to use (not set by user) */ + uint32 trcd; /* RAS to CAS latency */ + uint32 trp; /* Precharge latency */ + uint32 tclk_hi; /* SDRAM cycle time (highest CAS latency) */ + uint32 tclk_2hi; /* SDRAM second highest CAS latency */ + uint32 size; /* Size of bank in bytes */ + uint8 auto_refresh; /* Module supports auto refresh */ + uint32 refresh_time; /* Refresh time (in ns) */ +}; + + +/* +** Based in part on the evb64260 code +*/ + +/* + * translate ns.ns/10 coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short NS10to10PS (unsigned char spd_byte) +{ + unsigned short ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + return (ns * 100 + ns10 * 10); +} + +/* + * translate ns coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short NSto10PS (unsigned char spd_byte) +{ + return (spd_byte * 100); +} + + +long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks) +{ + DECLARE_GLOBAL_DATA_PTR; + int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR; + uint32 busclock = gd->bus_clk; + uint32 memclock = busclock; + uint32 tmemclock = 1000000000 / (memclock / 100); + uint32 datawidth; + + if (sm_get_data (rom, dimm_address) == 0) { + /* Nothing in slot, make both banks empty */ + debug ("Slot %d: vacant\n", dimmNum); + banks[0].used = 0; + banks[1].used = 0; + return 0; + } + + if (rom[2] != 0x04) { + debug ("Slot %d: No SDRAM\n", dimmNum); + banks[0].used = 0; + banks[1].used = 0; + return 0; + } + + /* Determine number of banks/rows */ + if (rom[5] == 1) { + banks[0].used = 1; + banks[1].used = 0; + } else { + banks[0].used = 1; + banks[1].used = 1; + } + + /* Determine number of row addresses */ + if (rom[3] & 0xf0) { + /* Different banks sizes */ + banks[0].rows = rom[3] & 0x0f; + banks[1].rows = (rom[3] & 0xf0) >> 4; + } else { + /* Equal sized banks */ + banks[0].rows = rom[3] & 0x0f; + banks[1].rows = banks[0].rows; + } + + /* Determine number of column addresses */ + if (rom[4] & 0xf0) { + /* Different bank sizes */ + banks[0].columns = rom[4] & 0x0f; + banks[1].columns = (rom[4] & 0xf0) >> 4; + } else { + banks[0].columns = rom[4] & 0x0f; + banks[1].columns = banks[0].columns; + } + + /* Check Jedec revision, and modify row/column accordingly */ + if (rom[62] > 0x10) { + if (banks[0].rows <= 3) + banks[0].rows += 15; + if (banks[1].rows <= 3) + banks[1].rows += 15; + if (banks[0].columns <= 3) + banks[0].columns += 15; + if (banks[0].columns <= 3) + banks[0].columns += 15; + } + + /* Check registered/unregisterd */ + if (rom[21] & 0x12) { + banks[0].registered = 1; + banks[1].registered = 1; + } else { + banks[0].registered = 0; + banks[1].registered = 0; + } + +#ifdef CONFIG_ECC + /* Check parity/ECC */ + banks[0].ecc = (rom[11] == 0x02); + banks[1].ecc = (rom[11] == 0x02); +#endif + + /* Find burst lengths supported */ + banks[0].burst_len = rom[16] & 0x8f; + banks[1].burst_len = rom[16] & 0x8f; + + /* Find possible cas latencies */ + banks[0].cas_lat = rom[18] & 0x7F; + banks[1].cas_lat = rom[18] & 0x7F; + + /* RAS/CAS latency */ + banks[0].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock; + banks[1].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock; + + /* Precharge latency */ + banks[0].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock; + banks[1].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock; + + /* highest CAS latency */ + banks[0].tclk_hi = NS10to10PS (rom[9]); + banks[1].tclk_hi = NS10to10PS (rom[9]); + + /* second highest CAS latency */ + banks[0].tclk_2hi = NS10to10PS (rom[23]); + banks[1].tclk_2hi = NS10to10PS (rom[23]); + + /* bank sizes */ + datawidth = rom[13] & 0x7f; + banks[0].size = + (1L << (banks[0].rows + banks[0].columns)) * + /* FIXME datawidth */ 8 * rom[17]; + if (rom[13] & 0x80) + banks[1].size = 2 * banks[0].size; + else + banks[1].size = (1L << (banks[1].rows + banks[1].columns)) * + /* FIXME datawidth */ 8 * rom[17]; + + /* Refresh */ + if (rom[12] & 0x80) { + banks[0].auto_refresh = 1; + banks[1].auto_refresh = 1; + } else { + banks[0].auto_refresh = 0; + banks[1].auto_refresh = 0; + } + + switch (rom[12] & 0x7f) { + case 0: + banks[0].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock; + banks[1].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock; + break; + case 1: + banks[0].refresh_time = (390600 + (tmemclock - 1)) / tmemclock; + banks[1].refresh_time = (390600 + (tmemclock - 1)) / tmemclock; + break; + case 2: + banks[0].refresh_time = (781200 + (tmemclock - 1)) / tmemclock; + banks[1].refresh_time = (781200 + (tmemclock - 1)) / tmemclock; + break; + case 3: + banks[0].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock; + banks[1].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock; + break; + case 4: + banks[0].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock; + banks[1].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock; + break; + case 5: + banks[0].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock; + banks[1].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock; + break; + default: + banks[0].refresh_time = 0x100; /* Default of Articia S */ + banks[1].refresh_time = 0x100; + break; + } + +#ifdef DEBUG + printf ("\nInformation for SIMM bank %ld:\n", dimmNum); + printf ("Number of banks: %ld\n", banks[0].used + banks[1].used); + printf ("Number of row addresses: %ld\n", banks[0].rows); + printf ("Number of coumns addresses: %ld\n", banks[0].columns); + printf ("SIMM is %sregistered\n", + banks[0].registered == 0 ? "not " : ""); +#ifdef CONFIG_ECC + printf ("SIMM %s ECC\n", + banks[0].ecc == 1 ? "supports" : "doesn't support"); +#endif + printf ("Supported burst lenghts: %s %s %s %s %s\n", + banks[0].burst_len & 0x08 ? "8" : " ", + banks[0].burst_len & 0x04 ? "4" : " ", + banks[0].burst_len & 0x02 ? "2" : " ", + banks[0].burst_len & 0x01 ? "1" : " ", + banks[0].burst_len & 0x80 ? "PAGE" : " "); + printf ("Supported CAS latencies: %s %s %s\n", + banks[0].cas_lat & 0x04 ? "CAS 3" : " ", + banks[0].cas_lat & 0x02 ? "CAS 2" : " ", + banks[0].cas_lat & 0x01 ? "CAS 1" : " "); + printf ("RAS to CAS latency: %ld\n", banks[0].trcd); + printf ("Precharge latency: %ld\n", banks[0].trp); + printf ("SDRAM highest CAS latency: %ld\n", banks[0].tclk_hi); + printf ("SDRAM 2nd highest CAS latency: %ld\n", banks[0].tclk_2hi); + printf ("SDRAM data width: %ld\n", datawidth); + printf ("Auto Refresh %ssupported\n", + banks[0].auto_refresh ? "" : "not "); + printf ("Refresh time: %ld clocks\n", banks[0].refresh_time); + if (banks[0].used) + printf ("Bank 0 size: %ld MB\n", banks[0].size / 1024 / 1024); + if (banks[1].used) + printf ("Bank 1 size: %ld MB\n", banks[1].size / 1024 / 1024); + + printf ("\n"); +#endif + + sm_term (); + return 1; +} + +void select_cas (struct dimm_bank *banks, uint8 fast) +{ + if (!banks[0].used) { + banks[0].cas_used = 0; + banks[0].cas_used = 0; + return; + } + + if (fast) { + /* Search for fast CAS */ + uint32 i; + uint32 c = 0x01; + + for (i = 1; i < 5; i++) { + if (banks[0].cas_lat & c) { + banks[0].cas_used = i; + banks[1].cas_used = i; + debug ("Using CAS %d (fast)\n", i); + return; + } + c <<= 1; + } + + /* Default to CAS 3 */ + banks[0].cas_used = 3; + banks[1].cas_used = 3; + debug ("Using CAS 3 (fast)\n"); + + return; + } else { + /* Search for slow cas */ + uint32 i; + uint32 c = 0x08; + + for (i = 4; i > 1; i--) { + if (banks[0].cas_lat & c) { + banks[0].cas_used = i; + banks[1].cas_used = i; + debug ("Using CAS %d (slow)\n", i); + return; + } + c >>= 1; + } + + /* Default to CAS 3 */ + banks[0].cas_used = 3; + banks[1].cas_used = 3; + debug ("Using CAS 3 (slow)\n"); + + return; + } + + banks[0].cas_used = 3; + banks[1].cas_used = 3; + debug ("Using CAS 3\n"); + + return; +} + +uint32 get_reg_setting (uint32 banks, uint32 rows, uint32 columns, uint32 size) +{ + uint32 i; + + struct RowColumnSize { + uint32 banks; + uint32 rows; + uint32 columns; + uint32 size; + uint32 register_value; + }; + + struct RowColumnSize rcs_map[] = { + /* Sbk Radr Cadr MB Value */ + {1, 11, 8, 8, 0x00840f00}, + {1, 11, 9, 16, 0x00925f00}, + {1, 11, 10, 32, 0x00a64f00}, + {2, 12, 8, 32, 0x00c55f00}, + {2, 12, 9, 64, 0x00d66f00}, + {2, 12, 10, 128, 0x00e77f00}, + {2, 12, 11, 256, 0x00ff8f00}, + {2, 13, 11, 512, 0x00ff9f00}, + {0, 0, 0, 0, 0x00000000} + }; + + + i = 0; + + while (rcs_map[i].banks != 0) { + if (rows == rcs_map[i].rows + && columns == rcs_map[i].columns + && (size / 1024 / 1024) == rcs_map[i].size) + return rcs_map[i].register_value; + + i++; + } + + return 0; +} + +uint32 burst_to_len (uint32 support) +{ + if (support & 0x80) + return 0x7; + else if (support & 0x8) + return 0x3; + else if (support & 0x4) + return 0x2; + else if (support & 0x2) + return 0x1; + else if (support & 0x1) + return 0x0; + + return 0; +} + +long articiaS_ram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + register uint32 i; + register uint32 value1; + register uint32 value2; + uint8 rom[128]; + uint32 burst_len; + uint32 burst_support; + uint32 total_ram = 0; + + struct dimm_bank banks[4]; /* FIXME: Move to initram */ + uint32 busclock = gd->bus_clk; + uint32 memclock = busclock; + uint32 reg32; + uint32 refresh_clocks; + uint8 auto_refresh; + + memset (banks, 0, sizeof (struct dimm_bank) * 4); + + detect_sdram (rom, 0, &banks[0]); + detect_sdram (rom, 1, &banks[2]); + + for (i = 0; i < 4; i++) { + total_ram = total_ram + (banks[i].used * banks[i].size); + } + + pci_write_cfg_long (0, 0, GLOBALINFO0, 0x117430c0); + pci_write_cfg_long (0, 0, HBUSACR0, 0x1f0100b0); + pci_write_cfg_long (0, 0, SRAM_CR, 0x00f12000); /* Note: Might also try 0x00f10000 (original: 0x00f12000) */ + pci_write_cfg_byte (0, 0, DRAM_RAS_CTL0, 0x3f); + pci_write_cfg_byte (0, 0, DRAM_RAS_CTL1, 0x00); /* was: 0x04); */ + pci_write_cfg_word (0, 0, DRAM_ECC0, 0x2020); /* was: 0x2400); No ECC yet */ + + /* FIXME: Move this stuff to seperate function, like setup_dimm_bank */ + if (banks[0].used) { + value1 = get_reg_setting (banks[0].used + banks[1].used, + banks[0].rows, banks[0].columns, + banks[0].size); + } else { + value1 = 0; + } + + if (banks[1].used) { + value2 = get_reg_setting (banks[0].used + banks[1].used, + banks[1].rows, banks[1].columns, + banks[1].size); + } else { + value2 = 0; + } + + pci_write_cfg_long (0, 0, DIMM0_B0_SCR0, value1); + pci_write_cfg_long (0, 0, DIMM0_B1_SCR0, value2); + + debug ("DIMM0_B0_SCR0 = 0x%08x\n", value1); + debug ("DIMM0_B1_SCR0 = 0x%08x\n", value2); + + if (banks[2].used) { + value1 = get_reg_setting (banks[2].used + banks[3].used, + banks[2].rows, banks[2].columns, + banks[2].size); + } else { + value1 = 0; + } + + if (banks[3].used) { + value2 = get_reg_setting (banks[2].used + banks[3].used, + banks[3].rows, banks[3].columns, + banks[3].size); + } else { + value2 = 0; + } + + pci_write_cfg_long (0, 0, DIMM1_B2_SCR0, value1); + pci_write_cfg_long (0, 0, DIMM1_B3_SCR0, value2); + + debug ("DIMM0_B2_SCR0 = 0x%08x\n", value1); + debug ("DIMM0_B3_SCR0 = 0x%08x\n", value2); + + pci_write_cfg_long (0, 0, DIMM2_B4_SCR0, 0); + pci_write_cfg_long (0, 0, DIMM2_B5_SCR0, 0); + pci_write_cfg_long (0, 0, DIMM3_B6_SCR0, 0); + pci_write_cfg_long (0, 0, DIMM3_B7_SCR0, 0); + + /* Determine timing */ + select_cas (&banks[0], 0); + select_cas (&banks[2], 0); + + /* FIXME: What about write recovery */ + /* Auto refresh Precharge */ +#if 0 + reg32 = (0x3 << 13) | (0x7 << 10) | ((banks[0].trp - 2) << 8) | + /* Write recovery CAS Latency */ + (0x1 << 6) | (banks[0].cas_used << 4) | + /* RAS/CAS latency */ + ((banks[0].trcd - 1) << 0); + + reg32 |= ((0x3 << 13) | (0x7 << 10) | ((banks[2].trp - 2) << 8) | + (0x1 << 6) | (banks[2].cas_used << 4) | + ((banks[2].trcd - 1) << 0)) << 16; +#else + if (100000000 == gd->bus_clk) + reg32 = 0x71737173; + else + reg32 = 0x69736973; +#endif + pci_write_cfg_long (0, 0, DIMM0_TCR0, reg32); + debug ("DIMM0_TCR0 = 0x%08x\n", reg32); + + /* Write default in DIMM2/3 (not used on A1) */ + pci_write_cfg_long (0, 0, DIMM2_TCR0, 0x7d737d73); + + + /* Determine buffered/unbuffered mode for each SIMM. Uses first bank as reference (second, if present, uses the same) */ + reg32 = pci_read_cfg_long (0, 0, DRAM_GCR0); + reg32 &= 0xFF00FFFF; + +#if 0 + if (banks[0].used && banks[0].registered) + reg32 |= 0x1 << 16; + + if (banks[2].used && banks[2].registered) + reg32 |= 0x1 << 18; +#else + if (banks[0].registered || banks[2].registered) + reg32 |= 0x55 << 16; +#endif + pci_write_cfg_long (0, 0, DRAM_GCR0, reg32); + debug ("DRAM_GCR0 = 0x%08x\n", reg32); + + /* Determine refresh */ + refresh_clocks = 0xffffffff; + auto_refresh = 1; + + for (i = 0; i < 4; i++) { + if (banks[i].used) { + if (banks[i].auto_refresh == 0) + auto_refresh = 0; + if (banks[i].refresh_time < refresh_clocks) + refresh_clocks = banks[i].refresh_time; + } + } + + +#if 1 + /* It seems this is suggested by the ArticiaS data book */ + if (100000000 == gd->bus_clk) + refresh_clocks = 1561; + else + refresh_clocks = 2083; +#endif + + + debug ("Refresh set to %ld clocks, auto refresh %s\n", + refresh_clocks, auto_refresh ? "on" : "off"); + + pci_write_cfg_long (0, 0, DRAM_REFRESH0, + (1 << 16) | (1 << 15) | (auto_refresh << 12) | + (refresh_clocks)); + debug ("DRAM_REFRESH0 = 0x%08x\n", + (1 << 16) | (1 << 15) | (auto_refresh << 12) | + (refresh_clocks)); + +/* pci_write_cfg_long(0, 0, DRAM_REFRESH0, 0x00019400); */ + + /* Set mode registers */ + /* FIXME: For now, set same burst len for all modules. Dunno if that's necessary */ + /* Find a common burst len */ + burst_support = 0xff; + + if (banks[0].used) + burst_support = banks[0].burst_len; + if (banks[1].used) + burst_support = banks[1].burst_len; + if (banks[2].used) + burst_support = banks[2].burst_len; + if (banks[3].used) + burst_support = banks[3].burst_len; + + /* + ** Mode register: + ** Bits Use + ** 0-2 Burst len + ** 3 Burst type (0 = sequential, 1 = interleave) + ** 4-6 CAS latency + ** 7-8 Operation mode (0 = default, all others invalid) + ** 9 Write burst + ** 10-11 Reserved + ** + ** Mode register burst table: + ** A2 A1 A0 lenght + ** 0 0 0 1 + ** 0 0 1 2 + ** 0 1 0 4 + ** 0 1 1 8 + ** 1 0 0 invalid + ** 1 0 1 invalid + ** 1 1 0 invalid + ** 1 1 1 page (only valid for non-interleaved) + */ + + burst_len = burst_to_len (burst_support); + burst_len = 2; /* FIXME */ + + if (banks[0].used) { + pci_write_cfg_word (0, 0, DRAM_PCR0, + 0x8000 | burst_len | (banks[0].cas_used << 4)); + debug ("Mode bank 0: 0x%08x\n", + 0x8000 | burst_len | (banks[0].cas_used << 4)); + } else { + /* Seems to be needed to disable the bank */ + pci_write_cfg_word (0, 0, DRAM_PCR0, 0x0000 | 0x032); + } + + if (banks[1].used) { + pci_write_cfg_word (0, 0, DRAM_PCR0, + 0x9000 | burst_len | (banks[1].cas_used << 4)); + debug ("Mode bank 1: 0x%08x\n", + 0x8000 | burst_len | (banks[1].cas_used << 4)); + } else { + /* Seems to be needed to disable the bank */ + pci_write_cfg_word (0, 0, DRAM_PCR0, 0x1000 | 0x032); + } + + + if (banks[2].used) { + pci_write_cfg_word (0, 0, DRAM_PCR0, + 0xa000 | burst_len | (banks[2].cas_used << 4)); + debug ("Mode bank 2: 0x%08x\n", + 0x8000 | burst_len | (banks[2].cas_used << 4)); + } else { + /* Seems to be needed to disable the bank */ + pci_write_cfg_word (0, 0, DRAM_PCR0, 0x2000 | 0x032); + } + + + if (banks[3].used) { + pci_write_cfg_word (0, 0, DRAM_PCR0, + 0xb000 | burst_len | (banks[3].cas_used << 4)); + debug ("Mode bank 3: 0x%08x\n", + 0x8000 | burst_len | (banks[3].cas_used << 4)); + } else { + /* Seems to be needed to disable the bank */ + pci_write_cfg_word (0, 0, DRAM_PCR0, 0x3000 | 0x032); + } + + + pci_write_cfg_word (0, 0, 0xba, 0x00); + + return total_ram; +} + +extern int drv_isa_kbd_init (void); + +int last_stage_init (void) +{ + drv_isa_kbd_init (); + return 0; +} + +int overwrite_console (void) +{ + return (0); +} + +#define in_8 read_byte +#define out_8 write_byte + +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + + asm volatile ("mfmsr %0":"=r" (msr):); + + return msr; +} + +static __inline__ void set_msr (unsigned long msr) +{ + asm volatile ("mtmsr %0"::"r" (msr)); +} + +int board_early_init_f (void) +{ + unsigned char c_value = 0; + unsigned long msr; + + /* Basic init of PS/2 keyboard (needed for some reason)... */ + /* Ripped from John's code */ + while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0); + out_8 ((unsigned char *) 0xfe000064, 0xaa); + while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0); + c_value = in_8 ((unsigned char *) 0xfe000060); + while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0); + out_8 ((unsigned char *) 0xfe000064, 0xab); + while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0); + c_value = in_8 ((unsigned char *) 0xfe000060); + while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0); + out_8 ((unsigned char *) 0xfe000064, 0xae); +/* while ((in_8((unsigned char *)0xfe000064) & 0x01) == 0); */ +/* c_value = in_8((unsigned char *)0xfe000060); */ + + /* Enable FPU */ + msr = get_msr (); + set_msr (msr | MSR_FP); + + via_calibrate_bus_freq (); + + return 0; +} diff --git a/board/MAI/AmigaOneG3SE/articiaS.h b/board/MAI/AmigaOneG3SE/articiaS.h new file mode 100644 index 0000000..ce20d03 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/articiaS.h @@ -0,0 +1,142 @@ +#ifndef ARTICIAS_H +#define ARTICIAS_H + +#include "short_types.h" +#include + +#define REG_GROUP 0xF0 + +/* ArticiaS registers */ +#define GLOBALINFO0 0x50 +#define GLOBALINFO1 0x51 +#define GLOBALINFO2 0x52 +#define GLOBALINFO3 0x53 +#define GLOBALCTL0 0x54 +#define GLOBALCTL1 0x55 +#define NVRAMCTL 0x56 +#define PCI1ACR0 0x58 +#define PCI1ACR1 0x59 +#define PCI1ACR2 0x5a +#define PCI1ACR3 0x5b +#define HBUSACR0 0x5c +#define HBUSACR1 0x5d +#define HBUSACR2 0x5e +#define HBUSACR3 0x5f +#define HOSTINT0 0x68 +#define HOSTINT1 0x69 +#define HOSTINT2 0x6a +#define HOSTINT3 0x6b +#define HOSTRBCR 0x70 +#define XDBCR 0x74 + +#define LBSBCR2 0xd2 + + +/* Memory controller */ + +#define DIMM0_B0_SCR0 0x90 +#define DIMM0_B1_SCR0 0x94 +#define DIMM1_B2_SCR0 0x98 +#define DIMM1_B3_SCR0 0x9c +#define DIMM2_B4_SCR0 0xa0 +#define DIMM2_B5_SCR0 0xa4 +#define DIMM3_B6_SCR0 0xa8 +#define DIMM3_B7_SCR0 0xac + +#define DIMM0_TCR0 0xb0 +#define DIMM1_TCR0 0xb2 +#define DIMM2_TCR0 0xb4 +#define DIMM3_TCR0 0xb6 + +#define DRAM_REFRESH0 0xb8 +#define DRAM_GCR0 0xc0 +#define DRAM_PCR0 0xc6 +#define DRAM_ECC0 0xc4 +#define SRAM_CR 0xc8 +#define DRAM_RAS_CTL0 0xcc +#define DRAM_RAS_CTL1 0xcd + +/* Bits for REG_GROUP */ +#define REG_GROUP_MULTI (1<<1) +#define REG_GROUP_SPECIAL (1<<3) +#define REG_GROUP_DIAG (0x1<<4) +#define REG_GROUP_POWER (0x2<<4) + + +#define GLOBALINFO0_BO (1<<7) + + +#define GLOBALINFO2_B1ARBITER (1<<6) + + +#define HBUSACR0_CPUAPC (1<<0) +#define HBUSACR0_NUMREQ_2 (0<<1) +#define HBUSACR0_NUMREQ_3 (1<<1) +#define HBUSACR0_NUMREQ_4 (2<<1) +#define HBUSACR0_NUMREQ_MASK (7<<1) +#define HBUSACR0_RAW (1<<6) +#define HBUSACR0_WAIT (1<<7) +#define HBUSACR0_RESERVED (0x30) + + +#define HBUSACR2_BURST (1<<0) +#define HBUSACR2_LAT (1<<1) + + +#define HBUSACR3_LMWC_SM (1<<0) +#define HBUSACR3_LMWC_PCI1 (1<<1) +#define HBUSACR3_LMWC_PCI0 (1<<2) +#define HBUSACR3_PMWC_PCI1 (1<<3) +#define HBUSACR3_PMWC_PCI0 (1<<4) +#define HBUSACR3_FKH (1<<5) +#define HBUSACR3_92H_EN (1<<6) +#define HBUSACR3_60H_64H_EN (1<<7) + + +#define HOSTRBCR_PREFETCH (1<<4) + + +#define XDBCR_HWTOXD (1<<0) +#define XDBCR_KBTOXD (1<<1) +#define XDBCR_RTCTOXD (1<<2) +#define XDBCR_SCALE_1_1 (0x0<<3) +#define XDBCR_SCALE_2_2 (0x1<<3) +#define XDBCR_SCALE_3_2 (0x2<<3) +#define XDBCR_SCALE_4_4 (0x3<<3) +#define XDBCR_SCALE_5_8 (0x4<<3) +#define XDBCR_SCALE_6_8 (0x5<<3) +#define XDBCR_SCALE_8_8 (0x6<<3) +#define XDBCR_SCALE_0_16 (0x7<<3) +#define XDBCR_XDPROM (1<<7) + + +#define LBSBCR2_1_RWAC (1<<2) + + +/* PCI controller */ +#define ARTICIAS_PCI_CFGADDR 0xfec00cf8 +#define ARTICIAS_PCI_CFGDATA 0xfee00cfc + +#define ARTICIAS_PCI_BUS 0x80000000 +#define ARTICIAS_PCI_MAXSIZE 0x7cffffff +#define ARTICIAS_PCI_PHYS 0x80000000 + +#define ARTICIAS_SYS_BUS 0x00000000 +#define ARTICIAS_SYS_MAXSIZE 0x7fffffff +#define ARTICIAS_SYS_PHYS 0x00000000 + +#define ARTICIAS_PCIIO_BUS 0x00800000 +#define ARTICIAS_PCIIO_MAXSIZE 0x003fffff +#define ARTICIAS_PCIIO_PHYS 0xfe800000 + +#define ARTICIAS_ISAIO_BUS 0x00002000 +#define ARTICIAS_ISAIO_MAXSIZE 0x0000d000 +#define ARTICIAS_ISAIO_PHYS 0xfe002000 + + +/* Prototypes */ +long articiaS_ram_init(void); +void articiaS_pci_init(void); + + +#endif diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c new file mode 100644 index 0000000..d2e9f29 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c @@ -0,0 +1,576 @@ +/* + * (C) Copyright 2002 + * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "memio.h" +#include "articiaS.h" + +#undef ARTICIA_PCI_DEBUG + +#ifdef ARTICIA_PCI_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +struct pci_controller articiaS_hose; + +long irq_alloc(long wanted); + +static pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index); +static int articiaS_init_vga(void); +static void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table); +unsigned char pci_irq_alloc(void); + +extern void via_cfgfunc_via686(struct pci_controller * host, pci_dev_t dev, struct pci_config_table *table); +extern void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table); +extern void via_init_irq_routing(uint8 []); +extern void via_init_afterscan(void); + +#define cfgfunc_via686 1 +#define cfgfunc_dummy 2 +#define cfgfunc_ide_init 3 + +static struct pci_config_table config_table[] = +{ + { + 0x1106, PCI_ANY_ID, PCI_CLASS_BRIDGE_ISA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + (void *)cfgfunc_via686, {0, 0, 0} + }, + { + 0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,4, + (void *)cfgfunc_dummy, {0,0,0} + }, + { + 0x1106, 0x3068, PCI_ANY_ID, 0, 7, PCI_ANY_ID, + (void *)cfgfunc_dummy, {0,0,0} + }, + { + 0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,1, + (void *)cfgfunc_ide_init, {0,0,0} + }, + { + 0, + } +}; + + +void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table) +{ + + +} + +unsigned long irq_penalties[16] = +{ + 1000, /* 0:timer */ + 1000, /* 1:keyboard */ + 1000, /* 2:cascade */ + 50, /* 3:serial (COM2) */ + 50, /* 4:serial (COM1) */ + 4, /* 5:USB2 */ + 100, /* 6:floppy */ + 3, /* 7:parallel */ + 50, /* 8:AC97/MC97 */ + 0, /* 9: */ + 3, /* 10:: */ + 0, /* 11: */ + 3, /* 12: USB1 */ + 0, /* 13: */ + 100, /* 14: ide0 */ + 100, /* 15: ide1 */ +}; + + +/* + * The following defines a hard-coded interrupt mapping for the + * know devices on the board. + * If a device isn't found here, assumed to be a device that's + * plugged into a PCI or AGP slot + * NOTE: This table is machine dependant. + */ + +struct pci_irq_fixup_table +{ + uint8 bus; /* Bus number */ + uint8 device; /* Device number */ + uint8 func; /* Function number */ + uint8 interrupt; /* Interrupt to use (0xff to disable) */ +}; + +struct pci_irq_fixup_table fixuptab [] = +{ + { 0, 0, 0, 0xff}, /* Articia S host bridge */ + { 0, 1, 0, 0xff}, /* Articia S AGP bridge */ +/* { 0, 6, 0, 0x05}, /###* 3COM ethernet */ + { 0, 7, 0, 0xff}, /* VIA southbridge */ + { 0, 7, 1, 0x0e}, /* IDE controller in legacy mode */ +/* { 0, 7, 2, 0x05}, /###* First USB controller */ +/* { 0, 7, 3, 0x0c}, /###* Second USB controller (shares interrupt with ethernet) */ + { 0, 7, 4, 0xff}, /* ACPI Power Management */ +/* { 0, 7, 5, 0x08}, /###* AC97 */ +/* { 0, 7, 6, 0x08}, /###* MC97 */ + { 0xff, 0xff, 0xff, 0xff} +}; + + +/* + * This table maps IRQ's to PCI interrupts + */ + +uint8 pci_intmap[4] = {0, 0, 0, 0}; + +/* + * Map PCI slots to interrupt routings + * This table lists the device number assigned to a card inserted + * into the slot, along with a permutation for the slot's IRQ routing. + * NOTE: This table is machine dependant. + */ + +struct pci_slot_irq_routing +{ + uint8 bus; + uint8 device; + + uint8 ints[4]; +}; + +struct pci_slot_irq_routing amigaone_pci_routing[] = +{ + {0, 8, {0, 1, 2, 3}}, /* Slot 1 (left of riser slot) */ + {0, 9, {1, 2, 3, 0}}, /* Slot 2 (middle slot) */ + {0, 10, {2, 3, 0, 1}}, /* Slot 3 (leftmost slot) */ + {1, 0, {1, 0, 2, 3}}, /* AGP slot (only IRQA and IRQB) */ + {1, 1, {1, 2, 3, 0}}, /* PCI slot on AGP bus */ + {0, 6, {3, 3, 3, 3}}, /* On board ethernet */ + {0, 7, {0, 1, 2, 3}}, /* Southbridge */ + {0xff, 0, {0, 0, 0, 0}} +}; + +void articiaS_pci_irq_init(void) +{ + char *s; + + s = getenv("pci_irqa"); + if (s) + pci_intmap[0] = simple_strtoul (s, NULL, 10); + else + pci_intmap[0] = pci_irq_alloc(); + + s = getenv("pci_irqb"); + if (s) + pci_intmap[1] = simple_strtoul (s, NULL, 10); + else + pci_intmap[1] = pci_irq_alloc(); + + s = getenv("pci_irqc"); + if (s) + pci_intmap[2] = simple_strtoul (s, NULL, 10); + else + pci_intmap[2] = pci_irq_alloc(); + + s = getenv("pci_irqd"); + if (s) + pci_intmap[3] = simple_strtoul (s, NULL, 10); + else + pci_intmap[3] = pci_irq_alloc(); +} + + +unsigned char pci_irq_alloc(void) +{ + int i; + int interrupt = 10; + unsigned long min_penalty = 1000; + + /* Search for the minimal penalty, favoring interrupts at the end */ + for (i = 0; i < 16; i++) + { + if (irq_penalties[i] <= min_penalty) + { + interrupt = i; + min_penalty = irq_penalties[i]; + } + } + + PRINTF("pci_irq_alloc: Minimal penalty is %ld for %d\n", min_penalty, interrupt); + + irq_penalties[interrupt]++; + + return interrupt; +} + + +void articiaS_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + int8 bus, device, func, pin, line; + int i; + + bus = PCI_BUS(dev); + device = PCI_DEV(dev); + func = PCI_FUNC(dev); + + PRINTF("Fixup irq of %d:%d.%d\n", bus, device, func); + + /* Search for the device in the table */ + for (i = 0; fixuptab[i].bus != 0xff; i++) + { + if (bus == fixuptab[i].bus && device == fixuptab[i].device && func == fixuptab[i].func) + { + /* If the device needs an interrupt, write it */ + if (fixuptab[i].interrupt != 0xff) + { + PRINTF("Assigning IRQ %d (fixed)\n", fixuptab[i].interrupt); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, fixuptab[i].interrupt); + } + else + { + /* Otherwise, see if it wants an interrupt, and disable it if needed */ + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + if (pin) + { + PRINTF("Disabling IRQ\n"); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0xff); + } + } + + return; + } + } + + /* If we get here, we have another PCI device in a slot... find the appropriate IRQ */ + + /* Find matching pin */ + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + pin--; + + /* Search for it's map */ + for (i = 0; amigaone_pci_routing[i].bus != 0xff; i++) + { + if (bus == amigaone_pci_routing[i].bus && device == amigaone_pci_routing[i].device) + { + line = pci_intmap[amigaone_pci_routing[i].ints[pin]]; + PRINTF("Assigning IRQ %d (pin %d)\n", line, pin); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, line); + return; + } + } + + PRINTF("Unkonwn PCI device found\n"); +} + +void articiaS_pci_init (void) +{ + int i; + char *s; + + PRINTF("atriciaS_pci_init\n"); + + /* Why aren't these relocated?? */ + for (i=0; config_table[i].config_device; i++) + { + switch((int)config_table[i].config_device) + { + case cfgfunc_via686: config_table[i].config_device = via_cfgfunc_via686; break; + case cfgfunc_dummy: config_table[i].config_device = pci_cfgfunc_dummy; break; + case cfgfunc_ide_init: config_table[i].config_device = via_cfgfunc_ide_init; break; + default: PRINTF("Error: Unknown constant\n"); + } + } + + articiaS_hose.first_busno = 0; + articiaS_hose.last_busno = 0xff; + articiaS_hose.config_table = config_table; + articiaS_hose.fixup_irq = articiaS_pci_fixup_irq; + + articiaS_pci_irq_init(); + + /* System memory */ + pci_set_region(articiaS_hose.regions + 0, + ARTICIAS_SYS_BUS, + ARTICIAS_SYS_PHYS, + ARTICIAS_SYS_MAXSIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(articiaS_hose.regions + 1, + ARTICIAS_PCI_BUS, + ARTICIAS_PCI_PHYS, + ARTICIAS_PCI_MAXSIZE, + PCI_REGION_MEM); + + /* PCI io space */ + pci_set_region(articiaS_hose.regions + 2, + ARTICIAS_PCIIO_BUS, + ARTICIAS_PCIIO_PHYS, + ARTICIAS_PCIIO_MAXSIZE, + PCI_REGION_IO); + + /* PCI/ISA io space */ + pci_set_region(articiaS_hose.regions + 3, + ARTICIAS_ISAIO_BUS, + ARTICIAS_ISAIO_PHYS, + ARTICIAS_ISAIO_MAXSIZE, + PCI_REGION_IO); + + + articiaS_hose.region_count = 4; + + pci_setup_indirect(&articiaS_hose, ARTICIAS_PCI_CFGADDR, ARTICIAS_PCI_CFGDATA); + PRINTF("Registering articia hose...\n"); + pci_register_hose(&articiaS_hose); + PRINTF("Enabling AGP...\n"); + pci_write_config_byte(PCI_BDF(0,0,0), 0x58, 0x01); + PRINTF("Scanning bus...\n"); + articiaS_hose.last_busno = pci_hose_scan(&articiaS_hose); + + via_init_irq_routing(pci_intmap); + + PRINTF("After-Scan results:\n"); + PRINTF("Bus range: %d - %d\n", articiaS_hose.first_busno , articiaS_hose.last_busno); + + via_init_afterscan(); + + pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF); + + s = getenv("as_irq"); + if (s) + { + pci_write_config_byte(PCI_BDF(0,0,0), PCI_INTERRUPT_LINE, simple_strtoul (s, NULL, 10)); + } + + s = getenv("x86_run_bios"); + if (!s || (s && strcmp(s, "on")==0)) + { + if (articiaS_init_vga() == -1) + { + /* If the VGA didn't init and we have stdout set to VGA, reset to serial */ +/* s = getenv("stdout"); */ +/* if (s && strcmp(s, "vga") == 0) */ +/* { */ +/* setenv("stdout", "serial"); */ +/* } */ + } + } + pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF); + +} + +pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index) +{ + unsigned int sub_bus, found_multi=0; + unsigned short vendor, class; + unsigned char header_type; + pci_dev_t dev; + u8 c1, c2; + + sub_bus = bus; + + for (dev = PCI_BDF(bus,0,0); + dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); + dev += PCI_BDF(0,0,1)) + { + if ( dev == PCI_BDF(hose->first_busno,0,0) ) + continue; + + if (PCI_FUNC(dev) && !found_multi) + continue; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); + + pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); + + if (vendor != 0xffff && vendor != 0x0000) + { + + if (!PCI_FUNC(dev)) + found_multi = header_type & 0x80; + pci_hose_read_config_byte(hose, dev, 0x0B, &c1); + pci_hose_read_config_byte(hose, dev, 0x0A, &c2); + class = c1<<8 | c2; + /*printf("At %02x:%02x:%02x: class %x\n", */ + /* PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class); */ + if (class == find_class) + { + if (index == 0) + return dev; + else index--; + } + } + } + + return ~0; +} + + +/* + * For a given bus number, find the bridge on this hose that provides this + * bus number. The function scans for bridges and peeks config space offset + * 0x19 (PCI_SECONDARY_BUS). + */ +pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr) +{ + pci_dev_t dev; + int bus; + unsigned int found_multi=0; + unsigned char header_type; + unsigned short vendor; + unsigned char secondary_bus; + + if (hose == NULL) hose = &articiaS_hose; + + if (busnr < hose->first_busno || busnr > hose->last_busno) return PCI_ANY_ID; /* Not in range */ + + /* + * The bridge must be on a lower bus number + */ + for (bus = hose->first_busno; bus < busnr; bus++) + { + for (dev = PCI_BDF(bus,0,0); + dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); + dev += PCI_BDF(0,0,1)) + { + if ( dev == PCI_BDF(hose->first_busno,0,0) ) + continue; + + if (PCI_FUNC(dev) && !found_multi) + continue; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); + + pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); + + if (vendor != 0xffff && vendor != 0x0000) + { + + if (!PCI_FUNC(dev)) + found_multi = header_type & 0x80; + if (header_type == 1) /* Bridge device header */ + { + pci_hose_read_config_byte(hose, dev, PCI_SECONDARY_BUS, &secondary_bus); + if ((int)secondary_bus == busnr) return dev; + } + + } + } + } + return PCI_ANY_ID; +} + +static short classes[] = +{ + PCI_CLASS_DISPLAY_VGA, + PCI_CLASS_DISPLAY_XGA, + PCI_CLASS_DISPLAY_3D, + PCI_CLASS_DISPLAY_OTHER, + ~0 +}; + +extern int execute_bios(pci_dev_t gr_dev, void *); + +pci_dev_t video_dev; + +int articiaS_init_vga (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + extern void shutdown_bios(void); + pci_dev_t dev = ~0; + int busnr = 0; + int classnr = 0; + + video_dev = PCI_ANY_ID; + + printf("VGA: "); + + PRINTF("Trying to initialize x86 VGA Card(s)\n"); + + while (dev == ~0) + { + PRINTF("Searching for class 0x%x on bus %d\n", classes[classnr], busnr); + /* Find the first of this class on this bus */ + dev = pci_hose_find_class(&articiaS_hose, busnr, classes[classnr], 0); + if (dev != ~0) + { + PRINTF("Found VGA Card at %02x:%02x:%02x\n", PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); + break; + } + busnr++; + if (busnr > articiaS_hose.last_busno) + { + busnr = 0; + classnr ++; + if (classes[classnr] == ~0) + { + printf("NOT PRESENT\n"); + return -1; + } + } + } + + /* + * If we get here we have found the first graphics card. + * If the bus number is not 0, then it is probably behind a bridge, and the + * bridge needs to be told to forward VGA access. + */ + + if (PCI_BUS(dev) != 0) + { + pci_dev_t bridge; + PRINTF("Behind bridge, looking for bridge\n"); + bridge = pci_find_bridge_for_bus(&articiaS_hose, PCI_BUS(dev)); + if (dev != PCI_ANY_ID) + { + unsigned char agp_control_0; + PRINTF("Got the bridge at %02x:%02x:%02x\n", + PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge)); + pci_hose_read_config_byte(&articiaS_hose, bridge, 0x3E, &agp_control_0); + agp_control_0 |= 0x18; + pci_hose_write_config_byte(&articiaS_hose, bridge, 0x3E, agp_control_0); + PRINTF("Configured for VGA forwarding\n"); + } + } + + /* + * Now try to run the bios + */ + PRINTF("Trying to run bios now\n"); + if (execute_bios(dev, gd->relocaddr)) + { + printf("OK\n"); + video_dev = dev; + } + else + { + printf("ERROR\n"); + } + + PRINTF("Done scanning.\n"); + + shutdown_bios(); + + if (dev == PCI_ANY_ID) return -1; + else return 0; + +} diff --git a/board/MAI/AmigaOneG3SE/board_asm_init.S b/board/MAI/AmigaOneG3SE/board_asm_init.S new file mode 100644 index 0000000..086b19c --- /dev/null +++ b/board/MAI/AmigaOneG3SE/board_asm_init.S @@ -0,0 +1,156 @@ +#include "macros.h" + + +#define GLOBALINFO0 0x50 +#define GLOBALINFO0_BO (1<<7) +#define GLOBALINFO2_B1ARBITER (1<<6) +#define HBUSACR0 0x5c +#define HBUSACR2_BURST (1<<0) +#define HBUSACR2_LAT (1<<1) + +#define RECEIVER_HOLDING 0 +#define TRANSMITTER_HOLDING 0 +#define INTERRUPT_ENABLE 1 +#define INTERRUPT_STATUS 2 +#define FIFO_CONTROL 2 +#define LINE_CONTROL 3 +#define MODEM_CONTROL 4 +#define LINE_STATUS 5 +#define MODEM_STATUS 6 +#define SCRATCH_PAD 7 + +#define DIVISOR_LATCH_LSB 0 +#define DIVISOR_LATCH_MSB 1 +#define PRESCALER_DIVISION 5 + +#define UART(x) (0x3f8+(x)) + +#define GLOBALINFO0 0x50 +#define GLOBALINFO0_BO (1<<7) +#define GLOBALINFO2_B1ARBITER (1<<6) +#define HBUSACR0 0x5c +#define HBUSACR2_BURST (1<<0) +#define HBUSACR2_LAT (1<<1) + +#define SUPERIO_1 ((7 << 3) | (0)) +#define SUPERIO_2 ((7 << 3) | (1)) + + .globl board_asm_init + +board_asm_init: + mflr r29 + /* Set 'Must-set' register */ + li r3, 0 + li r4, 0 + li r5, 0x5e + bl pci_read_cfg_byte + ori r3, r3, (1<<1) + xori r6, r3, (1<<1) + li r3, 0 + bl pci_write_cfg_byte + + li r3, 0 + li r5, 0x52 + bl pci_read_cfg_byte + ori r6, r3, (1<<6) + li r3, 0 + bl pci_write_cfg_byte + + li r3, 0 + li r4, 0x08 + li r5, 0xd2 + bl pci_read_cfg_byte + ori r6, r3, (1<<2) + li r3, 0 + bl pci_write_cfg_byte + + + /* Do PCI reset */ +/* li r3, 0 + li r4, 0x38 + li r5, 0x47 + bl pci_read_cfg_byte + ori r6, r3, 0x01 + li r3, 0 + li r4, 0x38 + li r5, 0x47 + bl pci_write_cfg_byte*/ + + + /* Enable NVRAM for environment */ + li r3, 0 + li r4, 0 + li r5, 0x56 + li r6, 0x0B + bl pci_write_cfg_byte + + + /* Init Super-I/O chips */ + + siowb 0x40, 0x08 + siowb 0x41, 0x01 + siowb 0x45, 0x80 + siowb 0x46, 0x60 + siowb 0x47, 0x20 + siowb 0x48, 0x01 + siowb 0x4a, 0xc4 + siowb 0x50, 0x0e + siowb 0x51, 0x76 + siowb 0x52, 0x34 + siowb 0x54, 0x00 + siowb 0x55, 0x90 + siowb 0x56, 0x99 + siowb 0x57, 0x90 + siowb 0x85, 0x01 + + /* Enable configuration mode for SuperIO */ + li r3, 0 + li r4, (7<<3) + li r5, 0x85 + bl pci_read_cfg_byte + ori r6, r3, 0x02 + mr r31, r6 + li r3,0 + bl pci_write_cfg_byte + + /* COM1 as 3f8 */ + outb 0x3f0, 0xe7 + outb 0x3f1, 0xfe + + /* COM2 as 2f8 */ + outb 0x3f0, 0xe8 + outb 0x3f1, 0xeb + + /* Enable */ + outb 0x3f0, 0xe2 + inb r3, 0x3f1 + ori r3, r3, 0x0c + outb 0x3f0, 0xe2 + outbr 0x3f1, r3 + + /* Disable configuration mode */ + li r3, 0 + li r4, (7<<3) + li r5, 0x85 + mr r6, r31 + bl pci_write_cfg_byte + + /* Set line control */ + outb UART(LINE_CONTROL), 0x83 + outb UART(DIVISOR_LATCH_LSB), 0x0c + outb UART(DIVISOR_LATCH_MSB), 0x00 + outb UART(LINE_CONTROL), 0x3 + + mtlr r29 + blr + + + .globl new_reset + .globl new_reset_end +new_reset: + li r0, 0x100 + oris r0, r0, 0xFFF0 + mtlr r0 + blr + +new_reset_end: diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c new file mode 100644 index 0000000..3e2835a --- /dev/null +++ b/board/MAI/AmigaOneG3SE/cmd_boota.c @@ -0,0 +1,129 @@ +#include +#include +#include "../disk/part_amiga.h" +#include + + +#undef BOOTA_DEBUG + +#ifdef BOOTA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +struct block_header { + u32 id; + u32 summed_longs; + s32 chk_sum; +}; + +extern block_dev_desc_t *ide_get_dev (int dev); +extern struct bootcode_block *get_bootcode (block_dev_desc_t * dev_desc); +extern int sum_block (struct block_header *header); + +struct bootcode_block bblk; + +int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR; + unsigned char *base_address; + unsigned long offset; + + unsigned long part_number = 0; + block_dev_desc_t *boot_disk; + char *s; + struct bootcode_block *boot_code; + + /* Get parameters */ + + switch (argc) { + case 2: + load_address = (unsigned char *) simple_strtol (argv[1], NULL, 16); + part_number = 0; + break; + case 3: + load_address = (unsigned char *) simple_strtol (argv[1], NULL, 16); + part_number = simple_strtol (argv[2], NULL, 16); + break; + } + + base_address = load_address; + + PRINTF ("Loading boot code from disk %d to %p\n", part_number, + load_address); + + /* Find the appropriate disk device */ + boot_disk = ide_get_dev (part_number); + if (!boot_disk) { + PRINTF ("Unknown disk %d\n", part_number); + return 1; + } + + /* Find the bootcode block */ + boot_code = get_bootcode (boot_disk); + if (!boot_code) { + PRINTF ("Not a bootable disk %d\n", part_number); + return 1; + } + + /* Only use the offset from the first block */ + offset = boot_code->load_data[0]; + memcpy (load_address, &boot_code->load_data[1], 122 * 4); + load_address += 122 * 4; + + /* Setup for the loop */ + bblk.next = boot_code->next; + boot_code = &bblk; + + /* Scan the chain, and copy the loader succesively into the destination area */ + while (0xffffffff != boot_code->next) { + PRINTF ("Loading block %d\n", boot_code->next); + + /* Load block */ + if (1 != + boot_disk->block_read (boot_disk->dev, boot_code->next, 1, + (ulong *) & bblk)) { + PRINTF ("Read error\n"); + return 1; + } + + /* check sum */ + if (sum_block ((struct block_header *) (ulong *) & bblk) != 0) { + PRINTF ("Checksum error\n"); + return 1; + } + + /* Ok, concatenate it to the already loaded code */ + memcpy (load_address, boot_code->load_data, 123 * 4); + load_address += 123 * 4; + } + + printf ("Bootcode loaded to %p (size %d)\n", base_address, + load_address - base_address); + printf ("Entry point at %p\n", base_address + offset); + + flush_cache (base_address, load_address - base_address); + + + s = getenv ("autostart"); + if (s && strcmp (s, "yes") == 0) { + DECLARE_GLOBAL_DATA_PTR; + + void (*boot) (bd_t *, char *, block_dev_desc_t *); + char *args; + + boot = (void (*)(bd_t *, char *, block_dev_desc_t *)) (base_address + offset); + boot (gd->bd, getenv ("amiga_bootargs"), boot_disk); + } + + + return 0; +} +#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP) +U_BOOT_CMD( + boota, 3, 1, do_boota, + "boota - boot an Amiga kernel\n", + "address disk" +); +#endif /* _CMD_BOOTA_H */ diff --git a/board/MAI/AmigaOneG3SE/config.mk b/board/MAI/AmigaOneG3SE/config.mk new file mode 100644 index 0000000..930a793 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AmigaOneG3SE boards +# + +X86EMU = -I../bios_emulator/scitech/include -I../bios_emulator/scitech/src/x86emu + +TEXT_BASE = 0xfff00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) -Dprintk=printf #-DDEBUG diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c new file mode 100644 index 0000000..d4be889 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/enet.c @@ -0,0 +1,884 @@ +/* + * (C) Copyright 2002 + * Adam Kowalczyk, ACK Software Controls Inc. akowalczyk@cogeco.ca + * + * Some portions taken from 3c59x.c Written 1996-1999 by Donald Becker. + * + * Outline of the program based on eepro100.c which is + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "articiaS.h" +#include "memio.h" + +/* 3Com Ethernet PCI definitions*/ + +/* #define PCI_VENDOR_ID_3COM 0x10B7 */ +#define PCI_DEVICE_ID_3COM_3C905C 0x9200 + +/* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */ + +#define TotalReset (0<<11) +#define SelectWindow (1<<11) +#define StartCoax (2<<11) +#define RxDisable (3<<11) +#define RxEnable (4<<11) +#define RxReset (5<<11) +#define UpStall (6<<11) +#define UpUnstall (6<<11)+1 +#define DownStall (6<<11)+2 +#define DownUnstall (6<<11)+3 +#define RxDiscard (8<<11) +#define TxEnable (9<<11) +#define TxDisable (10<<11) +#define TxReset (11<<11) +#define FakeIntr (12<<11) +#define AckIntr (13<<11) +#define SetIntrEnb (14<<11) +#define SetStatusEnb (15<<11) +#define SetRxFilter (16<<11) +#define SetRxThreshold (17<<11) +#define SetTxThreshold (18<<11) +#define SetTxStart (19<<11) +#define StartDMAUp (20<<11) +#define StartDMADown (20<<11)+1 +#define StatsEnable (21<<11) +#define StatsDisable (22<<11) +#define StopCoax (23<<11) +#define SetFilterBit (25<<11) + +/* The SetRxFilter command accepts the following classes */ + +#define RxStation 1 +#define RxMulticast 2 +#define RxBroadcast 4 +#define RxProm 8 + +/* 3Com status word defnitions */ + +#define IntLatch 0x0001 +#define HostError 0x0002 +#define TxComplete 0x0004 +#define TxAvailable 0x0008 +#define RxComplete 0x0010 +#define RxEarly 0x0020 +#define IntReq 0x0040 +#define StatsFull 0x0080 +#define DMADone (1<<8) +#define DownComplete (1<<9) +#define UpComplete (1<<10) +#define DMAInProgress (1<<11) /* DMA controller is still busy.*/ +#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ + +/* Polling Registers */ + +#define DnPoll 0x2d +#define UpPoll 0x3d + +/* Register window 0 offets */ + +#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ +#define Wn0EepromData 12 /* Window 0: EEPROM results register. */ +#define IntrStatus 0x0E /* Valid in all windows. */ + +/* Register window 0 EEPROM bits */ + +#define EEPROM_Read 0x80 +#define EEPROM_WRITE 0x40 +#define EEPROM_ERASE 0xC0 +#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ +#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ + +/* EEPROM locations. */ + +#define PhysAddr01 0 +#define PhysAddr23 1 +#define PhysAddr45 2 +#define ModelID 3 +#define EtherLink3ID 7 +#define IFXcvrIO 8 +#define IRQLine 9 +#define NodeAddr01 10 +#define NodeAddr23 11 +#define NodeAddr45 12 +#define DriverTune 13 +#define Checksum 15 + +/* Register window 1 offsets, the window used in normal operation */ + +#define TX_FIFO 0x10 +#define RX_FIFO 0x10 +#define RxErrors 0x14 +#define RxStatus 0x18 +#define Timer 0x1A +#define TxStatus 0x1B +#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ + +/* Register Window 2 */ + +#define Wn2_ResetOptions 12 + +/* Register Window 3: MAC/config bits */ + +#define Wn3_Config 0 /* Internal Configuration */ +#define Wn3_MAC_Ctrl 6 +#define Wn3_Options 8 + +#define BFEXT(value, offset, bitcount) \ + ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) + +#define BFINS(lhs, rhs, offset, bitcount) \ + (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ + (((rhs) & ((1 << (bitcount)) - 1)) << (offset))) + +#define RAM_SIZE(v) BFEXT(v, 0, 3) +#define RAM_WIDTH(v) BFEXT(v, 3, 1) +#define RAM_SPEED(v) BFEXT(v, 4, 2) +#define ROM_SIZE(v) BFEXT(v, 6, 2) +#define RAM_SPLIT(v) BFEXT(v, 16, 2) +#define XCVR(v) BFEXT(v, 20, 4) +#define AUTOSELECT(v) BFEXT(v, 24, 1) + +/* Register Window 4: Xcvr/media bits */ + +#define Wn4_FIFODiag 4 +#define Wn4_NetDiag 6 +#define Wn4_PhysicalMgmt 8 +#define Wn4_Media 10 + +#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */ +#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */ +#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */ +#define Media_LnkBeat 0x0800 + +/* Register Window 7: Bus Master control */ + +#define Wn7_MasterAddr 0 +#define Wn7_MasterLen 6 +#define Wn7_MasterStatus 12 + +/* Boomerang bus master control registers. */ + +#define PktStatus 0x20 +#define DownListPtr 0x24 +#define FragAddr 0x28 +#define FragLen 0x2c +#define TxFreeThreshold 0x2f +#define UpPktStatus 0x30 +#define UpListPtr 0x38 + +/* The Rx and Tx descriptor lists. */ + +#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ +#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */ + +struct rx_desc_3com { + u32 next; /* Last entry points to 0 */ + u32 status; /* FSH -> Frame Start Header */ + u32 addr; /* Up to 63 addr/len pairs possible */ + u32 length; /* Set LAST_FRAG to indicate last pair */ +}; + +/* Values for the Rx status entry. */ + +#define RxDComplete 0x00008000 +#define RxDError 0x4000 +#define IPChksumErr (1<<25) +#define TCPChksumErr (1<<26) +#define UDPChksumErr (1<<27) +#define IPChksumValid (1<<29) +#define TCPChksumValid (1<<30) +#define UDPChksumValid (1<<31) + +struct tx_desc_3com { + u32 next; /* Last entry points to 0 */ + u32 status; /* bits 0:12 length, others see below */ + u32 addr; + u32 length; +}; + +/* Values for the Tx status entry. */ + +#define CRCDisable 0x2000 +#define TxDComplete 0x8000 +#define AddIPChksum 0x02000000 +#define AddTCPChksum 0x04000000 +#define AddUDPChksum 0x08000000 +#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */ + +/* XCVR Types */ + +#define XCVR_10baseT 0 +#define XCVR_AUI 1 +#define XCVR_10baseTOnly 2 +#define XCVR_10base2 3 +#define XCVR_100baseTx 4 +#define XCVR_100baseFx 5 +#define XCVR_MII 6 +#define XCVR_NWAY 8 +#define XCVR_ExtMII 9 +#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */ + +struct descriptor { /* A generic descriptor. */ + u32 next; /* Last entry points to 0 */ + u32 status; /* FSH -> Frame Start Header */ + u32 addr; /* Up to 63 addr/len pairs possible */ + u32 length; /* Set LAST_FRAG to indicate last pair */ +}; + +/* Misc. definitions */ + +#define NUM_RX_DESC PKTBUFSRX * 10 +#define NUM_TX_DESC 1 /* Number of TX descriptors */ + +#define TOUT_LOOP 1000000 + +#define ETH_ALEN 6 + +#define EL3WINDOW(dev, win_num) ETH_OUTW(dev, SelectWindow + (win_num), EL3_CMD) +#define EL3_CMD 0x0e +#define EL3_STATUS 0x0e + + +#undef ETH_DEBUG + +#ifdef ETH_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + + +static struct rx_desc_3com *rx_ring; /* RX descriptor ring */ +static struct tx_desc_3com *tx_ring; /* TX descriptor ring */ +static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN]; /* storage for the incoming messages */ +static int rx_next = 0; /* RX descriptor ring pointer */ +static int tx_next = 0; /* TX descriptor ring pointer */ +static int tx_threshold; + +static void init_rx_ring(struct eth_device* dev); +static void purge_tx_ring(struct eth_device* dev); + +static void read_hw_addr(struct eth_device* dev, bd_t * bis); + +static int eth_3com_init(struct eth_device* dev, bd_t *bis); +static int eth_3com_send(struct eth_device* dev, volatile void *packet, int length); +static int eth_3com_recv(struct eth_device* dev); +static void eth_3com_halt(struct eth_device* dev); + +#define io_to_phys(a) pci_io_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_io(a) pci_phys_to_io((pci_dev_t)dev->priv, a) +#define mem_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_mem(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +static inline int ETH_INL(struct eth_device* dev, u_long addr) +{ + __asm volatile ("eieio"); + return le32_to_cpu(*(volatile u32 *)io_to_phys(addr + dev->iobase)); +} + +static inline int ETH_INW(struct eth_device* dev, u_long addr) +{ + __asm volatile ("eieio"); + return le16_to_cpu(*(volatile u16 *)io_to_phys(addr + dev->iobase)); +} + +static inline int ETH_INB(struct eth_device* dev, u_long addr) +{ + __asm volatile ("eieio"); + return *(volatile u8 *)io_to_phys(addr + dev->iobase); +} + +static inline void ETH_OUTB(struct eth_device* dev, int command, u_long addr) +{ + *(volatile u8 *)io_to_phys(addr + dev->iobase) = command; + __asm volatile ("eieio"); +} + +static inline void ETH_OUTW(struct eth_device* dev, int command, u_long addr) +{ + *(volatile u16 *)io_to_phys(addr + dev->iobase) = cpu_to_le16(command); + __asm volatile ("eieio"); +} + +static inline void ETH_OUTL(struct eth_device* dev, int command, u_long addr) +{ + *(volatile u32 *)io_to_phys(addr + dev->iobase) = cpu_to_le32(command); + __asm volatile ("eieio"); +} + +static inline int ETH_STATUS(struct eth_device* dev) +{ + __asm volatile ("eieio"); + return le16_to_cpu(*(volatile u16 *)io_to_phys(EL3_STATUS + dev->iobase)); +} + +static inline void ETH_CMD(struct eth_device* dev, int command) +{ + *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command); + __asm volatile ("eieio"); +} + +/* Command register is always in the same spot in all the register windows */ +/* This function issues a command and waits for it so complete by checking the CmdInProgress bit */ + +static int issue_and_wait(struct eth_device* dev, int command) +{ + + int i, status; + + ETH_CMD(dev, command); + for (i = 0; i < 2000; i++) { + status = ETH_STATUS(dev); + /*printf ("Issue: status 0x%4x.\n", status); */ + if (!(status & CmdInProgress)) + return 1; + } + + /* OK, that didn't work. Do it the slow way. One second */ + for (i = 0; i < 100000; i++) { + status = ETH_STATUS(dev); + /*printf ("Issue: status 0x%4x.\n", status); */ + return 1; + udelay(10); + } + PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) ); + return 0; +} + +/* Determine network media type and set up 3com accordingly */ +/* I think I'm going to start with something known first like 10baseT */ + +static int auto_negotiate(struct eth_device* dev) +{ + int i; + + EL3WINDOW(dev, 1); + + /* Wait for Auto negotiation to complete */ + for (i = 0; i <= 1000; i++) + { + if (ETH_INW(dev, 2) & 0x04) + break; + udelay(100); + + if (i == 1000) + { + PRINTF("Error: Auto negotiation failed\n"); + return 0; + } + } + + + return 1; +} + +void eth_interrupt(struct eth_device *dev) +{ + u16 status = ETH_STATUS(dev); + + printf("eth0: status = 0x%04x\n", status); + + if (!(status & IntLatch)) + return; + + if (status & (1<<6)) + { + ETH_CMD(dev, AckIntr | (1<<6)); + printf("Acknowledged Interrupt command\n"); + } + + if (status & DownComplete) + { + ETH_CMD(dev, AckIntr | DownComplete); + printf("Acknowledged DownComplete\n"); + } + + if (status & UpComplete) + { + ETH_CMD(dev, AckIntr | UpComplete); + printf("Acknowledged UpComplete\n"); + } + + ETH_CMD(dev, AckIntr | IntLatch); + printf("Acknowledged IntLatch\n"); +} + +int eth_3com_initialize(bd_t *bis) +{ + u32 eth_iobase = 0, status; + int card_number = 0, ret; + struct eth_device* dev; + pci_dev_t devno; + char *s; + + s = getenv("3com_base"); + + /* Find ethernet controller on the PCI bus */ + + if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0) + { + PRINTF("Error: Cannot find the ethernet device on the PCI bus\n"); + goto Done; + } + + if (s) + { + unsigned long base = atoi(s); + pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01); + } + + ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, ð_iobase); + eth_iobase &= ~0xf; + + PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase); + + pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled */ + + ret = pci_read_config_dword(devno, PCI_COMMAND, &status); + + if (!(status & PCI_COMMAND_IO)) + { + printf("Error: Cannot enable IO access.\n"); + goto Done; + } + + if (!(status & PCI_COMMAND_MEMORY)) + { + printf("Error: Cannot enable MEMORY access.\n"); + goto Done; + } + + if (!(status & PCI_COMMAND_MASTER)) + { + printf("Error: Cannot enable Bus Mastering.\n"); + goto Done; + } + + dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */ + + sprintf(dev->name, "3Com 3c920c#%d", card_number); + dev->iobase = eth_iobase; + dev->priv = (void*) devno; + dev->init = eth_3com_init; + dev->halt = eth_3com_halt; + dev->send = eth_3com_send; + dev->recv = eth_3com_recv; + + eth_register(dev); + +/* { */ +/* char interrupt; */ +/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */ +/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */ + +/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */ +/* irq_install_handler(interrupt, eth_interrupt, dev); */ +/* } */ + + card_number++; + + /* Set the latency timer for value */ + s = getenv("3com_latency"); + if (s) + { + ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s)); + } + else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a); + + read_hw_addr(dev, bis); /* get the MAC address from Window 2*/ + + /* Reset the ethernet controller */ + + PRINTF ("Issuing reset command....\n"); + if (!issue_and_wait(dev, TotalReset)) + { + printf("Error: Cannot reset ethernet controller.\n"); + goto Done; + } + else + PRINTF ("Ethernet controller reset.\n"); + + /* allocate memory for rx and tx rings */ + + if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16))) + { + PRINTF ("Cannot allocate memory for RX_RING.....\n"); + goto Done; + } + + if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16))) + { + PRINTF ("Cannot allocate memory for TX_RING.....\n"); + goto Done; + } + +Done: + return status; +} + + +static int eth_3com_init(struct eth_device* dev, bd_t *bis) +{ + int i, status = 0; + int tx_cur, loop; + u16 status_enable, intr_enable; + struct descriptor *ias_cmd; + + /* Determine what type of network the machine is connected to */ + /* presently drops the connect to 10Mbps */ + + if (!auto_negotiate(dev)) + { + printf("Error: Cannot determine network media.\n"); + goto Done; + } + + issue_and_wait(dev, TxReset); + issue_and_wait(dev, RxReset|0x04); + + /* Switch to register set 7 for normal use. */ + EL3WINDOW(dev, 7); + + /* Initialize Rx and Tx rings */ + + init_rx_ring(dev); + purge_tx_ring(dev); + + ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm); + + issue_and_wait(dev,SetTxStart|0x07ff); + + /* Below sets which indication bits to be seen. */ + + status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6); + ETH_CMD(dev, status_enable); + + /* Below sets no bits are to cause an interrupt since this is just polling */ + + intr_enable = SetIntrEnb; +/* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */ + ETH_CMD(dev, intr_enable); + ETH_OUTB(dev, 127, UpPoll); + + /* Ack all pending events, and set active indicator mask */ + + ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq); + ETH_CMD(dev, intr_enable); + + /* Tell the adapter where the RX ring is located */ + + issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */ + ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr); + ETH_CMD(dev, RxEnable); /* Enable the receiver. */ + issue_and_wait(dev,UpUnstall); + + /* Send the Individual Address Setup frame */ + + tx_cur = tx_next; + tx_next = ((tx_next+1) % NUM_TX_DESC); + + ias_cmd = (struct descriptor *)&tx_ring[tx_cur]; + ias_cmd->status = cpu_to_le32(1<<31); /* set DnIndicate bit. */ + ias_cmd->next = 0; + ias_cmd->addr = cpu_to_le32((u32)&bis->bi_enetaddr[0]); + ias_cmd->length = cpu_to_le32(6 | LAST_FRAG); + + /* Tell the adapter where the TX ring is located */ + + ETH_CMD(dev, TxEnable); /* Enable transmitter. */ + issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */ + ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr); + issue_and_wait(dev, DownUnstall); + for (i=0; !(ETH_STATUS(dev) & DownComplete); i++) + { + if (i >= TOUT_LOOP) + { + PRINTF("TX Ring status (Init): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status)); + PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev)); + goto Done; + } + } + if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */ + { + ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */ + issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */ + ETH_OUTL(dev, 0, DownListPtr); + issue_and_wait(dev, DownUnstall); + } + status = 1; + +Done: + return status; +} + +int eth_3com_send(struct eth_device* dev, volatile void *packet, int length) +{ + int i, status = 0; + int tx_cur; + + if (length <= 0) + { + PRINTF("eth: bad packet size: %d\n", length); + goto Done; + } + + tx_cur = tx_next; + tx_next = (tx_next+1) % NUM_TX_DESC; + + tx_ring[tx_cur].status = cpu_to_le32(1<<31); /* set DnIndicate bit */ + tx_ring[tx_cur].next = 0; + tx_ring[tx_cur].addr = cpu_to_le32(((u32) packet)); + tx_ring[tx_cur].length = cpu_to_le32(length | LAST_FRAG); + + /* Send the packet */ + + issue_and_wait(dev, DownStall); /* stall and set the DownListPtr */ + ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr); + issue_and_wait(dev, DownUnstall); + + for (i=0; !(ETH_STATUS(dev) & DownComplete); i++) + { + if (i >= TOUT_LOOP) + { + PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status)); + goto Done; + } + } + if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */ + { + ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */ + issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */ + ETH_OUTL(dev, 0, DownListPtr); + issue_and_wait(dev, DownUnstall); + } + status=1; + Done: + return status; +} + +void PrintPacket (uchar *packet, int length) +{ +int loop; +uchar *ptr; + + printf ("Printing packet of length %x.\n\n", length); + ptr = packet; + for (loop = 1; loop <= length; loop++) + { + printf ("%2x ", *ptr++); + if ((loop % 40)== 0) + printf ("\n"); + } +} + +int eth_3com_recv(struct eth_device* dev) +{ + u16 stat = 0; + u32 status; + int rx_prev, length = 0; + + while (!(ETH_STATUS(dev) & UpComplete)) /* wait on receipt of packet */ + ; + + status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */ + + while (status & (1<<15)) + { + /* A packet has been received */ + + if (status & (1<<15)) + { + /* A valid frame received */ + + length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */ + + /* Pass the packet up to the protocol layers */ + + NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length); + rx_ring[rx_next].status = 0; /* clear the status word */ + ETH_CMD(dev, AckIntr | UpComplete); + issue_and_wait(dev, UpUnstall); + } + else + if (stat & HostError) + { + /* There was an error */ + + printf("Rx error status: 0x%4x\n", stat); + init_rx_ring(dev); + goto Done; + } + + rx_prev = rx_next; + rx_next = (rx_next + 1) % NUM_RX_DESC; + stat = ETH_STATUS(dev); /* register status */ + status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */ + } + +Done: + return length; +} + +void eth_3com_halt(struct eth_device* dev) +{ + if (!(dev->iobase)) + { + goto Done; + } + + issue_and_wait(dev, DownStall); /* shut down transmit and receive */ + issue_and_wait(dev, UpStall); + issue_and_wait(dev, RxDisable); + issue_and_wait(dev, TxDisable); + +/* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */ +/* free(rx_ring); */ + +Done: + return; +} + +static void init_rx_ring(struct eth_device* dev) +{ + int i; + + PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer); + issue_and_wait(dev, UpStall); + + for (i = 0; i < NUM_RX_DESC; i++) + { + rx_ring[i].next = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC])); + rx_ring[i].status = 0; + rx_ring[i].addr = cpu_to_le32(((u32) &rx_buffer[i][0])); + rx_ring[i].length = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG); + } + rx_next = 0; +} + +static void purge_tx_ring(struct eth_device* dev) +{ + int i; + + PRINTF("Purging tx_ring.\n"); + + tx_next = 0; + + for (i = 0; i < NUM_TX_DESC; i++) + { + tx_ring[i].next = 0; + tx_ring[i].status = 0; + tx_ring[i].addr = 0; + tx_ring[i].length = 0; + } +} + +static void read_hw_addr(struct eth_device* dev, bd_t *bis) +{ + u8 hw_addr[ETH_ALEN]; + unsigned int eeprom[0x40]; + unsigned int checksum = 0; + int i, j, timer; + + /* Read the station address from the EEPROM. */ + + EL3WINDOW(dev, 0); + for (i = 0; i < 0x40; i++) + { + ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd); + /* Pause for at least 162 us. for the read to take place. */ + for (timer = 10; timer >= 0; timer--) + { + udelay(162); + if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0) + break; + } + eeprom[i] = ETH_INW(dev, Wn0EepromData); + } + + /* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */ + + for (i = 0; i < 0x21; i++) + checksum ^= eeprom[i]; + checksum = (checksum ^ (checksum >> 8)) & 0xff; + + if (checksum != 0xbb) + printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum); + + for (i = 0, j = 0; i < 3; i++) + { + hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff); + hw_addr[j++] = (u8)(eeprom[i+10] & 0xff); + } + + /* MAC Address is in window 2, write value from EEPROM to window 2 */ + + EL3WINDOW(dev, 2); + for (i = 0; i < 6; i++) + ETH_OUTB(dev, hw_addr[i], i); + + for (j = 0; j < ETH_ALEN; j+=2) + { + hw_addr[j] = (u8)(ETH_INW(dev, j) & 0xff); + hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff); + } + + for (i=0;ibi_enetaddr[i]) + { +/* printf("Warning: HW address don't match:\n"); */ +/* printf("Address in 3Com Window 2 is " */ +/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ +/* hw_addr[0], hw_addr[1], hw_addr[2], */ +/* hw_addr[3], hw_addr[4], hw_addr[5]); */ +/* printf("Address used by U-Boot is " */ +/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ +/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */ +/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */ +/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */ +/* goto Done; */ + char buffer[256]; + if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 && + bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 && + bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0) + { + + sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X", + hw_addr[0], hw_addr[1], hw_addr[2], + hw_addr[3], hw_addr[4], hw_addr[5]); + setenv("ethaddr", buffer); + } + } + } + + for(i=0; ienetaddr[i] = hw_addr[i]; + +Done: + return; +} diff --git a/board/MAI/AmigaOneG3SE/flash.c b/board/MAI/AmigaOneG3SE/flash.c new file mode 100644 index 0000000..409b955 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/flash.c @@ -0,0 +1,35 @@ +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +unsigned long flash_init(void) +{ + int i; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = 0; + flash_info[i].size = 0; + } + + + return 1; +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + return 1; +} + +void flash_print_info(flash_info_t *info) +{ + printf("No flashrom installed\n"); +} + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + return 0; +} diff --git a/board/MAI/AmigaOneG3SE/flash_new.c b/board/MAI/AmigaOneG3SE/flash_new.c new file mode 100644 index 0000000..d46bf46 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/flash_new.c @@ -0,0 +1,651 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "memio.h" + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static ulong flash_get_size (ulong addr, flash_info_t *info); +static int flash_get_offsets (ulong base, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_reset (ulong addr); + +int flash_xd_nest; + +static void flash_to_xd(void) +{ + unsigned char x; + + flash_xd_nest ++; + + if (flash_xd_nest == 1) + { + DEBUGF("Flash on XD\n"); + x = pci_read_cfg_byte(0, 0, 0x74); + pci_write_cfg_byte(0, 0, 0x74, x|1); + } +} + +static void flash_to_mem(void) +{ + unsigned char x; + + flash_xd_nest --; + + if (flash_xd_nest == 0) + { + DEBUGF("Flash on memory bus\n"); + x = pci_read_cfg_byte(0, 0, 0x74); + pci_write_cfg_byte(0, 0, 0x74, x&0xFE); + } +} + +unsigned long flash_init_old(void) +{ + int i; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = 0; + flash_info[i].size = 0; + } + + + return 1; +} + +unsigned long flash_init (void) +{ + unsigned int i; + unsigned long flash_size = 0; + + flash_xd_nest = 0; + + flash_to_xd(); + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE && \ + CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + } else { + puts ("Warning: the BOOT Flash is not initialised !"); + } + + flash_to_mem(); + + return flash_size; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (ulong addr, flash_info_t *info) +{ + short i; + uchar value; + uchar *x = (uchar *)addr; + + flash_to_xd(); + + /* Write auto select command: read Manufacturer ID */ + x[0x0555] = 0xAA; + __asm volatile ("sync\n eieio"); + x[0x02AA] = 0x55; + __asm volatile ("sync\n eieio"); + x[0x0555] = 0x90; + __asm volatile ("sync\n eieio"); + + value = x[0]; + __asm volatile ("sync\n eieio"); + + DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); + + switch (value | (value << 16)) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + + case STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + flash_reset (addr); + return 0; + } + + value = x[1]; + __asm volatile ("sync\n eieio"); + + DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value); + + switch (value) { + case AMD_ID_F040B: + DEBUGF("Am29F040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + + case AMD_ID_LV040B: + DEBUGF("Am29LV040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + + case AMD_ID_LV400T: + DEBUGF("Am29LV400T\n"); + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + DEBUGF("Am29LV400B\n"); + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + DEBUGF("Am29LV800T\n"); + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + DEBUGF("Am29LV400B\n"); + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + DEBUGF("Am29LV160T\n"); + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + DEBUGF("Am29LV160B\n"); + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV320T: + DEBUGF("Am29LV320T\n"); + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + +#if 0 + /* Has the same ID as AMD_ID_LV320T, to be fixed */ + case AMD_ID_LV320B: + DEBUGF("Am29LV320B\n"); + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + + case AMD_ID_LV033C: + DEBUGF("Am29LV033C\n"); + info->flash_id += FLASH_AM033C; + info->sector_count = 64; + info->size = 0x01000000; + break; /* => 16Mb */ + + case STM_ID_F040B: + DEBUGF("M29F040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + + default: + info->flash_id = FLASH_UNKNOWN; + flash_reset (addr); + flash_to_mem(); + return (0); /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + if (! flash_get_offsets (addr, info)) { + flash_reset (addr); + flash_to_mem(); + return 0; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + value = in8(info->start[i] + 2); + iobarrier_rw(); + info->protect[i] = (value & 1) != 0; + } + + /* + * Reset bank to read mode + */ + flash_reset (addr); + + flash_to_mem(); + + return (info->size); +} + +static int flash_get_offsets (ulong base, flash_info_t *info) +{ + unsigned int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + /* set sector offsets for uniform sector type */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + i * info->size / + info->sector_count; + } + break; + default: + return 0; + } + + return 1; +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile ulong addr = info->start[0]; + int flag, prot, sect, l_sect; + ulong start, now, last; + + flash_to_xd(); + + if (s_first < 0 || s_first > s_last) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + flash_to_mem(); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + flash_to_mem(); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + out8(addr + 0x555, 0x80); + iobarrier_rw(); + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = info->start[sect]; + out8(addr, 0x30); + iobarrier_rw(); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = info->start[l_sect]; + + DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT); + + while ((in8(addr) & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + flash_reset (info->start[0]); + flash_to_mem(); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + iobarrier_rw(); + } + +DONE: + /* reset to read mode */ + flash_reset (info->start[0]); + flash_to_mem(); + + printf (" done\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + flash_to_xd(); + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + flash_to_mem(); + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + flash_to_mem(); + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + flash_to_mem(); + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + + flash_to_mem(); + return (write_word(info, wp, data)); +} + +/* + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile ulong addr = info->start[0]; + ulong start; + int i; + + flash_to_xd(); + + /* Check if Flash is (sufficiently) erased */ + if ((in32(dest) & data) != data) { + flash_to_mem(); + return (2); + } + + /* write each byte out */ + for (i = 0; i < 4; i++) { + char *data_ch = (char *)&data; + int flag = disable_interrupts(); + + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + out8(addr + 0x555, 0xA0); + iobarrier_rw(); + out8(dest+i, data_ch[i]); + iobarrier_rw(); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flash_reset (addr); + flash_to_mem(); + return (1); + } + iobarrier_rw(); + } + } + + flash_reset (addr); + flash_to_mem(); + return (0); +} + +/* + * Reset bank to read mode + */ +static void flash_reset (ulong addr) +{ + flash_to_xd(); + out8(addr, 0xF0); /* reset bank */ + iobarrier_rw(); + flash_to_mem(); +} + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_STM: printf ("SGS THOMSON "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size % 0x100000 == 0) { + printf (" Size: %ld MB in %d Sectors\n", + info->size / 0x100000, info->sector_count); + } else if (info->size % 0x400 == 0) { + printf (" Size: %ld KB in %d Sectors\n", + info->size / 0x400, info->sector_count); + } else { + printf (" Size: %ld B in %d Sectors\n", + info->size, info->sector_count); + } + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} diff --git a/board/MAI/AmigaOneG3SE/i8259.c b/board/MAI/AmigaOneG3SE/i8259.c new file mode 100644 index 0000000..34f489f --- /dev/null +++ b/board/MAI/AmigaOneG3SE/i8259.c @@ -0,0 +1,230 @@ +/* + * (C) Copyright 2002 + * John W. Linville, linville@tuxdriver.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "i8259.h" + +#undef IRQ_DEBUG + +#ifdef IRQ_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +static inline unsigned char read_byte(volatile unsigned char* from) +{ + int x; + asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (unsigned char)x; +} + +static inline void write_byte(volatile unsigned char *to, int x) +{ + asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static inline unsigned long read_long_little(volatile unsigned long *from) +{ + unsigned long x; + asm volatile ("lwbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m"(*from)); + return (unsigned long)x; +} + +#ifdef out8 +#undef out8 +#endif + +#ifdef in8 +#undef in8 +#endif + +#define out8(addr, byte) write_byte(0xFE000000 | addr, byte) +#define in8(addr) read_byte(0xFE000000 | addr) + +/* + * This contains the irq mask for both 8259A irq controllers, + */ +static char cached_imr[2] = {0xff, 0xff}; + +#define cached_imr1 (cached_imr[0]) +#define cached_imr2 (cached_imr[1]) + +void i8259_init(void) +{ + char dummy; + PRINTF("Initializing Interrupt controller\n"); + /* init master interrupt controller */ + out8(0x20, 0x11); /* 0x19); /###* Start init sequence */ + out8(0x21, 0x00); /* Vector base */ + out8(0x21, 0x04); /* edge tiggered, Cascade (slave) on IRQ2 */ + out8(0x21, 0x11); /* was: 0x01); /###* Select 8086 mode */ + + /* init slave interrupt controller */ + out8(0xA0, 0x11); /* 0x19); /###* Start init sequence */ + out8(0xA1, 0x08); /* Vector base */ + out8(0xA1, 0x02); /* edge triggered, Cascade (slave) on IRQ2 */ + out8(0xA1, 0x11); /* was: 0x01); /###* Select 8086 mode */ + + /* always read ISR */ + out8(0x20, 0x0B); + dummy = in8(ISR_1); + out8(0xA0, 0x0B); + dummy = in8(ISR_2); + +/* out8(0x43, 0x30); */ +/* out8(0x40, 0); */ +/* out8(0x40, 0); */ +/* out8(0x43, 0x70); */ +/* out8(0x41, 0); */ +/* out8(0x41, 0); */ +/* out8(0x43, 0xb0); */ +/* out8(0x42, 0); */ +/* out8(0x42, 0); */ + + /* Mask all interrupts */ + out8(IMR_2, cached_imr2); + out8(IMR_1, cached_imr1); + + i8259_unmask_irq(2); +#if 0 + { + int i; + for (i=0; i<16; i++) + { + i8259_unmask_irq(i); + } + } +#endif +} + +static volatile char *pci_intack = (void *)0xFEF00000; + +int i8259_irq(void) +{ + int irq; + + irq = read_long_little(pci_intack) & 0xff; + if (irq==7) { + /* + * This may be a spurious interrupt. + * + * Read the interrupt status register (ISR). If the most + * significant bit is not set then there is no valid + * interrupt. + */ + if(~in8(0x20)&0x80) { + irq = -1; + } + } + + return irq; +} +int i8259_get_irq(struct pt_regs *regs) +{ + unsigned char irq; + + /* + * Perform an interrupt acknowledge cycle on controller 1 + */ + out8(OCW3_1, 0x0C); /* prepare for poll */ + irq = in8(IPL_1) & 7; + if (irq == 2) { + /* + * Interrupt is cascaded so perform interrupt + * acknowledge on controller 2 + */ + out8(OCW3_2, 0x0C); /* prepare for poll */ + irq = (in8(IPL_2) & 7) + 8; + if (irq == 15) { + /* + * This may be a spurious interrupt + * + * Read the interrupt status register. If the most + * significant bit is not set then there is no valid + * interrupt + */ + out8(OCW3_2, 0x0b); + if (~(in8(ISR_2) & 0x80)) { + return -1; + } + } + } else if (irq == 7) { + /* + * This may be a spurious interrupt + * + * Read the interrupt status register. If the most + * significant bit is not set then there is no valid + * interrupt + */ + out8(OCW3_1, 0x0b); + if (~(in8(ISR_1) & 0x80)) { + return -1; + } + } + return irq; +} + +/* + * Careful! The 8259A is a fragile beast, it pretty + * much _has_ to be done exactly like this (mask it + * first, _then_ send the EOI, and the order of EOI + * to the two 8259s is important! + */ +void i8259_mask_and_ack(int irq) +{ + if (irq > 7) { + cached_imr2 |= (1 << (irq - 8)); + in8(IMR_2); /* DUMMY */ + out8(IMR_2, cached_imr2); + out8(OCW2_2, 0x20); /* Non-specific EOI */ + out8(OCW2_1, 0x20); /* Non-specific EOI to cascade */ + } else { + cached_imr1 |= (1 << irq); + in8(IMR_1); /* DUMMY */ + out8(IMR_1, cached_imr1); + out8(OCW2_1, 0x20); /* Non-specific EOI */ + } +} + +void i8259_mask_irq(int irq) +{ + if (irq & 8) { + cached_imr2 |= (1 << (irq & 7)); + out8(IMR_2, cached_imr2); + } else { + cached_imr1 |= (1 << irq); + out8(IMR_1, cached_imr1); + } +} + +void i8259_unmask_irq(int irq) +{ + if (irq & 8) { + cached_imr2 &= ~(1 << (irq & 7)); + out8(IMR_2, cached_imr2); + } else { + cached_imr1 &= ~(1 << irq); + out8(IMR_1, cached_imr1); + } +} diff --git a/board/MAI/AmigaOneG3SE/i8259.h b/board/MAI/AmigaOneG3SE/i8259.h new file mode 100644 index 0000000..05c4052 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/i8259.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * John W. Linville, linville@tuxdriver.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define ICW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1 +#define ICW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1 +#define ICW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2 +#define ICW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2 +#define ICW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3 +#define ICW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3 +#define ICW4_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4 +#define ICW4_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4 +#define OCW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1 +#define OCW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1 +#define OCW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2 +#define OCW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2 +#define OCW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3 +#define OCW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3 + +#define IMR_1 OCW1_1 +#define IMR_2 OCW1_2 + +#define ISR_1 ICW1_1 +#define ISR_2 ICW1_2 + +#define IPL_1 ICW1_1 +#define IPL_2 ICW1_2 + +extern void i8259_init(void); + +extern int i8259_get_irq(struct pt_regs *regs); + +extern void i8259_mask_and_ack(int irq); + +extern void i8259_mask_irq(int irq); + +extern void i8259_unmask_irq(int irq); diff --git a/board/MAI/AmigaOneG3SE/interrupts.c b/board/MAI/AmigaOneG3SE/interrupts.c new file mode 100644 index 0000000..5b314a8 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/interrupts.c @@ -0,0 +1,266 @@ +/* + * (C) Copyright 2002 + * John W. Linville + * + * Copied and modified from original code by Josh Huber. Original + * copyright notice preserved below. + * + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * interrupts.c - just enough support for the decrementer/timer + */ + +#include +#include +#include +#include "i8259.h" + +#undef DEBUG +#ifdef DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif +#define NR_IRQS 16 + +void irq_alloc_init(void); +long irq_alloc(long wanted); + +/****************************************************************************/ + +unsigned decrementer_count; /* count value for 1e6/HZ microseconds */ + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + ulong count; +}; + +static struct irq_action irq_handlers[NR_IRQS]; + +/****************************************************************************/ + +static __inline__ unsigned long +get_msr(void) +{ + unsigned long msr; + + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void +set_msr(unsigned long msr) +{ + asm volatile("mtmsr %0" : : "r" (msr)); +} + +static __inline__ unsigned long +get_dec(void) +{ + unsigned long val; + + asm volatile("mfdec %0" : "=r" (val) :); + return val; +} + + +static __inline__ void +set_dec(unsigned long val) +{ + asm volatile("mtdec %0" : : "r" (val)); +} + + +void +enable_interrupts(void) +{ + set_msr (get_msr() | MSR_EE); +} + +/* returns flag if MSR_EE was set before */ +int +disable_interrupts(void) +{ + ulong msr; + + msr = get_msr(); + set_msr (msr & ~MSR_EE); + return ((msr & MSR_EE) != 0); +} + +/****************************************************************************/ + +int interrupt_init (void) +{ + extern void new_reset(void); + extern void new_reset_end(void); +#ifdef DEBUG + puts("interrupt_init: setting decrementer_count\n"); +#endif + decrementer_count = get_tbclk() / CFG_HZ; + +#ifdef DEBUG + puts("interrupt_init: setting actual decremter\n"); +#endif + set_dec (get_tbclk() / CFG_HZ); + +#ifdef DEBUG + puts("interrupt_init: clearing external interrupt table\n"); +#endif + /* clear external interrupt table here */ + memset(irq_handlers, 0, sizeof(irq_handlers)); + +#ifdef DEBUG + puts("interrupt_init: initializing interrupt controller\n"); +#endif + i8259_init(); + +#ifdef DEBUG + puts("Copying reset trampoline\n"); +#endif + /* WARNING: Assmues that the first megabyte is CACHEINHIBIT! */ + memcpy((void *)0x100, new_reset, new_reset_end - new_reset); + +#ifdef DEBUG + PRINTF("interrupt_init: enabling interrupts (msr = %08x)\n", + get_msr()); +#endif + set_msr (get_msr() | MSR_EE); + +#ifdef DEBUG + PRINTF("interrupt_init: done. (msr = %08x)\n", get_msr()); +#endif + +} + +/****************************************************************************/ + +/* + * Handle external interrupts + */ +void +external_interrupt(struct pt_regs *regs) +{ + extern int i8259_irq(void); + + int irq, unmask = 1; + + irq = i8259_irq(); /*i8259_get_irq(regs); */ +/* printf("irq = %d, handler at %p ack=%d\n", irq, irq_handlers[irq].handler, *(volatile unsigned char *)0xFEF00000); */ + i8259_mask_and_ack(irq); + + if (irq_handlers[irq].handler != NULL) + (*irq_handlers[irq].handler)(irq_handlers[irq].arg); + else { + PRINTF ("\nBogus External Interrupt IRQ %d\n", irq); + /* + * turn off the bogus interrupt, otherwise it + * might repeat forever + */ + unmask = 0; + } + + if (unmask) i8259_unmask_irq(irq); +} + +volatile ulong timestamp = 0; + +/* + * timer_interrupt - gets called when the decrementer overflows, + * with interrupts disabled. + * Trivial implementation - no need to be really accurate. + */ +void +timer_interrupt(struct pt_regs *regs) +{ + set_dec(decrementer_count); + timestamp++; +} + +/****************************************************************************/ + +void +reset_timer(void) +{ + timestamp = 0; +} + +ulong +get_timer(ulong base) +{ + return (timestamp - base); +} + +void +set_timer(ulong t) +{ + timestamp = t; +} + +/****************************************************************************/ + +/* + * Install and free a interrupt handler. + */ + +void +irq_install_handler(int irq, interrupt_handler_t *handler, void *arg) +{ + if (irq < 0 || irq >= NR_IRQS) { + PRINTF("irq_install_handler: bad irq number %d\n", irq); + return; + } + + if (irq_handlers[irq].handler != NULL) + PRINTF("irq_install_handler: 0x%08lx replacing 0x%08lx\n", + (ulong)handler, (ulong)irq_handlers[irq].handler); + + irq_handlers[irq].handler = handler; + irq_handlers[irq].arg = arg; + + i8259_unmask_irq(irq); +} + +void +irq_free_handler(int irq) +{ + if (irq < 0 || irq >= NR_IRQS) { + PRINTF("irq_free_handler: bad irq number %d\n", irq); + return; + } + + i8259_mask_irq(irq); + + irq_handlers[irq].handler = NULL; + irq_handlers[irq].arg = NULL; +} + +/****************************************************************************/ + +void +do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + puts("IRQ related functions are unimplemented currently.\n"); +} diff --git a/board/MAI/AmigaOneG3SE/macros.h b/board/MAI/AmigaOneG3SE/macros.h new file mode 100644 index 0000000..6020d7e --- /dev/null +++ b/board/MAI/AmigaOneG3SE/macros.h @@ -0,0 +1,84 @@ + +#ifndef _MACROS_H +#define _MACROS_H + + /* + ** Load a long integer into a register + */ + .macro liw reg, value + lis \reg, \value@h + ori \reg, \reg, \value@l + .endm + + + /* + ** Generate config_addr request + ** This macro expects the values in registers: + ** r3 - bus + ** r4 - devfn + ** r5 - offset + */ + .macro config_addr + rlwinm r9, r5, 24, 0, 6 + rlwinm r8, r4, 16, 0, 31 + rlwinm r7, r3, 8, 0, 31 + or r9, r8, r9 + or r9, r7, r9 + ori r9, r9, 0x80 + liw r10, 0xfec00cf8 + stw r9, 0(r10) + eieio + sync + .endm + + + /* + ** Generate config_data address + */ + .macro config_data mask + andi. r9, r5, \mask + addi r9, r9, 0xcfc + oris r9, r9, 0xfee0 + .endm + + + /* + ** Write a byte value to an output port + */ + .macro outb port, value + lis r2, 0xfe00 + li r0, \value + stb r0, \port(r2) + .endm + + + /* + ** Write a register byte value to an output port + */ + .macro outbr port, value + lis r2, 0xfe00 + stb \value, \port(r2) + .endm + + + /* + ** Read a byte value from a port into a specified register + */ + .macro inb reg, port + lis r2, 0xfe00 + lbz \reg, \port(r2) + .endm + + + /* + ** Write a byte to the SuperIO config area + */ + .macro siowb offset, value + li r3, 0 + li r4, (7<<3) + li r5, \offset + li r6, \value + bl pci_write_cfg_byte + .endm + +#endif diff --git a/board/MAI/AmigaOneG3SE/memio.S b/board/MAI/AmigaOneG3SE/memio.S new file mode 100644 index 0000000..980d343 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/memio.S @@ -0,0 +1,67 @@ +#include "macros.h" + + + .globl pci_read_cfg_byte + +pci_read_cfg_byte: + config_addr + config_data 3 + eieio + sync + lbz r3, 0(r9) + blr + + + .globl pci_write_cfg_byte + +pci_write_cfg_byte: + config_addr + config_data 3 + stb r6, 0(r9) + eieio + sync + blr + + + .globl pci_read_cfg_word + +pci_read_cfg_word: + config_addr + config_data 2 + lhbrx r3, 0, r9 + eieio + sync + blr + + + .globl pci_write_cfg_word + +pci_write_cfg_word: + config_addr + config_data 2 + sthbrx r6, 0, r9 + eieio + sync + blr + + + .globl pci_read_cfg_long + +pci_read_cfg_long: + config_addr + config_data 0 + lwbrx r3, 0, r9 + eieio + sync + blr + + + .globl pci_write_cfg_long + +pci_write_cfg_long: + config_addr + config_data 0 + stwbrx r6, 0, r9 + eieio + sync + blr diff --git a/board/MAI/AmigaOneG3SE/memio.h b/board/MAI/AmigaOneG3SE/memio.h new file mode 100644 index 0000000..f5ce303 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/memio.h @@ -0,0 +1,113 @@ +/* + * Memory mapped IO + * + * (C) Copyright 2002 + * Hyperion Entertainment, ThomasF@hyperion-entertainment.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * You may also use this under a BSD license. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef _MEMIO_H +#define _MEMIO_H + +#include "short_types.h" + +#define IOBASE 0xFE000000 + +#define in_byte(from) read_byte( (uint8 *)(IOBASE | (from))) +#define in_word(from) read_word_little((uint16 *)(IOBASE | (from))) +#define in_long(from) read_long_little((uint32 *)(IOBASE | (from))) +#define out_byte(to, val) write_byte((uint8 *)(IOBASE | (to)), val) +#define out_word(to, val) write_word_little((uint16 *)(IOBASE | (to)), val) +#define out_long(to, val) write_long_little((uint32 *)(IOBASE | (to)), val) + + +static inline uint8 read_byte(volatile uint8 *from) +{ + int x; + asm volatile ("lbz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from)); + return (uint8)x; +} + + +static inline void write_byte(volatile uint8 *to, uint8 x) +{ + asm volatile ("stb %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x)); +} + +static inline uint16 read_word_little(volatile uint16 *from) +{ + int x; + asm volatile ("lhbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m" (*from)); + return (uint16)x; +} + +static inline uint16 read_word_big(volatile uint16 *from) +{ + int x; + asm volatile ("lhz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from)); + return (uint16)x; +} + +static inline void write_word_little(volatile uint16 *to, int x) +{ + asm volatile ("sthbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_word_big(volatile uint16 *to, int x) +{ + asm volatile ("sth %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x)); +} + +static inline uint32 read_long_little(volatile uint32 *from) +{ + unsigned long x; + asm volatile ("lwbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m"(*from)); + return (uint32)x; +} + +static inline uint32 read_long_big(volatile uint32 *from) +{ + unsigned long x; + asm volatile ("lwz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from)); + return (uint32)x; +} + +static inline void write_long_little(volatile uint32 *to, uint32 x) +{ + asm volatile ("stwbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_long_big(volatile uint32 *to, uint32 x) +{ + asm volatile ("stw %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x)); +} + +#define CONFIG_ADDR(bus, devfn, offset) \ + write_long_big((uint32 *)0xFEC00CF8, \ + ((offset & 0xFC)<<24) | (devfn << 16) \ + | (bus<<8) | 0x80); +#define CONFIG_DATA(offset,mask) ((void *)(0xFEE00CFC+(offset & mask))) + + +uint8 pci_read_cfg_byte(int32 bus, int32 devfn, int32 offset); +void pci_write_cfg_byte(int32 bus, int32 devfn, int32 offset, uint8 x); +uint16 pci_read_cfg_word(int32 bus, int32 devfn, int32 offset); +void pci_write_cfg_word(int32 bus, int32 devfn, int32 offset, uint16 x); +uint32 pci_read_cfg_long(int32 bus, int32 devfn, int32 offset); +void pci_write_cfg_long(int32 bus, int32 devfn, int32 offset, uint32 x); + + +#endif diff --git a/board/MAI/AmigaOneG3SE/memory_dump b/board/MAI/AmigaOneG3SE/memory_dump new file mode 100644 index 0000000..65e7936 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/memory_dump @@ -0,0 +1,30 @@ +64 MB: +0x00: 80 08 04 0c 09 01 40 00 01 a0 60 00 80 08 00 01 +0x10: 8f 04 04 01 01 00 06 a0 60 00 00 14 10 14 2d 10 +0x20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00 +0x30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 f2 +0x40: 7f 61 00 00 00 00 00 00 46 04 00 ff ff ff ff ff +0x50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff +0x60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff +0x70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff 64 f4 + +512 MB: +0x00: 80 08 04 0d 0a 02 40 00 01 75 54 00 82 08 00 01 +0x10: 8f 04 04 01 01 00 0f 00 00 00 00 14 0f 14 2d 40 +0x20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 +0x30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 d2 +0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 fd + +256 MB: +0x00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 +0x10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2d 20 +0x20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 +0x30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 b0 +0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 f6 + diff --git a/board/MAI/AmigaOneG3SE/nvram.c b/board/MAI/AmigaOneG3SE/nvram.c new file mode 100644 index 0000000..d37eec1 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/nvram.c @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2002 + * Thomas Frieden, Hyperion Entertainment + * ThomasF@hyperion-entertainment.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "memio.h" + +void enable_nvram(void) +{ + pci_write_cfg_byte(0, 0, 0x56, 0x0b); +} + +void disable_nvram(void) +{ + pci_write_cfg_byte(0, 0, 0x56, 0x0); +} diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.c b/board/MAI/AmigaOneG3SE/ps2kbd.c new file mode 100644 index 0000000..cf4f4d0 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/ps2kbd.c @@ -0,0 +1,690 @@ +/* + * (C) Copyright 2002 + * John W. Linville, linville@tuxdriver.com + * + * Modified from code for support of MIP405 and PIP405 boards. Previous + * copyright follows. + * + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * Source partly derived from: + * linux/drivers/char/pc_keyb.c + * + * + */ +#include +#include +#include +#include "ps2kbd.h" + + +unsigned char kbd_read_status(void); +unsigned char kbd_read_input(void); +void kbd_send_data(unsigned char data); +void i8259_mask_irq(unsigned int irq); +void i8259_unmask_irq(unsigned int irq); + +/* used only by send_data - set by keyboard_interrupt */ + + +#undef KBG_DEBUG + +#ifdef KBG_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#define KBD_STAT_KOBF 0x01 +#define KBD_STAT_IBF 0x02 +#define KBD_STAT_SYS 0x04 +#define KBD_STAT_CD 0x08 +#define KBD_STAT_LOCK 0x10 +#define KBD_STAT_MOBF 0x20 +#define KBD_STAT_TI_OUT 0x40 +#define KBD_STAT_PARERR 0x80 + +#define KBD_INIT_TIMEOUT 2000 /* Timeout in ms for initializing the keyboard */ +#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */ +#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */ +/* + * Keyboard Controller Commands + */ + +#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ +#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ +#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ +#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ +#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ +#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ +#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ +#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ +#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ +#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ +#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if + initiated by the auxiliary device */ +#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ + +/* + * Keyboard Commands + */ + +#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ +#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ +#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ +#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ +#define KBD_CMD_RESET 0xFF /* Reset */ + +/* + * Keyboard Replies + */ + +#define KBD_REPLY_POR 0xAA /* Power on reset */ +#define KBD_REPLY_ACK 0xFA /* Command ACK */ +#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ + +/* + * Status Register Bits + */ + +#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ +#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ +#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ +#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ +#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ +#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ +#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ +#define KBD_STAT_PERR 0x80 /* Parity error */ + +#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF) + +/* + * Controller Mode Register Bits + */ + +#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ +#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ +#define KBD_MODE_SYS 0x04 /* The system flag (?) */ +#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ +#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ +#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ +#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ +#define KBD_MODE_RFU 0x80 + + +#define KDB_DATA_PORT 0x60 +#define KDB_COMMAND_PORT 0x64 + +#define LED_SCR 0x01 /* scroll lock led */ +#define LED_CAP 0x04 /* caps lock led */ +#define LED_NUM 0x02 /* num lock led */ + +#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ + + +static volatile char kbd_buffer[KBD_BUFFER_LEN]; +static volatile int in_pointer = 0; +static volatile int out_pointer = 0; + + +static unsigned char num_lock = 0; +static unsigned char caps_lock = 0; +static unsigned char scroll_lock = 0; +static unsigned char shift = 0; +static unsigned char ctrl = 0; +static unsigned char alt = 0; +static unsigned char e0 = 0; +static unsigned char leds = 0; + +#define DEVNAME "ps2kbd" + +/* Simple translation table for the keys */ + +static unsigned char kbd_plain_xlate[] = { + 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ + 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +static unsigned char kbd_shift_xlate[] = { + 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */ + 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +static unsigned char kbd_ctrl_xlate[] = { + 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */ + 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */ + 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */ + 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +/****************************************************************** + * Init + ******************************************************************/ + +int isa_kbd_init(void) +{ + char* result; + result=kbd_initialize(); + if (result != NULL) + { + result = kbd_initialize(); + } + if(result==NULL) { + printf("AT Keyboard initialized\n"); + irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL); + return (1); + } + else { + printf("%s\n",result); + return (-1); + } +} + +#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console (void); +#else +int overwrite_console (void) +{ + return (0); +} +#endif + +int drv_isa_kbd_init (void) +{ + int error; + device_t kbddev ; + char *stdinname = getenv ("stdin"); + + if(isa_kbd_init()==-1) + return -1; + memset (&kbddev, 0, sizeof(kbddev)); + strcpy(kbddev.name, DEVNAME); + kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbddev.putc = NULL ; + kbddev.puts = NULL ; + kbddev.getc = kbd_getc ; + kbddev.tstc = kbd_testc ; + + error = device_register (&kbddev); + if(error==0) { + /* check if this is the standard input device */ + if(strcmp(stdinname,DEVNAME)==0) { + /* reassign the console */ + if(overwrite_console()) { + return 1; + } + error=console_assign(stdin,DEVNAME); + if(error==0) + return 1; + else + return error; + } + return 1; + } + return error; +} + +/****************************************************************** + * Queue handling + ******************************************************************/ +/* puts character in the queue and sets up the in and out pointer */ +void kbd_put_queue(char data) +{ + if((in_pointer+1)==KBD_BUFFER_LEN) { + if(out_pointer==0) { + return; /* buffer full */ + } else{ + in_pointer=0; + } + } else { + if((in_pointer+1)==out_pointer) + return; /* buffer full */ + in_pointer++; + } + kbd_buffer[in_pointer]=data; + return; +} + +/* test if a character is in the queue */ +int kbd_testc(void) +{ + if(in_pointer==out_pointer) + return(0); /* no data */ + else + return(1); +} +/* gets the character from the queue */ +int kbd_getc(void) +{ + char c; + + while(in_pointer==out_pointer); + if((out_pointer+1)==KBD_BUFFER_LEN) + out_pointer=0; + else + out_pointer++; + c=kbd_buffer[out_pointer]; + return (int)c; + +} + + +/* set LEDs */ + +void kbd_set_leds(void) +{ + if(caps_lock==0) + leds&=~LED_CAP; /* switch caps_lock off */ + else + leds|=LED_CAP; /* switch on LED */ + if(num_lock==0) + leds&=~LED_NUM; /* switch LED off */ + else + leds|=LED_NUM; /* switch on LED */ + if(scroll_lock==0) + leds&=~LED_SCR; /* switch LED off */ + else + leds|=LED_SCR; /* switch on LED */ + kbd_send_data(KBD_CMD_SET_LEDS); + kbd_send_data(leds); +} + + +void handle_keyboard_event(unsigned char scancode) +{ + unsigned char keycode; + + /* Convert scancode to keycode */ + PRINTF("scancode %x\n",scancode); + if(scancode==0xe0) { + e0=1; /* special charakters */ + return; + } + if(e0==1) { + e0=0; /* delete flag */ + if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */ + ((scancode&0x7F)==0x1D)|| /* the right alt key */ + ((scancode&0x7F)==0x35)|| /* the right '/' key */ + ((scancode&0x7F)==0x1C)|| /* the right enter key */ + ((scancode)==0x48)|| /* arrow up */ + ((scancode)==0x50)|| /* arrow down */ + ((scancode)==0x4b)|| /* arrow left */ + ((scancode)==0x4d))) /* arrow right */ + /* we swallow unknown e0 codes */ + return; + } + /* special cntrl keys */ + switch(scancode) + { + case 0x48: + kbd_put_queue(27); + kbd_put_queue(91); + kbd_put_queue('A'); + return; + case 0x50: + kbd_put_queue(27); + kbd_put_queue(91); + kbd_put_queue('B'); + return; + case 0x4b: + kbd_put_queue(27); + kbd_put_queue(91); + kbd_put_queue('D'); + return; + case 0x4D: + kbd_put_queue(27); + kbd_put_queue(91); + kbd_put_queue('C'); + return; + case 0x58: /* F12 key */ + if (ctrl == 1) + { + extern int console_changed; + setenv("stdin", DEVNAME); + setenv("stdout", "vga"); + console_changed = 1; + } + return; + case 0x2A: + case 0x36: /* shift pressed */ + shift=1; + return; /* do nothing else */ + case 0xAA: + case 0xB6: /* shift released */ + shift=0; + return; /* do nothing else */ + case 0x38: /* alt pressed */ + alt=1; + return; /* do nothing else */ + case 0xB8: /* alt released */ + alt=0; + return; /* do nothing else */ + case 0x1d: /* ctrl pressed */ + ctrl=1; + return; /* do nothing else */ + case 0x9d: /* ctrl released */ + ctrl=0; + return; /* do nothing else */ + case 0x46: /* scrollock pressed */ + scroll_lock=~scroll_lock; + kbd_set_leds(); + return; /* do nothing else */ + case 0x3A: /* capslock pressed */ + caps_lock=~caps_lock; + kbd_set_leds(); + return; + case 0x45: /* numlock pressed */ + num_lock=~num_lock; + kbd_set_leds(); + return; + case 0xC6: /* scroll lock released */ + case 0xC5: /* num lock released */ + case 0xBA: /* caps lock released */ + return; /* just swallow */ + } + if((scancode&0x80)==0x80) /* key released */ + return; + /* now, decide which table we need */ + if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow it */ + } + /* setup plain code first */ + keycode=kbd_plain_xlate[scancode]; + if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown caps-locked scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_shift_xlate[scancode]; + if(keycode<'A') { /* we only want the alphas capital */ + keycode=kbd_plain_xlate[scancode]; + } + } + if(shift==1) { /* shift overwrites caps_lock */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown shifted scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_shift_xlate[scancode]; + } + if(ctrl==1) { /* ctrl overwrites caps_lock and shift */ + if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown ctrl scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_ctrl_xlate[scancode]; + } + /* check if valid keycode */ + if(keycode==0xff) { + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow unknown codes */ + } + + kbd_put_queue(keycode); + PRINTF("%x\n",keycode); +} + +/* + * This reads the keyboard status port, and does the + * appropriate action. + * + */ +unsigned char handle_kbd_event(void) +{ + unsigned char status = kbd_read_status(); + unsigned int work = 10000; + + while ((--work > 0) && (status & KBD_STAT_OBF)) { + unsigned char scancode; + + scancode = kbd_read_input(); + + /* Error bytes must be ignored to make the + Synaptics touchpads compaq use work */ + /* Ignore error bytes */ + if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) + { + if (status & KBD_STAT_MOUSE_OBF) + ; /* not supported: handle_mouse_event(scancode); */ + else + handle_keyboard_event(scancode); + } + status = kbd_read_status(); + } + if (!work) + PRINTF("pc_keyb: controller jammed (0x%02X).\n", status); + return status; +} + + +/****************************************************************************** + * Lowlevel Part of keyboard section + */ +unsigned char kbd_read_status(void) +{ + return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); +} + +unsigned char kbd_read_input(void) +{ + return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); +} + +void kbd_write_command(unsigned char cmd) +{ + out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); +} + +void kbd_write_output(unsigned char data) +{ + out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); +} + +int kbd_read_data(void) +{ + int val; + unsigned char status; + + val=-1; + status = kbd_read_status(); + if (status & KBD_STAT_OBF) { + val = kbd_read_input(); + if (status & (KBD_STAT_GTO | KBD_STAT_PERR)) + val = -2; + } + return val; +} + +int kbd_wait_for_input(void) +{ + unsigned long timeout; + int val; + + timeout = KBD_TIMEOUT; + val=kbd_read_data(); + while(val < 0) + { + if(timeout--==0) + return -1; + udelay(1000); + val=kbd_read_data(); + } + return val; +} + + +int kb_wait(void) +{ + unsigned long timeout = KBC_TIMEOUT * 10; + + do { + unsigned char status = handle_kbd_event(); + if (!(status & KBD_STAT_IBF)) + return 0; /* ok */ + udelay(1000); + timeout--; + } while (timeout); + return 1; +} + +void kbd_write_command_w(int data) +{ + if(kb_wait()) + PRINTF("timeout in kbd_write_command_w\n"); + kbd_write_command(data); +} + +void kbd_write_output_w(int data) +{ + if(kb_wait()) + PRINTF("timeout in kbd_write_output_w\n"); + kbd_write_output(data); +} + +void kbd_send_data(unsigned char data) +{ + unsigned char status; + i8259_mask_irq(KBD_INTERRUPT); /* disable interrupt */ + kbd_write_output_w(data); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + i8259_unmask_irq(KBD_INTERRUPT); /* enable interrupt */ +} + + +char * kbd_initialize(void) +{ + int status; + + in_pointer = 0; /* delete in Buffer */ + out_pointer = 0; + /* + * Test the keyboard interface. + * This seems to be the only way to get it going. + * If the test is successful a x55 is placed in the input buffer. + */ + kbd_write_command_w(KBD_CCMD_SELF_TEST); + if (kbd_wait_for_input() != 0x55) + return "Kbd: failed self test"; + /* + * Perform a keyboard interface test. This causes the controller + * to test the keyboard clock and data lines. The results of the + * test are placed in the input buffer. + */ + kbd_write_command_w(KBD_CCMD_KBD_TEST); + if (kbd_wait_for_input() != 0x00) + return "Kbd: interface failed self test"; + /* + * Enable the keyboard by allowing the keyboard clock to run. + */ + kbd_write_command_w(KBD_CCMD_KBD_ENABLE); + status = kbd_wait_for_input(); + /* + * Reset keyboard. If the read times out + * then the assumption is that no keyboard is + * plugged into the machine. + * This defaults the keyboard to scan-code set 2. + * + * Set up to try again if the keyboard asks for RESEND. + */ + do { + kbd_write_output_w(KBD_CMD_RESET); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + break; + if (status != KBD_REPLY_RESEND) + { + PRINTF("status: %X\n",status); + return "Kbd: reset failed, no ACK"; + } + } while (1); + if (kbd_wait_for_input() != KBD_REPLY_POR) + return "Kbd: reset failed, no POR"; + + /* + * Set keyboard controller mode. During this, the keyboard should be + * in the disabled state. + * + * Set up to try again if the keyboard asks for RESEND. + */ + do { + kbd_write_output_w(KBD_CMD_DISABLE); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + break; + if (status != KBD_REPLY_RESEND) + return "Kbd: disable keyboard: no ACK"; + } while (1); + + kbd_write_command_w(KBD_CCMD_WRITE_MODE); + kbd_write_output_w(KBD_MODE_KBD_INT + | KBD_MODE_SYS + | KBD_MODE_DISABLE_MOUSE + | KBD_MODE_KCC); + + /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */ + kbd_write_command_w(KBD_CCMD_READ_MODE); + if (!(kbd_wait_for_input() & KBD_MODE_KCC)) { + /* + * If the controller does not support conversion, + * Set the keyboard to scan-code set 1. + */ + kbd_write_output_w(0xF0); + kbd_wait_for_input(); + kbd_write_output_w(0x01); + kbd_wait_for_input(); + } + kbd_write_output_w(KBD_CMD_ENABLE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: enable keyboard: no ACK"; + + /* + * Finally, set the typematic rate to maximum. + */ + kbd_write_output_w(KBD_CMD_SET_RATE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: Set rate: no ACK"; + kbd_write_output_w(0x00); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: Set rate: no ACK"; + return NULL; +} + +void kbd_interrupt(void) +{ + handle_kbd_event(); +} diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.h b/board/MAI/AmigaOneG3SE/ps2kbd.h new file mode 100644 index 0000000..fc5c422 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/ps2kbd.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2002 + * John W. Linville, linville@tuxdriver.com + * + * Modified from code for support of MIP405 and PIP405 boards. Previous + * copyright follows. + * + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _KBD_H_ +#define _KBD_H_ + +extern int kbd_testc(void); +extern int kbd_getc(void); +extern void kbd_interrupt(void); +extern char *kbd_initialize(void); + +unsigned char kbd_is_init(void); +#define KBD_INTERRUPT 1 +#endif diff --git a/board/MAI/AmigaOneG3SE/serial.c b/board/MAI/AmigaOneG3SE/serial.c new file mode 100644 index 0000000..e83fb46 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/serial.c @@ -0,0 +1,247 @@ +#include +#include +#include "short_types.h" +#include "memio.h" +#include "articiaS.h" + +#ifndef CFG_NS16550 +static uint32 ComPort1; + +uint16 SerialEcho = 1; + + +#define RECEIVER_HOLDING 0 +#define TRANSMITTER_HOLDING 0 +#define INTERRUPT_ENABLE 1 +#define INTERRUPT_STATUS 2 +#define FIFO_CONTROL 2 +#define LINE_CONTROL 3 +#define MODEM_CONTROL 4 +#define LINE_STATUS 5 +#define MODEM_STATUS 6 +#define SCRATCH_PAD 7 + +#define DIVISOR_LATCH_LSB 0 +#define DIVISOR_LATCH_MSB 1 +#define PRESCALER_DIVISION 5 + +#define COM_WRITE_BYTE(reg, byte) out_byte((ComPort1+reg), byte) +#define COM_READ_BYTE(reg) in_byte((ComPort1+reg)) + +static int serial_init_done = 0; + +void serial_init (void) +{ +#if 0 + uint32 clock_divisor = 115200 / baudrate; + uint8 cfg; + uint8 a; + uint16 devfn = 7 << 3; + + if (serial_init_done) + return; + + /* Enter configuration mode */ + cfg = pci_read_cfg_byte (0, devfn, 0x85); + pci_write_cfg_byte (0, devfn, 0x85, cfg | 0x02); + + /* Set serial port COM1 as 3F8 */ + out_byte (0x3F0, 0xE7); + out_byte (0x3f1, 0xfe); + + /* Set serial port COM2 as 2F8 */ + out_byte (0x3f0, 0xe8); + out_byte (0x3f1, 0xeb); + + /* Enable */ + out_byte (0x3f0, 0xe2); + a = in_byte (0x3f1); + a |= 0xc; + out_byte (0x3f0, 0xe2); + out_byte (0x3f1, a); + + /* Reset the configuration mode */ + pci_write_cfg_byte (0, devfn, 0x85, cfg); +#endif + + ComPort1 = 0x3F8; + + /* Disable interrupts */ + COM_WRITE_BYTE (INTERRUPT_ENABLE, 0x00); + + /* Set baud rate */ + /* COM_WRITE_BYTE(LINE_CONTROL, 0x83); */ + /* COM_WRITE_BYTE(DIVISOR_LATCH_LSB, (uint8)(clock_divisor & 0xFF)); */ + /* COM_WRITE_BYTE(DIVISOR_LATCH_MSB, (uint8)(clock_divisor >> 8)); */ + /* __asm("eieio"); */ + + /* Set 8-N-1 */ + COM_WRITE_BYTE (LINE_CONTROL, 0x03); + __asm ("eieio"); + + /* Disable FIFO */ + COM_WRITE_BYTE (MODEM_CONTROL, 0x03); + COM_WRITE_BYTE (FIFO_CONTROL, 0x07); + + __asm ("eieio"); + serial_init_done = 1; +} + +extern int console_changed; + +void serial_putc (const char sendme) +{ + if (sendme == '\n') { + while ((in_byte (0x3FD) & 0x40) == 0); + out_byte (0x3f8, 0x0D); + } + + while ((in_byte (0x3FD) & 0x40) == 0); + out_byte (0x3f8, sendme); +} + +int serial_getc (void) +{ +#if 0 + uint8 c; + + for (;;) { + uint8 x = in_byte (0x3FD); + + if (x & 0x01) + break; + + if (x & 0x0C) + out_byte (0x3fd, 0x0c); + } + + c = in_byte (0x3F8); + + return c; +#else + while ((in_byte (0x3FD) & 0x01) == 0) { + if (console_changed != 0) { + printf ("Console changed\n"); + console_changed = 0; + return 0; + } + } + return in_byte (0x3F8); +#endif +} + +int serial_tstc (void) +{ + return (in_byte (0x03FD) & 0x01) != 0; +} + +void serial_debug_putc (int c) +{ + serial_puts ("DBG"); + serial_putc (c); + serial_putc (0x0d); + serial_putc (0x0A); +} + +#else + +const NS16550_t Com0 = (NS16550_t) CFG_NS16550_COM1; +const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2; + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uint32 clock_divisor = 115200 / gd->baudrate; + + NS16550_init (Com0, clock_divisor); + /* NS16550_reinit(Com1, clock_divisor); */ + /* serial_puts("COM1: 3F8h initalized"); */ + + return (0); +} + +#if 0 +void serial_putc (const char c) +{ + NS16550_putc (Com0, c); + if (c == '\n') + NS16550_putc (Com0, 0x0D); +} + +int serial_getc (void) +{ + return (int) NS16550_getc (Com0); +} + +int serial_tstc (void) +{ + return NS16550_tstc (Com0); +} +#else +void serial_putc (const char sendme) +{ + if (sendme == '\n') { + while ((in_byte (0x3FD) & 0x40) == 0); + out_byte (0x3f8, 0x0D); + } + + while ((in_byte (0x3FD) & 0x40) == 0); + out_byte (0x3f8, sendme); +} + + +extern int console_changed; + +int serial_getc (void) +{ +#if 0 + uint8 c; + + for (;;) { + uint8 x = in_byte (0x3FD); + + if (x & 0x01) + break; + + if (x & 0x0C) + out_byte (0x3fd, 0x0c); + } + + c = in_byte (0x3F8); + + return c; +#else + while ((in_byte (0x3FD) & 0x01) == 0) { + if (console_changed != 0) { + console_changed = 0; + return 0; + } + } + + return in_byte (0x3F8); +#endif +} + +int serial_tstc (void) +{ + return (in_byte (0x03FD) & 0x01) != 0; +} +#endif + +#endif + +void serial_puts (const char *string) +{ + while (*string) + serial_putc (*string++); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uint32 clock_divisor = 115200 / gd->baudrate; + + NS16550_init (Com0, clock_divisor); +} diff --git a/board/MAI/AmigaOneG3SE/short_types.h b/board/MAI/AmigaOneG3SE/short_types.h new file mode 100644 index 0000000..1840d28 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/short_types.h @@ -0,0 +1,36 @@ +/* + * short type names + * + * (C) Copyright 2002 + * Hyperion Entertainment, ThomasF@hyperion-entertainment.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SHORT_TYPES_H +#define _SHORT_TYPES_H + +typedef unsigned long uint32; +typedef long int32; +typedef unsigned short uint16; +typedef short int16; +typedef unsigned char uint8; +typedef signed char int8; + +#endif diff --git a/board/MAI/AmigaOneG3SE/smbus.c b/board/MAI/AmigaOneG3SE/smbus.c new file mode 100644 index 0000000..de13977 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/smbus.c @@ -0,0 +1,206 @@ +#include "memio.h" +#include "articiaS.h" + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + + +void sm_write_mode(void) +{ + out_byte(0xA539, 0x00); + out_byte(0xA53A, 0x03); +} + +void sm_read_mode(void) +{ + out_byte(0xA53A, 0x02); + out_byte(0xA539, 0x02); +} + +void sm_write_byte(uint8 writeme) +{ + int i; + int level; + + out_byte(0xA539, 0x00); + + level = 0; + + for (i=0; i<8; i++) + { + if ((writeme & 0x80) == (level<<7)) + { + /* Bit did not change, rewrite strobe */ + out_byte(0xA539, level | 0x02); + out_byte(0xA539, level); + } + else + { + /* Bit changed, set bit, then strobe */ + level = (writeme & 0x80) >> 7; + out_byte(0xA539, level); + out_byte(0xA539, level | 0x02); + out_byte(0xA539, level); + } + writeme <<= 1; + } + out_byte(0xA539, 0x00); +} + +uint8 sm_read_byte(void) +{ + uint8 retme, r; + int i; + + retme = 0; + for (i=0; i<8; i++) + { + retme <<= 1; + out_byte(0xA539, 0x00); + out_byte(0xA539, 0x02); + r = in_byte(0xA538) & 0x01; + retme |= r; + } + + return retme; +} + +int sm_get_ack(void) +{ + uint8 r; + r = in_byte(0xA538); + if ((r&0x01) == 0) return TRUE; + else return FALSE; +} + +void sm_write_ack(void) +{ + out_byte(0xA539, 0x00); + out_byte(0xA539, 0x02); + out_byte(0xA539, 0x00); +} + +void sm_write_nack(void) +{ + out_byte(0xA539, 0x01); + out_byte(0xA539, 0x03); + out_byte(0xA539, 0x01); +} + +void sm_send_start(void) +{ + out_byte(0xA539, 0x03); + out_byte(0xA539, 0x02); +} + +void sm_send_stop(void) +{ + out_byte(0xA539, 0x02); + out_byte(0xA539, 0x03); +} + +int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage) +{ + /* S Addr Wr */ + sm_write_mode(); + sm_send_start(); + sm_write_byte((addr<<1)); + + /* [A] */ + sm_read_mode(); + if (sm_get_ack() == FALSE) return FALSE; + + /* Comm */ + sm_write_mode(); + sm_write_byte(reg); + + /* [A] */ + sm_read_mode(); + if (sm_get_ack() == FALSE) return FALSE; + + /* S Addr Rd */ + sm_write_mode(); + sm_send_start(); + sm_write_byte((addr<<1)|1); + + /* [A] */ + sm_read_mode(); + if (sm_get_ack() == FALSE) return FALSE; + + /* [Data] */ + *storage = sm_read_byte(); + + /* NA */ + sm_write_mode(); + sm_write_nack(); + sm_send_stop(); + + return TRUE; +} + +void sm_init(void) +{ + /* Switch to PMC mode */ + pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER)); + + /* Set GPIO Base */ + pci_write_cfg_long(0, 0, 0x40, 0xa500); + + /* Enable GPIO */ + pci_write_cfg_byte(0, 0, 0x44, 0x11); + + /* Set both GPIO 0 and 1 as output */ + out_byte(0xA53A, 0x03); +} + + +void sm_term(void) +{ + /* Switch to normal mode */ + pci_write_cfg_byte(0, 0, REG_GROUP, 0); +} + + +int sm_get_data(uint8 *DataArray, int dimm_socket) +{ + int j; + +#if 0 + /* Switch to PMC mode */ + pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER)); + + /* Set GPIO Base */ + pci_write_cfg_long(0, 0, 0x40, 0xa500); + + /* Enable GPIO */ + pci_write_cfg_byte(0, 0, 0x44, 0x11); + + /* Set both GPIO 0 and 1 as output */ + out_byte(0xA53A, 0x03); +#endif + + sm_init(); + /* Start reading the rom */ + + j = 0; + + do + { + if (sm_read_byte_from_device(dimm_socket, (uint8)j, DataArray) == FALSE) + { + sm_term(); + return FALSE; + } + + DataArray++; + j++; + } while (j < 128); + + sm_term(); + return TRUE; +} diff --git a/board/MAI/AmigaOneG3SE/smbus.h b/board/MAI/AmigaOneG3SE/smbus.h new file mode 100644 index 0000000..beeb6a0 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/smbus.h @@ -0,0 +1,22 @@ +#ifndef _SMBUS_H_ +#define _SMBUS_H_ + +#include "short_types.h" + +#define SM_DIMM0_ADDR 0x51 +#define SM_DIMM1_ADDR 0x52 + +void sm_write_mode(void); +void sm_read_mode(void); +void sm_write_byte(uint8 writeme); +uint8 sm_read_byte(void); +int sm_get_ack(void); +void sm_write_ack(void); +void sm_write_nack(void); +void sm_send_start(void); +void sm_send_stop(void); +int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage); +int sm_get_data(uint8 *DataArray, int dimm_socket); +void sm_init(void); +void sm_term(void); +#endif diff --git a/board/MAI/AmigaOneG3SE/start.txt b/board/MAI/AmigaOneG3SE/start.txt new file mode 100644 index 0000000..e421462 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/start.txt @@ -0,0 +1,198 @@ + + /*------------------------------------------------------*/ + /* TERON Articia / SDRAM Init */ + /*------------------------------------------------------*/ + +* XD_CTL = 0x81000000 (0x74) + +* HBUS_ACC_CTL_0 &= 0xFFFFFDFF (0x5c) + /* host bus access ctl reg 2(5e) */ + /* set - CPU read from memory data one clock after data is latched */ + +* GLOBL_INFO_0 |= 0x00004000 (0x50) + /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */ + + PCI_1_SB_CONFIG_0 |= 0x00000400 (0x80d0) + /* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */ + + MEM_RAS_CTL_0 |= 0x3f000000 (0xcc) + &= 0x3fffffff + /* RAS park control reg 0(cc), park access enable is set */ + + HOST_RDBUF_CTL |= 0x10000000 (0x70) + &= 0x10ffffff + /* host read buffer control reg, enable prefetch for CPU read from DRAM control */ + + HBUS_ACC_CTL_0 |= 0x0100001f (0x5c) + &= 0xf1ffffff + /* host bus access control register, enable CPU address bus pipe control */ + /* two outstanding requests, *** changed to 2 from 3 */ + /* enable line merge write control for CPU write to system memory, PCI 1 */ + /* and PCI 0 bus memory; enable page merge write control for write to */ + /* PCI bus 0 & bus 1 memory */ + + SRAM_CTL |= 0x00004000 (0xc8) + &= 0xffbff7ff + /* DRAM detail timing control register 1 (ca), bit 3 set to 0 */ + /* DRAM start access latency control - wait for one clock */ + /* ff9f changed to ffbf */ + + DIM0_TIM_CTL_0 = 0x737d737d (0xc9) + /* DRAM timing control for dimm0 & dimm1; set wait one clock */ + /* cycle for next data access */ + + DIM2_TIM_CTL_0 = 0x737d737d (0xca) + /* DRAM timing control for dimm2 & dimm3; set wait one clock */ + /* cycle for next data access */ + + DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90) + /* set dimm0 bank0 for 128 MB */ + + DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB (0x94) + /* set dimm0 for bank1 */ + + DIM0_TIM_CTL_0 = 0xf3bf0000 (0xc9) + /* dimm0 timing control register; RAS - CAS latency - 4 clock */ + /* CAS access latency - 3 wait; pre-charge latency - 3 wait */ + /* pre-charge command period control - 5 clock; wait one clock */ + /* cycle for next data access; read to write access latency control */ + /* - 2 clock cycles */ + + DRAM_GBL_CTL_0 |= 0x00000100 (0xc0) + &= 0xffff01ff + /* memory global control register - support buffer sdram on bank 0 */ + + DRAM_ECC_CTL_0 |= 0x00260000 (0xc4) + &= 0xff26ffff + /* enable ECC; enable read, modify, write control */ + + DRAM_REF_CTL_0 = DRAM_REF_DATA (0xb8) + /* set DRAM refresh parameters *** changed to 00940100 */ + + nop + nop + nop + nop + nop + + DRAM_ECC_CTL_0 |= 0x20243280 (0xc4) + /* turn off ecc */ + /* for SDRAM bank 0 */ + + DRAM_ECC_CTL_0 |= 0x20243290 (0xc4) ? + /* for SDRAM bank 1 */ + + +/* Additional Stuff...*/ + + GLOBL_CTRL |= 0x20000b00 (0x54) + + PCI_0_SB_CONFIG |= 0x04100007 (0xd0) + /* PCI 0 Side band config reg*/ + + 0x8000083c |= 0x00080000 + /* Disable VGA decode on PCI Bus 1 */ + + +/*End Additional Stuff..*/ + + /*--------------------------------------------------------------*/ + /* TERON serial port initialization code */ + /*--------------------------------------------------------------*/ + + 0x84380080 |= 0x00030000 + /* enable super IO configuration VIA chip Register 85 */ + /* Enable super I/O config mode */ + + 0xfe0003f0 = 0xe2 + bl delay1 + + 0xfe0003f1 = 0x0f + bl delay1 + /* enable com1 & com2, parallel port disabled */ + + 0xfe0003f0 = 0xe7 + bl delay1 + /* let's make com1 base as 0x3f8 */ + + 0xfe0003f1 = 0xfe + bl delay1 + + 0xfe0003f0 = 0xe8 + bl delay1 + /* let's make com2 base as 0x2f8 */ + + 0xfe0003f1 = 0xbe + + 0x84380080 &= 0xfffdffff + /* closing super IO configuration VIA chip Register 85 */ + + +/* -------------------------------*/ + + 0xfe0003fb = 0x83 + bl delay1 + /*latch enable word length -8 bit */ /* set mslab bit */ + 0xfe0003f8 = 0x0c + bl delay1 + /* set baud rate lsb for 9600 baud */ + 0xfe0003f9 = 0x0 + bl delay1 + /* set baud rate msb for 9600 baud */ + 0xfe0003fb = 0x03 + bl delay1 + /* reset mslab */ + + /*--------------------------------------------------------------*/ + /* END TERON Serial Port Initialization Code */ + /*--------------------------------------------------------------*/ + + + /*--------------------------------------------------------------*/ + /* END TERON Articia / SDRAM Initialization code */ + /*--------------------------------------------------------------*/ + +Proposed from Documentation: + +write dmem 0xfec00cf8 0x50000080 +write dmem 0xfee00cfc 0xc0305411 + + Writes to index 0x50-0x53. + 0x50: Global Information Register 0 + 0xC0 = Little Endian CPU, Sequential order Burst + 0x51: Global Information Register 1 + Read only, 0x30 = Provides PowerPC and X86 support + 0x52: Global Information Register 2 + 0x05 = 64/128 bit CPU bus support + 0x53: Global Information Register 3 + 0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted + +write dmem 0xfec00cf8 0x5c000080 +write dmem 0xfee00cfc 0xb300011F + +write dmem 0xfec00cf8 0xc8000080 +write dmem 0xfee00cfc 0x0020f100 + +write dmem 0xfec00cf8 0x90000080 +write dmem 0xfee00cfc 0x007fe700 + +write dmem 0xfec00cf8 0x9400080 +write dmem 0xfee00cfc 0x007fe700 + +write dmem 0xfec00cf8 0xb0000080 +write dmem 0xfee00cfc 0x737d737d + +write dmem 0xfec00cf8 0xb4000080 +write dmem 0xfee00cfc 0x737d737d + +write dmem 0xfec00cf8 0xc0000080 +write dmem 0xfee00cfc 0x40005500 + +write dmem 0xfec00cf8 0xb8000080 +write dmem 0xfee00cfc 0x00940100 + +write dmem 0xfec00cf8 0xc4000080 +write dmem 0xfee00cfc 0x00003280 + +write dmem 0xfec00cf8 0xc4000080 +write dmem 0xfee00cfc 0x00003290 diff --git a/board/MAI/AmigaOneG3SE/todo.txt b/board/MAI/AmigaOneG3SE/todo.txt new file mode 100644 index 0000000..df25e3d --- /dev/null +++ b/board/MAI/AmigaOneG3SE/todo.txt @@ -0,0 +1,3 @@ +- Init interrupt controller +- init sdram +- init ide controller \ No newline at end of file diff --git a/board/MAI/AmigaOneG3SE/u-boot.lds b/board/MAI/AmigaOneG3SE/u-boot.lds new file mode 100644 index 0000000..b36b3cb --- /dev/null +++ b/board/MAI/AmigaOneG3SE/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on the AmigaOneG3SE Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = ALIGN(4) /*.*/ ; + PROVIDE (end = ALIGN(4) /*.*/); +} diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.c b/board/MAI/AmigaOneG3SE/usb_uhci.c new file mode 100644 index 0000000..14e8043 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/usb_uhci.c @@ -0,0 +1,1178 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: Part of this code has been derived from linux + * + */ + +/********************************************************************** + * How it works: + * ------------- + * The framelist / Transfer descriptor / Queue Heads are similar like + * in the linux usb_uhci.c. + * + * During initialization, the following skeleton is allocated in init_skel: + * + * framespecific | common chain + * + * framelist[] + * [ 0 ]-----> TD ---------\ + * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL + * ... TD ---------/ + * [1023]-----> TD --------/ + * + * ^^ ^^ ^^ ^^ ^^ + * 7 TDs for 1 TD for Start of Start of End Chain + * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain + * + * + * Since this is a bootloader, the isochronous transfer descriptor have been removed. + * + * Interrupt Transfers. + * -------------------- + * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They + * will be inserted after the appropriate (depending the interval setting) skeleton TD. + * If an interrupt has been detected the dev->irqhandler is called. The status and number + * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the + * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned, + * the interrupt TD will be reactivated. + * + * Control Transfers + * ----------------- + * Control Transfers are issued by filling the tmp_td with the appropriate data and connect + * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued, + * the programm has to wait for completion. This does not allows asynchronous data transfer. + * + * Bulk Transfers + * -------------- + * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect + * them to the qh_bulk queue header. Before other control/bulk transfers can be issued, + * the programm has to wait for completion. This does not allows asynchronous data transfer. + * + * + */ + +#include +#include + +#ifdef CONFIG_USB_UHCI + +#include +#include "usb_uhci.h" + +#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */ +#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */ + + +/*#define USB_UHCI_DEBUG */ + +#ifdef USB_UHCI_DEBUG +#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define USB_UHCI_PRINTF(fmt,args...) +#endif + + +static int irqvec = -1; /* irq vector, if -1 uhci is stopped / reseted */ +unsigned int usb_base_addr; /* base address */ + +static uhci_td_t td_int[8]; /* Interrupt Transfer descriptors */ +static uhci_qh_t qh_cntrl; /* control Queue Head */ +static uhci_qh_t qh_bulk; /* bulk Queue Head */ +static uhci_qh_t qh_end; /* end Queue Head */ +static uhci_td_t td_last; /* last TD (linked with end chain) */ + +/* temporary tds */ +static uhci_td_t tmp_td[USB_MAX_TEMP_TD]; /* temporary bulk/control td's */ +static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD]; /* temporary interrupt td's */ + +static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */ + +static struct virt_root_hub rh; /* struct for root hub */ + +/********************************************************************** + * some forward decleration + */ +int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len,struct devrequest *setup); + +/* fill a td with the approproiate data. Link, status, info and buffer + * are used by the USB controller itselfes, dev is used to identify the + * "connected" device + */ +void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status, + unsigned long info, unsigned long buffer, unsigned long dev) +{ + td->link=swap_32(link); + td->status=swap_32(status); + td->info=swap_32(info); + td->buffer=swap_32(buffer); + td->dev_ptr=dev; +} + +/* fill a qh with the approproiate data. Head and element are used by the USB controller + * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh. + * Please note, that after completion of the td chain, the entry element is removed / + * marked invalid by the USB controller. + */ +void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element) +{ + qh->head=swap_32(head); + qh->element=swap_32(element); + qh->dev_ptr=0L; +} + +/* get the status of a td->status + */ +unsigned long usb_uhci_td_stat(unsigned long status) +{ + unsigned long result=0; + result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0; + result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0; + result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0; + result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0; + result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0; + result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0; + result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0; + return result; +} + +/* get the status and the transfered len of a td chain. + * called from the completion handler + */ +int usb_get_td_status(uhci_td_t *td,struct usb_device *dev) +{ + unsigned long temp,info; + unsigned long stat; + uhci_td_t *mytd=td; + + if(dev->devnum==rh.devnum) + return 0; + dev->act_len=0; + stat=0; + do { + temp=swap_32((unsigned long)mytd->status); + stat=usb_uhci_td_stat(temp); + info=swap_32((unsigned long)mytd->info); + if(((info & 0xff)!= USB_PID_SETUP) && + (((info >> 21) & 0x7ff)!= 0x7ff) && + (temp & 0x7FF)!=0x7ff) + { /* if not setup and not null data pack */ + dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */ + } + if(stat) { /* status no ok */ + dev->status=stat; + return -1; + } + temp=swap_32((unsigned long)mytd->link); + mytd=(uhci_td_t *)(temp & 0xfffffff0); + }while((temp & 0x1)==0); /* process all TDs */ + dev->status=stat; + return 0; /* Ok */ +} + + +/*------------------------------------------------------------------- + * LOW LEVEL STUFF + * assembles QHs und TDs for control, bulk and iso + *-------------------------------------------------------------------*/ + +/* Submits a control message. That is a Setup, Data and Status transfer. + * Routine does not wait for completion. + */ +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len,struct devrequest *setup) +{ + unsigned long destination, status; + int maxsze = usb_maxpacket(dev, pipe); + unsigned long dataptr; + int len; + int pktsze; + int i=0; + + if (!maxsze) { + USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe); + return -1; + } + if(((pipe>>8)&0x7f)==rh.devnum) { + /* this is the root hub -> redirect it */ + return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup); + } + USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze); + /* The "pipe" thing contains the destination in bits 8--18 */ + destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */ + /* 3 errors */ + status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); + /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */ + /* Build the TD for the control request, try forever, 8 bytes of data */ + usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev); +#if 0 + { + char *sp=(char *)setup; + printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe, + sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]); + } +#endif + dataptr = (unsigned long)buffer; + len=transfer_len; + + /* If direction is "send", change the frame from SETUP (0x2D) + to OUT (0xE1). Else change it from SETUP to IN (0x69). */ + destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN); + while (len > 0) { + /* data stage */ + pktsze = len; + i++; + if (pktsze > maxsze) + pktsze = maxsze; + destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */ + usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ + tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); + + dataptr += pktsze; + len -= pktsze; + } + + /* Build the final TD for control status */ + /* It's only IN if the pipe is out AND we aren't expecting data */ + + destination &= ~UHCI_PID; + if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0)) + destination |= USB_PID_IN; + else + destination |= USB_PID_OUT; + destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */ + i++; + status &=~TD_CTRL_SPD; + /* no limit on errors on final packet , 0 bytes of data */ + usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev); + tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); /* queue status td */ + /* usb_show_td(i+1);*/ + USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i); + /* first mark the control QH element terminated */ + qh_cntrl.element=0xffffffffL; + /* set qh active */ + qh_cntrl.dev_ptr=(unsigned long)dev; + /* fill in tmp_td_chain */ + qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]); + return 0; +} + +/*------------------------------------------------------------------- + * Prepare TDs for bulk transfers. + */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len) +{ + unsigned long destination, status,info; + unsigned long dataptr; + int maxsze = usb_maxpacket(dev, pipe); + int len; + int i=0; + + if(transfer_len < 0) { + printf("Negative transfer length in submit_bulk\n"); + return -1; + } + if (!maxsze) + return -1; + /* The "pipe" thing contains the destination in bits 8--18. */ + destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe); + /* 3 errors */ + status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); + /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */ + /* Build the TDs for the bulk request */ + len = transfer_len; + dataptr = (unsigned long)buffer; + do { + int pktsze = len; + if (pktsze > maxsze) + pktsze = maxsze; + /* pktsze bytes of data */ + info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) | + (usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE); + + if((len-pktsze)==0) + status |= TD_CTRL_IOC; /* last one generates INT */ + + usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ + if(i>0) + tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); + i++; + dataptr += pktsze; + len -= pktsze; + usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); + } while (len > 0); + /* first mark the bulk QH element terminated */ + qh_bulk.element=0xffffffffL; + /* set qh active */ + qh_bulk.dev_ptr=(unsigned long)dev; + /* fill in tmp_td_chain */ + qh_bulk.element=swap_32((unsigned long)&tmp_td[0]); + return 0; +} + + +/* search a free interrupt td + */ +uhci_td_t *uhci_alloc_int_td(void) +{ + int i; + for(i=0;i free TD */ + return &tmp_int_td[i]; + } + return NULL; +} + +#if 0 +void uhci_show_temp_int_td(void) +{ + int i; + for(i=0;i free TD */ + printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr); + } + printf("all others temp_tds are free\n"); +} +#endif +/*------------------------------------------------------------------- + * submits USB interrupt (ie. polling ;-) + */ +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval) +{ + int nint, n; + unsigned long status, destination; + unsigned long info,tmp; + uhci_td_t *mytd; + if (interval < 0 || interval >= 256) + return -1; + + if (interval == 0) + nint = 0; + else { + for (nint = 0, n = 1; nint <= 8; nint++, n += n) /* round interval down to 2^n */ + { + if(interval < n) { + interval = n / 2; + break; + } + } + nint--; + } + + USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint); + mytd=uhci_alloc_int_td(); + if(mytd==NULL) { + printf("No free INT TDs found\n"); + return -1; + } + status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27); +/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27); +*/ + + destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21); + + info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE); + tmp = swap_32(td_int[nint].link); + usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev); + /* Link it */ + tmp = swap_32((unsigned long)mytd); + td_int[nint].link=tmp; + + usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); + + return 0; +} + +/********************************************************************** + * Low Level functions + */ + + +void reset_hc(void) +{ + + /* Global reset for 100ms */ + out16r( usb_base_addr + USBPORTSC1,0x0204); + out16r( usb_base_addr + USBPORTSC2,0x0204); + out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS); + /* Turn off all interrupts */ + out16r(usb_base_addr + USBINTR,0); + wait_ms(50); + out16r( usb_base_addr + USBCMD,0); + wait_ms(10); +} + +void start_hc(void) +{ + int timeout = 1000; + + while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) { + if (!--timeout) { + printf("USBCMD_HCRESET timed out!\n"); + break; + } + } + /* Turn on all interrupts */ + out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP); + /* Start at frame 0 */ + out16r(usb_base_addr + USBFRNUM,0); + /* set Framebuffer base address */ + out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist); + /* Run and mark it configured with a 64-byte max packet */ + out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP); +} + +/* Initialize the skeleton + */ +void usb_init_skel(void) +{ + unsigned long temp; + int n; + + for(n=0;nstatus & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ + qh_cntrl.dev_ptr=0; + } + } + /* now process the bulk */ + if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */ + { + dev=(struct usb_device *)qh_bulk.dev_ptr; + usb_get_td_status(&tmp_td[0],dev); /* update status */ + if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ + qh_bulk.dev_ptr=0; + } + } +} + +/* check the interrupt chain, ubdate the status of the appropriate device, + * call the appropriate irqhandler and reactivate the TD if the irqhandler + * returns with 1 + */ +void usb_check_int_chain(void) +{ + int i,res; + unsigned long link,status; + struct usb_device *dev; + uhci_td_t *td,*prevtd; + + for(i=0;i<8;i++) { + prevtd=&td_int[i]; /* the first previous td is the skeleton td */ + link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */ + td=(uhci_td_t *)link; /* assign it */ + /* all interrupt TDs are finally linked to the td_int[0]. + * so we process all until we find the td_int[0]. + * if int0 chain points to a QH, we're also done + */ + while(((i>0) && (link != (unsigned long)&td_int[0])) || + ((i==0) && !(swap_32(td->link) & UHCI_PTR_QH))) + { + /* check if a device is assigned with this td */ + status=swap_32(td->status); + if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) { + /* td is not active and a device is assigned -> call irqhandler */ + dev=(struct usb_device *)td->dev_ptr; + dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */ + dev->irq_status=usb_uhci_td_stat(status); /* get status */ + res=dev->irq_handle(dev); /* call irqhandler */ + if(res==1) { + /* reactivate */ + status|=TD_CTRL_ACTIVE; + td->status=swap_32(status); + prevtd=td; /* previous td = this td */ + } + else { + prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */ + /* remove device pointer */ + td->dev_ptr=0L; + } + } /* if we call the irq handler */ + link=swap_32(td->link) & 0xfffffff0; /* next in chain */ + td=(uhci_td_t *)link; /* assign it */ + } /* process all td in this int chain */ + } /* next interrupt chain */ +} + + +/* usb interrupt service routine. + */ +void handle_usb_interrupt(void) +{ + unsigned short status; + + /* + * Read the interrupt status, and write it back to clear the + * interrupt cause + */ + + status = in16r(usb_base_addr + USBSTS); + + if (!status) /* shared interrupt, not mine */ + return; + if (status != 1) { + /* remove host controller halted state */ + if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) { + out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD)); + } + } + usb_check_int_chain(); /* call interrupt handlers for int tds */ + usb_check_skel(); /* call completion handler for common transfer routines */ + out16r(usb_base_addr+USBSTS,status); +} + + +/* init uhci + */ +int usb_lowlevel_init(void) +{ + unsigned char temp; + int busdevfunc; +/* + * HJF - configure IRQ and base from variables optionally. + */ + char *s; + + + busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */ + if(busdevfunc==-1) { + printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID); + return -1; + } + +#if 1 + s = getenv("usb_irq"); + if (s) + { + temp = atoi(s); + pci_write_config_byte(busdevfunc, PCI_INTERRUPT_LINE, temp); + } + else +#endif + pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp); + + s = getenv("usb_base"); + if (s) + { + unsigned long temp2; + temp2 = atoi(s); + pci_write_config_dword(busdevfunc, PCI_BASE_ADDRESS_4, temp2|0x01); + } + + irqvec = temp; + irq_free_handler(irqvec); + USB_UHCI_PRINTF("Interrupt Line = %d\n",irqvec); + pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp); + USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp); + pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr); + USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr); + usb_base_addr&=0xFFFFFFF0; + usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS; + rh.devnum = 0; + usb_init_skel(); + reset_hc(); + start_hc(); + irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL); + irq_install_handler(0, (interrupt_handler_t *)handle_usb_interrupt, NULL); + + return 0; +} + +/* stop uhci + */ +int usb_lowlevel_stop(void) +{ + if(irqvec==-1) + return 1; + irq_free_handler(irqvec); + irq_free_handler(0); + reset_hc(); + irqvec=-1; + return 0; +} + +/******************************************************************************************* + * Virtual Root Hub + * Since the uhci does not have a real HUB, we simulate one ;-) + */ +#undef USB_RH_DEBUG + +#ifdef USB_RH_DEBUG +#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args) +static void usb_display_wValue(unsigned short wValue,unsigned short wIndex); +static void usb_display_Req(unsigned short req); +#else +#define USB_RH_PRINTF(fmt,args...) +static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {} +static void usb_display_Req(unsigned short req) {} +#endif + +static unsigned char root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x00, /* __u16 bcdUSB; v1.0 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x01, /* __u8 iManufacturer; */ + 0x00, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + + +/* Configuration descriptor */ +static unsigned char root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + + +static unsigned char root_hub_hub_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x29, /* __u8 bDescriptorType; Hub-descriptor */ + 0x02, /* __u8 bNbrPorts; */ + 0x00, /* __u16 wHubCharacteristics; */ + 0x00, + 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ + 0x00, /* __u8 bHubContrCurrent; 0 mA */ + 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ + 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'U', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + + +/* + * Root Hub Control Pipe (interrupt Pipes are not supported) + */ + + +int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd) +{ + void *data = buffer; + int leni = transfer_len; + int len = 0; + int status = 0; + int stat = 0; + int i; + + unsigned short cstatus; + + unsigned short bmRType_bReq; + unsigned short wValue; + unsigned short wIndex; + unsigned short wLength; + + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + printf("Root-Hub submit IRQ: NOT implemented\n"); +#if 0 + uhci->rh.urb = urb; + uhci->rh.send = 1; + uhci->rh.interval = urb->interval; + rh_init_int_timer (urb); +#endif + return 0; + } + bmRType_bReq = cmd->requesttype | cmd->request << 8; + wValue = swap_16(cmd->value); + wIndex = swap_16(cmd->index); + wLength = swap_16(cmd->length); + usb_display_Req(bmRType_bReq); + for (i = 0; i < 8; i++) + rh.c_p_r[i] = 0; + USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n", + dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(unsigned short *) data = swap_16(1); + len=2; + break; + case RH_GET_STATUS | RH_INTERFACE: + *(unsigned short *) data = swap_16(0); + len=2; + break; + case RH_GET_STATUS | RH_ENDPOINT: + *(unsigned short *) data = swap_16(0); + len=2; + break; + case RH_GET_STATUS | RH_CLASS: + *(unsigned long *) data = swap_32(0); + len=4; + break; /* hub power ** */ + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + + status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1)); + cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) | + ((status & USBPORTSC_PEC) >> (3 - 1)) | + (rh.c_p_r[wIndex - 1] << (0 + 4)); + status = (status & USBPORTSC_CCS) | + ((status & USBPORTSC_PE) >> (2 - 1)) | + ((status & USBPORTSC_SUSP) >> (12 - 2)) | + ((status & USBPORTSC_PR) >> (9 - 4)) | + (1 << 8) | /* power on ** */ + ((status & USBPORTSC_LSDA) << (-8 + 9)); + + *(unsigned short *) data = swap_16(status); + *(unsigned short *) (data + 2) = swap_16(cstatus); + len=4; + break; + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): + len=0; + break; + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case (RH_C_HUB_OVER_CURRENT): + len=0; /* hub power over current ** */ + break; + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + usb_display_wValue(wValue,wIndex); + switch (wValue) { + case (RH_PORT_ENABLE): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) & ~USBPORTSC_PE; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_PORT_SUSPEND): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) & ~USBPORTSC_SUSP; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_PORT_POWER): + len=0; /* port power ** */ + break; + case (RH_C_PORT_CONNECTION): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_CSC; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_C_PORT_ENABLE): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_PEC; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_C_PORT_SUSPEND): +/*** WR_RH_PORTSTAT(RH_PS_PSSC); */ + len=0; + break; + case (RH_C_PORT_OVER_CURRENT): + len=0; + break; + case (RH_C_PORT_RESET): + rh.c_p_r[wIndex - 1] = 0; + len=0; + break; + } + break; + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + usb_display_wValue(wValue,wIndex); + switch (wValue) { + case (RH_PORT_SUSPEND): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_SUSP; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_PORT_RESET): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_PR; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + wait_ms(10); + status = (status & 0xfff5) & ~USBPORTSC_PR; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + udelay(10); + status = (status & 0xfff5) | USBPORTSC_PE; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + wait_ms(10); + status = (status & 0xfff5) | 0xa; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_PORT_POWER): + len=0; /* port power ** */ + break; + case (RH_PORT_ENABLE): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_PE; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + } + break; + + case RH_SET_ADDRESS: + rh.devnum = wValue; + len=0; + break; + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + i=sizeof(root_hub_config_des); + status=i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_dev_des, len); + break; + case (0x02): /* configuration descriptor */ + i=sizeof(root_hub_config_des); + status=i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_config_des, len); + break; + case (0x03): /*string descriptors */ + if(wValue==0x0300) { + i=sizeof(root_hub_str_index0); + status = i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_str_index0, len); + break; + } + if(wValue==0x0301) { + i=sizeof(root_hub_str_index1); + status = i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_str_index1, len); + break; + } + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + root_hub_hub_des[2] = 2; + i=sizeof(root_hub_hub_des); + status= i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_hub_des, len); + break; + case RH_GET_CONFIGURATION: + *(unsigned char *) data = 0x01; + len = 1; + break; + case RH_SET_CONFIGURATION: + len=0; + break; + default: + stat = USB_ST_STALLED; + } + USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat, + in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2)); + dev->act_len=len; + dev->status=stat; + return stat; + +} + +/******************************************************************************** + * Some Debug Routines + */ + +#ifdef USB_RH_DEBUG + +static void usb_display_Req(unsigned short req) +{ + USB_RH_PRINTF("- Root-Hub Request: "); + switch (req) { + case RH_GET_STATUS: + USB_RH_PRINTF("Get Status "); + break; + case RH_GET_STATUS | RH_INTERFACE: + USB_RH_PRINTF("Get Status Interface "); + break; + case RH_GET_STATUS | RH_ENDPOINT: + USB_RH_PRINTF("Get Status Endpoint "); + break; + case RH_GET_STATUS | RH_CLASS: + USB_RH_PRINTF("Get Status Class"); + break; /* hub power ** */ + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + USB_RH_PRINTF("Get Status Class Others"); + break; + case RH_CLEAR_FEATURE | RH_ENDPOINT: + USB_RH_PRINTF("Clear Feature Endpoint "); + break; + case RH_CLEAR_FEATURE | RH_CLASS: + USB_RH_PRINTF("Clear Feature Class "); + break; + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + USB_RH_PRINTF("Clear Feature Other Class "); + break; + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + USB_RH_PRINTF("Set Feature Other Class "); + break; + case RH_SET_ADDRESS: + USB_RH_PRINTF("Set Address "); + break; + case RH_GET_DESCRIPTOR: + USB_RH_PRINTF("Get Descriptor "); + break; + case RH_GET_DESCRIPTOR | RH_CLASS: + USB_RH_PRINTF("Get Descriptor Class "); + break; + case RH_GET_CONFIGURATION: + USB_RH_PRINTF("Get Configuration "); + break; + case RH_SET_CONFIGURATION: + USB_RH_PRINTF("Get Configuration "); + break; + default: + USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req); + } + USB_RH_PRINTF("\n"); + +} + +static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) +{ + switch (wValue) { + case (RH_PORT_ENABLE): + USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex); + break; + case (RH_PORT_SUSPEND): + USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex); + break; + case (RH_PORT_POWER): + USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex); + break; + case (RH_C_PORT_CONNECTION): + USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex); + break; + case (RH_C_PORT_ENABLE): + USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex); + break; + case (RH_C_PORT_SUSPEND): + USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex); + break; + case (RH_C_PORT_OVER_CURRENT): + USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex); + break; + case (RH_C_PORT_RESET): + USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex); + break; + default: + USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex); + break; + } +} + +#endif + + +#ifdef USB_UHCI_DEBUG + +static int usb_display_td(uhci_td_t *td) +{ + unsigned long tmp; + int valid; + + printf("TD at %p:\n",td); + + tmp=swap_32(td->link); + printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0, + ((tmp & 0x4)==0x4) ? "Depth" : "Breath", + ((tmp & 0x2)==0x2) ? "QH" : "TD", + ((tmp & 0x1)==0x1) ? "invalid" : "valid"); + valid=((tmp & 0x1)==0x0); + tmp=swap_32(td->status); + printf(" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n", + (((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable", + ((tmp>>28)&0x3), + (((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed", + (((tmp>>25)&0x1)==0x1) ? "ISO " : "", + (((tmp>>24)&0x1)==0x1) ? "IOC " : "", + (((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ", + (((tmp>>22)&0x1)==0x1) ? "Stalled" : "", + (((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "", + (((tmp>>20)&0x1)==0x1) ? "Babble" : "", + (((tmp>>19)&0x1)==0x1) ? "NAK" : "", + (((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "", + (tmp&0x7ff)); + tmp=swap_32(td->info); + printf(" MaxLen 0x%lX\n",((tmp>>21)&0x7FF)); + printf(" %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "", + ((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF); + tmp=swap_32(td->buffer); + printf(" Buffer 0x%08lX\n",tmp); + printf(" DEV %08lX\n",td->dev_ptr); + return valid; +} + + +void usb_show_td(int max) +{ + int i; + if(max>0) { + for(i=0;i: */ +#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ +#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ +#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ +#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ +#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ +#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ +#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ +#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ +#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ +#define TD_CTRL_NAK (1 << 19) /* NAK Received */ +#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ +#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ +#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ + +#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ + TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) + +#define TD_TOKEN_TOGGLE 19 + +/* ------------------------------------------------------------------------------------ + Virtual Root HUB + ------------------------------------------------------------------------------------ */ +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +/* Our Vendor Specific feature */ +#define RH_REMOVE_EP 0x00 + + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* Transfer descriptor structure */ +typedef struct { + unsigned long link; /* next td/qh (LE)*/ + unsigned long status; /* status of the td */ + unsigned long info; /* Max Lenght / Endpoint / device address and PID */ + unsigned long buffer; /* pointer to data buffer (LE) */ + unsigned long dev_ptr; /* pointer to the assigned device (BE) */ + unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */ +} uhci_td_t, *puhci_td_t; + +/* Queue Header structure */ +typedef struct { + unsigned long head; /* Next QH (LE)*/ + unsigned long element; /* Queue element pointer (LE) */ + unsigned long res[5]; /* reserved */ + unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */ +} uhci_qh_t, *puhci_qh_t; + +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + int numports; /* number of ports */ + int c_p_r[8]; /* C_PORT_RESET */ +}; + + +#endif /* _USB_UHCI_H_ */ diff --git a/board/MAI/AmigaOneG3SE/via686.c b/board/MAI/AmigaOneG3SE/via686.c new file mode 100644 index 0000000..c797e47 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/via686.c @@ -0,0 +1,299 @@ +/* + * (C) Copyright 2002 + * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include "memio.h" +#include "articiaS.h" +#include "via686.h" +#include "i8259.h" + +#undef VIA_DEBUG + +#ifdef VIA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + + +/* Setup the ISA-to-PCI host bridge */ +void via_isa_init(pci_dev_t dev, struct pci_config_table *table) +{ + char regval; + if (PCI_FUNC(dev) == 0) + { + PRINTF("... PCI-to-ISA bridge, dev=0x%X\n", dev); + + /* Enable I/O Recovery time */ + pci_write_config_byte(dev, 0x40, 0x08); + + /* Enable ISA refresh */ + pci_write_config_byte(dev, 0x41, 0x41); /* was 01 */ + + /* Enable ISA line buffer */ + pci_write_config_byte(dev, 0x45, 0x80); + + /* Gate INTR, and flush line buffer */ + pci_write_config_byte(dev, 0x46, 0x60); + + /* Enable EISA ports 4D0/4D1. Do we need this ? */ + pci_write_config_byte(dev, 0x47, 0xe6); /* was 20 */ + + /* 512 K PCI Decode */ + pci_write_config_byte(dev, 0x48, 0x01); + + /* Wait for PGNT before grant to ISA Master/DMA */ + /* ports 0-FF to SDBus */ + /* IRQ 14 and 15 for ide 0/1 */ + pci_write_config_byte(dev, 0x4a, 0x04); /* Was c4 */ + + /* Plug'n'Play */ + /* Parallel DRQ 3, Floppy DRQ 2 (default) */ + pci_write_config_byte(dev, 0x50, 0x0e); + + /* IRQ Routing for Floppy and Parallel port */ + /* IRQ 6 for floppy, IRQ 7 for parallel port */ + pci_write_config_byte(dev, 0x51, 0x76); + + /* IRQ Routing for serial ports (take IRQ 3 and 4) */ + pci_write_config_byte(dev, 0x52, 0x34); + + /* All IRQ's level triggered. */ + pci_write_config_byte(dev, 0x54, 0x00); + + /* PCI IRQ's all at IRQ 9 */ + pci_write_config_byte(dev, 0x55, 0x90); + pci_write_config_byte(dev, 0x56, 0x99); + pci_write_config_byte(dev, 0x57, 0x90); + + /* Enable Keyboard */ + pci_read_config_byte(dev, 0x5A, ®val); + regval |= 0x01; + pci_write_config_byte(dev, 0x5A, regval); + + pci_write_config_byte(dev, 0x80, 0); + pci_write_config_byte(dev, 0x85, 0x01); + +/* pci_write_config_byte(dev, 0x77, 0x00); */ + } +} + +/* + * Initialize PNP irq routing + */ + +void via_init_irq_routing(uint8 irq_map[]) +{ + char *s; + uint8 level_edge_bits = 0xf; + + /* Set irq routings */ + pci_write_cfg_byte(0, 7<<3, 0x55, irq_map[0]<<4); + pci_write_cfg_byte(0, 7<<3, 0x56, irq_map[1] | irq_map[2]<<4); + pci_write_cfg_byte(0, 7<<3, 0x57, irq_map[3]<<4); + + /* + * Gather level/edge bits + * Default is to assume level triggered + */ + + s = getenv("pci_irqa_select"); + if (s && strcmp(s, "level") == 0) + level_edge_bits &= ~0x01; + + s = getenv("pci_irqb_select"); + if (s && strcmp(s, "level") == 0) + level_edge_bits &= ~0x02; + + s = getenv("pci_irqc_select"); + if (s && strcmp(s, "level") == 0) + level_edge_bits &= ~0x04; + + s = getenv("pci_irqd_select"); + if (s && strcmp(s, "level") == 0) + level_edge_bits &= ~0x08; + + PRINTF("IRQ map\n"); + PRINTF("%d: %s\n", irq_map[0], level_edge_bits&0x1 ? "edge" : "level"); + PRINTF("%d: %s\n", irq_map[1], level_edge_bits&0x2 ? "edge" : "level"); + PRINTF("%d: %s\n", irq_map[2], level_edge_bits&0x4 ? "edge" : "level"); + PRINTF("%d: %s\n", irq_map[3], level_edge_bits&0x8 ? "edge" : "level"); + pci_write_cfg_byte(0, 7<<3, 0x54, level_edge_bits); + + PRINTF("%02x %02x %02x %02x\n", pci_read_cfg_byte(0, 7<<3, 0x54), + pci_read_cfg_byte(0, 7<<3, 0x55), pci_read_cfg_byte(0, 7<<3, 0x56), + pci_read_cfg_byte(0, 7<<3, 0x57)); +} + + +/* Setup the IDE controller. This doesn't seem to work yet. I/O to an IDE controller port */ +/* always return the last character output on the serial port (!) */ +/* This function is called by the pnp-library when it encounters 0:7:1 */ +void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table) +{ + PRINTF("... IDE controller, dev=0x%X\n", dev); + + /* Enable both IDE channels. */ + pci_write_config_byte(dev, 0x40, 0x03); + /* udelay(10000); */ + /* udelay(10000); */ + + /* Enable IO Space */ + pci_write_config_word(dev, 0x04, 0x03); + + /* Set to compatibility mode */ + pci_write_config_byte(dev, 0x09, 0x8A); /* WAS: 0x8f); */ + + /* Set to legacy interrupt mode */ + pci_write_config_byte(dev, 0x3d, 0x00); /* WAS: 0x01); */ + +} + + +/* Set the base address of the floppy controller to 0x3F0 */ +void via_fdc_init(pci_dev_t dev) +{ + unsigned char c; + /* Enable Configuration mode */ + pci_read_config_byte(dev, 0x85, &c); + c |= 0x02; + pci_write_config_byte(dev, 0x85, c); + + /* Set floppy controller port to 0x3F0. */ + SIO_WRITE_CONFIG(0xE3, (0x3F<<2)); + + /* Enable floppy controller */ + SIO_READ_CONFIG(0xE2, c); + c |= 0x10; + SIO_WRITE_CONFIG(0xE2, c); + + /* Switch of configuration mode */ + pci_read_config_byte(dev, 0x85, &c); + c &= ~0x02; + pci_write_config_byte(dev, 0x85, c); +} + +/* Init function 0 of the via southbridge. Called by the pnp-library */ +void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table) +{ + if (PCI_FUNC(dev) == 0) + { + /* FIXME: Try to generate a PCI reset */ + /* unsigned char c; */ + /* pci_read_config_byte(dev, 0x47, &c); */ + /* pci_write_config_byte(dev, 0x47, c | 0x01); */ + + via_isa_init(dev, table); + via_fdc_init(dev); + } +} + +__asm (" .globl via_calibrate_time_base \n" + "via_calibrate_time_base: \n" + " lis 9, 0xfe00 \n" + " li 0, 0x00 \n" + " mttbu 0 \n" + " mttbl 0 \n" + "ctb_loop: \n" + " lbz 0, 0x61(9) \n" + " eieio \n" + " andi. 0, 0, 0x20 \n" + " beq ctb_loop \n" + "ctb_done: \n" + " mftb 3 \n" + " blr"); + +extern unsigned long via_calibrate_time_base(void); + +void via_calibrate_bus_freq(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long tb; + + /* This is 20 microseconds */ + #define CALIBRATE_TIME 28636 + + + /* Enable the timer (and disable speaker) */ + unsigned char c; + c = in_byte(0x61); + out_byte(0x61, ((c & ~0x02) | 0x01)); + + /* Set timer 2 to low/high writing */ + out_byte(0x43, 0xb0); + out_byte(0x42, CALIBRATE_TIME & 0xff); + out_byte(0x42, CALIBRATE_TIME >>8); + + /* Read the time base */ + tb = via_calibrate_time_base(); + + if (tb >= 700000) + gd->bus_clk = 133333333; + else + gd->bus_clk = 100000000; + +} + + +void ide_led(uchar led, uchar status) +{ +/* unsigned char c = in_byte(0x92); */ + +/* if (!status) */ +/* out_byte(0x92, c | 0xC0); */ +/* else */ +/* out_byte(0x92, c & ~0xC0); */ +} + + +void via_init_afterscan(void) +{ + /* Modify IDE controller setup */ + pci_write_cfg_byte(0, 7<<3|1, PCI_LATENCY_TIMER, 0x20); + pci_write_cfg_byte(0, 7<<3|1, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER); + pci_write_cfg_byte(0, 7<<3|1, PCI_INTERRUPT_LINE, 0xff); + pci_write_cfg_byte(0, 7<<3|1, 0x40, 0x0b); /* FIXME: Might depend on drives connected */ + pci_write_cfg_byte(0, 7<<3|1, 0x41, 0x42); /* FIXME: Might depend on drives connected */ + pci_write_cfg_byte(0, 7<<3|1, 0x43, 0x05); + pci_write_cfg_byte(0, 7<<3|1, 0x44, 0x18); + pci_write_cfg_byte(0, 7<<3|1, 0x45, 0x10); + pci_write_cfg_byte(0, 7<<3|1, 0x4e, 0x22); /* FIXME: Not documented, but set in PC bios */ + pci_write_cfg_byte(0, 7<<3|1, 0x4f, 0x20); /* FIXME: Not documented */ + + /* Modify some values in the USB controller */ + pci_write_cfg_byte(0, 7<<3|2, 0x05, 0x17); + pci_write_cfg_byte(0, 7<<3|2, 0x06, 0x01); + pci_write_cfg_byte(0, 7<<3|2, 0x41, 0x12); + pci_write_cfg_byte(0, 7<<3|2, 0x42, 0x03); + pci_write_cfg_byte(0, 7<<3|2, PCI_LATENCY_TIMER, 0x40); + + pci_write_cfg_byte(0, 7<<3|3, 0x05, 0x17); + pci_write_cfg_byte(0, 7<<3|3, 0x06, 0x01); + pci_write_cfg_byte(0, 7<<3|3, 0x41, 0x12); + pci_write_cfg_byte(0, 7<<3|3, 0x42, 0x03); + pci_write_cfg_byte(0, 7<<3|3, PCI_LATENCY_TIMER, 0x40); + + +} diff --git a/board/MAI/AmigaOneG3SE/via686.h b/board/MAI/AmigaOneG3SE/via686.h new file mode 100644 index 0000000..2a06a05 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/via686.h @@ -0,0 +1,29 @@ +#ifndef VIA686_H_ +#define VIA686_H_ + + +#define CMOS_ADDR 0x70 +#define CMOS_DATA 0x71 + +#define I8259_MASTER_CONTROL 0x20 +#define I8259_MASTER_MASK 0x21 + +#define I8259_SLAVE_CONTROL 0xA0 +#define I8259_SLAVE_MASK 0xA1 + +#define SIO_CONFIG_ADDR 0x3F0 +#define SIO_CONFIG_DATA 0x3F1 + +#define SIO_WRITE_CONFIG(addr, byte) \ + out_byte(SIO_CONFIG_ADDR, addr); \ + out_byte(SIO_CONFIG_DATA, byte); + +#define SIO_READ_CONFIG(addr, byte) \ + out_byte(SIO_CONFIG_ADDR, addr); \ + byte = in_byte(SIO_CONFIG_DATA); + +void via_init(void); + +void via_calibrate_bus_freq(void); + +#endif diff --git a/board/MAI/AmigaOneG3SE/video.c b/board/MAI/AmigaOneG3SE/video.c new file mode 100644 index 0000000..36e3c62 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/video.c @@ -0,0 +1,539 @@ +/* + * (C) Copyright 2002 + * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "memio.h" +#include + +unsigned char *cursor_position; +unsigned int cursor_row; +unsigned int cursor_col; + +unsigned char current_attr; + +unsigned int video_numrows = 25; +unsigned int video_numcols = 80; +unsigned int video_scrolls = 0; + +#define VIDEO_BASE (unsigned char *)0xFD0B8000 +#define VIDEO_ROWS video_numrows +#define VIDEO_COLS video_numcols +#define VIDEO_PITCH (2 * video_numcols) +#define VIDEO_SIZE (video_numrows * video_numcols * 2) +#define VIDEO_NAME "vga" + +void video_test(void); +void video_putc(char ch); +void video_puts(char *string); +void video_scroll(int rows); +void video_banner(void); +int video_init(void); +int video_start(void); +int video_rows(void); +int video_cols(void); + +char *prompt_string = "=>"; + +void video_set_color(unsigned char attr) +{ + unsigned char *fb = (unsigned char *)VIDEO_BASE; + int i; + + current_attr = video_get_attr(); + + for (i=0; i VIDEO_COLS-1) + { + cursor_row++; + cursor_col=0; + } + } + + if (cursor_row > VIDEO_ROWS-1) + video_scroll(1); + video_set_cursor(cursor_row, cursor_col); +} + +void video_scroll(int rows) +{ + unsigned short clear = ((unsigned short)current_attr) | (' '<<8); + unsigned short* addr16 = &((unsigned short *)VIDEO_BASE)[(VIDEO_ROWS-rows)*VIDEO_COLS]; + int i; + char *s; + + s = getenv("vga_askscroll"); + video_scrolls += rows; + + if (video_scrolls >= video_numrows) + { + if (s && strcmp(s, "yes")) + { + while (-1 == tstc()); + } + + video_scrolls = 0; + } + + + memcpy(VIDEO_BASE, VIDEO_BASE+rows*(VIDEO_COLS*2), (VIDEO_ROWS-rows)*(VIDEO_COLS*2)); + for (i = 0 ; i < rows * VIDEO_COLS ; i++) + addr16[i] = clear; + cursor_row-=rows; + cursor_col=0; +} + +void video_puts(char *string) +{ + while (*string) + { + video_putc(*string); + string++; + } +} + +int video_start(void) +{ + return 0; +} + +unsigned char video_single_box[] = +{ + 218, 196, 191, + 179, 179, + 192, 196, 217 +}; + +unsigned char video_double_box[] = +{ + 201, 205, 187, + 186, 186, + 200, 205, 188 +}; + +unsigned char video_single_title[] = +{ + 195, 196, 180, 180, 195 +}; + +unsigned char video_double_title[] = +{ + 204, 205, 185, 181, 198 +}; + +#define SINGLE_BOX 0 +#define DOUBLE_BOX 1 + +unsigned char *video_addr(int x, int y) +{ + return VIDEO_BASE + 2*(VIDEO_COLS*y) + 2*x; +} + +void video_bios_print_string(char *s, int x, int y, int attr, int count) +{ + int cattr = current_attr; + if (attr != -1) current_attr = attr; + video_set_cursor(x,y); + while (count) + { + char c = *s++; + if (attr == -1) current_attr = *s++; + video_putc(c); + count--; + } +} + +void video_draw_box(int style, int attr, char *title, int separate, int x, int y, int w, int h) +{ + unsigned char *fb, *fb2; + unsigned char *st = (style == SINGLE_BOX)?video_single_box : video_double_box; + unsigned char *ti = (style == SINGLE_BOX)?video_single_title : video_double_title; + int i; + + fb = video_addr(x,y); + *(fb) = st[0]; + *(fb+1) = attr; + fb += 2; + + fb2 = video_addr(x,y+h-1); + *(fb2) = st[5]; + *(fb2+1) = attr; + fb2 += 2; + + for (i=0; i 0) *fb = clearchar; + fb ++; + *save ++ = *fb; + if (clearattr > 0) *fb = clearattr; + } + fb = fbb + 2*VIDEO_COLS; + } +} + +void video_restore_rect(int x, int y, int w, int h, void *save_area) +{ + unsigned char *save = (unsigned char *)save_area; + unsigned char *fb = video_addr(x,y); + int i,j; + for (i=0; ibd->bi_memsize/(1024*1024)); + printf("FSB: %ld MHz\n", gd->bd->bi_busfreq/1000000); + + printf("\n---- Disk summary ----\n"); + for (i = 0; i < maxdev; i++) + { + ide = ide_get_dev(i); + printf("Device %d: ", i); + dev_print(ide); + } + +/* + video_draw_box(SINGLE_BOX, 0x0F, "Test 1", 0, 0,18, 72, 4); + video_draw_box(DOUBLE_BOX, 0x0F, "Test 2", 1, 4,10, 50, 6); + video_draw_box(DOUBLE_BOX, 0x0F, "Test 3", 0, 40, 3, 20, 5); + + video_draw_text(1, 4, 0x2F, "Highlighted options"); + video_draw_text(1, 5, 0x0F, "Non-selected option"); + video_draw_text(1, 6, 0x07, "disabled option"); +*/ +#ifdef EASTEREGG + } +#endif +} diff --git a/board/MAI/bios_emulator/bios.c b/board/MAI/bios_emulator/bios.c new file mode 100644 index 0000000..d51eb64 --- /dev/null +++ b/board/MAI/bios_emulator/bios.c @@ -0,0 +1,335 @@ +/* + * Mostly done after the Scitech Bios emulation + * Written by Hans-Jörg Frieden + * Hyperion Entertainment + */ +#include "x86emu.h" +#include "glue.h" + +#undef DEBUG +#ifdef DEBUG +#define PRINTF(fmt, args...) printf(fmt, ## args) +#else +#define PRINTF(fmt, args...) +#endif + +#define BIOS_SEG 0xFFF0 +#define PCIBIOS_SUCCESSFUL 0 +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 + +typedef unsigned char UBYTE; +typedef unsigned short UWORD; +typedef unsigned long ULONG; + +typedef char BYTE; +typedef short WORT; +typedef long LONG; + +static inline UBYTE read_byte(volatile UBYTE* from) +{ + int x; + asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (UBYTE)x; +} + +static inline void write_byte(volatile UBYTE *to, int x) +{ + asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static inline UWORD read_word_little(volatile UWORD *from) +{ + int x; + asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from)); + return (UWORD)x; +} + +static inline UWORD read_word_big(volatile UWORD *from) +{ + int x; + asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (UWORD)x; +} + +static inline void write_word_little(volatile UWORD *to, int x) +{ + asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_word_big(volatile UWORD *to, int x) +{ + asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static inline ULONG read_long_little(volatile ULONG *from) +{ + unsigned long x; + asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from)); + return (ULONG)x; +} + +static inline ULONG read_long_big(volatile ULONG *from) +{ + unsigned long x; + asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (ULONG)x; +} + +static inline void write_long_little(volatile ULONG *to, ULONG x) +{ + asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_long_big(volatile ULONG *to, ULONG x) +{ + asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +#define port_to_mem(from) (0xFE000000|(from)) +#define in_byte(from) read_byte( (UBYTE *)port_to_mem(from)) +#define in_word(from) read_word_little((UWORD *)port_to_mem(from)) +#define in_long(from) read_long_little((ULONG *)port_to_mem(from)) +#define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val) +#define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val) +#define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val) + +static void X86API undefined_intr(int intno) +{ + extern u16 A1_rdw(u32 addr); + if (A1_rdw(intno * 4 + 2) == BIOS_SEG) + { + PRINTF("Undefined interrupt %xh called AX = %xh, BX = %xh, CX = %xh, DX = %xh\n", + intno, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + X86EMU_halt_sys(); + } + else + { + PRINTF("Calling interrupt %xh, AL=%xh, AH=%xh\n", intno, M.x86.R_AL, M.x86.R_AH); + X86EMU_prepareForInt(intno); + } +} + +static void X86API int42(int intno); +static void X86API int15(int intno); + +static void X86API int10(int intno) +{ + if (A1_rdw(intno*4+2) == BIOS_SEG) + int42(intno); + else + { + PRINTF("int10: branching to %04X:%04X, AL=%xh, AH=%xh\n", A1_rdw(intno*4+2), A1_rdw(intno*4), + M.x86.R_AL, M.x86.R_AH); + X86EMU_prepareForInt(intno); + } +} + +static void X86API int1A(int intno) +{ + int device; + + switch(M.x86.R_AX) + { + case 0xB101: /* PCI Bios Present? */ + M.x86.R_AL = 0x00; + M.x86.R_EDX = 0x20494350; + M.x86.R_BX = 0x0210; + M.x86.R_CL = 3; + CLEAR_FLAG(F_CF); + break; + case 0xB102: /* Find device */ + device = mypci_find_device(M.x86.R_DX, M.x86.R_CX, M.x86.R_SI); + if (device != -1) + { + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + M.x86.R_BH = mypci_bus(device); + M.x86.R_BL = mypci_devfn(device); + } + else + { + M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + break; + case 0xB103: /* Find PCI class code */ + M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND; + /*printf("Find by class not yet implmented"); */ + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + break; + case 0xB108: /* read config byte */ + M.x86.R_CL = mypci_read_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("read_config_byte %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_CL); */ + break; + case 0xB109: /* read config word */ + M.x86.R_CX = mypci_read_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("read_config_word %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_CX); */ + break; + case 0xB10A: /* read config dword */ + M.x86.R_ECX = mypci_read_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("read_config_long %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_ECX); */ + break; + case 0xB10B: /* write config byte */ + mypci_write_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CL); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("write_config_byte %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_CL); */ + break; + case 0xB10C: /* write config word */ + mypci_write_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CX); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("write_config_word %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_CX); */ + break; + case 0xB10D: /* write config dword */ + mypci_write_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_ECX); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("write_config_long %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_ECX); */ + break; + default: + PRINTF("BIOS int %xh: Unknown function AX=%04xh\n", intno, M.x86.R_AX); + + } +} + +void bios_init(void) +{ + int i; + X86EMU_intrFuncs bios_intr_tab[256]; + + for (i=0; i<256; i++) + { + write_long_little(M.mem_base+i*4, BIOS_SEG<<16); + bios_intr_tab[i] = undefined_intr; + } + + bios_intr_tab[0x10] = int10; + bios_intr_tab[0x1A] = int1A; + bios_intr_tab[0x42] = int42; + bios_intr_tab[0x15] = int15; + + bios_intr_tab[0x6D] = int42; + + X86EMU_setupIntrFuncs(bios_intr_tab); + video_init(); +} + +unsigned char setup_40x25[] = +{ + 0x38, 0x28, 0x2d, 0x0a, 0x1f, 6, 0x19, + 0x1c, 2, 7, 6, 7, 0, 0, 0, 0 +}; + +unsigned char setup_80x25[] = +{ + 0x71, 0x50, 0x5a, 0x0a, 0x1f, 6, 0x19, + 0x1c, 2, 7, 6, 7, 0, 0, 0, 0 +}; + +unsigned char setup_graphics[] = +{ + 0x38, 0x28, 0x20, 0x0a, 0x7f, 6, 0x64, + 0x70, 2, 1, 6, 7, 0, 0, 0, 0 +}; + +unsigned char setup_bw[] = +{ + 0x61, 0x50, 0x52, 0x0f, 0x19, 6, 0x19, + 0x19, 2, 0x0d, 0x0b, 0x0c, 0, 0, 0, 0 +}; + +unsigned char * setup_modes[] = +{ + setup_40x25, /* mode 0: 40x25 bw text */ + setup_40x25, /* mode 1: 40x25 col text */ + setup_80x25, /* mode 2: 80x25 bw text */ + setup_80x25, /* mode 3: 80x25 col text */ + setup_graphics, /* mode 4: 320x200 col graphics */ + setup_graphics, /* mode 5: 320x200 bw graphics */ + setup_graphics, /* mode 6: 640x200 bw graphics */ + setup_bw /* mode 7: 80x25 mono text */ +}; + +unsigned int setup_cols[] = +{ + 40, 40, 80, 80, 40, 40, 80, 80 +}; + +unsigned char setup_modesets[] = +{ + 0x2C, 0x28, 0x2D, 0x29, 0x2A, 0x2E, 0x1E, 0x29 +}; + +unsigned int setup_bufsize[] = +{ + 2048, 2048, 4096, 2096, 16384, 16384, 16384, 4096 +}; + +void bios_set_mode(int mode) +{ + int i; + unsigned char mode_set = setup_modesets[mode]; /* Control register value */ + unsigned char *setup_regs = setup_modes[mode]; /* Register 3D4 Array */ + + /* Switch video off */ + out_byte(0x3D8, mode_set & 0x37); + + /* Set up parameters at 3D4h */ + for (i=0; i<16; i++) + { + out_byte(0x3D4, (unsigned char)i); + out_byte(0x3D5, *setup_regs); + setup_regs++; + } + + /* Enable video */ + out_byte(0x3D8, mode_set); + + /* Set overscan */ + if (mode == 6) out_byte(0x3D9, 0x3F); + else out_byte(0x3D9, 0x30); +} + +static void bios_print_string(void) +{ + extern void video_bios_print_string(char *string, int x, int y, int attr, int count); + char *s = (char *)(M.x86.R_ES<<4) + M.x86.R_BP; + int attr; + if (M.x86.R_AL & 0x02) attr = - 1; + else attr = M.x86.R_BL; + video_bios_print_string(s, M.x86.R_DH, M.x86.R_DL, attr, M.x86.R_CX); +} + +static void X86API int42(int intno) +{ + switch (M.x86.R_AH) + { + case 0x00: + bios_set_mode(M.x86.R_AL); + break; + case 0x13: + bios_print_string(); + break; + default: + PRINTF("Warning: VIDEO BIOS interrupt %xh unimplemented function %xh, AL = %xh\n", + intno, M.x86.R_AH, M.x86.R_AL); + } +} + +static void X86API int15(int intno) +{ + PRINTF("Called interrupt 15h: AX = %xh, BX = %xh, CX = %xh, DX = %xh\n", + M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); +} diff --git a/board/MAI/bios_emulator/glue.c b/board/MAI/bios_emulator/glue.c new file mode 100644 index 0000000..b380f0d --- /dev/null +++ b/board/MAI/bios_emulator/glue.c @@ -0,0 +1,515 @@ +#include +#include +#include <74xx_7xx.h> + + +#ifdef DEBUG +#undef DEBUG +#endif + +#ifdef DEBUG +#define PRINTF(format, args...) _printf(format , ## args) +#else +#define PRINTF(format, argc...) +#endif + +static pci_dev_t to_pci(int bus, int devfn) +{ + return PCI_BDF(bus, (devfn>>3), devfn&3); +} + +int mypci_find_device(int vendor, int product, int index) +{ + return pci_find_device(vendor, product, index); +} + +int mypci_bus(int device) +{ + return PCI_BUS(device); +} + +int mypci_devfn(int device) +{ + return (PCI_DEV(device)<<3) | PCI_FUNC(device); +} + + +#define mypci_read_func(type, size) \ +type mypci_read_cfg_##size##(int bus, int devfn, int offset) \ +{ \ + type c; \ + pci_read_config_##size##(to_pci(bus, devfn), offset, &c); \ + return c; \ +} + +#define mypci_write_func(type, size) \ +void mypci_write_cfg_##size##(int bus, int devfn, int offset, int value) \ +{ \ + pci_write_config_##size##(to_pci(bus, devfn), offset, value); \ +} + +mypci_read_func(u8,byte); +mypci_read_func(u16,word); + +mypci_write_func(u8,byte); +mypci_write_func(u16,word); + +u32 mypci_read_cfg_long(int bus, int devfn, int offset) +{ + u32 c; + pci_read_config_dword(to_pci(bus, devfn), offset, &c); + return c; +} + +void mypci_write_cfg_long(int bus, int devfn, int offset, int value) +{ + pci_write_config_dword(to_pci(bus, devfn), offset, value); +} + +void _printf(const char *fmt, ...) +{ + va_list args; + char buf[CFG_PBSIZE]; + + va_start(args, fmt); + (void)vsprintf(buf, fmt, args); + va_end(args); + + printf(buf); +} + +char *_getenv(char *name) +{ + return getenv(name); +} + +unsigned long get_bar_size(pci_dev_t dev, int offset) +{ + u32 bar_back, bar_value; + + /* Save old BAR value */ + pci_read_config_dword(dev, offset, &bar_back); + + /* Write all 1's. */ + pci_write_config_dword(dev, offset, ~0); + + /* Now read back the relevant bits */ + pci_read_config_dword(dev, offset, &bar_value); + + /* Restore original value */ + pci_write_config_dword(dev, offset, bar_back); + + if (bar_value == 0) return 0xFFFFFFFF; /* This BAR is disabled */ + + if ((bar_value & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) + { + /* This is a memory space BAR. Mask it out so we get the size of it */ + return ~(bar_value & PCI_BASE_ADDRESS_MEM_MASK) + 1; + } + + /* Not suitable */ + return 0xFFFFFFFF; +} + +void enable_compatibility_hole(void) +{ + u8 cfg; + pci_dev_t art = PCI_BDF(0,0,0); + + pci_read_config_byte(art, 0x54, &cfg); + /* cfg |= 0x08; */ + cfg |= 0x20; + pci_write_config_byte(art, 0x54, cfg); +} + +void disable_compatibility_hole(void) +{ + u8 cfg; + pci_dev_t art = PCI_BDF(0,0,0); + + pci_read_config_byte(art, 0x54, &cfg); + /* cfg &= ~0x08; */ + cfg &= ~0x20; + pci_write_config_byte(art, 0x54, cfg); +} + +void map_rom(pci_dev_t dev, u32 address) +{ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, address|PCI_ROM_ADDRESS_ENABLE); +} + +void unmap_rom(pci_dev_t dev) +{ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0); +} + +void bat_map(u8 batnum, u32 address, u32 length) +{ + u32 temp = address; + address &= 0xFFFE0000; + temp &= 0x0001FFFF; + length = (length - 1 ) >> 17; + length <<= 2; + + switch (batnum) + { + case 0: + __asm volatile ("mtdbatu 0, %0" : : "r" (address | length | 3)); + __asm volatile ("mtdbatl 0, %0" : : "r" (address | 0x22)); + break; + case 1: + __asm volatile ("mtdbatu 1, %0" : : "r" (address | length | 3)); + __asm volatile ("mtdbatl 1, %0" : : "r" (address | 0x22)); + break; + case 2: + __asm volatile ("mtdbatu 2, %0" : : "r" (address | length | 3)); + __asm volatile ("mtdbatl 2, %0" : : "r" (address | 0x22)); + break; + case 3: + __asm volatile ("mtdbatu 3, %0" : : "r" (address | length | 3)); + __asm volatile ("mtdbatl 3, %0" : : "r" (address | 0x22)); + break; + } +} + +int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size); + +int attempt_map_rom(pci_dev_t dev, void *copy_address) +{ + u32 rom_size = 0; + u32 rom_address = 0; + u32 bar_size = 0; + u32 bar_backup = 0; + int i,j; + void *image = 0; + u32 image_size = 0; + int did_correct = 0; + u32 prefetch_addr = 0; + u32 prefetch_size = 0; + u32 prefetch_idx = 0; + + /* Get the size of the expansion rom */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0xFFFFFFFF); + pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_size); + if ((rom_size & 0x01) == 0) + { + PRINTF("No ROM\n"); + return 0; + } + + rom_size &= 0xFFFFF800; + rom_size = (~rom_size)+1; + + PRINTF("ROM Size is %dK\n", rom_size/1024); + + /* + * Try to find a place for the ROM. We always attempt to use + * one of the card's bases for this, as this will be in any + * bridge's resource range as well as being free of conflicts + * with other cards. In a graphics card it is very unlikely + * that there won't be any base address that is large enough to + * hold the rom. + * + * FIXME: To work around this, theoretically the largest base + * could be used if none is found in the loop below. + */ + + for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4) + { + bar_size = get_bar_size(dev, i); + PRINTF("PCI_BASE_ADDRESS_%d is %dK large\n", + (i - PCI_BASE_ADDRESS_0)/4, + bar_size/1024); + if (bar_size != 0xFFFFFFFF && bar_size >= rom_size) + { + PRINTF("Found a match for rom size\n"); + pci_read_config_dword(dev, i, &rom_address); + rom_address &= 0xFFFFFFF0; + if (rom_address != 0 && rom_address != 0xFFFFFFF0) break; + } + } + + if (rom_address == 0 || rom_address == 0xFFFFFFF0) + { + PRINTF("No suitable rom address found\n"); + return 0; + } + + /* Disable the BAR */ + pci_read_config_dword(dev, i, &bar_backup); + pci_write_config_dword(dev, i, 0); + + /* Map ROM */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address | PCI_ROM_ADDRESS_ENABLE); + + /* Copy the rom to a place in the emulator space */ + PRINTF("Claiming BAT 2\n"); + bat_map(2, rom_address, rom_size); + /* show_bat_mapping(); */ + + if (0 == find_image(rom_address, rom_size, &image, &image_size)) + { + PRINTF("No x86 BIOS image found\n"); + return 0; + } + + PRINTF("Copying %ld bytes from 0x%lx to 0x%lx\n", (long)image_size, (long)image, (long)copy_address); + + /* memcpy(copy_address, rom_address, rom_size); */ + { + unsigned char *from = (unsigned char *)image; /* rom_address; */ + unsigned char *to = (unsigned char *)copy_address; + for (j=0; j>16, (prefetch_addr+prefetch_size)>>16); */ +/* pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, (prefetch_addr>>16)); */ +/* pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, (prefetch_addr+prefetch_size)>>16); */ + } + + pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, 0x1000); + pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, 0x0000); + + pci_write_config_byte(bridge, 0xD0, 0x0A); + pci_write_config_byte(bridge, 0xD3, 0x04); + + /* + * Set the interrupt pin to 0 + */ +#if 0 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0); + pci_write_config_byte(dev, PCI_INTERRUPT_PIN, 0); +#endif + pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0); + pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0); + + } + } + + /* Finally, enable the card's IO and memory response */ + pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0); + + return 1; +} + +int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size) +{ + int i = 0; + unsigned char *rom = (unsigned char *)rom_address; + /* if (*rom != 0x55 || *(rom+1) != 0xAA) return 0; /* No bios rom this is, yes. */ */ + + for (;;) + { + unsigned short pci_data_offset = *(rom+0x18) + 256 * *(rom+0x19); + unsigned short pci_image_length = (*(rom+pci_data_offset+0x10) + 256 * *(rom+pci_data_offset+0x11)) * 512; + unsigned char pci_image_type = *(rom+pci_data_offset+0x14); + if (*rom != 0x55 || *(rom+1) != 0xAA) + { + PRINTF("Invalid header this is\n"); + return 0; + } + PRINTF("Image %i: Type %d (%s)\n", i++, pci_image_type, + pci_image_type==0 ? "x86" : + pci_image_type==1 ? "OpenFirmware" : + "Unknown"); + if (pci_image_type == 0) + { + *image = rom; + *image_size = pci_image_length; + return 1; + } + + if (*(rom+pci_data_offset+0x15) & 0x80) + { + PRINTF("LAST image encountered, no image found\n"); + return 0; + } + + rom += pci_image_length; + } +} + +void show_bat_mapping(void) +{ + u32 dbat0u, dbat0l, ibat0u, ibat0l; + u32 dbat1u, dbat1l, ibat1u, ibat1l; + u32 dbat2u, dbat2l, ibat2u, ibat2l; + u32 dbat3u, dbat3l, ibat3u, ibat3l; + u32 msr, hid0, l2cr_reg; + + __asm volatile ("mfdbatu %0,0" : "=r" (dbat0u)); + __asm volatile ("mfdbatl %0,0" : "=r" (dbat0l)); + __asm volatile ("mfibatu %0,0" : "=r" (ibat0u)); + __asm volatile ("mfibatl %0,0" : "=r" (ibat0l)); + + __asm volatile ("mfdbatu %0,1" : "=r" (dbat1u)); + __asm volatile ("mfdbatl %0,1" : "=r" (dbat1l)); + __asm volatile ("mfibatu %0,1" : "=r" (ibat1u)); + __asm volatile ("mfibatl %0,1" : "=r" (ibat1l)); + + __asm volatile ("mfdbatu %0,2" : "=r" (dbat2u)); + __asm volatile ("mfdbatl %0,2" : "=r" (dbat2l)); + __asm volatile ("mfibatu %0,2" : "=r" (ibat2u)); + __asm volatile ("mfibatl %0,2" : "=r" (ibat2l)); + + __asm volatile ("mfdbatu %0,3" : "=r" (dbat3u)); + __asm volatile ("mfdbatl %0,3" : "=r" (dbat3l)); + __asm volatile ("mfibatu %0,3" : "=r" (ibat3u)); + __asm volatile ("mfibatl %0,3" : "=r" (ibat3l)); + + __asm volatile ("mfmsr %0" : "=r" (msr)); + __asm volatile ("mfspr %0,1008": "=r" (hid0)); + __asm volatile ("mfspr %0,1017": "=r" (l2cr_reg)); + + printf("dbat0u: %08x dbat0l: %08x ibat0u: %08x ibat0l: %08x\n", + dbat0u, dbat0l, ibat0u, ibat0l); + printf("dbat1u: %08x dbat1l: %08x ibat1u: %08x ibat1l: %08x\n", + dbat1u, dbat1l, ibat1u, ibat1l); + printf("dbat2u: %08x dbat2l: %08x ibat2u: %08x ibat2l: %08x\n", + dbat2u, dbat2l, ibat2u, ibat2l); + printf("dbat3u: %08x dbat3l: %08x ibat3u: %08x ibat3l: %08x\n", + dbat3u, dbat3l, ibat3u, ibat3l); + + printf("\nMSR: %08x HID0: %08x L2CR: %08x \n", msr,hid0, l2cr_reg); +} + + +void remove_init_data(void) +{ + char *s; + + /* Invalidate and disable data cache */ + invalidate_l1_data_cache(); + dcache_disable(); + + s = getenv("x86_cache"); + + if (!s) + { + icache_enable(); + dcache_enable(); + } + else if (s) + { + if (strcmp(s, "dcache")==0) + { + dcache_enable(); + } + else if (strcmp(s, "icache") == 0) + { + icache_enable(); + } + else if (strcmp(s, "on")== 0 || strcmp(s, "both") == 0) + { + dcache_enable(); + icache_enable(); + } + } + + /* show_bat_mapping();*/ +} diff --git a/board/MAI/bios_emulator/glue.h b/board/MAI/bios_emulator/glue.h new file mode 100644 index 0000000..585efe1 --- /dev/null +++ b/board/MAI/bios_emulator/glue.h @@ -0,0 +1,57 @@ +#ifndef GLUE_H +#define GLUE_H + +typedef unsigned int pci_dev_t; + +int mypci_find_device(int vendor, int product, int index); +int mypci_bus(int device); +int mypci_devfn(int device); +unsigned long get_bar_size(pci_dev_t dev, int offset); + +u8 mypci_read_cfg_byte(int bus, int devfn, int offset); +u16 mypci_read_cfg_word(int bus, int devfn, int offset); +u32 mypci_read_cfg_long(int bus, int devfn, int offset); + +void mypci_write_cfg_byte(int bus, int devfn, int offset, u8 value); +void mypci_write_cfg_word(int bus, int devfn, int offset, u16 value); +void mypci_write_cfg_long(int bus, int devfn, int offset, u32 value); + +void _printf(const char *fmt, ...); +char *_getenv(char *name); + +void *malloc(size_t size); +void memset(void *addr, int value, size_t size); +void memcpy(void *to, void *from, size_t numbytes); +int strcmp(char *, char *); + +void enable_compatibility_hole(void); +void disable_compatibility_hole(void); + +void map_rom(pci_dev_t dev, unsigned long address); +void unmap_rom(pci_dev_t dev); +int attempt_map_rom(pci_dev_t dev, void *copy_address); + +#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCI_BASE_ADDRESS_SPACE_IO 0x01 +#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) + +#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ +#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ +#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ +#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ +#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ +#define PCI_BUS(d) (((d) >> 16) & 0xff) +#define PCI_DEV(d) (((d) >> 11) & 0x1f) +#define PCI_FUNC(d) (((d) >> 8) & 0x7) +#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8) + +#define PCI_ANY_ID (~0) +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 + +#define OFF(addr) ((addr) & 0xFFFF) +#define SEG(addr) (((addr)>>4) &0xF000) + +#endif diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake new file mode 100755 index 0000000..4d6ccb3 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp new file mode 100755 index 0000000..d372949 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo new file mode 100755 index 0000000..6f65d41 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm new file mode 100755 index 0000000..7de5030 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep b/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep new file mode 100755 index 0000000..5451b22 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm new file mode 100755 index 0000000..fbd3352 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm new file mode 100755 index 0000000..dd14a7a Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans b/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans new file mode 100755 index 0000000..a1aea4f Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake new file mode 100755 index 0000000..f198f29 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm new file mode 100755 index 0000000..e312a0b Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm new file mode 100755 index 0000000..9fe81a3 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/trans b/board/MAI/bios_emulator/scitech/bin-linux/libc/trans new file mode 100755 index 0000000..e536c04 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/bin-linux/libc/trans differ diff --git a/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat new file mode 100755 index 0000000..776d138 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat @@ -0,0 +1,28 @@ +@echo off +REM Setup for compiling with Borland C++ 3.1. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC3;%BC3_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC3;%BC3_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC3_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC3.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_SNAP= +PATH %SCITECH_BIN%;%BC3_PATH%\BIN;%DEFPATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC3_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC3_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC3_PATH%\BIN\tlink.cfg + +echo Borland C++ 3.1 DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat new file mode 100755 index 0000000..d2939f4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat @@ -0,0 +1,37 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat new file mode 100755 index 0000000..246517d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 16 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg + +echo Borland C++ 4.5 16 bit DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat new file mode 100755 index 0000000..cbb2c79 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32 bit DOS compilation configuration set up (DPMI32). diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat new file mode 100755 index 0000000..14d7c05 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP=1 +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 Snap compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat new file mode 100755 index 0000000..50bd3cb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat @@ -0,0 +1,46 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT=1 +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32 bit DOS compilation configuration set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat new file mode 100755 index 0000000..4b59fa4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows VxD mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD=1 +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32-bit VxD compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat new file mode 100755 index 0000000..4d799b4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 16 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_VXD= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg + +echo Borland C++ 4.5 16 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat new file mode 100755 index 0000000..a6c199f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat @@ -0,0 +1,37 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat new file mode 100755 index 0000000..6a0fde2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET C_INCLUDE=%BC5_PATH%\INCLUDE +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat new file mode 100755 index 0000000..23b5038 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 16 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg + +echo Borland C++ 5.0 16 bit DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat new file mode 100755 index 0000000..0521f93 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat @@ -0,0 +1,35 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit DOS compilation configuration set up (DPMI32). diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat b/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat new file mode 100755 index 0000000..e3241ff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat @@ -0,0 +1,35 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SMX32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SMX32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32=1 +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit SMX compilation configuration set up (SMX32). diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat new file mode 100755 index 0000000..ab3acd2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP=1 +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 Snap compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat new file mode 100755 index 0000000..4dcc372 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat @@ -0,0 +1,48 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT=1 +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit DOS compilation configuration set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat new file mode 100755 index 0000000..2356911 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD=1 +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit Windows (VxD) compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat new file mode 100755 index 0000000..cd79d86 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat @@ -0,0 +1,34 @@ + @echo off +REM Setup for compiling with Borland C++ 5.0 in 16 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_VXD= +SET USE_BC5=1 +SET USE_SMX32= +SET USE_SMX16= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg + +echo Borland C++ 5.0 16 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat new file mode 100755 index 0000000..8b8cec9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET C_INCLUDE=%BC5_PATH%\INCLUDE +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat new file mode 100755 index 0000000..ebfeb2e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat new file mode 100755 index 0000000..6e09428 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET C_INCLUDE=%BCB5_PATH%\INCLUDE +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat new file mode 100755 index 0000000..aa13e7d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 16 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink.cfg + +echo Borland C++ Builder 5.0 16 bit DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat new file mode 100755 index 0000000..d0017d4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat @@ -0,0 +1,35 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit DOS compilation configuration set up (DPMI32). diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat new file mode 100755 index 0000000..2b969a9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat @@ -0,0 +1,35 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SMX32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SMX32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32=1 +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit SMX compilation configuration set up (SMX32). diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat new file mode 100755 index 0000000..d7b8ff2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP=1 +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 Snap compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat new file mode 100755 index 0000000..1de3601 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat @@ -0,0 +1,48 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BCB5;%BCB5_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BCB5;%BCB5_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT=1 +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit DOS compilation configuration set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat new file mode 100755 index 0000000..28de58c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD=1 +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit Windows (VxD) compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat new file mode 100755 index 0000000..c30d004 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat @@ -0,0 +1,34 @@ + @echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 16 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_VXD= +SET USE_BC5=1 +SET USE_SMX32= +SET USE_SMX16= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink.cfg + +echo Borland C++ Builder 5.0 16 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat new file mode 100755 index 0000000..18760e1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET C_INCLUDE=%BCB5_PATH%\INCLUDE +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat new file mode 100755 index 0000000..198c1a2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/build b/board/MAI/bios_emulator/scitech/bin/build new file mode 100755 index 0000000..ff1973d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/build @@ -0,0 +1,22 @@ +#! /bin/sh + +if [ $# -lt 1 ] || ( [ "$1" != gcc-linux ] && [ "$1" != qnx4 ] ) ; then + echo Usage: $0 compiler_name [DMAKE commands] + echo + echo Current compilers: + echo " gcc-linux - GNU C/C++ 2.7 or higher, 32 bit" + echo " qnx4 - Watcom C/C++ 10.6 or higher, 32 bit" + exit 1 +fi + +unset DBG OPT OPT_SIZE BUILD_DLL IMPORT_DLL FPU CHECKS BETA +. ${1}.sh + +shift +dmake $* && exit 0 + +echo ************************************************* +echo * An error occurred while building the library. * +echo ************************************************* +exit 1 + diff --git a/board/MAI/bios_emulator/scitech/bin/build.bat b/board/MAI/bios_emulator/scitech/bin/build.bat new file mode 100755 index 0000000..ee29093 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/build.bat @@ -0,0 +1,4 @@ +@echo off +rem Disable checked build and build release code +set CHECKED= +call build_it.bat %1 %2 %3 %4 %5 %6 %7 %8 %9 diff --git a/board/MAI/bios_emulator/scitech/bin/build_db.bat b/board/MAI/bios_emulator/scitech/bin/build_db.bat new file mode 100755 index 0000000..2b32529 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/build_db.bat @@ -0,0 +1,4 @@ +@echo off +rem Enable checked build and build debug code +set CHECKED=1 +call build_it.bat %1 %2 %3 %4 %5 %6 %7 %8 %9 diff --git a/board/MAI/bios_emulator/scitech/bin/build_it.bat b/board/MAI/bios_emulator/scitech/bin/build_it.bat new file mode 100755 index 0000000..5a619b4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/build_it.bat @@ -0,0 +1,432 @@ +@echo off +rem Generic batch file to build a version of the library. This batch file +rem assumes that the correct batch files exist to setup the appropriate +rem compilation environments, and that the DMAKE.EXE program is available +rem somewhere on the path. +rem +rem Builds as release or debug depending on the value of the CHECKED +rem environment variable. + +rem Unset all environment variables that change the compile process +set DBG= +set OPT= +set OPT_SIZE= +set BUILD_DLL= +set IMPORT_DLL= +set FPU= +set CHECKS= +set BETA= + +if %1==bc31-d16 goto bc31-d16 +if %1==bc45-d16 goto bc45-d16 +if %1==bc45-d32 goto bc45-d32 +if %1==bc45-tnt goto bc45-tnt +if %1==bc45-w16 goto bc45-w16 +if %1==bc45-w32 goto bc45-w32 +if %1==bc45-c32 goto bc45-c32 +if %1==bc45-vxd goto bc45-vxd +if %1==bc45-snp goto bc45-snp +if %1==bc50-d16 goto bc50-d16 +if %1==bc50-d32 goto bc50-d32 +if %1==bc50-tnt goto bc50-tnt +if %1==bc50-w16 goto bc50-w16 +if %1==bc50-w32 goto bc50-w32 +if %1==bc50-c32 goto bc50-c32 +if %1==bc50-vxd goto bc50-vxd +if %1==bc50-snp goto bc50-snp +if %1==gcc2-d32 goto gcc2-d32 +if %1==gcc2-w32 goto gcc2-w32 +if %1==gcc2-c32 goto gcc2-c32 +if %1==gcc2-linux goto gcc2-linux +if %1==vc40-d16 goto vc40-d16 +if %1==vc40-tnt goto vc40-tnt +if %1==vc40-w16 goto vc40-w16 +if %1==vc40-w32 goto vc40-w32 +if %1==vc40-c32 goto vc40-c32 +if %1==vc40-drv9x goto vc40-drv9x +if %1==vc40-drvnt goto vc40-drvnt +if %1==vc40-rtt goto vc40-rtt +if %1==vc40-snp goto vc40-snp +if %1==vc50-d16 goto vc50-d16 +if %1==vc50-tnt goto vc50-tnt +if %1==vc50-w16 goto vc50-w16 +if %1==vc50-w32 goto vc50-w32 +if %1==vc50-c32 goto vc50-c32 +if %1==vc50-drv9x goto vc50-drv9x +if %1==vc50-drvnt goto vc50-drvnt +if %1==vc50-rtt goto vc50-rtt +if %1==vc50-snp goto vc50-snp +if %1==vc60-d16 goto vc60-d16 +if %1==vc60-tnt goto vc60-tnt +if %1==vc60-w16 goto vc60-w16 +if %1==vc60-w32 goto vc60-w32 +if %1==vc60-c32 goto vc60-c32 +if %1==vc60-drv9x goto vc60-drv9x +if %1==vc60-drvnt goto vc60-drvnt +if %1==vc60-drvw2k goto vc60-drvw2k +if %1==vc60-rtt goto vc60-rtt +if %1==vc60-snp goto vc60-snp +if %1==wc10ad16 goto wc10ad16 +if %1==wc10ad32 goto wc10ad32 +if %1==wc10atnt goto wc10atnt +if %1==wc10aw16 goto wc10aw16 +if %1==wc10aw32 goto wc10aw32 +if %1==wc10ac32 goto wc10ac32 +if %1==wc10ao32 goto wc10ao32 +if %1==wc10ap32 goto wc10ap32 +if %1==wc10asnp goto wc10asnp +if %1==wc10-d16 goto wc10-d16 +if %1==wc10-d32 goto wc10-d32 +if %1==wc10-tnt goto wc10-tnt +if %1==wc10-w16 goto wc10-w16 +if %1==wc10-w32 goto wc10-w32 +if %1==wc10-c32 goto wc10-c32 +if %1==wc10-o32 goto wc10-o32 +if %1==wc10-p32 goto wc10-p32 +if %1==wc10-snp goto wc10-snp +if %1==wc11-d16 goto wc11-d16 +if %1==wc11-d32 goto wc11-d32 +if %1==wc11-tnt goto wc11-tnt +if %1==wc11-w16 goto wc11-w16 +if %1==wc11-w32 goto wc11-w32 +if %1==wc11-c32 goto wc11-c32 +if %1==wc11-o32 goto wc11-o32 +if %1==wc11-p32 goto wc11-p32 +if %1==wc11-snp goto wc11-snp + +echo Usage: BUILD 'compiler_name' [DMAKE commands] +echo. +echo Where 'compiler_name' is of the form comp-os, where +echo 'comp' defines the compiler and 'os' defines the OS environment. +echo For instance 'bc50-w32' is for Borland C++ 5.0 for Win32. +echo The value of 'comp' can be any of the following: +echo. +echo bc45 - Borland C++ 4.5x +echo bc50 - Borland C++ 5.x +echo vc40 - Visual C++ 4.x +echo vc50 - Visual C++ 5.x +echo vc60 - Visual C++ 6.x +echo wc10 - Watcom C++ 10.6 +echo wc11 - Watcom C++ 11.0 +echo gcc2 - GNU C/C++ 2.9x +echo. +echo The value of 'os' can be one of the following: +echo. +echo d16 - 16-bit DOS +echo d32 - 32-bit DOS +echo w16 - 16-bit Windows GUI mode +echo c32 - 32-bit Windows console mode +echo w32 - 32-bit Windows GUI mode +echo o16 - 16-bit OS/2 console mode +echo o32 - 32-bit OS/2 console mode +echo p32 - 32-bit OS/2 Presentation Manager +echo snp - 32-bit SciTech Snap application +echo linux - 32-bit Linux application +goto end + +rem ------------------------------------------------------------------------- +rem Setup for the specified compiler + +:bc31-d16 +call bc31-d16.bat +goto compileit + +:bc45-d16 +call bc45-d16.bat +goto compileit + +:bc45-d32 +call bc45-d32.bat +goto compileit + +:bc45-tnt +call bc45-tnt.bat +goto compileit + +:bc45-w16 +call bc45-w16.bat +goto compileit + +:bc45-w32 +call bc45-w32.bat +goto compileit + +:bc45-c32 +call bc45-c32.bat +goto compileit + +:bc45-vxd +call bc45-vxd.bat +goto compileit + +:bc50-d16 +call bc50-d16.bat +goto compileit + +:bc50-d32 +call bc50-d32.bat +goto compileit + +:bc50-tnt +call bc50-tnt.bat +goto compileit + +:bc50-w16 +call bc50-w16.bat +goto compileit + +:bc50-w32 +call bc50-w32.bat +goto compileit + +:bc50-c32 +call bc50-c32.bat +goto compileit + +:bc50-vxd +call bc50-vxd.bat +goto compileit + +:gcc2-d32 +call gcc2-d32.bat +goto compileit + +:gcc2-w32 +call gcc2-w32.bat +goto compileit + +:gcc2-c32 +call gcc2-c32.bat +goto compileit + +:gcc2-linux +call gcc2-linux.bat +goto compileit + +:sc70-d16 +call sc70-d16.bat +goto compileit + +:sc70-w16 +call sc70-w16.bat +goto compileit + +:sc70-tnt +call sc70-tnt.bat +goto compileit + +:sc70-w32 +call sc70-w32.bat +goto compileit + +:sc70-c32 +call sc70-c32.bat +goto compileit + +:vc40-d16 +call vc40-d16.bat +goto compileit + +:vc40-tnt +call vc40-tnt.bat +goto compileit + +:vc40-w16 +call vc40-w16.bat +goto compileit + +:vc40-w32 +call vc40-w32.bat +goto compileit + +:vc40-c32 +call vc40-c32.bat +goto compileit + +:vc40-drv9x +call vc40-drv9x.bat +goto compileit + +:vc40-drvnt +call vc40-drvnt.bat +goto compileit + +:vc40-rtt +call vc40-rtt.bat +goto compileit + +:vc50-d16 +call vc50-d16.bat +goto compileit + +:vc50-tnt +call vc50-tnt.bat +goto compileit + +:vc50-w16 +call vc50-w16.bat +goto compileit + +:vc50-w32 +call vc50-w32.bat +goto compileit + +:vc50-c32 +call vc50-c32.bat +goto compileit + +:vc50-drv9x +call vc50-drv9x.bat +goto compileit + +:vc50-drvnt +call vc50-drvnt.bat +goto compileit + +:vc50-rtt +call vc50-rtt.bat +goto compileit + +:vc60-d16 +call vc60-d16.bat +goto compileit + +:vc60-tnt +call vc60-tnt.bat +goto compileit + +:vc60-w16 +call vc60-w16.bat +goto compileit + +:vc60-w32 +call vc60-w32.bat +goto compileit + +:vc60-c32 +call vc60-c32.bat +goto compileit + +:vc60-drv9x +call vc60-drv9x.bat +goto compileit + +:vc60-drvnt +call vc60-drvnt.bat +goto compileit + +:vc60-drvw2k +call vc60-drvw2k.bat +goto compileit + +:vc60-rtt +call vc60-rtt.bat +goto compileit + +:wc10ad16 +call wc10ad16.bat +goto compileit + +:wc10ad32 +call wc10ad32.bat +goto compileit + +:wc10atnt +call wc10atnt.bat +goto compileit + +:wc10aw16 +call wc10aw16.bat +goto compileit + +:wc10aw32 +call wc10aw32.bat +goto compileit + +:wc10ac32 +call wc10ac32.bat +goto compileit + +:wc10ao32 +call wc10ao32.bat +goto compileit + +:wc10ap32 +call wc10ap32.bat +goto compileit + +:wc10-d16 +call wc10-d16.bat +goto compileit + +:wc10-d32 +call wc10-d32.bat +goto compileit + +:wc10-tnt +call wc10-tnt.bat +goto compileit + +:wc10-w16 +call wc10-w16.bat +goto compileit + +:wc10-w32 +call wc10-w32.bat +goto compileit + +:wc10-c32 +call wc10-c32.bat +goto compileit + +:wc10-o32 +call wc10-o32.bat +goto compileit + +:wc10-p32 +call wc10-p32.bat +goto compileit + +:wc11-d16 +call wc11-d16.bat +goto compileit + +:wc11-d32 +call wc11-d32.bat +goto compileit + +:wc11-tnt +call wc11-tnt.bat +goto compileit + +:wc11-w16 +call wc11-w16.bat +goto compileit + +:wc11-w32 +call wc11-w32.bat +goto compileit + +:wc11-c32 +call wc11-c32.bat +goto compileit + +:wc11-o32 +call wc11-o32.bat +goto compileit + +:wc11-p32 +call wc11-p32.bat +goto compileit + +:compileit +k_rm -f *.lib *.a +dmake %2 %3 %4 %5 %6 %7 %8 %9 +if errorlevel 1 goto errorend +goto end + +:errorend +echo ************************************************* +echo * An error occurred while building the library. * +echo ************************************************* +:end diff --git a/board/MAI/bios_emulator/scitech/bin/cddrv.bat b/board/MAI/bios_emulator/scitech/bin/cddrv.bat new file mode 100755 index 0000000..b64f4d7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/cddrv.bat @@ -0,0 +1,6 @@ +@echo off +%1 +cd %3 +%4 %5 %6 %7 %8 %9 +%2 + diff --git a/board/MAI/bios_emulator/scitech/bin/cdit b/board/MAI/bios_emulator/scitech/bin/cdit new file mode 100755 index 0000000..b22023d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/cdit @@ -0,0 +1,10 @@ +#! /bin/sh + +cd $1 +PROG=$2 +shift 2 +rm -f *.lib *.a +$PROG $* +RET=$? +cd .. +exit $RET diff --git a/board/MAI/bios_emulator/scitech/bin/cdit.bat b/board/MAI/bios_emulator/scitech/bin/cdit.bat new file mode 100755 index 0000000..950b648 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/cdit.bat @@ -0,0 +1,5 @@ +@echo off +cd %1 +k_rm -f *.lib *.a +shift 1 +%1 %2 %3 %4 %5 %6 %7 %8 %9 diff --git a/board/MAI/bios_emulator/scitech/bin/djgpp.env b/board/MAI/bios_emulator/scitech/bin/djgpp.env new file mode 100644 index 0000000..5a2c3d8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/djgpp.env @@ -0,0 +1,46 @@ +#= Don't edit this line unless you move djgpp.env outside +#= of the djgpp installation directory. If you do move +#= it, set DJDIR to the directory you installed DJGPP in. +#= +DJDIR=%:/>DJGPP% + ++USER=dosuser ++TMPDIR=%DJDIR%/tmp ++EMU387=%DJDIR%/bin/emu387.dxe ++LFN=y + +[bison] +BISON_HAIRY=%DJDIR%/lib/bison.hai +BISON_SIMPLE=%DJDIR%/lib/bison.sim + +[cpp] +CPLUS_INCLUDE_PATH=%/>;CPLUS_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/lang/cxx;%DJDIR%/include;%DJDIR%/contrib/grx20/include +C_INCLUDE_PATH=%/>;C_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/include;%DJDIR%/contrib/grx20/include +OBJCPLUS_INCLUDE_PATH=%/>;OBJCPLUS_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc +OBJC_INCLUDE_PATH=%/>;OBJC_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc + +[gcc] +COMPILER_PATH=%/>;COMPILER_PATH%%DJDIR%/bin +LIBRARY_PATH=%/>;LIBRARY_PATH%%DJDIR%/lib;%DJDIR%/contrib/grx20/lib;%SCITECH%/lib/release/dos32/dj2 + +[info] +INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info +INFO_COLORS=0x1f.0x31 + +[emacs] +INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info + +[less] +LESSBINFMT=*k<%X> +LESSCHARDEF=8bcccbcc12bc5b95.b127.b +LESS=%LESS% -h5$y5$Dd2.0$Du14.0$Ds4.7$Dk9.0$ + +[locate] ++LOCATE_PATH=%DJDIR%/lib/locatedb.dat + +[ls] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: +[dir] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: +[vdir] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: diff --git a/board/MAI/bios_emulator/scitech/bin/djgpp_db.env b/board/MAI/bios_emulator/scitech/bin/djgpp_db.env new file mode 100644 index 0000000..9b792c9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/djgpp_db.env @@ -0,0 +1,46 @@ +#= Don't edit this line unless you move djgpp.env outside +#= of the djgpp installation directory. If you do move +#= it, set DJDIR to the directory you installed DJGPP in. +#= +DJDIR=%:/>DJGPP% + ++USER=dosuser ++TMPDIR=%DJDIR%/tmp ++EMU387=%DJDIR%/bin/emu387.dxe ++LFN=y + +[bison] +BISON_HAIRY=%DJDIR%/lib/bison.hai +BISON_SIMPLE=%DJDIR%/lib/bison.sim + +[cpp] +CPLUS_INCLUDE_PATH=%/>;CPLUS_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/lang/cxx;%DJDIR%/include;%DJDIR%/contrib/grx20/include +C_INCLUDE_PATH=%/>;C_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/include;%DJDIR%/contrib/grx20/include +OBJCPLUS_INCLUDE_PATH=%/>;OBJCPLUS_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc +OBJC_INCLUDE_PATH=%/>;OBJC_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc + +[gcc] +COMPILER_PATH=%/>;COMPILER_PATH%%DJDIR%/bin +LIBRARY_PATH=%/>;LIBRARY_PATH%%DJDIR%/lib;%DJDIR%/contrib/grx20/lib;%SCITECH%/lib/debug/dos32/dj2 + +[info] +INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info +INFO_COLORS=0x1f.0x31 + +[emacs] +INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info + +[less] +LESSBINFMT=*k<%X> +LESSCHARDEF=8bcccbcc12bc5b95.b127.b +LESS=%LESS% -h5$y5$Dd2.0$Du14.0$Ds4.7$Dk9.0$ + +[locate] ++LOCATE_PATH=%DJDIR%/lib/locatedb.dat + +[ls] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: +[dir] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: +[vdir] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: diff --git a/board/MAI/bios_emulator/scitech/bin/findint3.bat b/board/MAI/bios_emulator/scitech/bin/findint3.bat new file mode 100755 index 0000000..2e1506c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/findint3.bat @@ -0,0 +1 @@ +perl c:\scitech\src\perl\findint3.per diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh b/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh new file mode 100755 index 0000000..61ffd93 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +# Setup for compiling with GCC/G++ for BeOS + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +export MAKESTARTUP=$SCITECH/makedefs/gcc_beos.mk +export INCLUDE="-Iinclude -I$SCITECH/include -I$PRIVATE/include" +export USE_X11=0 +export USE_BEOS=1 + +echo GCC BeOS console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh new file mode 100755 index 0000000..3816a5d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +# Setup for compiling with GCC/G++ for FreeBSD + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +export MAKESTARTUP=$SCITECH/makedefs/gcc_freebsd.mk +export INCLUDE="-Iinclude -I$SCITECH/include -I$PRIVATE/include" +export USE_X11=1 +export USE_FREEBSD=1 + +echo GCC FreeBSD console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh b/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh new file mode 100755 index 0000000..27a4c49 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh @@ -0,0 +1,19 @@ +#! /bin/sh + +# Setup for compiling with GCC/G++ for Linux + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +export MAKESTARTUP=$SCITECH/makedefs/gcc_linux.mk +export INCLUDE="include;$SCITECH/include;$PRIVATE/include" +export USE_LINUX=1 + +if [ "x$LIBC" = x ]; then + echo "GCC Linux console compilation environment set up (glib)" +else + echo "GCC Linux console compilation environment set up (libc5)" +fi diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat new file mode 100755 index 0000000..13c4783 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup for compiling with GNU C compiler + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2 +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2 +echo Checked debug build enabled. +goto setvars + +:setvars +set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include +set MAKESTARTUP=%SCITECH%\makedefs\gcc_win32.mk +set MAKE_MODE= +set USE_WIN16= +set USE_WIN32=1 +set WIN32_GUI= +set USE_SNAP= +set GCC_LIBBASE=gcc2 +PATH %SCITECH_BIN%;%GCC2_PATH%\NATIVE\BIN;%DEFPATH% + +echo GCC 2.9.x 32-bit Win32 console compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat new file mode 100755 index 0000000..97cb8bd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat @@ -0,0 +1,28 @@ +@echo off +REM Setup for compiling with DJGPP 2.02 + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\release\dos32\dj2 +%SCITECH%\bin-dos\k_cp %SCITECH%\BIN\DJGPP.ENV %DJ_PATH%\DJGPP.ENV +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\debug\dos32\dj2 +%SCITECH%\bin-dos\k_cp %SCITECH%\BIN\DJGPP_DB.ENV %DJ_PATH%\DJGPP.ENV +echo Checked debug build enabled. +goto setvars + +:setvars +set DJGPP=%DJ_PATH%\DJGPP.ENV +set INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%DJ_PATH%\INCLUDE; +set MAKESTARTUP=%SCITECH%\MAKEDEFS\DJ32.MK +set USE_WIN16= +set USE_WIN32= +set WIN32_GUI= +set USE_SNAP= +set DJ_LIBBASE=dj2 +PATH %SCITECH_BIN%;%DJ_PATH%\BIN;%DEFPATH% + +echo DJGPP 2.02 32-bit DOS compilation environment set up (DPMI). + diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat new file mode 100755 index 0000000..ceb2ab8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup for compiling with GNU C cross-compiler + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2 +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2 +echo Checked debug build enabled. +goto setvars + +:setvars +set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include +set MAKESTARTUP=%SCITECH%\MAKEDEFS\gcc_linux.mk +set MAKE_MODE=UNIX +set USE_WIN16= +set USE_WIN32= +set WIN32_GUI= +set USE_SNAP= +set GCC_LIBBASE=gcc2 +PATH %SCITECH_BIN%;%GCC2_PATH%\cross-linux\i386-redhat-linux\BIN;%DEFPATH% + +echo GCC 2.9.x 32-bit Linux console cross compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat new file mode 100755 index 0000000..bdb31aa --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup for compiling with GNU C compiler + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2 +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2 +echo Checked debug build enabled. +goto setvars + +:setvars +set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include +set MAKESTARTUP=%SCITECH%\makedefs\gcc_win32.mk +set MAKE_MODE= +set USE_WIN16= +set USE_WIN32=1 +set WIN32_GUI=1 +set USE_SNAP= +set GCC_LIBBASE=gcc2 +PATH %SCITECH_BIN%;%GCC2_PATH%\NATIVE\BIN;%DEFPATH% + +echo GCC 2.9.x 32-bit Win32 GUI compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/makelib.bat b/board/MAI/bios_emulator/scitech/bin/makelib.bat new file mode 100755 index 0000000..6316734 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/makelib.bat @@ -0,0 +1,97 @@ +call wc11-d32.bat + +cd c:\private\src\license +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\pm +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\console +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\nucleus +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\zlib +dmake clean +dmake depend +dmake -u install + +cd c:\private\src\graphics\ref2d +dmake clean +dmake depend +dmake -u install +cd c:\private\src\drvlib +dmake clean +dmake depend +dmake -u install + +call wc11-w32.bat + +cd c:\private\src\license +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\pm +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\console +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\nucleus +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\zlib +dmake clean +dmake depend +dmake -u install + +cd c:\private\src\graphics\ref2d +dmake clean +dmake depend +dmake -u install +cd c:\private\src\drvlib +dmake clean +dmake depend +dmake -u install + +call wc10-d32.bat + +cd c:\private\src\license +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\pm +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\console +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\nucleus +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\zlib +dmake clean +dmake depend +dmake -u install + +cd c:\private\src\graphics\ref2d +dmake clean +dmake depend +dmake -u install +cd c:\private\src\drvlib +dmake clean +dmake depend +dmake -u install + +cd \private\src\graphics\drivers diff --git a/board/MAI/bios_emulator/scitech/bin/meltobjs.sh b/board/MAI/bios_emulator/scitech/bin/meltobjs.sh new file mode 100755 index 0000000..fd1804b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/meltobjs.sh @@ -0,0 +1,23 @@ +#! /bin/sh +# +# This script generates a single object file from a set of libraries (*.a files) +# Usage: meltobjs.sh target.o library1.a library2.a ... +# +# (C) SciTech Software, Inc. 1998 +# + +TMPDIR=/tmp/melt$$ +TARGET=$1 +TARGETDIR=$PWD +shift +mkdir $TMPDIR + +cd $TMPDIR + +for a in $* +do + ar x $a +done +ld -r -o $TARGETDIR/$TARGET *.o + +rm -fr $TMPDIR \ No newline at end of file diff --git a/board/MAI/bios_emulator/scitech/bin/ntddk.bat b/board/MAI/bios_emulator/scitech/bin/ntddk.bat new file mode 100755 index 0000000..07c0d78 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/ntddk.bat @@ -0,0 +1,42 @@ +@echo off +REM: Set up environment variables for Microsoft Windows NT DDK development. +REM: Note that we have hard coded this for Windows NT i386 development. + +SET USE_NTDRV=1 +SET USE_W2KDRV= +SET BASEDIR=%NT_DDKROOT% +SET PATH=%BASEDIR%\bin;%PATH% +SET NTMAKEENV=%BASEDIR%\inc +SET BUILD_MAKE_PROGRAM=nmake.exe +SET BUILD_DEFAULT=-ei -nmake -i +SET BUILD_DEFAULT_TARGETS=-386 +SET _OBJ_DIR=obj +SET NEW_CRTS=1 +SET _NTROOT=%BASEDIR% +SET INCLUDE=%BASEDIR%\inc;%INCLUDE% + +if .%CHECKED%==.1 goto checked + +REM: set up an NT free build environment +SET DDKBUILDENV=free +SET C_DEFINES=-D_IDWBUILD +SET NTDBGFILES=1 +SET NTDEBUG= +SET NTDEBUGTYPE= +SET MSC_OPTIMIZATION= +set LIB=%BASEDIR%\lib\i386\free;%SCITECH_LIB%\LIB\RELEASE\NTDRV\VC6;%MSVCDir%\LIB;. + +goto done + +:checked + +REM: set up an NT checked build environment +SET DDKBUILDENV=checked +SET C_DEFINES=-D_IDWBUILD -DRDRDBG -DSRVDBG +SET NTDBGFILES= +SET NTDEBUG=ntsd +SET NTDEBUGTYPE=both +SET MSC_OPTIMIZATION=/Od /Oi +set LIB=%BASEDIR%\lib\i386\free;%SCITECH_LIB%\LIB\DEBUG\NTDRV\VC6;%MSVCDir%\LIB;. + +:done diff --git a/board/MAI/bios_emulator/scitech/bin/qnx4.sh b/board/MAI/bios_emulator/scitech/bin/qnx4.sh new file mode 100755 index 0000000..843c4d9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/qnx4.sh @@ -0,0 +1,18 @@ +#! /bin/sh + +# Setup for compiling with Watcom C/C++ for QNX4 + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +export MAKESTARTUP=$SCITECH/makedefs/qnx4.mk +export INCLUDE="-I$SCITECH/include -I$PRIVATE/include -I/usr/include" +export USE_QNX=1 +export USE_QNX4=1 +export WC_LIBBASE=wc10 + +echo Qnx 4 console compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/qnxnto.sh b/board/MAI/bios_emulator/scitech/bin/qnxnto.sh new file mode 100755 index 0000000..c114f9e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/qnxnto.sh @@ -0,0 +1,21 @@ +#! /bin/sh + +# Setup for compiling with Watcom C/C++ for QNX Neutrino + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +if [ X$GCC_PATH = "X" ]; then + export GCC_PATH=/usr/gcc/bin +fi + +export MAKESTARTUP=$SCITECH/makedefs/qnxnto.mk +export INCLUDE="-I$SCITECH/include -I$PRIVATE/include -I/usr/nto/include" +export USE_BIOS=1 # VBIOS lib is tiny under Neutrino, always include it +export USE_QNX=1 +export USE_QNXNTO=1 + +echo Qnx Neutrino console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh new file mode 100755 index 0000000..0a272d6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh @@ -0,0 +1,42 @@ +#! /bin/sh + +# BeOS VERSION +# Set the place where SciTech Software is installed, and where each +# of the supported compilers is installed. These environment variables +# are used by the batch files in the SCITECH\BIN directory. +# +# Modify the as appropriate for your compiler configuration (you should +# only need to change things in this batch file). +# +# This version is for a normal BeOS installation. + +# The SCITECH variable points to where batch files, makefile startups, +# include files and source files will be found when compiling. + +export SCITECH=$MGL_ROOT + +# The SCITECH_LIB variable points to where the SciTech libraries live +# for installation and linking. This allows you to have the source and +# include files on local machines for compiling and have the libraries +# located on a common network machine (for network builds). + +export SCITECH_LIB=$SCITECH + +# The PRIVATE variable points to where private source files reside that +# do not live in the public source tree + +export PRIVATE=$HOME/private + +# The following define the locations of all the compilers that you may +# be using. Change them to reflect where you have installed your +# compilers. + +export GCC_PATH=/boot/develop/tools/gnupro/bin + +# Add the Scitech bin path to the current PATH +export PATH=$SCITECH/bin:$SCITECH/bin-beos:$PATH +#if [ "x$LIBC" = x ]; then +# export PATH=$PATH:$SCITECH/bin-beos/glibc +#else +# export PATH=$PATH:$SCITECH/bin-beos/libc +#fi diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh new file mode 100755 index 0000000..c920748 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh @@ -0,0 +1,37 @@ +#! /bin/sh + +# LINUX VERSION +# Set the place where SciTech Software is installed, and where each +# of the supported compilers is installed. These environment variables +# are used by the batch files in the SCITECH\BIN directory. +# +# Modify the as appropriate for your compiler configuration (you should +# only need to change things in this batch file). +# +# This version is for a normal Linux installation. + +# The SCITECH variable points to where batch files, makefile startups, +# include files and source files will be found when compiling. + +export SCITECH=$MGL_ROOT + +# The SCITECH_LIB variable points to where the SciTech libraries live +# for installation and linking. This allows you to have the source and +# include files on local machines for compiling and have the libraries +# located on a common network machine (for network builds). + +export SCITECH_LIB=$SCITECH + +# The PRIVATE variable points to where private source files reside that +# do not live in the public source tree + +export PRIVATE=$HOME/private + +# The following define the locations of all the compilers that you may +# be using. Change them to reflect where you have installed your +# compilers. + +export GCC_PATH=/usr/bin + +# Add the Scitech bin path to the current PATH +export PATH=$SCITECH/bin:$SCITECH/bin-freebsd:$PATH diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh new file mode 100755 index 0000000..35cbf1d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh @@ -0,0 +1,43 @@ +#! /bin/sh + +# LINUX VERSION +# Set the place where SciTech Software is installed, and where each +# of the supported compilers is installed. These environment variables +# are used by the batch files in the SCITECH\BIN directory. +# +# Modify the as appropriate for your compiler configuration (you should +# only need to change things in this batch file). +# +# This version is for a normal Linux installation. + +# The SCITECH variable points to where batch files, makefile startups, +# include files and source files will be found when compiling. + +export SCITECH=$MGL_ROOT + +# The SCITECH_LIB variable points to where the SciTech libraries live +# for installation and linking. This allows you to have the source and +# include files on local machines for compiling and have the libraries +# located on a common network machine (for network builds). + +export SCITECH_LIB=$SCITECH + +# The PRIVATE variable points to where private source files reside that +# do not live in the public source tree + +export PRIVATE=$HOME/private + +# The following define the locations of all the compilers that you may +# be using. Change them to reflect where you have installed your +# compilers. + +export GCC_PATH=/usr/bin +export TEMP=/tmp TMP=/tmp + +# Add the Scitech bin path to the current PATH +export PATH=$SCITECH/bin:$SCITECH/bin-linux:$PATH +if [ "x$LIBC" = x ]; then + export PATH=$SCITECH/bin-linux/glibc:$PATH +else + export PATH=$SCITECH/bin-linux/libc:$PATH +fi diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh new file mode 100755 index 0000000..1d73109 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh @@ -0,0 +1,37 @@ +#! /bin/sh + +# QNX 4 VERSION +# Set the place where SciTech Software is installed, and where each +# of the supported compilers is installed. These environment variables +# are used by the batch files in the SCITECH\BIN directory. +# +# Modify the as appropriate for your compiler configuration (you should +# only need to change things in this batch file). +# +# This version is for a normal Linux installation. + +# The SCITECH variable points to where batch files, makefile startups, +# include files and source files will be found when compiling. + +export SCITECH=$MGL_ROOT + +# The SCITECH_LIB variable points to where the SciTech libraries live +# for installation and linking. This allows you to have the source and +# include files on local machines for compiling and have the libraries +# located on a common network machine (for network builds). + +export SCITECH_LIB=$SCITECH + +# The PRIVATE variable points to where private source files reside that +# do not live in the public source tree + +export PRIVATE=$HOME/private + +# The following define the locations of all the compilers that you may +# be using. Change them to reflect where you have installed your +# compilers. + +export WC10_PATH=/usr/watcom/10.6/usr + +# Add the Scitech bin path to the current PATH +export PATH=$SCITECH/bin:$SCITECH/bin-qnx:$PATH diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars.bat b/board/MAI/bios_emulator/scitech/bin/set-vars.bat new file mode 100755 index 0000000..2a2101d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars.bat @@ -0,0 +1,110 @@ +@echo off +REM:========================================================================= +REM: Master batch file to set up all necessary environment variables for +REM: the SciTech makefile utilities. This batch file should be executed +REM: *first* before any other batch files when you start a command shell. +REM: You should not need to modify any batch files except this one to +REM: configure the makefile utilities. +REM:========================================================================= + +REM: Set the place where SciTech Software is installed, and where each +REM: of the supported compilers is installed. These environment variables +REM: are used by the batch files in the SCITECH\BIN directory. +REM: +REM: Modify the as appropriate for your compiler configuration (you should +REM: only need to change things in this batch file). +REM: +REM: This version is for a normal MSDOS installation. + +REM: The SCITECH variable points to where batch files, makefile startups, +REM: include files and source files will be found when compiling. + +SET SCITECH=c:\scitech + +REM: The SCITECH_LIB variable points to where the SciTech libraries live +REM: for installation and linking. This allows you to have the source and +REM: include files on local machines for compiling and have the libraries +REM: located on a common network machine (for network builds). + +SET SCITECH_LIB=%SCITECH% + +REM: The PRIVATE variable points to where private source files reside that +REM: do not live in the public source tree + +SET PRIVATE=c:\private + +REM: The following sets up the path to the SciTech command line utilities +REM: for the development operating system. We select either DOS hosted +REM: tools or Win32 hosted tools depending on whether you are running +REM: on NT or not. Windows 9x users can use the Win32 hosted tools but +REM: they run slower, but you will have long filenames if you do this. + +IF .%OS%==.Windows_NT goto Win32_path +IF NOT .%WINDIR%==. goto Win32_path +SET SCITECH_BIN=%SCITECH%\bin;%SCITECH%\bin-dos +goto path_set + +REM: The following sets up the path to the SciTech command line utilities +REM: for the development operating system. This version uses the Win32 +REM: hosted tools by default, so you can use long filenames. + +:Win32_path +SET SCITECH_BIN=%SCITECH%\bin;%SCITECH%\bin-win32 + +:path_set + +REM: Set the TMP variable for dmake if this is not already set + +SET TMP=%SCITECH% + +REM: Set the following environment variable to use the Netwide Assembler +REM: (NASM) provided with the MGL tools to build all assembler modules. +REM: If you have Turbo Assembler 4.0 or later and you wish to use it, +REM: you can use it by removing the following line. + +SET USE_NASM=1 + +REM: The following is used to set up DDK directories for device driver +REM: development. They can safely be ignored unless you are using the +REM: SciTech makefile utilities to build device drivers. + +SET DDKDRIVE=c: +SET MSSDK=c:\c\win32sdk +SET W95_DDKROOT=c:\c\95ddk +SET W98_DDKROOT=c:\c\98ddk +SET NT_DDKROOT=c:\c\ntddk +SET W2K_DDKROOT=c:\c\2000ddk +SET MASM_ROOT=c:\c\masm611 +SET VTOOLSD=c:\c\vtd95 +SET SOFTICE_PATH=c:\c\sint + +REM: The following define the locations of all the compilers that you may +REM: be using. Change them to reflect where you have installed your +REM: compilers. + +SET BC3_PATH=c:\c\bc3 +SET BC4_PATH=c:\c\bc45 +SET BC5_PATH=c:\c\bc50 +SET BCB5_PATH=c:\c\bcb50 +SET VC_PATH=c:\c\msvc +SET VC4_PATH=c:\c\vc42 +SET VC5_PATH=c:\c\vc50 +SET VC6_PATH=c:\c\vc60 +SET SC70_PATH=c:\c\sc75 +SET WC10A_PATH=c:\c\wc10a +SET WC10_PATH=c:\c\wc10 +SET WC11_PATH=c:\c\wc11 +SET TNT_PATH=c:\c\tnt +SET DJ_PATH=c:\c\djgpp +SET GCC2_PATH=c:\unix\usr + +REM: The following define the locations of the IDE and compiler path +REM: tools for Visual C++. If you do a standard installation, you wont +REM: need to change this. If however you did a custom install and changed +REM: the paths to these directory, you will need to modify this to suit. + +SET VC5_MSDevDir=%VC5_PATH%\sharedide +SET VC5_MSVCDir=%VC5_PATH%\vc +SET VC6_MSDevDir=%VC6_PATH%\common\msdev98 +SET VC6_MSVCDir=%VC6_PATH%\vc98 + diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat new file mode 100755 index 0000000..71f7d8e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat @@ -0,0 +1,36 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC4_PATH% +set C_INCLUDE=%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 4.2 32 bit Windows compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat new file mode 100755 index 0000000..9817493 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat @@ -0,0 +1,27 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC4;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC4;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16 DOS bit compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat new file mode 100755 index 0000000..62e3521 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat @@ -0,0 +1,21 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +REM: First setup for Win32 console development +call vc40-c32.bat > NUL + +REM: Extra stuff to set up for Windows 9x DDK development +set MASTER_MAKE=1 +set DDKROOT=%W95_DDKROOT% +set SDKROOT=%MSSDK% +set C16_ROOT=%VC_PATH% +set C32_ROOT=%VC4_PATH% + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 4.2 Windows 9x driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat new file mode 100755 index 0000000..83b6780 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat @@ -0,0 +1,18 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +REM: First setup for Win32 console development (with Platform SDK) +call vc40-c32.bat sdk > NUL + +REM: Extra stuff to set up for Windows NT DDK development +SET BASEDIR=%NT_DDKROOT% +SET PATH=%NT_DDKROOT%\bin;%PATH% + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 4.2 Windows NT driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat new file mode 100755 index 0000000..7997044 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC4_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +set INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32= +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP=1 +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +echo Visual C++ 4.2 Snap compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat new file mode 100755 index 0000000..b0fc936 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat @@ -0,0 +1,42 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\COFFLIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\COFFLIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC4_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +set INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_TNT= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +echo Visual C++ 4.2 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat new file mode 100755 index 0000000..2849a20 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC4;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC4;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET VC_LIBBASE=VC4 +SET USE_RTTARGET= +SET USE_SNAP= +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16 bit Windows compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat new file mode 100755 index 0000000..d93a624 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat @@ -0,0 +1,37 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC4_PATH% +set C_INCLUDE=%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 4.2 32 bit Windows compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat new file mode 100755 index 0000000..a420a54 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat @@ -0,0 +1,20 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +SET LIB=%VC4_PATH%\LIB;. +SET TOOLROOTDIR=%VC4_PATH% +SET INCLUDE=\xc\include;%VC4_PATH%\INCLUDE +SET INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%DEFPATH% + +echo Visual C++ 4.2 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat new file mode 100755 index 0000000..62d27b9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat @@ -0,0 +1,39 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +SET MSDevDir=%VC5_MSDevDir% +SET MSVCDir=%VC5_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE; +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 5.0 32-bit Windows console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat new file mode 100755 index 0000000..c789c50 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC5;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC5;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat new file mode 100755 index 0000000..27a4a14 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat @@ -0,0 +1,21 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development +call vc60-c32.bat > NUL + +REM: Extra stuff to set up for Windows 9x DDK development +set MASTER_MAKE=1 +set DDKROOT=%W95_DDKROOT% +set SDKROOT=%MSSDK% +set C16_ROOT=%VC_PATH% +set C32_ROOT=%VC6_PATH% + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows 9x driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat new file mode 100755 index 0000000..17b2f25 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat @@ -0,0 +1,17 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development (with Platform SDK) +call vc60-c32.bat sdk > NUL + +REM: Now setup stuff for the NT DDK build environment +call ntddk.bat + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows NT driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat new file mode 100755 index 0000000..afb2fb1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC5_PATH%\VC +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC5_PATH%\VC\INCLUDE;%TNT_PATH%\INCLUDE; +set INIT=%VC5_PATH%\VC +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32= +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET=1 +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +echo Visual C++ 5.0 RTTarget-32 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat new file mode 100755 index 0000000..22d2e13 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat @@ -0,0 +1,33 @@ +@echo off REM Setup environment variables for Visual C++ 5.0 32 bit +edition + +SET MSDevDir=%VC5_MSDevDir% +SET MSVCDir=%VC5_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32= +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP=1 +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +echo Visual C++ 5.0 Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat new file mode 100755 index 0000000..6b09199 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat @@ -0,0 +1,42 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\COFFLIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\COFFLIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC5_PATH%\VC +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC5_PATH%\VC\INCLUDE;%TNT_PATH%\INCLUDE; +set INIT=%VC5_PATH%\VC +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_TNT= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +echo Visual C++ 5.0 32-bit compilation environment set up (with TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat new file mode 100755 index 0000000..52ab495 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat @@ -0,0 +1,27 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC5;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC5;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16-bit Windows compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat new file mode 100755 index 0000000..07bc5e5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat @@ -0,0 +1,39 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +SET MSDevDir=%VC5_MSDevDir% +SET MSVCDir=%VC5_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE; +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 5.0 32-bit Windows console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat new file mode 100755 index 0000000..fe286bd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat @@ -0,0 +1,20 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +SET LIB=%VC5_PATH%\VC\LIB;. +SET TOOLROOTDIR=%VC5_PATH%\VC +SET INCLUDE=\xc\include;%VC5_PATH%\VC\INCLUDE +SET INIT=%VC5_PATH%\VC +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%DEFPATH% + +echo Visual C++ 5.0 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat new file mode 100755 index 0000000..e98417d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat @@ -0,0 +1,39 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +SET MSDevDir=%VC6_MSDevDir% +SET MSVCDir=%VC6_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 6.0 32-bit Windows console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat new file mode 100755 index 0000000..10855e0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC6;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC6;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat new file mode 100755 index 0000000..27a4a14 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat @@ -0,0 +1,21 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development +call vc60-c32.bat > NUL + +REM: Extra stuff to set up for Windows 9x DDK development +set MASTER_MAKE=1 +set DDKROOT=%W95_DDKROOT% +set SDKROOT=%MSSDK% +set C16_ROOT=%VC_PATH% +set C32_ROOT=%VC6_PATH% + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows 9x driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat new file mode 100755 index 0000000..17b2f25 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat @@ -0,0 +1,17 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development (with Platform SDK) +call vc60-c32.bat sdk > NUL + +REM: Now setup stuff for the NT DDK build environment +call ntddk.bat + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows NT driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat new file mode 100755 index 0000000..f304293 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat @@ -0,0 +1,17 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development (with Platform SDK) +call vc60-c32.bat sdk > NUL + +REM: Now setup stuff for the NT DDK build environment +call w2kddk.bat + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows Windows 2000 driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat new file mode 100755 index 0000000..5348ef9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +SET MSDevDir=%VC6_MSDevDir% +SET MSVCDir=%VC6_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32= +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP=1 +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +echo Visual C++ 6.0 Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat new file mode 100755 index 0000000..1d8b5e3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat @@ -0,0 +1,42 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC6;%VC6_PATH%\VC98\LIB;%TNT_PATH%\COFFLIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC6;%VC6_PATH%\VC98\LIB;%TNT_PATH%\COFFLIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC6_PATH%\VC98 +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC6_PATH%\VC98\INCLUDE;%TNT_PATH%\INCLUDE; +set INIT=%VC6_PATH%\VC98 +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_TNT= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 PATH +%SCITECH_BIN%;%VC6_PATH%\VC98\BIN;%VC6_PATH%\COMMON\MSDEV98\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +echo Visual C++ 6.0 32-bit compilation environment set up (with TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat new file mode 100755 index 0000000..70175c3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat @@ -0,0 +1,27 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC6;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC6;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16-bit Windows compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat new file mode 100755 index 0000000..2f8e7ab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat @@ -0,0 +1,39 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +SET MSDevDir=%VC6_MSDevDir% +SET MSVCDir=%VC6_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 6.0 32-bit Windows compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat new file mode 100755 index 0000000..57b23d2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat @@ -0,0 +1,20 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +SET LIB=%VC6_PATH%\VC98\LIB;. +SET TOOLROOTDIR=%VC6_PATH%\VC98 +SET INCLUDE=\xc\include;%VC6_PATH%\VC98\INCLUDE; +SET INIT=%VC6_PATH%\VC98 +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%VC6_PATH%\VC98\BIN;%VC6_PATH%\COMMON\MSDEV98\BIN;%DEFPATH% + +echo Visual C++ 6.0 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/w2kddk.bat b/board/MAI/bios_emulator/scitech/bin/w2kddk.bat new file mode 100755 index 0000000..92858d1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/w2kddk.bat @@ -0,0 +1,42 @@ +@echo off +REM: Set up environment variables for Microsoft Windows NT DDK development. +REM: Note that we have hard coded this for Windows NT i386 development. + +SET USE_NTDRV=1 +SET USE_W2KDRV=1 +SET BASEDIR=%W2K_DDKROOT% +SET PATH=%BASEDIR%\bin;%PATH% +SET NTMAKEENV=%BASEDIR%\inc +SET BUILD_MAKE_PROGRAM=nmake.exe +SET BUILD_DEFAULT=-ei -nmake -i +SET BUILD_DEFAULT_TARGETS=-386 +SET _OBJ_DIR=obj +SET NEW_CRTS=1 +SET _NTROOT=%BASEDIR% +SET INCLUDE=%BASEDIR%\inc;%BASEDIR%\inc\ddk;%INCLUDE% + +if .%CHECKED%==.1 goto checked + +REM: set up an NT free build environment +SET DDKBUILDENV=free +SET C_DEFINES=-D_IDWBUILD +SET NTDBGFILES=1 +SET NTDEBUG= +SET NTDEBUGTYPE= +SET MSC_OPTIMIZATION= +set LIB=%BASEDIR%\libfre\i386;%SCITECH_LIB%\LIB\RELEASE\W2KDRV\VC6;%MSVCDir%\LIB;. + +goto done + +:checked + +REM: set up an NT checked build environment +SET DDKBUILDENV=checked +SET C_DEFINES=-D_IDWBUILD -DRDRDBG -DSRVDBG +SET NTDBGFILES= +SET NTDEBUG=ntsd +SET NTDEBUGTYPE=both +SET MSC_OPTIMIZATION=/Od /Oi +set LIB=%BASEDIR%\libchk\i386;%SCITECH_LIB%\LIB\DEBUG\W2KDRV\VC6;%MSVCDir%\LIB;. + +:done diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat new file mode 100755 index 0000000..2d738f3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 Win32 console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat new file mode 100755 index 0000000..5c53a90 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\WIN; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat new file mode 100755 index 0000000..a5c7210 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 32-bit DOS compilation environment set up (DOS4GW) + diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat new file mode 100755 index 0000000..579dece --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 16-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os216\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os216\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216=1 +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 16-bit OS/2 compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat new file mode 100755 index 0000000..3404b42 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 32-bit OS/2 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat new file mode 100755 index 0000000..57057de --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI=1 +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 32-bit OS/2 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat new file mode 100755 index 0000000..46f8659 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (QNX 4) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\QNX4\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\QNX;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\QNX4\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\QNX;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\QH; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4=1 +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 32-bit QNX compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat new file mode 100755 index 0000000..1fde624 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP=1 +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat new file mode 100755 index 0000000..d12f042 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat @@ -0,0 +1,46 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT;%TNT_PATH%\INCLUDE +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT=1 +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE=1 + +echo Watcom C/C++ 10.6 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat new file mode 100755 index 0000000..e8ba871 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 16 bit Windows mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\WIN; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 16-bit Windows compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat new file mode 100755 index 0000000..839bdde --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 Win32 GUI compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat new file mode 100755 index 0000000..fc783d8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat @@ -0,0 +1,24 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode + +SET LIB=%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=%WC10_PATH%\H;%WC10_PATH%\H\NT; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat new file mode 100755 index 0000000..6e0c24d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a Win32 console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat new file mode 100755 index 0000000..f9ecb67 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat @@ -0,0 +1,29 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC10A;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC10A;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\WIN; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +SET EDPATH=%WC10A_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat new file mode 100755 index 0000000..d52b79a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 32-bit DOS compilation environment set up (DOS4GW) diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat new file mode 100755 index 0000000..ba7351d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 16-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os216\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os216\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10A_PATH%\h\os2;%WC10A_PATH%\h +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216=1 +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=wc10 +SET EDPATH=%WC10A_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 16-bit OS/2 compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat new file mode 100755 index 0000000..f3caa59 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10AA_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10AA_PATH%\h\os2;%WC10AA_PATH%\h +SET WATCOM=%WC10AA_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +SET EDPATH=%WC10AA_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10AA_PATH%\BINNT;%WC10AA6_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 32-bit OS/2 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat new file mode 100755 index 0000000..8d21c62 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI=1 +SET USE_SNAP= +SET WC_LIBBASE=WC10A +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 32-bit OS/2 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat b/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat new file mode 100755 index 0000000..28f857c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP=1 +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat new file mode 100755 index 0000000..a2b3219 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat @@ -0,0 +1,45 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT;%TNT_PATH%\INCLUDE +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT=1 +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE=1 + +echo Watcom C/C++ 10.0a 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat new file mode 100755 index 0000000..94011cc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 16 bit Windows mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC10A;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC10A;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\WIN; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +SET EDPATH=%WC10A_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 16-bit Windows compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat new file mode 100755 index 0000000..1e14dbc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a Win32 GUI compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat new file mode 100755 index 0000000..e753129 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET C_INCLUDE=%WC11_PATH%\H;%WC11_PATH%\H\NT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Watcom C/C++ 11.0 Win32 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat new file mode 100755 index 0000000..4338ada --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat @@ -0,0 +1,30 @@ +@echo off +REM SETup for compiling with Watcom C/C++ 11.0 in 16 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\WIN; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat new file mode 100755 index 0000000..e5a54d4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 32-bit DOS compilation environment set up (DOS4GW). diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat new file mode 100755 index 0000000..d46754a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 16-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os216\wc11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os216\wc11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216=1 +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 16-bit OS/2 compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat new file mode 100755 index 0000000..37f5dc7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 32-bit OS/2 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat new file mode 100755 index 0000000..348cbbd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI=1 +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 32-bit OS/2 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat new file mode 100755 index 0000000..1fd60fe --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode (QNX 4) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\QNX4\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\QNX;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\QNX4\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\QNX;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\QH; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4=1 +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 32-bit QNX compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat new file mode 100755 index 0000000..6d2ac57 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP=1 +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 Snap compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat new file mode 100755 index 0000000..44dbf24 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat @@ -0,0 +1,46 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\NT;%TNT_PATH%\INCLUDE +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT=1 +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE=1 + +echo Watcom C/C++ 11.0 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat new file mode 100755 index 0000000..e65c70e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 16 bit Windows mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\WIN; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 16-bit Windows compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat new file mode 100755 index 0000000..764cdbd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET C_INCLUDE=%WC11_PATH%\H;%WC11_PATH%\H\NT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Watcom C/C++ 11.0 Win32 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat new file mode 100755 index 0000000..c2569a3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\NT; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 Win32 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/win32sdk.bat b/board/MAI/bios_emulator/scitech/bin/win32sdk.bat new file mode 100755 index 0000000..3c7f017 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/win32sdk.bat @@ -0,0 +1,20 @@ +@echo off +REM: Set up environment variables for Microsoft Platform SDK development +REM: Note that we have hard coded this for Windows NT i386 development. + +SET MSTOOLS=%MSSDK% +SET DXSDKROOT=%MSTOOLS% +SET INETSDK=%MSTOOLS% +SET BKOFFICE=%MSTOOLS% +SET BASEMAKE=%BKOFFICE%\INCLUDE\BKOffice.Mak +SET INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%MSTOOLS%\INCLUDE;%C_INCLUDE% +if .%1%==.borland goto borland +SET LIB=%MSTOOLS%\LIB;%LIB% +goto notborland +:borland +SET LIB=%MSTOOLS%\LIB\BORLAND;%LIB% +:notborland +SET PATH=%MSTOOLS%\Bin\;%MSTOOLS%\Bin\WinNT;%PATH% +SET CPU=i386 + +echo Microsoft Platform SDK support enbabled. diff --git a/board/MAI/bios_emulator/scitech/include/biosemu.h b/board/MAI/bios_emulator/scitech/include/biosemu.h new file mode 100644 index 0000000..82c33a7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/biosemu.h @@ -0,0 +1,154 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for the real mode x86 BIOS emulator, which is +* used to warmboot any number of VGA compatible PCI/AGP +* controllers under any OS, on any processor family that +* supports PCI. We also allow the user application to call +* real mode BIOS functions and Int 10h functions (including +* the VESA BIOS). +* +****************************************************************************/ + +#ifndef __BIOSEMU_H +#define __BIOSEMU_H + +#include "x86emu.h" +#include "pmapi.h" +#include "pcilib.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/**************************************************************************** +REMARKS: +Data structure used to describe the details specific to a particular VGA +controller. This information is used to allow the VGA controller to be +swapped on the fly within the BIOS emulator. + +HEADER: +biosemu.h + +MEMBERS: +pciInfo - PCI device information block for the controller +BIOSImage - Pointer to a read/write copy of the BIOS image +BIOSImageLen - Length of the BIOS image +LowMem - Copy of key low memory areas +****************************************************************************/ +typedef struct { + PCIDeviceInfo *pciInfo; + void *BIOSImage; + ulong BIOSImageLen; + uchar LowMem[1536]; + } BE_VGAInfo; + +/**************************************************************************** +REMARKS: +Data structure used to describe the details for the BIOS emulator system +environment as used by the X86 emulator library. + +HEADER: +biosemu.h + +MEMBERS: +vgaInfo - VGA BIOS information structure +biosmem_base - Base of the BIOS image +biosmem_limit - Limit of the BIOS image +busmem_base - Base of the VGA bus memory +****************************************************************************/ +typedef struct { + BE_VGAInfo vgaInfo; + ulong biosmem_base; + ulong biosmem_limit; + ulong busmem_base; + } BE_sysEnv; + +/**************************************************************************** +REMARKS: +Structure defining all the BIOS Emulator API functions as exported from +the Binary Portable DLL. +{secret} +****************************************************************************/ +typedef struct { + ulong dwSize; + ibool (PMAPIP BE_init)(u32 debugFlags,int memSize,BE_VGAInfo *info); + void (PMAPIP BE_setVGA)(BE_VGAInfo *info); + void (PMAPIP BE_getVGA)(BE_VGAInfo *info); + void * (PMAPIP BE_mapRealPointer)(uint r_seg,uint r_off); + void * (PMAPIP BE_getVESABuf)(uint *len,uint *rseg,uint *roff); + void (PMAPIP BE_callRealMode)(uint seg,uint off,RMREGS *regs,RMSREGS *sregs); + int (PMAPIP BE_int86)(int intno,RMREGS *in,RMREGS *out); + int (PMAPIP BE_int86x)(int intno,RMREGS *in,RMREGS *out,RMSREGS *sregs); + void * reserved1; + void (PMAPIP BE_exit)(void); + } BE_exports; + +/**************************************************************************** +REMARKS: +Function pointer type for the Binary Portable DLL initialisation entry point. +{secret} +****************************************************************************/ +typedef BE_exports * (PMAPIP BE_initLibrary_t)(PM_imports *PMImp); + +#pragma pack() + +/*---------------------------- Global variables ---------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* {secret} Global BIOS emulator system environment */ +extern BE_sysEnv _BE_env; + +/*-------------------------- Function Prototypes --------------------------*/ + +/* BIOS emulator library entry points */ + +ibool PMAPI BE_init(u32 debugFlags,int memSize,BE_VGAInfo *info); +void PMAPI BE_setVGA(BE_VGAInfo *info); +void PMAPI BE_getVGA(BE_VGAInfo *info); +void PMAPI BE_setDebugFlags(u32 debugFlags); +void * PMAPI BE_mapRealPointer(uint r_seg,uint r_off); +void * PMAPI BE_getVESABuf(uint *len,uint *rseg,uint *roff); +void PMAPI BE_callRealMode(uint seg,uint off,RMREGS *regs,RMSREGS *sregs); +int PMAPI BE_int86(int intno,RMREGS *in,RMREGS *out); +int PMAPI BE_int86x(int intno,RMREGS *in,RMREGS *out,RMSREGS *sregs); +void PMAPI BE_exit(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __BIOSEMU_H */ diff --git a/board/MAI/bios_emulator/scitech/include/event.h b/board/MAI/bios_emulator/scitech/include/event.h new file mode 100644 index 0000000..beeac87 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/event.h @@ -0,0 +1,696 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file for the SciTech cross platform event library +* +****************************************************************************/ + +#ifndef __EVENT_H +#define __EVENT_H + +#include "scitech.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/* 'C' calling conventions always */ + +#define EVTAPI _ASMAPI +#define EVTAPIP _ASMAPIP + +/* Event message masks for keyDown events */ + +#define EVT_ASCIIMASK 0x00FF /* ASCII code of key pressed */ +#define EVT_SCANMASK 0xFF00 /* Scan code of key pressed */ +#define EVT_COUNTMASK 0x7FFF0000L /* Count for KEYREPEAT's */ + +/* Macros to extract values from the message fields */ + +#define EVT_asciiCode(m) ( (uchar) (m & EVT_ASCIIMASK) ) +#define EVT_scanCode(m) ( (uchar) ( (m & EVT_SCANMASK) >> 8 ) ) +#define EVT_repeatCount(m) ( (short) ( (m & EVT_COUNTMASK) >> 16 ) ) + +/**************************************************************************** +REMARKS: +Defines the set of ASCII codes reported by the event library functions +in the message field. Use the EVT_asciiCode macro to extract the code +from the event structure. + +HEADER: +event.h +****************************************************************************/ +typedef enum { + ASCII_ctrlA = 0x01, + ASCII_ctrlB = 0x02, + ASCII_ctrlC = 0x03, + ASCII_ctrlD = 0x04, + ASCII_ctrlE = 0x05, + ASCII_ctrlF = 0x06, + ASCII_ctrlG = 0x07, + ASCII_backspace = 0x08, + ASCII_ctrlH = 0x08, + ASCII_tab = 0x09, + ASCII_ctrlI = 0x09, + ASCII_ctrlJ = 0x0A, + ASCII_ctrlK = 0x0B, + ASCII_ctrlL = 0x0C, + ASCII_enter = 0x0D, + ASCII_ctrlM = 0x0D, + ASCII_ctrlN = 0x0E, + ASCII_ctrlO = 0x0F, + ASCII_ctrlP = 0x10, + ASCII_ctrlQ = 0x11, + ASCII_ctrlR = 0x12, + ASCII_ctrlS = 0x13, + ASCII_ctrlT = 0x14, + ASCII_ctrlU = 0x15, + ASCII_ctrlV = 0x16, + ASCII_ctrlW = 0x17, + ASCII_ctrlX = 0x18, + ASCII_ctrlY = 0x19, + ASCII_ctrlZ = 0x1A, + ASCII_esc = 0x1B, + ASCII_space = 0x20, + ASCII_exclamation = 0x21, /* ! */ + ASCII_quote = 0x22, /* " */ + ASCII_pound = 0x23, /* # */ + ASCII_dollar = 0x24, /* $ */ + ASCII_percent = 0x25, /* % */ + ASCII_ampersand = 0x26, /* & */ + ASCII_apostrophe = 0x27, /* ' */ + ASCII_leftBrace = 0x28, /* ( */ + ASCII_rightBrace = 0x29, /* ) */ + ASCII_times = 0x2A, /* * */ + ASCII_plus = 0x2B, /* + */ + ASCII_comma = 0x2C, /* , */ + ASCII_minus = 0x2D, /* - */ + ASCII_period = 0x2E, /* . */ + ASCII_divide = 0x2F, /* / */ + ASCII_0 = 0x30, + ASCII_1 = 0x31, + ASCII_2 = 0x32, + ASCII_3 = 0x33, + ASCII_4 = 0x34, + ASCII_5 = 0x35, + ASCII_6 = 0x36, + ASCII_7 = 0x37, + ASCII_8 = 0x38, + ASCII_9 = 0x39, + ASCII_colon = 0x3A, /* : */ + ASCII_semicolon = 0x3B, /* ; */ + ASCII_lessThan = 0x3C, /* < */ + ASCII_equals = 0x3D, /* = */ + ASCII_greaterThan = 0x3E, /* > */ + ASCII_question = 0x3F, /* ? */ + ASCII_at = 0x40, /* @ */ + ASCII_A = 0x41, + ASCII_B = 0x42, + ASCII_C = 0x43, + ASCII_D = 0x44, + ASCII_E = 0x45, + ASCII_F = 0x46, + ASCII_G = 0x47, + ASCII_H = 0x48, + ASCII_I = 0x49, + ASCII_J = 0x4A, + ASCII_K = 0x4B, + ASCII_L = 0x4C, + ASCII_M = 0x4D, + ASCII_N = 0x4E, + ASCII_O = 0x4F, + ASCII_P = 0x50, + ASCII_Q = 0x51, + ASCII_R = 0x52, + ASCII_S = 0x53, + ASCII_T = 0x54, + ASCII_U = 0x55, + ASCII_V = 0x56, + ASCII_W = 0x57, + ASCII_X = 0x58, + ASCII_Y = 0x59, + ASCII_Z = 0x5A, + ASCII_leftSquareBrace = 0x5B, /* [ */ + ASCII_backSlash = 0x5C, /* \ */ + ASCII_rightSquareBrace = 0x5D, /* ] */ + ASCII_caret = 0x5E, /* ^ */ + ASCII_underscore = 0x5F, /* _ */ + ASCII_leftApostrophe = 0x60, /* ` */ + ASCII_a = 0x61, + ASCII_b = 0x62, + ASCII_c = 0x63, + ASCII_d = 0x64, + ASCII_e = 0x65, + ASCII_f = 0x66, + ASCII_g = 0x67, + ASCII_h = 0x68, + ASCII_i = 0x69, + ASCII_j = 0x6A, + ASCII_k = 0x6B, + ASCII_l = 0x6C, + ASCII_m = 0x6D, + ASCII_n = 0x6E, + ASCII_o = 0x6F, + ASCII_p = 0x70, + ASCII_q = 0x71, + ASCII_r = 0x72, + ASCII_s = 0x73, + ASCII_t = 0x74, + ASCII_u = 0x75, + ASCII_v = 0x76, + ASCII_w = 0x77, + ASCII_x = 0x78, + ASCII_y = 0x79, + ASCII_z = 0x7A, + ASCII_leftCurlyBrace = 0x7B, /* { */ + ASCII_verticalBar = 0x7C, /* | */ + ASCII_rightCurlyBrace = 0x7D, /* } */ + ASCII_tilde = 0x7E /* ~ */ + } EVT_asciiCodesType; + +/**************************************************************************** +REMARKS: +Defines the set of scan codes reported by the event library functions +in the message field. Use the EVT_scanCode macro to extract the code +from the event structure. Note that the scan codes reported will be the +same across all keyboards (assuming the placement of keys on a 101 key US +keyboard), but the translated ASCII values may be different depending on +the country code pages in use. + +NOTE: Scan codes in the event library are not really hardware scan codes, + but rather virtual scan codes as generated by a low level keyboard + interface driver. All virtual codes begin with scan code 0x60 and + range up from there. + +HEADER: +event.h +****************************************************************************/ +typedef enum { + KB_padEnter = 0x60, /* Keypad keys */ + KB_padMinus = 0x4A, + KB_padPlus = 0x4E, + KB_padTimes = 0x37, + KB_padDivide = 0x61, + KB_padLeft = 0x62, + KB_padRight = 0x63, + KB_padUp = 0x64, + KB_padDown = 0x65, + KB_padInsert = 0x66, + KB_padDelete = 0x67, + KB_padHome = 0x68, + KB_padEnd = 0x69, + KB_padPageUp = 0x6A, + KB_padPageDown = 0x6B, + KB_padCenter = 0x4C, + KB_F1 = 0x3B, /* Function keys */ + KB_F2 = 0x3C, + KB_F3 = 0x3D, + KB_F4 = 0x3E, + KB_F5 = 0x3F, + KB_F6 = 0x40, + KB_F7 = 0x41, + KB_F8 = 0x42, + KB_F9 = 0x43, + KB_F10 = 0x44, + KB_F11 = 0x57, + KB_F12 = 0x58, + KB_left = 0x4B, /* Cursor control keys */ + KB_right = 0x4D, + KB_up = 0x48, + KB_down = 0x50, + KB_insert = 0x52, + KB_delete = 0x53, + KB_home = 0x47, + KB_end = 0x4F, + KB_pageUp = 0x49, + KB_pageDown = 0x51, + KB_capsLock = 0x3A, + KB_numLock = 0x45, + KB_scrollLock = 0x46, + KB_leftShift = 0x2A, + KB_rightShift = 0x36, + KB_leftCtrl = 0x1D, + KB_rightCtrl = 0x6C, + KB_leftAlt = 0x38, + KB_rightAlt = 0x6D, + KB_leftWindows = 0x5B, + KB_rightWindows = 0x5C, + KB_menu = 0x5D, + KB_sysReq = 0x54, + KB_esc = 0x01, /* Normal keyboard keys */ + KB_1 = 0x02, + KB_2 = 0x03, + KB_3 = 0x04, + KB_4 = 0x05, + KB_5 = 0x06, + KB_6 = 0x07, + KB_7 = 0x08, + KB_8 = 0x09, + KB_9 = 0x0A, + KB_0 = 0x0B, + KB_minus = 0x0C, + KB_equals = 0x0D, + KB_backSlash = 0x2B, + KB_backspace = 0x0E, + KB_tab = 0x0F, + KB_Q = 0x10, + KB_W = 0x11, + KB_E = 0x12, + KB_R = 0x13, + KB_T = 0x14, + KB_Y = 0x15, + KB_U = 0x16, + KB_I = 0x17, + KB_O = 0x18, + KB_P = 0x19, + KB_leftSquareBrace = 0x1A, + KB_rightSquareBrace = 0x1B, + KB_enter = 0x1C, + KB_A = 0x1E, + KB_S = 0x1F, + KB_D = 0x20, + KB_F = 0x21, + KB_G = 0x22, + KB_H = 0x23, + KB_J = 0x24, + KB_K = 0x25, + KB_L = 0x26, + KB_semicolon = 0x27, + KB_apostrophe = 0x28, + KB_Z = 0x2C, + KB_X = 0x2D, + KB_C = 0x2E, + KB_V = 0x2F, + KB_B = 0x30, + KB_N = 0x31, + KB_M = 0x32, + KB_comma = 0x33, + KB_period = 0x34, + KB_divide = 0x35, + KB_space = 0x39, + KB_tilde = 0x29 + } EVT_scanCodesType; + +/**************************************************************************** +REMARKS: +Defines the mask for the joystick axes that are present + +HEADER: +event.h + +MEMBERS: +EVT_JOY_AXIS_X1 - Joystick 1, X axis is present +EVT_JOY_AXIS_Y1 - Joystick 1, Y axis is present +EVT_JOY_AXIS_X2 - Joystick 2, X axis is present +EVT_JOY_AXIS_Y2 - Joystick 2, Y axis is present +EVT_JOY_AXIS_ALL - Mask for all axes +****************************************************************************/ +typedef enum { + EVT_JOY_AXIS_X1 = 0x00000001, + EVT_JOY_AXIS_Y1 = 0x00000002, + EVT_JOY_AXIS_X2 = 0x00000004, + EVT_JOY_AXIS_Y2 = 0x00000008, + EVT_JOY_AXIS_ALL = 0x0000000F + } EVT_eventJoyAxisType; + +/**************************************************************************** +REMARKS: +Defines the event message masks for joystick events + +HEADER: +event.h + +MEMBERS: +EVT_JOY1_BUTTONA - Joystick 1, button A is down +EVT_JOY1_BUTTONB - Joystick 1, button B is down +EVT_JOY2_BUTTONA - Joystick 2, button A is down +EVT_JOY2_BUTTONB - Joystick 2, button B is down +****************************************************************************/ +typedef enum { + EVT_JOY1_BUTTONA = 0x00000001, + EVT_JOY1_BUTTONB = 0x00000002, + EVT_JOY2_BUTTONA = 0x00000004, + EVT_JOY2_BUTTONB = 0x00000008 + } EVT_eventJoyMaskType; + +/**************************************************************************** +REMARKS: +Defines the event message masks for mouse events + +HEADER: +event.h + +MEMBERS: +EVT_LEFTBMASK - Left button is held down +EVT_RIGHTBMASK - Right button is held down +EVT_MIDDLEBMASK - Middle button is held down +EVT_BOTHBMASK - Both left and right held down together +EVT_ALLBMASK - All buttons pressed +EVT_DBLCLICK - Set if mouse down event was a double click +****************************************************************************/ +typedef enum { + EVT_LEFTBMASK = 0x00000001, + EVT_RIGHTBMASK = 0x00000002, + EVT_MIDDLEBMASK = 0x00000004, + EVT_BOTHBMASK = 0x00000007, + EVT_ALLBMASK = 0x00000007, + EVT_DBLCLICK = 0x00010000 + } EVT_eventMouseMaskType; + +/**************************************************************************** +REMARKS: +Defines the event modifier masks. These are the masks used to extract +the modifier information from the modifiers field of the event_t structure. +Note that the values in the modifiers field represent the values of these +modifier keys at the time the event occurred, not the time you decided +to process the event. + +HEADER: +event.h + +MEMBERS: +EVT_LEFTBUT - Set if left mouse button was down +EVT_RIGHTBUT - Set if right mouse button was down +EVT_MIDDLEBUT - Set if the middle button was down +EVT_RIGHTSHIFT - Set if right shift was down +EVT_LEFTSHIFT - Set if left shift was down +EVT_RIGHTCTRL - Set if right ctrl key was down +EVT_RIGHTALT - Set if right alt key was down +EVT_LEFTCTRL - Set if left ctrl key was down +EVT_LEFTALT - Set if left alt key was down +EVT_SHIFTKEY - Mask for any shift key down +EVT_CTRLSTATE - Set if ctrl key was down +EVT_ALTSTATE - Set if alt key was down +EVT_CAPSLOCK - Caps lock is active +EVT_NUMLOCK - Num lock is active +EVT_SCROLLLOCK - Scroll lock is active +****************************************************************************/ +typedef enum { + EVT_LEFTBUT = 0x00000001, + EVT_RIGHTBUT = 0x00000002, + EVT_MIDDLEBUT = 0x00000004, + EVT_RIGHTSHIFT = 0x00000008, + EVT_LEFTSHIFT = 0x00000010, + EVT_RIGHTCTRL = 0x00000020, + EVT_RIGHTALT = 0x00000040, + EVT_LEFTCTRL = 0x00000080, + EVT_LEFTALT = 0x00000100, + EVT_SHIFTKEY = 0x00000018, + EVT_CTRLSTATE = 0x000000A0, + EVT_ALTSTATE = 0x00000140, + EVT_SCROLLLOCK = 0x00000200, + EVT_NUMLOCK = 0x00000400, + EVT_CAPSLOCK = 0x00000800 + } EVT_eventModMaskType; + +/**************************************************************************** +REMARKS: +Defines the event codes returned in the event_t structures what field. Note +that these are defined as a set of mutually exlusive bit fields, so you +can test for multiple event types using the combined event masks defined +in the EVT_eventMaskType enumeration. + +HEADER: +event.h + +MEMBERS: +EVT_NULLEVT - A null event +EVT_KEYDOWN - Key down event +EVT_KEYREPEAT - Key repeat event +EVT_KEYUP - Key up event +EVT_MOUSEDOWN - Mouse down event +EVT_MOUSEAUTO - Mouse down autorepeat event +EVT_MOUSEUP - Mouse up event +EVT_MOUSEMOVE - Mouse movement event +EVT_JOYCLICK - Joystick button state change event +EVT_JOYMOVE - Joystick movement event +EVT_USEREVT - First user event +****************************************************************************/ +typedef enum { + EVT_NULLEVT = 0x00000000, + EVT_KEYDOWN = 0x00000001, + EVT_KEYREPEAT = 0x00000002, + EVT_KEYUP = 0x00000004, + EVT_MOUSEDOWN = 0x00000008, + EVT_MOUSEAUTO = 0x00000010, + EVT_MOUSEUP = 0x00000020, + EVT_MOUSEMOVE = 0x00000040, + EVT_JOYCLICK = 0x00000080, + EVT_JOYMOVE = 0x00000100, + EVT_USEREVT = 0x00000200 + } EVT_eventType; + +/**************************************************************************** +REMARKS: +Defines the event code masks you can use to test for multiple types of +events, since the event codes are mutually exlusive bit fields. + +HEADER: +event.h + +MEMBERS: +EVT_KEYEVT - Mask for any key event +EVT_MOUSEEVT - Mask for any mouse event +EVT_MOUSECLICK - Mask for any mouse click event +EVT_JOYEVT - Mask for any joystick event +EVT_EVERYEVT - Mask for any event +****************************************************************************/ +typedef enum { + EVT_KEYEVT = (EVT_KEYDOWN | EVT_KEYREPEAT | EVT_KEYUP), + EVT_MOUSEEVT = (EVT_MOUSEDOWN | EVT_MOUSEAUTO | EVT_MOUSEUP | EVT_MOUSEMOVE), + EVT_MOUSECLICK = (EVT_MOUSEDOWN | EVT_MOUSEUP), + EVT_JOYEVT = (EVT_JOYCLICK | EVT_JOYMOVE), + EVT_EVERYEVT = 0x7FFFFFFF + } EVT_eventMaskType; + +/**************************************************************************** +REMARKS: +Structure describing the information contained in an event extracted from +the event queue. + +HEADER: +event.h + +MEMBERS: +which - Window identifier for message for use by high level window manager + code (i.e. MegaVision GUI or Windows API). +what - Type of event that occurred. Will be one of the values defined by + the EVT_eventType enumeration. +when - Time that the event occurred in milliseconds since startup +where_x - X coordinate of the mouse cursor location at the time of the event + (in screen coordinates). For joystick events this represents + the position of the first joystick X axis. +where_y - Y coordinate of the mouse cursor location at the time of the event + (in screen coordinates). For joystick events this represents + the position of the first joystick Y axis. +relative_x - Relative movement of the mouse cursor in the X direction (in + units of mickeys, or 1/200th of an inch). For joystick events + this represents the position of the second joystick X axis. +relative_y - Relative movement of the mouse cursor in the Y direction (in + units of mickeys, or 1/200th of an inch). For joystick events + this represents the position of the second joystick Y axis. +message - Event specific message for the event. For use events this can be + any user specific information. For keyboard events this contains + the ASCII code in bits 0-7, the keyboard scan code in bits 8-15 and + the character repeat count in bits 16-30. You can use the + EVT_asciiCode, EVT_scanCode and EVT_repeatCount macros to extract + this information from the message field. For mouse events this + contains information about which button was pressed, and will be a + combination of the flags defined by the EVT_eventMouseMaskType + enumeration. For joystick events, this conatins information + about which buttons were pressed, and will be a combination of + the flags defined by the EVT_eventJoyMaskType enumeration. +modifiers - Contains additional information about the state of the keyboard + shift modifiers (Ctrl, Alt and Shift keys) when the event + occurred. For mouse events it will also contain the state of + the mouse buttons. Will be a combination of the values defined + by the EVT_eventModMaskType enumeration. +next - Internal use; do not use. +prev - Internal use; do not use. +****************************************************************************/ +typedef struct { + ulong which; + ulong what; + ulong when; + int where_x; + int where_y; + int relative_x; + int relative_y; + ulong message; + ulong modifiers; + int next; + int prev; + } event_t; + +/**************************************************************************** +REMARKS: +Structure describing an entry in the code page table. A table of translation +codes for scan codes to ASCII codes is provided in this table to be used +by the keyboard event libraries. On some OS'es the keyboard translation is +handled by the OS, but for DOS and embedded systems you must register a +different code page translation table if you want to support keyboards +other than the US English keyboard (the default). + +NOTE: Entries in code page tables *must* be in ascending order for the + scan codes as we do a binary search on the tables for the ASCII + code equivalents. + +HEADER: +event.h + +MEMBERS: +scanCode - Scan code to translate (really the virtual scan code). +asciiCode - ASCII code for this scan code. +****************************************************************************/ +typedef struct { + uchar scanCode; + uchar asciiCode; + } codepage_entry_t; + +/**************************************************************************** +REMARKS: +Structure describing a complete code page translation table. The table +contains translation tables for normal keys, shifted keys and ctrl keys. +The Ctrl key always has precedence over the shift table, and the shift +table is used when the shift key is down or the CAPSLOCK key is down. + +HEADER: +event.h + +MEMBERS: +name - Name of the code page table (ie: "US English") +normal - Code page for translating normal keys +normalLen - Length of normal translation table +caps - Code page for translating keys when CAPSLOCK is down +capsLen - Length of CAPSLOCK translation table +shift - Code page for shifted keys (ie: shift key is held down) +shiftLen - Length of shifted translation table +shiftCaps - Code page for shifted keys when CAPSLOCK is down +shiftCapsLen - Length of shifted CAPSLOCK translation table +ctrl - Code page for ctrl'ed keys (ie: ctrl key is held down) +ctrlLen - Length of ctrl'ed translation table +numPad - Code page for NUMLOCK'ed keypad keys +numPadLen - Length of NUMLOCK'ed translation table +****************************************************************************/ +typedef struct { + char name[20]; + codepage_entry_t *normal; + int normalLen; + codepage_entry_t *caps; + int capsLen; + codepage_entry_t *shift; + int shiftLen; + codepage_entry_t *shiftCaps; + int shiftCapsLen; + codepage_entry_t *ctrl; + int ctrlLen; + codepage_entry_t *numPad; + int numPadLen; + } codepage_t; + +/* {secret} */ +typedef ibool (EVTAPIP _EVT_userEventFilter)(event_t *evt); +/* {secret} */ +typedef void (EVTAPIP _EVT_mouseMoveHandler)(int x,int y); +/* {secret} */ +typedef void (EVTAPIP _EVT_heartBeatCallback)(void *params); + +/* Macro to find the size of a static array */ + +#define EVT_ARR_SIZE(a) (sizeof(a)/sizeof((a)[0])) + +#pragma pack() + +/*--------------------------- Global variables ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Standard code page tables */ + +extern codepage_t _CP_US_English; + +/*------------------------- Function Prototypes ---------------------------*/ + +/* Public API functions for user applications */ + +ibool EVTAPI EVT_getNext(event_t *evt,ulong mask); +ibool EVTAPI EVT_peekNext(event_t *evt,ulong mask); +ibool EVTAPI EVT_post(ulong which,ulong what,ulong message,ulong modifiers); +void EVTAPI EVT_flush(ulong mask); +void EVTAPI EVT_halt(event_t *evt,ulong mask); +ibool EVTAPI EVT_isKeyDown(uchar scanCode); +void EVTAPI EVT_setMousePos(int x,int y); +void EVTAPI EVT_getMousePos(int *x,int *y); + +/* Function to enable/disable updating of keyboard LED status indicators */ + +void EVTAPI EVT_allowLEDS(ibool enable); + +/* Function to install a custom keyboard code page. Default is US English */ + +codepage_t *EVTAPI EVT_getCodePage(void); +void EVTAPI EVT_setCodePage(codepage_t *page); + +/* Functions for fine grained joystick calibration */ + +void EVTAPI EVT_pollJoystick(void); +int EVTAPI EVT_joyIsPresent(void); +void EVTAPI EVT_joySetUpperLeft(void); +void EVTAPI EVT_joySetLowerRight(void); +void EVTAPI EVT_joySetCenter(void); + +/* Install user supplied event filter callback */ + +void EVTAPI EVT_setUserEventFilter(_EVT_userEventFilter filter); + +/* Install user supplied event heartbeat callback function */ + +void EVTAPI EVT_setHeartBeatCallback(_EVT_heartBeatCallback callback,void *params); +void EVTAPI EVT_getHeartBeatCallback(_EVT_heartBeatCallback *callback,void **params); + +/* Internal functions to initialise and kill the event manager. MGL + * applications should never call these functions directly as the MGL + * libraries do it for you. + */ + +/* {secret} */ +void EVTAPI EVT_init(_EVT_mouseMoveHandler mouseMove); +/* {secret} */ +void EVTAPI EVT_setMouseRange(int xRes,int yRes); +/* {secret} */ +void EVTAPI EVT_suspend(void); +/* {secret} */ +void EVTAPI EVT_resume(void); +/* {secret} */ +void EVTAPI EVT_exit(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif /* __cplusplus */ + +#endif /* __EVENT_H */ diff --git a/board/MAI/bios_emulator/scitech/include/mtrr.h b/board/MAI/bios_emulator/scitech/include/mtrr.h new file mode 100644 index 0000000..b29812c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/mtrr.h @@ -0,0 +1,72 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Include file defining the external ring 0 helper functions +* needed by the MTRR module. These functions may be included +* directly for native ring 0 device drivers, or they may +* be calls down to a ring 0 helper device driver where +* appropriate (or the entire MTRR module may be located in +* the device driver if the device driver is 32-bit). +* +****************************************************************************/ + +#ifndef __MTRR_H +#define __MTRR_H + +#include "scitech.h" + +/*--------------------------- Function Prototypes -------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Internal functions (requires ring 0 access or helper functions!) */ + +void MTRR_init(void); +int MTRR_enableWriteCombine(ulong base,ulong size,uint type); + +/* External assembler helper functions */ + +ibool _ASMAPI _MTRR_isRing0(void); +ulong _ASMAPI _MTRR_disableInt(void); +void _ASMAPI _MTRR_restoreInt(ulong flags); +ulong _ASMAPI _MTRR_saveCR4(void); +void _ASMAPI _MTRR_restoreCR4(ulong cr4Val); +uchar _ASMAPI _MTRR_getCx86(uchar reg); +void _ASMAPI _MTRR_setCx86(uchar reg,uchar data); +#ifdef __16BIT__ +void _ASMAPI _MTRR_readMSR(ulong reg, ulong far *eax, ulong far *edx); +#else +void _ASMAPI _MTRR_readMSR(ulong reg, ulong *eax, ulong *edx); +#endif +void _ASMAPI _MTRR_writeMSR(ulong reg, ulong eax, ulong edx); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __MTRR_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pcilib.h b/board/MAI/bios_emulator/scitech/include/pcilib.h new file mode 100644 index 0000000..238f8ef --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pcilib.h @@ -0,0 +1,413 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file for interface routines to the PCI bus. +* +****************************************************************************/ + +#ifndef __PCILIB_H +#define __PCILIB_H + +#include "scitech.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/* Defines for PCIDeviceInfo.HeaderType */ + +typedef enum { + PCI_deviceType = 0x00, + PCI_bridgeType = 0x01, + PCI_cardBusBridgeType = 0x02, + PCI_multiFunctionType = 0x80 + } PCIHeaderTypeFlags; + +/* Defines for PCIDeviceInfo.Command */ + +typedef enum { + PCI_enableIOSpace = 0x0001, + PCI_enableMemorySpace = 0x0002, + PCI_enableBusMaster = 0x0004, + PCI_enableSpecialCylces = 0x0008, + PCI_enableWriteAndInvalidate = 0x0010, + PCI_enableVGACompatiblePalette = 0x0020, + PCI_enableParity = 0x0040, + PCI_enableWaitCycle = 0x0080, + PCI_enableSerr = 0x0100, + PCI_enableFastBackToBack = 0x0200 + } PCICommandFlags; + +/* Defines for PCIDeviceInfo.Status */ + +typedef enum { + PCI_statusCapabilitiesList = 0x0010, + PCI_status66MhzCapable = 0x0020, + PCI_statusUDFSupported = 0x0040, + PCI_statusFastBackToBack = 0x0080, + PCI_statusDataParityDetected = 0x0100, + PCI_statusDevSel = 0x0600, + PCI_statusSignaledTargetAbort = 0x0800, + PCI_statusRecievedTargetAbort = 0x1000, + PCI_statusRecievedMasterAbort = 0x2000, + PCI_statusSignaledSystemError = 0x4000, + PCI_statusDetectedParityError = 0x8000 + } PCIStatusFlags; + +/* PCI capability IDs */ + +typedef enum { + PCI_capsPowerManagement = 0x01, + PCI_capsAGP = 0x02, + PCI_capsMSI = 0x05 + } PCICapsType; + +/* PCI AGP rate definitions */ + +typedef enum { + PCI_AGPRate1X = 0x1, + PCI_AGPRate2X = 0x2, + PCI_AGPRate4X = 0x4 + } PCIAGPRateType; + +/* NOTE: We define all bitfield's as uint's, specifically so that the IBM + * Visual Age C++ compiler does not complain. We need them to be + * 32-bits wide, and this is the width of an unsigned integer, but + * we can't use a ulong to make this explicit or we get errors. + */ + +/* Structure defining a PCI slot identifier */ + +typedef union { + struct { + uint Zero:2; + uint Register:6; + uint Function:3; + uint Device:5; + uint Bus:8; + uint Reserved:7; + uint Enable:1; + } p; + ulong i; + } PCIslot; + +/* Structure defining the regular (type 0) PCI configuration register + * layout. We use this in a union below so we can describe all types of + * PCI configuration spaces with a single structure. + */ + +typedef struct { + ulong BaseAddress10; + ulong BaseAddress14; + ulong BaseAddress18; + ulong BaseAddress1C; + ulong BaseAddress20; + ulong BaseAddress24; + ulong CardbusCISPointer; + ushort SubSystemVendorID; + ushort SubSystemID; + ulong ROMBaseAddress; + uchar CapabilitiesPointer; + uchar reserved1; + uchar reserved2; + uchar reserved3; + ulong reserved4; + uchar InterruptLine; + uchar InterruptPin; + uchar MinimumGrant; + uchar MaximumLatency; + + /* These are not in the actual config space, but we enumerate them */ + ulong BaseAddress10Len; + ulong BaseAddress14Len; + ulong BaseAddress18Len; + ulong BaseAddress1CLen; + ulong BaseAddress20Len; + ulong BaseAddress24Len; + ulong ROMBaseAddressLen; + } PCIType0Info; + +/* Structure defining PCI to PCI bridge (type 1) PCI configuration register + * layout. We use this in a union below so we can describe all types of + * PCI configuration spaces with a single structure. + */ + +typedef struct { + ulong BaseAddress10; + ulong BaseAddress14; + uchar PrimaryBusNumber; + uchar SecondayBusNumber; + uchar SubordinateBusNumber; + uchar SecondaryLatencyTimer; + uchar IOBase; + uchar IOLimit; + ushort SecondaryStatus; + ushort MemoryBase; + ushort MemoryLimit; + ushort PrefetchableMemoryBase; + ushort PrefetchableMemoryLimit; + ulong PrefetchableBaseHi; + ulong PrefetchableLimitHi; + ushort IOBaseHi; + ushort IOLimitHi; + uchar CapabilitiesPointer; + uchar reserved1; + uchar reserved2; + uchar reserved3; + ulong ROMBaseAddress; + uchar InterruptLine; + uchar InterruptPin; + ushort BridgeControl; + } PCIType1Info; + +/* PCI to CardBus bridge (type 2) configuration information */ +typedef struct { + ulong SocketRegistersBaseAddress; + uchar CapabilitiesPointer; + uchar reserved1; + ushort SecondaryStatus; + uchar PrimaryBus; + uchar SecondaryBus; + uchar SubordinateBus; + uchar SecondaryLatency; + struct { + ulong Base; + ulong Limit; + } Range[4]; + uchar InterruptLine; + uchar InterruptPin; + ushort BridgeControl; + } PCIType2Info; + +/* Structure defining the PCI configuration space information for a + * single PCI device on the PCI bus. We enumerate all this information + * for all PCI devices on the bus. + */ + +typedef struct { + ulong dwSize; + PCIslot slot; + ulong mech1; + ushort VendorID; + ushort DeviceID; + ushort Command; + ushort Status; + uchar RevID; + uchar Interface; + uchar SubClass; + uchar BaseClass; + uchar CacheLineSize; + uchar LatencyTimer; + uchar HeaderType; + uchar BIST; + union { + PCIType0Info type0; + PCIType1Info type1; + PCIType2Info type2; + } u; + } PCIDeviceInfo; + +/* PCI Capability header structure. All PCI capabilities have the + * following header. + * + * capsID is used to identify the type of the structure as define above. + * + * next is the offset in PCI configuration space (0x40-0xFC) of the + * next capability structure in the list, or 0x00 if there are no more + * entries. + */ + +typedef struct { + uchar capsID; + uchar next; + } PCICapsHeader; + +/* Structure defining the PCI AGP status register contents */ + +typedef struct { + uint rate:3; + uint rsvd1:1; + uint fastWrite:1; + uint fourGB:1; + uint rsvd2:3; + uint sideBandAddressing:1; + uint rsvd3:14; + uint requestQueueDepthMaximum:8; + } PCIAGPStatus; + +/* Structure defining the PCI AGP command register contents */ + +typedef struct { + uint rate:3; + uint rsvd1:1; + uint fastWriteEnable:1; + uint fourGBEnable:1; + uint rsvd2:2; + uint AGPEnable:1; + uint SBAEnable:1; + uint rsvd3:14; + uint requestQueueDepth:8; + } PCIAGPCommand; + +/* AGP Capability structure */ + +typedef struct { + PCICapsHeader h; + ushort majMin; + PCIAGPStatus AGPStatus; + PCIAGPCommand AGPCommand; + } PCIAGPCapability; + +/* Structure for obtaining the PCI IRQ routing information */ + +typedef struct { + uchar bus; + uchar device; + uchar linkA; + ushort mapA; + uchar linkB; + ushort mapB; + uchar linkC; + ushort mapC; + uchar linkD; + ushort mapD; + uchar slot; + uchar reserved; + } PCIRouteInfo; + +typedef struct { + ushort BufferSize; + PCIRouteInfo *DataBuffer; + } PCIRoutingOptionsBuffer; + +#define NUM_PCI_REG (sizeof(PCIDeviceInfo) / 4) - 10 +#define PCI_BRIDGE_CLASS 0x06 +#define PCI_HOST_BRIDGE_SUBCLASS 0x00 +#define PCI_EARLY_VGA_CLASS 0x00 +#define PCI_EARLY_VGA_SUBCLASS 0x01 +#define PCI_DISPLAY_CLASS 0x03 +#define PCI_DISPLAY_VGA_SUBCLASS 0x00 +#define PCI_DISPLAY_XGA_SUBCLASS 0x01 +#define PCI_DISPLAY_OTHER_SUBCLASS 0x80 +#define PCI_MM_CLASS 0x04 +#define PCI_AUDIO_SUBCLASS 0x01 + +/* Macros to detect specific classes of devices */ + +#define PCI_IS_3DLABS_NONVGA_CLASS(pci) \ + (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_OTHER_SUBCLASS) \ + && ((pci)->VendorID == 0x3D3D || (pci)->VendorID == 0x104C)) + +#define PCI_IS_DISPLAY_CLASS(pci) \ + (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_VGA_SUBCLASS) \ + || ((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_XGA_SUBCLASS) \ + || ((pci)->BaseClass == PCI_EARLY_VGA_CLASS && (pci)->SubClass == PCI_EARLY_VGA_SUBCLASS) \ + || PCI_IS_3DLABS_NONVGA_CLASS(pci)) + +/* Function codes to pass to PCI_accessReg */ + +#define PCI_READ_BYTE 0 +#define PCI_READ_WORD 1 +#define PCI_READ_DWORD 2 +#define PCI_WRITE_BYTE 3 +#define PCI_WRITE_WORD 4 +#define PCI_WRITE_DWORD 5 + +/* Macros to read/write PCI registers. These assume a global PCI array + * of device information. + */ + +#define PCI_readPCIRegB(index,device) \ + PCI_accessReg(index,0,0,&PCI[DeviceIndex[device]]) + +#define PCI_readPCIRegW(index,device) \ + PCI_accessReg(index,0,1,&PCI[DeviceIndex[device]]) + +#define PCI_readPCIRegL(index,device) \ + PCI_accessReg(index,0,2,&PCI[DeviceIndex[device]]) + +#define PCI_writePCIRegB(index,value,device) \ + PCI_accessReg(index,value,3,&PCI[DeviceIndex[device]]) + +#define PCI_writePCIRegW(index,value,device) \ + PCI_accessReg(index,value,4,&PCI[DeviceIndex[device]]) + +#define PCI_writePCIRegL(index,value,device) \ + PCI_accessReg(index,value,5,&PCI[DeviceIndex[device]]) + +#pragma pack() + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Function to determine the number of PCI devices in the system */ + +int _ASMAPI PCI_getNumDevices(void); + +/* Function to enumerate all device on the PCI bus */ + +int _ASMAPI PCI_enumerate(PCIDeviceInfo info[]); + +/* Function to access PCI configuration registers */ + +ulong _ASMAPI PCI_accessReg(int index,ulong value,int func,PCIDeviceInfo *info); + +/* Function to get PCI IRQ routing options for a card */ + +int _ASMAPI PCI_getIRQRoutingOptions(int numDevices,PCIRouteInfo *buffer); + +/* Function to re-route the PCI IRQ setting for a device */ + +ibool _ASMAPI PCI_setHardwareIRQ(PCIDeviceInfo *info,uint intPin,uint IRQ); + +/* Function to generate a special cyle on the specified PCI bus */ + +void _ASMAPI PCI_generateSpecialCyle(uint bus,ulong specialCycleData); + +/* Function to determine the size of a PCI base address register */ + +ulong _ASMAPI PCI_findBARSize(int bar,PCIDeviceInfo *pci); + +/* Function to read a block of PCI configuration space registers */ + +void _ASMAPI PCI_readRegBlock(PCIDeviceInfo *info,int index,void *dst,int count); + +/* Function to write a block of PCI configuration space registers */ + +void _ASMAPI PCI_writeRegBlock(PCIDeviceInfo *info,int index,void *src,int count); + +/* Function to return the 32-bit PCI BIOS entry point */ + +ulong _ASMAPI PCIBIOS_getEntry(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __PCILIB_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pm_help.h b/board/MAI/bios_emulator/scitech/include/pm_help.h new file mode 100644 index 0000000..536a2ba --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pm_help.h @@ -0,0 +1,166 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32, OS/2 +* +* Description: Include file for the SciTech Portability Manager 32-bit +* helper VxD for Windows 9x for and the 16-bit ring 0 +* helper device driver for OS/2. +* +* This file documents all the public services used by the +* SciTech Portability Manager library and SciTech Nucleus +* loader library. +* +****************************************************************************/ + +#ifndef __PMHELP_H +#define __PMHELP_H + +/* Include version information */ + +#include "sdd/sddver.h" +#define PMHELP_Major SDD_RELEASE_MAJOR +#define PMHELP_Minor SDD_RELEASE_MINOR +#define PMHELP_VERSION ((PMHELP_Major << 8) | PMHELP_Minor) + +#ifdef __OS2__ + +/**************************************************************************** +* Public OS/2 Support functions +****************************************************************************/ + +#include "scitech.h" +#include "nucleus/graphics.h" + +/* Name of device driver */ + +#define PMHELP_NAME (PSZ)"sddhelp$" + +/* Main IOCTL function to talk to device driver */ + +#define PMHELP_IOCTL 0x0080 + +/* Macro definition for defining IOCTL function control codes for the SDDHELP + * device driver for OS/2. Similar to that used for the DOS/Win32 version. + */ + +#define PMHELP_CTL_CODE(name,value) \ + PMHELP_##name = value + +typedef enum { + /* Version function used by all drivers */ + PMHELP_CTL_CODE(GETVER ,0x0001), + PMHELP_CTL_CODE(MAPPHYS ,0x0002), + PMHELP_CTL_CODE(ALLOCLOCKED ,0x0003), + PMHELP_CTL_CODE(FREELOCKED ,0x0004), + PMHELP_CTL_CODE(GETGDT32 ,0x0005), + PMHELP_CTL_CODE(MALLOCSHARED ,0x0007), + PMHELP_CTL_CODE(FREESHARED ,0x0008), + PMHELP_CTL_CODE(MAPTOPROCESS ,0x0009), + PMHELP_CTL_CODE(FREEPHYS ,0x000A), + PMHELP_CTL_CODE(FLUSHTLB ,0x000B), + PMHELP_CTL_CODE(SAVECR4 ,0x000C), + PMHELP_CTL_CODE(RESTORECR4 ,0x000D), + PMHELP_CTL_CODE(READMSR ,0x000E), + PMHELP_CTL_CODE(WRITEMSR ,0x000F), + PMHELP_CTL_CODE(GETPHYSICALADDR ,0x0010), + PMHELP_CTL_CODE(GETPHYSICALADDRRANGE ,0x0011), + PMHELP_CTL_CODE(LOCKPAGES ,0x0012), + PMHELP_CTL_CODE(UNLOCKPAGES ,0x0013), + PMHELP_CTL_CODE(GETSHAREDEXP ,0x0042), + PMHELP_CTL_CODE(SETSHAREDEXP ,0x0043), + PMHELP_CTL_CODE(GETSTACKSWITCHRTN ,0x0044), + PMHELP_CTL_CODE(GETBUILDNO ,0x0050), + } PMHELP_ctlCodes; + +#else + +/**************************************************************************** +* Public DOS/Windows Support functions +****************************************************************************/ + +#ifdef DEVICE_MAIN +#include +#define PMHELP_Init_Order (VDD_INIT_ORDER-1) +#define RETURN_LONGS(n) *p->dioc_bytesret = (n) * sizeof(ulong) +#endif /* DEVICE_MAIN */ +#include "scitech.h" +#include "nucleus/graphics.h" + +/* We connect to the SDDHELP.VXD module if it is staticly loaded (as part + * of SciTech Display Doctor), otherwise we dynamically load the PMHELP.VXD + * public helper VxD. + */ + +#define PMHELP_DeviceID 0x0000 +#define SDDHELP_DeviceID 0x3DF8 +#define VXDLDR_DeviceID 0x0027 +#define SDDHELP_MODULE "SDDHELP" +#define SDDHELP_NAME "SDDHELP.VXD" +#define PMHELP_MODULE "PMHELP" +#define PMHELP_NAME "PMHELP.VXD" +#define PMHELP_DDBNAME "pmhelp " +#define SDDHELP_MODULE_PATH "\\\\.\\" SDDHELP_MODULE +#define PMHELP_MODULE_PATH "\\\\.\\" PMHELP_MODULE +#define PMHELP_VXD_PATH "\\\\.\\" PMHELP_NAME + +/* Macro definition for defining IOCTL function control codes for the PMHELP + * device drivers for Windows 9x and NT. This macro is basically derived from + * the CTL_CODE macro in the Windows 2000 DDK, but we hard code it here to + * avoid having to #include any of the Windows 2000 DDK header files. We also + * define both a 16-bit and 32-bit version of the control code within the same + * macro to simplify future additions. + * + * Essentially the Win32 macro would normally expand to the following: + * + * CTL_CODE(FILE_DEVICE_VIDEO,0x800+value,METHOD_BUFFERED,FILE_ANY_ACCESS) + */ + +#define PMHELP_CTL_CODE(name,value) \ + PMHELP_##name = value, \ + PMHELP_##name##32 = ((0x23 << 16) | (0 << 14) | ((0x800+value) << 2) | (0)) + +typedef enum { + /* Include all the control codes. We keep them in a separate header + * file so we can include them in multiple places to make this + * more versatile. + */ + #include "pm_wctl.h" + } PMHELP_ctlCodes; + +/* For real mode VxD calls, we put the function number into the high + * order word of EAX, and a value of 0x4FFF in AX. This allows our + * VxD handler which is set up to handle Int 10's to recognise a native + * PMHELP API call from a real mode DOS program. + */ + +#ifdef REALMODE +#define API_NUM(num) (((ulong)(num) << 16) | 0x4FFF) +#else +#define API_NUM(num) (num) +#endif + +#endif /* !__OS2__ */ + +#endif /* __PMHELP_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pm_wctl.h b/board/MAI/bios_emulator/scitech/include/pm_wctl.h new file mode 100644 index 0000000..20aa15e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pm_wctl.h @@ -0,0 +1,75 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32, OS/2 +* +* Description: Header file to define all the control codes for the DOS +* and Win32 device driver API's for calling from ring 3 +* into the ring 0 device drivers. +* +****************************************************************************/ + +/* Version function used by all drivers */ +PMHELP_CTL_CODE(GETVER ,0x0000), + +/* Functions used by obsolete 16-bit DOS TSR */ +PMHELP_CTL_CODE(RDREGB ,0x0003), +PMHELP_CTL_CODE(WRREGB ,0x0004), +PMHELP_CTL_CODE(RDREGW ,0x0005), +PMHELP_CTL_CODE(WRREGW ,0x0006), +PMHELP_CTL_CODE(RDREGL ,0x0008), +PMHELP_CTL_CODE(WRREGL ,0x0009), + +/* Functions used by obsolete WinDirect */ +PMHELP_CTL_CODE(MAPPHYS ,0x000F), +PMHELP_CTL_CODE(GETVESABUF ,0x0013), + +/* Functions used by PM library */ +PMHELP_CTL_CODE(DPMIINT86 ,0x0014), +PMHELP_CTL_CODE(INT86 ,0x0015), +PMHELP_CTL_CODE(INT86X ,0x0016), +PMHELP_CTL_CODE(CALLREALMODE ,0x0017), +PMHELP_CTL_CODE(ALLOCLOCKED ,0x0018), +PMHELP_CTL_CODE(FREELOCKED ,0x0019), +PMHELP_CTL_CODE(ENABLELFBCOMB ,0x001A), +PMHELP_CTL_CODE(GETPHYSICALADDR ,0x001B), +PMHELP_CTL_CODE(MALLOCSHARED ,0x001D), +PMHELP_CTL_CODE(FREESHARED ,0x001F), +PMHELP_CTL_CODE(LOCKDATAPAGES ,0x0020), +PMHELP_CTL_CODE(UNLOCKDATAPAGES ,0x0021), +PMHELP_CTL_CODE(LOCKCODEPAGES ,0x0022), +PMHELP_CTL_CODE(UNLOCKCODEPAGES ,0x0023), +PMHELP_CTL_CODE(GETCALLGATE ,0x0024), +PMHELP_CTL_CODE(SETCNTPATH ,0x0025), +PMHELP_CTL_CODE(GETPDB ,0x0026), +PMHELP_CTL_CODE(FLUSHTLB ,0x0027), +PMHELP_CTL_CODE(GETPHYSICALADDRRANGE ,0x0028), +PMHELP_CTL_CODE(ALLOCPAGE ,0x0029), +PMHELP_CTL_CODE(FREEPAGE ,0x002A), +PMHELP_CTL_CODE(ENABLERING3IOPL ,0x002B), +PMHELP_CTL_CODE(DISABLERING3IOPL ,0x002C), +PMHELP_CTL_CODE(GASETLOCALPATH ,0x002D), +PMHELP_CTL_CODE(GAGETEXPORTS ,0x002E), +PMHELP_CTL_CODE(GATHUNK ,0x002F), +PMHELP_CTL_CODE(SETNUCLEUSPATH ,0x0030), diff --git a/board/MAI/bios_emulator/scitech/include/pmapi.h b/board/MAI/bios_emulator/scitech/include/pmapi.h new file mode 100644 index 0000000..7ddace7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pmapi.h @@ -0,0 +1,1148 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#ifndef __PMAPI_H +#define __PMAPI_H + +#include "scitech.h" +#include "pcilib.h" +#include "ztimerc.h" +#if !defined(__WIN32_VXD__) && !defined(__OS2_VDD__) && !defined(__NT_DRIVER__) +#include +#include +#endif + +/*--------------------------- Macros and Typedefs -------------------------*/ + +/* You will need to define one of the following before you compile this + * library for it to work correctly with the DOS extender that you are + * using when compiling for extended DOS: + * + * TNT - Phar Lap TNT DOS Extender + * DOS4GW - Rational DOS/4GW, DOS/4GW Pro, Causeway and PMODE/W + * DJGPP - DJGPP port of GNU C++ + * + * If none is specified, we will automatically determine which operating + * system is being targetted and the following will be defined (provided by + * scitech.h header file): + * + * __MSDOS16__ - Default for 16 bit MSDOS mode + * __MSDOS32__ - Default for 32 bit MSDOS + * __WINDOWS16__ - Default for 16 bit Windows + * __WINDOWS32__ - Default for 32 bit Windows + * + * One of the following will be defined automatically for you to select + * which memory model is in effect: + * + * REALMODE - 16 bit real mode (large memory model) + * PM286 - 16 protected mode (large memory model) + * PM386 - 32 protected mode (flat memory model) + */ + +#if defined(__UNIX__) && !defined(_MAX_PATH) +#define _MAX_PATH 256 +#endif + +#if defined(TNT) || defined(DOSX) || defined(X32VM) || defined(DPMI32) \ + || defined(DOS4GW) || defined(DJGPP) || defined(__WINDOWS32__) \ + || defined(__MSDOS32__) || defined(__UNIX__) || defined(__WIN32_VXD__) \ + || defined(__32BIT__) || defined(__SMX32__) || defined(__RTTARGET__) +#define PM386 +#elif defined(DPMI16) || defined(__WINDOWS16__) +#define PM286 +#else +#define REALMODE +#endif + +#pragma pack(1) + +/* Provide the typedefs for the PM_int386 functions, which issue native + * interrupts in real or protected mode and can pass extended registers + * around. + */ + +struct _PMDWORDREGS { + ulong eax,ebx,ecx,edx,esi,edi,cflag; + }; + +struct _PMWORDREGS { + ushort ax,ax_hi; + ushort bx,bx_hi; + ushort cx,cx_hi; + ushort dx,dx_hi; + ushort si,si_hi; + ushort di,di_hi; + ushort cflag,cflag_hi; + }; + +struct _PMBYTEREGS { + uchar al, ah; ushort ax_hi; + uchar bl, bh; ushort bx_hi; + uchar cl, ch; ushort cx_hi; + uchar dl, dh; ushort dx_hi; + }; + +typedef union { + struct _PMDWORDREGS e; + struct _PMWORDREGS x; + struct _PMBYTEREGS h; + } PMREGS; + +typedef struct { + ushort es; + ushort cs; + ushort ss; + ushort ds; + ushort fs; + ushort gs; + } PMSREGS; + +/* Provide definitions for the real mode register structures passed to + * the PM_int86() and PM_int86x() routines. Note that we provide our own + * functions to do this for 16-bit code that calls the PM_int386 functions. + */ + +typedef PMREGS RMREGS; +typedef PMSREGS RMSREGS; + +typedef struct { + long edi; + long esi; + long ebp; + long reserved; + long ebx; + long edx; + long ecx; + long eax; + short flags; + short es,ds,fs,gs,ip,cs,sp,ss; + } DPMI_regs; + +#ifdef __MSDOS__ +/* Register structure passed to PM_VxDCall function */ +typedef struct { + ulong eax; + ulong ebx; + ulong ecx; + ulong edx; + ulong esi; + ulong edi; + ushort ds,es; + } VXD_regs; +#endif + +#define PM_MAX_DRIVE 3 +#define PM_MAX_PATH 256 +#define PM_FILE_INVALID (void*)0xFFFFFFFF + +/* Structure for generic directory traversal and management. Also the same + * values are passed to PM_setFileAttr to change the file attributes. + */ + +typedef struct { + ulong dwSize; + ulong attrib; + ulong sizeLo; + ulong sizeHi; + char name[PM_MAX_PATH]; + } PM_findData; + +/* Macro to compute the byte offset of a field in a structure of type type */ + +#define PM_FIELD_OFFSET(type,field) ((long)&(((type*)0)->field)) + +/* Marcto to compute the address of the base of the structure given its type, + * and an address of a field within the structure. + */ + +#define PM_CONTAINING_RECORD(address, type, field) \ + ((type*)( \ + (char*)(address) - \ + (char*)(&((type*)0)->field))) + +/* Flags stored in the PM_findData structure, and also values passed to + * PM_setFileAttr to change the file attributes. + */ + +#define PM_FILE_NORMAL 0x00000000 +#define PM_FILE_READONLY 0x00000001 +#define PM_FILE_DIRECTORY 0x00000002 +#define PM_FILE_ARCHIVE 0x00000004 +#define PM_FILE_HIDDEN 0x00000008 +#define PM_FILE_SYSTEM 0x00000010 + +/* Flags returned by the PM_splitpath function */ + +#define PM_HAS_WILDCARDS 0x01 +#define PM_HAS_EXTENSION 0x02 +#define PM_HAS_FILENAME 0x04 +#define PM_HAS_DIRECTORY 0x08 +#define PM_HAS_DRIVE 0x10 + +/* Structure passed to the PM_setFileTime functions */ +typedef struct { + short sec; /* Seconds */ + short min; /* Minutes */ + short hour; /* Hour (0--23) */ + short day; /* Day of month (1--31) */ + short mon; /* Month (0--11) */ + short year; /* Year (calendar year minus 1900) */ + } PM_time; + +/* Define a macro for creating physical base addresses from segment:offset */ + +#define MK_PHYS(s,o) (((ulong)(s) << 4) + (ulong)(o)) + +/* Define the different types of modes supported. This is a global variable + * that can be used to determine the type at runtime which will contain + * one of these values. + */ + +typedef enum { + PM_realMode, + PM_286, + PM_386 + } PM_mode_enum; + +/* Define types passed to PM_enableWriteCombine */ + +#define PM_MTRR_UNCACHABLE 0 +#define PM_MTRR_WRCOMB 1 +#define PM_MTRR_WRTHROUGH 4 +#define PM_MTRR_WRPROT 5 +#define PM_MTRR_WRBACK 6 +#define PM_MTRR_MAX 6 + +/* Error codes returned by PM_enableWriteCombine */ + +#define PM_MTRR_ERR_OK 0 +#define PM_MTRR_NOT_SUPPORTED -1 +#define PM_MTRR_ERR_PARAMS -2 +#define PM_MTRR_ERR_NOT_4KB_ALIGNED -3 +#define PM_MTRR_ERR_BELOW_1MB -4 +#define PM_MTRR_ERR_NOT_ALIGNED -5 +#define PM_MTRR_ERR_OVERLAP -6 +#define PM_MTRR_ERR_TYPE_MISMATCH -7 +#define PM_MTRR_ERR_NONE_FREE -8 +#define PM_MTRR_ERR_NOWRCOMB -9 +#define PM_MTRR_ERR_NO_OS_SUPPORT -10 + +/* Values passed to the PM_DMACProgram function */ + +#define PM_DMA_READ_ONESHOT 0x44 /* One-shot DMA read */ +#define PM_DMA_WRITE_ONESHOT 0x48 /* One-shot DMA write */ +#define PM_DMA_READ_AUTOINIT 0x54 /* Auto-init DMA read */ +#define PM_DMA_WRITE_AUTOINIT 0x58 /* Auto-init DMA write */ + +/* Flags passed to suspend application callback */ + +#define PM_DEACTIVATE 1 +#define PM_REACTIVATE 2 + +/* Return codes that the application can return from the suspend application + * callback registered with the PM library. See the MGL documentation for + * more details. + */ +#define PM_SUSPEND_APP 0 +#define PM_NO_SUSPEND_APP 1 + +/**************************************************************************** +REMARKS: +This enumeration defines the type values passed to the PM_agpReservePhysical +function, to define how the physical memory mapping should be handled. + +The PM_agpUncached type indicates that the memory should be allocated as +uncached memory. + +The PM_agpWriteCombine type indicates that write combining should be enabled +for physical memory mapping. This is used for framebuffer write combing and +speeds up direct framebuffer writes to the memory. + +The PM_agpIntelDCACHE type indicates that memory should come from the Intel +i81x Display Cache (or DCACHE) memory pool. This flag is specific to the +Intel i810 and i815 controllers, and should not be passed for any other +controller type. + +HEADER: +pmapi.h + +MEMBERS: +PM_agpUncached - Indicates that the memory should be uncached +PM_agpWriteCombine - Indicates that the memory should be write combined +PM_agpIntelDCACHE - Indicates that the memory should come from DCACHE pool +****************************************************************************/ +typedef enum { + PM_agpUncached, + PM_agpWriteCombine, + PM_agpIntelDCACHE + } PM_agpMemoryType; + +/* Defines the size of an system memory page */ + +#define PM_PAGE_SIZE 4096 + +/* Type definition for a physical memory address */ + +typedef unsigned long PM_physAddr; + +/* Define a bad physical address returned by map physical functions */ + +#define PM_BAD_PHYS_ADDRESS 0xFFFFFFFF + +/* Type definition for the 12-byte lock handle for locking linear memory */ + +typedef struct { + ulong h[3]; + } PM_lockHandle; + +/* 'C' calling conventions always */ + +#define PMAPI _ASMAPI +#define PMAPIP _ASMAPIP + +/* Internal typedef to override DPMI_int86 handler */ + +typedef ibool (PMAPIP DPMI_handler_t)(DPMI_regs *regs); +void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler); + +/* Type definitions for a window handle for console modes */ + +#if defined(__DRIVER__) || defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +typedef void *PM_HWND; /* Pointer for portable drivers */ +typedef void *PM_MODULE; /* Module handle for portable drivers */ +#elif defined(__WINDOWS__) +#ifdef DECLARE_HANDLE +typedef HWND PM_HWND; /* Real window handle */ +typedef HINSTANCE PM_MODULE; /* Win32 DLL handle */ +#else +typedef void *PM_HWND; /* Place holder if windows.h not included */ +typedef void *PM_MODULE; /* Place holder if windows.h not included */ +#endif +#elif defined(__USE_X11__) +typedef struct { + Window *window; + Display *display; + } PM_HWND; /* X11 window handle */ +#elif defined(__OS2__) +typedef void *PM_HWND; +typedef void *PM_MODULE; +#elif defined(__LINUX__) +typedef int PM_HWND; /* Console id for fullscreen Linux */ +typedef void *PM_MODULE; +#elif defined(__QNX__) +typedef int PM_HWND; /* Console id for fullscreen QNX */ +typedef void *PM_MODULE; +#elif defined(__RTTARGET__) +typedef int PM_HWND; /* Placeholder for RTTarget-32 */ +typedef void *PM_MODULE; +#elif defined(__REALDOS__) +typedef int PM_HWND; /* Placeholder for fullscreen DOS */ +typedef void *PM_MODULE; /* Placeholder for fullscreen DOS */ +#elif defined(__SMX32__) +typedef int PM_HWND; /* Placeholder for fullscreen SMX */ +typedef void *PM_MODULE; +#elif defined(__SNAP__) +typedef void *PM_HWND; +typedef void *PM_MODULE; +#else +#error PM library not ported to this platform yet! +#endif + +/* Type definition for code pointers */ + +typedef void (*__codePtr)(); + +/* Type definition for a C based interrupt handler */ + +typedef void (PMAPIP PM_intHandler)(void); +typedef ibool (PMAPIP PM_irqHandler)(void); + +/* Hardware IRQ handle used to save and restore the hardware IRQ */ + +typedef void *PM_IRQHandle; + +/* Type definition for the fatal cleanup handler */ + +typedef void (PMAPIP PM_fatalCleanupHandler)(void); + +/* Type defifinition for save state callback function */ + +typedef int (PMAPIP PM_saveState_cb)(int flags); + +/* Type definintion for enum write combined callback function */ + +typedef void (PMAPIP PM_enumWriteCombine_t)(ulong base,ulong length,uint type); + +/* Structure defining all the PM API functions as exported to + * the binary portable DLL's. + */ + +typedef struct { + ulong dwSize; + int (PMAPIP PM_getModeType)(void); + void * (PMAPIP PM_getBIOSPointer)(void); + void * (PMAPIP PM_getA0000Pointer)(void); + void * (PMAPIP PM_mapPhysicalAddr)(ulong base,ulong limit,ibool isCached); + void * (PMAPIP PM_mallocShared)(long size); + void * reserved1; + void (PMAPIP PM_freeShared)(void *ptr); + void * (PMAPIP PM_mapToProcess)(void *linear,ulong limit); + void * (PMAPIP PM_mapRealPointer)(uint r_seg,uint r_off); + void * (PMAPIP PM_allocRealSeg)(uint size,uint *r_seg,uint *r_off); + void (PMAPIP PM_freeRealSeg)(void *mem); + void * (PMAPIP PM_allocLockedMem)(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg); + void (PMAPIP PM_freeLockedMem)(void *p,uint size,ibool contiguous); + void (PMAPIP PM_callRealMode)(uint seg,uint off, RMREGS *regs,RMSREGS *sregs); + int (PMAPIP PM_int86)(int intno, RMREGS *in, RMREGS *out); + int (PMAPIP PM_int86x)(int intno, RMREGS *in, RMREGS *out,RMSREGS *sregs); + void (PMAPIP DPMI_int86)(int intno, DPMI_regs *regs); + void (PMAPIP PM_availableMemory)(ulong *physical,ulong *total); + void * (PMAPIP PM_getVESABuf)(uint *len,uint *rseg,uint *roff); + long (PMAPIP PM_getOSType)(void); + void (PMAPIP PM_fatalError)(const char *msg); + void (PMAPIP PM_setBankA)(int bank); + void (PMAPIP PM_setBankAB)(int bank); + void (PMAPIP PM_setCRTStart)(int x,int y,int waitVRT); + char * (PMAPIP PM_getCurrentPath)(char *path,int maxLen); + const char * (PMAPIP PM_getVBEAFPath)(void); + const char * (PMAPIP PM_getNucleusPath)(void); + const char * (PMAPIP PM_getNucleusConfigPath)(void); + const char * (PMAPIP PM_getUniqueID)(void); + const char * (PMAPIP PM_getMachineName)(void); + ibool (PMAPIP VF_available)(void); + void * (PMAPIP VF_init)(ulong baseAddr,int bankSize,int codeLen,void *bankFunc); + void (PMAPIP VF_exit)(void); + PM_HWND (PMAPIP PM_openConsole)(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen); + int (PMAPIP PM_getConsoleStateSize)(void); + void (PMAPIP PM_saveConsoleState)(void *stateBuf,PM_HWND hwndConsole); + void (PMAPIP PM_restoreConsoleState)(const void *stateBuf,PM_HWND hwndConsole); + void (PMAPIP PM_closeConsole)(PM_HWND hwndConsole); + void (PMAPIP PM_setOSCursorLocation)(int x,int y); + void (PMAPIP PM_setOSScreenWidth)(int width,int height); + int (PMAPIP PM_enableWriteCombine)(ulong base,ulong length,uint type); + void (PMAPIP PM_backslash)(char *filename); + int (PMAPIP PM_lockDataPages)(void *p,uint len,PM_lockHandle *lockHandle); + int (PMAPIP PM_unlockDataPages)(void *p,uint len,PM_lockHandle *lockHandle); + int (PMAPIP PM_lockCodePages)(__codePtr p,uint len,PM_lockHandle *lockHandle); + int (PMAPIP PM_unlockCodePages)(__codePtr p,uint len,PM_lockHandle *lockHandle); + ibool (PMAPIP PM_setRealTimeClockHandler)(PM_intHandler ih,int frequency); + void (PMAPIP PM_setRealTimeClockFrequency)(int frequency); + void (PMAPIP PM_restoreRealTimeClockHandler)(void); + ibool (PMAPIP PM_doBIOSPOST)(ushort axVal,ulong BIOSPhysAddr,void *BIOSPtr,ulong BIOSLen); + char (PMAPIP PM_getBootDrive)(void); + void (PMAPIP PM_freePhysicalAddr)(void *ptr,ulong limit); + uchar (PMAPIP PM_inpb)(int port); + ushort (PMAPIP PM_inpw)(int port); + ulong (PMAPIP PM_inpd)(int port); + void (PMAPIP PM_outpb)(int port,uchar val); + void (PMAPIP PM_outpw)(int port,ushort val); + void (PMAPIP PM_outpd)(int port,ulong val); + void * reserved2; + void (PMAPIP PM_setSuspendAppCallback)(PM_saveState_cb saveState); + ibool (PMAPIP PM_haveBIOSAccess)(void); + int (PMAPIP PM_kbhit)(void); + int (PMAPIP PM_getch)(void); + ibool (PMAPIP PM_findBPD)(const char *dllname,char *bpdpath); + ulong (PMAPIP PM_getPhysicalAddr)(void *p); + void (PMAPIP PM_sleep)(ulong milliseconds); + int (PMAPIP PM_getCOMPort)(int port); + int (PMAPIP PM_getLPTPort)(int port); + PM_MODULE (PMAPIP PM_loadLibrary)(const char *szDLLName); + void * (PMAPIP PM_getProcAddress)(PM_MODULE hModule,const char *szProcName); + void (PMAPIP PM_freeLibrary)(PM_MODULE hModule); + int (PMAPIP PCI_enumerate)(PCIDeviceInfo info[]); + ulong (PMAPIP PCI_accessReg)(int index,ulong value,int func,PCIDeviceInfo *info); + ibool (PMAPIP PCI_setHardwareIRQ)(PCIDeviceInfo *info,uint intPin,uint IRQ); + void (PMAPIP PCI_generateSpecialCyle)(uint bus,ulong specialCycleData); + void * reserved3; + ulong (PMAPIP PCIBIOS_getEntry)(void); + uint (PMAPIP CPU_getProcessorType)(void); + ibool (PMAPIP CPU_haveMMX)(void); + ibool (PMAPIP CPU_have3DNow)(void); + ibool (PMAPIP CPU_haveSSE)(void); + ibool (PMAPIP CPU_haveRDTSC)(void); + ulong (PMAPIP CPU_getProcessorSpeed)(ibool accurate); + void (PMAPIP ZTimerInit)(void); + void (PMAPIP LZTimerOn)(void); + ulong (PMAPIP LZTimerLap)(void); + void (PMAPIP LZTimerOff)(void); + ulong (PMAPIP LZTimerCount)(void); + void (PMAPIP LZTimerOnExt)(LZTimerObject *tm); + ulong (PMAPIP LZTimerLapExt)(LZTimerObject *tm); + void (PMAPIP LZTimerOffExt)(LZTimerObject *tm); + ulong (PMAPIP LZTimerCountExt)(LZTimerObject *tm); + void (PMAPIP ULZTimerOn)(void); + ulong (PMAPIP ULZTimerLap)(void); + void (PMAPIP ULZTimerOff)(void); + ulong (PMAPIP ULZTimerCount)(void); + ulong (PMAPIP ULZReadTime)(void); + ulong (PMAPIP ULZElapsedTime)(ulong start,ulong finish); + void (PMAPIP ULZTimerResolution)(ulong *resolution); + void * (PMAPIP PM_findFirstFile)(const char *filename,PM_findData *findData); + ibool (PMAPIP PM_findNextFile)(void *handle,PM_findData *findData); + void (PMAPIP PM_findClose)(void *handle); + void (PMAPIP PM_makepath)(char *p,const char *drive,const char *dir,const char *name,const char *ext); + int (PMAPIP PM_splitpath)(const char *fn,char *drive,char *dir,char *name,char *ext); + ibool (PMAPIP PM_driveValid)(char drive); + void (PMAPIP PM_getdcwd)(int drive,char *dir,int len); + void (PMAPIP PM_setFileAttr)(const char *filename,uint attrib); + ibool (PMAPIP PM_mkdir)(const char *filename); + ibool (PMAPIP PM_rmdir)(const char *filename); + uint (PMAPIP PM_getFileAttr)(const char *filename); + ibool (PMAPIP PM_getFileTime)(const char *filename,ibool gmtTime,PM_time *time); + ibool (PMAPIP PM_setFileTime)(const char *filename,ibool gmtTime,PM_time *time); + char * (PMAPIP CPU_getProcessorName)(void); + int (PMAPIP PM_getVGAStateSize)(void); + void (PMAPIP PM_saveVGAState)(void *stateBuf); + void (PMAPIP PM_restoreVGAState)(const void *stateBuf); + void (PMAPIP PM_vgaBlankDisplay)(void); + void (PMAPIP PM_vgaUnblankDisplay)(void); + void (PMAPIP PM_blockUntilTimeout)(ulong milliseconds); + void (PMAPIP _PM_add64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); + void (PMAPIP _PM_sub64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); + void (PMAPIP _PM_mul64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); + void (PMAPIP _PM_div64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); + void (PMAPIP _PM_shr64)(u32 a_low,s32 a_high,s32 shift,__i64 *result); + void (PMAPIP _PM_sar64)(u32 a_low,s32 a_high,s32 shift,__i64 *result); + void (PMAPIP _PM_shl64)(u32 a_low,s32 a_high,s32 shift,__i64 *result); + void (PMAPIP _PM_neg64)(u32 a_low,s32 a_high,__i64 *result); + ulong (PMAPIP PCI_findBARSize)(int bar,PCIDeviceInfo *pci); + void (PMAPIP PCI_readRegBlock)(PCIDeviceInfo *info,int index,void *dst,int count); + void (PMAPIP PCI_writeRegBlock)(PCIDeviceInfo *info,int index,void *src,int count); + void (PMAPIP PM_flushTLB)(void); + void (PMAPIP PM_useLocalMalloc)(void * (*malloc)(size_t size),void * (*calloc)(size_t nelem,size_t size),void * (*realloc)(void *ptr,size_t size),void (*free)(void *p)); + void * (PMAPIP PM_malloc)(size_t size); + void * (PMAPIP PM_calloc)(size_t nelem,size_t size); + void * (PMAPIP PM_realloc)(void *ptr,size_t size); + void (PMAPIP PM_free)(void *p); + ibool (PMAPIP PM_getPhysicalAddrRange)(void *p,ulong length,ulong *physAddress); + void * (PMAPIP PM_allocPage)(ibool locked); + void (PMAPIP PM_freePage)(void *p); + ulong (PMAPIP PM_agpInit)(void); + void (PMAPIP PM_agpExit)(void); + ibool (PMAPIP PM_agpReservePhysical)(ulong numPages,int type,void **physContext,PM_physAddr *physAddr); + ibool (PMAPIP PM_agpReleasePhysical)(void *physContext); + ibool (PMAPIP PM_agpCommitPhysical)(void *physContext,ulong numPages,ulong startOffset,PM_physAddr *physAddr); + ibool (PMAPIP PM_agpFreePhysical)(void *physContext,ulong numPages,ulong startOffset); + int (PMAPIP PCI_getNumDevices)(void); + void (PMAPIP PM_setLocalBPDPath)(const char *path); + void * (PMAPIP PM_loadDirectDraw)(int device); + void (PMAPIP PM_unloadDirectDraw)(int device); + PM_HWND (PMAPIP PM_getDirectDrawWindow)(void); + void (PMAPIP PM_doSuspendApp)(void); + } PM_imports; + +#pragma pack() + +/*---------------------------- Global variables ---------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +#ifdef __WIN32_VXD__ +#define VESA_BUF_SIZE 1024 +extern uchar *_PM_rmBufAddr; +#endif + +/* {secret} Pointer to global exports structure. + * Should not be used by application programs. + */ +extern PM_imports _VARAPI _PM_imports; + +/* {secret} */ +extern void * (*__PM_malloc)(size_t size); +/* {secret} */ +extern void * (*__PM_calloc)(size_t nelem,size_t size); +/* {secret} */ +extern void * (*__PM_realloc)(void *ptr,size_t size); +/* {secret} */ +extern void (*__PM_free)(void *p); + +/*--------------------------- Function Prototypes -------------------------*/ + +/* Routine to initialise the host side PM library. Note used from DLL's */ + +void PMAPI PM_init(void); + +/* Routine to return either PM_realMode, PM_286 or PM_386 */ + +int PMAPI PM_getModeType(void); + +/* Routine to return a selector to the BIOS data area at segment 0x40 */ + +void * PMAPI PM_getBIOSPointer(void); + +/* Routine to return a linear pointer to the VGA frame buffer memory */ + +void * PMAPI PM_getA0000Pointer(void); + +/* Routines to map/free physical memory into the current DS segment. In + * some environments (32-bit DOS is one), after the mapping has been + * allocated, it cannot be freed. Hence you should only allocate the + * mapping once and cache the value for use by other parts of your + * application. If the mapping cannot be createed, this function will + * return a NULL pointer. + * + * This routine will also work for memory addresses below 1Mb, but the + * mapped address cannot cross the 1Mb boundary. + */ + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached); +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit); + +/* Routine to determine the physical address of a linear address. It is + * up to the caller to ensure the entire address range for a linear + * block of memory is page aligned if that is required. + */ + +ulong PMAPI PM_getPhysicalAddr(void *p); +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress); + +/* Routines for memory allocation. By default these functions use the regular + * C runtime library malloc/free functions, but you can use the + * PM_useLocalMalloc function to override the default memory allocator with + * your own memory allocator. This will ensure that all memory allocation + * used by SciTech products will use your overridden memory allocator + * functions. + * + * Note that BPD files automatically map the C runtime library + * malloc/calloc/realloc/free calls from inside the BPD to the PM library + * versions by default. + */ + +void PMAPI PM_useLocalMalloc(void * (*malloc)(size_t size),void * (*calloc)(size_t nelem,size_t size),void * (*realloc)(void *ptr,size_t size),void (*free)(void *p)); +void * PMAPI PM_malloc(size_t size); +void * PMAPI PM_calloc(size_t nelem,size_t size); +void * PMAPI PM_realloc(void *ptr,size_t size); +void PMAPI PM_free(void *p); + +/* Routine to allocate a memory block in the global shared region that + * is common to all tasks and accessible from ring 0 code. + */ + +void * PMAPI PM_mallocShared(long size); + +/* Routine to free the allocated shared memory block */ + +void PMAPI PM_freeShared(void *ptr); + +/* Attach a previously allocated linear mapping to a new process */ + +void * PMAPI PM_mapToProcess(void *linear,ulong limit); + +/* Macros to extract byte, word and long values from a char pointer */ + +#define PM_getByte(p) *((volatile uchar*)(p)) +#define PM_getWord(p) *((volatile ushort*)(p)) +#define PM_getLong(p) *((volatile ulong*)(p)) +#define PM_setByte(p,v) PM_getByte(p) = (v) +#define PM_setWord(p,v) PM_getWord(p) = (v) +#define PM_setLong(p,v) PM_getLong(p) = (v) + +/* Routine for accessing a low 1Mb memory block. You dont need to free this + * pointer, but in 16 bit protected mode the selector allocated will be + * re-used the next time this routine is called. + */ + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off); + +/* Routine to allocate a block of conventional memory below the 1Mb + * limit so that it can be accessed from real mode. Ensure that you free + * the segment when you are done with it. + * + * This routine returns a selector and offset to the segment that has been + * allocated, and also returns the real mode segment and offset which can + * be passed to real mode routines. Will return 0 if memory could not be + * allocated. + * + * Please note that with some DOS extenders, memory allocated with the + * following function cannot be freed, hence it will be allocated for the + * life of your program. Thus if you need to call a bunch of different + * real-mode routines in your program, allocate a single large buffer at + * program startup that can be re-used throughout the program execution. + */ + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off); +void PMAPI PM_freeRealSeg(void *mem); + +/* Routine to allocate a block of locked memory, and return both the + * linear and physical addresses of the memory. You should always + * allocate locked memory blocks in page sized chunks (ie: 4K on IA32). + * If the memory is not contiguous, you will need to use the + * PM_getPhysicalAddr function to get the physical address of linear + * pages within the memory block (the returned physical address will be + * for the first address in the memory block only). + */ + +void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg); +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous); + +/* Routine to allocate and free paged sized blocks of shared memory. + * Addressable from all processes, but not from a ring 0 context + * under OS/2. Note that under OS/2 PM_mapSharedPages must be called + * to map the memory blocks into the shared memory address space + * of each connecting process. + */ + +void * PMAPI PM_allocPage(ibool locked); +void PMAPI PM_freePage(void *p); +#ifdef __OS2__ +void PMAPI PM_mapSharedPages(void); +#endif + +/* Routine to return true if we have access to the BIOS on the host OS */ + +ibool PMAPI PM_haveBIOSAccess(void); + +/* Routine to call a real mode assembly language procedure. Register + * values are passed in and out in the 'regs' and 'sregs' structures. We + * do not provide any method of copying data from the protected mode stack + * to the real mode stack, so if you need to pass data to real mode, you will + * need to write a real mode assembly language hook to recieve the values + * in registers, and to pass the data through a real mode block allocated + * with the PM_allocRealSeg() routine. + */ + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *regs,RMSREGS *sregs); + +/* Routines to generate real mode interrupts using the same interface that + * is used by int86() and int86x() in realmode. This routine is need to + * call certain BIOS and DOS functions that are not supported by some + * DOS extenders. No translation is done on any of the register values, + * so they must be correctly set up and translated by the calling program. + * + * Normally the DOS extenders will allow you to use the normal int86() + * function directly and will pass on unhandled calls to real mode to be + * handled by the real mode handler. However calls to int86x() with real + * mode segment values to be loaded will cause a GPF if used with the + * standard int86x(), so you should use these routines if you know you + * want to call a real mode handler. + */ + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out); +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,RMSREGS *sregs); + +/* Routine to generate a real mode interrupt. This is identical to the + * above function, but takes a DPMI_regs structure for the registers + * which has a lot more information. It is only available from 32-bit + * protected mode. + */ + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs); + +/* Function to return the amount of available physical and total memory. + * The results of this function are *only* valid before you have made any + * calls to malloc() and free(). If you need to keep track of exactly how + * much memory is currently allocated, you need to call this function to + * get the total amount of memory available and then keep track of + * the available memory every time you call malloc() and free(). + */ + +void PMAPI PM_availableMemory(ulong *physical,ulong *total); + +/* Return the address of a global VESA real mode transfer buffer for use + * by applications. + */ + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff); + +/* Handle fatal error conditions */ + +void PMAPI PM_fatalError(const char *msg); + +/* Function to set a cleanup error handler called when PM_fatalError + * is called. This allows us to the console back into a normal state + * if we get a failure from deep inside a BPD file. This function is + * not exported to BPD files, and is only used by code compiled for the + * OS. + */ + +void PMAPI PM_setFatalErrorCleanup(PM_fatalCleanupHandler cleanup); + +/* Return the OS type flag as defined in */ + +long PMAPI PM_getOSType(void); + +/* Functions to set a VBE bank via an Int 10h */ + +void PMAPI PM_setBankA(int bank); +void PMAPI PM_setBankAB(int bank); +void PMAPI PM_setCRTStart(int x,int y,int waitVRT); + +/* Return the current working directory */ + +char * PMAPI PM_getCurrentPath(char *path,int maxLen); + +/* Return paths to the VBE/AF and Nucleus directories */ + +const char * PMAPI PM_getVBEAFPath(void); +const char * PMAPI PM_getNucleusPath(void); +const char * PMAPI PM_getNucleusConfigPath(void); + +/* Find the path to a binary portable DLL */ + +void PMAPI PM_setLocalBPDPath(const char *path); +ibool PMAPI PM_findBPD(const char *dllname,char *bpdpath); + +/* Returns the drive letter of the boot drive for DOS, OS/2 and Windows */ + +char PMAPI PM_getBootDrive(void); + +/* Return a network unique machine identifier as a string */ + +const char * PMAPI PM_getUniqueID(void); + +/* Return the network machine name as a string */ + +const char * PMAPI PM_getMachineName(void); + +/* Functions to install and remove the virtual linear framebuffer + * emulation code. For unsupported DOS extenders and when running under + * a DPMI host like Windows or OS/2, this function will return a NULL. + */ + +ibool PMAPI VF_available(void); +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc); +void PMAPI VF_exit(void); + +/* Functions to wait for a keypress and read a key for command line + * environments such as DOS, Win32 console and Unix. + */ + +int PMAPI PM_kbhit(void); +int PMAPI PM_getch(void); + +/* Functions to create either a fullscreen or windowed console on the + * desktop, and to allow the resolution of fullscreen consoles to be + * changed on the fly without closing the console. For non-windowed + * environments (such as a Linux or OS/2 fullscreen console), these + * functions enable console graphics mode and restore console text mode. + * + * The suspend application callback is used to allow the application to + * save the state of the fullscreen console mode to allow temporary + * switching to another console or back to the regular GUI desktop. It + * is also called to restore the fullscreen graphics state after the + * fullscreen console regains the focus. + * + * The device parameter allows for the console to be opened on a different + * display controllers (0 is always the primary controller). + */ + +PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen); +int PMAPI PM_getConsoleStateSize(void); +void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole); +void PMAPI PM_setSuspendAppCallback(PM_saveState_cb saveState); +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole); +void PMAPI PM_closeConsole(PM_HWND hwndConsole); + +/* Functions to modify OS console information */ + +void PMAPI PM_setOSCursorLocation(int x,int y); +void PMAPI PM_setOSScreenWidth(int width,int height); + +/* Function to emable Intel PPro/PII write combining */ + +int PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type); +int PMAPI PM_enumWriteCombine(PM_enumWriteCombine_t callback); + +/* Function to add a path separator to the end of a filename (if not present) */ + +void PMAPI PM_backslash(char *filename); + +/* Routines to lock and unlock regions of memory under a virtual memory + * environment. These routines _must_ be used to lock all hardware + * and mouse interrupt handlers installed, _AND_ any global data that + * these handler manipulate, so that they will always be present in memory + * to handle the incoming interrupts. + * + * Note that it is important to call the correct routine depending on + * whether the area being locked is code or data, so that under 32 bit + * PM we will get the selector value correct. + */ + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lockHandle); +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lockHandle); +int PMAPI PM_lockCodePages(__codePtr p,uint len,PM_lockHandle *lockHandle); +int PMAPI PM_unlockCodePages(__codePtr p,uint len,PM_lockHandle *lockHandle); + +/* Routines to install and remove Real Time Clock interrupt handlers. The + * frequency of the real time clock can be changed by calling + * PM_setRealTimeClockFrequeny, and the value can be any power of 2 value + * from 2Hz to 8192Hz. + * + * Note that you _must_ lock the memory containing the interrupt + * handlers with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + * + * NOTE: User space versions of the PM library should fail these functions. + */ + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih,int frequency); +void PMAPI PM_setRealTimeClockFrequency(int frequency); +void PMAPI PM_restoreRealTimeClockHandler(void); + +/* Routines to install and remove hardware interrupt handlers. + * + * Note that you _must_ lock the memory containing the interrupt + * handlers with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + * + * NOTE: User space versions of the PM library should fail these functions. + */ + +PM_IRQHandle PMAPI PM_setIRQHandler(int IRQ,PM_irqHandler ih); +void PMAPI PM_restoreIRQHandler(PM_IRQHandle irqHandle); + +/* Functions to program DMA using the legacy ISA DMA controller */ + +void PMAPI PM_DMACEnable(int channel); +void PMAPI PM_DMACDisable(int channel); +void PMAPI PM_DMACProgram(int channel,int mode,ulong bufferPhys,int count); +ulong PMAPI PM_DMACPosition(int channel); + +/* Function to post secondary graphics controllers using the BIOS */ + +ibool PMAPI PM_doBIOSPOST(ushort axVal,ulong BIOSPhysAddr,void *mappedBIOS,ulong BIOSLen); + +/* Function to init the AGP functions and return the AGP aperture size in MB */ + +ulong PMAPI PM_agpInit(void); +void PMAPI PM_agpExit(void); + +/* Functions to reserve and release physical AGP memory ranges */ + +ibool PMAPI PM_agpReservePhysical(ulong numPages,int type,void **physContext,PM_physAddr *physAddr); +ibool PMAPI PM_agpReleasePhysical(void *physContext); + +/* Functions to commit and free physical AGP memory ranges */ + +ibool PMAPI PM_agpCommitPhysical(void *physContext,ulong numPages,ulong startOffset,PM_physAddr *physAddr); +ibool PMAPI PM_agpFreePhysical(void *physContext,ulong numPages,ulong startOffset); + +/* Functions to do I/O port manipulation directly from C code. These + * functions are portable and will work on any processor architecture + * to access I/O space registers on PCI devices. + */ + +uchar PMAPI PM_inpb(int port); +ushort PMAPI PM_inpw(int port); +ulong PMAPI PM_inpd(int port); +void PMAPI PM_outpb(int port,uchar val); +void PMAPI PM_outpw(int port,ushort val); +void PMAPI PM_outpd(int port,ulong val); + +/* Functions to determine the I/O port locations for COM and LPT ports. + * The functions are zero based, so for COM1 or LPT1 pass in a value of 0, + * for COM2 or LPT2 pass in a value of 1 etc. + */ + +int PMAPI PM_getCOMPort(int port); +int PMAPI PM_getLPTPort(int port); + +/* Internal functions that need prototypes */ + +void PMAPI _PM_getRMvect(int intno, long *realisr); +void PMAPI _PM_setRMvect(int intno, long realisr); +void PMAPI _PM_freeMemoryMappings(void); + +/* Function to override the default debug log file location */ + +void PMAPI PM_setDebugLog(const char *logFilePath); + +/* Function to put the process to sleep for the specified milliseconds */ + +void PMAPI PM_sleep(ulong milliseconds); + +/* Function to block until 'milliseconds' have passed since last call */ + +void PMAPI PM_blockUntilTimeout(ulong milliseconds); + +/* Functions for directory traversal and management */ + +void * PMAPI PM_findFirstFile(const char *filename,PM_findData *findData); +ibool PMAPI PM_findNextFile(void *handle,PM_findData *findData); +void PMAPI PM_findClose(void *handle); +void PMAPI PM_makepath(char *p,const char *drive,const char *dir,const char *name,const char *ext); +int PMAPI PM_splitpath(const char *fn,char *drive,char *dir,char *name,char *ext); +ibool PMAPI PM_driveValid(char drive); +void PMAPI PM_getdcwd(int drive,char *dir,int len); +uint PMAPI PM_getFileAttr(const char *filename); +void PMAPI PM_setFileAttr(const char *filename,uint attrib); +ibool PMAPI PM_getFileTime(const char *filename,ibool gmTime,PM_time *time); +ibool PMAPI PM_setFileTime(const char *filename,ibool gmTime,PM_time *time); +ibool PMAPI PM_mkdir(const char *filename); +ibool PMAPI PM_rmdir(const char *filename); + +/* Functions to handle loading OS specific shared libraries */ + +PM_MODULE PMAPI PM_loadLibrary(const char *szDLLName); +void * PMAPI PM_getProcAddress(PM_MODULE hModule,const char *szProcName); +void PMAPI PM_freeLibrary(PM_MODULE hModule); + +/* Functions and macros for 64-bit arithmetic */ + +void PMAPI _PM_add64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); +void PMAPI _PM_sub64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); +void PMAPI _PM_mul64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); +void PMAPI _PM_div64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); +void PMAPI _PM_shr64(u32 a_low,s32 a_high,s32 shift,__i64 *result); +void PMAPI _PM_sar64(u32 a_low,s32 a_high,s32 shift,__i64 *result); +void PMAPI _PM_shl64(u32 a_low,s32 a_high,s32 shift,__i64 *result); +void PMAPI _PM_neg64(u32 a_low,s32 a_high,__i64 *result); +#ifdef __NATIVE_INT64__ +#define PM_add64(r,a,b) (r) = (a) + (b) +#define PM_add64_32(r,a,b) (r) = (a) + (b) +#define PM_sub64(r,a,b) (r) = (a) - (b) +#define PM_sub64_32(r,a,b) (r) = (a) - (b) +#define PM_mul64(r,a,b) (r) = (a) * (b) +#define PM_mul64_32(r,a,b) (r) = (a) * (b) +#define PM_div64(r,a,b) (r) = (a) / (b) +#define PM_div64_32(r,a,b) (r) = (a) / (b) +#define PM_shr64(r,a,s) (r) = (a) >> (s) +#define PM_sar64(r,a,s) (r) = ((s64)(a)) >> (s) +#define PM_shl64(r,a,s) (r) = (u64)(a) << (s) +#define PM_neg64(r,a,s) (r) = -(a) +#define PM_not64(r,a,s) (r) = ~(a) +#define PM_eq64(a,b) (a) == (b) +#define PM_gt64(a,b) (a) > (b) +#define PM_lt64(a,b) (a) < (b) +#define PM_geq64(a,b) (a) >= (b) +#define PM_leq64(a,b) (a) <= (b) +#define PM_64to32(a) (u32)(a) +#define PM_64tos32(a) (s32)(a) +#define PM_set64(a,b,c) (a) = ((u64)(b) << 32) + (c) +#define PM_set64_32(a,b) (a) = (b) +#else +#define PM_add64(r,a,b) _PM_add64((a).low,(a).high,(b).low,(b).high,&(r)) +#define PM_add64_32(r,a,b) _PM_add64((a).low,(a).high,b,0,&(r)) +#define PM_sub64(r,a,b) _PM_sub64((a).low,(a).high,(b).low,(b).high,&(r)) +#define PM_sub64_32(r,a,b) _PM_sub64((a).low,(a).high,b,0,&(r)) +#define PM_mul64(r,a,b) _PM_mul64((a).low,(a).high,(b).low,(b).high,&(r)) +#define PM_mul64_32(r,a,b) _PM_mul64((a).low,(a).high,b,0,&(r)) +#define PM_div64(r,a,b) _PM_div64((a).low,(a).high,(b).low,(b).high,&(r)) +#define PM_div64_32(r,a,b) _PM_div64((a).low,(a).high,b,0,&(r)) +#define PM_shr64(r,a,s) _PM_shr64((a).low,(a).high,s,&(r)) +#define PM_sar64(r,a,s) _PM_sar64((a).low,(a).high,s,&(r)) +#define PM_shl64(r,a,s) _PM_shl64((a).low,(a).high,s,&(r)) +#define PM_neg64(r,a,s) _PM_neg64((a).low,(a).high,&(r)) +#define PM_not64(r,a,s) (r).low = ~(a).low, (r).high = ~(a).high +#define PM_eq64(a,b) ((a).low == (b).low && (a).high == (b).high) +#define PM_gt64(a,b) (((a).high > (b).high) || ((a).high == (b).high && (a).low > (b).low)) +#define PM_lt64(a,b) (((a).high < (b).high) || ((a).high == (b).high && (a).low < (b).low)) +#define PM_geq64(a,b) (PM_eq64(a,b) || PM_gt64(a,b)) +#define PM_leq64(a,b) (PM_eq64(a,b) || PM_lt64(a,b)) +#define PM_64to32(a) (u32)(a.low) +#define PM_64tos32(a) ((a).high < 0) ? -(a).low : (a).low) +#define PM_set64(a,b,c) (a).high = (b), (a).low = (c) +#define PM_set64_32(a,b) (a).high = 0, (a).low = (b) +#endif + +/* Function to enable IOPL access if required */ + +int PMAPI PM_setIOPL(int iopl); + +/* Function to flush the TLB and CPU caches */ + +void PMAPI PM_flushTLB(void); + +/* DOS specific fucntions */ + +#ifdef __MSDOS__ +uint PMAPI PMHELP_getVersion(void); +void PMAPI PM_VxDCall(VXD_regs *regs); +#endif + +/* Functions to save and restore the VGA hardware state */ + +int PMAPI PM_getVGAStateSize(void); +void PMAPI PM_saveVGAState(void *stateBuf); +void PMAPI PM_restoreVGAState(const void *stateBuf); +void PMAPI PM_vgaBlankDisplay(void); +void PMAPI PM_vgaUnblankDisplay(void); + +/* Functions to load and unload DirectDraw libraries. Only used on + * Windows platforms. + */ + +void * PMAPI PM_loadDirectDraw(int device); +void PMAPI PM_unloadDirectDraw(int device); +PM_HWND PMAPI PM_getDirectDrawWindow(void); +void PMAPI PM_doSuspendApp(void); + +/* Functions to install, start, stop and remove NT services. Valid only + * for Win32 apps running on Windows NT. + */ + +#ifdef __WINDOWS32__ +ulong PMAPI PM_installService(const char *szDriverName,const char *szServiceName,const char *szLoadGroup,ulong dwServiceType); +ulong PMAPI PM_startService(const char *szServiceName); +ulong PMAPI PM_stopService(const char *szServiceName); +ulong PMAPI PM_removeService(const char *szServiceName); +#endif + +/* Routines to generate native interrupts (ie: protected mode interrupts + * for protected mode apps) using an interface the same as that use by + * int86() and int86x() in realmode. These routines are required because + * many 32 bit compilers use different register structures and different + * functions causing major portability headaches. Thus we provide our + * own and solve it all in one fell swoop, and we also get a routine to + * put stuff into 32 bit registers from real mode ;-) + */ + +void PMAPI PM_segread(PMSREGS *sregs); +int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out); +int PMAPI PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs); + +/* Call the X86 emulator or the real BIOS in our test harness */ + +#if defined(TEST_HARNESS) && !defined(PMLIB) +#define PM_mapRealPointer(r_seg,r_off) _PM_imports.PM_mapRealPointer(r_seg,r_off) +#define PM_getVESABuf(len,rseg,roff) _PM_imports.PM_getVESABuf(len,rseg,roff) +#define PM_callRealMode(seg,off,regs,sregs) _PM_imports.PM_callRealMode(seg,off,regs,sregs) +#define PM_int86(intno,in,out) _PM_imports.PM_int86(intno,in,out) +#define PM_int86x(intno,in,out,sregs) _PM_imports.PM_int86x(intno,in,out,sregs) +#endif + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +/* Include OS extensions for interrupt handling */ + +#if defined(__REALDOS__) || defined(__SMX32__) +#include "pmint.h" +#endif + +#endif /* __PMAPI_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pmimp.h b/board/MAI/bios_emulator/scitech/include/pmimp.h new file mode 100644 index 0000000..817f5e6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pmimp.h @@ -0,0 +1,193 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file declaring all the PM imports structure for the +* current version of the PM library. Included in all code +* that needs to pass the PM imports to BPD files. +* +****************************************************************************/ + +PM_imports _VARAPI _PM_imports = { + sizeof(PM_imports), + PM_getModeType, + PM_getBIOSPointer, + PM_getA0000Pointer, + PM_mapPhysicalAddr, + PM_mallocShared, + NULL, + PM_freeShared, + PM_mapToProcess, + PM_mapRealPointer, + PM_allocRealSeg, + PM_freeRealSeg, + PM_allocLockedMem, + PM_freeLockedMem, + PM_callRealMode, + PM_int86, + PM_int86x, + DPMI_int86, + PM_availableMemory, + PM_getVESABuf, + PM_getOSType, + PM_fatalError, + PM_setBankA, + PM_setBankAB, + PM_setCRTStart, + PM_getCurrentPath, + PM_getVBEAFPath, + PM_getNucleusPath, + PM_getNucleusConfigPath, + PM_getUniqueID, + PM_getMachineName, + VF_available, + VF_init, + VF_exit, + PM_openConsole, + PM_getConsoleStateSize, + PM_saveConsoleState, + PM_restoreConsoleState, + PM_closeConsole, + PM_setOSCursorLocation, + PM_setOSScreenWidth, + PM_enableWriteCombine, + PM_backslash, + PM_lockDataPages, + PM_unlockDataPages, + PM_lockCodePages, + PM_unlockCodePages, + PM_setRealTimeClockHandler, + PM_setRealTimeClockFrequency, + PM_restoreRealTimeClockHandler, + PM_doBIOSPOST, + PM_getBootDrive, + PM_freePhysicalAddr, + PM_inpb, + PM_inpw, + PM_inpd, + PM_outpb, + PM_outpw, + PM_outpd, + NULL, + PM_setSuspendAppCallback, + PM_haveBIOSAccess, + PM_kbhit, + PM_getch, + PM_findBPD, + PM_getPhysicalAddr, + PM_sleep, + PM_getCOMPort, + PM_getLPTPort, + PM_loadLibrary, + PM_getProcAddress, + PM_freeLibrary, + PCI_enumerate, + PCI_accessReg, + PCI_setHardwareIRQ, + PCI_generateSpecialCyle, + NULL, + PCIBIOS_getEntry, + CPU_getProcessorType, + CPU_haveMMX, + CPU_have3DNow, + CPU_haveSSE, + CPU_haveRDTSC, + CPU_getProcessorSpeed, + ZTimerInit, + LZTimerOn, + LZTimerLap, + LZTimerOff, + LZTimerCount, + LZTimerOnExt, + LZTimerLapExt, + LZTimerOffExt, + LZTimerCountExt, + ULZTimerOn, + ULZTimerLap, + ULZTimerOff, + ULZTimerCount, + ULZReadTime, + ULZElapsedTime, + ULZTimerResolution, + PM_findFirstFile, + PM_findNextFile, + PM_findClose, + PM_makepath, + PM_splitpath, + PM_driveValid, + PM_getdcwd, + PM_setFileAttr, + PM_mkdir, + PM_rmdir, + PM_getFileAttr, + PM_getFileTime, + PM_setFileTime, + CPU_getProcessorName, + PM_getVGAStateSize, + PM_saveVGAState, + PM_restoreVGAState, + PM_vgaBlankDisplay, + PM_vgaUnblankDisplay, + PM_blockUntilTimeout, + _PM_add64, + _PM_sub64, + _PM_mul64, + _PM_div64, + _PM_shr64, + _PM_sar64, + _PM_shl64, + _PM_neg64, + PCI_findBARSize, + PCI_readRegBlock, + PCI_writeRegBlock, + PM_flushTLB, + PM_useLocalMalloc, + PM_malloc, + PM_calloc, + PM_realloc, + PM_free, + PM_getPhysicalAddrRange, + PM_allocPage, + PM_freePage, + PM_agpInit, + PM_agpExit, + PM_agpReservePhysical, + PM_agpReleasePhysical, + PM_agpCommitPhysical, + PM_agpFreePhysical, + PCI_getNumDevices, + PM_setLocalBPDPath, +#ifdef __WINDOWS32__ + PM_loadDirectDraw, + PM_unloadDirectDraw, + PM_getDirectDrawWindow, + PM_doSuspendApp, +#else + NULL, + NULL, + NULL, + NULL, +#endif + }; diff --git a/board/MAI/bios_emulator/scitech/include/pmint.h b/board/MAI/bios_emulator/scitech/include/pmint.h new file mode 100644 index 0000000..7d76dad --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pmint.h @@ -0,0 +1,211 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Real mode and 16/32 bit Protected Mode +* +* Description: Header file for the interrupt handling extensions to the OS +* Portability Manager Library. These extensions includes +* simplified interrupt handling, allowing all common interrupt +* handlers to be hooked and handled directly with normal C +* functions, both in 16 bit and 32 bit modes. Note however that +* simplified handling does not mean slow performance! All low +* level interrupt handling is done efficiently in assembler +* for speed (well actually necessary to insulate the +* application from the lack of far pointers in 32 bit PM). The +* interrupt handlers currently supported are: +* +* Mouse (0x33 callback) +* Timer Tick (0x8) +* Keyboard (0x9 and 0x15) +* Control C/Break (0x23/0x1B) +* Critical Error (0x24) +* +****************************************************************************/ + +#ifndef __PMINT_H +#define __PMINT_H + +/*--------------------------- Macros and Typedefs -------------------------*/ + +#ifdef __SMX32__ +/* PC interrupts (Ensure consistent with pme.inc) */ +#define PM_IRQ0 0x40 +#define PM_IRQ1 (PM_IRQ0+1) +#define PM_IRQ6 (PM_IRQ0+6) +#define PM_IRQ14 (PM_IRQ0+14) +#endif + +/* Define the different types of interrupt handlers that we support */ + +typedef uint (PMAPIP PM_criticalHandler)(uint axValue,uint diValue); +typedef void (PMAPIP PM_breakHandler)(uint breakHit); +typedef short (PMAPIP PM_key15Handler)(short scanCode); +typedef void (PMAPIP PM_mouseHandler)(uint event, uint butstate,int x,int y,int mickeyX,int mickeyY); + +/* Create a type for representing far pointers in both 16 and 32 bit + * protected mode. + */ + +#ifdef PM386 +typedef struct { + long off; + short sel; + } PMFARPTR; +#define PMNULL {0,0} +#else +typedef void *PMFARPTR; +#define PMNULL NULL +#endif + +/*--------------------------- Function Prototypes -------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Routine to load save default data segment selector value into a code + * segment variable, and another to load the value into the DS register. + */ + +void PMAPI PM_loadDS(void); +void PMAPI PM_saveDS(void); + +/* Routine to install a mouse interrupt handling routine. The + * mouse handler routine is a normal C function, and the PM library + * will take care of passing the correct parameters to the function, + * and switching to a local stack. + * + * Note that you _must_ lock the memory containing the mouse interrupt + * handler with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + */ + +int PMAPI PM_setMouseHandler(int mask,PM_mouseHandler mh); +void PMAPI PM_restoreMouseHandler(void); + +/* Routine to reset the mouse driver, and re-install the current + * mouse interrupt handler if one was currently installed (since the + * mouse reset will automatically remove this handler. + */ + +void PMAPI PM_resetMouseDriver(int hardReset); + +/* Routine to reset the mouse driver, and re-install the current + * mouse interrupt handler if one was currently installed (since the + * mouse reset will automatically remove this handler. + */ + +void PMAPI PM_resetMouseDriver(int hardReset); + +/* Routines to install and remove timer interrupt handlers. + * + * Note that you _must_ lock the memory containing the interrupt + * handlers with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + */ + +void PMAPI PM_setTimerHandler(PM_intHandler ih); +void PMAPI PM_chainPrevTimer(void); +void PMAPI PM_restoreTimerHandler(void); + +/* Routines to install and keyboard interrupt handlers. + * + * Note that you _must_ lock the memory containing the interrupt + * handlers with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + */ + +void PMAPI PM_setKeyHandler(PM_intHandler ih); +void PMAPI PM_chainPrevKey(void); +void PMAPI PM_restoreKeyHandler(void); + +/* Routines to hook and unhook the alternate Int 15h keyboard intercept + * callout routine. Your event handler will need to return the following: + * + * scanCode - Let the BIOS process scan code (chains to previous handler) + * 0 - You have processed the scan code so flush from BIOS + * + * Note that this is not available under all DOS extenders, but does + * work under real mode, DOS4GW and X32-VM. It does not work under the + * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know! + */ + +void PMAPI PM_setKey15Handler(PM_key15Handler ih); +void PMAPI PM_restoreKey15Handler(void); + +/* Routines to install and remove the control c/break interrupt handlers. + * Interrupt handling is performed by the PM/Pro library, and you can call + * the supplied routines to test the status of the Ctrl-C and Ctrl-Break + * flags. If you pass the value TRUE for 'clearFlag' to these routines, + * the internal flags will be reset in order to catch another Ctrl-C or + * Ctrl-Break interrupt. + */ + +void PMAPI PM_installBreakHandler(void); +int PMAPI PM_ctrlCHit(int clearFlag); +int PMAPI PM_ctrlBreakHit(int clearFlag); +void PMAPI PM_restoreBreakHandler(void); + +/* Routine to install an alternate break handler that will call your + * code directly. This is not available under all DOS extenders, but does + * work under real mode, DOS4GW and X32-VM. It does not work under the + * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know! + * + * Note that you should either install one or the other, but not both! + */ + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh); + +/* Routines to install and remove the critical error handler. The interrupt + * is handled by the PM/Pro library, and the operation will always be failed. + * You can check the status of the critical error handler with the + * appropriate function. If you pass the value TRUE for 'clearFlag', the + * internal flag will be reset ready to catch another critical error. + */ + +void PMAPI PM_installCriticalHandler(void); +int PMAPI PM_criticalError(int *axValue, int *diValue, int clearFlag); +void PMAPI PM_restoreCriticalHandler(void); + +/* Routine to install an alternate critical handler that will call your + * code directly. This is not available under all DOS extenders, but does + * work under real mode, DOS4GW and X32-VM. It does not work under the + * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know! + * + * Note that you should either install one or the other, but not both! + */ + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler); + +/* Functions to manage protected mode only interrupt handlers */ + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr); +void PMAPI PM_setPMvect(int intno, PM_intHandler ih); +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __PMINT_H */ diff --git a/board/MAI/bios_emulator/scitech/include/scitech.h b/board/MAI/bios_emulator/scitech/include/scitech.h new file mode 100644 index 0000000..8d5eee9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/scitech.h @@ -0,0 +1,712 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: General header file for operating system portable code. +* +****************************************************************************/ + +#ifndef __SCITECH_H +#define __SCITECH_H + +/* We have the following defines to identify the compilation environment: + * + * __16BIT__ Compiling for 16 bit code (any environment) + * __32BIT__ Compiling for 32 bit code (any environment) + * __MSDOS__ Compiling for MS-DOS (includes __WINDOWS16__, __WIN386__) + * __REALDOS__ Compiling for MS-DOS (excludes __WINDOWS16__) + * __MSDOS16__ Compiling for 16 bit MS-DOS + * __MSDOS32__ Compiling for 32 bit MS-DOS + * __WINDOWS__ Compiling for Windows + * __WINDOWS16__ Compiling for 16 bit Windows (__MSDOS__ also defined) + * __WINDOWS32__ Compiling for 32 bit Windows + * __WIN32_VXD__ Compiling for a 32-bit C based VxD + * __NT_DRIVER__ Compiling for a 32-bit C based NT device driver + * __OS2__ Compiling for OS/2 + * __OS2_16__ Compiling for 16 bit OS/2 + * __OS2_32__ Compiling for 32 bit OS/2 + * __UNIX__ Compiling for Unix + * __QNX__ Compiling for the QNX realtime OS (Unix compatible) + * __LINUX__ Compiling for the Linux OS (Unix compatible) + * __FREEBSD__ Compiling for the FreeBSD OS (Unix compatible) + * __BEOS__ Compiling for the BeOS (Unix compatible) + * __SMX32__ Compiling for the SMX 32-bit Real Time OS + * __ENEA_OSE__ Compiling for the OSE embedded OS + * __RTTARGET__ Compiling for the RTTarget 32-bit embedded OS + * __MACOS__ Compiling for the MacOS platform (PowerPC) + * __DRIVER__ Compiling for a 32-bit binary compatible driver + * __CONSOLE__ Compiling for a fullscreen OS console mode + * __SNAP__ Compiling as a Snap executeable or dynamic library + * + * __INTEL__ Compiling for Intel CPU's + * __ALPHA__ Compiling for DEC Alpha CPU's + * __MIPS__ Compiling for MIPS CPU's + * __PPC__ Compiling for PowerPC CPU's + * __MC68K__ Compiling for Motorola 680x0 + * + * __BIG_ENDIAN__ Compiling for a big endian processor + * + */ + +#ifdef __SC__ +#if __INTSIZE == 4 +#define __SC386__ +#endif +#endif + +/* Determine some things that are compiler specific */ + +#ifdef __GNUC__ +#ifdef __cplusplus +/* G++ currently fucks this up! */ +#define __cdecl +#define __stdcall +#else +#undef __cdecl +#undef __stdcall +#define __cdecl __attribute__ ((cdecl)) +#define __stdcall __attribute__ ((stdcall)) +#endif +#define __FLAT__ /* GCC is always 32 bit flat model */ +#define __HAS_BOOL__ /* Latest GNU C++ has ibool type */ +#define __HAS_LONG_LONG__ /* GNU C supports long long type */ +#include /* Bring in for definition of NULL */ +#endif + +#ifdef __BORLANDC__ +#if (__BORLANDC__ >= 0x500) || defined(CLASSLIB_DEFS_H) +#define __HAS_BOOL__ /* Borland C++ 5.0 defines ibool type */ +#endif +#if (__BORLANDC__ >= 0x502) && !defined(VTOOLSD) && !defined(__SMX32__) +#define __HAS_INT64__ /* Borland C++ 5.02 supports __int64 type */ +#endif +#endif + +#if defined(_MSC_VER) && !defined(__SC__) && !defined(VTOOLSD) && !defined(__SMX32__) +#define __HAS_INT64__ /* Visual C++ supports __int64 type */ +#endif + +#if defined(__WATCOMC__) && (__WATCOMC__ >= 1100) && !defined(VTOOLSD) && !defined(__SMX32__) +#define __HAS_INT64__ /* Watcom C++ 11.0 supports __int64 type */ +#endif + +/*--------------------------------------------------------------------------- + * Determine the compile time environment. This must be done for each + * supported platform so that we can determine at compile time the target + * environment, hopefully without requiring #define's from the user. + *-------------------------------------------------------------------------*/ + +/* 32-bit binary compatible driver. Compiled as Win32, but as OS neutral */ +#ifdef __DRIVER__ +#ifndef __32BIT__ +#define __32BIT__ +#endif +#undef __WINDOWS__ +#undef _WIN32 +#undef __WIN32__ +#undef __NT__ + +/* 32-bit Snap exe or dll. Compiled as Win32, but as OS neutral */ +#elif defined(__SNAP__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#undef __WINDOWS__ +#undef _WIN32 +#undef __WIN32__ +#undef __NT__ + +/* 32-bit Windows VxD compile environment */ +#elif defined(__vtoolsd_h_) || defined(VTOOLSD) +#include +#define __WIN32_VXD__ +#ifndef __32BIT__ +#define __32BIT__ +#endif +#define _MAX_PATH 256 +#undef __WINDOWS32__ + +/* 32-bit Windows NT driver compile environment: TODO!! */ +#elif defined(__NT_DRIVER__) +#include "ntdriver.h" +#ifndef __32BIT__ +#define __32BIT__ +#endif +#define _MAX_PATH 256 +#undef __WINDOWS32__ + +/* 32-bit SMX compile environment */ +#elif defined(__SMX32__) +#ifndef __MSDOS__ +#define __MSDOS__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif + +/* 32-bit Enea OSE environment */ +#elif defined(__ENEA_OSE__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif + +/* 32-bit RTTarget-32 environment */ +#elif defined(__RTTARGET__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif + +/* 32-bit extended DOS compile environment */ +#elif defined(__MSDOS__) || defined(__MSDOS32__) || defined(__DOS__) || defined(__DPMI32__) || (defined(M_I86) && (!defined(__SC386__) && !defined(M_I386))) || defined(TNT) +#ifndef __MSDOS__ +#define __MSDOS__ +#endif +#if defined(__MSDOS32__) || defined(__386__) || defined(__FLAT__) || defined(__NT__) || defined(__SC386__) +#ifndef __MSDOS32__ +#define __MSDOS32__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __REALDOS__ +#define __REALDOS__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif + +/* 16-bit Windows compile environment */ +#elif (defined(_Windows) || defined(_WINDOWS)) && !defined(__DPMI16__) +#ifndef __16BIT__ +#define __16BIT__ +#endif +#ifndef __WINDOWS16__ +#define __WINDOWS16__ +#endif +#ifndef __WINDOWS__ +#define __WINDOWS__ +#endif +#ifndef __MSDOS__ +#define __MSDOS__ +#endif + +/* 16-bit DOS compile environment */ +#else +#ifndef __16BIT__ +#define __16BIT__ +#endif +#ifndef __MSDOS16__ +#define __MSDOS16__ +#endif +#ifndef __REALDOS__ +#define __REALDOS__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit Windows compile environment */ +#elif defined(WIN32) || defined(_WIN32) || defined(__WIN32__) || defined(__NT__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __WINDOWS32__ +#define __WINDOWS32__ +#endif +#ifndef _WIN32 +#define _WIN32 /* Microsoft Win32 SDK headers use _WIN32 */ +#endif +#ifndef WIN32 +#define WIN32 /* OpenGL headers use WIN32 */ +#endif +#ifndef __WINDOWS__ +#define __WINDOWS__ +#endif + +/* 32-bit OS/2 VDD compile environment */ +/* We're assuming (for now) that CL386 must be used */ +#elif defined(MSDOS) && defined(M_I386) +/* fixes necessary to compile with CL386 */ +#define __cdecl _cdecl +typedef unsigned int size_t; + +#include + +/* This should probably be somewhere else... */ +/* Inline eligible functions (we have no CRT libs for CL386) */ +#pragma intrinsic (strcpy, strcmp, strlen, strcat) +#pragma intrinsic (memcmp, memcpy, memset) + +#define __OS2_VDD__ +#ifndef __32BIT__ +#define __32BIT__ +#endif +#define CCHMAXPATH 256 +#define _MAX_PATH 256 +#ifndef __OS2__ +#define __OS2__ +#endif +#ifndef __OS2_32__ +#define __OS2_32__ +#endif + +/* 16-bit OS/2 compile environment */ +#elif defined(__OS2_16__) +#ifndef __OS2__ +#define __OS2__ +#endif +#ifndef __16BIT__ +#define __16BIT__ +#endif +#ifndef __OS2_PM__ +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit OS/2 compile environment */ +#elif defined(__OS2__) || defined(__OS2_32__) +#ifndef __OS2__ +#define __OS2__ +#endif +#ifndef __OS2_32__ +#define __OS2_32__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __OS2_PM__ +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit QNX compile environment */ +#elif defined(__QNX__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __UNIX__ +#define __UNIX__ +#endif +#ifdef __GNUC__ +#define stricmp strcasecmp +#endif +#if !defined(__PHOTON__) && !defined(__X11__) +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit Linux compile environment */ +#elif defined(__LINUX__) || defined(linux) +#ifndef __LINUX__ +#define __LINUX__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __UNIX__ +#define __UNIX__ +#endif +#ifdef __GNUC__ +#define stricmp strcasecmp +#endif +#ifndef __X11__ +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit FreeBSD compile environment */ +#elif defined(__FREEBSD__) +#ifndef __FREEBSD__ +#define __FREEBSD__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __UNIX__ +#define __UNIX__ +#endif +#ifdef __GNUC__ +#define stricmp strcasecmp +#endif +#ifndef __X11__ +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit BeOS compile environment */ +#elif defined(__BEOS__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __UNIX__ +#define __UNIX__ +#endif +#ifdef __GNUC__ +#define stricmp strcasecmp +#endif + +/* Unsupported OS! */ +#else +#error This platform is not currently supported! +#endif + +/* Determine the CPU type that we are compiling for */ + +#if defined(__M_ALPHA) || defined(__ALPHA_) || defined(__ALPHA) || defined(__alpha) +#ifndef __ALPHA__ +#define __ALPHA__ +#endif +#elif defined(__M_PPC) || defined(__POWERC) +#ifndef __PPC__ +#define __PPC__ +#endif +#elif defined(__M_MRX000) +#ifndef __MIPS__ +#define __MIPS__ +#endif +#else +#ifndef __INTEL__ +#define __INTEL__ /* Assume Intel if nothing found */ +#endif +#endif + +/* We have the following defines to define the calling conventions for + * publicly accesible functions: + * + * _PUBAPI - Compiler default calling conventions for all public 'C' functions + * _ASMAPI - Calling conventions for all public assembler functions + * _VARAPI - Modifiers for variables; Watcom C++ mangles C++ globals + * _STDCALL - Win32 __stdcall where possible, __cdecl if not supported + */ + +#if defined(_MSC_VER) && defined(_WIN32) && !defined(__SC__) +#define __PASCAL __stdcall +#else +#define __PASCAL __pascal +#endif + +#if defined(NO_STDCALL) +#define _STDCALL __cdecl +#else +#define _STDCALL __stdcall +#endif + +#ifdef __WATCOMC__ +#if (__WATCOMC__ >= 1050) +#define _VARAPI __cdecl +#else +#define _VARAPI +#endif +#else +#define _VARAPI +#endif + +#if defined(__IBMC__) || defined(__IBMCPP__) +#define PTR_DECL_IN_FRONT +#endif + +/* Define the calling conventions for all public functions. For simplicity + * we define all public functions as __cdecl calling conventions, so that + * they are the same across all compilers and runtime DLL's. + */ + +#define _PUBAPI __cdecl +#define _ASMAPI __cdecl + +/* Determine the syntax for declaring a function pointer with a + * calling conventions override. Most compilers require the calling + * convention to be declared in front of the '*', but others require + * it to be declared after the '*'. We handle both in here depending + * on what the compiler requires. + */ + +#ifdef PTR_DECL_IN_FRONT +#define _PUBAPIP * _PUBAPI +#define _ASMAPIP * _ASMAPI +#else +#define _PUBAPIP _PUBAPI * +#define _ASMAPIP _ASMAPI * +#endif + +/* Useful macros */ + +#define PRIVATE static +#define PUBLIC + +/* This HAS to be 0L for 16-bit real mode code to work!!! */ + +#ifndef NULL +# define _NULL 0L +# define NULL _NULL +#endif + +#ifndef MAX +# define MAX(a,b) ( ((a) > (b)) ? (a) : (b)) +#endif +#ifndef MIN +# define MIN(a,b) ( ((a) < (b)) ? (a) : (b)) +#endif +#ifndef ABS +# define ABS(a) ((a) >= 0 ? (a) : -(a)) +#endif +#ifndef SIGN +# define SIGN(a) ((a) > 0 ? 1 : -1) +#endif + +/* General typedefs */ + +#ifndef __GENDEFS +#define __GENDEFS +#if defined(__BEOS__) +#include +#else +#ifdef __LINUX__ +#include +#ifdef __STRICT_ANSI__ +typedef unsigned short ushort; +typedef unsigned long ulong; +typedef unsigned int uint; +#endif +#ifdef __KERNEL__ +#define __GENDEFS_2 +#endif +#else +#if !(defined(__QNXNTO__) && defined(GENERAL_STRUCT)) +typedef unsigned short ushort; +typedef unsigned long ulong; +#endif +typedef unsigned int uint; +#endif +typedef unsigned char uchar; +#endif +typedef int ibool; /* Integer boolean type */ +#ifdef USE_BOOL /* Only for older code */ +#ifndef __cplusplus +#define bool ibool /* Standard C */ +#else +#ifndef __HAS_BOOL__ +#define bool ibool /* Older C++ compilers */ +#endif +#endif /* __cplusplus */ +#endif /* USE_BOOL */ +#endif /* __GENDEFS */ + +/* More general typedefs compatible with Linux kernel code */ + +#ifndef __GENDEFS_2 +#define __GENDEFS_2 +typedef char s8; +typedef unsigned char u8; +typedef short s16; +typedef unsigned short u16; +#ifdef __16BIT__ +typedef long s32; +typedef unsigned long u32; +#else +typedef int s32; +typedef unsigned int u32; +#endif +typedef struct { + u32 low; + s32 high; + } __i64; +#ifdef __HAS_LONG_LONG__ +#define __NATIVE_INT64__ +typedef long long s64; +typedef unsigned long long u64; +#elif defined(__HAS_INT64__) && !defined(__16BIT__) +#define __NATIVE_INT64__ +typedef __int64 s64; +typedef unsigned __int64 u64; +#else +typedef __i64 s64; +typedef __i64 u64; +#endif +#endif + +/* Boolean truth values */ + +#undef false +#undef true +#undef NO +#undef YES +#undef FALSE +#undef TRUE +#define false 0 +#define true 1 +#define NO 0 +#define YES 1 +#define FALSE 0 +#define TRUE 1 + +/* Inline debugger interrupts for Watcom C++ and Borland C++ */ + +#ifdef __WATCOMC__ +void DebugInt(void); +#pragma aux DebugInt = \ + "int 3"; +void DebugVxD(void); +#pragma aux DebugVxD = \ + "int 1"; +#elif defined(__BORLANDC__) +#define DebugInt() __emit__(0xCC) +#define DebugVxD() {__emit__(0xCD); __emit__(0x01);} +#elif defined(_MSC_VER) +#define DebugInt() _asm int 0x3 +#define DebugVxD() _asm int 0x1 +#elif defined(__GNUC__) +#define DebugInt() asm volatile ("int $0x3") +#define DebugVxD() asm volatile ("int $0x1") +#else +void _ASMAPI DebugInt(void); +void _ASMAPI DebugVxD(void); +#endif + +/* Macros to break once and never break again */ + +#define DebugIntOnce() \ +{ \ + static ibool firstTime = true; \ + if (firstTime) { \ + firstTime = false; \ + DebugInt(); \ + } \ +} + +#define DebugVxDOnce() \ +{ \ + static ibool firstTime = true; \ + if (firstTime) { \ + firstTime = false; \ + DebugVxD(); \ + } \ +} + +/* Macros for linux string compatibility functions */ + +#ifdef __LINUX__ +#define stricmp strcasecmp +#define strnicmp strncasecmp +#endif + +/* Macros for NT driver string compatibility functions */ + +#ifdef __NT_DRIVER__ +#define stricmp _stricmp +#define strnicmp _strnicmp +#endif + +/* Get rid of some helaciously annoying Visual C++ warnings! */ + +#if defined(_MSC_VER) && !defined(__MWERKS__) && !defined(__SC__) +#pragma warning(disable:4761) /* integral size mismatch in argument; conversion supplied */ +#pragma warning(disable:4244) /* conversion from 'unsigned short ' to 'unsigned char ', possible loss of data */ +#pragma warning(disable:4018) /* '<' : signed/unsigned mismatch */ +#pragma warning(disable:4305) /* 'initializing' : truncation from 'const double' to 'float' */ +#endif + +/*--------------------------------------------------------------------------- + * Set of debugging macros used by the libraries. If the debug flag is + * set, they are turned on depending on the setting of the flag. User code + * can override the default functions called when a check fails, and the + * MGL does this so it can restore the system from graphics mode to display + * an error message. These functions also log information to the + * scitech.log file in the root directory of the hard drive when problems + * show up. + * + * If you set the value of CHECKED to be 2, it will also enable code to + * insert hard coded debugger interrupt into the source code at the line of + * code where the check fail. This is useful if you run the code under a + * debugger as it will break inside the debugger before exiting with a + * failure condition. + * + * Also for code compiled to run under Windows, we also call the + * OutputDebugString function to send the message to the system debugger + * such as Soft-ICE or WDEB386. Hence if you get any non-fatal warnings you + * will see those on the debugger terminal as well as in the log file. + *-------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line); +void _CHK_defaultFail(int fatal,const char *msg,const char *cond,const char *file,int line); + +#ifdef CHECKED +# define CHK(x) x +#if CHECKED > 1 +# define CHECK(p) \ + ((p) ? (void)0 : DebugInt(), \ + _CHK_fail(1,"Check failed: '%s', file %s, line %d\n", \ + #p, __FILE__, __LINE__)) +# define WARN(p) \ + ((p) ? (void)0 : DebugInt(), \ + _CHK_fail(0,"Warning: '%s', file %s, line %d\n", \ + #p, __FILE__, __LINE__)) +#else +# define CHECK(p) \ + ((p) ? (void)0 : \ + _CHK_fail(1,"Check failed: '%s', file %s, line %d\n", \ + #p, __FILE__, __LINE__)) +# define WARN(p) \ + ((p) ? (void)0 : \ + _CHK_fail(0,"Warning: '%s', file %s, line %d\n", \ + #p, __FILE__, __LINE__)) +#endif +# define LOGFATAL(msg) \ + _CHK_fail(1,"Fatal error: '%s', file %s, line %d\n", \ + msg, __FILE__, __LINE__) +# define LOGWARN(msg) \ + _CHK_fail(0,"Warning: '%s', file %s, line %d\n", \ + msg, __FILE__, __LINE__) +#else +# define CHK(x) +# define CHECK(p) ((void)0) +# define WARN(p) ((void)0) +# define LOGFATAL(msg) ((void)0) +# define LOGWARN(msg) ((void)0) +#endif + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __SCITECH_H */ diff --git a/board/MAI/bios_emulator/scitech/include/scitech.mac b/board/MAI/bios_emulator/scitech/include/scitech.mac new file mode 100644 index 0000000..27a2fc0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/scitech.mac @@ -0,0 +1,1321 @@ +;**************************************************************************** +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NetWide Assembler (NASM) or Turbo Assembler (TASM) +;* Environment: Any Intel Environment +;* +;* Description: Macros to provide memory model independant assembly language +;* module for C programming. Supports the large and flat memory +;* models. +;* +;* The defines that you should use when assembling modules that +;* use this macro package are: +;* +;* __LARGE__ Assemble for 16-bit large model +;* __FLAT__ Assemble for 32-bit FLAT memory model +;* __NOU__ No underscore for all external C labels +;* __NOU_VAR__ No underscore for global variables only +;* +;* The default settings are for 16-bit large memory model with +;* leading underscores for symbol names. +;* +;* The main intent of the macro file is to enable programmers +;* to write _one_ set of source that can be assembled to run +;* in either 16 bit real and protected modes or 32 bit +;* protected mode without the need to riddle the code with +;* 'if flatmodel' style conditional assembly (it is still there +;* but nicely hidden by a macro layer that enhances the +;* readability and understandability of the resulting code). +;* +;**************************************************************************** + +; Include the appropriate version in here depending on the assembler. NASM +; appears to always try and parse code, even if it is in a non-compiling +; block of a ifdef expression, and hence crashes if we include the TASM +; macro package in the same header file. Hence we split the macros up into +; two separate header files. + +ifdef __NASM_MAJOR__ + +;============================================================================ +; Macro package when compiling with NASM. +;============================================================================ + +; Turn off underscores for globals if disabled for all externals + +%ifdef __NOU__ +%define __NOU_VAR__ +%endif + +; Define the __WINDOWS__ symbol if we are compiling for any Windows +; environment + +%ifdef __WINDOWS16__ +%define __WINDOWS__ 1 +%endif +%ifdef __WINDOWS32__ +%define __WINDOWS__ 1 +%define __WINDOWS32_386__ 1 +%endif + +; Macros for accessing 'generic' registers + +%ifdef __FLAT__ +%idefine _ax eax +%idefine _bx ebx +%idefine _cx ecx +%idefine _dx edx +%idefine _si esi +%idefine _di edi +%idefine _bp ebp +%idefine _sp esp +%idefine _es +%idefine UCHAR BYTE ; Size of a character +%idefine USHORT WORD ; Size of a short +%idefine UINT DWORD ; Size of an integer +%idefine ULONG DWORD ; Size of a long +%idefine BOOL DWORD ; Size of a boolean +%idefine DPTR DWORD ; Size of a data pointer +%idefine FDPTR FWORD ; Size of a far data pointer +%idefine NDPTR DWORD ; Size of a near data pointer +%idefine CPTR DWORD ; Size of a code pointer +%idefine FCPTR FWORD ; Size of a far code pointer +%idefine NCPTR DWORD ; Size of a near code pointer +%idefine FPTR NEAR ; Distance for function pointers +%idefine DUINT dd ; Declare a integer variable +%idefine intsize 4 +%idefine flatmodel 1 +%else +%idefine _ax ax +%idefine _bx bx +%idefine _cx cx +%idefine _dx dx +%idefine _si si +%idefine _di di +%idefine _bp bp +%idefine _sp sp +%idefine _es es: +%idefine UCHAR BYTE ; Size of a character +%idefine USHORT WORD ; Size of a short +%idefine UINT WORD ; Size of an integer +%idefine ULONG DWORD ; Size of a long +%idefine BOOL WORD ; Size of a boolean +%idefine DPTR DWORD ; Size of a data pointer +%idefine FDPTR DWORD ; Size of a far data pointer +%idefine NDPTR WORD ; Size of a near data pointer +%idefine CPTR DWORD ; Size of a code pointer +%idefine FCPTR DWORD ; Size of a far code pointer +%idefine NCPTR WORD ; Size of a near code pointer +%idefine FPTR FAR ; Distance for function pointers +%idefine DUINT dw ; Declare a integer variable +%idefine intsize 2 +%endif +%idefine invert ~ +%idefine offset +%idefine use_nasm + +; Convert all jumps to near jumps, since NASM does not so this automatically + +%idefine jo jo near +%idefine jno jno near +%idefine jz jz near +%idefine jnz jnz near +%idefine je je near +%idefine jne jne near +%idefine jb jb near +%idefine jbe jbe near +%idefine ja ja near +%idefine jae jae near +%idefine jl jl near +%idefine jle jle near +%idefine jg jg near +%idefine jge jge near +%idefine jc jc near +%idefine jnc jnc near +%idefine js js near +%idefine jns jns near + +%ifdef DOUBLE +%idefine REAL QWORD +%idefine DREAL dq +%else +%idefine REAL DWORD +%idefine DREAL dd +%endif + +; Boolean truth values (same as those in debug.h) + +%idefine False 0 +%idefine True 1 +%idefine No 0 +%idefine Yes 1 +%idefine Yes 1 + +; Macro to be invoked at the start of all modules to set up segments for +; later use. Does nothing for NASM. + +%imacro header 1 +%endmacro + +; Macro to begin a data segment + +%imacro begdataseg 1 +%ifdef __GNUC__ +segment .data public class=DATA use32 flat +%else +%ifdef flatmodel +segment _DATA public align=4 class=DATA use32 flat +%else +segment _DATA public align=4 class=DATA use16 +%endif +%endif +%endmacro + +; Macro to end a data segment + +%imacro enddataseg 1 +%endmacro + +; Macro to begin a code segment + +%imacro begcodeseg 1 +%ifdef __PIC__ +%ifdef __LINUX__ + extern _GLOBAL_OFFSET_TABLE_ +%else + extern __GLOBAL_OFFSET_TABLE_ +%endif +%endif +%ifdef __GNUC__ +segment .text public class=CODE use32 flat +%else +%ifdef flatmodel +segment _TEXT public align=16 class=CODE use32 flat +%else +segment %1_TEXT public align=16 class=CODE use16 +%endif +%endif +%endmacro + +; Macro to begin a near code segment + +%imacro begcodeseg_near 0 +%ifdef __GNUC__ +segment .text public class=CODE use32 flat +%else +%ifdef flatmodel +segment _TEXT public align=16 class=CODE use32 flat +%else +segment _TEXT public align=16 class=CODE use16 +%endif +%endif +%endmacro + +; Macro to end a code segment + +%imacro endcodeseg 1 +%endmacro + +; Macro to end a near code segment + +%imacro endcodeseg_near 0 +%endmacro + +; Macro for an extern C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +%imacro cextern 2 +%ifdef __NOU_VAR__ +extern %1 +%else +extern _%1 +%define %1 _%1 +%endif +%endmacro + +%imacro cexternfunc 2 +%ifdef __NOU__ +extern %1 +%else +extern _%1 +%define %1 _%1 +%endif +%endmacro + +; Macro for a public C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +%imacro cpublic 1 +%ifdef __NOU_VAR__ +global %1 +%1: +%else +global _%1 +_%1: +%define %1 _%1 +%endif +%endmacro + +; Macro for an global C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +%imacro cglobal 1 +%ifdef __NOU_VAR__ +global %1 +%else +global _%1 +%define %1 _%1 +%endif +%endmacro + +; Macro for an global C function symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +%imacro cglobalfunc 1 +%ifdef __PIC__ +global %1:function +%else +%ifdef __NOU__ +global %1 +%else +global _%1 +%define %1 _%1 +%endif +%endif +%endmacro + +; Macro to start a C callable function. This will be a far function for +; 16-bit code, and a near function for 32-bit code. + +%imacro cprocstatic 1 +%push cproc +%1: +%ifdef flatmodel +%stacksize flat +%define ret retn +%else +%stacksize large +%define ret retf +%endif +%assign %$localsize 0 +%endmacro + +%imacro cprocstart 1 +%push cproc + cglobalfunc %1 +%1: +%ifdef flatmodel +%stacksize flat +%define ret retn +%else +%stacksize large +%define ret retf +%endif +%assign %$localsize 0 +%endmacro + +; This macro sets up a procedure to be exported from a 16 bit DLL. Since the +; calling conventions are always _far _pascal for 16 bit DLL's, we actually +; rename this routine with an extra underscore with 'C' calling conventions +; and a small DLL stub will be provided by the high level code to call the +; assembler routine. + +%imacro cprocstartdll16 1 +%ifdef __WINDOWS16__ +cprocstart _%1 +%else +cprocstart %1 +%endif +%endmacro + +; Macro to start a C callable near function. + +%imacro cprocnear 1 +%push cproc + cglobalfunc %1 +%1: +%define ret retn +%ifdef flatmodel +%stacksize flat +%else +%stacksize small +%endif +%assign %$localsize 0 +%endmacro + +; Macro to start a C callable far function. + +%imacro cprocfar 1 +%push cproc + cglobalfunc %1 +%1: +%define ret retf +%ifdef flatmodel +%stacksize flat +%else +%stacksize large +%endif +%assign %$localsize 0 +%endmacro + +; Macro to end a C function + +%imacro cprocend 0 +%pop +%endmacro + +; Macros for entering and exiting C callable functions. Note that we must +; always save and restore the SI and DI registers for C functions, and for +; 32 bit C functions we also need to save and restore EBX and clear the +; direction flag. + +%imacro enter_c 0 + push _bp + mov _bp,_sp +%ifnidn %$localsize,0 + sub _sp,%$localsize +%endif +%ifdef flatmodel + push ebx +%endif + push _si + push _di +%endmacro + +%imacro leave_c 0 + pop _di + pop _si +%ifdef flatmodel + pop ebx + cld +%endif +%ifnidn %$localsize,0 + mov _sp,_bp +%endif + pop _bp +%endmacro + +%imacro use_ebx 0 +%ifdef flatmodel + push ebx +%endif +%endmacro + +%imacro unuse_ebx 0 +%ifdef flatmodel + pop ebx +%endif +%endmacro + +; Macros for saving and restoring the value of DS,ES,FS,GS when it is to +; be used in assembly routines. This evaluates to nothing in the flat memory +; model, but is saves and restores DS in the large memory model. + +%imacro use_ds 0 +%ifndef flatmodel + push ds +%endif +%endmacro + +%imacro unuse_ds 0 +%ifndef flatmodel + pop ds +%endif +%endmacro + +%imacro use_es 0 +%ifndef flatmodel + push es +%endif +%endmacro + +%imacro unuse_es 0 +%ifndef flatmodel + pop es +%endif +%endmacro + +; Macros for loading the address of a data pointer into a segment and +; index register pair. The %imacro explicitly loads DS or ES in the 16 bit +; memory model, or it simply loads the offset into the register in the flat +; memory model since DS and ES always point to all addressable memory. You +; must use the correct _REG (ie: _BX) %imacros for documentation purposes. + +%imacro _lds 2 +%ifdef flatmodel + mov %1,%2 +%else + lds %1,%2 +%endif +%endmacro + +%imacro _les 2 +%ifdef flatmodel + mov %1,%2 +%else + les %1,%2 +%endif +%endmacro + +; Macros for adding and subtracting a value from registers. Two value are +; provided, one for 16 bit modes and another for 32 bit modes (the extended +; register is used in 32 bit modes). + +%imacro _add 3 +%ifdef flatmodel + add e%1, %3 +%else + add %1, %2 +%endif +%endmacro + +%imacro _sub 3 +%ifdef flatmodel + sub e%1, %3 +%else + sub %1, %2 +%endif +%endmacro + +; Macro to clear the high order word for the 32 bit extended registers. +; This is used to convert an unsigned 16 bit value to an unsigned 32 bit +; value, and will evaluate to nothing in 16 bit modes. + +%imacro clrhi 1 +%ifdef flatmodel + movzx e%1,%1 +%endif +%endmacro + +%imacro sgnhi 1 +%ifdef flatmodel + movsx e%1,%1 +%endif +%endmacro + +; Macro to load an extended register with an integer value in either mode + +%imacro loadint 2 +%ifdef flatmodel + mov e%1,%2 +%else + xor e%1,e%1 + mov %1,%2 +%endif +%endmacro + +; Macros to load and store integer values with string instructions + +%imacro LODSINT 0 +%ifdef flatmodel + lodsd +%else + lodsw +%endif +%endmacro + +%imacro STOSINT 0 +%ifdef flatmodel + stosd +%else + stosw +%endif +%endmacro + +; Macros to provide resb, resw, resd compatibility with NASM + +%imacro dclb 1 +times %1 db 0 +%endmacro + +%imacro dclw 1 +times %1 dw 0 +%endmacro + +%imacro dcld 1 +times %1 dd 0 +%endmacro + +; Macro to get the addres of the GOT for Linux/FreeBSD shared +; libraries into the EBX register. + +%imacro get_GOT 1 + call %%getgot +%%getgot: pop %1 + add %1,_GLOBAL_OFFSET_TABLE_+$$-%%getgot wrt ..gotpc +%endmacro + +; Macro to get the address of a *local* variable that is global to +; a single module in a manner that will work correctly when compiled +; into a Linux shared library. Note that this will *not* work for +; variables that are defined as global to all modules. For that +; use the LEA_G macro + +%macro LEA_L 2 +%ifdef __PIC__ + get_GOT %1 + lea %1,[%1+%2 wrt ..gotoff] +%else + lea %1,[%2] +%endif +%endmacro + +; Same macro as above but for global variables public to *all* +; modules. + +%macro LEA_G 2 +%ifdef __PIC__ + get_GOT %1 + mov %1,[%1+%2 wrt ..got] +%else + lea %1,[%2] +%endif +%endmacro + +; macros to declare assembler function stubs for function structures + +%imacro BEGIN_STUBS_DEF 2 +begdataseg _STUBS +%ifdef __NOU_VAR__ +extern %1 +%define STUBS_START %1 +%else +extern _%1 +%define STUBS_START _%1 +%endif +enddataseg _STUBS +begcodeseg _STUBS +%assign off %2 +%endmacro + +%imacro DECLARE_STUB 1 +%ifdef __PIC__ + global %1:function +%1: + get_GOT eax + mov eax,[eax+STUBS_START wrt ..got] + jmp [eax+off] +%else +%ifdef __NOU__ + global %1 +%1: +%else + global _%1 +_%1: +%endif + jmp [DWORD STUBS_START+off] +%endif +%assign off off+4 +%endmacro + +%imacro SKIP_STUB 1 +%assign off off+4 +%endmacro + +%imacro DECLARE_STDCALL 2 +%ifdef STDCALL_MANGLE + global _%1@%2 +_%1@%2: +%else +%ifdef STDCALL_USCORE + global _%1 +_%1: +%else + global %1 +%1: +%endif +%endif + jmp [DWORD STUBS_START+off] +%assign off off+4 +%endmacro + +%imacro END_STUBS_DEF 0 +endcodeseg _STUBS +%endmacro + +; macros to declare assembler import stubs for binary loadable drivers + +%imacro BEGIN_IMPORTS_DEF 1 +BEGIN_STUBS_DEF %1,4 +%endmacro + +%imacro DECLARE_IMP 2 +DECLARE_STUB %1 +%endmacro + +%imacro SKIP_IMP 2 +SKIP_STUB %1 +%endmacro + +%imacro SKIP_IMP2 1 +DECLARE_STUB %1 +%endmacro + +%imacro SKIP_IMP3 1 +SKIP_STUB %1 +%endmacro + +%imacro END_IMPORTS_DEF 0 +END_STUBS_DEF +%endmacro + +else ; __NASM_MAJOR__ + +;============================================================================ +; Macro package when compiling with TASM. +;============================================================================ + +; Turn off underscores for globals if disabled for all externals + +ifdef __NOU__ +__NOU_VAR__ = 1 +endif + +; Define the __WINDOWS__ symbol if we are compiling for any Windows +; environment + +ifdef __WINDOWS16__ +__WINDOWS__ = 1 +endif +ifdef __WINDOWS32__ +__WINDOWS__ = 1 +__WINDOWS32_386__ = 1 +endif +ifdef __WIN386__ +__WINDOWS__ = 1 +__WINDOWS32_386__ = 1 +endif +ifdef __VXD__ +__WINDOWS__ = 1 +__WINDOWS32_386__ = 1 + MASM + .386 + NO_SEGMENTS = 1 + include vmm.inc ; IGNORE DEPEND + include vsegment.inc ; IGNORE DEPEND + IDEAL +endif + +; Macros for accessing 'generic' registers + +ifdef __FLAT__ + _ax EQU eax ; EAX is used for accumulator + _bx EQU ebx ; EBX is used for accumulator + _cx EQU ecx ; ECX is used for looping + _dx EQU edx ; EDX is used for data register + _si EQU esi ; ESI is the source index register + _di EQU edi ; EDI is the destination index register + _bp EQU ebp ; EBP is used for base pointer register + _sp EQU esp ; ESP is used for stack pointer register + _es EQU ; ES and DS are the same in 32 bit PM + typedef UCHAR BYTE ; Size of a character + typedef USHORT WORD ; Size of a short + typedef UINT DWORD ; Size of an integer + typedef ULONG DWORD ; Size of a long + typedef BOOL DWORD ; Size of a boolean + typedef DPTR DWORD ; Size of a data pointer + typedef FDPTR FWORD ; Size of a far data pointer + typedef NDPTR DWORD ; Size of a near data pointer + typedef CPTR DWORD ; Size of a code pointer + typedef FCPTR FWORD ; Size of a far code pointer + typedef NCPTR DWORD ; Size of a near code pointer + typedef DUINT DWORD ; Declare a integer variable + FPTR EQU NEAR ; Distance for function pointers + intsize = 4 ; Size of an integer + flatmodel = 1 ; This is a flat memory model + P386 ; Turn on 386 code generation + MODEL FLAT ; Set up for 32 bit simplified FLAT model +else + _ax EQU ax ; AX is used for accumulator + _bx EQU bx ; BX is used for accumulator + _cx EQU cx ; CX is used for looping + _dx EQU dx ; DX is used for data register + _si EQU si ; SI is the source index register + _di EQU di ; DI is the destination index register + _bp EQU bp ; BP is used for base pointer register + _sp EQU sp ; SP is used for stack pointer register + _es EQU es: ; ES is used for segment override + typedef UCHAR BYTE ; Size of a character + typedef USHORT WORD ; Size of a short + typedef UINT WORD ; Size of an integer + typedef ULONG DWORD ; Size of a long + typedef BOOL WORD ; Size of a boolean + typedef DPTR DWORD ; Size of a data pointer + typedef FDPTR DWORD ; Size of a far data pointer + typedef NDPTR WORD ; Size of a near data pointer + typedef CPTR DWORD ; Size of a code pointer + typedef FCPTR DWORD ; Size of a far code pointer + typedef NCPTR WORD ; Size of a near code pointer + typedef DUINT WORD ; Declare a integer variable + FPTR EQU FAR ; Distance for function pointers + intsize = 2 ; Size of an integer + P386 ; Turn on 386 code generation +endif + invert EQU not + +; Provide a typedef for real floating point numbers + +ifdef DOUBLE +typedef REAL QWORD +typedef DREAL QWORD +else +typedef REAL DWORD +typedef DREAL DWORD +endif + +; Macros to access the floating point stack registers to convert them +; from NASM style to TASM style + +st0 EQU st(0) +st1 EQU st(1) +st2 EQU st(2) +st3 EQU st(3) +st4 EQU st(4) +st5 EQU st(5) +st6 EQU st(6) +st7 EQU st(7) +st8 EQU st(8) + +; Boolean truth values (same as those in debug.h) + +ifndef __VXD__ +False = 0 +True = 1 +No = 0 +Yes = 1 +Yes = 1 +endif + +; Macros for the _DATA data segment. This segment contains initialised data. + +MACRO begdataseg name +ifdef __VXD__ + MASM +VXD_LOCKED_DATA_SEG + IDEAL +else +ifdef flatmodel + DATASEG +else +SEGMENT _DATA DWORD PUBLIC USE16 'DATA' +endif +endif +ENDM + +MACRO enddataseg name +ifdef __VXD__ + MASM +VXD_LOCKED_DATA_ENDS + IDEAL +else +ifndef flatmodel +ENDS _DATA +endif +endif +ENDM + +; Macro for the main code segment. + +MACRO begcodeseg name +ifdef __VXD__ + MASM +VXD_LOCKED_CODE_SEG + IDEAL +else +ifdef flatmodel + CODESEG + ASSUME CS:FLAT,DS:FLAT,SS:FLAT +else +SEGMENT &name&_TEXT PARA PUBLIC USE16 'CODE' + ASSUME CS:&name&_TEXT,DS:_DATA +endif +endif +ENDM + +; Macro for a near code segment + +MACRO begcodeseg_near +ifdef flatmodel + CODESEG + ASSUME CS:FLAT,DS:FLAT,SS:FLAT +else +SEGMENT _TEXT PARA PUBLIC USE16 'CODE' + ASSUME CS:_TEXT,DS:_DATA +endif +ENDM + +MACRO endcodeseg name +ifdef __VXD__ + MASM +VXD_LOCKED_CODE_ENDS + IDEAL +else +ifndef flatmodel +ENDS &name&_TEXT +endif +endif +ENDM + +MACRO endcodeseg_near +ifndef flatmodel +ENDS _TEXT +endif +ENDM + +; Macro to be invoked at the start of all modules to set up segments for +; later use. + +MACRO header name +begdataseg name +enddataseg name +ENDM + +; Macro for an extern C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +MACRO cextern name,size +ifdef __NOU_VAR__ + EXTRN name:size +else + EXTRN _&name&:size +name EQU _&name& +endif +ENDM + +MACRO cexternfunc name,size +ifdef __NOU__ + EXTRN name:size +else + EXTRN _&name&:size +name EQU _&name& +endif +ENDM + +MACRO stdexternfunc name,num_args,size +ifdef STDCALL_MANGLE + EXTRN _&name&@&num_args&:size +name EQU _&name&@&num_args +else + EXTRN name:size +endif +ENDM + +; Macro for a public C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +MACRO cpublic name +ifdef __NOU_VAR__ +name: + PUBLIC name +else +_&name&: + PUBLIC _&name& +name EQU _&name& +endif +ENDM + +; Macro for an global C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +MACRO cglobal name +ifdef __NOU_VAR__ + PUBLIC name +else + PUBLIC _&name& +name EQU _&name& +endif +ENDM + +; Macro for an global C function symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +MACRO cglobalfunc name +ifdef __NOU__ + PUBLIC name +else + PUBLIC _&name& +name EQU _&name& +endif +ENDM + +; Macro to start a C callable function. This will be a far function for +; 16-bit code, and a near function for 32-bit code. + +MACRO cprocstatic name ; Set up model independant private proc +ifdef flatmodel +PROC name NEAR +else +PROC name FAR +endif +LocalSize = 0 +ENDM + +MACRO cprocstart name ; Set up model independant proc +ifdef flatmodel +ifdef __NOU__ +PROC name NEAR +else +PROC _&name& NEAR +endif +else +ifdef __NOU__ +PROC name FAR +else +PROC _&name& FAR +endif +endif +LocalSize = 0 + cglobalfunc name +ENDM + +MACRO cprocnear name ; Set up near proc +ifdef __NOU__ +PROC name NEAR +else +PROC _&name& NEAR +endif +LocalSize = 0 + cglobalfunc name +ENDM + +MACRO cprocfar name ; Set up far proc +ifdef __NOU__ +PROC name FAR +else +PROC _&name& FAR +endif +LocalSize = 0 + cglobalfunc name +ENDM + +MACRO cprocend ; End procedure macro +ENDP +ENDM + +; This macro sets up a procedure to be exported from a 16 bit DLL. Since the +; calling conventions are always _far _pascal for 16 bit DLL's, we actually +; rename this routine with an extra underscore with 'C' calling conventions +; and a small DLL stub will be provided by the high level code to call the +; assembler routine. + +MACRO cprocstartdll16 name +ifdef __WINDOWS16__ +cprocstart _&name& +else +cprocstart name +endif +ENDM + +; Macros for entering and exiting C callable functions. Note that we must +; always save and restore the SI and DI registers for C functions, and for +; 32 bit C functions we also need to save and restore EBX and clear the +; direction flag. + +MACRO save_c_regs +ifdef flatmodel + push ebx +endif + push _si + push _di +ENDM + +MACRO enter_c + push _bp + mov _bp,_sp + IFDIFI ,<0> + sub _sp,LocalSize + ENDIF + save_c_regs +ENDM + +MACRO restore_c_regs + pop _di + pop _si +ifdef flatmodel + pop ebx +endif +ENDM + +MACRO leave_c + restore_c_regs + cld + IFDIFI ,<0> + mov _sp,_bp + ENDIF + pop _bp +ENDM + +MACRO use_ebx +ifdef flatmodel + push ebx +endif +ENDM + +MACRO unuse_ebx +ifdef flatmodel + pop ebx +endif +ENDM + +; Macros for saving and restoring the value of DS,ES,FS,GS when it is to +; be used in assembly routines. This evaluates to nothing in the flat memory +; model, but is saves and restores DS in the large memory model. + +MACRO use_ds +ifndef flatmodel + push ds +endif +ENDM + +MACRO unuse_ds +ifndef flatmodel + pop ds +endif +ENDM + +MACRO use_es +ifndef flatmodel + push es +endif +ENDM + +MACRO unuse_es +ifndef flatmodel + pop es +endif +ENDM + +; Macros for loading the address of a data pointer into a segment and +; index register pair. The macro explicitly loads DS or ES in the 16 bit +; memory model, or it simply loads the offset into the register in the flat +; memory model since DS and ES always point to all addressable memory. You +; must use the correct _REG (ie: _BX) macros for documentation purposes. + +MACRO _lds reg, addr +ifdef flatmodel + mov reg,addr +else + lds reg,addr +endif +ENDM + +MACRO _les reg, addr +ifdef flatmodel + mov reg,addr +else + les reg,addr +endif +ENDM + +; Macros for adding and subtracting a value from registers. Two value are +; provided, one for 16 bit modes and another for 32 bit modes (the extended +; register is used in 32 bit modes). + +MACRO _add reg, val16, val32 +ifdef flatmodel + add e®&, val32 +else + add reg, val16 +endif +ENDM + +MACRO _sub reg, val16, val32 +ifdef flatmodel + sub e®&, val32 +else + sub reg, val16 +endif +ENDM + +; Macro to clear the high order word for the 32 bit extended registers. +; This is used to convert an unsigned 16 bit value to an unsigned 32 bit +; value, and will evaluate to nothing in 16 bit modes. + +MACRO clrhi reg +ifdef flatmodel + movzx e®&,reg +endif +ENDM + +MACRO sgnhi reg +ifdef flatmodel + movsx e®&,reg +endif +ENDM + +; Macro to load an extended register with an integer value in either mode + +MACRO loadint reg,val +ifdef flatmodel + mov e®&,val +else + xor e®&,e®& + mov reg,val +endif +ENDM + +; Macros to load and store integer values with string instructions + +MACRO LODSINT +ifdef flatmodel + lodsd +else + lodsw +endif +ENDM + +MACRO STOSINT +ifdef flatmodel + stosd +else + stosw +endif +ENDM + +; Macros to provide resb, resw, resd compatibility with NASM + +MACRO dclb count +db count dup (0) +ENDM + +MACRO dclw count +dw count dup (0) +ENDM + +MACRO dcld count +dd count dup (0) +ENDM + +; Macros to provide resb, resw, resd compatibility with NASM + +MACRO resb count +db count dup (?) +ENDM + +MACRO resw count +dw count dup (?) +ENDM + +MACRO resd count +dd count dup (?) +ENDM + +; Macros to declare assembler stubs for function structures + +MACRO BEGIN_STUBS_DEF name, firstOffset +begdataseg _STUBS +ifdef __NOU_VAR__ + EXTRN name:DWORD +STUBS_START = name +else + EXTRN _&name&:DWORD +name EQU _&name& +STUBS_START = _&name +endif +enddataseg _STUBS +begcodeseg _STUBS +off = firstOffset +ENDM + +MACRO DECLARE_STUB name +ifdef __NOU__ +name: + PUBLIC name +else +_&name: + PUBLIC _&name +endif + jmp [DWORD STUBS_START+off] +off = off + 4 +ENDM + +MACRO SKIP_STUB name +off = off + 4 +ENDM + +MACRO DECLARE_STDCALL name,num_args +ifdef STDCALL_MANGLE +_&name&@&num_args&: + PUBLIC _&name&@&num_args& +else +name: + PUBLIC name +endif + jmp [DWORD STUBS_START+off] +off = off + 4 +ENDM + +MACRO END_STUBS_DEF +endcodeseg _STUBS +ENDM + +MACRO BEGIN_IMPORTS_DEF name +BEGIN_STUBS_DEF name,4 +ENDM + +ifndef LOCAL_DECLARE_IMP +MACRO DECLARE_IMP name, numArgs +DECLARE_STUB name +ENDM + +MACRO SKIP_IMP name +SKIP_STUB name +ENDM + +MACRO SKIP_IMP2 name, numArgs +DECLARE_STUB name +ENDM + +MACRO SKIP_IMP3 name +SKIP_STUB name +ENDM +endif + +MACRO END_IMPORTS_DEF +END_STUBS_DEF +ENDM + +MACRO LEA_L reg,name + lea reg,[name] +ENDM + +MACRO LEA_G reg,name + lea reg,[name] +ENDM + +endif + diff --git a/board/MAI/bios_emulator/scitech/include/x86emu.h b/board/MAI/bios_emulator/scitech/include/x86emu.h new file mode 100644 index 0000000..1d87d4e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/x86emu.h @@ -0,0 +1,194 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for public specific functions. +* Any application linking against us should only +* include this header +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMU_H +#define __X86EMU_X86EMU_H + +#ifdef SCITECH +#include "scitech.h" +#define X86API _ASMAPI +#define X86APIP _ASMAPIP +typedef int X86EMU_pioAddr; +#else +#include "x86emu/types.h" +#define X86API +#define X86APIP * +#endif +#include "x86emu/regs.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/**************************************************************************** +REMARKS: +Data structure containing ponters to programmed I/O functions used by the +emulator. This is used so that the user program can hook all programmed +I/O for the emulator to handled as necessary by the user program. By +default the emulator contains simple functions that do not do access the +hardware in any way. To allow the emualtor access the hardware, you will +need to override the programmed I/O functions using the X86EMU_setupPioFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +inb - Function to read a byte from an I/O port +inw - Function to read a word from an I/O port +inl - Function to read a dword from an I/O port +outb - Function to write a byte to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port +****************************************************************************/ +typedef struct { + u8 (X86APIP inb)(X86EMU_pioAddr addr); + u16 (X86APIP inw)(X86EMU_pioAddr addr); + u32 (X86APIP inl)(X86EMU_pioAddr addr); + void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); + void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); + void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); + } X86EMU_pioFuncs; + +/**************************************************************************** +REMARKS: +Data structure containing ponters to memory access functions used by the +emulator. This is used so that the user program can hook all memory +access functions as necessary for the emulator. By default the emulator +contains simple functions that only access the internal memory of the +emulator. If you need specialised functions to handle access to different +types of memory (ie: hardware framebuffer accesses and BIOS memory access +etc), you will need to override this using the X86EMU_setupMemFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +rdb - Function to read a byte from an address +rdw - Function to read a word from an address +rdl - Function to read a dword from an address +wrb - Function to write a byte to an address +wrw - Function to write a word to an address +wrl - Function to write a dword to an address +****************************************************************************/ +typedef struct { + u8 (X86APIP rdb)(u32 addr); + u16 (X86APIP rdw)(u32 addr); + u32 (X86APIP rdl)(u32 addr); + void (X86APIP wrb)(u32 addr, u8 val); + void (X86APIP wrw)(u32 addr, u16 val); + void (X86APIP wrl)(u32 addr, u32 val); + } X86EMU_memFuncs; + +/**************************************************************************** + Here are the default memory read and write + function in case they are needed as fallbacks. +***************************************************************************/ +extern u8 X86API rdb(u32 addr); +extern u16 X86API rdw(u32 addr); +extern u32 X86API rdl(u32 addr); +extern void X86API wrb(u32 addr, u8 val); +extern void X86API wrw(u32 addr, u16 val); +extern void X86API wrl(u32 addr, u32 val); + +#pragma pack() + +/*--------------------- type definitions -----------------------------------*/ + +typedef void (X86APIP X86EMU_intrFuncs)(int num); +extern X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); +void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); +void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); +void X86EMU_prepareForInt(int num); + +/* decode.c */ + +void X86EMU_exec(void); +void X86EMU_halt_sys(void); + +#ifdef DEBUG +#define HALT_SYS() \ + printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ + X86EMU_halt_sys() +#else +#define HALT_SYS() X86EMU_halt_sys() +#endif + +/* Debug options */ + +#define DEBUG_DECODE_F 0x0001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x0002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x0004 +#define DEBUG_DISASSEMBLE_F 0x0008 +#define DEBUG_BREAK_F 0x0010 +#define DEBUG_SVC_F 0x0020 +#define DEBUG_SAVE_CS_IP 0x0040 +#define DEBUG_FS_F 0x0080 +#define DEBUG_PROC_F 0x0100 +#define DEBUG_SYSINT_F 0x0200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x0400 +#define DEBUG_INSTRUMENT_F 0x0800 +#define DEBUG_MEM_TRACE_F 0x1000 +#define DEBUG_IO_TRACE_F 0x2000 +#define DEBUG_TRACECALL_REGS_F 0x4000 +#define DEBUG_DECODE_NOPRINT_F 0x8000 +#define DEBUG_EXIT 0x10000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) + +void X86EMU_trace_regs(void); +void X86EMU_trace_xregs(void); +void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); +int X86EMU_trace_on(void); +int X86EMU_trace_off(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMU_H */ diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h b/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h new file mode 100644 index 0000000..777b03c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h @@ -0,0 +1,115 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_REGS_H +#define __X86EMU_FPU_REGS_H + +#ifdef X86_FPU_SUPPORT + +#pragma pack(1) + +/* Basic 8087 register can hold any of the following values: */ + +union x86_fpu_reg_u { + s8 tenbytes[10]; + double dval; + float fval; + s16 sval; + s32 lval; + }; + +struct x86_fpu_reg { + union x86_fpu_reg_u reg; + char tag; + }; + +/* + * Since we are not going to worry about the problems of aliasing + * registers, every time a register is modified, its result type is + * set in the tag fields for that register. If some operation + * attempts to access the type in a way inconsistent with its current + * storage format, then we flag the operation. If common, we'll + * attempt the conversion. + */ + +#define X86_FPU_VALID 0x80 +#define X86_FPU_REGTYP(r) ((r) & 0x7F) + +#define X86_FPU_WORD 0x0 +#define X86_FPU_SHORT 0x1 +#define X86_FPU_LONG 0x2 +#define X86_FPU_FLOAT 0x3 +#define X86_FPU_DOUBLE 0x4 +#define X86_FPU_LDBL 0x5 +#define X86_FPU_BSD 0x6 + +#define X86_FPU_STKTOP 0 + +struct x86_fpu_registers { + struct x86_fpu_reg x86_fpu_stack[8]; + int x86_fpu_flags; + int x86_fpu_config; /* rounding modes, etc. */ + short x86_fpu_tos, x86_fpu_bos; + }; + +#pragma pack() + +/* + * There are two versions of the following macro. + * + * One version is for opcode D9, for which there are more than 32 + * instructions encoded in the second byte of the opcode. + * + * The other version, deals with all the other 7 i87 opcodes, for + * which there are only 32 strings needed to describe the + * instructions. + */ + +#endif /* X86_FPU_SUPPORT */ + +#ifdef DEBUG +# define DECODE_PRINTINSTR32(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<3)+(rh)]); +# define DECODE_PRINTINSTR256(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); +#else +# define DECODE_PRINTINSTR32(t,mod,rh,rl) +# define DECODE_PRINTINSTR256(t,mod,rh,rl) +#endif + +#endif /* __X86EMU_FPU_REGS_H */ diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/regs.h b/board/MAI/bios_emulator/scitech/include/x86emu/regs.h new file mode 100644 index 0000000..a12017b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/x86emu/regs.h @@ -0,0 +1,331 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_REGS_H +#define __X86EMU_REGS_H + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/* + * General EAX, EBX, ECX, EDX type registers. Note that for + * portability, and speed, the issue of byte swapping is not addressed + * in the registers. All registers are stored in the default format + * available on the host machine. The only critical issue is that the + * registers should line up EXACTLY in the same manner as they do in + * the 386. That is: + * + * EAX & 0xff === AL + * EAX & 0xffff == AX + * + * etc. The result is that alot of the calculations can then be + * done using the native instruction set fully. + */ + +#ifdef __BIG_ENDIAN__ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 filler0, x_reg; + } I16_reg_t; + +typedef struct { + u8 filler0, filler1, h_reg, l_reg; + } I8_reg_t; + +#else /* !__BIG_ENDIAN__ */ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 x_reg; + } I16_reg_t; + +typedef struct { + u8 l_reg, h_reg; + } I8_reg_t; + +#endif /* BIG_ENDIAN */ + +typedef union { + I32_reg_t I32_reg; + I16_reg_t I16_reg; + I8_reg_t I8_reg; + } i386_general_register; + +struct i386_general_regs { + i386_general_register A, B, C, D; + }; + +typedef struct i386_general_regs Gen_reg_t; + +struct i386_special_regs { + i386_general_register SP, BP, SI, DI, IP; + u32 FLAGS; + }; + +/* + * Segment registers here represent the 16 bit quantities + * CS, DS, ES, SS. + */ + +struct i386_segment_regs { + u16 CS, DS, SS, ES, FS, GS; + }; + +/* 8 bit registers */ +#define R_AH gen.A.I8_reg.h_reg +#define R_AL gen.A.I8_reg.l_reg +#define R_BH gen.B.I8_reg.h_reg +#define R_BL gen.B.I8_reg.l_reg +#define R_CH gen.C.I8_reg.h_reg +#define R_CL gen.C.I8_reg.l_reg +#define R_DH gen.D.I8_reg.h_reg +#define R_DL gen.D.I8_reg.l_reg + +/* 16 bit registers */ +#define R_AX gen.A.I16_reg.x_reg +#define R_BX gen.B.I16_reg.x_reg +#define R_CX gen.C.I16_reg.x_reg +#define R_DX gen.D.I16_reg.x_reg + +/* 32 bit extended registers */ +#define R_EAX gen.A.I32_reg.e_reg +#define R_EBX gen.B.I32_reg.e_reg +#define R_ECX gen.C.I32_reg.e_reg +#define R_EDX gen.D.I32_reg.e_reg + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_ESP spc.SP.I32_reg.e_reg +#define R_EBP spc.BP.I32_reg.e_reg +#define R_ESI spc.SI.I32_reg.e_reg +#define R_EDI spc.DI.I32_reg.e_reg +#define R_EIP spc.IP.I32_reg.e_reg +#define R_EFLG spc.FLAGS + +/* segment registers */ +#define R_CS seg.CS +#define R_DS seg.DS +#define R_SS seg.SS +#define R_ES seg.ES +#define R_FS seg.FS +#define R_GS seg.GS + +/* flag conditions */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ + +/* 80286 and above always have bit#1 set */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ + +/* + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) + */ +#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) + +/* following bits masked in to a 16bit quantity */ + +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ + +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) + +#define CONDITIONAL_SET_FLAG(COND,FLAG) \ + if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) + +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ + +#define F_ALL_CALC 0xff0000 /* All have been calced */ + +/* + * Emulator machine state. + * Segment usage control. + */ +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 + +typedef struct { + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; + /* + * MODE contains information on: + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits + */ + long mode; + u8 intno; + volatile int intr; /* mask of pending interrupts */ + int debug; +#ifdef DEBUG + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ +#endif + } X86EMU_regs; + +/**************************************************************************** +REMARKS: +Structure maintaining the emulator machine state. + +MEMBERS: +x86 - X86 registers +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator +****************************************************************************/ +typedef struct { + X86EMU_regs x86; + unsigned long mem_base; + unsigned long mem_size; + void* private; + } X86EMU_sysEnv; + +#pragma pack() + +/*----------------------------- Global Variables --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Global emulator machine state. + * + * We keep it global to avoid pointer dereferences in the code for speed. + */ + +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* Function to log information at runtime */ + +/*void printk(const char *fmt, ...); */ + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_REGS_H */ diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/types.h b/board/MAI/bios_emulator/scitech/include/x86emu/types.h new file mode 100644 index 0000000..0a17c54 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/x86emu/types.h @@ -0,0 +1,70 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 emulator type definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_TYPES_H +#define __X86EMU_TYPES_H + +#include + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Currently only for Linux/32bit */ +#if defined(__GNUC__) && !defined(NO_LONG_LONG) +#define __HAS_LONG_LONG__ +#endif + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +#ifdef __HAS_LONG_LONG__ +typedef unsigned long long u64; +#endif + +typedef char s8; +typedef short s16; +typedef long s32; +#ifdef __HAS_LONG_LONG__ +typedef long long s64; +#endif + +/*typedef unsigned int uint;*/ +typedef int sint; + +typedef u16 X86EMU_pioAddr; + +#endif /* __X86EMU_TYPES_H */ diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt new file mode 100644 index 0000000..0d87eff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt new file mode 100644 index 0000000..0d87eff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt new file mode 100644 index 0000000..0d87eff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt new file mode 100644 index 0000000..0d87eff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc.so/readme.txt new file mode 100644 index 0000000..0d87eff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc.so/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt new file mode 100644 index 0000000..0d87eff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc.so/readme.txt new file mode 100644 index 0000000..0d87eff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc.so/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt new file mode 100644 index 0000000..0d87eff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc16.mk b/board/MAI/bios_emulator/scitech/makedefs/bc16.mk new file mode 100644 index 0000000..aa4fe76 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/bc16.mk @@ -0,0 +1,137 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Borland C++ 4.x 16 bit version. Supports 16 bit DOS, +# DPMI16 DOS extender and 16 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_WIN16 USE_BC5 BC_LIBBASE USE_WIN95 + +# Default commands for compiling, assembling linking and archiving + CC := bcc + CFLAGS := -ml -H=bcc.sym -i60 -d -dc -4 -f287 +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /iINCLUDE /iINCLUDE /i$(SCITECH)\INCLUDE + LD := bclink tlink.exe + LDFLAGS := -c + RC := brc + RCFLAGS := +.IF $(USE_BC5) +.IF $(USE_WIN95) + WIN_VERSION := -V4.0 +.ENDIF +.ENDIF + LIBR := tlib + LIBFLAGS := /C /P32 + ILIB := implib + ILIBFLAGS := -c + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -v + LDFLAGS += -v + ASFLAGS += /zi + LIBFLAGS += /P128 +.ELSE + LDFLAGS += -x + ASFLAGS += /q +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -O2 -k- +.ELIF $(OPT_SIZE) + CFLAGS += -O1 -k- +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -DFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# Optionally compile as Win16 +.IF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += -WD -Fs- -DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -W -Fs- +.ENDIF + DEF_LIBS := import.lib mathwl.lib cwl.lib + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + DEF_LIBS := mathl.lib fp87.lib cl.lib + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +.IF $(USE_DPMI16) +PMLIB := dpmi16\pm.lib +.ELSE +PMLIB := pm.lib +.END + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := bc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc3.mk b/board/MAI/bios_emulator/scitech/makedefs/bc3.mk new file mode 100644 index 0000000..133d80e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/bc3.mk @@ -0,0 +1,102 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Borland C++ 3.1 version. Supports 16 bit DOS development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Default commands for compiling, assembling linking and archiving + CC := bcc + CFLAGS := -ml -H=bcc.sym -i60 -d +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /iINCLUDE /i$(SCITECH)\INCLUDE + LD := bclink tlink.exe + LDFLAGS := -c + LIB := tlib + LIBFLAGS := /C + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -v + LDFLAGS += -v + ASFLAGS += /zi + LIBFLAGS += /P128 +.ELSE + LDFLAGS += -x + ASFLAGS += /q +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -3 -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -3 -O1 +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -f287 -DFPU387 + ASFLAGS += -DFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + USE_REALDOS := 1 + +# Define the default libraries to link with + DEF_LIBS := mathl.lib cl.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)\dos16\bc3 + +# Define which file contains our rules + + RULES_MAK := bc3.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc32.mk b/board/MAI/bios_emulator/scitech/makedefs/bc32.mk new file mode 100644 index 0000000..246de1d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/bc32.mk @@ -0,0 +1,201 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Borland C++ 4.0 32 bit version. Supports Borland's DOS Power +# Pack DPMI32 DOS extender, Phar Lap's TNT DOS Extender and +# 32 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_SMX32 USE_TNT USE_WIN32 USE_BC5 USE_VXD BC_LIBBASE +.IMPORT .IGNORE : VTOOLSD + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := bcc32 +.IF $(USE_VXD) + CFLAGS := -4 -i60 -d -w-stu +.ELSE + CFLAGS := -4 -H=bcc32.sym -i60 -d -w-stu +.ENDIF +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -d__FLAT__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /w-res /w-mcp /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := bclink tlink32.exe + LDFLAGS := -c + RC := brc32 +.IF $(USE_BC5) + WIN_VERSION := -V4.0 + RCFLAGS := -32 +.ELSE + RCFLAGS := -w32 +.ENDIF + LIB := tlib + LIBFLAGS := /C + ILIB := implib + ILIBFLAGS := -c + INTEL_X86 := 1 + NMSYM := $(SOFTICE_PATH)\nmsym.exe + NMSYMFLAGS := /TRANSLATE:source,package,always /PROMPT /SOURCE:$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\win32 + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -v + LDFLAGS += -v + LIBFLAGS += /P256 +.IF $(USE_NASM) + ASFLAGS += -F borland -g +.ELSE + ASFLAGS += /zi +.ENDIF +.ELSE + LDFLAGS += -x + LIBFLAGS += /P128 +.IF $(USE_NASM) + ASFLAGS += -F null +.ELSE + ASFLAGS += /q +.ENDIF +.END + +# Optionally disable nagging warnings if MAX_WARN is not on +.IF $(MAX_WARN) +.ELSE + CFLAGS += -w-aus -w-par -w-hid -w-pia +.ENDIF + +# Optionally turn on optimisations (-5 -O2 breaks BC++ 4.0-4.5 sometimes) +.IF $(OPT) + CFLAGS += -5 -O2 -k- +.ELIF $(OPT_SIZE) + CFLAGS += -5 -O1 -k- +.END + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# Optionally use Phar Lap's TNT DOS Extender, otherwise use the DOS Power Pack +.IF $(USE_TNT) + CFLAGS += -D__MSDOS__ + DX_CFLAGS += -DTNT + DX_ASFLAGS += -dTNT + LIB_OS = DOS32 + DEF_LIBS := import32.lib cw32.lib dosx32.lib tntapi.lib +.ELIF $(USE_VXD) + LDFLAGS += -n -P- -x + CFLAGS += -RT- -x- -Oi -VC -I$(VTOOLSD)\INCLUDE -DIS_32 -DWANTVXDWRAPS -DVTOOLSD -DWIN40 -DWIN40_OR_LATER -DDEFSEG=1 -zC_LTEXT -zALCODE -zR_LDATA -zTLCODE + DEF_LIBS := $(VTOOLSD)\lib\cfbc440d.lib $(VTOOLSD)\lib\wr0bc440.lib $(VTOOLSD)\lib\wr1bc440.lib $(VTOOLSD)\lib\wr2bc440.lib $(VTOOLSD)\lib\wr3bc440.lib $(VTOOLSD)\lib\rtbc440d.lib + DX_ASFLAGS += -d__VXD__ -d__BORLANDC__=1 -I$(VTOOLSD)\INCLUDE -I$(VTOOLSD)\LIB\INCLUDE + LIB_OS = VXD +.ELIF $(USE_WIN32) +.IF $(WIN32_GUI) +.ELSE + CFLAGS += -D__CONSOLE__ +.ENDIF +.IF $(BUILD_DLL) + CFLAGS += -WD -DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -W -WM +.ENDIF +.IF $(USE_BC5) +.ELSE + CFLAGS += -D_WIN32 +.ENDIF + DEF_LIBS := import32.lib cw32mt.lib + DX_ASFLAGS += -d__WINDOWS32__ + LIB_OS = WIN32 +.ELIF $(USE_SMX32) + CFLAGS += -D__SMX32__ -DPME32 + DX_CFLAGS += + DX_ASFLAGS += -d__SMX32__ -dDPMI32 -dPME32 + USE_REALDOS := 1 + LIB_OS = SMX32 + DEF_LIBS := cw32mt.lib +.ELSE + USE_DPMI32 := 1 + CFLAGS += -D__MSDOS__ + DX_CFLAGS += -WX -DDPMI32 + DX_ASFLAGS += -dDPMI32 + USE_REALDOS := 1 + LIB_OS = DOS32 + DEF_LIBS := +.END + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Place to look for PMODE library files + +.IF $(USE_TNT) +PMLIB := $(LIB_BASE)\tnt\pm.lib +.ELIF $(USE_DPMI32) +PMLIB := $(LIB_BASE)\dpmi32\pm.lib +.ELSE +PMLIB := $(LIB_BASE)\pm.lib +.END + +# Define which file contains our rules + + RULES_MAK := bc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk b/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk new file mode 100644 index 0000000..23aeb7c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk @@ -0,0 +1,137 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Borland C++ 2.0 32-bit OS/2 version. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_OS2GUI BC_LIBBASE + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := bcc + CFLAGS := -w- -4 -H=bcc32.sym -i60 -d +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -d__FLAT__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE + AS := tasm + ASFLAGS := /t /mx /m /D__FLAT__ /D__OS2__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := bclink tlink.exe + LDFLAGS := -c + RC := brcc + RCFLAGS := + LIB := tlib + LIBFLAGS := /C /P32 + ILIB := implib + ILIBFLAGS := -c +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -v + LDFLAGS += -v + LIBFLAGS += /P128 +.IF $(USE_NASM) + ASFLAGS += -F borland +.ELSE + ASFLAGS += /zi +.ENDIF +.ELSE + LDFLAGS += -x +.IF $(USE_NASM) + ASFLAGS += -F null +.ELSE + ASFLAGS += /q +.ENDIF +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -5 -O2 -k- +.ELIF $(OPT_SIZE) + CFLAGS += -5 -O1 -k- +.END + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# Optionally use Phar Lap's TNT DOS Extender, otherwise use the DOS Power Pack +.IF $(BUILD_DLL) + CFLAGS += -sd -sm -DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -sm +.ENDIF + DEF_LIBS := os2.lib c2mt.lib + DX_ASFLAGS += -d__OS2__ + LIB_OS = os232 + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Place to look for PMODE library files + +.IF $(USE_OS2GUI) +DEF_LIBS += pm_pm.lib +.ELSE +DEF_LIBS += pm.lib +.ENDIF + +# Define which file contains our rules + + RULES_MAK := bcos2.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/cl16.mk b/board/MAI/bios_emulator/scitech/makedefs/cl16.mk new file mode 100644 index 0000000..0f29a15 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/cl16.mk @@ -0,0 +1,132 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Microsoft C 6.0 16 bit version. Supports 16 bit +# OS/2 development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : VC_LIBBASE +.IMPORT .IGNORE : USE_MASM + +# Default commands for compiling, assembling linking and archiving + CC := cl # C-compiler and flags + CFLAGS := /w /Gs + ASFLAGS := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELIF $(USE_MASM) + AS := masm # Assembler and flags + ASFLAGS := /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ELSE + AS := tasm # Assembler and flags +.ENDIF + LD := cl # Loader and flags + LDFLAGS = $(CFLAGS) + RC := rc # WIndows resource compiler + RCFLAGS := + LIB := lib # Librarian + LIBFLAGS := /NOI /NOE + ILIB := implib # Import librarian + ILIBFLAGS := /noignorecase + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Zi # Turn on debugging for C compiler + ASFLAGS += /zi # Turn on debugging for assembler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Ox +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += /FPi87 /DFPU387 + ASFLAGS += /DFPU387 /DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += /DBETA + ASFLAGS += /DBETA +.END + +# Use a larger stack during linking if requested ???? How the fuck do you +# specify linker options on the CL command line????? + +.IF $(STKSIZE) +.ENDIF + +# Optionally compile for 16 bit Windows +.IF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += /GD /Alfw /DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += /GA /AL +.ENDIF + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + CFLAGS += /AL + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +PMLIB := pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := cl16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/cl386.mk b/board/MAI/bios_emulator/scitech/makedefs/cl386.mk new file mode 100644 index 0000000..52157f9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/cl386.mk @@ -0,0 +1,120 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Microsoft 386 C 6.0 32 bit. Supports 32 bit +# OS/2 development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : CL_LIBBASE USE_VDD +.IMPORT .IGNORE : USE_MASM + +# Default commands for compiling, assembling linking and archiving + CC := cl386 # C-compiler and flags + # NB: The -Zf flag is ABSOLUTELY NECESSARY to compile IBM's OS/2 headers. + # It isn't documented anywhere but obviously adds support for 48-bit + # far pointers (ie. _far is valid in 32-bit code). Great. + CFLAGS := -G3s -Zf -D__386__ + ASFLAGS := /t /mx /m /oi /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELIF $(USE_MASM) + AS := masm # Assembler and flags + ASFLAGS := /t /mx /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ELSE + AS := tasm # Assembler and flags +.ENDIF + LD := link386 # Linker and flags + LDFLAGS = $(CFLAGS) + RC := rc # Windows resource compiler + RCFLAGS := + LIB := lib # Librarian + LIBFLAGS := /NOI /NOE + ILIB := implib # Import librarian + ILIBFLAGS := /noignorecase + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -Zi # Turn on debugging for C compiler + ASFLAGS += /zi # Turn on debugging for assembler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Ox +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += /FPi87 /DFPU387 + ASFLAGS += /DFPU387 /DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += /DBETA + ASFLAGS += /DBETA +.END + +# Use a larger stack during linking if requested ???? How the fuck do you +# specify linker options on the CL command line????? + +.IF $(STKSIZE) +.ENDIF + +# Place to look for PMODE library files + +PMLIB := pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_OS = os232 + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(CL_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := cl386.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/common.mk b/board/MAI/bios_emulator/scitech/makedefs/common.mk new file mode 100644 index 0000000..d337152 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/common.mk @@ -0,0 +1,180 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Common makefile targets used by all SciTech Software +# makefiles. This file includes targets for cleaning the +# current directory, and maintaining the source files with +# RCS. +# +############################################################################# + +# Override global OpenGL includes when compiling against MGL version + +.IF $(USE_MGL_OPENGL) +.IF $(UNIX_HOST) +CFLAGS += -I$(SCITECH)/include/mglgl +DEPEND_INC += $(SCITECH)/include/mglgl +.ELSE +CFLAGS += -I$(SCITECH)\include\mglgl +DEPEND_INC += $(SCITECH)\include/mglgl +.ENDIF +.ENDIF + +# Define where to install all compiled DLL files + +.IF $(UNIX_HOST) +.IF $(CHECKED) +DLL_DEST := $(SCITECH_LIB)/redist/debug +.ELSE +DLL_DEST := $(SCITECH_LIB)/redist/release +.ENDIF +.ELSE +.IF $(CHECKED) +DLL_DEST := $(SCITECH_LIB)\redist\debug +.ELSE +DLL_DEST := $(SCITECH_LIB)\redist\release +.ENDIF +.ENDIF + +# Target to build the library and DLL file if specified + +.IF $(LIBFILE) + +lib: $(LIBFILE) + +.IF $(DLLFILE) + +# Build and install a DLL file, or simply build import library and install + +.IF $(BUILD_DLL) + +$(DLLFILE): $(OBJECTS) +$(LIBFILE): $(DLLFILE) +install: $(LIBFILE) $(DLLFILE) + $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) + $(INSTALL) $(DLLFILE) $(DLL_DEST) +.IF $(USE_SOFTICE) + $(INSTALL) $(DLLFILE:s/.dll/.nms) $(DLL_DEST) +.ENDIF +.ELSE + +$(LIBFILE): $(DLL_DEST)\$(DLLFILE) +install: $(LIBFILE) + $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) + +.ENDIF +.ELSE + +.IF $(BUILD_DLL) + +# Build and install a Unix shared library + +$(LIBFILE): $(OBJECTS) +install: $(LIBFILE) + $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) + $(INSTALL) $(LIBFILE) $(DLL_DEST)/$(LIBFILE).$(VERSION) + +.ELSE + +# Build and install a normal library file + +.IF $(USE_DLL) +.ELSE +$(LIBFILE): $(OBJECTS) +install: $(LIBFILE) + $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) +.ENDIF +.ENDIF +.ENDIF +.ENDIF + +# Build and install a VxD file, including debug information + +.IF $(VXDFILE) +$(VXDFILE:s/.vxd/.dll): $(OBJECTS) +$(VXDFILE): $(VXDFILE:s/.vxd/.dll) +install: $(VXDFILE) + $(INSTALL) $(VXDFILE) $(DLL_DEST) +.IF $(DBG) + $(INSTALL) $(VXDFILE:s/.vxd/.nms) $(DLL_DEST) +.ENDIF +.ENDIF + +# Clean up directory removing all files not needed to make the library. + +__CLEAN_FILES := *.obj *.o *.sym *.bak *.tdk *.swp *.map *.err *.csm *.lib *.aps *.nms *.sys +__CLEAN_FILES += *.~* *.td *.tr *.tr? *.td? *.rws *.res *.exp *.ilk *.pdb *.pch *.a bcc32.* +__CLEAN_FILES += $(LIBCLEAN) +__CLEANEXE_FILES := $(__CLEAN_FILES) *$E *.drv *.rex *.dll *.vxd *.nms *.pel *.smf *.so.* + +.PHONY clean: + @$(RM) -f -S $(mktmp $(__CLEAN_FILES:t"\n")) + +.PHONY cleanexe: + @$(RM) -f -S $(mktmp $(__CLEANEXE_FILES:t"\n")) + +# Define the source directories to find common files + +.IF $(NO_SCITECH_COMMON) +.ELSE +.SOURCE: $(SCITECH)/src/common +.ENDIF + +# Create the include file dependencies using the MKUTIL makedep program if +# the list of dependent object files is defined + +.IF $(DEPEND_OBJ) +depend: + @$(RM) -f makefile.dep +.IF $(DEPEND_SRC) +.IF $(DEPEND_INC) + @makedep -amakefile.dep -r -s -I@$(mktmp $(DEPEND_INC:s/\/\\)) -S@$(mktmp $(DEPEND_SRC:s/\/\\);$(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) +.ELSE + @makedep -amakefile.dep -r -s -S@$(mktmp $(DEPEND_SRC:s/\/\\);$(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) +.ENDIF +.ELSE +.IF $(DEPEND_INC) + @makedep -amakefile.dep -r -s -I@$(mktmp $(DEPEND_INC:s/\/\\)) -S@$(mktmp $(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) +.ELSE + @makedep -amakefile.dep -r -s -S@$(mktmp $(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) +.ENDIF +.ENDIF + @$(ECHO) Object file dependency information generated. +.ENDIF + +# Set up for compiling Snap executeables and dynamic link libraries + +.IF $(USE_SNAP) +#CFLAGS += -I$(PRIVATE)\include\drvlib -I$(SCITECH)\include\drvlib -D__SNAP__ +CFLAGS += -D__SNAP__ +ASFLAGS += -d__SNAP__ +#EXELIBS += snap$L +.ENDIF + +# Include rule definitions for the compiler + +.INCLUDE: "$(SCITECH)/makedefs/rules/$(RULES_MAK)" + +# Include file dependencies + +.INCLUDE .IGNORE: "makefile.dep" diff --git a/board/MAI/bios_emulator/scitech/makedefs/emx.mk b/board/MAI/bios_emulator/scitech/makedefs/emx.mk new file mode 100644 index 0000000..f569790 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/emx.mk @@ -0,0 +1,194 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# OS/2 version for EMX/GNU C/C++. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE CRTDLL SHW BETA CHECKED NO_EXCEPT NO_RTTI +.IMPORT .IGNORE : FULLSCREEN SHOW_ARGS + TMPDIR := $(TEMP) + +# Standard file suffix definitions + L := .lib # Libraries + E := .exe # Executables + O := .obj # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# Import enivornment variables that we use +.IMPORT .IGNORE : EMX_LIBBASE USE_OS232 USE_OS2GUI + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes + +# Default commands for compiling, assembling linking and archiving. + CC := gcc + CFLAGS := -Zmt -Zomf -Wall -I. -I$(INCLUDE) + CXX := gcc -x c++ -fno-exceptions -fno-rtti +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -F null -d__FLAT__ -d__NOU__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE + AS := tasm # Assembler and flags + ASFLAGS := /t /mx /m /oi /D__FLAT__ /D__NOU__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := gcc + LDXX := gcc -x c++ + LDFLAGS := -L. -Zomf -Zmt + LIB := emxomfar + LIBFLAGS := -p32 rcv + + YACC := bison -y + LEX := flex + SED := sed + +# Optionally turn off exceptions and RTTI for C++ code +.IF $(NO_EXCEPT) + CXX += -fno-exceptions +.ENDIF +.IF $(NO_RTTI) + CXX += -fno-rtti +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g +.ELSE +# Without -s, emx always runs LINK386 with the /DEBUG option + CFLAGS += -s + LDFLAGS += -s +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O3 -fomit-frame-pointer +.ELIF $(OPT_SIZE) + CFLAGS += -Os +.ENDIF + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.ENDIF + +# Disable standard C runtime library +.IF $(NO_RUNTIME) +CFLAGS += -fno-builtin -nostdinc +.ENDIF + +# Link against EMX DLLs (CRTDLL=1) or link with static C runtime libraries +.IF $(CRTDLL) + LDFLAGS += -Zcrtdll +.ELSE + CFLAGS += -Zsys + LDFLAGS += -Zsys +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__OS2_32__ + CFLAGS += -D__OS2__ + ASFLAGS += -d__OS2__ + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)\OS232\$(EMX_LIBBASE) + LDFLAGS += -L$(LIB_DEST) + +# Build 32-bit OS/2 apps +.IF $(BUILD_DLL) + CFLAGS += -Zdll -DBUILD_DLL + LDFLAGS += -Zdll + ASFLAGS += -dBUILD_DLL +.ELSE +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ + LDFLAGS += -Zlinker /PMTYPE:PM +.ELSE +.IF $(FULLSCREEN) + LDFLAGS += -Zlinker /PMTYPE:NOVIO +.ELSE + LDFLAGS += -Zlinker /PMTYPE:VIO +.ENDIF +.ENDIF +.ENDIF + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := emx.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk new file mode 100644 index 0000000..0d62fdf --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk @@ -0,0 +1,161 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# BeOS version for GNU C/C++. +# +############################################################################# + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_X11 USE_LINUX +.IMPORT .IGNORE : USE_EGCS USE_PGCC STATIC_LIBS LIBC + TMPDIR := $(TEMP) + +# Standard file suffix definitions +# +# NOTE: BeOS does not require any extenion for executeable files, but you +# can use an extension if you wish. We use the .x extension for building +# executeable files so that we can use implicit rules to make the +# makefiles simpler and more portable between systems. When you install +# the files to a local bin directory, you will probably want to remove +# the .x extension. + L := .a # Libraries + E := .x # Executables + O := .o # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We use the Unix shell at all times + SHELLFLAGS := -c + +# Definition of $(MAKE) macro for recursive makes. + MAKE = $(MAKECMD) $(MFLAGS) + +# Macro to install a library file + INSTALL := cp + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes + +# Define that we are compiling for BeOS + USE_BEOS := 1 + +# Default commands for compiling, assembling linking and archiving. + CC := gcc + CFLAGS := -Wall -I. -Iinclude $(INCLUDE) + CXX := g++ + AS := nasm + ASFLAGS := -f elf -d__FLAT__ -iinclude -i$(SCITECH)/include -d__NOU__ + LD := gcc + LDFLAGS := -L. + LIB := ar + LIBFLAGS := rcs + +# Link to static libraries if requested +.IF $(STATIC_LIBS) + LDFLAGS += -static +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 +.ENDIF + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.ENDIF + +# Disable standard C runtime library + +.IF $(NO_RUNTIME) +CFLAGS += -fno-builtin -nostdinc +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__BEOS__ + ASFLAGS += -d__BEOS__ -d__UNIX__ + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files +LIB_DEST := $(LIB_BASE_DIR)/beos/gcc +LDFLAGS += -L$(LIB_DEST) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := gcc_beos.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk new file mode 100644 index 0000000..65589c8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk @@ -0,0 +1,112 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# DJGPP V2 port of GNU C/C++ to DOS with DPMI only. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Override some file suffix definitions + L := .a # Libraries + O := .o # Objects + +# Override the file prefix/suffix definitions for library naming. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# Import enivornment variables that we use +.IMPORT .IGNORE : DJ_LIBBASE + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := gcc # C-compiler and flags + CFLAGS := -Wall + AS := nasm + ASFLAGS := -t -f coff -F null -d__FLAT__ -d__GNUC__ -dSTDCALL_USCORE -iINCLUDE -i$(SCITECH)\INCLUDE + LD := dj_ld # Loader and flags + LDFLAGS := + LIB := ar # Librarian + LIBFLAGS := rs + USE_NASM := 1 + USE_GCC := 1 + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g # Turn on debugging for C compiler +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# DOS extender dependant flags + DX_CFLAGS += + DX_ASFLAGS += -dDJGPP + USE_REALDOS := 1 + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)\DOS32\$(DJ_LIBBASE) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := dj32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk new file mode 100644 index 0000000..0cb4b85 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk @@ -0,0 +1,174 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Linux version for GNU C/C++. +# +############################################################################# + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_X11 USE_FREEBSD +.IMPORT .IGNORE : USE_EGCS USE_PGCC STATIC_LIBS + TMPDIR := $(TEMP) + +# Standard file suffix definitions +# +# NOTE: Linux does not require any extenion for executeable files, but you +# can use an extension if you wish. We use the .x extension for building +# executeable files so that we can use implicit rules to make the +# makefiles simpler and more portable between systems. When you install +# the files to a local bin directory, you will probably want to remove +# the .x extension. + L := .a # Libraries + E := .x # Executables + O := .o # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We use the Unix shell at all times + SHELL := /bin/sh + SHELLFLAGS := -c + +# Definition of $(MAKE) macro for recursive makes. + MAKE = $(MAKECMD) $(MFLAGS) + +# Macro to install a library file + INSTALL := cp + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes + +# Define that we are compiling for FreeBSD + USE_LINUX := 1 + +# Default commands for compiling, assembling linking and archiving. +.IF $(USE_EGCS) + CC := egcs +.ELIF $(USE_PGCC) + CC := pgcc +.ELSE + CC := gcc +.ENDIF + CFLAGS := -Wall -I. -Iinclude $(INCLUDE) + CXX := g++ + AS := nasm +# TODO: On earlier versions of FreeBSD (<3.0) a.out is used instead of ELF + ASFLAGS := -f elf -d__FLAT__ -iinclude -i$(SCITECH)/include -d__NOU__ + LD := g++ + LDFLAGS := -L. + LIB := ar + LIBFLAGS := rcs + +# Link to static libraries if requested +.IF $(STATIC_LIBS) + LDFLAGS += -static +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 +.ENDIF + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.ENDIF + +# Disable standard C runtime library + +.IF $(NO_RUNTIME) +CFLAGS += -fno-builtin -nostdinc +.ENDIF + +# Compile flag for whether to build X11 or non-X11 lib +.IF $(USE_X11) + CFLAGS += -D__X11__ +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__FREEBSD__ + ASFLAGS += -d__FREEBSD__ -d__UNIX__ + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)/freebsd/gcc + LDFLAGS += -L$(LIB_DEST) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := gcc_freebsd.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk new file mode 100644 index 0000000..72c4ced --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk @@ -0,0 +1,180 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Linux version for GNU C/C++. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)/makedefs/startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : GCC2_LIBBASE + +# Override some file suffix definitions + L := .a # Libraries + O := .o # Objects + +# Override the file prefix/suffix definitions for library naming. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Define that we are compiling for Linux + USE_LINUX := 1 + +# Default commands for compiling, assembling linking and archiving. + CC := gcc + CFLAGS := -Wall -I. -Iinclude -I$(SCITECH:s,\,/)/include -I$(PRIVATE:s,\,/)/include + SHOW_CFLAGS := -c + CXX := g++ + AS := nasm + ASFLAGS := -t -f elf -d__FLAT__ -d__GNUC__ -iinclude -i$(SCITECH)/include -d__NOU__ + SHOW_ASFLAGS := -f elf + LD := gcc + LDXX := g++ + LDFLAGS := -L. + LIB := ar + LIBFLAGS := rcs + YACC := bison -y + LEX := flex + SED := sed + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g + SHOW_CFLAGS += -g +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 + SHOW_CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O2 + SHOW_CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 + SHOW_CFLAGS += -O1 +.ENDIF + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + SHOW_CFLAGS += -DBETA + ASFLAGS += -dBETA + SHOW_ASFLAGS += -dBETA +.ENDIF + +# Disable standard C runtime library + +.IF $(NO_RUNTIME) +CFLAGS += -fno-builtin -nostdinc +.ENDIF + +# Compile flag for whether to build X11 or non-X11 lib +.IF $(USE_X11) + CFLAGS += -D__X11__ +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__LINUX__ + ASFLAGS += -d__LINUX__ -d__UNIX__ + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug +CFLAGS += -DCHECKED=1 +SHOW_CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files +.IF $(LIBC) + LIB_DEST_SHARED := $(LIB_BASE_DIR)/linux/gcc/libc.so + LIB_DEST_STATIC := $(LIB_BASE_DIR)/linux/gcc/libc +.ELSE + LIB_DEST_SHARED := $(LIB_BASE_DIR)/linux/gcc/glibc.so + LIB_DEST_STATIC := $(LIB_BASE_DIR)/linux/gcc/glibc +.ENDIF + +# Link to static libraries if requested +.IF $(STATIC_LIBS_ALL) + LDFLAGS += -static + STATIC_LIBS := 1 +.ENDIF + +# Link to static libraries if requested +.IF $(STATIC_LIBS) + LDFLAGS += -L$(LIB_DEST_STATIC) +.ELSE + LDFLAGS += -L$(LIB_DEST_SHARED) -L$(LIB_DEST_STATIC) +.ENDIF + +# Optionally enable some dynamic libraries to be built +.IF $(BUILD_DLL) +.IF $(VERSIONMAJ) +.ELSE + VERSIONMAJ := 5 + VERSIONMIN := 0 +.ENDIF + VERSION := $(VERSIONMAJ).$(VERSIONMIN) + LIB := gcc -shared + LIBFLAGS := + L := .so + CFLAGS += -fPIC + SHOW_CFLAGS += -fPIC + ASFLAGS += -D__PIC__ + SHOW_ASFLAGS += -D__PIC__ + LIB_DEST := $(LIB_DEST_SHARED) +.ELSE + LIB_DEST := $(LIB_DEST_STATIC) +.ENDIF + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := gcc_linux.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk new file mode 100644 index 0000000..21ccf97 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk @@ -0,0 +1,135 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Cygwin port of GNU C/C++ to Win32. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : GCC2_LIBBASE + +# Override some file suffix definitions + L := .a # Libraries + O := .o # Objects + +# Override the file prefix/suffix definitions for library naming. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := gcc # C-compiler and flags + CFLAGS := -Wall -I. -Iinclude -I$(SCITECH:s,\,/)/include -I$(PRIVATE:s,\,/)/include + SHOW_CFLAGS := -c + CXX := g++ + AS := nasm + ASFLAGS := -t -f coff -F null -d__FLAT__ -d__GNUC__ -dSTDCALL_USCORE -iINCLUDE -i$(SCITECH)\INCLUDE + SHOW_ASFLAGS := -f coff + LD := gcc # Loader and flags + LDXX := g++ +.IF $(WIN32_GUI) + LDFLAGS := -L. -mwindows -e _mainCRTStartup +.ELSE + LDFLAGS := -L. +.ENDIF + RC := windres + RCFLAGS := -O coff + LIB := ar # Librarian + LIBFLAGS := rcs + YACC := bison -y + LEX := flex + SED := sed + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g + SHOW_CFLAGS += -g +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 + SHOW_CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O2 + SHOW_CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 + SHOW_CFLAGS += -O1 +.ENDIF + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + SHOW_CFLAGS += -DBETA + ASFLAGS += -dBETA + SHOW_ASFLAGS += -dBETA +.ENDIF + +# DOS extender dependant flags + DX_CFLAGS += + DX_ASFLAGS += -dGCC_WIN32 + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +SHOW_CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)\WIN32\$(GCC2_LIBBASE) + LDFLAGS += -L$(LIB_DEST) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := gcc_win32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/hc32.mk b/board/MAI/bios_emulator/scitech/makedefs/hc32.mk new file mode 100644 index 0000000..f0b065a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/hc32.mk @@ -0,0 +1,113 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Metaware High C/C++ 3.21 32 bit version. Supports Phar Lap's +# TNT DOS Extender. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := hc386 # C-compiler and flags + CFLAGS := +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + ASFLAGS := /t /mx /m /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE + LD := hc386 + LDFLAGS = $(CFLAGS) + LIB := 386lib # TNT 386|lib Librarian + LIBFLAGS := -TC + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g # Turn on debugging for C compiler + ASFLAGS += /zi # Turn on debugging for assembler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -586 -O +.ELIF $(OPT_SIZE) + CFLAGS += -586 -O1 +.ELSE + CFLAGS += -O0 +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -DFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# DOS extender dependant flags + USE_TNT := 1 + USE_REALDOS := 1 + DX_CFLAGS += -DTNT + DX_ASFLAGS += -DTNT + LDFLAGS += -LH:\TNT\LIB + +# Place to look for PMODE library files + +PMLIB := tnt\pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\DOS32\HC + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := hc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj b/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj new file mode 100644 index 0000000..edd8809 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj differ diff --git a/board/MAI/bios_emulator/scitech/makedefs/qnx4.mk b/board/MAI/bios_emulator/scitech/makedefs/qnx4.mk new file mode 100644 index 0000000..f583af3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/qnx4.mk @@ -0,0 +1,164 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# QNX version for Watcom C. +# +############################################################################# + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_QNX USE_QNX4 +.IMPORT .IGNORE : USE_PHOTON USE_X11 USE_BIOS SHOW_ARGS MAX_WARN WC_LIBBASE + TMPDIR := $(TEMP) + +# Standard file suffix definitions +# +# NOTE: Qnx does not require any extension for executeable files, but you +# can use an extension if you wish. We use the .x extension for building +# executeable files so that we can use implicit rules to make the +# makefiles simpler and more portable between systems. When you install +# the files to a local bin directory, you will probably want to remove +# the .x extension. + L := .a # Libraries + E := .exe # Executables + O := .o # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We use the Unix shell at all times + SHELL := /bin/sh + SHELLFLAGS := -c + +# Definition of $(MAKE) macro for recursive makes. + MAKE = $(MAKECMD) $(MFLAGS) + +# Macro to install a library file + INSTALL := cp + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes + +# Define that we are compiling for QNX + USE_QNX := 1 + +# Default commands for compiling, assembling linking and archiving. + CC := wcc386 + CFLAGS := -I. -Iinclude $(INCLUDE) + CXX := wpp386 + AS := nasm + ASFLAGS := -t -f obj -d__FLAT__ -dSTDCALL_MANGLE -iinclude -i$(SCITECH)/include + LD := cc + LDFLAGS := -L. + LIB := ar + LIBFLAGS := rc + +# Set the compiler warning level +.IF $(MAX_WARN) + CFLAGS += -w4 +.ELSE + CFLAGS += -w1 +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -d2 + LDFLAGS += -g2 +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -onatx-5r-fp5 +.ELIF $(OPT_SIZE) + CFLAGS += -onaslmr-5r-fp5 +.ELIF $(NOOPT) + CFLAGS += -od-5r +.END + +# Compile flag for whether to build photon or non-photon lib +.IF $(USE_PHOTON) + CFLAGS += -D__PHOTON__ +.ENDIF + +# Compile flag for whether to build X11 or non-X11 lib +.IF $(USE_X11) + CFLAGS += -D__X11__ +.ENDIF + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__QNX__ -D__UNIX__ + ASFLAGS += -d__QNX__ -d__UNIX__ + +# Define the base directory for library files + +.IF $(CHECKED) + LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug + CFLAGS += -DCHECKED=1 +.ELSE + LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)/qnx4/$(WC_LIBBASE) + LIB_DEST := $(LIB_BASE) + LDFLAGS += -L$(LIB_DEST) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := qnx4.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/qnxnto.mk b/board/MAI/bios_emulator/scitech/makedefs/qnxnto.mk new file mode 100644 index 0000000..5168ed2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/qnxnto.mk @@ -0,0 +1,157 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# QNX Neutrino version for GNU C/C++ +# +############################################################################# + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_QNX USE_QNXNTO +.IMPORT .IGNORE : USE_EGCS USE_PHOTON USE_X11 USE_BIOS + TMPDIR := $(TEMP) + +# Standard file suffix definitions +# +# NOTE: Qnx does not require any extension for executeable files, but you +# can use an extension if you wish. We use the .x extension for building +# executeable files so that we can use implicit rules to make the +# makefiles simpler and more portable between systems. When you install +# the files to a local bin directory, you will probably want to remove +# the .x extension. + L := .a # Libraries + E := .x # Executables + O := .o # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We use the Unix shell at all times + SHELL := /bin/sh + SHELLFLAGS := -c + +# Definition of $(MAKE) macro for recursive makes. + MAKE = $(MAKECMD) $(MFLAGS) + +# Macro to install a library file + INSTALL := cp + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes + +# Define that we are compiling for QNX + USE_QNX := 1 + +# Default commands for compiling, assembling linking and archiving. + CC := qcc + CFLAGS := -Vgcc_ntox86 -I. -Iinclude $(INCLUDE) + CPPFLAGS := -Vgcc_ntox86 -I. -Iinclude $(INCLUDE) + CXX := QCC + AS := nasm + ASFLAGS := -t -f elf -d__FLAT__ -d__GNUC__ -dSTDCALL_MANGLE -iinclude -i$(SCITECH)/include -d__NOU__ + LD := qcc + LDFLAGS := -Vgcc_ntox86 -L. -lm + LIB := ar + LIBFLAGS := rc + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g2 + LDFLAGS += -g2 +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -Ot +.ELIF $(OPT) + CFLAGS += -O +.ELIF $(OPT_SIZE) + CFLAGS += -Os +.ENDIF + +# Compile flag for whether to build photon or non-photon lib +.IF $(USE_PHOTON) + CFLAGS += -D__PHOTON__ +.ENDIF + +# Compile flag for whether to build X11 or non-X11 lib +.IF $(USE_X11) + CFLAGS += -D__X11__ +.ENDIF + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__QNX__ -D__UNIX__ + ASFLAGS += -d__QNX__ -d__UNIX__ + +# Define the base directory for library files + +.IF $(CHECKED) + LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug + CFLAGS += -DCHECKED=1 +.ELSE + LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)/qnxnto + LDFLAGS += -L$(LIB_DEST) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := qnxnto.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bc16.mk new file mode 100644 index 0000000..67ae910 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/bc16.mk @@ -0,0 +1,69 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $< +%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $< +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +%$D: ; $(LD) $(mktmp $(LDFLAGS) -C -Twd c0dl.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(EXELIBS)\n$*.def) + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; + @$(RM) $@ + $(LIBR) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN16) +%$E: ; $(LD) $(mktmp $(LDFLAGS) -C -Twe $(WIN_VERSION) c0wl.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(EXELIBS)\n$*.def) +.ELSE +%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tde c0l.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(PMLIB) $(DEF_LIBS) $(EXELIBS)) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bc3.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bc3.mk new file mode 100644 index 0000000..d4d071c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/bc3.mk @@ -0,0 +1,43 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) @$(mktmp $(CFLAGS)) -c $< +%$O: %$P ; $(CC) @$(mktmp $(CFLAGS)) -c $< +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) + +# Implicit rule for building a library file using response file +%$L: ; + @$(RM) $@ + $(LIBR) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n) + +# Implicit rule for building an executable file using response file +%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tde c0l.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(EXELIBS)) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bc32.mk new file mode 100644 index 0000000..e3ce25b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/bc32.mk @@ -0,0 +1,151 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +.IF $(USE_VXD) + +# Implicit rule generation to build VxD's + +%$O: %.c ; + $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) + @$(VTOOLSD)\bin\segalias.exe -p $(VTOOLSD)\include\default.seg $@ + +%$O: %$P ; + $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) + @$(VTOOLSD)\bin\segalias.exe -p $(VTOOLSD)\include\default.seg $@ + +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) + +%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n) + +%.dll: ; + @$(CP) $(mktmp EXPORTS\n_The_DDB @1) $*.def + tlink32.exe @$(mktmp $(LDFLAGS) -Tpd $(VTOOLSD:s/\/\\)\lib\icrtbc4.obj+\n$(&:s/\/\\)\n$*.dll\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS:s/\/\\)\n$*.def) + @$(RM) -S $(mktmp $*.def) + +%.vxd: %.dll ; + @$(CP) $(mktmp DYNAMIC\nATTRIB ICODE INIT\nATTRIB LCODE LOCKED\nATTRIB PCODE PAGEABLE\nATTRIB SCODE STATIC\nATTRIB DBOCODE DEBUG\nMERGE ICODE INITDAT0 INITDATA) $*.pel + @$(VTOOLSD)\bin\vxdver.exe $*.vrc $*.res + @$(VTOOLSD)\bin\pele.exe -d -s $*.smf -c $*.pel -o $@ -k 400 $*.dll + @$(VTOOLSD)\bin\sethdr.exe -n $* -x $@ -r $*.res +.IF $(DBG) + $(NMSYM) /TRANS:source,package /SOURCE:$(VXDSOURCE) $*.smf +.ENDIF + @$(RM) -S $(mktmp $*.pel) + +.ELSE + +# Implicit generation rules for making object files, libraries and exe's + +%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) +%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +.IF $(IMPORT_DLL) +.ELSE +.IF $(NO_RUNTIME) +%$D: ; $(LD) $(mktmp $(LDFLAGS) -Tpd -aa $(&:s/\/\\)\n$@\n$*.map\n$(EXELIBS)\n$*.def) +.ELSE +%$D: ; + makedef $(@:b) + $(LD) $(mktmp $(LDFLAGS) -Tpd -aa c0d32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) +.IF $(DBG) +.IF $(USE_SOFTICE) + $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ + tdstrp32 $@ +.ENDIF +.ENDIF +.ENDIF +.ENDIF + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n) +.ENDIF + +# Implicit rule for building an executable file using response file + +.IF $(USE_WIN32) +.IF $(WIN32_GUI) +%$E: ; + $(LD) $(mktmp $(LDFLAGS) -Tpe -aa $(WIN_VERSION) c0w32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) +.IF $(DBG) +.IF $(USE_SOFTICE) + $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ + tdstrp32 $@ +.ENDIF +.ENDIF +.ELSE +%$E: ; + $(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) +.IF $(USE_SOFTICE) + $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ + tdstrp32 $@ +.ENDIF +.ENDIF +.ELIF $(USE_TNT) +%$E: ; + @$(CP) $(mktmp stub 'gotnt.exe') $*.def + @$(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) +.IF $(DOSSTYLE) + @markphar $@ +.ENDIF + @$(RM) -S $(mktmp $*.def) +.ELIF $(USE_SMX32) +%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) +.ELSE +%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) +.END + +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bcos2.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bcos2.mk new file mode 100644 index 0000000..f473fec --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/bcos2.mk @@ -0,0 +1,70 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) +%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +%$D: ; + makedef $(@:b) + $(LD) $(mktmp $(LDFLAGS) -Tod -aa c02d.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(EXELIBS)\n$*.def) + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n) +.ENDIF + +# Implicit rule for building an executable file using response file + +.IF $(USE_OS2GUI) +%$E: ; $(LD) $(mktmp $(LDFLAGS) -Toe -aa c02.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(EXELIBS)\n$*.def) +.ELSE +%$E: ; $(LD) $(mktmp $(LDFLAGS) -Toe -ap c02.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(EXELIBS)\n$*.def) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/cl16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/cl16.mk new file mode 100644 index 0000000..6489a3e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/cl16.mk @@ -0,0 +1,67 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) /nologo $(CFLAGS) /c $< +%$O: %$P ; $(CC) /nologo $(CFLAGS) /c $< +%$O: %$A ; $(AS) $(ASFLAGS) $< $* NUL NUL + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +#%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS:s/\/\\) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS)) +#%$D: ; $(LD) $(LDFLAGS) /Fe$@ $& $(EXELIBS) +%$D: ; link @default.rsp + + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; $(LIB) /nologo $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+") &\n,,\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN16) +#%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) +%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) +.ELSE +%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/cl386.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/cl386.mk new file mode 100644 index 0000000..f50b274 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/cl386.mk @@ -0,0 +1,69 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) -nologo $(CFLAGS) -c $< +%$O: %$P ; $(CC) -nologo $(CFLAGS) -c $< +%$O: %$A ; $(AS) $(ASFLAGS) $< $* NUL NUL + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +#%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS:s/\/\\) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS)) +#%$D: ; $(LD) $(LDFLAGS) /Fe$@ $& $(EXELIBS) +%$D: ; link386 @default.rsp + +# Implicit rule for building a device driver using a response file +%.SYS: ; link386 @default.rsp + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; $(LIB) /nologo $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+") &\n,,\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN16) +#%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) +%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) +.ELSE +%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/dj32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/dj32.mk new file mode 100644 index 0000000..9f917bb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/dj32.mk @@ -0,0 +1,47 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\) -c) $(<:s,/,\) +%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\) -c) $(<:s,/,\) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) + +# Implicit rule for building a library file using response file +%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp $(&:s/\/\\)\n) + +# Implicit rule for building an executable file using response file +%$E: ; $(LD) $(LDFLAGS) $@ @$(mktmp $(&:s/\/\\) $(EXELIBS) $(PMLIB) -lstdcxx -lm) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/emx.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/emx.mk new file mode 100644 index 0000000..26d223a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/emx.mk @@ -0,0 +1,91 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +# OS/2 version for EMX/GNU C/C++. +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; +.IF $(SHOW_ARGS) + $(CC) -c $(CFLAGS) $(<:s,\,/) +.ELSE + @echo $(CC) -c $(<:s,\,/) + @$(CC) -c $(CFLAGS) $(<:s,\,/) +.ENDIF + +%$O: %$P ; +.IF $(SHOW_ARGS) + $(CXX) -c $(CFLAGS) $(<:s,\,/) +.ELSE + @echo $(CXX) -c $(<:s,\,/) + @$(CXX) -c $(CFLAGS) $(<:s,\,/) +.ENDIF + +%$O: %$A ; +.IF $(USE_NASM) +.IF $(SHOW_ARGS) + $(AS) -o $@ $(ASFLAGS) $(<:s,\,/) +.ELSE + @echo $(AS) $(<:s,\,/) + @$(AS) @$(mktmp -o $@ $(ASFLAGS)) $(<:s,\,/) +.ENDIF +.ELSE +.IF $(SHOW_ARGS) + + $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE + @echo $(AS) $(<:s,/,\) + $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF +.ENDIF + +# Implicit rule for building a library file using response file +%$L: ; +.IF $(SHOW_ARGS) + $(LIB) $(LIBFLAGS) $@ $(&:s,\,/) +.ELSE + @echo $(LIB) $@ + @$(LIB) $(LIBFLAGS) $@ @$(mktmp $(?:t"\n")) +.ENDIF + +# Implicit rule for building an executable file using response file +%$E: ; +.IF $(SHOW_ARGS) + $(LD) $(LDFLAGS) -o $@ $(&:s,\,/) $(EXELIBS) $(PMLIB) -lgpp -lstdcpp +.ELSE + @echo $(LD) $@ + @$(LD) $(LDFLAGS) -o $@ $(&:s,\,/) $(EXELIBS) $(PMLIB) -lgpp -lstdcpp +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_beos.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_beos.mk new file mode 100644 index 0000000..681b698 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_beos.mk @@ -0,0 +1,47 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files from source files +%$O: %.c ; $(CC) $(CFLAGS) -c $< +%$O: %$P ; $(CXX) $(CFLAGS) -c $< +%$O: %$A ; $(AS) $(ASFLAGS) $< + +# Implicit rule for building a library file +%$L: ; $(LIB) $(LIBFLAGS) $@ $& + +# Implicit rule for building an executable file +%$E: ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_freebsd.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_freebsd.mk new file mode 100644 index 0000000..9b4d236 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_freebsd.mk @@ -0,0 +1,47 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files from source files +%$O: %.c ; $(CC) $(CFLAGS) -c $< +%$O: %$P ; $(CXX) $(CFLAGS) -c $< +%$O: %$A ; $(AS) -o $@ $(ASFLAGS) $< + +# Implicit rule for building a library file +%$L: ; $(LIB) $(LIBFLAGS) $@ $& + +# Implicit rule for building an executable file +%$E: ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_linux.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_linux.mk new file mode 100644 index 0000000..5f91fe5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_linux.mk @@ -0,0 +1,93 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +.IF $(USE_CXX_LINKER) +LD := $(LDXX) +.ENDIF + +# Implicit generation rules for making object files from source files +%$O: %.c ; +.IF $(SHOW_ARGS) + $(CC) -c $(CFLAGS) $< +.ELSE + @$(ECHO) $(CC) $(SHOW_CFLAGS) $< + @$(CC) -c $(CFLAGS) $< +.ENDIF + +%$O: %$P ; +.IF $(SHOW_ARGS) + $(CXX) -c $(CFLAGS) $< +.ELSE + @$(ECHO) $(CXX) $(SHOW_CFLAGS) $< + @$(CXX) -c $(CFLAGS) $< +.ENDIF + +%$O: %$A ; +.IF $(SHOW_ARGS) + $(AS) -o $@ $(ASFLAGS) $< +.ELSE + @$(ECHO) $(AS) $(SHOW_ASFLAGS) $< + @$(AS) @$(mktmp -o $@ $(ASFLAGS)) $< +.ENDIF + +# Implicit rule for building a library file +.IF $(BUILD_DLL) +%$L: ; +.IF $(SHOW_ARGS) + $(LIB) $(LIBFLAGS) -Wl,-soname,$@.$(VERSIONMAJ) -o $@ $& $(LIBS) +.ELSE + @$(ECHO) $(LIB) $@ + @$(LIB) $(LIBFLAGS) -Wl,-soname,$@.$(VERSIONMAJ) -o $@ $& $(LIBS) +.ENDIF +.ELSE +%$L: ; +.IF $(SHOW_ARGS) + $(LIB) $(LIBFLAGS) $@ $& +.ELSE + @$(ECHO) $(LIB) $@ + @$(LIB) $(LIBFLAGS) $@ $& +.ENDIF +.ENDIF + +# Implicit rule for building an executable file +%$E: ; +.IF $(SHOW_ARGS) + $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm +.ELSE + @$(ECHO) ld $@ + @$(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_win32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_win32.mk new file mode 100644 index 0000000..485d166 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_win32.mk @@ -0,0 +1,90 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +.IF $(USE_CXX_LINKER) +LD := $(LDXX) +.ENDIF + +# Implicit generation rules for making object files from source files +%$O: %.c ; +.IF $(SHOW_ARGS) + $(CC) -c $(CFLAGS:s/\/\\) $(<:s,/,\) +.ELSE + @$(ECHO) $(CC) $(SHOW_CFLAGS:s/\/\\) $(<:s,/,\) + @$(CC) -c $(CFLAGS:s/\/\\) $(<:s,/,\) +.ENDIF + +%$O: %$P ; +.IF $(SHOW_ARGS) + $(CXX) -c $(CFLAGS:s/\/\\) $(<:s,/,\) +.ELSE + @$(ECHO) $(CXX) $(SHOW_CFLAGS:s/\/\\) $(<:s,/,\) + @$(CXX) -c $(CFLAGS:s/\/\\) $(<:s,/,\) +.ENDIF + +%$O: %$A ; +.IF $(SHOW_ARGS) + $(AS) -o $(ASFLAGS:s/\/\\) $(<:s,/,\) +.ELSE + @$(ECHO) $(AS) $(SHOW_ASFLAGS:s/\/\\) $(<:s,/,\) + @$(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $< $(RCFLAGS) -o $@ + +# Implicit rule for building a DLL +# TODO! +#%$D: ; +rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) + +# Implicit rule for building a library file +%$L: ; +.IF $(SHOW_ARGS) + $(LIB) $(LIBFLAGS) $@ $& +.ELSE + @$(ECHO) $(LIB) $@ + @$(LIB) $(LIBFLAGS) $@ @$(mktmp $(&:s/\/\\)\n) +.ENDIF + +# Implicit rule for building an executable file +%$E: ; +.IF $(SHOW_ARGS) + $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm +.ELSE + @$(ECHO) ld $@ + @$(LD) $(LDFLAGS) -o $@ @$(mktmp $(&:s/\/\\) $(EXELIBS) $(PMLIB) -lm) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/hc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/hc32.mk new file mode 100644 index 0000000..011e9ab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/hc32.mk @@ -0,0 +1,51 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) $(CFLAGS) -c $< +%$O: %$P ; $(CC) $(CFLAGS) -c $< +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building a library file using response file +%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp -R $?) + +# Implicit rule for building an executable file using response file +%$E: ; $(LD) $(LDFLAGS) -o $@ @$(mktmp $(&:s/\/\\) $(PMLIB) $(EXELIBS) -ldosx32.lib) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/qnx4.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/qnx4.mk new file mode 100644 index 0000000..55dc035 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/qnx4.mk @@ -0,0 +1,94 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Whether to link in real VBIOS library, or just the stub library + +.IF $(USE_BIOS) +VBIOSLIB := -lvbios.lib +.ELSE +VBIOSLIB := -lvbstubs.lib +.END + +# Require special privledges for Nucleus programs (requires root access) + +.IF $(USE_NUCLEUS) +LDFLAGS += -T1 +.ENDIF + +# Implicit generation rules for making object files from source files +%$O: %.c ; +.IF $(SHOW_ARGS) + $(CC) $(CFLAGS) $< +.ELSE + @echo $(CC) -c $< + +@$(CC) $(CFLAGS) $< > /dev/null +.ENDIF + +%$O: %$P ; +.IF $(SHOW_ARGS) + $(CXX) $(CFLAGS) $< +.ELSE + @echo $(CXX) -c $< + +@$(CXX) $(CFLAGS) $< > /dev/null +.ENDIF + +%$O: %$A ; +.IF $(SHOW_ARGS) + $(AS) -o $@ $(ASFLAGS) $< +.ELSE + @echo $(AS) $< + @$(AS) -o $@ $(ASFLAGS) $< +.ENDIF + +# Implicit rule for building a library file +%$L: ; +.IF $(SHOW_ARGS) + $(LIB) $(LIBFLAGS) -q $@ $& +.ELSE + @echo $(LIB) $@ + +@$(LIB) $(LIBFLAGS) -q $@ $& > /dev/null +.ENDIF + + +# Implicit rule for building an executable file +%$E: ; +.IF $(SHOW_ARGS) + $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB) +.ELSE + @echo wlink $@ + +@$(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB) > /dev/null +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/qnxnto.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/qnxnto.mk new file mode 100644 index 0000000..c43ad1f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/qnxnto.mk @@ -0,0 +1,55 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Whether to link in real VBIOS library, or just the stub library + +.IF $(USE_BIOS) +VBIOSLIB := -lvbios +.ELSE +VBIOSLIB := -lvbstubs +.END + +# Implicit generation rules for making object files from source files +%$O: %.c ; $(CC) $(CFLAGS) -c $< +%$O: %$P ; $(CXX) $(CPPFLAGS) -c $< +%$O: %$A ; $(AS) -o $@ $(ASFLAGS) $< + +# Implicit rule for building a library file +%$L: ; $(LIB) $(LIBFLAGS) $@ $& + +# Implicit rule for building an executable file +%$E: ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk new file mode 100644 index 0000000..b33bcd8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk @@ -0,0 +1,63 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) $(CFLAGS) -c $< +%$O: %$P ; $(CC) $(CFLAGS) -c $< +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +%$D: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(EXELIBS)) + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN16) +%$E: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(EXELIBS)) +.ELSE +%$E: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk new file mode 100644 index 0000000..2231906 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk @@ -0,0 +1,69 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) $(CFLAGS) -c $< +%$O: %$P ; $(CC) $(CFLAGS) -c $< +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +%$D: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(EXELIBS) kernel32.lib user32.lib gdi32.lib winmm.lib comdlg32.lib advapi32.lib) + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_TNT) +%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ELIF $(USE_WIN32) +%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(EXELIBS) kernel32.lib user32.lib gdi32.lib winmm.lib comdlg32.lib advapi32.lib) +.ELSE +%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk new file mode 100644 index 0000000..1a20319 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk @@ -0,0 +1,82 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +%$O: %$P ; $(CPP) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building help files +%.hlp: %.ipf; $(IPFC) $(IPFCFLAGS) $< + +# Implicit rule for building a DLL using a response file +.IF $(USE_OS2GUI) +%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.ELSE +%$D: ; $(LD) /nofree /nol @$(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.ENDIF + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; $(LIB) $(LIBFLAGS) @$(mktmp $@-+$(?:t"&\n-+":s/\/\\);) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_OS2GUI) +%$E: ; + rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ELSE +%$E: ; + rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n\n) +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk new file mode 100644 index 0000000..2b41801 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk @@ -0,0 +1,79 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +%$O: %$P ; $(CPP) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +.IF $(USE_OS2GUI) +%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.ELSE +%$D: ; $(LD) /nofree /nol @$(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.ENDIF + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) /out:$@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) /out:$@ $? +.ELSE +%$L: ; $(LIB) $(LIBFLAGS) /nowarn:86 /out:$@ @$(mktmp $(?:t"\n":s/\/\\)) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_OS2GUI) +%$E: ; + rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ELSE +%$E: ; + rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n\n) +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk new file mode 100644 index 0000000..6ffc270 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk @@ -0,0 +1,70 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) /nologo $(CFLAGS) /c $< +%$O: %$P ; $(CC) /nologo $(CFLAGS) /c $< +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS)) + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $@ /nologo $(LIBFLAGS) @$(mktmp +$(&:t" &\n+") &\n,\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN16) +%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) +#%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) +.ELSE +%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk new file mode 100644 index 0000000..97f1a0c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk @@ -0,0 +1,122 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Turn on pre-compiled headers as neccessary +.IF $(PRECOMP_HDR) + CFLAGS += -YX"$(PRECOMP_HDR)" +.ENDIF + +# Turn on runtime type information as necessary +.IF $(USE_RTTI) + CFLAGS += /GR +.ENDIF + +# Turn on C++ exception handling as necessary +.IF $(USE_CPPEXCEPT) + CFLAGS += /GX +.ENDIF + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) /nologo @$(mktmp $(CFLAGS:s/\/\\)) /c $(<:s,/,\) +%$O: %$P ; $(CC) /nologo @$(mktmp $(CFLAGS:s/\/\\)) /c $(<:s,/,\) +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rules for building NT device drivers + +%.sys: ; + $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.IF $(DBG) +.IF $(USE_SOFTICE) + $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ +.ENDIF +.ENDIF + +# Implicit rule for building a DLL using a response file +.IF $(IMPORT_DLL) +.ELSE +.IF $(NO_RUNTIME) +%$D: ; $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.ELSE +%$D: ; + makedef -v $* + $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.IF $(DBG) +.IF $(USE_SOFTICE) + $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ +.ENDIF +.ENDIF +.ENDIF +.ENDIF + +# Implicit rule for building a library file using response file. Note that +# we use a special .VCD file that contains the EXPORT definitions for the +# Microsoft compiler, since the LIB utility automatically adds leading +# underscores to exported functions. +.IF $(IMPORT_DLL) +%$L: ; + makedef -v $(?:b) + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) /DEF:$(?:b).def /OUT:$@ +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $(LIBFLAGS) /out:$@ @$(mktmp $(&:t"\n")\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN32) +%$E: ; + $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.IF $(DBG) +.IF $(USE_SOFTICE) + $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ +.ENDIF +.ENDIF +.ELSE +%$E: ; + @$(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.IF $(DOSSTYLE) + @markphar $@ +.ENDIF +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk new file mode 100644 index 0000000..d1ca917 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk @@ -0,0 +1,79 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) @$(mktmp $(CFLAGS)) $< +%$O: %$P ; $(CPP) @$(mktmp $(CFLAGS)) $< +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ +$? +.ELIF $(IMPORT_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ +$? +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp +$(&:t"\n+":s/\/\\)\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN16) +.IF $(BUILD_DLL) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS windows_dll\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk + @$(RM) -S $(mktmp $*.lnk) +.ELSE +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS windows\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk + @$(RM) -S $(mktmp $*.lnk) +.ENDIF +.ELSE +%$E: ; + @trimlib $(mktmp OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB) $(EXELIBS:t",")) $*.lnk + $(LD) $(LDFLAGS) @$*.lnk + @$(RM) -S $(mktmp $*.lnk) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk new file mode 100644 index 0000000..39b8819 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk @@ -0,0 +1,264 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Use a larger stack during linking if requested, or use a default stack +# of 200k. The usual default stack provided by Watcom C++ is *way* to small +# for real 32 bit code development. We also need a *huge* stack for OpenGL +# software rendering also! +.IF $(USE_QNX4) + # Not necessary for QNX code. +.ELSE +.IF $(STKSIZE) + LDFLAGS += OP STACK=$(STKSIZE) +.ELSE + LDFLAGS += OP STACK=204800 +.ENDIF +.ENDIF + +# Turn on runtime type information as necessary +.IF $(USE_RTTI) + CPFLAGS += -xr +.ENDIF + +# Optionally turn on pre-compiled headers +.IF $(PRECOMP_HDR) + CFLAGS += -fhq +.ENDIF + +.IF $(USE_QNX) +# Whether to link in real VBIOS library, or just the stub library +.IF $(USE_BIOS) +VBIOSLIB := vbios.lib, +.ELSE +VBIOSLIB := vbstubs.lib, +.END +# Require special privledges for Nucleus programs (requires root access) +.IF $(USE_NUCLEUS) +LDFLAGS += OP PRIV=1 +.ENDIF +.ENDIF + +# Implicit generation rules for making object files +.IF $(WC_LIBBASE) == WC10A +%$O: %.c ; $(CC) $(CFLAGS) $(<:s,/,\) +%$O: %$P ; $(CPP) $(CFLAGS) $(<:s,/,\) +.ELSE +%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +%$O: %$P ; $(CPP) @$(mktmp $(CPFLAGS:s/\/\\) $(CFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implit rule to compile .S assembler files. The first version +# uses GAS directly and the second uses a pre-processor to +# produce NASM code. + +.IF $(USE_GAS) +.IF $(WC_LIBBASE) == WC11 +%$O: %$S ; $(GAS) -c @$(mktmp $(GAS_FLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +# Black magic to build asm sources with Watcom 10.6 (requires sed) +%$O: %$S ; + $(GAS) -c @$(mktmp $(GAS_FLAGS:s/\/\\)) $(<:s,/,\) + wdisasm \\ -a $(*:s,/,\).o > $(*:s,/,\).lst + sed -e "s/\.text/_TEXT/; s/\.data/_DATA/; s/\.bss/_BSS/; s/\.386/\.586/; s/lar *ecx,cx/lar ecx,ecx/" $(*:s,/,\).lst > $(*:s,/,\).asm + wasm \\ $(WFLAGS) -zq -fr=nul -fp3 -fo=$@ $(*:s,/,\).asm + $(RM) -S $(mktmp $(*:s,/,\).o) + $(RM) -S $(mktmp $(*:s,/,\).lst) + $(RM) -S $(mktmp $(*:s,/,\).asm) +.ENDIF +.ELSE +%$O: %$S ; + @gcpp -DNASM_ASSEMBLER -D__WATCOMC__ -EP $(<:s,/,\) > $(*:s,/,\).asm + nasm @$(mktmp -f obj -o $@) $(*:s,/,\).asm + @$(RM) -S $(mktmp $(*:s,/,\).asm) +.ENDIF + +# Special target to build dllstart.asm using Borland TASM +dllstart.obj: dllstart.asm + $(DLL_TASM) @$(mktmp /t /mx /m /D__FLAT__ /i$(SCITECH)\INCLUDE /q) $(PRIVATE)\src\common\dllstart.asm + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +.IF $(IMPORT_DLL) +.ELSE +.IF $(USE_OS232) +%$D: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2 dll\nN $@\nF $(&:t",\n":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELIF $(USE_WIN32) +%$D: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt_dll\nN $@\nF $(&:t",\n":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELSE +%$D: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS win386\nN $*.rex\nF $(&:t",\n":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk + wbind $* -d -q -n +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ENDIF +.ENDIF + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ +$? +.ELIF $(IMPORT_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ +$? +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp +$(&:t"\n+":s/\/\\)\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_X32) +%$E: ; + @trimlib $(mktmp OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + $(LD) $(LDFLAGS) @$*.lnk + x32fix $@ +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELIF $(USE_OS232) +.IF $(USE_OS2GUI) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2_pm\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ELSE +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ENDIF +.ELIF $(USE_SNAP) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(DEFLIBS)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELIF $(USE_WIN32) +.IF $(WIN32_GUI) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS win95\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELSE +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ENDIF +.ELIF $(USE_WIN386) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS win386\nN $*.rex\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + rclink $(LD) wbind $*.rex $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELIF $(USE_TNT) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR dosx32.lib,tntapi.lib,$(PMLIB)$(EXELIBS:t",")) $*.lnk + $(LD) @$*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.IF $(DOSSTYLE) + @markphar $@ +.ENDIF +.ELIF $(USE_QNX4) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(VBIOSLIB)$(EXELIBS:t",")) $*.lnk + @+if exist $*.exe attrib -s $*.exe > NUL + $(LD) @$*.lnk + @attrib +s $*.exe +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELSE +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + $(LD) @$*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/sc16.mk b/board/MAI/bios_emulator/scitech/makedefs/sc16.mk new file mode 100644 index 0000000..099ad45 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/sc16.mk @@ -0,0 +1,128 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Symantec C++ 6.x/7.x 16 bit version. Supports 16 bit DOS +# and 16 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : SC_LIBBASE + +# Default commands for compiling, assembling linking and archiving + CC := sc # C-compiler and flags + CFLAGS := -ml -Jm +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + ASFLAGS := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE + LD := sc # Loader and flags + LDFLAGS = $(CFLAGS) + RC := rcc # WIndows resource compiler + RCFLAGS := # Mark as Win32 compatible resources + LIB := lib # Librarian + LIBFLAGS := /N /B + ILIB := implib # Import librarian + ILIBFLAGS := + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g # Turn on debugging for C compiler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -5 -o+all +.ELIF $(OPT_SIZE) + CFLAGS += -5 -o+space +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -ff -DFPU387 + ASFLAGS += -DFPU387 -DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# User a larger stack if requested + +.IF $(STKSIZE) + LDFLAGS += =$(STKSIZE) +.ENDIF + +# Optionally compile for 16 bit Windows +.IF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += -WD -DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -WA +.ENDIF + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +PMLIB := pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(SC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := sc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/sc32.mk b/board/MAI/bios_emulator/scitech/makedefs/sc32.mk new file mode 100644 index 0000000..9ca7570 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/sc32.mk @@ -0,0 +1,178 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Symantec C++ 6.x/7.x 32 bit version. Supports the DOSX +# extender, FlashTek X32 and Phar Lap's TNT DOS Extender +# and 32 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_TNT USE_X32 USE_X32VM SC_LIBBASE + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := sc # C-compiler and flags + CFLAGS := -Jm +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF +.IF $(USE_WIN32) + ASFLAGS := /t /mx /m /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ELSE + ASFLAGS := /t /mx /m /DES_NOT_DS /D__COMM__ /i$(SCITECH)\INCLUDE +.ENDIF + LD := sc # Loader and flags + LD_FLAGS = + RC := rcc # WIndows resource compiler + RCFLAGS := -32 # Mark as Win32 compatible resources + LIB := lib # Librarian + LIBFLAGS := /N /B + ILIB := implib # Import librarian + ILIBFLAGS := + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g # Turn on debugging for C compiler (FlashView) +.IF $(USE_TNT) + LDFLAGS += -fullsym # Turn on debugging for TNT 386link linker +.END +.IF $(USE_X32) or $(USE_X32VM) + LDFLAGS += -L/map # Turn on debugging for FlashView debugger +.END +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -5 -o+all +.ELIF $(OPT_SIZE) + CFLAGS += -5 -o+space +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -ff -DFPU387 + ASFLAGS += -DFPU387 -DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# User a larger stack if requested + +.IF $(STKSIZE) + LDFLAGS += =$(STKSIZE) +.ENDIF + +.IF $(USE_TNT) # Use Phar Lap's TNT DOS Extender + CFLAGS += -mp + DX_CFLAGS += -DTNT + ASFLAGS += /D__FLAT__ + DX_ASFLAGS += -DTNT + LD := 386link + LDFLAGS += @sc32.dos -exe $@ + LIB_OS = DOS32 +.ELIF $(USE_X32VM) # Use FlashTek X-32VM DOS extender + CFLAGS += -mx + DX_CFLAGS += -DX32VM + ASFLAGS += /D__X386__ + DX_ASFLAGS += -DX32VM + LD := sc + LDFLAGS += $(CFLAGS) x32v.lib + LIB_OS = DOS32 +.ELIF $(USE_X32) # Use FlashTek X-32 DOS extender + CFLAGS += -mx + DX_CFLAGS += -DX32VM + ASFLAGS += /D__X386__ + DX_ASFLAGS += -DX32VM + LD := sc + LDFLAGS += $(CFLAGS) x32.lib + LIB_OS = DOS32 +.ELIF $(USE_WIN32) # Build 32 bit Windows NT app +.IF $(BUILD_DLL) + CFLAGS += -WD -mn + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -WA -mn +.ENDIF + DX_ASFLAGS += -D__WINDOWS32__ + LIB_OS = WIN32 +.ELSE # Use default Symantec DOSX extender + USE_DOSX := 1 + USE_REALDOS := 1 + CFLAGS += -mx + DX_CFLAGS += -DDOSX + ASFLAGS += /D__X386__ + DX_ASFLAGS += -DDOSX + LD := sc + LDFLAGS += $(CFLAGS) + LIB_OS = DOS32 +.END + +# Place to look for PMODE library files + +.IF $(USE_TNT) +PMLIB := tnt\pm.lib +.ELIF $(USE_X32) +PMLIB := x32\pm.lib +.ELSE +PMLIB := dosx\pm.lib +.END + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(SC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := sc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/startup.mk b/board/MAI/bios_emulator/scitech/makedefs/startup.mk new file mode 100644 index 0000000..d8b2ba2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/startup.mk @@ -0,0 +1,161 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Common startup script that defines all variables common to +# all startup scripts. These define the DMAKE runtime +# environment and the values are dependant on the version of +# DMAKE in use. +# +############################################################################# + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL COMSPEC INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA USE_WIN32 FPU BUILD_DLL BUILD_FOR_DLL +.IMPORT .IGNORE : IMPORT_DLL USE_TASMX WIN32_GUI USE_WIN16 USE_NASM CHECKED +.IMPORT .IGNORE : OS2_SHELL SOFTICE_PATH MAX_WARN USE_SOFTICE USE_TASM32 +.IMPORT .IGNORE : DLL_START_TASM USE_SNAP USE_X11 USE_LINUX STATIC_LIBS LIBC +.IMPORT .IGNORE : SHOW_ARGS BOOT_STRAP_DMAKE + TMPDIR := $(TEMP) + +# Determine if the host machine is a Windows/DOS or Unix box +.IF $(COMSPEC) + WIN32_HOST := 1 +.ELSE + USE_NASM := 1 + UNIX_HOST := 1 +.ENDIF + +# Setup to either user NASM or TASM as the assembler +.IF $(USE_NASM) +.ELSE + USE_TASM := 1 +.ENDIF + +.IF $(UNIX_HOST) +# Standard file suffix definitions +# +# NOTE: Linux/Unix does not require any extenion for executeable files, but you +# can use an extension if you wish. We use the .exe extension for building +# executeable files so that we can use implicit rules to make the +# makefiles simpler and more portable between systems (exe also makes it +# easier for cross-compile/debugging situations). When you install +# the files to a local bin directory, you will probably want to remove +# the .exe extension. + L := .a # Libraries + E := .exe # Executables for glibc + O := .o # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We use the Unix shell at all times + SHELL := /bin/sh + SHELLFLAGS := -c + +.ELSE +# Standard file DOS/Win/OS2 suffix definitions + L := .lib # Libraries +.IF $(USE_SNAP) + E := .sxe # Snap Executables + D := .sll # Snap Dynamic Link Library file +.ELSE + E := .exe # Executables + D := .dll # Dynamic Link Library file +.ENDIF + O := .obj # Objects + A := .asm # Assembler sources + P := .cpp # C++ sources + R := .res # Compiled resource file + S := .s # Assyntax.h style assembler + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := # LP - Library file prefix (name of file on disk) + LL := # Library link prefix (name of library on link command line) + LE := .lib # Library link suffix (extension of library on link command line) + +# We use the DOS/Win/OS2 style shell at all times + SHELL := $(COMSPEC) + GROUPSHELL := $(SHELL) + SHELLFLAGS := $(SWITCHAR)c + GROUPFLAGS := $(SHELLFLAGS) + SHELLMETAS := *"?<> +.IF $(OS2_SHELL) + GROUPSUFFIX := .cmd +.ELSE + GROUPSUFFIX := .bat +.ENDIF + DIRSEPSTR := \\ + DIVFILE = $(TMPFILE:s,/,\) + +.ENDIF + +# Standard Unix style shell commands. Since these do not exist on +# regular DOS/Win/OS2 installations we use our own '' versions +# instead. To boostrtap a new OS you may wish to use the regular +# unix versions. + +.IF $(BOOT_STRAP_DMAKE) + CP := cp + MD := mkdir + RM := rm + ECHO := echo +.ELSE + CP := k_cp + MD := k_md + RM := k_rm + ECHO := k_echo +.ENDIF + +# Definition of $(MAKE) macro for recursive makes. + MAKE = $(MAKECMD) $(MFLAGS) + +# Macro to install a library file + INSTALL := $(CP) + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes diff --git a/board/MAI/bios_emulator/scitech/makedefs/va32.mk b/board/MAI/bios_emulator/scitech/makedefs/va32.mk new file mode 100644 index 0000000..fbca523 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/va32.mk @@ -0,0 +1,163 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# IBM VisualAge C++ 3.0 OS/2 32-bit version. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : VA_LIBBASE USE_OS232 USE_OS2GUI FULLSCREEN NOOPT MAX_WARN + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := icc + CPP := icc + CFLAGS := /Q /G5 /Gl+ /Fi /Si /J- /Ss+ /Sp1 /Gm+ /I. +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -F null -d__FLAT__ -dSTDCALL_MANGLE -d__NOU_VAR__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := ilink + LDFLAGS = /noi /exepack:2 /packcode /packdata /align:32 /map /noe + RC := rc + RCFLAGS := -n -x2 + LIB := ilib + LIBFLAGS := /nologo + ILIB := implib + ILIBFLAGS := /nologo + IPFC := ipfc + IPFCFLAGS := + IBMCOBJ := 1 + +# Set the compiler warning level +.IF $(MAX_WARN) + CFLAGS += /W3 +.ELSE + CFLAGS += /W1 +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Ti + LDFLAGS += /DE +.ELSE +.IF $(USE_TASM) + ASFLAGS += /q +.ENDIF +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Gfi /O /Oi +.ELIF $(OPT_SIZE) + CFLAGS += /Gfi /O /Oc +.ELIF $(NOOPT) + CFLAGS += /O- +.END + +# Optionally turn on direct i387 FPU instructions optimised for Pentium +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# Build 32-bit OS/2 apps +.IF $(BUILD_DLL) + CFLAGS += /Ge- /DBUILD_DLL + LDFLAGS += /DLL /NOE + ASFLAGS += -dBUILD_DLL +.ELSE +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ + LDFLAGS += /PMTYPE:PM +.ELSE +.IF $(FULLSCREEN) + LDFLAGS += /PMTYPE:NOVIO +.ELSE + LDFLAGS += /PMTYPE:VIO +.ENDIF +.ENDIF +.ENDIF + DX_ASFLAGS += -d__OS2__ + LIB_OS = os232 + +# Place to look for PMODE library files + +.IF $(USE_OS2GUI) +.IF $(USE_SDDPMDLL) +#Note: This is OK for now but might need to be changed if the GUI PM library +# were really different +PMLIB := sddpmlib.lib +.ELSE +PMLIB := pm_pm.lib +.ENDIF +.ELSE +.IF $(USE_SDDPMDLL) +PMLIB := sddpmlib.lib +.ELSE +PMLIB := pm.lib +.ENDIF +.ENDIF + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += /DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VA_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := va32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/va365.mk b/board/MAI/bios_emulator/scitech/makedefs/va365.mk new file mode 100644 index 0000000..3a2eccb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/va365.mk @@ -0,0 +1,151 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# IBM VisualAge C++ 3.65 OS/2 32-bit version. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : VA_LIBBASE USE_OS232 USE_OS2GUI FULLSCREEN NOOPT MAX_WARN + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := icc + CPP := icc + CFLAGS := /Q /G5l /Fi /Si /J- /Ss+ /Sp1 /Gm+ /I. +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -F null -d__FLAT__ -dSTDCALL_MANGLE -d__NOU_VAR__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := ilink + LDFLAGS = /noi /exepack /packcode /packdata /align:32 /map /noe + RC := rc + RCFLAGS := /nologo + LIB := ilib + LIBFLAGS := /nologo + ILIB := implib + ILIBFLAGS := /nologo + IBMCOBJ := 1 + +# Set the compiler warning level +.IF $(MAX_WARN) + CFLAGS += /W3 +.ELSE + CFLAGS += /W1 +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Ti + LDFLAGS += /DE +.ELSE +.IF $(USE_TASM) + ASFLAGS += /q +.ENDIF +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Gfi /O /Oi +.ELIF $(OPT_SIZE) + CFLAGS += /Gfi /O /Oc +.ELIF $(NOOPT) + CFLAGS += /O- +.END + +# Optionally turn on direct i387 FPU instructions optimised for Pentium +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# Build 32-bit OS/2 apps +.IF $(BUILD_DLL) + CFLAGS += /Gme- /DBUILD_DLL + LDFLAGS += /DLL /NOE + ASFLAGS += -dBUILD_DLL +.ELSE +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ + LDFLAGS += /PMTYPE:PM +.ELSE +.IF $(FULLSCREEN) + LDFLAGS += /PMTYPE:NOVIO +.ELSE + LDFLAGS += /PMTYPE:VIO +.ENDIF +.ENDIF +.ENDIF + DX_ASFLAGS += -d__OS2__ + LIB_OS = os232 + +# Place to look for PMODE library files + +.IF $(USE_OS2GUI) +PMLIB := pm_pm.lib +.ELSE +PMLIB := pm.lib +.ENDIF + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += /DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VA_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := va365.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/vc16.mk b/board/MAI/bios_emulator/scitech/makedefs/vc16.mk new file mode 100644 index 0000000..913bf9c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/vc16.mk @@ -0,0 +1,128 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Microsoft Visual C++ 1.x 16 bit version. Supports 16 bit +# DOS and Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : VC_LIBBASE + +# Default commands for compiling, assembling linking and archiving + CC := cl # C-compiler and flags + CFLAGS := /YX /w /G3 /Gs +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + ASFLAGS := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE + LD := cl # Loader and flags + LDFLAGS = $(CFLAGS) + RC := rc # WIndows resource compiler + RCFLAGS := + LIB := lib # Librarian + LIBFLAGS := /NOI /NOE + ILIB := implib # Import librarian + ILIBFLAGS := /noignorecase + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Yd /Zi # Turn on debugging for C compiler + ASFLAGS += /zi # Turn on debugging for assembler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Ox +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += /FPi87 /DFPU387 + ASFLAGS += /DFPU387 /DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += /DBETA + ASFLAGS += /DBETA +.END + +# Use a larger stack during linking if requested ???? How the fuck do you +# specify linker options on the CL command line????? + +.IF $(STKSIZE) +.ENDIF + +# Optionally compile for 16 bit Windows +.IF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += /GD /Alfw /DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += /GA /AL +.ENDIF + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + CFLAGS += /AL + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +PMLIB := pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := vc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/vc32.mk b/board/MAI/bios_emulator/scitech/makedefs/vc32.mk new file mode 100644 index 0000000..11c9071 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/vc32.mk @@ -0,0 +1,226 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Microsoft Visual C++ 2.x 32 bit version. Supports Phar Lap +# TNT DOS Extender and 32 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : TNT_PATH VC_LIBBASE DOSSTYLE USE_TNT USE_RTTARGET MSVCDIR +.IMPORT .IGNORE : USE_VXD USE_NTDRV USE_W2KDRV NT_DDKROOT USE_RTTI USE_CPPEXCEPT + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := cl # C-compiler and flags + CFLAGS := +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f win32 -F null -d__FLAT__ -dSTDCALL_MANGLE -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + ASFLAGS := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := cl +.IF $(USE_WIN32) + LDFLAGS = $(CFLAGS) +.IF $(USE_NTDRV) + LDENDFLAGS = -link /INCREMENTAL:NO /DRIVER /SUBSYSTEM:NATIVE,4.00 /VERSION:4.00 /MACHINE:I386 /NODEFAULTLIB /DEBUGTYPE:CV /PDB:NONE /ALIGN:0x20 /BASE:0x10000 /ENTRY:DriverEntry@8 + #/MERGE:_page=page /MERGE:_text=.text /MERGE:.rdata=.text +.ELIF $(WIN32_GUI) + LDENDFLAGS = -link /INCREMENTAL:NO /DEF:$(@:b).def /SUBSYSTEM:WINDOWS /MACHINE:I386 /DEBUGTYPE:CV /PDB:NONE +.ELSE + LDENDFLAGS = -link /INCREMENTAL:NO /SUBSYSTEM:CONSOLE /MACHINE:I386 /DEBUGTYPE:CV /PDB:NONE +.ENDIF +.ELSE + LDFLAGS = $(CFLAGS) + LDENDFLAGS := -link -stub:$(TNT_PATH:s/\/\\)\\bin\\gotnt.exe /PDB:NONE +.ENDIF + RC := rc # Watcom resource compiler + RCFLAGS := # Mark as Win32 compatible resources + LIB := lib # Librarian + LIBFLAGS := + ILIB := lib # Import librarian + ILIBFLAGS := /MACHINE:IX86 + INTEL_X86 := 1 + NMSYM := $(SOFTICE_PATH)\nmsym.exe +.IF $(USE_NTDRV) + NMSYMFLAGS := /TRANSLATE:source,package,always /PROMPT /SOURCE:$(MSVCDIR)\crt\src\intel;$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\ntdrv +.ELSE + NMSYMFLAGS := /TRANSLATE:source,package,always /PROMPT /SOURCE:$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\win32 +.ENDIF + +# Set the compiler warning level +.IF $(MAX_WARN) + CFLAGS += -W3 +.ELSE + CFLAGS += -W1 +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Yd /Zi # Turn on debugging for C compiler +.IF $(USE_TASM) + ASFLAGS += /zi # Turn on debugging for assembler +.ENDIF +.ELSE +.IF $(USE_TASM) + ASFLAGS += /q # Suppress object records not needed for linking +.ENDIF +.END + +# Optionally turn on optimisations +.IF $(VC_LIBBASE) == vc5 +.IF $(OPT) + CFLAGS += /G6 /O2 /Ox /Oi- +.ELIF $(OPT_SIZE) + CFLAGS += /G6 /O1 +.END +.ELSE +.IF $(OPT) + CFLAGS += /G5 /O2 /Ox +.ELIF $(OPT_SIZE) + CFLAGS += /G5 /O1 +.END +.ENDIF + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += /DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += /DBETA + ASFLAGS += -dBETA +.END + +# Use a larger stack during linking if requested, or use a default stack +# of 50k. The usual default stack provided by Visual C++ is *way* to small +# for real 32 bit code development. + +.IF $(USE_WIN32) + # Not necessary for Win32 code. +.ELSE +.IF $(STKSIZE) + LDENDFLAGS += /STACK:$(STKSIZE) +.ELSE + LDENDFLAGS += /STACK:51200 +.ENDIF +.ENDIF + +# DOS extender dependant flags +.IF $(USE_NTDRV) # Build 32 bit Windows NT driver + CFLAGS += /LD /Zl /Gy /Gz /GF /D__NT_DRIVER__ /D_X86_=1 /Di386=1 +.IF $(DBG) + CFLAGS += /QIf +.ENDIF + ASFLAGS += + DEF_LIBS := int64.lib ntoskrnl.lib hal.lib + DX_ASFLAGS += -d__NT_DRIVER__ +.IF $(USE_W2KDRV) # Build 32 bit Windows 2000 driver + LIB_OS = W2KDRV +.ELSE + LIB_OS = NTDRV +.ENDIF +.ELIF $(USE_WIN32) # Build 32 bit Windows NT app +.IF $(WIN32_GUI) +.ELSE + CFLAGS += -D__CONSOLE__ +.ENDIF +.IF $(BUILD_DLL) + CFLAGS += /MT /LD /DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.IF $(NO_RUNTIME) + LDENDFLAGS += /NODEFAULTLIB + CFLAGS += /Zl + DEF_LIBS := +.ELSE + DEF_LIBS := kernel32.lib user32.lib gdi32.lib advapi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib ole32.lib oleaut32.lib version.lib winspool.lib uuid.lib odbc32.lib odbccp32.lib wsock32.lib rpcrt4.lib +.ENDIF +.ELSE + CFLAGS += /MT + DEF_LIBS := kernel32.lib user32.lib gdi32.lib advapi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib ole32.lib oleaut32.lib version.lib winspool.lib uuid.lib odbc32.lib odbccp32.lib wsock32.lib rpcrt4.lib +.ENDIF + DX_ASFLAGS += -d__WINDOWS32__ + LIB_OS = WIN32 +.ELIF $(USE_RTTARGET) + CFLAGS += -D__RTTARGET__ + DX_CFLAGS += + DX_ASFLAGS += -d__RTTARGET__ + USE_REALDOS := + LIB_OS = RTT32 + DEF_LIBS := cw32mt.lib +.ELSE + USE_TNT := 1 + USE_REALDOS := 1 + CFLAGS += /MT /D__MSDOS32__ + DX_CFLAGS += -DTNT + DX_ASFLAGS += -dTNT + LIB_OS = DOS32 + DEF_LIBS := dosx32.lib tntapi.lib +.ENDIF + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += /DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Place to look for PMODE library files + +.IF $(USE_TNT) +PMLIB := $(LIB_BASE:s/\/\\)\\tnt\\pm.lib +.ELSE +PMLIB := $(LIB_BASE:s/\/\\)\\pm.lib +.ENDIF + +# Define which file contains our rules + + RULES_MAK := vc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/wc16.mk b/board/MAI/bios_emulator/scitech/makedefs/wc16.mk new file mode 100644 index 0000000..e316f4c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/wc16.mk @@ -0,0 +1,141 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Watcom C++ 10.x 16 bit version. Supports 16-bit DOS, +# 16-bit Windows development and 16-bit OS/2 development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : WC_LIBBASE USE_WIN16 USE_OS216 USE_OS2GUI + +# Default commands for compiling, assembling linking and archiving + CC := wcc # C-compiler and flags + CPP := wpp # C++-compiler and flags + CFLAGS := -ml-zq-j-w2-s-fh -fhq +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + AS := tasm # Assembler and flags + ASFLAGS := /t /mx /m /D__LARGE__ /iINCLUDE /i$(SCITECH)\INCLUDE + LD := wlink # Loader and flags + LDFLAGS = + RC := wrc # Watcom resource compiler + RCFLAGS := /bt=windows + LIB := wlib # Librarian + LIBFLAGS := -q + ILIB := wlib # Import librarian + ILIBFLAGS := -c + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -d2 # Turn on debugging for C compiler + LIBFLAGS += -p=128 # Larger page size for libraries with debug info! + ASFLAGS += /zi # Turn on debugging for assembler + LDFLAGS += D A # Turn on debugging for linker +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -onatx-5 +.ELIF $(OPT_SIZE) + CFLAGS += -onaslmr-5 +.END + +# Optionally turn on direct i387 FPU instructions optimised for Pentium + +.IF $(FPU) + CFLAGS += -fpi87-fp5-DFPU387 + ASFLAGS += -DFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# Use a larger stack during linking if requested + +.IF $(STKSIZE) + LDFLAGS += OP STACK=$(STKSIZE) +.ENDIF + +.IF $(USE_OS216) +.IF $(BUILD_DLL) + CFLAGS += -bd-bt=os2-DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -bt=os2 +.ENDIF + DX_ASFLAGS += -D__OS216__ + LIB_OS = os216 +.ELIF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += -bd-bt=windows-D_WINDOWS-DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -bt=windows-D_WINDOWS +.ENDIF + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +PMLIB := pm.lib, + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(WC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := wc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/wc32.mk b/board/MAI/bios_emulator/scitech/makedefs/wc32.mk new file mode 100644 index 0000000..e5175ca --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/wc32.mk @@ -0,0 +1,353 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Watcom C++ 10.x 32 bit version. Supports Rational's DOS4GW +# DOS Extender, PMODE/W, Causeway, FlashTek's X32-VM, +# Phar Lap's TNT DOS Extender, 32-bit Windows development and +# 32-bit OS/2 development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_TNT USE_X32 USE_X32VM USE_PMODEW STKCALL USE_CAUSEWAY +.IMPORT .IGNORE : USE_WIN386 USE_OS232 USE_OS2GUI WC_LIBBASE NOOPT DOSSTYLE +.IMPORT .IGNORE : OS2_SHELL USE_CODEVIEW USE_DOS32A USE_QNX4 LEAVE_LINKFILE + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Setup special environment for QNX 4 (Unix'ish) +.IF $(USE_QNX4) + USE_QNX := 1 + L := .a # Libraries + LP := lib # LP - Library file prefix (name of file on disk) + LL := lib # Library link prefix (name of library on link command line) + LE := .a # Library link suffix (extension of library on link command line) +.ENDIF + +# Default commands for compiling, assembling linking and archiving + CC := wcc386 + CPP := wpp386 + CFLAGS := -zq-j-s-fpi87 +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -d__FLAT__ -dSTDCALL_MANGLE -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 + DLL_TASM := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx + DLL_TASM := tasmx +.ELSE + AS := tasm + DLL_TASM := tasm +.ENDIF + ASFLAGS := /t /mx /m /w-res /w-mcp /D__FLAT__ /DSTDCALL_MANGLE /iINCLUDE /i$(SCITECH)\INCLUDE + GAS := gcc + GAS_FLAGS := -D__WATCOMC__ -D__SW_3S -D__SW_S -U__GNUC__ -UDJGPP -U__unix__ -Wall -I. -I$(SCITECH)\include -x assembler-with-cpp +.ENDIF + LD := wlink + LDFLAGS = +.IF $(USE_OS232) + RC := rc +.ELSE + RC := wrc +.ENDIF +.IF $(USE_WIN32) + RCFLAGS := -q /bt=nt +.ELIF $(USE_OS232) +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ +.ENDIF +.ELSE + RCFLAGS := -q +.ENDIF + LIB := wlib + LIBFLAGS := -q + ILIB := wlib + ILIBFLAGS := -c + INTEL_X86 := 1 + +# Set the compiler warning level +.IF $(MAX_WARN) + CFLAGS += -w4 +.ELSE + CFLAGS += -w1 +.ENDIF + +# Optionally turn on debugging information (Codeview format) +.IF $(DBG) +.IF $(USE_WIN32) +.IF $(USE_CODEVIEW) + CFLAGS += -d2 -hc + LDFLAGS += D CODEVIEW OPT CVPACK +.ELSE + CFLAGS += -d2 + LDFLAGS += D A +.ENDIF +.ELSE + CFLAGS += -d2 + LDFLAGS += D A +.ENDIF + LIBFLAGS += -p=768 +.IF $(USE_NASM) + ASFLAGS += -F borland -g +.ELSE +.IF $(USE_TASM32) + ASFLAGS += /q # TASM32 fucks up Watcom C++ debug info +.ELIF $(OS2_SHELL) + ASFLAGS += /q # TASM for OS/2 fucks up Watcom C++ debug info +.ELSE + ASFLAGS += /zi +.ENDIF +.ENDIF +.ELSE +.IF $(USE_NASM) + ASFLAGS += -F null +.ELSE + ASFLAGS += /q +.ENDIF +.END + +# Optionally turn on optimisations (with or without stack conventions) +.IF $(STKCALL) +.IF $(OPT) + CFLAGS += -onatx-5s-fp5 +.ELIF $(OPT_SIZE) + CFLAGS += -onaslmr-5s-fp5 +.ELIF $(NOOPT) + CFLAGS += -od-5s +.ELSE + CFLAGS += -3s +.END +.ELSE +.IF $(OPT) + CFLAGS += -onatx-5r-fp5 +.ELIF $(OPT_SIZE) + CFLAGS += -onaslmr-5r-fp5 +.ELIF $(NOOPT) + CFLAGS += -od-5r +.END +.END + +# Optionally turn on direct i387 FPU instructions optimised for Pentium +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +.IF $(USE_TNT) # Use Phar Lap's TNT DOS Extender + CFLAGS += -bt=nt -DTNT + ASFLAGS += -dTNT + LDFLAGS += SYS NT OP STUB=GOTNT.EXE + LIB_OS = DOS32 +.ELIF $(USE_X32VM) # Use FlashTek X-32VM DOS extender + CFLAGS += -bt=dos + LDFLAGS += SYS X32RV + DX_CFLAGS += -DX32VM + DX_ASFLAGS += -dX32VM + LIB_OS = DOS32 +.ELIF $(USE_X32) # Use FlashTek X-32 DOS extender + CFLAGS += -bt=dos + LDFLAGS += SYS X32R + DX_CFLAGS += -DX32VM + DX_ASFLAGS += -dX32VM + LIB_OS = DOS32 +.ELIF $(USE_QNX4) # Build QNX 4 app + CFLAGS += -bt=qnx386 + LDFLAGS += SYS QNX386FLAT OP CASEEXACT OP OFFSET=40k OP STACK=32k + CFLAGS += -D__QNX__ -D__UNIX__ + ASFLAGS += -d__QNX__ -d__UNIX__ + LIB_OS = QNX4 +.ELIF $(USE_OS232) +.IF $(BUILD_DLL) + CFLAGS += -bm-bd-bt=os2-sg-DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -bm-bt=os2-sg +.ENDIF + DX_ASFLAGS += -d__OS2__ + LIB_OS = os232 +.ELIF $(USE_SNAP) # Build 32 bit Snap app +.IF $(BUILD_DLL) + CFLAGS += -bm-bd-bt=nt-DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -bm-bt=nt-D_WIN32 +.ENDIF + LDFLAGS += OP nodefaultlibs +.IF $(STKCALL) + DEFLIBS := clib3s.lib,math3s.lib,noemu387.lib, +.ELSE + DEFLIBS := clib3r.lib,math3r.lib,noemu387.lib, +.ENDIF + LIB_OS = SNAP +.ELIF $(USE_WIN32) # Build 32 bit Windows NT app +.IF $(WIN32_GUI) +.ELSE + CFLAGS += -D__CONSOLE__ +.ENDIF +.IF $(BUILD_DLL) + CFLAGS += -bm-bd-bt=nt-sg-DBUILD_DLL -D_WIN32 + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -bm-bt=nt-sg-D_WIN32 +.ENDIF + DX_ASFLAGS += -d__WINDOWS32__ + LIB_OS = WIN32 + DEFLIBS := kernel32.lib,user32.lib,gdi32.lib,advapi32.lib,shell32.lib,winmm.lib,comdlg32.lib,comctl32.lib,ole32.lib,oleaut32.lib,version.lib,winspool.lib,uuid.lib,wsock32.lib,rpcrt4.lib, +.ELIF $(USE_WIN386) # Build 32 bit Win386 extended app +.IF $(BUILD_DLL) + CFLAGS += -bd-bt=windows-DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -bt=windows +.ENDIF + DX_ASFLAGS += -d__WIN386__ + LIB_OS = WIN386 +.ELIF $(USE_PMODEW) # PMODE/W + CFLAGS += -bt=dos + USE_DOS4GW := 1 + USE_REALDOS := 1 + LDFLAGS += SYS PMODEW + DX_CFLAGS += -DDOS4GW + DX_ASFLAGS += -dDOS4GW + LIB_OS = DOS32 +.ELIF $(USE_CAUSEWAY) # Causeway + CFLAGS += -bt=dos + USE_DOS4GW := 1 + USE_REALDOS := 1 + LDFLAGS += SYS CAUSEWAY + DX_CFLAGS += -DDOS4GW + DX_ASFLAGS += -dDOS4GW + LIB_OS = DOS32 +.ELIF $(USE_DOS32A) # DOS32/A + CFLAGS += -bt=dos + USE_DOS4GW := 1 + USE_REALDOS := 1 + LDFLAGS += SYS DOS32A + DX_CFLAGS += -DDOS4GW + DX_ASFLAGS += -dDOS4GW + LIB_OS = DOS32 +.ELSE # Use DOS4GW + CFLAGS += -bt=dos + USE_DOS4GW := 1 + USE_REALDOS := 1 + LDFLAGS += SYS DOS4G + DX_CFLAGS += -DDOS4GW + DX_ASFLAGS += -dDOS4GW + LIB_OS = DOS32 +.END + +# Disable linking to default C runtime library and PM library + +.IF $(NO_RUNTIME) +LDFLAGS += OP nodefaultlibs +DEFLIBS := +.ELSE + +# Place to look for PM library files + +.IF $(USE_SNAP) # Build 32 bit Snap app or dll +PMLIB := +.ELIF $(USE_WIN32) +.IF $(STKCALL) +PMLIB := spm.lib, +.ELSE +PMLIB := pm.lib, +.ENDIF +.ELIF $(USE_OS232) +.IF $(STKCALL) +.IF $(USE_OS2GUI) +PMLIB := spm_pm.lib, +.ELSE +PMLIB := spm.lib, +.ENDIF +.ELSE +.IF $(USE_OS2GUI) +PMLIB := pm_pm.lib, +.ELSE +PMLIB := pm.lib, +.ENDIF +.ENDIF +.ELIF $(USE_QNX4) +.IF $(STKCALL) +PMLIB := libspm.a, +.ELSE +PMLIB := libpm.a, +.ENDIF +.ELIF $(USE_TNT) +.IF $(STKCALL) +PMLIB := tnt\spm.lib, +.ELSE +PMLIB := tnt\pm.lib, +.ENDIF +.ELIF $(USE_X32) +.IF $(STKCALL) +PMLIB := x32\spm.lib, +.ELSE +PMLIB := x32\pm.lib, +.ENDIF +.ELSE +.IF $(STKCALL) +PMLIB := dos4gw\spm.lib, +.ELSE +PMLIB := dos4gw\pm.lib, +.ENDIF +.ENDIF +.ENDIF + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(WC_LIBBASE) + LIB_DEST := $(LIB_BASE) + + LDFLAGS += op map + +# Define which file contains our rules + + RULES_MAK := wc32.mk diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/besys.c b/board/MAI/bios_emulator/scitech/src/biosemu/besys.c new file mode 100644 index 0000000..1512ce9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/besys.c @@ -0,0 +1,408 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes BIOS emulator I/O and memory access +* functions. +* +****************************************************************************/ + +#include "biosemui.h" + +/*------------------------------- Macros ----------------------------------*/ + +/* Macros to read and write values to x86 bus memory. Replace these as + * necessary if you need to do something special to access memory over + * the bus on a particular processor family. + */ + +#define readb(base,off) *((u8*)((u32)(base) + (off))) +#define readw(base,off) *((u16*)((u32)(base) + (off))) +#define readl(base,off) *((u32*)((u32)(base) + (off))) +#define writeb(v,base,off) *((u8*)((u32)(base) + (off))) = (v) +#define writew(v,base,off) *((u16*)((u32)(base) + (off))) = (v) +#define writel(v,base,off) *((u32*)((u32)(base) + (off))) = (v) + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef DEBUG +# define DEBUG_MEM() (M.x86.debug & DEBUG_MEM_TRACE_F) +#else +# define DEBUG_MEM() +#endif + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +u8 X86API BE_rdb( + u32 addr) +{ + u8 val = 0; + + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { + val = *(u8*)(_BE_env.biosmem_base + addr - 0xC0000); + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { + val = readb(_BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size - 1) { +DB( printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { + val = *(u8*)(M.mem_base + addr); + } +DB( if (DEBUG_MEM()) + printk("%#08x 1 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +u16 X86API BE_rdw( + u32 addr) +{ + u16 val = 0; + + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xC0000; + val = ( *(u8*)(_BE_env.biosmem_base + addr) | + (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8)); + } + else +#endif + val = *(u16*)(_BE_env.biosmem_base + addr - 0xC0000); + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xA0000; + val = ( readb(_BE_env.busmem_base, addr) | + (readb(_BE_env.busmem_base, addr + 1) << 8)); + } + else +#endif + val = readw(_BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size - 2) { +DB( printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + val = ( *(u8*)(M.mem_base + addr) | + (*(u8*)(M.mem_base + addr + 1) << 8)); + } + else +#endif + val = *(u16*)(M.mem_base + addr); + } +DB( if (DEBUG_MEM()) + printk("%#08x 2 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. + +REMARKS: +Reads a long value from the emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +u32 X86API BE_rdl( + u32 addr) +{ + u32 val = 0; + + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + addr -= 0xC0000; + val = ( *(u8*)(_BE_env.biosmem_base + addr + 0) | + (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8) | + (*(u8*)(_BE_env.biosmem_base + addr + 2) << 16) | + (*(u8*)(_BE_env.biosmem_base + addr + 3) << 24)); + } + else +#endif + val = *(u32*)(_BE_env.biosmem_base + addr - 0xC0000); + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + addr -= 0xA0000; + val = ( readb(_BE_env.busmem_base, addr) | + (readb(_BE_env.busmem_base, addr + 1) << 8) | + (readb(_BE_env.busmem_base, addr + 2) << 16) | + (readb(_BE_env.busmem_base, addr + 3) << 24)); + } + else +#endif + val = readl(_BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size - 4) { +DB( printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + val = ( *(u8*)(M.mem_base + addr + 0) | + (*(u8*)(M.mem_base + addr + 1) << 8) | + (*(u8*)(M.mem_base + addr + 2) << 16) | + (*(u8*)(M.mem_base + addr + 3) << 24)); + } + else +#endif + val = *(u32*)(M.mem_base + addr); + } +DB( if (DEBUG_MEM()) + printk("%#08x 4 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +void X86API BE_wrb( + u32 addr, + u8 val) +{ +DB( if (DEBUG_MEM()) + printk("%#08x 1 <- %#x\n", addr, val);) + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { + *(u8*)(_BE_env.biosmem_base + addr - 0xC0000) = val; + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { + writeb(val, _BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size-1) { +DB( printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { + *(u8*)(M.mem_base + addr) = val; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +void X86API BE_wrw( + u32 addr, + u16 val) +{ +DB( if (DEBUG_MEM()) + printk("%#08x 2 <- %#x\n", addr, val);) + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xC0000; + *(u8*)(_BE_env.biosmem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(_BE_env.biosmem_base + addr + 1) = (val >> 8) & 0xff; + } + else +#endif + *(u16*)(_BE_env.biosmem_base + addr - 0xC0000) = val; + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xA0000; + writeb(val >> 0, _BE_env.busmem_base, addr); + writeb(val >> 8, _BE_env.busmem_base, addr + 1); + } + else +#endif + writew(val, _BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size-2) { +DB( printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + } + else +#endif + *(u16*)(M.mem_base + addr) = val; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a long value to emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +void X86API BE_wrl( + u32 addr, + u32 val) +{ +DB( if (DEBUG_MEM()) + printk("%#08x 4 <- %#x\n", addr, val);) + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xC0000; + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else +#endif + *(u32*)(M.mem_base + addr - 0xC0000) = val; + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + addr -= 0xA0000; + writeb(val >> 0, _BE_env.busmem_base, addr); + writeb(val >> 8, _BE_env.busmem_base, addr + 1); + writeb(val >> 16, _BE_env.busmem_base, addr + 1); + writeb(val >> 24, _BE_env.busmem_base, addr + 1); + } + else +#endif + writel(val, _BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size-4) { +DB( printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else +#endif + *(u32*)(M.mem_base + addr) = val; + } +} + +/* Debug functions to do ISA/PCI bus port I/O */ + +#ifdef DEBUG +#define DEBUG_IO() (M.x86.debug & DEBUG_IO_TRACE_F) + +u8 X86API BE_inb(int port) +{ + u8 val = PM_inpb(port); + if (DEBUG_IO()) + printk("%04X:%04X: inb.%04X -> %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + return val; +} + +u16 X86API BE_inw(int port) +{ + u16 val = PM_inpw(port); + if (DEBUG_IO()) + printk("%04X:%04X: inw.%04X -> %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + return val; +} + +u32 X86API BE_inl(int port) +{ + u32 val = PM_inpd(port); + if (DEBUG_IO()) + printk("%04X:%04X: inl.%04X -> %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + return val; +} + +void X86API BE_outb(int port, u8 val) +{ + if (DEBUG_IO()) + printk("%04X:%04X: outb.%04X <- %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + PM_outpb(port,val); +} + +void X86API BE_outw(int port, u16 val) +{ + if (DEBUG_IO()) + printk("%04X:%04X: outw.%04X <- %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + PM_outpw(port,val); +} + +void X86API BE_outl(int port, u32 val) +{ + if (DEBUG_IO()) + printk("%04X:%04X: outl.%04X <- %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + PM_outpd(port,val); +} +#endif diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/bios.c b/board/MAI/bios_emulator/scitech/src/biosemu/bios.c new file mode 100644 index 0000000..c0f4a4b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/bios.c @@ -0,0 +1,250 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Module implementing the BIOS specific functions. +* +****************************************************************************/ + +#include "biosemui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +Handler for undefined interrupts. +****************************************************************************/ +static void X86API undefined_intr( + int intno) +{ + if (BE_rdw(intno * 4 + 2) == BIOS_SEG) + printk("biosEmu: undefined interrupt %xh called!\n",intno); + else + X86EMU_prepareForInt(intno); +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +This function handles the default system BIOS Int 10h (the default is stored +in the Int 42h vector by the system BIOS at bootup). We only need to handle +a small number of special functions used by the BIOS during POST time. +****************************************************************************/ +static void X86API int42( + int intno) +{ + if (M.x86.R_AH == 0x12 && M.x86.R_BL == 0x32) { + if (M.x86.R_AL == 0) { + /* Enable CPU accesses to video memory */ + PM_outpb(0x3c2, PM_inpb(0x3cc) | (u8)0x02); + return; + } + else if (M.x86.R_AL == 1) { + /* Disable CPU accesses to video memory */ + PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8)~0x02); + return; + } +#ifdef DEBUG + else { + printk("biosEmu/bios.int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",M.x86.R_AL); + } +#endif + } +#ifdef DEBUG + else { + printk("biosEmu/bios.int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",M.x86.R_AH, M.x86.R_AL, M.x86.R_BL); + } +#endif +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +This function handles the default system BIOS Int 10h. If the POST code +has not yet re-vectored the Int 10h BIOS interrupt vector, we handle this +by simply calling the int42 interrupt handler above. Very early in the +BIOS POST process, the vector gets replaced and we simply let the real +mode interrupt handler process the interrupt. +****************************************************************************/ +static void X86API int10( + int intno) +{ + if (BE_rdw(intno * 4 + 2) == BIOS_SEG) + int42(intno); + else + X86EMU_prepareForInt(intno); +} + +/* Result codes returned by the PCI BIOS */ + +#define SUCCESSFUL 0x00 +#define FUNC_NOT_SUPPORT 0x81 +#define BAD_VENDOR_ID 0x83 +#define DEVICE_NOT_FOUND 0x86 +#define BAD_REGISTER_NUMBER 0x87 +#define SET_FAILED 0x88 +#define BUFFER_TOO_SMALL 0x89 + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +This function handles the default Int 1Ah interrupt handler for the real +mode code, which provides support for the PCI BIOS functions. Since we only +want to allow the real mode BIOS code *only* see the PCI config space for +its own device, we only return information for the specific PCI config +space that we have passed in to the init function. This solves problems +when using the BIOS to warm boot a secondary adapter when there is an +identical adapter before it on the bus (some BIOS'es get confused in this +case). +****************************************************************************/ +static void X86API int1A( + unused) +{ + u16 pciSlot; + + /* Fail if no PCI device information has been registered */ + if (!_BE_env.vgaInfo.pciInfo) + return; + pciSlot = (u16)(_BE_env.vgaInfo.pciInfo->slot.i >> 8); + switch (M.x86.R_AX) { + case 0xB101: /* PCI bios present? */ + M.x86.R_AL = 0x00; /* no config space/special cycle generation support */ + M.x86.R_EDX = 0x20494350; /* " ICP" */ + M.x86.R_BX = 0x0210; /* Version 2.10 */ + M.x86.R_CL = 0; /* Max bus number in system */ + CLEAR_FLAG(F_CF); + break; + case 0xB102: /* Find PCI device */ + M.x86.R_AH = DEVICE_NOT_FOUND; + if (M.x86.R_DX == _BE_env.vgaInfo.pciInfo->VendorID && + M.x86.R_CX == _BE_env.vgaInfo.pciInfo->DeviceID && + M.x86.R_SI == 0) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_BX = pciSlot; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB103: /* Find PCI class code */ + M.x86.R_AH = DEVICE_NOT_FOUND; + if (M.x86.R_CL == _BE_env.vgaInfo.pciInfo->Interface && + M.x86.R_CH == _BE_env.vgaInfo.pciInfo->SubClass && + (u8)(M.x86.R_ECX >> 16) == _BE_env.vgaInfo.pciInfo->BaseClass) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_BX = pciSlot; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB108: /* Read configuration byte */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_CL = (u8)PCI_accessReg(M.x86.R_DI,0,PCI_READ_BYTE,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB109: /* Read configuration word */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_CX = (u16)PCI_accessReg(M.x86.R_DI,0,PCI_READ_WORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10A: /* Read configuration dword */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_ECX = (u32)PCI_accessReg(M.x86.R_DI,0,PCI_READ_DWORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10B: /* Write configuration byte */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + PCI_accessReg(M.x86.R_DI,M.x86.R_CL,PCI_WRITE_BYTE,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10C: /* Write configuration word */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + PCI_accessReg(M.x86.R_DI,M.x86.R_CX,PCI_WRITE_WORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10D: /* Write configuration dword */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + PCI_accessReg(M.x86.R_DI,M.x86.R_ECX,PCI_WRITE_DWORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + default: + printk("biosEmu/bios.int1a: unknown function AX=%#04x\n", M.x86.R_AX); + } +} + +/**************************************************************************** +REMARKS: +This function initialises the BIOS emulation functions for the specific +PCI display device. We insulate the real mode BIOS from any other devices +on the bus, so that it will work correctly thinking that it is the only +device present on the bus (ie: avoiding any adapters present in from of +the device we are trying to control). +****************************************************************************/ +void _BE_bios_init( + u32 *intrTab) +{ + int i; + X86EMU_intrFuncs bios_intr_tab[256]; + + for (i = 0; i < 256; ++i) { + intrTab[i] = BIOS_SEG << 16; + bios_intr_tab[i] = undefined_intr; + } + bios_intr_tab[0x10] = int10; + bios_intr_tab[0x1A] = int1A; + bios_intr_tab[0x42] = int42; + X86EMU_setupIntrFuncs(bios_intr_tab); +} diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c b/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c new file mode 100644 index 0000000..0052709 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c @@ -0,0 +1,445 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Module implementing the system specific functions. This +* module is always compiled and linked in the OS depedent +* libraries, and never in a binary portable driver. +* +****************************************************************************/ + +#include "biosemui.h" +#include +#include + +/*------------------------- Global Variables ------------------------------*/ + +BE_sysEnv _BE_env; +#ifdef __DRIVER__ +PM_imports _VARAPI _PM_imports; +#endif +static X86EMU_memFuncs _BE_mem = { + BE_rdb, + BE_rdw, + BE_rdl, + BE_wrb, + BE_wrw, + BE_wrl, + }; +#ifdef DEBUG +static X86EMU_pioFuncs _BE_pio = { + BE_inb, + BE_inw, + BE_inl, + BE_outb, + BE_outw, + BE_outl, + }; +#else +static X86EMU_pioFuncs _BE_pio = { + (void*)PM_inpb, + (void*)PM_inpw, + (void*)PM_inpd, + (void*)PM_outpb, + (void*)PM_outpw, + (void*)PM_outpd, + }; +#endif + +/*-------------------------- Implementation -------------------------------*/ + +#define OFF(addr) (u16)(((addr) >> 0) & 0xffff) +#define SEG(addr) (u16)(((addr) >> 4) & 0xf000) + +/**************************************************************************** +PARAMETERS: +debugFlags - Flags to enable debugging options (debug builds only) +memSize - Amount of memory to allocate for real mode machine +info - Pointer to default VGA device information + +REMARKS: +This functions initialises the BElib, and uses the passed in +BIOS image as the BIOS that is used and emulated at 0xC0000. +****************************************************************************/ +ibool PMAPI BE_init( + u32 debugFlags, + int memSize, + BE_VGAInfo *info) +{ +#ifndef __DRIVER__ + PM_init(); +#endif + memset(&M,0,sizeof(M)); + if (memSize < 20480) + PM_fatalError("Emulator requires at least 20Kb of memory!\n"); + if ((M.mem_base = (unsigned long)malloc(memSize)) == NULL) + PM_fatalError("Out of memory!"); + M.mem_size = memSize; + _BE_env.busmem_base = (ulong)PM_mapPhysicalAddr(0xA0000,0x5FFFF,true); + M.x86.debug = debugFlags; + _BE_bios_init((u32*)info->LowMem); + X86EMU_setupMemFuncs(&_BE_mem); + X86EMU_setupPioFuncs(&_BE_pio); + BE_setVGA(info); + return true; +} + +/**************************************************************************** +PARAMETERS: +debugFlags - Flags to enable debugging options (debug builds only) + +REMARKS: +This function allows the application to enable logging and debug flags +on a function call basis, so we can specifically enable logging only +for specific functions that are causing problems in debug mode. +****************************************************************************/ +void PMAPI BE_setDebugFlags( + u32 debugFlags) +{ + M.x86.debug = debugFlags; +} + +/**************************************************************************** +PARAMETERS: +info - Pointer to VGA device information to make current + +REMARKS: +This function sets the VGA BIOS functions in the emulator to point to the +specific VGA BIOS in use. This includes swapping the BIOS interrupt +vectors, BIOS image and BIOS data area to the new BIOS. This allows the +real mode BIOS to be swapped without resetting the entire emulator. +****************************************************************************/ +void PMAPI BE_setVGA( + BE_VGAInfo *info) +{ + _BE_env.vgaInfo.pciInfo = info->pciInfo; + _BE_env.vgaInfo.BIOSImage = info->BIOSImage; + if (info->BIOSImage) { + _BE_env.biosmem_base = (ulong)info->BIOSImage; + _BE_env.biosmem_limit = 0xC0000 + info->BIOSImageLen-1; + } + else { + _BE_env.biosmem_base = _BE_env.busmem_base + 0x20000; + _BE_env.biosmem_limit = 0xC7FFF; + } + if (*((u32*)info->LowMem) == 0) + _BE_bios_init((u32*)info->LowMem); + memcpy((u8*)M.mem_base,info->LowMem,sizeof(info->LowMem)); +} + +/**************************************************************************** +PARAMETERS: +info - Pointer to VGA device information to retrieve current + +REMARKS: +This function returns the VGA BIOS functions currently active in the +emulator, so they can be restored at a later date. +****************************************************************************/ +void PMAPI BE_getVGA( + BE_VGAInfo *info) +{ + info->pciInfo = _BE_env.vgaInfo.pciInfo; + info->BIOSImage = _BE_env.vgaInfo.BIOSImage; + memcpy(info->LowMem,(u8*)M.mem_base,sizeof(info->LowMem)); +} + +/**************************************************************************** +PARAMETERS: +r_seg - Segment for pointer to convert +r_off - Offset for pointer to convert + +REMARKS: +This function maps a real mode pointer in the emulator memory to a protected +mode pointer that can be used to directly access the memory. + +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. +****************************************************************************/ +void * PMAPI BE_mapRealPointer( + uint r_seg, + uint r_off) +{ + u32 addr = ((u32)r_seg << 4) + r_off; + + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { + return (void*)(_BE_env.biosmem_base + addr - 0xC0000); + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { + return (void*)(_BE_env.busmem_base + addr - 0xA0000); + } + return (void*)(M.mem_base + addr); +} + +/**************************************************************************** +PARAMETERS: +len - Return the length of the VESA buffer +rseg - Place to store VESA buffer segment +roff - Place to store VESA buffer offset + +REMARKS: +This function returns the address of the VESA transfer buffer in real +mode emulator memory. The VESA transfer buffer is always 1024 bytes long, +and located at 15Kb into the start of the real mode memory (16Kb is where +we put the real mode code we execute for issuing interrupts). + +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. +****************************************************************************/ +void * PMAPI BE_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + *len = 1024; + *rseg = SEG(0x03C00); + *roff = OFF(0x03C00); + return (void*)(M.mem_base + ((u32)*rseg << 4) + *roff); +} + +/**************************************************************************** +REMARKS: +Cleans up and exits the emulator. +****************************************************************************/ +void PMAPI BE_exit(void) +{ + free((void*)M.mem_base); + PM_freePhysicalAddr((void*)_BE_env.busmem_base,0x5FFFF); +} + +/**************************************************************************** +PARAMETERS: +seg - Segment of code to call +off - Offset of code to call +regs - Real mode registers to load +sregs - Real mode segment registers to load + +REMARKS: +This functions calls a real mode far function at the specified address, +and loads all the x86 registers from the passed in registers structure. +On exit the registers returned from the call are returned in the same +structures. +****************************************************************************/ +void PMAPI BE_callRealMode( + uint seg, + uint off, + RMREGS *regs, + RMSREGS *sregs) +{ + M.x86.R_EAX = regs->e.eax; + M.x86.R_EBX = regs->e.ebx; + M.x86.R_ECX = regs->e.ecx; + M.x86.R_EDX = regs->e.edx; + M.x86.R_ESI = regs->e.esi; + M.x86.R_EDI = regs->e.edi; + M.x86.R_DS = sregs->ds; + M.x86.R_ES = sregs->es; + M.x86.R_FS = sregs->fs; + M.x86.R_GS = sregs->gs; + M.x86.R_CS = (u16)seg; + M.x86.R_IP = (u16)off; + M.x86.R_SS = SEG(M.mem_size - 1); + M.x86.R_SP = OFF(M.mem_size - 1); + X86EMU_exec(); + regs->e.cflag = M.x86.R_EFLG & F_CF; + regs->e.eax = M.x86.R_EAX; + regs->e.ebx = M.x86.R_EBX; + regs->e.ecx = M.x86.R_ECX; + regs->e.edx = M.x86.R_EDX; + regs->e.esi = M.x86.R_ESI; + regs->e.edi = M.x86.R_EDI; + sregs->ds = M.x86.R_DS; + sregs->es = M.x86.R_ES; + sregs->fs = M.x86.R_FS; + sregs->gs = M.x86.R_GS; +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers + +REMARKS: +This functions calls a real mode interrupt function at the specified address, +and loads all the x86 registers from the passed in registers structure. +On exit the registers returned from the call are returned in out stucture. +****************************************************************************/ +int PMAPI BE_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + M.x86.R_EAX = in->e.eax; + M.x86.R_EBX = in->e.ebx; + M.x86.R_ECX = in->e.ecx; + M.x86.R_EDX = in->e.edx; + M.x86.R_ESI = in->e.esi; + M.x86.R_EDI = in->e.edi; + ((u8*)M.mem_base)[0x4000] = 0xCD; + ((u8*)M.mem_base)[0x4001] = (u8)intno; + ((u8*)M.mem_base)[0x4002] = 0xC3; + M.x86.R_CS = SEG(0x04000); + M.x86.R_IP = OFF(0x04000); + M.x86.R_SS = SEG(M.mem_size - 1); + M.x86.R_SP = OFF(M.mem_size - 1); + X86EMU_exec(); + out->e.cflag = M.x86.R_EFLG & F_CF; + out->e.eax = M.x86.R_EAX; + out->e.ebx = M.x86.R_EBX; + out->e.ecx = M.x86.R_ECX; + out->e.edx = M.x86.R_EDX; + out->e.esi = M.x86.R_ESI; + out->e.edi = M.x86.R_EDI; + return out->x.ax; +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers +sregs - Real mode segment registers to load + +REMARKS: +This functions calls a real mode interrupt function at the specified address, +and loads all the x86 registers from the passed in registers structure. +On exit the registers returned from the call are returned in out stucture. +****************************************************************************/ +int PMAPI BE_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + M.x86.R_EAX = in->e.eax; + M.x86.R_EBX = in->e.ebx; + M.x86.R_ECX = in->e.ecx; + M.x86.R_EDX = in->e.edx; + M.x86.R_ESI = in->e.esi; + M.x86.R_EDI = in->e.edi; + M.x86.R_DS = sregs->ds; + M.x86.R_ES = sregs->es; + M.x86.R_FS = sregs->fs; + M.x86.R_GS = sregs->gs; + ((u8*)M.mem_base)[0x4000] = 0xCD; + ((u8*)M.mem_base)[0x4001] = (u8)intno; + ((u8*)M.mem_base)[0x4002] = 0xC3; + M.x86.R_CS = SEG(0x04000); + M.x86.R_IP = OFF(0x04000); + M.x86.R_SS = SEG(M.mem_size - 1); + M.x86.R_SP = OFF(M.mem_size - 1); + X86EMU_exec(); + out->e.cflag = M.x86.R_EFLG & F_CF; + out->e.eax = M.x86.R_EAX; + out->e.ebx = M.x86.R_EBX; + out->e.ecx = M.x86.R_ECX; + out->e.edx = M.x86.R_EDX; + out->e.esi = M.x86.R_ESI; + out->e.edi = M.x86.R_EDI; + sregs->ds = M.x86.R_DS; + sregs->es = M.x86.R_ES; + sregs->fs = M.x86.R_FS; + sregs->gs = M.x86.R_GS; + return out->x.ax; +} + +#ifdef __DRIVER__ + +/**************************************************************************** +REMARKS: +Empty log function for binary portable DLL. The BPD is compiled without +debug information, so very little is logged anyway so it is simpler this +way. +****************************************************************************/ +void printk(const char *msg, ...) +{ +} + +/**************************************************************************** +REMARKS: +Fatal error handler called when a non-imported function is called by the +driver. We leave this to a runtime error so that older applications and +shell drivers will work with newer bpd drivers provided no newer functions +are required by the driver itself. If they are, the application or shell +driver needs to be recompiled. +****************************************************************************/ +static void _PM_fatalErrorHandler(void) +{ + PM_fatalError("Unsupported PM_imports import function called! Please re-compile!\n"); +} + +/**************************************************************************** +PARAMETERS: +beImp - BE library imports +beImp - Generic emulator imports + +RETURNS: +Pointer to exported function list + +REMARKS: +This function initialises the BIOS emulator library and returns the list of +loader library exported functions. +{secret} +****************************************************************************/ +BE_exports * _CEXPORT BE_initLibrary( + PM_imports *pmImp) +{ + static BE_exports _BE_exports = { + sizeof(BE_exports), + BE_init, + BE_setVGA, + BE_getVGA, + BE_mapRealPointer, + BE_getVESABuf, + BE_callRealMode, + BE_int86, + BE_int86x, + NULL, + BE_exit, + }; + int i,max; + ulong *p; + + /* Initialize all default imports to point to fatal error handler */ + /* for upwards compatibility. */ + max = sizeof(_PM_imports)/sizeof(BE_initLibrary_t); + for (i = 0,p = (ulong*)&_PM_imports; i < max; i++) + *p++ = (ulong)_PM_fatalErrorHandler; + + /* Now copy all our imported functions */ + memcpy(&_PM_imports,pmImp,MIN(sizeof(_PM_imports),pmImp->dwSize)); + return &_BE_exports; +} + +#endif /* __DRIVER__ */ diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h b/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h new file mode 100644 index 0000000..23edebc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h @@ -0,0 +1,79 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Internal header file for the BIOS emulator library. +* +****************************************************************************/ + +#ifndef __BIOSEMUI_H +#define __BIOSEMUI_H + +#include + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#define BIOS_SEG 0xfff0 + +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* bios.c */ + +void _BE_bios_init(u32 *intrTab); +void _BE_setup_funcs(void); + +/* besys.c */ + +u8 X86API BE_rdb(u32 addr); +u16 X86API BE_rdw(u32 addr); +u32 X86API BE_rdl(u32 addr); +void X86API BE_wrb(u32 addr,u8 val); +void X86API BE_wrw(u32 addr,u16 val); +void X86API BE_wrl(u32 addr,u32 val); +#ifdef DEBUG +u8 X86API BE_inb(int port); +u16 X86API BE_inw(int port); +u32 X86API BE_inl(int port); +void X86API BE_outb(int port, u8 val); +void X86API BE_outw(int port, u16 val); +void X86API BE_outl(int port, u32 val); +#endif + +#endif /* __BIOSEMUI_H */ diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/makefile b/board/MAI/bios_emulator/scitech/src/biosemu/makefile new file mode 100644 index 0000000..80730b2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/makefile @@ -0,0 +1,99 @@ +############################################################################# +# +# BIOS emulator and interface +# to Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Generic makefile for the x86emu library. Requires +# the SciTech Software makefile definitions package to be +# installed, which uses the DMAKE make program. +# +############################################################################# + +.IMPORT .IGNORE: DEBUG + +#---------------------------------------------------------------------------- +# Define the lists of object files +#---------------------------------------------------------------------------- + +DLL_OBJS = dllstart$O _pm_imp$O +BIOS_OBJS = biosemu$O bios$O besys$O +X86_OBJS = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O +CFLAGS += -DSCITECH -I$(SCITECH)\src\x86emu + +.IF $(BUILD_DLL) + +CFLAGS += -I$(PRIVATE)\include\drvlib -I$(SCITECH)\include\drvlib -D__DRIVER__ +ASFLAGS += -d__DRIVER__ +EXELIBS = drvlib$L + +.ELSE + +.IF $(DEBUG) +CFLAGS += -DDEBUG +.ENDIF +OBJECTS = $(BIOS_OBJS) $(X86_OBJS) +LIBCLEAN = *.dll *.lib *.a +LIBFILE = $(LP)biosemu$L + +.ENDIF + +#---------------------------------------------------------------------------- +# Sample test programs +#---------------------------------------------------------------------------- + +all: $(LIBFILE) warmboot$E + +warmboot$E: warmboot$O $(LIBFILE) + +#---------------------------------------------------------------------------- +# Target to build the Binary Portable DLL target +#---------------------------------------------------------------------------- + +biosemu.dll: $(DLL_OBJS) $(BIOS_OBJS) $(X86_OBJS) + +#---------------------------------------------------------------------------- +# Target to build all Intel binary drivers +#---------------------------------------------------------------------------- + +.PHONY mkdrv: + @build wc11-w32 biosemu.dll -u BUILD_DLL=1 NO_RUNTIME=1 OPT=1 + @$(CP) biosemu.dll $(PRIVATE)\nucleus\graphics\biosemu.bpd + @dmake cleanexe + +.PHONY db: + @build wc11-w32 biosemu.dll BUILD_DLL=1 NO_RUNTIME=1 OPT=1 + @$(CP) biosemu.dll $(PRIVATE)\nucleus\graphics\biosemu.bpd + +#---------------------------------------------------------------------------- +# Define the list of object files to create dependency information for +#---------------------------------------------------------------------------- + +DEPEND_OBJ = warmboot$O $(BIOS_OBJS) $(X86_OBJS) $(DLL_OBJS) +DEPEND_SRC = $(SCITECH)/src/x86emu;$(PRIVATE)/src/common +.SOURCE: $(SCITECH)/src/x86emu $(PRIVATE)/src/common + +.INCLUDE: "$(SCITECH)/makedefs/common.mk" diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross b/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross new file mode 100644 index 0000000..9141003 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross @@ -0,0 +1,10 @@ +CC = ppc-elf32-gcc +AR = ppc-elf32-ar + +CFLAGS = -D__DRIVER__ -I../../include -DDEBUG -I. + +BIOS_OBJS = biosemu.o bios.o besys.o +X86_OBJS = sys.o decode.o ops.o prim_ops.o fpu.o debug.o + +libbios.a: $(BIOS_OBJS) + $(AR) rcs libbios.a $(BIOS_OBJS) \ No newline at end of file diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c b/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c new file mode 100644 index 0000000..98d5fb8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c @@ -0,0 +1,569 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Module to implement warm booting of all PCI/AGP controllers +* on the bus. We use the x86 real mode emulator to run the +* BIOS on the primary and secondary controllers to bring +* the cards up. +* +****************************************************************************/ + +#include +#include +#include +#include +#include "biosemu.h" +#ifndef _MAX_PATH +#define _MAX_PATH 256 +#endif + +/*------------------------- Global Variables ------------------------------*/ + +static PCIDeviceInfo PCI[MAX_PCI_DEVICES]; +static int NumPCI = -1; +static int BridgeIndex[MAX_PCI_DEVICES] = {0}; +static int NumBridges; +static PCIBridgeInfo *AGPBridge = NULL; +static int DeviceIndex[MAX_PCI_DEVICES] = {0}; +static int NumDevices; +static u32 debugFlags = 0; +static BE_VGAInfo VGAInfo[MAX_PCI_DEVICES] = {{0}}; +static ibool useV86 = false; +static ibool forcePost = false; + +/* Length of the BIOS image */ + +#define MAX_BIOSLEN (64 * 1024L) +#define FINAL_BIOSLEN (32 * 1024L) + +/* Macro to determine if the VGA is enabled and responding */ + +#define VGA_NOT_ACTIVE() (forcePost || (PM_inpb(0x3CC) == 0xFF) || ((PM_inpb(0x3CC) & 0x2) == 0)) + +#define ENABLE_DEVICE(device) \ + PCI_writePCIRegB(0x4,PCI[DeviceIndex[device]].Command | 0x7,device) + +#define DISABLE_DEVICE(device) \ + PCI_writePCIRegB(0x4,0,device) + +/* Macros to enable and disable AGP VGA resources */ + +#define ENABLE_AGP_VGA() \ + PCI_accessReg(0x3E,AGPBridge->BridgeControl | 0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge) + +#define DISABLE_AGP_VGA() \ + PCI_accessReg(0x3E,AGPBridge->BridgeControl & ~0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge) + +#define RESTORE_AGP_VGA() \ + PCI_accessReg(0x3E,AGPBridge->BridgeControl,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge) + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +RETURNS: +The address to use to map the secondary BIOS (PCI/AGP devices) + +REMARKS: +Searches all the PCI base address registers for the device looking for a +memory mapping that is large enough to hold our ROM BIOS. We usually end up +finding the framebuffer mapping (usually BAR 0x10), and we use this mapping +to map the BIOS for the device into. We use a mapping that is already +assigned to the device to ensure the memory range will be passed through +by any PCI->PCI or AGP->PCI bridge that may be present. + +NOTE: Usually this function is only used for AGP devices, but it may be + used for PCI devices that have already been POST'ed and the BIOS + ROM base address has been zero'ed out. +****************************************************************************/ +static ulong PCI_findBIOSAddr( + int device) +{ + ulong base,size; + int bar; + + for (bar = 0x10; bar <= 0x14; bar++) { + base = PCI_readPCIRegL(bar,device) & ~0xFF; + if (!(base & 0x1)) { + PCI_writePCIRegL(bar,0xFFFFFFFF,device); + size = PCI_readPCIRegL(bar,device) & ~0xFF; + size = ~size+1; + PCI_writePCIRegL(bar,0,device); + if (size >= MAX_BIOSLEN) + return base; + } + } + return 0; +} + +/**************************************************************************** +REMARKS: +Re-writes the PCI base address registers for the secondary PCI controller +with the values from our initial PCI bus enumeration. This fixes up the +values after we have POST'ed the secondary display controller BIOS, which +may have incorrectly re-programmed the base registers the same as the +primary display controller (the case for identical S3 cards). +****************************************************************************/ +static void _PCI_fixupSecondaryBARs(void) +{ + int i; + + for (i = 0; i < NumDevices; i++) { + PCI_writePCIRegL(0x10,PCI[DeviceIndex[i]].BaseAddress10,i); + PCI_writePCIRegL(0x14,PCI[DeviceIndex[i]].BaseAddress14,i); + PCI_writePCIRegL(0x18,PCI[DeviceIndex[i]].BaseAddress18,i); + PCI_writePCIRegL(0x1C,PCI[DeviceIndex[i]].BaseAddress1C,i); + PCI_writePCIRegL(0x20,PCI[DeviceIndex[i]].BaseAddress20,i); + PCI_writePCIRegL(0x24,PCI[DeviceIndex[i]].BaseAddress24,i); + } +} + +/**************************************************************************** +RETURNS: +True if successfully initialised, false if not. + +REMARKS: +This function executes the BIOS POST code on the controller. We assume that +at this stage the controller has its I/O and memory space enabled and +that all other controllers are in a disabled state. +****************************************************************************/ +static void PCI_doBIOSPOST( + int device, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + RMREGS regs; + RMSREGS sregs; + + /* Determine the value to store in AX for BIOS POST */ + regs.x.ax = (u16)(PCI[DeviceIndex[device]].slot.i >> 8); + if (useV86) { + /* Post the BIOS using the PM functions (ie: v86 mode on Linux) */ + if (!PM_doBIOSPOST(regs.x.ax,BIOSPhysAddr,mappedBIOS,BIOSLen)) { + /* If the PM function fails, this probably means are we are on */ + /* DOS and can't re-map the real mode 0xC0000 region. In thise */ + /* case if the device is the primary, we can use the real */ + /* BIOS at 0xC0000 directly. */ + if (device == 0) + PM_doBIOSPOST(regs.x.ax,0xC0000,mappedBIOS,BIOSLen); + } + } + else { + /* Setup the X86 emulator for the VGA BIOS */ + BE_setVGA(&VGAInfo[device]); + + /* Execute the BIOS POST code */ + BE_callRealMode(0xC000,0x0003,®s,&sregs); + + /* Cleanup and exit */ + BE_getVGA(&VGAInfo[device]); + } +} + +/**************************************************************************** +RETURNS: +True if successfully initialised, false if not. + +REMARKS: +Loads and POST's the secondary controllers BIOS, directly from the BIOS +image we can extract over the PCI bus. +****************************************************************************/ +static ibool PCI_postControllers(void) +{ + int device; + ulong BIOSImageLen,mappedBIOSPhys; + uchar *mappedBIOS,*copyOfBIOS; + char filename[_MAX_PATH]; + FILE *f; + + /* Disable the primary display controller and AGP VGA pass-through */ + DISABLE_DEVICE(0); + if (AGPBridge) + DISABLE_AGP_VGA(); + + /* Now POST all the secondary controllers */ + for (device = 0; device < NumDevices; device++) { + /* Skip the device if it is not enabled (probably an ISA device) */ + if (DeviceIndex[device] == -1) + continue; + + /* Enable secondary display controller. If the secondary controller */ + /* is on the AGP bus, then enable VGA resources for the AGP device. */ + ENABLE_DEVICE(device); + if (AGPBridge && AGPBridge->SecondayBusNumber == PCI[DeviceIndex[device]].slot.p.Bus) + ENABLE_AGP_VGA(); + + /* Check if the controller has already been POST'ed */ + if (VGA_NOT_ACTIVE()) { + /* Find a viable place to map the secondary PCI BIOS image and map it */ + printk("Device %d not enabled, so attempting warm boot it\n", device); + + /* For AGP devices (and PCI devices that do have the ROM base */ + /* address zero'ed out) we have to map the BIOS to a location */ + /* that is passed by the AGP bridge to the bus. Some AGP devices */ + /* have the ROM base address already set up for us, and some */ + /* do not (we map to one of the existing BAR locations in */ + /* this case). */ + mappedBIOS = NULL; + if (PCI[DeviceIndex[device]].ROMBaseAddress != 0) + mappedBIOSPhys = PCI[DeviceIndex[device]].ROMBaseAddress & ~0xF; + else + mappedBIOSPhys = PCI_findBIOSAddr(device); + printk("Mapping BIOS image to 0x%08X\n", mappedBIOSPhys); + mappedBIOS = PM_mapPhysicalAddr(mappedBIOSPhys,MAX_BIOSLEN-1,false); + PCI_writePCIRegL(0x30,mappedBIOSPhys | 0x1,device); + BIOSImageLen = mappedBIOS[2] * 512; + if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) + return false; + memcpy(copyOfBIOS,mappedBIOS,BIOSImageLen); + PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1); + + /* Allocate memory to store copy of BIOS from secondary controllers */ + VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; + VGAInfo[device].BIOSImage = copyOfBIOS; + VGAInfo[device].BIOSImageLen = BIOSImageLen; + + /* Restore device mappings */ + PCI_writePCIRegL(0x30,PCI[DeviceIndex[device]].ROMBaseAddress,device); + PCI_writePCIRegL(0x10,PCI[DeviceIndex[device]].BaseAddress10,device); + PCI_writePCIRegL(0x14,PCI[DeviceIndex[device]].BaseAddress14,device); + + /* Now execute the BIOS POST for the device */ + if (copyOfBIOS[0] == 0x55 && copyOfBIOS[1] == 0xAA) { + printk("Executing BIOS POST for controller.\n"); + PCI_doBIOSPOST(device,mappedBIOSPhys,copyOfBIOS,BIOSImageLen); + } + + /* Reset the size of the BIOS image to the final size */ + VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; + + /* Save the BIOS and interrupt vector information to disk */ + sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); + if ((f = fopen(filename,"wb")) != NULL) { + fwrite(copyOfBIOS,1,FINAL_BIOSLEN,f); + fwrite(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); + fclose(f); + } + } + else { + /* Allocate memory to store copy of BIOS from secondary controllers */ + if ((copyOfBIOS = malloc(FINAL_BIOSLEN)) == NULL) + return false; + VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; + VGAInfo[device].BIOSImage = copyOfBIOS; + VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; + + /* Load the BIOS and interrupt vector information from disk */ + sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); + if ((f = fopen(filename,"rb")) != NULL) { + fread(copyOfBIOS,1,FINAL_BIOSLEN,f); + fread(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); + fclose(f); + } + } + + /* Fix up all the secondary PCI base address registers */ + /* (restores them all from the values we read previously) */ + _PCI_fixupSecondaryBARs(); + + /* Disable the secondary controller and AGP VGA pass-through */ + DISABLE_DEVICE(device); + if (AGPBridge) + DISABLE_AGP_VGA(); + } + + /* Reenable primary display controller and reset AGP bridge control */ + if (AGPBridge) + RESTORE_AGP_VGA(); + ENABLE_DEVICE(0); + + /* Free physical BIOS image mapping */ + PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1); + + /* Restore the X86 emulator BIOS info to primary controller */ + if (!useV86) + BE_setVGA(&VGAInfo[0]); + return true; +} + +/**************************************************************************** +REMARKS: +Enumerates the PCI bus and dumps the PCI configuration information to the +log file. +****************************************************************************/ +static void EnumeratePCI(void) +{ + int i,index; + PCIBridgeInfo *info; + + printk("Displaying enumeration of PCI bus (%d devices, %d display devices)\n", + NumPCI, NumDevices); + for (index = 0; index < NumDevices; index++) + printk(" Display device %d is PCI device %d\n",index,DeviceIndex[index]); + printk("\n"); + printk("Bus Slot Fnc DeviceID SubSystem Rev Class IRQ Int Cmd\n"); + for (i = 0; i < NumPCI; i++) { + printk("%2d %2d %2d %04X:%04X %04X:%04X %02X %02X:%02X %02X %02X %04X ", + PCI[i].slot.p.Bus, + PCI[i].slot.p.Device, + PCI[i].slot.p.Function, + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].SubSystemVendorID, + PCI[i].SubSystemID, + PCI[i].RevID, + PCI[i].BaseClass, + PCI[i].SubClass, + PCI[i].InterruptLine, + PCI[i].InterruptPin, + PCI[i].Command); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } + printk("\n"); + printk("DeviceID Stat Ifc Cch Lat Hdr BIST\n"); + for (i = 0; i < NumPCI; i++) { + printk("%04X:%04X %04X %02X %02X %02X %02X %02X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].Status, + PCI[i].Interface, + PCI[i].CacheLineSize, + PCI[i].LatencyTimer, + PCI[i].HeaderType, + PCI[i].BIST); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } + printk("\n"); + printk("DeviceID Base10h Base14h Base18h Base1Ch Base20h Base24h ROMBase\n"); + for (i = 0; i < NumPCI; i++) { + printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].BaseAddress10, + PCI[i].BaseAddress14, + PCI[i].BaseAddress18, + PCI[i].BaseAddress1C, + PCI[i].BaseAddress20, + PCI[i].BaseAddress24, + PCI[i].ROMBaseAddress); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } + printk("\n"); + printk("DeviceID BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n"); + for (i = 0; i < NumPCI; i++) { + printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].BaseAddress10Len, + PCI[i].BaseAddress14Len, + PCI[i].BaseAddress18Len, + PCI[i].BaseAddress1CLen, + PCI[i].BaseAddress20Len, + PCI[i].BaseAddress24Len, + PCI[i].ROMBaseAddressLen); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } + printk("\n"); + printk("Displaying enumeration of %d bridge devices\n",NumBridges); + printk("\n"); + printk("DeviceID P# S# B# IOB IOL MemBase MemLimit PreBase PreLimit Ctrl\n"); + for (i = 0; i < NumBridges; i++) { + info = (PCIBridgeInfo*)&PCI[BridgeIndex[i]]; + printk("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n", + info->VendorID, + info->DeviceID, + info->PrimaryBusNumber, + info->SecondayBusNumber, + info->SubordinateBusNumber, + ((u16)info->IOBase << 8) & 0xF000, + info->IOLimit ? + ((u16)info->IOLimit << 8) | 0xFFF : 0, + ((u32)info->MemoryBase << 16) & 0xFFF00000, + info->MemoryLimit ? + ((u32)info->MemoryLimit << 16) | 0xFFFFF : 0, + ((u32)info->PrefetchableMemoryBase << 16) & 0xFFF00000, + info->PrefetchableMemoryLimit ? + ((u32)info->PrefetchableMemoryLimit << 16) | 0xFFFFF : 0, + info->BridgeControl); + } + printk("\n"); +} + +/**************************************************************************** +RETURNS: +Number of display devices found. + +REMARKS: +This function enumerates the number of available display devices on the +PCI bus, and returns the number found. +****************************************************************************/ +static int PCI_enumerateDevices(void) +{ + int i,j; + PCIBridgeInfo *info; + + /* If this is the first time we have been called, enumerate all */ + /* devices on the PCI bus. */ + if (NumPCI == -1) { + for (i = 0; i < MAX_PCI_DEVICES; i++) + PCI[i].dwSize = sizeof(PCI[i]); + if ((NumPCI = PCI_enumerate(PCI,MAX_PCI_DEVICES)) == 0) + return -1; + + /* Build a list of all PCI bridge devices */ + for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { + if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) { + if (NumBridges < MAX_PCI_DEVICES) + BridgeIndex[NumBridges++] = i; + } + } + + /* Now build a list of all display class devices */ + for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { + if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { + if ((PCI[i].Command & 0x3) == 0x3) { + DeviceIndex[0] = i; + } + else { + if (NumDevices < MAX_PCI_DEVICES) + DeviceIndex[NumDevices++] = i; + } + if (PCI[i].slot.p.Bus != 0) { + /* This device is on a different bus than the primary */ + /* PCI bus, so it is probably an AGP device. Find the */ + /* AGP bus device that controls that bus so we can */ + /* control it. */ + for (j = 0; j < NumBridges; j++) { + info = (PCIBridgeInfo*)&PCI[BridgeIndex[j]]; + if (info->SecondayBusNumber == PCI[i].slot.p.Bus) { + AGPBridge = info; + break; + } + } + } + } + } + + /* Enumerate all PCI and bridge devices to log file */ + EnumeratePCI(); + } + return NumDevices; +} + +FILE *logfile; + +void printk(const char *fmt, ...) +{ + va_list argptr; + va_start(argptr, fmt); + vfprintf(logfile, fmt, argptr); + fflush(logfile); + va_end(argptr); +} + +int main(int argc,char *argv[]) +{ + while (argc > 1) { + if (stricmp(argv[1],"-usev86") == 0) { + useV86 = true; + } + else if (stricmp(argv[1],"-force") == 0) { + forcePost = true; + } +#ifdef DEBUG + else if (stricmp(argv[1],"-decode") == 0) { + debugFlags |= DEBUG_DECODE_F; + } + else if (stricmp(argv[1],"-iotrace") == 0) { + debugFlags |= DEBUG_IO_TRACE_F; + } +#endif + else { + printf("Usage: warmboot [-usev86] [-force] [-decode] [-iotrace]\n"); + exit(-1); + } + argc--; + argv++; + } + if ((logfile = fopen("warmboot.log","w")) == NULL) + exit(1); + + PM_init(); + if (!useV86) { + /* Initialise the x86 BIOS emulator */ + BE_init(false,debugFlags,65536,&VGAInfo[0]); + } + + /* Enumerate all devices (which POST's them at the same time) */ + if (PCI_enumerateDevices() < 1) { + printk("No PCI display devices found!\n"); + return -1; + } + + /* Post all the display controller BIOS'es */ + PCI_postControllers(); + + /* Cleanup and exit the emulator */ + if (!useV86) + BE_exit(); + fclose(logfile); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm new file mode 100644 index 0000000..61a9024 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm @@ -0,0 +1,51 @@ +;**************************************************************************** +;* +;* SciTech Nucleus Audio Architecture +;* +;* Copyright (C) 1991-1998 SciTech Software, Inc. +;* All rights reserved. +;* +;* ====================================================================== +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* | | +;* |This copyrighted computer code contains proprietary technology | +;* |owned by SciTech Software, Inc., located at 505 Wall Street, | +;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +;* | | +;* |The contents of this file are subject to the SciTech Nucleus | +;* |License; you may *not* use this file or related software except in | +;* |compliance with the License. You may obtain a copy of the License | +;* |at http://www.scitechsoft.com/nucleus-license.txt | +;* | | +;* |Software distributed under the License is distributed on an | +;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +;* |implied. See the License for the specific language governing | +;* |rights and limitations under the License. | +;* | | +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* ====================================================================== +;* +;* Language: TASM 4.0 or NASM +;* Environment: IBM PC 32 bit Protected Mode. +;* +;* Description: Module to implement the import stubs for all the Nucleus +;* Audio API functions for Intel binary compatible drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +BEGIN_IMPORTS_DEF _AA_exports +SKIP_IMP AA_status ; Implemented in C code +SKIP_IMP AA_errorMsg ; Implemented in C code +SKIP_IMP AA_getDaysLeft ; Implemented in C code +SKIP_IMP AA_registerLicense ; Implemented in C code +SKIP_IMP AA_enumerateDevices ; Implemented in C code +SKIP_IMP AA_loadDriver ; Implemented in C code +DECLARE_IMP AA_unloadDriver +DECLARE_IMP AA_saveOptions +END_IMPORTS_DEF + + END diff --git a/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm new file mode 100644 index 0000000..5317600 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm @@ -0,0 +1,136 @@ +;**************************************************************************** +;* +;* SciTech Nucleus Graphics Architecture +;* +;* Copyright (C) 1991-1998 SciTech Software, Inc. +;* All rights reserved. +;* +;* ====================================================================== +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* | | +;* |This copyrighted computer code contains proprietary technology | +;* |owned by SciTech Software, Inc., located at 505 Wall Street, | +;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +;* | | +;* |The contents of this file are subject to the SciTech Nucleus | +;* |License; you may *not* use this file or related software except in | +;* |compliance with the License. You may obtain a copy of the License | +;* |at http://www.scitechsoft.com/nucleus-license.txt | +;* | | +;* |Software distributed under the License is distributed on an | +;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +;* |implied. See the License for the specific language governing | +;* |rights and limitations under the License. | +;* | | +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* ====================================================================== +;* +;* Language: TASM 4.0 or NASM +;* Environment: IBM PC 32 bit Protected Mode. +;* +;* Description: Module to implement the import stubs for all the Nucleus +;* Graphics API functions for Intel binary compatible drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +BEGIN_IMPORTS_DEF __GA_exports +SKIP_IMP GA_status,0 ; Implemented in C code +SKIP_IMP GA_errorMsg,1 ; Implemented in C code +SKIP_IMP GA_getDaysLeft,1 ; Implemented in C code +SKIP_IMP GA_registerLicense,2 ; Implemented in C code +SKIP_IMP GA_enumerateDevices,1 ; Implemented in C code +SKIP_IMP GA_loadDriver,2 ; Implemented in C code +DECLARE_IMP GA_setActiveDevice,1 +SKIP_IMP GA_reserved1,0 ; Implemented in C code +DECLARE_IMP GA_unloadDriver,1 +DECLARE_IMP REF2D_loadDriver,6 +DECLARE_IMP REF2D_unloadDriver,2 +DECLARE_IMP GA_loadRef2d,5 +DECLARE_IMP GA_unloadRef2d,1 +DECLARE_IMP GA_softStereoInit,1 +DECLARE_IMP GA_softStereoOn,0 +DECLARE_IMP GA_softStereoScheduleFlip,2 +DECLARE_IMP GA_softStereoGetFlipStatus,0 +DECLARE_IMP GA_softStereoWaitTillFlipped,0 +DECLARE_IMP GA_softStereoOff,0 +DECLARE_IMP GA_softStereoExit,0 +DECLARE_IMP GA_saveModeProfile,2 +DECLARE_IMP GA_saveOptions,2 +DECLARE_IMP GA_saveCRTCTimings,1 +DECLARE_IMP GA_restoreCRTCTimings,1 +DECLARE_IMP DDC_init,1 +DECLARE_IMP DDC_readEDID,5 +DECLARE_IMP EDID_parse,3 +DECLARE_IMP MCS_begin,1 +DECLARE_IMP MCS_getCapabilitiesString,2 +DECLARE_IMP MCS_isControlSupported,1 +DECLARE_IMP MCS_enableControl,2 +DECLARE_IMP MCS_getControlMax,2 +DECLARE_IMP MCS_getControlValue,2 +DECLARE_IMP MCS_getControlValues,3 +DECLARE_IMP MCS_setControlValue,2 +DECLARE_IMP MCS_setControlValues,3 +DECLARE_IMP MCS_resetControl,1 +DECLARE_IMP MCS_saveCurrentSettings,0 +DECLARE_IMP MCS_getTimingReport,3 +DECLARE_IMP MCS_getSelfTestReport,3 +DECLARE_IMP MCS_end,0 +SKIP_IMP GA_loadInGUI,1 ; Implemented in C code +DECLARE_IMP DDC_writeEDID,6 +DECLARE_IMP GA_useDoubleScan,1 +DECLARE_IMP GA_getMaxRefreshRate,4 +DECLARE_IMP GA_computeCRTCTimings,6 +DECLARE_IMP GA_addMode,5 +DECLARE_IMP GA_addRefresh,5 +DECLARE_IMP GA_delMode,5 +DECLARE_IMP N_getLogName,0 +SKIP_IMP2 N_log +DECLARE_IMP MDBX_getErrCode,0 +DECLARE_IMP MDBX_getErrorMsg,0 +DECLARE_IMP MDBX_open,1 +DECLARE_IMP MDBX_close,0 +DECLARE_IMP MDBX_first,1 +DECLARE_IMP MDBX_last,1 +DECLARE_IMP MDBX_next,1 +DECLARE_IMP MDBX_prev,1 +DECLARE_IMP MDBX_insert,1 +DECLARE_IMP MDBX_update,1 +DECLARE_IMP MDBX_flush,0 +DECLARE_IMP MDBX_importINF,2 +SKIP_IMP GA_getGlobalOptions,2 ; Implemented in C code +DECLARE_IMP GA_setGlobalOptions,1 +DECLARE_IMP GA_saveGlobalOptions,1 +DECLARE_IMP GA_getInternalName,1 +DECLARE_IMP GA_getNucleusConfigPath,0 +DECLARE_IMP GA_getFakePCIID,0 +SKIP_IMP GA_loadLibrary,3 ; Implemented in C code +SKIP_IMP GA_isOEMVersion,1 ; Implemented in C code +DECLARE_IMP GA_isLiteVersion,1 +DECLARE_IMP GA_getDisplaySerialNo,1 +DECLARE_IMP GA_getDisplayUserName,1 +SKIP_IMP GA_getCurrentDriver,1 ; Implemented in C code +SKIP_IMP GA_getCurrentRef2d,1 ; Implemented in C code +SKIP_IMP GA_getLicensedDevices,1 ; Implemented in C code +DECLARE_IMP DDC_initExt,2 +DECLARE_IMP MCS_beginExt,2 +DECLARE_IMP GA_loadRegionMgr,3 +DECLARE_IMP GA_unloadRegionMgr,1 +DECLARE_IMP GA_getProcAddress,2 +DECLARE_IMP GA_enableVBEMode,5 +DECLARE_IMP GA_disableVBEMode,5 +DECLARE_IMP GA_loadModeProfile,2 +DECLARE_IMP GA_getCRTCTimings,4 +DECLARE_IMP GA_setCRTCTimings,4 +DECLARE_IMP GA_setDefaultRefresh,6 +DECLARE_IMP GA_saveMonitorInfo,2 +DECLARE_IMP GA_detectPnPMonitor,3 +SKIP_IMP3 GA_queryFunctions +SKIP_IMP3 REF2D_queryFunctions +END_IMPORTS_DEF + + END + diff --git a/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm b/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm new file mode 100644 index 0000000..0194a62 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm @@ -0,0 +1,248 @@ +;**************************************************************************** +;* +;* SciTech Nucleus Graphics Architecture +;* +;* Copyright (C) 1991-1998 SciTech Software, Inc. +;* All rights reserved. +;* +;* ====================================================================== +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* | | +;* |This copyrighted computer code contains proprietary technology | +;* |owned by SciTech Software, Inc., located at 505 Wall Street, | +;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +;* | | +;* |The contents of this file are subject to the SciTech Nucleus | +;* |License; you may *not* use this file or related software except in | +;* |compliance with the License. You may obtain a copy of the License | +;* |at http://www.scitechsoft.com/nucleus-license.txt | +;* | | +;* |Software distributed under the License is distributed on an | +;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +;* |implied. See the License for the specific language governing | +;* |rights and limitations under the License. | +;* | | +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* ====================================================================== +;* +;* Language: 80386 Assembler, NASM or TASM +;* Environment: IBM PC 32 bit Protected Mode. +;* +;* Description: Assembly support functions for the Nucleus library for +;* the high resolution timing support functions provided by +;* the Intel Pentium and compatible processors. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _gatimer + +begcodeseg _gatimer + +ifdef USE_NASM +%macro mCPU_ID 0 +db 00Fh,0A2h +%endmacro +else +MACRO mCPU_ID +db 00Fh,0A2h +ENDM +endif + +ifdef USE_NASM +%macro mRDTSC 0 +db 00Fh,031h +%endmacro +else +MACRO mRDTSC +db 00Fh,031h +ENDM +endif + +;---------------------------------------------------------------------------- +; bool _GA_haveCPUID(void) +;---------------------------------------------------------------------------- +; Determines if we have support for the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _GA_haveCPUID + + enter_c + pushfd ; Get original EFLAGS + pop eax + mov ecx, eax + xor eax, 200000h ; Flip ID bit in EFLAGS + push eax ; Save new EFLAGS value on stack + popfd ; Replace current EFLAGS value + pushfd ; Get new EFLAGS + pop eax ; Store new EFLAGS in EAX + xor eax, ecx ; Can not toggle ID bit, + jnz @@1 ; Processor=80486 + mov eax,0 ; We dont have CPUID support + jmp @@Done +@@1: mov eax,1 ; We have CPUID support +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uint _GA_getCPUIDFeatures(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _GA_getCPUIDFeatures + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + mov eax, edx +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; void _GA_readTimeStamp(GA_largeInteger *time) +;---------------------------------------------------------------------------- +; Reads the time stamp counter and returns the 64-bit result. +;---------------------------------------------------------------------------- +cprocstart _GA_readTimeStamp + + mRDTSC + mov ecx,[esp+4] ; Access directly without stack frame + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; N_uint32 GA_TimerDifference(GA_largeInteger *a,GA_largeInteger *b) +;---------------------------------------------------------------------------- +; Computes the difference between two 64-bit numbers (a-b) +;---------------------------------------------------------------------------- +cprocstart GA_TimerDifference + + ARG a:DPTR, b:DPTR, t:DPTR + + enter_c + + mov ecx,[a] + mov eax,[ecx] ; EAX := b.low + mov ecx,[b] + sub eax,[ecx] + mov edx,eax ; EDX := low difference + mov ecx,[a] + mov eax,[ecx+4] ; ECX := b.high + mov ecx,[b] + sbb eax,[ecx+4] ; EAX := high difference + mov eax,edx ; Return low part + + leave_c + ret + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY_TIMER 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +else +macro DELAY_TIMER + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +endif + +;---------------------------------------------------------------------------- +; void _OS_delay8253(N_uint32 microSeconds); +;---------------------------------------------------------------------------- +; Delays for the specified number of microseconds, by directly programming +; the 8253 timer chips. +;---------------------------------------------------------------------------- +cprocstart _OS_delay8253 + + ARG microSec:UINT + + enter_c + +; Start timer 2 counting + + mov _ax,[microSec] ; EAX := count in microseconds + mov ecx,1196 + mul ecx + mov ecx,1000 + div ecx + mov ecx,eax ; ECX := count in timer ticks + in al,61h + or al,1 + out 61h,al + +; Set the timer 2 count to 0 again to start the timing interval. + + mov al,10110100b ; set up to load initial (timer 2) + out 43h,al ; timer count + DELAY_TIMER + sub al,al + out 42h,al ; load count lsb + DELAY_TIMER + out 42h,al ; load count msb + xor di,di ; Allow max 64K loop iterations + +@@LoopStart: + dec di ; This is a guard against the possibility that + jz @@LoopEnd ; someone eg. stopped the timer behind our back. + ; After 64K iterations we bail out no matter what + ; (and hope it wasn't too soon) + mov al,00000000b ; latch timer 0 + out 43h,al + DELAY_TIMER + in al,42h ; least significant byte + DELAY_TIMER + mov ah,al + in al,42h ; most significant byte + xchg ah,al + neg ax ; Convert from countdown remaining + ; to elapsed count + cmp ax,cx ; Has delay expired? + jb @@LoopStart ; No, so loop till done + +; Stop timer 2 from counting +@@LoopEnd: + in al,61H + and al,0FEh + out 61H,al + +; Some programs have a problem if we change the control port; better change it +; to something they expect (mode 3 - square wave generator)... + mov al,0B6h + out 43h,al + + leave_c + ret + +cprocend + +endcodeseg _gatimer + + END + diff --git a/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm new file mode 100644 index 0000000..d4b1179 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm @@ -0,0 +1,195 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* Copyright (C) 1991-1998 SciTech Software, Inc. +;* All rights reserved. +;* +;* ====================================================================== +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* | | +;* |This copyrighted computer code contains proprietary technology | +;* |owned by SciTech Software, Inc., located at 505 Wall Street, | +;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +;* | | +;* |The contents of this file are subject to the SciTech Nucleus | +;* |License; you may *not* use this file or related software except in | +;* |compliance with the License. You may obtain a copy of the License | +;* |at http://www.scitechsoft.com/nucleus-license.txt | +;* | | +;* |Software distributed under the License is distributed on an | +;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +;* |implied. See the License for the specific language governing | +;* |rights and limitations under the License. | +;* | | +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* ====================================================================== +;* +;* Language: TASM 4.0 or NASM +;* Environment: IBM PC 32 bit Protected Mode. +;* +;* Description: Module to implement the import stubs for all the PM +;* API functions for Intel binary portable drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +BEGIN_IMPORTS_DEF _PM_imports +DECLARE_IMP PM_getModeType,0 +DECLARE_IMP PM_getBIOSPointer,0 +DECLARE_IMP PM_getA0000Pointer,0 +DECLARE_IMP PM_mapPhysicalAddr,0 +DECLARE_IMP PM_mallocShared,0 +SKIP_IMP _PM_reserved1,0 +DECLARE_IMP PM_freeShared,0 +DECLARE_IMP PM_mapToProcess,0 +DECLARE_IMP PM_mapRealPointer,0 +DECLARE_IMP PM_allocRealSeg,0 +DECLARE_IMP PM_freeRealSeg,0 +DECLARE_IMP PM_allocLockedMem,0 +DECLARE_IMP PM_freeLockedMem,0 +DECLARE_IMP PM_callRealMode,0 +DECLARE_IMP PM_int86,0 +DECLARE_IMP PM_int86x,0 +DECLARE_IMP DPMI_int86,0 +DECLARE_IMP PM_availableMemory,0 +DECLARE_IMP PM_getVESABuf,0 +DECLARE_IMP PM_getOSType,0 +DECLARE_IMP PM_fatalError,0 +DECLARE_IMP PM_setBankA,0 +DECLARE_IMP PM_setBankAB,0 +DECLARE_IMP PM_setCRTStart,0 +DECLARE_IMP PM_getCurrentPat,0 +DECLARE_IMP PM_getVBEAFPath,0 +DECLARE_IMP PM_getNucleusPath,0 +DECLARE_IMP PM_getNucleusConfigPath,0 +DECLARE_IMP PM_getUniqueID,0 +DECLARE_IMP PM_getMachineName,0 +DECLARE_IMP VF_available,0 +DECLARE_IMP VF_init,0 +DECLARE_IMP VF_exit,0 +DECLARE_IMP PM_openConsole,0 +DECLARE_IMP PM_getConsoleStateSize,0 +DECLARE_IMP PM_saveConsoleState,0 +DECLARE_IMP PM_restoreConsoleState,0 +DECLARE_IMP PM_closeConsole,0 +DECLARE_IMP PM_setOSCursorLocation,0 +DECLARE_IMP PM_setOSScreenWidth,0 +DECLARE_IMP PM_enableWriteCombine,0 +DECLARE_IMP PM_backslash,0 +DECLARE_IMP PM_lockDataPages,0 +DECLARE_IMP PM_unlockDataPages,0 +DECLARE_IMP PM_lockCodePages,0 +DECLARE_IMP PM_unlockCodePages,0 +DECLARE_IMP PM_setRealTimeClockHandler,0 +DECLARE_IMP PM_setRealTimeClockFrequency,0 +DECLARE_IMP PM_restoreRealTimeClockHandler,0 +DECLARE_IMP PM_doBIOSPOST,0 +DECLARE_IMP PM_getBootDrive,0 +DECLARE_IMP PM_freePhysicalAddr,0 +DECLARE_IMP PM_inpb,0 +DECLARE_IMP PM_inpw,0 +DECLARE_IMP PM_inpd,0 +DECLARE_IMP PM_outpb,0 +DECLARE_IMP PM_outpw,0 +DECLARE_IMP PM_outpd,0 +SKIP_IMP _PM_reserved2,0 +DECLARE_IMP PM_setSuspendAppCallback,0 +DECLARE_IMP PM_haveBIOSAccess,0 +DECLARE_IMP PM_kbhit,0 +DECLARE_IMP PM_getch,0 +DECLARE_IMP PM_findBPD,0 +DECLARE_IMP PM_getPhysicalAddr,0 +DECLARE_IMP PM_sleep,0 +DECLARE_IMP PM_getCOMPort,0 +DECLARE_IMP PM_getLPTPort,0 +DECLARE_IMP PM_loadLibrary,0 +DECLARE_IMP PM_getProcAddress,0 +DECLARE_IMP PM_freeLibrary,0 +DECLARE_IMP PCI_enumerate,0 +DECLARE_IMP PCI_accessReg,0 +DECLARE_IMP PCI_setHardwareIRQ,0 +DECLARE_IMP PCI_generateSpecialCyle,0 +SKIP_IMP _PM_reserved3,0 +DECLARE_IMP PCIBIOS_getEntry,0 +DECLARE_IMP CPU_getProcessorType,0 +DECLARE_IMP CPU_haveMMX,0 +DECLARE_IMP CPU_have3DNow,0 +DECLARE_IMP CPU_haveSSE,0 +DECLARE_IMP CPU_haveRDTSC,0 +DECLARE_IMP CPU_getProcessorSpeed,0 +DECLARE_IMP ZTimerInit,0 +DECLARE_IMP LZTimerOn,0 +DECLARE_IMP LZTimerLap,0 +DECLARE_IMP LZTimerOff,0 +DECLARE_IMP LZTimerCount,0 +DECLARE_IMP LZTimerOnExt,0 +DECLARE_IMP LZTimerLapExt,0 +DECLARE_IMP LZTimerOffExt,0 +DECLARE_IMP LZTimerCountExt,0 +DECLARE_IMP ULZTimerOn,0 +DECLARE_IMP ULZTimerLap,0 +DECLARE_IMP ULZTimerOff,0 +DECLARE_IMP ULZTimerCount,0 +DECLARE_IMP ULZReadTime,0 +DECLARE_IMP ULZElapsedTime,0 +DECLARE_IMP ULZTimerResolution,0 +DECLARE_IMP PM_findFirstFile,0 +DECLARE_IMP PM_findNextFile,0 +DECLARE_IMP PM_findClose,0 +DECLARE_IMP PM_makepath,0 +DECLARE_IMP PM_splitpath,0 +DECLARE_IMP PM_driveValid,0 +DECLARE_IMP PM_getdcwd,0 +DECLARE_IMP PM_setFileAttr,0 +DECLARE_IMP PM_mkdir,0 +DECLARE_IMP PM_rmdir,0 +DECLARE_IMP PM_getFileAttr,0 +DECLARE_IMP PM_getFileTime,0 +DECLARE_IMP PM_setFileTime,0 +DECLARE_IMP CPU_getProcessorName,0 +DECLARE_IMP PM_getVGAStateSize,0 +DECLARE_IMP PM_saveVGAState,0 +DECLARE_IMP PM_restoreVGAState,0 +DECLARE_IMP PM_vgaBlankDisplay,0 +DECLARE_IMP PM_vgaUnblankDisplay,0 +DECLARE_IMP PM_blockUntilTimeout,0 +DECLARE_IMP _PM_add64,0 +DECLARE_IMP _PM_sub64,0 +DECLARE_IMP _PM_mul64,0 +DECLARE_IMP _PM_div64,0 +DECLARE_IMP _PM_shr64,0 +DECLARE_IMP _PM_sar64,0 +DECLARE_IMP _PM_shl64,0 +DECLARE_IMP _PM_neg64,0 +DECLARE_IMP PCI_findBARSize,0 +DECLARE_IMP PCI_readRegBlock,0 +DECLARE_IMP PCI_writeRegBlock,0 +DECLARE_IMP PM_flushTLB,0 +DECLARE_IMP PM_useLocalMalloc,0 +DECLARE_IMP PM_malloc,0 +DECLARE_IMP PM_calloc,0 +DECLARE_IMP PM_realloc,0 +DECLARE_IMP PM_free,0 +DECLARE_IMP PM_getPhysicalAddrRange,0 +DECLARE_IMP PM_allocPage,0 +DECLARE_IMP PM_freePage,0 +DECLARE_IMP PM_agpInit,0 +DECLARE_IMP PM_agpExit,0 +DECLARE_IMP PM_agpReservePhysical,0 +DECLARE_IMP PM_agpReleasePhysical,0 +DECLARE_IMP PM_agpCommitPhysical,0 +DECLARE_IMP PM_agpFreePhysical,0 +DECLARE_IMP PCI_getNumDevices,0 +DECLARE_IMP PM_setLocalBPDPath,0 +DECLARE_IMP PM_loadDirectDraw,0 +DECLARE_IMP PM_unloadDirectDraw,0 +DECLARE_IMP PM_getDirectDrawWindow,0 +DECLARE_IMP PM_doSuspendApp,0 +END_IMPORTS_DEF + + END + diff --git a/board/MAI/bios_emulator/scitech/src/common/aabeos.c b/board/MAI/bios_emulator/scitech/src/common/aabeos.c new file mode 100644 index 0000000..ad5698a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aabeos.c @@ -0,0 +1,92 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Linux operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timeval t; + gettimeofday(&t, NULL); + value->low = t.tv_sec*1000000 + t.tv_usec; + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aados.c b/board/MAI/bios_emulator/scitech/src/common/aados.c new file mode 100644 index 0000000..342d2f3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aados.c @@ -0,0 +1,64 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: MSDOS +* +* Description: OS specific Nucleus Graphics Architecture services for +* the MSDOS operating system. +* +****************************************************************************/ + +#include "pm_help.h" +#include "pmapi.h" +#include +#include +#include + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the DOS +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aalib.c b/board/MAI/bios_emulator/scitech/src/common/aalib.c new file mode 100644 index 0000000..5003b22 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aalib.c @@ -0,0 +1,225 @@ +/**************************************************************************** +* +* SciTech Nucleus Audio Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Any 32-bit protected mode environment +* +* Description: C module for the Graphics Accelerator Driver API. Uses +* the SciTech PM library for interfacing with DOS +* extender specific functions. +* +****************************************************************************/ + +#include "nucleus/audio.h" +#ifdef __WIN32_VXD__ +#include "sdd/sddhelp.h" +#else +#include +#include +#endif + +/*---------------------------- Global Variables ---------------------------*/ + +#ifdef TEST_HARNESS +extern PM_imports _VARAPI _PM_imports; +#else +AA_exports _VARAPI _AA_exports; +static int loaded = false; +static PE_MODULE *hModBPD = NULL; + +#ifdef __DRIVER__ +extern PM_imports _PM_imports; +#else +#include "pmimp.h" +#endif + +static N_imports _N_imports = { + sizeof(N_imports), + _OS_delay, + }; + +#ifdef __DRIVER__ +extern AA_imports _AA_imports; +#else +static AA_imports _AA_imports = { + sizeof(AA_imports), + }; +#endif +#endif + +/*----------------------------- Implementation ----------------------------*/ + +#define DLL_NAME "audio.bpd" + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Fatal error handler for non-exported AA_exports. +****************************************************************************/ +static void _AA_fatalErrorHandler(void) +{ + PM_fatalError("Unsupported Nucleus export function called! Please upgrade your copy of Nucleus!\n"); +} + +/**************************************************************************** +REMARKS: +Loads the Nucleus binary portable DLL into memory and initilises it. +****************************************************************************/ +static ibool LoadDriver(void) +{ + AA_initLibrary_t AA_initLibrary; + AA_exports *aaExp; + char filename[PM_MAX_PATH]; + char bpdpath[PM_MAX_PATH]; + int i,max; + ulong *p; + + /* Check if we have already loaded the driver */ + if (loaded) + return true; + PM_init(); + _AA_exports.dwSize = sizeof(_AA_exports); + + /* Open the BPD file */ + if (!PM_findBPD(DLL_NAME,bpdpath)) + return false; + strcpy(filename,bpdpath); + strcat(filename,DLL_NAME); + if ((hModBPD = PE_loadLibrary(filename,false)) == NULL) + return false; + if ((AA_initLibrary = (AA_initLibrary_t)PE_getProcAddress(hModBPD,"_AA_initLibrary")) == NULL) + return false; + bpdpath[strlen(bpdpath)-1] = 0; + if (strcmp(bpdpath,PM_getNucleusPath()) == 0) + strcpy(bpdpath,PM_getNucleusConfigPath()); + else { + PM_backslash(bpdpath); + strcat(bpdpath,"config"); + } + if ((aaExp = AA_initLibrary(bpdpath,filename,&_PM_imports,&_N_imports,&_AA_imports)) == NULL) + PM_fatalError("AA_initLibrary failed!\n"); + + /* Initialize all default imports to point to fatal error handler + * for upwards compatibility, and copy the exported functions. + */ + max = sizeof(_AA_exports)/sizeof(AA_initLibrary_t); + for (i = 0,p = (ulong*)&_AA_exports; i < max; i++) + *p++ = (ulong)_AA_fatalErrorHandler; + memcpy(&_AA_exports,aaExp,MIN(sizeof(_AA_exports),aaExp->dwSize)); + loaded = true; + return true; +} + +/* The following are stub entry points that the application calls to + * initialise the Nucleus loader library, and we use this to load our + * driver DLL from disk and initialise the library using it. + */ + +/* {secret} */ +int NAPI AA_status(void) +{ + if (!loaded) + return nDriverNotFound; + return _AA_exports.AA_status(); +} + +/* {secret} */ +const char * NAPI AA_errorMsg( + N_int32 status) +{ + if (!loaded) + return "Unable to load Nucleus device driver!"; + return _AA_exports.AA_errorMsg(status); +} + +/* {secret} */ +int NAPI AA_getDaysLeft(void) +{ + if (!LoadDriver()) + return -1; + return _AA_exports.AA_getDaysLeft(); +} + +/* {secret} */ +int NAPI AA_registerLicense(uchar *license) +{ + if (!LoadDriver()) + return 0; + return _AA_exports.AA_registerLicense(license); +} + +/* {secret} */ +int NAPI AA_enumerateDevices(void) +{ + if (!LoadDriver()) + return 0; + return _AA_exports.AA_enumerateDevices(); +} + +/* {secret} */ +AA_devCtx * NAPI AA_loadDriver(N_int32 deviceIndex) +{ + if (!LoadDriver()) + return NULL; + return _AA_exports.AA_loadDriver(deviceIndex); +} +#endif + +typedef struct { + N_uint32 low; + N_uint32 high; + } AA_largeInteger; + +void NAPI _OS_delay8253(N_uint32 microSeconds); +ibool NAPI _GA_haveCPUID(void); +uint NAPI _GA_getCPUIDFeatures(void); +void NAPI _GA_readTimeStamp(AA_largeInteger *time); +#define CPU_HaveRDTSC 0x00000010 + +/**************************************************************************** +REMARKS: +This function delays for the specified number of microseconds +****************************************************************************/ +void NAPI _OS_delay( + N_uint32 microSeconds) +{ + static ibool inited = false; + LZTimerObject tm; + + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + if (!inited) { + ZTimerInit(); + inited = true; + } + LZTimerOnExt(&tm); + while (LZTimerLapExt(&tm) < microSeconds) + ; + LZTimerOnExt(&tm); + } + else + _OS_delay8253(microSeconds); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aalinux.c b/board/MAI/bios_emulator/scitech/src/common/aalinux.c new file mode 100644 index 0000000..d3d468e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aalinux.c @@ -0,0 +1,94 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Linux operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timeval t; + gettimeofday(&t, NULL); + value->low = t.tv_sec*1000000 + t.tv_usec; + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aaos2.c b/board/MAI/bios_emulator/scitech/src/common/aaos2.c new file mode 100644 index 0000000..0ec8c9f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aaos2.c @@ -0,0 +1,124 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: OS/2 32-bit +* +* Description: OS specific Nucleus Graphics Architecture services for +* the OS/2 operating system environments. +* +****************************************************************************/ + +#include "pm_help.h" +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static HFILE hSDDHelp; +static ulong outLen; /* Must not cross 64Kb boundary! */ +static ulong result; /* Must not cross 64Kb boundary! */ +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +This function returns a pointer to the common graphics driver loaded in the +helper VxD. The memory for the VxD is shared between all processes via +the VxD, so that the VxD, 16-bit code and 32-bit code all see the same +state when accessing the graphics binary portable driver. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + /* Initialise the PM library and connect to our runtime DLL's */ + PM_init(); + + /* Open our helper device driver */ + if (DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0, + FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, + NULL)) + PM_fatalError("Unable to open SDDHELP$ helper device driver!"); + outLen = sizeof(result); + DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,PMHELP_GETSHAREDINFO, + NULL, 0, NULL, + &result, outLen, &outLen); + DosClose(hSDDHelp); + if (result) { + /* We have found the shared Nucleus packet. Because not all processes + * map to SDDPMI.DLL, we need to ensure that we connect to this + * DLL so that it gets mapped into our address space (that is + * where the shared Nucleus packet is located). Simply doing a + * DosLoadModule on it is enough for this. + */ + HMODULE hModSDDPMI; + char buf[80]; + DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"SDDPMI.DLL",&hModSDDPMI); + } + return (GA_sharedInfo*)result; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + DosTmrQueryTime((QWORD*)value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aaqnx.c b/board/MAI/bios_emulator/scitech/src/common/aaqnx.c new file mode 100644 index 0000000..13531be --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aaqnx.c @@ -0,0 +1,95 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: OS specific Nucleus Graphics Architecture services for +* the QNX operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timespec ts; + + clock_gettime(CLOCK_REALTIME, &ts); + value->low = (ts.tv_nsec / 1000 + ts.tv_sec * 1000000); + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aartt.c b/board/MAI/bios_emulator/scitech/src/common/aartt.c new file mode 100644 index 0000000..1a5a67a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aartt.c @@ -0,0 +1,89 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the RTTarget-32 operating system environments. +* +****************************************************************************/ + +#include "nucleus/graphics.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aasmx.c b/board/MAI/bios_emulator/scitech/src/common/aasmx.c new file mode 100644 index 0000000..163060f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aasmx.c @@ -0,0 +1,83 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: smx32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the smx32 platform -- no vxD support. +* +****************************************************************************/ + +#include "pmapi.h" +#include "nucleus/graphics.h" + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aavxd.c b/board/MAI/bios_emulator/scitech/src/common/aavxd.c new file mode 100644 index 0000000..221b02b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aavxd.c @@ -0,0 +1,90 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Win32 VxD +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Win32 VxD's. +* +****************************************************************************/ + +#include "sdd/sddhelp.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Return the internal shared info structure. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + static GA_sharedInfo shared = {0,-1}; + return &shared; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + } + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + VTD_Get_Real_Time(&value->high,&value->low); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aawin32.c b/board/MAI/bios_emulator/scitech/src/common/aawin32.c new file mode 100644 index 0000000..541df4a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aawin32.c @@ -0,0 +1,264 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Win32 operating system environments. +* +****************************************************************************/ + +#include "pm_help.h" +#include "pmapi.h" +#include +#include +#include +#define STRICT +#define WIN32_LEAN_AND_MEAN +#include + +/*------------------------- Global Variables ------------------------------*/ + +#if GA_MAX_DEVICES > 4 +#error GA_MAX_DEVICES has changed! +#endif + +static ibool haveRDTSC; +static GA_largeInteger countFreq; +static GA_loadDriver_t ORG_GA_loadDriver; +extern HANDLE _PM_hDevice; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +DESCRIPTION: +Get the current graphics driver imports from the VxD + +REMARKS: +This function returns a pointer to the common graphics driver loaded in the +helper VxD. The memory for the VxD is shared between all processes via +the VxD, so that the VxD, 16-bit code and 32-bit code all see the same +state when accessing the graphics binary portable driver. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD outBuf[2]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + PM_init(); + inBuf[0] = device; + if (DeviceIoControl(_PM_hDevice, PMHELP_GETSHAREDINFO32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) { + return (GA_sharedInfo*)outBuf[0]; + } + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the software stereo module by either calling +the Nucleus libraries directly, or calling into the VxD if we are running +on the shared Nucleus libraries loaded by the Windows VxD. +****************************************************************************/ +static ibool NAPI _GA_softStereoInit( + GA_devCtx *dc) +{ + if (_PM_hDevice) { + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)dc; + if (DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOINIT32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) { + return outBuf[0]; + } + } + return false; +} + +/**************************************************************************** +REMARKS: +This function turns on software stereo mode, either directly or via the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoOn(void) +{ + if (_PM_hDevice) { + DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOON32, NULL, 0, + NULL, 0, NULL, NULL); + } +} + +/**************************************************************************** +REMARKS: +This function schedules a software stereo mode page flip, either directly +or via the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoScheduleFlip( + N_uint32 leftAddr, + N_uint32 rightAddr) +{ + if (_PM_hDevice) { + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)leftAddr; + inBuf[1] = (ulong)rightAddr; + DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOFLIP32, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); + } +} + +/**************************************************************************** +REMARKS: +This function turns off software stereo mode, either directly or via the VxD. +****************************************************************************/ +static N_int32 NAPI _GA_softStereoGetFlipStatus(void) +{ + if (_PM_hDevice) { + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOFLIPSTATUS32, NULL, 0, + outBuf, sizeof(outBuf), &count, NULL)) { + return outBuf[0]; + } + } + return 0; +} + +/**************************************************************************** +REMARKS: +This function turns off software stereo mode, either directly or via the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoWaitTillFlipped(void) +{ + while (!_GA_softStereoGetFlipStatus()) + ; +} + +/**************************************************************************** +REMARKS: +This function turns off software stereo mode, either directly or via the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoOff(void) +{ + if (_PM_hDevice) { + DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOOFF32, NULL, 0, + NULL, 0, NULL, NULL); + } +} + +/**************************************************************************** +REMARKS: +This function disable the software stereo handler, either directly or via +the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoExit(void) +{ + if (_PM_hDevice) { + DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOEXIT32, NULL, 0, + NULL, 0, NULL, NULL); + } +} + +/**************************************************************************** +REMARKS: +We hook this function in here so that we can avoid the memory detect and +other destructive sequences in the drivers if we are loading the driver +from a Win32 application (our display drivers in contrast load them inside +the VxD directly, but the control panel applets use this function). +****************************************************************************/ +static GA_devCtx * NAPI _GA_loadDriver( + N_int32 deviceIndex, + N_int32 shared) +{ + GA_devCtx *dc; + DWORD inBuf[1]; + DWORD outBuf[1]; + N_int32 totalMemory = 0,oldIOPL; + + if (deviceIndex >= GA_MAX_DEVICES) + PM_fatalError("DeviceIndex too large in GA_loadDriver!"); + PM_init(); + inBuf[0] = deviceIndex; + if (DeviceIoControl(_PM_hDevice, PMHELP_GETMEMSIZE32, + inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), NULL, NULL)) + totalMemory = outBuf[0]; + if (totalMemory == 0) + totalMemory = 8192; + _GA_exports.GA_forceMemSize(totalMemory,shared); + oldIOPL = PM_setIOPL(3); + dc = ORG_GA_loadDriver(deviceIndex,shared); + PM_setIOPL(oldIOPL); + return dc; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + return true; + } + else if (QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq)) { + haveRDTSC = false; + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + QueryPerformanceCounter((LARGE_INTEGER*)value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/agplib.c b/board/MAI/bios_emulator/scitech/src/common/agplib.c new file mode 100644 index 0000000..476eedc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/agplib.c @@ -0,0 +1,219 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Any 32-bit protected mode environment +* +* Description: C module for the Graphics Accelerator Driver API. Uses +* the SciTech PM library for interfacing with DOS +* extender specific functions. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include "nucleus/agp.h" + +/*---------------------------- Global Variables ---------------------------*/ + +#ifndef DEBUG_AGP_DRIVER +static AGP_exports _AGP_exports; +static int loaded = false; +static PE_MODULE *hModBPD = NULL; + +static N_imports _N_imports = { + sizeof(N_imports), + _OS_delay, + }; + +static AGP_imports _AGP_imports = { + sizeof(AGP_imports), + }; +#endif + +#include "pmimp.h" + +/*----------------------------- Implementation ----------------------------*/ + +#define DLL_NAME "agp.bpd" + +#ifndef DEBUG_AGP_DRIVER +/**************************************************************************** +REMARKS: +Fatal error handler for non-exported GA_exports. +****************************************************************************/ +static void _AGP_fatalErrorHandler(void) +{ + PM_fatalError("Unsupported AGP export function called! Please upgrade your copy of AGP!\n"); +} + +/**************************************************************************** +PARAMETERS: +shared - True to load the driver into shared memory. + +REMARKS: +Loads the Nucleus binary portable DLL into memory and initilises it. +****************************************************************************/ +static ibool LoadDriver(void) +{ + AGP_initLibrary_t AGP_initLibrary; + AGP_exports *agpExp; + char filename[PM_MAX_PATH]; + char bpdpath[PM_MAX_PATH]; + int i,max; + ulong *p; + + /* Check if we have already loaded the driver */ + if (loaded) + return true; + PM_init(); + + /* Open the BPD file */ + if (!PM_findBPD(DLL_NAME,bpdpath)) + return false; + strcpy(filename,bpdpath); + strcat(filename,DLL_NAME); + if ((hModBPD = PE_loadLibrary(filename,false)) == NULL) + return false; + if ((AGP_initLibrary = (AGP_initLibrary_t)PE_getProcAddress(hModBPD,"_AGP_initLibrary")) == NULL) + return false; + bpdpath[strlen(bpdpath)-1] = 0; + if (strcmp(bpdpath,PM_getNucleusPath()) == 0) + strcpy(bpdpath,PM_getNucleusConfigPath()); + else { + PM_backslash(bpdpath); + strcat(bpdpath,"config"); + } + if ((agpExp = AGP_initLibrary(bpdpath,filename,GA_getSystemPMImports(),&_N_imports,&_AGP_imports)) == NULL) + PM_fatalError("AGP_initLibrary failed!\n"); + _AGP_exports.dwSize = sizeof(_AGP_exports); + max = sizeof(_AGP_exports)/sizeof(AGP_initLibrary_t); + for (i = 0,p = (ulong*)&_AGP_exports; i < max; i++) + *p++ = (ulong)_AGP_fatalErrorHandler; + memcpy(&_AGP_exports,agpExp,MIN(sizeof(_AGP_exports),agpExp->dwSize)); + loaded = true; + return true; +} + +/* The following are stub entry points that the application calls to + * initialise the Nucleus loader library, and we use this to load our + * driver DLL from disk and initialise the library using it. + */ + +/* {secret} */ +int NAPI AGP_status(void) +{ + if (!loaded) + return nDriverNotFound; + return _AGP_exports.AGP_status(); +} + +/* {secret} */ +const char * NAPI AGP_errorMsg( + N_int32 status) +{ + if (!loaded) + return "Unable to load Nucleus device driver!"; + return _AGP_exports.AGP_errorMsg(status); +} + +/* {secret} */ +AGP_devCtx * NAPI AGP_loadDriver(N_int32 deviceIndex) +{ + if (!LoadDriver()) + return NULL; + return _AGP_exports.AGP_loadDriver(deviceIndex); +} + +/* {secret} */ +void NAPI AGP_unloadDriver( + AGP_devCtx *dc) +{ + if (loaded) + _AGP_exports.AGP_unloadDriver(dc); +} + +/* {secret} */ +void NAPI AGP_getGlobalOptions( + AGP_globalOptions *options) +{ + if (LoadDriver()) + _AGP_exports.AGP_getGlobalOptions(options); +} + +/* {secret} */ +void NAPI AGP_setGlobalOptions( + AGP_globalOptions *options) +{ + if (LoadDriver()) + _AGP_exports.AGP_setGlobalOptions(options); +} + +/* {secret} */ +void NAPI AGP_saveGlobalOptions( + AGP_globalOptions *options) +{ + if (loaded) + _AGP_exports.AGP_saveGlobalOptions(options); +} +#endif + +/* {secret} */ +void NAPI _OS_delay8253(N_uint32 microSeconds); + +/**************************************************************************** +REMARKS: +This function delays for the specified number of microseconds +****************************************************************************/ +void NAPI _OS_delay( + N_uint32 microSeconds) +{ + static ibool inited = false; + static ibool haveRDTSC; + LZTimerObject tm; + + if (!inited) { +#ifndef __WIN32_VXD__ + /* This has been causing problems in VxD's for some reason, so for now */ + /* we avoid using it. */ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + ZTimerInit(); + haveRDTSC = true; + } + else +#endif + haveRDTSC = false; + inited = true; + } + if (haveRDTSC) { + LZTimerOnExt(&tm); + while (LZTimerLapExt(&tm) < microSeconds) + ; + LZTimerOnExt(&tm); + } + else + _OS_delay8253(microSeconds); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/center.c b/board/MAI/bios_emulator/scitech/src/common/center.c new file mode 100644 index 0000000..68e17c2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/center.c @@ -0,0 +1,122 @@ +/**************************************************************************** +* +* Display Doctor Windows Interface Code +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code is a proprietary trade secret of | +* |SciTech Software, Inc., located at 505 Wall Street, Chico, CA 95928 | +* |USA (www.scitechsoft.com). ANY UNAUTHORIZED POSSESSION, USE, | +* |VIEWING, COPYING, MODIFICATION OR DISSEMINATION OF THIS CODE IS | +* |STRICTLY PROHIBITED BY LAW. Unless you have current, express | +* |written authorization from SciTech to possess or use this code, you | +* |may be subject to civil and/or criminal penalties. | +* | | +* |If you received this code in error or you would like to report | +* |improper use, please immediately contact SciTech Software, Inc. at | +* |530-894-8400. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: C++ 3.0 +* Environment: Win16 +* +* Description: Dialog driven configuration program for UniVBE and +* WinDirect Professional products. +* +****************************************************************************/ + +#include "center.h" + +/*------------------------------ Implementation ---------------------------*/ + +void _EXPORT CenterWindow(HWND hWndCenter, HWND parent, BOOL repaint) +/**************************************************************************** +* +* Function: CenterWindow +* Parameters: hWndCenter - Window to center +* parent - Handle for parent window +* repaint - true if window should be re-painted +* +* Description: Centers the specified window within the bounds of the +* specified parent window. If the parent window is NULL, then +* we center it using the Desktop window. +* +****************************************************************************/ +{ + HWND hWndParent = (parent ? parent : GetDesktopWindow()); + RECT RectParent; + RECT RectCenter; + int CenterX,CenterY,Height,Width; + + GetWindowRect(hWndParent, &RectParent); + GetWindowRect(hWndCenter, &RectCenter); + + Width = (RectCenter.right - RectCenter.left); + Height = (RectCenter.bottom - RectCenter.top); + CenterX = ((RectParent.right - RectParent.left) - Width) / 2; + CenterY = ((RectParent.bottom - RectParent.top) - Height) / 2; + + if ((CenterX < 0) || (CenterY < 0)) { + /* The Center Window is smaller than the parent window. */ + if (hWndParent != GetDesktopWindow()) { + /* If the parent window is not the desktop use the desktop size. */ + CenterX = (GetSystemMetrics(SM_CXSCREEN) - Width) / 2; + CenterY = (GetSystemMetrics(SM_CYSCREEN) - Height) / 2; + } + CenterX = (CenterX < 0) ? 0: CenterX; + CenterY = (CenterY < 0) ? 0: CenterY; + } + else { + CenterX += RectParent.left; + CenterY += RectParent.top; + } + + /* Copy the values into RectCenter */ + RectCenter.left = CenterX; + RectCenter.right = CenterX + Width; + RectCenter.top = CenterY; + RectCenter.bottom = CenterY + Height; + + /* Move the window to the new location */ + MoveWindow(hWndCenter, RectCenter.left, RectCenter.top, + (RectCenter.right - RectCenter.left), + (RectCenter.bottom - RectCenter.top), repaint); +} + +void _EXPORT CenterLogo(HWND hWndLogo, HWND hWndParent, int CenterY) +/**************************************************************************** +* +* Function: CenterLogo +* Parameters: hWndLogo - Window to center +* hWndParent - Handle for parent window +* CenterY - Top coordinate for logo +* +* Description: Centers the specified window within the bounds of the +* specified parent window in the horizontal direction only. +* +****************************************************************************/ +{ + RECT RectParent; + RECT RectCenter; + int CenterX,Height,Width; + + GetWindowRect(hWndParent, &RectParent); + GetWindowRect(hWndLogo, &RectCenter); + Width = (RectCenter.right - RectCenter.left); + Height = (RectCenter.bottom - RectCenter.top); + CenterX = ((RectParent.right - RectParent.left) - Width) / 2; + + /* Copy the values into RectCenter */ + RectCenter.left = CenterX; + RectCenter.right = CenterX + Width; + RectCenter.top = CenterY; + RectCenter.bottom = CenterY + Height; + + /* Move the window to the new location */ + MoveWindow(hWndLogo, RectCenter.left, RectCenter.top, + (RectCenter.right - RectCenter.left), + (RectCenter.bottom - RectCenter.top), false); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/cmdline.c b/board/MAI/bios_emulator/scitech/src/common/cmdline.c new file mode 100644 index 0000000..531e5e1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/cmdline.c @@ -0,0 +1,428 @@ +/**************************************************************************** +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: This module contains code to parse the command line, +* extracting options and parameters in standard System V +* style. +* +****************************************************************************/ + +#include +#include +#include +#include "cmdline.h" + +/*------------------------- Global variables ------------------------------*/ + +int nextargv = 1; /* Index into argv array */ +char *nextchar = NULL; /* Pointer to next character */ + +/*-------------------------- Implementation -------------------------------*/ + +#define IS_SWITCH_CHAR(c) ((c) == '-') +#define IS_NOT_SWITCH_CHAR(c) ((c) != '-') + +/**************************************************************************** +DESCRIPTION: +Parse the command line for specific options + +HEADER: +cmdline.h + +PARAMETERS: +argc - Value passed to program through argc variable +argv - Pointer to the argv array passed to the program +format - A string representing the expected format of the command line +argument - Pointer to optional argument on command line + +RETURNS: +Character code representing the next option parsed from the command line by +getcmdopt. Returns ALLDONE (-1) when there are no more parameters to be parsed +on the command line, PARAMETER (-2) when the argument being parsed is a +parameter and not an option switch and lastly INVALID (-3) if an error +occured while parsing the command line. + +REMARKS: +Function to parse the command line option switches in UNIX System V style. +When getcmdopt is called, it returns the character code of the next valid +option that is parsed from the command line as specified by the Format +string. The format string should be in the following form: + + "abcd:e:f:" + +where a,b and c represent single switch style options and the character +code returned by getcmdopt is the only value returned. Also d, e and f +represent options that expect arguments immediately after them on the +command line. The argument that follows the option on the command line is +returned via a reference in the pointer argument. Thus a valid command line +for this format string might be: + + myprogram -adlines -b -f format infile outfile + +where a and b will be returned as single character options with no argument, +while d is returned with the argument lines and f is returned with the +argument format. + +When getcmdopt returns with PARAMETER (we attempted to parse a paramter, not +an option), the global variable NextArgv will hold an index in the argv +array to the argument on the command line AFTER the options, ie in the +above example the string 'infile'. If the parameter is successfully used, +NextArgv should be incremented and getcmdopt can be called again to parse any +more options. Thus you can also have options interspersed throught the +command line. eg: + + myprogram -adlines infile -b outfile -f format + +can be made to be a valid form of the above command line. +****************************************************************************/ +int getcmdopt( + int argc, + char **argv, + char *format, + char **argument) +{ + char ch; + char *formatchar; + + if (argc > nextargv) { + if (nextchar == NULL) { + nextchar = argv[nextargv]; /* Index next argument */ + if (nextchar == NULL) { + nextargv++; + return ALLDONE; /* No more options */ + } + if (IS_NOT_SWITCH_CHAR(*nextchar)) { + nextchar = NULL; + return PARAMETER; /* We have a parameter */ + } + nextchar++; /* Move past switch operator */ + if (IS_SWITCH_CHAR(*nextchar)) { + nextchar = NULL; + return INVALID; /* Ignore rest of line */ + } + } + if ((ch = *(nextchar++)) == 0) { + nextchar = NULL; + return INVALID; /* No options on line */ + } + + if (ch == ':' || (formatchar = strchr(format, ch)) == NULL) + return INVALID; + + if (*(++formatchar) == ':') { /* Expect an argument after option */ + nextargv++; + if (*nextchar == 0) { + if (argc <= nextargv) + return INVALID; + nextchar = argv[nextargv++]; + } + *argument = nextchar; + nextchar = NULL; + } + else { /* We have a switch style option */ + if (*nextchar == 0) { + nextargv++; + nextchar = NULL; + } + *argument = NULL; + } + return ch; /* return the option specifier */ + } + nextchar = NULL; + nextargv++; + return ALLDONE; /* no arguments on command line */ +} + +/**************************************************************************** +PARAMETERS: +optarr - Description for the option we are parsing +argument - String to parse + +RETURNS: +INVALID on error, ALLDONE on success. + +REMARKS: +Parses the argument string depending on the type of argument that is +expected, filling in the argument for that option. Note that to parse a +string, we simply return a pointer to argument. +****************************************************************************/ +static int parse_option( + Option *optarr, + char *argument) +{ + int num_read; + + switch ((int)(optarr->type)) { + case OPT_INTEGER: + num_read = sscanf(argument,"%d",(int*)optarr->arg); + break; + case OPT_HEX: + num_read = sscanf(argument,"%x",(int*)optarr->arg); + break; + case OPT_OCTAL: + num_read = sscanf(argument,"%o",(int*)optarr->arg); + break; + case OPT_UNSIGNED: + num_read = sscanf(argument,"%u",(uint*)optarr->arg); + break; + case OPT_LINTEGER: + num_read = sscanf(argument,"%ld",(long*)optarr->arg); + break; + case OPT_LHEX: + num_read = sscanf(argument,"%lx",(long*)optarr->arg); + break; + case OPT_LOCTAL: + num_read = sscanf(argument,"%lo",(long*)optarr->arg); + break; + case OPT_LUNSIGNED: + num_read = sscanf(argument,"%lu",(ulong*)optarr->arg); + break; + case OPT_FLOAT: + num_read = sscanf(argument,"%f",(float*)optarr->arg); + break; + case OPT_DOUBLE: + num_read = sscanf(argument,"%lf",(double*)optarr->arg); + break; + case OPT_LDOUBLE: + num_read = sscanf(argument,"%Lf",(long double*)optarr->arg); + break; + case OPT_STRING: + num_read = 1; /* This always works */ + *((char**)optarr->arg) = argument; + break; + default: + return INVALID; + } + + if (num_read == 0) + return INVALID; + else + return ALLDONE; +} + +/**************************************************************************** +HEADER: +cmdline.h + +PARAMETERS: +argc - Number of arguments on command line +argv - Array of command line arguments +num_opt - Number of options in option array +optarr - Array to specify how to parse the command line +do_param - Routine to handle a command line parameter + +RETURNS: +ALLDONE, INVALID or HELP + +REMARKS: +Function to parse the command line according to a table of options. This +routine calls getcmdopt above to parse each individual option and attempts +to parse each option into a variable of the specified type. The routine +can parse integers and long integers in either decimal, octal, hexadecimal +notation, unsigned integers and unsigned longs, strings and option switches. +Option switches are simply boolean variables that get turned on if the +switch was parsed. + +Parameters are extracted from the command line by calling a user supplied +routine do_param() to handle each parameter as it is encountered. The +routine do_param() should accept a pointer to the parameter on the command +line and an integer representing how many parameters have been encountered +(ie: 1 if this is the first parameter, 10 if it is the 10th etc), and return +ALLDONE upon successfully parsing it or INVALID if the parameter was invalid. + +We return either ALLDONE if all the options were successfully parsed, +INVALID if an invalid option was encountered or HELP if any of -h, -H or +-? were present on the command line. +****************************************************************************/ +int getargs( + int argc, + char *argv[], + int num_opt, + Option optarr[], + int (*do_param)( + char *param, + int num)) +{ + int i,opt; + char *argument; + int param_num = 1; + char cmdstr[MAXARG*2 + 4]; + + /* Build the command string from the array of options */ + + strcpy(cmdstr,"hH?"); + for (i = 0,opt = 3; i < num_opt; i++,opt++) { + cmdstr[opt] = optarr[i].opt; + if (optarr[i].type != OPT_SWITCH) { + cmdstr[++opt] = ':'; + } + } + cmdstr[opt] = '\0'; + + for (;;) { + opt = getcmdopt(argc,argv,cmdstr,&argument); + switch (opt) { + case 'H': + case 'h': + case '?': + return HELP; + case ALLDONE: + return ALLDONE; + case INVALID: + return INVALID; + case PARAMETER: + if (do_param == NULL) + return INVALID; + if (do_param(argv[nextargv],param_num) == INVALID) + return INVALID; + nextargv++; + param_num++; + break; + default: + + /* Search for the option in the option array. We are + * guaranteed to find it. + */ + + for (i = 0; i < num_opt; i++) { + if (optarr[i].opt == opt) + break; + } + if (optarr[i].type == OPT_SWITCH) + *((ibool*)optarr[i].arg) = true; + else { + if (parse_option(&optarr[i],argument) == INVALID) + return INVALID; + } + break; + } + } +} + +/**************************************************************************** +HEADER: +cmdline.h + +PARAMETERS: +num_opt - Number of options in the table +optarr - Table of option descriptions + +REMARKS: +Prints the description of each option in a standard format to the standard +output device. The description for each option is obtained from the table +of options. +****************************************************************************/ +void print_desc( + int num_opt, + Option optarr[]) +{ + int i; + + for (i = 0; i < num_opt; i++) { + if (optarr[i].type == OPT_SWITCH) + printf(" -%c %s\n",optarr[i].opt,optarr[i].desc); + else + printf(" -%c %s\n",optarr[i].opt,optarr[i].desc); + } +} + +/**************************************************************************** +HEADER: +cmdline.h + +PARAMETERS: +moduleName - Module name for program +cmdLine - Command line to parse +pargc - Pointer to 'argc' parameter +pargv - Pointer to 'argv' parameter +maxArgc - Maximum argv array index + +REMARKS: +Parses a command line from a single string into the C style 'argc' and +'argv' format. Most useful for Windows programs where the command line +is passed in verbatim. +****************************************************************************/ +int parse_commandline( + char *moduleName, + char *cmdLine, + int *pargc, + char *argv[], + int maxArgv) +{ + static char str[512]; + static char filename[260]; + char *prevWord = NULL; + ibool inQuote = FALSE; + ibool noStrip = FALSE; + int argc; + + argc = 0; + strcpy(filename,moduleName); + argv[argc++] = filename; + cmdLine = strncpy(str, cmdLine, sizeof(str)-1); + while (*cmdLine) { + switch (*cmdLine) { + case '"' : + if (prevWord != NULL) { + if (inQuote) { + if (!noStrip) + *cmdLine = '\0'; + argv [argc++] = prevWord; + prevWord = NULL; + } + else + noStrip = TRUE; + } + inQuote = !inQuote; + break; + case ' ' : + case '\t' : + if (!inQuote) { + if (prevWord != NULL) { + *cmdLine = '\0'; + argv [argc++] = prevWord; + prevWord = NULL; + noStrip = FALSE; + } + } + break; + default : + if (prevWord == NULL) + prevWord = cmdLine; + break; + } + if (argc >= maxArgv - 1) + break; + cmdLine++; + } + + if ((prevWord != NULL || (inQuote && prevWord != NULL)) && argc < maxArgv - 1) { + *cmdLine = '\0'; + argv [argc++] = prevWord; + } + argv[argc] = NULL; + + /* Return updated parameters */ + return (*pargc = argc); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gabeos.c b/board/MAI/bios_emulator/scitech/src/common/gabeos.c new file mode 100644 index 0000000..a934bd1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gabeos.c @@ -0,0 +1,146 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Linux operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + /* TODO: We may very well want to provide a system shared library */ + /* that eports the PM functions required by the Nucleus library */ + /* for BeOS here. That will eliminate fatal errors loading new */ + /* drivers on BeOS! */ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timeval t; + gettimeofday(&t, NULL); + value->low = t.tv_sec*1000000 + t.tv_usec; + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gados.c b/board/MAI/bios_emulator/scitech/src/common/gados.c new file mode 100644 index 0000000..d2be776 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gados.c @@ -0,0 +1,135 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: MSDOS +* +* Description: OS specific Nucleus Graphics Architecture services for +* the MSDOS operating system. +* +****************************************************************************/ + +#include "pm_help.h" +#include "pmapi.h" +#include +#include +#include + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +Nothing to do here for DOS. Basically since DOS has no system wide shared +library mechanism we are essentially screwed if the binary API changes. +By default for 32-bit DOS apps the local Nucleus drivers should always be +used in preference to the system wide Nucleus drivers. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#if !defined(TEST_HARNESS) && !defined(VBETEST) +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the DOS +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/galib.c b/board/MAI/bios_emulator/scitech/src/common/galib.c new file mode 100644 index 0000000..f2eacc3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/galib.c @@ -0,0 +1,268 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Any 32-bit protected mode environment +* +* Description: C module for the Graphics Accelerator Driver API. Uses +* the SciTech PM library for interfacing with DOS +* extender specific functions. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +#include "sdd/sddhelp.h" +#else +#include +#include +#endif + +/*---------------------------- Global Variables ---------------------------*/ + +#ifndef TEST_HARNESS +GA_exports _VARAPI __GA_exports; +static int loaded = false; +static PE_MODULE *hModBPD = NULL; + +static N_imports _N_imports = { + sizeof(N_imports), + _OS_delay, + }; + +static GA_imports _GA_imports = { + sizeof(GA_imports), + GA_getSharedInfo, + GA_TimerInit, + GA_TimerRead, + GA_TimerDifference, + }; +#endif + +/*----------------------------- Implementation ----------------------------*/ + +#define DLL_NAME "graphics.bpd" + +/**************************************************************************** +REMARKS: +This function is no longer used but we must implement it and return NULL +for compatibility with older binary drivers. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + return NULL; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Fatal error handler for non-exported GA_exports. +****************************************************************************/ +static void _GA_fatalErrorHandler(void) +{ + PM_fatalError("Unsupported Nucleus export function called! Please upgrade your copy of Nucleus!\n"); +} + +/**************************************************************************** +PARAMETERS: +shared - True to load the driver into shared memory. + +REMARKS: +Loads the Nucleus binary portable DLL into memory and initilises it. +****************************************************************************/ +static ibool LoadDriver( + ibool shared) +{ + GA_initLibrary_t GA_initLibrary; + GA_exports *gaExp; + char filename[PM_MAX_PATH]; + char bpdpath[PM_MAX_PATH]; + int i,max; + ulong *p; + + /* Check if we have already loaded the driver */ + if (loaded) + return true; + PM_init(); + + /* First try to see if we can find the system wide shared exports + * if they are available. Under OS/2 this connects to our global + * shared Nucleus loader in SDDPMI.DLL. + */ + __GA_exports.dwSize = sizeof(__GA_exports); + if (GA_getSharedExports(&__GA_exports,shared)) + return loaded = true; + + /* Open the BPD file */ + if (!PM_findBPD(DLL_NAME,bpdpath)) + return false; + strcpy(filename,bpdpath); + strcat(filename,DLL_NAME); + if ((hModBPD = PE_loadLibrary(filename,shared)) == NULL) + return false; + if ((GA_initLibrary = (GA_initLibrary_t)PE_getProcAddress(hModBPD,"_GA_initLibrary")) == NULL) + return false; + bpdpath[strlen(bpdpath)-1] = 0; + if (strcmp(bpdpath,PM_getNucleusPath()) == 0) + strcpy(bpdpath,PM_getNucleusConfigPath()); + else { + PM_backslash(bpdpath); + strcat(bpdpath,"config"); + } + if ((gaExp = GA_initLibrary(shared,bpdpath,filename,GA_getSystemPMImports(),&_N_imports,&_GA_imports)) == NULL) + PM_fatalError("GA_initLibrary failed!\n"); + + /* Initialize all default imports to point to fatal error handler + * for upwards compatibility, and copy the exported functions. + */ + max = sizeof(__GA_exports)/sizeof(GA_initLibrary_t); + for (i = 0,p = (ulong*)&__GA_exports; i < max; i++) + *p++ = (ulong)_GA_fatalErrorHandler; + memcpy(&__GA_exports,gaExp,MIN(sizeof(__GA_exports),gaExp->dwSize)); + loaded = true; + return true; +} + +/* The following are stub entry points that the application calls to + * initialise the Nucleus loader library, and we use this to load our + * driver DLL from disk and initialise the library using it. + */ + +/* {secret} */ +int NAPI GA_status(void) +{ + if (!loaded) + return nDriverNotFound; + return __GA_exports.GA_status(); +} + +/* {secret} */ +const char * NAPI GA_errorMsg( + N_int32 status) +{ + if (!loaded) + return "Unable to load Nucleus device driver!"; + return __GA_exports.GA_errorMsg(status); +} + +/* {secret} */ +int NAPI GA_getDaysLeft(N_int32 shared) +{ + if (!LoadDriver(shared)) + return -1; + return __GA_exports.GA_getDaysLeft(shared); +} + +/* {secret} */ +int NAPI GA_registerLicense(uchar *license,N_int32 shared) +{ + if (!LoadDriver(shared)) + return 0; + return __GA_exports.GA_registerLicense(license,shared); +} + +/* {secret} */ +ibool NAPI GA_loadInGUI(N_int32 shared) +{ + if (!LoadDriver(shared)) + return false; + return __GA_exports.GA_loadInGUI(shared); +} + +/* {secret} */ +int NAPI GA_enumerateDevices(N_int32 shared) +{ + if (!LoadDriver(shared)) + return 0; + return __GA_exports.GA_enumerateDevices(shared); +} + +/* {secret} */ +GA_devCtx * NAPI GA_loadDriver(N_int32 deviceIndex,N_int32 shared) +{ + if (!LoadDriver(shared)) + return NULL; + return __GA_exports.GA_loadDriver(deviceIndex,shared); +} + +/* {secret} */ +void NAPI GA_getGlobalOptions( + GA_globalOptions *options, + ibool shared) +{ + if (LoadDriver(shared)) + __GA_exports.GA_getGlobalOptions(options,shared); +} + +/* {secret} */ +PE_MODULE * NAPI GA_loadLibrary( + const char *szBPDName, + ulong *size, + ibool shared) +{ + if (!LoadDriver(shared)) + return NULL; + return __GA_exports.GA_loadLibrary(szBPDName,size,shared); +} + +/* {secret} */ +GA_devCtx * NAPI GA_getCurrentDriver( + N_int32 deviceIndex) +{ + /* Bail for older drivers that didn't export this function! */ + if (!__GA_exports.GA_getCurrentDriver) + return NULL; + return __GA_exports.GA_getCurrentDriver(deviceIndex); +} + +/* {secret} */ +REF2D_driver * NAPI GA_getCurrentRef2d( + N_int32 deviceIndex) +{ + /* Bail for older drivers that didn't export this function! */ + if (!__GA_exports.GA_getCurrentRef2d) + return NULL; + return __GA_exports.GA_getCurrentRef2d(deviceIndex); +} + +/* {secret} */ +int NAPI GA_isOEMVersion(ibool shared) +{ + if (!LoadDriver(shared)) + return 0; + return __GA_exports.GA_isOEMVersion(shared); +} + +/* {secret} */ +N_uint32 * NAPI GA_getLicensedDevices(ibool shared) +{ + if (!LoadDriver(shared)) + return 0; + return __GA_exports.GA_getLicensedDevices(shared); +} +#endif diff --git a/board/MAI/bios_emulator/scitech/src/common/galinux.c b/board/MAI/bios_emulator/scitech/src/common/galinux.c new file mode 100644 index 0000000..47e4e85 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/galinux.c @@ -0,0 +1,148 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Linux operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + /* TODO: We may very well want to provide a system shared library */ + /* that eports the PM functions required by the Nucleus library */ + /* for Linux here. That will eliminate fatal errors loading new */ + /* drivers on Linux! */ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timeval t; + gettimeofday(&t, NULL); + value->low = t.tv_sec*1000000 + t.tv_usec; + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gantdrv.c b/board/MAI/bios_emulator/scitech/src/common/gantdrv.c new file mode 100644 index 0000000..050f737 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gantdrv.c @@ -0,0 +1,136 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: NT device driver +* +* Description: OS specific Nucleus Graphics Architecture services for +* the NT device drivers. +* +****************************************************************************/ + +#include "sdd/sddhelp.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +Nothing special for this OS. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + } + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + KeQuerySystemTime((LARGE_INTEGER*)value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gaos2.c b/board/MAI/bios_emulator/scitech/src/common/gaos2.c new file mode 100644 index 0000000..26e6503 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gaos2.c @@ -0,0 +1,248 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: OS/2 32-bit +* +* Description: OS specific Nucleus Graphics Architecture services for +* the OS/2 operating system environments. +* +****************************************************************************/ + +#include "pm_help.h" +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include + +/*--------------------------- Global variables ----------------------------*/ + +static ibool haveRDTSC = false; +static ulong parms[3]; /* Must not cross 64Kb boundary! */ +static ulong result[4]; /* Must not cross 64Kb boundary! */ + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +func - Helper device driver function to call + +RETURNS: +First return value from the device driver in parmsOut[0] + +REMARKS: +Function to open our helper device driver, call it and close the file +handle. Note that we have to open the device driver for every call because +of two problems: + + 1. We cannot open a single file handle in a DLL that is shared amongst + programs, since every process must have it's own open file handle. + + 2. For some reason there appears to be a limit of about 12 open file + handles on a device driver in the system. Hence when we open more + than about 12 file handles things start to go very strange. + +Hence we simply open the file handle every time that we need to call the +device driver to work around these problems. +****************************************************************************/ +static ulong CallSDDHelp( + int func) +{ + static ulong inLen; /* Must not cross 64Kb boundary! */ + static ulong outLen; /* Must not cross 64Kb boundary! */ + HFILE hSDDHelp; + + /* If this code in here fails, we are screwed! Many of our drivers + * use this code and don't have a C library, so we simply assume we + * can't fail here. + */ + DosOpen(PMHELP_NAME,&hSDDHelp,&result[0],0,0, + FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, + NULL); + DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,func, + &parms, inLen = sizeof(parms), &inLen, + &result, outLen = sizeof(result), &outLen); + DosClose(hSDDHelp); + return result[0]; +} + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +For OS/2 we don't need to do anything special because Nucleus is always +loaded via the shared SDDPMI driver when SDD is loaded so we don't need +a system wide PM library imports function. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +PARAMETERS: +gaExp - Place to store the exported functions +shared - True if connecting to the shared, global Nucleus driver + +REMARKS: +For OS/2 if SDD is loaded we *always* connect to the shared Nucleus functions +contained within the SDDPMI driver. This allows the Nucleus functions contained +within this driver to be utilised by all Nucleus apps in the system and +maintains a consistent state between versions. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + /* In test harness mode, we need to load a local copy of Nucleus */ +#if !defined (TEST_HARNESS) || defined (DEBUG_SDDPMI) + HMODULE hModSDDPMI; + char buf[80]; + GA_exports *exp; + + /* Initialise the PM library and connect to our runtime DLL's */ + PM_init(); + if (CallSDDHelp(PMHELP_GETSHAREDEXP) != 0) { + /* We have found the shared Nucleus exports. Because not all processes + * map to SDDPMI.DLL, we need to ensure that we connect to this + * DLL so that it gets mapped into our address space (that is + * where the shared Nucleus loader code is located). Simply doing a + * DosLoadModule on it is enough for this. + */ + DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"SDDPMI.DLL",&hModSDDPMI); + exp = (GA_exports*)result[0]; + memcpy(gaExp,exp,MIN(gaExp->dwSize,exp->dwSize)); + return true; + } +#endif + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + DosTmrQueryTime((QWORD*)value); +} + +/**************************************************************************** +REMARKS: +On OS/2, we need special memory allocation functions if we build SDDPMI in +test harness mode. But if we build GATest etc. in test mode, we want to use +the normal C runtime functions, so route them back here. +****************************************************************************/ + +#if defined (TEST_HARNESS) && !defined (DEBUG_SDDPMI) + +/* Undefine these macros first or we'll recurse to hell! */ +#undef malloc +#undef calloc +#undef realloc +#undef free + +void *SDDPMI_malloc(size_t size) { + return malloc(size); +} + +void *SDDPMI_calloc(size_t num, size_t size) { + return calloc(num, size); +} + +void SDDPMI_free(void *ptr) { + free(ptr); +} + +void *SDDPMI_realloc(void *ptr, size_t size) { + return realloc(ptr, size); +} + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/common/gaqnx.c b/board/MAI/bios_emulator/scitech/src/common/gaqnx.c new file mode 100644 index 0000000..525d662 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gaqnx.c @@ -0,0 +1,149 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: OS specific Nucleus Graphics Architecture services for +* the QNX operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + /* TODO: We may very well want to provide a system shared library */ + /* that eports the PM functions required by the Nucleus library */ + /* for QNX here. That will eliminate fatal errors loading new */ + /* drivers on QNX! */ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timespec ts; + + clock_gettime(CLOCK_REALTIME, &ts); + value->low = (ts.tv_nsec / 1000 + ts.tv_sec * 1000000); + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gartt.c b/board/MAI/bios_emulator/scitech/src/common/gartt.c new file mode 100644 index 0000000..3a41f59 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gartt.c @@ -0,0 +1,139 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the RTTarget-32 operating system environments. +* +****************************************************************************/ + +#include "nucleus/graphics.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gasmx.c b/board/MAI/bios_emulator/scitech/src/common/gasmx.c new file mode 100644 index 0000000..ae31941 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gasmx.c @@ -0,0 +1,133 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: smx32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the smx32 platform -- no vxD support. +* +****************************************************************************/ + +#include "pmapi.h" +#include "nucleus/graphics.h" + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gavxd.c b/board/MAI/bios_emulator/scitech/src/common/gavxd.c new file mode 100644 index 0000000..fc8ba8d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gavxd.c @@ -0,0 +1,136 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Win32 VxD +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Win32 VxD's. +* +****************************************************************************/ + +#include "sdd/sddhelp.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +Nothing special for this OS. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + } + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + VTD_Get_Real_Time(&value->high,&value->low); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gawin32.c b/board/MAI/bios_emulator/scitech/src/common/gawin32.c new file mode 100644 index 0000000..6944334 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gawin32.c @@ -0,0 +1,255 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Win32 operating system environments. +* +****************************************************************************/ + +#include "pm_help.h" +#include "pmapi.h" +#include +#include +#include +#define STRICT +#define WIN32_LEAN_AND_MEAN +#include + +/*------------------------- Global Variables ------------------------------*/ + +#define DLL_NAME "nga_w32.dll" + +extern HANDLE _PM_hDevice; +static HMODULE hModDLL = NULL; +static ibool useRing0Driver = false; +static ibool haveRDTSC; +static GA_largeInteger countFreq; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Loads the shared "nga_w32.dll" library from disk and connects to it. This +library is *always* located in the same directory as the Nucleus +graphics.bpd file. +****************************************************************************/ +static ibool LoadSharedDLL(void) +{ + char filename[PM_MAX_PATH]; + char bpdpath[PM_MAX_PATH]; + + /* Check if we have already loaded the DLL */ + if (hModDLL) + return true; + PM_init(); + + /* Open the DLL file */ + if (!PM_findBPD(DLL_NAME,bpdpath)) + return false; + strcpy(filename,bpdpath); + strcat(filename,DLL_NAME); + if ((hModDLL = LoadLibrary(filename)) == NULL) + return false; + return true; +} + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. + +Note that for Win32 we also call into the loaded PMHELP device driver +as necessary to change the local Nucleus path for system wide Nucleus +drivers. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + DWORD inBuf[1]; + DWORD outBuf[1],outCnt; + + PM_setLocalBPDPath(path); + if (_PM_hDevice != INVALID_HANDLE_VALUE) { + inBuf[0] = (DWORD)path; + DeviceIoControl(_PM_hDevice, PMHELP_GASETLOCALPATH32, + inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &outCnt, NULL); + } +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + PM_imports * pmImp; + PM_imports * (NAPIP _GA_getSystemPMImports)(void); + + if (LoadSharedDLL()) { + /* Note that Visual C++ build DLL's with only a single underscore in front + * of the exported name while Watcom C provides two of them. We check for + * both to allow working with either compiled DLL. + */ + if ((_GA_getSystemPMImports = (void*)GetProcAddress(hModDLL,"_GA_getSystemPMImports")) != NULL) { + if ((_GA_getSystemPMImports = (void*)GetProcAddress(hModDLL,"__GA_getSystemPMImports")) != NULL) { + pmImp = _GA_getSystemPMImports(); + memcpy(&_PM_imports,pmImp,MIN(_PM_imports.dwSize,pmImp->dwSize)); + return pmImp; + } + } + } + return &_PM_imports; +} + +/**************************************************************************** +PARAMETERS: +gaExp - Place to store the exported functions +shared - True if connecting to the shared, global Nucleus driver + +REMARKS: +For Win32 if we are connecting to the shared, global Nucleus driver (loaded +at ring 0) then we need to load a special nga_w32.dll library which contains +thunks to call down into the Ring 0 device driver as necessary. If we are +connecting to the application local Nucleus drivers (ie: Nucleus on DirectDraw +emulation layer) then we do nothing here. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + GA_exports * exp; + GA_exports * (NAPIP _GA_getSystemGAExports)(void); + + useRing0Driver = false; + if (shared) { + if (!LoadSharedDLL()) + PM_fatalError("Unable to load " DLL_NAME "!"); + if ((_GA_getSystemGAExports = (void*)GetProcAddress(hModDLL,"_GA_getSystemGAExports")) == NULL) + if ((_GA_getSystemGAExports = (void*)GetProcAddress(hModDLL,"__GA_getSystemGAExports")) == NULL) + PM_fatalError("Unable to load " DLL_NAME "!"); + exp = _GA_getSystemGAExports(); + memcpy(gaExp,exp,MIN(gaExp->dwSize,exp->dwSize)); + useRing0Driver = true; + return true; + } + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + static ibool (NAPIP _GA_queryFunctions)(GA_devCtx *dc,N_uint32 id,void _FAR_ *funcs) = NULL; + + if (useRing0Driver) { + /* Call the version in nga_w32.dll if it is loaded */ + if (!_GA_queryFunctions) { + if ((_GA_queryFunctions = (void*)GetProcAddress(hModDLL,"_GA_queryFunctions")) == NULL) + if ((_GA_queryFunctions = (void*)GetProcAddress(hModDLL,"__GA_queryFunctions")) == NULL) + PM_fatalError("Unable to get exports from " DLL_NAME "!"); + } + return _GA_queryFunctions(dc,id,funcs); + } + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + static ibool (NAPIP _REF2D_queryFunctions)(REF2D_driver *ref2d,N_uint32 id,void _FAR_ *funcs) = NULL; + + if (useRing0Driver) { + /* Call the version in nga_w32.dll if it is loaded */ + if (!_REF2D_queryFunctions) { + if ((_REF2D_queryFunctions = (void*)GetProcAddress(hModDLL,"_REF2D_queryFunctions")) == NULL) + if ((_REF2D_queryFunctions = (void*)GetProcAddress(hModDLL,"__REF2D_queryFunctions")) == NULL) + PM_fatalError("Unable to get exports from " DLL_NAME "!"); + } + return _REF2D_queryFunctions(ref2d,id,funcs); + } + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + return true; + } + else if (QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq)) { + haveRDTSC = false; + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + QueryPerformanceCounter((LARGE_INTEGER*)value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c b/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c new file mode 100644 index 0000000..1d547e9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c @@ -0,0 +1,436 @@ +/**************************************************************************** +* +* VESA Generalized Timing Formula (GTF) +* Version 1.1 +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Developed by: SciTech Software, Inc. +* +* Language: ANSI C +* Environment: Any. +* +* Description: C module for generating GTF compatible timings given a set +* of input requirements. Translated from the original GTF +* 1.14 spreadsheet definition. +* +* Compile with #define TESTING to build a command line test +* program. +* +* NOTE: The code in here has been written for clarity and +* to follow the original GTF spec as closely as +* possible. +* +****************************************************************************/ + +#include "gtf.h" +#ifndef __WIN32_VXD__ +#include +#include +#include +#include +#include +#endif + +/*------------------------- Global Variables ------------------------------*/ + +static GTF_constants GC = { + 1.8, /* Margin size as percentage of display */ + 8, /* Character cell granularity */ + 1, /* Minimum front porch in lines/chars */ + 3, /* Width of V sync in lines */ + 8, /* Width of H sync as percent of total */ + 550, /* Minimum vertical sync + back porch (us) */ + 600, /* Blanking formula gradient */ + 40, /* Blanking formula offset */ + 128, /* Blanking formula scaling factor */ + 20, /* Blanking formula scaling factor weight */ + }; + +/*-------------------------- Implementation -------------------------------*/ + +#ifdef __WIN32_VXD__ +/* These functions are not supported in a VxD, so we stub them out so this + * module will at least compile. Calling the functions in here will do + * something wierd! + */ +double sqrt(double x) +{ return x; } + +double floor(double x) +{ return x; } + +double pow(double x,double y) +{ return x*y; } +#endif + +static double round(double v) +{ + return floor(v + 0.5); +} + +static void GetInternalConstants(GTF_constants *c) +/**************************************************************************** +* +* Function: GetInternalConstants +* Parameters: c - Place to store the internal constants +* +* Description: Calculates the rounded, internal set of GTF constants. +* These constants are different to the real GTF constants +* that can be set up for the monitor. The calculations to +* get these real constants are defined in the 'Work Area' +* after the constants are defined in the Excel spreadsheet. +* +****************************************************************************/ +{ + c->margin = GC.margin; + c->cellGran = round(GC.cellGran); + c->minPorch = round(GC.minPorch); + c->vSyncRqd = round(GC.vSyncRqd); + c->hSync = GC.hSync; + c->minVSyncBP = GC.minVSyncBP; + if (GC.k == 0) + c->k = 0.001; + else + c->k = GC.k; + c->m = (c->k / 256) * GC.m; + c->c = (GC.c - GC.j) * (c->k / 256) + GC.j; + c->j = GC.j; +} + +void GTF_calcTimings(double hPixels,double vLines,double freq, + int type,ibool wantMargins,ibool wantInterlace,GTF_timings *t) +/**************************************************************************** +* +* Function: GTF_calcTimings +* Parameters: hPixels - X resolution +* vLines - Y resolution +* freq - Frequency (Hz, KHz or MHz depending on type) +* type - 1 - vertical, 2 - horizontal, 3 - dot clock +* margins - True if margins should be generated +* interlace - True if interlaced timings to be generated +* t - Place to store the resulting timings +* +* Description: Calculates a set of GTF timing parameters given a specified +* resolution and vertical frequency. The horizontal frequency +* and dot clock will be automatically generated by this +* routines. +* +* For interlaced modes the CRTC parameters are calculated for +* a single field, so will be half what would be used in +* a non-interlaced mode. +* +****************************************************************************/ +{ + double interlace,vFieldRate,hPeriod; + double topMarginLines,botMarginLines; + double leftMarginPixels,rightMarginPixels; + double hPeriodEst,vSyncBP,vBackPorch; + double vTotalLines,vFieldRateEst; + double hTotalPixels,hTotalActivePixels,hBlankPixels; + double idealDutyCycle,hSyncWidth,hSyncBP,hBackPorch; + double idealHPeriod; + double vFreq,hFreq,dotClock; + GTF_constants c; + + /* Get rounded GTF constants used for internal calculations */ + GetInternalConstants(&c); + + /* Move input parameters into appropriate variables */ + vFreq = hFreq = dotClock = freq; + + /* Round pixels to character cell granularity */ + hPixels = round(hPixels / c.cellGran) * c.cellGran; + + /* For interlaced mode halve the vertical parameters, and double + * the required field refresh rate. + */ + vFieldRate = vFreq; + interlace = 0; + if (wantInterlace) + dotClock *= 2; + + /* Determine the lines for margins */ + if (wantMargins) { + topMarginLines = round(c.margin / 100 * vLines); + botMarginLines = round(c.margin / 100 * vLines); + } + else { + topMarginLines = 0; + botMarginLines = 0; + } + + if (type != GTF_lockPF) { + if (type == GTF_lockVF) { + /* Estimate the horizontal period */ + hPeriodEst = ((1/vFieldRate) - (c.minVSyncBP/1000000)) / + (vLines + (2*topMarginLines) + c.minPorch + interlace) * 1000000; + + /* Find the number of lines in vSync + back porch */ + vSyncBP = round(c.minVSyncBP / hPeriodEst); + } + else if (type == GTF_lockHF) { + /* Find the number of lines in vSync + back porch */ + vSyncBP = round((c.minVSyncBP * hFreq) / 1000); + } + + /* Find the number of lines in the V back porch alone */ + vBackPorch = vSyncBP - c.vSyncRqd; + + /* Find the total number of lines in the vertical period */ + vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP + + interlace + c.minPorch; + + if (type == GTF_lockVF) { + /* Estimate the vertical frequency */ + vFieldRateEst = 1000000 / (hPeriodEst * vTotalLines); + + /* Find the actual horizontal period */ + hPeriod = (hPeriodEst * vFieldRateEst) / vFieldRate; + + /* Find the actual vertical field frequency */ + vFieldRate = 1000000 / (hPeriod * vTotalLines); + } + else if (type == GTF_lockHF) { + /* Find the actual vertical field frequency */ + vFieldRate = (hFreq / vTotalLines) * 1000; + } + } + + /* Find the number of pixels in the left and right margins */ + if (wantMargins) { + leftMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran); + rightMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran); + } + else { + leftMarginPixels = 0; + rightMarginPixels = 0; + } + + /* Find the total number of active pixels in image + margins */ + hTotalActivePixels = hPixels + leftMarginPixels + rightMarginPixels; + + if (type == GTF_lockVF) { + /* Find the ideal blanking duty cycle */ + idealDutyCycle = c.c - ((c.m * hPeriod) / 1000); + } + else if (type == GTF_lockHF) { + /* Find the ideal blanking duty cycle */ + idealDutyCycle = c.c - (c.m / hFreq); + } + else if (type == GTF_lockPF) { + /* Find ideal horizontal period from blanking duty cycle formula */ + idealHPeriod = (((c.c - 100) + (sqrt((pow(100-c.c,2)) + + (0.4 * c.m * (hTotalActivePixels + rightMarginPixels + + leftMarginPixels) / dotClock)))) / (2 * c.m)) * 1000; + + /* Find the ideal blanking duty cycle */ + idealDutyCycle = c.c - ((c.m * idealHPeriod) / 1000); + } + + /* Find the number of pixels in blanking time */ + hBlankPixels = round((hTotalActivePixels * idealDutyCycle) / + ((100 - idealDutyCycle) * c.cellGran)) * c.cellGran; + + /* Find the total number of pixels */ + hTotalPixels = hTotalActivePixels + hBlankPixels; + + /* Find the horizontal back porch */ + hBackPorch = round((hBlankPixels / 2) / c.cellGran) * c.cellGran; + + /* Find the horizontal sync width */ + hSyncWidth = round(((c.hSync/100) * hTotalPixels) / c.cellGran) * c.cellGran; + + /* Find the horizontal sync + back porch */ + hSyncBP = hBackPorch + hSyncWidth; + + if (type == GTF_lockPF) { + /* Find the horizontal frequency */ + hFreq = (dotClock / hTotalPixels) * 1000; + + /* Find the number of lines in vSync + back porch */ + vSyncBP = round((c.minVSyncBP * hFreq) / 1000); + + /* Find the number of lines in the V back porch alone */ + vBackPorch = vSyncBP - c.vSyncRqd; + + /* Find the total number of lines in the vertical period */ + vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP + + interlace + c.minPorch; + + /* Find the actual vertical field frequency */ + vFieldRate = (hFreq / vTotalLines) * 1000; + } + else { + if (type == GTF_lockVF) { + /* Find the horizontal frequency */ + hFreq = 1000 / hPeriod; + } + else if (type == GTF_lockHF) { + /* Find the horizontal frequency */ + hPeriod = 1000 / hFreq; + } + + /* Find the pixel clock frequency */ + dotClock = hTotalPixels / hPeriod; + } + + /* Return the computed frequencies */ + t->vFreq = vFieldRate; + t->hFreq = hFreq; + t->dotClock = dotClock; + + /* Determine the vertical timing parameters */ + t->h.hTotal = (int)hTotalPixels; + t->h.hDisp = (int)hTotalActivePixels; + t->h.hSyncStart = t->h.hTotal - (int)hSyncBP; + t->h.hSyncEnd = t->h.hTotal - (int)hBackPorch; + t->h.hFrontPorch = t->h.hSyncStart - t->h.hDisp; + t->h.hSyncWidth = (int)hSyncWidth; + t->h.hBackPorch = (int)hBackPorch; + + /* Determine the vertical timing parameters */ + t->v.vTotal = (int)vTotalLines; + t->v.vDisp = (int)vLines; + t->v.vSyncStart = t->v.vTotal - (int)vSyncBP; + t->v.vSyncEnd = t->v.vTotal - (int)vBackPorch; + t->v.vFrontPorch = t->v.vSyncStart - t->v.vDisp; + t->v.vSyncWidth = (int)c.vSyncRqd; + t->v.vBackPorch = (int)vBackPorch; + if (wantInterlace) { + /* Halve the timings for interlaced modes */ + t->v.vTotal /= 2; + t->v.vDisp /= 2; + t->v.vSyncStart /= 2; + t->v.vSyncEnd /= 2; + t->v.vFrontPorch /= 2; + t->v.vSyncWidth /= 2; + t->v.vBackPorch /= 2; + t->dotClock /= 2; + } + + /* Mark as GTF timing using the sync polarities */ + t->interlace = (wantInterlace) ? 'I' : 'N'; + t->hSyncPol = '-'; + t->vSyncPol = '+'; +} + +void GTF_getConstants(GTF_constants *constants) +{ *constants = GC; } + +void GTF_setConstants(GTF_constants *constants) +{ GC = *constants; } + +#ifdef TESTING_GTF + +void main(int argc,char *argv[]) +{ + FILE *f; + double xPixels,yPixels,freq; + ibool interlace; + GTF_timings t; + + if (argc != 5 && argc != 6) { + printf("Usage: GTFCALC [[Hz] [KHz] [MHz]] [I]\n"); + printf("\n"); + printf("where is the horizontal resolution of the mode, is the\n"); + printf("vertical resolution of the mode. The value will be the frequency to\n"); + printf("drive the calculations, and will be either the vertical frequency (in Hz)\n"); + printf("the horizontal frequency (in KHz) or the dot clock (in MHz). To generate\n"); + printf("timings for an interlaced mode, add 'I' to the end of the command line.\n"); + printf("\n"); + printf("For example to generate timings for 640x480 at 60Hz vertical:\n"); + printf("\n"); + printf(" GTFCALC 640 480 60 Hz\n"); + printf("\n"); + printf("For example to generate timings for 640x480 at 31.5KHz horizontal:\n"); + printf("\n"); + printf(" GTFCALC 640 480 31.5 KHz\n"); + printf("\n"); + printf("For example to generate timings for 640x480 with a 25.175Mhz dot clock:\n"); + printf("\n"); + printf(" GTFCALC 640 480 25.175 MHz\n"); + printf("\n"); + printf("GTFCALC will print a summary of the results found, and dump the CRTC\n"); + printf("values to the UVCONFIG.CRT file in the format used by SciTech Display Doctor.\n"); + exit(1); + } + + /* Get values from command line */ + xPixels = atof(argv[1]); + yPixels = atof(argv[2]); + freq = atof(argv[3]); + interlace = ((argc == 6) && (argv[5][0] == 'I')); + + /* Compute the CRTC timings */ + if (toupper(argv[4][0]) == 'H') + GTF_calcTimings(xPixels,yPixels,freq,GTF_lockVF,false,interlace,&t); + else if (toupper(argv[4][0]) == 'K') + GTF_calcTimings(xPixels,yPixels,freq,GTF_lockHF,false,interlace,&t); + else if (toupper(argv[4][0]) == 'M') + GTF_calcTimings(xPixels,yPixels,freq,GTF_lockPF,false,interlace,&t); + else { + printf("Unknown command line!\n"); + exit(1); + } + + /* Dump summary info to standard output */ + printf("CRTC values for %.0fx%.0f @ %.2f %s\n", xPixels, yPixels, freq, argv[4]); + printf("\n"); + printf(" hTotal = %-4d vTotal = %-4d\n", + t.h.hTotal, t.v.vTotal); + printf(" hDisp = %-4d vDisp = %-4d\n", + t.h.hDisp, t.v.vDisp); + printf(" hSyncStart = %-4d vSyncStart = %-4d\n", + t.h.hSyncStart, t.v.vSyncStart); + printf(" hSyncEnd = %-4d vSyncEnd = %-4d\n", + t.h.hSyncEnd, t.v.vSyncEnd); + printf(" hFrontPorch = %-4d vFrontPorch = %-4d\n", + t.h.hFrontPorch, t.v.vFrontPorch); + printf(" hSyncWidth = %-4d vSyncWidth = %-4d\n", + t.h.hSyncWidth, t.v.vSyncWidth); + printf(" hBackPorch = %-4d vBackPorch = %-4d\n", + t.h.hBackPorch, t.v.vBackPorch); + printf("\n"); + printf(" Interlaced = %s\n", (t.interlace == 'I') ? "Yes" : "No"); + printf(" H sync pol = %c\n", t.hSyncPol); + printf(" V sync pol = %c\n", t.vSyncPol); + printf("\n"); + printf(" Vert freq = %.2f Hz\n", t.vFreq); + printf(" Horiz freq = %.2f KHz\n", t.hFreq); + printf(" Dot Clock = %.2f Mhz\n", t.dotClock); + + /* Dump to file in format used by SciTech Display Doctor */ + if ((f = fopen("UVCONFIG.CRT","w")) != NULL) { + fprintf(f, "[%.0f %.0f]\n", xPixels, yPixels); + fprintf(f, "%d %d %d %d '%c' %s\n", + t.h.hTotal, t.h.hDisp, + t.h.hSyncStart, t.h.hSyncEnd, + t.hSyncPol, (t.interlace == 'I') ? "I" : "NI"); + fprintf(f, "%d %d %d %d '%c'\n", + t.v.vTotal, t.v.vDisp, + t.v.vSyncStart, t.v.vSyncEnd, + t.vSyncPol); + fprintf(f, "%.2f\n", t.dotClock); + fclose(f); + } +} + +#endif /* TESTING */ diff --git a/board/MAI/bios_emulator/scitech/src/common/libcimp.c b/board/MAI/bios_emulator/scitech/src/common/libcimp.c new file mode 100644 index 0000000..ab73ad5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/libcimp.c @@ -0,0 +1,827 @@ +/**************************************************************************** +* +* SciTech MGL Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module to implement a the OS specific side of the Binary +* Portable DLL C runtime library. The functions in here +* are imported into the Binary Portable DLL's to implement +* OS specific services. +* +****************************************************************************/ + +#include "pmapi.h" +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +#include "drvlib/peloader.h" +#include "drvlib/attrib.h" +#include "drvlib/libc/init.h" +#define __BUILDING_PE_LOADER__ +#include "drvlib/libc/file.h" +#if defined(__WIN32_VXD__) +#include "vxdfile.h" +#endif +#else +#include +#include +#include +#include +#include +#include +#include +#if defined(__GNUC__) || defined(__UNIX__) +#include +#include +#include +#else +#include +#endif +#include "drvlib/attrib.h" +#include "drvlib/libc/init.h" +#define __BUILDING_PE_LOADER__ +#include "drvlib/libc/file.h" +#if defined(__WINDOWS__) || defined(TNT) || defined(__RTTARGET__) +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#endif +#ifdef __MSDOS__ +#include +#endif +#ifdef __OS2__ +#define INCL_DOS +#define INCL_DOSERRORS +#define INCL_SUB +#include +#endif +#endif + +/* No text or binary modes for Unix */ + +#ifndef O_BINARY +#define O_BINARY 0 +#define O_TEXT 0 +#endif + +/*--------------------------- Global variables ----------------------------*/ + +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +#define MAX_FILES 16 +static FILE *openHandles[MAX_FILES] = {NULL}; +#endif + +/* stub functions */ +void _CDECL stub_abort(void); +int _CDECL stub_atexit(void (*)(void)); +void * _CDECL stub_calloc(size_t _nelem, size_t _size); +void _CDECL stub_exit(int _status); +void _CDECL stub_free(void *_ptr); +char * _CDECL stub_getenv(const char *_name); +void * _CDECL stub_malloc(size_t _size); +void * _CDECL stub_realloc(void *_ptr, size_t _size); +int _CDECL stub_system(const char *_s); +int _CDECL stub_putenv(const char *_val); + +/* stub functions */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode); +int _CDECL stub_access(const char *_path, int _amode); +int _CDECL stub_close(int _fildes); +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence); +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte); +int _CDECL stub_unlink(const char *_path); +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte); +int _CDECL stub_isatty(int _fildes); + +/* stub functions */ +int _CDECL stub_remove(const char *_filename); +int _CDECL stub_rename(const char *_old, const char *_new); + +/* stub functions */ +time_t _CDECL stub_time(time_t *_tod); + +/* stub functions */ +int _CDECL stub_raise(int); +void * _CDECL stub_signal(int, void *); + +/* functions */ +#define stub_OS_setfileattr _OS_setfileattr +#define stub_OS_getcurrentdate _OS_getcurrentdate + +LIBC_imports _VARAPI ___imports = { + sizeof(LIBC_imports), + + /* exports */ + stub_abort, + stub_atexit, + stub_calloc, + stub_exit, + stub_free, + stub_getenv, + stub_malloc, + stub_realloc, + stub_system, + stub_putenv, + + /* exports */ + stub_open, + stub_access, + stub_close, + stub_lseek, + stub_read, + stub_unlink, + stub_write, + stub_isatty, + + /* exports */ + stub_remove, + stub_rename, + + /* functions */ + stub_raise, + stub_signal, + + /* exports */ + stub_time, + + /* exports */ + stub_OS_setfileattr, + stub_OS_getcurrentdate, + }; + +/*---------------------- Stub function implementation ---------------------*/ + +/* stub functions */ +void _CDECL stub_abort(void) +{ +#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__) + abort(); +#endif +} + +int _CDECL stub_atexit(void (*func)(void)) +{ +#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__) + return atexit((void(*)(void))func); +#else + return -1; +#endif +} + +void * _CDECL stub_calloc(size_t _nelem, size_t _size) +{ return __PM_calloc(_nelem,_size); } + +void _CDECL stub_exit(int _status) +{ +#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__) + exit(_status); +#endif +} + +void _CDECL stub_free(void *_ptr) +{ __PM_free(_ptr); } + +char * _CDECL stub_getenv(const char *_name) +{ +#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__) + return NULL; +#else + return getenv(_name); +#endif +} + +void * _CDECL stub_malloc(size_t _size) +{ return __PM_malloc(_size); } + +void * _CDECL stub_realloc(void *_ptr, size_t _size) +{ return __PM_realloc(_ptr,_size); } + +int _CDECL stub_system(const char *_s) +{ +#if defined(__WINDOWS__) || defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) || defined(__RTTARGET__) + (void)_s; + return -1; +#else + return system(_s); +#endif +} + +int _CDECL stub_putenv(const char *_val) +{ +#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__) + return -1; +#else + return putenv((char*)_val); +#endif +} + +time_t _CDECL stub_time(time_t *_tod) +{ +#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__) + return 0; +#else + return time(_tod); +#endif +} + +#if defined(__MSDOS__) + +#if defined(TNT) && defined(_MSC_VER) + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ SetFileAttributes((LPSTR)filename, (DWORD)attrib); } + +#else + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ _dos_setfileattr(filename,attrib); } + +#endif + +#elif defined(__WIN32_VXD__) + +#define USE_LOCAL_FILEIO +#define USE_LOCAL_GETDATE + +/* stub functions */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) +{ + char mode[10]; + int i; + + /* Find an empty file handle to use */ + for (i = 3; i < MAX_FILES; i++) { + if (!openHandles[i]) + break; + } + if (openHandles[i]) + return -1; + + /* Find the open flags to use */ + if (_oflag & ___O_TRUNC) + strcpy(mode,"w"); + else if (_oflag & ___O_CREAT) + strcpy(mode,"a"); + else + strcpy(mode,"r"); + if (_oflag & ___O_BINARY) + strcat(mode,"b"); + if (_oflag & ___O_TEXT) + strcat(mode,"t"); + + /* Open the file and store the file handle */ + if ((openHandles[i] = fopen(_path,mode)) == NULL) + return -1; + return i; +} + +int _CDECL stub_access(const char *_path, int _amode) +{ return -1; } + +int _CDECL stub_close(int _fildes) +{ + if (_fildes >= 3 && openHandles[_fildes]) { + fclose(openHandles[_fildes]); + openHandles[_fildes] = NULL; + } + return 0; +} + +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) +{ + if (_fildes >= 3) { + fseek(openHandles[_fildes],_offset,_whence); + return ftell(openHandles[_fildes]); + } + return 0; +} + +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) +{ + if (_fildes >= 3) + return fread(_buf,1,_nbyte,openHandles[_fildes]); + return 0; +} + +int _CDECL stub_unlink(const char *_path) +{ + WORD error; + + if (initComplete) { + if (R0_DeleteFile((char*)_path,0,&error)) + return 0; + return -1; + } + else + return i_remove(_path); +} + +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) +{ + if (_fildes >= 3) + return fwrite(_buf,1,_nbyte,openHandles[_fildes]); + return _nbyte; +} + +int _CDECL stub_isatty(int _fildes) +{ return 0; } + +/* stub functions */ +int _CDECL stub_remove(const char *_filename) +{ return stub_unlink(_filename); } + +int _CDECL stub_rename(const char *_old, const char *_new) +{ return -1; } + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ + WORD error; + if (initComplete) + R0_SetFileAttributes((char*)filename,attrib,&error); +} + +/* Return the current date in days since 1/1/1980 */ +ulong _CDECL _OS_getcurrentdate(void) +{ + DWORD date; + VTD_Get_Date_And_Time(&date); + return date; +} + +#elif defined(__NT_DRIVER__) + +#define USE_LOCAL_FILEIO +#define USE_LOCAL_GETDATE + +/* stub functions */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) +{ + char mode[10]; + int i; + + /* Find an empty file handle to use */ + for (i = 3; i < MAX_FILES; i++) { + if (!openHandles[i]) + break; + } + if (openHandles[i]) + return -1; + + /* Find the open flags to use */ + if (_oflag & ___O_TRUNC) + strcpy(mode,"w"); + else if (_oflag & ___O_CREAT) + strcpy(mode,"a"); + else + strcpy(mode,"r"); + if (_oflag & ___O_BINARY) + strcat(mode,"b"); + if (_oflag & ___O_TEXT) + strcat(mode,"t"); + + /* Open the file and store the file handle */ + if ((openHandles[i] = fopen(_path,mode)) == NULL) + return -1; + return i; +} + +int _CDECL stub_close(int _fildes) +{ + if (_fildes >= 3 && openHandles[_fildes]) { + fclose(openHandles[_fildes]); + openHandles[_fildes] = NULL; + } + return 0; +} + +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) +{ + if (_fildes >= 3) { + fseek(openHandles[_fildes],_offset,_whence); + return ftell(openHandles[_fildes]); + } + return 0; +} + +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) +{ + if (_fildes >= 3) + return fread(_buf,1,_nbyte,openHandles[_fildes]); + return 0; +} + +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) +{ + if (_fildes >= 3) + return fwrite(_buf,1,_nbyte,openHandles[_fildes]); + return _nbyte; +} + +int _CDECL stub_access(const char *_path, int _amode) +{ return -1; } + +int _CDECL stub_isatty(int _fildes) +{ return 0; } + +int _CDECL stub_unlink(const char *_path) +{ + /* TODO: Implement this! */ + return -1; +} + +/* stub functions */ +int _CDECL stub_remove(const char *_filename) +{ return stub_unlink(_filename); } + +int _CDECL stub_rename(const char *_old, const char *_new) +{ + /* TODO: Implement this! */ + return -1; +} + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ + uint _attr = 0; + if (attrib & __A_RDONLY) + _attr |= FILE_ATTRIBUTE_READONLY; + if (attrib & __A_HIDDEN) + _attr |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & __A_SYSTEM) + _attr |= FILE_ATTRIBUTE_SYSTEM; + PM_setFileAttr(filename,_attr); +} + +/* Return the current date in days since 1/1/1980 */ +ulong _CDECL _OS_getcurrentdate(void) +{ + TIME_FIELDS tm; + _int64 count,count_1_1_1980; + + tm.Year = 1980; + tm.Month = 1; + tm.Day = 1; + tm.Hour = 0; + tm.Minute = 0; + tm.Second = 0; + tm.Milliseconds = 0; + tm.Weekday = 0; + RtlTimeFieldsToTime(&tm,(PLARGE_INTEGER)&count_1_1_1980); + KeQuerySystemTime((PLARGE_INTEGER)&count); + return (ulong)( (count - count_1_1_1980) / ((_int64)24 * (_int64)3600 * (_int64)10000000) ); +} + +#elif defined(__WINDOWS32__) || defined(__RTTARGET__) + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ SetFileAttributes((LPSTR)filename, (DWORD)attrib); } + +#elif defined(__OS2__) + +#define USE_LOCAL_FILEIO + +#ifndef W_OK +#define W_OK 0x02 +#endif + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ + FILESTATUS3 s; + if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s))) + return; + s.attrFile = attrib; + DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s),0L); +} + +/* stub functions */ + +#define BUF_SIZE 4096 + +/* Note: the implementation of the standard Unix-ish handle-based I/O isn't + * complete - but that wasn't the intent either. Note also that we + * don't presently support text file I/O, so all text files end + * up in Unix format (and are not translated!). + */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) +{ + HFILE handle; + ULONG error, actiontaken, openflag, openmode; + char path[PM_MAX_PATH]; + + /* Determine open flags */ + if (_oflag & ___O_CREAT) { + if (_oflag & ___O_EXCL) + openflag = OPEN_ACTION_FAIL_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + else if (_oflag & ___O_TRUNC) + openflag = OPEN_ACTION_REPLACE_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + else + openflag = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + } + else if (_oflag & ___O_TRUNC) + openflag = OPEN_ACTION_REPLACE_IF_EXISTS; + else + openflag = OPEN_ACTION_OPEN_IF_EXISTS; + + /* Determine open mode flags */ + if (_oflag & ___O_RDONLY) + openmode = OPEN_ACCESS_READONLY | OPEN_SHARE_DENYNONE; + else if (_oflag & ___O_WRONLY) + openmode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_DENYWRITE; + else + openmode = OPEN_ACCESS_READWRITE | OPEN_SHARE_DENYWRITE; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(path,_path); + if (DosOpen(path, &handle, &actiontaken, 0, FILE_NORMAL, + openflag, openmode, NULL) != NO_ERROR) + return -1; + + /* Handle append mode of operation */ + if (_oflag & ___O_APPEND) { + if (DosSetFilePtr(handle, 0, FILE_END, &error) != NO_ERROR) + return -1; + } + return handle; +} + +int _CDECL stub_access(const char *_path, int _amode) +{ + char path[PM_MAX_PATH]; + FILESTATUS fs; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(path,_path); + if (DosQueryPathInfo(path, FIL_STANDARD, &fs, sizeof(fs)) != NO_ERROR) + return -1; + if ((_amode & W_OK) && (fs.attrFile & FILE_READONLY)) + return -1; + return 0; +} + +int _CDECL stub_close(int _fildes) +{ + if (DosClose(_fildes) != NO_ERROR) + return -1; + return 0; +} + +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) +{ + ULONG cbActual, origin; + + switch (_whence) { + case SEEK_CUR: + origin = FILE_CURRENT; + break; + case SEEK_END: + origin = FILE_END; + break; + default: + origin = FILE_BEGIN; + } + if (DosSetFilePtr(_fildes, _offset, origin, &cbActual) != NO_ERROR) + return -1; + return cbActual; +} + +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) +{ + ULONG cbActual = 0,cbRead; + uchar *p = _buf; + uchar file_io_buf[BUF_SIZE]; + + /* We need to perform the physical read in chunks into a + * a temporary static buffer, since the buffer passed in may be + * in kernel space and will cause DosRead to bail internally. + */ + while (_nbyte > BUF_SIZE) { + if (DosRead(_fildes, file_io_buf, BUF_SIZE, &cbRead) != NO_ERROR) + return -1; + cbActual += cbRead; + memcpy(p,file_io_buf,BUF_SIZE); + p += BUF_SIZE; + _nbyte -= BUF_SIZE; + } + if (_nbyte) { + if (DosRead(_fildes, file_io_buf, _nbyte, &cbRead) != NO_ERROR) + return -1; + cbActual += cbRead; + memcpy(p,file_io_buf,_nbyte); + } + return cbActual; +} + +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) +{ + ULONG cbActual = 0,cbWrite; + uchar *p = (PVOID)_buf; + uchar file_io_buf[BUF_SIZE]; + + /* We need to perform the physical write in chunks from a + * a temporary static buffer, since the buffer passed in may be + * in kernel space and will cause DosWrite to bail internally. + */ + while (_nbyte > BUF_SIZE) { + memcpy(file_io_buf,p,BUF_SIZE); + if (DosWrite(_fildes, file_io_buf, BUF_SIZE, &cbWrite) != NO_ERROR) + return -1; + cbActual += cbWrite; + p += BUF_SIZE; + _nbyte -= BUF_SIZE; + } + if (_nbyte) { + memcpy(file_io_buf,p,_nbyte); + if (DosWrite(_fildes, file_io_buf, _nbyte, &cbWrite) != NO_ERROR) + return -1; + cbActual += cbWrite; + } + return cbActual; +} + +int _CDECL stub_unlink(const char *_path) +{ + char path[PM_MAX_PATH]; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(path,_path); + if (DosDelete(path) != NO_ERROR) + return -1; + return 0; +} + +int _CDECL stub_isatty(int _fildes) +{ + ULONG htype, flags; + + if (DosQueryHType(_fildes, &htype, &flags) != NO_ERROR) + return 0; + return ((htype & 0xFF) == HANDTYPE_DEVICE); +} + +/* stub functions */ +int _CDECL stub_remove(const char *_path) +{ + char path[PM_MAX_PATH]; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(path,_path); + if (DosDelete(path) != NO_ERROR) + return -1; + return 0; +} + +int _CDECL stub_rename(const char *_old, const char *_new) +{ + char old[PM_MAX_PATH]; + char new[PM_MAX_PATH]; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(old,_old); + strcpy(new,_new); + if (DosMove(old, new) != NO_ERROR) + return -1; + return 0; +} + +#else + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ /* Unable to set hidden, system attributes on Unix. */ } + +#endif + +#ifndef USE_LOCAL_FILEIO + +/* stub functions */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) +{ + int oflag_tab[] = { + ___O_RDONLY, O_RDONLY, + ___O_WRONLY, O_WRONLY, + ___O_RDWR, O_RDWR, + ___O_BINARY, O_BINARY, + ___O_TEXT, O_TEXT, + ___O_CREAT, O_CREAT, + ___O_EXCL, O_EXCL, + ___O_TRUNC, O_TRUNC, + ___O_APPEND, O_APPEND, + }; + int i,oflag = 0; + + /* Translate the oflag's to the OS dependent versions */ + for (i = 0; i < sizeof(oflag_tab) / sizeof(int); i += 2) { + if (_oflag & oflag_tab[i]) + oflag |= oflag_tab[i+1]; + } + return open(_path,oflag,_mode); +} + +int _CDECL stub_access(const char *_path, int _amode) +{ return access(_path,_amode); } + +int _CDECL stub_close(int _fildes) +{ return close(_fildes); } + +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) +{ return lseek(_fildes,_offset,_whence); } + +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) +{ return read(_fildes,_buf,_nbyte); } + +int _CDECL stub_unlink(const char *_path) +{ return unlink(_path); } + +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) +{ return write(_fildes,_buf,_nbyte); } + +int _CDECL stub_isatty(int _fildes) +{ return isatty(_fildes); } + +/* stub functions */ +int _CDECL stub_remove(const char *_filename) +{ return remove(_filename); } + +int _CDECL stub_rename(const char *_old, const char *_new) +{ return rename(_old,_new); } + +#endif + +#ifndef USE_LOCAL_GETDATE + +/* Return the current date in days since 1/1/1980 */ +ulong _CDECL _OS_getcurrentdate(void) +{ + struct tm refTime; + refTime.tm_year = 80; + refTime.tm_mon = 0; + refTime.tm_mday = 1; + refTime.tm_hour = 0; + refTime.tm_min = 0; + refTime.tm_sec = 0; + refTime.tm_isdst = -1; + return (time(NULL) - mktime(&refTime)) / (24 * 3600L); +} + +#endif + +int _CDECL stub_raise(int sig) +{ +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) + return -1; +#else + return raise(sig); +#endif +} + +#ifdef __WINDOWS32__ +typedef void (*__code_ptr)(int); +#else +typedef void (*__code_ptr)(); +#endif + +void * _CDECL stub_signal(int sig, void *handler) +{ +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) + return NULL; +#else + return (void*)signal(sig,(__code_ptr)handler); +#endif +} diff --git a/board/MAI/bios_emulator/scitech/src/common/makefile b/board/MAI/bios_emulator/scitech/src/common/makefile new file mode 100644 index 0000000..5aac038 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/makefile @@ -0,0 +1,18 @@ +############################################################################# +# +# Copyright (C) 1996 SciTech Software. +# All rights reserved. +# +# Descripton: Makefile for UniVBE(tm), UniPOWER(tm), UVBELib(tm) and +# DPMSLib library files. Requires Borland C++ 4.52 to build +# some components. +# +# $Date: 2002/10/02 15:35:20 $ $Author: hfrieden $ +# +############################################################################# + +CFLAGS += -DTESTING_GTF + +gtfcalc$E: gtfcalc$O + +.INCLUDE: "$(SCITECH)/makedefs/common.mk" diff --git a/board/MAI/bios_emulator/scitech/src/common/peloader.c b/board/MAI/bios_emulator/scitech/src/common/peloader.c new file mode 100644 index 0000000..a134bb0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/peloader.c @@ -0,0 +1,586 @@ +/**************************************************************************** +* +* SciTech MGL Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module to implement a simple Portable Binary DLL loader +* library. This library can be used to load PE DLL's under +* any Intel based OS, provided the DLL's do not have any +* imports in the import table. +* +* NOTE: This loader module expects the DLL's to be built with +* Watcom C++ and may produce unexpected results with +* DLL's linked by another compiler. +* +****************************************************************************/ + +#include "drvlib/peloader.h" +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "drvlib/libc/init.h" +#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#endif +#include "drvlib/pe.h" + +/*--------------------------- Global variables ----------------------------*/ + +static int result = PE_ok; + +/*------------------------- Implementation --------------------------------*/ + +/**************************************************************************** +PARAMETERS: +f - Handle to open file to read driver from +startOffset - Offset to the start of the driver within the file + +RETURNS: +Handle to loaded PE DLL, or NULL on failure. + +REMARKS: +This function loads a Portable Binary DLL library from disk, relocates +the code and returns a handle to the loaded library. This function is the +same as the regular PE_loadLibrary except that it take a handle to an +open file and an offset within that file for the DLL to load. +****************************************************************************/ +static int PE_readHeader( + FILE *f, + long startOffset, + FILE_HDR *filehdr, + OPTIONAL_HDR *opthdr) +{ + EXE_HDR exehdr; + ulong offset,signature; + + /* Read the EXE header and check for valid header signature */ + result = PE_invalidDLLImage; + fseek(f, startOffset, SEEK_SET); + if (fread(&exehdr, 1, sizeof(exehdr), f) != sizeof(exehdr)) + return false; + if (exehdr.signature != 0x5A4D) + return false; + + /* Now seek to the start of the PE header defined at offset 0x3C + * in the MS-DOS EXE header, and read the signature and check it. + */ + fseek(f, startOffset+0x3C, SEEK_SET); + if (fread(&offset, 1, sizeof(offset), f) != sizeof(offset)) + return false; + fseek(f, startOffset+offset, SEEK_SET); + if (fread(&signature, 1, sizeof(signature), f) != sizeof(signature)) + return false; + if (signature != 0x00004550) + return false; + + /* Now read the PE file header and check that it is correct */ + if (fread(filehdr, 1, sizeof(*filehdr), f) != sizeof(*filehdr)) + return false; + if (filehdr->Machine != IMAGE_FILE_MACHINE_I386) + return false; + if (!(filehdr->Characteristics & IMAGE_FILE_32BIT_MACHINE)) + return false; + if (!(filehdr->Characteristics & IMAGE_FILE_DLL)) + return false; + if (fread(opthdr, 1, sizeof(*opthdr), f) != sizeof(*opthdr)) + return false; + if (opthdr->Magic != 0x10B) + return false; + + /* Success, so return true! */ + return true; +} + +/**************************************************************************** +PARAMETERS: +f - Handle to open file to read driver from +startOffset - Offset to the start of the driver within the file + +RETURNS: +Size of the DLL file on disk, or -1 on error + +REMARKS: +This function scans the headers for a Portable Binary DLL to determine the +length of the DLL file on disk. +{secret} +****************************************************************************/ +ulong PEAPI PE_getFileSize( + FILE *f, + ulong startOffset) +{ + FILE_HDR filehdr; + OPTIONAL_HDR opthdr; + SECTION_HDR secthdr; + ulong size; + int i; + + /* Read the PE file headers from disk */ + if (!PE_readHeader(f,startOffset,&filehdr,&opthdr)) + return 0xFFFFFFFF; + + /* Scan all the section headers summing up the total size */ + size = opthdr.SizeOfHeaders; + for (i = 0; i < filehdr.NumberOfSections; i++) { + if (fread(§hdr, 1, sizeof(secthdr), f) != sizeof(secthdr)) + return 0xFFFFFFFF; + size += secthdr.SizeOfRawData; + } + return size; +} + +/**************************************************************************** +DESCRIPTION: +Loads a Portable Binary DLL into memory from an open file + +HEADER: +peloader.h + +PARAMETERS: +f - Handle to open file to read driver from +startOffset - Offset to the start of the driver within the file +size - Place to store the size of the driver loaded +shared - True to load module into shared memory + +RETURNS: +Handle to loaded PE DLL, or NULL on failure. + +REMARKS: +This function loads a Portable Binary DLL library from disk, relocates +the code and returns a handle to the loaded library. This function is the +same as the regular PE_loadLibrary except that it take a handle to an +open file and an offset within that file for the DLL to load. + +SEE ALSO: +PE_loadLibrary, PE_getProcAddress, PE_freeLibrary +****************************************************************************/ +PE_MODULE * PEAPI PE_loadLibraryExt( + FILE *f, + ulong startOffset, + ulong *size, + ibool shared) +{ + FILE_HDR filehdr; + OPTIONAL_HDR opthdr; + SECTION_HDR secthdr; + ulong offset,pageOffset; + ulong text_off,text_addr,text_size; + ulong data_off,data_addr,data_size,data_end; + ulong export_off,export_addr,export_size,export_end; + ulong reloc_off,reloc_size; + ulong image_size; + int i,delta,numFixups; + ushort relocType,*fixup; + PE_MODULE *hMod = NULL; + void *reloc = NULL; + BASE_RELOCATION *baseReloc; + InitLibC_t InitLibC; + + /* Read the PE file headers from disk */ + if (!PE_readHeader(f,startOffset,&filehdr,&opthdr)) + return NULL; + + /* Scan all the section headers and find the necessary sections */ + text_off = data_off = reloc_off = export_off = 0; + text_addr = text_size = 0; + data_addr = data_size = data_end = 0; + export_addr = export_size = export_end = 0; + reloc_size = 0; + for (i = 0; i < filehdr.NumberOfSections; i++) { + if (fread(§hdr, 1, sizeof(secthdr), f) != sizeof(secthdr)) + goto Error; + if (strcmp(secthdr.Name, ".edata") == 0 || strcmp(secthdr.Name, ".rdata") == 0) { + /* Exports section */ + export_off = secthdr.PointerToRawData; + export_addr = secthdr.VirtualAddress; + export_size = secthdr.SizeOfRawData; + export_end = export_addr + export_size; + } + else if (strcmp(secthdr.Name, ".idata") == 0) { + /* Imports section, ignore */ + } + else if (strcmp(secthdr.Name, ".reloc") == 0) { + /* Relocations section */ + reloc_off = secthdr.PointerToRawData; + reloc_size = secthdr.SizeOfRawData; + } + else if (!text_off && secthdr.Characteristics & IMAGE_SCN_CNT_CODE) { + /* Code section */ + text_off = secthdr.PointerToRawData; + text_addr = secthdr.VirtualAddress; + text_size = secthdr.SizeOfRawData; + } + else if (!data_off && secthdr.Characteristics & IMAGE_SCN_CNT_INITIALIZED_DATA) { + /* Data section */ + data_off = secthdr.PointerToRawData; + data_addr = secthdr.VirtualAddress; + data_size = secthdr.SizeOfRawData; + data_end = data_addr + data_size; + } + } + + /* Check to make sure that we have all the sections we need */ + if (!text_off || !data_off || !export_off || !reloc_off) { + result = PE_invalidDLLImage; + goto Error; + } + + /* Find the size of the image to load allocate memory for it */ + image_size = MAX(export_end,data_end) - text_addr; + *size = sizeof(PE_MODULE) + image_size + 4096; + if (shared) + hMod = PM_mallocShared(*size); + else + hMod = PM_malloc(*size); + reloc = PM_malloc(reloc_size); + if (!hMod || !reloc) { + result = PE_outOfMemory; + goto Error; + } + + hMod->text = (uchar*)ROUND_4K((ulong)hMod + sizeof(PE_MODULE)); + hMod->data = (uchar*)((ulong)hMod->text + (data_addr - text_addr)); + hMod->export = (uchar*)((ulong)hMod->text + (export_addr - text_addr)); + hMod->textBase = text_addr; + hMod->dataBase = data_addr; + hMod->exportBase = export_addr; + hMod->exportDir = opthdr.DataDirectory[0].RelVirtualAddress - export_addr; + hMod->shared = shared; + + /* Now read the section images from disk */ + result = PE_invalidDLLImage; + fseek(f, startOffset+text_off, SEEK_SET); + if (fread(hMod->text, 1, text_size, f) != text_size) + goto Error; + fseek(f, startOffset+data_off, SEEK_SET); + if (fread(hMod->data, 1, data_size, f) != data_size) + goto Error; + fseek(f, startOffset+export_off, SEEK_SET); + if (fread(hMod->export, 1, export_size, f) != export_size) + goto Error; + fseek(f, startOffset+reloc_off, SEEK_SET); + if (fread(reloc, 1, reloc_size, f) != reloc_size) + goto Error; + + /* Now perform relocations on all sections in the image */ + delta = (ulong)hMod->text - opthdr.ImageBase - text_addr; + baseReloc = (BASE_RELOCATION*)reloc; + for (;;) { + /* Check for termination condition */ + if (!baseReloc->PageRVA || !baseReloc->BlockSize) + break; + + /* Do fixups */ + pageOffset = baseReloc->PageRVA - hMod->textBase; + numFixups = (baseReloc->BlockSize - sizeof(BASE_RELOCATION)) / sizeof(ushort); + fixup = (ushort*)(baseReloc + 1); + for (i = 0; i < numFixups; i++) { + relocType = *fixup >> 12; + if (relocType) { + offset = pageOffset + (*fixup & 0x0FFF); + *(ulong*)(hMod->text + offset) += delta; + } + fixup++; + } + + /* Move to next relocation block */ + baseReloc = (BASE_RELOCATION*)((ulong)baseReloc + baseReloc->BlockSize); + } + + /* Initialise the C runtime library for the loaded DLL */ + result = PE_unableToInitLibC; + if ((InitLibC = (InitLibC_t)PE_getProcAddress(hMod,"_InitLibC")) == NULL) + goto Error; + if (!InitLibC(&___imports,PM_getOSType())) + goto Error; + + /* Clean up, close the file and return the loaded module handle */ + PM_free(reloc); + result = PE_ok; + return hMod; + +Error: + if (shared) + PM_freeShared(hMod); + else + PM_free(hMod); + PM_free(reloc); + return NULL; +} + +/**************************************************************************** +DESCRIPTION: +Loads a Portable Binary DLL into memory + +HEADER: +peloader.h + +PARAMETERS: +szDLLName - Name of the PE DLL library to load +shared - True to load module into shared memory + +RETURNS: +Handle to loaded PE DLL, or NULL on failure. + +REMARKS: +This function loads a Portable Binary DLL library from disk, relocates +the code and returns a handle to the loaded library. This function +will only work on DLL's that do not have any imports, since we don't +resolve import dependencies in this function. + +SEE ALSO: +PE_getProcAddress, PE_freeLibrary +****************************************************************************/ +PE_MODULE * PEAPI PE_loadLibrary( + const char *szDLLName, + ibool shared) +{ + PE_MODULE *hMod; + +#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) + if (!shared) { + PM_MODULE hInst; + InitLibC_t InitLibC; + + /* For Win32 if are building checked libraries for debugging, we use + * the real Win32 DLL functions so that we can debug the resulting DLL + * files with the Win32 debuggers. Note that we can't do this if + * we need to load the files into a shared memory context. + */ + if ((hInst = PM_loadLibrary(szDLLName)) == NULL) { + result = PE_fileNotFound; + return NULL; + } + + /* Initialise the C runtime library for the loaded DLL */ + result = PE_unableToInitLibC; + if ((InitLibC = (void*)PM_getProcAddress(hInst,"_InitLibC")) == NULL) + return NULL; + if (!InitLibC(&___imports,PM_getOSType())) + return NULL; + + /* Allocate the PE_MODULE structure */ + if ((hMod = PM_malloc(sizeof(*hMod))) == NULL) + return NULL; + hMod->text = (void*)hInst; + hMod->shared = -1; + + /* DLL loaded successfully so return module handle */ + result = PE_ok; + return hMod; + } + else +#endif + { + FILE *f; + ulong size; + + /* Attempt to open the file on disk */ + if (shared < 0) + shared = 0; + if ((f = fopen(szDLLName,"rb")) == NULL) { + result = PE_fileNotFound; + return NULL; + } + hMod = PE_loadLibraryExt(f,0,&size,shared); + fclose(f); + return hMod; + } +} + +/**************************************************************************** +DESCRIPTION: +Loads a Portable Binary DLL into memory + +HEADER: +peloader.h + +PARAMETERS: +szDLLName - Name of the PE DLL library to load +shared - True to load module into shared memory + +RETURNS: +Handle to loaded PE DLL, or NULL on failure. + +REMARKS: +This function is the same as the regular PE_loadLibrary function, except +that it looks for the drivers in the MGL_ROOT/drivers directory or a +/drivers directory relative to the current directory. + +SEE ALSO: +PE_loadLibraryMGL, PE_getProcAddress, PE_freeLibrary +****************************************************************************/ +PE_MODULE * PEAPI PE_loadLibraryMGL( + const char *szDLLName, + ibool shared) +{ +#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) + PE_MODULE *hMod; +#endif + char path[256] = ""; + + /* We look in the 'drivers' directory, optionally under the MGL_ROOT + * environment variable directory. + */ +#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) + if (getenv("MGL_ROOT")) { + strcpy(path,getenv("MGL_ROOT")); + PM_backslash(path); + } + strcat(path,"drivers"); + PM_backslash(path); + strcat(path,szDLLName); + if ((hMod = PE_loadLibrary(path,shared)) != NULL) + return hMod; +#endif + strcpy(path,"drivers"); + PM_backslash(path); + strcat(path,szDLLName); + return PE_loadLibrary(path,shared); +} + +/**************************************************************************** +DESCRIPTION: +Gets a function address from a Portable Binary DLL + +HEADER: +peloader.h + +PARAMETERS: +hModule - Handle to a loaded PE DLL library +szProcName - Name of the function to get the address of + +RETURNS: +Pointer to the function, or NULL on failure. + +REMARKS: +This function searches for the named, exported function in a loaded PE +DLL library, and returns the address of the function. If the function is +not found in the library, this function return NULL. + +SEE ALSO: +PE_loadLibrary, PE_freeLibrary +****************************************************************************/ +void * PEAPI PE_getProcAddress( + PE_MODULE *hModule, + const char *szProcName) +{ +#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) + if (hModule->shared == -1) + return (void*)PM_getProcAddress(hModule->text,szProcName); + else +#endif + { + uint i; + EXPORT_DIRECTORY *exports; + ulong funcOffset; + ulong *AddressTable; + ulong *NameTable; + ushort *OrdinalTable; + char *name; + + /* Find the address of the export tables from the export section */ + if (!hModule) + return NULL; + exports = (EXPORT_DIRECTORY*)(hModule->export + hModule->exportDir); + AddressTable = (ulong*)(hModule->export + exports->AddressTableRVA - hModule->exportBase); + NameTable = (ulong*)(hModule->export + exports->NameTableRVA - hModule->exportBase); + OrdinalTable = (ushort*)(hModule->export + exports->OrdinalTableRVA - hModule->exportBase); + + /* Search the export name table to find the function name */ + for (i = 0; i < exports->NumberOfNamePointers; i++) { + name = (char*)(hModule->export + NameTable[i] - hModule->exportBase); + if (strcmp(name,szProcName) == 0) + break; + } + if (i == exports->NumberOfNamePointers) + return NULL; + funcOffset = AddressTable[OrdinalTable[i]]; + if (!funcOffset) + return NULL; + return (void*)(hModule->text + funcOffset - hModule->textBase); + } +} + +/**************************************************************************** +DESCRIPTION: +Frees a loaded Portable Binary DLL + +HEADER: +peloader.h + +PARAMETERS: +hModule - Handle to a loaded PE DLL library to free + +REMARKS: +This function frees a loaded PE DLL library from memory. + +SEE ALSO: +PE_getProcAddress, PE_loadLibrary +****************************************************************************/ +void PEAPI PE_freeLibrary( + PE_MODULE *hModule) +{ + TerminateLibC_t TerminateLibC; + +#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) + if (hModule->shared == -1) { + /* Run the C runtime library exit code on module unload */ + if ((TerminateLibC = (TerminateLibC_t)PM_getProcAddress(hModule->text,"_TerminateLibC")) != NULL) + TerminateLibC(); + PM_freeLibrary(hModule->text); + PM_free(hModule); + } + else +#endif + { + if (hModule) { + /* Run the C runtime library exit code on module unload */ + if ((TerminateLibC = (TerminateLibC_t)PE_getProcAddress(hModule,"_TerminateLibC")) != NULL) + TerminateLibC(); + if (hModule->shared) + PM_freeShared(hModule); + else + PM_free(hModule); + } + } +} + +/**************************************************************************** +DESCRIPTION: +Returns the error code for the last operation + +HEADER: +peloader.h + +RETURNS: +Error code for the last operation. + +SEE ALSO: +PE_getProcAddress, PE_loadLibrary +****************************************************************************/ +int PEAPI PE_getError(void) +{ + return result; +} diff --git a/board/MAI/bios_emulator/scitech/src/common/vesavbe.c b/board/MAI/bios_emulator/scitech/src/common/vesavbe.c new file mode 100644 index 0000000..a669e5c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/vesavbe.c @@ -0,0 +1,1214 @@ +/**************************************************************************** +* +* The SuperVGA Kit - UniVBE Software Development Kit +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: IBM PC Real Mode and 16/32 bit Protected Mode. +* +* Description: Module to implement a C callable interface to the standard +* VESA VBE routines. You should rip out this module and use it +* directly in your own applications, or you can use the +* high level SDK functions. +* +* MUST be compiled in the LARGE or FLAT models. +* +****************************************************************************/ + +#include +#include +#include +#include "vesavbe.h" +#include "pmapi.h" +#include "drvlib/os/os.h" + +/*---------------------------- Global Variables ---------------------------*/ + +#define VBE_SUCCESS 0x004F +#define MAX_LIN_PTRS 10 + +static uint VESABuf_len = 1024;/* Length of the VESABuf buffer */ +static ibool haveRiva128; /* True if we have a Riva128 */ +static VBE_state defState = {0}; /* Default state buffer */ +static VBE_state *state = &defState; /* Pointer to current buffer */ +static int VBE_shared = 0; +#ifndef REALMODE +static char localBuf[512]; /* Global PM string translate buf */ +#define MAX_LOCAL_BUF &localBuf[511] +#endif + +/*----------------------------- Implementation ----------------------------*/ + +/* static function in WinDirect for passing 32-bit registers to BIOS */ +int PMAPI WD_int386(int intno, RMREGS *in, RMREGS *out); + +void VBEAPI VBE_init(void) +/**************************************************************************** +* +* Function: VBE_init +* +* Description: Initialises the VBE transfer buffer in real mode DC.memory. +* This routine is called by the VESAVBE module every time +* it needs to use the transfer buffer, so we simply allocate +* it once and then return. +* +****************************************************************************/ +{ + if (!state->VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((state->VESABuf_ptr = PM_getVESABuf(&VESABuf_len, &state->VESABuf_rseg, &state->VESABuf_roff)) == NULL) + PM_fatalError("VESAVBE.C: Real mode memory allocation failed!"); + } +} + +void * VBEAPI VBE_getRMBuf(uint *len,uint *rseg,uint *roff) +/**************************************************************************** +* +* Function: VBE_getRMBuf +* +* Description: This function returns the location and length of the real +* mode memory buffer for calling real mode functions. +* +****************************************************************************/ +{ + *len = VESABuf_len; + *rseg = state->VESABuf_rseg; + *roff = state->VESABuf_roff; + return state->VESABuf_ptr; +} + +void VBEAPI VBE_setStateBuffer(VBE_state *s) +/**************************************************************************** +* +* Function: VBE_setStateBuffer +* +* Description: This functions sets the internal state buffer for the +* VBE module to the passed in buffer. By default the internal +* global buffer is used, but you must use separate buffers +* for each device in a multi-controller environment. +* +****************************************************************************/ +{ + state = s; +} + +void VBEAPI VBE_callESDI(RMREGS *regs, void *buffer, int size) +/**************************************************************************** +* +* Function: VBE_callESDI +* Parameters: regs - Registers to load when calling VBE +* buffer - Buffer to copy VBE info block to +* size - Size of buffer to fill +* +* Description: Calls the VESA VBE and passes in a buffer for the VBE to +* store information in, which is then copied into the users +* buffer space. This works in protected mode as the buffer +* passed to the VESA VBE is allocated in conventional +* memory, and is then copied into the users memory block. +* +****************************************************************************/ +{ + RMSREGS sregs; + + if (!state->VESABuf_ptr) + PM_fatalError("You *MUST* call VBE_init() before you can call the VESAVBE.C module!"); + sregs.es = (ushort)state->VESABuf_rseg; + regs->x.di = (ushort)state->VESABuf_roff; + memcpy(state->VESABuf_ptr, buffer, size); + PM_int86x(0x10, regs, regs, &sregs); + memcpy(buffer, state->VESABuf_ptr, size); +} + +#ifndef REALMODE +static char *VBE_copyStrToLocal(char *p,char *realPtr,char *max) +/**************************************************************************** +* +* Function: VBE_copyStrToLocal +* Parameters: p - Flat model buffer to copy to +* realPtr - Real mode pointer to copy +* Returns: Pointer to the next byte after string +* +* Description: Copies the string from the real mode location pointed to +* by 'realPtr' into the flat model buffer pointed to by +* 'p'. We return a pointer to the next byte past the copied +* string. +* +****************************************************************************/ +{ + uchar *v; + + v = PM_mapRealPointer((uint)((ulong)realPtr >> 16), (uint)((ulong)realPtr & 0xFFFF)); + while (*v != 0 && p < max) + *p++ = *v++; + *p++ = 0; + return p; +} + +static void VBE_copyShortToLocal(ushort *p,ushort *realPtr) +/**************************************************************************** +* +* Function: VBE_copyShortToLocal +* Parameters: p - Flat model buffer to copy to +* realPtr - Real mode pointer to copy +* +* Description: Copies the mode table from real mode memory to the flat +* model buffer. +* +****************************************************************************/ +{ + ushort *v; + + v = PM_mapRealPointer((uint)((ulong)realPtr >> 16),(uint)((ulong)realPtr & 0xFFFF)); + while (*v != 0xFFFF) + *p++ = *v++; + *p = 0xFFFF; +} +#endif + +int VBEAPI VBE_detectEXT(VBE_vgaInfo *vgaInfo,ibool forceUniVBE) +/**************************************************************************** +* +* Function: VBE_detect +* Parameters: vgaInfo - Place to store the VGA information block +* Returns: VBE version number, or 0 if not detected. +* +* Description: Detects if a VESA VBE is out there and functioning +* correctly. If we detect a VBE interface we return the +* VGAInfoBlock returned by the VBE and the VBE version number. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F00; /* Get SuperVGA information */ + if (forceUniVBE) { + regs.x.bx = 0x1234; + regs.x.cx = 0x4321; + } + else { + regs.x.bx = 0; + regs.x.cx = 0; + } + strncpy(vgaInfo->VESASignature,"VBE2",4); + VBE_callESDI(®s, vgaInfo, sizeof(*vgaInfo)); + if (regs.x.ax != VBE_SUCCESS) + return 0; + if (strncmp(vgaInfo->VESASignature,"VESA",4) != 0) + return 0; + + /* Check for bogus BIOSes that return a VBE version number that is + * not correct, and fix it up. We also check the OemVendorNamePtr for a + * valid value, and if it is invalid then we also reset to VBE 1.2. + */ + if (vgaInfo->VESAVersion >= 0x200 && vgaInfo->OemVendorNamePtr == 0) + vgaInfo->VESAVersion = 0x102; +#ifndef REALMODE + /* Relocate all the indirect information (mode tables, OEM strings + * etc) from the low 1Mb memory region into a static buffer in + * our default data segment. We do this to insulate the application + * from mapping the strings from real mode to protected mode. + */ + { + char *p,*p2; + p2 = VBE_copyStrToLocal(localBuf,vgaInfo->OemStringPtr,MAX_LOCAL_BUF); + vgaInfo->OemStringPtr = localBuf; + if (vgaInfo->VESAVersion >= 0x200) { + p = VBE_copyStrToLocal(p2,vgaInfo->OemVendorNamePtr,MAX_LOCAL_BUF); + vgaInfo->OemVendorNamePtr = p2; + p2 = VBE_copyStrToLocal(p,vgaInfo->OemProductNamePtr,MAX_LOCAL_BUF); + vgaInfo->OemProductNamePtr = p; + p = VBE_copyStrToLocal(p2,vgaInfo->OemProductRevPtr,MAX_LOCAL_BUF); + vgaInfo->OemProductRevPtr = p2; + VBE_copyShortToLocal((ushort*)p,vgaInfo->VideoModePtr); + vgaInfo->VideoModePtr = (ushort*)p; + } + else { + VBE_copyShortToLocal((ushort*)p2,vgaInfo->VideoModePtr); + vgaInfo->VideoModePtr = (ushort*)p2; + } + } +#endif + state->VBEMemory = vgaInfo->TotalMemory * 64; + + /* Check for Riva128 based cards since they have broken triple buffering + * and stereo support. + */ + haveRiva128 = false; + if (vgaInfo->VESAVersion >= 0x300 && + (strstr(vgaInfo->OemStringPtr,"NVidia") != NULL || + strstr(vgaInfo->OemStringPtr,"Riva") != NULL)) { + haveRiva128 = true; + } + + /* Check for Matrox G400 cards which claim to be VBE 3.0 + * compliant yet they don't implement the refresh rate control + * functions. + */ + if (vgaInfo->VESAVersion >= 0x300 && (strcmp(vgaInfo->OemProductNamePtr,"Matrox G400") == 0)) + vgaInfo->VESAVersion = 0x200; + return (state->VBEVersion = vgaInfo->VESAVersion); +} + +int VBEAPI VBE_detect(VBE_vgaInfo *vgaInfo) +/**************************************************************************** +* +* Function: VBE_detect +* Parameters: vgaInfo - Place to store the VGA information block +* Returns: VBE version number, or 0 if not detected. +* +* Description: Detects if a VESA VBE is out there and functioning +* correctly. If we detect a VBE interface we return the +* VGAInfoBlock returned by the VBE and the VBE version number. +* +****************************************************************************/ +{ + return VBE_detectEXT(vgaInfo,false); +} + +ibool VBEAPI VBE_getModeInfo(int mode,VBE_modeInfo *modeInfo) +/**************************************************************************** +* +* Function: VBE_getModeInfo +* Parameters: mode - VBE mode to get information for +* modeInfo - Place to store VBE mode information +* Returns: True on success, false if function failed. +* +* Description: Obtains information about a specific video mode from the +* VBE. You should use this function to find the video mode +* you wish to set, as the new VBE 2.0 mode numbers may be +* completely arbitrary. +* +****************************************************************************/ +{ + RMREGS regs; + int bits; + + regs.x.ax = 0x4F01; /* Get mode information */ + regs.x.cx = (ushort)mode; + VBE_callESDI(®s, modeInfo, sizeof(*modeInfo)); + if (regs.x.ax != VBE_SUCCESS) + return false; + if ((modeInfo->ModeAttributes & vbeMdAvailable) == 0) + return false; + + /* Map out triple buffer and stereo flags for NVidia Riva128 + * chips. + */ + if (haveRiva128) { + modeInfo->ModeAttributes &= ~vbeMdTripleBuf; + modeInfo->ModeAttributes &= ~vbeMdStereo; + } + + /* Support old style RGB definitions for VBE 1.1 BIOSes */ + bits = modeInfo->BitsPerPixel; + if (modeInfo->MemoryModel == vbeMemPK && bits > 8) { + modeInfo->MemoryModel = vbeMemRGB; + switch (bits) { + case 15: + modeInfo->RedMaskSize = 5; + modeInfo->RedFieldPosition = 10; + modeInfo->GreenMaskSize = 5; + modeInfo->GreenFieldPosition = 5; + modeInfo->BlueMaskSize = 5; + modeInfo->BlueFieldPosition = 0; + modeInfo->RsvdMaskSize = 1; + modeInfo->RsvdFieldPosition = 15; + break; + case 16: + modeInfo->RedMaskSize = 5; + modeInfo->RedFieldPosition = 11; + modeInfo->GreenMaskSize = 5; + modeInfo->GreenFieldPosition = 5; + modeInfo->BlueMaskSize = 5; + modeInfo->BlueFieldPosition = 0; + modeInfo->RsvdMaskSize = 0; + modeInfo->RsvdFieldPosition = 0; + break; + case 24: + modeInfo->RedMaskSize = 8; + modeInfo->RedFieldPosition = 16; + modeInfo->GreenMaskSize = 8; + modeInfo->GreenFieldPosition = 8; + modeInfo->BlueMaskSize = 8; + modeInfo->BlueFieldPosition = 0; + modeInfo->RsvdMaskSize = 0; + modeInfo->RsvdFieldPosition = 0; + break; + } + } + + /* Convert the 32k direct color modes of VBE 1.2+ BIOSes to + * be recognised as 15 bits per pixel modes. + */ + if (bits == 16 && modeInfo->RsvdMaskSize == 1) + modeInfo->BitsPerPixel = 15; + + /* Fix up bogus BIOS'es that report incorrect reserved pixel masks + * for 32K color modes. Quite a number of BIOS'es have this problem, + * and this affects our OS/2 drivers in VBE fallback mode. + */ + if (bits == 15 && (modeInfo->RsvdMaskSize != 1 || modeInfo->RsvdFieldPosition != 15)) { + modeInfo->RsvdMaskSize = 1; + modeInfo->RsvdFieldPosition = 15; + } + return true; +} + +long VBEAPI VBE_getPageSize(VBE_modeInfo *mi) +/**************************************************************************** +* +* Function: VBE_getPageSize +* Parameters: mi - Pointer to mode information block +* Returns: Caculated page size in bytes rounded to correct boundary +* +* Description: Computes the page size in bytes for the specified mode +* information block, rounded up to the appropriate boundary +* (8k, 16k, 32k or 64k). Pages >= 64k in size are always +* rounded to the nearest 64k boundary (so the start of a +* page is always bank aligned). +* +****************************************************************************/ +{ + long size; + + size = (long)mi->BytesPerScanLine * (long)mi->YResolution; + if (mi->BitsPerPixel == 4) { + /* We have a 16 color video mode, so round up the page size to + * 8k, 16k, 32k or 64k boundaries depending on how large it is. + */ + + size = (size + 0x1FFFL) & 0xFFFFE000L; + if (size != 0x2000) { + size = (size + 0x3FFFL) & 0xFFFFC000L; + if (size != 0x4000) { + size = (size + 0x7FFFL) & 0xFFFF8000L; + if (size != 0x8000) + size = (size + 0xFFFFL) & 0xFFFF0000L; + } + } + } + else size = (size + 0xFFFFL) & 0xFFFF0000L; + return size; +} + +ibool VBEAPI VBE_setVideoModeExt(int mode,VBE_CRTCInfo *crtc) +/**************************************************************************** +* +* Function: VBE_setVideoModeExt +* Parameters: mode - SuperVGA video mode to set. +* Returns: True if the mode was set, false if not. +* +* Description: Attempts to set the specified video mode. This version +* includes support for the VBE/Core 3.0 refresh rate control +* mechanism. +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion < 0x200 && mode < 0x100) { + /* Some VBE implementations barf terribly if you try to set non-VBE + * video modes with the VBE set mode call. VBE 2.0 implementations + * must be able to handle this. + */ + regs.h.al = (ushort)mode; + regs.h.ah = 0; + PM_int86(0x10,®s,®s); + } + else { + if (state->VBEVersion < 0x300 && (mode & vbeRefreshCtrl)) + return false; + regs.x.ax = 0x4F02; + regs.x.bx = (ushort)mode; + if ((mode & vbeRefreshCtrl) && crtc) + VBE_callESDI(®s, crtc, sizeof(*crtc)); + else + PM_int86(0x10,®s,®s); + if (regs.x.ax != VBE_SUCCESS) + return false; + } + return true; +} + +ibool VBEAPI VBE_setVideoMode(int mode) +/**************************************************************************** +* +* Function: VBE_setVideoMode +* Parameters: mode - SuperVGA video mode to set. +* Returns: True if the mode was set, false if not. +* +* Description: Attempts to set the specified video mode. +* +****************************************************************************/ +{ + return VBE_setVideoModeExt(mode,NULL); +} + +int VBEAPI VBE_getVideoMode(void) +/**************************************************************************** +* +* Function: VBE_getVideoMode +* Returns: Current video mode +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F03; + PM_int86(0x10,®s,®s); + if (regs.x.ax != VBE_SUCCESS) + return -1; + return regs.x.bx; +} + +ibool VBEAPI VBE_setBank(int window,int bank) +/**************************************************************************** +* +* Function: VBE_setBank +* Parameters: window - Window to set +* bank - Bank number to set window to +* Returns: True on success, false on failure. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F05; + regs.h.bh = 0; + regs.h.bl = window; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; +} + +int VBEAPI VBE_getBank(int window) +/**************************************************************************** +* +* Function: VBE_setBank +* Parameters: window - Window to read +* Returns: Bank number for the window (-1 on failure) +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F05; + regs.h.bh = 1; + regs.h.bl = window; + PM_int86(0x10,®s,®s); + if (regs.x.ax != VBE_SUCCESS) + return -1; + return regs.x.dx; +} + +ibool VBEAPI VBE_setPixelsPerLine(int pixelsPerLine,int *newBytes, + int *newPixels,int *maxScanlines) +/**************************************************************************** +* +* Function: VBE_setPixelsPerLine +* Parameters: pixelsPerLine - Pixels per scanline +* newBytes - Storage for bytes per line value set +* newPixels - Storage for pixels per line value set +* maxScanLines - Storage for maximum number of scanlines +* Returns: True on success, false on failure +* +* Description: Sets the scanline length for the video mode to the specified +* number of pixels per scanline. If you need more granularity +* in TrueColor modes, use the VBE_setBytesPerLine routine +* (only valid for VBE 2.0). +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F06; + regs.h.bl = 0; + regs.x.cx = pixelsPerLine; + PM_int86(0x10,®s,®s); + *newBytes = regs.x.bx; + *newPixels = regs.x.cx; + *maxScanlines = regs.x.dx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_setBytesPerLine(int bytesPerLine,int *newBytes, + int *newPixels,int *maxScanlines) +/**************************************************************************** +* +* Function: VBE_setBytesPerLine +* Parameters: pixelsPerLine - Pixels per scanline +* newBytes - Storage for bytes per line value set +* newPixels - Storage for pixels per line value set +* maxScanLines - Storage for maximum number of scanlines +* Returns: True on success, false on failure +* +* Description: Sets the scanline length for the video mode to the specified +* number of bytes per scanline (valid for VBE 2.0 only). +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F06; + regs.h.bl = 2; + regs.x.cx = bytesPerLine; + PM_int86(0x10,®s,®s); + *newBytes = regs.x.bx; + *newPixels = regs.x.cx; + *maxScanlines = regs.x.dx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_getScanlineLength(int *bytesPerLine,int *pixelsPerLine, + int *maxScanlines) +/**************************************************************************** +* +* Function: VBE_getScanlineLength +* Parameters: bytesPerLine - Storage for bytes per scanline +* pixelsPerLine - Storage for pixels per scanline +* maxScanLines - Storage for maximum number of scanlines +* Returns: True on success, false on failure +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F06; + regs.h.bl = 1; + PM_int86(0x10,®s,®s); + *bytesPerLine = regs.x.bx; + *pixelsPerLine = regs.x.cx; + *maxScanlines = regs.x.dx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_getMaxScanlineLength(int *maxBytes,int *maxPixels) +/**************************************************************************** +* +* Function: VBE_getMaxScanlineLength +* Parameters: maxBytes - Maximum scanline width in bytes +* maxPixels - Maximum scanline width in pixels +* Returns: True if successful, false if function failed +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F06; + regs.h.bl = 3; + PM_int86(0x10,®s,®s); + *maxBytes = regs.x.bx; + *maxPixels = regs.x.cx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_setDisplayStart(int x,int y,ibool waitVRT) +/**************************************************************************** +* +* Function: VBE_setDisplayStart +* Parameters: x,y - Position of the first pixel to display +* waitVRT - True to wait for retrace, false if not +* Returns: True if function was successful. +* +* Description: Sets the new starting display position to implement +* hardware scrolling. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F07; + if (waitVRT) + regs.x.bx = 0x80; + else regs.x.bx = 0x00; + regs.x.cx = x; + regs.x.dx = y; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_getDisplayStart(int *x,int *y) +/**************************************************************************** +* +* Function: VBE_getDisplayStart +* Parameters: x,y - Place to store starting address value +* Returns: True if function was successful. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F07; + regs.x.bx = 0x01; + PM_int86(0x10,®s,®s); + *x = regs.x.cx; + *y = regs.x.dx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_setDisplayStartAlt(ulong startAddr,ibool waitVRT) +/**************************************************************************** +* +* Function: VBE_setDisplayStartAlt +* Parameters: startAddr - 32-bit starting address in display memory +* waitVRT - True to wait for vertical retrace, false if not +* Returns: True if function was successful, false if not supported. +* +* Description: Sets the new starting display position to the specified +* 32-bit display start address. Note that this function is +* different the the version above, since it takes a 32-bit +* byte offset in video memory as the starting address which +* gives the programmer maximum control over the stat address. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = waitVRT ? 0x82 : 0x02; + regs.e.ecx = startAddr; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; + } + return false; +} + +int VBEAPI VBE_getDisplayStartStatus(void) +/**************************************************************************** +* +* Function: VBE_getDisplayStartStatus +* Returns: 0 if last flip not occurred, 1 if already flipped +* -1 if not supported +* +* Description: Returns the status of the previous display start request. +* If this function is supported the programmer can implement +* hardware triple buffering using this function. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = 0x0004; + PM_int86(0x10,®s,®s); + if (regs.x.ax == VBE_SUCCESS) + return (regs.x.cx != 0); + } + return -1; +} + +ibool VBEAPI VBE_enableStereoMode(void) +/**************************************************************************** +* +* Function: VBE_enableStereoMode +* Returns: True if stereo mode enabled, false if not supported. +* +* Description: Puts the system into hardware stereo mode for LC shutter +* glasses, where the display swaps between two display start +* addresses every vertical retrace. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = 0x0005; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; + } + return false; +} + +ibool VBEAPI VBE_disableStereoMode(void) +/**************************************************************************** +* +* Function: VBE_disableStereoMode +* Returns: True if stereo mode disabled, false if not supported. +* +* Description: Puts the system back into normal, non-stereo display mode +* after having stereo mode enabled. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = 0x0006; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; + } + return false; +} + +ibool VBEAPI VBE_setStereoDisplayStart(ulong leftAddr,ulong rightAddr, + ibool waitVRT) +/**************************************************************************** +* +* Function: VBE_setStereoDisplayStart +* Parameters: leftAddr - 32-bit start address for left image +* rightAddr - 32-bit start address for right image +* waitVRT - True to wait for vertical retrace, false if not +* Returns: True if function was successful, false if not supported. +* +* Description: Sets the new starting display position to the specified +* 32-bit display start address. Note that this function is +* different the the version above, since it takes a 32-bit +* byte offset in video memory as the starting address which +* gives the programmer maximum control over the stat address. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = waitVRT ? 0x83 : 0x03; + regs.e.ecx = leftAddr; + regs.e.edx = rightAddr; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; + } + return false; +} + +ulong VBEAPI VBE_getClosestClock(ushort mode,ulong pixelClock) +/**************************************************************************** +* +* Function: VBE_getClosestClock +* Parameters: mode - VBE mode to be used (include vbeLinearBuffer) +* pixelClock - Desired pixel clock +* Returns: Closest pixel clock to desired clock (-1 if not supported) +* +* Description: Calls the VBE/Core 3.0 interface to determine the closest +* pixel clock to the requested value. The BIOS will always +* search for a pixel clock that is no more than 1% below the +* requested clock or somewhere higher than the clock. If the +* clock is higher note that it may well be many Mhz higher +* that requested and the application will have to check that +* the returned value is suitable for it's needs. This function +* returns the actual pixel clock that will be programmed by +* the hardware. +* +* Note that if the pixel clock will be used with a linear +* framebuffer mode, make sure you pass in the linear +* framebuffer flag to this function. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F0B; + regs.h.bl = 0x00; + regs.e.ecx = pixelClock; + regs.x.dx = mode; + PM_int86(0x10,®s,®s); + if (regs.x.ax == VBE_SUCCESS) + return regs.e.ecx; + } + return -1; +} + +ibool VBEAPI VBE_setDACWidth(int width) +/**************************************************************************** +* +* Function: VBE_setDACWidth +* Parameters: width - Width to set the DAC to +* Returns: True on success, false on failure +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F08; + regs.h.bl = 0x00; + regs.h.bh = width; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; +} + +int VBEAPI VBE_getDACWidth(void) +/**************************************************************************** +* +* Function: VBE_getDACWidth +* Returns: Current width of the palette DAC +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F08; + regs.h.bl = 0x01; + PM_int86(0x10,®s,®s); + if (regs.x.ax != VBE_SUCCESS) + return -1; + return regs.h.bh; +} + +ibool VBEAPI VBE_setPalette(int start,int num,VBE_palette *pal,ibool waitVRT) +/**************************************************************************** +* +* Function: VBE_setPalette +* Parameters: start - Starting palette index to program +* num - Number of palette indexes to program +* pal - Palette buffer containing values +* waitVRT - Wait for vertical retrace flag +* Returns: True on success, false on failure +* +* Description: Sets a block of palette registers by calling the VBE 2.0 +* BIOS. This function will fail on VBE 1.2 implementations. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F09; + regs.h.bl = waitVRT ? 0x80 : 0x00; + regs.x.cx = num; + regs.x.dx = start; + VBE_callESDI(®s, pal, sizeof(VBE_palette) * num); + return regs.x.ax == VBE_SUCCESS; +} + +void * VBEAPI VBE_getBankedPointer(VBE_modeInfo *modeInfo) +/**************************************************************************** +* +* Function: VBE_getBankedPointer +* Parameters: modeInfo - Mode info block for video mode +* Returns: Selector to the linear framebuffer (0 on failure) +* +* Description: Returns a near pointer to the VGA framebuffer area. +* +****************************************************************************/ +{ + /* We just map the pointer every time, since the pointer will always + * be in real mode memory, so we wont actually be mapping any real + * memory. + * + * NOTE: We cannot currently map a near pointer to the banked frame + * buffer for Watcom Win386, so we create a 16:16 far pointer to + * the video memory. All the assembler code will render to the + * video memory by loading the selector rather than using a + * near pointer. + */ + ulong seg = (ushort)modeInfo->WinASegment; + if (seg != 0) { + if (seg == 0xA000) + return (void*)PM_getA0000Pointer(); + else + return (void*)PM_mapPhysicalAddr(seg << 4,0xFFFF,true); + } + return NULL; +} + +#ifndef REALMODE + +void * VBEAPI VBE_getLinearPointer(VBE_modeInfo *modeInfo) +/**************************************************************************** +* +* Function: VBE_getLinearPointer +* Parameters: modeInfo - Mode info block for video mode +* Returns: Selector to the linear framebuffer (0 on failure) +* +* Description: Returns a near pointer to the linear framebuffer for the video +* mode. +* +****************************************************************************/ +{ + static ulong physPtr[MAX_LIN_PTRS] = {0}; + static void *linPtr[MAX_LIN_PTRS] = {0}; + static int numPtrs = 0; + int i; + + /* Search for an already mapped pointer */ + for (i = 0; i < numPtrs; i++) { + if (physPtr[i] == modeInfo->PhysBasePtr) + return linPtr[i]; + } + if (numPtrs < MAX_LIN_PTRS) { + physPtr[numPtrs] = modeInfo->PhysBasePtr; + linPtr[numPtrs] = PM_mapPhysicalAddr(modeInfo->PhysBasePtr,(state->VBEMemory * 1024L)-1,true); + return linPtr[numPtrs++]; + } + return NULL; +} + +static void InitPMCode(void) +/**************************************************************************** +* +* Function: InitPMCode - 32 bit protected mode version +* +* Description: Finds the address of and relocates the protected mode +* code block from the VBE 2.0 into a local memory block. The +* memory block is allocated with malloc() and must be freed +* with VBE_freePMCode() after graphics processing is complete. +* +* Note that this buffer _must_ be recopied after each mode set, +* as the routines will change depending on the underlying +* video mode. +* +****************************************************************************/ +{ + RMREGS regs; + RMSREGS sregs; + uchar *code; + int pmLen; + + if (!state->pmInfo && state->VBEVersion >= 0x200) { + regs.x.ax = 0x4F0A; + regs.x.bx = 0; + PM_int86x(0x10,®s,®s,&sregs); + if (regs.x.ax != VBE_SUCCESS) + return; + if (VBE_shared) + state->pmInfo = PM_mallocShared(regs.x.cx); + else + state->pmInfo = PM_malloc(regs.x.cx); + if (state->pmInfo == NULL) + return; + state->pmInfo32 = state->pmInfo; + pmLen = regs.x.cx; + + /* Relocate the block into our local data segment */ + code = PM_mapRealPointer(sregs.es,regs.x.di); + memcpy(state->pmInfo,code,pmLen); + + /* Now do a sanity check on the information we recieve to ensure + * that is is correct. Some BIOS return totally bogus information + * in here (Matrox is one)! Under DOS this works OK, but under OS/2 + * we are screwed. + */ + if (state->pmInfo->setWindow >= pmLen || + state->pmInfo->setDisplayStart >= pmLen || + state->pmInfo->setPalette >= pmLen || + state->pmInfo->IOPrivInfo >= pmLen) { + if (VBE_shared) + PM_freeShared(state->pmInfo); + else + PM_free(state->pmInfo); + state->pmInfo32 = state->pmInfo = NULL; + return; + } + + /* Read the IO priveledge info and determine if we need to + * pass a selector to MMIO registers to the bank switch code. + * Since we no longer support selector allocation, we no longer + * support this mechanism so we disable the protected mode + * interface in this case. + */ + if (state->pmInfo->IOPrivInfo && !state->MMIOSel) { + ushort *p = (ushort*)((uchar*)state->pmInfo + state->pmInfo->IOPrivInfo); + while (*p != 0xFFFF) + p++; + p++; + if (*p != 0xFFFF) + VBE_freePMCode(); + } + } +} + +void * VBEAPI VBE_getSetBank(void) +/**************************************************************************** +* +* Function: VBE_getSetBank +* Returns: Pointer to the 32 VBE 2.0 bit bank switching routine. +* +****************************************************************************/ +{ + if (state->VBEVersion >= 0x200) { + InitPMCode(); + if (state->pmInfo) + return (uchar*)state->pmInfo + state->pmInfo->setWindow; + } + return NULL; +} + +void * VBEAPI VBE_getSetDisplayStart(void) +/**************************************************************************** +* +* Function: VBE_getSetDisplayStart +* Returns: Pointer to the 32 VBE 2.0 bit CRT start address routine. +* +****************************************************************************/ +{ + if (state->VBEVersion >= 0x200) { + InitPMCode(); + if (state->pmInfo) + return (uchar*)state->pmInfo + state->pmInfo->setDisplayStart; + } + return NULL; +} + +void * VBEAPI VBE_getSetPalette(void) +/**************************************************************************** +* +* Function: VBE_getSetPalette +* Returns: Pointer to the 32 VBE 2.0 bit palette programming routine. +* +****************************************************************************/ +{ + if (state->VBEVersion >= 0x200) { + InitPMCode(); + if (state->pmInfo) + return (uchar*)state->pmInfo + state->pmInfo->setPalette; + } + return NULL; +} + +void VBEAPI VBE_freePMCode(void) +/**************************************************************************** +* +* Function: VBE_freePMCode +* +* Description: This routine frees the protected mode code blocks that +* we copied from the VBE 2.0 interface. This routine must +* be after you have finished graphics processing to free up +* the memory occupied by the routines. This is necessary +* because the PM info memory block must be re-copied after +* every video mode set from the VBE 2.0 implementation. +* +****************************************************************************/ +{ + if (state->pmInfo) { + if (VBE_shared) + PM_freeShared(state->pmInfo); + else + PM_free(state->pmInfo); + state->pmInfo = NULL; + state->pmInfo32 = NULL; + } +} + +void VBEAPI VBE_sharePMCode(void) +/**************************************************************************** +* +* Function: VBE_sharePMCode +* +* Description: Enables internal sharing of the PM code buffer for OS/2. +* +****************************************************************************/ +{ + VBE_shared = true; +} + +/* Set of code stubs used to build the final bank switch code */ + +#define VBE20_adjustOffset 7 + +static uchar VBE20A_bankFunc32_Start[] = { + 0x53,0x51, /* push ebx,ecx */ + 0x8B,0xD0, /* mov edx,eax */ + 0x33,0xDB, /* xor ebx,ebx */ + 0xB1,0x00, /* mov cl,0 */ + 0xD2,0xE2, /* shl dl,cl */ + }; + +static uchar VBE20_bankFunc32_End[] = { + 0x59,0x5B, /* pop ecx,ebx */ + }; + +static uchar bankFunc32[100]; + +#define copy(p,b,a) memcpy(b,a,sizeof(a)); (p) = (b) + sizeof(a) + +ibool VBEAPI VBE_getBankFunc32(int *codeLen,void **bankFunc,int dualBanks, + int bankAdjust) +/**************************************************************************** +* +* Function: VBE_getBankFunc32 +* Parameters: codeLen - Place to store length of code +* bankFunc - Place to store pointer to bank switch code +* dualBanks - True if dual banks are in effect +* bankAdjust - Bank shift adjustment factor +* Returns: True on success, false if not compatible. +* +* Description: Creates a local 32 bit bank switch function from the +* VBE 2.0 bank switch code that is compatible with the +* virtual flat framebuffer devices (does not have a return +* instruction at the end and takes the bank number in EAX +* not EDX). Note that this 32 bit code cannot include int 10h +* instructions, so we can only do this if we have VBE 2.0 +* or later. +* +* Note that we need to know the length of the 32 bit +* bank switch function, which the standard VBE 2.0 spec +* does not provide. In order to support this we have +* extended the VBE 2.0 state->pmInfo structure in UniVBE 5.2 in a +* way to support this, and we hope that this will become +* a VBE 2.0 ammendment. +* +* Note also that we cannot run the linear framebuffer +* emulation code with bank switching routines that require +* a selector to the memory mapped registers passed in ES. +* +****************************************************************************/ +{ + int len; + uchar *code; + uchar *p; + + InitPMCode(); + if (state->VBEVersion >= 0x200 && state->pmInfo32 && !state->MMIOSel) { + code = (uchar*)state->pmInfo32 + state->pmInfo32->setWindow; + if (state->pmInfo32->extensionSig == VBE20_EXT_SIG) + len = state->pmInfo32->setWindowLen-1; + else { + /* We are running on a system without the UniVBE 5.2 extension. + * We do as best we can by scanning through the code for the + * ret function to determine the length. This is not foolproof, + * but is the best we can do. + */ + p = code; + while (*p != 0xC3) + p++; + len = p - code; + } + if ((len + sizeof(VBE20A_bankFunc32_Start) + sizeof(VBE20_bankFunc32_End)) > sizeof(bankFunc32)) + PM_fatalError("32-bit bank switch function too long!"); + copy(p,bankFunc32,VBE20A_bankFunc32_Start); + memcpy(p,code,len); + p += len; + copy(p,p,VBE20_bankFunc32_End); + *codeLen = p - bankFunc32; + bankFunc32[VBE20_adjustOffset] = (uchar)bankAdjust; + *bankFunc = bankFunc32; + return true; + } + return false; +} + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c new file mode 100644 index 0000000..cb3afe2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c @@ -0,0 +1,80 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: Module to implement OS specific services to measure the +* CPU frequency. +* +****************************************************************************/ + +#include + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Increase the thread priority to maximum, if possible. +****************************************************************************/ +static int SetMaxThreadPriority(void) +{ + thread_id thid = find_thread(NULL); + thread_info tinfo; + get_thread_info(thid, &tinfo); + set_thread_priority(thid, B_REAL_TIME_PRIORITY); + return tinfo.priority; +} + +/**************************************************************************** +REMARKS: +Restore the original thread priority. +****************************************************************************/ +static void RestoreThreadPriority( + int priority) +{ + thread_id thid = find_thread(NULL); + set_thread_priority(thid, priority); +} + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + /* TODO: Return the frequency of the counter in here. You should try to */ + /* normalise this value to be around 100,000 ticks per second. */ + freq->low = 1000000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. + +TODO: Implement this to read the counter. It should be done as a macro + for accuracy. +****************************************************************************/ +#define GetCounter(t) { *((bigtime_t*) t) = system_time(); } diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/event.c b/board/MAI/bios_emulator/scitech/src/pm/beos/event.c new file mode 100644 index 0000000..93c6c0a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/event.c @@ -0,0 +1,199 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: BeOS implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under non-DOS systems */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + /* TODO: Implement this for your OS! */ +} + +/**************************************************************************** +REMARKS: +Pumps all messages in the application message queue into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + /* TODO: The purpose of this function is to read all keyboard and mouse */ + /* events from the OS specific event queue, translate them and post */ + /* them into the SciTech event queue. */ + /* */ + /* NOTE: There are a couple of important things that this function must */ + /* take care of: */ + /* */ + /* 1. Support for KEYDOWN, KEYREPEAT and KEYUP is required. */ + /* */ + /* 2. Support for reading hardware scan code as well as ASCII */ + /* translated values is required. Games use the scan codes rather */ + /* than ASCII values. Scan codes go into the high order byte of the */ + /* keyboard message field. */ + /* */ + /* 3. Support for at least reading mouse motion data (mickeys) from the */ + /* mouse is required. Using the mickey values, we can then translate */ + /* to mouse cursor coordinates scaled to the range of the current */ + /* graphics display mode. Mouse values are scaled based on the */ + /* global 'rangeX' and 'rangeY'. */ + /* */ + /* 4. Support for a timestamp for the events is required, which is */ + /* defined as the number of milliseconds since some event (usually */ + /* system startup). This is the timestamp when the event occurred */ + /* (ie: at interrupt time) not when it was stuff into the SciTech */ + /* event queue. */ + /* */ + /* 5. Support for mouse double click events. If the OS has a native */ + /* mechanism to determine this, it should be used. Otherwise the */ + /* time stamp information will be used by the generic event code */ + /* to generate double click events. */ +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* TODO: Do any OS specific initialisation here */ + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* TODO: Do any OS specific cleanup in here */ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h new file mode 100644 index 0000000..043d73e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h @@ -0,0 +1,32 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +/* This is where you include OS specific headers for the event handling */ +/* library. */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c b/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c new file mode 100644 index 0000000..2dcb1b8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c @@ -0,0 +1,539 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include +#include +#include + +/* TODO: Include any BeOS specific headers here! */ + +/*--------------------------- Global variables ----------------------------*/ + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +void PMAPI PM_init(void) +{ + /* TODO: Do any initialisation in here. This includes getting IOPL */ + /* access for the process calling PM_init. This will get called */ + /* more than once. */ + + /* TODO: If you support the supplied MTRR register stuff (you need to */ + /* be at ring 0 for this!), you should initialise it in here. */ + +/* MTRR_init(); */ +} + +long PMAPI PM_getOSType(void) +{ return _OS_BEOS; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '/') { + s[pos] = '/'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + /* TODO: If you are running in a GUI environment without a console, */ + /* this needs to be changed to bring up a fatal error message */ + /* box and terminate the program. */ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + exit(1); +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + /* No BIOS access for the BeOS */ + return NULL; +} + +int PMAPI PM_kbhit(void) +{ + /* TODO: This function checks if a key is available to be read. This */ + /* should be implemented, but is mostly used by the test programs */ + /* these days. */ + return true; +} + +int PMAPI PM_getch(void) +{ + /* TODO: This returns the ASCII code of the key pressed. This */ + /* should be implemented, but is mostly used by the test programs */ + /* these days. */ + return 0xD; +} + +int PMAPI PM_openConsole(void) +{ + /* TODO: Opens up a fullscreen console for graphics output. If your */ + /* console does not have graphics/text modes, this can be left */ + /* empty. The main purpose of this is to disable console switching */ + /* when in graphics modes if you can switch away from fullscreen */ + /* consoles (if you want to allow switching, this can be done */ + /* elsewhere with a full save/restore state of the graphics mode). */ + return 0; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + /* TODO: Returns the size of the console state buffer used to save the */ + /* state of the console before going into graphics mode. This is */ + /* used to restore the console back to normal when we are done. */ + return 1; +} + +void PMAPI PM_saveConsoleState(void *stateBuf,int console_id) +{ + /* TODO: Saves the state of the console into the state buffer. This is */ + /* used to restore the console back to normal when we are done. */ + /* We will always restore 80x25 text mode after being in graphics */ + /* mode, so if restoring text mode is all you need to do this can */ + /* be left empty. */ +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,int console_id) +{ + /* TODO: Restore the state of the console from the state buffer. This is */ + /* used to restore the console back to normal when we are done. */ + /* We will always restore 80x25 text mode after being in graphics */ + /* mode, so if restoring text mode is all you need to do this can */ + /* be left empty. */ +} + +void PMAPI PM_closeConsole(int console_id) +{ + /* TODO: Close the console when we are done, going back to text mode. */ +} + +void PM_setOSCursorLocation(int x,int y) +{ + /* TODO: Set the OS console cursor location to the new value. This is */ + /* generally used for new OS ports (used mostly for DOS). */ +} + +void PM_setOSScreenWidth(int width,int height) +{ + /* TODO: Set the OS console screen width. This is generally unused for */ + /* new OS ports. */ +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency) +{ + /* TODO: Install a real time clock interrupt handler. Normally this */ + /* will not be supported from most OS'es in user land, so an */ + /* alternative mechanism is needed to enable software stereo. */ + /* Hence leave this unimplemented unless you have a high priority */ + /* mechanism to call the 32-bit callback when the real time clock */ + /* interrupt fires. */ + return false; +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + /* TODO: Set the real time clock interrupt frequency. Used for stereo */ + /* LC shutter glasses when doing software stereo. Usually sets */ + /* the frequency to around 2048 Hz. */ +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Restores the real time clock handler. */ +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return '/'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return PM_getNucleusConfigPath(); } + +const char * PMAPI PM_getNucleusPath(void) +{ + char *env = getenv("NUCLEUS_PATH"); + return env ? env : "/usr/lib/nucleus"; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ + /* TODO: Return a unique ID for the machine. If a unique ID is not */ + /* available, return the machine name. */ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +const char * PMAPI PM_getMachineName(void) +{ + /* TODO: Return the network machine name for the machine. */ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +void * PMAPI PM_getBIOSPointer(void) +{ + /* No BIOS access on the BeOS */ + return NULL; +} + +void * PMAPI PM_getA0000Pointer(void) +{ + static void *bankPtr; + if (!bankPtr) + bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + return bankPtr; +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + /* TODO: This function maps a physical memory address to a linear */ + /* address in the address space of the calling process. */ + + /* NOTE: This function *must* be able to handle any phsyical base */ + /* address, and hence you will have to handle rounding of */ + /* the physical base address to a page boundary (ie: 4Kb on */ + /* x86 CPU's) to be able to properly map in the memory */ + /* region. */ + + /* NOTE: If possible the isCached bit should be used to ensure that */ + /* the PCD (Page Cache Disable) and PWT (Page Write Through) */ + /* bits are set to disable caching for a memory mapping used */ + /* for MMIO register access. We also disable caching using */ + /* the MTRR registers for Pentium Pro and later chipsets so if */ + /* MTRR support is enabled for your OS then you can safely ignore */ + /* the isCached flag and always enable caching in the page */ + /* tables. */ + return NULL; +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* TODO: This function will free a physical memory mapping previously */ + /* allocated with PM_mapPhysicalAddr() if at all possible. If */ + /* you can't free physical memory mappings, simply do nothing. */ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* TODO: Put the process to sleep for milliseconds */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +void * PMAPI PM_mallocShared(long size) +{ + /* TODO: This is used to allocate memory that is shared between process */ + /* that all access the common Nucleus drivers via a common display */ + /* driver DLL. If your OS does not support shared memory (or if */ + /* the display driver does not need to allocate shared memory */ + /* for each process address space), this should just call PM_malloc. */ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + /* TODO: Free the shared memory block. This will be called in the context */ + /* of the original calling process that allocated the shared */ + /* memory with PM_mallocShared. Simply call free if you do not */ + /* need this. */ + PM_free(ptr); +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ + /* TODO: This function is used to map a physical memory mapping */ + /* previously allocated with PM_mapPhysicalAddr into the */ + /* address space of the calling process. If the memory mapping */ + /* allocated by PM_mapPhysicalAddr is global to all processes, */ + /* simply return the pointer. */ + return base; +} + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + /* No BIOS access on the BeOS */ + return NULL; +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + /* No BIOS access on the BeOS */ + return NULL; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + /* No BIOS access on the BeOS */ +} + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + /* No BIOS access on the BeOS */ +} + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + /* No BIOS access on the BeOS */ + return 0; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + /* No BIOS access on the BeOS */ + return 0; +} + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + /* No BIOS access on the BeOS */ +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + /* TODO: Report the amount of available memory, both the amount of */ + /* physical memory left and the amount of virtual memory left. */ + /* If the OS does not provide these services, report 0's. */ + *physical = *total = 0; +} + +void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg) +{ + /* TODO: Allocate a block of locked, physical memory of the specified */ + /* size. This is used for bus master operations. If this is not */ + /* supported by the OS, return NULL and bus mastering will not */ + /* be used. */ + return NULL; +} + +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) +{ + /* TODO: Free a memory block allocated with PM_allocLockedMem. */ +} + +void PMAPI PM_setBankA(int bank) +{ + /* No BIOS access on the BeOS */ +} + +void PMAPI PM_setBankAB(int bank) +{ + /* No BIOS access on the BeOS */ +} + +void PMAPI PM_setCRTStart(int x,int y,int waitVRT) +{ + /* No BIOS access on the BeOS */ +} + +ibool PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type) +{ + /* TODO: This function should enable Pentium Pro and Pentium II MTRR */ + /* write combining for the passed in physical memory base address */ + /* and length. Normally this is done via calls to an OS specific */ + /* device driver as this can only be done at ring 0. */ + /* */ + /* NOTE: This is a *very* important function to implement! If you do */ + /* not implement, graphics performance on the latest Intel chips */ + /* will be severly impaired. For sample code that can be used */ + /* directly in a ring 0 device driver, see the MSDOS implementation */ + /* which includes assembler code to do this directly (if the */ + /* program is running at ring 0). */ + return false; +} + +ibool PMAPI PM_doBIOSPOST(ushort axVal,ulong BIOSPhysAddr,void *mappedBIOS) +{ + /* TODO: This function is used to run the BIOS POST code on a secondary */ + /* controller to initialise it for use. This is not necessary */ + /* for multi-controller operation, but it will make it a lot */ + /* more convenicent for end users (otherwise they have to boot */ + /* the system once with the secondary controller as primary, and */ + /* then boot with both controllers installed). */ + /* */ + /* Even if you don't support full BIOS access, it would be */ + /* adviseable to be able to POST the secondary controllers in the */ + /* system using this function as a minimum requirement. Some */ + /* graphics hardware has registers that contain values that only */ + /* the BIOS knows about, which makes bring up a card from cold */ + /* reset difficult if the BIOS has not POST'ed it. */ + return false; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +ulong PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + ulong handle, + PM_findData *findData) +{ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + ulong handle) +{ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + if (drive == 3) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + (void)drive; + getcwd(dir,len); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Set the file attributes for a file */ + (void)filename; + (void)attrib; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c new file mode 100644 index 0000000..579ef2c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c new file mode 100644 index 0000000..a528b73 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c @@ -0,0 +1,111 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void _ZTimerInit(void) +{ + /* TODO: Do any specific internal initialisation in here */ +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +static void _LZTimerOn( + LZTimerObject *tm) +{ + /* TODO: Start the Zen Timer counting. This should be a macro if */ + /* possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong _LZTimerLap( + LZTimerObject *tm) +{ + /* TODO: Compute the lap time between the current time and when the */ + /* timer was started. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Stop the Zen Timer counting. +****************************************************************************/ +static void _LZTimerOff( + LZTimerObject *tm) +{ + /* TODO: Stop the timer counting. Should be a macro if possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time in microseconds between start and end timings. +****************************************************************************/ +static ulong _LZTimerCount( + LZTimerObject *tm) +{ + /* TODO: Compute the elapsed time and return it. Always microseconds. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Read the Long Period timer from the OS +****************************************************************************/ +static ulong _ULZReadTime(void) +{ + /* TODO: Read the long period timer from the OS. The resolution of this */ + /* timer should be around 1/20 of a second for timing long */ + /* periods if possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong _ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c b/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c new file mode 100644 index 0000000..9aa8714 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c @@ -0,0 +1,285 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Keyboard translation code pages for US English keyboards. +* +****************************************************************************/ + +#include "event.h" + +/*--------------------------- Global variables ----------------------------*/ + +/* This table is used for all normal key translations, and is the fallback + * table if the key is not found in any of the other translation tables. + * If the code is not found in this table, the ASCII code is set to 0 to + * indicate that there is no ASCII code equivalent for this key. + */ +static codepage_entry_t US_normal[] = { + {0x01, 0x1B}, + {0x02, '1'}, + {0x03, '2'}, + {0x04, '3'}, + {0x05, '4'}, + {0x06, '5'}, + {0x07, '6'}, + {0x08, '7'}, + {0x09, '8'}, + {0x0A, '9'}, + {0x0B, '0'}, + {0x0C, '-'}, + {0x0D, '='}, + {0x0E, 0x08}, + {0x0F, 0x09}, + {0x10, 'q'}, + {0x11, 'w'}, + {0x12, 'e'}, + {0x13, 'r'}, + {0x14, 't'}, + {0x15, 'y'}, + {0x16, 'u'}, + {0x17, 'i'}, + {0x18, 'o'}, + {0x19, 'p'}, + {0x1A, '['}, + {0x1B, ']'}, + {0x1C, 0x0D}, + {0x1E, 'a'}, + {0x1F, 's'}, + {0x20, 'd'}, + {0x21, 'f'}, + {0x22, 'g'}, + {0x23, 'h'}, + {0x24, 'j'}, + {0x25, 'k'}, + {0x26, 'l'}, + {0x27, ';'}, + {0x28, '\''}, + {0x29, '`'}, + {0x2B, '\\'}, + {0x2C, 'z'}, + {0x2D, 'x'}, + {0x2E, 'c'}, + {0x2F, 'v'}, + {0x30, 'b'}, + {0x31, 'n'}, + {0x32, 'm'}, + {0x33, ','}, + {0x34, '.'}, + {0x35, '/'}, + {0x37, '*'}, /* Keypad */ + {0x39, ' '}, + {0x4A, '-'}, /* Keypad */ + {0x4E, '+'}, /* Keypad */ + {0x60, 0x0D}, /* Keypad */ + {0x61, '/'}, /* Keypad */ + }; + +/* This table is used for when CAPSLOCK is active and the shift or ctrl + * keys are not down. If the code is not found in this table, the normal + * table above is then searched. + */ +static codepage_entry_t US_caps[] = { + {0x10, 'Q'}, + {0x11, 'W'}, + {0x12, 'E'}, + {0x13, 'R'}, + {0x14, 'T'}, + {0x15, 'Y'}, + {0x16, 'U'}, + {0x17, 'I'}, + {0x18, 'O'}, + {0x19, 'P'}, + {0x1E, 'A'}, + {0x1F, 'S'}, + {0x20, 'D'}, + {0x21, 'F'}, + {0x22, 'G'}, + {0x23, 'H'}, + {0x24, 'J'}, + {0x25, 'K'}, + {0x26, 'L'}, + {0x2C, 'Z'}, + {0x2D, 'X'}, + {0x2E, 'C'}, + {0x2F, 'V'}, + {0x30, 'B'}, + {0x31, 'N'}, + {0x32, 'M'}, + }; + +/* This table is used for when shift key is down, but the ctrl key is not + * down and CAPSLOCK is not active. If the code is not found in this table, + * the normal table above is then searched. + */ +static codepage_entry_t US_shift[] = { + {0x02, '!'}, + {0x03, '@'}, + {0x04, '#'}, + {0x05, '$'}, + {0x06, '%'}, + {0x07, '^'}, + {0x08, '&'}, + {0x09, '*'}, + {0x0A, '('}, + {0x0B, ')'}, + {0x0C, '_'}, + {0x0D, '+'}, + {0x10, 'Q'}, + {0x11, 'W'}, + {0x12, 'E'}, + {0x13, 'R'}, + {0x14, 'T'}, + {0x15, 'Y'}, + {0x16, 'U'}, + {0x17, 'I'}, + {0x18, 'O'}, + {0x19, 'P'}, + {0x1A, '{'}, + {0x1B, '}'}, + {0x1E, 'A'}, + {0x1F, 'S'}, + {0x20, 'D'}, + {0x21, 'F'}, + {0x22, 'G'}, + {0x23, 'H'}, + {0x24, 'J'}, + {0x25, 'K'}, + {0x26, 'L'}, + {0x27, ':'}, + {0x28, '"'}, + {0x29, '~'}, + {0x2B, '|'}, + {0x2C, 'Z'}, + {0x2D, 'X'}, + {0x2E, 'C'}, + {0x2F, 'V'}, + {0x30, 'B'}, + {0x31, 'N'}, + {0x32, 'M'}, + {0x33, '<'}, + {0x34, '>'}, + {0x35, '?'}, + }; + +/* This table is used for when CAPSLOCK is active and the shift key is + * down, but the ctrl key is not. If the code is not found in this table, + * the shift table above is then searched. + */ +static codepage_entry_t US_shiftCaps[] = { + {0x10, 'q'}, + {0x11, 'w'}, + {0x12, 'e'}, + {0x13, 'r'}, + {0x14, 't'}, + {0x15, 'y'}, + {0x16, 'u'}, + {0x17, 'i'}, + {0x18, 'o'}, + {0x19, 'p'}, + {0x1E, 'a'}, + {0x1F, 's'}, + {0x20, 'd'}, + {0x21, 'f'}, + {0x22, 'g'}, + {0x23, 'h'}, + {0x24, 'j'}, + {0x25, 'k'}, + {0x26, 'l'}, + {0x2C, 'z'}, + {0x2D, 'x'}, + {0x2E, 'c'}, + {0x2F, 'v'}, + {0x30, 'b'}, + {0x31, 'n'}, + {0x32, 'm'}, + }; + +/* This table is used for all key translations when the ctrl key is down, + * regardless of the state of the shift key and CAPSLOCK. If the code is + * not found in this table, the ASCII code is set to 0 to indicate that + * there is no ASCII code equivalent for this key. + */ +static codepage_entry_t US_ctrl[] = { + {0x01, 0x1B}, + {0x06, 0x1E}, + {0x0C, 0x1F}, + {0x0E, 0x7F}, + {0x10, 0x11}, + {0x11, 0x17}, + {0x12, 0x05}, + {0x13, 0x12}, + {0x14, 0x14}, + {0x15, 0x19}, + {0x16, 0x16}, + {0x17, 0x09}, + {0x18, 0x0F}, + {0x19, 0x10}, + {0x1A, 0x1B}, + {0x1B, 0x1D}, + {0x1C, 0x0A}, + {0x1E, 0x01}, + {0x1F, 0x13}, + {0x20, 0x04}, + {0x21, 0x06}, + {0x22, 0x07}, + {0x23, 0x08}, + {0x24, 0x0A}, + {0x25, 0x0B}, + {0x26, 0x0C}, + {0x2B, 0x1C}, + {0x2C, 0x1A}, + {0x2D, 0x18}, + {0x2E, 0x03}, + {0x2F, 0x16}, + {0x30, 0x02}, + {0x31, 0x0E}, + {0x32, 0x0D}, + {0x39, ' '}, + }; + +static codepage_entry_t US_numPad[] = { + {0x4C, '5'}, + {0x62, '4'}, + {0x63, '6'}, + {0x64, '8'}, + {0x65, '2'}, + {0x66, '0'}, + {0x67, '.'}, + {0x68, '7'}, + {0x69, '1'}, + {0x6A, '9'}, + {0x6B, '3'}, + }; + +codepage_t _CP_US_English = { + "US English", + US_normal, EVT_ARR_SIZE(US_normal), + US_caps, EVT_ARR_SIZE(US_caps), + US_shift, EVT_ARR_SIZE(US_shift), + US_shiftCaps, EVT_ARR_SIZE(US_shiftCaps), + US_ctrl, EVT_ARR_SIZE(US_ctrl), + US_numPad, EVT_ARR_SIZE(US_numPad), + }; diff --git a/board/MAI/bios_emulator/scitech/src/pm/common.c b/board/MAI/bios_emulator/scitech/src/pm/common.c new file mode 100644 index 0000000..d5a8e8f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common.c @@ -0,0 +1,480 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module containing code common to all platforms. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#if defined(__WIN32_VXD__) || defined(__OS2_VDD__) || defined(__NT_DRIVER__) +#include "sdd/sddhelp.h" +#else +#include +#include +#include +#endif + +/*---------------------------- Global variables ---------------------------*/ + +/* {secret} */ +long _VARAPI ___drv_os_type = _OS_UNSUPPORTED; +static char localBPDPath[PM_MAX_PATH] = ""; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus BPD driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. By default the local BPD path is +always set to the current directory if not initialised. +****************************************************************************/ +void PMAPI PM_setLocalBPDPath( + const char *path) +{ + PM_init(); + strncpy(localBPDPath,path,sizeof(localBPDPath)); + localBPDPath[sizeof(localBPDPath)-1] = 0; +} + +/**************************************************************************** +PARAMETERS: +bpdpath - Place to store the actual path to the file +cachedpath - Place to store the cached BPD driver path +trypath - Path to try to find the BPD file in +subpath - Optional sub path to append to trypath +dllname - Name of the Binary Portable DLL to load + +RETURNS: +True if found, false if not. + +REMARKS: +Trys the specified path to see if the BPD file can be found or not. If so, +the path used is returned in bpdpath and cachedpath. +****************************************************************************/ +static ibool TryPath( + char *bpdpath, + char *cachedpath, + const char *trypath, + const char *subpath, + const char *dllname) +{ + char filename[256]; + FILE *f; + + strcpy(bpdpath, trypath); + PM_backslash(bpdpath); + strcat(bpdpath,subpath); + PM_backslash(bpdpath); + strcpy(filename,bpdpath); + strcat(filename,dllname); + if ((f = fopen(filename,"rb")) == NULL) + return false; + if (cachedpath) + strcpy(cachedpath,bpdpath); + fclose(f); + return true; +} + +/**************************************************************************** +RETURNS: +True if local override enabled, false if not. + +REMARKS: +Tests to see if the local override option is enabled, and if so it will +look for the Nucleus drivers in the local application directories in +preference to the Nucleus system directories. +****************************************************************************/ +static ibool GetLocalOverride(void) +{ + char filename[256]; + FILE *f; + static ibool local_override = -1; + + if (local_override == -1) { + local_override = false; + strcpy(filename,PM_getNucleusPath()); + PM_backslash(filename); + strcat(filename,"graphics.ini"); + if ((f = fopen(filename,"r")) != NULL) { + while (!feof(f) && fgets(filename,sizeof(filename),f)) { + if (strnicmp(filename,"uselocal",8) == 0) { + local_override = ((*(filename+9) - '0') == 1); + break; + } + } + fclose(f); + } + } + return local_override; +} + +/**************************************************************************** +DESCRIPTION: +Sets the location of the debug log file. + +HEADER: +pmapi.h + +PARAMETERS: +dllname - Name of the Binary Portable DLL to load +bpdpath - Place to store the actual path to the file + +RETURNS: +True if found, false if not. + +REMARKS: +Finds the location of a specific Binary Portable DLL, by searching all +the standard SciTech Nucleus driver locations. +****************************************************************************/ +ibool PMAPI PM_findBPD( + const char *dllname, + char *bpdpath) +{ + static char cachedpath[PM_MAX_PATH] = ""; + + /* On the first call determine the path to the Nucleus drivers */ + if (cachedpath[0] == 0) { + /* First try in the global system Nucleus driver path if + * the local override setting is not enabled. + */ + PM_init(); + if (!GetLocalOverride()) { + if (TryPath(bpdpath,cachedpath,PM_getNucleusPath(),"",dllname)) + return true; + } + + /* Next try in the local application directory if available */ + if (localBPDPath[0] != 0) { + if (TryPath(bpdpath,cachedpath,localBPDPath,"",dllname)) + return true; + } + else { +#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) + char *mgl_root; + if ((mgl_root = getenv("MGL_ROOT")) != NULL) { + if (TryPath(bpdpath,cachedpath,mgl_root,"drivers",dllname)) + return true; + } +#endif + PM_getCurrentPath(bpdpath,PM_MAX_PATH); + if (TryPath(bpdpath,cachedpath,bpdpath,"drivers",dllname)) + return true; + } + + /* Finally try in the global system path again so that we + * will still find the drivers in the global system path if + * the local override option is on, but the application does + * not have any local override drivers. + */ + if (TryPath(bpdpath,cachedpath,PM_getNucleusPath(),"",dllname)) + return true; + + /* Whoops, we can't find the BPD file! */ + return false; + } + + /* Always try in the previously discovered path */ + return TryPath(bpdpath,NULL,cachedpath,"",dllname); +} + +/**************************************************************************** +REMARKS: +Copies a string into another, and returns dest + strlen(src). +****************************************************************************/ +static char *_stpcpy( + char *_dest, + const char *_src) +{ + if (!_dest || !_src) + return 0; + while ((*_dest++ = *_src++) != 0) + ; + return --_dest; +} + +/**************************************************************************** +REMARKS: +Copies a string into another, stopping at the maximum length. The string +is properly terminated (unlike strncpy). +****************************************************************************/ +static void safe_strncpy( + char *dst, + const char *src, + unsigned maxlen) +{ + if (dst) { + if(strlen(src) >= maxlen) { + strncpy(dst, src, maxlen); + dst[maxlen] = 0; + } + else + strcpy(dst, src); + } +} + +/**************************************************************************** +REMARKS: +Determins if the dot separator is present in the string. +****************************************************************************/ +static int findDot( + char *p) +{ + if (*(p-1) == '.') + p--; + switch (*--p) { + case ':': + if (*(p-2) != '\0') + break; + case '/': + case '\\': + case '\0': + return true; + } + return false; +} + +/**************************************************************************** +DESCRIPTION: +Make a full pathname from split components. + +HEADER: +pmapi.h + +PARAMETERS: +path - Place to store full path +drive - Drive component for path +dir - Directory component for path +name - Filename component for path +ext - Extension component for path + +REMARKS: +Function to make a full pathname from split components. Under Unix the +drive component will usually be empty. If the drive, dir, name, or ext +parameters are null or empty, they are not inserted in the path string. +Otherwise, if the drive doesn't end with a colon, one is inserted in the +path. If the dir doesn't end in a slash, one is inserted in the path. +If the ext doesn't start with a dot, one is inserted in the path. + +The maximum sizes for the path string is given by the constant PM_MAX_PATH, +which includes space for the null-terminator. + +SEE ALSO: +PM_splitPath +****************************************************************************/ +void PMAPI PM_makepath( + char *path, + const char *drive, + const char *dir, + const char *name, + const char *ext) +{ + if (drive && *drive) { + *path++ = *drive; + *path++ = ':'; + } + if (dir && *dir) { + path = _stpcpy(path,dir); + if (*(path-1) != '\\' && *(path-1) != '/') +#ifdef __UNIX__ + *path++ = '/'; +#else + *path++ = '\\'; +#endif + } + if (name) + path = _stpcpy(path,name); + if (ext && *ext) { + if (*ext != '.') + *path++ = '.'; + path = _stpcpy(path,ext); + } + *path = 0; +} + +/**************************************************************************** +DESCRIPTION: +Split a full pathname into components. + +HEADER: +pmapi.h + +PARAMETERS: +path - Full path to split +drive - Drive component for path +dir - Directory component for path +name - Filename component for path +ext - Extension component for path + +RETURNS: +Flags indicating what components were parsed. + +REMARKS: +Function to split a full pathmame into separate components in the form + + X:\DIR\SUBDIR\NAME.EXT + +and splits path into its four components. It then stores those components +in the strings pointed to by drive, dir, name and ext. (Each component is +required but can be a NULL, which means the corresponding component will be +parsed but not stored). + +The maximum sizes for these strings are given by the constants PM_MAX_DRIVE +and PM_MAX_PATH. PM_MAX_DRIVE is always 4, and PM_MAX_PATH is usually at +least 256 characters. Under Unix the dir, name and ext components may be +up to the full path in length. + +SEE ALSO: +PM_makePath +****************************************************************************/ +int PMAPI PM_splitpath( + const char *path, + char *drive, + char *dir, + char *name, + char *ext) +{ + char *p; + int temp,ret; + char buf[PM_MAX_PATH+2]; + + /* Set all string to default value zero */ + ret = 0; + if (drive) *drive = 0; + if (dir) *dir = 0; + if (name) *name = 0; + if (ext) *ext = 0; + + /* Copy filename into template up to PM_MAX_PATH characters */ + p = buf; + if ((temp = strlen(path)) > PM_MAX_PATH) + temp = PM_MAX_PATH; + *p++ = 0; + strncpy(p, path, temp); + *(p += temp) = 0; + + /* Split the filename and fill corresponding nonzero pointers */ + temp = 0; + for (;;) { + switch (*--p) { + case '.': + if (!temp && (*(p+1) == '\0')) + temp = findDot(p); + if ((!temp) && ((ret & PM_HAS_EXTENSION) == 0)) { + ret |= PM_HAS_EXTENSION; + safe_strncpy(ext, p, PM_MAX_PATH - 1); + *p = 0; + } + continue; + case ':': + if (p != &buf[2]) + continue; + case '\0': + if (temp) { + if (*++p) + ret |= PM_HAS_DIRECTORY; + safe_strncpy(dir, p, PM_MAX_PATH - 1); + *p-- = 0; + break; + } + case '/': + case '\\': + if (!temp) { + temp++; + if (*++p) + ret |= PM_HAS_FILENAME; + safe_strncpy(name, p, PM_MAX_PATH - 1); + *p-- = 0; + if (*p == 0 || (*p == ':' && p == &buf[2])) + break; + } + continue; + case '*': + case '?': + if (!temp) + ret |= PM_HAS_WILDCARDS; + default: + continue; + } + break; + } + if (*p == ':') { + if (buf[1]) + ret |= PM_HAS_DRIVE; + safe_strncpy(drive, &buf[1], PM_MAX_DRIVE - 1); + } + return ret; +} + +/**************************************************************************** +DESCRIPTION: +Block until a specific time has elapsed since the last call + +HEADER: +pmapi.h + +PARAMETERS: +milliseconds - Number of milliseconds for delay + +REMARKS: +This function will block the calling thread or process until the specified +number of milliseconds have passed since the /last/ call to this function. +The first time this function is called, it will return immediately. On +subsquent calls it will block until the specified time has elapsed, or it +will return immediately if the time has already elapsed. + +This function is useful to provide constant time functionality in a +program, such as a frame rate limiter for graphics applications etc. + +SEE ALSO: +PM_sleep +****************************************************************************/ +void PMAPI PM_blockUntilTimeout( + ulong milliseconds) +{ + ulong microseconds = milliseconds * 1000L,msDelay; + static LZTimerObject tm; + static ibool firstTime = true; + + if (firstTime) { + firstTime = false; + LZTimerOnExt(&tm); + } + else { + if ((msDelay = (microseconds - LZTimerLapExt(&tm)) / 1000L) > 0) + PM_sleep(msDelay); + while (LZTimerLapExt(&tm) < microseconds) + ; + LZTimerOffExt(&tm); + LZTimerOnExt(&tm); + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm new file mode 100644 index 0000000..60ebed7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm @@ -0,0 +1,600 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM or TASM Assembler +;* Environment: Intel 32 bit Protected Mode. +;* +;* Description: Code to determine the Intel processor type. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" + +header _cpuinfo + +begdataseg _cpuinfo ; Start of data segment + +cache_id db "01234567890123456" +intel_id db "GenuineIntel" ; Intel vendor ID +cyrix_id db "CyrixInstead" ; Cyrix vendor ID +amd_id db "AuthenticAMD" ; AMD vendor ID +idt_id db "CentaurHauls" ; IDT vendor ID + +CPU_IDT EQU 01000h ; Flag for IDT processors +CPU_Cyrix EQU 02000h ; Flag for Cyrix processors +CPU_AMD EQU 04000h ; Flag for AMD processors +CPU_Intel EQU 08000h ; Flag for Intel processors + +enddataseg _cpuinfo + +begcodeseg _cpuinfo ; Start of code segment + +ifdef USE_NASM +%macro mCPU_ID 0 +db 00Fh,0A2h +%endmacro +else +MACRO mCPU_ID +db 00Fh,0A2h +ENDM +endif + +ifdef USE_NASM +%macro mRDTSC 0 +db 00Fh,031h +%endmacro +else +MACRO mRDTSC +db 00Fh,031h +ENDM +endif + +;---------------------------------------------------------------------------- +; bool _CPU_check80386(void) +;---------------------------------------------------------------------------- +; Determines if we have an i386 processor. +;---------------------------------------------------------------------------- +cprocstart _CPU_check80386 + + enter_c + + xor edx,edx ; EDX = 0, not an 80386 + mov bx, sp +ifdef USE_NASM + and sp, ~3 +else + and sp, not 3 +endif + pushfd ; Push original EFLAGS + pop eax ; Get original EFLAGS + mov ecx, eax ; Save original EFLAGS + xor eax, 40000h ; Flip AC bit in EFLAGS + push eax ; Save new EFLAGS value on + ; stack + popfd ; Replace current EFLAGS value + pushfd ; Get new EFLAGS + pop eax ; Store new EFLAGS in EAX + xor eax, ecx ; Can't toggle AC bit, + ; processor=80386 + jnz @@Done ; Jump if not an 80386 processor + inc edx ; We have an 80386 + +@@Done: push ecx + popfd + mov sp, bx + mov eax, edx + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; bool _CPU_check80486(void) +;---------------------------------------------------------------------------- +; Determines if we have an i486 processor. +;---------------------------------------------------------------------------- +cprocstart _CPU_check80486 + + enter_c + +; Distinguish between the i486 and Pentium by the ability to set the ID flag +; in the EFLAGS register. If the ID flag is set, then we can use the CPUID +; instruction to determine the final version of the chip. Otherwise we +; simply have an 80486. + +; Distinguish between the i486 and Pentium by the ability to set the ID flag +; in the EFLAGS register. If the ID flag is set, then we can use the CPUID +; instruction to determine the final version of the chip. Otherwise we +; simply have an 80486. + + pushfd ; Get original EFLAGS + pop eax + mov ecx, eax + xor eax, 200000h ; Flip ID bit in EFLAGS + push eax ; Save new EFLAGS value on stack + popfd ; Replace current EFLAGS value + pushfd ; Get new EFLAGS + pop eax ; Store new EFLAGS in EAX + xor eax, ecx ; Can not toggle ID bit, + jnz @@1 ; Processor=80486 + mov eax,1 ; We dont have a Pentium + jmp @@Done +@@1: mov eax,0 ; We have Pentium or later +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; bool _CPU_checkClone(void) +;---------------------------------------------------------------------------- +; Checks if the i386 or i486 processor is a clone or genuine Intel. +;---------------------------------------------------------------------------- +cprocstart _CPU_checkClone + + enter_c + + mov ax,5555h ; Check to make sure this is a 32-bit processor + xor dx,dx + mov cx,2h + div cx ; Perform Division + clc + jnz @@NoClone + jmp @@Clone +@@NoClone: + stc +@@Clone: + pushfd + pop eax ; Get the flags + and eax,1 + xor eax,1 ; EAX=0 is probably Intel, EAX=1 is a Clone + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; bool _CPU_haveCPUID(void) +;---------------------------------------------------------------------------- +; Determines if we have support for the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_haveCPUID + + enter_c + +ifdef flatmodel + pushfd ; Get original EFLAGS + pop eax + mov ecx, eax + xor eax, 200000h ; Flip ID bit in EFLAGS + push eax ; Save new EFLAGS value on stack + popfd ; Replace current EFLAGS value + pushfd ; Get new EFLAGS + pop eax ; Store new EFLAGS in EAX + xor eax, ecx ; Can not toggle ID bit, + jnz @@1 ; Processor=80486 + mov eax,0 ; We dont have CPUID support + jmp @@Done +@@1: mov eax,1 ; We have CPUID support +else + mov eax,0 ; CPUID requires 32-bit pmode +endif +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_checkCPUID(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_checkCPUID + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax,eax ; Assume vendor is unknown + +; Check for GenuineIntel processors + + LEA_L esi,intel_id + cmp [DWORD esi], ebx + jne @@NotIntel + cmp [DWORD esi+4], edx + jne @@NotIntel + cmp [DWORD esi+8], ecx + jne @@NotIntel + mov eax,CPU_Intel ; Flag that we have GenuineIntel + jmp @@FoundVendor + +; Check for CyrixInstead processors + +@@NotIntel: + LEA_L esi,cyrix_id + cmp [DWORD esi], ebx + jne @@NotCyrix + cmp [DWORD esi+4], edx + jne @@NotCyrix + cmp [DWORD esi+8], ecx + jne @@NotCyrix + mov eax,CPU_Cyrix ; Flag that we have CyrixInstead + jmp @@FoundVendor + +; Check for AuthenticAMD processors + +@@NotCyrix: + LEA_L esi,amd_id + cmp [DWORD esi], ebx + jne @@NotAMD + cmp [DWORD esi+4], edx + jne @@NotAMD + cmp [DWORD esi+8], ecx + jne @@NotAMD + mov eax,CPU_AMD ; Flag that we have AuthenticAMD + jmp @@FoundVendor + +; Check for CentaurHauls processors + +@@NotAMD: + LEA_L esi,idt_id + cmp [DWORD esi], ebx + jne @@NotIDT + cmp [DWORD esi+4], edx + jne @@NotIDT + cmp [DWORD esi+8], ecx + jne @@NotIDT + mov eax,CPU_IDT ; Flag that we have AuthenticIDT + jmp @@FoundVendor + +@@NotIDT: + +@@FoundVendor: + push eax + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + and eax, 0F00h + shr eax, 8 ; Isolate family + and eax, 0Fh + pop ecx + or eax,ecx ; Combine in the clone flag +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_getCPUIDModel(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_getCPUIDModel + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + and eax, 0F0h + shr eax, 4 ; Isolate model +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_getCPUIDStepping(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_getCPUIDStepping + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + and eax, 00Fh ; Isolate stepping +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_getCPUIDFeatures(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_getCPUIDFeatures + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + mov eax, edx +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_getCacheSize(void) +;---------------------------------------------------------------------------- +; Determines the CPU cache size for Intel processors +;---------------------------------------------------------------------------- +cprocstart _CPU_getCacheSize + + enter_c + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax,2 ; Make sure 2 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + mov eax,2 + mCPU_ID ; Get cache descriptors + LEA_L esi,cache_id ; Get address of cache ID (-fPIC aware) + shr eax,8 + mov [esi+0],eax + mov [esi+3],ebx + mov [esi+7],ecx + mov [esi+11],edx + xor eax,eax + LEA_L esi,cache_id ; Get address of cache ID (-fPIC aware) + mov edi,15 +@@ScanLoop: + cmp [BYTE esi],41h + mov eax,128 + je @@Done + cmp [BYTE esi],42h + mov eax,256 + je @@Done + cmp [BYTE esi],43h + mov eax,512 + je @@Done + cmp [BYTE esi],44h + mov eax,1024 + je @@Done + cmp [BYTE esi],45h + mov eax,2048 + je @@Done + inc esi + dec edi + jnz @@ScanLoop + +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_have3DNow(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_have3DNow + + enter_c + + mov eax,80000000h ; Query for extended functions + mCPU_ID ; Get extended function limit + cmp eax,80000001h + jbe @@Fail ; Nope, we dont have function 800000001h + mov eax,80000001h ; Setup extended function 800000001h + mCPU_ID ; and get the information + test edx,80000000h ; Bit 31 is set if 3DNow! present + jz @@Fail ; Nope, we dont have 3DNow support + mov eax,1 ; Yep, we have 3DNow! support! +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; ulong _CPU_quickRDTSC(void) +;---------------------------------------------------------------------------- +; Reads the time stamp counter and returns the low order 32-bits +;---------------------------------------------------------------------------- +cprocstart _CPU_quickRDTSC + + mRDTSC + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _CPU_runBSFLoop(ulong interations) +;---------------------------------------------------------------------------- +; Runs a loop of BSF instructions for the specified number of iterations +;---------------------------------------------------------------------------- +cprocstart _CPU_runBSFLoop + + ARG iterations:ULONG + + push _bp + mov _bp,_sp + push _bx + + mov edx,[iterations] + mov eax,80000000h + mov ebx,edx + + ALIGN 4 + +@@loop: bsf ecx,eax + dec ebx + jnz @@loop + + pop _bx + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _CPU_readTimeStamp(CPU_largeInteger *time); +;---------------------------------------------------------------------------- +; Reads the time stamp counter and returns the 64-bit result. +;---------------------------------------------------------------------------- +cprocstart _CPU_readTimeStamp + + mRDTSC + mov ecx,[esp+4] ; Access directly without stack frame + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _CPU_diffTime64(CPU_largeInteger *t1,CPU_largeInteger *t2,CPU_largeInteger *t) +;---------------------------------------------------------------------------- +; Computes the difference between two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _CPU_diffTime64 + + ARG t1:DPTR, t2:DPTR, t:DPTR + + enter_c + + mov ecx,[t2] + mov eax,[ecx] ; EAX := t2.low + mov ecx,[t1] + sub eax,[ecx] + mov edx,eax ; EDX := low difference + mov ecx,[t2] + mov eax,[ecx+4] ; ECX := t2.high + mov ecx,[t1] + sbb eax,[ecx+4] ; EAX := high difference + + mov ebx,[t] ; Store the result + mov [ebx],edx ; Store low part + mov [ebx+4],eax ; Store high part + mov eax,edx ; Return low part +ifndef flatmodel + shld edx,eax,16 ; Return in DX:AX +endif + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _CPU_calcMicroSec(CPU_largeInteger *count,ulong freq); +;---------------------------------------------------------------------------- +; Computes the value in microseconds for the elapsed time with maximum +; precision. The formula we use is: +; +; us = (((diff * 0x100000) / freq) * 1000000) / 0x100000) +; +; The power of two multiple before the first divide allows us to scale the +; 64-bit difference using simple shifts, and then the divide brings the +; final result into the range to fit into a 32-bit integer. +;---------------------------------------------------------------------------- +cprocstart _CPU_calcMicroSec + + ARG count:DPTR, freq:ULONG + + enter_c + + mov ecx,[count] + mov eax,[ecx] ; EAX := low part + mov edx,[ecx+4] ; EDX := high part + shld edx,eax,20 + shl eax,20 ; diff * 0x100000 + div [DWORD freq] ; (diff * 0x100000) / freq + mov ecx,1000000 + xor edx,edx + mul ecx ; ((diff * 0x100000) / freq) * 1000000) + shrd eax,edx,20 ; ((diff * 0x100000) / freq) * 1000000) / 0x100000 +ifndef flatmodel + shld edx,eax,16 ; Return in DX:AX +endif + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _CPU_mulDiv(ulong a,ulong b,ulong c); +;---------------------------------------------------------------------------- +; Computes the following with 64-bit integer precision: +; +; result = (a * b) / c +; +;---------------------------------------------------------------------------- +cprocstart _CPU_mulDiv + + ARG a:ULONG, b:ULONG, c:ULONG + + enter_c + mov eax,[a] + imul [ULONG b] + idiv [ULONG c] +ifndef flatmodel + shld edx,eax,16 ; Return in DX:AX +endif + leave_c + ret + +cprocend + +endcodeseg _cpuinfo + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm new file mode 100644 index 0000000..2b6e1e8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm @@ -0,0 +1,246 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 16/32 bit Ring 0 device driver +;* +;* Description: Assembler support routines for ISA DMA controller. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _dma ; Set up memory model + +begdataseg _dma ; Start of data segment + +cpublic _PM_DMADataStart + +; DMA register I/O addresses for channels 0-7 (except 4) + +DMAC_page db 087h,083h,081h,082h, -1,08Bh,089h,08Ah +DMAC_addr db 000h,002h,004h,006h, -1,0C4h,0C8h,0CCh +DMAC_cnt db 001h,003h,005h,007h, -1,0C6h,0CAh,0CEh +DMAC_mask db 00Ah,00Ah,00Ah,00Ah, -1,0D4h,0D4h,0D4h +DMAC_mode db 00Bh,00Bh,00Bh,00Bh, -1,0D6h,0D6h,0D6h +DMAC_FF db 00Ch,00Ch,00Ch,00Ch, -1,0D8h,0D8h,0D8h + +cpublic _PM_DMADataEnd + +enddataseg _dma + +begcodeseg _dma ; Start of code segment + +ifdef flatmodel + +cpublic _PM_DMACodeStart + +;---------------------------------------------------------------------------- +; void PM_DMACDisable(int channel); +;---------------------------------------------------------------------------- +; Masks DMA channel, inhibiting DMA transfers +;---------------------------------------------------------------------------- +cprocstart PM_DMACDisable + + ARG channel:UINT + + push ebp + mov ebp,esp + mov ecx,[channel] ; ECX indexes DMAC register tables + mov dh,0 ; DH = 0 for DMAC register port access + mov al,cl + and al,11b + or al,100b ; AL = (channel & 3) | "set mask bit" + mov dl,[DMAC_mask+ecx] + out dx,al + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_DMACEnable(int channel); +;---------------------------------------------------------------------------- +; Unmasks DMA channel, enabling DMA transfers +;---------------------------------------------------------------------------- +cprocstart PM_DMACEnable + + ARG channel:UINT + + push ebp + mov ebp,esp + mov ecx,[channel] ; ECX indexes DMAC register tables + mov dh,0 ; DH = 0 for DMAC register port access + mov al,cl + and al,11b ; AL = (channel & 3), "set mask bit"=0 + mov dl,[DMAC_mask+ecx] + out dx,al + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_DMACProgram(int channel,int mode,ulong bufferPhys,int count); +;---------------------------------------------------------------------------- +; Purpose: Program DMA controller to perform transfer from first 16MB +; based on previously selected mode and channel. DMA transfer may be enabled +; by subsequent call to PM_DMACEnable. +; +; Entry: channel - DMA channel in use (0-7) +; mode - Selected DMAMODE type for transfer +; buffer - 32-bit physical address of DMA buffer +; count - DMA byte count (1-65536 bytes) +;---------------------------------------------------------------------------- +cprocstart PM_DMACProgram + + ARG channel:UINT, mode:UINT, bufferPhys:ULONG, count:UINT + + enter_c + pushfd + cli ; Disable interrupts + +; Mask DMA channel to disable it + + mov ebx,[channel] ; EBX indexes DMAC register tables + mov dh,0 ; DH = 0 for DMAC register port access + mov al,bl + and al,11b + or al,100b ; AL = (channel & 3) | "set mask bit" + mov dl,[DMAC_mask+ebx] + out dx,al + +; Generate IOW to clear FF toggle state + + mov al,0 + mov dl,[DMAC_FF+ebx] + out dx,al + +; Compute buffer address to program + + mov eax,[bufferPhys] ; AX := DMA address offset + mov ecx,eax + shr ecx,16 ; CL := bufferPhys >> 16 (DMA page) + mov esi,[count] ; ESI = # of bytes to transfer + cmp ebx,4 ; 16-bit channel? + jb @@WriteDMAC ; No, program DMAC + shr eax,1 ; Yes, convert address and count + shr esi,1 ; to 16-bit, 128K/page format + +; Set the DMA address word (bits 0-15) + +@@WriteDMAC: + mov dl,[DMAC_addr+ebx] + out dx,al + mov al,ah + out dx,al + +; Set DMA transfer count + + mov eax,esi + dec eax ; ESI = # of bytes to transfer - 1 + mov dl,[DMAC_cnt+ebx] + out dx,al + mov al,ah + out dx,al + +; Set DMA page byte (bits 16-23) + + mov al,cl + mov dl,[DMAC_page+ebx] + out dx,al + +; Set the DMA channel mode + + mov al,bl + and al,11b + or al,[BYTE mode] ; EAX = (channel & 3) | mode + mov dl,[DMAC_mode+ebx] + out dx,al + + pop eax ; SMP safe interrupt state restore! + test eax,200h + jz @@1 + sti +@@1: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong PMAPI PM_DMACPosition(int channel); +;---------------------------------------------------------------------------- +; Returns the current position in a dma transfer. Interrupts should be +; disabled before calling this function. +;---------------------------------------------------------------------------- +cprocstart PM_DMACPosition + + ARG channel:UINT + + enter_c + mov ecx,[channel] ; ECX indexes DMAC register tables + mov dh,0 ; DH = 0 for DMAC register port access + +; Generate IOW to clear FF toggle state + + mov al,0 + mov dl,[DMAC_FF+ebx] + out dx,al + xor eax,eax + xor ecx,ecx + +; Now read the current position for the channel + +@@ReadLoop: + mov dl,[DMAC_cnt+ebx] + out dx,al + in al,dx + mov cl,al + in al,dx + mov ch,al ; ECX := first count read + in al,dx + mov ah,al + in al,dx + xchg al,ah ; EAX := second count read + sub ecx,eax + cmp ecx,40h + jg @@ReadLoop + cmp ebx,4 ; 16-bit channel? + jb @@Exit ; No, we are done + shl eax,1 ; Yes, adjust to byte address + +@@Exit: leave_c + ret + +cprocend + + +cpublic _PM_DMACodeEnd + +endif + +endcodeseg _dma + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm new file mode 100644 index 0000000..fdec1b5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm @@ -0,0 +1,309 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM or TASM Assembler +;* Environment: Intel 32 bit Protected Mode. +;* +;* Description: Code for 64-bit arhithmetic +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" + +header _int64 + +begcodeseg _int64 ; Start of code segment + +a_low EQU 04h ; Access a_low directly on stack +a_high EQU 08h ; Access a_high directly on stack +b_low EQU 0Ch ; Access b_low directly on stack +shift EQU 0Ch ; Access shift directly on stack +result_2 EQU 0Ch ; Access result directly on stack +b_high EQU 10h ; Access b_high directly on stack +result_3 EQU 10h ; Access result directly on stack +result_4 EQU 14h ; Access result directly on stack + +;---------------------------------------------------------------------------- +; void _PM_add64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result); +;---------------------------------------------------------------------------- +; Adds two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _PM_add64 + + mov eax,[esp+a_low] + add eax,[esp+b_low] + mov edx,[esp+a_high] + adc edx,[esp+b_high] + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_sub64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result); +;---------------------------------------------------------------------------- +; Subtracts two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _PM_sub64 + + mov eax,[esp+a_low] + sub eax,[esp+b_low] + mov edx,[esp+a_high] + sbb edx,[esp+b_high] + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_mul64(u32 a_high,u32 a_low,u32 b_high,u32 b_low,__u64 *result); +;---------------------------------------------------------------------------- +; Multiples two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _PM_mul64 + + mov eax,[esp+a_high] + mov ecx,[esp+b_high] + or ecx,eax + mov ecx,[esp+b_low] + jnz @@FullMultiply + mov eax,[esp+a_low] ; EDX:EAX = b.low * a.low + mul ecx + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +@@FullMultiply: + push ebx + mul ecx ; EDX:EAX = a.high * b.low + mov ebx,eax + mov eax,[esp+a_low+4] + mul [DWORD esp+b_high+4] ; EDX:EAX = b.high * a.low + add ebx,eax + mov eax,[esp+a_low+4] + mul ecx ; EDX:EAX = a.low * b.low + add edx,ebx + pop ebx + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_div64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result); +;---------------------------------------------------------------------------- +; Divides two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _PM_div64 + + push edi + push esi + push ebx + xor edi,edi + mov eax,[esp+a_high+0Ch] + or eax,eax + jns @@ANotNeg + +; Dividend is negative, so negate it and save result for later + + inc edi + mov edx,[esp+a_low+0Ch] + neg eax + neg edx + sbb eax,0 + mov [esp+a_high+0Ch],eax + mov [esp+a_low+0Ch],edx + +@@ANotNeg: + mov eax,[esp+b_high+0Ch] + or eax,eax + jns @@BNotNeg + +; Divisor is negative, so negate it and save result for later + + inc edi + mov edx,[esp+b_low+0Ch] + neg eax + neg edx + sbb eax,0 + mov [esp+b_high+0Ch],eax + mov [esp+b_low+0Ch],edx + +@@BNotNeg: + or eax,eax + jnz @@BHighNotZero + +; b.high is zero, so handle this faster + + mov ecx,[esp+b_low+0Ch] + mov eax,[esp+a_high+0Ch] + xor edx,edx + div ecx + mov ebx,eax + mov eax,[esp+a_low+0Ch] + div ecx + mov edx,ebx + jmp @@BHighZero + +@@BHighNotZero: + mov ebx,eax + mov ecx,[esp+b_low+0Ch] + mov edx,[esp+a_high+0Ch] + mov eax,[esp+a_low+0Ch] + +; Shift values right until b.high becomes zero + +@@ShiftLoop: + shr ebx,1 + rcr ecx,1 + shr edx,1 + rcr eax,1 + or ebx,ebx + jnz @@ShiftLoop + +; Now complete the divide process + + div ecx + mov esi,eax + mul [DWORD esp+b_high+0Ch] + mov ecx,eax + mov eax,[esp+b_low+0Ch] + mul esi + add edx,ecx + jb @@8 + cmp edx,[esp+a_high+0Ch] + ja @@8 + jb @@9 + cmp eax,[esp+a_low+0Ch] + jbe @@9 +@@8: dec esi +@@9: xor edx,edx + mov eax,esi + +@@BHighZero: + dec edi + jnz @@Done + +; The result needs to be negated as either a or b was negative + + neg edx + neg eax + sbb edx,0 + +@@Done: pop ebx + pop esi + pop edi + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; __i64 _PM_shr64(u32 a_low,s32 a_high,s32 shift,__u64 *result); +;---------------------------------------------------------------------------- +; Shift a 64-bit number right +;---------------------------------------------------------------------------- +cprocstart _PM_shr64 + + mov eax,[esp+a_low] + mov edx,[esp+a_high] + mov cl,[esp+shift] + shrd edx,eax,cl + mov ecx,[esp+result_3] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; __i64 _PM_sar64(u32 a_low,s32 a_high,s32 shift,__u64 *result); +;---------------------------------------------------------------------------- +; Shift a 64-bit number right (signed) +;---------------------------------------------------------------------------- +cprocstart _PM_sar64 + + mov eax,[esp+a_low] + mov edx,[esp+a_high] + mov cl,[esp+shift] + sar edx,cl + rcr eax,cl + mov ecx,[esp+result_3] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; __i64 _PM_shl64(u32 a_low,s32 a_high,s32 shift,__u64 *result); +;---------------------------------------------------------------------------- +; Shift a 64-bit number left +;---------------------------------------------------------------------------- +cprocstart _PM_shl64 + + mov eax,[esp+a_low] + mov edx,[esp+a_high] + mov cl,[esp+shift] + shld edx,eax,cl + mov ecx,[esp+result_3] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; __i64 _PM_neg64(u32 a_low,s32 a_high,__u64 *result); +;---------------------------------------------------------------------------- +; Shift a 64-bit number left +;---------------------------------------------------------------------------- +cprocstart _PM_neg64 + + mov eax,[esp+a_low] + mov edx,[esp+a_high] + neg eax + neg edx + sbb eax,0 + mov ecx,[esp+result_2] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + + +endcodeseg _int64 + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm new file mode 100644 index 0000000..0ff1ecf --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm @@ -0,0 +1,230 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler +;* Environment: Intel x86, any OS +;* +;* Description: Assembly language support routines for reading analogue +;* joysticks. +;* +;**************************************************************************** + + ideal + +include "scitech.mac" ; Memory model macros + +ifdef flatmodel + +header _joy ; Set up memory model + +begcodeseg _joy ; Start of code segment + +;---------------------------------------------------------------------------- +; initTimer +;---------------------------------------------------------------------------- +; Sets up 8253 timer 2 (PC speaker) to start timing, but not produce output. +;---------------------------------------------------------------------------- +cprocstatic initTimer + +; Start timer 2 counting + + in al,61h + and al,0FDh ; Disable speaker output (just in case) + or al,1 + out 61h,al + +; Set the timer 2 count to 0 again to start the timing interval. + + mov al,10110100b ; set up to load initial (timer 2) + out 43h,al ; timer count + sub al,al + out 42h,al ; load count lsb + out 42h,al ; load count msb + ret + +cprocend + +;---------------------------------------------------------------------------- +; readTimer2 +;---------------------------------------------------------------------------- +; Reads the number of ticks from the 8253 timer chip using channel 2 (PC +; speaker). This is non-destructive and does not screw up other libraries. +;---------------------------------------------------------------------------- +cprocstatic readTimer + + xor al,al ; Latch timer 0 command + out 43h,al ; Latch timer + in al,42h ; least significant byte + mov ah,al + in al,42h ; most significant byte + xchg ah,al + and eax,0FFFFh + ret + +cprocend + +;---------------------------------------------------------------------------- +; exitTimer +;---------------------------------------------------------------------------- +; Stops the 8253 timer 2 (PC speaker) counting +;---------------------------------------------------------------------------- +cprocstatic exitTimer + +; Stop timer 2 from counting + + push eax + in al,61h + and al,0FEh + out 61h,al + +; Some programs have a problem if we change the control port; better change it +; to something they expect (mode 3 - square wave generator)... + mov al,0B6h + out 43h,al + + pop eax + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _EVT_readJoyAxis(int jmask,int *axis); +;---------------------------------------------------------------------------- +; Function to poll the joystick to read the current axis positions. +;---------------------------------------------------------------------------- +cprocstart _EVT_readJoyAxis + + ARG jmask:UINT, axis:DPTR + + LOCAL firstTick:UINT, lastTick:UINT, totalTicks:UINT = LocalSize + + enter_c + + mov ebx,[jmask] + mov edi,[axis] + mov ecx,(1193180/100) + and ebx,01111b ; Mask out supported axes + mov dx,201h ; DX := joystick I/O port + call initTimer ; Start timer 2 counting + call readTimer ; Returns counter in EAX + mov [lastTick],eax + +@@WaitStable: + in al,dx + and al,bl ; Wait for the axes in question to be + jz @@Stable ; done reading... + call readTimer ; Returns counter in EAX + xchg eax,[lastTick] + cmp eax,[lastTick] + jb @@1 + sub eax,[lastTick] +@@1: add [totalTicks],eax + cmp [totalTicks],ecx ; Check for timeout + jae @@Stable + jmp @@WaitStable + +@@Stable: + mov al,0FFh + out dx,al ; Start joystick reading + call initTimer ; Start timer 2 counting + call readTimer ; Returns counter in EAX + mov [firstTick],eax ; Store initial count + mov [lastTick],eax + mov [DWORD totalTicks],0 + cli + +@@PollLoop: + in al,dx ; Read Joystick port + not al + and al,bl ; Mask off channels we don't want to read + jnz @@AxisFlipped ; See if any of the channels flipped + call readTimer ; Returns counter in EAX + xchg eax,[lastTick] + cmp eax,[lastTick] + jb @@2 + sub eax,[lastTick] +@@2: add [totalTicks],eax + cmp [totalTicks],ecx ; Check for timeout + jae @@TimedOut + jmp @@PollLoop + +@@AxisFlipped: + xor esi,esi + mov ah,1 + test al,ah + jnz @@StoreCount ; Joystick 1, X axis flipped + add esi,4 + mov ah,2 + test al,ah + jnz @@StoreCount ; Joystick 1, Y axis flipped + add esi,4 + mov ah,4 + test al,ah + jnz @@StoreCount ; Joystick 2, X axis flipped + add esi,4 ; Joystick 2, Y axis flipped + mov ah,8 + +@@StoreCount: + or bh,ah ; Indicate this axis is active + xor bl,ah ; Unmark the channels that just tripped + call readTimer ; Returns counter in EAX + xchg eax,[lastTick] + cmp eax,[lastTick] + jb @@3 + sub eax,[lastTick] +@@3: add [totalTicks],eax + mov eax,[totalTicks] + mov [edi+esi],eax ; Record the time this channel flipped + cmp bl,0 ; If there are more channels to read, + jne @@PollLoop ; keep looping + +@@TimedOut: + sti + call exitTimer ; Stop timer 2 counting + movzx eax,bh ; Return the mask of working axes + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _EVT_readJoyButtons(void); +;---------------------------------------------------------------------------- +; Function to poll the current joystick buttons +;---------------------------------------------------------------------------- +cprocstart _EVT_readJoyButtons + + mov dx,0201h + in al,dx + shr al,4 + not al + and eax,0Fh + ret + +cprocend + +endcodeseg _joy + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm new file mode 100644 index 0000000..1e0a696 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm @@ -0,0 +1,272 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 16/32 bit Ring 0 device driver +;* +;* Description: Assembler support routines for the Memory Type Range Register +;* (MTRR) module. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _mtrr ; Set up memory model + +begdataseg _mtrr + +ifdef DOS4GW + cextern _PM_haveCauseWay,UINT +endif + +enddataseg _mtrr + +begcodeseg _mtrr ; Start of code segment + +P586 + +;---------------------------------------------------------------------------- +; ibool _MTRR_isRing0(void); +;---------------------------------------------------------------------------- +; Checks to see if we are running at ring 0. This check is only relevant +; for 32-bit DOS4GW and compatible programs. If we are not running under +; DOS4GW, then we simply assume we are a ring 0 device driver. +;---------------------------------------------------------------------------- +cprocnear _MTRR_isRing0 + +; Are we running under CauseWay? + +ifdef DOS4GW + enter_c + mov ax,cs + and eax,3 + xor eax,3 + jnz @@Exit + +; CauseWay runs the apps at ring 3, but implements support for specific +; ring 0 instructions that we need to get stuff done under real DOS. + + mov eax,1 + cmp [UINT _PM_haveCauseWay],0 + jnz @@Exit +@@Fail: xor eax,eax +@@Exit: leave_c + ret +else +ifdef __SMX32__ + mov eax,1 ; SMX is ring 0! + ret +else +ifdef __VXD__ + mov eax,1 ; VxD is ring 0! + ret +else +ifdef __NT_DRIVER__ + mov eax,1 ; NT/W2K is ring 0! + ret +else +else + xor eax,eax ; Assume ring 3 for 32-bit DOS + ret +endif +endif +endif +endif + +cprocend + +;---------------------------------------------------------------------------- +; ulong _MTRR_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _MTRR_disableInt + + pushfd ; Put flag word on stack + cli ; Disable interrupts! + pop eax ; deposit flag word in return register + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_restoreInt(ulong ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _MTRR_restoreInt + + ARG ps:ULONG + + push ebp + mov ebp,esp ; Set up stack frame + mov ecx,[ps] + test ecx,200h ; SMP safe interrupt flag restore! + jz @@1 + sti +@@1: pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _MTRR_saveCR4(void); +;---------------------------------------------------------------------------- +; Save the value of CR4 and clear the Page Global Enable (bit 7). We also +; disable and flush the caches. +;---------------------------------------------------------------------------- +cprocstart _MTRR_saveCR4 + + enter_c + +; Save value of CR4 and clear Page Global Enable (bit 7) + + mov ebx,cr4 + mov eax,ebx + and al,7Fh + mov cr4,eax + +; Disable and flush caches + + mov eax,cr0 + or eax,40000000h + wbinvd + mov cr0,eax + wbinvd + +; Return value from CR4 + + mov eax,ebx + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_restoreCR4(ulong cr4Val) +;---------------------------------------------------------------------------- +; Save the value of CR4 and clear the Page Global Enable (bit 7). We also +; disable and flush the caches. +;---------------------------------------------------------------------------- +cprocstart _MTRR_restoreCR4 + + ARG cr4Val:ULONG + + enter_c + +; Enable caches + + mov eax,cr0 + and eax,0BFFFFFFFh + mov cr0,eax + mov eax,[cr4Val] + mov cr4,eax + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_getCx86(uchar reg); +;---------------------------------------------------------------------------- +; Read a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_getCx86 + + ARG reg:UCHAR + + enter_c + mov al,[reg] + out 22h,al + in al,23h + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_setCx86(uchar reg,uchar val); +;---------------------------------------------------------------------------- +; Write a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_setCx86 + + ARG reg:UCHAR, val:UCHAR + + enter_c + mov al,[reg] + out 22h,al + mov al,[val] + out 23h,al + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_readMSR(uong reg, ulong FAR *eax, ulong FAR *edx); +;---------------------------------------------------------------------------- +; Writes the specific Machine Status Register used on the newer Intel +; Pentium Pro and Pentium II motherboards. +;---------------------------------------------------------------------------- +cprocnear _MTRR_readMSR + + ARG reg:ULONG, v_eax:DPTR, v_edx:DPTR + + enter_c + mov ecx,[reg] + rdmsr + mov ebx,[v_eax] + mov [ebx],eax + mov ebx,[v_edx] + mov [ebx],edx + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_writeMSR(uong reg, ulong eax, ulong edx); +;---------------------------------------------------------------------------- +; Writes the specific Machine Status Register used on the newer Intel +; Pentium Pro and Pentium II motherboards. +;---------------------------------------------------------------------------- +cprocnear _MTRR_writeMSR + + ARG reg:ULONG, v_eax:ULONG, v_edx:ULONG + + enter_c + mov ecx,[reg] + mov eax,[v_eax] + mov edx,[v_edx] + wrmsr + leave_c + ret + +cprocend + +endcodeseg _mtrr + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm new file mode 100644 index 0000000..5b8dbcc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm @@ -0,0 +1,358 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: Any +;* +;* Description: Helper assembler functions for PCI access module. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pcilib + +begcodeseg _pcilib + +ifdef flatmodel + +;---------------------------------------------------------------------------- +; uchar _ASMAPI _BIOS32_service( +; ulong service, +; ulong func, +; ulong *physBase, +; ulong *length, +; ulong *serviceOffset, +; PCIBIOS_entry entry); +;---------------------------------------------------------------------------- +; Call the BIOS32 services directory +;---------------------------------------------------------------------------- +cprocstart _BIOS32_service + + ARG service:ULONG, func:ULONG, physBase:DPTR, len:DPTR, off:DPTR, entry:QWORD + + enter_c + mov eax,[service] + mov ebx,[func] +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif + mov esi,[physBase] + mov [esi],ebx + mov esi,[len] + mov [esi],ecx + mov esi,[off] + mov [esi],edx + leave_c + ret + +cprocend + +endif + +;---------------------------------------------------------------------------- +; ushort _ASMAPI _PCIBIOS_isPresent(ulong i_eax,ulong *o_edx,ushort *oeax, +; uchar *o_cl,PCIBIOS_entry entry) +;---------------------------------------------------------------------------- +; Call the PCI BIOS to determine if it is present. +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_isPresent + + ARG i_eax:ULONG, o_edx:DPTR, oeax:DPTR, o_cl:DPTR, entry:QWORD + + enter_c + mov eax,[i_eax] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + _les _si,[o_edx] + mov [_ES _si],edx + _les _si,[oeax] + mov [_ES _si],ax + _les _si,[o_cl] + mov [_ES _si],cl + mov ax,bx + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _PCIBIOS_service(ulong r_eax,ulong r_ebx,ulong r_edi,ulong r_ecx, +; PCIBIOS_entry entry) +;---------------------------------------------------------------------------- +; Call the PCI BIOS services, either via the 32-bit protected mode entry +; point or via the Int 1Ah 16-bit interrupt. +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_service + + ARG r_eax:ULONG, r_ebx:ULONG, r_edi:ULONG, r_ecx:ULONG, entry:QWORD + + enter_c + mov eax,[r_eax] + mov ebx,[r_ebx] + mov edi,[r_edi] + mov ecx,[r_ecx] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + mov eax,ecx +ifndef flatmodel + shld edx,eax,16 ; Return result in DX:AX +endif + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _PCIBIOS_getRouting(PCIRoutingOptionsBuffer *buf,PCIBIOS_entry entry); +;---------------------------------------------------------------------------- +; Get the routing options for PCI devices +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_getRouting + + ARG buf:DPTR, entry:QWORD + + enter_c + mov eax,0B10Eh + mov bx,0 + _les _di,[buf] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + movzx eax,ah + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ibool _PCIBIOS_setIRQ(int busDev,int intPin,int IRQ,PCIBIOS_entry entry); +;---------------------------------------------------------------------------- +; Change the IRQ routing for the PCI device +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_setIRQ + + ARG busDev:UINT, intPin:UINT, IRQ:UINT, entry:QWORD + + enter_c + mov eax,0B10Fh + mov bx,[USHORT busDev] + mov cl,[BYTE intPin] + mov ch,[BYTE IRQ] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + mov eax,1 + jnc @@1 + xor eax,eax ; Function failed! +@@1: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _PCIBIOS_specialCycle(int bus,ulong data,PCIBIOS_entry entry); +;---------------------------------------------------------------------------- +; Generate a special cycle via the PCI BIOS. +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_specialCycle + + ARG bus:UINT, data:ULONG, entry:QWORD + + enter_c + mov eax,0B106h + mov bh,[BYTE bus] + mov ecx,[data] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ushort _PCI_getCS(void) +;---------------------------------------------------------------------------- +cprocstart _PCI_getCS + + mov ax,cs + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_inpb(int port) +;---------------------------------------------------------------------------- +; Reads a byte from the specified port +;---------------------------------------------------------------------------- +cprocstart PM_inpb + + ARG port:UINT + + push _bp + mov _bp,_sp + xor _ax,_ax + mov _dx,[port] + in al,dx + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_inpw(int port) +;---------------------------------------------------------------------------- +; Reads a word from the specified port +;---------------------------------------------------------------------------- +cprocstart PM_inpw + + ARG port:UINT + + push _bp + mov _bp,_sp + xor _ax,_ax + mov _dx,[port] + in ax,dx + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong PM_inpd(int port) +;---------------------------------------------------------------------------- +; Reads a word from the specified port +;---------------------------------------------------------------------------- +cprocstart PM_inpd + + ARG port:UINT + + push _bp + mov _bp,_sp + mov _dx,[port] + in eax,dx +ifndef flatmodel + shld edx,eax,16 ; DX:AX = result +endif + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_outpb(int port,int value) +;---------------------------------------------------------------------------- +; Write a byte to the specified port. +;---------------------------------------------------------------------------- +cprocstart PM_outpb + + ARG port:UINT, value:UINT + + push _bp + mov _bp,_sp + mov _dx,[port] + mov _ax,[value] + out dx,al + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_outpw(int port,int value) +;---------------------------------------------------------------------------- +; Write a word to the specified port. +;---------------------------------------------------------------------------- +cprocstart PM_outpw + + ARG port:UINT, value:UINT + + push _bp + mov _bp,_sp + mov _dx,[port] + mov _ax,[value] + out dx,ax + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_outpd(int port,ulong value) +;---------------------------------------------------------------------------- +; Write a word to the specified port. +;---------------------------------------------------------------------------- +cprocstart PM_outpd + + ARG port:UINT, value:ULONG + + push _bp + mov _bp,_sp + mov _dx,[port] + mov eax,[value] + out dx,eax + pop _bp + ret + +cprocend + +endcodeseg _pcilib + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/agp.c b/board/MAI/bios_emulator/scitech/src/pm/common/agp.c new file mode 100644 index 0000000..d53bc88 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/agp.c @@ -0,0 +1,189 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Ring 0 device driver +* +* Description: Generic module to implement AGP support functions using the +* SciTech Nucleus AGP support drivers. If the OS provides +* native AGP support, this module should *NOT* be used. Instead +* wrappers should be placed around the OS support functions +* to implement this functionality. +* +****************************************************************************/ + +#include "pmapi.h" +#ifndef REALMODE +#include "nucleus/agp.h" + +/*--------------------------- Global variables ----------------------------*/ + +static AGP_devCtx *agp; +static AGP_driverFuncs driver; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +RETURNS: +Size of AGP aperture in MB on success, 0 on failure. + +REMARKS: +This function initialises the AGP driver in the system and returns the +size of the available AGP aperture in megabytes. +****************************************************************************/ +ulong PMAPI PM_agpInit(void) +{ + if ((agp = AGP_loadDriver(0)) == NULL) + return 0; + driver.dwSize = sizeof(driver); + if (!agp->QueryFunctions(AGP_GET_DRIVERFUNCS,&driver)) + return 0; + switch (driver.GetApertureSize()) { + case agpSize4MB: return 4; + case agpSize8MB: return 8; + case agpSize16MB: return 16; + case agpSize32MB: return 32; + case agpSize64MB: return 64; + case agpSize128MB: return 128; + case agpSize256MB: return 256; + case agpSize512MB: return 512; + case agpSize1GB: return 1024; + case agpSize2GB: return 2048; + } + return 0; +} + +/**************************************************************************** +REMARKS: +This function closes down the loaded AGP driver. +****************************************************************************/ +void PMAPI PM_agpExit(void) +{ + AGP_unloadDriver(agp); +} + +/**************************************************************************** +PARAMETERS: +numPages - Number of memory pages that should be reserved +type - Type of memory to allocate +physContext - Returns the physical context handle for the mapping +physAddr - Returns the physical address for the mapping + +RETURNS: +True on success, false on failure. + +REMARKS: +This function reserves a range of physical memory addresses on the system +bus which the AGP controller will respond to. If this function succeeds, +the AGP controller can respond to the reserved physical address range on +the bus. However you must first call AGP_commitPhysical to cause this memory +to actually be committed for use before it can be accessed. +****************************************************************************/ +ibool PMAPI PM_agpReservePhysical( + ulong numPages, + int type, + void **physContext, + PM_physAddr *physAddr) +{ + switch (type) { + case PM_agpUncached: + type = agpUncached; + break; + case PM_agpWriteCombine: + type = agpWriteCombine; + break; + case PM_agpIntelDCACHE: + type = agpIntelDCACHE; + break; + default: + return false; + } + return driver.ReservePhysical(numPages,type,physContext,physAddr) == nOK; +} + +/**************************************************************************** +PARAMETERS: +physContext - Physical AGP context to release + +RETURNS: +True on success, false on failure. + +REMARKS: +This function releases a range of physical memory addresses on the system +bus which the AGP controller will respond to. All committed memory for +the physical address range covered by the context will be released. +****************************************************************************/ +ibool PMAPI PM_agpReleasePhysical( + void *physContext) +{ + return driver.ReleasePhysical(physContext) == nOK; +} + +/**************************************************************************** +PARAMETERS: +physContext - Physical AGP context to commit memory for +numPages - Number of pages to be committed +startOffset - Offset in pages into the reserved physical context +physAddr - Returns the physical address of the committed memory + +RETURNS: +True on success, false on failure. + +REMARKS: +This function commits into the specified physical context that was previously +reserved by a call to ReservePhysical. You can use the startOffset and +numPages parameters to only commit portions of the reserved memory range at +a time. +****************************************************************************/ +ibool PMAPI PM_agpCommitPhysical( + void *physContext, + ulong numPages, + ulong startOffset, + PM_physAddr *physAddr) +{ + return driver.CommitPhysical(physContext,numPages,startOffset,physAddr) == nOK; +} + +/**************************************************************************** +PARAMETERS: +physContext - Physical AGP context to free memory for +numPages - Number of pages to be freed +startOffset - Offset in pages into the reserved physical context + +RETURNS: +True on success, false on failure. + +REMARKS: +This function frees memory previously committed by the CommitPhysical +function. Note that you can free a portion of a memory range that was +previously committed if you wish. +****************************************************************************/ +ibool PMAPI PM_agpFreePhysical( + void *physContext, + ulong numPages, + ulong startOffset) +{ + return driver.FreePhysical(physContext,numPages,startOffset) == nOK; +} + +#endif /* !REALMODE */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c b/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c new file mode 100644 index 0000000..36867bd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c @@ -0,0 +1,449 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Direct keyboard event handling module. This module contains +* code to process raw scan code information, convert it to +* virtual scan codes and do code page translation to ASCII +* for different international keyboard layouts. +* +****************************************************************************/ + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +PARAMETERS: +scanCode - Keyboard scan code to translate +table - Code page table to search +count - Number of entries in the code page table + +REMARKS: +This function translates the scan codes from keyboard scan codes to ASCII +codes using a binary search on the code page table. +****************************************************************************/ +static uchar translateScan( + uchar scanCode, + codepage_entry_t *table, + int count) +{ + codepage_entry_t *test; + int n,pivot,val; + + for (n = count; n > 0; ) { + pivot = n >> 1; + test = table + pivot; + val = scanCode - test->scanCode; + if (val < 0) + n = pivot; + else if (val == 0) + return test->asciiCode; + else { + table = test + 1; + n -= pivot + 1; + } + } + return 0; +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +{secret} +****************************************************************************/ +void _EVT_maskKeyCode( + event_t *evt) +{ + int ascii,scan = EVT_scanCode(evt->message); + + evt->message &= ~0xFF; + if (evt->modifiers & EVT_NUMLOCK) { + if ((ascii = translateScan(scan,EVT.codePage->numPad,EVT.codePage->numPadLen)) != 0) { + evt->message |= ascii; + return; + } + } + if (evt->modifiers & EVT_CTRLSTATE) { + evt->message |= translateScan(scan,EVT.codePage->ctrl,EVT.codePage->ctrlLen); + return; + } + if (evt->modifiers & EVT_CAPSLOCK) { + if (evt->modifiers & EVT_SHIFTKEY) { + if ((ascii = translateScan(scan,EVT.codePage->shiftCaps,EVT.codePage->shiftCapsLen)) != 0) { + evt->message |= ascii; + return; + } + } + else { + if ((ascii = translateScan(scan,EVT.codePage->caps,EVT.codePage->capsLen)) != 0) { + evt->message |= ascii; + return; + } + } + } + if (evt->modifiers & EVT_SHIFTKEY) { + if ((ascii = translateScan(scan,EVT.codePage->shift,EVT.codePage->shiftLen)) != 0) { + evt->message |= ascii; + return; + } + } + evt->message |= translateScan(scan,EVT.codePage->normal,EVT.codePage->normalLen); +} + +/**************************************************************************** +REMARKS: +Returns true if the key with the specified scan code is being held down. +****************************************************************************/ +static ibool _EVT_isKeyDown( + uchar scanCode) +{ + if (scanCode > 0x7F) + return false; + else + return EVT.keyTable[scanCode] != 0; +} + +/**************************************************************************** +PARAMETERS: +what - Event code +message - Event message (ASCII code and scan code) + +REMARKS: +Adds a new keyboard event to the event queue. This routine is called from +within the keyboard interrupt subroutine! + +NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, + and we leave them OFF the entire time. +****************************************************************************/ +static void addKeyEvent( + uint what, + uint message) +{ + event_t evt; + + if (EVT.count < EVENTQSIZE) { + /* Save information in event record */ + evt.when = _EVT_getTicks(); + evt.what = what; + evt.message = message | 0x10000UL; + evt.where_x = 0; + evt.where_y = 0; + evt.relative_x = 0; + evt.relative_y = 0; + evt.modifiers = EVT.keyModifiers; + if (evt.what == EVT_KEYREPEAT) { + if (EVT.oldKey != -1) + EVT.evtq[EVT.oldKey].message += 0x10000UL; + else { + EVT.oldKey = EVT.freeHead; + addEvent(&evt); /* Add to tail of event queue */ + } + } + else { +#ifdef __QNX__ + _EVT_maskKeyCode(&evt); +#endif + addEvent(&evt); /* Add to tail of event queue */ + } + EVT.oldMove = -1; + } +} + +/**************************************************************************** +REMARKS: +This function waits for the keyboard controller to set the ready-for-write +bit. +****************************************************************************/ +static int kbWaitForWriteReady(void) +{ + int timeout = 8192; + while ((timeout > 0) && (PM_inpb(0x64) & 0x02)) + timeout--; + return (timeout > 0); +} + +/**************************************************************************** +REMARKS: +This function waits for the keyboard controller to set the ready-for-read +bit. +****************************************************************************/ +static int kbWaitForReadReady(void) +{ + int timeout = 8192; + while ((timeout > 0) && (!(PM_inpb(0x64) & 0x01))) + timeout--; + return (timeout > 0); +} + +/**************************************************************************** +PARAMETERS: +data - Data to send to the keyboard + +REMARKS: +This function sends a data byte to the keyboard controller. +****************************************************************************/ +static int kbSendData( + uchar data) +{ + int resends = 4; + int timeout, temp; + + do { + if (!kbWaitForWriteReady()) + return 0; + PM_outpb(0x60,data); + timeout = 8192; + while (--timeout > 0) { + if (!kbWaitForReadReady()) + return 0; + temp = PM_inpb(0x60); + if (temp == 0xFA) + return 1; + if (temp == 0xFE) + break; + } + } while ((resends-- > 0) && (timeout > 0)); + return 0; +} + +/**************************************************************************** +PARAMETERS: +modifiers - Keyboard modifier flags + +REMARKS: +This function re-programs the LED's on the keyboard to the values stored +in the passed in modifier flags. If the 'allowLEDS' flag is false, this +function does nothing. +****************************************************************************/ +static void setLEDS( + uint modifiers) +{ + if (EVT.allowLEDS) { + if (!kbSendData(0xED) || !kbSendData((modifiers>>9) & 7)) { + kbSendData(0xF4); + } + } +} + +/**************************************************************************** +REMARKS: +Function to process raw scan codes read from the keyboard controller. + +NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, + and we leave them OFF the entire time. +{secret} +****************************************************************************/ +void processRawScanCode( + int scan) +{ + static int pauseLoop = 0; + static int extended = 0; + int what; + + if (pauseLoop) { + /* Skip scan codes until the pause key sequence has been read */ + pauseLoop--; + } + else if (scan == 0xE0) { + /* This signals the start of an extended scan code sequence */ + extended = 1; + } + else if (scan == 0xE1) { + /* The Pause key sends a strange scan code sequence, which is: + * + * E1 1D 52 E1 9D D2 + * + * However there is never any release code nor any auto-repeat for + * this key. For this reason we simply ignore the key and skip the + * next 5 scan codes read from the keyboard. + */ + pauseLoop = 5; + } + else { + /* Process the scan code normally (it may be an extended code + * however!). Bit 7 means key was released, and bits 0-6 are the + * scan code. + */ + what = (scan & 0x80) ? EVT_KEYUP : EVT_KEYDOWN; + scan &= 0x7F; + if (extended) { + extended = 0; + if (scan == 0x2A || scan == 0x36) { + /* Ignore these extended scan code sequences. These are + * used by the keyboard controller to wrap around certain + * key sequences for the keypad (and when NUMLOCK is down + * internally). + */ + return; + } + + /* Convert extended codes for key sequences that we map to + * virtual scan codes so the user can detect them in their + * code. + */ + switch (scan) { + case KB_leftCtrl: scan = KB_rightCtrl; break; + case KB_leftAlt: scan = KB_rightAlt; break; + case KB_divide: scan = KB_padDivide; break; + case KB_enter: scan = KB_padEnter; break; + case KB_padTimes: scan = KB_sysReq; break; + } + } + else { + /* Convert regular scan codes for key sequences that we map to + * virtual scan codes so the user can detect them in their + * code. + */ + switch (scan) { + case KB_left: scan = KB_padLeft; break; + case KB_right: scan = KB_padRight; break; + case KB_up: scan = KB_padUp; break; + case KB_down: scan = KB_padDown; break; + case KB_insert: scan = KB_padInsert; break; + case KB_delete: scan = KB_padDelete; break; + case KB_home: scan = KB_padHome; break; + case KB_end: scan = KB_padEnd; break; + case KB_pageUp: scan = KB_padPageUp; break; + case KB_pageDown: scan = KB_padPageDown; break; + } + } + + /* Determine if the key is an UP, DOWN or REPEAT and maintain the + * up/down status of all keys in our global key array. + */ + if (what == EVT_KEYDOWN) { + if (EVT.keyTable[scan]) + what = EVT_KEYREPEAT; + else + EVT.keyTable[scan] = scan; + } + else { + EVT.keyTable[scan] = 0; + } + + /* Handle shift key modifiers */ + if (what != EVT_KEYREPEAT) { + switch (scan) { + case KB_capsLock: + if (what == EVT_KEYDOWN) + EVT.keyModifiers ^= EVT_CAPSLOCK; + setLEDS(EVT.keyModifiers); + break; + case KB_numLock: + if (what == EVT_KEYDOWN) + EVT.keyModifiers ^= EVT_NUMLOCK; + setLEDS(EVT.keyModifiers); + break; + case KB_scrollLock: + if (what == EVT_KEYDOWN) + EVT.keyModifiers ^= EVT_SCROLLLOCK; + setLEDS(EVT.keyModifiers); + break; + case KB_leftShift: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_LEFTSHIFT; + else + EVT.keyModifiers |= EVT_LEFTSHIFT; + break; + case KB_rightShift: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_RIGHTSHIFT; + else + EVT.keyModifiers |= EVT_RIGHTSHIFT; + break; + case KB_leftCtrl: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_LEFTCTRL; + else + EVT.keyModifiers |= EVT_LEFTCTRL; + break; + case KB_rightCtrl: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_RIGHTCTRL; + else + EVT.keyModifiers |= EVT_RIGHTCTRL; + break; + case KB_leftAlt: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_LEFTALT; + else + EVT.keyModifiers |= EVT_LEFTALT; + break; + case KB_rightAlt: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_RIGHTALT; + else + EVT.keyModifiers |= EVT_RIGHTALT; + break; +#ifdef SUPPORT_CTRL_ALT_DEL + case KB_delete: + if ((EVT.keyModifiers & EVT_CTRLSTATE) && (EVT.keyModifiers & EVT_ALTSTATE)) + Reboot(); + break; +#endif + } + } + + /* Add the untranslated key code to the event queue. All + * translation to ASCII from the key codes occurs when the key + * is extracted from the queue, saving time in the low level + * interrupt handler. + */ + addKeyEvent(what,scan << 8); + } +} + +/**************************************************************************** +DESCRIPTION: +Enables/disables the update of the keyboard LED status indicators. + +HEADER: +event.h + +PARAMETERS: +enable - True to enable, false to disable + +REMARKS: +Enables the update of the keyboard LED status indicators. Sometimes it may +be convenient in the application to turn off the updating of the LED +status indicators (such as if a game is using the CAPSLOCK key for some +function). Passing in a value of FALSE to this function will turn off all +the LEDS, and stop updating them when the internal status changes (note +however that internally we still keep track of the toggle key status!). +****************************************************************************/ +void EVTAPI EVT_allowLEDS( + ibool enable) +{ + EVT.allowLEDS = true; + if (enable) + setLEDS(EVT.keyModifiers); + else + setLEDS(0); + EVT.allowLEDS = enable; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c b/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c new file mode 100644 index 0000000..83ef221 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c @@ -0,0 +1,205 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module for implementing the PM library overrideable memory +* allocator functions. +* +****************************************************************************/ + +#include "pmapi.h" + +/*--------------------------- Global variables ----------------------------*/ + +void * (*__PM_malloc)(size_t size) = malloc; +void * (*__PM_calloc)(size_t nelem,size_t size) = calloc; +void * (*__PM_realloc)(void *ptr,size_t size) = realloc; +void (*__PM_free)(void *p) = free; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +DESCRIPTION: +Use local memory allocation routines. + +HEADER: +pmapi.h + +PARAMETERS: +malloc - Pointer to new malloc routine to use +calloc - Pointer to new caalloc routine to use +realloc - Pointer to new realloc routine to use +free - Pointer to new free routine to use + +REMARKS: +Tells the PM library to use a set of user specified memory allocation +routines instead of using the normal malloc/calloc/realloc/free standard +C library functions. This is useful if you wish to use a third party +debugging malloc library or perhaps a set of faster memory allocation +functions with the PM library, or any apps that use the PM library (such as +the MGL). Once you have registered your memory allocation routines, all +calls to PM_malloc, PM_calloc, PM_realloc and PM_free will be revectored to +your local memory allocation routines. + +This is also useful if you need to keep track of just how much physical +memory your program has been using. You can use the PM_availableMemory +function to find out how much physical memory is available when the program +starts, and then you can use your own local memory allocation routines to +keep track of how much memory has been used and freed. + +NOTE: This function should be called right at the start of your application, + before you initialise any other components or libraries. + +NOTE: Code compiled into Binary Portable DLL's and Drivers automatically + end up calling these functions via the BPD C runtime library. + +SEE ALSO: +PM_malloc, PM_calloc, PM_realloc, PM_free, PM_availableMemory +****************************************************************************/ +void PMAPI PM_useLocalMalloc( + void * (*malloc)(size_t size), + void * (*calloc)(size_t nelem,size_t size), + void * (*realloc)(void *ptr,size_t size), + void (*free)(void *p)) +{ + __PM_malloc = malloc; + __PM_calloc = calloc; + __PM_realloc = realloc; + __PM_free = free; +} + +/**************************************************************************** +DESCRIPTION: +Allocate a block of memory. + +HEADER: +pmapi.h + +PARAMETERS: +size - Size of block to allocate in bytes + +RETURNS: +Pointer to allocated block, or NULL if out of memory. + +REMARKS: +Allocates a block of memory of length size. If you have changed the memory +allocation routines with the PM_useLocalMalloc function, then calls to this +function will actually make calls to the local memory allocation routines +that you have registered. + +SEE ALSO: +PM_calloc, PM_realloc, PM_free, PM_useLocalMalloc +****************************************************************************/ +void * PMAPI PM_malloc( + size_t size) +{ + return __PM_malloc(size); +} + +/**************************************************************************** +DESCRIPTION: +Allocate and clear a large memory block. + +HEADER: +pmapi.h + +PARAMETERS: +nelem - number of contiguous size-byte units to allocate +size - size of unit in bytes + +RETURNS: +Pointer to allocated memory if successful, NULL if out of memory. + +REMARKS: +Allocates a block of memory of length (size * nelem), and clears the +allocated area with zeros (0). If you have changed the memory allocation +routines with the PM_useLocalMalloc function, then calls to this function +will actually make calls to the local memory allocation routines that you +have registered. + +SEE ALSO: +PM_malloc, PM_realloc, PM_free, PM_useLocalMalloc +****************************************************************************/ +void * PMAPI PM_calloc( + size_t nelem, + size_t size) +{ + return __PM_calloc(nelem,size); +} + +/**************************************************************************** +DESCRIPTION: +Re-allocate a block of memory + +HEADER: +pmapi.h + +PARAMETERS: +ptr - Pointer to block to resize +size - size of unit in bytes + +RETURNS: +Pointer to allocated memory if successful, NULL if out of memory. + +REMARKS: +This function reallocates a block of memory that has been previously been +allocated to the new of size. The new size may be smaller or larger than +the original block of memory. If you have changed the memory allocation +routines with the PM_useLocalMalloc function, then calls to this function +will actually make calls to the local memory allocation routines that you +have registered. + +SEE ALSO: +PM_malloc, PM_calloc, PM_free, PM_useLocalMalloc +****************************************************************************/ +void * PMAPI PM_realloc( + void *ptr, + size_t size) +{ + return __PM_realloc(ptr,size); +} + +/**************************************************************************** +DESCRIPTION: +Frees a block of memory. + +HEADER: +pmapi.h + +PARAMETERS: +p - Pointer to memory block to free + +REMARKS: +Frees a block of memory previously allocated with either PM_malloc, +PM_calloc or PM_realloc. + +SEE ALSO: +PM_malloc, PM_calloc, PM_realloc, PM_useLocalMalloc +****************************************************************************/ +void PMAPI PM_free( + void *p) +{ + __PM_free(p); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c b/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c new file mode 100644 index 0000000..eed5f45 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c @@ -0,0 +1,867 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Heavily based on code copyright (C) Richard Gooch +* +* Language: ANSI C +* Environment: 32-bit Ring 0 device driver +* +* Description: Generic Memory Type Range Register (MTRR) functions to +* manipulate the MTRR registers on supported CPU's. This code +* *must* run at ring 0, so you can't normally include this +* code directly in normal applications (the except is DOS4GW +* apps which run at ring 0 under real DOS). Thus this code +* will normally be compiled into a ring 0 device driver for +* the target operating system. +* +****************************************************************************/ + +#include "pmapi.h" +#include "ztimerc.h" +#include "mtrr.h" + +#ifndef REALMODE + +/*--------------------------- Global variables ----------------------------*/ + +/* Intel pre-defined MTRR registers */ + +#define NUM_FIXED_RANGES 88 +#define INTEL_cap_MSR 0x0FE +#define INTEL_defType_MSR 0x2FF +#define INTEL_fix64K_00000_MSR 0x250 +#define INTEL_fix16K_80000_MSR 0x258 +#define INTEL_fix16K_A0000_MSR 0x259 +#define INTEL_fix4K_C0000_MSR 0x268 +#define INTEL_fix4K_C8000_MSR 0x269 +#define INTEL_fix4K_D0000_MSR 0x26A +#define INTEL_fix4K_D8000_MSR 0x26B +#define INTEL_fix4K_E0000_MSR 0x26C +#define INTEL_fix4K_E8000_MSR 0x26D +#define INTEL_fix4K_F0000_MSR 0x26E +#define INTEL_fix4K_F8000_MSR 0x26F + +/* Macros to find the address of a paricular MSR register */ + +#define INTEL_physBase_MSR(reg) (0x200 + 2 * (reg)) +#define INTEL_physMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +/* Cyrix CPU configuration register indexes */ +#define CX86_CCR0 0xC0 +#define CX86_CCR1 0xC1 +#define CX86_CCR2 0xC2 +#define CX86_CCR3 0xC3 +#define CX86_CCR4 0xE8 +#define CX86_CCR5 0xE9 +#define CX86_CCR6 0xEA +#define CX86_DIR0 0xFE +#define CX86_DIR1 0xFF +#define CX86_ARR_BASE 0xC4 +#define CX86_RCR_BASE 0xDC + +/* Structure to maintain machine state while updating MTRR registers */ + +typedef struct { + ulong flags; + ulong defTypeLo; + ulong defTypeHi; + ulong cr4Val; + ulong ccr3; + } MTRRContext; + +static int numMTRR = -1; +static int cpuFamily,cpuType,cpuStepping; +static void (*getMTRR)(uint reg,ulong *base,ulong *size,int *type) = NULL; +static void (*setMTRR)(uint reg,ulong base,ulong size,int type) = NULL; +static int (*getFreeRegion)(ulong base,ulong size) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +RETURNS: +Returns non-zero if we have the write-combining memory type +****************************************************************************/ +static int MTRR_haveWriteCombine(void) +{ + ulong config,dummy; + + switch (cpuFamily) { + case CPU_AMD: + if (cpuType < CPU_AMDAthlon) { + /* AMD K6-2 stepping 8 and later support the MTRR registers. + * The earlier K6-2 steppings (300Mhz models) do not + * support MTRR's. + */ + if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) + return 0; + return 1; + } + /* Fall through for AMD Athlon which uses P6 style MTRR's */ + case CPU_Intel: + _MTRR_readMSR(INTEL_cap_MSR,&config,&dummy); + return (config & (1 << 10)); + case CPU_Cyrix: + /* Cyrix 6x86 and later support the MTRR registers */ + if (cpuType < CPU_Cyrix6x86) + return 0; + return 1; + } + return 0; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region + +RETURNS: +The index of the region on success, else -1 on error. + +REMARKS: +Generic function to find the location of a free MTRR register to be used +for creating a new mapping. +****************************************************************************/ +static int GENERIC_getFreeRegion( + ulong base, + ulong size) +{ + int i,ltype; + ulong lbase,lsize; + + for (i = 0; i < numMTRR; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lsize < 1) + return i; + } + (void)base; + (void)size; + return -1; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region + +RETURNS: +The index of the region on success, else -1 on error. + +REMARKS: +Generic function to find the location of a free MTRR register to be used +for creating a new mapping. +****************************************************************************/ +static int AMDK6_getFreeRegion( + ulong base, + ulong size) +{ + int i,ltype; + ulong lbase,lsize; + + for (i = 0; i < numMTRR; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lsize < 1) + return i; + } + (void)base; + (void)size; + return -1; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region + +RETURNS: +The index of the region on success, else -1 on error. + +REMARKS: +Cyrix specific function to find the location of a free MTRR register to be +used for creating a new mapping. +****************************************************************************/ +static int CYRIX_getFreeRegion( + ulong base, + ulong size) +{ + int i,ltype; + ulong lbase, lsize; + + if (size > 0x2000000UL) { + /* If we are to set up a region >32M then look at ARR7 immediately */ + getMTRR(7,&lbase,&lsize,<ype); + if (lsize < 1) + return 7; + } + else { + /* Check ARR0-6 registers */ + for (i = 0; i < 7; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lsize < 1) + return i; + } + /* Try ARR7 but its size must be at least 256K */ + getMTRR(7,&lbase,&lsize,<ype); + if ((lsize < 1) && (size >= 0x40000)) + return i; + } + (void)base; + return -1; +} + +/**************************************************************************** +PARAMETERS: +c - Place to store the machine context across the call + +REMARKS: +Puts the processor into a state where MTRRs can be safely updated +****************************************************************************/ +static void MTRR_beginUpdate( + MTRRContext *c) +{ + c->flags = _MTRR_disableInt(); + if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) { + switch (cpuFamily) { + case CPU_Intel: + case CPU_AMD: + /* Disable MTRRs, and set the default type to uncached */ + c->cr4Val = _MTRR_saveCR4(); + _MTRR_readMSR(INTEL_defType_MSR,&c->defTypeLo,&c->defTypeHi); + _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo & 0xF300UL,c->defTypeHi); + break; + case CPU_Cyrix: + c->ccr3 = _MTRR_getCx86(CX86_CCR3); + _MTRR_setCx86(CX86_CCR3, (uchar)((c->ccr3 & 0x0F) | 0x10)); + break; + } + } +} + +/**************************************************************************** +PARAMETERS: +c - Place to restore the machine context from + +REMARKS: +Restores the processor after updating any of the registers +****************************************************************************/ +static void MTRR_endUpdate( + MTRRContext *c) +{ + if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) { + PM_flushTLB(); + switch (cpuFamily) { + case CPU_Intel: + case CPU_AMD: + _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo,c->defTypeHi); + _MTRR_restoreCR4(c->cr4Val); + break; + case CPU_Cyrix: + _MTRR_setCx86(CX86_CCR3,(uchar)c->ccr3); + break; + } + } + + /* Re-enable interrupts (if enabled previously) */ + _MTRR_restoreInt(c->flags); +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to read +base - Place to store the starting physical base address of the region +size - Place to store the size in bytes of the region +type - Place to store the type of the MTRR register + +REMARKS: +Intel specific function to read the value of a specific MTRR register. +****************************************************************************/ +static void INTEL_getMTRR( + uint reg, + ulong *base, + ulong *size, + int *type) +{ + ulong hi,maskLo,baseLo; + + _MTRR_readMSR(INTEL_physMask_MSR(reg),&maskLo,&hi); + if ((maskLo & 0x800) == 0) { + /* MTRR is disabled, so it is free */ + *base = 0; + *size = 0; + *type = 0; + return; + } + _MTRR_readMSR(INTEL_physBase_MSR(reg),&baseLo,&hi); + maskLo = (maskLo & 0xFFFFF000UL); + *size = ~(maskLo - 1); + *base = (baseLo & 0xFFFFF000UL); + *type = (baseLo & 0xFF); +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void INTEL_setMTRR( + uint reg, + ulong base, + ulong size, + int type) +{ + MTRRContext c; + + MTRR_beginUpdate(&c); + if (size == 0) { + /* The invalid bit is kept in the mask, so we simply clear the + * relevant mask register to disable a range. + */ + _MTRR_writeMSR(INTEL_physMask_MSR(reg),0,0); + } + else { + _MTRR_writeMSR(INTEL_physBase_MSR(reg),base | type,0); + _MTRR_writeMSR(INTEL_physMask_MSR(reg),~(size - 1) | 0x800,0); + } + MTRR_endUpdate(&c); +} + +/**************************************************************************** +REMARKS: +Disabled banked write combing for Intel processors. We always disable this +because it invariably causes problems with older hardware. +****************************************************************************/ +static void INTEL_disableBankedWriteCombine(void) +{ + MTRRContext c; + + MTRR_beginUpdate(&c); + _MTRR_writeMSR(INTEL_fix16K_A0000_MSR,0,0); + MTRR_endUpdate(&c); +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void AMD_getMTRR( + uint reg, + ulong *base, + ulong *size, + int *type) +{ + ulong low,high; + + /* Upper dword is region 1, lower is region 0 */ + _MTRR_readMSR(0xC0000085, &low, &high); + if (reg == 1) + low = high; + + /* Find the base and type for the region */ + *base = low & 0xFFFE0000; + *type = 0; + if (low & 1) + *type = PM_MTRR_UNCACHABLE; + if (low & 2) + *type = PM_MTRR_WRCOMB; + if ((low & 3) == 0) { + *size = 0; + return; + } + + /* This needs a little explaining. The size is stored as an + * inverted mask of bits of 128K granularity 15 bits long offset + * 2 bits + * + * So to get a size we do invert the mask and add 1 to the lowest + * mask bit (4 as its 2 bits in). This gives us a size we then shift + * to turn into 128K blocks + * + * eg 111 1111 1111 1100 is 512K + * + * invert 000 0000 0000 0011 + * +1 000 0000 0000 0100 + * *128K ... + */ + low = (~low) & 0x0FFFC; + *size = (low + 4) << 15; +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void AMD_setMTRR( + uint reg, + ulong base, + ulong size, + int type) +{ + ulong low,high,newVal; + MTRRContext c; + + MTRR_beginUpdate(&c); + _MTRR_readMSR(0xC0000085, &low, &high); + if (size == 0) { + /* Clear register to disable */ + if (reg) + high = 0; + else + low = 0; + } + else { + /* Set the register to the base (already shifted for us), the + * type (off by one) and an inverted bitmask of the size + * The size is the only odd bit. We are fed say 512K + * We invert this and we get 111 1111 1111 1011 but + * if you subtract one and invert you get the desired + * 111 1111 1111 1100 mask + */ + newVal = (((~(size-1)) >> 15) & 0x0001FFFC) | base | (type+1); + if (reg) + high = newVal; + else + low = newVal; + } + + /* The writeback rule is quite specific. See the manual. Its + * disable local interrupts, write back the cache, set the MTRR + */ + PM_flushTLB(); + _MTRR_writeMSR(0xC0000085, low, high); + MTRR_endUpdate(&c); +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void CYRIX_getMTRR( + uint reg, + ulong *base, + ulong *size, + int *type) +{ + MTRRContext c; + uchar arr = CX86_ARR_BASE + reg*3; + uchar rcr,shift; + + /* Save flags and disable interrupts */ + MTRR_beginUpdate(&c); + ((uchar*)base)[3] = _MTRR_getCx86(arr); + ((uchar*)base)[2] = _MTRR_getCx86((uchar)(arr+1)); + ((uchar*)base)[1] = _MTRR_getCx86((uchar)(arr+2)); + rcr = _MTRR_getCx86((uchar)(CX86_RCR_BASE + reg)); + MTRR_endUpdate(&c); + + /* Enable interrupts if it was enabled previously */ + shift = ((uchar*)base)[1] & 0x0f; + *base &= 0xFFFFF000UL; + + /* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7 + * Note: shift==0xF means 4G, this is unsupported. + */ + if (shift) + *size = (reg < 7 ? 0x800UL : 0x20000UL) << shift; + else + *size = 0; + + /* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */ + if (reg < 7) { + switch (rcr) { + case 1: *type = PM_MTRR_UNCACHABLE; break; + case 8: *type = PM_MTRR_WRBACK; break; + case 9: *type = PM_MTRR_WRCOMB; break; + case 24: + default: *type = PM_MTRR_WRTHROUGH; break; + } + } + else { + switch (rcr) { + case 0: *type = PM_MTRR_UNCACHABLE; break; + case 8: *type = PM_MTRR_WRCOMB; break; + case 9: *type = PM_MTRR_WRBACK; break; + case 25: + default: *type = PM_MTRR_WRTHROUGH; break; + } + } +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void CYRIX_setMTRR( + uint reg, + ulong base, + ulong size, + int type) +{ + MTRRContext c; + uchar arr = CX86_ARR_BASE + reg*3; + uchar arr_type,arr_size; + + /* Count down from 32M (ARR0-ARR6) or from 2G (ARR7) */ + size >>= (reg < 7 ? 12 : 18); + size &= 0x7FFF; /* Make sure arr_size <= 14 */ + for (arr_size = 0; size; arr_size++, size >>= 1) + ; + if (reg < 7) { + switch (type) { + case PM_MTRR_UNCACHABLE: arr_type = 1; break; + case PM_MTRR_WRCOMB: arr_type = 9; break; + case PM_MTRR_WRTHROUGH: arr_type = 24; break; + default: arr_type = 8; break; + } + } + else { + switch (type) { + case PM_MTRR_UNCACHABLE: arr_type = 0; break; + case PM_MTRR_WRCOMB: arr_type = 8; break; + case PM_MTRR_WRTHROUGH: arr_type = 25; break; + default: arr_type = 9; break; + } + } + MTRR_beginUpdate(&c); + _MTRR_setCx86((uchar)arr, ((uchar*)&base)[3]); + _MTRR_setCx86((uchar)(arr+1), ((uchar*)&base)[2]); + _MTRR_setCx86((uchar)(arr+2), (uchar)((((uchar*)&base)[1]) | arr_size)); + _MTRR_setCx86((uchar)(CX86_RCR_BASE + reg), (uchar)arr_type); + MTRR_endUpdate(&c); +} + +/**************************************************************************** +REMARKS: +On Cyrix 6x86(MX) and MII the ARR3 is special: it has connection +with the SMM (System Management Mode) mode. So we need the following: +Check whether SMI_LOCK (CCR3 bit 0) is set + if it is set, ARR3 cannot be changed (it cannot be changed until the + next processor reset) + if it is reset, then we can change it, set all the needed bits: + - disable access to SMM memory through ARR3 range (CCR1 bit 7 reset) + - disable access to SMM memory (CCR1 bit 2 reset) + - disable SMM mode (CCR1 bit 1 reset) + - disable write protection of ARR3 (CCR6 bit 1 reset) + - (maybe) disable ARR3 +Just to be sure, we enable ARR usage by the processor (CCR5 bit 5 set) +****************************************************************************/ +static void CYRIX_initARR(void) +{ + MTRRContext c; + uchar ccr[7]; + int ccrc[7] = { 0, 0, 0, 0, 0, 0, 0 }; + + /* Begin updating */ + MTRR_beginUpdate(&c); + + /* Save all CCRs locally */ + ccr[0] = _MTRR_getCx86(CX86_CCR0); + ccr[1] = _MTRR_getCx86(CX86_CCR1); + ccr[2] = _MTRR_getCx86(CX86_CCR2); + ccr[3] = (uchar)c.ccr3; + ccr[4] = _MTRR_getCx86(CX86_CCR4); + ccr[5] = _MTRR_getCx86(CX86_CCR5); + ccr[6] = _MTRR_getCx86(CX86_CCR6); + if (ccr[3] & 1) + ccrc[3] = 1; + else { + /* Disable SMM mode (bit 1), access to SMM memory (bit 2) and + * access to SMM memory through ARR3 (bit 7). + */ + if (ccr[6] & 0x02) { + ccr[6] &= 0xFD; + ccrc[6] = 1; /* Disable write protection of ARR3. */ + _MTRR_setCx86(CX86_CCR6,ccr[6]); + } + } + + /* If we changed CCR1 in memory, change it in the processor, too. */ + if (ccrc[1]) + _MTRR_setCx86(CX86_CCR1,ccr[1]); + + /* Enable ARR usage by the processor */ + if (!(ccr[5] & 0x20)) { + ccr[5] |= 0x20; + ccrc[5] = 1; + _MTRR_setCx86(CX86_CCR5,ccr[5]); + } + + /* We are finished updating */ + MTRR_endUpdate(&c); +} + +/**************************************************************************** +REMARKS: +Initialise the MTRR module, by detecting the processor type and determining +if the processor supports the MTRR functionality. +****************************************************************************/ +void MTRR_init(void) +{ + int i,cpu,ltype; + ulong eax,edx,lbase,lsize; + + /* Check that we have a compatible CPU */ + if (numMTRR == -1) { + numMTRR = 0; + if (!_MTRR_isRing0()) + return; + cpu = CPU_getProcessorType(); + cpuFamily = cpu & CPU_familyMask; + cpuType = cpu & CPU_mask; + cpuStepping = (cpu & CPU_steppingMask) >> CPU_steppingShift; + switch (cpuFamily) { + case CPU_Intel: + /* Intel Pentium Pro and later support the MTRR registers */ + if (cpuType < CPU_PentiumPro) + return; + _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); + numMTRR = eax & 0xFF; + getMTRR = INTEL_getMTRR; + setMTRR = INTEL_setMTRR; + getFreeRegion = GENERIC_getFreeRegion; + INTEL_disableBankedWriteCombine(); + break; + case CPU_AMD: + /* AMD K6-2 and later support the MTRR registers */ + if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) + return; + if (cpuType < CPU_AMDAthlon) { + numMTRR = 2; /* AMD CPU's have 2 MTRR's */ + getMTRR = AMD_getMTRR; + setMTRR = AMD_setMTRR; + getFreeRegion = AMDK6_getFreeRegion; + + /* For some reason some IBM systems with K6-2 processors + * have write combined enabled for the system BIOS + * region from 0xE0000 to 0xFFFFFF. We need *both* MTRR's + * for our own graphics drivers, so if we detect any + * regions below the 1Meg boundary, we remove them + * so we can use this MTRR register ourselves. + */ + for (i = 0; i < numMTRR; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lbase < 0x100000) + setMTRR(i,0,0,0); + } + } + else { + /* AMD Athlon uses P6 style MTRR's */ + _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); + numMTRR = eax & 0xFF; + getMTRR = INTEL_getMTRR; + setMTRR = INTEL_setMTRR; + getFreeRegion = GENERIC_getFreeRegion; + INTEL_disableBankedWriteCombine(); + } + break; + case CPU_Cyrix: + /* Cyrix 6x86 and later support the MTRR registers */ + if (cpuType < CPU_Cyrix6x86 || cpuType >= CPU_CyrixMediaGX) + return; + numMTRR = 8; /* Cyrix CPU's have 8 ARR's */ + getMTRR = CYRIX_getMTRR; + setMTRR = CYRIX_setMTRR; + getFreeRegion = CYRIX_getFreeRegion; + CYRIX_initARR(); + break; + default: + return; + } + } +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int MTRR_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + int i; + int ltype; + ulong lbase,lsize,last; + + /* Check that we have a CPU that supports MTRR's and type is valid */ + if (numMTRR <= 0) { + if (!_MTRR_isRing0()) + return PM_MTRR_ERR_NO_OS_SUPPORT; + return PM_MTRR_NOT_SUPPORTED; + } + if (type >= PM_MTRR_MAX) + return PM_MTRR_ERR_PARAMS; + + /* If the type is WC, check that this processor supports it */ + if (!MTRR_haveWriteCombine()) + return PM_MTRR_ERR_NOWRCOMB; + + /* Adjust the boundaries depending on the CPU type */ + switch (cpuFamily) { + case CPU_AMD: + if (cpuType < CPU_AMDAthlon) { + /* Apply the K6 block alignment and size rules. In order: + * o Uncached or gathering only + * o 128K or bigger block + * o Power of 2 block + * o base suitably aligned to the power + */ + if (type > PM_MTRR_WRCOMB && (size < (1 << 17) || (size & ~(size-1))-size || (base & (size-1)))) + return PM_MTRR_ERR_NOT_ALIGNED; + break; + } + /* Fall through for AMD Athlon which uses P6 style MTRR's */ + case CPU_Intel: + case CPU_Cyrix: + if ((base & 0xFFF) || (size & 0xFFF)) { + /* Base and size must be multiples of 4Kb */ + return PM_MTRR_ERR_NOT_4KB_ALIGNED; + } + if (base < 0x100000) { + /* Base must be >= 1Mb */ + return PM_MTRR_ERR_BELOW_1MB; + } + + /* Check upper bits of base and last are equal and lower bits + * are 0 for base and 1 for last + */ + last = base + size - 1; + for (lbase = base; !(lbase & 1) && (last & 1); lbase = lbase >> 1, last = last >> 1) + ; + if (lbase != last) { + /* Base is not aligned on the correct boundary */ + return PM_MTRR_ERR_NOT_ALIGNED; + } + break; + default: + return PM_MTRR_NOT_SUPPORTED; + } + + /* Search for existing MTRR */ + for (i = 0; i < numMTRR; ++i) { + getMTRR(i,&lbase,&lsize,<ype); + if (lbase == 0 && lsize == 0) + continue; + if (base > lbase + (lsize-1)) + continue; + if ((base < lbase) && (base+size-1 < lbase)) + continue; + + /* Check that we don't overlap an existing region */ + if (type != PM_MTRR_UNCACHABLE) { + if ((base < lbase) || (base+size-1 > lbase+lsize-1)) + return PM_MTRR_ERR_OVERLAP; + } + else if (base == lbase && size == lsize) { + /* The region already exists so leave it alone */ + return PM_MTRR_ERR_OK; + } + + /* New region is enclosed by an existing region, so only allow + * a new type to be created if we are setting a region to be + * uncacheable (such as MMIO registers within a framebuffer). + */ + if (ltype != (int)type) { + if (type == PM_MTRR_UNCACHABLE) + continue; + return PM_MTRR_ERR_TYPE_MISMATCH; + } + return PM_MTRR_ERR_OK; + } + + /* Search for an empty MTRR */ + if ((i = getFreeRegion(base,size)) < 0) + return PM_MTRR_ERR_NONE_FREE; + setMTRR(i,base,size,type); + return PM_MTRR_ERR_OK; +} + +/**************************************************************************** +PARAMETERS: +callback - Function to callback with write combine information + +REMARKS: +Function to enumerate all write combine regions currently enabled for the +processor. +****************************************************************************/ +int PMAPI PM_enumWriteCombine( + PM_enumWriteCombine_t callback) +{ + int i,ltype; + ulong lbase,lsize; + + /* Check that we have a CPU that supports MTRR's and type is valid */ + if (numMTRR <= 0) { + if (!_MTRR_isRing0()) + return PM_MTRR_ERR_NO_OS_SUPPORT; + return PM_MTRR_NOT_SUPPORTED; + } + + /* Enumerate all existing MTRR's */ + for (i = 0; i < numMTRR; ++i) { + getMTRR(i,&lbase,&lsize,<ype); + callback(lbase,lsize,ltype); + } + return PM_MTRR_ERR_OK; +} +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c b/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c new file mode 100644 index 0000000..1d542fc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c @@ -0,0 +1,747 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module for interfacing to the PCI bus and configuration +* space registers. +* +****************************************************************************/ + +#include "pmapi.h" +#include "pcilib.h" +#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) +#include +#endif + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/* Length of the memory mapping for the PCI BIOS */ + +#define BIOS_LIMIT (128 * 1024L - 1) + +/* Macros for accessing the PCI BIOS functions from 32-bit protected mode */ + +#define BIOS32_SIGNATURE (((ulong)'_' << 0) + ((ulong)'3' << 8) + ((ulong)'2' << 16) + ((ulong)'_' << 24)) +#define PCI_SIGNATURE (((ulong)'P' << 0) + ((ulong)'C' << 8) + ((ulong)'I' << 16) + ((ulong)' ' << 24)) +#define PCI_SERVICE (((ulong)'$' << 0) + ((ulong)'P' << 8) + ((ulong)'C' << 16) + ((ulong)'I' << 24)) +#define PCI_BIOS_PRESENT 0xB101 +#define FIND_PCI_DEVICE 0xB102 +#define FIND_PCI_CLASS 0xB103 +#define GENERATE_SPECIAL 0xB106 +#define READ_CONFIG_BYTE 0xB108 +#define READ_CONFIG_WORD 0xB109 +#define READ_CONFIG_DWORD 0xB10A +#define WRITE_CONFIG_BYTE 0xB10B +#define WRITE_CONFIG_WORD 0xB10C +#define WRITE_CONFIG_DWORD 0xB10D +#define GET_IRQ_ROUTING_OPT 0xB10E +#define SET_PCI_IRQ 0xB10F + +/* This is the standard structure used to identify the entry point to the + * BIOS32 Service Directory, as documented in PCI 2.1 BIOS Specicition. + */ + +typedef union { + struct { + ulong signature; /* _32_ */ + ulong entry; /* 32 bit physical address */ + uchar revision; /* Revision level, 0 */ + uchar length; /* Length in paragraphs should be 01 */ + uchar checksum; /* All bytes must add up to zero */ + uchar reserved[5]; /* Must be zero */ + } fields; + char chars[16]; + } PCI_bios32; + +/* Structure for a far pointer to call the PCI BIOS services with */ + +typedef struct { + ulong address; + ushort segment; + } PCIBIOS_entry; + +/* Macros to copy a structure that includes dwSize members */ + +#define COPY_STRUCTURE(d,s) memcpy(d,s,MIN((s)->dwSize,(d)->dwSize)) + +#pragma pack() + +/*--------------------------- Global variables ----------------------------*/ + +static uchar *BIOSImage = NULL; /* BIOS image mapping */ +static int PCIBIOSVersion = -1;/* PCI BIOS version */ +static PCIBIOS_entry PCIEntry; /* PCI services entry point */ +static ulong PCIPhysEntry = 0; /* Physical address */ + +/*----------------------------- Implementation ----------------------------*/ + +/* External assembler helper functions */ + +uchar _ASMAPI _BIOS32_service(ulong service,ulong function,ulong *physBase,ulong *length,ulong *serviceOffset,PCIBIOS_entry entry); +ushort _ASMAPI _PCIBIOS_isPresent(ulong i_eax,ulong *o_edx,ushort *o_ax,uchar *o_cl,PCIBIOS_entry entry); +ulong _ASMAPI _PCIBIOS_service(ulong r_eax,ulong r_ebx,ulong r_edi,ulong r_ecx,PCIBIOS_entry entry); +int _ASMAPI _PCIBIOS_getRouting(PCIRoutingOptionsBuffer *buf,PCIBIOS_entry entry); +ibool _ASMAPI _PCIBIOS_setIRQ(int busDev,int intPin,int IRQ,PCIBIOS_entry entry); +ulong _ASMAPI _PCIBIOS_specialCycle(int bus,ulong data,PCIBIOS_entry entry); +ushort _ASMAPI _PCI_getCS(void); + +/**************************************************************************** +REMARKS: +This functions returns the physical address of the PCI BIOS entry point. +****************************************************************************/ +ulong _ASMAPI PCIBIOS_getEntry(void) +{ return PCIPhysEntry; } + +/**************************************************************************** +PARAMETERS: +hwType - Place to store the PCI hardware access mechanism flags +lastBus - Place to store the index of the last PCI bus in the system + +RETURNS: +Version number of the PCI BIOS found. + +REMARKS: +This function determines if the PCI BIOS is present in the system, and if +so returns the information returned by the PCI BIOS detect function. +****************************************************************************/ +static int PCIBIOS_detect( + uchar *hwType, + uchar *lastBus) +{ + ulong signature; + ushort stat,version; + +#ifndef __16BIT__ + PCIBIOS_entry BIOSEntry = {0}; + uchar *BIOSEnd; + PCI_bios32 *BIOSDir; + ulong physBase,length,offset; + + /* Bail if we have already detected no BIOS is present */ + if (PCIBIOSVersion == 0) + return 0; + + /* First scan the memory from 0xE0000 to 0xFFFFF looking for the + * BIOS32 service directory, so we can determine if we can call it + * from 32-bit protected mode. + */ + if (PCIBIOSVersion == -1) { + PCIBIOSVersion = 0; + BIOSImage = PM_mapPhysicalAddr(0xE0000,BIOS_LIMIT,false); + if (!BIOSImage) + return 0; + BIOSEnd = BIOSImage + 0x20000; + for (BIOSDir = (PCI_bios32*)BIOSImage; BIOSDir < (PCI_bios32*)BIOSEnd; BIOSDir++) { + uchar sum; + int i,length; + + if (BIOSDir->fields.signature != BIOS32_SIGNATURE) + continue; + length = BIOSDir->fields.length * 16; + if (!length) + continue; + for (sum = i = 0; i < length ; i++) + sum += BIOSDir->chars[i]; + if (sum != 0) + continue; + BIOSEntry.address = (ulong)BIOSImage + (BIOSDir->fields.entry - 0xE0000); + BIOSEntry.segment = _PCI_getCS(); + break; + } + + /* If we found the BIOS32 directory, call it to get the address of the + * PCI services. + */ + if (BIOSEntry.address == 0) + return 0; + if (_BIOS32_service(PCI_SERVICE,0,&physBase,&length,&offset,BIOSEntry) != 0) + return 0; + PCIPhysEntry = physBase + offset; + PCIEntry.address = (ulong)BIOSImage + (PCIPhysEntry - 0xE0000); + PCIEntry.segment = _PCI_getCS(); + } +#endif + /* We found the BIOS entry, so now do the version check */ + version = _PCIBIOS_isPresent(PCI_BIOS_PRESENT,&signature,&stat,lastBus,PCIEntry); + if (version > 0 && ((stat >> 8) == 0) && signature == PCI_SIGNATURE) { + *hwType = stat & 0xFF; + return PCIBIOSVersion = version; + } + return 0; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to check against +index - Index of the current device to check + +RETURNS: +True if the device is a duplicate, false if not. + +REMARKS: +This function goes through the list of all devices preceeding the newly +found device in the info structure, and checks that the device is not a +duplicate of a previous device. Some devices incorrectly enumerate +themselves at different function addresses so we check here to exclude +those cases. +****************************************************************************/ +static ibool CheckDuplicate( + PCIDeviceInfo *info, + PCIDeviceInfo *prev) +{ + /* Ignore devices with a vendor ID of 0 */ + if (info->VendorID == 0) + return true; + + /* NOTE: We only check against the current device on + * the bus to ensure that we do not exclude + * multiple controllers of the same device ID. + */ + if (info->slot.p.Bus == prev->slot.p.Bus && + info->slot.p.Device == prev->slot.p.Device && + info->DeviceID == prev->DeviceID) + return true; + return false; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +static int PCI_enumerateMech1( + PCIDeviceInfo info[]) +{ + int bus,device,function,i,numFound = 0; + ulong *lp,tmp; + PCIslot slot = {{0,0,0,0,0,0,1}}; + PCIDeviceInfo pci,prev = {0}; + + /* Try PCI access mechanism 1 */ + PM_outpb(0xCFB,0x01); + tmp = PM_inpd(0xCF8); + PM_outpd(0xCF8,slot.i); + if ((PM_inpd(0xCF8) == slot.i) && (PM_inpd(0xCFC) != 0xFFFFFFFFUL)) { + /* PCI access mechanism 1 - the preferred mechanism */ + for (bus = 0; bus < 8; bus++) { + slot.p.Bus = bus; + for (device = 0; device < 32; device++) { + slot.p.Device = device; + for (function = 0; function < 8; function++) { + slot.p.Function = function; + slot.p.Register = 0; + PM_outpd(0xCF8,slot.i); + if (PM_inpd(0xCFC) != 0xFFFFFFFFUL) { + memset(&pci,0,sizeof(pci)); + pci.dwSize = sizeof(pci); + pci.mech1 = 1; + pci.slot = slot; + lp = (ulong*)&(pci.VendorID); + for (i = 0; i < NUM_PCI_REG; i++, lp++) { + slot.p.Register = i; + PM_outpd(0xCF8,slot.i); + *lp = PM_inpd(0xCFC); + } + if (!CheckDuplicate(&pci,&prev)) { + if (info) + COPY_STRUCTURE(&info[numFound],&pci); + ++numFound; + } + prev = pci; + } + } + } + } + + /* Disable PCI config cycle on exit */ + PM_outpd(0xCF8,0); + return numFound; + } + PM_outpd(0xCF8,tmp); + + /* No hardware access mechanism 1 found */ + return 0; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +static int PCI_enumerateMech2( + PCIDeviceInfo info[]) +{ + int bus,device,function,i,numFound = 0; + ushort deviceIO; + ulong *lp; + PCIslot slot = {{0,0,0,0,0,0,1}}; + PCIDeviceInfo pci,prev = {0}; + + /* Try PCI access mechanism 2 */ + PM_outpb(0xCFB,0x00); + PM_outpb(0xCF8,0x00); + PM_outpb(0xCFA,0x00); + if (PM_inpb(0xCF8) == 0x00 && PM_inpb(0xCFB) == 0x00) { + /* PCI access mechanism 2 - the older mechanism for legacy busses */ + for (bus = 0; bus < 2; bus++) { + slot.p.Bus = bus; + PM_outpb(0xCFA,(uchar)bus); + for (device = 0; device < 16; device++) { + slot.p.Device = device; + deviceIO = 0xC000 + (device << 8); + for (function = 0; function < 8; function++) { + slot.p.Function = function; + slot.p.Register = 0; + PM_outpb(0xCF8,(uchar)((function << 1) | 0x10)); + if (PM_inpd(deviceIO) != 0xFFFFFFFFUL) { + memset(&pci,0,sizeof(pci)); + pci.dwSize = sizeof(pci); + pci.mech1 = 0; + pci.slot = slot; + lp = (ulong*)&(pci.VendorID); + for (i = 0; i < NUM_PCI_REG; i++, lp++) { + slot.p.Register = i; + *lp = PM_inpd(deviceIO + (i << 2)); + } + if (!CheckDuplicate(&pci,&prev)) { + if (info) + COPY_STRUCTURE(&info[numFound],&pci); + ++numFound; + } + prev = pci; + } + } + } + } + + /* Disable PCI config cycle on exit */ + PM_outpb(0xCF8,0); + return numFound; + } + + /* No hardware access mechanism 2 found */ + return 0; +} + +/**************************************************************************** +REMARKS: +This functions reads a configuration dword via the PCI BIOS. +****************************************************************************/ +static ulong PCIBIOS_readDWORD( + int index, + ulong slot) +{ + return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,slot >> 8,index,0,PCIEntry); +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +static int PCI_enumerateBIOS( + PCIDeviceInfo info[]) +{ + uchar hwType,lastBus; + int bus,device,function,i,numFound = 0; + ulong *lp; + PCIslot slot = {{0,0,0,0,0,0,1}}; + PCIDeviceInfo pci,prev = {0}; + + if (PCIBIOS_detect(&hwType,&lastBus)) { + /* PCI BIOS access - the ultimate fallback */ + for (bus = 0; bus <= lastBus; bus++) { + slot.p.Bus = bus; + for (device = 0; device < 32; device++) { + slot.p.Device = device; + for (function = 0; function < 8; function++) { + slot.p.Function = function; + if (PCIBIOS_readDWORD(0,slot.i) != 0xFFFFFFFFUL) { + memset(&pci,0,sizeof(pci)); + pci.dwSize = sizeof(pci); + pci.mech1 = 2; + pci.slot = slot; + lp = (ulong*)&(pci.VendorID); + for (i = 0; i < NUM_PCI_REG; i++, lp++) + *lp = PCIBIOS_readDWORD(i << 2,slot.i); + if (!CheckDuplicate(&pci,&prev)) { + if (info) + COPY_STRUCTURE(&info[numFound],&pci); + ++numFound; + } + prev = pci; + } + } + } + } + } + + /* Return number of devices found */ + return numFound; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +int _ASMAPI PCI_enumerate( + PCIDeviceInfo info[]) +{ + int numFound; + + /* First try via the direct access mechanisms which are faster if we + * have them (nearly always). The BIOS is used as a fallback, and for + * stuff we can't do directly. + */ + if ((numFound = PCI_enumerateMech1(info)) == 0) { + if ((numFound = PCI_enumerateMech2(info)) == 0) { + if ((numFound = PCI_enumerateBIOS(info)) == 0) + return 0; + } + } + return numFound; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +int _ASMAPI PCI_getNumDevices(void) +{ + return PCI_enumerate(NULL); +} + +/**************************************************************************** +PARAMETERS: +bar - Base address to measure +pci - PCI device to access + +RETURNS: +Size of the PCI base address in bytes + +REMARKS: +This function measures the size of the PCI base address register in bytes, +by writing all F's to the register, and reading the value back. The size +of the base address is determines by the bits that are hardwired to zero's. +****************************************************************************/ +ulong _ASMAPI PCI_findBARSize( + int bar, + PCIDeviceInfo *pci) +{ + ulong base,size = 0; + + base = PCI_accessReg(bar,0,PCI_READ_DWORD,pci); + if (base && !(base & 0x1)) { + /* For some strange reason some devices don't properly decode + * their base address registers (Intel PCI/PCI bridges!), and + * we read completely bogus values. We check for that here + * and clear out those BAR's. + * + * We check for that here because at least the low 12 bits + * of the address range must be zeros, since the page size + * on IA32 processors is always 4Kb. + */ + if ((base & 0xFFF) == 0) { + PCI_accessReg(bar,0xFFFFFFFF,PCI_WRITE_DWORD,pci); + size = PCI_accessReg(bar,0,PCI_READ_DWORD,pci) & ~0xFF; + size = ~size+1; + PCI_accessReg(bar,base,PCI_WRITE_DWORD,pci); + } + } + pci->slot.p.Register = 0; + return size; +} + +/**************************************************************************** +PARAMETERS: +index - DWORD index of the register to access +value - Value to write to the register for write access +func - Function to implement + +RETURNS: +The value read from the register for read operations + +REMARKS: +The function code are defined as follows + +code - function +0 - Read BYTE +1 - Read WORD +2 - Read DWORD +3 - Write BYTE +4 - Write WORD +5 - Write DWORD +****************************************************************************/ +ulong _ASMAPI PCI_accessReg( + int index, + ulong value, + int func, + PCIDeviceInfo *info) +{ + int iobase; + + if (info->mech1 == 2) { + /* Use PCI BIOS access since we dont have direct hardware access */ + switch (func) { + case PCI_READ_BYTE: + return (uchar)_PCIBIOS_service(READ_CONFIG_BYTE,info->slot.i >> 8,index,0,PCIEntry); + case PCI_READ_WORD: + return (ushort)_PCIBIOS_service(READ_CONFIG_WORD,info->slot.i >> 8,index,0,PCIEntry); + case PCI_READ_DWORD: + return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,info->slot.i >> 8,index,0,PCIEntry); + case PCI_WRITE_BYTE: + _PCIBIOS_service(WRITE_CONFIG_BYTE,info->slot.i >> 8,index,value,PCIEntry); + break; + case PCI_WRITE_WORD: + _PCIBIOS_service(WRITE_CONFIG_WORD,info->slot.i >> 8,index,value,PCIEntry); + break; + case PCI_WRITE_DWORD: + _PCIBIOS_service(WRITE_CONFIG_DWORD,info->slot.i >> 8,index,value,PCIEntry); + break; + } + } + else { + /* Use direct hardware access mechanisms */ + if (info->mech1) { + /* PCI access mechanism 1 */ + iobase = 0xCFC + (index & 3); + info->slot.p.Register = index >> 2; + PM_outpd(0xCF8,info->slot.i); + } + else { + /* PCI access mechanism 2 */ + PM_outpb(0xCF8,(uchar)((info->slot.p.Function << 1) | 0x10)); + PM_outpb(0xCFA,(uchar)info->slot.p.Bus); + iobase = 0xC000 + (info->slot.p.Device << 8) + index; + } + switch (func) { + case PCI_READ_BYTE: + case PCI_READ_WORD: + case PCI_READ_DWORD: value = PM_inpd(iobase); break; + case PCI_WRITE_BYTE: PM_outpb(iobase,(uchar)value); break; + case PCI_WRITE_WORD: PM_outpw(iobase,(ushort)value); break; + case PCI_WRITE_DWORD: PM_outpd(iobase,(ulong)value); break; + } + PM_outpd(0xCF8,0); + } + return value; +} + +/**************************************************************************** +PARAMETERS: +numDevices - Number of devices to query info for + +RETURNS: +0 on success, -1 on error, number of devices to enumerate if numDevices = 0 + +REMARKS: +This function reads the PCI routing information. If you pass a value of +0 for numDevices, this function will return with the number of devices +needed in the routing buffer that will be filled in by the BIOS. +****************************************************************************/ +ibool _ASMAPI PCI_getIRQRoutingOptions( + int numDevices, + PCIRouteInfo *buffer) +{ + PCIRoutingOptionsBuffer buf; + int ret; + + if (PCIPhysEntry) { + buf.BufferSize = numDevices * sizeof(PCIRouteInfo); + buf.DataBuffer = buffer; + if ((ret = _PCIBIOS_getRouting(&buf,PCIEntry)) == 0x89) + return buf.BufferSize / sizeof(PCIRouteInfo); + if (ret != 0) + return -1; + return 0; + } + + /* We currently only support this via the PCI BIOS functions */ + return -1; +} + +/**************************************************************************** +PARAMETERS: +info - PCI device information for the specified device +intPin - Value to store in the PCI InterruptPin register +IRQ - New ISA IRQ to map the PCI interrupt to (0-15) + +RETURNS: +True on success, or false if this function failed. + +REMARKS: +This function changes the PCI IRQ routing for the specified device to the +desired PCI interrupt and the desired ISA bus compatible IRQ. This function +may not be supported by the PCI BIOS, in which case this function will +fail. +****************************************************************************/ +ibool _ASMAPI PCI_setHardwareIRQ( + PCIDeviceInfo *info, + uint intPin, + uint IRQ) +{ + if (PCIPhysEntry) { + if (_PCIBIOS_setIRQ(info->slot.i >> 8,intPin,IRQ,PCIEntry)) { + info->u.type0.InterruptPin = intPin; + info->u.type0.InterruptLine = IRQ; + return true; + } + return false; + } + + /* We currently only support this via the PCI BIOS functions */ + return false; +} + +/**************************************************************************** +PARAMETERS: +bus - Bus number to generate the special cycle for +specialCycleData - Data to send for the special cyle + +REMARKS: +This function generates a special cycle on the specified bus using with +the specified data. +****************************************************************************/ +void _ASMAPI PCI_generateSpecialCyle( + uint bus, + ulong specialCycleData) +{ + if (PCIPhysEntry) + _PCIBIOS_specialCycle(bus,specialCycleData,PCIEntry); + /* We currently only support this via the PCI BIOS functions */ +} + +/**************************************************************************** +PARAMETERS: +info - PCI device information block for device to access +index - Index of register to start reading from +dst - Place to store the values read from configuration space +count - Count of bytes to read from configuration space + +REMARKS: +This function is used to read a block of PCI configuration space registers +from the configuration space into the passed in data block. This function +will properly handle reading non-DWORD aligned data from the configuration +space correctly. +****************************************************************************/ +void _ASMAPI PCI_readRegBlock( + PCIDeviceInfo *info, + int index, + void *dst, + int count) +{ + uchar *pb; + ulong *pd; + int i; + int startCount = (index & 3); + int middleCount = (count - startCount) >> 2; + int endCount = count - middleCount * 4 - startCount; + + for (i = 0,pb = dst; i < startCount; i++, index++) { + *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); + } + for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) { + *pd++ = (ulong)PCI_accessReg(index,0,PCI_READ_DWORD,info); + } + for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) { + *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); + } +} + +/**************************************************************************** +PARAMETERS: +info - PCI device information block for device to access +index - Index of register to start reading from +dst - Place to store the values read from configuration space +count - Count of bytes to read from configuration space + +REMARKS: +This function is used to write a block of PCI configuration space registers +to the configuration space from the passed in data block. This function +will properly handle writing non-DWORD aligned data to the configuration +space correctly. +****************************************************************************/ +void _ASMAPI PCI_writeRegBlock( + PCIDeviceInfo *info, + int index, + void *src, + int count) +{ + uchar *pb; + ulong *pd; + int i; + int startCount = (index & 3); + int middleCount = (count - startCount) >> 2; + int endCount = count - middleCount * 4 - startCount; + + for (i = 0,pb = src; i < startCount; i++, index++) { + PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); + } + for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) { + PCI_accessReg(index,*pd++,PCI_WRITE_DWORD,info); + } + for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) { + PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c b/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c new file mode 100644 index 0000000..c3a66a7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c @@ -0,0 +1,306 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module containing Unix I/O functions. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include +#include +#include +#include +#include + +/*----------------------------- Implementation ----------------------------*/ + +/* {secret} */ +typedef struct { + DIR *d; + char path[PM_MAX_PATH]; + char mask[PM_MAX_PATH]; + } PM_findHandle; + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + struct dirent *blk, + const char *path) +{ + ulong dwSize = findData->dwSize; + struct stat st; + char filename[PM_MAX_PATH]; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + strcpy(filename,path); + PM_backslash(filename); + strcat(filename,blk->d_name); + stat(filename,&st); + if (!(st.st_mode & S_IWRITE)) + findData->attrib |= PM_FILE_READONLY; + if (st.st_mode & S_IFDIR) + findData->attrib |= PM_FILE_DIRECTORY; + findData->sizeLo = st.st_size; + findData->sizeHi = 0; + strncpy(findData->name,blk->d_name,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +/**************************************************************************** +REMARKS: +Determines if a file name matches the passed in pattern. +****************************************************************************/ +static ibool filematch( + char *pattern, + char *dirpath, + struct dirent *dire) +{ + struct stat st; + int i = 0,j = 0,lastchar = '\0'; + char fullpath[PM_MAX_PATH]; + + strcpy(fullpath,dirpath); + PM_backslash(fullpath); + strcat(fullpath, dire->d_name); + if (stat(fullpath, &st) != 0) + return false; + for (; i < (int)strlen(dire->d_name) && j < (int)strlen(pattern); i++, j++) { + if (pattern[j] == '*' && lastchar != '\\') { + if (pattern[j+1] == '\0') + return true; + while (dire->d_name[i++] != pattern[j+1]) { + if (dire->d_name[i] == '\0') + return false; + } + i -= 2; + } + else if (dire->d_name[i] != pattern[j] && + !(pattern[j] == '?' && lastchar != '\\')) + return false; + lastchar = pattern[i]; + } + if (j == (int)strlen(pattern) && i == (int)strlen(dire->d_name)) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void * PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + PM_findHandle *d; + struct dirent *dire; + char name[PM_MAX_PATH]; + char ext[PM_MAX_PATH]; + + if ((d = PM_malloc(sizeof(*d))) == NULL) + return PM_FILE_INVALID; + PM_splitpath(filename,NULL,d->path,name,ext); + strcpy(d->mask,name); + strcat(d->mask,ext); + if (strlen(d->path) == 0) + strcpy(d->path, "."); + if (d->path[strlen(d->path)-1] == '/') + d->path[strlen(d->path)-1] = 0; + if ((d->d = opendir(d->path)) != NULL) { + while ((dire = readdir(d->d)) != NULL) { + if (filematch(d->mask,d->path,dire)) { + convertFindData(findData,dire,d->path); + return d; + } + } + closedir(d->d); + } + PM_free(d); + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + PM_findHandle *d = handle; + struct dirent *dire; + + while ((dire = readdir(d->d)) != NULL) { + if (filematch(d->mask,d->path,dire)) { + convertFindData(findData,dire,d->path); + return true; + } + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + PM_findHandle *d = handle; + + closedir(d->d); + free(d); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + if (drive == 3) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + (void)drive; + getcwd(dir,len); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + struct stat st; + mode_t mode; + + stat(filename,&st); + mode = st.st_mode; + if (attrib & PM_FILE_READONLY) + mode &= ~S_IWRITE; + else + mode |= S_IWRITE; + chmod(filename,mode); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + struct stat st; + + stat(filename,&st); + if (st.st_mode & S_IWRITE) + return 0; + return PM_FILE_READONLY; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return mkdir(filename,0x1FF) == 0; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return rmdir(filename) == 0; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_getFileTime not implemented yet!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_setFileTime not implemented yet!"); + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c b/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c new file mode 100644 index 0000000..8056e9a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c @@ -0,0 +1,377 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Portions copyright (C) Josh Vanderhoof +* +* Language: ANSI C +* Environment: Any +* +* Description: Functions to save and restore the VGA hardware state. +* +****************************************************************************/ + +#include "pmapi.h" +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +#include "sdd/sddhelp.h" +#else +#include +#endif + +/*--------------------------- Global variables ----------------------------*/ + +/* VGA index register ports */ +#define CRT_I 0x3D4 /* CRT Controller Index */ +#define ATT_IW 0x3C0 /* Attribute Controller Index & Data */ +#define GRA_I 0x3CE /* Graphics Controller Index */ +#define SEQ_I 0x3C4 /* Sequencer Index */ + +/* VGA data register ports */ +#define CRT_D 0x3D5 /* CRT Controller Data Register */ +#define ATT_R 0x3C1 /* Attribute Controller Data Read Register */ +#define GRA_D 0x3CF /* Graphics Controller Data Register */ +#define SEQ_D 0x3C5 /* Sequencer Data Register */ +#define MIS_R 0x3CC /* Misc Output Read Register */ +#define MIS_W 0x3C2 /* Misc Output Write Register */ +#define IS1_R 0x3DA /* Input Status Register 1 */ +#define PEL_IW 0x3C8 /* PEL Write Index */ +#define PEL_IR 0x3C7 /* PEL Read Index */ +#define PEL_D 0x3C9 /* PEL Data Register */ + +/* standard VGA indexes max counts */ +#define CRT_C 24 /* 24 CRT Controller Registers */ +#define ATT_C 21 /* 21 Attribute Controller Registers */ +#define GRA_C 9 /* 9 Graphics Controller Registers */ +#define SEQ_C 5 /* 5 Sequencer Registers */ +#define MIS_C 1 /* 1 Misc Output Register */ +#define PAL_C 768 /* 768 Palette Registers */ +#define FONT_C 8192 /* Total size of character generator RAM */ + +/* VGA registers saving indexes */ +#define CRT 0 /* CRT Controller Registers start */ +#define ATT (CRT+CRT_C) /* Attribute Controller Registers start */ +#define GRA (ATT+ATT_C) /* Graphics Controller Registers start */ +#define SEQ (GRA+GRA_C) /* Sequencer Registers */ +#define MIS (SEQ+SEQ_C) /* General Registers */ +#define PAL (MIS+MIS_C) /* VGA Palette Registers */ +#define FONT (PAL+PAL_C) /* VGA font data */ + +/* Macros for port I/O with arguments reversed */ + +#define _port_out(v,p) PM_outpb(p,(uchar)(v)) +#define _port_in(p) PM_inpb(p) + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Returns the size of the VGA state buffer. +****************************************************************************/ +int PMAPI PM_getVGAStateSize(void) +{ + return CRT_C + ATT_C + GRA_C + SEQ_C + MIS_C + PAL_C + FONT_C; +} + +/**************************************************************************** +REMARKS: +Delay for a short period of time. +****************************************************************************/ +static void vga_delay(void) +{ + int i; + + /* For the loop here we program the POST register. The length of this + * delay is dependant only on ISA bus speed, but it is enough for + * what we need. + */ + for (i = 0; i <= 10; i++) + PM_outpb(0x80, 0); +} + +/**************************************************************************** +PARAMETERS: +port - I/O port to read value from +index - Port index to read + +RETURNS: +Byte read from 'port' register 'index'. +****************************************************************************/ +static ushort vga_rdinx( + ushort port, + ushort index) +{ + PM_outpb(port,(uchar)index); + return PM_inpb(port+1); +} + +/**************************************************************************** +PARAMETERS: +port - I/O port to write to +index - Port index to write +value - Byte to write to port + +REMARKS: +Writes a byte value to the 'port' register 'index'. +****************************************************************************/ +static void vga_wrinx( + ushort port, + ushort index, + ushort value) +{ + PM_outpb(port,(uchar)index); + PM_outpb(port+1,(uchar)value); +} + +/**************************************************************************** +REMARKS: +Save the color palette values +****************************************************************************/ +static void vga_savepalette( + uchar *pal) +{ + int i; + + _port_out(0, PEL_IR); + for (i = 0; i < 768; i++) { + vga_delay(); + *pal++ = _port_in(PEL_D); + } +} + +/**************************************************************************** +REMARKS: +Restore the color palette values +****************************************************************************/ +static void vga_restorepalette( + const uchar *pal) +{ + int i; + + /* restore saved palette */ + _port_out(0, PEL_IW); + for (i = 0; i < 768; i++) { + vga_delay(); + _port_out(*pal++, PEL_D); + } +} + +/**************************************************************************** +REMARKS: +Read the font data from the VGA character generator RAM +****************************************************************************/ +static void vga_saveFont( + uchar *data) +{ + uchar *A0000Ptr = PM_getA0000Pointer(); + uchar save[7]; + + /* Enable access to character generator RAM */ + save[0] = (uchar)vga_rdinx(SEQ_I,0x00); + save[1] = (uchar)vga_rdinx(SEQ_I,0x02); + save[2] = (uchar)vga_rdinx(SEQ_I,0x04); + save[3] = (uchar)vga_rdinx(SEQ_I,0x00); + save[4] = (uchar)vga_rdinx(GRA_I,0x04); + save[5] = (uchar)vga_rdinx(GRA_I,0x05); + save[6] = (uchar)vga_rdinx(GRA_I,0x06); + vga_wrinx(SEQ_I,0x00,0x01); + vga_wrinx(SEQ_I,0x02,0x04); + vga_wrinx(SEQ_I,0x04,0x07); + vga_wrinx(SEQ_I,0x00,0x03); + vga_wrinx(GRA_I,0x04,0x02); + vga_wrinx(GRA_I,0x05,0x00); + vga_wrinx(GRA_I,0x06,0x00); + + /* Copy character generator RAM */ + memcpy(data,A0000Ptr,FONT_C); + + /* Restore VGA state */ + vga_wrinx(SEQ_I,0x00,save[0]); + vga_wrinx(SEQ_I,0x02,save[1]); + vga_wrinx(SEQ_I,0x04,save[2]); + vga_wrinx(SEQ_I,0x00,save[3]); + vga_wrinx(GRA_I,0x04,save[4]); + vga_wrinx(GRA_I,0x05,save[5]); + vga_wrinx(GRA_I,0x06,save[6]); +} + +/**************************************************************************** +REMARKS: +Downloads the font data to the VGA character generator RAM +****************************************************************************/ +static void vga_restoreFont( + const uchar *data) +{ + uchar *A0000Ptr = PM_getA0000Pointer(); + + /* Enable access to character generator RAM */ + vga_wrinx(SEQ_I,0x00,0x01); + vga_wrinx(SEQ_I,0x02,0x04); + vga_wrinx(SEQ_I,0x04,0x07); + vga_wrinx(SEQ_I,0x00,0x03); + vga_wrinx(GRA_I,0x04,0x02); + vga_wrinx(GRA_I,0x05,0x00); + vga_wrinx(GRA_I,0x06,0x00); + + /* Copy font back to character generator RAM */ + memcpy(A0000Ptr,data,FONT_C); +} + +/**************************************************************************** +REMARKS: +Save the state of all VGA compatible registers +****************************************************************************/ +void PMAPI PM_saveVGAState( + void *stateBuf) +{ + uchar *regs = stateBuf; + int i; + + /* Save state of VGA registers */ + for (i = 0; i < CRT_C; i++) { + _port_out(i, CRT_I); + regs[CRT + i] = _port_in(CRT_D); + } + for (i = 0; i < ATT_C; i++) { + _port_in(IS1_R); + vga_delay(); + _port_out(i, ATT_IW); + vga_delay(); + regs[ATT + i] = _port_in(ATT_R); + vga_delay(); + } + for (i = 0; i < GRA_C; i++) { + _port_out(i, GRA_I); + regs[GRA + i] = _port_in(GRA_D); + } + for (i = 0; i < SEQ_C; i++) { + _port_out(i, SEQ_I); + regs[SEQ + i] = _port_in(SEQ_D); + } + regs[MIS] = _port_in(MIS_R); + + /* Save the VGA palette values */ + vga_savepalette(®s[PAL]); + + /* Save the VGA character generator RAM */ + vga_saveFont(®s[FONT]); + + /* Turn the VGA display back on */ + PM_vgaUnblankDisplay(); +} + +/**************************************************************************** +REMARKS: +Retore the state of all VGA compatible registers +****************************************************************************/ +void PMAPI PM_restoreVGAState( + const void *stateBuf) +{ + const uchar *regs = stateBuf; + int i; + + /* Blank the display before we start the restore */ + PM_vgaBlankDisplay(); + + /* Restore the VGA character generator RAM */ + vga_restoreFont(®s[FONT]); + + /* Restore the VGA palette values */ + vga_restorepalette(®s[PAL]); + + /* Restore the state of the VGA compatible registers */ + _port_out(regs[MIS], MIS_W); + + /* Delay to allow clock change to settle */ + for (i = 0; i < 10; i++) + vga_delay(); + + /* Synchronous reset on */ + _port_out(0x00,SEQ_I); + _port_out(0x01,SEQ_D); + + /* Write seqeuencer registers */ + _port_out(1, SEQ_I); + _port_out(regs[SEQ + 1] | 0x20, SEQ_D); + for (i = 2; i < SEQ_C; i++) { + _port_out(i, SEQ_I); + _port_out(regs[SEQ + i], SEQ_D); + } + + /* Synchronous reset off */ + _port_out(0x00,SEQ_I); + _port_out(0x03,SEQ_D); + + /* Deprotect CRT registers 0-7 and write CRTC */ + _port_out(0x11, CRT_I); + _port_out(_port_in(CRT_D) & 0x7F, CRT_D); + for (i = 0; i < CRT_C; i++) { + _port_out(i, CRT_I); + _port_out(regs[CRT + i], CRT_D); + } + for (i = 0; i < GRA_C; i++) { + _port_out(i, GRA_I); + _port_out(regs[GRA + i], GRA_D); + } + for (i = 0; i < ATT_C; i++) { + _port_in(IS1_R); /* reset flip-flop */ + vga_delay(); + _port_out(i, ATT_IW); + vga_delay(); + _port_out(regs[ATT + i], ATT_IW); + vga_delay(); + } + + /* Ensure the VGA screen is turned on */ + PM_vgaUnblankDisplay(); +} + +/**************************************************************************** +REMARKS: +Disables the VGA display for screen output making it blank. +****************************************************************************/ +void PMAPI PM_vgaBlankDisplay(void) +{ + /* Turn screen off */ + _port_out(0x01, SEQ_I); + _port_out(_port_in(SEQ_D) | 0x20, SEQ_D); + + /* Disable video output */ + _port_in(IS1_R); + vga_delay(); + _port_out(0x00, ATT_IW); +} + +/**************************************************************************** +REMARKS: +Enables the VGA display for screen output. +****************************************************************************/ +void PMAPI PM_vgaUnblankDisplay(void) +{ + /* Turn screen back on */ + _port_out(0x01, SEQ_I); + _port_out(_port_in(SEQ_D) & 0xDF, SEQ_D); + + /* Enable video output */ + _port_in(IS1_R); + vga_delay(); + _port_out(0x20, ATT_IW); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c new file mode 100644 index 0000000..ac62e81 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c @@ -0,0 +1,808 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Main module to implement the Zen Timer support functions. +* +****************************************************************************/ + +#include "ztimer.h" +#include "pmapi.h" +#include "oshdr.h" +#if !defined(__WIN32_VXD__) && !defined(__OS2_VDD__) && !defined(__NT_DRIVER__) +#include +#include +#endif + +/*----------------------------- Implementation ----------------------------*/ + +/* External Intel assembler functions */ +#ifdef __INTEL__ +/* {secret} */ +ibool _ASMAPI _CPU_haveCPUID(void); +/* {secret} */ +ibool _ASMAPI _CPU_check80386(void); +/* {secret} */ +ibool _ASMAPI _CPU_check80486(void); +/* {secret} */ +uint _ASMAPI _CPU_checkCPUID(void); +/* {secret} */ +uint _ASMAPI _CPU_getCPUIDModel(void); +/* {secret} */ +uint _ASMAPI _CPU_getCPUIDStepping(void); +/* {secret} */ +uint _ASMAPI _CPU_getCPUIDFeatures(void); +/* {secret} */ +uint _ASMAPI _CPU_getCacheSize(void); +/* {secret} */ +uint _ASMAPI _CPU_have3DNow(void); +/* {secret} */ +ibool _ASMAPI _CPU_checkClone(void); +/* {secret} */ +void _ASMAPI _CPU_readTimeStamp(CPU_largeInteger *time); +/* {secret} */ +void _ASMAPI _CPU_runBSFLoop(ulong iterations); +/* {secret} */ +ulong _ASMAPI _CPU_mulDiv(ulong a,ulong b,ulong c); +/* {secret} */ +void ZTimerQuickInit(void); +#define CPU_HaveMMX 0x00800000 +#define CPU_HaveRDTSC 0x00000010 +#define CPU_HaveSSE 0x02000000 +#endif + +#if defined(__SMX32__) +#include "smx/cpuinfo.c" +#elif defined(__RTTARGET__) +#include "rttarget/cpuinfo.c" +#elif defined(__REALDOS__) +#include "dos/cpuinfo.c" +#elif defined(__NT_DRIVER__) +#include "ntdrv/cpuinfo.c" +#elif defined(__WIN32_VXD__) +#include "vxd/cpuinfo.c" +#elif defined(__WINDOWS32__) +#include "win32/cpuinfo.c" +#elif defined(__OS2_VDD__) +#include "vdd/cpuinfo.c" +#elif defined(__OS2__) +#include "os2/cpuinfo.c" +#elif defined(__LINUX__) +#include "linux/cpuinfo.c" +#elif defined(__QNX__) +#include "qnx/cpuinfo.c" +#elif defined(__BEOS__) +#include "beos/cpuinfo.c" +#else +#error CPU library not ported to this platform yet! +#endif + +/*------------------------ Public interface routines ----------------------*/ + +/**************************************************************************** +REMARKS: +Read an I/O port location. +****************************************************************************/ +static uchar rdinx( + int port, + int index) +{ + PM_outpb(port,(uchar)index); + return PM_inpb(port+1); +} + +/**************************************************************************** +REMARKS: +Write an I/O port location. +****************************************************************************/ +static void wrinx( + ushort port, + ushort index, + ushort value) +{ + PM_outpb(port,(uchar)index); + PM_outpb(port+1,(uchar)value); +} + +/**************************************************************************** +REMARKS: +Enables the Cyrix CPUID instruction to properly detect MediaGX and 6x86 +processors. +****************************************************************************/ +static void _CPU_enableCyrixCPUID(void) +{ + uchar ccr3; + + PM_init(); + ccr3 = rdinx(0x22,0xC3); + wrinx(0x22,0xC3,(uchar)(ccr3 | 0x10)); + wrinx(0x22,0xE8,(uchar)(rdinx(0x22,0xE8) | 0x80)); + wrinx(0x22,0xC3,ccr3); +} + +/**************************************************************************** +DESCRIPTION: +Returns the type of processor in the system. + +HEADER: +ztimer.h + +RETURNS: +Numerical identifier for the installed processor + +REMARKS: +Returns the type of processor in the system. Note that if the CPU is an +unknown Pentium family processor that we don't have an enumeration for, +the return value will be greater than or equal to the value of CPU_UnkPentium +(depending on the value returned by the CPUID instruction). + +SEE ALSO: +CPU_getProcessorSpeed, CPU_haveMMX, CPU_getProcessorName +****************************************************************************/ +uint ZAPI CPU_getProcessorType(void) +{ +#if defined(__INTEL__) + uint cpu,vendor,model,cacheSize; + static ibool firstTime = true; + + if (_CPU_haveCPUID()) { + cpu = _CPU_checkCPUID(); + vendor = cpu & ~CPU_mask; + if (vendor == CPU_Intel) { + /* Check for Intel processors */ + switch (cpu & CPU_mask) { + case 4: cpu = CPU_i486; break; + case 5: cpu = CPU_Pentium; break; + case 6: + if ((model = _CPU_getCPUIDModel()) == 1) + cpu = CPU_PentiumPro; + else if (model <= 6) { + cacheSize = _CPU_getCacheSize(); + if ((model == 5 && cacheSize == 0) || + (model == 5 && cacheSize == 256) || + (model == 6 && cacheSize == 128)) + cpu = CPU_Celeron; + else + cpu = CPU_PentiumII; + } + else if (model >= 7) { + /* Model 7 == Pentium III */ + /* Model 8 == Celeron/Pentium III Coppermine */ + cacheSize = _CPU_getCacheSize(); + if ((model == 8 && cacheSize == 128)) + cpu = CPU_Celeron; + else + cpu = CPU_PentiumIII; + } + break; + default: + cpu = CPU_UnkIntel; + } + } + else if (vendor == CPU_Cyrix) { + /* Check for Cyrix processors */ + switch (cpu & CPU_mask) { + case 4: + if ((model = _CPU_getCPUIDModel()) == 4) + cpu = CPU_CyrixMediaGX; + else + cpu = CPU_UnkCyrix; + break; + case 5: + if ((model = _CPU_getCPUIDModel()) == 2) + cpu = CPU_Cyrix6x86; + else if (model == 4) + cpu = CPU_CyrixMediaGXm; + else + cpu = CPU_UnkCyrix; + break; + case 6: + if ((model = _CPU_getCPUIDModel()) <= 1) + cpu = CPU_Cyrix6x86MX; + else + cpu = CPU_UnkCyrix; + break; + default: + cpu = CPU_UnkCyrix; + } + } + else if (vendor == CPU_AMD) { + /* Check for AMD processors */ + switch (cpu & CPU_mask) { + case 4: + if ((model = _CPU_getCPUIDModel()) == 0) + cpu = CPU_AMDAm5x86; + else + cpu = CPU_AMDAm486; + break; + case 5: + if ((model = _CPU_getCPUIDModel()) <= 3) + cpu = CPU_AMDK5; + else if (model <= 7) + cpu = CPU_AMDK6; + else if (model == 8) + cpu = CPU_AMDK6_2; + else if (model == 9) + cpu = CPU_AMDK6_III; + else if (model == 13) { + if (_CPU_getCPUIDStepping() <= 3) + cpu = CPU_AMDK6_IIIplus; + else + cpu = CPU_AMDK6_2plus; + } + else + cpu = CPU_UnkAMD; + break; + case 6: + if ((model = _CPU_getCPUIDModel()) == 3) + cpu = CPU_AMDDuron; + else + cpu = CPU_AMDAthlon; + break; + default: + cpu = CPU_UnkAMD; + } + } + else if (vendor == CPU_IDT) { + /* Check for IDT WinChip processors */ + switch (cpu & CPU_mask) { + case 5: + if ((model = _CPU_getCPUIDModel()) <= 4) + cpu = CPU_WinChipC6; + else if (model == 8) + cpu = CPU_WinChip2; + else + cpu = CPU_UnkIDT; + break; + default: + cpu = CPU_UnkIDT; + } + } + else { + /* Assume a Pentium compatible Intel clone */ + cpu = CPU_Pentium; + } + return cpu | vendor | (_CPU_getCPUIDStepping() << CPU_steppingShift); + } + else { + if (_CPU_check80386()) + cpu = CPU_i386; + else if (_CPU_check80486()) { + /* If we get here we may have a Cyrix processor so we can try + * enabling the CPUID instruction and trying again. + */ + if (firstTime) { + firstTime = false; + _CPU_enableCyrixCPUID(); + return CPU_getProcessorType(); + } + cpu = CPU_i486; + } + else + cpu = CPU_Pentium; + if (!_CPU_checkClone()) + return cpu | CPU_Intel; + return cpu; + } +#elif defined(__ALPHA__) + return CPU_Alpha; +#elif defined(__MIPS__) + return CPU_Mips; +#elif defined(__PPC__) + return CPU_PowerPC; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns true if the processor supports Intel MMX extensions. + +HEADER: +ztimer.h + +RETURNS: +True if MMX is available, false if not. + +REMARKS: +This function determines if the processor supports the Intel MMX extended +instruction set. + +SEE ALSO: +CPU_getProcessorType, CPU_getProcessorSpeed, CPU_have3DNow, CPU_haveSSE, +CPU_getProcessorName +****************************************************************************/ +ibool ZAPI CPU_haveMMX(void) +{ +#ifdef __INTEL__ + if (_CPU_haveCPUID()) + return (_CPU_getCPUIDFeatures() & CPU_HaveMMX) != 0; + return false; +#else + return false; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns true if the processor supports AMD 3DNow! extensions. + +HEADER: +ztimer.h + +RETURNS: +True if 3DNow! is available, false if not. + +REMARKS: +This function determines if the processor supports the AMD 3DNow! extended +instruction set. + +SEE ALSO: +CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_haveSSE, +CPU_getProcessorName +****************************************************************************/ +ibool ZAPI CPU_have3DNow(void) +{ +#ifdef __INTEL__ + if (_CPU_haveCPUID()) + return _CPU_have3DNow(); + return false; +#else + return false; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns true if the processor supports Intel KNI extensions. + +HEADER: +ztimer.h + +RETURNS: +True if Intel KNI is available, false if not. + +REMARKS: +This function determines if the processor supports the Intel KNI extended +instruction set. + +SEE ALSO: +CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_have3DNow, +CPU_getProcessorName +****************************************************************************/ +ibool ZAPI CPU_haveSSE(void) +{ +#ifdef __INTEL__ + if (_CPU_haveCPUID()) + return (_CPU_getCPUIDFeatures() & CPU_HaveSSE) != 0; + return false; +#else + return false; +#endif +} + +/**************************************************************************** +RETURNS: +True if the RTSC instruction is available, false if not. + +REMARKS: +This function determines if the processor supports the Intel RDTSC +instruction, for high precision timing. If the processor is not an Intel or +Intel clone CPU, this function will always return false. + +DESCRIPTION: +Returns true if the processor supports RDTSC extensions. + +HEADER: +ztimer.h + +RETURNS: +True if RTSC is available, false if not. + +REMARKS: +This function determines if the processor supports the RDTSC instruction +for reading the processor time stamp counter. + +SEE ALSO: +CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_have3DNow, +CPU_getProcessorName +****************************************************************************/ +ibool ZAPI CPU_haveRDTSC(void) +{ +#ifdef __INTEL__ + if (_CPU_haveCPUID()) + return (_CPU_getCPUIDFeatures() & CPU_HaveRDTSC) != 0; + return false; +#else + return false; +#endif +} + +#ifdef __INTEL__ + +#define ITERATIONS 16000 +#define SAMPLINGS 2 +#define INNER_LOOPS 400 + +/**************************************************************************** +REMARKS: +If processor does not support time stamp reading, but is at least a 386 or +above, utilize method of timing a loop of BSF instructions which take a +known number of cycles to run on i386(tm), i486(tm), and Pentium(R) +processors. +****************************************************************************/ +static ulong GetBSFCpuSpeed( + ulong cycles) +{ + CPU_largeInteger t0,t1,count_freq; + ulong ticks; /* Microseconds elapsed during test */ + ulong current; /* Variable to store time elapsed */ + int i,j,iPriority; + ulong lowest = (ulong)-1; + + iPriority = SetMaxThreadPriority(); + GetCounterFrequency(&count_freq); + for (i = 0; i < SAMPLINGS; i++) { + GetCounter(&t0); + for (j = 0; j < INNER_LOOPS; j++) + _CPU_runBSFLoop(ITERATIONS); + GetCounter(&t1); + current = t1.low - t0.low; + if (current < lowest) + lowest = current; + } + RestoreThreadPriority(iPriority); + + /* Compute frequency */ + ticks = _CPU_mulDiv(lowest,1000000,count_freq.low); + if ((ticks % count_freq.low) > (count_freq.low/2)) + ticks++; /* Round up if necessary */ + if (ticks == 0) + return 0; + return ((cycles*INNER_LOOPS)/ticks); +} + +#define TOLERANCE 1 + +/**************************************************************************** +REMARKS: +On processors supporting the Read Time Stamp opcode, compare elapsed +time on the High-Resolution Counter with elapsed cycles on the Time +Stamp Register. + +The inner loop runs up to 20 times oruntil the average of the previous +three calculated frequencies is within 1 MHz of each of the individual +calculated frequencies. This resampling increases the accuracy of the +results since outside factors could affect this calculation. +****************************************************************************/ +static ulong GetRDTSCCpuSpeed( + ibool accurate) +{ + CPU_largeInteger t0,t1,s0,s1,count_freq; + u64 stamp0, stamp1, ticks0, ticks1; + u64 total_cycles, cycles, hz, freq; + u64 total_ticks, ticks; + int tries,iPriority; + ulong maxCount; + + PM_set64_32(total_cycles,0); + PM_set64_32(total_ticks,0); + maxCount = accurate ? 600000 : 30000; + iPriority = SetMaxThreadPriority(); + GetCounterFrequency(&count_freq); + PM_set64(freq,count_freq.high,count_freq.low); + for (tries = 0; tries < 3; tries++) { + /* Loop until 100 ticks have passed since last read of hi-res + * counter. This accounts for overhead later. + */ + GetCounter(&t0); + t1.low = t0.low; + t1.high = t0.high; + while ((t1.low - t0.low) < 100) { + GetCounter(&t1); + _CPU_readTimeStamp(&s0); + } + + /* Loop until 30000 ticks have passed since last read of hi-res counter. + * This allows for elapsed time for sampling. For a hi-res frequency + * of 1MHz, this is about 0.03 of a second. The frequency reported + * by the OS dependent code should be tuned to provide a good + * sample period depending on the accuracy of the OS timers (ie: + * if the accuracy is lower, lower the frequency to spend more time + * in the inner loop to get better accuracy). + */ + t0.low = t1.low; + t0.high = t1.high; + while ((t1.low - t0.low) < maxCount) { + GetCounter(&t1); + _CPU_readTimeStamp(&s1); + } + + /* Find the difference during the timing loop */ + PM_set64(stamp0,s0.high,s0.low); + PM_set64(stamp1,s1.high,s1.low); + PM_set64(ticks0,t0.high,t0.low); + PM_set64(ticks1,t1.high,t1.low); + PM_sub64(cycles,stamp1,stamp0); + PM_sub64(ticks,ticks1,ticks0); + + /* Sum up the results */ + PM_add64(total_ticks,total_ticks,ticks); + PM_add64(total_cycles,total_cycles,cycles); + } + RestoreThreadPriority(iPriority); + + /* Compute frequency in Hz */ + PM_mul64(hz,total_cycles,freq); + PM_div64(hz,hz,total_ticks); + return PM_64to32(hz); +} + +#endif /* __INTEL__ */ + +/**************************************************************************** +DESCRIPTION: +Returns the speed of the processor in MHz. + +HEADER: +ztimer.h + +PARAMETERS: +accurate - True of the speed should be measured accurately + +RETURNS: +Processor speed in MHz. + +REMARKS: +This function returns the speed of the CPU in MHz. Note that if the speed +cannot be determined, this function will return 0. + +If the accurate parameter is set to true, this function will spend longer +profiling the speed of the CPU, and will not round the CPU speed that is +reported. This is important for highly accurate timing using the Pentium +RDTSC instruction, but it does take a lot longer for the profiling to +produce accurate results. + +SEE ALSO: +CPU_getProcessorSpeedInHz, CPU_getProcessorType, CPU_haveMMX, +CPU_getProcessorName +****************************************************************************/ +ulong ZAPI CPU_getProcessorSpeed( + ibool accurate) +{ +#if defined(__INTEL__) + /* Number of cycles needed to execute a single BSF instruction on i386+ + * processors. + */ + ulong cpuSpeed; + uint i; + static ulong intel_cycles[] = { + 115,47,43, + }; + static ulong cyrix_cycles[] = { + 38,38,52,52, + }; + static ulong amd_cycles[] = { + 49, + }; + static ulong known_speeds[] = { + 1000,950,900,850,800,750,700,650,600,550,500,450,433,400,350, + 333,300,266,233,200,166,150,133,120,100,90,75,66,60,50,33,20,0, + }; + + if (CPU_haveRDTSC()) { + cpuSpeed = (GetRDTSCCpuSpeed(accurate) + 500000) / 1000000; + } + else { + int type = CPU_getProcessorType(); + int processor = type & CPU_mask; + int vendor = type & CPU_familyMask; + if (vendor == CPU_Intel) + cpuSpeed = GetBSFCpuSpeed(ITERATIONS * intel_cycles[processor - CPU_i386]); + else if (vendor == CPU_Cyrix) + cpuSpeed = GetBSFCpuSpeed(ITERATIONS * cyrix_cycles[processor - CPU_Cyrix6x86]); + else if (vendor == CPU_AMD) + cpuSpeed = GetBSFCpuSpeed(ITERATIONS * amd_cycles[0]); + else + return 0; + } + + /* Now normalise the results given known processors speeds, if the + * speed we measure is within 2MHz of the expected values + */ + if (!accurate) { + for (i = 0; known_speeds[i] != 0; i++) { + if (cpuSpeed >= (known_speeds[i]-3) && cpuSpeed <= (known_speeds[i]+3)) { + return known_speeds[i]; + } + } + } + return cpuSpeed; +#else + return 0; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns the speed of the processor in Hz. + +HEADER: +ztimer.h + +RETURNS: +Accurate processor speed in Hz. + +REMARKS: +This function returns the accurate speed of the CPU in Hz. Note that if the +speed cannot be determined, this function will return 0. + +This function is similar to the CPU_getProcessorSpeed function, except that +it attempts to accurately measure the CPU speed in Hz. This is used +internally in the Zen Timer libraries to provide accurate real world timing +information. This is important for highly accurate timing using the Pentium +RDTSC instruction, but it does take a lot longer for the profiling to +produce accurate results. + +SEE ALSO: +CPU_getProcessorSpeed, CPU_getProcessorType, CPU_haveMMX, +CPU_getProcessorName +****************************************************************************/ +ulong ZAPI CPU_getProcessorSpeedInHZ( + ibool accurate) +{ +#if defined(__INTEL__) + if (CPU_haveRDTSC()) { + return GetRDTSCCpuSpeed(accurate); + } + return CPU_getProcessorSpeed(false) * 1000000; +#else + return 0; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns a string defining the speed and name of the processor. + +HEADER: +ztimer.h + +RETURNS: +Processor name string. + +REMARKS: +This function returns an English string describing the speed and name of the +CPU. + +SEE ALSO: +CPU_getProcessorType, CPU_haveMMX, CPU_getProcessorName +****************************************************************************/ +char * ZAPI CPU_getProcessorName(void) +{ +#if defined(__INTEL__) + static int cpu,speed = -1; + static char name[80]; + + if (speed == -1) { + cpu = CPU_getProcessorType(); + speed = CPU_getProcessorSpeed(false); + } + sprintf(name,"%d MHz ", speed); + switch (cpu & CPU_mask) { + case CPU_i386: + strcat(name,"Intel i386 processor"); + break; + case CPU_i486: + strcat(name,"Intel i486 processor"); + break; + case CPU_Pentium: + strcat(name,"Intel Pentium processor"); + break; + case CPU_PentiumPro: + strcat(name,"Intel Pentium Pro processor"); + break; + case CPU_PentiumII: + strcat(name,"Intel Pentium II processor"); + break; + case CPU_Celeron: + strcat(name,"Intel Celeron processor"); + break; + case CPU_PentiumIII: + strcat(name,"Intel Pentium III processor"); + break; + case CPU_UnkIntel: + strcat(name,"Unknown Intel processor"); + break; + case CPU_Cyrix6x86: + strcat(name,"Cyrix 6x86 processor"); + break; + case CPU_Cyrix6x86MX: + strcat(name,"Cyrix 6x86MX processor"); + break; + case CPU_CyrixMediaGX: + strcat(name,"Cyrix MediaGX processor"); + break; + case CPU_CyrixMediaGXm: + strcat(name,"Cyrix MediaGXm processor"); + break; + case CPU_UnkCyrix: + strcat(name,"Unknown Cyrix processor"); + break; + case CPU_AMDAm486: + strcat(name,"AMD Am486 processor"); + break; + case CPU_AMDAm5x86: + strcat(name,"AMD Am5x86 processor"); + break; + case CPU_AMDK5: + strcat(name,"AMD K5 processor"); + break; + case CPU_AMDK6: + strcat(name,"AMD K6 processor"); + break; + case CPU_AMDK6_2: + strcat(name,"AMD K6-2 processor"); + break; + case CPU_AMDK6_III: + strcat(name,"AMD K6-III processor"); + break; + case CPU_AMDK6_2plus: + strcat(name,"AMD K6-2+ processor"); + break; + case CPU_AMDK6_IIIplus: + strcat(name,"AMD K6-III+ processor"); + break; + case CPU_UnkAMD: + strcat(name,"Unknown AMD processor"); + break; + case CPU_AMDAthlon: + strcat(name,"AMD Athlon processor"); + break; + case CPU_AMDDuron: + strcat(name,"AMD Duron processor"); + break; + case CPU_WinChipC6: + strcat(name,"IDT WinChip C6 processor"); + break; + case CPU_WinChip2: + strcat(name,"IDT WinChip 2 processor"); + break; + case CPU_UnkIDT: + strcat(name,"Unknown IDT processor"); + break; + default: + strcat(name,"Unknown processor"); + } + if (CPU_haveMMX()) + strcat(name," with MMX(R)"); + if (CPU_have3DNow()) + strcat(name,", 3DNow!(R)"); + if (CPU_haveSSE()) + strcat(name,", SSE(R)"); + return name; +#else + return "Unknown"; +#endif +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/debug.c b/board/MAI/bios_emulator/scitech/src/pm/debug.c new file mode 100644 index 0000000..751bf09 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/debug.c @@ -0,0 +1,107 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Main module containing debug checking features. +* +****************************************************************************/ + +#include "pmapi.h" +#ifdef __WIN32_VXD__ +#include "vxdfile.h" +#elif defined(__NT_DRIVER__) +#include "ntdriver.h" +#elif defined(__OS2_VDD__) +#include "vddfile.h" +#else +#include +#include +#include +#endif + +/*---------------------------- Global variables ---------------------------*/ + +/* {secret} */ +void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line) = _CHK_defaultFail; +static char logFile[256] = ""; + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef CHECKED +void _CHK_defaultFail( + int fatal, + const char *msg, + const char *cond, + const char *file, + int line) +{ + FILE *f; + char buf[256]; + + if (logFile[0] == 0) { + strcpy(logFile,PM_getNucleusPath()); + PM_backslash(logFile); + strcat(logFile,"scitech.log"); + } + if ((f = fopen(logFile,"a+")) != NULL) { +#if defined(__WIN32_VXD__) || defined(__OS2_VDD__) || defined(__NT_DRIVER__) + sprintf(buf,msg,cond,file,line); + fwrite(buf,1,strlen(buf),f); +#else + fprintf(f,msg,cond,file,line); +#endif + fclose(f); + } + if (fatal) { + sprintf(buf,"Check failed: check '%s' for details", logFile); + PM_fatalError(buf); + } +} +#endif + +/**************************************************************************** +DESCRIPTION: +Sets the location of the debug log file. + +HEADER: +pmapi.h + +PARAMETERS: +logFilePath - Full file and path name to debug log file. + +REMARKS: +Sets the name and location of the debug log file. The debug log file is +created and written to when runtime checks, warnings and failure conditions +are logged to disk when code is compiled in CHECKED mode. By default the +log file is called 'scitech.log' and goes into the current SciTech Nucleus +path for the application. You can use this function to set the filename +and location of the debug log file to your own application specific +directory. +****************************************************************************/ +void PMAPI PM_setDebugLog( + const char *logFilePath) +{ + strcpy(logFile,logFilePath); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm new file mode 100644 index 0000000..36dcaab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm @@ -0,0 +1,194 @@ +;**************************************************************************** +;* +;* SciTech Multi-platform Graphics Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler +;* Environment: IBM PC (MS DOS) +;* +;* Description: Assembly language support routines for the event module. +;* +;**************************************************************************** + + ideal + +include "scitech.mac" ; Memory model macros + +ifdef flatmodel + +header _event ; Set up memory model + +begdataseg _event + + cextern _EVT_biosPtr,DPTR + +ifdef USE_NASM +%define KB_HEAD WORD esi+01Ah ; Keyboard buffer head in BIOS data area +%define KB_TAIL WORD esi+01Ch ; Keyboard buffer tail in BIOS data area +%define KB_START WORD esi+080h ; Start of keyboard buffer in BIOS data area +%define KB_END WORD esi+082h ; End of keyboard buffer in BIOS data area +else +KB_HEAD EQU WORD esi+01Ah ; Keyboard buffer head in BIOS data area +KB_TAIL EQU WORD esi+01Ch ; Keyboard buffer tail in BIOS data area +KB_START EQU WORD esi+080h ; Start of keyboard buffer in BIOS data area +KB_END EQU WORD esi+082h ; End of keyboard buffer in BIOS data area +endif + +enddataseg _event + +begcodeseg _event ; Start of code segment + + cpublic _EVT_codeStart + +;---------------------------------------------------------------------------- +; int _EVT_getKeyCode(void) +;---------------------------------------------------------------------------- +; Returns the key code for the next available key by extracting it from +; the BIOS keyboard buffer. +;---------------------------------------------------------------------------- +cprocstart _EVT_getKeyCode + + enter_c + + mov esi,[_EVT_biosPtr] + xor ebx,ebx + xor eax,eax + mov bx,[KB_HEAD] + cmp bx,[KB_TAIL] + jz @@Done + xor eax,eax + mov ax,[esi+ebx] ; EAX := character from keyboard buffer + inc _bx + inc _bx + cmp bx,[KB_END] ; Hit the end of the keyboard buffer? + jl @@1 + mov bx,[KB_START] +@@1: mov [KB_HEAD],bx ; Update keyboard buffer head pointer + +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _EVT_pumpMessages(void) +;---------------------------------------------------------------------------- +; This function would normally do nothing, however due to strange bugs +; in the Windows 3.1 and OS/2 DOS boxes, we don't get any hardware keyboard +; interrupts unless we periodically call the BIOS keyboard functions. Hence +; this function gets called every time that we check for events, and works +; around this problem (in essence it tells the DOS VDM to pump the +; keyboard events to our program ;-). +; +; Note that this bug is not present under Win 9x DOS boxes. +;---------------------------------------------------------------------------- +cprocstart _EVT_pumpMessages + + mov ah,11h ; Function - Check keyboard status + int 16h ; Call BIOS + + mov ax, 0Bh ; Reset Move Mouse + int 33h + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _EVT_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _EVT_disableInt + + pushf ; Put flag word on stack + cli ; Disable interrupts! + pop eax ; deposit flag word in return register + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _EVT_restoreInt(int ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _EVT_restoreInt + + ARG ps:UINT + + push ebp + mov ebp,esp ; Set up stack frame + push [DWORD ps] + popf ; Restore processor status (and interrupts) + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; int EVT_rdinx(int port,int index) +;---------------------------------------------------------------------------- +; Reads an indexed register value from an I/O port. +;---------------------------------------------------------------------------- +cprocstart EVT_rdinx + + ARG port:UINT, index:UINT + + push ebp + mov ebp,esp + mov edx,[port] + mov al,[BYTE index] + out dx,al + inc dx + in al,dx + movzx eax,al + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void EVT_wrinx(int port,int index,int value) +;---------------------------------------------------------------------------- +; Writes an indexed register value to an I/O port. +;---------------------------------------------------------------------------- +cprocstart EVT_wrinx + + ARG port:UINT, index:UINT, value:UINT + + push ebp + mov ebp,esp + mov edx,[port] + mov al,[BYTE index] + mov ah,[BYTE value] + out dx,ax + pop ebp + ret + +cprocend + + cpublic _EVT_codeEnd + +endcodeseg _event + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm new file mode 100644 index 0000000..a4a9c79 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm @@ -0,0 +1,438 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM or TASM Assembler +;* Environment: IBM PC (MS DOS) +;* +;* Description: Uses the 8253 timer and the BIOS time-of-day count to time +;* the performance of code that takes less than an hour to +;* execute. +;* +;* The routines in this package only works with interrupts +;* enabled, and in fact will explicitly turn interrupts on +;* in order to ensure we get accurate results from the timer. +;* +;* Externally 'C' callable routines: +;* +;* LZ_timerOn: Saves the BIOS time of day count and starts the +;* long period Zen Timer. +;* +;* LZ_timerLap: Latches the current count, and keeps the timer running +;* +;* LZ_timerOff: Stops the long-period Zen Timer and saves the timer +;* count and the BIOS time of day count. +;* +;* LZ_timerCount: Returns an unsigned long representing the timed count +;* in microseconds. If more than an hour passed during +;* the timing interval, LZ_timerCount will return the +;* value 0xFFFFFFFF (an invalid count). +;* +;* Note: If either more than an hour passes between calls to LZ_timerOn +;* and LZ_timerOff, an error is reported. For timing code that takes +;* more than a few minutes to execute, use the low resolution +;* Ultra Long Period Zen Timer code, which should be accurate +;* enough for most purposes. +;* +;* Note: Each block of code being timed should ideally be run several +;* times, with at least two similar readings required to +;* establish a true measurement, in order to eliminate any +;* variability caused by interrupts. +;* +;* Note: Interrupts must not be disabled for more than 54 ms at a +;* stretch during the timing interval. Because interrupts are +;* enabled, key, mice, and other devices that generate interrupts +;* should not be used during the timing interval. +;* +;* Note: Any extra code running off the timer interrupt (such as +;* some memory resident utilities) will increase the time +;* measured by the Zen Timer. +;* +;* Note: These routines can introduce inaccuracies of up to a few +;* tenths of a second into the system clock count for each +;* code section being timed. Consequently, it's a good idea to +;* reboot at the conclusion of timing sessions. (The +;* battery-backed clock, if any, is not affected by the Zen +;* timer.) +;* +;* All registers and all flags are preserved by all routines, except +;* interrupts which are always turned on +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" + +;**************************************************************************** +; +; Equates used by long period Zen Timer +; +;**************************************************************************** + +; Base address of 8253 timer chip + +BASE_8253 equ 40h + +; The address of the timer 0 count registers in the 8253 + +TIMER_0_8253 equ BASE_8253 + 0 + +; The address of the mode register in the 8253 + +MODE_8253 equ BASE_8253 + 3 + +; The address of the BIOS timer count variable in the BIOS data area. + +TIMER_COUNT equ 6Ch + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +endif + +header _lztimer + +begdataseg _lztimer + + cextern _ZTimerBIOSPtr,DPTR + +StartBIOSCount dd 0 ; Starting BIOS count dword +EndBIOSCount dd 0 ; Ending BIOS count dword +EndTimedCount dw 0 ; Timer 0 count at the end of timing period + +enddataseg _lztimer + +begcodeseg _lztimer ; Start of code segment + +;---------------------------------------------------------------------------- +; void LZ_timerOn(void); +;---------------------------------------------------------------------------- +; Starts the Long period Zen timer counting. +;---------------------------------------------------------------------------- +cprocstart LZ_timerOn + +; Set the timer 0 of the 8253 to mode 2 (divide-by-N), to cause +; linear counting rather than count-by-two counting. Also stops +; timer 0 until the timer count is loaded, except on PS/2 computers. + + mov al,00110100b ; mode 2 + out MODE_8253,al + +; Set the timer count to 0, so we know we won't get another timer +; interrupt right away. Note: this introduces an inaccuracy of up to 54 ms +; in the system clock count each time it is executed. + + DELAY + sub al,al + out TIMER_0_8253,al ; lsb + DELAY + out TIMER_0_8253,al ; msb + +; Store the timing start BIOS count + + use_es +ifdef flatmodel + mov ebx,[_ZTimerBIOSPtr] +else + les bx,[_ZTimerBIOSPtr] +endif + cli ; No interrupts while we grab the count + mov eax,[_ES _bx+TIMER_COUNT] + sti + mov [StartBIOSCount],eax + unuse_es + +; Set the timer count to 0 again to start the timing interval. + + mov al,00110100b ; set up to load initial + out MODE_8253,al ; timer count + DELAY + sub al,al + out TIMER_0_8253,al ; load count lsb + DELAY + out TIMER_0_8253,al ; load count msb + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void LZ_timerOff(void); +;---------------------------------------------------------------------------- +; Stops the long period Zen timer and saves count. +;---------------------------------------------------------------------------- +cprocstart LZ_timerOff + +; Latch the timer count. + + mov al,00000000b ; latch timer 0 + out MODE_8253,al + cli ; Stop the BIOS count + +; Read the BIOS count. (Since interrupts are disabled, the BIOS +; count won't change). + + use_es +ifdef flatmodel + mov ebx,[_ZTimerBIOSPtr] +else + les bx,[_ZTimerBIOSPtr] +endif + mov eax,[_ES _bx+TIMER_COUNT] + mov [EndBIOSCount],eax + unuse_es + +; Read out the count we latched earlier. + + in al,TIMER_0_8253 ; least significant byte + DELAY + mov ah,al + in al,TIMER_0_8253 ; most significant byte + xchg ah,al + neg ax ; Convert from countdown remaining + ; to elapsed count + mov [EndTimedCount],ax + sti ; Let the BIOS count continue + + ret + +cprocend + +;---------------------------------------------------------------------------- +; unsigned long LZ_timerLap(void) +;---------------------------------------------------------------------------- +; Latches the current count and converts it to a microsecond timing value, +; but leaves the timer still running. We dont check for and overflow, +; where the time has gone over an hour in this routine, since we want it +; to execute as fast as possible. +;---------------------------------------------------------------------------- +cprocstart LZ_timerLap + + push ebx ; Save EBX for 32 bit code + +; Latch the timer count. + + mov al,00000000b ; latch timer 0 + out MODE_8253,al + cli ; Stop the BIOS count + +; Read the BIOS count. (Since interrupts are disabled, the BIOS +; count wont change). + + use_es +ifdef flatmodel + mov ebx,[_ZTimerBIOSPtr] +else + les bx,[_ZTimerBIOSPtr] +endif + mov eax,[_ES _bx+TIMER_COUNT] + mov [EndBIOSCount],eax + unuse_es + +; Read out the count we latched earlier. + + in al,TIMER_0_8253 ; least significant byte + DELAY + mov ah,al + in al,TIMER_0_8253 ; most significant byte + xchg ah,al + neg ax ; Convert from countdown remaining + ; to elapsed count + mov [EndTimedCount],ax + sti ; Let the BIOS count continue + +; See if a midnight boundary has passed and adjust the finishing BIOS +; count by the number of ticks in 24 hours. We wont be able to detect +; more than 24 hours, but at least we can time across a midnight +; boundary + + mov eax,[EndBIOSCount] ; Is end < start? + cmp eax,[StartBIOSCount] + jae @@CalcBIOSTime ; No, calculate the time taken + +; Adjust the finishing time by adding the number of ticks in 24 hours +; (1573040). + + add [DWORD EndBIOSCount],1800B0h + +; Convert the BIOS time to microseconds + +@@CalcBIOSTime: + mov ax,[WORD EndBIOSCount] + sub ax,[WORD StartBIOSCount] + mov dx,54925 ; Number of microseconds each + ; BIOS count represents. + mul dx + mov bx,ax ; set aside BIOS count in + mov cx,dx ; microseconds + +; Convert timer count to microseconds + + push _si + mov ax,[EndTimedCount] + mov si,8381 + mul si + mov si,10000 + div si ; * 0.8381 = * 8381 / 10000 + pop _si + +; Add the timer and BIOS counts together to get an overall time in +; microseconds. + + add ax,bx + adc cx,0 +ifdef flatmodel + shl ecx,16 + mov cx,ax + mov eax,ecx ; EAX := timer count +else + mov dx,cx +endif + pop ebx ; Restore EBX for 32 bit code + ret + +cprocend + +;---------------------------------------------------------------------------- +; unsigned long LZ_timerCount(void); +;---------------------------------------------------------------------------- +; Returns an unsigned long representing the net time in microseconds. +; +; If an hour has passed while timing, we return 0xFFFFFFFF as the count +; (which is not a possible count in itself). +;---------------------------------------------------------------------------- +cprocstart LZ_timerCount + + push ebx ; Save EBX for 32 bit code + +; See if a midnight boundary has passed and adjust the finishing BIOS +; count by the number of ticks in 24 hours. We wont be able to detect +; more than 24 hours, but at least we can time across a midnight +; boundary + + mov eax,[EndBIOSCount] ; Is end < start? + cmp eax,[StartBIOSCount] + jae @@CheckForHour ; No, check for hour passing + +; Adjust the finishing time by adding the number of ticks in 24 hours +; (1573040). + + add [DWORD EndBIOSCount],1800B0h + +; See if more than an hour passed during timing. If so, notify the user. + +@@CheckForHour: + mov ax,[WORD StartBIOSCount+2] + cmp ax,[WORD EndBIOSCount+2] + jz @@CalcBIOSTime ; Hour count didn't change, so + ; everything is fine + + inc ax + cmp ax,[WORD EndBIOSCount+2] + jnz @@TestTooLong ; Two hour boundaries passed, so the + ; results are no good + mov ax,[WORD EndBIOSCount] + cmp ax,[WORD StartBIOSCount] + jb @@CalcBIOSTime ; a single hour boundary passed. That's + ; OK, so long as the total time wasn't + ; more than an hour. + +; Over an hour elapsed passed during timing, which renders +; the results invalid. Notify the user. This misses the case where a +; multiple of 24 hours has passed, but we'll rely on the perspicacity of +; the user to detect that case :-). + +@@TestTooLong: +ifdef flatmodel + mov eax,0FFFFFFFFh +else + mov ax,0FFFFh + mov dx,0FFFFh +endif + jmp short @@Done + +; Convert the BIOS time to microseconds + +@@CalcBIOSTime: + mov ax,[WORD EndBIOSCount] + sub ax,[WORD StartBIOSCount] + mov dx,54925 ; Number of microseconds each + ; BIOS count represents. + mul dx + mov bx,ax ; set aside BIOS count in + mov cx,dx ; microseconds + +; Convert timer count to microseconds + + push _si + mov ax,[EndTimedCount] + mov si,8381 + mul si + mov si,10000 + div si ; * 0.8381 = * 8381 / 10000 + pop _si + +; Add the timer and BIOS counts together to get an overall time in +; microseconds. + + add ax,bx + adc cx,0 +ifdef flatmodel + shl ecx,16 + mov cx,ax + mov eax,ecx ; EAX := timer count +else + mov dx,cx +endif + +@@Done: pop ebx ; Restore EBX for 32 bit code + ret + +cprocend + +cprocstart LZ_disable + cli + ret +cprocend + +cprocstart LZ_enable + sti + ret +cprocend + +endcodeseg _lztimer + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm new file mode 100644 index 0000000..42b5cf3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm @@ -0,0 +1,656 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: IBM PC Real mode and 16/32 bit protected mode +;* +;* Description: Low level assembly support for the PM library specific to +;* MSDOS. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmdos ; Set up memory model + +begdataseg _pmdos + +ifndef flatmodel + +struc rmregs_s +ax dw ? +ax_high dw ? +bx dw ? +bx_high dw ? +cx dw ? +cx_high dw ? +dx dw ? +dx_high dw ? +si dw ? +si_high dw ? +di dw ? +di_high dw ? +cflag dw ? +cflag_high dw ? +ends rmregs_s +RMREGS = (rmregs_s PTR es:bx) + +struc rmsregs_s +es dw ? +cs dw ? +ss dw ? +ds dw ? +ends rmsregs_s +RMSREGS = (rmsregs_s PTR es:bx) + +endif ; !flatmodel + +ifdef flatmodel + cextern _PM_savedDS,USHORT + cextern _PM_VXD_off,UINT + cextern _PM_VXD_sel,UINT +ifdef DOS4GW + cextern _PM_haveCauseWay,UINT +endif +endif +intel_id db "GenuineIntel" ; Intel vendor ID + +PMHELP_GETPDB EQU 0026h +PMHELP_FLUSHTLB EQU 0027h + +enddataseg _pmdos + +P586 + +begcodeseg _pmdos ; Start of code segment + +ifndef flatmodel + +;---------------------------------------------------------------------------- +; void PM_callRealMode(unsigned s,unsigned o, RMREGS *regs, +; RMSREGS *sregs) +;---------------------------------------------------------------------------- +; Calls a real mode procedure, loading the appropriate registers values +; from the passed in structures. Only the DS and ES register are loaded +; from the SREGS structure. +;---------------------------------------------------------------------------- +cprocstart PM_callRealMode + + ARG s:WORD, o:WORD, regs:DWORD, sregs:DWORD + + LOCAL addr:DWORD, bxVal:WORD, esVal:WORD, flags:WORD = LocalSize + + enter_c + push ds + push es + + mov ax,[o] ; Build the address to call in 'addr' + mov [WORD addr],ax + mov ax,[s] + mov [WORD addr+2],ax + + les bx,[sregs] + mov ax,[RMSREGS.ds] + mov ds,ax ; DS := passed in value + mov ax,[RMSREGS.es] + mov [esVal],ax + les bx,[regs] + mov ax,[RMREGS.bx] + mov [bxVal],ax + mov ax,[RMREGS.ax] ; AX := passed in value + mov cx,[RMREGS.cx] ; CX := passed in value + mov dx,[RMREGS.dx] ; DX := passed in value + mov si,[RMREGS.si] ; SI := passed in value + mov di,[RMREGS.di] ; DI := passed in value + push bp + push [esVal] + pop es ; ES := passed in value + mov bx,[bxVal] ; BX := passed in value + + call [addr] ; Call the specified routine + + pushf ; Save flags for later + pop [flags] + + pop bp + push es + pop [esVal] + push bx + pop [bxVal] + les bx,[sregs] + push ds + pop [RMSREGS.ds] ; Save value of DS + push [esVal] + pop [RMSREGS.es] ; Save value of ES + les bx,[regs] + mov [RMREGS.ax],ax ; Save value of AX + mov [RMREGS.cx],cx ; Save value of CX + mov [RMREGS.dx],dx ; Save value of DX + mov [RMREGS.si],si ; Save value of SI + mov [RMREGS.di],di ; Save value of DI + mov ax,[flags] ; Return flags + and ax,1h ; Isolate carry flag + mov [RMREGS.cflag],ax ; Save carry flag status + mov ax,[bxVal] + mov [RMREGS.bx],ax ; Save value of BX + + pop es + pop ds + leave_c + ret + +cprocend + +endif + +;---------------------------------------------------------------------------- +; void PM_segread(PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Read the current value of all segment registers +;---------------------------------------------------------------------------- +cprocstartdll16 PM_segread + + ARG sregs:DPTR + + enter_c + + mov ax,es + _les _si,[sregs] + mov [_ES _si],ax + mov [_ES _si+2],cs + mov [_ES _si+4],ss + mov [_ES _si+6],ds + mov [_ES _si+8],fs + mov [_ES _si+10],gs + + leave_c + ret + +cprocend + +; Create a table of the 256 different interrupt calls that we can jump +; into + +ifdef USE_NASM + +%assign intno 0 + +intTable: +%rep 256 + db 0CDh + db intno +%assign intno intno + 1 + ret + nop +%endrep + +else + +intno = 0 + +intTable: + REPT 256 + db 0CDh + db intno +intno = intno + 1 + ret + nop + ENDM + +endif + +;---------------------------------------------------------------------------- +; _PM_genInt - Generate the appropriate interrupt +;---------------------------------------------------------------------------- +cprocnear _PM_genInt + + push _ax ; Save _ax + push _bx ; Save _bx +ifdef flatmodel + mov ebx,[UINT esp+12] ; EBX := interrupt number +else + mov bx,sp ; Make sure ESP is zeroed + mov bx,[UINT ss:bx+6] ; BX := interrupt number +endif + mov _ax,offset intTable ; Point to interrupt generation table + shl _bx,2 ; _BX := index into table + add _ax,_bx ; _AX := pointer to interrupt code +ifdef flatmodel + xchg eax,[esp+4] ; Restore eax, and set for int +else + mov bx,sp + xchg ax,[ss:bx+2] ; Restore ax, and set for int +endif + pop _bx ; restore _bx + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Issues a software interrupt in protected mode. This routine has been +; written to allow user programs to load CS and DS with different values +; other than the default. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_int386x + + ARG intno:UINT, inptr:DPTR, outptr:DPTR, sregs:DPTR + + LOCAL flags:UINT, sv_ds:UINT, sv_esi:ULONG = LocalSize + + enter_c + push ds + push es ; Save segment registers + push fs + push gs + + _lds _si,[sregs] ; DS:_SI -> Load segment registers + mov es,[_si] + mov bx,[_si+6] + mov [sv_ds],_bx ; Save value of user DS on stack + mov fs,[_si+8] + mov gs,[_si+10] + + _lds _si,[inptr] ; Load CPU registers + mov eax,[_si] + mov ebx,[_si+4] + mov ecx,[_si+8] + mov edx,[_si+12] + mov edi,[_si+20] + mov esi,[_si+16] + + push ds ; Save value of DS + push _bp ; Some interrupts trash this! + clc ; Generate the interrupt + push [UINT intno] + mov ds,[WORD sv_ds] ; Set value of user's DS selector + call _PM_genInt + pop _bp ; Pop intno from stack (flags unchanged) + pop _bp ; Restore value of stack frame pointer + pop ds ; Restore value of DS + + pushf ; Save flags for later + pop [UINT flags] + push esi ; Save ESI for later + pop [DWORD sv_esi] + push ds ; Save DS for later + pop [UINT sv_ds] + + _lds _si,[outptr] ; Save CPU registers + mov [_si],eax + mov [_si+4],ebx + mov [_si+8],ecx + mov [_si+12],edx + push [DWORD sv_esi] + pop [DWORD _si+16] + mov [_si+20],edi + + mov _bx,[flags] ; Return flags + and ebx,1h ; Isolate carry flag + mov [_si+24],ebx ; Save carry flag status + + _lds _si,[sregs] ; Save segment registers + mov [_si],es + mov _bx,[sv_ds] + mov [_si+6],bx ; Get returned DS from stack + mov [_si+8],fs + mov [_si+10],gs + + pop gs ; Restore segment registers + pop fs + pop es + pop ds + leave_c + ret + +cprocend + +ifndef flatmodel +_PM_savedDS dw _DATA ; Saved value of DS +endif + +;---------------------------------------------------------------------------- +; void PM_saveDS(void) +;---------------------------------------------------------------------------- +; Save the value of DS into a section of the code segment, so that we can +; quickly load this value at a later date in the PM_loadDS() routine from +; inside interrupt handlers etc. The method to do this is different +; depending on the DOS extender being used. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_saveDS + +ifdef flatmodel + mov [_PM_savedDS],ds ; Store away in data segment +endif + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_loadDS(void) +;---------------------------------------------------------------------------- +; Routine to load the DS register with the default value for the current +; DOS extender. Only the DS register is loaded, not the ES register, so +; if you wish to call C code, you will need to also load the ES register +; in 32 bit protected mode. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_loadDS + + mov ds,[cs:_PM_savedDS] ; We can access the proper DS through CS + ret + +cprocend + +ifdef flatmodel + +;---------------------------------------------------------------------------- +; ibool DPMI_allocateCallback(void (*pmcode)(), void *rmregs, long *RMCB) +;---------------------------------------------------------------------------- +cprocstart _DPMI_allocateCallback + + ARG pmcode:CPTR, rmregs:DPTR, RMCB:DPTR + + enter_c + push ds + push es + + push cs + pop ds + mov esi,[pmcode] ; DS:ESI -> protected mode code to call + mov edi,[rmregs] ; ES:EDI -> real mode register buffer + mov ax,303h ; AX := allocate realmode callback function + int 31h + mov eax,0 ; Return failure! + jc @@Fail + + mov eax,[RMCB] + shl ecx,16 + mov cx,dx + mov [es:eax],ecx ; Return real mode address + mov eax,1 ; Return success! + +@@Fail: pop es + pop ds + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void DPMI_freeCallback(long RMCB) +;---------------------------------------------------------------------------- +cprocstart _DPMI_freeCallback + + ARG RMCB:ULONG + + enter_c + + mov cx,[WORD RMCB+2] + mov dx,[WORD RMCB] ; CX:DX := real mode callback + mov ax,304h + int 31h + + leave_c + ret + +cprocend + +endif + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; uchar _PM_readCMOS(int index) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_readCMOS + + ARG index:UINT + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + in al,71h + mov ah,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + sti + mov al,ah ; Return value in AL + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_writeCMOS(int index,uchar value) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_writeCMOS + + ARG index:UINT, value:UCHAR + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + mov al,[value] + out 71h,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + sti + popfd + pop _bp + ret + +cprocend + +ifdef flatmodel + +;---------------------------------------------------------------------------- +; int _PM_pagingEnabled(void) +;---------------------------------------------------------------------------- +; Returns 1 if paging is enabled, 0 if not or -1 if not at ring 0 +;---------------------------------------------------------------------------- +cprocstart _PM_pagingEnabled + + mov eax,-1 +ifdef DOS4GW + mov cx,cs + and ecx,3 + jz @@Ring0 + cmp [UINT _PM_haveCauseWay],0 + jnz @@Ring0 + jmp @@Exit + +@@Ring0: + mov eax,cr0 ; Load CR0 + shr eax,31 ; Isolate paging enabled bit +endif +@@Exit: ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_getPDB - Return the Page Table Directory Base address +;---------------------------------------------------------------------------- +cprocstart _PM_getPDB + +ifdef DOS4GW + mov ax,cs + and eax,3 + jz @@Ring0 + cmp [UINT _PM_haveCauseWay],0 + jnz @@Ring0 +endif + +; Call VxD if running at ring 3 in a DOS box + + cmp [WORD _PM_VXD_sel],0 + jz @@Fail + mov eax,PMHELP_GETPDB +ifdef USE_NASM + call far dword [_PM_VXD_off] +else + call [FCPTR _PM_VXD_off] +endif + ret + +@@Ring0: +ifdef DOS4GW + mov eax,cr3 + and eax,0FFFFF000h + ret +endif +@@Fail: xor eax,eax + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_flushTLB - Flush the Translation Lookaside buffer +;---------------------------------------------------------------------------- +cprocstart PM_flushTLB + + mov ax,cs + and eax,3 + jz @@Ring0 +ifdef DOS4GW + cmp [UINT _PM_haveCauseWay],0 + jnz @@Ring0 +endif + +; Call VxD if running at ring 3 in a DOS box + + cmp [WORD _PM_VXD_sel],0 + jz @@Fail + mov eax,PMHELP_FLUSHTLB +ifdef USE_NASM + call far dword [_PM_VXD_off] +else + call [FCPTR _PM_VXD_off] +endif + ret + +@@Ring0: +ifdef DOS4GW + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB +endif +@@Fail: ret + +cprocend + +endif + +;---------------------------------------------------------------------------- +; void _PM_VxDCall(VXD_regs far *r,uint off,uint sel); +;---------------------------------------------------------------------------- +cprocstart _PM_VxDCall + + ARG r:DPTR, off:UINT, sel:UINT + + enter_c + +; Load all registers from the registers structure + + mov ebx,[r] + mov eax,[ebx+0] + mov ecx,[ebx+8] + mov edx,[ebx+12] + mov esi,[ebx+16] + mov edi,[ebx+20] + mov ebx,[ebx+4] ; Trashes BX structure pointer! + +; Call the VxD entry point (on stack) + +ifdef USE_NASM + call far dword [off] +else + call [FCPTR off] +endif + +; Save all registers back in the structure + + push ebx ; Push EBX onto stack for later + mov ebx,[r] + mov [ebx+0],eax + mov [ebx+8],ecx + mov [ebx+12],edx + mov [ebx+16],esi + mov [ebx+20],edi + pop [DWORD ebx+4] ; Save value of EBX from stack + + leave_c + ret + +cprocend + +endcodeseg _pmdos + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm new file mode 100644 index 0000000..5c741f3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm @@ -0,0 +1,1105 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: IBM PC Real mode and 16/32 bit protected mode +;* +;* Description: Low level assembly support for the PM library specific to +;* MSDOS interrupt handling. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmdos ; Set up memory model + +; Define the size of our local stacks. For real mode code they cant be +; that big, but for 32 bit protected mode code we can make them nice and +; large so that complex C functions can be used. + +ifdef flatmodel +MOUSE_STACK EQU 4096 +TIMER_STACK EQU 4096 +KEY_STACK EQU 1024 +INT10_STACK EQU 1024 +IRQ_STACK EQU 1024 +else +MOUSE_STACK EQU 1024 +TIMER_STACK EQU 512 +KEY_STACK EQU 256 +INT10_STACK EQU 256 +IRQ_STACK EQU 256 +endif + +ifdef USE_NASM + +; Macro to load DS and ES registers with correct value. + +%imacro LOAD_DS 0 +%ifdef flatmodel + mov ds,[cs:_PM_savedDS] + mov es,[cs:_PM_savedDS] +%else + push ax + mov ax,_DATA + mov ds,ax + pop ax +%endif +%endmacro + +; Note that interrupts we disable interrupts during the following stack +; %imacro for correct operation, but we do not enable them again. Normally +; these %imacros are used within interrupt handlers so interrupts should +; already be off. We turn them back on explicitly later if the user code +; needs them to be back on. + +; Macro to switch to a new local stack. + +%imacro NEWSTK 1 + cli + mov [seg_%1],ss + mov [ptr_%1],_sp + mov [TempSeg],ds + mov ss,[TempSeg] + mov _sp,offset %1 +%endmacro + +; %imacro to switch back to the old stack. + +%imacro RESTSTK 1 + cli + mov ss,[seg_%1] + mov _sp,[ptr_%1] +%endmacro + +; %imacro to swap the current stack with the one saved away. + +%imacro SWAPSTK 1 + cli + mov ax,ss + xchg ax,[seg_%1] + mov ss,ax + xchg _sp,[ptr_%1] +%endmacro + +else + +; Macro to load DS and ES registers with correct value. + +MACRO LOAD_DS +ifdef flatmodel + mov ds,[cs:_PM_savedDS] + mov es,[cs:_PM_savedDS] +else + push ax + mov ax,_DATA + mov ds,ax + pop ax +endif +ENDM + +; Note that interrupts we disable interrupts during the following stack +; macro for correct operation, but we do not enable them again. Normally +; these macros are used within interrupt handlers so interrupts should +; already be off. We turn them back on explicitly later if the user code +; needs them to be back on. + +; Macro to switch to a new local stack. + +MACRO NEWSTK stkname + cli + mov [seg_&stkname&],ss + mov [ptr_&stkname&],_sp + mov [TempSeg],ds + mov ss,[TempSeg] + mov _sp,offset stkname +ENDM + +; Macro to switch back to the old stack. + +MACRO RESTSTK stkname + cli + mov ss,[seg_&stkname&] + mov _sp,[ptr_&stkname&] +ENDM + +; Macro to swap the current stack with the one saved away. + +MACRO SWAPSTK stkname + cli + mov ax,ss + xchg ax,[seg_&stkname&] + mov ss,ax + xchg _sp,[ptr_&stkname&] +ENDM + +endif + +begdataseg _pmdos + +ifdef flatmodel + cextern _PM_savedDS,USHORT +endif + cextern _PM_critHandler,CPTR + cextern _PM_breakHandler,CPTR + cextern _PM_timerHandler,CPTR + cextern _PM_rtcHandler,CPTR + cextern _PM_keyHandler,CPTR + cextern _PM_key15Handler,CPTR + cextern _PM_mouseHandler,CPTR + cextern _PM_int10Handler,CPTR + + cextern _PM_ctrlCPtr,DPTR + cextern _PM_ctrlBPtr,DPTR + cextern _PM_critPtr,DPTR + + cextern _PM_prevTimer,FCPTR + cextern _PM_prevRTC,FCPTR + cextern _PM_prevKey,FCPTR + cextern _PM_prevKey15,FCPTR + cextern _PM_prevBreak,FCPTR + cextern _PM_prevCtrlC,FCPTR + cextern _PM_prevCritical,FCPTR + cextern _PM_prevRealTimer,ULONG + cextern _PM_prevRealRTC,ULONG + cextern _PM_prevRealKey,ULONG + cextern _PM_prevRealKey15,ULONG + cextern _PM_prevRealInt10,ULONG + +cpublic _PM_pmdosDataStart + +; Allocate space for all of the local stacks that we need. These stacks +; are not very large, but should be large enough for most purposes +; (generally you want to handle these interrupts quickly, simply storing +; the information for later and then returning). If you need bigger +; stacks then change the appropriate value in here. + + ALIGN 4 + dclb MOUSE_STACK ; Space for local stack (small) +MsStack: ; Stack starts at end! +ptr_MsStack DUINT 0 ; Place to store old stack offset +seg_MsStack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb INT10_STACK ; Space for local stack (small) +Int10Stack: ; Stack starts at end! +ptr_Int10Stack DUINT 0 ; Place to store old stack offset +seg_Int10Stack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb TIMER_STACK ; Space for local stack (small) +TmStack: ; Stack starts at end! +ptr_TmStack DUINT 0 ; Place to store old stack offset +seg_TmStack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb TIMER_STACK ; Space for local stack (small) +RtcStack: ; Stack starts at end! +ptr_RtcStack DUINT 0 ; Place to store old stack offset +seg_RtcStack dw 0 ; Place to store old stack segment +RtcInside dw 0 ; Are we still handling current interrupt + + ALIGN 4 + dclb KEY_STACK ; Space for local stack (small) +KyStack: ; Stack starts at end! +ptr_KyStack DUINT 0 ; Place to store old stack offset +seg_KyStack dw 0 ; Place to store old stack segment +KyInside dw 0 ; Are we still handling current interrupt + + ALIGN 4 + dclb KEY_STACK ; Space for local stack (small) +Ky15Stack: ; Stack starts at end! +ptr_Ky15Stack DUINT 0 ; Place to store old stack offset +seg_Ky15Stack dw 0 ; Place to store old stack segment + +TempSeg dw 0 ; Place to store stack segment + +cpublic _PM_pmdosDataEnd + +enddataseg _pmdos + +begcodeseg _pmdos ; Start of code segment + +cpublic _PM_pmdosCodeStart + +;---------------------------------------------------------------------------- +; PM_mouseISR - Mouse interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Interrupt subroutine called by the mouse driver upon interrupts, to +; dispatch control to high level C based subroutines. Interrupts are on +; when we call the user code. +; +; It is _extremely_ important to save the state of the extended registers +; as these may well be trashed by the routines called from here and not +; restored correctly by the mouse interface module. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. For mouse handlers this is not a +; problem, as the mouse driver arbitrates calls to the user mouse +; handler for us. +; +; Entry: AX - Condition mask giving reason for call +; BX - Mouse button state +; CX - Horizontal cursor coordinate +; DX - Vertical cursor coordinate +; SI - Horizontal mickey value +; DI - Vertical mickey value +; +;---------------------------------------------------------------------------- +ifdef DJGPP +cprocstart _PM_mouseISR +else +cprocfar _PM_mouseISR +endif + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + NEWSTK MsStack ; Switch to local stack + +; Call the installed high level C code routine + + clrhi dx ; Clear out high order values + clrhi cx + clrhi bx + clrhi ax + sgnhi si + sgnhi di + + push _di + push _si + push _dx + push _cx + push _bx + push _ax + sti ; Enable interrupts + call [CPTR _PM_mouseHandler] + _add sp,12,24 + + RESTSTK MsStack ; Restore previous stack + + popad ; Restore all extended registers + pop es + pop ds + ret ; We are done!! + +cprocend + +;---------------------------------------------------------------------------- +; PM_timerISR - Timer interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_timerISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + + NEWSTK TmStack ; Switch to local stack + call [CPTR _PM_timerHandler] + RESTSTK TmStack ; Restore previous stack + + popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; PM_chainPrevTimer - Chain to previous timer interrupt and return +;---------------------------------------------------------------------------- +; Chains to the previous timer interrupt routine and returns control +; back to the high level interrupt handler. +;---------------------------------------------------------------------------- +cprocstart PM_chainPrevTimer + +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealTimer] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax + ret +else + SWAPSTK TmStack ; Swap back to previous stack + pushf ; Save state of interrupt flag + pushf ; Push flags on stack to simulate interrupt +ifdef USE_NASM + call far dword [_PM_prevTimer] +else + call [_PM_prevTimer] +endif + popf ; Restore state of interrupt flag + SWAPSTK TmStack ; Swap back to C stack again + ret +endif + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; PM_rtcISR - Real time clock interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_rtcISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + +; Clear priority interrupt controller and re-enable interrupts so we +; dont lock things up for long. + + mov al,20h + out 0A0h,al + out 020h,al + +; Clear real-time clock timeout + + in al,70h ; Read CMOS index register + push _ax ; and save for later + IODELAYN 3 + mov al,0Ch + out 70h,al + IODELAYN 5 + in al,71h + +; Call the C interrupt handler function + + LOAD_DS ; Load DS register + cmp [BYTE RtcInside],1 ; Check for mutual exclusion + je @@Exit + mov [BYTE RtcInside],1 + NEWSTK RtcStack ; Switch to local stack + sti ; Re-enable interrupts + call [CPTR _PM_rtcHandler] + RESTSTK RtcStack ; Restore previous stack + mov [BYTE RtcInside],0 + +@@Exit: pop _ax + out 70h,al ; Restore CMOS index register + popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +cprocend + +ifdef flatmodel +;---------------------------------------------------------------------------- +; PM_irqISRTemplate - Hardware interrupt handler IRQ template +;---------------------------------------------------------------------------- +; Hardware interrupt handler for any interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible. +;---------------------------------------------------------------------------- +cprocfar _PM_irqISRTemplate + + push ebx + mov ebx,0 ; Relocation adjustment factor + jmp __IRQEntry + +; Global variables stored in the IRQ thunk code segment + +_CHandler dd 0 ; Pointer to C interrupt handler +_PrevIRQ dd 0 ; Previous IRQ handler + dd 0 +_IRQ dd 0 ; IRQ we are hooked for +ptr_IRQStack DUINT 0 ; Place to store old stack offset +seg_IRQStack dw 0 ; Place to store old stack segment +_Inside db 0 ; Mutual exclusion flag + ALIGN 4 + dclb IRQ_STACK ; Space for local stack +_IRQStack: ; Stack starts at end! + +; Check for and reject spurious IRQ 7 signals + +__IRQEntry: + cmp [BYTE cs:ebx+_IRQ],7 ; Spurious IRQs occur only on IRQ 7 + jmp @@ValidIRQ + push eax + mov al,1011b ; OCW3: read ISR + out 20h,al ; (Intel Peripheral Components, 1991, + in al,20h ; p. 3-188) + shl al,1 ; Set C = bit 7 (IRQ 7) of ISR register + pop eax + jc @@ValidIRQ + iret ; Return from interrupt + +; Save all registers for duration of IRQ handler + +@@ValidIRQ: + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + LOAD_DS ; Load DS register + +; Send an EOI to the PIC + + mov al,20h ; Send EOI to PIC + cmp [BYTE ebx+_IRQ],8 ; Clear PIC1 first if IRQ >= 8 + jb @@1 + out 0A0h,al +@@1: out 20h,al + +; Check for mutual exclusion + + cmp [BYTE ebx+_Inside],1 + je @@ChainOldHandler + mov [BYTE ebx+_Inside],1 + +; Call the C interrupt handler function + + mov [ebx+seg_IRQStack],ss ; Switch to local stack + mov [ebx+ptr_IRQStack],esp + mov [TempSeg],ds + mov ss,[TempSeg] + lea esp,[ebx+_IRQStack] + sti ; Re-enable interrupts + push ebx + call [DWORD ebx+_CHandler] + pop ebx + cli + mov ss,[ebx+seg_IRQStack] ; Restore previous stack + mov esp,[ebx+ptr_IRQStack] + or eax,eax + jz @@ChainOldHandler ; Chain if not handled for shared IRQ + +@@Exit: mov [BYTE ebx+_Inside],0 + popad ; Restore all extended registers + pop es + pop ds + pop ebx + iret ; Return from interrupt + +@@ChainOldHandler: + cmp [DWORD ebx+_PrevIRQ],0 + jz @@Exit + mov [BYTE ebx+_Inside],0 + mov eax,[DWORD ebx+_PrevIRQ] + mov ebx,[DWORD ebx+_PrevIRQ+4] + mov [DWORD _PrevIRQ],eax + mov [DWORD _PrevIRQ+4],ebx + popad ; Restore all extended registers + pop es + pop ds + pop ebx + jmp [cs:_PrevIRQ] ; Chain to previous IRQ handler + +cprocend +cpublic _PM_irqISRTemplateEnd +endif + +;---------------------------------------------------------------------------- +; PM_keyISR - keyboard interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the keyboard interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. However we ensure within this routine +; mutual exclusion to the keyboard handling routine. +;---------------------------------------------------------------------------- +cprocfar _PM_keyISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + + cmp [BYTE KyInside],1 ; Check for mutual exclusion + je @@Reissued + + mov [BYTE KyInside],1 + NEWSTK KyStack ; Switch to local stack + call [CPTR _PM_keyHandler] ; Call C code + RESTSTK KyStack ; Restore previous stack + mov [BYTE KyInside],0 + +@@Exit: popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +; When the BIOS keyboard handler needs to change the SHIFT status lights +; on the keyboard, in the process of doing this the keyboard controller +; re-issues another interrupt, while the current handler is still executing. +; If we recieve another interrupt while still handling the current one, +; then simply chain directly to the previous handler. +; +; Note that for most DOS extenders, the real mode interrupt handler that we +; install takes care of this for us. + +@@Reissued: +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax +else + pushf +ifdef USE_NASM + call far dword [_PM_prevKey] +else + call [_PM_prevKey] +endif +endif + jmp @@Exit + +cprocend + +;---------------------------------------------------------------------------- +; PM_chainPrevkey - Chain to previous key interrupt and return +;---------------------------------------------------------------------------- +; Chains to the previous key interrupt routine and returns control +; back to the high level interrupt handler. +;---------------------------------------------------------------------------- +cprocstart PM_chainPrevKey + +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax + ret +else + +; YIKES! For some strange reason, when execution returns from the +; previous keyboard handler, interrupts are re-enabled!! Since we expect +; interrupts to remain off during the duration of our handler, this can +; cause havoc. However our stack macros always turn off interrupts, so they +; will be off when we exit this routine. Obviously there is a tiny weeny +; window when interrupts will be enabled, but there is nothing we can +; do about this. + + SWAPSTK KyStack ; Swap back to previous stack + pushf ; Push flags on stack to simulate interrupt +ifdef USE_NASM + call far dword [_PM_prevKey] +else + call [_PM_prevKey] +endif + SWAPSTK KyStack ; Swap back to C stack again + ret +endif + +cprocend + +;---------------------------------------------------------------------------- +; PM_key15ISR - Int 15h keyboard interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; This routine gets called if we have been called to handle the Int 15h +; keyboard interrupt callout from real mode. +; +; Entry: AX - Hardware scan code to process +; Exit: AX - Hardware scan code to process (0 to ignore) +;---------------------------------------------------------------------------- +cprocfar _PM_key15ISR + + push ds + push es + LOAD_DS + cmp ah,4Fh + jnz @@NotOurs ; Quit if not keyboard callout + + pushad + cld ; Clear direction flag + xor ah,ah ; AX := scan code + NEWSTK Ky15Stack ; Switch to local stack + push _ax + call [CPTR _PM_key15Handler] ; Call C code + _add sp,2,4 + RESTSTK Ky15Stack ; Restore previous stack + test ax,ax + jz @@1 + stc ; Set carry to process as normal + jmp @@2 +@@1: clc ; Clear carry to ignore scan code +@@2: popad + jmp @@Exit ; We are done + +@@NotOurs: +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey15] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax +else + pushf +ifdef USE_NASM + call far dword [_PM_prevKey15] +else + call [_PM_prevKey15] +endif +endif +@@Exit: pop es + pop ds +ifdef flatmodel + retf 4 +else + retf 2 +endif + +cprocend + +;---------------------------------------------------------------------------- +; PM_breakISR - Control Break interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the Ctrl-Break interrupt. We simply set +; the Ctrl-Break flag to a 1 and leave (note that this is accessed through +; a far pointer, as it may well be located in conventional memory). +;---------------------------------------------------------------------------- +cprocfar _PM_breakISR + + sti + push ds ; Save value of DS + push es + push _bx + + LOAD_DS ; Load DS register +ifdef flatmodel + mov ebx,[_PM_ctrlBPtr] +else + les bx,[_PM_ctrlBPtr] +endif + mov [UINT _ES _bx],1 + +; Run alternate break handler code if installed + + cmp [CPTR _PM_breakHandler],0 + je @@Exit + + pushad + mov _ax,1 + push _ax + call [CPTR _PM_breakHandler] ; Call C code + pop _ax + popad + +@@Exit: pop _bx + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; int PM_ctrlBreakHit(int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the Ctrl-Break flag and possibly clears it. +;---------------------------------------------------------------------------- +cprocstart PM_ctrlBreakHit + + ARG clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es +ifdef flatmodel + mov ebx,[_PM_ctrlBPtr] +else + les bx,[_PM_ctrlBPtr] +endif + cli ; No interrupts thanks! + mov _ax,[_ES _bx] + test [BYTE clearFlag],1 + jz @@Done + mov [UINT _ES _bx],0 + +@@Done: pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_ctrlCISR - Control Break interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the Ctrl-C interrupt. We simply set +; the Ctrl-C flag to a 1 and leave (note that this is accessed through +; a far pointer, as it may well be located in conventional memory). +;---------------------------------------------------------------------------- +cprocfar _PM_ctrlCISR + + sti + push ds ; Save value of DS + push es + push _bx + + LOAD_DS ; Load DS register +ifdef flatmodel + mov ebx,[_PM_ctrlCPtr] +else + les bx,[_PM_ctrlCPtr] +endif + mov [UINT _ES _bx],1 + +; Run alternate break handler code if installed + + cmp [CPTR _PM_breakHandler],0 + je @@Exit + + pushad + mov _ax,0 + push _ax + call [CPTR _PM_breakHandler] ; Call C code + pop _ax + popad + +@@Exit: pop _bx + pop es + pop ds + iret ; Return from interrupt + iretd + +cprocend + +;---------------------------------------------------------------------------- +; int PM_ctrlCHit(int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the Ctrl-C flag and possibly clears it. +;---------------------------------------------------------------------------- +cprocstart PM_ctrlCHit + + ARG clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es +ifdef flatmodel + mov ebx,[_PM_ctrlCPtr] +else + les bx,[_PM_ctrlCPtr] +endif + cli ; No interrupts thanks! + mov _ax,[_ES _bx] + test [BYTE clearFlag],1 + jz @@Done + mov [UINT _ES _bx],0 + +@@Done: + pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_criticalISR - Control Error handler interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Interrupt handler for the MSDOS Critical Error interrupt, to dispatch +; control to high level C based subroutines. We save the state of all +; registers in this routine, and switch to a local stack. We also pass +; the values of the AX and DI registers to the as pointers, so that the +; values can be modified before returning to MSDOS. +;---------------------------------------------------------------------------- +cprocfar _PM_criticalISR + + sti + push ds ; Save value of DS + push es + push _bx ; Save register values changed + cld ; Clear direction flag + + LOAD_DS ; Load DS register +ifdef flatmodel + mov ebx,[_PM_critPtr] +else + les bx,[_PM_critPtr] +endif + mov [_ES _bx],ax + mov [_ES _bx+2],di + +; Run alternate critical handler code if installed + + cmp [CPTR _PM_critHandler],0 + je @@NoAltHandler + + pushad + push _di + push _ax + call [CPTR _PM_critHandler] ; Call C code + _add sp,4,8 + popad + + pop _bx + pop es + pop ds + iret ; Return from interrupt + +@@NoAltHandler: + mov ax,3 ; Tell MSDOS to fail the operation + pop _bx + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; int PM_criticalError(int *axVal,int *diVal,int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the critical error flags, and the values that +; MSDOS passed in the AX and DI registers to our handler. +;---------------------------------------------------------------------------- +cprocstart PM_criticalError + + ARG axVal:DPTR, diVal:DPTR, clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es +ifdef flatmodel + mov ebx,[_PM_critPtr] +else + les bx,[_PM_critPtr] +endif + cli ; No interrupts thanks! + xor _ax,_ax + xor _di,_di + mov ax,[_ES _bx] + mov di,[_ES _bx+2] + test [BYTE clearFlag],1 + jz @@NoClear + mov [ULONG _ES _bx],0 +@@NoClear: + _les _bx,[axVal] + mov [_ES _bx],_ax + _les _bx,[diVal] + mov [_ES _bx],_di + pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setMouseHandler(int mask, PM_mouseHandler mh) +;---------------------------------------------------------------------------- +cprocstart _PM_setMouseHandler + + ARG mouseMask:UINT + + enter_c + push es + + mov ax,0Ch ; AX := Function 12 - install interrupt sub + mov _cx,[mouseMask] ; CX := mouse mask + mov _dx,offset _PM_mouseISR + push cs + pop es ; ES:_DX -> mouse handler + int 33h ; Call mouse driver + + pop es + leave_c + ret + +cprocend + +ifdef flatmodel + +;---------------------------------------------------------------------------- +; void PM_mousePMCB(void) +;---------------------------------------------------------------------------- +; Mouse realmode callback routine. Upon entry to this routine, we recieve +; the following from the DPMI server: +; +; Entry: DS:_SI -> Real mode stack at time of call +; ES:_DI -> Real mode register data structure +; SS:_SP -> Locked protected mode stack to use +;---------------------------------------------------------------------------- +cprocfar _PM_mousePMCB + + pushad + mov eax,[es:_di+1Ch] ; Load register values from real mode + mov ebx,[es:_di+10h] + mov ecx,[es:_di+18h] + mov edx,[es:_di+14h] + mov esi,[es:_di+04h] + mov edi,[es:_di] + call _PM_mouseISR ; Call the mouse handler + popad + + mov ax,[ds:_si] + mov [es:_di+2Ah],ax ; Plug in return IP address + mov ax,[ds:_si+2] + mov [es:_di+2Ch],ax ; Plug in return CS value + add [WORD es:_di+2Eh],4 ; Remove return address from stack + iret ; Go back to real mode! + +cprocend + +;---------------------------------------------------------------------------- +; void PM_int10PMCB(void) +;---------------------------------------------------------------------------- +; int10 realmode callback routine. Upon entry to this routine, we recieve +; the following from the DPMI server: +; +; Entry: DS:ESI -> Real mode stack at time of call +; ES:EDI -> Real mode register data structure +; SS:ESP -> Locked protected mode stack to use +;---------------------------------------------------------------------------- +cprocfar _PM_int10PMCB + + pushad + push ds + push es + push fs + + pushfd + pop eax + mov [es:edi+20h],ax ; Save return flag status + mov ax,[ds:esi] + mov [es:edi+2Ah],ax ; Plug in return IP address + mov ax,[ds:esi+2] + mov [es:edi+2Ch],ax ; Plug in return CS value + add [WORD es:edi+2Eh],4 ; Remove return address from stack + +; Call the install int10 handler in protected mode. This function gets called +; with DS set to the current data selector, and ES:EDI pointing the the +; real mode DPMI register structure at the time of the interrupt. The +; handle must be written in assembler to be able to extract the real mode +; register values from the structure + + push es + pop fs ; FS:EDI -> real mode registers + LOAD_DS + NEWSTK Int10Stack ; Switch to local stack + + call [_PM_int10Handler] + + RESTSTK Int10Stack ; Restore previous stack + pop fs + pop es + pop ds + popad + iret ; Go back to real mode! + +cprocend + +endif + +cpublic _PM_pmdosCodeEnd + +endcodeseg _pmdos + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm new file mode 100644 index 0000000..34985a9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm @@ -0,0 +1,652 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Based on original code Copyright 1994 Otto Chrons +;* +;* Language: 80386 Assembler, TASM 4.0 or later +;* Environment: IBM PC 32 bit protected mode +;* +;* Description: Low level page fault handler for virtual linear framebuffers. +;* +;**************************************************************************** + + IDEAL + JUMPS + +include "scitech.mac" ; Memory model macros + +header _vflat ; Set up memory model + +VFLAT_START EQU 0F0000000h +VFLAT_END EQU 0F03FFFFFh +PAGE_PRESENT EQU 1 +PAGE_NOTPRESENT EQU 0 +PAGE_READ EQU 0 +PAGE_WRITE EQU 2 + +ifdef DOS4GW + +;---------------------------------------------------------------------------- +; DOS4G/W flat linear framebuffer emulation. +;---------------------------------------------------------------------------- + +begdataseg _vflat + +; Near pointers to the page directory base and our page tables. All of +; this memory is always located in the first Mb of DOS memory. + +PDBR dd 0 ; Page directory base register (CR3) +accessPageAddr dd 0 +accessPageTable dd 0 + +; CauseWay page directory & 1st page table linear addresses. + +CauseWayDIRLinear dd 0 +CauseWay1stLinear dd 0 + +; Place to store a copy of the original Page Table Directory before we +; intialised our virtual buffer code. + +pageDirectory: resd 1024 ; Saved page table directory + +ValidCS dw 0 ; Valid CS for page faults +Ring0CS dw 0 ; Our ring 0 code selector +LastPage dd 0 ; Last page we mapped in +BankFuncBuf: resb 101 ; Place to store bank switch code +BankFuncPtr dd offset BankFuncBuf + +INT14Gate: +INT14Offset dd 0 ; eip of original vector +INT14Selector dw 0 ; cs of original vector + + cextern _PM_savedDS,USHORT + cextern VF_haveCauseWay,BOOL + +enddataseg _vflat + +begcodeseg _vflat ; Start of code segment + + cextern VF_malloc,FPTR + +;---------------------------------------------------------------------------- +; PF_handler64k - Page fault handler for 64k banks +;---------------------------------------------------------------------------- +; The handler below is a 32 bit ring 0 page fault handler. It receives +; control immediately after any page fault or after an IRQ6 (hardware +; interrupt). This provides the fastest possible handling of page faults +; since it jump directly here. If this is a page fault, the number +; immediately on the stack will be an error code, at offset 4 will be +; the eip of the faulting instruction, at offset 8 will be the cs of the +; faulting instruction. If it is a hardware interrupt, it will not have +; the error code and the eflags will be at offset 8. +;---------------------------------------------------------------------------- +cprocfar PF_handler64k + +; Check if this is a processor exeception or a page fault + + push eax + mov ax,[cs:ValidCS] ; Use CS override to access data + cmp [ss:esp+12],ax ; Is this a page fault? + jne @@ToOldHandler ; Nope, jump to the previous handler + +; Get address of page fault and check if within our handlers range + + mov eax,cr2 ; EBX has page fault linear address + cmp eax,VFLAT_START ; Is the fault less than ours? + jb @@ToOldHandler ; Yep, go to previous handler + cmp eax,VFLAT_END ; Is the fault more than ours? + jae @@ToOldHandler ; Yep, go to previous handler + +; This is our page fault, so we need to handle it + + pushad + push ds + push es + mov ebx,eax ; EBX := page fault address + and ebx,invert 0FFFFh ; Mask to 64k bank boundary + mov ds,[cs:_PM_savedDS]; Load segment registers + mov es,[cs:_PM_savedDS] + +; Map in the page table for our virtual framebuffer area for modification + + mov edi,[PDBR] ; EDI points to page directory + mov edx,ebx ; EDX = linear address + shr edx,22 ; EDX = offset to page directory + mov edx,[edx*4+edi] ; EDX = physical page table address + mov eax,edx + mov edx,[accessPageTable] + or eax,7 + mov [edx],eax + mov eax,cr3 + mov cr3,eax ; Update page table cache + +; Mark all pages valid for the new page fault area + + mov esi,ebx ; ESI := linear address for page + shr esi,10 + and esi,0FFFh ; Offset into page table + add esi,[accessPageAddr] +ifdef USE_NASM +%assign off 0 +%rep 16 + or [DWORD esi+off],0000000001h ; Enable pages +%assign off off+4 +%endrep +else +off = 0 +REPT 16 + or [DWORD esi+off],0000000001h ; Enable pages +off = off+4 +ENDM +endif + +; Mark all pages invalid for the previously mapped area + + xchg esi,[LastPage] ; Save last page for next page fault + test esi,esi + jz @@DoneMapping ; Dont update if first time round +ifdef USE_NASM +%assign off 0 +%rep 16 + or [DWORD esi+off],0FFFFFFFEh ; Disable pages +%assign off off+4 +%endrep +else +off = 0 +REPT 16 + and [DWORD esi+off],0FFFFFFFEh ; Disable pages +off = off+4 +ENDM +endif + +@@DoneMapping: + mov eax,cr3 + mov cr3,eax ; Flush the TLB + +; Now program the new SuperVGA starting bank address + + mov eax,ebx ; EAX := page fault address + shr eax,16 + and eax,0FFh ; Mask to 0-255 + call [BankFuncPtr] ; Call the bank switch function + + pop es + pop ds + popad + pop eax + add esp,4 ; Pop the error code from stack + iretd ; Return to faulting instruction + +@@ToOldHandler: + pop eax +ifdef USE_NASM + jmp far dword [cs:INT14Gate]; Chain to previous handler +else + jmp [FWORD cs:INT14Gate]; Chain to previous handler +endif + +cprocend + +;---------------------------------------------------------------------------- +; PF_handler4k - Page fault handler for 4k banks +;---------------------------------------------------------------------------- +; The handler below is a 32 bit ring 0 page fault handler. It receives +; control immediately after any page fault or after an IRQ6 (hardware +; interrupt). This provides the fastest possible handling of page faults +; since it jump directly here. If this is a page fault, the number +; immediately on the stack will be an error code, at offset 4 will be +; the eip of the faulting instruction, at offset 8 will be the cs of the +; faulting instruction. If it is a hardware interrupt, it will not have +; the error code and the eflags will be at offset 8. +;---------------------------------------------------------------------------- +cprocfar PF_handler4k + +; Fill in when we have tested all the 64Kb code + +ifdef USE_NASM + jmp far dword [cs:INT14Gate]; Chain to previous handler +else + jmp [FWORD cs:INT14Gate]; Chain to previous handler +endif + +cprocend + +;---------------------------------------------------------------------------- +; void InstallFaultHandler(void *baseAddr,int bankSize) +;---------------------------------------------------------------------------- +; Installes the page fault handler directly int the interrupt descriptor +; table for maximum performance. This of course requires ring 0 access, +; but none of this stuff will run without ring 0! +;---------------------------------------------------------------------------- +cprocstart InstallFaultHandler + + ARG baseAddr:ULONG, bankSize:UINT + + enter_c + + mov [DWORD LastPage],0 ; No pages have been mapped + mov ax,cs + mov [ValidCS],ax ; Save CS value for page faults + +; Put address of our page fault handler into the IDT directly + + sub esp,6 ; Allocate space on stack +ifdef USE_NASM + sidt [ss:esp] ; Store pointer to IDT +else + sidt [FWORD ss:esp] ; Store pointer to IDT +endif + pop ax ; add esp,2 + pop eax ; Absolute address of IDT + add eax,14*8 ; Point to Int #14 + +; Note that Interrupt gates do not have the high and low word of the +; offset in adjacent words in memory, there are 4 bytes separating them. + + mov ecx,[eax] ; Get cs and low 16 bits of offset + mov edx,[eax+6] ; Get high 16 bits of offset in dx + shl edx,16 + mov dx,cx ; edx has offset + mov [INT14Offset],edx ; Save offset + shr ecx,16 + mov [INT14Selector],cx ; Save original cs + mov [eax+2],cs ; Install new cs + mov edx,offset PF_handler64k + cmp [UINT bankSize],4 + jne @@1 + mov edx,offset PF_handler4k +@@1: mov [eax],dx ; Install low word of offset + shr edx,16 + mov [eax+6],dx ; Install high word of offset + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void RemoveFaultHandler(void) +;---------------------------------------------------------------------------- +; Closes down the virtual framebuffer services and restores the previous +; page fault handler. +;---------------------------------------------------------------------------- +cprocstart RemoveFaultHandler + + enter_c + +; Remove page fault handler from IDT + + sub esp,6 ; Allocate space on stack +ifdef USE_NASM + sidt [ss:esp] ; Store pointer to IDT +else + sidt [FWORD ss:esp] ; Store pointer to IDT +endif + + pop ax ; add esp,2 + pop eax ; Absolute address of IDT + add eax,14*8 ; Point to Int #14 + mov cx,[INT14Selector] + mov [eax+2],cx ; Restore original CS + mov edx,[INT14Offset] + mov [eax],dx ; Install low word of offset + shr edx,16 + mov [eax+6],dx ; Install high word of offset + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void InstallBankFunc(int codeLen,void *bankFunc) +;---------------------------------------------------------------------------- +; Installs the bank switch function by relocating it into our data segment +; and making it into a callable function. We do it this way to make the +; code identical to the way that the VflatD devices work under Windows. +;---------------------------------------------------------------------------- +cprocstart InstallBankFunc + + ARG codeLen:UINT, bankFunc:DPTR + + enter_c + + mov esi,[bankFunc] ; Copy the code into buffer + mov edi,offset BankFuncBuf + mov ecx,[codeLen] + rep movsb + mov [BYTE edi],0C3h ; Terminate the function with a near ret + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int InitPaging(void) +;---------------------------------------------------------------------------- +; Initializes paging system. If paging is not enabled, builds a page table +; directory and page tables for physical memory +; +; Exit: 0 - Successful +; -1 - Couldn't initialize paging mechanism +;---------------------------------------------------------------------------- +cprocstart InitPaging + + push ebx + push ecx + push edx + push esi + push edi + +; Are we running under CauseWay? + + mov ax,0FFF9h + int 31h + jc @@NotCauseway + cmp ecx,"CAUS" + jnz @@NotCauseway + cmp edx,"EWAY" + jnz @@NotCauseway + + mov [BOOL VF_haveCauseWay],1 + mov [CauseWayDIRLinear],esi + mov [CauseWay1stLinear],edi + +; Check for DPMI + + mov ax,0ff00h + push es + int 31h + pop es + shr edi,2 + and edi,3 + cmp edi,2 + jz @@ErrExit ; Not supported under DPMI + + mov eax,[CauseWayDIRLinear] + jmp @@CopyCR3 + +@@NotCauseway: + mov ax,cs + test ax,3 ; Which ring are we running + jnz @@ErrExit ; Needs zero ring to access + ; page tables (CR3) + mov eax,cr0 ; Load CR0 + test eax,80000000h ; Is paging enabled? + jz @@ErrExit ; No, we must have paging! + + mov eax,cr3 ; Load directory address + and eax,0FFFFF000h + +@@CopyCR3: + mov [PDBR],eax ; Save it + mov esi,eax + mov edi,offset pageDirectory + mov ecx,1024 + cld + rep movsd ; Copy the original page table directory + cmp [DWORD accessPageAddr],0; Check if we have allocated page + jne @@HaveRealMem ; table already (we cant free it) + + mov eax,0100h ; DPMI DOS allocate + mov ebx,8192/16 + int 31h ; Allocate 8192 bytes + and eax,0FFFFh + shl eax,4 ; EAX points to newly allocated memory + add eax,4095 + and eax,0FFFFF000h ; Page align + mov [accessPageAddr],eax + +@@HaveRealMem: + mov eax,[accessPageAddr] ; EAX -> page table in 1st Mb + shr eax,12 + and eax,3FFh ; Page table offset + shl eax,2 + cmp [BOOL VF_haveCauseWay],0 + jz @@NotCW0 + mov ebx,[CauseWay1stLinear] + jmp @@Put1st + +@@NotCW0: + mov ebx,[PDBR] + mov ebx,[ebx] + and ebx,0FFFFF000h ; Page table for 1st megabyte + +@@Put1st: + add eax,ebx + mov [accessPageTable],eax + sub eax,eax ; No error + jmp @@Exit + +@@ErrExit: + mov eax,-1 + +@@Exit: pop edi + pop esi + pop edx + pop ecx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void ClosePaging(void) +;---------------------------------------------------------------------------- +; Closes the paging system +;---------------------------------------------------------------------------- +cprocstart ClosePaging + + push eax + push ecx + push edx + push esi + push edi + + mov eax,[accessPageAddr] + call AccessPage ; Restore AccessPage mapping + mov edi,[PDBR] + mov esi,offset pageDirectory + mov ecx,1024 + cld + rep movsd ; Restore the original page table directory + +@@Exit: pop edi + pop esi + pop edx + pop ecx + pop eax + ret + +cprocend + +;---------------------------------------------------------------------------- +; long AccessPage(long phys) +;---------------------------------------------------------------------------- +; Maps a known page to given physical memory +; Entry: EAX - Physical memory +; Exit: EAX - Linear memory address of mapped phys mem +;---------------------------------------------------------------------------- +cprocstatic AccessPage + + push edx + mov edx,[accessPageTable] + or eax,7 + mov [edx],eax + mov eax,cr3 + mov cr3,eax ; Update page table cache + mov eax,[accessPageAddr] + pop edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; long GetPhysicalAddress(long linear) +;---------------------------------------------------------------------------- +; Returns the physical address of linear address +; Entry: EAX - Linear address to convert +; Exit: EAX - Physical address +;---------------------------------------------------------------------------- +cprocstatic GetPhysicalAddress + + push ebx + push edx + mov edx,eax + shr edx,22 ; EDX is the directory offset + mov ebx,[PDBR] + mov edx,[edx*4+ebx] ; Load page table address + push eax + mov eax,edx + call AccessPage ; Access the page table + mov edx,eax + pop eax + shr eax,12 + and eax,03FFh ; EAX offset into page table + mov eax,[edx+eax*4] ; Load physical address + and eax,0FFFFF000h + pop edx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void CreatePageTable(long pageDEntry) +;---------------------------------------------------------------------------- +; Creates a page table for specific address (4MB) +; Entry: EAX - Page directory entry (top 10-bits of address) +;---------------------------------------------------------------------------- +cprocstatic CreatePageTable + + push ebx + push ecx + push edx + push edi + mov ebx,eax ; Save address + mov eax,8192 + push eax + call VF_malloc ; Allocate page table directory + add esp,4 + add eax,0FFFh + and eax,0FFFFF000h ; Page align (4KB) + mov edi,eax ; Save page table linear address + sub eax,eax ; Fill with zero + mov ecx,1024 + cld + rep stosd ; Clear page table + sub edi,4096 + mov eax,edi + call GetPhysicalAddress + mov edx,[PDBR] + or eax,7 ; Present/write/user bit + mov [edx+ebx*4],eax ; Save physical address into page directory + mov eax,cr3 + mov cr3,eax ; Update page table cache + pop edi + pop edx + pop ecx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags); +;---------------------------------------------------------------------------- +; Maps physical memory into linear memory +; Entry: pAddr - Physical address +; lAddr - Linear address +; pages - Number of 4K pages to map +; flags - Page flags +; bit 0 = present +; bit 1 = Read(0)/Write(1) +;---------------------------------------------------------------------------- +cprocstart MapPhysical2Linear + + ARG pAddr:ULONG, lAddr:ULONG, pages:UINT, pflags:UINT + + enter_c + + and [ULONG pAddr],0FFFFF000h; Page boundary + and [ULONG lAddr],0FFFFF000h; Page boundary + mov ecx,[pflags] + and ecx,11b ; Just two bits + or ecx,100b ; Supervisor bit + mov [pflags],ecx + + mov edx,[lAddr] + shr edx,22 ; EDX = Directory + mov esi,[PDBR] + mov edi,[pages] ; EDI page count + mov ebx,[lAddr] + +@@CreateLoop: + mov ecx,[esi+edx*4] ; Load page table address + test ecx,1 ; Is it present? + jnz @@TableOK + mov eax,edx + call CreatePageTable ; Create a page table +@@TableOK: + mov eax,ebx + shr eax,12 + and eax,3FFh + sub eax,1024 + neg eax ; EAX = page count in this table + inc edx ; Next table + mov ebx,0 ; Next time we'll map 1K pages + sub edi,eax ; Subtract mapped pages from page count + jns @@CreateLoop ; Create more tables if necessary + + mov ecx,[pages] ; ECX = Page count + mov esi,[lAddr] + shr esi,12 ; Offset part isn't needed + mov edi,[pAddr] +@@MappingLoop: + mov eax,esi + shr eax,10 ; EAX = offset to page directory + mov ebx,[PDBR] + mov eax,[eax*4+ebx] ; EAX = page table address + call AccessPage + mov ebx,esi + and ebx,3FFh ; EBX = offset to page table + mov edx,edi + add edi,4096 ; Next physical address + inc esi ; Next linear page + or edx,[pflags] ; Update flags... + mov [eax+ebx*4],edx ; Store page table entry + loop @@MappingLoop + mov eax,cr3 + mov cr3,eax ; Update page table cache + + leave_c + ret + +cprocend + +endcodeseg _vflat + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c new file mode 100644 index 0000000..ee117c7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c @@ -0,0 +1,72 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: DOS +* +* Description: MSDOS specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/* External timing function */ + +void __ZTimerInit(void); + +/**************************************************************************** +REMARKS: +Do nothing for DOS because we don't have thread priorities. +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for DOS because we don't have thread priorities. +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + ulong resolution; + + __ZTimerInit(); + ULZTimerResolution(&resolution); + freq->low = (ulong)(10000000000.0 / resolution); + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + (t)->low = ULZReadTime() * 10000L; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/event.c b/board/MAI/bios_emulator/scitech/src/pm/dos/event.c new file mode 100644 index 0000000..a969d11 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/event.c @@ -0,0 +1,494 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit DOS +* +* Description: 32-bit DOS implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*--------------------------- Global variables ----------------------------*/ + +ibool _VARAPI _EVT_useEvents = true; /* True to use event handling */ +ibool _VARAPI _EVT_installed = 0; /* Event handers installed? */ +uchar _VARAPI *_EVT_biosPtr = NULL; /* Pointer to the BIOS data area */ +static ibool haveMouse = false; /* True if we have a mouse */ + +/*---------------------------- Implementation -----------------------------*/ + +/* External assembler functions */ + +void EVTAPI _EVT_pollJoystick(void); +uint EVTAPI _EVT_disableInt(void); +uint EVTAPI _EVT_restoreInt(uint flags); +void EVTAPI _EVT_codeStart(void); +void EVTAPI _EVT_codeEnd(void); +void EVTAPI _EVT_cCodeStart(void); +void EVTAPI _EVT_cCodeEnd(void); +int EVTAPI _EVT_getKeyCode(void); +void EVTAPI _EVT_pumpMessages(void); +int EVTAPI EVT_rdinx(int port,int index); +void EVTAPI EVT_wrinx(int port,int index,int value); + +#ifdef NO_KEYBOARD_INTERRUPT +/**************************************************************************** +REMARKS: +This function is used to pump all keyboard messages from the BIOS keyboard +handler into our event queue. This can be used to avoid using the +installable keyboard handler if this is causing problems. +****************************************************************************/ +static void EVTAPI _EVT_pumpMessages(void) +{ + RMREGS regs; + uint key,ps; + + /* Since the keyboard ISR has not been installed if NO_IDE_BUG has + * been defined, we first check for any pending keyboard events + * here, and if there are some insert them into the event queue to + * be picked up later - what a kludge. + */ + while ((key = _EVT_getKeyCode()) != 0) { + ps = _EVT_disableInt(); + addKeyEvent(EVT_KEYDOWN, key); + _EVT_restoreInt(ps); + } + + regs.x.ax = 0x0B; /* Reset Move Mouse */ + PM_int86(0x33,®s,®s); +} +#endif + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + return (ulong)PM_getLong(_EVT_biosPtr+0x6C) * 55UL; +} + +/**************************************************************************** +REMARKS: +Reboots the machine from DOS (warm boot) +****************************************************************************/ +static void Reboot(void) +{ + PMREGS regs; + PMSREGS sregs; + + ushort *rebootType = PM_mapRealPointer(0x40,0x72); + *rebootType = 0x1234; + PM_callRealMode(0xFFFF,0x0000,®s,&sregs); +} + +/**************************************************************************** +REMARKS: +Include generic raw scancode keyboard module. +****************************************************************************/ +#define SUPPORT_CTRL_ALT_DEL +#include "common/keyboard.c" + +/**************************************************************************** +REMARKS: +This function fools the DOS mouse driver into thinking that it is running +in graphics mode, rather than text mode so we always get virtual coordinates +correctly rather than character coordinates. +****************************************************************************/ +int _EVT_foolMouse(void) +{ + int oldmode = PM_getByte(_EVT_biosPtr+0x49); + PM_setByte(_EVT_biosPtr+0x49,0x10); + oldmode |= (EVT_rdinx(0x3C4,0x2) << 8); + return oldmode; +} + +/**************************************************************************** +REMARKS: +This function unfools the DOS mouse driver after we have finished calling it. +****************************************************************************/ +void _EVT_unfoolMouse( + int oldmode) +{ + PM_setByte(_EVT_biosPtr+0x49,oldmode); + + /* Some mouse drivers reset the plane mask register for VGA plane 4 + * modes, which screws up the display on some VGA compatible controllers + * in SuperVGA modes. We reset the value back again in here to solve + * the problem. + */ + EVT_wrinx(0x3C4,0x2,oldmode >> 8); +} + +/**************************************************************************** +REMARKS: +Determines if we have a mouse attached and functioning. +****************************************************************************/ +static ibool detectMouse(void) +{ + RMREGS regs; + RMSREGS sregs; + uchar *p; + ibool retval; + + regs.x.ax = 0x3533; /* Get interrupt vector 0x33 */ + PM_int86x(0x21,®s,®s,&sregs); + + /* Check that interrupt vector 0x33 is not a zero, and that the first + * instruction in the interrupt vector is not an IRET instruction + */ + p = PM_mapRealPointer(sregs.es, regs.x.bx); + retval = ((sregs.es != 0) || (regs.x.bx != 0)) && (PM_getByte(p) != 207); + return retval; +} + +/**************************************************************************** +PARAMETERS: +what - Event code +message - Event message +x,y - Mouse position at time of event +but_stat - Mouse button status at time of event + +REMARKS: +Adds a new mouse event to the event queue. This routine is called from within +the mouse interrupt subroutine, so it must be efficient. + +NOTE: Interrupts MUST be OFF while this routine is called to ensure we have + mutually exclusive access to our internal data structures for + interrupt driven systems (like under DOS). +****************************************************************************/ +static void addMouseEvent( + uint what, + uint message, + int x, + int y, + int mickeyX, + int mickeyY, + uint but_stat) +{ + event_t evt; + + if (EVT.count < EVENTQSIZE) { + /* Save information in event record. */ + evt.when = _EVT_getTicks(); + evt.what = what; + evt.message = message; + evt.modifiers = but_stat; + evt.where_x = x; /* Save mouse event position */ + evt.where_y = y; + evt.relative_x = mickeyX; + evt.relative_y = mickeyY; + evt.modifiers |= EVT.keyModifiers; + addEvent(&evt); /* Add to tail of event queue */ + } +} + +/**************************************************************************** +PARAMETERS: +mask - Event mask +butstate - Button state +x - Mouse x coordinate +y - Mouse y coordinate + +REMARKS: +Mouse event handling routine. This gets called when a mouse event occurs, +and we call the addMouseEvent() routine to add the appropriate mouse event +to the event queue. + +Note: Interrupts are ON when this routine is called by the mouse driver code. +****************************************************************************/ +static void EVTAPI mouseISR( + uint mask, + uint butstate, + int x, + int y, + int mickeyX, + int mickeyY) +{ + uint ps; + uint buttonMask; + + if (mask & 1) { + /* Save the current mouse coordinates */ + EVT.mx = x; EVT.my = y; + + /* If the last event was a movement event, then modify the last + * event rather than post a new one, so that the queue will not + * become saturated. Before we modify the data structures, we + * MUST ensure that interrupts are off. + */ + ps = _EVT_disableInt(); + if (EVT.oldMove != -1) { + EVT.evtq[EVT.oldMove].where_x = x; /* Modify existing one */ + EVT.evtq[EVT.oldMove].where_y = y; + EVT.evtq[EVT.oldMove].relative_x += mickeyX; + EVT.evtq[EVT.oldMove].relative_y += mickeyY; + } + else { + EVT.oldMove = EVT.freeHead; /* Save id of this move event */ + addMouseEvent(EVT_MOUSEMOVE,0,x,y,mickeyX,mickeyY,butstate); + } + _EVT_restoreInt(ps); + } + if (mask & 0x2A) { + ps = _EVT_disableInt(); + buttonMask = 0; + if (mask & 2) buttonMask |= EVT_LEFTBMASK; + if (mask & 8) buttonMask |= EVT_RIGHTBMASK; + if (mask & 32) buttonMask |= EVT_MIDDLEBMASK; + addMouseEvent(EVT_MOUSEDOWN,buttonMask,x,y,0,0,butstate); + EVT.oldMove = -1; + _EVT_restoreInt(ps); + } + if (mask & 0x54) { + ps = _EVT_disableInt(); + buttonMask = 0; + if (mask & 2) buttonMask |= EVT_LEFTBMASK; + if (mask & 8) buttonMask |= EVT_RIGHTBMASK; + if (mask & 32) buttonMask |= EVT_MIDDLEBMASK; + addMouseEvent(EVT_MOUSEUP,buttonMask,x,y,0,0,butstate); + EVT.oldMove = -1; + _EVT_restoreInt(ps); + } + EVT.oldKey = -1; +} + +/**************************************************************************** +REMARKS: +Keyboard interrupt handler function. + +NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, + and we leave them OFF the entire time. +****************************************************************************/ +static void EVTAPI keyboardISR(void) +{ + processRawScanCode(PM_inpb(0x60)); + PM_outpb(0x20,0x20); +} + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + + PM_init(); + EVT.mouseMove = mouseMove; + _EVT_biosPtr = PM_getBIOSPointer(); + EVT_resume(); + + /* Grab all characters pending in the keyboard buffer and stuff + * them into our event buffer. This allows us to pick up any keypresses + * while the program is initialising. + */ + while ((i = _EVT_getKeyCode()) != 0) + addKeyEvent(EVT_KEYDOWN,i); +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVTAPI EVT_resume(void) +{ + static int locked = 0; + int stat; + uchar mods; + PM_lockHandle lh; /* Unused in DOS */ + + if (_EVT_useEvents) { + /* Initialise the event queue and enable our interrupt handlers */ + initEventQueue(); +#ifndef NO_KEYBOARD_INTERRUPT + PM_setKeyHandler(keyboardISR); +#endif +#ifndef NO_MOUSE_INTERRUPT + if ((haveMouse = detectMouse()) != 0) { + int oldmode = _EVT_foolMouse(); + PM_setMouseHandler(0xFFFF,mouseISR); + _EVT_unfoolMouse(oldmode); + } +#endif + + /* Read the keyboard modifier flags from the BIOS to get the + * correct initialisation state. The only state we care about is + * the correct toggle state flags such as SCROLLLOCK, NUMLOCK and + * CAPSLOCK. + */ + EVT.keyModifiers = 0; + mods = PM_getByte(_EVT_biosPtr+0x17); + if (mods & 0x10) + EVT.keyModifiers |= EVT_SCROLLLOCK; + if (mods & 0x20) + EVT.keyModifiers |= EVT_NUMLOCK; + if (mods & 0x40) + EVT.keyModifiers |= EVT_CAPSLOCK; + + /* Lock all of the code and data used by our protected mode interrupt + * handling routines, so that it will continue to work correctly + * under real mode. + */ + if (!locked) { + /* It is difficult to ensure that we lock our global data, so we + * do this by taking the address of a variable locking all data + * 2Kb on either side. This should properly cover the global data + * used by the module (the other alternative is to declare the + * variables in assembler, in which case we know it will be + * correct). + */ + stat = !PM_lockDataPages(&EVT,sizeof(EVT),&lh); + stat |= !PM_lockDataPages(&_EVT_biosPtr,sizeof(_EVT_biosPtr),&lh); + stat |= !PM_lockCodePages((__codePtr)_EVT_cCodeStart,(int)_EVT_cCodeEnd-(int)_EVT_cCodeStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_EVT_codeStart,(int)_EVT_codeEnd-(int)_EVT_codeStart,&lh); + if (stat) { + PM_fatalError("Page locking services failed - interrupt handling not safe!"); + exit(1); + } + locked = 1; + } + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); + _EVT_installed = true; + } +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + RMREGS regs; + + if (haveMouse) { + int oldmode = _EVT_foolMouse(); + PM_resetMouseDriver(1); + regs.x.ax = 7; /* Mouse function 7 - Set horizontal min and max */ + regs.x.cx = 0; + regs.x.dx = xRes; + PM_int86(0x33,®s,®s); + regs.x.ax = 8; /* Mouse function 8 - Set vertical min and max */ + regs.x.cx = 0; + regs.x.dx = yRes; + PM_int86(0x33,®s,®s); + _EVT_unfoolMouse(oldmode); + } +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +void _EVT_setMousePos( + int *x, + int *y) +{ + RMREGS regs; + + if (haveMouse) { + int oldmode = _EVT_foolMouse(); + regs.x.ax = 4; /* Mouse function 4 - Set mouse position */ + regs.x.cx = *x; /* New horizontal coordinate */ + regs.x.dx = *y; /* New vertical coordinate */ + PM_int86(0x33,®s,®s); + _EVT_unfoolMouse(oldmode); + } +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVTAPI EVT_suspend(void) +{ + uchar mods; + + if (_EVT_installed) { + /* Restore the interrupt handlers */ + PM_restoreKeyHandler(); + if (haveMouse) + PM_restoreMouseHandler(); + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* Set the keyboard modifier flags in the BIOS to our values */ + EVT_allowLEDS(true); + mods = PM_getByte(_EVT_biosPtr+0x17) & ~0x70; + if (EVT.keyModifiers & EVT_SCROLLLOCK) + mods |= 0x10; + if (EVT.keyModifiers & EVT_NUMLOCK) + mods |= 0x20; + if (EVT.keyModifiers & EVT_CAPSLOCK) + mods |= 0x40; + PM_setByte(_EVT_biosPtr+0x17,mods); + + /* Flag that we are no longer installed */ + _EVT_installed = false; + } +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVTAPI EVT_exit(void) +{ + EVT_suspend(); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h new file mode 100644 index 0000000..35e8e00 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h @@ -0,0 +1,29 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit DOS +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c b/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c new file mode 100644 index 0000000..2ad9e34 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c @@ -0,0 +1,2243 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 16/32 bit DOS +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "ztimerc.h" +#include "mtrr.h" +#include "pm_help.h" +#include +#include +#include +#include +#include +#ifdef __GNUC__ +#include +#include +#include +#else +#include +#endif +#ifdef __BORLANDC__ +#pragma warn -par +#endif + +/*--------------------------- Global variables ----------------------------*/ + +typedef struct { + int oldMode; + int old50Lines; + } DOS_stateBuf; + +#define MAX_RM_BLOCKS 10 + +static struct { + void *p; + uint tag; + } rmBlocks[MAX_RM_BLOCKS]; + +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +static void (PMAPIP fatalErrorCleanup)(void) = NULL; +ushort _VARAPI _PM_savedDS = 0; +#ifdef DOS4GW +static ulong PDB = 0,*pPDB = NULL; +#endif +#ifndef REALMODE +static char VXD_name[] = PMHELP_NAME; +static char VXD_module[] = PMHELP_MODULE; +static char VXD_DDBName[] = PMHELP_DDBNAME; +static uint VXD_version = -1; +static uint VXD_loadOff = 0; +static uint VXD_loadSel = 0; +uint _VARAPI _PM_VXD_off = 0; +uint _VARAPI _PM_VXD_sel = 0; +int _VARAPI _PM_haveCauseWay = -1; + +/* Memory mapping cache */ + +#define MAX_MEMORY_MAPPINGS 100 +typedef struct { + ulong physical; + ulong linear; + ulong limit; + } mmapping; +static mmapping maps[MAX_MEMORY_MAPPINGS] = {0}; +static int numMaps = 0; + +/* Page sized block cache */ + +#define PAGES_PER_BLOCK 100 +#define FREELIST_NEXT(p) (*(void**)(p)) +typedef struct pageblock { + struct pageblock *next; + struct pageblock *prev; + void *freeListStart; + void *freeList; + void *freeListEnd; + int freeCount; + } pageblock; +static pageblock *pageBlocks = NULL; +#endif + +/* Start of all page tables in CauseWay */ + +#define CW_PAGE_TABLE_START (1024UL*4096UL*1023UL) + +/*----------------------------- Implementation ----------------------------*/ + +/* External assembler functions */ + +ulong _ASMAPI _PM_getPDB(void); +int _ASMAPI _PM_pagingEnabled(void); +void _ASMAPI _PM_VxDCall(VXD_regs *regs,uint off,uint sel); + +#ifndef REALMODE +/**************************************************************************** +REMARKS: +Exit function to unload the dynamically loaded VxD +****************************************************************************/ +static void UnloadVxD(void) +{ + PMSREGS sregs; + VXD_regs r; + + r.eax = 2; + r.ebx = 0; + r.edx = (uint)VXD_module; + PM_segread(&sregs); +#ifdef __16BIT__ + r.ds = ((ulong)VXD_module) >> 16; +#else + r.ds = sregs.ds; +#endif + r.es = sregs.es; + _PM_VxDCall(&r,VXD_loadOff,VXD_loadSel); +} + +/**************************************************************************** +REMARKS: +External function to call the PMHELP helper VxD. +****************************************************************************/ +void PMAPI PM_VxDCall( + VXD_regs *regs) +{ + if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) + _PM_VxDCall(regs,_PM_VXD_off,_PM_VXD_sel); +} + +/**************************************************************************** +RETURNS: +BCD coded version number of the VxD, or 0 if not loaded (ie: 0x202 - 2.2) + +REMARKS: +This function gets the version number for the VxD that we have connected to. +****************************************************************************/ +uint PMAPI PMHELP_getVersion(void) +{ + VXD_regs r; + + /* Call the helper VxD to determine the version number */ + if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) { + memset(&r,0,sizeof(r)); + r.eax = API_NUM(PMHELP_GETVER); + _PM_VxDCall(&r,_PM_VXD_off,_PM_VXD_sel); + return VXD_version = (uint)r.eax; + } + return VXD_version = 0; +} + +/**************************************************************************** +DESCRIPTION: +Connects to the helper VxD and returns the version number + +RETURNS: +True if the VxD was found and loaded, false otherwise. + +REMARKS: +This function connects to the VxD (loading it if it is dynamically loadable) +and returns the version number of the VxD. +****************************************************************************/ +static ibool PMHELP_connect(void) +{ + PMREGS regs; + PMSREGS sregs; + VXD_regs r; + + /* Bail early if we have alread connected */ + if (VXD_version != -1) + return VXD_version != 0; + + /* Get the static SDDHELP.VXD entry point if available */ + PM_segread(&sregs); + regs.x.ax = 0x1684; + regs.x.bx = SDDHELP_DeviceID; + regs.x.di = 0; + sregs.es = 0; + PM_int386x(0x2F,®s,®s,&sregs); + _PM_VXD_sel = sregs.es; + _PM_VXD_off = regs.x.di; + if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) { + if (PMHELP_getVersion() >= PMHELP_VERSION) + return true; + } + + /* If we get here, then either SDDHELP.VXD is not loaded, or it is an + * earlier version. In this case try to dynamically load the PMHELP.VXD + * helper VxD instead. + */ + PM_segread(&sregs); + regs.x.ax = 0x1684; + regs.x.bx = VXDLDR_DeviceID; + regs.x.di = 0; + sregs.es = 0; + PM_int386x(0x2F,®s,®s,&sregs); + VXD_loadSel = sregs.es; + VXD_loadOff = regs.x.di; + if (VXD_loadSel == 0 && VXD_loadOff == 0) + return VXD_version = 0; + r.eax = 1; + r.ebx = 0; + r.edx = (uint)VXD_name; + PM_segread(&sregs); + r.ds = sregs.ds; + r.es = sregs.es; + _PM_VxDCall(&r,VXD_loadOff,VXD_loadSel); + if (r.eax != 0) + return VXD_version = 0; + + /* Get the dynamic VxD entry point so we can call it */ + atexit(UnloadVxD); + PM_segread(&sregs); + regs.x.ax = 0x1684; + regs.x.bx = 0; + regs.e.edi = (uint)VXD_DDBName; + PM_int386x(0x2F,®s,®s,&sregs); + _PM_VXD_sel = sregs.es; + _PM_VXD_off = regs.x.di; + if (_PM_VXD_sel == 0 && _PM_VXD_off == 0) + return VXD_version = 0; + if (PMHELP_getVersion() >= PMHELP_VERSION) + return true; + return VXD_version = 0; +} +#endif + +/**************************************************************************** +REMARKS: +Initialise the PM library. First we try to connect to a static SDDHELP.VXD +helper VxD, and check that it is a version we can use. If not we try to +dynamically load the PMHELP.VXD helper VxD +****************************************************************************/ +void PMAPI PM_init(void) +{ +#ifndef REALMODE + PMREGS regs; + + /* Check if we are running under CauseWay under real DOS */ + if (_PM_haveCauseWay == -1) { + /* Check if we are running under DPMI in which case we will not be + * able to use our special ring 0 CauseWay functions. + */ + _PM_haveCauseWay = false; + regs.x.ax = 0xFF00; + PM_int386(0x31,®s,®s); + if (regs.x.cflag || !(regs.e.edi & 8)) { + /* We are not under DPMI, so now check if CauseWay is active */ + regs.x.ax = 0xFFF9; + PM_int386(0x31,®s,®s); + if (!regs.x.cflag && regs.e.ecx == 0x43415553 && regs.e.edx == 0x45574159) + _PM_haveCauseWay = true; + } + + /* Now connect to PMHELP.VXD and initialise MTRR module */ + if (!PMHELP_connect()) + MTRR_init(); + } +#endif +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ +#ifndef REALMODE + VXD_regs regs; + + if (PMHELP_connect()) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_ENABLELFBCOMB); + regs.ebx = base; + regs.ecx = size; + regs.edx = type; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return regs.eax; + } + return MTRR_enableWriteCombine(base,size,type); +#else + return PM_MTRR_NOT_SUPPORTED; +#endif +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return true; } + +long PMAPI PM_getOSType(void) +{ return _OS_DOS; } + +int PMAPI PM_getModeType(void) +{ +#if defined(REALMODE) + return PM_realMode; +#elif defined(PM286) + return PM_286; +#elif defined(PM386) + return PM_386; +#endif +} + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + exit(1); +} + +static void ExitVBEBuf(void) +{ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out) +{ + PMSREGS sregs; + PM_segread(&sregs); + return PM_int386x(intno,in,out,&sregs); +} + +/* Routines to set and get the real mode interrupt vectors, by making + * direct real mode calls to DOS and bypassing the DOS extenders API. + * This is the safest way to handle this, as some servers try to be + * smart about changing real mode vectors. + */ + +void PMAPI _PM_getRMvect(int intno, long *realisr) +{ + RMREGS regs; + RMSREGS sregs; + + PM_saveDS(); + regs.h.ah = 0x35; + regs.h.al = intno; + PM_int86x(0x21, ®s, ®s, &sregs); + *realisr = ((long)sregs.es << 16) | regs.x.bx; +} + +void PMAPI _PM_setRMvect(int intno, long realisr) +{ + RMREGS regs; + RMSREGS sregs; + + PM_saveDS(); + regs.h.ah = 0x25; + regs.h.al = intno; + sregs.ds = (int)(realisr >> 16); + regs.x.dx = (int)(realisr & 0xFFFF); + PM_int86x(0x21, ®s, ®s, &sregs); +} + +void PMAPI _PM_addRealModeBlock(void *mem,uint tag) +{ + int i; + + for (i = 0; i < MAX_RM_BLOCKS; i++) { + if (rmBlocks[i].p == NULL) { + rmBlocks[i].p = mem; + rmBlocks[i].tag = tag; + return; + } + } + PM_fatalError("To many real mode memory block allocations!"); +} + +uint PMAPI _PM_findRealModeBlock(void *mem) +{ + int i; + + for (i = 0; i < MAX_RM_BLOCKS; i++) { + if (rmBlocks[i].p == mem) + return rmBlocks[i].tag; + } + PM_fatalError("Could not find prior real mode memory block allocation!"); + return 0; +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return 'C'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return "c:\\"; } + +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + char *env; + + if ((env = getenv("NUCLEUS_PATH")) != NULL) + return env; + if ((env = getenv("WINBOOTDIR")) != NULL) { + /* Running in a Windows 9x DOS box or DOS mode */ + strcpy(path,env); + strcat(path,"\\system\\nucleus"); + return path; + } + if ((env = getenv("SystemRoot")) != NULL) { + /* Running in an NT/2K DOS box */ + strcpy(path,env); + strcat(path,"\\system32\\nucleus"); + return path; + } + return "c:\\nucleus"; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ return "DOS"; } + +const char * PMAPI PM_getMachineName(void) +{ return "DOS"; } + +int PMAPI PM_kbhit(void) +{ + return kbhit(); +} + +int PMAPI PM_getch(void) +{ + return getch(); +} + +PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen) +{ + /* Not used for DOS */ + (void)hwndUser; + (void)device; + (void)xRes; + (void)yRes; + (void)bpp; + (void)fullScreen; + return 0; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + return sizeof(DOS_stateBuf); +} + +void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole) +{ + RMREGS regs; + DOS_stateBuf *sb = stateBuf; + + /* Save the old video mode state */ + regs.h.ah = 0x0F; + PM_int86(0x10,®s,®s); + sb->oldMode = regs.h.al & 0x7F; + sb->old50Lines = false; + if (sb->oldMode == 0x3) { + regs.x.ax = 0x1130; + regs.x.bx = 0; + regs.x.dx = 0; + PM_int86(0x10,®s,®s); + sb->old50Lines = (regs.h.dl == 42 || regs.h.dl == 49); + } + (void)hwndConsole; +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* Not used for DOS */ + (void)saveState; +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) +{ + RMREGS regs; + const DOS_stateBuf *sb = stateBuf; + + /* Retore 50 line mode if set */ + if (sb->old50Lines) { + regs.x.ax = 0x1112; + regs.x.bx = 0; + PM_int86(0x10,®s,®s); + } + (void)hwndConsole; +} + +void PMAPI PM_closeConsole(PM_HWND hwndConsole) +{ + /* Not used for DOS */ + (void)hwndConsole; +} + +void PMAPI PM_setOSCursorLocation(int x,int y) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x50,x); + PM_setByte(_biosPtr+0x51,y); +} + +void PMAPI PM_setOSScreenWidth(int width,int height) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setWord(_biosPtr+0x4A,width); + PM_setWord(_biosPtr+0x4C,width*2); + PM_setByte(_biosPtr+0x84,height-1); + if (height > 25) { + PM_setWord(_biosPtr+0x60,0x0607); + PM_setByte(_biosPtr+0x85,0x08); + } + else { + PM_setWord(_biosPtr+0x60,0x0D0E); + PM_setByte(_biosPtr+0x85,0x016); + } +} + +void * PMAPI PM_mallocShared(long size) +{ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + PM_free(ptr); +} + +#define GetRMVect(intno,isr) *(isr) = ((ulong*)rmZeroPtr)[intno] +#define SetRMVect(intno,isr) ((ulong*)rmZeroPtr)[intno] = (isr) + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + static int firstTime = true; + static uchar *rmZeroPtr; + long Current10,Current6D,Current42; + RMREGS regs; + RMSREGS sregs; + + /* Create a zero memory mapping for us to use */ + if (firstTime) { + rmZeroPtr = PM_mapPhysicalAddr(0,0x7FFF,true); + firstTime = false; + } + + /* Remap the secondary BIOS to 0xC0000 physical */ + if (BIOSPhysAddr != 0xC0000L || BIOSLen > 32768) { + /* DOS cannot virtually remap the BIOS, so we can only work if all + * the secondary controllers are identical, and we then use the + * BIOS on the first controller for all the remaining controllers. + * + * For OS'es that do virtual memory, and remapping of 0xC0000 + * physical (perhaps a copy on write mapping) should be all that + * is needed. + */ + return false; + } + + /* Save current handlers of int 10h and 6Dh */ + GetRMVect(0x10,&Current10); + GetRMVect(0x6D,&Current6D); + + /* POST the secondary BIOS */ + GetRMVect(0x42,&Current42); + SetRMVect(0x10,Current42); /* Restore int 10h to STD-BIOS */ + regs.x.ax = axVal; + PM_callRealMode(0xC000,0x0003,®s,&sregs); + + /* Restore current handlers */ + SetRMVect(0x10,Current10); + SetRMVect(0x6D,Current6D); + + /* Second the primary BIOS mappin 1:1 for 0xC0000 physical */ + if (BIOSPhysAddr != 0xC0000L) { + /* DOS does not support this */ + (void)mappedBIOS; + } + return true; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + ulong microseconds = milliseconds * 1000L; + LZTimerObject tm; + + LZTimerOnExt(&tm); + while (LZTimerLapExt(&tm) < microseconds) + ; + LZTimerOffExt(&tm); +} + +int PMAPI PM_getCOMPort(int port) +{ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + (void)hModule; +} + +int PMAPI PM_setIOPL( + int level) +{ + return level; +} + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + struct find_t *blk) +{ + ulong dwSize = findData->dwSize; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + if (blk->attrib & _A_RDONLY) + findData->attrib |= PM_FILE_READONLY; + if (blk->attrib & _A_SUBDIR) + findData->attrib |= PM_FILE_DIRECTORY; + if (blk->attrib & _A_ARCH) + findData->attrib |= PM_FILE_ARCHIVE; + if (blk->attrib & _A_HIDDEN) + findData->attrib |= PM_FILE_HIDDEN; + if (blk->attrib & _A_SYSTEM) + findData->attrib |= PM_FILE_SYSTEM; + findData->sizeLo = blk->size; + strncpy(findData->name,blk->name,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +#define FIND_MASK (_A_RDONLY | _A_ARCH | _A_SUBDIR | _A_HIDDEN | _A_SYSTEM) + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void * PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + struct find_t *blk; + + if ((blk = PM_malloc(sizeof(*blk))) == NULL) + return PM_FILE_INVALID; + if (_dos_findfirst((char*)filename,FIND_MASK,blk) == 0) { + convertFindData(findData,blk); + return blk; + } + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + struct find_t *blk = handle; + + if (_dos_findnext(blk) == 0) { + convertFindData(findData,blk); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + PM_free(handle); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + RMREGS regs; + regs.h.dl = (uchar)(drive - 'A' + 1); + regs.h.ah = 0x36; /* Get disk information service */ + PM_int86(0x21,®s,®s); + return regs.x.ax != 0xFFFF; /* AX = 0xFFFF if disk is invalid */ +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + uint oldDrive,maxDrives; + _dos_getdrive(&oldDrive); + _dos_setdrive(drive,&maxDrives); + getcwd(dir,len); + _dos_setdrive(oldDrive,&maxDrives); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ +#if defined(TNT) && defined(_MSC_VER) + DWORD attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= FILE_ATTRIBUTE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= FILE_ATTRIBUTE_ARCHIVE; + if (attrib & PM_FILE_HIDDEN) + attr |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= FILE_ATTRIBUTE_SYSTEM; + SetFileAttributes((LPSTR)filename, attr); +#else + uint attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= _A_RDONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= _A_ARCH; + if (attrib & PM_FILE_HIDDEN) + attr |= _A_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= _A_SYSTEM; + _dos_setfileattr(filename,attr); +#endif +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ +#ifdef __GNUC__ + return mkdir(filename,S_IRUSR) == 0; +#else + return mkdir(filename) == 0; +#endif +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return rmdir(filename) == 0; +} + +/*-------------------------------------------------------------------------*/ +/* Generic DPMI routines common to 16/32 bit code */ +/*-------------------------------------------------------------------------*/ + +#ifndef REALMODE +ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit) +{ + PMREGS r; + int i; + ulong baseAddr,baseOfs,roundedLimit; + + /* We can't map memory below 1Mb, but the linear address are already + * mapped 1:1 for this memory anyway so we just return the base address. + */ + if (physAddr < 0x100000L) + return physAddr; + + /* Search table of existing mappings to see if we have already mapped + * a region of memory that will serve this purpose. We do this because + * DPMI 0.9 does not allow us to free physical memory mappings, and if + * the mappings get re-used in the program we want to avoid allocating + * more mappings than necessary. + */ + for (i = 0; i < numMaps; i++) { + if (maps[i].physical == physAddr && maps[i].limit == limit) + return maps[i].linear; + } + + /* Find a free slot in our physical memory mapping table */ + for (i = 0; i < numMaps; i++) { + if (maps[i].limit == 0) + break; + } + if (i == numMaps) { + i = numMaps++; + if (i == MAX_MEMORY_MAPPINGS) + return NULL; + } + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to DPMI as some extenders + * will fail the calls unless this is the case. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = physAddr & 4095; + baseAddr = physAddr & ~4095; + roundedLimit = ((limit+baseOfs+1+4095) & ~4095)-1; + r.x.ax = 0x800; + r.x.bx = baseAddr >> 16; + r.x.cx = baseAddr & 0xFFFF; + r.x.si = roundedLimit >> 16; + r.x.di = roundedLimit & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0xFFFFFFFFUL; + maps[i].physical = physAddr; + maps[i].limit = limit; + maps[i].linear = ((ulong)r.x.bx << 16) + r.x.cx + baseOfs; + return maps[i].linear; +} + +int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr) +{ + PMREGS r; + + r.x.ax = 7; /* DPMI set selector base address */ + r.x.bx = sel; + r.x.cx = linAddr >> 16; + r.x.dx = linAddr & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0; + return 1; +} + +ulong PMAPI DPMI_getSelectorBase(ushort sel) +{ + PMREGS r; + + r.x.ax = 6; /* DPMI get selector base address */ + r.x.bx = sel; + PM_int386(0x31, &r, &r); + return ((ulong)r.x.cx << 16) + r.x.dx; +} + +int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit) +{ + PMREGS r; + + r.x.ax = 8; /* DPMI set selector limit */ + r.x.bx = sel; + r.x.cx = limit >> 16; + r.x.dx = limit & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0; + return 1; +} + +uint PMAPI DPMI_createSelector(ulong base,ulong limit) +{ + uint sel; + PMREGS r; + + /* Allocate 1 descriptor */ + r.x.ax = 0; + r.x.cx = 1; + PM_int386(0x31, &r, &r); + if (r.x.cflag) return 0; + sel = r.x.ax; + + /* Set the descriptor access rights (for a 32 bit page granular + * segment). + */ + if (limit >= 0x10000L) { + r.x.ax = 9; + r.x.bx = sel; + r.x.cx = 0x40F3; + PM_int386(0x31, &r, &r); + } + + /* Map physical memory and create selector */ + if ((base = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFFUL) + return 0; + if (!DPMI_setSelectorBase(sel,base)) + return 0; + if (!DPMI_setSelectorLimit(sel,limit)) + return 0; + return sel; +} + +void PMAPI DPMI_freeSelector(uint sel) +{ + PMREGS r; + + r.x.ax = 1; + r.x.bx = sel; + PM_int386(0x31, &r, &r); +} + +int PMAPI DPMI_lockLinearPages(ulong linear,ulong len) +{ + PMREGS r; + + r.x.ax = 0x600; /* DPMI Lock Linear Region */ + r.x.bx = (linear >> 16); /* Linear address in BX:CX */ + r.x.cx = (linear & 0xFFFF); + r.x.si = (len >> 16); /* Length in SI:DI */ + r.x.di = (len & 0xFFFF); + PM_int386(0x31, &r, &r); + return (!r.x.cflag); +} + +int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len) +{ + PMREGS r; + + r.x.ax = 0x601; /* DPMI Unlock Linear Region */ + r.x.bx = (linear >> 16); /* Linear address in BX:CX */ + r.x.cx = (linear & 0xFFFF); + r.x.si = (len >> 16); /* Length in SI:DI */ + r.x.di = (len & 0xFFFF); + PM_int386(0x31, &r, &r); + return (!r.x.cflag); +} + +/**************************************************************************** +REMARKS: +Adjust the page table caching bits directly. Requires ring 0 access and +only works with DOS4GW and compatible extenders (CauseWay also works since +it has direct support for the ring 0 instructions we need from ring 3). Will +not work in a DOS box, but we call into the ring 0 helper VxD so we should +never get here in a DOS box anyway (assuming the VxD is present). If we +do get here and we are in windows, this code will be skipped. +****************************************************************************/ +static void PM_adjustPageTables( + ulong linear, + ulong limit, + ibool isCached) +{ +#ifdef DOS4GW + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong andMask,orMask,pageTable,*pPageTable; + + andMask = ~0x18; + orMask = (isCached) ? 0x00 : 0x18; + if (_PM_pagingEnabled() == 1 && (PDB = _PM_getPDB()) != 0) { + if (_PM_haveCauseWay) { + /* CauseWay is a little different in the page table handling. + * The code that we use for DOS4G/W does not appear to work + * with CauseWay correctly as it does not appear to allow us + * to map the page tables directly. Instead we can directly + * access the page table entries in extended memory where + * CauseWay always locates them (starting at 1024*4096*1023) + */ + startPage = (linear >> 12); + endPage = ((linear+limit) >> 12); + pPageTable = (ulong*)CW_PAGE_TABLE_START; + for (iPage = startPage; iPage <= endPage; iPage++) + pPageTable[iPage] = (pPageTable[iPage] & andMask) | orMask; + } + else { + pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF); + if (pPDB) { + startPDB = (linear >> 22) & 0x3FF; + startPage = (linear >> 12) & 0x3FF; + endPDB = ((linear+limit) >> 22) & 0x3FF; + endPage = ((linear+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + pageTable = pPDB[iPDB] & ~0xFFF; + pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF); + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) + pPageTable[iPage] = (pPageTable[iPage] & andMask) | orMask; + } + } + } + PM_flushTLB(); + } +#endif +} + +void * PMAPI DPMI_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + PMSREGS sregs; + ulong linAddr; + ulong DSBaseAddr; + + /* Get the base address for the default DS selector */ + PM_segread(&sregs); + DSBaseAddr = DPMI_getSelectorBase(sregs.ds); + if ((base < 0x100000) && (DSBaseAddr == 0)) { + /* DS is zero based, so we can directly access the first 1Mb of + * system memory (like under DOS4GW). + */ + return (void*)base; + } + + /* Map the memory to a linear address using DPMI function 0x800 */ + if ((linAddr = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFF) { + if (base >= 0x100000) + return NULL; + /* If the linear address mapping fails but we are trying to + * map an area in the first 1Mb of system memory, then we must + * be running under a Windows or OS/2 DOS box. Under these + * environments we can use the segment wrap around as a fallback + * measure, as this does work properly. + */ + linAddr = base; + } + + /* Now expand the default DS selector to 4Gb so we can access it */ + if (!DPMI_setSelectorLimit(sregs.ds,0xFFFFFFFFUL)) + return NULL; + + /* Finally enable caching for the page tables that we just mapped in, + * since DOS4GW and PMODE/W create the page table entries without + * caching enabled which hurts the performance of the linear framebuffer + * as it disables write combining on Pentium Pro and above processors. + * + * For those processors cache disabling is better handled through the + * MTRR registers anyway (we can write combine a region but disable + * caching) so that MMIO register regions do not screw up. + */ + if (DSBaseAddr == 0) + PM_adjustPageTables(linAddr,limit,isCached); + + /* Now return the base address of the memory into the default DS */ + return (void*)(linAddr - DSBaseAddr); +} + +#if defined(PM386) + +/* Some DOS extender implementations do not directly support calling a + * real mode procedure from protected mode. However we can simulate what + * we need temporarily hooking the INT 6Ah vector with a small real mode + * stub that will call our real mode code for us. + */ + +static uchar int6AHandler[] = { + 0x00,0x00,0x00,0x00, /* __PMODE_callReal variable */ + 0xFB, /* sti */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PMODE_callReal] */ + 0xCF, /* iretf */ + }; +static uchar *crPtr = NULL; /* Pointer to of int 6A handler */ +static uint crRSeg,crROff; /* Real mode seg:offset of handler */ + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + uchar *p; + uint oldSeg,oldOff; + + if (!crPtr) { + /* Allocate and copy the memory block only once */ + crPtr = PM_allocRealSeg(sizeof(int6AHandler), &crRSeg, &crROff); + memcpy(crPtr,int6AHandler,sizeof(int6AHandler)); + } + PM_setWord(crPtr,off); /* Plug in address to call */ + PM_setWord(crPtr+2,seg); + p = PM_mapRealPointer(0,0x6A * 4); + oldOff = PM_getWord(p); /* Save old handler address */ + oldSeg = PM_getWord(p+2); + PM_setWord(p,crROff+4); /* Hook 6A handler */ + PM_setWord(p+2,crRSeg); + PM_int86x(0x6A, in, in, sregs); /* Call real mode code */ + PM_setWord(p,oldOff); /* Restore old handler */ + PM_setWord(p+2,oldSeg); +} + +#endif /* PM386 */ + +#endif /* !REALMODE */ + +/**************************************************************************** +REMARKS: +Allocates a block of locked, physically contiguous memory. The memory +may be required to be below the 16Meg boundary. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16Meg) +{ + uchar *p,*roundedP; + uint r_seg,r_off; + uint roundedSize = (size + 4 + 0xFFF) & ~0xFFF; + PM_lockHandle lh; /* Unused in DOS */ +#ifndef REALMODE + VXD_regs regs; + + /* If we have connected to our helper VxD in a Windows DOS box, use the + * helper VxD services to allocate the memory that we need. + */ + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_ALLOCLOCKED); + regs.ebx = size; + regs.ecx = (ulong)physAddr; + regs.edx = contiguous | (below16Meg << 8); + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + + /* If the memory is not contiguous, we simply need to allocate it + * using regular memory allocation services, and lock it down + * in memory. + * + * For contiguous memory blocks, the only way to guarantee contiguous physical + * memory addresses under DOS is to allocate the memory below the + * 1Meg boundary as real mode memory. + * + * Note that we must page align the memory block, and we also must + * keep track of the non-aligned pointer so we can properly free + * it later. Hence we actually allocate 4 bytes more than the + * size rounded up to the next 4K boundary. + */ + if (!contiguous) + p = PM_malloc(roundedSize); + else +#endif + p = PM_allocRealSeg(roundedSize,&r_seg,&r_off); + if (p == NULL) + return NULL; + roundedP = (void*)(((ulong)p + 0xFFF) & ~0xFFF); + *((ulong*)(roundedP + size)) = (ulong)p; + PM_lockDataPages(roundedP,size,&lh); + if ((*physAddr = PM_getPhysicalAddr(roundedP)) == 0xFFFFFFFF) { + PM_freeLockedMem(roundedP,size,contiguous); + return NULL; + } + + /* Disable caching for the memory since it is probably a DMA buffer */ +#ifndef REALMODE + PM_adjustPageTables((ulong)roundedP,size-1,false); +#endif + return roundedP; +} + +/**************************************************************************** +REMARKS: +Free a block of locked memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) +{ +#ifndef REALMODE + VXD_regs regs; + PM_lockHandle lh; /* Unused in DOS */ + + if (!p) + return; + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_FREELOCKED); + regs.ebx = (ulong)p; + regs.ecx = size; + regs.edx = contiguous; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return; + } + PM_unlockDataPages(p,size,&lh); + if (!contiguous) + free(*((void**)((uchar*)p + size))); + else +#endif + PM_freeRealSeg(*((void**)((char*)p + size))); +} + +#ifndef REALMODE +/**************************************************************************** +REMARKS: +Allocates a new block of pages for the page block manager. +****************************************************************************/ +static pageblock *PM_addNewPageBlock(void) +{ + int i,size; + pageblock *newBlock; + char *p,*next; + + /* Allocate memory for the new page block, and add to head of list */ + size = PAGES_PER_BLOCK * PM_PAGE_SIZE + (PM_PAGE_SIZE-1) + sizeof(pageblock); + if ((newBlock = PM_malloc(size)) == NULL) + return NULL; + newBlock->prev = NULL; + newBlock->next = pageBlocks; + if (pageBlocks) + pageBlocks->prev = newBlock; + pageBlocks = newBlock; + + /* Initialise the page aligned free list for the page block */ + newBlock->freeCount = PAGES_PER_BLOCK; + newBlock->freeList = p = (char*)(((ulong)(newBlock + 1) + (PM_PAGE_SIZE-1)) & ~(PM_PAGE_SIZE-1)); + newBlock->freeListStart = newBlock->freeList; + newBlock->freeListEnd = p + (PAGES_PER_BLOCK-1) * PM_PAGE_SIZE; + for (i = 0; i < PAGES_PER_BLOCK; i++,p = next) + FREELIST_NEXT(p) = next = p + PM_PAGE_SIZE; + FREELIST_NEXT(p - PM_PAGE_SIZE) = NULL; + return newBlock; +} +#endif + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ +#ifndef REALMODE + VXD_regs regs; + pageblock *block; + void *p; + PM_lockHandle lh; /* Unused in DOS */ + + /* Call the helper VxD for this service if we are running in a DOS box */ + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_ALLOCPAGE); + regs.ebx = locked; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + + /* Scan the block list looking for any free blocks. Allocate a new + * page block if no free blocks are found. + */ + for (block = pageBlocks; block != NULL; block = block->next) { + if (block->freeCount) + break; + } + if (block == NULL && (block = PM_addNewPageBlock()) == NULL) + return NULL; + block->freeCount--; + p = block->freeList; + block->freeList = FREELIST_NEXT(p); + if (locked) + PM_lockDataPages(p,PM_PAGE_SIZE,&lh); + return p; +#else + return NULL; +#endif +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ +#ifndef REALMODE + VXD_regs regs; + pageblock *block; + + /* Call the helper VxD for this service if we are running in a DOS box */ + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_FREEPAGE); + regs.ebx = (ulong)p; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return; + } + + /* First find the page block that this page belongs to */ + for (block = pageBlocks; block != NULL; block = block->next) { + if (p >= block->freeListStart && p <= block->freeListEnd) + break; + } + CHECK(block != NULL); + + /* Now free the block by adding it to the free list */ + FREELIST_NEXT(p) = block->freeList; + block->freeList = p; + if (++block->freeCount == PAGES_PER_BLOCK) { + /* If all pages in the page block are now free, free the entire + * page block itself. + */ + if (block == pageBlocks) { + /* Delete from head */ + pageBlocks = block->next; + if (block->next) + block->next->prev = NULL; + } + else { + /* Delete from middle of list */ + CHECK(block->prev != NULL); + block->prev->next = block->next; + if (block->next) + block->next->prev = block->prev; + } + PM_free(block); + } +#else + (void)p; +#endif +} + +/*-------------------------------------------------------------------------*/ +/* DOS Real Mode support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef REALMODE + +#ifndef MK_FP +#define MK_FP(s,o) ( (void far *)( ((ulong)(s) << 16) + \ + (ulong)(o) )) +#endif + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ return MK_FP(r_seg,r_off); } + +void * PMAPI PM_getBIOSPointer(void) +{ + return MK_FP(0x40,0); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + return MK_FP(0xA000,0); +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + uint sel = base >> 4; + uint off = base & 0xF; + limit = limit; + return MK_FP(sel,off); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ ptr = ptr; } + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + return ((((ulong)p >> 16) << 4) + (ushort)p); +} + +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) +{ return false; } + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + /* Call malloc() to allocate the memory for us */ + void *p = PM_malloc(size); + *r_seg = FP_SEG(p); + *r_off = FP_OFF(p); + return p; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + if (mem) PM_free(mem); +} + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + return PM_int386(intno,in,out); +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + return PM_int386x(intno,in,out,sregs); +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS regs; + + regs.h.ah = 0x48; + regs.x.bx = 0xFFFF; + PM_int86(0x21,®s,®s); + *physical = *total = regs.x.bx * 16UL; +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Phar Lap TNT DOS Extender support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef TNT + +#include +#include +#include + +static uchar *zeroPtr = NULL; + +void * PMAPI PM_getBIOSPointer(void) +{ + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + 0x400); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + static void *bankPtr; + if (!bankPtr) + bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + return bankPtr; +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + CONFIG_INF config; + ULONG offset; + int err; + ulong baseAddr,baseOfs,newLimit; + VXD_regs regs; + + /* If we have connected to our helper VxD in a Windows DOS box, use + * the helper VxD services to map memory instead of the DPMI services. + * We do this because the helper VxD can properly disable caching + * where necessary, which we can only do directly here if we are + * running at ring 0 (ie: under real DOS). + */ + if (VXD_version == -1) + PM_init(); + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_MAPPHYS); + regs.ebx = base; + regs.ecx = limit; + regs.edx = isCached; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to TNT. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = base & 4095; + baseAddr = base & ~4095; + newLimit = ((limit+baseOfs+1+4095) & ~4095)-1; + _dx_config_inf(&config, (UCHAR*)&config); + err = _dx_map_phys(config.c_ds_sel,baseAddr,(newLimit + 4095) / 4096,&offset); + if (err == 130) { + /* If the TNT function failed, we are running in a DPMI environment + * and this function does not work. However we know how to handle + * DPMI properly, so we use our generic DPMI functions to do + * what the TNT runtime libraries can't. + */ + return DPMI_mapPhysicalAddr(base,limit,isCached); + } + if (err == 0) + return (void*)(offset + baseOfs); + return NULL; +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ return 0xFFFFFFFFUL; } + +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) +{ return false; } + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF); + return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + USHORT addr,t; + void *p; + + if (_dx_real_alloc((size + 0xF) >> 4,&addr,&t) != 0) + return 0; + *r_seg = addr; /* Real mode segment address */ + *r_off = 0; /* Real mode segment offset */ + p = PM_mapRealPointer(*r_seg,*r_off); + _PM_addRealModeBlock(p,addr); + return p; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + if (mem) _dx_real_free(_PM_findRealModeBlock(mem)); +} + +#define INDPMI(reg) rmregs.reg = regs->reg +#define OUTDPMI(reg) regs->reg = rmregs.reg + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + SWI_REGS rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + INDPMI(eax); INDPMI(ebx); INDPMI(ecx); INDPMI(edx); INDPMI(esi); INDPMI(edi); + + _dx_real_int(intno,&rmregs); + + OUTDPMI(eax); OUTDPMI(ebx); OUTDPMI(ecx); OUTDPMI(edx); OUTDPMI(esi); OUTDPMI(edi); + regs->flags = rmregs.flags; +} + +#define IN(reg) rmregs.reg = in->e.reg +#define OUT(reg) out->e.reg = rmregs.reg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + SWI_REGS rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + + _dx_real_int(intno,&rmregs); + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + SWI_REGS rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + + _dx_real_int(intno,&rmregs); + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->cs = rmregs.cs; + sregs->ss = rmregs.ss; + sregs->ds = rmregs.ds; + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS r; + uint data[25]; + + r.x.ax = 0x2520; /* Get free memory info */ + r.x.bx = 0; + r.e.edx = (uint)data; + PM_int386(0x21, &r, &r); + *physical = data[21] * 4096; + *total = data[23] * 4096; +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Symantec C++ DOSX and FlashTek X-32/X-32VM support */ +/*-------------------------------------------------------------------------*/ + +#if defined(DOSX) || defined(X32VM) + +#ifdef X32VM +#include + +#define _x386_mk_protected_ptr(p) _x32_mk_protected_ptr((void*)p) +#define _x386_free_protected_ptr(p) _x32_free_protected_ptr(p) +#define _x386_zero_base_ptr _x32_zero_base_ptr +#else +extern void *_x386_zero_base_ptr; +#endif + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + return (void*)((ulong)_x386_zero_base_ptr + MK_PHYS(r_seg,r_off)); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + PMREGS r; + + r.h.ah = 0x48; /* DOS function 48h - allocate mem */ + r.x.bx = (size + 0xF) >> 4; /* Number of paragraphs to allocate */ + PM_int386(0x21, &r, &r); /* Call DOS extender */ + if (r.x.cflag) + return 0; /* Could not allocate the memory */ + *r_seg = r.e.eax; + *r_off = 0; + return PM_mapRealPointer(*r_seg,*r_off); +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + /* Cannot de-allocate this memory */ + mem = mem; +} + +#pragma pack(1) + +typedef struct { + ushort intno; + ushort ds; + ushort es; + ushort fs; + ushort gs; + ulong eax; + ulong edx; + } _RMREGS; + +#pragma pack() + +#define IN(reg) regs.e.reg = in->e.reg +#define OUT(reg) out->e.reg = regs.e.reg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + _RMREGS rmregs; + PMREGS regs; + PMSREGS pmsregs; + + rmregs.intno = intno; + rmregs.eax = in->e.eax; + rmregs.edx = in->e.edx; + IN(ebx); IN(ecx); IN(esi); IN(edi); + regs.x.ax = 0x2511; + regs.e.edx = (uint)(&rmregs); + PM_segread(&pmsregs); + PM_int386x(0x21,®s,®s,&pmsregs); + + OUT(eax); OUT(ebx); OUT(ecx); OUT(esi); OUT(edi); + out->x.dx = rmregs.edx; + out->x.cflag = regs.x.cflag; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, RMSREGS *sregs) +{ + _RMREGS rmregs; + PMREGS regs; + PMSREGS pmsregs; + + rmregs.intno = intno; + rmregs.eax = in->e.eax; + rmregs.edx = in->e.edx; + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + IN(ebx); IN(ecx); IN(esi); IN(edi); + regs.x.ax = 0x2511; + regs.e.edx = (uint)(&rmregs); + PM_segread(&pmsregs); + PM_int386x(0x21,®s,®s,&pmsregs); + + OUT(eax); OUT(ebx); OUT(ecx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->ds = rmregs.ds; + out->x.dx = rmregs.edx; + out->x.cflag = regs.x.cflag; + return out->x.ax; +} + +void * PMAPI PM_getBIOSPointer(void) +{ + return (void*)((ulong)_x386_zero_base_ptr + 0x400); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + return (void*)((ulong)_x386_zero_base_ptr + 0xA0000); +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + VXD_regs regs; + + /* If we have connected to our helper VxD in a Windows DOS box, use + * the helper VxD services to map memory instead of the DPMI services. + * We do this because the helper VxD can properly disable caching + * where necessary, which we can only do directly here if we are + * running at ring 0 (ie: under real DOS). + */ + if (VXD_version == -1) + PM_init(); + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_MAPPHYS); + regs.ebx = base; + regs.ecx = limit; + regs.edx = isCached; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + + if (base > 0x100000) + return _x386_map_physical_address((void*)base,limit); + return (void*)((ulong)_x386_zero_base_ptr + base); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* Mapping cannot be freed */ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ return 0xFFFFFFFFUL; } + +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) +{ return false; } + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +ulong _cdecl _X32_getPhysMem(void); + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS regs; + + /* Get total memory available, including virtual memory */ + regs.x.ax = 0x350B; + PM_int386(0x21,®s,®s); + *total = regs.e.eax; + + /* Get physical memory available */ + *physical = _X32_getPhysMem(); + if (*physical > *total) + *physical = *total; +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Borland's DPMI32, Watcom DOS4GW and DJGPP DPMI support routines */ +/*-------------------------------------------------------------------------*/ + +#if defined(DPMI32) || defined(DOS4GW) || defined(DJGPP) + +void * PMAPI PM_getBIOSPointer(void) +{ + return PM_mapPhysicalAddr(0x400,0xFFFF,true); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + VXD_regs regs; + +#ifdef DJGPP + /* Enable near pointers for DJGPP V2 */ + __djgpp_nearptr_enable(); +#endif + /* If we have connected to our helper VxD in a Windows DOS box, use + * the helper VxD services to map memory instead of the DPMI services. + * We do this because the helper VxD can properly disable caching + * where necessary, which we can only do directly here if we are + * running at ring 0 (ie: under real DOS). + */ + if (VXD_version == -1) + PM_init(); + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_MAPPHYS); + regs.ebx = base; + regs.ecx = limit; + regs.edx = isCached; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + return DPMI_mapPhysicalAddr(base,limit,isCached); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* Mapping cannot be freed */ + (void)ptr; + (void)limit; +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + ulong physAddr; + if (!PM_getPhysicalAddrRange(p,1,&physAddr)) + return 0xFFFFFFFF; + return physAddr | ((ulong)p & 0xFFF); +} + +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + VXD_regs regs; + ulong pte; + PMSREGS sregs; + ulong DSBaseAddr; + + /* If we have connected to our helper VxD in a Windows DOS box, use the + * helper VxD services to find the physical address of an address. + */ + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_GETPHYSICALADDRRANGE); + regs.ebx = (ulong)p; + regs.ecx = (ulong)length; + regs.edx = (ulong)physAddress; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return regs.eax; + } + + /* Find base address for default DS selector */ + PM_segread(&sregs); + DSBaseAddr = DPMI_getSelectorBase(sregs.ds); + + /* Otherwise directly access the page tables to determine the + * physical memory address. Note that we touch the memory before + * calling, otherwise the memory may not be paged in correctly. + */ + pte = *((ulong*)p); +#ifdef DOS4GW + if (_PM_pagingEnabled() == 0) { + int count; + ulong linAddr = (ulong)p; + + /* When paging is disabled physical=linear */ + for (count = (length+0xFFF) >> 12; count > 0; count--) { + *physAddress++ = linAddr; + linAddr += 4096; + } + return true; + } + else if ((PDB = _PM_getPDB()) != 0 && DSBaseAddr == 0) { + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPageTable,linAddr = (ulong)p; + ulong limit = length-1; + + pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF); + if (pPDB) { + startPDB = (linAddr >> 22) & 0x3FFL; + startPage = (linAddr >> 12) & 0x3FFL; + endPDB = ((linAddr+limit) >> 22) & 0x3FFL; + endPage = ((linAddr+limit) >> 12) & 0x3FFL; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + pageTable = pPDB[iPDB] & ~0xFFFL; + pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF); + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FFL; + for (iPage = start; iPage <= end; iPage++) + *physAddress++ = (pPageTable[iPage] & ~0xFFF); + } + return true; + } + } +#endif + return false; +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ + (void)limit; + return (void*)base; +} + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + static uchar *zeroPtr = NULL; + + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + PMREGS r; + void *p; + + r.x.ax = 0x100; /* DPMI allocate DOS memory */ + r.x.bx = (size + 0xF) >> 4; /* number of paragraphs */ + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return NULL; /* DPMI call failed */ + *r_seg = r.x.ax; /* Real mode segment */ + *r_off = 0; + p = PM_mapRealPointer(*r_seg,*r_off); + _PM_addRealModeBlock(p,r.x.dx); + return p; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + PMREGS r; + + if (mem) { + r.x.ax = 0x101; /* DPMI free DOS memory */ + r.x.dx = _PM_findRealModeBlock(mem);/* DX := selector from 0x100 */ + PM_int386(0x31, &r, &r); + } +} + +static DPMI_handler_t DPMI_int10 = NULL; + +void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler) +{ + DPMI_int10 = handler; +} + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + PMREGS r; + PMSREGS sr; + + if (intno == 0x10 && DPMI_int10) { + if (DPMI_int10(regs)) + return; + } + PM_segread(&sr); + r.x.ax = 0x300; /* DPMI issue real interrupt */ + r.h.bl = intno; + r.h.bh = 0; + r.x.cx = 0; + sr.es = sr.ds; + r.e.edi = (uint)regs; + PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ +} + +#define IN(reg) rmregs.reg = in->e.reg +#define OUT(reg) out->e.reg = rmregs.reg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + + DPMI_int86(intno,&rmregs); /* DPMI issue real interrupt */ + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + + DPMI_int86(intno,&rmregs); /* DPMI issue real interrupt */ + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->cs = rmregs.cs; + sregs->ss = rmregs.ss; + sregs->ds = rmregs.ds; + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +#pragma pack(1) + +typedef struct { + uint LargestBlockAvail; + uint MaxUnlockedPage; + uint LargestLockablePage; + uint LinAddrSpace; + uint NumFreePagesAvail; + uint NumPhysicalPagesFree; + uint TotalPhysicalPages; + uint FreeLinAddrSpace; + uint SizeOfPageFile; + uint res[3]; + } MemInfo; + +#pragma pack() + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS r; + PMSREGS sr; + MemInfo memInfo; + + PM_segread(&sr); + r.x.ax = 0x500; /* DPMI get free memory info */ + sr.es = sr.ds; + r.e.edi = (uint)&memInfo; + PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ + *physical = memInfo.NumPhysicalPagesFree * 4096; + *total = memInfo.LargestBlockAvail; + if (*total < *physical) + *physical = *total; +} + +#endif + +#ifndef __16BIT__ + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + DPMI_regs regs; + memset(®s, 0, sizeof(regs)); + regs.eax = 0x4F05; + regs.ebx = 0x0000; + regs.edx = bank; + DPMI_int86(0x10,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + DPMI_regs regs; + memset(®s, 0, sizeof(regs)); + regs.eax = 0x4F05; + regs.ebx = 0x0000; + regs.edx = bank; + DPMI_int86(0x10,®s); + regs.eax = 0x4F05; + regs.ebx = 0x0001; + regs.edx = bank; + DPMI_int86(0x10,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + DPMI_regs regs; + memset(®s, 0, sizeof(regs)); + regs.eax = 0x4F07; + regs.ebx = waitVRT; + regs.ecx = x; + regs.edx = y; + DPMI_int86(0x10,®s); +} + +#endif + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + /* TODO: Implement this! */ + return 0; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c b/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c new file mode 100644 index 0000000..eecc2da --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c @@ -0,0 +1,1637 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 16/32 bit DOS +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include +#include +#include + +/*--------------------------- Global variables ----------------------------*/ + +#ifndef REALMODE +static int globalDataStart; +#endif + +PM_criticalHandler _VARAPI _PM_critHandler = NULL; +PM_breakHandler _VARAPI _PM_breakHandler = NULL; +PM_intHandler _VARAPI _PM_timerHandler = NULL; +PM_intHandler _VARAPI _PM_rtcHandler = NULL; +PM_intHandler _VARAPI _PM_keyHandler = NULL; +PM_key15Handler _VARAPI _PM_key15Handler = NULL; +PM_mouseHandler _VARAPI _PM_mouseHandler = NULL; +PM_intHandler _VARAPI _PM_int10Handler = NULL; +int _VARAPI _PM_mouseMask; + +uchar * _VARAPI _PM_ctrlCPtr; /* Location of Ctrl-C flag */ +uchar * _VARAPI _PM_ctrlBPtr; /* Location of Ctrl-Break flag */ +uchar * _VARAPI _PM_critPtr; /* Location of Critical error Bf*/ +PMFARPTR _VARAPI _PM_prevTimer = PMNULL; /* Previous timer handler */ +PMFARPTR _VARAPI _PM_prevRTC = PMNULL; /* Previous RTC handler */ +PMFARPTR _VARAPI _PM_prevKey = PMNULL; /* Previous key handler */ +PMFARPTR _VARAPI _PM_prevKey15 = PMNULL; /* Previous key15 handler */ +PMFARPTR _VARAPI _PM_prevBreak = PMNULL; /* Previous break handler */ +PMFARPTR _VARAPI _PM_prevCtrlC = PMNULL; /* Previous CtrlC handler */ +PMFARPTR _VARAPI _PM_prevCritical = PMNULL; /* Previous critical handler */ +long _VARAPI _PM_prevRealTimer; /* Previous real mode timer */ +long _VARAPI _PM_prevRealRTC; /* Previous real mode RTC */ +long _VARAPI _PM_prevRealKey; /* Previous real mode key */ +long _VARAPI _PM_prevRealKey15; /* Previous real mode key15 */ +long _VARAPI _PM_prevRealInt10; /* Previous real mode int 10h */ +static uchar _PM_oldCMOSRegA; /* CMOS register A contents */ +static uchar _PM_oldCMOSRegB; /* CMOS register B contents */ +static uchar _PM_oldRTCPIC2; /* Mask value for RTC IRQ8 */ + +/* Structure to maintain information about hardware interrupt handlers, + * include a copy of the hardware IRQ assembler thunk (one for each + * hooked interrupt handler). + */ + +typedef struct { + uchar IRQ; + uchar IRQVect; + uchar prevPIC; + uchar prevPIC2; + PMFARPTR prevHandler; + long prevRealhandler; + uchar thunk[1]; + /* IRQ assembler thunk follows ... */ + } _PM_IRQHandle; + +/*----------------------------- Implementation ----------------------------*/ + +/* Globals for locking interrupt handlers in _pmdos.asm */ + +#ifndef REALMODE +extern int _VARAPI _PM_pmdosDataStart; +extern int _VARAPI _PM_pmdosDataEnd; +extern int _VARAPI _PM_DMADataStart; +extern int _VARAPI _PM_DMADataEnd; +void _ASMAPI _PM_pmdosCodeStart(void); +void _ASMAPI _PM_pmdosCodeEnd(void); +void _ASMAPI _PM_DMACodeStart(void); +void _ASMAPI _PM_DMACodeEnd(void); +#endif + +/* Protected mode interrupt handlers, also called by PM callbacks below */ + +void _ASMAPI _PM_timerISR(void); +void _ASMAPI _PM_rtcISR(void); +void _ASMAPI _PM_irqISRTemplate(void); +void _ASMAPI _PM_irqISRTemplateEnd(void); +void _ASMAPI _PM_keyISR(void); +void _ASMAPI _PM_key15ISR(void); +void _ASMAPI _PM_breakISR(void); +void _ASMAPI _PM_ctrlCISR(void); +void _ASMAPI _PM_criticalISR(void); +void _ASMAPI _PM_mouseISR(void); +void _ASMAPI _PM_int10PMCB(void); + +/* Protected mode DPMI callback handlers */ + +void _ASMAPI _PM_mousePMCB(void); + +/* Routine to install a mouse handler function */ + +void _ASMAPI _PM_setMouseHandler(int mask); + +/* Routine to allocate DPMI real mode callback routines */ + +ibool _ASMAPI _DPMI_allocateCallback(void (_ASMAPI *pmcode)(),void *rmregs,long *RMCB); +void _ASMAPI _DPMI_freeCallback(long RMCB); + +/* DPMI helper functions in PMLITE.C */ + +ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit); +int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr); +ulong PMAPI DPMI_getSelectorBase(ushort sel); +int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit); +uint PMAPI DPMI_createSelector(ulong base,ulong limit); +void PMAPI DPMI_freeSelector(uint sel); +int PMAPI DPMI_lockLinearPages(ulong linear,ulong len); +int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len); + +/* Functions to read and write CMOS registers */ + +uchar PMAPI _PM_readCMOS(int index); +void PMAPI _PM_writeCMOS(int index,uchar value); + +/*-------------------------------------------------------------------------*/ +/* Generic routines common to all environments */ +/*-------------------------------------------------------------------------*/ + +void PMAPI PM_resetMouseDriver(int hardReset) +{ + RMREGS regs; + PM_mouseHandler oldHandler = _PM_mouseHandler; + + PM_restoreMouseHandler(); + regs.x.ax = hardReset ? 0 : 33; + PM_int86(0x33, ®s, ®s); + if (oldHandler) + PM_setMouseHandler(_PM_mouseMask, oldHandler); +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + static short convert[] = { + 8192, + 4096, + 2048, + 1024, + 512, + 256, + 128, + 64, + 32, + 16, + 8, + 4, + 2, + -1, + }; + int i; + + /* First clear any pending RTC timeout if not cleared */ + _PM_readCMOS(0x0C); + if (frequency == 0) { + /* Disable RTC timout */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F); + } + else { + /* Convert frequency value to RTC clock indexes */ + for (i = 0; convert[i] != -1; i++) { + if (convert[i] == frequency) + break; + } + + /* Set RTC timout value and enable timeout */ + _PM_writeCMOS(0x0A,0x20 | (i+3)); + _PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40); + } +} + +#ifndef REALMODE + +static void PMAPI lockPMHandlers(void) +{ + static int locked = 0; + int stat; + PM_lockHandle lh; /* Unused in DOS */ + + /* Lock all of the code and data used by our protected mode interrupt + * handling routines, so that it will continue to work correctly + * under real mode. + */ + if (!locked) { + PM_saveDS(); + stat = !PM_lockDataPages(&globalDataStart-2048,4096,&lh); + stat |= !PM_lockDataPages(&_PM_pmdosDataStart,(int)&_PM_pmdosDataEnd - (int)&_PM_pmdosDataStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_PM_pmdosCodeStart,(int)_PM_pmdosCodeEnd-(int)_PM_pmdosCodeStart,&lh); + stat |= !PM_lockDataPages(&_PM_DMADataStart,(int)&_PM_DMADataEnd - (int)&_PM_DMADataStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_PM_DMACodeStart,(int)_PM_DMACodeEnd-(int)_PM_DMACodeStart,&lh); + if (stat) { + printf("Page locking services failed - interrupt handling not safe!\n"); + exit(1); + } + locked = 1; + } +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* DOS Real Mode support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef REALMODE + +#ifndef MK_FP +#define MK_FP(s,o) ( (void far *)( ((ulong)(s) << 16) + \ + (ulong)(o) )) +#endif + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + PM_saveDS(); + _PM_mouseHandler = mh; + _PM_setMouseHandler(_PM_mouseMask = mask); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + union REGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + int86(0x33, ®s, ®s); + _PM_mouseHandler = NULL; + } +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + _PM_getRMvect(0x8, (long*)&_PM_prevTimer); + _PM_timerHandler = th; + _PM_setRMvect(0x8, (long)_PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + _PM_setRMvect(0x8, (long)_PM_prevTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + _PM_getRMvect(0x70, (long*)&_PM_prevRTC); + _PM_rtcHandler = th; + _PM_setRMvect(0x70, (long)_PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + _PM_setRMvect(0x70, (long)_PM_prevRTC); + _PM_rtcHandler = NULL; + } +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + _PM_getRMvect(0x9, (long*)&_PM_prevKey); + _PM_keyHandler = kh; + _PM_setRMvect(0x9, (long)_PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + _PM_setRMvect(0x9, (long)_PM_prevKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + _PM_getRMvect(0x15, (long*)&_PM_prevKey15); + _PM_key15Handler = kh; + _PM_setRMvect(0x15, (long)_PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + _PM_setRMvect(0x15, (long)_PM_prevKey15); + _PM_key15Handler = NULL; + } +} + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ + static int ctrlCFlag,ctrlBFlag; + + _PM_ctrlCPtr = (uchar*)&ctrlCFlag; + _PM_ctrlBPtr = (uchar*)&ctrlBFlag; + _PM_getRMvect(0x1B, (long*)&_PM_prevBreak); + _PM_getRMvect(0x23, (long*)&_PM_prevCtrlC); + _PM_breakHandler = bh; + _PM_setRMvect(0x1B, (long)_PM_breakISR); + _PM_setRMvect(0x23, (long)_PM_ctrlCISR); +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak) { + _PM_setRMvect(0x1B, (long)_PM_prevBreak); + _PM_setRMvect(0x23, (long)_PM_prevCtrlC); + _PM_prevBreak = NULL; + _PM_breakHandler = NULL; + } +} + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ + static short critBuf[2]; + + _PM_critPtr = (uchar*)critBuf; + _PM_getRMvect(0x24, (long*)&_PM_prevCritical); + _PM_critHandler = ch; + _PM_setRMvect(0x24, (long)_PM_criticalISR); +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical) { + _PM_setRMvect(0x24, (long)_PM_prevCritical); + _PM_prevCritical = NULL; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; /* Do nothing for real mode */ + return 1; +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; /* Do nothing for real mode */ + return 1; +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; /* Do nothing for real mode */ + return 1; +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; /* Do nothing for real mode */ + return 1; +} + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + long t; + _PM_getRMvect(intno,&t); + *isr = (void*)t; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PM_saveDS(); + _PM_setRMvect(intno,(long)isr); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + _PM_setRMvect(intno,(long)isr); +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Phar Lap TNT DOS Extender support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef TNT + +#include +#include +#include + +static long prevRealBreak; /* Previous real mode break handler */ +static long prevRealCtrlC; /* Previous real mode CtrlC handler */ +static long prevRealCritical; /* Prev real mode critical handler */ +static uchar *mousePtr; + +/* The following real mode routine is used to call a 32 bit protected + * mode FAR function from real mode. We use this for passing up control + * from the real mode mouse callback to our protected mode code. + */ + +static UCHAR realHandler[] = { /* Real mode code generic handler */ + 0x00,0x00,0x00,0x00, /* __PM_callProtp */ + 0x00,0x00, /* __PM_protCS */ + 0x00,0x00,0x00,0x00, /* __PM_protHandler */ + 0x66,0x60, /* pushad */ + 0x1E, /* push ds */ + 0x6A,0x00, /* push 0 */ + 0x6A,0x00, /* push 0 */ + 0x2E,0xFF,0x36,0x04,0x00, /* push [cs:__PM_protCS] */ + 0x66,0x2E,0xFF,0x36,0x06,0x00, /* push [cs:__PM_protHandler] */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PM_callProtp] */ + 0x83,0xC4,0x0A, /* add sp,10 */ + 0x1F, /* pop ds */ + 0x66,0x61, /* popad */ + 0xCB, /* retf */ + }; + +/* The following functions installs the above realmode callback mechanism + * in real mode memory for calling the protected mode routine. + */ + +uchar * installCallback(void (PMAPI *pmCB)(),uint *rseg, uint *roff) +{ + CONFIG_INF config; + REALPTR realBufAdr,callProtp; + ULONG bufSize; + FARPTR protBufAdr; + uchar *p; + + /* Get address of real mode routine to call up to protected mode */ + _dx_rmlink_get(&callProtp, &realBufAdr, &bufSize, &protBufAdr); + _dx_config_inf(&config, (UCHAR*)&config); + + /* Fill in the values in the real mode code segment so that it will + * call the correct routine. + */ + *((REALPTR*)&realHandler[0]) = callProtp; + *((USHORT*)&realHandler[4]) = config.c_cs_sel; + *((ULONG*)&realHandler[6]) = (ULONG)pmCB; + + /* Copy the real mode handler to real mode memory */ + if ((p = PM_allocRealSeg(sizeof(realHandler),rseg,roff)) == NULL) + return NULL; + memcpy(p,realHandler,sizeof(realHandler)); + + /* Skip past global variabls in real mode code segment */ + *roff += 0x0A; + return p; +} + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + RMREGS regs; + RMSREGS sregs; + uint rseg,roff; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + if ((mousePtr = installCallback(_PM_mouseISR, &rseg, &roff)) == NULL) + return 0; + _PM_mouseHandler = mh; + + /* Install the real mode mouse handler */ + sregs.es = rseg; + regs.x.dx = roff; + regs.x.cx = _PM_mouseMask = mask; + regs.x.ax = 0xC; + PM_int86x(0x33, ®s, ®s, &sregs); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + RMREGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + PM_int86(0x33, ®s, ®s); + PM_freeRealSeg(mousePtr); + _PM_mouseHandler = NULL; + } +} + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + FARPTR ph; + + _dx_pmiv_get(intno, &ph); + isr->sel = FP_SEL(ph); + isr->off = FP_OFF(ph); +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + CONFIG_INF config; + FARPTR ph; + + PM_saveDS(); + _dx_config_inf(&config, (UCHAR*)&config); + FP_SET(ph,(uint)isr,config.c_cs_sel); + _dx_pmiv_set(intno,ph); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + FARPTR ph; + + FP_SET(ph,isr.off,isr.sel); + _dx_pmiv_set(intno,ph); +} + +static void getISR(int intno, PMFARPTR *pmisr, long *realisr) +{ + PM_getPMvect(intno,pmisr); + _PM_getRMvect(intno, realisr); +} + +static void restoreISR(int intno, PMFARPTR pmisr, long realisr) +{ + _PM_setRMvect(intno,realisr); + PM_restorePMvect(intno,pmisr); +} + +static void setISR(int intno, void (PMAPI *isr)()) +{ + CONFIG_INF config; + FARPTR ph; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + _dx_config_inf(&config, (UCHAR*)&config); + FP_SET(ph,(uint)isr,config.c_cs_sel); + _dx_apmiv_set(intno,ph); +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer); + _PM_timerHandler = th; + setISR(0x8, _PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); + _PM_rtcHandler = th; + setISR(0x70, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); + _PM_rtcHandler = NULL; + } +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + getISR(0x9, &_PM_prevKey, &_PM_prevRealKey); + _PM_keyHandler = kh; + setISR(0x9, _PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + restoreISR(0x9, _PM_prevKey, _PM_prevRealKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); + _PM_key15Handler = kh; + setISR(0x15, _PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); + _PM_key15Handler = NULL; + } +} + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ + static int ctrlCFlag,ctrlBFlag; + + _PM_ctrlCPtr = (uchar*)&ctrlCFlag; + _PM_ctrlBPtr = (uchar*)&ctrlBFlag; + getISR(0x1B, &_PM_prevBreak, &prevRealBreak); + getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); + _PM_breakHandler = bh; + setISR(0x1B, _PM_breakISR); + setISR(0x23, _PM_ctrlCISR); +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak.sel) { + restoreISR(0x1B, _PM_prevBreak, prevRealBreak); + restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); + _PM_prevBreak.sel = 0; + _PM_breakHandler = NULL; + } +} + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ + static short critBuf[2]; + + _PM_critPtr = (uchar*)critBuf; + getISR(0x24, &_PM_prevCritical, &prevRealCritical); + _PM_critHandler = ch; + setISR(0x24, _PM_criticalISR); +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical.sel) { + restoreISR(0x24, _PM_prevCritical, prevRealCritical); + _PM_prevCritical.sel = 0; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + return (_dx_lock_pgsn(p,len) == 0); +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + return (_dx_ulock_pgsn(p,len) == 0); +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + CONFIG_INF config; + FARPTR fp; + + _dx_config_inf(&config, (UCHAR*)&config); + FP_SET(fp,p,config.c_cs_sel); + return (_dx_lock_pgs(fp,len) == 0); +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + CONFIG_INF config; + FARPTR fp; + + _dx_config_inf(&config, (UCHAR*)&config); + FP_SET(fp,p,config.c_cs_sel); + return (_dx_ulock_pgs(fp,len) == 0); +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Symantec C++ DOSX and FlashTek X-32/X-32VM support */ +/*-------------------------------------------------------------------------*/ + +#if defined(DOSX) || defined(X32VM) + +#ifdef X32VM +#include +#endif + +static long prevRealBreak; /* Previous real mode break handler */ +static long prevRealCtrlC; /* Previous real mode CtrlC handler */ +static long prevRealCritical; /* Prev real mode critical handler */ + +static uint mouseSel = 0,mouseOff; + +/* The following real mode routine is used to call a 32 bit protected + * mode FAR function from real mode. We use this for passing up control + * from the real mode mouse callback to our protected mode code. + */ + +static char realHandler[] = { /* Real mode code generic handler */ + 0x00,0x00,0x00,0x00, /* __PM_callProtp */ + 0x00,0x00, /* __PM_protCS */ + 0x00,0x00,0x00,0x00, /* __PM_protHandler */ + 0x1E, /* push ds */ + 0x6A,0x00, /* push 0 */ + 0x6A,0x00, /* push 0 */ + 0x2E,0xFF,0x36,0x04,0x00, /* push [cs:__PM_protCS] */ + 0x66,0x2E,0xFF,0x36,0x06,0x00, /* push [cs:__PM_protHandler] */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PM_callProtp] */ + 0x83,0xC4,0x0A, /* add sp,10 */ + 0x1F, /* pop ds */ + 0xCB, /* retf */ + }; + +/* The following functions installs the above realmode callback mechanism + * in real mode memory for calling the protected mode routine. + */ + +int installCallback(void (PMAPI *pmCB)(),uint *psel, uint *poff, + uint *rseg, uint *roff) +{ + PMREGS regs; + PMSREGS sregs; + + regs.x.ax = 0x250D; + PM_segread(&sregs); + PM_int386x(0x21,®s,®s,&sregs); /* Get RM callback address */ + + /* Fill in the values in the real mode code segment so that it will + * call the correct routine. + */ + *((ulong*)&realHandler[0]) = regs.e.eax; + *((ushort*)&realHandler[4]) = sregs.cs; + *((ulong*)&realHandler[6]) = (ulong)pmCB; + + /* Copy the real mode handler to real mode memory (only allocate the + * buffer once since we cant dealloate it with X32). + */ + if (*psel == 0) { + if (!PM_allocRealSeg(sizeof(realHandler),psel,poff,rseg,roff)) + return 0; + } + PM_memcpyfn(*psel,*poff,realHandler,sizeof(realHandler)); + + /* Skip past global variables in real mode code segment */ + *roff += 0x0A; + return 1; +} + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + RMREGS regs; + RMSREGS sregs; + uint rseg,roff; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + if (!installCallback(_PM_mouseISR, &mouseSel, &mouseOff, &rseg, &roff)) + return 0; + _PM_mouseHandler = mh; + + /* Install the real mode mouse handler */ + sregs.es = rseg; + regs.x.dx = roff; + regs.x.cx = _PM_mouseMask = mask; + regs.x.ax = 0xC; + PM_int86x(0x33, ®s, ®s, &sregs); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + RMREGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + PM_int86(0x33, ®s, ®s); + _PM_mouseHandler = NULL; + } +} + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.x.ax = 0x2502; /* Get PM interrupt vector */ + regs.x.cx = intno; + PM_int386x(0x21, ®s, ®s, &sregs); + isr->sel = sregs.es; + isr->off = regs.e.ebx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMFARPTR pmisr; + PMSREGS sregs; + + PM_saveDS(); + PM_segread(&sregs); + pmisr.sel = sregs.cs; + pmisr.off = (uint)isr; + PM_restorePMvect(intno, pmisr); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.x.ax = 0x2505; /* Set PM interrupt vector */ + regs.x.cx = intno; + sregs.ds = isr.sel; + regs.e.edx = isr.off; + PM_int386x(0x21, ®s, ®s, &sregs); +} + +static void getISR(int intno, PMFARPTR *pmisr, long *realisr) +{ + PM_getPMvect(intno,pmisr); + _PM_getRMvect(intno,realisr); +} + +static void restoreISR(int intno, PMFARPTR pmisr, long realisr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.x.ax = 0x2507; /* Set real and PM vectors */ + regs.x.cx = intno; + sregs.ds = pmisr.sel; + regs.e.edx = pmisr.off; + regs.e.ebx = realisr; + PM_int386x(0x21, ®s, ®s, &sregs); +} + +static void setISR(int intno, void *isr) +{ + PMREGS regs; + PMSREGS sregs; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + PM_segread(&sregs); + regs.x.ax = 0x2506; /* Hook real and protected vectors */ + regs.x.cx = intno; + sregs.ds = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386x(0x21, ®s, ®s, &sregs); +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer); + _PM_timerHandler = th; + setISR(0x8, _PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); + _PM_rtcHandler = th; + setISR(0x70, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); + _PM_rtcHandler = NULL; + } +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + getISR(0x9, &_PM_prevKey, &_PM_prevRealKey); + _PM_keyHandler = kh; + setISR(0x9, _PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + restoreISR(0x9, _PM_prevKey, _PM_prevRealKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); + _PM_key15Handler = kh; + setISR(0x15, _PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); + _PM_key15Handler = NULL; + } +} + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ + static int ctrlCFlag,ctrlBFlag; + + _PM_ctrlCPtr = (uchar*)&ctrlCFlag; + _PM_ctrlBPtr = (uchar*)&ctrlBFlag; + getISR(0x1B, &_PM_prevBreak, &prevRealBreak); + getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); + _PM_breakHandler = bh; + setISR(0x1B, _PM_breakISR); + setISR(0x23, _PM_ctrlCISR); +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak.sel) { + restoreISR(0x1B, _PM_prevBreak, prevRealBreak); + restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); + _PM_prevBreak.sel = 0; + _PM_breakHandler = NULL; + } +} + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ + static short critBuf[2]; + + _PM_critPtr = (uchar*)critBuf; + getISR(0x24, &_PM_prevCritical, &prevRealCritical); + _PM_critHandler = ch; + setISR(0x24, _PM_criticalISR); +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical.sel) { + restoreISR(0x24, _PM_prevCritical, prevRealCritical); + _PM_prevCritical.sel = 0; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + return (_x386_memlock(p,len) == 0); +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + return (_x386_memunlock(p,len) == 0); +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + return (_x386_memlock(p,len) == 0); +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + return (_x386_memunlock(p,len) == 0); +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Borland's DPMI32 DOS Power Pack Extender support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef DPMI32 +#define GENERIC_DPMI32 /* Use generic 32 bit DPMI routines */ + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + + regs.x.ax = 0x204; + regs.h.bl = intno; + PM_int386(0x31,®s,®s); + isr->sel = regs.x.cx; + isr->off = regs.e.edx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMSREGS sregs; + PMREGS regs; + + PM_saveDS(); + regs.x.ax = 0x205; /* Set protected mode vector */ + regs.h.bl = intno; + PM_segread(&sregs); + regs.x.cx = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386(0x31,®s,®s); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + + regs.x.ax = 0x205; + regs.h.bl = intno; + regs.x.cx = isr.sel; + regs.e.edx = isr.off; + PM_int386(0x31,®s,®s); +} +#endif + +/*-------------------------------------------------------------------------*/ +/* Watcom C/C++ with Rational DOS/4GW support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef DOS4GW +#define GENERIC_DPMI32 /* Use generic 32 bit DPMI routines */ + +#define MOUSE_SUPPORTED /* DOS4GW directly supports mouse */ + +/* We use the normal DOS services to save and restore interrupts handlers + * for Watcom C++, because using the direct DPMI functions does not + * appear to work properly. At least if we use the DPMI functions, we + * dont get the auto-passup feature that we need to correctly trap + * real and protected mode interrupts without installing Bi-model + * interrupt handlers. + */ + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.h.ah = 0x35; + regs.h.al = intno; + PM_int386x(0x21,®s,®s,&sregs); + isr->sel = sregs.es; + isr->off = regs.e.ebx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_saveDS(); + PM_segread(&sregs); + regs.h.ah = 0x25; + regs.h.al = intno; + sregs.ds = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386x(0x21,®s,®s,&sregs); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.h.ah = 0x25; + regs.h.al = intno; + sregs.ds = isr.sel; + regs.e.edx = isr.off; + PM_int386x(0x21,®s,®s,&sregs); +} + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + lockPMHandlers(); /* Ensure our handlers are locked */ + + _PM_mouseHandler = mh; + _PM_setMouseHandler(_PM_mouseMask = mask); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + PMREGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + PM_int386(0x33, ®s, ®s); + _PM_mouseHandler = NULL; + } +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* DJGPP port of GNU C++ support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef DJGPP +#define GENERIC_DPMI32 /* Use generic 32 bit DPMI routines */ + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + + regs.x.ax = 0x204; + regs.h.bl = intno; + PM_int386(0x31,®s,®s); + isr->sel = regs.x.cx; + isr->off = regs.e.edx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMSREGS sregs; + PMREGS regs; + + PM_saveDS(); + regs.x.ax = 0x205; /* Set protected mode vector */ + regs.h.bl = intno; + PM_segread(&sregs); + regs.x.cx = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386(0x31,®s,®s); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + + regs.x.ax = 0x205; + regs.h.bl = intno; + regs.x.cx = isr.sel; + regs.e.edx = isr.off; + PM_int386(0x31,®s,®s); +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Generic 32 bit DPMI routines */ +/*-------------------------------------------------------------------------*/ + +#if defined(GENERIC_DPMI32) + +static long prevRealBreak; /* Previous real mode break handler */ +static long prevRealCtrlC; /* Previous real mode CtrlC handler */ +static long prevRealCritical; /* Prev real mode critical handler */ + +#ifndef MOUSE_SUPPORTED + +/* The following real mode routine is used to call a 32 bit protected + * mode FAR function from real mode. We use this for passing up control + * from the real mode mouse callback to our protected mode code. + */ + +static long mouseRMCB; /* Mouse real mode callback address */ +static uchar *mousePtr; +static char mouseRegs[0x32]; /* Real mode regs for mouse callback */ +static uchar mouseHandler[] = { + 0x00,0x00,0x00,0x00, /* _realRMCB */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:_realRMCB] */ + 0xCB, /* retf */ + }; + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + RMREGS regs; + RMSREGS sregs; + uint rseg,roff; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + /* Copy the real mode handler to real mode memory */ + if ((mousePtr = PM_allocRealSeg(sizeof(mouseHandler),&rseg,&roff)) == NULL) + return 0; + memcpy(mousePtr,mouseHandler,sizeof(mouseHandler)); + if (!_DPMI_allocateCallback(_PM_mousePMCB, mouseRegs, &mouseRMCB)) + PM_fatalError("Unable to allocate real mode callback!\n"); + PM_setLong(mousePtr,mouseRMCB); + + /* Install the real mode mouse handler */ + _PM_mouseHandler = mh; + sregs.es = rseg; + regs.x.dx = roff+4; + regs.x.cx = _PM_mouseMask = mask; + regs.x.ax = 0xC; + PM_int86x(0x33, ®s, ®s, &sregs); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + RMREGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + PM_int86(0x33, ®s, ®s); + PM_freeRealSeg(mousePtr); + _DPMI_freeCallback(mouseRMCB); + _PM_mouseHandler = NULL; + } +} + +#endif + +static void getISR(int intno, PMFARPTR *pmisr, long *realisr) +{ + PM_getPMvect(intno,pmisr); + _PM_getRMvect(intno,realisr); +} + +static void restoreISR(int intno, PMFARPTR pmisr, long realisr) +{ + _PM_setRMvect(intno,realisr); + PM_restorePMvect(intno,pmisr); +} + +static void setISR(int intno, void (* PMAPI pmisr)()) +{ + lockPMHandlers(); /* Ensure our handlers are locked */ + PM_setPMvect(intno,pmisr); +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer); + _PM_timerHandler = th; + setISR(0x8, _PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); + _PM_rtcHandler = th; + setISR(0x70, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); + _PM_rtcHandler = NULL; + } +} + +PM_IRQHandle PMAPI PM_setIRQHandler( + int IRQ, + PM_irqHandler ih) +{ + int thunkSize,PICmask,chainPrevious; + ulong offsetAdjust; + _PM_IRQHandle *handle; + + thunkSize = (ulong)_PM_irqISRTemplateEnd - (ulong)_PM_irqISRTemplate; + if ((handle = PM_malloc(sizeof(_PM_IRQHandle) + thunkSize)) == NULL) + return NULL; + handle->IRQ = IRQ; + handle->prevPIC = PM_inpb(0x21); + handle->prevPIC2 = PM_inpb(0xA1); + if (IRQ < 8) { + handle->IRQVect = (IRQ + 8); + PICmask = (1 << IRQ); + chainPrevious = ((handle->prevPIC & PICmask) == 0); + } + else { + handle->IRQVect = (0x60 + IRQ + 8); + PICmask = ((1 << IRQ) | 0x4); + chainPrevious = ((handle->prevPIC2 & (PICmask >> 8)) == 0); + } + + /* Copy and setup the assembler thunk */ + offsetAdjust = (ulong)handle->thunk - (ulong)_PM_irqISRTemplate; + memcpy(handle->thunk,_PM_irqISRTemplate,thunkSize); + *((ulong*)&handle->thunk[2]) = offsetAdjust; + *((ulong*)&handle->thunk[11+0]) = (ulong)ih; + if (chainPrevious) { + *((ulong*)&handle->thunk[11+4]) = handle->prevHandler.off; + *((ulong*)&handle->thunk[11+8]) = handle->prevHandler.sel; + } + else { + *((ulong*)&handle->thunk[11+4]) = 0; + *((ulong*)&handle->thunk[11+8]) = 0; + } + *((ulong*)&handle->thunk[11+12]) = IRQ; + + /* Set the real time clock interrupt handler */ + getISR(handle->IRQVect, &handle->prevHandler, &handle->prevRealhandler); + setISR(handle->IRQVect, (PM_intHandler)handle->thunk); + + /* Unmask the IRQ in the PIC */ + PM_outpb(0xA1,handle->prevPIC2 & ~(PICmask >> 8)); + PM_outpb(0x21,handle->prevPIC & ~PICmask); + return handle; +} + +void PMAPI PM_restoreIRQHandler( + PM_IRQHandle irqHandle) +{ + int PICmask; + _PM_IRQHandle *handle = irqHandle; + + /* Restore PIC mask for the interrupt */ + if (handle->IRQ < 8) + PICmask = (1 << handle->IRQ); + else + PICmask = ((1 << handle->IRQ) | 0x4); + PM_outpb(0xA1,(PM_inpb(0xA1) & ~(PICmask >> 8)) | (handle->prevPIC2 & (PICmask >> 8))); + PM_outpb(0x21,(PM_inpb(0x21) & ~PICmask) | (handle->prevPIC & PICmask)); + + /* Restore the interrupt vector */ + restoreISR(handle->IRQVect, handle->prevHandler, handle->prevRealhandler); + + /* Finally free the thunk */ + PM_free(handle); +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + getISR(0x9, &_PM_prevKey, &_PM_prevRealKey); + _PM_keyHandler = kh; + setISR(0x9, _PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + restoreISR(0x9, _PM_prevKey, _PM_prevRealKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); + _PM_key15Handler = kh; + setISR(0x15, _PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); + _PM_key15Handler = NULL; + } +} + +/* Real mode Ctrl-C and Ctrl-Break handler. This handler simply sets a + * flag in the real mode code segment and exit. We save the location + * of this flag in real mode memory so that both the real mode and + * protected mode code will be modifying the same flags. + */ + +#ifndef DOS4GW +static uchar ctrlHandler[] = { + 0x00,0x00,0x00,0x00, /* ctrlBFlag */ + 0x66,0x2E,0xC7,0x06,0x00,0x00, + 0x01,0x00,0x00,0x00, /* mov [cs:ctrlBFlag],1 */ + 0xCF, /* iretf */ + }; +#endif + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ +#ifndef DOS4GW + uint rseg,roff; +#else + static int ctrlCFlag,ctrlBFlag; + + _PM_ctrlCPtr = (uchar*)&ctrlCFlag; + _PM_ctrlBPtr = (uchar*)&ctrlBFlag; +#endif + + getISR(0x1B, &_PM_prevBreak, &prevRealBreak); + getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); + _PM_breakHandler = bh; + setISR(0x1B, _PM_breakISR); + setISR(0x23, _PM_ctrlCISR); + +#ifndef DOS4GW + /* Hook the real mode vectors for these handlers, as these are not + * normally reflected by the DPMI server up to protected mode + */ + _PM_ctrlBPtr = PM_allocRealSeg(sizeof(ctrlHandler)*2, &rseg, &roff); + memcpy(_PM_ctrlBPtr,ctrlHandler,sizeof(ctrlHandler)); + memcpy(_PM_ctrlBPtr+sizeof(ctrlHandler),ctrlHandler,sizeof(ctrlHandler)); + _PM_ctrlCPtr = _PM_ctrlBPtr + sizeof(ctrlHandler); + _PM_setRMvect(0x1B,((long)rseg << 16) | (roff+4)); + _PM_setRMvect(0x23,((long)rseg << 16) | (roff+sizeof(ctrlHandler)+4)); +#endif +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak.sel) { + restoreISR(0x1B, _PM_prevBreak, prevRealBreak); + restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); + _PM_prevBreak.sel = 0; + _PM_breakHandler = NULL; +#ifndef DOS4GW + PM_freeRealSeg(_PM_ctrlBPtr); +#endif + } +} + +/* Real mode Critical Error handler. This handler simply saves the AX and + * DI values in the real mode code segment and exits. We save the location + * of this flag in real mode memory so that both the real mode and + * protected mode code will be modifying the same flags. + */ + +#ifndef DOS4GW +static uchar criticalHandler[] = { + 0x00,0x00, /* axCode */ + 0x00,0x00, /* diCode */ + 0x2E,0xA3,0x00,0x00, /* mov [cs:axCode],ax */ + 0x2E,0x89,0x3E,0x02,0x00, /* mov [cs:diCode],di */ + 0xB8,0x03,0x00, /* mov ax,3 */ + 0xCF, /* iretf */ + }; +#endif + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ +#ifndef DOS4GW + uint rseg,roff; +#else + static short critBuf[2]; + + _PM_critPtr = (uchar*)critBuf; +#endif + + getISR(0x24, &_PM_prevCritical, &prevRealCritical); + _PM_critHandler = ch; + setISR(0x24, _PM_criticalISR); + +#ifndef DOS4GW + /* Hook the real mode vector, as this is not normally reflected by the + * DPMI server up to protected mode. + */ + _PM_critPtr = PM_allocRealSeg(sizeof(criticalHandler)*2, &rseg, &roff); + memcpy(_PM_critPtr,criticalHandler,sizeof(criticalHandler)); + _PM_setRMvect(0x24,((long)rseg << 16) | (roff+4)); +#endif +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical.sel) { + restoreISR(0x24, _PM_prevCritical, prevRealCritical); + PM_freeRealSeg(_PM_critPtr); + _PM_prevCritical.sel = 0; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.cs),len); +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.cs),len); +} + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c new file mode 100644 index 0000000..c3e9b6c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c @@ -0,0 +1,251 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit DOS +* +* Description: Main C module for the VFlat framebuffer routines. The page +* fault handler is always installed to handle up to a 4Mb +* framebuffer with a window size of 4Kb or 64Kb in size. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include + +/*-------------------------------------------------------------------------*/ +/* DOS4G/W, PMODE/W and CauseWay support. */ +/*-------------------------------------------------------------------------*/ + +#if defined(DOS4GW) + +#define VFLAT_START_ADDR 0xF0000000U +#define VFLAT_END_ADDR 0xF03FFFFFU +#define VFLAT_LIMIT (VFLAT_END_ADDR - VFLAT_START_ADDR) +#define PAGE_PRESENT 1 +#define PAGE_NOTPRESENT 0 +#define PAGE_READ 0 +#define PAGE_WRITE 2 + +PRIVATE ibool installed = false; +PRIVATE ibool haveDPMI = false; +PUBLIC ibool _ASMAPI VF_haveCauseWay = false; +PUBLIC uchar * _ASMAPI VF_zeroPtr = NULL; + +/* Low level assembler code */ + +int _ASMAPI InitPaging(void); +void _ASMAPI ClosePaging(void); +void _ASMAPI MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags); +void _ASMAPI InstallFaultHandler(ulong baseAddr,int bankSize); +void _ASMAPI RemoveFaultHandler(void); +void _ASMAPI InstallBankFunc(int codeLen,void *bankFunc); + +void * _ASMAPI VF_malloc(uint size) +{ return PM_malloc(size); } + +void _ASMAPI VF_free(void *p) +{ PM_free(p); } + +PRIVATE ibool CheckDPMI(void) +/**************************************************************************** +* +* Function: CheckDPMI +* Returns: True if we are running under DPMI +* +****************************************************************************/ +{ + PMREGS regs; + + if (haveDPMI) + return true; + + /* Check if we are running under DPMI in which case we will not be + * able to install our page fault handlers. We can however use the + * DVA.386 or VFLATD.386 virtual device drivers if they are present. + */ + regs.x.ax = 0xFF00; + PM_int386(0x31,®s,®s); + if (!regs.x.cflag && (regs.e.edi & 8)) + return (haveDPMI = true); + return false; +} + +ibool PMAPI VF_available(void) +/**************************************************************************** +* +* Function: VF_available +* Returns: True if virtual buffer is available, false if not. +* +****************************************************************************/ +{ + if (!VF_zeroPtr) + VF_zeroPtr = PM_mapPhysicalAddr(0,0xFFFFFFFF,true); + if (CheckDPMI()) + return false; + + /* Standard DOS4GW, PMODE/W and Causeway */ + if (InitPaging() == -1) + return false; + ClosePaging(); + return true; +} + +void * PMAPI InitDPMI(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +/**************************************************************************** +* +* Function: InitDOS4GW +* Parameters: baseAddr - Base address of framebuffer bank window +* bankSize - Physical size of banks in Kb (4 or 64) +* codeLen - Length of 32 bit bank switch function +* bankFunc - Pointer to protected mode bank function +* Returns: Near pointer to virtual framebuffer, or NULL on failure. +* +* Description: Installs the virtual linear framebuffer handling for +* DPMI environments. This requires the DVA.386 or VFLATD.386 +* virtual device drivers to be installed and functioning. +* +****************************************************************************/ +{ + (void)baseAddr; + (void)bankSize; + (void)codeLen; + (void)bankFunc; + return NULL; +} + +void * PMAPI InitDOS4GW(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +/**************************************************************************** +* +* Function: InitDOS4GW +* Parameters: baseAddr - Base address of framebuffer bank window +* bankSize - Physical size of banks in Kb (4 or 64) +* codeLen - Length of 32 bit bank switch function +* bankFunc - Pointer to protected mode bank function +* Returns: Near pointer to virtual framebuffer, or NULL on failure. +* +* Description: Installs the virtual linear framebuffer handling for +* the DOS4GW extender. +* +****************************************************************************/ +{ + int i; + + if (InitPaging() == -1) + return NULL; /* Cannot do hardware paging! */ + + /* Map 4MB of video memory into linear address space (read/write) */ + if (bankSize == 64) { + for (i = 0; i < 64; i++) { + MapPhysical2Linear(baseAddr,VFLAT_START_ADDR+(i<<16),16, + PAGE_WRITE | PAGE_NOTPRESENT); + } + } + else { + for (i = 0; i < 1024; i++) { + MapPhysical2Linear(baseAddr,VFLAT_START_ADDR+(i<<12),1, + PAGE_WRITE | PAGE_NOTPRESENT); + } + } + + /* Install our page fault handler and banks switch function */ + InstallFaultHandler(baseAddr,bankSize); + InstallBankFunc(codeLen,bankFunc); + installed = true; + return (void*)VFLAT_START_ADDR; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +/**************************************************************************** +* +* Function: VF_init +* Parameters: baseAddr - Base address of framebuffer bank window +* bankSize - Physical size of banks in Kb (4 or 64) +* codeLen - Length of 32 bit bank switch function +* bankFunc - Pointer to protected mode bank function +* Returns: Near pointer to virtual framebuffer, or NULL on failure. +* +* Description: Installs the virtual linear framebuffer handling. +* +****************************************************************************/ +{ + if (installed) + return (void*)VFLAT_START_ADDR; + if (codeLen > 100) + return NULL; /* Bank function is too large! */ + if (!VF_zeroPtr) + VF_zeroPtr = PM_mapPhysicalAddr(0,0xFFFFFFFF,true); + if (CheckDPMI()) + return InitDPMI(baseAddr,bankSize,codeLen,bankFunc); + return InitDOS4GW(baseAddr,bankSize,codeLen,bankFunc); +} + +void PMAPI VF_exit(void) +/**************************************************************************** +* +* Function: VF_exit +* +* Description: Closes down the virtual framebuffer services and +* restores the previous page fault handler. +* +****************************************************************************/ +{ + if (installed) { + if (haveDPMI) { + /* DPMI support */ + } + else { + /* Standard DOS4GW and PMODE/W support */ + RemoveFaultHandler(); + ClosePaging(); + } + installed = false; + } +} + +/*-------------------------------------------------------------------------*/ +/* Support mapped out for other compilers. */ +/*-------------------------------------------------------------------------*/ + +#else + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + (void)baseAddr; + (void)bankSize; + (void)codeLen; + (void)bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c new file mode 100644 index 0000000..53ab16c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c @@ -0,0 +1,111 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: MSDOS +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + + +/*---------------------------- Global variables ---------------------------*/ + +uchar * _VARAPI _ZTimerBIOSPtr; + +/*----------------------------- Implementation ----------------------------*/ + +/* External assembler functions */ + +void _ASMAPI LZ_timerOn(void); +ulong _ASMAPI LZ_timerLap(void); +void _ASMAPI LZ_timerOff(void); +ulong _ASMAPI LZ_timerCount(void); +void _ASMAPI LZ_disable(void); +void _ASMAPI LZ_enable(void); + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ + _ZTimerBIOSPtr = PM_getBIOSPointer(); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOn(tm) LZ_timerOn() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerLap(tm) LZ_timerLap() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) LZ_timerOff() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerCount(tm) LZ_timerCount() + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 54925 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + ulong ticks; + LZ_disable(); /* Turn of interrupts */ + ticks = PM_getLong(_ZTimerBIOSPtr+0x6C); + LZ_enable(); /* Turn on interrupts again */ + return ticks; +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ + if (finish < start) + finish += 1573040L; /* Number of ticks in 24 hours */ + return finish - start; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/event.c b/board/MAI/bios_emulator/scitech/src/pm/event.c new file mode 100644 index 0000000..b6f4586 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/event.c @@ -0,0 +1,1115 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Main implementation for the SciTech cross platform event +* library. This module contains all the generic cross platform +* code, and pulls in modules specific to each target OS +* environment. +* +****************************************************************************/ + +#include "event.h" +#include "pmapi.h" +#include +#include +#include +#include +#include +#include "oshdr.h" + +/*--------------------------- Global variables ----------------------------*/ + +#define EVENTQSIZE 100 /* Number of events in event queue */ +#define JOY_NUM_AXES 4 /* Number of joystick axes supported */ + +static struct { + int mx,my; /* Current mouse position */ + int head; /* Head of event queue */ + int tail; /* Tail of event queue */ + int freeHead; /* Head of free list */ + int count; /* No. of items currently in queue */ + event_t evtq[EVENTQSIZE]; /* The queue structure itself */ + int oldMove; /* Previous movement event */ + int oldKey; /* Previous key repeat event */ + int oldJoyMove; /* Previous joystick movement event */ + int joyMask; /* Mask of joystick axes present */ + int joyMin[JOY_NUM_AXES]; + int joyCenter[JOY_NUM_AXES]; + int joyMax[JOY_NUM_AXES]; + int joyPrev[JOY_NUM_AXES]; + int joyButState; + ulong doubleClick; + ulong autoRepeat; + ulong autoDelay; + ulong autoTicks; + ulong doubleClickThresh; + ulong firstAuto; + int autoMouse_x; + int autoMouse_y; + event_t downMouse; + ulong keyModifiers; /* Current keyboard modifiers */ + uchar keyTable[128]; /* Table of key up/down flags */ + ibool allowLEDS; /* True if LEDS should change */ + _EVT_userEventFilter userEventCallback; + _EVT_mouseMoveHandler mouseMove; + _EVT_heartBeatCallback heartBeat; + void *heartBeatParams; + codepage_t *codePage; + } EVT; + +/*---------------------------- Implementation -----------------------------*/ + +#if defined(__REALDOS__) || defined(__SMX32__) +/* {secret} */ +void EVTAPI _EVT_cCodeStart(void) {} +#endif + +/* External assembler functions */ + +int EVTAPI _EVT_readJoyAxis(int mask,int *axis); +int EVTAPI _EVT_readJoyButtons(void); + +/* Forward declaration */ + +ulong _EVT_getTicks(void); + +/**************************************************************************** +PARAMETERS: +evt - Event to add to the event queue + +REMARKS: +Adds an event to the event queue by tacking it onto the tail of the event +queue. This routine assumes that at least one spot is available on the +freeList for the event to be inserted. + +NOTE: Interrupts MUST be OFF while this routine is called to ensure we have + mutually exclusive access to our internal data structures for + interrupt driven systems (like under DOS). +****************************************************************************/ +static void addEvent( + event_t *evt) +{ + int evtID; + + /* Check for mouse double click events */ + if (evt->what & EVT_MOUSEEVT) { + EVT.autoMouse_x = evt->where_x; + EVT.autoMouse_y = evt->where_y; + if ((evt->what & EVT_MOUSEDOWN) && !(evt->message & EVT_DBLCLICK)) { + /* Determine if the last mouse event was a double click event */ + uint diff_x = ABS(evt->where_x - EVT.downMouse.where_x); + uint diff_y = ABS(evt->where_y - EVT.downMouse.where_y); + if ((evt->message == EVT.downMouse.message) + && ((evt->when - EVT.downMouse.when) <= EVT.doubleClick) + && (diff_x <= EVT.doubleClickThresh) + && (diff_y <= EVT.doubleClickThresh)) { + evt->message |= EVT_DBLCLICK; + EVT.downMouse = *evt; + EVT.downMouse.when = 0; + } + else + EVT.downMouse = *evt; + EVT.autoTicks = _EVT_getTicks(); + } + else if (evt->what & EVT_MOUSEUP) { + EVT.downMouse.what = EVT_NULLEVT; + EVT.firstAuto = true; + } + } + + /* Call user supplied callback to modify the event if desired */ + if (EVT.userEventCallback) { + if (!EVT.userEventCallback(evt)) + return; + } + + /* Get spot to place the event from the free list */ + evtID = EVT.freeHead; + EVT.freeHead = EVT.evtq[EVT.freeHead].next; + + /* Add to the EVT.tail of the event queue */ + evt->next = -1; + evt->prev = EVT.tail; + if (EVT.tail != -1) + EVT.evtq[EVT.tail].next = evtID; + else + EVT.head = evtID; + EVT.tail = evtID; + EVT.evtq[evtID] = *evt; + EVT.count++; +} + +/**************************************************************************** +REMARKS: +Internal function to initialise the event queue to the empty state. +****************************************************************************/ +static void initEventQueue(void) +{ + int i; + + /* Build free list, and initialize global data structures */ + for (i = 0; i < EVENTQSIZE; i++) + EVT.evtq[i].next = i+1; + EVT.evtq[EVENTQSIZE-1].next = -1; /* Terminate list */ + EVT.count = EVT.freeHead = 0; + EVT.head = EVT.tail = -1; + EVT.oldMove = -1; + EVT.oldKey = -1; + EVT.oldJoyMove = -1; + EVT.joyButState = 0; + EVT.mx = EVT.my = 0; + EVT.keyModifiers = 0; + EVT.allowLEDS = true; + + /* Set default values for mouse double click and mouse auto events */ + EVT.doubleClick = 440; + EVT.autoRepeat = 55; + EVT.autoDelay = 330; + EVT.autoTicks = 0; + EVT.doubleClickThresh = 5; + EVT.firstAuto = true; + EVT.autoMouse_x = EVT.autoMouse_y = 0; + memset(&EVT.downMouse,0,sizeof(EVT.downMouse)); + + /* Setup default pointers for event library */ + EVT.userEventCallback = NULL; + EVT.codePage = &_CP_US_English; + + /* Initialise the joystick module and do basic calibration (which assumes + * the joystick is centered. + */ + EVT.joyMask = EVT_joyIsPresent(); +} + +#if defined(NEED_SCALE_JOY_AXIS) || !defined(USE_OS_JOYSTICK) +/**************************************************************************** +REMARKS: +This function scales a joystick axis value to normalised form. +****************************************************************************/ +static int scaleJoyAxis( + int raw, + int axis) +{ + int scaled,range; + + /* Make sure the joystick is calibrated properly */ + if (EVT.joyCenter[axis] - EVT.joyMin[axis] < 5) + return raw; + if (EVT.joyMax[axis] - EVT.joyCenter[axis] < 5) + return raw; + + /* Now scale the coordinates to -128 to 127 */ + raw -= EVT.joyCenter[axis]; + if (raw < 0) + range = EVT.joyCenter[axis]-EVT.joyMin[axis]; + else + range = EVT.joyMax[axis]-EVT.joyCenter[axis]; + scaled = (raw * 128) / range; + if (scaled < -128) + scaled = -128; + if (scaled > 127) + scaled = 127; + return scaled; +} +#endif + +#if defined(__SMX32__) +#include "smx/event.c" +#elif defined(__RTTARGET__) +#include "rttarget/event.c" +#elif defined(__REALDOS__) +#include "dos/event.c" +#elif defined(__WINDOWS32__) +#include "win32/event.c" +#elif defined(__OS2__) +#if defined(__OS2_PM__) +#include "os2pm/event.c" +#else +#include "os2/event.c" +#endif +#elif defined(__LINUX__) +#if defined(__USE_X11__) +#include "x11/event.c" +#else +#include "linux/event.c" +#endif +#elif defined(__QNX__) +#if defined(__USE_PHOTON__) +#include "photon/event.c" +#elif defined(__USE_X11__) +#include "x11/event.c" +#else +#include "qnx/event.c" +#endif +#elif defined(__BEOS__) +#include "beos/event.c" +#else +#error Event library not ported to this platform yet! +#endif + +/*------------------------ Public interface routines ----------------------*/ + +/* If USE_OS_JOYSTICK is defined, the OS specific libraries will implement + * the joystick code rather than using the generic OS portable version. + */ + +#ifndef USE_OS_JOYSTICK +/**************************************************************************** +DESCRIPTION: +Returns the mask indicating what joystick axes are attached. + +HEADER: +event.h + +REMARKS: +This function is used to detect the attached joysticks, and determine +what axes are present and functioning. This function will re-detect any +attached joysticks when it is called, so if the user forgot to attach +the joystick when the application started, you can call this function to +re-detect any newly attached joysticks. + +SEE ALSO: +EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +int EVTAPI EVT_joyIsPresent(void) +{ + int mask,i; + + memset(EVT.joyMin,0,sizeof(EVT.joyMin)); + memset(EVT.joyCenter,0,sizeof(EVT.joyCenter)); + memset(EVT.joyMax,0,sizeof(EVT.joyMax)); + memset(EVT.joyPrev,0,sizeof(EVT.joyPrev)); + EVT.joyButState = 0; +#ifdef __LINUX__ + PM_init(); +#endif + mask = _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); + if (mask) { + for (i = 0; i < JOY_NUM_AXES; i++) + EVT.joyMax[i] = EVT.joyCenter[i]*2; + } + return mask; +} + +/**************************************************************************** +DESCRIPTION: +Polls the joystick for position and button information. + +HEADER: +event.h + +REMARKS: +This routine is used to poll analogue joysticks for button and position +information. It should be called once for each main loop of the user +application, just before processing all pending events via EVT_getNext. +All information polled from the joystick will be posted to the event +queue for later retrieval. + +Note: Most analogue joysticks will provide readings that change even + though the joystick has not moved. Hence if you call this routine + you will likely get an EVT_JOYMOVE event every time through your + event loop. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight, +EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_pollJoystick(void) +{ + event_t evt; + int i,axis[JOY_NUM_AXES],newButState,mask,moved,ps; + + if (EVT.joyMask) { + /* Read joystick axes and post movement events if they have + * changed since the last time we polled. Until the events are + * actually flushed, we keep modifying the same joystick movement + * event, so you won't get multiple movement event + */ + mask = _EVT_readJoyAxis(EVT.joyMask,axis); + newButState = _EVT_readJoyButtons(); + moved = false; + for (i = 0; i < JOY_NUM_AXES; i++) { + if (mask & (EVT_JOY_AXIS_X1 << i)) + axis[i] = scaleJoyAxis(axis[i],i); + else + axis[i] = EVT.joyPrev[i]; + if (axis[i] != EVT.joyPrev[i]) + moved = true; + } + if (moved) { + memcpy(EVT.joyPrev,axis,sizeof(EVT.joyPrev)); + ps = _EVT_disableInt(); + if (EVT.oldJoyMove != -1) { + /* Modify the existing joystick movement event */ + EVT.evtq[EVT.oldJoyMove].message = newButState; + EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; + EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; + EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; + EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; + } + else if (EVT.count < EVENTQSIZE) { + /* Add a new joystick movement event */ + EVT.oldJoyMove = EVT.freeHead; + memset(&evt,0,sizeof(evt)); + evt.what = EVT_JOYMOVE; + evt.message = EVT.joyButState; + evt.where_x = EVT.joyPrev[0]; + evt.where_y = EVT.joyPrev[1]; + evt.relative_x = EVT.joyPrev[2]; + evt.relative_y = EVT.joyPrev[3]; + addEvent(&evt); + } + _EVT_restoreInt(ps); + } + + /* Read the joystick buttons, and post events to reflect the change + * in state for the joystick buttons. + */ + if (newButState != EVT.joyButState) { + if (EVT.count < EVENTQSIZE) { + /* Add a new joystick click event */ + ps = _EVT_disableInt(); + memset(&evt,0,sizeof(evt)); + evt.what = EVT_JOYCLICK; + evt.message = newButState; + EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; + EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; + EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; + EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; + addEvent(&evt); + _EVT_restoreInt(ps); + } + EVT.joyButState = newButState; + } + } +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick upper left position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the upper left +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetUpperLeft(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMin); +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick lower right position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the lower right +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetLowerRight(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMax); +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick center position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the center +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter +****************************************************************************/ +void EVTAPI EVT_joySetCenter(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); +} +#endif + +/**************************************************************************** +DESCRIPTION: +Posts a user defined event to the event queue + +HEADER: +event.h + +RETURNS: +True if event was posted, false if event queue is full. + +PARAMETERS: +what - Type code for message to post +message - Event specific message to post +modifiers - Event specific modifier flags to post + +REMARKS: +This routine is used to post user defined events to the event queue. + +SEE ALSO: +EVT_flush, EVT_getNext, EVT_peekNext, EVT_halt +****************************************************************************/ +ibool EVTAPI EVT_post( + ulong which, + ulong what, + ulong message, + ulong modifiers) +{ + event_t evt; + uint ps; + + if (EVT.count < EVENTQSIZE) { + /* Save information in event record */ + ps = _EVT_disableInt(); + evt.which = which; + evt.when = _EVT_getTicks(); + evt.what = what; + evt.message = message; + evt.modifiers = modifiers; + addEvent(&evt); /* Add to EVT.tail of event queue */ + _EVT_restoreInt(ps); + return true; + } + else + return false; +} + +/**************************************************************************** +DESCRIPTION: +Flushes all events of a specified type from the event queue. + +PARAMETERS: +mask - Mask specifying the types of events that should be removed + +HEADER: +event.h + +REMARKS: +Flushes (removes) all pending events of the specified type from the event +queue. You may combine the masks for different event types with a simple +logical OR. + +SEE ALSO: +EVT_getNext, EVT_halt, EVT_peekNext +****************************************************************************/ +void EVTAPI EVT_flush( + ulong mask) +{ + event_t evt; + + do { /* Flush all events */ + EVT_getNext(&evt,mask); + } while (evt.what != EVT_NULLEVT); +} + +/**************************************************************************** +DESCRIPTION: +Halts until and event of the specified type is recieved. + +HEADER: +event.h + +PARAMETERS: +evt - Pointer to +mask - Mask specifying the types of events that should be removed + +REMARKS: +This functions halts exceution until an event of the specified type is +recieved into the event queue. It does not flush the event queue of events +before performing the busy loop. However this function does throw away +any events other than the ones you have requested via the event mask, to +avoid the event queue filling up with unwanted events (like EVT_KEYUP or +EVT_MOUSEMOVE events). + +SEE ALSO: +EVT_getNext, EVT_flush, EVT_peekNext +****************************************************************************/ +void EVTAPI EVT_halt( + event_t *evt, + ulong mask) +{ + do { /* Wait for an event */ + if (mask & (EVT_JOYEVT)) + EVT_pollJoystick(); + EVT_getNext(evt,EVT_EVERYEVT); + } while (!(evt->what & mask)); +} + +/**************************************************************************** +DESCRIPTION: +Peeks at the next pending event in the event queue. + +HEADER: +event.h + +RETURNS: +True if an event is pending, false if not. + +PARAMETERS: +evt - Pointer to structure to return the event info in +mask - Mask specifying the types of events that should be removed + +REMARKS: +Peeks at the next pending event of the specified type in the event queue. The +mask parameter is used to specify the type of events to be peeked at, and +can be any logical combination of any of the flags defined by the +EVT_eventType enumeration. + +In contrast to EVT_getNext, the event is not removed from the event queue. +You may combine the masks for different event types with a simple logical OR. + +SEE ALSO: +EVT_flush, EVT_getNext, EVT_halt +****************************************************************************/ +ibool EVTAPI EVT_peekNext( + event_t *evt, + ulong mask) +{ + int evtID; + uint ps; + + if (EVT.heartBeat) + EVT.heartBeat(EVT.heartBeatParams); + _EVT_pumpMessages(); /* Pump all messages into queue */ + EVT.mouseMove(EVT.mx,EVT.my); /* Move the mouse cursor */ + evt->what = EVT_NULLEVT; /* Default to null event */ + if (EVT.count) { + /* It is possible that an event be posted while we are trying + * to access the event queue. This would create problems since + * we may end up with invalid data for our event queue pointers. To + * alleviate this, all interrupts are suspended while we manipulate + * our pointers. + */ + ps = _EVT_disableInt(); /* disable interrupts */ + for (evtID = EVT.head; evtID != -1; evtID = EVT.evtq[evtID].next) { + if (EVT.evtq[evtID].what & mask) + break; /* Found an event */ + } + if (evtID == -1) { + _EVT_restoreInt(ps); + return false; /* Event was not found */ + } + *evt = EVT.evtq[evtID]; /* Return the event */ + _EVT_restoreInt(ps); + if (evt->what & EVT_KEYEVT) + _EVT_maskKeyCode(evt); + } + return evt->what != EVT_NULLEVT; +} + +/**************************************************************************** +DESCRIPTION: +Retrieves the next pending event from the event queue. + +PARAMETERS: +evt - Pointer to structure to return the event info in +mask - Mask specifying the types of events that should be removed + +HEADER: +event.h + +RETURNS: +True if an event was pending, false if not. + +REMARKS: +Retrieves the next pending event from the event queue, and stores it in a +event_t structure. The mask parameter is used to specify the type of events +to be removed, and can be any logical combination of any of the flags defined +by the EVT_eventType enumeration. + +The what field of the event contains the event code of the event that was +extracted. All application specific events should begin with the EVT_USEREVT +code and build from there. Since the event code is stored in an integer, +there is a maximum of 32 different event codes that can be distinguished. +You can store extra information about the event in the message field to +distinguish between events of the same class (for instance the button used in +a EVT_MOUSEDOWN event). + +If an event of the specified type was not in the event queue, the what field +of the event will be set to NULLEVT, and the return value will return false. + +Note: You should /always/ use the EVT_EVERYEVT mask for extracting events + from your main event loop handler. Using a mask for only a specific + type of event for long periods of time will cause the event queue to + fill up with events of the type you are ignoring, eventually causing + the application to hang when the event queue becomes full. + +SEE ALSO: +EVT_flush, EVT_halt, EVT_peekNext +****************************************************************************/ +ibool EVTAPI EVT_getNext( + event_t *evt, + ulong mask) +{ + int evtID,next,prev; + uint ps; + + if (EVT.heartBeat) + EVT.heartBeat(EVT.heartBeatParams); + _EVT_pumpMessages(); /* Pump all messages into queue */ + EVT.mouseMove(EVT.mx,EVT.my); /* Move the mouse cursor */ + evt->what = EVT_NULLEVT; /* Default to null event */ + if (EVT.count) { + /* It is possible that an event be posted while we are trying + * to access the event queue. This would create problems since + * we may end up with invalid data for our event queue pointers. To + * alleviate this, all interrupts are suspended while we manipulate + * our pointers. + */ + ps = _EVT_disableInt(); /* disable interrupts */ + for (evtID = EVT.head; evtID != -1; evtID = EVT.evtq[evtID].next) { + if (EVT.evtq[evtID].what & mask) + break; /* Found an event */ + } + if (evtID == -1) { + _EVT_restoreInt(ps); + return false; /* Event was not found */ + } + next = EVT.evtq[evtID].next; + prev = EVT.evtq[evtID].prev; + if (prev != -1) + EVT.evtq[prev].next = next; + else + EVT.head = next; + if (next != -1) + EVT.evtq[next].prev = prev; + else + EVT.tail = prev; + *evt = EVT.evtq[evtID]; /* Return the event */ + EVT.evtq[evtID].next = EVT.freeHead; /* and return to free list */ + EVT.freeHead = evtID; + EVT.count--; + if (evt->what == EVT_MOUSEMOVE) + EVT.oldMove = -1; + if (evt->what == EVT_KEYREPEAT) + EVT.oldKey = -1; + if (evt->what == EVT_JOYMOVE) + EVT.oldJoyMove = -1; + _EVT_restoreInt(ps); /* enable interrupts */ + if (evt->what & EVT_KEYEVT) + _EVT_maskKeyCode(evt); + } + + /* If there is no event pending, check if we should generate an auto + * mouse down event if the mouse is still currently down. + */ + if (evt->what == EVT_NULLEVT && EVT.autoRepeat && (mask & EVT_MOUSEAUTO) && (EVT.downMouse.what & EVT_MOUSEDOWN)) { + ulong ticks = _EVT_getTicks(); + if ((ticks - EVT.autoTicks) >= (EVT.autoRepeat + (EVT.firstAuto ? EVT.autoDelay : 0))) { + evt->what = EVT_MOUSEAUTO; + evt->message = EVT.downMouse.message; + evt->modifiers = EVT.downMouse.modifiers; + evt->where_x = EVT.autoMouse_x; + evt->where_y = EVT.autoMouse_y; + evt->relative_x = 0; + evt->relative_y = 0; + EVT.autoTicks = evt->when = ticks; + EVT.firstAuto = false; + } + } + return evt->what != EVT_NULLEVT; +} + +/**************************************************************************** +DESCRIPTION: +Installs a user supplied event filter callback for event handling. + +HEADER: +event.h + +PARAMETERS: +userEventFilter - Address of user supplied event filter callback + +REMARKS: +This function allows the application programmer to install an event filter +callback for event handling. Once you install your callback, the MGL +event handling routines will call your callback with a pointer to the +new event that will be placed into the event queue. Your callback can the +modify the contents of the event before it is placed into the queue (for +instance adding custom information or perhaps high precision timing +information). + +If your callback returns FALSE, the event will be ignore and will not be +posted to the event queue. You should always return true from your event +callback unless you plan to use the events immediately that they are +recieved. + +Note: Your event callback may be called in response to a hardware + interrupt and will be executing in the context of the hardware + interrupt handler under MSDOS (ie: keyboard interrupt or mouse + interrupt). For this reason the code pages for the callback that + you register must be locked in memory with the PM_lockCodePages + function. You must also lock down any data pages that your function + needs to reference as well. + +Note: You can also use this filter callback to process events at the + time they are activated by the user (ie: when the user hits the + key or moves the mouse), but make sure your code runs as fast as + possible as it will be executing inside the context of an interrupt + handler on some systems. + +SEE ALSO: +EVT_getNext, EVT_peekNext +****************************************************************************/ +void EVTAPI EVT_setUserEventFilter( + _EVT_userEventFilter filter) +{ + EVT.userEventCallback = filter; +} + +/**************************************************************************** +DESCRIPTION: +Installs a user supplied event heartbeat callback function. + +HEADER: +event.h + +PARAMETERS: +callback - Address of user supplied event heartbeat callback +params - Parameters to pass to the event heartbeat function + +REMARKS: +This function allows the application programmer to install an event heatbeat +function that gets called every time that EVT_getNext or EVT_peekNext +is called. This is primarily useful for simulating text mode cursors inside +event handling code when running in graphics modes as opposed to hardware +text modes. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_getHeartBeatCallback +****************************************************************************/ +void EVTAPI EVT_setHeartBeatCallback( + _EVT_heartBeatCallback callback, + void *params) +{ + EVT.heartBeat = callback; + EVT.heartBeatParams = params; +} + + +/**************************************************************************** +DESCRIPTION: +Returns the current user supplied event heartbeat callback function. + +HEADER: +event.h + +PARAMETERS: +callback - Place to store the address of user supplied event heartbeat callback +params - Place to store the parameters to pass to the event heartbeat function + +REMARKS: +This function retrieves the current event heatbeat function that gets called +every time that EVT_getNext or EVT_peekNext is called. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_setHeartBeatCallback +****************************************************************************/ +void EVTAPI EVT_getHeartBeatCallback( + _EVT_heartBeatCallback *callback, + void **params) +{ + *callback = EVT.heartBeat; + *params = EVT.heartBeatParams; +} + +/**************************************************************************** +DESCRIPTION: +Determines if a specified key is currently down. + +PARAMETERS: +scanCode - Scan code to test + +RETURNS: +True of the specified key is currently held down. + +HEADER: +event.h + +REMARKS: +This function determines if a specified key is currently down at the +time that the call is made. You simply need to pass in the scan code of +the key that you wish to test, and the MGL will tell you if it is currently +down or not. The MGL does this by keeping track of the up and down state +of all the keys. +****************************************************************************/ +ibool EVTAPI EVT_isKeyDown( + uchar scanCode) +{ + return _EVT_isKeyDown(scanCode); +} + +/**************************************************************************** +DESCRIPTION: +Set the mouse position for the event module + +PARAMETERS: +x - X coordinate to move the mouse cursor position to +y - Y coordinate to move the mouse cursor position to + +HEADER: +event.h + +REMARKS: +This function moves the mouse cursor position for the event module to the +specified location. + +SEE ALSO: +EVT_getMousePos +****************************************************************************/ +void EVTAPI EVT_setMousePos( + int x, + int y) +{ + EVT.mx = x; + EVT.my = y; + _EVT_setMousePos(&EVT.mx,&EVT.my); + EVT.mouseMove(EVT.mx,EVT.my); +} + +/**************************************************************************** +DESCRIPTION: +Returns the current mouse cursor location. + +HEADER: +event.h + +PARAMETERS: +x - Place to store value for mouse x coordinate (screen coordinates) +y - Place to store value for mouse y coordinate (screen coordinates) + +REMARKS: +Obtains the current mouse cursor position in screen coordinates. Normally the +mouse cursor location is tracked using the mouse movement events that are +posted to the event queue when the mouse moves, however this routine +provides an alternative method of polling the mouse cursor location. + +SEE ALSO: +EVT_setMousePos +****************************************************************************/ +void EVTAPI EVT_getMousePos( + int *x, + int *y) +{ + *x = EVT.mx; + *y = EVT.my; +} + +/**************************************************************************** +DESCRIPTION: +Returns the currently active code page for translation of keyboard characters. + +HEADER: +event.h + +RETURNS: +Pointer to the currently active code page translation table. + +REMARKS: +This function is returns a pointer to the currently active code page +translation table. See EVT_setCodePage for more information. + +SEE ALSO: +EVT_setCodePage +****************************************************************************/ +codepage_t * EVTAPI EVT_getCodePage(void) +{ + return EVT.codePage; +} + +/**************************************************************************** +DESCRIPTION: +Sets the currently active code page for translation of keyboard characters. + +HEADER: +event.h + +PARAMETERS: +page - New code page to make active + +REMARKS: +This function is used to set a new code page translation table that is used +to translate virtual scan code values to ASCII characters for different +keyboard configurations. The default is usually US English, although if +possible the PM library will auto-detect the correct code page translation +for the target OS if OS services are available to determine what type of +keyboard is currently attached. + +SEE ALSO: +EVT_getCodePage +****************************************************************************/ +void EVTAPI EVT_setCodePage( + codepage_t *page) +{ + EVT.codePage = page; +} + +/* The following contains fake C prototypes and documentation for the + * macro functions in the event.h header file. These exist soley so + * that DocJet will correctly pull in the documentation for these functions. + */ +#ifdef INCLUDE_DOC_FUNCTIONS + +/**************************************************************************** +DESCRIPTION: +Macro to extract the ASCII code from a message. + +PARAMETERS: +message - Message to extract ASCII code from + +RETURNS: +ASCII code extracted from the message. + +HEADER: +event.h + +REMARKS: +Macro to extract the ASCII code from the message field of the event_t +structure. You pass the message field to the macro as the parameter and +the ASCII code is the result, for example: + + event_t EVT.myEvent; + uchar code; + code = EVT_asciiCode(EVT.myEvent.message); + +SEE ALSO: +EVT_scanCode, EVT_repeatCount +****************************************************************************/ +uchar EVT_asciiCode( + ulong message); + +/**************************************************************************** +DESCRIPTION: +Macro to extract the keyboard scan code from a message. + +HEADER: +event.h + +PARAMETERS: +message - Message to extract scan code from + +RETURNS: +Keyboard scan code extracted from the message. + +REMARKS: +Macro to extract the keyboard scan code from the message field of the event +structure. You pass the message field to the macro as the parameter and +the scan code is the result, for example: + + event_t EVT.myEvent; + uchar code; + code = EVT_scanCode(EVT.myEvent.message); + +NOTE: Scan codes in the event library are not really hardware scan codes, + but rather virtual scan codes as generated by a low level keyboard + interface driver. All virtual scan code values are defined by the + EVT_scanCodesType enumeration, and will be identical across all + supports OS'es and platforms. + +SEE ALSO: +EVT_asciiCode, EVT_repeatCount +****************************************************************************/ +uchar EVT_scanCode( + ulong message); + +/**************************************************************************** +DESCRIPTION: +Macro to extract the repeat count from a message. + +HEADER: +event.h + +PARAMETERS: +message - Message to extract repeat count from + +RETURNS: +Repeat count extracted from the message. + +REMARKS: +Macro to extract the repeat count from the message field of the event +structure. The repeat count is the number of times that the key repeated +before there was another keyboard event to be place in the queue, and +allows the event handling code to avoid keyboard buffer overflow +conditions when a single key is held down by the user. If you are processing +a key repeat code, you will probably want to check this field to see how +many key repeats you should process for this message. + +SEE ALSO: +EVT_asciiCode, EVT_repeatCount +****************************************************************************/ +short EVT_repeatCount( + ulong message); + +#endif /* DOC FUNCTIONS */ + +#if defined(__REALDOS__) || defined(__SMX32__) +/* {secret} */ +void EVTAPI _EVT_cCodeEnd(void) {} +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c new file mode 100644 index 0000000..e88d210 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c @@ -0,0 +1,68 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: Linux specific code for the CPU detection module. +* +****************************************************************************/ + +#include + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +TODO: We should implement this for Linux! +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +TODO: We should implement this for Linux! +****************************************************************************/ +#define RestoreThreadPriority(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = 1000000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + struct timeval tv; \ + gettimeofday(&tv,NULL); \ + (t)->low = tv.tv_sec*1000000 + tv.tv_usec; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/event.c b/board/MAI/bios_emulator/scitech/src/pm/linux/event.c new file mode 100644 index 0000000..ce38732 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/event.c @@ -0,0 +1,1360 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: Linux fullscreen console implementation for the SciTech +* cross platform event library. +* Portions ripped straigth from the gpm source code for mouse +* handling. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +extern int _PM_console_fd; +static ushort keyUpMsg[256] = {0}; +static int _EVT_mouse_fd = 0; +static int range_x, range_y; +static int opt_baud = 1200, opt_sample = 100; +#ifdef USE_OS_JOYSTICK +static short *axis0 = NULL, *axis1 = NULL; +static uchar *buts0 = NULL, *buts1 = NULL; +static int joystick0_fd = 0, joystick1_fd = 0; +static int js_version = 0; +#endif + +/* This defines the supported mouse drivers */ + +typedef enum { + EVT_noMouse = -1, + EVT_microsoft = 0, + EVT_ps2, + EVT_mousesystems, + EVT_gpm, + EVT_MMseries, + EVT_logitech, + EVT_busmouse, + EVT_mouseman, + EVT_intellimouse, + EVT_intellimouse_ps2, + } mouse_drivers_t; + +static mouse_drivers_t mouse_driver = EVT_noMouse; +static char mouse_dev[20] = "/dev/mouse"; + +typedef struct { + char *name; + int flags; + void (*init)(void); + uchar proto[4]; + int packet_len; + int read; + } mouse_info; + +#define STD_FLG (CREAD | CLOCAL | HUPCL) + +static void _EVT_mouse_init(void); +static void _EVT_logitech_init(void); +static void _EVT_pnpmouse_init(void); + +mouse_info mouse_infos[] = { + {"Microsoft", CS7 | B1200 | STD_FLG, _EVT_mouse_init, {0x40, 0x40, 0x40, 0x00}, 3, 1}, + {"PS2", STD_FLG, NULL, {0xc0, 0x00, 0x00, 0x00}, 3, 1}, + {"MouseSystems", CS8 | CSTOPB | STD_FLG, _EVT_mouse_init, {0xf8, 0x80, 0x00, 0x00}, 5, 5}, + {"GPM", CS8 | CSTOPB | STD_FLG, NULL, {0xf8, 0x80, 0x00, 0x00}, 5, 5}, + {"MMSeries", CS8 | PARENB | PARODD | STD_FLG, _EVT_mouse_init, {0xe0, 0x80, 0x80, 0x00}, 3, 1}, + {"Logitech", CS8 | CSTOPB | STD_FLG, _EVT_logitech_init, {0xe0, 0x80, 0x80, 0x00}, 3, 3}, + {"BusMouse", STD_FLG, NULL, {0xf8, 0x80, 0x00, 0x00}, 3, 3}, + {"MouseMan", CS7 | STD_FLG, _EVT_mouse_init, {0x40, 0x40, 0x40, 0x00}, 3, 1}, + {"IntelliMouse", CS7 | STD_FLG, _EVT_pnpmouse_init, {0xc0, 0x40, 0xc0, 0x00}, 4, 1}, + {"IMPS2", CS7 | STD_FLG, NULL, {0xc0, 0x40, 0xc0, 0x00}, 4, 1}, /* ? */ + }; + +#define NB_MICE (sizeof(mouse_infos)/sizeof(mouse_info)) + +/* The name of the environment variables that are used to change the defaults above */ + +#define ENV_MOUSEDRV "MGL_MOUSEDRV" +#define ENV_MOUSEDEV "MGL_MOUSEDEV" +#define ENV_MOUSESPD "MGL_MOUSESPD" +#define ENV_JOYDEV0 "MGL_JOYDEV1" +#define ENV_JOYDEV1 "MGL_JOYDEV2" + +/* Scancode mappings on Linux for special keys */ + +typedef struct { + int scan; + int map; + } keymap; + +/* TODO: Fix this and set it up so we can do a binary search! */ + +keymap keymaps[] = { + {96, KB_padEnter}, + {74, KB_padMinus}, + {78, KB_padPlus}, + {55, KB_padTimes}, + {98, KB_padDivide}, + {71, KB_padHome}, + {72, KB_padUp}, + {73, KB_padPageUp}, + {75, KB_padLeft}, + {76, KB_padCenter}, + {77, KB_padRight}, + {79, KB_padEnd}, + {80, KB_padDown}, + {81, KB_padPageDown}, + {82, KB_padInsert}, + {83, KB_padDelete}, + {105,KB_left}, + {108,KB_down}, + {106,KB_right}, + {103,KB_up}, + {110,KB_insert}, + {102,KB_home}, + {104,KB_pageUp}, + {111,KB_delete}, + {107,KB_end}, + {109,KB_pageDown}, + {125,KB_leftWindows}, + {126,KB_rightWindows}, + {127,KB_menu}, + {100,KB_rightAlt}, + {97,KB_rightCtrl}, + }; + +/* And the keypad with num lock turned on (changes the ASCII code only) */ + +keymap keypad[] = { + {71, ASCII_7}, + {72, ASCII_8}, + {73, ASCII_9}, + {75, ASCII_4}, + {76, ASCII_5}, + {77, ASCII_6}, + {79, ASCII_1}, + {80, ASCII_2}, + {81, ASCII_3}, + {82, ASCII_0}, + {83, ASCII_period}, + }; + +#define NB_KEYMAPS (sizeof(keymaps)/sizeof(keymaps[0])) +#define NB_KEYPAD (sizeof(keypad)/sizeof(keypad[0])) + +typedef struct { + int sample; + char code[2]; + } sample_rate; + +sample_rate sampletab[]={ + { 0,"O"}, + { 15,"J"}, + { 27,"K"}, + { 42,"L"}, + { 60,"R"}, + { 85,"M"}, + {125,"Q"}, + {1E9,"N"}, + }; + +/* Number of keycodes to read at a time from the console */ + +#define KBDREADBUFFERSIZE 32 + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under Linux */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flaps) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + static uint starttime = 0; + struct timeval t; + + gettimeofday(&t, NULL); + if (starttime == 0) + starttime = t.tv_sec * 1000 + (t.tv_usec/1000); + return ((t.tv_sec * 1000 + (t.tv_usec/1000)) - starttime); +} + +/**************************************************************************** +REMARKS: +Small Unix function that checks for availability on a file using select() +****************************************************************************/ +static ibool dataReady( + int fd) +{ + static struct timeval t = { 0L, 0L }; + fd_set fds; + + FD_ZERO(&fds); + FD_SET(fd, &fds); + return select(fd+1, &fds, NULL, NULL, &t) > 0; +} + +/**************************************************************************** +REMARKS: +Reads mouse data according to the selected mouse driver. +****************************************************************************/ +static ibool readMouseData( + int *buttons, + int *dx, + int *dy) +{ + static uchar data[32],prev = 0; + int cnt = 0,ret; + mouse_info *drv; + + /* Read the first byte to check for the protocol */ + drv = &mouse_infos[mouse_driver]; + if (read(_EVT_mouse_fd, data, drv->read) != drv->read) { + perror("read"); + return false; + } + if ((data[0] & drv->proto[0]) != drv->proto[1]) + return false; + + /* Load a whole protocol packet */ + cnt += drv->read; + while (cnt < drv->packet_len) { + ret = read(_EVT_mouse_fd, data+cnt, drv->read); + if (ret == drv->read) + cnt += ret; + else { + perror("read"); + return false; + } + } + if ((data[1] & drv->proto[2]) != drv->proto[3]) + return false; + + /* Now decode the protocol packet */ + switch (mouse_driver) { + case EVT_microsoft: + if (data[0] == 0x40 && !(prev|data[1]|data[2])) + *buttons = 2; /* Third button on MS compatible mouse */ + else + *buttons= ((data[0] & 0x20) >> 3) | ((data[0] & 0x10) >> 4); + prev = *buttons; + *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F)); + *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F)); + break; + case EVT_ps2: + *buttons = !!(data[0]&1) * 4 + !!(data[0]&2) * 1 + !!(data[0]&4) * 2; + if (data[1] != 0) + *dx = (data[0] & 0x10) ? data[1]-256 : data[1]; + else + *dx = 0; + if (data[2] != 0) + *dy = -((data[0] & 0x20) ? data[2]-256 : data[2]); + else + *dy = 0; + break; + case EVT_mousesystems: case EVT_gpm: + *buttons = (~data[0]) & 0x07; + *dx = (char)(data[1]) + (char)(data[3]); + *dy = -((char)(data[2]) + (char)(data[4])); + break; + case EVT_logitech: + *buttons= data[0] & 0x07; + *dx = (data[0] & 0x10) ? data[1] : - data[1]; + *dy = (data[0] & 0x08) ? - data[2] : data[2]; + break; + case EVT_busmouse: + *buttons= (~data[0]) & 0x07; + *dx = (char)data[1]; + *dy = -(char)data[2]; + break; + case EVT_MMseries: + *buttons = data[0] & 0x07; + *dx = (data[0] & 0x10) ? data[1] : - data[1]; + *dy = (data[0] & 0x08) ? - data[2] : data[2]; + break; + case EVT_intellimouse: + *buttons = ((data[0] & 0x20) >> 3) /* left */ + | ((data[3] & 0x10) >> 3) /* middle */ + | ((data[0] & 0x10) >> 4); /* right */ + *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F)); + *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F)); + break; + case EVT_intellimouse_ps2: + *buttons = (data[0] & 0x04) >> 1 /* Middle */ + | (data[0] & 0x02) >> 1 /* Right */ + | (data[0] & 0x01) << 2; /* Left */ + *dx = (data[0] & 0x10) ? data[1]-256 : data[1]; + *dy = (data[0] & 0x20) ? -(data[2]-256) : -data[2]; + break; + case EVT_mouseman: { + static int getextra; + static uchar prev=0; + uchar b; + + /* The damned MouseMan has 3/4 bytes packets. The extra byte + * is only there if the middle button is active. + * I get the extra byte as a packet with magic numbers in it. + * and then switch to 4-byte mode. + */ + if (data[1] == 0xAA && data[2] == 0x55) { + /* Got unexpected fourth byte */ + if ((b = (*data>>4)) > 0x3) + return false; /* just a sanity check */ + *dx = *dy = 0; + drv->packet_len=4; + getextra=0; + } + else { + /* Got 3/4, as expected */ + /* Motion is independent of packetlen... */ + *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F)); + *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F)); + prev = ((data[0] & 0x20) >> 3) | ((data[0] & 0x10) >> 4); + if (drv->packet_len==4) + b = data[3]>>4; + } + if (drv->packet_len == 4) { + if (b == 0) { + drv->packet_len = 3; + getextra = 1; + } + else { + if (b & 0x2) + prev |= 2; + } + } + *buttons = prev; + + /* This "chord-middle" behaviour was reported by David A. van Leeuwen */ + if (((prev ^ *buttons) & 5) == 5) + *buttons = *buttons ? 2 : 0; + prev = *buttons; + break; + } + case EVT_noMouse: + return false; + break; + } + return true; +} + +/**************************************************************************** +REMARKS: +Map a keypress via the key mapping table +****************************************************************************/ +static int getKeyMapping( + keymap *tab, + int nb, + int key) +{ + int i; + + for(i = 0; i < nb; i++) { + if (tab[i].scan == key) + return tab[i].map; + } + return key; +} + +#ifdef USE_OS_JOYSTICK + +static char js0_axes = 0, js0_buttons = 0; +static char js1_axes = 0, js1_buttons = 0; +static char joystick0_dev[20] = "/dev/js0"; +static char joystick1_dev[20] = "/dev/js1"; + +/**************************************************************************** +REMARKS: +Create a joystick event from the joystick data +****************************************************************************/ +static void makeJoyEvent( + event_t *evt) +{ + evt->message = 0; + if (buts0 && axis0) { + if (buts0[0]) evt->message |= EVT_JOY1_BUTTONA; + if (buts0[1]) evt->message |= EVT_JOY1_BUTTONB; + evt->where_x = axis0[0]; + evt->where_y = axis0[1]; + } + else + evt->where_x = evt->where_y = 0; + if (buts1 && axis1) { + if (buts1[0]) evt->message |= EVT_JOY2_BUTTONA; + if (buts1[1]) evt->message |= EVT_JOY2_BUTTONB; + evt->where_x = axis1[0]; + evt->where_y = axis1[1]; + } + else + evt->where_x = evt->where_y = 0; +} + +/**************************************************************************** +REMARKS: +Read the joystick axis data +****************************************************************************/ +int EVTAPI _EVT_readJoyAxis( + int jmask, + int *axis) +{ + int mask = 0; + + if ((js_version & ~0xffff) == 0) { + /* Old 0.x driver */ + struct JS_DATA_TYPE js; + if (joystick0_fd && read(joystick0_fd, &js, JS_RETURN) == JS_RETURN) { + if (jmask & EVT_JOY_AXIS_X1) + axis[0] = js.x; + if (jmask & EVT_JOY_AXIS_Y1) + axis[1] = js.y; + mask |= EVT_JOY_AXIS_X1|EVT_JOY_AXIS_Y1; + } + if (joystick1_fd && read(joystick1_fd, &js, JS_RETURN) == JS_RETURN) { + if (jmask & EVT_JOY_AXIS_X2) + axis[2] = js.x; + if (jmask & EVT_JOY_AXIS_Y2) + axis[3] = js.y; + mask |= EVT_JOY_AXIS_X2|EVT_JOY_AXIS_Y2; + } + } + else { + if (axis0) { + if (jmask & EVT_JOY_AXIS_X1) + axis[0] = axis0[0]; + if (jmask & EVT_JOY_AXIS_Y1) + axis[1] = axis0[1]; + mask |= EVT_JOY_AXIS_X1 | EVT_JOY_AXIS_Y1; + } + if (axis1) { + if (jmask & EVT_JOY_AXIS_X2) + axis[2] = axis1[0]; + if (jmask & EVT_JOY_AXIS_Y2) + axis[3] = axis1[1]; + mask |= EVT_JOY_AXIS_X2 | EVT_JOY_AXIS_Y2; + } + } + return mask; +} + +/**************************************************************************** +REMARKS: +Read the joystick button data +****************************************************************************/ +int EVTAPI _EVT_readJoyButtons(void) +{ + int buts = 0; + + if ((js_version & ~0xffff) == 0) { + /* Old 0.x driver */ + struct JS_DATA_TYPE js; + if (joystick0_fd && read(joystick0_fd, &js, JS_RETURN) == JS_RETURN) + buts = js.buttons; + if (joystick1_fd && read(joystick1_fd, &js, JS_RETURN) == JS_RETURN) + buts |= js.buttons << 2; + } + else { + if (buts0) + buts |= EVT_JOY1_BUTTONA*buts0[0] + EVT_JOY1_BUTTONB*buts0[1]; + if (buts1) + buts |= EVT_JOY2_BUTTONA*buts1[0] + EVT_JOY2_BUTTONB*buts1[1]; + } + return buts; +} + +/**************************************************************************** +DESCRIPTION: +Returns the mask indicating what joystick axes are attached. + +HEADER: +event.h + +REMARKS: +This function is used to detect the attached joysticks, and determine +what axes are present and functioning. This function will re-detect any +attached joysticks when it is called, so if the user forgot to attach +the joystick when the application started, you can call this function to +re-detect any newly attached joysticks. + +SEE ALSO: +EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +int EVTAPI EVT_joyIsPresent(void) +{ + static int mask = 0; + int i; + char *tmp, name0[128], name1[128]; + static ibool inited = false; + + if (inited) + return mask; + memset(EVT.joyMin,0,sizeof(EVT.joyMin)); + memset(EVT.joyCenter,0,sizeof(EVT.joyCenter)); + memset(EVT.joyMax,0,sizeof(EVT.joyMax)); + memset(EVT.joyPrev,0,sizeof(EVT.joyPrev)); + EVT.joyButState = 0; + if ((tmp = getenv(ENV_JOYDEV0)) != NULL) + strcpy(joystick0_dev,tmp); + if ((tmp = getenv(ENV_JOYDEV1)) != NULL) + strcpy(joystick1_dev,tmp); + if ((joystick0_fd = open(joystick0_dev, O_RDONLY)) < 0) + joystick0_fd = 0; + if ((joystick1_fd = open(joystick1_dev, O_RDONLY)) < 0) + joystick1_fd = 0; + if (!joystick0_fd && !joystick1_fd) /* No joysticks detected */ + return 0; + inited = true; + if (ioctl(joystick0_fd ? joystick0_fd : joystick1_fd, JSIOCGVERSION, &js_version) < 0) + return 0; + + /* Initialise joystick 0 */ + if (joystick0_fd) { + ioctl(joystick0_fd, JSIOCGNAME(sizeof(name0)), name0); + if (js_version & ~0xffff) { + struct js_event js; + + ioctl(joystick0_fd, JSIOCGAXES, &js0_axes); + ioctl(joystick0_fd, JSIOCGBUTTONS, &js0_buttons); + axis0 = PM_calloc((int)js0_axes, sizeof(short)); + buts0 = PM_malloc((int)js0_buttons); + /* Read the initial events */ + while(dataReady(joystick0_fd) + && read(joystick0_fd, &js, sizeof(struct js_event)) == sizeof(struct js_event) + && (js.type & JS_EVENT_INIT) + ) { + if (js.type & JS_EVENT_BUTTON) + buts0[js.number] = js.value; + else if (js.type & JS_EVENT_AXIS) + axis0[js.number] = scaleJoyAxis(js.value,js.number); + } + } + else { + js0_axes = 2; + js0_buttons = 2; + axis0 = PM_calloc((int)js0_axes, sizeof(short)); + buts0 = PM_malloc((int)js0_buttons); + } + } + + /* Initialise joystick 1 */ + if (joystick1_fd) { + ioctl(joystick1_fd, JSIOCGNAME(sizeof(name1)), name1); + if (js_version & ~0xffff) { + struct js_event js; + + ioctl(joystick1_fd, JSIOCGAXES, &js1_axes); + ioctl(joystick1_fd, JSIOCGBUTTONS, &js1_buttons); + axis1 = PM_calloc((int)js1_axes, sizeof(short)); + buts1 = PM_malloc((int)js1_buttons); + /* Read the initial events */ + while(dataReady(joystick1_fd) + && read(joystick1_fd, &js, sizeof(struct js_event))==sizeof(struct js_event) + && (js.type & JS_EVENT_INIT) + ) { + if (js.type & JS_EVENT_BUTTON) + buts1[js.number] = js.value; + else if (js.type & JS_EVENT_AXIS) + axis1[js.number] = scaleJoyAxis(js.value,js.number<<2); + } + } + else { + js1_axes = 2; + js1_buttons = 2; + axis1 = PM_calloc((int)js1_axes, sizeof(short)); + buts1 = PM_malloc((int)js1_buttons); + } + } + +#ifdef CHECKED + fprintf(stderr,"Using joystick driver version %d.%d.%d\n", + js_version >> 16, (js_version >> 8) & 0xff, js_version & 0xff); + if (joystick0_fd) + fprintf(stderr,"Joystick 1 (%s): %s\n", joystick0_dev, name0); + if (joystick1_fd) + fprintf(stderr,"Joystick 2 (%s): %s\n", joystick1_dev, name1); +#endif + mask = _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); + if (mask) { + for (i = 0; i < JOY_NUM_AXES; i++) + EVT.joyMax[i] = EVT.joyCenter[i]*2; + } + return mask; +} + +/**************************************************************************** +DESCRIPTION: +Polls the joystick for position and button information. + +HEADER: +event.h + +REMARKS: +This routine is used to poll analogue joysticks for button and position +information. It should be called once for each main loop of the user +application, just before processing all pending events via EVT_getNext. +All information polled from the joystick will be posted to the event +queue for later retrieval. + +Note: Most analogue joysticks will provide readings that change even + though the joystick has not moved. Hence if you call this routine + you will likely get an EVT_JOYMOVE event every time through your + event loop. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight, +EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_pollJoystick(void) +{ + event_t evt; + int i,axis[JOY_NUM_AXES],newButState,mask,moved,ps; + + if ((js_version & ~0xFFFF) == 0 && EVT.joyMask) { + /* Read joystick axes and post movement events if they have + * changed since the last time we polled. Until the events are + * actually flushed, we keep modifying the same joystick movement + * event, so you won't get multiple movement event + */ + mask = _EVT_readJoyAxis(EVT.joyMask,axis); + newButState = _EVT_readJoyButtons(); + moved = false; + for (i = 0; i < JOY_NUM_AXES; i++) { + if (mask & (EVT_JOY_AXIS_X1 << i)) + axis[i] = scaleJoyAxis(axis[i],i); + else + axis[i] = EVT.joyPrev[i]; + if (axis[i] != EVT.joyPrev[i]) + moved = true; + } + if (moved) { + memcpy(EVT.joyPrev,axis,sizeof(EVT.joyPrev)); + ps = _EVT_disableInt(); + if (EVT.oldJoyMove != -1) { + /* Modify the existing joystick movement event */ + EVT.evtq[EVT.oldJoyMove].message = newButState; + EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; + EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; + EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; + EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; + } + else if (EVT.count < EVENTQSIZE) { + /* Add a new joystick movement event */ + EVT.oldJoyMove = EVT.freeHead; + memset(&evt,0,sizeof(evt)); + evt.what = EVT_JOYMOVE; + evt.message = EVT.joyButState; + evt.where_x = EVT.joyPrev[0]; + evt.where_y = EVT.joyPrev[1]; + evt.relative_x = EVT.joyPrev[2]; + evt.relative_y = EVT.joyPrev[3]; + addEvent(&evt); + } + _EVT_restoreInt(ps); + } + + /* Read the joystick buttons, and post events to reflect the change + * in state for the joystick buttons. + */ + if (newButState != EVT.joyButState) { + if (EVT.count < EVENTQSIZE) { + /* Add a new joystick movement event */ + ps = _EVT_disableInt(); + memset(&evt,0,sizeof(evt)); + evt.what = EVT_JOYCLICK; + evt.message = newButState; + EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; + EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; + EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; + EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; + addEvent(&evt); + _EVT_restoreInt(ps); + } + EVT.joyButState = newButState; + } + } +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick upper left position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the upper left +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetUpperLeft(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMin); +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick lower right position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the lower right +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetLowerRight(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMax); +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick center position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the center +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter +****************************************************************************/ +void EVTAPI EVT_joySetCenter(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); +} +#endif + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from Linux into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + event_t evt; + int i,numkeys, c; + ibool release; + static struct kbentry ke; + static char buf[KBDREADBUFFERSIZE]; + static ushort repeatKey[128] = {0}; + + /* Poll keyboard events */ + while (dataReady(_PM_console_fd) && (numkeys = read(_PM_console_fd, buf, KBDREADBUFFERSIZE)) > 0) { + for (i = 0; i < numkeys; i++) { + c = buf[i]; + release = c & 0x80; + c &= 0x7F; + + /* TODO: This is wrong! We need this to be the time stamp at */ + /* ** interrupt ** time!! One solution would be to */ + /* put the keyboard and mouse polling loops into */ + /* a separate thread that can block on I/O to the */ + /* necessay file descriptor. */ + evt.when = _EVT_getTicks(); + + if (release) { + /* Key released */ + evt.what = EVT_KEYUP; + switch (c) { + case KB_leftShift: + _PM_modifiers &= ~EVT_LEFTSHIFT; + break; + case KB_rightShift: + _PM_modifiers &= ~EVT_RIGHTSHIFT; + break; + case 29: + _PM_modifiers &= ~(EVT_LEFTCTRL|EVT_CTRLSTATE); + break; + case 97: /* Control */ + _PM_modifiers &= ~EVT_CTRLSTATE; + break; + case 56: + _PM_modifiers &= ~(EVT_LEFTALT|EVT_ALTSTATE); + break; + case 100: + _PM_modifiers &= ~EVT_ALTSTATE; + break; + default: + } + evt.modifiers = _PM_modifiers; + evt.message = keyUpMsg[c]; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + keyUpMsg[c] = 0; + repeatKey[c] = 0; + } + else { + /* Key pressed */ + evt.what = EVT_KEYDOWN; + switch (c) { + case KB_leftShift: + _PM_modifiers |= EVT_LEFTSHIFT; + break; + case KB_rightShift: + _PM_modifiers |= EVT_RIGHTSHIFT; + break; + case 29: + _PM_modifiers |= EVT_LEFTCTRL|EVT_CTRLSTATE; + break; + case 97: /* Control */ + _PM_modifiers |= EVT_CTRLSTATE; + break; + case 56: + _PM_modifiers |= EVT_LEFTALT|EVT_ALTSTATE; + break; + case 100: + _PM_modifiers |= EVT_ALTSTATE; + break; + case KB_capsLock: /* Caps Lock */ + _PM_leds ^= LED_CAP; + ioctl(_PM_console_fd, KDSETLED, _PM_leds); + break; + case KB_numLock: /* Num Lock */ + _PM_leds ^= LED_NUM; + ioctl(_PM_console_fd, KDSETLED, _PM_leds); + break; + case KB_scrollLock: /* Scroll Lock */ + _PM_leds ^= LED_SCR; + ioctl(_PM_console_fd, KDSETLED, _PM_leds); + break; + default: + } + evt.modifiers = _PM_modifiers; + if (keyUpMsg[c]) { + evt.what = EVT_KEYREPEAT; + evt.message = keyUpMsg[c] | (repeatKey[c]++ << 16); + } + else { + int asc; + + evt.message = getKeyMapping(keymaps, NB_KEYMAPS, c) << 8; + ke.kb_index = c; + ke.kb_table = 0; + if ((_PM_modifiers & EVT_SHIFTKEY) || (_PM_leds & LED_CAP)) + ke.kb_table |= K_SHIFTTAB; + if (_PM_modifiers & (EVT_LEFTALT | EVT_ALTSTATE)) + ke.kb_table |= K_ALTTAB; + if (ioctl(_PM_console_fd, KDGKBENT, (unsigned long)&ke)<0) + perror("ioctl(KDGKBENT)"); + if ((_PM_leds & LED_NUM) && (getKeyMapping(keypad, NB_KEYPAD, c)!=c)) { + asc = getKeyMapping(keypad, NB_KEYPAD, c); + } + else { + switch (c) { + case 14: + asc = ASCII_backspace; + break; + case 15: + asc = ASCII_tab; + break; + case 28: + case 96: + asc = ASCII_enter; + break; + case 1: + asc = ASCII_esc; + default: + asc = ke.kb_value & 0xFF; + if (asc < 0x1B) + asc = 0; + break; + } + } + if ((_PM_modifiers & (EVT_CTRLSTATE|EVT_LEFTCTRL)) && isalpha(asc)) + evt.message |= toupper(asc) - 'A' + 1; + else + evt.message |= asc; + keyUpMsg[c] = evt.message; + repeatKey[c]++; + } + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + } + + /* Poll mouse events */ + if (_EVT_mouse_fd) { + int dx, dy, buts; + static int oldbuts; + + while (dataReady(_EVT_mouse_fd)) { + if (readMouseData(&buts, &dx, &dy)) { + EVT.mx += dx; + EVT.my += dy; + if (EVT.mx < 0) EVT.mx = 0; + if (EVT.my < 0) EVT.my = 0; + if (EVT.mx > range_x) EVT.mx = range_x; + if (EVT.my > range_y) EVT.my = range_y; + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = dx; + evt.relative_y = dy; + + /* TODO: This is wrong! We need this to be the time stamp at */ + /* ** interrupt ** time!! One solution would be to */ + /* put the keyboard and mouse polling loops into */ + /* a separate thread that can block on I/O to the */ + /* necessay file descriptor. */ + evt.when = _EVT_getTicks(); + evt.modifiers = _PM_modifiers; + if (buts & 4) + evt.modifiers |= EVT_LEFTBUT; + if (buts & 1) + evt.modifiers |= EVT_RIGHTBUT; + if (buts & 2) + evt.modifiers |= EVT_MIDDLEBUT; + + /* Left click events */ + if ((buts&4) != (oldbuts&4)) { + if (buts&4) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_LEFTBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Right click events */ + if ((buts&1) != (oldbuts&1)) { + if (buts&1) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_RIGHTBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Middle click events */ + if ((buts&2) != (oldbuts&2)) { + if (buts&2) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_MIDDLEBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Mouse movement event */ + if (dx || dy) { + evt.what = EVT_MOUSEMOVE; + evt.message = 0; + if (EVT.oldMove != -1) { + /* Modify existing movement event */ + EVT.evtq[EVT.oldMove].where_x = evt.where_x; + EVT.evtq[EVT.oldMove].where_y = evt.where_y; + } + else { + /* Save id of this movement event */ + EVT.oldMove = EVT.freeHead; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + oldbuts = buts; + } + } + } + +#ifdef USE_OS_JOYSTICK + /* Poll joystick events using the 1.x joystick driver API in the 2.2 kernels */ + if (js_version & ~0xffff) { + static struct js_event js; + + /* Read joystick axis 0 */ + evt.when = 0; + evt.modifiers = _PM_modifiers; + if (joystick0_fd && dataReady(joystick0_fd) && + read(joystick0_fd, &js, sizeof(js)) == sizeof(js)) { + if (js.type & JS_EVENT_BUTTON) { + if (js.number < 2) { /* Only 2 buttons for now :( */ + buts0[js.number] = js.value; + evt.what = EVT_JOYCLICK; + makeJoyEvent(&evt); + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + else if (js.type & JS_EVENT_AXIS) { + axis0[js.number] = scaleJoyAxis(js.value,js.number); + evt.what = EVT_JOYMOVE; + if (EVT.oldJoyMove != -1) { + makeJoyEvent(&EVT.evtq[EVT.oldJoyMove]); + } + else if (EVT.count < EVENTQSIZE) { + EVT.oldJoyMove = EVT.freeHead; + makeJoyEvent(&evt); + addEvent(&evt); + } + } + } + + /* Read joystick axis 1 */ + if (joystick1_fd && dataReady(joystick1_fd) && + read(joystick1_fd, &js, sizeof(js))==sizeof(js)) { + if (js.type & JS_EVENT_BUTTON) { + if (js.number < 2) { /* Only 2 buttons for now :( */ + buts1[js.number] = js.value; + evt.what = EVT_JOYCLICK; + makeJoyEvent(&evt); + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + else if (js.type & JS_EVENT_AXIS) { + axis1[js.number] = scaleJoyAxis(js.value,js.number<<2); + evt.what = EVT_JOYMOVE; + if (EVT.oldJoyMove != -1) { + makeJoyEvent(&EVT.evtq[EVT.oldJoyMove]); + } + else if (EVT.count < EVENTQSIZE) { + EVT.oldJoyMove = EVT.freeHead; + makeJoyEvent(&evt); + addEvent(&evt); + } + } + } + } +#endif +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift _PM_modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Set the speed of the serial port +****************************************************************************/ +static int setspeed( + int fd, + int old, + int new, + unsigned short flags) +{ + struct termios tty; + char *c; + + tcgetattr(fd, &tty); + tty.c_iflag = IGNBRK | IGNPAR; + tty.c_oflag = 0; + tty.c_lflag = 0; + tty.c_line = 0; + tty.c_cc[VTIME] = 0; + tty.c_cc[VMIN] = 1; + switch (old) { + case 9600: tty.c_cflag = flags | B9600; break; + case 4800: tty.c_cflag = flags | B4800; break; + case 2400: tty.c_cflag = flags | B2400; break; + case 1200: + default: tty.c_cflag = flags | B1200; break; + } + tcsetattr(fd, TCSAFLUSH, &tty); + switch (new) { + case 9600: c = "*q"; tty.c_cflag = flags | B9600; break; + case 4800: c = "*p"; tty.c_cflag = flags | B4800; break; + case 2400: c = "*o"; tty.c_cflag = flags | B2400; break; + case 1200: + default: c = "*n"; tty.c_cflag = flags | B1200; break; + } + write(fd, c, 2); + usleep(100000); + tcsetattr(fd, TCSAFLUSH, &tty); + return 0; +} + +/**************************************************************************** +REMARKS: +Generic mouse driver init code +****************************************************************************/ +static void _EVT_mouse_init(void) +{ + int i; + + /* Change from any available speed to the chosen one */ + for (i = 9600; i >= 1200; i /= 2) + setspeed(_EVT_mouse_fd, i, opt_baud, mouse_infos[mouse_driver].flags); +} + +/**************************************************************************** +REMARKS: +Logitech mouse driver init code +****************************************************************************/ +static void _EVT_logitech_init(void) +{ + int i; + struct stat buf; + int busmouse; + + /* is this a serial- or a bus- mouse? */ + if (fstat(_EVT_mouse_fd,&buf) == -1) + perror("fstat"); + i = MAJOR(buf.st_rdev); + if (stat("/dev/ttyS0",&buf) == -1) + perror("stat"); + busmouse=(i != MAJOR(buf.st_rdev)); + + /* Fix the howmany field, so that serial mice have 1, while busmice have 3 */ + mouse_infos[mouse_driver].read = busmouse ? 3 : 1; + + /* Change from any available speed to the chosen one */ + for (i = 9600; i >= 1200; i /= 2) + setspeed(_EVT_mouse_fd, i, opt_baud, mouse_infos[mouse_driver].flags); + + /* This stuff is peculiar of logitech mice, also for the serial ones */ + write(_EVT_mouse_fd, "S", 1); + setspeed(_EVT_mouse_fd, opt_baud, opt_baud,CS8 |PARENB |PARODD |CREAD |CLOCAL |HUPCL); + + /* Configure the sample rate */ + for (i = 0; opt_sample <= sampletab[i].sample; i++) + ; + write(_EVT_mouse_fd,sampletab[i].code,1); +} + +/**************************************************************************** +REMARKS: +Microsoft Intellimouse init code +****************************************************************************/ +static void _EVT_pnpmouse_init(void) +{ + struct termios tty; + + tcgetattr(_EVT_mouse_fd, &tty); + tty.c_iflag = IGNBRK | IGNPAR; + tty.c_oflag = 0; + tty.c_lflag = 0; + tty.c_line = 0; + tty.c_cc[VTIME] = 0; + tty.c_cc[VMIN] = 1; + tty.c_cflag = mouse_infos[mouse_driver].flags | B1200; + tcsetattr(_EVT_mouse_fd, TCSAFLUSH, &tty); /* set parameters */ +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + char *tmp; + + /* Initialise the event queue */ + EVT.mouseMove = mouseMove; + initEventQueue(); + for (i = 0; i < 256; i++) + keyUpMsg[i] = 0; + + /* Keyboard initialization */ + if (_PM_console_fd == -1) + PM_fatalError("You must first call PM_openConsole to use the EVT functions!"); + _PM_keyboard_rawmode(); + fcntl(_PM_console_fd,F_SETFL,fcntl(_PM_console_fd,F_GETFL) | O_NONBLOCK); + + /* Mouse initialization */ + if ((tmp = getenv(ENV_MOUSEDRV)) != NULL) { + for (i = 0; i < NB_MICE; i++) { + if (!strcasecmp(tmp, mouse_infos[i].name)) { + mouse_driver = i; + break; + } + } + if (i == NB_MICE) { + fprintf(stderr,"Unknown mouse driver: %s\n", tmp); + mouse_driver = EVT_noMouse; + _EVT_mouse_fd = 0; + } + } + if (mouse_driver != EVT_noMouse) { + if (mouse_driver == EVT_gpm) + strcpy(mouse_dev,"/dev/gpmdata"); + if ((tmp = getenv(ENV_MOUSEDEV)) != NULL) + strcpy(mouse_dev,tmp); +#ifdef CHECKED + fprintf(stderr,"Using the %s MGL mouse driver on %s.\n", mouse_infos[mouse_driver].name, mouse_dev); +#endif + if ((_EVT_mouse_fd = open(mouse_dev, O_RDWR)) < 0) { + perror("open"); + fprintf(stderr, "Unable to open mouse device %s, dropping mouse support.\n", mouse_dev); + sleep(1); + mouse_driver = EVT_noMouse; + _EVT_mouse_fd = 0; + } + else { + char c; + + /* Init and flush the mouse pending input queue */ + if (mouse_infos[mouse_driver].init) + mouse_infos[mouse_driver].init(); + while(dataReady(_EVT_mouse_fd) && read(_EVT_mouse_fd, &c, 1) == 1) + ; + } + } +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + range_x = xRes; + range_y = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +#define _EVT_setMousePos(x,y) + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for Linux */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for Linux */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + _PM_restore_kb_mode(); + if (_EVT_mouse_fd) { + close(_EVT_mouse_fd); + _EVT_mouse_fd = 0; + } +#ifdef USE_OS_JOYSTICK + if (joystick0_fd) { + close(joystick0_fd); + free(axis0); + free(buts0); + joystick0_fd = 0; + } + if (joystick1_fd) { + close(joystick1_fd); + free(axis1); + free(buts1); + joystick1_fd = 0; + } +#endif +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga b/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga new file mode 100644 index 0000000..c0358a0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga @@ -0,0 +1,1058 @@ +/**************************************************************************** +* +* The SuperVGA Kit - UniVBE Software Development Kit +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: IBM PC (MS DOS) +* +* Description: Routines to provide a Linux event queue, which automatically +* handles keyboard and mouse events for the Linux compatability +* libraries. Based on the event handling code in the MGL. +* +****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pm.h" +#include "vesavbe.h" +#include "wdirect.h" + +/*--------------------------- Global variables ----------------------------*/ + +#define EVENTQSIZE 100 /* Number of events in event queue */ + +static int head = -1; /* Head of event queue */ +static int tail = -1; /* Tail of event queue */ +static int freeHead = -1; /* Head of free list */ +static int count = 0; /* No. of items currently in queue */ +static WD_event evtq[EVENTQSIZE]; /* The queue structure itself */ +static int oldMove = -1; /* Previous movement event */ +static int oldKey = -1; /* Previous key repeat event */ +static int mx,my; /* Current mouse position */ +static int xRes,yRes; /* Screen resolution coordinates */ +static void *stateBuf; /* Pointer to console state buffer */ +static int conn; /* GPM file descriptor for mouse handling */ +static int tty_fd; /* File descriptor for /dev/console */ +extern int tty_vc; /* Virtual console ID, from the PM/Pro library */ +static ibool key_down[128]; /* State of all keyboard keys */ +static struct termios old_conf; /* Saved terminal configuration */ +static int oldkbmode; /* and previous keyboard mode */ +struct vt_mode oldvtmode; /* Old virtual terminal mode */ +static int old_flags; /* Old flags for fcntl */ +static ulong key_modifiers; /* Keyboard modifiers */ +static int forbid_vt_release=0;/* Flag to forbid release of VT */ +static int forbid_vt_acquire=0;/* Flag to forbid cature of VT */ +static int oldmode; /* Old SVGA mode saved for VT switch*/ +static int initmode; /* Initial text mode */ +static ibool installed = false; /* True if we are installed */ +static void (_ASMAPI *moveCursor)(int x,int y) = NULL; +static int (_ASMAPI *suspendAppCallback)(int flags) = NULL; + +#if 0 +/* Keyboard Translation table from scancodes to ASCII */ + +static uchar keyTable[128] = +"\0\0331234567890-=\010" +"\011qwertyuiop[]\015" +"\0asdfghjkl;'`\0\\" +"zxcvbnm,./\0*\0 \0" +"\0\0\0\0\0\0\0\0\0\0\0\0" /* Function keys */ +"789-456+1230.\0\0\0\0\0" /* Keypad keys */ +"\0\0\0\0\0\0\0\015\0/"; + +static uchar keyTableShifted[128] = +"\0\033!@#$%^&*()_+\010" +"\011QWERTYUIOP{}\015" +"\0ASDFGHJKL:\"~\0|" +"ZXCVBNM<>?\0*\0 \0" +"\0\0\0\0\0\0\0\0\0\0\0\0" /* Function keys */ +"789-456+1230.\0\0\0\0\0" /* Keypad keys */ +"\0\0\0\0\0\0\0\015\0/"; +#endif + +/* Macros to keep track of the CAPS and NUM lock states */ + +#define EVT_CAPSSTATE 0x0100 +#define EVT_NUMSTATE 0x0200 + +/* Helper macros for dealing with timers */ + +#define TICKS_TO_USEC(t) ((t)*65536.0/1.193180) +#define USEC_TO_TICKS(u) ((u)*1.193180/65536.0) + +/* Number of keycodes to read at a time from the console */ + +#define KBDREADBUFFERSIZE 32 + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +REMARKS: +Returns the current time stamp in units of 18.2 ticks per second. +****************************************************************************/ +static ulong getTimeStamp(void) +{ + return (ulong)(clock() / (CLOCKS_PER_SEC / 18.2)); +} + +/**************************************************************************** +PARAMETERS: +evt - Event to place onto event queue + +REMARKS: +Adds an event to the event queue by tacking it onto the tail of the event +queue. This routine assumes that at least one spot is available on the +freeList for the event to be inserted. +****************************************************************************/ +static void addEvent( + WD_event *evt) +{ + int evtID; + + /* Get spot to place the event from the free list */ + evtID = freeHead; + freeHead = evtq[freeHead].next; + + /* Add to the tail of the event queue */ + evt->next = -1; + evt->prev = tail; + if (tail != -1) + evtq[tail].next = evtID; + else + head = evtID; + tail = evtID; + evtq[evtID] = *evt; + count++; +} + +/**************************************************************************** +PARAMETERS: +what - Event code +message - Event message +modifiers - keyboard modifiers +x - Mouse X position at time of event +y - Mouse Y position at time of event +but_stat - Mouse button status at time of event + +REMARKS: +Adds a new mouse event to the event queue. This routine is called from +within the mouse interrupt subroutine, so it must be efficient. +****************************************************************************/ +static void addMouseEvent( + uint what, + uint message, + int x, + int y, + uint but_stat) +{ + WD_event evt; + + if (count < EVENTQSIZE) { + evt.what = what; + evt.when = getTimeStamp(); + evt.message = message; + evt.modifiers = but_stat | key_modifiers; + evt.where_x = x; + evt.where_y = y; + fprintf(stderr, "(%d,%d), buttons %ld\n", x,y, evt.modifiers); + addEvent(&evt); /* Add to tail of event queue */ + } +} + +/**************************************************************************** +PARAMETERS: +scancode - Raw keyboard scan code +modifiers - Keyboard modifiers flags + +REMARKS: +Converts the raw scan code into the appropriate ASCII code using the scan +code and the keyboard modifier flags. +****************************************************************************/ +static ulong getKeyMessage( + uint scancode, + ulong modifiers) +{ + ushort code = scancode << 8; + ushort ascii; + struct kbentry ke; + + ke.kb_index = scancode; + + /* Find the basic ASCII code for the scan code */ + if (modifiers & EVT_CAPSSTATE) { + if (modifiers & EVT_SHIFTKEY) + ke.kb_table = K_NORMTAB; + // ascii = tolower(keyTableShifted[scancode]); + else + ke.kb_table = K_SHIFTTAB; + // ascii = toupper(keyTable[scancode]); + } + else { + if (modifiers & EVT_SHIFTKEY) + ke.kb_table = K_SHIFTTAB; + // ascii = keyTableShifted[scancode]; + else + ke.kb_table = K_NORMTAB; + // ascii = keyTable[scancode]; + } + if(modifiers & EVT_ALTSTATE) + ke.kb_table |= K_ALTTAB; + + if (ioctl(tty_fd, KDGKBENT, (unsigned long)&ke)) { + fprintf(stderr, "KDGKBENT at index %d in table %d: ", + scancode, ke.kb_table); + return 0; + } + ascii = ke.kb_value; + + /* Add ASCII code if key is not alt'ed or ctrl'ed */ + if (!(modifiers & (EVT_ALTSTATE | EVT_CTRLSTATE))) + code |= ascii; + + return code; +} + +/**************************************************************************** +PARAMETERS: +what - Event code +scancode - Raw scancode of keyboard event to add + +REMARKS: +Adds a new keyboard event to the event queue. We only take KEYUP and +KEYDOWN event codes, however if a key is already down we convert the KEYDOWN +to a KEYREPEAT. +****************************************************************************/ +static void addKeyEvent( + uint what, + uint scancode) +{ + WD_event evt; + + if (count < EVENTQSIZE) { + evt.what = what; + evt.when = getTimeStamp(); + evt.message = getKeyMessage(scancode,key_modifiers) | 0x10000UL; + evt.where_x = evt.where_y = 0; + evt.modifiers = key_modifiers; + if (evt.what == EVT_KEYUP) + key_down[scancode] = false; + else if (evt.what == EVT_KEYDOWN) { + if (key_down[scancode]) { + if (oldKey != -1) { + evtq[oldKey].message += 0x10000UL; + } + else { + evt.what = EVT_KEYREPEAT; + oldKey = freeHead; + addEvent(&evt); + oldMove = -1; + } + return; + } + key_down[scancode] = true; + } + + addEvent(&evt); + oldMove = -1; + } +} + +/**************************************************************************** +PARAMETERS: +sig - Signal being sent to this signal handler + +REMARKS: +Signal handler for the timer. This routine takes care of periodically +posting timer events to the event queue. +****************************************************************************/ +void timerHandler( + int sig) +{ + WD_event evt; + + if (sig == SIGALRM) { + if (count < EVENTQSIZE) { + evt.when = getTimeStamp(); + evt.what = EVT_TIMERTICK; + evt.message = 0; + evt.where_x = evt.where_y = 0; + evt.modifiers = 0; + addEvent(&evt); + oldMove = -1; + oldKey = -1; + } + signal(SIGALRM, timerHandler); + } +} + +/**************************************************************************** +REMARKS: +Restore the terminal to normal operation on exit +****************************************************************************/ +static void restore_term(void) +{ + RMREGS regs; + + if (installed) { + /* Restore text mode and the state of the console */ + regs.x.ax = 0x3; + PM_int86(0x10,®s,®s); + PM_restoreConsoleState(stateBuf,tty_fd); + + /* Restore console to normal operation */ + ioctl(tty_fd, VT_SETMODE, &oldvtmode); + ioctl(tty_fd, KDSKBMODE, oldkbmode); + tcsetattr(tty_fd, TCSAFLUSH, &old_conf); + fcntl(tty_fd,F_SETFL,old_flags &= ~O_NONBLOCK); + PM_closeConsole(tty_fd); + + /* Close the mouse driver */ + close(conn); + + /* Flag that we are not no longer installed */ + installed = false; + } +} + +/**************************************************************************** +REMARKS: +Signal handler to capture forced program termination conditions so that +we can clean up properly. +****************************************************************************/ +static void exitHandler(int sig) +{ + exit(-1); +} + +/**************************************************************************** +REMARKS: +Sleep until the virtual terminal is active +****************************************************************************/ +void wait_vt_active(void) +{ + while (ioctl(tty_fd, VT_WAITACTIVE, tty_vc) < 0) { + if ((errno != EAGAIN) && (errno != EINTR)) { + perror("ioctl(VT_WAITACTIVE)"); + exit(1); + } + usleep(150000); + } +} + +/**************************************************************************** +REMARKS: +Signal handler called when our virtual terminal has been released and we are +losing the active focus. +****************************************************************************/ +static void release_vt_signal(int n) +{ + forbid_vt_acquire = 1; + if (forbid_vt_release) { + forbid_vt_acquire = 0; + ioctl(tty_fd, VT_RELDISP, 0); + return; + } + + // TODO: Call the user supplied suspendAppCallback and restore text + // mode (saving the existing mode so we can restore it). + // + // Also if the suspendAppCallback is NULL then we have to + // ignore the switch request! + if(suspendAppCallback){ + oldmode = VBE_getVideoMode(); + suspendAppCallback(true); + VBE_setVideoMode(initmode); + } + + ioctl(tty_fd, VT_RELDISP, 1); + forbid_vt_acquire = 0; + wait_vt_active(); +} + +/**************************************************************************** +REMARKS: +Signal handler called when our virtual terminal has been re-aquired and we +are now regaiing the active focus. +****************************************************************************/ +static void acquire_vt_signal(int n) +{ + forbid_vt_release = 1; + if (forbid_vt_acquire) { + forbid_vt_release = 0; + return; + } + + // TODO: Restore the old display mode, call the user suspendAppCallback + // and and we will be back in graphics mode. + + if(suspendAppCallback){ + VBE_setVideoMode(oldmode); + suspendAppCallback(false); + } + + ioctl(tty_fd, VT_RELDISP, VT_ACKACQ); + forbid_vt_release = 0; +} + +/**************************************************************************** +REMARKS: +Function to set the action for a specific signal to call our signal handler. +****************************************************************************/ +static void set_sigaction(int sig,void (*handler)(int)) +{ + struct sigaction siga; + + siga.sa_handler = handler; + siga.sa_flags = SA_RESTART; + memset(&(siga.sa_mask), 0, sizeof(sigset_t)); + sigaction(sig, &siga, NULL); +} + +/**************************************************************************** +REMARKS: +Function to take over control of VT switching so that we can capture +virtual terminal release and aquire signals, allowing us to properly +support VT switching while in graphics modes. +****************************************************************************/ +static void take_vt_control(void) +{ + struct vt_mode vtmode; + + ioctl(tty_fd, VT_GETMODE, &vtmode); + oldvtmode = vtmode; + vtmode.mode = VT_PROCESS; + vtmode.relsig = SIGUSR1; + vtmode.acqsig = SIGUSR2; + set_sigaction(SIGUSR1, release_vt_signal); + set_sigaction(SIGUSR2, acquire_vt_signal); + ioctl(tty_fd, VT_SETMODE, &oldvtmode); +} + +/**************************************************************************** +REMARKS: +Set the shift keyboard LED's based on the current keyboard modifiers flags. +****************************************************************************/ +static void updateLEDStatus(void) +{ + int state = 0; + if (key_modifiers & EVT_CAPSSTATE) + state |= LED_CAP; + if (key_modifiers & EVT_NUMSTATE) + state |= LED_NUM; + ioctl(tty_fd,KDSETLED,state); +} + +/**************************************************************************** +PARAMETERS: +scancode - Raw scan code to handle + +REMARKS: +Handles the shift key modifiers and keeps track of the shift key states +so that we can return the correct ASCII codes for the keyboard. +****************************************************************************/ +static void toggleModifiers( + int scancode) +{ + static int caps_down = 0,num_down = 0; + + if (scancode & 0x80) { + /* Handle key-release function */ + scancode &= 0x7F; + if (scancode == 0x2A || scancode == 0x36) + key_modifiers &= ~EVT_SHIFTKEY; + else if (scancode == 0x1D || scancode == 0x61) + key_modifiers &= ~EVT_CTRLSTATE; + else if (scancode == 0x38 || scancode == 0x64) + key_modifiers &= ~EVT_ALTSTATE; + else if (scancode == 0x3A) + caps_down = false; + else if (scancode == 0x45) + num_down = false; + } + else { + /* Handle key-down function */ + scancode &= 0x7F; + if (scancode == 0x2A || scancode == 0x36) + key_modifiers |= EVT_SHIFTKEY; + else if (scancode == 0x1D || scancode == 0x61) + key_modifiers |= EVT_CTRLSTATE; + else if (scancode == 0x38 || scancode == 0x64) + key_modifiers |= EVT_ALTSTATE; + else if (scancode == 0x3A) { + if (!caps_down) { + key_modifiers ^= EVT_CAPSSTATE; + updateLEDStatus(); + } + caps_down = true; + } + else if (scancode == 0x45) { + if (!num_down) { + key_modifiers ^= EVT_NUMSTATE; + updateLEDStatus(); + } + num_down = true; + } + } +} + +/*************************************************************************** +REMARKS: +Returns the number of bits that have changed from 0 to 1 +(a negative value means the number of bits that have changed from 1 to 0) + **************************************************************************/ +static int compareBits(short a, short b) +{ + int ret = 0; + if( (a&1) != (b&1) ) ret += (b&1) ? 1 : -1; + if( (a&2) != (b&2) ) ret += (b&2) ? 1 : -1; + if( (a&4) != (b&4) ) ret += (b&4) ? 1 : -1; + return ret; +} + +/*************************************************************************** +REMARKS: +Turns off all keyboard state because we can't rely on them anymore as soon +as we switch VT's +***************************************************************************/ +static void keyboard_clearstate(void) +{ + key_modifiers = 0; + memset(key_down, 0, sizeof(key_down)); +} + +/**************************************************************************** +REMARKS: +Pumps all events from the console event queue into the WinDirect event queue. +****************************************************************************/ +static void pumpEvents(void) +{ + static uchar buf[KBDREADBUFFERSIZE]; + static char data[5]; + static int old_buts, old_mx, old_my; + static struct timeval t; + fd_set fds; + int numkeys,i; + int dx, dy, buts; + + /* Read all pending keypresses from keyboard buffer and process */ + while ((numkeys = read(tty_fd, buf, KBDREADBUFFERSIZE)) > 0) { + for (i = 0; i < numkeys; i++) { + toggleModifiers(buf[i]); + if (key_modifiers & EVT_ALTSTATE){ + int fkey = 0; + + // Do VT switching here for Alt+Fx keypresses + switch(buf[i] & 0x7F){ + case 59 ... 68: /* F1 to F10 */ + fkey = (buf[i] & 0x7F) - 58; + break; + case 87: /* F11 */ + case 88: /* F12 */ + fkey = (buf[i] & 0x7F) - 76; + break; + } + if(fkey){ + struct vt_stat vts; + ioctl(tty_fd, VT_GETSTATE, &vts); + + if(fkey != vts.v_active){ + keyboard_clearstate(); + ioctl(tty_fd, VT_ACTIVATE, fkey); + } + } + } + + if (buf[i] & 0x80) + addKeyEvent(EVT_KEYUP,buf[i] & 0x7F); + else + addKeyEvent(EVT_KEYDOWN,buf[i] & 0x7F); + } + + // TODO: If we want to handle VC switching we will need to do it + // in here so that we can switch away from the VC and then + // switch back to it later. Right now VC switching is disabled + // and in order to enable it we need to save/restore the state + // of the graphics screen (using the suspendAppCallback and + // saving/restoring the state of the current display mode). + + } + + /* Read all pending mouse events and process them */ + if(conn > 0){ + FD_ZERO(&fds); + FD_SET(conn, &fds); + t.tv_sec = t.tv_usec = 0L; + while (select(conn+1, &fds, NULL, NULL, &t) > 0) { + if(read(conn, data, 5) == 5){ + buts = (~data[0]) & 0x07; + dx = (char)(data[1]) + (char)(data[3]); + dy = -((char)(data[2]) + (char)(data[4])); + + mx += dx; my += dy; + + if (dx || dy) + addMouseEvent(EVT_MOUSEMOVE, 0, mx, my, buts); + + if (buts != old_buts){ + int c = compareBits(buts,old_buts); + if(c>0) + addMouseEvent(EVT_MOUSEDOWN, 0, mx, my, buts); + else if(c<0) + addMouseEvent(EVT_MOUSEUP, 0, mx, my, buts); + } + old_mx = mx; old_my = my; + old_buts = buts; + FD_SET(conn, &fds); + t.tv_sec = t.tv_usec = 0L; + } + } + } +} + +/*------------------------ Public interface routines ----------------------*/ + +/**************************************************************************** +PARAMETERS: +which - Which code for event to post +what - Event code for event to post +message - Event message +modifiers - Shift key/mouse button modifiers + +RETURNS: +True if the event was posted, false if queue is full. + +REMARKS: +Posts an event to the event queue. This routine can be used to post any type +of event into the queue. +****************************************************************************/ +ibool _WDAPI WD_postEvent( + ulong which, + uint what, + ulong message, + ulong modifiers) +{ + WD_event evt; + + if (count < EVENTQSIZE) { + /* Save information in event record */ + evt.which = which; + evt.what = what; + evt.when = getTimeStamp(); + evt.message = message; + evt.modifiers = modifiers; + addEvent(&evt); /* Add to tail of event queue */ + return true; + } + else + return false; +} + +/**************************************************************************** +PARAMETERS: +mask - Event mask to use + +REMARKS: +Flushes all the event specified in 'mask' from the event queue. +****************************************************************************/ +void _WDAPI WD_flushEvent( + uint mask) +{ + WD_event evt; + + do { /* Flush all events */ + WD_getEvent(&evt,mask); + } while (evt.what != EVT_NULLEVT); +} + +/**************************************************************************** +PARAMETERS: +evt - Place to store event +mask - Event mask to use + +REMARKS: +Halts program execution until a specified event occurs. The event is +returned. All pending events not in the specified mask will be ignored and +removed from the queue. +****************************************************************************/ +void _WDAPI WD_haltEvent( + WD_event *evt, + uint mask) +{ + do { /* Wait for an event */ + WD_getEvent(evt,EVT_EVERYEVT); + } while (!(evt->what & mask)); +} + +/**************************************************************************** +PARAMETERS: +evt - Place to store event +mask - Event mask to use + +RETURNS: +True if an event was pending. + +REMARKS: +Retrieves the next pending event defined in 'mask' from the event queue. +The event queue is adjusted to reflect the new state after the event has +been removed. +****************************************************************************/ +ibool _WDAPI WD_getEvent( + WD_event *evt, + uint mask) +{ + int evtID,next,prev; + + pumpEvents(); + if (moveCursor) + moveCursor(mx,my); /* Move the mouse cursor */ + evt->what = EVT_NULLEVT; /* Default to null event */ + + if (count) { + for (evtID = head; evtID != -1; evtID = evtq[evtID].next) { + if (evtq[evtID].what & mask) + break; /* Found an event */ + } + if (evtID == -1) + return false; /* Event was not found */ + next = evtq[evtID].next; + prev = evtq[evtID].prev; + if (prev != -1) + evtq[prev].next = next; + else + head = next; + if (next != -1) + evtq[next].prev = prev; + else + tail = prev; + *evt = evtq[evtID]; /* Return the event */ + evtq[evtID].next = freeHead; /* and return to free list */ + freeHead = evtID; + count--; + if (evt->what == EVT_MOUSEMOVE) + oldMove = -1; + if (evt->what == EVT_KEYREPEAT) + oldKey = -1; + } + return evt->what != EVT_NULLEVT; +} + +/**************************************************************************** +PARAMETERS: +evt - Place to store event +mask - Event mask to use + +RETURNS: +True if an event is pending. + +REMARKS: +Peeks at the next pending event defined in 'mask' in the event queue. The +event is not removed from the event queue. +****************************************************************************/ +ibool _WDAPI WD_peekEvent( + WD_event *evt, + uint mask) +{ + int evtID; + + pumpEvents(); + if (moveCursor) + moveCursor(mx,my); /* Move the mouse cursor */ + evt->what = EVT_NULLEVT; /* Default to null event */ + + if (count) { + for (evtID = head; evtID != -1; evtID = evtq[evtID].next) { + if (evtq[evtID].what & mask) + break; /* Found an event */ + } + if (evtID == -1) + return false; /* Event was not found */ + + *evt = evtq[evtID]; /* Return the event */ + } + return evt->what != EVT_NULLEVT; +} + +/**************************************************************************** +PARAMETERS: +hwndMain - Handle to main window +_xRes - X resolution of graphics mode to be used +_yRes - Y resolulion of graphics mode to be used + +RETURNS: +Handle to the fullscreen event window if (we return hwndMain on Linux) + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling +ISR to be called whenever any button's are pressed or released. We also +build the free list of events in the event queue. +****************************************************************************/ +WD_HWND _WDAPI WD_startFullScreen( + WD_HWND hwndMain, + int _xRes, + int _yRes) +{ + int i; + struct termios conf; + if (!installed) { + Gpm_Connect gpm; + + /* Build free list, and initialise global data structures */ + for (i = 0; i < EVENTQSIZE; i++) + evtq[i].next = i+1; + evtq[EVENTQSIZE-1].next = -1; /* Terminate list */ + count = freeHead = 0; + head = tail = -1; + oldMove = -1; + oldKey = -1; + xRes = _xRes; + yRes = _yRes; + + /* Open the console device and initialise it for raw mode */ + tty_fd = PM_openConsole(); + + /* Wait until virtual terminal is active and take over control */ + wait_vt_active(); + take_vt_control(); + + /* Initialise keyboard handling to raw mode */ + if (ioctl(tty_fd, KDGKBMODE, &oldkbmode)) { + printf("WD_startFullScreen: cannot get keyboard mode.\n"); + exit(-1); + } + old_flags = fcntl(tty_fd,F_GETFL); + fcntl(tty_fd,F_SETFL,old_flags |= O_NONBLOCK); + tcgetattr(tty_fd, &conf); + old_conf = conf; + conf.c_lflag &= ~(ICANON | ECHO | ECHOE | ECHOK | ECHONL | NOFLSH | ISIG); + conf.c_iflag &= ~(ISTRIP | IGNCR | ICRNL | INLCR | BRKINT | PARMRK | INPCK | IUCLC | IXON | IXOFF); + conf.c_iflag |= (IGNBRK | IGNPAR); + conf.c_cc[VMIN] = 1; + conf.c_cc[VTIME] = 0; + conf.c_cc[VSUSP] = 0; + tcsetattr(tty_fd, TCSAFLUSH, &conf); + ioctl(tty_fd, KDSKBMODE, K_MEDIUMRAW); + + /* Clear the keyboard state information */ + memset(key_down, 0, sizeof(key_down)); + ioctl(tty_fd,KDSETLED,key_modifiers = 0); + + /* Initialize the mouse connection + The user *MUST* run gpm with the option -R for this to work (or have a MouseSystems mouse) + */ + if(Gpm_Open(&gpm,0) > 0){ /* GPM available */ + if ((conn = open(GPM_NODE_FIFO,O_RDONLY|O_SYNC)) < 0) + fprintf(stderr,"WD_startFullScreen: Can't open mouse connection.\n"); + }else{ + fprintf(stderr,"Warning: when not using gpm -R, only MouseSystems mice are currently supported.\n"); + if ((conn = open("/dev/mouse",O_RDONLY|O_SYNC)) < 0) + fprintf(stderr,"WD_startFullScreen: Can't open /dev/mouse.\n"); + } + Gpm_Close(); + + /* TODO: Scale the mouse coordinates to the specific resolution */ + + /* Save the state of the console */ + if ((stateBuf = malloc(PM_getConsoleStateSize())) == NULL) { + printf("Out of memory!\n"); + exit(-1); + } + PM_saveConsoleState(stateBuf,tty_fd); + initmode = VBE_getVideoMode(); + + /* Initialize the signal handler for timer events */ + signal(SIGALRM, timerHandler); + + /* Capture termination signals so we can clean up properly */ + signal(SIGTERM, exitHandler); + signal(SIGINT, exitHandler); + signal(SIGQUIT, exitHandler); + atexit(restore_term); + + /* Signal that we are installed */ + installed = true; + } + return hwndMain; +} + +/**************************************************************************** +REMARKS: +Lets the library know when fullscreen graphics mode has been initialized so +that we can properly scale the mouse driver coordinates. +****************************************************************************/ +void _WDAPI WD_inFullScreen(void) +{ + /* Nothing to do in here */ +} + +/**************************************************************************** +REMARKS: +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void _WDAPI WD_restoreGDI(void) +{ + restore_term(); +} + +/**************************************************************************** +PARAMETERS: +ticks - Number of ticks between timer tick messages + +RETURNS: +Previous value for the timer tick event spacing. + +REMARKS: +The event module will automatically generate periodic timer tick events for +you, with 'ticks' between each event posting. If you set the value of +'ticks' to 0, the timer tick events are turned off. +****************************************************************************/ +int _WDAPI WD_setTimerTick( + int ticks) +{ + int old; + struct itimerval tim; + long ms = TICKS_TO_USEC(ticks); + + getitimer(ITIMER_REAL, &tim); + old = USEC_TO_TICKS(tim.it_value.tv_sec*1000000.0 + tim.it_value.tv_usec); + tim.it_interval.tv_sec = ms / 1000000; + tim.it_interval.tv_usec = ms % 1000000; + setitimer(ITIMER_REAL, &tim, NULL); + return old; +} + +/**************************************************************************** +PARAMETERS: +saveState - Address of suspend app callback to register + +REMARKS: +Registers a user application supplied suspend application callback so that +we can properly handle virtual terminal switching. +****************************************************************************/ +void _WDAPI WD_setSuspendAppCallback( + int (_ASMAPI *saveState)(int flags)) +{ + suspendAppCallback = saveState; +} + +/**************************************************************************** +PARAMETERS: +x - New X coordinate to move the mouse cursor to +y - New Y coordinate to move the mouse cursor to + +REMARKS: +Moves to mouse cursor to the specified coordinate. +****************************************************************************/ +void _WDAPI WD_setMousePos( + int x, + int y) +{ + mx = x; + my = y; +} + +/**************************************************************************** +PARAMETERS: +x - Place to store X coordinate of mouse cursor +y - Place to store Y coordinate of mouse cursor + +REMARKS: +Reads the current mouse cursor location int *screen* coordinates. +****************************************************************************/ +void _WDAPI WD_getMousePos( + int *x, + int *y) +{ + *x = mx; + *y = my; +} + +/**************************************************************************** +PARAMETERS: +mcb - Address of mouse callback function + +REMARKS: +Registers an application supplied mouse callback function that is called +whenever the mouse cursor moves. +****************************************************************************/ +void _WDAPI WD_setMouseCallback( + void (_ASMAPI *mcb)(int x,int y)) +{ + moveCursor = mcb; +} + +/**************************************************************************** +PARAMETERS: +xRes - New X resolution of graphics mode +yRes - New Y resolution of graphics mode + +REMARKS: +This is called to inform the event handling code that the screen resolution +has changed so that the mouse coordinates can be scaled appropriately. +****************************************************************************/ +void _WDAPI WD_changeResolution( + int xRes, + int yRes) +{ + // Gpm_FitValues(xRes, yRes); // ?? +} + +/**************************************************************************** +PARAMETERS: +scancode - Scan code to check if a key is down + +REMARKS: +Determines if a particular key is down based on the scan code for the key. +****************************************************************************/ +ibool _WDAPI WD_isKeyDown( + uchar scancode) +{ + return key_down[scancode]; +} + +/**************************************************************************** +REMARKS: +Determines if the application needs to run in safe mode. Not necessary for +anything but broken Windows 95 display drivers so we return false for +Linux. +****************************************************************************/ +int _WDAPI WD_isSafeMode(void) +{ + return false; +} + + diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h new file mode 100644 index 0000000..eadedfb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h @@ -0,0 +1,60 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: Include all the OS specific header files. +* +****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef USE_OS_JOYSTICK +#include +#endif +#include +#include +#include +#include +#include + +/* Internal global variables */ + +extern int _PM_console_fd,_PM_leds,_PM_modifiers; + +/* Internal function prototypes */ + +void _PM_restore_kb_mode(void); +void _PM_keyboard_rawmode(void); + +/* Linux needs the generic joystick scaling code */ + +#define NEED_SCALE_JOY_AXIS diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c b/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c new file mode 100644 index 0000000..c12a835 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c @@ -0,0 +1,1809 @@ +;/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Portions copyright (C) Josh Vanderhoof +* +* Language: ANSI C +* Environment: Linux +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ENABLE_MTRR +#include +#endif +#include +#ifdef __GLIBC__ +#include +#endif + +/*--------------------------- Global variables ----------------------------*/ + +#define REAL_MEM_BASE ((void *)0x10000) +#define REAL_MEM_SIZE 0x10000 +#define REAL_MEM_BLOCKS 0x100 +#define DEFAULT_VM86_FLAGS (IF_MASK | IOPL_MASK) +#define DEFAULT_STACK_SIZE 0x1000 +#define RETURN_TO_32_INT 255 + +/* Quick and dirty fix for vm86() syscall from lrmi 0.6 */ +static int +vm86(struct vm86_struct *vm) + { + int r; +#ifdef __PIC__ + asm volatile ( + "pushl %%ebx\n\t" + "movl %2, %%ebx\n\t" + "int $0x80\n\t" + "popl %%ebx" + : "=a" (r) + : "0" (113), "r" (vm)); +#else + asm volatile ( + "int $0x80" + : "=a" (r) + : "0" (113), "b" (vm)); +#endif + return r; + } + + +static struct { + int ready; + unsigned short ret_seg, ret_off; + unsigned short stack_seg, stack_off; + struct vm86_struct vm; + } context = {0}; + +struct mem_block { + unsigned int size : 20; + unsigned int free : 1; + }; + +static struct { + int ready; + int count; + struct mem_block blocks[REAL_MEM_BLOCKS]; + } mem_info = {0}; + +int _PM_console_fd = -1; +int _PM_leds = 0,_PM_modifiers = 0; +static ibool inited = false; +static int tty_vc = 0; +static int console_count = 0; +static int startup_vc; +static int fd_mem = 0; +static ibool in_raw_mode = false; +#ifdef ENABLE_MTRR +static int mtrr_fd; +#endif +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +#ifdef TRACE_IO +static ulong traceAddr; +#endif + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef TRACE_IO +extern void printk(char *msg,...); +#endif + +static inline void port_out(int value, int port) +{ +#ifdef TRACE_IO + printk("%04X:%04X: outb.%04X <- %02X\n", traceAddr >> 16, traceAddr & 0xFFFF, (ushort)port, (uchar)value); +#endif + asm volatile ("outb %0,%1" + ::"a" ((unsigned char) value), "d"((unsigned short) port)); +} + +static inline void port_outw(int value, int port) +{ +#ifdef TRACE_IO + printk("%04X:%04X: outw.%04X <- %04X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ushort)value); +#endif + asm volatile ("outw %0,%1" + ::"a" ((unsigned short) value), "d"((unsigned short) port)); +} + +static inline void port_outl(int value, int port) +{ +#ifdef TRACE_IO + printk("%04X:%04X: outl.%04X <- %08X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ulong)value); +#endif + asm volatile ("outl %0,%1" + ::"a" ((unsigned long) value), "d"((unsigned short) port)); +} + +static inline unsigned int port_in(int port) +{ + unsigned char value; + asm volatile ("inb %1,%0" + :"=a" ((unsigned char)value) + :"d"((unsigned short) port)); +#ifdef TRACE_IO + printk("%04X:%04X: inb.%04X -> %02X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (uchar)value); +#endif + return value; +} + +static inline unsigned int port_inw(int port) +{ + unsigned short value; + asm volatile ("inw %1,%0" + :"=a" ((unsigned short)value) + :"d"((unsigned short) port)); +#ifdef TRACE_IO + printk("%04X:%04X: inw.%04X -> %04X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ushort)value); +#endif + return value; +} + +static inline unsigned int port_inl(int port) +{ + unsigned long value; + asm volatile ("inl %1,%0" + :"=a" ((unsigned long)value) + :"d"((unsigned short) port)); +#ifdef TRACE_IO + printk("%04X:%04X: inl.%04X -> %08X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ulong)value); +#endif + return value; +} + +static int real_mem_init(void) +{ + void *m; + int fd_zero; + + if (mem_info.ready) + return 1; + + if ((fd_zero = open("/dev/zero", O_RDONLY)) == -1) + PM_fatalError("You must have root privledges to run this program!"); + if ((m = mmap((void *)REAL_MEM_BASE, REAL_MEM_SIZE, + PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_FIXED | MAP_PRIVATE, fd_zero, 0)) == (void *)-1) { + close(fd_zero); + PM_fatalError("You must have root privledges to run this program!"); + } + mem_info.ready = 1; + mem_info.count = 1; + mem_info.blocks[0].size = REAL_MEM_SIZE; + mem_info.blocks[0].free = 1; + return 1; +} + +static void insert_block(int i) +{ + memmove( + mem_info.blocks + i + 1, + mem_info.blocks + i, + (mem_info.count - i) * sizeof(struct mem_block)); + mem_info.count++; +} + +static void delete_block(int i) +{ + mem_info.count--; + + memmove( + mem_info.blocks + i, + mem_info.blocks + i + 1, + (mem_info.count - i) * sizeof(struct mem_block)); +} + +static inline void set_bit(unsigned int bit, void *array) +{ + unsigned char *a = array; + a[bit / 8] |= (1 << (bit % 8)); +} + +static inline unsigned int get_int_seg(int i) +{ + return *(unsigned short *)(i * 4 + 2); +} + +static inline unsigned int get_int_off(int i) +{ + return *(unsigned short *)(i * 4); +} + +static inline void pushw(unsigned short i) +{ + struct vm86_regs *r = &context.vm.regs; + r->esp -= 2; + *(unsigned short *)(((unsigned int)r->ss << 4) + r->esp) = i; +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return true; } + +void PMAPI PM_init(void) +{ + void *m; + uint r_seg,r_off; + + if (inited) + return; + + /* Map the Interrupt Vectors (0x0 - 0x400) + BIOS data (0x400 - 0x502) + * and the physical framebuffer and ROM images from (0xa0000 - 0x100000) + */ + real_mem_init(); + if (!fd_mem && (fd_mem = open("/dev/mem", O_RDWR)) == -1) { + PM_fatalError("You must have root privileges to run this program!"); + } + if ((m = mmap((void *)0, 0x502, + PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_FIXED | MAP_PRIVATE, fd_mem, 0)) == (void *)-1) { + PM_fatalError("You must have root privileges to run this program!"); + } + if ((m = mmap((void *)0xA0000, 0xC0000 - 0xA0000, + PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_SHARED, fd_mem, 0xA0000)) == (void *)-1) { + PM_fatalError("You must have root privileges to run this program!"); + } + if ((m = mmap((void *)0xC0000, 0xD0000 - 0xC0000, + PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_FIXED | MAP_PRIVATE, fd_mem, 0xC0000)) == (void *)-1) { + PM_fatalError("You must have root privileges to run this program!"); + } + if ((m = mmap((void *)0xD0000, 0x100000 - 0xD0000, + PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_SHARED, fd_mem, 0xD0000)) == (void *)-1) { + PM_fatalError("You must have root privileges to run this program!"); + } + inited = 1; + + /* Allocate a stack */ + m = PM_allocRealSeg(DEFAULT_STACK_SIZE,&r_seg,&r_off); + context.stack_seg = r_seg; + context.stack_off = r_off+DEFAULT_STACK_SIZE; + + /* Allocate the return to 32 bit routine */ + m = PM_allocRealSeg(2,&r_seg,&r_off); + context.ret_seg = r_seg; + context.ret_off = r_off; + ((uchar*)m)[0] = 0xCD; /* int opcode */ + ((uchar*)m)[1] = RETURN_TO_32_INT; + memset(&context.vm, 0, sizeof(context.vm)); + + /* Enable kernel emulation of all ints except RETURN_TO_32_INT */ + memset(&context.vm.int_revectored, 0, sizeof(context.vm.int_revectored)); + set_bit(RETURN_TO_32_INT, &context.vm.int_revectored); + context.ready = 1; +#ifdef ENABLE_MTRR + mtrr_fd = open("/dev/cpu/mtrr", O_RDWR, 0); + if (mtrr_fd < 0) + mtrr_fd = open("/proc/mtrr", O_RDWR, 0); +#endif + /* Enable I/O permissions to directly access I/O ports. We break the + * allocation into two parts, one for the ports from 0-0x3FF and + * another for the remaining ports up to 0xFFFF. Standard Linux kernels + * only allow the first 0x400 ports to be enabled, so to enable all + * 65536 ports you need a patched kernel that will enable the full + * 8Kb I/O permissions bitmap. + */ +#ifndef TRACE_IO + ioperm(0x0,0x400,1); + ioperm(0x400,0x10000-0x400,1); +#endif + iopl(3); +} + +long PMAPI PM_getOSType(void) +{ return _OS_LINUX; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '/') { + s[pos] = '/'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + fflush(stderr); + exit(1); +} + +static void ExitVBEBuf(void) +{ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +/* New raw console based getch and kbhit functions */ + +#define KB_CAPS LED_CAP /* 4 */ +#define KB_NUMLOCK LED_NUM /* 2 */ +#define KB_SCROLL LED_SCR /* 1 */ +#define KB_SHIFT 8 +#define KB_CONTROL 16 +#define KB_ALT 32 + +/* Structure used to save the keyboard mode to disk. We save it to disk + * so that we can properly restore the mode later if the program crashed. + */ + +typedef struct { + struct termios termios; + int kb_mode; + int leds; + int flags; + int startup_vc; + } keyboard_mode; + +/* Name of the file used to save keyboard mode information */ + +#define KBMODE_DAT "kbmode.dat" + +/**************************************************************************** +REMARKS: +Open the keyboard mode file on disk. +****************************************************************************/ +static FILE *open_kb_mode( + char *mode, + char *path) +{ + if (!PM_findBPD("graphics.bpd",path)) + return NULL; + PM_backslash(path); + strcat(path,KBMODE_DAT); + return fopen(path,mode); +} + +/**************************************************************************** +REMARKS: +Restore the keyboard to normal mode +****************************************************************************/ +void _PM_restore_kb_mode(void) +{ + FILE *kbmode; + keyboard_mode mode; + char path[PM_MAX_PATH]; + + if (_PM_console_fd != -1 && (kbmode = open_kb_mode("rb",path)) != NULL) { + if (fread(&mode,1,sizeof(mode),kbmode) == sizeof(mode)) { + if (mode.startup_vc > 0) + ioctl(_PM_console_fd, VT_ACTIVATE, mode.startup_vc); + ioctl(_PM_console_fd, KDSKBMODE, mode.kb_mode); + ioctl(_PM_console_fd, KDSETLED, mode.leds); + tcsetattr(_PM_console_fd, TCSAFLUSH, &mode.termios); + fcntl(_PM_console_fd,F_SETFL,mode.flags); + } + fclose(kbmode); + unlink(path); + in_raw_mode = false; + } +} + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _PM_abort( + int signo) +{ + char buf[80]; + + sprintf(buf,"Terminating on signal %d",signo); + _PM_restore_kb_mode(); + PM_fatalError(buf); +} + +/**************************************************************************** +REMARKS: +Put the keyboard into raw mode +****************************************************************************/ +void _PM_keyboard_rawmode(void) +{ + struct termios conf; + FILE *kbmode; + keyboard_mode mode; + char path[PM_MAX_PATH]; + int i; + static int sig_list[] = { + SIGHUP, + SIGINT, + SIGQUIT, + SIGILL, + SIGTRAP, + SIGABRT, + SIGIOT, + SIGBUS, + SIGFPE, + SIGKILL, + SIGSEGV, + SIGTERM, + }; + + if ((kbmode = open_kb_mode("rb",path)) == NULL) { + if ((kbmode = open_kb_mode("wb",path)) == NULL) + PM_fatalError("Unable to open kbmode.dat file for writing!"); + if (ioctl(_PM_console_fd, KDGKBMODE, &mode.kb_mode)) + perror("KDGKBMODE"); + ioctl(_PM_console_fd, KDGETLED, &mode.leds); + _PM_leds = mode.leds & 0xF; + _PM_modifiers = 0; + tcgetattr(_PM_console_fd, &mode.termios); + conf = mode.termios; + conf.c_lflag &= ~(ICANON | ECHO | ISIG); + conf.c_iflag &= ~(ISTRIP | IGNCR | ICRNL | INLCR | BRKINT | PARMRK | INPCK | IUCLC | IXON | IXOFF); + conf.c_iflag |= (IGNBRK | IGNPAR); + conf.c_cc[VMIN] = 1; + conf.c_cc[VTIME] = 0; + conf.c_cc[VSUSP] = 0; + tcsetattr(_PM_console_fd, TCSAFLUSH, &conf); + mode.flags = fcntl(_PM_console_fd,F_GETFL); + if (ioctl(_PM_console_fd, KDSKBMODE, K_MEDIUMRAW)) + perror("KDSKBMODE"); + atexit(_PM_restore_kb_mode); + for (i = 0; i < sizeof(sig_list)/sizeof(sig_list[0]); i++) + signal(sig_list[i], _PM_abort); + mode.startup_vc = startup_vc; + if (fwrite(&mode,1,sizeof(mode),kbmode) != sizeof(mode)) + PM_fatalError("Error writing kbmode.dat!"); + fclose(kbmode); + in_raw_mode = true; + } +} + +int PMAPI PM_kbhit(void) +{ + fd_set s; + struct timeval tv = { 0, 0 }; + + if (console_count == 0) + PM_fatalError("You *must* open a console before using PM_kbhit!"); + if (!in_raw_mode) + _PM_keyboard_rawmode(); + FD_ZERO(&s); + FD_SET(_PM_console_fd, &s); + return select(_PM_console_fd+1, &s, NULL, NULL, &tv) > 0; +} + +int PMAPI PM_getch(void) +{ + static uchar c; + int release; + static struct kbentry ke; + + if (console_count == 0) + PM_fatalError("You *must* open a console before using PM_getch!"); + if (!in_raw_mode) + _PM_keyboard_rawmode(); + while (read(_PM_console_fd, &c, 1) > 0) { + release = c & 0x80; + c &= 0x7F; + if (release) { + switch(c){ + case 42: case 54: /* Shift */ + _PM_modifiers &= ~KB_SHIFT; + break; + case 29: case 97: /* Control */ + _PM_modifiers &= ~KB_CONTROL; + break; + case 56: case 100: /* Alt / AltGr */ + _PM_modifiers &= ~KB_ALT; + break; + } + continue; + } + switch (c) { + case 42: case 54: /* Shift */ + _PM_modifiers |= KB_SHIFT; + break; + case 29: case 97: /* Control */ + _PM_modifiers |= KB_CONTROL; + break; + case 56: case 100: /* Alt / AltGr */ + _PM_modifiers |= KB_ALT; + break; + case 58: /* Caps Lock */ + _PM_modifiers ^= KB_CAPS; + ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7); + break; + case 69: /* Num Lock */ + _PM_modifiers ^= KB_NUMLOCK; + ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7); + break; + case 70: /* Scroll Lock */ + _PM_modifiers ^= KB_SCROLL; + ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7); + break; + case 28: + return 0x1C; + default: + ke.kb_index = c; + ke.kb_table = 0; + if ((_PM_modifiers & KB_SHIFT) || (_PM_modifiers & KB_CAPS)) + ke.kb_table |= K_SHIFTTAB; + if (_PM_modifiers & KB_ALT) + ke.kb_table |= K_ALTTAB; + ioctl(_PM_console_fd, KDGKBENT, (ulong)&ke); + c = ke.kb_value & 0xFF; + return c; + } + } + return 0; +} + +/**************************************************************************** +REMARKS: +Sleep until the virtual terminal is active +****************************************************************************/ +static void wait_vt_active( + int _PM_console_fd) +{ + while (ioctl(_PM_console_fd, VT_WAITACTIVE, tty_vc) < 0) { + if ((errno != EAGAIN) && (errno != EINTR)) { + perror("ioctl(VT_WAITACTIVE)"); + exit(1); + } + usleep(150000); + } +} + +/**************************************************************************** +REMARKS: +Checks the owner of the specified virtual console. +****************************************************************************/ +static int check_owner( + int vc) +{ + struct stat sbuf; + char fname[30]; + + sprintf(fname, "/dev/tty%d", vc); + if ((stat(fname, &sbuf) >= 0) && (getuid() == sbuf.st_uid)) + return 1; + printf("You must be the owner of the current console to use this program.\n"); + return 0; +} + +/**************************************************************************** +REMARKS: +Checks if the console is currently in graphics mode, and if so we forcibly +restore it back to text mode again. This handles the case when a Nucleus or +MGL program crashes and leaves the console in graphics mode. Running the +textmode utility (or any other Nucleus/MGL program) via a telnet session +into the machine will restore it back to normal. +****************************************************************************/ +static void restore_text_console( + int console_id) +{ + if (ioctl(console_id, KDSETMODE, KD_TEXT) < 0) + LOGWARN("ioctl(KDSETMODE) failed"); + _PM_restore_kb_mode(); +} + +/**************************************************************************** +REMARKS: +Opens up the console device for output by finding an appropriate virutal +console that we can run on. +****************************************************************************/ +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + struct vt_mode vtm; + struct vt_stat vts; + struct stat sbuf; + char fname[30]; + + /* Check if we have already opened the console */ + if (console_count++) + return _PM_console_fd; + + /* Now, it would be great if we could use /dev/tty and see what it is + * connected to. Alas, we cannot find out reliably what VC /dev/tty is + * bound to. Thus we parse stdin through stderr for a reliable VC. + */ + startup_vc = 0; + for (_PM_console_fd = 0; _PM_console_fd < 3; _PM_console_fd++) { + if (fstat(_PM_console_fd, &sbuf) < 0) + continue; + if (ioctl(_PM_console_fd, VT_GETMODE, &vtm) < 0) + continue; + if ((sbuf.st_rdev & 0xFF00) != 0x400) + continue; + if (!(sbuf.st_rdev & 0xFF)) + continue; + tty_vc = sbuf.st_rdev & 0xFF; + restore_text_console(_PM_console_fd); + return _PM_console_fd; + } + if ((_PM_console_fd = open("/dev/console", O_RDWR)) < 0) { + printf("open_dev_console: can't open /dev/console \n"); + exit(1); + } + if (ioctl(_PM_console_fd, VT_OPENQRY, &tty_vc) < 0) + goto Error; + if (tty_vc <= 0) + goto Error; + sprintf(fname, "/dev/tty%d", tty_vc); + close(_PM_console_fd); + + /* Change our control terminal */ + setsid(); + + /* We must use RDWR to allow for output... */ + if (((_PM_console_fd = open(fname, O_RDWR)) >= 0) && + (ioctl(_PM_console_fd, VT_GETSTATE, &vts) >= 0)) { + if (!check_owner(vts.v_active)) + goto Error; + restore_text_console(_PM_console_fd); + + /* Success, redirect all stdios */ + fflush(stdin); + fflush(stdout); + fflush(stderr); + close(0); + close(1); + close(2); + dup(_PM_console_fd); + dup(_PM_console_fd); + dup(_PM_console_fd); + + /* clear screen and switch to it */ + fwrite("\e[H\e[J", 6, 1, stderr); + fflush(stderr); + if (tty_vc != vts.v_active) { + startup_vc = vts.v_active; + ioctl(_PM_console_fd, VT_ACTIVATE, tty_vc); + wait_vt_active(_PM_console_fd); + } + } + return _PM_console_fd; + +Error: + if (_PM_console_fd > 2) + close(_PM_console_fd); + console_count = 0; + PM_fatalError( + "Not running in a graphics capable console,\n" + "and unable to find one.\n"); + return -1; +} + +#define FONT_C 0x10000 /* 64KB for font data */ + +/**************************************************************************** +REMARKS: +Returns the size of the console state buffer. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + if (!inited) + PM_init(); + return PM_getVGAStateSize() + FONT_C*2; +} + +/**************************************************************************** +REMARKS: +Save the state of the Linux console. +****************************************************************************/ +void PMAPI PM_saveConsoleState(void *stateBuf,int console_id) +{ + uchar *regs = stateBuf; + + /* Save the current console font */ + if (ioctl(console_id,GIO_FONT,®s[PM_getVGAStateSize()]) < 0) + perror("ioctl(GIO_FONT)"); + + /* Inform the Linux console that we are going into graphics mode */ + if (ioctl(console_id, KDSETMODE, KD_GRAPHICS) < 0) + perror("ioctl(KDSETMODE)"); + + /* Save state of VGA registers */ + PM_saveVGAState(stateBuf); +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* TODO: Implement support for allowing console switching! */ +} + +/**************************************************************************** +REMARKS: +Restore the state of the Linux console. +****************************************************************************/ +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND console_id) +{ + const uchar *regs = stateBuf; + + /* Restore the state of the VGA compatible registers */ + PM_restoreVGAState(stateBuf); + + /* Inform the Linux console that we are back from graphics modes */ + if (ioctl(console_id, KDSETMODE, KD_TEXT) < 0) + LOGWARN("ioctl(KDSETMODE) failed"); + + /* Restore the old console font */ + if (ioctl(console_id,PIO_FONT,®s[PM_getVGAStateSize()]) < 0) + LOGWARN("ioctl(KDSETMODE) failed"); + + /* Coming back from graphics mode on Linux also restored the previous + * text mode console contents, so we need to clear the screen to get + * around this since the cursor does not get homed by our code. + */ + fflush(stdout); + fflush(stderr); + printf("\033[H\033[J"); + fflush(stdout); +} + +/**************************************************************************** +REMARKS: +Close the Linux console and put it back to normal. +****************************************************************************/ +void PMAPI PM_closeConsole(PM_HWND _PM_console_fd) +{ + /* Restore console to normal operation */ + if (--console_count == 0) { + /* Re-activate the original virtual console */ + if (startup_vc > 0) + ioctl(_PM_console_fd, VT_ACTIVATE, startup_vc); + + /* Close the console file descriptor */ + if (_PM_console_fd > 2) + close(_PM_console_fd); + _PM_console_fd = -1; + } +} + +void PM_setOSCursorLocation(int x,int y) +{ + /* Nothing to do in here */ +} + +/**************************************************************************** +REMARKS: +Set the screen width and height for the Linux console. +****************************************************************************/ +void PM_setOSScreenWidth(int width,int height) +{ + struct winsize ws; + struct vt_sizes vs; + + /* Resize the software terminal */ + ws.ws_col = width; + ws.ws_row = height; + ioctl(_PM_console_fd, TIOCSWINSZ, &ws); + + /* And the hardware */ + vs.v_rows = height; + vs.v_cols = width; + vs.v_scrollsize = 0; + ioctl(_PM_console_fd, VT_RESIZE, &vs); +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency) +{ + /* TODO: Implement this for Linux */ + return false; +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + /* TODO: Implement this for Linux */ +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Implement this for Linux */ +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return '/'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return PM_getNucleusConfigPath(); } + +const char * PMAPI PM_getNucleusPath(void) +{ + char *env = getenv("NUCLEUS_PATH"); + return env ? env : "/usr/lib/nucleus"; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +const char * PMAPI PM_getMachineName(void) +{ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +void * PMAPI PM_getBIOSPointer(void) +{ + static uchar *zeroPtr = NULL; + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + 0x400); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + /* PM_init maps in the 0xA0000 framebuffer region 1:1 with our + * address mapping, so we can return the address here. + */ + if (!inited) + PM_init(); + return (void*)(0xA0000); +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + uchar *p; + ulong baseAddr,baseOfs; + + if (!inited) + PM_init(); + if (base >= 0xA0000 && base < 0x100000) + return (void*)base; + if (!fd_mem && (fd_mem = open("/dev/mem", O_RDWR)) == -1) + return NULL; + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to mmap. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = base & 4095; + baseAddr = base & ~4095; + limit = ((limit+baseOfs+1+4095) & ~4095)-1; + if ((p = mmap(0, limit+1, + PROT_READ | PROT_WRITE, MAP_SHARED, + fd_mem, baseAddr)) == (void *)-1) + return NULL; + return (void*)(p+baseOfs); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + if ((ulong)ptr >= 0x100000) + munmap(ptr,limit+1); +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) +{ + /* TODO: This function should find a range of physical addresses */ + /* for a linear address. */ + return false; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* TODO: Put the process to sleep for milliseconds */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +void * PMAPI PM_mallocShared(long size) +{ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + PM_free(ptr); +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + /* PM_init maps in the 0xA0000-0x100000 region 1:1 with our + * address mapping, as well as all memory blocks in a 1:1 address + * mapping so we can simply return the physical address in here. + */ + if (!inited) + PM_init(); + return (void*)MK_PHYS(r_seg,r_off); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + int i; + char *r = (char *)REAL_MEM_BASE; + + if (!inited) + PM_init(); + if (!mem_info.ready) + return NULL; + if (mem_info.count == REAL_MEM_BLOCKS) + return NULL; + size = (size + 15) & ~15; + for (i = 0; i < mem_info.count; i++) { + if (mem_info.blocks[i].free && size < mem_info.blocks[i].size) { + insert_block(i); + mem_info.blocks[i].size = size; + mem_info.blocks[i].free = 0; + mem_info.blocks[i + 1].size -= size; + *r_seg = (uint)(r) >> 4; + *r_off = (uint)(r) & 0xF; + return (void *)r; + } + r += mem_info.blocks[i].size; + } + return NULL; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + int i; + char *r = (char *)REAL_MEM_BASE; + + if (!mem_info.ready) + return; + i = 0; + while (mem != (void *)r) { + r += mem_info.blocks[i].size; + i++; + if (i == mem_info.count) + return; + } + mem_info.blocks[i].free = 1; + if (i + 1 < mem_info.count && mem_info.blocks[i + 1].free) { + mem_info.blocks[i].size += mem_info.blocks[i + 1].size; + delete_block(i + 1); + } + if (i - 1 >= 0 && mem_info.blocks[i - 1].free) { + mem_info.blocks[i - 1].size += mem_info.blocks[i].size; + delete_block(i); + } +} + +#define DIRECTION_FLAG (1 << 10) + +static void em_ins(int size) +{ + unsigned int edx, edi; + + edx = context.vm.regs.edx & 0xffff; + edi = context.vm.regs.edi & 0xffff; + edi += (unsigned int)context.vm.regs.ds << 4; + if (context.vm.regs.eflags & DIRECTION_FLAG) { + if (size == 4) + asm volatile ("std; insl; cld" + : "=D" (edi) : "d" (edx), "0" (edi)); + else if (size == 2) + asm volatile ("std; insw; cld" + : "=D" (edi) : "d" (edx), "0" (edi)); + else + asm volatile ("std; insb; cld" + : "=D" (edi) : "d" (edx), "0" (edi)); + } + else { + if (size == 4) + asm volatile ("cld; insl" + : "=D" (edi) : "d" (edx), "0" (edi)); + else if (size == 2) + asm volatile ("cld; insw" + : "=D" (edi) : "d" (edx), "0" (edi)); + else + asm volatile ("cld; insb" + : "=D" (edi) : "d" (edx), "0" (edi)); + } + edi -= (unsigned int)context.vm.regs.ds << 4; + context.vm.regs.edi &= 0xffff0000; + context.vm.regs.edi |= edi & 0xffff; +} + +static void em_rep_ins(int size) +{ + unsigned int ecx, edx, edi; + + ecx = context.vm.regs.ecx & 0xffff; + edx = context.vm.regs.edx & 0xffff; + edi = context.vm.regs.edi & 0xffff; + edi += (unsigned int)context.vm.regs.ds << 4; + if (context.vm.regs.eflags & DIRECTION_FLAG) { + if (size == 4) + asm volatile ("std; rep; insl; cld" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + else if (size == 2) + asm volatile ("std; rep; insw; cld" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + else + asm volatile ("std; rep; insb; cld" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + } + else { + if (size == 4) + asm volatile ("cld; rep; insl" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + else if (size == 2) + asm volatile ("cld; rep; insw" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + else + asm volatile ("cld; rep; insb" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + } + + edi -= (unsigned int)context.vm.regs.ds << 4; + context.vm.regs.edi &= 0xffff0000; + context.vm.regs.edi |= edi & 0xffff; + context.vm.regs.ecx &= 0xffff0000; + context.vm.regs.ecx |= ecx & 0xffff; +} + +static void em_outs(int size) +{ + unsigned int edx, esi; + + edx = context.vm.regs.edx & 0xffff; + esi = context.vm.regs.esi & 0xffff; + esi += (unsigned int)context.vm.regs.ds << 4; + if (context.vm.regs.eflags & DIRECTION_FLAG) { + if (size == 4) + asm volatile ("std; outsl; cld" + : "=S" (esi) : "d" (edx), "0" (esi)); + else if (size == 2) + asm volatile ("std; outsw; cld" + : "=S" (esi) : "d" (edx), "0" (esi)); + else + asm volatile ("std; outsb; cld" + : "=S" (esi) : "d" (edx), "0" (esi)); + } + else { + if (size == 4) + asm volatile ("cld; outsl" + : "=S" (esi) : "d" (edx), "0" (esi)); + else if (size == 2) + asm volatile ("cld; outsw" + : "=S" (esi) : "d" (edx), "0" (esi)); + else + asm volatile ("cld; outsb" + : "=S" (esi) : "d" (edx), "0" (esi)); + } + + esi -= (unsigned int)context.vm.regs.ds << 4; + context.vm.regs.esi &= 0xffff0000; + context.vm.regs.esi |= esi & 0xffff; +} + +static void em_rep_outs(int size) +{ + unsigned int ecx, edx, esi; + + ecx = context.vm.regs.ecx & 0xffff; + edx = context.vm.regs.edx & 0xffff; + esi = context.vm.regs.esi & 0xffff; + esi += (unsigned int)context.vm.regs.ds << 4; + if (context.vm.regs.eflags & DIRECTION_FLAG) { + if (size == 4) + asm volatile ("std; rep; outsl; cld" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + else if (size == 2) + asm volatile ("std; rep; outsw; cld" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + else + asm volatile ("std; rep; outsb; cld" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + } + else { + if (size == 4) + asm volatile ("cld; rep; outsl" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + else if (size == 2) + asm volatile ("cld; rep; outsw" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + else + asm volatile ("cld; rep; outsb" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + } + + esi -= (unsigned int)context.vm.regs.ds << 4; + context.vm.regs.esi &= 0xffff0000; + context.vm.regs.esi |= esi & 0xffff; + context.vm.regs.ecx &= 0xffff0000; + context.vm.regs.ecx |= ecx & 0xffff; +} + +static int emulate(void) +{ + unsigned char *insn; + struct { + unsigned int size : 1; + unsigned int rep : 1; + } prefix = { 0, 0 }; + int i = 0; + + insn = (unsigned char *)((unsigned int)context.vm.regs.cs << 4); + insn += context.vm.regs.eip; + + while (1) { +#ifdef TRACE_IO + traceAddr = ((ulong)context.vm.regs.cs << 16) + context.vm.regs.eip + i; +#endif + if (insn[i] == 0x66) { + prefix.size = 1 - prefix.size; + i++; + } + else if (insn[i] == 0xf3) { + prefix.rep = 1; + i++; + } + else if (insn[i] == 0xf0 || insn[i] == 0xf2 + || insn[i] == 0x26 || insn[i] == 0x2e + || insn[i] == 0x36 || insn[i] == 0x3e + || insn[i] == 0x64 || insn[i] == 0x65 + || insn[i] == 0x67) { + /* these prefixes are just ignored */ + i++; + } + else if (insn[i] == 0x6c) { + if (prefix.rep) + em_rep_ins(1); + else + em_ins(1); + i++; + break; + } + else if (insn[i] == 0x6d) { + if (prefix.rep) { + if (prefix.size) + em_rep_ins(4); + else + em_rep_ins(2); + } + else { + if (prefix.size) + em_ins(4); + else + em_ins(2); + } + i++; + break; + } + else if (insn[i] == 0x6e) { + if (prefix.rep) + em_rep_outs(1); + else + em_outs(1); + i++; + break; + } + else if (insn[i] == 0x6f) { + if (prefix.rep) { + if (prefix.size) + em_rep_outs(4); + else + em_rep_outs(2); + } + else { + if (prefix.size) + em_outs(4); + else + em_outs(2); + } + i++; + break; + } + else if (insn[i] == 0xec) { + *((uchar*)&context.vm.regs.eax) = port_in(context.vm.regs.edx); + i++; + break; + } + else if (insn[i] == 0xed) { + if (prefix.size) + *((ulong*)&context.vm.regs.eax) = port_inl(context.vm.regs.edx); + else + *((ushort*)&context.vm.regs.eax) = port_inw(context.vm.regs.edx); + i++; + break; + } + else if (insn[i] == 0xee) { + port_out(context.vm.regs.eax,context.vm.regs.edx); + i++; + break; + } + else if (insn[i] == 0xef) { + if (prefix.size) + port_outl(context.vm.regs.eax,context.vm.regs.edx); + else + port_outw(context.vm.regs.eax,context.vm.regs.edx); + i++; + break; + } + else + return 0; + } + + context.vm.regs.eip += i; + return 1; +} + +static void debug_info(int vret) +{ + int i; + unsigned char *p; + + fputs("vm86() failed\n", stderr); + fprintf(stderr, "return = 0x%x\n", vret); + fprintf(stderr, "eax = 0x%08lx\n", context.vm.regs.eax); + fprintf(stderr, "ebx = 0x%08lx\n", context.vm.regs.ebx); + fprintf(stderr, "ecx = 0x%08lx\n", context.vm.regs.ecx); + fprintf(stderr, "edx = 0x%08lx\n", context.vm.regs.edx); + fprintf(stderr, "esi = 0x%08lx\n", context.vm.regs.esi); + fprintf(stderr, "edi = 0x%08lx\n", context.vm.regs.edi); + fprintf(stderr, "ebp = 0x%08lx\n", context.vm.regs.ebp); + fprintf(stderr, "eip = 0x%08lx\n", context.vm.regs.eip); + fprintf(stderr, "cs = 0x%04x\n", context.vm.regs.cs); + fprintf(stderr, "esp = 0x%08lx\n", context.vm.regs.esp); + fprintf(stderr, "ss = 0x%04x\n", context.vm.regs.ss); + fprintf(stderr, "ds = 0x%04x\n", context.vm.regs.ds); + fprintf(stderr, "es = 0x%04x\n", context.vm.regs.es); + fprintf(stderr, "fs = 0x%04x\n", context.vm.regs.fs); + fprintf(stderr, "gs = 0x%04x\n", context.vm.regs.gs); + fprintf(stderr, "eflags = 0x%08lx\n", context.vm.regs.eflags); + fputs("cs:ip = [ ", stderr); + p = (unsigned char *)((context.vm.regs.cs << 4) + (context.vm.regs.eip & 0xffff)); + for (i = 0; i < 16; ++i) + fprintf(stderr, "%02x ", (unsigned int)p[i]); + fputs("]\n", stderr); + fflush(stderr); +} + +static int run_vm86(void) +{ + unsigned int vret; + + for (;;) { + vret = vm86(&context.vm); + if (VM86_TYPE(vret) == VM86_INTx) { + unsigned int v = VM86_ARG(vret); + if (v == RETURN_TO_32_INT) + return 1; + pushw(context.vm.regs.eflags); + pushw(context.vm.regs.cs); + pushw(context.vm.regs.eip); + context.vm.regs.cs = get_int_seg(v); + context.vm.regs.eip = get_int_off(v); + context.vm.regs.eflags &= ~(VIF_MASK | TF_MASK); + continue; + } + if (VM86_TYPE(vret) != VM86_UNKNOWN) + break; + if (!emulate()) + break; + } + debug_info(vret); + return 0; +} + +#define IND(ereg) context.vm.regs.ereg = regs->ereg +#define OUTD(ereg) regs->ereg = context.vm.regs.ereg + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + IND(eax); IND(ebx); IND(ecx); IND(edx); IND(esi); IND(edi); + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(intno); + context.vm.regs.eip = get_int_off(intno); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + OUTD(eax); OUTD(ebx); OUTD(ecx); OUTD(edx); OUTD(esi); OUTD(edi); + regs->flags = context.vm.regs.eflags; +} + +#define IN(ereg) context.vm.regs.ereg = in->e.ereg +#define OUT(ereg) out->e.ereg = context.vm.regs.ereg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(intno); + context.vm.regs.eip = get_int_off(intno); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = context.vm.regs.eflags & 1; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + if (!inited) + PM_init(); + if (intno == 0x21) { + time_t today = time(NULL); + struct tm *t; + t = localtime(&today); + out->x.cx = t->tm_year + 1900; + out->h.dh = t->tm_mon + 1; + out->h.dl = t->tm_mday; + } + else { + unsigned int seg, off; + seg = get_int_seg(intno); + off = get_int_off(intno); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = seg; + context.vm.regs.eip = off; + context.vm.regs.es = sregs->es; + context.vm.regs.ds = sregs->ds; + context.vm.regs.fs = sregs->fs; + context.vm.regs.gs = sregs->gs; + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = context.vm.regs.es; + sregs->ds = context.vm.regs.ds; + sregs->fs = context.vm.regs.fs; + sregs->gs = context.vm.regs.gs; + out->x.cflag = context.vm.regs.eflags & 1; + } + return out->e.eax; +} + +#define OUTR(ereg) in->e.ereg = context.vm.regs.ereg + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = seg; + context.vm.regs.eip = off; + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + context.vm.regs.es = sregs->es; + context.vm.regs.ds = sregs->ds; + context.vm.regs.fs = sregs->fs; + context.vm.regs.gs = sregs->gs; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + OUTR(eax); OUTR(ebx); OUTR(ecx); OUTR(edx); OUTR(esi); OUTR(edi); + sregs->es = context.vm.regs.es; + sregs->ds = context.vm.regs.ds; + sregs->fs = context.vm.regs.fs; + sregs->gs = context.vm.regs.gs; + in->x.cflag = context.vm.regs.eflags & 1; +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + FILE *mem = fopen("/proc/meminfo","r"); + char buf[1024]; + + fgets(buf,1024,mem); + fgets(buf,1024,mem); + sscanf(buf,"Mem: %*d %*d %ld", physical); + fgets(buf,1024,mem); + sscanf(buf,"Swap: %*d %*d %ld", total); + fclose(mem); + *total += *physical; +} + +void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16M) +{ + /* TODO: Implement this for Linux */ + return NULL; +} + +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) +{ + /* TODO: Implement this for Linux */ +} + +void * PMAPI PM_allocPage( + ibool locked) +{ + /* TODO: Implement this for Linux */ + return NULL; +} + +void PMAPI PM_freePage( + void *p) +{ + /* TODO: Implement this for Linux */ +} + +void PMAPI PM_setBankA(int bank) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + context.vm.regs.eax = 0x4F05; + context.vm.regs.ebx = 0x0000; + context.vm.regs.edx = bank; + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(0x10); + context.vm.regs.eip = get_int_off(0x10); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); +} + +void PMAPI PM_setBankAB(int bank) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + context.vm.regs.eax = 0x4F05; + context.vm.regs.ebx = 0x0000; + context.vm.regs.edx = bank; + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(0x10); + context.vm.regs.eip = get_int_off(0x10); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + context.vm.regs.eax = 0x4F05; + context.vm.regs.ebx = 0x0001; + context.vm.regs.edx = bank; + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(0x10); + context.vm.regs.eip = get_int_off(0x10); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); +} + +void PMAPI PM_setCRTStart(int x,int y,int waitVRT) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + context.vm.regs.eax = 0x4F07; + context.vm.regs.ebx = waitVRT; + context.vm.regs.ecx = x; + context.vm.regs.edx = y; + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(0x10); + context.vm.regs.eip = get_int_off(0x10); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); +} + +int PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type) +{ +#ifdef ENABLE_MTRR + struct mtrr_sentry sentry; + + if (mtrr_fd < 0) + return PM_MTRR_ERR_NO_OS_SUPPORT; + sentry.base = base; + sentry.size = length; + sentry.type = type; + if (ioctl(mtrr_fd, MTRRIOC_ADD_ENTRY, &sentry) == -1) { + /* TODO: Need to decode MTRR error codes!! */ + return PM_MTRR_NOT_SUPPORTED; + } + return PM_MTRR_ERR_OK; +#else + return PM_MTRR_ERR_NO_OS_SUPPORT; +#endif +} + +/**************************************************************************** +PARAMETERS: +callback - Function to callback with write combine information + +REMARKS: +Function to enumerate all write combine regions currently enabled for the +processor. +****************************************************************************/ +int PMAPI PM_enumWriteCombine( + PM_enumWriteCombine_t callback) +{ +#ifdef ENABLE_MTRR + struct mtrr_gentry gentry; + + if (mtrr_fd < 0) + return PM_MTRR_ERR_NO_OS_SUPPORT; + + for (gentry.regnum = 0; ioctl (mtrr_fd, MTRRIOC_GET_ENTRY, &gentry) == 0; + ++gentry.regnum) { + if (gentry.size > 0) { + /* WARNING: This code assumes that the types in pmapi.h match the ones */ + /* in the Linux kernel (mtrr.h) */ + callback(gentry.base, gentry.size, gentry.type); + } + } + + return PM_MTRR_ERR_OK; +#else + return PM_MTRR_ERR_NO_OS_SUPPORT; +#endif +} + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *copyOfBIOS, + ulong BIOSLen) +{ + char *bios_ptr = (char*)0xC0000; + char *old_bios; + ulong Current10, Current6D, *rvec = 0; + RMREGS regs; + RMSREGS sregs; + + /* The BIOS is mapped to 0xC0000 with a private memory mapping enabled + * which means we have a copy on write scheme. Hence we simply copy + * the secondary BIOS image over the top of the old one. + */ + if (!inited) + PM_init(); + if ((old_bios = PM_malloc(BIOSLen)) == NULL) + return false; + if (BIOSPhysAddr != 0xC0000) { + memcpy(old_bios,bios_ptr,BIOSLen); + memcpy(bios_ptr,copyOfBIOS,BIOSLen); + } + + /* The interrupt vectors should already be mmap()'ed from 0-0x400 in PM_init */ + Current10 = rvec[0x10]; + Current6D = rvec[0x6D]; + + /* POST the secondary BIOS */ + rvec[0x10] = rvec[0x42]; /* Restore int 10h to STD-BIOS */ + regs.x.ax = axVal; + PM_callRealMode(0xC000,0x0003,®s,&sregs); + + /* Restore interrupt vectors */ + rvec[0x10] = Current10; + rvec[0x6D] = Current6D; + + /* Restore original BIOS image */ + if (BIOSPhysAddr != 0xC0000) + memcpy(bios_ptr,old_bios,BIOSLen); + PM_free(old_bios); + return true; +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: Implement this to load shared libraries! */ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: Implement this! */ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: Implement this! */ + (void)hModule; +} + +int PMAPI PM_setIOPL( + int level) +{ + /* TODO: Move the IOPL switching into this function!! */ + return level; +} + +void PMAPI PM_flushTLB(void) +{ + /* Do nothing on Linux. */ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c new file mode 100644 index 0000000..579ef2c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c new file mode 100644 index 0000000..1b9bae2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c @@ -0,0 +1,95 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: Linux specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +} + +/**************************************************************************** +REMARKS: +Use the gettimeofday() function to get microsecond precision (probably less +though) +****************************************************************************/ +static inline ulong __ULZReadTime(void) +{ + struct timeval t; + gettimeofday(&t, NULL); + return t.tv_sec*1000000 + t.tv_usec; +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +#define __LZTimerOn(tm) tm->start.low = __ULZReadTime() + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +#define __LZTimerLap(tm) (__ULZReadTime() - tm->start.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) tm->end.low = __ULZReadTime() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerCount(tm) (tm->end.low - tm->start.low) + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/makefile b/board/MAI/bios_emulator/scitech/src/pm/makefile new file mode 100644 index 0000000..265f0e3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/makefile @@ -0,0 +1,290 @@ +############################################################################# +# +# Copyright (C) 1996 SciTech Software. +# All rights reserved. +# +# Descripton: Generic makefile for the PM library. Builds the library +# file and all test programs. +# +############################################################################# + +.IMPORT .IGNORE : DEBUG_AGP_DRIVER TEST_HARNESS DEBUG_SDDPMI + +#---------------------------------------------------------------------------- +# Add DOS extender dependant flags to command line +#---------------------------------------------------------------------------- + +CFLAGS += $(DX_CFLAGS) +ASFLAGS += $(DX_ASFLAGS) +NO_PMLIB := 1 + +#---------------------------------------------------------------------------- +# Include definitions specific for the target system +#---------------------------------------------------------------------------- + +.IF $(USE_VXD) + +# Building for Win32 VxD (minimal PM library implementation) + +LIBNAME = pm +OBJECTS = pm$O vflat$O ztimer$O cpuinfo$O mtrr$O fileio$O pcilib$O \ + agp$O malloc$O vgastate$O gavxd$O _pm$O _mtrr$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := vxd;common;codepage;tests +.SOURCE: vxd common codepage tests + +.ELIF $(USE_NTDRV) + +# Building for NT device drivers (minimal PM library implementation) + +LIBNAME = pm +OBJECTS = pm$O vflat$O ztimer$O cpuinfo$O mtrr$O mem$O irq$O int86$O \ + stdio$O stdlib$O pcilib$O agp$O malloc$O vgastate$O gantdrv$O \ + _pm$O _mtrr$O _cpuinfo$O _int64$O _pcihelp$O _irq$O +DEPEND_SRC := ntdrv;common;codepage;tests +.SOURCE: ntdrv common codepage tests + +.ELIF $(USE_WIN32) + +# Building for Win32 + +CFLAGS += -DUSE_OS_JOYSTICK +LIBNAME = pm +OBJECTS = pm$O vflat$O event$O ddraw$O ztimer$O cpuinfo$O pcilib$O \ + agp$O malloc$O vgastate$O gawin32$O ntservc$O _joy$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := win32;common;codepage;tests +.SOURCE: win32 common codepage tests + +.ELIF $(USE_OS232) + +# Building for OS/2 + +.IF $(USE_OS2GUI) +LIBNAME = pm_pm +.ELSE +LIBNAME = pm +.ENDIF +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ + agp$O malloc$O vgastate$O gaos2$O _pmos2$O _joy$O _cpuinfo$O \ + _int64$O _pcihelp$O dossctl$O +DEPEND_SRC := os2;common;codepage;tests +.SOURCE: os2 common codepage tests + +.ELIF $(USE_QNX) + +# Building for QNX + +USE_BIOS := 1 +.IF $(USE_PHOTON) +LIBNAME = pm_ph +.ELIF $(USE_X11) +LIBNAME = pm_x11 +.ELSE +LIBNAME = pm +.ENDIF +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ + agp$O malloc$O mtrrqnx$O unixio$O vgastate$O gaqnx$O _joy$O \ + _mtrrqnx$O _cpuinfo$O _int64$O _pcihelp$O +DEPEND_SRC := qnx;common;codepage;tests +.SOURCE: qnx common codepage tests + +# Indicate that this program uses Nucleus device drivers (so needs I/O access) +USE_NUCLEUS := 1 + +.ELIF $(USE_LINUX) + +# Building for Linux + +CFLAGS += -DENABLE_MTRR -DUSE_OS_JOYSTICK +.IF $(USE_X11) +LIBNAME = pm_x11 +.ELSE +LIBNAME = pm +.ENDIF +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O pcilib$O \ + agp$O malloc$O unixio$O vgastate$O galinux$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := linux;common;codepage;tests;x11 +.SOURCE: linux common codepage tests x11 + +# Building a shared library +.IF $(SOFILE) +LIB := ld +LIBFLAGS := -r -o +CFLAGS += -fPIC +.ENDIF + +.ELIF $(USE_BEOS) + +# Building for BeOS GUI + +LIBNAME = pm +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O pcilib$O \ + agp$O malloc$O vgastate$O gabeos$O _joy$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := beos;common;codepage;tests +.SOURCE: beos common codepage tests + +.ELIF $(USE_SMX32) + +# Building for SMX + +LIBNAME = pm +OBJECTS = pm$O pmsmx$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ + agp$O malloc$O vgastate$O gasmx$O _pm$O _pmsmx$O _mtrr$O _event$O \ + _joy$O _cpuinfo$O _int64$O _pcihelp$O _lztimer$O +DEPEND_SRC := smx;common;codepage;tests +.SOURCE: smx common codepage tests + +.ELIF $(USE_RTTARGET) + +# Building for RTTarget-32 + +LIBNAME = pm +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ + agp$O malloc$O vgastate$O gartt$O _mtrr$O _joy$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := rttarget;common;codepage;tests +.SOURCE: rttarget common codepage tests + +.ELSE + +# Building for MSDOS + +LIBNAME = pm +OBJECTS = pm$O pmdos$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O \ + agp$O malloc$O pcilib$O vgastate$O gados$O \ + _pm$O _pmdos$O _mtrr$O _vflat$O _event$O _joy$O _pcihelp$O \ + _cpuinfo$O _int64$O _lztimer$O _dma$O +DEPEND_SRC := dos;common;codepage;tests +.SOURCE: dos common codepage tests + +.ENDIF + +# Object modules for keyboard code pages + +OBJECTS += us_eng$O + +# Common object modules + +OBJECTS += common$O +.IF $(CHECKED) +OBJECTS += debug$O +.ENDIF + +# Nucleus loader library object modules. Note that when compiling a test harness +# library we need to exclude the Nucleus loader library. + +.IF $(TEST_HARNESS) +CFLAGS += -DTEST_HARNESS -DPMLIB +LIBNAME = pm_test +.ELSE +OBJECTS += galib$O _ga_imp$O +.ENDIF + +.IF $(DEBUG_SDDPMI) +CFLAGS += -DDEBUG_SDDPMI +.ENDIF + +# AGP library object modules + +.IF $(DEBUG_AGP_DRIVER) +CFLAGS += -DDEBUG_AGP_DRIVER +OBJECTS += agplib$O +.ELSE +OBJECTS += agplib$O peloader$O libcimp$O _gatimer$O +.ENDIF + +#---------------------------------------------------------------------------- +# Name of library and generic object files required to build it +#---------------------------------------------------------------------------- + +.IF $(STKCALL) +LIBFILE = s$(LP)$(LIBNAME)$L +.ELSE +LIBFILE = $(LP)$(LIBNAME)$L +.ENDIF +LIBCLEAN = *.lib *.a + +#---------------------------------------------------------------------------- +# Change destination for library file depending the extender being used. This +# is only necessary for DOS extender since the file go into a subdirectory +# in the normal library directory, one for each supported extender. Other +# OS'es put the file into the regular library directory, since there is +# only one per OS in this case. +#---------------------------------------------------------------------------- + +MK_PMODE = 1 + +.IF $(TEST_HARNESS) +LIB_DEST := $(LIB_BASE) +.ELIF $(USE_TNT) +LIB_DEST := $(LIB_BASE)\tnt +.ELIF $(USE_DOS4GW) +LIB_DEST := $(LIB_BASE)\dos4gw +.ELIF $(USE_X32) +LIB_DEST := $(LIB_BASE)\x32 +.ELIF $(USE_DPMI16) +LIB_DEST := $(LIB_BASE)\dpmi16 +.ELIF $(USE_DPMI32) +LIB_DEST := $(LIB_BASE)\dpmi32 +.ELIF $(USE_DOSX) +LIB_DEST := $(LIB_BASE)\dosx +.END + +#---------------------------------------------------------------------------- +# Names of all executable files built +#---------------------------------------------------------------------------- + +.IF $(USE_REALDOS) +EXEFILES = memtest$E biosptr$E video$E isvesa$E callreal$E \ + mouse$E tick$E key$E key15$E brk$E altbrk$E \ + critical$E altcrit$E vftest$E rtc$E getch$E \ + cpu$E timerc$E timercpp$E showpci$E uswc$E block$E +.ELSE +EXEFILES = memtest$E video$E isvesa$E callreal$E vftest$E getch$E \ + cpu$E timerc$E timercpp$E showpci$E uswc$E block$E \ + save$E restore$E +.ENDIF + +all: $(EXEFILES) + +$(EXEFILES): $(LIBFILE) + +memtest$E: memtest$O +biosptr$E: biosptr$O +video$E: video$O +isvesa$E: isvesa$O +mouse$E: mouse$O +tick$E: tick$O +key$E: key$O +key15$E: key15$O +brk$E: brk$O +altbrk$E: altbrk$O +critical$E: critical$O +altcrit$E: altcrit$O +callreal$E: callreal$O +vftest$E: vftest$O +rtc$E: rtc$O +getch$E: getch$O +cpu$E: cpu$O +timerc$E: timerc$O +timercpp$E: timercpp$O +showpci$E: showpci$O +uswc$E: uswc$O +block$E: block$O +save$E: save$O +restore$E: restore$O +test$E: test$O _test$O + +#---------------------------------------------------------------------------- +# Define the list of object files to create dependency information for +#---------------------------------------------------------------------------- + +DEPEND_OBJ := $(OBJECTS) memtest$O biosptr$O video$O isvesa$O mouse$O \ + tick$O key$O key$O brk$O altbrk$O critical$O altcrit$O \ + callreal$O vftest$O getch$O timercpp$O + +.INCLUDE: "$(SCITECH)/makedefs/common.mk" + diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm new file mode 100644 index 0000000..11824a0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm @@ -0,0 +1,288 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit Windows NT device driver +;* +;* Description: Low level assembly support for the PM library specific to +;* Windows NT device drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _irq ; Set up memory model + +begdataseg _irq + + cextern _PM_rtcHandler,CPTR + cextern _PM_prevRTC,FCPTR + +RtcInside dw 0 ; Are we still handling current interrupt +sidtBuf df 0 ; Buffer for sidt instruction + +enddataseg _irq + +begcodeseg _irq ; Start of code segment + +cpublic _PM_irqCodeStart + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; PM_rtcISR - Real time clock interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_rtcISR + +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +; If we enable interrupts and call into any C based interrupt handling code, +; we need to setup a bunch of important information for the NT kernel. The +; code below takes care of this housekeeping for us (see Undocumented NT for +; details). If we don't do this housekeeping and interrupts are enabled, +; the kernel will become very unstable and crash within 10 seconds or so. +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + pushad + pushfd + push fs + + mov ebx,00000030h + mov fs,bx + sub esp,50h + mov ebp,esp + +; Setup the exception frame to NULL + + mov ebx,[DWORD cs:0FFDFF000h] + mov [DWORD ds:0FFDFF000h], 0FFFFFFFFh + mov [DWORD ebp],ebx + +; Save away the existing KSS ebp + + mov esi,[DWORD cs:0FFDFF124h] + mov ebx,[DWORD esi+00000128h] + mov [DWORD ebp+4h],ebx + mov [DWORD esi+00000128h],ebp + +; Save away the kernel time and the thread mode (kernel/user) + + mov edi,[DWORD esi+00000137h] + mov [DWORD ebp+8h],edi + +; Set the thread mode (kernel/user) based on the code selector + + mov ebx,[DWORD ebp+7Ch] + and ebx,01 + mov [BYTE esi+00000137h],bl + +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +; End of special interrupt Prolog code +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +; Clear priority interrupt controller and re-enable interrupts so we +; dont lock things up for long. + + mov al,20h + out 0A0h,al + out 020h,al + +; Clear real-time clock timeout + + in al,70h ; Read CMOS index register + push eax ; and save for later + IODELAYN 3 + mov al,0Ch + out 70h,al + IODELAYN 5 + in al,71h + +; Call the C interrupt handler function + + cmp [BYTE RtcInside],1 ; Check for mutual exclusion + je @@Exit + mov [BYTE RtcInside],1 + sti ; Enable interrupts + cld ; Clear direction flag for C code + call [CPTR _PM_rtcHandler] + cli ; Disable interrupts on exit! + mov [BYTE RtcInside],0 + +@@Exit: pop eax + out 70h,al ; Restore CMOS index register + +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +; Start of special epilog code to restore stuff on exit from handler +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +; Restore the KSS ebp + + mov esi,[DWORD cs:0FFDFF124h] + mov ebx,[DWORD ebp+4] + mov [DWORD esi+00000128h],ebx + +; Restore the exception frame + + mov ebx,[DWORD ebp] + mov [DWORD fs:00000000],ebx + +; Restore the thread mode + + mov ebx,[DWORD ebp+8h] + mov esi,[DWORD fs:00000124h] + mov [BYTE esi+00000137h],bl + add esp, 50h + pop fs + popfd + popad + +; Return from interrupt + + iret + +cprocend + +cpublic _PM_irqCodeEnd + +;---------------------------------------------------------------------------- +; void _PM_getISR(int irq,PMFARPTR *handler); +;---------------------------------------------------------------------------- +; Function to return the specific IRQ handler direct from the IDT. +;---------------------------------------------------------------------------- +cprocstart _PM_getISR + + ARG idtEntry:UINT, handler:DPTR + + enter_c 0 + mov ecx,[handler] ; Get address of handler to fill in + sidt [sidtBuf] ; Get IDTR register into sidtBuf + mov eax,[DWORD sidtBuf+2] ; Get address of IDT into EAX + mov ebx,[idtEntry] + lea eax,[eax+ebx*8] ; Get entry in the IDT + movzx edx,[WORD eax+6] ; Get high order 16-bits + shl edx,16 ; Move into top 16-bits of address + mov dx,[WORD eax] ; Get low order 16-bits + mov [DWORD ecx],edx ; Store linear address of handler + mov dx,[WORD eax+2] ; Get selector value + mov [WORD ecx+4],dx ; Store selector value + leave_c + ret + +cprocend _PM_getISR + +;---------------------------------------------------------------------------- +; void _PM_setISR(int irq,void *handler); +;---------------------------------------------------------------------------- +; Function to set the specific IRQ handler direct in the IDT. +;---------------------------------------------------------------------------- +cprocstart _PM_setISR + + ARG irq:UINT, handler:CPTR + + enter_c 0 + mov ecx,[handler] ; Get address of new handler + mov dx,cs ; Get selector for new handler + sidt [sidtBuf] ; Get IDTR register into sidtBuf + mov eax,[DWORD sidtBuf+2] ; Get address of IDT into EAX + mov ebx,[idtEntry] + lea eax,[eax+ebx*8] ; Get entry in the IDT + cli + mov [WORD eax+2],dx ; Store code segment selector + mov [WORD eax],cx ; Store low order bits of handler + shr ecx,16 + mov [WORD eax+6],cx ; Store high order bits of handler + sti + leave_c + ret + +cprocend _PM_setISR + +;---------------------------------------------------------------------------- +; void _PM_restoreISR(int irq,PMFARPTR *handler); +;---------------------------------------------------------------------------- +; Function to set the specific IRQ handler direct in the IDT. +;---------------------------------------------------------------------------- +cprocstart _PM_restoreISR + + ARG irq:UINT, handler:CPTR + + enter_c 0 + mov ecx,[handler] + mov dx,[WORD ecx+4] ; Get selector for old handler + mov ecx,[DWORD ecx] ; Get address of old handler + sidt [sidtBuf] ; Get IDTR register into sidtBuf + mov eax,[DWORD sidtBuf+2] ; Get address of IDT into EAX + mov ebx,[idtEntry] + lea eax,[eax+ebx*8] ; Get entry in the IDT + cli + mov [WORD eax+2],dx ; Store code segment selector + mov [WORD eax],cx ; Store low order bits of handler + shr ecx,16 + mov [WORD eax+6],cx ; Store high order bits of handler + sti + leave_c + ret + +cprocend _PM_restoreISR + +endcodeseg _irq + + END ; End of module + diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm new file mode 100644 index 0000000..6cb276d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm @@ -0,0 +1,281 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit Windows NT device driver +;* +;* Description: Low level assembly support for the PM library specific to +;* Windows NT device drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pm ; Set up memory model + +P586 + +begdataseg + +; Watcom C++ externals required to link when compiling floating point +; C code. They are not actually used in the code because we compile with +; inline floating point instructions, however the compiler still generates +; the references in the object modules. + +__8087 dd 0 + PUBLIC __8087 +__imthread: +__fltused: +_fltused_ dd 0 + PUBLIC __imthread + PUBLIC _fltused_ + PUBLIC __fltused + +enddataseg + +begcodeseg _pm ; Start of code segment + +;---------------------------------------------------------------------------- +; void PM_segread(PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Read the current value of all segment registers +;---------------------------------------------------------------------------- +cprocstart PM_segread + + ARG sregs:DPTR + + enter_c + + mov ax,es + _les _si,[sregs] + mov [_ES _si],ax + mov [_ES _si+2],cs + mov [_ES _si+4],ss + mov [_ES _si+6],ds + mov [_ES _si+8],fs + mov [_ES _si+10],gs + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Issues a software interrupt in protected mode. This routine has been +; written to allow user programs to load CS and DS with different values +; other than the default. +;---------------------------------------------------------------------------- +cprocstart PM_int386x + +; Not used for NT device drivers + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankA(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankA + +; Not used for NT device drivers + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankAB(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankAB + +; Not used for NT device drivers + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setCRTStart(int x,int y,int waitVRT) +;---------------------------------------------------------------------------- +cprocstart PM_setCRTStart + +; Not used for NT device drivers + + ret + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; uchar _PM_readCMOS(int index) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_readCMOS + + ARG index:UINT + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + in al,71h + mov ah,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + mov al,ah ; Return value in AL + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_writeCMOS(int index,uchar value) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_writeCMOS + + ARG index:UINT, value:UCHAR + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + mov al,[value] + out 71h,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; double _ftol(double f) +;---------------------------------------------------------------------------- +; Calls to __ftol are generated by the Borland C++ compiler for code +; that needs to convert a floating point type to an integral type. +; +; Input: floating point number on the top of the '87. +; +; Output: a (signed or unsigned) long in EAX +; All other registers preserved. +;----------------------------------------------------------------------- +cprocstart _ftol + + LOCAL temp1:WORD, temp2:QWORD = LocalSize + + push ebp + mov ebp,esp + sub esp,LocalSize + + fstcw [temp1] ; save the control word + fwait + mov al,[BYTE temp1+1] + or [BYTE temp1+1],0Ch ; set rounding control to chop + fldcw [temp1] + fistp [temp2] ; convert to 64-bit integer + mov [BYTE temp1+1],al + fldcw [temp1] ; restore the control word + mov eax,[DWORD temp2] ; return LS 32 bits + mov edx,[DWORD temp2+4] ; MS 32 bits + + mov esp,ebp + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_getPDB - Return the Page Table Directory Base address +;---------------------------------------------------------------------------- +cprocstart _PM_getPDB + + mov eax,cr3 + and eax,0FFFFF000h + ret + +cprocend + +;---------------------------------------------------------------------------- +; Flush the Translation Lookaside buffer +;---------------------------------------------------------------------------- +cprocstart PM_flushTLB + + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB + ret + +cprocend + +endcodeseg _pm + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c new file mode 100644 index 0000000..d15b07c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c @@ -0,0 +1,64 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: VxD specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Do nothing for VxD's +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for VxD's +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + KeQueryPerformanceCounter((LARGE_INTEGER*)freq); +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL); \ + (t)->low = lt.LowPart; \ + (t)->high = lt.HighPart; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c new file mode 100644 index 0000000..c82648b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c @@ -0,0 +1,251 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT device drivers. +* +* Description: Implementation for the real mode software interrupt +* handling functions. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" +#include "oshdr.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +We do have limited BIOS access under Windows NT device drivers. +****************************************************************************/ +ibool PMAPI PM_haveBIOSAccess(void) +{ + /* Return false unless we have full buffer passing! */ + return false; +} + +/**************************************************************************** +PARAMETERS: +len - Place to store the length of the buffer +rseg - Place to store the real mode segment of the buffer +roff - Place to store the real mode offset of the buffer + +REMARKS: +This function returns the address and length of the global VESA transfer +buffer that is used for communicating with the VESA BIOS functions from +Win16 and Win32 programs under Windows. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + /* No buffers supported under Windows NT (Windows XP has them however if */ + /* we ever decide to support this!) */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Issue a protected mode software interrupt. +****************************************************************************/ +int PMAPI PM_int386( + int intno, + PMREGS *in, + PMREGS *out) +{ + PMSREGS sregs; + PM_segread(&sregs); + return PM_int386x(intno,in,out,&sregs); +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + /* Not used for Windows NT drivers! */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + /* Not supported in NT drivers */ + (void)size; + (void)r_seg; + (void)r_off; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* Not supported in NT drivers */ + (void)mem; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + /* Not used in NT drivers */ +} + +/**************************************************************************** +REMARKS: +Call a V86 real mode function with the specified register values +loaded before the call. The call returns with a far ret. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *regs, + RMSREGS *sregs) +{ + /* TODO!! */ +#if 0 + CLIENT_STRUCT saveRegs; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) + return; + + TRACE("SDDHELP: Entering PM_callRealMode()\n"); + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,regs,sregs); + Simulate_Far_Call(seg, off); + Resume_Exec(); + ReadV86Registers(&saveRegs,regs,sregs); + End_Nest_Exec(); + TRACE("SDDHELP: Exiting PM_callRealMode()\n"); +#endif +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + /* TODO!! */ +#if 0 + RMSREGS sregs = {0}; + CLIENT_STRUCT saveRegs; + ushort oldDisable; + + /* Disable pass-up to our VxD handler so we directly call BIOS */ + TRACE("SDDHELP: Entering PM_int86()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,in,&sregs); + Exec_Int(intno); + ReadV86Registers(&saveRegs,out,&sregs); + End_Nest_Exec(); + + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; + + TRACE("SDDHELP: Exiting PM_int86()\n"); +#else + *out = *in; +#endif + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + /* TODO!! */ +#if 0 + CLIENT_STRUCT saveRegs; + ushort oldDisable; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) { + *out = *in; + return out->x.ax; + } + + /* Disable pass-up to our VxD handler so we directly call BIOS */ + TRACE("SDDHELP: Entering PM_int86x()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,in,sregs); + Exec_Int(intno); + ReadV86Registers(&saveRegs,out,sregs); + End_Nest_Exec(); + + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; + + TRACE("SDDHELP: Exiting PM_int86x()\n"); +#else + *out = *in; +#endif + return out->x.ax; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c new file mode 100644 index 0000000..9cd5204 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c @@ -0,0 +1,142 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT device drivers. +* +* Description: Implementation for the NT driver IRQ management functions +* for the PM library. +* +****************************************************************************/ + +#include "pmapi.h" +#include "pmint.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" +#include "oshdr.h" + +/*--------------------------- Global variables ----------------------------*/ + +static int globalDataStart; +static uchar _PM_oldCMOSRegA; +static uchar _PM_oldCMOSRegB; +static uchar _PM_oldRTCPIC2; +static ulong RTC_idtEntry; +PM_intHandler _PM_rtcHandler = NULL; +PMFARPTR _VARAPI _PM_prevRTC = PMNULL; + +/*----------------------------- Implementation ----------------------------*/ + +/* Functions to read and write CMOS registers */ + +uchar _ASMAPI _PM_readCMOS(int index); +void _ASMAPI _PM_writeCMOS(int index,uchar value); +void _ASMAPI _PM_rtcISR(void); +void _ASMAPI _PM_getISR(int irq,PMFARPTR *handler); +void _ASMAPI _PM_setISR(int irq,void *handler); +void _ASMAPI _PM_restoreISR(int irq,PMFARPTR *handler); +void _ASMAPI _PM_irqCodeStart(void); +void _ASMAPI _PM_irqCodeEnd(void); + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + static short convert[] = { + 8192, + 4096, + 2048, + 1024, + 512, + 256, + 128, + 64, + 32, + 16, + 8, + 4, + 2, + -1, + }; + int i; + + /* First clear any pending RTC timeout if not cleared */ + _PM_readCMOS(0x0C); + if (frequency == 0) { + /* Disable RTC timout */ + _PM_writeCMOS(0x0A,(uchar)_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,(uchar)(_PM_oldCMOSRegB & 0x0F)); + } + else { + /* Convert frequency value to RTC clock indexes */ + for (i = 0; convert[i] != -1; i++) { + if (convert[i] == frequency) + break; + } + + /* Set RTC timout value and enable timeout */ + _PM_writeCMOS(0x0A,(uchar)(0x20 | (i+3))); + _PM_writeCMOS(0x0B,(uchar)((_PM_oldCMOSRegB & 0x0F) | 0x40)); + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + static ibool locked = false; + + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Install the interrupt handler */ + RTC_idtEntry = 0x38; + _PM_getISR(RTC_idtEntry, &_PM_prevRTC); + _PM_rtcHandler = th; + _PM_setISR(RTC_idtEntry, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,(uchar)(_PM_oldRTCPIC2 & 0xFE)); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(uchar)((PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE))); + + /* Restore the interrupt vector */ + _PM_restoreISR(RTC_idtEntry, &_PM_prevRTC); + _PM_rtcHandler = NULL; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c new file mode 100644 index 0000000..3128c6a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c @@ -0,0 +1,518 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT device drivers. +* +* Description: Implementation for the NT driver memory management functions +* for the PM library. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" +#include "oshdr.h" + +/*--------------------------- Global variables ----------------------------*/ + +#define MAX_MEMORY_SHARED 100 +#define MAX_MEMORY_MAPPINGS 100 +#define MAX_MEMORY_LOCKED 100 + +typedef struct { + void *linear; + ulong length; + PMDL pMdl; + } memshared; + +typedef struct { + void *linear; + void *mmIoMapped; + ulong length; + PMDL pMdl; + } memlocked; + +typedef struct { + ulong physical; + ulong linear; + ulong length; + ibool isCached; + } mmapping; + +static int numMappings = 0; +static memshared shared[MAX_MEMORY_MAPPINGS] = {0}; +static mmapping maps[MAX_MEMORY_MAPPINGS]; +static memlocked locked[MAX_MEMORY_LOCKED]; + +/*----------------------------- Implementation ----------------------------*/ + +ulong PMAPI _PM_getPDB(void); + +/* Page table entry flags */ + +#define PAGE_FLAGS_PRESENT 0x00000001 +#define PAGE_FLAGS_WRITEABLE 0x00000002 +#define PAGE_FLAGS_USER 0x00000004 +#define PAGE_FLAGS_WRITE_THROUGH 0x00000008 +#define PAGE_FLAGS_CACHE_DISABLE 0x00000010 +#define PAGE_FLAGS_ACCESSED 0x00000020 +#define PAGE_FLAGS_DIRTY 0x00000040 +#define PAGE_FLAGS_4MB 0x00000080 + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to maps in +limit - Limit of physical memory to region to maps in + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +Maps a physical memory range to a linear memory range. +****************************************************************************/ +static ulong _PM_mapPhysicalToLinear( + ulong base, + ulong limit, + ibool isCached) +{ + ulong length = limit+1; + PHYSICAL_ADDRESS paIoBase = {0}; + + /* NT loves large Ints */ + paIoBase = RtlConvertUlongToLargeInteger( base ); + + /* Map IO space into Kernel */ + if (isCached) + return (ULONG)MmMapIoSpace(paIoBase, length, MmCached ); + else + return (ULONG)MmMapIoSpace(paIoBase, length, MmNonCached ); +} + +/**************************************************************************** +REMARKS: +Adjust the page table caching bits directly. Requires ring 0 access and +only works with DOS4GW and compatible extenders (CauseWay also works since +it has direct support for the ring 0 instructions we need from ring 3). Will +not work in a DOS box, but we call into the ring 0 helper VxD so we should +never get here in a DOS box anyway (assuming the VxD is present). If we +do get here and we are in windows, this code will be skipped. +****************************************************************************/ +static void _PM_adjustPageTables( + ulong linear, + ulong limit, + ibool isGlobal, + ibool isCached) +{ + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPDB,*pPageTable; + ulong mask = 0xFFFFFFFF; + ulong bits = 0x00000000; + + /* Enable user level access for page table entry */ + if (isGlobal) { + mask &= ~PAGE_FLAGS_USER; + bits |= PAGE_FLAGS_USER; + } + + /* Disable PCD bit if page table entry should be uncached */ + if (!isCached) { + mask &= ~(PAGE_FLAGS_CACHE_DISABLE | PAGE_FLAGS_WRITE_THROUGH); + bits |= (PAGE_FLAGS_CACHE_DISABLE | PAGE_FLAGS_WRITE_THROUGH); + } + + pPDB = (ulong*)_PM_mapPhysicalToLinear(_PM_getPDB(),0xFFF,true); + if (pPDB) { + startPDB = (linear >> 22) & 0x3FF; + startPage = (linear >> 12) & 0x3FF; + endPDB = ((linear+limit) >> 22) & 0x3FF; + endPage = ((linear+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + /* Set the bits in the page directory entry - required as per */ + /* Pentium 4 manual. This also takes care of the 4MB page entries */ + pPDB[iPDB] = (pPDB[iPDB] & mask) | bits; + if (!(pPDB[iPDB] & PAGE_FLAGS_4MB)) { + /* If we are dealing with 4KB pages then we need to iterate */ + /* through each of the page table entries */ + pageTable = pPDB[iPDB] & ~0xFFF; + pPageTable = (ulong*)_PM_mapPhysicalToLinear(pageTable,0xFFF,true); + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) { + pPageTable[iPage] = (pPageTable[iPage] & mask) | bits; + } + MmUnmapIoSpace(pPageTable,0xFFF); + } + } + MmUnmapIoSpace(pPDB,0xFFF); + PM_flushTLB(); + } +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For NT we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + int i; + + /* First find a free slot in our shared memory table */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].linear == 0) + break; + } + if (i == MAX_MEMORY_SHARED) + return NULL; + + /* Allocate the paged pool */ + shared[i].linear = ExAllocatePool(PagedPool, size); + + /* Create a list to manage this allocation */ + shared[i].pMdl = IoAllocateMdl(shared[i].linear,size,FALSE,FALSE,(PIRP) NULL); + + /* Lock this allocation in memory */ + MmProbeAndLockPages(shared[i].pMdl,KernelMode,IoModifyAccess); + + /* Modify bits to grant user access */ + _PM_adjustPageTables((ulong)shared[i].linear, size, true, true); + return (void*)shared[i].linear; +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory +****************************************************************************/ +void PMAPI PM_freeShared( + void *p) +{ + int i; + + /* Find a shared memory block in our table and free it */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].linear == p) { + /* Unlock what we locked */ + MmUnlockPages(shared[i].pMdl); + + /* Free our MDL */ + IoFreeMdl(shared[i].pMdl); + + /* Free our mem */ + ExFreePool(shared[i].linear); + + /* Flag that is entry is available */ + shared[i].linear = 0; + break; + } + } +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + ulong linear,length = limit+1; + int i; + + /* Search table of existing mappings to see if we have already mapped */ + /* a region of memory that will serve this purpose. */ + for (i = 0; i < numMappings; i++) { + if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) { + _PM_adjustPageTables((ulong)maps[i].linear, maps[i].length, true, isCached); + return (void*)maps[i].linear; + } + } + if (numMappings == MAX_MEMORY_MAPPINGS) + return NULL; + + /* We did not find any previously mapped memory region, so maps it in. */ + if ((linear = _PM_mapPhysicalToLinear(base,limit,isCached)) == 0xFFFFFFFF) + return NULL; + maps[numMappings].physical = base; + maps[numMappings].length = length; + maps[numMappings].linear = linear; + maps[numMappings].isCached = isCached; + numMappings++; + + /* Grant user access to this I/O space */ + _PM_adjustPageTables((ulong)linear, length, true, isCached); + return (void*)linear; +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* We don't free the memory mappings in here because we cache all */ + /* the memory mappings we create in the system for later use. */ +} + +/**************************************************************************** +REMARKS: +Called when the device driver unloads to free all the page table mappings! +****************************************************************************/ +void PMAPI _PM_freeMemoryMappings(void) +{ + int i; + + for (i = 0; i < numMappings; i++) + MmUnmapIoSpace((void *)maps[i].linear,maps[i].length); +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ulong PMAPI PM_getPhysicalAddr( + void *p) +{ + PHYSICAL_ADDRESS paOurAddress; + + paOurAddress = MmGetPhysicalAddress(p); + return paOurAddress.LowPart; +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + int i; + ulong linear = (ulong)p & ~0xFFF; + + for (i = (length + 0xFFF) >> 12; i > 0; i--) { + if ((*physAddress++ = PM_getPhysicalAddr((void*)linear)) == 0xFFFFFFFF) + return false; + linear += 4096; + } + return true; +} + +/**************************************************************************** +REMARKS: +Allocates a block of locked physical memory. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + int i; + PHYSICAL_ADDRESS paOurAddress; + + /* First find a free slot in our shared memory table */ + for (i = 0; i < MAX_MEMORY_LOCKED; i++) { + if (locked[i].linear == 0) + break; + } + if (i == MAX_MEMORY_LOCKED) + return NULL; + + /* HighestAcceptableAddress - Specifies the highest valid physical address */ + /* the driver can use. For example, if a device can only reference physical */ + /* memory in the lower 16MB, this value would be set to 0x00000000FFFFFF. */ + paOurAddress.HighPart = 0; + if (below16M) + paOurAddress.LowPart = 0x00FFFFFF; + else + paOurAddress.LowPart = 0xFFFFFFFF; + + if (contiguous) { + /* Allocate from the non-paged pool (unfortunately 4MB pages) */ + locked[i].linear = MmAllocateContiguousMemory(size, paOurAddress); + if (!locked[i].linear) + return NULL; + + /* Flag no MDL */ + locked[i].pMdl = NULL; + + /* Map the physical address for the memory so we can manage */ + /* the page tables in 4KB chunks mapped into user space. */ + + /* TODO: Map this with the physical address to the linear addresss */ + locked[i].mmIoMapped = locked[i].linear; + + /* Modify bits to grant user access, flag not cached */ + _PM_adjustPageTables((ulong)locked[i].mmIoMapped, size, true, false); + return (void*)locked[i].mmIoMapped; + } + else { + /* Allocate from the paged pool */ + locked[i].linear = ExAllocatePool(PagedPool, size); + if (!locked[i].linear) + return NULL; + + /* Create a list to manage this allocation */ + locked[i].pMdl = IoAllocateMdl(locked[i].linear,size,FALSE,FALSE,(PIRP) NULL); + + /* Lock this allocation in memory */ + MmProbeAndLockPages(locked[i].pMdl,KernelMode,IoModifyAccess); + + /* Modify bits to grant user access, flag not cached */ + _PM_adjustPageTables((ulong)locked[i].linear, size, true, false); + return (void*)locked[i].linear; + } +} + +/**************************************************************************** +REMARKS: +Frees a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + int i; + + /* Find a locked memory block in our table and free it */ + for (i = 0; i < MAX_MEMORY_LOCKED; i++) { + if (locked[i].linear == p) { + /* An Mdl indicates that we used the paged pool, and locked it, */ + /* so now we have to unlock, free the MDL, and free paged */ + if (locked[i].pMdl) { + /* Unlock what we locked and free the Mdl */ + MmUnlockPages(locked[i].pMdl); + IoFreeMdl(locked[i].pMdl); + ExFreePool(locked[i].linear); + } + else { + /* TODO: Free the mmIoMap mapping for the memory! */ + + /* Free non-paged pool */ + MmFreeContiguousMemory(locked[i].linear); + } + + /* Flag that is entry is available */ + locked[i].linear = 0; + break; + } + } +} + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ + /* Allocate the memory from the non-paged pool if we want the memory */ + /* to be locked. */ + return ExAllocatePool( + locked ? NonPagedPoolCacheAligned : PagedPoolCacheAligned, + PAGE_SIZE); +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ + if (p) ExFreePool(p); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages( + void *p, + uint len, + PM_lockHandle *lh) +{ + MDL *pMdl; + + /* Create a list to manage this allocation */ + if ((pMdl = IoAllocateMdl(p,len,FALSE,FALSE,(PIRP)NULL)) == NULL) + return false; + + /* Lock this allocation in memory */ + MmProbeAndLockPages(pMdl,KernelMode,IoModifyAccess); + *((PMDL*)(&lh->h)) = pMdl; + return true; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages( + void *p, + uint len, + PM_lockHandle *lh) +{ + if (p && lh) { + /* Unlock what we locked */ + MDL *pMdl = *((PMDL*)(&lh->h)); + MmUnlockPages(pMdl); + IoFreeMdl(pMdl); + } + return true; +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lh) +{ + return PM_lockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lh) +{ + return PM_unlockDataPages((void*)p,len,lh); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h new file mode 100644 index 0000000..65b7bae --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT drivers +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#ifndef __NTDRV_OSHDR_H +#define __NTDRV_OSHDR_H + +/*--------------------------- Macros and Typedefs -------------------------*/ + +/*---------------------------- Global variables ---------------------------*/ + +/*--------------------------- Function Prototypes -------------------------*/ + +/* Internal unicode string handling functions */ + +UNICODE_STRING * _PM_CStringToUnicodeString(const char *cstr); +void _PM_FreeUnicodeString(UNICODE_STRING *uniStr); + +#endif /* __NTDRV_OSHDR_H */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c new file mode 100644 index 0000000..c660631 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c @@ -0,0 +1,933 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT device drivers. +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" +#include "oshdr.h" + +/*--------------------------- Global variables ----------------------------*/ + +char _PM_cntPath[PM_MAX_PATH] = ""; +char _PM_nucleusPath[PM_MAX_PATH] = ""; +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +static char *szNTWindowsKey = "\\REGISTRY\\Machine\\Software\\Microsoft\\Windows NT\\CurrentVersion"; +static char *szNTSystemRoot = "SystemRoot"; +static char *szMachineNameKey = "\\REGISTRY\\Machine\\System\\CurrentControlSet\\control\\ComputerName\\ComputerName"; +static char *szMachineNameKeyNT = "\\REGISTRY\\Machine\\System\\CurrentControlSet\\control\\ComputerName\\ActiveComputerName"; +static char *szMachineName = "ComputerName"; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the PM library. +****************************************************************************/ +void PMAPI PM_init(void) +{ + /* Initialiase the MTRR module */ + MTRR_init(); +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + return _OS_WINNTDRV; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier. +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ + return PM_386; +} + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Handle fatal errors internally in the driver. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + ULONG BugCheckCode = 0; + ULONG MoreBugCheckData[4] = {0}; + char *p; + ULONG len; + + if (fatalErrorCleanup) + fatalErrorCleanup(); + +#ifdef DBG /* Send output to debugger, just return so as not to force a reboot */ +#pragma message("INFO: building for debug, PM_fatalError() re-routed") + DBGMSG2("SDDHELP> PM_fatalError(): ERROR: %s\n", msg); + return ; +#endif + /* KeBugCheckEx brings down the system in a controlled */ + /* manner when the caller discovers an unrecoverable */ + /* inconsistency that would corrupt the system if */ + /* the caller continued to run. */ + /* */ + /* hack - dump the first 20 chars in hex using the variables */ + /* provided - Each ULONG is equal to four characters... */ + for(len = 0; len < 20; len++) + if (msg[len] == (char)0) + break; + + /* This looks bad but it's quick and reliable... */ + p = (char *)&BugCheckCode; + if(len > 0) p[3] = msg[0]; + if(len > 1) p[2] = msg[1]; + if(len > 2) p[1] = msg[2]; + if(len > 3) p[0] = msg[3]; + + p = (char *)&MoreBugCheckData[0]; + if(len > 4) p[3] = msg[4]; + if(len > 5) p[2] = msg[5]; + if(len > 6) p[1] = msg[6]; + if(len > 7) p[0] = msg[7]; + + p = (char *)&MoreBugCheckData[1]; + if(len > 8) p[3] = msg[8]; + if(len > 9) p[2] = msg[9]; + if(len > 10) p[1] = msg[10]; + if(len > 11) p[0] = msg[11]; + + p = (char *)&MoreBugCheckData[2]; + if(len > 12) p[3] = msg[12]; + if(len > 13) p[2] = msg[13]; + if(len > 14) p[1] = msg[14]; + if(len > 15) p[0] = msg[15]; + + p = (char *)&MoreBugCheckData[3]; + if(len > 16) p[3] = msg[16]; + if(len > 17) p[2] = msg[17]; + if(len > 18) p[1] = msg[18]; + if(len > 19) p[0] = msg[19]; + + /* Halt the system! */ + KeBugCheckEx(BugCheckCode, MoreBugCheckData[0], MoreBugCheckData[1], MoreBugCheckData[2], MoreBugCheckData[3]); +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + strncpy(path,_PM_cntPath,maxLen); + path[maxLen-1] = 0; + return path; +} + +/**************************************************************************** +PARAMETERS: +szKey - Key to query (can contain version number formatting) +szValue - Value to get information for +value - Place to store the registry key data read +size - Size of the string buffer to read into + +RETURNS: +true if the key was found, false if not. +****************************************************************************/ +static ibool REG_queryString( + char *szKey, + const char *szValue, + char *value, + DWORD size) +{ + ibool status; + NTSTATUS rval; + ULONG length; + HANDLE Handle; + OBJECT_ATTRIBUTES keyAttributes; + UNICODE_STRING *uniKey = NULL; + UNICODE_STRING *uniValue = NULL; + PKEY_VALUE_FULL_INFORMATION fullInfo = NULL; + STRING stringdata; + UNICODE_STRING unidata; + + /* Convert strings to UniCode */ + status = false; + if ((uniKey = _PM_CStringToUnicodeString(szKey)) == NULL) + goto Exit; + if ((uniValue = _PM_CStringToUnicodeString(szValue)) == NULL) + goto Exit; + + /* Open the key */ + InitializeObjectAttributes( &keyAttributes, + uniKey, + OBJ_CASE_INSENSITIVE, + NULL, + NULL ); + rval = ZwOpenKey( &Handle, + KEY_ALL_ACCESS, + &keyAttributes ); + if (!NT_SUCCESS(rval)) + goto Exit; + + /* Query the value */ + length = sizeof (KEY_VALUE_FULL_INFORMATION) + + size * sizeof(WCHAR); + if ((fullInfo = ExAllocatePool (PagedPool, length)) == NULL) + goto Exit; + RtlZeroMemory(fullInfo, length); + rval = ZwQueryValueKey (Handle, + uniValue, + KeyValueFullInformation, + fullInfo, + length, + &length); + if (NT_SUCCESS (rval)) { + /* Create the UniCode string so we can convert it */ + unidata.Buffer = (PWCHAR)(((PCHAR)fullInfo) + fullInfo->DataOffset); + unidata.Length = (USHORT)fullInfo->DataLength; + unidata.MaximumLength = (USHORT)fullInfo->DataLength + sizeof(WCHAR); + + /* Convert unicode univalue to ansi string. */ + rval = RtlUnicodeStringToAnsiString(&stringdata, &unidata, TRUE); + if (NT_SUCCESS(rval)) { + strcpy(value,stringdata.Buffer); + status = true; + } + } + +Exit: + if (fullInfo) ExFreePool(fullInfo); + if (uniKey) _PM_FreeUnicodeString(uniKey); + if (uniValue) _PM_FreeUnicodeString(uniValue); + return status; +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + char path[256]; + if (REG_queryString(szNTWindowsKey,szNTSystemRoot,path,sizeof(path))) + return 'c'; + return path[0]; +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files. +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + return "c:\\"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + + if (strlen(_PM_nucleusPath) > 0) { + strcpy(path,_PM_nucleusPath); + PM_backslash(path); + return path; + } + if (!REG_queryString(szNTWindowsKey,szNTSystemRoot,path,sizeof(path))) + strcpy(path,"c:\\winnt"); + PM_backslash(path); + strcat(path,"system32\\nucleus"); + return path; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + return PM_getMachineName(); +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + static char name[256]; + + if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name))) + return name; + if (REG_queryString(szMachineNameKeyNT,szMachineName,name,sizeof(name))) + return name; + return "Unknown"; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + /* Not used in NT drivers */ + return true; +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + /* Not used in NT drivers */ + return 0xD; +} + +/**************************************************************************** +REMARKS: +Open a console for output to the screen, creating the main event handling +window if necessary. +****************************************************************************/ +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + /* Not used in NT drivers */ + (void)hwndUser; + (void)device; + (void)xRes; + (void)yRes; + (void)bpp; + (void)fullScreen; + return NULL; +} + +/**************************************************************************** +REMARKS: +Find the size of the console state buffer. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + /* Not used in NT drivers */ + return 1; +} + +/**************************************************************************** +REMARKS: +Save the state of the console. +****************************************************************************/ +void PMAPI PM_saveConsoleState( + void *stateBuf, + PM_HWND hwndConsole) +{ + /* Not used in NT drivers */ + (void)stateBuf; + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Set the suspend application callback for the fullscreen console. +****************************************************************************/ +void PMAPI PM_setSuspendAppCallback( + PM_saveState_cb saveState) +{ + /* Not used in NT drivers */ + (void)saveState; +} + +/**************************************************************************** +REMARKS: +Restore the console state. +****************************************************************************/ +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + PM_HWND hwndConsole) +{ + /* Not used in NT drivers */ + (void)stateBuf; + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Close the fullscreen console. +****************************************************************************/ +void PMAPI PM_closeConsole( + PM_HWND hwndConsole) +{ + /* Not used in NT drivers */ + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PMAPI PM_setOSCursorLocation( + int x, + int y) +{ + /* Nothing to do for Windows */ + (void)x; + (void)y; +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PMAPI PM_setOSScreenWidth( + int width, + int height) +{ + /* Nothing to do for Windows */ + (void)width; + (void)height; +} + +/**************************************************************************** +REMARKS: +Maps a shared memory block into process address space. Does nothing since +the memory blocks are already globally mapped into all processes. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + /* Not used anymore */ + (void)base; + (void)limit; + return NULL; +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + /* This may not be possible in NT and should be done by the OS anyway */ + (void)axVal; + (void)BIOSPhysAddr; + (void)mappedBIOS; + (void)BIOSLen; + return false; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + /* Note that on NT this probably does not do what we expect! */ + return PM_mapPhysicalAddr(0x400, 0x1000, true); +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + return PM_mapPhysicalAddr(0xA0000,0xFFFF,false); +} + +/**************************************************************************** +REMARKS: +Sleep for the specified number of milliseconds. +****************************************************************************/ +void PMAPI PM_sleep( + ulong milliseconds) +{ + /* We never use this in NT drivers */ + (void)milliseconds; +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified COM port. +****************************************************************************/ +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + case 2: return 0x3E8; + case 3: return 0x2E8; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified LPT port. +****************************************************************************/ +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Returns available memory. Not possible under Windows. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* Not used in NT drivers */ + (void)szDLLName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* Not used in NT drivers */ + (void)hModule; + (void)szProcName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* Not used in NT drivers */ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + /* Not supported in NT drivers */ + (void)drive; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + /* Not supported in NT drivers */ + (void)drive; + (void)dir; + (void)len; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + return MTRR_enableWriteCombine(base,size,type); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + NTSTATUS status; + ACCESS_MASK DesiredAccess = GENERIC_READ | GENERIC_WRITE; + OBJECT_ATTRIBUTES ObjectAttributes; + ULONG ShareAccess = FILE_SHARE_READ; + ULONG CreateDisposition = FILE_OPEN; + HANDLE FileHandle = NULL; + UNICODE_STRING *uniFile = NULL; + IO_STATUS_BLOCK IoStatusBlock; + FILE_BASIC_INFORMATION FileBasic; + char kernelFilename[PM_MAX_PATH+5]; + ULONG FileAttributes = 0; + + /* Convert file attribute flags */ + if (attrib & PM_FILE_READONLY) + FileAttributes |= FILE_ATTRIBUTE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + FileAttributes |= FILE_ATTRIBUTE_ARCHIVE; + if (attrib & PM_FILE_HIDDEN) + FileAttributes |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + FileAttributes |= FILE_ATTRIBUTE_SYSTEM; + + /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */ + strcpy(kernelFilename, "\\??\\"); + strcat(kernelFilename, filename); + + /* Convert filename string to ansi string */ + if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL) + goto Exit; + + /* Must open a file to query it's attributes */ + InitializeObjectAttributes (&ObjectAttributes, + uniFile, + OBJ_CASE_INSENSITIVE, + NULL, + NULL ); + status = ZwCreateFile( &FileHandle, + DesiredAccess | SYNCHRONIZE, + &ObjectAttributes, + &IoStatusBlock, + NULL, /*AllocationSize OPTIONAL, */ + FILE_ATTRIBUTE_NORMAL, + ShareAccess, + CreateDisposition, + FILE_RANDOM_ACCESS, /*CreateOptions, */ + NULL, /*EaBuffer OPTIONAL, */ + 0 /*EaLength (required if EaBuffer) */ + ); + if (!NT_SUCCESS (status)) + goto Exit; + + /* Query timestamps */ + status = ZwQueryInformationFile(FileHandle, + &IoStatusBlock, + &FileBasic, + sizeof(FILE_BASIC_INFORMATION), + FileBasicInformation + ); + if (!NT_SUCCESS (status)) + goto Exit; + + /* Change the four bits we change */ + FileBasic.FileAttributes &= ~(FILE_ATTRIBUTE_READONLY | FILE_ATTRIBUTE_ARCHIVE + | FILE_ATTRIBUTE_HIDDEN | FILE_ATTRIBUTE_SYSTEM); + FileBasic.FileAttributes |= FileAttributes; + + /* Set timestamps */ + ZwSetInformationFile( FileHandle, + &IoStatusBlock, + &FileBasic, + sizeof(FILE_BASIC_INFORMATION), + FileBasicInformation + ); + +Exit: + if (FileHandle) ZwClose(FileHandle); + if (uniFile) _PM_FreeUnicodeString(uniFile); + return; +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + NTSTATUS status; + ACCESS_MASK DesiredAccess = GENERIC_READ | GENERIC_WRITE; + OBJECT_ATTRIBUTES ObjectAttributes; + ULONG ShareAccess = FILE_SHARE_READ; + ULONG CreateDisposition = FILE_OPEN; + HANDLE FileHandle = NULL; + UNICODE_STRING *uniFile = NULL; + IO_STATUS_BLOCK IoStatusBlock; + FILE_BASIC_INFORMATION FileBasic; + char kernelFilename[PM_MAX_PATH+5]; + ULONG FileAttributes = 0; + uint retval = 0; + + /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */ + strcpy(kernelFilename, "\\??\\"); + strcat(kernelFilename, filename); + + /* Convert filename string to ansi string */ + if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL) + goto Exit; + + /* Must open a file to query it's attributes */ + InitializeObjectAttributes (&ObjectAttributes, + uniFile, + OBJ_CASE_INSENSITIVE, + NULL, + NULL ); + status = ZwCreateFile( &FileHandle, + DesiredAccess | SYNCHRONIZE, + &ObjectAttributes, + &IoStatusBlock, + NULL, /*AllocationSize OPTIONAL, */ + FILE_ATTRIBUTE_NORMAL, + ShareAccess, + CreateDisposition, + FILE_RANDOM_ACCESS, /*CreateOptions, */ + NULL, /*EaBuffer OPTIONAL, */ + 0 /*EaLength (required if EaBuffer) */ + ); + if (!NT_SUCCESS (status)) + goto Exit; + + /* Query timestamps */ + status = ZwQueryInformationFile(FileHandle, + &IoStatusBlock, + &FileBasic, + sizeof(FILE_BASIC_INFORMATION), + FileBasicInformation + ); + if (!NT_SUCCESS (status)) + goto Exit; + + /* Translate the file attributes */ + if (FileBasic.FileAttributes & FILE_ATTRIBUTE_READONLY) + retval |= PM_FILE_READONLY; + if (FileBasic.FileAttributes & FILE_ATTRIBUTE_ARCHIVE) + retval |= PM_FILE_ARCHIVE; + if (FileBasic.FileAttributes & FILE_ATTRIBUTE_HIDDEN) + retval |= PM_FILE_HIDDEN; + if (FileBasic.FileAttributes & FILE_ATTRIBUTE_SYSTEM) + retval |= PM_FILE_SYSTEM; + +Exit: + if (FileHandle) ZwClose(FileHandle); + if (uniFile) _PM_FreeUnicodeString(uniFile); + return retval; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + /* Not supported in NT drivers */ + (void)filename; + return false; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + /* Not supported in NT drivers */ + (void)filename; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* Not supported in NT drivers */ + (void)filename; + (void)gmTime; + (void)time; + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* Not supported in NT drivers */ + (void)filename; + (void)gmTime; + (void)time; + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c new file mode 100644 index 0000000..658f1c8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c @@ -0,0 +1,330 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT driver +* +* Description: C library compatible I/O functions for use within a Windows +* NT driver. +* +****************************************************************************/ + +#include "pmapi.h" +#include "oshdr.h" + +/*------------------------ Main Code Implementation -----------------------*/ + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fopen function. +****************************************************************************/ +FILE * fopen( + const char *filename, + const char *mode) +{ + ACCESS_MASK DesiredAccess; /* for ZwCreateFile... */ + OBJECT_ATTRIBUTES ObjectAttributes; + ULONG ShareAccess; + ULONG CreateDisposition; + NTSTATUS status; + HANDLE FileHandle; + UNICODE_STRING *uniFile = NULL; + PWCHAR bufFile = NULL; + IO_STATUS_BLOCK IoStatusBlock; + FILE_STANDARD_INFORMATION FileInformation; + FILE_POSITION_INFORMATION FilePosition; + char kernelFilename[PM_MAX_PATH+5]; + FILE *f; + + /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */ + strcpy(kernelFilename, "\\??\\"); + strcat(kernelFilename, filename); + if ((f = PM_malloc(sizeof(FILE))) == NULL) + goto Error; + f->offset = 0; + f->text = (mode[1] == 't' || mode[2] == 't'); + f->writemode = (mode[0] == 'w') || (mode[0] == 'a'); + if (mode[0] == 'r') { + /* omode = OPEN_ACCESS_READONLY | OPEN_SHARE_COMPATIBLE; */ + /* action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_FAIL; */ + DesiredAccess = GENERIC_READ; + ShareAccess = FILE_SHARE_READ | FILE_SHARE_WRITE; + CreateDisposition = FILE_OPEN; + } + else if (mode[0] == 'w') { + /* omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_COMPATIBLE; */ + /* action = ACTION_IFEXISTS_TRUNCATE | ACTION_IFNOTEXISTS_CREATE; */ + DesiredAccess = GENERIC_WRITE; + ShareAccess = FILE_SHARE_READ | FILE_SHARE_WRITE; + CreateDisposition = FILE_SUPERSEDE; + } + else { + /* omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_COMPATIBLE; */ + /* action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_CREATE; */ + DesiredAccess = GENERIC_READ | GENERIC_WRITE; + ShareAccess = FILE_SHARE_READ; + CreateDisposition = FILE_OPEN_IF; + } + + /* Convert filename string to ansi string and then to UniCode string */ + if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL) + return NULL; + + /* Create the file */ + InitializeObjectAttributes (&ObjectAttributes, + uniFile, + OBJ_CASE_INSENSITIVE, + NULL, + NULL); + status = ZwCreateFile( &FileHandle, + DesiredAccess | SYNCHRONIZE, + &ObjectAttributes, + &IoStatusBlock, + NULL, /* AllocationSize OPTIONAL, */ + FILE_ATTRIBUTE_NORMAL, + ShareAccess, + CreateDisposition, + FILE_RANDOM_ACCESS, /* CreateOptions, */ + NULL, /* EaBuffer OPTIONAL, */ + 0 /* EaLength (required if EaBuffer) */ + ); + if (!NT_SUCCESS (status)) + goto Error; + f->handle = (int)FileHandle; + + /* Determine size of the file */ + status = ZwQueryInformationFile( FileHandle, + &IoStatusBlock, + &FileInformation, + sizeof(FILE_STANDARD_INFORMATION), + FileStandardInformation + ); + if (!NT_SUCCESS (status)) + goto Error; + f->filesize = FileInformation.EndOfFile.LowPart; + + /* Move to the end of the file if we are appending */ + if (mode[0] == 'a') { + FilePosition.CurrentByteOffset.HighPart = 0; + FilePosition.CurrentByteOffset.LowPart = f->filesize; + status = ZwSetInformationFile( FileHandle, + &IoStatusBlock, + &FilePosition, + sizeof(FILE_POSITION_INFORMATION), + FilePositionInformation + ); + if (!NT_SUCCESS (status)) + goto Error; + } + return f; + +Error: + if (f) PM_free(f); + if (uniFile) _PM_FreeUnicodeString(uniFile); + return NULL; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fread function. +****************************************************************************/ +size_t fread( + void *ptr, + size_t size, + size_t n, + FILE *f) +{ + NTSTATUS status; + IO_STATUS_BLOCK IoStatusBlock; + LARGE_INTEGER ByteOffset; + + /* Read any extra bytes from the file */ + ByteOffset.HighPart = 0; + ByteOffset.LowPart = f->offset; + status = ZwReadFile( (HANDLE)f->handle, + NULL, /*IN HANDLE Event OPTIONAL, */ + NULL, /* IN PIO_APC_ROUTINE ApcRoutine OPTIONAL, */ + NULL, /* IN PVOID ApcContext OPTIONAL, */ + &IoStatusBlock, + ptr, /* OUT PVOID Buffer, */ + size * n, /*IN ULONG Length, */ + &ByteOffset, /*OPTIONAL, */ + NULL /*IN PULONG Key OPTIONAL */ + ); + if (!NT_SUCCESS (status)) + return 0; + f->offset += IoStatusBlock.Information; + return IoStatusBlock.Information / size; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fwrite function. +****************************************************************************/ +size_t fwrite( + const void *ptr, + size_t size, + size_t n, + FILE *f) +{ + NTSTATUS status; + IO_STATUS_BLOCK IoStatusBlock; + LARGE_INTEGER ByteOffset; + + if (!f->writemode) + return 0; + ByteOffset.HighPart = 0; + ByteOffset.LowPart = f->offset; + status = ZwWriteFile( (HANDLE)f->handle, + NULL, /*IN HANDLE Event OPTIONAL, */ + NULL, /* IN PIO_APC_ROUTINE ApcRoutine OPTIONAL, */ + NULL, /* IN PVOID ApcContext OPTIONAL, */ + &IoStatusBlock, + (void*)ptr, /* OUT PVOID Buffer, */ + size * n, /*IN ULONG Length, */ + &ByteOffset, /*OPTIONAL, */ + NULL /*IN PULONG Key OPTIONAL */ + ); + if (!NT_SUCCESS (status)) + return 0; + f->offset += IoStatusBlock.Information; + if (f->offset > f->filesize) + f->filesize = f->offset; + return IoStatusBlock.Information / size; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fflush function. +****************************************************************************/ +int fflush( + FILE *f) +{ + /* Nothing to do here as we are not doing buffered I/O */ + (void)f; + return 0; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fseek function. +****************************************************************************/ +int fseek( + FILE *f, + long int offset, + int whence) +{ + NTSTATUS status; + FILE_POSITION_INFORMATION FilePosition; + IO_STATUS_BLOCK IoStatusBlock; + + if (whence == 0) + f->offset = offset; + else if (whence == 1) + f->offset += offset; + else if (whence == 2) + f->offset = f->filesize + offset; + FilePosition.CurrentByteOffset.HighPart = 0; + FilePosition.CurrentByteOffset.LowPart = f->offset; + status = ZwSetInformationFile( (HANDLE)f->handle, + &IoStatusBlock, + &FilePosition, + sizeof(FILE_POSITION_INFORMATION), + FilePositionInformation + ); + if (!NT_SUCCESS (status)) + return -1; + return 0; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C ftell function. +****************************************************************************/ +long ftell( + FILE *f) +{ + return f->offset; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C feof function. +****************************************************************************/ +int feof( + FILE *f) +{ + return (f->offset == f->filesize); +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fgets function. +****************************************************************************/ +char *fgets( + char *s, + int n, + FILE *f) +{ + int len; + char *cs; + + /* Read the entire buffer into memory (our functions are unbuffered!) */ + if ((len = fread(s,1,n,f)) == 0) + return NULL; + + /* Search for '\n' or end of string */ + if (n > len) + n = len; + cs = s; + while (--n > 0) { + if (*cs == '\n') + break; + cs++; + } + *cs = '\0'; + return s; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fputs function. +****************************************************************************/ +int fputs( + const char *s, + FILE *f) +{ + return fwrite(s,1,strlen(s),f); +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fclose function. +****************************************************************************/ +int fclose( + FILE *f) +{ + ZwClose((HANDLE)f->handle); + PM_free(f); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c new file mode 100644 index 0000000..bbf0cbf --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c @@ -0,0 +1,139 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT driver +* +* Description: C library compatible stdlib.h functions for use within a +* Windows NT driver. +* +****************************************************************************/ + +#include "pmapi.h" +#include "oshdr.h" + +/*------------------------ Main Code Implementation -----------------------*/ + +/**************************************************************************** +REMARKS: +PM_malloc override function for Nucleus drivers loaded in NT drivers's. +****************************************************************************/ +void * malloc( + size_t size) +{ + return PM_mallocShared(size); +} + +/**************************************************************************** +REMARKS: +calloc library function for Nucleus drivers loaded in NT drivers's. +****************************************************************************/ +void * calloc( + size_t nelem, + size_t size) +{ + void *p = PM_mallocShared(nelem * size); + if (p) + memset(p,0,nelem * size); + return p; +} + +/**************************************************************************** +REMARKS: +PM_realloc override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void * realloc( + void *ptr, + size_t size) +{ + void *p = PM_mallocShared(size); + if (p) { + memcpy(p,ptr,size); + PM_freeShared(ptr); + } + return p; +} + +/**************************************************************************** +REMARKS: +PM_free override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void free( + void *p) +{ + PM_freeShared(p); +} + +/**************************************************************************** +PARAMETERS: +cstr - C style ANSI string to convert + +RETURNS: +Pointer to the UniCode string structure or NULL on failure to allocate memory + +REMARKS: +Converts a C style string to a UniCode string structure that can be passed +directly to NT kernel functions. +****************************************************************************/ +UNICODE_STRING *_PM_CStringToUnicodeString( + const char *cstr) +{ + int length; + ANSI_STRING ansiStr; + UNICODE_STRING *uniStr; + + /* Allocate memory for the string structure */ + if ((uniStr = ExAllocatePool(NonPagedPool, sizeof(UNICODE_STRING))) == NULL) + return NULL; + + /* Allocate memory for the wide string itself */ + length = (strlen(cstr) * sizeof(WCHAR)) + sizeof(WCHAR); + if ((uniStr->Buffer = ExAllocatePool(NonPagedPool, length)) == NULL) { + ExFreePool(uniStr); + return NULL; + } + RtlZeroMemory(uniStr->Buffer, length); + uniStr->Length = 0; + uniStr->MaximumLength = (USHORT)length; + + /* Convert filename string to ansi string and then to UniCode string */ + RtlInitAnsiString(&ansiStr, cstr); + RtlAnsiStringToUnicodeString(uniStr, &ansiStr, FALSE); + return uniStr; +} + +/**************************************************************************** +PARAMETERS: +uniStr - UniCode string structure to free + +REMARKS: +Frees a string allocated by the above _PM_CStringToUnicodeString function. +****************************************************************************/ +void _PM_FreeUnicodeString( + UNICODE_STRING *uniStr) +{ + if (uniStr) { + ExFreePool(uniStr->Buffer); + ExFreePool(uniStr); + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c new file mode 100644 index 0000000..901ce1c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c new file mode 100644 index 0000000..f4c4bd4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c @@ -0,0 +1,123 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static CPU_largeInteger countFreq; +static ulong start,finish; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +static void __ZTimerInit(void) +{ + KeQueryPerformanceCounter((LARGE_INTEGER*)&countFreq); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static void __LZTimerOn( + LZTimerObject *tm) +{ + LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL); + tm->start.low = lt.LowPart; + tm->start.high = lt.HighPart; +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + LARGE_INTEGER tmLap = KeQueryPerformanceCounter(NULL); + CPU_largeInteger tmCount; + + _CPU_diffTime64(&tm->start,(CPU_largeInteger*)&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static void __LZTimerOff( + LZTimerObject *tm) +{ + LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL); + tm->end.low = lt.LowPart; + tm->end.high = lt.HighPart; +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + LARGE_INTEGER count; + KeQuerySystemTime(&count); + return (ulong)(*((_int64*)&count) / 10); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm b/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm new file mode 100644 index 0000000..761f0f4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm @@ -0,0 +1,180 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: OS/2 32 bit protected mode +;* +;* Description: Low level assembly support for the PM library specific +;* to OS/2 +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmos2 ; Set up memory model + +begdataseg _pmos2 + + cglobal _PM_ioentry + cglobal _PM_gdt +_PM_ioentry dd 0 ; Offset to call gate +_PM_gdt dw 0 ; Selector to call gate + +enddataseg _pmos2 + +begcodeseg _pmos2 ; Start of code segment + +;---------------------------------------------------------------------------- +; int PM_setIOPL(int iopl) +;---------------------------------------------------------------------------- +; Change the IOPL level for the 32-bit task. Returns the previous level +; so it can be restored for the task correctly. +;---------------------------------------------------------------------------- +cprocstart PM_setIOPL + + ARG iopl:UINT + + enter_c + pushfd ; Save the old EFLAGS for later + mov ecx,[iopl] ; ECX := IOPL level + xor ebx,ebx ; Change IOPL level function code (0) +ifdef USE_NASM + call far dword [_PM_ioentry] +else + call [FWORD _PM_ioentry] +endif + pop eax + and eax,0011000000000000b + shr eax,12 + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_setGDTSelLimit(ushort selector, ulong limit); +;---------------------------------------------------------------------------- +; Change the GDT selector limit to given value. Used to change selector +; limits to address the entire system address space. +;---------------------------------------------------------------------------- +cprocstart _PM_setGDTSelLimit + + ARG selector:USHORT, limit:UINT + + enter_c + sub esp,20 ; Make room for selector data on stack + mov ecx,esp ; ECX := selector data structure + mov bx,[selector] ; Fill out the data structure + and bx,0FFF8h ; Kick out the LDT/GDT and DPL bits + mov [WORD ecx],bx + mov ebx,[limit] + mov [DWORD ecx+4],ebx + mov ebx,5 ; Set GDT selector limit function code +ifdef USE_NASM + call far dword [_PM_ioentry] +else + call [FWORD _PM_ioentry] +endif + add esp,20 + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_getCx86(uchar reg); +;---------------------------------------------------------------------------- +; Read a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_getCx86 + + ARG reg:UCHAR + + enter_c + mov al,[reg] + out 22h,al + in al,23h + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_setCx86(uchar reg,uchar val); +;---------------------------------------------------------------------------- +; Write a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_setCx86 + + ARG reg:UCHAR, val:UCHAR + + enter_c + mov al,[reg] + out 22h,al + mov al,[val] + out 23h,al + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _MTRR_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _MTRR_disableInt + +; Do nothing! + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_restoreInt(ulong ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _MTRR_restoreInt + +; Do nothing! + ret + +cprocend + +;---------------------------------------------------------------------------- +; void DebugInt(void) +;---------------------------------------------------------------------------- +cprocstart DebugInt + + int 3 + ret + +cprocend + +endcodeseg _pmos2 + + END ; End of module + diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c new file mode 100644 index 0000000..7de400d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c @@ -0,0 +1,66 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: OS/2 +* +* Description: OS/2 specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +TODO: This should be implemented for OS/2! +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +TODO: This should be implemented for OS/2! +****************************************************************************/ +#define RestoreThreadPriority(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = 100000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + ULONG count; \ + DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) ); \ + (t)->low = count * 100; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj b/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj new file mode 100644 index 0000000..5533346 Binary files /dev/null and b/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj differ diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/event.c b/board/MAI/bios_emulator/scitech/src/pm/os2/event.c new file mode 100644 index 0000000..91cc19b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/event.c @@ -0,0 +1,565 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: IBM PC (OS/2) +* +* Description: OS/2 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +/* Define generous keyboard monitor circular buffer size to minimize + * the danger of losing keystrokes + */ +#define KEYBUFSIZE (EVENTQSIZE + 10) + +static int oldMouseState; /* Old mouse state */ +static ulong oldKeyMessage; /* Old keyboard state */ +static ushort keyUpMsg[256] = {0}; /* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ +HMOU _EVT_hMouse; /* Handle to the mouse driver */ +HMONITOR _EVT_hKbdMon; /* Handle to the keyboard driver */ +TID kbdMonTID = 0; /* Keyboard monitor thread ID */ +HEV hevStart; /* Start event semaphore handle */ +BOOL bMonRunning; /* Flag set if monitor thread OK */ +HMTX hmtxKeyBuf; /* Mutex protecting key buffer */ +KEYPACKET keyMonPkts[KEYBUFSIZE]; /* Array of monitor key packets */ +int kpHead = 0; /* Key packet buffer head */ +int kpTail = 0; /* Key packet buffer tail */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under OS/2 */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + ULONG count; + DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) ); + return count; +} + +/**************************************************************************** +REMARKS: +Converts a mickey movement value to a pixel adjustment value. +****************************************************************************/ +static int MickeyToPixel( + int mickey) +{ + /* TODO: We can add some code in here to handle 'acceleration' for */ + /* the mouse cursor. For now just use the mickeys. */ + return mickey; +} + +/* Some useful defines any typedefs used in the keyboard handling */ +#define KEY_RELEASE 0x40 + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from OS/2 into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + KBDINFO keyInfo; /* Must not cross a 64K boundary */ + KBDKEYINFO key; /* Must not cross a 64K boundary */ + MOUQUEINFO mqueue; /* Must not cross a 64K boundary */ + MOUEVENTINFO mouse; /* Must not cross a 64K boundary */ + ushort mWait; /* Must not cross a 64K boundary */ + KEYPACKET kp; /* Must not cross a 64K boundary */ + event_t evt; + int scan; + ibool noInput = TRUE; /* Flag to determine if any input was available */ + + /* First of all, check if we should do any session switch work */ + __PM_checkConsoleSwitch(); + + /* Pump all keyboard messages from our circular buffer */ + for (;;) { + /* Check that the monitor thread is still running */ + if (!bMonRunning) + PM_fatalError("Keyboard monitor thread died!"); + + /* Protect keypacket buffer with mutex */ + DosRequestMutexSem(hmtxKeyBuf, SEM_INDEFINITE_WAIT); + if (kpHead == kpTail) { + DosReleaseMutexSem(hmtxKeyBuf); + break; + } + + noInput = FALSE; + + /* Read packet from circular buffer and remove it */ + memcpy(&kp, &keyMonPkts[kpTail], sizeof(KEYPACKET)); + if (++kpTail == KEYBUFSIZE) + kpTail = 0; + DosReleaseMutexSem(hmtxKeyBuf); + + /* Compensate for the 0xE0 character */ + if (kp.XlatedScan && kp.XlatedChar == 0xE0) + kp.XlatedChar = 0; + + /* Determine type of keyboard event */ + memset(&evt,0,sizeof(evt)); + if (kp.KbdDDFlagWord & KEY_RELEASE) + evt.what = EVT_KEYUP; + else + evt.what = EVT_KEYDOWN; + + /* Convert keyboard codes */ + scan = kp.MonFlagWord >> 8; + if (evt.what == EVT_KEYUP) { + /* Get message for keyup code from table of cached down values */ + evt.message = keyUpMsg[scan]; + keyUpMsg[scan] = 0; + oldKeyMessage = -1; + } + else { + evt.message = ((ulong)scan << 8) | kp.XlatedChar; + if (evt.message == keyUpMsg[scan]) { + evt.what = EVT_KEYREPEAT; + evt.message |= 0x10000; + } + oldKeyMessage = evt.message & 0x0FFFF; + keyUpMsg[scan] = (ushort)evt.message; + } + + /* Convert shift state modifiers */ + if (kp.u.ShiftState & 0x0001) + evt.modifiers |= EVT_RIGHTSHIFT; + if (kp.u.ShiftState & 0x0002) + evt.modifiers |= EVT_LEFTSHIFT; + if (kp.u.ShiftState & 0x0100) + evt.modifiers |= EVT_LEFTCTRL; + if (kp.u.ShiftState & 0x0200) + evt.modifiers |= EVT_LEFTALT; + if (kp.u.ShiftState & 0x0400) + evt.modifiers |= EVT_RIGHTCTRL; + if (kp.u.ShiftState & 0x0800) + evt.modifiers |= EVT_RIGHTALT; + EVT.oldMove = -1; + + /* Add time stamp and add the event to the queue */ + evt.when = key.time; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Don't just flush because that terminally confuses the monitor */ + do { + KbdCharIn(&key, IO_NOWAIT, 0); + } while (key.fbStatus & KBDTRF_FINAL_CHAR_IN); + + /* Pump all mouse messages */ + KbdGetStatus(&keyInfo,0); + /* Check return code - mouse may not be operational!! */ + if (MouGetNumQueEl(&mqueue,_EVT_hMouse) == NO_ERROR) { + while (mqueue.cEvents) { + while (mqueue.cEvents--) { + memset(&evt,0,sizeof(evt)); + mWait = MOU_NOWAIT; + MouReadEventQue(&mouse,&mWait,_EVT_hMouse); + + /* Update the mouse position. We get the mouse coordinates + * in mickeys so we have to translate these into pixels and + * move our mouse position. If we don't do this, OS/2 gives + * us the coordinates in character positions since it still + * thinks we are in text mode! + */ + EVT.mx += MickeyToPixel(mouse.col); + EVT.my += MickeyToPixel(mouse.row); + if (EVT.mx < 0) EVT.mx = 0; + if (EVT.my < 0) EVT.my = 0; + if (EVT.mx > rangeX) EVT.mx = rangeX; + if (EVT.my > rangeY) EVT.my = rangeY; + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = mouse.col; + evt.relative_y = mouse.row; + evt.when = key.time; + if (mouse.fs & (MOUSE_BN1_DOWN | MOUSE_MOTION_WITH_BN1_DOWN)) + evt.modifiers |= EVT_LEFTBUT; + if (mouse.fs & (MOUSE_BN2_DOWN | MOUSE_MOTION_WITH_BN2_DOWN)) + evt.modifiers |= EVT_RIGHTBUT; + if (mouse.fs & (MOUSE_BN3_DOWN | MOUSE_MOTION_WITH_BN3_DOWN)) + evt.modifiers |= EVT_MIDDLEBUT; + if (keyInfo.fsState & 0x0001) + evt.modifiers |= EVT_RIGHTSHIFT; + if (keyInfo.fsState & 0x0002) + evt.modifiers |= EVT_LEFTSHIFT; + if (keyInfo.fsState & 0x0100) + evt.modifiers |= EVT_LEFTCTRL; + if (keyInfo.fsState & 0x0200) + evt.modifiers |= EVT_LEFTALT; + if (keyInfo.fsState & 0x0400) + evt.modifiers |= EVT_RIGHTCTRL; + if (keyInfo.fsState & 0x0800) + evt.modifiers |= EVT_RIGHTALT; + + /* Check for left mouse click events */ + /* 0x06 == (MOUSE_BN1_DOWN | MOUSE_MOTION_WITH_BN1_DOWN) */ + if (((mouse.fs & 0x0006) && !(oldMouseState & 0x0006)) + || (!(mouse.fs & 0x0006) && (oldMouseState & 0x0006))) { + if (mouse.fs & 0x0006) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_LEFTBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Check for right mouse click events */ + /* 0x0018 == (MOUSE_BN2_DOWN | MOUSE_MOTION_WITH_BN2_DOWN) */ + if (((mouse.fs & 0x0018) && !(oldMouseState & 0x0018)) + || (!(mouse.fs & 0x0018) && (oldMouseState & 0x0018))) { + if (mouse.fs & 0x0018) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_RIGHTBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Check for middle mouse click events */ + /* 0x0060 == (MOUSE_BN3_DOWN | MOUSE_MOTION_WITH_BN3_DOWN) */ + if (((mouse.fs & 0x0060) && !(oldMouseState & 0x0060)) + || (!(mouse.fs & 0x0060) && (oldMouseState & 0x0060))) { + if (mouse.fs & 0x0060) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_MIDDLEBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Check for mouse movement event */ + if (mouse.fs & 0x002B) { + evt.what = EVT_MOUSEMOVE; + if (EVT.oldMove != -1) { + EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */ + EVT.evtq[EVT.oldMove].where_y = evt.where_y; + } + else { + EVT.oldMove = EVT.freeHead; /* Save id of this move event */ + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + + /* Save current mouse state */ + oldMouseState = mouse.fs; + } + MouGetNumQueEl(&mqueue,_EVT_hMouse); + } + noInput = FALSE; + } + + /* If there was no input available, give up the current timeslice + * Note: DosSleep(0) will effectively do nothing if no other thread is ready. Hence + * DosSleep(0) will still use 100% CPU _but_ should not interfere with other programs. + */ + if (noInput) + DosSleep(0); +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Keyboard monitor thread. Needed to catch both keyup and keydown events. +****************************************************************************/ +static void _kbdMonThread( + void *params) +{ + APIRET rc; + KEYPACKET kp; + USHORT count = sizeof(KEYPACKET); + MONBUF monInbuf; + MONBUF monOutbuf; + int kpNew; + + /* Raise thread priority for higher responsiveness */ + DosSetPriority(PRTYS_THREAD, PRTYC_TIMECRITICAL, 0, 0); + monInbuf.cb = sizeof(monInbuf) - sizeof(monInbuf.cb); + monOutbuf.cb = sizeof(monOutbuf) - sizeof(monOutbuf.cb); + bMonRunning = FALSE; + + /* Register the buffers to be used for monitoring for current session */ + if (DosMonReg(_EVT_hKbdMon, &monInbuf, (ULONG*)&monOutbuf,MONITOR_END, -1)) { + DosPostEventSem(hevStart); /* unblock the main thread */ + return; + } + + /* Unblock the main thread and tell it we're OK*/ + bMonRunning = TRUE; + DosPostEventSem(hevStart); + while (bMonRunning) { /* Start an endless loop */ + /* Read data from keyboard driver */ + rc = DosMonRead((PBYTE)&monInbuf, IO_WAIT, (PBYTE)&kp, (PUSHORT)&count); + if (rc) { +#ifdef CHECKED + if (bMonRunning) + printf("Error in DosMonRead, rc = %ld\n", rc); +#endif + bMonRunning = FALSE; + return; + } + + /* Pass FLUSH packets immediately */ + if (kp.MonFlagWord & 4) { +#ifdef CHECKED + printf("Flush packet!\n"); +#endif + DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count); + continue; + } + + /*TODO: to be removed */ + /* Skip extended scancodes & some others */ + if (((kp.MonFlagWord >> 8) == 0xE0) || ((kp.KbdDDFlagWord & 0x0F) == 0x0F)) { + DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count); + continue; + } + +/* printf("RawScan = %X, XlatedScan = %X, fbStatus = %X, KbdDDFlags = %X\n", */ +/* kp.MonFlagWord >> 8, kp.XlatedScan, kp.u.ShiftState, kp.KbdDDFlagWord); */ + + /* Protect access to buffer with mutex semaphore */ + rc = DosRequestMutexSem(hmtxKeyBuf, 1000); + if (rc) { +#ifdef CHECKED + printf("Can't get access to mutex, rc = %ld\n", rc); +#endif + bMonRunning = FALSE; + return; + } + + /* Store packet in circular buffer, drop it if it's full */ + kpNew = kpHead + 1; + if (kpNew == KEYBUFSIZE) + kpNew = 0; + if (kpNew != kpTail) { + memcpy(&keyMonPkts[kpHead], &kp, sizeof(KEYPACKET)); + /* TODO: fix this! */ + /* Convert break to make code */ + keyMonPkts[kpHead].MonFlagWord &= 0x7FFF; + kpHead = kpNew; + } + DosReleaseMutexSem(hmtxKeyBuf); + + /* Finally write the packet */ + rc = DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count); + if (rc) { +#ifdef CHECKED + if (bMonRunning) + printf("Error in DosMonWrite, rc = %ld\n", rc); +#endif + bMonRunning = FALSE; + return; + } + } + (void)params; +} + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort( + int signal) +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + ushort stat; + + /* Initialise the event queue */ + PM_init(); + EVT.mouseMove = mouseMove; + initEventQueue(); + oldMouseState = 0; + oldKeyMessage = 0; + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* Open the mouse driver, and set it up to report events in mickeys */ + MouOpen(NULL,&_EVT_hMouse); + stat = 0x7F; + MouSetEventMask(&stat,_EVT_hMouse); + stat = (MOU_NODRAW | MOU_MICKEYS) << 8; + MouSetDevStatus(&stat,_EVT_hMouse); + + /* Open the keyboard monitor */ + if (DosMonOpen((PSZ)"KBD$", &_EVT_hKbdMon)) + PM_fatalError("Unable to open keyboard monitor!"); + + /* Create event semaphore, the monitor will post it when it's initalized */ + if (DosCreateEventSem(NULL, &hevStart, 0, FALSE)) + PM_fatalError("Unable to create event semaphore!"); + + /* Create mutex semaphore protecting the keypacket buffer */ + if (DosCreateMutexSem(NULL, &hmtxKeyBuf, 0, FALSE)) + PM_fatalError("Unable to create mutex semaphore!"); + + /* Start keyboard monitor thread, use 32K stack */ + kbdMonTID = _beginthread(_kbdMonThread, NULL, 0x8000, NULL); + + /* Now block until the monitor thread is up and running */ + /* Give the thread one second */ + DosWaitEventSem(hevStart, 1000); + if (!bMonRunning) { /* Check the thread is OK */ + DosMonClose(_EVT_hKbdMon); + PM_fatalError("Keyboard monitor thread didn't initialize!"); + } + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +#define _EVT_setMousePos(x,y) + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for OS/2 */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for OS/2 */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + APIRET rc; + + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* Close the mouse driver */ + MouClose(_EVT_hMouse); + + /* Stop the keyboard monitor thread and close the monitor */ + bMonRunning = FALSE; + rc = DosKillThread(kbdMonTID); +#ifdef CHECKED + if (rc) + printf("DosKillThread failed, rc = %ld\n", rc); +#endif + rc = DosMonClose(_EVT_hKbdMon); +#ifdef CHECKED + if (rc) { + printf("DosMonClose failed, rc = %ld\n", rc); + } +#endif + DosCloseEventSem(hevStart); + DosCloseMutexSem(hmtxKeyBuf); + KbdFlushBuffer(0); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h b/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h new file mode 100644 index 0000000..28d39fb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h @@ -0,0 +1,165 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 +* +* Description: Include file to include all OS/2 keyboard monitor stuff. +* +****************************************************************************/ + +/* Monitors stuff */ + +#define MONITOR_DEFAULT 0x0000 +#define MONITOR_BEGIN 1 +#define MONITOR_END 2 + +typedef SHANDLE HMONITOR; +typedef HMONITOR *PHMONITOR; + +typedef struct _KEYPACKET { + USHORT MonFlagWord; + UCHAR XlatedChar; + UCHAR XlatedScan; + UCHAR DBCSStatus; + UCHAR DBCSShift; + + union + { + USHORT ShiftState; + USHORT LayerIndex; + } u; + + ULONG Milliseconds; + USHORT KbdDDFlagWord; +} KEYPACKET; + +typedef struct _MLNPACKET { + USHORT MonFlagWord; + USHORT IOCTL; + USHORT CPId; + USHORT CPIndex; + ULONG Reserved; + USHORT KbdDDFlagWord; +} MLNPACKET; + +/* DBCSStatus */ + +#define SF_SHIFTS 1 /* If set to 1, shift status returned without a character */ +#define SF_NOTCHAR 2 /* 0 - Scan code is a character */ + /* 1 - Scan code is not a character; */ + /* instead it is an extended key code from the keyboard. */ +#define SF_IMMEDIATE 32 /* If set to 1, immediate conversion requested */ +#define SF_TYPEMASK 192 /* Has the following values: */ + /* 00 - Undefined */ + /* 01 - Final character; interim character flag is turned off */ + /* 10 - Interim character */ + /* 11 - Final character; interim character flag is turned on. */ +/* MonFlagWord */ + +#define MF_OPEN 1 /* open */ +#define MF_CLOSE 2 /* close */ +#define MF_FLUSH 4 /* is flush packet */ + +/* KbdDDFlagWord */ + +#define KF_NOTSQPACKET 1024 /* Don't put this packet in SQ buffer */ +#define KF_ACCENTEDKEY 512 /* Key was translated using previous accent. */ +#define KF_MULTIMAKE 256 /* Key was repeated make of a toggle key. */ +#define KF_SECONDARYKEY 128 /* Previous scan code was the E0 prefix code. */ +#define KF_KEYBREAK 64 /* This is the break of the key. */ +#define KF_KEYTYPEMASK 63 /* Isolates the Key Type field of DDFlags. */ +#define KF_UNDEFKEY 63 /* Key packet is undefined */ +#define KF_SYSREQKEY 23 /* This key packet is the SysReq key (4990) */ +#define KF_PRINTFLUSHKEY 22 /* This packet is Ct-Alt-PrtScr */ +#define KF_PSPRINTECHOKEY 21 /* This packet is Ctl-P */ +#define KF_PRINTECHOKEY 20 /* This packet is Ctl-PrtScr */ +#define KF_PRTSCRKEY 19 /* This packet is PrtScr */ +#define KF_PSBREAKKEY 18 /* This packet is Ctl-C */ +#define KF_BREAKKEY 17 /* This packet is Ctl-Break */ +#define KF_ACCENTKEY 16 /* This packet is an accent key */ +#define KF_XRORPNOT 13 /* This packet is a Read or Peek Notification Pct. */ +#define KF_MLNOTIFICATION 14 /* packet is a Multi-Layer NLS packet */ +#define KF_HOTKEYPACKET 12 /* This packet is the hot key. */ +#define KF_BADKEYCOMBO 11 /* Accent/char combo undefined, beep only. */ +#define KF_WAKEUPKEY 10 /* This packet is one following PAUSEKEY */ +#define KF_PSPAUSEKEY 9 /* This packet is Ctl-S */ +#define KF_PAUSEKEY 8 /* This packet is Ctl-Numlock or PAUSE */ +#define KF_SHIFTMASK 7 /* Key is a shift Key */ +#define KF_DUMPKEY 6 /* This packet is Ctl-Numlock-NumLock */ +#define KF_REBOOTKEY 5 /* This packet is Ctl-Alt-Del */ +#define KF_RESENDCODE 4 /* This packet is resend code from controller */ +#define KF_OVERRUNCODE 3 /* This packet is overrun code from controller */ +#define KF_SECPREFIXCODE 2 /* This packet is E0/E1 scan code */ +#define KF_ACKCODE 1 /* This packet is ack code from keyboard */ + + +typedef struct _MONBUF { + USHORT cb; + KEYPACKET Buffer; + BYTE Reserved[20]; +} MONBUF; + +#define RS_SYSREG 32768 /* Bit 15 SysReq key down */ +#define RS_CAPSLOCK 16384 /* Bit 14 Caps Lock key down */ +#define RS_NUMLOCK 8192 /* Bit 13 NumLock key down */ +#define RS_SCROLLLOCK 4096 /* Bit 12 Scroll Lock key down */ +#define RS_RALT 2048 /* Bit 11 Right Alt key down */ +#define RS_RCONTROL 1024 /* Bit 10 Right Ctrl key down */ +#define RS_LALT 512 /* Bit 9 Left Alt key down */ +#define RS_LCONTROL 256 /* Bit 8 Left Ctrl key down */ +#define RS_INSERT 128 /* Bit 7 Insert on */ +#define RS_CAPS 64 /* Bit 6 Caps Lock on */ +#define RS_NUM 32 /* Bit 5 NumLock on */ +#define RS_SCROLL 16 /* Bit 4 Scroll Lock on */ +#define RS_ALT 8 /* Bit 3 Either Alt key down */ +#define RS_CONTROL 4 /* Bit 2 Either Ctrl key down */ +#define RS_LSHIFT 2 /* Bit 1 Left Shift key down */ +#define RS_RSHIFT 1 /* Bit 0 Right Shift key down */ + + +#define CS_RCONTROL 91 /* Right Control */ +#define CS_LSHIFT 42 /* Left Shift */ +#define CS_RSHIFT 54 /* Right Shift */ +#define CS_LALT 56 /* Left Alt */ +#define CS_RALT 94 /* Right Alt */ + + +/* DosMon* prototypes */ +#ifdef __EMX__ + #define APIRET16 USHORT + #define APIENTRY16 +#else + #define DosMonOpen DOS16MONOPEN + #define DosMonClose DOS16MONCLOSE + #define DosMonReg DOS16MONREG + #define DosMonRead DOS16MONREAD + #define DosMonWrite DOS16MONWRITE + #define DosGetInfoSeg DOS16GETINFOSEG +#endif + +APIRET16 APIENTRY16 DosMonOpen (PSZ pszDevName, PHMONITOR phmon); +APIRET16 APIENTRY16 DosMonClose (HMONITOR hmon); +APIRET16 APIENTRY16 DosMonReg (HMONITOR hmon, MONBUF *pbInBuf, /*MONBUF*/ULONG *pbOutBuf, USHORT fPosition, USHORT usIndex); +APIRET16 APIENTRY16 DosMonRead (PBYTE pbInBuf, USHORT fWait, PBYTE pbDataBuf, PUSHORT pcbData); +APIRET16 APIENTRY16 DosMonWrite (PBYTE pbOutBuf, PBYTE pbDataBuf, USHORT cbData); diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h new file mode 100644 index 0000000..e7aa1c6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h @@ -0,0 +1,41 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#define INCL_DOSPROFILE +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include +#include +#include "os2/mon.h" + +void __PM_checkConsoleSwitch(void); diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c b/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c new file mode 100644 index 0000000..756eead --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c @@ -0,0 +1,2008 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "pm_help.h" +#include "mtrr.h" +#include +#include +#include +#include +#ifndef __EMX__ +#include +#endif +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include + +/* Semaphore for communication with our background daemon */ +#define SHAREDSEM ((PSZ)"\\SEM32\\SDD\\DAEMON") +#define DAEMON_NAME "SDDDAEMN.EXE" + +/*--------------------------- Global variables ----------------------------*/ + +/* Public structures used to communicate with VIDEOPMI for implementing + * the ability to call the real mode BIOS functions. + */ + +typedef struct _VIDEOMODEINFO { + ULONG miModeId; + USHORT usType; + USHORT usInt10ModeSet; + USHORT usXResolution; + USHORT usYResolution; + ULONG ulBufferAddress; + ULONG ulApertureSize; + BYTE bBitsPerPixel; + BYTE bBitPlanes; + BYTE bXCharSize; + BYTE bYCharSize; + USHORT usBytesPerScanLine; + USHORT usTextRows; + ULONG ulPageLength; + ULONG ulSaveSize; + BYTE bVrtRefresh; + BYTE bHrtRefresh; + BYTE bVrtPolPos; + BYTE bHrtPolPos; + CHAR bRedMaskSize; + CHAR bRedFieldPosition; + CHAR bGreenMaskSize; + CHAR bGreenFieldPosition; + CHAR bBlueMaskSize; + CHAR bBlueFieldPosition; + CHAR bRsvdMaskSize; + CHAR bRsvdFieldPosition; + ULONG ulColors; + ULONG ulReserved[3]; + } VIDEOMODEINFO, FAR *PVIDEOMODEINFO; + +typedef struct _ADAPTERINFO { + ULONG ulAdapterID; + CHAR szOEMString[128]; + CHAR szDACString[128]; + CHAR szRevision[128]; + ULONG ulTotalMemory; + ULONG ulMMIOBaseAddress; + ULONG ulPIOBaseAddress; + BYTE bBusType; + BYTE bEndian; + USHORT usDeviceBusID; + USHORT usVendorBusID; + USHORT SlotID; + } ADAPTERINFO, FAR *PADAPTERINFO; + +typedef struct _VIDEO_ADAPTER { + void *hvideo; + ADAPTERINFO Adapter; + VIDEOMODEINFO ModeInfo; + } VIDEO_ADAPTER, FAR *PVIDEO_ADAPTER; + +/* PMIREQUEST_SOFTWAREINT structures from OS/2 DDK */ + +typedef struct { + ULONG ulFlags; /* VDM initialization type */ +#define VDM_POSTLOAD 0x1 /* adapter just loaded, used internally for initialization */ +#define VDM_INITIALIZE 0x2 /* force initialization of a permanently open VDM, even if previously initialized */ +#define VDM_TERMINATE_POSTINITIALIZE 0x6 /*start VDM with initialization, but close it afterwards (includes VDM_INITIALIZE) */ +#define VDM_QUERY_CAPABILITY 0x10 /* query the current int 10 capability */ +#define VDM_FULL_VDM_CREATED 0x20 /* a full VDM is created */ +#define VDM_MINI_VDM_CREATED 0x40 /* a mini VDM is created */ +#define VDM_MINI_VDM_SUPPORTED 0x80 /* mini VDM support is available */ + PCHAR szName; /* VDM initialization program */ + PCHAR szArgs; /* VDM initialization arguments */ + }INITVDM; + +typedef struct { + BYTE bBufferType; +#define BUFFER_NONE 0 +#define INPUT_BUFFER 1 +#define OUTPUT_BUFFER 2 + BYTE bReserved; + BYTE bSelCRF; + BYTE bOffCRF; + PVOID pAddress; + ULONG ulSize; + } BUFFER, *PBUFFER; + +typedef struct vcrf_s { + ULONG reg_eax; + ULONG reg_ebx; + ULONG reg_ecx; + ULONG reg_edx; + ULONG reg_ebp; + ULONG reg_esi; + ULONG reg_edi; + ULONG reg_ds; + ULONG reg_es; + ULONG reg_fs; + ULONG reg_gs; + ULONG reg_cs; + ULONG reg_eip; + ULONG reg_eflag; + ULONG reg_ss; + ULONG reg_esp; + } VCRF; + +typedef struct { + ULONG ulBIOSIntNo; + VCRF aCRF; + BUFFER pB[2]; + } INTCRF; + +#define PMIREQUEST_LOADPMIFILE 21 +#define PMIREQUEST_IDENTIFYADAPTER 22 +#define PMIREQUEST_SOFTWAREINT 23 + +#ifdef PTR_DECL_IN_FRONT +#define EXPENTRYP * EXPENTRY +#else +#define EXPENTRYP EXPENTRY * +#endif + +/* Entry point to VIDEOPMI32Request. This may be overridden by external + * code that has already loaded VIDEOPMI to avoid loading it twice. + */ + +APIRET (EXPENTRYP PM_VIDEOPMI32Request)(PVIDEO_ADAPTER, ULONG, PVOID, PVOID) = NULL; +static ibool haveInt10 = -1; /* True if we have Int 10 support */ +static ibool useVPMI = true; /* False if VIDEOPMI unavailable */ +static VIDEO_ADAPTER Adapter; /* Video adapter for VIDEOPMI */ +static uchar RMBuf[1024]; /* Fake real mode transfer buffer */ +static uint VESABuf_len = 1024;/* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL;/* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +static uchar * lowMem = NULL; +static ibool isSessionSwitching = false; +static ulong parmsIn[4]; /* Must not cross 64Kb boundary! */ +static ulong parmsOut[4]; /* Must not cross 64Kb boundary! */ +extern ushort _PM_gdt; +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/* DosSysCtl prototype. It is not declared in the headers but it is in the + * standard import libraries (DOSCALLS.876). Funny. + */ +APIRET APIENTRY DosSysCtl(ULONG ulFunction, PVOID pvData); + +/* This is the stack size for the threads that track the session switch event */ +#define SESSION_SWITCH_STACK_SIZE 32768 + +typedef struct { + VIOMODEINFO vmi; + USHORT CursorX; + USHORT CursorY; + UCHAR FrameBuffer[1]; + } CONSOLE_SAVE; + +typedef struct _SESWITCHREC { + /* The following variable is volatile because of PM_SUSPEND_APP */ + volatile int Flags; /* -1 or PM_DEACTIVATE or PM_REACTIVATE */ + PM_saveState_cb Callback; /* Save/restore context callback */ + HMTX Mutex; /* Exclusive access mutex */ + HEV Event; /* Posted after callback is called */ + } SESWITCHREC; + +/* Page sized block cache */ + +#define PAGES_PER_BLOCK 32 +#define PAGE_BLOCK_SIZE (PAGES_PER_BLOCK * PM_PAGE_SIZE + (PM_PAGE_SIZE-1) + sizeof(pageblock)) +#define FREELIST_NEXT(p) (*(void**)(p)) +typedef struct pageblock { + struct pageblock *next; + struct pageblock *prev; + void *freeListStart; + void *freeList; + void *freeListEnd; + int freeCount; + PM_lockHandle lockHandle; + } pageblock; + +static pageblock *pageBlocks = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +func - Helper device driver function to call + +RETURNS: +First return value from the device driver in parmsOut[0] + +REMARKS: +Function to open our helper device driver, call it and close the file +handle. Note that we have to open the device driver for every call because +of two problems: + + 1. We cannot open a single file handle in a DLL that is shared amongst + programs, since every process must have it's own open file handle. + + 2. For some reason there appears to be a limit of about 12 open file + handles on a device driver in the system. Hence when we open more + than about 12 file handles things start to go very strange. + +Hence we simply open the file handle every time that we need to call the +device driver to work around these problems. +****************************************************************************/ +static ulong CallSDDHelp( + int func) +{ + static ulong inLen; /* Must not cross 64Kb boundary! */ + static ulong outLen; /* Must not cross 64Kb boundary! */ + HFILE hSDDHelp; + ULONG rc; + ulong result; + + if ((rc = DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0, + FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, + NULL)) != 0) { + if (rc == 4) { /* Did we run out of file handles? */ + ULONG ulNewFHs; + LONG lAddFHs = 5; + + if (DosSetRelMaxFH(&lAddFHs, &ulNewFHs) != 0) + PM_fatalError("Failed to raise the file handles limit!"); + else { + if ((rc = DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0, + FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, + NULL)) != 0) { + PM_fatalError("Unable to open SDDHELP$ helper device driver! (#2)"); + } + } + } + else + PM_fatalError("Unable to open SDDHELP$ helper device driver!"); + } + if (DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,func, + &parmsIn, inLen = sizeof(parmsIn), &inLen, + &parmsOut, outLen = sizeof(parmsOut), &outLen) != 0) + PM_fatalError("Failure calling SDDHELP$ helper device driver!"); + DosClose(hSDDHelp); + return parmsOut[0]; +} + +/**************************************************************************** +REMARKS: +Determine if we're running on a DBCS system. +****************************************************************************/ +ibool __IsDBCSSystem(void) +{ + CHAR achDBCSInfo[12]; + COUNTRYCODE ccStruct = {0, 0}; + + memset(achDBCSInfo, 0, 12); + + /* Get the DBCS vector - if it's not empty, we're on DBCS */ + DosQueryDBCSEnv(sizeof(achDBCSInfo), &ccStruct, achDBCSInfo); + if (achDBCSInfo[0] != 0) + return true; + else + return false; +} + +/**************************************************************************** +REMARKS: +Determine if PMSHELL is running - if it isn't, we can't use certain calls +****************************************************************************/ +ibool __isShellLoaded(void) +{ + PVOID ptr; + + if (DosGetNamedSharedMem(&ptr, (PSZ)"\\SHAREMEM\\PMGLOBAL.MEM", PAG_READ) == NO_ERROR) { + DosFreeMem(ptr); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Initialise the PM library and connect to our helper device driver. If we +cannot connect to our helper device driver, we bail out with an error +message. +****************************************************************************/ +void PMAPI PM_init(void) +{ + if (!lowMem) { + /* Obtain the 32->16 callgate from the device driver to enable IOPL */ + if ((_PM_gdt = CallSDDHelp(PMHELP_GETGDT32)) == 0) + PM_fatalError("Unable to obtain call gate selector!"); + + PM_setIOPL(3); + + /* Map the first Mb of physical memory into lowMem */ + if ((lowMem = PM_mapPhysicalAddr(0,0xFFFFF,true)) == NULL) + PM_fatalError("Unable to map first Mb physical memory!"); + + /* Initialise the MTRR interface functions */ + MTRR_init(); + } +} + +/**************************************************************************** +REMARKS: +Initialise the PM library for BIOS access via VIDEOPMI. This should work +with any GRADD driver, including SDD/2. +****************************************************************************/ +static ibool InitInt10(void) +{ + HMODULE hModGENPMI,hModSDDPMI,hModVideoPMI; + CHAR buf[80],path[_MAX_PATH]; + HEV hevDaemon = NULLHANDLE; + RESULTCODES resCodes; + + if (haveInt10 == -1) { + /* Connect to VIDEOPMI and get entry point. Note that we only + * do this if GENPMI or SDDPMI are already loaded, since we need + * a GRADD based driver for this to work. + */ + PM_init(); + haveInt10 = false; + if (DosQueryModuleHandle((PSZ)"GENPMI.DLL",&hModGENPMI) != 0) + hModGENPMI = NULLHANDLE; + if (DosQueryModuleHandle((PSZ)"SDDPMI.DLL",&hModSDDPMI) != 0) + hModSDDPMI = NULLHANDLE; + if (hModGENPMI || hModSDDPMI) { + if (DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"VIDEOPMI.DLL",&hModVideoPMI) == 0) { + if (DosQueryProcAddr(hModVideoPMI,0,(PSZ)"VIDEOPMI32Request",(void*)&PM_VIDEOPMI32Request) != 0) + PM_fatalError("Unable to get VIDEOPMI32Request entry point!"); + strcpy(path,"X:\\OS2\\SVGADATA.PMI"); + path[0] = PM_getBootDrive(); + if (PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_LOADPMIFILE,path,NULL) != 0) { + DosFreeModule(hModVideoPMI); + PM_VIDEOPMI32Request = NULL; + haveInt10 = false; + } + else { + /* Attempt to initialise the full VDM in the system. This will only + * work if VPRPMI.SYS is loaded, but it provides support for passing + * values in ES/DS/ESI/EDI between the BIOS which does not work with + * kernel VDM's in fixpacks earlier than FP15. FP15 and later and + * the new Warp 4.51 and Warp Server convenience packs should work + * fine with the kernel mini-VDM. + * + * Also the full VDM is the only solution for really old kernels + * (but GRADD won't run on them so this is superfluous ;-). + */ + INITVDM InitVDM = {VDM_INITIALIZE,NULL,NULL}; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&InitVDM,NULL); + haveInt10 = true; + } + } + } + else { + /* A GRADD driver isn't loaded, hence we can't use VIDEOPMI. But we will try + * to access the mini-VDM directly, first verifying that the support is + * available in the kernel (it should be for kernels that support GRADD). + * This may be needed in a command line boot or if non-GRADD driver is + * used (Matrox or classic VGA). + * Note: because of problems with mini-VDM support in the kernel, we have to + * spawn a daemon process that will do the actual mini-VDM access for us. + */ + /* Try to open shared semaphore to see if our daemon is already up */ + if (DosOpenEventSem(SHAREDSEM, &hevDaemon) == NO_ERROR) { + if (DosWaitEventSem(hevDaemon, 1) == NO_ERROR) { + /* If semaphore is posted, all is well */ + useVPMI = false; + haveInt10 = true; + } + } + else { + /* Create shared event semaphore */ + if (DosCreateEventSem(SHAREDSEM, &hevDaemon, DC_SEM_SHARED, FALSE) == NO_ERROR) { + PM_findBPD(DAEMON_NAME, path); + strcat(path, DAEMON_NAME); + if (DosExecPgm(buf, sizeof(buf), EXEC_BACKGROUND, (PSZ)DAEMON_NAME, + NULL, &resCodes, (PSZ)path) == NO_ERROR) { + /* The daemon was successfully spawned, now give it a sec to come up */ + if (DosWaitEventSem(hevDaemon, 2000) == NO_ERROR) { + /* It's up! */ + useVPMI = false; + haveInt10 = true; + } + } + } + } + } + } + return haveInt10; +} + +/**************************************************************************** +REMARKS: +We "probably" have BIOS access under OS/2 but we have to verify/initialize it +first. +****************************************************************************/ +ibool PMAPI PM_haveBIOSAccess(void) +{ + return InitInt10(); +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + return _OS_OS2; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier. +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ + return PM_386; +} + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash( + char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Report a fatal error condition and halt the program. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + /* Be prepare to be called recursively (failed to fail situation :-) */ + static int fatalErrorCount = 0; + if (fatalErrorCount++ == 0) { + if (fatalErrorCleanup) + fatalErrorCleanup(); + } + fprintf(stderr,"%s\n", msg); + exit(1); +} + +/**************************************************************************** +REMARKS: +Allocate the real mode VESA transfer buffer for communicating with the BIOS. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + KBDKEYINFO key; /* Must not cross a 64K boundary */ + + KbdPeek(&key, 0); + return (key.fbStatus & KBDTRF_FINAL_CHAR_IN); +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + KBDKEYINFO key; /* Must not cross a 64K boundary */ + + KbdCharIn(&key,IO_WAIT,0); + return key.chChar; +} + +/**************************************************************************** +REMARKS: +Open a fullscreen console for output to the screen. This requires that +the application be a fullscreen VIO program. +****************************************************************************/ +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + (void)hwndUser; + (void)device; + (void)xRes; + (void)yRes; + (void)bpp; + (void)fullScreen; + return 0; +} + +/**************************************************************************** +REMARKS: +Find the size of the console state buffer. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + VIOMODEINFO vmi; + vmi.cb = sizeof (VIOMODEINFO); + VioGetMode (&vmi, (HVIO)0); + return sizeof (CONSOLE_SAVE) - 1 + vmi.col * vmi.row * 2; +} + +/**************************************************************************** +REMARKS: +Save the state of the console. +****************************************************************************/ +void PMAPI PM_saveConsoleState( + void *stateBuf, + PM_HWND hwndConsole) +{ + USHORT fblen; + CONSOLE_SAVE *cs = (CONSOLE_SAVE*)stateBuf; + VIOMODEINFO vmi; + + /* The reason for the VIOMODEINFO juggling is 16-bit code. Because the user + * allocates the state buffer, cd->vmi might be crossing the 64K boundary and + * the 16-bit API would fail. If we create another copy on stack, the compiler + * should ensure that the 64K boundary will not be crossed (it adjusts the stack + * if it should cross). + */ + vmi.cb = sizeof(VIOMODEINFO); + VioGetMode(&vmi,(HVIO)0); + memcpy(&cs->vmi, &vmi, sizeof(VIOMODEINFO)); + VioGetCurPos(&cs->CursorY, &cs->CursorX, (HVIO)0); + fblen = cs->vmi.col * cs->vmi.row * 2; + VioReadCellStr((PCH)cs->FrameBuffer, &fblen, 0, 0, (HVIO)0); +} + +/* Global variable to communicate between threads */ +static SESWITCHREC SesSwitchRec = { -1 }; + +/**************************************************************************** +REMARKS: +Called by external routines at least once per frame to check whenever a +session save/restore should be performed. Since we receive such notifications +asyncronously, we can't perform all required operations at that time. +****************************************************************************/ +void __PM_checkConsoleSwitch(void) +{ + int Flags, Mode; + PM_saveState_cb Callback; + + /* Quick optimized path for most common case */ + if (SesSwitchRec.Flags == -1) + return; + +again: + if (DosRequestMutexSem(SesSwitchRec.Mutex, 100)) + return; + Flags = SesSwitchRec.Flags; + Callback = SesSwitchRec.Callback; + SesSwitchRec.Flags = -1; + DosReleaseMutexSem(SesSwitchRec.Mutex); + + isSessionSwitching = true; /* Prevent VIO calls */ + Mode = Callback(Flags); + isSessionSwitching = false; + DosPostEventSem(SesSwitchRec.Event); + if (Flags == PM_DEACTIVATE && Mode == PM_SUSPEND_APP) + /* Suspend application until we switch back to our application */ + for (;;) { + DosSleep (500); + /* SesSwitchRec.Flags is volatile so optimizer + * won't load it into a register + */ + if (SesSwitchRec.Flags != -1) + goto again; + } +} + +/**************************************************************************** +REMARKS: +Waits until main thread processes the session switch event. +****************************************************************************/ +static void _PM_SessionSwitchEvent( + PM_saveState_cb saveState, + int flags) +{ + ULONG Count; + + if (DosRequestMutexSem(SesSwitchRec.Mutex, 10000)) + return; + + /* We're going to wait on that semaphore */ + DosResetEventSem(SesSwitchRec.Event, &Count); + SesSwitchRec.Callback = saveState; + SesSwitchRec.Flags = flags; + DosReleaseMutexSem(SesSwitchRec.Mutex); + + /* Now wait until all required operations are complete */ + DosWaitEventSem (SesSwitchRec.Event, 10000); +} + +/**************************************************************************** +REMARKS: +This is the thread responsible for tracking switches back to our +fullscreen session. +****************************************************************************/ +static void _PM_ConsoleSwitch( + PM_saveState_cb saveState) +{ + USHORT NotifyType; + + for (;;) { + if (VioModeWait(VMWR_POPUP, &NotifyType, 0) != 0) + break; + _PM_SessionSwitchEvent(saveState, PM_REACTIVATE); + } + VioModeUndo(UNDOI_RELEASEOWNER, UNDOK_ERRORCODE, (HVIO)0); +} + +/**************************************************************************** +REMARKS: +This is the thread responsible for tracking screen popups (usually fatal +error handler uses them). +****************************************************************************/ +static void _PM_ConsolePopup( + PM_saveState_cb saveState) +{ + USHORT NotifyType; + for (;;) { + if (VioSavRedrawWait(VSRWI_SAVEANDREDRAW, &NotifyType, 0) != 0) + break; + if (NotifyType == VSRWN_SAVE) + _PM_SessionSwitchEvent(saveState, PM_DEACTIVATE); + else if (NotifyType == VSRWN_REDRAW) + _PM_SessionSwitchEvent(saveState, PM_REACTIVATE); + } + VioSavRedrawUndo(UNDOI_RELEASEOWNER, UNDOK_ERRORCODE, (HVIO)0); +} + +/**************************************************************************** +REMARKS: +Set the suspend application callback for the fullscreen console. +****************************************************************************/ +void PMAPI PM_setSuspendAppCallback( + PM_saveState_cb saveState) +{ + /* If PM isn't loaded, this stuff will cause crashes! */ + if (__isShellLoaded()) { + if (saveState) { + /* Create the threads responsible for tracking console switches */ + SesSwitchRec.Flags = -1; + DosCreateMutexSem(NULL, &SesSwitchRec.Mutex, 0, FALSE); + DosCreateEventSem(NULL, &SesSwitchRec.Event, 0, FALSE); + _beginthread ((void(*)(void*))_PM_ConsoleSwitch,NULL,SESSION_SWITCH_STACK_SIZE, (void*)saveState); + _beginthread ((void(*)(void*))_PM_ConsolePopup,NULL,SESSION_SWITCH_STACK_SIZE, (void*)saveState); + } + else { + /* Kill the threads responsible for tracking console switches */ + VioModeUndo(UNDOI_RELEASEOWNER, UNDOK_TERMINATE, (HVIO)0); + VioSavRedrawUndo(UNDOI_RELEASEOWNER, UNDOK_TERMINATE, (HVIO)0); + DosCloseEventSem(SesSwitchRec.Event); + DosCloseMutexSem(SesSwitchRec.Mutex); + } + } +} + +/**************************************************************************** +REMARKS: +Restore the console state. +****************************************************************************/ +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + PM_HWND hwndConsole) +{ + CONSOLE_SAVE *cs = (CONSOLE_SAVE *)stateBuf; + VIOMODEINFO vmi; + + if (!cs) + return; + + memcpy(&vmi, &cs->vmi, sizeof (VIOMODEINFO)); + VioSetMode(&vmi, (HVIO)0); + VioSetCurPos(cs->CursorY, cs->CursorX, (HVIO)0); + VioWrtCellStr((PCH)cs->FrameBuffer, cs->vmi.col * cs->vmi.row * 2,0, 0, (HVIO)0); +} + +/**************************************************************************** +REMARKS: +Close the fullscreen console. +****************************************************************************/ +void PMAPI PM_closeConsole( + PM_HWND hwndConsole) +{ + /* Kill the threads responsible for tracking console switches */ + PM_setSuspendAppCallback(NULL); + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PM_setOSCursorLocation( + int x, + int y) +{ + /* If session switch is in progress, calling into VIO causes deadlocks! */ + /* Also this call to VIO screws up our console library on DBCS boxes... */ + if (!isSessionSwitching && !__IsDBCSSystem()) + VioSetCurPos(y,x,0); +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PM_setOSScreenWidth( + int width, + int height) +{ + /* Nothing to do in here */ + (void)width; + (void)height; +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + /* TODO: Implement this! */ + (void)ih; + (void)frequency; + return false; +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + /* TODO: Implement this! */ + (void)frequency; +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Implement this! */ +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + ulong boot = 3; + DosQuerySysInfo(QSV_BOOT_DRIVE,QSV_BOOT_DRIVE,&boot,sizeof(boot)); + return (char)('a' + boot - 1); +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files. +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + static char path[CCHMAXPATH]; + strcpy(path,"x:\\"); + path[0] = PM_getBootDrive(); + return path; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[CCHMAXPATH]; + if (getenv("NUCLEUS_PATH") != NULL) + return getenv("NUCLEUS_PATH"); + strcpy(path,"x:\\os2\\drivers"); + path[0] = PM_getBootDrive(); + PM_backslash(path); + strcat(path,"nucleus"); + return path; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[CCHMAXPATH]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + return PM_getMachineName(); +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + static char name[40],*env; + + if ((env = getenv("HOSTNAME")) != NULL) { + strncpy(name,env,sizeof(name)); + name[sizeof(name)-1] = 0; + return name; + } + return "OS2"; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + PM_init(); + return lowMem + 0x400; +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + PM_init(); + return lowMem + 0xA0000; +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + ulong baseAddr,baseOfs,linear; + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to mmap. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = base & 4095; + baseAddr = base & ~4095; + limit = ((limit+baseOfs+1+4095) & ~4095)-1; + parmsIn[0] = baseAddr; + parmsIn[1] = limit; + parmsIn[2] = isCached; + if ((linear = CallSDDHelp(PMHELP_MAPPHYS)) == 0) + return NULL; + return (void*)(linear + baseOfs); +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + parmsIn[0] = (ulong)ptr; + parmsIn[1] = limit; + CallSDDHelp(PMHELP_FREEPHYS); +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ulong PMAPI PM_getPhysicalAddr( + void *p) +{ + parmsIn[0] = (ulong)p; + return CallSDDHelp(PMHELP_GETPHYSICALADDR); +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + parmsIn[0] = (ulong)p; + parmsIn[1] = (ulong)length; + parmsIn[2] = (ulong)physAddress; + return CallSDDHelp(PMHELP_GETPHYSICALADDRRANGE); +} + +/**************************************************************************** +REMARKS: +Sleep for the specified number of milliseconds. +****************************************************************************/ +void PMAPI PM_sleep( + ulong milliseconds) +{ + DosSleep(milliseconds); +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified COM port. +****************************************************************************/ +int PMAPI PM_getCOMPort( + int port) +{ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified LPT port. +****************************************************************************/ +int PMAPI PM_getLPTPort( + int port) +{ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For Win9x we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + parmsIn[0] = size; + return (void*)CallSDDHelp(PMHELP_MALLOCSHARED); +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory. +****************************************************************************/ +void PMAPI PM_freeShared( + void *ptr) +{ + parmsIn[0] = (ulong)ptr; + CallSDDHelp(PMHELP_FREESHARED); +} + +/**************************************************************************** +REMARKS: +Map a linear memory address to the calling process address space. The +address will have been allocated in another process using the +PM_mapPhysicalAddr function. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + ulong baseAddr,baseOfs; + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to mmap. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = (ulong)base & 4095; + baseAddr = (ulong)base & ~4095; + limit = ((limit+baseOfs+1+4095) & ~4095)-1; + parmsIn[0] = (ulong)baseAddr; + parmsIn[1] = limit; + return (void*)(CallSDDHelp(PMHELP_MAPTOPROCESS)+baseOfs); +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + if (r_seg == 0xFFFF) + return &RMBuf[r_off]; + return lowMem + MK_PHYS(r_seg,r_off); +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + if (size > sizeof(RMBuf)) + return NULL; + *r_seg = 0xFFFF; + *r_off = 0x0000; + return &RMBuf; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* Nothing to do in here */ + (void)mem; +} + +#define INDPMI(reg) rmregs.aCRF.reg_##reg = regs->reg +#define OUTDPMI(reg) regs->reg = rmregs.aCRF.reg_##reg + +#define REG_OFFSET(field) (((ULONG)&(((VCRF*)0)->field)) / sizeof(ULONG)) + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + INTCRF rmregs; + ulong eax = 0; + + if (!InitInt10()) + return; + memset(&rmregs, 0, sizeof(rmregs)); + rmregs.ulBIOSIntNo = intno; + INDPMI(eax); INDPMI(ebx); INDPMI(ecx); INDPMI(edx); INDPMI(esi); INDPMI(edi); + rmregs.aCRF.reg_ds = regs->ds; + rmregs.aCRF.reg_es = regs->es; + if (intno == 0x10) { + eax = rmregs.aCRF.reg_eax; + switch (eax & 0xFFFF) { + case 0x4F00: + /* We have to hack the way this function works, due to + * some bugs in the IBM mini-VDM BIOS support. Specifically + * we need to make the input buffer and output buffer the + * 'same' buffer, and that ES:SI points to the output + * buffer (ignored by the BIOS). The data will end up + * being returned in the input buffer, except for the + * first four bytes ('VESA') that will not be returned. + */ + rmregs.pB[0].bBufferType = INPUT_BUFFER; + rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); + rmregs.pB[0].pAddress = RMBuf; + rmregs.pB[0].ulSize = 4; + rmregs.pB[1].bBufferType = OUTPUT_BUFFER; + rmregs.pB[1].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[1].bOffCRF = REG_OFFSET(reg_esi); + rmregs.pB[1].pAddress = ((PBYTE)RMBuf)+4; + rmregs.pB[1].ulSize = 512-4; + break; + case 0x4F01: + rmregs.pB[0].bBufferType = OUTPUT_BUFFER; + rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); + rmregs.pB[0].pAddress = RMBuf; + rmregs.pB[0].ulSize = 256; + break; + case 0x4F02: + rmregs.pB[0].bBufferType = INPUT_BUFFER; + rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); + rmregs.pB[0].pAddress = RMBuf; + rmregs.pB[0].ulSize = 256; + break; + case 0x4F09: + rmregs.pB[0].bBufferType = INPUT_BUFFER; + rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); + rmregs.pB[0].pAddress = RMBuf; + rmregs.pB[0].ulSize = 1024; + break; + case 0x4F0A: + /* Due to bugs in the mini-VDM in OS/2, the 0x4F0A protected + * mode interface functions will not work (we never get any + * selectors returned), so we fail this function here. The + * rest of the VBE/Core driver will work properly if this + * function is failed, because the VBE 2.0 and 3.0 specs + * allow for this. + */ + regs->eax = 0x014F; + return; + } + } + if (useVPMI) + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,NULL,&rmregs); + else { + DosSysCtl(6, &rmregs); + } + + OUTDPMI(eax); OUTDPMI(ebx); OUTDPMI(ecx); OUTDPMI(edx); OUTDPMI(esi); OUTDPMI(edi); + if (((regs->eax & 0xFFFF) == 0x004F) && ((eax & 0xFFFF) == 0x4F00)) { + /* Hack to fix up the missing 'VESA' string for mini-VDM */ + memcpy(RMBuf,"VESA",4); + } + regs->ds = rmregs.aCRF.reg_ds; + regs->es = rmregs.aCRF.reg_es; + regs->flags = rmregs.aCRF.reg_eflag; +} + +#define IN(reg) rmregs.reg = in->e.reg +#define OUT(reg) out->e.reg = rmregs.reg + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + DPMI_int86(intno,&rmregs); + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + DPMI_int86(intno,&rmregs); + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->cs = rmregs.cs; + sregs->ss = rmregs.ss; + sregs->ds = rmregs.ds; + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Call a real mode far function. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *in, + RMSREGS *sregs) +{ + PM_fatalError("PM_callRealMode not supported on OS/2!"); +} + +/**************************************************************************** +REMARKS: +Return the amount of available memory. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + /* Unable to get reliable values from OS/2 for this */ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of locked, physical memory for DMA operations. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + parmsIn[0] = size; + parmsIn[1] = contiguous; + parmsIn[2] = below16M; + CallSDDHelp(PMHELP_ALLOCLOCKED); + *physAddr = parmsOut[1]; + return (void*)parmsOut[0]; +} + +/**************************************************************************** +REMARKS: +Free a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + parmsIn[0] = (ulong)p; + CallSDDHelp(PMHELP_FREELOCKED); +} + +/**************************************************************************** +REMARKS: +Allocates a new block of pages for the page block manager. +****************************************************************************/ +static pageblock *PM_addNewPageBlock(void) +{ + int i; + pageblock *newBlock; + char *p,*next; + + /* Allocate memory for the new page block, and add to head of list */ + if (DosAllocSharedMem((void**)&newBlock,NULL,PAGE_BLOCK_SIZE,OBJ_GETTABLE | PAG_READ | PAG_WRITE | PAG_COMMIT)) + return NULL; + if (!PM_lockDataPages(newBlock,PAGE_BLOCK_SIZE,&newBlock->lockHandle)) + return NULL; + newBlock->prev = NULL; + newBlock->next = pageBlocks; + if (pageBlocks) + pageBlocks->prev = newBlock; + pageBlocks = newBlock; + + /* Initialise the page aligned free list for the page block */ + newBlock->freeCount = PAGES_PER_BLOCK; + newBlock->freeList = p = (char*)(((ulong)(newBlock + 1) + (PM_PAGE_SIZE-1)) & ~(PM_PAGE_SIZE-1)); + newBlock->freeListStart = newBlock->freeList; + newBlock->freeListEnd = p + (PAGES_PER_BLOCK-1) * PM_PAGE_SIZE; + for (i = 0; i < PAGES_PER_BLOCK; i++,p = next) + FREELIST_NEXT(p) = next = p + PM_PAGE_SIZE; + FREELIST_NEXT(p - PM_PAGE_SIZE) = NULL; + return newBlock; +} + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ + pageblock *block; + void *p; + + /* Scan the block list looking for any free blocks. Allocate a new + * page block if no free blocks are found. + */ + for (block = pageBlocks; block != NULL; block = block->next) { + if (block->freeCount) + break; + } + if (block == NULL && (block = PM_addNewPageBlock()) == NULL) + return NULL; + block->freeCount--; + p = block->freeList; + block->freeList = FREELIST_NEXT(p); + (void)locked; + return p; +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ + pageblock *block; + + /* First find the page block that this page belongs to */ + for (block = pageBlocks; block != NULL; block = block->next) { + if (p >= block->freeListStart && p <= block->freeListEnd) + break; + } + CHECK(block != NULL); + + /* Now free the block by adding it to the free list */ + FREELIST_NEXT(p) = block->freeList; + block->freeList = p; + if (++block->freeCount == PAGES_PER_BLOCK) { + /* If all pages in the page block are now free, free the entire + * page block itself. + */ + if (block == pageBlocks) { + /* Delete from head */ + pageBlocks = block->next; + if (block->next) + block->next->prev = NULL; + } + else { + /* Delete from middle of list */ + CHECK(block->prev != NULL); + block->prev->next = block->next; + if (block->next) + block->next->prev = block->prev; + } + + /* Unlock the memory and free it */ + PM_unlockDataPages(block,PAGE_BLOCK_SIZE,&block->lockHandle); + DosFreeMem(block); + } +} + +/**************************************************************************** +REMARKS: +Map in all the shared memory blocks for managing the memory pages above. +****************************************************************************/ +void PMAPI PM_mapSharedPages(void) +{ + pageblock *block; + + /* Map all the page blocks above into the shared memory for process */ + for (block = pageBlocks; block != NULL; block = block->next) { + DosGetSharedMem(block, PAG_READ | PAG_WRITE); + } +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages( + void *p, + uint len, + PM_lockHandle *lockHandle) +{ + parmsIn[0] = (ulong)p; + parmsIn[1] = len; + CallSDDHelp(PMHELP_LOCKPAGES); + lockHandle->h[0] = parmsOut[1]; + lockHandle->h[1] = parmsOut[2]; + lockHandle->h[2] = parmsOut[3]; + return parmsOut[0]; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages( + void *p, + uint len, + PM_lockHandle *lockHandle) +{ + parmsIn[0] = lockHandle->h[0]; + parmsIn[1] = lockHandle->h[1]; + parmsIn[2] = lockHandle->h[2]; + return CallSDDHelp(PMHELP_UNLOCKPAGES); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lockHandle) +{ + parmsIn[0] = (ulong)p; + parmsIn[1] = len; + CallSDDHelp(PMHELP_LOCKPAGES); + lockHandle->h[0] = parmsOut[1]; + lockHandle->h[1] = parmsOut[2]; + lockHandle->h[2] = parmsOut[3]; + return parmsOut[0]; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lockHandle) +{ + parmsIn[0] = lockHandle->h[0]; + parmsIn[1] = lockHandle->h[1]; + parmsIn[2] = lockHandle->h[2]; + return CallSDDHelp(PMHELP_UNLOCKPAGES); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + INTCRF rmregs; + + if (!InitInt10()) + return; + memset(&rmregs, 0, sizeof(rmregs)); + rmregs.ulBIOSIntNo = 0x10; + rmregs.aCRF.reg_eax = 0x4F05; + rmregs.aCRF.reg_ebx = 0x0000; + rmregs.aCRF.reg_edx = bank; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + INTCRF rmregs; + + if (!InitInt10()) + return; + memset(&rmregs, 0, sizeof(rmregs)); + rmregs.ulBIOSIntNo = 0x10; + rmregs.aCRF.reg_eax = 0x4F05; + rmregs.aCRF.reg_ebx = 0x0000; + rmregs.aCRF.reg_edx = bank; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); + rmregs.ulBIOSIntNo = 0x10; + rmregs.aCRF.reg_eax = 0x4F05; + rmregs.aCRF.reg_ebx = 0x0001; + rmregs.aCRF.reg_edx = bank; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + INTCRF rmregs; + + if (!InitInt10()) + return; + memset(&rmregs, 0, sizeof(rmregs)); + rmregs.ulBIOSIntNo = 0x10; + rmregs.aCRF.reg_eax = 0x4F07; + rmregs.aCRF.reg_ebx = waitVRT; + rmregs.aCRF.reg_ecx = x; + rmregs.aCRF.reg_edx = y; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + (void)axVal; + (void)BIOSPhysAddr; + (void)mappedBIOS; + (void)BIOSLen; + return false; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + return MTRR_enableWriteCombine(base,size,type); +} + +/* TODO: Move the MTRR helper stuff into the call gate, or better yet */ +/* entirely into the ring 0 helper driver!! */ + +/* MTRR helper functions. To make it easier to implement the MTRR support + * under OS/2, we simply put our ring 0 helper functions into the + * helper device driver rather than the entire MTRR module. This makes + * it easier to maintain the MTRR support since we don't need to deal + * with 16-bit ring 0 code in the MTRR library. + */ + +/**************************************************************************** +REMARKS: +Flush the translation lookaside buffer. +****************************************************************************/ +void PMAPI PM_flushTLB(void) +{ + CallSDDHelp(PMHELP_FLUSHTLB); +} + +/**************************************************************************** +REMARKS: +Return true if ring 0 (or if we can call the helpers functions at ring 0) +****************************************************************************/ +ibool _ASMAPI _MTRR_isRing0(void) +{ + return true; +} + +/**************************************************************************** +REMARKS: +Read and return the value of the CR4 register +****************************************************************************/ +ulong _ASMAPI _MTRR_saveCR4(void) +{ + return CallSDDHelp(PMHELP_SAVECR4); +} + +/**************************************************************************** +REMARKS: +Restore the value of the CR4 register +****************************************************************************/ +void _ASMAPI _MTRR_restoreCR4(ulong cr4Val) +{ + parmsIn[0] = cr4Val; + CallSDDHelp(PMHELP_RESTORECR4); +} + +/**************************************************************************** +REMARKS: +Read a machine status register for the CPU. +****************************************************************************/ +void _ASMAPI _MTRR_readMSR( + ulong reg, + ulong *eax, + ulong *edx) +{ + parmsIn[0] = reg; + CallSDDHelp(PMHELP_READMSR); + *eax = parmsOut[0]; + *edx = parmsOut[1]; +} + +/**************************************************************************** +REMARKS: +Write a machine status register for the CPU. +****************************************************************************/ +void _ASMAPI _MTRR_writeMSR( + ulong reg, + ulong eax, + ulong edx) +{ + parmsIn[0] = reg; + parmsIn[1] = eax; + parmsIn[2] = edx; + CallSDDHelp(PMHELP_WRITEMSR); +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: Implement this to load shared libraries! */ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: Implement this! */ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: Implement this! */ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + FILEFINDBUF3 *blk) +{ + ulong dwSize = findData->dwSize; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + if (blk->attrFile & FILE_READONLY) + findData->attrib |= PM_FILE_READONLY; + if (blk->attrFile & FILE_DIRECTORY) + findData->attrib |= PM_FILE_DIRECTORY; + if (blk->attrFile & FILE_ARCHIVED) + findData->attrib |= PM_FILE_ARCHIVE; + if (blk->attrFile & FILE_HIDDEN) + findData->attrib |= PM_FILE_HIDDEN; + if (blk->attrFile & FILE_SYSTEM) + findData->attrib |= PM_FILE_SYSTEM; + findData->sizeLo = blk->cbFile; + findData->sizeHi = 0; + strncpy(findData->name,blk->achName,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +#define FIND_MASK (FILE_ARCHIVED | FILE_DIRECTORY | FILE_SYSTEM | FILE_HIDDEN | FILE_READONLY) + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + FILEFINDBUF3 blk; + HDIR hdir = HDIR_CREATE; + ulong count = 1; + + if (DosFindFirst((PSZ)filename,&hdir,FIND_MASK,&blk,sizeof(blk),&count,FIL_STANDARD) == NO_ERROR) { + convertFindData(findData,&blk); + return (void*)hdir; + } + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + FILEFINDBUF3 blk; + ulong count = 1; + + if (DosFindNext((HDIR)handle,&blk,sizeof(blk),&count) == NO_ERROR) { + convertFindData(findData,&blk); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + DosFindClose((HDIR)handle); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 0 - Current drive + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + ulong cntDisk,cntDriveMap; + ibool valid; + + DosQueryCurrentDisk(&cntDisk,&cntDriveMap); + valid = (DosSetDefaultDisk(drive) == NO_ERROR); + DosSetDefaultDisk(cntDisk); + return valid; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + ulong length = len; + + DosQueryCurrentDir(drive, (PSZ)dir, &length); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + FILESTATUS3 s; + + if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s))) + return; + s.attrFile = 0; + if (attrib & PM_FILE_READONLY) + s.attrFile |= FILE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + s.attrFile |= FILE_ARCHIVED; + if (attrib & PM_FILE_HIDDEN) + s.attrFile |= FILE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + s.attrFile |= FILE_SYSTEM; + DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s),0L); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + FILESTATUS3 fs3; + uint retval = 0; + + if (DosQueryPathInfo((PSZ)filename, FIL_STANDARD, &fs3, sizeof(FILESTATUS3))) + return 0; + if (fs3.attrFile & FILE_READONLY) + retval |= PM_FILE_READONLY; + if (fs3.attrFile & FILE_ARCHIVED) + retval |= PM_FILE_ARCHIVE; + if (fs3.attrFile & FILE_HIDDEN) + retval |= PM_FILE_HIDDEN; + if (fs3.attrFile & FILE_SYSTEM) + retval |= PM_FILE_SYSTEM; + return retval; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return DosCreateDir((PSZ)filename,NULL) == NO_ERROR; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return DosDeleteDir((PSZ)filename) == NO_ERROR; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + FILESTATUS3 fs3; + struct tm tc; + struct tm *ret; + time_t tt; + + if (DosQueryPathInfo((PSZ)filename, FIL_STANDARD, &fs3, sizeof(FILESTATUS3))) + return false; + if (gmTime) { + tc.tm_year = fs3.fdateLastWrite.year + 80; + tc.tm_mon = fs3.fdateLastWrite.month - 1; + tc.tm_mday = fs3.fdateLastWrite.day; + tc.tm_hour = fs3.ftimeLastWrite.hours; + tc.tm_min = fs3.ftimeLastWrite.minutes; + tc.tm_sec = fs3.ftimeLastWrite.twosecs * 2; + if((tt = mktime(&tc)) == -1) + return false; + if(!(ret = gmtime(&tt))) + return false; + time->sec = ret->tm_sec; + time->day = ret->tm_mday; + time->mon = ret->tm_mon + 1; + time->year = ret->tm_year - 80; + time->min = ret->tm_min; + time->hour = ret->tm_hour; + } + else { + time->sec = fs3.ftimeLastWrite.twosecs * 2; + time->day = fs3.fdateLastWrite.day; + time->mon = fs3.fdateLastWrite.month; + time->year = fs3.fdateLastWrite.year; + time->min = fs3.ftimeLastWrite.minutes; + time->hour = fs3.ftimeLastWrite.hours; + } + return true; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + FILESTATUS3 fs3; + struct tm tc; + struct tm *ret; + time_t tt; + + if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&fs3,sizeof(fs3))) + return false; + if (gmTime) { + tc.tm_year = time->year + 80; + tc.tm_mon = time->mon - 1; + tc.tm_mday = time->day; + tc.tm_hour = time->hour; + tc.tm_min = time->min; + tc.tm_sec = time->sec; + if((tt = mktime(&tc)) == -1) + return false; + ret = localtime(&tt); + fs3.ftimeLastWrite.twosecs = ret->tm_sec / 2; + fs3.fdateLastWrite.day = ret->tm_mday; + fs3.fdateLastWrite.month = ret->tm_mon + 1; + fs3.fdateLastWrite.year = ret->tm_year - 80; + fs3.ftimeLastWrite.minutes = ret->tm_min; + fs3.ftimeLastWrite.hours = ret->tm_hour; + } + else { + fs3.ftimeLastWrite.twosecs = time->sec / 2; + fs3.fdateLastWrite.day = time->day; + fs3.fdateLastWrite.month = time->mon; + fs3.fdateLastWrite.year = time->year; + fs3.ftimeLastWrite.minutes = time->min; + fs3.ftimeLastWrite.hours = time->hour; + } + memcpy(&fs3.fdateLastAccess, &fs3.fdateLastWrite, sizeof(FDATE)); + memcpy(&fs3.fdateCreation, &fs3.fdateLastWrite, sizeof(FDATE)); + memcpy(&fs3.ftimeLastAccess, &fs3.ftimeLastWrite, sizeof(FTIME)); + memcpy(&fs3.ftimeCreation, &fs3.ftimeLastWrite, sizeof(FTIME)); + DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&fs3,sizeof(FILESTATUS3),0L); + return true; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c new file mode 100644 index 0000000..579ef2c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c new file mode 100644 index 0000000..30ffe43 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c @@ -0,0 +1,110 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: OS/2 +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ulong frequency; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ + DosTmrQueryFreq(&frequency); +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +#define __LZTimerOn(tm) DosTmrQueryTime((QWORD*)&tm->start) + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger tmLap,tmCount; + + DosTmrQueryTime((QWORD*)&tmLap); + _CPU_diffTime64(&tm->start,&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,frequency); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) DosTmrQueryTime((QWORD*)&tm->end) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,frequency); +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + ULONG count; + DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) ); + return count; +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c b/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c new file mode 100644 index 0000000..7af20a9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c @@ -0,0 +1,170 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: IBM PC (OS/2) +* +* Description: OS/2 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static int oldMouseState; /* Old mouse state */ +static ulong oldKeyMessage; /* Old keyboard state */ +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ +HMOU _EVT_hMouse; /* Handle to the mouse driver */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under OS/2 */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from OS/2 into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + /* TODO: Implement this for OS/2 Presentation Manager apps! */ +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + EVT.mouseMove = mouseMove; + initEventQueue(); + oldMouseState = 0; + oldKeyMessage = 0; + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* TODO: OS/2 PM specific initialisation code! */ + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for OS/2 */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for OS/2 */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* TODO: OS/2 PM specific exit code */ +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +#define _EVT_setMousePos(x,y) diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h new file mode 100644 index 0000000..0b69f82 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h @@ -0,0 +1,36 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include diff --git a/board/MAI/bios_emulator/scitech/src/pm/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/oshdr.h new file mode 100644 index 0000000..404e5c9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/oshdr.h @@ -0,0 +1,70 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file to pull in OS specific headers for the target +* OS environment. +* +****************************************************************************/ + +#if defined(__SMX32__) +#include "smx/oshdr.h" +#elif defined(__RTTARGET__) +#include "rttarget/oshdr.h" +#elif defined(__REALDOS__) +#include "dos/oshdr.h" +#elif defined(__WIN32_VXD__) +#include "vxd/oshdr.h" +#elif defined(__NT_DRIVER__) +#include "ntdrv/oshdr.h" +#elif defined(__WINDOWS32__) +#include "win32/oshdr.h" +#elif defined(__OS2_VDD__) +#include "vxd/oshdr.h" +#elif defined(__OS2__) +#if defined(__OS2_PM__) +#include "os2pm/oshdr.h" +#else +#include "os2/oshdr.h" +#endif +#elif defined(__LINUX__) +#if defined(__USE_X11__) +#include "x11/oshdr.h" +#else +#include "linux/oshdr.h" +#endif +#elif defined(__QNX__) +#if defined(__USE_PHOTON__) +#include "photon/oshdr.h" +#elif defined(__USE_X11__) +#include "x11/oshdr.h" +#else +#include "qnx/oshdr.h" +#endif +#elif defined(__BEOS__) +#include "beos/oshdr.h" +#else +#error PM library not ported to this platform yet! +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/photon/event.c b/board/MAI/bios_emulator/scitech/src/pm/photon/event.c new file mode 100644 index 0000000..581da16 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/photon/event.c @@ -0,0 +1,268 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX Photon GUI +* +* Description: QNX fullscreen console implementation for the SciTech +* cross platform event library. +* +****************************************************************************/ + +/*--------------------------- Global variables ----------------------------*/ + +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under Linux */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +static ibool _EVT_isKeyDown( + uchar scancode) +{ + return (KeyState[(scancode & 0xf8) >> 3] & (1 << (scancode & 0x7)) ? + true : false); +} + +/**************************************************************************** +REMARKS: +Retrieves all events from the mouse/keyboard event queue and stuffs them +into the MGL event queue for further processing. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + int pid; + uint msg, but_stat, message; + uchar evt[sizeof (PhEvent_t) + 1024]; + PhEvent_t *event = (void *)evt; + PhKeyEvent_t *key; + PhPointerEvent_t *mouse; + static int extended; + event_t _evt; + + while (count < EVENTQSIZE) { + uint mods = 0, keyp = 0; + + pid = Creceive(0, &msg, sizeof (msg)); + + if (pid == -1) + return; + + if (PhEventRead(pid, event, sizeof (evt)) == Ph_EVENT_MSG) { + memset(&evt, 0, sizeof (evt)); + if (event->type == Ph_EV_KEY) { + key = PhGetData(event); + + if (key->key_flags & KEY_SCAN_VALID) { + keyp = key->key_scan; + if (key->key_flags & KEY_DOWN) + KeyState[(keyp & 0xf800) >> 11] + |= 1 << ((keyp & 0x700) >> 8); + else + KeyState[(keyp & 0xf800) >> 11] + &= ~(1 << ((keyp & 0x700) >> 8)); + } + if ((key->key_flags & KEY_SYM_VALID) || extended) + keyp |= key->key_sym; + + /* No way to tell left from right... */ + if (key->key_mods & KEYMOD_SHIFT) + mods = (EVT_LEFTSHIFT | EVT_RIGHTSHIFT); + if (key->key_mods & KEYMOD_CTRL) + mods |= (EVT_CTRLSTATE | EVT_LEFTCTRL); + if (key->key_mods & KEYMOD_ALT) + mods |= (EVT_ALTSTATE | EVT_LEFTALT); + + _evt.when = evt->timestamp; + if (key->key_flags & KEY_REPEAT) { + _evt.what = EVT_KEYREPEAT; + _evt.message = 0x10000; + } + else if (key->key_flags & KEY_DOWN) + _evt.what = EVT_KEYDOWN; + else + _evt.what = EVT_KEYUP; + _evt.modifiers = mods; + _evt.message |= keyp; + + addEvent(&_evt); + + switch(key->key_scan & 0xff00) { + case 0xe000: + extended = 1; + break; + case 0xe001: + extended = 2; + break; + default: + if (extended) + extended--; + } + } + else if (event->type & Ph_EV_PTR_ALL) { + but_stat = message = 0; + mouse = PhGetData(event); + + if (mouse->button_state & Ph_BUTTON_3) + but_stat = EVT_LEFTBUT; + if (mouse->buttons & Ph_BUTTON_3) + message = EVT_LEFTBMASK; + + if (mouse->button_state & Ph_BUTTON_1) + but_stat |= EVT_RIGHTBUT; + if (mouse->buttons & Ph_BUTTON_1) + message |= EVT_RIGHTBMASK; + + _evt.when = evt->timestamp; + if (event->type & Ph_EV_PTR_MOTION) { + _evt.what = EVT_MOUSEMOVE; + _evt.where_x = mouse->pos.x; + _evt.where_y = mouse->pos.y; + _evt.modifiers = but_stat; + addEvent(&_evt); + } + if (event->type & Ph_EV_BUT_PRESS) + _evt.what = EVT_MOUSEDOWN; + else + _evt.what = EVT_MOUSEUP; + _evt.where_x = mouse->pos.x; + _evt.where_y = mouse->pos.y; + _evt.modifiers = but_stat; + _evt.message = message; + addEvent(&_evt); + } + } + else + return; + } +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort( + int signo) +{ + char buf[80]; + + EVT_exit(); + sprintf(buf,"Terminating on signal %d",signo); + PM_fatalError(buf); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset((void *)KeyState, 0, sizeof (KeyState)); + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + /* TODO: Need to call Input to change the coordinates that it returns */ + /* for mouse events!! */ +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for Photon */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for Photon */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h new file mode 100644 index 0000000..3c72563 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h @@ -0,0 +1,38 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX Photon GUI +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include diff --git a/board/MAI/bios_emulator/scitech/src/pm/pm.vpw b/board/MAI/bios_emulator/scitech/src/pm/pm.vpw new file mode 100644 index 0000000..26e68a7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pm.vpw @@ -0,0 +1,43 @@ +[Dependencies] +[CurrentProject] +curproj=pmlinux.vpj +[ProjectFiles] +pmcommon.vpj +pmdos.vpj +pmlinux.vpj +pmqnx.vpj +pmvxd.vpj +pmwin32.vpj +z_samples.vpj +..\a-global includes.vpj +[TreeExpansion] +"..\a-global includes.vpj" 0 +pmcommon.vpj 0 +pmdos.vpj 0 +pmlinux.vpj 0 +pmqnx.vpj 0 +pmvxd.vpj 0 +pmwin32.vpj 0 +z_samples.vpj 1 1 +[State] +SCREEN: 1280 1024 0 0 960 746 0 0 M 0 0 0 0 977 631 +CWD: C:\scitech\src\pm +FILEHIST: 9 +C:\scitech\makedefs\gcc_win32.mk +C:\scitech\bin\gcc2-w32.bat +C:\scitech\bin\gcc2-c32.bat +C:\scitech\bin\gcc2-linux.bat +C:\scitech\makedefs\gcc_linux.mk +C:\scitech\src\pm\linux\event.c +C:\scitech\src\pm\linux\oshdr.h +C:\scitech\src\pm\event.c +C:\scitech\src\pm\pmlinux.vpj +[ProjectDates] +pmcommon.vpj=20010517164335290 +pmdos.vpj=20010517164335290 +pmlinux.vpj=20010620175829812 +pmqnx.vpj=20010517164335290 +pmvxd.vpj=20010517164335306 +pmwin32.vpj=20010517164335306 +z_samples.vpj=20010517164335306 +..\a-global includes.vpj=20010517164334978 diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj new file mode 100644 index 0000000..48b872d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj @@ -0,0 +1,45 @@ +[COMPILER] +version=5.0b +MACRO=\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\nOther Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n*.*\n +FILTERASSOCIATEFILETYPES=0 0 0 0 +FILTERAPPCOMMAND=\n\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|hide|:Compile:&Compile, +make=concur|capture|hide|clear|saveall|:Build:&Build, +rebuild=concur|capture|hide|clear|saveall|:Rebuild:&Rebuild, +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +common.c +cpuinfo.c +debug.c +event.c +makefile +oshdr.h +ztimer.c +..\common\agplib.c +codepage\us_eng.c +common\_cpuinfo.asm +common\_dma.asm +common\_int64.asm +common\_joy.asm +common\_mtrr.asm +common\_pcilib.asm +common\agp.c +common\keyboard.c +common\malloc.c +common\mtrr.c +common\pcilib.c +common\unixio.c +common\vgastate.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj new file mode 100644 index 0000000..1157513 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj @@ -0,0 +1,41 @@ +[SciTech] +compiler=wc10- +targetos=d32 +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,TEST_HARNESS=1 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|clear|:Compile:&Compile,dmake %n.obj -u %b +make=concur|capture|clear|saveall|:Build:&Build,dmake install %b +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u %b +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +dos\_event.asm +dos\_lztimer.asm +dos\_pm.asm +dos\_pmdos.asm +dos\_vflat.asm +dos\cpuinfo.c +dos\event.c +dos\oshdr.h +dos\pm.c +dos\pmdos.c +dos\vflat.c +dos\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] +config=,NORMAL_BUILD=1 +config=,TEST_HARNESS=1 diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj new file mode 100644 index 0000000..0bfbf84 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj @@ -0,0 +1,35 @@ +[SciTech] +compiler=gcc2- +targetos=linux +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +activeconfig=,install BUILD_DLL=1 +compile=concur|capture|clear|:Compile:&Compile,dmake %n.o -u +make=concur|capture|clear|saveall|:Build:&Build,dmake %b +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake -u %b +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +linux\cpuinfo.c +linux\event.c +linux\oshdr.h +linux\pm.c +linux\vflat.c +linux\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] +config=,install BUILD_DLL=1 +config=,install diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj new file mode 100644 index 0000000..3ec35a7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj @@ -0,0 +1,39 @@ +[SciTech] +compiler=vc60- +targetos=drvw2k +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|:Build:&Build,dmake install +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|:Clean Directory:&Clean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +..\..\include\ntdriver.h +ntdrv\_pm.asm +ntdrv\cpuinfo.c +ntdrv\int86.c +ntdrv\irq.c +ntdrv\mem.c +ntdrv\oshdr.h +ntdrv\pm.c +ntdrv\stdio.c +ntdrv\stdlib.c +ntdrv\vflat.c +ntdrv\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj new file mode 100644 index 0000000..d541702 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj @@ -0,0 +1,35 @@ +[SciTech] +compiler=wc10- +targetos=qnx +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|clear|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|:Build:&Build,dmake install +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +qnx\_mtrrqnx.asm +qnx\cpuinfo.c +qnx\event.c +qnx\mtrrqnx.c +qnx\oshdr.h +qnx\pm.c +qnx\vflat.c +qnx\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj new file mode 100644 index 0000000..1fcf911 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj @@ -0,0 +1,34 @@ +[SciTech] +compiler=bc50- +targetos=vxd +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|nochangedir|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|nochangedir|:Build:&Build,dmake install +rebuild=concur|capture|clear|saveall|nochangedir|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u +debug=concur|capture|hide|savenone|nochangedir|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:&Clean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +vxd\_pm.asm +vxd\cpuinfo.c +vxd\fileio.c +vxd\oshdr.h +vxd\pm.c +vxd\vflat.c +vxd\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj new file mode 100644 index 0000000..ace6822 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj @@ -0,0 +1,35 @@ +[SciTech] +compiler=vc60- +targetos=c32 +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|:Build:&Build,dmake install +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|savenone|:Clean Directory:&Clean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +win32\_pmwin32.asm +win32\cpuinfo.c +win32\ddraw.c +win32\event.c +win32\oshdr.h +win32\pm.c +win32\vflat.c +win32\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm b/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm new file mode 100644 index 0000000..5a3fe10 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm @@ -0,0 +1,226 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM +;* Environment: QNX +;* +;* Description: Assembler support routines for the Memory Type Range Register +;* (MTRR) module for QNX. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _mtrrqnx ; Set up memory model + +begdataseg _mtrrqnx ; Start of code segment + +ifdef USE_NASM +%define R0_FLUSH_TLB 0 +%define R0_SAVE_CR4 1 +%define R0_RESTORE_CR4 2 +%define R0_READ_MSR 3 +%define R0_WRITE_MSR 4 +else +R0_FLUSH_TLB EQU 0 +R0_SAVE_CR4 EQU 1 +R0_RESTORE_CR4 EQU 2 +R0_READ_MSR EQU 3 +R0_WRITE_MSR EQU 4 +endif + +cpublic _PM_R0 +_PM_R0_service dd 0 +_PM_R0_reg dd 0 +_PM_R0_eax dd 0 +_PM_R0_edx dd 0 + +enddataseg _mtrrqnx ; Start of code segment + +begcodeseg _mtrrqnx ; Start of code segment + +P586 + +;---------------------------------------------------------------------------- +; ulong _MTRR_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _MTRR_disableInt + + pushfd ; Put flag word on stack +; cli ; Disable interrupts! + pop eax ; deposit flag word in return register + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_restoreInt(ulong ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _MTRR_restoreInt + + ARG ps:ULONG + + push ebp + mov ebp,esp ; Set up stack frame + push [ULONG ps] + popfd ; Restore processor status (and interrupts) + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_getCx86(uchar reg); +;---------------------------------------------------------------------------- +; Read a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_getCx86 + + ARG reg:UCHAR + + enter_c + mov al,[reg] + out 22h,al + in al,23h + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_setCx86(uchar reg,uchar val); +;---------------------------------------------------------------------------- +; Write a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_setCx86 + + ARG reg:UCHAR, val:UCHAR + + enter_c + mov al,[reg] + out 22h,al + mov al,[val] + out 23h,al + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _PM_ring0_isr(void); +;---------------------------------------------------------------------------- +; Ring 0 clock interrupt handler that we use to execute the MTRR support +; code. +;---------------------------------------------------------------------------- +cprocnear _PM_ring0_isr + +;-------------------------------------------------------- +; void PM_flushTLB(void); +;-------------------------------------------------------- + pushad + cmp [DWORD _PM_R0_service],R0_FLUSH_TLB + jne @@1 + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB + jmp @@Exit + +;-------------------------------------------------------- +; ulong _MTRR_saveCR4(void); +;-------------------------------------------------------- +@@1: cmp [DWORD _PM_R0_service],R0_SAVE_CR4 + jne @@2 + +; Save value of CR4 and clear Page Global Enable (bit 7) + + mov ebx,cr4 + mov eax,ebx + and al,7Fh + mov cr4,eax + +; Disable and flush caches + + mov eax,cr0 + or eax,40000000h + wbinvd + mov cr0,eax + wbinvd + +; Return value from CR4 + + mov [_PM_R0_reg],ebx + jmp @@Exit + +;-------------------------------------------------------- +; void _MTRR_restoreCR4(ulong cr4Val) +;-------------------------------------------------------- +@@2: cmp [DWORD _PM_R0_service],R0_RESTORE_CR4 + jne @@3 + + mov eax,cr0 + and eax,0BFFFFFFFh + mov cr0,eax + mov eax,[_PM_R0_reg] + mov cr4,eax + jmp @@Exit + +;-------------------------------------------------------- +; void _MTRR_readMSR(int reg, ulong FAR *eax, ulong FAR *edx); +;-------------------------------------------------------- +@@3: cmp [DWORD _PM_R0_service],R0_READ_MSR + jne @@4 + + mov ecx,[_PM_R0_reg] + rdmsr + mov [_PM_R0_eax],eax + mov [_PM_R0_edx],edx + jmp @@Exit + +;-------------------------------------------------------- +; void _MTRR_writeMSR(int reg, ulong eax, ulong edx); +;-------------------------------------------------------- +@@4: cmp [DWORD _PM_R0_service],R0_WRITE_MSR + jne @@Exit + + mov ecx,[_PM_R0_reg] + mov eax,[_PM_R0_eax] + mov edx,[_PM_R0_edx] + wrmsr + jmp @@Exit + +@@Exit: mov [DWORD _PM_R0_service],-1 + popad + mov eax,0 + retf + +cprocend + +endcodeseg _mtrrqnx + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c new file mode 100644 index 0000000..a878254 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c @@ -0,0 +1,64 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: QNX specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +TODO: We should implement this for QNX! +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +TODO: We should implement this for QNX! +****************************************************************************/ +#define RestoreThreadPriority(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = CLOCKS_PER_SEC * 1000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + (t)->low = clock() * 1000; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c new file mode 100644 index 0000000..45cd514 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c @@ -0,0 +1,601 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: QNX fullscreen console implementation for the SciTech +* cross platform event library. +* +****************************************************************************/ + +#include +#include + +/*--------------------------- Global variables ----------------------------*/ + +#ifndef __QNXNTO__ +static struct _mouse_ctrl *_PM_mouse_ctl; +static int _PM_keyboard_fd = -1; +/*static int _PM_modifiers, _PM_leds; */ +#else +static int kbd_fd = -1, mouse_fd = -1; +#endif +static int kill_pid = 0; +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +#define TIME_TO_MSEC(__t) ((__t).tv_nsec / 1000000 + (__t).tv_sec * 1000) + +#define LED_NUM 1 +#define LED_CAP 2 +#define LED_SCR 4 + +/* Scancode mappings on QNX for special keys */ + +typedef struct { + int scan; + int map; + } keymap; + +/* TODO: Fix this and set it up so we can do a binary search! */ + +keymap keymaps[] = { + {96, KB_padEnter}, + {74, KB_padMinus}, + {78, KB_padPlus}, + {55, KB_padTimes}, + {98, KB_padDivide}, + {71, KB_padHome}, + {72, KB_padUp}, + {73, KB_padPageUp}, + {75, KB_padLeft}, + {76, KB_padCenter}, + {77, KB_padRight}, + {79, KB_padEnd}, + {80, KB_padDown}, + {81, KB_padPageDown}, + {82, KB_padInsert}, + {83, KB_padDelete}, + {105,KB_left}, + {108,KB_down}, + {106,KB_right}, + {103,KB_up}, + {110,KB_insert}, + {102,KB_home}, + {104,KB_pageUp}, + {111,KB_delete}, + {107,KB_end}, + {109,KB_pageDown}, + {125,KB_leftWindows}, + {126,KB_rightWindows}, + {127,KB_menu}, + {100,KB_rightAlt}, + {97,KB_rightCtrl}, + }; + +/* And the keypad with num lock turned on (changes the ASCII code only) */ + +keymap keypad[] = { + {71, ASCII_7}, + {72, ASCII_8}, + {73, ASCII_9}, + {75, ASCII_4}, + {76, ASCII_5}, + {77, ASCII_6}, + {79, ASCII_1}, + {80, ASCII_2}, + {81, ASCII_3}, + {82, ASCII_0}, + {83, ASCII_period}, + }; + +#define NB_KEYMAPS (sizeof(keymaps)/sizeof(keymaps[0])) +#define NB_KEYPAD (sizeof(keypad)/sizeof(keypad[0])) + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +REMARKS: +Include generic raw scancode keyboard module. +****************************************************************************/ +#include "common/keyboard.c" + +/* These are not used under QNX */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + struct timespec t; + clock_gettime(CLOCK_REALTIME,&t); + return (t.tv_nsec / 1000000 + t.tv_sec * 1000); +} + +/**************************************************************************** +REMARKS: +Converts a mickey movement value to a pixel adjustment value. +****************************************************************************/ +static int MickeyToPixel( + int mickey) +{ + /* TODO: We can add some code in here to handle 'acceleration' for */ + /* the mouse cursor. For now just use the mickeys. */ + return mickey; +} + +#ifdef __QNXNTO__ +/**************************************************************************** +REMARKS: +Retrieves all events from the mouse/keyboard event queue and stuffs them +into the MGL event queue for further processing. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + int rc1, rc2; + struct _keyboard_packet key; + struct _mouse_packet ms; + static long old_buttons = 0; + uint message = 0, but_stat = 0, mods = 0; + event_t evt; + + while (EVT.count < EVENTQSIZE) { + rc1 = read(kbd_fd, (void *)&key, sizeof(key)); + if (rc1 == -1) { + if (errno == EAGAIN) + rc1 = 0; + else { + perror("getEvents"); + PM_fatalError("Keyboard error"); + } + } + if (rc1 > 0) { + memset(&evt, 0, sizeof(evt)); + if (key.data.modifiers & KEYMOD_SHIFT) + mods |= EVT_LEFTSHIFT; + if (key.data.modifiers & KEYMOD_CTRL) + mods |= EVT_CTRLSTATE; + if (key.data.modifiers & KEYMOD_ALT) + mods |= EVT_ALTSTATE; + + /* Now store the keyboard event data */ + evt.when = TIME_TO_MSEC(key.time); + if (key.data.flags & KEY_SCAN_VALID) + evt.message |= (key.data.key_scan & 0x7F) << 8; + if ((key.data.flags & KEY_SYM_VALID) && + (((key.data.key_sym & 0xff00) == 0xf000 && + (key.data.key_sym & 0xff) < 0x20) || + key.data.key_sym < 0x80)) + evt.message |= (key.data.key_sym & 0xFF); + evt.modifiers = mods; + if (key.data.flags & KEY_DOWN) { + evt.what = EVT_KEYDOWN; + keyUpMsg[evt.message >> 8] = (ushort)evt.message; + } + else if (key.data.flags & KEY_REPEAT) { + evt.message |= 0x10000; + evt.what = EVT_KEYREPEAT; + } + else { + evt.what = EVT_KEYUP; + evt.message = keyUpMsg[evt.message >> 8]; + if (evt.message == 0) + continue; + keyUpMsg[evt.message >> 8] = 0; + } + + /* Now add the new event to the event queue */ + addEvent(&evt); + } + rc2 = read(mouse_fd, (void *)&ms, sizeof (ms)); + if (rc2 == -1) { + if (errno == EAGAIN) + rc2 = 0; + else { + perror("getEvents"); + PM_fatalError("Mouse error"); + } + } + if (rc2 > 0) { + memset(&evt, 0, sizeof(evt)); + ms.hdr.buttons &= + (_POINTER_BUTTON_LEFT | _POINTER_BUTTON_RIGHT); + if (ms.hdr.buttons & _POINTER_BUTTON_LEFT) + but_stat = EVT_LEFTBUT; + if ((ms.hdr.buttons & _POINTER_BUTTON_LEFT) != + (old_buttons & _POINTER_BUTTON_LEFT)) + message = EVT_LEFTBMASK; + if (ms.hdr.buttons & _POINTER_BUTTON_RIGHT) + but_stat |= EVT_RIGHTBUT; + if ((ms.hdr.buttons & _POINTER_BUTTON_RIGHT) != + (old_buttons & _POINTER_BUTTON_RIGHT)) + message |= EVT_RIGHTBMASK; + if (ms.dx || ms.dy) { + ms.dy = -ms.dy; + EVT.mx += MickeyToPixel(ms.dx); + EVT.my += MickeyToPixel(ms.dy); + if (EVT.mx < 0) EVT.mx = 0; + if (EVT.my < 0) EVT.my = 0; + if (EVT.mx > rangeX) EVT.mx = rangeX; + if (EVT.my > rangeY) EVT.my = rangeY; + evt.what = EVT_MOUSEMOVE; + evt.when = TIME_TO_MSEC(ms.hdr.time); + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = ms.dx; + evt.relative_y = ms.dy; + evt.modifiers = but_stat; + addEvent(&evt); + } + evt.what = ms.hdr.buttons < old_buttons ? + EVT_MOUSEUP : EVT_MOUSEDOWN; + evt.when = TIME_TO_MSEC(ms.hdr.time); + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = ms.dx; + evt.relative_y = ms.dy; + evt.modifiers = but_stat; + evt.message = message; + if (ms.hdr.buttons != old_buttons) { + addEvent(&evt); + old_buttons = ms.hdr.buttons; + } + } + if (rc1 + rc2 == 0) + break; + } +} +#else +/**************************************************************************** +REMARKS: +Retrieves all events from the mouse/keyboard event queue and stuffs them +into the MGL event queue for further processing. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + struct mouse_event ev; + int rc; + static long old_buttons = 0; + uint message = 0, but_stat = 0; + event_t evt; + char buf[32]; + int numkeys, i; + + /* Poll keyboard events */ + while ((numkeys = read(_PM_keyboard_fd, buf, sizeof buf)) > 0) { + for (i = 0; i < numkeys; i++) { + processRawScanCode(buf[i]); + } + } + + if (_PM_mouse_ctl == NULL) + return; + + /* Gobble pending mouse events */ + while (EVT.count < EVENTQSIZE) { + rc = mouse_read(_PM_mouse_ctl, &ev, 1, 0, NULL); + if (rc == -1) { + perror("getEvents"); + PM_fatalError("Mouse error (Input terminated?)"); + } + if (rc == 0) + break; + + message = 0, but_stat = 0; + memset(&evt, 0, sizeof(evt)); + + ev.buttons &= (_MOUSE_LEFT | _MOUSE_RIGHT); + if (ev.buttons & _MOUSE_LEFT) + but_stat = EVT_LEFTBUT; + if ((ev.buttons & _MOUSE_LEFT) != (old_buttons & _MOUSE_LEFT)) + message = EVT_LEFTBMASK; + if (ev.buttons & _MOUSE_RIGHT) + but_stat |= EVT_RIGHTBUT; + if ((ev.buttons & _MOUSE_RIGHT) != (old_buttons & _MOUSE_RIGHT)) + message |= EVT_RIGHTBMASK; + if (ev.dx || ev.dy) { + ev.dy = -ev.dy; + EVT.mx += MickeyToPixel(ev.dx); + EVT.my += MickeyToPixel(ev.dy); + if (EVT.mx < 0) EVT.mx = 0; + if (EVT.my < 0) EVT.my = 0; + if (EVT.mx > rangeX) EVT.mx = rangeX; + if (EVT.my > rangeY) EVT.my = rangeY; + evt.what = EVT_MOUSEMOVE; + evt.when = ev.timestamp*100; + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = ev.dx; + evt.relative_y = ev.dy; + evt.modifiers = but_stat; + addEvent(&evt); + } + evt.what = ev.buttons < old_buttons ? EVT_MOUSEUP : EVT_MOUSEDOWN; + evt.when = ev.timestamp*100; + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = ev.dx; + evt.relative_y = ev.dy; + evt.modifiers = but_stat; + evt.message = message; + if (ev.buttons != old_buttons) { + addEvent(&evt); + old_buttons = ev.buttons; + } + } +} +#endif /* __QNXNTO__ */ + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort( + int signo) +{ + char buf[80]; + + EVT_exit(); + sprintf(buf,"Terminating on signal %d",signo); + PM_fatalError(buf); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + struct stat st; + char *iarg[16]; +#ifdef __QNXNTO__ + char buf[128]; + FILE *p; + int argno,len; +#endif + +#ifdef __QNXNTO__ + ThreadCtl(_NTO_TCTL_IO, 0); /* So joystick code won't blow up */ +#endif + + /* Initialise the event queue */ + EVT.mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + +#ifdef __QNXNTO__ + /* + * User may already have input running with the right parameters. + * Thus they could start input at boot time, using the output of + * inputtrap, passing the the -r flag to make it run as a resource + * manager. + */ + if ((mouse_fd = open("/dev/mouse0", O_RDONLY | O_NONBLOCK)) < 0) { + /* Run inputtrap to get the args for input */ + if ((p = popen("inputtrap", "r")) == NULL) + PM_fatalError("Error running 'inputtrap'"); + fgets(buf, sizeof(buf), p); + pclose(p); + + /* Build the argument list */ + len = strlen(buf); + iarg[0] = buf; + for (i = 0, argno = 0; i < len && argno < 15;) { + if (argno == 1) { + /* + * Add flags to input's arg list. + * '-r' means run as resource + * manager, providing the /dev/mouse + * and /dev/keyboard interfaces. + * '-P' supresses the /dev/photon + * mechanism. + */ + iarg[argno++] = "-Pr"; + continue; + } + while (buf[i] == ' ') + i++; + if (buf[i] == '\0' || buf[i] == '\n') + break; + iarg[argno++] = &buf[i]; + while (buf[i] != ' ' + && buf[i] != '\0' && buf[i] != '\n') + i++; + buf[i++] = '\0'; + } + iarg[argno] = NULL; + + if ((kill_pid = spawnvp(P_NOWAITO, iarg[0], iarg)) == -1) { + perror("spawning input resmgr"); + PM_fatalError("Could not start input resmgr"); + } + for (i = 0; i < 10; i++) { + if (stat("/dev/mouse0", &st) == 0) + break; + sleep(1); + } + if ((mouse_fd = open("/dev/mouse0", O_RDONLY|O_NONBLOCK)) < 0) { + perror("/dev/mouse0"); + PM_fatalError("Could not open /dev/mouse0"); + } + } + if ((kbd_fd = open("/dev/keyboard0", O_RDONLY|O_NONBLOCK)) < 0) { + perror("/dev/keyboard0"); + PM_fatalError("Could not open /dev/keyboard0"); + } +#else + /* Connect to Input/Mouse for event handling */ + if (_PM_mouse_ctl == NULL) { + _PM_mouse_ctl = mouse_open(0, "/dev/mouse", 0); + + /* "Mouse" is not running; attempt to start it */ + if (_PM_mouse_ctl == NULL) { + iarg[0] = "mousetrap"; + iarg[1] = "start"; + iarg[2] = NULL; + if ((kill_pid = spawnvp(P_NOWAITO, iarg[0], (void*)iarg)) == -1) + perror("spawn (mousetrap)"); + else { + for (i = 0; i < 10; i++) { + if (stat("/dev/mouse", &st) == 0) + break; + sleep(1); + } + _PM_mouse_ctl = mouse_open(0, "/dev/mouse", 0); + } + } + } + if (_PM_keyboard_fd == -1) + _PM_keyboard_fd = open("/dev/kbd", O_RDONLY|O_NONBLOCK); +#endif + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +#define _EVT_setMousePos(x,y) + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for QNX */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for QNX */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ +#ifdef __QNXNTO__ + char c; + int flags; + + if (kbd_fd != -1) { + close(kbd_fd); + kbd_fd = -1; + } + if (mouse_fd != -1) { + close(mouse_fd); + mouse_fd = -1; + } +#endif + + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + +#ifndef __QNXNTO__ + /* Kill the Input/Mouse driver if we have spawned it */ + if (_PM_mouse_ctl != NULL) { + struct _fd_entry fde; + uint pid = 0; + + /* Find out the pid of the mouse driver */ + if (kill_pid > 0) { + if (qnx_fd_query(0, + 0, _PM_mouse_ctl->fd, &fde) != -1) + pid = fde.pid; + } + mouse_close(_PM_mouse_ctl); + _PM_mouse_ctl = NULL; + + if (pid > 0) { + /* For some reasons the PID's are different under QNX4, + * so we use the old mechanism to kill the mouse server. + */ + kill(pid, SIGTERM); + kill_pid = 0; + } + } +#endif + if (kill_pid > 0) { + kill(kill_pid, SIGTERM); + kill_pid = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c new file mode 100644 index 0000000..f960c75 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c @@ -0,0 +1,182 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: MTRR helper functions module. To make it easier to implement +* the MTRR support under QNX, we simply put our ring 0 helper +* functions into stubs that run them at ring 0 using whatever +* mechanism is available. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include +#include +#ifdef __QNXNTO__ +#include +#include +#else +#include +#include +#endif + +/*--------------------------- Global variables ----------------------------*/ + +#define R0_FLUSH_TLB 0 +#define R0_SAVE_CR4 1 +#define R0_RESTORE_CR4 2 +#define R0_READ_MSR 3 +#define R0_WRITE_MSR 4 + +typedef struct { + int service; + int reg; + ulong eax; + ulong edx; + } R0_data; + +extern volatile R0_data _PM_R0; + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef __QNXNTO__ +const struct sigevent * _ASMAPI _PM_ring0_isr(void *arg, int id); +#else +pid_t far _ASMAPI _PM_ring0_isr(); +#endif + +/**************************************************************************** +REMARKS: +Return true if ring 0 (or if we can call the helpers functions at ring 0) +****************************************************************************/ +ibool _ASMAPI _MTRR_isRing0(void) +{ +#ifdef __QNXNTO__ + return false; /* Not implemented yet! */ +#else + return true; +#endif +} + +/**************************************************************************** +REMARKS: +Function to execute a service at ring 0. This is done using the clock +interrupt handler since the code we attach to it will always run at ring 0. +****************************************************************************/ +static void CallRing0(void) +{ +#ifdef __QNXNTO__ + uint clock_intno = SYSPAGE_ENTRY(qtime)->intr; +#else + uint clock_intno = 0; /* clock irq */ +#endif + int intrid; + +#ifdef __QNXNTO__ + mlock((void*)&_PM_R0, sizeof(_PM_R0)); + ThreadCtl(_NTO_TCTL_IO, 0); +#endif +#ifdef __QNXNTO__ + if ((intrid = InterruptAttach(_NTO_INTR_CLASS_EXTERNAL | clock_intno, + _PM_ring0_isr, (void*)&_PM_R0, sizeof(_PM_R0), _NTO_INTR_FLAGS_END)) == -1) { +#else + if ((intrid = qnx_hint_attach(clock_intno, _PM_ring0_isr, FP_SEG(&_PM_R0))) == -1) { +#endif + perror("Attach"); + exit(-1); + } + while (_PM_R0.service != -1) + ; +#ifdef __QNXNTO__ + InterruptDetachId(intrid); +#else + qnx_hint_detach(intrid); +#endif +} + +/**************************************************************************** +REMARKS: +Flush the translation lookaside buffer. +****************************************************************************/ +void PMAPI PM_flushTLB(void) +{ + _PM_R0.service = R0_FLUSH_TLB; + CallRing0(); +} + +/**************************************************************************** +REMARKS: +Read and return the value of the CR4 register +****************************************************************************/ +ulong _ASMAPI _MTRR_saveCR4(void) +{ + _PM_R0.service = R0_SAVE_CR4; + CallRing0(); + return _PM_R0.reg; +} + +/**************************************************************************** +REMARKS: +Restore the value of the CR4 register +****************************************************************************/ +void _ASMAPI _MTRR_restoreCR4(ulong cr4Val) +{ + _PM_R0.service = R0_RESTORE_CR4; + _PM_R0.reg = cr4Val; + CallRing0(); +} + +/**************************************************************************** +REMARKS: +Read a machine status register for the CPU. +****************************************************************************/ +void _ASMAPI _MTRR_readMSR( + int reg, + ulong *eax, + ulong *edx) +{ + _PM_R0.service = R0_READ_MSR; + _PM_R0.reg = reg; + CallRing0(); + *eax = _PM_R0.eax; + *edx = _PM_R0.edx; +} + +/**************************************************************************** +REMARKS: +Write a machine status register for the CPU. +****************************************************************************/ +void _ASMAPI _MTRR_writeMSR( + int reg, + ulong eax, + ulong edx) +{ + _PM_R0.service = R0_WRITE_MSR; + _PM_R0.reg = reg; + _PM_R0.eax = eax; + _PM_R0.edx = edx; + CallRing0(); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h new file mode 100644 index 0000000..0961193 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h @@ -0,0 +1,103 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#include +#include +#include +#include +#ifndef __QNXNTO__ +#include +#include +#include +#include +#else +#include + +/* Things 'borrowed' from photon/keycodes.h */ + +/* + * Keyboard modifiers + */ +#define KEYMODBIT_SHIFT 0 +#define KEYMODBIT_CTRL 1 +#define KEYMODBIT_ALT 2 +#define KEYMODBIT_ALTGR 3 +#define KEYMODBIT_SHL3 4 +#define KEYMODBIT_MOD6 5 +#define KEYMODBIT_MOD7 6 +#define KEYMODBIT_MOD8 7 + +#define KEYMODBIT_SHIFT_LOCK 8 +#define KEYMODBIT_CTRL_LOCK 9 +#define KEYMODBIT_ALT_LOCK 10 +#define KEYMODBIT_ALTGR_LOCK 11 +#define KEYMODBIT_SHL3_LOCK 12 +#define KEYMODBIT_MOD6_LOCK 13 +#define KEYMODBIT_MOD7_LOCK 14 +#define KEYMODBIT_MOD8_LOCK 15 + +#define KEYMODBIT_CAPS_LOCK 16 +#define KEYMODBIT_NUM_LOCK 17 +#define KEYMODBIT_SCROLL_LOCK 18 + +#define KEYMOD_SHIFT (1 << KEYMODBIT_SHIFT) +#define KEYMOD_CTRL (1 << KEYMODBIT_CTRL) +#define KEYMOD_ALT (1 << KEYMODBIT_ALT) +#define KEYMOD_ALTGR (1 << KEYMODBIT_ALTGR) +#define KEYMOD_SHL3 (1 << KEYMODBIT_SHL3) +#define KEYMOD_MOD6 (1 << KEYMODBIT_MOD6) +#define KEYMOD_MOD7 (1 << KEYMODBIT_MOD7) +#define KEYMOD_MOD8 (1 << KEYMODBIT_MOD8) + +#define KEYMOD_SHIFT_LOCK (1 << KEYMODBIT_SHIFT_LOCK) +#define KEYMOD_CTRL_LOCK (1 << KEYMODBIT_CTRL_LOCK) +#define KEYMOD_ALT_LOCK (1 << KEYMODBIT_ALT_LOCK) +#define KEYMOD_ALTGR_LOCK (1 << KEYMODBIT_ALTGR_LOCK) +#define KEYMOD_SHL3_LOCK (1 << KEYMODBIT_SHL3_LOCK) +#define KEYMOD_MOD6_LOCK (1 << KEYMODBIT_MOD6_LOCK) +#define KEYMOD_MOD7_LOCK (1 << KEYMODBIT_MOD7_LOCK) +#define KEYMOD_MOD8_LOCK (1 << KEYMODBIT_MOD8_LOCK) + +#define KEYMOD_CAPS_LOCK (1 << KEYMODBIT_CAPS_LOCK) +#define KEYMOD_NUM_LOCK (1 << KEYMODBIT_NUM_LOCK) +#define KEYMOD_SCROLL_LOCK (1 << KEYMODBIT_SCROLL_LOCK) + +/* + * Keyboard flags + */ +#define KEY_DOWN 0x00000001 /* Key was pressed down */ +#define KEY_REPEAT 0x00000002 /* Key was repeated */ +#define KEY_SCAN_VALID 0x00000020 /* Scancode is valid */ +#define KEY_SYM_VALID 0x00000040 /* Key symbol is valid */ +#define KEY_CAP_VALID 0x00000080 /* Key cap is valid */ +#define KEY_DEAD 0x40000000 /* Key symbol is a DEAD key */ +#define KEY_OEM_CAP 0x80000000 /* Key cap is an OEM scan code from keyboard */ + +#endif /* __QNXNTO__ */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c new file mode 100644 index 0000000..c993ee0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c @@ -0,0 +1,891 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "mtrr.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qnx/vbios.h" +#ifndef __QNXNTO__ +#include +#include +#include +#include +#else +#include +#include +#endif + +/*--------------------------- Global variables ----------------------------*/ + +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +static VBIOSregs_t *VRegs = NULL; /* Pointer to VBIOS registers */ +static int raw_count = 0; +static struct _console_ctrl *cc = NULL; +static int console_count = 0; +static int rmbuf_inuse = 0; + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +void PMAPI PM_init(void) +{ + char *force; + + if (VRegs == NULL) { +#ifdef __QNXNTO__ + ThreadCtl(_NTO_TCTL_IO, 0); /* Get IO privilidge */ +#endif + force = getenv("VBIOS_METHOD"); + VRegs = VBIOSinit(force ? atoi(force) : 0); + } +#ifndef __QNXNTO__ + MTRR_init(); +#endif +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return VRegs != NULL; } + +long PMAPI PM_getOSType(void) +{ return _OS_QNX; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '/') { + s[pos] = '/'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + exit(1); +} + +static void ExitVBEBuf(void) +{ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +static int term_raw(void) +{ + struct termios termios_p; + + if (raw_count++ > 0) + return 0; + + /* Go into "raw" input mode */ + if (tcgetattr(STDIN_FILENO, &termios_p)) + return -1; + + termios_p.c_cc[VMIN] = 1; + termios_p.c_cc[VTIME] = 0; + termios_p.c_lflag &= ~( ECHO|ICANON|ISIG|ECHOE|ECHOK|ECHONL); + tcsetattr(STDIN_FILENO, TCSADRAIN, &termios_p); + return 0; +} + +static void term_restore(void) +{ + struct termios termios_p; + + if (raw_count-- != 1) + return; + + tcgetattr(STDIN_FILENO, &termios_p); + termios_p.c_lflag |= (ECHO|ICANON|ISIG|ECHOE|ECHOK|ECHONL); + termios_p.c_oflag |= (OPOST); + tcsetattr(STDIN_FILENO, TCSADRAIN, &termios_p); +} + +int PMAPI PM_kbhit(void) +{ + int blocking, c; + + if (term_raw() == -1) + return 0; + + /* Go into non blocking mode */ + blocking = fcntl(STDIN_FILENO, F_GETFL) | O_NONBLOCK; + fcntl(STDIN_FILENO, F_SETFL, blocking); + c = getc(stdin); + + /* restore blocking mode */ + fcntl(STDIN_FILENO, F_SETFL, blocking & ~O_NONBLOCK); + term_restore(); + if (c != EOF) { + ungetc(c, stdin); + return c; + } + clearerr(stdin); + return 0; +} + +int PMAPI PM_getch(void) +{ + int c; + + if (term_raw() == -1) + return (0); + c = getc(stdin); +#if defined(__QNX__) && !defined(__QNXNTO__) + if (c == 0xA) + c = 0x0D; + else if (c == 0x7F) + c = 0x08; +#endif + term_restore(); + return c; +} + +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ +#ifndef __QNXNTO__ + int fd; + + if (console_count++) + return 0; + if ((fd = open("/dev/con1", O_RDWR)) == -1) + return -1; + cc = console_open(fd, O_RDWR); + close(fd); + if (cc == NULL) + return -1; +#endif + return 1; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + return PM_getVGAStateSize() + sizeof(int) * 3; +} + +void PMAPI PM_saveConsoleState(void *stateBuf,int console_id) +{ +#ifdef __QNXNTO__ + int fd; + int flags; + + if ((fd = open("/dev/con1", O_RDWR)) == -1) + return; + flags = _CONCTL_INVISIBLE_CHG | _CONCTL_INVISIBLE; + devctl(fd, DCMD_CHR_SERCTL, &flags, sizeof flags, 0); + close(fd); +#else + uchar *buf = &((uchar*)stateBuf)[PM_getVGAStateSize()]; + + /* Save QNX 4 console state */ + console_read(cc, -1, 0, NULL, 0, + (int *)buf+1, (int *)buf+2, NULL); + *(int *)buf = console_ctrl(cc, -1, + CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE, + CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE); + + /* Save state of VGA registers */ + PM_saveVGAState(stateBuf); +#endif +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* TODO: Implement support for console switching if possible */ +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) +{ +#ifdef __QNXNTO__ + int fd; + int flags; + + if ((fd = open("/dev/con1", O_RDWR)) == -1) + return; + flags = _CONCTL_INVISIBLE_CHG; + devctl(fd, DCMD_CHR_SERCTL, &flags, sizeof flags, 0); + close(fd); +#else + uchar *buf = &((uchar*)stateBuf)[PM_getVGAStateSize()]; + + /* Restore the state of the VGA compatible registers */ + PM_restoreVGAState(stateBuf); + + /* Restore QNX 4 console state */ + console_ctrl(cc, -1, *(int *)buf, + CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE); + console_write(cc, -1, 0, NULL, 0, + (int *)buf+1, (int *)buf+2, NULL); +#endif +} + +void PMAPI PM_closeConsole(PM_HWND hwndConsole) +{ +#ifndef __QNXNTO__ + if (--console_count == 0) { + console_close(cc); + cc = NULL; + } +#endif +} + +void PM_setOSCursorLocation(int x,int y) +{ + if (!cc) + return; +#ifndef __QNXNTO__ + console_write(cc, -1, 0, NULL, 0, &y, &x, NULL); +#endif +} + +void PM_setOSScreenWidth(int width,int height) +{ +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency) +{ + /* TODO: Implement this for QNX */ + return false; +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + /* TODO: Implement this for QNX */ +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Implement this for QNX */ +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return '/'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return PM_getNucleusConfigPath(); } + +const char * PMAPI PM_getNucleusPath(void) +{ + char *env = getenv("NUCLEUS_PATH"); +#ifdef __QNXNTO__ +#ifdef __X86__ + return env ? env : "/nto/scitech/x86/bin"; +#elif defined (__PPC__) + return env ? env : "/nto/scitech/ppcbe/bin"; +#elif defined (__MIPS__) +#ifdef __BIGENDIAN__ + return env ? env : "/nto/scitech/mipsbe/bin"; +#else + return env ? env : "/nto/scitech/mipsle/bin"; +#endif +#elif defined (__SH__) +#ifdef __BIGENDIAN__ + return env ? env : "/nto/scitech/shbe/bin"; +#else + return env ? env : "/nto/scitech/shle/bin"; +#endif +#elif defined (__ARM__) + return env ? env : "/nto/scitech/armle/bin"; +#endif +#else /* QNX 4 */ + return env ? env : "/qnx4/scitech/bin"; +#endif +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[512]; + char *env; +#ifdef __QNXNTO__ + char temp[64]; + gethostname(temp, sizeof (temp)); + temp[sizeof (temp) - 1] = '\0'; /* Paranoid */ + sprintf(path,"/etc/config/scitech/%s/config", temp); +#else + sprintf(path,"/etc/config/scitech/%d/config", getnid()); +#endif + if ((env = getenv("NUCLEUS_PATH")) != NULL) { + strcpy(path,env); + PM_backslash(path); + strcat(path,"config"); + } + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ + static char buf[128]; +#ifdef __QNXNTO__ + gethostname(buf, sizeof (buf)); +#else + sprintf(buf,"node%d", getnid()); +#endif + return buf; +} + +const char * PMAPI PM_getMachineName(void) +{ + static char buf[128]; +#ifdef __QNXNTO__ + gethostname(buf, sizeof (buf)); +#else + sprintf(buf,"node%d", getnid()); +#endif + return buf; +} + +void * PMAPI PM_getBIOSPointer(void) +{ + return PM_mapRealPointer(0, 0x400); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + static void *ptr = NULL; + void *freeptr; + unsigned offset, i, maplen; + + if (ptr != NULL) + return ptr; + + /* Some trickery is required to get the linear address 64K aligned */ + for (i = 0; i < 5; i++) { + ptr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + offset = 0x10000 - ((unsigned)ptr % 0x10000); + if (!offset) + break; + munmap(ptr, 0x10000); + maplen = 0x10000 + offset; + freeptr = PM_mapPhysicalAddr(0xA0000-offset, maplen-1,true); + ptr = (void *)(offset + (unsigned)freeptr); + if (0x10000 - ((unsigned)ptr % 0x10000)) + break; + munmap(freeptr, maplen); + } + if (i == 5) { + printf("Could not get a 64K aligned linear address for A0000 region\n"); + exit(1); + } + return ptr; +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + uchar_t *p; + unsigned o; + unsigned prot = PROT_READ|PROT_WRITE|(isCached?0:PROT_NOCACHE); +#ifdef __PAGESIZE + int pagesize = __PAGESIZE; +#else + int pagesize = 4096; +#endif + int rounddown = base % pagesize; +#ifndef __QNXNTO__ + static int __VidFD = -1; +#endif + + if (rounddown) { + if (base < rounddown) + return NULL; + base -= rounddown; + limit += rounddown; + } + +#ifndef __QNXNTO__ + if (__VidFD < 0) { + if ((__VidFD = shm_open( "Physical", O_RDWR, 0777 )) == -1) { + perror( "Cannot open Physical memory" ); + exit(1); + } + } + o = base & 0xFFF; + limit = (limit + o + 0xFFF) & ~0xFFF; + if ((int)(p = mmap( 0, limit, prot, MAP_SHARED, + __VidFD, base )) == -1 ) { + return NULL; + } + p += o; +#else + if ((p = mmap(0, limit, prot, MAP_PHYS | MAP_SHARED, + NOFD, base)) == MAP_FAILED) { + return (void *)-1; + } +#endif + return (p + rounddown); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + munmap(ptr,limit+1); +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + /* TODO: Implement this! */ + return false; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* TODO: Put the process to sleep for milliseconds */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +void * PMAPI PM_mallocShared(long size) +{ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + PM_free(ptr); +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + void *p; + + PM_init(); + + if ((p = VBIOSgetmemptr(r_seg, r_off, VRegs)) == (void *)-1) + return NULL; + return p; +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + if (size > 1024) { + printf("PM_allocRealSeg: can't handle %d bytes\n", size); + return 0; + } + if (rmbuf_inuse != 0) { + printf("PM_allocRealSeg: transfer area already in use\n"); + return 0; + } + PM_init(); + rmbuf_inuse = 1; + *r_seg = VBIOS_TransBufVSeg(VRegs); + *r_off = VBIOS_TransBufVOff(VRegs); + return (void*)VBIOS_TransBufPtr(VRegs); +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + if (rmbuf_inuse == 0) { + printf("PM_freeRealSeg: nothing was allocated\n"); + return; + } + rmbuf_inuse = 0; +} + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = regs->eax; + VRegs->l.ebx = regs->ebx; + VRegs->l.ecx = regs->ecx; + VRegs->l.edx = regs->edx; + VRegs->l.esi = regs->esi; + VRegs->l.edi = regs->edi; + + VBIOSint(intno, VRegs, 1024); + + regs->eax = VRegs->l.eax; + regs->ebx = VRegs->l.ebx; + regs->ecx = VRegs->l.ecx; + regs->edx = VRegs->l.edx; + regs->esi = VRegs->l.esi; + regs->edi = VRegs->l.edi; + regs->flags = VRegs->w.flags & 0x1; +} + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + PM_init(); + if (VRegs == NULL) + return 0; + + VRegs->l.eax = in->e.eax; + VRegs->l.ebx = in->e.ebx; + VRegs->l.ecx = in->e.ecx; + VRegs->l.edx = in->e.edx; + VRegs->l.esi = in->e.esi; + VRegs->l.edi = in->e.edi; + + VBIOSint(intno, VRegs, 1024); + + out->e.eax = VRegs->l.eax; + out->e.ebx = VRegs->l.ebx; + out->e.ecx = VRegs->l.ecx; + out->e.edx = VRegs->l.edx; + out->e.esi = VRegs->l.esi; + out->e.edi = VRegs->l.edi; + out->x.cflag = VRegs->w.flags & 0x1; + + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + PM_init(); + if (VRegs == NULL) + return 0; + + if (intno == 0x21) { + time_t today = time(NULL); + struct tm *t; + t = localtime(&today); + out->x.cx = t->tm_year + 1900; + out->h.dh = t->tm_mon + 1; + out->h.dl = t->tm_mday; + return 0; + } + else { + VRegs->l.eax = in->e.eax; + VRegs->l.ebx = in->e.ebx; + VRegs->l.ecx = in->e.ecx; + VRegs->l.edx = in->e.edx; + VRegs->l.esi = in->e.esi; + VRegs->l.edi = in->e.edi; + VRegs->w.es = sregs->es; + VRegs->w.ds = sregs->ds; + + VBIOSint(intno, VRegs, 1024); + + out->e.eax = VRegs->l.eax; + out->e.ebx = VRegs->l.ebx; + out->e.ecx = VRegs->l.ecx; + out->e.edx = VRegs->l.edx; + out->e.esi = VRegs->l.esi; + out->e.edi = VRegs->l.edi; + out->x.cflag = VRegs->w.flags & 0x1; + sregs->es = VRegs->w.es; + sregs->ds = VRegs->w.ds; + + return out->x.ax; + } +} + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = in->e.eax; + VRegs->l.ebx = in->e.ebx; + VRegs->l.ecx = in->e.ecx; + VRegs->l.edx = in->e.edx; + VRegs->l.esi = in->e.esi; + VRegs->l.edi = in->e.edi; + VRegs->w.es = sregs->es; + VRegs->w.ds = sregs->ds; + + VBIOScall(seg, off, VRegs, 1024); + + in->e.eax = VRegs->l.eax; + in->e.ebx = VRegs->l.ebx; + in->e.ecx = VRegs->l.ecx; + in->e.edx = VRegs->l.edx; + in->e.esi = VRegs->l.esi; + in->e.edi = VRegs->l.edi; + in->x.cflag = VRegs->w.flags & 0x1; + sregs->es = VRegs->w.es; + sregs->ds = VRegs->w.ds; +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ +#ifndef __QNXNTO__ + *physical = *total = _memavl(); +#endif +} + +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + /* TODO: Implement this on QNX */ + return NULL; +} + +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + /* TODO: Implement this on QNX */ +} + +void * PMAPI PM_allocPage( + ibool locked) +{ + /* TODO: Implement this on QNX */ + return NULL; +} + +void PMAPI PM_freePage( + void *p) +{ + /* TODO: Implement this on QNX */ +} + +void PMAPI PM_setBankA(int bank) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = 0x4F05; + VRegs->l.ebx = 0x0000; + VRegs->l.edx = bank; + VBIOSint(0x10, VRegs, 1024); +} + +void PMAPI PM_setBankAB(int bank) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = 0x4F05; + VRegs->l.ebx = 0x0000; + VRegs->l.edx = bank; + VBIOSint(0x10, VRegs, 1024); + + VRegs->l.eax = 0x4F05; + VRegs->l.ebx = 0x0001; + VRegs->l.edx = bank; + VBIOSint(0x10, VRegs, 1024); +} + +void PMAPI PM_setCRTStart(int x,int y,int waitVRT) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = 0x4F07; + VRegs->l.ebx = waitVRT; + VRegs->l.ecx = x; + VRegs->l.edx = y; + VBIOSint(0x10, VRegs, 1024); +} + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *copyOfBIOS, + ulong BIOSLen) +{ + (void)axVal; + (void)BIOSPhysAddr; + (void)copyOfBIOS; + (void)BIOSLen; + return false; +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: Implement this to load shared libraries! */ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: Implement this! */ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: Implement this! */ + (void)hModule; +} + +int PMAPI PM_setIOPL( + int level) +{ + /* QNX handles IOPL selection at the program link level. */ + return level; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ +#ifndef __QNXNTO__ + return MTRR_enableWriteCombine(base,size,type); +#else + return PM_MTRR_NOT_SUPPORTED; +#endif +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c new file mode 100644 index 0000000..579ef2c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c new file mode 100644 index 0000000..d274097 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c @@ -0,0 +1,91 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: QNX specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +} + +/**************************************************************************** +REMARKS: +Use the gettimeofday() function to get microsecond precision (probably less +though) +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + struct timespec ts; + clock_gettime(CLOCK_REALTIME, &ts); + return (ts.tv_nsec / 1000 + ts.tv_sec * 1000000); +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +#define __LZTimerOn(tm) tm->start.low = __ULZReadTime() + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +#define __LZTimerLap(tm) (__ULZReadTime() - tm->start.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) tm->end.low = __ULZReadTime() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerCount(tm) (tm->end.low - tm->start.low) + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c new file mode 100644 index 0000000..4f32c3e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c @@ -0,0 +1,94 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Module to implement OS specific services to measure the +* CPU frequency. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ibool havePerformanceCounter; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Increase the thread priority to maximum, if possible. +****************************************************************************/ +static int SetMaxThreadPriority(void) +{ + int oldPriority; + HANDLE hThread = GetCurrentThread(); + + oldPriority = GetThreadPriority(hThread); + if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) + SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL); + return oldPriority; +} + +/**************************************************************************** +REMARKS: +Restore the original thread priority. +****************************************************************************/ +static void RestoreThreadPriority( + int oldPriority) +{ + HANDLE hThread = GetCurrentThread(); + + if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) + SetThreadPriority(hThread, oldPriority); +} + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + if (!QueryPerformanceFrequency((LARGE_INTEGER*)freq)) { + havePerformanceCounter = false; + freq->low = 100000; + freq->high = 0; + } + else + havePerformanceCounter = true; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + if (havePerformanceCounter) \ + QueryPerformanceCounter((LARGE_INTEGER*)t); \ + else { \ + (t)->low = timeGetTime() * 100; \ + (t)->high = 0; \ + } \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c new file mode 100644 index 0000000..962a14a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c @@ -0,0 +1,287 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Win32 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0}; /* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under Win32 */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ return timeGetTime(); } + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from Win32 into our event queue. +****************************************************************************/ +void _EVT_pumpMessages(void) +{ + MSG msg; + MSG charMsg; + event_t evt; + + while (PeekMessage(&msg,NULL,0,0,PM_REMOVE)) { + memset(&evt,0,sizeof(evt)); + switch (msg.message) { + case WM_MOUSEMOVE: + evt.what = EVT_MOUSEMOVE; + break; + case WM_LBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_LEFTBMASK | EVT_DBLCLICK; + break; + case WM_LBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_LEFTBMASK; + break; + case WM_LBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_LEFTBMASK; + break; + case WM_RBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK; + evt.message = EVT_RIGHTBMASK; + break; + case WM_RBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_RIGHTBMASK; + break; + case WM_RBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_RIGHTBMASK; + break; + case WM_KEYDOWN: + case WM_SYSKEYDOWN: + if (HIWORD(msg.lParam) & KF_REPEAT) { + evt.what = EVT_KEYREPEAT; + } + else { + evt.what = EVT_KEYDOWN; + } + break; + case WM_KEYUP: + case WM_SYSKEYUP: + evt.what = EVT_KEYUP; + break; + } + + /* Convert mouse event modifier flags */ + if (evt.what & EVT_MOUSEEVT) { + evt.where_x = msg.pt.x; + evt.where_y = msg.pt.y; + if (evt.what == EVT_MOUSEMOVE) { + if (oldMove != -1) { + evtq[oldMove].where_x = evt.where_x;/* Modify existing one */ + evtq[oldMove].where_y = evt.where_y; + evt.what = 0; + } + else { + oldMove = freeHead; /* Save id of this move event */ + } + } + else + oldMove = -1; + if (msg.wParam & MK_LBUTTON) + evt.modifiers |= EVT_LEFTBUT; + if (msg.wParam & MK_RBUTTON) + evt.modifiers |= EVT_RIGHTBUT; + if (msg.wParam & MK_SHIFT) + evt.modifiers |= EVT_SHIFTKEY; + if (msg.wParam & MK_CONTROL) + evt.modifiers |= EVT_CTRLSTATE; + } + + /* Convert keyboard codes */ + TranslateMessage(&msg); + if (evt.what & EVT_KEYEVT) { + int scanCode = (msg.lParam >> 16) & 0xFF; + if (evt.what == EVT_KEYUP) { + /* Get message for keyup code from table of cached down values */ + evt.message = keyUpMsg[scanCode]; + keyUpMsg[scanCode] = 0; + } + else { + if (PeekMessage(&charMsg,NULL,WM_CHAR,WM_CHAR,PM_REMOVE)) + evt.message = charMsg.wParam; + if (PeekMessage(&charMsg,NULL,WM_SYSCHAR,WM_SYSCHAR,PM_REMOVE)) + evt.message = charMsg.wParam; + evt.message |= ((msg.lParam >> 8) & 0xFF00); + keyUpMsg[scanCode] = (ushort)evt.message; + } + if (evt.what == EVT_KEYREPEAT) + evt.message |= (msg.lParam << 16); + if (HIWORD(msg.lParam) & KF_ALTDOWN) + evt.modifiers |= EVT_ALTSTATE; + if (GetKeyState(VK_SHIFT) & 0x8000U) + evt.modifiers |= EVT_SHIFTKEY; + if (GetKeyState(VK_CONTROL) & 0x8000U) + evt.modifiers |= EVT_CTRLSTATE; + oldMove = -1; + } + + if (evt.what != 0) { + /* Add time stamp and add the event to the queue */ + evt.when = msg.time; + if (count < EVENTQSIZE) { + addEvent(&evt); + } + } + DispatchMessage(&msg); + } +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +void _EVT_setMousePos( + int *x, + int *y) +{ + SetCursorPos(*x,*y); +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for Win32 */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for Win32 */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h new file mode 100644 index 0000000..1352dad --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h @@ -0,0 +1,34 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#include diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c new file mode 100644 index 0000000..47d7ed6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c @@ -0,0 +1,701 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include +#include +#include +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#include +#ifdef __BORLANDC__ +#pragma warn -par +#endif + +/*--------------------------- Global variables ----------------------------*/ + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +void MTRR_init(void); + +/**************************************************************************** +REMARKS: +Initialise the PM library. +****************************************************************************/ +void PMAPI PM_init(void) +{ + /* TODO: dO any special init code in here. */ + MTRR_init(); +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + return _OS_RTTARGET; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier. +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ + return PM_386; +} + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash( + char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Report a fatal error condition and halt the program. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + /* TODO: Display a fatal error message and exit! */ +/* MessageBox(NULL,msg,"Fatal Error!", MB_ICONEXCLAMATION); */ + exit(1); +} + +/**************************************************************************** +REMARKS: +Allocate the real mode VESA transfer buffer for communicating with the BIOS. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + /* No BIOS access for the RTTarget */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + /* TODO: Need to check if a key is waiting on the keyboard queue */ + return true; +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + /* TODO: Need to obtain the next keypress, and block until one is hit */ + return 0xD; +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PM_setOSCursorLocation( + int x, + int y) +{ + /* Nothing to do for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PM_setOSScreenWidth( + int width, + int height) +{ + /* Nothing to do for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + /* Not supported for RTTarget-32 */ + return false; +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + /* Not supported under RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* Not supported under RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + return 'c'; +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files. +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + return "c:\\"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + /* TODO: Point this at the path when the Nucleus drivers will be found */ + return "c:\\nucleus"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + return PM_getMachineName(); +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + /* Not necessary for RTTarget-32 */ + return "Unknown"; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + /* Not used for RTTarget-32 */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + static void *bankPtr; + if (!bankPtr) + bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + return bankPtr; +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + /* TODO: Map a physical memory address to a linear address */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* TODO: Free the physical address mapping */ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + Sleep(milliseconds); +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of (unnamed) shared memory. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + return PM_malloc(size); +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory. +****************************************************************************/ +void PMAPI PM_freeShared( + void *ptr) +{ + PM_free(ptr); +} + +/**************************************************************************** +REMARKS: +Map a linear memory address to the calling process address space. The +address will have been allocated in another process using the +PM_mapPhysicalAddr function. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + return base; +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + /* Not used for RTTarget-32 */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + /* Not used for RTTarget-32 */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + /* Not used for RTTarget-32 */ + return 0; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + /* Not used for RTTarget-32 */ + return 0; +} + +/**************************************************************************** +REMARKS: +Call a real mode far function. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *in, + RMSREGS *sregs) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Return the amount of available memory. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + /* TODO: Figure out how to determine the available memory. Not entirely */ + /* critical so returning 0 is OK. */ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of locked, physical memory for DMA operations. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + /* TODO: Allocate a block of locked, phsyically contigous memory for DMA */ + return 0; +} + +/**************************************************************************** +REMARKS: +Free a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + + ibool contiguous) +{ + /* TODO: Free a locked memory buffer */ +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS) +{ + /* Not used for RTTarget-32 */ + return false; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: Implement this to load shared libraries! */ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: Implement this! */ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: Implement this! */ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +ulong PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + ulong handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + ulong handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + if (drive == 3) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + (void)drive; + getcwd(dir,len); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Set the file attributes for a file */ + (void)filename; + (void)attrib; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return mkdir(filename) == 0; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return rmdir(filename) == 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c new file mode 100644 index 0000000..dd9dfe6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c @@ -0,0 +1,48 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" +#ifdef __BORLANDC__ +#pragma warn -par +#endif + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c new file mode 100644 index 0000000..80c184d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c @@ -0,0 +1,136 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static CPU_largeInteger countFreq; +static ibool havePerformanceCounter; +static ulong start,finish; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +#ifdef NO_ASSEMBLER + havePerformanceCounter = false; +#else + havePerformanceCounter = QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq); +#endif +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOn( + LZTimerObject *tm) +{ + if (havePerformanceCounter) + QueryPerformanceCounter((LARGE_INTEGER*)&tm->start); + else + tm->start.low = timeGetTime(); +} + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger tmLap,tmCount; + + if (havePerformanceCounter) { + QueryPerformanceCounter((LARGE_INTEGER*)&tmLap); + _CPU_diffTime64(&tm->start,&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); + } + else { + tmLap.low = timeGetTime(); + return (tmLap.low - tm->start.low) * 1000L; + } +} + +/**************************************************************************** +REMARKS: +Stop the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOff( + LZTimerObject *tm) +{ + if (havePerformanceCounter) + QueryPerformanceCounter((LARGE_INTEGER*)&tm->end); + else + tm->end.low = timeGetTime(); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time in microseconds between start and end timings. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + + if (havePerformanceCounter) { + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); + } + else + return (tm->end.low - tm->start.low) * 1000L; +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer from the OS +****************************************************************************/ +static ulong __ULZReadTime(void) +{ return timeGetTime(); } + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm new file mode 100644 index 0000000..da62b1f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm @@ -0,0 +1,175 @@ +;**************************************************************************** +;* +;* SciTech Multi-platform Graphics Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler +;* Environment: IBM PC (MS DOS) +;* +;* Description: Assembly language support routines for the event module. +;* +;**************************************************************************** + + ideal + +include "scitech.mac" ; Memory model macros + +ifdef flatmodel + +header _event ; Set up memory model + +begdataseg _event + + cextern _EVT_biosPtr,DPTR + + cpublic _EVT_dataStart + +ifdef USE_NASM +%define KB_HEAD WORD esi+01Ah ; Keyboard buffer head in BIOS data area +%define KB_TAIL WORD esi+01Ch ; Keyboard buffer tail in BIOS data area +%define KB_START WORD esi+080h ; Start of keyboard buffer in BIOS data area +%define KB_END WORD esi+082h ; End of keyboard buffer in BIOS data area +else +KB_HEAD EQU WORD esi+01Ah ; Keyboard buffer head in BIOS data area +KB_TAIL EQU WORD esi+01Ch ; Keyboard buffer tail in BIOS data area +KB_START EQU WORD esi+080h ; Start of keyboard buffer in BIOS data area +KB_END EQU WORD esi+082h ; End of keyboard buffer in BIOS data area +endif + + cpublic _EVT_dataEnd + +enddataseg _event + +begcodeseg _event ; Start of code segment + + cpublic _EVT_codeStart + +;---------------------------------------------------------------------------- +; int _EVT_getKeyCode(void) +;---------------------------------------------------------------------------- +; Returns the key code for the next available key by extracting it from +; the BIOS keyboard buffer. +;---------------------------------------------------------------------------- +cprocstart _EVT_getKeyCode + + enter_c + + mov esi,[_EVT_biosPtr] + xor ebx,ebx + xor eax,eax + mov bx,[KB_HEAD] + cmp bx,[KB_TAIL] + jz @@Done + xor eax,eax + mov ax,[esi+ebx] ; EAX := character from keyboard buffer + inc _bx + inc _bx + cmp bx,[KB_END] ; Hit the end of the keyboard buffer? + jl @@1 + mov bx,[KB_START] +@@1: mov [KB_HEAD],bx ; Update keyboard buffer head pointer + +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _EVT_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _EVT_disableInt + + pushf ; Put flag word on stack + cli ; Disable interrupts! + pop eax ; deposit flag word in return register + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _EVT_restoreInt(int ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _EVT_restoreInt + + ARG ps:UINT + + push ebp + mov ebp,esp ; Set up stack frame + push [DWORD ps] + popf ; Restore processor status (and interrupts) + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; int EVT_rdinx(int port,int index) +;---------------------------------------------------------------------------- +; Reads an indexed register value from an I/O port. +;---------------------------------------------------------------------------- +cprocstart EVT_rdinx + + ARG port:UINT, index:UINT + + push ebp + mov ebp,esp + mov edx,[port] + mov al,[BYTE index] + out dx,al + inc dx + in al,dx + movzx eax,al + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void EVT_wrinx(int port,int index,int value) +;---------------------------------------------------------------------------- +; Writes an indexed register value to an I/O port. +;---------------------------------------------------------------------------- +cprocstart EVT_wrinx + + ARG port:UINT, index:UINT, value:UINT + + push ebp + mov ebp,esp + mov edx,[port] + mov al,[BYTE index] + mov ah,[BYTE value] + out dx,ax + pop ebp + ret + +cprocend + + cpublic _EVT_codeEnd + +endcodeseg _event + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm new file mode 100644 index 0000000..068eea6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm @@ -0,0 +1,58 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM or TASM Assembler +;* Environment: smx 32 bit intel CPU +;* +;* Description: SMX does not support 486's, so this module is not necessary. +;* +;* All registers and all flags are preserved by all routines, except +;* interrupts which are always turned on +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" + +header _lztimer + +begdataseg _lztimer + +enddataseg _lztimer + +begcodeseg _lztimer ; Start of code segment + +cprocstart LZ_disable + cli + ret +cprocend + +cprocstart LZ_enable + sti + ret +cprocend + +endcodeseg _lztimer + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm new file mode 100644 index 0000000..1c7cb21 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm @@ -0,0 +1,448 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit SMX embedded systems development +;* +;* Description: Low level assembly support for the PM library specific to +;* SMX. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pm ; Set up memory model + +begdataseg _pm + + cextern _PM_savedDS,USHORT + +intel_id db "GenuineIntel" ; Intel vendor ID + +enddataseg _pm + +begcodeseg _pm ; Start of code segment + +;---------------------------------------------------------------------------- +; void PM_segread(PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Read the current value of all segment registers +;---------------------------------------------------------------------------- +cprocstartdll16 PM_segread + + ARG sregs:DPTR + + enter_c + + mov ax,es + _les _si,[sregs] + mov [_ES _si],ax + mov [_ES _si+2],cs + mov [_ES _si+4],ss + mov [_ES _si+6],ds + mov [_ES _si+8],fs + mov [_ES _si+10],gs + + leave_c + ret + +cprocend + +; Create a table of the 256 different interrupt calls that we can jump +; into + +ifdef USE_NASM + +%assign intno 0 + +intTable: +%rep 256 + db 0CDh + db intno +%assign intno intno + 1 + ret + nop +%endrep + +else + +intno = 0 + +intTable: + REPT 256 + db 0CDh + db intno +intno = intno + 1 + ret + nop + ENDM + +endif + +;---------------------------------------------------------------------------- +; _PM_genInt - Generate the appropriate interrupt +;---------------------------------------------------------------------------- +cprocnear _PM_genInt + + push _ax ; Save _ax + push _bx ; Save _bx + mov ebx,[UINT esp+12] ; EBX := interrupt number + mov _ax,offset intTable ; Point to interrupt generation table + shl _bx,2 ; _BX := index into table + add _ax,_bx ; _AX := pointer to interrupt code + xchg eax,[esp+4] ; Restore eax, and set for int + pop _bx ; restore _bx + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Issues a software interrupt in protected mode. This routine has been +; written to allow user programs to load CS and DS with different values +; other than the default. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_int386x + + ARG intno:UINT, inptr:DPTR, outptr:DPTR, sregs:DPTR + + LOCAL flags:UINT, sv_ds:UINT, sv_esi:ULONG = LocalSize + + enter_c + push ds + push es ; Save segment registers + push fs + push gs + + _lds _si,[sregs] ; DS:_SI -> Load segment registers + mov es,[_si] + mov bx,[_si+6] + mov [sv_ds],_bx ; Save value of user DS on stack + mov fs,[_si+8] + mov gs,[_si+10] + + _lds _si,[inptr] ; Load CPU registers + mov eax,[_si] + mov ebx,[_si+4] + mov ecx,[_si+8] + mov edx,[_si+12] + mov edi,[_si+20] + mov esi,[_si+16] + + push ds ; Save value of DS + push _bp ; Some interrupts trash this! + clc ; Generate the interrupt + push [UINT intno] + mov ds,[WORD sv_ds] ; Set value of user's DS selector + call _PM_genInt + pop _bp ; Pop intno from stack (flags unchanged) + pop _bp ; Restore value of stack frame pointer + pop ds ; Restore value of DS + + pushf ; Save flags for later + pop [UINT flags] + push esi ; Save ESI for later + pop [DWORD sv_esi] + push ds ; Save DS for later + pop [UINT sv_ds] + + _lds _si,[outptr] ; Save CPU registers + mov [_si],eax + mov [_si+4],ebx + mov [_si+8],ecx + mov [_si+12],edx + push [DWORD sv_esi] + pop [DWORD _si+16] + mov [_si+20],edi + + mov _bx,[flags] ; Return flags + and ebx,1h ; Isolate carry flag + mov [_si+24],ebx ; Save carry flag status + + _lds _si,[sregs] ; Save segment registers + mov [_si],es + mov _bx,[sv_ds] + mov [_si+6],bx ; Get returned DS from stack + mov [_si+8],fs + mov [_si+10],gs + + pop gs ; Restore segment registers + pop fs + pop es + pop ds + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_saveDS(void) +;---------------------------------------------------------------------------- +; Save the value of DS into a section of the code segment, so that we can +; quickly load this value at a later date in the PM_loadDS() routine from +; inside interrupt handlers etc. The method to do this is different +; depending on the DOS extender being used. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_saveDS + + mov [_PM_savedDS],ds ; Store away in data segment + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_loadDS(void) +;---------------------------------------------------------------------------- +; Routine to load the DS register with the default value for the current +; DOS extender. Only the DS register is loaded, not the ES register, so +; if you wish to call C code, you will need to also load the ES register +; in 32 bit protected mode. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_loadDS + + mov ds,[cs:_PM_savedDS] ; We can access the proper DS through CS + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankA(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankA + + ARG bank:UINT + + push ebp + mov ebp,esp + push ebx + mov _bx,0 + mov _ax,4F05h + mov _dx,[bank] + int 10h + pop ebx + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankAB(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankAB + + ARG bank:UINT + + push ebp + mov ebp,esp + push ebx + mov _bx,0 + mov _ax,4F05h + mov _dx,[bank] + int 10h + mov _bx,1 + mov _ax,4F05h + mov _dx,[bank] + int 10h + pop ebx + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setCRTStart(int x,int y,int waitVRT) +;---------------------------------------------------------------------------- +cprocstart PM_setCRTStart + + ARG x:UINT, y:UINT, waitVRT:UINT + + push ebp + mov ebp,esp + push ebx + mov _bx,[waitVRT] + mov _cx,[x] + mov _dx,[y] + mov _ax,4F07h + int 10h + pop ebx + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _PM_inp(int port) +;---------------------------------------------------------------------------- +; Reads a byte from the specified port +;---------------------------------------------------------------------------- +cprocstart _PM_inp + + ARG port:UINT + + push _bp + mov _bp,_sp + xor _ax,_ax + mov _dx,[port] + in al,dx + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_outp(int port,int value) +;---------------------------------------------------------------------------- +; Write a byte to the specified port. +;---------------------------------------------------------------------------- +cprocstart _PM_outp + + ARG port:UINT, value:UINT + + push _bp + mov _bp,_sp + mov _dx,[port] + mov _ax,[value] + out dx,al + pop _bp + ret + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; uchar _PM_readCMOS(int index) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_readCMOS + + ARG index:UINT + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + in al,71h + mov ah,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + sti + mov al,ah ; Return value in AL + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_writeCMOS(int index,uchar value) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_writeCMOS + + ARG index:UINT, value:UCHAR + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + mov al,[value] + out 71h,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + sti + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_getPDB - Return the Page Table Directory Base address +;---------------------------------------------------------------------------- +cprocstart _PM_getPDB + + mov eax,cr3 + and eax,0FFFFF000h + ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_flushTLB - Flush the Translation Lookaside buffer +;---------------------------------------------------------------------------- +cprocstart PM_flushTLB + + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB + ret + +cprocend + +endcodeseg _pm + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm new file mode 100644 index 0000000..8352ce3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm @@ -0,0 +1,933 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit SMX embedded systems development +;* +;* Description: Low level assembly support for the PM library specific to +;* SMX interrupt handling. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmsmx ; Set up memory model + +; Define the size of our local stacks. For real mode code they cant be +; that big, but for 32 bit protected mode code we can make them nice and +; large so that complex C functions can be used. + +MOUSE_STACK EQU 4096 +TIMER_STACK EQU 4096 +KEY_STACK EQU 1024 +INT10_STACK EQU 1024 + +ifdef USE_NASM + +; Macro to load DS and ES registers with correct value. + +%imacro LOAD_DS 0 + mov ds,[cs:_PM_savedDS] + mov es,[cs:_PM_savedDS] +%endmacro + +; Note that interrupts we disable interrupts during the following stack +; %imacro for correct operation, but we do not enable them again. Normally +; these %imacros are used within interrupt handlers so interrupts should +; already be off. We turn them back on explicitly later if the user code +; needs them to be back on. + +; Macro to switch to a new local stack. + +%imacro NEWSTK 1 + cli + mov [seg_%1],ss + mov [ptr_%1],_sp + mov [TempSeg],ds + mov ss,[TempSeg] + mov _sp,offset %1 +%endmacro + +; %imacro to switch back to the old stack. + +%imacro RESTSTK 1 + cli + mov ss,[seg_%1] + mov _sp,[ptr_%1] +%endmacro + +; %imacro to swap the current stack with the one saved away. + +%imacro SWAPSTK 1 + cli + mov ax,ss + xchg ax,[seg_%1] + mov ss,ax + xchg _sp,[ptr_%1] +%endmacro + +else + +; Macro to load DS and ES registers with correct value. + +MACRO LOAD_DS + mov ds,[cs:_PM_savedDS] + mov es,[cs:_PM_savedDS] +ENDM + +; Note that interrupts we disable interrupts during the following stack +; macro for correct operation, but we do not enable them again. Normally +; these macros are used within interrupt handlers so interrupts should +; already be off. We turn them back on explicitly later if the user code +; needs them to be back on. + +; Macro to switch to a new local stack. + +MACRO NEWSTK stkname + cli + mov [seg_&stkname&],ss + mov [ptr_&stkname&],_sp + mov [TempSeg],ds + mov ss,[TempSeg] + mov _sp,offset stkname +ENDM + +; Macro to switch back to the old stack. + +MACRO RESTSTK stkname + cli + mov ss,[seg_&stkname&] + mov _sp,[ptr_&stkname&] +ENDM + +; Macro to swap the current stack with the one saved away. + +MACRO SWAPSTK stkname + cli + mov ax,ss + xchg ax,[seg_&stkname&] + mov ss,ax + xchg _sp,[ptr_&stkname&] +ENDM + +endif + +begdataseg _pmsmx + + cextern _PM_savedDS,USHORT + cextern _PM_critHandler,CPTR + cextern _PM_breakHandler,CPTR + cextern _PM_timerHandler,CPTR + cextern _PM_rtcHandler,CPTR + cextern _PM_keyHandler,CPTR + cextern _PM_key15Handler,CPTR + cextern _PM_mouseHandler,CPTR + cextern _PM_int10Handler,CPTR + + cextern _PM_ctrlCPtr,DPTR + cextern _PM_ctrlBPtr,DPTR + cextern _PM_critPtr,DPTR + + cextern _PM_prevTimer,FCPTR + cextern _PM_prevRTC,FCPTR + cextern _PM_prevKey,FCPTR + cextern _PM_prevKey15,FCPTR + cextern _PM_prevBreak,FCPTR + cextern _PM_prevCtrlC,FCPTR + cextern _PM_prevCritical,FCPTR + cextern _PM_prevRealTimer,ULONG + cextern _PM_prevRealRTC,ULONG + cextern _PM_prevRealKey,ULONG + cextern _PM_prevRealKey15,ULONG + cextern _PM_prevRealInt10,ULONG + +cpublic _PM_pmsmxDataStart + +; Allocate space for all of the local stacks that we need. These stacks +; are not very large, but should be large enough for most purposes +; (generally you want to handle these interrupts quickly, simply storing +; the information for later and then returning). If you need bigger +; stacks then change the appropriate value in here. + + ALIGN 4 + dclb MOUSE_STACK ; Space for local stack (small) +MsStack: ; Stack starts at end! +ptr_MsStack DUINT 0 ; Place to store old stack offset +seg_MsStack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb INT10_STACK ; Space for local stack (small) +Int10Stack: ; Stack starts at end! +ptr_Int10Stack DUINT 0 ; Place to store old stack offset +seg_Int10Stack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb TIMER_STACK ; Space for local stack (small) +TmStack: ; Stack starts at end! +ptr_TmStack DUINT 0 ; Place to store old stack offset +seg_TmStack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb TIMER_STACK ; Space for local stack (small) +RtcStack: ; Stack starts at end! +ptr_RtcStack DUINT 0 ; Place to store old stack offset +seg_RtcStack dw 0 ; Place to store old stack segment +RtcInside dw 0 ; Are we still handling current interrupt + + ALIGN 4 + dclb KEY_STACK ; Space for local stack (small) +KyStack: ; Stack starts at end! +ptr_KyStack DUINT 0 ; Place to store old stack offset +seg_KyStack dw 0 ; Place to store old stack segment +KyInside dw 0 ; Are we still handling current interrupt + + ALIGN 4 + dclb KEY_STACK ; Space for local stack (small) +Ky15Stack: ; Stack starts at end! +ptr_Ky15Stack DUINT 0 ; Place to store old stack offset +seg_Ky15Stack dw 0 ; Place to store old stack segment + +TempSeg dw 0 ; Place to store stack segment + +cpublic _PM_pmsmxDataEnd + +enddataseg _pmsmx + +begcodeseg _pmsmx ; Start of code segment + +cpublic _PM_pmsmxCodeStart + +;---------------------------------------------------------------------------- +; PM_mouseISR - Mouse interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Interrupt subroutine called by the mouse driver upon interrupts, to +; dispatch control to high level C based subroutines. Interrupts are on +; when we call the user code. +; +; It is _extremely_ important to save the state of the extended registers +; as these may well be trashed by the routines called from here and not +; restored correctly by the mouse interface module. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. For mouse handlers this is not a +; problem, as the mouse driver arbitrates calls to the user mouse +; handler for us. +; +; Entry: AX - Condition mask giving reason for call +; BX - Mouse button state +; CX - Horizontal cursor coordinate +; DX - Vertical cursor coordinate +; SI - Horizontal mickey value +; DI - Vertical mickey value +; +;---------------------------------------------------------------------------- +cprocfar _PM_mouseISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + NEWSTK MsStack ; Switch to local stack + +; Call the installed high level C code routine + + clrhi dx ; Clear out high order values + clrhi cx + clrhi bx + clrhi ax + sgnhi si + sgnhi di + + push _di + push _si + push _dx + push _cx + push _bx + push _ax + sti ; Enable interrupts + call [CPTR _PM_mouseHandler] + _add sp,12,24 + + RESTSTK MsStack ; Restore previous stack + + popad ; Restore all extended registers + pop es + pop ds + ret ; We are done!! + +cprocend + +;---------------------------------------------------------------------------- +; PM_timerISR - Timer interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_timerISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + + NEWSTK TmStack ; Switch to local stack + call [CPTR _PM_timerHandler] + RESTSTK TmStack ; Restore previous stack + + popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; PM_chainPrevTimer - Chain to previous timer interrupt and return +;---------------------------------------------------------------------------- +; Chains to the previous timer interrupt routine and returns control +; back to the high level interrupt handler. +;---------------------------------------------------------------------------- +cprocstart PM_chainPrevTimer + +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealTimer] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax + ret +else + SWAPSTK TmStack ; Swap back to previous stack + pushf ; Save state of interrupt flag + pushf ; Push flags on stack to simulate interrupt +ifdef USE_NASM + call far dword [_PM_prevTimer] +else + call [_PM_prevTimer] +endif + popf ; Restore state of interrupt flag + SWAPSTK TmStack ; Swap back to C stack again + ret +endif + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; PM_rtcISR - Real time clock interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_rtcISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + +; Clear priority interrupt controller and re-enable interrupts so we +; dont lock things up for long. + + mov al,20h + out 0A0h,al + out 020h,al + +; Clear real-time clock timeout + + in al,70h ; Read CMOS index register + push _ax ; and save for later + IODELAYN 3 + mov al,0Ch + out 70h,al + IODELAYN 5 + in al,71h + +; Call the C interrupt handler function + + LOAD_DS ; Load DS register + cmp [BYTE RtcInside],1 ; Check for mutual exclusion + je @@Exit + mov [BYTE RtcInside],1 + sti ; Re-enable interrupts + NEWSTK RtcStack ; Switch to local stack + call [CPTR _PM_rtcHandler] + RESTSTK RtcStack ; Restore previous stack + mov [BYTE RtcInside],0 + +@@Exit: pop _ax + out 70h,al ; Restore CMOS index register + popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; PM_keyISR - keyboard interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the keyboard interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. However we ensure within this routine +; mutual exclusion to the keyboard handling routine. +;---------------------------------------------------------------------------- +cprocfar _PM_keyISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + + cmp [BYTE KyInside],1 ; Check for mutual exclusion + je @@Reissued + + mov [BYTE KyInside],1 + NEWSTK KyStack ; Switch to local stack + call [CPTR _PM_keyHandler] ; Call C code + RESTSTK KyStack ; Restore previous stack + mov [BYTE KyInside],0 + +@@Exit: popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +; When the BIOS keyboard handler needs to change the SHIFT status lights +; on the keyboard, in the process of doing this the keyboard controller +; re-issues another interrupt, while the current handler is still executing. +; If we recieve another interrupt while still handling the current one, +; then simply chain directly to the previous handler. +; +; Note that for most DOS extenders, the real mode interrupt handler that we +; install takes care of this for us. + +@@Reissued: +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax +else + pushf +ifdef USE_NASM + call far dword [_PM_prevKey] +else + call [_PM_prevKey] +endif +endif + jmp @@Exit + +cprocend + +;---------------------------------------------------------------------------- +; PM_chainPrevkey - Chain to previous key interrupt and return +;---------------------------------------------------------------------------- +; Chains to the previous key interrupt routine and returns control +; back to the high level interrupt handler. +;---------------------------------------------------------------------------- +cprocstart PM_chainPrevKey + +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax + ret +else + +; YIKES! For some strange reason, when execution returns from the +; previous keyboard handler, interrupts are re-enabled!! Since we expect +; interrupts to remain off during the duration of our handler, this can +; cause havoc. However our stack macros always turn off interrupts, so they +; will be off when we exit this routine. Obviously there is a tiny weeny +; window when interrupts will be enabled, but there is nothing we can +; do about this. + + SWAPSTK KyStack ; Swap back to previous stack + pushf ; Push flags on stack to simulate interrupt +ifdef USE_NASM + call far dword [_PM_prevKey] +else + call [_PM_prevKey] +endif + SWAPSTK KyStack ; Swap back to C stack again + ret +endif + +cprocend + +;---------------------------------------------------------------------------- +; PM_key15ISR - Int 15h keyboard interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; This routine gets called if we have been called to handle the Int 15h +; keyboard interrupt callout from real mode. +; +; Entry: AX - Hardware scan code to process +; Exit: AX - Hardware scan code to process (0 to ignore) +;---------------------------------------------------------------------------- +cprocfar _PM_key15ISR + + push ds + push es + LOAD_DS + cmp ah,4Fh + jnz @@NotOurs ; Quit if not keyboard callout + + pushad + cld ; Clear direction flag + xor ah,ah ; AX := scan code + NEWSTK Ky15Stack ; Switch to local stack + push _ax + call [CPTR _PM_key15Handler] ; Call C code + _add sp,2,4 + RESTSTK Ky15Stack ; Restore previous stack + test ax,ax + jz @@1 + stc ; Set carry to process as normal + jmp @@2 +@@1: clc ; Clear carry to ignore scan code +@@2: popad + jmp @@Exit ; We are done + +@@NotOurs: +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey15] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax +else + pushf +ifdef USE_NASM + call far dword [_PM_prevKey15] +else + call [_PM_prevKey15] +endif +endif +@@Exit: pop es + pop ds + retf 4 + +cprocend + +;---------------------------------------------------------------------------- +; PM_breakISR - Control Break interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the Ctrl-Break interrupt. We simply set +; the Ctrl-Break flag to a 1 and leave (note that this is accessed through +; a far pointer, as it may well be located in conventional memory). +;---------------------------------------------------------------------------- +cprocfar _PM_breakISR + + sti + push ds ; Save value of DS + push es + push _bx + + LOAD_DS ; Load DS register + mov ebx,[_PM_ctrlBPtr] + mov [UINT _ES _bx],1 + +; Run alternate break handler code if installed + + cmp [CPTR _PM_breakHandler],0 + je @@Exit + + pushad + mov _ax,1 + push _ax + call [CPTR _PM_breakHandler] ; Call C code + pop _ax + popad + +@@Exit: pop _bx + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; int PM_ctrlBreakHit(int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the Ctrl-Break flag and possibly clears it. +;---------------------------------------------------------------------------- +cprocstart PM_ctrlBreakHit + + ARG clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es + mov ebx,[_PM_ctrlBPtr] + cli ; No interrupts thanks! + mov _ax,[_ES _bx] + test [BYTE clearFlag],1 + jz @@Done + mov [UINT _ES _bx],0 + +@@Done: pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_ctrlCISR - Control Break interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the Ctrl-C interrupt. We simply set +; the Ctrl-C flag to a 1 and leave (note that this is accessed through +; a far pointer, as it may well be located in conventional memory). +;---------------------------------------------------------------------------- +cprocfar _PM_ctrlCISR + + sti + push ds ; Save value of DS + push es + push _bx + + LOAD_DS ; Load DS register + mov ebx,[_PM_ctrlCPtr] + mov [UINT _ES _bx],1 + +; Run alternate break handler code if installed + + cmp [CPTR _PM_breakHandler],0 + je @@Exit + + pushad + mov _ax,0 + push _ax + call [CPTR _PM_breakHandler] ; Call C code + pop _ax + popad + +@@Exit: pop _bx + pop es + pop ds + iret ; Return from interrupt + iretd + +cprocend + +;---------------------------------------------------------------------------- +; int PM_ctrlCHit(int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the Ctrl-C flag and possibly clears it. +;---------------------------------------------------------------------------- +cprocstart PM_ctrlCHit + + ARG clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es + mov ebx,[_PM_ctrlCPtr] + cli ; No interrupts thanks! + mov _ax,[_ES _bx] + test [BYTE clearFlag],1 + jz @@Done + mov [UINT _ES _bx],0 + +@@Done: + pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_criticalISR - Control Error handler interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Interrupt handler for the MSDOS Critical Error interrupt, to dispatch +; control to high level C based subroutines. We save the state of all +; registers in this routine, and switch to a local stack. We also pass +; the values of the AX and DI registers to the as pointers, so that the +; values can be modified before returning to MSDOS. +;---------------------------------------------------------------------------- +cprocfar _PM_criticalISR + + sti + push ds ; Save value of DS + push es + push _bx ; Save register values changed + cld ; Clear direction flag + + LOAD_DS ; Load DS register + mov ebx,[_PM_critPtr] + mov [_ES _bx],ax + mov [_ES _bx+2],di + +; Run alternate critical handler code if installed + + cmp [CPTR _PM_critHandler],0 + je @@NoAltHandler + + pushad + push _di + push _ax + call [CPTR _PM_critHandler] ; Call C code + _add sp,4,8 + popad + + pop _bx + pop es + pop ds + iret ; Return from interrupt + +@@NoAltHandler: + mov ax,3 ; Tell MSDOS to fail the operation + pop _bx + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; int PM_criticalError(int *axVal,int *diVal,int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the critical error flags, and the values that +; MSDOS passed in the AX and DI registers to our handler. +;---------------------------------------------------------------------------- +cprocstart PM_criticalError + + ARG axVal:DPTR, diVal:DPTR, clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es + mov ebx,[_PM_critPtr] + cli ; No interrupts thanks! + xor _ax,_ax + xor _di,_di + mov ax,[_ES _bx] + mov di,[_ES _bx+2] + test [BYTE clearFlag],1 + jz @@NoClear + mov [ULONG _ES _bx],0 +@@NoClear: + _les _bx,[axVal] + mov [_ES _bx],_ax + _les _bx,[diVal] + mov [_ES _bx],_di + pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setMouseHandler(int mask, PM_mouseHandler mh) +;---------------------------------------------------------------------------- +cprocstart _PM_setMouseHandler + + ARG mouseMask:UINT + + enter_c + push es + + mov ax,0Ch ; AX := Function 12 - install interrupt sub + mov _cx,[mouseMask] ; CX := mouse mask + mov _dx,offset _PM_mouseISR + push cs + pop es ; ES:_DX -> mouse handler + int 33h ; Call mouse driver + + pop es + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_mousePMCB(void) +;---------------------------------------------------------------------------- +; Mouse realmode callback routine. Upon entry to this routine, we recieve +; the following from the DPMI server: +; +; Entry: DS:_SI -> Real mode stack at time of call +; ES:_DI -> Real mode register data structure +; SS:_SP -> Locked protected mode stack to use +;---------------------------------------------------------------------------- +cprocfar _PM_mousePMCB + + pushad + mov eax,[es:_di+1Ch] ; Load register values from real mode + mov ebx,[es:_di+10h] + mov ecx,[es:_di+18h] + mov edx,[es:_di+14h] + mov esi,[es:_di+04h] + mov edi,[es:_di] + call _PM_mouseISR ; Call the mouse handler + popad + + mov ax,[ds:_si] + mov [es:_di+2Ah],ax ; Plug in return IP address + mov ax,[ds:_si+2] + mov [es:_di+2Ch],ax ; Plug in return CS value + add [WORD es:_di+2Eh],4 ; Remove return address from stack + iret ; Go back to real mode! + +cprocend + +;---------------------------------------------------------------------------- +; void PM_int10PMCB(void) +;---------------------------------------------------------------------------- +; int10 realmode callback routine. Upon entry to this routine, we recieve +; the following from the DPMI server: +; +; Entry: DS:ESI -> Real mode stack at time of call +; ES:EDI -> Real mode register data structure +; SS:ESP -> Locked protected mode stack to use +;---------------------------------------------------------------------------- +cprocfar _PM_int10PMCB + + pushad + push ds + push es + push fs + + pushfd + pop eax + mov [es:edi+20h],ax ; Save return flag status + mov ax,[ds:esi] + mov [es:edi+2Ah],ax ; Plug in return IP address + mov ax,[ds:esi+2] + mov [es:edi+2Ch],ax ; Plug in return CS value + add [WORD es:edi+2Eh],4 ; Remove return address from stack + +; Call the install int10 handler in protected mode. This function gets called +; with DS set to the current data selector, and ES:EDI pointing the the +; real mode DPMI register structure at the time of the interrupt. The +; handle must be written in assembler to be able to extract the real mode +; register values from the structure + + push es + pop fs ; FS:EDI -> real mode registers + LOAD_DS + NEWSTK Int10Stack ; Switch to local stack + + call [_PM_int10Handler] + + RESTSTK Int10Stack ; Restore previous stack + pop fs + pop es + pop ds + popad + iret ; Go back to real mode! + +cprocend + +cpublic _PM_pmsmxCodeEnd + +endcodeseg _pmsmx + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm new file mode 100644 index 0000000..34985a9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm @@ -0,0 +1,652 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Based on original code Copyright 1994 Otto Chrons +;* +;* Language: 80386 Assembler, TASM 4.0 or later +;* Environment: IBM PC 32 bit protected mode +;* +;* Description: Low level page fault handler for virtual linear framebuffers. +;* +;**************************************************************************** + + IDEAL + JUMPS + +include "scitech.mac" ; Memory model macros + +header _vflat ; Set up memory model + +VFLAT_START EQU 0F0000000h +VFLAT_END EQU 0F03FFFFFh +PAGE_PRESENT EQU 1 +PAGE_NOTPRESENT EQU 0 +PAGE_READ EQU 0 +PAGE_WRITE EQU 2 + +ifdef DOS4GW + +;---------------------------------------------------------------------------- +; DOS4G/W flat linear framebuffer emulation. +;---------------------------------------------------------------------------- + +begdataseg _vflat + +; Near pointers to the page directory base and our page tables. All of +; this memory is always located in the first Mb of DOS memory. + +PDBR dd 0 ; Page directory base register (CR3) +accessPageAddr dd 0 +accessPageTable dd 0 + +; CauseWay page directory & 1st page table linear addresses. + +CauseWayDIRLinear dd 0 +CauseWay1stLinear dd 0 + +; Place to store a copy of the original Page Table Directory before we +; intialised our virtual buffer code. + +pageDirectory: resd 1024 ; Saved page table directory + +ValidCS dw 0 ; Valid CS for page faults +Ring0CS dw 0 ; Our ring 0 code selector +LastPage dd 0 ; Last page we mapped in +BankFuncBuf: resb 101 ; Place to store bank switch code +BankFuncPtr dd offset BankFuncBuf + +INT14Gate: +INT14Offset dd 0 ; eip of original vector +INT14Selector dw 0 ; cs of original vector + + cextern _PM_savedDS,USHORT + cextern VF_haveCauseWay,BOOL + +enddataseg _vflat + +begcodeseg _vflat ; Start of code segment + + cextern VF_malloc,FPTR + +;---------------------------------------------------------------------------- +; PF_handler64k - Page fault handler for 64k banks +;---------------------------------------------------------------------------- +; The handler below is a 32 bit ring 0 page fault handler. It receives +; control immediately after any page fault or after an IRQ6 (hardware +; interrupt). This provides the fastest possible handling of page faults +; since it jump directly here. If this is a page fault, the number +; immediately on the stack will be an error code, at offset 4 will be +; the eip of the faulting instruction, at offset 8 will be the cs of the +; faulting instruction. If it is a hardware interrupt, it will not have +; the error code and the eflags will be at offset 8. +;---------------------------------------------------------------------------- +cprocfar PF_handler64k + +; Check if this is a processor exeception or a page fault + + push eax + mov ax,[cs:ValidCS] ; Use CS override to access data + cmp [ss:esp+12],ax ; Is this a page fault? + jne @@ToOldHandler ; Nope, jump to the previous handler + +; Get address of page fault and check if within our handlers range + + mov eax,cr2 ; EBX has page fault linear address + cmp eax,VFLAT_START ; Is the fault less than ours? + jb @@ToOldHandler ; Yep, go to previous handler + cmp eax,VFLAT_END ; Is the fault more than ours? + jae @@ToOldHandler ; Yep, go to previous handler + +; This is our page fault, so we need to handle it + + pushad + push ds + push es + mov ebx,eax ; EBX := page fault address + and ebx,invert 0FFFFh ; Mask to 64k bank boundary + mov ds,[cs:_PM_savedDS]; Load segment registers + mov es,[cs:_PM_savedDS] + +; Map in the page table for our virtual framebuffer area for modification + + mov edi,[PDBR] ; EDI points to page directory + mov edx,ebx ; EDX = linear address + shr edx,22 ; EDX = offset to page directory + mov edx,[edx*4+edi] ; EDX = physical page table address + mov eax,edx + mov edx,[accessPageTable] + or eax,7 + mov [edx],eax + mov eax,cr3 + mov cr3,eax ; Update page table cache + +; Mark all pages valid for the new page fault area + + mov esi,ebx ; ESI := linear address for page + shr esi,10 + and esi,0FFFh ; Offset into page table + add esi,[accessPageAddr] +ifdef USE_NASM +%assign off 0 +%rep 16 + or [DWORD esi+off],0000000001h ; Enable pages +%assign off off+4 +%endrep +else +off = 0 +REPT 16 + or [DWORD esi+off],0000000001h ; Enable pages +off = off+4 +ENDM +endif + +; Mark all pages invalid for the previously mapped area + + xchg esi,[LastPage] ; Save last page for next page fault + test esi,esi + jz @@DoneMapping ; Dont update if first time round +ifdef USE_NASM +%assign off 0 +%rep 16 + or [DWORD esi+off],0FFFFFFFEh ; Disable pages +%assign off off+4 +%endrep +else +off = 0 +REPT 16 + and [DWORD esi+off],0FFFFFFFEh ; Disable pages +off = off+4 +ENDM +endif + +@@DoneMapping: + mov eax,cr3 + mov cr3,eax ; Flush the TLB + +; Now program the new SuperVGA starting bank address + + mov eax,ebx ; EAX := page fault address + shr eax,16 + and eax,0FFh ; Mask to 0-255 + call [BankFuncPtr] ; Call the bank switch function + + pop es + pop ds + popad + pop eax + add esp,4 ; Pop the error code from stack + iretd ; Return to faulting instruction + +@@ToOldHandler: + pop eax +ifdef USE_NASM + jmp far dword [cs:INT14Gate]; Chain to previous handler +else + jmp [FWORD cs:INT14Gate]; Chain to previous handler +endif + +cprocend + +;---------------------------------------------------------------------------- +; PF_handler4k - Page fault handler for 4k banks +;---------------------------------------------------------------------------- +; The handler below is a 32 bit ring 0 page fault handler. It receives +; control immediately after any page fault or after an IRQ6 (hardware +; interrupt). This provides the fastest possible handling of page faults +; since it jump directly here. If this is a page fault, the number +; immediately on the stack will be an error code, at offset 4 will be +; the eip of the faulting instruction, at offset 8 will be the cs of the +; faulting instruction. If it is a hardware interrupt, it will not have +; the error code and the eflags will be at offset 8. +;---------------------------------------------------------------------------- +cprocfar PF_handler4k + +; Fill in when we have tested all the 64Kb code + +ifdef USE_NASM + jmp far dword [cs:INT14Gate]; Chain to previous handler +else + jmp [FWORD cs:INT14Gate]; Chain to previous handler +endif + +cprocend + +;---------------------------------------------------------------------------- +; void InstallFaultHandler(void *baseAddr,int bankSize) +;---------------------------------------------------------------------------- +; Installes the page fault handler directly int the interrupt descriptor +; table for maximum performance. This of course requires ring 0 access, +; but none of this stuff will run without ring 0! +;---------------------------------------------------------------------------- +cprocstart InstallFaultHandler + + ARG baseAddr:ULONG, bankSize:UINT + + enter_c + + mov [DWORD LastPage],0 ; No pages have been mapped + mov ax,cs + mov [ValidCS],ax ; Save CS value for page faults + +; Put address of our page fault handler into the IDT directly + + sub esp,6 ; Allocate space on stack +ifdef USE_NASM + sidt [ss:esp] ; Store pointer to IDT +else + sidt [FWORD ss:esp] ; Store pointer to IDT +endif + pop ax ; add esp,2 + pop eax ; Absolute address of IDT + add eax,14*8 ; Point to Int #14 + +; Note that Interrupt gates do not have the high and low word of the +; offset in adjacent words in memory, there are 4 bytes separating them. + + mov ecx,[eax] ; Get cs and low 16 bits of offset + mov edx,[eax+6] ; Get high 16 bits of offset in dx + shl edx,16 + mov dx,cx ; edx has offset + mov [INT14Offset],edx ; Save offset + shr ecx,16 + mov [INT14Selector],cx ; Save original cs + mov [eax+2],cs ; Install new cs + mov edx,offset PF_handler64k + cmp [UINT bankSize],4 + jne @@1 + mov edx,offset PF_handler4k +@@1: mov [eax],dx ; Install low word of offset + shr edx,16 + mov [eax+6],dx ; Install high word of offset + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void RemoveFaultHandler(void) +;---------------------------------------------------------------------------- +; Closes down the virtual framebuffer services and restores the previous +; page fault handler. +;---------------------------------------------------------------------------- +cprocstart RemoveFaultHandler + + enter_c + +; Remove page fault handler from IDT + + sub esp,6 ; Allocate space on stack +ifdef USE_NASM + sidt [ss:esp] ; Store pointer to IDT +else + sidt [FWORD ss:esp] ; Store pointer to IDT +endif + + pop ax ; add esp,2 + pop eax ; Absolute address of IDT + add eax,14*8 ; Point to Int #14 + mov cx,[INT14Selector] + mov [eax+2],cx ; Restore original CS + mov edx,[INT14Offset] + mov [eax],dx ; Install low word of offset + shr edx,16 + mov [eax+6],dx ; Install high word of offset + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void InstallBankFunc(int codeLen,void *bankFunc) +;---------------------------------------------------------------------------- +; Installs the bank switch function by relocating it into our data segment +; and making it into a callable function. We do it this way to make the +; code identical to the way that the VflatD devices work under Windows. +;---------------------------------------------------------------------------- +cprocstart InstallBankFunc + + ARG codeLen:UINT, bankFunc:DPTR + + enter_c + + mov esi,[bankFunc] ; Copy the code into buffer + mov edi,offset BankFuncBuf + mov ecx,[codeLen] + rep movsb + mov [BYTE edi],0C3h ; Terminate the function with a near ret + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int InitPaging(void) +;---------------------------------------------------------------------------- +; Initializes paging system. If paging is not enabled, builds a page table +; directory and page tables for physical memory +; +; Exit: 0 - Successful +; -1 - Couldn't initialize paging mechanism +;---------------------------------------------------------------------------- +cprocstart InitPaging + + push ebx + push ecx + push edx + push esi + push edi + +; Are we running under CauseWay? + + mov ax,0FFF9h + int 31h + jc @@NotCauseway + cmp ecx,"CAUS" + jnz @@NotCauseway + cmp edx,"EWAY" + jnz @@NotCauseway + + mov [BOOL VF_haveCauseWay],1 + mov [CauseWayDIRLinear],esi + mov [CauseWay1stLinear],edi + +; Check for DPMI + + mov ax,0ff00h + push es + int 31h + pop es + shr edi,2 + and edi,3 + cmp edi,2 + jz @@ErrExit ; Not supported under DPMI + + mov eax,[CauseWayDIRLinear] + jmp @@CopyCR3 + +@@NotCauseway: + mov ax,cs + test ax,3 ; Which ring are we running + jnz @@ErrExit ; Needs zero ring to access + ; page tables (CR3) + mov eax,cr0 ; Load CR0 + test eax,80000000h ; Is paging enabled? + jz @@ErrExit ; No, we must have paging! + + mov eax,cr3 ; Load directory address + and eax,0FFFFF000h + +@@CopyCR3: + mov [PDBR],eax ; Save it + mov esi,eax + mov edi,offset pageDirectory + mov ecx,1024 + cld + rep movsd ; Copy the original page table directory + cmp [DWORD accessPageAddr],0; Check if we have allocated page + jne @@HaveRealMem ; table already (we cant free it) + + mov eax,0100h ; DPMI DOS allocate + mov ebx,8192/16 + int 31h ; Allocate 8192 bytes + and eax,0FFFFh + shl eax,4 ; EAX points to newly allocated memory + add eax,4095 + and eax,0FFFFF000h ; Page align + mov [accessPageAddr],eax + +@@HaveRealMem: + mov eax,[accessPageAddr] ; EAX -> page table in 1st Mb + shr eax,12 + and eax,3FFh ; Page table offset + shl eax,2 + cmp [BOOL VF_haveCauseWay],0 + jz @@NotCW0 + mov ebx,[CauseWay1stLinear] + jmp @@Put1st + +@@NotCW0: + mov ebx,[PDBR] + mov ebx,[ebx] + and ebx,0FFFFF000h ; Page table for 1st megabyte + +@@Put1st: + add eax,ebx + mov [accessPageTable],eax + sub eax,eax ; No error + jmp @@Exit + +@@ErrExit: + mov eax,-1 + +@@Exit: pop edi + pop esi + pop edx + pop ecx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void ClosePaging(void) +;---------------------------------------------------------------------------- +; Closes the paging system +;---------------------------------------------------------------------------- +cprocstart ClosePaging + + push eax + push ecx + push edx + push esi + push edi + + mov eax,[accessPageAddr] + call AccessPage ; Restore AccessPage mapping + mov edi,[PDBR] + mov esi,offset pageDirectory + mov ecx,1024 + cld + rep movsd ; Restore the original page table directory + +@@Exit: pop edi + pop esi + pop edx + pop ecx + pop eax + ret + +cprocend + +;---------------------------------------------------------------------------- +; long AccessPage(long phys) +;---------------------------------------------------------------------------- +; Maps a known page to given physical memory +; Entry: EAX - Physical memory +; Exit: EAX - Linear memory address of mapped phys mem +;---------------------------------------------------------------------------- +cprocstatic AccessPage + + push edx + mov edx,[accessPageTable] + or eax,7 + mov [edx],eax + mov eax,cr3 + mov cr3,eax ; Update page table cache + mov eax,[accessPageAddr] + pop edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; long GetPhysicalAddress(long linear) +;---------------------------------------------------------------------------- +; Returns the physical address of linear address +; Entry: EAX - Linear address to convert +; Exit: EAX - Physical address +;---------------------------------------------------------------------------- +cprocstatic GetPhysicalAddress + + push ebx + push edx + mov edx,eax + shr edx,22 ; EDX is the directory offset + mov ebx,[PDBR] + mov edx,[edx*4+ebx] ; Load page table address + push eax + mov eax,edx + call AccessPage ; Access the page table + mov edx,eax + pop eax + shr eax,12 + and eax,03FFh ; EAX offset into page table + mov eax,[edx+eax*4] ; Load physical address + and eax,0FFFFF000h + pop edx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void CreatePageTable(long pageDEntry) +;---------------------------------------------------------------------------- +; Creates a page table for specific address (4MB) +; Entry: EAX - Page directory entry (top 10-bits of address) +;---------------------------------------------------------------------------- +cprocstatic CreatePageTable + + push ebx + push ecx + push edx + push edi + mov ebx,eax ; Save address + mov eax,8192 + push eax + call VF_malloc ; Allocate page table directory + add esp,4 + add eax,0FFFh + and eax,0FFFFF000h ; Page align (4KB) + mov edi,eax ; Save page table linear address + sub eax,eax ; Fill with zero + mov ecx,1024 + cld + rep stosd ; Clear page table + sub edi,4096 + mov eax,edi + call GetPhysicalAddress + mov edx,[PDBR] + or eax,7 ; Present/write/user bit + mov [edx+ebx*4],eax ; Save physical address into page directory + mov eax,cr3 + mov cr3,eax ; Update page table cache + pop edi + pop edx + pop ecx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags); +;---------------------------------------------------------------------------- +; Maps physical memory into linear memory +; Entry: pAddr - Physical address +; lAddr - Linear address +; pages - Number of 4K pages to map +; flags - Page flags +; bit 0 = present +; bit 1 = Read(0)/Write(1) +;---------------------------------------------------------------------------- +cprocstart MapPhysical2Linear + + ARG pAddr:ULONG, lAddr:ULONG, pages:UINT, pflags:UINT + + enter_c + + and [ULONG pAddr],0FFFFF000h; Page boundary + and [ULONG lAddr],0FFFFF000h; Page boundary + mov ecx,[pflags] + and ecx,11b ; Just two bits + or ecx,100b ; Supervisor bit + mov [pflags],ecx + + mov edx,[lAddr] + shr edx,22 ; EDX = Directory + mov esi,[PDBR] + mov edi,[pages] ; EDI page count + mov ebx,[lAddr] + +@@CreateLoop: + mov ecx,[esi+edx*4] ; Load page table address + test ecx,1 ; Is it present? + jnz @@TableOK + mov eax,edx + call CreatePageTable ; Create a page table +@@TableOK: + mov eax,ebx + shr eax,12 + and eax,3FFh + sub eax,1024 + neg eax ; EAX = page count in this table + inc edx ; Next table + mov ebx,0 ; Next time we'll map 1K pages + sub edi,eax ; Subtract mapped pages from page count + jns @@CreateLoop ; Create more tables if necessary + + mov ecx,[pages] ; ECX = Page count + mov esi,[lAddr] + shr esi,12 ; Offset part isn't needed + mov edi,[pAddr] +@@MappingLoop: + mov eax,esi + shr eax,10 ; EAX = offset to page directory + mov ebx,[PDBR] + mov eax,[eax*4+ebx] ; EAX = page table address + call AccessPage + mov ebx,esi + and ebx,3FFh ; EBX = offset to page table + mov edx,edi + add edi,4096 ; Next physical address + inc esi ; Next linear page + or edx,[pflags] ; Update flags... + mov [eax+ebx*4],edx ; Store page table entry + loop @@MappingLoop + mov eax,cr3 + mov cr3,eax ; Update page table cache + + leave_c + ret + +cprocend + +endcodeseg _vflat + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c new file mode 100644 index 0000000..5447e57 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c @@ -0,0 +1,72 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development. +* +* Description: SMX specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/* External timing function */ + +void __ZTimerInit(void); + +/**************************************************************************** +REMARKS: +Do nothing for DOS because we don't have thread priorities. +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for DOS because we don't have thread priorities. +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + ulong resolution; + + __ZTimerInit(); + ULZTimerResolution(&resolution); + freq->low = (ulong)(10000000000.0 / resolution); + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + (t)->low = ULZReadTime() * 10000L; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/event.c b/board/MAI/bios_emulator/scitech/src/pm/smx/event.c new file mode 100644 index 0000000..533c261 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/event.c @@ -0,0 +1,368 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development +* +* Description: 32-bit SMX implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +#include "smx/ps2mouse.h" + +/*--------------------------- Global variables ----------------------------*/ + +ibool _VARAPI _EVT_useEvents = true; /* True to use event handling */ +ibool _VARAPI _EVT_installed = 0; /* Event handers installed? */ +uchar _VARAPI *_EVT_biosPtr = NULL; /* Pointer to the BIOS data area */ +static ibool haveMouse = false; /* True if we have a mouse */ + +/*---------------------------- Implementation -----------------------------*/ + +/* External assembler functions */ + +void EVTAPI _EVT_pollJoystick(void); +uint EVTAPI _EVT_disableInt(void); +uint EVTAPI _EVT_restoreInt(uint flags); +void EVTAPI _EVT_codeStart(void); +void EVTAPI _EVT_codeEnd(void); +void EVTAPI _EVT_cCodeStart(void); +void EVTAPI _EVT_cCodeEnd(void); +int EVTAPI _EVT_getKeyCode(void); +int EVTAPI EVT_rdinx(int port,int index); +void EVTAPI EVT_wrinx(int port,int index,int value); + +/**************************************************************************** +REMARKS: +Do nothing for DOS, because we are fully interrupt driven. +****************************************************************************/ +#define _EVT_pumpMessages() + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + return (ulong)PM_getLong(_EVT_biosPtr+0x6C) * 55UL; +} + +/**************************************************************************** +REMARKS: +Include generic raw scancode keyboard module. +****************************************************************************/ +#include "common/keyboard.c" + +/**************************************************************************** +REMARKS: +Determines if we have a mouse attached and functioning. +****************************************************************************/ +static ibool detectMouse(void) +{ + return(ps2Query()); +} + +/**************************************************************************** +PARAMETERS: +what - Event code +message - Event message +x,y - Mouse position at time of event +but_stat - Mouse button status at time of event + +REMARKS: +Adds a new mouse event to the event queue. This routine is called from within +the mouse interrupt subroutine, so it must be efficient. + +NOTE: Interrupts MUST be OFF while this routine is called to ensure we have + mutually exclusive access to our internal data structures for + interrupt driven systems (like under DOS). +****************************************************************************/ +static void addMouseEvent( + uint what, + uint message, + int x, + int y, + int mickeyX, + int mickeyY, + uint but_stat) +{ + event_t evt; + + if (EVT.count < EVENTQSIZE) { + /* Save information in event record. */ + evt.when = _EVT_getTicks(); + evt.what = what; + evt.message = message; + evt.modifiers = but_stat; + evt.where_x = x; /* Save mouse event position */ + evt.where_y = y; + evt.relative_x = mickeyX; + evt.relative_y = mickeyY; + evt.modifiers |= EVT.keyModifiers; + addEvent(&evt); /* Add to tail of event queue */ + } +} + +/**************************************************************************** +PARAMETERS: +mask - Event mask +butstate - Button state +x - Mouse x coordinate +y - Mouse y coordinate + +REMARKS: +Mouse event handling routine. This gets called when a mouse event occurs, +and we call the addMouseEvent() routine to add the appropriate mouse event +to the event queue. + +Note: Interrupts are ON when this routine is called by the mouse driver code. +/*AM: NOTE: This function has not actually been ported from DOS yet and should not */ +/*AM: be installed until it is. */ +****************************************************************************/ +static void EVTAPI mouseISR( + uint mask, + uint butstate, + int x, + int y, + int mickeyX, + int mickeyY) +{ + RMREGS regs; + uint ps; + + if (mask & 1) { + /* Save the current mouse coordinates */ + EVT.mx = x; EVT.my = y; + + /* If the last event was a movement event, then modify the last + * event rather than post a new one, so that the queue will not + * become saturated. Before we modify the data structures, we + * MUST ensure that interrupts are off. + */ + ps = _EVT_disableInt(); + if (EVT.oldMove != -1) { + EVT.evtq[EVT.oldMove].where_x = x; /* Modify existing one */ + EVT.evtq[EVT.oldMove].where_y = y; + EVT.evtq[EVT.oldMove].relative_x += mickeyX; + EVT.evtq[EVT.oldMove].relative_y += mickeyY; + } + else { + EVT.oldMove = EVT.freeHead; /* Save id of this move event */ + addMouseEvent(EVT_MOUSEMOVE,0,x,y,mickeyX,mickeyY,butstate); + } + _EVT_restoreInt(ps); + } + if (mask & 0x2A) { + ps = _EVT_disableInt(); + addMouseEvent(EVT_MOUSEDOWN,mask >> 1,x,y,0,0,butstate); + EVT.oldMove = -1; + _EVT_restoreInt(ps); + } + if (mask & 0x54) { + ps = _EVT_disableInt(); + addMouseEvent(EVT_MOUSEUP,mask >> 2,x,y,0,0,butstate); + EVT.oldMove = -1; + _EVT_restoreInt(ps); + } + EVT.oldKey = -1; +} + +/**************************************************************************** +REMARKS: +Keyboard interrupt handler function. + +NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, + and we leave them OFF the entire time. This has been modified to work + in conjunction with smx keyboard handler. +****************************************************************************/ +static void EVTAPI keyboardISR(void) +{ + PM_chainPrevKey(); + processRawScanCode(PM_inpb(0x60)); + PM_outpb(0x20,0x20); +} + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + + EVT.mouseMove = mouseMove; + _EVT_biosPtr = PM_getBIOSPointer(); + EVT_resume(); +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVTAPI EVT_resume(void) +{ + static int locked = 0; + int stat; + uchar mods; + PM_lockHandle lh; + + if (_EVT_useEvents) { + /* Initialise the event queue and enable our interrupt handlers */ + initEventQueue(); + PM_setKeyHandler(keyboardISR); + if ((haveMouse = detectMouse()) != 0) + PM_setMouseHandler(0xFFFF,mouseISR); + + /* Read the keyboard modifier flags from the BIOS to get the + * correct initialisation state. The only state we care about is + * the correct toggle state flags such as SCROLLLOCK, NUMLOCK and + * CAPSLOCK. + */ + EVT.keyModifiers = 0; + mods = PM_getByte(_EVT_biosPtr+0x17); + if (mods & 0x10) + EVT.keyModifiers |= EVT_SCROLLLOCK; + if (mods & 0x20) + EVT.keyModifiers |= EVT_NUMLOCK; + if (mods & 0x40) + EVT.keyModifiers |= EVT_CAPSLOCK; + + /* Lock all of the code and data used by our protected mode interrupt + * handling routines, so that it will continue to work correctly + * under real mode. + */ + if (!locked) { + /* It is difficult to ensure that we lock our global data, so we + * do this by taking the address of a variable locking all data + * 2Kb on either side. This should properly cover the global data + * used by the module (the other alternative is to declare the + * variables in assembler, in which case we know it will be + * correct). + */ + stat = !PM_lockDataPages(&EVT,sizeof(EVT),&lh); + stat |= !PM_lockDataPages(&_EVT_biosPtr,sizeof(_EVT_biosPtr),&lh); + stat |= !PM_lockCodePages((__codePtr)_EVT_cCodeStart,(int)_EVT_cCodeEnd-(int)_EVT_cCodeStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_EVT_codeStart,(int)_EVT_codeEnd-(int)_EVT_codeStart,&lh); + if (stat) { + PM_fatalError("Page locking services failed - interrupt handling not safe!"); + exit(1); + } + locked = 1; + } + + _EVT_installed = true; + } +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + if (haveMouse) { + ps2MouseStop(); + ps2MouseStart( 0, xRes, 0, yRes, -1, -1, -1); + } +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +void _EVT_setMousePos( + int *x, + int *y) +{ + if (haveMouse) + ps2MouseMove(*x, *y); +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVTAPI EVT_suspend(void) +{ + uchar mods; + + if (_EVT_installed) { + PM_restoreKeyHandler(); + if (haveMouse) + PM_restoreMouseHandler(); + + /* Set the keyboard modifier flags in the BIOS to our values */ + EVT_allowLEDS(true); + mods = PM_getByte(_EVT_biosPtr+0x17) & ~0x70; + if (EVT.keyModifiers & EVT_SCROLLLOCK) + mods |= 0x10; + if (EVT.keyModifiers & EVT_NUMLOCK) + mods |= 0x20; + if (EVT.keyModifiers & EVT_CAPSLOCK) + mods |= 0x40; + PM_setByte(_EVT_biosPtr+0x17,mods); + + /* Flag that we are no longer installed */ + _EVT_installed = false; + } +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVTAPI EVT_exit(void) +{ + EVT_suspend(); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h new file mode 100644 index 0000000..3ff8daa --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h @@ -0,0 +1,29 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development. +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c b/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c new file mode 100644 index 0000000..99ee3d4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c @@ -0,0 +1,1187 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32 bit SMX embedded systems development. +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "ztimerc.h" +#include "event.h" +#include "mtrr.h" +#include "pm_help.h" +#include +#include +#include +#include +#include +#ifdef __GNUC__ +#include +#include +#include +#else +#include +#endif +#ifdef __BORLANDC__ +#pragma warn -par +#endif + +/*--------------------------- Global variables ----------------------------*/ + +typedef struct { + int oldMode; + int old50Lines; + } DOS_stateBuf; + +#define MAX_RM_BLOCKS 10 + +static struct { + void *p; + uint tag; + } rmBlocks[MAX_RM_BLOCKS]; + +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +static void (PMAPIP fatalErrorCleanup)(void) = NULL; +ushort _VARAPI _PM_savedDS = 0; +static ulong PDB = 0,*pPDB = NULL; +static uint VXD_version = -1; + +/*----------------------------- Implementation ----------------------------*/ + +ulong _ASMAPI _PM_getPDB(void); +void _ASMAPI _PM_VxDCall(VXD_regs *regs,uint off,uint sel); + +/**************************************************************************** +REMARKS: +External function to call the PMHELP helper VxD. +****************************************************************************/ +void PMAPI PM_VxDCall( + VXD_regs *regs) +{ +} + +/**************************************************************************** +RETURNS: +BCD coded version number of the VxD, or 0 if not loaded (ie: 0x202 - 2.2) + +REMARKS: +This function gets the version number for the VxD that we have connected to. +****************************************************************************/ +uint PMAPI PMHELP_getVersion(void) +{ + return VXD_version = 0; +} + +void PMAPI PM_init(void) +{ +#ifndef REALMODE + MTRR_init(); +#endif +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ +#ifndef REALMODE + return MTRR_enableWriteCombine(base,size,type); +#else + return PM_MTRR_NOT_SUPPORTED; +#endif +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return false; } + +long PMAPI PM_getOSType(void) +{ return _OS_SMX; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void MGLOutput(char *); + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + MGLOutput(msg); +/* No support for fprintf() under smx currently! */ +/* fprintf(stderr,"%s\n", msg); */ + exit(1); +} + +static void ExitVBEBuf(void) +{ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out) +{ + PMSREGS sregs; + PM_segread(&sregs); + return PM_int386x(intno,in,out,&sregs); +} + +/* Routines to set and get the real mode interrupt vectors, by making + * direct real mode calls to DOS and bypassing the DOS extenders API. + * This is the safest way to handle this, as some servers try to be + * smart about changing real mode vectors. + */ + +void PMAPI _PM_getRMvect(int intno, long *realisr) +{ + RMREGS regs; + RMSREGS sregs; + + PM_saveDS(); + regs.h.ah = 0x35; + regs.h.al = intno; + PM_int86x(0x21, ®s, ®s, &sregs); + *realisr = ((long)sregs.es << 16) | regs.x.bx; +} + +void PMAPI _PM_setRMvect(int intno, long realisr) +{ + RMREGS regs; + RMSREGS sregs; + + PM_saveDS(); + regs.h.ah = 0x25; + regs.h.al = intno; + sregs.ds = (int)(realisr >> 16); + regs.x.dx = (int)(realisr & 0xFFFF); + PM_int86x(0x21, ®s, ®s, &sregs); +} + +void PMAPI _PM_addRealModeBlock(void *mem,uint tag) +{ + int i; + + for (i = 0; i < MAX_RM_BLOCKS; i++) { + if (rmBlocks[i].p == NULL) { + rmBlocks[i].p = mem; + rmBlocks[i].tag = tag; + return; + } + } + PM_fatalError("To many real mode memory block allocations!"); +} + +uint PMAPI _PM_findRealModeBlock(void *mem) +{ + int i; + + for (i = 0; i < MAX_RM_BLOCKS; i++) { + if (rmBlocks[i].p == mem) + return rmBlocks[i].tag; + } + PM_fatalError("Could not find prior real mode memory block allocation!"); + return 0; +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return 'C'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return "c:\\"; } + +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + char *env; + + if ((env = getenv("NUCLEUS_PATH")) != NULL) + return env; + return "c:\\nucleus"; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ return "SMX"; } + +const char * PMAPI PM_getMachineName(void) +{ return "SMX"; } + +int PMAPI PM_kbhit(void) +{ + int hit; + event_t evt; + + hit = EVT_peekNext(&evt,EVT_KEYDOWN | EVT_KEYREPEAT); + EVT_flush(~(EVT_KEYDOWN | EVT_KEYREPEAT)); + return hit; +} + +int PMAPI PM_getch(void) +{ + event_t evt; + + EVT_halt(&evt,EVT_KEYDOWN); + return EVT_asciiCode(evt.message); +} + +PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen) +{ + /* Not used for SMX */ + (void)hwndUser; + (void)device; + (void)xRes; + (void)yRes; + (void)bpp; + (void)fullScreen; + return 0; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + return sizeof(DOS_stateBuf); +} + +void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole) +{ + RMREGS regs; + DOS_stateBuf *sb = stateBuf; + + /* Save the old video mode state */ + regs.h.ah = 0x0F; + PM_int86(0x10,®s,®s); + sb->oldMode = regs.h.al & 0x7F; + sb->old50Lines = false; + if (sb->oldMode == 0x3) { + regs.x.ax = 0x1130; + regs.x.bx = 0; + regs.x.dx = 0; + PM_int86(0x10,®s,®s); + sb->old50Lines = (regs.h.dl == 42 || regs.h.dl == 49); + } + (void)hwndConsole; +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* Not used for SMX */ + (void)saveState; +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) +{ + RMREGS regs; + const DOS_stateBuf *sb = stateBuf; + + /* Retore 50 line mode if set */ + if (sb->old50Lines) { + regs.x.ax = 0x1112; + regs.x.bx = 0; + PM_int86(0x10,®s,®s); + } + (void)hwndConsole; +} + +void PMAPI PM_closeConsole(PM_HWND hwndConsole) +{ + /* Not used for SMX */ + (void)hwndConsole; +} + +void PMAPI PM_setOSCursorLocation(int x,int y) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x50,x); + PM_setByte(_biosPtr+0x51,y); +} + +void PMAPI PM_setOSScreenWidth(int width,int height) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setWord(_biosPtr+0x4A,width); + PM_setWord(_biosPtr+0x4C,width*2); + PM_setByte(_biosPtr+0x84,height-1); + if (height > 25) { + PM_setWord(_biosPtr+0x60,0x0607); + PM_setByte(_biosPtr+0x85,0x08); + } + else { + PM_setWord(_biosPtr+0x60,0x0D0E); + PM_setByte(_biosPtr+0x85,0x016); + } +} + +void * PMAPI PM_mallocShared(long size) +{ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + PM_free(ptr); +} + +#define GetRMVect(intno,isr) *(isr) = ((ulong*)rmZeroPtr)[intno] +#define SetRMVect(intno,isr) ((ulong*)rmZeroPtr)[intno] = (isr) + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + static int firstTime = true; + static uchar *rmZeroPtr; + long Current10,Current6D,Current42; + RMREGS regs; + RMSREGS sregs; + + /* Create a zero memory mapping for us to use */ + if (firstTime) { + rmZeroPtr = PM_mapPhysicalAddr(0,0x7FFF,true); + firstTime = false; + } + + /* Remap the secondary BIOS to 0xC0000 physical */ + if (BIOSPhysAddr != 0xC0000L || BIOSLen > 32768) { + /* SMX cannot virtually remap the BIOS, so we can only work if all + * the secondary controllers are identical, and we then use the + * BIOS on the first controller for all the remaining controllers. + * + * For OS'es that do virtual memory, and remapping of 0xC0000 + * physical (perhaps a copy on write mapping) should be all that + * is needed. + */ + return false; + } + + /* Save current handlers of int 10h and 6Dh */ + GetRMVect(0x10,&Current10); + GetRMVect(0x6D,&Current6D); + + /* POST the secondary BIOS */ + GetRMVect(0x42,&Current42); + SetRMVect(0x10,Current42); /* Restore int 10h to STD-BIOS */ + regs.x.ax = axVal; + PM_callRealMode(0xC000,0x0003,®s,&sregs); + + /* Restore current handlers */ + SetRMVect(0x10,Current10); + SetRMVect(0x6D,Current6D); + + /* Second the primary BIOS mappin 1:1 for 0xC0000 physical */ + if (BIOSPhysAddr != 0xC0000L) { + /* SMX does not support this */ + (void)mappedBIOS; + } + return true; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + ulong microseconds = milliseconds * 1000L; + LZTimerObject tm; + + LZTimerOnExt(&tm); + while (LZTimerLapExt(&tm) < microseconds) + ; + LZTimerOffExt(&tm); +} + +int PMAPI PM_getCOMPort(int port) +{ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + (void)hModule; +} + +int PMAPI PM_setIOPL( + int level) +{ + return level; +} + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + struct find_t *blk) +{ + ulong dwSize = findData->dwSize; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + if (blk->attrib & _A_RDONLY) + findData->attrib |= PM_FILE_READONLY; + if (blk->attrib & _A_SUBDIR) + findData->attrib |= PM_FILE_DIRECTORY; + if (blk->attrib & _A_ARCH) + findData->attrib |= PM_FILE_ARCHIVE; + if (blk->attrib & _A_HIDDEN) + findData->attrib |= PM_FILE_HIDDEN; + if (blk->attrib & _A_SYSTEM) + findData->attrib |= PM_FILE_SYSTEM; + findData->sizeLo = blk->size; + strncpy(findData->name,blk->name,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +#define FIND_MASK (_A_RDONLY | _A_ARCH | _A_SUBDIR | _A_HIDDEN | _A_SYSTEM) + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void * PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + struct find_t *blk; + + if ((blk = PM_malloc(sizeof(*blk))) == NULL) + return PM_FILE_INVALID; + if (_dos_findfirst((char*)filename,FIND_MASK,blk) == 0) { + convertFindData(findData,blk); + return blk; + } + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + struct find_t *blk = handle; + + if (_dos_findnext(blk) == 0) { + convertFindData(findData,blk); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + PM_free(handle); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + RMREGS regs; + regs.h.dl = (uchar)(drive - 'A' + 1); + regs.h.ah = 0x36; /* Get disk information service */ + PM_int86(0x21,®s,®s); + return regs.x.ax != 0xFFFF; /* AX = 0xFFFF if disk is invalid */ +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + uint oldDrive,maxDrives; + _dos_getdrive(&oldDrive); + _dos_setdrive(drive,&maxDrives); + getcwd(dir,len); + _dos_setdrive(oldDrive,&maxDrives); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ +#if defined(TNT) && defined(_MSC_VER) + DWORD attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= FILE_ATTRIBUTE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= FILE_ATTRIBUTE_ARCHIVE; + if (attrib & PM_FILE_HIDDEN) + attr |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= FILE_ATTRIBUTE_SYSTEM; + SetFileAttributes((LPSTR)filename, attr); +#else + uint attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= _A_RDONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= _A_ARCH; + if (attrib & PM_FILE_HIDDEN) + attr |= _A_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= _A_SYSTEM; + _dos_setfileattr(filename,attr); +#endif +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ +#ifdef __GNUC__ + return mkdir(filename,S_IRUSR) == 0; +#else +/*AM: return mkdir(filename) == 0; */ + return(false); +#endif +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ +/*AM: return rmdir(filename) == 0; */ + return(false); +} + +/**************************************************************************** +REMARKS: +Allocates a block of locked, physically contiguous memory. The memory +may be required to be below the 16Meg boundary. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + void *p; + uint r_seg,r_off; + PM_lockHandle lh; + + /* Under DOS the only way to know the physical memory address is to + * allocate the memory below the 1Meg boundary as real mode memory. + * We also allocate 4095 bytes more memory than we need, so we can + * properly page align the start of the memory block for DMA operations. + */ + if (size > 4096) + return NULL; + if ((p = PM_allocRealSeg((size + 0xFFF) & ~0xFFF,&r_seg,&r_off)) == NULL) + return NULL; + *physAddr = ((r_seg << 4) + r_off + 0xFFF) & ~0xFFF; + PM_lockDataPages(p,size*2,&lh); + return p; +} + +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) +{ + (void)size; + PM_freeRealSeg(p); +} + +/*-------------------------------------------------------------------------*/ +/* Generic DPMI routines common to 16/32 bit code */ +/*-------------------------------------------------------------------------*/ + +ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit) +{ + PMREGS r; + ulong physOfs; + + if (physAddr < 0x100000L) { + /* We can't map memory below 1Mb, but the linear address are already + * mapped 1:1 for this memory anyway so we just return the base address. + */ + return physAddr; + } + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to DPMI as some extenders + * will fail the calls unless this is the case. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + physOfs = physAddr & 4095; + physAddr = physAddr & ~4095; + limit = ((limit+physOfs+1+4095) & ~4095)-1; + + r.x.ax = 0x800; /* DPMI map physical to linear */ + r.x.bx = physAddr >> 16; + r.x.cx = physAddr & 0xFFFF; + r.x.si = limit >> 16; + r.x.di = limit & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0xFFFFFFFFUL; + return ((ulong)r.x.bx << 16) + r.x.cx + physOfs; +} + +int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr) +{ + PMREGS r; + + r.x.ax = 7; /* DPMI set selector base address */ + r.x.bx = sel; + r.x.cx = linAddr >> 16; + r.x.dx = linAddr & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0; + return 1; +} + +ulong PMAPI DPMI_getSelectorBase(ushort sel) +{ + PMREGS r; + + r.x.ax = 6; /* DPMI get selector base address */ + r.x.bx = sel; + PM_int386(0x31, &r, &r); + return ((ulong)r.x.cx << 16) + r.x.dx; +} + +int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit) +{ + PMREGS r; + + r.x.ax = 8; /* DPMI set selector limit */ + r.x.bx = sel; + r.x.cx = limit >> 16; + r.x.dx = limit & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0; + return 1; +} + +uint PMAPI DPMI_createSelector(ulong base,ulong limit) +{ + uint sel; + PMREGS r; + + /* Allocate 1 descriptor */ + r.x.ax = 0; + r.x.cx = 1; + PM_int386(0x31, &r, &r); + if (r.x.cflag) return 0; + sel = r.x.ax; + + /* Set the descriptor access rights (for a 32 bit page granular + * segment, ring 0). + */ + r.x.ax = 9; + r.x.bx = sel; + r.x.cx = 0x4093; + PM_int386(0x31, &r, &r); + + /* Map physical memory and create selector */ + if ((base = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFFUL) + return 0; + if (!DPMI_setSelectorBase(sel,base)) + return 0; + if (!DPMI_setSelectorLimit(sel,limit)) + return 0; + return sel; +} + +void PMAPI DPMI_freeSelector(uint sel) +{ + PMREGS r; + + r.x.ax = 1; + r.x.bx = sel; + PM_int386(0x31, &r, &r); +} + +int PMAPI DPMI_lockLinearPages(ulong linear,ulong len) +{ + PMREGS r; + + r.x.ax = 0x600; /* DPMI Lock Linear Region */ + r.x.bx = (linear >> 16); /* Linear address in BX:CX */ + r.x.cx = (linear & 0xFFFF); + r.x.si = (len >> 16); /* Length in SI:DI */ + r.x.di = (len & 0xFFFF); + PM_int386(0x31, &r, &r); + return (!r.x.cflag); +} + +int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len) +{ + PMREGS r; + + r.x.ax = 0x601; /* DPMI Unlock Linear Region */ + r.x.bx = (linear >> 16); /* Linear address in BX:CX */ + r.x.cx = (linear & 0xFFFF); + r.x.si = (len >> 16); /* Length in SI:DI */ + r.x.di = (len & 0xFFFF); + PM_int386(0x31, &r, &r); + return (!r.x.cflag); +} + +void * PMAPI DPMI_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + PMSREGS sregs; + ulong linAddr; + ulong DSBaseAddr; + + /* Get the base address for the default DS selector */ + PM_segread(&sregs); + DSBaseAddr = DPMI_getSelectorBase(sregs.ds); + if ((base < 0x100000) && (DSBaseAddr == 0)) { + /* DS is zero based, so we can directly access the first 1Mb of + * system memory (like under DOS4GW). + */ + return (void*)base; + } + + /* Map the memory to a linear address using DPMI function 0x800 */ + if ((linAddr = DPMI_mapPhysicalToLinear(base,limit)) == 0) { + if (base >= 0x100000) + return NULL; + /* If the linear address mapping fails but we are trying to + * map an area in the first 1Mb of system memory, then we must + * be running under a Windows or OS/2 DOS box. Under these + * environments we can use the segment wrap around as a fallback + * measure, as this does work properly. + */ + linAddr = base; + } + + /* Now expand the default DS selector to 4Gb so we can access it */ + if (!DPMI_setSelectorLimit(sregs.ds,0xFFFFFFFFUL)) + return NULL; + + /* Finally enable caching for the page tables that we just mapped in, + * since DOS4GW and PMODE/W create the page table entries without + * caching enabled which hurts the performance of the linear framebuffer + * as it disables write combining on Pentium Pro and above processors. + * + * For those processors cache disabling is better handled through the + * MTRR registers anyway (we can write combine a region but disable + * caching) so that MMIO register regions do not screw up. + */ + if (isCached) { + if ((PDB = _PM_getPDB()) != 0 && DSBaseAddr == 0) { + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPageTable; + if (!pPDB) { + if (PDB >= 0x100000) + pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF); + else + pPDB = (ulong*)PDB; + } + if (pPDB) { + startPDB = (linAddr >> 22) & 0x3FF; + startPage = (linAddr >> 12) & 0x3FF; + endPDB = ((linAddr+limit) >> 22) & 0x3FF; + endPage = ((linAddr+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + pageTable = pPDB[iPDB] & ~0xFFF; + if (pageTable >= 0x100000) + pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF); + else + pPageTable = (ulong*)pageTable; + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) + pPageTable[iPage] &= ~0x18; + } + } + } + } + + /* Now return the base address of the memory into the default DS */ + return (void*)(linAddr - DSBaseAddr); +} + +/* Some DOS extender implementations do not directly support calling a + * real mode procedure from protected mode. However we can simulate what + * we need temporarily hooking the INT 6Ah vector with a small real mode + * stub that will call our real mode code for us. + */ + +static uchar int6AHandler[] = { + 0x00,0x00,0x00,0x00, /* __PMODE_callReal variable */ + 0xFB, /* sti */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PMODE_callReal] */ + 0xCF, /* iretf */ + }; +static uchar *crPtr = NULL; /* Pointer to of int 6A handler */ +static uint crRSeg,crROff; /* Real mode seg:offset of handler */ + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + uchar *p; + uint oldSeg,oldOff; + + if (!crPtr) { + /* Allocate and copy the memory block only once */ + crPtr = PM_allocRealSeg(sizeof(int6AHandler), &crRSeg, &crROff); + memcpy(crPtr,int6AHandler,sizeof(int6AHandler)); + } + PM_setWord(crPtr,off); /* Plug in address to call */ + PM_setWord(crPtr+2,seg); + p = PM_mapRealPointer(0,0x6A * 4); + oldOff = PM_getWord(p); /* Save old handler address */ + oldSeg = PM_getWord(p+2); + PM_setWord(p,crROff+4); /* Hook 6A handler */ + PM_setWord(p+2,crRSeg); + PM_int86x(0x6A, in, in, sregs); /* Call real mode code */ + PM_setWord(p,oldOff); /* Restore old handler */ + PM_setWord(p+2,oldSeg); +} + +void * PMAPI PM_getBIOSPointer(void) +{ return PM_mapPhysicalAddr(0x400,0xFFFF,true); } + +void * PMAPI PM_getA0000Pointer(void) +{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); } + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ return DPMI_mapPhysicalAddr(base,limit,isCached); } + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* Mapping cannot be free */ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + (void)p; + return 0xFFFFFFFFUL; +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ + (void)limit; + return (void*)base; +} + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + static uchar *zeroPtr = NULL; + + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + PMREGS r; + void *p; + + r.x.ax = 0x100; /* DPMI allocate DOS memory */ + r.x.bx = (size + 0xF) >> 4; /* number of paragraphs */ + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return NULL; /* DPMI call failed */ + *r_seg = r.x.ax; /* Real mode segment */ + *r_off = 0; + p = PM_mapRealPointer(*r_seg,*r_off); + _PM_addRealModeBlock(p,r.x.dx); + return p; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + PMREGS r; + + r.x.ax = 0x101; /* DPMI free DOS memory */ + r.x.dx = _PM_findRealModeBlock(mem);/* DX := selector from 0x100 */ + PM_int386(0x31, &r, &r); +} + +static DPMI_handler_t DPMI_int10 = NULL; + +void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler) +{ + DPMI_int10 = handler; +} + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + PMREGS r; + PMSREGS sr; + + if (intno == 0x10 && DPMI_int10) { + if (DPMI_int10(regs)) + return; + } + PM_segread(&sr); + r.x.ax = 0x300; /* DPMI issue real interrupt */ + r.h.bl = intno; + r.h.bh = 0; + r.x.cx = 0; + sr.es = sr.ds; + r.e.edi = (uint)regs; + PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ +} + +#define IN(reg) rmregs.reg = in->e.reg +#define OUT(reg) out->e.reg = rmregs.reg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + +/* These real mode ints may cause crashes. */ +/*AM: DPMI_int86(intno,&rmregs); /###* DPMI issue real interrupt */ + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + +/*AM: DPMI_int86(intno,&rmregs); /###* DPMI issue real interrupt */ + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->cs = rmregs.cs; + sregs->ss = rmregs.ss; + sregs->ds = rmregs.ds; + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +#pragma pack(1) + +typedef struct { + uint LargestBlockAvail; + uint MaxUnlockedPage; + uint LargestLockablePage; + uint LinAddrSpace; + uint NumFreePagesAvail; + uint NumPhysicalPagesFree; + uint TotalPhysicalPages; + uint FreeLinAddrSpace; + uint SizeOfPageFile; + uint res[3]; + } MemInfo; + +#pragma pack() + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS r; + PMSREGS sr; + MemInfo memInfo; + + PM_segread(&sr); + r.x.ax = 0x500; /* DPMI get free memory info */ + sr.es = sr.ds; + r.e.edi = (uint)&memInfo; + PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ + *physical = memInfo.NumPhysicalPagesFree * 4096; + *total = memInfo.LargestBlockAvail; + if (*total < *physical) + *physical = *total; +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + /* TODO: Implement this! */ + return 0; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c b/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c new file mode 100644 index 0000000..98e31bc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c @@ -0,0 +1,471 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include +#include +#include +#include "smx/ps2mouse.h" + +/*--------------------------- Global variables ----------------------------*/ + +static int globalDataStart; + +PM_criticalHandler _VARAPI _PM_critHandler = NULL; +PM_breakHandler _VARAPI _PM_breakHandler = NULL; +PM_intHandler _VARAPI _PM_timerHandler = NULL; +PM_intHandler _VARAPI _PM_rtcHandler = NULL; +PM_intHandler _VARAPI _PM_keyHandler = NULL; +PM_key15Handler _VARAPI _PM_key15Handler = NULL; +PM_mouseHandler _VARAPI _PM_mouseHandler = NULL; +PM_intHandler _VARAPI _PM_int10Handler = NULL; +int _VARAPI _PM_mouseMask; + +uchar * _VARAPI _PM_ctrlCPtr; /* Location of Ctrl-C flag */ +uchar * _VARAPI _PM_ctrlBPtr; /* Location of Ctrl-Break flag */ +uchar * _VARAPI _PM_critPtr; /* Location of Critical error Bf*/ +PMFARPTR _VARAPI _PM_prevTimer = PMNULL; /* Previous timer handler */ +PMFARPTR _VARAPI _PM_prevRTC = PMNULL; /* Previous RTC handler */ +PMFARPTR _VARAPI _PM_prevKey = PMNULL; /* Previous key handler */ +PMFARPTR _VARAPI _PM_prevKey15 = PMNULL; /* Previous key15 handler */ +PMFARPTR _VARAPI _PM_prevBreak = PMNULL; /* Previous break handler */ +PMFARPTR _VARAPI _PM_prevCtrlC = PMNULL; /* Previous CtrlC handler */ +PMFARPTR _VARAPI _PM_prevCritical = PMNULL; /* Previous critical handler */ +long _VARAPI _PM_prevRealTimer; /* Previous real mode timer */ +long _VARAPI _PM_prevRealRTC; /* Previous real mode RTC */ +long _VARAPI _PM_prevRealKey; /* Previous real mode key */ +long _VARAPI _PM_prevRealKey15; /* Previous real mode key15 */ +long _VARAPI _PM_prevRealInt10; /* Previous real mode int 10h */ +static uchar _PM_oldCMOSRegA; /* CMOS register A contents */ +static uchar _PM_oldCMOSRegB; /* CMOS register B contents */ +static uchar _PM_oldRTCPIC2; /* Mask value for RTC IRQ8 */ + +/*----------------------------- Implementation ----------------------------*/ + +/* Globals for locking interrupt handlers in _pmsmx.asm */ + +extern int _ASMAPI _PM_pmsmxDataStart; +extern int _ASMAPI _PM_pmsmxDataEnd; +void _ASMAPI _PM_pmsmxCodeStart(void); +void _ASMAPI _PM_pmsmxCodeEnd(void); + +/* Protected mode interrupt handlers, also called by PM callbacks below */ + +void _ASMAPI _PM_timerISR(void); +void _ASMAPI _PM_rtcISR(void); +void _ASMAPI _PM_keyISR(void); +void _ASMAPI _PM_key15ISR(void); +void _ASMAPI _PM_breakISR(void); +void _ASMAPI _PM_ctrlCISR(void); +void _ASMAPI _PM_criticalISR(void); +void _ASMAPI _PM_mouseISR(void); +void _ASMAPI _PM_int10PMCB(void); + +/* Protected mode DPMI callback handlers */ + +void _ASMAPI _PM_mousePMCB(void); + +/* Routine to install a mouse handler function */ + +void _ASMAPI _PM_setMouseHandler(int mask); + +/* Routine to allocate DPMI real mode callback routines */ + +void _ASMAPI _DPMI_allocateCallback(void (_ASMAPI *pmcode)(),void *rmregs,long *RMCB); +void _ASMAPI _DPMI_freeCallback(long RMCB); + +/* DPMI helper functions in PMLITE.C */ + +ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit); +int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr); +ulong PMAPI DPMI_getSelectorBase(ushort sel); +int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit); +uint PMAPI DPMI_createSelector(ulong base,ulong limit); +void PMAPI DPMI_freeSelector(uint sel); +int PMAPI DPMI_lockLinearPages(ulong linear,ulong len); +int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len); + +/* Functions to read and write CMOS registers */ + +uchar PMAPI _PM_readCMOS(int index); +void PMAPI _PM_writeCMOS(int index,uchar value); + +/*-------------------------------------------------------------------------*/ +/* Generic routines common to all environments */ +/*-------------------------------------------------------------------------*/ + +void PMAPI PM_resetMouseDriver(int hardReset) +{ + ps2MouseReset(); +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + static short convert[] = { + 8192, + 4096, + 2048, + 1024, + 512, + 256, + 128, + 64, + 32, + 16, + 8, + 4, + 2, + -1, + }; + int i; + + /* First clear any pending RTC timeout if not cleared */ + _PM_readCMOS(0x0C); + if (frequency == 0) { + /* Disable RTC timout */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F); + } + else { + /* Convert frequency value to RTC clock indexes */ + for (i = 0; convert[i] != -1; i++) { + if (convert[i] == frequency) + break; + } + + /* Set RTC timout value and enable timeout */ + _PM_writeCMOS(0x0A,(_PM_oldCMOSRegA & 0xF0) | (i+3)); + _PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40); + } +} + +static void PMAPI lockPMHandlers(void) +{ + static int locked = 0; + int stat = 0; + PM_lockHandle lh; + + /* Lock all of the code and data used by our protected mode interrupt + * handling routines, so that it will continue to work correctly + * under real mode. + */ + if (!locked) { + PM_saveDS(); + stat = !PM_lockDataPages(&globalDataStart-2048,4096,&lh); + stat |= !PM_lockDataPages(&_PM_pmsmxDataStart,(int)&_PM_pmsmxDataEnd - (int)&_PM_pmsmxDataStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_PM_pmsmxCodeStart,(int)_PM_pmsmxCodeEnd-(int)_PM_pmsmxCodeStart,&lh); + if (stat) { + printf("Page locking services failed - interrupt handling not safe!\n"); + exit(1); + } + locked = 1; + } +} + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + + regs.x.ax = 0x204; + regs.h.bl = intno; + PM_int386(0x31,®s,®s); + isr->sel = regs.x.cx; + isr->off = regs.e.edx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMSREGS sregs; + PMREGS regs; + + PM_saveDS(); + regs.x.ax = 0x205; /* Set protected mode vector */ + regs.h.bl = intno; + PM_segread(&sregs); + regs.x.cx = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386(0x31,®s,®s); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + + regs.x.ax = 0x205; + regs.h.bl = intno; + regs.x.cx = isr.sel; + regs.e.edx = isr.off; + PM_int386(0x31,®s,®s); +} + +static long prevRealBreak; /* Previous real mode break handler */ +static long prevRealCtrlC; /* Previous real mode CtrlC handler */ +static long prevRealCritical; /* Prev real mode critical handler */ + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + lockPMHandlers(); /* Ensure our handlers are locked */ + + _PM_mouseHandler = mh; + return 0; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + if (_PM_mouseHandler) + _PM_mouseHandler = NULL; +} + +static void getISR(int intno, PMFARPTR *pmisr, long *realisr) +{ + PM_getPMvect(intno,pmisr); +} + +static void restoreISR(int intno, PMFARPTR pmisr, long realisr) +{ + PM_restorePMvect(intno,pmisr); +} + +static void setISR(int intno, void (* PMAPI pmisr)()) +{ + lockPMHandlers(); /* Ensure our handlers are locked */ + PM_setPMvect(intno,pmisr); +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + getISR(PM_IRQ0, &_PM_prevTimer, &_PM_prevRealTimer); + _PM_timerHandler = th; + setISR(PM_IRQ0, _PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + restoreISR(PM_IRQ0, _PM_prevTimer, _PM_prevRealTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); + _PM_rtcHandler = th; + setISR(0x70, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); + _PM_rtcHandler = NULL; + } +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + getISR(PM_IRQ1, &_PM_prevKey, &_PM_prevRealKey); + _PM_keyHandler = kh; + setISR(PM_IRQ1, _PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + restoreISR(PM_IRQ1, _PM_prevKey, _PM_prevRealKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); + _PM_key15Handler = kh; + setISR(0x15, _PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); + _PM_key15Handler = NULL; + } +} + +/* Real mode Ctrl-C and Ctrl-Break handler. This handler simply sets a + * flag in the real mode code segment and exit. We save the location + * of this flag in real mode memory so that both the real mode and + * protected mode code will be modifying the same flags. + */ + +static uchar ctrlHandler[] = { + 0x00,0x00,0x00,0x00, /* ctrlBFlag */ + 0x66,0x2E,0xC7,0x06,0x00,0x00, + 0x01,0x00,0x00,0x00, /* mov [cs:ctrlBFlag],1 */ + 0xCF, /* iretf */ + }; + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ + uint rseg,roff; + + getISR(0x1B, &_PM_prevBreak, &prevRealBreak); + getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); + _PM_breakHandler = bh; + setISR(0x1B, _PM_breakISR); + setISR(0x23, _PM_ctrlCISR); + + /* Hook the real mode vectors for these handlers, as these are not + * normally reflected by the DPMI server up to protected mode + */ + _PM_ctrlBPtr = PM_allocRealSeg(sizeof(ctrlHandler)*2, &rseg, &roff); + memcpy(_PM_ctrlBPtr,ctrlHandler,sizeof(ctrlHandler)); + memcpy(_PM_ctrlBPtr+sizeof(ctrlHandler),ctrlHandler,sizeof(ctrlHandler)); + _PM_ctrlCPtr = _PM_ctrlBPtr + sizeof(ctrlHandler); + _PM_setRMvect(0x1B,((long)rseg << 16) | (roff+4)); + _PM_setRMvect(0x23,((long)rseg << 16) | (roff+sizeof(ctrlHandler)+4)); +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak.sel) { + restoreISR(0x1B, _PM_prevBreak, prevRealBreak); + restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); + _PM_prevBreak.sel = 0; + _PM_breakHandler = NULL; + PM_freeRealSeg(_PM_ctrlBPtr); + } +} + +/* Real mode Critical Error handler. This handler simply saves the AX and + * DI values in the real mode code segment and exits. We save the location + * of this flag in real mode memory so that both the real mode and + * protected mode code will be modifying the same flags. + */ + +static uchar criticalHandler[] = { + 0x00,0x00, /* axCode */ + 0x00,0x00, /* diCode */ + 0x2E,0xA3,0x00,0x00, /* mov [cs:axCode],ax */ + 0x2E,0x89,0x3E,0x02,0x00, /* mov [cs:diCode],di */ + 0xB8,0x03,0x00, /* mov ax,3 */ + 0xCF, /* iretf */ + }; + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ + uint rseg,roff; + + getISR(0x24, &_PM_prevCritical, &prevRealCritical); + _PM_critHandler = ch; + setISR(0x24, _PM_criticalISR); + + /* Hook the real mode vector, as this is not normally reflected by the + * DPMI server up to protected mode. + */ + _PM_critPtr = PM_allocRealSeg(sizeof(criticalHandler)*2, &rseg, &roff); + memcpy(_PM_critPtr,criticalHandler,sizeof(criticalHandler)); + _PM_setRMvect(0x24,((long)rseg << 16) | (roff+4)); +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical.sel) { + restoreISR(0x24, _PM_prevCritical, prevRealCritical); + PM_freeRealSeg(_PM_critPtr); + _PM_prevCritical.sel = 0; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); +/*AM: causes minor glitch with */ +/*AM: older versions pmEasy which don't allow DPMI 06 on */ +/*AM: Code selector 0x0C -- assume base is 0 which it should be. */ + return DPMI_lockLinearPages((uint)p,len); +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_unlockLinearPages((uint)p,len); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c new file mode 100644 index 0000000..579ef2c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c new file mode 100644 index 0000000..7941192 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c @@ -0,0 +1,115 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development +* +* Description: OS specific implementation for the Zen Timer functions. +* LZTimer not supported for smx (as needed for i486 processors), only +* ULZTimer is supported at this time. +* +****************************************************************************/ + +/*---------------------------- Global smx variables -----------------------*/ + +extern ulong _cdecl etime; /* elapsed time */ +extern ulong _cdecl xticks_per_second(void); + +/*----------------------------- Implementation ----------------------------*/ + +/* External assembler functions */ + +void _ASMAPI LZ_disable(void); +void _ASMAPI LZ_enable(void); + + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +} + +ulong reterr(void) +{ + PM_fatalError("Zen Timer not supported for smx."); + return(0); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOn(tm) PM_fatalError("Zen Timer not supported for smx.") + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerLap(tm) reterr() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) PM_fatalError("Zen Timer not supported for smx.") + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerCount(tm) reterr() + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as seconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION (ulong)(1000000/xticks_per_second()) + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the smx timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + ulong ticks; + LZ_disable(); /* Turn of interrupts */ + ticks = etime; + LZ_enable(); /* Turn on interrupts again */ + return ticks; +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ + if (finish < start) + finish += xticks_per_second() * 3600 *24; /* Number of ticks in 24 hours */ + return finish - start; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c new file mode 100644 index 0000000..0615e90 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c @@ -0,0 +1,79 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: Module to implement OS specific services to measure the +* CPU frequency. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Increase the thread priority to maximum, if possible. +****************************************************************************/ +static int SetMaxThreadPriority(void) +{ + /* TODO: If you have thread priorities, increase it to maximum for the */ + /* thread for timing the CPU frequency. */ + return oldPriority; +} + +/**************************************************************************** +REMARKS: +Restore the original thread priority. +****************************************************************************/ +static void RestoreThreadPriority( + int priority) +{ + /* TODO: Restore the original thread priority on exit. */ +} + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + /* TODO: Return the frequency of the counter in here. You should try to */ + /* normalise this value to be around 100,000 ticks per second. */ + freq->low = 0; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. + +TODO: Implement this to read the counter. It should be done as a macro + for accuracy. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + (t)->low = 0; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/event.c b/board/MAI/bios_emulator/scitech/src/pm/stub/event.c new file mode 100644 index 0000000..204c492 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/event.c @@ -0,0 +1,199 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: **** implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under non-DOS systems */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + /* TODO: Implement this for your OS! */ +} + +/**************************************************************************** +REMARKS: +Pumps all messages in the application message queue into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + /* TODO: The purpose of this function is to read all keyboard and mouse */ + /* events from the OS specific event queue, translate them and post */ + /* them into the SciTech event queue. */ + /* */ + /* NOTE: There are a couple of important things that this function must */ + /* take care of: */ + /* */ + /* 1. Support for KEYDOWN, KEYREPEAT and KEYUP is required. */ + /* */ + /* 2. Support for reading hardware scan code as well as ASCII */ + /* translated values is required. Games use the scan codes rather */ + /* than ASCII values. Scan codes go into the high order byte of the */ + /* keyboard message field. */ + /* */ + /* 3. Support for at least reading mouse motion data (mickeys) from the */ + /* mouse is required. Using the mickey values, we can then translate */ + /* to mouse cursor coordinates scaled to the range of the current */ + /* graphics display mode. Mouse values are scaled based on the */ + /* global 'rangeX' and 'rangeY'. */ + /* */ + /* 4. Support for a timestamp for the events is required, which is */ + /* defined as the number of milliseconds since some event (usually */ + /* system startup). This is the timestamp when the event occurred */ + /* (ie: at interrupt time) not when it was stuff into the SciTech */ + /* event queue. */ + /* */ + /* 5. Support for mouse double click events. If the OS has a native */ + /* mechanism to determine this, it should be used. Otherwise the */ + /* time stamp information will be used by the generic event code */ + /* to generate double click events. */ +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* TODO: Do any OS specific initialisation here */ + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* TODO: Do any OS specific cleanup in here */ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h new file mode 100644 index 0000000..1395cbc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h @@ -0,0 +1,33 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +/* TODO: This is where you include OS specific headers for the event handling */ +/* library. You may leave this empty if you have no OS specific headers */ +/* to include. */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c b/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c new file mode 100644 index 0000000..5f278c3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c @@ -0,0 +1,980 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include +#include +#include + +/* TODO: Include any OS specific headers here! */ + +/*--------------------------- Global variables ----------------------------*/ + +/* TODO: If you support access to the BIOS, the following VESABuf globals */ +/* keep track of a single VESA transfer buffer. If you don't support */ +/* access to the BIOS, remove these variables. */ + +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the PM library. +****************************************************************************/ +void PMAPI PM_init(void) +{ + /* TODO: Do any initialisation in here. This includes getting IOPL */ + /* access for the process calling PM_init. This will get called */ + /* more than once. */ + + /* TODO: If you support the supplied MTRR register stuff (you need to */ + /* be at ring 0 for this!), you should initialise it in here. */ + +/* MTRR_init(); */ +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + /* TODO: Change this to return the define for your OS from drvlib/os.h */ + return _OS_MYOS; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier (always PM_386 for protected mode) +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ return PM_386; } + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash( + char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '/') { + s[pos] = '/'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Report a fatal error condition and halt the program. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + /* TODO: If you are running in a GUI environment without a console, */ + /* this needs to be changed to bring up a fatal error message */ + /* box and terminate the program. */ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + exit(1); +} + +/**************************************************************************** +REMARKS: +Exit handler to kill the VESA transfer buffer. +****************************************************************************/ +static void ExitVBEBuf(void) +{ + /* TODO: If you do not have BIOS access, remove this function. */ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +/**************************************************************************** +REMARKS: +Allocate the real mode VESA transfer buffer for communicating with the BIOS. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + /* TODO: If you do not have BIOS access, simply delete the guts of */ + /* this function and return NULL. */ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + /* TODO: This function checks if a key is available to be read. This */ + /* should be implemented, but is mostly used by the test programs */ + /* these days. */ + return true; +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + /* TODO: This returns the ASCII code of the key pressed. This */ + /* should be implemented, but is mostly used by the test programs */ + /* these days. */ + return 0xD; +} + +/**************************************************************************** +REMARKS: +Open a fullscreen console mode for output. +****************************************************************************/ +int PMAPI PM_openConsole(void) +{ + /* TODO: Opens up a fullscreen console for graphics output. If your */ + /* console does not have graphics/text modes, this can be left */ + /* empty. The main purpose of this is to disable console switching */ + /* when in graphics modes if you can switch away from fullscreen */ + /* consoles (if you want to allow switching, this can be done */ + /* elsewhere with a full save/restore state of the graphics mode). */ + return 0; +} + +/**************************************************************************** +REMARKS: +Return the size of the state buffer used to save the console state. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + /* TODO: Returns the size of the console state buffer used to save the */ + /* state of the console before going into graphics mode. This is */ + /* used to restore the console back to normal when we are done. */ + return 1; +} + +/**************************************************************************** +REMARKS: +Save the state of the console into the state buffer. +****************************************************************************/ +void PMAPI PM_saveConsoleState( + void *stateBuf, + int console_id) +{ + /* TODO: Saves the state of the console into the state buffer. This is */ + /* used to restore the console back to normal when we are done. */ + /* We will always restore 80x25 text mode after being in graphics */ + /* mode, so if restoring text mode is all you need to do this can */ + /* be left empty. */ +} + +/**************************************************************************** +REMARKS: +Restore the state of the console from the state buffer. +****************************************************************************/ +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + int console_id) +{ + /* TODO: Restore the state of the console from the state buffer. This is */ + /* used to restore the console back to normal when we are done. */ + /* We will always restore 80x25 text mode after being in graphics */ + /* mode, so if restoring text mode is all you need to do this can */ + /* be left empty. */ +} + +/**************************************************************************** +REMARKS: +Close the console and return to non-fullscreen console mode. +****************************************************************************/ +void PMAPI PM_closeConsole( + int console_id) +{ + /* TODO: Close the console when we are done, going back to text mode. */ +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PM_setOSCursorLocation( + int x, + int y) +{ + /* TODO: Set the OS console cursor location to the new value. This is */ + /* generally used for new OS ports (used mostly for DOS). */ +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PM_setOSScreenWidth( + int width, + int height) +{ + /* TODO: Set the OS console screen width. This is generally unused for */ + /* new OS ports. */ +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + /* TODO: Install a real time clock interrupt handler. Normally this */ + /* will not be supported from most OS'es in user land, so an */ + /* alternative mechanism is needed to enable software stereo. */ + /* Hence leave this unimplemented unless you have a high priority */ + /* mechanism to call the 32-bit callback when the real time clock */ + /* interrupt fires. */ + return false; +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + /* TODO: Set the real time clock interrupt frequency. Used for stereo */ + /* LC shutter glasses when doing software stereo. Usually sets */ + /* the frequency to around 2048 Hz. */ +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Restores the real time clock handler. */ +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + /* TODO: Return the boot drive letter for the OS. Normally this is 'c' */ + /* for DOS based OS'es and '/' for Unices. */ + return '/'; +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files (legacy and not used). +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + return PM_getNucleusConfigPath(); +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + /* TODO: Change this to the default path to Nucleus driver files. The */ + /* following is the default for Unices. */ + char *env = getenv("NUCLEUS_PATH"); + return env ? env : "/usr/lib/nucleus"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + /* TODO: Return a unique ID for the machine. If a unique ID is not */ + /* available, return the machine name. */ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + /* TODO: Return the network machine name for the machine. */ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + /* TODO: This returns a pointer to the real mode BIOS data area. If you */ + /* do not support BIOS access, you can simply return NULL here. */ + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + 0x400); +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + static void *bankPtr; + if (!bankPtr) + bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + return bankPtr; +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + /* TODO: This function maps a physical memory address to a linear */ + /* address in the address space of the calling process. */ + + /* NOTE: This function *must* be able to handle any phsyical base */ + /* address, and hence you will have to handle rounding of */ + /* the physical base address to a page boundary (ie: 4Kb on */ + /* x86 CPU's) to be able to properly map in the memory */ + /* region. */ + + /* NOTE: If possible the isCached bit should be used to ensure that */ + /* the PCD (Page Cache Disable) and PWT (Page Write Through) */ + /* bits are set to disable caching for a memory mapping used */ + /* for MMIO register access. We also disable caching using */ + /* the MTRR registers for Pentium Pro and later chipsets so if */ + /* MTRR support is enabled for your OS then you can safely ignore */ + /* the isCached flag and always enable caching in the page */ + /* tables. */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* TODO: This function will free a physical memory mapping previously */ + /* allocated with PM_mapPhysicalAddr() if at all possible. If */ + /* you can't free physical memory mappings, simply do nothing. */ +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* TODO: Put the process to sleep for milliseconds */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of (unnamed) shared memory. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + /* TODO: This is used to allocate memory that is shared between process */ + /* that all access the common Nucleus drivers via a common display */ + /* driver DLL. If your OS does not support shared memory (or if */ + /* the display driver does not need to allocate shared memory */ + /* for each process address space), this should just call PM_malloc. */ + return PM_malloc(size); +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory. +****************************************************************************/ +void PMAPI PM_freeShared( + void *ptr) +{ + /* TODO: Free the shared memory block. This will be called in the context */ + /* of the original calling process that allocated the shared */ + /* memory with PM_mallocShared. Simply call PM_free if you do not */ + /* need this. */ + PM_free(ptr); +} + +/**************************************************************************** +REMARKS: +Map a linear memory address to the calling process address space. The +address will have been allocated in another process using the +PM_mapPhysicalAddr function. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + /* TODO: This function is used to map a physical memory mapping */ + /* previously allocated with PM_mapPhysicalAddr into the */ + /* address space of the calling process. If the memory mapping */ + /* allocated by PM_mapPhysicalAddr is global to all processes, */ + /* simply return the pointer. */ + + /* NOTE: This function must also handle rounding to page boundaries, */ + /* since this function is used to map in shared memory buffers */ + /* allocated with PM_mapPhysicalAddr(). Hence if you aligned */ + /* the physical address above, then you also need to do it here. */ + return base; +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + /* TODO: This function maps a real mode memory pointer into the */ + /* calling processes address space as a 32-bit near pointer. If */ + /* you do not support BIOS access, simply return NULL here. */ + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF); + return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + /* TODO: This function allocates a block of real mode memory for the */ + /* calling process used to communicate with real mode BIOS */ + /* functions. If you do not support BIOS access, simply return */ + /* NULL here. */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* TODO: Frees a previously allocated real mode memory block. If you */ + /* do not support BIOS access, this function should be empty. */ +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + /* TODO: This function calls the real mode BIOS using the passed in */ + /* register structure. If you do not support real mode BIOS */ + /* access, this function should be empty. */ +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + /* TODO: This function calls the real mode BIOS using the passed in */ + /* register structure. If you do not support real mode BIOS */ + /* access, this function should return 0. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + /* TODO: This function calls the real mode BIOS using the passed in */ + /* register structure. If you do not support real mode BIOS */ + /* access, this function should return 0. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Call a real mode far function. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *in, + RMSREGS *sregs) +{ + /* TODO: This function calls a real mode far function with a far call. */ + /* If you do not support BIOS access, this function should be */ + /* empty. */ +} + +/**************************************************************************** +REMARKS: +Return the amount of available memory. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + /* TODO: Report the amount of available memory, both the amount of */ + /* physical memory left and the amount of virtual memory left. */ + /* If the OS does not provide these services, report 0's. */ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of locked, physical memory for DMA operations. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + /* TODO: Allocate a block of locked, physical memory of the specified */ + /* size. This is used for bus master operations. If this is not */ + /* supported by the OS, return NULL and bus mastering will not */ + /* be used. */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + /* TODO: Free a memory block allocated with PM_allocLockedMem. */ +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + RMREGS regs; + + /* TODO: This does a bank switch function by calling the real mode */ + /* VESA BIOS. If you do not support BIOS access, this function should */ + /* be empty. */ + regs.x.ax = 0x4F05; + regs.x.bx = 0x0000; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + RMREGS regs; + + /* TODO: This does a bank switch function by calling the real mode */ + /* VESA BIOS. If you do not support BIOS access, this function should */ + /* be empty. */ + regs.x.ax = 0x4F05; + regs.x.bx = 0x0000; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); + regs.x.ax = 0x4F05; + regs.x.bx = 0x0001; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + RMREGS regs; + + /* TODO: This changes the display start address by calling the real mode */ + /* VESA BIOS. If you do not support BIOS access, this function */ + /* should be empty. */ + regs.x.ax = 0x4F07; + regs.x.bx = waitVRT; + regs.x.cx = x; + regs.x.dx = y; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Enable write combining for the memory region. +****************************************************************************/ +ibool PMAPI PM_enableWriteCombine( + ulong base, + ulong length, + uint type) +{ + /* TODO: This function should enable Pentium Pro and Pentium II MTRR */ + /* write combining for the passed in physical memory base address */ + /* and length. Normally this is done via calls to an OS specific */ + /* device driver as this can only be done at ring 0. */ + /* */ + /* NOTE: This is a *very* important function to implement! If you do */ + /* not implement, graphics performance on the latest Intel chips */ + /* will be severly impaired. For sample code that can be used */ + /* directly in a ring 0 device driver, see the MSDOS implementation */ + /* which includes assembler code to do this directly (if the */ + /* program is running at ring 0). */ + return false; +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS) +{ + /* TODO: This function is used to run the BIOS POST code on a secondary */ + /* controller to initialise it for use. This is not necessary */ + /* for multi-controller operation, but it will make it a lot */ + /* more convenicent for end users (otherwise they have to boot */ + /* the system once with the secondary controller as primary, and */ + /* then boot with both controllers installed). */ + /* */ + /* Even if you don't support full BIOS access, it would be */ + /* adviseable to be able to POST the secondary controllers in the */ + /* system using this function as a minimum requirement. Some */ + /* graphics hardware has registers that contain values that only */ + /* the BIOS knows about, which makes bring up a card from cold */ + /* reset difficult if the BIOS has not POST'ed it. */ + return false; +} + +/**************************************************************************** +REMARKS: +Load an OS specific shared library or DLL. If the OS does not support +shared libraries, simply return NULL. +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: This function should load a native shared library from disk */ + /* given the path to the library. */ + (void)szDLLName; + return NULL; +} + +/**************************************************************************** +REMARKS: +Get the address of a named procedure from a shared library. +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: This function should return the address of a named procedure */ + /* from a native shared library. */ + (void)hModule; + (void)szProcName; + return NULL; +} + +/**************************************************************************** +REMARKS: +Unload a shared library. +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: This function free a previously loaded native shared library. */ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Enable requested I/O privledge level (usually only to set to a value of +3, and then restore it back again). If the OS is protected this function +must be implemented in order to enable I/O port access for ring 3 +applications. The function should return the IOPL level active before +the switch occurred so it can be properly restored. +****************************************************************************/ +int PMAPI PM_setIOPL( + int level) +{ + /* TODO: This function should enable IOPL for the task (if IOPL is */ + /* not always enabled for the app through some other means). */ + return level; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + if (drive == 3) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + (void)drive; + getcwd(dir,len); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Set the file attributes for a file */ + (void)filename; + (void)attrib; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return mkdir(filename) == 0; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return rmdir(filename) == 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c new file mode 100644 index 0000000..579ef2c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c new file mode 100644 index 0000000..820e292 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c @@ -0,0 +1,111 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ + /* TODO: Do any specific internal initialisation in here */ +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOn( + LZTimerObject *tm) +{ + /* TODO: Start the Zen Timer counting. This should be a macro if */ + /* possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + /* TODO: Compute the lap time between the current time and when the */ + /* timer was started. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Stop the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOff( + LZTimerObject *tm) +{ + /* TODO: Stop the timer counting. Should be a macro if possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time in microseconds between start and end timings. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + /* TODO: Compute the elapsed time and return it. Always microseconds. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Read the Long Period timer from the OS +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + /* TODO: Read the long period timer from the OS. The resolution of this */ + /* timer should be around 1/20 of a second for timing long */ + /* periods if possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c b/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c new file mode 100644 index 0000000..ba90262 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c @@ -0,0 +1,90 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* control C/break interrupt handler. Note that this +* alternate version does not work with all extenders. +* +* Functions tested: PM_installAltBreakHandler() +* PM_restoreBreakHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile int breakHit = false; +volatile int ctrlCHit = false; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI breakHandler(uint bHit) +{ + if (bHit) + breakHit = true; + else + ctrlCHit = true; +} + +int main(void) +{ + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + PM_installAltBreakHandler(breakHandler); + printf("Control C/Break interrupt handler installed\n"); + while (1) { + if (ctrlCHit) { + printf("Code termimated with Ctrl-C.\n"); + break; + } + if (breakHit) { + printf("Code termimated with Ctrl-Break.\n"); + break; + } + if (PM_kbhit() && PM_getch() == 0x1B) { + printf("No break code detected!\n"); + break; + } + printf("Hit Ctrl-C or Ctrl-Break to exit!\n"); + } + + PM_restoreBreakHandler(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c b/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c new file mode 100644 index 0000000..e137307 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c @@ -0,0 +1,85 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* critical error handler. +* +* Functions tested: PM_installCriticalHandler() +* PM_criticalError() +* PM_restoreCriticalHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile uint criticalError = false; +volatile uint axValue; +volatile uint diValue; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +uint PMAPI criticalHandler(uint axVal,uint diVal) +{ + criticalError = true; + axValue = axVal; + diValue = diVal; + return 3; /* Tell MS-DOS to fail the operation */ +} + +int main(void) +{ + FILE *f; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + PM_installAltCriticalHandler(criticalHandler); + printf("Critical Error handler installed - trying to read from A: drive...\n"); + f = fopen("a:\bog.bog","rb"); + if (f) fclose(f); + if (criticalError) { + printf("Critical error occured on INT 21h function %02X!\n", + axValue >> 8); + } + else + printf("Critical error was not caught!\n"); + PM_restoreCriticalHandler(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c b/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c new file mode 100644 index 0000000..5fa3382 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c @@ -0,0 +1,92 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to manipulate the +* BIOS data area from protected mode using the PM +* library. Compile and link with the appropriate command +* line for your DOS extender. +* +* Functions tested: PM_getBIOSSelector() +* PM_getLong() +* PM_getByte() +* PM_getWord() +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +/* Macros to obtain values from the BIOS data area */ + +#define TICKS() PM_getLong(bios+0x6C) +#define KB_STAT PM_getByte(bios+0x17) +#define KB_HEAD PM_getWord(bios+0x1A) +#define KB_TAIL PM_getWord(bios+0x1C) + +/* Macros for working with the keyboard buffer */ + +#define KB_HIT() (KB_HEAD != KB_TAIL) +#define CTRL() (KB_STAT & 4) +#define SHIFT() (KB_STAT & 2) +#define ESC 0x1B + +/* Selector for BIOS data area */ + +uchar *bios; + +int main(void) +{ + int c,done = 0; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + bios = PM_getBIOSPointer(); + printf("Hit any key to test, Ctrl-Shift-Esc to quit\n"); + while (!done) { + if (KB_HIT()) { + c = PM_getch(); + if (c == 0) PM_getch(); + printf("TIME=%-8lX ST=%02X CHAR=%02X ", TICKS(), KB_STAT, c); + printf("\n"); + if ((c == ESC) && SHIFT() && CTRL())/* Ctrl-Shift-Esc */ + break; + } + } + + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/block.c b/board/MAI/bios_emulator/scitech/src/pm/tests/block.c new file mode 100644 index 0000000..15d503c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/block.c @@ -0,0 +1,69 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Test program for the PM_blockUntilTimeout function. +* +****************************************************************************/ + +#include +#include "pmapi.h" + +#define DELAY_MSECS 1100 +#define LOOPS 5 + +/*-------------------------- Implementation -------------------------------*/ + +/* The following routine takes a long count in microseconds and outputs + * a string representing the count in seconds. It could be modified to + * return a pointer to a static string representing the count rather + * than printing it out. + */ + +void ReportTime(ulong count) +{ + ulong secs; + + secs = count / 1000000L; + count = count - secs * 1000000L; + printf("Time taken: %lu.%06lu seconds\n",secs,count); +} + +int main(void) +{ + int i; + + printf("Detecting processor information ..."); + fflush(stdout); + printf("\n\n%s\n", CPU_getProcessorName()); + ZTimerInit(); + LZTimerOn(); + for (i = 0; i < LOOPS; i++) { + PM_blockUntilTimeout(DELAY_MSECS); + ReportTime(LZTimerLap()); + } + LZTimerOff(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c b/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c new file mode 100644 index 0000000..10b6446 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c @@ -0,0 +1,78 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* control C/break interrupt handler. +* +* Functions tested: PM_installBreakHandler() +* PM_ctrlCHit() +* PM_ctrlBreakHit() +* PM_restoreBreakHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +int main(void) +{ + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + PM_installBreakHandler(); + printf("Control C/Break interrupt handler installed\n"); + while (1) { + if (PM_ctrlCHit(1)) { + printf("Code termimated with Ctrl-C.\n"); + break; + } + if (PM_ctrlBreakHit(1)) { + printf("Code termimated with Ctrl-Break.\n"); + break; + } + if (PM_kbhit() && PM_getch() == 0x1B) { + printf("No break code detected!\n"); + break; + } + printf("Hit Ctrl-C or Ctrl-Break to exit!\n"); + } + + PM_restoreBreakHandler(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c b/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c new file mode 100644 index 0000000..4d37cab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c @@ -0,0 +1,107 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to call a real mode +* procedure. We simply copy a terribly simple assembly +* language routine into a real mode block that we allocate, +* and then attempt to call the routine and verify that it +* was successful. +* +* Functions tested: PM_allocRealSeg() +* PM_freeRealSeg() +* PM_callRealMode() +* +****************************************************************************/ + +#include +#include +#include +#include "pmapi.h" + +/* Block of real mode code we will eventually call */ + +static unsigned char realModeCode[] = { + 0x93, /* xchg ax,bx */ + 0x87, 0xCA, /* xchg cx,dx */ + 0xCB /* retf */ + }; + +int main(void) +{ + RMREGS regs; + RMSREGS sregs; + uchar *p; + unsigned r_seg,r_off; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Allocate a the block of real mode memory */ + if ((p = PM_allocRealSeg(sizeof(realModeCode), &r_seg, &r_off)) == NULL) { + printf("Unable to allocate real mode memory!\n"); + exit(1); + } + + /* Copy the real mode code */ + memcpy(p,realModeCode,sizeof(realModeCode)); + + /* Now call the real mode code */ + regs.x.ax = 1; + regs.x.bx = 2; + regs.x.cx = 3; + regs.x.dx = 4; + regs.x.si = 5; + regs.x.di = 6; + sregs.es = 7; + sregs.ds = 8; + PM_callRealMode(r_seg,r_off,®s,&sregs); + if (regs.x.ax != 2 || regs.x.bx != 1 || regs.x.cx != 4 || regs.x.dx != 3 + || regs.x.si != 5 || regs.x.di != 6 || sregs.es != 7 + || sregs.ds != 8) { + printf("Real mode call failed!\n"); + printf("\n"); + printf("ax = %04X, bx = %04X, cx = %04X, dx = %04X\n", + regs.x.ax,regs.x.bx,regs.x.cx,regs.x.dx); + printf("si = %04X, di = %04X, es = %04X, ds = %04X\n", + regs.x.si,regs.x.di,sregs.es,sregs.ds); + } + else + printf("Real mode call succeeded!\n"); + + /* Free the memory we allocated */ + PM_freeRealSeg(p); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c b/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c new file mode 100644 index 0000000..5933ac9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c @@ -0,0 +1,100 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Main module for building checked builds of products with +* assertions and trace code. +* +****************************************************************************/ + +#include "scitech.h" +#include +#include +#include +#ifdef __WINDOWS__ +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#endif + +#ifdef CHECKED + +/*---------------------------- Global variables ---------------------------*/ + +#define LOGFILE "\\scitech.log" + +void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line) = _CHK_defaultFail; + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +DESCRIPTION: +Handles fatal error and warning conditions for checked builds. + +HEADER: +scitech.h + +REMARKS: +This function is called whenever an inline check or warning fails in any +of the SciTech runtime libraries. Warning conditions simply cause the +condition to be logged to the log file and send to the system debugger +under Window. Fatal error conditions do all of the above, and then +terminate the program with a fatal error conditions. + +This handler may be overriden by the user code if necessary to replace it +with a different handler (the MGL for instance overrides this and replaces +it with a handler that does an MGL_exit() before terminating the application +so that it will clean up correctly. +****************************************************************************/ +void _CHK_defaultFail( + int fatal, + const char *msg, + const char *cond, + const char *file, + int line) +{ + char buf[256]; + FILE *log = fopen(LOGFILE, "at+"); + + sprintf(buf,msg,cond,file,line); + if (log) { + fputs(buf,log); + fflush(log); + fclose(log); +#ifdef __WINDOWS__ + OutputDebugStr(buf); +#endif + } + if (fatal) { +#ifdef __WINDOWS__ + MessageBox(NULL, buf,"Fatal Error!",MB_ICONEXCLAMATION); +#else + fputs(buf,stderr); +#endif + exit(-1); + } +} + +#endif /* CHECKED */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c b/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c new file mode 100644 index 0000000..30e5dd3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c @@ -0,0 +1,46 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Test program for the CPU detection code. +* +****************************************************************************/ + +#include "ztimer.h" +#include "pmapi.h" +#include +#include + +/*----------------------------- Implementation ----------------------------*/ + +int main(void) +{ + printf("Detecting processor information ..."); + fflush(stdout); + printf("\n\n%s\n", CPU_getProcessorName()); + if (CPU_haveRDTSC()) + printf("\nProcessor supports Read Time Stamp Counter performance timer.\n"); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c b/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c new file mode 100644 index 0000000..60f1251 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c @@ -0,0 +1,70 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* critical error handler. +* +* Functions tested: PM_installAltCriticalHandler() +* PM_restoreCriticalHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +int main(void) +{ + FILE *f; + int axcode,dicode; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + PM_installCriticalHandler(); + printf("Critical Error handler installed - trying to read from A: drive...\n"); + f = fopen("a:\bog.bog","rb"); + if (f) fclose(f); + if (PM_criticalError(&axcode,&dicode,1)) { + printf("Critical error occured on INT 21h function %02X!\n", + axcode >> 8); + } + else printf("Critical error was not caught!\n"); + PM_restoreCriticalHandler(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c b/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c new file mode 100644 index 0000000..06c2180 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c @@ -0,0 +1,501 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Test program to test out the cross platform event handling +* library. +* +****************************************************************************/ + +#include +#include +#include +#include "pmapi.h" +#include "event.h" + +/* Translation table for key codes */ + +typedef struct { + int code; + char *name; + } KeyEntry; + +KeyEntry ASCIICodes[] = { + {ASCII_ctrlA ,"ASCII_ctrlA"}, + {ASCII_ctrlB ,"ASCII_ctrlB"}, + {ASCII_ctrlC ,"ASCII_ctrlC"}, + {ASCII_ctrlD ,"ASCII_ctrlD"}, + {ASCII_ctrlE ,"ASCII_ctrlE"}, + {ASCII_ctrlF ,"ASCII_ctrlF"}, + {ASCII_ctrlG ,"ASCII_ctrlG"}, + {ASCII_backspace ,"ASCII_backspace"}, + {ASCII_ctrlH ,"ASCII_ctrlH"}, + {ASCII_tab ,"ASCII_tab"}, + {ASCII_ctrlI ,"ASCII_ctrlI"}, + {ASCII_ctrlJ ,"ASCII_ctrlJ"}, + {ASCII_ctrlK ,"ASCII_ctrlK"}, + {ASCII_ctrlL ,"ASCII_ctrlL"}, + {ASCII_enter ,"ASCII_enter"}, + {ASCII_ctrlM ,"ASCII_ctrlM"}, + {ASCII_ctrlN ,"ASCII_ctrlN"}, + {ASCII_ctrlO ,"ASCII_ctrlO"}, + {ASCII_ctrlP ,"ASCII_ctrlP"}, + {ASCII_ctrlQ ,"ASCII_ctrlQ"}, + {ASCII_ctrlR ,"ASCII_ctrlR"}, + {ASCII_ctrlS ,"ASCII_ctrlS"}, + {ASCII_ctrlT ,"ASCII_ctrlT"}, + {ASCII_ctrlU ,"ASCII_ctrlU"}, + {ASCII_ctrlV ,"ASCII_ctrlV"}, + {ASCII_ctrlW ,"ASCII_ctrlW"}, + {ASCII_ctrlX ,"ASCII_ctrlX"}, + {ASCII_ctrlY ,"ASCII_ctrlY"}, + {ASCII_ctrlZ ,"ASCII_ctrlZ"}, + {ASCII_esc ,"ASCII_esc"}, + {ASCII_space ,"ASCII_space"}, + {ASCII_exclamation ,"ASCII_exclamation"}, + {ASCII_quote ,"ASCII_quote"}, + {ASCII_pound ,"ASCII_pound"}, + {ASCII_dollar ,"ASCII_dollar"}, + {ASCII_percent ,"ASCII_percent"}, + {ASCII_ampersand ,"ASCII_ampersand"}, + {ASCII_apostrophe ,"ASCII_apostrophe"}, + {ASCII_leftBrace ,"ASCII_leftBrace"}, + {ASCII_rightBrace ,"ASCII_rightBrace"}, + {ASCII_times ,"ASCII_times"}, + {ASCII_plus ,"ASCII_plus"}, + {ASCII_comma ,"ASCII_comma"}, + {ASCII_minus ,"ASCII_minus"}, + {ASCII_period ,"ASCII_period"}, + {ASCII_divide ,"ASCII_divide"}, + {ASCII_0 ,"ASCII_0"}, + {ASCII_1 ,"ASCII_1"}, + {ASCII_2 ,"ASCII_2"}, + {ASCII_3 ,"ASCII_3"}, + {ASCII_4 ,"ASCII_4"}, + {ASCII_5 ,"ASCII_5"}, + {ASCII_6 ,"ASCII_6"}, + {ASCII_7 ,"ASCII_7"}, + {ASCII_8 ,"ASCII_8"}, + {ASCII_9 ,"ASCII_9"}, + {ASCII_colon ,"ASCII_colon"}, + {ASCII_semicolon ,"ASCII_semicolon"}, + {ASCII_lessThan ,"ASCII_lessThan"}, + {ASCII_equals ,"ASCII_equals"}, + {ASCII_greaterThan ,"ASCII_greaterThan"}, + {ASCII_question ,"ASCII_question"}, + {ASCII_at ,"ASCII_at"}, + {ASCII_A ,"ASCII_A"}, + {ASCII_B ,"ASCII_B"}, + {ASCII_C ,"ASCII_C"}, + {ASCII_D ,"ASCII_D"}, + {ASCII_E ,"ASCII_E"}, + {ASCII_F ,"ASCII_F"}, + {ASCII_G ,"ASCII_G"}, + {ASCII_H ,"ASCII_H"}, + {ASCII_I ,"ASCII_I"}, + {ASCII_J ,"ASCII_J"}, + {ASCII_K ,"ASCII_K"}, + {ASCII_L ,"ASCII_L"}, + {ASCII_M ,"ASCII_M"}, + {ASCII_N ,"ASCII_N"}, + {ASCII_O ,"ASCII_O"}, + {ASCII_P ,"ASCII_P"}, + {ASCII_Q ,"ASCII_Q"}, + {ASCII_R ,"ASCII_R"}, + {ASCII_S ,"ASCII_S"}, + {ASCII_T ,"ASCII_T"}, + {ASCII_U ,"ASCII_U"}, + {ASCII_V ,"ASCII_V"}, + {ASCII_W ,"ASCII_W"}, + {ASCII_X ,"ASCII_X"}, + {ASCII_Y ,"ASCII_Y"}, + {ASCII_Z ,"ASCII_Z"}, + {ASCII_leftSquareBrace ,"ASCII_leftSquareBrace"}, + {ASCII_backSlash ,"ASCII_backSlash"}, + {ASCII_rightSquareBrace ,"ASCII_rightSquareBrace"}, + {ASCII_caret ,"ASCII_caret"}, + {ASCII_underscore ,"ASCII_underscore"}, + {ASCII_leftApostrophe ,"ASCII_leftApostrophe"}, + {ASCII_a ,"ASCII_a"}, + {ASCII_b ,"ASCII_b"}, + {ASCII_c ,"ASCII_c"}, + {ASCII_d ,"ASCII_d"}, + {ASCII_e ,"ASCII_e"}, + {ASCII_f ,"ASCII_f"}, + {ASCII_g ,"ASCII_g"}, + {ASCII_h ,"ASCII_h"}, + {ASCII_i ,"ASCII_i"}, + {ASCII_j ,"ASCII_j"}, + {ASCII_k ,"ASCII_k"}, + {ASCII_l ,"ASCII_l"}, + {ASCII_m ,"ASCII_m"}, + {ASCII_n ,"ASCII_n"}, + {ASCII_o ,"ASCII_o"}, + {ASCII_p ,"ASCII_p"}, + {ASCII_q ,"ASCII_q"}, + {ASCII_r ,"ASCII_r"}, + {ASCII_s ,"ASCII_s"}, + {ASCII_t ,"ASCII_t"}, + {ASCII_u ,"ASCII_u"}, + {ASCII_v ,"ASCII_v"}, + {ASCII_w ,"ASCII_w"}, + {ASCII_x ,"ASCII_x"}, + {ASCII_y ,"ASCII_y"}, + {ASCII_z ,"ASCII_z"}, + {ASCII_leftCurlyBrace ,"ASCII_leftCurlyBrace"}, + {ASCII_verticalBar ,"ASCII_verticalBar"}, + {ASCII_rightCurlyBrace ,"ASCII_rightCurlyBrace"}, + {ASCII_tilde ,"ASCII_tilde"}, + {0 ,"ASCII_unknown"}, + }; + +KeyEntry ScanCodes[] = { + {KB_padEnter ,"KB_padEnter"}, + {KB_padMinus ,"KB_padMinus"}, + {KB_padPlus ,"KB_padPlus"}, + {KB_padTimes ,"KB_padTimes"}, + {KB_padDivide ,"KB_padDivide"}, + {KB_padLeft ,"KB_padLeft"}, + {KB_padRight ,"KB_padRight"}, + {KB_padUp ,"KB_padUp"}, + {KB_padDown ,"KB_padDown"}, + {KB_padInsert ,"KB_padInsert"}, + {KB_padDelete ,"KB_padDelete"}, + {KB_padHome ,"KB_padHome"}, + {KB_padEnd ,"KB_padEnd"}, + {KB_padPageUp ,"KB_padPageUp"}, + {KB_padPageDown ,"KB_padPageDown"}, + {KB_padCenter ,"KB_padCenter"}, + {KB_F1 ,"KB_F1"}, + {KB_F2 ,"KB_F2"}, + {KB_F3 ,"KB_F3"}, + {KB_F4 ,"KB_F4"}, + {KB_F5 ,"KB_F5"}, + {KB_F6 ,"KB_F6"}, + {KB_F7 ,"KB_F7"}, + {KB_F8 ,"KB_F8"}, + {KB_F9 ,"KB_F9"}, + {KB_F10 ,"KB_F10"}, + {KB_F11 ,"KB_F11"}, + {KB_F12 ,"KB_F12"}, + {KB_left ,"KB_left"}, + {KB_right ,"KB_right"}, + {KB_up ,"KB_up"}, + {KB_down ,"KB_down"}, + {KB_insert ,"KB_insert"}, + {KB_delete ,"KB_delete"}, + {KB_home ,"KB_home"}, + {KB_end ,"KB_end"}, + {KB_pageUp ,"KB_pageUp"}, + {KB_pageDown ,"KB_pageDown"}, + {KB_capsLock ,"KB_capsLock"}, + {KB_numLock ,"KB_numLock"}, + {KB_scrollLock ,"KB_scrollLock"}, + {KB_leftShift ,"KB_leftShift"}, + {KB_rightShift ,"KB_rightShift"}, + {KB_leftCtrl ,"KB_leftCtrl"}, + {KB_rightCtrl ,"KB_rightCtrl"}, + {KB_leftAlt ,"KB_leftAlt"}, + {KB_rightAlt ,"KB_rightAlt"}, + {KB_leftWindows ,"KB_leftWindows"}, + {KB_rightWindows ,"KB_rightWindows"}, + {KB_menu ,"KB_menu"}, + {KB_sysReq ,"KB_sysReq"}, + {KB_esc ,"KB_esc"}, + {KB_1 ,"KB_1"}, + {KB_2 ,"KB_2"}, + {KB_3 ,"KB_3"}, + {KB_4 ,"KB_4"}, + {KB_5 ,"KB_5"}, + {KB_6 ,"KB_6"}, + {KB_7 ,"KB_7"}, + {KB_8 ,"KB_8"}, + {KB_9 ,"KB_9"}, + {KB_0 ,"KB_0"}, + {KB_minus ,"KB_minus"}, + {KB_equals ,"KB_equals"}, + {KB_backSlash ,"KB_backSlash"}, + {KB_backspace ,"KB_backspace"}, + {KB_tab ,"KB_tab"}, + {KB_Q ,"KB_Q"}, + {KB_W ,"KB_W"}, + {KB_E ,"KB_E"}, + {KB_R ,"KB_R"}, + {KB_T ,"KB_T"}, + {KB_Y ,"KB_Y"}, + {KB_U ,"KB_U"}, + {KB_I ,"KB_I"}, + {KB_O ,"KB_O"}, + {KB_P ,"KB_P"}, + {KB_leftSquareBrace ,"KB_leftSquareBrace"}, + {KB_rightSquareBrace ,"KB_rightSquareBrace"}, + {KB_enter ,"KB_enter"}, + {KB_A ,"KB_A"}, + {KB_S ,"KB_S"}, + {KB_D ,"KB_D"}, + {KB_F ,"KB_F"}, + {KB_G ,"KB_G"}, + {KB_H ,"KB_H"}, + {KB_J ,"KB_J"}, + {KB_K ,"KB_K"}, + {KB_L ,"KB_L"}, + {KB_semicolon ,"KB_semicolon"}, + {KB_apostrophe ,"KB_apostrophe"}, + {KB_Z ,"KB_Z"}, + {KB_X ,"KB_X"}, + {KB_C ,"KB_C"}, + {KB_V ,"KB_V"}, + {KB_B ,"KB_B"}, + {KB_N ,"KB_N"}, + {KB_M ,"KB_M"}, + {KB_comma ,"KB_comma"}, + {KB_period ,"KB_period"}, + {KB_divide ,"KB_divide"}, + {KB_space ,"KB_space"}, + {KB_tilde ,"KB_tilde"}, + {0 ,"KB_unknown"}, + }; + +/**************************************************************************** +PARAMETERS: +x - X coordinate of the mouse cursor position (screen coordinates) +y - Y coordinate of the mouse cursor position (screen coordinates) + +REMARKS: +This gets called periodically to move the mouse. It will get called when +the mouse may not have actually moved, so check if it has before redrawing +it. +****************************************************************************/ +void EVTAPI moveMouse( + int x, + int y) +{ +} + +/**************************************************************************** +PARAMETERS: +code - Code to translate +keys - Table of translation key values to look up + +REMARKS: +Simple function to look up the printable name for the keyboard code. +****************************************************************************/ +KeyEntry *FindKey( + int code, + KeyEntry *keys) +{ + KeyEntry *key; + + for (key = keys; key->code != 0; key++) { + if (key->code == code) + break; + } + return key; +} + +/**************************************************************************** +PARAMETERS: +evt - Event to display modifiers for + +REMARKS: +Function to display shift modifiers flags +****************************************************************************/ +void DisplayModifiers( + event_t *evt) +{ + if (evt->modifiers & EVT_LEFTBUT) + printf(", LBUT"); + if (evt->modifiers & EVT_RIGHTBUT) + printf(", RBUT"); + if (evt->modifiers & EVT_MIDDLEBUT) + printf(", MBUT"); + if (evt->modifiers & EVT_SHIFTKEY) { + if (evt->modifiers & EVT_LEFTSHIFT) + printf(", LSHIFT"); + if (evt->modifiers & EVT_RIGHTSHIFT) + printf(", RSHIFT"); + } + if (evt->modifiers & EVT_CTRLSTATE) { + if (evt->modifiers & EVT_LEFTCTRL) + printf(", LCTRL"); + if (evt->modifiers & EVT_RIGHTCTRL) + printf(", RCTRL"); + } + if (evt->modifiers & EVT_ALTSTATE) { + if (evt->modifiers & EVT_LEFTALT) + printf(", LALT"); + if (evt->modifiers & EVT_RIGHTALT) + printf(", RALT"); + } +} + +/**************************************************************************** +PARAMETERS: +msg - Message to display for type of event +evt - Event to display + +REMARKS: +Function to display the status of the keyboard event to the screen. +****************************************************************************/ +void DisplayKey( + char *msg, + event_t *evt) +{ + KeyEntry *ascii,*scan; + char ch = EVT_asciiCode(evt->message); + + ascii = FindKey(ch,ASCIICodes); + scan = FindKey(EVT_scanCode(evt->message),ScanCodes); + printf("%s: 0x%04X -> %s, %s, '%c'", + msg, (int)evt->message & 0xFFFF, scan->name, ascii->name, isprint(ch) ? ch : ' '); + DisplayModifiers(evt); + printf("\n"); +} + +/**************************************************************************** +PARAMETERS: +msg - Message to display for type of event +evt - Event to display + +REMARKS: +Function to display the status of the mouse event to the screen. +****************************************************************************/ +void DisplayMouse( + char *msg, + event_t *evt) +{ + printf("%s: ", msg); + if (evt->message & EVT_LEFTBMASK) + printf("LEFT "); + if (evt->message & EVT_RIGHTBMASK) + printf("RIGHT "); + if (evt->message & EVT_MIDDLEBMASK) + printf("MIDDLE "); + printf("abs(%d,%d), rel(%d,%d)", evt->where_x, evt->where_y, evt->relative_x, evt->relative_y); + DisplayModifiers(evt); + if (evt->message & EVT_DBLCLICK) + printf(", DBLCLICK"); + printf("\n"); +} + +/**************************************************************************** +PARAMETERS: +msg - Message to display for type of event +evt - Event to display + +REMARKS: +Function to display the status of the joystick event to the screen. +****************************************************************************/ +void DisplayJoy( + char *msg, + event_t *evt) +{ + printf("%s: Joy1(%4d,%4d,%c%c), Joy2(%4d,%4d,%c%c)\n", msg, + evt->where_x,evt->where_y, + (evt->message & EVT_JOY1_BUTTONA) ? 'A' : 'a', + (evt->message & EVT_JOY1_BUTTONB) ? 'B' : 'b', + evt->relative_x,evt->relative_y, + (evt->message & EVT_JOY2_BUTTONA) ? 'A' : 'a', + (evt->message & EVT_JOY2_BUTTONB) ? 'B' : 'b'); +} + +/**************************************************************************** +REMARKS: +Joystick calibration routine +****************************************************************************/ +void CalibrateJoy(void) +{ + event_t evt; + if(EVT_joyIsPresent()){ + printf("Joystick Calibration\nMove the joystick to the upper left corner and press any button.\n"); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_joySetUpperLeft(); + printf("Move the joystick to the lower right corner and press any button.\n"); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_joySetLowerRight(); + printf("Move the joystick to center position and press any button.\n"); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_joySetCenter(); + printf("Joystick calibrated\n"); + } +} + +/**************************************************************************** +REMARKS: +Main program entry point +****************************************************************************/ +int main(void) +{ + event_t evt; + ibool done = false; + PM_HWND hwndConsole; + + hwndConsole = PM_openConsole(0,0,0,0,0,true); + EVT_init(&moveMouse); + EVT_setMouseRange(1024,768); + CalibrateJoy(); + do { + EVT_pollJoystick(); + if (EVT_getNext(&evt,EVT_EVERYEVT)) { + switch (evt.what) { + case EVT_KEYDOWN: + DisplayKey("EVT_KEYDOWN ", &evt); + if (EVT_scanCode(evt.message) == KB_esc) + done = true; + break; + case EVT_KEYREPEAT: + DisplayKey("EVT_KEYREPEAT", &evt); + break; + case EVT_KEYUP: + DisplayKey("EVT_KEYUP ", &evt); + break; + case EVT_MOUSEDOWN: + DisplayMouse("EVT_MOUSEDOWN", &evt); + break; + case EVT_MOUSEAUTO: + DisplayMouse("EVT_MOUSEAUTO", &evt); + break; + case EVT_MOUSEUP: + DisplayMouse("EVT_MOUSEUP ", &evt); + break; + case EVT_MOUSEMOVE: + DisplayMouse("EVT_MOUSEMOVE", &evt); + break; + case EVT_JOYCLICK: + DisplayJoy("EVT_JOYCLICK ", &evt); + break; + case EVT_JOYMOVE: + DisplayJoy("EVT_JOYMOVE ", &evt); + break; + } + } + } while (!done); + EVT_exit(); + PM_closeConsole(hwndConsole); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c b/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c new file mode 100644 index 0000000..67ad245 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c @@ -0,0 +1,110 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to allocate real mode +* memory and to call real mode interrupt handlers such as +* the VESA VBE BIOS from protected mode. Compile and link +* with the appropriate command line for your DOS extender. +* +* Functions tested: PM_getVESABuf() +* PM_mapRealPointer() +* PM_int86x() +* +****************************************************************************/ + +#include +#include +#include +#include "pmapi.h" + +/* SuperVGA information block */ + +#pragma pack(1) + +typedef struct { + char VESASignature[4]; /* 'VESA' 4 byte signature */ + short VESAVersion; /* VBE version number */ + ulong OEMStringPtr; /* Far pointer to OEM string */ + ulong Capabilities; /* Capabilities of video card */ + ulong VideoModePtr; /* Far pointer to supported modes */ + short TotalMemory; /* Number of 64kb memory blocks */ + char reserved[236]; /* Pad to 256 byte block size */ + } VgaInfoBlock; + +#pragma pack() + +int main(void) +{ + RMREGS regs; + RMSREGS sregs; + VgaInfoBlock vgaInfo; + ushort *mode; + uint vgLen; + uchar *vgPtr; + unsigned r_vgseg,r_vgoff; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Allocate a 256 byte block of real memory for communicating with + * the VESA BIOS. + */ + if ((vgPtr = PM_getVESABuf(&vgLen,&r_vgseg,&r_vgoff)) == NULL) { + printf("Unable to allocate VESA memory buffer!\n"); + exit(1); + } + + /* Call the VESA VBE to see if it is out there */ + regs.x.ax = 0x4F00; + regs.x.di = r_vgoff; + sregs.es = r_vgseg; + memcpy(vgPtr,"VBE2",4); + PM_int86x(0x10, ®s, ®s, &sregs); + memcpy(&vgaInfo,vgPtr,sizeof(VgaInfoBlock)); + if (regs.x.ax == 0x4F && strncmp(vgaInfo.VESASignature,"VESA",4) == 0) { + printf("VESA VBE version %d.%d BIOS detected\n\n", + vgaInfo.VESAVersion >> 8, vgaInfo.VESAVersion & 0xF); + printf("Available video modes:\n"); + mode = PM_mapRealPointer(vgaInfo.VideoModePtr >> 16, vgaInfo.VideoModePtr & 0xFFFF); + while (*mode != 0xFFFF) { + printf(" %04hXh (%08X)\n", *mode, (int)mode); + mode++; + } + } + else + printf("VESA VBE not found\n"); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/key.c b/board/MAI/bios_emulator/scitech/src/pm/tests/key.c new file mode 100644 index 0000000..dba8885 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/key.c @@ -0,0 +1,92 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* keyboard interrupt handler. +* +* Functions tested: PM_setKeyHandler() +* PM_chainPrevKey() +* PM_restoreKeyHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI keyHandler(void) +{ + count++; + PM_chainPrevKey(); /* Chain to previous handler */ +} + +int main(void) +{ + int ch; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Install our timer handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)keyHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + PM_installBreakHandler(); /* We *DONT* want Ctrl-Breaks! */ + PM_setKeyHandler(keyHandler); + printf("Keyboard interrupt handler installed - Type some characters and\n"); + printf("hit ESC to exit\n"); + while ((ch = PM_getch()) != 0x1B) { + printf("%c", ch); + fflush(stdout); + } + + PM_restoreKeyHandler(); + PM_restoreBreakHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)keyHandler,100,&lh); + printf("\n\nKeyboard handler was called %ld times\n", count); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c b/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c new file mode 100644 index 0000000..b0b94be --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c @@ -0,0 +1,96 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* keyboard Int 15h interrupt handler. This is an alternate +* way to intercept scancodes from the keyboard by hooking +* the Int 15h keyboard intercept callout. +* +* Functions tested: PM_setKey15Handler() +* PM_restoreKey15Handler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; +volatile short lastScanCode = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +short PMAPI keyHandler(short scanCode) +{ + count++; + lastScanCode = scanCode; + return scanCode; /* Let BIOS process as normal */ +} + +int main(void) +{ + int ch; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Install our timer handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)keyHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + PM_installBreakHandler(); /* We *DONT* want Ctrl-Break's! */ + PM_setKey15Handler(keyHandler); + printf("Keyboard interrupt handler installed - Type some characters and\n"); + printf("hit ESC to exit\n"); + while ((ch = PM_getch()) != 0x1B) { + printf("%c", ch); + fflush(stdout); + } + + PM_restoreKey15Handler(); + PM_restoreBreakHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)keyHandler,100,&lh); + printf("\n\nKeyboard handler was called %ld times\n", count); + printf("Last scan code %04X\n", lastScanCode); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c b/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c new file mode 100644 index 0000000..a2c655b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c @@ -0,0 +1,106 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to determine just how much memory can be +* allocated with the compiler in use. Compile and link +* with the appropriate command line for your DOS extender. +* +* Functions tested: PM_malloc() +* PM_availableMemory() +* +* +****************************************************************************/ + +#include +#include +#include +#include +#include "pmapi.h" + +#ifdef __16BIT__ +#define MAXALLOC 64 +#else +#define MAXALLOC 2000 +#endif + +int main(void) +{ + int i; + ulong allocs; + ulong physical,total; + char *p,*pa[MAXALLOC]; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + printf("Memory available at start:\n"); + PM_availableMemory(&physical,&total); + printf(" Physical memory: %ld Kb\n", physical / 1024); + printf(" Total (including virtual): %ld Kb\n", total / 1024); + printf("\n"); + for (allocs = i = 0; i < MAXALLOC; i++) { + if ((pa[i] = PM_malloc(10*1024)) != 0) { /* in 10k blocks */ + p = pa[allocs]; + memset(p, 0, 10*1024); /* touch every byte */ + *p = 'x'; /* do something, anything with */ + p[1023] = 'y'; /* the allocated memory */ + allocs++; + printf("Allocated %lu bytes\r", 10*(allocs << 10)); + } + else break; + if (PM_kbhit() && (PM_getch() == 0x1B)) + break; + } + + printf("\n\nAllocated total of %lu bytes\n", 10 * (allocs << 10)); + + printf("\nMemory available at end:\n"); + PM_availableMemory(&physical,&total); + printf(" Physical memory: %ld Kb\n", physical / 1024); + printf(" Total (including virtual): %ld Kb\n", total / 1024); + + for (i = allocs-1; i >= 0; i--) + PM_free(pa[i]); + + printf("\nMemory available after freeing all blocks (note that under protected mode\n"); + printf("this will most likely not be correct after freeing blocks):\n\n"); + PM_availableMemory(&physical,&total); + printf(" Physical memory: %ld Kb\n", physical / 1024); + printf(" Total (including virtual): %ld Kb\n", total / 1024); + + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c b/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c new file mode 100644 index 0000000..2765a0d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c @@ -0,0 +1,109 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install an assembly +* language mouse interrupt handler. We use assembly language +* as it must be a far function and should swap to a local +* 32 bit stack if it is going to call any C based code (which +* we do in this example). +* +* Functions tested: PM_installMouseHandler() +* PM_int86() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI mouseHandler( + uint mask, + uint butstate, + int x, + int y, + int mickeyX, + int mickeyY) +{ + mask = mask; /* We dont use any of the parameters */ + butstate = butstate; + x = x; + y = y; + mickeyX = mickeyX; + mickeyY = mickeyY; + count++; +} + +int main(void) +{ + RMREGS regs; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + regs.x.ax = 33; /* Mouse function 33 - Software reset */ + PM_int86(0x33,®s,®s); + if (regs.x.bx == 0) { + printf("No mouse installed.\n"); + exit(1); + } + + /* Install our mouse handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)mouseHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + if (!PM_setMouseHandler(0xFFFF, mouseHandler)) { + printf("Unable to install mouse handler!\n"); + exit(1); + } + printf("Mouse handler installed - Hit any key to exit\n"); + PM_getch(); + + PM_restoreMouseHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)mouseHandler,100,&lh); + printf("Mouse handler was called %ld times\n", count); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c b/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c new file mode 100644 index 0000000..e00be75 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c @@ -0,0 +1,81 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux/QNX +* +* Description: Program to restore the console state state from a previously +* saved state if the program crashed while the console +* was in graphics mode. +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +void setVideoMode(int mode) +{ + RMREGS r; + + r.x.ax = mode; + PM_int86(0x10, &r, &r); +} + +int main(void) +{ + PM_HWND hwndConsole; + ulong stateSize; + void *stateBuf; + FILE *f; + + /* Write the saved console state buffer to disk */ + if ((f = fopen("/etc/pmsave.dat","rb")) == NULL) { + printf("Unable to open /etc/pmsave.dat for reading!\n"); + return -1; + } + fread(&stateSize,1,sizeof(stateSize),f); + if (stateSize != PM_getConsoleStateSize()) { + printf("Size mismatch in /etc/pmsave.dat!\n"); + return -1; + } + if ((stateBuf = PM_malloc(stateSize)) == NULL) { + printf("Unable to allocate console state buffer!\n"); + return -1; + } + fread(stateBuf,1,stateSize,f); + fclose(f); + + /* Open the console */ + hwndConsole = PM_openConsole(0,0,0,0,0,true); + + /* Forcibly set 80x25 text mode using the BIOS */ + setVideoMode(0x3); + + /* Restore the previous console state */ + PM_restoreConsoleState(stateBuf,0); + PM_closeConsole(hwndConsole); + PM_free(stateBuf); + printf("Console state successfully restored from /etc/pmsave.dat\n"); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c new file mode 100644 index 0000000..acef922 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c @@ -0,0 +1,92 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* Real Time Clock interrupt handler. +* +* Functions tested: PM_setRealTimeClockHandler() +* PM_restoreRealTimeClockHandler() +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI RTCHandler(void) +{ + count++; +} + +int main(void) +{ + long oldCount; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Install our timer handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)RTCHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + PM_installBreakHandler(); /* We *DONT* want Ctrl-Breaks! */ + PM_setRealTimeClockHandler(RTCHandler,128); + printf("RealTimeClock interrupt handler installed - Hit ESC to exit\n"); + oldCount = count; + while (1) { + if (PM_kbhit() && (PM_getch() == 0x1B)) + break; + if (count != oldCount) { + printf("Tick, Tock: %ld\n", count); + oldCount = count; + } + } + + PM_restoreRealTimeClockHandler(); + PM_restoreBreakHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)RTCHandler,100,&lh); + printf("RealTimeClock handler was called %ld times\n", count); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/save.c b/board/MAI/bios_emulator/scitech/src/pm/tests/save.c new file mode 100644 index 0000000..f732456 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/save.c @@ -0,0 +1,69 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux/QNX +* +* Description: Program to save the console state state so that it can +* be later restored if the program crashed while the console +* was in graphics mode. +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +int main(void) +{ + PM_HWND hwndConsole; + ulong stateSize; + void *stateBuf; + FILE *f; + + /* Allocate a buffer to save console state and save the state */ + hwndConsole = PM_openConsole(0,0,0,0,0,true); + stateSize = PM_getConsoleStateSize(); + if ((stateBuf = PM_malloc(stateSize)) == NULL) { + PM_closeConsole(hwndConsole); + printf("Unable to allocate console state buffer!\n"); + return -1; + } + PM_saveConsoleState(stateBuf,0); + + /* Restore the console state on exit */ + PM_restoreConsoleState(stateBuf,0); + PM_closeConsole(hwndConsole); + + /* Write the saved console state buffer to disk */ + if ((f = fopen("/etc/pmsave.dat","wb")) == NULL) + printf("Unable to open /etc/pmsave/dat for writing!\n"); + else { + fwrite(&stateSize,1,sizeof(stateSize),f); + fwrite(stateBuf,1,stateSize,f); + fclose(f); + printf("Console state successfully saved to /etc/pmsave.dat\n"); + } + PM_free(stateBuf); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c b/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c new file mode 100644 index 0000000..be275e1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c @@ -0,0 +1,253 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to test the PCI library functions. +* +****************************************************************************/ + +#include "pmapi.h" +#include "pcilib.h" +#include +#include +#include +#include + +/*------------------------- Global Variables ------------------------------*/ + +static int NumPCI = -1; +static PCIDeviceInfo *PCI; +static int *BridgeIndex; +static int *DeviceIndex; +static int NumBridges; +static PCIDeviceInfo *AGPBridge = NULL; +static int NumDevices; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Enumerates the PCI bus and dumps the PCI configuration information to the +log file. +****************************************************************************/ +static void EnumeratePCI(void) +{ + int i,index; + PCIDeviceInfo *info; + + printf("Displaying enumeration of PCI bus (%d devices, %d display devices)\n", + NumPCI, NumDevices); + for (index = 0; index < NumDevices; index++) + printf(" Display device %d is PCI device %d\n",index,DeviceIndex[index]); + printf("\n"); + printf("Bus Slot Fnc DeviceID SubSystem Rev Class IRQ Int Cmd\n"); + for (i = 0; i < NumPCI; i++) { + printf("%2d %2d %2d %04X:%04X %04X:%04X %02X %02X:%02X %02X %02X %04X ", + PCI[i].slot.p.Bus, + PCI[i].slot.p.Device, + PCI[i].slot.p.Function, + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].u.type0.SubSystemVendorID, + PCI[i].u.type0.SubSystemID, + PCI[i].RevID, + PCI[i].BaseClass, + PCI[i].SubClass, + PCI[i].u.type0.InterruptLine, + PCI[i].u.type0.InterruptPin, + PCI[i].Command); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printf("<- %d\n", index); + else + printf("\n"); + } + printf("\n"); + printf("DeviceID Stat Ifc Cch Lat Hdr BIST\n"); + for (i = 0; i < NumPCI; i++) { + printf("%04X:%04X %04X %02X %02X %02X %02X %02X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].Status, + PCI[i].Interface, + PCI[i].CacheLineSize, + PCI[i].LatencyTimer, + PCI[i].HeaderType, + PCI[i].BIST); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printf("<- %d\n", index); + else + printf("\n"); + } + printf("\n"); + printf("DeviceID Base10h Base14h Base18h Base1Ch Base20h Base24h ROMBase\n"); + for (i = 0; i < NumPCI; i++) { + printf("%04X:%04X %08lX %08lX %08lX %08lX %08lX %08lX %08lX ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].u.type0.BaseAddress10, + PCI[i].u.type0.BaseAddress14, + PCI[i].u.type0.BaseAddress18, + PCI[i].u.type0.BaseAddress1C, + PCI[i].u.type0.BaseAddress20, + PCI[i].u.type0.BaseAddress24, + PCI[i].u.type0.ROMBaseAddress); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printf("<- %d\n", index); + else + printf("\n"); + } + printf("\n"); + printf("DeviceID BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n"); + for (i = 0; i < NumPCI; i++) { + printf("%04X:%04X %08lX %08lX %08lX %08lX %08lX %08lX %08lX ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].u.type0.BaseAddress10Len, + PCI[i].u.type0.BaseAddress14Len, + PCI[i].u.type0.BaseAddress18Len, + PCI[i].u.type0.BaseAddress1CLen, + PCI[i].u.type0.BaseAddress20Len, + PCI[i].u.type0.BaseAddress24Len, + PCI[i].u.type0.ROMBaseAddressLen); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printf("<- %d\n", index); + else + printf("\n"); + } + printf("\n"); + printf("Displaying enumeration of %d bridge devices\n",NumBridges); + printf("\n"); + printf("DeviceID P# S# B# IOB IOL MemBase MemLimit PreBase PreLimit Ctrl\n"); + for (i = 0; i < NumBridges; i++) { + info = (PCIDeviceInfo*)&PCI[BridgeIndex[i]]; + printf("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n", + info->VendorID, + info->DeviceID, + info->u.type1.PrimaryBusNumber, + info->u.type1.SecondayBusNumber, + info->u.type1.SubordinateBusNumber, + ((u16)info->u.type1.IOBase << 8) & 0xF000, + info->u.type1.IOLimit ? + ((u16)info->u.type1.IOLimit << 8) | 0xFFF : 0, + ((u32)info->u.type1.MemoryBase << 16) & 0xFFF00000, + info->u.type1.MemoryLimit ? + ((u32)info->u.type1.MemoryLimit << 16) | 0xFFFFF : 0, + ((u32)info->u.type1.PrefetchableMemoryBase << 16) & 0xFFF00000, + info->u.type1.PrefetchableMemoryLimit ? + ((u32)info->u.type1.PrefetchableMemoryLimit << 16) | 0xFFFFF : 0, + info->u.type1.BridgeControl); + } + printf("\n"); +} + +/**************************************************************************** +RETURNS: +Number of display devices found. + +REMARKS: +This function enumerates the number of available display devices on the +PCI bus, and returns the number found. +****************************************************************************/ +static int PCI_enumerateDevices(void) +{ + int i,j; + PCIDeviceInfo *info; + + /* If this is the first time we have been called, enumerate all */ + /* devices on the PCI bus. */ + if (NumPCI == -1) { + if ((NumPCI = PCI_getNumDevices()) == 0) + return -1; + PCI = malloc(NumPCI * sizeof(PCI[0])); + BridgeIndex = malloc(NumPCI * sizeof(BridgeIndex[0])); + DeviceIndex = malloc(NumPCI * sizeof(DeviceIndex[0])); + if (!PCI || !BridgeIndex || !DeviceIndex) + return -1; + for (i = 0; i < NumPCI; i++) + PCI[i].dwSize = sizeof(PCI[i]); + if (PCI_enumerate(PCI) == 0) + return -1; + + /* Build a list of all PCI bridge devices */ + for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { + if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) + BridgeIndex[NumBridges++] = i; + } + + /* Now build a list of all display class devices */ + for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { + if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { + if ((PCI[i].Command & 0x3) == 0x3) + DeviceIndex[0] = i; + else + DeviceIndex[NumDevices++] = i; + if (PCI[i].slot.p.Bus != 0) { + /* This device is on a different bus than the primary */ + /* PCI bus, so it is probably an AGP device. Find the */ + /* AGP bus device that controls that bus so we can */ + /* control it. */ + for (j = 0; j < NumBridges; j++) { + info = (PCIDeviceInfo*)&PCI[BridgeIndex[j]]; + if (info->u.type1.SecondayBusNumber == PCI[i].slot.p.Bus) { + AGPBridge = info; + break; + } + } + } + } + } + + /* Enumerate all PCI and bridge devices to standard output */ + EnumeratePCI(); + } + return NumDevices; +} + +int main(void) +{ + /* Enumerate all PCI devices */ + PM_init(); + if (PCI_enumerateDevices() < 1) { + printf("No PCI display devices found!\n"); + return -1; + } + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c b/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c new file mode 100644 index 0000000..378725e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c @@ -0,0 +1,94 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* timer interrupt handler. +* +* Functions tested: PM_setTimerHandler() +* PM_chainPrevTimer(); +* PM_restoreTimerHandler() +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI timerHandler(void) +{ + PM_chainPrevTimer(); /* Chain to previous handler */ + count++; +} + +int main(void) +{ + long oldCount; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Install our timer handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)timerHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + PM_installBreakHandler(); /* We *DONT* want Ctrl-Breaks! */ + PM_setTimerHandler(timerHandler); + printf("Timer interrupt handler installed - Hit ESC to exit\n"); + oldCount = count; + while (1) { + if (PM_kbhit() && (PM_getch() == 0x1B)) + break; + if (count != oldCount) { + printf("Tick, Tock: %ld\n", count); + oldCount = count; + } + } + + PM_restoreTimerHandler(); + PM_restoreBreakHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)timerHandler,100,&lh); + printf("Timer handler was called %ld times\n", count); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c new file mode 100644 index 0000000..7fa77b7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c @@ -0,0 +1,87 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Test program for the Zen Timer Library. +* +****************************************************************************/ + +#include +#include "pmapi.h" +#include "ztimer.h" + +#define DELAY_SECS 10 + +/*-------------------------- Implementation -------------------------------*/ + +/* The following routine takes a long count in microseconds and outputs + * a string representing the count in seconds. It could be modified to + * return a pointer to a static string representing the count rather + * than printing it out. + */ + +void ReportTime(ulong count) +{ + ulong secs; + + secs = count / 1000000L; + count = count - secs * 1000000L; + printf("Time taken: %lu.%06lu seconds\n",secs,count); +} + +int i,j; /* NON register variables! */ + +int main(void) +{ +#ifdef LONG_TEST + ulong start,finish; +#endif + + printf("Processor type: %d %ld MHz\n", CPU_getProcessorType(), CPU_getProcessorSpeed(true)); + + ZTimerInit(); + + /* Test the long period Zen Timer (we don't check for overflow coz + * it would take tooooo long!) + */ + + LZTimerOn(); + for (j = 0; j < 10; j++) + for (i = 0; i < 20000; i++) + i = i; + LZTimerOff(); + ReportTime(LZTimerCount()); + + /* Test the ultra long period Zen Timer */ +#ifdef LONG_TEST + start = ULZReadTime(); + delay(DELAY_SECS * 1000); + finish = ULZReadTime(); + printf("Delay of %d secs took %d 1/10ths of a second\n", + DELAY_SECS,ULZElapsedTime(start,finish)); +#endif + + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp b/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp new file mode 100644 index 0000000..1258a4b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp @@ -0,0 +1,107 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: C++ 3.0 +* Environment: Any +* +* Description: Test program for the Zen Timer Library C++ interface. +* +****************************************************************************/ + +#include +#include "pmapi.h" +#include "ztimer.h" + +/*-------------------------- Implementation -------------------------------*/ + +int i,j,k; /* NON register variables! */ + +void dummy() {} + +int main(void) +{ + LZTimer ltimer; + ULZTimer ultimer; + + ZTimerInit(); + + /* Test the long period Zen Timer (we don't check for overflow coz + * it would take tooooo long!) + */ + + cout << endl; + ultimer.restart(); + ltimer.start(); + for (j = 0; j < 10; j++) + for (i = 0; i < 20000; i++) + dummy(); + ltimer.stop(); + ultimer.stop(); + cout << "LCount: " << ltimer.count() << endl; + cout << "Time: " << ltimer << " secs\n"; + cout << "ULCount: " << ultimer.count() << endl; + cout << "ULTime: " << ultimer << " secs\n"; + + cout << endl << "Timing ... \n"; + ultimer.restart(); + ltimer.restart(); + for (j = 0; j < 200; j++) + for (i = 0; i < 20000; i++) + dummy(); + ltimer.stop(); + ultimer.stop(); + cout << "LCount: " << ltimer.count() << endl; + cout << "Time: " << ltimer << " secs\n"; + cout << "ULCount: " << ultimer.count() << endl; + cout << "ULTime: " << ultimer << " secs\n"; + + /* Test the lap function of the long period Zen Timer */ + + cout << endl << "Timing ... \n"; + ultimer.restart(); + ltimer.restart(); + for (j = 0; j < 20; j++) { + for (k = 0; k < 10; k++) + for (i = 0; i < 20000; i++) + dummy(); + cout << "lap: " << ltimer.lap() << endl; + } + ltimer.stop(); + ultimer.stop(); + cout << "LCount: " << ltimer.count() << endl; + cout << "Time: " << ltimer << " secs\n"; + cout << "ULCount: " << ultimer.count() << endl; + cout << "ULTime: " << ultimer << " secs\n"; + +#ifdef LONG_TEST + /* Test the ultra long period Zen Timer */ + + ultimer.start(); + delay(DELAY_SECS * 1000); + ultimer.stop(); + cout << "Delay of " << DELAY_SECS << " secs took " << ultimer.count() + << " 1/10ths of a second\n"; + cout << "Time: " << ultimer << " secs\n"; +#endif + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c new file mode 100644 index 0000000..f0c7bd6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c @@ -0,0 +1,311 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Simple test program to test the write combine functions. +* +* Note that this program should never be used in a production +* environment, because write combining needs to be handled +* with more intimate knowledge of the display hardware than +* you can obtain by simply examining the PCI configuration +* space. +* +****************************************************************************/ + +#include "pmapi.h" +#include "pcilib.h" +#include +#include +#include +#include + +/*------------------------- Global Variables ------------------------------*/ + +static int NumPCI = -1; +static PCIDeviceInfo *PCI; +static int *BridgeIndex; +static int *DeviceIndex; +static int NumBridges; +static PCIDeviceInfo *AGPBridge = NULL; +static int NumDevices; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +RETURNS: +Number of display devices found. + +REMARKS: +This function enumerates the number of available display devices on the +PCI bus, and returns the number found. +****************************************************************************/ +static int PCI_enumerateDevices(void) +{ + int i,j; + PCIDeviceInfo *info; + + /* If this is the first time we have been called, enumerate all */ + /* devices on the PCI bus. */ + if (NumPCI == -1) { + if ((NumPCI = PCI_getNumDevices()) == 0) + return -1; + PCI = malloc(NumPCI * sizeof(PCI[0])); + BridgeIndex = malloc(NumPCI * sizeof(BridgeIndex[0])); + DeviceIndex = malloc(NumPCI * sizeof(DeviceIndex[0])); + if (!PCI || !BridgeIndex || !DeviceIndex) + return -1; + for (i = 0; i < NumPCI; i++) + PCI[i].dwSize = sizeof(PCI[i]); + if (PCI_enumerate(PCI) == 0) + return -1; + + /* Build a list of all PCI bridge devices */ + for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { + if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) + BridgeIndex[NumBridges++] = i; + } + + /* Now build a list of all display class devices */ + for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { + if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { + if ((PCI[i].Command & 0x3) == 0x3) + DeviceIndex[0] = i; + else + DeviceIndex[NumDevices++] = i; + if (PCI[i].slot.p.Bus != 0) { + /* This device is on a different bus than the primary */ + /* PCI bus, so it is probably an AGP device. Find the */ + /* AGP bus device that controls that bus so we can */ + /* control it. */ + for (j = 0; j < NumBridges; j++) { + info = (PCIDeviceInfo*)&PCI[BridgeIndex[j]]; + if (info->u.type1.SecondayBusNumber == PCI[i].slot.p.Bus) { + AGPBridge = info; + break; + } + } + } + } + } + } + return NumDevices; +} + +/**************************************************************************** +REMARKS: +Enumerates useful information about attached display devices. +****************************************************************************/ +static void ShowDisplayDevices(void) +{ + int i,index; + + printf("Displaying enumeration of %d PCI display devices\n", NumDevices); + printf("\n"); + printf("DeviceID SubSystem Base10h (length ) Base14h (length )\n"); + for (index = 0; index < NumDevices; index++) { + i = DeviceIndex[index]; + printf("%04X:%04X %04X:%04X %08lX (%6ld KB) %08lX (%6ld KB)\n", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].u.type0.SubSystemVendorID, + PCI[i].u.type0.SubSystemID, + PCI[i].u.type0.BaseAddress10, + PCI[i].u.type0.BaseAddress10Len / 1024, + PCI[i].u.type0.BaseAddress14, + PCI[i].u.type0.BaseAddress14Len / 1024); + } + printf("\n"); +} + +/**************************************************************************** +REMARKS: +Dumps the value for a write combine region to the display. +****************************************************************************/ +static char *DecodeWCType( + uint type) +{ + static char *names[] = { + "UNCACHABLE", + "WRCOMB", + "UNKNOWN", + "UNKNOWN", + "WRTHROUGH", + "WRPROT", + "WRBACK", + }; + if (type <= PM_MTRR_MAX) + return names[type]; + return "UNKNOWN"; +} + +/**************************************************************************** +REMARKS: +Dumps the value for a write combine region to the display. +****************************************************************************/ +static void PMAPI EnumWriteCombine( + ulong base, + ulong length, + uint type) +{ + printf("%08lX %-10ld %s\n", base, length / 1024, DecodeWCType(type)); +} + +/**************************************************************************** +PARAMETERS: +err - Error to log + +REMARKS: +Function to log an error message if the MTRR write combining attempt failed. +****************************************************************************/ +static void LogMTRRError( + int err) +{ + if (err == PM_MTRR_ERR_OK) + return; + switch (err) { + case PM_MTRR_NOT_SUPPORTED: + printf("Failed: MTRR is not supported by host CPU\n"); + break; + case PM_MTRR_ERR_PARAMS: + printf("Failed: Invalid parameters passed to PM_enableWriteCombined!\n"); + break; + case PM_MTRR_ERR_NOT_4KB_ALIGNED: + printf("Failed: Address is not 4Kb aligned!\n"); + break; + case PM_MTRR_ERR_BELOW_1MB: + printf("Failed: Addresses below 1Mb cannot be write combined!\n"); + break; + case PM_MTRR_ERR_NOT_ALIGNED: + printf("Failed: Address is not correctly aligned for processor!\n"); + break; + case PM_MTRR_ERR_OVERLAP: + printf("Failed: Address overlaps an existing region!\n"); + break; + case PM_MTRR_ERR_TYPE_MISMATCH: + printf("Failed: Adress is contained with existing region, but type is different!\n"); + break; + case PM_MTRR_ERR_NONE_FREE: + printf("Failed: Out of MTRR registers!\n"); + break; + case PM_MTRR_ERR_NOWRCOMB: + printf("Failed: This processor does not support write combining!\n"); + break; + case PM_MTRR_ERR_NO_OS_SUPPORT: + printf("Failed: MTRR is not supported by host OS\n"); + break; + default: + printf("Failed: UNKNOWN ERROR!\n"); + break; + } + exit(-1); +} + +/**************************************************************************** +REMARKS: +Shows all write combine regions. +****************************************************************************/ +static void ShowWriteCombine(void) +{ + printf("Base Length(KB) Type\n"); + LogMTRRError(PM_enumWriteCombine(EnumWriteCombine)); + printf("\n"); +} + +/**************************************************************************** +REMARKS: +Dumps the value for a write combine region to the display. +****************************************************************************/ +static void EnableWriteCombine(void) +{ + int i,index; + + for (index = 0; index < NumDevices; index++) { + i = DeviceIndex[index]; + if (PCI[i].u.type0.BaseAddress10 & 0x8) { + LogMTRRError(PM_enableWriteCombine( + PCI[i].u.type0.BaseAddress10 & 0xFFFFFFF0, + PCI[i].u.type0.BaseAddress10Len, + PM_MTRR_WRCOMB)); + } + if (PCI[i].u.type0.BaseAddress14 & 0x8) { + LogMTRRError(PM_enableWriteCombine( + PCI[i].u.type0.BaseAddress14 & 0xFFFFFFF0, + PCI[i].u.type0.BaseAddress14Len, + PM_MTRR_WRCOMB)); + } + } + printf("\n"); + ShowDisplayDevices(); + ShowWriteCombine(); +} + +/**************************************************************************** +REMARKS: +Dumps the value for a write combine region to the display. +****************************************************************************/ +static void DisableWriteCombine(void) +{ + int i,index; + + for (index = 0; index < NumDevices; index++) { + i = DeviceIndex[index]; + if (PCI[i].u.type0.BaseAddress10 & 0x8) { + LogMTRRError(PM_enableWriteCombine( + PCI[i].u.type0.BaseAddress10 & 0xFFFFFFF0, + PCI[i].u.type0.BaseAddress10Len, + PM_MTRR_UNCACHABLE)); + } + if (PCI[i].u.type0.BaseAddress14 & 0x8) { + LogMTRRError(PM_enableWriteCombine( + PCI[i].u.type0.BaseAddress14 & 0xFFFFFFF0, + PCI[i].u.type0.BaseAddress14Len, + PM_MTRR_UNCACHABLE)); + } + } + printf("\n"); + ShowDisplayDevices(); + ShowWriteCombine(); +} + +int main(int argc,char *argv[]) +{ + PM_init(); + if (PCI_enumerateDevices() < 1) { + printf("No PCI display devices found!\n"); + return -1; + } + if (argc < 2) { + printf("usage: uswc [-show -on -off]\n\n"); + ShowDisplayDevices(); + return -1; + } + if (stricmp(argv[1],"-show") == 0) + ShowWriteCombine(); + else if (stricmp(argv[1],"-on") == 0) + EnableWriteCombine(); + else if (stricmp(argv[1],"-off") == 0) + DisableWriteCombine(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c b/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c new file mode 100644 index 0000000..b7e3bb7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c @@ -0,0 +1,78 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Filename: $Workfile$ +* Version: $Revision: 1.1 $ +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to test the VFlat virtual framebuffer functions. +* +* Functions tested: VF_available() +* VF_init() +* VF_exit() +* +* $Date: 2002/10/02 15:35:21 $ $Author: hfrieden $ +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +uchar code[] = { + 0xC3, /* ret */ + }; + +int main(void) +{ + void *vfBuffer; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + if (!VF_available()) { + printf("Virtual Linear Framebuffer not available.\n"); + exit(1); + } + + vfBuffer = VF_init(0xA0000,64,sizeof(code),code); + if (!vfBuffer) { + printf("Failure to initialise Virtual Linear Framebuffer!\n"); + exit(1); + } + VF_exit(); + printf("Virtual Linear Framebuffer set up successfully!\n"); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/video.c b/board/MAI/bios_emulator/scitech/src/pm/tests/video.c new file mode 100644 index 0000000..92adcdd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/video.c @@ -0,0 +1,199 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to generate real mode +* interrupts and to be able to obtain direct access to the +* video memory from protected mode. Compile and link with +* the appropriate command line for your DOS extender. +* +* Functions tested: PM_getBIOSSelector() +* PM_mapPhysicalAddr() +* PM_int86() +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +uchar *bios; /* Pointer to BIOS data area */ +uchar *videoPtr; /* Pointer to VGA framebuffer */ +void *stateBuf; /* Console state save buffer */ + +/* Routine to return the current video mode number */ + +int getVideoMode(void) +{ + return PM_getByte(bios+0x49); +} + +/* Routine to set a specified video mode */ + +void setVideoMode(int mode) +{ + RMREGS r; + + r.x.ax = mode; + PM_int86(0x10, &r, &r); +} + +/* Routine to clear a rectangular region on the display by calling the + * video BIOS. + */ + +void clearScreen(int startx, int starty, int endx, int endy, unsigned char attr) +{ + RMREGS r; + + r.x.ax = 0x0600; + r.h.bh = attr; + r.h.cl = startx; + r.h.ch = starty; + r.h.dl = endx; + r.h.dh = endy; + PM_int86(0x10, &r, &r); +} + +/* Routine to fill a rectangular region on the display using direct + * video writes. + */ + +#define SCREEN(x,y) (videoPtr + ((y) * 160) + ((x) << 1)) + +void fill(int startx, int starty, int endx, int endy, unsigned char c, + unsigned char attr) +{ + unsigned char *v; + int x,y; + + for (y = starty; y <= endy; y++) { + v = SCREEN(startx,y); + for (x = startx; x <= endx; x++) { + *v++ = c; + *v++ = attr; + } + } +} + +/* Routine to display a single character using direct video writes */ + +void writeChar(int x, int y, unsigned char c, unsigned char attr) +{ + unsigned char *v = SCREEN(x,y); + *v++ = c; + *v = attr; +} + +/* Routine to draw a border around a rectangular area using direct video + * writes. + */ + +static unsigned char border_chars[] = { + 186, 205, 201, 187, 200, 188 /* double box chars */ + }; + +void border(int startx, int starty, int endx, int endy, unsigned char attr) +{ + unsigned char *v; + unsigned char *b; + int i; + + b = border_chars; + + for (i = starty+1; i < endy; i++) { + writeChar(startx, i, *b, attr); + writeChar(endx, i, *b, attr); + } + b++; + for (i = startx+1, v = SCREEN(startx+1, starty); i < endx; i++) { + *v++ = *b; + *v++ = attr; + } + for (i = startx+1, v = SCREEN(startx+1, endy); i < endx; i++) { + *v++ = *b; + *v++ = attr; + } + b++; + writeChar(startx, starty, *b++, attr); + writeChar(endx, starty, *b++, attr); + writeChar(startx, endy, *b++, attr); + writeChar(endx, endy, *b++, attr); +} + +int main(void) +{ + int orgMode; + PM_HWND hwndConsole; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + hwndConsole = PM_openConsole(0,0,0,0,0,true); + printf("Hit any key to start 80x25 text mode and perform some direct video output.\n"); + PM_getch(); + + /* Allocate a buffer to save console state and save the state */ + if ((stateBuf = PM_malloc(PM_getConsoleStateSize())) == NULL) { + printf("Unable to allocate console state buffer!\n"); + exit(1); + } + PM_saveConsoleState(stateBuf,0); + bios = PM_getBIOSPointer(); + orgMode = getVideoMode(); + setVideoMode(0x3); + if ((videoPtr = PM_mapPhysicalAddr(0xB8000,0xFFFF,true)) == NULL) { + printf("Unable to obtain pointer to framebuffer!\n"); + exit(1); + } + + /* Draw some text on the screen */ + fill(0, 0, 79, 24, 176, 0x1E); + border(0, 0, 79, 24, 0x1F); + PM_getch(); + clearScreen(0, 0, 79, 24, 0x7); + + /* Restore the console state on exit */ + PM_restoreConsoleState(stateBuf,0); + PM_free(stateBuf); + PM_closeConsole(hwndConsole); + + /* Display useful status information */ + printf("\n"); + printf("Original Video Mode = %02X\n", orgMode); + printf("BIOS Pointer = %08X\n", (int)bios); + printf("Video Memory = %08X\n", (int)videoPtr); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c new file mode 100644 index 0000000..3460b72 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c @@ -0,0 +1,66 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: VDD specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Do nothing for VDD's +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for VDD's +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = 100000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + ULONG count; \ + count = VDHQuerySysValue(0, VDHGSV_MSECSBOOT); \ + (t)->low = count * 100; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c new file mode 100644 index 0000000..93742de --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c @@ -0,0 +1,359 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: C library compatible I/O functions for use within a VDD. +* +****************************************************************************/ + +#include "pmapi.h" +#include "vddfile.h" + +/*------------------------ Main Code Implementation -----------------------*/ + +#define EOF -1 + +/* NB: none of the file VDHs are available during the DOS session */ +/* initialzation context! */ + +/* Macros for Open/Close APIs to allow using this module in both VDDs and */ +/* normal OS/2 applications. Unfortunately VDHRead/Write/Seek don't map to */ +/* their Dos* counterparts so cleanly. */ +#ifdef __OS2_VDD__ +#define _OS2Open VDHOpen +#define _OS2Close VDHClose +#else +#define _OS2Open DosOpen +#define _OS2Close DosClose +#endif + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C fopen function. +****************************************************************************/ +FILE * fopen( + const char *filename, + const char *mode) +{ + FILE *f = PM_malloc(sizeof(FILE)); + long oldpos; + ULONG rc, ulAction; + ULONG omode, oflags; + + if (f != NULL) { + f->offset = 0; + f->text = (mode[1] == 't' || mode[2] == 't'); + f->writemode = (mode[0] == 'w') || (mode[0] == 'a'); + f->unputc = EOF; + f->endp = f->buf + sizeof(f->buf); + f->curp = f->startp = f->buf; + + if (mode[0] == 'r') { + #ifdef __OS2_VDD__ + omode = VDHOPEN_ACCESS_READONLY | VDHOPEN_SHARE_DENYNONE; + oflags = VDHOPEN_ACTION_OPEN_IF_EXISTS | VDHOPEN_ACTION_FAIL_IF_NEW; + #else + omode = OPEN_ACCESS_READONLY | OPEN_SHARE_DENYNONE; + oflags = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_FAIL_IF_NEW; + #endif + } + else if (mode[0] == 'w') { + #ifdef __OS2_VDD__ + omode = VDHOPEN_ACCESS_WRITEONLY | VDHOPEN_SHARE_DENYWRITE; + oflags = VDHOPEN_ACTION_REPLACE_IF_EXISTS | VDHOPEN_ACTION_CREATE_IF_NEW; + #else + omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_DENYWRITE; + oflags = OPEN_ACTION_REPLACE_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + #endif + } + else { + #ifdef __OS2_VDD__ + omode = VDHOPEN_ACCESS_READWRITE | VDHOPEN_SHARE_DENYWRITE; + oflags = VDHOPEN_ACTION_OPEN_IF_EXISTS | VDHOPEN_ACTION_CREATE_IF_NEW; + #else + omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_DENYWRITE; + oflags = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + #endif + } + rc = _OS2Open((PSZ)filename, (PHFILE)&f->handle, &ulAction, 0, VDHOPEN_FILE_NORMAL, oflags, omode, NULL); + if (rc != 0) { + PM_free(f); + return NULL; + } + + #ifdef __OS2_VDD__ + f->filesize = VDHSeek((HFILE)f->handle, 0, VDHSK_END_OF_FILE); + #else + rc = DosSetFilePtr((HFILE)f->handle, 0, FILE_END, &f->filesize); + #endif + + if (mode[0] == 'a') + fseek(f,0,2); + } + return f; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C fread function. Note that unlike Windows VxDs, +OS/2 VDDs are not limited to 64K reads or writes. +****************************************************************************/ +size_t fread( + void *ptr, + size_t size, + size_t n, + FILE *f) +{ + char *buf = ptr; + int bytes,readbytes,totalbytes = 0; + + /* First copy any data already read into our buffer */ + if ((bytes = (f->curp - f->startp)) > 0) { + memcpy(buf,f->curp,bytes); + f->startp = f->curp = f->buf; + buf += bytes; + totalbytes += bytes; + bytes = (size * n) - bytes; + } + else + bytes = size * n; + if (bytes) { + #ifdef __OS2_VDD__ + readbytes = VDHRead((HFILE)f->handle, buf, bytes); + #else + DosRead((HFILE)f->handle, buf, bytes, &readbytes); + #endif + totalbytes += readbytes; + f->offset += readbytes; + } + return totalbytes / size; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C fwrite function. +****************************************************************************/ +size_t fwrite( + void *ptr, + size_t size, + size_t n, + FILE *f) +{ + char *buf = ptr; + int bytes,writtenbytes,totalbytes = 0; + + /* Flush anything already in the buffer */ + if (!f->writemode) + return 0; + fflush(f); + bytes = size * n; + #ifdef __OS2_VDD__ + writtenbytes = VDHWrite((HFILE)f->handle, buf, bytes); + #else + DosWrite((HFILE)f->handle, buf, bytes, &writtenbytes); + #endif + totalbytes += writtenbytes; + f->offset += writtenbytes; + if (f->offset > f->filesize) + f->filesize = f->offset; + return totalbytes / size; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fflush function. +****************************************************************************/ +int fflush( + FILE *f) +{ + ULONG bytes; + + /* First copy any data already written into our buffer */ + if (f->writemode && (bytes = (f->curp - f->startp)) > 0) { + #ifdef __OS2_VDD__ + bytes = VDHWrite((HFILE)f->handle, f->startp, bytes); + #else + DosWrite((HFILE)f->handle, f->startp, bytes, &bytes); + #endif + f->offset += bytes; + if (f->offset > f->filesize) + f->filesize = f->offset; + f->startp = f->curp = f->buf; + } + return 0; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C fseek function. +****************************************************************************/ +int fseek( + FILE *f, + long int offset, + int whence) +{ + fflush(f); + + if (whence == 0) + f->offset = offset; + else if (whence == 1) + f->offset += offset; + else if (whence == 2) + f->offset = f->filesize + offset; + + #ifdef __OS2_VDD__ + VDHSeek((HFILE)f->handle, f->offset, VDHSK_ABSOLUTE); + #else + DosSetFilePtr((HFILE)f->handle, f->offset, FILE_BEGIN, NULL); + #endif + + return 0; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C ftell function. +****************************************************************************/ +long ftell( + FILE *f) +{ + long offset; + + offset = (f->curp - f->startp); + offset += f->offset; + return offset; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C feof function. +****************************************************************************/ +int feof( + FILE *f) +{ + return (f->offset == f->filesize); +} + +/**************************************************************************** +REMARKS: +Read a single character from the input file buffer, including translation +of the character in text transation modes. +****************************************************************************/ +static int __getc( + FILE *f) +{ + int c; + + if (f->unputc != EOF) { + c = f->unputc; + f->unputc = EOF; + } + else { + if (f->startp == f->curp) { + int bytes = fread(f->buf,1,sizeof(f->buf),f); + if (bytes == 0) + return EOF; + f->curp = f->startp + bytes; + } + c = *f->startp++; + if (f->text && c == '\r') { + int nc = __getc(f); + if (nc != '\n') + f->unputc = nc; + } + } + return c; +} + +/**************************************************************************** +REMARKS: +Write a single character from to input buffer, including translation of the +character in text transation modes. +****************************************************************************/ +static int __putc(int c,FILE *f) +{ + int count = 1; + if (f->text && c == '\n') { + __putc('\r',f); + count = 2; + } + if (f->curp == f->endp) + fflush(f); + *f->curp++ = c; + return count; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fgets function. +****************************************************************************/ +char *fgets( + char *s, + int n, + FILE *f) +{ + int c = 0; + char *cs; + + cs = s; + while (--n > 0 && (c = __getc(f)) != EOF) { + *cs++ = c; + if (c == '\n') + break; + } + if (c == EOF && cs == s) + return NULL; + *cs = '\0'; + return s; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fputs function. +****************************************************************************/ +int fputs( + const char *s, + FILE *f) +{ + int r = 0; + int c; + + while ((c = *s++) != 0) + r = __putc(c, f); + return r; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fclose function. +****************************************************************************/ +int fclose( + FILE *f) +{ + fflush(f); + _OS2Close((HFILE)f->handle); + PM_free(f); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h new file mode 100644 index 0000000..03286bd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h @@ -0,0 +1,29 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c new file mode 100644 index 0000000..6688bab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c @@ -0,0 +1,1050 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" + +#define TRACE(a) + +/*--------------------------- Global variables ----------------------------*/ + +#define MAX_MEMORY_SHARED 100 +#define MAX_MEMORY_MAPPINGS 100 + +/* TODO: I think the global and linear members will be the same, but not sure yet. */ +typedef struct { + void *linear; + ulong global; + ulong length; + int npages; + } memshared; + +typedef struct { + ulong physical; + ulong linear; + ulong length; + int npages; + ibool isCached; + } mmapping; + +static int numMappings = 0; +static memshared shared[MAX_MEMORY_MAPPINGS] = {0}; +static mmapping maps[MAX_MEMORY_MAPPINGS]; +ibool _PM_haveBIOS = TRUE; +char _PM_cntPath[PM_MAX_PATH] = ""; /* there just isn't any */ +uchar *_PM_rmBufAddr = NULL; +ushort _VARAPI PM_savedDS = 0; /* why can't I use the underscore prefix? */ + +HVDHSEM hevFarCallRet = NULL; +HVDHSEM hevIRet = NULL; +HHOOK hhookUserReturnHook = NULL; +HHOOK hhookUserIRetHook = NULL; + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/* Functions to read and write CMOS registers */ + +ulong PMAPI _PM_getPDB(void); +uchar PMAPI _PM_readCMOS(int index); +void PMAPI _PM_writeCMOS(int index,uchar value); + +VOID HOOKENTRY UserReturnHook(PVOID pRefData, PCRF pcrf); +VOID HOOKENTRY UserIRetHook(PVOID pRefData, PCRF pcrf); + +void PMAPI PM_init(void) +{ + MTRR_init(); + + /* Initialize VDD-specific data */ + /* Note: PM_init must be (obviously) called in VDM task context! */ + VDHCreateSem(&hevFarCallRet, VDH_EVENTSEM); + VDHCreateSem(&hevIRet, VDH_EVENTSEM); + hhookUserReturnHook = VDHAllocHook(VDH_RETURN_HOOK, (PFNARM)UserReturnHook, 0); + hhookUserIRetHook = VDHAllocHook(VDH_RETURN_HOOK, (PFNARM)UserIRetHook, 0); + + if ((hevIRet == NULL) || (hevFarCallRet == NULL) || + (hhookUserReturnHook == NULL) || (hhookUserIRetHook == NULL)) { + /* something failed, we can't go on */ + /* TODO: take some action here! */ + } +} + +/* Do some cleaning up */ +void PMAPI PM_exit(void) +{ + /* Note: Hooks allocated during or after VDM creation are deallocated automatically */ + if (hevIRet != NULL) + VDHDestroySem(hevIRet); + + if (hevFarCallRet != NULL) + VDHDestroySem(hevFarCallRet); +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return _PM_haveBIOS; } + +long PMAPI PM_getOSType(void) +{ return /*_OS_OS2VDD*/ _OS_OS2; } /*FIX!! */ + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); +/* Fatal_Error_Handler(msg,0); TODO: implement somehow! */ +} + +/**************************************************************************** +PARAMETERS: +len - Place to store the length of the buffer +rseg - Place to store the real mode segment of the buffer +roff - Place to store the real mode offset of the buffer + +REMARKS: +This function returns the address and length of the global VESA transfer +buffer. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + if (_PM_rmBufAddr) { + *len = 0; /*VESA_BUF_SIZE; */ + *rseg = (ulong)(_PM_rmBufAddr) >> 4; + *roff = (ulong)(_PM_rmBufAddr) & 0xF; + return _PM_rmBufAddr; + } + return NULL; +} + +int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out) +{ + /* Unused in VDDs */ + return 0; +} + +char * PMAPI PM_getCurrentPath(char *path,int maxLen) +{ + strncpy(path, _PM_cntPath, maxLen); + path[maxLen - 1] = 0; + return path; +} + +char PMAPI PM_getBootDrive(void) +{ + ulong boot = 3; + boot = VDHQuerySysValue(0, VDHGSV_BOOTDRV); + return (char)('a' + boot - 1); +} + +const char * PMAPI PM_getVBEAFPath(void) +{ + static char path[CCHMAXPATH]; + strcpy(path,"x:\\"); + path[0] = PM_getBootDrive(); + return path; +} + +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[CCHMAXPATH]; + strcpy(path,"x:\\os2\\drivers"); + path[0] = PM_getBootDrive(); + PM_backslash(path); + strcat(path,"nucleus"); + return path; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ return PM_getMachineName(); } + +const char * PMAPI PM_getMachineName(void) +{ + return "Unknown"; +} + +int PMAPI PM_kbhit(void) +{ return 1; } + +int PMAPI PM_getch(void) +{ return 0; } + +PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen) +{ + /* Unused in VDDs */ + return NULL; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + /* Unused in VDDs */ + return 1; +} + +void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole) +{ + /* Unused in VDDs */ +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* Unused in VDDs */ +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) +{ + /* Unused in VDDs */ +} + +void PMAPI PM_closeConsole(PM_HWND hwndConsole) +{ + /* Unused in VDDs */ +} + +void PMAPI PM_setOSCursorLocation(int x,int y) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x50,x); + PM_setByte(_biosPtr+0x51,y); +} + +void PMAPI PM_setOSScreenWidth(int width,int height) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x4A,width); + PM_setByte(_biosPtr+0x84,height-1); +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For OS/2 VDD we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared(long size) +{ + ULONG nPages = (size + 0xFFF) >> 12; + int i; + + /* First find a free slot in our shared memory table */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].linear == 0) + break; + } + if (i < MAX_MEMORY_SHARED) { + shared[i].linear = VDHAllocPages(NULL, nPages, VDHAP_SYSTEM | VDHAP_FIXED); + shared[i].npages = nPages; + shared[i].global = (ULONG)shared[i].linear; + return (void*)shared[i].global; + } + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory +****************************************************************************/ +void PMAPI PM_freeShared(void *p) +{ + int i; + + /* Find a shared memory block in our table and free it */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].global == (ulong)p) { + VDHFreePages(shared[i].linear); + shared[i].linear = 0; + break; + } + } +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + /* TODO: Figure out how to do this */ + return false; +} + +void * PMAPI PM_getBIOSPointer(void) +{ return (void*)0x400; } + +void * PMAPI PM_getA0000Pointer(void) +{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); } + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to maps in +limit - Limit of physical memory to region to maps in + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +Maps a physical memory range to a linear memory range. +****************************************************************************/ +ulong MapPhysicalToLinear( + ulong base, + ulong limit, + int *npages) +{ + ulong linear,length = limit+1; + int i,ppage,flags; +#if 0 + ppage = base >> 12; + *npages = (length + (base & 0xFFF) + 4095) >> 12; + flags = PR_FIXED | PR_STATIC; + if (base == 0xA0000) { + /* We require the linear address to be aligned to a 64Kb boundary + * for mapping the banked framebuffer (so we can do efficient + * carry checking for bank changes in the assembler code). The only + * way to ensure this is to force the linear address to be aligned + * to a 4Mb boundary. + */ + flags |= PR_4MEG; + } + if ((linear = (ulong)PageReserve(PR_SYSTEM,*npages,flags)) == (ulong)-1) + return 0; + if (!PageCommitPhys(linear >> 12,*npages,ppage,PC_INCR | PC_USER | PC_WRITEABLE)) + return 0; +#endif + return linear + (base & 0xFFF); +} + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to map in +limit - Limit of physical memory to region to map in +isCached - True if the memory should be cached, false if not + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +This function maps physical memory to linear memory, which can then be used +to create a selector or used directly from 32-bit protected mode programs. +This is better than DPMI 0x800, since it allows you to maps physical +memory below 1Mb, which gets this memory out of the way of the Windows VxD's +sticky paws. + +NOTE: If the memory is not expected to be cached, this function will + directly re-program the PCD (Page Cache Disable) bit in the + page tables. There does not appear to be a mechanism in the VMM + to control this bit via the regular interface. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + ulong linear,length = limit+1; + int i,npages; + ulong PDB,*pPDB; + + /* Search table of existing mappings to see if we have already mapped + * a region of memory that will serve this purpose. + */ + for (i = 0; i < numMappings; i++) { + if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) + return (void*)maps[i].linear; + } + if (numMappings == MAX_MEMORY_MAPPINGS) + return NULL; + + /* We did not find any previously mapped memory region, so map it in. + * Note that we do not use MapPhysToLinear, since this function appears + * to have problems mapping memory in the 1Mb physical address space. + * Hence we use PageReserve and PageCommitPhys. + */ + if ((linear = MapPhysicalToLinear(base,limit,&npages)) == 0) + return NULL; + maps[numMappings].physical = base; + maps[numMappings].length = length; + maps[numMappings].linear = linear; + maps[numMappings].npages = npages; + maps[numMappings].isCached = isCached; + numMappings++; + +#if 0 + /* Finally disable caching where necessary */ + if (!isCached && (PDB = _PM_getPDB()) != 0) { + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPageTable; + + if (PDB >= 0x100000) + pPDB = (ulong*)MapPhysicalToLinear(PDB,0xFFF,&npages); + else + pPDB = (ulong*)PDB; + if (pPDB) { + startPDB = (linear >> 22) & 0x3FF; + startPage = (linear >> 12) & 0x3FF; + endPDB = ((linear+limit) >> 22) & 0x3FF; + endPage = ((linear+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + pageTable = pPDB[iPDB] & ~0xFFF; + if (pageTable >= 0x100000) + pPageTable = (ulong*)MapPhysicalToLinear(pageTable,0xFFF,&npages); + else + pPageTable = (ulong*)pageTable; + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) + pPageTable[iPage] |= 0x10; + PageFree((ulong)pPageTable,PR_STATIC); + } + PageFree((ulong)pPDB,PR_STATIC); + } + } +#endif + return (void*)linear; +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* We never free the mappings */ +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* We never sleep in a VDD */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +void PMAPI _PM_freeMemoryMappings(void) +{ + int i; +/* for (i = 0; i < numMappings; i++) */ +/* PageFree(maps[i].linear,PR_STATIC); */ +} + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ return (void*)MK_PHYS(r_seg,r_off); } + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ return NULL; } + +void PMAPI PM_freeRealSeg(void *mem) +{ } + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + /* Unsed in VDDs */ +} + +/**************************************************************************** +REMARKS: +Load the V86 registers in the client state, and save the original state +before loading the registers. +****************************************************************************/ +static void LoadV86Registers( + PCRF saveRegs, + RMREGS *in, + RMSREGS *sregs) +{ + PCRF pcrf; /* current client register frame */ + + /* get pointer to registers */ + pcrf = (PCRF)VDHQuerySysValue(CURRENT_VDM, VDHLSV_PCRF); + + /* Note: We could do VDHPushRegs instead but this should be safer as it */ + /* doesn't rely on the VDM session having enough free stack space. */ + *saveRegs = *pcrf; /* save all registers */ + + pcrf->crf_eax = in->e.eax; /* load new values */ + pcrf->crf_ebx = in->e.ebx; + pcrf->crf_ecx = in->e.ecx; + pcrf->crf_edx = in->e.edx; + pcrf->crf_esi = in->e.esi; + pcrf->crf_edi = in->e.edi; + pcrf->crf_es = sregs->es; + pcrf->crf_ds = sregs->ds; + +} + +/**************************************************************************** +REMARKS: +Read the V86 registers from the client state and restore the original state. +****************************************************************************/ +static void ReadV86Registers( + PCRF saveRegs, + RMREGS *out, + RMSREGS *sregs) +{ + PCRF pcrf; /* current client register frame */ + + /* get pointer to registers */ + pcrf = (PCRF)VDHQuerySysValue(CURRENT_VDM, VDHLSV_PCRF); + + /* read new register values */ + out->e.eax = pcrf->crf_eax; + out->e.ebx = pcrf->crf_ebx; + out->e.ecx = pcrf->crf_ecx; + out->e.edx = pcrf->crf_edx; + out->e.esi = pcrf->crf_esi; + out->e.edi = pcrf->crf_edi; + sregs->es = pcrf->crf_es; + sregs->ds = pcrf->crf_ds; + + /* restore original client registers */ + *pcrf = *saveRegs; +} + +/**************************************************************************** +REMARKS: Used for far calls into V86 code +****************************************************************************/ +VOID HOOKENTRY UserReturnHook( + PVOID pRefData, + PCRF pcrf ) +{ + VDHPostEventSem(hevFarCallRet); +} + +/**************************************************************************** +REMARKS: Used for calling BIOS interrupts +****************************************************************************/ +VOID HOOKENTRY UserIRetHook( + PVOID pRefData, + PCRF pcrf ) +{ + VDHPostEventSem(hevIRet); +} + +/**************************************************************************** +REMARKS: +Call a V86 real mode function with the specified register values +loaded before the call. The call returns with a far ret. +Must be called from within a DOS session context! +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *regs, + RMSREGS *sregs) +{ + CRF saveRegs; + FPFN fnAddress; + ULONG rc; + + TRACE("SDDHELP: Entering PM_callRealMode()\n"); + LoadV86Registers(SSToDS(&saveRegs),regs,sregs); + + /* set up return hook for call */ + rc = VDHArmReturnHook(hhookUserReturnHook, VDHARH_CSEIP_HOOK); + + VDHResetEventSem(hevFarCallRet); + + /* the address is a 16:32 pointer */ + OFFSETOF32(fnAddress) = off; + SEGMENTOF32(fnAddress) = seg; + rc = VDHPushFarCall(fnAddress); + VDHYield(0); + + /* wait until the V86 call returns - our return hook posts the semaphore */ + rc = VDHWaitEventSem(hevFarCallRet, SEM_INDEFINITE_WAIT); + + ReadV86Registers(SSToDS(&saveRegs),regs,sregs); + TRACE("SDDHELP: Exiting PM_callRealMode()\n"); +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +Must be called from within a DOS session context! +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + RMSREGS sregs = {0}; + CRF saveRegs; + ushort oldDisable; + ULONG rc; + + memset(SSToDS(&sregs), 0, sizeof(sregs)); + +#if 0 /* do we need this?? */ + /* Disable pass-up to our VDD handler so we directly call BIOS */ + TRACE("SDDHELP: Entering PM_int86()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } +#endif + + LoadV86Registers(SSToDS(&saveRegs), in, SSToDS(&sregs)); + + VDHResetEventSem(hevIRet); + rc = VDHPushInt(intno); + + /* set up return hook for interrupt */ + rc = VDHArmReturnHook(hhookUserIRetHook, VDHARH_NORMAL_IRET); + + VDHYield(0); + + /* wait until the V86 IRETs - our return hook posts the semaphore */ + rc = VDHWaitEventSem(hevIRet, 5000); /*SEM_INDEFINITE_WAIT); */ + + ReadV86Registers(SSToDS(&saveRegs), out, SSToDS(&sregs)); + +#if 0 + /* Re-enable pass-up to our VDD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; +#endif + + TRACE("SDDHELP: Exiting PM_int86()\n"); + return out->x.ax; + +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + CRF saveRegs; + ushort oldDisable; + ULONG rc; + +#if 0 + /* Disable pass-up to our VxD handler so we directly call BIOS */ + TRACE("SDDHELP: Entering PM_int86x()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } +#endif + LoadV86Registers(SSToDS(&saveRegs), in, sregs); + + VDHResetEventSem(hevIRet); + rc = VDHPushInt(intno); + + /* set up return hook for interrupt */ + rc = VDHArmReturnHook(hhookUserIRetHook, VDHARH_NORMAL_IRET); + + VDHYield(0); + + /* wait until the V86 IRETs - our return hook posts the semaphore */ + rc = VDHWaitEventSem(hevIRet, 5000); /*SEM_INDEFINITE_WAIT); */ + + ReadV86Registers(SSToDS(&saveRegs), out, sregs); + +#if 0 + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; +#endif + + TRACE("SDDHELP: Exiting PM_int86x()\n"); + return out->x.ax; +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ *physical = *total = 0; } + +/**************************************************************************** +REMARKS: +Allocates a block of locked physical memory. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + ULONG flags = VDHAP_SYSTEM; + ULONG nPages = (size + 0xFFF) >> 12; + + flags |= (physAddr != NULL) ? VDHAP_PHYSICAL : VDHAP_FIXED; + + return VDHAllocPages(physAddr, nPages, VDHAP_SYSTEM | VDHAP_PHYSICAL); +} + +/**************************************************************************** +REMARKS: +Frees a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + if (p) + VDHFreePages((PVOID)p); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + ULONG lockHandle; + + /* TODO: the lock handle is essential for the unlock operation!! */ + lockHandle = VDHLockMem(p, len, 0, (PVOID)VDHLM_NO_ADDR, NULL); + + if (lockHandle != NULL) + return 0; + else + return 1; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + /* TODO: implement - use a table of lock handles? */ + /* VDHUnlockPages(lockHandle); */ + return 0; +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + return PM_lockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + return PM_unlockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VDD +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + (void)szDLLName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VDD +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + (void)hModule; + (void)szProcName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VDD +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + /* Not applicable in a VDD */ + (void)drive; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + /* Not applicable in a VDD */ + (void)drive; + (void)dir; + (void)len; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + return MTRR_enableWriteCombine(base,size,type); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Implement this ? */ + (void)filename; + (void)attrib; + PM_fatalError("PM_setFileAttr not implemented!"); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + /* TODO: Implement this ? */ + (void)filename; + PM_fatalError("PM_getFileAttr not implemented!"); + return 0; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + /* TODO: Implement this ? */ + (void)filename; + PM_fatalError("PM_mkdir not implemented!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + /* TODO: Implement this ? */ + (void)filename; + PM_fatalError("PM_rmdir not implemented!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this ? */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_getFileTime not implemented!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this ? */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_setFileTime not implemented!"); + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c new file mode 100644 index 0000000..2163928 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c new file mode 100644 index 0000000..631f655 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c @@ -0,0 +1,103 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ulong frequency = 1193180; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +#define __ZTimerInit() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOn(tm) VTD_Get_Real_Time(&tm->start.high,&tm->start.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger lap,count; + VTD_Get_Real_Time(&lap.high,&lap.low); + _CPU_diffTime64(&tm->start,&lap,&count); + return _CPU_calcMicroSec(&count,frequency); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) VTD_Get_Real_Time(&tm->end.high,&tm->end.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,frequency); +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + return VDHQuerySysValue(0, VDHGSV_MSECSBOOT); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm new file mode 100644 index 0000000..64a7cec --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm @@ -0,0 +1,299 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit Windows VxD +;* +;* Description: Low level assembly support for the PM library specific to +;* Windows VxDs. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pm ; Set up memory model + +begdataseg _pm + + cextern _PM_savedDS,USHORT + +enddataseg _pm + +P586 + +begcodeseg _pm ; Start of code segment + +;---------------------------------------------------------------------------- +; void PM_segread(PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Read the current value of all segment registers +;---------------------------------------------------------------------------- +cprocstart PM_segread + + ARG sregs:DPTR + + enter_c + + mov ax,es + _les _si,[sregs] + mov [_ES _si],ax + mov [_ES _si+2],cs + mov [_ES _si+4],ss + mov [_ES _si+6],ds + mov [_ES _si+8],fs + mov [_ES _si+10],gs + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Issues a software interrupt in protected mode. This routine has been +; written to allow user programs to load CS and DS with different values +; other than the default. +;---------------------------------------------------------------------------- +cprocstart PM_int386x + +; Not used for VxDs + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_saveDS(void) +;---------------------------------------------------------------------------- +; Save the value of DS into a section of the code segment, so that we can +; quickly load this value at a later date in the PM_loadDS() routine from +; inside interrupt handlers etc. The method to do this is different +; depending on the DOS extender being used. +;---------------------------------------------------------------------------- +cprocstart PM_saveDS + + mov [_PM_savedDS],ds ; Store away in data segment + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_loadDS(void) +;---------------------------------------------------------------------------- +; Routine to load the DS register with the default value for the current +; DOS extender. Only the DS register is loaded, not the ES register, so +; if you wish to call C code, you will need to also load the ES register +; in 32 bit protected mode. +;---------------------------------------------------------------------------- +cprocstart PM_loadDS + + mov ds,[cs:_PM_savedDS] ; We can access the proper DS through CS + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankA(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankA + +; Not used for VxDs + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankAB(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankAB + +; Not used for VxDs + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setCRTStart(int x,int y,int waitVRT) +;---------------------------------------------------------------------------- +cprocstart PM_setCRTStart + +; Not used for VxDs + + ret + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; uchar _PM_readCMOS(int index) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_readCMOS + + ARG index:UINT + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + in al,71h + mov ah,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + mov al,ah ; Return value in AL + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_writeCMOS(int index,uchar value) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_writeCMOS + + ARG index:UINT, value:UCHAR + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + mov al,[value] + out 71h,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; double _ftol(double f) +;---------------------------------------------------------------------------- +; Calls to __ftol are generated by the Borland C++ compiler for code +; that needs to convert a floating point type to an integral type. +; +; Input: floating point number on the top of the '87. +; +; Output: a (signed or unsigned) long in EAX +; All other registers preserved. +;----------------------------------------------------------------------- +cprocstart _ftol + + LOCAL temp1:WORD, temp2:QWORD = LocalSize + + push ebp + mov ebp,esp + sub esp,LocalSize + + fstcw [temp1] ; save the control word + fwait + mov al,[BYTE temp1+1] + or [BYTE temp1+1],0Ch ; set rounding control to chop + fldcw [temp1] + fistp [temp2] ; convert to 64-bit integer + mov [BYTE temp1+1],al + fldcw [temp1] ; restore the control word + mov eax,[DWORD temp2] ; return LS 32 bits + mov edx,[DWORD temp2+4] ; MS 32 bits + + mov esp,ebp + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_getPDB - Return the Page Table Directory Base address +;---------------------------------------------------------------------------- +cprocstart _PM_getPDB + + mov eax,cr3 + and eax,0FFFFF000h + ret + +cprocend + +;---------------------------------------------------------------------------- +; Flush the Translation Lookaside buffer +;---------------------------------------------------------------------------- +cprocstart PM_flushTLB + + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB + ret + +cprocend + +endcodeseg _pm + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c new file mode 100644 index 0000000..3c7eaae --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c @@ -0,0 +1,66 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: VxD specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Do nothing for VxD's +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for VxD's +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = 1193180; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + CPU_largeInteger count; \ + VTD_Get_Real_Time(&count.high,&count.low); \ + (t)->low = count.low; \ + (t)->high = count.high; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c new file mode 100644 index 0000000..3c6ce99 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c @@ -0,0 +1,304 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: C library compatible I/O functions for use within a VxD. +* +****************************************************************************/ + +#include "pmapi.h" +#include "vxdfile.h" + +/*------------------------ Main Code Implementation -----------------------*/ + +#define EOF -1 + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fopen function. +****************************************************************************/ +FILE * fopen( + const char *filename, + const char *mode) +{ + FILE *f = PM_malloc(sizeof(FILE)); + long oldpos; + + if (f) { + f->offset = 0; + f->text = (mode[1] == 't' || mode[2] == 't'); + f->writemode = (mode[0] == 'w') || (mode[0] == 'a'); + if (initComplete) { + WORD omode,error; + BYTE action; + + if (mode[0] == 'r') { + omode = OPEN_ACCESS_READONLY | OPEN_SHARE_COMPATIBLE; + action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_FAIL; + } + else if (mode[0] == 'w') { + omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_COMPATIBLE; + action = ACTION_IFEXISTS_TRUNCATE | ACTION_IFNOTEXISTS_CREATE; + } + else { + omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_COMPATIBLE; + action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_CREATE; + } + f->handle = (int)R0_OpenCreateFile(false,(char*)filename,omode,ATTR_NORMAL,action,0,&error,&action); + if (f->handle == 0) { + PM_free(f); + return NULL; + } + f->filesize = R0_GetFileSize((HANDLE)f->handle,&error); + if (mode[0] == 'a') + fseek(f,0,2); + } + else { + int oflag,pmode; + + if (mode[0] == 'r') { + pmode = _S_IREAD; + oflag = _O_RDONLY; + } + else if (mode[0] == 'w') { + pmode = _S_IWRITE; + oflag = _O_WRONLY | _O_CREAT | _O_TRUNC; + } + else { + pmode = _S_IWRITE; + oflag = _O_RDWR | _O_CREAT | _O_APPEND; + } + if (f->text) + oflag |= _O_TEXT; + else + oflag |= _O_BINARY; + if ((f->handle = i_open(filename,oflag,pmode)) == -1) { + PM_free(f); + return NULL; + } + oldpos = i_lseek(f->handle,0,1); + f->filesize = i_lseek(f->handle,0,2); + i_lseek(f->handle,oldpos,0); + } + } + return f; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fread function. Note that the VxD file I/O +functions are layered on DOS, so can only read up to 64K at a time. Since +we are expected to handle much larger chunks than this, we handle larger +blocks automatically in here. +****************************************************************************/ +size_t fread( + void *ptr, + size_t size, + size_t n, + FILE *f) +{ + char *buf = ptr; + WORD error; + int bytes = size * n; + int readbytes,totalbytes = 0; + + while (bytes > 0x10000) { + if (initComplete) { + readbytes = R0_ReadFile(false,(HANDLE)f->handle,buf,0x8000,f->offset,&error); + readbytes += R0_ReadFile(false,(HANDLE)f->handle,buf+0x8000,0x8000,f->offset+0x8000,&error); + } + else { + readbytes = i_read(f->handle,buf,0x8000); + readbytes += i_read(f->handle,buf+0x8000,0x8000); + } + totalbytes += readbytes; + f->offset += readbytes; + buf += 0x10000; + bytes -= 0x10000; + } + if (bytes) { + if (initComplete) + readbytes = R0_ReadFile(false,(HANDLE)f->handle,buf,bytes,f->offset,&error); + else + readbytes = i_read(f->handle,buf,bytes); + totalbytes += readbytes; + f->offset += readbytes; + } + return totalbytes / size; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fwrite function. Note that the VxD file I/O +functions are layered on DOS, so can only read up to 64K at a time. Since +we are expected to handle much larger chunks than this, we handle larger +blocks automatically in here. +****************************************************************************/ +size_t fwrite( + const void *ptr, + size_t size, + size_t n, + FILE *f) +{ + const char *buf = ptr; + WORD error; + int bytes = size * n; + int writtenbytes,totalbytes = 0; + + if (!f->writemode) + return 0; + while (bytes > 0x10000) { + if (initComplete) { + writtenbytes = R0_WriteFile(false,(HANDLE)f->handle,buf,0x8000,f->offset,&error); + writtenbytes += R0_WriteFile(false,(HANDLE)f->handle,buf+0x8000,0x8000,f->offset+0x8000,&error); + } + else { + writtenbytes = i_write(f->handle,buf,0x8000); + writtenbytes += i_write(f->handle,buf+0x8000,0x8000); + } + totalbytes += writtenbytes; + f->offset += writtenbytes; + buf += 0x10000; + bytes -= 0x10000; + } + if (initComplete) + writtenbytes = R0_WriteFile(false,(HANDLE)f->handle,buf,bytes,f->offset,&error); + else + writtenbytes = i_write(f->handle,buf,bytes); + totalbytes += writtenbytes; + f->offset += writtenbytes; + if (f->offset > f->filesize) + f->filesize = f->offset; + return totalbytes / size; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fflush function. +****************************************************************************/ +int fflush( + FILE *f) +{ + /* Nothing to do since we are not doing buffered file I/O */ + (void)f; + return 0; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fseek function. +****************************************************************************/ +int fseek( + FILE *f, + long int offset, + int whence) +{ + if (whence == 0) + f->offset = offset; + else if (whence == 1) + f->offset += offset; + else if (whence == 2) + f->offset = f->filesize + offset; + if (!initComplete) + i_lseek(f->handle,f->offset,0); + return 0; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C ftell function. +****************************************************************************/ +long ftell( + FILE *f) +{ + return f->offset; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C feof function. +****************************************************************************/ +int feof( + FILE *f) +{ + return (f->offset == f->filesize); +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fgets function. +****************************************************************************/ +char *fgets( + char *s, + int n, + FILE *f) +{ + int len; + char *cs; + + /* Read the entire buffer into memory (our functions are unbuffered!) */ + if ((len = fread(s,1,n,f)) == 0) + return NULL; + + /* Search for '\n' or end of string */ + if (n > len) + n = len; + cs = s; + while (--n > 0) { + if (*cs == '\n') + break; + cs++; + } + *cs = '\0'; + return s; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fputs function. +****************************************************************************/ +int fputs( + const char *s, + FILE *f) +{ + return fwrite(s,1,strlen(s),f); +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fclose function. +****************************************************************************/ +int fclose( + FILE *f) +{ + WORD error; + + if (initComplete) + R0_CloseFile((HANDLE)f->handle,&error); + else + i_close(f->handle); + PM_free(f); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h new file mode 100644 index 0000000..7efc0f9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h @@ -0,0 +1,29 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c new file mode 100644 index 0000000..4cb7f19 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c @@ -0,0 +1,1359 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" + +/*--------------------------- Global variables ----------------------------*/ + +#define MAX_MEMORY_SHARED 100 +#define MAX_MEMORY_MAPPINGS 100 + +typedef struct { + void *linear; + ulong global; + ulong length; + int npages; + } memshared; + +typedef struct { + ulong physical; + ulong linear; + ulong length; + int npages; + ibool isCached; + } mmapping; + +static int numMappings = 0; +static memshared shared[MAX_MEMORY_MAPPINGS] = {0}; +static mmapping maps[MAX_MEMORY_MAPPINGS]; +extern ibool _PM_haveBIOS; +char _PM_cntPath[PM_MAX_PATH] = ""; +char _PM_nucleusPath[PM_MAX_PATH] = ""; +uchar *_PM_rmBufAddr = NULL; +ushort _VARAPI _PM_savedDS = 0; +static uchar _PM_oldCMOSRegA; +static uchar _PM_oldCMOSRegB; +PM_intHandler _PM_rtcHandler = NULL; +IRQHANDLE RTCIRQHandle = 0; +VPICD_HWInt_THUNK RTCInt_Thunk; + +static char *szWindowsKey = "Software\\Microsoft\\Windows\\CurrentVersion"; +static char *szSystemRoot = "SystemRoot"; +static char *szMachineNameKey = "System\\CurrentControlSet\\control\\ComputerName\\ComputerName"; +static char *szMachineName = "ComputerName"; +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/* Functions to read and write CMOS registers */ + +ulong PMAPI _PM_getPDB(void); +uchar PMAPI _PM_readCMOS(int index); +void PMAPI _PM_writeCMOS(int index,uchar value); + +/**************************************************************************** +REMARKS: +PM_malloc override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void * VXD_malloc( + size_t size) +{ + return PM_mallocShared(size); +} + +/**************************************************************************** +REMARKS: +PM_calloc override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void * VXD_calloc( + size_t nelem, + size_t size) +{ + void *p = PM_mallocShared(nelem * size); + if (p) + memset(p,0,nelem * size); + return p; +} + +/**************************************************************************** +REMARKS: +PM_realloc override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void * VXD_realloc( + void *ptr, + size_t size) +{ + void *p = PM_mallocShared(size); + if (p) { + memcpy(p,ptr,size); + PM_freeShared(ptr); + } + return p; +} + +/**************************************************************************** +REMARKS: +PM_free override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void VXD_free( + void *p) +{ + PM_freeShared(p); +} + +/**************************************************************************** +REMARKS: +Initialise the PM library. +****************************************************************************/ +void PMAPI PM_init(void) +{ + /* Override the default memory allocators for all Nucleus drivers + * loaded in SDDHELP/PMHELP. We do this so that we can ensure all memory + * dynamically allocated by Nucleus drivers and internal C runtime + * library functions are shared memory blocks that all processes + * connecting to SDDHELP can see. + */ + PM_useLocalMalloc(VXD_malloc,VXD_calloc,VXD_realloc,VXD_free); + + /* Initialiase the MTRR module */ + MTRR_init(); +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return _PM_haveBIOS; } + +long PMAPI PM_getOSType(void) +{ return _OS_WIN32VXD; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + Fatal_Error_Handler(msg,0); +} + +/**************************************************************************** +PARAMETERS: +len - Place to store the length of the buffer +rseg - Place to store the real mode segment of the buffer +roff - Place to store the real mode offset of the buffer + +REMARKS: +This function returns the address and length of the global VESA transfer +buffer that is used for communicating with the VESA BIOS functions from +Win16 and Win32 programs under Windows. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + /* If the VxD is dynamically loaded we will not have a real mode + * transfer buffer to return, so we fail the call. + */ + if (_PM_rmBufAddr) { + *len = VESA_BUF_SIZE; + *rseg = (ulong)(_PM_rmBufAddr) >> 4; + *roff = (ulong)(_PM_rmBufAddr) & 0xF; + return _PM_rmBufAddr; + } + return NULL; +} + +int PMAPI PM_int386( + int intno, + PMREGS *in, + PMREGS *out) +{ + /* Unused in VxDs */ + return 0; +} + +void PMAPI _PM_getRMvect( + int intno, + long *realisr) +{ + WORD seg; + DWORD off; + + Get_V86_Int_Vector(intno,&seg,&off); + *realisr = ((long)seg << 16) | (off & 0xFFFF); +} + +void PMAPI _PM_setRMvect( + int intno, + long realisr) +{ + Set_V86_Int_Vector(intno,realisr >> 16,realisr & 0xFFFF); +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + strncpy(path,_PM_cntPath,maxLen); + path[maxLen-1] = 0; + return path; +} + +char PMAPI PM_getBootDrive(void) +{ return 'c'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return "c:\\"; } + +/**************************************************************************** +PARAMETERS: +szKey - Key to query (can contain version number formatting) +szValue - Value to get information for +value - Place to store the registry key data read +size - Size of the string buffer to read into + +RETURNS: +true if the key was found, false if not. +****************************************************************************/ +static ibool REG_queryString( + char *szKey, + char *szValue, + char *value, + ulong size) +{ + HKEY hKey; + ulong type; + ibool status = false; + + memset(value,0,sizeof(value)); + if (RegOpenKey(HKEY_LOCAL_MACHINE,szKey,&hKey) == ERROR_SUCCESS) { + if (RegQueryValueEx(hKey,(PCHAR)szValue,(ulong*)NULL,(ulong*)&type,value,(ulong*)&size) == ERROR_SUCCESS) + status = true; + RegCloseKey(hKey); + } + return status; +} + +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + + if (strlen(_PM_nucleusPath) > 0) { + strcpy(path,_PM_nucleusPath); + PM_backslash(path); + return path; + } + if (!REG_queryString(szWindowsKey,szSystemRoot,path,sizeof(path))) + strcpy(path,"c:\\windows"); + PM_backslash(path); + strcat(path,"system\\nucleus"); + return path; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ return PM_getMachineName(); } + +const char * PMAPI PM_getMachineName(void) +{ + static char name[256]; + if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name))) + return name; + return "Unknown"; +} + +int PMAPI PM_kbhit(void) +{ return 1; } + +int PMAPI PM_getch(void) +{ return 0; } + +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + /* Unused in VxDs */ + return NULL; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + /* Unused in VxDs */ + return 1; +} + +void PMAPI PM_saveConsoleState( + void *stateBuf, + PM_HWND hwndConsole) +{ + /* Unused in VxDs */ +} + +void PMAPI PM_setSuspendAppCallback( + int (_ASMAPIP saveState)( + int flags)) +{ + /* Unused in VxDs */ +} + +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + PM_HWND hwndConsole) +{ + /* Unused in VxDs */ +} + +void PMAPI PM_closeConsole( + PM_HWND hwndConsole) +{ + /* Unused in VxDs */ +} + +void PM_setOSCursorLocation( + int x, + int y) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x50,x); + PM_setByte(_biosPtr+0x51,y); +} + +void PM_setOSScreenWidth( + int width, + int height) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x4A,width); + PM_setByte(_biosPtr+0x84,height-1); +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For Win9x we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + MEMHANDLE hMem; + DWORD pgNum,nPages = (size + 0xFFF) >> 12; + int i; + + /* First find a free slot in our shared memory table */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].linear == 0) + break; + } + if (i < MAX_MEMORY_SHARED) { + PageAllocate(nPages,PG_SYS,0,0,0,0,NULL,0,&hMem,&shared[i].linear); + shared[i].npages = nPages; + pgNum = (ulong)shared[i].linear >> 12; + shared[i].global = LinPageLock(pgNum,nPages,PAGEMAPGLOBAL); + return (void*)shared[i].global; + } + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory +****************************************************************************/ +void PMAPI PM_freeShared(void *p) +{ + int i; + + /* Find a shared memory block in our table and free it */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].global == (ulong)p) { + LinPageUnLock(shared[i].global >> 12,shared[i].npages,PAGEMAPGLOBAL); + PageFree((ulong)shared[i].linear,0); + shared[i].linear = 0; + break; + } + } +} + +/**************************************************************************** +REMARKS: +Maps a shared memory block into process address space. Does nothing since +the memory blocks are already globally7 mapped into all processes. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + return (void*)base; +} + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + /* TODO: Figure out how to do this */ + return false; +} + +void * PMAPI PM_getBIOSPointer(void) +{ return (void*)0x400; } + +void * PMAPI PM_getA0000Pointer(void) +{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); } + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to maps in +limit - Limit of physical memory to region to maps in + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +Maps a physical memory range to a linear memory range. +****************************************************************************/ +ulong _PM_mapPhysicalToLinear( + ulong base, + ulong limit, + int *npages) +{ + ulong linear,length = limit+1; + int i,ppage,flags; + + if (base < 0x100000) { + /* Windows 9x is zero based for the first meg of memory */ + return base; + } + ppage = base >> 12; + *npages = (length + (base & 0xFFF) + 4095) >> 12; + flags = PR_FIXED | PR_STATIC; + if (base == 0xA0000) { + /* We require the linear address to be aligned to a 64Kb boundary + * for mapping the banked framebuffer (so we can do efficient + * carry checking for bank changes in the assembler code). The only + * way to ensure this is to force the linear address to be aligned + * to a 4Mb boundary. + */ + flags |= PR_4MEG; + } + if ((linear = (ulong)PageReserve(PR_SYSTEM,*npages,flags)) == (ulong)-1) + return 0xFFFFFFFF; + if (!PageCommitPhys(linear >> 12,*npages,ppage,PC_INCR | PC_USER | PC_WRITEABLE)) + return 0xFFFFFFFF; + return linear + (base & 0xFFF); +} + +/* Page table flags */ + +#define PAGE_FLAGS_PRESENT 0x00000001 +#define PAGE_FLAGS_WRITEABLE 0x00000002 +#define PAGE_FLAGS_USER 0x00000004 +#define PAGE_FLAGS_WRITE_THROUGH 0x00000008 +#define PAGE_FLAGS_CACHE_DISABLE 0x00000010 +#define PAGE_FLAGS_ACCESSED 0x00000020 +#define PAGE_FLAGS_DIRTY 0x00000040 +#define PAGE_FLAGS_4MB 0x00000080 + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to maps in +limit - Limit of physical memory to region to maps in +isCached - True if the memory should be cached, false if not + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +This function maps physical memory to linear memory, which can then be used +to create a selector or used directly from 32-bit protected mode programs. +This is better than DPMI 0x800, since it allows you to maps physical +memory below 1Mb, which gets this memory out of the way of the Windows VDD's +sticky paws. + +NOTE: If the memory is not expected to be cached, this function will + directly re-program the PCD (Page Cache Disable) bit in the + page tables. There does not appear to be a mechanism in the VMM + to control this bit via the regular interface. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + ulong linear,length = limit+1; + int i,npages; + ulong PDB,*pPDB; + + /* Search table of existing mappings to see if we have already mapped + * a region of memory that will serve this purpose. + */ + for (i = 0; i < numMappings; i++) { + if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) + return (void*)maps[i].linear; + } + if (numMappings == MAX_MEMORY_MAPPINGS) + return NULL; + + /* We did not find any previously mapped memory region, so maps it in. + * Note that we do not use MapPhysToLinear, since this function appears + * to have problems mapping memory in the 1Mb physical address space. + * Hence we use PageReserve and PageCommitPhys. + */ + if ((linear = _PM_mapPhysicalToLinear(base,limit,&npages)) == 0xFFFFFFFF) + return NULL; + maps[numMappings].physical = base; + maps[numMappings].length = length; + maps[numMappings].linear = linear; + maps[numMappings].npages = npages; + maps[numMappings].isCached = isCached; + numMappings++; + + /* Finally disable caching where necessary */ + if (!isCached && (PDB = _PM_getPDB()) != 0) { + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPageTable; + pPDB = (ulong*)_PM_mapPhysicalToLinear(PDB,0xFFF,&npages); + if (pPDB) { + startPDB = (linear >> 22) & 0x3FF; + startPage = (linear >> 12) & 0x3FF; + endPDB = ((linear+limit) >> 22) & 0x3FF; + endPage = ((linear+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + /* Set the bits in the page directory entry - required as per */ + /* Pentium 4 manual. This also takes care of the 4MB page entries */ + pPDB[iPDB] = pPDB[iPDB] |= (PAGE_FLAGS_WRITE_THROUGH | PAGE_FLAGS_CACHE_DISABLE); + if (!(pPDB[iPDB] & PAGE_FLAGS_4MB)) { + /* If we are dealing with 4KB pages then we need to iterate */ + /* through each of the page table entries */ + pageTable = pPDB[iPDB] & ~0xFFF; + pPageTable = (ulong*)_PM_mapPhysicalToLinear(pageTable,0xFFF,&npages); + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) + pPageTable[iPage] |= (PAGE_FLAGS_WRITE_THROUGH | PAGE_FLAGS_CACHE_DISABLE); + PageFree((ulong)pPageTable,PR_STATIC); + } + } + PageFree((ulong)pPDB,PR_STATIC); + PM_flushTLB(); + } + } + return (void*)linear; +} + +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* We never free the mappings */ +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* We never sleep in a VxD */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + case 2: return 0x3E8; + case 3: return 0x2E8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +ulong PMAPI PM_getPhysicalAddr( + void *p) +{ + DWORD pte; + + /* Touch the memory before calling CopyPageTable. For some reason */ + /* we need to do this on Windows 9x, otherwise the memory may not */ + /* be paged in correctly. Of course if the passed in pointer is */ + /* invalid, this function will fault, but we shouldn't be passed bogus */ + /* pointers anyway ;-) */ + pte = *((ulong*)p); + + /* Return assembled address value only if VMM service succeeds */ + if (CopyPageTable(((DWORD)p) >> 12, 1, (PVOID*)&pte, 0)) + return (pte & ~0xFFF) | (((DWORD)p) & 0xFFF); + + /* Return failure to the caller! */ + return 0xFFFFFFFFUL; +} + +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + int i; + ulong linear = (ulong)p & ~0xFFF; + + for (i = (length + 0xFFF) >> 12; i > 0; i--) { + if ((*physAddress++ = PM_getPhysicalAddr((void*)linear)) == 0xFFFFFFFF) + return false; + linear += 4096; + } + return true; +} + +void PMAPI _PM_freeMemoryMappings(void) +{ + int i; + for (i = 0; i < numMappings; i++) + PageFree(maps[i].linear,PR_STATIC); +} + +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + return (void*)MK_PHYS(r_seg,r_off); +} + +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + return NULL; +} + +void PMAPI PM_freeRealSeg( + void *mem) +{ +} + +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + /* Unsed in VxD's */ +} + +/**************************************************************************** +REMARKS: +Load the V86 registers in the client state, and save the original state +before loading the registers. +****************************************************************************/ +static void LoadV86Registers( + CLIENT_STRUCT *saveRegs, + RMREGS *in, + RMSREGS *sregs) +{ + CLIENT_STRUCT newRegs; + + Save_Client_State(saveRegs); + newRegs = *saveRegs; + newRegs.CRS.Client_EAX = in->e.eax; + newRegs.CRS.Client_EBX = in->e.ebx; + newRegs.CRS.Client_ECX = in->e.ecx; + newRegs.CRS.Client_EDX = in->e.edx; + newRegs.CRS.Client_ESI = in->e.esi; + newRegs.CRS.Client_EDI = in->e.edi; + newRegs.CRS.Client_ES = sregs->es; + newRegs.CRS.Client_DS = sregs->ds; + Restore_Client_State(&newRegs); +} + +/**************************************************************************** +REMARKS: +Read the V86 registers from the client state and restore the original state. +****************************************************************************/ +static void ReadV86Registers( + CLIENT_STRUCT *saveRegs, + RMREGS *out, + RMSREGS *sregs) +{ + CLIENT_STRUCT newRegs; + + Save_Client_State(&newRegs); + out->e.eax = newRegs.CRS.Client_EAX; + out->e.ebx = newRegs.CRS.Client_EBX; + out->e.ecx = newRegs.CRS.Client_ECX; + out->e.edx = newRegs.CRS.Client_EDX; + out->e.esi = newRegs.CRS.Client_ESI; + out->e.edi = newRegs.CRS.Client_EDI; + sregs->es = newRegs.CRS.Client_ES; + sregs->ds = newRegs.CRS.Client_DS; + Restore_Client_State(saveRegs); +} + +/**************************************************************************** +REMARKS: +Call a V86 real mode function with the specified register values +loaded before the call. The call returns with a far ret. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *regs, + RMSREGS *sregs) +{ + CLIENT_STRUCT saveRegs; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) + return; + + _TRACE("SDDHELP: Entering PM_callRealMode()\n"); + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,regs,sregs); + Simulate_Far_Call(seg, off); + Resume_Exec(); + ReadV86Registers(&saveRegs,regs,sregs); + End_Nest_Exec(); + _TRACE("SDDHELP: Exiting PM_callRealMode()\n"); +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + RMSREGS sregs = {0}; + CLIENT_STRUCT saveRegs; + ushort oldDisable; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) { + *out = *in; + return out->x.ax; + } + + /* Disable pass-up to our VxD handler so we directly call BIOS */ + _TRACE("SDDHELP: Entering PM_int86()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,in,&sregs); + Exec_Int(intno); + ReadV86Registers(&saveRegs,out,&sregs); + End_Nest_Exec(); + + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; + + _TRACE("SDDHELP: Exiting PM_int86()\n"); + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + CLIENT_STRUCT saveRegs; + ushort oldDisable; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) { + *out = *in; + return out->x.ax; + } + + /* Disable pass-up to our VxD handler so we directly call BIOS */ + _TRACE("SDDHELP: Entering PM_int86x()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,in,sregs); + Exec_Int(intno); + ReadV86Registers(&saveRegs,out,sregs); + End_Nest_Exec(); + + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; + + _TRACE("SDDHELP: Exiting PM_int86x()\n"); + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Returns available memory. Not possible under Windows. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocates a block of locked physical memory. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + MEMHANDLE hMem; + DWORD nPages = (size + 0xFFF) >> 12; + DWORD flags = PAGEFIXED | PAGEUSEALIGN | (contiguous ? PAGECONTIG : 0); + DWORD maxPhys = below16M ? 0x00FFFFFF : 0xFFFFFFFF; + void *p; + + /* TODO: This may need to be modified if the memory needs to be globally */ + /* accessible. Check how we implemented PM_mallocShared() as we */ + /* may need to do something similar in here. */ + PageAllocate(nPages,PG_SYS,0,0,0,maxPhys,physAddr,flags,&hMem,&p); + + /* TODO: We may need to modify the memory blocks to disable caching via */ + /* the page tables (PCD|PWT) since DMA memory blocks *cannot* be */ + /* cached! */ + return p; +} + +/**************************************************************************** +REMARKS: +Frees a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + if (p) + PageFree((ulong)p,0); +} + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ + MEMHANDLE hMem; + void *p; + + /* TODO: This will need to be modified if the memory needs to be globally */ + /* accessible. Check how we implemented PM_mallocShared() as we */ + /* may need to do something similar in here. */ + PageAllocate(1,PG_SYS,0,0,0,0,0,PAGEFIXED,&hMem,&p); + return p; +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ + if (p) + PageFree((ulong)p,0); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages( + void *p, + uint len, + PM_lockHandle *lh) +{ + DWORD pgNum = (ulong)p >> 12; + DWORD nPages = (len + (ulong)p - (pgNum << 12) + 0xFFF) >> 12; + return LinPageLock(pgNum,nPages,0); +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages( + void *p, + uint len, + PM_lockHandle *lh) +{ + DWORD pgNum = (ulong)p >> 12; + DWORD nPages = (len + (ulong)p - (pgNum << 12) + 0xFFF) >> 12; + return LinPageUnLock(pgNum,nPages,0); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lh) +{ + return PM_lockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lh) +{ + return PM_unlockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + static short convert[] = { + 8192, + 4096, + 2048, + 1024, + 512, + 256, + 128, + 64, + 32, + 16, + 8, + 4, + 2, + -1, + }; + int i; + + /* First clear any pending RTC timeout if not cleared */ + _PM_readCMOS(0x0C); + if (frequency == 0) { + /* Disable RTC timout */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F); + } + else { + /* Convert frequency value to RTC clock indexes */ + for (i = 0; convert[i] != -1; i++) { + if (convert[i] == frequency) + break; + } + + /* Set RTC timout value and enable timeout */ + _PM_writeCMOS(0x0A,0x20 | (i+3)); + _PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40); + } +} + +/**************************************************************************** +REMARKS: +Real time clock interrupt handler, which calls the user registered C code. +****************************************************************************/ +static BOOL __stdcall RTCInt_Handler( + VMHANDLE hVM, + IRQHANDLE hIRQ) +{ + static char inside = 0; + + /* Clear priority interrupt controller and re-enable interrupts so we + * dont lock things up for long. + */ + VPICD_Phys_EOI(hIRQ); + + /* Clear real-time clock timeout */ + _PM_readCMOS(0x0C); + + /* Now call the C based interrupt handler (but check for mutual + * exclusion since we may still be servicing an old interrupt when a + * new one comes along; if that happens we ignore the old one). + */ + if (!inside) { + inside = 1; + enable(); + _PM_rtcHandler(); + inside = 0; + } + return TRUE; +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + struct VPICD_IRQ_Descriptor IRQdesc; + + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + CHECK(ih != NULL); + _PM_rtcHandler = ih; + IRQdesc.VID_IRQ_Number = 0x8; + IRQdesc.VID_Options = 0; + IRQdesc.VID_Hw_Int_Proc = (DWORD)VPICD_Thunk_HWInt(RTCInt_Handler, &RTCInt_Thunk); + IRQdesc.VID_EOI_Proc = 0; + IRQdesc.VID_Virt_Int_Proc = 0; + IRQdesc.VID_Mask_Change_Proc= 0; + IRQdesc.VID_IRET_Proc = 0; + IRQdesc.VID_IRET_Time_Out = 500; + if ((RTCIRQHandle = VPICD_Virtualize_IRQ(&IRQdesc)) == 0) + return false; + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC */ + VPICD_Physically_Unmask(RTCIRQHandle); + return true; +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (RTCIRQHandle) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + + /* Restore the interrupt vector */ + VPICD_Set_Auto_Masking(RTCIRQHandle); + VPICD_Force_Default_Behavior(RTCIRQHandle); + RTCIRQHandle = 0; + } +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + (void)szDLLName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + (void)hModule; + (void)szProcName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + /* Not supported in a VxD */ + (void)drive; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + /* Not supported in a VxD */ + (void)drive; + (void)dir; + (void)len; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + return MTRR_enableWriteCombine(base,size,type); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Implement this */ + (void)filename; + (void)attrib; + PM_fatalError("PM_setFileAttr not implemented yet!"); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + /* TODO: Implement this */ + (void)filename; + PM_fatalError("PM_getFileAttr not implemented yet!"); + return 0; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + /* TODO: Implement this */ + (void)filename; + PM_fatalError("PM_mkdir not implemented yet!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + /* TODO: Implement this */ + (void)filename; + PM_fatalError("PM_rmdir not implemented yet!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_getFileTime not implemented yet!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_setFileTime not implemented yet!"); + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c new file mode 100644 index 0000000..901ce1c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c new file mode 100644 index 0000000..76df48c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c @@ -0,0 +1,105 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ulong frequency = 1193180; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +#define __ZTimerInit() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOn(tm) VTD_Get_Real_Time(&tm->start.high,&tm->start.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger lap,count; + VTD_Get_Real_Time(&lap.high,&lap.low); + _CPU_diffTime64(&tm->start,&lap,&count); + return _CPU_calcMicroSec(&count,frequency); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) VTD_Get_Real_Time(&tm->end.high,&tm->end.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,frequency); +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + CPU_largeInteger count; + VTD_Get_Real_Time(&count.high,&count.low); + return (count.low * 1000.0 / frequency); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm b/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm new file mode 100644 index 0000000..7c242b5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm @@ -0,0 +1,78 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: Win32 +;* +;* Description: Low level assembly support for the PM library specific +;* to Windows. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmwin32 ; Set up memory model + +begdataseg _pmwin32 + + cglobal _PM_ioentry + cglobal _PM_gdt +_PM_ioentry dd 0 ; Offset to call gate +_PM_gdt dw 0 ; Selector to call gate + +enddataseg _pmwin32 + +begcodeseg _pmwin32 ; Start of code segment + +;---------------------------------------------------------------------------- +; int PM_setIOPL(int iopl) +;---------------------------------------------------------------------------- +; Change the IOPL level for the 32-bit task. Returns the previous level +; so it can be restored for the task correctly. +;---------------------------------------------------------------------------- +cprocstart _PM_setIOPLViaCallGate + + ARG iopl:UINT + + enter_c + pushfd ; Save the old EFLAGS for later + mov ecx,[iopl] ; ECX := IOPL level + xor ebx,ebx ; Change IOPL level function code +ifdef USE_NASM + call far dword [_PM_ioentry] +else + call [FWORD _PM_ioentry] +endif + pop eax + and eax,0011000000000000b + shr eax,12 + leave_c + ret + +cprocend + +endcodeseg _pmwin32 + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c new file mode 100644 index 0000000..7da9752 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c @@ -0,0 +1,94 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Module to implement OS specific services to measure the +* CPU frequency. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ibool havePerformanceCounter; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Increase the thread priority to maximum, if possible. +****************************************************************************/ +static int SetMaxThreadPriority(void) +{ + int oldPriority; + HANDLE hThread = GetCurrentThread(); + + oldPriority = GetThreadPriority(hThread); + if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) + SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL); + return oldPriority; +} + +/**************************************************************************** +REMARKS: +Restore the original thread priority. +****************************************************************************/ +static void RestoreThreadPriority( + int oldPriority) +{ + HANDLE hThread = GetCurrentThread(); + + if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) + SetThreadPriority(hThread, oldPriority); +} + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + if (!QueryPerformanceFrequency((LARGE_INTEGER*)freq)) { + havePerformanceCounter = false; + freq->low = 100000; + freq->high = 0; + } + else + havePerformanceCounter = true; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + if (havePerformanceCounter) \ + QueryPerformanceCounter((LARGE_INTEGER*)t); \ + else { \ + (t)->low = timeGetTime() * 100; \ + (t)->high = 0; \ + } \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c new file mode 100644 index 0000000..d6c3f60 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c @@ -0,0 +1,582 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Win32 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +#include "event.h" +#include "pmapi.h" +#include "win32/oshdr.h" +#include "nucleus/graphics.h" + +/*---------------------------- Global Variables ---------------------------*/ + +/* Publicly accessible variables */ + +int _PM_deskX,_PM_deskY;/* Desktop dimentions */ +HWND _PM_hwndConsole; /* Window handle for console */ +#ifdef __INTEL__ +uint _PM_cw_default; /* Default FPU control word */ +#endif + +/* Private internal variables */ + +static HINSTANCE hInstApp = NULL;/* Application instance handle */ +static HWND hwndUser = NULL;/* User window handle */ +static HINSTANCE hInstDD = NULL; /* Handle to DirectDraw DLL */ +static LPDIRECTDRAW lpDD = NULL; /* DirectDraw object */ +static LONG oldWndStyle; /* Info about old user window */ +static LONG oldExWndStyle; /* Info about old user window */ +static int oldWinPosX; /* Old window position X coordinate */ +static int oldWinPosY; /* Old window pisition Y coordinate */ +static int oldWinSizeX; /* Old window size X */ +static int oldWinSizeY; /* Old window size Y */ +static WNDPROC oldWinProc = NULL; +static PM_saveState_cb suspendApp = NULL; +static ibool waitActive = false; +static ibool isFullScreen = false; +static ibool backInGDI = false; + +/* Internal strings */ + +static char *szWinClassName = "SciTechDirectDrawWindow"; +static char *szAutoPlayKey = "Software\\Microsoft\\Windows\\CurrentVersion\\Policies\\Explorer"; +static char *szAutoPlayValue = "NoDriveTypeAutoRun"; + +/* Dynalinks to DirectDraw functions */ + +static HRESULT (WINAPI *pDirectDrawCreate)(GUID FAR *lpGUID, LPDIRECTDRAW FAR *lplpDD, IUnknown FAR *pUnkOuter); + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +REMARKS: +Temporarily disables AutoPlay operation while we are running in fullscreen +graphics modes. +****************************************************************************/ +static void DisableAutoPlay(void) +{ + DWORD dwAutoPlay,dwSize = sizeof(dwAutoPlay); + HKEY hKey; + + if (RegOpenKeyEx(HKEY_CURRENT_USER,szAutoPlayKey,0,KEY_EXECUTE | KEY_WRITE,&hKey) == ERROR_SUCCESS) { + RegQueryValueEx(hKey,szAutoPlayValue,NULL,NULL,(void*)&dwAutoPlay,&dwSize); + dwAutoPlay |= AUTOPLAY_DRIVE_CDROM; + RegSetValueEx(hKey,szAutoPlayValue,0,REG_DWORD,(void*)&dwAutoPlay,dwSize); + RegCloseKey(hKey); + } +} + +/**************************************************************************** +REMARKS: +Re-enables AutoPlay operation when we return to regular GDI mode. +****************************************************************************/ +static void RestoreAutoPlay(void) +{ + DWORD dwAutoPlay,dwSize = sizeof(dwAutoPlay); + HKEY hKey; + + if (RegOpenKeyEx(HKEY_CURRENT_USER,szAutoPlayKey,0,KEY_EXECUTE | KEY_WRITE,&hKey) == ERROR_SUCCESS) { + RegQueryValueEx(hKey,szAutoPlayValue,NULL,NULL,(void*)&dwAutoPlay,&dwSize); + dwAutoPlay &= ~AUTOPLAY_DRIVE_CDROM; + RegSetValueEx(hKey,szAutoPlayValue,0,REG_DWORD,(void*)&dwAutoPlay,dwSize); + RegCloseKey(hKey); + } +} + +/**************************************************************************** +REMARKS: +Suspends the application by switching back to the GDI desktop, allowing +normal application code to be processed, and then waiting for the +application activate command to bring us back to fullscreen mode with our +window minimised. +****************************************************************************/ +static void LeaveFullScreen(void) +{ + int retCode = PM_SUSPEND_APP; + + if (backInGDI) + return; + if (suspendApp) + retCode = suspendApp(PM_DEACTIVATE); + RestoreAutoPlay(); + backInGDI = true; + + /* Now process messages normally until we are re-activated */ + waitActive = true; + if (retCode != PM_NO_SUSPEND_APP) { + while (waitActive) { + _EVT_pumpMessages(); + Sleep(200); + } + } +} + +/**************************************************************************** +REMARKS: +Reactivate all the surfaces for DirectDraw and set the system back up for +fullscreen rendering. +****************************************************************************/ +static void RestoreFullScreen(void) +{ + static ibool firstTime = true; + + if (firstTime) { + /* Clear the message queue while waiting for the surfaces to be + * restored. + */ + firstTime = false; + while (1) { + /* Continue looping until out application has been restored + * and we have reset the display mode. + */ + _EVT_pumpMessages(); + if (GetActiveWindow() == _PM_hwndConsole) { + if (suspendApp) + suspendApp(PM_REACTIVATE); + DisableAutoPlay(); + backInGDI = false; + waitActive = false; + firstTime = true; + return; + } + Sleep(200); + } + } +} + +/**************************************************************************** +REMARKS: +This function suspends the application by switching back to the GDI desktop, +allowing normal application code to be processed and then waiting for the +application activate command to bring us back to fullscreen mode with our +window minimised. + +This version only gets called if we have not captured the screen switch in +our activate message loops and will occur if the DirectDraw drivers lose a +surface for some reason while rendering. This should not normally happen, +but it is included just to be sure (it can happen on WinNT/2000 if the user +hits the Ctrl-Alt-Del key combination). Note that this code will always +spin loop, and we cannot disable the spin looping from this version (ie: +if the user hits Ctrl-Alt-Del under WinNT/2000 the application main loop +will cease to be executed until the user switches back to the application). +****************************************************************************/ +void PMAPI PM_doSuspendApp(void) +{ + static ibool firstTime = true; + + /* Call system DLL version if found */ + if (_PM_imports.PM_doSuspendApp != PM_doSuspendApp) { + _PM_imports.PM_doSuspendApp(); + return; + } + + if (firstTime) { + if (suspendApp) + suspendApp(PM_DEACTIVATE); + RestoreAutoPlay(); + firstTime = false; + backInGDI = true; + } + RestoreFullScreen(); + firstTime = true; +} + +/**************************************************************************** +REMARKS: +Main Window proc for the full screen DirectDraw Window that we create while +running in full screen mode. Here we capture all mouse and keyboard events +for the window and plug them into our event queue. +****************************************************************************/ +static LONG CALLBACK PM_winProc( + HWND hwnd, + UINT msg, + WPARAM wParam, + LONG lParam) +{ + switch (msg) { + case WM_SYSCHAR: + /* Stop Alt-Space from pausing our application */ + return 0; + case WM_KEYDOWN: + case WM_SYSKEYDOWN: + if (HIWORD(lParam) & KF_REPEAT) { + if (msg == WM_SYSKEYDOWN) + return 0; + break; + } + /* Fall through for keydown events */ + case WM_KEYUP: + case WM_SYSKEYUP: + if (msg == WM_SYSKEYDOWN || msg == WM_SYSKEYUP) { + if ((HIWORD(lParam) & KF_ALTDOWN) && wParam == VK_RETURN) + break; + /* We ignore the remainder of the system keys to stop the + * system menu from being activated from the keyboard and pausing + * our app while fullscreen (ie: pressing the Alt key). + */ + return 0; + } + break; + case WM_SYSCOMMAND: + switch (wParam & ~0x0F) { + case SC_SCREENSAVE: + case SC_MONITORPOWER: + /* Ignore screensaver requests in fullscreen modes */ + return 0; + } + break; + case WM_SIZE: + if (waitActive && backInGDI && (wParam != SIZE_MINIMIZED)) { + /* Start the re-activation process */ + PostMessage(hwnd,WM_DO_SUSPEND_APP,WM_PM_RESTORE_FULLSCREEN,0); + } + else if (!waitActive && isFullScreen && !backInGDI && (wParam == SIZE_MINIMIZED)) { + /* Start the de-activation process */ + PostMessage(hwnd,WM_DO_SUSPEND_APP,WM_PM_LEAVE_FULLSCREEN,0); + } + break; + case WM_DO_SUSPEND_APP: + switch (wParam) { + case WM_PM_RESTORE_FULLSCREEN: + RestoreFullScreen(); + break; + case WM_PM_LEAVE_FULLSCREEN: + LeaveFullScreen(); + break; + } + return 0; + } + if (oldWinProc) + return oldWinProc(hwnd,msg,wParam,lParam); + return DefWindowProc(hwnd,msg,wParam,lParam); +} + +/**************************************************************************** +PARAMETERS: +hwnd - User window to convert +width - Window of the fullscreen window +height - Height of the fullscreen window + +RETURNS: +Handle to converted fullscreen Window. + +REMARKS: +This function takes the original user window handle and modifies the size, +position and attributes for the window to convert it into a fullscreen +window that we can use. +****************************************************************************/ +static PM_HWND _PM_convertUserWindow( + HWND hwnd, + int width, + int height) +{ + RECT window; + + GetWindowRect(hwnd,&window); + oldWinPosX = window.left; + oldWinPosY = window.top; + oldWinSizeX = window.right - window.left; + oldWinSizeY = window.bottom - window.top; + oldWndStyle = SetWindowLong(hwnd,GWL_STYLE,WS_POPUP | WS_SYSMENU); + oldExWndStyle = SetWindowLong(hwnd,GWL_EXSTYLE,WS_EX_APPWINDOW); + ShowWindow(hwnd,SW_SHOW); + MoveWindow(hwnd,0,0,width,height,TRUE); + SetWindowPos(hwnd,HWND_TOPMOST,0,0,0,0,SWP_NOMOVE | SWP_NOSIZE); + oldWinProc = (WNDPROC)SetWindowLong(hwnd,GWL_WNDPROC, (LPARAM)PM_winProc); + return hwnd; +} + +/**************************************************************************** +PARAMETERS: +hwnd - User window to restore + +REMARKS: +This function restores the original attributes of the user window and put's +it back into it's original state before it was converted to a fullscreen +window. +****************************************************************************/ +static void _PM_restoreUserWindow( + HWND hwnd) +{ + SetWindowLong(hwnd,GWL_WNDPROC, (LPARAM)oldWinProc); + SetWindowLong(hwnd,GWL_EXSTYLE,oldExWndStyle); + SetWindowLong(hwnd,GWL_STYLE,oldWndStyle); + SetWindowPos(hwnd,HWND_NOTOPMOST,0,0,0,0,SWP_NOMOVE | SWP_NOSIZE); + ShowWindow(hwnd,SW_SHOW); + MoveWindow(hwnd,oldWinPosX,oldWinPosY,oldWinSizeX,oldWinSizeY,TRUE); + oldWinProc = NULL; +} + +/**************************************************************************** +PARAMETERS: +device - Index of the device to load DirectDraw for (0 for primary) + +REMARKS: +Attempts to dynamically load the DirectDraw DLL's and create the DirectDraw +objects that we need. +****************************************************************************/ +void * PMAPI PM_loadDirectDraw( + int device) +{ + HDC hdc; + int bits; + + /* Call system DLL version if found */ + if (_PM_imports.PM_loadDirectDraw != PM_loadDirectDraw) + return _PM_imports.PM_loadDirectDraw(device); + + /* TODO: Handle multi-monitor!! */ + if (device != 0) + return NULL; + + /* Load the DirectDraw DLL if not presently loaded */ + GET_DEFAULT_CW(); + if (!hInstDD) { + hdc = GetDC(NULL); + bits = GetDeviceCaps(hdc,BITSPIXEL); + ReleaseDC(NULL,hdc); + if (bits < 8) + return NULL; + if ((hInstDD = LoadLibrary("ddraw.dll")) == NULL) + return NULL; + pDirectDrawCreate = (void*)GetProcAddress(hInstDD,"DirectDrawCreate"); + if (!pDirectDrawCreate) + return NULL; + } + + /* Create the DirectDraw object */ + if (!lpDD && pDirectDrawCreate(NULL, &lpDD, NULL) != DD_OK) { + lpDD = NULL; + return NULL; + } + RESET_DEFAULT_CW(); + return lpDD; +} + +/**************************************************************************** +PARAMETERS: +device - Index of the device to unload DirectDraw for (0 for primary) + +REMARKS: +Frees any DirectDraw objects for the device. We never actually explicitly +unload the ddraw.dll library, since unloading and reloading it is +unnecessary since we only want to unload it when the application exits and +that happens automatically. +****************************************************************************/ +void PMAPI PM_unloadDirectDraw( + int device) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_unloadDirectDraw != PM_unloadDirectDraw) { + _PM_imports.PM_unloadDirectDraw(device); + return; + } + if (lpDD) { + IDirectDraw_Release(lpDD); + lpDD = NULL; + } + (void)device; +} + +/**************************************************************************** +REMARKS: +Open a console for output to the screen, creating the main event handling +window if necessary. +****************************************************************************/ +PM_HWND PMAPI PM_openConsole( + PM_HWND hWndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + WNDCLASS cls; + static ibool classRegistered = false; + + /* Call system DLL version if found */ + GA_getSystemPMImports(); + if (_PM_imports.PM_openConsole != PM_openConsole) { + if (fullScreen) { + _PM_deskX = xRes; + _PM_deskY = yRes; + } + return _PM_imports.PM_openConsole(hWndUser,device,xRes,yRes,bpp,fullScreen); + } + + /* Create the fullscreen window if necessary */ + hwndUser = hWndUser; + if (fullScreen) { + if (!classRegistered) { + /* Create a Window class for the fullscreen window in here, since + * we need to register one that will do all our event handling for + * us. + */ + hInstApp = GetModuleHandle(NULL); + cls.hCursor = LoadCursor(NULL,IDC_ARROW); + cls.hIcon = LoadIcon(hInstApp,MAKEINTRESOURCE(1)); + cls.lpszMenuName = NULL; + cls.lpszClassName = szWinClassName; + cls.hbrBackground = GetStockObject(BLACK_BRUSH); + cls.hInstance = hInstApp; + cls.style = CS_DBLCLKS; + cls.lpfnWndProc = PM_winProc; + cls.cbWndExtra = 0; + cls.cbClsExtra = 0; + if (!RegisterClass(&cls)) + return NULL; + classRegistered = true; + } + _PM_deskX = xRes; + _PM_deskY = yRes; + if (!hwndUser) { + char windowTitle[80]; + if (LoadString(hInstApp,1,windowTitle,sizeof(windowTitle)) == 0) + strcpy(windowTitle,"MGL Fullscreen Application"); + _PM_hwndConsole = CreateWindowEx(WS_EX_APPWINDOW,szWinClassName, + windowTitle,WS_POPUP | WS_SYSMENU,0,0,xRes,yRes, + NULL,NULL,hInstApp,NULL); + } + else { + _PM_hwndConsole = _PM_convertUserWindow(hwndUser,xRes,yRes); + } + ShowCursor(false); + isFullScreen = true; + } + else { + _PM_hwndConsole = hwndUser; + isFullScreen = false; + } + SetFocus(_PM_hwndConsole); + SetForegroundWindow(_PM_hwndConsole); + DisableAutoPlay(); + (void)bpp; + return _PM_hwndConsole; +} + +/**************************************************************************** +REMARKS: +Find the size of the console state buffer. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_getConsoleStateSize != PM_getConsoleStateSize) + return _PM_imports.PM_getConsoleStateSize(); + + /* Not used in Windows */ + return 1; +} + +/**************************************************************************** +REMARKS: +Save the state of the console. +****************************************************************************/ +void PMAPI PM_saveConsoleState( + void *stateBuf, + PM_HWND hwndConsole) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_saveConsoleState != PM_saveConsoleState) { + _PM_imports.PM_saveConsoleState(stateBuf,hwndConsole); + return; + } + + /* Not used in Windows */ + (void)stateBuf; + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Set the suspend application callback for the fullscreen console. +****************************************************************************/ +void PMAPI PM_setSuspendAppCallback( + PM_saveState_cb saveState) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_setSuspendAppCallback != PM_setSuspendAppCallback) { + _PM_imports.PM_setSuspendAppCallback(saveState); + return; + } + suspendApp = saveState; +} + +/**************************************************************************** +REMARKS: +Restore the console state. +****************************************************************************/ +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + PM_HWND hwndConsole) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_restoreConsoleState != PM_restoreConsoleState) { + _PM_imports.PM_restoreConsoleState(stateBuf,hwndConsole); + return; + } + + /* Not used in Windows */ + (void)stateBuf; + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Close the fullscreen console. +****************************************************************************/ +void PMAPI PM_closeConsole( + PM_HWND hwndConsole) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_closeConsole != PM_closeConsole) { + _PM_imports.PM_closeConsole(hwndConsole); + return; + } + ShowCursor(true); + RestoreAutoPlay(); + if (hwndUser) + _PM_restoreUserWindow(hwndConsole); + else + DestroyWindow(hwndConsole); + hwndUser = NULL; + _PM_hwndConsole = NULL; +} + +/**************************************************************************** +REMARKS: +Return the DirectDraw window handle used by the application. +****************************************************************************/ +PM_HWND PMAPI PM_getDirectDrawWindow(void) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_getDirectDrawWindow != PM_getDirectDrawWindow) + return _PM_imports.PM_getDirectDrawWindow(); + return _PM_hwndConsole; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c new file mode 100644 index 0000000..86448e3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c @@ -0,0 +1,459 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Win32 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0}; /* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under Win32 */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) (void)(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ return timeGetTime(); } + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from Win32 into our event queue. +****************************************************************************/ +void _EVT_pumpMessages(void) +{ + MSG msg; + MSG charMsg; + event_t evt; + + /* TODO: Add support for DirectInput! We can't support relative mouse */ + /* movement motion counters without DirectInput ;-(. */ + while (PeekMessage(&msg,NULL,0,0,PM_REMOVE)) { + memset(&evt,0,sizeof(evt)); + switch (msg.message) { + case WM_MOUSEMOVE: + evt.what = EVT_MOUSEMOVE; + break; + case WM_LBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_LEFTBMASK | EVT_DBLCLICK; + break; + case WM_LBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_LEFTBMASK; + break; + case WM_LBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_LEFTBMASK; + break; + case WM_RBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK; + evt.message = EVT_RIGHTBMASK; + break; + case WM_RBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_RIGHTBMASK; + break; + case WM_RBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_RIGHTBMASK; + break; + case WM_MBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK; + evt.message = EVT_MIDDLEBMASK; + break; + case WM_MBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_MIDDLEBMASK; + break; + case WM_MBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_MIDDLEBMASK; + break; + case WM_KEYDOWN: + case WM_SYSKEYDOWN: + if (HIWORD(msg.lParam) & KF_REPEAT) { + evt.what = EVT_KEYREPEAT; + } + else { + evt.what = EVT_KEYDOWN; + } + break; + case WM_KEYUP: + case WM_SYSKEYUP: + evt.what = EVT_KEYUP; + break; + } + + /* Convert mouse event modifier flags */ + if (evt.what & EVT_MOUSEEVT) { + if (_PM_deskX) { + evt.where_x = ((long)msg.pt.x * rangeX) / _PM_deskX; + evt.where_y = ((long)msg.pt.y * rangeY) / _PM_deskY; + } + else { + ScreenToClient(_PM_hwndConsole, &msg.pt); + evt.where_x = msg.pt.x; + evt.where_y = msg.pt.y; + } + if (evt.what == EVT_MOUSEMOVE) { + /* Save the current mouse position */ + EVT.mx = evt.where_x; + EVT.my = evt.where_y; + if (EVT.oldMove != -1) { + EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */ + EVT.evtq[EVT.oldMove].where_y = evt.where_y; +/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; // TODO! */ +/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; // TODO! */ + evt.what = 0; + } + else { + EVT.oldMove = EVT.freeHead; /* Save id of this move event */ +/* evt.relative_x = mickeyX; // TODO! */ +/* evt.relative_y = mickeyY; // TODO! */ + } + } + else + EVT.oldMove = -1; + if (msg.wParam & MK_LBUTTON) + evt.modifiers |= EVT_LEFTBUT; + if (msg.wParam & MK_RBUTTON) + evt.modifiers |= EVT_RIGHTBUT; + if (msg.wParam & MK_MBUTTON) + evt.modifiers |= EVT_MIDDLEBUT; + if (msg.wParam & MK_SHIFT) + evt.modifiers |= EVT_SHIFTKEY; + if (msg.wParam & MK_CONTROL) + evt.modifiers |= EVT_CTRLSTATE; + } + + /* Convert keyboard codes */ + TranslateMessage(&msg); + if (evt.what & EVT_KEYEVT) { + int scanCode = (msg.lParam >> 16) & 0xFF; + if (evt.what == EVT_KEYUP) { + /* Get message for keyup code from table of cached down values */ + evt.message = keyUpMsg[scanCode]; + keyUpMsg[scanCode] = 0; + } + else { + if (PeekMessage(&charMsg,NULL,WM_CHAR,WM_CHAR,PM_REMOVE)) + evt.message = charMsg.wParam; + if (PeekMessage(&charMsg,NULL,WM_SYSCHAR,WM_SYSCHAR,PM_REMOVE)) + evt.message = charMsg.wParam; + evt.message |= ((msg.lParam >> 8) & 0xFF00); + keyUpMsg[scanCode] = (ushort)evt.message; + } + if (evt.what == EVT_KEYREPEAT) + evt.message |= (msg.lParam << 16); + if (HIWORD(msg.lParam) & KF_ALTDOWN) + evt.modifiers |= EVT_ALTSTATE; + if (GetKeyState(VK_SHIFT) & 0x8000U) + evt.modifiers |= EVT_SHIFTKEY; + if (GetKeyState(VK_CONTROL) & 0x8000U) + evt.modifiers |= EVT_CTRLSTATE; + EVT.oldMove = -1; + } + + if (evt.what != 0) { + /* Add time stamp and add the event to the queue */ + evt.when = msg.time; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + DispatchMessage(&msg); + } +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort( + int signal) +{ + (void)signal; + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + EVT.mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +void _EVT_setMousePos( + int *x, + int *y) +{ + /* Scale coordinates up to desktop coordinates first */ + int scaledX = (*x * _PM_deskX) / rangeX; + int scaledY = (*y * _PM_deskY) / rangeY; + + /* Scale coordinates back to screen coordinates again */ + *x = (scaledX * rangeX) / _PM_deskX; + *y = (scaledY * rangeY) / _PM_deskY; + SetCursorPos(scaledX,scaledY); +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for Win32 */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for Win32 */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); +} + +/**************************************************************************** +DESCRIPTION: +Returns the mask indicating what joystick axes are attached. + +HEADER: +event.h + +REMARKS: +This function is used to detect the attached joysticks, and determine +what axes are present and functioning. This function will re-detect any +attached joysticks when it is called, so if the user forgot to attach +the joystick when the application started, you can call this function to +re-detect any newly attached joysticks. + +SEE ALSO: +EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +int EVTAPI EVT_joyIsPresent(void) +{ + /* TODO: Implement joystick code based on DirectX! */ + return 0; +} + +/**************************************************************************** +DESCRIPTION: +Polls the joystick for position and button information. + +HEADER: +event.h + +REMARKS: +This routine is used to poll analogue joysticks for button and position +information. It should be called once for each main loop of the user +application, just before processing all pending events via EVT_getNext. +All information polled from the joystick will be posted to the event +queue for later retrieval. + +Note: Most analogue joysticks will provide readings that change even + though the joystick has not moved. Hence if you call this routine + you will likely get an EVT_JOYMOVE event every time through your + event loop. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight, +EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_pollJoystick(void) +{ +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick upper left position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the upper left +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetUpperLeft(void) +{ +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick lower right position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the lower right +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetLowerRight(void) +{ +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick center position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the center +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter +****************************************************************************/ +void EVTAPI EVT_joySetCenter(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c new file mode 100644 index 0000000..59d9aa0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c @@ -0,0 +1,258 @@ +/**************************************************************************** +* +* SciTech Display Doctor +* +* Copyright (C) 1991-2001 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code is a proprietary trade secret of | +* |SciTech Software, Inc., located at 505 Wall Street, Chico, CA 95928 | +* |USA (www.scitechsoft.com). ANY UNAUTHORIZED POSSESSION, USE, | +* |VIEWING, COPYING, MODIFICATION OR DISSEMINATION OF THIS CODE IS | +* |STRICTLY PROHIBITED BY LAW. Unless you have current, express | +* |written authorization from SciTech to possess or use this code, you | +* |may be subject to civil and/or criminal penalties. | +* | | +* |If you received this code in error or you would like to report | +* |improper use, please immediately contact SciTech Software, Inc. at | +* |530-894-8400. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Windows NT, Windows 2K or Windows XP. +* +* Description: Main module to do the installation of the SDD and GLDirect +* device driver components under Windows NT/2K/XP. +* +****************************************************************************/ + +#include "pmapi.h" +#include "win32/oshdr.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +szDriverName - Actual name of the driver to install in the system +szServiceName - Name of the service to create +szLoadGroup - Load group for the driver (NULL for normal drivers) +dwServiceType - Service type to create + +RETURNS: +True on success, false on failure. + +REMARKS: +This function does all the work to install the driver into the system. +The driver is not however activated; for that you must use the Start_SddFilt +function. +****************************************************************************/ +ulong PMAPI PM_installService( + const char *szDriverName, + const char *szServiceName, + const char *szLoadGroup, + ulong dwServiceType) +{ + SC_HANDLE scmHandle; + SC_HANDLE driverHandle; + char szDriverPath[MAX_PATH]; + HKEY key; + char keyPath[MAX_PATH]; + ulong status; + + /* Obtain a handle to the service control manager requesting all access */ + if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) + return GetLastError(); + + /* Find the path to the driver in system directory */ + GetSystemDirectory(szDriverPath, sizeof(szDriverPath)); + strcat(szDriverPath, "\\drivers\\"); + strcat(szDriverPath, szDriverName); + + /* Create the service with the Service Control Manager. */ + driverHandle = CreateService(scmHandle, + szServiceName, + szServiceName, + SERVICE_ALL_ACCESS, + dwServiceType, + SERVICE_BOOT_START, + SERVICE_ERROR_NORMAL, + szDriverPath, + szLoadGroup, + NULL, + NULL, + NULL, + NULL); + + /* Check to see if the driver could actually be installed. */ + if (!driverHandle) { + status = GetLastError(); + CloseServiceHandle(scmHandle); + return status; + } + + /* Get a handle to the key for driver so that it can be altered in the */ + /* next step. */ + strcpy(keyPath, "SYSTEM\\CurrentControlSet\\Services\\"); + strcat(keyPath, szServiceName); + if ((status = RegOpenKeyEx(HKEY_LOCAL_MACHINE,keyPath,0,KEY_ALL_ACCESS,&key)) != ERROR_SUCCESS) { + /* A problem has occured. Delete the service so that it is not installed. */ + status = GetLastError(); + DeleteService(driverHandle); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + + /* Delete the ImagePath value in the newly created key so that the */ + /* system looks for the driver in the normal location. */ + if ((status = RegDeleteValue(key, "ImagePath")) != ERROR_SUCCESS) { + /* A problem has occurred. Delete the service so that it is not */ + /* installed and will not try to start. */ + RegCloseKey(key); + DeleteService(driverHandle); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + + /* Clean up and exit */ + RegCloseKey(key); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return ERROR_SUCCESS; +} + +/**************************************************************************** +PARAMETERS: +szServiceName - Name of the service to start + +RETURNS: +True on success, false on failure. + +REMARKS: +This function is used to start the specified service and make it active. +****************************************************************************/ +ulong PMAPI PM_startService( + const char *szServiceName) +{ + SC_HANDLE scmHandle; + SC_HANDLE driverHandle; + SERVICE_STATUS serviceStatus; + ulong status; + + /* Obtain a handle to the service control manager requesting all access */ + if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) + return GetLastError(); + + /* Open the service with the Service Control Manager. */ + if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) { + status = GetLastError(); + CloseServiceHandle(scmHandle); + return status; + } + + /* Start the service */ + if (!StartService(driverHandle,0,NULL)) { + status = GetLastError(); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + + /* Query the service to make sure it is there */ + if (!QueryServiceStatus(driverHandle,&serviceStatus)) { + status = GetLastError(); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return ERROR_SUCCESS; +} + +/**************************************************************************** +PARAMETERS: +szServiceName - Name of the service to stop + +RETURNS: +True on success, false on failure. + +REMARKS: +This function is used to stop the specified service and disable it. +****************************************************************************/ +ulong PMAPI PM_stopService( + const char *szServiceName) +{ + SC_HANDLE scmHandle; + SC_HANDLE driverHandle; + SERVICE_STATUS serviceStatus; + ulong status; + + /* Obtain a handle to the service control manager requesting all access */ + if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) + return GetLastError(); + + /* Open the service with the Service Control Manager. */ + if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) { + status = GetLastError(); + CloseServiceHandle(scmHandle); + return status; + } + + /* Stop the service from running */ + if (!ControlService(driverHandle, SERVICE_CONTROL_STOP, &serviceStatus)) { + status = GetLastError(); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return ERROR_SUCCESS; +} + +/**************************************************************************** +PARAMETERS: +szServiceName - Name of the service to remove + +RETURNS: +True on success, false on failure. + +REMARKS: +This function is used to remove a service completely from the system. +****************************************************************************/ +ulong PMAPI PM_removeService( + const char *szServiceName) +{ + SC_HANDLE scmHandle; + SC_HANDLE driverHandle; + ulong status; + + /* Obtain a handle to the service control manager requesting all access */ + if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) + return GetLastError(); + + /* Open the service with the Service Control Manager. */ + if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) { + status = GetLastError(); + CloseServiceHandle(scmHandle); + return status; + } + + /* Remove the service */ + if (!DeleteService(driverHandle)) { + status = GetLastError(); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return ERROR_SUCCESS; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h new file mode 100644 index 0000000..0c59e90 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h @@ -0,0 +1,79 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#include +#include +#define NONAMELESSUNION +#include "pm/ddraw.h" + +/* Macros to save and restore the default control word. Windows 9x has + * some bugs in it such that calls to load any DLL's which load 16-bit + * DLL's cause the floating point control word to get trashed. We fix + * this by saving and restoring the control word across problematic + * calls. + */ + +#if defined(__INTEL__) +#define GET_DEFAULT_CW() \ +{ \ + if (_PM_cw_default == 0) \ + _PM_cw_default = _control87(0,0); \ +} +#define RESET_DEFAULT_CW() \ + _control87(_PM_cw_default,0xFFFFFFFF) +#else +#define GET_DEFAULT_CW() +#define RESET_DEFAULT_CW() +#endif + +/* Custom window messages */ + +#define WM_DO_SUSPEND_APP WM_USER +#define WM_PM_LEAVE_FULLSCREEN 0 +#define WM_PM_RESTORE_FULLSCREEN 1 + +/* Macro for disabling AutoPlay on a use system */ + +#define AUTOPLAY_DRIVE_CDROM 0x20 + +/*--------------------------- Global Variables ----------------------------*/ + +#ifdef __INTEL__ +extern uint _PM_cw_default; /* Default FPU control word */ +#endif +extern int _PM_deskX,_PM_deskY; /* Desktop dimensions */ +extern HWND _PM_hwndConsole; /* Window handle for console */ + +/*-------------------------- Internal Functions ---------------------------*/ + +void _EVT_pumpMessages(void); diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c b/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c new file mode 100644 index 0000000..1ffdbcc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c @@ -0,0 +1,1459 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#include +#include +#include +#include +#include +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "pm_help.h" + +/*--------------------------- Global variables ----------------------------*/ + +ibool _PM_haveWinNT; /* True if we are running on NT */ +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL;/* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +HANDLE _PM_hDevice = NULL; /* Handle to Win32 VxD */ +static ibool inited = false; /* Flags if we are initialised */ +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +static char *szMachineNameKey = "System\\CurrentControlSet\\control\\ComputerName\\ComputerName"; +static char *szMachineNameKeyNT = "System\\CurrentControlSet\\control\\ComputerName\\ActiveComputerName"; +static char *szMachineName = "ComputerName"; + +/*----------------------------- Implementation ----------------------------*/ + +/* Macro to check for a valid, loaded version of PMHELP. We check this + * on demand when we need these services rather than when PM_init() is + * called because if we are running on DirectDraw we don't need PMHELP.VXD. + */ + +#define CHECK_FOR_PMHELP() \ +{ \ + if (_PM_hDevice == INVALID_HANDLE_VALUE) \ + if (_PM_haveWinNT) \ + PM_fatalError("Unable to connect to PMHELP.SYS or SDDHELP.SYS!"); \ + else \ + PM_fatalError("Unable to connect to PMHELP.VXD or SDDHELP.VXD!"); \ +} + +/**************************************************************************** +REMARKS: +Initialise the PM library and connect to our helper device driver. If we +cannot connect to our helper device driver, we bail out with an error +message. Our Windows 9x VxD is dynamically loadable, so it can be loaded +after the system has started. +****************************************************************************/ +void PMAPI PM_init(void) +{ + DWORD inBuf[1]; /* Buffer to receive data from VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + char cntPath[PM_MAX_PATH]; + char *env; + + /* Create a file handle for the static VxD if possible, otherwise + * dynamically load the PMHELP helper VxD. Note that if an old version + * of SDD is loaded, we use the PMHELP VxD instead. + */ + if (!inited) { + /* Determine if we are running under Windows NT or not and + * set the global OS type variable. + */ + _PM_haveWinNT = false; + if ((GetVersion() & 0x80000000UL) == 0) + _PM_haveWinNT = true; + ___drv_os_type = (_PM_haveWinNT) ? _OS_WINNT : _OS_WIN95; + + /* Now try to connect to SDDHELP.VXD or SDDHELP.SYS */ + _PM_hDevice = CreateFile(SDDHELP_MODULE_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); + if (_PM_hDevice != INVALID_HANDLE_VALUE) { + if (!DeviceIoControl(_PM_hDevice, PMHELP_GETVER32, NULL, 0, + outBuf, sizeof(outBuf), &count, NULL) || outBuf[0] < PMHELP_VERSION) { + /* Old version of SDDHELP loaded, so use PMHELP instead */ + CloseHandle(_PM_hDevice); + _PM_hDevice = INVALID_HANDLE_VALUE; + } + } + if (_PM_hDevice == INVALID_HANDLE_VALUE) { + /* First try to see if there is a currently loaded PMHELP driver. + * This is usually the case when we are running under Windows NT/2K. + */ + _PM_hDevice = CreateFile(PMHELP_MODULE_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); + if (_PM_hDevice == INVALID_HANDLE_VALUE) { + /* The driver was not staticly loaded, so try creating a file handle + * to a dynamic version of the VxD if possible. Note that on WinNT/2K we + * cannot support dynamically loading the drivers. + */ + _PM_hDevice = CreateFile(PMHELP_VXD_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); + } + } + if (_PM_hDevice != INVALID_HANDLE_VALUE) { + /* Call the driver to determine the version number */ + if (!DeviceIoControl(_PM_hDevice, PMHELP_GETVER32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL) || outBuf[0] < PMHELP_VERSION) { + if (_PM_haveWinNT) + PM_fatalError("Older version of PMHELP.SYS found!"); + else + PM_fatalError("Older version of PMHELP.VXD found!"); + } + + /* Now set the current path inside the VxD so it knows what the + * current directory is for loading Nucleus drivers. + */ + inBuf[0] = (ulong)PM_getCurrentPath(cntPath,sizeof(cntPath)); + if (!DeviceIoControl(_PM_hDevice, PMHELP_SETCNTPATH32, inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &count, NULL)) + PM_fatalError("Unable to set VxD current path!"); + + /* Now pass down the NUCLEUS_PATH environment variable to the device + * driver so it can use this value if it is found. + */ + if ((env = getenv("NUCLEUS_PATH")) != NULL) { + inBuf[0] = (ulong)env; + if (!DeviceIoControl(_PM_hDevice, PMHELP_SETNUCLEUSPATH32, inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &count, NULL)) + PM_fatalError("Unable to set VxD Nucleus path!"); + } + + /* Enable IOPL for ring-3 code by default if driver is present */ + if (_PM_haveWinNT) + PM_setIOPL(3); + } + + /* Indicate that we have been initialised */ + inited = true; + } +} + +/**************************************************************************** +REMARKS: +We do have BIOS access under Windows 9x, but not under Windows NT. +****************************************************************************/ +int PMAPI PM_setIOPL( + int iopl) +{ + DWORD inBuf[1]; /* Buffer to receive data from VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + static int cntIOPL = 0; + int oldIOPL = cntIOPL; + + /* Enable I/O by adjusting the I/O permissions map on Windows NT */ + if (_PM_haveWinNT) { + CHECK_FOR_PMHELP(); + if (iopl == 3) + DeviceIoControl(_PM_hDevice, PMHELP_ENABLERING3IOPL, inBuf, sizeof(inBuf),outBuf, sizeof(outBuf), &count, NULL); + else + DeviceIoControl(_PM_hDevice, PMHELP_DISABLERING3IOPL, inBuf, sizeof(inBuf),outBuf, sizeof(outBuf), &count, NULL); + cntIOPL = iopl; + return oldIOPL; + } + + /* We always have IOPL on Windows 9x */ + return 3; +} + +/**************************************************************************** +REMARKS: +We do have BIOS access under Windows 9x, but not under Windows NT. +****************************************************************************/ +ibool PMAPI PM_haveBIOSAccess(void) +{ + if (PM_getOSType() == _OS_WINNT) + return false; + else + return _PM_hDevice != INVALID_HANDLE_VALUE; +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + if ((GetVersion() & 0x80000000UL) == 0) + return ___drv_os_type = _OS_WINNT; + else + return ___drv_os_type = _OS_WIN95; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier. +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ + return PM_386; +} + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash( + char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Report a fatal error condition and halt the program. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + MessageBox(NULL,msg,"Fatal Error!", MB_ICONEXCLAMATION); + exit(1); +} + +/**************************************************************************** +REMARKS: +Allocate the real mode VESA transfer buffer for communicating with the BIOS. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + DWORD outBuf[4]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + /* We require the helper VxD to be loaded staticly in order to support + * the VESA transfer buffer. We do not support dynamically allocating + * real mode memory buffers from Win32 programs (we need a 16-bit DLL + * for this, and Windows 9x becomes very unstable if you free the + * memory blocks out of order). + */ + if (!inited) + PM_init(); + if (!VESABuf_ptr) { + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_GETVESABUF32, NULL, 0, + outBuf, sizeof(outBuf), &count, NULL)) { + if (!outBuf[0]) + return NULL; + VESABuf_ptr = (void*)outBuf[0]; + VESABuf_len = outBuf[1]; + VESABuf_rseg = outBuf[2]; + VESABuf_roff = outBuf[3]; + } + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + /* Not used in Windows */ + return true; +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + /* Not used in Windows */ + return 0xD; +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PM_setOSCursorLocation( + int x, + int y) +{ + /* Nothing to do for Windows */ + (void)x; + (void)y; +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PM_setOSScreenWidth( + int width, + int height) +{ + /* Nothing to do for Windows */ + (void)width; + (void)height; +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + /* We do not support this from Win32 programs. Rather the VxD handles + * this stuff it will take care of hooking the stereo flip functions at + * the VxD level. + */ + (void)ih; + (void)frequency; + return false; +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + /* Not supported under Win32 */ + (void)frequency; +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* Not supported under Win32 */ +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +/**************************************************************************** +REMARKS: +Query a string from the registry (extended version). +****************************************************************************/ +static ibool REG_queryStringEx( + HKEY hKey, + const char *szValue, + char *value, + ulong size) +{ + DWORD type; + + if (RegQueryValueEx(hKey,(PCHAR)szValue,(PDWORD)NULL,(PDWORD)&type,(LPBYTE)value,(PDWORD)&size) == ERROR_SUCCESS) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Query a string from the registry. +****************************************************************************/ +static ibool REG_queryString( + const char *szKey, + const char *szValue, + char *value, + DWORD size) +{ + HKEY hKey; + ibool status = false; + + memset(value,0,sizeof(value)); + if (RegOpenKey(HKEY_LOCAL_MACHINE,szKey,&hKey) == ERROR_SUCCESS) { + status = REG_queryStringEx(hKey,szValue,value,size); + RegCloseKey(hKey); + } + return status; +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + static char path[256]; + GetSystemDirectory(path,sizeof(path)); + return path[0]; +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files. +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + return "c:\\"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + char *env; + + if ((env = getenv("NUCLEUS_PATH")) != NULL) + return env; + GetSystemDirectory(path,sizeof(path)); + strcat(path,"\\nucleus"); + return path; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + return PM_getMachineName(); +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + static char name[256]; + + if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name))) + return name; + if (REG_queryString(szMachineNameKeyNT,szMachineName,name,sizeof(name))) + return name; + return "Unknown"; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + if (_PM_haveWinNT) { + /* On Windows NT we have to map it physically directly */ + return PM_mapPhysicalAddr(0x400, 0x1000, true); + } + else { + /* For Windows 9x we can access this memory directly */ + return (void*)0x400; + } +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + if (_PM_haveWinNT) { + /* On Windows NT we have to map it physically directly */ + return PM_mapPhysicalAddr(0xA0000, 0x0FFFF, false); + } + else { + /* Always use the 0xA0000 linear address so that we will use + * whatever page table mappings are set up for us (ie: for virtual + * bank switching. + */ + return (void*)0xA0000; + } +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = base; + inBuf[1] = limit; + inBuf[2] = isCached; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_MAPPHYS32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return (void*)outBuf[0]; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* We never free the mappings under Win32 (the VxD tracks them and + * reissues the same mappings until the system is rebooted). + */ + (void)ptr; + (void)limit; +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ulong PMAPI PM_getPhysicalAddr( + void *p) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = (ulong)p; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_GETPHYSICALADDR32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0xFFFFFFFFUL; +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = (ulong)p; + inBuf[1] = (ulong)length; + inBuf[2] = (ulong)physAddress; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_GETPHYSICALADDRRANGE32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return false; +} + +/**************************************************************************** +REMARKS: +Sleep for the specified number of milliseconds. +****************************************************************************/ +void PMAPI PM_sleep( + ulong milliseconds) +{ + Sleep(milliseconds); +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified COM port. +****************************************************************************/ +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + case 2: return 0x3E8; + case 3: return 0x2E8; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified LPT port. +****************************************************************************/ +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For Win9x we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = size; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_MALLOCSHARED32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return (void*)outBuf[0]; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory. +****************************************************************************/ +void PMAPI PM_freeShared( + void *ptr) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + + inBuf[0] = (ulong)ptr; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_FREESHARED32, inBuf, sizeof(inBuf), NULL, 0, NULL, NULL); +} + +/**************************************************************************** +REMARKS: +Map a linear memory address to the calling process address space. The +address will have been allocated in another process using the +PM_mapPhysicalAddr function. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + (void)base; + (void)limit; + return base; +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + return (void*)(MK_PHYS(r_seg,r_off)); +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + /* We do not support dynamically allocating real mode memory buffers + * from Win32 programs (we need a 16-bit DLL for this, and Windows + * 9x becomes very unstable if you free the memory blocks out of order). + */ + (void)size; + (void)r_seg; + (void)r_off; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* Not supported in Windows */ + (void)mem; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = intno; + inBuf[1] = (ulong)regs; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_DPMIINT8632, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = intno; + inBuf[1] = (ulong)in; + inBuf[2] = (ulong)out; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_INT8632, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + DWORD inBuf[4]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = intno; + inBuf[1] = (ulong)in; + inBuf[2] = (ulong)out; + inBuf[3] = (ulong)sregs; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_INT86X32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Call a real mode far function. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *in, + RMSREGS *sregs) +{ + DWORD inBuf[4]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = seg; + inBuf[1] = off; + inBuf[2] = (ulong)in; + inBuf[3] = (ulong)sregs; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_CALLREALMODE32, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); +} + +/**************************************************************************** +REMARKS: +Return the amount of available memory. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + /* We don't support this under Win32 at the moment */ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of locked, physical memory for DMA operations. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + DWORD inBuf[4]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = size; + inBuf[1] = (ulong)physAddr; + inBuf[2] = (ulong)contiguous; + inBuf[3] = (ulong)below16M; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_ALLOCLOCKED32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return (void*)outBuf[0]; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = (ulong)p; + inBuf[1] = size; + inBuf[2] = contiguous; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_FREELOCKED32, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); +} + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = locked; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_ALLOCPAGE32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return (void*)outBuf[0]; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = (ulong)p; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_FREEPAGE32, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)p; + inBuf[1] = len; + inBuf[2] = (ulong)lh; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_LOCKDATAPAGES32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)p; + inBuf[1] = len; + inBuf[2] = (ulong)lh; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_UNLOCKDATAPAGES32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)p; + inBuf[1] = len; + inBuf[2] = (ulong)lh; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_LOCKCODEPAGES32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)p; + inBuf[1] = len; + inBuf[2] = (ulong)lh; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_UNLOCKCODEPAGES32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + RMREGS regs; + regs.x.ax = 0x4F05; + regs.x.bx = 0x0000; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + RMREGS regs; + regs.x.ax = 0x4F05; + regs.x.bx = 0x0000; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); + regs.x.ax = 0x4F05; + regs.x.bx = 0x0001; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + RMREGS regs; + regs.x.ax = 0x4F07; + regs.x.bx = waitVRT; + regs.x.cx = x; + regs.x.dx = y; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Enable write combining for the memory region. +****************************************************************************/ +ibool PMAPI PM_enableWriteCombine( + ulong base, + ulong length, + uint type) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = base; + inBuf[1] = length; + inBuf[2] = type; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_ENABLELFBCOMB32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return false; +} + +/**************************************************************************** +REMARKS: +Get the page directory base register value +****************************************************************************/ +ulong PMAPI _PM_getPDB(void) +{ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_GETPDB32, NULL, 0, + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Flush the translation lookaside buffer. +****************************************************************************/ +void PMAPI PM_flushTLB(void) +{ + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_FLUSHTLB32, NULL, 0, NULL, 0, NULL, NULL); +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + /* This is never done by Win32 programs, but rather done by the VxD + * when the system boots. + */ + (void)axVal; + (void)BIOSPhysAddr; + (void)mappedBIOS; + (void)BIOSLen; + return false; +} + +/**************************************************************************** +REMARKS: +Load an OS specific shared library or DLL. If the OS does not support +shared libraries, simply return NULL. +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + return (PM_MODULE)LoadLibrary(szDLLName); +} + +/**************************************************************************** +REMARKS: +Get the address of a named procedure from a shared library. +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + return (void*)GetProcAddress((HINSTANCE)hModule,szProcName); +} + +/**************************************************************************** +REMARKS: +Unload a shared library. +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + FreeLibrary((HINSTANCE)hModule); +} + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + WIN32_FIND_DATA *blk) +{ + ulong dwSize = findData->dwSize; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_READONLY) + findData->attrib |= PM_FILE_READONLY; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) + findData->attrib |= PM_FILE_DIRECTORY; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_ARCHIVE) + findData->attrib |= PM_FILE_ARCHIVE; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_HIDDEN) + findData->attrib |= PM_FILE_HIDDEN; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_SYSTEM) + findData->attrib |= PM_FILE_SYSTEM; + findData->sizeLo = blk->nFileSizeLow; + findData->sizeHi = blk->nFileSizeHigh; + strncpy(findData->name,blk->cFileName,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + WIN32_FIND_DATA blk; + HANDLE hfile; + + if ((hfile = FindFirstFile(filename,&blk)) != INVALID_HANDLE_VALUE) { + convertFindData(findData,&blk); + return (void*)hfile; + } + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + WIN32_FIND_DATA blk; + + if (FindNextFile((HANDLE)handle,&blk)) { + convertFindData(findData,&blk); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + FindClose((HANDLE)handle); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + char buf[5]; + int type; + + sprintf(buf,"%c:\\", drive); + return ((type = GetDriveType(buf)) != 0 && type != 1); +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + /* NT stores the current directory for drive N in the magic environment */ + /* variable =N: so we simply look for that environment variable. */ + char envname[4]; + + envname[0] = '='; + envname[1] = drive - 1 + 'A'; + envname[2] = ':'; + envname[3] = '\0'; + if (GetEnvironmentVariable(envname,dir,len) == 0) { + /* The current directory or the drive has not been set yet, so */ + /* simply set it to the root. */ + dir[0] = envname[1]; + dir[1] = ':'; + dir[2] = '\\'; + dir[3] = '\0'; + SetEnvironmentVariable(envname,dir); + } +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + DWORD attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= FILE_ATTRIBUTE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= FILE_ATTRIBUTE_ARCHIVE; + if (attrib & PM_FILE_HIDDEN) + attr |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= FILE_ATTRIBUTE_SYSTEM; + SetFileAttributes((LPSTR)filename, attr); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + DWORD attr = GetFileAttributes(filename); + uint attrib = 0; + + if (attr & FILE_ATTRIBUTE_READONLY) + attrib |= PM_FILE_READONLY; + if (attr & FILE_ATTRIBUTE_ARCHIVE) + attrib |= PM_FILE_ARCHIVE; + if (attr & FILE_ATTRIBUTE_HIDDEN) + attrib |= PM_FILE_HIDDEN; + if (attr & FILE_ATTRIBUTE_SYSTEM) + attrib |= PM_FILE_SYSTEM; + return attrib; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return CreateDirectory(filename,NULL); +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return RemoveDirectory(filename); +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + HFILE f; + OFSTRUCT of; + FILETIME utcTime,localTime; + SYSTEMTIME sysTime; + ibool status = false; + + of.cBytes = sizeof(of); + if ((f = OpenFile(filename,&of,OF_READ)) == HFILE_ERROR) + return false; + if (!GetFileTime((HANDLE)f,NULL,NULL,&utcTime)) + goto Exit; + if (!gmTime) { + if (!FileTimeToLocalFileTime(&utcTime,&localTime)) + goto Exit; + } + else + localTime = utcTime; + if (!FileTimeToSystemTime(&localTime,&sysTime)) + goto Exit; + time->year = sysTime.wYear; + time->mon = sysTime.wMonth-1; + time->day = sysTime.wYear; + time->hour = sysTime.wHour; + time->min = sysTime.wMinute; + time->sec = sysTime.wSecond; + status = true; + +Exit: + CloseHandle((HANDLE)f); + return status; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + HFILE f; + OFSTRUCT of; + FILETIME utcTime,localTime; + SYSTEMTIME sysTime; + ibool status = false; + + of.cBytes = sizeof(of); + if ((f = OpenFile(filename,&of,OF_WRITE)) == HFILE_ERROR) + return false; + sysTime.wYear = time->year; + sysTime.wMonth = time->mon+1; + sysTime.wYear = time->day; + sysTime.wHour = time->hour; + sysTime.wMinute = time->min; + sysTime.wSecond = time->sec; + if (!SystemTimeToFileTime(&sysTime,&localTime)) + goto Exit; + if (!gmTime) { + if (!LocalFileTimeToFileTime(&localTime,&utcTime)) + goto Exit; + } + else + utcTime = localTime; + if (!SetFileTime((HANDLE)f,NULL,NULL,&utcTime)) + goto Exit; + status = true; + +Exit: + CloseHandle((HANDLE)f); + return status; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c new file mode 100644 index 0000000..70491cd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c @@ -0,0 +1,53 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init( + ulong baseAddr, + int bankSize, + int codeLen, + void *bankFunc) +{ + (void)baseAddr; + (void)bankSize; + (void)codeLen; + (void)bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c new file mode 100644 index 0000000..5a901a4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c @@ -0,0 +1,136 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static CPU_largeInteger countFreq; +static ibool havePerformanceCounter; +static ulong start,finish; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +#ifdef NO_ASSEMBLER + havePerformanceCounter = false; +#else + havePerformanceCounter = QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq); +#endif +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOn( + LZTimerObject *tm) +{ + if (havePerformanceCounter) + QueryPerformanceCounter((LARGE_INTEGER*)&tm->start); + else + tm->start.low = timeGetTime(); +} + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger tmLap,tmCount; + + if (havePerformanceCounter) { + QueryPerformanceCounter((LARGE_INTEGER*)&tmLap); + _CPU_diffTime64(&tm->start,&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); + } + else { + tmLap.low = timeGetTime(); + return (tmLap.low - tm->start.low) * 1000L; + } +} + +/**************************************************************************** +REMARKS: +Stop the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOff( + LZTimerObject *tm) +{ + if (havePerformanceCounter) + QueryPerformanceCounter((LARGE_INTEGER*)&tm->end); + else + tm->end.low = timeGetTime(); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time in microseconds between start and end timings. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + + if (havePerformanceCounter) { + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); + } + else + return (tm->end.low - tm->start.low) * 1000L; +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer from the OS +****************************************************************************/ +static ulong __ULZReadTime(void) +{ return timeGetTime(); } + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/x11/event.c b/board/MAI/bios_emulator/scitech/src/pm/x11/event.c new file mode 100644 index 0000000..b34bfac --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/x11/event.c @@ -0,0 +1,307 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Unix / X11 +* +* Description: X11 event queue implementation for the MGL. +* This can be used both for windowed and fullscreen (DGA) modes. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +static Display *_EVT_dpy; +static Window _EVT_win; + +typedef struct { + int keycode; + int scancode; +} xkeymap; + +xkeymap xkeymaps[] = { + { 9, KB_esc}, + {24, KB_Q}, + {25, KB_W}, + {26, KB_E}, + {27, KB_R}, + {28, KB_T}, + {29, KB_Y}, + {30, KB_U}, + {31, KB_I}, + {32, KB_O}, + {33, KB_P}, +}; + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under non-DOS systems */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + static unsigned starttime = 0; + struct timeval t; + + gettimeofday(&t, NULL); + if (starttime == 0) + starttime = t.tv_sec * 1000 + (t.tv_usec/1000); + return ((t.tv_sec * 1000 + (t.tv_usec/1000)) - starttime); +} + +static int getScancode(int keycode) +{ + return keycode-8; +} + +/**************************************************************************** +REMARKS: +Pumps all messages in the application message queue into our event queue. +****************************************************************************/ +#ifdef X11_CORE +static void _EVT_pumpX11Messages(void) +#else +static void _EVT_pumpMessages(void) +#endif +{ + /* TODO: The purpose of this function is to read all keyboard and mouse */ + /* events from the OS specific event queue, translate them and post */ + /* them into the SciTech event queue. */ + event_t evt; + XEvent ev; + static int old_mx = 0, old_my = 0, buts = 0, c; + char buf[2]; + + while (XPending(_EVT_dpy) && XNextEvent(_EVT_dpy,&ev)) { + evt.when = _MGL_getTicks(); + + switch(ev.type){ + case KeyPress: + c = getScancode(ev.xkey.keycode); + evt.what = EVT_KEYDOWN; + evt.message = c << 8; + XLookupString(&ev.xkey, buf, 2, NULL, NULL); + evt.message |= buf[0]; + break; + case KeyRelease: + c = getScancode(ev.xkey.keycode); + evt.what = EVT_KEYUP; + evt.message = keyUpMsg[c]; + if(count < EVENTQSIZE) + addEvent(&evt); + keyUpMsg[c] = 0; + repeatKey[c] = 0; + break; + case ButtonPress: + evt.what = EVT_MOUSEDOWN; + if(ev.xbutton.button == 1){ + buts |= EVT_LEFTBUT; + evt.message = EVT_LEFTBMASK; + }else if(ev.xbutton.button == 2){ + buts |= EVT_MIDDLEBUT; + evt.message = EVT_MIDDLEBMASK; + }else if(ev.xbutton.button == 3){ + buts |= EVT_RIGHTBUT; + evt.message = EVT_RIGHTBMASK; + } + evt.modifiers = modifiers | buts; + + break; + case ButtonRelease: + evt.what = EVT_MOUSEUP; + if(ev.xbutton.button == 1){ + buts &= ~EVT_LEFTBUT; + evt.message = EVT_LEFTBMASK; + }else if(ev.xbutton.button == 2){ + buts &= ~EVT_MIDDLEBUT; + evt.message = EVT_MIDDLEBMASK; + }else if(ev.xbutton.button == 3){ + buts &= ~EVT_RIGHTBUT; + evt.message = EVT_RIGHTBMASK; + } + evt.modifiers = modifiers | buts; + + break; + case MotionNotify: + evt.what = EVT_MOUSEMOVE; + evt.where_x = ev.xmotion.x; + evt.where_y = ev.xmotion.y; + evt.relative_x = evt.where_x - old_mx; + evt.relative_y = evt.where_y - old_my; + old_mx = evt.where_x; + old_my = evt.where_y; + break; + } + if (count < EVENTQSIZE) + addEvent(&evt); + } + +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +#ifdef X11_CORE +void EVTAPI EVT_initX11( +#else +void EVTAPI EVT_init( +#endif + _EVT_mouseMoveHandler mouseMove) +{ + int result, i,j,k; + XDeviceInfoPtr list,slist; + + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + + /* query server for input extensions */ + result =XQueryExtension(_EVT_dpy,"XInputExtension",&i,&j,&k); + if(!result) { + fprintf(stderr,"Your server doesn't support XInput Extensions\n"); + fprintf(stderr,"X11 Joystick disabled\n"); + } + list = XListInputDevices(_EVT_dpy,&result); + if (!list) { + fprintf(stderr,"No extended input devices found !!\n"); + fprintf(stderr,"X11 Joystick disabled\n"); + } + + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* TODO: Do any OS specific cleanup in here */ +} + +/**************************************************************************** +REMARKS +Sets the current X11 display +****************************************************************************/ +void EVT_setX11Display(Display *dpy, Window win) +{ + _EVT_dpy = dpy; + _EVT_win = win; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h new file mode 100644 index 0000000..45d7451 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h @@ -0,0 +1,38 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#include +#include +#include +#include +#ifdef USE_OS_JOYSTICK +#include +#include +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj b/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj new file mode 100644 index 0000000..0c6c80f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj @@ -0,0 +1,74 @@ +[SciTech] +compiler=wc10- +targetos=d32 +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,getch.exe +FILTERNAME=Source Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n +FILTERASSOCIATEFILETYPES=0 +FILTERAPPCOMMAND=\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|:Build:&Build,dmake %b +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake -u %b +debug=concur|capture|savenone|nochangedir|:Debug:&Debug,wdn %b +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|nochangedir|:User 1:User 1, +user2=hide|nochangedir|:User 2:User 2, +usertool_build_all=concur|capture|clear|savenone|:Build All:Build All,dmake all +usertool_rebuild_all=concur|capture|clear|savenone|:Rebuild All:Rebuild All,dmake -u all +usertool_clean_directory=concur|capture|savenone|:Clean Directory:&Clean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +tests\altbrk.c +tests\altcrit.c +tests\biosptr.c +tests\block.c +tests\brk.c +tests\callreal.c +tests\checks.c +tests\cpu.c +tests\critical.c +tests\getch.c +tests\isvesa.c +tests\key.c +tests\key15.c +tests\memtest.c +tests\mouse.c +tests\rtc.c +tests\showpci.c +tests\tick.c +tests\timerc.c +tests\timercpp.cpp +tests\uswc.c +tests\vftest.c +tests\video.c +[ASSOCIATION] +[CONFIGURATIONS] +config=,altbrk.exe +config=,altcrit.exe +config=,biosptr.exe +config=,block.exe +config=,brk.exe +config=,callreal.exe +config=,cpu.exe +config=,critical.exe +config=,getch.exe +config=,isvesa.exe +config=,key.exe +config=,key15.exe +config=,memtest.exe +config=,mouse.exe +config=,rtc.exe +config=,showpci.exe +config=,tick.exe +config=,timerc.exe +config=,timercpp.exe +config=,uswc.exe +config=,vftest.exe +config=,video.exe diff --git a/board/MAI/bios_emulator/scitech/src/pm/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/ztimer.c new file mode 100644 index 0000000..5acf7b1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ztimer.c @@ -0,0 +1,516 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module to implement high precision timing on each OS. +* +****************************************************************************/ + +#include "ztimer.h" +#include "pmapi.h" +#include "oshdr.h" + +/*---------------------------- Global variables ---------------------------*/ + +static LZTimerObject LZTimer; +static ulong start,finish; +#ifdef __INTEL__ +static long cpuSpeed = -1; +static ibool haveRDTSC = false; +#endif + +/*----------------------------- Implementation ----------------------------*/ + +/* External Intel assembler functions */ +#ifdef __INTEL__ +/* {secret} */ +void _ASMAPI _CPU_readTimeStamp(CPU_largeInteger *time); +/* {secret} */ +ulong _ASMAPI _CPU_diffTime64(CPU_largeInteger *t1,CPU_largeInteger *t2,CPU_largeInteger *t); +/* {secret} */ +ulong _ASMAPI _CPU_calcMicroSec(CPU_largeInteger *count,ulong freq); +#endif + +#if defined(__SMX32__) +#include "smx/ztimer.c" +#elif defined(__RTTARGET__) +#include "rttarget/ztimer.c" +#elif defined(__REALDOS__) +#include "dos/ztimer.c" +#elif defined(__NT_DRIVER__) +#include "ntdrv/ztimer.c" +#elif defined(__WIN32_VXD__) +#include "vxd/ztimer.c" +#elif defined(__WINDOWS32__) +#include "win32/ztimer.c" +#elif defined(__OS2_VDD__) +#include "vdd/ztimer.c" +#elif defined(__OS2__) +#include "os2/ztimer.c" +#elif defined(__LINUX__) +#include "linux/ztimer.c" +#elif defined(__QNX__) +#include "qnx/ztimer.c" +#elif defined(__BEOS__) +#include "beos/ztimer.c" +#else +#error Timer library not ported to this platform yet! +#endif + +/*------------------------ Public interface routines ----------------------*/ + +/**************************************************************************** +DESCRIPTION: +Initializes the Zen Timer library (extended) + +PARAMETERS: +accurate - True of the speed should be measured accurately + +HEADER: +ztimer.h + +REMARKS: +This function initializes the Zen Timer library, and /must/ be called before +any of the remaining Zen Timer library functions are called. The accurate +parameter is used to determine whether highly accurate timing should be +used or not. If high accuracy is needed, more time is spent profiling the +actual speed of the CPU so that we can obtain highly accurate timing +results, but the time spent in the initialisation routine will be +significantly longer (on the order of 5 seconds). +****************************************************************************/ +void ZAPI ZTimerInitExt( + ibool accurate) +{ + if (cpuSpeed == -1) { + __ZTimerInit(); +#ifdef __INTEL__ + cpuSpeed = CPU_getProcessorSpeedInHZ(accurate); + haveRDTSC = CPU_haveRDTSC() && (cpuSpeed > 0); +#endif + } +} + +/**************************************************************************** +DESCRIPTION: +Initializes the Zen Timer library. + +HEADER: +ztimer.h + +REMARKS: +This function initializes the Zen Timer library, and /must/ be called before +any of the remaining Zen Timer library functions are called. +****************************************************************************/ +void ZAPI ZTimerInit(void) +{ + ZTimerInitExt(false); +} + +/**************************************************************************** +DESCRIPTION: +Starts the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +PARAMETERS: +tm - Timer object to start timing with + +REMARKS: +Starts the Long Period Zen Timer counting. Once you have started the timer, +you can stop it with LZTimerOff or you can latch the current count with +LZTimerLap. + +The Long Period Zen Timer uses a number of different high precision timing +mechanisms to obtain microsecond accurate timings results whenever possible. +The following different techniques are used depending on the operating +system, runtime environment and CPU on the target machine. If the target +system has a Pentium CPU installed which supports the Read Time Stamp +Counter instruction (RDTSC), the Zen Timer library will use this to +obtain the maximum timing precision available. + +Under 32-bit Windows, if the Pentium RDTSC instruction is not available, we +first try to use the Win32 QueryPerformanceCounter API, and if that is not +available we fall back on the timeGetTime API which is always supported. + +Under 32-bit DOS, if the Pentium RDTSC instruction is not available, we +then do all timing using the old style 8253 timer chip. The 8253 timer +routines provide highly accurate timings results in pure DOS mode, however +in a DOS box under Windows or other Operating Systems the virtualization +of the timer can produce inaccurate results. + +Note: Because the Long Period Zen Timer stores the results in a 32-bit + unsigned integer, you can only time periods of up to 2^32 microseconds, + or about 1hr 20mins. For timing longer periods use the Ultra Long + Period Zen Timer. + +SEE ALSO: +LZTimerOff, LZTimerLap, LZTimerCount +****************************************************************************/ +void ZAPI LZTimerOnExt( + LZTimerObject *tm) +{ +#ifdef __INTEL__ + if (haveRDTSC) { + _CPU_readTimeStamp(&tm->start); + } + else +#endif + __LZTimerOn(tm); +} + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Long Period Zen Timer and keeps it +running. + +HEADER: +ztimer.h + +PARAMETERS: +tm - Timer object to do lap timing with + +RETURNS: +Count that has elapsed in microseconds. + +REMARKS: +Returns the current count that has elapsed since the last call to +LZTimerOn in microseconds. The time continues to run after this function is +called so you can call this function repeatedly. + +SEE ALSO: +LZTimerOn, LZTimerOff, LZTimerCount +****************************************************************************/ +ulong ZAPI LZTimerLapExt( + LZTimerObject *tm) +{ +#ifdef __INTEL__ + CPU_largeInteger tmLap,tmCount; + + if (haveRDTSC) { + _CPU_readTimeStamp(&tmLap); + _CPU_diffTime64(&tm->start,&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,cpuSpeed); + } + else +#endif + return __LZTimerLap(tm); +} + +/**************************************************************************** +DESCRIPTION: +Stops the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +PARAMETERS: +tm - Timer object to stop timing with + +REMARKS: +Stops the Long Period Zen Timer counting and latches the count. Once you +have stopped the timer you can read the count with LZTimerCount. If you need +highly accurate timing, you should use the on and off functions rather than +the lap function since the lap function does not subtract the overhead of +the function calls from the timed count. + +SEE ALSO: +LZTimerOn, LZTimerLap, LZTimerCount +****************************************************************************/ +void ZAPI LZTimerOffExt( + LZTimerObject *tm) +{ +#ifdef __INTEL__ + if (haveRDTSC) { + _CPU_readTimeStamp(&tm->end); + } + else +#endif + __LZTimerOff(tm); +} + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Long Period Zen Timer. + +HEADER: +ztimer.h + +PARAMETERS: +tm - Timer object to compute the elapsed time with. + +RETURNS: +Count that has elapsed in microseconds. + +REMARKS: +Returns the current count that has elapsed between calls to +LZTimerOn and LZTimerOff in microseconds. + +SEE ALSO: +LZTimerOn, LZTimerOff, LZTimerLap +****************************************************************************/ +ulong ZAPI LZTimerCountExt( + LZTimerObject *tm) +{ +#ifdef __INTEL__ + CPU_largeInteger tmCount; + + if (haveRDTSC) { + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,cpuSpeed); + } + else +#endif + return __LZTimerCount(tm); +} + +/**************************************************************************** +DESCRIPTION: +Starts the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +REMARKS: +Obsolete function. You should use the LZTimerOnExt function instead +which allows for multiple timers running at the same time. +****************************************************************************/ +void ZAPI LZTimerOn(void) +{ LZTimerOnExt(&LZTimer); } + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Long Period Zen Timer and keeps it +running. + +HEADER: +ztimer.h + +RETURNS: +Count that has elapsed in microseconds. + +REMARKS: +Obsolete function. You should use the LZTimerLapExt function instead +which allows for multiple timers running at the same time. +****************************************************************************/ +ulong ZAPI LZTimerLap(void) +{ return LZTimerLapExt(&LZTimer); } + +/**************************************************************************** +DESCRIPTION: +Stops the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +REMARKS: +Obsolete function. You should use the LZTimerOffExt function instead +which allows for multiple timers running at the same time. +****************************************************************************/ +void ZAPI LZTimerOff(void) +{ LZTimerOffExt(&LZTimer); } + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Long Period Zen Timer. + +HEADER: +ztimer.h + +RETURNS: +Count that has elapsed in microseconds. + +REMARKS: +Obsolete function. You should use the LZTimerCountExt function instead +which allows for multiple timers running at the same time. +****************************************************************************/ +ulong ZAPI LZTimerCount(void) +{ return LZTimerCountExt(&LZTimer); } + +/**************************************************************************** +DESCRIPTION: +Starts the Ultra Long Period Zen Timer counting. + +HEADER: +ztimer.h + +REMARKS: +Starts the Ultra Long Period Zen Timer counting. Once you have started the +timer, you can stop it with ULZTimerOff or you can latch the current count +with ULZTimerLap. + +The Ultra Long Period Zen Timer uses the available operating system services +to obtain accurate timings results with as much precision as the operating +system provides, but with enough granularity to time longer periods of +time than the Long Period Zen Timer. Note that the resolution of the timer +ticks is not constant between different platforms, and you should use the +ULZTimerResolution function to determine the number of seconds in a single +tick of the timer, and use this to convert the timer counts to seconds. + +Under 32-bit Windows, we use the timeGetTime function which provides a +resolution of 1 millisecond (0.001 of a second). Given that the timer +count is returned as an unsigned 32-bit integer, this we can time intervals +that are a maximum of 2^32 milliseconds in length (or about 1,200 hours or +50 days!). + +Under 32-bit DOS, we use the system timer tick which runs at 18.2 times per +second. Given that the timer count is returned as an unsigned 32-bit integer, +this we can time intervals that are a maximum of 2^32 * (1/18.2) in length +(or about 65,550 hours or 2731 days!). + +SEE ALSO: +ULZTimerOff, ULZTimerLap, ULZTimerCount, ULZElapsedTime, ULZReadTime +****************************************************************************/ +void ZAPI ULZTimerOn(void) +{ start = __ULZReadTime(); } + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Ultra Long Period Zen Timer and keeps it +running. + +HEADER: +ztimer.h + +RETURNS: +Count that has elapsed in resolution counts. + +REMARKS: +Returns the current count that has elapsed since the last call to +ULZTimerOn in microseconds. The time continues to run after this function is +called so you can call this function repeatedly. + +SEE ALSO: +ULZTimerOn, ULZTimerOff, ULZTimerCount +****************************************************************************/ +ulong ZAPI ULZTimerLap(void) +{ return (__ULZReadTime() - start); } + +/**************************************************************************** +DESCRIPTION: +Stops the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +REMARKS: +Stops the Ultra Long Period Zen Timer counting and latches the count. Once +you have stopped the timer you can read the count with ULZTimerCount. + +SEE ALSO: +ULZTimerOn, ULZTimerLap, ULZTimerCount +****************************************************************************/ +void ZAPI ULZTimerOff(void) +{ finish = __ULZReadTime(); } + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Ultra Long Period Zen Timer. + +HEADER: +ztimer.h + +RETURNS: +Count that has elapsed in resolution counts. + +REMARKS: +Returns the current count that has elapsed between calls to +ULZTimerOn and ULZTimerOff in resolution counts. + +SEE ALSO: +ULZTimerOn, ULZTimerOff, ULZTimerLap, ULZTimerResolution +****************************************************************************/ +ulong ZAPI ULZTimerCount(void) +{ return (finish - start); } + +/**************************************************************************** +DESCRIPTION: +Reads the current time from the Ultra Long Period Zen Timer. + +HEADER: +ztimer.h + +RETURNS: +Current timer value in resolution counts. + +REMARKS: +Reads the current Ultra Long Period Zen Timer and returns it’s current +count. You can use the ULZElapsedTime function to find the elapsed time +between two timer count readings. + +SEE ALSO: +ULZElapsedTime, ULZTimerResolution +****************************************************************************/ +ulong ZAPI ULZReadTime(void) +{ return __ULZReadTime(); } + +/**************************************************************************** +DESCRIPTION: +Compute the elapsed time between two timer counts. + +HEADER: +ztimer.h + +PARAMETERS: +start - Starting time for elapsed count +finish - Ending time for elapsed count + +RETURNS: +Elapsed timer in resolution counts. + +REMARKS: +Returns the elapsed time for the Ultra Long Period Zen Timer in units of the +timers resolution (1/18th of a second under DOS). This function correctly +computes the difference even if a midnight boundary has been crossed +during the timing period. + +SEE ALSO: +ULZReadTime, ULZTimerResolution +****************************************************************************/ +ulong ZAPI ULZElapsedTime( + ulong start, + ulong finish) +{ return __ULZElapsedTime(start,finish); } + +/**************************************************************************** +DESCRIPTION: +Returns the resolution of the Ultra Long Period Zen Timer. + +HEADER: +ztimer.h + +PARAMETERS: +resolution - Place to store the timer in microseconds per timer count. + +REMARKS: +Returns the resolution of the Ultra Long Period Zen Timer as a 32-bit +integer value measured in microseconds per timer count. + +SEE ALSO: +ULZReadTime, ULZElapsedTime, ULZTimerCount +****************************************************************************/ +void ZAPI ULZTimerResolution( + ulong *resolution) +{ *resolution = ULZTIMER_RESOLUTION; } diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h b/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h new file mode 100644 index 0000000..77c545a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h @@ -0,0 +1,450 @@ +/* $XConsortium: AsmMacros.h /main/13 1996/10/25 11:33:12 kaleb $ */ +/* + * (c) Copyright 1993,1994 by David Wexelblat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of David Wexelblat shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from David Wexelblat. + * + */ +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * This software is furnished under license and may be used and copied only in + * accordance with the following terms and conditions. Subject to these + * conditions, you may download, copy, install, use, modify and distribute + * this software in source and/or binary form. No title or ownership is + * transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce and retain + * this copyright notice and list of conditions as they appear in the source + * file. + * + * 2) No right is granted to use any trade name, trademark, or logo of Digital + * Equipment Corporation. Neither the "Digital Equipment Corporation" name + * nor any trademark or logo of Digital Equipment Corporation may be used + * to endorse or promote products derived from this software without the + * prior written permission of Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied warranties, + * including but not limited to, any implied warranties of merchantability, + * fitness for a particular purpose, or non-infringement are disclaimed. In + * no event shall DIGITAL be liable for any damages whatsoever, and in + * particular, DIGITAL shall not be liable for special, indirect, + * consequential, or incidental damages or damages for + * lost profits, loss of revenue or loss of use, whether such damages arise + * in contract, + * negligence, tort, under statute, in equity, at law or otherwise, even if + * advised of the possibility of such damage. + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/AsmMacros.h,v 3.14 1999/09/25 14:36:58 dawes Exp $ */ + +#if defined(__GNUC__) +#if defined(linux) && (defined(__alpha__) || defined(__ia64__)) +#undef inb +#define inb _inb +#undef inw +#define inw _inw +#undef inl +#define inl _inl +#undef outb +#define outb(p,v) _outb((v),(p)) +#undef outw +#define outw(p,v) _outw((v),(p)) +#undef outl +#define outl(p,v) _outl((v),(p)) +#else +#if defined(__sparc__) +#ifndef ASI_PL +#define ASI_PL 0x88 +#endif + +static __inline__ void +outb(port, val) +unsigned long port; +char val; +{ + __asm__ __volatile__("stba %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ void +outw(port, val) +unsigned long port; +char val; +{ + __asm__ __volatile__("stha %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ void +outl(port, val) +unsigned long port; +char val; +{ + __asm__ __volatile__("sta %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ unsigned int +inb(port) +unsigned long port; +{ + unsigned char ret; + __asm__ __volatile__("lduba [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +inw(port) +unsigned long port; +{ + unsigned char ret; + __asm__ __volatile__("lduha [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +inl(port) +unsigned long port; +{ + unsigned char ret; + __asm__ __volatile__("lda [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} +#else +#ifdef __arm32__ +unsigned int IOPortBase; /* Memory mapped I/O port area */ + +static __inline__ void +outb(port, val) + short port; + char val; +{ + if ((unsigned short)port >= 0x400) return; + + *(volatile unsigned char*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ void +outw(port, val) + short port; + short val; +{ + if ((unsigned short)port >= 0x400) return; + + *(volatile unsigned short*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ void +outl(port, val) + short port; + int val; +{ + if ((unsigned short)port >= 0x400) return; + + *(volatile unsigned long*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ unsigned int +inb(port) + short port; +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + + return(*(volatile unsigned char*)(((unsigned short)(port))+IOPortBase)); +} + +static __inline__ unsigned int +inw(port) + short port; +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + + return(*(volatile unsigned short*)(((unsigned short)(port))+IOPortBase)); +} + +static __inline__ unsigned int +inl(port) + short port; +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + + return(*(volatile unsigned long*)(((unsigned short)(port))+IOPortBase)); +} +#else /* __arm32__ */ +#if defined(Lynx) && defined(__powerpc__) +extern unsigned char *ioBase; + +static volatile void +eieio() +{ + __asm__ __volatile__ ("eieio"); +} + +static void +outb(port, value) +short port; +unsigned char value; +{ + *(uchar *)(ioBase + port) = value; eieio(); +} + +static void +outw(port, value) +short port; +unsigned short value; +{ + *(unsigned short *)(ioBase + port) = value; eieio(); +} + +static void +outl(port, value) +short port; +unsigned long value; +{ + *(unsigned long *)(ioBase + port) = value; eieio(); +} + +static unsigned char +inb(port) +short port; +{ + unsigned char val; + + val = *((unsigned char *)(ioBase + port)); eieio(); + return(val); +} + +static unsigned short +inw(port) +short port; +{ + unsigned short val; + + val = *((unsigned short *)(ioBase + port)); eieio(); + return(val); +} + +static unsigned long +inl(port) +short port; +{ + unsigned long val; + + val = *((unsigned long *)(ioBase + port)); eieio(); + return(val); +} + +#else +#if defined(__FreeBSD__) && defined(__alpha__) + +#include + +extern void outb(u_int32_t port, u_int8_t val); +extern void outw(u_int32_t port, u_int16_t val); +extern void outl(u_int32_t port, u_int32_t val); +extern u_int8_t inb(u_int32_t port); +extern u_int16_t inw(u_int32_t port); +extern u_int32_t inl(u_int32_t port); + +#else +#ifdef GCCUSESGAS +static __inline__ void +outb(port, val) +short port; +char val; +{ + __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ void +outw(port, val) +short port; +short val; +{ + __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(port, val) +short port; +unsigned int val; +{ + __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(port) +short port; +{ + unsigned char ret; + __asm__ __volatile__("inb %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(port) +short port; +{ + unsigned short ret; + __asm__ __volatile__("inw %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(port) +short port; +{ + unsigned int ret; + __asm__ __volatile__("inl %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +#else /* GCCUSESGAS */ + +static __inline__ void +outb(port, val) + short port; + char val; +{ + __asm__ __volatile__("out%B0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ void +outw(port, val) + short port; + short val; +{ + __asm__ __volatile__("out%W0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(port, val) + short port; + unsigned int val; +{ + __asm__ __volatile__("out%L0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(port) + short port; +{ + unsigned int ret; + __asm__ __volatile__("in%B0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(port) + short port; +{ + unsigned int ret; + __asm__ __volatile__("in%W0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(port) + short port; +{ + unsigned int ret; + __asm__ __volatile__("in%L0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +#endif /* GCCUSESGAS */ +#endif /* Lynx && __powerpc__ */ +#endif /* arm32 */ +#endif /* linux && __sparc__ */ +#endif /* linux && __alpha__ */ +#endif /* __FreeBSD__ && __alpha__ */ + +#if defined(linux) || defined(__arm32__) || (defined(Lynx) && defined(__powerpc__)) + +#define intr_disable() +#define intr_enable() + +#else + +static __inline__ void +intr_disable() +{ + __asm__ __volatile__("cli"); +} + +static __inline__ void +intr_enable() +{ + __asm__ __volatile__("sti"); +} + +#endif /* else !linux && !__arm32__ */ + +#else /* __GNUC__ */ + +#if defined(_MINIX) && defined(_ACK) + +/* inb, outb, inw and outw are defined in the library */ +/* ... but I've no idea if the same is true for inl & outl */ + +u8_t inb(U16_t); +void outb(U16_t, U8_t); +u16_t inw(U16_t); +void outw(U16_t, U16_t); +u32_t inl(U16_t); +void outl(U16_t, U32_t); + +#else /* not _MINIX and _ACK */ + +# if defined(__STDC__) && (__STDC__ == 1) +# ifndef NCR +# define asm __asm +# endif +# endif +# ifdef SVR4 +# include +# ifndef __USLC__ +# define __USLC__ +# endif +# endif +#ifndef SCO325 +# include +#else +# include "../common/scoasm.h" +#endif +#define intr_disable() asm("cli") +#define intr_enable() asm("sti") + +#endif /* _MINIX and _ACK */ +#endif /* __GNUC__ */ diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/README b/board/MAI/bios_emulator/scitech/src/v86bios/README new file mode 100644 index 0000000..cb65674 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/README @@ -0,0 +1,32 @@ + +This is a preliminary version of a VGA softbooter for LINUX. + +It makes use of the of the vm86() call and is therefore only +usable on ix86 systems. +There are plans to port this program to use a x86 emulator +like x86emu. Also it may be ported to other operating systems. + +So far it has been tested on a small number of cards. It might +well be that it will fail on your card. + +If you need to make modifications to the programs to be able +to boot your card please let the author know. + +So far there is no command line interface. All options need +to be hardcoded. You can do this by editing debug.h. You can +turn on a bunch of debug output. Other options allow you to +boot the primary card (CONFIG_ACTIVE_DEVICE), save the bios +to a file (SAVE_BIOS), and map the original system bios +(MAP_SYS_BIOS). + +The author wants to thank + Hans Lermen (dosemu) + and + Kendall Bennett (x86emu) +for their support. + +Parts of the code - especially in v86.c and io.c - are based on code +taken from dosemu. Parts of the code in int.c are based on code taken +from x86emu + +Egbert Eich. diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr b/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr new file mode 100644 index 0000000..9d2a80d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr @@ -0,0 +1,15 @@ +/.*\(0x3da.*/||/.*\(0x3ba.*/ { + if (v_3da != 1) print "_v_retrace_"; + v_3da = 1; + next; + } +/.*\(0x42.*/||/.*\(0x43.*/ { + if (v_4x != 1) print "_timer_"; + v_4x = 1; + next; +} +{ + print; + v_3da = 0; + v_4x = 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c b/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c new file mode 100644 index 0000000..6b12dff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c @@ -0,0 +1,415 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(__alpha__) || defined (__ia64__) +#include +#elif defined(HAVE_SYS_PERM) +#include +#endif +#include "debug.h" +#include "v86bios.h" +#include "pci.h" +#include "AsmMacros.h" + +#define SIZE 0x100000 +#define VRAM_START 0xA0000 +#define VRAM_SIZE 0x1FFFF +#define V_BIOS_SIZE 0x1FFFF +#define BIOS_START 0x7C00 /* default BIOS entry */ +#define BIOS_MEM 0x600 + +CARD8 code[] = { 0xcd, 0x10, 0xf4 }; +struct config Config; + +static int map(void); +static void unmap(void); +static void runBIOS(int argc, char **argv); +static int map_vram(void); +static void unmap_vram(void); +static int copy_vbios(memType base); +static int copy_sys_bios(void); +static CARD32 setup_int_vect(void); +static void update_bios_vars(void); +static int chksum(CARD8 *start); +static void setup_bios_regs(i86biosRegsPtr regs, int argc, char **argv); +static void print_regs(i86biosRegsPtr regs); +void dprint(unsigned long start, unsigned long size); + +void loadCodeToMem(unsigned char *ptr, CARD8 *code); + +static int vram_mapped = 0; +static char* bios_var; + + +int +main(int argc,char **argv) +{ + CARD32 vbios_base; + + Config.PrintPort = PRINT_PORT; + Config.IoStatistics = IO_STATISTICS; + Config.PrintIrq = PRINT_IRQ; + Config.PrintPci = PRINT_PCI; + Config.ShowAllDev = SHOW_ALL_DEV; + Config.PrintIp = PRINT_IP; + Config.SaveBios = SAVE_BIOS; + Config.Trace = TRACE; + Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY; + Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; + Config.MapSysBios = MAP_SYS_BIOS; + Config.Resort = RESORT; + Config.FixRom = FIX_ROM; + Config.NoConsole = NO_CONSOLE; + Config.Verbose = VERBOSE; + + if (!map()) + exit(1); + if (!copy_sys_bios()) + exit(1); + if (!(vbios_base = setup_int_vect())) + exit(1); + if (!map_vram()) + exit(1); + if (!copy_vbios(vbios_base)) + exit(1); + + iopl(3); + setup_io(); + runBIOS(argc,argv); + update_bios_vars(); + unmap_vram(); + iopl(0); + unmap(); + printf("done !\n"); + exit (1); +} + +int +map(void) +{ + void* mem; + + mem = mmap(0, (size_t)SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_PRIVATE | MAP_ANON, + -1, 0 ); + if (mem != 0) { + perror("anonymous map"); + return (0); + } + memset(mem,0,SIZE); + + loadCodeToMem((unsigned char *) BIOS_START, code); + return (1); +} + +static int +copy_sys_bios(void) +{ +#define SYS_BIOS 0xF0000 + int mem_fd; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS) + goto Error; + if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF) + goto Error; + + close(mem_fd); + return (1); + +Error: + perror("sys_bios"); + close(mem_fd); + return (0); +} + +static int +map_vram(void) +{ + int mem_fd; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return 0; + } + +#ifndef __alpha__ + if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, + mem_fd, VRAM_START) == (void *) -1) +#else + if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */ + if (!_bus_base_sparse()) sparse_shift = 0; + if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift), + PROT_READ | PROT_WRITE, + MAP_SHARED, + mem_fd, (VRAM_START << sparse_shift) + | _bus_base_sparse())) == (void *) -1) +#endif + { + perror("mmap error in map_hardware_ram"); + close(mem_fd); + return (0); + } + vram_mapped = 1; + close(mem_fd); + return (1); +} + +static int +copy_vbios(memType v_base) +{ + int mem_fd; + unsigned char *tmp; + int size; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) v_base, SEEK_SET) != (off_t) v_base) { + fprintf(stderr,"Cannot lseek\n"); + goto Error; + } + tmp = (unsigned char *)malloc(3); + if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + if (lseek(mem_fd,(off_t) v_base,SEEK_SET) != (off_t) v_base) + goto Error; + + if (*tmp != 0x55 || *(tmp+1) != 0xAA ) { + fprintf(stderr,"No bios found at: 0x%lx\n",v_base); + goto Error; + } +#ifdef DEBUG + dprint((unsigned long)tmp,0x100); +#endif + size = *(tmp+2) * 512; + + if (read(mem_fd, (char *)v_base, (size_t) size) != (size_t) size) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + free(tmp); + close(mem_fd); + if (!chksum((CARD8*)v_base)) + return (0); + + return (1); + +Error: + perror("v_bios"); + close(mem_fd); + return (0); +} + +static void +unmap(void) +{ + munmap(0,SIZE); +} + +static void +unmap_vram(void) +{ + if (!vram_mapped) return; + + munmap((void*)VRAM_START,VRAM_SIZE); + vram_mapped = 0; +} + +static void +runBIOS(int argc, char ** argv) +{ + i86biosRegs bRegs; +#ifdef V86BIOS_DEBUG + printf("starting BIOS\n"); +#endif + setup_bios_regs(&bRegs, argc, argv); + do_x86(BIOS_START,&bRegs); + print_regs(&bRegs); +#ifdef V86BIOS_DEBUG + printf("done\n"); +#endif +} + +static CARD32 +setup_int_vect(void) +{ + int mem_fd; + CARD32 vbase; + void *map; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if ((map = mmap((void *) 0, (size_t) 0x2000, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, + mem_fd, 0)) == (void *)-1) { + perror("mmap error in map_hardware_ram"); + close(mem_fd); + return (0); + } + + close(mem_fd); + memcpy(0,map,BIOS_MEM); + munmap(map,0x2000); + /* + * create a backup copy of the bios variables to write back the + * modified values + */ + bios_var = (char *)malloc(BIOS_MEM); + memcpy(bios_var,0,BIOS_MEM); + + vbase = (*((CARD16*)(0x10 << 2) + 1)) << 4; + fprintf(stderr,"vbase: 0x%x\n",vbase); + return vbase; +} + +static void +update_bios_vars(void) +{ + int mem_fd; + void *map; + memType i; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return; + } + + if ((map = mmap((void *) 0, (size_t) 0x2000, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, + mem_fd, 0)) == (void *)-1) { + perror("mmap error in map_hardware_ram"); + close(mem_fd); + return; + } + + for (i = 0; i < BIOS_MEM; i++) { + if (bios_var[i] != *(CARD8*)i) + *((CARD8*)map + i) = *(CARD8*)i; + } + + munmap(map,0x2000); + close(mem_fd); +} + + +static void +setup_bios_regs(i86biosRegsPtr regs, int argc, char **argv) +{ + int c; + + regs->ax = 0; + regs->bx = 0; + regs->cx = 0; + regs->dx = 0; + regs->es = 0; + regs->di = 0; + opterr = 0; + while ((c = getopt(argc,argv,"a:b:c:d:e:i:")) != EOF) { + switch (c) { + case 'a': + regs->ax = strtol(optarg,NULL,0); + break; + case 'b': + regs->bx = strtol(optarg,NULL,0); + break; + case 'c': + regs->cx = strtol(optarg,NULL,0); + break; + case 'd': + regs->dx = strtol(optarg,NULL,0); + break; + case 'e': + regs->es = strtol(optarg,NULL,0); + break; + case 'i': + regs->di = strtol(optarg,NULL,0); + break; + } + } +} + + +static int +chksum(CARD8 *start) +{ + CARD16 size; + CARD8 val = 0; + int i; + + size = *(start+2) * 512; + for (i = 0; iax, + (CARD16)regs->bx,(CARD16)regs->cx,(CARD16)regs->dx, + (CARD16)regs->es,(CARD16)regs->di); +} + +void +loadCodeToMem(unsigned char *ptr, CARD8 code[]) +{ + int i; + CARD8 val; + + for ( i=0;;i++) { + val = code[i]; + *ptr++ = val; + if (val == 0xf4) break; + } + return; +} + +void +dprint(unsigned long start, unsigned long size) +{ + int i,j; + char *c = (char *)start; + + for (j = 0; j < (size >> 4); j++) { + printf ("\n0x%lx: ",(unsigned long)c); + for (i = 0; i<16; i++) + printf("%x ",(unsigned char) (*(c++))); + } + printf("\n"); +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/command.c b/board/MAI/bios_emulator/scitech/src/v86bios/command.c new file mode 100644 index 0000000..e2bce6d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/command.c @@ -0,0 +1,38 @@ +#include +#include +#include +#include + +#define PROMPT ">" + + +void +getline(char *buf,int *num,int max_num) +{ + static int line_len = 0; + static char *line = NULL; + static char *line_pointer = NULL; + static int len = 0; + int tmp_len; + char *buff; + + if (len <= 0) { + buff = readline(PROMPT); + add_history(buff); + + if ((tmp_len = strlen(buff)) > line_len) { + free(line); + line = malloc(tmp_len); + line_len = tmp_len; + } + sprintf(line,"%s\n",buff); + free(buff); + line_pointer = line; + len = strlen(line); + } + + *num = max_num > len? len : max_num; + strncpy(buf,line_pointer,*num); + line_pointer = line_pointer + *num; + len = len - *num; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/console.c b/board/MAI/bios_emulator/scitech/src/v86bios/console.c new file mode 100644 index 0000000..5e9c924 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/console.c @@ -0,0 +1,95 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include "debug.h" +#include "v86bios.h" + +console +open_console(void) +{ + int fd; + int VTno; + char VTname[11]; + console Con = {-1,-1}; + struct vt_stat vts; + + if (NO_CONSOLE) + return Con; + + if ((fd = open("/dev/tty0",O_WRONLY,0)) < 0) + return Con; + + if ((ioctl(fd, VT_OPENQRY, &VTno) < 0) || (VTno == -1)) { + fprintf(stderr,"cannot get a vt\n"); + return Con; + } + + close(fd); + sprintf(VTname,"/dev/tty%i",VTno); + + if ((fd = open(VTname, O_RDWR|O_NDELAY, 0)) < 0) { + fprintf(stderr,"cannot open console\n"); + return Con; + } + + if (ioctl(fd, VT_GETSTATE, &vts) == 0) + Con.vt = vts.v_active; + + if (ioctl(fd, VT_ACTIVATE, VTno) != 0) { + fprintf(stderr,"cannot activate console\n"); + close(fd); + return Con; + } + if (ioctl(fd, VT_WAITACTIVE, VTno) != 0) { + fprintf(stderr,"wait for active console failed\n"); + close(fd); + return Con; + } +#if 0 + if (ioctl(fd, KDSETMODE, KD_GRAPHICS) < 0) { + close(fd); + return Con; + } +#endif + Con.fd = fd; + return Con; +} + +void +close_console(console Con) +{ + if (Con.fd == -1) + return; + +#if 0 + ioctl(Con.fd, KDSETMODE, KD_TEXT); +#endif + if (Con.vt >=0) + ioctl(Con.fd, VT_ACTIVATE, Con.vt); + + close(Con.fd); +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/debug.h b/board/MAI/bios_emulator/scitech/src/v86bios/debug.h new file mode 100644 index 0000000..c5c906b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/debug.h @@ -0,0 +1,60 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/*#define V86BIOS_DEBUG */ + +/* + * uncomment the following if needed + * should be command line options + */ + +#define PRINT_PORT 0 +#define IO_STATISTICS 0 +#define PRINT_IRQ 0 +#define PRINT_PCI 1 +#define PRINT_IP 0 /* print IP address with PIO information */ +#define TRACE 0 /* turn on debugger in x86emu */ + /* requires x86emu compiled with -DDEBUG */ + +/* + * these should not be here. + * Should be converted to command line options. + */ +#define CONFIG_ACTIVE_ONLY 0 +#define CONFIG_ACTIVE_DEVICE 1 +#define SAVE_BIOS 0 +#define MAP_SYS_BIOS 1 +#define RESORT 1 +#define FIX_ROM 0 +#define NO_CONSOLE 0 +#define SHOW_ALL_DEV 0 +#define VERBOSE 0 + +/*#define V_BIOS 0xe0000 */ +/*#define V_BIOS 0xe4000 */ + + +#if (PRINT_IO == 1) && (PRINT_PORT == 0) +# define PRINT_IO 0 +#endif +#if (IO_STATISTICS == 1) && (PRINT_PORT == 0) +# define IO_STATISTICS 0 +#endif diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards b/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards new file mode 100644 index 0000000..943d44e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards @@ -0,0 +1,76 @@ +What I had to do to make cards happy: + +1. Tseng ET4000 W32P +This card wants to call the original system BIOS video routines. +It sets the int 0x42 vector to F000:F065, the entry point to the +system bios video routines. +CAVE: don't catch int 0x42 and use the vbios int 0x10 routines. +At early stage during initialization they call int 0x42. This +causes an infinite loop. + +2. ATi Mach64 Rage IIc AGP +This card does similar things like the Tseng ET4000 W32P. +However it doesn't have the problem with the ininite loop. + +3. Elsa Victory II-A16 AGP Banshee +This card is very clever: It knows it is an AGP card. Therefore +it knows it is behind a PCI-PCI bridge. It also knows that noone +else is behind this bridge. Therefore it start reprogramming the +bridge! For this it assumes the AGP bridge is on bus 1. + +4. Elsa Gloria Synergy 8 ViVo AGP PM2 +This card likes to see a complete interrupt vector table. If +we fill this table with 0 the VBIOS detects this and quits +initialization. + +5. Dimond Viper 330 AGP NVIDIA Riva 128. +This card has a similar problem like the Elsa Gloria. It wants +to read the system BIOS date at 0xffffd. + +6. Matrox Mystique PCI +This card reads the IO port 0x62. If it doesn't like what it sees +it loops forever. To keep the card happy put 0xfc into 0xffffe. +This location holds the system model id. 0xfc means IBM-AT. + One can make an interesting observation: this card likes to know +with whom it has to share the system. Therefore it accesses PCI +config space of all the other cards. It does this bypassing the +PCI BIOS by reading the PCI access ports directly. + +7. Matrox G100 AGP +This card has the same problem as the Mystique. + +Apperantly this works now. However not all combinations of cards are +checked, yet. + +Further notes: +the IO register 0x42-0x43 as well as 0x61-0x63 are of special interest +for many graphic cards. They should be emulated. +The so called "Industry Standard BIOS Entry Points" to int 0x42 (0xFF065) +and to int 0x1a (0xFFE6E) should be filled with useful code. This code +needs to return as if it was called as int. +The subvendor ID PCI registers might cause problems. On some chipsets +they are programmed in a non-obivous non-PCI conformant way. +V_Bioses are seen to modify the following int: +0x10 (default video), 0x1f(font table), 0x42(copy of default video), +0x43 (??), 0x6d (copy of default video - same as 0x10?) + +TODO: +Int 0x6d needs to be done. +All interrupts where there is no default industry standard entry point +should point to an unused location in the 0xF000 segmant (possibly +0xF0000). This way they could be trapped. A trap handler for +a. int 0x42 and int 0x1a needs to be implemented. +The default "industry entry point" for video and PCI (0xFFE6E) should +also be implemented. (any others?) They should either be routed to +int 0x42(0x6d?) (video) and 0x1A (PCI) or some other interrupts to +trap them. Mapping of system bios might not be a good idea. Maybe +the system bios area should just be filled with "hlt" to trap any +access there. +Handling of timer IO registers 0x42, 0x43 and IO registers 0x61, 0x62. + +Find documentation: +- on interrupt vector table +- on industry standard entry points to the system bios +- on IO registers 0x61 and 0x62 + + diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/hexdump b/board/MAI/bios_emulator/scitech/src/v86bios/hexdump new file mode 100644 index 0000000..4f359e5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/hexdump @@ -0,0 +1,3 @@ +"%06.6_ax " 16/1 "%02x " +" " 16/1 "%_p" +"\n" diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/int.c b/board/MAI/bios_emulator/scitech/src/v86bios/int.c new file mode 100644 index 0000000..3504c6c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/int.c @@ -0,0 +1,238 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "debug.h" +#if defined(__alpha__) || defined (__ia64__) +#include +#endif + +#include "v86bios.h" +#include "AsmMacros.h" +#include "pci.h" + +static int int1A_handler(struct regs86 *regs); +static int int42_handler(int num, struct regs86 *regs); + +int +int_handler(int num, struct regs86 *regs) +{ + switch (num) { + case 0x10: + case 0x42: + return (int42_handler(num,regs)); + case 0x1A: + return (int1A_handler(regs)); + default: + return 0; + } + return 0; +} + +static int +int42_handler(int num,struct regs86 *regs) +{ + unsigned char c; + CARD32 val; + + i_printf("int 0x%x: ax:0x%lx bx:0x%lx cx:0x%lx dx:0x%lx\n",num, + regs->eax,regs->ebx, regs->ecx, regs->edx); + + /* + * video bios has modified these - + * leave it to the video bios to do this + */ + + val = getIntVect(num); + if (val != 0xF000F065) + return 0; + + if ((regs->ebx & 0xff) == 0x32) { + switch (regs->eax & 0xFFFF) { + case 0x1200: + i_printf("enabling video\n"); + c = inb(0x3cc); + c |= 0x02; + outb(0x3c2,c); + return 1; + case 0x1201: + i_printf("disabling video\n"); + c = inb(0x3cc); + c &= ~0x02; + outb(0x3c2,c); + return 1; + default: + } + } + if (num == 0x42) + return 1; + else + return 0; +} + +#define SUCCESSFUL 0x00 +#define DEVICE_NOT_FOUND 0x86 +#define BAD_REGISTER_NUMBER 0x87 + +static int +int1A_handler(struct regs86 *regs) +{ + CARD32 Slot; + PciStructPtr pPci; + + if (! CurrentPci) return 0; /* oops */ + + i_printf("int 0x1a: ax=0x%lx bx=0x%lx cx=0x%lx dx=0x%lx di=0x%lx" + " si=0x%lx\n", regs->eax,regs->ebx,regs->ecx,regs->edx, + regs->edi,regs->esi); + switch (regs->eax & 0xFFFF) { + case 0xb101: + regs->eax &= 0xFF00; /* no config space/special cycle support */ + regs->edx = 0x20494350; /* " ICP" */ + regs->ebx = 0x0210; /* Version 2.10 */ + regs->ecx &= 0xFF00; + regs->ecx |= (pciMaxBus & 0xFF); /* Max bus number in system */ + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + i_printf("ax=0x%lx dx=0x%lx bx=0x%lx cx=0x%lx flags=0x%lx\n", + regs->eax,regs->edx,regs->ebx,regs->ecx,regs->eflags); + return 1; + case 0xb102: + if (((regs->edx & 0xFFFF) == CurrentPci->VendorID) && + ((regs->ecx & 0xFFFF) == CurrentPci->DeviceID) && + (regs->esi == 0)) { + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + regs->ebx = pciSlotBX(CurrentPci); + } + else if (Config.ShowAllDev && + (pPci = findPciDevice(regs->edx,regs->ecx,regs->esi)) != NULL) { + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + regs->ebx = pciSlotBX(pPci); + } else { + regs->eax = (regs->eax & 0x00FF) | (DEVICE_NOT_FOUND << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx bx=0x%lx flags=0x%lx\n", + regs->eax,regs->ebx,regs->eflags); + return 1; + case 0xb103: + if (((regs->ecx & 0xFF) == CurrentPci->Interface) && + (((regs->ecx & 0xFF00) >> 8) == CurrentPci->SubClass) && + (((regs->ecx & 0xFFFF0000) >> 16) == CurrentPci->BaseClass) && + ((regs->esi & 0xff) == 0)) { + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->ebx = pciSlotBX(CurrentPci); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } + else if (Config.ShowAllDev + && (pPci = findPciClass(regs->ecx & 0xFF, (regs->ecx & 0xff00) >> 8, + (regs->ecx & 0xffff0000) >> 16, regs->esi)) != NULL) { + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->ebx = pciSlotBX(pPci); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (DEVICE_NOT_FOUND << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx flags=0x%lx\n",regs->eax,regs->eflags); + return 1; + case 0xb108: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + regs->ecx &= 0xFFFFFF00; + regs->ecx |= PciRead8(regs->edi,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n", + regs->eax,regs->ecx,regs->eflags); + return 1; + case 0xb109: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + regs->ecx &= 0xFFFF0000; + regs->ecx |= PciRead16(regs->edi,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n", + regs->eax,regs->ecx,regs->eflags); + return 1; + case 0xb10a: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + regs->ecx &= 0; + regs->ecx |= PciRead32(regs->edi,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n", + regs->eax,regs->ecx,regs->eflags); + return 1; + case 0xb10b: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + PciWrite8(regs->edi,(CARD8)regs->ecx,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags); + return 1; + case 0xb10c: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + PciWrite16(regs->edi,(CARD16)regs->ecx,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags); + return 1; + case 0xb10d: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + PciWrite32(regs->edi,(CARD32)regs->ecx,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags); + return 1; + default: + return 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/io.c b/board/MAI/bios_emulator/scitech/src/v86bios/io.c new file mode 100644 index 0000000..f35b43e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/io.c @@ -0,0 +1,257 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "debug.h" + +#include +#if defined(__alpha__) || defined (__ia64__) +#include +#endif +#include "AsmMacros.h" +#include "v86bios.h" +#include "pci.h" + +int r_inb = 0, r_inw = 0, r_inl = 0, r_outb = 0, r_outw = 0, r_outl = 0; +int in_b = 0, in_w = 0, in_l = 0, out_b = 0, out_w = 0, out_l = 0; + + +int +port_rep_inb(CARD16 port, CARD8 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD8 *dst = base; + + p_printf(" rep_insb(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_inb++; + while (count--) { + *dst = inb(port); + dst += inc; + } + return (dst-base); +} + +int +port_rep_inw(CARD16 port, CARD16 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD16 *dst = base; + + p_printf(" rep_insw(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_inw++; + while (count--) { + *dst = inw(port); + dst += inc; + } + return (dst-base); +} + +int +port_rep_inl(CARD16 port, CARD32 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD32 *dst = base; + + p_printf(" rep_insl(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_inl++; + while (count--) { + *dst = inl(port); + dst += inc; + } + return (dst-base); +} + +int +port_rep_outb(CARD16 port, CARD8 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD8 *dst = base; + + p_printf(" rep_outb(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_outb++; + while (count--) { + outb(port,*dst); + dst += inc; + } + return (dst-base); +} + +int +port_rep_outw(CARD16 port, CARD16 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD16 *dst = base; + + p_printf(" rep_outw(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_outw++; + while (count--) { + outw(port,*dst); + dst += inc; + } + return (dst-base); +} + +int +port_rep_outl(CARD16 port, CARD32 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD32 *dst = base; + + p_printf(" rep_outl(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_outl++; + while (count--) { + outl(port,*dst); + dst += inc; + } + return (dst-base); +} + +CARD8 +p_inb(CARD16 port) +{ + CARD8 val = 0; + in_b++; + val = inb(port); + p_printf(" inb(%#x) = %2.2x",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + return val; +} + +CARD16 +p_inw(CARD16 port) +{ + CARD16 val = 0; + in_w++; + val = inw(port); + p_printf(" inw(%#x) = %4.4x",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + return val; +} + +CARD32 +p_inl(CARD16 port) +{ + CARD32 val = 0; + in_l++; +#ifdef NEED_PCI_IO + if (cfg1in(port,&val)) + return val; + else +#endif + val = inl(port); + p_printf(" inl(%#x) = %8.8x",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + return val; +} + +void +p_outb(CARD16 port, CARD8 val) +{ + out_b++; + p_printf(" outb(%#x, %2.2x)",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + outb(port,val); +} + +void +p_outw(CARD16 port, CARD16 val) +{ + out_w++; + p_printf(" outw(%#x, %4.4x)",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + outw(port,val); +} + +void +p_outl(CARD16 port, CARD32 val) +{ + out_l++; + p_printf(" outl(%#x, %8.8x)",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + +#ifdef NEED_PCI_IO + if (cfg1out(port,val)) + return; +#endif + outl(port,val); +} + +void +io_statistics(void) +{ + p_printf("rep: inb: %i, inw: %i, inl: %i, outb: %i, outw: %i, outl: %i\n", + r_inb,r_inw,r_inl,r_outb,r_outw,r_outl); + p_printf("inb: %i, inw: %i, inl: %i, outb: %i, outw: %i, outl: %i\n", + in_b,in_w,in_l,out_b,out_w,out_l); +} + +void +clear_stat(void) +{ + r_inb = r_inw = r_inl = r_outb = r_outw = r_outl = 0; + in_b = in_w = in_l = out_b = out_w = out_l = 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/lex.l b/board/MAI/bios_emulator/scitech/src/v86bios/lex.l new file mode 100644 index 0000000..3a3391c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/lex.l @@ -0,0 +1,79 @@ +%{ +#include "parser.h" + +#include +#include + + void getline(char *buf,int *num,int max_num); + +#define YY_INPUT(buf,result,max_size) {\ + getline(buf,&result,max_size);\ + } + + void + yyerror (char *s) + { + printf ("%s\n", s); + } + +%} + +DIGIT [0-9a-fA-F] + +%% + +"0x"?{DIGIT}+ { yylval = strtol(yytext,NULL,0); return TOK_NUM; } +"ax" { return TOK_REG_AX; } +"bx" { return TOK_REG_BX; } +"cx" { return TOK_REG_CX; } +"dx" { return TOK_REG_DX; } +"di" { return TOK_REG_SI; } +"si" { return TOK_REG_DI; } +"ds" { return TOK_SEG_DS; } +"es" { return TOK_SEG_ES; } +":" { return TOK_SEP;} +"$"{DIGIT}{1,2} { yylval = strtol(yytext+1,NULL,0); return TOK_VAR; } +"$mem" { return TOK_VAR_MEM; } +[ \t]+ +"#".*[\n] { return TOK_END; } +"boot" { return TOK_COMMAND_BOOT; } +"do" { return TOK_COMMAND_EXEC; } +"\"".*"\"" { yylval = (unsigned long) yytext; return TOK_STRING; } +"byte" { return TOK_BYTE; } +"word" { return TOK_WORD; } +"long" { return TOK_LONG; } +"setmem" { return TOK_COMMAND_MEMSET; } +"dumpmem" { return TOK_COMMAND_MEMDUMP; } +"quit" { return TOK_COMMAND_QUIT; } +"\n" { return TOK_END; } +"select" { return TOK_SELECT; } +"isa" { return TOK_ISA; } +"pci" { return TOK_PCI; } +"pport" { return TOK_PRINT_PORT; } +"iostat" { return TOK_IOSTAT; } +"pirq" { return TOK_PRINT_IRQ; } +"ppci" { return TOK_PPCI; } +"pip" { return TOK_PIP; } +"trace" { return TOK_TRACE; } +"on" { return TOK_ON; } +"off" { return TOK_OFF; } +"verbose" { return TOK_VERBOSE; } +"log" { return TOK_LOG; } +"print" { return TOK_STDOUT; } +"clstat" { return TOK_CLSTAT; } +"hlt" { return TOK_HLT; } +"del" { return TOK_DEL; } +"ioperm" { return TOK_IOPERM; } +"lpci" { return TOK_DUMP_PCI; } +"bootbios" { return TOK_BOOT_BIOS; } +"?" { return '?'; } +. { return TOK_ERROR; } + +%% + + + + + + + diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/main.c b/board/MAI/bios_emulator/scitech/src/v86bios/main.c new file mode 100644 index 0000000..15f9115 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/main.c @@ -0,0 +1,616 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#define DELETE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(__alpha__) || defined (__ia64__) +#include +#elif defined(HAVE_SYS_PERM) +#include +#endif +#include "debug.h" +#include "v86bios.h" +#include "pci.h" +#include "AsmMacros.h" + +#define SIZE 0x100000 +#define VRAM_START 0xA0000 +#define VRAM_SIZE 0x1FFFF +#define V_BIOS_SIZE 0x1FFFF +#define BIOS_START 0x7C00 /* default BIOS entry */ + +/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0, 0xf4 }; */ +#define VB_X(x) (V_BIOS >> x) & 0xFF +CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xf4 }; +/*CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xb8, 0x03, 0x00, */ +/*0xcd, 0x10, 0xf4 }; */ +/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0 ,0xf4 }; */ + +static void sig_handler(int); +static int map(void); +static void unmap(void); +static void bootBIOS(CARD16 ax); +static int map_vram(void); +static void unmap_vram(void); +static int copy_vbios(void); +static int copy_sys_bios(void); +static void save_bios_to_file(void); +static int setup_system_bios(void); +static void setup_int_vect(void); +static int chksum(CARD8 *start); +static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax); + +void loadCodeToMem(unsigned char *ptr, CARD8 *code); +void dprint(unsigned long start, unsigned long size); + +static int vram_mapped = 0; +static CARD8 save_msr; +static CARD8 save_pos102; +static CARD8 save_vse; +static CARD8 save_46e8; +console Console; +struct config Config; + + +int +main(void) +{ + int Active_is_Pci = 0; +#ifdef DELETE + Config.PrintPort = PRINT_PORT; + Config.IoStatistics = IO_STATISTICS; + Config.PrintIrq = PRINT_IRQ; + Config.PrintPci = PRINT_PCI; + Config.ShowAllDev = SHOW_ALL_DEV; + Config.PrintIp = PRINT_IP; + Config.SaveBios = SAVE_BIOS; + Config.Trace = TRACE; + Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY; + Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; + Config.MapSysBios = MAP_SYS_BIOS; + Config.Resort = RESORT; + Config.FixRom = FIX_ROM; + Config.NoConsole = NO_CONSOLE; + Config.Verbose = VERBOSE; + + if (!map()) + exit(1); + + if (!setup_system_bios()) + exit(1); + + iopl(3); + setup_io(); + + scan_pci(); + if (!CurrentPci && !Config.ConfigActiveDevice && !Config.ConfigActiveOnly) + exit (1); +#endif + Console = open_console(); + + if (Config.ConfigActiveOnly) { + CARD16 ax; + int activePci = 0; + int error = 0; + + while (CurrentPci) { + if (CurrentPci->active) { + activePci = 1; + if (!(mapPciRom(NULL) && chksum((CARD8*)V_BIOS))) + error = 1; + break; + } + CurrentPci = CurrentPci->next; + } + ax = ((CARD16)(CurrentPci->bus) << 8) + | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7); + P_printf("ax: 0x%x\n",ax); + setup_int_vect(); + if (!error && (activePci || copy_vbios())) { + + if (Config.SaveBios) save_bios_to_file(); + if (map_vram()) { + printf("initializing ISA\n"); + bootBIOS(0); + } + } + unmap_vram(); + sleep(1); + } else { + /* disable primary card */ + save_msr = inb(0x3CC); + save_vse = inb(0x3C3); + save_46e8 = inb(0x46e8); + save_pos102 = inb(0x102); + + signal(2,sig_handler); + signal(11,sig_handler); + + outb(0x3C2,~(CARD8)0x03 & save_msr); + outb(0x3C3,~(CARD8)0x01 & save_vse); + outb(0x46e8, ~(CARD8)0x08 & save_46e8); + outb(0x102, ~(CARD8)0x01 & save_pos102); + + pciVideoDisable(); + + while (CurrentPci) { + CARD16 ax; + + if (CurrentPci->active) { + Active_is_Pci = 1; + if (!Config.ConfigActiveDevice) { + CurrentPci = CurrentPci->next; + continue; + } + } + + EnableCurrent(); + + if (CurrentPci->active) { + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + } + + /* clear interrupt vectors */ + setup_int_vect(); + + ax = ((CARD16)(CurrentPci->bus) << 8) + | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7); + P_printf("ax: 0x%x\n",ax); + + if (!((mapPciRom(NULL) && chksum((CARD8*)V_BIOS)) + || (CurrentPci->active && copy_vbios()))) { + CurrentPci = CurrentPci->next; + continue; + } + if (!map_vram()) { + CurrentPci = CurrentPci->next; + continue; + } + if (Config.SaveBios) save_bios_to_file(); + printf("initializing PCI bus: %i dev: %i func: %i\n",CurrentPci->bus, + CurrentPci->dev,CurrentPci->func); + bootBIOS(ax); + unmap_vram(); + + CurrentPci = CurrentPci->next; + } + + /* We have an ISA device - configure if requested */ + if (!Active_is_Pci && Config.ConfigActiveDevice) { + pciVideoDisable(); + + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + + setup_int_vect(); + if (copy_vbios()) { + + if (Config.SaveBios) save_bios_to_file(); + if (map_vram()) { + printf("initializing ISA\n"); + bootBIOS(0); + } + } + + unmap_vram(); + sleep(1); + } + + pciVideoRestore(); + + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + } + + close_console(Console); +#ifdef DELETE + iopl(0); + unmap(); + + printf("done !\n"); +#endif + if (Config.IoStatistics) + io_statistics(); +#ifdef DELETE + exit(0); +#endif +} + +int +map(void) +{ + void* mem; + + mem = mmap(0, (size_t)SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_PRIVATE | MAP_ANON, + -1, 0 ); + if (mem != 0) { + perror("anonymous map"); + return (0); + } + memset(mem,0,SIZE); + + loadCodeToMem((unsigned char *) BIOS_START, code); + return (1); +} + +static void +unmap(void) +{ + munmap(0,SIZE); +} + +static void +bootBIOS(CARD16 ax) +{ + i86biosRegs bRegs; +#ifdef V86BIOS_DEBUG + printf("starting BIOS\n"); +#endif + setup_bios_regs(&bRegs, ax); + do_x86(BIOS_START,&bRegs); +#ifdef V86BIOS_DEBUG + printf("done\n"); +#endif +} + +static int +map_vram(void) +{ + int mem_fd; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return 0; + } + +#ifndef __alpha__ + if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, + mem_fd, VRAM_START) == (void *) -1) +#else + if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */ + if (!_bus_base_sparse()) sparse_shift = 0; + if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift), + PROT_READ | PROT_WRITE, + MAP_SHARED, + mem_fd, (VRAM_START << sparse_shift) + | _bus_base_sparse())) == (void *) -1) +#endif + { + perror("mmap error in map_hardware_ram"); + close(mem_fd); + return (0); + } + vram_mapped = 1; + close(mem_fd); + return (1); +} + +static void +unmap_vram(void) +{ + if (!vram_mapped) return; + + munmap((void*)VRAM_START,VRAM_SIZE); + vram_mapped = 0; +} + +static int +copy_vbios(void) +{ + int mem_fd; + unsigned char *tmp; + int size; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) V_BIOS, SEEK_SET) != (off_t) V_BIOS) { + fprintf(stderr,"Cannot lseek\n"); + goto Error; + } + tmp = (unsigned char *)malloc(3); + if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + if (lseek(mem_fd,(off_t) V_BIOS,SEEK_SET) != (off_t) V_BIOS) + goto Error; + + if (*tmp != 0x55 || *(tmp+1) != 0xAA ) { +#ifdef DEBUG + dprint((unsigned long)tmp,0x100); +#endif + fprintf(stderr,"No bios found at: 0x%x\n",V_BIOS); + goto Error; + } + size = *(tmp+2) * 512; + + if (read(mem_fd, (char *)V_BIOS, (size_t) size) != (size_t) size) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + free(tmp); + close(mem_fd); + if (!chksum((CARD8)V_BIOS)) + return (0); + + return (1); + +Error: + perror("v_bios"); + close(mem_fd); + return (0); +} + +static int +copy_sys_bios(void) +{ +#define SYS_BIOS 0xF0000 + int mem_fd; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS) + goto Error; + if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF) + goto Error; + + close(mem_fd); + return (1); + +Error: + perror("sys_bios"); + close(mem_fd); + return (0); +} + +void +loadCodeToMem(unsigned char *ptr, CARD8 code[]) +{ + int i; + CARD8 val; + + for ( i=0;;i++) { + val = code[i]; + *ptr++ = val; + if (val == 0xf4) break; + } + return; +} + +void +dprint(unsigned long start, unsigned long size) +{ + int i,j; + char *c = (char *)start; + + for (j = 0; j < (size >> 4); j++) { + char *d = c; + printf("\n0x%lx: ",(unsigned long)c); + for (i = 0; i<16; i++) + printf("%2.2x ",(unsigned char) (*(c++))); + c = d; + for (i = 0; i<16; i++) { + printf("%c",((((CARD8)(*c)) > 32) && (((CARD8)(*c)) < 128)) ? + (unsigned char) (*(c)): '.'); + c++; + } + } + printf("\n"); +} + +static void +save_bios_to_file(void) +{ + static int num = 0; + int size, count; + char file_name[256]; + int fd; + + sprintf(file_name,"bios_%i.fil",num); + if ((fd = open(file_name,O_WRONLY | O_CREAT | O_TRUNC,00644)) == -1) + return; + size = (*(unsigned char*)(V_BIOS + 2)) * 512; +#ifdef V86BIOS_DEBUG + dprint(V_BIOS,20); +#endif + if ((count = write(fd,(void *)(V_BIOS),size)) != size) + fprintf(stderr,"only saved %i of %i bytes\n",size,count); + num++; +} + +static void +sig_handler(int unused) +{ + fflush(stdout); + fflush(stderr); + + /* put system back in a save state */ + unmap_vram(); + pciVideoRestore(); + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + + close_console(Console); + iopl(0); + unmap(); + + exit(1); +} + +/* + * For initialization we just pass ax to the BIOS. + * PCI BIOSes need this. All other register are set 0. + */ +static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax) +{ + regs->ax = ax; + regs->bx = 0; + regs->cx = 0; + regs->dx = 0; + regs->es = 0; + regs->di = 0; +} + +/* + * here we are really paranoid about faking a "real" + * BIOS. Most of this information was pulled from + * dosem. + */ +static void +setup_int_vect(void) +{ + const CARD16 cs = 0x0000; + const CARD16 ip = 0x0; + int i; + + /* let the int vects point to the SYS_BIOS seg */ + for (i=0; i<0x80; i++) { + ((CARD16*)0)[i<<1] = ip; + ((CARD16*)0)[(i<<1)+1] = cs; + } + /* video interrupts default location */ + ((CARD16*)0)[(0x42<<1)+1] = 0xf000; + ((CARD16*)0)[0x42<<1] = 0xf065; + ((CARD16*)0)[(0x10<<1)+1] = 0xf000; + ((CARD16*)0)[0x10<<1] = 0xf065; + /* video param table default location (int 1d) */ + ((CARD16*)0)[(0x1d<<1)+1] = 0xf000; + ((CARD16*)0)[0x1d<<1] = 0xf0A4; + /* font tables default location (int 1F) */ + ((CARD16*)0)[(0x1f<<1)+1] = 0xf000; + ((CARD16*)0)[0x1f<<1] = 0xfa6e; + + /* int 11 default location */ + ((CARD16*)0)[(0x11<1)+1] = 0xf000; + ((CARD16*)0)[0x11<<1] = 0xf84d; + /* int 12 default location */ + ((CARD16*)0)[(0x12<<1)+1] = 0xf000; + ((CARD16*)0)[0x12<<1] = 0xf841; + /* int 15 default location */ + ((CARD16*)0)[(0x15<<1)+1] = 0xf000; + ((CARD16*)0)[0x15<<1] = 0xf859; + /* int 1A default location */ + ((CARD16*)0)[(0x1a<<1)+1] = 0xf000; + ((CARD16*)0)[0x1a<<1] = 0xff6e; + /* int 05 default location */ + ((CARD16*)0)[(0x05<<1)+1] = 0xf000; + ((CARD16*)0)[0x05<<1] = 0xff54; + /* int 08 default location */ + ((CARD16*)0)[(0x8<<1)+1] = 0xf000; + ((CARD16*)0)[0x8<<1] = 0xfea5; + /* int 13 default location (fdd) */ + ((CARD16*)0)[(0x13<<1)+1] = 0xf000; + ((CARD16*)0)[0x13<<1] = 0xec59; + /* int 0E default location */ + ((CARD16*)0)[(0xe<<1)+1] = 0xf000; + ((CARD16*)0)[0xe<<1] = 0xef57; + /* int 17 default location */ + ((CARD16*)0)[(0x17<<1)+1] = 0xf000; + ((CARD16*)0)[0x17<<1] = 0xefd2; + /* fdd table default location (int 1e) */ + ((CARD16*)0)[(0x1e<<1)+1] = 0xf000; + ((CARD16*)0)[0x1e<<1] = 0xefc7; +} + +static int +setup_system_bios(void) +{ + char *date = "06/01/99"; + char *eisa_ident = "PCI/ISA"; + +#if MAP_SYS_BIOS + if (!copy_sys_bios()) return 0; + return 1; +#endif +/* memset((void *)0xF0000,0xf4,0xfff7); */ + + /* + * we trap the "industry standard entry points" to the BIOS + * and all other locations by filling them with "hlt" + * TODO: implement hlt-handler for these + */ + memset((void *)0xF0000,0xf4,0x10000); + + /* + * TODO: we should copy the fdd table (0xfec59-0xfec5b) + * the video parameter table (0xf0ac-0xf0fb) + * and the font tables (0xfa6e-0xfe6d) + * from the original bios here + */ + + /* set bios date */ + strcpy((char *)0xFFFF5,date); + /* set up eisa ident string */ + strcpy((char *)0xFFFD9,eisa_ident); + /* write system model id for IBM-AT */ + ((char *)0)[0xFFFFE] = 0xfc; + + return 1; +} + +static int +chksum(CARD8 *start) +{ + CARD16 size; + CARD8 val = 0; + int i; + + size = *(start+2) * 512; + for (i = 0; i= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + shift = (addr & 0x3) * 8; + result = *(vuip) ((unsigned long)vram_map + (addr << sparse_shift)); + result >>= shift; + return 0xffUL & result; + } else +#endif + return rdb(addr); +} + +CARD16 +mem_rw(CARD32 addr) +{ + unsigned long result, shift; +#if 1 + if (addr >= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + shift = (addr & 0x2) * 8; + result = *(vuip)((unsigned long)vram_map+(addr<>= shift; + return 0xffffUL & result; + } else +#endif + return rdw(addr); +} + +CARD32 +mem_rl(CARD32 addr) +{ + unsigned long result; +#if 1 + if (addr >= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + result = *(vuip)((unsigned long)vram_map+(addr<= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + *(vuip) ((unsigned long)vram_map + (addr << sparse_shift)) = b * 0x01010101; + mem_barrier(); + } else +#endif + wrb(addr,val); +} + +void +mem_ww(CARD32 addr, CARD16 val) +{ + unsigned int w = val & 0xffffU; +#if 1 + if (addr >= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + *(vuip)((unsigned long)vram_map+(addr<= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + *(vuip)((unsigned long)vram_map+(addr< +#include +#include "v86bios.h" +#include "pci.h" + +#define YYSTYPE unsigned long + +#define MAX_VAR 0x20 + + CARD32 var[MAX_VAR]; + CARD32 var_mem; + + +i86biosRegs regs = { 00 }; + +enum mem_type { BYTE, WORD, LONG, STRING }; +union mem_val { + CARD32 integer; + char *ptr; +} rec; + +struct mem { + enum mem_type type; + union mem_val val; + struct mem *next; +}; + + +struct device Device = {FALSE,NONE,{0}}; + +extern void yyerror(char *s); +extern int yylex( void ); + +static void boot(void); +static void dump_mem(CARD32 addr, int len); +static void exec_int(int num); +static void *add_to_list(enum mem_type type, union mem_val *rec, void *next); +static void do_list(struct mem *list, memType addr); +static char * normalize_string(char *ptr); +%} + +%token TOK_NUM +%token TOK_REG_AX +%token TOK_REG_BX +%token TOK_REG_CX +%token TOK_REG_DX +%token TOK_REG_DI +%token TOK_REG_SI +%token TOK_SEG_DS +%token TOK_SEG_ES +%token TOK_SEP +%token TOK_VAR +%token TOK_VAR_MEM +%token TOK_COMMAND_BOOT +%token TOK_COMMAND_EXEC +%token TOK_SELECT +%token TOK_STRING +%token TOK_MODIFIER_BYTE +%token TOK_MODIFIER_WORD +%token TOK_MODIFIER_LONG +%token TOK_MODIFIER_MEMSET +%token TOK_COMMAND_MEMSET +%token TOK_COMMAND_MEMDUMP +%token TOK_COMMAND_QUIT +%token TOK_ERROR +%token TOK_END +%token TOK_ISA +%token TOK_PCI +%token TOK_BYTE +%token TOK_WORD +%token TOK_LONG +%token TOK_PRINT_PORT +%token TOK_IOSTAT +%token TOK_PRINT_IRQ +%token TOK_PPCI +%token TOK_PIP +%token TOK_TRACE +%token TOK_ON +%token TOK_OFF +%token TOK_VERBOSE +%token TOK_LOG +%token TOK_LOGOFF +%token TOK_CLSTAT +%token TOK_STDOUT +%token TOK_HLT +%token TOK_DEL +%token TOK_IOPERM +%token TOK_DUMP_PCI +%token TOK_BOOT_BIOS +%% +input: | input line +line: end | com_reg | com_var | com_select + | com_boot | com_memset | com_memdump | com_quit + | com_exec | hlp | config | verbose | logging | print | clstat + | com_hlt | ioperm | list_pci | boot_bios + | error end { printf("unknown command\n"); } +; +end: TOK_END +; +com_reg: reg_off val end { *(CARD16*)$1 = $2 & 0xffff; } + | reg_seg TOK_SEP reg_off val end { + *(CARD16*)$1 = ($4 & 0xf0000) >> 4; + *(CARD16*)$3 = ($4 & 0x0ffff); + } + | reg_off '?' end { printf("0x%x\n",*(CARD16*)$1);} + | reg_seg TOK_SEP reg_off '?' end + { printf("0x%x:0x%x\n",*(CARD16*)$1, + *(CARD16*)$3); } +; +register_read: reg_seg TOK_SEP reg_off { $$ = (((*(CARD16*)$1) << 4) + | ((*(CARD16*)$3) & 0xffff)); + } + | reg_off { $$ = ((*(CARD16*)$1) & 0xffff); } +; +reg_off: TOK_REG_AX { $$ = (unsigned long)&(regs.ax); } + | TOK_REG_BX { $$ = (unsigned long)&(regs.bx); } + | TOK_REG_CX { $$ = (unsigned long)&(regs.cx); } + | TOK_REG_DX { $$ = (unsigned long)&(regs.dx); } + | TOK_REG_DI { $$ = (unsigned long)&(regs.di); } + | TOK_REG_SI { $$ = (unsigned long)&(regs.si); } +; +reg_seg: TOK_SEG_DS { $$ = (unsigned long)&(regs.ds); } + | TOK_SEG_ES { $$ = (unsigned long)&(regs.es); } +; +com_var: TOK_VAR_MEM '?' end { printf("var mem: 0x%x\n",var_mem); } + | TOK_VAR '?' end { if ($1 < MAX_VAR) + printf("var[%i]: 0x%x\n",(int)$1,var[$1]); + else + printf("var index %i out of range\n",(int)$1); } + | TOK_VAR_MEM val end { var_mem = $2; } + | TOK_VAR val end { if ($1 <= MAX_VAR) + var[$1] = $2; + else + printf("var index %i out of range\n",(int)$1); } + | TOK_VAR error end { printf("$i val\n"); } + | TOK_VAR_MEM error end { printf("$i val\n"); } +; +com_boot: TOK_COMMAND_BOOT end { boot(); } + TOK_COMMAND_BOOT error end { boot(); } +; +com_select: TOK_SELECT TOK_ISA end { Device.booted = FALSE; + Device.type = ISA; + CurrentPci = NULL; } + | TOK_SELECT TOK_PCI val TOK_SEP val TOK_SEP val end + { Device.booted = FALSE; + Device.type = PCI; + Device.loc.pci.bus = $3; + Device.loc.pci.dev = $5; + Device.loc.pci.func = $7; } + | TOK_SELECT '?' end + { switch (Device.type) { + case ISA: + printf("isa\n"); + break; + case PCI: + printf("pci: %x:%x:%x\n",Device.loc.pci.bus, + Device.loc.pci.dev, + Device.loc.pci.func); + break; + default: + printf("no device selected\n"); + break; + } + } + | TOK_SELECT error end { printf("select ? | isa " + "| pci:bus:dev:func\n"); } +; +com_quit: TOK_COMMAND_QUIT end { return 0; } + | TOK_COMMAND_QUIT error end { logoff(); return 0; } +; +com_exec: TOK_COMMAND_EXEC end { exec_int(0x10); } + | TOK_COMMAND_EXEC val end { exec_int($2); } + | TOK_COMMAND_EXEC error end { exec_int(0x10); } +; +com_memdump: TOK_COMMAND_MEMDUMP val val end { dump_mem($2,$3); } + | TOK_COMMAND_MEMDUMP error end { printf("memdump start len\n"); } + + +; +com_memset: TOK_COMMAND_MEMSET val list end { do_list((struct mem*)$3,$2);} + | TOK_COMMAND_MEMSET error end { printf("setmem addr [byte val] " + "[word val] [long val] " + "[\"string\"]\n"); } +; +list: { $$ = 0; } + | TOK_BYTE val list { rec.integer = $2; + $$ = (unsigned long)add_to_list(BYTE,&rec,(void*)$3); } + | TOK_WORD val list { rec.integer = $2; + $$ = (unsigned long) add_to_list(WORD,&rec,(void*)$3); } + | TOK_LONG val list { rec.integer = $2; + $$ = (unsigned long) add_to_list(LONG,&rec,(void*)$3); } + | TOK_STRING list { rec.ptr = (void*)$1; + $$ = (unsigned long) add_to_list(STRING,&rec,(void*)$2); } +; +val: TOK_VAR { if ($1 > MAX_VAR) { + printf("variable index out of range\n"); + $$=0; + } else + $$ = var[$1]; } + | TOK_NUM { $$ = $1; } + | register_read +; +bool: TOK_ON { $$ = 1; } + | TOK_OFF { $$ = 0; } +; +config: TOK_PRINT_PORT bool end { Config.PrintPort = $2; } + | TOK_PRINT_PORT '?' end { printf("print port %s\n", + Config.PrintPort?"on":"off"); } + | TOK_PRINT_PORT error end { printf("pport on | off | ?\n") } + | TOK_PRINT_IRQ bool end { Config.PrintIrq = $2; } + | TOK_PRINT_IRQ '?' end { printf("print irq %s\n", + Config.PrintIrq?"on":"off"); } + | TOK_PRINT_IRQ error end { printf("pirq on | off | ?\n") } + | TOK_PPCI bool end { Config.PrintPci = $2; } + | TOK_PPCI '?' end { printf("print PCI %s\n", + Config.PrintPci?"on":"off"); } + | TOK_PPCI error end { printf("ppci on | off | ?\n") } + | TOK_PIP bool end { Config.PrintIp = $2; } + | TOK_PIP '?' end { printf("printip %s\n", + Config.PrintIp?"on":"off"); } + | TOK_PIP error end { printf("pip on | off | ?\n") } + | TOK_IOSTAT bool end { Config.IoStatistics = $2; } + | TOK_IOSTAT '?' end { printf("io statistics %s\n", + Config.IoStatistics?"on":"off"); } + | TOK_IOSTAT error end { printf("iostat on | off | ?\n") } + | TOK_TRACE bool end { Config.Trace = $2; } + | TOK_TRACE '?' end { printf("trace %s\n", + Config.Trace ?"on":"off"); } + | TOK_TRACE error end { printf("trace on | off | ?\n") } +; +verbose: TOK_VERBOSE val end { Config.Verbose = $2; } + | TOK_VERBOSE '?' end { printf("verbose: %i\n", + Config.Verbose); } + | TOK_VERBOSE error end { printf("verbose val | ?\n"); } +; +logging: TOK_LOG TOK_STRING end { logon(normalize_string((char*)$2)); } + | TOK_LOG '?' end { if (logging) printf("logfile: %s\n", + logfile); + else printf("no logging\n?"); } + | TOK_LOG TOK_OFF end { logoff(); } + | TOK_LOG error end { printf("log \"\" | ? |" + " off\n"); } +; +clstat: TOK_CLSTAT end { clear_stat(); } + | TOK_CLSTAT error end { printf("clstat\n"); } +; +print: TOK_STDOUT bool end { nostdout = !$2; } + | TOK_STDOUT '?' end { printf("print %s\n",nostdout ? + "no":"yes"); } + | TOK_STDOUT error end { printf("print on | off\n"); } +; +com_hlt: TOK_HLT val end { add_hlt($2); } + | TOK_HLT TOK_DEL val end { del_hlt($3); } + | TOK_HLT TOK_DEL end { del_hlt(21); } + | TOK_HLT '?' end { list_hlt(); } + | TOK_HLT error end { printf( + "hlt val | del [val] | ?\n"); } +; +ioperm: TOK_IOPERM val val val end { int i,max; + if ($2 >= 0) { + max = $2 + $3 - 1; + if (max > IOPERM_BITS) + max = IOPERM_BITS; + for (i = $2;i <= max; i++) + ioperm_list[i] + = $4>0 ? 1 : 0; + } + } + | TOK_IOPERM '?' end { int i,start; + for (i=0; i <= IOPERM_BITS; i++) { + if (ioperm_list[i]) { + start = i; + for (; i <= IOPERM_BITS; i++) + if (!ioperm_list[i]) { + printf("ioperm on in " + "0x%x+0x%x\n", start,i-start); + break; + } + } + } + } + | TOK_IOPERM error end { printf("ioperm start len val\n"); } +; +list_pci: TOK_DUMP_PCI end { list_pci(); } + | TOK_DUMP_PCI error end { list_pci(); } +; +boot_bios: TOK_BOOT_BIOS '?' end { if (!BootBios) printf("No Boot BIOS\n"); + else printf("BootBIOS from: %i:%i:%i\n", + BootBios->bus, BootBios->dev, + BootBios->func); } + | TOK_BOOT_BIOS error end { printf ("bootbios bus:dev:num\n"); } +; +hlp: '?' { printf("Command list:\n"); + printf(" select isa | pci bus:dev:func\n"); + printf(" boot\n"); + printf(" seg:reg val | reg val \n"); + printf(" $x val | $mem val\n"); + printf(" setmem addr list; addr := val\n"); + printf(" dumpmem addr len; addr,len := val\n"); + printf(" do [val]\n"); + printf(" quit\n"); + printf(" ?\n"); + printf(" seg := ds | es;" + " reg := ax | bx | cx | dx | si \n"); + printf(" val := var | | seg:reg | seg\n"); + printf(" var := $x | $mem; x := 0..20\n"); + printf(" list := byte val | word val | long val " + "| \"string\"\n"); + printf(" pport on | off | ?\n"); + printf(" ppci on | off | ?\n"); + printf(" pirq on | off | ?\n"); + printf(" pip on | off | ?\n"); + printf(" trace on | off | ?\n"); + printf(" iostat on | off | ?\n"); + printf(" verbose val\n"); + printf(" log \"\" | off | ?\n"); + printf(" print on | off\n"); + printf(" hlt val | del [val] | ?\n"); + printf(" clstat\n"); + printf(" lpci\n"); + printf ("bootbios ?\n"); +} +; + +%% + +static void +dump_mem(CARD32 addr, int len) +{ + dprint(addr,len); +} + +static void +exec_int(int num) +{ + if (num == 0x10) { /* video interrupt */ + if (Device.type == NONE) { + CurrentPci = PciList; + while (CurrentPci) { + if (CurrentPci->active) + break; + CurrentPci = CurrentPci->next; + } + if (!CurrentPci) + Device.type = ISA; + else { + Device.type = PCI; + Device.loc.pci.dev = CurrentPci->dev; + Device.loc.pci.bus = CurrentPci->bus; + Device.loc.pci.func = CurrentPci->func; + } + } + if (Device.type != ISA) { + if (!Device.booted) { + if (!CurrentPci || (Device.type == PCI + && (!CurrentPci->active + && (Device.loc.pci.dev != CurrentPci->dev + || Device.loc.pci.bus != CurrentPci->bus + || Device.loc.pci.func != CurrentPci->func)))) { + printf("boot the device fist\n"); + return; + } + } + } else + CurrentPci = NULL; + } else { + Device.booted = FALSE; /* we need this for sanity! */ + } + + runINT(num,®s); +} + +static void +boot(void) +{ + if (Device.type == NONE) { + printf("select a device fist\n"); + return; + } + + call_boot(&Device); +} + +static void * +add_to_list(enum mem_type type, union mem_val *rec, void *next) +{ + struct mem *mem_rec = (struct mem *) malloc(sizeof(mem_rec)); + + mem_rec->type = type; + mem_rec->next = next; + + switch (type) { + case BYTE: + case WORD: + case LONG: + mem_rec->val.integer = rec->integer; + break; + case STRING: + mem_rec->val.ptr = normalize_string(rec->ptr); + break; + } + return mem_rec; +} + +static int +validRange(int addr,int len) +{ + int end = addr + len; + + if (addr < 0x1000 || end > 0xc0000) + return 0; + return 1; +} + +static void +do_list(struct mem *list, memType addr) +{ + struct mem *prev; + int len; + + while (list) { + switch (list->type) { + case BYTE: + if (!validRange(addr,1)) goto error; + *(CARD8*)addr = list->val.integer; + addr =+ 1; + break; + case WORD: + if (!validRange(addr,2)) goto error; + *(CARD16*)addr = list->val.integer; + addr =+ 2; + break; + case LONG: + if (!validRange(addr,4)) goto error; + *(CARD32*)addr = list->val.integer; + addr =+ 4; + break; + case STRING: + len = strlen((char*)list->val.ptr); + if (!validRange(addr,len)) goto error; + memcpy((CARD8*)addr,(void*)list->val.ptr,len); + addr =+ len; + free(list->val.ptr); + break; + } + prev = list; + list = list->next; + free(prev); + continue; + error: + printf("address out of range\n"); + while (list) { + prev = list; + list = list->next; + free(prev); + } + break; + } +} + +static char * +normalize_string(char *ptr) +{ + int i = 0, j = 0, c = 0, esc= 0; + int size; + char *mem_ptr; + + size = strlen(ptr); + mem_ptr = malloc(size); + while (1) { + switch (*(ptr + i)) { + case '\\': + if (esc) { + *(mem_ptr + j++) = *(ptr + i); + esc = 0; + } else + esc = 1; + break; + case '\"': + if (esc) { + *(mem_ptr + j++) = *(ptr + i); + esc = 0; + } else + c++; + break; + default: + *(mem_ptr + j++) = *(ptr + i); + break; + } + if (c > 1) { + *(mem_ptr + j) = '\0'; + break; + } + i++; + } + return mem_ptr; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/pci.c b/board/MAI/bios_emulator/scitech/src/v86bios/pci.c new file mode 100644 index 0000000..b58a571 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/pci.c @@ -0,0 +1,902 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "debug.h" +#include +#include +#include +#include +#include +#include +#include +#include +#if defined (__alpha__) || defined (__ia64__) +#include +#endif +#include "AsmMacros.h" + +#include "pci.h" + +/* + * I'm rather simple mindend - therefore I do a poor man's + * pci scan without all the fancy stuff that is done in + * scanpci. However that's all we need. + */ + +PciStructPtr PciStruct = NULL; +PciBusPtr PciBuses = NULL; +PciStructPtr CurrentPci = NULL; +PciStructPtr PciList = NULL; +PciStructPtr BootBios = NULL; +int pciMaxBus = 0; + +static CARD32 PciCfg1Addr; + +static void readConfigSpaceCfg1(CARD32 bus, CARD32 dev, CARD32 func, + CARD32 *reg); +static int checkSlotCfg1(CARD32 bus, CARD32 dev, CARD32 func); +static int checkSlotCfg2(CARD32 bus, int dev); +static void readConfigSpaceCfg2(CARD32 bus, int dev, CARD32 *reg); +static CARD8 interpretConfigSpace(CARD32 *reg, int busidx, + CARD8 dev, CARD8 func); +static CARD32 findBIOSMap(PciStructPtr pciP, CARD32 *biosSize); +static void restoreMem(PciStructPtr pciP); + + +#ifdef __alpha__ +#define PCI_BUS_FROM_TAG(tag) (((tag) & 0x00ff0000) >> 16) +#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00) >> 8) + +#include + +CARD32 +axpPciCfgRead(CARD32 tag) +{ + int bus, dfn; + CARD32 val = 0xffffffff; + + bus = PCI_BUS_FROM_TAG(tag); + dfn = PCI_DFN_FROM_TAG(tag); + + syscall(__NR_pciconfig_read, bus, dfn, tag & 0xff, 4, &val); + return(val); +} + +void +axpPciCfgWrite(CARD32 tag, CARD32 val) +{ + int bus, dfn; + + bus = PCI_BUS_FROM_TAG(tag); + dfn = PCI_DFN_FROM_TAG(tag); + + syscall(__NR_pciconfig_write, bus, dfn, tag & 0xff, 4, &val); +} + +static CARD32 (*readPci)(CARD32 reg) = axpPciCfgRead; +static void (*writePci)(CARD32 reg, CARD32 val) = axpPciCfgWrite; +#else +static CARD32 readPciCfg1(CARD32 reg); +static void writePciCfg1(CARD32 reg, CARD32 val); +static CARD32 readPciCfg2(CARD32 reg); +static void writePciCfg2(CARD32 reg, CARD32 val); + +static CARD32 (*readPci)(CARD32 reg) = readPciCfg1; +static void (*writePci)(CARD32 reg, CARD32 val) = writePciCfg1; +#endif + +#if defined(__alpha__) || defined(__sparc__) +#define PCI_EN 0x00000000 +#else +#define PCI_EN 0x80000000 +#endif + + +static int numbus; +static int hostbridges = 1; +static unsigned long pciMinMemReg = ~0; + + +void +scan_pci(void) +{ + unsigned short configtype; + + CARD32 reg[64]; + int busidx; + CARD8 cardnum; + CARD8 func; + int idx; + + int i; + PciStructPtr pci1; + PciBusPtr pci_b1,pci_b2; + +#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc__) || defined(__ia64__) + configtype = 1; +#else + CARD8 tmp1, tmp2; + CARD32 tmp32_1, tmp32_2; + outb(PCI_MODE2_ENABLE_REG, 0x00); + outb(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = inb(PCI_MODE2_ENABLE_REG); + tmp2 = inb(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + configtype = 2; + readPci = readPciCfg2; + writePci = writePciCfg2; + P_printf("PCI says configuration type 2\n"); + } else { + tmp32_1 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmp32_2 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, tmp32_1); + if (tmp32_2 == PCI_EN) { + configtype = 1; + P_printf("PCI says configuration type 1\n"); + } else { + P_printf("No PCI !\n"); + return; + } + } +#endif + + if (configtype == 1) { + P_printf("PCI probing configuration type 1\n"); + busidx = 0; + numbus = 1; + idx = 0; + do { + P_printf("\nProbing for devices on PCI bus %d:\n", busidx); + for (cardnum = 0; cardnum < MAX_DEV_PER_VENDOR_CFG1; cardnum++) { + func = 0; + do { + /* loop over the different functions, if present */ + if (!checkSlotCfg1(busidx,cardnum,func)) + break; + readConfigSpaceCfg1(busidx,cardnum,func,reg); + + func = interpretConfigSpace(reg,busidx, + cardnum,func); + + if (idx++ > MAX_PCI_DEVICES) + continue; + } while (func < 8); + } + } while (++busidx < PCI_MAXBUS); +#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc__) || defined(__ia64__) + /* don't use outl() ;-) */ +#else + outl(PCI_MODE1_ADDRESS_REG, 0); +#endif + } else { + int slot; + + P_printf("PCI probing configuration type 2\n"); + busidx = 0; + numbus = 1; + idx = 0; + do { + for (slot=0xc0; slot<0xd0; i++) { + if (!checkSlotCfg2(busidx,slot)) + break; + readConfigSpaceCfg2(busidx,slot,reg); + + interpretConfigSpace(reg,busidx, + slot,0); + if (idx++ > MAX_PCI_DEVICES) + continue; + } + } while (++busidx < PCI_MAXBUS); + } + + + pciMaxBus = numbus - 1; + P_printf("Number of buses in system: %i\n",pciMaxBus + 1); + P_printf("Min PCI mem address: 0x%lx\n",pciMinMemReg); + + /* link buses */ + pci_b1 = PciBuses; + while (pci_b1) { + pci_b2 = PciBuses; + pci_b1->pBus = NULL; + while (pci_b2) { + if (pci_b1->primary == pci_b2->secondary) + pci_b1->pBus = pci_b2; + pci_b2 = pci_b2->next; + } + pci_b1 = pci_b1->next; + } + pci1 = PciStruct; + while (pci1) { + pci_b2 = PciBuses; + pci1->pBus = NULL; + while (pci_b2) { + if (pci1->bus == pci_b2->secondary) + pci1->pBus = pci_b2; + pci_b2 = pci_b2->next; + } + pci1 = pci1->next; + } + if (RESORT) { + PciStructPtr tmp = PciStruct, tmp1; + PciStruct = NULL; + while (tmp) { + tmp1 = tmp->next; + tmp->next = PciStruct; + PciStruct = tmp; + tmp = tmp1; + } + } + PciList = CurrentPci = PciStruct; +} + +#ifndef __alpha__ +static CARD32 +readPciCfg1(CARD32 reg) +{ + CARD32 val; + + outl(PCI_MODE1_ADDRESS_REG, reg); + val = inl(PCI_MODE1_DATA_REG); + outl(PCI_MODE1_ADDRESS_REG, 0); + P_printf("reading: 0x%x from 0x%x\n",val,reg); + return val; +} + +static void +writePciCfg1(CARD32 reg, CARD32 val) +{ + P_printf("writing: 0x%x to 0x%x\n",val,reg); + outl(PCI_MODE1_ADDRESS_REG, reg); + outl(PCI_MODE1_DATA_REG,val); + outl(PCI_MODE1_ADDRESS_REG, 0); +} + +static CARD32 +readPciCfg2(CARD32 reg) +{ + CARD32 val; + CARD8 bus = (reg >> 16) & 0xff; + CARD8 dev = (reg >> 11) & 0x1f; + CARD8 num = reg & 0xff; + + outb(PCI_MODE2_ENABLE_REG, 0xF1); + outb(PCI_MODE2_FORWARD_REG, bus); + val = inl((dev << 8) + num); + outb(PCI_MODE2_ENABLE_REG, 0x00); + P_printf("reading: 0x%x from 0x%x\n",val,reg); + return val; +} + +static void +writePciCfg2(CARD32 reg, CARD32 val) +{ + CARD8 bus = (reg >> 16) & 0xff; + CARD8 dev = (reg >> 11) & 0x1f; + CARD8 num = reg & 0xff; + + P_printf("writing: 0x%x to 0x%x\n",val,reg); + outb(PCI_MODE2_ENABLE_REG, 0xF1); + outb(PCI_MODE2_FORWARD_REG, bus); + outl((dev << 8) + num,val); + outb(PCI_MODE2_ENABLE_REG, 0x00); +} +#endif + +void +pciVideoDisable(void) +{ + /* disable VGA routing on bridges */ + PciBusPtr pbp = PciBuses; + PciStructPtr pcp = PciStruct; + + while (pbp) { + writePci(pbp->Slot.l | 0x3c, pbp->bctl & ~(CARD32)(8<<16)); + pbp = pbp->next; + } + /* disable display devices */ + while (pcp) { + writePci(pcp->Slot.l | 0x04, pcp->cmd_st & ~(CARD32)3); + writePci(pcp->Slot.l | 0x30, pcp->RomBase & ~(CARD32)1); + pcp = pcp->next; + } +} + +void +pciVideoRestore(void) +{ + /* disable VGA routing on bridges */ + PciBusPtr pbp = PciBuses; + PciStructPtr pcp = PciStruct; + + while (pbp) { + writePci(pbp->Slot.l | 0x3c, pbp->bctl); + pbp = pbp->next; + } + /* disable display devices */ + while (pcp) { + writePci(pcp->Slot.l | 0x04, pcp->cmd_st); + writePci(pcp->Slot.l | 0x30, pcp->RomBase); + pcp = pcp->next; + } +} + +void +EnableCurrent() +{ + PciBusPtr pbp; + PciStructPtr pcp = CurrentPci; + + pciVideoDisable(); + + pbp = pcp->pBus; + while (pbp) { /* enable bridges */ + writePci(pbp->Slot.l | 0x3c, pbp->bctl | (CARD32)(8<<16)); + pbp = pbp->pBus; + } + writePci(pcp->Slot.l | 0x04, pcp->cmd_st | (CARD32)3); + writePci(pcp->Slot.l | 0x30, pcp->RomBase | (CARD32)1); +} + +CARD8 +PciRead8(int offset, CARD32 Slot) +{ + int shift = offset & 0x3; + offset = offset & 0xFC; + return ((readPci(Slot | offset) >> (shift << 3)) & 0xff); +} + +CARD16 +PciRead16(int offset, CARD32 Slot) +{ + int shift = offset & 0x2; + offset = offset & 0xFC; + return ((readPci(Slot | offset) >> (shift << 3)) & 0xffff); +} + +CARD32 +PciRead32(int offset, CARD32 Slot) +{ + offset = offset & 0xFC; + return (readPci(Slot | offset)); +} + +void +PciWrite8(int offset, CARD8 byte, CARD32 Slot) +{ + CARD32 val; + int shift = offset & 0x3; + offset = offset & 0xFC; + val = readPci(Slot | offset); + val &= ~(CARD32)(0xff << (shift << 3)); + val |= byte << (shift << 3); + writePci(Slot | offset, val); +} + +void +PciWrite16(int offset, CARD16 word, CARD32 Slot) +{ + CARD32 val; + int shift = offset & 0x2; + offset = offset & 0xFC; + val = readPci(Slot | offset); + val &= ~(CARD32)(0xffff << (shift << 3)); + val |= word << (shift << 3); + writePci(Slot | offset, val); +} + +void +PciWrite32(int offset, CARD32 lg, CARD32 Slot) +{ + offset = offset & 0xFC; + writePci(Slot | offset, lg); +} + +int +mapPciRom(PciStructPtr pciP) +{ + unsigned long RomBase = 0; + int mem_fd; + unsigned char *mem, *ptr; + unsigned char *scratch = NULL; + int length = 0; + CARD32 biosSize = 0x1000000; + CARD32 enablePci; + + if (!pciP) + pciP = CurrentPci; + + if (FIX_ROM) { + RomBase = findBIOSMap(pciP, &biosSize); + if (!RomBase) { + fprintf(stderr,"Cannot remap BIOS of %i:%i:%i " + "- trying preset address\n",pciP->bus,pciP->dev, + pciP->func); + RomBase = pciP->RomBase & ~(CARD32)0xFF; + } + } else { + RomBase = pciP->RomBase & ~(CARD32)0xFF; + if (~RomBase + 1 < biosSize || !RomBase) + RomBase = findBIOSMap(pciP, &biosSize); + } + + P_printf("RomBase: 0x%lx\n",RomBase); + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + restoreMem(pciP); + return (0); + } + + PciWrite32(0x30,RomBase | 1,pciP->Slot.l); + +#ifdef __alpha__ + mem = ptr = (unsigned char *)mmap(0, biosSize, PROT_READ, + MAP_SHARED, mem_fd, RomBase | _bus_base()); +#else + mem = ptr = (unsigned char *)mmap(0, biosSize, PROT_READ, + MAP_SHARED, mem_fd, RomBase); +#endif + if (pciP != CurrentPci) { + enablePci = PciRead32(0x4,pciP->Slot.l); + PciWrite32(0x4,enablePci | 0x2,pciP->Slot.l); + } + +#ifdef PRINT_PCI + dprint((unsigned long)ptr,0x30); +#endif + while ( *ptr == 0x55 && *(ptr+1) == 0xAA) { + unsigned short data_off = *(ptr+0x18) | (*(ptr+0x19)<< 8); + unsigned char *data = ptr + data_off; + unsigned char type; + int i; + + if (*data!='P' || *(data+1)!='C' || *(data+2)!='I' || *(data+3)!='R') { + break; + } + type = *(data + 0x14); + P_printf("data segment in BIOS: 0x%x, type: 0x%x ",data_off,type); + + if (type != 0) { /* not PC-AT image: find next one */ + unsigned int image_length; + unsigned char indicator = *(data + 0x15); + if (indicator & 0x80) /* last image */ + break; + image_length = (*(data + 0x10) + | (*(data + 0x11) << 8)) << 9; + P_printf("data image length: 0x%x, ind: 0x%x\n", + image_length,indicator); + ptr = ptr + image_length; + continue; + } + /* OK, we have a PC Image */ + length = (*(ptr + 2) << 9); + P_printf("BIOS length: 0x%x\n",length); + scratch = (unsigned char *)malloc(length); + /* don't use memcpy() here: Reading from bus! */ + for (i=0;iSlot.l); + + /* unmap/close/disable PCI bios mem */ + munmap(mem, biosSize); + close(mem_fd); + /* disable and restore mapping */ + writePci(pciP->Slot.l | 0x30, pciP->RomBase & ~(CARD32)1); + + if (scratch && length) { + memcpy((unsigned char *)V_BIOS, scratch, length); + free(scratch); + } + + restoreMem(pciP); + return length; +} + +CARD32 +findPci(CARD16 slotBX) +{ + CARD32 slot = slotBX << 8; + + if (slot == (CurrentPci->Slot.l & ~PCI_EN)) + return (CurrentPci->Slot.l | PCI_EN); + else { +#if !SHOW_ALL_DEV + PciBusPtr pBus = CurrentPci->pBus; + while (pBus) { + /* fprintf(stderr,"slot: 0x%x bridge: 0x%x\n",slot, pBus->Slot.l); */ + if (slot == (pBus->Slot.l & ~PCI_EN)) + return pBus->Slot.l | PCI_EN; + pBus = pBus->next; + } +#else + PciStructPtr pPci = PciStruct; + while (pPci) { + /*fprintf(stderr,"slot: 0x%x bridge: 0x%x\n",slot, pPci->Slot.l); */ + if (slot == (pPci->Slot.l & ~PCI_EN)) + return pPci->Slot.l | PCI_EN; + pPci = pPci->next; + } +#endif + } + return 0; +} + +CARD16 +pciSlotBX(PciStructPtr pPci) +{ + return (CARD16)((pPci->Slot.l >> 8) & 0xFFFF); +} + +PciStructPtr +findPciDevice(CARD16 vendorID, CARD16 deviceID, char n) +{ + PciStructPtr pPci = CurrentPci; + n++; + + while (pPci) { + if ((pPci->VendorID == vendorID) && (pPci->DeviceID == deviceID)) { + if (!(--n)) break; + } + pPci = pPci->next; + } + return pPci; +} + +PciStructPtr +findPciClass(CARD8 intf, CARD8 subClass, CARD16 class, char n) +{ + PciStructPtr pPci = CurrentPci; + n++; + + while (pPci) { + if ((pPci->Interface == intf) && (pPci->SubClass == subClass) + && (pPci->BaseClass == class)) { + if (!(--n)) break; + } + pPci = pPci->next; + } + return pPci; +} + +static void +readConfigSpaceCfg1(CARD32 bus, CARD32 dev, CARD32 func, CARD32 *reg) +{ + CARD32 config_cmd = PCI_EN | (bus<<16) | + (dev<<11) | (func<<8); + int i; + + for (i = 0; i<64;i+=4) { +#ifdef __alpha__ + reg[i] = axpPciCfgRead(config_cmd | i); +#else + outl(PCI_MODE1_ADDRESS_REG, config_cmd | i); + reg[i] = inl(PCI_MODE1_DATA_REG); +#endif + +#ifdef V86BIOS_DEBUG + P_printf("0x%lx\n",reg[i]); +#endif + } +} + +static int +checkSlotCfg1(CARD32 bus, CARD32 dev, CARD32 func) +{ + CARD32 config_cmd = PCI_EN | (bus<<16) | + (dev<<11) | (func<<8); + CARD32 reg; +#ifdef __alpha__ + reg = axpPciCfgRead(config_cmd); +#else + outl(PCI_MODE1_ADDRESS_REG, config_cmd); + reg = inl(PCI_MODE1_DATA_REG); +#endif + if (reg != 0xFFFFFFFF) + return 1; + else + return 0; +} + +static int +checkSlotCfg2(CARD32 bus, int dev) +{ + CARD32 val; + + outb(PCI_MODE2_ENABLE_REG, 0xF1); + outb(PCI_MODE2_FORWARD_REG, bus); + val = inl(dev << 8); + outb(PCI_MODE2_FORWARD_REG, 0x00); + outb(PCI_MODE2_ENABLE_REG, 0x00); + if (val == 0xFFFFFFFF) + return 0; + if (val == 0xF0F0F0F0) + return 0; + return 1; +} + +static void +readConfigSpaceCfg2(CARD32 bus, int dev, CARD32 *reg) +{ + int i; + + outb(PCI_MODE2_ENABLE_REG, 0xF1); + outb(PCI_MODE2_FORWARD_REG, bus); + for (i = 0; i<64;i+=4) { + reg[i] = inl((dev << 8) + i); +#ifdef V86BIOS_DEBUG + P_printf("0x%lx\n",reg[i]); +#endif + } + outb(PCI_MODE2_ENABLE_REG, 0x00); +} + +static CARD8 +interpretConfigSpace(CARD32 *reg, int busidx, CARD8 dev, CARD8 func) +{ + CARD32 config_cmd; + CARD16 vendor, device; + CARD8 baseclass, subclass; + CARD8 primary, secondary; + CARD8 header, interface; + int i; + + config_cmd = PCI_EN | busidx<<16 | + (dev<<11) | (func<<8); + + for (i = 0x10; i < 0x28; i+=4) { + if (IS_MEM32(reg[i])) + if ((reg[i] & 0xFFFFFFF0) < pciMinMemReg) + pciMinMemReg = (reg[i] & 0xFFFFFFF0); +#ifdef __alpha__ + if (IS_MEM64(reg[i])) { + unsigned long addr = reg[i] | + (unsigned long)(reg[i+4]) << 32; + if ((addr & ~0xfL) < pciMinMemReg) + pciMinMemReg = (addr & ~0xfL); + i+=4; + } +#endif + } + vendor = reg[0] & 0xFFFF; + device = reg[0] >> 16; + P_printf("bus: %i card: %i func %i reg0: 0x%x ", busidx,dev,func,reg[0]); + baseclass = reg[8] >> 24; + subclass = (reg[8] >> 16) & 0xFF; + interface = (reg[8] >> 8) & 0xFF; + + header = (reg[0x0c] >> 16) & 0xff; + P_printf("bc 0x%x, sub 0x%x, if 0x%x, hdr 0x%x\n", + baseclass,subclass,interface,header); + if (BRIDGE_CLASS(baseclass)) { + if (BRIDGE_PCI_CLASS(subclass)) { + PciBusPtr pbp = malloc(sizeof(PciBusRec)); + P_printf("Pci-Pci Bridge found; "); + primary = reg[0x18] & 0xFF; + secondary = (reg[0x18] >> 8) & 0xFF; + P_printf("primary: 0x%x secondary: 0x%x\n", + primary,secondary); + pbp->bctl = reg[0x3c]; + pbp->primary = primary; + pbp->secondary = secondary; + pbp->Slot.l = config_cmd; + pbp->next = PciBuses; + PciBuses = pbp; + numbus++; + } else if (BRIDGE_HOST_CLASS(subclass) + && (hostbridges++ > 1)) { + numbus++; + } + } else if (VIDEO_CLASS(baseclass,subclass)) { + PciStructPtr pcp = malloc(sizeof(PciStructRec)); + P_printf("Display adapter found\n"); + pcp->RomBase = reg[0x30]; + pcp->cmd_st = reg[4]; + pcp->active = (reg[4] & 0x03) == 3 ? 1 : 0; + pcp->VendorID = vendor; + pcp->DeviceID = device; + pcp->Interface = interface; + pcp->BaseClass = baseclass; + pcp->SubClass = subclass; + pcp->Slot.l = config_cmd; + pcp->bus = busidx; + pcp->dev = dev; + pcp->func = func; + pcp->next = PciStruct; + PciStruct = pcp; + } + if ((func == 0) + && ((header & PCI_MULTIFUNC_DEV) == 0)) + func = 8; + else + func++; + return func; +} + +static CARD32 remapMEM_val; +static int remapMEM_num; + +static int /* map it on some other video device */ +remapMem(PciStructPtr pciP, int num, CARD32 size) +{ + PciStructPtr pciPtr = PciStruct; + int i; + CARD32 org; + CARD32 val; + CARD32 size_n; + + org = PciRead32(num + 0x10,pciP->Slot.l); + + while (pciPtr) { + for (i = 0; i < 20; i=i+4) { + + val = PciRead32(i + 0x10,pciPtr->Slot.l); + /* don't map it on itself */ + if ((org & 0xfffffff0) == (val & 0xfffffff0)) + continue; + if (val && !(val & 1)) + PciWrite32(i + 0x10,0xffffffff,pciPtr->Slot.l); + else + continue; + size_n = PciRead32(i + 0x10,pciPtr->Slot.l); + PciWrite32(i + 0x10,val,pciPtr->Slot.l); + size_n = ~(CARD32)(size_n & 0xfffffff0) + 1; + + if (size_n >= size) { + PciWrite32(num + 0x10,val,pciP->Slot.l); + return 1; + } + } + pciPtr = pciPtr->next; + } + /* last resort: try to go below lowest PCI mem address */ + val = ((pciMinMemReg & ~(CARD32)(size - 1)) - size); + if (val > 0x7fffffff) { + PciWrite32(num + 0x10,val, pciP->Slot.l); + return 1; + } + + return 0; +} + +static void +restoreMem(PciStructPtr pciP) +{ + if (remapMEM_val == 0) return; + PciWrite32(remapMEM_num + 0x10,remapMEM_val,pciP->Slot.l); + return; +} + +static CARD32 +findBIOSMap(PciStructPtr pciP, CARD32 *biosSize) +{ + PciStructPtr pciPtr = PciStruct; + int i; + CARD32 val; + CARD32 size; + + PciWrite32(0x30,0xffffffff,pciP->Slot.l); + *biosSize = PciRead32(0x30,pciP->Slot.l); + P_printf("bios size: 0x%x\n",*biosSize); + PciWrite32(0x30,pciP->RomBase,pciP->Slot.l); + *biosSize = ~(*biosSize & 0xFFFFFF00) + 1; + P_printf("bios size masked: 0x%x\n",*biosSize); + if (*biosSize > (1024 * 1024 * 16)) { + *biosSize = 1024 * 1024 * 16; + P_printf("fixing broken BIOS size: 0x%x\n",*biosSize); + } + while (pciPtr) { + if (pciPtr->bus != pciP->bus) { + pciPtr = pciPtr->next; + continue; + } + for (i = 0; i < 20; i=i+4) { + + val = PciRead32(i + 0x10,pciPtr->Slot.l); + if (!(val & 1)) + + PciWrite32(i + 0x10,0xffffffff,pciPtr->Slot.l); + else + continue; + size = PciRead32(i + 0x10,pciPtr->Slot.l); + PciWrite32(i + 0x10,val,pciPtr->Slot.l); + size = ~(CARD32)(size & 0xFFFFFFF0) + 1; +#ifdef V86_BIOS_DEBUG + P_printf("size: 0x%x\n",size); +#endif + if (size >= *biosSize) { + if (pciP == pciPtr) { /* if same device remap ram*/ + if (!(remapMem(pciP,i,size))) + continue; + remapMEM_val = val; + remapMEM_num = i; + } else { + remapMEM_val = 0; + } + return val & 0xFFFFFF00; + } + } + pciPtr = pciPtr->next; + } + remapMEM_val = 0; + /* very last resort */ + if (pciP->bus == 0 && (pciMinMemReg > *biosSize)) + return (pciMinMemReg - size) & ~(size - 1); + + return 0; +} + +int +cfg1out(CARD16 addr, CARD32 val) +{ + if (addr == 0xCF8) { + PciCfg1Addr = val; + return 1; + } else if (addr == 0xCFC) { + writePci(PciCfg1Addr, val); + return 1; + } + return 0; +} + +int +cfg1in(CARD16 addr, CARD32 *val) +{ + if (addr == 0xCF8) { + *val = PciCfg1Addr; + return 1; + } else if (addr == 0xCFC) { + *val = readPci(PciCfg1Addr); + return 1; + } + return 0; +} + +void +list_pci(void) +{ + PciStructPtr pci = PciList; + + while (pci) { + printf("[0x%x:0x%x:0x%x] vendor: 0x%4.4x dev: 0x%4.4x class: 0x%4.4x" + " subclass: 0x%4.4x\n",pci->bus,pci->dev,pci->func, + pci->VendorID,pci->DeviceID,pci->BaseClass,pci->SubClass); + pci = pci->next; + } +} + +PciStructPtr +findPciByIDs(int bus, int dev, int func) +{ + PciStructPtr pciP = PciList; + + while (pciP) { + if (pciP->bus == bus && pciP->dev == dev && pciP->func == func) + return pciP; + pciP = pciP->next; + } + return NULL; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/pci.h b/board/MAI/bios_emulator/scitech/src/v86bios/pci.h new file mode 100644 index 0000000..58ad522 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/pci.h @@ -0,0 +1,127 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "v86bios.h" + +#ifndef V86_PCI_H +#define V86_PCI_H + +typedef union { + struct { + unsigned int zero:2; + unsigned int reg:6; + unsigned int func:3; + unsigned int dev:5; + unsigned int bus:8; + unsigned int reserved:7; + unsigned int enable:1; + } pci; + CARD32 l; +} PciSlot; + +typedef struct pciBusRec { + CARD8 primary; + CARD8 secondary; + CARD32 bctl; + PciSlot Slot; + struct pciBusRec *next; + struct pciBusRec *pBus; +} PciBusRec, *PciBusPtr; + +typedef struct pciStructRec { + CARD16 VendorID; + CARD16 DeviceID; + CARD8 Interface; + CARD8 BaseClass; + CARD8 SubClass; + CARD32 RomBase; + CARD32 bus; + CARD8 dev; + CARD8 func; + CARD32 cmd_st; + int active; + PciSlot Slot; + struct pciStructRec *next; + PciBusPtr pBus; +} PciStructRec , *PciStructPtr; + + +extern PciStructPtr CurrentPci; +extern PciStructPtr PciList; +extern PciStructPtr BootBios; +extern int pciMaxBus; + +extern CARD32 findPci(CARD16 slotBX); +extern CARD16 pciSlotBX(PciStructPtr); +PciStructPtr findPciDevice(CARD16 vendorID, CARD16 deviceID, char n); +PciStructPtr findPciClass(CARD8 intf, CARD8 subClass, CARD16 class, char n); + +extern CARD8 PciRead8(int offset, CARD32 slot); +extern CARD16 PciRead16(int offset, CARD32 slot); +extern CARD32 PciRead32(int offset, CARD32 slot); + +extern void PciWrite8(int offset,CARD8 byte, CARD32 slot); +extern void PciWrite16(int offset,CARD16 word, CARD32 slot); +extern void PciWrite32(int offset,CARD32 lg, CARD32 slot); + +extern void scan_pci(void); +extern void pciVideoDisable(void); +extern void pciVideoRestore(void); +extern void EnableCurrent(void); +extern int mapPciRom(PciStructPtr pciP); +extern int cfg1out(CARD16 addr, CARD32 val); +extern int cfg1in(CARD16 addr, CARD32 *val); +extern void list_pci(void); +extern PciStructPtr findPciByIDs(int bus, int dev, int func); + +#define PCI_MODE2_ENABLE_REG 0xCF8 +#define PCI_MODE2_FORWARD_REG 0xCFA +#define PCI_MODE1_ADDRESS_REG 0xCF8 +#define PCI_MODE1_DATA_REG 0xCFC +#if defined(__alpha__) || defined(__sparc__) +#define PCI_EN 0x00000000 +#else +#define PCI_EN 0x80000000 +#endif +#define MAX_DEV_PER_VENDOR_CFG1 32 +#define BRIDGE_CLASS(x) (x == 0x06) +#define BRIDGE_PCI_CLASS(x) (x == 0x04) +#define BRIDGE_HOST_CLASS(x) (x == 0x00) +#define PCI_CLASS_PREHISTORIC 0x00 +#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 +#define PCI_CLASS_DISPLAY 0x03 +#define PCI_SUBCLASS_DISPLAY_VGA 0x00 +#define PCI_SUBCLASS_DISPLAY_XGA 0x01 +#define PCI_SUBCLASS_DISPLAY_MISC 0x80 +#define VIDEO_CLASS(b,s) \ + (((b) == PCI_CLASS_PREHISTORIC && (s) == PCI_SUBCLASS_PREHISTORIC_VGA) || \ + ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_VGA) ||\ + ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_XGA) ||\ + ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_MISC)) +#define PCI_MULTIFUNC_DEV 0x80 +#define MAX_PCI_DEVICES 64 +#define PCI_MAXBUS 16 +#define PCI_IS_MEM 0x00000001 +#define MAX_PCI_ROM_SIZE (1024 * 1024 * 16) + +#define IS_MEM32(x) ((x & 0x7) == 0 && x != 0) +#define IS_MEM64(x) ((x & 0x7) == 0x4) +#endif diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86.c b/board/MAI/bios_emulator/scitech/src/v86bios/v86.c new file mode 100644 index 0000000..4deed04 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/v86.c @@ -0,0 +1,562 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "debug.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "v86bios.h" +#include "AsmMacros.h" + +struct vm86_struct vm86s; + +static int vm86_GP_fault(void); +static int vm86_do_int(int num); +static void dump_code(void); +static void dump_registers(void); +static void stack_trace(void); +static int vm86_rep(struct vm86_struct *ptr); + +#define CPU_REG(x) (vm86s.regs.##x) +#define CPU_REG_LW(reg) (*((CARD16 *)&CPU_REG(reg))) +#define CPU_REG_HW(reg) (*((CARD16 *)&CPU_REG(reg) + 1)) +#define CPU_REG_LB(reg) (*(CARD8 *)&CPU_REG(e##reg)) +#define SEG_ADR(type, seg, reg) type((CPU_REG_LW(seg) << 4) \ + + CPU_REG_LW(e##reg)) +#define DF (1 << 10) + +struct pio P; + + +void +setup_io(void) +{ + if (!Config.PrintPort && !Config.IoStatistics) { + P.inb = (CARD8(*)(CARD16))inb; + P.inw = (CARD16(*)(CARD16))inw; + P.inl = (CARD32(*)(CARD16))inl; + P.outb = (void(*)(CARD16,CARD8))outb; + P.outw = (void(*)(CARD16,CARD16))outw; + P.outl = (void(*)(CARD16,CARD32))outl; + } else { + P.inb = p_inb; + P.inw = p_inw; + P.inl = p_inl; + P.outb = p_outb; + P.outw = p_outw; + P.outl = p_outl; + } +} + + +static void +setup_vm86(unsigned long bios_start, i86biosRegsPtr regs) +{ + CARD32 eip; + CARD16 cs; + + vm86s.flags = VM86_SCREEN_BITMAP; + vm86s.flags = 0; + vm86s.screen_bitmap = 0; + vm86s.cpu_type = CPU_586; + memset(&vm86s.int_revectored, 0xff,sizeof(vm86s.int_revectored)) ; + memset(&vm86s.int21_revectored, 0xff,sizeof(vm86s.int21_revectored)) ; + + eip = bios_start & 0xFFFF; + cs = (bios_start & 0xFF0000) >> 4; + + CPU_REG(eax) = regs->ax; + CPU_REG(ebx) = regs->bx; + CPU_REG(ecx) = regs->cx; + CPU_REG(edx) = regs->dx; + CPU_REG(esi) = 0; + CPU_REG(edi) = regs->di; + CPU_REG(ebp) = 0; + CPU_REG(eip) = eip; + CPU_REG(cs) = cs; + CPU_REG(esp) = 0x100; + CPU_REG(ss) = 0x30; /* This is the standard pc bios stack */ + CPU_REG(es) = regs->es; + CPU_REG(ds) = 0x40; /* standard pc ds */ + CPU_REG(fs) = 0; + CPU_REG(gs) = 0; + CPU_REG(eflags) |= (VIF_MASK | VIP_MASK); +} + +void +collect_bios_regs(i86biosRegsPtr regs) +{ + regs->ax = CPU_REG(eax); + regs->bx = CPU_REG(ebx); + regs->cx = CPU_REG(ecx); + regs->dx = CPU_REG(edx); + regs->es = CPU_REG(es); + regs->ds = CPU_REG(ds); + regs->di = CPU_REG(edi); + regs->si = CPU_REG(esi); +} + +static int +do_vm86(void) +{ + int retval; + +#ifdef V86BIOS_DEBUG + dump_registers(); +#endif +/* retval = SYS_vm86old(&vm86s); */ +/* retval = syscall(SYS_vm86old,&vm86s); */ + + retval = vm86_rep(&vm86s); + + switch (VM86_TYPE(retval)) { + case VM86_UNKNOWN: + if (!vm86_GP_fault()) return 0; + break; + case VM86_STI: + fprintf(stderr,"vm86_sti :-((\n"); + stack_trace(); + dump_code(); + return 0; + case VM86_INTx: + if (!vm86_do_int(VM86_ARG(retval))) { + fprintf(stderr,"\nUnknown vm86_int: %X\n\n",VM86_ARG(retval)); + dump_registers(); + return 0; + } + /* I'm not sure yet what to do if we can handle ints */ + break; + case VM86_SIGNAL: + fprintf(stderr,"received signal\n"); + return 0; + default: + fprintf(stderr,"unknown type(0x%x)=0x%x\n", + VM86_ARG(retval),VM86_TYPE(retval)); + dump_registers(); + dump_code(); + stack_trace(); + return 0; + } + + return 1; +} + +static jmp_buf x86_esc; +static void +vmexit(int unused) +{ + longjmp(x86_esc,1); +} + +void +do_x86(unsigned long bios_start, i86biosRegsPtr regs) +{ + static void (*org_handler)(int); + + setup_vm86(bios_start, regs); + if (setjmp(x86_esc) == 0) { + org_handler = signal(2,vmexit); + while(do_vm86()) {}; + signal(2,org_handler); + collect_bios_regs(regs); + } else { + signal(2,org_handler); + printf("interrupted at 0x%x\n",((CARD16)CPU_REG(cs)) << 4 + | (CARD16)CPU_REG(eip)); + } +} + +/* get the linear address */ +#define LIN_PREF_SI ((pref_seg << 4) + CPU_REG_LW(esi)) + +#define LWECX (prefix66 ^ prefix67 ? CPU_REG(ecx) : CPU_REG_LW(ecx)) + +static int +vm86_GP_fault(void) +{ + unsigned char *csp, *lina; + CARD32 org_eip; + int pref_seg; + int done,is_rep,prefix66,prefix67; + + + csp = lina = SEG_ADR((unsigned char *), cs, ip); +#ifdef V86BIOS_DEBUG + printf("exception: \n"); + dump_code(); +#endif + + is_rep = 0; + prefix66 = prefix67 = 0; + pref_seg = -1; + + /* eat up prefixes */ + done = 0; + do { + switch (*(csp++)) { + case 0x66: /* operand prefix */ prefix66=1; break; + case 0x67: /* address prefix */ prefix67=1; break; + case 0x2e: /* CS */ pref_seg=CPU_REG(cs); break; + case 0x3e: /* DS */ pref_seg=CPU_REG(ds); break; + case 0x26: /* ES */ pref_seg=CPU_REG(es); break; + case 0x36: /* SS */ pref_seg=CPU_REG(ss); break; + case 0x65: /* GS */ pref_seg=CPU_REG(gs); break; + case 0x64: /* FS */ pref_seg=CPU_REG(fs); break; + case 0xf2: /* repnz */ + case 0xf3: /* rep */ is_rep=1; break; + default: done=1; + } + } while (!done); + csp--; /* oops one too many */ + org_eip = CPU_REG(eip); + CPU_REG_LW(eip) += (csp - lina); + + switch (*csp) { + + case 0x6c: /* insb */ + /* NOTE: ES can't be overwritten; prefixes 66,67 should use esi,edi,ecx + * but is anyone using extended regs in real mode? */ + /* WARNING: no test for DI wrapping! */ + CPU_REG_LW(edi) += port_rep_inb(CPU_REG_LW(edx), + SEG_ADR((CARD8 *),es,di), + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + if (is_rep) LWECX = 0; + CPU_REG_LW(eip)++; + break; + + case 0x6d: /* (rep) insw / insd */ + /* NOTE: ES can't be overwritten */ + /* WARNING: no test for _DI wrapping! */ + if (prefix66) { + CPU_REG_LW(edi) += port_rep_inl(CPU_REG_LW(edx), + SEG_ADR((CARD32 *),es,di), + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + } + else { + CPU_REG_LW(edi) += port_rep_inw(CPU_REG_LW(edx), + SEG_ADR((CARD16 *),es,di), + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + } + if (is_rep) LWECX = 0; + CPU_REG_LW(eip)++; + break; + + case 0x6e: /* (rep) outsb */ + if (pref_seg < 0) pref_seg = CPU_REG_LW(ds); + /* WARNING: no test for _SI wrapping! */ + CPU_REG_LW(esi) += port_rep_outb(CPU_REG_LW(edx),(CARD8*)LIN_PREF_SI, + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + if (is_rep) LWECX = 0; + CPU_REG_LW(eip)++; + break; + + case 0x6f: /* (rep) outsw / outsd */ + if (pref_seg < 0) pref_seg = CPU_REG_LW(ds); + /* WARNING: no test for _SI wrapping! */ + if (prefix66) { + CPU_REG_LW(esi) += port_rep_outl(CPU_REG_LW(edx), + (CARD32 *)LIN_PREF_SI, + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + } + else { + CPU_REG_LW(esi) += port_rep_outw(CPU_REG_LW(edx), + (CARD16 *)LIN_PREF_SI, + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + } + if (is_rep) LWECX = 0; + CPU_REG_LW(eip)++; + break; + + case 0xe5: /* inw xx, inl xx */ + if (prefix66) CPU_REG(eax) = P.inl((int) csp[1]); + else CPU_REG_LW(eax) = P.inw((int) csp[1]); + CPU_REG_LW(eip) += 2; + break; + case 0xe4: /* inb xx */ + CPU_REG_LW(eax) &= ~(CARD32)0xff; + CPU_REG_LB(ax) |= P.inb((int) csp[1]); + CPU_REG_LW(eip) += 2; + break; + case 0xed: /* inw dx, inl dx */ + if (prefix66) CPU_REG(eax) = P.inl(CPU_REG_LW(edx)); + else CPU_REG_LW(eax) = P.inw(CPU_REG_LW(edx)); + CPU_REG_LW(eip) += 1; + break; + case 0xec: /* inb dx */ + CPU_REG_LW(eax) &= ~(CARD32)0xff; + CPU_REG_LB(ax) |= P.inb(CPU_REG_LW(edx)); + CPU_REG_LW(eip) += 1; + break; + + case 0xe7: /* outw xx */ + if (prefix66) P.outl((int)csp[1], CPU_REG(eax)); + else P.outw((int)csp[1], CPU_REG_LW(eax)); + CPU_REG_LW(eip) += 2; + break; + case 0xe6: /* outb xx */ + P.outb((int) csp[1], CPU_REG_LB(ax)); + CPU_REG_LW(eip) += 2; + break; + case 0xef: /* outw dx */ + if (prefix66) P.outl(CPU_REG_LW(edx), CPU_REG(eax)); + else P.outw(CPU_REG_LW(edx), CPU_REG_LW(eax)); + CPU_REG_LW(eip) += 1; + break; + case 0xee: /* outb dx */ + P.outb(CPU_REG_LW(edx), CPU_REG_LB(ax)); + CPU_REG_LW(eip) += 1; + break; + + case 0xf4: +#ifdef V86BIOS_DEBUG + printf("hlt at %p\n", lina); +#endif + return 0; + + case 0x0f: + fprintf(stderr,"CPU 0x0f Trap at eip=0x%lx\n",CPU_REG(eip)); + goto op0ferr; + break; + + case 0xf0: /* lock */ + default: + fprintf(stderr,"unknown reason for exception\n"); + dump_registers(); + stack_trace(); + op0ferr: + dump_code(); + fprintf(stderr,"cannot continue\n"); + return 0; + } /* end of switch() */ + return 1; +} + +static int +vm86_do_int(int num) +{ + int val; + struct regs86 regs; + + i_printf("int 0x%x received: ax:0x%lx",num,CPU_REG(eax)); + if (Config.PrintIp) + i_printf(" at: 0x%x\n",getIP()); + else + i_printf("\n"); + + /* try to run bios interrupt */ + + /* if not installed fall back */ +#define COPY(x) regs.##x = CPU_REG(x) +#define COPY_R(x) CPU_REG(x) = regs.##x + + COPY(eax); + COPY(ebx); + COPY(ecx); + COPY(edx); + COPY(esi); + COPY(edi); + COPY(ebp); + COPY(eip); + COPY(esp); + COPY(cs); + COPY(ss); + COPY(ds); + COPY(es); + COPY(fs); + COPY(gs); + COPY(eflags); + + if (!(val = int_handler(num,®s))) + if (!(val = run_bios_int(num,®s))) + return val; + + COPY_R(eax); + COPY_R(ebx); + COPY_R(ecx); + COPY_R(edx); + COPY_R(esi); + COPY_R(edi); + COPY_R(ebp); + COPY_R(eip); + COPY_R(esp); + COPY_R(cs); + COPY_R(ss); + COPY_R(ds); + COPY_R(es); + COPY_R(fs); + COPY_R(gs); + COPY_R(eflags); + + return val; +#undef COPY +#undef COPY_R +} + +static void +dump_code(void) +{ + int i; + unsigned char *lina = SEG_ADR((unsigned char *), cs, ip); + + fprintf(stderr,"code at 0x%8.8x: ",(CARD32)lina); + for (i=0; i<0x10; i++) + fprintf(stderr,"%2.2x ",*(lina + i)); + fprintf(stderr,"\n "); + for (; i<0x20; i++) + fprintf(stderr,"%2.2x ",*(lina + i)); + fprintf(stderr,"\n"); +} + +#define PRINT(x) fprintf(stderr,#x":%4.4x ",CPU_REG_LW(x)) +#define PRINT_FLAGS(x) fprintf(stderr,#x":%8.8x ",CPU_REG_LW(x)) +static void +dump_registers(void) +{ + PRINT(eip); + PRINT(eax); + PRINT(ebx); + PRINT(ecx); + PRINT(edx); + PRINT(esi); + PRINT(edi); + PRINT(ebp); + fprintf(stderr,"\n"); + PRINT(esp); + PRINT(cs); + PRINT(ss); + PRINT(es); + PRINT(ds); + PRINT(fs); + PRINT(gs); + PRINT_FLAGS(eflags); + fprintf(stderr,"\n"); +} + +static void +stack_trace(void) +{ + int i; + unsigned char *stack = SEG_ADR((unsigned char *), ss, sp); + + fprintf(stderr,"stack at 0x%8.8lx:\n",(unsigned long)stack); + for (i=0; i < 0x10; i++) + fprintf(stderr,"%2.2x ",*(stack + i)); + fprintf(stderr,"\n"); + +} + +static int +vm86_rep(struct vm86_struct *ptr) +{ + + int __res; + + __asm__ __volatile__("int $0x80\n" + :"=a" (__res):"a" ((int)113), + "b" ((struct vm86_struct *)ptr)); + + if ((__res) < 0) { + errno = -__res; + __res=-1; + } + else errno = 0; + return __res; +} + +#define pushw(base, ptr, val) \ +__asm__ __volatile__( \ + "decw %w0\n\t" \ + "movb %h2,(%1,%0)\n\t" \ + "decw %w0\n\t" \ + "movb %b2,(%1,%0)" \ + : "=r" (ptr) \ + : "r" (base), "q" (val), "0" (ptr)) + +int +run_bios_int(int num, struct regs86 *regs) +{ + CARD16 *ssp; + CARD32 sp; + CARD32 eflags; + +#ifdef V86BIOS_DEBUG + static int firsttime = 1; +#endif + /* check if bios vector is initialized */ + if (((CARD16*)0)[(num<<1)+1] == 0x0000) { /* SYS_BIOS_SEG ?*/ +#ifdef V86BIOS_DEBUG + i_printf("card BIOS not loaded\n"); +#endif + return 0; + } + +#ifdef V86BIOS_DEBUG + if (firsttime) { + dprint(0,0x3D0); + firsttime = 0; + } +#endif + + i_printf("calling card BIOS at: "); + ssp = (CARD16*)(CPU_REG(ss)<<4); + sp = (CARD32) CPU_REG_LW(esp); + + eflags = regs->eflags; + eflags = ((eflags & VIF_MASK) != 0) + ? (eflags | IF_MASK) : (eflags & ~(CARD32) IF_MASK); + pushw(ssp, sp, eflags); + pushw(ssp, sp, regs->cs); + pushw(ssp, sp, (CARD16)regs->eip); + regs->esp -= 6; + regs->cs = ((CARD16 *) 0)[(num << 1) + 1]; + regs->eip = (regs->eip & 0xFFFF0000) | ((CARD16 *) 0)[num << 1]; + i_printf("0x%x:%lx\n",regs->cs,regs->eip); +#ifdef V86BIOS_DEBUG + dump_code(); +#endif + regs->eflags = regs->eflags + & ~(VIF_MASK | TF_MASK | IF_MASK | NT_MASK); + return 1; +} + +CARD32 +getIntVect(int num) +{ + return ((CARD32*)0)[num]; +} + +CARD32 +getIP(void) +{ + return (CPU_REG(cs) << 4) + CPU_REG(eip); +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c new file mode 100644 index 0000000..101c1f2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c @@ -0,0 +1,933 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#define DELETE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(__alpha__) || defined (__ia64__) +#include +#elif defined(HAVE_SYS_PERM) +#include +#endif +#include "debug.h" +#include "v86bios.h" +#include "pci.h" +#include "AsmMacros.h" + +#define SIZE 0x100000 +#define VRAM_START 0xA0000 +#define VRAM_SIZE 0x1FFFF +#define V_BIOS_SIZE 0x1FFFF +#define BIOS_START 0x7C00 /* default BIOS entry */ +#define BIOS_MEM 0x600 + +/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0, 0xf4 }; */ +#define VB_X(x) (V_BIOS >> x) & 0xFF +CARD8 code[] = { 6, 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xf4 }; +/*CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xb8, 0x03, 0x00, */ +/*0xcd, 0x10, 0xf4 }; */ +/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0 ,0xf4 }; */ + +int ioperm_list[IOPERM_BITS] = {0,}; + +static void sig_handler(int); +static int map(void); +static void unmap(void); +static void bootBIOS(CARD16 ax); +static int map_vram(void); +static void unmap_vram(void); +static int copy_vbios(memType v_base); +static int copy_sys_bios(void); +static void save_bios_to_file(void); +static int setup_system_bios(void); +static CARD32 setup_int_vect(void); +#ifdef __ia32__ +static CARD32 setup_primary_int_vect(void); +#endif +static int chksum(CARD8 *start); +static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax); +static void print_regs(i86biosRegsPtr regs); +static void print_usage(void); +static void set_hlt(Bool set); +static void set_ioperm(void); + +extern void yyparse(); + +void loadCodeToMem(unsigned char *ptr, CARD8 *code); +void dprint(unsigned long start, unsigned long size); + +static int vram_mapped = 0; +static char* bios_var = NULL; +static CARD8 save_msr; +static CARD8 save_pos102; +static CARD8 save_vse; +static CARD8 save_46e8; +static haltpoints hltp[20] = { {0, 0}, }; + +console Console = {-1,-1}; +struct config Config; + +int main(int argc,char **argv) +{ + int c; + + Config.PrintPort = PRINT_PORT; + Config.IoStatistics = IO_STATISTICS; + Config.PrintIrq = PRINT_IRQ; + Config.PrintPci = PRINT_PCI; + Config.ShowAllDev = SHOW_ALL_DEV; + Config.PrintIp = PRINT_IP; + Config.SaveBios = SAVE_BIOS; + Config.Trace = TRACE; + Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY; /* boot */ + Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; /* boot */ + Config.MapSysBios = MAP_SYS_BIOS; + Config.Resort = RESORT; /* boot */ + Config.FixRom = FIX_ROM; + Config.NoConsole = NO_CONSOLE; + Config.BootOnly = FALSE; + Config.Verbose = VERBOSE; + + opterr = 0; + while ((c = getopt(argc,argv,"psicaPStAdbrfnv:?")) != EOF) { + switch(c) { + case 'p': + Config.PrintPort = TRUE; + break; + case 's': + Config.IoStatistics = TRUE; + break; + case 'i': + Config.PrintIrq = TRUE; + break; + case 'c': + Config.PrintPci = TRUE; + break; + case 'a': + Config.ShowAllDev = TRUE; + break; + case 'P': + Config.PrintIp = TRUE; + break; + case 'S': + Config.SaveBios = TRUE; + break; + case 't': + Config.Trace = TRUE; + break; + case 'A': + Config.ConfigActiveOnly = TRUE; + break; + case 'd': + Config.ConfigActiveDevice = TRUE; + break; + case 'b': + Config.MapSysBios = TRUE; + break; + case 'r': + Config.Resort = TRUE; + break; + case 'f': + Config.FixRom = TRUE; + break; + case 'n': + Config.NoConsole = TRUE; + break; + case 'v': + Config.Verbose = strtol(optarg,NULL,0); + break; + case '?': + print_usage(); + break; + default: + break; + } + } + + + if (!map()) + exit(1); + + if (!setup_system_bios()) + exit(1); + + iopl(3); + + scan_pci(); + + save_msr = inb(0x3CC); + save_vse = inb(0x3C3); + save_46e8 = inb(0x46e8); + save_pos102 = inb(0x102); + + if (Config.BootOnly) { + + if (!CurrentPci && !Config.ConfigActiveDevice + && !Config.ConfigActiveOnly) { + iopl(0); + unmap(); + exit (1); + } + call_boot(NULL); + } else { + using_history(); + yyparse(); + } + + unmap(); + + pciVideoRestore(); + + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + + iopl(0); + + close_console(Console); + + exit(0); +} + + +void +call_boot(struct device *dev) +{ + int Active_is_Pci = 0; + CARD32 vbios_base; + + CurrentPci = PciList; + Console = open_console(); + + set_ioperm(); + + + signal(2,sig_handler); + signal(11,sig_handler); + + /* disable primary card */ + pciVideoRestore(); /* reset PCI state to see primary card */ + outb(0x3C2,~(CARD8)0x03 & save_msr); + outb(0x3C3,~(CARD8)0x01 & save_vse); + outb(0x46e8, ~(CARD8)0x08 & save_46e8); + outb(0x102, ~(CARD8)0x01 & save_pos102); + + pciVideoDisable(); + + while (CurrentPci) { + CARD16 ax; + + if (CurrentPci->active) { + Active_is_Pci = 1; + if (!Config.ConfigActiveDevice && !dev) { + CurrentPci = CurrentPci->next; + continue; + } + } else if (Config.ConfigActiveOnly && !dev) { + CurrentPci = CurrentPci->next; + continue; + } + if (dev && ((dev->type != PCI) + || (dev->type == PCI + && (dev->loc.pci.dev != CurrentPci->dev + || dev->loc.pci.bus != CurrentPci->bus + || dev->loc.pci.func != CurrentPci->func)))) { + CurrentPci = CurrentPci->next; + continue; + } + + EnableCurrent(); + + if (CurrentPci->active) { + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + } + + /* clear interrupt vectors */ +#ifdef __ia32__ + vbios_base = CurrentPci->active ? setup_primary_int_vect() + : setup_int_vect(); +#else + vbios_base = setup_int_vect(); +#endif + ax = ((CARD16)(CurrentPci->bus) << 8) + | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7); + if (Config.Verbose > 1) P_printf("ax: 0x%x\n",ax); + + BootBios = findPciByIDs(CurrentPci->bus,CurrentPci->dev, + CurrentPci->func); + if (!((mapPciRom(BootBios) && chksum((CARD8*)V_BIOS)) + || (CurrentPci->active && copy_vbios(vbios_base)))) { + CurrentPci = CurrentPci->next; + continue; + } + if (!map_vram()) { + CurrentPci = CurrentPci->next; + continue; + } + if (Config.SaveBios) save_bios_to_file(); + printf("initializing PCI bus: %i dev: %i func: %i\n",CurrentPci->bus, + CurrentPci->dev,CurrentPci->func); + bootBIOS(ax); + unmap_vram(); + + if (CurrentPci->active) + close_console(Console); + + if (dev) return; + + CurrentPci = CurrentPci->next; + } + + /* We have an ISA device - configure if requested */ + if (!Active_is_Pci /* no isa card in system! */ + && ((!dev && (Config.ConfigActiveDevice || Config.ConfigActiveOnly)) + || (dev && dev->type == ISA))) { + + pciVideoDisable(); + + if (!dev || dev->type == ISA) { + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + +#ifdef __ia32__ + vbios_base = setup_primary_int_vect(); +#else + vbios_base = setup_int_vect(); +#endif + if (copy_vbios(vbios_base)) { + + if (Config.SaveBios) save_bios_to_file(); + if (map_vram()) { + printf("initializing ISA bus\n"); + bootBIOS(0); + } + } + + unmap_vram(); + sleep(1); + close_console(Console); + } + } + + +} + +int +map(void) +{ + void* mem; + mem = mmap(0, (size_t)SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_PRIVATE | MAP_ANON, + -1, 0 ); + if (mem != 0) { + perror("anonymous map"); + return (0); + } + memset(mem,0,SIZE); + + return (1); +} + +static void +unmap(void) +{ + munmap(0,SIZE); +} + +static void +bootBIOS(CARD16 ax) +{ + i86biosRegs bRegs; +#ifdef V86BIOS_DEBUG + printf("starting BIOS\n"); +#endif + setup_io(); + setup_bios_regs(&bRegs, ax); + loadCodeToMem((unsigned char *) BIOS_START, code); + do_x86(BIOS_START,&bRegs); +#ifdef V86BIOS_DEBUG + printf("done\n"); +#endif +} + +static int +map_vram(void) +{ + int mem_fd; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return 0; + } + +#ifdef __alpha__ + if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */ + if (!_bus_base_sparse()) sparse_shift = 0; + if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift), + PROT_READ | PROT_WRITE, + MAP_SHARED, + mem_fd, (VRAM_START << sparse_shift) + | _bus_base_sparse())) == (void *) -1) +#else + if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, + mem_fd, VRAM_START) == (void *) -1) +#endif + { + perror("mmap error in map_hardware_ram (1)"); + close(mem_fd); + return (0); + } + vram_mapped = 1; + close(mem_fd); + return (1); +} + +static void +unmap_vram(void) +{ + if (!vram_mapped) return; + + munmap((void*)VRAM_START,VRAM_SIZE); + vram_mapped = 0; +} + +static int +copy_vbios(memType v_base) +{ + int mem_fd; + unsigned char *tmp; + int size; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) v_base, SEEK_SET) != (off_t) v_base) { + fprintf(stderr,"Cannot lseek\n"); + goto Error; + } + tmp = (unsigned char *)malloc(3); + if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + if (lseek(mem_fd,(off_t) v_base,SEEK_SET) != (off_t) v_base) + goto Error; + + if (*tmp != 0x55 || *(tmp+1) != 0xAA ) { + fprintf(stderr,"No bios found at: 0x%lx\n",v_base); + goto Error; + } +#ifdef DEBUG + dprint((unsigned long)tmp,0x100); +#endif + size = *(tmp+2) * 512; + + if (read(mem_fd, (char *)v_base, (size_t) size) != (size_t) size) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + free(tmp); + close(mem_fd); + if (!chksum((CARD8*)v_base)) + return (0); + + return (1); + +Error: + perror("v_bios"); + close(mem_fd); + return (0); +} + +static int +copy_sys_bios(void) +{ +#define SYS_BIOS 0xF0000 + int mem_fd; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS) + goto Error; + if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF) + goto Error; + + close(mem_fd); + return (1); + +Error: + perror("sys_bios"); + close(mem_fd); + return (0); +} + +void +loadCodeToMem(unsigned char *ptr, CARD8 code[]) +{ + int i; + CARD8 val; + int size = code[0]; + + for ( i=1;i<=size;i++) { + val = code[i]; + *ptr++ = val; + } + return; +} + +void +dprint(unsigned long start, unsigned long size) +{ + int i,j; + char *c = (char *)start; + + for (j = 0; j < (size >> 4); j++) { + char *d = c; + printf("\n0x%lx: ",(unsigned long)c); + for (i = 0; i<16; i++) + printf("%2.2x ",(unsigned char) (*(c++))); + c = d; + for (i = 0; i<16; i++) { + printf("%c",((((CARD8)(*c)) > 32) && (((CARD8)(*c)) < 128)) ? + (unsigned char) (*(c)): '.'); + c++; + } + } + printf("\n"); +} + +static void +save_bios_to_file(void) +{ + static int num = 0; + int size, count; + char file_name[256]; + int fd; + + sprintf(file_name,"bios_%i.fil",num); + if ((fd = open(file_name,O_WRONLY | O_CREAT | O_TRUNC,00644)) == -1) + return; + size = (*(unsigned char*)(V_BIOS + 2)) * 512; +#ifdef V86BIOS_DEBUG + dprint(V_BIOS,20); +#endif + if ((count = write(fd,(void *)(V_BIOS),size)) != size) + fprintf(stderr,"only saved %i of %i bytes\n",size,count); + num++; +} + +static void +sig_handler(int unused) +{ + fflush(stdout); + fflush(stderr); + + /* put system back in a save state */ + unmap_vram(); + pciVideoRestore(); + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + + close_console(Console); + iopl(0); + unmap(); + + exit(1); +} + +/* + * For initialization we just pass ax to the BIOS. + * PCI BIOSes need this. All other register are set 0. + */ +static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax) +{ + regs->ax = ax; + regs->bx = 0; + regs->cx = 0; + regs->dx = 0; + regs->es = 0; + regs->ds = 0x40; /* standard pc ds */ + regs->si = 0; + regs->di = 0; +} + +/* + * here we are really paranoid about faking a "real" + * BIOS. Most of this information was pulled from + * dosem. + */ + +#ifdef __ia32__ +static CARD32 +setup_primary_int_vect(void) +{ + int mem_fd; + CARD32 vbase; + void *map; + + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) + { + perror("opening memory"); + return (0); + } + + if ((map = mmap((void *) 0, (size_t) 0x2000, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, + mem_fd, 0)) == (void *)-1) { + perror("mmap error in map_hardware_ram (2)"); + close(mem_fd); + return (0); + } + + close(mem_fd); + memcpy(0,map,BIOS_MEM); + munmap(map,0x2000); + /* + * create a backup copy of the bios variables to write back the + * modified values + */ + if (!bios_var) + bios_var = (char *)malloc(BIOS_MEM); + memcpy(bios_var,0,BIOS_MEM); + + vbase = (*((CARD16*)(0x10 << 2) + 1)) << 4; + if (Config.Verbose > 0) printf("vbase: 0x%x\n",vbase); + return vbase; +} +#endif + +static CARD32 +setup_int_vect(void) +{ + const CARD16 cs = 0x0; + const CARD16 ip = 0x0; + int i; + + /* let the int vects point to the SYS_BIOS seg */ + for (i=0; i<0x80; i++) { + ((CARD16*)0)[i<<1] = ip; + ((CARD16*)0)[(i<<1)+1] = cs; + } + /* video interrupts default location */ + ((CARD16*)0)[(0x42<<1)+1] = 0xf000; + ((CARD16*)0)[0x42<<1] = 0xf065; + ((CARD16*)0)[(0x10<<1)+1] = 0xf000; + ((CARD16*)0)[0x10<<1] = 0xf065; + /* video param table default location (int 1d) */ + ((CARD16*)0)[(0x1d<<1)+1] = 0xf000; + ((CARD16*)0)[0x1d<<1] = 0xf0A4; + /* font tables default location (int 1F) */ + ((CARD16*)0)[(0x1f<<1)+1] = 0xf000; + ((CARD16*)0)[0x1f<<1] = 0xfa6e; + + /* int 11 default location */ + ((CARD16*)0)[(0x11<<1)+1] = 0xf000; + ((CARD16*)0)[0x11<<1] = 0xf84d; + /* int 12 default location */ + ((CARD16*)0)[(0x12<<1)+1] = 0xf000; + ((CARD16*)0)[0x12<<1] = 0xf841; + /* int 15 default location */ + ((CARD16*)0)[(0x15<<1)+1] = 0xf000; + ((CARD16*)0)[0x15<<1] = 0xf859; + /* int 1A default location */ + ((CARD16*)0)[(0x1a<<1)+1] = 0xf000; + ((CARD16*)0)[0x1a<<1] = 0xff6e; + /* int 05 default location */ + ((CARD16*)0)[(0x05<<1)+1] = 0xf000; + ((CARD16*)0)[0x05<<1] = 0xff54; + /* int 08 default location */ + ((CARD16*)0)[(0x8<<1)+1] = 0xf000; + ((CARD16*)0)[0x8<<1] = 0xfea5; + /* int 13 default location (fdd) */ + ((CARD16*)0)[(0x13<<1)+1] = 0xf000; + ((CARD16*)0)[0x13<<1] = 0xec59; + /* int 0E default location */ + ((CARD16*)0)[(0xe<<1)+1] = 0xf000; + ((CARD16*)0)[0xe<<1] = 0xef57; + /* int 17 default location */ + ((CARD16*)0)[(0x17<<1)+1] = 0xf000; + ((CARD16*)0)[0x17<<1] = 0xefd2; + /* fdd table default location (int 1e) */ + ((CARD16*)0)[(0x1e<<1)+1] = 0xf000; + ((CARD16*)0)[0x1e<<1] = 0xefc7; + return V_BIOS; +} + +static int +setup_system_bios(void) +{ + char *date = "06/01/99"; + char *eisa_ident = "PCI/ISA"; + + if (Config.MapSysBios) { + + if (!copy_sys_bios()) return 0; + return 1; + + } else { + +/* memset((void *)0xF0000,0xf4,0xfff7); */ + + /* + * we trap the "industry standard entry points" to the BIOS + * and all other locations by filling them with "hlt" + * TODO: implement hlt-handler for these + */ + memset((void *)0xF0000,0xf4,0x10000); + + /* + * TODO: we should copy the fdd table (0xfec59-0xfec5b) + * the video parameter table (0xf0ac-0xf0fb) + * and the font tables (0xfa6e-0xfe6d) + * from the original bios here + */ + + /* set bios date */ + strcpy((char *)0xFFFF5,date); + /* set up eisa ident string */ + strcpy((char *)0xFFFD9,eisa_ident); + /* write system model id for IBM-AT */ + ((char *)0)[0xFFFFE] = 0xfc; + + return 1; + } + +} + +static void +update_bios_vars(void) +{ + int mem_fd; + void *map; + memType i; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return; + } + + if ((map = mmap((void *) 0, (size_t) 0x2000, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, + mem_fd, 0)) == (void *)-1) { + perror("mmap error in map_hardware_ram (3)"); + close(mem_fd); + return; + } + + for (i = 0; i < BIOS_MEM; i++) { + if (bios_var[i] != *(CARD8*)i) + *((CARD8*)map + i) = *(CARD8*)i; + } + + munmap(map,0x2000); + close(mem_fd); +} + +static int +chksum(CARD8 *start) +{ + CARD16 size; + CARD8 val = 0; + int i; + + size = *(start+2) * 512; + for (i = 0; iactive)) || !isVideo) { + CARD32 vbios_base; + +#ifdef __ia32__ + if (!(vbios_base = setup_primary_int_vect())) +#else + if (!(vbios_base = setup_int_vect())) +#endif + return; + if (!copy_vbios(vbios_base)) + return; + } + + if (!map_vram()) + return; + +#ifdef V86BIOS_DEBUG + printf("starting BIOS\n"); +#endif + loadCodeToMem((unsigned char *) BIOS_START, code_int); + setup_io(); + print_regs(Regs); + set_ioperm(); + set_hlt(TRUE); + do_x86(BIOS_START,Regs); + set_hlt(FALSE); + print_regs(Regs); + +#ifdef V86BIOS_DEBUG + printf("done\n"); +#endif + + if ((isVideo && (!CurrentPci || CurrentPci->active)) || !isVideo) + update_bios_vars(); +} + +static void +print_regs(i86biosRegsPtr regs) +{ + printf("ax=%x bx=%x cx=%x dx=%x ds=%x es=%x di=%x si=%x\n", + (CARD16)regs->ax,(CARD16)regs->bx,(CARD16)regs->cx,(CARD16)regs->dx, + (CARD16)regs->ds,(CARD16)regs->es,(CARD16)regs->di, + (CARD16)regs->si); +} + +static void +print_usage(void) +{ +} + +void +add_hlt(unsigned long val) +{ + int i; + + if (val < BIOS_MEM || (val > VRAM_START && val < (VRAM_START + VRAM_SIZE)) + || val >= SIZE) { + printf("address out of range\n"); + return; + } + + for (i=0; i<20; i++) { + if (hltp[i].address == 0) { + hltp[i].address = (void*)val; + break; + } + } + if (i == 20) printf("no more hltpoints available\n"); +} + +void +del_hlt(int val) +{ + if (val == 21) { /* delete all */ + int i; + printf("clearing all hltpoints\n"); + for (i=0; i <20; i++) + hltp[i].address = NULL; + } else if (val >= 0 && val <20) + hltp[val].address = NULL; + else printf("hltpoint %i out of range: valid range 0-19\n",val); +} + +void +list_hlt() +{ + int i; + for (i=0; i<20; i++) + if (hltp[i].address) + printf("hltpoint[%i]: 0x%lx\n",i,(unsigned long)hltp[i].address); +} + +static void +set_hlt(Bool set) +{ + int i; + for (i=0; i<20; i++) + if (hltp[i].address) { + if (set) { + hltp[i].orgval = *(CARD8*)hltp[i].address; + *(CARD8*)hltp[i].address = 0xf4; + } else + *(CARD8*)hltp[i].address = hltp[i].orgval; + } +} + +static void +set_ioperm(void) +{ + int i, start; + + ioperm(0,IOPERM_BITS,0); + + for (i = 0; i < IOPERM_BITS;i++) + if (ioperm_list[i]) { + start = i; + for (;i < IOPERM_BITS; i++) { + if (!ioperm_list[i]) { + ioperm(start,i - start, 1); + break; + } + } + } +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h new file mode 100644 index 0000000..a8f3f8e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h @@ -0,0 +1,214 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef V86_BIOS_H +#define V86_BIOS_H + +#if defined (__i386__) || defined (__i486__) || defined (__i586__) || defined (__i686__) || defined (__k6__) +# ifndef __ia32__ +# define __ia32__ +# endif +#endif + +#include + +#define p_printf(f,a...) do {if (Config.PrintPort) lprintf(f,##a);} \ + while(0) +#define i_printf(f,a...) do {if (Config.PrintIrq) lprintf(f,##a);} \ + while(0) +#define P_printf(f,a...) do {if (Config.PrintPci) lprintf(f,##a);} \ + while(0) + +typedef unsigned char CARD8; +typedef unsigned short CARD16; +typedef unsigned int CARD32; +#if defined (__alpha__) || defined (__ia64__) +typedef unsigned long memType; +#else +typedef unsigned int memType; +#endif + +typedef int Bool; + +#define FALSE 0 +#define TRUE 1 + +struct config { + Bool PrintPort; + Bool IoStatistics; + Bool PrintIrq; + Bool PrintPci; + Bool ShowAllDev; + Bool PrintIp; + Bool SaveBios; + Bool Trace; + Bool ConfigActiveOnly; + Bool ConfigActiveDevice; + Bool MapSysBios; + Bool Resort; + Bool FixRom; + Bool NoConsole; + Bool BootOnly; + int Verbose; +}; + +struct pio { + CARD8 (*inb)(CARD16); + CARD16 (*inw)(CARD16); + CARD32 (*inl)(CARD16); + void (*outb)(CARD16,CARD8); + void (*outw)(CARD16,CARD16); + void (*outl)(CARD16,CARD32); +}; + +struct regs86 { + long ebx; + long ecx; + long edx; + long esi; + long edi; + long ebp; + long eax; + long eip; + long esp; + unsigned short cs; + unsigned short ss; + unsigned short es; + unsigned short ds; + unsigned short fs; + unsigned short gs; + long eflags; +}; + +typedef struct { + CARD32 ax; + CARD32 bx; + CARD32 cx; + CARD32 dx; + CARD32 cs; + CARD32 es; + CARD32 ds; + CARD32 si; + CARD32 di; +} i86biosRegs, *i86biosRegsPtr; + +typedef struct { + int fd; + int vt; +} console; + +typedef struct { + void* address; + CARD8 orgval; +} haltpoints; + +enum dev_type { NONE, ISA, PCI }; +struct device { + Bool booted; + enum dev_type type; + union { + int none; + struct pci { + int bus; + int dev; + int func; + } pci; + } loc; +}; + +extern struct device Device; + +#ifdef __alpha__ +unsigned long _bus_base(void); +extern void* vram_map; +extern int sparse_shift; +#endif + +extern struct pio P; +extern struct config Config; +#define IOPERM_BITS 1024 +extern int ioperm_list[IOPERM_BITS]; + +extern void setup_io(void); +extern void do_x86(unsigned long bios_start,i86biosRegsPtr regs); +extern int run_bios_int(int num, struct regs86 *regs); +extern CARD32 getIntVect(int num); +CARD32 getIP(void); + +extern void call_boot(struct device *dev); +extern void runINT(int num,i86biosRegsPtr Regs); +extern void add_hlt(unsigned long addr); +extern void del_hlt(int addr); +extern void list_hlt(); + +extern int port_rep_inb(CARD16 port, CARD8 *base, int d_f, CARD32 count); +extern int port_rep_inw(CARD16 port, CARD16 *base, int d_f, CARD32 count); +extern int port_rep_inl(CARD16 port, CARD32 *base, int d_f, CARD32 count); +extern int port_rep_outb(CARD16 port, CARD8 *base, int d_f, CARD32 count); +extern int port_rep_outw(CARD16 port, CARD16 *base, int d_f, CARD32 count); +extern int port_rep_outl(CARD16 port, CARD32 *base, int d_f, CARD32 count); +extern CARD8 p_inb(CARD16 port); +extern CARD16 p_inw(CARD16 port); +extern CARD32 p_inl(CARD16 port); +extern void p_outb(CARD16 port, CARD8 val); +extern void p_outw(CARD16 port, CARD16 val); +extern void p_outl(CARD16 port, CARD32 val); +#ifdef __alpha__ +extern CARD8 a_inb(CARD16 port); +extern CARD16 a_inw(CARD16 port); +extern void a_outb(CARD16 port, CARD8 val); +extern void a_outw(CARD16 port, CARD16 val); +#endif +#ifdef __alpha__ +CARD8 mem_rb(CARD32 addr); +CARD16 mem_rw(CARD32 addr); +CARD32 mem_rl(CARD32 addr); +void mem_wb(CARD32 addr, CARD8 val); +void mem_ww(CARD32 addr, CARD16 val); +void mem_wl(CARD32 addr, CARD32 val); +#endif +extern void io_statistics(void); +extern void clear_stat(void); +extern int int_handler(int num, struct regs86 *regs); + +extern console open_console(void); +extern void close_console(console); + +extern void dprint(unsigned long start, unsigned long size); + +extern Bool logging; +extern Bool nostdout; +extern char* logfile; +extern void logon(void* ptr); +extern void logoff(); +extern void lprintf(const char *f, ...); + +#define MEM_FILE "/dev/mem" +#define DEFAULT_V_BIOS 0xc0000 +#ifndef V_BIOS +#define V_BIOS DEFAULT_V_BIOS +#endif + +#ifdef __alpha__ +#define NEED_PCI_IO +#endif + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/working_cards b/board/MAI/bios_emulator/scitech/src/v86bios/working_cards new file mode 100644 index 0000000..7753f24 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/working_cards @@ -0,0 +1,7 @@ +David Monro: Trident TGUI 9440 + Virge/VX (Diamond Stealth 3D 3400) + Riva TNT (Diamond Viper V550) no vbios? +Jarno Paananen : Guillemot Maxigamer Xentor 32 + (NVIDIA TNT2 Ultra) + Creative Graphics Blaster Exxtreme + (Permedia 2) diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c b/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c new file mode 100644 index 0000000..b5c99d7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c @@ -0,0 +1,316 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "debug.h" + +#define IF_MASK 0x00000200 +#define VIF_MASK 0x00080000 /* virtual interrupt flag */ +#define VIP_MASK 0x00100000 /* virtual interrupt pending */ + +#include +#include +#include +/*#include */ +#include +#include +#include +#include +#ifdef __alpha__ +#include +#endif +#include +#include +#include "AsmMacros.h" +#include "v86bios.h" +# define DEBUG +#include "x86emu.h" +#undef DEBUG + +#define M _X86EMU_env +#define CPU_REG(reg) M.x86.R_##reg + +struct pio P; + +void +setup_io(void) +{ + if (!Config.PrintPort && !Config.IoStatistics) { + +#if defined (__i386__) + P.inb = (u8(*)(u16))inb; + P.inw = (u16(*)(u16))inw; + P.outb = (void(*)(u16,u8))outb; + P.outw = (void(*)(u16,u16))outw; +#else + P.inb = p_inb; + P.inw = p_inw; + P.outb = p_outb; + P.outw = p_outw; +#endif +#if defined (__i386__) && ! defined(NEED_PCI_IO) + P.inl = (u32(*)(u16))inl; + P.outl = (void(*)(u16,u32))outl; +#else + P.inl = p_inl; + P.outl = p_outl; +#endif + } else { + P.inb = p_inb; + P.inw = p_inw; + P.inl = p_inl; + P.outb = p_outb; + P.outw = p_outw; + P.outl = p_outl; + } +} + +void +x86emu_do_int(int num) +{ + struct regs86 regs; + + i_printf("int 0x%x received: ax:0x%x",num,CPU_REG(AX)); + if (Config.PrintIp) + i_printf(" at: 0x%x\n",getIP()); + else + i_printf("\n"); + + /* try to run bios interrupt */ + + /* if not installed fall back */ +#define COPY(x,y) regs.y = M.x86.x +#define COPY_R(x,y) M.x86.x = regs.y + + COPY(R_EAX,eax); + COPY(R_EBX,ebx); + COPY(R_ECX,ecx); + COPY(R_EDX,edx); + COPY(R_ESI,esi); + COPY(R_EDI,edi); + COPY(R_EBP,ebp); + COPY(R_EIP,eip); + COPY(R_ESP,esp); + COPY(R_CS,cs); + COPY(R_SS,ss); + COPY(R_DS,ds); + COPY(R_ES,es); + COPY(R_FS,fs); + COPY(R_GS,gs); + COPY(R_EFLG,eflags); + + if (!(int_handler(num,®s))) { + if (!run_bios_int(num,®s)) + goto unknown_int; + else + return; + } + + COPY_R(R_EAX,eax); + COPY_R(R_EBX,ebx); + COPY_R(R_ECX,ecx); + COPY_R(R_EDX,edx); + COPY_R(R_ESI,esi); + COPY_R(R_EDI,edi); + COPY_R(R_EBP,ebp); + COPY_R(R_EIP,eip); + COPY_R(R_ESP,esp); + COPY_R(R_CS,cs); + COPY_R(R_SS,ss); + COPY_R(R_DS,ds); + COPY_R(R_ES,es); + COPY_R(R_FS,fs); + COPY_R(R_GS,gs); + COPY_R(R_EFLG,eflags); + return; + + unknown_int: + fprintf(stderr,"\nUnknown vm86_int: %X\n\n",num); + X86EMU_halt_sys(); + return; + +#undef COPY +#undef COPY_R +} + +void +setup_x86emu(unsigned long bios_start, i86biosRegsPtr regs) +{ + int i; + CARD32 eip; + CARD16 cs; + X86EMU_intrFuncs intFuncs[256]; + + X86EMU_pioFuncs pioFuncs = { + (u8(*)(u16))P.inb, + (u16(*)(u16))P.inw, + (u32(*)(u16))P.inl, + (void(*)(u16,u8))P.outb, + (void(*)(u16,u16))P.outw, + (void(*)(u16,u32))P.outl + }; +#ifdef __alpha__ + X86EMU_memFuncs memFuncs = { + (u8(*)(u32))mem_rb, + (u16(*)(u32))mem_rw, + (u32(*)(u32))mem_rl, + (void(*)(u32,u8))mem_wb, + (void(*)(u32,u16))mem_ww, + (void(*)(u32,u32))mem_wl + }; +#endif + M.mem_base = 0; + M.mem_size = 1024*1024 + 1024; + /* M.x86.debug = DEBUG_DISASSEMBLE_F | DEBUG_TRACE_F | DEBUG_DECODE_F; */ + /* M.x86.debug |= DEBUG_DECODE_F | DEBUG_TRACE_F; */ +/* + * For single step tracing compile x86emu with option -DDEBUG + */ + M.x86.debug = 0; + if (Config.PrintIp) + M.x86.debug = DEBUG_SAVE_CS_IP; + + if (Config.Trace) + X86EMU_trace_on(); + + X86EMU_setupPioFuncs(&pioFuncs); +#ifdef __alpha__ + X86EMU_setupMemFuncs(&memFuncs); +#endif + for (i=0;i<256;i++) + intFuncs[i] = x86emu_do_int; + X86EMU_setupIntrFuncs(intFuncs); + + eip = bios_start & 0xFFFF; + cs = (bios_start & 0xFF0000) >> 4; + + CPU_REG(EAX) = regs->ax; + CPU_REG(EBX) = regs->bx; + CPU_REG(ECX) = regs->cx; + CPU_REG(EDX) = regs->dx; + CPU_REG(ESI) = regs->si; + CPU_REG(EDI) = regs->di; + CPU_REG(EBP) = 0; + CPU_REG(EIP) = eip; + CPU_REG(CS) = cs; + CPU_REG(SP) = 0x100; + CPU_REG(SS) = 0x30; /* This is the standard pc bios stack */ + CPU_REG(ES) = regs->es; + CPU_REG(DS) = regs->ds; + CPU_REG(FS) = 0; + CPU_REG(GS) = 0; + CPU_REG(EFLG) |= (VIF_MASK | VIP_MASK | IF_MASK | 0x2); +} + +void +collect_bios_regs(i86biosRegsPtr regs) +{ + regs->ax = CPU_REG(EAX); + regs->bx = CPU_REG(EBX); + regs->cx = CPU_REG(ECX); + regs->dx = CPU_REG(EDX); + regs->es = CPU_REG(ES); + regs->ds = CPU_REG(DS); + regs->di = CPU_REG(EDI); + regs->si = CPU_REG(ESI); +} + +static void +do_x86emu(void) +{ + X86EMU_exec(); +} + +static jmp_buf x86_esc; +static void +vmexit(int unused) +{ + longjmp(x86_esc,1); +} + +void +do_x86(unsigned long bios_start, i86biosRegsPtr regs) +{ + static void (*org_handler)(int); + + setup_x86emu(bios_start,regs); + if (setjmp(x86_esc) == 0) { + org_handler = signal(2,vmexit); + do_x86emu(); + signal(2,org_handler); + collect_bios_regs(regs); + } else { + signal(2,org_handler); + printf("interrupted at 0x%x\n",((CARD16)CPU_REG(CS)) << 4 + | (CARD16)CPU_REG(EIP)); + } +} + +int +run_bios_int(int num, struct regs86 *regs) +{ +#ifdef V86BIOS_DEBUG + static int firsttime = 1; +#endif + /* check if bios vector is initialized */ + if (((CARD16*)0)[(num<<1)+1] == 0x0000) { /* SYS_BIOS_SEG ?*/ +#ifdef V86BIOS_DEBUG + i_printf("card BIOS not loaded\n"); +#endif + return 0; + } + +#ifdef V86BIOS_DEBUG + if (firsttime) { + dprint(0,0x3D0); + firsttime = 0; + } +#endif + + i_printf("calling card BIOS at: "); + i_printf("0x%x:%x\n",((CARD16 *) 0)[(num << 1) + 1], + (CARD32)((CARD16 *) 0)[num << 1]); + X86EMU_prepareForInt(num); + + return 1; +} + +CARD32 +getIntVect(int num) +{ + return ((CARD32*)0)[num]; +} +#if 0 +void +printk(const char *fmt, ...) +{ + va_list argptr; + va_start(argptr, fmt); + vfprintf(stdout, fmt, argptr); + fflush(stdout); + va_end(argptr); +} +#endif + +CARD32 +getIP(void) +{ + return (M.x86.saved_cs << 4) + M.x86.saved_ip; +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE b/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE new file mode 100644 index 0000000..a3ede4a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE @@ -0,0 +1,17 @@ + License information + ------------------- + +The x86emu library is under a BSD style license, comaptible +with the XFree86 and X licenses used by XFree86. The +original x86emu libraries were under the GNU General Public +License. Due to license incompatibilities between the GPL +and the XFree86 license, the original authors of the code +decided to allow a license change. If you have submitted +code to the original x86emu project, and you don't agree +with the license change, please contact us and let you +know. Your code will be removed to comply with your wishes. + +If you have any questions about this, please send email to +x86emu@linuxlabs.com or KendallB@scitechsoft.com for +clarification. + diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/debug.c b/board/MAI/bios_emulator/scitech/src/x86emu/debug.c new file mode 100644 index 0000000..235e6ac --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/debug.c @@ -0,0 +1,443 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to handle debugging of the +* emulator. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" +#include +#include + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef DEBUG + +static void print_encoded_bytes (u16 s, u16 o); +static void print_decoded_instruction (void); +static int parse_line (char *s, int *ps, int *n); + +/* should look something like debug's output. */ +void X86EMU_trace_regs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_regs(); + } + if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) { + printk("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); + } +} + +void X86EMU_trace_xregs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_xregs(); + } +} + +void x86emu_just_disassemble (void) +{ + /* + * This routine called if the flag DEBUG_DISASSEMBLE is set kind + * of a hack! + */ + printk("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); +} + +static void disassemble_forward (u16 seg, u16 off, int n) +{ + X86EMU_sysEnv tregs; + int i; + u8 op1; + /* + * hack, hack, hack. What we do is use the exact machinery set up + * for execution, except that now there is an additional state + * flag associated with the "execution", and we are using a copy + * of the register struct. All the major opcodes, once fully + * decoded, have the following two steps: TRACE_REGS(r,m); + * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to + * the preprocessor. The TRACE_REGS macro expands to: + * + * if (debug&DEBUG_DISASSEMBLE) + * {just_disassemble(); goto EndOfInstruction;} + * if (debug&DEBUG_TRACE) trace_regs(r,m); + * + * ...... and at the last line of the routine. + * + * EndOfInstruction: end_instr(); + * + * Up to the point where TRACE_REG is expanded, NO modifications + * are done to any register EXCEPT the IP register, for fetch and + * decoding purposes. + * + * This was done for an entirely different reason, but makes a + * nice way to get the system to help debug codes. + */ + tregs = M; + tregs.x86.R_IP = off; + tregs.x86.R_CS = seg; + + /* reset the decoding buffers */ + tregs.x86.enc_str_pos = 0; + tregs.x86.enc_pos = 0; + + /* turn on the "disassemble only, no execute" flag */ + tregs.x86.debug |= DEBUG_DISASSEMBLE_F; + + /* DUMP NEXT n instructions to screen in straight_line fashion */ + /* + * This looks like the regular instruction fetch stream, except + * that when this occurs, each fetched opcode, upon seeing the + * DEBUG_DISASSEMBLE flag set, exits immediately after decoding + * the instruction. XXX --- CHECK THAT MEM IS NOT AFFECTED!!! + * Note the use of a copy of the register structure... + */ + for (i=0; i 256) return; + seg = fetch_data_word_abs(0,iv*4); + off = fetch_data_word_abs(0,iv*4+2); + printk("%04x:%04x ", seg, off); +} + +void X86EMU_dump_memory (u16 seg, u16 off, u32 amt) +{ + u32 start = off & 0xfffffff0; + u32 end = (off+16) & 0xfffffff0; + u32 i; + u32 current; + + current = start; + while (end <= off + amt) { + printk("%04x:%04x ", seg, start); + for (i=start; i< off; i++) + printk(" "); + for ( ; i< end; i++) + printk("%02x ", fetch_data_byte_abs(seg,i)); + printk("\n"); + start = end; + end = start + 16; + } +} + +void x86emu_single_step (void) +{ + char s[1024]; + int ps[10]; + int ntok; + int cmd; + int done; + int segment; + int offset; + static int breakpoint; + static int noDecode = 1; + + char *p; + + if (DEBUG_BREAK()) { + if (M.x86.saved_ip != breakpoint) { + return; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + M.x86.debug |= DEBUG_TRACE_F; + M.x86.debug &= ~DEBUG_BREAK_F; + print_decoded_instruction (); + X86EMU_trace_regs(); + } + } + + done=0; + offset = M.x86.saved_ip; + while (!done) { + printk("-"); + /*p = fgets(s, 1023, stdin); */ + cons_gets(s); + cmd = parse_line(s, ps, &ntok); + switch(cmd) { + case 'u': + disassemble_forward(M.x86.saved_cs,(u16)offset,10); + break; + case 'd': + if (ntok == 2) { + segment = M.x86.saved_cs; + offset = ps[1]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else if (ntok == 3) { + segment = ps[1]; + offset = ps[2]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else { + segment = M.x86.saved_cs; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } + break; + case 'c': + M.x86.debug ^= DEBUG_TRACECALL_F; + break; + case 's': + M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; + break; + case 'r': + X86EMU_trace_regs(); + break; + case 'x': + X86EMU_trace_xregs(); + break; + case 'g': + if (ntok == 2) { + breakpoint = ps[1]; + printk("breakpoint set to 0x%X\n", breakpoint); + if (noDecode) { + M.x86.debug |= DEBUG_DECODE_NOPRINT_F; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + } + M.x86.debug &= ~DEBUG_TRACE_F; + M.x86.debug |= DEBUG_BREAK_F; + done = 1; + } + break; + case 'q': + M.x86.debug |= DEBUG_EXIT; + return; + case 'P': + noDecode = (noDecode)?0:1; + printk("Toggled decoding to %s\n",(noDecode)?"FALSE":"TRUE"); + break; + case 't': + case 0: + done = 1; + break; + } + } +} + +int X86EMU_trace_on(void) +{ + return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F; +} + +int X86EMU_trace_off(void) +{ + return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); +} + +static int parse_line (char *s, int *ps, int *n) +{ + int cmd; + + *n = 0; + while(*s == ' ' || *s == '\t') s++; + ps[*n] = *s; + switch (*s) { + case '\n': + *n += 1; + return 0; + default: + cmd = *s; + *n += 1; + } + + while (1) { + while (*s != ' ' && *s != '\t' && *s != '\n') s++; + + if (*s == '\n') + return cmd; + + while(*s == ' ' || *s == '\t') s++; + + ps[*n]=atoi(s); + /*sscanf(s,"%x",&ps[*n]); */ + *n += 1; + } +} + +#endif /* DEBUG */ + +void x86emu_dump_stack(void) +{ + int i; + printk("Stack: "); + for (i = 0; i<16; i++) + { + u8 x = fetch_data_byte_abs(M.x86.R_SS, M.x86.R_SP + i); + printk("%02x ", (int)x); + } + printk("\n"); +} + +void x86emu_dump_regs (void) +{ + printk("\tAX=%04x ", M.x86.R_AX ); + printk("BX=%04x ", M.x86.R_BX ); + printk("CX=%04x ", M.x86.R_CX ); + printk("DX=%04x ", M.x86.R_DX ); + printk("SP=%04x ", M.x86.R_SP ); + printk("BP=%04x ", M.x86.R_BP ); + printk("SI=%04x ", M.x86.R_SI ); + printk("DI=%04x\n", M.x86.R_DI ); + printk("\tDS=%04x ", M.x86.R_DS ); + printk("ES=%04x ", M.x86.R_ES ); + printk("SS=%04x ", M.x86.R_SS ); + printk("CS=%04x ", M.x86.R_CS ); + printk("IP=%04x ", M.x86.R_IP ); + if (ACCESS_FLAG(F_OF)) printk("OV "); /* CHECKED... */ + else printk("NV "); + if (ACCESS_FLAG(F_DF)) printk("DN "); + else printk("UP "); + if (ACCESS_FLAG(F_IF)) printk("EI "); + else printk("DI "); + if (ACCESS_FLAG(F_SF)) printk("NG "); + else printk("PL "); + if (ACCESS_FLAG(F_ZF)) printk("ZR "); + else printk("NZ "); + if (ACCESS_FLAG(F_AF)) printk("AC "); + else printk("NA "); + if (ACCESS_FLAG(F_PF)) printk("PE "); + else printk("PO "); + if (ACCESS_FLAG(F_CF)) printk("CY "); + else printk("NC "); + printk("\n"); + /*x86emu_dump_stack(); */ +} + +void x86emu_dump_xregs (void) +{ + printk("\tEAX=%08x ", M.x86.R_EAX ); + printk("EBX=%08x ", M.x86.R_EBX ); + printk("ECX=%08x ", M.x86.R_ECX ); + printk("EDX=%08x \n", M.x86.R_EDX ); + printk("\tESP=%08x ", M.x86.R_ESP ); + printk("EBP=%08x ", M.x86.R_EBP ); + printk("ESI=%08x ", M.x86.R_ESI ); + printk("EDI=%08x\n", M.x86.R_EDI ); + printk("\tDS=%04x ", M.x86.R_DS ); + printk("ES=%04x ", M.x86.R_ES ); + printk("SS=%04x ", M.x86.R_SS ); + printk("CS=%04x ", M.x86.R_CS ); + printk("EIP=%08x\n\t", M.x86.R_EIP ); + if (ACCESS_FLAG(F_OF)) printk("OV "); /* CHECKED... */ + else printk("NV "); + if (ACCESS_FLAG(F_DF)) printk("DN "); + else printk("UP "); + if (ACCESS_FLAG(F_IF)) printk("EI "); + else printk("DI "); + if (ACCESS_FLAG(F_SF)) printk("NG "); + else printk("PL "); + if (ACCESS_FLAG(F_ZF)) printk("ZR "); + else printk("NZ "); + if (ACCESS_FLAG(F_AF)) printk("AC "); + else printk("NA "); + if (ACCESS_FLAG(F_PF)) printk("PE "); + else printk("PO "); + if (ACCESS_FLAG(F_CF)) printk("CY "); + else printk("NC "); + printk("\n"); +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/decode.c b/board/MAI/bios_emulator/scitech/src/x86emu/decode.c new file mode 100644 index 0000000..832b1f5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/decode.c @@ -0,0 +1,970 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* instruction decoding and accessess of immediate data via IP. etc. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Handles any pending asychronous interrupts. +****************************************************************************/ +static void x86emu_intr_handle(void) +{ + u8 intno; + + if (M.x86.intr & INTR_SYNCH) { + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } + } +} + +/**************************************************************************** +PARAMETERS: +intrnum - Interrupt number to raise + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. +****************************************************************************/ +void x86emu_intr_raise( + u8 intrnum) +{ + M.x86.intno = intrnum; + M.x86.intr |= INTR_SYNCH; +} + +/**************************************************************************** +REMARKS: +Main execution loop for the emulator. We return from here when the system +halts, which is normally caused by a stack fault when we return from the +original real mode call. +****************************************************************************/ +void X86EMU_exec(void) +{ + u8 op1; + + M.x86.intr = 0; + DB(x86emu_end_instr();) + + for (;;) { + DB(if (CHECK_IP_FETCH()) x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { + DB( printk("halted\n"); X86EMU_trace_regs();) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + if (M.x86.debug & DEBUG_EXIT) { + M.x86.debug &= ~DEBUG_EXIT; + return; + } + } +} + +/**************************************************************************** +REMARKS: +Halts the system by setting the halted system flag. +****************************************************************************/ +void X86EMU_halt_sys(void) +{ + M.x86.intr |= INTR_HALTED; +} + +/**************************************************************************** +PARAMETERS: +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +void fetch_decode_modrm( + int *mod, + int *regh, + int *regl) +{ + int fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + *mod = (fetched >> 6) & 0x03; + *regh = (fetched >> 3) & 0x07; + *regl = (fetched >> 0) & 0x07; +} + +/**************************************************************************** +RETURNS: +Immediate byte value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +u8 fetch_byte_imm(void) +{ + u8 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate word value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u16 fetch_word_imm(void) +{ + u16 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 2; + INC_DECODED_INST_LEN(2); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate lone value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u32 fetch_long_imm(void) +{ + u32 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 4; + INC_DECODED_INST_LEN(4); + return fetched; +} + +/**************************************************************************** +RETURNS: +Value of the default data segment + +REMARKS: +Inline function that returns the default data segment for the current +instruction. + +On the x86 processor, the default segment is not always DS if there is +no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to +addresses relative to SS (ie: on the stack). So, at the minimum, all +decodings of addressing modes would have to set/clear a bit describing +whether the access is relative to DS or SS. That is the function of the +cpu-state-varible M.x86.mode. There are several potential states: + + repe prefix seen (handled elsewhere) + repne prefix seen (ditto) + + cs segment override + ds segment override + es segment override + fs segment override + gs segment override + ss segment override + + ds/ss select (in absense of override) + +Each of the above 7 items are handled with a bit in the mode field. +****************************************************************************/ +_INLINE u32 get_data_segment(void) +{ +#define GET_SEGMENT(segment) + switch (M.x86.mode & SYSMODE_SEGMASK) { + case 0: /* default case: use ds register */ + case SYSMODE_SEGOVR_DS: + case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; + case SYSMODE_SEGOVR_CS: + case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: + return M.x86.R_CS; + case SYSMODE_SEGOVR_ES: + case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: + return M.x86.R_ES; + case SYSMODE_SEGOVR_FS: + case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: + return M.x86.R_FS; + case SYSMODE_SEGOVR_GS: + case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: + return M.x86.R_GS; + case SYSMODE_SEGOVR_SS: + case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: + return M.x86.R_SS; + default: +#ifdef DEBUG + printk("error: should not happen: multiple overrides.\n"); +#endif + HALT_SYS(); + return 0; + } +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte( + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdb)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word( + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdw)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long( + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdl)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte_abs( + uint segment, + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdb)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word_abs( + uint segment, + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdw)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long_abs( + uint segment, + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdl)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte( + uint offset, + u8 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrb)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word( + uint offset, + u16 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrw)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long( + uint offset, + u32 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrl)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a byte value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte_abs( + uint segment, + uint offset, + u8 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrb)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word_abs( + uint segment, + uint offset, + u16 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrw)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long_abs( + uint segment, + uint offset, + u32 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrl)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for byte operands. Also enables the decoding of instructions. +****************************************************************************/ +u8* decode_rm_byte_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AL"); + return &M.x86.R_AL; + case 1: + DECODE_PRINTF("CL"); + return &M.x86.R_CL; + case 2: + DECODE_PRINTF("DL"); + return &M.x86.R_DL; + case 3: + DECODE_PRINTF("BL"); + return &M.x86.R_BL; + case 4: + DECODE_PRINTF("AH"); + return &M.x86.R_AH; + case 5: + DECODE_PRINTF("CH"); + return &M.x86.R_CH; + case 6: + DECODE_PRINTF("DH"); + return &M.x86.R_DH; + case 7: + DECODE_PRINTF("BH"); + return &M.x86.R_BH; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_word_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AX"); + return &M.x86.R_AX; + case 1: + DECODE_PRINTF("CX"); + return &M.x86.R_CX; + case 2: + DECODE_PRINTF("DX"); + return &M.x86.R_DX; + case 3: + DECODE_PRINTF("BX"); + return &M.x86.R_BX; + case 4: + DECODE_PRINTF("SP"); + return &M.x86.R_SP; + case 5: + DECODE_PRINTF("BP"); + return &M.x86.R_BP; + case 6: + DECODE_PRINTF("SI"); + return &M.x86.R_SI; + case 7: + DECODE_PRINTF("DI"); + return &M.x86.R_DI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for dword operands. Also enables the decoding of instructions. +****************************************************************************/ +u32* decode_rm_long_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; + case 1: + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; + case 2: + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; + case 3: + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; + case 4: + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; + case 5: + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; + case 6: + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; + case 7: + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands, modified from above for the weirdo +special case of segreg operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_seg_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("ES"); + return &M.x86.R_ES; + case 1: + DECODE_PRINTF("CS"); + return &M.x86.R_CS; + case 2: + DECODE_PRINTF("SS"); + return &M.x86.R_SS; + case 3: + DECODE_PRINTF("DS"); + return &M.x86.R_DS; + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF("ILLEGAL SEGREG"); + break; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=00 addressing. Also enables the +decoding of instructions. + +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). +****************************************************************************/ +unsigned decode_rm00_address( + int rm) +{ + unsigned offset; + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) + { + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); +/* M.x86.mode |= SYSMODE_SEG_DS_SS; */ + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); +/* M.x86.mode |= SYSMODE_SEG_DS_SS; */ + return M.x86.R_EBX; + case 4: + printk("Unsupported SIB encoding\n"); + HALT_SYS(); + return 0; + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } + } + else + { + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return M.x86.R_BX + M.x86.R_SI; + case 1: + DECODE_PRINTF("[BX+DI]"); + return M.x86.R_BX + M.x86.R_DI; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + M.x86.R_SI; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + M.x86.R_DI; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } + } + HALT_SYS(); + return 0; +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=01 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +unsigned decode_rm01_address( + int rm) +{ + int displacement = (s8)fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_ADDR) + { + switch (rm) + { + case 0: + DECODE_PRINTF2("%d[EAX}", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + printk("Unsupported SIB addressing mode\n"); + HALT_SYS(); + return 0; + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + } + else + { + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return M.x86.R_BX + M.x86.R_SI + displacement; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return M.x86.R_BX + M.x86.R_DI + displacement; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + M.x86.R_SI + displacement; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + M.x86.R_DI + displacement; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return M.x86.R_SI + displacement; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return M.x86.R_DI + displacement; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + displacement; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return M.x86.R_BX + displacement; + } + HALT_SYS(); + } + return 0; /* SHOULD NOT HAPPEN */ +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=10 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +unsigned decode_rm10_address( + int rm) +{ + if (M.x86.mode & SYSMODE_PREFIX_ADDR) + { + int displacement = (s32)fetch_long_imm(); + switch (rm) + { + case 0: + DECODE_PRINTF2("%d[EAX}", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + printk("Unsupported SIB addressing mode\n"); + HALT_SYS(); + return 0; + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + } + else + { + int displacement = (s16)fetch_word_imm(); + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + } + HALT_SYS(); + return 0; + /*NOTREACHED */ +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c b/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c new file mode 100644 index 0000000..7f7c345 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c @@ -0,0 +1,945 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the decoding and +* emulation of the FPU instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/* opcode=0xd8 */ +void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ESC D8\n"); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +static char *x86emu_fpu_op_d9_tab[] = { + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", +}; + +static char *x86emu_fpu_op_d9_tab1[] = { + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + + "FNOP", "ESC_D9", "ESC_D9", "ESC_D9", + "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", + + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + + "FCHS", "FABS", "ESC_D9", "ESC_D9", + "FTST", "FXAM", "ESC_D9", "ESC_D9", + + "FLD1", "FLDL2T", "FLDL2E", "FLDPI", + "FLDLG2", "FLDLN2", "FLDZ", "ESC_D9", + + "F2XM1", "FYL2X", "FPTAN", "FPATAN", + "FXTRACT", "ESC_D9", "FDECSTP", "FINCSTP", + + "FPREM", "FYL2XP1", "FSQRT", "ESC_D9", + "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", +}; + +#endif /* DEBUG */ + +/* opcode=0xd9 */ +void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); + } else { + DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + if (rh < 4) { + DECODE_PRINTF2("ST(%d)\n", stkelem); + } else { + DECODE_PRINTF("\n"); + } + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); + break; + case 1: + x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); + break; + case 2: + switch (rl) { + case 0: + x86emu_fpu_R_nop(); + break; + default: + x86emu_fpu_illegal(); + break; + } + case 3: + x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); + break; + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); + break; + default: + /* 2,3,6,7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 5: + switch (rl) { + case 0: + x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); + break; + default: + /* 7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 6: + switch (rl) { + case 0: + x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_R_decstp(); + break; + case 7: + x86emu_fpu_R_incstp(); + break; + } + break; + + case 7: + switch (rl) { + case 0: + x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); + break; + case 6: + case 7: + default: + x86emu_fpu_illegal(); + break; + } + break; + + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); + break; + case 4: + x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); + break; + } + } + } +#endif /* X86EMU_FPU_PRESENT */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +char *x86emu_fpu_op_da_tab[] = { + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", +}; + +#endif /* DEBUG */ + +/* opcode=0xda */ +void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + x86emu_fpu_illegal(); + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); + break; + case 2: + x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); + break; + case 5: + x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); + break; + case 6: + x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); + break; + case 7: + x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +char *x86emu_fpu_op_db_tab[] = { + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", +}; + +#endif /* DEBUG */ + +/* opcode=0xdb */ +void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); + } else if (rh == 4) { /* === 11 10 0 nnn */ + switch (rl) { + case 0: + DECODE_PRINTF("FENI\n"); + break; + case 1: + DECODE_PRINTF("FDISI\n"); + break; + case 2: + DECODE_PRINTF("FCLEX\n"); + break; + case 3: + DECODE_PRINTF("FINIT\n"); + break; + } + } else { + DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); + } +#endif /* DEBUG */ + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + break; + case 1: + destoffset = decode_rm01_address(rl); + break; + case 2: + destoffset = decode_rm10_address(rl); + break; + case 3: /* register to register */ + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_feni(); + break; + case 1: + x86emu_fpu_R_fdisi(); + break; + case 2: + x86emu_fpu_R_fclex(); + break; + case 3: + x86emu_fpu_R_finit(); + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_illegal(); + break; + case 5: + x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); + break; + case 6: + x86emu_fpu_illegal(); + break; + case 7: + x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG +char *x86emu_fpu_op_dc_tab[] = { + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", + "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", +}; +#endif /* DEBUG */ + +/* opcode=0xdc */ +void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); + break; + case 2: + x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); + break; + case 5: + x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); + break; + case 6: + x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); + break; + case 7: + x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +static char *x86emu_fpu_op_dd_tab[] = { + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", +}; + +#endif /* DEBUG */ + +/* opcode=0xdd */ +void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +static char *x86emu_fpu_op_de_tab[] = +{ + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FADDP\t", "FMULP\t", "FCOMP\t", "FCOMPP\t", + "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", +}; + +#endif /* DEBUG */ + +/* opcode=0xde */ +void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + if (stkelem == 1) + x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); + else + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); + break; + case 2: + x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +static char *x86emu_fpu_op_df_tab[] = { + /* mod == 00 */ + "FILD\tWORD PTR ", "ESC_DF\t39\n", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 01 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 10 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 11 */ + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," +}; + +#endif /* DEBUG */ + +/* opcode=0xdf */ +void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d)\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); + break; + case 5: + x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); + break; + case 6: + x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); + break; + case 7: + x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile b/board/MAI/bios_emulator/scitech/src/x86emu/makefile new file mode 100644 index 0000000..8ce2e9e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile @@ -0,0 +1,63 @@ +############################################################################# +# +# Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Generic makefile for the x86emu library. Requires +# the SciTech Software makefile definitions package to be +# installed, which uses the DMAKE make program. +# +############################################################################# + +.IMPORT .IGNORE: DEBUG + +#---------------------------------------------------------------------------- +# Define the lists of object files +#---------------------------------------------------------------------------- + +OBJECTS = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O +CFLAGS += -DSCITECH +.IF $(DEBUG) +CFLAGS += -DDEBUG +.ENDIF +LIBCLEAN = *.dll *.lib *.a +LIBFILE = $(LP)x86emu$L + +#---------------------------------------------------------------------------- +# Sample test programs +#---------------------------------------------------------------------------- + +all: $(LIBFILE) + +validate$E: validate$O $(LIBFILE) + +#---------------------------------------------------------------------------- +# Define the list of object files to create dependency information for +#---------------------------------------------------------------------------- + +DEPEND_OBJ = validate$O $(OBJECTS) + +.INCLUDE: "$(SCITECH)/makedefs/common.mk" diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross new file mode 100644 index 0000000..0bce9a9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross @@ -0,0 +1,82 @@ +############################################################################# +# +# Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Linux specific makefile for the x86emu library. +# +############################################################################# + +CC = $(CROSS_COMPILE)gcc +AR = $(CROSS_COMPILE)ar + +TARGETLIB = libx86emu.a +TARGETDEBUGLIB =libx86emud.a + +OBJS=\ +decode.o \ +fpu.o \ +ops.o \ +ops2.o \ +prim_ops.o \ +sys.o + +DEBUGOBJS=debug.d \ + decode.d \ + fpu.d \ + ops.d \ + ops2.d \ + prim_ops.d \ + sys.d + +.SUFFIXES: .d + +all: $(TARGETLIB) $(TARGETDEBUGLIB) + +$(TARGETLIB): $(OBJS) + $(AR) rv $(TARGETLIB) $(OBJS) + +$(TARGETDEBUGLIB): $(DEBUGOBJS) + $(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS) + +INCS = -I. -Ix86emu -I../../include +CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -fPIC -ffixed-r14 -meabi +CDEBUGFLAGS = -DDEBUG + +.c.o: + $(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c + +.c.d: + $(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c + +.cpp.o: + $(CC) -c $(CFLAGS) $(INCS) $*.cpp + +clean: + rm -f *.a *.o *.d + +validate: validate.o libx86emu.a + $(CC) -o validate validate.o -lx86emu -L. diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux new file mode 100644 index 0000000..f74b88d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux @@ -0,0 +1,81 @@ +############################################################################# +# +# Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Linux specific makefile for the x86emu library. +# +############################################################################# + +TARGETLIB = libx86emu.a +TARGETDEBUGLIB =libx86emud.a + +OBJS=\ +decode.o \ +fpu.o \ +ops.o \ +ops2.o \ +prim_ops.o \ +pregs.o \ +sys.o + +DEBUGOBJS=debug.d \ + decode.d \ + fpu.d \ + ops.d \ + ops2.d \ + prim_ops.d \ + pregs.d \ + sys.d + +.SUFFIXES: .d + +all: $(TARGETLIB) $(TARGETDEBUGLIB) + +$(TARGETLIB): $(OBJS) + ar rv $(TARGETLIB) $(OBJS) + +$(TARGETDEBUGLIB): $(DEBUGOBJS) + ar rv $(TARGETDEBUGLIB) $(DEBUGOBJS) + +INCS = -I. -Ix86emu -I../../include +CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG +CDEBUGFLAGS = -DDEBUG + +.c.o: + gcc -g -O -Wall -c $(CFLAGS) $(INCS) $*.c + +.c.d: + gcc -g -O -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c + +.cpp.o: + gcc -c $(CFLAGS) $(INCS) $*.cpp + +clean: + rm -f *.a *.o *.d + +validate: validate.o libx86emu.a + gcc -o validate validate.o -lx86emu -L. diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot new file mode 100644 index 0000000..af9ae1f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot @@ -0,0 +1,80 @@ +############################################################################# +# +# Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Linux specific makefile for the x86emu library. +# +############################################################################# +CC = $(CROSS_COMPILE)gcc +AR = $(CROSS_COMPILE)ar +TARGETLIB = libx86emu.a +TARGETDEBUGLIB =libx86emud.a + +OBJS=\ +decode.o \ +fpu.o \ +ops.o \ +ops2.o \ +prim_ops.o \ +sys.o + +DEBUGOBJS=debug.d \ + decode.d \ + fpu.d \ + ops.d \ + ops2.d \ + prim_ops.d \ + sys.d + +.SUFFIXES: .d + +all: $(TARGETLIB) $(TARGETDEBUGLIB) + +$(TARGETLIB): $(OBJS) + $(AR) rv $(TARGETLIB) $(OBJS) + +$(TARGETDEBUGLIB): $(DEBUGOBJS) + $(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS) + +INCS = -I. -Ix86emu -I../../include +CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -fPIC -ffixed-r14 -meabi +CDEBUGFLAGS = -DDEBUG + +.c.o: + $(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c + +.c.d: + $(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c + +.cpp.o: + $(CC) -c $(CFLAGS) $(INCS) $*.cpp + +clean: + rm -f *.a *.o *.d + +validate: validate.o libx86emu.a + $(CC) -o validate validate.o -lx86emu -L. diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/ops.c b/board/MAI/bios_emulator/scitech/src/x86emu/ops.c new file mode 100644 index 0000000..2d4f93e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/ops.c @@ -0,0 +1,11701 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 processor instructions. +* +* There are approximately 250 subroutines in here, which correspond +* to the 256 byte-"opcodes" found on the 8086. The table which +* dispatches this is found in the files optab.[ch]. +* +* Each opcode proc has a comment preceeding it which gives it's table +* address. Several opcodes are missing (undefined) in the table. +* +* Each proc includes information for decoding (DECODE_PRINTF and +* DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc +* functions (START_OF_INSTR, END_OF_INSTR). +* +* Many of the procedures are *VERY* similar in coding. This has +* allowed for a very large amount of code to be generated in a fairly +* short amount of time (i.e. cut, paste, and modify). The result is +* that much of the code below could have been folded into subroutines +* for a large reduction in size of this file. The downside would be +* that there would be a penalty in execution speed. The file could +* also have been *MUCH* larger by inlining certain functions which +* were called. This could have resulted even faster execution. The +* prime directive I used to decide whether to inline the code or to +* modularize it, was basically: 1) no unnecessary subroutine calls, +* 2) no routines more than about 200 lines in size, and 3) modularize +* any code that I might not get right the first time. The fetch_* +* subroutines fall into the latter category. The The decode_* fall +* into the second category. The coding of the "switch(mod){ .... }" +* in many of the subroutines below falls into the first category. +* Especially, the coding of {add,and,or,sub,...}_{byte,word} +* subroutines are an especially glaring case of the third guideline. +* Since so much of the code is cloned from other modules (compare +* opcode #00 to opcode #01), making the basic operations subroutine +* calls is especially important; otherwise mistakes in coding an +* "add" would represent a nightmare in maintenance. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +void x86emuOp_illegal_op( + u8 op1) +{ + START_OF_INSTR(); + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-1,op1); + HALT_SYS(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x00 +****************************************************************************/ +void x86emuOp_add_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x01 +****************************************************************************/ +void x86emuOp_add_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x02 +****************************************************************************/ +void x86emuOp_add_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x03 +****************************************************************************/ +void x86emuOp_add_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x04 +****************************************************************************/ +void x86emuOp_add_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = add_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x05 +****************************************************************************/ +void x86emuOp_add_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADD\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADD\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = add_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = add_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x06 +****************************************************************************/ +void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tES\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_ES); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x07 +****************************************************************************/ +void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tES\n"); + TRACE_AND_STEP(); + M.x86.R_ES = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x08 +****************************************************************************/ +void x86emuOp_or_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x09 +****************************************************************************/ +void x86emuOp_or_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0a +****************************************************************************/ +void x86emuOp_or_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0b +****************************************************************************/ +void x86emuOp_or_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0c +****************************************************************************/ +void x86emuOp_or_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = or_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0d +****************************************************************************/ +void x86emuOp_or_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("OR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = or_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = or_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0e +****************************************************************************/ +void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tCS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f. Escape for two-byte opcode (286 or better) +****************************************************************************/ +void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + (*x86emu_optab2[op2])(op2); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x10 +****************************************************************************/ +void x86emuOp_adc_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x11 +****************************************************************************/ +void x86emuOp_adc_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x12 +****************************************************************************/ +void x86emuOp_adc_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x13 +****************************************************************************/ +void x86emuOp_adc_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x14 +****************************************************************************/ +void x86emuOp_adc_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = adc_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x15 +****************************************************************************/ +void x86emuOp_adc_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADC\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADC\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = adc_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = adc_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x16 +****************************************************************************/ +void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tSS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_SS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x17 +****************************************************************************/ +void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tSS\n"); + TRACE_AND_STEP(); + M.x86.R_SS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x18 +****************************************************************************/ +void x86emuOp_sbb_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x19 +****************************************************************************/ +void x86emuOp_sbb_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1a +****************************************************************************/ +void x86emuOp_sbb_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1b +****************************************************************************/ +void x86emuOp_sbb_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1c +****************************************************************************/ +void x86emuOp_sbb_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sbb_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1d +****************************************************************************/ +void x86emuOp_sbb_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SBB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SBB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sbb_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sbb_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1e +****************************************************************************/ +void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tDS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_DS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1f +****************************************************************************/ +void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tDS\n"); + TRACE_AND_STEP(); + M.x86.R_DS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x20 +****************************************************************************/ +void x86emuOp_and_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x21 +****************************************************************************/ +void x86emuOp_and_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x22 +****************************************************************************/ +void x86emuOp_and_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x23 +****************************************************************************/ +void x86emuOp_and_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + break; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + break; + } + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x24 +****************************************************************************/ +void x86emuOp_and_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = and_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x25 +****************************************************************************/ +void x86emuOp_and_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("AND\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("AND\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = and_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = and_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x26 +****************************************************************************/ +void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ES:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_ES; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x27 +****************************************************************************/ +void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAA\n"); + TRACE_AND_STEP(); + M.x86.R_AL = daa_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x28 +****************************************************************************/ +void x86emuOp_sub_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x29 +****************************************************************************/ +void x86emuOp_sub_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2a +****************************************************************************/ +void x86emuOp_sub_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2b +****************************************************************************/ +void x86emuOp_sub_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2c +****************************************************************************/ +void x86emuOp_sub_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sub_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2d +****************************************************************************/ +void x86emuOp_sub_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SUB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SUB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sub_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sub_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2e +****************************************************************************/ +void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("CS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_CS; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2f +****************************************************************************/ +void x86emuOp_das(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAS\n"); + TRACE_AND_STEP(); + M.x86.R_AL = das_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x30 +****************************************************************************/ +void x86emuOp_xor_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x31 +****************************************************************************/ +void x86emuOp_xor_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x32 +****************************************************************************/ +void x86emuOp_xor_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x33 +****************************************************************************/ +void x86emuOp_xor_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x34 +****************************************************************************/ +void x86emuOp_xor_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = xor_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x35 +****************************************************************************/ +void x86emuOp_xor_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XOR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("XOR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = xor_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = xor_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x36 +****************************************************************************/ +void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_SS; + /* no DECODE_CLEAR_SEGOVR ! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x37 +****************************************************************************/ +void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAA\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aaa_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x38 +****************************************************************************/ +void x86emuOp_cmp_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x39 +****************************************************************************/ +void x86emuOp_cmp_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3a +****************************************************************************/ +void x86emuOp_cmp_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3b +****************************************************************************/ +void x86emuOp_cmp_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3c +****************************************************************************/ +void x86emuOp_cmp_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + cmp_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3d +****************************************************************************/ +void x86emuOp_cmp_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMP\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("CMP\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + cmp_long(M.x86.R_EAX, srcval); + } else { + cmp_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3e +****************************************************************************/ +void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_DS; + /* NO DECODE_CLEAR_SEGOVR! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3f +****************************************************************************/ +void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAS\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aas_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x40 +****************************************************************************/ +void x86emuOp_inc_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEAX\n"); + } else { + DECODE_PRINTF("INC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = inc_long(M.x86.R_EAX); + } else { + M.x86.R_AX = inc_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x41 +****************************************************************************/ +void x86emuOp_inc_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tECX\n"); + } else { + DECODE_PRINTF("INC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = inc_long(M.x86.R_ECX); + } else { + M.x86.R_CX = inc_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x42 +****************************************************************************/ +void x86emuOp_inc_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDX\n"); + } else { + DECODE_PRINTF("INC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = inc_long(M.x86.R_EDX); + } else { + M.x86.R_DX = inc_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x43 +****************************************************************************/ +void x86emuOp_inc_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBX\n"); + } else { + DECODE_PRINTF("INC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = inc_long(M.x86.R_EBX); + } else { + M.x86.R_BX = inc_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x44 +****************************************************************************/ +void x86emuOp_inc_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESP\n"); + } else { + DECODE_PRINTF("INC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = inc_long(M.x86.R_ESP); + } else { + M.x86.R_SP = inc_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x45 +****************************************************************************/ +void x86emuOp_inc_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBP\n"); + } else { + DECODE_PRINTF("INC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = inc_long(M.x86.R_EBP); + } else { + M.x86.R_BP = inc_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x46 +****************************************************************************/ +void x86emuOp_inc_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESI\n"); + } else { + DECODE_PRINTF("INC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = inc_long(M.x86.R_ESI); + } else { + M.x86.R_SI = inc_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x47 +****************************************************************************/ +void x86emuOp_inc_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDI\n"); + } else { + DECODE_PRINTF("INC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = inc_long(M.x86.R_EDI); + } else { + M.x86.R_DI = inc_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x48 +****************************************************************************/ +void x86emuOp_dec_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEAX\n"); + } else { + DECODE_PRINTF("DEC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = dec_long(M.x86.R_EAX); + } else { + M.x86.R_AX = dec_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x49 +****************************************************************************/ +void x86emuOp_dec_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tECX\n"); + } else { + DECODE_PRINTF("DEC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = dec_long(M.x86.R_ECX); + } else { + M.x86.R_CX = dec_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4a +****************************************************************************/ +void x86emuOp_dec_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDX\n"); + } else { + DECODE_PRINTF("DEC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = dec_long(M.x86.R_EDX); + } else { + M.x86.R_DX = dec_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4b +****************************************************************************/ +void x86emuOp_dec_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBX\n"); + } else { + DECODE_PRINTF("DEC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = dec_long(M.x86.R_EBX); + } else { + M.x86.R_BX = dec_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4c +****************************************************************************/ +void x86emuOp_dec_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESP\n"); + } else { + DECODE_PRINTF("DEC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = dec_long(M.x86.R_ESP); + } else { + M.x86.R_SP = dec_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4d +****************************************************************************/ +void x86emuOp_dec_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBP\n"); + } else { + DECODE_PRINTF("DEC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = dec_long(M.x86.R_EBP); + } else { + M.x86.R_BP = dec_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4e +****************************************************************************/ +void x86emuOp_dec_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESI\n"); + } else { + DECODE_PRINTF("DEC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = dec_long(M.x86.R_ESI); + } else { + M.x86.R_SI = dec_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4f +****************************************************************************/ +void x86emuOp_dec_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDI\n"); + } else { + DECODE_PRINTF("DEC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = dec_long(M.x86.R_EDI); + } else { + M.x86.R_DI = dec_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x50 +****************************************************************************/ +void x86emuOp_push_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEAX\n"); + } else { + DECODE_PRINTF("PUSH\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EAX); + } else { + push_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x51 +****************************************************************************/ +void x86emuOp_push_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tECX\n"); + } else { + DECODE_PRINTF("PUSH\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ECX); + } else { + push_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x52 +****************************************************************************/ +void x86emuOp_push_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDX\n"); + } else { + DECODE_PRINTF("PUSH\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDX); + } else { + push_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x53 +****************************************************************************/ +void x86emuOp_push_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBX\n"); + } else { + DECODE_PRINTF("PUSH\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBX); + } else { + push_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x54 +****************************************************************************/ +void x86emuOp_push_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESP\n"); + } else { + DECODE_PRINTF("PUSH\tSP\n"); + } + TRACE_AND_STEP(); + /* Always push (E)SP, since we are emulating an i386 and above + * processor. This is necessary as some BIOS'es use this to check + * what type of processor is in the system. + */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESP); + } else { + push_word((u16)(M.x86.R_SP)); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x55 +****************************************************************************/ +void x86emuOp_push_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBP\n"); + } else { + DECODE_PRINTF("PUSH\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBP); + } else { + push_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x56 +****************************************************************************/ +void x86emuOp_push_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESI\n"); + } else { + DECODE_PRINTF("PUSH\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESI); + } else { + push_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x57 +****************************************************************************/ +void x86emuOp_push_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDI\n"); + } else { + DECODE_PRINTF("PUSH\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDI); + } else { + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x58 +****************************************************************************/ +void x86emuOp_pop_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEAX\n"); + } else { + DECODE_PRINTF("POP\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x59 +****************************************************************************/ +void x86emuOp_pop_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tECX\n"); + } else { + DECODE_PRINTF("POP\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = pop_long(); + } else { + M.x86.R_CX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5a +****************************************************************************/ +void x86emuOp_pop_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDX\n"); + } else { + DECODE_PRINTF("POP\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = pop_long(); + } else { + M.x86.R_DX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5b +****************************************************************************/ +void x86emuOp_pop_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBX\n"); + } else { + DECODE_PRINTF("POP\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = pop_long(); + } else { + M.x86.R_BX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5c +****************************************************************************/ +void x86emuOp_pop_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESP\n"); + } else { + DECODE_PRINTF("POP\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = pop_long(); + } else { + M.x86.R_SP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5d +****************************************************************************/ +void x86emuOp_pop_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBP\n"); + } else { + DECODE_PRINTF("POP\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = pop_long(); + } else { + M.x86.R_BP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5e +****************************************************************************/ +void x86emuOp_pop_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESI\n"); + } else { + DECODE_PRINTF("POP\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = pop_long(); + } else { + M.x86.R_SI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5f +****************************************************************************/ +void x86emuOp_pop_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDI\n"); + } else { + DECODE_PRINTF("POP\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + } else { + M.x86.R_DI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x60 +****************************************************************************/ +void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHAD\n"); + } else { + DECODE_PRINTF("PUSHA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); + } else { + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x61 +****************************************************************************/ +void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPAD\n"); + } else { + DECODE_PRINTF("POPA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ + +/**************************************************************************** +REMARKS: +Handles opcode 0x64 +****************************************************************************/ +void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("FS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_FS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x65 +****************************************************************************/ +void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("GS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_GS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x66 - prefix for 32-bit register +****************************************************************************/ +void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DATA:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_DATA; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x67 - prefix for 32-bit address +****************************************************************************/ +void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ADDR:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_ADDR; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x68 +****************************************************************************/ +void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 imm; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + imm = fetch_long_imm(); + } else { + imm = fetch_word_imm(); + } + DECODE_PRINTF2("PUSH\t%x\n", imm); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(imm); + } else { + push_word((u16)imm); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x69 +****************************************************************************/ +void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6a +****************************************************************************/ +void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 imm; + + START_OF_INSTR(); + imm = (s8)fetch_byte_imm(); + DECODE_PRINTF2("PUSH\t%d\n", imm); + TRACE_AND_STEP(); + push_word(imm); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6b +****************************************************************************/ +void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + s8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6c +****************************************************************************/ +void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INSB\n"); + ins(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6d +****************************************************************************/ +void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INSD\n"); + ins(4); + } else { + DECODE_PRINTF("INSW\n"); + ins(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6e +****************************************************************************/ +void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUTSB\n"); + outs(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6f +****************************************************************************/ +void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUTSD\n"); + outs(4); + } else { + DECODE_PRINTF("OUTSW\n"); + outs(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x70 +****************************************************************************/ +void x86emuOp_jump_near_O(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x71 +****************************************************************************/ +void x86emuOp_jump_near_NO(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow is not set */ + START_OF_INSTR(); + DECODE_PRINTF("JNO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x72 +****************************************************************************/ +void x86emuOp_jump_near_B(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x73 +****************************************************************************/ +void x86emuOp_jump_near_NB(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x74 +****************************************************************************/ +void x86emuOp_jump_near_Z(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x75 +****************************************************************************/ +void x86emuOp_jump_near_NZ(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x76 +****************************************************************************/ +void x86emuOp_jump_near_BE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set or if the zero + flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x77 +****************************************************************************/ +void x86emuOp_jump_near_NBE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear and if the zero + flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x78 +****************************************************************************/ +void x86emuOp_jump_near_S(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x79 +****************************************************************************/ +void x86emuOp_jump_near_NS(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7a +****************************************************************************/ +void x86emuOp_jump_near_P(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is set (even parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7b +****************************************************************************/ +void x86emuOp_jump_near_NP(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is clear (odd parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JNP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7c +****************************************************************************/ +void x86emuOp_jump_near_L(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if (sf ^ of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7d +****************************************************************************/ +void x86emuOp_jump_near_NL(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JNL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + /* note: inverse of above, but using == instead of xor. */ + if (sf == of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7e +****************************************************************************/ +void x86emuOp_jump_near_LE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag + or the zero flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf ^ of) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7f +****************************************************************************/ +void x86emuOp_jump_near_NLE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag equal to overflow flag. + and the zero flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf == of) && !ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc80_byte_operation[])(u8 d, u8 s) = +{ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x80 +****************************************************************************/ +void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc81_word_operation[])(u16 d, u16 s) = +{ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ +}; + +static u32 (*opc81_long_operation[])(u32 d, u32 s) = +{ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x81 +****************************************************************************/ +void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* + * Know operation, decode the mod byte to find the addressing + * mode. + */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc82_byte_operation[])(u8 s, u8 d) = +{ + add_byte, /*00 */ + or_byte, /*01 */ /*YYY UNUSED ???? */ + adc_byte, /*02 */ + sbb_byte, /*03 */ + and_byte, /*04 */ /*YYY UNUSED ???? */ + sub_byte, /*05 */ + xor_byte, /*06 */ /*YYY UNUSED ???? */ + cmp_byte, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x82 +****************************************************************************/ +void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc83_word_operation[])(u16 s, u16 d) = +{ + add_word, /*00 */ + or_word, /*01 */ /*YYY UNUSED ???? */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ /*YYY UNUSED ???? */ + sub_word, /*05 */ + xor_word, /*06 */ /*YYY UNUSED ???? */ + cmp_word, /*07 */ +}; + +static u32 (*opc83_long_operation[])(u32 s, u32 d) = +{ + add_long, /*00 */ + or_long, /*01 */ /*YYY UNUSED ???? */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ /*YYY UNUSED ???? */ + sub_long, /*05 */ + xor_long, /*06 */ /*YYY UNUSED ???? */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x83 +****************************************************************************/ +void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x84 +****************************************************************************/ +void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x85 +****************************************************************************/ +void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x86 +****************************************************************************/ +void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + u8 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x87 +****************************************************************************/ +void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x88 +****************************************************************************/ +void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x89 +****************************************************************************/ +void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8a +****************************************************************************/ +void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8b +****************************************************************************/ +void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8c +****************************************************************************/ +void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint destoffset; + u16 destval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8d +****************************************************************************/ +void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *srcreg; + uint destoffset; + +/* + * TODO: Need to handle address size prefix! + * + * lea eax,[eax+ebx*2] ?? + */ + + START_OF_INSTR(); + DECODE_PRINTF("LEA\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + break; + case 1: + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + break; + case 2: + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + break; + case 3: /* register to register */ + /* undefined. Do nothing. */ + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8e +****************************************************************************/ +void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint srcoffset; + u16 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + /* + * Clean up, and reset all the R_xSP pointers to the correct + * locations. This is about 3x too much overhead (doing all the + * segreg ptrs when only one is needed, but this instruction + * *cannot* be that common, and this isn't too much work anyway. + */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8f +****************************************************************************/ +void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("POP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x90 +****************************************************************************/ +void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("NOP\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x91 +****************************************************************************/ +void x86emuOp_xchg_word_AX_CX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ECX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,CX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ECX; + M.x86.R_ECX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_CX; + M.x86.R_CX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x92 +****************************************************************************/ +void x86emuOp_xchg_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDX; + M.x86.R_EDX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DX; + M.x86.R_DX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x93 +****************************************************************************/ +void x86emuOp_xchg_word_AX_BX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBX; + M.x86.R_EBX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BX; + M.x86.R_BX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x94 +****************************************************************************/ +void x86emuOp_xchg_word_AX_SP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESP; + M.x86.R_ESP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SP; + M.x86.R_SP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x95 +****************************************************************************/ +void x86emuOp_xchg_word_AX_BP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBP; + M.x86.R_EBP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BP; + M.x86.R_BP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x96 +****************************************************************************/ +void x86emuOp_xchg_word_AX_SI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESI; + M.x86.R_ESI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SI; + M.x86.R_SI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x97 +****************************************************************************/ +void x86emuOp_xchg_word_AX_DI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDI; + M.x86.R_EDI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DI; + M.x86.R_DI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x98 +****************************************************************************/ +void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CWDE\n"); + } else { + DECODE_PRINTF("CBW\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } + } else { + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x99 +****************************************************************************/ +void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CDQ\n"); + } else { + DECODE_PRINTF("CWD\n"); + } + DECODE_PRINTF("CWD\n"); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } + } else { + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9a +****************************************************************************/ +void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 farseg, faroff; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); + DECODE_PRINTF2("%04x:", farseg); + DECODE_PRINTF2("%04x\n", faroff); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); + + /* XXX + * + * Hooked interrupt vectors calling into our "BIOS" will cause + * problems unless all intersegment stuff is checked for BIOS + * access. Check needed here. For moment, let it alone. + */ + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = farseg; + push_word(M.x86.R_IP); + M.x86.R_IP = faroff; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9b +****************************************************************************/ +void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("WAIT"); + TRACE_AND_STEP(); + /* NADA. */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9c +****************************************************************************/ +void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) +{ + u32 flags; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHFD\n"); + } else { + DECODE_PRINTF("PUSHF\n"); + } + TRACE_AND_STEP(); + + /* clear out *all* bits not representing flags, and turn on real bits */ + flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(flags); + } else { + push_word((u16)flags); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9d +****************************************************************************/ +void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPFD\n"); + } else { + DECODE_PRINTF("POPF\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EFLG = pop_long(); + } else { + M.x86.R_FLG = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9e +****************************************************************************/ +void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SAHF\n"); + TRACE_AND_STEP(); + /* clear the lower bits of the flag register */ + M.x86.R_FLG &= 0xffffff00; + /* or in the AH register into the flags register */ + M.x86.R_FLG |= M.x86.R_AH; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9f +****************************************************************************/ +void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LAHF\n"); + TRACE_AND_STEP(); + M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff); + /*undocumented TC++ behavior??? Nope. It's documented, but + you have too look real hard to notice it. */ + M.x86.R_AH |= 0x2; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa0 +****************************************************************************/ +void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]\n", offset); + TRACE_AND_STEP(); + M.x86.R_AL = fetch_data_byte(offset); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa1 +****************************************************************************/ +void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + } else { + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(offset); + } else { + M.x86.R_AX = fetch_data_word(offset); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa2 +****************************************************************************/ +void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x],AL\n", offset); + TRACE_AND_STEP(); + store_data_byte(offset, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa3 +****************************************************************************/ +void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + } else { + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long(offset, M.x86.R_EAX); + } else { + store_data_word(offset, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa4 +****************************************************************************/ +void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 val; + u32 count; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("MOVS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa5 +****************************************************************************/ +void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val; + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa6 +****************************************************************************/ +void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val1, val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("CMPS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa7 +****************************************************************************/ +void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val1,val2; + int inc; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMPS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("CMPS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa8 +****************************************************************************/ +void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + int imm; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%04x\n", imm); + TRACE_AND_STEP(); + test_byte(M.x86.R_AL, (u8)imm); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa9 +****************************************************************************/ +void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + test_long(M.x86.R_EAX, srcval); + } else { + test_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaa +****************************************************************************/ +void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("STOS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xab +****************************************************************************/ +void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xac +****************************************************************************/ +void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("LODS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xad +****************************************************************************/ +void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xae +****************************************************************************/ +void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("SCAS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaf +****************************************************************************/ +void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 val; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb0 +****************************************************************************/ +void x86emuOp_mov_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb1 +****************************************************************************/ +void x86emuOp_mov_byte_CL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb2 +****************************************************************************/ +void x86emuOp_mov_byte_DL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb3 +****************************************************************************/ +void x86emuOp_mov_byte_BL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb4 +****************************************************************************/ +void x86emuOp_mov_byte_AH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb5 +****************************************************************************/ +void x86emuOp_mov_byte_CH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb6 +****************************************************************************/ +void x86emuOp_mov_byte_DH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb7 +****************************************************************************/ +void x86emuOp_mov_byte_BH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb8 +****************************************************************************/ +void x86emuOp_mov_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = srcval; + } else { + M.x86.R_AX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb9 +****************************************************************************/ +void x86emuOp_mov_word_CX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tECX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tCX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = srcval; + } else { + M.x86.R_CX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xba +****************************************************************************/ +void x86emuOp_mov_word_DX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = srcval; + } else { + M.x86.R_DX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbb +****************************************************************************/ +void x86emuOp_mov_word_BX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = srcval; + } else { + M.x86.R_BX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbc +****************************************************************************/ +void x86emuOp_mov_word_SP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = srcval; + } else { + M.x86.R_SP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbd +****************************************************************************/ +void x86emuOp_mov_word_BP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = srcval; + } else { + M.x86.R_BP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbe +****************************************************************************/ +void x86emuOp_mov_word_SI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = srcval; + } else { + M.x86.R_SI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbf +****************************************************************************/ +void x86emuOp_mov_word_DI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = srcval; + } else { + M.x86.R_DI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c0, d0, and d2. */ +static u8(*opcD0_byte_operation[])(u8 d, u8 s) = +{ + rol_byte, + ror_byte, + rcl_byte, + rcr_byte, + shl_byte, + shr_byte, + shl_byte, /* sal_byte === shl_byte by definition */ + sar_byte, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc0 +****************************************************************************/ +void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c1, d1, and d3. */ +static u16(*opcD1_word_operation[])(u16 s, u8 d) = +{ + rol_word, + ror_word, + rcl_word, + rcr_word, + shl_word, + shr_word, + shl_word, /* sal_byte === shl_byte by definition */ + sar_word, +}; + +/* used by opcodes c1, d1, and d3. */ +static u32 (*opcD1_long_operation[])(u32 s, u8 d) = +{ + rol_long, + ror_long, + rcl_long, + rcr_long, + shl_long, + shr_long, + shl_long, /* sal_byte === shl_byte by definition */ + sar_long, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc1 +****************************************************************************/ +void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc2 +****************************************************************************/ +void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RET\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc3 +****************************************************************************/ +void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RET\n"); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc4 +****************************************************************************/ +void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LES\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc5 +****************************************************************************/ +void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LDS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc6 +****************************************************************************/ +void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc7 +****************************************************************************/ +void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { + u16 *destreg; + u16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc8 +****************************************************************************/ +void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) +{ + u16 local,frame_pointer; + u8 nesting; + int i; + + START_OF_INSTR(); + local = fetch_word_imm(); + nesting = fetch_byte_imm(); + DECODE_PRINTF2("ENTER %x\n", local); + DECODE_PRINTF2(",%x\n", nesting); + TRACE_AND_STEP(); + push_word(M.x86.R_BP); + frame_pointer = M.x86.R_SP; + if (nesting > 0) { + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } + M.x86.R_BP = frame_pointer; + M.x86.R_SP = (u16)(M.x86.R_SP - local); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc9 +****************************************************************************/ +void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LEAVE\n"); + TRACE_AND_STEP(); + M.x86.R_SP = M.x86.R_BP; + M.x86.R_BP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xca +****************************************************************************/ +void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RETF\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcb +****************************************************************************/ +void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RETF\n"); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcc +****************************************************************************/ +void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) +{ + u16 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("INT 3\n"); + tmp = (u16) mem_access_word(3 * 4 + 2); + /* access the segment register */ + TRACE_AND_STEP(); + if (_X86EMU_intrTab[3]) { + (*_X86EMU_intrTab[3])(3); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcd +****************************************************************************/ +void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 tmp; + u8 intnum; + + START_OF_INSTR(); + DECODE_PRINTF("INT\t"); + intnum = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", intnum); + tmp = mem_access_word(intnum * 4 + 2); + TRACE_AND_STEP(); + if (_X86EMU_intrTab[intnum]) { + (*_X86EMU_intrTab[intnum])(intnum); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xce +****************************************************************************/ +void x86emuOp_into(u8 X86EMU_UNUSED(op1)) +{ + u16 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("INTO\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) { + tmp = mem_access_word(4 * 4 + 2); + if (_X86EMU_intrTab[4]) { + (*_X86EMU_intrTab[4])(4); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcf +****************************************************************************/ +void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IRET\n"); + + TRACE_AND_STEP(); + + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_FLG = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd0 +****************************************************************************/ +void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd1 +****************************************************************************/ +void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { + u16 destval; + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd2 +****************************************************************************/ +void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd3 +****************************************************************************/ +void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd4 +****************************************************************************/ +void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAM\n"); + a = fetch_byte_imm(); /* this is a stupid encoding. */ + if (a != 10) { + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } + TRACE_AND_STEP(); + /* note the type change here --- returning AL and AH in AX. */ + M.x86.R_AX = aam_word(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd5 +****************************************************************************/ +void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAD\n"); + a = fetch_byte_imm(); + TRACE_AND_STEP(); + M.x86.R_AX = aad_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* opcode 0xd6 ILLEGAL OPCODE */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xd7 +****************************************************************************/ +void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) +{ + u16 addr; + + START_OF_INSTR(); + DECODE_PRINTF("XLAT\n"); + TRACE_AND_STEP(); + addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL); + M.x86.R_AL = fetch_data_byte(addr); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* instuctions D8 .. DF are in i87_ops.c */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xe0 +****************************************************************************/ +void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPNE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe1 +****************************************************************************/ +void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe2 +****************************************************************************/ +void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOP\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0) + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe3 +****************************************************************************/ +void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JCXZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (M.x86.R_CX == 0) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe4 +****************************************************************************/ +void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(port); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe5 +****************************************************************************/ +void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("EAX,%x\n", port); + } else { + DECODE_PRINTF2("AX,%x\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(port); + } else { + M.x86.R_AX = (*sys_inw)(port); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe6 +****************************************************************************/ +void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + (*sys_outb)(port, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe7 +****************************************************************************/ +void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("%x,EAX\n", port); + } else { + DECODE_PRINTF2("%x,AX\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(port, M.x86.R_EAX); + } else { + (*sys_outw)(port, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe8 +****************************************************************************/ +void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + ip = (s16) fetch_word_imm(); + ip += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", ip); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe9 +****************************************************************************/ +void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + int ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xea +****************************************************************************/ +void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 cs, ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\tFAR "); + ip = fetch_word_imm(); + cs = fetch_word_imm(); + DECODE_PRINTF2("%04x:", cs); + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_IP = ip; + M.x86.R_CS = cs; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xeb +****************************************************************************/ +void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xec +****************************************************************************/ +void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IN\tAL,DX\n"); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(M.x86.R_DX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xed +****************************************************************************/ +void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("IN\tEAX,DX\n"); + } else { + DECODE_PRINTF("IN\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + } else { + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xee +****************************************************************************/ +void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUT\tDX,AL\n"); + TRACE_AND_STEP(); + (*sys_outb)(M.x86.R_DX, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xef +****************************************************************************/ +void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUT\tDX,EAX\n"); + } else { + DECODE_PRINTF("OUT\tDX,AX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + } else { + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf0 +****************************************************************************/ +void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LOCK:\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0xf1 ILLEGAL OPERATION */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xf2 +****************************************************************************/ +void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPNE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPNE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf3 +****************************************************************************/ +void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf4 +****************************************************************************/ +void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("HALT\n"); + TRACE_AND_STEP(); + HALT_SYS(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf5 +****************************************************************************/ +void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) +{ + /* complement the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CMC\n"); + TRACE_AND_STEP(); + TOGGLE_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf6 +****************************************************************************/ +void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval, srcval; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + case 7: + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf7 +****************************************************************************/ +void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + } else { + u16 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + } + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf8 +****************************************************************************/ +void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) +{ + /* clear the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CLC\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf9 +****************************************************************************/ +void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) +{ + /* set the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("STC\n"); + TRACE_AND_STEP(); + SET_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfa +****************************************************************************/ +void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLI\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfb +****************************************************************************/ +void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) +{ + /* enable interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STI\n"); + TRACE_AND_STEP(); + SET_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfc +****************************************************************************/ +void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLD\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfd +****************************************************************************/ +void x86emuOp_std(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STD\n"); + TRACE_AND_STEP(); + SET_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfe +****************************************************************************/ +void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u8 destval; + uint destoffset; + u8 *destreg; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: /* dec word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 3: + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + TRACE_AND_STEP(); + *destreg = inc_byte(*destreg); + break; + case 1: + TRACE_AND_STEP(); + *destreg = dec_byte(*destreg); + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xff +****************************************************************************/ +void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + uint destoffset = 0; + u16 *destreg; + u16 destval,destval2; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t "); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 3: + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Single byte operation code table: + **************************************************************************/ +void (*x86emu_optab[256])(u8) = +{ +/* 0x00 */ x86emuOp_add_byte_RM_R, +/* 0x01 */ x86emuOp_add_word_RM_R, +/* 0x02 */ x86emuOp_add_byte_R_RM, +/* 0x03 */ x86emuOp_add_word_R_RM, +/* 0x04 */ x86emuOp_add_byte_AL_IMM, +/* 0x05 */ x86emuOp_add_word_AX_IMM, +/* 0x06 */ x86emuOp_push_ES, +/* 0x07 */ x86emuOp_pop_ES, + +/* 0x08 */ x86emuOp_or_byte_RM_R, +/* 0x09 */ x86emuOp_or_word_RM_R, +/* 0x0a */ x86emuOp_or_byte_R_RM, +/* 0x0b */ x86emuOp_or_word_R_RM, +/* 0x0c */ x86emuOp_or_byte_AL_IMM, +/* 0x0d */ x86emuOp_or_word_AX_IMM, +/* 0x0e */ x86emuOp_push_CS, +/* 0x0f */ x86emuOp_two_byte, + +/* 0x10 */ x86emuOp_adc_byte_RM_R, +/* 0x11 */ x86emuOp_adc_word_RM_R, +/* 0x12 */ x86emuOp_adc_byte_R_RM, +/* 0x13 */ x86emuOp_adc_word_R_RM, +/* 0x14 */ x86emuOp_adc_byte_AL_IMM, +/* 0x15 */ x86emuOp_adc_word_AX_IMM, +/* 0x16 */ x86emuOp_push_SS, +/* 0x17 */ x86emuOp_pop_SS, + +/* 0x18 */ x86emuOp_sbb_byte_RM_R, +/* 0x19 */ x86emuOp_sbb_word_RM_R, +/* 0x1a */ x86emuOp_sbb_byte_R_RM, +/* 0x1b */ x86emuOp_sbb_word_R_RM, +/* 0x1c */ x86emuOp_sbb_byte_AL_IMM, +/* 0x1d */ x86emuOp_sbb_word_AX_IMM, +/* 0x1e */ x86emuOp_push_DS, +/* 0x1f */ x86emuOp_pop_DS, + +/* 0x20 */ x86emuOp_and_byte_RM_R, +/* 0x21 */ x86emuOp_and_word_RM_R, +/* 0x22 */ x86emuOp_and_byte_R_RM, +/* 0x23 */ x86emuOp_and_word_R_RM, +/* 0x24 */ x86emuOp_and_byte_AL_IMM, +/* 0x25 */ x86emuOp_and_word_AX_IMM, +/* 0x26 */ x86emuOp_segovr_ES, +/* 0x27 */ x86emuOp_daa, + +/* 0x28 */ x86emuOp_sub_byte_RM_R, +/* 0x29 */ x86emuOp_sub_word_RM_R, +/* 0x2a */ x86emuOp_sub_byte_R_RM, +/* 0x2b */ x86emuOp_sub_word_R_RM, +/* 0x2c */ x86emuOp_sub_byte_AL_IMM, +/* 0x2d */ x86emuOp_sub_word_AX_IMM, +/* 0x2e */ x86emuOp_segovr_CS, +/* 0x2f */ x86emuOp_das, + +/* 0x30 */ x86emuOp_xor_byte_RM_R, +/* 0x31 */ x86emuOp_xor_word_RM_R, +/* 0x32 */ x86emuOp_xor_byte_R_RM, +/* 0x33 */ x86emuOp_xor_word_R_RM, +/* 0x34 */ x86emuOp_xor_byte_AL_IMM, +/* 0x35 */ x86emuOp_xor_word_AX_IMM, +/* 0x36 */ x86emuOp_segovr_SS, +/* 0x37 */ x86emuOp_aaa, + +/* 0x38 */ x86emuOp_cmp_byte_RM_R, +/* 0x39 */ x86emuOp_cmp_word_RM_R, +/* 0x3a */ x86emuOp_cmp_byte_R_RM, +/* 0x3b */ x86emuOp_cmp_word_R_RM, +/* 0x3c */ x86emuOp_cmp_byte_AL_IMM, +/* 0x3d */ x86emuOp_cmp_word_AX_IMM, +/* 0x3e */ x86emuOp_segovr_DS, +/* 0x3f */ x86emuOp_aas, + +/* 0x40 */ x86emuOp_inc_AX, +/* 0x41 */ x86emuOp_inc_CX, +/* 0x42 */ x86emuOp_inc_DX, +/* 0x43 */ x86emuOp_inc_BX, +/* 0x44 */ x86emuOp_inc_SP, +/* 0x45 */ x86emuOp_inc_BP, +/* 0x46 */ x86emuOp_inc_SI, +/* 0x47 */ x86emuOp_inc_DI, + +/* 0x48 */ x86emuOp_dec_AX, +/* 0x49 */ x86emuOp_dec_CX, +/* 0x4a */ x86emuOp_dec_DX, +/* 0x4b */ x86emuOp_dec_BX, +/* 0x4c */ x86emuOp_dec_SP, +/* 0x4d */ x86emuOp_dec_BP, +/* 0x4e */ x86emuOp_dec_SI, +/* 0x4f */ x86emuOp_dec_DI, + +/* 0x50 */ x86emuOp_push_AX, +/* 0x51 */ x86emuOp_push_CX, +/* 0x52 */ x86emuOp_push_DX, +/* 0x53 */ x86emuOp_push_BX, +/* 0x54 */ x86emuOp_push_SP, +/* 0x55 */ x86emuOp_push_BP, +/* 0x56 */ x86emuOp_push_SI, +/* 0x57 */ x86emuOp_push_DI, + +/* 0x58 */ x86emuOp_pop_AX, +/* 0x59 */ x86emuOp_pop_CX, +/* 0x5a */ x86emuOp_pop_DX, +/* 0x5b */ x86emuOp_pop_BX, +/* 0x5c */ x86emuOp_pop_SP, +/* 0x5d */ x86emuOp_pop_BP, +/* 0x5e */ x86emuOp_pop_SI, +/* 0x5f */ x86emuOp_pop_DI, + +/* 0x60 */ x86emuOp_push_all, +/* 0x61 */ x86emuOp_pop_all, +/* 0x62 */ x86emuOp_illegal_op, /* bound */ +/* 0x63 */ x86emuOp_illegal_op, /* arpl */ +/* 0x64 */ x86emuOp_segovr_FS, +/* 0x65 */ x86emuOp_segovr_GS, +/* 0x66 */ x86emuOp_prefix_data, +/* 0x67 */ x86emuOp_prefix_addr, + +/* 0x68 */ x86emuOp_push_word_IMM, +/* 0x69 */ x86emuOp_imul_word_IMM, +/* 0x6a */ x86emuOp_push_byte_IMM, +/* 0x6b */ x86emuOp_imul_byte_IMM, +/* 0x6c */ x86emuOp_ins_byte, +/* 0x6d */ x86emuOp_ins_word, +/* 0x6e */ x86emuOp_outs_byte, +/* 0x6f */ x86emuOp_outs_word, + +/* 0x70 */ x86emuOp_jump_near_O, +/* 0x71 */ x86emuOp_jump_near_NO, +/* 0x72 */ x86emuOp_jump_near_B, +/* 0x73 */ x86emuOp_jump_near_NB, +/* 0x74 */ x86emuOp_jump_near_Z, +/* 0x75 */ x86emuOp_jump_near_NZ, +/* 0x76 */ x86emuOp_jump_near_BE, +/* 0x77 */ x86emuOp_jump_near_NBE, + +/* 0x78 */ x86emuOp_jump_near_S, +/* 0x79 */ x86emuOp_jump_near_NS, +/* 0x7a */ x86emuOp_jump_near_P, +/* 0x7b */ x86emuOp_jump_near_NP, +/* 0x7c */ x86emuOp_jump_near_L, +/* 0x7d */ x86emuOp_jump_near_NL, +/* 0x7e */ x86emuOp_jump_near_LE, +/* 0x7f */ x86emuOp_jump_near_NLE, + +/* 0x80 */ x86emuOp_opc80_byte_RM_IMM, +/* 0x81 */ x86emuOp_opc81_word_RM_IMM, +/* 0x82 */ x86emuOp_opc82_byte_RM_IMM, +/* 0x83 */ x86emuOp_opc83_word_RM_IMM, +/* 0x84 */ x86emuOp_test_byte_RM_R, +/* 0x85 */ x86emuOp_test_word_RM_R, +/* 0x86 */ x86emuOp_xchg_byte_RM_R, +/* 0x87 */ x86emuOp_xchg_word_RM_R, + +/* 0x88 */ x86emuOp_mov_byte_RM_R, +/* 0x89 */ x86emuOp_mov_word_RM_R, +/* 0x8a */ x86emuOp_mov_byte_R_RM, +/* 0x8b */ x86emuOp_mov_word_R_RM, +/* 0x8c */ x86emuOp_mov_word_RM_SR, +/* 0x8d */ x86emuOp_lea_word_R_M, +/* 0x8e */ x86emuOp_mov_word_SR_RM, +/* 0x8f */ x86emuOp_pop_RM, + +/* 0x90 */ x86emuOp_nop, +/* 0x91 */ x86emuOp_xchg_word_AX_CX, +/* 0x92 */ x86emuOp_xchg_word_AX_DX, +/* 0x93 */ x86emuOp_xchg_word_AX_BX, +/* 0x94 */ x86emuOp_xchg_word_AX_SP, +/* 0x95 */ x86emuOp_xchg_word_AX_BP, +/* 0x96 */ x86emuOp_xchg_word_AX_SI, +/* 0x97 */ x86emuOp_xchg_word_AX_DI, + +/* 0x98 */ x86emuOp_cbw, +/* 0x99 */ x86emuOp_cwd, +/* 0x9a */ x86emuOp_call_far_IMM, +/* 0x9b */ x86emuOp_wait, +/* 0x9c */ x86emuOp_pushf_word, +/* 0x9d */ x86emuOp_popf_word, +/* 0x9e */ x86emuOp_sahf, +/* 0x9f */ x86emuOp_lahf, + +/* 0xa0 */ x86emuOp_mov_AL_M_IMM, +/* 0xa1 */ x86emuOp_mov_AX_M_IMM, +/* 0xa2 */ x86emuOp_mov_M_AL_IMM, +/* 0xa3 */ x86emuOp_mov_M_AX_IMM, +/* 0xa4 */ x86emuOp_movs_byte, +/* 0xa5 */ x86emuOp_movs_word, +/* 0xa6 */ x86emuOp_cmps_byte, +/* 0xa7 */ x86emuOp_cmps_word, +/* 0xa8 */ x86emuOp_test_AL_IMM, +/* 0xa9 */ x86emuOp_test_AX_IMM, +/* 0xaa */ x86emuOp_stos_byte, +/* 0xab */ x86emuOp_stos_word, +/* 0xac */ x86emuOp_lods_byte, +/* 0xad */ x86emuOp_lods_word, +/* 0xac */ x86emuOp_scas_byte, +/* 0xad */ x86emuOp_scas_word, + + +/* 0xb0 */ x86emuOp_mov_byte_AL_IMM, +/* 0xb1 */ x86emuOp_mov_byte_CL_IMM, +/* 0xb2 */ x86emuOp_mov_byte_DL_IMM, +/* 0xb3 */ x86emuOp_mov_byte_BL_IMM, +/* 0xb4 */ x86emuOp_mov_byte_AH_IMM, +/* 0xb5 */ x86emuOp_mov_byte_CH_IMM, +/* 0xb6 */ x86emuOp_mov_byte_DH_IMM, +/* 0xb7 */ x86emuOp_mov_byte_BH_IMM, + +/* 0xb8 */ x86emuOp_mov_word_AX_IMM, +/* 0xb9 */ x86emuOp_mov_word_CX_IMM, +/* 0xba */ x86emuOp_mov_word_DX_IMM, +/* 0xbb */ x86emuOp_mov_word_BX_IMM, +/* 0xbc */ x86emuOp_mov_word_SP_IMM, +/* 0xbd */ x86emuOp_mov_word_BP_IMM, +/* 0xbe */ x86emuOp_mov_word_SI_IMM, +/* 0xbf */ x86emuOp_mov_word_DI_IMM, + +/* 0xc0 */ x86emuOp_opcC0_byte_RM_MEM, +/* 0xc1 */ x86emuOp_opcC1_word_RM_MEM, +/* 0xc2 */ x86emuOp_ret_near_IMM, +/* 0xc3 */ x86emuOp_ret_near, +/* 0xc4 */ x86emuOp_les_R_IMM, +/* 0xc5 */ x86emuOp_lds_R_IMM, +/* 0xc6 */ x86emuOp_mov_byte_RM_IMM, +/* 0xc7 */ x86emuOp_mov_word_RM_IMM, +/* 0xc8 */ x86emuOp_enter, +/* 0xc9 */ x86emuOp_leave, +/* 0xca */ x86emuOp_ret_far_IMM, +/* 0xcb */ x86emuOp_ret_far, +/* 0xcc */ x86emuOp_int3, +/* 0xcd */ x86emuOp_int_IMM, +/* 0xce */ x86emuOp_into, +/* 0xcf */ x86emuOp_iret, + +/* 0xd0 */ x86emuOp_opcD0_byte_RM_1, +/* 0xd1 */ x86emuOp_opcD1_word_RM_1, +/* 0xd2 */ x86emuOp_opcD2_byte_RM_CL, +/* 0xd3 */ x86emuOp_opcD3_word_RM_CL, +/* 0xd4 */ x86emuOp_aam, +/* 0xd5 */ x86emuOp_aad, +/* 0xd6 */ x86emuOp_illegal_op, /* Undocumented SETALC instruction */ +/* 0xd7 */ x86emuOp_xlat, +/* 0xd8 */ x86emuOp_esc_coprocess_d8, +/* 0xd9 */ x86emuOp_esc_coprocess_d9, +/* 0xda */ x86emuOp_esc_coprocess_da, +/* 0xdb */ x86emuOp_esc_coprocess_db, +/* 0xdc */ x86emuOp_esc_coprocess_dc, +/* 0xdd */ x86emuOp_esc_coprocess_dd, +/* 0xde */ x86emuOp_esc_coprocess_de, +/* 0xdf */ x86emuOp_esc_coprocess_df, + +/* 0xe0 */ x86emuOp_loopne, +/* 0xe1 */ x86emuOp_loope, +/* 0xe2 */ x86emuOp_loop, +/* 0xe3 */ x86emuOp_jcxz, +/* 0xe4 */ x86emuOp_in_byte_AL_IMM, +/* 0xe5 */ x86emuOp_in_word_AX_IMM, +/* 0xe6 */ x86emuOp_out_byte_IMM_AL, +/* 0xe7 */ x86emuOp_out_word_IMM_AX, + +/* 0xe8 */ x86emuOp_call_near_IMM, +/* 0xe9 */ x86emuOp_jump_near_IMM, +/* 0xea */ x86emuOp_jump_far_IMM, +/* 0xeb */ x86emuOp_jump_byte_IMM, +/* 0xec */ x86emuOp_in_byte_AL_DX, +/* 0xed */ x86emuOp_in_word_AX_DX, +/* 0xee */ x86emuOp_out_byte_DX_AL, +/* 0xef */ x86emuOp_out_word_DX_AX, + +/* 0xf0 */ x86emuOp_lock, +/* 0xf1 */ x86emuOp_illegal_op, +/* 0xf2 */ x86emuOp_repne, +/* 0xf3 */ x86emuOp_repe, +/* 0xf4 */ x86emuOp_halt, +/* 0xf5 */ x86emuOp_cmc, +/* 0xf6 */ x86emuOp_opcF6_byte_RM, +/* 0xf7 */ x86emuOp_opcF7_word_RM, + +/* 0xf8 */ x86emuOp_clc, +/* 0xf9 */ x86emuOp_stc, +/* 0xfa */ x86emuOp_cli, +/* 0xfb */ x86emuOp_sti, +/* 0xfc */ x86emuOp_cld, +/* 0xfd */ x86emuOp_std, +/* 0xfe */ x86emuOp_opcFE_byte_RM, +/* 0xff */ x86emuOp_opcFF_word_RM, +}; + +void tables_relocate(unsigned int offset) +{ + int i; + for (i=0; i<8; i++) + { + opc80_byte_operation[i] -= offset; + opc81_word_operation[i] -= offset; + opc81_long_operation[i] -= offset; + + opc82_byte_operation[i] -= offset; + opc83_word_operation[i] -= offset; + opc83_long_operation[i] -= offset; + + opcD0_byte_operation[i] -= offset; + opcD1_word_operation[i] -= offset; + opcD1_long_operation[i] -= offset; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c b/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c new file mode 100644 index 0000000..d381307 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c @@ -0,0 +1,2800 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 extended two-byte processor +* instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +void x86emuOp2_illegal_op( + u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-2,op2); + HALT_SYS(); + END_OF_INSTR(); +} + +#define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x80-0x8F +****************************************************************************/ +void x86emuOp2_long_jump(u8 op2) +{ + s32 target; + char *name = 0; + int cond = 0; + + /* conditional jump to word offset. */ + START_OF_INSTR(); + switch (op2) { + case 0x80: + name = "JO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x81: + name = "JNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x82: + name = "JB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x83: + name = "JNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x84: + name = "JZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x85: + name = "JNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x86: + name = "JBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x87: + name = "JNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x88: + name = "JS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x89: + name = "JNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x8a: + name = "JP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x8b: + name = "JNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x8c: + name = "JL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8d: + name = "JNL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8e: + name = "JLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x8f: + name = "JNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + target = (s16) fetch_word_imm(); + target += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", target); + TRACE_AND_STEP(); + if (cond) + M.x86.R_IP = (u16)target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x90-0x9F +****************************************************************************/ +void x86emuOp2_set_byte(u8 op2) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg; + char *name = 0; + int cond = 0; + + START_OF_INSTR(); + switch (op2) { + case 0x90: + name = "SETO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x91: + name = "SETNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x92: + name = "SETB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x93: + name = "SETNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x94: + name = "SETZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x95: + name = "SETNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x96: + name = "SETBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x97: + name = "SETNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x98: + name = "SETS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x99: + name = "SETNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x9a: + name = "SETP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x9b: + name = "SETNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x9c: + name = "SETL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9d: + name = "SETNL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9e: + name = "SETLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x9f: + name = "SETNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 1: + destoffset = decode_rm01_address(rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 2: + destoffset = decode_rm10_address(rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + TRACE_AND_STEP(); + *destreg = cond ? 0x01 : 0x00; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa0 +****************************************************************************/ +void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tFS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_FS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa1 +****************************************************************************/ +void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tFS\n"); + TRACE_AND_STEP(); + M.x86.R_FS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa3 +****************************************************************************/ +void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BT\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } else { + u16 *srcreg,*shiftreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa4 +****************************************************************************/ +void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa5 +****************************************************************************/ +void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa8 +****************************************************************************/ +void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tGS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_GS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa9 +****************************************************************************/ +void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tGS\n"); + TRACE_AND_STEP(); + M.x86.R_GS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaa +****************************************************************************/ +void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xac +****************************************************************************/ +void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xad +****************************************************************************/ +void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaf +****************************************************************************/ +void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + res = (s16)*destreg * (s16)*srcreg; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb2 +****************************************************************************/ +void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LSS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb3 +****************************************************************************/ +void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb4 +****************************************************************************/ +void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LFS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb5 +****************************************************************************/ +void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LGS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb6 +****************************************************************************/ +void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb7 +****************************************************************************/ +void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xba +****************************************************************************/ +void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (rh) { + case 3: + DECODE_PRINTF("BT\t"); + break; + case 4: + DECODE_PRINTF("BTS\t"); + break; + case 5: + DECODE_PRINTF("BTR\t"); + break; + case 6: + DECODE_PRINTF("BTC\t"); + break; + default: + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", + M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_long(srcoffset, srcval | mask); + break; + case 5: + store_data_long(srcoffset, srcval & ~mask); + break; + case 6: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_word(srcoffset, srcval | mask); + break; + case 5: + store_data_word(srcoffset, srcval & ~mask); + break; + case 6: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_long(srcoffset, srcval | mask); + break; + case 5: + store_data_long(srcoffset, srcval & ~mask); + break; + case 6: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_word(srcoffset, srcval | mask); + break; + case 5: + store_data_word(srcoffset, srcval & ~mask); + break; + case 6: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_long(srcoffset, srcval | mask); + break; + case 5: + store_data_long(srcoffset, srcval & ~mask); + break; + case 6: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_word(srcoffset, srcval | mask); + break; + case 5: + store_data_word(srcoffset, srcval & ~mask); + break; + case 6: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 mask; + u8 shift; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 4: + *srcreg |= mask; + break; + case 5: + *srcreg &= ~mask; + break; + case 6: + *srcreg ^= mask; + break; + default: + break; + } + } else { + u16 *srcreg; + u16 mask; + u8 shift; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0xF; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 4: + *srcreg |= mask; + break; + case 5: + *srcreg &= ~mask; + break; + case 6: + *srcreg ^= mask; + break; + default: + break; + } + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbb +****************************************************************************/ +void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbc +****************************************************************************/ +void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSF\n"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbd +****************************************************************************/ +void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSF\n"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbe +****************************************************************************/ +void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s8)*srcreg); + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s16)((s8)*srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbf +****************************************************************************/ +void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s16)*srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Double byte operation code table: + **************************************************************************/ +void (*x86emu_optab2[256])(u8) = +{ +/* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ +/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ +/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ +/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ +/* 0x04 */ x86emuOp2_illegal_op, +/* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ +/* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ +/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ +/* 0x0a */ x86emuOp2_illegal_op, +/* 0x0b */ x86emuOp2_illegal_op, +/* 0x0c */ x86emuOp2_illegal_op, +/* 0x0d */ x86emuOp2_illegal_op, +/* 0x0e */ x86emuOp2_illegal_op, +/* 0x0f */ x86emuOp2_illegal_op, + +/* 0x10 */ x86emuOp2_illegal_op, +/* 0x11 */ x86emuOp2_illegal_op, +/* 0x12 */ x86emuOp2_illegal_op, +/* 0x13 */ x86emuOp2_illegal_op, +/* 0x14 */ x86emuOp2_illegal_op, +/* 0x15 */ x86emuOp2_illegal_op, +/* 0x16 */ x86emuOp2_illegal_op, +/* 0x17 */ x86emuOp2_illegal_op, +/* 0x18 */ x86emuOp2_illegal_op, +/* 0x19 */ x86emuOp2_illegal_op, +/* 0x1a */ x86emuOp2_illegal_op, +/* 0x1b */ x86emuOp2_illegal_op, +/* 0x1c */ x86emuOp2_illegal_op, +/* 0x1d */ x86emuOp2_illegal_op, +/* 0x1e */ x86emuOp2_illegal_op, +/* 0x1f */ x86emuOp2_illegal_op, + +/* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */ +/* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */ +/* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */ +/* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */ +/* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */ +/* 0x25 */ x86emuOp2_illegal_op, +/* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */ +/* 0x27 */ x86emuOp2_illegal_op, +/* 0x28 */ x86emuOp2_illegal_op, +/* 0x29 */ x86emuOp2_illegal_op, +/* 0x2a */ x86emuOp2_illegal_op, +/* 0x2b */ x86emuOp2_illegal_op, +/* 0x2c */ x86emuOp2_illegal_op, +/* 0x2d */ x86emuOp2_illegal_op, +/* 0x2e */ x86emuOp2_illegal_op, +/* 0x2f */ x86emuOp2_illegal_op, + +/* 0x30 */ x86emuOp2_illegal_op, +/* 0x31 */ x86emuOp2_illegal_op, +/* 0x32 */ x86emuOp2_illegal_op, +/* 0x33 */ x86emuOp2_illegal_op, +/* 0x34 */ x86emuOp2_illegal_op, +/* 0x35 */ x86emuOp2_illegal_op, +/* 0x36 */ x86emuOp2_illegal_op, +/* 0x37 */ x86emuOp2_illegal_op, +/* 0x38 */ x86emuOp2_illegal_op, +/* 0x39 */ x86emuOp2_illegal_op, +/* 0x3a */ x86emuOp2_illegal_op, +/* 0x3b */ x86emuOp2_illegal_op, +/* 0x3c */ x86emuOp2_illegal_op, +/* 0x3d */ x86emuOp2_illegal_op, +/* 0x3e */ x86emuOp2_illegal_op, +/* 0x3f */ x86emuOp2_illegal_op, + +/* 0x40 */ x86emuOp2_illegal_op, +/* 0x41 */ x86emuOp2_illegal_op, +/* 0x42 */ x86emuOp2_illegal_op, +/* 0x43 */ x86emuOp2_illegal_op, +/* 0x44 */ x86emuOp2_illegal_op, +/* 0x45 */ x86emuOp2_illegal_op, +/* 0x46 */ x86emuOp2_illegal_op, +/* 0x47 */ x86emuOp2_illegal_op, +/* 0x48 */ x86emuOp2_illegal_op, +/* 0x49 */ x86emuOp2_illegal_op, +/* 0x4a */ x86emuOp2_illegal_op, +/* 0x4b */ x86emuOp2_illegal_op, +/* 0x4c */ x86emuOp2_illegal_op, +/* 0x4d */ x86emuOp2_illegal_op, +/* 0x4e */ x86emuOp2_illegal_op, +/* 0x4f */ x86emuOp2_illegal_op, + +/* 0x50 */ x86emuOp2_illegal_op, +/* 0x51 */ x86emuOp2_illegal_op, +/* 0x52 */ x86emuOp2_illegal_op, +/* 0x53 */ x86emuOp2_illegal_op, +/* 0x54 */ x86emuOp2_illegal_op, +/* 0x55 */ x86emuOp2_illegal_op, +/* 0x56 */ x86emuOp2_illegal_op, +/* 0x57 */ x86emuOp2_illegal_op, +/* 0x58 */ x86emuOp2_illegal_op, +/* 0x59 */ x86emuOp2_illegal_op, +/* 0x5a */ x86emuOp2_illegal_op, +/* 0x5b */ x86emuOp2_illegal_op, +/* 0x5c */ x86emuOp2_illegal_op, +/* 0x5d */ x86emuOp2_illegal_op, +/* 0x5e */ x86emuOp2_illegal_op, +/* 0x5f */ x86emuOp2_illegal_op, + +/* 0x60 */ x86emuOp2_illegal_op, +/* 0x61 */ x86emuOp2_illegal_op, +/* 0x62 */ x86emuOp2_illegal_op, +/* 0x63 */ x86emuOp2_illegal_op, +/* 0x64 */ x86emuOp2_illegal_op, +/* 0x65 */ x86emuOp2_illegal_op, +/* 0x66 */ x86emuOp2_illegal_op, +/* 0x67 */ x86emuOp2_illegal_op, +/* 0x68 */ x86emuOp2_illegal_op, +/* 0x69 */ x86emuOp2_illegal_op, +/* 0x6a */ x86emuOp2_illegal_op, +/* 0x6b */ x86emuOp2_illegal_op, +/* 0x6c */ x86emuOp2_illegal_op, +/* 0x6d */ x86emuOp2_illegal_op, +/* 0x6e */ x86emuOp2_illegal_op, +/* 0x6f */ x86emuOp2_illegal_op, + +/* 0x70 */ x86emuOp2_illegal_op, +/* 0x71 */ x86emuOp2_illegal_op, +/* 0x72 */ x86emuOp2_illegal_op, +/* 0x73 */ x86emuOp2_illegal_op, +/* 0x74 */ x86emuOp2_illegal_op, +/* 0x75 */ x86emuOp2_illegal_op, +/* 0x76 */ x86emuOp2_illegal_op, +/* 0x77 */ x86emuOp2_illegal_op, +/* 0x78 */ x86emuOp2_illegal_op, +/* 0x79 */ x86emuOp2_illegal_op, +/* 0x7a */ x86emuOp2_illegal_op, +/* 0x7b */ x86emuOp2_illegal_op, +/* 0x7c */ x86emuOp2_illegal_op, +/* 0x7d */ x86emuOp2_illegal_op, +/* 0x7e */ x86emuOp2_illegal_op, +/* 0x7f */ x86emuOp2_illegal_op, + +/* 0x80 */ x86emuOp2_long_jump, +/* 0x81 */ x86emuOp2_long_jump, +/* 0x82 */ x86emuOp2_long_jump, +/* 0x83 */ x86emuOp2_long_jump, +/* 0x84 */ x86emuOp2_long_jump, +/* 0x85 */ x86emuOp2_long_jump, +/* 0x86 */ x86emuOp2_long_jump, +/* 0x87 */ x86emuOp2_long_jump, +/* 0x88 */ x86emuOp2_long_jump, +/* 0x89 */ x86emuOp2_long_jump, +/* 0x8a */ x86emuOp2_long_jump, +/* 0x8b */ x86emuOp2_long_jump, +/* 0x8c */ x86emuOp2_long_jump, +/* 0x8d */ x86emuOp2_long_jump, +/* 0x8e */ x86emuOp2_long_jump, +/* 0x8f */ x86emuOp2_long_jump, + +/* 0x90 */ x86emuOp2_set_byte, +/* 0x91 */ x86emuOp2_set_byte, +/* 0x92 */ x86emuOp2_set_byte, +/* 0x93 */ x86emuOp2_set_byte, +/* 0x94 */ x86emuOp2_set_byte, +/* 0x95 */ x86emuOp2_set_byte, +/* 0x96 */ x86emuOp2_set_byte, +/* 0x97 */ x86emuOp2_set_byte, +/* 0x98 */ x86emuOp2_set_byte, +/* 0x99 */ x86emuOp2_set_byte, +/* 0x9a */ x86emuOp2_set_byte, +/* 0x9b */ x86emuOp2_set_byte, +/* 0x9c */ x86emuOp2_set_byte, +/* 0x9d */ x86emuOp2_set_byte, +/* 0x9e */ x86emuOp2_set_byte, +/* 0x9f */ x86emuOp2_set_byte, + +/* 0xa0 */ x86emuOp2_push_FS, +/* 0xa1 */ x86emuOp2_pop_FS, +/* 0xa2 */ x86emuOp2_illegal_op, +/* 0xa3 */ x86emuOp2_bt_R, +/* 0xa4 */ x86emuOp2_shld_IMM, +/* 0xa5 */ x86emuOp2_shld_CL, +/* 0xa6 */ x86emuOp2_illegal_op, +/* 0xa7 */ x86emuOp2_illegal_op, +/* 0xa8 */ x86emuOp2_push_GS, +/* 0xa9 */ x86emuOp2_pop_GS, +/* 0xaa */ x86emuOp2_illegal_op, +/* 0xab */ x86emuOp2_bt_R, +/* 0xac */ x86emuOp2_shrd_IMM, +/* 0xad */ x86emuOp2_shrd_CL, +/* 0xae */ x86emuOp2_illegal_op, +/* 0xaf */ x86emuOp2_imul_R_RM, + +/* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb2 */ x86emuOp2_lss_R_IMM, +/* 0xb3 */ x86emuOp2_btr_R, +/* 0xb4 */ x86emuOp2_lfs_R_IMM, +/* 0xb5 */ x86emuOp2_lgs_R_IMM, +/* 0xb6 */ x86emuOp2_movzx_byte_R_RM, +/* 0xb7 */ x86emuOp2_movzx_word_R_RM, +/* 0xb8 */ x86emuOp2_illegal_op, +/* 0xb9 */ x86emuOp2_illegal_op, +/* 0xba */ x86emuOp2_btX_I, +/* 0xbb */ x86emuOp2_btc_R, +/* 0xbc */ x86emuOp2_bsf, +/* 0xbd */ x86emuOp2_bsr, +/* 0xbe */ x86emuOp2_movsx_byte_R_RM, +/* 0xbf */ x86emuOp2_movsx_word_R_RM, + +/* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc2 */ x86emuOp2_illegal_op, +/* 0xc3 */ x86emuOp2_illegal_op, +/* 0xc4 */ x86emuOp2_illegal_op, +/* 0xc5 */ x86emuOp2_illegal_op, +/* 0xc6 */ x86emuOp2_illegal_op, +/* 0xc7 */ x86emuOp2_illegal_op, +/* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */ + +/* 0xd0 */ x86emuOp2_illegal_op, +/* 0xd1 */ x86emuOp2_illegal_op, +/* 0xd2 */ x86emuOp2_illegal_op, +/* 0xd3 */ x86emuOp2_illegal_op, +/* 0xd4 */ x86emuOp2_illegal_op, +/* 0xd5 */ x86emuOp2_illegal_op, +/* 0xd6 */ x86emuOp2_illegal_op, +/* 0xd7 */ x86emuOp2_illegal_op, +/* 0xd8 */ x86emuOp2_illegal_op, +/* 0xd9 */ x86emuOp2_illegal_op, +/* 0xda */ x86emuOp2_illegal_op, +/* 0xdb */ x86emuOp2_illegal_op, +/* 0xdc */ x86emuOp2_illegal_op, +/* 0xdd */ x86emuOp2_illegal_op, +/* 0xde */ x86emuOp2_illegal_op, +/* 0xdf */ x86emuOp2_illegal_op, + +/* 0xe0 */ x86emuOp2_illegal_op, +/* 0xe1 */ x86emuOp2_illegal_op, +/* 0xe2 */ x86emuOp2_illegal_op, +/* 0xe3 */ x86emuOp2_illegal_op, +/* 0xe4 */ x86emuOp2_illegal_op, +/* 0xe5 */ x86emuOp2_illegal_op, +/* 0xe6 */ x86emuOp2_illegal_op, +/* 0xe7 */ x86emuOp2_illegal_op, +/* 0xe8 */ x86emuOp2_illegal_op, +/* 0xe9 */ x86emuOp2_illegal_op, +/* 0xea */ x86emuOp2_illegal_op, +/* 0xeb */ x86emuOp2_illegal_op, +/* 0xec */ x86emuOp2_illegal_op, +/* 0xed */ x86emuOp2_illegal_op, +/* 0xee */ x86emuOp2_illegal_op, +/* 0xef */ x86emuOp2_illegal_op, + +/* 0xf0 */ x86emuOp2_illegal_op, +/* 0xf1 */ x86emuOp2_illegal_op, +/* 0xf2 */ x86emuOp2_illegal_op, +/* 0xf3 */ x86emuOp2_illegal_op, +/* 0xf4 */ x86emuOp2_illegal_op, +/* 0xf5 */ x86emuOp2_illegal_op, +/* 0xf6 */ x86emuOp2_illegal_op, +/* 0xf7 */ x86emuOp2_illegal_op, +/* 0xf8 */ x86emuOp2_illegal_op, +/* 0xf9 */ x86emuOp2_illegal_op, +/* 0xfa */ x86emuOp2_illegal_op, +/* 0xfb */ x86emuOp2_illegal_op, +/* 0xfc */ x86emuOp2_illegal_op, +/* 0xfd */ x86emuOp2_illegal_op, +/* 0xfe */ x86emuOp2_illegal_op, +/* 0xff */ x86emuOp2_illegal_op, +}; diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c b/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c new file mode 100644 index 0000000..72b1bf2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c @@ -0,0 +1,2914 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the primitive +* machine operations used by the emulation code in ops.c +* +* Carry Chain Calculation +* +* This represents a somewhat expensive calculation which is +* apparently required to emulate the setting of the OF and AF flag. +* The latter is not so important, but the former is. The overflow +* flag is the XOR of the top two bits of the carry chain for an +* addition (similar for subtraction). Since we do not want to +* simulate the addition in a bitwise manner, we try to calculate the +* carry chain given the two operands and the result. +* +* So, given the following table, which represents the addition of two +* bits, we can derive a formula for the carry chain. +* +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 +* +* By inspection, one gets: cc = ab + r'(a + b) +* +* That represents alot of operations, but NO CHOICE.... +* +* Borrow Chain Calculation. +* +* The following table represents the subtraction of two bits, from +* which we can derive a formula for the borrow chain. +* +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 +* +* By inspection, one gets: bc = a'b + r(a' + b) +* +****************************************************************************/ + +#define PRIM_OPS_NO_REDEFINE_ASM +#include "x86emu/x86emui.h" + +/*------------------------- Global Variables ------------------------------*/ + +#ifndef __HAVE_INLINE_ASSEMBLER__ + +static u32 x86emu_parity_tab[8] = +{ + 0x96696996, + 0x69969669, + 0x69969669, + 0x96696996, + 0x69969669, + 0x96696996, + 0x96696996, + 0x69969669, +}; + +#endif + +#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) + +/*----------------------------- Implementation ----------------------------*/ + +#ifndef __HAVE_INLINE_ASSEMBLER__ + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aaa_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aas_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAD instruction and side effects. +****************************************************************************/ +u16 aad_word(u16 d) +{ + u16 l; + u8 hb, lb; + + hb = (u8)((d >> 8) & 0xff); + lb = (u8)((d & 0xff)); + l = (u16)((lb + 10 * hb) & 0xFF); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the AAM instruction and side effects. +****************************************************************************/ +u16 aam_word(u8 d) +{ + u16 h, l; + + h = (u16)(d / 10); + l = (u16)(d % 10); + l |= (u16)(h << 8); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u8 adc_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u16 adc_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u32 adc_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + if (ACCESS_FLAG(F_CF)) { + lo = 1 + (d & 0xFFFF) + (s & 0xFFFF); + res = 1 + d + s; + } + else { + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + } + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u8 add_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u16 add_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u32 add_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u8 and_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u16 and_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u32 and_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u8 cmp_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CLEAR_FLAG(F_CF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u16 cmp_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u32 cmp_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DAA instruction and side effects. +****************************************************************************/ +u8 daa_byte(u8 d) +{ + u32 res = d; + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + res += 6; + SET_FLAG(F_AF); + } + if (res > 0x9F || ACCESS_FLAG(F_CF)) { + res += 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xFF) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DAS instruction and side effects. +****************************************************************************/ +u8 das_byte(u8 d) +{ + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + d -= 6; + SET_FLAG(F_AF); + } + if (d > 0x9F || ACCESS_FLAG(F_CF)) { + d -= 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(d & 0x80, F_SF); + CONDITIONAL_SET_FLAG(d == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(d & 0xff), F_PF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u8 dec_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on sub_byte, uses s==1. */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u16 dec_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on the sub_byte routine, with s==1 */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u32 dec_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u8 inc_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = ((1 & d) | (~res)) & (1 | d); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u16 inc_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u32 inc_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 or_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d | s; + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 or_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d | s; + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 or_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d | s; + + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 neg_byte(u8 s) +{ + register u8 res; + register u8 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u8)-s; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 neg_word(u16 s) +{ + register u16 res; + register u16 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u16)-s; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 neg_long(u32 s) +{ + register u32 res; + register u32 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u32)-s; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u8 not_byte(u8 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u16 not_word(u16 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u32 not_long(u32 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u8 rcl_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + /* s is the rotate distance. It varies from 0 - 8. */ + /* have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + want to rotate through the carry by "s" bits. We could + loop, but that's inefficient. So the width is 9, + and we split into three parts: + + The new carry flag (was B_n) + the stuff in B_n-1 .. B_0 + the stuff in B_7 .. B_n+1 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the MSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(8-n) + 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 + 3) B_(n-1) <- cf + 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated + into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to + be causing OF to be misset */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF); + + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u16 rcl_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + res = d; + if ((cnt = s % 17) != 0) { + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u32 rcl_long(u32 d, u8 s) +{ + register u32 res, cnt, mask, cf; + + res = d; + if ((cnt = s % 33) != 0) { + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u8 rcr_byte(u8 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the LSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(n-1) + 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 3) B_(8-n) <- cf + 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to either + 0 if flag not set + non-zero if flag is set. + doing access_flag(..) != 0 casts that into either + 0..1 in any representation of the flags register + (i.e. packed bit array or unpacked.) + */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask + This is effectively done by shifting the + object to the right. The result must be masked, + in case the object came in and was treated + as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u16 rcr_word(u16 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 17) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u32 rcr_long(u32 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 33) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u8 rol_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate left */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 ... B_0 + + The new rotate is done mod 8. + Much simpler than the "rcl" or "rcr" operations. + + IF n > 0 + 1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) + 2) B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) + */ + res = d; + if ((cnt = s % 8) != 0) { + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of CF and the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u16 rol_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u32 rol_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u8 ror_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate right */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + B_7 ... B_0 + + The rotate is done mod 8. + + IF n > 0 + 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) + */ + res = d; + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of the two most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u16 ror_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u32 ror_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u8 shl_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (M.x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u16 shl_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u16) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u32 shl_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u8 shr_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u16 shr_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u32 shr_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u8 sar_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + res = d; + sf = d & 0x80; + cnt = s % 8; + if (cnt > 0 && cnt < 8) { + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + } else if (cnt >= 8) { + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u16 sar_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + sf = d & 0x8000; + cnt = s % 16; + res = d; + if (cnt > 0 && cnt < 16) { + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 16) { + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u32 sar_long(u32 d, u8 s) +{ + u32 cnt, res, cf, mask, sf; + + sf = d & 0x80000000; + cnt = s % 32; + res = d; + if (cnt > 0 && cnt < 32) { + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 32) { + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u16 shld_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16-cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u32 shld_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32-cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u16 shrd_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u32 shrd_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u8 sbb_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u16 sbb_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u32 sbb_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u8 sub_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u16 sub_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u32 sub_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u8 xor_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u16 xor_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u32 xor_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_byte(u8 s) +{ + s16 res = (s16)((s8)M.x86.R_AL * (s8)s); + + M.x86.R_AX = res; + if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || + ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_word(u16 s) +{ + s32 res = (s16)M.x86.R_AX * (s16)s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x00) || + ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 res = (s32)d * (s32)s; + + *res_lo = (u32)res; + *res_hi = (u32)(res >> 32); +#else + u32 d_lo,d_hi,d_sign; + u32 s_lo,s_hi,s_sign; + u32 rlo_lo,rlo_hi,rhi_lo; + + if ((d_sign = d & 0x80000000) != 0) + d = -d; + d_lo = d & 0xFFFF; + d_hi = d >> 16; + if ((s_sign = s & 0x80000000) != 0) + s = -s; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = d_lo * s_lo; + rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = d_hi * s_hi + (rlo_hi >> 16); + *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + *res_hi = rhi_lo; + if (d_sign != s_sign) { + d = ~*res_lo; + s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); + *res_lo = ~*res_lo+1; + *res_hi = ~*res_hi+(s >> 16); + } +#endif +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long(u32 s) +{ + imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); + if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00) || + ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_byte(u8 s) +{ + u16 res = (u16)(M.x86.R_AL * s); + + M.x86.R_AX = res; + if (M.x86.R_AH == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_word(u16 s) +{ + u32 res = M.x86.R_AX * s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (M.x86.R_DX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 res = (u32)M.x86.R_EAX * (u32)s; + + M.x86.R_EAX = (u32)res; + M.x86.R_EDX = (u32)(res >> 32); +#else + u32 a,a_lo,a_hi; + u32 s_lo,s_hi; + u32 rlo_lo,rlo_hi,rhi_lo; + + a = M.x86.R_EAX; + a_lo = a & 0xFFFF; + a_hi = a >> 16; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = a_lo * s_lo; + rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = a_hi * s_hi + (rlo_hi >> 16); + M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + M.x86.R_EDX = rhi_lo; +#endif + + if (M.x86.R_EDX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_byte(u8 s) +{ + s32 dvd, div, mod; + + dvd = (s16)M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s8)s; + mod = dvd % (s8)s; + if (abs(div) > 0x7f) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (s8) div; + M.x86.R_AH = (s8) mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_word(u16 s) +{ + s32 dvd, div, mod; + + dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s16)s; + mod = dvd % (s16)s; + if (abs(div) > 0x7fff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 dvd, div, mod; + + dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s32)s; + mod = dvd % (s32)s; + if (abs(div) > 0x7fffffff) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + u32 abs_s = s & 0x7FFFFFFF; + u32 abs_h_dvd = h_dvd & 0x7FFFFFFF; + u32 h_s = abs_s >> 1; + u32 l_s = abs_s << 31; + int counter = 31; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (abs_h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = abs_s << (--counter); + continue; + } else { + abs_h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = abs_s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (abs_h_dvd || (l_dvd > abs_s)) { + x86emu_intr_raise(0); + return; + } + /* sign */ + div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); + mod = l_dvd; + +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_byte(u8 s) +{ + u32 dvd, div, mod; + + dvd = M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u8)s; + mod = dvd % (u8)s; + if (abs(div) > 0xff) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (u8)div; + M.x86.R_AH = (u8)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_word(u16 s) +{ + u32 dvd, div, mod; + + dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u16)s; + mod = dvd % (u16)s; + if (abs(div) > 0xffff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 dvd, div, mod; + + dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u32)s; + mod = dvd % (u32)s; + if (abs(div) > 0xffffffff) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + + u32 h_s = s; + u32 l_s = 0; + int counter = 32; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = s << (--counter); + continue; + } else { + h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (h_dvd || (l_dvd > s)) { + x86emu_intr_raise(0); + return; + } + mod = l_dvd; +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +#endif /* __HAVE_INLINE_ASSEMBLER__ */ + +/**************************************************************************** +REMARKS: +Implements the IN string instruction and side effects. +****************************************************************************/ +void ins(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* in until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + + case 2: + while (count--) { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + case 4: + while (count--) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + M.x86.R_DI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + break; + case 2: + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + break; + case 4: + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + break; + } + M.x86.R_DI += inc; + } +} + +/**************************************************************************** +REMARKS: +Implements the OUT string instruction and side effects. +****************************************************************************/ +void outs(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* out until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + + case 2: + while (count--) { + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + case 4: + while (count--) { + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 2: + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 4: + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + break; + } + M.x86.R_SI += inc; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Address to fetch word from + +REMARKS: +Fetches a word from emulator memory using an absolute address. +****************************************************************************/ +u16 mem_access_word(int addr) +{ +DB( if (CHECK_MEM_ACCESS()) + x86emu_check_mem_access(addr);) + return (*sys_rdw)(addr); +} + +/**************************************************************************** +REMARKS: +Pushes a word onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_word(u16 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 2; + (*sys_wrw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pushes a long onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_long(u32 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 4; + (*sys_wrl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pops a word from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u16 pop_word(void) +{ + register u16 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 2; + return res; +} + +/**************************************************************************** +REMARKS: +Pops a long from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u32 pop_long(void) +{ + register u32 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 4; + return res; +} + +#ifdef __HAVE_INLINE_ASSEMBLER__ + +u16 aaa_word (u16 d) +{ return aaa_word_asm(&M.x86.R_EFLG,d); } + +u16 aas_word (u16 d) +{ return aas_word_asm(&M.x86.R_EFLG,d); } + +u16 aad_word (u16 d) +{ return aad_word_asm(&M.x86.R_EFLG,d); } + +u16 aam_word (u8 d) +{ return aam_word_asm(&M.x86.R_EFLG,d); } + +u8 adc_byte (u8 d, u8 s) +{ return adc_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 adc_word (u16 d, u16 s) +{ return adc_word_asm(&M.x86.R_EFLG,d,s); } + +u32 adc_long (u32 d, u32 s) +{ return adc_long_asm(&M.x86.R_EFLG,d,s); } + +u8 add_byte (u8 d, u8 s) +{ return add_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 add_word (u16 d, u16 s) +{ return add_word_asm(&M.x86.R_EFLG,d,s); } + +u32 add_long (u32 d, u32 s) +{ return add_long_asm(&M.x86.R_EFLG,d,s); } + +u8 and_byte (u8 d, u8 s) +{ return and_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 and_word (u16 d, u16 s) +{ return and_word_asm(&M.x86.R_EFLG,d,s); } + +u32 and_long (u32 d, u32 s) +{ return and_long_asm(&M.x86.R_EFLG,d,s); } + +u8 cmp_byte (u8 d, u8 s) +{ return cmp_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 cmp_word (u16 d, u16 s) +{ return cmp_word_asm(&M.x86.R_EFLG,d,s); } + +u32 cmp_long (u32 d, u32 s) +{ return cmp_long_asm(&M.x86.R_EFLG,d,s); } + +u8 daa_byte (u8 d) +{ return daa_byte_asm(&M.x86.R_EFLG,d); } + +u8 das_byte (u8 d) +{ return das_byte_asm(&M.x86.R_EFLG,d); } + +u8 dec_byte (u8 d) +{ return dec_byte_asm(&M.x86.R_EFLG,d); } + +u16 dec_word (u16 d) +{ return dec_word_asm(&M.x86.R_EFLG,d); } + +u32 dec_long (u32 d) +{ return dec_long_asm(&M.x86.R_EFLG,d); } + +u8 inc_byte (u8 d) +{ return inc_byte_asm(&M.x86.R_EFLG,d); } + +u16 inc_word (u16 d) +{ return inc_word_asm(&M.x86.R_EFLG,d); } + +u32 inc_long (u32 d) +{ return inc_long_asm(&M.x86.R_EFLG,d); } + +u8 or_byte (u8 d, u8 s) +{ return or_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 or_word (u16 d, u16 s) +{ return or_word_asm(&M.x86.R_EFLG,d,s); } + +u32 or_long (u32 d, u32 s) +{ return or_long_asm(&M.x86.R_EFLG,d,s); } + +u8 neg_byte (u8 s) +{ return neg_byte_asm(&M.x86.R_EFLG,s); } + +u16 neg_word (u16 s) +{ return neg_word_asm(&M.x86.R_EFLG,s); } + +u32 neg_long (u32 s) +{ return neg_long_asm(&M.x86.R_EFLG,s); } + +u8 not_byte (u8 s) +{ return not_byte_asm(&M.x86.R_EFLG,s); } + +u16 not_word (u16 s) +{ return not_word_asm(&M.x86.R_EFLG,s); } + +u32 not_long (u32 s) +{ return not_long_asm(&M.x86.R_EFLG,s); } + +u8 rcl_byte (u8 d, u8 s) +{ return rcl_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 rcl_word (u16 d, u8 s) +{ return rcl_word_asm(&M.x86.R_EFLG,d,s); } + +u32 rcl_long (u32 d, u8 s) +{ return rcl_long_asm(&M.x86.R_EFLG,d,s); } + +u8 rcr_byte (u8 d, u8 s) +{ return rcr_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 rcr_word (u16 d, u8 s) +{ return rcr_word_asm(&M.x86.R_EFLG,d,s); } + +u32 rcr_long (u32 d, u8 s) +{ return rcr_long_asm(&M.x86.R_EFLG,d,s); } + +u8 rol_byte (u8 d, u8 s) +{ return rol_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 rol_word (u16 d, u8 s) +{ return rol_word_asm(&M.x86.R_EFLG,d,s); } + +u32 rol_long (u32 d, u8 s) +{ return rol_long_asm(&M.x86.R_EFLG,d,s); } + +u8 ror_byte (u8 d, u8 s) +{ return ror_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 ror_word (u16 d, u8 s) +{ return ror_word_asm(&M.x86.R_EFLG,d,s); } + +u32 ror_long (u32 d, u8 s) +{ return ror_long_asm(&M.x86.R_EFLG,d,s); } + +u8 shl_byte (u8 d, u8 s) +{ return shl_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 shl_word (u16 d, u8 s) +{ return shl_word_asm(&M.x86.R_EFLG,d,s); } + +u32 shl_long (u32 d, u8 s) +{ return shl_long_asm(&M.x86.R_EFLG,d,s); } + +u8 shr_byte (u8 d, u8 s) +{ return shr_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 shr_word (u16 d, u8 s) +{ return shr_word_asm(&M.x86.R_EFLG,d,s); } + +u32 shr_long (u32 d, u8 s) +{ return shr_long_asm(&M.x86.R_EFLG,d,s); } + +u8 sar_byte (u8 d, u8 s) +{ return sar_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 sar_word (u16 d, u8 s) +{ return sar_word_asm(&M.x86.R_EFLG,d,s); } + +u32 sar_long (u32 d, u8 s) +{ return sar_long_asm(&M.x86.R_EFLG,d,s); } + +u16 shld_word (u16 d, u16 fill, u8 s) +{ return shld_word_asm(&M.x86.R_EFLG,d,fill,s); } + +u32 shld_long (u32 d, u32 fill, u8 s) +{ return shld_long_asm(&M.x86.R_EFLG,d,fill,s); } + +u16 shrd_word (u16 d, u16 fill, u8 s) +{ return shrd_word_asm(&M.x86.R_EFLG,d,fill,s); } + +u32 shrd_long (u32 d, u32 fill, u8 s) +{ return shrd_long_asm(&M.x86.R_EFLG,d,fill,s); } + +u8 sbb_byte (u8 d, u8 s) +{ return sbb_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 sbb_word (u16 d, u16 s) +{ return sbb_word_asm(&M.x86.R_EFLG,d,s); } + +u32 sbb_long (u32 d, u32 s) +{ return sbb_long_asm(&M.x86.R_EFLG,d,s); } + +u8 sub_byte (u8 d, u8 s) +{ return sub_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 sub_word (u16 d, u16 s) +{ return sub_word_asm(&M.x86.R_EFLG,d,s); } + +u32 sub_long (u32 d, u32 s) +{ return sub_long_asm(&M.x86.R_EFLG,d,s); } + +void test_byte (u8 d, u8 s) +{ test_byte_asm(&M.x86.R_EFLG,d,s); } + +void test_word (u16 d, u16 s) +{ test_word_asm(&M.x86.R_EFLG,d,s); } + +void test_long (u32 d, u32 s) +{ test_long_asm(&M.x86.R_EFLG,d,s); } + +u8 xor_byte (u8 d, u8 s) +{ return xor_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 xor_word (u16 d, u16 s) +{ return xor_word_asm(&M.x86.R_EFLG,d,s); } + +u32 xor_long (u32 d, u32 s) +{ return xor_long_asm(&M.x86.R_EFLG,d,s); } + +void imul_byte (u8 s) +{ imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); } + +void imul_word (u16 s) +{ imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); } + +void imul_long (u32 s) +{ imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); } + +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) +{ imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s); } + +void mul_byte (u8 s) +{ mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); } + +void mul_word (u16 s) +{ mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); } + +void mul_long (u32 s) +{ mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); } + +void idiv_byte (u8 s) +{ idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); } + +void idiv_word (u16 s) +{ idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); } + +void idiv_long (u32 s) +{ idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); } + +void div_byte (u8 s) +{ div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); } + +void div_word (u16 s) +{ div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); } + +void div_long (u32 s) +{ div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); } + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/sys.c b/board/MAI/bios_emulator/scitech/src/x86emu/sys.c new file mode 100644 index 0000000..afe58f8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/sys.c @@ -0,0 +1,658 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* programmed I/O and memory access. Included in this module +* are default functions with limited usefulness. For real +* uses these functions will most likely be overriden by the +* user library. +* +****************************************************************************/ + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/prim_ops.h" +#include + +/*------------------------- Global Variables ------------------------------*/ + +X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ +X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*----------------------------- Implementation ----------------------------*/ +#ifdef __alpha__ +/* to cope with broken egcs-1.1.2 :-(((( */ + +/* + * inline functions to do unaligned accesses + * from linux/include/asm-alpha/unaligned.h + */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; +#endif + +static __inline__ unsigned long ldq_u(unsigned long * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extql %0,%2,%0\n\t" + "extqh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(7+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldl_u(unsigned int * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extll %0,%2,%0\n\t" + "extlh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(3+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldw_u(unsigned short * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extwl %0,%2,%0\n\t" + "extwh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(1+(char *) r11))); + return r1 | r2; +#endif +} + +/* + * Elemental unaligned stores + */ + +static __inline__ void stq_u(unsigned long r5, unsigned long * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "insqh %6,%7,%5\n\t" + "insql %6,%7,%4\n\t" + "mskqh %3,%7,%3\n\t" + "mskql %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(7+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stl_u(unsigned long r5, unsigned int * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inslh %6,%7,%5\n\t" + "insll %6,%7,%4\n\t" + "msklh %3,%7,%3\n\t" + "mskll %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(3+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stw_u(unsigned long r5, unsigned short * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inswh %6,%7,%5\n\t" + "inswl %6,%7,%4\n\t" + "mskwh %3,%7,%3\n\t" + "mskwl %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(1+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +#elif defined (__ia64__) +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +static __inline__ unsigned long +__uldq (const unsigned long * r11) +{ + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldl (const unsigned int * r11) +{ + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldw (const unsigned short * r11) +{ + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +} + +static __inline__ void +ustq (unsigned long r5, unsigned long * r11) +{ + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustl (unsigned long r5, unsigned int * r11) +{ + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustw (unsigned long r5, unsigned short * r11) +{ + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +} + +#endif + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. +****************************************************************************/ +u8 X86API rdb( + u32 addr) +{ + u8 val; + + if (addr > M.mem_size - 1) { + DB(printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + val = *(u8*)(M.mem_base + addr); +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 1 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. +****************************************************************************/ +u16 X86API rdw( + u32 addr) +{ + u16 val = 0; + + if (addr > M.mem_size - 2) { + DB(printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + val = (*(u8*)(M.mem_base + addr) | + (*(u8*)(M.mem_base + addr + 1) << 8)); + } + else +#endif +#ifdef __alpha__ + val = ldw_u((u16*)(M.mem_base + addr)); +#elif defined (__ia64__) + val = uldw((u16*)(M.mem_base + addr)); +#else + val = *(u16*)(M.mem_base + addr); +#endif + DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 2 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. +REMARKS: +Reads a long value from the emulator memory. +****************************************************************************/ +u32 X86API rdl( + u32 addr) +{ + u32 val = 0; + + if (addr > M.mem_size - 4) { + DB(printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + val = (*(u8*)(M.mem_base + addr + 0) | + (*(u8*)(M.mem_base + addr + 1) << 8) | + (*(u8*)(M.mem_base + addr + 2) << 16) | + (*(u8*)(M.mem_base + addr + 3) << 24)); + } + else +#endif +#ifdef __alpha__ + val = ldl_u((u32*)(M.mem_base + addr)); +#elif defined (__ia64__) + val = uldl((u32*)(M.mem_base + addr)); +#else + val = *(u32*)(M.mem_base + addr); +#endif +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 4 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. +****************************************************************************/ +void X86API wrb( + u32 addr, + u8 val) +{ +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 1 <- %#x\n", addr, val);) + if (addr > M.mem_size - 1) { + DB(printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + *(u8*)(M.mem_base + addr) = val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. +****************************************************************************/ +void X86API wrw( + u32 addr, + u16 val) +{ +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 2 <- %#x\n", addr, val);) + if (addr > M.mem_size - 2) { + DB(printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + } + else +#endif +#ifdef __alpha__ + stw_u(val,(u16*)(M.mem_base + addr)); +#elif defined (__ia64__) + ustw(val,(u16*)(M.mem_base + addr)); +#else + *(u16*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a long value to emulator memory. +****************************************************************************/ +void X86API wrl( + u32 addr, + u32 val) +{ +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 4 <- %#x\n", addr, val);) + if (addr > M.mem_size - 4) { + DB(printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else +#endif +#ifdef __alpha__ + stl_u(val,(u32*)(M.mem_base + addr)); +#elif defined (__ia64__) + ustl(val,(u32*)(M.mem_base + addr)); +#else + *(u32*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO byte read function. Doesn't perform real inb. +****************************************************************************/ +static u8 X86API p_inb( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + printk("inb %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO word read function. Doesn't perform real inw. +****************************************************************************/ +static u16 X86API p_inw( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + printk("inw %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO long read function. Doesn't perform real inl. +****************************************************************************/ +static u32 X86API p_inl( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + printk("inl %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO byte write function. Doesn't perform real outb. +****************************************************************************/ +static void X86API p_outb( + X86EMU_pioAddr addr, + u8 val) +{ +DB( if (DEBUG_IO_TRACE()) + printk("outb %#02x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO word write function. Doesn't perform real outw. +****************************************************************************/ +static void X86API p_outw( + X86EMU_pioAddr addr, + u16 val) +{ +DB( if (DEBUG_IO_TRACE()) + printk("outw %#04x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO ;ong write function. Doesn't perform real outl. +****************************************************************************/ +static void X86API p_outl( + X86EMU_pioAddr addr, + u32 val) +{ +DB( if (DEBUG_IO_TRACE()) + printk("outl %#08x -> %#04x \n", val, addr);) + return; +} + +/*------------------------- Global Variables ------------------------------*/ + +u8 (X86APIP sys_rdb)(u32 addr) = rdb; +u16 (X86APIP sys_rdw)(u32 addr) = rdw; +u32 (X86APIP sys_rdl)(u32 addr) = rdl; +void (X86APIP sys_wrb)(u32 addr,u8 val) = wrb; +void (X86APIP sys_wrw)(u32 addr,u16 val) = wrw; +void (X86APIP sys_wrl)(u32 addr,u32 val) = wrl; +u8 (X86APIP sys_inb)(X86EMU_pioAddr addr) = p_inb; +u16 (X86APIP sys_inw)(X86EMU_pioAddr addr) = p_inw; +u32 (X86APIP sys_inl)(X86EMU_pioAddr addr) = p_inl; +void (X86APIP sys_outb)(X86EMU_pioAddr addr, u8 val) = p_outb; +void (X86APIP sys_outw)(X86EMU_pioAddr addr, u16 val) = p_outw; +void (X86APIP sys_outl)(X86EMU_pioAddr addr, u32 val) = p_outl; + +/*----------------------------- Setup -------------------------------------*/ + +/**************************************************************************** +PARAMETERS: +funcs - New memory function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +memory space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupMemFuncs( + X86EMU_memFuncs *funcs) +{ + sys_rdb = funcs->rdb; + sys_rdw = funcs->rdw; + sys_rdl = funcs->rdl; + sys_wrb = funcs->wrb; + sys_wrw = funcs->wrw; + sys_wrl = funcs->wrl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New programmed I/O function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +I/O space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupPioFuncs( + X86EMU_pioFuncs *funcs) +{ + sys_inb = funcs->inb; + sys_inw = funcs->inw; + sys_inl = funcs->inl; + sys_outb = funcs->outb; + sys_outw = funcs->outw; + sys_outl = funcs->outl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New interrupt vector table to make active + +REMARKS: +This function is used to set the pointers to functions which handle +interrupt processing in the emulator, allowing the user application to +hook interrupts as necessary for their application. Any interrupts that +are not hooked by the user application, and reflected and handled internally +in the emulator via the interrupt vector table. This allows the application +to get control when the code being emulated executes specific software +interrupts. +****************************************************************************/ +void X86EMU_setupIntrFuncs( + X86EMU_intrFuncs funcs[]) +{ + int i; + + for (i=0; i < 256; i++) + _X86EMU_intrTab[i] = NULL; + if (funcs) { + for (i = 0; i < 256; i++) + _X86EMU_intrTab[i] = funcs[i]; + } +} + +/**************************************************************************** +PARAMETERS: +int - New software interrupt to prepare for + +REMARKS: +This function is used to set up the emulator state to exceute a software +interrupt. This can be used by the user application code to allow an +interrupt to be hooked, examined and then reflected back to the emulator +so that the code in the emulator will continue processing the software +interrupt as per normal. This essentially allows system code to actively +hook and handle certain software interrupts as necessary. +****************************************************************************/ +void X86EMU_prepareForInt( + int num) +{ + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(num * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(num * 4); + M.x86.intr = 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/validate.c b/board/MAI/bios_emulator/scitech/src/x86emu/validate.c new file mode 100644 index 0000000..c951301 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/validate.c @@ -0,0 +1,765 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: Watcom C 10.6 or later +* Environment: 32-bit DOS +* Developer: Kendall Bennett +* +* Description: Program to validate the x86 emulator library for +* correctness. We run the emulator primitive operations +* functions against the real x86 CPU, and compare the result +* and flags to ensure correctness. +* +* We use inline assembler to compile and build this program. +* +****************************************************************************/ + +#include +#include +#include +#include +#include "x86emu.h" +#include "x86emu/prim_asm.h" + +/*-------------------------- Implementation -------------------------------*/ + +#define true 1 +#define false 0 + +#define ALL_FLAGS (F_CF | F_PF | F_AF | F_ZF | F_SF | F_OF) + +#define VAL_START_BINARY(parm_type,res_type,dmax,smax,dincr,sincr) \ +{ \ + parm_type d,s; \ + res_type r,r_asm; \ + ulong flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < dmax; d += dincr) { \ + for (s = 0; s < smax; s += sincr) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { + +#define VAL_TEST_BINARY(name) \ + r_asm = name##_asm(&flags,d,s); \ + r = name(d,s); \ + if (r != r_asm || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { + +#define VAL_TEST_BINARY_VOID(name) \ + name##_asm(&flags,d,s); \ + name(d,s); \ + r = r_asm = 0; \ + if (M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { + +#define VAL_FAIL_BYTE_BYTE_BINARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ + r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_WORD_WORD_BINARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ + r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_LONG_LONG_BINARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ + r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_END_BINARY() \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_BYTE_BYTE_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_BYTE_BYTE_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_WORD_WORD_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_WORD_WORD_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_LONG_LONG_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_LONG_LONG_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_VOID_BYTE_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1) \ + VAL_TEST_BINARY_VOID(name) \ + VAL_FAIL_BYTE_BYTE_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_VOID_WORD_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \ + VAL_TEST_BINARY_VOID(name) \ + VAL_FAIL_WORD_WORD_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_VOID_LONG_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \ + VAL_TEST_BINARY_VOID(name) \ + VAL_FAIL_LONG_LONG_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_BYTE_ROTATE(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u8,u8,0xFF,8,1,1) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_BYTE_BYTE_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_WORD_ROTATE(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u16,u16,0xFF00,16,0x100,1) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_WORD_WORD_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_LONG_ROTATE(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u32,u32,0xFF000000,32,0x1000000,1) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_LONG_LONG_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_START_TERNARY(parm_type,res_type,dmax,smax,dincr,sincr,maxshift)\ +{ \ + parm_type d,s; \ + res_type r,r_asm; \ + u8 shift; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < dmax; d += dincr) { \ + for (s = 0; s < smax; s += sincr) { \ + for (shift = 0; shift < maxshift; shift += 1) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { + +#define VAL_TEST_TERNARY(name) \ + r_asm = name##_asm(&flags,d,s,shift); \ + r = name(d,s,shift); \ + if (r != r_asm || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { + +#define VAL_FAIL_WORD_WORD_TERNARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n", \ + r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_LONG_LONG_TERNARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n", \ + r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_END_TERNARY() \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_WORD_ROTATE_DBL(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_TERNARY(u16,u16,0xFF00,0xFF00,0x100,0x100,16) \ + VAL_TEST_TERNARY(name) \ + VAL_FAIL_WORD_WORD_TERNARY(name) \ + VAL_END_TERNARY() + +#define VAL_LONG_ROTATE_DBL(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_TERNARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000,32) \ + VAL_TEST_TERNARY(name) \ + VAL_FAIL_LONG_LONG_TERNARY(name) \ + VAL_END_TERNARY() + +#define VAL_START_UNARY(parm_type,max,incr) \ +{ \ + parm_type d,r,r_asm; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < max; d += incr) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { + +#define VAL_TEST_UNARY(name) \ + r_asm = name##_asm(&flags,d); \ + r = name(d); \ + if (r != r_asm || M.x86.R_EFLG != flags) { \ + failed = true; + +#define VAL_FAIL_BYTE_UNARY(name) \ + printk("fail\n"); \ + printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n", \ + r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_WORD_UNARY(name) \ + printk("fail\n"); \ + printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n", \ + r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_LONG_UNARY(name) \ + printk("fail\n"); \ + printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n", \ + r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_END_UNARY() \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | ALL_FLAGS; \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_BYTE_UNARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_UNARY(u8,0xFF,0x1) \ + VAL_TEST_UNARY(name) \ + VAL_FAIL_BYTE_UNARY(name) \ + VAL_END_UNARY() + +#define VAL_WORD_UNARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_UNARY(u16,0xFF00,0x100) \ + VAL_TEST_UNARY(name) \ + VAL_FAIL_WORD_UNARY(name) \ + VAL_END_UNARY() + +#define VAL_WORD_BYTE_UNARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_UNARY(u16,0xFF,0x1) \ + VAL_TEST_UNARY(name) \ + VAL_FAIL_WORD_UNARY(name) \ + VAL_END_UNARY() + +#define VAL_LONG_UNARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_UNARY(u32,0xFF000000,0x1000000) \ + VAL_TEST_UNARY(name) \ + VAL_FAIL_LONG_UNARY(name) \ + VAL_END_UNARY() + +#define VAL_BYTE_MUL(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u8 d,s; \ + u16 r,r_asm; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF; d += 1) { \ + for (s = 0; s < 0xFF; s += 1) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + name##_asm(&flags,&r_asm,d,s); \ + M.x86.R_AL = d; \ + name(s); \ + r = M.x86.R_AX; \ + if (r != r_asm || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ + r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_WORD_MUL(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u16 d,s; \ + u16 r_lo,r_asm_lo; \ + u16 r_hi,r_asm_hi; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF00; d += 0x100) { \ + for (s = 0; s < 0xFF00; s += 0x100) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s); \ + M.x86.R_AX = d; \ + name(s); \ + r_lo = M.x86.R_AX; \ + r_hi = M.x86.R_DX; \ + if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ + r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ + r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_LONG_MUL(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u32 d,s; \ + u32 r_lo,r_asm_lo; \ + u32 r_hi,r_asm_hi; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF000000; d += 0x1000000) { \ + for (s = 0; s < 0xFF000000; s += 0x1000000) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s); \ + M.x86.R_EAX = d; \ + name(s); \ + r_lo = M.x86.R_EAX; \ + r_hi = M.x86.R_EDX; \ + if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ + r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ + r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_BYTE_DIV(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u16 d,s; \ + u8 r_quot,r_rem,r_asm_quot,r_asm_rem; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF00; d += 0x100) { \ + for (s = 1; s < 0xFF; s += 1) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + M.x86.intr = 0; \ + M.x86.R_AX = d; \ + name(s); \ + r_quot = M.x86.R_AL; \ + r_rem = M.x86.R_AH; \ + if (M.x86.intr & INTR_SYNCH) \ + continue; \ + name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,s); \ + if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n", \ + r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n", \ + r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_WORD_DIV(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u32 d,s; \ + u16 r_quot,r_rem,r_asm_quot,r_asm_rem; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF000000; d += 0x1000000) { \ + for (s = 0x100; s < 0xFF00; s += 0x100) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + M.x86.intr = 0; \ + M.x86.R_AX = d & 0xFFFF; \ + M.x86.R_DX = d >> 16; \ + name(s); \ + r_quot = M.x86.R_AX; \ + r_rem = M.x86.R_DX; \ + if (M.x86.intr & INTR_SYNCH) \ + continue; \ + name##_asm(&flags,&r_asm_quot,&r_asm_rem,d & 0xFFFF,d >> 16,s);\ + if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n", \ + r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n", \ + r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_LONG_DIV(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u32 d,s; \ + u32 r_quot,r_rem,r_asm_quot,r_asm_rem; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF000000; d += 0x1000000) { \ + for (s = 0x100; s < 0xFF00; s += 0x100) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + M.x86.intr = 0; \ + M.x86.R_EAX = d; \ + M.x86.R_EDX = 0; \ + name(s); \ + r_quot = M.x86.R_EAX; \ + r_rem = M.x86.R_EDX; \ + if (M.x86.intr & INTR_SYNCH) \ + continue; \ + name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,0,s); \ + if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n", \ + r_quot, r_rem, #name, 0, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n", \ + r_asm_quot, r_asm_rem, #name"_asm", 0, d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +void printk(const char *fmt, ...) +{ + va_list argptr; + va_start(argptr, fmt); + vfprintf(stdout, fmt, argptr); + fflush(stdout); + va_end(argptr); +} + +char * print_flags(char *buf,ulong flags) +{ + char *separator = ""; + + buf[0] = 0; + if (flags & F_CF) { + strcat(buf,separator); + strcat(buf,"CF"); + separator = ","; + } + if (flags & F_PF) { + strcat(buf,separator); + strcat(buf,"PF"); + separator = ","; + } + if (flags & F_AF) { + strcat(buf,separator); + strcat(buf,"AF"); + separator = ","; + } + if (flags & F_ZF) { + strcat(buf,separator); + strcat(buf,"ZF"); + separator = ","; + } + if (flags & F_SF) { + strcat(buf,separator); + strcat(buf,"SF"); + separator = ","; + } + if (flags & F_OF) { + strcat(buf,separator); + strcat(buf,"OF"); + separator = ","; + } + if (separator[0] == 0) + strcpy(buf,"None"); + return buf; +} + +int main(int argc) +{ + ulong def_flags; + int trace = false; + + if (argc > 1) + trace = true; + memset(&M, 0, sizeof(M)); + def_flags = get_flags_asm() & ~ALL_FLAGS; + + VAL_WORD_UNARY(aaa_word); + VAL_WORD_UNARY(aas_word); + + VAL_WORD_UNARY(aad_word); + VAL_WORD_UNARY(aam_word); + + VAL_BYTE_BYTE_BINARY(adc_byte); + VAL_WORD_WORD_BINARY(adc_word); + VAL_LONG_LONG_BINARY(adc_long); + + VAL_BYTE_BYTE_BINARY(add_byte); + VAL_WORD_WORD_BINARY(add_word); + VAL_LONG_LONG_BINARY(add_long); + + VAL_BYTE_BYTE_BINARY(and_byte); + VAL_WORD_WORD_BINARY(and_word); + VAL_LONG_LONG_BINARY(and_long); + + VAL_BYTE_BYTE_BINARY(cmp_byte); + VAL_WORD_WORD_BINARY(cmp_word); + VAL_LONG_LONG_BINARY(cmp_long); + + VAL_BYTE_UNARY(daa_byte); + VAL_BYTE_UNARY(das_byte); /* Fails for 0x9A (out of range anyway) */ + + VAL_BYTE_UNARY(dec_byte); + VAL_WORD_UNARY(dec_word); + VAL_LONG_UNARY(dec_long); + + VAL_BYTE_UNARY(inc_byte); + VAL_WORD_UNARY(inc_word); + VAL_LONG_UNARY(inc_long); + + VAL_BYTE_BYTE_BINARY(or_byte); + VAL_WORD_WORD_BINARY(or_word); + VAL_LONG_LONG_BINARY(or_long); + + VAL_BYTE_UNARY(neg_byte); + VAL_WORD_UNARY(neg_word); + VAL_LONG_UNARY(neg_long); + + VAL_BYTE_UNARY(not_byte); + VAL_WORD_UNARY(not_word); + VAL_LONG_UNARY(not_long); + + VAL_BYTE_ROTATE(rcl_byte); + VAL_WORD_ROTATE(rcl_word); + VAL_LONG_ROTATE(rcl_long); + + VAL_BYTE_ROTATE(rcr_byte); + VAL_WORD_ROTATE(rcr_word); + VAL_LONG_ROTATE(rcr_long); + + VAL_BYTE_ROTATE(rol_byte); + VAL_WORD_ROTATE(rol_word); + VAL_LONG_ROTATE(rol_long); + + VAL_BYTE_ROTATE(ror_byte); + VAL_WORD_ROTATE(ror_word); + VAL_LONG_ROTATE(ror_long); + + VAL_BYTE_ROTATE(shl_byte); + VAL_WORD_ROTATE(shl_word); + VAL_LONG_ROTATE(shl_long); + + VAL_BYTE_ROTATE(shr_byte); + VAL_WORD_ROTATE(shr_word); + VAL_LONG_ROTATE(shr_long); + + VAL_BYTE_ROTATE(sar_byte); + VAL_WORD_ROTATE(sar_word); + VAL_LONG_ROTATE(sar_long); + + VAL_WORD_ROTATE_DBL(shld_word); + VAL_LONG_ROTATE_DBL(shld_long); + + VAL_WORD_ROTATE_DBL(shrd_word); + VAL_LONG_ROTATE_DBL(shrd_long); + + VAL_BYTE_BYTE_BINARY(sbb_byte); + VAL_WORD_WORD_BINARY(sbb_word); + VAL_LONG_LONG_BINARY(sbb_long); + + VAL_BYTE_BYTE_BINARY(sub_byte); + VAL_WORD_WORD_BINARY(sub_word); + VAL_LONG_LONG_BINARY(sub_long); + + VAL_BYTE_BYTE_BINARY(xor_byte); + VAL_WORD_WORD_BINARY(xor_word); + VAL_LONG_LONG_BINARY(xor_long); + + VAL_VOID_BYTE_BINARY(test_byte); + VAL_VOID_WORD_BINARY(test_word); + VAL_VOID_LONG_BINARY(test_long); + + VAL_BYTE_MUL(imul_byte); + VAL_WORD_MUL(imul_word); + VAL_LONG_MUL(imul_long); + + VAL_BYTE_MUL(mul_byte); + VAL_WORD_MUL(mul_word); + VAL_LONG_MUL(mul_long); + + VAL_BYTE_DIV(idiv_byte); + VAL_WORD_DIV(idiv_word); + VAL_LONG_DIV(idiv_long); + + VAL_BYTE_DIV(div_byte); + VAL_WORD_DIV(div_word); + VAL_LONG_DIV(div_long); + + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h new file mode 100644 index 0000000..9a4a096 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h @@ -0,0 +1,210 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for debug definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_DEBUG_H +#define __X86EMU_DEBUG_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* checks to be enabled for "runtime" */ + +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ + +#ifdef DEBUG +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +#else +# define CHECK_IP_FETCH() +# define CHECK_SP_ACCESS() +# define CHECK_MEM_ACCESS() +# define CHECK_DATA_ACCESS() +#endif + +#ifdef DEBUG +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) +#else +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 +# define DEBUG_DECODE_NOPRINT() 0 +#endif + +#ifdef DEBUG + +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) + +/* + * The following allow us to look at the bytes of an instruction. The + * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * the decoding process. The SAVE_IP_CS is called initially when the + * major opcode of the instruction is accessed. + */ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) + +#define SAVE_IP_CS(x,y) \ + if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ + } +#else +# define INC_DECODED_INST_LEN(x) +# define DECODE_PRINTF(x) +# define DECODE_PRINTF2(x,y) +# define SAVE_IP_CS(x,y) +#endif + +#ifdef DEBUG +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ + if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() +#else +# define TRACE_REGS() +#endif + +#ifdef DEBUG +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +#else +# define SINGLE_STEP() +#endif + +#define TRACE_AND_STEP() \ + TRACE_REGS(); \ + SINGLE_STEP() + +#ifdef DEBUG +# define START_OF_INSTR() +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); +#else +# define START_OF_INSTR() +# define END_OF_INSTR() +# define END_OF_INSTR_NO_TRACE() +#endif + +#ifdef DEBUG +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: %s\n",u,v,n); +#else +# define CALL_TRACE(u,v,w,x,s) +# define RETURN_TRACE(n,u,v) +#endif + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern void x86emu_inc_decoded_inst_len (int x); +extern void x86emu_decode_printf (char *x); +extern void x86emu_decode_printf2 (char *x, int y); +extern void x86emu_just_disassemble (void); +extern void x86emu_single_step (void); +extern void x86emu_end_instr (void); +extern void x86emu_dump_regs (void); +extern void x86emu_dump_xregs (void); +extern void x86emu_print_int_vect (u16 iv); +extern void x86emu_instrument_instruction (void); +extern void x86emu_check_ip_access (void); +extern void x86emu_check_sp_access (void); +extern void x86emu_check_mem_access (u32 p); +extern void x86emu_check_data_access (uint s, uint o); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DEBUG_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h new file mode 100644 index 0000000..321a345 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h @@ -0,0 +1,87 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for instruction decoding logic. +* +****************************************************************************/ + +#ifndef __X86EMU_DECODE_H +#define __X86EMU_DECODE_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Instruction Decoding Stuff */ + +#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) +#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) +#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) +#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void x86emu_intr_raise (u8 type); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); +u8* decode_rm_byte_register(int reg); +u16* decode_rm_word_register(int reg); +u32* decode_rm_long_register(int reg); +u16* decode_rm_seg_register(int reg); +unsigned decode_rm00_address(int rm); +unsigned decode_rm01_address(int rm); +unsigned decode_rm10_address(int rm); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DECODE_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h new file mode 100644 index 0000000..5fb2714 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h @@ -0,0 +1,61 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU instruction decoding. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_H +#define __X86EMU_FPU_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* these have to be defined, whether 8087 support compiled in or not. */ + +extern void x86emuOp_esc_coprocess_d8 (u8 op1); +extern void x86emuOp_esc_coprocess_d9 (u8 op1); +extern void x86emuOp_esc_coprocess_da (u8 op1); +extern void x86emuOp_esc_coprocess_db (u8 op1); +extern void x86emuOp_esc_coprocess_dc (u8 op1); +extern void x86emuOp_esc_coprocess_dd (u8 op1); +extern void x86emuOp_esc_coprocess_de (u8 op1); +extern void x86emuOp_esc_coprocess_df (u8 op1); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_FPU_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h new file mode 100644 index 0000000..65ea676 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for operand decoding functions. +* +****************************************************************************/ + +#ifndef __X86EMU_OPS_H +#define __X86EMU_OPS_H + +extern void (*x86emu_optab[0x100])(u8 op1); +extern void (*x86emu_optab2[0x100])(u8 op2); + +#endif /* __X86EMU_OPS_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h new file mode 100644 index 0000000..e023cf8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h @@ -0,0 +1,970 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: Watcom C++ 10.6 or later +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Inline assembler versions of the primitive operand +* functions for faster performance. At the moment this is +* x86 inline assembler, but these functions could be replaced +* with native inline assembler for each supported processor +* platform. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_ASM_H +#define __X86EMU_PRIM_ASM_H + +#ifdef __WATCOMC__ + +#ifndef VALIDATE +#define __HAVE_INLINE_ASSEMBLER__ +#endif + +u32 get_flags_asm(void); +#pragma aux get_flags_asm = \ + "pushf" \ + "pop eax" \ + value [eax] \ + modify exact [eax]; + +u16 aaa_word_asm(u32 *flags,u16 d); +#pragma aux aaa_word_asm = \ + "push [edi]" \ + "popf" \ + "aaa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aas_word_asm(u32 *flags,u16 d); +#pragma aux aas_word_asm = \ + "push [edi]" \ + "popf" \ + "aas" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aad_word_asm(u32 *flags,u16 d); +#pragma aux aad_word_asm = \ + "push [edi]" \ + "popf" \ + "aad" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aam_word_asm(u32 *flags,u8 d); +#pragma aux aam_word_asm = \ + "push [edi]" \ + "popf" \ + "aam" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [ax] \ + modify exact [ax]; + +u8 adc_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux adc_byte_asm = \ + "push [edi]" \ + "popf" \ + "adc al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 adc_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux adc_word_asm = \ + "push [edi]" \ + "popf" \ + "adc ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 adc_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux adc_long_asm = \ + "push [edi]" \ + "popf" \ + "adc eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 add_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux add_byte_asm = \ + "push [edi]" \ + "popf" \ + "add al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 add_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux add_word_asm = \ + "push [edi]" \ + "popf" \ + "add ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 add_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux add_long_asm = \ + "push [edi]" \ + "popf" \ + "add eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 and_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux and_byte_asm = \ + "push [edi]" \ + "popf" \ + "and al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 and_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux and_word_asm = \ + "push [edi]" \ + "popf" \ + "and ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 and_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux and_long_asm = \ + "push [edi]" \ + "popf" \ + "and eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 cmp_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux cmp_byte_asm = \ + "push [edi]" \ + "popf" \ + "cmp al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 cmp_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux cmp_word_asm = \ + "push [edi]" \ + "popf" \ + "cmp ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 cmp_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux cmp_long_asm = \ + "push [edi]" \ + "popf" \ + "cmp eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 daa_byte_asm(u32 *flags,u8 d); +#pragma aux daa_byte_asm = \ + "push [edi]" \ + "popf" \ + "daa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 das_byte_asm(u32 *flags,u8 d); +#pragma aux das_byte_asm = \ + "push [edi]" \ + "popf" \ + "das" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 dec_byte_asm(u32 *flags,u8 d); +#pragma aux dec_byte_asm = \ + "push [edi]" \ + "popf" \ + "dec al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 dec_word_asm(u32 *flags,u16 d); +#pragma aux dec_word_asm = \ + "push [edi]" \ + "popf" \ + "dec ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 dec_long_asm(u32 *flags,u32 d); +#pragma aux dec_long_asm = \ + "push [edi]" \ + "popf" \ + "dec eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 inc_byte_asm(u32 *flags,u8 d); +#pragma aux inc_byte_asm = \ + "push [edi]" \ + "popf" \ + "inc al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 inc_word_asm(u32 *flags,u16 d); +#pragma aux inc_word_asm = \ + "push [edi]" \ + "popf" \ + "inc ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 inc_long_asm(u32 *flags,u32 d); +#pragma aux inc_long_asm = \ + "push [edi]" \ + "popf" \ + "inc eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 or_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux or_byte_asm = \ + "push [edi]" \ + "popf" \ + "or al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 or_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux or_word_asm = \ + "push [edi]" \ + "popf" \ + "or ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 or_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux or_long_asm = \ + "push [edi]" \ + "popf" \ + "or eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 neg_byte_asm(u32 *flags,u8 d); +#pragma aux neg_byte_asm = \ + "push [edi]" \ + "popf" \ + "neg al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 neg_word_asm(u32 *flags,u16 d); +#pragma aux neg_word_asm = \ + "push [edi]" \ + "popf" \ + "neg ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 neg_long_asm(u32 *flags,u32 d); +#pragma aux neg_long_asm = \ + "push [edi]" \ + "popf" \ + "neg eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 not_byte_asm(u32 *flags,u8 d); +#pragma aux not_byte_asm = \ + "push [edi]" \ + "popf" \ + "not al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 not_word_asm(u32 *flags,u16 d); +#pragma aux not_word_asm = \ + "push [edi]" \ + "popf" \ + "not ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 not_long_asm(u32 *flags,u32 d); +#pragma aux not_long_asm = \ + "push [edi]" \ + "popf" \ + "not eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 rcl_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rcl_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcl_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rcl_word_asm = \ + "push [edi]" \ + "popf" \ + "rcl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcl_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rcl_long_asm = \ + "push [edi]" \ + "popf" \ + "rcl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rcr_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rcr_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcr_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rcr_word_asm = \ + "push [edi]" \ + "popf" \ + "rcr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcr_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rcr_long_asm = \ + "push [edi]" \ + "popf" \ + "rcr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rol_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rol_byte_asm = \ + "push [edi]" \ + "popf" \ + "rol al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rol_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rol_word_asm = \ + "push [edi]" \ + "popf" \ + "rol ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rol_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rol_long_asm = \ + "push [edi]" \ + "popf" \ + "rol eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 ror_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux ror_byte_asm = \ + "push [edi]" \ + "popf" \ + "ror al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 ror_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux ror_word_asm = \ + "push [edi]" \ + "popf" \ + "ror ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 ror_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux ror_long_asm = \ + "push [edi]" \ + "popf" \ + "ror eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shl_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux shl_byte_asm = \ + "push [edi]" \ + "popf" \ + "shl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shl_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux shl_word_asm = \ + "push [edi]" \ + "popf" \ + "shl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shl_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux shl_long_asm = \ + "push [edi]" \ + "popf" \ + "shl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shr_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux shr_byte_asm = \ + "push [edi]" \ + "popf" \ + "shr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shr_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux shr_word_asm = \ + "push [edi]" \ + "popf" \ + "shr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shr_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux shr_long_asm = \ + "push [edi]" \ + "popf" \ + "shr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 sar_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sar_byte_asm = \ + "push [edi]" \ + "popf" \ + "sar al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 sar_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux sar_word_asm = \ + "push [edi]" \ + "popf" \ + "sar ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 sar_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux sar_long_asm = \ + "push [edi]" \ + "popf" \ + "sar eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u16 shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s); +#pragma aux shld_word_asm = \ + "push [edi]" \ + "popf" \ + "shld ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +#pragma aux shld_long_asm = \ + "push [edi]" \ + "popf" \ + "shld eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u16 shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s); +#pragma aux shrd_word_asm = \ + "push [edi]" \ + "popf" \ + "shrd ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +#pragma aux shrd_long_asm = \ + "push [edi]" \ + "popf" \ + "shrd eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u8 sbb_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sbb_byte_asm = \ + "push [edi]" \ + "popf" \ + "sbb al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sbb_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux sbb_word_asm = \ + "push [edi]" \ + "popf" \ + "sbb ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sbb_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux sbb_long_asm = \ + "push [edi]" \ + "popf" \ + "sbb eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 sub_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sub_byte_asm = \ + "push [edi]" \ + "popf" \ + "sub al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sub_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux sub_word_asm = \ + "push [edi]" \ + "popf" \ + "sub ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sub_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux sub_long_asm = \ + "push [edi]" \ + "popf" \ + "sub eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void test_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux test_byte_asm = \ + "push [edi]" \ + "popf" \ + "test al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + modify exact [al bl]; + +void test_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux test_word_asm = \ + "push [edi]" \ + "popf" \ + "test ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + modify exact [ax bx]; + +void test_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux test_long_asm = \ + "push [edi]" \ + "popf" \ + "test eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + modify exact [eax ebx]; + +u8 xor_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux xor_byte_asm = \ + "push [edi]" \ + "popf" \ + "xor al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 xor_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux xor_word_asm = \ + "push [edi]" \ + "popf" \ + "xor ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 xor_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux xor_long_asm = \ + "push [edi]" \ + "popf" \ + "xor eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +#pragma aux imul_byte_asm = \ + "push [edi]" \ + "popf" \ + "imul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +#pragma aux imul_word_asm = \ + "push [edi]" \ + "popf" \ + "imul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +#pragma aux imul_long_asm = \ + "push [edi]" \ + "popf" \ + "imul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +#pragma aux mul_byte_asm = \ + "push [edi]" \ + "popf" \ + "mul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +#pragma aux mul_word_asm = \ + "push [edi]" \ + "popf" \ + "mul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +#pragma aux mul_long_asm = \ + "push [edi]" \ + "popf" \ + "mul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); +#pragma aux idiv_byte_asm = \ + "push [edi]" \ + "popf" \ + "idiv bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); +#pragma aux idiv_word_asm = \ + "push [edi]" \ + "popf" \ + "idiv bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); +#pragma aux idiv_long_asm = \ + "push [edi]" \ + "popf" \ + "idiv ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +void div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); +#pragma aux div_byte_asm = \ + "push [edi]" \ + "popf" \ + "div bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); +#pragma aux div_word_asm = \ + "push [edi]" \ + "popf" \ + "div bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); +#pragma aux div_long_asm = \ + "push [edi]" \ + "popf" \ + "div ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +#endif + +#endif /* __X86EMU_PRIM_ASM_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h new file mode 100644 index 0000000..1633fe1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h @@ -0,0 +1,231 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for primitive operation functions. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_OPS_H +#define __X86EMU_PRIM_OPS_H + +#include "x86emu/prim_asm.h" + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +u16 aaa_word (u16 d); +u16 aas_word (u16 d); +u16 aad_word (u16 d); +u16 aam_word (u8 d); +u8 adc_byte (u8 d, u8 s); +u16 adc_word (u16 d, u16 s); +u32 adc_long (u32 d, u32 s); +u8 add_byte (u8 d, u8 s); +u16 add_word (u16 d, u16 s); +u32 add_long (u32 d, u32 s); +u8 and_byte (u8 d, u8 s); +u16 and_word (u16 d, u16 s); +u32 and_long (u32 d, u32 s); +u8 cmp_byte (u8 d, u8 s); +u16 cmp_word (u16 d, u16 s); +u32 cmp_long (u32 d, u32 s); +u8 daa_byte (u8 d); +u8 das_byte (u8 d); +u8 dec_byte (u8 d); +u16 dec_word (u16 d); +u32 dec_long (u32 d); +u8 inc_byte (u8 d); +u16 inc_word (u16 d); +u32 inc_long (u32 d); +u8 or_byte (u8 d, u8 s); +u16 or_word (u16 d, u16 s); +u32 or_long (u32 d, u32 s); +u8 neg_byte (u8 s); +u16 neg_word (u16 s); +u32 neg_long (u32 s); +u8 not_byte (u8 s); +u16 not_word (u16 s); +u32 not_long (u32 s); +u8 rcl_byte (u8 d, u8 s); +u16 rcl_word (u16 d, u8 s); +u32 rcl_long (u32 d, u8 s); +u8 rcr_byte (u8 d, u8 s); +u16 rcr_word (u16 d, u8 s); +u32 rcr_long (u32 d, u8 s); +u8 rol_byte (u8 d, u8 s); +u16 rol_word (u16 d, u8 s); +u32 rol_long (u32 d, u8 s); +u8 ror_byte (u8 d, u8 s); +u16 ror_word (u16 d, u8 s); +u32 ror_long (u32 d, u8 s); +u8 shl_byte (u8 d, u8 s); +u16 shl_word (u16 d, u8 s); +u32 shl_long (u32 d, u8 s); +u8 shr_byte (u8 d, u8 s); +u16 shr_word (u16 d, u8 s); +u32 shr_long (u32 d, u8 s); +u8 sar_byte (u8 d, u8 s); +u16 sar_word (u16 d, u8 s); +u32 sar_long (u32 d, u8 s); +u16 shld_word (u16 d, u16 fill, u8 s); +u32 shld_long (u32 d, u32 fill, u8 s); +u16 shrd_word (u16 d, u16 fill, u8 s); +u32 shrd_long (u32 d, u32 fill, u8 s); +u8 sbb_byte (u8 d, u8 s); +u16 sbb_word (u16 d, u16 s); +u32 sbb_long (u32 d, u32 s); +u8 sub_byte (u8 d, u8 s); +u16 sub_word (u16 d, u16 s); +u32 sub_long (u32 d, u32 s); +void test_byte (u8 d, u8 s); +void test_word (u16 d, u16 s); +void test_long (u32 d, u32 s); +u8 xor_byte (u8 d, u8 s); +u16 xor_word (u16 d, u16 s); +u32 xor_long (u32 d, u32 s); +void imul_byte (u8 s); +void imul_word (u16 s); +void imul_long (u32 s); +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); +void mul_byte (u8 s); +void mul_word (u16 s); +void mul_long (u32 s); +void idiv_byte (u8 s); +void idiv_word (u16 s); +void idiv_long (u32 s); +void div_byte (u8 s); +void div_word (u16 s); +void div_long (u32 s); +void ins (int size); +void outs (int size); +u16 mem_access_word (int addr); +void push_word (u16 w); +void push_long (u32 w); +u16 pop_word (void); +u32 pop_long (void); + +#if defined(__HAVE_INLINE_ASSEMBLER__) && !defined(PRIM_OPS_NO_REDEFINE_ASM) + +#define aaa_word(d) aaa_word_asm(&M.x86.R_EFLG,d) +#define aas_word(d) aas_word_asm(&M.x86.R_EFLG,d) +#define aad_word(d) aad_word_asm(&M.x86.R_EFLG,d) +#define aam_word(d) aam_word_asm(&M.x86.R_EFLG,d) +#define adc_byte(d,s) adc_byte_asm(&M.x86.R_EFLG,d,s) +#define adc_word(d,s) adc_word_asm(&M.x86.R_EFLG,d,s) +#define adc_long(d,s) adc_long_asm(&M.x86.R_EFLG,d,s) +#define add_byte(d,s) add_byte_asm(&M.x86.R_EFLG,d,s) +#define add_word(d,s) add_word_asm(&M.x86.R_EFLG,d,s) +#define add_long(d,s) add_long_asm(&M.x86.R_EFLG,d,s) +#define and_byte(d,s) and_byte_asm(&M.x86.R_EFLG,d,s) +#define and_word(d,s) and_word_asm(&M.x86.R_EFLG,d,s) +#define and_long(d,s) and_long_asm(&M.x86.R_EFLG,d,s) +#define cmp_byte(d,s) cmp_byte_asm(&M.x86.R_EFLG,d,s) +#define cmp_word(d,s) cmp_word_asm(&M.x86.R_EFLG,d,s) +#define cmp_long(d,s) cmp_long_asm(&M.x86.R_EFLG,d,s) +#define daa_byte(d) daa_byte_asm(&M.x86.R_EFLG,d) +#define das_byte(d) das_byte_asm(&M.x86.R_EFLG,d) +#define dec_byte(d) dec_byte_asm(&M.x86.R_EFLG,d) +#define dec_word(d) dec_word_asm(&M.x86.R_EFLG,d) +#define dec_long(d) dec_long_asm(&M.x86.R_EFLG,d) +#define inc_byte(d) inc_byte_asm(&M.x86.R_EFLG,d) +#define inc_word(d) inc_word_asm(&M.x86.R_EFLG,d) +#define inc_long(d) inc_long_asm(&M.x86.R_EFLG,d) +#define or_byte(d,s) or_byte_asm(&M.x86.R_EFLG,d,s) +#define or_word(d,s) or_word_asm(&M.x86.R_EFLG,d,s) +#define or_long(d,s) or_long_asm(&M.x86.R_EFLG,d,s) +#define neg_byte(s) neg_byte_asm(&M.x86.R_EFLG,s) +#define neg_word(s) neg_word_asm(&M.x86.R_EFLG,s) +#define neg_long(s) neg_long_asm(&M.x86.R_EFLG,s) +#define not_byte(s) not_byte_asm(&M.x86.R_EFLG,s) +#define not_word(s) not_word_asm(&M.x86.R_EFLG,s) +#define not_long(s) not_long_asm(&M.x86.R_EFLG,s) +#define rcl_byte(d,s) rcl_byte_asm(&M.x86.R_EFLG,d,s) +#define rcl_word(d,s) rcl_word_asm(&M.x86.R_EFLG,d,s) +#define rcl_long(d,s) rcl_long_asm(&M.x86.R_EFLG,d,s) +#define rcr_byte(d,s) rcr_byte_asm(&M.x86.R_EFLG,d,s) +#define rcr_word(d,s) rcr_word_asm(&M.x86.R_EFLG,d,s) +#define rcr_long(d,s) rcr_long_asm(&M.x86.R_EFLG,d,s) +#define rol_byte(d,s) rol_byte_asm(&M.x86.R_EFLG,d,s) +#define rol_word(d,s) rol_word_asm(&M.x86.R_EFLG,d,s) +#define rol_long(d,s) rol_long_asm(&M.x86.R_EFLG,d,s) +#define ror_byte(d,s) ror_byte_asm(&M.x86.R_EFLG,d,s) +#define ror_word(d,s) ror_word_asm(&M.x86.R_EFLG,d,s) +#define ror_long(d,s) ror_long_asm(&M.x86.R_EFLG,d,s) +#define shl_byte(d,s) shl_byte_asm(&M.x86.R_EFLG,d,s) +#define shl_word(d,s) shl_word_asm(&M.x86.R_EFLG,d,s) +#define shl_long(d,s) shl_long_asm(&M.x86.R_EFLG,d,s) +#define shr_byte(d,s) shr_byte_asm(&M.x86.R_EFLG,d,s) +#define shr_word(d,s) shr_word_asm(&M.x86.R_EFLG,d,s) +#define shr_long(d,s) shr_long_asm(&M.x86.R_EFLG,d,s) +#define sar_byte(d,s) sar_byte_asm(&M.x86.R_EFLG,d,s) +#define sar_word(d,s) sar_word_asm(&M.x86.R_EFLG,d,s) +#define sar_long(d,s) sar_long_asm(&M.x86.R_EFLG,d,s) +#define shld_word(d,fill,s) shld_word_asm(&M.x86.R_EFLG,d,fill,s) +#define shld_long(d,fill,s) shld_long_asm(&M.x86.R_EFLG,d,fill,s) +#define shrd_word(d,fill,s) shrd_word_asm(&M.x86.R_EFLG,d,fill,s) +#define shrd_long(d,fill,s) shrd_long_asm(&M.x86.R_EFLG,d,fill,s) +#define sbb_byte(d,s) sbb_byte_asm(&M.x86.R_EFLG,d,s) +#define sbb_word(d,s) sbb_word_asm(&M.x86.R_EFLG,d,s) +#define sbb_long(d,s) sbb_long_asm(&M.x86.R_EFLG,d,s) +#define sub_byte(d,s) sub_byte_asm(&M.x86.R_EFLG,d,s) +#define sub_word(d,s) sub_word_asm(&M.x86.R_EFLG,d,s) +#define sub_long(d,s) sub_long_asm(&M.x86.R_EFLG,d,s) +#define test_byte(d,s) test_byte_asm(&M.x86.R_EFLG,d,s) +#define test_word(d,s) test_word_asm(&M.x86.R_EFLG,d,s) +#define test_long(d,s) test_long_asm(&M.x86.R_EFLG,d,s) +#define xor_byte(d,s) xor_byte_asm(&M.x86.R_EFLG,d,s) +#define xor_word(d,s) xor_word_asm(&M.x86.R_EFLG,d,s) +#define xor_long(d,s) xor_long_asm(&M.x86.R_EFLG,d,s) +#define imul_byte(s) imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s) +#define imul_word(s) imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s) +#define imul_long(s) imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s) +#define imul_long_direct(res_lo,res_hi,d,s) imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s) +#define mul_byte(s) mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s) +#define mul_word(s) mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s) +#define mul_long(s) mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s) +#define idiv_byte(s) idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s) +#define idiv_word(s) idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s) +#define idiv_long(s) idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s) +#define div_byte(s) div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s) +#define div_word(s) div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s) +#define div_long(s) div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s) + +#endif + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_PRIM_OPS_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h new file mode 100644 index 0000000..bff4903 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h @@ -0,0 +1,98 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for system specific functions. These functions +* are always compiled and linked in the OS depedent libraries, +* and never in a binary portable driver. +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMUI_H +#define __X86EMU_X86EMUI_H + +/* If we are compiling in C++ mode, we can compile some functions as + * inline to increase performance (however the code size increases quite + * dramatically in this case). + */ + +#if defined(__cplusplus) && !defined(_NO_INLINE) +#define _INLINE inline +#else +#define _INLINE static +#endif + +/* Get rid of unused parameters in C++ compilation mode */ + +#ifdef __cplusplus +#define X86EMU_UNUSED(v) +#else +#define X86EMU_UNUSED(v) v +#endif + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/decode.h" +#include "x86emu/ops.h" +#include "x86emu/prim_ops.h" +#include "x86emu/fpu.h" +#include "x86emu/fpu_regs.h" +#include +#include + +/*--------------------------- Inline Functions ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern u8 (X86APIP sys_rdb)(u32 addr); +extern u16 (X86APIP sys_rdw)(u32 addr); +extern u32 (X86APIP sys_rdl)(u32 addr); +extern void (X86APIP sys_wrb)(u32 addr,u8 val); +extern void (X86APIP sys_wrw)(u32 addr,u16 val); +extern void (X86APIP sys_wrl)(u32 addr,u32 val); + +extern u8 (X86APIP sys_inb)(X86EMU_pioAddr addr); +extern u16 (X86APIP sys_inw)(X86EMU_pioAddr addr); +extern u32 (X86APIP sys_inl)(X86EMU_pioAddr addr); +extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val); +extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); +extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMUI_H */ diff --git a/board/MAI/bios_emulator/x86interface.c b/board/MAI/bios_emulator/x86interface.c new file mode 100644 index 0000000..909cb3c --- /dev/null +++ b/board/MAI/bios_emulator/x86interface.c @@ -0,0 +1,814 @@ +#include "x86emu.h" +#include "glue.h" + + +/* + * This isn't nice, but there are a lot of incompatibilities in the U-Boot and scitech include + * files that this is the only really workable solution. + * Might be cleaned out later. + */ + +#ifdef DEBUG +#undef DEBUG +#endif + +#undef IO_LOGGING +#undef MEM_LOGGING + +#ifdef IO_LOGGING +#define LOGIO(port, format, args...) if (dolog(port)) _printf(format , ## args) +#else +#define LOGIO(port, format, args...) +#endif + +#ifdef MEM_LOGGIN +#define LOGMEM(format, args...) _printf(format , ## args) +#else +#define LOGMEM(format, args...) +#endif + +#ifdef DEBUG +#define PRINTF(format, args...) _printf(format , ## args) +#else +#define PRINTF(format, argc...) +#endif + +typedef unsigned char UBYTE; +typedef unsigned short UWORD; +typedef unsigned long ULONG; + +typedef char BYTE; +typedef short WORT; +typedef long LONG; + +#define EMULATOR_MEM_SIZE (1024*1024) +#define EMULATOR_BIOS_OFFSET 0xC0000 +#define EMULATOR_STRAP_OFFSET 0x30000 +#define EMULATOR_STACK_OFFSET 0x20000 +#define EMULATOR_LOGO_OFFSET 0x40000 /* If you change this, change the strap code, too */ +#define VIDEO_BASE (void *)0xFD0B8000 + +extern char *getenv(char *); +extern int tstc(void); +extern int getc(void); +extern unsigned char video_get_attr(void); + +int atoi(char *string) +{ + int res = 0; + while (*string>='0' && *string <='9') + { + res *= 10; + res += *string-'0'; + string++; + } + + return res; +} + +void cons_gets(char *buffer) +{ + int i = 0; + char c = 0; + + buffer[0] = 0; + if (getenv("x86_runthru")) return; /*FIXME: */ + while (c != 0x0D && c != 0x0A) + { + while (!tstc()); + c = getc(); + if (c>=32 && c < 127) + { + buffer[i] = c; + i++; + buffer[i] = 0; + putc(c); + } + else + { + if (c == 0x08) + { + if (i>0) i--; + buffer[i] = 0; + } + } + } + buffer[i] = '\n'; + buffer[i+1] = 0; +} + +char *bios_date = "08/14/02"; +UBYTE model = 0xFC; +UBYTE submodel = 0x00; + +static inline UBYTE read_byte(volatile UBYTE* from) +{ + int x; + asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (UBYTE)x; +} + +static inline void write_byte(volatile UBYTE *to, int x) +{ + asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static inline UWORD read_word_little(volatile UWORD *from) +{ + int x; + asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from)); + return (UWORD)x; +} + +static inline UWORD read_word_big(volatile UWORD *from) +{ + int x; + asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (UWORD)x; +} + +static inline void write_word_little(volatile UWORD *to, int x) +{ + asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_word_big(volatile UWORD *to, int x) +{ + asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static inline ULONG read_long_little(volatile ULONG *from) +{ + unsigned long x; + asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from)); + return (ULONG)x; +} + +static inline ULONG read_long_big(volatile ULONG *from) +{ + unsigned long x; + asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (ULONG)x; +} + +static inline void write_long_little(volatile ULONG *to, ULONG x) +{ + asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_long_big(volatile ULONG *to, ULONG x) +{ + asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static int log_init = 0; +static int log_do = 0; +static int log_low = 0; + +int dolog(int port) +{ + if (log_init && log_do) + { + if (log_low && port > 0x400) return 0; + return 1; + } + + if (!log_init) + { + log_init = 1; + log_do = (getenv("x86_logio") != (char *)0); + log_low = (getenv("x86_loglow") != (char *)0); + if (log_do) + { + if (log_low && port > 0x400) return 0; + return 1; + } + } + return 0; +} + +/* Converts an emulator address to a physical address. */ +/* Handles all special cases (bios date, model etc), and might need work */ +u32 memaddr(u32 addr) +{ +/* if (addr >= 0xF0000 && addr < 0xFFFFF) printf("WARNING: Segment F access (0x%x)\n", addr); */ +/* printf("MemAddr=%p\n", addr); */ + if (addr >= 0xA0000 && addr < 0xC0000) + return 0xFD000000 + addr; + else if (addr >= 0xFFFF5 && addr < 0xFFFFE) + { + return (u32)bios_date+addr-0xFFFF5; + } + else if (addr == 0xFFFFE) + return (u32)&model; + else if (addr == 0xFFFFF) + return (u32)&submodel; + else if (addr >= 0x80000000) + { + /*printf("Warning: High memory access at 0x%x\n", addr); */ + return addr; + } + else + return (u32)M.mem_base+addr; +} + +u8 A1_rdb(u32 addr) +{ + u8 a = read_byte((UBYTE *)memaddr(addr)); + LOGMEM("rdb: %x -> %x\n", addr, a); + return a; +} + +u16 A1_rdw(u32 addr) +{ + u16 a = read_word_little((UWORD *)memaddr(addr)); + LOGMEM("rdw: %x -> %x\n", addr, a); + return a; +} + +u32 A1_rdl(u32 addr) +{ + u32 a = read_long_little((ULONG *)memaddr(addr)); + LOGMEM("rdl: %x -> %x\n", addr, a); + return a; +} + +void A1_wrb(u32 addr, u8 val) +{ + LOGMEM("wrb: %x <- %x\n", addr, val); + write_byte((UBYTE *)memaddr(addr), val); +} + +void A1_wrw(u32 addr, u16 val) +{ + LOGMEM("wrw: %x <- %x\n", addr, val); + write_word_little((UWORD *)memaddr(addr), val); +} + +void A1_wrl(u32 addr, u32 val) +{ + LOGMEM("wrl: %x <- %x\n", addr, val); + write_long_little((ULONG *)memaddr(addr), val); +} + +X86EMU_memFuncs _A1_mem = +{ + A1_rdb, + A1_rdw, + A1_rdl, + A1_wrb, + A1_wrw, + A1_wrl, +}; + +#define ARTICIAS_PCI_CFGADDR 0xfec00cf8 +#define ARTICIAS_PCI_CFGDATA 0xfee00cfc +#define IOBASE 0xFE000000 + +#define in_byte(from) read_byte( (UBYTE *)port_to_mem(from)) +#define in_word(from) read_word_little((UWORD *)port_to_mem(from)) +#define in_long(from) read_long_little((ULONG *)port_to_mem(from)) +#define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val) +#define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val) +#define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val) + +u32 port_to_mem(int port) +{ + if (port >= 0xCFC && port <= 0xCFF) return 0xFEE00000+port; + else if (port >= 0xCF8 && port <= 0xCFB) return 0xFEC00000+port; + else return IOBASE + port; +} + +u8 A1_inb(int port) +{ + u8 a; + /*if (port == 0x3BA) return 0; */ + a = in_byte(port); + LOGIO(port, "inb: %Xh -> %d (%Xh)\n", port, a, a); + return a; +} + +u16 A1_inw(int port) +{ + u16 a = in_word(port); + LOGIO(port, "inw: %Xh -> %d (%Xh)\n", port, a, a); + return a; +} + +u32 A1_inl(int port) +{ + u32 a = in_long(port); + LOGIO(port, "inl: %Xh -> %d (%Xh)\n", port, a, a); + return a; +} + +void A1_outb(int port, u8 val) +{ + LOGIO(port, "outb: %Xh <- %d (%Xh)\n", port, val, val); +/* if (port == 0xCF8) port = 0xCFB; + else if (port == 0xCF9) port = 0xCFA; + else if (port == 0xCFA) port = 0xCF9; + else if (port == 0xCFB) port = 0xCF8;*/ + out_byte(port, val); +} + +void A1_outw(int port, u16 val) +{ + LOGIO(port, "outw: %Xh <- %d (%Xh)\n", port, val, val); + out_word(port, val); +} + +void A1_outl(int port, u32 val) +{ + LOGIO(port, "outl: %Xh <- %d (%Xh)\n", port, val, val); + out_long(port, val); +} + +X86EMU_pioFuncs _A1_pio = +{ + A1_inb, + A1_inw, + A1_inl, + A1_outb, + A1_outw, + A1_outl, +}; + +static int reloced_ops = 0; + +void reloc_ops(void *reloc_addr) +{ + extern void (*x86emu_optab[256])(u8); + extern void (*x86emu_optab2[256])(u8); + extern void tables_relocate(unsigned int offset); + int i; + unsigned long delta; + if (reloced_ops == 1) return; + reloced_ops = 1; + + delta = TEXT_BASE - (unsigned long)reloc_addr; + + for (i=0; i<256; i++) + { + x86emu_optab[i] -= delta; + x86emu_optab2[i] -= delta; + } + + _A1_mem.rdb = A1_rdb; + _A1_mem.rdw = A1_rdw; + _A1_mem.rdl = A1_rdl; + _A1_mem.wrb = A1_wrb; + _A1_mem.wrw = A1_wrw; + _A1_mem.wrl = A1_wrl; + + _A1_pio.inb = A1_inb; + _A1_pio.inw = A1_inw; + _A1_pio.inl = A1_inl; + _A1_pio.outb = A1_outb; + _A1_pio.outw = A1_outw; + _A1_pio.outl = A1_outl; + + tables_relocate(delta); + +} + + +#define ANY_KEY(text) \ + printf(text); \ + while (!tstc()); + + +unsigned char more_strap[] = { + 0xb4, 0x0, 0xb0, 0x2, 0xcd, 0x10, +}; +#define MORE_STRAP_BYTES 6 /* Additional bytes of strap code */ + + +unsigned char *done_msg="VGA Initialized\0"; + +int execute_bios(pci_dev_t gr_dev, void *reloc_addr) +{ + extern void bios_init(void); + extern void remove_init_data(void); + extern int video_rows(void); + extern int video_cols(void); + extern int video_size(int, int); + u8 *strap; + unsigned char *logo; + u8 cfg; + int i; + char c; + char *s; +#ifdef EASTEREGG + int easteregg_active = 0; +#endif + char *pal_reset; + u8 *fb; + unsigned char *msg; + unsigned char current_attr; + + PRINTF("Trying to remove init data\n"); + remove_init_data(); + PRINTF("Removed init data from cache, now in RAM\n"); + + reloc_ops(reloc_addr); + PRINTF("Attempting to run emulator on %02x:%02x:%02x\n", + PCI_BUS(gr_dev), PCI_DEV(gr_dev), PCI_FUNC(gr_dev)); + + /* Enable compatibility hole for emulator access to frame buffer */ + PRINTF("Enabling compatibility hole\n"); + enable_compatibility_hole(); + + /* Allocate memory */ + /* FIXME: We shouldn't use this much memory really. */ + memset(&M, 0, sizeof(X86EMU_sysEnv)); + M.mem_base = malloc(EMULATOR_MEM_SIZE); + M.mem_size = EMULATOR_MEM_SIZE; + + if (!M.mem_base) + { + PRINTF("Unable to allocate one megabyte for emulator\n"); + return 0; + } + + if (attempt_map_rom(gr_dev, M.mem_base + EMULATOR_BIOS_OFFSET) == 0) + { + PRINTF("Error mapping rom. Emulation terminated\n"); + return 0; + } + +#if 1 /*def DEBUG*/ + s = getenv("x86_ask_start"); + if (s) + { + printf("Press 'q' to skip initialization, 'd' for dry init\n'i' for i/o session"); + while (!tstc()); + c = getc(); + if (c == 'q') return 0; + if (c == 'd') + { + extern void bios_set_mode(int mode); + bios_set_mode(0x03); + return 0; + } + if (c == 'i') do_inout(); + } + + +#endif + +#ifdef EASTEREGG +/* if (tstc()) + { + if (getc() == 'c') + { + easteregg_active = 1; + } + } +*/ + if (getenv("easteregg")) + { + easteregg_active = 1; + } + + if (easteregg_active) + { + /* Yay! */ + setenv("x86_mode", "1"); + setenv("vga_fg_color", "11"); + setenv("vga_bg_color", "1"); + easteregg_active = 1; + } +#endif + + strap = (u8*)M.mem_base + EMULATOR_STRAP_OFFSET; + + { + char *m = getenv("x86_mode"); + if (m) + { + more_strap[3] = atoi(m); + if (more_strap[3] == 1) video_size(40, 25); + else video_size(80, 25); + } + } + + /* + * Poke the strap routine. This might need a bit of extending + * if there is a mode switch involved, i.e. we want to int10 + * afterwards to set a different graphics mode, or alternatively + * there might be a different start address requirement if the + * ROM doesn't have an x86 image in its first image. + */ + + PRINTF("Poking strap...\n"); + + /* FAR CALL c000:0003 */ + *strap++ = 0x9A; *strap++ = 0x03; *strap++ = 0x00; + *strap++ = 0x00; *strap++ = 0xC0; + +#if 1 + /* insert additional strap code */ + for (i=0; i < MORE_STRAP_BYTES; i++) + { + *strap++ = more_strap[i]; + } +#endif + /* HALT */ + *strap++ = 0xF4; + + PRINTF("Setting up logo data\n"); + logo = (unsigned char *)M.mem_base + EMULATOR_LOGO_OFFSET; + for (i=0; i<16; i++) + { + *logo++ = 0xFF; + } + + /* + * Setup the init parameters. + * Per PCI specs, AH must contain the bus and AL + * must contain the devfn, encoded as (dev<<3)|fn + */ + + /* Execution starts here */ + M.x86.R_CS = SEG(EMULATOR_STRAP_OFFSET); + M.x86.R_IP = OFF(EMULATOR_STRAP_OFFSET); + + /* Stack at top of ram */ + M.x86.R_SS = SEG(EMULATOR_STACK_OFFSET); + M.x86.R_SP = OFF(EMULATOR_STACK_OFFSET); + + /* Input parameters */ + M.x86.R_AH = PCI_BUS(gr_dev); + M.x86.R_AL = (PCI_DEV(gr_dev)<<3) | PCI_FUNC(gr_dev); + + /* Set the I/O and memory access functions */ + X86EMU_setupMemFuncs(&_A1_mem); + X86EMU_setupPioFuncs(&_A1_pio); + + /* Enable timer 2 */ + cfg = in_byte(0x61); /* Get Misc control */ + cfg |= 0x01; /* Enable timer 2 */ + out_byte(0x61, cfg); /* output again */ + + /* Set up the timers */ + out_byte(0x43, 0x54); + out_byte(0x41, 0x18); + + out_byte(0x43, 0x36); + out_byte(0x40, 0x00); + out_byte(0x40, 0x00); + + out_byte(0x43, 0xb6); + out_byte(0x42, 0x31); + out_byte(0x42, 0x13); + + /* Init the "BIOS". */ + bios_init(); + + /* Video Card Reset */ + out_byte(0x3D8, 0); + out_byte(0x3B8, 1); + (void)in_byte(0x3BA); + (void)in_byte(0x3DA); + out_byte(0x3C0, 0); + out_byte(0x61, 0xFC); + +#ifdef DEBUG + s = _getenv("x86_singlestep"); + if (s && strcmp(s, "on")==0) + { + PRINTF("Enabling single stepping for debug\n"); + X86EMU_trace_on(); + } +#endif + + /* Ready set go... */ + PRINTF("Running emulator\n"); + X86EMU_exec(); + PRINTF("Done running emulator\n"); + +/* FIXME: Remove me */ + pal_reset = getenv("x86_palette_reset"); + if (pal_reset && strcmp(pal_reset, "on") == 0) + { + PRINTF("Palette reset\n"); + /*(void)in_byte(0x3da); */ + /*out_byte(0x3c0, 0); */ + + out_byte(0x3C8, 0); + out_byte(0x3C9, 0); + out_byte(0x3C9, 0); + out_byte(0x3C9, 0); + for (i=0; i<254; i++) + { + out_byte(0x3C9, 63); + out_byte(0x3C9, 63); + out_byte(0x3C9, 63); + } + + out_byte(0x3c0, 0x20); + } +/* FIXME: remove me */ +#ifdef EASTEREGG + if (easteregg_active) + { + extern void video_easteregg(void); + video_easteregg(); + } +#endif +/* + current_attr = video_get_attr(); + fb = (u8 *)VIDEO_BASE; + for (i=0; i +#include + +int do_menu( cmd_tbl_t *cmdtp, /*bd_t *bd,*/ int flag, int argc, char *argv[] ) +{ +/* printf("\n"); */ + return 0; +} + +#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP) +U_BOOT_CMD( + menu, 1, 1, do_menu, + "menu - display BIOS setup menu\n", + "" +); +#endif diff --git a/board/MAI/menu/menu.c b/board/MAI/menu/menu.c new file mode 100644 index 0000000..c0c63a8 --- /dev/null +++ b/board/MAI/menu/menu.c @@ -0,0 +1,66 @@ +#include "menu.h" + +#define SINGLE_BOX 0 +#define DOUBLE_BOX 1 + +void video_draw_box(int style, int attr, char *title, int separate, int x, int y, int w, int h); +void video_draw_text(int x, int y, int attr, char *text); +void video_save_rect(int x, int y, int w, int h, void *save_area, int clearchar, int clearattr); +void video_restore_rect(int x, int y, int w, int h, void *save_area); +int video_rows(void); +int video_cols(void); + +#define MAX_MENU_OPTIONS 200 + +typedef struct +{ + int used; /* flag if this entry is used */ + int entry_x; /* Character column of the menu entry */ + int entry_y; /* Character line of the entry */ + int option_x; /* Character colum of the option (entry is same) */ +} option_data_t; + +option_data_t odata[MAX_MENU_OPTIONS]; + +int normal_attr = 0x0F; +int select_attr = 0x2F; +int disabled_attr = 0x07; + +menu_t *root_menu; + +int menu_init (menu_t *root) +{ + char *s; + int i; + + s = getenv("menu_normal"); + if (s) normal_attr = atoi(s); + + s = getenv("menu_select"); + if (s) select_attr = atoi(s); + + s = getenv("menu_disabled"); + if (s) disabled_attr = atoi(s); + + for (i=0; iused = 0; +} + +void menu_layout (menu_t *menu) +{ diff --git a/board/MAI/menu/menu.h b/board/MAI/menu/menu.h new file mode 100644 index 0000000..8aebb7d --- /dev/null +++ b/board/MAI/menu/menu.h @@ -0,0 +1,174 @@ +#ifndef MENU_H +#define MENU_H + +/* A single menu */ +typedef void (*menu_finish_callback)(struct menu_s *menu); + +typedef struct menu_s +{ + char *name; /* Menu name */ + int num_options; /* Number of options in this menu */ + int flags; /* Various flags - see below */ + int option_align; /* Aligns options to a field width of this much characters if != 0 */ + + struct menu_option_s **options; /* Pointer to this menu's options */ + menu_finish_callback callback; /* Called when the menu closes */ +} menu_t; + +/* + * type: Type of the option (see below) + * name: Name to display for this option + * help: Optional help string + * id : optional id number + * sys : pointer for system-specific data, init to NULL and don't touch + */ + +#define OPTION_PREAMBLE \ + int type; \ + char *name; \ + char *help; \ + int id; \ + void *sys; \ + + +/* + * Menu option types. + * There are a number of different layouts for menu options depending + * on their types. Currently there are the following possibilities: + * + * Submenu: + * This entry links to a new menu. + * + * Boolean: + * A simple on/off toggle entry. Booleans can be either yes/no, 0/1 or on/off. + * Optionally, this entry can enable/disable a set of other options. An example would + * be to enable/disable on-board USB, and if enabled give access to further options like + * irq settings, base address etc. + * + * Text: + * A single line/limited number of characters text entry box. Text can be restricted + * to a certain charset (digits/hex digits/all/custom). Result is also available as an + * int if numeric. + * + * Selection: + * One-of-many type of selection entry. User may choose on of a set of strings, which + * maps to a specific value for the variable. + * + * Routine: + * Selecting this calls an entry-specific routine. This can be used for saving contents etc. + * + * Custom: + * Display and behaviour of this entry is defined by a set of callbacks. + */ + +#define MENU_SUBMENU_TYPE 0 +typedef struct menu_submenu_s +{ + OPTION_PREAMBLE + + menu_t * submenu; /* Pointer to the submenu */ +} menu_submenu_t; + +#define MENU_BOOLEAN_TYPE 1 +typedef struct menu_boolean_s +{ + OPTION_PREAMBLE + + char *variable; /* Name of the variable to getenv()/setenv() */ + int subtype; /* Subtype (on/off, 0/1, yes/no, enable/disable), see below */ + int mutex; /* Bit mask of options to enable/disable. Bit 0 is the option + immediately following this one, bit 1 is the next one etc. + bit 7 = 0 means to disable when this option is off, + bit 7 = 1 means to disable when this option is on. + An option is disabled when the type field's upper bit is set */ +} menu_boolean_t; + +/* BOOLEAN Menu flags */ +#define MENU_BOOLEAN_ONOFF 0x01 +#define MENU_BOOLEAN_01 0x02 +#define MENU_BOOLEAN_YESNO 0x03 +#define MENU_BOOLEAN_ENDIS 0x04 +#define MENU_BOOLEAN_TYPE_MASK 0x07 + + +#define MENU_TEXT_TYPE 2 +typedef struct menu_text_s +{ + OPTION_PREAMBLE + + char *variable; /* Name of the variable to getenv()/setenv() */ + int maxchars; /* Max number of characters */ + char *charset; /* Optional charset to use */ + int flags; /* Flags - see below */ +} menu_text_t; + +/* TEXT entry menu flags */ +#define MENU_TEXT_NUMERIC 0x01 +#define MENU_TEXT_HEXADECIMAL 0x02 +#define MENU_TEXT_FREE 0x03 +#define MENU_TEXT_TYPE_MASK 0x07 + + +#define MENU_SELECTION_TYPE 3 +typedef struct menu_select_option_s +{ + char *map_from; /* Map this variable contents ... */ + char *map_to; /* ... to this menu text and vice versa */ +} menu_select_option_t; + +typedef struct menu_select_s +{ + OPTION_PREAMBLE + + int num_options; /* Number of mappings */ + menu_select_option_t **options; + /* Option list array */ +} menu_select_t; + + +#define MENU_ROUTINE_TYPE 4 +typedef void (*menu_routine_callback)(struct menu_routine_s *); + +typedef struct menu_routine_s +{ + OPTION_PREAMBLE + menu_routine_callback callback; + /* routine to be called */ + void *user_data; /* User data, don't care for system */ +} menu_routine_t; + + +#define MENU_CUSTOM_TYPE 5 +typedef void (*menu_custom_draw)(struct menu_custom_s *); +typedef void (*menu_custom_key)(struct menu_custom_s *, int); + +typedef struct menu_custom_s +{ + OPTION_PREAMBLE + menu_custom_draw drawfunc; + menu_custom_key keyfunc; + void *user_data; +} menu_custom_t; + +/* + * The menu option superstructure + */ +typedef struct menu_option_s +{ + union + { + menu_submenu_t m_sub_menu; + menu_boolean_t m_boolean; + menu_text_t m_text; + menu_select_t m_select; + menu_routine_t m_routine; + }; +} menu_option_t; + +/* Init the menu system. Returns <0 on error */ +int menu_init(menu_t *root); + +/* Execute a single menu. Returns <0 on error */ +int menu_do(menu_t *menu); + +#endif diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt new file mode 100644 index 0000000..391d49a --- /dev/null +++ b/board/Marvell/common/bootseq.txt @@ -0,0 +1,94 @@ +(cpu/mpc7xxx/start.S) + +start: + b boot_cold + +start_warm: + b boot_warm + + +boot_cold: +boot_warm: + clear bats + init l2 (if enabled) + init altivec (if enabled) + invalidate l2 (if enabled) + setup bats (from defines in config_EVB) + enable_addr_trans: (if MMU enabled) + enable MSR_IR and MSR_DR + jump to in_flash + +in_flash: + enable l1 dcache + gal_low_init: (board/evb64260/sdram_init.S) + config SDRAM (CFG, TIMING, DECODE) + init scratch regs (810 + 814) + + detect DIMM0 (bank 0 only) + config SDRAM_PARA0 to 256/512Mbit + bl sdram_op_mode + detect bank0 width + write scratch reg 810 + config SDRAM_PARA0 with results + config SDRAM_PARA1 with results + + detect DIMM1 (bank 2 only) + config SDRAM_PARA2 to 256/512Mbit + detect bank2 width + write scratch reg 814 + config SDRAM_PARA2 with results + config SDRAM_PARA3 with results + + setup device bus timings/width + setup boot device timings/width + + setup CPU_CONF (0x0) + setup cpu master control register 0x160 + setup PCI0 TIMEOUT + setup PCI1 TIMEOUT + setup PCI0 BAR + setup PCI1 BAR + + setup MPP control 0-3 + setup GPP level control + setup Serial ports multiplex + + setup stack pointer (r1) + setup GOT + call cpu_init_f + debug leds + board_init_f: (common/board.c) + board_early_init_f: + remap gt regs? + map PCI mem/io + map device space + clear out interupts + init_timebase + env_init + serial_init + console_init_f + display_options + initdram: (board/evb64260/evb64260.c) + detect memory + for each bank: + dram_size() + setup PCI slave memory mappings + setup SCS + setup monitor + alloc board info struct + init bd struct + relocate_code: (cpu/mpc7xxx/start.S) + copy,got,clearbss + board_init_r(bd, dest_addr) (common/board.c) + setup bd function pointers + trap_init + flash_init: (board/evb64260/flash.c) + setup bd flash info + cpu_init_r: (cpu/mpc7xxx/cpu_init.c) + nothing + mem_malloc_init + malloc_bin_reloc + spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + env_relocated + misc_init_r(bd): (board/evb64260/evb64260.c) + mpsc_init2 diff --git a/board/Marvell/common/ecctest.c b/board/Marvell/common/ecctest.c new file mode 100644 index 0000000..e22b113 --- /dev/null +++ b/board/Marvell/common/ecctest.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2001 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifdef ECC_TEST +static inline void ecc_off (void) +{ + *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000; +} + +static inline void ecc_on (void) +{ + *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000; +} + +static int putshex (const char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) { + printf ("%02x", buf[i]); + } + return 0; +} + +static int char_memcpy (void *d, const void *s, int len) +{ + int i; + char *cd = d; + const char *cs = s; + + for (i = 0; i < len; i++) { + *(cd++) = *(cs++); + } + return 0; +} + +static int memory_test (char *buf) +{ + const char src[][16] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}, + {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}, + {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}, + {0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, + 0x08, 0x08, 0x08, 0x08, 0x08, 0x08}, + {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, + {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20}, + {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}, + {0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}, + {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55}, + {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}, + {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }; + const int foo[] = { 0 }; + int i, j, a; + + printf ("\ntest @ %d %p\n", foo[0], buf); + for (i = 0; i < 12; i++) { + for (a = 0; a < 8; a++) { + const char *s = src[i] + a; + int align = (unsigned) (s) & 0x7; + + /* ecc_off(); */ + memcpy (buf, s, 8); + /* ecc_on(); */ + putshex (s, 8); + if (memcmp (buf, s, 8)) { + putc ('\n'); + putshex (buf, 8); + printf (" [FAIL] (%p) align=%d\n", s, align); + for (j = 0; j < 8; j++) { + s[j] == buf[j] ? puts (" ") : + printf ("%02x", + (s[j]) ^ (buf[j])); + } + putc ('\n'); + } else { + printf (" [PASS] (%p) align=%d\n", s, align); + } + /* ecc_off(); */ + char_memcpy (buf, s, 8); + /* ecc_on(); */ + putshex (s, 8); + if (memcmp (buf, s, 8)) { + putc ('\n'); + putshex (buf, 8); + printf (" [FAIL] (%p) align=%d\n", s, align); + for (j = 0; j < 8; j++) { + s[j] == buf[j] ? puts (" ") : + printf ("%02x", + (s[j]) ^ (buf[j])); + } + putc ('\n'); + } else { + printf (" [PASS] (%p) align=%d\n", s, align); + } + } + } + + return 0; +} +#endif diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c new file mode 100644 index 0000000..a8add85 --- /dev/null +++ b/board/Marvell/common/flash.c @@ -0,0 +1,1072 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * flash.c - flash support for the 512k, 8bit boot flash + and the 8MB 32bit extra flash on the DB64360 + * most of this file was based on the existing U-Boot + * flash drivers. + * + * written or collected and sometimes rewritten by + * Ingo Assmus + * + */ + +#include +#include +#include "../include/mv_gen_reg.h" +#include "../include/memory.h" +#include "intel_flash.h" + +#define FLASH_ROM 0xFFFD /* unknown flash type */ +#define FLASH_RAM 0xFFFE /* unknown flash type */ +#define FLASH_MAN_UNKNOWN 0xFFFF0000 + +/* #define DEBUG */ + +/* Intel flash commands */ +int flash_erase_intel (flash_info_t * info, int s_first, int s_last); +int write_word_intel (bank_addr_t addr, bank_word_t value); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (int portwidth, vu_long * addr, + flash_info_t * info); +static int write_word (flash_info_t * info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned int i; + unsigned long size_b0 = 0, size_b1 = 0; + unsigned long base, flash_size; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* the boot flash */ + base = CFG_FLASH_BASE; + size_b0 = + flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base, + &flash_info[0]); + + printf ("[%ldkB@%lx] ", size_b0 / 1024, base); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20); + } + + base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE); +/* base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/ + for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) { + unsigned long size = + flash_get_size (CFG_EXTRA_FLASH_WIDTH, + (vu_long *) base, &flash_info[i]); + + printf ("[%ldMB@%lx] ", size >> 20, base); + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + if (i == 1) { + printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b1, size_b1 << 20); + } + break; + } + size_b1 += size; + base += size; + } + + flash_size = size_b0 + size_b1; + return flash_size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + int sector_size; + + if (!info->sector_count) + return; + + /* set up sector start address table */ + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + case FLASH_28F128J3A: + case FLASH_28F640J3A: + case FLASH_RAM: + /* this chip has uniformly spaced sectors */ + sector_size = info->size / info->sector_count; + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * sector_size); + break; + default: + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_STM: + printf ("STM "); + break; + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf ("AM29LV040B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400B: + printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_28F640J3A: + printf ("28F640J3A (64 Mbit)\n"); + break; + case FLASH_28F128J3A: + printf ("28F128J3A (128 Mbit)\n"); + break; + case FLASH_ROM: + printf ("ROM\n"); + break; + case FLASH_RAM: + printf ("RAM\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + if ((info->size >> 20) > 0) { + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + } else { + printf (" Size: %ld kB in %d Sectors\n", + info->size >> 10, info->sector_count); + } + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static inline void flash_cmd (int width, volatile unsigned char *addr, + int offset, unsigned char cmd) +{ + /* supports 1x8, 1x16, and 2x16 */ + /* 2x8 and 4x8 are not supported */ + if (width == 4) { + /* assuming chips are in 16 bit mode */ + /* 2x16 */ + unsigned long cmd32 = (cmd << 16) | cmd; + + *(volatile unsigned long *) (addr + offset * 2) = cmd32; + } else { + /* 1x16 or 1x8 */ + *(volatile unsigned char *) (addr + offset) = cmd; + } +} + +static ulong +flash_get_size (int portwidth, vu_long * addr, flash_info_t * info) +{ + short i; + volatile unsigned char *caddr = (unsigned char *) addr; + volatile unsigned short *saddr = (unsigned short *) addr; + volatile unsigned long *laddr = (unsigned long *) addr; + char old[2], save; + ulong id = 0, manu = 0, base = (ulong) addr; + +#ifdef DEBUG + printf ("%s: enter\n", __FUNCTION__); +#endif + info->portwidth = portwidth; + + save = *caddr; + + flash_cmd (portwidth, caddr, 0, 0xf0); + flash_cmd (portwidth, caddr, 0, 0xf0); + + udelay (10); + + old[0] = caddr[0]; + old[1] = caddr[1]; + + + if (old[0] != 0xf0) { + flash_cmd (portwidth, caddr, 0, 0xf0); + flash_cmd (portwidth, caddr, 0, 0xf0); + + udelay (10); + + if (*caddr == 0xf0) { + /* this area is ROM */ + *caddr = save; + info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; + info->sector_count = 8; + info->size = 0x80000; + flash_get_offsets (base, info); + return info->size; + } + } else { + *caddr = 0; + + udelay (10); + + if (*caddr == 0) { + /* this area is RAM */ + *caddr = save; + info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN; + info->sector_count = 8; + info->size = 0x80000; + flash_get_offsets (base, info); + return info->size; + } + flash_cmd (portwidth, caddr, 0, 0xf0); + + udelay (10); + } + + /* Write auto select command: read Manufacturer ID */ + flash_cmd (portwidth, caddr, 0x555, 0xAA); + flash_cmd (portwidth, caddr, 0x2AA, 0x55); + flash_cmd (portwidth, caddr, 0x555, 0x90); + + udelay (10); + + if ((caddr[0] == old[0]) && (caddr[1] == old[1])) { + + /* this area is ROM */ + info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; + info->sector_count = 8; + info->size = 0x80000; + flash_get_offsets (base, info); + return info->size; +#ifdef DEBUG + } else { + printf ("%px%d: %02x:%02x -> %02x:%02x\n", + caddr, portwidth, old[0], old[1], caddr[0], caddr[1]); +#endif + } + + switch (portwidth) { + case 1: + manu = caddr[0]; + manu |= manu << 16; + id = caddr[1]; + break; + case 2: + manu = saddr[0]; + manu |= manu << 16; + id = saddr[1]; + id |= id << 16; + break; + case 4: + manu = laddr[0]; + id = laddr[1]; + break; + } + +#ifdef DEBUG + flash_cmd (portwidth, caddr, 0, 0xf0); + + printf ("\n%08lx:%08lx:%08lx\n", base, manu, id); + printf ("%08lx %08lx %08lx %08lx\n", + laddr[0], laddr[1], laddr[2], laddr[3]); +#endif + + switch (manu) { + case STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + flash_cmd (portwidth, caddr, 0, 0xf0); + + printf ("Unknown Mfr [%08lx]:%08lx\n", manu, id); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + switch (id) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + info->chipwidth = 1; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + info->chipwidth = 1; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + info->chipwidth = 1; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + info->chipwidth = 1; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + info->chipwidth = 1; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + info->chipwidth = 1; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + case AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x80000; + info->chipwidth = 1; + break; /* => 512 kB */ + + case INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 128 * 1024 * 64; /* 128kbytes x 64 blocks */ + info->chipwidth = 2; + if (portwidth == 4) + info->size *= 2; /* 2x16 */ + break; + + case INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 128 * 1024 * 128; /* 128kbytes x 128 blocks */ + info->chipwidth = 2; + if (portwidth == 4) + info->size *= 2; /* 2x16 */ + break; + + default: + flash_cmd (portwidth, caddr, 0, 0xf0); + + printf ("Unknown id %lx:[%lx]\n", manu, id); + info->flash_id = FLASH_UNKNOWN; + info->chipwidth = 1; + return (0); /* => no or unknown flash */ + + } + + flash_get_offsets (base, info); + + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0)=0x02 */ + /* D0 = 1 if protected */ + caddr = (volatile unsigned char *) (info->start[i]); + saddr = (volatile unsigned short *) (info->start[i]); + laddr = (volatile unsigned long *) (info->start[i]); + if (portwidth == 1) + info->protect[i] = caddr[2] & 1; + else if (portwidth == 2) + info->protect[i] = saddr[2] & 1; + else + info->protect[i] = laddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (volatile unsigned char *) info->start[0]; + + flash_cmd (portwidth, caddr, 0, 0xF0); /* reset bank */ + } + + return (info->size); +} + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile unsigned char *addr = (uchar *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + +/* modified to support 2x16 Intel flash */ +/* Note that the code will not exit on a flash erasure error or timeout */ +/* but will print and error message and continue processing sectors */ +/* until they are all erased. */ +/* 10-16-2002 P. Marchese */ + ulong mask; + int timeout; + + if (info->portwidth == 4) +/* { + printf ("- Warning: erasing of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); + return 1; + }*/ + { + /* make sure it's Intel flash */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + /* yup! it's an Intel flash */ + /* is it 16-bits wide? */ + if (info->chipwidth == 2) { + /* yup! it's 16-bits wide */ + /* are there any sectors to process? */ + if ((s_first < 0) || (s_first > s_last)) { + printf ("Error: There are no sectors to erase\n"); + printf ("Either sector %d is less than zero\n", s_first); + printf ("or sector %d is greater than sector %d\n", s_first, s_last); + return 1; + } + /* check for protected sectors */ + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) + if (info->protect[sect]) + prot++; + /* if variable "prot" is nonzero, there are protected sectors */ + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + /* reset the flash */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RST); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + /* Clear the status register */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_CLR_STAT); + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RST); + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + /* is the sector unprotected? */ + if (info->protect[sect] == 0) { /* not protected */ + /* issue the single block erase command, 0x20 */ + flash_cmd (info->portwidth, + (volatile unsigned + char *) info-> + start[sect], 0, + CHIP_CMD_ERASE1); + /* issue the erase confirm command, 0xD0 */ + flash_cmd (info->portwidth, + (volatile unsigned + char *) info-> + start[sect], 0, + CHIP_CMD_ERASE2); + l_sect = sect; + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + /* poll for erasure completion */ + /* put flash into read status mode by writing 0x70 to it */ + flash_cmd (info->portwidth, + addr, 0, + CHIP_CMD_RD_STAT); + /* setup the status register mask */ + mask = CHIP_STAT_RDY | + (CHIP_STAT_RDY << 16); + /* init. the timeout counter */ + start = get_timer (0); + /* keep looping while the flash is not ready */ + /* exit the loop by timing out or the flash */ + /* becomes ready again */ + timeout = 0; + while ((* + (volatile unsigned + long *) info-> + start[sect] & mask) != + mask) { + /* has the timeout limit been reached? */ + if (get_timer (start) + > + CFG_FLASH_ERASE_TOUT) + { + /* timeout limit reached */ + printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]); + printf ("Continuing with next sector\n"); + timeout = 1; + goto timed_out_error; + } + /* put flash into read status mode by writing 0x70 to it */ + flash_cmd (info-> + portwidth, + addr, 0, + CHIP_CMD_RD_STAT); + } + /* did we timeout? */ + timed_out_error:if (timeout == 0) + { + /* didn't timeout, so check the status register */ + /* create the status mask to check for errors */ + mask = CHIP_STAT_ECLBS; + mask = mask | (mask << + 16); + /* put flash into read status mode by writing 0x70 to it */ + flash_cmd (info-> + portwidth, + addr, 0, + CHIP_CMD_RD_STAT); + /* are there any errors? */ + if ((* + (volatile + unsigned long *) + info-> + start[sect] & + mask) != 0) { + /* We got an erasure error */ + printf ("Flash erasure error at address 0x%08lx\n", info->start[sect]); + printf ("Continuing with next sector\n"); + /* reset the flash */ + flash_cmd + (info-> + portwidth, + addr, + 0, + CHIP_CMD_RST); + } + } + /* erasure completed without errors */ + /* reset the flash */ + flash_cmd (info->portwidth, + addr, 0, + CHIP_CMD_RST); + } /* end if not protected */ + } /* end for loop */ + printf ("Flash erasure done\n"); + return 0; + } else { + /* The Intel flash is not 16-bit wide */ + /* print and error message and return */ + /* NOTE: you can add routines here to handle other size flash */ + printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8); + printf ("The erasure code only handles Intel 16-bit wide flash memory\n"); + return 1; + } + } else { + /* Not Intel flash so return an error as a write timeout */ + /* NOTE: if it's another type flash, stick its routine here */ + printf ("Error: The flash device is not Intel type\n"); + printf ("The erasure code only supports Intel flash in a 32-bit port width\n"); + return 1; + } + } + + /* end 32-bit wide flash code */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) + return 1; /* Rom can not be erased */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { /* RAM just copy 0s to RAM */ + for (sect = s_first; sect <= s_last; sect++) { + int sector_size = info->size / info->sector_count; + + addr = (uchar *) (info->start[sect]); + memset ((void *) addr, 0, sector_size); + } + return 0; + } + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { /* Intel works spezial */ + return flash_erase_intel (info, + (unsigned short) s_first, + (unsigned short) s_last); + } +#if 0 + if ((info->flash_id == FLASH_UNKNOWN) || /* Flash is unknown to PPCBoot */ + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } +#endif + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + flash_cmd (info->portwidth, addr, 0x555, 0xAA); /* start erase routine */ + flash_cmd (info->portwidth, addr, 0x2AA, 0x55); + flash_cmd (info->portwidth, addr, 0x555, 0x80); + flash_cmd (info->portwidth, addr, 0x555, 0xAA); + flash_cmd (info->portwidth, addr, 0x2AA, 0x55); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (uchar *) (info->start[sect]); + flash_cmd (info->portwidth, addr, 0, 0x30); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile unsigned char *) (info->start[l_sect]); + /* broken for 2x16: TODO */ + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned char *) info->start[0]; + flash_cmd (info->portwidth, addr, 0, 0xf0); + flash_cmd (info->portwidth, addr, 0, 0xf0); + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +/* broken for 2x16: TODO */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + +/* Commented out since the below code should work for 32-bit(2x 16 flash) */ +/* 10-16-2002 P. Marchese */ +/* if(info->portwidth==4) return 1; */ +/* if(info->portwidth==4) { + printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); + return 1; + }*/ + + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) + return 0; + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { + memcpy ((void *) addr, src, cnt); + return 0; + } + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +/* broken for 2x16: TODO */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile unsigned char *addr = (uchar *) (info->start[0]); + ulong start; + int flag, i; + ulong mask; + +/* modified so that it handles 32-bit(2x16 Intel flash programming */ +/* 10-16-2002 P. Marchese */ + + if (info->portwidth == 4) +/* { + printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); + return 1; + }*/ + { + /* make sure it's Intel flash */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + /* yup! it's an Intel flash */ + /* is it 16-bits wide? */ + if (info->chipwidth == 2) { + /* yup! it's 16-bits wide */ + /* so we know how to program it */ + /* reset the flash */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RST); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + /* Clear the status register */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_CLR_STAT); + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RST); + /* 1st cycle of word/byte program */ + /* write 0x40 to the location to program */ + flash_cmd (info->portwidth, (uchar *) dest, 0, + CHIP_CMD_PROG); + /* 2nd cycle of word/byte program */ + /* write the data to the destination address */ + *(ulong *) dest = data; + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + /* setup the status register mask */ + mask = CHIP_STAT_RDY | (CHIP_STAT_RDY << 16); + /* put flash into read status mode by writing 0x70 to it */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RD_STAT); + /* init. the timeout counter */ + start = get_timer (0); + /* keep looping while the flash is not ready */ + /* exit the loop by timing out or the flash */ + /* becomes ready again */ +/* 11-13-2002 Paul Marchese */ +/* modified while loop conditional statement */ +/* because we were always timing out. */ +/* there is a type mismatch, "addr[0]" */ +/* returns a byte but "mask" is a 32-bit value */ + while ((*(volatile unsigned long *) info-> + start[0] & mask) != mask) +/* original code */ +/* while (addr[0] & mask) != mask) */ + { + /* has the timeout limit been reached? */ + if (get_timer (start) > + CFG_FLASH_WRITE_TOUT) { + /* timeout limit reached */ + printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data); + /* reset the flash */ + flash_cmd (info->portwidth, + addr, 0, + CHIP_CMD_RST); + return (1); + } + /* put flash into read status mode by writing 0x70 to it */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RD_STAT); + } + /* flash is ready, so check the status */ + /* create the status mask to check for errors */ + mask = CHIP_STAT_DPS | CHIP_STAT_VPPS | + CHIP_STAT_PSLBS; + mask = mask | (mask << 16); + /* put flash into read status mode by writing 0x70 to it */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RD_STAT); + /* are there any errors? */ + if ((addr[0] & mask) != 0) { + /* We got a one of the following errors: */ + /* Voltage range, Device protect, or programming */ + /* return the error as a device timeout */ + /* put flash into read status mode by writing 0x70 to it */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RD_STAT); + printf ("Flash programming error at address 0x%08lx\n", dest); + printf ("Flash status register contains 0x%08lx\n", (unsigned long) addr[0]); + /* reset the flash */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RST); + return 1; + } + /* write completed without errors */ + /* reset the flash */ + flash_cmd (info->portwidth, addr, 0, + CHIP_CMD_RST); + return 0; + } else { + /* it's not 16-bits wide, so return an error as a write timeout */ + /* NOTE: you can add routines here to handle other size flash */ + printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8); + printf ("The write code only handles Intel 16-bit wide flash memory\n"); + return 1; + } + } else { + /* not Intel flash so return an error as a write timeout */ + /* NOTE: if it's another type flash, stick its routine here */ + printf ("Error: The flash device is not Intel type\n"); + printf ("The code only supports Intel flash in a 32-bit port width\n"); + return 1; + } + } + + /* end of 32-bit flash code */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) + return 1; + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { + *(unsigned long *) dest = data; + return 0; + } + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + unsigned short low = data & 0xffff; + unsigned short hi = (data >> 16) & 0xffff; + int ret = write_word_intel ((bank_addr_t) dest, hi); + + if (!ret) + ret = write_word_intel ((bank_addr_t) (dest + 2), + low); + + return ret; + } + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *) dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* first, perform an unlock bypass command to speed up flash writes */ + addr[0x555] = 0xAA; + addr[0x2AA] = 0x55; + addr[0x555] = 0x20; + + /* write each byte out */ + for (i = 0; i < 4; i++) { + char *data_ch = (char *) &data; + + addr[0] = 0xA0; + *(((char *) dest) + i) = data_ch[i]; + udelay (10); /* XXX */ + } + + /* we're done, now do an unlock bypass reset */ + addr[0] = 0x90; + addr[0] = 0x00; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c new file mode 100644 index 0000000..32b2b30 --- /dev/null +++ b/board/Marvell/common/i2c.c @@ -0,0 +1,532 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the DB64360 board by Ingo.Assmus@keymile.com + * extra improvments by Brain Waite + */ +#include +#include +#include +#include "../include/mv_gen_reg.h" +#include "../include/core.h" + +#define MAX_I2C_RETRYS 10 +#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */ +#undef DEBUG_I2C +/*#define DEBUG_I2C*/ + +#ifdef DEBUG_I2C +#define DP(x) x +#else +#define DP(x) +#endif + +/* Assuming that there is only one master on the bus (us) */ + +static void i2c_init (int speed, int slaveaddr) +{ + unsigned int n, m, freq, margin, power; + unsigned int actualN = 0, actualM = 0; + unsigned int control, status; + unsigned int minMargin = 0xffffffff; + unsigned int tclk = CFG_TCLK; + unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ + + DP (puts ("i2c_init\n")); +/* gtI2cMasterInit */ + for (n = 0; n < 8; n++) { + for (m = 0; m < 16; m++) { + power = 2 << n; /* power = 2^(n+1) */ + freq = tclk / (10 * (m + 1) * power); + if (i2cFreq > freq) + margin = i2cFreq - freq; + else + margin = freq - i2cFreq; + if (margin < minMargin) { + minMargin = margin; + actualN = n; + actualM = m; + } + } + } + + DP (puts ("setup i2c bus\n")); + + /* Setup bus */ +/* gtI2cReset */ + GT_REG_WRITE (I2C_SOFT_RESET, 0); + + DP (puts ("udelay...\n")); + + udelay (I2C_DELAY); + + DP (puts ("set baudrate\n")); + + GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); + GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); + + udelay (I2C_DELAY * 10); + + DP (puts ("read control, baudrate\n")); + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + GT_REG_READ (I2C_CONTROL, &control); +} + +static uchar i2c_start (void) +{ /* DB64360 checked -> ok */ + unsigned int control, status; + int count = 0; + + DP (puts ("i2c_start\n")); + + /* Set the start bit */ + +/* gtI2cGenerateStartBit() */ + + GT_REG_READ (I2C_CONTROL, &control); + control |= (0x1 << 5); /* generate the I2C_START_BIT */ + GT_REG_WRITE (I2C_CONTROL, control); + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + + count = 0; + while ((status & 0xff) != 0x08) { + udelay (I2C_DELAY); + if (count > 20) { + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + + return (0); +} + +static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit) +{ + unsigned int status, data, bits = 7; + int count = 0; + + DP (puts ("i2c_select_device\n")); + + /* Output slave address */ + + if (ten_bit) { + bits = 10; + } + + data = (dev_addr << 1); + /* set the read bit */ + data |= read; + GT_REG_WRITE (I2C_DATA, data); + /* assert the address */ + RESET_REG_BITS (I2C_CONTROL, BIT3); + + udelay (I2C_DELAY); + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count = 0; + while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { + udelay (I2C_DELAY); + if (count > 20) { + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + + if (bits == 10) { + printf ("10 bit I2C addressing not yet implemented\n"); + return (0xff); + } + + return (0); +} + +static uchar i2c_get_data (uchar * return_data, int len) +{ + + unsigned int data, status = 0; + int count = 0; + + DP (puts ("i2c_get_data\n")); + + while (len) { + + /* Get and return the data */ + + RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); + + udelay (I2C_DELAY * 5); + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x50) { + udelay (I2C_DELAY); + if (count > 2) { + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + return 0; + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + GT_REG_READ (I2C_DATA, &data); + len--; + *return_data = (uchar) data; + return_data++; + } + RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3); + while ((status & 0xff) != 0x58) { + udelay (I2C_DELAY); + if (count > 200) { + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */ + + return (0); +} + +static uchar i2c_write_data (unsigned int *data, int len) +{ + unsigned int status; + int count = 0; + unsigned int temp; + unsigned int *temp_ptr = data; + + DP (puts ("i2c_write_data\n")); + + while (len) { + temp = (unsigned int) (*temp_ptr); + GT_REG_WRITE (I2C_DATA, temp); + RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); + + udelay (I2C_DELAY); + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x28) { + udelay (I2C_DELAY); + if (count > 20) { + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + len--; + temp_ptr++; + } +/* 11-14-2002 Paul Marchese */ +/* Can't have the write issuing a stop command */ +/* it's wrong to have a stop bit in read stream or write stream */ +/* since we don't know if it's really the end of the command */ +/* or whether we have just send the device address + offset */ +/* we will push issuing the stop command off to the original */ +/* calling function */ + /* set the interrupt bit in the control register */ + GT_REG_WRITE (I2C_CONTROL, (0x1 << 3)); + udelay (I2C_DELAY * 10); + return (0); +} + +/* 11-14-2002 Paul Marchese */ +/* created this function to get the i2c_write() */ +/* function working properly. */ +/* function to write bytes out on the i2c bus */ +/* this is identical to the function i2c_write_data() */ +/* except that it requires a buffer that is an */ +/* unsigned character array. You can't use */ +/* i2c_write_data() to send an array of unsigned characters */ +/* since the byte of interest ends up on the wrong end of the bus */ +/* aah, the joys of big endian versus little endian! */ +/* */ +/* returns 0 = success */ +/* anything other than zero is failure */ +static uchar i2c_write_byte (unsigned char *data, int len) +{ + unsigned int status; + int count = 0; + unsigned int temp; + unsigned char *temp_ptr = data; + + DP (puts ("i2c_write_byte\n")); + + while (len) { + /* Set and assert the data */ + temp = *temp_ptr; + GT_REG_WRITE (I2C_DATA, temp); + RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); + + udelay (I2C_DELAY); + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x28) { + udelay (I2C_DELAY); + if (count > 20) { + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + len--; + temp_ptr++; + } +/* Can't have the write issuing a stop command */ +/* it's wrong to have a stop bit in read stream or write stream */ +/* since we don't know if it's really the end of the command */ +/* or whether we have just send the device address + offset */ +/* we will push issuing the stop command off to the original */ +/* calling function */ +/* GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4)); + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */ + /* set the interrupt bit in the control register */ + GT_REG_WRITE (I2C_CONTROL, (0x1 << 3)); + udelay (I2C_DELAY * 10); + + return (0); +} + +static uchar +i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit, + int alen) +{ + uchar status; + unsigned int table[2]; + +/* initialize the table of address offset bytes */ +/* utilized for 2 byte address offsets */ +/* NOTE: the order is high byte first! */ + table[1] = offset & 0xff; /* low byte */ + table[0] = offset / 0x100; /* high byte */ + + DP (puts ("i2c_set_dev_offset\n")); + + status = i2c_select_device (dev_addr, 0, ten_bit); + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to select device setting offset: 0x%02x\n", + status); +#endif + return status; + } +/* check the address offset length */ + if (alen == 0) + /* no address offset */ + return (0); + else if (alen == 1) { + /* 1 byte address offset */ + status = i2c_write_data (&offset, 1); + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to write data: 0x%02x\n", status); +#endif + return status; + } + } else if (alen == 2) { + /* 2 bytes address offset */ + status = i2c_write_data (table, 2); + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to write data: 0x%02x\n", status); +#endif + return status; + } + } else { + /* address offset unknown or not supported */ + printf ("Address length offset %d is not supported\n", alen); + return 1; + } + return 0; /* sucessful completion */ +} + +uchar +i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, + int len) +{ + uchar status = 0; + unsigned int i2cFreq = CFG_I2C_SPEED; + + DP (puts ("i2c_read\n")); + + i2c_init (i2cFreq, 0); /* set the i2c frequency */ + + status = i2c_start (); + + if (status) { +#ifdef DEBUG_I2C + printf ("Transaction start failed: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to set slave address & offset: 0x%02x\n", + status); +#endif + return status; + } + + i2c_init (i2cFreq, 0); /* set the i2c frequency again */ + + status = i2c_start (); + if (status) { +#ifdef DEBUG_I2C + printf ("Transaction restart failed: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_select_device (dev_addr, 1, 0); /* send the slave address */ + if (status) { +#ifdef DEBUG_I2C + printf ("Address not acknowledged: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_get_data (data, len); + if (status) { +#ifdef DEBUG_I2C + printf ("Data not recieved: 0x%02x\n", status); +#endif + return status; + } + + return 0; +} + +/* 11-14-2002 Paul Marchese */ +/* Function to set the I2C stop bit */ +void i2c_stop (void) +{ + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); +} + +/* 11-14-2002 Paul Marchese */ +/* I2C write function */ +/* dev_addr = device address */ +/* offset = address offset */ +/* alen = length in bytes of the address offset */ +/* data = pointer to buffer to read data into */ +/* len = # of bytes to read */ +/* */ +/* returns 0 = succesful */ +/* anything but zero is failure */ +uchar +i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, + int len) +{ + uchar status = 0; + unsigned int i2cFreq = CFG_I2C_SPEED; + + DP (puts ("i2c_write\n")); + + i2c_init (i2cFreq, 0); /* set the i2c frequency */ + + status = i2c_start (); /* send a start bit */ + + if (status) { +#ifdef DEBUG_I2C + printf ("Transaction start failed: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to set slave address & offset: 0x%02x\n", + status); +#endif + return status; + } + + + status = i2c_write_byte (data, len); /* write the data */ + if (status) { +#ifdef DEBUG_I2C + printf ("Data not written: 0x%02x\n", status); +#endif + return status; + } + /* issue a stop bit */ + i2c_stop (); + return 0; +} + +/* 11-14-2002 Paul Marchese */ +/* function to determine if an I2C device is present */ +/* chip = device address of chip to check for */ +/* */ +/* returns 0 = sucessful, the device exists */ +/* anything other than zero is failure, no device */ +int i2c_probe (uchar chip) +{ + + /* We are just looking for an back. */ + /* To see if the device/chip is there */ + +#ifdef DEBUG_I2C + unsigned int i2c_status; +#endif + uchar status = 0; + unsigned int i2cFreq = CFG_I2C_SPEED; + + DP (puts ("i2c_probe\n")); + + i2c_init (i2cFreq, 0); /* set the i2c frequency */ + + status = i2c_start (); /* send a start bit */ + + if (status) { +#ifdef DEBUG_I2C + printf ("Transaction start failed: 0x%02x\n", status); +#endif + return (int) status; + } + + status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */ + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to set slave address: 0x%02x\n", status); +#endif + return (int) status; + } +#ifdef DEBUG_I2C + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status); + printf ("address %#x returned %#x\n", chip, i2c_status); +#endif + /* issue a stop bit */ + i2c_stop (); + return 0; /* successful completion */ +} diff --git a/board/Marvell/common/i2c.h b/board/Marvell/common/i2c.h new file mode 100644 index 0000000..b669ff0 --- /dev/null +++ b/board/Marvell/common/i2c.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the DB64360 board by Ingo.Assmus@keymile.com + */ + +#ifndef __I2C_H__ +#define __I2C_H__ + +/* function declarations */ +uchar i2c_read(uchar, unsigned int, int, uchar*, int); + +#endif diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c new file mode 100644 index 0000000..d26f883 --- /dev/null +++ b/board/Marvell/common/intel_flash.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the marvell db64360 eval board by + * Ingo Assmus + */ + +#include +#include +#include "../include/mv_gen_reg.h" +#include "../include/memory.h" +#include "intel_flash.h" + + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +static void bank_reset (flash_info_t * info, int sect) +{ + bank_addr_t addrw, eaddrw; + + addrw = (bank_addr_t) info->start[sect]; + eaddrw = BANK_ADDR_NEXT_WORD (addrw); + + while (addrw < eaddrw) { +#ifdef FLASH_DEBUG + printf (" writing reset cmd to addr 0x%08lx\n", + (unsigned long) addrw); +#endif + *addrw = BANK_CMD_RST; + addrw++; + } +} + +static void bank_erase_init (flash_info_t * info, int sect) +{ + bank_addr_t addrw, saddrw, eaddrw; + int flag; + +#ifdef FLASH_DEBUG + printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG); + printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1); + printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2); + printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT); + printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST); + printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY); + printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR); +#endif + + saddrw = (bank_addr_t) info->start[sect]; + eaddrw = BANK_ADDR_NEXT_WORD (saddrw); + +#ifdef FLASH_DEBUG + printf ("erasing sector %d, start addr = 0x%08lx " + "(bank next word addr = 0x%08lx)\n", sect, + (unsigned long) saddrw, (unsigned long) eaddrw); +#endif + + /* Disable intrs which might cause a timeout here */ + flag = disable_interrupts (); + + for (addrw = saddrw; addrw < eaddrw; addrw++) { +#ifdef FLASH_DEBUG + printf (" writing erase cmd to addr 0x%08lx\n", + (unsigned long) addrw); +#endif + *addrw = BANK_CMD_ERASE1; + *addrw = BANK_CMD_ERASE2; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); +} + +static int bank_erase_poll (flash_info_t * info, int sect) +{ + bank_addr_t addrw, saddrw, eaddrw; + int sectdone, haderr; + + saddrw = (bank_addr_t) info->start[sect]; + eaddrw = BANK_ADDR_NEXT_WORD (saddrw); + + sectdone = 1; + haderr = 0; + + for (addrw = saddrw; addrw < eaddrw; addrw++) { + bank_word_t stat = *addrw; + +#ifdef FLASH_DEBUG + printf (" checking status at addr " + "0x%08x [0x%08x]\n", (unsigned long) addrw, stat); +#endif + if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY) + sectdone = 0; + else if ((stat & BANK_STAT_ERR) != 0) { + printf (" failed on sector %d " + "(stat = 0x%08x) at " + "address 0x%p\n", sect, stat, addrw); + *addrw = BANK_CMD_CLR_STAT; + haderr = 1; + } + } + + if (haderr) + return (-1); + else + return (sectdone); +} + +int write_word_intel (bank_addr_t addr, bank_word_t value) +{ + bank_word_t stat; + ulong start; + int flag, retval; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = BANK_CMD_PROG; + + *addr = value; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + retval = 0; + + /* data polling for D7 */ + start = get_timer (0); + do { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + retval = 1; + goto done; + } + stat = *addr; + } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); + + if ((stat & BANK_STAT_ERR) != 0) { + printf ("flash program failed (stat = 0x%08lx) " + "at address 0x%08lx\n", (ulong) stat, (ulong) addr); + *addr = BANK_CMD_CLR_STAT; + retval = 3; + } + + done: + /* reset to read mode */ + *addr = BANK_CMD_RST; + + return (retval); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase_intel (flash_info_t * info, int s_first, int s_last) +{ + int prot, sect, haderr; + ulong start, now, last; + +#ifdef FLASH_DEBUG + printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" + " Bank # %d: ", s_last - s_first + 1, s_first, s_last, + (info - flash_info) + 1); + flash_print_info (info); +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : "")); + } + + start = get_timer (0); + last = 0; + haderr = 0; + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + ulong estart; + int sectdone; + + bank_erase_init (info, sect); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + estart = get_timer (start); + + do { + now = get_timer (start); + + if (now - estart > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout (sect %d)\n", sect); + haderr = 1; + break; + } +#ifndef FLASH_DEBUG + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } +#endif + + sectdone = bank_erase_poll (info, sect); + + if (sectdone < 0) { + haderr = 1; + break; + } + + } while (!sectdone); + + if (haderr) + break; + } + } + + if (haderr > 0) + printf (" failed\n"); + else + printf (" done\n"); + + /* reset to read mode */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + bank_reset (info, sect); + } + } + return haderr; +} diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h new file mode 100644 index 0000000..666a4cd --- /dev/null +++ b/board/Marvell/common/intel_flash.h @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the marvell db64360 eval board by + * Ingo Assmus + */ + +/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ + +/* + * acceptable chips types are: + * + * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A + */ + +/* register addresses, valid only following an CHIP_CMD_RD_ID command */ +#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */ +#define CHIP_ADDR_REG_DEV 0x000001 /* device id */ +#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */ +#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */ + +/* Commands */ +#define CHIP_CMD_RST 0xFF /* reset flash */ +#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ +#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ +#define CHIP_CMD_RD_STAT 0x70 /* read the status register */ +#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ +#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */ +#define CHIP_CMD_PROG 0x40 /* program word command */ +#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ +#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ +#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ +#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ +#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ +#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ +#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ + +/* status register bits */ +#define CHIP_STAT_DPS 0x02 /* Device Protect Status */ +#define CHIP_STAT_VPPS 0x08 /* VPP Status */ +#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ +#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ +#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ +#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ + +#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \ + CHIP_STAT_ECLBS | CHIP_STAT_PSLBS) + +/* ID and Lock Configuration */ +#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ +#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ +#define CHIP_RD_ID_DEV CFG_FLASH_ID + +/* dimensions */ +#define CHIP_WIDTH 2 /* chips are in 16 bit mode */ +#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */ +#define CHIP_NBLOCKS 128 +#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */ +#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS) + +/********************** DEFINES for Hymod Flash ******************************/ + +/* + * The hymod board has 2 x 28F320J5 chips running in + * 16 bit mode, for a 32 bit wide bank. + */ + +typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */ +typedef volatile bank_word_t *bank_addr_t; +typedef unsigned long bank_size_t; /* want this big - >= 32 bit */ + +#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */ +#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */ + +#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH) +#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT) +#define BANK_NBLOCKS CHIP_NBLOCKS +#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH) +#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH) + +#define MAX_BANKS 1 /* only one bank possible */ + +/* align bank addresses and sizes to bank word boundaries */ +#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(BANK_WIDTH - 1))) +#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \ + (bank_size_t)(s) + (BANK_WIDTH - 1))) + +/* align bank addresses and sizes to bank block boundaries */ +#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(BANK_BLKSZ - 1))) +#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \ + (bank_size_t)(s) + (BANK_BLKSZ - 1))) + +/* align bank addresses and sizes to bank boundaries */ +#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(BANK_SIZE - 1))) +#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \ + (bank_size_t)(s) + (BANK_SIZE - 1))) + +/* add an offset to a bank address */ +#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \ + (bank_size_t)(o)) + +/* get base address of bank b, given flash base address a */ +#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ + (bank_size_t)(b) * BANK_SIZE) + +/* adjust a bank address to start of next word, block or bank */ +#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ + BANK_WIDTH) +#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ + BANK_BLKSZ) +#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ + BANK_SIZE) + +/* get bank address of chip register r given a bank base address a */ +#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ + ((bank_size_t)(r) << BANK_WSHIFT)) + +/* make a bank address for each chip register address */ + +#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN) +#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV) +#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM) +#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b)) + +/* + * replicate a chip cmd/stat/rd value into each byte position within a word + * so that multiple chips are accessed in a single word i/o operation + * + * this must be as wide as the bank_word_t type, and take into account the + * chip width and bank layout + */ + +#define BANK_FILL_WORD(o) ((bank_word_t)(o)) + +/* make a bank word value for each chip cmd/stat/rd value */ + +/* Commands */ +#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST) +#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID) +#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT) +#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT) +#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1) +#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2) +#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG) +#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK) +#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK) +#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR) +#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK) + +/* status register bits */ +#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS) +#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS) +#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS) +#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS) +#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS) +#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS) +#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY) + +#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR) + +/* ID and Lock Configuration */ +#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK) +#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN) +#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV) diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c new file mode 100644 index 0000000..45353af --- /dev/null +++ b/board/Marvell/common/memory.c @@ -0,0 +1,1390 @@ +/* + * Copyright - Galileo technology. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * written or collected and sometimes rewritten by + * Ingo Assmus + * + */ + + +#include +#include "../include/core.h" +#include "../include/memory.h" + +/******************************************************************************* +* memoryGetBankBaseAddress - Returns the base address of a memory bank. +* DESCRIPTION: +* This function returns the base address of one of the SDRAM’s memory +* banks. There are 4 memory banks and each one represents one DIMM side. +* INPUT: +* MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h. +* OUTPUT: +* None. +* RETURN: +* 32 bit Memory bank base address. +*******************************************************************************/ +static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank) +{ + switch (bank) { + case BANK0: + return SCS_0_LOW_DECODE_ADDRESS; + case BANK1: + return SCS_1_LOW_DECODE_ADDRESS; + case BANK2: + return SCS_2_LOW_DECODE_ADDRESS; + case BANK3: + return SCS_3_LOW_DECODE_ADDRESS; + + } + return SCS_0_LOW_DECODE_ADDRESS; /* default value */ +} + +unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank) +{ + unsigned int base; + unsigned int regOffset = memoryGetBankRegOffset (bank); + + GT_REG_READ (regOffset, &base); + base = base << 16; /* MV6436x */ + return base; +} + +/******************************************************************************* +* memoryGetDeviceBaseAddress - Returns the base address of a device. +* DESCRIPTION: +* This function returns the base address of a device on the system. There +* are 5 possible devices (0 - 4 and one boot device) as defined in +* gtMemory.h. Each of the device parameters is maped to one of the CS +* (Devices chip selects) base address register. +* INPUT: +* device - Selects one of the five devices as defined in Memory.h. +* OUTPUT: +* None. +* RETURN: +* 32 bit Device base address. +* +*******************************************************************************/ +static unsigned int memoryGetDeviceRegOffset (DEVICE device) +{ + switch (device) { + case DEVICE0: + return CS_0_LOW_DECODE_ADDRESS; + case DEVICE1: + return CS_1_LOW_DECODE_ADDRESS; + case DEVICE2: + return CS_2_LOW_DECODE_ADDRESS; + case DEVICE3: + return CS_3_LOW_DECODE_ADDRESS; + case BOOT_DEVICE: + return BOOTCS_LOW_DECODE_ADDRESS; + } + return CS_0_LOW_DECODE_ADDRESS; /* default value */ +} + +unsigned int memoryGetDeviceBaseAddress (DEVICE device) +{ + unsigned int regBase; + unsigned int regOffset = memoryGetDeviceRegOffset (device); + + GT_REG_READ (regOffset, ®Base); + + regBase = regBase << 16; /* MV6436x */ + return regBase; +} + +/******************************************************************************* +* MemoryGetPciBaseAddr - Returns the base address of a PCI window. +* DESCRIPTION: +* This function returns the base address of a PCI window. There are 5 +* possible PCI windows (memory 0 - 3 and one for I/O) for each PCI +* interface as defined in gtMemory.h, used by the CPU's address decoding +* mechanism. +* New in MV6436x +* INPUT: +* pciWindow - Selects one of the PCI windows as defined in Memory.h. +* OUTPUT: +* None. +* RETURN: +* 32 bit PCI window base address. +*******************************************************************************/ +unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow) +{ + unsigned int baseAddrReg, base; + + switch (pciWindow) { + case PCI_0_IO: + baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */ + break; + case PCI_0_MEM0: + baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */ + break; + case PCI_0_MEM1: + baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */ + break; + case PCI_0_MEM2: + baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */ + break; + case PCI_0_MEM3: + baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */ + break; +#ifdef INCLUDE_PCI_1 + case PCI_1_IO: + baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */ + break; + case PCI_1_MEM0: + baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */ + break; + case PCI_1_MEM1: + baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */ + break; + case PCI_1_MEM2: + baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */ + break; + case PCI_1_MEM3: + baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */ + break; +#endif /* INCLUDE_PCI_1 */ + default: + return 0xffffffff; + } + GT_REG_READ (baseAddrReg, &base); + return (base << 16); +} + +/******************************************************************************* +* memoryGetBankSize - Returns the size of a memory bank. +* DESCRIPTION: +* This function returns the size of memory bank as described in +* 'gtMemoryGetBankBaseAddress' function. +* INPUT: +* bank - Selects one of the four banks as defined in Memory.h. +* OUTPUT: +* None. +* RETURN: +* 32 bit size memory bank size or 0 for a closed or non populated bank. +* +*******************************************************************************/ +unsigned int memoryGetBankSize (MEMORY_BANK bank) +{ + unsigned int sizeReg, size; + MEMORY_WINDOW window; + + switch (bank) { + case BANK0: + sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /* CS_0_SIZE; */ + window = CS_0_WINDOW; + break; + case BANK1: + sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /* CS_1_SIZE; */ + window = CS_1_WINDOW; + break; + case BANK2: + sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /* CS_2_SIZE; */ + window = CS_2_WINDOW; + break; + case BANK3: + sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /* CS_3_SIZE; */ + window = CS_3_WINDOW; + break; + default: + return 0; + break; + } + /* If the window is closed, a size of 0 is returned */ + if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED) + return 0; + GT_REG_READ (sizeReg, &size); + size = ((size << 16) | 0xffff) + 1; + return size; +} + +/******************************************************************************* +* memoryGetDeviceSize - Returns the size of a device memory space. +* DESCRIPTION: +* This function returns the memory space size of a given device. +* INPUT: +* device - Selects one of the five devices as defined in Memory.h. +* OUTPUT: +* None. +* RETURN: +* 32 bit size of a device memory space. +*******************************************************************************/ +unsigned int memoryGetDeviceSize (DEVICE device) +{ + unsigned int sizeReg, size; + MEMORY_WINDOW window; + + switch (device) { + case DEVICE0: + sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */ + window = DEVCS_0_WINDOW; + break; + case DEVICE1: + sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */ + window = DEVCS_1_WINDOW; + break; + case DEVICE2: + sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */ + window = DEVCS_2_WINDOW; + break; + case DEVICE3: + sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */ + window = DEVCS_3_WINDOW; + break; + case BOOT_DEVICE: + sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */ + window = BOOT_CS_WINDOW; + break; + default: + return 0; + break; + } + /* If the window is closed, a size of 0 is returned */ + if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED) + return 0; + GT_REG_READ (sizeReg, &size); + size = ((size << 16) | 0xffff) + 1; + return size; +} + +/******************************************************************************* +* MemoryGetPciWindowSize - Returns the size of a PCI memory window. +* DESCRIPTION: +* This function returns the size of a PCI window. +* INPUT: +* pciWindow - Selects one of the PCI memory windows as defined in +* Memory.h. +* OUTPUT: +* None. +* RETURN: +* 32 bit size of a PCI memory window. +*******************************************************************************/ +unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow) +{ + unsigned int sizeReg, size; + + switch (pciWindow) { + case PCI_0_IO: + sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */ + break; + case PCI_0_MEM0: + sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */ + break; + case PCI_0_MEM1: + sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */ + break; + case PCI_0_MEM2: + sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */ + break; + case PCI_0_MEM3: + sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */ + break; +#ifdef INCLUDE_PCI_1 + case PCI_1_IO: + sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */ + break; + case PCI_1_MEM0: + sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */ + break; + case PCI_1_MEM1: + sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */ + break; + case PCI_1_MEM2: + sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */ + break; + case PCI_1_MEM3: + sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */ + break; +#endif /* INCLUDE_PCI_1 */ + default: + return 0x0; + } + /* If the memory window is disabled, retrun size = 0 */ + if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow) + == MEM_WINDOW_DISABLED) + return 0; + GT_REG_READ (sizeReg, &size); + size = ((size << 16) | 0xffff) + 1; + return size; +} + +/******************************************************************************* +* memoryGetDeviceWidth - Returns the width of a given device. +* DESCRIPTION: +* The MV's device interface supports up to 32 Bit wide devices. A device +* can have a 1, 2, 4 or 8 Bytes data width. This function returns the +* width of a device as defined by the user or the operating system. +* INPUT: +* device - Selects one of the five devices as defined in Memory.h. +* OUTPUT: +* None. +* RETURN: +* Device width in Bytes (1,2,4 or 8), 0 if error had occurred. +*******************************************************************************/ +unsigned int memoryGetDeviceWidth (DEVICE device) +{ + unsigned int width; + unsigned int regValue; + + GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, ®Value); + width = (regValue & (BIT20 | BIT21)) >> 20; + return (BIT0 << width); +} + +/******************************************************************************* +* memoryMapBank - Set new base address and size for one of the memory +* banks. +* +* DESCRIPTION: +* The CPU interface address decoding map consists of 21 address windows +* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each +* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte +* space. Each address window is defined by two registers - base and size. +* The CPU address is compared with the values in the various CPU windows +* until a match is found and the address is than targeted to that window. +* This function sets new base and size for one the memory banks +* (CS0 - CS3). It is the programmer`s responsibility to make sure that +* there are no conflicts with other memory spaces. When two memory spaces +* overlap, the MV’s behavior is not defined .If a bank needs to be closed, +* set the ’bankLength’ parameter size to 0x0. +* +* INPUT: +* bank - One of the memory banks (CS0-CS3) as defined in gtMemory.h. +* bankBase - The memory bank base address. +* bankLength - The memory bank size. This function will decrement the +* 'bankLength' parameter by one and then check if the size is +* valid. A valid size must be programed from LSB to MSB as +* sequence of ‘1’s followed by sequence of ‘0’s. +* To close a memory window simply set the size to 0. +* NOTE!!! +* The size must be in 64Kbyte granularity. +* The base address must be aligned to the size. +* OUTPUT: +* None. +* RETURN: +* False for invalid size, true otherwise. +* +* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!! +* +*******************************************************************************/ + +bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase, + unsigned int bankLength) +{ + unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift; + +/* PCI_INTERNAL_BAR pciBAR; */ + + switch (bank) { + case BANK0: + baseReg = SCS_0_LOW_DECODE_ADDRESS; /*CS_0_BASE_ADDR; */ + sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /*CS_0_SIZE; */ +/* pciBAR = PCI_CS0_BAR; */ + break; + case BANK1: + baseReg = SCS_1_LOW_DECODE_ADDRESS; /*CS_1_BASE_ADDR; */ + sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /*CS_1_SIZE; */ + /* pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */ + break; + case BANK2: + baseReg = SCS_2_LOW_DECODE_ADDRESS; /*CS_2_BASE_ADDR; */ + sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /*CS_2_SIZE; */ +/* pciBAR = PCI_CS2_BAR;*/ + break; + case BANK3: + baseReg = SCS_3_LOW_DECODE_ADDRESS; /*CS_3_BASE_ADDR; */ + sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /*CS_3_SIZE; */ +/* pciBAR = PCI_CS3_BAR; */ + break; + default: + return false; + } + /* If the size is 0, the window will be disabled */ + if (bankLength == 0) { + MemoryDisableWindow (CS_0_WINDOW << bank); + /* Disable the BAR from the PCI slave side */ +/* gtPci0DisableInternalBAR(pciBAR); */ +/* gtPci1DisableInternalBAR(pciBAR); */ + return true; + } + /* The base address must be aligned to the size */ + if ((bankBase % bankLength) != 0) { + return false; + } + if (bankLength >= MINIMUM_MEM_BANK_SIZE) { + newBase = bankBase >> 16; + newSize = bankLength >> 16; + /* Checking that the size is a sequence of '1' followed by a + sequence of '0' starting from LSB to MSB. */ + temp = newSize - 1; + for (rShift = 0; rShift < 16; rShift++) { + temp = temp >> rShift; + if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ + /* or the size is not valid */ + if (temp > 0x0) + return false; + else + break; + } + } +#ifdef DEBUG + { + unsigned int oldBase, oldSize; + + GT_REG_READ (baseReg, &oldBase); + GT_REG_READ (sizeReg + 8, &oldSize); + + printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n", + bank, oldBase, oldSize, newBase, newSize); + } +#endif + /* writing the new values */ + GT_REG_WRITE (baseReg, newBase); + GT_REG_WRITE (sizeReg, newSize - 1); + /* Enable back the window */ + MemoryEnableWindow (CS_0_WINDOW << bank); + /* Enable the BAR from the PCI slave side */ +/* gtPci0EnableInternalBAR(pciBAR); */ +/* gtPci1EnableInternalBAR(pciBAR); */ + return true; + } + return false; +} + + +/******************************************************************************* +* memoryMapDeviceSpace - Set new base address and size for one of the device +* windows. +* +* DESCRIPTION: +* The CPU interface address decoding map consists of 21 address windows +* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each +* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte +* space. Each address window is defined by two registers - base and size. +* The CPU address is compared with the values in the various CPU windows +* until a match is found and the address is than targeted to that window. +* This function sets new base and size for one the device windows +* (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure +* that there are no conflicts with other memory spaces. When two memory +* spaces overlap, the MV’s behavior is not defined .If a device window +* needs to be closed, set the 'deviceLength' parameter size to 0x0. +* +* INPUT: +* device - One of the device windows (DEV_CS0-DEV_CS3) as +* defined in gtMemory.h. +* deviceBase - The device window base address. +* deviceLength - The device window size. This function will decrement +* the 'deviceLength' parameter by one and then +* check if the size is valid. A valid size must be +* programed from LSB to MSB as sequence of ‘1’s +* followed by sequence of ‘0’s. +* To close a memory window simply set the size to 0. +* +* NOTE!!! +* The size must be in 64Kbyte granularity. +* The base address must be aligned to the size. +* +* OUTPUT: +* None. +* +* RETURN: +* False for invalid size, true otherwise. +* +* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!! +* +*******************************************************************************/ + +bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase, + unsigned int deviceLength) +{ + unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift; + +/* PCI_INTERNAL_BAR pciBAR;*/ + + switch (device) { + case DEVICE0: + baseReg = CS_0_LOW_DECODE_ADDRESS; /*DEV_CS0_BASE_ADDR; */ + sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */ +/* pciBAR = PCI_DEV_CS0_BAR; */ + break; + case DEVICE1: + baseReg = CS_1_LOW_DECODE_ADDRESS; /*DEV_CS1_BASE_ADDR; */ + sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */ +/* pciBAR = PCI_DEV_CS1_BAR; */ + break; + case DEVICE2: + baseReg = CS_2_LOW_DECODE_ADDRESS; /*DEV_CS2_BASE_ADDR; */ + sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */ +/* pciBAR = PCI_DEV_CS2_BAR; */ + break; + case DEVICE3: + baseReg = CS_3_LOW_DECODE_ADDRESS; /*DEV_CS3_BASE_ADDR; */ + sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */ +/* pciBAR = PCI_DEV_CS3_BAR; */ + break; + case BOOT_DEVICE: + baseReg = BOOTCS_LOW_DECODE_ADDRESS; /*BOOTCS_BASE_ADDR; */ + sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */ +/* pciBAR = PCI_BOOT_CS_BAR; */ + break; + default: + return false; + } + if (deviceLength == 0) { + MemoryDisableWindow (DEVCS_0_WINDOW << device); + /* Disable the BAR from the PCI slave side */ +/* gtPci0DisableInternalBAR(pciBAR); */ +/* gtPci1DisableInternalBAR(pciBAR); */ + return true; + } + /* The base address must be aligned to the size */ + if ((deviceBase % deviceLength) != 0) { + return false; + } + if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) { + newBase = deviceBase >> 16; + newSize = deviceLength >> 16; + /* Checking that the size is a sequence of '1' followed by a + sequence of '0' starting from LSB to MSB. */ + temp = newSize - 1; + for (rShift = 0; rShift < 16; rShift++) { + temp = temp >> rShift; + if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ + /* or the size is not valid */ + if (temp > 0x0) + return false; + else + break; + } + } + /* writing the new values */ + GT_REG_WRITE (baseReg, newBase); + GT_REG_WRITE (sizeReg, newSize - 1); + MemoryEnableWindow (DEVCS_0_WINDOW << device); + /* Enable the BAR from the PCI slave side */ +/* gtPci0EnableInternalBAR(pciBAR); */ +/* gtPci1EnableInternalBAR(pciBAR); */ + return true; + } + return false; +} + +/******************************************************************************* +* MemorySetPciWindow - Set new base address and size for one of the PCI +* windows. +* +* DESCRIPTION: +* The CPU interface address decoding map consists of 21 address windows +* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each +* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte +* space. Each address window is defined by two registers - base and size. +* The CPU address is compared with the values in the various CPU windows +* until a match is found and the address is than targeted to that window. +* This function sets new base and size for one the PCI windows +* (PCI memory0/1/2..). It is the programmer`s responsibility to make sure +* that there are no conflicts with other memory spaces. When two memory +* spaces overlap, the MV’s behavior is not defined .If a PCI window +* needs to be closed, set the 'pciWindowSize' parameter size to 0x0. +* +* INPUT: +* pciWindow - One of the PCI windows as defined in gtMemory.h. +* pciWindowBase - The PCI window base address. +* pciWindowSize - The PCI window size. This function will decrement the +* 'pciWindowSize' parameter by one and then check if the +* size is valid. A valid size must be programed from LSB +* to MSB as sequence of ‘1’s followed by sequence of ‘0’s. +* To close a memory window simply set the size to 0. +* +* NOTE!!! +* The size must be in 64Kbyte granularity. +* The base address must be aligned to the size. +* +* OUTPUT: +* None. +* +* RETURN: +* False for invalid size, true otherwise. +* +*******************************************************************************/ +bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase, + unsigned int pciWindowSize) +{ + unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift; + + switch (pciWindow) { + case PCI_0_IO: + baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */ + sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */ + break; + case PCI_0_MEM0: + baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */ + sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */ + break; + case PCI_0_MEM1: + baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */ + sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */ + break; + case PCI_0_MEM2: + baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */ + sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */ + break; + case PCI_0_MEM3: + baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */ + sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */ + break; +#ifdef INCLUDE_PCI_1 + case PCI_1_IO: + baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */ + sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */ + break; + case PCI_1_MEM0: + baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */ + sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */ + break; + case PCI_1_MEM1: + baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */ + sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */ + break; + case PCI_1_MEM2: + baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */ + sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */ + break; + case PCI_1_MEM3: + baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */ + sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */ + break; +#endif /* INCLUDE_PCI_1 */ + default: + return false; + } + if (pciWindowSize == 0) { + MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow); + return true; + } + /* The base address must be aligned to the size */ + if ((pciWindowBase % pciWindowSize) != 0) { + return false; + } + if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) { + pciWindowBase >>= 16; + pciWindowSize >>= 16; + /* Checking that the size is a sequence of '1' followed by a + sequence of '0' starting from LSB to MSB. */ + temp = pciWindowSize - 1; + for (rShift = 0; rShift < 16; rShift++) { + temp = temp >> rShift; + if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ + /* or the size is not valid */ + if (temp > 0x0) + return false; + else + break; + } + } + GT_REG_WRITE (sizeReg, pciWindowSize - 1); + GT_REG_READ (baseAddrReg, ¤tLow); + pciWindowBase = + (pciWindowBase & 0xfffff) | (currentLow & 0xfff00000); + GT_REG_WRITE (baseAddrReg, pciWindowBase); + MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow); + return true; + } + return false; +} + +/******************************************************************************* +* memoryMapInternalRegistersSpace - Sets new base address for the internal +* registers memory space. +* +* DESCRIPTION: +* This function set new base address for the internal register’s memory +* space (the size is fixed and cannot be modified). The function does not +* handle overlapping with other memory spaces, it is the programer's +* responsibility to ensure that overlapping does not occur. +* When two memory spaces overlap, the MV’s behavior is not defined. +* +* INPUT: +* internalRegBase - new base address for the internal register’s memory +* space. +* +* OUTPUT: +* None. +* +* RETURN: +* true on success, false on failure +* +*******************************************************************************/ +/******************************************************************** +* memoryMapInternalRegistersSpace - Sets new base address for the internals +* registers. +* +* INPUTS: unsigned int internalRegBase - The new base address. +* RETURNS: true on success, false on failure +*********************************************************************/ +bool memoryMapInternalRegistersSpace (unsigned int internalRegBase) +{ + unsigned int currentValue; + unsigned int internalValue = internalRegBase; + + internalRegBase = (internalRegBase >> 16); + GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue); + internalRegBase = (currentValue & 0xff000000) | internalRegBase; + GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase); + /* initializing also the global variable 'internalRegBaseAddr' */ +/* gtInternalRegBaseAddr = internalValue; */ + INTERNAL_REG_BASE_ADDR = internalValue; + return true; +} + +/******************************************************************************* +* memoryGetInternalRegistersSpace - Returns the internal registers Base +* address. +* +* DESCRIPTION: +* This function returns the base address of the internal register’s +* memory space . +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32 bit base address of the internal register’s memory space. +* +*******************************************************************************/ +unsigned int memoryGetInternalRegistersSpace (void) +{ + unsigned int currentValue = 0; + + GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue); + return ((currentValue & 0x000fffff) << 16); +} + +/******************************************************************************* +* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address. +* +* DESCRIPTION: +* The Atlantis incorporate integrated 2Mbit SRAM for general use. This +* funcnion return the SRAM's base address. +* INPUT: +* None. +* OUTPUT: +* None. +* RETURN: +* 32 bit SRAM's base address. +* +*******************************************************************************/ +unsigned int memoryGetInternalSramBaseAddr (void) +{ + return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16); +} + +/******************************************************************************* +* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address. +* +* DESCRIPTION: +* The Atlantis incorporate integrated 2Mbit SRAM for general use. This +* function sets a new base address to the SRAM . +* INPUT: +* sramBaseAddress - The SRAM's base address. +* OUTPUT: +* None. +* RETURN: +* None. +* +*******************************************************************************/ +void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress) +{ + GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16); +} + +/******************************************************************************* +* memorySetProtectRegion - Set protection mode for one of the 8 regions. +* +* DESCRIPTION: +* The CPU interface supports configurable access protection. This includes +* up to eight address ranges defined to a different protection type : +* whether the address range is cacheable or not, whether it is writable or +* not , and whether it is accessible or not. A Low and High registers +* define each window while the minimum address range of each window is +* 1Mbyte. An address driven by the CPU, in addition to the address +* decoding and remapping process, is compared against the eight Access +* Protection Low/High registers , if an address matches one of the windows +* , the MV device checks the transaction type against the protection bits +* defined in CPU Access Protection register, to determine if the access is +* allowed. This function set a protection mode to one of the 8 possible +* regions. +* NOTE: +* The CPU address windows are restricted to a size of 2 power n and the +* start address must be aligned to the window size. For example, if using +* a 16 MB window, the start address bits [23:0] must be 0.The MV's +* internal registers space is not protected, even if the access protection +* windows contain this space. +* +* INPUT: +* region - selects which region to be configured. The values defined in +* gtMemory.h: +* +* - MEM_REGION0 +* - MEM_REGION1 +* - etc. +* +* memAccess - Allows or forbids access (read or write ) to the region. The +* values defined in gtMemory.h: +* +* - MEM_ACCESS_ALLOWED +* - MEM_ACCESS_FORBIDEN +* +* memWrite - CPU write protection to the region. The values defined in +* gtMemory.h: +* +* - MEM_WRITE_ALLOWED +* - MEM_WRITE_FORBIDEN +* +* cacheProtection - Defines whether caching the region is allowed or not. +* The values defined in gtMemory.h: +* +* - MEM_CACHE_ALLOWED +* - MEM_CACHE_FORBIDEN +* +* baseAddress - the region's base Address. +* regionSize - The region's size. This function will decrement the +* 'regionSize' parameter by one and then check if the size +* is valid. A valid size must be programed from LSB to MSB +* as sequence of ‘1’s followed by sequence of ‘0’s. +* To close a memory window simply set the size to 0. +* +* NOTE!!! +* The size must be in 64Kbyte granularity. +* The base address must be aligned to the size. +* +* OUTPUT: +* None. +* +* RETURN: +* False for invalid size, true otherwise. +* +*******************************************************************************/ +bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window, + MEMORY_ACCESS memAccess, + MEMORY_ACCESS_WRITE memWrite, + MEMORY_CACHE_PROTECT cacheProtection, + unsigned int baseAddress, unsigned int size) +{ + unsigned int dataForReg, temp, rShift; + + if (size == 0) { + GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window), + 0x0); + return true; + } + /* The base address must be aligned to the size. */ + if (baseAddress % size != 0) { + return false; + } + if (size >= MINIMUM_ACCESS_WIN_SIZE) { + baseAddress = ((baseAddress >> 16) & 0xfffff); + dataForReg = baseAddress | ((memAccess << 20) & BIT20) | + ((memWrite << 21) & BIT21) | ((cacheProtection << 22) + & BIT22) | BIT31; + GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window, + dataForReg); + size >>= 16; + /* Checking that the size is a sequence of '1' followed by a + sequence of '0' starting from LSB to MSB. */ + temp = size - 1; + for (rShift = 0; rShift < 16; rShift++) { + temp = temp >> rShift; + if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ + /* or the size is not valid */ + if (temp > 0x0) + return false; + else + break; + } + } + GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window), + size - 1); + return true; + } + return false; +} + +/******************************************************************************* +* gtMemoryDisableProtectRegion - Disable a protected window. +* +* DESCRIPTION: +* This function disable a protected window set by +* 'gtMemorySetProtectRegion' function. +* +* INPUT: +* window - one of the 4 windows ( defined in gtMemory.h ). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window) +{ + RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)), + BIT31); +} + +/******************************************************************************* +* memorySetPciRemapValue - Set a remap value to a PCI memory space target. +* +* DESCRIPTION: +* In addition to the address decoding mechanism, the CPU has an address +* remapping mechanism to be used by every PCI decoding window. Each PCI +* window can be remaped to a desired address target according to the remap +* value within the remap register. The address remapping is useful when a +* CPU address range must be reallocated to a different location on the +* PCI bus. Also, it enables CPU access to a PCI agent located above the +* 4Gbyte space. On system boot, each of the PCI memory spaces is maped to +* a defualt value (see CPU interface section in the MV spec for the +* default values). The remap mechanism does not always produce the desired +* address on the PCI bus because of the remap mechanism way of working +* (to fully understand why, please see the 'Address Remapping' section in +* the MV's spec). Therefor, this function sets a desired remap value to +* one of the PCI memory windows and return the effective address that +* should be used when exiting the PCI memory window. You should ALWAYS use +* the returned value by this function when remapping a PCI window and +* exiting it. If for example the base address of PCI0 memory 0 is +* 0x90000000, the size is 0x03ffffff and the remap value is 0x11000000, +* the function will return the value of 0x91000000 that MUST +* be used to exit this memory window in order to achive the deisred +* remapping. +* +* INPUT: +* memoryWindow - One of the PCI memory windows as defined in Memory.h +* remapValueLow - The low remap value. +* remapValueHigh - The high remap value. +* OUTPUT: +* None. +* +* RETURN: +* The effective base address to exit the PCI, or 0xffffffff if one of the +* parameters is erroneous or the effective base address is higher the top +* decode value. +* +*******************************************************************************/ +unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow, + unsigned int remapValueHigh, + unsigned int remapValueLow) +{ + unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0; + unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0; + unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh; + + /* Initializing the base and size variables of the PCI + memory windows */ + switch (memoryWindow) { + case PCI_0_IO: + pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR; + pciMemWindowSizeReg = PCI_0_IO_SIZE; + remapRegLow = PCI_0_IO_ADDR_REMAP; + remapRegHigh = PCI_0_IO_ADDR_REMAP; + break; + case PCI_0_MEM0: + pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR; + pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE; + remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP; + remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP; + break; + case PCI_0_MEM1: + pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR; + pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE; + remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP; + remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP; + break; + case PCI_0_MEM2: + pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR; + pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE; + remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP; + remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP; + break; + case PCI_0_MEM3: + pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR; + pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE; + remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP; + remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP; + break; +#ifdef INCLUDE_PCI_1 + case PCI_1_IO: + pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR; + pciMemWindowSizeReg = PCI_1_IO_SIZE; + remapRegLow = PCI_1_IO_ADDR_REMAP; + remapRegHigh = PCI_1_IO_ADDR_REMAP; + break; + case PCI_1_MEM0: + pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR; + pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE; + remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP; + remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP; + break; + case PCI_1_MEM1: + pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR; + pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE; + remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP; + remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP; + break; + case PCI_1_MEM2: + pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR; + pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE; + remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP; + remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP; + break; + case PCI_1_MEM3: + pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR; + pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE; + remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP; + remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP; + break; +#endif /* INCLUDE_PCI_1 */ + default: + /* Retrun an invalid effective base address */ + return 0xffffffff; + } + /* Writing the remap value to the remap regisers */ + GT_REG_WRITE (remapRegHigh, remapValueHigh); + GT_REG_WRITE (remapRegLow, remapValueLow >> 16); + /* Reading the values from the base address and size registers */ + baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff; + windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff; + /* Start calculating the effective Base Address */ + effectiveBaseAddress = baseAddrValue << 16; + /* The effective base address will be combined from the chopped (if any) + remap value (according to the size value and remap mechanism) and the + window's base address */ + effectiveBaseAddress |= + (((windowSizeValue << 16) | 0xffff) & remapValueLow); + /* If the effectiveBaseAddress exceed the window boundaries return an + invalid value. */ + if (effectiveBaseAddress > + ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff))) + return 0xffffffff; + return effectiveBaseAddress; +} + +/******************************************************************** +* memorySetRegionSnoopMode - This function modifys one of the 4 regions which +* supports Cache Coherency. +* +* +* Inputs: SNOOP_REGION region - One of the four regions. +* SNOOP_TYPE snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* unsigned int baseAddress - Base Address of this region. +* unsigned int topAddress - Top Address of this region. +* Returns: false if one of the parameters is wrong and true else +*********************************************************************/ +/* evb6260 code */ +#if 0 +bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, + MEMORY_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int snoopXbaseAddress; + unsigned int snoopXtopAddress; + unsigned int data; + unsigned int snoopHigh = baseAddress + regionLength; + + if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) ) + return false; + snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region; + snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region; + if(regionLength == 0) /* closing the region */ + { + GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); + GT_REG_WRITE(snoopXtopAddress,0); + return true; + } + baseAddress = baseAddress & 0xffff0000; + data = (baseAddress >> 16) | snoopType << 16; + GT_REG_WRITE(snoopXbaseAddress,data); + snoopHigh = (snoopHigh & 0xfff00000) >> 20; + GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1); + return true; +} +#endif + +/******************************************************************** +* memoryRemapAddress - This fubction used for address remapping. +* +* +* Inputs: regOffset: remap register +* remapValue : +* Returns: false if one of the parameters is erroneous,true otherwise. +* +* Not needed function To_do !!!! +*********************************************************************/ +bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue) +{ + unsigned int valueForReg; + + valueForReg = (remapValue & 0xfff00000) >> 20; + GT_REG_WRITE (remapReg, valueForReg); + return true; +} + +/******************************************************************************* +* memoryGetDeviceParam - Extract the device parameters from the device bank +* parameters register. +* +* DESCRIPTION: +* To allow interfacing with very slow devices and fast synchronous SRAMs, +* each device can be programed to different timing parameters. Each bank +* has its own parameters register. Bank width can be programmed to 8, 16, +* or 32-bits. Bank timing parameters can be programmed to support +* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O +* Controllers). The MV allows you to set timing parameters and width for +* each device through parameters register . +* This function extracts the parameters described from the Device Bank +* parameters register and fills the given 'deviceParam' (defined in +* gtMemory.h) structure with the read data. +* +* INPUT: +* deviceParam - pointer to a structure DEVICE_PARAM (defined in +* Memory.h).For details about each structure field please +* see the device timing parameter section in the MV +* datasheet. +* deviceNum - Select on of the five device banks (defined in +* Memory.h) : +* +* - DEVICE0 +* - DEVICE1 +* - DEVICE2 +* - etc. +* +* OUTPUT: +* None. +* +* RETURN: +* false if one of the parameters is erroneous,true otherwise. +* +*******************************************************************************/ +/******************************************************************** +* memoryGetDeviceParam - This function used for getting device parameters from +* DEVICE BANK PARAMETERS REGISTER +* +* +* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK +* PARAMETERS REGISTER +* - deviceNum : number of device +* Returns: false if one of the parameters is erroneous,true otherwise. +*********************************************************************/ + +bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum) +{ + unsigned int valueOfReg; + unsigned int calcData; + + if (deviceNum > 4) + return false; + GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg); + calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19); + deviceParam->turnOff = calcData; /* Turn Off */ + + calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19); + deviceParam->acc2First = calcData; /* Access To First */ + + calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20); + deviceParam->acc2Next = calcData; /* Access To Next */ + + calcData = + ((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22); + deviceParam->ale2Wr = calcData; /* Ale To Write */ + + calcData = ((0x1c000 & valueOfReg) >> 14) + + ((BIT26 & valueOfReg) >> 23); + deviceParam->wrLow = calcData; /* Write Active */ + + calcData = ((0xe0000 & valueOfReg) >> 17) + + ((BIT27 & valueOfReg) >> 24); + deviceParam->wrHigh = calcData; /* Write High */ + + calcData = ((0x300000 & valueOfReg) >> 20); + deviceParam->deviceWidth = (BIT0 << calcData); /* In bytes */ + calcData = ((0x30000000 & valueOfReg) >> 28); + deviceParam->badrSkew = calcData; /* Cycles gap between BAdr + toggle to read data sample. */ + calcData = ((0x40000000 & valueOfReg) >> 30); + deviceParam->DPEn = calcData; /* Data Parity enable */ + return true; +} + +/******************************************************************************* +* memorySetDeviceParam - Set new parameters for a device. +* +* +* DESCRIPTION: +* To allow interfacing with very slow devices and fast synchronous SRAMs, +* each device can be programed to different timing parameters. Each bank +* has its own parameters register. Bank width can be programmed to 8, 16, +* or 32-bits. Bank timing parameters can be programmed to support +* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O +* Controllers). The MV allows you to set timing parameters and width for +* each device through parameters register. This function set new +* parameters to a device Bank from the delivered structure 'deviceParam' +* (defined in gtMemory.h). The structure must be initialized with data +* prior to the use of these function. +* +* INPUT: +* deviceParam - pointer to a structure DEVICE_PARAM (defined in +* Memory.h).For details about each structure field please +* see the device timing parameter section in the MV +* datasheet. +* deviceNum - Select on of the five device banks (defined in +* Memory.h) : +* +* - DEVICE0 +* - DEVICE1 +* - DEVICE2 +* - etc. +* +* OUTPUT: +* None. +* +* RETURN: +* false if one of the parameters is erroneous,true otherwise. +* +*******************************************************************************/ +/******************************************************************** +* memorySetDeviceParam - This function used for setting device parameters to +* DEVICE BANK PARAMETERS REGISTER +* +* +* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK +* PARAMETERS REGISTER +* - deviceNum : number of device +* Returns: false if one of the parameters is erroneous,true otherwise. +*********************************************************************/ +bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum) +{ + unsigned int valueForReg; + + if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) || + (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) || + (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) || + (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) { + return false; + } + valueForReg = (((deviceParam->turnOff) & 0x7) | + (((deviceParam->turnOff) & 0x8) << 19) | + (((deviceParam->acc2First) & 0xf) << 3) | + (((deviceParam->acc2First) & 0x10) << 19) | + (((deviceParam->acc2Next) & 0xf) << 7) | + (((deviceParam->acc2Next) & 0x10) << 20) | + (((deviceParam->ale2Wr) & 0x7) << 11) | + (((deviceParam->ale2Wr) & 0xf) << 22) | + (((deviceParam->wrLow) & 0x7) << 14) | + (((deviceParam->wrLow) & 0xf) << 23) | + (((deviceParam->wrHigh) & 0x7) << 17) | + (((deviceParam->wrHigh) & 0xf) << 24) | + (((deviceParam->badrSkew) & 0x3) << 28) | + (((deviceParam->DPEn) & 0x1) << 30)); + + /* insert the device width: */ + switch (deviceParam->deviceWidth) { + case 1: + valueForReg = valueForReg | _8BIT; + break; + case 2: + valueForReg = valueForReg | _16BIT; + break; + case 4: + valueForReg = valueForReg | _32BIT; + break; + default: + valueForReg = valueForReg | _8BIT; + break; + } + GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg); + return true; +} + +/******************************************************************************* +* MemoryDisableWindow - Disable a memory space by the disable bit. +* DESCRIPTION: +* This function disables one of the 21 availiable windows dedicated for +* the CPU decoding mechanism. Its possible to combine several windows with +* the OR command. +* INPUT: +* window - One or more of the memory windows (defined in gtMemory.h). +* OUTPUT: +* None. +* RETURN: +* None. +*******************************************************************************/ +void MemoryDisableWindow (MEMORY_WINDOW window) +{ + SET_REG_BITS (BASE_ADDR_ENABLE, window); +} + +/******************************************************************************* +* MemoryEnableWindow - Enable a memory space that was disabled by +* 'MemoryDisableWindow'. +* DESCRIPTION: +* This function enables one of the 21 availiable windows dedicated for the +* CPU decoding mechanism. Its possible to combine several windows with the +* OR command. +* INPUT: +* window - One or more of the memory windows (defined in gtMemory.h). +* OUTPUT: +* None. +* RETURN: +* None. +*******************************************************************************/ +void MemoryEnableWindow (MEMORY_WINDOW window) +{ + RESET_REG_BITS (BASE_ADDR_ENABLE, window); +} + +/******************************************************************************* +* MemoryGetMemWindowStatus - This function check whether the memory window is +* disabled or not. +* DESCRIPTION: +* This function checks if the given memory window is closed . +* INPUT: +* window - One or more of the memory windows (defined in gtMemory.h). +* OUTPUT: +* None. +* RETURN: +* True for a closed window, false otherwise . +*******************************************************************************/ +MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window) +{ + if (GTREGREAD (BASE_ADDR_ENABLE) & window) + return MEM_WINDOW_DISABLED; + return MEM_WINDOW_ENABLED; +} diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S new file mode 100644 index 0000000..41c3a95 --- /dev/null +++ b/board/Marvell/common/misc.S @@ -0,0 +1,235 @@ +#include +#include <74xx_7xx.h> +#include "version.h" + +#include +#include + +#include +#include + +#include "../include/mv_gen_reg.h" + +#ifdef CONFIG_ECC + /* Galileo specific asm code for initializing ECC */ + .globl board_relocate_rom +board_relocate_rom: + mflr r7 + /* update the location of the GT registers */ + lis r11, CFG_GT_REGS@h + /* if we're using ECC, we must use the DMA engine to copy ourselves */ + bl start_idma_transfer_0 + bl wait_for_idma_0 + bl stop_idma_engine_0 + + mtlr r7 + blr + + .globl board_init_ecc +board_init_ecc: + mflr r7 + /* NOTE: r10 still contains the location we've been relocated to + * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + + /* now that we're running from ram, init the rest of main memory + * for ECC use */ + lis r8, CFG_MONITOR_LEN@h + ori r8, r8, CFG_MONITOR_LEN@l + + divw r3, r10, r8 + + /* set up the counter, and init the starting address */ + mtctr r3 + li r12, 0 + + /* bytes per transfer */ + mr r5, r8 +about_to_init_ecc: +1: mr r3, r12 + mr r4, r12 + bl start_idma_transfer_0 + bl wait_for_idma_0 + bl stop_idma_engine_0 + add r12, r12, r8 + bdnz 1b + + mtlr r7 + blr + + /* r3: dest addr + * r4: source addr + * r5: byte count + * r11: gt regbase + * trashes: r6, r5 + */ +start_idma_transfer_0: + /* set the byte count, including the OWN bit */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_BYTE_COUNT + stwbrx r5, 0, (r6) + + /* set the source address */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS + stwbrx r4, 0, (r6) + + /* set the dest address */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS + stwbrx r3, 0, (r6) + + /* set the next record pointer */ + li r5, 0 + mr r6, r11 + ori r6, r6, CHANNEL0NEXT_RECORD_POINTER + stwbrx r5, 0, (r6) + + /* set the low control register */ + /* bit 9 is NON chained mode, bit 31 is new style descriptors. + bit 12 is channel enable */ + ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) + /* 15 shifted by 16 (oris) == bit 31 */ + oris r5, r5, (1 << 15) + mr r6, r11 + ori r6, r6, CHANNEL0CONTROL + stwbrx r5, 0, (r6) + + blr + + /* this waits for the bytecount to return to zero, indicating + * that the trasfer is complete */ +wait_for_idma_0: + mr r5, r11 + lis r6, 0xff + ori r6, r6, 0xffff + ori r5, r5, CHANNEL0_DMA_BYTE_COUNT +1: lwbrx r4, 0, (r5) + and. r4, r4, r6 + bne 1b + + blr + + /* this turns off channel 0 of the idma engine */ +stop_idma_engine_0: + /* shut off the DMA engine */ + li r5, 0 + mr r6, r11 + ori r6, r6, CHANNEL0CONTROL + stwbrx r5, 0, (r6) + + blr +#endif + +#ifdef CFG_BOARD_ASM_INIT + /* NOTE: trashes r3-r7 */ + .globl board_asm_init +board_asm_init: + /* just move the GT registers to where they belong */ + lis r3, CFG_DFL_GT_REGS@h + ori r3, r3, CFG_DFL_GT_REGS@l + lis r4, CFG_GT_REGS@h + ori r4, r4, CFG_GT_REGS@l + li r5, INTERNAL_SPACE_DECODE + + /* test to see if we've already moved */ + lwbrx r6, r5, r4 + andi. r6, r6, 0xffff + /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ +/* rlwinm r7, r4, 8, 16, 31 + rlwinm r7, r4, 12, 16, 31 */ /* original */ + rlwinm r7, r4, 16, 16, 31 + /* -----------------------------------------------------*/ + cmp cr0, r7, r6 + beqlr + + /* nope, have to move the registers */ + lwbrx r6, r5, r3 + andis. r6, r6, 0xffff + or r6, r6, r7 + stwbrx r6, r5, r3 + + /* now, poll for the change */ +1: lwbrx r7, r5, r4 + cmp cr0, r7, r6 + bne 1b + + /* done! */ + blr +#endif + +/* For use of the debug LEDs */ + .global led_on0_relocated +led_on0_relocated: + xor r21, r21, r21 + xor r18, r18, r18 + lis r18, 0xFC80 + ori r18, r18, 0x8000 + stw r21, 0x0(r18) +/* stw r18, 0x0(r18) */ + sync + blr + + .global led_off0_relocated +led_off0_relocated: + xor r21, r21, r21 + xor r18, r18, r18 + lis r18, 0xFC81 + ori r18, r18, 0x4000 + stw r21, 0x0(r18) +/* stw r18, 0x0(r18) */ + sync + blr + + .global led_on0 +led_on0: + xor r18, r18, r18 + lis r18, 0x1c80 + ori r18, r18, 0x8000 + stw r18, 0x0(r18) + sync + blr + + .global led_off0 +led_off0: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0x4000 + stw r18, 0x0(r18) + sync + blr + + .global led_on1 +led_on1: + xor r18, r18, r18 + lis r18, 0x1c80 + ori r18, r18, 0xc000 + stw r18, 0x0(r18) + sync + blr + + .global led_off1 +led_off1: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0x8000 + stw r18, 0x0(r18) + sync + blr + + .global led_on2 +led_on2: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0x0000 + stw r18, 0x0(r18) + sync + blr + + .global led_off2 +led_off2: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0xc000 + stw r18, 0x0(r18) + sync + blr diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c new file mode 100644 index 0000000..475445b --- /dev/null +++ b/board/Marvell/common/ns16550.c @@ -0,0 +1,66 @@ +/* + * COM1 NS16550 support + * originally from linux source (arch/ppc/boot/ns16550.c) + * modified to use CFG_ISA_MEM and new defines + * + * further modified by Josh Huber to support + * the DUART on the Galileo Eval board. (db64360) + */ + +#include +#include "ns16550.h" + +#ifdef ZUMA_NTL +/* no 16550 device */ +#else +const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0), + (NS16550_t) (CFG_DUART_IO + 0x20) +}; + +volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) +{ + volatile struct NS16550 *com_port; + + com_port = (struct NS16550 *) COM_PORTS[chan]; + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; /* Access baud rate */ + com_port->dll = baud_divisor & 0xff; /* 9600 baud */ + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ + com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ + + /* Clear & enable FIFOs */ + com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; + return (com_port); +} + +void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) +{ + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; /* Access baud rate */ + com_port->dll = baud_divisor & 0xff; /* 9600 baud */ + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ + com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ + + /* Clear & enable FIFOs */ + com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; +} + +void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c) +{ + while ((com_port->lsr & LSR_THRE) == 0); + com_port->thr = c; +} + +unsigned char NS16550_getc (volatile struct NS16550 *com_port) +{ + while ((com_port->lsr & LSR_DR) == 0); + return (com_port->rbr); +} + +int NS16550_tstc (volatile struct NS16550 *com_port) +{ + return ((com_port->lsr & LSR_DR) != 0); +} +#endif diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h new file mode 100644 index 0000000..f2ed2ab --- /dev/null +++ b/board/Marvell/common/ns16550.h @@ -0,0 +1,102 @@ +/* + * NS16550 Serial Port + * originally from linux source (arch/ppc/boot/ns16550.h) + * modified slightly to + * have addresses as offsets from CFG_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + * + * further modified to support the DUART in the Galileo eval board + * modifications (c) Josh Huber , Mission Critical Linux, Inc. + */ + +#ifndef __NS16550_H__ +#define __NS16550_H__ + +/* the padding is necessary because on the galileo board the UART is + wired in with the 3 address lines shifted over by 2 bits */ +struct NS16550 +{ + unsigned char rbr; /* 0 = 0-3*/ + int pad1:24; + + unsigned char ier; /* 1 = 4-7*/ + int pad2:24; + + unsigned char fcr; /* 2 = 8-b*/ + int pad3:24; + + unsigned char lcr; /* 3 = c-f*/ + int pad4:24; + + unsigned char mcr; /* 4 = 10-13*/ + int pad5:24; + + unsigned char lsr; /* 5 = 14-17*/ + int pad6:24; + + unsigned char msr; /* 6 =18-1b*/ + int pad7:24; + + unsigned char scr; /* 7 =1c-1f*/ + int pad8:24; +} __attribute__ ((packed)); + +/* aliases */ +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +#define FCR_FIFO_EN 0x01 /*fifo enable*/ +#define FCR_RXSR 0x02 /*reciever soft reset*/ +#define FCR_TXSR 0x04 /*transmitter soft reset*/ + + +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_DMA_EN 0x04 +#define MCR_TX_DFR 0x08 + + +#define LCR_WLS_MSK 0x03 /* character length slect mask*/ +#define LCR_WLS_5 0x00 /* 5 bit character length */ +#define LCR_WLS_6 0x01 /* 6 bit character length */ +#define LCR_WLS_7 0x02 /* 7 bit character length */ +#define LCR_WLS_8 0x03 /* 8 bit character length */ +#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define LCR_PEN 0x08 /* Parity eneble*/ +#define LCR_EPS 0x10 /* Even Parity Select*/ +#define LCR_STKP 0x20 /* Stick Parity*/ +#define LCR_SBRK 0x40 /* Set Break*/ +#define LCR_BKSE 0x80 /* Bank select enable*/ + +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +/* useful defaults for LCR*/ +#define LCR_8N1 0x03 + + +#define COM1 0x03F8 +#define COM2 0x02F8 + +volatile struct NS16550 * NS16550_init(int chan, int baud_divisor); +void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c); +unsigned char NS16550_getc(volatile struct NS16550 *com_port); +int NS16550_tstc(volatile struct NS16550 *com_port); +void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor); + +typedef struct NS16550 *NS16550_t; + +extern const NS16550_t COM_PORTS[]; + +#endif diff --git a/board/Marvell/common/ppc_error_no.h b/board/Marvell/common/ppc_error_no.h new file mode 100644 index 0000000..53687c8 --- /dev/null +++ b/board/Marvell/common/ppc_error_no.h @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus + */ +#ifndef _MV_PPC_ERRNO_H +#define _MV_PPC_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ +#define EDEADLOCK 58 /* File locking deadlock error */ +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +/* Should never be seen by user programs */ +#define ERESTARTSYS 512 +#define ERESTARTNOINTR 513 +#define ERESTARTNOHAND 514 /* restart if no handler.. */ +#define ENOIOCTLCMD 515 /* No ioctl command */ + +#define _LAST_ERRNO 515 + +#endif diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c new file mode 100644 index 0000000..9d0d213 --- /dev/null +++ b/board/Marvell/common/serial.c @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * modified for marvell db64360 eval board by + * Ingo Assmus + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * serial.c - serial support for the gal ev board + */ + +/* supports both the 16650 duart and the MPSC */ + +#include +#include +#include "../include/memory.h" +#include "serial.h" + +#ifdef CONFIG_DB64360 +#include "../db64360/mpsc.h" +#endif + +#ifdef CONFIG_DB64460 +#include "../db64460/mpsc.h" +#endif + +#include "ns16550.h" + +#ifdef CONFIG_MPSC + + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) + int clock_divisor = 230400 / gd->baudrate; +#endif + + mpsc_init (gd->baudrate); + + /* init the DUART chans so that KGDB in the kernel can use them */ +#ifdef CFG_INIT_CHAN1 + NS16550_reinit (COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + NS16550_reinit (COM_PORTS[1], clock_divisor); +#endif + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') + mpsc_putchar ('\r'); + + mpsc_putchar (c); +} + +int serial_getc (void) +{ + return mpsc_getchar (); +} + +int serial_tstc (void) +{ + return mpsc_test_char (); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); +} + +#else /* ! CONFIG_MPSC */ + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = 230400 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + (void) NS16550_init (0, clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + (void) NS16550_init (1, clock_divisor); +#endif + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') + NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); + + NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); +} + +int serial_getc (void) +{ + return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); +} + +int serial_tstc (void) +{ + return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = 230400 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + NS16550_reinit (COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + NS16550_reinit (COM_PORTS[1], clock_divisor); +#endif +} + +#endif /* CONFIG_MPSC */ + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +void kgdb_serial_init (void) +{ +} + +void putDebugChar (int c) +{ + serial_putc (c); +} + +void putDebugStr (const char *str) +{ + serial_puts (str); +} + +int getDebugChar (void) +{ + return serial_getc (); +} + +void kgdb_interruptible (int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ diff --git a/board/Marvell/common/serial.h b/board/Marvell/common/serial.h new file mode 100644 index 0000000..c7fc8c1 --- /dev/null +++ b/board/Marvell/common/serial.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * modified for marvell db64360 eval board by + * Ingo Assmus + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* serial.h - mostly useful for DUART serial_init in serial.c */ + +#ifndef __SERIAL_H__ +#define __SERIAL_H__ + +#if 0 + +#define B230400 1 +#define B115200 2 +#define B57600 4 +#define B38400 82 +#define B19200 163 +#define B9600 24 +#define B4800 651 +#define B2400 1302 +#define B1200 2604 +#define B600 5208 +#define B300 10417 +#define B150 20833 +#define B110 28409 +#define BDEFAULT B115200 + + /* this stuff is important to initialize + the DUART channels */ + +#define Scale 0x01L /* distance between port addresses */ +#define COM1 0x000003f8 /* Keyboard */ +#define COM2 0x000002f8 /* Host */ + + +/* Port Definitions relative to base COM port addresses */ +#define DataIn (0x00*Scale) /* data input port */ +#define DataOut (0x00*Scale) /* data output port */ +#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ +#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ +#define Ier (0x01*Scale) /* interrupt enable register */ +#define Iir (0x02*Scale) /* interrupt identification register */ +#define Lcr (0x03*Scale) /* line control register */ +#define Mcr (0x04*Scale) /* modem control register */ +#define Lsr (0x05*Scale) /* line status register */ +#define Msr (0x06*Scale) /* modem status register */ + +/* Bit Definitions for above ports */ +#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ +#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ + +#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ +#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ +#define McrDflt (McrRts|McrDtr) + +#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ + /* b6: transmitter empty */ +#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ + +#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ +#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ +#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ + +#define IerRda 0xf /* b0: Enable received data available interrupt */ + +#endif + +#endif /* __SERIAL_H__ */ diff --git a/board/Marvell/db64360/64360.h b/board/Marvell/db64360/64360.h new file mode 100644 index 0000000..a65e23b --- /dev/null +++ b/board/Marvell/db64360/64360.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * main board support/init for the Galileo Eval board DB64360. + */ + +#ifndef __64360_H__ +#define __64360_H__ + +/* CPU Configuration bits */ +#define CPU_CONF_ADDR_MISS_EN (1 << 8) +#define CPU_CONF_SINGLE_CPU (1 << 11) +#define CPU_CONF_ENDIANESS (1 << 12) +#define CPU_CONF_PIPELINE (1 << 13) +#define CPU_CONF_STOP_RETRY (1 << 17) +#define CPU_CONF_MULTI_DECODE (1 << 18) +#define CPU_CONF_DP_VALID (1 << 19) +#define CPU_CONF_PERR_PROP (1 << 22) +#define CPU_CONF_AACK_DELAY_2 (1 << 25) +#define CPU_CONF_AP_VALID (1 << 26) +#define CPU_CONF_REMAP_WR_DIS (1 << 27) + +/* CPU Master Control bits */ +#define CPU_MAST_CTL_ARB_EN (1 << 8) +#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) +#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) +#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) +#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) +#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) + +#endif /* __64360_H__ */ diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile new file mode 100644 index 0000000..768ccdd --- /dev/null +++ b/board/Marvell/db64360/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001 +# Josh Huber , Mission Critical Linux, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +SOBJS = ../common/misc.o + +OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ + mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ + sdram_init.o ../common/intel_flash.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/Marvell/db64360/config.mk b/board/Marvell/db64360/config.mk new file mode 100644 index 0000000..0e42b48 --- /dev/null +++ b/board/Marvell/db64360/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Josh Huber , Mission Critical Linux, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EVB64360 boards +# + +TEXT_BASE = 0xfff00000 diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c new file mode 100644 index 0000000..a2ab2d7 --- /dev/null +++ b/board/Marvell/db64360/db64360.c @@ -0,0 +1,936 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com + */ + +/* + * db64360.c - main board support/init for the Galileo Eval board. + */ + +#include +#include <74xx_7xx.h> +#include "../include/memory.h" +#include "../include/pci.h" +#include "../include/mv_gen_reg.h" +#include + +#include "eth.h" +#include "mpsc.h" +#include "i2c.h" +#include "64360.h" +#include "mv_regs.h" + +#undef DEBUG +/*#define DEBUG */ + +#define MAP_PCI + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +extern void flush_data_cache (void); +extern void invalidate_l1_instruction_cache (void); + +/* ------------------------------------------------------------------------- */ + +/* this is the current GT register space location */ +/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ + +/* Unfortunately, we cant change it while we are in flash, so we initialize it + * to the "final" value. This means that any debug_led calls before + * board_early_init_f wont work right (like in cpu_init_f). + * See also my_remap_gt_regs below. (NTL) + */ + +void board_prebootm_init (void); +unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +int display_mem_map (void); + +/* ------------------------------------------------------------------------- */ + +/* + * This is a version of the GT register space remapping function that + * doesn't touch globals (meaning, it's ok to run from flash.) + * + * Unfortunately, this has the side effect that a writable + * INTERNAL_REG_BASE_ADDR is impossible. Oh well. + */ + +void my_remap_gt_regs (u32 cur_loc, u32 new_loc) +{ + u32 temp; + + /* check and see if it's already moved */ + +/* original ppcboot 1.1.6 source + + temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 20) + return; + + temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 20); + + out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); + + while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); +original ppcboot 1.1.6 source end */ + + temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 16) + return; + + temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 16); + + out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); + + while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); +} + +#ifdef CONFIG_PCI + +static void gt_pci_config (void) +{ + unsigned int stat; + unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ + + /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's + * config registers by writing ones to the bus and device. + * We then update the Virtual register with the correct value for the bus and device. + */ + if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ + GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); + + GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); + + GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); + GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, + (stat & 0xffff0000) | CFG_PCI_IDSEL); + + } + if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ + GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); + GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); + + GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); + GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, + (stat & 0xffff0000) | CFG_PCI_IDSEL); + } + + /* Enable master */ + PCI_MASTER_ENABLE (0, SELF); + PCI_MASTER_ENABLE (1, SELF); + + /* Enable PCI0/1 Mem0 and IO 0 disable all others */ + GT_REG_READ (BASE_ADDR_ENABLE, &stat); + stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 + << + 18); + stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); + GT_REG_WRITE (BASE_ADDR_ENABLE, stat); + + /* ronen- add write to pci remap registers for 64460. + in 64360 when writing to pci base go and overide remap automaticaly, + in 64460 it doesn't */ + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + + /* PCI interface settings */ + /* Timeout set to retry forever */ + GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); + GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); + + /* ronen - enable only CS0 and Internal reg!! */ + GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); + GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); + +/*ronen update the pci internal registers base address.*/ +#ifdef MAP_PCI + for (stat = 0; stat <= PCI_HOST1; stat++) + pciWriteConfigReg (stat, + PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, + SELF, CFG_GT_REGS); +#endif + +} +#endif + +/* Setup CPU interface paramaters */ +static void gt_cpu_config (void) +{ + cpu_t cpu = get_cpu_type (); + ulong tmp; + + /* cpu configuration register */ + tmp = GTREGREAD (CPU_CONFIGURATION); + + /* set the SINGLE_CPU bit see MV64360 P.399 */ +#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ + tmp |= CPU_CONF_SINGLE_CPU; +#endif + + tmp &= ~CPU_CONF_AACK_DELAY_2; + + tmp |= CPU_CONF_DP_VALID; + tmp |= CPU_CONF_AP_VALID; + + tmp |= CPU_CONF_PIPELINE; + + GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ + + /* CPU master control register */ + tmp = GTREGREAD (CPU_MASTER_CONTROL); + + tmp |= CPU_MAST_CTL_ARB_EN; + + if ((cpu == CPU_7400) || + (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { + + tmp |= CPU_MAST_CTL_CLEAN_BLK; + tmp |= CPU_MAST_CTL_FLUSH_BLK; + + } else { + /* cleanblock must be cleared for CPUs + * that do not support this command (603e, 750) + * see Res#1 */ + tmp &= ~CPU_MAST_CTL_CLEAN_BLK; + tmp &= ~CPU_MAST_CTL_FLUSH_BLK; + } + GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); +} + +/* + * board_early_init_f. + * + * set up gal. device mappings, etc. + */ +int board_early_init_f (void) +{ + uchar sram_boot = 0; + + /* + * set up the GT the way the kernel wants it + * the call to move the GT register space will obviously + * fail if it has already been done, but we're going to assume + * that if it's not at the power-on location, it's where we put + * it last time. (huber) + */ + + my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + + /* No PCI in first release of Port To_do: enable it. */ +#ifdef CONFIG_PCI + gt_pci_config (); +#endif + /* mask all external interrupt sources */ + GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); + /* new in MV6436x */ + GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); + /* --------------------- */ + GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); + GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); + /* does not exist in MV6436x + GT_REG_WRITE(CPU_INT_0_MASK, 0); + GT_REG_WRITE(CPU_INT_1_MASK, 0); + GT_REG_WRITE(CPU_INT_2_MASK, 0); + GT_REG_WRITE(CPU_INT_3_MASK, 0); + --------------------- */ + + + /* ----- DEVICE BUS SETTINGS ------ */ + + /* + * EVB + * 0 - SRAM ???? + * 1 - RTC ???? + * 2 - UART ???? + * 3 - Flash checked 32Bit Intel Strata + * boot - BootCS checked 8Bit 29LV040B + * + * Zuma + * 0 - Flash + * boot - BootCS + */ + + /* + * the dual 7450 module requires burst access to the boot + * device, so the serial rom copies the boot device to the + * on-board sram on the eval board, and updates the correct + * registers to boot from the sram. (device0) + */ + if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) + sram_boot = 1; + if (!sram_boot) + memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + + memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + + + /* configure device timing */ +#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */ + if (!sram_boot) + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); +#endif + +#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */ + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#endif +#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */ + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#endif + +#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ + /* detect if we are booting from the 32 bit flash */ + if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { + /* 32 bit boot flash */ + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, + CFG_32BIT_BOOT_PAR); + } else { + /* 8 bit boot flash */ + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + } +#else + /* 8 bit boot flash only */ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +#endif + + + gt_cpu_config (); + + /* MPP setup */ + GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + + GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + DEBUG_LED0_ON (); + DEBUG_LED1_ON (); + DEBUG_LED2_ON (); + + return 0; +} + +/* various things to do after relocation */ + +int misc_init_r () +{ + icache_enable (); +#ifdef CFG_L2 + l2cache_enable (); +#endif +#ifdef CONFIG_MPSC + + mpsc_sdma_init (); + mpsc_init2 (); +#endif + +#if 0 + /* disable the dcache and MMU */ + dcache_lock (); +#endif + return 0; +} + +void after_reloc (ulong dest_addr, gd_t * gd) +{ + /* check to see if we booted from the sram. If so, move things + * back to the way they should be. (we're running from main + * memory at this point now */ + if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) { + memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M); + } + display_mem_map (); + /* now, jump to the main ppcboot board init code */ + board_init_r (gd, dest_addr); + /* NOTREACHED */ +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + * + * right now, assume borad type. (there is just one...after all) + */ + +int checkboard (void) +{ + int l_type = 0; + + printf ("BOARD: %s\n", CFG_BOARD_NAME); + return (l_type); +} + +/* utility functions */ +void debug_led (int led, int mode) +{ + volatile int *addr = 0; + int dummy; + + if (mode == 1) { + switch (led) { + case 0: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x08000); + break; + + case 1: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x0c000); + break; + + case 2: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x10000); + break; + } + } else if (mode == 0) { + switch (led) { + case 0: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x14000); + break; + + case 1: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x18000); + break; + + case 2: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x1c000); + break; + } + } + + dummy = *addr; +} + +int display_mem_map (void) +{ + int i, j; + unsigned int base, size, width; + + /* SDRAM */ + printf ("SD (DDR) RAM\n"); + for (i = 0; i <= BANK3; i++) { + base = memoryGetBankBaseAddress (i); + size = memoryGetBankSize (i); + if (size != 0) { + printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", + i, base, size >> 20); + } + } + + /* CPU's PCI windows */ + for (i = 0; i <= PCI_HOST1; i++) { + printf ("\nCPU's PCI %d windows\n", i); + base = pciGetSpaceBase (i, PCI_IO); + size = pciGetSpaceSize (i, PCI_IO); + printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, + size >> 20); + for (j = 0; + j <= + PCI_REGION0 + /*ronen currently only first PCI MEM is used 3 */ ; + j++) { + base = pciGetSpaceBase (i, j); + size = pciGetSpaceSize (i, j); + printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); + } + } + + /* Devices */ + printf ("\nDEVICES\n"); + for (i = 0; i <= DEVICE3; i++) { + base = memoryGetDeviceBaseAddress (i); + size = memoryGetDeviceSize (i); + width = memoryGetDeviceWidth (i) * 8; + printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); + if (i == 0) + printf ("\t- EXT SRAM (actual - 1M)\n"); + else if (i == 1) + printf ("\t- RTC\n"); + else if (i == 2) + printf ("\t- UART\n"); + else + printf ("\t- LARGE FLASH\n"); + } + + /* Bootrom */ + base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ + size = memoryGetDeviceSize (BOOT_DEVICE); + width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; + printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n", + base, size >> 20, width); + return (0); +} + +/* DRAM check routines copied from gw8260 */ + +#if defined (CFG_DRAM_TEST) + +/*********************************************************************/ +/* NAME: move64() - moves a double word (64-bit) */ +/* */ +/* DESCRIPTION: */ +/* this function performs a double word move from the data at */ +/* the source pointer to the location at the destination pointer. */ +/* */ +/* INPUTS: */ +/* unsigned long long *src - pointer to data to move */ +/* */ +/* OUTPUTS: */ +/* unsigned long long *dest - pointer to locate to move data */ +/* */ +/* RETURNS: */ +/* None */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* May cloober fr0. */ +/* */ +/*********************************************************************/ +static void move64 (unsigned long long *src, unsigned long long *dest) +{ + asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : : "fr0"); /* Clobbers fr0 */ + return; +} + + +#if defined (CFG_DRAM_TEST_DATA) + +unsigned long long pattern[] = { + 0xaaaaaaaaaaaaaaaaULL, + 0xccccccccccccccccULL, + 0xf0f0f0f0f0f0f0f0ULL, + 0xff00ff00ff00ff00ULL, + 0xffff0000ffff0000ULL, + 0xffffffff00000000ULL, + 0x00000000ffffffffULL, + 0x0000ffff0000ffffULL, + 0x00ff00ff00ff00ffULL, + 0x0f0f0f0f0f0f0f0fULL, + 0x3333333333333333ULL, + 0x5555555555555555ULL, +}; + +/*********************************************************************/ +/* NAME: mem_test_data() - test data lines for shorts and opens */ +/* */ +/* DESCRIPTION: */ +/* Tests data lines for shorts and opens by forcing adjacent data */ +/* to opposite states. Because the data lines could be routed in */ +/* an arbitrary manner the must ensure test patterns ensure that */ +/* every case is tested. By using the following series of binary */ +/* patterns every combination of adjacent bits is test regardless */ +/* of routing. */ +/* */ +/* ...101010101010101010101010 */ +/* ...110011001100110011001100 */ +/* ...111100001111000011110000 */ +/* ...111111110000000011111111 */ +/* */ +/* Carrying this out, gives us six hex patterns as follows: */ +/* */ +/* 0xaaaaaaaaaaaaaaaa */ +/* 0xcccccccccccccccc */ +/* 0xf0f0f0f0f0f0f0f0 */ +/* 0xff00ff00ff00ff00 */ +/* 0xffff0000ffff0000 */ +/* 0xffffffff00000000 */ +/* */ +/* The number test patterns will always be given by: */ +/* */ +/* log(base 2)(number data bits) = log2 (64) = 6 */ +/* */ +/* To test for short and opens to other signals on our boards. we */ +/* simply */ +/* test with the 1's complemnt of the paterns as well. */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* Assumes only one one SDRAM bank */ +/* */ +/*********************************************************************/ +int mem_test_data (void) +{ + unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long temp64 = 0; + int num_patterns = sizeof (pattern) / sizeof (pattern[0]); + int i; + unsigned int hi, lo; + + for (i = 0; i < num_patterns; i++) { + move64 (&(pattern[i]), pmem); + move64 (pmem, &temp64); + + /* hi = (temp64>>32) & 0xffffffff; */ + /* lo = temp64 & 0xffffffff; */ + /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ + + hi = (pattern[i] >> 32) & 0xffffffff; + lo = pattern[i] & 0xffffffff; + /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ + + if (temp64 != pattern[i]) { + printf ("\n Data Test Failed, pattern 0x%08x%08x", + hi, lo); + return 1; + } + } + + return 0; +} +#endif /* CFG_DRAM_TEST_DATA */ + +#if defined (CFG_DRAM_TEST_ADDRESS) +/*********************************************************************/ +/* NAME: mem_test_address() - test address lines */ +/* */ +/* DESCRIPTION: */ +/* This function performs a test to verify that each word im */ +/* memory is uniquly addressable. The test sequence is as follows: */ +/* */ +/* 1) write the address of each word to each word. */ +/* 2) verify that each location equals its address */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_address (void) +{ + volatile unsigned int *pmem = + (volatile unsigned int *) CFG_MEMTEST_START; + const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + unsigned int i; + + /* write address to each location */ + for (i = 0; i < size; i++) { + pmem[i] = i; + } + + /* verify each loaction */ + for (i = 0; i < size; i++) { + if (pmem[i] != i) { + printf ("\n Address Test Failed at 0x%x", i); + return 1; + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_ADDRESS */ + +#if defined (CFG_DRAM_TEST_WALK) +/*********************************************************************/ +/* NAME: mem_march() - memory march */ +/* */ +/* DESCRIPTION: */ +/* Marches up through memory. At each location verifies rmask if */ +/* read = 1. At each location write wmask if write = 1. Displays */ +/* failing address and pattern. */ +/* */ +/* INPUTS: */ +/* volatile unsigned long long * base - start address of test */ +/* unsigned int size - number of dwords(64-bit) to test */ +/* unsigned long long rmask - read verify mask */ +/* unsigned long long wmask - wrtie verify mask */ +/* short read - verifies rmask if read = 1 */ +/* short write - writes wmask if write = 1 */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_march (volatile unsigned long long *base, + unsigned int size, + unsigned long long rmask, + unsigned long long wmask, short read, short write) +{ + unsigned int i; + unsigned long long temp = 0; + unsigned int hitemp, lotemp, himask, lomask; + + for (i = 0; i < size; i++) { + if (read != 0) { + /* temp = base[i]; */ + move64 ((unsigned long long *) &(base[i]), &temp); + if (rmask != temp) { + hitemp = (temp >> 32) & 0xffffffff; + lotemp = temp & 0xffffffff; + himask = (rmask >> 32) & 0xffffffff; + lomask = rmask & 0xffffffff; + + printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); + return 1; + } + } + if (write != 0) { + /* base[i] = wmask; */ + move64 (&wmask, (unsigned long long *) &(base[i])); + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_WALK */ + +/*********************************************************************/ +/* NAME: mem_test_walk() - a simple walking ones test */ +/* */ +/* DESCRIPTION: */ +/* Performs a walking ones through entire physical memory. The */ +/* test uses as series of memory marches, mem_march(), to verify */ +/* and write the test patterns to memory. The test sequence is as */ +/* follows: */ +/* 1) march writing 0000...0001 */ +/* 2) march verifying 0000...0001 , writing 0000...0010 */ +/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ +/* the write mask equals 1000...0000 */ +/* 4) march verifying 1000...0000 */ +/* The test fails if any of the memory marches return a failure. */ +/* */ +/* OUTPUTS: */ +/* Displays which pass on the memory test is executing */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_walk (void) +{ + unsigned long long mask; + volatile unsigned long long *pmem = + (volatile unsigned long long *) CFG_MEMTEST_START; + const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + + unsigned int i; + + mask = 0x01; + + printf ("Initial Pass"); + mem_march (pmem, size, 0x0, 0x1, 0, 1); + + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + + for (i = 0; i < 63; i++) { + printf ("Pass %2d", i + 2); + if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { + /*printf("mask: 0x%x, pass: %d, ", mask, i); */ + return 1; + } + mask = mask << 1; + printf ("\b\b\b\b\b\b\b"); + } + + printf ("Last Pass"); + if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { + /* printf("mask: 0x%x", mask); */ + return 1; + } + printf ("\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b"); + + return 0; +} + +/*********************************************************************/ +/* NAME: testdram() - calls any enabled memory tests */ +/* */ +/* DESCRIPTION: */ +/* Runs memory tests if the environment test variables are set to */ +/* 'y'. */ +/* */ +/* INPUTS: */ +/* testdramdata - If set to 'y', data test is run. */ +/* testdramaddress - If set to 'y', address test is run. */ +/* testdramwalk - If set to 'y', walking ones test is run */ +/* */ +/* OUTPUTS: */ +/* None */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int testdram (void) +{ + char *s; + int rundata, runaddress, runwalk; + + s = getenv ("testdramdata"); + rundata = (s && (*s == 'y')) ? 1 : 0; + s = getenv ("testdramaddress"); + runaddress = (s && (*s == 'y')) ? 1 : 0; + s = getenv ("testdramwalk"); + runwalk = (s && (*s == 'y')) ? 1 : 0; + +/* rundata = 1; */ +/* runaddress = 0; */ +/* runwalk = 0; */ + + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + } +#ifdef CFG_DRAM_TEST_DATA + if (rundata == 1) { + printf ("Test DATA ... "); + if (mem_test_data () == 1) { + printf ("failed \n"); + return 1; + } else + printf ("ok \n"); + } +#endif +#ifdef CFG_DRAM_TEST_ADDRESS + if (runaddress == 1) { + printf ("Test ADDRESS ... "); + if (mem_test_address () == 1) { + printf ("failed \n"); + return 1; + } else + printf ("ok \n"); + } +#endif +#ifdef CFG_DRAM_TEST_WALK + if (runwalk == 1) { + printf ("Test WALKING ONEs ... "); + if (mem_test_walk () == 1) { + printf ("failed \n"); + return 1; + } else + printf ("ok \n"); + } +#endif + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf ("passed\n"); + } + return 0; + +} +#endif /* CFG_DRAM_TEST */ + +/* ronen - the below functions are used by the bootm function */ +/* - we map the base register to fbe00000 (same mapping as in the LSP) */ +/* - we turn off the RX gig dmas - to prevent the dma from overunning */ +/* the kernel data areas. */ +/* - we diable and invalidate the icache and dcache. */ +void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) +{ + u32 temp; + + temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 16) + return; + + temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 16); + + out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); + + while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | + new_loc | + (INTERNAL_SPACE_DECODE))))) + != temp); + +} + +void board_prebootm_init () +{ + +/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ + GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); + +/* Stop GigE Rx DMA engines */ + GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); + GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); +/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */ + +/* Relocate MV64360 internal regs */ + my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM); + + icache_disable (); + invalidate_l1_instruction_cache (); + flush_data_cache (); + dcache_disable (); +} diff --git a/board/Marvell/db64360/eth.h b/board/Marvell/db64360/eth.h new file mode 100644 index 0000000..aab32d2 --- /dev/null +++ b/board/Marvell/db64360/eth.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * eth.h - header file for the polled mode GT ethernet driver + */ + +#ifndef __EVB64360_ETH_H__ +#define __EVB64360_ETH_H__ + +#include +#include +#include +#include + + +int db64360_eth0_poll(void); +int db64360_eth0_transmit(unsigned int s, volatile char *p); +void db64360_eth0_disable(void); +bool network_start(bd_t *bis); + + +#endif /* __EVB64360_ETH_H__ */ diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c new file mode 100644 index 0000000..ccb3adc --- /dev/null +++ b/board/Marvell/db64360/mpsc.c @@ -0,0 +1,1019 @@ +/* + * (C) Copyright 2001 + * John Clemens , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * changes for Marvell DB64360 eval board 2003 by Ingo Assmus + * + ************************************************************************/ + +/* + * mpsc.c - driver for console over the MPSC. + */ + + +#include +#include +#include + +#include +#include "mpsc.h" + +#include "mv_regs.h" + +#include "../include/memory.h" + +/* Define this if you wish to use the MPSC as a register based UART. + * This will force the serial port to not use the SDMA engine at all. + */ +#undef CONFIG_MPSC_DEBUG_PORT + + +int (*mpsc_putchar) (char ch) = mpsc_putchar_early; +char (*mpsc_getchar) (void) = mpsc_getchar_debug; +int (*mpsc_test_char) (void) = mpsc_test_char_debug; + + +static volatile unsigned int *rx_desc_base = NULL; +static unsigned int rx_desc_index = 0; +static volatile unsigned int *tx_desc_base = NULL; +static unsigned int tx_desc_index = 0; + +/* local function declarations */ +static int galmpsc_connect (int channel, int connect); +static int galmpsc_route_rx_clock (int channel, int brg); +static int galmpsc_route_tx_clock (int channel, int brg); +static int galmpsc_write_config_regs (int mpsc, int mode); +static int galmpsc_config_channel_regs (int mpsc); +static int galmpsc_set_char_length (int mpsc, int value); +static int galmpsc_set_stop_bit_length (int mpsc, int value); +static int galmpsc_set_parity (int mpsc, int value); +static int galmpsc_enter_hunt (int mpsc); +static int galmpsc_set_brkcnt (int mpsc, int value); +static int galmpsc_set_tcschar (int mpsc, int value); +static int galmpsc_set_snoop (int mpsc, int value); +static int galmpsc_shutdown (int mpsc); + +static int galsdma_set_RFT (int channel); +static int galsdma_set_SFM (int channel); +static int galsdma_set_rxle (int channel); +static int galsdma_set_txle (int channel); +static int galsdma_set_burstsize (int channel, unsigned int value); +static int galsdma_set_RC (int channel, unsigned int value); + +static int galbrg_set_CDV (int channel, int value); +static int galbrg_enable (int channel); +static int galbrg_disable (int channel); +static int galbrg_set_clksrc (int channel, int value); +static int galbrg_set_CUV (int channel, int value); + +static void galsdma_enable_rx (void); +static int galsdma_set_mem_space (unsigned int memSpace, + unsigned int memSpaceTarget, + unsigned int memSpaceAttr, + unsigned int baseAddress, + unsigned int size); + + +#define SOFTWARE_CACHE_MANAGEMENT + +#ifdef SOFTWARE_CACHE_MANAGEMENT +#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} +#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} +#else +#define FLUSH_DCACHE(a,b) +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) +#define INVALIDATE_DCACHE(a,b) +#endif + +#ifdef CONFIG_MPSC_DEBUG_PORT +static void mpsc_debug_init (void) +{ + + volatile unsigned int temp; + + /* Clear the CFR (CHR4) */ + /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ + temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&". Assuming "= &" + +REG_GAP)); + temp &= 0xffffff00; + temp |= BIT29; + GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), + temp); + + /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ + temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); + temp |= (BIT12 | BIT15); + GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), + temp); + + /* Set int mask */ + temp = GTREGREAD (GALMPSC_0_INT_MASK); + temp |= BIT6; + GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); +} +#endif + +char mpsc_getchar_debug (void) +{ + volatile int temp; + volatile unsigned int cause; + + cause = GTREGREAD (GALMPSC_0_INT_CAUSE); + while ((cause & BIT6) == 0) { + cause = GTREGREAD (GALMPSC_0_INT_CAUSE); + } + + temp = GTREGREAD (GALMPSC_CHANNELREG_10 + + (CHANNEL * GALMPSC_REG_GAP)); + /* By writing 1's to the set bits, the register is cleared */ + GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), + temp); + GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); + return (temp >> 16) & 0xff; +} + +/* special function for running out of flash. doesn't modify any + * global variables [josh] */ +int mpsc_putchar_early (char ch) +{ + DECLARE_GLOBAL_DATA_PTR; + int mpsc = CHANNEL; + int temp = + GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + galmpsc_set_tcschar (mpsc, ch); + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), + temp | 0x200); + +#define MAGIC_FACTOR (10*1000000) + + udelay (MAGIC_FACTOR / gd->baudrate); + return 0; +} + +/* This is used after relocation, see serial.c and mpsc_init2 */ +static int mpsc_putchar_sdma (char ch) +{ + volatile unsigned int *p; + unsigned int temp; + + + /* align the descriptor */ + p = tx_desc_base; + memset ((void *) p, 0, 8 * sizeof (unsigned int)); + + /* fill one 64 bit buffer */ + /* word swap, pad with 0 */ + p[4] = 0; /* x */ + p[5] = (unsigned int) ch; /* x */ + + /* CHANGED completely according to GT64260A dox - NTL */ + p[0] = 0x00010001; /* 0 */ + p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ + p[2] = 0; /* 8 */ + p[3] = (unsigned int) &p[4]; /* c */ + +#if 0 + p[9] = DESC_FIRST | DESC_LAST; + p[10] = (unsigned int) &p[0]; + p[11] = (unsigned int) &p[12]; +#endif + + FLUSH_DCACHE (&p[0], &p[8]); + + GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), + (unsigned int) &p[0]); + GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), + (unsigned int) &p[0]); + + temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); + temp |= (TX_DEMAND | TX_STOP); + GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); + + INVALIDATE_DCACHE (&p[1], &p[2]); + + while (p[1] & DESC_OWNER_BIT) { + udelay (100); + INVALIDATE_DCACHE (&p[1], &p[2]); + } + return 0; +} + +char mpsc_getchar_sdma (void) +{ + static unsigned int done = 0; + volatile char ch; + unsigned int len = 0, idx = 0, temp; + + volatile unsigned int *p; + + + do { + p = &rx_desc_base[rx_desc_index * 8]; + + INVALIDATE_DCACHE (&p[0], &p[1]); + /* Wait for character */ + while (p[1] & DESC_OWNER_BIT) { + udelay (100); + INVALIDATE_DCACHE (&p[0], &p[1]); + } + + /* Handle error case */ + if (p[1] & (1 << 15)) { + printf ("oops, error: %08x\n", p[1]); + + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + + (CHANNEL * GALMPSC_REG_GAP)); + temp |= (1 << 23); + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + + (CHANNEL * GALMPSC_REG_GAP), temp); + + /* Can't poll on abort bit, so we just wait. */ + udelay (100); + + galsdma_enable_rx (); + } + + /* Number of bytes left in this descriptor */ + len = p[0] & 0xffff; + + if (len) { + /* Where to look */ + idx = 5; + if (done > 3) + idx = 4; + if (done > 7) + idx = 7; + if (done > 11) + idx = 6; + + INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); + ch = p[idx] & 0xff; + done++; + } + + if (done < len) { + /* this descriptor has more bytes still + * shift down the char we just read, and leave the + * buffer in place for the next time around + */ + p[idx] = p[idx] >> 8; + FLUSH_DCACHE (&p[idx], &p[idx + 1]); + } + + if (done == len) { + /* nothing left in this descriptor. + * go to next one + */ + p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; + p[0] = 0x00100000; + FLUSH_DCACHE (&p[0], &p[1]); + /* Next descriptor */ + rx_desc_index = (rx_desc_index + 1) % RX_DESC; + done = 0; + } + } while (len == 0); /* galileo bug.. len might be zero */ + + return ch; +} + + +int mpsc_test_char_debug (void) +{ + if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) + return 0; + else { + return 1; + } +} + + +int mpsc_test_char_sdma (void) +{ + volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; + + INVALIDATE_DCACHE (&p[1], &p[2]); + + if (p[1] & DESC_OWNER_BIT) + return 0; + else + return 1; +} + +int mpsc_init (int baud) +{ + /* BRG CONFIG */ + galbrg_set_baudrate (CHANNEL, baud); + galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ + galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ + galbrg_enable (CHANNEL); /* Enable BRG */ + + /* Set up clock routing */ + galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ + + galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ + galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ + + /* reset MPSC state */ + galmpsc_shutdown (CHANNEL); + + /* SDMA CONFIG */ + galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ + galsdma_set_txle (CHANNEL); + galsdma_set_rxle (CHANNEL); + galsdma_set_RC (CHANNEL, 0xf); + galsdma_set_SFM (CHANNEL); + galsdma_set_RFT (CHANNEL); + + /* MPSC CONFIG */ + galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); + galmpsc_config_channel_regs (CHANNEL); + galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ + galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ + galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ + +#ifdef CONFIG_MPSC_DEBUG_PORT + mpsc_debug_init (); +#endif + + /* COMM_MPSC CONFIG */ +#ifdef SOFTWARE_CACHE_MANAGEMENT + galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ +#else + galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ +#endif + + return 0; +} + + +void mpsc_sdma_init (void) +{ +/* Setup SDMA channel0 SDMA_CONFIG_REG*/ + GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); + +/* Enable MPSC-Window0 for DRAM Bank0 */ + if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT, + MV64360_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_0_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK0)) != true) + printf ("%s: SDMA_Window0 memory setup failed !!! \n", + __FUNCTION__); + + +/* Disable MPSC-Window1 */ + if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT, + MV64360_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_1_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK3)) != true) + printf ("%s: SDMA_Window1 memory setup failed !!! \n", + __FUNCTION__); + + +/* Disable MPSC-Window2 */ + if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT, + MV64360_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_2_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK3)) != true) + printf ("%s: SDMA_Window2 memory setup failed !!! \n", + __FUNCTION__); + + +/* Disable MPSC-Window3 */ + if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT, + MV64360_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_3_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK3)) != true) + printf ("%s: SDMA_Window3 memory setup failed !!! \n", + __FUNCTION__); + +/* Setup MPSC0 access mode Window0 full access */ + GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, + (MV64360_SDMA_WIN_ACCESS_FULL << + (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); + +/* Setup MPSC1 access mode Window1 full access */ + GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, + (MV64360_SDMA_WIN_ACCESS_FULL << + (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); + +/* Setup MPSC internal address space base address */ + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + +/* no high address remap*/ + GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); + GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); + +/* clear interrupt cause register for MPSC (fault register)*/ + GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); +} + + +void mpsc_init2 (void) +{ + int i; + +#ifndef CONFIG_MPSC_DEBUG_PORT + mpsc_putchar = mpsc_putchar_sdma; + mpsc_getchar = mpsc_getchar_sdma; + mpsc_test_char = mpsc_test_char_sdma; +#endif + /* RX descriptors */ + rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * + sizeof (unsigned int)); + + /* align descriptors */ + rx_desc_base = (unsigned int *) + (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); + + rx_desc_index = 0; + + memset ((void *) rx_desc_base, 0, + (RX_DESC * 8) * sizeof (unsigned int)); + + for (i = 0; i < RX_DESC; i++) { + rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ + rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ + rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ + rx_desc_base[i * 8] = 0x00100000; + } + rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; + + FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); + GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), + (unsigned int) &rx_desc_base[0]); + + /* TX descriptors */ + tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * + sizeof (unsigned int)); + + /* align descriptors */ + tx_desc_base = (unsigned int *) + (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); + + tx_desc_index = -1; + + memset ((void *) tx_desc_base, 0, + (TX_DESC * 8) * sizeof (unsigned int)); + + for (i = 0; i < TX_DESC; i++) { + tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; + tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; + tx_desc_base[i * 8 + 3] = + (unsigned int) &tx_desc_base[i * 8 + 4]; + tx_desc_base[i * 8 + 2] = + (unsigned int) &tx_desc_base[(i + 1) * 8]; + tx_desc_base[i * 8 + 1] = + DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; + + /* set sbytecnt and shadow byte cnt to 1 */ + tx_desc_base[i * 8] = 0x00010001; + } + tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; + + FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); + + udelay (100); + + galsdma_enable_rx (); + + return; +} + +int galbrg_set_baudrate (int channel, int rate) +{ + DECLARE_GLOBAL_DATA_PTR; + int clock; + + galbrg_disable (channel); /*ok */ + +#ifdef ZUMA_NTL + /* from tclk */ + clock = (CFG_TCLK / (16 * rate)) - 1; +#else + clock = (CFG_TCLK / (16 * rate)) - 1; +#endif + + galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ + + galbrg_enable (channel); + + gd->baudrate = rate; + + return 0; +} + +/* ------------------------------------------------------------------ */ + +/* Below are all the private functions that no one else needs */ + +static int galbrg_set_CDV (int channel, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp &= 0xFFFF0000; + temp |= (value & 0x0000FFFF); + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} + +static int galbrg_enable (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp |= 0x00010000; + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} + +static int galbrg_disable (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp &= 0xFFFEFFFF; + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} + +static int galbrg_set_clksrc (int channel, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ + temp |= (value << 18); + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + return 0; +} + +static int galbrg_set_CUV (int channel, int value) +{ + /* set CountUpValue */ + GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); + + return 0; +} + +#if 0 +static int galbrg_reset (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp |= 0x20000; + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} +#endif + +static int galsdma_set_RFT (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000001; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_SFM (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000002; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_rxle (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000040; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_txle (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000080; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_RC (int channel, unsigned int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp &= ~0x0000003c; + temp |= (value << 2); + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_burstsize (int channel, unsigned int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp &= 0xFFFFCFFF; + switch (value) { + case 8: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x3 << 12))); + break; + + case 4: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x2 << 12))); + break; + + case 2: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x1 << 12))); + break; + + case 1: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x0 << 12))); + break; + + default: + return -1; + break; + } + + return 0; +} + +static int galmpsc_connect (int channel, int connect) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); + + if ((channel == 0) && connect) + temp &= ~0x00000007; + else if ((channel == 1) && connect) + temp &= ~(0x00000007 << 6); + else if ((channel == 0) && !connect) + temp |= 0x00000007; + else + temp |= (0x00000007 << 6); + + /* Just in case... */ + temp &= 0x3fffffff; + + GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); + + return 0; +} + +static int galmpsc_route_rx_clock (int channel, int brg) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_RxC_ROUTE); + + if (channel == 0) { + temp &= ~0x0000000F; + temp |= brg; + } else { + temp &= ~0x00000F00; + temp |= (brg << 8); + } + + GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); + + return 0; +} + +static int galmpsc_route_tx_clock (int channel, int brg) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_TxC_ROUTE); + + if (channel == 0) { + temp &= ~0x0000000F; + temp |= brg; + } else { + temp &= ~0x00000F00; + temp |= (brg << 8); + } + + GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); + + return 0; +} + +static int galmpsc_write_config_regs (int mpsc, int mode) +{ + if (mode == GALMPSC_UART) { + /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ + GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), + 0x000004c4); + + /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ + GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), + 0x024003f8); + /* 22 2222 1111 */ + /* 54 3210 9876 */ + /* 0000 0010 0000 0000 */ + /* 1 */ + /* 098 7654 3210 */ + /* 0000 0011 1111 1000 */ + } else + return -1; + + return 0; +} + +static int galmpsc_config_channel_regs (int mpsc) +{ + GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); + GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); + + galmpsc_set_brkcnt (mpsc, 0x3); + galmpsc_set_tcschar (mpsc, 0xab); + + return 0; +} + +static int galmpsc_set_brkcnt (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); + temp &= 0x0000FFFF; + temp |= (value << 16); + GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_tcschar (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); + temp &= 0xFFFF0000; + temp |= value; + GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_char_length (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); + temp &= 0xFFFFCFFF; + temp |= (value << 12); + GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_stop_bit_length (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); + temp &= 0xFFFFBFFF; + temp |= (value << 14); + GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_parity (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + if (value != -1) { + temp &= 0xFFF3FFF3; + temp |= ((value << 18) | (value << 2)); + temp |= ((value << 17) | (value << 1)); + } else { + temp &= 0xFFF1FFF1; + } + + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_enter_hunt (int mpsc) +{ + int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + temp |= 0x80000000; + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); + + while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & + MPSC_ENTER_HUNT) { + udelay (1); + } + return 0; +} + + +static int galmpsc_shutdown (int mpsc) +{ + unsigned int temp; + + /* cause RX abort (clears RX) */ + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; + temp &= ~MPSC_ENTER_HUNT; + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); + + GT_REG_WRITE (GALSDMA_0_COM_REG, 0); + GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); + + /* shut down the MPSC */ + GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); + GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); + GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); + + udelay (100); + + /* shut down the sdma engines. */ + /* reset config to default */ + GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); + + udelay (100); + + /* clear the SDMA current and first TX and RX pointers */ + GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); + GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); + GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); + + udelay (100); + + return 0; +} + +static void galsdma_enable_rx (void) +{ + int temp; + + /* Enable RX processing */ + temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); + temp |= RX_ENABLE; + GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); + + galmpsc_enter_hunt (CHANNEL); +} + +static int galmpsc_set_snoop (int mpsc, int value) +{ + int reg = + mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : + MPSC_0_ADDRESS_CONTROL_LOW; + int temp = GTREGREAD (reg); + + if (value) + temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); + else + temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); + GT_REG_WRITE (reg, temp); + return 0; +} + +/******************************************************************************* +* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map. +* +* DESCRIPTION: +* the MV64360 SDMA has its own address decoding map that is de-coupled +* from the CPU interface address decoding windows. The SDMA channels +* share four address windows. Each region can be individually configured +* by this function by associating it to a target interface and setting +* base and size values. +* +* NOTE!!! +* The size must be in 64Kbyte granularity. +* The base address must be aligned to the size. +* The size must be a series of 1s followed by a series of zeros +* +* OUTPUT: +* None. +* +* RETURN: +* True for success, false otherwise. +* +*******************************************************************************/ + +static int galsdma_set_mem_space (unsigned int memSpace, + unsigned int memSpaceTarget, + unsigned int memSpaceAttr, + unsigned int baseAddress, unsigned int size) +{ + unsigned int temp; + + if (size == 0) { + GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, + 1 << memSpace); + return true; + } + + /* The base address must be aligned to the size. */ + if (baseAddress % size != 0) { + return false; + } + if (size < 0x10000) { + return false; + } + + /* Align size and base to 64K */ + baseAddress &= 0xffff0000; + size &= 0xffff0000; + temp = size >> 16; + + /* Checking that the size is a sequence of '1' followed by a + sequence of '0' starting from LSB to MSB. */ + while ((temp > 0) && (temp & 0x1)) { + temp = temp >> 1; + } + + if (temp != 0) { + GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8, + (baseAddress | memSpaceTarget | memSpaceAttr)); + GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8), + (size - 1) & 0xffff0000); + GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, + 1 << memSpace); + } else { + /* An invalid size was specified */ + return false; + } + return true; +} diff --git a/board/Marvell/db64360/mpsc.h b/board/Marvell/db64360/mpsc.h new file mode 100644 index 0000000..f95f8c0 --- /dev/null +++ b/board/Marvell/db64360/mpsc.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2001 + * John Clemens , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * changes for Marvell DB64360 eval board 2003 by Ingo Assmus + * + ************************************************************************/ + + +/* + * mpsc.h - header file for MPSC in uart mode (console driver) + */ + +#ifndef __MPSC_H__ +#define __MPSC_H__ + +/* include actual Galileo defines */ +#include "../include/mv_gen_reg.h" + +/* driver related defines */ + +int mpsc_init(int baud); +void mpsc_sdma_init(void); +void mpsc_init2(void); +int galbrg_set_baudrate(int channel, int rate); + +int mpsc_putchar_early(char ch); +char mpsc_getchar_debug(void); +int mpsc_test_char_debug(void); + +int mpsc_test_char_sdma(void); + +extern int (*mpsc_putchar)(char ch); +extern char (*mpsc_getchar)(void); +extern int (*mpsc_test_char)(void); + +#define CHANNEL CONFIG_MPSC_PORT + +#define TX_DESC 5 +#define RX_DESC 20 + +#define DESC_FIRST 0x00010000 +#define DESC_LAST 0x00020000 +#define DESC_OWNER_BIT 0x80000000 + +#define TX_DEMAND 0x00800000 +#define TX_STOP 0x00010000 +#define RX_ENABLE 0x00000080 + +#define SDMA_RX_ABORT (1 << 15) +#define SDMA_TX_ABORT (1 << 31) +#define MPSC_TX_ABORT (1 << 7) +#define MPSC_RX_ABORT (1 << 23) +#define MPSC_ENTER_HUNT (1 << 31) + +/* MPSC defines */ + +#define GALMPSC_CONNECT 0x1 +#define GALMPSC_DISCONNECT 0x0 + +#define GALMPSC_UART 0x1 + +#define GALMPSC_STOP_BITS_1 0x0 +#define GALMPSC_STOP_BITS_2 0x1 +#define GALMPSC_CHAR_LENGTH_8 0x3 +#define GALMPSC_CHAR_LENGTH_7 0x2 + +#define GALMPSC_PARITY_ODD 0x0 +#define GALMPSC_PARITY_EVEN 0x2 +#define GALMPSC_PARITY_MARK 0x3 +#define GALMPSC_PARITY_SPACE 0x1 +#define GALMPSC_PARITY_NONE -1 + +#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ +#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ +#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ +#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ +#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ +#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ +#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ + +#define GALMPSC_REG_GAP 0x1000 + +#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ +#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ +#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ +#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ +#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ +#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ +#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ +#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ +#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ +#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ +#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ +#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ + +#define GALSDMA_COMMAND_FIRST (1 << 16) +#define GALSDMA_COMMAND_LAST (1 << 17) +#define GALSDMA_COMMAND_ENABLEINT (1 << 23) +#define GALSDMA_COMMAND_AUTO (1 << 30) +#define GALSDMA_COMMAND_OWNER (1 << 31) + +#define GALSDMA_RX 0 +#define GALSDMA_TX 1 + +/* CHANNEL2 should be CHANNEL1, according to documentation, + * but to work with the current GTREGS file... + */ +#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ +#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ +#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ +#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ +#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ +#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ +#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ +#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ +#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ +#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ +#define GALSDMA_REG_DIFF 0x2000 + +/* WRONG in gt64260R.h */ +#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ +#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ +#define GALMPSC_0_INT_CAUSE 0xb804 +#define GALMPSC_0_INT_MASK 0xb884 + +#define GALSDMA_MODE_UART 0 +#define GALSDMA_MODE_BISYNC 1 +#define GALSDMA_MODE_HDLC 2 +#define GALSDMA_MODE_TRANSPARENT 3 + +#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ +#define GALBRG_REG_GAP 0x0008 +#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ + +#endif /* __MPSC_H__ */ diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c new file mode 100644 index 0000000..3c5dee7 --- /dev/null +++ b/board/Marvell/db64360/mv_eth.c @@ -0,0 +1,3183 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mv_eth.c - header file for the polled mode GT ethernet driver + */ +#include +#include +#include + +#include "mv_eth.h" + +/* enable Debug outputs */ + +#undef DEBUG_MV_ETH + +#ifdef DEBUG_MV_ETH +#define DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +#undef MV64360_CHECKSUM_OFFLOAD +/************************************************************************* +************************************************************************** +************************************************************************** +* The first part is the high level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ + +/* Definition for configuring driver */ +/* #define UPDATE_STATS_BY_SOFTWARE */ +#undef MV64360_RX_QUEUE_FILL_ON_TASK + + +/* Constants */ +#define MAGIC_ETH_RUNNING 8031971 +#define MV64360_INTERNAL_SRAM_SIZE _256K +#define EXTRA_BYTES 32 +#define WRAP ETH_HLEN + 2 + 4 + 16 +#define BUFFER_MTU dev->mtu + WRAP +#define INT_CAUSE_UNMASK_ALL 0x0007ffff +#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff +#ifdef MV64360_RX_FILL_ON_TASK +#define INT_CAUSE_MASK_ALL 0x00000000 +#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL +#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT +#endif + +/* Read/Write to/from MV64360 internal registers */ +#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) +#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) +#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) +#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) + +/* Static function declarations */ +static int mv64360_eth_real_open (struct eth_device *eth); +static int mv64360_eth_real_stop (struct eth_device *eth); +static struct net_device_stats *mv64360_eth_get_stats (struct eth_device + *dev); +static void eth_port_init_mac_tables (ETH_PORT eth_port_num); +static void mv64360_eth_update_stat (struct eth_device *dev); +bool db64360_eth_start (struct eth_device *eth); +unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, + unsigned int mib_offset); +int mv64360_eth_receive (struct eth_device *dev); + +int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); + +#ifndef UPDATE_STATS_BY_SOFTWARE +static void mv64360_eth_print_stat (struct eth_device *dev); +#endif +/* Processes a received packet */ +extern void NetReceive (volatile uchar *, int); + +extern unsigned int INTERNAL_REG_BASE_ADDR; + +/************************************************* + *Helper functions - used inside the driver only * + *************************************************/ +#ifdef DEBUG_MV_ETH +void print_globals (struct eth_device *dev) +{ + printf ("Ethernet PRINT_Globals-Debug function\n"); + printf ("Base Address for ETH_PORT_INFO: %08x\n", + (unsigned int) dev->priv); + printf ("Base Address for mv64360_eth_priv: %08x\n", + (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> + port_private)); + + printf ("GT Internal Base Address: %08x\n", + INTERNAL_REG_BASE_ADDR); + printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); + printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); + printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", + (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> + p_rx_buffer_base[0], + (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); + printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", + (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> + p_tx_buffer_base[0], + (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); +} +#endif + +#define my_cpu_to_le32(x) my_le32_to_cpu((x)) + +unsigned long my_le32_to_cpu (unsigned long x) +{ + return (((x & 0x000000ffU) << 24) | + ((x & 0x0000ff00U) << 8) | + ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); +} + + +/********************************************************************** + * mv64360_eth_print_phy_status + * + * Prints gigabit ethenret phy status + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + **********************************************************************/ + +static void mv64360_eth_print_phy_status (struct eth_device *dev) +{ + struct mv64360_eth_priv *port_private; + unsigned int port_num; + ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; + unsigned int port_status, phy_reg_data; + + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Check Link status on phy */ + eth_port_read_smi_reg (port_num, 1, &phy_reg_data); + if (!(phy_reg_data & 0x20)) { + printf ("Ethernet port changed link status to DOWN\n"); + } else { + port_status = + MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); + printf ("Ethernet status port %d: Link up", port_num); + printf (", %s", + (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); + if (port_status & BIT4) + printf (", Speed 1 Gbps"); + else + printf (", %s", + (port_status & BIT5) ? "Speed 100 Mbps" : + "Speed 10 Mbps"); + printf ("\n"); + } +} + +/********************************************************************** + * u-boot entry functions for mv64360_eth + * + **********************************************************************/ +int db64360_eth_probe (struct eth_device *dev) +{ + return ((int) db64360_eth_start (dev)); +} + +int db64360_eth_poll (struct eth_device *dev) +{ + return mv64360_eth_receive (dev); +} + +int db64360_eth_transmit (struct eth_device *dev, volatile void *packet, + int length) +{ + mv64360_eth_xmit (dev, packet, length); + return 0; +} + +void db64360_eth_disable (struct eth_device *dev) +{ + mv64360_eth_stop (dev); +} + + +void mv6436x_eth_initialize (bd_t * bis) +{ + struct eth_device *dev; + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + int devnum, x, temp; + char *s, *e, buf[64]; + + for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { + dev = calloc (sizeof (*dev), 1); + if (!dev) { + printf ("%s: mv_enet%d allocation failure, %s\n", + __FUNCTION__, devnum, "eth_device structure"); + return; + } + + /* must be less than NAMESIZE (16) */ + sprintf (dev->name, "mv_enet%d", devnum); + +#ifdef DEBUG + printf ("Initializing %s\n", dev->name); +#endif + + /* Extract the MAC address from the environment */ + switch (devnum) { + case 0: + s = "ethaddr"; + break; + + case 1: + s = "eth1addr"; + break; + + case 2: + s = "eth2addr"; + break; + + default: /* this should never happen */ + printf ("%s: Invalid device number %d\n", + __FUNCTION__, devnum); + return; + } + + temp = getenv_r (s, buf, sizeof (buf)); + s = (temp > 0) ? buf : NULL; + +#ifdef DEBUG + printf ("Setting MAC %d to %s\n", devnum, s); +#endif + for (x = 0; x < 6; ++x) { + dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + /* ronen - set the MAC addr in the HW */ + eth_port_uc_addr_set (devnum, dev->enetaddr, 0); + + dev->init = (void *) db64360_eth_probe; + dev->halt = (void *) ethernet_phy_reset; + dev->send = (void *) db64360_eth_transmit; + dev->recv = (void *) db64360_eth_poll; + + ethernet_private = calloc (sizeof (*ethernet_private), 1); + dev->priv = (void *) ethernet_private; + + if (!ethernet_private) { + printf ("%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, + "Private Device Structure"); + free (dev); + return; + } + /* start with an zeroed ETH_PORT_INFO */ + memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); + memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); + + /* set pointer to memory for stats data structure etc... */ + port_private = calloc (sizeof (*ethernet_private), 1); + ethernet_private->port_private = (void *)port_private; + if (!port_private) { + printf ("%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, + "Port Private Device Structure"); + + free (ethernet_private); + free (dev); + return; + } + + port_private->stats = + calloc (sizeof (struct net_device_stats), 1); + if (!port_private->stats) { + printf ("%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, + "Net stat Structure"); + + free (port_private); + free (ethernet_private); + free (dev); + return; + } + memset (ethernet_private->port_private, 0, + sizeof (struct mv64360_eth_priv)); + switch (devnum) { + case 0: + ethernet_private->port_num = ETH_0; + break; + case 1: + ethernet_private->port_num = ETH_1; + break; + case 2: + ethernet_private->port_num = ETH_2; + break; + default: + printf ("Invalid device number %d\n", devnum); + break; + }; + + port_private->port_num = devnum; + /* + * Read MIB counter on the GT in order to reset them, + * then zero all the stats fields in memory + */ + mv64360_eth_update_stat (dev); + memset (port_private->stats, 0, + sizeof (struct net_device_stats)); + /* Extract the MAC address from the environment */ + switch (devnum) { + case 0: + s = "ethaddr"; + break; + + case 1: + s = "eth1addr"; + break; + + case 2: + s = "eth2addr"; + break; + + default: /* this should never happen */ + printf ("%s: Invalid device number %d\n", + __FUNCTION__, devnum); + return; + } + + temp = getenv_r (s, buf, sizeof (buf)); + s = (temp > 0) ? buf : NULL; + +#ifdef DEBUG + printf ("Setting MAC %d to %s\n", devnum, s); +#endif + for (x = 0; x < 6; ++x) { + dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + DP (printf ("Allocating descriptor and buffer rings\n")); + + ethernet_private->p_rx_desc_area_base[0] = + (ETH_RX_DESC *) memalign (16, + RX_DESC_ALIGNED_SIZE * + MV64360_RX_QUEUE_SIZE + 1); + ethernet_private->p_tx_desc_area_base[0] = + (ETH_TX_DESC *) memalign (16, + TX_DESC_ALIGNED_SIZE * + MV64360_TX_QUEUE_SIZE + 1); + + ethernet_private->p_rx_buffer_base[0] = + (char *) memalign (16, + MV64360_RX_QUEUE_SIZE * + MV64360_TX_BUFFER_SIZE + 1); + ethernet_private->p_tx_buffer_base[0] = + (char *) memalign (16, + MV64360_RX_QUEUE_SIZE * + MV64360_TX_BUFFER_SIZE + 1); + +#ifdef DEBUG_MV_ETH + /* DEBUG OUTPUT prints adresses of globals */ + print_globals (dev); +#endif + eth_register (dev); + + } + DP (printf ("%s: exit\n", __FUNCTION__)); + +} + +/********************************************************************** + * mv64360_eth_open + * + * This function is called when openning the network device. The function + * should initialize all the hardware, initialize cyclic Rx/Tx + * descriptors chain and buffers and allocate an IRQ to the network + * device. + * + * Input : a pointer to the network device structure + * / / ronen - changed the output to match net/eth.c needs + * Output : nonzero of success , zero if fails. + * under construction + **********************************************************************/ + +int mv64360_eth_open (struct eth_device *dev) +{ + return (mv64360_eth_real_open (dev)); +} + +/* Helper function for mv64360_eth_open */ +static int mv64360_eth_real_open (struct eth_device *dev) +{ + + unsigned int queue; + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + u32 port_status, phy_reg_data; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + /* ronen - when we update the MAC env params we only update dev->enetaddr + see ./net/eth.c eth_set_enetaddr() */ + memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); + + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Stop RX Queues */ + MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), + 0x0000ff00); + + /* Clear the ethernet port interrupts */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); + MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); + + /* Unmask RX buffer and TX end interrupt */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), + INT_CAUSE_UNMASK_ALL); + + /* Unmask phy and link status changes interrupts */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), + INT_CAUSE_UNMASK_ALL_EXT); + + /* Set phy address of the port */ + ethernet_private->port_phy_addr = 0x8 + port_num; + + /* Activate the DMA channels etc */ + eth_port_init (ethernet_private); + + + /* "Allocate" setup TX rings */ + + for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { + unsigned int size; + + port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; + size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ + ethernet_private->tx_desc_area_size[queue] = size; + + /* first clear desc area completely */ + memset ((void *) ethernet_private->p_tx_desc_area_base[queue], + 0, ethernet_private->tx_desc_area_size[queue]); + + /* initialize tx desc ring with low level driver */ + if (ether_init_tx_desc_ring + (ethernet_private, ETH_Q0, + port_private->tx_ring_size[queue], + MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , + (unsigned int) ethernet_private-> + p_tx_desc_area_base[queue], + (unsigned int) ethernet_private-> + p_tx_buffer_base[queue]) == false) + printf ("### Error initializing TX Ring\n"); + } + + /* "Allocate" setup RX rings */ + for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { + unsigned int size; + + /* Meantime RX Ring are fixed - but must be configurable by user */ + port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; + size = (port_private->rx_ring_size[queue] * + RX_DESC_ALIGNED_SIZE); + ethernet_private->rx_desc_area_size[queue] = size; + + /* first clear desc area completely */ + memset ((void *) ethernet_private->p_rx_desc_area_base[queue], + 0, ethernet_private->rx_desc_area_size[queue]); + if ((ether_init_rx_desc_ring + (ethernet_private, ETH_Q0, + port_private->rx_ring_size[queue], + MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , + (unsigned int) ethernet_private-> + p_rx_desc_area_base[queue], + (unsigned int) ethernet_private-> + p_rx_buffer_base[queue])) == false) + printf ("### Error initializing RX Ring\n"); + } + + eth_port_start (ethernet_private); + + /* Set maximum receive buffer to 9700 bytes */ + MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), + (0x5 << 17) | + (MV_REG_READ + (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) + & 0xfff1ffff)); + + /* + * Set ethernet MTU for leaky bucket mechanism to 0 - this will + * disable the leaky bucket mechanism . + */ + + MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); + port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); + + /* Check Link status on phy */ + eth_port_read_smi_reg (port_num, 1, &phy_reg_data); + if (!(phy_reg_data & 0x20)) { + /* Reset PHY */ + if ((ethernet_phy_reset (port_num)) != true) { + printf ("$$ Warnning: No link on port %d \n", + port_num); + return 0; + } else { + eth_port_read_smi_reg (port_num, 1, &phy_reg_data); + if (!(phy_reg_data & 0x20)) { + printf ("### Error: Phy is not active\n"); + return 0; + } + } + } else { + mv64360_eth_print_phy_status (dev); + } + port_private->eth_running = MAGIC_ETH_RUNNING; + return 1; +} + + +static int mv64360_eth_free_tx_rings (struct eth_device *dev) +{ + unsigned int queue; + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + volatile ETH_TX_DESC *p_tx_curr_desc; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Stop Tx Queues */ + MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), + 0x0000ff00); + + /* Free TX rings */ + DP (printf ("Clearing previously allocated TX queues... ")); + for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { + /* Free on TX rings */ + for (p_tx_curr_desc = + ethernet_private->p_tx_desc_area_base[queue]; + ((unsigned int) p_tx_curr_desc <= (unsigned int) + ethernet_private->p_tx_desc_area_base[queue] + + ethernet_private->tx_desc_area_size[queue]); + p_tx_curr_desc = + (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + + TX_DESC_ALIGNED_SIZE)) { + /* this is inside for loop */ + if (p_tx_curr_desc->return_info != 0) { + p_tx_curr_desc->return_info = 0; + DP (printf ("freed\n")); + } + } + DP (printf ("Done\n")); + } + return 0; +} + +static int mv64360_eth_free_rx_rings (struct eth_device *dev) +{ + unsigned int queue; + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + volatile ETH_RX_DESC *p_rx_curr_desc; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + + /* Stop RX Queues */ + MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), + 0x0000ff00); + + /* Free RX rings */ + DP (printf ("Clearing previously allocated RX queues... ")); + for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { + /* Free preallocated skb's on RX rings */ + for (p_rx_curr_desc = + ethernet_private->p_rx_desc_area_base[queue]; + (((unsigned int) p_rx_curr_desc < + ((unsigned int) ethernet_private-> + p_rx_desc_area_base[queue] + + ethernet_private->rx_desc_area_size[queue]))); + p_rx_curr_desc = + (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + + RX_DESC_ALIGNED_SIZE)) { + if (p_rx_curr_desc->return_info != 0) { + p_rx_curr_desc->return_info = 0; + DP (printf ("freed\n")); + } + } + DP (printf ("Done\n")); + } + return 0; +} + +/********************************************************************** + * mv64360_eth_stop + * + * This function is used when closing the network device. + * It updates the hardware, + * release all memory that holds buffers and descriptors and release the IRQ. + * Input : a pointer to the device structure + * Output : zero if success , nonzero if fails + *********************************************************************/ + +int mv64360_eth_stop (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Disable all gigE address decoder */ + MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); + DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); + mv64360_eth_real_stop (dev); + + return 0; +}; + +/* Helper function for mv64360_eth_stop */ + +static int mv64360_eth_real_stop (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + + mv64360_eth_free_tx_rings (dev); + mv64360_eth_free_rx_rings (dev); + + eth_port_reset (ethernet_private->port_num); + /* Disable ethernet port interrupts */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); + MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); + /* Mask RX buffer and TX end interrupt */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); + /* Mask phy and link status changes interrupts */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); + MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, + BIT0 << port_num); + /* Print Network statistics */ +#ifndef UPDATE_STATS_BY_SOFTWARE + /* + * Print statistics (only if ethernet is running), + * then zero all the stats fields in memory + */ + if (port_private->eth_running == MAGIC_ETH_RUNNING) { + port_private->eth_running = 0; + mv64360_eth_print_stat (dev); + } + memset (port_private->stats, 0, sizeof (struct net_device_stats)); +#endif + DP (printf ("\nEthernet stopped ... \n")); + return 0; +} + + +/********************************************************************** + * mv64360_eth_start_xmit + * + * This function is queues a packet in the Tx descriptor for + * required port. + * + * Input : skb - a pointer to socket buffer + * dev - a pointer to the required port + * + * Output : zero upon success + **********************************************************************/ + +int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, + int dataSize) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + PKT_INFO pkt_info; + ETH_FUNC_RET_STATUS status; + struct net_device_stats *stats; + ETH_FUNC_RET_STATUS release_result; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + stats = port_private->stats; + + /* Update packet info data structure */ + pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ + pkt_info.byte_cnt = dataSize; + pkt_info.buf_ptr = (unsigned int) dataPtr; + + status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); + if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { + printf ("Error on transmitting packet .."); + if (status == ETH_QUEUE_FULL) + printf ("ETH Queue is full. \n"); + if (status == ETH_QUEUE_LAST_RESOURCE) + printf ("ETH Queue: using last available resource. \n"); + goto error; + } + + /* Update statistics and start of transmittion time */ + stats->tx_bytes += dataSize; + stats->tx_packets++; + + /* Check if packet(s) is(are) transmitted correctly (release everything) */ + do { + release_result = + eth_tx_return_desc (ethernet_private, ETH_Q0, + &pkt_info); + switch (release_result) { + case ETH_OK: + DP (printf ("descriptor released\n")); + if (pkt_info.cmd_sts & BIT0) { + printf ("Error in TX\n"); + stats->tx_errors++; + + } + break; + case ETH_RETRY: + DP (printf ("transmission still in process\n")); + break; + + case ETH_ERROR: + printf ("routine can not access Tx desc ring\n"); + break; + + case ETH_END_OF_JOB: + DP (printf ("the routine has nothing to release\n")); + break; + default: /* should not happen */ + break; + } + } while (release_result == ETH_OK); + + + return 0; /* success */ + error: + return 1; /* Failed - higher layers will free the skb */ +} + +/********************************************************************** + * mv64360_eth_receive + * + * This function is forward packets that are received from the port's + * queues toward kernel core or FastRoute them to another interface. + * + * Input : dev - a pointer to the required interface + * max - maximum number to receive (0 means unlimted) + * + * Output : number of served packets + **********************************************************************/ + +int mv64360_eth_receive (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + PKT_INFO pkt_info; + struct net_device_stats *stats; + + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + stats = port_private->stats; + + while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == + ETH_OK)) { + +#ifdef DEBUG_MV_ETH + if (pkt_info.byte_cnt != 0) { + printf ("%s: Received %d byte Packet @ 0x%x\n", + __FUNCTION__, pkt_info.byte_cnt, + pkt_info.buf_ptr); + } +#endif + /* Update statistics. Note byte count includes 4 byte CRC count */ + stats->rx_packets++; + stats->rx_bytes += pkt_info.byte_cnt; + + /* + * In case received a packet without first / last bits on OR the error + * summary bit is on, the packets needs to be dropeed. + */ + if (((pkt_info. + cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != + (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) + || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { + stats->rx_dropped++; + + printf ("Received packet spread on multiple descriptors\n"); + + /* Is this caused by an error ? */ + if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { + stats->rx_errors++; + } + + /* free these descriptors again without forwarding them to the higher layers */ + pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ + pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ + + if (eth_rx_return_buff + (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { + printf ("Error while returning the RX Desc to Ring\n"); + } else { + DP (printf ("RX Desc returned to Ring\n")); + } + /* /free these descriptors again */ + } else { + +/* !!! call higher layer processing */ +#ifdef DEBUG_MV_ETH + printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); +#endif + /* let the upper layer handle the packet */ + NetReceive ((uchar *) pkt_info.buf_ptr, + (int) pkt_info.byte_cnt); + +/* **************************************************************** */ +/* free descriptor */ + pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ + pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ + DP (printf + ("RX: pkt_info.buf_ptr = %x\n", + pkt_info.buf_ptr)); + if (eth_rx_return_buff + (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { + printf ("Error while returning the RX Desc to Ring\n"); + } else { + DP (printf ("RX Desc returned to Ring\n")); + } + +/* **************************************************************** */ + + } + } + mv64360_eth_get_stats (dev); /* update statistics */ + return 1; +} + +/********************************************************************** + * mv64360_eth_get_stats + * + * Returns a pointer to the interface statistics. + * + * Input : dev - a pointer to the required interface + * + * Output : a pointer to the interface's statistics + **********************************************************************/ + +static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + mv64360_eth_update_stat (dev); + + return port_private->stats; +} + + +/********************************************************************** + * mv64360_eth_update_stat + * + * Update the statistics structure in the private data structure + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + **********************************************************************/ + +static void mv64360_eth_update_stat (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + struct net_device_stats *stats; + unsigned int port_num; + volatile unsigned int dummy; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + stats = port_private->stats; + + /* These are false updates */ + stats->rx_packets += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_FRAMES_RECEIVED); + stats->tx_packets += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_FRAMES_SENT); + stats->rx_bytes += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); + /* + * Ideally this should be as follows - + * + * stats->rx_bytes += stats->rx_bytes + + * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , + * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); + * + * But the unsigned long in PowerPC and MIPS are 32bit. So the next read + * is just a dummy read for proper work of the GigE port + */ + dummy = eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); + stats->tx_bytes += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_SENT_LOW); + dummy = eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_SENT_HIGH); + stats->rx_errors += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_MAC_RECEIVE_ERROR); + + /* Rx dropped is for received packet with CRC error */ + stats->rx_dropped += + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_BAD_CRC_EVENT); + stats->multicast += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_MULTICAST_FRAMES_RECEIVED); + stats->collisions += + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_COLLISION) + + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_LATE_COLLISION); + /* detailed rx errors */ + stats->rx_length_errors += + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_UNDERSIZE_RECEIVED) + + + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_OVERSIZE_RECEIVED); + /* detailed tx errors */ +} + +#ifndef UPDATE_STATS_BY_SOFTWARE +/********************************************************************** + * mv64360_eth_print_stat + * + * Update the statistics structure in the private data structure + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + **********************************************************************/ + +static void mv64360_eth_print_stat (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + struct net_device_stats *stats; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + stats = port_private->stats; + + /* These are false updates */ + printf ("\n### Network statistics: ###\n"); + printf ("--------------------------\n"); + printf (" Packets received: %ld\n", stats->rx_packets); + printf (" Packets send: %ld\n", stats->tx_packets); + printf (" Received bytes: %ld\n", stats->rx_bytes); + printf (" Send bytes: %ld\n", stats->tx_bytes); + if (stats->rx_errors != 0) + printf (" Rx Errors: %ld\n", + stats->rx_errors); + if (stats->rx_dropped != 0) + printf (" Rx dropped (CRC Errors): %ld\n", + stats->rx_dropped); + if (stats->multicast != 0) + printf (" Rx mulicast frames: %ld\n", + stats->multicast); + if (stats->collisions != 0) + printf (" No. of collisions: %ld\n", + stats->collisions); + if (stats->rx_length_errors != 0) + printf (" Rx length errors: %ld\n", + stats->rx_length_errors); +} +#endif + +/************************************************************************** + *network_start - Network Kick Off Routine UBoot + *Inputs : + *Outputs : + **************************************************************************/ + +bool db64360_eth_start (struct eth_device *dev) +{ + return (mv64360_eth_open (dev)); /* calls real open */ +} + +/************************************************************************* +************************************************************************** +************************************************************************** +* The second part is the low level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ +/* + * based on Linux code + * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +/******************************************************************************** + * Marvell's Gigabit Ethernet controller low level driver + * + * DESCRIPTION: + * This file introduce low level API to Marvell's Gigabit Ethernet + * controller. This Gigabit Ethernet Controller driver API controls + * 1) Operations (i.e. port init, start, reset etc'). + * 2) Data flow (i.e. port send, receive etc'). + * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO + * struct. + * This struct includes user configuration information as well as + * driver internal data needed for its operations. + * + * Supported Features: + * - This low level driver is OS independent. Allocating memory for + * the descriptor rings and buffers are not within the scope of + * this driver. + * - The user is free from Rx/Tx queue managing. + * - This low level driver introduce functionality API that enable + * the to operate Marvell's Gigabit Ethernet Controller in a + * convenient way. + * - Simple Gigabit Ethernet port operation API. + * - Simple Gigabit Ethernet port data flow API. + * - Data flow and operation API support per queue functionality. + * - Support cached descriptors for better performance. + * - Enable access to all four DRAM banks and internal SRAM memory + * spaces. + * - PHY access and control API. + * - Port control register configuration API. + * - Full control over Unicast and Multicast MAC configurations. + * + * Operation flow: + * + * Initialization phase + * This phase complete the initialization of the ETH_PORT_INFO + * struct. + * User information regarding port configuration has to be set + * prior to calling the port initialization routine. For example, + * the user has to assign the port_phy_addr field which is board + * depended parameter. + * In this phase any port Tx/Rx activity is halted, MIB counters + * are cleared, PHY address is set according to user parameter and + * access to DRAM and internal SRAM memory spaces. + * + * Driver ring initialization + * Allocating memory for the descriptor rings and buffers is not + * within the scope of this driver. Thus, the user is required to + * allocate memory for the descriptors ring and buffers. Those + * memory parameters are used by the Rx and Tx ring initialization + * routines in order to curve the descriptor linked list in a form + * of a ring. + * Note: Pay special attention to alignment issues when using + * cached descriptors/buffers. In this phase the driver store + * information in the ETH_PORT_INFO struct regarding each queue + * ring. + * + * Driver start + * This phase prepares the Ethernet port for Rx and Tx activity. + * It uses the information stored in the ETH_PORT_INFO struct to + * initialize the various port registers. + * + * Data flow: + * All packet references to/from the driver are done using PKT_INFO + * struct. + * This struct is a unified struct used with Rx and Tx operations. + * This way the user is not required to be familiar with neither + * Tx nor Rx descriptors structures. + * The driver's descriptors rings are management by indexes. + * Those indexes controls the ring resources and used to indicate + * a SW resource error: + * 'current' + * This index points to the current available resource for use. For + * example in Rx process this index will point to the descriptor + * that will be passed to the user upon calling the receive routine. + * In Tx process, this index will point to the descriptor + * that will be assigned with the user packet info and transmitted. + * 'used' + * This index points to the descriptor that need to restore its + * resources. For example in Rx process, using the Rx buffer return + * API will attach the buffer returned in packet info to the + * descriptor pointed by 'used'. In Tx process, using the Tx + * descriptor return will merely return the user packet info with + * the command status of the transmitted buffer pointed by the + * 'used' index. Nevertheless, it is essential to use this routine + * to update the 'used' index. + * 'first' + * This index supports Tx Scatter-Gather. It points to the first + * descriptor of a packet assembled of multiple buffers. For example + * when in middle of Such packet we have a Tx resource error the + * 'curr' index get the value of 'first' to indicate that the ring + * returned to its state before trying to transmit this packet. + * + * Receive operation: + * The eth_port_receive API set the packet information struct, + * passed by the caller, with received information from the + * 'current' SDMA descriptor. + * It is the user responsibility to return this resource back + * to the Rx descriptor ring to enable the reuse of this source. + * Return Rx resource is done using the eth_rx_return_buff API. + * + * Transmit operation: + * The eth_port_send API supports Scatter-Gather which enables to + * send a packet spanned over multiple buffers. This means that + * for each packet info structure given by the user and put into + * the Tx descriptors ring, will be transmitted only if the 'LAST' + * bit will be set in the packet info command status field. This + * API also consider restriction regarding buffer alignments and + * sizes. + * The user must return a Tx resource after ensuring the buffer + * has been transmitted to enable the Tx ring indexes to update. + * + * BOARD LAYOUT + * This device is on-board. No jumper diagram is necessary. + * + * EXTERNAL INTERFACE + * + * Prior to calling the initialization routine eth_port_init() the user + * must set the following fields under ETH_PORT_INFO struct: + * port_num User Ethernet port number. + * port_phy_addr User PHY address of Ethernet port. + * port_mac_addr[6] User defined port MAC address. + * port_config User port configuration value. + * port_config_extend User port config extend value. + * port_sdma_config User port SDMA config value. + * port_serial_control User port serial control value. + * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. + * *port_private User scratch pad for user specific data structures. + * + * This driver introduce a set of default values: + * PORT_CONFIG_VALUE Default port configuration value + * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value + * PORT_SDMA_CONFIG_VALUE Default sdma control value + * PORT_SERIAL_CONTROL_VALUE Default port serial control value + * + * This driver data flow is done using the PKT_INFO struct which is + * a unified struct for Rx and Tx operations: + * byte_cnt Tx/Rx descriptor buffer byte count. + * l4i_chk CPU provided TCP Checksum. For Tx operation only. + * cmd_sts Tx/Rx descriptor command status. + * buf_ptr Tx/Rx descriptor buffer pointer. + * return_info Tx/Rx user resource return information. + * + * + * EXTERNAL SUPPORT REQUIREMENTS + * + * This driver requires the following external support: + * + * D_CACHE_FLUSH_LINE (address, address offset) + * + * This macro applies assembly code to flush and invalidate cache + * line. + * address - address base. + * address offset - address offset + * + * + * CPU_PIPE_FLUSH + * + * This macro applies assembly code to flush the CPU pipeline. + * + *******************************************************************************/ +/* includes */ + +/* defines */ +/* SDMA command macros */ +#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ + MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) + +#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ + MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ + (1 << (8 + tx_queue))) + +#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ +MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) + +#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ +MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) + +#define CURR_RFD_GET(p_curr_desc, queue) \ + ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) + +#define CURR_RFD_SET(p_curr_desc, queue) \ + (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) + +#define USED_RFD_GET(p_used_desc, queue) \ + ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) + +#define USED_RFD_SET(p_used_desc, queue)\ +(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) + + +#define CURR_TFD_GET(p_curr_desc, queue) \ + ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) + +#define CURR_TFD_SET(p_curr_desc, queue) \ + (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) + +#define USED_TFD_GET(p_used_desc, queue) \ + ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) + +#define USED_TFD_SET(p_used_desc, queue) \ + (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) + +#define FIRST_TFD_GET(p_first_desc, queue) \ + ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) + +#define FIRST_TFD_SET(p_first_desc, queue) \ + (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) + + +/* Macros that save access to desc in order to find next desc pointer */ +#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + +#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + +#define LINK_UP_TIMEOUT 100000 +#define PHY_BUSY_TIMEOUT 10000000 + +/* locals */ + +/* PHY routines */ +static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); +static int ethernet_phy_get (ETH_PORT eth_port_num); + +/* Ethernet Port routines */ +static void eth_set_access_control (ETH_PORT eth_port_num, + ETH_WIN_PARAM * param); +static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, + ETH_QUEUE queue, int option); +#if 0 /* FIXME */ +static bool eth_port_smc_addr (ETH_PORT eth_port_num, + unsigned char mc_byte, + ETH_QUEUE queue, int option); +static bool eth_port_omc_addr (ETH_PORT eth_port_num, + unsigned char crc8, + ETH_QUEUE queue, int option); +#endif + +static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, + int byte_count); + +void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); + + +typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; +u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) +{ + u32 result = 0; + u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); + + if (enable & (1 << bank)) + return 0; + if (bank == BANK0) + result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); + if (bank == BANK1) + result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); + if (bank == BANK2) + result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); + if (bank == BANK3) + result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); + result &= 0x0000ffff; + result = result << 16; + return result; +} + +u32 mv_get_dram_bank_size (MEMORY_BANK bank) +{ + u32 result = 0; + u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); + + if (enable & (1 << bank)) + return 0; + if (bank == BANK0) + result = MV_REG_READ (MV64360_CS_0_SIZE); + if (bank == BANK1) + result = MV_REG_READ (MV64360_CS_1_SIZE); + if (bank == BANK2) + result = MV_REG_READ (MV64360_CS_2_SIZE); + if (bank == BANK3) + result = MV_REG_READ (MV64360_CS_3_SIZE); + result += 1; + result &= 0x0000ffff; + result = result << 16; + return result; +} + +u32 mv_get_internal_sram_base (void) +{ + u32 result; + + result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); + result &= 0x0000ffff; + result = result << 16; + return result; +} + +/******************************************************************************* +* eth_port_init - Initialize the Ethernet port driver +* +* DESCRIPTION: +* This function prepares the ethernet port to start its activity: +* 1) Completes the ethernet port driver struct initialization toward port +* start routine. +* 2) Resets the device to a quiescent state in case of warm reboot. +* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. +* 4) Clean MAC tables. The reset status of those tables is unknown. +* 5) Set PHY address. +* Note: Call this routine prior to eth_port_start routine and after setting +* user values in the user fields of Ethernet port control struct (i.e. +* port_phy_addr). +* +* INPUT: +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* +* OUTPUT: +* See description. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) +{ + int queue; + ETH_WIN_PARAM win_param; + + p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; + p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; + p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; + p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; + + p_eth_port_ctrl->port_rx_queue_command = 0; + p_eth_port_ctrl->port_tx_queue_command = 0; + + /* Zero out SW structs */ + for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { + CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); + USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); + p_eth_port_ctrl->rx_resource_err[queue] = false; + } + + for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { + CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); + USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); + FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); + p_eth_port_ctrl->tx_resource_err[queue] = false; + } + + eth_port_reset (p_eth_port_ctrl->port_num); + + /* Set access parameters for DRAM bank 0 */ + win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); + win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for DRAM bank 1 */ + win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); + win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for DRAM bank 2 */ + win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); + win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for DRAM bank 3 */ + win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); + win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for Internal SRAM */ + win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ + win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ + win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; + win_param.high_addr = 0; + win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ + win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + eth_port_init_mac_tables (p_eth_port_ctrl->port_num); + + ethernet_phy_set (p_eth_port_ctrl->port_num, + p_eth_port_ctrl->port_phy_addr); + + return; + +} + +/******************************************************************************* +* eth_port_start - Start the Ethernet port activity. +* +* DESCRIPTION: +* This routine prepares the Ethernet port for Rx and Tx activity: +* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that +* has been initialized a descriptor's ring (using ether_init_tx_desc_ring +* for Tx and ether_init_rx_desc_ring for Rx) +* 2. Initialize and enable the Ethernet configuration port by writing to +* the port's configuration and command registers. +* 3. Initialize and enable the SDMA by writing to the SDMA's +* configuration and command registers. +* After completing these steps, the ethernet port SDMA can starts to +* perform Rx and Tx activities. +* +* Note: Each Rx and Tx queue descriptor's list must be initialized prior +* to calling this function (use ether_init_tx_desc_ring for Tx queues and +* ether_init_rx_desc_ring for Rx queues). +* +* INPUT: +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* +* OUTPUT: +* Ethernet port is ready to receive and transmit. +* +* RETURN: +* false if the port PHY is not up. +* true otherwise. +* +*******************************************************************************/ +static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) +{ + int queue; + volatile ETH_TX_DESC *p_tx_curr_desc; + volatile ETH_RX_DESC *p_rx_curr_desc; + unsigned int phy_reg_data; + ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; + + + /* Assignment of Tx CTRP of given queue */ + for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { + CURR_TFD_GET (p_tx_curr_desc, queue); + MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 + (eth_port_num) + + (4 * queue)), + ((unsigned int) p_tx_curr_desc)); + + } + + /* Assignment of Rx CRDP of given queue */ + for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { + CURR_RFD_GET (p_rx_curr_desc, queue); + MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 + (eth_port_num) + + (4 * queue)), + ((unsigned int) p_rx_curr_desc)); + + if (p_rx_curr_desc != NULL) + /* Add the assigned Ethernet address to the port's address table */ + eth_port_uc_addr_set (p_eth_port_ctrl->port_num, + p_eth_port_ctrl->port_mac_addr, + queue); + } + + /* Assign port configuration and command. */ + MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), + p_eth_port_ctrl->port_config); + + MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), + p_eth_port_ctrl->port_config_extend); + + MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), + p_eth_port_ctrl->port_serial_control); + + MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), + ETH_SERIAL_PORT_ENABLE); + + /* Assign port SDMA configuration */ + MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), + p_eth_port_ctrl->port_sdma_config); + + MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT + (eth_port_num), 0x3fffffff); + MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG + (eth_port_num), 0x03fffcff); + /* Turn off the port/queue bandwidth limitation */ + MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); + + /* Enable port Rx. */ + MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), + p_eth_port_ctrl->port_rx_queue_command); + + /* Check if link is up */ + eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); + + if (!(phy_reg_data & 0x20)) + return false; + + return true; +} + +/******************************************************************************* +* eth_port_uc_addr_set - This function Set the port Unicast address. +* +* DESCRIPTION: +* This function Set the port Ethernet MAC address. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* char * p_addr Address to be set +* ETH_QUEUE queue Rx queue number for this MAC address. +* +* OUTPUT: +* Set MAC address low and high registers. also calls eth_port_uc_addr() +* To set the unicast table with the proper information. +* +* RETURN: +* N/A. +* +*******************************************************************************/ +static void eth_port_uc_addr_set (ETH_PORT eth_port_num, + unsigned char *p_addr, ETH_QUEUE queue) +{ + unsigned int mac_h; + unsigned int mac_l; + + mac_l = (p_addr[4] << 8) | (p_addr[5]); + mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | + (p_addr[2] << 8) | (p_addr[3] << 0); + + MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); + MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); + + /* Accept frames of this address */ + eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); + + return; +} + +/******************************************************************************* +* eth_port_uc_addr - This function Set the port unicast address table +* +* DESCRIPTION: +* This function locates the proper entry in the Unicast table for the +* specified MAC nibble and sets its properties according to function +* parameters. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char uc_nibble Unicast MAC Address last nibble. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* This function add/removes MAC addresses from the port unicast address +* table. +* +* RETURN: +* true is output succeeded. +* false if option parameter is invalid. +* +*******************************************************************************/ +static bool eth_port_uc_addr (ETH_PORT eth_port_num, + unsigned char uc_nibble, + ETH_QUEUE queue, int option) +{ + unsigned int unicast_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the Unicast table entry */ + uc_nibble = (0xf & uc_nibble); + tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ + reg_offset = uc_nibble % 4; /* Entry offset within the above register */ + + switch (option) { + case REJECT_MAC_ADDR: + /* Clear accepts frame bit at specified unicast DA table entry */ + unicast_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset)); + + unicast_reg &= (0x0E << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset), unicast_reg); + break; + + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at unicast DA filter table entry */ + unicast_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset)); + + unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset), unicast_reg); + + break; + + default: + return false; + } + return true; +} + +#if 0 /* FIXME */ +/******************************************************************************* +* eth_port_mc_addr - Multicast address settings. +* +* DESCRIPTION: +* This API controls the MV device MAC multicast support. +* The MV device supports multicast using two tables: +* 1) Special Multicast Table for MAC addresses of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* In this case, the function calls eth_port_smc_addr() routine to set the +* Special Multicast Table. +* 2) Other Multicast Table for multicast of another type. A CRC-8bit +* is used as an index to the Other Multicast Table entries in the +* DA-Filter table. +* In this case, the function calculates the CRC-8bit value and calls +* eth_port_omc_addr() routine to set the Other Multicast Table. +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char *p_addr Unicast MAC Address. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* true is output succeeded. +* false if add_address_table_entry( ) failed. +* +*******************************************************************************/ +static void eth_port_mc_addr (ETH_PORT eth_port_num, + unsigned char *p_addr, + ETH_QUEUE queue, int option) +{ + unsigned int mac_h; + unsigned int mac_l; + unsigned char crc_result = 0; + int mac_array[48]; + int crc[8]; + int i; + + + if ((p_addr[0] == 0x01) && + (p_addr[1] == 0x00) && + (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) + + eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); + else { + /* Calculate CRC-8 out of the given address */ + mac_h = (p_addr[0] << 8) | (p_addr[1]); + mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | + (p_addr[4] << 8) | (p_addr[5] << 0); + + for (i = 0; i < 32; i++) + mac_array[i] = (mac_l >> i) & 0x1; + for (i = 32; i < 48; i++) + mac_array[i] = (mac_h >> (i - 32)) & 0x1; + + + crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ + mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ + mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ + mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ + mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ + mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ + mac_array[6] ^ mac_array[0]; + + crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ + mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ + mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ + mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ + mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ + mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ + mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ + mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ + mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ + mac_array[0]; + + crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ + mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ + mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ + mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ + mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ + mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ + mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ + mac_array[2] ^ mac_array[1] ^ mac_array[0]; + + crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ + mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ + mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ + mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ + mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ + mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ + mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ + mac_array[2] ^ mac_array[1]; + + crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ + mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ + mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ + mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ + mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ + mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ + mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ + mac_array[2]; + + crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ + mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ + mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ + mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ + mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ + mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ + mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ + mac_array[3]; + + crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ + mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ + mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ + mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ + mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ + mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ + mac_array[6] ^ mac_array[5] ^ mac_array[4]; + + crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ + mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ + mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ + mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ + mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ + mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ + mac_array[6] ^ mac_array[5]; + + for (i = 0; i < 8; i++) + crc_result = crc_result | (crc[i] << i); + + eth_port_omc_addr (eth_port_num, crc_result, queue, option); + } + return; +} + +/******************************************************************************* +* eth_port_smc_addr - Special Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device special MAC multicast support. +* The Special Multicast Table for MAC addresses supports MAC of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* This function set the Special Multicast Table appropriate entry +* according to the argument given. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* true is output succeeded. +* false if option parameter is invalid. +* +*******************************************************************************/ +static bool eth_port_smc_addr (ETH_PORT eth_port_num, + unsigned char mc_byte, + ETH_QUEUE queue, int option) +{ + unsigned int smc_table_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the SMC table entry */ + tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ + reg_offset = mc_byte % 4; /* Entry offset within the above register */ + queue &= 0x7; + + switch (option) { + case REJECT_MAC_ADDR: + /* Clear accepts frame bit at specified Special DA table entry */ + smc_table_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + smc_table_reg &= (0x0E << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); + break; + + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at specified Special DA table entry */ + smc_table_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); + break; + + default: + return false; + } + return true; +} + +/******************************************************************************* +* eth_port_omc_addr - Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device Other MAC multicast support. +* The Other Multicast Table is used for multicast of another type. +* A CRC-8bit is used as an index to the Other Multicast Table entries +* in the DA-Filter table. +* The function gets the CRC-8bit value from the calling routine and +* set the Other Multicast Table appropriate entry according to the +* CRC-8 argument given. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* true is output succeeded. +* false if option parameter is invalid. +* +*******************************************************************************/ +static bool eth_port_omc_addr (ETH_PORT eth_port_num, + unsigned char crc8, + ETH_QUEUE queue, int option) +{ + unsigned int omc_table_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the OMC table entry */ + tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ + reg_offset = crc8 % 4; /* Entry offset within the above register */ + queue &= 0x7; + + switch (option) { + case REJECT_MAC_ADDR: + /* Clear accepts frame bit at specified Other DA table entry */ + omc_table_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + omc_table_reg &= (0x0E << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); + break; + + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at specified Other DA table entry */ + omc_table_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); + break; + + default: + return false; + } + return true; +} +#endif + +/******************************************************************************* +* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables +* +* DESCRIPTION: +* Go through all the DA filter tables (Unicast, Special Multicast & Other +* Multicast) and set each entry to 0. +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* +* OUTPUT: +* Multicast and Unicast packets are rejected. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void eth_port_init_mac_tables (ETH_PORT eth_port_num) +{ + int table_index; + + /* Clear DA filter unicast table (Ex_dFUT) */ + for (table_index = 0; table_index <= 0xC; table_index += 4) + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + table_index), 0); + + for (table_index = 0; table_index <= 0xFC; table_index += 4) { + /* Clear DA filter special multicast table (Ex_dFSMT) */ + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); + /* Clear DA filter other multicast table (Ex_dFOMT) */ + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); + } +} + +/******************************************************************************* +* eth_clear_mib_counters - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters of a specific ethernet port. +* A read from the MIB counter will reset the counter. +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* +* OUTPUT: +* After reading all MIB counters, the counters resets. +* +* RETURN: +* MIB counter value. +* +*******************************************************************************/ +static void eth_clear_mib_counters (ETH_PORT eth_port_num) +{ + int i; + unsigned int dummy; + + /* Perform dummy reads from MIB counters */ + for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; + i += 4) + dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE + (eth_port_num) + i)); + + return; +} + +/******************************************************************************* +* eth_read_mib_counter - Read a MIB counter +* +* DESCRIPTION: +* This function reads a MIB counter of a specific ethernet port. +* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the +* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH +* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and +* ETH_MIB_GOOD_OCTETS_SENT_HIGH +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). +* +* OUTPUT: +* After reading the MIB counter, the counter resets. +* +* RETURN: +* MIB counter value. +* +*******************************************************************************/ +unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, + unsigned int mib_offset) +{ + return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) + + mib_offset)); +} + +/******************************************************************************* +* ethernet_phy_set - Set the ethernet port PHY address. +* +* DESCRIPTION: +* This routine set the ethernet port PHY address according to given +* parameter. +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* +* OUTPUT: +* Set PHY Address Register with given PHY address parameter. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) +{ + unsigned int reg_data; + + reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); + + reg_data &= ~(0x1F << (5 * eth_port_num)); + reg_data |= (phy_addr << (5 * eth_port_num)); + + MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); + + return; +} + +/******************************************************************************* + * ethernet_phy_get - Get the ethernet port PHY address. + * + * DESCRIPTION: + * This routine returns the given ethernet port PHY address. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * None. + * + * RETURN: + * PHY address. + * + *******************************************************************************/ +static int ethernet_phy_get (ETH_PORT eth_port_num) +{ + unsigned int reg_data; + + reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); + + return ((reg_data >> (5 * eth_port_num)) & 0x1f); +} + +/******************************************************************************* + * ethernet_phy_reset - Reset Ethernet port PHY. + * + * DESCRIPTION: + * This routine utilize the SMI interface to reset the ethernet port PHY. + * The routine waits until the link is up again or link up is timeout. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * The ethernet port PHY renew its link. + * + * RETURN: + * None. + * +*******************************************************************************/ +static bool ethernet_phy_reset (ETH_PORT eth_port_num) +{ + unsigned int time_out = 50; + unsigned int phy_reg_data; + + /* Reset the PHY */ + eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); + phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ + eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); + + /* Poll on the PHY LINK */ + do { + eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); + + if (time_out-- == 0) + return false; + } + while (!(phy_reg_data & 0x20)); + + return true; +} + +/******************************************************************************* + * eth_port_reset - Reset Ethernet port + * + * DESCRIPTION: + * This routine resets the chip by aborting any SDMA engine activity and + * clearing the MIB counters. The Receiver and the Transmit unit are in + * idle state after this command is performed and the port is disabled. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * Channel activity is halted. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void eth_port_reset (ETH_PORT eth_port_num) +{ + unsigned int reg_data; + + /* Stop Tx port activity. Check port Tx activity. */ + reg_data = + MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG + (eth_port_num)); + + if (reg_data & 0xFF) { + /* Issue stop command for active channels only */ + MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG + (eth_port_num), (reg_data << 8)); + + /* Wait for all Tx activity to terminate. */ + do { + /* Check port cause register that all Tx queues are stopped */ + reg_data = + MV_REG_READ + (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG + (eth_port_num)); + } + while (reg_data & 0xFF); + } + + /* Stop Rx port activity. Check port Rx activity. */ + reg_data = + MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG + (eth_port_num)); + + if (reg_data & 0xFF) { + /* Issue stop command for active channels only */ + MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG + (eth_port_num), (reg_data << 8)); + + /* Wait for all Rx activity to terminate. */ + do { + /* Check port cause register that all Rx queues are stopped */ + reg_data = + MV_REG_READ + (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG + (eth_port_num)); + } + while (reg_data & 0xFF); + } + + + /* Clear all MIB counters */ + eth_clear_mib_counters (eth_port_num); + + /* Reset the Enable bit in the Configuration Register */ + reg_data = + MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG + (eth_port_num)); + reg_data &= ~ETH_SERIAL_PORT_ENABLE; + MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), + reg_data); + + return; +} + +#if 0 /* Not needed here */ +/******************************************************************************* + * ethernet_set_config_reg - Set specified bits in configuration register. + * + * DESCRIPTION: + * This function sets specified bits in the given ethernet + * configuration register. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int value 32 bit value. + * + * OUTPUT: + * The set bits in the value parameter are set in the configuration + * register. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void ethernet_set_config_reg (ETH_PORT eth_port_num, + unsigned int value) +{ + unsigned int eth_config_reg; + + eth_config_reg = + MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); + eth_config_reg |= value; + MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), + eth_config_reg); + + return; +} +#endif + +#if 0 /* FIXME */ +/******************************************************************************* + * ethernet_reset_config_reg - Reset specified bits in configuration register. + * + * DESCRIPTION: + * This function resets specified bits in the given Ethernet + * configuration register. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int value 32 bit value. + * + * OUTPUT: + * The set bits in the value parameter are reset in the configuration + * register. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void ethernet_reset_config_reg (ETH_PORT eth_port_num, + unsigned int value) +{ + unsigned int eth_config_reg; + + eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG + (eth_port_num)); + eth_config_reg &= ~value; + MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), + eth_config_reg); + + return; +} +#endif + +#if 0 /* Not needed here */ +/******************************************************************************* + * ethernet_get_config_reg - Get the port configuration register + * + * DESCRIPTION: + * This function returns the configuration register value of the given + * ethernet port. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * None. + * + * RETURN: + * Port configuration register value. + * + *******************************************************************************/ +static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) +{ + unsigned int eth_config_reg; + + eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG + (eth_port_num)); + return eth_config_reg; +} + +#endif + +/******************************************************************************* + * eth_port_read_smi_reg - Read PHY registers + * + * DESCRIPTION: + * This routine utilize the SMI interface to interact with the PHY in + * order to perform PHY register read. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int phy_reg PHY register address offset. + * unsigned int *value Register value buffer. + * + * OUTPUT: + * Write the value of a specified PHY register into given buffer. + * + * RETURN: + * false if the PHY is busy or read data is not in valid state. + * true otherwise. + * + *******************************************************************************/ +static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, + unsigned int phy_reg, unsigned int *value) +{ + unsigned int reg_value; + unsigned int time_out = PHY_BUSY_TIMEOUT; + int phy_addr; + + phy_addr = ethernet_phy_get (eth_port_num); +/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ + + /* first check that it is not busy */ + do { + reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); + if (time_out-- == 0) { + return false; + } + } + while (reg_value & ETH_SMI_BUSY); + + /* not busy */ + + MV_REG_WRITE (MV64360_ETH_SMI_REG, + (phy_addr << 16) | (phy_reg << 21) | + ETH_SMI_OPCODE_READ); + + time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ + + do { + reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); + if (time_out-- == 0) { + return false; + } + } + while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ + + /* Wait for the data to update in the SMI register */ +#define PHY_UPDATE_TIMEOUT 10000 + for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); + + reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); + + *value = reg_value & 0xffff; + + return true; +} + +/******************************************************************************* + * eth_port_write_smi_reg - Write to PHY registers + * + * DESCRIPTION: + * This routine utilize the SMI interface to interact with the PHY in + * order to perform writes to PHY registers. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int phy_reg PHY register address offset. + * unsigned int value Register value. + * + * OUTPUT: + * Write the given value to the specified PHY register. + * + * RETURN: + * false if the PHY is busy. + * true otherwise. + * + *******************************************************************************/ +static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, + unsigned int phy_reg, unsigned int value) +{ + unsigned int reg_value; + unsigned int time_out = PHY_BUSY_TIMEOUT; + int phy_addr; + + phy_addr = ethernet_phy_get (eth_port_num); + + /* first check that it is not busy */ + do { + reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); + if (time_out-- == 0) { + return false; + } + } + while (reg_value & ETH_SMI_BUSY); + + /* not busy */ + MV_REG_WRITE (MV64360_ETH_SMI_REG, + (phy_addr << 16) | (phy_reg << 21) | + ETH_SMI_OPCODE_WRITE | (value & 0xffff)); + return true; +} + +/******************************************************************************* + * eth_set_access_control - Config address decode parameters for Ethernet unit + * + * DESCRIPTION: + * This function configures the address decode parameters for the Gigabit + * Ethernet Controller according the given parameters struct. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * ETH_WIN_PARAM *param Address decode parameter struct. + * + * OUTPUT: + * An access window is opened using the given access parameters. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void eth_set_access_control (ETH_PORT eth_port_num, + ETH_WIN_PARAM * param) +{ + unsigned int access_prot_reg; + + /* Set access control register */ + access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG + (eth_port_num)); + access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ + access_prot_reg |= (param->access_ctrl << (param->win * 2)); + MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), + access_prot_reg); + + /* Set window Size reg (SR) */ + MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + + (ETH_SIZE_REG_GAP * param->win)), + (((param->size / 0x10000) - 1) << 16)); + + /* Set window Base address reg (BA) */ + MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), + (param->target | param->attributes | param->base_addr)); + /* High address remap reg (HARR) */ + if (param->win < 4) + MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + + (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), + param->high_addr); + + /* Base address enable reg (BARER) */ + if (param->enable == 1) + MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, + (1 << param->win)); + else + MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, + (1 << param->win)); +} + +/******************************************************************************* + * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. + * + * DESCRIPTION: + * This function prepares a Rx chained list of descriptors and packet + * buffers in a form of a ring. The routine must be called after port + * initialization routine and before port start routine. + * The Ethernet SDMA engine uses CPU bus addresses to access the various + * devices in the system (i.e. DRAM). This function uses the ethernet + * struct 'virtual to physical' routine (set by the user) to set the ring + * with physical addresses. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE rx_queue Number of Rx queue. + * int rx_desc_num Number of Rx descriptors + * int rx_buff_size Size of Rx buffer + * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. + * unsigned int rx_buff_base_addr Rx buffer memory area base addr. + * + * OUTPUT: + * The routine updates the Ethernet port control struct with information + * regarding the Rx descriptors and buffers. + * + * RETURN: + * false if the given descriptors memory area is not aligned according to + * Ethernet SDMA specifications. + * true otherwise. + * + *******************************************************************************/ +static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE rx_queue, + int rx_desc_num, + int rx_buff_size, + unsigned int rx_desc_base_addr, + unsigned int rx_buff_base_addr) +{ + ETH_RX_DESC *p_rx_desc; + ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ + unsigned int buffer_addr; + int ix; /* a counter */ + + + p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; + p_rx_prev_desc = p_rx_desc; + buffer_addr = rx_buff_base_addr; + + /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ + if (rx_buff_base_addr & 0xF) + return false; + + /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ + if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) + return false; + + /* Rx buffers must be 64-bit aligned. */ + if ((rx_buff_base_addr + rx_buff_size) & 0x7) + return false; + + /* initialize the Rx descriptors ring */ + for (ix = 0; ix < rx_desc_num; ix++) { + p_rx_desc->buf_size = rx_buff_size; + p_rx_desc->byte_cnt = 0x0000; + p_rx_desc->cmd_sts = + ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; + p_rx_desc->next_desc_ptr = + ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; + p_rx_desc->buf_ptr = buffer_addr; + p_rx_desc->return_info = 0x00000000; + D_CACHE_FLUSH_LINE (p_rx_desc, 0); + buffer_addr += rx_buff_size; + p_rx_prev_desc = p_rx_desc; + p_rx_desc = (ETH_RX_DESC *) + ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); + } + + /* Closing Rx descriptors ring */ + p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); + D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); + + /* Save Rx desc pointer to driver struct. */ + CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); + USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); + + p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = + (ETH_RX_DESC *) rx_desc_base_addr; + p_eth_port_ctrl->rx_desc_area_size[rx_queue] = + rx_desc_num * RX_DESC_ALIGNED_SIZE; + + p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); + + return true; +} + +/******************************************************************************* + * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. + * + * DESCRIPTION: + * This function prepares a Tx chained list of descriptors and packet + * buffers in a form of a ring. The routine must be called after port + * initialization routine and before port start routine. + * The Ethernet SDMA engine uses CPU bus addresses to access the various + * devices in the system (i.e. DRAM). This function uses the ethernet + * struct 'virtual to physical' routine (set by the user) to set the ring + * with physical addresses. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE tx_queue Number of Tx queue. + * int tx_desc_num Number of Tx descriptors + * int tx_buff_size Size of Tx buffer + * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. + * unsigned int tx_buff_base_addr Tx buffer memory area base addr. + * + * OUTPUT: + * The routine updates the Ethernet port control struct with information + * regarding the Tx descriptors and buffers. + * + * RETURN: + * false if the given descriptors memory area is not aligned according to + * Ethernet SDMA specifications. + * true otherwise. + * + *******************************************************************************/ +static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE tx_queue, + int tx_desc_num, + int tx_buff_size, + unsigned int tx_desc_base_addr, + unsigned int tx_buff_base_addr) +{ + + ETH_TX_DESC *p_tx_desc; + ETH_TX_DESC *p_tx_prev_desc; + unsigned int buffer_addr; + int ix; /* a counter */ + + + /* save the first desc pointer to link with the last descriptor */ + p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; + p_tx_prev_desc = p_tx_desc; + buffer_addr = tx_buff_base_addr; + + /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ + if (tx_buff_base_addr & 0xF) + return false; + + /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ + if ((tx_buff_size > TX_BUFFER_MAX_SIZE) + || (tx_buff_size < TX_BUFFER_MIN_SIZE)) + return false; + + /* Initialize the Tx descriptors ring */ + for (ix = 0; ix < tx_desc_num; ix++) { + p_tx_desc->byte_cnt = 0x0000; + p_tx_desc->l4i_chk = 0x0000; + p_tx_desc->cmd_sts = 0x00000000; + p_tx_desc->next_desc_ptr = + ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; + + p_tx_desc->buf_ptr = buffer_addr; + p_tx_desc->return_info = 0x00000000; + D_CACHE_FLUSH_LINE (p_tx_desc, 0); + buffer_addr += tx_buff_size; + p_tx_prev_desc = p_tx_desc; + p_tx_desc = (ETH_TX_DESC *) + ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); + + } + /* Closing Tx descriptors ring */ + p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; + D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); + /* Set Tx desc pointer in driver struct. */ + CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); + USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); + + /* Init Tx ring base and size parameters */ + p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = + (ETH_TX_DESC *) tx_desc_base_addr; + p_eth_port_ctrl->tx_desc_area_size[tx_queue] = + (tx_desc_num * TX_DESC_ALIGNED_SIZE); + + /* Add the queue to the list of Tx queues of this port */ + p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); + + return true; +} + +/******************************************************************************* + * eth_port_send - Send an Ethernet packet + * + * DESCRIPTION: + * This routine send a given packet described by p_pktinfo parameter. It + * supports transmitting of a packet spaned over multiple buffers. The + * routine updates 'curr' and 'first' indexes according to the packet + * segment passed to the routine. In case the packet segment is first, + * the 'first' index is update. In any case, the 'curr' index is updated. + * If the routine get into Tx resource error it assigns 'curr' index as + * 'first'. This way the function can abort Tx process of multiple + * descriptors per packet. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE tx_queue Number of Tx queue. + * PKT_INFO *p_pkt_info User packet buffer. + * + * OUTPUT: + * Tx ring 'curr' and 'first' indexes are updated. + * + * RETURN: + * ETH_QUEUE_FULL in case of Tx resource error. + * ETH_ERROR in case the routine can not access Tx desc ring. + * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_TX_DESC *p_tx_desc_first; + volatile ETH_TX_DESC *p_tx_desc_curr; + volatile ETH_TX_DESC *p_tx_next_desc_curr; + volatile ETH_TX_DESC *p_tx_desc_used; + unsigned int command_status; + + /* Do not process Tx ring in case of Tx ring resource error */ + if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) + return ETH_QUEUE_FULL; + + /* Get the Tx Desc ring indexes */ + CURR_TFD_GET (p_tx_desc_curr, tx_queue); + USED_TFD_GET (p_tx_desc_used, tx_queue); + + if (p_tx_desc_curr == NULL) + return ETH_ERROR; + + /* The following parameters are used to save readings from memory */ + p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); + command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; + + if (command_status & (ETH_TX_FIRST_DESC)) { + /* Update first desc */ + FIRST_TFD_SET (p_tx_desc_curr, tx_queue); + p_tx_desc_first = p_tx_desc_curr; + } else { + FIRST_TFD_GET (p_tx_desc_first, tx_queue); + command_status |= ETH_BUFFER_OWNED_BY_DMA; + } + + /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ + /* boundary. We use the memory allocated for Tx descriptor. This memory */ + /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ + if (p_pkt_info->byte_cnt <= 8) { + printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ + return ETH_ERROR; + + p_tx_desc_curr->buf_ptr = + (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; + eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, + p_pkt_info->byte_cnt); + } else + p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; + + p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; + p_tx_desc_curr->return_info = p_pkt_info->return_info; + + if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { + /* Set last desc with DMA ownership and interrupt enable. */ + p_tx_desc_curr->cmd_sts = command_status | + ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; + + if (p_tx_desc_curr != p_tx_desc_first) + p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; + + /* Flush CPU pipe */ + + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); + CPU_PIPE_FLUSH; + + /* Apply send command */ + ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); + + /* Finish Tx packet. Update first desc in case of Tx resource error */ + p_tx_desc_first = p_tx_next_desc_curr; + FIRST_TFD_SET (p_tx_desc_first, tx_queue); + + } else { + p_tx_desc_curr->cmd_sts = command_status; + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); + } + + /* Check for ring index overlap in the Tx desc ring */ + if (p_tx_next_desc_curr == p_tx_desc_used) { + /* Update the current descriptor */ + CURR_TFD_SET (p_tx_desc_first, tx_queue); + + p_eth_port_ctrl->tx_resource_err[tx_queue] = true; + return ETH_QUEUE_LAST_RESOURCE; + } else { + /* Update the current descriptor */ + CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); + return ETH_OK; + } +} + +/******************************************************************************* + * eth_tx_return_desc - Free all used Tx descriptors + * + * DESCRIPTION: + * This routine returns the transmitted packet information to the caller. + * It uses the 'first' index to support Tx desc return in case a transmit + * of a packet spanned over multiple buffer still in process. + * In case the Tx queue was in "resource error" condition, where there are + * no available Tx resources, the function resets the resource error flag. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE tx_queue Number of Tx queue. + * PKT_INFO *p_pkt_info User packet buffer. + * + * OUTPUT: + * Tx ring 'first' and 'used' indexes are updated. + * + * RETURN: + * ETH_ERROR in case the routine can not access Tx desc ring. + * ETH_RETRY in case there is transmission in process. + * ETH_END_OF_JOB if the routine has nothing to release. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * + p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_TX_DESC *p_tx_desc_used = NULL; + volatile ETH_TX_DESC *p_tx_desc_first = NULL; + unsigned int command_status; + + + /* Get the Tx Desc ring indexes */ + USED_TFD_GET (p_tx_desc_used, tx_queue); + FIRST_TFD_GET (p_tx_desc_first, tx_queue); + + + /* Sanity check */ + if (p_tx_desc_used == NULL) + return ETH_ERROR; + + command_status = p_tx_desc_used->cmd_sts; + + /* Still transmitting... */ + if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); + return ETH_RETRY; + } + + /* Stop release. About to overlap the current available Tx descriptor */ + if ((p_tx_desc_used == p_tx_desc_first) && + (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); + return ETH_END_OF_JOB; + } + + /* Pass the packet information to the caller */ + p_pkt_info->cmd_sts = command_status; + p_pkt_info->return_info = p_tx_desc_used->return_info; + p_tx_desc_used->return_info = 0; + + /* Update the next descriptor to release. */ + USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); + + /* Any Tx return cancels the Tx resource error status */ + if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) + p_eth_port_ctrl->tx_resource_err[tx_queue] = false; + + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); + + return ETH_OK; + +} + +/******************************************************************************* + * eth_port_receive - Get received information from Rx ring. + * + * DESCRIPTION: + * This routine returns the received data to the caller. There is no + * data copying during routine operation. All information is returned + * using pointer to packet information struct passed from the caller. + * If the routine exhausts Rx ring resources then the resource error flag + * is set. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE rx_queue Number of Rx queue. + * PKT_INFO *p_pkt_info User packet buffer. + * + * OUTPUT: + * Rx ring current and used indexes are updated. + * + * RETURN: + * ETH_ERROR in case the routine can not access Rx desc ring. + * ETH_QUEUE_FULL if Rx ring resources are exhausted. + * ETH_END_OF_JOB if there is no received data. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_RX_DESC *p_rx_curr_desc; + volatile ETH_RX_DESC *p_rx_next_curr_desc; + volatile ETH_RX_DESC *p_rx_used_desc; + unsigned int command_status; + + /* Do not process Rx ring in case of Rx ring resource error */ + if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { + printf ("\nRx Queue is full ...\n"); + return ETH_QUEUE_FULL; + } + + /* Get the Rx Desc ring 'curr and 'used' indexes */ + CURR_RFD_GET (p_rx_curr_desc, rx_queue); + USED_RFD_GET (p_rx_used_desc, rx_queue); + + /* Sanity check */ + if (p_rx_curr_desc == NULL) + return ETH_ERROR; + + /* The following parameters are used to save readings from memory */ + p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); + command_status = p_rx_curr_desc->cmd_sts; + + /* Nothing to receive... */ + if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { +/* DP(printf("Rx: command_status: %08x\n", command_status)); */ + D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); +/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ + return ETH_END_OF_JOB; + } + + p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; + p_pkt_info->cmd_sts = command_status; + p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; + p_pkt_info->return_info = p_rx_curr_desc->return_info; + p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ + + /* Clean the return info field to indicate that the packet has been */ + /* moved to the upper layers */ + p_rx_curr_desc->return_info = 0; + + /* Update 'curr' in data structure */ + CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); + + /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ + if (p_rx_next_curr_desc == p_rx_used_desc) + p_eth_port_ctrl->rx_resource_err[rx_queue] = true; + + D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); + CPU_PIPE_FLUSH; + return ETH_OK; +} + +/******************************************************************************* + * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. + * + * DESCRIPTION: + * This routine returns a Rx buffer back to the Rx ring. It retrieves the + * next 'used' descriptor and attached the returned buffer to it. + * In case the Rx ring was in "resource error" condition, where there are + * no available Rx resources, the function resets the resource error flag. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE rx_queue Number of Rx queue. + * PKT_INFO *p_pkt_info Information on the returned buffer. + * + * OUTPUT: + * New available Rx resource in Rx descriptor ring. + * + * RETURN: + * ETH_ERROR in case the routine can not access Rx desc ring. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * + p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ + + /* Get 'used' Rx descriptor */ + USED_RFD_GET (p_used_rx_desc, rx_queue); + + /* Sanity check */ + if (p_used_rx_desc == NULL) + return ETH_ERROR; + + p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; + p_used_rx_desc->return_info = p_pkt_info->return_info; + p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; + p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ + + /* Flush the write pipe */ + CPU_PIPE_FLUSH; + + /* Return the descriptor to DMA ownership */ + p_used_rx_desc->cmd_sts = + ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; + + /* Flush descriptor and CPU pipe */ + D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); + CPU_PIPE_FLUSH; + + /* Move the used descriptor pointer to the next descriptor */ + USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); + + /* Any Rx return cancels the Rx resource error status */ + if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) + p_eth_port_ctrl->rx_resource_err[rx_queue] = false; + + return ETH_OK; +} + +/******************************************************************************* + * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path + * + * DESCRIPTION: + * This routine sets the RX coalescing interrupt mechanism parameter. + * This parameter is a timeout counter, that counts in 64 t_clk + * chunks ; that when timeout event occurs a maskable interrupt + * occurs. + * The parameter is calculated using the tClk of the MV-643xx chip + * , and the required delay of the interrupt in usec. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet port number + * unsigned int t_clk t_clk of the MV-643xx chip in HZ units + * unsigned int delay Delay in usec + * + * OUTPUT: + * Interrupt coalescing mechanism value is set in MV-643xx chip. + * + * RETURN: + * The interrupt coalescing value set in the gigE port. + * + *******************************************************************************/ +#if 0 /* FIXME */ +static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, + unsigned int t_clk, + unsigned int delay) +{ + unsigned int coal; + + coal = ((t_clk / 1000000) * delay) / 64; + /* Set RX Coalescing mechanism */ + MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), + ((coal & 0x3fff) << 8) | + (MV_REG_READ + (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) + & 0xffc000ff)); + return coal; +} + +#endif +/******************************************************************************* + * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path + * + * DESCRIPTION: + * This routine sets the TX coalescing interrupt mechanism parameter. + * This parameter is a timeout counter, that counts in 64 t_clk + * chunks ; that when timeout event occurs a maskable interrupt + * occurs. + * The parameter is calculated using the t_cLK frequency of the + * MV-643xx chip and the required delay in the interrupt in uSec + * + * INPUT: + * ETH_PORT eth_port_num Ethernet port number + * unsigned int t_clk t_clk of the MV-643xx chip in HZ units + * unsigned int delay Delay in uSeconds + * + * OUTPUT: + * Interrupt coalescing mechanism value is set in MV-643xx chip. + * + * RETURN: + * The interrupt coalescing value set in the gigE port. + * + *******************************************************************************/ +#if 0 /* FIXME */ +static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, + unsigned int t_clk, + unsigned int delay) +{ + unsigned int coal; + + coal = ((t_clk / 1000000) * delay) / 64; + /* Set TX Coalescing mechanism */ + MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), + coal << 4); + return coal; +} +#endif + +/******************************************************************************* + * eth_b_copy - Copy bytes from source to destination + * + * DESCRIPTION: + * This function supports the eight bytes limitation on Tx buffer size. + * The routine will zero eight bytes starting from the destination address + * followed by copying bytes from the source address to the destination. + * + * INPUT: + * unsigned int src_addr 32 bit source address. + * unsigned int dst_addr 32 bit destination address. + * int byte_count Number of bytes to copy. + * + * OUTPUT: + * See description. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, + int byte_count) +{ + /* Zero the dst_addr area */ + *(unsigned int *) dst_addr = 0x0; + + while (byte_count != 0) { + *(char *) dst_addr = *(char *) src_addr; + dst_addr++; + src_addr++; + byte_count--; + } +} diff --git a/board/Marvell/db64360/mv_eth.h b/board/Marvell/db64360/mv_eth.h new file mode 100644 index 0000000..943d30b --- /dev/null +++ b/board/Marvell/db64360/mv_eth.h @@ -0,0 +1,844 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mv_eth.h - header file for the polled mode GT ethernet driver + */ + +#ifndef __DB64360_ETH_H__ +#define __DB64360_ETH_H__ + +#include +#include +#include +#include +#include +#include "mv_regs.h" +#include "../common/ppc_error_no.h" + + +/************************************************************************* +************************************************************************** +************************************************************************** +* The first part is the high level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ +#ifndef MAX_SKB_FRAGS +#define MAX_SKB_FRAGS 0 +#endif + +/* Port attributes */ +/*#define MAX_RX_QUEUE_NUM 8*/ +/*#define MAX_TX_QUEUE_NUM 8*/ +#define MAX_RX_QUEUE_NUM 1 +#define MAX_TX_QUEUE_NUM 1 + + +/* Use one TX queue and one RX queue */ +#define MV64360_TX_QUEUE_NUM 1 +#define MV64360_RX_QUEUE_NUM 1 + +/* + * Number of RX / TX descriptors on RX / TX rings. + * Note that allocating RX descriptors is done by allocating the RX + * ring AND a preallocated RX buffers (skb's) for each descriptor. + * The TX descriptors only allocates the TX descriptors ring, + * with no pre allocated TX buffers (skb's are allocated by higher layers. + */ + +/* Default TX ring size is 10 descriptors */ +#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE +#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE +#else +#define MV64360_TX_QUEUE_SIZE 4 +#endif + +/* Default RX ring size is 4 descriptors */ +#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE +#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE +#else +#define MV64360_RX_QUEUE_SIZE 4 +#endif + +#ifdef CONFIG_RX_BUFFER_SIZE +#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE +#else +#define MV64360_RX_BUFFER_SIZE 1600 +#endif + +#ifdef CONFIG_TX_BUFFER_SIZE +#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE +#else +#define MV64360_TX_BUFFER_SIZE 1600 +#endif + + +/* + * Network device statistics. Akin to the 2.0 ether stats but + * with byte counters. + */ + +struct net_device_stats +{ + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_errors; /* bad packets received */ + unsigned long tx_errors; /* packet transmit problems */ + unsigned long rx_dropped; /* no space in linux buffers */ + unsigned long tx_dropped; /* no space available in linux */ + unsigned long multicast; /* multicast packets received */ + unsigned long collisions; + + /* detailed rx_errors: */ + unsigned long rx_length_errors; + unsigned long rx_over_errors; /* receiver ring buff overflow */ + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_frame_errors; /* recv'd frame alignment error */ + unsigned long rx_fifo_errors; /* recv'r fifo overrun */ + unsigned long rx_missed_errors; /* receiver missed packet */ + + /* detailed tx_errors */ + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; + + /* for cslip etc */ + unsigned long rx_compressed; + unsigned long tx_compressed; +}; + + +/* Private data structure used for ethernet device */ +struct mv64360_eth_priv { + unsigned int port_num; + struct net_device_stats *stats; + +/* to buffer area aligned */ + char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ + char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ + + /* Size of Tx Ring per queue */ + unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; + + + /* Size of Rx Ring per queue */ + unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; + + /* Magic Number for Ethernet running */ + unsigned int eth_running; + +}; + + +int mv64360_eth_init (struct eth_device *dev); +int mv64360_eth_stop (struct eth_device *dev); +int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length); +/* return db64360_eth0_poll(); */ + +int mv64360_eth_open (struct eth_device *dev); + + +/************************************************************************* +************************************************************************** +************************************************************************** +* The second part is the low level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ + + +/******************************************************************************** + * Header File for : MV-643xx network interface header + * + * DESCRIPTION: + * This header file contains macros typedefs and function declaration for + * the Marvell Gig Bit Ethernet Controller. + * + * DEPENDENCIES: + * None. + * + *******************************************************************************/ + + +#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY +#ifdef CONFIG_MV64360_SRAM_CACHEABLE +/* In case SRAM is cacheable but not cache coherent */ +#define D_CACHE_FLUSH_LINE(addr, offset) \ +{ \ + __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ +} +#else +/* In case SRAM is cache coherent or non-cacheable */ +#define D_CACHE_FLUSH_LINE(addr, offset) ; +#endif +#else +#ifdef CONFIG_NOT_COHERENT_CACHE +/* In case of descriptors on DDR but not cache coherent */ +#define D_CACHE_FLUSH_LINE(addr, offset) \ +{ \ + __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ +} +#else +/* In case of descriptors on DDR and cache coherent */ +#define D_CACHE_FLUSH_LINE(addr, offset) ; +#endif /* CONFIG_NOT_COHERENT_CACHE */ +#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ + + +#define CPU_PIPE_FLUSH \ +{ \ + __asm__ __volatile__ ("eieio"); \ +} + + +/* defines */ + +/* Default port configuration value */ +#define PORT_CONFIG_VALUE \ + ETH_UNICAST_NORMAL_MODE | \ + ETH_DEFAULT_RX_QUEUE_0 | \ + ETH_DEFAULT_RX_ARP_QUEUE_0 | \ + ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ + ETH_RECEIVE_BC_IF_IP | \ + ETH_RECEIVE_BC_IF_ARP | \ + ETH_CAPTURE_TCP_FRAMES_DIS | \ + ETH_CAPTURE_UDP_FRAMES_DIS | \ + ETH_DEFAULT_RX_TCP_QUEUE_0 | \ + ETH_DEFAULT_RX_UDP_QUEUE_0 | \ + ETH_DEFAULT_RX_BPDU_QUEUE_0 + +/* Default port extend configuration value */ +#define PORT_CONFIG_EXTEND_VALUE \ + ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ + ETH_PARTITION_DISABLE + + +/* Default sdma control value */ +#ifdef CONFIG_NOT_COHERENT_CACHE +#define PORT_SDMA_CONFIG_VALUE \ + ETH_RX_BURST_SIZE_16_64BIT | \ + GT_ETH_IPG_INT_RX(0) | \ + ETH_TX_BURST_SIZE_16_64BIT; +#else +#define PORT_SDMA_CONFIG_VALUE \ + ETH_RX_BURST_SIZE_4_64BIT | \ + GT_ETH_IPG_INT_RX(0) | \ + ETH_TX_BURST_SIZE_4_64BIT; +#endif + +#define GT_ETH_IPG_INT_RX(value) \ + ((value & 0x3fff) << 8) + +/* Default port serial control value */ +#define PORT_SERIAL_CONTROL_VALUE \ + ETH_FORCE_LINK_PASS | \ + ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ + ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ + ETH_ADV_SYMMETRIC_FLOW_CTRL | \ + ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + ETH_FORCE_BP_MODE_NO_JAM | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL | \ + ETH_RETRANSMIT_16_ETTEMPTS | \ + ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ + ETH_DTE_ADV_0 | \ + ETH_DISABLE_AUTO_NEG_BYPASS | \ + ETH_AUTO_NEG_NO_CHANGE | \ + ETH_MAX_RX_PACKET_1552BYTE | \ + ETH_CLR_EXT_LOOPBACK | \ + ETH_SET_FULL_DUPLEX_MODE | \ + ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; + +#define RX_BUFFER_MAX_SIZE 0xFFFF +#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ + +#define RX_BUFFER_MIN_SIZE 0x8 +#define TX_BUFFER_MIN_SIZE 0x8 + +/* Tx WRR confoguration macros */ +#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ +#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ +#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ + +/* MAC accepet/reject macros */ +#define ACCEPT_MAC_ADDR 0 +#define REJECT_MAC_ADDR 1 + +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define RX_DESC_ALIGNED_SIZE 0x20 +#define TX_DESC_ALIGNED_SIZE 0x20 + +/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ +#define TX_BUF_OFFSET_IN_DESC 0x18 +/* Buffer offset from buffer pointer */ +#define RX_BUF_OFFSET 0x2 + +/* Gap define */ +#define ETH_BAR_GAP 0x8 +#define ETH_SIZE_REG_GAP 0x8 +#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 +#define ETH_PORT_ACCESS_CTRL_GAP 0x4 + +/* Gigabit Ethernet Unit Global Registers */ + +/* MIB Counters register definitions */ +#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 +#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 +#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 +#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc +#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 +#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 +#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 +#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c +#define ETH_MIB_FRAMES_64_OCTETS 0x20 +#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 +#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 +#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c +#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 +#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 +#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 +#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c +#define ETH_MIB_GOOD_FRAMES_SENT 0x40 +#define ETH_MIB_EXCESSIVE_COLLISION 0x44 +#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 +#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c +#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 +#define ETH_MIB_FC_SENT 0x54 +#define ETH_MIB_GOOD_FC_RECEIVED 0x58 +#define ETH_MIB_BAD_FC_RECEIVED 0x5c +#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 +#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 +#define ETH_MIB_OVERSIZE_RECEIVED 0x68 +#define ETH_MIB_JABBER_RECEIVED 0x6c +#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 +#define ETH_MIB_BAD_CRC_EVENT 0x74 +#define ETH_MIB_COLLISION 0x78 +#define ETH_MIB_LATE_COLLISION 0x7c + +/* Port serial status reg (PSR) */ +#define ETH_INTERFACE_GMII_MII 0 +#define ETH_INTERFACE_PCM BIT0 +#define ETH_LINK_IS_DOWN 0 +#define ETH_LINK_IS_UP BIT1 +#define ETH_PORT_AT_HALF_DUPLEX 0 +#define ETH_PORT_AT_FULL_DUPLEX BIT2 +#define ETH_RX_FLOW_CTRL_DISABLED 0 +#define ETH_RX_FLOW_CTRL_ENBALED BIT3 +#define ETH_GMII_SPEED_100_10 0 +#define ETH_GMII_SPEED_1000 BIT4 +#define ETH_MII_SPEED_10 0 +#define ETH_MII_SPEED_100 BIT5 +#define ETH_NO_TX 0 +#define ETH_TX_IN_PROGRESS BIT7 +#define ETH_BYPASS_NO_ACTIVE 0 +#define ETH_BYPASS_ACTIVE BIT8 +#define ETH_PORT_NOT_AT_PARTITION_STATE 0 +#define ETH_PORT_AT_PARTITION_STATE BIT9 +#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 +#define ETH_PORT_TX_FIFO_EMPTY BIT10 + + +/* These macros describes the Port configuration reg (Px_cR) bits */ +#define ETH_UNICAST_NORMAL_MODE 0 +#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 +#define ETH_DEFAULT_RX_QUEUE_0 0 +#define ETH_DEFAULT_RX_QUEUE_1 BIT1 +#define ETH_DEFAULT_RX_QUEUE_2 BIT2 +#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) +#define ETH_DEFAULT_RX_QUEUE_4 BIT3 +#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) +#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) +#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) +#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 +#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 +#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 +#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) +#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 +#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) +#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) +#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) +#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 +#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 +#define ETH_RECEIVE_BC_IF_IP 0 +#define ETH_REJECT_BC_IF_IP BIT8 +#define ETH_RECEIVE_BC_IF_ARP 0 +#define ETH_REJECT_BC_IF_ARP BIT9 +#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 +#define ETH_CAPTURE_TCP_FRAMES_DIS 0 +#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 +#define ETH_CAPTURE_UDP_FRAMES_DIS 0 +#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 +#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 +#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 +#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 +#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) +#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 +#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) +#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) +#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) +#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 +#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 +#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 +#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) +#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 +#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) +#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) +#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) +#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 +#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 +#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 +#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) +#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 +#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) +#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) +#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) + + +/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ +#define ETH_CLASSIFY_EN BIT0 +#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 +#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 +#define ETH_PARTITION_DISABLE 0 +#define ETH_PARTITION_ENABLE BIT2 + + +/* Tx/Rx queue command reg (RQCR/TQCR)*/ +#define ETH_QUEUE_0_ENABLE BIT0 +#define ETH_QUEUE_1_ENABLE BIT1 +#define ETH_QUEUE_2_ENABLE BIT2 +#define ETH_QUEUE_3_ENABLE BIT3 +#define ETH_QUEUE_4_ENABLE BIT4 +#define ETH_QUEUE_5_ENABLE BIT5 +#define ETH_QUEUE_6_ENABLE BIT6 +#define ETH_QUEUE_7_ENABLE BIT7 +#define ETH_QUEUE_0_DISABLE BIT8 +#define ETH_QUEUE_1_DISABLE BIT9 +#define ETH_QUEUE_2_DISABLE BIT10 +#define ETH_QUEUE_3_DISABLE BIT11 +#define ETH_QUEUE_4_DISABLE BIT12 +#define ETH_QUEUE_5_DISABLE BIT13 +#define ETH_QUEUE_6_DISABLE BIT14 +#define ETH_QUEUE_7_DISABLE BIT15 + + +/* These macros describes the Port Sdma configuration reg (SDCR) bits */ +#define ETH_RIFB BIT0 +#define ETH_RX_BURST_SIZE_1_64BIT 0 +#define ETH_RX_BURST_SIZE_2_64BIT BIT1 +#define ETH_RX_BURST_SIZE_4_64BIT BIT2 +#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) +#define ETH_RX_BURST_SIZE_16_64BIT BIT3 +#define ETH_BLM_RX_NO_SWAP BIT4 +#define ETH_BLM_RX_BYTE_SWAP 0 +#define ETH_BLM_TX_NO_SWAP BIT5 +#define ETH_BLM_TX_BYTE_SWAP 0 +#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 +#define ETH_DESCRIPTORS_NO_SWAP 0 +#define ETH_TX_BURST_SIZE_1_64BIT 0 +#define ETH_TX_BURST_SIZE_2_64BIT BIT22 +#define ETH_TX_BURST_SIZE_4_64BIT BIT23 +#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) +#define ETH_TX_BURST_SIZE_16_64BIT BIT24 + + +/* These macros describes the Port serial control reg (PSCR) bits */ +#define ETH_SERIAL_PORT_DISABLE 0 +#define ETH_SERIAL_PORT_ENABLE BIT0 +#define ETH_FORCE_LINK_PASS BIT1 +#define ETH_DO_NOT_FORCE_LINK_PASS 0 +#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 +#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 +#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 +#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 +#define ETH_ADV_NO_FLOW_CTRL 0 +#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 +#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 +#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 +#define ETH_FORCE_BP_MODE_NO_JAM 0 +#define ETH_FORCE_BP_MODE_JAM_TX BIT7 +#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 +#define ETH_FORCE_LINK_FAIL 0 +#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 +#define ETH_RETRANSMIT_16_ETTEMPTS 0 +#define ETH_RETRANSMIT_FOREVER BIT11 +#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 +#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 +#define ETH_DTE_ADV_0 0 +#define ETH_DTE_ADV_1 BIT14 +#define ETH_DISABLE_AUTO_NEG_BYPASS 0 +#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 +#define ETH_AUTO_NEG_NO_CHANGE 0 +#define ETH_RESTART_AUTO_NEG BIT16 +#define ETH_MAX_RX_PACKET_1518BYTE 0 +#define ETH_MAX_RX_PACKET_1522BYTE BIT17 +#define ETH_MAX_RX_PACKET_1552BYTE BIT18 +#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) +#define ETH_MAX_RX_PACKET_9192BYTE BIT19 +#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) +#define ETH_SET_EXT_LOOPBACK BIT20 +#define ETH_CLR_EXT_LOOPBACK 0 +#define ETH_SET_FULL_DUPLEX_MODE BIT21 +#define ETH_SET_HALF_DUPLEX_MODE 0 +#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 +#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 +#define ETH_SET_GMII_SPEED_TO_10_100 0 +#define ETH_SET_GMII_SPEED_TO_1000 BIT23 +#define ETH_SET_MII_SPEED_TO_10 0 +#define ETH_SET_MII_SPEED_TO_100 BIT24 + + +/* SMI reg */ +#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ +#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ +#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ +#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ + +/* SDMA command status fields macros */ + +/* Tx & Rx descriptors status */ +#define ETH_ERROR_SUMMARY (BIT0) + +/* Tx & Rx descriptors command */ +#define ETH_BUFFER_OWNED_BY_DMA (BIT31) + +/* Tx descriptors status */ +#define ETH_LC_ERROR (0 ) +#define ETH_UR_ERROR (BIT1 ) +#define ETH_RL_ERROR (BIT2 ) +#define ETH_LLC_SNAP_FORMAT (BIT9 ) + +/* Rx descriptors status */ +#define ETH_CRC_ERROR (0 ) +#define ETH_OVERRUN_ERROR (BIT1 ) +#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) +#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) +#define ETH_VLAN_TAGGED (BIT19) +#define ETH_BPDU_FRAME (BIT20) +#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) +#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) +#define ETH_OTHER_FRAME_TYPE (BIT22) +#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) +#define ETH_FRAME_TYPE_IP_V_4 (BIT24) +#define ETH_FRAME_HEADER_OK (BIT25) +#define ETH_RX_LAST_DESC (BIT26) +#define ETH_RX_FIRST_DESC (BIT27) +#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) +#define ETH_RX_ENABLE_INTERRUPT (BIT29) +#define ETH_LAYER_4_CHECKSUM_OK (BIT30) + +/* Rx descriptors byte count */ +#define ETH_FRAME_FRAGMENTED (BIT2) + +/* Tx descriptors command */ +#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) +#define ETH_FRAME_SET_TO_VLAN (BIT15) +#define ETH_TCP_FRAME (0 ) +#define ETH_UDP_FRAME (BIT16) +#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) +#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) +#define ETH_ZERO_PADDING (BIT19) +#define ETH_TX_LAST_DESC (BIT20) +#define ETH_TX_FIRST_DESC (BIT21) +#define ETH_GEN_CRC (BIT22) +#define ETH_TX_ENABLE_INTERRUPT (BIT23) +#define ETH_AUTO_MODE (BIT30) + +/* Address decode parameters */ +/* Ethernet Base Address Register bits */ +#define EBAR_TARGET_DRAM 0x00000000 +#define EBAR_TARGET_DEVICE 0x00000001 +#define EBAR_TARGET_CBS 0x00000002 +#define EBAR_TARGET_PCI0 0x00000003 +#define EBAR_TARGET_PCI1 0x00000004 +#define EBAR_TARGET_CUNIT 0x00000005 +#define EBAR_TARGET_AUNIT 0x00000006 +#define EBAR_TARGET_GUNIT 0x00000007 + +/* Window attributes */ +#define EBAR_ATTR_DRAM_CS0 0x00000E00 +#define EBAR_ATTR_DRAM_CS1 0x00000D00 +#define EBAR_ATTR_DRAM_CS2 0x00000B00 +#define EBAR_ATTR_DRAM_CS3 0x00000700 + +/* DRAM Target interface */ +#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 +#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 +#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 + +/* Device Bus Target interface */ +#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 +#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 +#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 +#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 +#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 + +/* PCI Target interface */ +#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 +#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 +#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 +#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 +#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 +#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 +#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 +#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 +#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 +#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 + +/* CPU 60x bus or internal SRAM interface */ +#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 +#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 +#define EBAR_ATTR_CBS_SRAM 0x00000000 +#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 + +/* Window access control */ +#define EWIN_ACCESS_NOT_ALLOWED 0 +#define EWIN_ACCESS_READ_ONLY BIT0 +#define EWIN_ACCESS_FULL (BIT1 | BIT0) +#define EWIN0_ACCESS_MASK 0x0003 +#define EWIN1_ACCESS_MASK 0x000C +#define EWIN2_ACCESS_MASK 0x0030 +#define EWIN3_ACCESS_MASK 0x00C0 + +/* typedefs */ + +typedef enum _eth_port +{ + ETH_0 = 0, + ETH_1 = 1, + ETH_2 = 2 +}ETH_PORT; + +typedef enum _eth_func_ret_status +{ + ETH_OK, /* Returned as expected. */ + ETH_ERROR, /* Fundamental error. */ + ETH_RETRY, /* Could not process request. Try later. */ + ETH_END_OF_JOB, /* Ring has nothing to process. */ + ETH_QUEUE_FULL, /* Ring resource error. */ + ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ +}ETH_FUNC_RET_STATUS; + +typedef enum _eth_queue +{ + ETH_Q0 = 0, + ETH_Q1 = 1, + ETH_Q2 = 2, + ETH_Q3 = 3, + ETH_Q4 = 4, + ETH_Q5 = 5, + ETH_Q6 = 6, + ETH_Q7 = 7 +} ETH_QUEUE; + +typedef enum _addr_win +{ + ETH_WIN0, + ETH_WIN1, + ETH_WIN2, + ETH_WIN3, + ETH_WIN4, + ETH_WIN5 +} ETH_ADDR_WIN; + +typedef enum _eth_target +{ + ETH_TARGET_DRAM , + ETH_TARGET_DEVICE, + ETH_TARGET_CBS , + ETH_TARGET_PCI0 , + ETH_TARGET_PCI1 +}ETH_TARGET; + +typedef struct _eth_rx_desc +{ + unsigned short byte_cnt ; /* Descriptor buffer byte count */ + unsigned short buf_size ; /* Buffer size */ + unsigned int cmd_sts ; /* Descriptor command status */ + unsigned int next_desc_ptr; /* Next descriptor pointer */ + unsigned int buf_ptr ; /* Descriptor buffer pointer */ + unsigned int return_info ; /* User resource return information */ +} ETH_RX_DESC; + + +typedef struct _eth_tx_desc +{ + unsigned short byte_cnt ; /* Descriptor buffer byte count */ + unsigned short l4i_chk ; /* CPU provided TCP Checksum */ + unsigned int cmd_sts ; /* Descriptor command status */ + unsigned int next_desc_ptr; /* Next descriptor pointer */ + unsigned int buf_ptr ; /* Descriptor buffer pointer */ + unsigned int return_info ; /* User resource return information */ +} ETH_TX_DESC; + +/* Unified struct for Rx and Tx operations. The user is not required to */ +/* be familier with neither Tx nor Rx descriptors. */ +typedef struct _pkt_info +{ + unsigned short byte_cnt ; /* Descriptor buffer byte count */ + unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ + unsigned int cmd_sts ; /* Descriptor command status */ + unsigned int buf_ptr ; /* Descriptor buffer pointer */ + unsigned int return_info ; /* User resource return information */ +} PKT_INFO; + + +typedef struct _eth_win_param +{ + ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ + ETH_TARGET target; /* System targets. See ETH_TARGET enum */ + unsigned short attributes; /* BAR attributes. See above macros. */ + unsigned int base_addr; /* Window base address in unsigned int form */ + unsigned int high_addr; /* Window high address in unsigned int form */ + unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ + bool enable; /* Enable/disable access to the window. */ + unsigned short access_ctrl; /* Access ctrl register. see above macros */ +} ETH_WIN_PARAM; + + +/* Ethernet port specific infomation */ + +typedef struct _eth_port_ctrl +{ + ETH_PORT port_num; /* User Ethernet port number */ + int port_phy_addr; /* User phy address of Ethrnet port */ + unsigned char port_mac_addr[6]; /* User defined port MAC address. */ + unsigned int port_config; /* User port configuration value */ + unsigned int port_config_extend; /* User port config extend value */ + unsigned int port_sdma_config; /* User port SDMA config value */ + unsigned int port_serial_control; /* User port serial control value */ + unsigned int port_tx_queue_command; /* Port active Tx queues summary */ + unsigned int port_rx_queue_command; /* Port active Rx queues summary */ + + /* User function to cast virtual address to CPU bus address */ + unsigned int (*port_virt_to_phys)(unsigned int addr); + /* User scratch pad for user specific data structures */ + void *port_private; + + bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ + bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ + + /* Tx/Rx rings managment indexes fields. For driver use */ + + /* Next available Rx resource */ + volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; + /* Returning Rx resource */ + volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; + + /* Next available Tx resource */ + volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; + /* Returning Tx resource */ + volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; + /* An extra Tx index to support transmit of multiple buffers per packet */ + volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; + + /* Tx/Rx rings size and base variables fields. For driver use */ + + volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; + unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; + char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; + + volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; + unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; + char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; + +} ETH_PORT_INFO; + + +/* ethernet.h API list */ + +/* Port operation control routines */ +static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); +static void eth_port_reset(ETH_PORT eth_port_num); +static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); + + +/* Port MAC address routines */ +static void eth_port_uc_addr_set (ETH_PORT eth_port_num, + unsigned char *p_addr, + ETH_QUEUE queue); +#if 0 /* FIXME */ +static void eth_port_mc_addr (ETH_PORT eth_port_num, + unsigned char *p_addr, + ETH_QUEUE queue, + int option); +#endif + +/* PHY and MIB routines */ +static bool ethernet_phy_reset(ETH_PORT eth_port_num); + +static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, + unsigned int phy_reg, + unsigned int value); + +static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, + unsigned int phy_reg, + unsigned int* value); + +static void eth_clear_mib_counters(ETH_PORT eth_port_num); + +/* Port data flow control routines */ +static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO *p_pkt_info); +static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO *p_pkt_info); +static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO *p_pkt_info); +static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO *p_pkt_info); + + +static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE tx_queue, + int tx_desc_num, + int tx_buff_size, + unsigned int tx_desc_base_addr, + unsigned int tx_buff_base_addr); + +static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE rx_queue, + int rx_desc_num, + int rx_buff_size, + unsigned int rx_desc_base_addr, + unsigned int rx_buff_base_addr); + +#endif /* MV64360_ETH_ */ diff --git a/board/Marvell/db64360/mv_regs.h b/board/Marvell/db64360/mv_regs.h new file mode 100644 index 0000000..0d6370b --- /dev/null +++ b/board/Marvell/db64360/mv_regs.h @@ -0,0 +1,1124 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/******************************************************************************** +* gt64360r.h - GT-64360 Internal registers definition file. +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv_regsh +#define __INCmv_regsh + +#define MV64360 + +/* Supported by the Atlantis */ +#define MV64360_INCLUDE_PCI_1 +#define MV64360_INCLUDE_PCI_0_ARBITER +#define MV64360_INCLUDE_PCI_1_ARBITER +#define MV64360_INCLUDE_SNOOP_SUPPORT +#define MV64360_INCLUDE_P2P +#define MV64360_INCLUDE_ETH_PORT_2 +#define MV64360_INCLUDE_CPU_MAPPING +#define MV64360_INCLUDE_MPSC + +/* Not supported features */ +#undef INCLUDE_CNTMR_4_7 +#undef INCLUDE_DMA_4_7 + +/****************************************/ +/* Processor Address Space */ +/****************************************/ + +/* DDR SDRAM BAR and size registers */ + +#define MV64360_CS_0_BASE_ADDR 0x008 +#define MV64360_CS_0_SIZE 0x010 +#define MV64360_CS_1_BASE_ADDR 0x208 +#define MV64360_CS_1_SIZE 0x210 +#define MV64360_CS_2_BASE_ADDR 0x018 +#define MV64360_CS_2_SIZE 0x020 +#define MV64360_CS_3_BASE_ADDR 0x218 +#define MV64360_CS_3_SIZE 0x220 + +/* Devices BAR and size registers */ + +#define MV64360_DEV_CS0_BASE_ADDR 0x028 +#define MV64360_DEV_CS0_SIZE 0x030 +#define MV64360_DEV_CS1_BASE_ADDR 0x228 +#define MV64360_DEV_CS1_SIZE 0x230 +#define MV64360_DEV_CS2_BASE_ADDR 0x248 +#define MV64360_DEV_CS2_SIZE 0x250 +#define MV64360_DEV_CS3_BASE_ADDR 0x038 +#define MV64360_DEV_CS3_SIZE 0x040 +#define MV64360_BOOTCS_BASE_ADDR 0x238 +#define MV64360_BOOTCS_SIZE 0x240 + +/* PCI 0 BAR and size registers */ + +#define MV64360_PCI_0_IO_BASE_ADDR 0x048 +#define MV64360_PCI_0_IO_SIZE 0x050 +#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058 +#define MV64360_PCI_0_MEMORY0_SIZE 0x060 +#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080 +#define MV64360_PCI_0_MEMORY1_SIZE 0x088 +#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258 +#define MV64360_PCI_0_MEMORY2_SIZE 0x260 +#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280 +#define MV64360_PCI_0_MEMORY3_SIZE 0x288 + +/* PCI 1 BAR and size registers */ +#define MV64360_PCI_1_IO_BASE_ADDR 0x090 +#define MV64360_PCI_1_IO_SIZE 0x098 +#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0 +#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8 +#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0 +#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8 +#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0 +#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8 +#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0 +#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8 + +/* SRAM base address */ +#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268 + +/* internal registers space base address */ +#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068 + +/* Enables the CS , DEV_CS , PCI 0 and PCI 1 + windows above */ +#define MV64360_BASE_ADDR_ENABLE 0x278 + +/****************************************/ +/* PCI remap registers */ +/****************************************/ + /* PCI 0 */ +#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0 +#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 +#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 +#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 +#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 +#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 +#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 +#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 +#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 + /* PCI 1 */ +#define MV64360_PCI_1_IO_ADDR_REMAP 0x108 +#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 +#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 +#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 +#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 +#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 +#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 +#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 +#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 + +#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 +#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 +#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 +#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 +#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 +#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 +#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 +#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 + +/****************************************/ +/* CPU Control Registers */ +/****************************************/ + +#define MV64360_CPU_CONFIG 0x000 +#define MV64360_CPU_MODE 0x120 +#define MV64360_CPU_MASTER_CONTROL 0x160 +#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150 +#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158 +#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168 + +/****************************************/ +/* SMP RegisterS */ +/****************************************/ + +#define MV64360_SMP_WHO_AM_I 0x200 +#define MV64360_SMP_CPU0_DOORBELL 0x214 +#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C +#define MV64360_SMP_CPU1_DOORBELL 0x224 +#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C +#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234 +#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C +#define MV64360_SMP_SEMAPHOR0 0x244 +#define MV64360_SMP_SEMAPHOR1 0x24c +#define MV64360_SMP_SEMAPHOR2 0x254 +#define MV64360_SMP_SEMAPHOR3 0x25c +#define MV64360_SMP_SEMAPHOR4 0x264 +#define MV64360_SMP_SEMAPHOR5 0x26c +#define MV64360_SMP_SEMAPHOR6 0x274 +#define MV64360_SMP_SEMAPHOR7 0x27c + +/****************************************/ +/* CPU Sync Barrier Register */ +/****************************************/ + +#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 +#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 +#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 +#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 + +/****************************************/ +/* CPU Access Protect */ +/****************************************/ + +#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 +#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188 +#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 +#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198 +#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 +#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 +#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 +#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 + + +/****************************************/ +/* CPU Error Report */ +/****************************************/ + +#define MV64360_CPU_ERROR_ADDR_LOW 0x070 +#define MV64360_CPU_ERROR_ADDR_HIGH 0x078 +#define MV64360_CPU_ERROR_DATA_LOW 0x128 +#define MV64360_CPU_ERROR_DATA_HIGH 0x130 +#define MV64360_CPU_ERROR_PARITY 0x138 +#define MV64360_CPU_ERROR_CAUSE 0x140 +#define MV64360_CPU_ERROR_MASK 0x148 + +/****************************************/ +/* CPU Interface Debug Registers */ +/****************************************/ + +#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360 +#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368 +#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370 +#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378 +#define MV64360_PUNIT_MMASK 0x3e4 + +/****************************************/ +/* Integrated SRAM Registers */ +/****************************************/ + +#define MV64360_SRAM_CONFIG 0x380 +#define MV64360_SRAM_TEST_MODE 0X3F4 +#define MV64360_SRAM_ERROR_CAUSE 0x388 +#define MV64360_SRAM_ERROR_ADDR 0x390 +#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8 +#define MV64360_SRAM_ERROR_DATA_LOW 0x398 +#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0 +#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8 + +/****************************************/ +/* SDRAM Configuration */ +/****************************************/ + +#define MV64360_SDRAM_CONFIG 0x1400 +#define MV64360_D_UNIT_CONTROL_LOW 0x1404 +#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 +#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408 +#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c +#define MV64360_SDRAM_ADDR_CONTROL 0x1410 +#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414 +#define MV64360_SDRAM_OPERATION 0x1418 +#define MV64360_SDRAM_MODE 0x141c +#define MV64360_EXTENDED_DRAM_MODE 0x1420 +#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 +#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 +#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438 +#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 +#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4 + +/****************************************/ +/* SDRAM Error Report */ +/****************************************/ + +#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444 +#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440 +#define MV64360_SDRAM_ERROR_ADDR 0x1450 +#define MV64360_SDRAM_RECEIVED_ECC 0x1448 +#define MV64360_SDRAM_CALCULATED_ECC 0x144c +#define MV64360_SDRAM_ECC_CONTROL 0x1454 +#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458 + +/******************************************/ +/* Controlled Delay Line (CDL) Registers */ +/******************************************/ + +#define MV64360_DFCDL_CONFIG0 0x1480 +#define MV64360_DFCDL_CONFIG1 0x1484 +#define MV64360_DLL_WRITE 0x1488 +#define MV64360_DLL_READ 0x148c +#define MV64360_SRAM_ADDR 0x1490 +#define MV64360_SRAM_DATA0 0x1494 +#define MV64360_SRAM_DATA1 0x1498 +#define MV64360_SRAM_DATA2 0x149c +#define MV64360_DFCL_PROBE 0x14a0 + +/******************************************/ +/* Debug Registers */ +/******************************************/ + +#define MV64360_DUNIT_DEBUG_LOW 0x1460 +#define MV64360_DUNIT_DEBUG_HIGH 0x1464 +#define MV64360_DUNIT_MMASK 0X1b40 + +/****************************************/ +/* Device Parameters */ +/****************************************/ + +#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c +#define MV64360_DEVICE_BANK1_PARAMETERS 0x460 +#define MV64360_DEVICE_BANK2_PARAMETERS 0x464 +#define MV64360_DEVICE_BANK3_PARAMETERS 0x468 +#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c +#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0 +#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 +#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc +#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 + +/****************************************/ +/* Device interrupt registers */ +/****************************************/ + +#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0 +#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4 +#define MV64360_DEVICE_ERROR_ADDR 0x4d8 +#define MV64360_DEVICE_ERROR_DATA 0x4dc +#define MV64360_DEVICE_ERROR_PARITY 0x4e0 + +/****************************************/ +/* Device debug registers */ +/****************************************/ + +#define MV64360_DEVICE_DEBUG_LOW 0x4e4 +#define MV64360_DEVICE_DEBUG_HIGH 0x4e8 +#define MV64360_RUNIT_MMASK 0x4f0 + +/****************************************/ +/* PCI Slave Address Decoding registers */ +/****************************************/ + +#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08 +#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88 +#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08 +#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88 +#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c +#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c +#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c +#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c +#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10 +#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90 +#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10 +#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90 +#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18 +#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98 +#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14 +#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94 +#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 +#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 +#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c +#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c +#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 +#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 +#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24 +#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4 +#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28 +#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8 +#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 +#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 +#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c +#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c +#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c +#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc +#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 +#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 +#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 +#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 +#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c +#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc +#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c +#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc +#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 +#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 +#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 +#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 +#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C +#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C +#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 +#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 +#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 +#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 +#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 +#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 +#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 +#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 +#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 +#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 +#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 +#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 +#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c +#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc +#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 +#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 +#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 +#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 +#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 +#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 +#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c +#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec +#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 +#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 +#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 +#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 +#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 +#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 +#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 +#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 +#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c +#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc +#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 +#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 +#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44 +#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4 +#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48 +#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 + +/***********************************/ +/* PCI Control Register Map */ +/***********************************/ + +#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 +#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 +#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C +#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C +#define MV64360_PCI_0_COMMAND 0xc00 +#define MV64360_PCI_1_COMMAND 0xc80 +#define MV64360_PCI_0_MODE 0xd00 +#define MV64360_PCI_1_MODE 0xd80 +#define MV64360_PCI_0_RETRY 0xc04 +#define MV64360_PCI_1_RETRY 0xc84 +#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 +#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 +#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38 +#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8 +#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00 +#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80 +#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 +#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 +#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c +#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c +#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 +#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 +#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 +#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 +#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 +#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 +#define MV64360_PCI_0_P2P_CONFIG 0x1d14 +#define MV64360_PCI_1_P2P_CONFIG 0x1d94 + +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 + +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 + +/****************************************/ +/* PCI Configuration Access Registers */ +/****************************************/ + +#define MV64360_PCI_0_CONFIG_ADDR 0xcf8 +#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc +#define MV64360_PCI_1_CONFIG_ADDR 0xc78 +#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c +#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 +#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 + +/****************************************/ +/* PCI Error Report Registers */ +/****************************************/ + +#define MV64360_PCI_0_SERR_MASK 0xc28 +#define MV64360_PCI_1_SERR_MASK 0xca8 +#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40 +#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0 +#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44 +#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4 +#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48 +#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8 +#define MV64360_PCI_0_ERROR_COMMAND 0x1d50 +#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0 +#define MV64360_PCI_0_ERROR_CAUSE 0x1d58 +#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8 +#define MV64360_PCI_0_ERROR_MASK 0x1d5c +#define MV64360_PCI_1_ERROR_MASK 0x1ddc + +/****************************************/ +/* PCI Debug Registers */ +/****************************************/ + +#define MV64360_PCI_0_MMASK 0X1D24 +#define MV64360_PCI_1_MMASK 0X1DA4 + +/*********************************************/ +/* PCI Configuration, Function 0, Registers */ +/*********************************************/ + +#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000 +#define MV64360_PCI_STATUS_AND_COMMAND 0x004 +#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C + +#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010 +#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014 +#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018 +#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C +#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 +#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 +#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c +#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034 +#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C + /* capability list */ +#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define MV64360_PCI_VPD_ADDR 0x048 +#define MV64360_PCI_VPD_DATA 0x04c +#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050 +#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054 +#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 +#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c +#define MV64360_PCI_X_COMMAND 0x060 +#define MV64360_PCI_X_STATUS 0x064 +#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068 + +/***********************************************/ +/* PCI Configuration, Function 1, Registers */ +/***********************************************/ + +#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110 +#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114 +#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118 +#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c +#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 +#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 + +/***********************************************/ +/* PCI Configuration, Function 2, Registers */ +/***********************************************/ + +#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 +#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 +#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 +#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c +#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 +#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 3, Registers */ +/***********************************************/ + +#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 +#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 +#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 +#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c +#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220 +#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 4, Registers */ +/***********************************************/ + +#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 +#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 +#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 +#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c +#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420 +#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 + +/****************************************/ +/* Messaging Unit Registers (I20) */ +/****************************************/ + +#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 +#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C +#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 +#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 +#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 +#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C +#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 +#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 +#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 +#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 +#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 +#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 +#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 +#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 +#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 +#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C +#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 +#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 +#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 +#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC + +#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 +#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C +#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 +#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 +#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 +#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC +#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 +#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 +#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 +#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 +#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 +#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 +#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 +#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 +#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 +#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC +#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 +#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 +#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 +#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C + +#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 +#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C +#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 +#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 +#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 +#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C +#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 +#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 +#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 +#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 +#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 +#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 +#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 +#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 +#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 +#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C +#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 +#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 +#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 +#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC +#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 +#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C +#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 +#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 +#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 +#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC +#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 +#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 +#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 +#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 +#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 +#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 +#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 +#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 +#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 +#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC +#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 +#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 +#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 +#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ + +#define MV64360_ETH_PHY_ADDR_REG 0x2000 +#define MV64360_ETH_SMI_REG 0x2004 +#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 +#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c +#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 +#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 +#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc +#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094 +#define MV64360_ETH_BAR_0 0x2200 +#define MV64360_ETH_BAR_1 0x2208 +#define MV64360_ETH_BAR_2 0x2210 +#define MV64360_ETH_BAR_3 0x2218 +#define MV64360_ETH_BAR_4 0x2220 +#define MV64360_ETH_BAR_5 0x2228 +#define MV64360_ETH_SIZE_REG_0 0x2204 +#define MV64360_ETH_SIZE_REG_1 0x220c +#define MV64360_ETH_SIZE_REG_2 0x2214 +#define MV64360_ETH_SIZE_REG_3 0x221c +#define MV64360_ETH_SIZE_REG_4 0x2224 +#define MV64360_ETH_SIZE_REG_5 0x222c +#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230 +#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 +#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 +#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 +#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 +#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c +#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290 +#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) +#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) +#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) +#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) +#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) +#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) +#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) +#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) +#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) +#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) +#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10)) +#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10)) +#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10)) +#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10)) +#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10)) +#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10)) +#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10)) +#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) +#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) +#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) +#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) +#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) +#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) +#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) +#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) +#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) +#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) +#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) +#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) +#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) +#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) +#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) +#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) +#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) +#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) +#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) +#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) +#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) +#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) +#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) +#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) +#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) +#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) + +/*******************************************/ +/* CUNIT Registers */ +/*******************************************/ + + /* Address Decoding Register Map */ + +#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200 +#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208 +#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210 +#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218 +#define MV64360_CUNIT_SIZE0 0xf204 +#define MV64360_CUNIT_SIZE1 0xf20c +#define MV64360_CUNIT_SIZE2 0xf214 +#define MV64360_CUNIT_SIZE3 0xf21c +#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 +#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 +#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 +#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254 +#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258 +#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C + + /* Error Report Registers */ + +#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310 +#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314 +#define MV64360_CUNIT_ERROR_ADDR 0xf318 + + /* Cunit Control Registers */ + +#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300 +#define MV64360_CUNIT_CONFIG_REG 0xb40c +#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 + + /* Cunit Debug Registers */ + +#define MV64360_CUNIT_DEBUG_LOW 0xf340 +#define MV64360_CUNIT_DEBUG_HIGH 0xf344 +#define MV64360_CUNIT_MMASK 0xf380 + + /* Cunit Base Address Enable Window Bits*/ +#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 +#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 +#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 +#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 + + /* MPSCs Clocks Routing Registers */ + +#define MV64360_MPSC_ROUTING_REG 0xb400 +#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404 +#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408 + + /* MPSCs Interrupts Registers */ + +#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) +#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3)) + +#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) +#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) +#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) + + /* MPSC0 Registers */ + + +/***************************************/ +/* SDMA Registers */ +/***************************************/ + +#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) +#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) +#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) +#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) +#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) + +#define MV64360_SDMA_CAUSE_REG 0xb800 +#define MV64360_SDMA_MASK_REG 0xb880 + + +/****************************************/ +/* SDMA Address Space Targets */ +/****************************************/ + +#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00 +#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00 +#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00 +#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700 + +#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01 +#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01 +#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01 +#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701 + +#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00 + +#define MV64360_SDMA_SRAM_TARGET 0x0003 +#define MV64360_SDMA_60X_BUS_TARGET 0x4003 + +#define MV64360_PCI_0_TARGET 0x0003 +#define MV64360_PCI_1_TARGET 0x0004 + + +/* Devices BAR and size registers */ + +#define MV64360_DEV_CS0_BASE_ADDR 0x028 +#define MV64360_DEV_CS0_SIZE 0x030 +#define MV64360_DEV_CS1_BASE_ADDR 0x228 +#define MV64360_DEV_CS1_SIZE 0x230 +#define MV64360_DEV_CS2_BASE_ADDR 0x248 +#define MV64360_DEV_CS2_SIZE 0x250 +#define MV64360_DEV_CS3_BASE_ADDR 0x038 +#define MV64360_DEV_CS3_SIZE 0x040 +#define MV64360_BOOTCS_BASE_ADDR 0x238 +#define MV64360_BOOTCS_SIZE 0x240 + +/* SDMA Window access protection */ +#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0 +#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1 +#define MV64360_SDMA_WIN_ACCESS_FULL 2 + +/* BRG Interrupts */ + +#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) +#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) +#define MV64360_BRG_CAUSE_REG 0xb834 +#define MV64360_BRG_MASK_REG 0xb8b4 + +/****************************************/ +/* DMA Channel Control */ +/****************************************/ + +#define MV64360_DMA_CHANNEL0_CONTROL 0x840 +#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880 +#define MV64360_DMA_CHANNEL1_CONTROL 0x844 +#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884 +#define MV64360_DMA_CHANNEL2_CONTROL 0x848 +#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888 +#define MV64360_DMA_CHANNEL3_CONTROL 0x84C +#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C + + +/****************************************/ +/* IDMA Registers */ +/****************************************/ + +#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800 +#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804 +#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808 +#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C +#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810 +#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814 +#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818 +#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c +#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820 +#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824 +#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828 +#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C +#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 +#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 +#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 +#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C +#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 +#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 +#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 +#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C + + /* IDMA Address Decoding Base Address Registers */ + +#define MV64360_DMA_BASE_ADDR_REG0 0xa00 +#define MV64360_DMA_BASE_ADDR_REG1 0xa08 +#define MV64360_DMA_BASE_ADDR_REG2 0xa10 +#define MV64360_DMA_BASE_ADDR_REG3 0xa18 +#define MV64360_DMA_BASE_ADDR_REG4 0xa20 +#define MV64360_DMA_BASE_ADDR_REG5 0xa28 +#define MV64360_DMA_BASE_ADDR_REG6 0xa30 +#define MV64360_DMA_BASE_ADDR_REG7 0xa38 + + /* IDMA Address Decoding Size Address Register */ + +#define MV64360_DMA_SIZE_REG0 0xa04 +#define MV64360_DMA_SIZE_REG1 0xa0c +#define MV64360_DMA_SIZE_REG2 0xa14 +#define MV64360_DMA_SIZE_REG3 0xa1c +#define MV64360_DMA_SIZE_REG4 0xa24 +#define MV64360_DMA_SIZE_REG5 0xa2c +#define MV64360_DMA_SIZE_REG6 0xa34 +#define MV64360_DMA_SIZE_REG7 0xa3C + + /* IDMA Address Decoding High Address Remap and Access + Protection Registers */ + +#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60 +#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64 +#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68 +#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C +#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80 +#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 +#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 +#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 +#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c +#define MV64360_DMA_ARBITER_CONTROL 0x860 +#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0 + + /* IDMA Headers Retarget Registers */ + +#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84 +#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88 + + /* IDMA Interrupt Register */ + +#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0 +#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4 +#define MV64360_DMA_ERROR_ADDR 0x8c8 +#define MV64360_DMA_ERROR_SELECT 0x8cc + + /* IDMA Debug Register ( for internal use ) */ + +#define MV64360_DMA_DEBUG_LOW 0x8e0 +#define MV64360_DMA_DEBUG_HIGH 0x8e4 +#define MV64360_DMA_SPARE 0xA8C + +/****************************************/ +/* Timer_Counter */ +/****************************************/ + +#define MV64360_TIMER_COUNTER0 0x850 +#define MV64360_TIMER_COUNTER1 0x854 +#define MV64360_TIMER_COUNTER2 0x858 +#define MV64360_TIMER_COUNTER3 0x85C +#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864 +#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 +#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c + +/****************************************/ +/* Watchdog registers */ +/****************************************/ + +#define MV64360_WATCHDOG_CONFIG_REG 0xb410 +#define MV64360_WATCHDOG_VALUE_REG 0xb414 + +/****************************************/ +/* I2C Registers */ +/****************************************/ + +#define MV64360_I2C_SLAVE_ADDR 0xc000 +#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010 +#define MV64360_I2C_DATA 0xc004 +#define MV64360_I2C_CONTROL 0xc008 +#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C +#define MV64360_I2C_SOFT_RESET 0xc01c + +/****************************************/ +/* GPP Interface Registers */ +/****************************************/ + +#define MV64360_GPP_IO_CONTROL 0xf100 +#define MV64360_GPP_LEVEL_CONTROL 0xf110 +#define MV64360_GPP_VALUE 0xf104 +#define MV64360_GPP_INTERRUPT_CAUSE 0xf108 +#define MV64360_GPP_INTERRUPT_MASK0 0xf10c +#define MV64360_GPP_INTERRUPT_MASK1 0xf114 +#define MV64360_GPP_VALUE_SET 0xf118 +#define MV64360_GPP_VALUE_CLEAR 0xf11c + +/****************************************/ +/* Interrupt Controller Registers */ +/****************************************/ + +/****************************************/ +/* Interrupts */ +/****************************************/ + +#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004 +#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c +#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014 +#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c +#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024 +#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034 +#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c +#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044 +#define MV64360_INTERRUPT0_MASK_0_LOW 0x054 +#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c +#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064 +#define MV64360_INTERRUPT1_MASK_0_LOW 0x074 +#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c +#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084 + +/****************************************/ +/* MPP Interface Registers */ +/****************************************/ + +#define MV64360_MPP_CONTROL0 0xf000 +#define MV64360_MPP_CONTROL1 0xf004 +#define MV64360_MPP_CONTROL2 0xf008 +#define MV64360_MPP_CONTROL3 0xf00c + +/****************************************/ +/* Serial Initialization registers */ +/****************************************/ + +#define MV64360_SERIAL_INIT_LAST_DATA 0xf324 +#define MV64360_SERIAL_INIT_CONTROL 0xf328 +#define MV64360_SERIAL_INIT_STATUS 0xf32c + + +#endif /* __INCgt64360rh */ diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c new file mode 100644 index 0000000..5637284 --- /dev/null +++ b/board/Marvell/db64360/pci.c @@ -0,0 +1,940 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* PCI.c - PCI functions */ + + +#include +#include + +#include "../include/pci.h" + +#undef DEBUG +#undef IDE_SET_NATIVE_MODE +static unsigned int local_buses[] = { 0, 0 }; + +static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { + {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, + {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, +}; + + +#ifdef DEBUG +static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; +static void gt_pci_bus_mode_display (PCI_HOST host) +{ + unsigned int mode; + + + mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; + switch (mode) { + case 0: + printf ("PCI %d bus mode: Conventional PCI\n", host); + break; + case 1: + printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + break; + case 2: + printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + break; + case 3: + printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + break; + default: + printf ("Unknown BUS %d\n", mode); + } +} +#endif + +static const unsigned int pci_p2p_configuration_reg[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION +}; + +static const unsigned int pci_configuration_address[] = { + PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS +}; + +static const unsigned int pci_configuration_data[] = { + PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, + PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER +}; + +static const unsigned int pci_error_cause_reg[] = { + PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE +}; + +static const unsigned int pci_arbiter_control[] = { + PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL +}; + +static const unsigned int pci_address_space_en[] = { + PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE +}; + +static const unsigned int pci_snoop_control_base_0_low[] = { + PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW +}; +static const unsigned int pci_snoop_control_top_0[] = { + PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 +}; + +static const unsigned int pci_access_control_base_0_low[] = { + PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW +}; +static const unsigned int pci_access_control_top_0[] = { + PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 +}; + +static const unsigned int pci_scs_bank_size[2][4] = { + {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, + PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, + {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, + PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} +}; + +static const unsigned int pci_p2p_configuration[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION +}; + + +/******************************************************************** +* pciWriteConfigReg - Write to a PCI configuration register +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* +* +* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum, unsigned int data) +{ + volatile unsigned int DataForAddrReg; + unsigned int functionNum; + unsigned int busNum = 0; + unsigned int addr; + + if (pciDevNum > 32) /* illegal device Number */ + return; + if (pciDevNum == SELF) { /* configure our configuration space. */ + pciDevNum = + (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & + 0x1f; + busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & + 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = + (regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); + GT_REG_READ (pci_configuration_address[host], &addr); + if (addr != DataForAddrReg) + return; + GT_REG_WRITE (pci_configuration_data[host], data); +} + +/******************************************************************** +* pciReadConfigReg - Read from a PCI0 configuration register +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec) +* pciDevNum: The device number needs to be addressed. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum) +{ + volatile unsigned int DataForAddrReg; + unsigned int data; + unsigned int functionNum; + unsigned int busNum = 0; + + if (pciDevNum > 32) /* illegal device Number */ + return 0xffffffff; + if (pciDevNum == SELF) { /* configure our configuration space. */ + pciDevNum = + (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & + 0x1f; + busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & + 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = + (regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); + GT_REG_READ (pci_configuration_address[host], &data); + if (data != DataForAddrReg) + return 0xffffffff; + GT_REG_READ (pci_configuration_data[host], &data); + return data; +} + +/******************************************************************** +* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. +* +* Inputs: unsigned int regOffset - The register offset as it apears in the +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +* The configuration Address is configure as type-I (bits[1:0] = '01') due to +* PCI spec referring to P2P. +* +*********************************************************************/ +void pciOverBridgeWriteConfigReg (PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum, unsigned int data) +{ + unsigned int DataForReg; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if (pciDevNum == SELF) { /* This board */ + DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; + } else { + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | + BIT31 | BIT0; + } + GT_REG_WRITE (pci_configuration_address[host], DataForReg); + GT_REG_WRITE (pci_configuration_data[host], data); +} + + +/******************************************************************** +* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum) +{ + unsigned int DataForReg; + unsigned int data; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if (pciDevNum == SELF) { /* This board */ + DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; + } else { /* agent on another bus */ + + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | + BIT0 | BIT31; + } + GT_REG_WRITE (pci_configuration_address[host], DataForReg); + GT_REG_READ (pci_configuration_data[host], &data); + return data; +} + + +/******************************************************************** +* pciGetRegOffset - Gets the register offset for this region config. +* +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI register base address +*********************************************************************/ +static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) +{ + switch (host) { + case PCI_HOST0: + switch (region) { + case PCI_IO: + return PCI_0I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: + return PCI_0MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: + return PCI_0MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: + return PCI_0MEMORY3_LOW_DECODE_ADDRESS; + } + case PCI_HOST1: + switch (region) { + case PCI_IO: + return PCI_1I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: + return PCI_1MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: + return PCI_1MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: + return PCI_1MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: + return PCI_1MEMORY3_LOW_DECODE_ADDRESS; + } + } + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; +} + +static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) +{ + switch (host) { + case PCI_HOST0: + switch (region) { + case PCI_IO: + return PCI_0I_O_ADDRESS_REMAP; + case PCI_REGION0: + return PCI_0MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: + return PCI_0MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: + return PCI_0MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: + return PCI_0MEMORY3_ADDRESS_REMAP; + } + case PCI_HOST1: + switch (region) { + case PCI_IO: + return PCI_1I_O_ADDRESS_REMAP; + case PCI_REGION0: + return PCI_1MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: + return PCI_1MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: + return PCI_1MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: + return PCI_1MEMORY3_ADDRESS_REMAP; + } + } + return PCI_0MEMORY0_ADDRESS_REMAP; +} + +/******************************************************************** +* pciGetBaseAddress - Gets the base address of a PCI. +* - If the PCI size is 0 then this base address has no meaning!!! +* +* +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI base address. +*********************************************************************/ +unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) +{ + unsigned int regBase; + unsigned int regEnd; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, ®Base); + GT_REG_READ (regOffset + 8, ®End); + + if (regEnd <= regBase) + return 0xffffffff; /* ERROR !!! */ + + regBase = regBase << 16; + return regBase; +} + +bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, + unsigned int bankBase, unsigned int bankLength) +{ + unsigned int low = 0xfff; + unsigned int high = 0x0; + unsigned int regOffset = pciGetRegOffset (host, region); + unsigned int remapOffset = pciGetRemapOffset (host, region); + + if (bankLength != 0) { + low = (bankBase >> 16) & 0xffff; + high = ((bankBase + bankLength) >> 16) - 1; + } + + GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ + GT_REG_WRITE (regOffset + 8, high); + + if (bankLength != 0) { /* must do AFTER writing maps */ + GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. + dont support upper 32 + in this driver */ + } + return true; +} + +unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) +{ + unsigned int low; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, &low); + return (low & 0xffff) << 16; +} + +unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) +{ + unsigned int low, high; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, &low); + GT_REG_READ (regOffset + 8, &high); + return ((high & 0xffff) + 1) << 16; +} + + +/* ronen - 7/Dec/03*/ +/******************************************************************** +* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. +* Inputs: one of the PCI BAR +*********************************************************************/ +void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) +{ + RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); +} + +void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) +{ + SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); +} + +/******************************************************************** +* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. +* +* Inputs: base and size of PCI SCS +*********************************************************************/ +void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, + unsigned int pciDramBase, unsigned int pciDramSize) +{ + /*ronen different function for 3rd bank. */ + unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; + + pciDramBase = pciDramBase & 0xfffff000; + pciDramBase = pciDramBase | (pciReadConfigReg (host, + PCI_SCS_0_BASE_ADDRESS + + offset, + SELF) & 0x00000fff); + pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, + pciDramBase); + if (pciDramSize == 0) + pciDramSize++; + GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); + gtPciEnableInternalBAR (host, bank); +} + +/******************************************************************** +* pciSetRegionFeatures - This function modifys one of the 8 regions with +* feature bits given as an input. +* - Be advised to check the spec before modifying them. +* Inputs: PCI_PROTECT_REGION region - one of the eight regions. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. +* Returns: false if one of the parameters is erroneous true otherwise. +*********************************************************************/ +bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, + unsigned int features, unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int accessLow; + unsigned int accessHigh; + unsigned int accessTop = baseAddress + regionLength; + + if (regionLength == 0) { /* close the region. */ + pciDisableAccessRegion (host, region); + return true; + } + /* base Address is store is bits [11:0] */ + accessLow = (baseAddress & 0xfff00000) >> 20; + /* All the features are update according to the defines in pci.h (to be on + the safe side we disable bits: [11:0] */ + accessLow = accessLow | (features & 0xfffff000); + /* write to the Low Access Region register */ + GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, + accessLow); + + accessHigh = (accessTop & 0xfff00000) >> 20; + + /* write to the High Access Region register */ + GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, + accessHigh - 1); + return true; +} + +/******************************************************************** +* pciDisableAccessRegion - Disable The given Region by writing MAX size +* to its low Address and MIN size to its high Address. +* +* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. +* Returns: N/A. +*********************************************************************/ +void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) +{ + /* writing back the registers default values. */ + GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, + 0x01001fff); + GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); +} + +/******************************************************************** +* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true. +*********************************************************************/ +bool pciArbiterEnable (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); + return true; +} + +/******************************************************************** +* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true +*********************************************************************/ +bool pciArbiterDisable (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); + return true; +} + +/******************************************************************** +* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) +* +* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. +* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. +* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. +* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. +* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. +* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. +* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. +* Returns: true +*********************************************************************/ +bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, + PCI_AGENT_PRIO externalAgent0, + PCI_AGENT_PRIO externalAgent1, + PCI_AGENT_PRIO externalAgent2, + PCI_AGENT_PRIO externalAgent3, + PCI_AGENT_PRIO externalAgent4, + PCI_AGENT_PRIO externalAgent5) +{ + unsigned int regData; + unsigned int writeData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + writeData = (internalAgent << 7) + (externalAgent0 << 8) + + (externalAgent1 << 9) + (externalAgent2 << 10) + + (externalAgent3 << 11) + (externalAgent4 << 12) + + (externalAgent5 << 13); + regData = (regData & 0xffffc07f) | writeData; + GT_REG_WRITE (pci_arbiter_control[host], regData & regData); + return true; +} + +/******************************************************************** +* pciParkingDisable - Park on last option disable, with this function you can +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. +* +* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* Returns: true +*********************************************************************/ +bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, + PCI_AGENT_PARK externalAgent0, + PCI_AGENT_PARK externalAgent1, + PCI_AGENT_PARK externalAgent2, + PCI_AGENT_PARK externalAgent3, + PCI_AGENT_PARK externalAgent4, + PCI_AGENT_PARK externalAgent5) +{ + unsigned int regData; + unsigned int writeData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + writeData = (internalAgent << 14) + (externalAgent0 << 15) + + (externalAgent1 << 16) + (externalAgent2 << 17) + + (externalAgent3 << 18) + (externalAgent4 << 19) + + (externalAgent5 << 20); + regData = (regData & ~(0x7f << 14)) | writeData; + GT_REG_WRITE (pci_arbiter_control[host], regData); + return true; +} + +/******************************************************************** +* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to +* respond to grant assertion within a window specified in +* the input value: 'brokenValue'. +* +* Inputs: unsigned char brokenValue - A value which limits the Master to hold the +* grant without asserting frame. +* Returns: Error for illegal broken value otherwise true. +*********************************************************************/ +bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) +{ + unsigned int data; + unsigned int regData; + + if (brokenValue > 0xf) + return false; /* brokenValue must be 4 bit */ + data = brokenValue << 3; + GT_REG_READ (pci_arbiter_control[host], ®Data); + regData = (regData & 0xffffff87) | data; + GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); + return true; +} + +/******************************************************************** +* pciDisableBrokenAgentDetection - This function disable the Broken agent +* Detection mechanism. +* NOTE: This operation may cause a dead lock on the +* pci0 arbitration. +* +* Inputs: N/A +* Returns: true. +*********************************************************************/ +bool pciDisableBrokenAgentDetection (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + regData = regData & 0xfffffffd; + GT_REG_WRITE (pci_arbiter_control[host], regData); + return true; +} + +/******************************************************************** +* pciP2PConfig - This function set the PCI_n P2P configurate. +* For more information on the P2P read PCI spec. +* +* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. +* +* Returns: true. +*********************************************************************/ +bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, + unsigned int SecondBusHigh, + unsigned int busNum, unsigned int devNum) +{ + unsigned int regData; + + regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | + ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); + GT_REG_WRITE (pci_p2p_configuration[host], regData); + return true; +} + +/******************************************************************** +* pciSetRegionSnoopMode - This function modifys one of the 4 regions which +* supports Cache Coherency in the PCI_n interface. +* Inputs: region - One of the four regions. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. +* Returns: false if one of the parameters is wrong otherwise return true. +*********************************************************************/ +bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, + PCI_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int snoopXbaseAddress; + unsigned int snoopXtopAddress; + unsigned int data; + unsigned int snoopHigh = baseAddress + regionLength; + + if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) + return false; + snoopXbaseAddress = + pci_snoop_control_base_0_low[host] + 0x10 * region; + snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; + if (regionLength == 0) { /* closing the region */ + GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); + GT_REG_WRITE (snoopXtopAddress, 0); + return true; + } + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + data = (baseAddress >> 20) | snoopType << 12; + GT_REG_WRITE (snoopXbaseAddress, data); + snoopHigh = (snoopHigh & 0xfff00000) >> 20; + GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); + return true; +} + +static int gt_read_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 * value) +{ + int bus = PCI_BUS (dev); + + if ((bus == local_buses[0]) || (bus == local_buses[1])) { + *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, + PCI_DEV (dev)); + } else { + *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> + cfg_addr, offset, + PCI_DEV (dev), bus); + } + + return 0; +} + +static int gt_write_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + int bus = PCI_BUS (dev); + + if ((bus == local_buses[0]) || (bus == local_buses[1])) { + pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, + PCI_DEV (dev), value); + } else { + pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, + offset, PCI_DEV (dev), bus, + value); + } + return 0; +} + + +static void gt_setup_ide (struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; + u32 bar_response, bar_value; + int bar; + + for (bar = 0; bar < 6; bar++) { + /*ronen different function for 3rd bank. */ + unsigned int offset = + (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; + + pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, + 0x0); + pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, + &bar_response); + + pciauto_region_allocate (bar_response & + PCI_BASE_ADDRESS_SPACE_IO ? hose-> + pci_io : hose->pci_mem, ide_bar[bar], + &bar_value); + + pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, + bar_value); + } +} + + +/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ +/* and is curently not called *. */ +#if 0 +static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char pin, irq; + + pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); + + if (pin == 1) { /* only allow INT A */ + irq = pci_irq_swizzle[(PCI_HOST) hose-> + cfg_addr][PCI_DEV (dev)]; + if (irq) + pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); + } +} +#endif + +struct pci_config_table gt_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, + + {} +}; + +struct pci_controller pci0_hose = { +/* fixup_irq: gt_fixup_irq, */ + config_table:gt_config_table, +}; + +struct pci_controller pci1_hose = { +/* fixup_irq: gt_fixup_irq, */ + config_table:gt_config_table, +}; + +void pci_init_board (void) +{ + unsigned int command; + +#ifdef DEBUG + gt_pci_bus_mode_display (PCI_HOST0); +#endif + + pci0_hose.first_busno = 0; + pci0_hose.last_busno = 0xff; + local_buses[0] = pci0_hose.first_busno; + + /* PCI memory space */ + pci_set_region (pci0_hose.regions + 0, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (pci0_hose.regions + 1, + CFG_PCI0_IO_SPACE_PCI, + CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + + pci_set_ops (&pci0_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + pci0_hose.region_count = 2; + + pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; + + pci_register_hose (&pci0_hose); + pciArbiterEnable (PCI_HOST0); + pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + + pci0_hose.last_busno = pci_hose_scan (&pci0_hose); + +#ifdef DEBUG + gt_pci_bus_mode_display (PCI_HOST1); +#endif + pci1_hose.first_busno = pci0_hose.last_busno + 1; + pci1_hose.last_busno = 0xff; + pci1_hose.current_busno = pci1_hose.first_busno; + local_buses[1] = pci1_hose.first_busno; + + /* PCI memory space */ + pci_set_region (pci1_hose.regions + 0, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (pci1_hose.regions + 1, + CFG_PCI1_IO_SPACE_PCI, + CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + + pci_set_ops (&pci1_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + + pci1_hose.region_count = 2; + + pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; + + pci_register_hose (&pci1_hose); + + pciArbiterEnable (PCI_HOST1); + pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); + + command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); + + pci1_hose.last_busno = pci_hose_scan (&pci1_hose); + + command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); + +} diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c new file mode 100644 index 0000000..d2635f8 --- /dev/null +++ b/board/Marvell/db64360/sdram_init.c @@ -0,0 +1,1984 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * adaption for the Marvell DB64360 Board + * Ingo Assmus (ingo.assmus@keymile.com) + ************************************************************************/ + + +/* sdram_init.c - automatic memory sizing */ + +#include +#include <74xx_7xx.h> +#include "../include/memory.h" +#include "../include/pci.h" +#include "../include/mv_gen_reg.h" +#include + +#include "eth.h" +#include "mpsc.h" +#include "../common/i2c.h" +#include "64360.h" +#include "mv_regs.h" + +#undef DEBUG +#define MAP_PCI + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +int set_dfcdlInit (void); /* setup delay line of Mv64360 */ +int mvDmaIsChannelActive (int); +int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); +int mvDmaTransfer (int, ulong, ulong, ulong, ulong); + +/* ------------------------------------------------------------------------- */ + +int +memory_map_bank (unsigned int bankNo, + unsigned int bankBase, unsigned int bankLength) +{ +#ifdef MAP_PCI + PCI_HOST host; +#endif + + +#ifdef DEBUG + if (bankLength > 0) { + printf ("mapping bank %d at %08x - %08x\n", + bankNo, bankBase, bankBase + bankLength - 1); + } else { + printf ("unmapping bank %d\n", bankNo); + } +#endif + + memoryMapBank (bankNo, bankBase, bankLength); + +#ifdef MAP_PCI + for (host = PCI_HOST0; host <= PCI_HOST1; host++) { + const int features = + PREFETCH_ENABLE | + DELAYED_READ_ENABLE | + AGGRESSIVE_PREFETCH | + READ_LINE_AGGRESSIVE_PREFETCH | + READ_MULTI_AGGRESSIVE_PREFETCH | + MAX_BURST_4 | PCI_NO_SWAP; + + pciMapMemoryBank (host, bankNo, bankBase, bankLength); + + pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, + bankLength); + + pciSetRegionFeatures (host, bankNo, features, bankBase, + bankLength); + } +#endif + return 0; +} + +#define GB (1 << 30) + +/* much of this code is based on (or is) the code in the pip405 port */ +/* thanks go to the authors of said port - Josh */ + +/* structure to store the relevant information about an sdram bank */ +typedef struct sdram_info { + uchar drb_size; + uchar registered, ecc; + uchar tpar; + uchar tras_clocks; + uchar burst_len; + uchar banks, slot; +} sdram_info_t; + +/* Typedefs for 'gtAuxilGetDIMMinfo' function */ + +typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE; + +typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, + SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, +} VOLTAGE_INTERFACE; + +typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 = + 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 = + 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR; +typedef enum _max_CL_supported_SD { SD_CL_1 = + 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, + SD_FAULT } MAX_CL_SUPPORTED_SD; + + +/* SDRAM/DDR information struct */ +typedef struct _gtMemoryDimmInfo { + MEMORY_TYPE memoryType; + unsigned int numOfRowAddresses; + unsigned int numOfColAddresses; + unsigned int numOfModuleBanks; + unsigned int dataWidth; + VOLTAGE_INTERFACE voltageInterface; + unsigned int errorCheckType; /* ECC , PARITY.. */ + unsigned int sdramWidth; /* 4,8,16 or 32 */ ; + unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ + unsigned int minClkDelay; + unsigned int burstLengthSupported; + unsigned int numOfBanksOnEachDevice; + unsigned int suportedCasLatencies; + unsigned int RefreshInterval; + unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ + unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ + MAX_CL_SUPPORTED_DDR maxClSupported_DDR; + MAX_CL_SUPPORTED_SD maxClSupported_SD; + unsigned int moduleBankDensity; + /* module attributes (true for yes) */ + bool bufferedAddrAndControlInputs; + bool registeredAddrAndControlInputs; + bool onCardPLL; + bool bufferedDQMBinputs; + bool registeredDQMBinputs; + bool differentialClockInput; + bool redundantRowAddressing; + + /* module general attributes */ + bool suportedAutoPreCharge; + bool suportedPreChargeAll; + bool suportedEarlyRasPreCharge; + bool suportedWrite1ReadBurst; + bool suported5PercentLowVCC; + bool suported5PercentUpperVCC; + /* module timing parameters */ + unsigned int minRasToCasDelay; + unsigned int minRowActiveRowActiveDelay; + unsigned int minRasPulseWidth; + unsigned int minRowPrechargeTime; /* measured in ns */ + + int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ + int addrAndCommandSetupTime; /* (measured in ns/100) */ + int dataInputSetupTime; /* LoP left of point (measured in ns) */ + int dataInputHoldTime; /* LoP left of point (measured in ns) */ +/* tAC times for highest 2nd and 3rd highest CAS Latency values */ + unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ + unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ + unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ + + unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ + + unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ + + unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ + + /* Parameters calculated from + the extracted DIMM information */ + unsigned int size; + unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ + unsigned int numberOfDevices; + uchar drb_size; /* DRAM size in n*64Mbit */ + uchar slot; /* Slot Number this module is inserted in */ + uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ +#ifdef DEBUG + uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ + uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ + uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ + unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ + unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ + unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ + uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ + +#endif +} AUX_MEM_DIMM_INFO; + + +/* + * translate ns.ns/10 coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short NS10to10PS (unsigned char spd_byte) +{ + unsigned short ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + return (ns * 100 + ns10 * 10); +} + +/* + * translate ns coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short NSto10PS (unsigned char spd_byte) +{ + return (spd_byte * 100); +} + +/* This code reads the SPD chip on the sdram and populates + * the array which is passed in with the relevant information */ +/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ +static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long spd_checksum; + +#ifdef ZUMA_NTL + /* zero all the values */ + memset (info, 0, sizeof (*info)); + +/* + if (!slot) { + info->slot = 0; + info->banks = 1; + info->registered = 0; + info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */ +/* info->tpar = 3; + info->tras_clocks = 5; + info->burst_len = 4; +*/ +#ifdef CONFIG_MV64360_ECC + /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ + dimmInfo->errorCheckType = 2; +/* info->ecc = 2;*/ +#endif +} + +return 0; + +#else + uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; + int ret; + unsigned int i, j, density = 1, devicesForErrCheck = 0; + +#ifdef DEBUG + unsigned int k; +#endif + unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; + int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; + uchar supp_cal, cal_val; + ulong memclk, tmemclk; + ulong tmp; + uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar data[128]; + + memclk = gd->bus_clk; + tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ + + DP (puts ("before i2c read\n")); + + ret = i2c_read (addr, 0, 1, data, 128); + + DP (puts ("after i2c read\n")); + + /* zero all the values */ + memset (dimmInfo, 0, sizeof (*dimmInfo)); + + /* copy the SPD content 1:1 into the dimmInfo structure */ + for (i = 0; i <= 127; i++) { + dimmInfo->spd_raw_data[i] = data[i]; + } + + if (ret) { + DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + return 0; + } else + dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ + +#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT + + for (i = 0; i <= 127; i++) { + printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], + data[i]); + } + +#endif +#ifdef DEBUG +/* find Manufactura of Dimm Module */ + for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { + dimmInfo->manufactura[i] = data[64 + i]; + } + printf ("\nThis RAM-Module is produced by: %s\n", + dimmInfo->manufactura); + +/* find Manul-ID of Dimm Module */ + for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { + dimmInfo->modul_id[i] = data[73 + i]; + } + printf ("The Module-ID of this RAM-Module is: %s\n", + dimmInfo->modul_id); + +/* find Vendor-Data of Dimm Module */ + for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { + dimmInfo->vendor_data[i] = data[99 + i]; + } + printf ("Vendor Data of this RAM-Module is: %s\n", + dimmInfo->vendor_data); + +/* find modul_serial_no of Dimm Module */ + dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); + printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", + dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); + +/* find Manufac-Data of Dimm Module */ + dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); + printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ + +/* find modul_revision of Dimm Module */ + dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); + printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ + +/* find manufac_place of Dimm Module */ + dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); + printf ("manufac_place of this RAM-Module is: %d\n", + dimmInfo->manufac_place); + +#endif + +/*------------------------------------------------------------------------------------------------------------------------------*/ +/* calculate SPD checksum */ +/*------------------------------------------------------------------------------------------------------------------------------*/ + spd_checksum = 0; + + for (i = 0; i <= 62; i++) { + spd_checksum += data[i]; + } + + if ((spd_checksum & 0xff) != data[63]) { + printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); + hang (); + } + + else + printf ("SPD Checksum ok!\n"); + + +/*------------------------------------------------------------------------------------------------------------------------------*/ + for (i = 2; i <= 35; i++) { + switch (i) { + case 2: /* Memory type (DDR / SDRAM) */ + dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; +#ifdef DEBUG + if (dimmInfo->memoryType == 0) + DP (printf + ("Dram_type in slot %d is: SDRAM\n", + dimmInfo->slot)); + if (dimmInfo->memoryType == 1) + DP (printf + ("Dram_type in slot %d is: DDRAM\n", + dimmInfo->slot)); +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 3: /* Number Of Row Addresses */ + dimmInfo->numOfRowAddresses = data[i]; + DP (printf + ("Module Number of row addresses: %d\n", + dimmInfo->numOfRowAddresses)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 4: /* Number Of Column Addresses */ + dimmInfo->numOfColAddresses = data[i]; + DP (printf + ("Module Number of col addresses: %d\n", + dimmInfo->numOfColAddresses)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 5: /* Number Of Module Banks */ + dimmInfo->numOfModuleBanks = data[i]; + DP (printf + ("Number of Banks on Mod. : %d\n", + dimmInfo->numOfModuleBanks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 6: /* Data Width */ + dimmInfo->dataWidth = data[i]; + DP (printf + ("Module Data Width: %d\n", + dimmInfo->dataWidth)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 8: /* Voltage Interface */ + switch (data[i]) { + case 0x0: + dimmInfo->voltageInterface = TTL_5V_TOLERANT; + DP (printf + ("Module is TTL_5V_TOLERANT\n")); + break; + case 0x1: + dimmInfo->voltageInterface = LVTTL; + DP (printf + ("Module is LVTTL\n")); + break; + case 0x2: + dimmInfo->voltageInterface = HSTL_1_5V; + DP (printf + ("Module is TTL_5V_TOLERANT\n")); + break; + case 0x3: + dimmInfo->voltageInterface = SSTL_3_3V; + DP (printf + ("Module is HSTL_1_5V\n")); + break; + case 0x4: + dimmInfo->voltageInterface = SSTL_2_5V; + DP (printf + ("Module is SSTL_2_5V\n")); + break; + default: + dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; + DP (printf + ("Module is VOLTAGE_UNKNOWN\n")); + break; + } + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 9: /* Minimum Cycle Time At Max CasLatancy */ + shift = (dimmInfo->memoryType == DDR) ? 4 : 2; + mult = (dimmInfo->memoryType == DDR) ? 10 : 25; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf : 0x03; + leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; + rightOfPoint = (data[i] & maskRightOfPoint) * mult; + dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = + leftOfPoint; + dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = + rightOfPoint; + DP (printf + ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", + leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 10: /* Clock To Data Out */ + div = (dimmInfo->memoryType == DDR) ? 100 : 10; + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + dimmInfo->clockToDataOut_LoP = leftOfPoint; + dimmInfo->clockToDataOut_RoP = rightOfPoint; + DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + +/*#ifdef CONFIG_ECC */ + case 11: /* Error Check Type */ + dimmInfo->errorCheckType = data[i]; + DP (printf + ("Error Check Type (0=NONE): %d\n", + dimmInfo->errorCheckType)); + break; +/* #endif */ +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 12: /* Refresh Interval */ + dimmInfo->RefreshInterval = data[i]; + DP (printf + ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", + dimmInfo->RefreshInterval)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 13: /* Sdram Width */ + dimmInfo->sdramWidth = data[i]; + DP (printf + ("Sdram Width: %d\n", + dimmInfo->sdramWidth)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 14: /* Error Check Data Width */ + dimmInfo->errorCheckDataWidth = data[i]; + DP (printf + ("Error Check Data Width: %d\n", + dimmInfo->errorCheckDataWidth)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 15: /* Minimum Clock Delay */ + dimmInfo->minClkDelay = data[i]; + DP (printf + ("Minimum Clock Delay: %d\n", + dimmInfo->minClkDelay)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 16: /* Burst Length Supported */ + /******-******-******-******* + * bit3 | bit2 | bit1 | bit0 * + *******-******-******-******* + burst length = * 8 | 4 | 2 | 1 * + ***************************** + + If for example bit0 and bit2 are set, the burst + length supported are 1 and 4. */ + + dimmInfo->burstLengthSupported = data[i]; +#ifdef DEBUG + DP (printf + ("Burst Length Supported: ")); + if (dimmInfo->burstLengthSupported & 0x01) + DP (printf ("1, ")); + if (dimmInfo->burstLengthSupported & 0x02) + DP (printf ("2, ")); + if (dimmInfo->burstLengthSupported & 0x04) + DP (printf ("4, ")); + if (dimmInfo->burstLengthSupported & 0x08) + DP (printf ("8, ")); + DP (printf (" Bit \n")); +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 17: /* Number Of Banks On Each Device */ + dimmInfo->numOfBanksOnEachDevice = data[i]; + DP (printf + ("Number Of Banks On Each Chip: %d\n", + dimmInfo->numOfBanksOnEachDevice)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 18: /* Suported Cas Latencies */ + + /* DDR: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + ********************************************************* + SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + dimmInfo->suportedCasLatencies = data[i]; +#ifdef DEBUG + DP (printf + ("Suported Cas Latencies: (CL) ")); + if (dimmInfo->memoryType == 0) { /* SDRAM */ + for (k = 0; k <= 7; k++) { + if (dimmInfo-> + suportedCasLatencies & (1 << k)) + DP (printf + ("%d, ", + k + 1)); + } + + } else { /* DDR-RAM */ + + if (dimmInfo->suportedCasLatencies & 1) + DP (printf ("1, ")); + if (dimmInfo->suportedCasLatencies & 2) + DP (printf ("1.5, ")); + if (dimmInfo->suportedCasLatencies & 4) + DP (printf ("2, ")); + if (dimmInfo->suportedCasLatencies & 8) + DP (printf ("2.5, ")); + if (dimmInfo->suportedCasLatencies & 16) + DP (printf ("3, ")); + if (dimmInfo->suportedCasLatencies & 32) + DP (printf ("3.5, ")); + + } + DP (printf ("\n")); +#endif + /* Calculating MAX CAS latency */ + for (j = 7; j > 0; j--) { + if (((dimmInfo-> + suportedCasLatencies >> j) & 0x1) == + 1) { + switch (dimmInfo->memoryType) { + case DDR: + /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ + switch (j) { + case 7: + DP (printf + ("Max. Cas Latencies (DDR): ERROR !!!\n")); + dimmInfo-> + maxClSupported_DDR + = + DDR_CL_FAULT; + hang (); + break; + case 6: + DP (printf + ("Max. Cas Latencies (DDR): ERROR !!!\n")); + dimmInfo-> + maxClSupported_DDR + = + DDR_CL_FAULT; + hang (); + break; + case 5: + DP (printf + ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_3_5; + break; + case 4: + DP (printf + ("Max. Cas Latencies (DDR): 3 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_3; + break; + case 3: + DP (printf + ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_2_5; + break; + case 2: + DP (printf + ("Max. Cas Latencies (DDR): 2 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_2; + break; + case 1: + DP (printf + ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_1_5; + break; + } + + /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy + lower then our SDRAM cycle count, we won't be able to support this CAL + and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */ + if ((dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_LoP + < + CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + || + ((dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_LoP + == + CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + && (dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_RoP + < + CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + { + dimmInfo-> + maxClSupported_DDR + = + dimmInfo-> + maxClSupported_DDR + >> 1; + DP (printf + ("*** Change actual Cas Latencies cause of minimumCycleTime n")); + } + /* ronen - checkif the Dimm frequency compared to the Sysclock. */ + if ((dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_LoP + > + CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + || + ((dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_LoP + == + CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + && (dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_RoP + > + CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + { + printf ("*********************************************************\n"); + printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); + printf ("*********************************************************\n"); + hang (); + } + + dimmInfo-> + maxCASlatencySupported_LoP + = + 1 + + (int) (5 * j / 10); + if (((5 * j) % 10) != 0) + dimmInfo-> + maxCASlatencySupported_RoP + = 5; + else + dimmInfo-> + maxCASlatencySupported_RoP + = 0; + DP (printf + ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + dimmInfo-> + maxCASlatencySupported_LoP, + dimmInfo-> + maxCASlatencySupported_RoP)); + break; + case SDRAM: + /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ + dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ + DP (printf + ("Max. Cas Latencies (SD): %d\n", + dimmInfo-> + maxClSupported_SD)); + dimmInfo-> + maxCASlatencySupported_LoP + = j; + dimmInfo-> + maxCASlatencySupported_RoP + = 0; + DP (printf + ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + dimmInfo-> + maxCASlatencySupported_LoP, + dimmInfo-> + maxCASlatencySupported_RoP)); + break; + } + break; + } + } + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 21: /* Buffered Address And Control Inputs */ + DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + dimmInfo->bufferedAddrAndControlInputs = + data[i] & BIT0; + dimmInfo->registeredAddrAndControlInputs = + (data[i] & BIT1) >> 1; + dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; + dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; + dimmInfo->registeredDQMBinputs = + (data[i] & BIT4) >> 4; + dimmInfo->differentialClockInput = + (data[i] & BIT5) >> 5; + dimmInfo->redundantRowAddressing = + (data[i] & BIT6) >> 6; +#ifdef DEBUG + if (dimmInfo->bufferedAddrAndControlInputs == 1) + DP (printf + (" - Buffered Address/Control Input: Yes \n")); + else + DP (printf + (" - Buffered Address/Control Input: No \n")); + + if (dimmInfo->registeredAddrAndControlInputs == 1) + DP (printf + (" - Registered Address/Control Input: Yes \n")); + else + DP (printf + (" - Registered Address/Control Input: No \n")); + + if (dimmInfo->onCardPLL == 1) + DP (printf + (" - On-Card PLL (clock): Yes \n")); + else + DP (printf + (" - On-Card PLL (clock): No \n")); + + if (dimmInfo->bufferedDQMBinputs == 1) + DP (printf + (" - Bufferd DQMB Inputs: Yes \n")); + else + DP (printf + (" - Bufferd DQMB Inputs: No \n")); + + if (dimmInfo->registeredDQMBinputs == 1) + DP (printf + (" - Registered DQMB Inputs: Yes \n")); + else + DP (printf + (" - Registered DQMB Inputs: No \n")); + + if (dimmInfo->differentialClockInput == 1) + DP (printf + (" - Differential Clock Input: Yes \n")); + else + DP (printf + (" - Differential Clock Input: No \n")); + + if (dimmInfo->redundantRowAddressing == 1) + DP (printf + (" - redundant Row Addressing: Yes \n")); + else + DP (printf + (" - redundant Row Addressing: No \n")); + +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 22: /* Suported AutoPreCharge */ + DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; + dimmInfo->suportedAutoPreCharge = + (data[i] & BIT1) >> 1; + dimmInfo->suportedPreChargeAll = + (data[i] & BIT2) >> 2; + dimmInfo->suportedWrite1ReadBurst = + (data[i] & BIT3) >> 3; + dimmInfo->suported5PercentLowVCC = + (data[i] & BIT4) >> 4; + dimmInfo->suported5PercentUpperVCC = + (data[i] & BIT5) >> 5; +#ifdef DEBUG + if (dimmInfo->suportedEarlyRasPreCharge == 1) + DP (printf + (" - Early Ras Precharge: Yes \n")); + else + DP (printf + (" - Early Ras Precharge: No \n")); + + if (dimmInfo->suportedAutoPreCharge == 1) + DP (printf + (" - AutoPreCharge: Yes \n")); + else + DP (printf + (" - AutoPreCharge: No \n")); + + if (dimmInfo->suportedPreChargeAll == 1) + DP (printf + (" - Precharge All: Yes \n")); + else + DP (printf + (" - Precharge All: No \n")); + + if (dimmInfo->suportedWrite1ReadBurst == 1) + DP (printf + (" - Write 1/ReadBurst: Yes \n")); + else + DP (printf + (" - Write 1/ReadBurst: No \n")); + + if (dimmInfo->suported5PercentLowVCC == 1) + DP (printf + (" - lower VCC tolerance: 5 Percent \n")); + else + DP (printf + (" - lower VCC tolerance: 10 Percent \n")); + + if (dimmInfo->suported5PercentUpperVCC == 1) + DP (printf + (" - upper VCC tolerance: 5 Percent \n")); + else + DP (printf + (" - upper VCC tolerance: 10 Percent \n")); + +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ + shift = (dimmInfo->memoryType == DDR) ? 4 : 2; + mult = (dimmInfo->memoryType == DDR) ? 10 : 25; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf : 0x03; + leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; + rightOfPoint = (data[i] & maskRightOfPoint) * mult; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = + leftOfPoint; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = + rightOfPoint; + DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ + div = (dimmInfo->memoryType == DDR) ? 100 : 10; + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; + dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; + DP (printf + ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ + shift = (dimmInfo->memoryType == DDR) ? 4 : 2; + mult = (dimmInfo->memoryType == DDR) ? 10 : 25; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf : 0x03; + leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; + rightOfPoint = (data[i] & maskRightOfPoint) * mult; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = + leftOfPoint; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = + rightOfPoint; + DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ + div = (dimmInfo->memoryType == DDR) ? 100 : 10; + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; + dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; + DP (printf + ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 27: /* Minimum Row Precharge Time */ + shift = (dimmInfo->memoryType == DDR) ? 2 : 0; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; + leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (data[i] & maskRightOfPoint) * 25; + + dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ + trp_clocks = + (dimmInfo->minRowPrechargeTime + + (tmemclk - 1)) / tmemclk; + DP (printf + ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", + tmemclk, tmemclk / 100, tmemclk % 100)); + DP (printf + ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 28: /* Minimum Row Active to Row Active Time */ + shift = (dimmInfo->memoryType == DDR) ? 2 : 0; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; + leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (data[i] & maskRightOfPoint) * 25; + + dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ + trrd_clocks = + (dimmInfo->minRowActiveRowActiveDelay + + (tmemclk - 1)) / tmemclk; + DP (printf + ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 29: /* Minimum Ras-To-Cas Delay */ + shift = (dimmInfo->memoryType == DDR) ? 2 : 0; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; + leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (data[i] & maskRightOfPoint) * 25; + + dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ + trcd_clocks = + (dimmInfo->minRowActiveRowActiveDelay + + (tmemclk - 1)) / tmemclk; + DP (printf + ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 30: /* Minimum Ras Pulse Width */ + dimmInfo->minRasPulseWidth = data[i]; + tras_clocks = + (NSto10PS (data[i]) + + (tmemclk - 1)) / tmemclk; + DP (printf + ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", + dimmInfo->minRasPulseWidth, tras_clocks)); + + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 31: /* Module Bank Density */ + dimmInfo->moduleBankDensity = data[i]; + DP (printf + ("Module Bank Density: %d\n", + dimmInfo->moduleBankDensity)); +#ifdef DEBUG + DP (printf + ("*** Offered Densities (more than 1 = Multisize-Module): ")); + { + if (dimmInfo->moduleBankDensity & 1) + DP (printf ("4MB, ")); + if (dimmInfo->moduleBankDensity & 2) + DP (printf ("8MB, ")); + if (dimmInfo->moduleBankDensity & 4) + DP (printf ("16MB, ")); + if (dimmInfo->moduleBankDensity & 8) + DP (printf ("32MB, ")); + if (dimmInfo->moduleBankDensity & 16) + DP (printf ("64MB, ")); + if (dimmInfo->moduleBankDensity & 32) + DP (printf ("128MB, ")); + if ((dimmInfo->moduleBankDensity & 64) + || (dimmInfo->moduleBankDensity & 128)) { + DP (printf ("ERROR, ")); + hang (); + } + } + DP (printf ("\n")); +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 32: /* Address And Command Setup Time (measured in ns/1000) */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->addrAndCommandSetupTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Address And Command Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 33: /* Address And Command Hold Time */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->addrAndCommandHoldTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Address And Command Hold Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 34: /* Data Input Setup Time */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->dataInputSetupTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Data Input Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 35: /* Data Input Hold Time */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->dataInputHoldTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Data Input Hold Time [ns]: %d.%d\n\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + } + } + /* calculating the sdram density */ + for (i = 0; + i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; + i++) { + density = density * 2; + } + dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * + dimmInfo->sdramWidth; + dimmInfo->numberOfDevices = + (dimmInfo->dataWidth / dimmInfo->sdramWidth) * + dimmInfo->numOfModuleBanks; + devicesForErrCheck = + (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; + if ((dimmInfo->errorCheckType == 0x1) + || (dimmInfo->errorCheckType == 0x2) + || (dimmInfo->errorCheckType == 0x3)) { + dimmInfo->size = + (dimmInfo->deviceDensity / 8) * + (dimmInfo->numberOfDevices - + /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */ + dimmInfo->numberOfDevices / 8); + } else { + dimmInfo->size = + (dimmInfo->deviceDensity / 8) * + dimmInfo->numberOfDevices; + } + + /* compute the module DRB size */ + tmp = (1 << + (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); + tmp *= dimmInfo->numOfModuleBanks; + tmp *= dimmInfo->sdramWidth; + tmp = tmp >> 24; /* div by 0x4000000 (64M) */ + dimmInfo->drb_size = (uchar) tmp; + DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + + /* try a CAS latency of 3 first... */ + + /* bit 1 is CL2, bit 2 is CL3 */ + supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1; + + cal_val = 0; + if (supp_cal & 3) { + if (NS10to10PS (data[9]) <= tmemclk) + cal_val = 3; + } + + /* then 2... */ + if (supp_cal & 2) { + if (NS10to10PS (data[23]) <= tmemclk) + cal_val = 2; + } + + DP (printf ("cal_val = %d\n", cal_val)); + + /* bummer, did't work... */ + if (cal_val == 0) { + DP (printf ("Couldn't find a good CAS latency\n")); + hang (); + return 0; + } + + return true; + +#endif +} + +/* sets up the GT properly with information passed in */ +int setup_sdram (AUX_MEM_DIMM_INFO * info) +{ + ulong tmp, check; + ulong tmp_sdram_mode = 0; /* 0x141c */ + ulong tmp_dunit_control_low = 0; /* 0x1404 */ + int i; + + /* added 8/21/2003 P. Marchese */ + unsigned int sdram_config_reg; + + /* added 10/10/2003 P. Marchese */ + ulong sdram_chip_size; + + /* sanity checking */ + if (!info->numOfModuleBanks) { + printf ("setup_sdram called with 0 banks\n"); + return 1; + } + + /* delay line */ + set_dfcdlInit (); /* may be its not needed */ + DP (printf ("Delay line set done\n")); + + /* set SDRAM mode NOP */ /* To_do check it */ + GT_REG_WRITE (SDRAM_OPERATION, 0x5); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + } + + /* SDRAM configuration */ +/* added 8/21/2003 P. Marchese */ +/* code allows usage of registered DIMMS */ + + /* figure out the memory refresh internal */ + switch (info->RefreshInterval) { + case 0x0: + case 0x80: /* refresh period is 15.625 usec */ + sdram_config_reg = + (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ) + / (float) 1000000.0); + break; + case 0x1: + case 0x81: /* refresh period is 3.9 usec */ + sdram_config_reg = + (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + case 0x2: + case 0x82: /* refresh period is 7.8 usec */ + sdram_config_reg = + (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + case 0x3: + case 0x83: /* refresh period is 31.3 usec */ + sdram_config_reg = + (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + case 0x4: + case 0x84: /* refresh period is 62.5 usec */ + sdram_config_reg = + (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + case 0x5: + case 0x85: /* refresh period is 125 usec */ + sdram_config_reg = + (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + default: /* refresh period undefined */ + printf ("DRAM refresh period is unknown!\n"); + printf ("Aborting DRAM setup with an error\n"); + hang (); + break; + } + DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); + + /* make sure the refresh value is only 14 bits */ + if (sdram_config_reg > 0x1fff) + sdram_config_reg = 0x1fff; + DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); + + /* we want physical bank interleaving and */ + /* virtual bank interleaving enabled so do nothing */ + /* since these bits need to be zero to enable the interleaving */ + + /* registered DRAM ? */ + if (info->registeredAddrAndControlInputs == 1) { + /* it's registered DRAM, so set the reg. DRAM bit */ + sdram_config_reg = sdram_config_reg | BIT17; + DP (printf ("Enabling registered DRAM bit\n")); + } + /* turn on DRAM ECC? */ +#ifdef CONFIG_MV64360_ECC + if (info->errorCheckType == 0x2) { + /* DRAM has ECC, so turn it on */ + sdram_config_reg = sdram_config_reg | BIT18; + DP (printf ("Enabling ECC\n")); + } +#endif + /* set the data DQS pin configuration */ + switch (info->sdramWidth) { + case 0x4: /* memory is x4 */ + sdram_config_reg = sdram_config_reg | BIT20 | BIT21; + DP (printf ("Data DQS pins set for 16 pins\n")); + break; + case 0x8: /* memory is x8 or x16 */ + case 0x10: + sdram_config_reg = sdram_config_reg | BIT21; + DP (printf ("Data DQS pins set for 8 pins\n")); + break; + case 0x20: /* memory is x32 */ + /* both bits are cleared for x32 so nothing to do */ + DP (printf ("Data DQS pins set for 2 pins\n")); + break; + default: /* memory width unsupported */ + printf ("DRAM chip width is unknown!\n"); + printf ("Aborting DRAM setup with an error\n"); + hang (); + break; + } + + /* perform read buffer assignments */ + /* we are going to use the Power-up defaults */ + /* bit 26 = CPU = buffer 1 */ + /* bit 27 = PCI bus #0 = buffer 0 */ + /* bit 28 = PCI bus #1 = buffer 0 */ + /* bit 29 = MPSC = buffer 0 */ + /* bit 30 = IDMA = buffer 0 */ + /* bit 31 = Gigabit = buffer 0 */ + sdram_config_reg = sdram_config_reg | BIT26; + /* sdram_config_reg = sdram_config_reg | 0x58000000; */ + /* sdram_config_reg = sdram_config_reg & 0xffffff00; */ + + /* write the value into the SDRAM configuration register */ + GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); + DP (printf + ("OOOOOOOOO sdram_conf 0x1400: %08x\n", + GTREGREAD (SDRAM_CONFIG))); + + /* SDRAM open pages control keep open as much as I can */ + GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); + DP (printf + ("sdram_open_pages_controll 0x1414: %08x\n", + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + + /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ + tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ + if (tmp == 0) + DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + else + DP (printf + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + + /* SDRAM set CAS Latency according to SPD information */ + switch (info->memoryType) { + case SDRAM: + printf ("### SD-RAM not supported !!!\n"); + printf ("Aborting!!!\n"); + hang (); + /* ToDo fill SD-RAM if needed !!!!! */ + break; + /* Calculate the settings for SDRAM mode and Dunit control low registers */ + /* Values set according to technical bulletin TB-92 rev. c */ + case DDR: + DP (printf ("### SET-CL for DDR-RAM\n")); + switch (info->maxClSupported_DDR) { + case DDR_CL_3: + tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ + if (tmp == 1) { /* clocks sync */ + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0x05110051; + else + tmp_dunit_control_low = 0x24110051; + DP (printf + ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } else { /* clk sync. bypassed */ + + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0x2C1107F2; + else + tmp_dunit_control_low = 0x3C1107d2; + DP (printf + ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + case DDR_CL_2_5: + tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */ + if (tmp == 1) { /* clocks sync */ + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0x25110051; + else + tmp_dunit_control_low = 0x24110051; + DP (printf + ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } else { /* clk sync. bypassed */ + + if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ + printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); + printf ("Aborting!!!\n"); + hang (); + } else + tmp_dunit_control_low = 0x1B1107d2; + DP (printf + ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + case DDR_CL_2: + tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ + if (tmp == 1) { /* clocks sync */ + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0x04110051; + else + tmp_dunit_control_low = 0x03110051; + DP (printf + ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } else { /* clk sync. bypassed */ + + if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ + printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); + printf ("Aborting!!!\n"); + hang (); + } else + tmp_dunit_control_low = 0x3B1107d2; + DP (printf + ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + case DDR_CL_1_5: + tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */ + if (tmp == 1) { /* clocks sync */ + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0x24110051; + else + tmp_dunit_control_low = 0x23110051; + DP (printf + ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } else { /* clk sync. bypassed */ + + if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ + printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); + printf ("Aborting!!!\n"); + hang (); + } else + tmp_dunit_control_low = 0x1A1107d2; + DP (printf + ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + + default: + printf ("Max. CL is out of range %d\n", + info->maxClSupported_DDR); + hang (); + break; + } /* end DDR switch */ + break; + } /* end CL switch */ + + /* Write results of CL detection procedure */ + /* set SDRAM mode reg. 0x141c */ + GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); + + /* set SDRAM mode SetCommand 0x1418 */ + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + } + + /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ + GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low); + + /* set SDRAM mode SetCommand 0x1418 */ + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + } + +/*------------------------------------------------------------------------------ */ + + /* bank parameters */ + /* SDRAM address decode register 0x1410 */ + /* program this with the default value */ + tmp = 0x02; /* power-up default address select decoding value */ + + DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); +/* figure out the DRAM chip size */ + sdram_chip_size = + (1 << (info->numOfRowAddresses + info->numOfColAddresses)); + sdram_chip_size *= info->sdramWidth; + sdram_chip_size *= 4; + DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); + /* divide sdram chip size by 64 Mbits */ + sdram_chip_size = sdram_chip_size / 0x4000000; + switch (sdram_chip_size) { + case 1: /* 64 Mbit */ + case 2: /* 128 Mbit */ + DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + tmp |= (0x00 << 4); + break; + case 4: /* 256 Mbit */ + case 8: /* 512 Mbit */ + DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + tmp |= (0x01 << 4); + break; + case 16: /* 1 Gbit */ + case 32: /* 2 Gbit */ + DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + tmp |= (0x02 << 4); + break; + default: + printf ("Error in dram size calculation\n"); + printf ("RAM-Device_size is unsupported\n"); + hang (); + } + + /* SDRAM address control */ + GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); + DP (printf + ("setting up sdram address control (0x1410) with: %08lx \n", + tmp)); + +/* ------------------------------------------------------------------------------ */ +/* same settings for registerd & non-registerd DDR SDRAM */ + DP (printf + ("setting up sdram_timing_control_low (0x1408) with: %08x \n", + 0x11511220)); + GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); + + +/* ------------------------------------------------------------------------------ */ + + /* SDRAM configuration */ + tmp = GTREGREAD (SDRAM_CONFIG); + + if (info->registeredAddrAndControlInputs + || info->registeredDQMBinputs) { + tmp |= (1 << 17); + DP (printf + ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", + info->registeredAddrAndControlInputs, + info->registeredDQMBinputs)); + } + + /* Use buffer 1 to return read data to the CPU + * Page 426 MV64360 */ + tmp |= (1 << 26); + DP (printf + ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", + GTREGREAD (SDRAM_CONFIG))); + DP (printf + ("After Buffer assignment - sdram_conf (0x1400): %08x\n", + GTREGREAD (SDRAM_CONFIG))); + + /* SDRAM timing To_do: */ +/* ------------------------------------------------------------------------------ */ + + DP (printf + ("setting up sdram_timing_control_high (0x140c) with: %08x \n", + 0x9)); + GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9); + + DP (printf + ("setting up sdram address pads control (0x14c0) with: %08x \n", + 0x7d5014a)); + GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); + + DP (printf + indent: Standard input:1450: Warning:old style assignment ambiguity in "=*". Assuming "= *" + +indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". Assuming "= *" + + ("setting up sdram data pads control (0x14c4) with: %08x \n", + 0x7d5014a)); + GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); + +/* ------------------------------------------------------------------------------ */ + + /* set the SDRAM configuration for each bank */ + +/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ + { + i = info->slot; + DP (printf + ("\n*** Running a MRS cycle for bank %d ***\n", i)); + + /* map the bank */ + memory_map_bank (i, 0, GB / 4); + + /* set SDRAM mode */ /* To_do check it */ + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + check = GTREGREAD (SDRAM_OPERATION); + DP (printf + ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", + check)); + + + /* switch back to normal operation mode */ + GT_REG_WRITE (SDRAM_OPERATION, 0); + check = GTREGREAD (SDRAM_OPERATION); + DP (printf + ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", + check)); + + /* unmap the bank */ + memory_map_bank (i, 0, 0); + } + + return 0; + +} + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +long int dram_size (long int *base, long int maxsize) +{ + volatile long int *addr, *b = base; + long int cnt, val, save1, save2; + +#define STARTVAL (1<<20) /* start test at 1M */ + for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); + cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + save1 = *addr; /* save contents of addr */ + save2 = *b; /* save contents of base */ + + *addr = cnt; /* write cnt to addr */ + *b = 0; /* put null at base */ + + /* check at base address */ + if ((*b) != 0) { + *addr = save1; /* restore *addr */ + *b = save2; /* restore *b */ + return (0); + } + val = *addr; /* read *addr */ + val = *addr; /* read *addr */ + + *addr = save1; + *b = save2; + + if (val != cnt) { + DP (printf + ("Found %08x at Address %08x (failure)\n", + (unsigned int) val, (unsigned int) addr)); + /* fix boundary condition.. STARTVAL means zero */ + if (cnt == STARTVAL / sizeof (long)) + cnt = 0; + return (cnt * sizeof (long)); + } + } + return maxsize; +} + +/* ------------------------------------------------------------------------- */ + +/* ppcboot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int initdram (int board_type) +{ + int s0 = 0, s1 = 0; + int checkbank[4] = {[0 ... 3] = 0 }; + ulong realsize, total, check; + AUX_MEM_DIMM_INFO dimmInfo1; + AUX_MEM_DIMM_INFO dimmInfo2; + int nhr, bank_no; + ulong dest, memSpaceAttr; + + /* first, use the SPD to get info about the SDRAM/ DDRRAM */ + + /* check the NHR bit and skip mem init if it's already done */ + nhr = get_hid0 () & (1 << 16); + + if (nhr) { + printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); + } else { + /* DIMM0 */ + s0 = check_dimm (0, &dimmInfo1); + + /* DIMM1 */ + s1 = check_dimm (1, &dimmInfo2); + + memory_map_bank (0, 0, 0); + memory_map_bank (1, 0, 0); + memory_map_bank (2, 0, 0); + memory_map_bank (3, 0, 0); + + /* ronen check correct set of DIMMS */ + if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) { + if (dimmInfo1.errorCheckType != + dimmInfo2.errorCheckType) + printf ("***WARNNING***!!!! different ECC support of the DIMMS\n"); + if (dimmInfo1.maxClSupported_DDR != + dimmInfo2.maxClSupported_DDR) + printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n"); + if (dimmInfo1.registeredAddrAndControlInputs != + dimmInfo2.registeredAddrAndControlInputs) + printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n"); + } + + if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) { + printf ("Setup for DIMM1 failed.\n"); + } + + if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) { + printf ("Setup for DIMM2 failed.\n"); + } + + /* set the NHR bit */ + set_hid0 (get_hid0 () | (1 << 16)); + } + /* next, size the SDRAM banks */ + + realsize = total = 0; + check = GB / 4; + if (dimmInfo1.numOfModuleBanks > 0) { + checkbank[0] = 1; + } + if (dimmInfo1.numOfModuleBanks > 1) { + checkbank[1] = 1; + } + if (dimmInfo1.numOfModuleBanks > 2) + printf ("Error, SPD claims DIMM1 has >2 banks\n"); + + printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks); + + if (dimmInfo2.numOfModuleBanks > 0) { + checkbank[2] = 1; + } + if (dimmInfo2.numOfModuleBanks > 1) { + checkbank[3] = 1; + } + if (dimmInfo2.numOfModuleBanks > 2) + printf ("Error, SPD claims DIMM2 has >2 banks\n"); + + printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); + + for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + /* skip over banks that are not populated */ + if (!checkbank[bank_no]) + continue; + + /* ronen - realsize = dram_size((long int *)total, check); */ + if (bank_no == 0 || bank_no == 1) { + if (checkbank[1] == 1) + realsize = dimmInfo1.size / 2; + else + realsize = dimmInfo1.size; + } + if (bank_no == 2 || bank_no == 3) { + if (checkbank[3] == 1) + realsize = dimmInfo2.size / 2; + else + realsize = dimmInfo2.size; + } + memory_map_bank (bank_no, total, realsize); + + /* ronen - initialize the DRAM for ECC */ +#ifdef CONFIG_MV64360_ECC + if ((dimmInfo1.errorCheckType != 0) && + ((dimmInfo2.errorCheckType != 0) + || (dimmInfo2.numOfModuleBanks == 0))) { + printf ("ECC Initialization of Bank %d:", bank_no); + memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8; + mvDmaSetMemorySpace (0, 0, memSpaceAttr, total, + realsize); + for (dest = total; dest < total + realsize; + dest += _8M) { + mvDmaTransfer (0, total, dest, _8M, + BIT8 /*DMA_DTL_128BYTES */ | + BIT3 /*DMA_HOLD_SOURCE_ADDR */ + | + BIT11 + /*DMA_BLOCK_TRANSFER_MODE */ ); + while (mvDmaIsChannelActive (0)); + } + printf (" PASS\n"); + } +#endif + + total += realsize; + } + + /* ronen- add DRAM conf prints */ + switch ((GTREGREAD (0x141c) >> 4) & 0x7) { + case 0x2: + printf ("CAS Latency = 2"); + break; + case 0x3: + printf ("CAS Latency = 3"); + break; + case 0x5: + printf ("CAS Latency = 1.5"); + break; + case 0x6: + printf ("CAS Latency = 2.5"); + break; + } + printf (" tRP = %d tRAS = %d tRCD=%d\n", + ((GTREGREAD (0x1408) >> 8) & 0xf) + 1, + ((GTREGREAD (0x1408) >> 20) & 0xf) + 1, + ((GTREGREAD (0x1408) >> 4) & 0xf) + 1); + +/* Setup Ethernet DMA Adress window to DRAM Area */ + if (total > _256M) + printf ("*** ONLY the first 256MB DRAM memory are used out of the "); + else + printf ("Total SDRAM memory is "); + /* (cause all the 4 BATS are taken) */ + return (total); +} + + +/* ronen- add Idma functions for usage of the ecc dram init. */ +/******************************************************************************* +* mvDmaIsChannelActive - Checks if a engine is busy. +********************************************************************************/ +int mvDmaIsChannelActive (int engine) +{ + ulong data; + + data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine); + if (data & BIT14 /*activity status */ ) { + return 1; + } + return 0; +} + +/******************************************************************************* +* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding +* map. +*******************************************************************************/ +int mvDmaSetMemorySpace (ulong memSpace, + ulong memSpaceTarget, + ulong memSpaceAttr, ulong baseAddress, ulong size) +{ + ulong temp; + + /* The base address must be aligned to the size. */ + if (baseAddress % size != 0) { + return 0; + } + if (size >= 0x10000 /*64K */ ) { + size &= 0xffff0000; + baseAddress = (baseAddress & 0xffff0000); + /* Set the new attributes */ + GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8, + (baseAddress | memSpaceTarget | memSpaceAttr)); + GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8), + (size - 1) & 0xffff0000); + temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG); + GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, + (temp & ~(BIT0 << memSpace))); + return 1; + } + return 0; +} + + +/******************************************************************************* +* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4 +* DMA channels. +********************************************************************************/ +int mvDmaTransfer (int engine, ulong sourceAddr, + ulong destAddr, ulong numOfBytes, ulong command) +{ + ulong engOffReg = 0; /* Engine Offset Register */ + + if (numOfBytes > 0xffff) { + command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ; + } + command = command | ((command >> 6) & 0x7); + engOffReg = engine * 4; + GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg, + numOfBytes); + GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, + sourceAddr); + GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, + destAddr); + command = + command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9 + /*DMA_NON_CHAIN_MODE */ ; + /* Activate DMA engine By writting to mvDmaControlRegister */ + GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command); + return 1; +} + +/**************************************************************************************** + * SDRAM INIT * + * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * + * This procedure fits only the Atlantis * + * * + ***************************************************************************************/ + + +/**************************************************************************************** + * DFCDL initialize MV643xx Design Considerations * + * * + ***************************************************************************************/ +int set_dfcdlInit (void) +{ + int i; + unsigned int dfcdl_word = 0x391; /* 0x14f; ronen new dfcdl */ + + for (i = 0; i < 64; i++) { + GT_REG_WRITE (SRAM_DATA0, dfcdl_word); +/* dfcdl_word += 0x41; - ronen new dfcdl */ + } + GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ + + return (0); +} diff --git a/board/Marvell/db64360/u-boot.lds b/board/Marvell/db64360/u-boot.lds new file mode 100644 index 0000000..d89eb6c --- /dev/null +++ b/board/Marvell/db64360/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/Marvell/db64460/64460.h b/board/Marvell/db64460/64460.h new file mode 100644 index 0000000..8bb0ebf --- /dev/null +++ b/board/Marvell/db64460/64460.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * main board support/init for the Galileo Eval board DB64460. + */ + +#ifndef __64460_H__ +#define __64460_H__ + +/* CPU Configuration bits */ +#define CPU_CONF_ADDR_MISS_EN (1 << 8) +#define CPU_CONF_SINGLE_CPU (1 << 11) +#define CPU_CONF_ENDIANESS (1 << 12) +#define CPU_CONF_PIPELINE (1 << 13) +#define CPU_CONF_STOP_RETRY (1 << 17) +#define CPU_CONF_MULTI_DECODE (1 << 18) +#define CPU_CONF_DP_VALID (1 << 19) +#define CPU_CONF_PERR_PROP (1 << 22) +#define CPU_CONF_AACK_DELAY_2 (1 << 25) +#define CPU_CONF_AP_VALID (1 << 26) +#define CPU_CONF_REMAP_WR_DIS (1 << 27) + +/* CPU Master Control bits */ +#define CPU_MAST_CTL_ARB_EN (1 << 8) +#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) +#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) +#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) +#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) +#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) + +#endif /* __64460_H__ */ diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile new file mode 100644 index 0000000..768ccdd --- /dev/null +++ b/board/Marvell/db64460/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001 +# Josh Huber , Mission Critical Linux, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +SOBJS = ../common/misc.o + +OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ + mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ + sdram_init.o ../common/intel_flash.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/Marvell/db64460/config.mk b/board/Marvell/db64460/config.mk new file mode 100644 index 0000000..5a434d9 --- /dev/null +++ b/board/Marvell/db64460/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Josh Huber , Mission Critical Linux, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EVB64460 boards +# + +TEXT_BASE = 0xfff00000 diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c new file mode 100644 index 0000000..a4abf8d --- /dev/null +++ b/board/Marvell/db64460/db64460.c @@ -0,0 +1,936 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com + */ + +/* + * db64460.c - main board support/init for the Galileo Eval board. + */ + +#include +#include <74xx_7xx.h> +#include "../include/memory.h" +#include "../include/pci.h" +#include "../include/mv_gen_reg.h" +#include + +#include "eth.h" +#include "mpsc.h" +#include "i2c.h" +#include "64460.h" +#include "mv_regs.h" + +#undef DEBUG +/*#define DEBUG */ + +#define MAP_PCI + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +extern void flush_data_cache (void); +extern void invalidate_l1_instruction_cache (void); + +/* ------------------------------------------------------------------------- */ + +/* this is the current GT register space location */ +/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ + +/* Unfortunately, we cant change it while we are in flash, so we initialize it + * to the "final" value. This means that any debug_led calls before + * board_early_init_f wont work right (like in cpu_init_f). + * See also my_remap_gt_regs below. (NTL) + */ + +void board_prebootm_init (void); +unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +int display_mem_map (void); + +/* ------------------------------------------------------------------------- */ + +/* + * This is a version of the GT register space remapping function that + * doesn't touch globals (meaning, it's ok to run from flash.) + * + * Unfortunately, this has the side effect that a writable + * INTERNAL_REG_BASE_ADDR is impossible. Oh well. + */ + +void my_remap_gt_regs (u32 cur_loc, u32 new_loc) +{ + u32 temp; + + /* check and see if it's already moved */ + +/* original ppcboot 1.1.6 source + + temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 20) + return; + + temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 20); + + out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); + + while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); +original ppcboot 1.1.6 source end */ + + temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 16) + return; + + temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 16); + + out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); + + while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); +} + +#ifdef CONFIG_PCI + +static void gt_pci_config (void) +{ + unsigned int stat; + unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ + + /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's + * config registers by writing ones to the bus and device. + * We then update the Virtual register with the correct value for the bus and device. + */ + if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ + GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); + + GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); + + GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); + GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, + (stat & 0xffff0000) | CFG_PCI_IDSEL); + + } + if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ + GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); + GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); + + GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); + GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, + (stat & 0xffff0000) | CFG_PCI_IDSEL); + } + + /* Enable master */ + PCI_MASTER_ENABLE (0, SELF); + PCI_MASTER_ENABLE (1, SELF); + + /* Enable PCI0/1 Mem0 and IO 0 disable all others */ + GT_REG_READ (BASE_ADDR_ENABLE, &stat); + stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 + << + 18); + stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); + GT_REG_WRITE (BASE_ADDR_ENABLE, stat); + + /* ronen- add write to pci remap registers for 64460. + in 64360 when writing to pci base go and overide remap automaticaly, + in 64460 it doesn't */ + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + + /* PCI interface settings */ + /* Timeout set to retry forever */ + GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); + GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); + + /* ronen - enable only CS0 and Internal reg!! */ + GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); + GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); + +/*ronen update the pci internal registers base address.*/ +#ifdef MAP_PCI + for (stat = 0; stat <= PCI_HOST1; stat++) + pciWriteConfigReg (stat, + PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, + SELF, CFG_GT_REGS); +#endif + +} +#endif + +/* Setup CPU interface paramaters */ +static void gt_cpu_config (void) +{ + cpu_t cpu = get_cpu_type (); + ulong tmp; + + /* cpu configuration register */ + tmp = GTREGREAD (CPU_CONFIGURATION); + + /* set the SINGLE_CPU bit see MV64460 P.399 */ +#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ + tmp |= CPU_CONF_SINGLE_CPU; +#endif + + tmp &= ~CPU_CONF_AACK_DELAY_2; + + tmp |= CPU_CONF_DP_VALID; + tmp |= CPU_CONF_AP_VALID; + + tmp |= CPU_CONF_PIPELINE; + + GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ + + /* CPU master control register */ + tmp = GTREGREAD (CPU_MASTER_CONTROL); + + tmp |= CPU_MAST_CTL_ARB_EN; + + if ((cpu == CPU_7400) || + (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { + + tmp |= CPU_MAST_CTL_CLEAN_BLK; + tmp |= CPU_MAST_CTL_FLUSH_BLK; + + } else { + /* cleanblock must be cleared for CPUs + * that do not support this command (603e, 750) + * see Res#1 */ + tmp &= ~CPU_MAST_CTL_CLEAN_BLK; + tmp &= ~CPU_MAST_CTL_FLUSH_BLK; + } + GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); +} + +/* + * board_early_init_f. + * + * set up gal. device mappings, etc. + */ +int board_early_init_f (void) +{ + uchar sram_boot = 0; + + /* + * set up the GT the way the kernel wants it + * the call to move the GT register space will obviously + * fail if it has already been done, but we're going to assume + * that if it's not at the power-on location, it's where we put + * it last time. (huber) + */ + + my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + + /* No PCI in first release of Port To_do: enable it. */ +#ifdef CONFIG_PCI + gt_pci_config (); +#endif + /* mask all external interrupt sources */ + GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); + /* new in MV6446x */ + GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); + /* --------------------- */ + GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); + GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); + /* does not exist in MV6446x + GT_REG_WRITE(CPU_INT_0_MASK, 0); + GT_REG_WRITE(CPU_INT_1_MASK, 0); + GT_REG_WRITE(CPU_INT_2_MASK, 0); + GT_REG_WRITE(CPU_INT_3_MASK, 0); + --------------------- */ + + + /* ----- DEVICE BUS SETTINGS ------ */ + + /* + * EVB + * 0 - SRAM ???? + * 1 - RTC ???? + * 2 - UART ???? + * 3 - Flash checked 32Bit Intel Strata + * boot - BootCS checked 8Bit 29LV040B + * + * Zuma + * 0 - Flash + * boot - BootCS + */ + + /* + * the dual 7450 module requires burst access to the boot + * device, so the serial rom copies the boot device to the + * on-board sram on the eval board, and updates the correct + * registers to boot from the sram. (device0) + */ + if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) + sram_boot = 1; + if (!sram_boot) + memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + + memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + + + /* configure device timing */ +#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */ + if (!sram_boot) + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); +#endif + +#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */ + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#endif +#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */ + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#endif + +#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ + /* detect if we are booting from the 32 bit flash */ + if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { + /* 32 bit boot flash */ + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, + CFG_32BIT_BOOT_PAR); + } else { + /* 8 bit boot flash */ + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + } +#else + /* 8 bit boot flash only */ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +#endif + + + gt_cpu_config (); + + /* MPP setup */ + GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + + GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + DEBUG_LED0_ON (); + DEBUG_LED1_ON (); + DEBUG_LED2_ON (); + + return 0; +} + +/* various things to do after relocation */ + +int misc_init_r () +{ + icache_enable (); +#ifdef CFG_L2 + l2cache_enable (); +#endif +#ifdef CONFIG_MPSC + + mpsc_sdma_init (); + mpsc_init2 (); +#endif + +#if 0 + /* disable the dcache and MMU */ + dcache_lock (); +#endif + return 0; +} + +void after_reloc (ulong dest_addr, gd_t * gd) +{ + /* check to see if we booted from the sram. If so, move things + * back to the way they should be. (we're running from main + * memory at this point now */ + if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) { + memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M); + } + display_mem_map (); + /* now, jump to the main ppcboot board init code */ + board_init_r (gd, dest_addr); + /* NOTREACHED */ +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + * + * right now, assume borad type. (there is just one...after all) + */ + +int checkboard (void) +{ + int l_type = 0; + + printf ("BOARD: %s\n", CFG_BOARD_NAME); + return (l_type); +} + +/* utility functions */ +void debug_led (int led, int mode) +{ + volatile int *addr = 0; + int dummy; + + if (mode == 1) { + switch (led) { + case 0: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x08000); + break; + + case 1: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x0c000); + break; + + case 2: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x10000); + break; + } + } else if (mode == 0) { + switch (led) { + case 0: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x14000); + break; + + case 1: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x18000); + break; + + case 2: + addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + 0x1c000); + break; + } + } + + dummy = *addr; +} + +int display_mem_map (void) +{ + int i, j; + unsigned int base, size, width; + + /* SDRAM */ + printf ("SD (DDR) RAM\n"); + for (i = 0; i <= BANK3; i++) { + base = memoryGetBankBaseAddress (i); + size = memoryGetBankSize (i); + if (size != 0) { + printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", + i, base, size >> 20); + } + } + + /* CPU's PCI windows */ + for (i = 0; i <= PCI_HOST1; i++) { + printf ("\nCPU's PCI %d windows\n", i); + base = pciGetSpaceBase (i, PCI_IO); + size = pciGetSpaceSize (i, PCI_IO); + printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, + size >> 20); + for (j = 0; + j <= + PCI_REGION0 + /*ronen currently only first PCI MEM is used 3 */ ; + j++) { + base = pciGetSpaceBase (i, j); + size = pciGetSpaceSize (i, j); + printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); + } + } + + /* Devices */ + printf ("\nDEVICES\n"); + for (i = 0; i <= DEVICE3; i++) { + base = memoryGetDeviceBaseAddress (i); + size = memoryGetDeviceSize (i); + width = memoryGetDeviceWidth (i) * 8; + printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); + if (i == 0) + printf ("\t- EXT SRAM (actual - 1M)\n"); + else if (i == 1) + printf ("\t- RTC\n"); + else if (i == 2) + printf ("\t- UART\n"); + else + printf ("\t- LARGE FLASH\n"); + } + + /* Bootrom */ + base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ + size = memoryGetDeviceSize (BOOT_DEVICE); + width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; + printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n", + base, size >> 20, width); + return (0); +} + +/* DRAM check routines copied from gw8260 */ + +#if defined (CFG_DRAM_TEST) + +/*********************************************************************/ +/* NAME: move64() - moves a double word (64-bit) */ +/* */ +/* DESCRIPTION: */ +/* this function performs a double word move from the data at */ +/* the source pointer to the location at the destination pointer. */ +/* */ +/* INPUTS: */ +/* unsigned long long *src - pointer to data to move */ +/* */ +/* OUTPUTS: */ +/* unsigned long long *dest - pointer to locate to move data */ +/* */ +/* RETURNS: */ +/* None */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* May cloober fr0. */ +/* */ +/*********************************************************************/ +static void move64 (unsigned long long *src, unsigned long long *dest) +{ + asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : : "fr0"); /* Clobbers fr0 */ + return; +} + + +#if defined (CFG_DRAM_TEST_DATA) + +unsigned long long pattern[] = { + 0xaaaaaaaaaaaaaaaaULL, + 0xccccccccccccccccULL, + 0xf0f0f0f0f0f0f0f0ULL, + 0xff00ff00ff00ff00ULL, + 0xffff0000ffff0000ULL, + 0xffffffff00000000ULL, + 0x00000000ffffffffULL, + 0x0000ffff0000ffffULL, + 0x00ff00ff00ff00ffULL, + 0x0f0f0f0f0f0f0f0fULL, + 0x3333333333333333ULL, + 0x5555555555555555ULL, +}; + +/*********************************************************************/ +/* NAME: mem_test_data() - test data lines for shorts and opens */ +/* */ +/* DESCRIPTION: */ +/* Tests data lines for shorts and opens by forcing adjacent data */ +/* to opposite states. Because the data lines could be routed in */ +/* an arbitrary manner the must ensure test patterns ensure that */ +/* every case is tested. By using the following series of binary */ +/* patterns every combination of adjacent bits is test regardless */ +/* of routing. */ +/* */ +/* ...101010101010101010101010 */ +/* ...110011001100110011001100 */ +/* ...111100001111000011110000 */ +/* ...111111110000000011111111 */ +/* */ +/* Carrying this out, gives us six hex patterns as follows: */ +/* */ +/* 0xaaaaaaaaaaaaaaaa */ +/* 0xcccccccccccccccc */ +/* 0xf0f0f0f0f0f0f0f0 */ +/* 0xff00ff00ff00ff00 */ +/* 0xffff0000ffff0000 */ +/* 0xffffffff00000000 */ +/* */ +/* The number test patterns will always be given by: */ +/* */ +/* log(base 2)(number data bits) = log2 (64) = 6 */ +/* */ +/* To test for short and opens to other signals on our boards. we */ +/* simply */ +/* test with the 1's complemnt of the paterns as well. */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* Assumes only one one SDRAM bank */ +/* */ +/*********************************************************************/ +int mem_test_data (void) +{ + unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long temp64 = 0; + int num_patterns = sizeof (pattern) / sizeof (pattern[0]); + int i; + unsigned int hi, lo; + + for (i = 0; i < num_patterns; i++) { + move64 (&(pattern[i]), pmem); + move64 (pmem, &temp64); + + /* hi = (temp64>>32) & 0xffffffff; */ + /* lo = temp64 & 0xffffffff; */ + /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ + + hi = (pattern[i] >> 32) & 0xffffffff; + lo = pattern[i] & 0xffffffff; + /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ + + if (temp64 != pattern[i]) { + printf ("\n Data Test Failed, pattern 0x%08x%08x", + hi, lo); + return 1; + } + } + + return 0; +} +#endif /* CFG_DRAM_TEST_DATA */ + +#if defined (CFG_DRAM_TEST_ADDRESS) +/*********************************************************************/ +/* NAME: mem_test_address() - test address lines */ +/* */ +/* DESCRIPTION: */ +/* This function performs a test to verify that each word im */ +/* memory is uniquly addressable. The test sequence is as follows: */ +/* */ +/* 1) write the address of each word to each word. */ +/* 2) verify that each location equals its address */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_address (void) +{ + volatile unsigned int *pmem = + (volatile unsigned int *) CFG_MEMTEST_START; + const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + unsigned int i; + + /* write address to each location */ + for (i = 0; i < size; i++) { + pmem[i] = i; + } + + /* verify each loaction */ + for (i = 0; i < size; i++) { + if (pmem[i] != i) { + printf ("\n Address Test Failed at 0x%x", i); + return 1; + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_ADDRESS */ + +#if defined (CFG_DRAM_TEST_WALK) +/*********************************************************************/ +/* NAME: mem_march() - memory march */ +/* */ +/* DESCRIPTION: */ +/* Marches up through memory. At each location verifies rmask if */ +/* read = 1. At each location write wmask if write = 1. Displays */ +/* failing address and pattern. */ +/* */ +/* INPUTS: */ +/* volatile unsigned long long * base - start address of test */ +/* unsigned int size - number of dwords(64-bit) to test */ +/* unsigned long long rmask - read verify mask */ +/* unsigned long long wmask - wrtie verify mask */ +/* short read - verifies rmask if read = 1 */ +/* short write - writes wmask if write = 1 */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_march (volatile unsigned long long *base, + unsigned int size, + unsigned long long rmask, + unsigned long long wmask, short read, short write) +{ + unsigned int i; + unsigned long long temp = 0; + unsigned int hitemp, lotemp, himask, lomask; + + for (i = 0; i < size; i++) { + if (read != 0) { + /* temp = base[i]; */ + move64 ((unsigned long long *) &(base[i]), &temp); + if (rmask != temp) { + hitemp = (temp >> 32) & 0xffffffff; + lotemp = temp & 0xffffffff; + himask = (rmask >> 32) & 0xffffffff; + lomask = rmask & 0xffffffff; + + printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); + return 1; + } + } + if (write != 0) { + /* base[i] = wmask; */ + move64 (&wmask, (unsigned long long *) &(base[i])); + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_WALK */ + +/*********************************************************************/ +/* NAME: mem_test_walk() - a simple walking ones test */ +/* */ +/* DESCRIPTION: */ +/* Performs a walking ones through entire physical memory. The */ +/* test uses as series of memory marches, mem_march(), to verify */ +/* and write the test patterns to memory. The test sequence is as */ +/* follows: */ +/* 1) march writing 0000...0001 */ +/* 2) march verifying 0000...0001 , writing 0000...0010 */ +/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ +/* the write mask equals 1000...0000 */ +/* 4) march verifying 1000...0000 */ +/* The test fails if any of the memory marches return a failure. */ +/* */ +/* OUTPUTS: */ +/* Displays which pass on the memory test is executing */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_walk (void) +{ + unsigned long long mask; + volatile unsigned long long *pmem = + (volatile unsigned long long *) CFG_MEMTEST_START; + const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + + unsigned int i; + + mask = 0x01; + + printf ("Initial Pass"); + mem_march (pmem, size, 0x0, 0x1, 0, 1); + + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + + for (i = 0; i < 63; i++) { + printf ("Pass %2d", i + 2); + if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { + /*printf("mask: 0x%x, pass: %d, ", mask, i); */ + return 1; + } + mask = mask << 1; + printf ("\b\b\b\b\b\b\b"); + } + + printf ("Last Pass"); + if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { + /* printf("mask: 0x%x", mask); */ + return 1; + } + printf ("\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b"); + + return 0; +} + +/*********************************************************************/ +/* NAME: testdram() - calls any enabled memory tests */ +/* */ +/* DESCRIPTION: */ +/* Runs memory tests if the environment test variables are set to */ +/* 'y'. */ +/* */ +/* INPUTS: */ +/* testdramdata - If set to 'y', data test is run. */ +/* testdramaddress - If set to 'y', address test is run. */ +/* testdramwalk - If set to 'y', walking ones test is run */ +/* */ +/* OUTPUTS: */ +/* None */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int testdram (void) +{ + char *s; + int rundata, runaddress, runwalk; + + s = getenv ("testdramdata"); + rundata = (s && (*s == 'y')) ? 1 : 0; + s = getenv ("testdramaddress"); + runaddress = (s && (*s == 'y')) ? 1 : 0; + s = getenv ("testdramwalk"); + runwalk = (s && (*s == 'y')) ? 1 : 0; + +/* rundata = 1; */ +/* runaddress = 0; */ +/* runwalk = 0; */ + + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + } +#ifdef CFG_DRAM_TEST_DATA + if (rundata == 1) { + printf ("Test DATA ... "); + if (mem_test_data () == 1) { + printf ("failed \n"); + return 1; + } else + printf ("ok \n"); + } +#endif +#ifdef CFG_DRAM_TEST_ADDRESS + if (runaddress == 1) { + printf ("Test ADDRESS ... "); + if (mem_test_address () == 1) { + printf ("failed \n"); + return 1; + } else + printf ("ok \n"); + } +#endif +#ifdef CFG_DRAM_TEST_WALK + if (runwalk == 1) { + printf ("Test WALKING ONEs ... "); + if (mem_test_walk () == 1) { + printf ("failed \n"); + return 1; + } else + printf ("ok \n"); + } +#endif + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf ("passed\n"); + } + return 0; + +} +#endif /* CFG_DRAM_TEST */ + +/* ronen - the below functions are used by the bootm function */ +/* - we map the base register to fbe00000 (same mapping as in the LSP) */ +/* - we turn off the RX gig dmas - to prevent the dma from overunning */ +/* the kernel data areas. */ +/* - we diable and invalidate the icache and dcache. */ +void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) +{ + u32 temp; + + temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 16) + return; + + temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 16); + + out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); + + while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | + new_loc | + (INTERNAL_SPACE_DECODE))))) + != temp); + +} + +void board_prebootm_init () +{ + +/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ + GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); + +/* Stop GigE Rx DMA engines */ + GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); + GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); + GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); + +/* Relocate MV64460 internal regs */ + my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM); + + icache_disable (); + invalidate_l1_instruction_cache (); + flush_data_cache (); + dcache_disable (); +} diff --git a/board/Marvell/db64460/eth.h b/board/Marvell/db64460/eth.h new file mode 100644 index 0000000..6c3b2e0 --- /dev/null +++ b/board/Marvell/db64460/eth.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * eth.h - header file for the polled mode GT ethernet driver + */ + +#ifndef __EVB64460_ETH_H__ +#define __EVB64460_ETH_H__ + +#include +#include +#include +#include + +int db64460_eth0_poll(void); +int db64460_eth0_transmit(unsigned int s, volatile char *p); +void db64460_eth0_disable(void); +bool network_start(bd_t *bis); + +#endif /* __EVB64460_ETH_H__ */ diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c new file mode 100644 index 0000000..33fbc49 --- /dev/null +++ b/board/Marvell/db64460/mpsc.c @@ -0,0 +1,1019 @@ +/* + * (C) Copyright 2001 + * John Clemens , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * changes for Marvell DB64460 eval board 2003 by Ingo Assmus + * + ************************************************************************/ + +/* + * mpsc.c - driver for console over the MPSC. + */ + + +#include +#include +#include + +#include +#include "mpsc.h" + +#include "mv_regs.h" + +#include "../include/memory.h" + +/* Define this if you wish to use the MPSC as a register based UART. + * This will force the serial port to not use the SDMA engine at all. + */ +#undef CONFIG_MPSC_DEBUG_PORT + + +int (*mpsc_putchar) (char ch) = mpsc_putchar_early; +char (*mpsc_getchar) (void) = mpsc_getchar_debug; +int (*mpsc_test_char) (void) = mpsc_test_char_debug; + + +static volatile unsigned int *rx_desc_base = NULL; +static unsigned int rx_desc_index = 0; +static volatile unsigned int *tx_desc_base = NULL; +static unsigned int tx_desc_index = 0; + +/* local function declarations */ +static int galmpsc_connect (int channel, int connect); +static int galmpsc_route_rx_clock (int channel, int brg); +static int galmpsc_route_tx_clock (int channel, int brg); +static int galmpsc_write_config_regs (int mpsc, int mode); +static int galmpsc_config_channel_regs (int mpsc); +static int galmpsc_set_char_length (int mpsc, int value); +static int galmpsc_set_stop_bit_length (int mpsc, int value); +static int galmpsc_set_parity (int mpsc, int value); +static int galmpsc_enter_hunt (int mpsc); +static int galmpsc_set_brkcnt (int mpsc, int value); +static int galmpsc_set_tcschar (int mpsc, int value); +static int galmpsc_set_snoop (int mpsc, int value); +static int galmpsc_shutdown (int mpsc); + +static int galsdma_set_RFT (int channel); +static int galsdma_set_SFM (int channel); +static int galsdma_set_rxle (int channel); +static int galsdma_set_txle (int channel); +static int galsdma_set_burstsize (int channel, unsigned int value); +static int galsdma_set_RC (int channel, unsigned int value); + +static int galbrg_set_CDV (int channel, int value); +static int galbrg_enable (int channel); +static int galbrg_disable (int channel); +static int galbrg_set_clksrc (int channel, int value); +static int galbrg_set_CUV (int channel, int value); + +static void galsdma_enable_rx (void); +static int galsdma_set_mem_space (unsigned int memSpace, + unsigned int memSpaceTarget, + unsigned int memSpaceAttr, + unsigned int baseAddress, + unsigned int size); + + +#define SOFTWARE_CACHE_MANAGEMENT + +#ifdef SOFTWARE_CACHE_MANAGEMENT +#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} +#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} +#else +#define FLUSH_DCACHE(a,b) +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) +#define INVALIDATE_DCACHE(a,b) +#endif + +#ifdef CONFIG_MPSC_DEBUG_PORT +static void mpsc_debug_init (void) +{ + + volatile unsigned int temp; + + /* Clear the CFR (CHR4) */ + /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ + temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&". Assuming "= &" + +REG_GAP)); + temp &= 0xffffff00; + temp |= BIT29; + GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), + temp); + + /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ + temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); + temp |= (BIT12 | BIT15); + GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), + temp); + + /* Set int mask */ + temp = GTREGREAD (GALMPSC_0_INT_MASK); + temp |= BIT6; + GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); +} +#endif + +char mpsc_getchar_debug (void) +{ + volatile int temp; + volatile unsigned int cause; + + cause = GTREGREAD (GALMPSC_0_INT_CAUSE); + while ((cause & BIT6) == 0) { + cause = GTREGREAD (GALMPSC_0_INT_CAUSE); + } + + temp = GTREGREAD (GALMPSC_CHANNELREG_10 + + (CHANNEL * GALMPSC_REG_GAP)); + /* By writing 1's to the set bits, the register is cleared */ + GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), + temp); + GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); + return (temp >> 16) & 0xff; +} + +/* special function for running out of flash. doesn't modify any + * global variables [josh] */ +int mpsc_putchar_early (char ch) +{ + DECLARE_GLOBAL_DATA_PTR; + int mpsc = CHANNEL; + int temp = + GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + galmpsc_set_tcschar (mpsc, ch); + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), + temp | 0x200); + +#define MAGIC_FACTOR (10*1000000) + + udelay (MAGIC_FACTOR / gd->baudrate); + return 0; +} + +/* This is used after relocation, see serial.c and mpsc_init2 */ +static int mpsc_putchar_sdma (char ch) +{ + volatile unsigned int *p; + unsigned int temp; + + + /* align the descriptor */ + p = tx_desc_base; + memset ((void *) p, 0, 8 * sizeof (unsigned int)); + + /* fill one 64 bit buffer */ + /* word swap, pad with 0 */ + p[4] = 0; /* x */ + p[5] = (unsigned int) ch; /* x */ + + /* CHANGED completely according to GT64260A dox - NTL */ + p[0] = 0x00010001; /* 0 */ + p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ + p[2] = 0; /* 8 */ + p[3] = (unsigned int) &p[4]; /* c */ + +#if 0 + p[9] = DESC_FIRST | DESC_LAST; + p[10] = (unsigned int) &p[0]; + p[11] = (unsigned int) &p[12]; +#endif + + FLUSH_DCACHE (&p[0], &p[8]); + + GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), + (unsigned int) &p[0]); + GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), + (unsigned int) &p[0]); + + temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); + temp |= (TX_DEMAND | TX_STOP); + GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); + + INVALIDATE_DCACHE (&p[1], &p[2]); + + while (p[1] & DESC_OWNER_BIT) { + udelay (100); + INVALIDATE_DCACHE (&p[1], &p[2]); + } + return 0; +} + +char mpsc_getchar_sdma (void) +{ + static unsigned int done = 0; + volatile char ch; + unsigned int len = 0, idx = 0, temp; + + volatile unsigned int *p; + + + do { + p = &rx_desc_base[rx_desc_index * 8]; + + INVALIDATE_DCACHE (&p[0], &p[1]); + /* Wait for character */ + while (p[1] & DESC_OWNER_BIT) { + udelay (100); + INVALIDATE_DCACHE (&p[0], &p[1]); + } + + /* Handle error case */ + if (p[1] & (1 << 15)) { + printf ("oops, error: %08x\n", p[1]); + + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + + (CHANNEL * GALMPSC_REG_GAP)); + temp |= (1 << 23); + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + + (CHANNEL * GALMPSC_REG_GAP), temp); + + /* Can't poll on abort bit, so we just wait. */ + udelay (100); + + galsdma_enable_rx (); + } + + /* Number of bytes left in this descriptor */ + len = p[0] & 0xffff; + + if (len) { + /* Where to look */ + idx = 5; + if (done > 3) + idx = 4; + if (done > 7) + idx = 7; + if (done > 11) + idx = 6; + + INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); + ch = p[idx] & 0xff; + done++; + } + + if (done < len) { + /* this descriptor has more bytes still + * shift down the char we just read, and leave the + * buffer in place for the next time around + */ + p[idx] = p[idx] >> 8; + FLUSH_DCACHE (&p[idx], &p[idx + 1]); + } + + if (done == len) { + /* nothing left in this descriptor. + * go to next one + */ + p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; + p[0] = 0x00100000; + FLUSH_DCACHE (&p[0], &p[1]); + /* Next descriptor */ + rx_desc_index = (rx_desc_index + 1) % RX_DESC; + done = 0; + } + } while (len == 0); /* galileo bug.. len might be zero */ + + return ch; +} + + +int mpsc_test_char_debug (void) +{ + if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) + return 0; + else { + return 1; + } +} + + +int mpsc_test_char_sdma (void) +{ + volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; + + INVALIDATE_DCACHE (&p[1], &p[2]); + + if (p[1] & DESC_OWNER_BIT) + return 0; + else + return 1; +} + +int mpsc_init (int baud) +{ + /* BRG CONFIG */ + galbrg_set_baudrate (CHANNEL, baud); + galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ + galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ + galbrg_enable (CHANNEL); /* Enable BRG */ + + /* Set up clock routing */ + galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ + + galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ + galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ + + /* reset MPSC state */ + galmpsc_shutdown (CHANNEL); + + /* SDMA CONFIG */ + galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ + galsdma_set_txle (CHANNEL); + galsdma_set_rxle (CHANNEL); + galsdma_set_RC (CHANNEL, 0xf); + galsdma_set_SFM (CHANNEL); + galsdma_set_RFT (CHANNEL); + + /* MPSC CONFIG */ + galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); + galmpsc_config_channel_regs (CHANNEL); + galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ + galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ + galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ + +#ifdef CONFIG_MPSC_DEBUG_PORT + mpsc_debug_init (); +#endif + + /* COMM_MPSC CONFIG */ +#ifdef SOFTWARE_CACHE_MANAGEMENT + galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ +#else + galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ +#endif + + return 0; +} + + +void mpsc_sdma_init (void) +{ +/* Setup SDMA channel0 SDMA_CONFIG_REG*/ + GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); + +/* Enable MPSC-Window0 for DRAM Bank0 */ + if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT, + MV64460_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_0_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK0)) != true) + printf ("%s: SDMA_Window0 memory setup failed !!! \n", + __FUNCTION__); + + +/* Disable MPSC-Window1 */ + if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT, + MV64460_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_1_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK3)) != true) + printf ("%s: SDMA_Window1 memory setup failed !!! \n", + __FUNCTION__); + + +/* Disable MPSC-Window2 */ + if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT, + MV64460_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_2_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK3)) != true) + printf ("%s: SDMA_Window2 memory setup failed !!! \n", + __FUNCTION__); + + +/* Disable MPSC-Window3 */ + if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT, + MV64460_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_3_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK3)) != true) + printf ("%s: SDMA_Window3 memory setup failed !!! \n", + __FUNCTION__); + +/* Setup MPSC0 access mode Window0 full access */ + GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, + (MV64460_SDMA_WIN_ACCESS_FULL << + (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); + +/* Setup MPSC1 access mode Window1 full access */ + GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, + (MV64460_SDMA_WIN_ACCESS_FULL << + (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); + +/* Setup MPSC internal address space base address */ + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + +/* no high address remap*/ + GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); + GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); + +/* clear interrupt cause register for MPSC (fault register)*/ + GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); +} + + +void mpsc_init2 (void) +{ + int i; + +#ifndef CONFIG_MPSC_DEBUG_PORT + mpsc_putchar = mpsc_putchar_sdma; + mpsc_getchar = mpsc_getchar_sdma; + mpsc_test_char = mpsc_test_char_sdma; +#endif + /* RX descriptors */ + rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * + sizeof (unsigned int)); + + /* align descriptors */ + rx_desc_base = (unsigned int *) + (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); + + rx_desc_index = 0; + + memset ((void *) rx_desc_base, 0, + (RX_DESC * 8) * sizeof (unsigned int)); + + for (i = 0; i < RX_DESC; i++) { + rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ + rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ + rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ + rx_desc_base[i * 8] = 0x00100000; + } + rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; + + FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); + GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), + (unsigned int) &rx_desc_base[0]); + + /* TX descriptors */ + tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * + sizeof (unsigned int)); + + /* align descriptors */ + tx_desc_base = (unsigned int *) + (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); + + tx_desc_index = -1; + + memset ((void *) tx_desc_base, 0, + (TX_DESC * 8) * sizeof (unsigned int)); + + for (i = 0; i < TX_DESC; i++) { + tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; + tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; + tx_desc_base[i * 8 + 3] = + (unsigned int) &tx_desc_base[i * 8 + 4]; + tx_desc_base[i * 8 + 2] = + (unsigned int) &tx_desc_base[(i + 1) * 8]; + tx_desc_base[i * 8 + 1] = + DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; + + /* set sbytecnt and shadow byte cnt to 1 */ + tx_desc_base[i * 8] = 0x00010001; + } + tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; + + FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); + + udelay (100); + + galsdma_enable_rx (); + + return; +} + +int galbrg_set_baudrate (int channel, int rate) +{ + DECLARE_GLOBAL_DATA_PTR; + int clock; + + galbrg_disable (channel); /*ok */ + +#ifdef ZUMA_NTL + /* from tclk */ + clock = (CFG_TCLK / (16 * rate)) - 1; +#else + clock = (CFG_TCLK / (16 * rate)) - 1; +#endif + + galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ + + galbrg_enable (channel); + + gd->baudrate = rate; + + return 0; +} + +/* ------------------------------------------------------------------ */ + +/* Below are all the private functions that no one else needs */ + +static int galbrg_set_CDV (int channel, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp &= 0xFFFF0000; + temp |= (value & 0x0000FFFF); + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} + +static int galbrg_enable (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp |= 0x00010000; + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} + +static int galbrg_disable (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp &= 0xFFFEFFFF; + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} + +static int galbrg_set_clksrc (int channel, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ + temp |= (value << 18); + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + return 0; +} + +static int galbrg_set_CUV (int channel, int value) +{ + /* set CountUpValue */ + GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); + + return 0; +} + +#if 0 +static int galbrg_reset (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp |= 0x20000; + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} +#endif + +static int galsdma_set_RFT (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000001; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_SFM (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000002; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_rxle (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000040; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_txle (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000080; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_RC (int channel, unsigned int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp &= ~0x0000003c; + temp |= (value << 2); + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_burstsize (int channel, unsigned int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp &= 0xFFFFCFFF; + switch (value) { + case 8: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x3 << 12))); + break; + + case 4: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x2 << 12))); + break; + + case 2: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x1 << 12))); + break; + + case 1: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x0 << 12))); + break; + + default: + return -1; + break; + } + + return 0; +} + +static int galmpsc_connect (int channel, int connect) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); + + if ((channel == 0) && connect) + temp &= ~0x00000007; + else if ((channel == 1) && connect) + temp &= ~(0x00000007 << 6); + else if ((channel == 0) && !connect) + temp |= 0x00000007; + else + temp |= (0x00000007 << 6); + + /* Just in case... */ + temp &= 0x3fffffff; + + GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); + + return 0; +} + +static int galmpsc_route_rx_clock (int channel, int brg) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_RxC_ROUTE); + + if (channel == 0) { + temp &= ~0x0000000F; + temp |= brg; + } else { + temp &= ~0x00000F00; + temp |= (brg << 8); + } + + GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); + + return 0; +} + +static int galmpsc_route_tx_clock (int channel, int brg) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_TxC_ROUTE); + + if (channel == 0) { + temp &= ~0x0000000F; + temp |= brg; + } else { + temp &= ~0x00000F00; + temp |= (brg << 8); + } + + GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); + + return 0; +} + +static int galmpsc_write_config_regs (int mpsc, int mode) +{ + if (mode == GALMPSC_UART) { + /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ + GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), + 0x000004c4); + + /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ + GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), + 0x024003f8); + /* 22 2222 1111 */ + /* 54 3210 9876 */ + /* 0000 0010 0000 0000 */ + /* 1 */ + /* 098 7654 3210 */ + /* 0000 0011 1111 1000 */ + } else + return -1; + + return 0; +} + +static int galmpsc_config_channel_regs (int mpsc) +{ + GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); + GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); + + galmpsc_set_brkcnt (mpsc, 0x3); + galmpsc_set_tcschar (mpsc, 0xab); + + return 0; +} + +static int galmpsc_set_brkcnt (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); + temp &= 0x0000FFFF; + temp |= (value << 16); + GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_tcschar (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); + temp &= 0xFFFF0000; + temp |= value; + GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_char_length (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); + temp &= 0xFFFFCFFF; + temp |= (value << 12); + GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_stop_bit_length (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); + temp &= 0xFFFFBFFF; + temp |= (value << 14); + GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_parity (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + if (value != -1) { + temp &= 0xFFF3FFF3; + temp |= ((value << 18) | (value << 2)); + temp |= ((value << 17) | (value << 1)); + } else { + temp &= 0xFFF1FFF1; + } + + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_enter_hunt (int mpsc) +{ + int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + temp |= 0x80000000; + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); + + while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & + MPSC_ENTER_HUNT) { + udelay (1); + } + return 0; +} + + +static int galmpsc_shutdown (int mpsc) +{ + unsigned int temp; + + /* cause RX abort (clears RX) */ + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; + temp &= ~MPSC_ENTER_HUNT; + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); + + GT_REG_WRITE (GALSDMA_0_COM_REG, 0); + GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); + + /* shut down the MPSC */ + GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); + GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); + GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); + + udelay (100); + + /* shut down the sdma engines. */ + /* reset config to default */ + GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); + + udelay (100); + + /* clear the SDMA current and first TX and RX pointers */ + GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); + GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); + GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); + + udelay (100); + + return 0; +} + +static void galsdma_enable_rx (void) +{ + int temp; + + /* Enable RX processing */ + temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); + temp |= RX_ENABLE; + GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); + + galmpsc_enter_hunt (CHANNEL); +} + +static int galmpsc_set_snoop (int mpsc, int value) +{ + int reg = + mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : + MPSC_0_ADDRESS_CONTROL_LOW; + int temp = GTREGREAD (reg); + + if (value) + temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); + else + temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); + GT_REG_WRITE (reg, temp); + return 0; +} + +/******************************************************************************* +* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map. +* +* DESCRIPTION: +* the MV64460 SDMA has its own address decoding map that is de-coupled +* from the CPU interface address decoding windows. The SDMA channels +* share four address windows. Each region can be individually configured +* by this function by associating it to a target interface and setting +* base and size values. +* +* NOTE!!! +* The size must be in 64Kbyte granularity. +* The base address must be aligned to the size. +* The size must be a series of 1s followed by a series of zeros +* +* OUTPUT: +* None. +* +* RETURN: +* True for success, false otherwise. +* +*******************************************************************************/ + +static int galsdma_set_mem_space (unsigned int memSpace, + unsigned int memSpaceTarget, + unsigned int memSpaceAttr, + unsigned int baseAddress, unsigned int size) +{ + unsigned int temp; + + if (size == 0) { + GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, + 1 << memSpace); + return true; + } + + /* The base address must be aligned to the size. */ + if (baseAddress % size != 0) { + return false; + } + if (size < 0x10000) { + return false; + } + + /* Align size and base to 64K */ + baseAddress &= 0xffff0000; + size &= 0xffff0000; + temp = size >> 16; + + /* Checking that the size is a sequence of '1' followed by a + sequence of '0' starting from LSB to MSB. */ + while ((temp > 0) && (temp & 0x1)) { + temp = temp >> 1; + } + + if (temp != 0) { + GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8, + (baseAddress | memSpaceTarget | memSpaceAttr)); + GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8), + (size - 1) & 0xffff0000); + GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, + 1 << memSpace); + } else { + /* An invalid size was specified */ + return false; + } + return true; +} diff --git a/board/Marvell/db64460/mpsc.h b/board/Marvell/db64460/mpsc.h new file mode 100644 index 0000000..3cc0c0f --- /dev/null +++ b/board/Marvell/db64460/mpsc.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2001 + * John Clemens , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * changes for Marvell DB64460 eval board 2003 by Ingo Assmus + * + ************************************************************************/ + + +/* + * mpsc.h - header file for MPSC in uart mode (console driver) + */ + +#ifndef __MPSC_H__ +#define __MPSC_H__ + +/* include actual Galileo defines */ +#include "../include/mv_gen_reg.h" + +/* driver related defines */ + +int mpsc_init(int baud); +void mpsc_sdma_init(void); +void mpsc_init2(void); +int galbrg_set_baudrate(int channel, int rate); + +int mpsc_putchar_early(char ch); +char mpsc_getchar_debug(void); +int mpsc_test_char_debug(void); + +int mpsc_test_char_sdma(void); + +extern int (*mpsc_putchar)(char ch); +extern char (*mpsc_getchar)(void); +extern int (*mpsc_test_char)(void); + +#define CHANNEL CONFIG_MPSC_PORT + +#define TX_DESC 5 +#define RX_DESC 20 + +#define DESC_FIRST 0x00010000 +#define DESC_LAST 0x00020000 +#define DESC_OWNER_BIT 0x80000000 + +#define TX_DEMAND 0x00800000 +#define TX_STOP 0x00010000 +#define RX_ENABLE 0x00000080 + +#define SDMA_RX_ABORT (1 << 15) +#define SDMA_TX_ABORT (1 << 31) +#define MPSC_TX_ABORT (1 << 7) +#define MPSC_RX_ABORT (1 << 23) +#define MPSC_ENTER_HUNT (1 << 31) + +/* MPSC defines */ + +#define GALMPSC_CONNECT 0x1 +#define GALMPSC_DISCONNECT 0x0 + +#define GALMPSC_UART 0x1 + +#define GALMPSC_STOP_BITS_1 0x0 +#define GALMPSC_STOP_BITS_2 0x1 +#define GALMPSC_CHAR_LENGTH_8 0x3 +#define GALMPSC_CHAR_LENGTH_7 0x2 + +#define GALMPSC_PARITY_ODD 0x0 +#define GALMPSC_PARITY_EVEN 0x2 +#define GALMPSC_PARITY_MARK 0x3 +#define GALMPSC_PARITY_SPACE 0x1 +#define GALMPSC_PARITY_NONE -1 + +#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ +#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ +#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ +#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ +#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ +#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ +#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ + +#define GALMPSC_REG_GAP 0x1000 + +#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ +#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ +#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ +#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ +#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ +#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ +#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ +#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ +#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ +#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ +#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ +#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ + +#define GALSDMA_COMMAND_FIRST (1 << 16) +#define GALSDMA_COMMAND_LAST (1 << 17) +#define GALSDMA_COMMAND_ENABLEINT (1 << 23) +#define GALSDMA_COMMAND_AUTO (1 << 30) +#define GALSDMA_COMMAND_OWNER (1 << 31) + +#define GALSDMA_RX 0 +#define GALSDMA_TX 1 + +/* CHANNEL2 should be CHANNEL1, according to documentation, + * but to work with the current GTREGS file... + */ +#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ +#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ +#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ +#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ +#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ +#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ +#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ +#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ +#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ +#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ +#define GALSDMA_REG_DIFF 0x2000 + +/* WRONG in gt64260R.h */ +#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ +#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ +#define GALMPSC_0_INT_CAUSE 0xb804 +#define GALMPSC_0_INT_MASK 0xb884 + +#define GALSDMA_MODE_UART 0 +#define GALSDMA_MODE_BISYNC 1 +#define GALSDMA_MODE_HDLC 2 +#define GALSDMA_MODE_TRANSPARENT 3 + +#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ +#define GALBRG_REG_GAP 0x0008 +#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ + +#endif /* __MPSC_H__ */ diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c new file mode 100644 index 0000000..ec5d581 --- /dev/null +++ b/board/Marvell/db64460/mv_eth.c @@ -0,0 +1,3182 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64460X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mv_eth.c - header file for the polled mode GT ethernet driver + */ +#include +#include +#include + +#include "mv_eth.h" + +/* enable Debug outputs */ + +#undef DEBUG_MV_ETH + +#ifdef DEBUG_MV_ETH +#define DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +#undef MV64460_CHECKSUM_OFFLOAD +/************************************************************************* +************************************************************************** +************************************************************************** +* The first part is the high level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ + +/* Definition for configuring driver */ +/* #define UPDATE_STATS_BY_SOFTWARE */ +#undef MV64460_RX_QUEUE_FILL_ON_TASK + + +/* Constants */ +#define MAGIC_ETH_RUNNING 8031971 +#define MV64460_INTERNAL_SRAM_SIZE _256K +#define EXTRA_BYTES 32 +#define WRAP ETH_HLEN + 2 + 4 + 16 +#define BUFFER_MTU dev->mtu + WRAP +#define INT_CAUSE_UNMASK_ALL 0x0007ffff +#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff +#ifdef MV64460_RX_FILL_ON_TASK +#define INT_CAUSE_MASK_ALL 0x00000000 +#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL +#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT +#endif + +/* Read/Write to/from MV64460 internal registers */ +#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) +#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) +#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) +#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) + +/* Static function declarations */ +static int mv64460_eth_real_open (struct eth_device *eth); +static int mv64460_eth_real_stop (struct eth_device *eth); +static struct net_device_stats *mv64460_eth_get_stats (struct eth_device + *dev); +static void eth_port_init_mac_tables (ETH_PORT eth_port_num); +static void mv64460_eth_update_stat (struct eth_device *dev); +bool db64460_eth_start (struct eth_device *eth); +unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, + unsigned int mib_offset); +int mv64460_eth_receive (struct eth_device *dev); + +int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length); + +#ifndef UPDATE_STATS_BY_SOFTWARE +static void mv64460_eth_print_stat (struct eth_device *dev); +#endif +/* Processes a received packet */ +extern void NetReceive (volatile uchar *, int); + +extern unsigned int INTERNAL_REG_BASE_ADDR; + +/************************************************* + *Helper functions - used inside the driver only * + *************************************************/ +#ifdef DEBUG_MV_ETH +void print_globals (struct eth_device *dev) +{ + printf ("Ethernet PRINT_Globals-Debug function\n"); + printf ("Base Address for ETH_PORT_INFO: %08x\n", + (unsigned int) dev->priv); + printf ("Base Address for mv64460_eth_priv: %08x\n", + (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> + port_private)); + + printf ("GT Internal Base Address: %08x\n", + INTERNAL_REG_BASE_ADDR); + printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE); + printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE); + printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", + (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> + p_rx_buffer_base[0], + (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32); + printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", + (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> + p_tx_buffer_base[0], + (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32); +} +#endif + +#define my_cpu_to_le32(x) my_le32_to_cpu((x)) + +unsigned long my_le32_to_cpu (unsigned long x) +{ + return (((x & 0x000000ffU) << 24) | + ((x & 0x0000ff00U) << 8) | + ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); +} + + +/********************************************************************** + * mv64460_eth_print_phy_status + * + * Prints gigabit ethenret phy status + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + **********************************************************************/ + +static void mv64460_eth_print_phy_status (struct eth_device *dev) +{ + struct mv64460_eth_priv *port_private; + unsigned int port_num; + ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; + unsigned int port_status, phy_reg_data; + + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Check Link status on phy */ + eth_port_read_smi_reg (port_num, 1, &phy_reg_data); + if (!(phy_reg_data & 0x20)) { + printf ("Ethernet port changed link status to DOWN\n"); + } else { + port_status = + MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); + printf ("Ethernet status port %d: Link up", port_num); + printf (", %s", + (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); + if (port_status & BIT4) + printf (", Speed 1 Gbps"); + else + printf (", %s", + (port_status & BIT5) ? "Speed 100 Mbps" : + "Speed 10 Mbps"); + printf ("\n"); + } +} + +/********************************************************************** + * u-boot entry functions for mv64460_eth + * + **********************************************************************/ +int db64460_eth_probe (struct eth_device *dev) +{ + return ((int) db64460_eth_start (dev)); +} + +int db64460_eth_poll (struct eth_device *dev) +{ + return mv64460_eth_receive (dev); +} + +int db64460_eth_transmit (struct eth_device *dev, volatile void *packet, + int length) +{ + mv64460_eth_xmit (dev, packet, length); + return 0; +} + +void db64460_eth_disable (struct eth_device *dev) +{ + mv64460_eth_stop (dev); +} + + +void mv6446x_eth_initialize (bd_t * bis) +{ + struct eth_device *dev; + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + int devnum, x, temp; + char *s, *e, buf[64]; + + for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { + dev = calloc (sizeof (*dev), 1); + if (!dev) { + printf ("%s: mv_enet%d allocation failure, %s\n", + __FUNCTION__, devnum, "eth_device structure"); + return; + } + + /* must be less than NAMESIZE (16) */ + sprintf (dev->name, "mv_enet%d", devnum); + +#ifdef DEBUG + printf ("Initializing %s\n", dev->name); +#endif + + /* Extract the MAC address from the environment */ + switch (devnum) { + case 0: + s = "ethaddr"; + break; + + case 1: + s = "eth1addr"; + break; + + case 2: + s = "eth2addr"; + break; + + default: /* this should never happen */ + printf ("%s: Invalid device number %d\n", + __FUNCTION__, devnum); + return; + } + + temp = getenv_r (s, buf, sizeof (buf)); + s = (temp > 0) ? buf : NULL; + +#ifdef DEBUG + printf ("Setting MAC %d to %s\n", devnum, s); +#endif + for (x = 0; x < 6; ++x) { + dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + /* ronen - set the MAC addr in the HW */ + eth_port_uc_addr_set (devnum, dev->enetaddr, 0); + + dev->init = (void *) db64460_eth_probe; + dev->halt = (void *) ethernet_phy_reset; + dev->send = (void *) db64460_eth_transmit; + dev->recv = (void *) db64460_eth_poll; + + ethernet_private = calloc (sizeof (*ethernet_private), 1); + dev->priv = (void *)ethernet_private; + if (!ethernet_private) { + printf ("%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, + "Private Device Structure"); + free (dev); + return; + } + /* start with an zeroed ETH_PORT_INFO */ + memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); + memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); + + /* set pointer to memory for stats data structure etc... */ + port_private = calloc (sizeof (*ethernet_private), 1); + ethernet_private->port_private = (void *)port_private; + if (!port_private) { + printf ("%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, + "Port Private Device Structure"); + + free (ethernet_private); + free (dev); + return; + } + + port_private->stats = + calloc (sizeof (struct net_device_stats), 1); + if (!port_private->stats) { + printf ("%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, + "Net stat Structure"); + + free (port_private); + free (ethernet_private); + free (dev); + return; + } + memset (ethernet_private->port_private, 0, + sizeof (struct mv64460_eth_priv)); + switch (devnum) { + case 0: + ethernet_private->port_num = ETH_0; + break; + case 1: + ethernet_private->port_num = ETH_1; + break; + case 2: + ethernet_private->port_num = ETH_2; + break; + default: + printf ("Invalid device number %d\n", devnum); + break; + }; + + port_private->port_num = devnum; + /* + * Read MIB counter on the GT in order to reset them, + * then zero all the stats fields in memory + */ + mv64460_eth_update_stat (dev); + memset (port_private->stats, 0, + sizeof (struct net_device_stats)); + /* Extract the MAC address from the environment */ + switch (devnum) { + case 0: + s = "ethaddr"; + break; + + case 1: + s = "eth1addr"; + break; + + case 2: + s = "eth2addr"; + break; + + default: /* this should never happen */ + printf ("%s: Invalid device number %d\n", + __FUNCTION__, devnum); + return; + } + + temp = getenv_r (s, buf, sizeof (buf)); + s = (temp > 0) ? buf : NULL; + +#ifdef DEBUG + printf ("Setting MAC %d to %s\n", devnum, s); +#endif + for (x = 0; x < 6; ++x) { + dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + DP (printf ("Allocating descriptor and buffer rings\n")); + + ethernet_private->p_rx_desc_area_base[0] = + (ETH_RX_DESC *) memalign (16, + RX_DESC_ALIGNED_SIZE * + MV64460_RX_QUEUE_SIZE + 1); + ethernet_private->p_tx_desc_area_base[0] = + (ETH_TX_DESC *) memalign (16, + TX_DESC_ALIGNED_SIZE * + MV64460_TX_QUEUE_SIZE + 1); + + ethernet_private->p_rx_buffer_base[0] = + (char *) memalign (16, + MV64460_RX_QUEUE_SIZE * + MV64460_TX_BUFFER_SIZE + 1); + ethernet_private->p_tx_buffer_base[0] = + (char *) memalign (16, + MV64460_RX_QUEUE_SIZE * + MV64460_TX_BUFFER_SIZE + 1); + +#ifdef DEBUG_MV_ETH + /* DEBUG OUTPUT prints adresses of globals */ + print_globals (dev); +#endif + eth_register (dev); + + } + DP (printf ("%s: exit\n", __FUNCTION__)); + +} + +/********************************************************************** + * mv64460_eth_open + * + * This function is called when openning the network device. The function + * should initialize all the hardware, initialize cyclic Rx/Tx + * descriptors chain and buffers and allocate an IRQ to the network + * device. + * + * Input : a pointer to the network device structure + * / / ronen - changed the output to match net/eth.c needs + * Output : nonzero of success , zero if fails. + * under construction + **********************************************************************/ + +int mv64460_eth_open (struct eth_device *dev) +{ + return (mv64460_eth_real_open (dev)); +} + +/* Helper function for mv64460_eth_open */ +static int mv64460_eth_real_open (struct eth_device *dev) +{ + + unsigned int queue; + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + unsigned int port_num; + u32 port_status, phy_reg_data; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + /* ronen - when we update the MAC env params we only update dev->enetaddr + see ./net/eth.c eth_set_enetaddr() */ + memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); + + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Stop RX Queues */ + MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), + 0x0000ff00); + + /* Clear the ethernet port interrupts */ + MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); + MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); + + /* Unmask RX buffer and TX end interrupt */ + MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), + INT_CAUSE_UNMASK_ALL); + + /* Unmask phy and link status changes interrupts */ + MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), + INT_CAUSE_UNMASK_ALL_EXT); + + /* Set phy address of the port */ + ethernet_private->port_phy_addr = 0x8 + port_num; + + /* Activate the DMA channels etc */ + eth_port_init (ethernet_private); + + + /* "Allocate" setup TX rings */ + + for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { + unsigned int size; + + port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE; + size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ + ethernet_private->tx_desc_area_size[queue] = size; + + /* first clear desc area completely */ + memset ((void *) ethernet_private->p_tx_desc_area_base[queue], + 0, ethernet_private->tx_desc_area_size[queue]); + + /* initialize tx desc ring with low level driver */ + if (ether_init_tx_desc_ring + (ethernet_private, ETH_Q0, + port_private->tx_ring_size[queue], + MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , + (unsigned int) ethernet_private-> + p_tx_desc_area_base[queue], + (unsigned int) ethernet_private-> + p_tx_buffer_base[queue]) == false) + printf ("### Error initializing TX Ring\n"); + } + + /* "Allocate" setup RX rings */ + for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { + unsigned int size; + + /* Meantime RX Ring are fixed - but must be configurable by user */ + port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE; + size = (port_private->rx_ring_size[queue] * + RX_DESC_ALIGNED_SIZE); + ethernet_private->rx_desc_area_size[queue] = size; + + /* first clear desc area completely */ + memset ((void *) ethernet_private->p_rx_desc_area_base[queue], + 0, ethernet_private->rx_desc_area_size[queue]); + if ((ether_init_rx_desc_ring + (ethernet_private, ETH_Q0, + port_private->rx_ring_size[queue], + MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , + (unsigned int) ethernet_private-> + p_rx_desc_area_base[queue], + (unsigned int) ethernet_private-> + p_rx_buffer_base[queue])) == false) + printf ("### Error initializing RX Ring\n"); + } + + eth_port_start (ethernet_private); + + /* Set maximum receive buffer to 9700 bytes */ + MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num), + (0x5 << 17) | + (MV_REG_READ + (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num)) + & 0xfff1ffff)); + + /* + * Set ethernet MTU for leaky bucket mechanism to 0 - this will + * disable the leaky bucket mechanism . + */ + + MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); + port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); + + /* Check Link status on phy */ + eth_port_read_smi_reg (port_num, 1, &phy_reg_data); + if (!(phy_reg_data & 0x20)) { + /* Reset PHY */ + if ((ethernet_phy_reset (port_num)) != true) { + printf ("$$ Warnning: No link on port %d \n", + port_num); + return 0; + } else { + eth_port_read_smi_reg (port_num, 1, &phy_reg_data); + if (!(phy_reg_data & 0x20)) { + printf ("### Error: Phy is not active\n"); + return 0; + } + } + } else { + mv64460_eth_print_phy_status (dev); + } + port_private->eth_running = MAGIC_ETH_RUNNING; + return 1; +} + + +static int mv64460_eth_free_tx_rings (struct eth_device *dev) +{ + unsigned int queue; + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + unsigned int port_num; + volatile ETH_TX_DESC *p_tx_curr_desc; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Stop Tx Queues */ + MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), + 0x0000ff00); + + /* Free TX rings */ + DP (printf ("Clearing previously allocated TX queues... ")); + for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { + /* Free on TX rings */ + for (p_tx_curr_desc = + ethernet_private->p_tx_desc_area_base[queue]; + ((unsigned int) p_tx_curr_desc <= (unsigned int) + ethernet_private->p_tx_desc_area_base[queue] + + ethernet_private->tx_desc_area_size[queue]); + p_tx_curr_desc = + (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + + TX_DESC_ALIGNED_SIZE)) { + /* this is inside for loop */ + if (p_tx_curr_desc->return_info != 0) { + p_tx_curr_desc->return_info = 0; + DP (printf ("freed\n")); + } + } + DP (printf ("Done\n")); + } + return 0; +} + +static int mv64460_eth_free_rx_rings (struct eth_device *dev) +{ + unsigned int queue; + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + unsigned int port_num; + volatile ETH_RX_DESC *p_rx_curr_desc; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + + /* Stop RX Queues */ + MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), + 0x0000ff00); + + /* Free RX rings */ + DP (printf ("Clearing previously allocated RX queues... ")); + for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { + /* Free preallocated skb's on RX rings */ + for (p_rx_curr_desc = + ethernet_private->p_rx_desc_area_base[queue]; + (((unsigned int) p_rx_curr_desc < + ((unsigned int) ethernet_private-> + p_rx_desc_area_base[queue] + + ethernet_private->rx_desc_area_size[queue]))); + p_rx_curr_desc = + (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + + RX_DESC_ALIGNED_SIZE)) { + if (p_rx_curr_desc->return_info != 0) { + p_rx_curr_desc->return_info = 0; + DP (printf ("freed\n")); + } + } + DP (printf ("Done\n")); + } + return 0; +} + +/********************************************************************** + * mv64460_eth_stop + * + * This function is used when closing the network device. + * It updates the hardware, + * release all memory that holds buffers and descriptors and release the IRQ. + * Input : a pointer to the device structure + * Output : zero if success , nonzero if fails + *********************************************************************/ + +int mv64460_eth_stop (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Disable all gigE address decoder */ + MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); + DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); + mv64460_eth_real_stop (dev); + + return 0; +}; + +/* Helper function for mv64460_eth_stop */ + +static int mv64460_eth_real_stop (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + + mv64460_eth_free_tx_rings (dev); + mv64460_eth_free_rx_rings (dev); + + eth_port_reset (ethernet_private->port_num); + /* Disable ethernet port interrupts */ + MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); + MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); + /* Mask RX buffer and TX end interrupt */ + MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0); + /* Mask phy and link status changes interrupts */ + MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); + MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH, + BIT0 << port_num); + /* Print Network statistics */ +#ifndef UPDATE_STATS_BY_SOFTWARE + /* + * Print statistics (only if ethernet is running), + * then zero all the stats fields in memory + */ + if (port_private->eth_running == MAGIC_ETH_RUNNING) { + port_private->eth_running = 0; + mv64460_eth_print_stat (dev); + } + memset (port_private->stats, 0, sizeof (struct net_device_stats)); +#endif + DP (printf ("\nEthernet stopped ... \n")); + return 0; +} + + +/********************************************************************** + * mv64460_eth_start_xmit + * + * This function is queues a packet in the Tx descriptor for + * required port. + * + * Input : skb - a pointer to socket buffer + * dev - a pointer to the required port + * + * Output : zero upon success + **********************************************************************/ + +int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, + int dataSize) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + unsigned int port_num; + PKT_INFO pkt_info; + ETH_FUNC_RET_STATUS status; + struct net_device_stats *stats; + ETH_FUNC_RET_STATUS release_result; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + stats = port_private->stats; + + /* Update packet info data structure */ + pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ + pkt_info.byte_cnt = dataSize; + pkt_info.buf_ptr = (unsigned int) dataPtr; + + status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); + if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { + printf ("Error on transmitting packet .."); + if (status == ETH_QUEUE_FULL) + printf ("ETH Queue is full. \n"); + if (status == ETH_QUEUE_LAST_RESOURCE) + printf ("ETH Queue: using last available resource. \n"); + goto error; + } + + /* Update statistics and start of transmittion time */ + stats->tx_bytes += dataSize; + stats->tx_packets++; + + /* Check if packet(s) is(are) transmitted correctly (release everything) */ + do { + release_result = + eth_tx_return_desc (ethernet_private, ETH_Q0, + &pkt_info); + switch (release_result) { + case ETH_OK: + DP (printf ("descriptor released\n")); + if (pkt_info.cmd_sts & BIT0) { + printf ("Error in TX\n"); + stats->tx_errors++; + + } + break; + case ETH_RETRY: + DP (printf ("transmission still in process\n")); + break; + + case ETH_ERROR: + printf ("routine can not access Tx desc ring\n"); + break; + + case ETH_END_OF_JOB: + DP (printf ("the routine has nothing to release\n")); + break; + default: /* should not happen */ + break; + } + } while (release_result == ETH_OK); + + + return 0; /* success */ + error: + return 1; /* Failed - higher layers will free the skb */ +} + +/********************************************************************** + * mv64460_eth_receive + * + * This function is forward packets that are received from the port's + * queues toward kernel core or FastRoute them to another interface. + * + * Input : dev - a pointer to the required interface + * max - maximum number to receive (0 means unlimted) + * + * Output : number of served packets + **********************************************************************/ + +int mv64460_eth_receive (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + unsigned int port_num; + PKT_INFO pkt_info; + struct net_device_stats *stats; + + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + stats = port_private->stats; + + while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == + ETH_OK)) { + +#ifdef DEBUG_MV_ETH + if (pkt_info.byte_cnt != 0) { + printf ("%s: Received %d byte Packet @ 0x%x\n", + __FUNCTION__, pkt_info.byte_cnt, + pkt_info.buf_ptr); + } +#endif + /* Update statistics. Note byte count includes 4 byte CRC count */ + stats->rx_packets++; + stats->rx_bytes += pkt_info.byte_cnt; + + /* + * In case received a packet without first / last bits on OR the error + * summary bit is on, the packets needs to be dropeed. + */ + if (((pkt_info. + cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != + (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) + || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { + stats->rx_dropped++; + + printf ("Received packet spread on multiple descriptors\n"); + + /* Is this caused by an error ? */ + if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { + stats->rx_errors++; + } + + /* free these descriptors again without forwarding them to the higher layers */ + pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ + pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ + + if (eth_rx_return_buff + (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { + printf ("Error while returning the RX Desc to Ring\n"); + } else { + DP (printf ("RX Desc returned to Ring\n")); + } + /* /free these descriptors again */ + } else { + +/* !!! call higher layer processing */ +#ifdef DEBUG_MV_ETH + printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); +#endif + /* let the upper layer handle the packet */ + NetReceive ((uchar *) pkt_info.buf_ptr, + (int) pkt_info.byte_cnt); + +/* **************************************************************** */ +/* free descriptor */ + pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ + pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ + DP (printf + ("RX: pkt_info.buf_ptr = %x\n", + pkt_info.buf_ptr)); + if (eth_rx_return_buff + (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { + printf ("Error while returning the RX Desc to Ring\n"); + } else { + DP (printf ("RX Desc returned to Ring\n")); + } + +/* **************************************************************** */ + + } + } + mv64460_eth_get_stats (dev); /* update statistics */ + return 1; +} + +/********************************************************************** + * mv64460_eth_get_stats + * + * Returns a pointer to the interface statistics. + * + * Input : dev - a pointer to the required interface + * + * Output : a pointer to the interface's statistics + **********************************************************************/ + +static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + mv64460_eth_update_stat (dev); + + return port_private->stats; +} + + +/********************************************************************** + * mv64460_eth_update_stat + * + * Update the statistics structure in the private data structure + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + **********************************************************************/ + +static void mv64460_eth_update_stat (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + struct net_device_stats *stats; + unsigned int port_num; + volatile unsigned int dummy; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + stats = port_private->stats; + + /* These are false updates */ + stats->rx_packets += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_FRAMES_RECEIVED); + stats->tx_packets += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_FRAMES_SENT); + stats->rx_bytes += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); + /* + * Ideally this should be as follows - + * + * stats->rx_bytes += stats->rx_bytes + + * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , + * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); + * + * But the unsigned long in PowerPC and MIPS are 32bit. So the next read + * is just a dummy read for proper work of the GigE port + */ + dummy = eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); + stats->tx_bytes += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_SENT_LOW); + dummy = eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_SENT_HIGH); + stats->rx_errors += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_MAC_RECEIVE_ERROR); + + /* Rx dropped is for received packet with CRC error */ + stats->rx_dropped += + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_BAD_CRC_EVENT); + stats->multicast += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_MULTICAST_FRAMES_RECEIVED); + stats->collisions += + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_COLLISION) + + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_LATE_COLLISION); + /* detailed rx errors */ + stats->rx_length_errors += + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_UNDERSIZE_RECEIVED) + + + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_OVERSIZE_RECEIVED); + /* detailed tx errors */ +} + +#ifndef UPDATE_STATS_BY_SOFTWARE +/********************************************************************** + * mv64460_eth_print_stat + * + * Update the statistics structure in the private data structure + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + **********************************************************************/ + +static void mv64460_eth_print_stat (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64460_eth_priv *port_private; + struct net_device_stats *stats; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64460_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + stats = port_private->stats; + + /* These are false updates */ + printf ("\n### Network statistics: ###\n"); + printf ("--------------------------\n"); + printf (" Packets received: %ld\n", stats->rx_packets); + printf (" Packets send: %ld\n", stats->tx_packets); + printf (" Received bytes: %ld\n", stats->rx_bytes); + printf (" Send bytes: %ld\n", stats->tx_bytes); + if (stats->rx_errors != 0) + printf (" Rx Errors: %ld\n", + stats->rx_errors); + if (stats->rx_dropped != 0) + printf (" Rx dropped (CRC Errors): %ld\n", + stats->rx_dropped); + if (stats->multicast != 0) + printf (" Rx mulicast frames: %ld\n", + stats->multicast); + if (stats->collisions != 0) + printf (" No. of collisions: %ld\n", + stats->collisions); + if (stats->rx_length_errors != 0) + printf (" Rx length errors: %ld\n", + stats->rx_length_errors); +} +#endif + +/************************************************************************** + *network_start - Network Kick Off Routine UBoot + *Inputs : + *Outputs : + **************************************************************************/ + +bool db64460_eth_start (struct eth_device *dev) +{ + return (mv64460_eth_open (dev)); /* calls real open */ +} + +/************************************************************************* +************************************************************************** +************************************************************************** +* The second part is the low level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ +/* + * based on Linux code + * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +/******************************************************************************** + * Marvell's Gigabit Ethernet controller low level driver + * + * DESCRIPTION: + * This file introduce low level API to Marvell's Gigabit Ethernet + * controller. This Gigabit Ethernet Controller driver API controls + * 1) Operations (i.e. port init, start, reset etc'). + * 2) Data flow (i.e. port send, receive etc'). + * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO + * struct. + * This struct includes user configuration information as well as + * driver internal data needed for its operations. + * + * Supported Features: + * - This low level driver is OS independent. Allocating memory for + * the descriptor rings and buffers are not within the scope of + * this driver. + * - The user is free from Rx/Tx queue managing. + * - This low level driver introduce functionality API that enable + * the to operate Marvell's Gigabit Ethernet Controller in a + * convenient way. + * - Simple Gigabit Ethernet port operation API. + * - Simple Gigabit Ethernet port data flow API. + * - Data flow and operation API support per queue functionality. + * - Support cached descriptors for better performance. + * - Enable access to all four DRAM banks and internal SRAM memory + * spaces. + * - PHY access and control API. + * - Port control register configuration API. + * - Full control over Unicast and Multicast MAC configurations. + * + * Operation flow: + * + * Initialization phase + * This phase complete the initialization of the ETH_PORT_INFO + * struct. + * User information regarding port configuration has to be set + * prior to calling the port initialization routine. For example, + * the user has to assign the port_phy_addr field which is board + * depended parameter. + * In this phase any port Tx/Rx activity is halted, MIB counters + * are cleared, PHY address is set according to user parameter and + * access to DRAM and internal SRAM memory spaces. + * + * Driver ring initialization + * Allocating memory for the descriptor rings and buffers is not + * within the scope of this driver. Thus, the user is required to + * allocate memory for the descriptors ring and buffers. Those + * memory parameters are used by the Rx and Tx ring initialization + * routines in order to curve the descriptor linked list in a form + * of a ring. + * Note: Pay special attention to alignment issues when using + * cached descriptors/buffers. In this phase the driver store + * information in the ETH_PORT_INFO struct regarding each queue + * ring. + * + * Driver start + * This phase prepares the Ethernet port for Rx and Tx activity. + * It uses the information stored in the ETH_PORT_INFO struct to + * initialize the various port registers. + * + * Data flow: + * All packet references to/from the driver are done using PKT_INFO + * struct. + * This struct is a unified struct used with Rx and Tx operations. + * This way the user is not required to be familiar with neither + * Tx nor Rx descriptors structures. + * The driver's descriptors rings are management by indexes. + * Those indexes controls the ring resources and used to indicate + * a SW resource error: + * 'current' + * This index points to the current available resource for use. For + * example in Rx process this index will point to the descriptor + * that will be passed to the user upon calling the receive routine. + * In Tx process, this index will point to the descriptor + * that will be assigned with the user packet info and transmitted. + * 'used' + * This index points to the descriptor that need to restore its + * resources. For example in Rx process, using the Rx buffer return + * API will attach the buffer returned in packet info to the + * descriptor pointed by 'used'. In Tx process, using the Tx + * descriptor return will merely return the user packet info with + * the command status of the transmitted buffer pointed by the + * 'used' index. Nevertheless, it is essential to use this routine + * to update the 'used' index. + * 'first' + * This index supports Tx Scatter-Gather. It points to the first + * descriptor of a packet assembled of multiple buffers. For example + * when in middle of Such packet we have a Tx resource error the + * 'curr' index get the value of 'first' to indicate that the ring + * returned to its state before trying to transmit this packet. + * + * Receive operation: + * The eth_port_receive API set the packet information struct, + * passed by the caller, with received information from the + * 'current' SDMA descriptor. + * It is the user responsibility to return this resource back + * to the Rx descriptor ring to enable the reuse of this source. + * Return Rx resource is done using the eth_rx_return_buff API. + * + * Transmit operation: + * The eth_port_send API supports Scatter-Gather which enables to + * send a packet spanned over multiple buffers. This means that + * for each packet info structure given by the user and put into + * the Tx descriptors ring, will be transmitted only if the 'LAST' + * bit will be set in the packet info command status field. This + * API also consider restriction regarding buffer alignments and + * sizes. + * The user must return a Tx resource after ensuring the buffer + * has been transmitted to enable the Tx ring indexes to update. + * + * BOARD LAYOUT + * This device is on-board. No jumper diagram is necessary. + * + * EXTERNAL INTERFACE + * + * Prior to calling the initialization routine eth_port_init() the user + * must set the following fields under ETH_PORT_INFO struct: + * port_num User Ethernet port number. + * port_phy_addr User PHY address of Ethernet port. + * port_mac_addr[6] User defined port MAC address. + * port_config User port configuration value. + * port_config_extend User port config extend value. + * port_sdma_config User port SDMA config value. + * port_serial_control User port serial control value. + * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. + * *port_private User scratch pad for user specific data structures. + * + * This driver introduce a set of default values: + * PORT_CONFIG_VALUE Default port configuration value + * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value + * PORT_SDMA_CONFIG_VALUE Default sdma control value + * PORT_SERIAL_CONTROL_VALUE Default port serial control value + * + * This driver data flow is done using the PKT_INFO struct which is + * a unified struct for Rx and Tx operations: + * byte_cnt Tx/Rx descriptor buffer byte count. + * l4i_chk CPU provided TCP Checksum. For Tx operation only. + * cmd_sts Tx/Rx descriptor command status. + * buf_ptr Tx/Rx descriptor buffer pointer. + * return_info Tx/Rx user resource return information. + * + * + * EXTERNAL SUPPORT REQUIREMENTS + * + * This driver requires the following external support: + * + * D_CACHE_FLUSH_LINE (address, address offset) + * + * This macro applies assembly code to flush and invalidate cache + * line. + * address - address base. + * address offset - address offset + * + * + * CPU_PIPE_FLUSH + * + * This macro applies assembly code to flush the CPU pipeline. + * + *******************************************************************************/ +/* includes */ + +/* defines */ +/* SDMA command macros */ +#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ + MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) + +#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ + MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ + (1 << (8 + tx_queue))) + +#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ +MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) + +#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ +MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) + +#define CURR_RFD_GET(p_curr_desc, queue) \ + ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) + +#define CURR_RFD_SET(p_curr_desc, queue) \ + (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) + +#define USED_RFD_GET(p_used_desc, queue) \ + ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) + +#define USED_RFD_SET(p_used_desc, queue)\ +(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) + + +#define CURR_TFD_GET(p_curr_desc, queue) \ + ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) + +#define CURR_TFD_SET(p_curr_desc, queue) \ + (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) + +#define USED_TFD_GET(p_used_desc, queue) \ + ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) + +#define USED_TFD_SET(p_used_desc, queue) \ + (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) + +#define FIRST_TFD_GET(p_first_desc, queue) \ + ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) + +#define FIRST_TFD_SET(p_first_desc, queue) \ + (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) + + +/* Macros that save access to desc in order to find next desc pointer */ +#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + +#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + +#define LINK_UP_TIMEOUT 100000 +#define PHY_BUSY_TIMEOUT 10000000 + +/* locals */ + +/* PHY routines */ +static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); +static int ethernet_phy_get (ETH_PORT eth_port_num); + +/* Ethernet Port routines */ +static void eth_set_access_control (ETH_PORT eth_port_num, + ETH_WIN_PARAM * param); +static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, + ETH_QUEUE queue, int option); +#if 0 /* FIXME */ +static bool eth_port_smc_addr (ETH_PORT eth_port_num, + unsigned char mc_byte, + ETH_QUEUE queue, int option); +static bool eth_port_omc_addr (ETH_PORT eth_port_num, + unsigned char crc8, + ETH_QUEUE queue, int option); +#endif + +static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, + int byte_count); + +void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); + + +typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; +u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) +{ + u32 result = 0; + u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); + + if (enable & (1 << bank)) + return 0; + if (bank == BANK0) + result = MV_REG_READ (MV64460_CS_0_BASE_ADDR); + if (bank == BANK1) + result = MV_REG_READ (MV64460_CS_1_BASE_ADDR); + if (bank == BANK2) + result = MV_REG_READ (MV64460_CS_2_BASE_ADDR); + if (bank == BANK3) + result = MV_REG_READ (MV64460_CS_3_BASE_ADDR); + result &= 0x0000ffff; + result = result << 16; + return result; +} + +u32 mv_get_dram_bank_size (MEMORY_BANK bank) +{ + u32 result = 0; + u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); + + if (enable & (1 << bank)) + return 0; + if (bank == BANK0) + result = MV_REG_READ (MV64460_CS_0_SIZE); + if (bank == BANK1) + result = MV_REG_READ (MV64460_CS_1_SIZE); + if (bank == BANK2) + result = MV_REG_READ (MV64460_CS_2_SIZE); + if (bank == BANK3) + result = MV_REG_READ (MV64460_CS_3_SIZE); + result += 1; + result &= 0x0000ffff; + result = result << 16; + return result; +} + +u32 mv_get_internal_sram_base (void) +{ + u32 result; + + result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR); + result &= 0x0000ffff; + result = result << 16; + return result; +} + +/******************************************************************************* +* eth_port_init - Initialize the Ethernet port driver +* +* DESCRIPTION: +* This function prepares the ethernet port to start its activity: +* 1) Completes the ethernet port driver struct initialization toward port +* start routine. +* 2) Resets the device to a quiescent state in case of warm reboot. +* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. +* 4) Clean MAC tables. The reset status of those tables is unknown. +* 5) Set PHY address. +* Note: Call this routine prior to eth_port_start routine and after setting +* user values in the user fields of Ethernet port control struct (i.e. +* port_phy_addr). +* +* INPUT: +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* +* OUTPUT: +* See description. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) +{ + int queue; + ETH_WIN_PARAM win_param; + + p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; + p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; + p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; + p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; + + p_eth_port_ctrl->port_rx_queue_command = 0; + p_eth_port_ctrl->port_tx_queue_command = 0; + + /* Zero out SW structs */ + for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { + CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); + USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); + p_eth_port_ctrl->rx_resource_err[queue] = false; + } + + for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { + CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); + USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); + FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); + p_eth_port_ctrl->tx_resource_err[queue] = false; + } + + eth_port_reset (p_eth_port_ctrl->port_num); + + /* Set access parameters for DRAM bank 0 */ + win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); + win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for DRAM bank 1 */ + win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); + win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for DRAM bank 2 */ + win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); + win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for DRAM bank 3 */ + win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); + win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for Internal SRAM */ + win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ + win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ + win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; + win_param.high_addr = 0; + win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ + win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */ + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + eth_port_init_mac_tables (p_eth_port_ctrl->port_num); + + ethernet_phy_set (p_eth_port_ctrl->port_num, + p_eth_port_ctrl->port_phy_addr); + + return; + +} + +/******************************************************************************* +* eth_port_start - Start the Ethernet port activity. +* +* DESCRIPTION: +* This routine prepares the Ethernet port for Rx and Tx activity: +* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that +* has been initialized a descriptor's ring (using ether_init_tx_desc_ring +* for Tx and ether_init_rx_desc_ring for Rx) +* 2. Initialize and enable the Ethernet configuration port by writing to +* the port's configuration and command registers. +* 3. Initialize and enable the SDMA by writing to the SDMA's +* configuration and command registers. +* After completing these steps, the ethernet port SDMA can starts to +* perform Rx and Tx activities. +* +* Note: Each Rx and Tx queue descriptor's list must be initialized prior +* to calling this function (use ether_init_tx_desc_ring for Tx queues and +* ether_init_rx_desc_ring for Rx queues). +* +* INPUT: +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* +* OUTPUT: +* Ethernet port is ready to receive and transmit. +* +* RETURN: +* false if the port PHY is not up. +* true otherwise. +* +*******************************************************************************/ +static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) +{ + int queue; + volatile ETH_TX_DESC *p_tx_curr_desc; + volatile ETH_RX_DESC *p_rx_curr_desc; + unsigned int phy_reg_data; + ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; + + + /* Assignment of Tx CTRP of given queue */ + for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { + CURR_TFD_GET (p_tx_curr_desc, queue); + MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 + (eth_port_num) + + (4 * queue)), + ((unsigned int) p_tx_curr_desc)); + + } + + /* Assignment of Rx CRDP of given queue */ + for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { + CURR_RFD_GET (p_rx_curr_desc, queue); + MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 + (eth_port_num) + + (4 * queue)), + ((unsigned int) p_rx_curr_desc)); + + if (p_rx_curr_desc != NULL) + /* Add the assigned Ethernet address to the port's address table */ + eth_port_uc_addr_set (p_eth_port_ctrl->port_num, + p_eth_port_ctrl->port_mac_addr, + queue); + } + + /* Assign port configuration and command. */ + MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), + p_eth_port_ctrl->port_config); + + MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), + p_eth_port_ctrl->port_config_extend); + + MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), + p_eth_port_ctrl->port_serial_control); + + MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), + ETH_SERIAL_PORT_ENABLE); + + /* Assign port SDMA configuration */ + MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), + p_eth_port_ctrl->port_sdma_config); + + MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT + (eth_port_num), 0x3fffffff); + MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG + (eth_port_num), 0x03fffcff); + /* Turn off the port/queue bandwidth limitation */ + MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); + + /* Enable port Rx. */ + MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), + p_eth_port_ctrl->port_rx_queue_command); + + /* Check if link is up */ + eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); + + if (!(phy_reg_data & 0x20)) + return false; + + return true; +} + +/******************************************************************************* +* eth_port_uc_addr_set - This function Set the port Unicast address. +* +* DESCRIPTION: +* This function Set the port Ethernet MAC address. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* char * p_addr Address to be set +* ETH_QUEUE queue Rx queue number for this MAC address. +* +* OUTPUT: +* Set MAC address low and high registers. also calls eth_port_uc_addr() +* To set the unicast table with the proper information. +* +* RETURN: +* N/A. +* +*******************************************************************************/ +static void eth_port_uc_addr_set (ETH_PORT eth_port_num, + unsigned char *p_addr, ETH_QUEUE queue) +{ + unsigned int mac_h; + unsigned int mac_l; + + mac_l = (p_addr[4] << 8) | (p_addr[5]); + mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | + (p_addr[2] << 8) | (p_addr[3] << 0); + + MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); + MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); + + /* Accept frames of this address */ + eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); + + return; +} + +/******************************************************************************* +* eth_port_uc_addr - This function Set the port unicast address table +* +* DESCRIPTION: +* This function locates the proper entry in the Unicast table for the +* specified MAC nibble and sets its properties according to function +* parameters. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char uc_nibble Unicast MAC Address last nibble. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* This function add/removes MAC addresses from the port unicast address +* table. +* +* RETURN: +* true is output succeeded. +* false if option parameter is invalid. +* +*******************************************************************************/ +static bool eth_port_uc_addr (ETH_PORT eth_port_num, + unsigned char uc_nibble, + ETH_QUEUE queue, int option) +{ + unsigned int unicast_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the Unicast table entry */ + uc_nibble = (0xf & uc_nibble); + tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ + reg_offset = uc_nibble % 4; /* Entry offset within the above register */ + + switch (option) { + case REJECT_MAC_ADDR: + /* Clear accepts frame bit at specified unicast DA table entry */ + unicast_reg = + MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset)); + + unicast_reg &= (0x0E << (8 * reg_offset)); + + MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset), unicast_reg); + break; + + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at unicast DA filter table entry */ + unicast_reg = + MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset)); + + unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); + + MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset), unicast_reg); + + break; + + default: + return false; + } + return true; +} + +#if 0 /* FIXME */ +/******************************************************************************* +* eth_port_mc_addr - Multicast address settings. +* +* DESCRIPTION: +* This API controls the MV device MAC multicast support. +* The MV device supports multicast using two tables: +* 1) Special Multicast Table for MAC addresses of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* In this case, the function calls eth_port_smc_addr() routine to set the +* Special Multicast Table. +* 2) Other Multicast Table for multicast of another type. A CRC-8bit +* is used as an index to the Other Multicast Table entries in the +* DA-Filter table. +* In this case, the function calculates the CRC-8bit value and calls +* eth_port_omc_addr() routine to set the Other Multicast Table. +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char *p_addr Unicast MAC Address. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* true is output succeeded. +* false if add_address_table_entry( ) failed. +* +*******************************************************************************/ +static void eth_port_mc_addr (ETH_PORT eth_port_num, + unsigned char *p_addr, + ETH_QUEUE queue, int option) +{ + unsigned int mac_h; + unsigned int mac_l; + unsigned char crc_result = 0; + int mac_array[48]; + int crc[8]; + int i; + + + if ((p_addr[0] == 0x01) && + (p_addr[1] == 0x00) && + (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) + + eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); + else { + /* Calculate CRC-8 out of the given address */ + mac_h = (p_addr[0] << 8) | (p_addr[1]); + mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | + (p_addr[4] << 8) | (p_addr[5] << 0); + + for (i = 0; i < 32; i++) + mac_array[i] = (mac_l >> i) & 0x1; + for (i = 32; i < 48; i++) + mac_array[i] = (mac_h >> (i - 32)) & 0x1; + + + crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ + mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ + mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ + mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ + mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ + mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ + mac_array[6] ^ mac_array[0]; + + crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ + mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ + mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ + mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ + mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ + mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ + mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ + mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ + mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ + mac_array[0]; + + crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ + mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ + mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ + mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ + mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ + mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ + mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ + mac_array[2] ^ mac_array[1] ^ mac_array[0]; + + crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ + mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ + mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ + mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ + mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ + mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ + mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ + mac_array[2] ^ mac_array[1]; + + crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ + mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ + mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ + mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ + mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ + mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ + mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ + mac_array[2]; + + crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ + mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ + mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ + mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ + mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ + mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ + mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ + mac_array[3]; + + crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ + mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ + mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ + mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ + mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ + mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ + mac_array[6] ^ mac_array[5] ^ mac_array[4]; + + crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ + mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ + mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ + mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ + mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ + mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ + mac_array[6] ^ mac_array[5]; + + for (i = 0; i < 8; i++) + crc_result = crc_result | (crc[i] << i); + + eth_port_omc_addr (eth_port_num, crc_result, queue, option); + } + return; +} + +/******************************************************************************* +* eth_port_smc_addr - Special Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device special MAC multicast support. +* The Special Multicast Table for MAC addresses supports MAC of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* This function set the Special Multicast Table appropriate entry +* according to the argument given. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* true is output succeeded. +* false if option parameter is invalid. +* +*******************************************************************************/ +static bool eth_port_smc_addr (ETH_PORT eth_port_num, + unsigned char mc_byte, + ETH_QUEUE queue, int option) +{ + unsigned int smc_table_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the SMC table entry */ + tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ + reg_offset = mc_byte % 4; /* Entry offset within the above register */ + queue &= 0x7; + + switch (option) { + case REJECT_MAC_ADDR: + /* Clear accepts frame bit at specified Special DA table entry */ + smc_table_reg = + MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + smc_table_reg &= (0x0E << (8 * reg_offset)); + + MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); + break; + + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at specified Special DA table entry */ + smc_table_reg = + MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); + + MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); + break; + + default: + return false; + } + return true; +} + +/******************************************************************************* +* eth_port_omc_addr - Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device Other MAC multicast support. +* The Other Multicast Table is used for multicast of another type. +* A CRC-8bit is used as an index to the Other Multicast Table entries +* in the DA-Filter table. +* The function gets the CRC-8bit value from the calling routine and +* set the Other Multicast Table appropriate entry according to the +* CRC-8 argument given. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* true is output succeeded. +* false if option parameter is invalid. +* +*******************************************************************************/ +static bool eth_port_omc_addr (ETH_PORT eth_port_num, + unsigned char crc8, + ETH_QUEUE queue, int option) +{ + unsigned int omc_table_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the OMC table entry */ + tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ + reg_offset = crc8 % 4; /* Entry offset within the above register */ + queue &= 0x7; + + switch (option) { + case REJECT_MAC_ADDR: + /* Clear accepts frame bit at specified Other DA table entry */ + omc_table_reg = + MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + omc_table_reg &= (0x0E << (8 * reg_offset)); + + MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); + break; + + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at specified Other DA table entry */ + omc_table_reg = + MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); + + MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); + break; + + default: + return false; + } + return true; +} +#endif + +/******************************************************************************* +* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables +* +* DESCRIPTION: +* Go through all the DA filter tables (Unicast, Special Multicast & Other +* Multicast) and set each entry to 0. +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* +* OUTPUT: +* Multicast and Unicast packets are rejected. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void eth_port_init_mac_tables (ETH_PORT eth_port_num) +{ + int table_index; + + /* Clear DA filter unicast table (Ex_dFUT) */ + for (table_index = 0; table_index <= 0xC; table_index += 4) + MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + table_index), 0); + + for (table_index = 0; table_index <= 0xFC; table_index += 4) { + /* Clear DA filter special multicast table (Ex_dFSMT) */ + MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); + /* Clear DA filter other multicast table (Ex_dFOMT) */ + MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); + } +} + +/******************************************************************************* +* eth_clear_mib_counters - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters of a specific ethernet port. +* A read from the MIB counter will reset the counter. +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* +* OUTPUT: +* After reading all MIB counters, the counters resets. +* +* RETURN: +* MIB counter value. +* +*******************************************************************************/ +static void eth_clear_mib_counters (ETH_PORT eth_port_num) +{ + int i; + unsigned int dummy; + + /* Perform dummy reads from MIB counters */ + for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; + i += 4) + dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE + (eth_port_num) + i)); + + return; +} + +/******************************************************************************* +* eth_read_mib_counter - Read a MIB counter +* +* DESCRIPTION: +* This function reads a MIB counter of a specific ethernet port. +* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the +* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH +* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and +* ETH_MIB_GOOD_OCTETS_SENT_HIGH +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). +* +* OUTPUT: +* After reading the MIB counter, the counter resets. +* +* RETURN: +* MIB counter value. +* +*******************************************************************************/ +unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, + unsigned int mib_offset) +{ + return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num) + + mib_offset)); +} + +/******************************************************************************* +* ethernet_phy_set - Set the ethernet port PHY address. +* +* DESCRIPTION: +* This routine set the ethernet port PHY address according to given +* parameter. +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* +* OUTPUT: +* Set PHY Address Register with given PHY address parameter. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) +{ + unsigned int reg_data; + + reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); + + reg_data &= ~(0x1F << (5 * eth_port_num)); + reg_data |= (phy_addr << (5 * eth_port_num)); + + MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data); + + return; +} + +/******************************************************************************* + * ethernet_phy_get - Get the ethernet port PHY address. + * + * DESCRIPTION: + * This routine returns the given ethernet port PHY address. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * None. + * + * RETURN: + * PHY address. + * + *******************************************************************************/ +static int ethernet_phy_get (ETH_PORT eth_port_num) +{ + unsigned int reg_data; + + reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); + + return ((reg_data >> (5 * eth_port_num)) & 0x1f); +} + +/******************************************************************************* + * ethernet_phy_reset - Reset Ethernet port PHY. + * + * DESCRIPTION: + * This routine utilize the SMI interface to reset the ethernet port PHY. + * The routine waits until the link is up again or link up is timeout. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * The ethernet port PHY renew its link. + * + * RETURN: + * None. + * +*******************************************************************************/ +static bool ethernet_phy_reset (ETH_PORT eth_port_num) +{ + unsigned int time_out = 50; + unsigned int phy_reg_data; + + /* Reset the PHY */ + eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); + phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ + eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); + + /* Poll on the PHY LINK */ + do { + eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); + + if (time_out-- == 0) + return false; + } + while (!(phy_reg_data & 0x20)); + + return true; +} + +/******************************************************************************* + * eth_port_reset - Reset Ethernet port + * + * DESCRIPTION: + * This routine resets the chip by aborting any SDMA engine activity and + * clearing the MIB counters. The Receiver and the Transmit unit are in + * idle state after this command is performed and the port is disabled. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * Channel activity is halted. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void eth_port_reset (ETH_PORT eth_port_num) +{ + unsigned int reg_data; + + /* Stop Tx port activity. Check port Tx activity. */ + reg_data = + MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG + (eth_port_num)); + + if (reg_data & 0xFF) { + /* Issue stop command for active channels only */ + MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG + (eth_port_num), (reg_data << 8)); + + /* Wait for all Tx activity to terminate. */ + do { + /* Check port cause register that all Tx queues are stopped */ + reg_data = + MV_REG_READ + (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG + (eth_port_num)); + } + while (reg_data & 0xFF); + } + + /* Stop Rx port activity. Check port Rx activity. */ + reg_data = + MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG + (eth_port_num)); + + if (reg_data & 0xFF) { + /* Issue stop command for active channels only */ + MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG + (eth_port_num), (reg_data << 8)); + + /* Wait for all Rx activity to terminate. */ + do { + /* Check port cause register that all Rx queues are stopped */ + reg_data = + MV_REG_READ + (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG + (eth_port_num)); + } + while (reg_data & 0xFF); + } + + + /* Clear all MIB counters */ + eth_clear_mib_counters (eth_port_num); + + /* Reset the Enable bit in the Configuration Register */ + reg_data = + MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG + (eth_port_num)); + reg_data &= ~ETH_SERIAL_PORT_ENABLE; + MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), + reg_data); + + return; +} + +#if 0 /* Not needed here */ +/******************************************************************************* + * ethernet_set_config_reg - Set specified bits in configuration register. + * + * DESCRIPTION: + * This function sets specified bits in the given ethernet + * configuration register. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int value 32 bit value. + * + * OUTPUT: + * The set bits in the value parameter are set in the configuration + * register. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void ethernet_set_config_reg (ETH_PORT eth_port_num, + unsigned int value) +{ + unsigned int eth_config_reg; + + eth_config_reg = + MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num)); + eth_config_reg |= value; + MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), + eth_config_reg); + + return; +} +#endif + +#if 0 /* FIXME */ +/******************************************************************************* + * ethernet_reset_config_reg - Reset specified bits in configuration register. + * + * DESCRIPTION: + * This function resets specified bits in the given Ethernet + * configuration register. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int value 32 bit value. + * + * OUTPUT: + * The set bits in the value parameter are reset in the configuration + * register. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void ethernet_reset_config_reg (ETH_PORT eth_port_num, + unsigned int value) +{ + unsigned int eth_config_reg; + + eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG + (eth_port_num)); + eth_config_reg &= ~value; + MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), + eth_config_reg); + + return; +} +#endif + +#if 0 /* Not needed here */ +/******************************************************************************* + * ethernet_get_config_reg - Get the port configuration register + * + * DESCRIPTION: + * This function returns the configuration register value of the given + * ethernet port. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * None. + * + * RETURN: + * Port configuration register value. + * + *******************************************************************************/ +static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) +{ + unsigned int eth_config_reg; + + eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG + (eth_port_num)); + return eth_config_reg; +} + +#endif + +/******************************************************************************* + * eth_port_read_smi_reg - Read PHY registers + * + * DESCRIPTION: + * This routine utilize the SMI interface to interact with the PHY in + * order to perform PHY register read. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int phy_reg PHY register address offset. + * unsigned int *value Register value buffer. + * + * OUTPUT: + * Write the value of a specified PHY register into given buffer. + * + * RETURN: + * false if the PHY is busy or read data is not in valid state. + * true otherwise. + * + *******************************************************************************/ +static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, + unsigned int phy_reg, unsigned int *value) +{ + unsigned int reg_value; + unsigned int time_out = PHY_BUSY_TIMEOUT; + int phy_addr; + + phy_addr = ethernet_phy_get (eth_port_num); +/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ + + /* first check that it is not busy */ + do { + reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); + if (time_out-- == 0) { + return false; + } + } + while (reg_value & ETH_SMI_BUSY); + + /* not busy */ + + MV_REG_WRITE (MV64460_ETH_SMI_REG, + (phy_addr << 16) | (phy_reg << 21) | + ETH_SMI_OPCODE_READ); + + time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ + + do { + reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); + if (time_out-- == 0) { + return false; + } + } + while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ + + /* Wait for the data to update in the SMI register */ +#define PHY_UPDATE_TIMEOUT 10000 + for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); + + reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); + + *value = reg_value & 0xffff; + + return true; +} + +/******************************************************************************* + * eth_port_write_smi_reg - Write to PHY registers + * + * DESCRIPTION: + * This routine utilize the SMI interface to interact with the PHY in + * order to perform writes to PHY registers. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int phy_reg PHY register address offset. + * unsigned int value Register value. + * + * OUTPUT: + * Write the given value to the specified PHY register. + * + * RETURN: + * false if the PHY is busy. + * true otherwise. + * + *******************************************************************************/ +static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, + unsigned int phy_reg, unsigned int value) +{ + unsigned int reg_value; + unsigned int time_out = PHY_BUSY_TIMEOUT; + int phy_addr; + + phy_addr = ethernet_phy_get (eth_port_num); + + /* first check that it is not busy */ + do { + reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); + if (time_out-- == 0) { + return false; + } + } + while (reg_value & ETH_SMI_BUSY); + + /* not busy */ + MV_REG_WRITE (MV64460_ETH_SMI_REG, + (phy_addr << 16) | (phy_reg << 21) | + ETH_SMI_OPCODE_WRITE | (value & 0xffff)); + return true; +} + +/******************************************************************************* + * eth_set_access_control - Config address decode parameters for Ethernet unit + * + * DESCRIPTION: + * This function configures the address decode parameters for the Gigabit + * Ethernet Controller according the given parameters struct. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * ETH_WIN_PARAM *param Address decode parameter struct. + * + * OUTPUT: + * An access window is opened using the given access parameters. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void eth_set_access_control (ETH_PORT eth_port_num, + ETH_WIN_PARAM * param) +{ + unsigned int access_prot_reg; + + /* Set access control register */ + access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG + (eth_port_num)); + access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ + access_prot_reg |= (param->access_ctrl << (param->win * 2)); + MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num), + access_prot_reg); + + /* Set window Size reg (SR) */ + MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 + + (ETH_SIZE_REG_GAP * param->win)), + (((param->size / 0x10000) - 1) << 16)); + + /* Set window Base address reg (BA) */ + MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), + (param->target | param->attributes | param->base_addr)); + /* High address remap reg (HARR) */ + if (param->win < 4) + MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 + + (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), + param->high_addr); + + /* Base address enable reg (BARER) */ + if (param->enable == 1) + MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, + (1 << param->win)); + else + MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, + (1 << param->win)); +} + +/******************************************************************************* + * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. + * + * DESCRIPTION: + * This function prepares a Rx chained list of descriptors and packet + * buffers in a form of a ring. The routine must be called after port + * initialization routine and before port start routine. + * The Ethernet SDMA engine uses CPU bus addresses to access the various + * devices in the system (i.e. DRAM). This function uses the ethernet + * struct 'virtual to physical' routine (set by the user) to set the ring + * with physical addresses. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE rx_queue Number of Rx queue. + * int rx_desc_num Number of Rx descriptors + * int rx_buff_size Size of Rx buffer + * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. + * unsigned int rx_buff_base_addr Rx buffer memory area base addr. + * + * OUTPUT: + * The routine updates the Ethernet port control struct with information + * regarding the Rx descriptors and buffers. + * + * RETURN: + * false if the given descriptors memory area is not aligned according to + * Ethernet SDMA specifications. + * true otherwise. + * + *******************************************************************************/ +static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE rx_queue, + int rx_desc_num, + int rx_buff_size, + unsigned int rx_desc_base_addr, + unsigned int rx_buff_base_addr) +{ + ETH_RX_DESC *p_rx_desc; + ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ + unsigned int buffer_addr; + int ix; /* a counter */ + + + p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; + p_rx_prev_desc = p_rx_desc; + buffer_addr = rx_buff_base_addr; + + /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ + if (rx_buff_base_addr & 0xF) + return false; + + /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ + if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) + return false; + + /* Rx buffers must be 64-bit aligned. */ + if ((rx_buff_base_addr + rx_buff_size) & 0x7) + return false; + + /* initialize the Rx descriptors ring */ + for (ix = 0; ix < rx_desc_num; ix++) { + p_rx_desc->buf_size = rx_buff_size; + p_rx_desc->byte_cnt = 0x0000; + p_rx_desc->cmd_sts = + ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; + p_rx_desc->next_desc_ptr = + ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; + p_rx_desc->buf_ptr = buffer_addr; + p_rx_desc->return_info = 0x00000000; + D_CACHE_FLUSH_LINE (p_rx_desc, 0); + buffer_addr += rx_buff_size; + p_rx_prev_desc = p_rx_desc; + p_rx_desc = (ETH_RX_DESC *) + ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); + } + + /* Closing Rx descriptors ring */ + p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); + D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); + + /* Save Rx desc pointer to driver struct. */ + CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); + USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); + + p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = + (ETH_RX_DESC *) rx_desc_base_addr; + p_eth_port_ctrl->rx_desc_area_size[rx_queue] = + rx_desc_num * RX_DESC_ALIGNED_SIZE; + + p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); + + return true; +} + +/******************************************************************************* + * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. + * + * DESCRIPTION: + * This function prepares a Tx chained list of descriptors and packet + * buffers in a form of a ring. The routine must be called after port + * initialization routine and before port start routine. + * The Ethernet SDMA engine uses CPU bus addresses to access the various + * devices in the system (i.e. DRAM). This function uses the ethernet + * struct 'virtual to physical' routine (set by the user) to set the ring + * with physical addresses. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE tx_queue Number of Tx queue. + * int tx_desc_num Number of Tx descriptors + * int tx_buff_size Size of Tx buffer + * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. + * unsigned int tx_buff_base_addr Tx buffer memory area base addr. + * + * OUTPUT: + * The routine updates the Ethernet port control struct with information + * regarding the Tx descriptors and buffers. + * + * RETURN: + * false if the given descriptors memory area is not aligned according to + * Ethernet SDMA specifications. + * true otherwise. + * + *******************************************************************************/ +static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE tx_queue, + int tx_desc_num, + int tx_buff_size, + unsigned int tx_desc_base_addr, + unsigned int tx_buff_base_addr) +{ + + ETH_TX_DESC *p_tx_desc; + ETH_TX_DESC *p_tx_prev_desc; + unsigned int buffer_addr; + int ix; /* a counter */ + + + /* save the first desc pointer to link with the last descriptor */ + p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; + p_tx_prev_desc = p_tx_desc; + buffer_addr = tx_buff_base_addr; + + /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ + if (tx_buff_base_addr & 0xF) + return false; + + /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ + if ((tx_buff_size > TX_BUFFER_MAX_SIZE) + || (tx_buff_size < TX_BUFFER_MIN_SIZE)) + return false; + + /* Initialize the Tx descriptors ring */ + for (ix = 0; ix < tx_desc_num; ix++) { + p_tx_desc->byte_cnt = 0x0000; + p_tx_desc->l4i_chk = 0x0000; + p_tx_desc->cmd_sts = 0x00000000; + p_tx_desc->next_desc_ptr = + ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; + + p_tx_desc->buf_ptr = buffer_addr; + p_tx_desc->return_info = 0x00000000; + D_CACHE_FLUSH_LINE (p_tx_desc, 0); + buffer_addr += tx_buff_size; + p_tx_prev_desc = p_tx_desc; + p_tx_desc = (ETH_TX_DESC *) + ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); + + } + /* Closing Tx descriptors ring */ + p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; + D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); + /* Set Tx desc pointer in driver struct. */ + CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); + USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); + + /* Init Tx ring base and size parameters */ + p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = + (ETH_TX_DESC *) tx_desc_base_addr; + p_eth_port_ctrl->tx_desc_area_size[tx_queue] = + (tx_desc_num * TX_DESC_ALIGNED_SIZE); + + /* Add the queue to the list of Tx queues of this port */ + p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); + + return true; +} + +/******************************************************************************* + * eth_port_send - Send an Ethernet packet + * + * DESCRIPTION: + * This routine send a given packet described by p_pktinfo parameter. It + * supports transmitting of a packet spaned over multiple buffers. The + * routine updates 'curr' and 'first' indexes according to the packet + * segment passed to the routine. In case the packet segment is first, + * the 'first' index is update. In any case, the 'curr' index is updated. + * If the routine get into Tx resource error it assigns 'curr' index as + * 'first'. This way the function can abort Tx process of multiple + * descriptors per packet. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE tx_queue Number of Tx queue. + * PKT_INFO *p_pkt_info User packet buffer. + * + * OUTPUT: + * Tx ring 'curr' and 'first' indexes are updated. + * + * RETURN: + * ETH_QUEUE_FULL in case of Tx resource error. + * ETH_ERROR in case the routine can not access Tx desc ring. + * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_TX_DESC *p_tx_desc_first; + volatile ETH_TX_DESC *p_tx_desc_curr; + volatile ETH_TX_DESC *p_tx_next_desc_curr; + volatile ETH_TX_DESC *p_tx_desc_used; + unsigned int command_status; + + /* Do not process Tx ring in case of Tx ring resource error */ + if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) + return ETH_QUEUE_FULL; + + /* Get the Tx Desc ring indexes */ + CURR_TFD_GET (p_tx_desc_curr, tx_queue); + USED_TFD_GET (p_tx_desc_used, tx_queue); + + if (p_tx_desc_curr == NULL) + return ETH_ERROR; + + /* The following parameters are used to save readings from memory */ + p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); + command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; + + if (command_status & (ETH_TX_FIRST_DESC)) { + /* Update first desc */ + FIRST_TFD_SET (p_tx_desc_curr, tx_queue); + p_tx_desc_first = p_tx_desc_curr; + } else { + FIRST_TFD_GET (p_tx_desc_first, tx_queue); + command_status |= ETH_BUFFER_OWNED_BY_DMA; + } + + /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ + /* boundary. We use the memory allocated for Tx descriptor. This memory */ + /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ + if (p_pkt_info->byte_cnt <= 8) { + printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ + return ETH_ERROR; + + p_tx_desc_curr->buf_ptr = + (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; + eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, + p_pkt_info->byte_cnt); + } else + p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; + + p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; + p_tx_desc_curr->return_info = p_pkt_info->return_info; + + if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { + /* Set last desc with DMA ownership and interrupt enable. */ + p_tx_desc_curr->cmd_sts = command_status | + ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; + + if (p_tx_desc_curr != p_tx_desc_first) + p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; + + /* Flush CPU pipe */ + + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); + CPU_PIPE_FLUSH; + + /* Apply send command */ + ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); + + /* Finish Tx packet. Update first desc in case of Tx resource error */ + p_tx_desc_first = p_tx_next_desc_curr; + FIRST_TFD_SET (p_tx_desc_first, tx_queue); + + } else { + p_tx_desc_curr->cmd_sts = command_status; + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); + } + + /* Check for ring index overlap in the Tx desc ring */ + if (p_tx_next_desc_curr == p_tx_desc_used) { + /* Update the current descriptor */ + CURR_TFD_SET (p_tx_desc_first, tx_queue); + + p_eth_port_ctrl->tx_resource_err[tx_queue] = true; + return ETH_QUEUE_LAST_RESOURCE; + } else { + /* Update the current descriptor */ + CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); + return ETH_OK; + } +} + +/******************************************************************************* + * eth_tx_return_desc - Free all used Tx descriptors + * + * DESCRIPTION: + * This routine returns the transmitted packet information to the caller. + * It uses the 'first' index to support Tx desc return in case a transmit + * of a packet spanned over multiple buffer still in process. + * In case the Tx queue was in "resource error" condition, where there are + * no available Tx resources, the function resets the resource error flag. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE tx_queue Number of Tx queue. + * PKT_INFO *p_pkt_info User packet buffer. + * + * OUTPUT: + * Tx ring 'first' and 'used' indexes are updated. + * + * RETURN: + * ETH_ERROR in case the routine can not access Tx desc ring. + * ETH_RETRY in case there is transmission in process. + * ETH_END_OF_JOB if the routine has nothing to release. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * + p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_TX_DESC *p_tx_desc_used = NULL; + volatile ETH_TX_DESC *p_tx_desc_first = NULL; + unsigned int command_status; + + + /* Get the Tx Desc ring indexes */ + USED_TFD_GET (p_tx_desc_used, tx_queue); + FIRST_TFD_GET (p_tx_desc_first, tx_queue); + + + /* Sanity check */ + if (p_tx_desc_used == NULL) + return ETH_ERROR; + + command_status = p_tx_desc_used->cmd_sts; + + /* Still transmitting... */ + if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); + return ETH_RETRY; + } + + /* Stop release. About to overlap the current available Tx descriptor */ + if ((p_tx_desc_used == p_tx_desc_first) && + (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); + return ETH_END_OF_JOB; + } + + /* Pass the packet information to the caller */ + p_pkt_info->cmd_sts = command_status; + p_pkt_info->return_info = p_tx_desc_used->return_info; + p_tx_desc_used->return_info = 0; + + /* Update the next descriptor to release. */ + USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); + + /* Any Tx return cancels the Tx resource error status */ + if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) + p_eth_port_ctrl->tx_resource_err[tx_queue] = false; + + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); + + return ETH_OK; + +} + +/******************************************************************************* + * eth_port_receive - Get received information from Rx ring. + * + * DESCRIPTION: + * This routine returns the received data to the caller. There is no + * data copying during routine operation. All information is returned + * using pointer to packet information struct passed from the caller. + * If the routine exhausts Rx ring resources then the resource error flag + * is set. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE rx_queue Number of Rx queue. + * PKT_INFO *p_pkt_info User packet buffer. + * + * OUTPUT: + * Rx ring current and used indexes are updated. + * + * RETURN: + * ETH_ERROR in case the routine can not access Rx desc ring. + * ETH_QUEUE_FULL if Rx ring resources are exhausted. + * ETH_END_OF_JOB if there is no received data. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_RX_DESC *p_rx_curr_desc; + volatile ETH_RX_DESC *p_rx_next_curr_desc; + volatile ETH_RX_DESC *p_rx_used_desc; + unsigned int command_status; + + /* Do not process Rx ring in case of Rx ring resource error */ + if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { + printf ("\nRx Queue is full ...\n"); + return ETH_QUEUE_FULL; + } + + /* Get the Rx Desc ring 'curr and 'used' indexes */ + CURR_RFD_GET (p_rx_curr_desc, rx_queue); + USED_RFD_GET (p_rx_used_desc, rx_queue); + + /* Sanity check */ + if (p_rx_curr_desc == NULL) + return ETH_ERROR; + + /* The following parameters are used to save readings from memory */ + p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); + command_status = p_rx_curr_desc->cmd_sts; + + /* Nothing to receive... */ + if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { +/* DP(printf("Rx: command_status: %08x\n", command_status)); */ + D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); +/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ + return ETH_END_OF_JOB; + } + + p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; + p_pkt_info->cmd_sts = command_status; + p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; + p_pkt_info->return_info = p_rx_curr_desc->return_info; + p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ + + /* Clean the return info field to indicate that the packet has been */ + /* moved to the upper layers */ + p_rx_curr_desc->return_info = 0; + + /* Update 'curr' in data structure */ + CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); + + /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ + if (p_rx_next_curr_desc == p_rx_used_desc) + p_eth_port_ctrl->rx_resource_err[rx_queue] = true; + + D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); + CPU_PIPE_FLUSH; + return ETH_OK; +} + +/******************************************************************************* + * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. + * + * DESCRIPTION: + * This routine returns a Rx buffer back to the Rx ring. It retrieves the + * next 'used' descriptor and attached the returned buffer to it. + * In case the Rx ring was in "resource error" condition, where there are + * no available Rx resources, the function resets the resource error flag. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE rx_queue Number of Rx queue. + * PKT_INFO *p_pkt_info Information on the returned buffer. + * + * OUTPUT: + * New available Rx resource in Rx descriptor ring. + * + * RETURN: + * ETH_ERROR in case the routine can not access Rx desc ring. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * + p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ + + /* Get 'used' Rx descriptor */ + USED_RFD_GET (p_used_rx_desc, rx_queue); + + /* Sanity check */ + if (p_used_rx_desc == NULL) + return ETH_ERROR; + + p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; + p_used_rx_desc->return_info = p_pkt_info->return_info; + p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; + p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */ + + /* Flush the write pipe */ + CPU_PIPE_FLUSH; + + /* Return the descriptor to DMA ownership */ + p_used_rx_desc->cmd_sts = + ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; + + /* Flush descriptor and CPU pipe */ + D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); + CPU_PIPE_FLUSH; + + /* Move the used descriptor pointer to the next descriptor */ + USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); + + /* Any Rx return cancels the Rx resource error status */ + if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) + p_eth_port_ctrl->rx_resource_err[rx_queue] = false; + + return ETH_OK; +} + +/******************************************************************************* + * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path + * + * DESCRIPTION: + * This routine sets the RX coalescing interrupt mechanism parameter. + * This parameter is a timeout counter, that counts in 64 t_clk + * chunks ; that when timeout event occurs a maskable interrupt + * occurs. + * The parameter is calculated using the tClk of the MV-643xx chip + * , and the required delay of the interrupt in usec. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet port number + * unsigned int t_clk t_clk of the MV-643xx chip in HZ units + * unsigned int delay Delay in usec + * + * OUTPUT: + * Interrupt coalescing mechanism value is set in MV-643xx chip. + * + * RETURN: + * The interrupt coalescing value set in the gigE port. + * + *******************************************************************************/ +#if 0 /* FIXME */ +static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, + unsigned int t_clk, + unsigned int delay) +{ + unsigned int coal; + + coal = ((t_clk / 1000000) * delay) / 64; + /* Set RX Coalescing mechanism */ + MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), + ((coal & 0x3fff) << 8) | + (MV_REG_READ + (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num)) + & 0xffc000ff)); + return coal; +} + +#endif +/******************************************************************************* + * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path + * + * DESCRIPTION: + * This routine sets the TX coalescing interrupt mechanism parameter. + * This parameter is a timeout counter, that counts in 64 t_clk + * chunks ; that when timeout event occurs a maskable interrupt + * occurs. + * The parameter is calculated using the t_cLK frequency of the + * MV-643xx chip and the required delay in the interrupt in uSec + * + * INPUT: + * ETH_PORT eth_port_num Ethernet port number + * unsigned int t_clk t_clk of the MV-643xx chip in HZ units + * unsigned int delay Delay in uSeconds + * + * OUTPUT: + * Interrupt coalescing mechanism value is set in MV-643xx chip. + * + * RETURN: + * The interrupt coalescing value set in the gigE port. + * + *******************************************************************************/ +#if 0 /* FIXME */ +static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, + unsigned int t_clk, + unsigned int delay) +{ + unsigned int coal; + + coal = ((t_clk / 1000000) * delay) / 64; + /* Set TX Coalescing mechanism */ + MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), + coal << 4); + return coal; +} +#endif + +/******************************************************************************* + * eth_b_copy - Copy bytes from source to destination + * + * DESCRIPTION: + * This function supports the eight bytes limitation on Tx buffer size. + * The routine will zero eight bytes starting from the destination address + * followed by copying bytes from the source address to the destination. + * + * INPUT: + * unsigned int src_addr 32 bit source address. + * unsigned int dst_addr 32 bit destination address. + * int byte_count Number of bytes to copy. + * + * OUTPUT: + * See description. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, + int byte_count) +{ + /* Zero the dst_addr area */ + *(unsigned int *) dst_addr = 0x0; + + while (byte_count != 0) { + *(char *) dst_addr = *(char *) src_addr; + dst_addr++; + src_addr++; + byte_count--; + } +} diff --git a/board/Marvell/db64460/mv_eth.h b/board/Marvell/db64460/mv_eth.h new file mode 100644 index 0000000..b4e498b --- /dev/null +++ b/board/Marvell/db64460/mv_eth.h @@ -0,0 +1,840 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64460X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mv_eth.h - header file for the polled mode GT ethernet driver + */ + +#ifndef __DB64460_ETH_H__ +#define __DB64460_ETH_H__ + +#include +#include +#include +#include +#include +#include "mv_regs.h" +#include "../common/ppc_error_no.h" + + +/************************************************************************* +************************************************************************** +************************************************************************** +* The first part is the high level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ +#ifndef MAX_SKB_FRAGS +#define MAX_SKB_FRAGS 0 +#endif + +/* Port attributes */ +/*#define MAX_RX_QUEUE_NUM 8*/ +/*#define MAX_TX_QUEUE_NUM 8*/ +#define MAX_RX_QUEUE_NUM 1 +#define MAX_TX_QUEUE_NUM 1 + + +/* Use one TX queue and one RX queue */ +#define MV64460_TX_QUEUE_NUM 1 +#define MV64460_RX_QUEUE_NUM 1 + +/* + * Number of RX / TX descriptors on RX / TX rings. + * Note that allocating RX descriptors is done by allocating the RX + * ring AND a preallocated RX buffers (skb's) for each descriptor. + * The TX descriptors only allocates the TX descriptors ring, + * with no pre allocated TX buffers (skb's are allocated by higher layers. + */ + +/* Default TX ring size is 10 descriptors */ +#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE +#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE +#else +#define MV64460_TX_QUEUE_SIZE 4 +#endif + +/* Default RX ring size is 4 descriptors */ +#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE +#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE +#else +#define MV64460_RX_QUEUE_SIZE 4 +#endif + +#ifdef CONFIG_RX_BUFFER_SIZE +#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE +#else +#define MV64460_RX_BUFFER_SIZE 1600 +#endif + +#ifdef CONFIG_TX_BUFFER_SIZE +#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE +#else +#define MV64460_TX_BUFFER_SIZE 1600 +#endif + +/* + * Network device statistics. Akin to the 2.0 ether stats but + * with byte counters. + */ + +struct net_device_stats +{ + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_errors; /* bad packets received */ + unsigned long tx_errors; /* packet transmit problems */ + unsigned long rx_dropped; /* no space in linux buffers */ + unsigned long tx_dropped; /* no space available in linux */ + unsigned long multicast; /* multicast packets received */ + unsigned long collisions; + + /* detailed rx_errors: */ + unsigned long rx_length_errors; + unsigned long rx_over_errors; /* receiver ring buff overflow */ + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_frame_errors; /* recv'd frame alignment error */ + unsigned long rx_fifo_errors; /* recv'r fifo overrun */ + unsigned long rx_missed_errors; /* receiver missed packet */ + + /* detailed tx_errors */ + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; + + /* for cslip etc */ + unsigned long rx_compressed; + unsigned long tx_compressed; +}; + + +/* Private data structure used for ethernet device */ +struct mv64460_eth_priv { + unsigned int port_num; + struct net_device_stats *stats; + +/* to buffer area aligned */ + char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ + char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ + + /* Size of Tx Ring per queue */ + unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; + + + /* Size of Rx Ring per queue */ + unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; + + /* Magic Number for Ethernet running */ + unsigned int eth_running; + +}; + +int mv64460_eth_init (struct eth_device *dev); +int mv64460_eth_stop (struct eth_device *dev); +int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length); +/* return db64460_eth0_poll(); */ + +int mv64460_eth_open (struct eth_device *dev); + + +/************************************************************************* +************************************************************************** +************************************************************************** +* The second part is the low level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ + + +/******************************************************************************** + * Header File for : MV-643xx network interface header + * + * DESCRIPTION: + * This header file contains macros typedefs and function declaration for + * the Marvell Gig Bit Ethernet Controller. + * + * DEPENDENCIES: + * None. + * + *******************************************************************************/ + + +#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY +#ifdef CONFIG_MV64460_SRAM_CACHEABLE +/* In case SRAM is cacheable but not cache coherent */ +#define D_CACHE_FLUSH_LINE(addr, offset) \ +{ \ + __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ +} +#else +/* In case SRAM is cache coherent or non-cacheable */ +#define D_CACHE_FLUSH_LINE(addr, offset) ; +#endif +#else +#ifdef CONFIG_NOT_COHERENT_CACHE +/* In case of descriptors on DDR but not cache coherent */ +#define D_CACHE_FLUSH_LINE(addr, offset) \ +{ \ + __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ +} +#else +/* In case of descriptors on DDR and cache coherent */ +#define D_CACHE_FLUSH_LINE(addr, offset) ; +#endif /* CONFIG_NOT_COHERENT_CACHE */ +#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ + + +#define CPU_PIPE_FLUSH \ +{ \ + __asm__ __volatile__ ("eieio"); \ +} + + +/* defines */ + +/* Default port configuration value */ +#define PORT_CONFIG_VALUE \ + ETH_UNICAST_NORMAL_MODE | \ + ETH_DEFAULT_RX_QUEUE_0 | \ + ETH_DEFAULT_RX_ARP_QUEUE_0 | \ + ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ + ETH_RECEIVE_BC_IF_IP | \ + ETH_RECEIVE_BC_IF_ARP | \ + ETH_CAPTURE_TCP_FRAMES_DIS | \ + ETH_CAPTURE_UDP_FRAMES_DIS | \ + ETH_DEFAULT_RX_TCP_QUEUE_0 | \ + ETH_DEFAULT_RX_UDP_QUEUE_0 | \ + ETH_DEFAULT_RX_BPDU_QUEUE_0 + +/* Default port extend configuration value */ +#define PORT_CONFIG_EXTEND_VALUE \ + ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ + ETH_PARTITION_DISABLE + + +/* Default sdma control value */ +#ifdef CONFIG_NOT_COHERENT_CACHE +#define PORT_SDMA_CONFIG_VALUE \ + ETH_RX_BURST_SIZE_16_64BIT | \ + GT_ETH_IPG_INT_RX(0) | \ + ETH_TX_BURST_SIZE_16_64BIT; +#else +#define PORT_SDMA_CONFIG_VALUE \ + ETH_RX_BURST_SIZE_4_64BIT | \ + GT_ETH_IPG_INT_RX(0) | \ + ETH_TX_BURST_SIZE_4_64BIT; +#endif + +#define GT_ETH_IPG_INT_RX(value) \ + ((value & 0x3fff) << 8) + +/* Default port serial control value */ +#define PORT_SERIAL_CONTROL_VALUE \ + ETH_FORCE_LINK_PASS | \ + ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ + ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ + ETH_ADV_SYMMETRIC_FLOW_CTRL | \ + ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + ETH_FORCE_BP_MODE_NO_JAM | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL | \ + ETH_RETRANSMIT_16_ETTEMPTS | \ + ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ + ETH_DTE_ADV_0 | \ + ETH_DISABLE_AUTO_NEG_BYPASS | \ + ETH_AUTO_NEG_NO_CHANGE | \ + ETH_MAX_RX_PACKET_1552BYTE | \ + ETH_CLR_EXT_LOOPBACK | \ + ETH_SET_FULL_DUPLEX_MODE | \ + ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; + +#define RX_BUFFER_MAX_SIZE 0xFFFF +#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ + +#define RX_BUFFER_MIN_SIZE 0x8 +#define TX_BUFFER_MIN_SIZE 0x8 + +/* Tx WRR confoguration macros */ +#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ +#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ +#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ + +/* MAC accepet/reject macros */ +#define ACCEPT_MAC_ADDR 0 +#define REJECT_MAC_ADDR 1 + +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define RX_DESC_ALIGNED_SIZE 0x20 +#define TX_DESC_ALIGNED_SIZE 0x20 + +/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ +#define TX_BUF_OFFSET_IN_DESC 0x18 +/* Buffer offset from buffer pointer */ +#define RX_BUF_OFFSET 0x2 + +/* Gap define */ +#define ETH_BAR_GAP 0x8 +#define ETH_SIZE_REG_GAP 0x8 +#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 +#define ETH_PORT_ACCESS_CTRL_GAP 0x4 + +/* Gigabit Ethernet Unit Global Registers */ + +/* MIB Counters register definitions */ +#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 +#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 +#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 +#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc +#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 +#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 +#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 +#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c +#define ETH_MIB_FRAMES_64_OCTETS 0x20 +#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 +#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 +#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c +#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 +#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 +#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 +#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c +#define ETH_MIB_GOOD_FRAMES_SENT 0x40 +#define ETH_MIB_EXCESSIVE_COLLISION 0x44 +#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 +#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c +#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 +#define ETH_MIB_FC_SENT 0x54 +#define ETH_MIB_GOOD_FC_RECEIVED 0x58 +#define ETH_MIB_BAD_FC_RECEIVED 0x5c +#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 +#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 +#define ETH_MIB_OVERSIZE_RECEIVED 0x68 +#define ETH_MIB_JABBER_RECEIVED 0x6c +#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 +#define ETH_MIB_BAD_CRC_EVENT 0x74 +#define ETH_MIB_COLLISION 0x78 +#define ETH_MIB_LATE_COLLISION 0x7c + +/* Port serial status reg (PSR) */ +#define ETH_INTERFACE_GMII_MII 0 +#define ETH_INTERFACE_PCM BIT0 +#define ETH_LINK_IS_DOWN 0 +#define ETH_LINK_IS_UP BIT1 +#define ETH_PORT_AT_HALF_DUPLEX 0 +#define ETH_PORT_AT_FULL_DUPLEX BIT2 +#define ETH_RX_FLOW_CTRL_DISABLED 0 +#define ETH_RX_FLOW_CTRL_ENBALED BIT3 +#define ETH_GMII_SPEED_100_10 0 +#define ETH_GMII_SPEED_1000 BIT4 +#define ETH_MII_SPEED_10 0 +#define ETH_MII_SPEED_100 BIT5 +#define ETH_NO_TX 0 +#define ETH_TX_IN_PROGRESS BIT7 +#define ETH_BYPASS_NO_ACTIVE 0 +#define ETH_BYPASS_ACTIVE BIT8 +#define ETH_PORT_NOT_AT_PARTITION_STATE 0 +#define ETH_PORT_AT_PARTITION_STATE BIT9 +#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 +#define ETH_PORT_TX_FIFO_EMPTY BIT10 + + +/* These macros describes the Port configuration reg (Px_cR) bits */ +#define ETH_UNICAST_NORMAL_MODE 0 +#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 +#define ETH_DEFAULT_RX_QUEUE_0 0 +#define ETH_DEFAULT_RX_QUEUE_1 BIT1 +#define ETH_DEFAULT_RX_QUEUE_2 BIT2 +#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) +#define ETH_DEFAULT_RX_QUEUE_4 BIT3 +#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) +#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) +#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) +#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 +#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 +#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 +#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) +#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 +#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) +#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) +#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) +#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 +#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 +#define ETH_RECEIVE_BC_IF_IP 0 +#define ETH_REJECT_BC_IF_IP BIT8 +#define ETH_RECEIVE_BC_IF_ARP 0 +#define ETH_REJECT_BC_IF_ARP BIT9 +#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 +#define ETH_CAPTURE_TCP_FRAMES_DIS 0 +#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 +#define ETH_CAPTURE_UDP_FRAMES_DIS 0 +#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 +#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 +#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 +#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 +#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) +#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 +#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) +#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) +#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) +#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 +#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 +#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 +#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) +#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 +#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) +#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) +#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) +#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 +#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 +#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 +#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) +#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 +#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) +#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) +#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) + + +/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ +#define ETH_CLASSIFY_EN BIT0 +#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 +#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 +#define ETH_PARTITION_DISABLE 0 +#define ETH_PARTITION_ENABLE BIT2 + + +/* Tx/Rx queue command reg (RQCR/TQCR)*/ +#define ETH_QUEUE_0_ENABLE BIT0 +#define ETH_QUEUE_1_ENABLE BIT1 +#define ETH_QUEUE_2_ENABLE BIT2 +#define ETH_QUEUE_3_ENABLE BIT3 +#define ETH_QUEUE_4_ENABLE BIT4 +#define ETH_QUEUE_5_ENABLE BIT5 +#define ETH_QUEUE_6_ENABLE BIT6 +#define ETH_QUEUE_7_ENABLE BIT7 +#define ETH_QUEUE_0_DISABLE BIT8 +#define ETH_QUEUE_1_DISABLE BIT9 +#define ETH_QUEUE_2_DISABLE BIT10 +#define ETH_QUEUE_3_DISABLE BIT11 +#define ETH_QUEUE_4_DISABLE BIT12 +#define ETH_QUEUE_5_DISABLE BIT13 +#define ETH_QUEUE_6_DISABLE BIT14 +#define ETH_QUEUE_7_DISABLE BIT15 + +/* These macros describes the Port Sdma configuration reg (SDCR) bits */ +#define ETH_RIFB BIT0 +#define ETH_RX_BURST_SIZE_1_64BIT 0 +#define ETH_RX_BURST_SIZE_2_64BIT BIT1 +#define ETH_RX_BURST_SIZE_4_64BIT BIT2 +#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) +#define ETH_RX_BURST_SIZE_16_64BIT BIT3 +#define ETH_BLM_RX_NO_SWAP BIT4 +#define ETH_BLM_RX_BYTE_SWAP 0 +#define ETH_BLM_TX_NO_SWAP BIT5 +#define ETH_BLM_TX_BYTE_SWAP 0 +#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 +#define ETH_DESCRIPTORS_NO_SWAP 0 +#define ETH_TX_BURST_SIZE_1_64BIT 0 +#define ETH_TX_BURST_SIZE_2_64BIT BIT22 +#define ETH_TX_BURST_SIZE_4_64BIT BIT23 +#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) +#define ETH_TX_BURST_SIZE_16_64BIT BIT24 + +/* These macros describes the Port serial control reg (PSCR) bits */ +#define ETH_SERIAL_PORT_DISABLE 0 +#define ETH_SERIAL_PORT_ENABLE BIT0 +#define ETH_FORCE_LINK_PASS BIT1 +#define ETH_DO_NOT_FORCE_LINK_PASS 0 +#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 +#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 +#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 +#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 +#define ETH_ADV_NO_FLOW_CTRL 0 +#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 +#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 +#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 +#define ETH_FORCE_BP_MODE_NO_JAM 0 +#define ETH_FORCE_BP_MODE_JAM_TX BIT7 +#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 +#define ETH_FORCE_LINK_FAIL 0 +#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 +#define ETH_RETRANSMIT_16_ETTEMPTS 0 +#define ETH_RETRANSMIT_FOREVER BIT11 +#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 +#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 +#define ETH_DTE_ADV_0 0 +#define ETH_DTE_ADV_1 BIT14 +#define ETH_DISABLE_AUTO_NEG_BYPASS 0 +#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 +#define ETH_AUTO_NEG_NO_CHANGE 0 +#define ETH_RESTART_AUTO_NEG BIT16 +#define ETH_MAX_RX_PACKET_1518BYTE 0 +#define ETH_MAX_RX_PACKET_1522BYTE BIT17 +#define ETH_MAX_RX_PACKET_1552BYTE BIT18 +#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) +#define ETH_MAX_RX_PACKET_9192BYTE BIT19 +#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) +#define ETH_SET_EXT_LOOPBACK BIT20 +#define ETH_CLR_EXT_LOOPBACK 0 +#define ETH_SET_FULL_DUPLEX_MODE BIT21 +#define ETH_SET_HALF_DUPLEX_MODE 0 +#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 +#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 +#define ETH_SET_GMII_SPEED_TO_10_100 0 +#define ETH_SET_GMII_SPEED_TO_1000 BIT23 +#define ETH_SET_MII_SPEED_TO_10 0 +#define ETH_SET_MII_SPEED_TO_100 BIT24 + + +/* SMI reg */ +#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ +#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ +#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ +#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ + +/* SDMA command status fields macros */ + +/* Tx & Rx descriptors status */ +#define ETH_ERROR_SUMMARY (BIT0) + +/* Tx & Rx descriptors command */ +#define ETH_BUFFER_OWNED_BY_DMA (BIT31) + +/* Tx descriptors status */ +#define ETH_LC_ERROR (0 ) +#define ETH_UR_ERROR (BIT1 ) +#define ETH_RL_ERROR (BIT2 ) +#define ETH_LLC_SNAP_FORMAT (BIT9 ) + +/* Rx descriptors status */ +#define ETH_CRC_ERROR (0 ) +#define ETH_OVERRUN_ERROR (BIT1 ) +#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) +#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) +#define ETH_VLAN_TAGGED (BIT19) +#define ETH_BPDU_FRAME (BIT20) +#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) +#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) +#define ETH_OTHER_FRAME_TYPE (BIT22) +#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) +#define ETH_FRAME_TYPE_IP_V_4 (BIT24) +#define ETH_FRAME_HEADER_OK (BIT25) +#define ETH_RX_LAST_DESC (BIT26) +#define ETH_RX_FIRST_DESC (BIT27) +#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) +#define ETH_RX_ENABLE_INTERRUPT (BIT29) +#define ETH_LAYER_4_CHECKSUM_OK (BIT30) + +/* Rx descriptors byte count */ +#define ETH_FRAME_FRAGMENTED (BIT2) + +/* Tx descriptors command */ +#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) +#define ETH_FRAME_SET_TO_VLAN (BIT15) +#define ETH_TCP_FRAME (0 ) +#define ETH_UDP_FRAME (BIT16) +#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) +#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) +#define ETH_ZERO_PADDING (BIT19) +#define ETH_TX_LAST_DESC (BIT20) +#define ETH_TX_FIRST_DESC (BIT21) +#define ETH_GEN_CRC (BIT22) +#define ETH_TX_ENABLE_INTERRUPT (BIT23) +#define ETH_AUTO_MODE (BIT30) + +/* Address decode parameters */ +/* Ethernet Base Address Register bits */ +#define EBAR_TARGET_DRAM 0x00000000 +#define EBAR_TARGET_DEVICE 0x00000001 +#define EBAR_TARGET_CBS 0x00000002 +#define EBAR_TARGET_PCI0 0x00000003 +#define EBAR_TARGET_PCI1 0x00000004 +#define EBAR_TARGET_CUNIT 0x00000005 +#define EBAR_TARGET_AUNIT 0x00000006 +#define EBAR_TARGET_GUNIT 0x00000007 + +/* Window attributes */ +#define EBAR_ATTR_DRAM_CS0 0x00000E00 +#define EBAR_ATTR_DRAM_CS1 0x00000D00 +#define EBAR_ATTR_DRAM_CS2 0x00000B00 +#define EBAR_ATTR_DRAM_CS3 0x00000700 + +/* DRAM Target interface */ +#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 +#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 +#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 + +/* Device Bus Target interface */ +#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 +#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 +#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 +#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 +#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 + +/* PCI Target interface */ +#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 +#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 +#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 +#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 +#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 +#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 +#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 +#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 +#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 +#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 + +/* CPU 60x bus or internal SRAM interface */ +#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 +#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 +#define EBAR_ATTR_CBS_SRAM 0x00000000 +#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 + +/* Window access control */ +#define EWIN_ACCESS_NOT_ALLOWED 0 +#define EWIN_ACCESS_READ_ONLY BIT0 +#define EWIN_ACCESS_FULL (BIT1 | BIT0) +#define EWIN0_ACCESS_MASK 0x0003 +#define EWIN1_ACCESS_MASK 0x000C +#define EWIN2_ACCESS_MASK 0x0030 +#define EWIN3_ACCESS_MASK 0x00C0 + +/* typedefs */ + +typedef enum _eth_port +{ + ETH_0 = 0, + ETH_1 = 1, + ETH_2 = 2 +}ETH_PORT; + +typedef enum _eth_func_ret_status +{ + ETH_OK, /* Returned as expected. */ + ETH_ERROR, /* Fundamental error. */ + ETH_RETRY, /* Could not process request. Try later. */ + ETH_END_OF_JOB, /* Ring has nothing to process. */ + ETH_QUEUE_FULL, /* Ring resource error. */ + ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ +}ETH_FUNC_RET_STATUS; + +typedef enum _eth_queue +{ + ETH_Q0 = 0, + ETH_Q1 = 1, + ETH_Q2 = 2, + ETH_Q3 = 3, + ETH_Q4 = 4, + ETH_Q5 = 5, + ETH_Q6 = 6, + ETH_Q7 = 7 +} ETH_QUEUE; + +typedef enum _addr_win +{ + ETH_WIN0, + ETH_WIN1, + ETH_WIN2, + ETH_WIN3, + ETH_WIN4, + ETH_WIN5 +} ETH_ADDR_WIN; + +typedef enum _eth_target +{ + ETH_TARGET_DRAM , + ETH_TARGET_DEVICE, + ETH_TARGET_CBS , + ETH_TARGET_PCI0 , + ETH_TARGET_PCI1 +}ETH_TARGET; + +typedef struct _eth_rx_desc +{ + unsigned short byte_cnt ; /* Descriptor buffer byte count */ + unsigned short buf_size ; /* Buffer size */ + unsigned int cmd_sts ; /* Descriptor command status */ + unsigned int next_desc_ptr; /* Next descriptor pointer */ + unsigned int buf_ptr ; /* Descriptor buffer pointer */ + unsigned int return_info ; /* User resource return information */ +} ETH_RX_DESC; + + +typedef struct _eth_tx_desc +{ + unsigned short byte_cnt ; /* Descriptor buffer byte count */ + unsigned short l4i_chk ; /* CPU provided TCP Checksum */ + unsigned int cmd_sts ; /* Descriptor command status */ + unsigned int next_desc_ptr; /* Next descriptor pointer */ + unsigned int buf_ptr ; /* Descriptor buffer pointer */ + unsigned int return_info ; /* User resource return information */ +} ETH_TX_DESC; + +/* Unified struct for Rx and Tx operations. The user is not required to */ +/* be familier with neither Tx nor Rx descriptors. */ +typedef struct _pkt_info +{ + unsigned short byte_cnt ; /* Descriptor buffer byte count */ + unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ + unsigned int cmd_sts ; /* Descriptor command status */ + unsigned int buf_ptr ; /* Descriptor buffer pointer */ + unsigned int return_info ; /* User resource return information */ +} PKT_INFO; + + +typedef struct _eth_win_param +{ + ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ + ETH_TARGET target; /* System targets. See ETH_TARGET enum */ + unsigned short attributes; /* BAR attributes. See above macros. */ + unsigned int base_addr; /* Window base address in unsigned int form */ + unsigned int high_addr; /* Window high address in unsigned int form */ + unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ + bool enable; /* Enable/disable access to the window. */ + unsigned short access_ctrl; /* Access ctrl register. see above macros */ +} ETH_WIN_PARAM; + + +/* Ethernet port specific infomation */ + +typedef struct _eth_port_ctrl +{ + ETH_PORT port_num; /* User Ethernet port number */ + int port_phy_addr; /* User phy address of Ethrnet port */ + unsigned char port_mac_addr[6]; /* User defined port MAC address. */ + unsigned int port_config; /* User port configuration value */ + unsigned int port_config_extend; /* User port config extend value */ + unsigned int port_sdma_config; /* User port SDMA config value */ + unsigned int port_serial_control; /* User port serial control value */ + unsigned int port_tx_queue_command; /* Port active Tx queues summary */ + unsigned int port_rx_queue_command; /* Port active Rx queues summary */ + + /* User function to cast virtual address to CPU bus address */ + unsigned int (*port_virt_to_phys)(unsigned int addr); + /* User scratch pad for user specific data structures */ + void *port_private; + + bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ + bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ + + /* Tx/Rx rings managment indexes fields. For driver use */ + + /* Next available Rx resource */ + volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; + /* Returning Rx resource */ + volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; + + /* Next available Tx resource */ + volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; + /* Returning Tx resource */ + volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; + /* An extra Tx index to support transmit of multiple buffers per packet */ + volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; + + /* Tx/Rx rings size and base variables fields. For driver use */ + + volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; + unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; + char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; + + volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; + unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; + char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; + +} ETH_PORT_INFO; + + +/* ethernet.h API list */ + +/* Port operation control routines */ +static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); +static void eth_port_reset(ETH_PORT eth_port_num); +static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); + + +/* Port MAC address routines */ +static void eth_port_uc_addr_set (ETH_PORT eth_port_num, + unsigned char *p_addr, + ETH_QUEUE queue); +#if 0 /* FIXME */ +static void eth_port_mc_addr (ETH_PORT eth_port_num, + unsigned char *p_addr, + ETH_QUEUE queue, + int option); +#endif + +/* PHY and MIB routines */ +static bool ethernet_phy_reset(ETH_PORT eth_port_num); + +static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, + unsigned int phy_reg, + unsigned int value); + +static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, + unsigned int phy_reg, + unsigned int* value); + +static void eth_clear_mib_counters(ETH_PORT eth_port_num); + +/* Port data flow control routines */ +static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO *p_pkt_info); +static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO *p_pkt_info); +static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO *p_pkt_info); +static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO *p_pkt_info); + + +static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE tx_queue, + int tx_desc_num, + int tx_buff_size, + unsigned int tx_desc_base_addr, + unsigned int tx_buff_base_addr); + +static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE rx_queue, + int rx_desc_num, + int rx_buff_size, + unsigned int rx_desc_base_addr, + unsigned int rx_buff_base_addr); + +#endif /* MV64460_ETH_ */ diff --git a/board/Marvell/db64460/mv_regs.h b/board/Marvell/db64460/mv_regs.h new file mode 100644 index 0000000..fb50bb6 --- /dev/null +++ b/board/Marvell/db64460/mv_regs.h @@ -0,0 +1,1124 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64460X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/******************************************************************************** +* gt64460r.h - GT-64460 Internal registers definition file. +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv_regsh +#define __INCmv_regsh + +#define MV64460 + +/* Supported by the Atlantis */ +#define MV64460_INCLUDE_PCI_1 +#define MV64460_INCLUDE_PCI_0_ARBITER +#define MV64460_INCLUDE_PCI_1_ARBITER +#define MV64460_INCLUDE_SNOOP_SUPPORT +#define MV64460_INCLUDE_P2P +#define MV64460_INCLUDE_ETH_PORT_2 +#define MV64460_INCLUDE_CPU_MAPPING +#define MV64460_INCLUDE_MPSC + +/* Not supported features */ +#undef INCLUDE_CNTMR_4_7 +#undef INCLUDE_DMA_4_7 + +/****************************************/ +/* Processor Address Space */ +/****************************************/ + +/* DDR SDRAM BAR and size registers */ + +#define MV64460_CS_0_BASE_ADDR 0x008 +#define MV64460_CS_0_SIZE 0x010 +#define MV64460_CS_1_BASE_ADDR 0x208 +#define MV64460_CS_1_SIZE 0x210 +#define MV64460_CS_2_BASE_ADDR 0x018 +#define MV64460_CS_2_SIZE 0x020 +#define MV64460_CS_3_BASE_ADDR 0x218 +#define MV64460_CS_3_SIZE 0x220 + +/* Devices BAR and size registers */ + +#define MV64460_DEV_CS0_BASE_ADDR 0x028 +#define MV64460_DEV_CS0_SIZE 0x030 +#define MV64460_DEV_CS1_BASE_ADDR 0x228 +#define MV64460_DEV_CS1_SIZE 0x230 +#define MV64460_DEV_CS2_BASE_ADDR 0x248 +#define MV64460_DEV_CS2_SIZE 0x250 +#define MV64460_DEV_CS3_BASE_ADDR 0x038 +#define MV64460_DEV_CS3_SIZE 0x040 +#define MV64460_BOOTCS_BASE_ADDR 0x238 +#define MV64460_BOOTCS_SIZE 0x240 + +/* PCI 0 BAR and size registers */ + +#define MV64460_PCI_0_IO_BASE_ADDR 0x048 +#define MV64460_PCI_0_IO_SIZE 0x050 +#define MV64460_PCI_0_MEMORY0_BASE_ADDR 0x058 +#define MV64460_PCI_0_MEMORY0_SIZE 0x060 +#define MV64460_PCI_0_MEMORY1_BASE_ADDR 0x080 +#define MV64460_PCI_0_MEMORY1_SIZE 0x088 +#define MV64460_PCI_0_MEMORY2_BASE_ADDR 0x258 +#define MV64460_PCI_0_MEMORY2_SIZE 0x260 +#define MV64460_PCI_0_MEMORY3_BASE_ADDR 0x280 +#define MV64460_PCI_0_MEMORY3_SIZE 0x288 + +/* PCI 1 BAR and size registers */ +#define MV64460_PCI_1_IO_BASE_ADDR 0x090 +#define MV64460_PCI_1_IO_SIZE 0x098 +#define MV64460_PCI_1_MEMORY0_BASE_ADDR 0x0a0 +#define MV64460_PCI_1_MEMORY0_SIZE 0x0a8 +#define MV64460_PCI_1_MEMORY1_BASE_ADDR 0x0b0 +#define MV64460_PCI_1_MEMORY1_SIZE 0x0b8 +#define MV64460_PCI_1_MEMORY2_BASE_ADDR 0x2a0 +#define MV64460_PCI_1_MEMORY2_SIZE 0x2a8 +#define MV64460_PCI_1_MEMORY3_BASE_ADDR 0x2b0 +#define MV64460_PCI_1_MEMORY3_SIZE 0x2b8 + +/* SRAM base address */ +#define MV64460_INTEGRATED_SRAM_BASE_ADDR 0x268 + +/* internal registers space base address */ +#define MV64460_INTERNAL_SPACE_BASE_ADDR 0x068 + +/* Enables the CS , DEV_CS , PCI 0 and PCI 1 + windows above */ +#define MV64460_BASE_ADDR_ENABLE 0x278 + +/****************************************/ +/* PCI remap registers */ +/****************************************/ + /* PCI 0 */ +#define MV64460_PCI_0_IO_ADDR_REMAP 0x0f0 +#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 +#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 +#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 +#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 +#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 +#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 +#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 +#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 + /* PCI 1 */ +#define MV64460_PCI_1_IO_ADDR_REMAP 0x108 +#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 +#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 +#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 +#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 +#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 +#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 +#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 +#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 + +#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 +#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 +#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 +#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 +#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 +#define MV64460_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 +#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 +#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 + +/****************************************/ +/* CPU Control Registers */ +/****************************************/ + +#define MV64460_CPU_CONFIG 0x000 +#define MV64460_CPU_MODE 0x120 +#define MV64460_CPU_MASTER_CONTROL 0x160 +#define MV64460_CPU_CROSS_BAR_CONTROL_LOW 0x150 +#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH 0x158 +#define MV64460_CPU_CROSS_BAR_TIMEOUT 0x168 + +/****************************************/ +/* SMP RegisterS */ +/****************************************/ + +#define MV64460_SMP_WHO_AM_I 0x200 +#define MV64460_SMP_CPU0_DOORBELL 0x214 +#define MV64460_SMP_CPU0_DOORBELL_CLEAR 0x21C +#define MV64460_SMP_CPU1_DOORBELL 0x224 +#define MV64460_SMP_CPU1_DOORBELL_CLEAR 0x22C +#define MV64460_SMP_CPU0_DOORBELL_MASK 0x234 +#define MV64460_SMP_CPU1_DOORBELL_MASK 0x23C +#define MV64460_SMP_SEMAPHOR0 0x244 +#define MV64460_SMP_SEMAPHOR1 0x24c +#define MV64460_SMP_SEMAPHOR2 0x254 +#define MV64460_SMP_SEMAPHOR3 0x25c +#define MV64460_SMP_SEMAPHOR4 0x264 +#define MV64460_SMP_SEMAPHOR5 0x26c +#define MV64460_SMP_SEMAPHOR6 0x274 +#define MV64460_SMP_SEMAPHOR7 0x27c + +/****************************************/ +/* CPU Sync Barrier Register */ +/****************************************/ + +#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 +#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 +#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 +#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 + +/****************************************/ +/* CPU Access Protect */ +/****************************************/ + +#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 +#define MV64460_CPU_PROTECT_WINDOW_0_SIZE 0x188 +#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 +#define MV64460_CPU_PROTECT_WINDOW_1_SIZE 0x198 +#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 +#define MV64460_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 +#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 +#define MV64460_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 + + +/****************************************/ +/* CPU Error Report */ +/****************************************/ + +#define MV64460_CPU_ERROR_ADDR_LOW 0x070 +#define MV64460_CPU_ERROR_ADDR_HIGH 0x078 +#define MV64460_CPU_ERROR_DATA_LOW 0x128 +#define MV64460_CPU_ERROR_DATA_HIGH 0x130 +#define MV64460_CPU_ERROR_PARITY 0x138 +#define MV64460_CPU_ERROR_CAUSE 0x140 +#define MV64460_CPU_ERROR_MASK 0x148 + +/****************************************/ +/* CPU Interface Debug Registers */ +/****************************************/ + +#define MV64460_PUNIT_SLAVE_DEBUG_LOW 0x360 +#define MV64460_PUNIT_SLAVE_DEBUG_HIGH 0x368 +#define MV64460_PUNIT_MASTER_DEBUG_LOW 0x370 +#define MV64460_PUNIT_MASTER_DEBUG_HIGH 0x378 +#define MV64460_PUNIT_MMASK 0x3e4 + +/****************************************/ +/* Integrated SRAM Registers */ +/****************************************/ + +#define MV64460_SRAM_CONFIG 0x380 +#define MV64460_SRAM_TEST_MODE 0X3F4 +#define MV64460_SRAM_ERROR_CAUSE 0x388 +#define MV64460_SRAM_ERROR_ADDR 0x390 +#define MV64460_SRAM_ERROR_ADDR_HIGH 0X3F8 +#define MV64460_SRAM_ERROR_DATA_LOW 0x398 +#define MV64460_SRAM_ERROR_DATA_HIGH 0x3a0 +#define MV64460_SRAM_ERROR_DATA_PARITY 0x3a8 + +/****************************************/ +/* SDRAM Configuration */ +/****************************************/ + +#define MV64460_SDRAM_CONFIG 0x1400 +#define MV64460_D_UNIT_CONTROL_LOW 0x1404 +#define MV64460_D_UNIT_CONTROL_HIGH 0x1424 +#define MV64460_SDRAM_TIMING_CONTROL_LOW 0x1408 +#define MV64460_SDRAM_TIMING_CONTROL_HIGH 0x140c +#define MV64460_SDRAM_ADDR_CONTROL 0x1410 +#define MV64460_SDRAM_OPEN_PAGES_CONTROL 0x1414 +#define MV64460_SDRAM_OPERATION 0x1418 +#define MV64460_SDRAM_MODE 0x141c +#define MV64460_EXTENDED_DRAM_MODE 0x1420 +#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 +#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 +#define MV64460_SDRAM_CROSS_BAR_TIMEOUT 0x1438 +#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 +#define MV64460_SDRAM_DATA_PADS_CALIBRATION 0x14c4 + +/****************************************/ +/* SDRAM Error Report */ +/****************************************/ + +#define MV64460_SDRAM_ERROR_DATA_LOW 0x1444 +#define MV64460_SDRAM_ERROR_DATA_HIGH 0x1440 +#define MV64460_SDRAM_ERROR_ADDR 0x1450 +#define MV64460_SDRAM_RECEIVED_ECC 0x1448 +#define MV64460_SDRAM_CALCULATED_ECC 0x144c +#define MV64460_SDRAM_ECC_CONTROL 0x1454 +#define MV64460_SDRAM_ECC_ERROR_COUNTER 0x1458 + +/******************************************/ +/* Controlled Delay Line (CDL) Registers */ +/******************************************/ + +#define MV64460_DFCDL_CONFIG0 0x1480 +#define MV64460_DFCDL_CONFIG1 0x1484 +#define MV64460_DLL_WRITE 0x1488 +#define MV64460_DLL_READ 0x148c +#define MV64460_SRAM_ADDR 0x1490 +#define MV64460_SRAM_DATA0 0x1494 +#define MV64460_SRAM_DATA1 0x1498 +#define MV64460_SRAM_DATA2 0x149c +#define MV64460_DFCL_PROBE 0x14a0 + +/******************************************/ +/* Debug Registers */ +/******************************************/ + +#define MV64460_DUNIT_DEBUG_LOW 0x1460 +#define MV64460_DUNIT_DEBUG_HIGH 0x1464 +#define MV64460_DUNIT_MMASK 0X1b40 + +/****************************************/ +/* Device Parameters */ +/****************************************/ + +#define MV64460_DEVICE_BANK0_PARAMETERS 0x45c +#define MV64460_DEVICE_BANK1_PARAMETERS 0x460 +#define MV64460_DEVICE_BANK2_PARAMETERS 0x464 +#define MV64460_DEVICE_BANK3_PARAMETERS 0x468 +#define MV64460_DEVICE_BOOT_BANK_PARAMETERS 0x46c +#define MV64460_DEVICE_INTERFACE_CONTROL 0x4c0 +#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 +#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc +#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 + +/****************************************/ +/* Device interrupt registers */ +/****************************************/ + +#define MV64460_DEVICE_INTERRUPT_CAUSE 0x4d0 +#define MV64460_DEVICE_INTERRUPT_MASK 0x4d4 +#define MV64460_DEVICE_ERROR_ADDR 0x4d8 +#define MV64460_DEVICE_ERROR_DATA 0x4dc +#define MV64460_DEVICE_ERROR_PARITY 0x4e0 + +/****************************************/ +/* Device debug registers */ +/****************************************/ + +#define MV64460_DEVICE_DEBUG_LOW 0x4e4 +#define MV64460_DEVICE_DEBUG_HIGH 0x4e8 +#define MV64460_RUNIT_MMASK 0x4f0 + +/****************************************/ +/* PCI Slave Address Decoding registers */ +/****************************************/ + +#define MV64460_PCI_0_CS_0_BANK_SIZE 0xc08 +#define MV64460_PCI_1_CS_0_BANK_SIZE 0xc88 +#define MV64460_PCI_0_CS_1_BANK_SIZE 0xd08 +#define MV64460_PCI_1_CS_1_BANK_SIZE 0xd88 +#define MV64460_PCI_0_CS_2_BANK_SIZE 0xc0c +#define MV64460_PCI_1_CS_2_BANK_SIZE 0xc8c +#define MV64460_PCI_0_CS_3_BANK_SIZE 0xd0c +#define MV64460_PCI_1_CS_3_BANK_SIZE 0xd8c +#define MV64460_PCI_0_DEVCS_0_BANK_SIZE 0xc10 +#define MV64460_PCI_1_DEVCS_0_BANK_SIZE 0xc90 +#define MV64460_PCI_0_DEVCS_1_BANK_SIZE 0xd10 +#define MV64460_PCI_1_DEVCS_1_BANK_SIZE 0xd90 +#define MV64460_PCI_0_DEVCS_2_BANK_SIZE 0xd18 +#define MV64460_PCI_1_DEVCS_2_BANK_SIZE 0xd98 +#define MV64460_PCI_0_DEVCS_3_BANK_SIZE 0xc14 +#define MV64460_PCI_1_DEVCS_3_BANK_SIZE 0xc94 +#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 +#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 +#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c +#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c +#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 +#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 +#define MV64460_PCI_0_P2P_I_O_BAR_SIZE 0xd24 +#define MV64460_PCI_1_P2P_I_O_BAR_SIZE 0xda4 +#define MV64460_PCI_0_CPU_BAR_SIZE 0xd28 +#define MV64460_PCI_1_CPU_BAR_SIZE 0xda8 +#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 +#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 +#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c +#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c +#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c +#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc +#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 +#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 +#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 +#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 +#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c +#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc +#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c +#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc +#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 +#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 +#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 +#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 +#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C +#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C +#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 +#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 +#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 +#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 +#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 +#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 +#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 +#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 +#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 +#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 +#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 +#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 +#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c +#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc +#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 +#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 +#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 +#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 +#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 +#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 +#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c +#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec +#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 +#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 +#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 +#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 +#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 +#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 +#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 +#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 +#define MV64460_PCI_0_ADDR_DECODE_CONTROL 0xd3c +#define MV64460_PCI_1_ADDR_DECODE_CONTROL 0xdbc +#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 +#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 +#define MV64460_PCI_0_HEADERS_RETARGET_BASE 0xF44 +#define MV64460_PCI_1_HEADERS_RETARGET_BASE 0xFc4 +#define MV64460_PCI_0_HEADERS_RETARGET_HIGH 0xF48 +#define MV64460_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 + +/***********************************/ +/* PCI Control Register Map */ +/***********************************/ + +#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 +#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 +#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C +#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C +#define MV64460_PCI_0_COMMAND 0xc00 +#define MV64460_PCI_1_COMMAND 0xc80 +#define MV64460_PCI_0_MODE 0xd00 +#define MV64460_PCI_1_MODE 0xd80 +#define MV64460_PCI_0_RETRY 0xc04 +#define MV64460_PCI_1_RETRY 0xc84 +#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 +#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 +#define MV64460_PCI_0_MSI_TRIGGER_TIMER 0xc38 +#define MV64460_PCI_1_MSI_TRIGGER_TIMER 0xcb8 +#define MV64460_PCI_0_ARBITER_CONTROL 0x1d00 +#define MV64460_PCI_1_ARBITER_CONTROL 0x1d80 +#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 +#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 +#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c +#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c +#define MV64460_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 +#define MV64460_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 +#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 +#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 +#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 +#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 +#define MV64460_PCI_0_P2P_CONFIG 0x1d14 +#define MV64460_PCI_1_P2P_CONFIG 0x1d94 + +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 +#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 +#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 +#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 +#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 +#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 +#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 +#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 + +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 +#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 +#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 +#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 +#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 +#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 +#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 +#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 + +/****************************************/ +/* PCI Configuration Access Registers */ +/****************************************/ + +#define MV64460_PCI_0_CONFIG_ADDR 0xcf8 +#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc +#define MV64460_PCI_1_CONFIG_ADDR 0xc78 +#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c +#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 +#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 + +/****************************************/ +/* PCI Error Report Registers */ +/****************************************/ + +#define MV64460_PCI_0_SERR_MASK 0xc28 +#define MV64460_PCI_1_SERR_MASK 0xca8 +#define MV64460_PCI_0_ERROR_ADDR_LOW 0x1d40 +#define MV64460_PCI_1_ERROR_ADDR_LOW 0x1dc0 +#define MV64460_PCI_0_ERROR_ADDR_HIGH 0x1d44 +#define MV64460_PCI_1_ERROR_ADDR_HIGH 0x1dc4 +#define MV64460_PCI_0_ERROR_ATTRIBUTE 0x1d48 +#define MV64460_PCI_1_ERROR_ATTRIBUTE 0x1dc8 +#define MV64460_PCI_0_ERROR_COMMAND 0x1d50 +#define MV64460_PCI_1_ERROR_COMMAND 0x1dd0 +#define MV64460_PCI_0_ERROR_CAUSE 0x1d58 +#define MV64460_PCI_1_ERROR_CAUSE 0x1dd8 +#define MV64460_PCI_0_ERROR_MASK 0x1d5c +#define MV64460_PCI_1_ERROR_MASK 0x1ddc + +/****************************************/ +/* PCI Debug Registers */ +/****************************************/ + +#define MV64460_PCI_0_MMASK 0X1D24 +#define MV64460_PCI_1_MMASK 0X1DA4 + +/*********************************************/ +/* PCI Configuration, Function 0, Registers */ +/*********************************************/ + +#define MV64460_PCI_DEVICE_AND_VENDOR_ID 0x000 +#define MV64460_PCI_STATUS_AND_COMMAND 0x004 +#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C + +#define MV64460_PCI_SCS_0_BASE_ADDR_LOW 0x010 +#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH 0x014 +#define MV64460_PCI_SCS_1_BASE_ADDR_LOW 0x018 +#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH 0x01C +#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 +#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 +#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c +#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define MV64460_PCI_CAPABILTY_LIST_POINTER 0x034 +#define MV64460_PCI_INTERRUPT_PIN_AND_LINE 0x03C + /* capability list */ +#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define MV64460_PCI_VPD_ADDR 0x048 +#define MV64460_PCI_VPD_DATA 0x04c +#define MV64460_PCI_MSI_MESSAGE_CONTROL 0x050 +#define MV64460_PCI_MSI_MESSAGE_ADDR 0x054 +#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 +#define MV64460_PCI_MSI_MESSAGE_DATA 0x05c +#define MV64460_PCI_X_COMMAND 0x060 +#define MV64460_PCI_X_STATUS 0x064 +#define MV64460_PCI_COMPACT_PCI_HOT_SWAP 0x068 + +/***********************************************/ +/* PCI Configuration, Function 1, Registers */ +/***********************************************/ + +#define MV64460_PCI_SCS_2_BASE_ADDR_LOW 0x110 +#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH 0x114 +#define MV64460_PCI_SCS_3_BASE_ADDR_LOW 0x118 +#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH 0x11c +#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 +#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 + +/***********************************************/ +/* PCI Configuration, Function 2, Registers */ +/***********************************************/ + +#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 +#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 +#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 +#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c +#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 +#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 3, Registers */ +/***********************************************/ + +#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 +#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 +#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 +#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c +#define MV64460_PCI_CPU_BASE_ADDR_LOW 0x220 +#define MV64460_PCI_CPU_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 4, Registers */ +/***********************************************/ + +#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 +#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 +#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 +#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c +#define MV64460_PCI_P2P_I_O_BASE_ADDR 0x420 +#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 + +/****************************************/ +/* Messaging Unit Registers (I20) */ +/****************************************/ + +#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 +#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 +#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 +#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C +#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 +#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 +#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 +#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C +#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 +#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 +#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 +#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 +#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 +#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 +#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 +#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 +#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 +#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C +#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 +#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 +#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 +#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC + +#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 +#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 +#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 +#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C +#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 +#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 +#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 +#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC +#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 +#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 +#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 +#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 +#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 +#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 +#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 +#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 +#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 +#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC +#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 +#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 +#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 +#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C + +#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 +#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 +#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 +#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C +#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 +#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 +#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 +#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C +#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 +#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 +#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 +#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 +#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 +#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 +#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 +#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 +#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 +#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C +#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 +#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 +#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 +#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC +#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 +#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 +#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 +#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C +#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 +#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 +#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 +#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC +#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 +#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 +#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 +#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 +#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 +#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 +#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 +#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 +#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 +#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC +#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 +#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 +#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 +#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ + +#define MV64460_ETH_PHY_ADDR_REG 0x2000 +#define MV64460_ETH_SMI_REG 0x2004 +#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 +#define MV64460_ETH_UNIT_DEFAULTID_REG 0x200c +#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 +#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 +#define MV64460_ETH_UNIT_INTERNAL_USE_REG 0x24fc +#define MV64460_ETH_UNIT_ERROR_ADDR_REG 0x2094 +#define MV64460_ETH_BAR_0 0x2200 +#define MV64460_ETH_BAR_1 0x2208 +#define MV64460_ETH_BAR_2 0x2210 +#define MV64460_ETH_BAR_3 0x2218 +#define MV64460_ETH_BAR_4 0x2220 +#define MV64460_ETH_BAR_5 0x2228 +#define MV64460_ETH_SIZE_REG_0 0x2204 +#define MV64460_ETH_SIZE_REG_1 0x220c +#define MV64460_ETH_SIZE_REG_2 0x2214 +#define MV64460_ETH_SIZE_REG_3 0x221c +#define MV64460_ETH_SIZE_REG_4 0x2224 +#define MV64460_ETH_SIZE_REG_5 0x222c +#define MV64460_ETH_HEADERS_RETARGET_BASE_REG 0x2230 +#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 +#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 +#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 +#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 +#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3 0x228c +#define MV64460_ETH_BASE_ADDR_ENABLE_REG 0x2290 +#define MV64460_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) +#define MV64460_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) +#define MV64460_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) +#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) +#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) +#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) +#define MV64460_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) +#define MV64460_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) +#define MV64460_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) +#define MV64460_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) +#define MV64460_ETH_DSCP_0(port) (0x2420 + (port<<10)) +#define MV64460_ETH_DSCP_1(port) (0x2424 + (port<<10)) +#define MV64460_ETH_DSCP_2(port) (0x2428 + (port<<10)) +#define MV64460_ETH_DSCP_3(port) (0x242c + (port<<10)) +#define MV64460_ETH_DSCP_4(port) (0x2430 + (port<<10)) +#define MV64460_ETH_DSCP_5(port) (0x2434 + (port<<10)) +#define MV64460_ETH_DSCP_6(port) (0x2438 + (port<<10)) +#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) +#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) +#define MV64460_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) +#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) +#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) +#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) +#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) +#define MV64460_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) +#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) +#define MV64460_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) +#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) +#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) +#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) +#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) +#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) +#define MV64460_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) +#define MV64460_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) +#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) +#define MV64460_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) +#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) +#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) +#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) +#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) +#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) +#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) +#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) +#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) +#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) +#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) +#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) +#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) +#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) +#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) +#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) +#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) +#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) +#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) +#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) +#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) +#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) +#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) +#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) +#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) + +/*******************************************/ +/* CUNIT Registers */ +/*******************************************/ + + /* Address Decoding Register Map */ + +#define MV64460_CUNIT_BASE_ADDR_REG0 0xf200 +#define MV64460_CUNIT_BASE_ADDR_REG1 0xf208 +#define MV64460_CUNIT_BASE_ADDR_REG2 0xf210 +#define MV64460_CUNIT_BASE_ADDR_REG3 0xf218 +#define MV64460_CUNIT_SIZE0 0xf204 +#define MV64460_CUNIT_SIZE1 0xf20c +#define MV64460_CUNIT_SIZE2 0xf214 +#define MV64460_CUNIT_SIZE3 0xf21c +#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 +#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 +#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 +#define MV64460_MPSC0_ACCESS_PROTECTION_REG 0xf254 +#define MV64460_MPSC1_ACCESS_PROTECTION_REG 0xf258 +#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C + + /* Error Report Registers */ + +#define MV64460_CUNIT_INTERRUPT_CAUSE_REG 0xf310 +#define MV64460_CUNIT_INTERRUPT_MASK_REG 0xf314 +#define MV64460_CUNIT_ERROR_ADDR 0xf318 + + /* Cunit Control Registers */ + +#define MV64460_CUNIT_ARBITER_CONTROL_REG 0xf300 +#define MV64460_CUNIT_CONFIG_REG 0xb40c +#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 + + /* Cunit Debug Registers */ + +#define MV64460_CUNIT_DEBUG_LOW 0xf340 +#define MV64460_CUNIT_DEBUG_HIGH 0xf344 +#define MV64460_CUNIT_MMASK 0xf380 + + /* Cunit Base Address Enable Window Bits*/ +#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 +#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 +#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 +#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 + + /* MPSCs Clocks Routing Registers */ + +#define MV64460_MPSC_ROUTING_REG 0xb400 +#define MV64460_MPSC_RX_CLOCK_ROUTING_REG 0xb404 +#define MV64460_MPSC_TX_CLOCK_ROUTING_REG 0xb408 + + /* MPSCs Interrupts Registers */ + +#define MV64460_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) +#define MV64460_MPSC_MASK_REG(port) (0xb884 + (port<<3)) + +#define MV64460_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) +#define MV64460_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) +#define MV64460_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) +#define MV64460_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) + + /* MPSC0 Registers */ + + +/***************************************/ +/* SDMA Registers */ +/***************************************/ + +#define MV64460_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) +#define MV64460_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) +#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) +#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) +#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) + +#define MV64460_SDMA_CAUSE_REG 0xb800 +#define MV64460_SDMA_MASK_REG 0xb880 + + +/****************************************/ +/* SDMA Address Space Targets */ +/****************************************/ + +#define MV64460_SDMA_DRAM_CS_0_TARGET 0x0e00 +#define MV64460_SDMA_DRAM_CS_1_TARGET 0x0d00 +#define MV64460_SDMA_DRAM_CS_2_TARGET 0x0b00 +#define MV64460_SDMA_DRAM_CS_3_TARGET 0x0700 + +#define MV64460_SDMA_DEV_CS_0_TARGET 0x1e01 +#define MV64460_SDMA_DEV_CS_1_TARGET 0x1d01 +#define MV64460_SDMA_DEV_CS_2_TARGET 0x1b01 +#define MV64460_SDMA_DEV_CS_3_TARGET 0x1701 + +#define MV64460_SDMA_BOOT_CS_TARGET 0x0f00 + +#define MV64460_SDMA_SRAM_TARGET 0x0003 +#define MV64460_SDMA_60X_BUS_TARGET 0x4003 + +#define MV64460_PCI_0_TARGET 0x0003 +#define MV64460_PCI_1_TARGET 0x0004 + + +/* Devices BAR and size registers */ + +#define MV64460_DEV_CS0_BASE_ADDR 0x028 +#define MV64460_DEV_CS0_SIZE 0x030 +#define MV64460_DEV_CS1_BASE_ADDR 0x228 +#define MV64460_DEV_CS1_SIZE 0x230 +#define MV64460_DEV_CS2_BASE_ADDR 0x248 +#define MV64460_DEV_CS2_SIZE 0x250 +#define MV64460_DEV_CS3_BASE_ADDR 0x038 +#define MV64460_DEV_CS3_SIZE 0x040 +#define MV64460_BOOTCS_BASE_ADDR 0x238 +#define MV64460_BOOTCS_SIZE 0x240 + +/* SDMA Window access protection */ +#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0 +#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1 +#define MV64460_SDMA_WIN_ACCESS_FULL 2 + +/* BRG Interrupts */ + +#define MV64460_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) +#define MV64460_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) +#define MV64460_BRG_CAUSE_REG 0xb834 +#define MV64460_BRG_MASK_REG 0xb8b4 + +/****************************************/ +/* DMA Channel Control */ +/****************************************/ + +#define MV64460_DMA_CHANNEL0_CONTROL 0x840 +#define MV64460_DMA_CHANNEL0_CONTROL_HIGH 0x880 +#define MV64460_DMA_CHANNEL1_CONTROL 0x844 +#define MV64460_DMA_CHANNEL1_CONTROL_HIGH 0x884 +#define MV64460_DMA_CHANNEL2_CONTROL 0x848 +#define MV64460_DMA_CHANNEL2_CONTROL_HIGH 0x888 +#define MV64460_DMA_CHANNEL3_CONTROL 0x84C +#define MV64460_DMA_CHANNEL3_CONTROL_HIGH 0x88C + + +/****************************************/ +/* IDMA Registers */ +/****************************************/ + +#define MV64460_DMA_CHANNEL0_BYTE_COUNT 0x800 +#define MV64460_DMA_CHANNEL1_BYTE_COUNT 0x804 +#define MV64460_DMA_CHANNEL2_BYTE_COUNT 0x808 +#define MV64460_DMA_CHANNEL3_BYTE_COUNT 0x80C +#define MV64460_DMA_CHANNEL0_SOURCE_ADDR 0x810 +#define MV64460_DMA_CHANNEL1_SOURCE_ADDR 0x814 +#define MV64460_DMA_CHANNEL2_SOURCE_ADDR 0x818 +#define MV64460_DMA_CHANNEL3_SOURCE_ADDR 0x81c +#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR 0x820 +#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR 0x824 +#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR 0x828 +#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR 0x82C +#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 +#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 +#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 +#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C +#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 +#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 +#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 +#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C + + /* IDMA Address Decoding Base Address Registers */ + +#define MV64460_DMA_BASE_ADDR_REG0 0xa00 +#define MV64460_DMA_BASE_ADDR_REG1 0xa08 +#define MV64460_DMA_BASE_ADDR_REG2 0xa10 +#define MV64460_DMA_BASE_ADDR_REG3 0xa18 +#define MV64460_DMA_BASE_ADDR_REG4 0xa20 +#define MV64460_DMA_BASE_ADDR_REG5 0xa28 +#define MV64460_DMA_BASE_ADDR_REG6 0xa30 +#define MV64460_DMA_BASE_ADDR_REG7 0xa38 + + /* IDMA Address Decoding Size Address Register */ + +#define MV64460_DMA_SIZE_REG0 0xa04 +#define MV64460_DMA_SIZE_REG1 0xa0c +#define MV64460_DMA_SIZE_REG2 0xa14 +#define MV64460_DMA_SIZE_REG3 0xa1c +#define MV64460_DMA_SIZE_REG4 0xa24 +#define MV64460_DMA_SIZE_REG5 0xa2c +#define MV64460_DMA_SIZE_REG6 0xa34 +#define MV64460_DMA_SIZE_REG7 0xa3C + + /* IDMA Address Decoding High Address Remap and Access + Protection Registers */ + +#define MV64460_DMA_HIGH_ADDR_REMAP_REG0 0xa60 +#define MV64460_DMA_HIGH_ADDR_REMAP_REG1 0xa64 +#define MV64460_DMA_HIGH_ADDR_REMAP_REG2 0xa68 +#define MV64460_DMA_HIGH_ADDR_REMAP_REG3 0xa6C +#define MV64460_DMA_BASE_ADDR_ENABLE_REG 0xa80 +#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 +#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 +#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 +#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c +#define MV64460_DMA_ARBITER_CONTROL 0x860 +#define MV64460_DMA_CROSS_BAR_TIMEOUT 0x8d0 + + /* IDMA Headers Retarget Registers */ + +#define MV64460_DMA_HEADERS_RETARGET_CONTROL 0xa84 +#define MV64460_DMA_HEADERS_RETARGET_BASE 0xa88 + + /* IDMA Interrupt Register */ + +#define MV64460_DMA_INTERRUPT_CAUSE_REG 0x8c0 +#define MV64460_DMA_INTERRUPT_CAUSE_MASK 0x8c4 +#define MV64460_DMA_ERROR_ADDR 0x8c8 +#define MV64460_DMA_ERROR_SELECT 0x8cc + + /* IDMA Debug Register ( for internal use ) */ + +#define MV64460_DMA_DEBUG_LOW 0x8e0 +#define MV64460_DMA_DEBUG_HIGH 0x8e4 +#define MV64460_DMA_SPARE 0xA8C + +/****************************************/ +/* Timer_Counter */ +/****************************************/ + +#define MV64460_TIMER_COUNTER0 0x850 +#define MV64460_TIMER_COUNTER1 0x854 +#define MV64460_TIMER_COUNTER2 0x858 +#define MV64460_TIMER_COUNTER3 0x85C +#define MV64460_TIMER_COUNTER_0_3_CONTROL 0x864 +#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 +#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c + +/****************************************/ +/* Watchdog registers */ +/****************************************/ + +#define MV64460_WATCHDOG_CONFIG_REG 0xb410 +#define MV64460_WATCHDOG_VALUE_REG 0xb414 + +/****************************************/ +/* I2C Registers */ +/****************************************/ + +#define MV64460_I2C_SLAVE_ADDR 0xc000 +#define MV64460_I2C_EXTENDED_SLAVE_ADDR 0xc010 +#define MV64460_I2C_DATA 0xc004 +#define MV64460_I2C_CONTROL 0xc008 +#define MV64460_I2C_STATUS_BAUDE_RATE 0xc00C +#define MV64460_I2C_SOFT_RESET 0xc01c + +/****************************************/ +/* GPP Interface Registers */ +/****************************************/ + +#define MV64460_GPP_IO_CONTROL 0xf100 +#define MV64460_GPP_LEVEL_CONTROL 0xf110 +#define MV64460_GPP_VALUE 0xf104 +#define MV64460_GPP_INTERRUPT_CAUSE 0xf108 +#define MV64460_GPP_INTERRUPT_MASK0 0xf10c +#define MV64460_GPP_INTERRUPT_MASK1 0xf114 +#define MV64460_GPP_VALUE_SET 0xf118 +#define MV64460_GPP_VALUE_CLEAR 0xf11c + +/****************************************/ +/* Interrupt Controller Registers */ +/****************************************/ + +/****************************************/ +/* Interrupts */ +/****************************************/ + +#define MV64460_MAIN_INTERRUPT_CAUSE_LOW 0x004 +#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH 0x00c +#define MV64460_CPU_INTERRUPT0_MASK_LOW 0x014 +#define MV64460_CPU_INTERRUPT0_MASK_HIGH 0x01c +#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE 0x024 +#define MV64460_CPU_INTERRUPT1_MASK_LOW 0x034 +#define MV64460_CPU_INTERRUPT1_MASK_HIGH 0x03c +#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE 0x044 +#define MV64460_INTERRUPT0_MASK_0_LOW 0x054 +#define MV64460_INTERRUPT0_MASK_0_HIGH 0x05c +#define MV64460_INTERRUPT0_SELECT_CAUSE 0x064 +#define MV64460_INTERRUPT1_MASK_0_LOW 0x074 +#define MV64460_INTERRUPT1_MASK_0_HIGH 0x07c +#define MV64460_INTERRUPT1_SELECT_CAUSE 0x084 + +/****************************************/ +/* MPP Interface Registers */ +/****************************************/ + +#define MV64460_MPP_CONTROL0 0xf000 +#define MV64460_MPP_CONTROL1 0xf004 +#define MV64460_MPP_CONTROL2 0xf008 +#define MV64460_MPP_CONTROL3 0xf00c + +/****************************************/ +/* Serial Initialization registers */ +/****************************************/ + +#define MV64460_SERIAL_INIT_LAST_DATA 0xf324 +#define MV64460_SERIAL_INIT_CONTROL 0xf328 +#define MV64460_SERIAL_INIT_STATUS 0xf32c + + +#endif /* __INCgt64460rh */ diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c new file mode 100644 index 0000000..5637284 --- /dev/null +++ b/board/Marvell/db64460/pci.c @@ -0,0 +1,940 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* PCI.c - PCI functions */ + + +#include +#include + +#include "../include/pci.h" + +#undef DEBUG +#undef IDE_SET_NATIVE_MODE +static unsigned int local_buses[] = { 0, 0 }; + +static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { + {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, + {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, +}; + + +#ifdef DEBUG +static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; +static void gt_pci_bus_mode_display (PCI_HOST host) +{ + unsigned int mode; + + + mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; + switch (mode) { + case 0: + printf ("PCI %d bus mode: Conventional PCI\n", host); + break; + case 1: + printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + break; + case 2: + printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + break; + case 3: + printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + break; + default: + printf ("Unknown BUS %d\n", mode); + } +} +#endif + +static const unsigned int pci_p2p_configuration_reg[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION +}; + +static const unsigned int pci_configuration_address[] = { + PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS +}; + +static const unsigned int pci_configuration_data[] = { + PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, + PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER +}; + +static const unsigned int pci_error_cause_reg[] = { + PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE +}; + +static const unsigned int pci_arbiter_control[] = { + PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL +}; + +static const unsigned int pci_address_space_en[] = { + PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE +}; + +static const unsigned int pci_snoop_control_base_0_low[] = { + PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW +}; +static const unsigned int pci_snoop_control_top_0[] = { + PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 +}; + +static const unsigned int pci_access_control_base_0_low[] = { + PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW +}; +static const unsigned int pci_access_control_top_0[] = { + PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 +}; + +static const unsigned int pci_scs_bank_size[2][4] = { + {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, + PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, + {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, + PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} +}; + +static const unsigned int pci_p2p_configuration[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION +}; + + +/******************************************************************** +* pciWriteConfigReg - Write to a PCI configuration register +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* +* +* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum, unsigned int data) +{ + volatile unsigned int DataForAddrReg; + unsigned int functionNum; + unsigned int busNum = 0; + unsigned int addr; + + if (pciDevNum > 32) /* illegal device Number */ + return; + if (pciDevNum == SELF) { /* configure our configuration space. */ + pciDevNum = + (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & + 0x1f; + busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & + 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = + (regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); + GT_REG_READ (pci_configuration_address[host], &addr); + if (addr != DataForAddrReg) + return; + GT_REG_WRITE (pci_configuration_data[host], data); +} + +/******************************************************************** +* pciReadConfigReg - Read from a PCI0 configuration register +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec) +* pciDevNum: The device number needs to be addressed. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum) +{ + volatile unsigned int DataForAddrReg; + unsigned int data; + unsigned int functionNum; + unsigned int busNum = 0; + + if (pciDevNum > 32) /* illegal device Number */ + return 0xffffffff; + if (pciDevNum == SELF) { /* configure our configuration space. */ + pciDevNum = + (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & + 0x1f; + busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & + 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = + (regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); + GT_REG_READ (pci_configuration_address[host], &data); + if (data != DataForAddrReg) + return 0xffffffff; + GT_REG_READ (pci_configuration_data[host], &data); + return data; +} + +/******************************************************************** +* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. +* +* Inputs: unsigned int regOffset - The register offset as it apears in the +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +* The configuration Address is configure as type-I (bits[1:0] = '01') due to +* PCI spec referring to P2P. +* +*********************************************************************/ +void pciOverBridgeWriteConfigReg (PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum, unsigned int data) +{ + unsigned int DataForReg; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if (pciDevNum == SELF) { /* This board */ + DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; + } else { + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | + BIT31 | BIT0; + } + GT_REG_WRITE (pci_configuration_address[host], DataForReg); + GT_REG_WRITE (pci_configuration_data[host], data); +} + + +/******************************************************************** +* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum) +{ + unsigned int DataForReg; + unsigned int data; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if (pciDevNum == SELF) { /* This board */ + DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; + } else { /* agent on another bus */ + + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | + BIT0 | BIT31; + } + GT_REG_WRITE (pci_configuration_address[host], DataForReg); + GT_REG_READ (pci_configuration_data[host], &data); + return data; +} + + +/******************************************************************** +* pciGetRegOffset - Gets the register offset for this region config. +* +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI register base address +*********************************************************************/ +static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) +{ + switch (host) { + case PCI_HOST0: + switch (region) { + case PCI_IO: + return PCI_0I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: + return PCI_0MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: + return PCI_0MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: + return PCI_0MEMORY3_LOW_DECODE_ADDRESS; + } + case PCI_HOST1: + switch (region) { + case PCI_IO: + return PCI_1I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: + return PCI_1MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: + return PCI_1MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: + return PCI_1MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: + return PCI_1MEMORY3_LOW_DECODE_ADDRESS; + } + } + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; +} + +static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) +{ + switch (host) { + case PCI_HOST0: + switch (region) { + case PCI_IO: + return PCI_0I_O_ADDRESS_REMAP; + case PCI_REGION0: + return PCI_0MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: + return PCI_0MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: + return PCI_0MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: + return PCI_0MEMORY3_ADDRESS_REMAP; + } + case PCI_HOST1: + switch (region) { + case PCI_IO: + return PCI_1I_O_ADDRESS_REMAP; + case PCI_REGION0: + return PCI_1MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: + return PCI_1MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: + return PCI_1MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: + return PCI_1MEMORY3_ADDRESS_REMAP; + } + } + return PCI_0MEMORY0_ADDRESS_REMAP; +} + +/******************************************************************** +* pciGetBaseAddress - Gets the base address of a PCI. +* - If the PCI size is 0 then this base address has no meaning!!! +* +* +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI base address. +*********************************************************************/ +unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) +{ + unsigned int regBase; + unsigned int regEnd; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, ®Base); + GT_REG_READ (regOffset + 8, ®End); + + if (regEnd <= regBase) + return 0xffffffff; /* ERROR !!! */ + + regBase = regBase << 16; + return regBase; +} + +bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, + unsigned int bankBase, unsigned int bankLength) +{ + unsigned int low = 0xfff; + unsigned int high = 0x0; + unsigned int regOffset = pciGetRegOffset (host, region); + unsigned int remapOffset = pciGetRemapOffset (host, region); + + if (bankLength != 0) { + low = (bankBase >> 16) & 0xffff; + high = ((bankBase + bankLength) >> 16) - 1; + } + + GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ + GT_REG_WRITE (regOffset + 8, high); + + if (bankLength != 0) { /* must do AFTER writing maps */ + GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. + dont support upper 32 + in this driver */ + } + return true; +} + +unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) +{ + unsigned int low; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, &low); + return (low & 0xffff) << 16; +} + +unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) +{ + unsigned int low, high; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, &low); + GT_REG_READ (regOffset + 8, &high); + return ((high & 0xffff) + 1) << 16; +} + + +/* ronen - 7/Dec/03*/ +/******************************************************************** +* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. +* Inputs: one of the PCI BAR +*********************************************************************/ +void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) +{ + RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); +} + +void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) +{ + SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); +} + +/******************************************************************** +* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. +* +* Inputs: base and size of PCI SCS +*********************************************************************/ +void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, + unsigned int pciDramBase, unsigned int pciDramSize) +{ + /*ronen different function for 3rd bank. */ + unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; + + pciDramBase = pciDramBase & 0xfffff000; + pciDramBase = pciDramBase | (pciReadConfigReg (host, + PCI_SCS_0_BASE_ADDRESS + + offset, + SELF) & 0x00000fff); + pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, + pciDramBase); + if (pciDramSize == 0) + pciDramSize++; + GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); + gtPciEnableInternalBAR (host, bank); +} + +/******************************************************************** +* pciSetRegionFeatures - This function modifys one of the 8 regions with +* feature bits given as an input. +* - Be advised to check the spec before modifying them. +* Inputs: PCI_PROTECT_REGION region - one of the eight regions. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. +* Returns: false if one of the parameters is erroneous true otherwise. +*********************************************************************/ +bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, + unsigned int features, unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int accessLow; + unsigned int accessHigh; + unsigned int accessTop = baseAddress + regionLength; + + if (regionLength == 0) { /* close the region. */ + pciDisableAccessRegion (host, region); + return true; + } + /* base Address is store is bits [11:0] */ + accessLow = (baseAddress & 0xfff00000) >> 20; + /* All the features are update according to the defines in pci.h (to be on + the safe side we disable bits: [11:0] */ + accessLow = accessLow | (features & 0xfffff000); + /* write to the Low Access Region register */ + GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, + accessLow); + + accessHigh = (accessTop & 0xfff00000) >> 20; + + /* write to the High Access Region register */ + GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, + accessHigh - 1); + return true; +} + +/******************************************************************** +* pciDisableAccessRegion - Disable The given Region by writing MAX size +* to its low Address and MIN size to its high Address. +* +* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. +* Returns: N/A. +*********************************************************************/ +void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) +{ + /* writing back the registers default values. */ + GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, + 0x01001fff); + GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); +} + +/******************************************************************** +* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true. +*********************************************************************/ +bool pciArbiterEnable (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); + return true; +} + +/******************************************************************** +* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true +*********************************************************************/ +bool pciArbiterDisable (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); + return true; +} + +/******************************************************************** +* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) +* +* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. +* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. +* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. +* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. +* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. +* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. +* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. +* Returns: true +*********************************************************************/ +bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, + PCI_AGENT_PRIO externalAgent0, + PCI_AGENT_PRIO externalAgent1, + PCI_AGENT_PRIO externalAgent2, + PCI_AGENT_PRIO externalAgent3, + PCI_AGENT_PRIO externalAgent4, + PCI_AGENT_PRIO externalAgent5) +{ + unsigned int regData; + unsigned int writeData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + writeData = (internalAgent << 7) + (externalAgent0 << 8) + + (externalAgent1 << 9) + (externalAgent2 << 10) + + (externalAgent3 << 11) + (externalAgent4 << 12) + + (externalAgent5 << 13); + regData = (regData & 0xffffc07f) | writeData; + GT_REG_WRITE (pci_arbiter_control[host], regData & regData); + return true; +} + +/******************************************************************** +* pciParkingDisable - Park on last option disable, with this function you can +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. +* +* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* Returns: true +*********************************************************************/ +bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, + PCI_AGENT_PARK externalAgent0, + PCI_AGENT_PARK externalAgent1, + PCI_AGENT_PARK externalAgent2, + PCI_AGENT_PARK externalAgent3, + PCI_AGENT_PARK externalAgent4, + PCI_AGENT_PARK externalAgent5) +{ + unsigned int regData; + unsigned int writeData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + writeData = (internalAgent << 14) + (externalAgent0 << 15) + + (externalAgent1 << 16) + (externalAgent2 << 17) + + (externalAgent3 << 18) + (externalAgent4 << 19) + + (externalAgent5 << 20); + regData = (regData & ~(0x7f << 14)) | writeData; + GT_REG_WRITE (pci_arbiter_control[host], regData); + return true; +} + +/******************************************************************** +* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to +* respond to grant assertion within a window specified in +* the input value: 'brokenValue'. +* +* Inputs: unsigned char brokenValue - A value which limits the Master to hold the +* grant without asserting frame. +* Returns: Error for illegal broken value otherwise true. +*********************************************************************/ +bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) +{ + unsigned int data; + unsigned int regData; + + if (brokenValue > 0xf) + return false; /* brokenValue must be 4 bit */ + data = brokenValue << 3; + GT_REG_READ (pci_arbiter_control[host], ®Data); + regData = (regData & 0xffffff87) | data; + GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); + return true; +} + +/******************************************************************** +* pciDisableBrokenAgentDetection - This function disable the Broken agent +* Detection mechanism. +* NOTE: This operation may cause a dead lock on the +* pci0 arbitration. +* +* Inputs: N/A +* Returns: true. +*********************************************************************/ +bool pciDisableBrokenAgentDetection (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + regData = regData & 0xfffffffd; + GT_REG_WRITE (pci_arbiter_control[host], regData); + return true; +} + +/******************************************************************** +* pciP2PConfig - This function set the PCI_n P2P configurate. +* For more information on the P2P read PCI spec. +* +* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. +* +* Returns: true. +*********************************************************************/ +bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, + unsigned int SecondBusHigh, + unsigned int busNum, unsigned int devNum) +{ + unsigned int regData; + + regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | + ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); + GT_REG_WRITE (pci_p2p_configuration[host], regData); + return true; +} + +/******************************************************************** +* pciSetRegionSnoopMode - This function modifys one of the 4 regions which +* supports Cache Coherency in the PCI_n interface. +* Inputs: region - One of the four regions. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. +* Returns: false if one of the parameters is wrong otherwise return true. +*********************************************************************/ +bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, + PCI_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int snoopXbaseAddress; + unsigned int snoopXtopAddress; + unsigned int data; + unsigned int snoopHigh = baseAddress + regionLength; + + if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) + return false; + snoopXbaseAddress = + pci_snoop_control_base_0_low[host] + 0x10 * region; + snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; + if (regionLength == 0) { /* closing the region */ + GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); + GT_REG_WRITE (snoopXtopAddress, 0); + return true; + } + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + data = (baseAddress >> 20) | snoopType << 12; + GT_REG_WRITE (snoopXbaseAddress, data); + snoopHigh = (snoopHigh & 0xfff00000) >> 20; + GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); + return true; +} + +static int gt_read_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 * value) +{ + int bus = PCI_BUS (dev); + + if ((bus == local_buses[0]) || (bus == local_buses[1])) { + *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, + PCI_DEV (dev)); + } else { + *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> + cfg_addr, offset, + PCI_DEV (dev), bus); + } + + return 0; +} + +static int gt_write_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + int bus = PCI_BUS (dev); + + if ((bus == local_buses[0]) || (bus == local_buses[1])) { + pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, + PCI_DEV (dev), value); + } else { + pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, + offset, PCI_DEV (dev), bus, + value); + } + return 0; +} + + +static void gt_setup_ide (struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; + u32 bar_response, bar_value; + int bar; + + for (bar = 0; bar < 6; bar++) { + /*ronen different function for 3rd bank. */ + unsigned int offset = + (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; + + pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, + 0x0); + pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, + &bar_response); + + pciauto_region_allocate (bar_response & + PCI_BASE_ADDRESS_SPACE_IO ? hose-> + pci_io : hose->pci_mem, ide_bar[bar], + &bar_value); + + pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, + bar_value); + } +} + + +/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ +/* and is curently not called *. */ +#if 0 +static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char pin, irq; + + pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); + + if (pin == 1) { /* only allow INT A */ + irq = pci_irq_swizzle[(PCI_HOST) hose-> + cfg_addr][PCI_DEV (dev)]; + if (irq) + pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); + } +} +#endif + +struct pci_config_table gt_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, + + {} +}; + +struct pci_controller pci0_hose = { +/* fixup_irq: gt_fixup_irq, */ + config_table:gt_config_table, +}; + +struct pci_controller pci1_hose = { +/* fixup_irq: gt_fixup_irq, */ + config_table:gt_config_table, +}; + +void pci_init_board (void) +{ + unsigned int command; + +#ifdef DEBUG + gt_pci_bus_mode_display (PCI_HOST0); +#endif + + pci0_hose.first_busno = 0; + pci0_hose.last_busno = 0xff; + local_buses[0] = pci0_hose.first_busno; + + /* PCI memory space */ + pci_set_region (pci0_hose.regions + 0, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (pci0_hose.regions + 1, + CFG_PCI0_IO_SPACE_PCI, + CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + + pci_set_ops (&pci0_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + pci0_hose.region_count = 2; + + pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; + + pci_register_hose (&pci0_hose); + pciArbiterEnable (PCI_HOST0); + pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + + pci0_hose.last_busno = pci_hose_scan (&pci0_hose); + +#ifdef DEBUG + gt_pci_bus_mode_display (PCI_HOST1); +#endif + pci1_hose.first_busno = pci0_hose.last_busno + 1; + pci1_hose.last_busno = 0xff; + pci1_hose.current_busno = pci1_hose.first_busno; + local_buses[1] = pci1_hose.first_busno; + + /* PCI memory space */ + pci_set_region (pci1_hose.regions + 0, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (pci1_hose.regions + 1, + CFG_PCI1_IO_SPACE_PCI, + CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + + pci_set_ops (&pci1_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + + pci1_hose.region_count = 2; + + pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; + + pci_register_hose (&pci1_hose); + + pciArbiterEnable (PCI_HOST1); + pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); + + command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); + + pci1_hose.last_busno = pci_hose_scan (&pci1_hose); + + command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); + +} diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c new file mode 100644 index 0000000..8cfe84c --- /dev/null +++ b/board/Marvell/db64460/sdram_init.c @@ -0,0 +1,1985 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * adaption for the Marvell DB64460 Board + * Ingo Assmus (ingo.assmus@keymile.com) + ************************************************************************/ + + +/* sdram_init.c - automatic memory sizing */ + +#include +#include <74xx_7xx.h> +#include "../include/memory.h" +#include "../include/pci.h" +#include "../include/mv_gen_reg.h" +#include + +#include "eth.h" +#include "mpsc.h" +#include "../common/i2c.h" +#include "64460.h" +#include "mv_regs.h" + +#undef DEBUG +#define MAP_PCI + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +int set_dfcdlInit (void); /* setup delay line of Mv64460 */ +int mvDmaIsChannelActive (int); +int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); +int mvDmaTransfer (int, ulong, ulong, ulong, ulong); + +/* ------------------------------------------------------------------------- */ + +int +memory_map_bank (unsigned int bankNo, + unsigned int bankBase, unsigned int bankLength) +{ +#ifdef MAP_PCI + PCI_HOST host; +#endif + + +#ifdef DEBUG + if (bankLength > 0) { + printf ("mapping bank %d at %08x - %08x\n", + bankNo, bankBase, bankBase + bankLength - 1); + } else { + printf ("unmapping bank %d\n", bankNo); + } +#endif + + memoryMapBank (bankNo, bankBase, bankLength); + +#ifdef MAP_PCI + for (host = PCI_HOST0; host <= PCI_HOST1; host++) { + const int features = + PREFETCH_ENABLE | + DELAYED_READ_ENABLE | + AGGRESSIVE_PREFETCH | + READ_LINE_AGGRESSIVE_PREFETCH | + READ_MULTI_AGGRESSIVE_PREFETCH | + MAX_BURST_4 | PCI_NO_SWAP; + + pciMapMemoryBank (host, bankNo, bankBase, bankLength); + + pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, + bankLength); + + pciSetRegionFeatures (host, bankNo, features, bankBase, + bankLength); + } +#endif + return 0; +} + +#define GB (1 << 30) + +/* much of this code is based on (or is) the code in the pip405 port */ +/* thanks go to the authors of said port - Josh */ + +/* structure to store the relevant information about an sdram bank */ +typedef struct sdram_info { + uchar drb_size; + uchar registered, ecc; + uchar tpar; + uchar tras_clocks; + uchar burst_len; + uchar banks, slot; +} sdram_info_t; + +/* Typedefs for 'gtAuxilGetDIMMinfo' function */ + +typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE; + +typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, + SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, +} VOLTAGE_INTERFACE; + +typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 = + 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 = + 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR; +typedef enum _max_CL_supported_SD { SD_CL_1 = + 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, + SD_FAULT } MAX_CL_SUPPORTED_SD; + + +/* SDRAM/DDR information struct */ +typedef struct _gtMemoryDimmInfo { + MEMORY_TYPE memoryType; + unsigned int numOfRowAddresses; + unsigned int numOfColAddresses; + unsigned int numOfModuleBanks; + unsigned int dataWidth; + VOLTAGE_INTERFACE voltageInterface; + unsigned int errorCheckType; /* ECC , PARITY.. */ + unsigned int sdramWidth; /* 4,8,16 or 32 */ ; + unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ + unsigned int minClkDelay; + unsigned int burstLengthSupported; + unsigned int numOfBanksOnEachDevice; + unsigned int suportedCasLatencies; + unsigned int RefreshInterval; + unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ + unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ + MAX_CL_SUPPORTED_DDR maxClSupported_DDR; + MAX_CL_SUPPORTED_SD maxClSupported_SD; + unsigned int moduleBankDensity; + /* module attributes (true for yes) */ + bool bufferedAddrAndControlInputs; + bool registeredAddrAndControlInputs; + bool onCardPLL; + bool bufferedDQMBinputs; + bool registeredDQMBinputs; + bool differentialClockInput; + bool redundantRowAddressing; + + /* module general attributes */ + bool suportedAutoPreCharge; + bool suportedPreChargeAll; + bool suportedEarlyRasPreCharge; + bool suportedWrite1ReadBurst; + bool suported5PercentLowVCC; + bool suported5PercentUpperVCC; + /* module timing parameters */ + unsigned int minRasToCasDelay; + unsigned int minRowActiveRowActiveDelay; + unsigned int minRasPulseWidth; + unsigned int minRowPrechargeTime; /* measured in ns */ + + int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ + int addrAndCommandSetupTime; /* (measured in ns/100) */ + int dataInputSetupTime; /* LoP left of point (measured in ns) */ + int dataInputHoldTime; /* LoP left of point (measured in ns) */ +/* tAC times for highest 2nd and 3rd highest CAS Latency values */ + unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ + unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ + unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ + + unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ + + unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ + + unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ + + /* Parameters calculated from + the extracted DIMM information */ + unsigned int size; + unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ + unsigned int numberOfDevices; + uchar drb_size; /* DRAM size in n*64Mbit */ + uchar slot; /* Slot Number this module is inserted in */ + uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ +#ifdef DEBUG + uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ + uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ + uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ + unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ + unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ + unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ + uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ + +#endif +} AUX_MEM_DIMM_INFO; + + +/* + * translate ns.ns/10 coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short NS10to10PS (unsigned char spd_byte) +{ + unsigned short ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + return (ns * 100 + ns10 * 10); +} + +/* + * translate ns coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short NSto10PS (unsigned char spd_byte) +{ + return (spd_byte * 100); +} + +/* This code reads the SPD chip on the sdram and populates + * the array which is passed in with the relevant information */ +/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ +static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long spd_checksum; + +#ifdef ZUMA_NTL + /* zero all the values */ + memset (info, 0, sizeof (*info)); + +/* + if (!slot) { + info->slot = 0; + info->banks = 1; + info->registered = 0; + info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */ +/* info->tpar = 3; + info->tras_clocks = 5; + info->burst_len = 4; +*/ +#ifdef CONFIG_MV64460_ECC + /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ + dimmInfo->errorCheckType = 2; +/* info->ecc = 2;*/ +#endif +} + +return 0; + +#else + uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; + int ret; + unsigned int i, j, density = 1, devicesForErrCheck = 0; + +#ifdef DEBUG + unsigned int k; +#endif + unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; + int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; + uchar supp_cal, cal_val; + ulong memclk, tmemclk; + ulong tmp; + uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar data[128]; + + memclk = gd->bus_clk; + tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ + + DP (puts ("before i2c read\n")); + + ret = i2c_read (addr, 0, 1, data, 128); + + DP (puts ("after i2c read\n")); + + /* zero all the values */ + memset (dimmInfo, 0, sizeof (*dimmInfo)); + + /* copy the SPD content 1:1 into the dimmInfo structure */ + for (i = 0; i <= 127; i++) { + dimmInfo->spd_raw_data[i] = data[i]; + } + + if (ret) { + DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + return 0; + } else + dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ + +#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT + + for (i = 0; i <= 127; i++) { + printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], + data[i]); + } + +#endif +#ifdef DEBUG +/* find Manufactura of Dimm Module */ + for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { + dimmInfo->manufactura[i] = data[64 + i]; + } + printf ("\nThis RAM-Module is produced by: %s\n", + dimmInfo->manufactura); + +/* find Manul-ID of Dimm Module */ + for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { + dimmInfo->modul_id[i] = data[73 + i]; + } + printf ("The Module-ID of this RAM-Module is: %s\n", + dimmInfo->modul_id); + +/* find Vendor-Data of Dimm Module */ + for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { + dimmInfo->vendor_data[i] = data[99 + i]; + } + printf ("Vendor Data of this RAM-Module is: %s\n", + dimmInfo->vendor_data); + +/* find modul_serial_no of Dimm Module */ + dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); + printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", + dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); + +/* find Manufac-Data of Dimm Module */ + dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); + printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ + +/* find modul_revision of Dimm Module */ + dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); + printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ + +/* find manufac_place of Dimm Module */ + dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); + printf ("manufac_place of this RAM-Module is: %d\n", + dimmInfo->manufac_place); + +#endif + +/*------------------------------------------------------------------------------------------------------------------------------*/ +/* calculate SPD checksum */ +/*------------------------------------------------------------------------------------------------------------------------------*/ + spd_checksum = 0; + + for (i = 0; i <= 62; i++) { + spd_checksum += data[i]; + } + + if ((spd_checksum & 0xff) != data[63]) { + printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); + hang (); + } + + else + printf ("SPD Checksum ok!\n"); + + +/*------------------------------------------------------------------------------------------------------------------------------*/ + for (i = 2; i <= 35; i++) { + switch (i) { + case 2: /* Memory type (DDR / SDRAM) */ + dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; +#ifdef DEBUG + if (dimmInfo->memoryType == 0) + DP (printf + ("Dram_type in slot %d is: SDRAM\n", + dimmInfo->slot)); + if (dimmInfo->memoryType == 1) + DP (printf + ("Dram_type in slot %d is: DDRAM\n", + dimmInfo->slot)); +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 3: /* Number Of Row Addresses */ + dimmInfo->numOfRowAddresses = data[i]; + DP (printf + ("Module Number of row addresses: %d\n", + dimmInfo->numOfRowAddresses)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 4: /* Number Of Column Addresses */ + dimmInfo->numOfColAddresses = data[i]; + DP (printf + ("Module Number of col addresses: %d\n", + dimmInfo->numOfColAddresses)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 5: /* Number Of Module Banks */ + dimmInfo->numOfModuleBanks = data[i]; + DP (printf + ("Number of Banks on Mod. : %d\n", + dimmInfo->numOfModuleBanks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 6: /* Data Width */ + dimmInfo->dataWidth = data[i]; + DP (printf + ("Module Data Width: %d\n", + dimmInfo->dataWidth)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 8: /* Voltage Interface */ + switch (data[i]) { + case 0x0: + dimmInfo->voltageInterface = TTL_5V_TOLERANT; + DP (printf + ("Module is TTL_5V_TOLERANT\n")); + break; + case 0x1: + dimmInfo->voltageInterface = LVTTL; + DP (printf + ("Module is LVTTL\n")); + break; + case 0x2: + dimmInfo->voltageInterface = HSTL_1_5V; + DP (printf + ("Module is TTL_5V_TOLERANT\n")); + break; + case 0x3: + dimmInfo->voltageInterface = SSTL_3_3V; + DP (printf + ("Module is HSTL_1_5V\n")); + break; + case 0x4: + dimmInfo->voltageInterface = SSTL_2_5V; + DP (printf + ("Module is SSTL_2_5V\n")); + break; + default: + dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; + DP (printf + ("Module is VOLTAGE_UNKNOWN\n")); + break; + } + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 9: /* Minimum Cycle Time At Max CasLatancy */ + shift = (dimmInfo->memoryType == DDR) ? 4 : 2; + mult = (dimmInfo->memoryType == DDR) ? 10 : 25; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf : 0x03; + leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; + rightOfPoint = (data[i] & maskRightOfPoint) * mult; + dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = + leftOfPoint; + dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = + rightOfPoint; + DP (printf + ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", + leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 10: /* Clock To Data Out */ + div = (dimmInfo->memoryType == DDR) ? 100 : 10; + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + dimmInfo->clockToDataOut_LoP = leftOfPoint; + dimmInfo->clockToDataOut_RoP = rightOfPoint; + DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + +/*#ifdef CONFIG_ECC */ + case 11: /* Error Check Type */ + dimmInfo->errorCheckType = data[i]; + DP (printf + ("Error Check Type (0=NONE): %d\n", + dimmInfo->errorCheckType)); + break; +/* #endif */ +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 12: /* Refresh Interval */ + dimmInfo->RefreshInterval = data[i]; + DP (printf + ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", + dimmInfo->RefreshInterval)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 13: /* Sdram Width */ + dimmInfo->sdramWidth = data[i]; + DP (printf + ("Sdram Width: %d\n", + dimmInfo->sdramWidth)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 14: /* Error Check Data Width */ + dimmInfo->errorCheckDataWidth = data[i]; + DP (printf + ("Error Check Data Width: %d\n", + dimmInfo->errorCheckDataWidth)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 15: /* Minimum Clock Delay */ + dimmInfo->minClkDelay = data[i]; + DP (printf + ("Minimum Clock Delay: %d\n", + dimmInfo->minClkDelay)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 16: /* Burst Length Supported */ + /******-******-******-******* + * bit3 | bit2 | bit1 | bit0 * + *******-******-******-******* + burst length = * 8 | 4 | 2 | 1 * + ***************************** + + If for example bit0 and bit2 are set, the burst + length supported are 1 and 4. */ + + dimmInfo->burstLengthSupported = data[i]; +#ifdef DEBUG + DP (printf + ("Burst Length Supported: ")); + if (dimmInfo->burstLengthSupported & 0x01) + DP (printf ("1, ")); + if (dimmInfo->burstLengthSupported & 0x02) + DP (printf ("2, ")); + if (dimmInfo->burstLengthSupported & 0x04) + DP (printf ("4, ")); + if (dimmInfo->burstLengthSupported & 0x08) + DP (printf ("8, ")); + DP (printf (" Bit \n")); +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 17: /* Number Of Banks On Each Device */ + dimmInfo->numOfBanksOnEachDevice = data[i]; + DP (printf + ("Number Of Banks On Each Chip: %d\n", + dimmInfo->numOfBanksOnEachDevice)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 18: /* Suported Cas Latencies */ + + /* DDR: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + ********************************************************* + SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + dimmInfo->suportedCasLatencies = data[i]; +#ifdef DEBUG + DP (printf + ("Suported Cas Latencies: (CL) ")); + if (dimmInfo->memoryType == 0) { /* SDRAM */ + for (k = 0; k <= 7; k++) { + if (dimmInfo-> + suportedCasLatencies & (1 << k)) + DP (printf + ("%d, ", + k + 1)); + } + + } else { /* DDR-RAM */ + + if (dimmInfo->suportedCasLatencies & 1) + DP (printf ("1, ")); + if (dimmInfo->suportedCasLatencies & 2) + DP (printf ("1.5, ")); + if (dimmInfo->suportedCasLatencies & 4) + DP (printf ("2, ")); + if (dimmInfo->suportedCasLatencies & 8) + DP (printf ("2.5, ")); + if (dimmInfo->suportedCasLatencies & 16) + DP (printf ("3, ")); + if (dimmInfo->suportedCasLatencies & 32) + DP (printf ("3.5, ")); + + } + DP (printf ("\n")); +#endif + /* Calculating MAX CAS latency */ + for (j = 7; j > 0; j--) { + if (((dimmInfo-> + suportedCasLatencies >> j) & 0x1) == + 1) { + switch (dimmInfo->memoryType) { + case DDR: + /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ + switch (j) { + case 7: + DP (printf + ("Max. Cas Latencies (DDR): ERROR !!!\n")); + dimmInfo-> + maxClSupported_DDR + = + DDR_CL_FAULT; + hang (); + break; + case 6: + DP (printf + ("Max. Cas Latencies (DDR): ERROR !!!\n")); + dimmInfo-> + maxClSupported_DDR + = + DDR_CL_FAULT; + hang (); + break; + case 5: + DP (printf + ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_3_5; + break; + case 4: + DP (printf + ("Max. Cas Latencies (DDR): 3 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_3; + break; + case 3: + DP (printf + ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_2_5; + break; + case 2: + DP (printf + ("Max. Cas Latencies (DDR): 2 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_2; + break; + case 1: + DP (printf + ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_1_5; + break; + } + + /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy + lower then our SDRAM cycle count, we won't be able to support this CAL + and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */ + if ((dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_LoP + < + CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + || + ((dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_LoP + == + CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + && (dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_RoP + < + CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + { + dimmInfo-> + maxClSupported_DDR + = + dimmInfo-> + maxClSupported_DDR + >> 1; + DP (printf + ("*** Change actual Cas Latencies cause of minimumCycleTime n")); + } + /* ronen - checkif the Dimm frequency compared to the Sysclock. */ + if ((dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_LoP + > + CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + || + ((dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_LoP + == + CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + && (dimmInfo-> + minimumCycleTimeAtMaxCasLatancy_RoP + > + CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + { + printf ("*********************************************************\n"); + printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); + printf ("*********************************************************\n"); + hang (); + } + + dimmInfo-> + maxCASlatencySupported_LoP + = + 1 + + (int) (5 * j / 10); + if (((5 * j) % 10) != 0) + dimmInfo-> + maxCASlatencySupported_RoP + = 5; + else + dimmInfo-> + maxCASlatencySupported_RoP + = 0; + DP (printf + ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + dimmInfo-> + maxCASlatencySupported_LoP, + dimmInfo-> + maxCASlatencySupported_RoP)); + break; + case SDRAM: + /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ + dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ + DP (printf + ("Max. Cas Latencies (SD): %d\n", + dimmInfo-> + maxClSupported_SD)); + dimmInfo-> + maxCASlatencySupported_LoP + = j; + dimmInfo-> + maxCASlatencySupported_RoP + = 0; + DP (printf + ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + dimmInfo-> + maxCASlatencySupported_LoP, + dimmInfo-> + maxCASlatencySupported_RoP)); + break; + } + break; + } + } + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 21: /* Buffered Address And Control Inputs */ + DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + dimmInfo->bufferedAddrAndControlInputs = + data[i] & BIT0; + dimmInfo->registeredAddrAndControlInputs = + (data[i] & BIT1) >> 1; + dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; + dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; + dimmInfo->registeredDQMBinputs = + (data[i] & BIT4) >> 4; + dimmInfo->differentialClockInput = + (data[i] & BIT5) >> 5; + dimmInfo->redundantRowAddressing = + (data[i] & BIT6) >> 6; +#ifdef DEBUG + if (dimmInfo->bufferedAddrAndControlInputs == 1) + DP (printf + (" - Buffered Address/Control Input: Yes \n")); + else + DP (printf + (" - Buffered Address/Control Input: No \n")); + + if (dimmInfo->registeredAddrAndControlInputs == 1) + DP (printf + (" - Registered Address/Control Input: Yes \n")); + else + DP (printf + (" - Registered Address/Control Input: No \n")); + + if (dimmInfo->onCardPLL == 1) + DP (printf + (" - On-Card PLL (clock): Yes \n")); + else + DP (printf + (" - On-Card PLL (clock): No \n")); + + if (dimmInfo->bufferedDQMBinputs == 1) + DP (printf + (" - Bufferd DQMB Inputs: Yes \n")); + else + DP (printf + (" - Bufferd DQMB Inputs: No \n")); + + if (dimmInfo->registeredDQMBinputs == 1) + DP (printf + (" - Registered DQMB Inputs: Yes \n")); + else + DP (printf + (" - Registered DQMB Inputs: No \n")); + + if (dimmInfo->differentialClockInput == 1) + DP (printf + (" - Differential Clock Input: Yes \n")); + else + DP (printf + (" - Differential Clock Input: No \n")); + + if (dimmInfo->redundantRowAddressing == 1) + DP (printf + (" - redundant Row Addressing: Yes \n")); + else + DP (printf + (" - redundant Row Addressing: No \n")); + +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 22: /* Suported AutoPreCharge */ + DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; + dimmInfo->suportedAutoPreCharge = + (data[i] & BIT1) >> 1; + dimmInfo->suportedPreChargeAll = + (data[i] & BIT2) >> 2; + dimmInfo->suportedWrite1ReadBurst = + (data[i] & BIT3) >> 3; + dimmInfo->suported5PercentLowVCC = + (data[i] & BIT4) >> 4; + dimmInfo->suported5PercentUpperVCC = + (data[i] & BIT5) >> 5; +#ifdef DEBUG + if (dimmInfo->suportedEarlyRasPreCharge == 1) + DP (printf + (" - Early Ras Precharge: Yes \n")); + else + DP (printf + (" - Early Ras Precharge: No \n")); + + if (dimmInfo->suportedAutoPreCharge == 1) + DP (printf + (" - AutoPreCharge: Yes \n")); + else + DP (printf + (" - AutoPreCharge: No \n")); + + if (dimmInfo->suportedPreChargeAll == 1) + DP (printf + (" - Precharge All: Yes \n")); + else + DP (printf + (" - Precharge All: No \n")); + + if (dimmInfo->suportedWrite1ReadBurst == 1) + DP (printf + (" - Write 1/ReadBurst: Yes \n")); + else + DP (printf + (" - Write 1/ReadBurst: No \n")); + + if (dimmInfo->suported5PercentLowVCC == 1) + DP (printf + (" - lower VCC tolerance: 5 Percent \n")); + else + DP (printf + (" - lower VCC tolerance: 10 Percent \n")); + + if (dimmInfo->suported5PercentUpperVCC == 1) + DP (printf + (" - upper VCC tolerance: 5 Percent \n")); + else + DP (printf + (" - upper VCC tolerance: 10 Percent \n")); + +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ + shift = (dimmInfo->memoryType == DDR) ? 4 : 2; + mult = (dimmInfo->memoryType == DDR) ? 10 : 25; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf : 0x03; + leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; + rightOfPoint = (data[i] & maskRightOfPoint) * mult; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = + leftOfPoint; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = + rightOfPoint; + DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ + div = (dimmInfo->memoryType == DDR) ? 100 : 10; + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; + dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; + DP (printf + ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ + shift = (dimmInfo->memoryType == DDR) ? 4 : 2; + mult = (dimmInfo->memoryType == DDR) ? 10 : 25; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf : 0x03; + leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; + rightOfPoint = (data[i] & maskRightOfPoint) * mult; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = + leftOfPoint; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = + rightOfPoint; + DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ + div = (dimmInfo->memoryType == DDR) ? 100 : 10; + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; + dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; + DP (printf + ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 27: /* Minimum Row Precharge Time */ + shift = (dimmInfo->memoryType == DDR) ? 2 : 0; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; + leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (data[i] & maskRightOfPoint) * 25; + + dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ + trp_clocks = + (dimmInfo->minRowPrechargeTime + + (tmemclk - 1)) / tmemclk; + DP (printf + ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", + tmemclk, tmemclk / 100, tmemclk % 100)); + DP (printf + ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 28: /* Minimum Row Active to Row Active Time */ + shift = (dimmInfo->memoryType == DDR) ? 2 : 0; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; + leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (data[i] & maskRightOfPoint) * 25; + + dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ + trrd_clocks = + (dimmInfo->minRowActiveRowActiveDelay + + (tmemclk - 1)) / tmemclk; + DP (printf + ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 29: /* Minimum Ras-To-Cas Delay */ + shift = (dimmInfo->memoryType == DDR) ? 2 : 0; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; + leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (data[i] & maskRightOfPoint) * 25; + + dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ + trcd_clocks = + (dimmInfo->minRowActiveRowActiveDelay + + (tmemclk - 1)) / tmemclk; + DP (printf + ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 30: /* Minimum Ras Pulse Width */ + dimmInfo->minRasPulseWidth = data[i]; + tras_clocks = + (NSto10PS (data[i]) + + (tmemclk - 1)) / tmemclk; + DP (printf + ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", + dimmInfo->minRasPulseWidth, tras_clocks)); + + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 31: /* Module Bank Density */ + dimmInfo->moduleBankDensity = data[i]; + DP (printf + ("Module Bank Density: %d\n", + dimmInfo->moduleBankDensity)); +#ifdef DEBUG + DP (printf + ("*** Offered Densities (more than 1 = Multisize-Module): ")); + { + if (dimmInfo->moduleBankDensity & 1) + DP (printf ("4MB, ")); + if (dimmInfo->moduleBankDensity & 2) + DP (printf ("8MB, ")); + if (dimmInfo->moduleBankDensity & 4) + DP (printf ("16MB, ")); + if (dimmInfo->moduleBankDensity & 8) + DP (printf ("32MB, ")); + if (dimmInfo->moduleBankDensity & 16) + DP (printf ("64MB, ")); + if (dimmInfo->moduleBankDensity & 32) + DP (printf ("128MB, ")); + if ((dimmInfo->moduleBankDensity & 64) + || (dimmInfo->moduleBankDensity & 128)) { + DP (printf ("ERROR, ")); + hang (); + } + } + DP (printf ("\n")); +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 32: /* Address And Command Setup Time (measured in ns/1000) */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->addrAndCommandSetupTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Address And Command Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 33: /* Address And Command Hold Time */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->addrAndCommandHoldTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Address And Command Hold Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 34: /* Data Input Setup Time */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->dataInputSetupTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Data Input Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 35: /* Data Input Hold Time */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->dataInputHoldTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Data Input Hold Time [ns]: %d.%d\n\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + } + } + /* calculating the sdram density */ + for (i = 0; + i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; + i++) { + density = density * 2; + } + dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * + dimmInfo->sdramWidth; + dimmInfo->numberOfDevices = + (dimmInfo->dataWidth / dimmInfo->sdramWidth) * + dimmInfo->numOfModuleBanks; + devicesForErrCheck = + (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; + if ((dimmInfo->errorCheckType == 0x1) + || (dimmInfo->errorCheckType == 0x2) + || (dimmInfo->errorCheckType == 0x3)) { + dimmInfo->size = + (dimmInfo->deviceDensity / 8) * + (dimmInfo->numberOfDevices - + /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */ + dimmInfo->numberOfDevices / 8); + } else { + dimmInfo->size = + (dimmInfo->deviceDensity / 8) * + dimmInfo->numberOfDevices; + } + + /* compute the module DRB size */ + tmp = (1 << + (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); + tmp *= dimmInfo->numOfModuleBanks; + tmp *= dimmInfo->sdramWidth; + tmp = tmp >> 24; /* div by 0x4000000 (64M) */ + dimmInfo->drb_size = (uchar) tmp; + DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + + /* try a CAS latency of 3 first... */ + + /* bit 1 is CL2, bit 2 is CL3 */ + supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1; + + cal_val = 0; + if (supp_cal & 3) { + if (NS10to10PS (data[9]) <= tmemclk) + cal_val = 3; + } + + /* then 2... */ + if (supp_cal & 2) { + if (NS10to10PS (data[23]) <= tmemclk) + cal_val = 2; + } + + DP (printf ("cal_val = %d\n", cal_val)); + + /* bummer, did't work... */ + if (cal_val == 0) { + DP (printf ("Couldn't find a good CAS latency\n")); + hang (); + return 0; + } + + return true; +#endif +} + +/* sets up the GT properly with information passed in */ +int setup_sdram (AUX_MEM_DIMM_INFO * info) +{ + ulong tmp, check; + ulong tmp_sdram_mode = 0; /* 0x141c */ + ulong tmp_dunit_control_low = 0; /* 0x1404 */ + int i; + + /* added 8/21/2003 P. Marchese */ + unsigned int sdram_config_reg; + + /* added 10/10/2003 P. Marchese */ + ulong sdram_chip_size; + + /* sanity checking */ + if (!info->numOfModuleBanks) { + printf ("setup_sdram called with 0 banks\n"); + return 1; + } + + /* delay line */ + set_dfcdlInit (); /* may be its not needed */ + DP (printf ("Delay line set done\n")); + + /* set SDRAM mode NOP */ /* To_do check it */ + GT_REG_WRITE (SDRAM_OPERATION, 0x5); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + } + + /* SDRAM configuration */ +/* added 8/21/2003 P. Marchese */ +/* code allows usage of registered DIMMS */ + + /* figure out the memory refresh internal */ + switch (info->RefreshInterval) { + case 0x0: + case 0x80: /* refresh period is 15.625 usec */ + sdram_config_reg = + (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ) + / (float) 1000000.0); + break; + case 0x1: + case 0x81: /* refresh period is 3.9 usec */ + sdram_config_reg = + (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + case 0x2: + case 0x82: /* refresh period is 7.8 usec */ + sdram_config_reg = + (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + case 0x3: + case 0x83: /* refresh period is 31.3 usec */ + sdram_config_reg = + (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + case 0x4: + case 0x84: /* refresh period is 62.5 usec */ + sdram_config_reg = + (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + case 0x5: + case 0x85: /* refresh period is 125 usec */ + sdram_config_reg = + (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) / + (float) 1000000.0); + break; + default: /* refresh period undefined */ + printf ("DRAM refresh period is unknown!\n"); + printf ("Aborting DRAM setup with an error\n"); + hang (); + break; + } + DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); + + /* make sure the refresh value is only 14 bits */ + if (sdram_config_reg > 0x1fff) + sdram_config_reg = 0x1fff; + DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); + + /* we want physical bank interleaving and */ + /* virtual bank interleaving enabled so do nothing */ + /* since these bits need to be zero to enable the interleaving */ + + /* registered DRAM ? */ + if (info->registeredAddrAndControlInputs == 1) { + /* it's registered DRAM, so set the reg. DRAM bit */ + sdram_config_reg = sdram_config_reg | BIT17; + DP (printf ("Enabling registered DRAM bit\n")); + } + /* turn on DRAM ECC? */ +#ifdef CONFIG_MV64460_ECC + if (info->errorCheckType == 0x2) { + /* DRAM has ECC, so turn it on */ + sdram_config_reg = sdram_config_reg | BIT18; + DP (printf ("Enabling ECC\n")); + } +#endif + /* set the data DQS pin configuration */ + switch (info->sdramWidth) { + case 0x4: /* memory is x4 */ + sdram_config_reg = sdram_config_reg | BIT20 | BIT21; + DP (printf ("Data DQS pins set for 16 pins\n")); + break; + case 0x8: /* memory is x8 or x16 */ + case 0x10: + sdram_config_reg = sdram_config_reg | BIT21; + DP (printf ("Data DQS pins set for 8 pins\n")); + break; + case 0x20: /* memory is x32 */ + /* both bits are cleared for x32 so nothing to do */ + DP (printf ("Data DQS pins set for 2 pins\n")); + break; + default: /* memory width unsupported */ + printf ("DRAM chip width is unknown!\n"); + printf ("Aborting DRAM setup with an error\n"); + hang (); + break; + } + + /*ronen db64460 */ + /* perform read buffer assignments */ + /* we are going to use the Power-up defaults */ + /* bit 27 = PCI bus #0 = buffer 0 */ + /* bit 28 = PCI bus #1 = buffer 0 */ + /* bit 29 = MPSC = buffer 0 */ + /* bit 30 = IDMA = buffer 0 */ + /* bit 31 = Gigabit = buffer 0 */ + sdram_config_reg = sdram_config_reg | 0x58000000; + sdram_config_reg = sdram_config_reg & 0xffffff00; + /* bit 14 FBSplit = FCRAM controller bsplit enable. */ + /* bit 15 vw = FCRAM Variable write length enable. */ + /* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */ + sdram_config_reg = sdram_config_reg | BIT14 | BIT15; + + /* write the value into the SDRAM configuration register */ + GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); + DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); + + /* SDRAM open pages control keep open as much as I can */ + GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); + DP (printf + ("sdram_open_pages_controll 0x1414: %08x\n", + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + + /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ + tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ + if (tmp == 0) + DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + else + DP (printf + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + + /* SDRAM set CAS Latency according to SPD information */ + switch (info->memoryType) { + case SDRAM: + printf ("### SD-RAM not supported !!!\n"); + printf ("Aborting!!!\n"); + hang (); + /* ToDo fill SD-RAM if needed !!!!! */ + break; + /* Calculate the settings for SDRAM mode and Dunit control low registers */ + /* Values set according to technical bulletin TB-92 rev. c */ + case DDR: + DP (printf ("### SET-CL for DDR-RAM\n")); + /* ronen db64460 - change the tmp_dunit_control_low setting!!! */ + switch (info->maxClSupported_DDR) { + case DDR_CL_3: + tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ + if (tmp == 1) { /* clocks sync */ + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0x05110051; + else + tmp_dunit_control_low = 0x24110051; + DP (printf + ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); + } else { /* clk sync. bypassed */ + + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0xC5000540; + else + tmp_dunit_control_low = 0xC4000540; + DP (printf + ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + case DDR_CL_2_5: + tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */ + if (tmp == 1) { /* clocks sync */ + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0x25110051; + else + tmp_dunit_control_low = 0x24110051; + DP (printf + ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); + } else { /* clk sync. bypassed */ + + if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0xC5000540; + /* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ + /* printf("Aborting!!!\n");1 */ + /* hang();1 */ + } else + tmp_dunit_control_low = 0xC4000540; + DP (printf + ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + case DDR_CL_2: + tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ + if (tmp == 1) { /* clocks sync */ + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0x04110051; + else + tmp_dunit_control_low = 0x03110051; + DP (printf + ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); + } else { /* clk sync. bypassed */ + + if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ + /*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ + /*printf("Aborting!!!\n");1 */ + /*hang();1 */ + tmp_dunit_control_low = 0xC4000540; + } else + tmp_dunit_control_low = 0xC3000540;; + DP (printf + ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + case DDR_CL_1_5: + tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */ + if (tmp == 1) { /* clocks sync */ + if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ + tmp_dunit_control_low = 0x24110051; + else + tmp_dunit_control_low = 0x23110051; + DP (printf + ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); + } else { /* clk sync. bypassed */ + + if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ + /*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ + /*printf("Aborting!!!\n");1 */ + /*hang();1 */ + tmp_dunit_control_low = 0xC4000540; + } else + tmp_dunit_control_low = 0xC3000540; + DP (printf + ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + + default: + printf ("Max. CL is out of range %d\n", + info->maxClSupported_DDR); + hang (); + break; + } /* end DDR switch */ + break; + } /* end CL switch */ + + /* Write results of CL detection procedure */ + /* set SDRAM mode reg. 0x141c */ + GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); + + /* set SDRAM mode SetCommand 0x1418 */ + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + } + + /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ + GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low); + + /* set SDRAM mode SetCommand 0x1418 */ + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + } + +/*------------------------------------------------------------------------------ */ + + /* bank parameters */ + /* SDRAM address decode register 0x1410 */ + /* program this with the default value */ + tmp = 0x02; /* power-up default address select decoding value */ + + DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); +/* figure out the DRAM chip size */ + sdram_chip_size = + (1 << (info->numOfRowAddresses + info->numOfColAddresses)); + sdram_chip_size *= info->sdramWidth; + sdram_chip_size *= 4; + DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); + /* divide sdram chip size by 64 Mbits */ + sdram_chip_size = sdram_chip_size / 0x4000000; + switch (sdram_chip_size) { + case 1: /* 64 Mbit */ + case 2: /* 128 Mbit */ + DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + tmp |= (0x00 << 4); + break; + case 4: /* 256 Mbit */ + case 8: /* 512 Mbit */ + DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + tmp |= (0x01 << 4); + break; + case 16: /* 1 Gbit */ + case 32: /* 2 Gbit */ + DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + tmp |= (0x02 << 4); + break; + default: + printf ("Error in dram size calculation\n"); + printf ("RAM-Device_size is unsupported\n"); + hang (); + } + + /* SDRAM address control */ + GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); + DP (printf + ("setting up sdram address control (0x1410) with: %08lx \n", + tmp)); + +/* ------------------------------------------------------------------------------ */ +/* same settings for registerd & non-registerd DDR SDRAM */ + DP (printf + ("setting up sdram_timing_control_low (0x1408) with: %08x \n", + 0x01501220)); + /*ronen db64460 */ + GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220); + + +/* ------------------------------------------------------------------------------ */ + + /* SDRAM configuration */ + tmp = GTREGREAD (SDRAM_CONFIG); + + if (info->registeredAddrAndControlInputs + || info->registeredDQMBinputs) { + tmp |= (1 << 17); + DP (printf + ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", + info->registeredAddrAndControlInputs, + info->registeredDQMBinputs)); + } + + /* Use buffer 1 to return read data to the CPU + * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*". Assuming "= *" + +indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". Assuming "= *" + +4460 */ + tmp |= (1 << 26); + DP (printf + ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", + GTREGREAD (SDRAM_CONFIG))); + DP (printf + ("After Buffer assignment - sdram_conf (0x1400): %08x\n", + GTREGREAD (SDRAM_CONFIG))); + + /* SDRAM timing To_do: */ +/* ------------------------------------------------------------------------------ */ + /* ronen db64460 */ + DP (printf + ("setting up sdram_timing_control_high (0x140c) with: %08x \n", + 0xc)); + GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc); + + DP (printf + ("setting up sdram address pads control (0x14c0) with: %08x \n", + 0x7d5014a)); + GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); + + DP (printf + ("setting up sdram data pads control (0x14c4) with: %08x \n", + 0x7d5014a)); + GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); + +/* ------------------------------------------------------------------------------ */ + + /* set the SDRAM configuration for each bank */ + +/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ + { + i = info->slot; + DP (printf + ("\n*** Running a MRS cycle for bank %d ***\n", i)); + + /* map the bank */ + memory_map_bank (i, 0, GB / 4); + + /* set SDRAM mode */ /* To_do check it */ + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + check = GTREGREAD (SDRAM_OPERATION); + DP (printf + ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", + check)); + + + /* switch back to normal operation mode */ + GT_REG_WRITE (SDRAM_OPERATION, 0); + check = GTREGREAD (SDRAM_OPERATION); + DP (printf + ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", + check)); + + /* unmap the bank */ + memory_map_bank (i, 0, 0); + } + + return 0; + +} + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +long int dram_size (long int *base, long int maxsize) +{ + volatile long int *addr, *b = base; + long int cnt, val, save1, save2; + +#define STARTVAL (1<<20) /* start test at 1M */ + for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); + cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + save1 = *addr; /* save contents of addr */ + save2 = *b; /* save contents of base */ + + *addr = cnt; /* write cnt to addr */ + *b = 0; /* put null at base */ + + /* check at base address */ + if ((*b) != 0) { + *addr = save1; /* restore *addr */ + *b = save2; /* restore *b */ + return (0); + } + val = *addr; /* read *addr */ + val = *addr; /* read *addr */ + + *addr = save1; + *b = save2; + + if (val != cnt) { + DP (printf + ("Found %08x at Address %08x (failure)\n", + (unsigned int) val, (unsigned int) addr)); + /* fix boundary condition.. STARTVAL means zero */ + if (cnt == STARTVAL / sizeof (long)) + cnt = 0; + return (cnt * sizeof (long)); + } + } + return maxsize; +} + +/* ------------------------------------------------------------------------- */ + +/* ppcboot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int initdram (int board_type) +{ + int s0 = 0, s1 = 0; + int checkbank[4] = {[0 ... 3] = 0 }; + ulong realsize, total, check; + AUX_MEM_DIMM_INFO dimmInfo1; + AUX_MEM_DIMM_INFO dimmInfo2; + int nhr, bank_no; + ulong dest, memSpaceAttr; + + /* first, use the SPD to get info about the SDRAM/ DDRRAM */ + + /* check the NHR bit and skip mem init if it's already done */ + nhr = get_hid0 () & (1 << 16); + + if (nhr) { + printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); + } else { + /* DIMM0 */ + s0 = check_dimm (0, &dimmInfo1); + + /* DIMM1 */ + s1 = check_dimm (1, &dimmInfo2); + + memory_map_bank (0, 0, 0); + memory_map_bank (1, 0, 0); + memory_map_bank (2, 0, 0); + memory_map_bank (3, 0, 0); + + /* ronen check correct set of DIMMS */ + if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) { + if (dimmInfo1.errorCheckType != + dimmInfo2.errorCheckType) + printf ("***WARNNING***!!!! different ECC support of the DIMMS\n"); + if (dimmInfo1.maxClSupported_DDR != + dimmInfo2.maxClSupported_DDR) + printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n"); + if (dimmInfo1.registeredAddrAndControlInputs != + dimmInfo2.registeredAddrAndControlInputs) + printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n"); + } + + if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) { + printf ("Setup for DIMM1 failed.\n"); + } + + if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) { + printf ("Setup for DIMM2 failed.\n"); + } + + /* set the NHR bit */ + set_hid0 (get_hid0 () | (1 << 16)); + } + /* next, size the SDRAM banks */ + + realsize = total = 0; + check = GB / 4; + if (dimmInfo1.numOfModuleBanks > 0) { + checkbank[0] = 1; + } + if (dimmInfo1.numOfModuleBanks > 1) { + checkbank[1] = 1; + } + if (dimmInfo1.numOfModuleBanks > 2) + printf ("Error, SPD claims DIMM1 has >2 banks\n"); + + printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks); + + if (dimmInfo2.numOfModuleBanks > 0) { + checkbank[2] = 1; + } + if (dimmInfo2.numOfModuleBanks > 1) { + checkbank[3] = 1; + } + if (dimmInfo2.numOfModuleBanks > 2) + printf ("Error, SPD claims DIMM2 has >2 banks\n"); + + printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); + + for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + /* skip over banks that are not populated */ + if (!checkbank[bank_no]) + continue; + + /* ronen - realsize = dram_size((long int *)total, check); */ + if (bank_no == 0 || bank_no == 1) { + if (checkbank[1] == 1) + realsize = dimmInfo1.size / 2; + else + realsize = dimmInfo1.size; + } + if (bank_no == 2 || bank_no == 3) { + if (checkbank[3] == 1) + realsize = dimmInfo2.size / 2; + else + realsize = dimmInfo2.size; + } + memory_map_bank (bank_no, total, realsize); + + /* ronen - initialize the DRAM for ECC */ +#ifdef CONFIG_MV64460_ECC + if ((dimmInfo1.errorCheckType != 0) && + ((dimmInfo2.errorCheckType != 0) + || (dimmInfo2.numOfModuleBanks == 0))) { + printf ("ECC Initialization of Bank %d:", bank_no); + memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8; + mvDmaSetMemorySpace (0, 0, memSpaceAttr, total, + realsize); + for (dest = total; dest < total + realsize; + dest += _8M) { + mvDmaTransfer (0, total, dest, _8M, + BIT8 /*DMA_DTL_128BYTES */ | + BIT3 /*DMA_HOLD_SOURCE_ADDR */ + | + BIT11 + /*DMA_BLOCK_TRANSFER_MODE */ ); + while (mvDmaIsChannelActive (0)); + } + printf (" PASS\n"); + } +#endif + + total += realsize; + } + + /* ronen */ + switch ((GTREGREAD (0x141c) >> 4) & 0x7) { + case 0x2: + printf ("CAS Latency = 2"); + break; + case 0x3: + printf ("CAS Latency = 3"); + break; + case 0x5: + printf ("CAS Latency = 1.5"); + break; + case 0x6: + printf ("CAS Latency = 2.5"); + break; + } + printf (" tRP = %d tRAS = %d tRCD=%d\n", + ((GTREGREAD (0x1408) >> 8) & 0xf) + 1, + ((GTREGREAD (0x1408) >> 20) & 0xf) + 1, + ((GTREGREAD (0x1408) >> 4) & 0xf) + 1); + +/* Setup Ethernet DMA Adress window to DRAM Area */ + if (total > _256M) + printf ("*** ONLY the first 256MB DRAM memory are used out of the "); + else + printf ("Total SDRAM memory is "); + /* (cause all the 4 BATS are taken) */ + return (total); +} + + +/* ronen- add Idma functions for usage of the ecc dram init. */ +/******************************************************************************* +* mvDmaIsChannelActive - Checks if a engine is busy. +********************************************************************************/ +int mvDmaIsChannelActive (int engine) +{ + ulong data; + + data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine); + if (data & BIT14 /*activity status */ ) { + return 1; + } + return 0; +} + +/******************************************************************************* +* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding +* map. +*******************************************************************************/ +int mvDmaSetMemorySpace (ulong memSpace, + ulong memSpaceTarget, + ulong memSpaceAttr, ulong baseAddress, ulong size) +{ + ulong temp; + + /* The base address must be aligned to the size. */ + if (baseAddress % size != 0) { + return 0; + } + if (size >= 0x10000 /*64K */ ) { + size &= 0xffff0000; + baseAddress = (baseAddress & 0xffff0000); + /* Set the new attributes */ + GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8, + (baseAddress | memSpaceTarget | memSpaceAttr)); + GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8), + (size - 1) & 0xffff0000); + temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG); + GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, + (temp & ~(BIT0 << memSpace))); + return 1; + } + return 0; +} + + +/******************************************************************************* +* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4 +* DMA channels. +********************************************************************************/ +int mvDmaTransfer (int engine, ulong sourceAddr, + ulong destAddr, ulong numOfBytes, ulong command) +{ + ulong engOffReg = 0; /* Engine Offset Register */ + + if (numOfBytes > 0xffff) { + command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ; + } + command = command | ((command >> 6) & 0x7); + engOffReg = engine * 4; + GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, + numOfBytes); + GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, + sourceAddr); + GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, + destAddr); + command = + command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9 + /*DMA_NON_CHAIN_MODE */ ; + /* Activate DMA engine By writting to mvDmaControlRegister */ + GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command); + return 1; +} + +/**************************************************************************************** + * SDRAM INIT * + * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * + * This procedure fits only the Atlantis * + * * + ***************************************************************************************/ + + +/**************************************************************************************** + * DFCDL initialize MV643xx Design Considerations * + * * + ***************************************************************************************/ +int set_dfcdlInit (void) +{ + /*ronen the dfcdl init are done by the I2C */ + return (0); +} diff --git a/board/Marvell/db64460/u-boot.lds b/board/Marvell/db64460/u-boot.lds new file mode 100644 index 0000000..d89eb6c --- /dev/null +++ b/board/Marvell/db64460/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h new file mode 100644 index 0000000..081d5fd --- /dev/null +++ b/board/Marvell/include/core.h @@ -0,0 +1,238 @@ +/* Core.h - Basic core logic functions and definitions */ + +/* Copyright Galileo Technology. */ + +/* +DESCRIPTION +This header file contains simple read/write macros for addressing +the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address +space). The macros take care of Big/Little endian conversions. +*/ + +#ifndef __INCcoreh +#define __INCcoreh + +#include "mv_gen_reg.h" + +extern unsigned int INTERNAL_REG_BASE_ADDR; + +/****************************************/ +/* GENERAL Definitions */ +/****************************************/ + +#define NO_BIT 0x00000000 +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#define _1K 0x00000400 +#define _2K 0x00000800 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _3M 0x00300000 +#define _4M 0x00400000 +#define _5M 0x00500000 +#define _6M 0x00600000 +#define _7M 0x00700000 +#define _8M 0x00800000 +#define _9M 0x00900000 +#define _10M 0x00a00000 +#define _11M 0x00b00000 +#define _12M 0x00c00000 +#define _13M 0x00d00000 +#define _14M 0x00e00000 +#define _15M 0x00f00000 +#define _16M 0x01000000 + +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + +typedef enum _bool{false,true} bool; + +/* Little to Big endian conversion macros */ + +#ifdef LE /* Little Endian */ +#define SHORT_SWAP(X) (X) +#define WORD_SWAP(X) (X) +#define LONG_SWAP(X) ((l64)(X)) + +#else /* Big Endian */ +#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) + +#define WORD_SWAP(X) (((X)&0xff)<<24)+ \ + (((X)&0xff00)<<8)+ \ + (((X)&0xff0000)>>8)+ \ + (((X)&0xff000000)>>24) + +#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ + (((X)&0xff00ULL)<<40)+ \ + (((X)&0xff0000ULL)<<24)+ \ + (((X)&0xff000000ULL)<<8)+ \ + (((X)&0xff00000000ULL)>>8)+ \ + (((X)&0xff0000000000ULL)>>24)+ \ + (((X)&0xff000000000000ULL)>>40)+ \ + (((X)&0xff00000000000000ULL)>>56)) + +#endif + +#ifndef NULL +#define NULL 0 +#endif + +/* Those two definitions were defined to be compatible with MIPS */ +#define NONE_CACHEABLE 0x00000000 +#define CACHEABLE 0x00000000 + +/* 750 cache line */ +#define CACHE_LINE_SIZE 32 +#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1) +#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS) + +/* Read/Write to/from GT`s internal registers */ +#define GT_REG_READ(offset, pData) \ +*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ + INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ +*pData = WORD_SWAP(*pData) + +#define GTREGREAD(offset) \ + (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ + INTERNAL_REG_BASE_ADDR | (offset))) )) + +#define GT_REG_WRITE(offset, data) \ +*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \ + WORD_SWAP(data) + +/* Write 32/16/8 bit */ +#define WRITE_CHAR(address, data) \ + *((unsigned char *)(address)) = data +#define WRITE_SHORT(address, data) \ + *((unsigned short *)(address)) = data +#define WRITE_WORD(address, data) \ + *((unsigned int *)(address)) = data + +#define GT_WRITE_CHAR(address, data) WRITE_CHAR(address, data) + +/* Write 32/16/8 bit NonCacheable */ +/* +#define GT_WRITE_CHAR(address, data) \ + (*((unsigned char *)NONE_CACHEABLE(address))) = data +#define GT_WRITE_SHORT(address, data) \ + (*((unsigned short *)NONE_CACHEABLE(address))) = data +#define GT_WRITE_WORD(address, data) \ + (*((unsigned int *)NONE_CACHEABLE(address))) = data +*/ + /*#define GT_WRITE_CHAR(address, data) ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */ + + /*#define GT_WRITE_SHORT(address, data) ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */ + + /*#define GT_WRITE_WORD(address, data) ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */ + + +/* Read 32/16/8 bits - returns data in variable. */ +#define READ_CHAR(address, pData) \ + *pData = *((volatile unsigned char *)(address)) + +#define READ_SHORT(address, pData) \ + *pData = *((volatile unsigned short *)(address)) + +#define READ_WORD(address, pData) \ + *pData = *((volatile unsigned int *)(address)) + +/* Read 32/16/8 bit - returns data direct. */ +#define READCHAR(address) \ + *((volatile unsigned char *)((address) | NONE_CACHEABLE)) + +#define READSHORT(address) \ + *((volatile unsigned short *)((address) | NONE_CACHEABLE)) + +#define READWORD(address) \ + *((volatile unsigned int *)((address) | NONE_CACHEABLE)) + +/* Those two Macros were defined to be compatible with MIPS */ +#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff) +#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE) + +/* SET_REG_BITS(regOffset,bits) - + gets register offset and bits: a 32bit value. It set to logic '1' in the + internal register the bits which given as an input example: + SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic + '1' in register 0x840 while the other bits stays as is. */ +#define SET_REG_BITS(regOffset,bits) \ + *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ + regOffset) |= (unsigned int)WORD_SWAP(bits) + +/* RESET_REG_BITS(regOffset,bits) - + gets register offset and bits: a 32bit value. It set to logic '0' in the + internal register the bits which given as an input example: + RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic + '0' in register 0x840 while the other bits stays as is. */ +#define RESET_REG_BITS(regOffset,bits) \ + *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ + | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) +/* gets register offset and bits: a 32bit value. It set to logic '1' in the + internal register the bits which given as an input example: + GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic + '1' in register 0x840 while the other bits stays as is. */ + /*#define GT_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */ + /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */ +#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits) +/* gets register offset and bits: a 32bit value. It set to logic '0' in the + internal register the bits which given as an input example: + GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to + logic '0' in register 0x840 while the other bits stays as is. */ + /*#define GT_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */ +#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits) + + +#define DEBUG_LED0_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0) +#define DEBUG_LED1_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0) +#define DEBUG_LED2_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0) +#define DEBUG_LED0_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0) +#define DEBUG_LED1_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0) +#define DEBUG_LED2_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0) + +#endif /* __INCcoreh */ diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h new file mode 100644 index 0000000..0947b6e --- /dev/null +++ b/board/Marvell/include/memory.h @@ -0,0 +1,173 @@ +/* Memory.h - Memory mappings and remapping functions declarations */ + +/* Copyright - Galileo technology. */ + +#ifndef __INCmemoryh +#define __INCmemoryh + +/* includes */ + +#include "core.h" + +/* defines */ + +#define DONT_MODIFY 0xffffffff +#define PARITY_SUPPORT 0x40000000 +#define MINIMUM_MEM_BANK_SIZE 0x10000 +#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000 +#define MINIMUM_PCI_WINDOW_SIZE 0x10000 +#define MINIMUM_ACCESS_WIN_SIZE 0x10000 + +#define _8BIT 0x00000000 +#define _16BIT 0x00100000 +#define _32BIT 0x00200000 +#define _64BIT 0x00300000 + +/* typedefs */ + + typedef struct deviceParam +{ /* boundary values */ + unsigned int turnOff; /* 0x0 - 0xf */ + unsigned int acc2First; /* 0x0 - 0x1f */ + unsigned int acc2Next; /* 0x0 - 0x1f */ + unsigned int ale2Wr; /* 0x0 - 0xf */ + unsigned int wrLow; /* 0x0 - 0xf */ + unsigned int wrHigh; /* 0x0 - 0xf */ + unsigned int badrSkew; /* 0x0 - 0x2 */ + unsigned int DPEn; /* 0x0 - 0x1 */ + unsigned int deviceWidth; /* in Bytes */ +} DEVICE_PARAM; + + +typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK; +typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE; + +/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \ + MEM_REGION3,MEM_REGION4,MEM_REGION5, \ + MEM_REGION6,MEM_REGION7} \ + MEMORY_PROTECT_REGION;*/ +/* There are four possible windows that can be defined as protected */ +typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2, + MEM_WINDOW3 + } MEMORY_PROTECT_WINDOW; +/* When defining a protected window , this paramter indicates whether it + is accessible or not */ +typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \ + MEMORY_ACCESS; +typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \ + MEMORY_ACCESS_WRITE; +typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \ + MEMORY_CACHE_PROTECT; +typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \ + MEMORY_SNOOP_TYPE; +typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \ + MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \ + MEMORY_SNOOP_REGION; + +/* There are 21 memory windows dedicated for the varios interfaces (PCI, + devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's + address decoding mechanism. */ +typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1, + CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3, + DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5, + DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7, + BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9, + PCI_0_MEM0_WINDOW = BIT10, + PCI_0_MEM1_WINDOW = BIT11, + PCI_0_MEM2_WINDOW = BIT12, + PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14, + PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16, + PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18, + INTEGRATED_SRAM_WINDOW = BIT19, + INTERNAL_SPACE_WINDOW = BIT20, + ALL_WINDOWS = 0X1FFFFF + } MEMORY_WINDOW; + +typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED + } MEMORY_WINDOW_STATUS; + + +typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3 +#ifdef INCLUDE_PCI_1 + ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3 +#endif /* INCLUDE_PCI_1 */ + } PCI_MEM_WINDOW; + + +/* -------------------------------------------------------------------------------------------------*/ + +/* functions */ +unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank); +unsigned int memoryGetDeviceBaseAddress(DEVICE device); +/* New at MV6436x */ +unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow); +unsigned int memoryGetBankSize(MEMORY_BANK bank); +unsigned int memoryGetDeviceSize(DEVICE device); +unsigned int memoryGetDeviceWidth(DEVICE device); +/* New at MV6436x */ +unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow); + +/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/ +bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength); +/* Set a new base and size for one of the memory banks (CS0 - CS3) */ +bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase, + unsigned int bankSize); +bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength); + +/* Change the Internal Register Base Address to a new given Address. */ +bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); +/* returns internal Register Space Base Address. */ +unsigned int memoryGetInternalRegistersSpace(void); + +/* Returns the integrated SRAM Base Address. */ +unsigned int memoryGetInternalSramBaseAddr(void); +/* -------------------------------------------------------------------------------------------------*/ + +/* Set new base address for the integrated SRAM. */ +void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress); +/* -------------------------------------------------------------------------------------------------*/ + +/* Delete a protection feature to a given space. */ +void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window); +/* -------------------------------------------------------------------------------------------------*/ + +/* Writes a new remap value to the remap register */ +unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow, + unsigned int remapValueHigh, + unsigned int remapValueLow); +/* -------------------------------------------------------------------------------------------------*/ + +/* Configurate the protection feature to a given space. */ +bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window, + MEMORY_ACCESS gtMemoryAccess, + MEMORY_ACCESS_WRITE gtMemoryWrite, + MEMORY_CACHE_PROTECT cacheProtection, + unsigned int baseAddress, + unsigned int size); + +/* Configurate the protection feature to a given space. */ +/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, + MEMORY_ACCESS memoryAccess, + MEMORY_ACCESS_WRITE memoryWrite, + MEMORY_CACHE_PROTECT cacheProtection, + unsigned int baseAddress, + unsigned int regionLength); */ +/* Configurate the snoop feature to a given space. */ +bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, + MEMORY_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength); + +bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue); +bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); +bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); +/* Set a new base and size for one of the PCI windows. */ +bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase, + unsigned int pciWindowSize); + +/* Disable or enable one of the 21 windows dedicated for the CPU's + address decoding mechanism */ +void MemoryDisableWindow(MEMORY_WINDOW window); +void MemoryEnableWindow (MEMORY_WINDOW window); +MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window); +#endif /* __INCmemoryh */ diff --git a/board/Marvell/include/mv_gen_reg.h b/board/Marvell/include/mv_gen_reg.h new file mode 100644 index 0000000..5e4f076 --- /dev/null +++ b/board/Marvell/include/mv_gen_reg.h @@ -0,0 +1,2288 @@ +/* mv_gen_reg.h - Internal registers definition file */ +/* Copyright - Galileo technology. */ + + +/******************************************************************************* +* Copyright 2002, GALILEO TECHNOLOGY, LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI). * +******************************************************************************** +* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file. +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv_gen_regh +#define __INCmv_gen_regh + + +/* Supported by the Atlantis */ +#define INCLUDE_PCI_1 +#define INCLUDE_PCI_0_ARBITER +#define INCLUDE_PCI_1_ARBITER +#define INCLUDE_SNOOP_SUPPORT +#define INCLUDE_P2P +#define INCLUDE_ETH_PORT_2 +#define INCLUDE_CPU_MAPPING +#define INCLUDE_MPSC + +/* Not supported features */ +#undef INCLUDE_CNTMR_4_7 +#undef INCLUDE_DMA_4_7 + + +/****************************************/ +/* Processor Address Space */ +/****************************************/ +/* DDR SDRAM BAR and size registers */ + +/* Sdram's BAR'S */ +#define SCS_0_LOW_DECODE_ADDRESS 0x008 +#define SCS_0_HIGH_DECODE_ADDRESS 0x010 +#define SCS_1_LOW_DECODE_ADDRESS 0x208 +#define SCS_1_HIGH_DECODE_ADDRESS 0x210 +#define SCS_2_LOW_DECODE_ADDRESS 0x018 +#define SCS_2_HIGH_DECODE_ADDRESS 0x020 +#define SCS_3_LOW_DECODE_ADDRESS 0x218 +#define SCS_3_HIGH_DECODE_ADDRESS 0x220 + +/* Make it fit the MV64360 and MV64460 Lowlevel driver */ +#define CS_0_BASE_ADDR SCS_0_LOW_DECODE_ADDRESS +#define CS_0_SIZE SCS_0_HIGH_DECODE_ADDRESS +#define CS_1_BASE_ADDR SCS_1_LOW_DECODE_ADDRESS +#define CS_1_SIZE SCS_1_HIGH_DECODE_ADDRESS +#define CS_2_BASE_ADDR SCS_2_LOW_DECODE_ADDRESS +#define CS_2_SIZE SCS_2_HIGH_DECODE_ADDRESS +#define CS_3_BASE_ADDR SCS_3_LOW_DECODE_ADDRESS +#define CS_3_SIZE SCS_3_HIGH_DECODE_ADDRESS + +/* Devices BAR'S */ +#define CS_0_LOW_DECODE_ADDRESS 0x028 +#define CS_0_HIGH_DECODE_ADDRESS 0x030 +#define CS_1_LOW_DECODE_ADDRESS 0x228 +#define CS_1_HIGH_DECODE_ADDRESS 0x230 +#define CS_2_LOW_DECODE_ADDRESS 0x248 +#define CS_2_HIGH_DECODE_ADDRESS 0x250 +#define CS_3_LOW_DECODE_ADDRESS 0x038 +#define CS_3_HIGH_DECODE_ADDRESS 0x040 +#define BOOTCS_LOW_DECODE_ADDRESS 0x238 +#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 + +/* Make it fit the MV64360 and MV64460 Lowlevel driver */ +/* Devices BAR and size registers */ + +#define DEV_CS0_BASE_ADDR CS_0_LOW_DECODE_ADDRESS +#define DEV_CS0_SIZE CS_0_HIGH_DECODE_ADDRESS +#define DEV_CS1_BASE_ADDR CS_1_LOW_DECODE_ADDRESS +#define DEV_CS1_SIZE CS_1_HIGH_DECODE_ADDRESS +#define DEV_CS2_BASE_ADDR CS_2_LOW_DECODE_ADDRESS +#define DEV_CS2_SIZE CS_2_HIGH_DECODE_ADDRESS +#define DEV_CS3_BASE_ADDR CS_3_LOW_DECODE_ADDRESS +#define DEV_CS3_SIZE CS_3_HIGH_DECODE_ADDRESS +#define BOOTCS_BASE_ADDR BOOTCS_LOW_DECODE_ADDRESS +#define BOOTCS_SIZE BOOTCS_HIGH_DECODE_ADDRESS + +/* PCI 0 BAR and size registers old names of evb64260*/ + +#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 +#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 +#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 +#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 +#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 +#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 +#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 +#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 +#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 +#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 + +/* Make it fit the MV64360 and MV64460 Lowlevel driver */ +#define PCI_0_IO_BASE_ADDR 0x048 +#define PCI_0_IO_SIZE 0x050 +#define PCI_0_MEMORY0_BASE_ADDR 0x058 +#define PCI_0_MEMORY0_SIZE 0x060 +#define PCI_0_MEMORY1_BASE_ADDR 0x080 +#define PCI_0_MEMORY1_SIZE 0x088 +#define PCI_0_MEMORY2_BASE_ADDR 0x258 +#define PCI_0_MEMORY2_SIZE 0x260 +#define PCI_0_MEMORY3_BASE_ADDR 0x280 +#define PCI_0_MEMORY3_SIZE 0x288 + +/* PCI 1 BAR and size registers old names of evb64260*/ +#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 +#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 +#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 +#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 +#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 +#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 +#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 +#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 +#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 +#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 + +/* Make it fit the MV64360 and MV64460 Lowlevel driver */ +#define PCI_1_IO_BASE_ADDR 0x090 +#define PCI_1_IO_SIZE 0x098 +#define PCI_1_MEMORY0_BASE_ADDR 0x0a0 +#define PCI_1_MEMORY0_SIZE 0x0a8 +#define PCI_1_MEMORY1_BASE_ADDR 0x0b0 +#define PCI_1_MEMORY1_SIZE 0x0b8 +#define PCI_1_MEMORY2_BASE_ADDR 0x2a0 +#define PCI_1_MEMORY2_SIZE 0x2a8 +#define PCI_1_MEMORY3_BASE_ADDR 0x2b0 +#define PCI_1_MEMORY3_SIZE 0x2b8 + +/* internal registers space base address */ +#define INTERNAL_SPACE_DECODE 0x068 +#define INTERNAL_SPACE_BASE_ADDR INTERNAL_SPACE_DECODE + +/* SRAM base address */ +#define INTEGRATED_SRAM_BASE_ADDR 0x268 + +/* Enables the CS , DEV_CS , PCI 0 and PCI 1 + windows above */ +#define BASE_ADDR_ENABLE 0x278 + + +#define CPU_0_LOW_DECODE_ADDRESS 0x290 +#define CPU_0_HIGH_DECODE_ADDRESS 0x298 +#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 +#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 + +/****************************************/ +/* PCI remap registers */ +/****************************************/ +/*****************************************************************************************/ + /* PCI 0 */ +/* old fashion evb 64260 */ +#define PCI_0I_O_ADDRESS_REMAP 0x0f0 +#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 +#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 +#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 +#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 +#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 +#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 +#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 +#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 + +#define PCI_0_IO_ADDR_REMAP PCI_0I_O_ADDRESS_REMAP +#define PCI_0_MEMORY0_LOW_ADDR_REMAP PCI_0MEMORY0_ADDRESS_REMAP +#define PCI_0_MEMORY0_HIGH_ADDR_REMAP PCI_0MEMORY0_HIGH_ADDRESS_REMAP +#define PCI_0_MEMORY1_LOW_ADDR_REMAP PCI_0MEMORY1_ADDRESS_REMAP +#define PCI_0_MEMORY1_HIGH_ADDR_REMAP PCI_0MEMORY1_HIGH_ADDRESS_REMAP +#define PCI_0_MEMORY2_LOW_ADDR_REMAP PCI_0MEMORY2_ADDRESS_REMAP +#define PCI_0_MEMORY2_HIGH_ADDR_REMAP PCI_0MEMORY2_HIGH_ADDRESS_REMAP +#define PCI_0_MEMORY3_LOW_ADDR_REMAP PCI_0MEMORY3_ADDRESS_REMAP +#define PCI_0_MEMORY3_HIGH_ADDR_REMAP PCI_0MEMORY3_HIGH_ADDRESS_REMAP + + /* PCI 1 */ +/* old fashion evb 64260 */ +#define PCI_1I_O_ADDRESS_REMAP 0x108 +#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 +#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 +#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 +#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 +#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 +#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 +#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 +#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 + +#define PCI_1_IO_ADDR_REMAP PCI_1I_O_ADDRESS_REMAP +#define PCI_1_MEMORY0_LOW_ADDR_REMAP PCI_1MEMORY0_ADDRESS_REMAP +#define PCI_1_MEMORY0_HIGH_ADDR_REMAP PCI_1MEMORY0_HIGH_ADDRESS_REMAP +#define PCI_1_MEMORY1_LOW_ADDR_REMAP PCI_1MEMORY1_ADDRESS_REMAP +#define PCI_1_MEMORY1_HIGH_ADDR_REMAP PCI_1MEMORY1_HIGH_ADDRESS_REMAP +#define PCI_1_MEMORY2_LOW_ADDR_REMAP PCI_1MEMORY2_ADDRESS_REMAP +#define PCI_1_MEMORY2_HIGH_ADDR_REMAP PCI_1MEMORY2_HIGH_ADDRESS_REMAP +#define PCI_1_MEMORY3_LOW_ADDR_REMAP PCI_1MEMORY3_ADDRESS_REMAP +#define PCI_1_MEMORY3_HIGH_ADDR_REMAP PCI_1MEMORY3_HIGH_ADDRESS_REMAP + +/* old fashion evb 64260 */ +#define CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 +#define CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 +#define CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 +#define CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 +#define CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 +#define CPU_GE_HEADERS_RETARGET_BASE 0x3d8 + +/* MV64360 and MV64460 no changes needed*/ +/*****************************************************************************************/ + +/****************************************/ +/* CPU Control Registers */ +/****************************************/ +/* CPU MASTER CONTROL REGISTER */ +#define CPU_CONFIGURATION 0x000 +#define CPU_MASTER_CONTROL 0x160 + +#define CPU_CONFIG 0x000 +#define CPU_MODE 0x120 +#define CPU_MASTER_CONTROL 0x160 +/* new in MV64360 and MV64460 */ +#define CPU_CROSS_BAR_CONTROL_LOW 0x150 +#define CPU_CROSS_BAR_CONTROL_HIGH 0x158 +#define CPU_CROSS_BAR_TIMEOUT 0x168 + +/****************************************/ +/* SMP RegisterS */ +/****************************************/ + +#define SMP_WHO_AM_I 0x200 +#define SMP_CPU0_DOORBELL 0x214 +#define SMP_CPU0_DOORBELL_CLEAR 0x21C +#define SMP_CPU1_DOORBELL 0x224 +#define SMP_CPU1_DOORBELL_CLEAR 0x22C +#define SMP_CPU0_DOORBELL_MASK 0x234 +#define SMP_CPU1_DOORBELL_MASK 0x23C +#define SMP_SEMAPHOR0 0x244 +#define SMP_SEMAPHOR1 0x24c +#define SMP_SEMAPHOR2 0x254 +#define SMP_SEMAPHOR3 0x25c +#define SMP_SEMAPHOR4 0x264 +#define SMP_SEMAPHOR5 0x26c +#define SMP_SEMAPHOR6 0x274 +#define SMP_SEMAPHOR7 0x27c + + +/****************************************/ +/* CPU Sync Barrier */ +/****************************************/ +#define CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 +#define CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 +#define CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 +#define CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 + + +/****************************************/ +/* CPU Access Protect */ +/****************************************/ + +#define CPU_LOW_PROTECT_ADDRESS_0 0x180 +#define CPU_HIGH_PROTECT_ADDRESS_0 0x188 +#define CPU_LOW_PROTECT_ADDRESS_1 0x190 +#define CPU_HIGH_PROTECT_ADDRESS_1 0x198 +#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0 +#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8 +#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0 +#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8 +/*#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0 +#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8 +#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0 +#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8 +#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0 +#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8 +#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0 +#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8 +*/ + +#define CPU_PROTECT_WINDOW_0_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */ +#define CPU_PROTECT_WINDOW_0_SIZE CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */ +#define CPU_PROTECT_WINDOW_1_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */ +#define CPU_PROTECT_WINDOW_1_SIZE CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */ +#define CPU_PROTECT_WINDOW_2_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */ +#define CPU_PROTECT_WINDOW_2_SIZE CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */ +#define CPU_PROTECT_WINDOW_3_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */ +#define CPU_PROTECT_WINDOW_3_SIZE CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */ + + +/****************************************/ +/* Snoop Control */ +/****************************************/ + +/*#define SNOOP_BASE_ADDRESS_0 0x380 +#define SNOOP_TOP_ADDRESS_0 0x388 +#define SNOOP_BASE_ADDRESS_1 0x390 +#define SNOOP_TOP_ADDRESS_1 0x398 +#define SNOOP_BASE_ADDRESS_2 0x3a0 +#define SNOOP_TOP_ADDRESS_2 0x3a8 +#define SNOOP_BASE_ADDRESS_3 0x3b0 +#define SNOOP_TOP_ADDRESS_3 0x3b8 +*/ + +/****************************************/ +/* Integrated SRAM Registers */ +/****************************************/ + +#define SRAM_CONFIG 0x380 +#define SRAM_TEST_MODE 0x3F4 +#define SRAM_ERROR_CAUSE 0x388 +#define SRAM_ERROR_ADDR 0x390 +#define SRAM_ERROR_ADDR_HIGH 0x3F8 +#define SRAM_ERROR_DATA_LOW 0x398 +#define SRAM_ERROR_DATA_HIGH 0x3a0 +#define SRAM_ERROR_DATA_PARITY 0x3a8 + +/****************************************/ +/* CPU Error Report */ +/****************************************/ + +#define CPU_ERROR_ADDRESS_LOW 0x070 +#define CPU_ERROR_ADDRESS_HIGH 0x078 +#define CPU_ERROR_DATA_LOW 0x128 +#define CPU_ERROR_DATA_HIGH 0x130 +#define CPU_ERROR_PARITY 0x138 +#define CPU_ERROR_CAUSE 0x140 +#define CPU_ERROR_MASK 0x148 + +#define CPU_ERROR_ADDR_LOW CPU_ERROR_ADDRESS_LOW /* 0x0701 */ +#define CPU_ERROR_ADDR_HIGH CPU_ERROR_ADDRESS_HIGH /* 0x0781 */ + +/****************************************/ +/* Pslave Debug */ +/* CPU Interface Debug Registers */ +/****************************************/ + +#define X_0_ADDRESS 0x360 +#define X_0_COMMAND_ID 0x368 +#define X_1_ADDRESS 0x370 +#define X_1_COMMAND_ID 0x378 + /*#define WRITE_DATA_LOW 0x3c01 */ + /*#define WRITE_DATA_HIGH 0x3c81 */ + /*#define WRITE_BYTE_ENABLE 0x3e01 */ + /*#define READ_DATA_LOW 0x3d01 */ + /*#define READ_DATA_HIGH 0x3d81 */ + /*#define READ_ID 0x3e81 */ + +#define PUNIT_SLAVE_DEBUG_LOW X_0_ADDRESS /* 0x3601 */ +#define PUNIT_SLAVE_DEBUG_HIGH X_0_COMMAND_ID /* 0x3681 */ +#define PUNIT_MASTER_DEBUG_LOW X_1_ADDRESS /* 0x3701 */ +#define PUNIT_MASTER_DEBUG_HIGH X_1_COMMAND_ID /* 0x3781 */ +#define PUNIT_MMASK 0x3e4 + + +/****************************************/ +/* SDRAM and Device Address Space */ +/****************************************/ + +/****************************************/ +/* SDRAM Configuration */ +/****************************************/ +#define SDRAM_CONFIG 0x1400 /* MV64260 0x448 some changes*/ +#define D_UNIT_CONTROL_LOW 0x1404 /* NEW in MV64360 and MV64460 */ +#define D_UNIT_CONTROL_HIGH 0x1424 /* NEW in MV64360 and MV64460 */ +#define SDRAM_TIMING_CONTROL_LOW 0x1408 /* MV64260 0x4b4 new SDRAM TIMING REGISTER */ +#define SDRAM_TIMING_CONTROL_HIGH 0x140c /* MV64260 0x4b4 new SDRAM TIMING REGISTER */ +#define SDRAM_ADDR_CONTROL 0x1410 /* MV64260 0x47c some changes*/ +#define SDRAM_OPEN_PAGES_CONTROL 0x1414 /* NEW in MV64360 and MV64460 */ +#define SDRAM_OPERATION 0x1418 /* MV64260 0x474 some changes*/ +#define SDRAM_MODE 0x141c /* NEW in MV64360 and MV64460 */ +#define EXTENDED_DRAM_MODE 0x1420 /* NEW in MV64360 and MV64460 */ +#define SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 /* MV64260 0x4a8 NO changes*/ +#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 /* MV64260 0x4ac NO changes*/ +#define SDRAM_CROSS_BAR_TIMEOUT 0x1438 /* MV64260 0x4b0 NO changes*/ +#define SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 /* what is this ??? */ +#define SDRAM_DATA_PADS_CALIBRATION 0x14c4 /* what is this ??? */ +/****************************************/ +/* SDRAM Configuration MV64260 */ +/****************************************/ + /*#define SDRAM_CONFIGURATION 0x4481 */ + /*#define SDRAM_OPERATION_MODE 0x4741 */ + /*#define SDRAM_ADDRESS_DECODE 0x47c1 */ + /*#define SDRAM_UMA_CONTROL 0x4a4 eliminated in MV64360 and MV64460 */ + /*#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a81 */ + /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */ + /*#define SDRAM_CROSS_BAR_TIMEOUT 0x4b01 */ + /*#define SDRAM_TIMING 0x4b41 */ + + +/****************************************/ +/* SDRAM Error Report */ +/****************************************/ +#define SDRAM_ERROR_DATA_LOW 0x1444 /* MV64260 0x484 NO changes*/ +#define SDRAM_ERROR_DATA_HIGH 0x1440 /* MV64260 0x480 NO changes*/ +#define SDRAM_ERROR_ADDR 0x1450 /* MV64260 0x490 NO changes*/ +#define SDRAM_RECEIVED_ECC 0x1448 /* MV64260 0x488 NO changes*/ +#define SDRAM_CALCULATED_ECC 0x144c /* MV64260 0x48c NO changes*/ +#define SDRAM_ECC_CONTROL 0x1454 /* MV64260 0x494 NO changes*/ +#define SDRAM_ECC_ERROR_COUNTER 0x1458 /* MV64260 0x498 NO changes*/ +#define SDRAM_MMASK 0x1B40 /* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/ +/****************************************/ +/* SDRAM Error Report MV64260 */ +/****************************************/ + /*#define SDRAM_ERROR_DATA_LOW 0x4841 */ + /*#define SDRAM_ERROR_DATA_HIGH 0x4801 */ + /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x4901 */ + /*#define SDRAM_RECEIVED_ECC 0x4881 */ + /*#define SDRAM_CALCULATED_ECC 0x48c1 */ + /*#define SDRAM_ECC_CONTROL 0x4941 */ + /*#define SDRAM_ECC_ERROR_COUNTER 0x4981 */ + +/******************************************/ +/* Controlled Delay Line (CDL) Registers */ +/******************************************/ +#define DFCDL_CONFIG0 0x1480 +#define DFCDL_CONFIG1 0x1484 +#define DLL_WRITE 0x1488 +#define DLL_READ 0x148c +#define SRAM_ADDR 0x1490 +#define SRAM_DATA0 0x1494 +#define SRAM_DATA1 0x1498 +#define SRAM_DATA2 0x149c +#define DFCL_PROBE 0x14a0 + + +/****************************************/ +/* SDRAM Parameters only in MV64260 */ +/****************************************/ + + /*#define SDRAM_BANK0PARAMETERS 0x44C eliminated in MV64360 and MV64460 */ + /*#define SDRAM_BANK1PARAMETERS 0x450 eliminated in MV64360 and MV64460 */ + /*#define SDRAM_BANK2PARAMETERS 0x454 eliminated in MV64360 and MV64460 */ + /*#define SDRAM_BANK3PARAMETERS 0x458 eliminated in MV64360 and MV64460 */ + +/******************************************/ +/* Debug Registers */ +/******************************************/ + +#define DUNIT_DEBUG_LOW 0x1460 +#define DUNIT_DEBUG_HIGH 0x1464 +#define DUNIT_MMASK 0x1b40 + +/****************************************/ +/* SDunit Debug (for internal use) */ +/****************************************/ + +#define X0_ADDRESS 0x500 +#define X0_COMMAND_AND_ID 0x504 +#define X0_WRITE_DATA_LOW 0x508 +#define X0_WRITE_DATA_HIGH 0x50c +#define X0_WRITE_BYTE_ENABLE 0x518 +#define X0_READ_DATA_LOW 0x510 +#define X0_READ_DATA_HIGH 0x514 +#define X0_READ_ID 0x51c +#define X1_ADDRESS 0x520 +#define X1_COMMAND_AND_ID 0x524 +#define X1_WRITE_DATA_LOW 0x528 +#define X1_WRITE_DATA_HIGH 0x52c +#define X1_WRITE_BYTE_ENABLE 0x538 +#define X1_READ_DATA_LOW 0x530 +#define X1_READ_DATA_HIGH 0x534 +#define X1_READ_ID 0x53c +#define X0_SNOOP_ADDRESS 0x540 +#define X0_SNOOP_COMMAND 0x544 +#define X1_SNOOP_ADDRESS 0x548 +#define X1_SNOOP_COMMAND 0x54c + +/****************************************/ +/* Device Parameters */ +/****************************************/ + +#define DEVICE_BANK0PARAMETERS 0x45c +#define DEVICE_BANK1PARAMETERS 0x460 +#define DEVICE_BANK2PARAMETERS 0x464 +#define DEVICE_BANK3PARAMETERS 0x468 +#define DEVICE_BOOT_BANK_PARAMETERS 0x46c +#define DEVICE_CONTROL 0x4c0 +#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 +#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc +#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 + +/****************************************/ +/* Device Parameters */ +/****************************************/ + +#define DEVICE_BANK0_PARAMETERS DEVICE_BANK0PARAMETERS /* 0x45c1 */ +#define DEVICE_BANK1_PARAMETERS DEVICE_BANK1PARAMETERS /* 0x4601 */ +#define DEVICE_BANK2_PARAMETERS DEVICE_BANK2PARAMETERS /* 0x4641 */ +#define DEVICE_BANK3_PARAMETERS DEVICE_BANK3PARAMETERS /* 0x4681 */ +/*#define DEVICE_BOOT_BANK_PARAMETERS 0x46c1 */ +#define DEVICE_INTERFACE_CONTROL DEVICE_CONTROL /* 0x4c01 */ +#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW DEVICE_CROSS_BAR_CONTROL_LOW /* 0x4c81 */ +#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH DEVICE_CROSS_BAR_CONTROL_HIGH /* 0x4cc1 */ +#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT DEVICE_CROSS_BAR_TIMEOUT /* 0x4c41 */ + + +/****************************************/ +/* Device Interrupt */ +/****************************************/ + +#define DEVICE_INTERRUPT_CAUSE 0x4d0 +#define DEVICE_INTERRUPT_MASK 0x4d4 +#define DEVICE_ERROR_ADDRESS 0x4d8 + /*#define DEVICE_INTERRUPT_CAUSE 0x4d01 */ + /*#define DEVICE_INTERRUPT_MASK 0x4d41 */ +#define DEVICE_ERROR_ADDR DEVICE_ERROR_ADDRESS /*0x4d81 */ +#define DEVICE_ERROR_DATA 0x4dc +#define DEVICE_ERROR_PARITY 0x4e0 + +/****************************************/ +/* Device debug registers */ +/****************************************/ + +#define DEVICE_DEBUG_LOW 0x4e4 +#define DEVICE_DEBUG_HIGH 0x4e8 +#define RUNIT_MMASK 0x4f0 + +/****************************************/ +/* DMA Record */ +/****************************************/ + + /*#define CHANNEL4_DMA_BYTE_COUNT 0x9001 */ + /*#define CHANNEL5_DMA_BYTE_COUNT 0x9041 */ + /*#define CHANNEL6_DMA_BYTE_COUNT 0x9081 */ + /*#define CHANNEL7_DMA_BYTE_COUNT 0x90C1 */ + /*#define CHANNEL4_DMA_SOURCE_ADDRESS 0x9101 */ + /*#define CHANNEL5_DMA_SOURCE_ADDRESS 0x9141 */ + /*#define CHANNEL6_DMA_SOURCE_ADDRESS 0x9181 */ + /*#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C1 */ + /*#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x9201 */ + /*#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x9241 */ + /*#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x9281 */ + /*#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C1 */ + /*#define CHANNEL4NEXT_RECORD_POINTER 0x9301 */ + /*#define CHANNEL5NEXT_RECORD_POINTER 0x9341 */ + /*#define CHANNEL6NEXT_RECORD_POINTER 0x9381 */ + /*#define CHANNEL7NEXT_RECORD_POINTER 0x93C1 */ + /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x9701 */ + /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x9741 */ + /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x9781 */ + /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C1 */ + /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8901 */ + /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8941 */ + /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8981 */ + /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c1 */ + /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9901 */ + /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9941 */ + /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9981 */ + /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c1 */ + /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a01 */ + /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a41 */ + /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a81 */ + /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac1 */ + /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a01 */ + /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a41 */ + /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a81 */ + /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac1 */ + /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b01 */ + /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b41 */ + /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b81 */ + /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc1 */ + /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b01 */ + /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b41 */ + /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b81 */ + /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc1 */ + +/****************************************/ +/* DMA Channel Control */ +/****************************************/ + +#define CHANNEL0CONTROL 0x840 +#define CHANNEL0CONTROL_HIGH 0x880 +#define CHANNEL1CONTROL 0x844 +#define CHANNEL1CONTROL_HIGH 0x884 +#define CHANNEL2CONTROL 0x848 +#define CHANNEL2CONTROL_HIGH 0x888 +#define CHANNEL3CONTROL 0x84C +#define CHANNEL3CONTROL_HIGH 0x88C + +#define DMA_CHANNEL0_CONTROL CHANNEL0CONTROL /*0x8401 */ +#define DMA_CHANNEL0_CONTROL_HIGH CHANNEL0CONTROL_HIGH /*0x8801 */ +#define DMA_CHANNEL1_CONTROL CHANNEL1CONTROL /* 0x8441 */ +#define DMA_CHANNEL1_CONTROL_HIGH CHANNEL1CONTROL_HIGH /*0x8841 */ +#define DMA_CHANNEL2_CONTROL CHANNEL2CONTROL /*0x8481 */ +#define DMA_CHANNEL2_CONTROL_HIGH CHANNEL2CONTROL_HIGH /*0x8881 */ +#define DMA_CHANNEL3_CONTROL CHANNEL3CONTROL /*0x84C1 */ +#define DMA_CHANNEL3_CONTROL_HIGH CHANNEL3CONTROL_HIGH /*0x88C1 */ + + /*#define CHANNEL4CONTROL 0x9401 */ + /*#define CHANNEL4CONTROL_HIGH 0x9801 */ + /*#define CHANNEL5CONTROL 0x9441 */ + /*#define CHANNEL5CONTROL_HIGH 0x9841 */ + /*#define CHANNEL6CONTROL 0x9481 */ + /*#define CHANNEL6CONTROL_HIGH 0x9881 */ + /*#define CHANNEL7CONTROL 0x94C1 */ + /*#define CHANNEL7CONTROL_HIGH 0x98C1 */ + + +/****************************************/ +/* DMA Arbiter */ +/****************************************/ + + /*#define ARBITER_CONTROL_0_3 0x8601 */ +#define ARBITER_CONTROL_4_7 0x960 +/****************************************/ +/* IDMA Registers */ +/****************************************/ + +#define DMA_CHANNEL0_BYTE_COUNT CHANNEL0_DMA_BYTE_COUNT /*0x8001 */ +#define DMA_CHANNEL1_BYTE_COUNT CHANNEL1_DMA_BYTE_COUNT /*0x8041 */ +#define DMA_CHANNEL2_BYTE_COUNT CHANNEL2_DMA_BYTE_COUNT /*0x8081 */ +#define DMA_CHANNEL3_BYTE_COUNT CHANNEL3_DMA_BYTE_COUNT /*0x80C1 */ +#define DMA_CHANNEL0_SOURCE_ADDR CHANNEL0_DMA_SOURCE_ADDRESS /*0x8101 */ +#define DMA_CHANNEL1_SOURCE_ADDR CHANNEL1_DMA_SOURCE_ADDRESS /*0x8141 */ +#define DMA_CHANNEL2_SOURCE_ADDR CHANNEL2_DMA_SOURCE_ADDRESS /*0x8181 */ +#define DMA_CHANNEL3_SOURCE_ADDR CHANNEL3_DMA_SOURCE_ADDRESS /*0x81c1 */ +#define DMA_CHANNEL0_DESTINATION_ADDR CHANNEL0_DMA_DESTINATION_ADDRESS /*0x8201 */ +#define DMA_CHANNEL1_DESTINATION_ADDR CHANNEL1_DMA_DESTINATION_ADDRESS /*0x8241 */ +#define DMA_CHANNEL2_DESTINATION_ADDR CHANNEL2_DMA_DESTINATION_ADDRESS /*0x8281 */ +#define DMA_CHANNEL3_DESTINATION_ADDR CHANNEL3_DMA_DESTINATION_ADDRESS /*0x82C1 */ +#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER CHANNEL0NEXT_RECORD_POINTER /*0x8301 */ +#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER CHANNEL1NEXT_RECORD_POINTER /*0x8341 */ +#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER CHANNEL2NEXT_RECORD_POINTER /*0x8381 */ +#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER CHANNEL3NEXT_RECORD_POINTER /*0x83C1 */ +#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER CHANNEL0CURRENT_DESCRIPTOR_POINTER /*0x8701 */ +#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER CHANNEL1CURRENT_DESCRIPTOR_POINTER /*0x8741 */ +#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER CHANNEL2CURRENT_DESCRIPTOR_POINTER /*0x8781 */ +#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER CHANNEL3CURRENT_DESCRIPTOR_POINTER /*0x87C1 */ + +#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C +#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 +#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 +#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 +#define CHANNEL0NEXT_RECORD_POINTER 0x830 +#define CHANNEL1NEXT_RECORD_POINTER 0x834 +#define CHANNEL2NEXT_RECORD_POINTER 0x838 +#define CHANNEL3NEXT_RECORD_POINTER 0x83C +#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 +#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 +#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 +#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C +#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 +#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 +#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 +#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C +#define CHANNEL0_DMA_BYTE_COUNT 0x800 +#define CHANNEL1_DMA_BYTE_COUNT 0x804 +#define CHANNEL2_DMA_BYTE_COUNT 0x808 +#define CHANNEL3_DMA_BYTE_COUNT 0x80C + + /* IDMA Address Decoding Base Address Registers */ + +#define DMA_BASE_ADDR_REG0 0xa00 +#define DMA_BASE_ADDR_REG1 0xa08 +#define DMA_BASE_ADDR_REG2 0xa10 +#define DMA_BASE_ADDR_REG3 0xa18 +#define DMA_BASE_ADDR_REG4 0xa20 +#define DMA_BASE_ADDR_REG5 0xa28 +#define DMA_BASE_ADDR_REG6 0xa30 +#define DMA_BASE_ADDR_REG7 0xa38 + + /* IDMA Address Decoding Size Address Register */ + +#define DMA_SIZE_REG0 0xa04 +#define DMA_SIZE_REG1 0xa0c +#define DMA_SIZE_REG2 0xa14 +#define DMA_SIZE_REG3 0xa1c +#define DMA_SIZE_REG4 0xa24 +#define DMA_SIZE_REG5 0xa2c +#define DMA_SIZE_REG6 0xa34 +#define DMA_SIZE_REG7 0xa3C + + /* IDMA Address Decoding High Address Remap and Access + Protection Registers */ + +#define DMA_HIGH_ADDR_REMAP_REG0 0xa60 +#define DMA_HIGH_ADDR_REMAP_REG1 0xa64 +#define DMA_HIGH_ADDR_REMAP_REG2 0xa68 +#define DMA_HIGH_ADDR_REMAP_REG3 0xa6C +#define DMA_BASE_ADDR_ENABLE_REG 0xa80 +#define DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 +#define DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 +#define DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 +#define DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c +#define DMA_ARBITER_CONTROL 0x860 +#define DMA_CROSS_BAR_TIMEOUT 0x8d0 + + /* IDMA Headers Retarget Registers */ + + /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e01 */ + /*#define CPU_IDMA_HEADERS_RETARGET_BASE 0x3e81 */ + +#define DMA_HEADERS_RETARGET_CONTROL 0xa84 +#define DMA_HEADERS_RETARGET_BASE 0xa88 + +/****************************************/ +/* DMA Interrupt */ +/****************************************/ + +#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 +#define CHANELS0_3_INTERRUPT_MASK 0x8c4 +#define CHANELS0_3_ERROR_ADDRESS 0x8c8 +#define CHANELS0_3_ERROR_SELECT 0x8cc + /*#define CHANELS4_7_INTERRUPT_CAUSE 0x9c01 */ + /*#define CHANELS4_7_INTERRUPT_MASK 0x9c41 */ + /*#define CHANELS4_7_ERROR_ADDRESS 0x9c81 */ + /*#define CHANELS4_7_ERROR_SELECT 0x9cc1 */ + +#define DMA_INTERRUPT_CAUSE_REG CHANELS0_3_INTERRUPT_CAUSE /*0x8c01 */ +#define DMA_INTERRUPT_CAUSE_MASK CHANELS0_3_INTERRUPT_MASK /*0x8c41 */ +#define DMA_ERROR_ADDR CHANELS0_3_ERROR_ADDRESS /*0x8c81 */ +#define DMA_ERROR_SELECT CHANELS0_3_ERROR_SELECT /*0x8cc1 */ + + +/****************************************/ +/* DMA Debug (for internal use) */ +/****************************************/ + +#define DMA_X0_ADDRESS 0x8e0 +#define DMA_X0_COMMAND_AND_ID 0x8e4 + /*#define DMA_X0_WRITE_DATA_LOW 0x8e81 */ + /*#define DMA_X0_WRITE_DATA_HIGH 0x8ec1 */ + /*#define DMA_X0_WRITE_BYTE_ENABLE 0x8f81 */ + /*#define DMA_X0_READ_DATA_LOW 0x8f01 */ + /*#define DMA_X0_READ_DATA_HIGH 0x8f41 */ + /*#define DMA_X0_READ_ID 0x8fc1 */ + /*#define DMA_X1_ADDRESS 0x9e01 */ + /*#define DMA_X1_COMMAND_AND_ID 0x9e41 */ + /*#define DMA_X1_WRITE_DATA_LOW 0x9e81 */ + /*#define DMA_X1_WRITE_DATA_HIGH 0x9ec1 */ + /*#define DMA_X1_WRITE_BYTE_ENABLE 0x9f81 */ + /*#define DMA_X1_READ_DATA_LOW 0x9f01 */ + /*#define DMA_X1_READ_DATA_HIGH 0x9f41 */ + /*#define DMA_X1_READ_ID 0x9fc1 */ + + /* IDMA Debug Register ( for internal use ) */ + +#define DMA_DEBUG_LOW DMA_X0_ADDRESS /* 0x8e01 */ +#define DMA_DEBUG_HIGH DMA_X0_COMMAND_AND_ID /*0x8e41 */ +#define DMA_SPARE 0xA8C + + +/****************************************/ +/* Timer_Counter */ +/****************************************/ + +#define TIMER_COUNTER0 0x850 +#define TIMER_COUNTER1 0x854 +#define TIMER_COUNTER2 0x858 +#define TIMER_COUNTER3 0x85C +#define TIMER_COUNTER_0_3_CONTROL 0x864 +#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 +#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c + /*#define TIMER_COUNTER4 0x9501 */ + /*#define TIMER_COUNTER5 0x9541 */ + /*#define TIMER_COUNTER6 0x9581 */ + /*#define TIMER_COUNTER7 0x95C1 */ + /*#define TIMER_COUNTER_4_7_CONTROL 0x9641 */ + /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x9681 */ + /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c1 */ + +/****************************************/ +/* PCI Slave Address Decoding */ +/****************************************/ +/****************************************/ +/* PCI Slave Address Decoding registers */ +/****************************************/ +#define PCI_0_CS_0_BANK_SIZE PCI_0SCS_0_BANK_SIZE /*0xc081 */ +#define PCI_1_CS_0_BANK_SIZE PCI_1SCS_0_BANK_SIZE /* 0xc881 */ +#define PCI_0_CS_1_BANK_SIZE PCI_0SCS_1_BANK_SIZE /*0xd081 */ +#define PCI_1_CS_1_BANK_SIZE PCI_1SCS_1_BANK_SIZE /* 0xd881 */ +#define PCI_0_CS_2_BANK_SIZE PCI_0SCS_2_BANK_SIZE /*0xc0c1 */ +#define PCI_1_CS_2_BANK_SIZE PCI_1SCS_2_BANK_SIZE /*0xc8c1 */ +#define PCI_0_CS_3_BANK_SIZE PCI_0SCS_3_BANK_SIZE /*0xd0c1 */ +#define PCI_1_CS_3_BANK_SIZE PCI_1SCS_3_BANK_SIZE /*0xd8c1 */ +#define PCI_0_DEVCS_0_BANK_SIZE PCI_0CS_0_BANK_SIZE /*0xc101 */ +#define PCI_1_DEVCS_0_BANK_SIZE PCI_1CS_0_BANK_SIZE /*0xc901 */ +#define PCI_0_DEVCS_1_BANK_SIZE PCI_0CS_1_BANK_SIZE /*0xd101 */ +#define PCI_1_DEVCS_1_BANK_SIZE PCI_1CS_1_BANK_SIZE /* 0xd901 */ +#define PCI_0_DEVCS_2_BANK_SIZE PCI_0CS_2_BANK_SIZE /* 0xd181 */ +#define PCI_1_DEVCS_2_BANK_SIZE PCI_1CS_2_BANK_SIZE /*0xd981 */ +#define PCI_0_DEVCS_3_BANK_SIZE PCI_0CS_3_BANK_SIZE /* 0xc141 */ +#define PCI_1_DEVCS_3_BANK_SIZE PCI_1CS_3_BANK_SIZE /*0xc941 */ +#define PCI_0_DEVCS_BOOT_BANK_SIZE PCI_0CS_BOOT_BANK_SIZE /*0xd141 */ +#define PCI_1_DEVCS_BOOT_BANK_SIZE PCI_1CS_BOOT_BANK_SIZE /* 0xd941 */ +#define PCI_0_P2P_MEM0_BAR_SIZE PCI_0P2P_MEM0_BAR_SIZE /*0xd1c1 */ +#define PCI_1_P2P_MEM0_BAR_SIZE PCI_1P2P_MEM0_BAR_SIZE /*0xd9c1 */ +#define PCI_0_P2P_MEM1_BAR_SIZE PCI_0P2P_MEM1_BAR_SIZE /*0xd201 */ +#define PCI_1_P2P_MEM1_BAR_SIZE PCI_1P2P_MEM1_BAR_SIZE /*0xda01 */ +#define PCI_0_P2P_I_O_BAR_SIZE PCI_0P2P_I_O_BAR_SIZE /*0xd241 */ +#define PCI_1_P2P_I_O_BAR_SIZE PCI_1P2P_I_O_BAR_SIZE /*0xda41 */ +#define PCI_0_CPU_BAR_SIZE PCI_0CPU_BAR_SIZE /*0xd281 */ +#define PCI_1_CPU_BAR_SIZE PCI_1CPU_BAR_SIZE /*0xda81 */ +#define PCI_0_INTERNAL_SRAM_BAR_SIZE PCI_0DAC_SCS_0_BANK_SIZE /*0xe001 */ +#define PCI_1_INTERNAL_SRAM_BAR_SIZE PCI_1DAC_SCS_0_BANK_SIZE /*0xe801 */ +#define PCI_0_EXPANSION_ROM_BAR_SIZE PCI_0EXPANSION_ROM_BAR_SIZE /*0xd2c1 */ +#define PCI_1_EXPANSION_ROM_BAR_SIZE PCI_1EXPANSION_ROM_BAR_SIZE /*0xd9c1 */ +#define PCI_0_BASE_ADDR_REG_ENABLE PCI_0BASE_ADDRESS_REGISTERS_ENABLE /*0xc3c1 */ +#define PCI_1_BASE_ADDR_REG_ENABLE PCI_1BASE_ADDRESS_REGISTERS_ENABLE /*0xcbc1 */ +#define PCI_0_CS_0_BASE_ADDR_REMAP PCI_0SCS_0_BASE_ADDRESS_REMAP /*0xc481 */ +#define PCI_1_CS_0_BASE_ADDR_REMAP PCI_1SCS_0_BASE_ADDRESS_REMAP /*0xcc81 */ +#define PCI_0_CS_1_BASE_ADDR_REMAP PCI_0SCS_1_BASE_ADDRESS_REMAP /*0xd481 */ +#define PCI_1_CS_1_BASE_ADDR_REMAP PCI_1SCS_1_BASE_ADDRESS_REMAP /*0xdc81 */ +#define PCI_0_CS_2_BASE_ADDR_REMAP PCI_0SCS_2_BASE_ADDRESS_REMAP /*0xc4c1 */ +#define PCI_1_CS_2_BASE_ADDR_REMAP PCI_1SCS_2_BASE_ADDRESS_REMAP /*0xccc1 */ +#define PCI_0_CS_3_BASE_ADDR_REMAP PCI_0SCS_3_BASE_ADDRESS_REMAP /*0xd4c1 */ +#define PCI_1_CS_3_BASE_ADDR_REMAP PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */ +#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP +#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP +#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP +#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP +#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP +#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP +#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP +#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP +#define PCI_0_DEVCS_0_BASE_ADDR_REMAP PCI_0CS_0_BASE_ADDRESS_REMAP /*0xc501 */ +#define PCI_1_DEVCS_0_BASE_ADDR_REMAP PCI_1CS_0_BASE_ADDRESS_REMAP /*0xcd01 */ +#define PCI_0_DEVCS_1_BASE_ADDR_REMAP PCI_0CS_1_BASE_ADDRESS_REMAP /*0xd501 */ +#define PCI_1_DEVCS_1_BASE_ADDR_REMAP PCI_1CS_1_BASE_ADDRESS_REMAP /*0xdd01 */ +#define PCI_0_DEVCS_2_BASE_ADDR_REMAP PCI_0CS_2_BASE_ADDRESS_REMAP /*0xd581 */ +#define PCI_1_DEVCS_2_BASE_ADDR_REMAP PCI_1CS_2_BASE_ADDRESS_REMAP /*0xdd81 */ +#define PCI_0_DEVCS_3_BASE_ADDR_REMAP PCI_0CS_3_BASE_ADDRESS_REMAP /*0xc541 */ +#define PCI_1_DEVCS_3_BASE_ADDR_REMAP PCI_1CS_3_BASE_ADDRESS_REMAP /*0xcd41 */ +#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP /*0xd541 */ +#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP /*0xdd41 */ +#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xd5c1 */ +#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xddc1 */ +#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xd601 */ +#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xde01 */ +#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xd641 */ +#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xde41 */ +#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xd681 */ +#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xde81 */ +#define PCI_0_P2P_I_O_BASE_ADDR_REMAP PCI_0P2P_I_O_BASE_ADDRESS_REMAP /*0xd6c1 */ +#define PCI_1_P2P_I_O_BASE_ADDR_REMAP PCI_1P2P_I_O_BASE_ADDRESS_REMAP /*0xdec 1 */ +#define PCI_0_CPU_BASE_ADDR_REMAP_LOW PCI_0CPU_BASE_ADDRESS_REMAP /*0xd701 */ +#define PCI_1_CPU_BASE_ADDR_REMAP_LOW PCI_1CPU_BASE_ADDRESS_REMAP /*0xdf01 */ +#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 +#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 +#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP /*0xf001 */ +#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 +#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xf381 */ +#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xfb81 */ +#define PCI_0_ADDR_DECODE_CONTROL PCI_0ADDRESS_DECODE_CONTROL /*0xd3c1 */ +#define PCI_1_ADDR_DECODE_CONTROL PCI_1ADDRESS_DECODE_CONTROL /*0xdbc1 */ +#define PCI_0_HEADERS_RETARGET_CONTROL 0xF40 +#define PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 +#define PCI_0_HEADERS_RETARGET_BASE 0xF44 +#define PCI_1_HEADERS_RETARGET_BASE 0xFc4 +#define PCI_0_HEADERS_RETARGET_HIGH 0xF48 +#define PCI_1_HEADERS_RETARGET_HIGH 0xFc8 + +#define PCI_0SCS_0_BANK_SIZE 0xc08 +#define PCI_1SCS_0_BANK_SIZE 0xc88 +#define PCI_0SCS_1_BANK_SIZE 0xd08 +#define PCI_1SCS_1_BANK_SIZE 0xd88 +#define PCI_0SCS_2_BANK_SIZE 0xc0c +#define PCI_1SCS_2_BANK_SIZE 0xc8c +#define PCI_0SCS_3_BANK_SIZE 0xd0c +#define PCI_1SCS_3_BANK_SIZE 0xd8c +#define PCI_0CS_0_BANK_SIZE 0xc10 +#define PCI_1CS_0_BANK_SIZE 0xc90 +#define PCI_0CS_1_BANK_SIZE 0xd10 +#define PCI_1CS_1_BANK_SIZE 0xd90 +#define PCI_0CS_2_BANK_SIZE 0xd18 +#define PCI_1CS_2_BANK_SIZE 0xd98 +#define PCI_0CS_3_BANK_SIZE 0xc14 +#define PCI_1CS_3_BANK_SIZE 0xc94 +#define PCI_0CS_BOOT_BANK_SIZE 0xd14 +#define PCI_1CS_BOOT_BANK_SIZE 0xd94 +#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c +#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c +#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 +#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 +#define PCI_0P2P_I_O_BAR_SIZE 0xd24 +#define PCI_1P2P_I_O_BAR_SIZE 0xda4 +#define PCI_0CPU_BAR_SIZE 0xd28 +#define PCI_1CPU_BAR_SIZE 0xda8 +#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 +#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 +#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 +#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 +#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 +#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 +#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c +#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c +#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 +#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 +#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 +#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 +#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 +#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 +#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c +#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c +#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 +#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 + +#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 +#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 +#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 +#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 +#define PCI_0DAC_CPU_BAR_SIZE 0xe2c +#define PCI_1DAC_CPU_BAR_SIZE 0xeac +#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c +#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac +#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c +#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc +#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 +#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 +#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 +#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 +#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c +#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc +#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c +#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc +#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 +#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 +#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 +#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 +#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 +#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 +#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 +#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 +#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 +#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 +#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c +#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc +#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 +#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 +#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 +#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 +#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 +#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 +#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c +#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec +#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 +#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 +#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 +#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 +#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 +#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 +#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 +#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 +#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c +#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c +#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 +#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 +#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 +#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 +#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 +#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 +#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c +#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c +#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 +#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 +#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 +#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 +#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 +#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 +#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c +#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac +#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 +#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 +#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 +#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 +#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 +#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 +#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c +#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc + +/****************************************/ +/* PCI Control */ +/****************************************/ + +#define PCI_0COMMAND 0xc00 +#define PCI_1COMMAND 0xc80 +#define PCI_0MODE 0xd00 +#define PCI_1MODE 0xd80 +#define PCI_0TIMEOUT_RETRY 0xc04 +#define PCI_1TIMEOUT_RETRY 0xc84 +#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 +#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 +#define MSI_0TRIGGER_TIMER 0xc38 +#define MSI_1TRIGGER_TIMER 0xcb8 +#define PCI_0ARBITER_CONTROL 0x1d00 +#define PCI_1ARBITER_CONTROL 0x1d80 +/* changing untill here */ +#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 +#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c +#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 +#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 +#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c +#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 +#define PCI_0P2P_CONFIGURATION 0x1d14 +#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 +#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 +#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 +#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10 +#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 +#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 +#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20 +#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 +#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 +#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30 +#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 +#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 +#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40 +#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 +#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 +#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50 +#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 +#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 +#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60 +#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 +#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 +#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70 +#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 +#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 +#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 +#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c +#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 +#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 +#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c +#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 +#define PCI_1P2P_CONFIGURATION 0x1d94 +#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 +#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 +#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 +#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90 +#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 +#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 +#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0 +#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 +#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 +#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0 +#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 +#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 +#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0 +#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 +#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 +#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0 +#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 +#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 +#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0 +#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 +#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 +#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0 +#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 +#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 + +/****************************************/ +/* PCI Snoop Control */ +/****************************************/ + +#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 +#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 +#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 +#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 +#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 +#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 +#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 +#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 +#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 +#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 +#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 +#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 +#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 +#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 +#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 +#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 +#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 +#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 +#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 +#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 +#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 +#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 +#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 +#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 + +/****************************************/ +/* PCI Configuration Address */ +/****************************************/ + +#define PCI_0CONFIGURATION_ADDRESS 0xcf8 +#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc +#define PCI_1CONFIGURATION_ADDRESS 0xc78 +#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c +#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 +#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 + +/****************************************/ +/* PCI Error Report */ +/****************************************/ + +#define PCI_0SERR_MASK 0xc28 +#define PCI_0ERROR_ADDRESS_LOW 0x1d40 +#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 +#define PCI_0ERROR_DATA_LOW 0x1d48 +#define PCI_0ERROR_DATA_HIGH 0x1d4c +#define PCI_0ERROR_COMMAND 0x1d50 +#define PCI_0ERROR_CAUSE 0x1d58 +#define PCI_0ERROR_MASK 0x1d5c +#define PCI_1SERR_MASK 0xca8 +#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 +#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 +#define PCI_1ERROR_DATA_LOW 0x1dc8 +#define PCI_1ERROR_DATA_HIGH 0x1dcc +#define PCI_1ERROR_COMMAND 0x1dd0 +#define PCI_1ERROR_CAUSE 0x1dd8 +#define PCI_1ERROR_MASK 0x1ddc + + +/****************************************/ +/* Lslave Debug (for internal use) */ +/****************************************/ + +#define L_SLAVE_X0_ADDRESS 0x1d20 +#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 +#define L_SLAVE_X1_ADDRESS 0x1d28 +#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c +#define L_SLAVE_WRITE_DATA_LOW 0x1d30 +#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 +#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 +#define L_SLAVE_READ_DATA_LOW 0x1d38 +#define L_SLAVE_READ_DATA_HIGH 0x1d3c +#define L_SLAVE_READ_ID 0x1d64 + +/****************************************/ +/* PCI Configuration Function 0 */ +/****************************************/ + +#define PCI_DEVICE_AND_VENDOR_ID 0x000 +#define PCI_STATUS_AND_COMMAND 0x004 +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C +#define PCI_SCS_0_BASE_ADDRESS 0x010 +#define PCI_SCS_1_BASE_ADDRESS 0x014 +#define PCI_SCS_2_BASE_ADDRESS 0x018 +#define PCI_SCS_3_BASE_ADDRESS 0x01C +#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 +#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 +#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C +#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 +#define PCI_CAPABILTY_LIST_POINTER 0x034 +#define PCI_INTERRUPT_PIN_AND_LINE 0x03C +#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define PCI_VPD_ADDRESS 0x048 +#define PCI_VPD_DATA 0x04c +#define PCI_MSI_MESSAGE_CONTROL 0x050 +#define PCI_MSI_MESSAGE_ADDRESS 0x054 +#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 +#define PCI_MSI_MESSAGE_DATA 0x05c +#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 + +/****************************************/ +/* PCI Configuration Function 1 */ +/****************************************/ + +#define PCI_CS_0_BASE_ADDRESS 0x110 +#define PCI_CS_1_BASE_ADDRESS 0x114 +#define PCI_CS_2_BASE_ADDRESS 0x118 +#define PCI_CS_3_BASE_ADDRESS 0x11c +#define PCI_BOOTCS_BASE_ADDRESS 0x120 + +/****************************************/ +/* PCI Configuration Function 2 */ +/****************************************/ + +#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 + /*#define PCI_P2P_MEM1_BASE_ADDRESS 0x2141 */ +#define PCI_P2P_I_O_BASE_ADDRESS 0x218 + /*#define PCI_CPU_BASE_ADDRESS 0x21c1 */ + +/****************************************/ +/* PCI Configuration Function 4 */ +/****************************************/ + +#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 +#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 +#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 +#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 + + +/****************************************/ +/* PCI Configuration Function 5 */ +/****************************************/ + +#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 +#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 +#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 +#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 + + +/****************************************/ +/* PCI Configuration Function 6 */ +/****************************************/ + +#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 +#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 +#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 +#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c +#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 +#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 + +/****************************************/ +/* PCI Configuration Function 7 */ +/****************************************/ + +#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 +#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c +#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 +#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 + +/****************************** MV64360 and MV64460 PCI ***************************/ +/***********************************/ +/* PCI Control Register Map */ +/***********************************/ + +#define PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 +#define PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 +#define PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C +#define PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C +#define PCI_0_COMMAND 0xc00 +#define PCI_1_COMMAND 0xc80 +#define PCI_0_MODE 0xd00 +#define PCI_1_MODE 0xd80 +#define PCI_0_RETRY 0xc04 +#define PCI_1_RETRY 0xc84 +#define PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 +#define PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 +#define PCI_0_MSI_TRIGGER_TIMER 0xc38 +#define PCI_1_MSI_TRIGGER_TIMER 0xcb8 +#define PCI_0_ARBITER_CONTROL 0x1d00 +#define PCI_1_ARBITER_CONTROL 0x1d80 +#define PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 +#define PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 +#define PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c +#define PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c +#define PCI_0_CROSS_BAR_TIMEOUT 0x1d04 +#define PCI_1_CROSS_BAR_TIMEOUT 0x1d84 +#define PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 +#define PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 +#define PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 +#define PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 +#define PCI_0_P2P_CONFIG 0x1d14 +#define PCI_1_P2P_CONFIG 0x1d94 + +#define PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 +#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 +#define PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 +#define PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 +#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 +#define PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 +#define PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 +#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 +#define PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 +#define PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 +#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 +#define PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 +#define PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 +#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 +#define PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 +#define PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 +#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 +#define PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 + +#define PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 +#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 +#define PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 +#define PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 +#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 +#define PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 +#define PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 +#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 +#define PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 +#define PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 +#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 +#define PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 +#define PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 +#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 +#define PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 +#define PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 +#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 +#define PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 + +/****************************************/ +/* PCI Configuration Access Registers */ +/****************************************/ + +#define PCI_0_CONFIG_ADDR 0xcf8 +#define PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc +#define PCI_1_CONFIG_ADDR 0xc78 +#define PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c +#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 +#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 + +/****************************************/ +/* PCI Error Report Registers */ +/****************************************/ + +#define PCI_0_SERR_MASK 0xc28 +#define PCI_1_SERR_MASK 0xca8 +#define PCI_0_ERROR_ADDR_LOW 0x1d40 +#define PCI_1_ERROR_ADDR_LOW 0x1dc0 +#define PCI_0_ERROR_ADDR_HIGH 0x1d44 +#define PCI_1_ERROR_ADDR_HIGH 0x1dc4 +#define PCI_0_ERROR_ATTRIBUTE 0x1d48 +#define PCI_1_ERROR_ATTRIBUTE 0x1dc8 +#define PCI_0_ERROR_COMMAND 0x1d50 +#define PCI_1_ERROR_COMMAND 0x1dd0 +#define PCI_0_ERROR_CAUSE 0x1d58 +#define PCI_1_ERROR_CAUSE 0x1dd8 +#define PCI_0_ERROR_MASK 0x1d5c +#define PCI_1_ERROR_MASK 0x1ddc + +/****************************************/ +/* PCI Debug Registers */ +/****************************************/ + +#define PCI_0_MMASK 0X1D24 +#define PCI_1_MMASK 0X1DA4 + +/*********************************************/ +/* PCI Configuration, Function 0, Registers */ +/*********************************************/ + +#define PCI_DEVICE_AND_VENDOR_ID 0x000 +#define PCI_STATUS_AND_COMMAND 0x004 +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C + +#define PCI_SCS_0_BASE_ADDR_LOW 0x010 +#define PCI_SCS_0_BASE_ADDR_HIGH 0x014 +#define PCI_SCS_1_BASE_ADDR_LOW 0x018 +#define PCI_SCS_1_BASE_ADDR_HIGH 0x01C +#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 +#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 + /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c1 */ +#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define PCI_CAPABILTY_LIST_POINTER 0x034 +#define PCI_INTERRUPT_PIN_AND_LINE 0x03C + /* capability list */ +#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define PCI_VPD_ADDR 0x048 +#define PCI_VPD_DATA 0x04c +#define PCI_MSI_MESSAGE_CONTROL 0x050 +#define PCI_MSI_MESSAGE_ADDR 0x054 +#define PCI_MSI_MESSAGE_UPPER_ADDR 0x058 +#define PCI_MSI_MESSAGE_DATA 0x05c +#define PCI_X_COMMAND 0x060 +#define PCI_X_STATUS 0x064 +#define PCI_COMPACT_PCI_HOT_SWAP 0x068 + +/***********************************************/ +/* PCI Configuration, Function 1, Registers */ +/***********************************************/ + +#define PCI_SCS_2_BASE_ADDR_LOW 0x110 +#define PCI_SCS_2_BASE_ADDR_HIGH 0x114 +#define PCI_SCS_3_BASE_ADDR_LOW 0x118 +#define PCI_SCS_3_BASE_ADDR_HIGH 0x11c +#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 +#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 + +/***********************************************/ +/* PCI Configuration, Function 2, Registers */ +/***********************************************/ + +#define PCI_DEVCS_0_BASE_ADDR_LOW 0x210 +#define PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 +#define PCI_DEVCS_1_BASE_ADDR_LOW 0x218 +#define PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c +#define PCI_DEVCS_2_BASE_ADDR_LOW 0x220 +#define PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 3, Registers */ +/***********************************************/ + +#define PCI_DEVCS_3_BASE_ADDR_LOW 0x310 +#define PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 +#define PCI_BOOT_CS_BASE_ADDR_LOW 0x318 +#define PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c +#define PCI_CPU_BASE_ADDR_LOW 0x220 +#define PCI_CPU_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 4, Registers */ +/***********************************************/ + +#define PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 +#define PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 +#define PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 +#define PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c +#define PCI_P2P_I_O_BASE_ADDR 0x420 +#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 + +/****************************** MV64360 and MV64460 PCI End ***************************/ +/****************************************/ +/* I20 Support registers */ +/****************************************/ + +#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 +#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 +#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 +#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C +#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 +#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 +#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 +#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 +#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 +#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 +#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C + +#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10 +#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14 +#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18 +#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C +#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24 +#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28 +#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44 +#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50 +#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64 +#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68 +#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C + + +/****************************************/ +/* Messaging Unit Registers (I20) */ +/****************************************/ + +#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 +#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 +#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 +#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C +#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 +#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 +#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 +#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C +#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 +#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 +#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 +#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 +#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 +#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 +#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 +#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 +#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 +#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C +#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 +#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 +#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 +#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC + +#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 +#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 +#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 +#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C +#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 +#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 +#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 +#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC +#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 +#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 +#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 +#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 +#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 +#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 +#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 +#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 +#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 +#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC +#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 +#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 +#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 +#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C + +#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 +#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 +#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 +#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C +#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 +#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 +#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 +#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C +#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 +#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 +#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 +#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 +#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 +#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 +#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 +#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 +#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 +#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C +#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 +#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 +#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 +#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC +#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 +#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 +#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 +#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C +#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 +#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 +#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 +#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC +#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 +#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 +#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 +#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 +#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 +#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 +#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 +#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 +#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 +#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC +#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 +#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 +#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 +#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C + + +/****************************************/ +/* Communication Unit Registers */ +/****************************************/ +/* +#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200 +#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 +#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 +#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c +#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 +#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 +#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 +#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 +#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 +#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 +#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c +#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 +#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 +#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 +#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 +#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 +#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 +#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c +#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 +#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 +#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 + */ +#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 +#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 +#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 +#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c +#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 +#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 +#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0 +#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4 +#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 +#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc +#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 +#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 + /*#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf3201 */ +#define COMM_UNIT_ARBITER_CONTROL 0xf300 +#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 +#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 +#define COMM_UNIT_INTERRUPT_MASK 0xf314 +#define COMM_UNIT_ERROR_ADDRESS 0xf314 +/****************************************/ +/* Serial Initialization registers */ +/****************************************/ + + /*#define SERIAL_INIT_LAST_DATA 0xf3241 */ + /*#define SERIAL_INIT_STATUS_AND_CONTROL 0xf3281 */ +#define SERIAL_INIT_LAST_DATA 0xf324 +#define SERIAL_INIT_CONTROL 0xf328 +#define SERIAL_INIT_STATUS 0xf32c + + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ + +#define ETH_PHY_ADDR_REG 0x2000 +#define ETH_SMI_REG 0x2004 +#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008 +#define ETH_UNIT_DEFAULTID_REG 0x200c +#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 +#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084 +#define ETH_UNIT_INTERNAL_USE_REG 0x24fc +#define ETH_UNIT_ERROR_ADDR_REG 0x2094 +#define ETH_BAR_0 0x2200 +#define ETH_BAR_1 0x2208 +#define ETH_BAR_2 0x2210 +#define ETH_BAR_3 0x2218 +#define ETH_BAR_4 0x2220 +#define ETH_BAR_5 0x2228 +#define ETH_SIZE_REG_0 0x2204 +#define ETH_SIZE_REG_1 0x220c +#define ETH_SIZE_REG_2 0x2214 +#define ETH_SIZE_REG_3 0x221c +#define ETH_SIZE_REG_4 0x2224 +#define ETH_SIZE_REG_5 0x222c +#define ETH_HEADERS_RETARGET_BASE_REG 0x2230 +#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 +#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280 +#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284 +#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288 +#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c +#define ETH_BASE_ADDR_ENABLE_REG 0x2290 +#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) +#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) +#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) +#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) +#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) +#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) +#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) +#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) +#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) +#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) +#define ETH_DSCP_0(port) (0x2420 + (port<<10)) +#define ETH_DSCP_1(port) (0x2424 + (port<<10)) +#define ETH_DSCP_2(port) (0x2428 + (port<<10)) +#define ETH_DSCP_3(port) (0x242c + (port<<10)) +#define ETH_DSCP_4(port) (0x2430 + (port<<10)) +#define ETH_DSCP_5(port) (0x2434 + (port<<10)) +#define ETH_DSCP_6(port) (0x2438 + (port<<10)) +#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) +#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) +#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) +#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) +#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) +#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) +#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) +#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) +#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) +#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) +#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) +#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) +#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) +#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) +#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) +#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) +#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) +#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) +#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) +#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) +#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) +#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) +#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) +#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) +#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) +#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) +#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) +#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) +#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) +#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) +#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) +#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) +#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) +#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) +#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) +#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) +#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) +#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) +#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) +#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) +#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) +#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) +#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) +#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) +#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) +#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) +#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) +#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) +#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) +#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) + +/****************************************/ +/* Cunit Debug (for internal use) */ +/****************************************/ + +#define CUNIT_ADDRESS 0xf340 +#define CUNIT_COMMAND_AND_ID 0xf344 +#define CUNIT_WRITE_DATA_LOW 0xf348 +#define CUNIT_WRITE_DATA_HIGH 0xf34c +#define CUNIT_WRITE_BYTE_ENABLE 0xf358 +#define CUNIT_READ_DATA_LOW 0xf350 +#define CUNIT_READ_DATA_HIGH 0xf354 +#define CUNIT_READ_ID 0xf35c + +/****************************************/ +/* Fast Ethernet Unit Registers */ +/****************************************/ + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ + +#define ETH_PHY_ADDR_REG 0x2000 +#define ETH_SMI_REG 0x2004 +#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008 +#define ETH_UNIT_DEFAULTID_REG 0x200c +#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 +#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084 +#define ETH_UNIT_INTERNAL_USE_REG 0x24fc +#define ETH_UNIT_ERROR_ADDR_REG 0x2094 +#define ETH_BAR_0 0x2200 +#define ETH_BAR_1 0x2208 +#define ETH_BAR_2 0x2210 +#define ETH_BAR_3 0x2218 +#define ETH_BAR_4 0x2220 +#define ETH_BAR_5 0x2228 +#define ETH_SIZE_REG_0 0x2204 +#define ETH_SIZE_REG_1 0x220c +#define ETH_SIZE_REG_2 0x2214 +#define ETH_SIZE_REG_3 0x221c +#define ETH_SIZE_REG_4 0x2224 +#define ETH_SIZE_REG_5 0x222c +#define ETH_HEADERS_RETARGET_BASE_REG 0x2230 +#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 +#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280 +#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284 +#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288 +#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c +#define ETH_BASE_ADDR_ENABLE_REG 0x2290 +#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) +#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) +#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) +#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) +#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) +#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) +#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) +#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) +#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) +#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) +#define ETH_DSCP_0(port) (0x2420 + (port<<10)) +#define ETH_DSCP_1(port) (0x2424 + (port<<10)) +#define ETH_DSCP_2(port) (0x2428 + (port<<10)) +#define ETH_DSCP_3(port) (0x242c + (port<<10)) +#define ETH_DSCP_4(port) (0x2430 + (port<<10)) +#define ETH_DSCP_5(port) (0x2434 + (port<<10)) +#define ETH_DSCP_6(port) (0x2438 + (port<<10)) +#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) +#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) +#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) +#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) +#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) +#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) +#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) +#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) +#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) +#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) +#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) +#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) +#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) +#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) +#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) +#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) +#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) +#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) +#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) +#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) +#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) +#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) +#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) +#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) +#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) +#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) +#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) +#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) +#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) +#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) +#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) +#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) +#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) +#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) +#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) +#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) +#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) +#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) +#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) +#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) +#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) +#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) +#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) +#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) +#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) +#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) +#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) +#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) +#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) +#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) +#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) +#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) + + +/* Ethernet GT64260 */ +/* +#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 +#define ETHERNET_SMI_REGISTER 0x2010 +*/ +/* Ethernet 0 */ +/* +#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 +#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 +#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 +#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 +#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 +#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 +#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 +#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 +#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 +#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 +#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 +#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac +#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 +#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 +#define ETHERNET0_MIB_COUNTER_BASE 0x2500 +*/ +/* Ethernet 1 */ +/* +#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 +#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 +#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 +#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 +#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 +#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 +#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 +#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 +#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 +#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 +#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 +#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac +#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 +#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 +#define ETHERNET1_MIB_COUNTER_BASE 0x2900 +*/ +/* Ethernet 2 */ +/* +#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 +#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 +#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 +#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 +#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 +#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 +#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 +#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 +#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 +#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 +#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 +#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac +#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 +#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 +#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 +*/ + +/****************************************/ +/* SDMA Registers */ +/****************************************/ + +#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 +#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 +#define CHANNEL0_COMMAND_REGISTER 0x4008 +#define CHANNEL0_RX_CMD_STATUS 0x4800 +#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 +#define CHANNEL0_RX_BUFFER_POINTER 0x4808 +#define CHANNEL0_RX_NEXT_POINTER 0x480c +#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 +#define CHANNEL0_TX_CMD_STATUS 0x4C00 +#define CHANNEL0_TX_PACKET_SIZE 0x4C04 +#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 +#define CHANNEL0_TX_NEXT_POINTER 0x4C0c +#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 +#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 +/* +#define CHANNEL1_CONFIGURATION_REGISTER 0x5000 +#define CHANNEL1_COMMAND_REGISTER 0x5008 +#define CHANNEL1_RX_CMD_STATUS 0x5800 +#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804 +#define CHANNEL1_RX_BUFFER_POINTER 0x5808 +#define CHANNEL1_RX_NEXT_POINTER 0x580c +#define CHANNEL1_TX_CMD_STATUS 0x5C00 +#define CHANNEL1_TX_PACKET_SIZE 0x5C04 +#define CHANNEL1_TX_BUFFER_POINTER 0x5C08 +#define CHANNEL1_TX_NEXT_POINTER 0x5C0c +#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810 +#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10 +#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14 +#define CHANNEL2_CONFIGURATION_REGISTER 0x6000 +#define CHANNEL2_COMMAND_REGISTER 0x6008 +#define CHANNEL2_RX_CMD_STATUS 0x6800 +#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804 +#define CHANNEL2_RX_BUFFER_POINTER 0x6808 +#define CHANNEL2_RX_NEXT_POINTER 0x680c +#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 +#define CHANNEL2_TX_CMD_STATUS 0x6C00 +#define CHANNEL2_TX_PACKET_SIZE 0x6C04 +#define CHANNEL2_TX_BUFFER_POINTER 0x6C08 +#define CHANNEL2_TX_NEXT_POINTER 0x6C0c +#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 +#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 +#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 +*/ +/* SDMA Interrupt */ +/* +#define SDMA_CAUSE 0xb820 +#define SDMA_MASK 0xb8a0 +*/ +/***************************************/ +/* SDMA Registers */ +/***************************************/ + +#define SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) +#define SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) +#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) +#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) +#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) + +#define SDMA_CAUSE_REG 0xb800 +#define SDMA_MASK_REG 0xb880 + +/****************************************/ +/* Baude Rate Generators Registers */ +/****************************************/ + +/* BRG 0 */ +#define BRG0_CONFIGURATION_REGISTER 0xb200 +#define BRG0_BAUDE_TUNING_REGISTER 0xb204 + +/* BRG 1 */ +#define BRG1_CONFIGURATION_REGISTER 0xb208 +#define BRG1_BAUDE_TUNING_REGISTER 0xb20c + +/* BRG 2 */ +#define BRG2_CONFIGURATION_REGISTER 0xb210 +#define BRG2_BAUDE_TUNING_REGISTER 0xb214 + +/* BRG Interrupts */ +#define BRG_CAUSE_REGISTER 0xb834 +#define BRG_MASK_REGISTER 0xb8b4 +#define BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) +#define BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3)) +#define BRG_CAUSE_REG BRG_CAUSE_REGISTER /*0xb8341 */ +#define BRG_MASK_REG BRG_MASK_REGISTER /*0xb8b41 */ + +/* MISC */ + +#define MAIN_ROUTING_REGISTER 0xb400 +#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 +#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 +#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c + +/****************************************/ +/* Watchdog registers */ +/****************************************/ +#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 +#define WATCHDOG_VALUE_REGISTER 0xb414 +#define WATCHDOG_CONFIG_REG WATCHDOG_CONFIGURATION_REGISTER /*0xb4101 */ +#define WATCHDOG_VALUE_REG WATCHDOG_VALUE_REGISTER /*0xb4141 */ + + +/****************************************/ +/* Flex TDM Registers */ +/****************************************/ + +/* FTDM Port */ + +#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 +#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 +#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 +#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c +#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 +#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 +#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 + +/* FTDM Interrupts */ + +#define FTDM_CAUSE_REGISTER 0xb830 +#define FTDM_MASK_REGISTER 0xb8b0 + + +/****************************************/ +/* GPP Interface Registers */ +/****************************************/ + +#define GPP_IO_CONTROL 0xf100 +#define GPP_LEVEL_CONTROL 0xf110 +#define GPP_VALUE 0xf104 +#define GPP_INTERRUPT_CAUSE 0xf108 +#define GPP_INTERRUPT_MASK 0xf10c +#define GPP_INTERRUPT_MASK0 GPP_INTERRUPT_MASK /* 0xf10c1 */ +#define GPP_INTERRUPT_MASK1 0xf114 +#define GPP_VALUE_SET 0xf118 +#define GPP_VALUE_CLEAR 0xf11c + +/****************************************/ +/* MPP Interface Registers */ +/****************************************/ +#define MPP_CONTROL0 0xf000 +#define MPP_CONTROL1 0xf004 +#define MPP_CONTROL2 0xf008 +#define MPP_CONTROL3 0xf00c +#define DEBUG_PORT_MULTIPLEX 0xf014 + /*#define SERIAL_PORT_MULTIPLEX 0xf0101 */ + +/****************************************/ +/* Interrupt Controller Registers */ +/****************************************/ + +/****************************************/ +/* Interrupts */ +/****************************************/ +/****************************************/ +/* Interrupts (checked I.A. 14.10.02) */ +/****************************************/ + +#define LOW_INTERRUPT_CAUSE_REGISTER 0x004 /* gt64260: 0xc181 */ +#define HIGH_INTERRUPT_CAUSE_REGISTER 0x00c /* gt64260: 0xc681 */ +#define CPU_INTERRUPT_MASK_REGISTER_LOW 0x014 /* gt64260: 0xc1c1 */ +#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0x01c /* gt64260: 0xc6c1 */ +#define CPU_SELECT_CAUSE_REGISTER 0x024 /* gt64260: 0xc701 */ +#define CPU_INTERRUPT_1_MASK_REGISTER_LOW 0x034 /* new in the MV64360 and MV64460 */ +#define CPU_INTERRUPT_1_MASK_REGISTER_HIGH 0x03c /* new in the MV64360 and MV64460 */ +#define CPU_SELECT_1_CAUSE_REGISTER 0x044 /* new in the MV64360 and MV64460 */ +#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x054 /* gt64260: 0xc241 */ +#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c /* gt64260: 0xc641 */ +#define PCI_0SELECT_CAUSE 0x064 /* gt64260: 0xc741 */ +#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x074 /* gt64260: 0xca41 */ +#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c /* gt64260: 0xce41 */ +#define PCI_1SELECT_CAUSE 0x084 /* gt64260: 0xcf41 */ +/*#define CPU_INT_0_MASK 0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */ +/*#define CPU_INT_1_MASK 0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */ +/*#define CPU_INT_2_MASK 0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */ +/*#define CPU_INT_3_MASK 0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */ + +#define MAIN_INTERRUPT_CAUSE_LOW LOW_INTERRUPT_CAUSE_REGISTER /* 0x0041 */ +#define MAIN_INTERRUPT_CAUSE_HIGH HIGH_INTERRUPT_CAUSE_REGISTER /* 0x00c1 */ +#define CPU_INTERRUPT0_MASK_LOW CPU_INTERRUPT_MASK_REGISTER_LOW /* 0x0141 */ +#define CPU_INTERRUPT0_MASK_HIGH CPU_INTERRUPT_MASK_REGISTER_HIGH /*0x01c1 */ +#define CPU_INTERRUPT0_SELECT_CAUSE CPU_SELECT_CAUSE_REGISTER /* 0x0241 */ +#define CPU_INTERRUPT1_MASK_LOW CPU_INTERRUPT_1_MASK_REGISTER_LOW /* 0x0341 */ +#define CPU_INTERRUPT1_MASK_HIGH CPU_INTERRUPT_1_MASK_REGISTER_HIGH /* 0x03c1 */ +#define CPU_INTERRUPT1_SELECT_CAUSE CPU_SELECT_1_CAUSE_REGISTER /* 0x0441 */ +#define INTERRUPT0_MASK_0_LOW PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */ +#define INTERRUPT0_MASK_0_HIGH PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x05c1 */ +#define INTERRUPT0_SELECT_CAUSE PCI_0SELECT_CAUSE /* 0x0641 */ +#define INTERRUPT1_MASK_0_LOW PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0741 */ +#define INTERRUPT1_MASK_0_HIGH PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x07c1 */ +#define INTERRUPT1_SELECT_CAUSE PCI_1SELECT_CAUSE /* 0x0841 */ + +/****************************************/ +/* I2C Registers */ +/****************************************/ + +#define I2C_SLAVE_ADDRESS 0xc000 +#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 +#define I2C_DATA 0xc004 +#define I2C_CONTROL 0xc008 +#define I2C_STATUS_BAUDE_RATE 0xc00C +#define I2C_SOFT_RESET 0xc01c +#define I2C_SLAVE_ADDR I2C_SLAVE_ADDRESS /* 0xc0001 */ +#define I2C_EXTENDED_SLAVE_ADDR I2C_EXTENDED_SLAVE_ADDRESS /*0xc0101 */ + +/****************************************/ +/* MPSC Registers */ +/****************************************/ + + /* MPSCs Clocks Routing Registers */ + +#define MPSC_ROUTING_REG 0xb400 +#define MPSC_RX_CLOCK_ROUTING_REG 0xb404 +#define MPSC_TX_CLOCK_ROUTING_REG 0xb408 + + /* MPSCs Interrupts Registers */ + +#define MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) +#define MPSC_MASK_REG(port) (0xb884 + (port<<3)) + +#define MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) +#define MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) +#define MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) +#define MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) +#define MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) +#define MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) +#define MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) +#define MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) +#define MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) +#define MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) +#define MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) +#define MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) +#define MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) + + +/* MPSC0 */ + +#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 +#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 +#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 +#define CHANNEL0_REGISTER1 0x800c +#define CHANNEL0_REGISTER2 0x8010 +#define CHANNEL0_REGISTER3 0x8014 +#define CHANNEL0_REGISTER4 0x8018 +#define CHANNEL0_REGISTER5 0x801c +#define CHANNEL0_REGISTER6 0x8020 +#define CHANNEL0_REGISTER7 0x8024 +#define CHANNEL0_REGISTER8 0x8028 +#define CHANNEL0_REGISTER9 0x802c +#define CHANNEL0_REGISTER10 0x8030 +#define CHANNEL0_REGISTER11 0x8034 + +/* MPSC1 */ + +#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840 +#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844 +#define MPSC1_PROTOCOL_CONFIGURATION 0x8848 +#define CHANNEL1_REGISTER1 0x884c +#define CHANNEL1_REGISTER2 0x8850 +#define CHANNEL1_REGISTER3 0x8854 +#define CHANNEL1_REGISTER4 0x8858 +#define CHANNEL1_REGISTER5 0x885c +#define CHANNEL1_REGISTER6 0x8860 +#define CHANNEL1_REGISTER7 0x8864 +#define CHANNEL1_REGISTER8 0x8868 +#define CHANNEL1_REGISTER9 0x886c +#define CHANNEL1_REGISTER10 0x8870 +#define CHANNEL1_REGISTER11 0x8874 + +/* MPSC2 */ + +#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040 +#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044 +#define MPSC2_PROTOCOL_CONFIGURATION 0x9048 +#define CHANNEL2_REGISTER1 0x904c +#define CHANNEL2_REGISTER2 0x9050 +#define CHANNEL2_REGISTER3 0x9054 +#define CHANNEL2_REGISTER4 0x9058 +#define CHANNEL2_REGISTER5 0x905c +#define CHANNEL2_REGISTER6 0x9060 +#define CHANNEL2_REGISTER7 0x9064 +#define CHANNEL2_REGISTER8 0x9068 +#define CHANNEL2_REGISTER9 0x906c +#define CHANNEL2_REGISTER10 0x9070 +#define CHANNEL2_REGISTER11 0x9074 + +/* MPSCs Interupts */ + +#define MPSC0_CAUSE 0xb824 +#define MPSC0_MASK 0xb8a4 +#define MPSC1_CAUSE 0xb828 +#define MPSC1_MASK 0xb8a8 +#define MPSC2_CAUSE 0xb82c +#define MPSC2_MASK 0xb8ac + +/*******************************************/ +/* CUNIT Registers */ +/*******************************************/ + + /* Address Decoding Register Map */ + +#define CUNIT_BASE_ADDR_REG0 0xf200 +#define CUNIT_BASE_ADDR_REG1 0xf208 +#define CUNIT_BASE_ADDR_REG2 0xf210 +#define CUNIT_BASE_ADDR_REG3 0xf218 +#define CUNIT_SIZE0 0xf204 +#define CUNIT_SIZE1 0xf20c +#define CUNIT_SIZE2 0xf214 +#define CUNIT_SIZE3 0xf21c +#define CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 +#define CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 +#define CUNIT_BASE_ADDR_ENABLE_REG 0xf250 +#define MPSC0_ACCESS_PROTECTION_REG 0xf254 +#define MPSC1_ACCESS_PROTECTION_REG 0xf258 +#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C + + /* Error Report Registers */ + +#define CUNIT_INTERRUPT_CAUSE_REG 0xf310 +#define CUNIT_INTERRUPT_MASK_REG 0xf314 +#define CUNIT_ERROR_ADDR 0xf318 + + /* Cunit Control Registers */ + +#define CUNIT_ARBITER_CONTROL_REG 0xf300 +#define CUNIT_CONFIG_REG 0xb40c +#define CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 + + /* Cunit Debug Registers */ + +#define CUNIT_DEBUG_LOW 0xf340 +#define CUNIT_DEBUG_HIGH 0xf344 +#define CUNIT_MMASK 0xf380 + +#endif /* __INCmv_gen_regh */ diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h new file mode 100644 index 0000000..167248d --- /dev/null +++ b/board/Marvell/include/pci.h @@ -0,0 +1,293 @@ +/* PCI.h - PCI functions header file */ + +/* Copyright - Galileo technology. */ + +#ifndef __INCpcih +#define __INCpcih + +/* includes */ + +#include"core.h" +#include"memory.h" + +/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ +#define PCI_MAX_DEVICES 22 + + +/* Macros */ + +/* The next Macros configurate the initiator board (SELF) or any any agent on + the PCI to become: MASTER, response to MEMORY transactions , response to + IO transactions or TWO both MEMORY_IO transactions. Those configuration + are for both PCI0 and PCI1. */ + +#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ + PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \ + pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) + +#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ + PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \ + pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) + +#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ + PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \ + pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) + +#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \ + PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \ + pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber)) + +#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \ + PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \ + pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) + +#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \ + PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \ + pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) + +#define MASTER_ENABLE BIT2 +#define MEMORY_ENABLE BIT1 +#define I_O_ENABLE BIT0 +#define SELF 32 + +/* Agent on the PCI bus may have up to 6 BARS. */ +#define BAR0 0x10 +#define BAR1 0x14 +#define BAR2 0x18 +#define BAR3 0x1c +#define BAR4 0x20 +#define BAR5 0x24 +#define BAR_SEL_MEM_IO BIT0 +#define BAR_MEM_TYPE_32_BIT NO_BIT +#define BAR_MEM_TYPE_BELOW_1M BIT1 +#define BAR_MEM_TYPE_64_BIT BIT2 +#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2) +#define BAR_MEM_TYPE_MASK (BIT1 | BIT2) +#define BAR_PREFETCHABLE BIT3 +#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3) + +/* Defines for the access regions. */ +#define PREFETCH_ENABLE BIT12 +#define PREFETCH_DISABLE NO_BIT +#define DELAYED_READ_ENABLE BIT13 +/* #define CACHING_ENABLE BIT14 */ +/* aggressive prefetch: PCI slave prefetch two burst in advance*/ +#define AGGRESSIVE_PREFETCH BIT16 +/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/ +#define READ_LINE_AGGRESSIVE_PREFETCH BIT17 +/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/ +#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18 +#define MAX_BURST_4 NO_BIT +#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */ +#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */ +#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */ +#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */ +#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */ +#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */ +#define PCI_ACCESS_PROTECT BIT28 +#define PCI_WRITE_PROTECT BIT29 + +/* typedefs */ + +typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5, + REGION6,REGION7} PCI_ACCESS_REGIONS; + +typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO; +typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK; + +typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} + PCI_SNOOP_TYPE; +typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, + PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} + PCI_SNOOP_REGION; + +typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; +typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, + PCI_REGION2,PCI_REGION3, + PCI_IO} + PCI_REGION; + +/*ronen 7/Dec/03 */ +typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR, + PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR, + PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR, + PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR, + PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR, + PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR, + PCI_LAST_BAR} PCI_INTERNAL_BAR; + +typedef struct pciBar { + unsigned int detectBase; + unsigned int base; + unsigned int size; + unsigned int type; +} PCI_BAR; + +typedef struct pciDevice { + PCI_HOST host; + char type[40]; + unsigned int deviceNum; + unsigned int venID; + unsigned int deviceID; + PCI_BAR bar[6]; +} PCI_DEVICE; + +typedef struct pciSelfBars { + unsigned int SCS0Base; + unsigned int SCS0Size; + unsigned int SCS1Base; + unsigned int SCS1Size; + unsigned int SCS2Base; + unsigned int SCS2Size; + unsigned int SCS3Base; + unsigned int SCS3Size; + unsigned int internalMemBase; + unsigned int internalIOBase; + unsigned int CS0Base; + unsigned int CS0Size; + unsigned int CS1Base; + unsigned int CS1Size; + unsigned int CS2Base; + unsigned int CS2Size; + unsigned int CS3Base; + unsigned int CS3Size; + unsigned int CSBootBase; + unsigned int CSBootSize; + unsigned int P2PMem0Base; + unsigned int P2PMem0Size; + unsigned int P2PMem1Base; + unsigned int P2PMem1Size; + unsigned int P2PIOBase; + unsigned int P2PIOSize; + unsigned int CPUBase; + unsigned int CPUSize; +} PCI_SELF_BARS; + +/* read/write configuration registers on local PCI bus. */ +void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum, unsigned int data); +unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum); + +/* read/write configuration registers on another PCI bus. */ +void pciOverBridgeWriteConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum,unsigned int data); +unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum); + +/* Performs full scane on both PCI and returns all detail possible on the + agents which exist on the bus. */ +void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect, + unsigned int numberOfElment); + +/* Master`s memory space */ +bool pciMapSpace(PCI_HOST host, PCI_REGION region, + unsigned int remapBase, + unsigned int deviceBase, + unsigned int deviceLength); +unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); +unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); + +/* Slave`s memory space */ +void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, + unsigned int pci0Dram0Base, unsigned int pci0Dram0Size); + +#if 0 /* GARBAGE routines - dont use till they get cleaned up */ +void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars); +void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars); +void pci0MapInternalRegSpace(unsigned int pci0InternalBase); +void pci1MapInternalRegSpace(unsigned int pci1InternalBase); +void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase); +void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase); +void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base, + unsigned int pci0Dev0Length); +void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base, + unsigned int pci1Dev0Length); +void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base, + unsigned int pci0Dev1Length); +void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base, + unsigned int pci1Dev1Length); +void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base, + unsigned int pci0Dev2Length); +void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base, + unsigned int pci1Dev2Length); +void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base, + unsigned int pci0Dev3Length); +void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base, + unsigned int pci1Dev3Length); +void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase, + unsigned int pci0DevBootLength); +void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase, + unsigned int pci1DevBootLength); +void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base, + unsigned int pci0P2pMem0Length); +void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base, + unsigned int pci1P2pMem0Length); +void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base, + unsigned int pci0P2pMem1Length); +void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base, + unsigned int pci1P2pMem1Length); +void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase, + unsigned int pci0P2pIoLength); +void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, + unsigned int pci1P2pIoLength); + +void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs); +void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs); +#endif + +/* PCI region options */ + +bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region, + unsigned int features, unsigned int baseAddress, + unsigned int regionLength); + +void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); + +/* PCI arbiter */ + +bool pciArbiterEnable(PCI_HOST host); +bool pciArbiterDisable(PCI_HOST host); +bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, + PCI_AGENT_PRIO externalAgent0, + PCI_AGENT_PRIO externalAgent1, + PCI_AGENT_PRIO externalAgent2, + PCI_AGENT_PRIO externalAgent3, + PCI_AGENT_PRIO externalAgent4, + PCI_AGENT_PRIO externalAgent5); +bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, + PCI_AGENT_PRIO externalAgent0, + PCI_AGENT_PRIO externalAgent1, + PCI_AGENT_PRIO externalAgent2, + PCI_AGENT_PRIO externalAgent3, + PCI_AGENT_PRIO externalAgent4, + PCI_AGENT_PRIO externalAgent5); +bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, + PCI_AGENT_PARK externalAgent0, + PCI_AGENT_PARK externalAgent1, + PCI_AGENT_PARK externalAgent2, + PCI_AGENT_PARK externalAgent3, + PCI_AGENT_PARK externalAgent4, + PCI_AGENT_PARK externalAgent5); +bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); +bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); + +/* PCI-to-PCI (P2P) */ + +bool pciP2PConfig(PCI_HOST host, + unsigned int SecondBusLow,unsigned int SecondBusHigh, + unsigned int busNum,unsigned int devNum); +/* PCI Cache-coherency */ + +bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, + PCI_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength); + +PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev); + +#endif /* __INCpcih */ diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile new file mode 100644 index 0000000..93907ba --- /dev/null +++ b/board/RPXClassic/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o eccx.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c new file mode 100644 index 0000000..49cb8ad --- /dev/null +++ b/board/RPXClassic/RPXClassic.c @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2001 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * U-Boot port on RPXClassic LF (CLLF_BW31) board + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); +static unsigned char aschex_to_byte (unsigned char *cp); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFCC25 + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 00h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, + 0x3FBFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Read. (Offset 08h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, + 0x3FBFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, + 0x3FFFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, + 0x0CFFCC00, 0x33FFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* + * Refresh. (Offset 30h in UPMA RAM) + */ + 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, + 0x3FFFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3Ch in UPMA RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: RPXClassic\n"); + return (0); +} + +/*----------------------------------------------------------------------------- + * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM + *----------------------------------------------------------------------------- + */ +void board_get_enetaddr (uchar * enet) +{ + int i; + char buff[256], *cp; + + /* Initialize I2C */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read 256 bytes in EEPROM */ + i2c_read (0x54, 0, 1, (uchar *)buff, 128); + i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128); + + /* Retrieve MAC address in buffer (key EA) */ + for (cp = buff;;) { + if (cp[0] == 'E' && cp[1] == 'A') { + cp += 3; + /* Read MAC address */ + for (i = 0; i < 6; i++, cp += 2) { + enet[i] = aschex_to_byte ((unsigned char *)cp); + } + } + /* Scan to the end of the record */ + while ((*cp != '\n') && (*cp != (char)0xff)) { + cp++; + } + /* If the next character is a \n, 0 or ff, we are done. */ + cp++; + if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff)) + break; + } + +#ifdef CONFIG_FEC_ENET + /* The MAC address is the same as normal ethernet except the 3rd byte */ + /* (See the E.P. Planet Core Overview manual */ + enet[3] |= 0x80; +#endif + + printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n", + enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]); + +} + +void rpxclassic_init (void) +{ + /* Enable NVRAM */ + *((uchar *) BCSR0) |= BCSR0_ENNVRAM; + +#ifdef CONFIG_FEC_ENET + + /* Validate the fast ethernet tranceiver */ + *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL; + *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN; + *((volatile uchar *) BCSR2) |= BCSR2_MIIRST; + *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN; +#endif + +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size10; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* Refresh clock prescalar */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000000; + + /* Map controller banks 1 to the SDRAM bank */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* Check Bank 0 Memory Size + * try 10 column mode + */ + + size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM, + SDRAM_MAX_SIZE); + + return (size10); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} +/*----------------------------------------------------------------------------- + * aschex_to_byte -- + *----------------------------------------------------------------------------- + */ +static unsigned char aschex_to_byte (unsigned char *cp) +{ + u_char byte, c; + + c = *cp++; + + if ((c >= 'A') && (c <= 'F')) { + c -= 'A'; + c += 10; + } else if ((c >= 'a') && (c <= 'f')) { + c -= 'a'; + c += 10; + } else { + c -= '0'; + } + + byte = c * 16; + + c = *cp; + + if ((c >= 'A') && (c <= 'F')) { + c -= 'A'; + c += 10; + } else if ((c >= 'a') && (c <= 'f')) { + c -= 'a'; + c += 10; + } else { + c -= '0'; + } + + byte += c; + + return (byte); +} diff --git a/board/RPXClassic/config.mk b/board/RPXClassic/config.mk new file mode 100644 index 0000000..ae455e1 --- /dev/null +++ b/board/RPXClassic/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2001 +# Stäubli Faverges - +# Pierre AUBERT p.aubert@staubli.com +# U-Boot port on RPXClassic LF (CLLF_BW31) board +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xff000000 diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c new file mode 100644 index 0000000..cc76bbd --- /dev/null +++ b/board/RPXClassic/eccx.c @@ -0,0 +1,351 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* Video support for the ECCX daughter board */ + + +#include +#include + +#ifdef CONFIG_VIDEO_SED13806 +#include + + +/* Screen configurations: the initialization of the SD13806 depends on + screen and on display mode. We handle only 8bpp and 16 bpp modes */ + +/* ECCX board is supplied with a NEC NL6448BC20 screen */ +#ifdef CONFIG_NEC_NL6448BC20 +#define DISPLAY_WIDTH 640 +#define DISPLAY_HEIGHT 480 + +#ifdef CONFIG_VIDEO_SED13806_8BPP +static const S1D_REGS init_regs [] = +{ + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ + {0x0008,0xe5}, /* General IO Pins Control Register 0 */ + {0x0009,0x1f}, /* General IO Pins Control Register 1 */ + {0x0010,0x02}, /* Memory Clock Configuration Register */ + {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x04}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x25}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ + {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x01}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x03}, /* LCD Display Mode Register */ + {0x0041,0x02}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x40}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x01}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x00}, /* TV Output Control Register */ + {0x0060,0x03}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x00}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01E4,0x00}, /* Look-Up Table Data Register */ + {0x01F0,0x10}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ + {0, 0} +}; +#endif /* CONFIG_VIDEO_SED13806_8BPP */ + +#ifdef CONFIG_VIDEO_SED13806_16BPP + +static const S1D_REGS init_regs [] = +{ + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ + {0x0008,0xe5}, /* General IO Pins Control Register 0 */ + {0x0009,0x1f}, /* General IO Pins Control Register 1 */ + {0x0010,0x02}, /* Memory Clock Configuration Register */ + {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x04}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x25}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ + {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x01}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x05}, /* LCD Display Mode Register */ + {0x0041,0x02}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x00}, /* TV Output Control Register */ + {0x0060,0x05}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x01}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01E4,0x00}, /* Look-Up Table Data Register */ + {0x01F0,0x10}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ + {0, 0} +}; + +#endif /* CONFIG_VIDEO_SED13806_16BPP */ +#endif /* CONFIG_NEC_NL6448BC20 */ + + +#ifdef CONFIG_CONSOLE_EXTRA_INFO + +/*----------------------------------------------------------------------------- + * video_get_info_str -- setup a board string: type, speed, etc. + * line_number= location to place info string beside logo + * info= buffer for info string + *----------------------------------------------------------------------------- + */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { + strcpy (info, " RPXClassic board"); + } + else { + info [0] = '\0'; + } + +} +#endif + +/*----------------------------------------------------------------------------- + * board_video_init -- init de l'EPSON, config du CS + *----------------------------------------------------------------------------- + */ +unsigned int board_video_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* Program ECCX registers */ + *(ECCX_CSR12) |= ECCX_860; + *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2; + *(ECCX_CSR8) |= ECCX_ENEPSON; + + memctl->memc_or2 = SED13806_OR; + memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES; + + return (SED13806_REG_ADDR); +} + +/*----------------------------------------------------------------------------- + * board_validate_screen -- + *----------------------------------------------------------------------------- + */ +void board_validate_screen (unsigned int base) +{ + /* Activate the panel bias power */ + *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80; +} +/*----------------------------------------------------------------------------- + * board_get_regs -- + *----------------------------------------------------------------------------- + */ +const S1D_REGS *board_get_regs (void) +{ + return (init_regs); +} +/*----------------------------------------------------------------------------- + * board_get_width -- + *----------------------------------------------------------------------------- + */ +int board_get_width (void) +{ + return (DISPLAY_WIDTH); +} + +/*----------------------------------------------------------------------------- + * board_get_height -- + *----------------------------------------------------------------------------- + */ +int board_get_height (void) +{ + return (DISPLAY_HEIGHT); +} + +#endif /* CONFIG_VIDEO_SED13806 */ diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c new file mode 100644 index 0000000..2e0b8f9 --- /dev/null +++ b/board/RPXClassic/flash.c @@ -0,0 +1,447 @@ +/* + * (C) Copyright 2001 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * U-Boot port on RPXClassic LF (CLLF_BW31) board + * + * RPXClassic uses Am29DL323B flash memory with 2 banks + * + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0 ; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x00010000; + info->start[3] = base + 0x00018000; + info->start[4] = base + 0x00020000; + info->start[5] = base + 0x00028000; + info->start[6] = base + 0x00030000; + info->start[7] = base + 0x00038000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i-7) * 0x00040000) ; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDL323B: + printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Reset flash componeny */ + addr [0] = 0xf0f0f0f0; + + /* Write auto select command: read Manufacturer ID */ + addr[0xAAA] = 0xAAAAAAAA ; + addr[0x555] = 0x55555555 ; + addr[0xAAA] = 0x90909090 ; + + value = addr[0] ; + + switch (value & 0x00FF00FF) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[2] ; /* device ID */ + + switch (value & 0x00FF00FF) { + case (AMD_ID_DL323B & 0x00FF00FF): + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x01000000; /* 16 Mb */ + + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + /* set up sector start address table */ + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x00010000; + info->start[3] = base + 0x00018000; + info->start[4] = base + 0x00020000; + info->start[5] = base + 0x00028000; + info->start[6] = base + 0x00030000; + info->start[7] = base + 0x00038000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i-7) * 0x00040000) ; + } + + /* check for protected sectors */ + for (i = 0; i < 23; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[4] & 1 ; + } + /* Check for protected sectors in the 2nd bank */ + addr[0x100AAA] = 0xAAAAAAAA ; + addr[0x100555] = 0x55555555 ; + addr[0x100AAA] = 0x90909090 ; + + for (i = 23; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[4] & 1 ; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0xF0F0F0F0; /* reset bank 1 */ + addr = (volatile unsigned long *)info->start[23]; + + *addr = 0xF0F0F0F0; /* reset bank 2 */ + + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0x80808080; + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long *)(info->start[sect]) ; + addr[0] = 0x30303030 ; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long *)(info->start[l_sect]); + while ((addr[0] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0xA0A0A0A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds new file mode 100644 index 0000000..049f990 --- /dev/null +++ b/board/RPXClassic/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) +/* XXX ? + . = env_offset; +*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug new file mode 100644 index 0000000..ddd4678 --- /dev/null +++ b/board/RPXClassic/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/RPXlite/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c new file mode 100644 index 0000000..f37e07b --- /dev/null +++ b/board/RPXlite/RPXlite.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * U-Boot port on RPXlite board + * + * DRAM related UPMA register values are modified. + * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFCC25 + +const uint sdram_table[] = { + /* + * Single Read. (Offset 00h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, + 0x3FBFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Read. (Offset 08h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, + 0x3FBFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, + 0x3FFFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20h in UPMA RAM) + */ + 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, + 0x0CFFCC00, 0x33FFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* + * Refresh. (Offset 30h in UPMA RAM) + */ + 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, + 0x3FFFCC27, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3Ch in UPMA RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: RPXlite\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size10; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* Refresh clock prescalar */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000000; + + /* Map controller banks 1 to the SDRAM bank */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* Check Bank 0 Memory Size + * try 10 column mode + */ + + size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM, + SDRAM_MAX_SIZE); + + return (size10); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size (base, maxsize)); +} diff --git a/board/RPXlite/config.mk b/board/RPXlite/config.mk new file mode 100644 index 0000000..6536b77 --- /dev/null +++ b/board/RPXlite/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# RPXlite boards +# + +TEXT_BASE = 0xfff00000 diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c new file mode 100644 index 0000000..846794d --- /dev/null +++ b/board/RPXlite/flash.c @@ -0,0 +1,524 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * U-Boot port on RPXlite board + * + * Some of flash control words are modified. (from 2x16bit device + * to 4x8bit device) + * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices + * are not tested. + * + * (?) Does an RPXLite board which + * does not use AM29LV800 flash memory exist ? + * I don't know... + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ +/* volatile immap_t *immap = (immap_t *)CFG_IMMR; */ +/* volatile memctl8xx_t *memctl = &immap->im_memctl; */ + unsigned long size_b0 ; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; +%%%*/ + /* Re-do sizing to get full correct info */ + + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00010000; + info->start[2] = base + 0x00018000; + info->start[3] = base + 0x00020000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + ((i-3) * 0x00040000) ; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00040000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0xAAA] = 0x00AA00AA ; + addr[0x555] = 0x00550055 ; + addr[0xAAA] = 0x00900090 ; + + value = addr[0] ; + + switch (value & 0x00FF00FF) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[2] ; /* device ID */ + + switch (value & 0x00FF00FF) { + case (AMD_ID_LV400T & 0x00FF00FF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV400B & 0x00FF00FF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800T & 0x00FF00FF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV800B & 0x00FF00FF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00400000; /*%%% Size doubled by yooth */ + break; /* => 4 MB */ + + case (AMD_ID_LV160T & 0x00FF00FF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV160B & 0x00FF00FF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + /*%%% sector start address modified */ + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00010000; + info->start[2] = base + 0x00018000; + info->start[3] = base + 0x00020000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + ((i-3) * 0x00040000) ; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00040000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[4] & 1 ; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0xF0F0F0F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0x80808080; + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long *)(info->start[sect]) ; + addr[0] = 0x30303030 ; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long *)(info->start[l_sect]); + while ((addr[0] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0xA0A0A0A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds new file mode 100644 index 0000000..049f990 --- /dev/null +++ b/board/RPXlite/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) +/* XXX ? + . = env_offset; +*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug new file mode 100644 index 0000000..ddd4678 --- /dev/null +++ b/board/RPXlite/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/RPXlite_dw/Makefile b/board/RPXlite_dw/Makefile new file mode 100644 index 0000000..d457020 --- /dev/null +++ b/board/RPXlite_dw/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/RPXlite_dw/README b/board/RPXlite_dw/README new file mode 100644 index 0000000..28bcb31 --- /dev/null +++ b/board/RPXlite_dw/README @@ -0,0 +1,161 @@ + +After following the step of Yoo. Jonghoon and Wolfgang Denk, +I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW. + +There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW. + +Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH +RPXlite RPXlite CW 850 16MB 4MB +RPXlite_DW RPXlite DW(EP 823 H1 DW) 823e 64MB 16MB + +This fireware is specially coded for EmbeddedPlanet Co. Software Development +Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel. + +It has the following three features: + +1. 64MHz/48MHz system frequence setting options. +The default setting is 48MHz.To get a 64MHz u-boot,just add +'64' in make command,like + +make distclean +make RPXlite_DW_64_config +make all + +2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM + +The default environment parameter is stored in FLASH because it is a common choice for +environment parameter.So I make NVRAM as backup parameter storeage.The reason why I +didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter +home.Because of the possibility of using two firewares on this board,I didn't +'disturb' EEPROM.To get NVRAM support,you may use the following build command: + +make distclean +make RPXlite_DW_NVRAM_config +make all + +3. LCD panel support + +To support the Platform better,I added LCD panel(NL6448BC20-08) function. +For the convenience of debug, CONFIG_PERBOOT was supported. So you just +perss ENTER if you want to get a serial console in boot downcounting. +Then you can switch to LCD and serial console freely just typing +'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled. + +To get a LCD support u-boot,you can do the following: + +make distclean +make RPXlite_DW_LCD_config +make all + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The basic make commands could be: + +make RPXlite_DW_config +make RPXlite_DW_64_config +make RPXlite_DW_LCD_config +make RPXlite_DW_NVRAM_config + +BTW,you can combine the above features together and get a workable u-boot to meet your need. +For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type: + +make RPXlite_DW_NVRAM_64_LCD_config +make all + +So other combining make commands could be: + +make RPXlite_DW_NVRAM_64_config +make RPXlite_DW_NVRAM_LCD_config +make RPXlite_DW_64_LCD_config + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The boot process by "make RPXlite_DW_config" could be: + +U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) + +CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache +Board: RPXlite_DW +DRAM: 64 MB +FLASH: 16 MB +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET +u-boot> + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +A word on the U-Boot enviroment variable setting and usage : + +In the beginning, you could just need very simple defult environment variable setting, +like[include/configs/RPXlite.h] : + +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +This is enough for kernel NFS test. But as debug process goes on, you would expect +to save some time on environment variable setting and u-boot/kernel updating. +So the default environment variable setting would become more complicated. Just like +the one I did in include/configs/RPXlite_DW.h. + +Two u-boot commands, ku and uu, should be careful to use. They were designed to update +kernel and u-boot image file respectively. You must tftp your image to default address +'100000' and then use them correctly. Yeah, you can create your own command to do this +job. :-) The example u-boot image updating process could be : + +u-boot>t 100000 RPXlite_DW_LCD.bin +Using SCC ETHERNET device +TFTP from server 172.16.115.6; our IP address is 172.16.115.7 +Filename 'RPXlite_DW_LCD.bin'. +Load address: 0x100000 +Loading: ############################# +done +Bytes transferred = 144700 (2353c hex) +u-boot>run uu +Un-Protect Flash Sectors 0-4 in Bank # 1 +Erase Flash Sectors 0-4 in Bank # 1 +.... done +Copy to Flash... done +ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2 +ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 - +ff000020: 31353a32 303a3238 29000000 00000000 15:20:28)....... +ff000030: 00000000 00000000 00000000 00000000 ................ +ff000040: 00000000 00000000 00000000 00000000 ................ +ff000050: 00000000 00000000 00000000 00000000 ................ +ff000060: 00000000 00000000 00000000 00000000 ................ +ff000070: 00000000 00000000 00000000 00000000 ................ +ff000080: 00000000 00000000 00000000 00000000 ................ +ff000090: 00000000 00000000 00000000 00000000 ................ +ff0000a0: 00000000 00000000 00000000 00000000 ................ +ff0000b0: 00000000 00000000 00000000 00000000 ................ +ff0000c0: 00000000 00000000 00000000 00000000 ................ +ff0000d0: 00000000 00000000 00000000 00000000 ................ +ff0000e0: 00000000 00000000 00000000 00000000 ................ +ff0000f0: 00000000 00000000 00000000 00000000 ................ +u-boot updating finished +u-boot> + +Also for environment updating, 'run eu' could let you erase OLD default environment variable +and then use the working u-boot environment setting. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Finally, if you want to keep the serial port to possible debug on spot for deployment, you +just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string +defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot. + +I'd like to extend my heartfelt gratitute to kind people for helping me work it out. +I would particually thank Wolfgang Denk for his nice help. + +Enjoy, + +Sam Song, samsongshu@yahoo.com.cn +Institute of Electrical Machinery and Controls +Shanghai University + +Oct. 11, 2004 diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c new file mode 100644 index 0000000..237c58a --- /dev/null +++ b/board/RPXlite_dw/RPXlite_dw.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2004 + * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Sam Song + * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW + * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz + * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75. + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ +static long int dram_size (long int, long int *, long int); +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFCC25 + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 00h in UPMA RAM) + */ + 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, + + /* + * Burst Read. (Offset 08h in UPMA RAM) + */ + 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, + 0x01FFCC20, 0x1FF74C20, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18h in UPMA RAM) + */ + 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */ + _NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35, + _NOT_USED_, + + /* + * Burst Write. (Offset 20h in UPMA RAM) + */ + 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, + 0x01FFFC24, 0x1FF74C25, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* + * Refresh. (Offset 30h in UPMA RAM) + */ + 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, + 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4, + /* INIT sequence RAM WORDS + * SDRAM Initialization (offset 0x36 in UPMA RAM) + * The above definition uses the remaining space + * to establish an initialization sequence, + * which is executed by a RUN command. + * The sequence is COMMAND INHIBIT(NOP),Precharge, + * Load Mode Register,NOP,Auto Refresh. + */ + + /* + * Exception. (Offset 3Ch in UPMA RAM) + */ + 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ +}; + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: RPXlite_DW\n") ; + return (0) ; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size9; + + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + /* Refresh clock prescalar */ + memctl->memc_mptpr = CFG_MPTPR ; + + memctl->memc_mar = 0x00000088; + + /* Map controller banks 1 to the SDRAM bank */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ + /*Disable Periodic timer A. */ + + udelay(200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */ + + udelay(1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + /*Enable Periodic timer A */ + + udelay (1000); + + /* Check Bank 0 Memory Size + * try 9 column mode + */ + + size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); + + /* + * Final mapping: + */ + + memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + + udelay (1000); + + return (size9); +} + +void rpxlite_init (void) +{ + /* Enable NVRAM */ + *((uchar *) BCSR0) |= BCSR0_ENNVRAM; +} + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size (base, maxsize)); +} diff --git a/board/RPXlite_dw/config.mk b/board/RPXlite_dw/config.mk new file mode 100644 index 0000000..7970910 --- /dev/null +++ b/board/RPXlite_dw/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# RPXlite dw boards : lite_dw +# + +TEXT_BASE = 0xff000000 diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c new file mode 100644 index 0000000..1cbd537 --- /dev/null +++ b/board/RPXlite_dw/flash.c @@ -0,0 +1,490 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * U-Boot port on RPXlite board + * + * Some of flash control words are modified. (from 2x16bit device + * to 4x8bit device) + * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices + * are not tested. + * + * (?) Does an RPXLite board which + * does not use AM29LV800 flash memory exist ? + * I don't know... + */ + +/* Yes,Yoo.They do use other FLASH for the board. + * + * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn + * U-Boot port on RPXlite DW version board + * + * By now,it uses 4 AM29DL323DB90VI devices(4x8bit). + * The total FLASH has 16MB(4x4MB). + * I just made some necessary changes on the basis of Wolfgang and Yoo's job. + * + * June 8, 2004 */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions vu_long : volatile unsigned long IN include/common.h + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +unsigned long flash_init (void) +{ + unsigned long size_b0 ; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + /* If Monitor is in the cope of FLASH,then + * protect this area by default in case for + * other occupation. [SAM] */ + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif + flash_info[0].size = size_b0; + return (size_b0); +} + +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x00010000; + info->start[3] = base + 0x00018000; + info->start[4] = base + 0x00020000; + info->start[5] = base + 0x00028000; + info->start[6] = base + 0x00030000; + info->start[7] = base + 0x00038000; + + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i-7) * 0x00040000); + } + } else { + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00040000; + } + } + +} + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sector)\n"); + break; + /* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM] */ + default: printf ("Unknown Chip Type\n"); + break; + } + printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count); + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0xAAA] = 0x00AA00AA ; + addr[0x555] = 0x00550055 ; + addr[0xAAA] = 0x00900090 ; + + value = addr[0] ; + switch (value & 0x00FF00FF) { + case AMD_MANUFACT: /* AMD_MANUFACT=0x00010001 in flash.h. */ + info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/ + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[2] ; /* device ID */ + switch (value & 0x00FF00FF) { + case (AMD_ID_LV400T & 0x00FF00FF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + case (AMD_ID_LV400B & 0x00FF00FF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + case (AMD_ID_LV800T & 0x00FF00FF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + case (AMD_ID_LV800B & 0x00FF00FF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00400000; /* Size doubled by yooth */ + break; /* => 4 MB */ + case (AMD_ID_LV160T & 0x00FF00FF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + case (AMD_ID_LV160B & 0x00FF00FF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + case (AMD_ID_DL323B & 0x00FF00FF): + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x01000000; + break; /* => 16 MB(4x4MB) */ + /* AMD_ID_DL323B= 0x22532253 FLASH_AMDL323B= 0x0013 + * AMD_ID_DL323B could be found in .[SAM] + * So we could get : flash_id = 0x00000013. + * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1, + * it means bottom boot flash. GOOD IDEA! [SAM] + */ + + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x00010000; + info->start[3] = base + 0x00018000; + info->start[4] = base + 0x00020000; + info->start[5] = base + 0x00028000; + info->start[6] = base + 0x00030000; + info->start[7] = base + 0x00038000; + + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i-7) * 0x00040000) ; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00040000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + /* info->protect[i] = addr[4] & 1 ; */ + /* Mask it for disorder FLASH protection **[Sam]** */ + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0xF0F0F0F0; /* reset bank */ + } + return (info->size); +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0x80808080; + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long *)(info->start[sect]) ; + addr[0] = 0x30303030 ; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long *)(info->start[l_sect]); + while ((addr[0] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0xA0A0A0A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds new file mode 100644 index 0000000..a9c88f6 --- /dev/null +++ b/board/RPXlite_dw/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) +/* XXX ? + . = env_offset; +*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug new file mode 100644 index 0000000..c0cf1cb --- /dev/null +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/RRvision/Makefile b/board/RRvision/Makefile new file mode 100644 index 0000000..fdc6fd5 --- /dev/null +++ b/board/RRvision/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c new file mode 100644 index 0000000..f46bb9e --- /dev/null +++ b/board/RRvision/RRvision.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Always return 1 (no second DRAM bank). + */ + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + puts ("Board: RRvision "); + + for (; s && *s; ++s) { + if (*s == ' ') + break; + putc (*s); + } + + putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long reg; + long int size8, size9; + long int size = 0; + + upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 1 the SDRAM bank 2 at physical address 0. + */ + memctl->memc_or1 = CFG_OR2_PRELIM; + memctl->memc_br1 = CFG_BR2_PRELIM; + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, + SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, + SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size = size9; +/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + size = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); +/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type + * For types > 128 MBit leave it at the current (fast) rate + */ + if (size < 0x02000000) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping + */ + memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + /* + * No bank 1 + * + * invalidate bank + */ + memctl->memc_br3 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + + udelay (10000); + + return (size); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} diff --git a/board/RRvision/config.mk b/board/RRvision/config.mk new file mode 100644 index 0000000..ab1c8d6 --- /dev/null +++ b/board/RRvision/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# RedRock vision boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/RRvision/flash.c b/board/RRvision/flash.c new file mode 100644 index 0000000..d8e07e6 --- /dev/null +++ b/board/RRvision/flash.c @@ -0,0 +1,522 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define DEBUG + +#include +#include + +#ifndef CFG_ENV_ADDR +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size & OR_AM_MSK); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + + flash_info[0].size = size; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + puts ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: puts ("AMD "); break; + case FLASH_MAN_FUJ: puts ("FUJITSU "); break; + default: puts ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: puts ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + puts (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + puts ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + puts ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + switch (value) { + case AMD_ID_LV400B: + case AMD_ID_LV800B: + case AMD_ID_LV160B: + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + break; + case AMD_ID_LV400T: + case AMD_ID_LV800T: + case AMD_ID_LV160T: + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + break; + case AMD_ID_LV320B: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The first 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < 8) + ? 2 * ( 8 << 10) + : 2 * (64 << 10); + } + break; + case AMD_ID_LV320T: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The last 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < (info->sector_count - 8)) + ? 2 * (64 << 10) + : 2 * ( 8 << 10); + } + break; + default: + return (0); + break; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + puts ("- missing\n"); + } else { + puts ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + puts ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + puts ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + puts (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds new file mode 100644 index 0000000..1d6288f --- /dev/null +++ b/board/RRvision/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = env_offset; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/RRvision/video_ad7179.h b/board/RRvision/video_ad7179.h new file mode 100644 index 0000000..f146738 --- /dev/null +++ b/board/RRvision/video_ad7179.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2003 Wolfgang Grandegger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define VIDEO_ENCODER_NAME "Analog Devices AD7179" + +#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */ +#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ + +#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ +#undef VIDEO_MODE_RGB +#define VIDEO_MODE_BPP 16 + +#ifdef VIDEO_MODE_PAL +#define VIDEO_ACTIVE_COLS 720 +#define VIDEO_ACTIVE_ROWS 576 +#define VIDEO_VISIBLE_COLS 640 +#define VIDEO_VISIBLE_ROWS 480 +#else +#error "NTSC mode is not supported" +#endif + +static unsigned char video_encoder_data[] = { + 0x05, /* Mode Register 0 */ + 0x11, /* Mode Register 1 */ + 0x20, /* Mode Register 2 */ + 0x0C, /* Mode Register 3 */ + 0x01, /* Mode Register 4 */ + 0x00, /* Reserved */ + 0x00, /* Reserved */ + 0x04, /* Timing Register 0 */ + 0x00, /* Timing Register 1 */ + 0xCB, /* Subcarrier Frequency Register 0 */ + 0x0A, /* Subcarrier Frequency Register 1 */ + 0x09, /* Subcarrier Frequency Register 2 */ + 0x2A, /* Subcarrier Frequency Register 3 */ + 0x00, /* Subcarrier Phase */ + 0x00, /* Closed Captioning Ext Reg 0 */ + 0x00, /* Closed Captioning Ext Reg 1 */ + 0x00, /* Closed Captioning Reg 0 */ + 0x00, /* Closed Captioning Reg 1 */ + 0x00, /* Pedestal Control Reg 0 */ + 0x00, /* Pedestal Control Reg 1 */ + 0x00, /* Pedestal Control Reg 2 */ + 0x00, /* Pedestal Control Reg 3 */ + 0x00, /* CGMS_WSS Reg 0 */ + 0x00, /* CGMS_WSS Reg 0 */ + 0x00, /* CGMS_WSS Reg 0 */ + 0x00 /* Teletext Req. Control Reg */ +} ; diff --git a/board/a3000/Makefile b/board/a3000/Makefile new file mode 100644 index 0000000..5fde362 --- /dev/null +++ b/board/a3000/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/a3000/README b/board/a3000/README new file mode 100644 index 0000000..f0e92c5 --- /dev/null +++ b/board/a3000/README @@ -0,0 +1,17 @@ +U-Boot for Artis SBC-A3000 +--------------------------- + +Artis SBC-A3000 has one flash socket that the user uses Intel 28F128J3A (16MB) +or 28F064J3A (8MB) chips. + +In board's notation, bank 0 is the one at the address of 0xFF000000. +bank 1 is the one at the address of 0xFF800000 + +On power-up the processor jumps to the address of 0xFFF00100, the last +megabyte of the bank 0 of flash. + +Thus, U-Boot is configured to reside in flash starting at the address of +0xFFF00000. The environment space is located in flash separately from +U-Boot, at the address of 0xFFFE0000. + +There is a National ns83815 10/100M ethernet controller on-board. diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c new file mode 100644 index 0000000..ab707ae --- /dev/null +++ b/board/a3000/a3000.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * Modified during 2003 by + * Ken Chou, kchou@ieee.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int checkboard (void) +{ + ulong busfreq = get_bus_freq(0); + char buf[32]; + + printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq)); + return 0; + +} + +long int initdram (int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +} + +/* + * Initialize PCI Devices + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_a3000_config_table[] = { + /* vendor, device, class */ + /* bus, dev, func */ + { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */ + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */ + pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */ + pci_cfgfunc_config_device, { PCI_ENET2_IOADDR, + PCI_ENET2_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */ + pci_cfgfunc_config_device, { PCI_ENET3_IOADDR, + PCI_ENET3_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_a3000_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} diff --git a/board/a3000/config.mk b/board/a3000/config.mk new file mode 100644 index 0000000..798e032 --- /dev/null +++ b/board/a3000/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Artis A-3000 boards +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/a3000/flash.c b/board/a3000/flash.c new file mode 100644 index 0000000..13a5ca5 --- /dev/null +++ b/board/a3000/flash.c @@ -0,0 +1,454 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + + +/*---------------------------------------------------------------------*/ +#define DEBUG_FLASH + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_char *addr, flash_info_t *info); +static int write_data (flash_info_t *info, uchar *dest, uchar data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +#define BS(b) (b) +#define BYTEME(x) ((x) & 0xFF) + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long flash_banks[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS; + unsigned long size, size_b[CFG_MAX_FLASH_BANKS]; + + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN); + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE); + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + + size = 0; + DEBUGF("## Final Flash bank sizes: "); + for (i=0; iflash_id == FLASH_UNKNOWN) { + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x00020000; /* 128k per bank */ + } + return; + + default: + printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id); + return; + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("Fujitsu "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_MT: printf ("MT "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: + printf ("28F320J3A (32Mbit = 128K x 32)\n"); + break; + case FLASH_28F640J3A: + printf ("28F640J3A (64Mbit = 128K x 64)\n"); + break; + case FLASH_28F128J3A: + printf ("28F128J3A (128Mbit = 128K x 128)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + +#if 1 + if (info->size >= (1 << 20)) { + i = 20; + } else { + i = 10; + } + printf (" Size: %ld %cB in %d Sectors\n", + info->size >> i, + (i == 20) ? 'M' : 'k', + info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +#endif + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_char *addr, flash_info_t *info) +{ + vu_char manuf, device; + + addr[0] = BS(0x90); + manuf = BS(addr[0]); + DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, manuf); + + switch (manuf) { + case BYTEME(AMD_MANUFACT): + info->flash_id = FLASH_MAN_AMD; + break; + case BYTEME(FUJ_MANUFACT): + info->flash_id = FLASH_MAN_FUJ; + break; + case BYTEME(SST_MANUFACT): + info->flash_id = FLASH_MAN_SST; + break; + case BYTEME(STM_MANUFACT): + info->flash_id = FLASH_MAN_STM; + break; + case BYTEME(INTEL_MANUFACT): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */ + return 0; /* no or unknown flash */ + } + + device = BS(addr[2]); /* device ID */ + + DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), device); + + switch (device) { + case BYTEME(INTEL_ID_28F320J3A): + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 4 MB */ + + case BYTEME(INTEL_ID_28F640J3A): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + case BYTEME(INTEL_ID_28F128J3A): + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */ + return 0; /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = BS(0xFF); /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_char *addr = (vu_char *)(info->start[sect]); + unsigned long status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = BS(0x50); /* clear status register */ + *addr = BS(0x20); /* erase setup */ + *addr = BS(0xD0); /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = BS(0xB0); /* suspend erase */ + *addr = BS(0xFF); /* reset to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = BS(0xFF); /* reset to read mode */ + } + } + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 1 /* flash bus width in bytes */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + uchar *wp = (uchar *)addr; + int rc; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + while (cnt > 0) { + if ((rc = write_data(info, wp, *src)) != 0) { + return rc; + } + wp++; + src++; + cnt--; + } + + return cnt; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, uchar *dest, uchar data) +{ + vu_char *addr = (vu_char *)dest; + ulong status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((BS(*addr) & data) != data) { + return 2; + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = BS(0x40); /* write setup */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + start = get_timer (0); + + while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = BS(0xFF); /* restore read mode */ + return 1; + } + } + + *addr = BS(0xFF); /* restore read mode */ + + return 0; +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/a3000/u-boot.lds b/board/a3000/u-boot.lds new file mode 100644 index 0000000..acb9ffd --- /dev/null +++ b/board/a3000/u-boot.lds @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/adder/Makefile b/board/adder/Makefile new file mode 100644 index 0000000..9123a80 --- /dev/null +++ b/board/adder/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2004 Arabella Software Ltd. +# Yuli Barcohen +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/adder/adder.c b/board/adder/adder.c new file mode 100644 index 0000000..cab6e2f --- /dev/null +++ b/board/adder/adder.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen + * + * Support for Analogue&Micro Adder boards family. + * Tested on AdderII and Adder87x. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * SDRAM is single Samsung K4S643232F-T70 chip. + * Minimal CPU frequency is 40MHz. + */ +static uint sdram_table[] = { + /* Single read (offset 0x00 in UPM RAM) */ + 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00, + 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04, + + /* Burst read (offset 0x08 in UPM RAM) */ + 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44, + 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35, + 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35, + + /* Single write (offset 0x18 in UPM RAM) */ + 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47, + 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* Burst write (offset 0x20 in UPM RAM) */ + 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, + 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* Refresh (offset 0x30 in UPM RAM) */ + 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* Exception (offset 0x3C in UPM RAM) */ + 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 +}; + +long int initdram (int board_type) +{ + long int msize = CFG_SDRAM_SIZE; + volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); + + /* Configure SDRAM refresh */ + memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ + + memctl->memc_mamr = (94 << 24) | CFG_MAMR; + memctl->memc_mar = 0x0; + udelay(200); + + /* Run precharge from location 0x15 */ + memctl->memc_mcr = 0x80002115; + udelay(200); + + /* Run 8 refresh cycles */ + memctl->memc_mcr = 0x80002830; + udelay(200); + + memctl->memc_mar = 0x88; + udelay(200); + + /* Run MRS pattern from location 0x16 */ + memctl->memc_mcr = 0x80002116; + udelay(200); + + return msize; +} + +int checkboard( void ) +{ + puts("Board: Adder"); +#if defined(CONFIG_MPC885_FAMILY) + puts("87x\n"); +#elif defined(CONFIG_MPC866_FAMILY) + puts("II\n"); +#endif + + return 0; +} diff --git a/board/adder/config.mk b/board/adder/config.mk new file mode 100644 index 0000000..4691a69 --- /dev/null +++ b/board/adder/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2004 Arabella Software Ltd. +# Yuli Barcohen +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Analogue&Micro Adder boards family +# +TEXT_BASE = 0xFE000000 diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds new file mode 100644 index 0000000..66c3246 --- /dev/null +++ b/board/adder/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/adsvix/Makefile b/board/adsvix/Makefile new file mode 100644 index 0000000..24d5d06 --- /dev/null +++ b/board/adsvix/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := adsvix.o pcmcia.o +SOBJS := lowlevel_init.o pxavoltage.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/adsvix/adsvix.c b/board/adsvix/adsvix.c new file mode 100644 index 0000000..5e770e9 --- /dev/null +++ b/board/adsvix/adsvix.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of ADSVIX-Board */ + gd->bd->bi_arch_number = 620; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa000003c; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/adsvix/config.mk b/board/adsvix/config.mk new file mode 100644 index 0000000..98be4eb --- /dev/null +++ b/board/adsvix/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1700000 diff --git a/board/adsvix/lowlevel_init.S b/board/adsvix/lowlevel_init.S new file mode 100644 index 0000000..8dea71c --- /dev/null +++ b/board/adsvix/lowlevel_init.S @@ -0,0 +1,466 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/adsvix/pcmcia.c b/board/adsvix/pcmcia.c new file mode 100644 index 0000000..ba5be01 --- /dev/null +++ b/board/adsvix/pcmcia.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void pcmcia_power_on(void) +{ +#if 0 + if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */ + GPCR(81) = GPIO_bit(81); + GPSR(82) = GPIO_bit(82); + } + else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */ + GPCR(81) = GPIO_bit(81); + GPCR(82) = GPIO_bit(82); + } +#else +#warning "Board will only supply 5V, wait for next HW spin for selectable power" + /* 5.0V */ + GPCR(81) = GPIO_bit(81); + GPCR(82) = GPIO_bit(82); +#endif + + udelay(300000); + + /* reset the card */ + GPSR(52) = GPIO_bit(52); + + /* enable PCMCIA */ + GPCR(83) = GPIO_bit(83); + + /* clear reset */ + udelay(10); + GPCR(52) = GPIO_bit(52); + + udelay(20000); +} + +void pcmcia_power_off(void) +{ + /* 0V */ + GPSR(81) = GPIO_bit(81); + GPSR(82) = GPIO_bit(82); + /* disable PCMCIA */ + GPSR(83) = GPIO_bit(83); +} diff --git a/board/adsvix/pxavoltage.S b/board/adsvix/pxavoltage.S new file mode 100644 index 0000000..2fe1cab --- /dev/null +++ b/board/adsvix/pxavoltage.S @@ -0,0 +1,230 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define LTC1663_ADDR 0x20 + +#define LTC1663_SY 0x01 /* Sync ACK */ +#define LTC1663_SD 0x04 /* shutdown */ +#define LTC1663_BG 0x04 /* Internal Voltage Ref */ + +#define VOLT_1_55 18 /* DAC value for 1.55V */ + + .global initPXAvoltage + +@ Set the voltage to 1.55V early in the boot process so we can run +@ at a high clock speed and boot quickly. Note that this is necessary +@ because the reset button does not reset the CPU voltage, so if the +@ voltage was low (say 0.85V) then the CPU would crash without this +@ routine + +@ This routine clobbers r0-r4 + +initializei2c: + + ldr r2, =CKEN + ldr r3, [r2] + orr r3, r3, #CKEN15_PWRI2C + str r3, [r2] + + ldr r2, =PCFR + ldr r3, [r2] + orr r3, r3, #PCFR_PI2C_EN + str r3, [r2] + + /* delay for about 250msec + */ + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC0000 + +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + ldr r0, =PWRICR + ldr r1, [r0] + bic r1, r1, #(ICR_MA | ICR_START | ICR_STOP) + str r1, [r0] + + orr r1, r1, #ICR_UR + str r1, [r0] + + ldr r2, =PWRISR + ldr r3, =0x7ff + str r3, [r2] + + bic r1, r1, #ICR_UR + str r1, [r0] + + mov r1, #(ICR_GCD | ICR_SCLE) + str r1, [r0] + + orr r1, r1, #ICR_IUE + str r1, [r0] + + orr r1, r1, #ICR_FM + str r1, [r0] + + /* delay for about 1msec + */ + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC00 + +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + mov pc, lr + +sendbytei2c: + ldr r3, =PWRIDBR + str r0, [r3] + ldr r3, =PWRICR + ldr r0, [r3] + orr r0, r0, r1 + bic r0, r0, r2 + str r0, [r3] + orr r0, r0, #ICR_TB + str r0, [r3] + + mov r2, #0x100000 + +waitfortxemptyi2c: + + ldr r0, =PWRISR + ldr r1, [r0] + + /* take it from the top if we don't get empty after a while */ + subs r2, r2, #1 + moveq lr, r4 + beq initPXAvoltage + + tst r1, #ISR_ITE + + beq waitfortxemptyi2c + + orr r1, r1, #ISR_ITE + str r1, [r0] + + mov pc, lr + +initPXAvoltage: + + mov r4, lr + + bl setleds + + bl initializei2c + + bl setleds + + /* now send the real message to set the correct voltage */ + ldr r0, =LTC1663_ADDR + mov r0, r0, LSL #1 + mov r1, #ICR_START + ldr r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK) + bl sendbytei2c + + bl setleds + + mov r0, #LTC1663_BG + mov r1, #0 + mov r2, #(ICR_STOP | ICR_START) + bl sendbytei2c + + bl setleds + + ldr r0, =VOLT_1_55 + and r0, r0, #0xff + mov r1, #0 + mov r2, #(ICR_STOP | ICR_START) + bl sendbytei2c + + bl setleds + + ldr r0, =VOLT_1_55 + mov r0, r0, ASR #8 + and r0, r0, #0xff + mov r1, #ICR_STOP + mov r2, #ICR_START + bl sendbytei2c + + bl setleds + + @ delay a little for the volatage to stablize + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC0 + +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + mov pc, r4 + +setleds: + mov pc, lr + + ldr r5, =0x40e00058 + ldr r3, [r5] + bic r3, r3, #0x3 + str r3, [r5] + ldr r5, =0x40e0000c + ldr r3, [r5] + orr r3, r3, #0x00010000 + str r3, [r5] + + @ inner loop + mov r0, #0x2 +1: + + ldr r5, =0x40e00018 + mov r3, #0x00010000 + str r3, [r5] + + @ outer loop + mov r3, #0x00F00000 +2: + subs r3, r3, #1 + bne 2b + + ldr r5, =0x40e00024 + mov r3, #0x00010000 + str r3, [r5] + + @ outer loop + mov r3, #0x00F00000 +3: + subs r3, r3, #1 + bne 3b + + subs r0, r0, #1 + bne 1b + + mov pc, lr diff --git a/board/adsvix/u-boot.lds b/board/adsvix/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/adsvix/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/alaska/Makefile b/board/alaska/Makefile new file mode 100644 index 0000000..a4c1d2e --- /dev/null +++ b/board/alaska/Makefile @@ -0,0 +1,45 @@ +# (C) Copyright 2003-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c new file mode 100644 index 0000000..93874b2 --- /dev/null +++ b/board/alaska/alaska.c @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2004, Freescale Inc. + * TsiChung Liew, Tsi-Chung.Liew@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +void setupBat (ulong size) +{ + ulong batu, batl; + int blocksize = 0; + + /* Flash 0 */ +#if defined (CFG_AMD_BOOT) + batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; +#else + batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; +#endif + batl = CFG_FLASH0_BASE | 0x22; + write_bat (IBAT0, batu, batl); + write_bat (DBAT0, batu, batl); + + /* Flash 1 */ +#if defined (CFG_AMD_BOOT) + batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; +#else + batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; +#endif + batl = CFG_FLASH1_BASE | 0x22; + write_bat (IBAT1, batu, batl); + write_bat (DBAT1, batu, batl); + + /* CPLD */ + batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batl = CFG_CPLD_BASE | 0x22; + write_bat (IBAT2, 0, 0); + write_bat (DBAT2, batu, batl); + + /* FPGA */ + batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batl = CFG_FPGA_BASE | 0x22; + write_bat (IBAT3, 0, 0); + write_bat (DBAT3, batu, batl); + + /* MBAR - Data only */ + batu = CFG_MBAR | BPP_RW | BPP_RX; + batl = CFG_MBAR | 0x22; + mtspr (IBAT4L, 0); + mtspr (IBAT4U, 0); + mtspr (DBAT4L, batl); + mtspr (DBAT4U, batu); + + /* MBAR - SRAM */ + batu = CFG_SRAM_BASE | BPP_RW | BPP_RX; + batl = CFG_SRAM_BASE | 0x42; + mtspr (IBAT5L, batl); + mtspr (IBAT5U, batu); + mtspr (DBAT5L, batl); + mtspr (DBAT5U, batu); + + if (size <= 0x800000) /* 8MB */ + blocksize = BL_8M << 2; + else if (size <= 0x1000000) /* 16MB */ + blocksize = BL_16M << 2; + else if (size <= 0x2000000) /* 32MB */ + blocksize = BL_32M << 2; + else if (size <= 0x4000000) /* 64MB */ + blocksize = BL_64M << 2; + else if (size <= 0x8000000) /* 128MB */ + blocksize = BL_128M << 2; + else if (size <= 0x10000000) /* 256MB */ + blocksize = BL_256M << 2; + + /* Memory */ + batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX; + batl = CFG_SDRAM_BASE | 0x42; + mtspr (IBAT6L, batl); + mtspr (IBAT6U, batu); + mtspr (DBAT6L, batl); + mtspr (DBAT6U, batu); + + /* memory size is less than 256MB */ + if (size <= 0x10000000) { + /* Nothing */ + batu = 0; + batl = 0; + } else { + size -= 0x10000000; + if (size <= 0x800000) /* 8MB */ + blocksize = BL_8M << 2; + else if (size <= 0x1000000) /* 16MB */ + blocksize = BL_16M << 2; + else if (size <= 0x2000000) /* 32MB */ + blocksize = BL_32M << 2; + else if (size <= 0x4000000) /* 64MB */ + blocksize = BL_64M << 2; + else if (size <= 0x8000000) /* 128MB */ + blocksize = BL_128M << 2; + else if (size <= 0x10000000) /* 256MB */ + blocksize = BL_256M << 2; + + batu = (CFG_SDRAM_BASE + + 0x10000000) | blocksize | BPP_RW | BPP_RX; + batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42; + } + + mtspr (IBAT7L, batl); + mtspr (IBAT7U, batu); + mtspr (DBAT7L, batl); + mtspr (DBAT7U, batu); +} + +long int initdram (int board_type) +{ + ulong size; + + size = dramSetup (); + +/* if iCache ad dCache is defined */ +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) +/* setupBat(size);*/ +#endif + + return size; +} + +int checkboard (void) +{ + puts ("Board: Alaska MPC8220 Evaluation Board\n"); + + return 0; +} diff --git a/board/alaska/config.mk b/board/alaska/config.mk new file mode 100644 index 0000000..99d28a5 --- /dev/null +++ b/board/alaska/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# alaska board +# + +TEXT_BASE = 0xfff00000 +# TEXT_BASE = 0x00100000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/alaska/flash.c b/board/alaska/flash.c new file mode 100644 index 0000000..383491f --- /dev/null +++ b/board/alaska/flash.c @@ -0,0 +1,936 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH8 + +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; + +#define SWAP(x) (x) + +/* Intel-compatible flash ID */ +#define INTEL_COMPAT 0x89 +#define INTEL_ALT 0xB0 + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x10 +#define INTEL_ERASE 0x20 +#define INTEL_CLEAR 0x50 +#define INTEL_LOCKBIT 0x60 +#define INTEL_PROTECT 0x01 +#define INTEL_STATUS 0x70 +#define INTEL_READID 0x90 +#define INTEL_CONFIRM 0xD0 +#define INTEL_RESET 0xFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x80 +#define INTEL_OK 0x80 + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +#define WR_BLOCK 0x20 +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static int write_data_block (flash_info_t * info, ulong src, ulong dest); +static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +static void flash_sync_real_protect (flash_info_t * info); +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); +static unsigned char same_chip_banks (int bank1, int bank2); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + ulong fsize = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + memset (&flash_info[i], 0, sizeof (flash_info_t)); + + switch (i) { + case 0: + flash_get_size ((FPW *) CFG_FLASH1_BASE, + &flash_info[i]); + flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]); + break; + case 1: + flash_get_size ((FPW *) CFG_FLASH1_BASE, + &flash_info[i]); + fsize = CFG_FLASH1_BASE + flash_info[i - 1].size; + flash_get_offsets (fsize, &flash_info[i]); + break; + case 2: + flash_get_size ((FPW *) CFG_FLASH0_BASE, + &flash_info[i]); + flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]); + break; + case 3: + flash_get_size ((FPW *) CFG_FLASH0_BASE, + &flash_info[i]); + fsize = CFG_FLASH0_BASE + flash_info[i - 1].size; + flash_get_offsets (fsize, &flash_info[i]); + break; + default: + panic ("configured to many flash banks!\n"); + break; + } + size += flash_info[i].size; + + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); + } + + /* Protect monitor and environment sectors + */ +#if defined (CFG_AMD_BOOT) + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[2]); + flash_protect (FLAG_PROTECT_SET, + CFG_INTEL_BASE, + CFG_INTEL_BASE + monitor_flash_len - 1, + &flash_info[1]); +#else + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[3]); + flash_protect (FLAG_PROTECT_SET, + CFG_AMD_BASE, + CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]); +#endif + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV1_ADDR, + CFG_ENV1_ADDR + CFG_ENV1_SIZE - 1, &flash_info[1]); + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[3]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) + return; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_AMD_SECT_SIZE); + info->protect[i] = 0; + } + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE); + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + case FLASH_MAN_AMD: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + + case FLASH_AM040: + printf ("AMD29F040B\n"); + break; + + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + FPWV value; + static int amd = 0; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ + __asm__ ("sync"); + addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ + __asm__ ("sync"); + addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */ + __asm__ ("sync"); + + udelay (100); + + switch (addr[0] & 0xff) { + + case (uchar) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + value = addr[1]; + break; + + case (uchar) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + value = addr[2]; + break; + + default: + printf ("unknown\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 64; + info->size = 0x00800000; /* => 16 MB */ + break; + + case (FPW) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + if (amd == 0) { + info->sector_count = 7; + info->size = 0x00070000; /* => 448 KB */ + amd = 1; + } else { + /* for Environment settings */ + info->sector_count = 1; + info->size = PHYS_AMD_SECT_SIZE; /* => 64 KB */ + amd = 0; + } + break; + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + if (value == (FPW) INTEL_ID_28F128J3A) + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + else + addr[0] = (FPW) 0x00F000F0; /* restore read mode */ + + return (info->size); +} + + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +static void flash_sync_real_protect (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + case FLASH_AM040: + default: + /* no h/w protect support */ + break; + } +} + + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + udelay(1); + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer (0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* wait at least 35ns (W12) before reading */ + udelay(1); + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector] + 4; + ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + + +/* + * Checks if "bank1" and "bank2" are on the same chip. Returns 1 if they + * are and 0 otherwise. + */ +static unsigned char same_chip_banks (int bank1, int bank2) +{ + unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = { + {1, 1, 0, 0}, + {1, 1, 0, 0}, + {0, 0, 1, 1}, + {0, 0, 1, 1} + }; + return same_chip[bank1][bank2]; +} + + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0, intel = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf ("- missing\n"); + else + printf ("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_AMD)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + } + + if (type == FLASH_MAN_INTEL) + intel = 1; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + start = get_timer (0); + + if (intel) { + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + } else { + FPWV *base; /* first address in bank */ + + base = (FPWV *) (CFG_AMD_BASE); + base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ + *addr = (FPW) 0x00300030; /* erase sector */ + } + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + if (intel) { + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + } else + *addr = (FPW) 0x00F000F0; /* reset to read mode */ + + rcode = 1; + break; + } + } + + if (intel) { + *addr = (FPW) 0x00500050; /* clear status register cmd. */ + *addr = (FPW) 0x00FF00FF; /* resest to read mode */ + } else + *addr = (FPW) 0x00F000F0; /* reset to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + { + FPW data = 0; /* 16 or 32 bit word, matches flash bus width */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof (data), left -= + sizeof (data) - bytes) { + + bytes = addr & (sizeof (data) - 1); + addr &= ~(sizeof (data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof (data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left) + data += *((uchar *) addr + i); + else + data += *src++; + } + + res = write_word_amd (info, (FPWV *) addr, + data); + } + return res; + } /* case FLASH_MAN_AMD */ + + case FLASH_MAN_INTEL: + { + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + /* get lower word aligned address */ + wp = addr; + port_width = 1; + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = + write_data (info, wp, SWAP (data))) != 0) + return (rc); + wp += port_width; + } + + if (cnt > WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= WR_BLOCK) { + + if ((rc = + write_data_block (info, + (ulong) src, + wp)) != 0) + return (rc); + + wp += WR_BLOCK; + src += WR_BLOCK; + cnt -= WR_BLOCK; + + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + } + + if (cnt < WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) + data = (data << 8) | *src++; + + if ((rc = + write_data (info, wp, + SWAP (data))) != 0) + return (rc); + + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + } + + if (cnt == 0) + return (0); + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; + ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + + for (; i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + return (write_data (info, wp, SWAP (data))); + } /* case FLASH_MAN_INTEL */ + + } /* switch */ + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + start = get_timer (0); + + /* wait while polling the status register */ + while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data_block (flash_info_t * info, ulong src, ulong dest) +{ + FPWV *srcaddr = (FPWV *) src; + FPWV *dstaddr = (FPWV *) dest; + ulong start; + int flag, i; + + /* Check if Flash is (sufficiently) erased */ + for (i = 0; i < WR_BLOCK; i++) + if ((*dstaddr++ & 0xff) != 0xff) { + printf ("not erased at %08lx (%lx)\n", + (ulong) dstaddr, *dstaddr); + return (2); + } + + dstaddr = (FPWV *) dest; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *dstaddr = (FPW) 0x00e800e8; /* write block setup */ + + /* arm simple, non interrupt dependent timer */ + start = get_timer (0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) 0x001f001f; /* write 32 to buffer */ + for (i = 0; i < WR_BLOCK; i++) + *dstaddr++ = *srcaddr++; + + dstaddr -= 1; + *dstaddr = (FPW) 0x00d000d0; /* write 32 to buffer */ + + /* arm simple, non interrupt dependent timer */ + start = get_timer (0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + base = (FPWV *) (CFG_AMD_BASE); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW) 0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +/*----------------------------------------------------------------------- + * Set/Clear sector's lock bit, returns: + * 0 - OK + * 1 - Error (timeout, voltage problems, etc.) + */ +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + ulong start; + int i, j; + int curr_bank; + int bank; + int rc = 0; + FPWV *addr = (FPWV *) (info->start[sector]); + int flag = disable_interrupts (); + + /* + * 29F040B AMD flash does not support software protection/unprotection, + * the only way to protect the AMD flash is marked it as prot bit. + * This flash only support hardware protection, by supply or not supply + * 12vpp to the flash + */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { + info->protect[sector] = prot; + + return 0; + } + + *addr = INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + } else { /* Clear sector lock bit */ + *addr = INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = INTEL_CONFIRM; /* clear */ + } + + start = get_timer (0); + + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) { + printf ("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + + if (*addr != INTEL_OK) { + printf ("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint) addr, (uint) * addr); + rc = 1; + } + + if (!rc) + info->protect[sector] = prot; + + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + */ + if (!prot) { + /* + * re-locking must be done for all banks that belong on one + * FLASH chip, as all the sectors on the chip were unlocked + * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope + * that banks never span chips, in particular chips which + * support h/w protection differently). + */ + + /* find the current bank number */ + curr_bank = CFG_MAX_FLASH_BANKS + 1; + for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) { + if (&flash_info[j] == info) { + curr_bank = j; + } + } + if (curr_bank == CFG_MAX_FLASH_BANKS + 1) { + printf("Error: can't determine bank number!\n"); + } + + for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) { + if (!same_chip_banks(curr_bank, bank)) { + continue; + } + info = &flash_info[bank]; + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) { + start = get_timer (0); + addr = (FPWV *) (info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + while ((*addr & INTEL_FINISHED) != + INTEL_FINISHED) { + if (get_timer (start) > + CFG_FLASH_UNLOCK_TOUT) { + printf ("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + } + } + } + + /* + * get the s/w sector protection status in sync with the h/w, + * in case something went wrong during the re-locking. + */ + flash_sync_real_protect(info); /* resets flash to read mode */ + } + + if (flag) + enable_interrupts (); + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} diff --git a/board/alaska/u-boot.lds b/board/alaska/u-boot.lds new file mode 100644 index 0000000..889bc77 --- /dev/null +++ b/board/alaska/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8220/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/altera/common/flash.c b/board/altera/common/flash.c new file mode 100644 index 0000000..2638ea8 --- /dev/null +++ b/board/altera/common/flash.c @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*--------------------------------------------------------------------*/ +void flash_print_info (flash_info_t * info) +{ + int i, k; + unsigned long size; + int erased; + volatile unsigned char *flash; + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + + /* Check if whole sector is erased */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned char *) info->start[i]; + for (k = 0; k < size; k++) { + if (*flash++ != 0xff) { + erased = 0; + break; + } + } + + /* Print the info */ + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", info->start[i], erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf ("\n"); +} + +/*-------------------------------------------------------------------*/ + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int prot, sect; + unsigned oldpri; + ulong start; + + /* Some sanity checking */ + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + +#ifdef DEBUG + for (sect = s_first; sect <= s_last; sect++) { + printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]); + } +#endif + + /* NOTE: disabling interrupts on Nios can be very bad since it + * also disables the LO_LIMIT exception. It's better here to + * set the interrupt priority to 3 & restore it when we're done. + */ + oldpri = ipri (3); + + /* It's ok to erase multiple sectors provided we don't delay more + * than 50 usec between cmds ... at which point the erase time-out + * occurs. So don't go and put printf() calls in the loop ... it + * won't be very helpful ;-) + */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + *addr = 0xaa; + *addr = 0x55; + *addr = 0x80; + *addr = 0xaa; + *addr = 0x55; + *addr2 = 0x30; + /* Now just wait for 0xff & provide some user + * feedback while we wait. Here we have to grant + * timer interrupts. Otherwise get_timer() can't + * work right. */ + ipri(oldpri); + start = get_timer (0); + while (*addr2 != 0xff) { + udelay (1000 * 1000); + putc ('.'); + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + printf ("timeout\n"); + return 1; + } + } + oldpri = ipri (3); /* disallow non important irqs again */ + } + } + + printf ("\n"); + + /* Restore interrupt priority */ + ipri (oldpri); + + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + + vu_char *cmd = (vu_char *) info->start[0]; + vu_char *dst = (vu_char *) addr; + unsigned char b; + unsigned oldpri; + ulong start; + + while (cnt) { + /* Check for sufficient erase */ + b = *src; + if ((*dst & b) != b) { + printf ("%02x : %02x\n", *dst, b); + return (2); + } + + /* Disable interrupts other than window underflow + * (interrupt priority 2) + */ + oldpri = ipri (3); + *cmd = 0xaa; + *cmd = 0x55; + *cmd = 0xa0; + *dst = b; + + /* Verify write */ + start = get_timer (0); + while (*dst != b) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + ipri (oldpri); + return 1; + } + } + dst++; + src++; + cnt--; + ipri (oldpri); + } + + return (0); +} diff --git a/board/altera/common/sevenseg.c b/board/altera/common/sevenseg.c new file mode 100644 index 0000000..c53cec1 --- /dev/null +++ b/board/altera/common/sevenseg.c @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * common/sevenseg.c + * + * NIOS PIO based seven segment led support functions + */ + +#include +#include + +#ifdef CONFIG_SEVENSEG + +#define SEVENDEG_MASK_DP ((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP) + +#ifdef SEVENSEG_WRONLY /* emulate read access */ +#if (SEVENSEG_ACTIVE == 0) +static unsigned int sevenseg_portval = ~0; +#else +static unsigned int sevenseg_portval = 0; +#endif +#endif + +static int sevenseg_init_done = 0; + +static inline void __sevenseg_set_masked (unsigned int mask, int value) +{ + nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; + +#ifdef SEVENSEG_WRONLY /* emulate read access */ + +#if (SEVENSEG_ACTIVE == 0) + if (value) + sevenseg_portval &= ~mask; + else + sevenseg_portval |= mask; +#else + if (value) + sevenseg_portval |= mask; + else + sevenseg_portval &= ~mask; +#endif + + piop->data = sevenseg_portval; + +#else /* !SEVENSEG_WRONLY */ + +#if (SEVENSEG_ACTIVE == 0) + if (value) + piop->data &= ~mask; + else + piop->data |= mask; +#else + if (value) + piop->data |= mask; + else + piop->data &= ~mask; +#endif + +#endif /* SEVENSEG_WRONLY */ +} + +static inline void __sevenseg_toggle_masked (unsigned int mask) +{ + nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE; + +#ifdef SEVENSEG_WRONLY /* emulate read access */ + + sevenseg_portval ^= mask; + piop->data = sevenseg_portval; + +#else /* !SEVENSEG_WRONLY */ + + piop->data ^= mask; + +#endif /* SEVENSEG_WRONLY */ +} + +static inline void __sevenseg_set (unsigned int value) +{ + nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; + +#ifdef SEVENSEG_WRONLY /* emulate read access */ + +#if (SEVENSEG_ACTIVE == 0) + sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP) + | ((~value) & (~SEVENDEG_MASK_DP)); +#else + sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP) + | (value); +#endif + + piop->data = sevenseg_portval; + +#else /* !SEVENSEG_WRONLY */ + +#if (SEVENSEG_ACTIVE == 0) + piop->data = (piop->data & SEVENDEG_MASK_DP) + | ((~value) & (~SEVENDEG_MASK_DP)); +#else + piop->data = (piop->data & SEVENDEG_MASK_DP) + | (value); +#endif + +#endif /* SEVENSEG_WRONLY */ +} + +static inline void __sevenseg_init (void) +{ + nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; + + __sevenseg_set(0); + +#ifndef SEVENSEG_WRONLY /* setup direction */ + + piop->direction |= mask; + +#endif /* SEVENSEG_WRONLY */ +} + + +void sevenseg_set(int value) +{ + unsigned char digits[] = { + SEVENSEG_DIGITS_0, + SEVENSEG_DIGITS_1, + SEVENSEG_DIGITS_2, + SEVENSEG_DIGITS_3, + SEVENSEG_DIGITS_4, + SEVENSEG_DIGITS_5, + SEVENSEG_DIGITS_6, + SEVENSEG_DIGITS_7, + SEVENSEG_DIGITS_8, + SEVENSEG_DIGITS_9, + SEVENSEG_DIGITS_A, + SEVENSEG_DIGITS_B, + SEVENSEG_DIGITS_C, + SEVENSEG_DIGITS_D, + SEVENSEG_DIGITS_E, + SEVENSEG_DIGITS_F + }; + + if (!sevenseg_init_done) { + __sevenseg_init(); + sevenseg_init_done++; + } + + switch (value & SEVENSEG_MASK_CTRL) { + + case SEVENSEG_RAW: + __sevenseg_set( ( + (digits[((value & SEVENSEG_MASK_VAL) >> 4)] << 8) | + digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) ); + return; + break; /* paranoia */ + + case SEVENSEG_OFF: + __sevenseg_set(0); + __sevenseg_set_masked(SEVENDEG_MASK_DP, 0); + return; + break; /* paranoia */ + + case SEVENSEG_SET_DPL: + __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1); + return; + break; /* paranoia */ + + case SEVENSEG_SET_DPH: + __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1); + return; + break; /* paranoia */ + + case SEVENSEG_RES_DPL: + __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0); + return; + break; /* paranoia */ + + case SEVENSEG_RES_DPH: + __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0); + return; + break; /* paranoia */ + + case SEVENSEG_TOG_DPL: + __sevenseg_toggle_masked(SEVENSEG_DIGIT_DP); + return; + break; /* paranoia */ + + case SEVENSEG_TOG_DPH: + __sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8)); + return; + break; /* paranoia */ + + case SEVENSEG_LO: + case SEVENSEG_HI: + case SEVENSEG_STR: + default: + break; + } +} + +#endif /* CONFIG_SEVENSEG */ diff --git a/board/altera/common/sevenseg.h b/board/altera/common/sevenseg.h new file mode 100644 index 0000000..cbfd2e7 --- /dev/null +++ b/board/altera/common/sevenseg.h @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * common/sevenseg.h + * + * NIOS PIO based seven segment led support functions + */ + +#ifndef __DK1S10_SEVENSEG_H__ +#define __DK1S10_SEVENSEG_H__ + +#ifdef CONFIG_SEVENSEG + +/* + * 15 8 7 0 + * |-----------------------|--------| + * | controll value | value | + * ---------------------------------- + */ +#define SEVENSEG_RAW (int)(0) /* write out byte value (hex) */ +#define SEVENSEG_OFF (int)( 1 << 8) /* display switch off */ +#define SEVENSEG_SET_DPL (int)( 2 << 8) /* set dp low nibble */ +#define SEVENSEG_SET_DPH (int)( 3 << 8) /* set dp high nibble */ +#define SEVENSEG_RES_DPL (int)( 4 << 8) /* reset dp low nibble */ +#define SEVENSEG_RES_DPH (int)( 5 << 8) /* reset dp high nibble */ +#define SEVENSEG_TOG_DPL (int)( 6 << 8) /* toggle dp low nibble */ +#define SEVENSEG_TOG_DPH (int)( 7 << 8) /* toggle dp high nibble */ +#define SEVENSEG_LO (int)( 8 << 8) /* write out low nibble only */ +#define SEVENSEG_HI (int)( 9 << 8) /* write out high nibble only */ +#define SEVENSEG_STR (int)(10 << 8) /* write out a string */ + +#define SEVENSEG_MASK_VAL (0xff) /* only used by SEVENSEG_RAW */ +#define SEVENSEG_MASK_CTRL (~SEVENSEG_MASK_VAL) + +#ifdef SEVENSEG_DIGIT_HI_LO_EQUAL + +#define SEVENSEG_DIGITS_0 ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_F ) +#define SEVENSEG_DIGITS_1 ( SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_C ) +#define SEVENSEG_DIGITS_2 ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_3 ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_4 ( SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_F \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_5 ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_F \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_6 ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_F \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_7 ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_C ) +#define SEVENSEG_DIGITS_8 ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_F \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_9 ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_F \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_A ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_F \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_B ( SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_F \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_C ( SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_D ( SEVENSEG_DIGIT_B \ + | SEVENSEG_DIGIT_C \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_E ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_D \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_F \ + | SEVENSEG_DIGIT_G ) +#define SEVENSEG_DIGITS_F ( SEVENSEG_DIGIT_A \ + | SEVENSEG_DIGIT_E \ + | SEVENSEG_DIGIT_F \ + | SEVENSEG_DIGIT_G ) + +#else /* !SEVENSEG_DIGIT_HI_LO_EQUAL */ +#error SEVENSEG: different pin asssignments not supported +#endif + +void sevenseg_set(int value); + +#endif /* CONFIG_SEVENSEG */ + +#endif /* __DK1S10_SEVENSEG_H__ */ diff --git a/board/altera/dk1c20/Makefile b/board/altera/dk1c20/Makefile new file mode 100644 index 0000000..9182a4e --- /dev/null +++ b/board/altera/dk1c20/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o misc.o + +SOBJS = vectors.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/altera/dk1c20/config.mk b/board/altera/dk1c20/config.mk new file mode 100644 index 0000000..d200715 --- /dev/null +++ b/board/altera/dk1c20/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2003 +# Psyent Corporation +# Scott McNutt +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x018c0000 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c new file mode 100644 index 0000000..98ee7a7 --- /dev/null +++ b/board/altera/dk1c20/dk1c20.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * CompactFlash/IDE: + * (C) Copyright 2004, Shlomo Kut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#if defined(CONFIG_SEVENSEG) +#include "../common/sevenseg.h" +#endif + +void _default_hdlr (void) +{ + printf ("default_hdlr\n"); +} + +int board_early_init_f (void) +{ +#if defined(CONFIG_SEVENSEG) + /* init seven segment led display and switch off */ + sevenseg_set(SEVENSEG_OFF); +#endif + return 0; +} + +int checkboard (void) +{ + puts ("Board: Altera Nios 1C20 Development Kit\n"); + return 0; +} + +long int initdram (int board_type) +{ + return (0); +} + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +int ide_preinit (void) +{ + nios_pio_t *present = (nios_pio_t *) CFG_CF_PRESENT; + nios_pio_t *power = (nios_pio_t *) CFG_CF_POWER; + nios_pio_t *atasel = (nios_pio_t *) CFG_CF_ATASEL; + + /* setup data direction registers */ + present->direction = NIOS_PIO_IN; + power->direction = NIOS_PIO_OUT; + atasel->direction = NIOS_PIO_OUT; + + /* Check for presence of card */ + if (present->data) + return 1; + printf ("Ok\n"); + + /* Finish setup */ + power->data = 1; /* Turn on power FET */ + atasel->data = 0; /* Put in ATA mode */ + + return 0; +} +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ diff --git a/board/altera/dk1c20/flash.c b/board/altera/dk1c20/flash.c new file mode 100644 index 0000000..1f344dd --- /dev/null +++ b/board/altera/dk1c20/flash.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +/* + * include common flash code (for altera boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------*/ +#define BANKSZ CFG_FLASH_SIZE +#define SECTSZ (64 * 1024) +#define USERFLASH (2 * 1024 * 1024) /* bottom 2 MB for user */ + +/*----------------------------------------------------------------------*/ +unsigned long flash_init (void) +{ + int i; + unsigned long addr; + flash_info_t *fli = &flash_info[0]; + + fli->size = BANKSZ; + fli->sector_count = CFG_MAX_FLASH_SECT; + fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; + + addr = CFG_FLASH_BASE; + for (i = 0; i < fli->sector_count; ++i) { + fli->start[i] = addr; + addr += SECTSZ; + + /* Protect all but 2 MByte user area */ + if (addr < (CFG_FLASH_BASE + USERFLASH)) + fli->protect[i] = 0; + else + fli->protect[i] = 1; + } + + return (BANKSZ); +} diff --git a/board/altera/dk1c20/misc.c b/board/altera/dk1c20/misc.c new file mode 100644 index 0000000..f25cdeb --- /dev/null +++ b/board/altera/dk1c20/misc.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * board/altera/dk1s10/misc.c + * + * miscellaneous board interfaces / drivers + */ + +#include + +#if defined(CONFIG_SEVENSEG) +#include "../common/sevenseg.h" +#include "../common/sevenseg.c" +#endif diff --git a/board/altera/dk1c20/u-boot.lds b/board/altera/dk1c20/u-boot.lds new file mode 100644 index 0000000..8b01f45 --- /dev/null +++ b/board/altera/dk1c20/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-nios") +OUTPUT_ARCH(nios) +ENTRY(_start) + +SECTIONS +{ + .text : + { + cpu/nios/start.o (.text) + *(.text) + } + __text_end = .; + + . = ALIGN(4); + .rodata : + { + *(.rodata) + } + __rodata_end = .; + + . = ALIGN(4); + .data : + { + *(.data) + } + . = ALIGN(4); + __data_end = .; + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + __bss_start = .; + . = ALIGN(4); + .bss : + { + *(.bss) + } + . = ALIGN(4); + __bss_end = .; +} diff --git a/board/altera/dk1c20/vectors.S b/board/altera/dk1c20/vectors.S new file mode 100644 index 0000000..c83c0e7 --- /dev/null +++ b/board/altera/dk1c20/vectors.S @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +/************************************************************************* + * Exception Vector Table + * + * This could have gone in the cpu soure tree, but the whole point of + * Nios is customization -- and polluting the cpu source tree with + * board-specific ifdef's really defeats the purpose, no? With this in + * the board-specific tree, each board has the freedom to organize + * vectors/traps, etc anyway it wants. The init code copies this table + * to the proper location. + * + * Each board can do what it likes here. But there are four "standard" + * handlers availble: + * + * _cwp_lolimit -Handles register window underflows. + * _cwp_hilimit -Handles register window overflows. + * _timebase_int -Increments the timebase. + * _brkpt_hw_int -Hardware breakpoint handler. + * _brkpt_sw_int -Software breakpoint handler. + * _def_xhandler -Default exception handler. + * + * _timebase_int handles a Nios Timer interrupt and increments the + * timestamp used for the get_timer(), reset_timer(), etc. routines. It + * expects the timer to be configured like the standard-32 low priority + * timer. + * + * _def_xhandler dispatches exceptions/traps via the external_interrupt() + * routine. This lets you use the irq_install_handler() and handle your + * interrupts/traps with code written in C. + ************************************************************************/ + + .data + .global _vectors + .align 4 +_vectors: + + .long _def_xhandler@h /* Vector 0 - NMI */ + .long _cwp_lolimit@h /* Vector 1 - underflow */ + .long _cwp_hilimit@h /* Vector 2 - overflow */ + .long _brkpt_hw_int@h /* Vector 3 - Breakpoint */ + .long _brkpt_sw_int@h /* Vector 4 - Single step*/ + .long _def_xhandler@h /* Vector 5 - GNUPro debug */ + .long _def_xhandler@h /* Vector 6 - future reserved */ + .long _def_xhandler@h /* Vector 7 - future reserved */ + .long _def_xhandler@h /* Vector 8 - future reserved */ + .long _def_xhandler@h /* Vector 9 - future reserved */ + .long _def_xhandler@h /* Vector 10 - future reserved */ + .long _def_xhandler@h /* Vector 11 - future reserved */ + .long _def_xhandler@h /* Vector 12 - future reserved */ + .long _def_xhandler@h /* Vector 13 - future reserved */ + .long _def_xhandler@h /* Vector 14 - future reserved */ + .long _def_xhandler@h /* Vector 15 - future reserved */ + .long _def_xhandler@h /* Vector 16 */ + .long _def_xhandler@h /* Vector 17 */ + .long _def_xhandler@h /* Vector 18 */ + .long _def_xhandler@h /* Vector 19 */ + .long _def_xhandler@h /* Vector 20 */ + .long _def_xhandler@h /* Vector 21 */ + .long _def_xhandler@h /* Vector 22 */ + .long _def_xhandler@h /* Vector 23 */ + .long _def_xhandler@h /* Vector 24 */ + .long _def_xhandler@h /* Vector 25 */ + .long _def_xhandler@h /* Vector 26 */ + .long _def_xhandler@h /* Vector 27 */ + .long _def_xhandler@h /* Vector 28 */ + .long _def_xhandler@h /* Vector 29 */ + .long _def_xhandler@h /* Vector 30 */ + .long _def_xhandler@h /* Vector 31 */ + .long _def_xhandler@h /* Vector 32 */ + .long _def_xhandler@h /* Vector 33 */ + .long _def_xhandler@h /* Vector 34 */ + .long _def_xhandler@h /* Vector 35 */ + .long _def_xhandler@h /* Vector 36 */ + .long _def_xhandler@h /* Vector 37 */ + .long _def_xhandler@h /* Vector 38 */ + .long _def_xhandler@h /* Vector 39 */ + .long _def_xhandler@h /* Vector 40 */ + .long _def_xhandler@h /* Vector 41 */ + .long _def_xhandler@h /* Vector 42 */ + .long _def_xhandler@h /* Vector 43 */ + .long _def_xhandler@h /* Vector 44 */ + .long _def_xhandler@h /* Vector 45 */ + .long _def_xhandler@h /* Vector 46 */ + .long _def_xhandler@h /* Vector 47 */ + .long _def_xhandler@h /* Vector 48 */ + .long _def_xhandler@h /* Vector 49 */ + .long _timebase_int@h /* Vector 50 - lopri timer*/ + .long _def_xhandler@h /* Vector 51 */ + .long _def_xhandler@h /* Vector 52 */ + .long _def_xhandler@h /* Vector 53 */ + .long _def_xhandler@h /* Vector 54 */ + .long _def_xhandler@h /* Vector 55 */ + .long _def_xhandler@h /* Vector 56 */ + .long _def_xhandler@h /* Vector 57 */ + .long _def_xhandler@h /* Vector 58 */ + .long _def_xhandler@h /* Vector 59 */ + .long _def_xhandler@h /* Vector 60 */ + .long _def_xhandler@h /* Vector 61 */ + .long _def_xhandler@h /* Vector 62 */ + .long _def_xhandler@h /* Vector 63 */ diff --git a/board/altera/dk1s10/Makefile b/board/altera/dk1s10/Makefile new file mode 100644 index 0000000..9182a4e --- /dev/null +++ b/board/altera/dk1s10/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o misc.o + +SOBJS = vectors.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/altera/dk1s10/config.mk b/board/altera/dk1s10/config.mk new file mode 100644 index 0000000..d200715 --- /dev/null +++ b/board/altera/dk1s10/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2003 +# Psyent Corporation +# Scott McNutt +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x018c0000 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/altera/dk1s10/dk1s10.c b/board/altera/dk1s10/dk1s10.c new file mode 100644 index 0000000..c45e7f1 --- /dev/null +++ b/board/altera/dk1s10/dk1s10.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_SEVENSEG) +#include "../common/sevenseg.h" +#endif + +void _default_hdlr (void) +{ + printf ("default_hdlr\n"); +} + +int board_early_init_f (void) +{ +#if defined(CONFIG_SEVENSEG) + /* init seven segment led display and switch off */ + sevenseg_set(SEVENSEG_OFF); +#endif + return 0; +} + +int checkboard (void) +{ + puts ("Board: Altera Nios 1S10 Development Kit\n"); +#if defined(CONFIG_NIOS_SAFE_32) + puts ("Conf.: Altera Safe 32 (safe_32)\n"); +#elif defined(CONFIG_NIOS_STANDARD_32) + puts ("Conf.: Altera Standard 32 (standard_32)\n"); +#elif defined(CONFIG_NIOS_MTX_LDK_20) + puts ("Conf.: Microtronix LDK 2.0 (LDK2)\n"); +#endif + + return 0; +} + +long int initdram (int board_type) +{ + return (0); +} diff --git a/board/altera/dk1s10/flash.c b/board/altera/dk1s10/flash.c new file mode 100644 index 0000000..5c70933 --- /dev/null +++ b/board/altera/dk1s10/flash.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +/* + * include common flash code (for altera boards) + */ +#include "../common/flash.c" + +/*---------------------------------------------------------------------*/ +#define BANKSZ (8 * 1024 * 1024) +#define SECTSZ (64 * 1024) +#define USERFLASH (2 * 1024 * 1024) /* bottom 2 MB for user */ + +/*---------------------------------------------------------------------*/ +unsigned long flash_init (void) +{ + int i; + unsigned long addr; + flash_info_t *fli = &flash_info[0]; + + fli->size = BANKSZ; + fli->sector_count = CFG_MAX_FLASH_SECT; + fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; + + addr = CFG_FLASH_BASE; + for (i = 0; i < fli->sector_count; ++i) { + fli->start[i] = addr; + addr += SECTSZ; + + /* Protect all but 2 MByte user area */ + if (addr < (CFG_FLASH_BASE + USERFLASH)) + fli->protect[i] = 0; + else + fli->protect[i] = 1; + } + + return (BANKSZ); +} diff --git a/board/altera/dk1s10/misc.c b/board/altera/dk1s10/misc.c new file mode 100644 index 0000000..f25cdeb --- /dev/null +++ b/board/altera/dk1s10/misc.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * board/altera/dk1s10/misc.c + * + * miscellaneous board interfaces / drivers + */ + +#include + +#if defined(CONFIG_SEVENSEG) +#include "../common/sevenseg.h" +#include "../common/sevenseg.c" +#endif diff --git a/board/altera/dk1s10/u-boot.lds b/board/altera/dk1s10/u-boot.lds new file mode 100644 index 0000000..8b01f45 --- /dev/null +++ b/board/altera/dk1s10/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-nios") +OUTPUT_ARCH(nios) +ENTRY(_start) + +SECTIONS +{ + .text : + { + cpu/nios/start.o (.text) + *(.text) + } + __text_end = .; + + . = ALIGN(4); + .rodata : + { + *(.rodata) + } + __rodata_end = .; + + . = ALIGN(4); + .data : + { + *(.data) + } + . = ALIGN(4); + __data_end = .; + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + __bss_start = .; + . = ALIGN(4); + .bss : + { + *(.bss) + } + . = ALIGN(4); + __bss_end = .; +} diff --git a/board/altera/dk1s10/vectors.S b/board/altera/dk1s10/vectors.S new file mode 100644 index 0000000..2f44875 --- /dev/null +++ b/board/altera/dk1s10/vectors.S @@ -0,0 +1,139 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + +/************************************************************************* + * Exception Vector Table + * + * This could have gone in the cpu soure tree, but the whole point of + * Nios is customization -- and polluting the cpu source tree with + * board-specific ifdef's really defeats the purpose, no? With this in + * the board-specific tree, each board has the freedom to organize + * vectors/traps, etc anyway it wants. The init code copies this table + * to the proper location. + * + * Each board can do what it likes here. But there are four "standard" + * handlers availble: + * + * _cwp_lolimit -Handles register window underflows. + * _cwp_hilimit -Handles register window overflows. + * _timebase_int -Increments the timebase. + * _def_xhandler -Default exception handler. + * + * _timebase_int handles a Nios Timer interrupt and increments the + * timestamp used for the get_timer(), reset_timer(), etc. routines. It + * expects the timer to be configured like the standard-32 low priority + * timer. + * + * _def_xhandler dispatches exceptions/traps via the external_interrupt() + * routine. This lets you use the irq_install_handler() and handle your + * interrupts/traps with code written in C. + ************************************************************************/ + + .data + .global _vectors + .align 4 +_vectors: + +#if defined(CFG_NIOS_CPU_OCI_BASE) + /* OCI does the reset job */ + .long _def_xhandler@h /* Vector 0 - NMI / Reset */ +#else + /* there is no OCI, so we have to do a direct reset jump here */ + .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ +#endif + .long _cwp_lolimit@h /* Vector 1 - underflow */ + .long _cwp_hilimit@h /* Vector 2 - overflow */ + + .long _def_xhandler@h /* Vector 3 - GNUPro debug */ + .long _def_xhandler@h /* Vector 4 - GNUPro debug */ + .long _def_xhandler@h /* Vector 5 - GNUPro debug */ + .long _def_xhandler@h /* Vector 6 - future reserved */ + .long _def_xhandler@h /* Vector 7 - future reserved */ + .long _def_xhandler@h /* Vector 8 - future reserved */ + .long _def_xhandler@h /* Vector 9 - future reserved */ + .long _def_xhandler@h /* Vector 10 - future reserved */ + .long _def_xhandler@h /* Vector 11 - future reserved */ + .long _def_xhandler@h /* Vector 12 - future reserved */ + .long _def_xhandler@h /* Vector 13 - future reserved */ + .long _def_xhandler@h /* Vector 14 - future reserved */ + .long _def_xhandler@h /* Vector 15 - future reserved */ +#if (CFG_NIOS_TMRIRQ == 16) + .long _timebase_int@h /* Vector 16 - lopri timer*/ +#else + .long _def_xhandler@h /* Vector 16 */ +#endif + .long _def_xhandler@h /* Vector 17 */ + .long _def_xhandler@h /* Vector 18 */ + .long _def_xhandler@h /* Vector 19 */ + .long _def_xhandler@h /* Vector 20 */ + .long _def_xhandler@h /* Vector 21 */ + .long _def_xhandler@h /* Vector 22 */ + .long _def_xhandler@h /* Vector 23 */ + .long _def_xhandler@h /* Vector 24 */ + .long _def_xhandler@h /* Vector 25 */ + .long _def_xhandler@h /* Vector 26 */ + .long _def_xhandler@h /* Vector 27 */ + .long _def_xhandler@h /* Vector 28 */ + .long _def_xhandler@h /* Vector 29 */ + .long _def_xhandler@h /* Vector 30 */ + .long _def_xhandler@h /* Vector 31 */ + .long _def_xhandler@h /* Vector 32 */ + .long _def_xhandler@h /* Vector 33 */ + .long _def_xhandler@h /* Vector 34 */ + .long _def_xhandler@h /* Vector 35 */ + .long _def_xhandler@h /* Vector 36 */ + .long _def_xhandler@h /* Vector 37 */ + .long _def_xhandler@h /* Vector 38 */ + .long _def_xhandler@h /* Vector 39 */ + .long _def_xhandler@h /* Vector 40 */ + .long _def_xhandler@h /* Vector 41 */ + .long _def_xhandler@h /* Vector 42 */ + .long _def_xhandler@h /* Vector 43 */ + .long _def_xhandler@h /* Vector 44 */ + .long _def_xhandler@h /* Vector 45 */ + .long _def_xhandler@h /* Vector 46 */ + .long _def_xhandler@h /* Vector 47 */ + .long _def_xhandler@h /* Vector 48 */ + .long _def_xhandler@h /* Vector 49 */ +#if (CFG_NIOS_TMRIRQ == 50) + .long _timebase_int@h /* Vector 50 - lopri timer*/ +#else + .long _def_xhandler@h /* Vector 50 */ +#endif + .long _def_xhandler@h /* Vector 51 */ + .long _def_xhandler@h /* Vector 52 */ + .long _def_xhandler@h /* Vector 53 */ + .long _def_xhandler@h /* Vector 54 */ + .long _def_xhandler@h /* Vector 55 */ + .long _def_xhandler@h /* Vector 56 */ + .long _def_xhandler@h /* Vector 57 */ + .long _def_xhandler@h /* Vector 58 */ + .long _def_xhandler@h /* Vector 59 */ + .long _def_xhandler@h /* Vector 60 */ + .long _def_xhandler@h /* Vector 61 */ + .long _def_xhandler@h /* Vector 62 */ + .long _def_xhandler@h /* Vector 63 */ diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile new file mode 100644 index 0000000..5654f91 --- /dev/null +++ b/board/amcc/bamboo/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +OBJS += flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c new file mode 100644 index 0000000..803995a --- /dev/null +++ b/board/amcc/bamboo/bamboo.c @@ -0,0 +1,2089 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "bamboo.h" + +void ext_bus_cntlr_init(void); +void configure_ppc440ep_pins(void); +int is_nand_selected(void); + +unsigned char cfg_simulate_spd_eeprom[128]; + +gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; +#if 0 +{ /* GPIO Alternate1 Alternate2 Alternate3 */ + { + /* GPIO Core 0 */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */ + { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */ + }, + { + /* GPIO Core 1 */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */ + } +}; +#endif + +/*----------------------------------------------------------------------------+ + | EBC Devices Characteristics + | Peripheral Bank Access Parameters - EBC0_BnAP + | Peripheral Bank Configuration Register - EBC0_BnCR + +----------------------------------------------------------------------------*/ +/* Small Flash */ +#define EBC0_BNAP_SMALL_FLASH \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(6) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(3) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ + EBC0_BNAP_PEN_DISABLED + +#define EBC0_BNCR_SMALL_FLASH_CS0 \ + EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_8BIT + +#define EBC0_BNCR_SMALL_FLASH_CS4 \ + EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_8BIT + +/* Large Flash or SRAM */ +#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(8) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(1) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_RW | \ + EBC0_BNAP_PEN_DISABLED + +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ + EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_16BIT + + +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ + EBC0_BNCR_BAS_ENCODE(0x87800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_16BIT + +/* NVRAM - FPGA */ +#define EBC0_BNAP_NVRAM_FPGA \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(9) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ + EBC0_BNAP_PEN_DISABLED + +#define EBC0_BNCR_NVRAM_FPGA_CS5 \ + EBC0_BNCR_BAS_ENCODE(0x80000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_8BIT + +/* Nand Flash */ +#define EBC0_BNAP_NAND_FLASH \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(3) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(0) | \ + EBC0_BNAP_WBN_ENCODE(0) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_NOT_DELAYED | \ + EBC0_BNAP_BEM_RW | \ + EBC0_BNAP_PEN_DISABLED + + +#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000 + +/* NAND0 */ +#define EBC0_BNCR_NAND_FLASH_CS1 \ + EBC0_BNCR_BAS_ENCODE(0x90000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_32BIT +/* NAND1 - Bank2 */ +#define EBC0_BNCR_NAND_FLASH_CS2 \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_32BIT + +/* NAND1 - Bank3 */ +#define EBC0_BNCR_NAND_FLASH_CS3 \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_32BIT + +int board_early_init_f(void) +{ + ext_bus_cntlr_init(); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + out32(GPIO0_OSRL, 0x00000400); + out32(GPIO0_OSRH, 0x00000000); + out32(GPIO0_TSRL, 0x00000400); + out32(GPIO0_TSRH, 0x00000000); + out32(GPIO0_ISR1L, 0x00000000); + out32(GPIO0_ISR1H, 0x00000000); + out32(GPIO0_ISR2L, 0x00000000); + out32(GPIO0_ISR2H, 0x00000000); + out32(GPIO0_ISR3L, 0x00000000); + out32(GPIO0_ISR3H, 0x00000000); + + out32(GPIO1_OSRL, 0x0C380000); + out32(GPIO1_OSRH, 0x00000000); + out32(GPIO1_TSRL, 0x0C380000); + out32(GPIO1_TSRH, 0x00000000); + out32(GPIO1_ISR1L, 0x0FC30000); + out32(GPIO1_ISR1H, 0x00000000); + out32(GPIO1_ISR2L, 0x0C010000); + out32(GPIO1_ISR2H, 0x00000000); + out32(GPIO1_ISR3L, 0x01400000); + out32(GPIO1_ISR3H, 0x00000000); + + configure_ppc440ep_pins(); + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +/*----------------------------------------------------------------------------+ + | nand_reset. + | Reset Nand flash + | This routine will abort previous cmd + +----------------------------------------------------------------------------*/ +int nand_reset(ulong addr) +{ + int wait=0, stat=0; + + out8(addr + NAND_CMD_REG, NAND0_CMD_RESET); + out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS); + + while ((stat != 0xc0) && (wait != 0xffff)) { + stat = in8(addr + NAND_DATA_REG); + wait++; + } + + if (stat == 0xc0) { + return 0; + } else { + printf("NAND Reset timeout.\n"); + return -1; + } +} + +void board_nand_set_device(int cs, ulong addr) +{ + /* Set NandFlash Core Configuration Register */ + out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24)); + + switch (cs) { + case 1: + /* ------- + * NAND0 + * ------- + * K9F1208U0A : 4 addr cyc, 1 col + 3 Row + * Set NDF1CR - Enable External CS1 in NAND FLASH controller + */ + out32(addr + NAND_CR1_REG, 0x80002222); + break; + + case 2: + /* ------- + * NAND1 + * ------- + * K9K2G0B : 5 addr cyc, 2 col + 3 Row + * Set NDF2CR : Enable External CS2 in NAND FLASH controller + */ + out32(addr + NAND_CR2_REG, 0xC0007777); + break; + } + + /* Perform Reset Command */ + if (nand_reset(addr) != 0) + return; +} + +void nand_init(void) +{ + board_nand_set_device(1, CFG_NAND_ADDR); + + nand_probe(CFG_NAND_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } + +#if 0 /* NAND1 not supported yet */ + board_nand_set_device(2, CFG_NAND2_ADDR); + + nand_probe(CFG_NAND2_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +#endif +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Bamboo - AMCC PPC440EP Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * + * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM) + * + * Fixed memory is composed of : + * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, + * 13 row add bits, 10 column add bits (but 12 row used only). + * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, + * 12 row add bits, 10 column add bits. + * Prepare a subset (only the used ones) of SPD data + * + * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of + * the corresponding bank is divided by 2 due to number of Row addresses + * 12 in the ECC module + * + * Assumes: 64 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +static void init_spd_array(void) +{ + cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */ + cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */ + +#ifdef CONFIG_DDR_ECC + cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */ + cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */ + cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */ +#else + cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */ + cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */ + cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */ +#endif + + cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */ + cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */ + cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */ + cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */ + cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/ + cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */ + cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */ + cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */ + cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */ + cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */ + + cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */ + + cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */ + + cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ + cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */ + cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */ + cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */ +} + +long int initdram (int board_type) +{ + long dram_size = 0; + + /* + * First write simulated values in eeprom array for onboard bank 0 + */ + init_spd_array(); + + dram_size = spd_sdram (0); + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440 EP PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Bamboo is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ + +/*----------------------------------------------------------------------------+ + | is_powerpc440ep_pass1. + +----------------------------------------------------------------------------*/ +int is_powerpc440ep_pass1(void) +{ + unsigned long pvr; + + pvr = get_pvr(); + + if (pvr == PVR_POWERPC_440EP_PASS1) + return TRUE; + else if (pvr == PVR_POWERPC_440EP_PASS2) + return FALSE; + else { + printf("brdutil error 3\n"); + for (;;) + ; + } + + return(FALSE); +} + +/*----------------------------------------------------------------------------+ + | is_nand_selected. + +----------------------------------------------------------------------------*/ +int is_nand_selected(void) +{ +#ifdef CONFIG_BAMBOO_NAND + return TRUE; +#else + return FALSE; +#endif +} + +/*----------------------------------------------------------------------------+ + | config_on_ebc_cs4_is_small_flash => from EPLD + +----------------------------------------------------------------------------*/ +unsigned char config_on_ebc_cs4_is_small_flash(void) +{ + /* Not implemented yet => returns constant value */ + return TRUE; +} + +/*----------------------------------------------------------------------------+ + | Ext_bus_cntlr_init. + | Initialize the external bus controller + +----------------------------------------------------------------------------*/ +void ext_bus_cntlr_init(void) +{ + unsigned long sdr0_pstrp0, sdr0_sdstp1; + unsigned long bootstrap_settings, boot_selection, ebc_boot_size; + int computed_boot_device = BOOT_DEVICE_UNKNOWN; + unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0; + unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0; + unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0; + unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0; + unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0; + + + /*-------------------------------------------------------------------------+ + | + | PART 1 : Initialize EBC Bank 5 + | ============================== + | Bank5 is always associated to the NVRAM/EPLD. + | It has to be initialized prior to other banks settings computation since + | some board registers values may be needed + | + +-------------------------------------------------------------------------*/ + /* NVRAM - FPGA */ + mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA); + mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5); + + /*-------------------------------------------------------------------------+ + | + | PART 2 : Determine which boot device was selected + | ========================================= + | + | Read Pin Strap Register in PPC440EP + | In case of boot from IIC, read Serial Device Strap Register1 + | + | Result can either be : + | - Boot from EBC 8bits => SMALL FLASH + | - Boot from EBC 16bits => Large Flash or SRAM + | - Boot from NAND Flash + | - Boot from PCI + | + +-------------------------------------------------------------------------*/ + /* Read Pin Strap Register in PPC440EP */ + mfsdr(sdr_pstrp0, sdr0_pstrp0); + bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK; + + /*-------------------------------------------------------------------------+ + | PPC440EP Pass1 + +-------------------------------------------------------------------------*/ + if (is_powerpc440ep_pass1() == TRUE) { + switch(bootstrap_settings) { + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: + /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ + /* Boot from Small Flash */ + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: + /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */ + /* Boot from PCI */ + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: + /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */ + /* Boot from Nand Flash */ + computed_boot_device = BOOT_FROM_NAND_FLASH0; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: + /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */ + /* Boot from Small Flash */ + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + + case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: + case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: + /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ + /* Read Serial Device Strap Register1 in PPC440EP */ + mfsdr(sdr_sdstp1, sdr0_sdstp1); + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; + + switch(boot_selection) { + case SDR0_SDSTP1_BOOT_SEL_EBC: + switch(ebc_boot_size) { + case SDR0_SDSTP1_EBC_ROM_BS_16BIT: + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; + break; + case SDR0_SDSTP1_EBC_ROM_BS_8BIT: + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + } + break; + + case SDR0_SDSTP1_BOOT_SEL_PCI: + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_SDSTP1_BOOT_SEL_NDFC: + computed_boot_device = BOOT_FROM_NAND_FLASH0; + break; + } + break; + } + } + + /*-------------------------------------------------------------------------+ + | PPC440EP Pass2 + +-------------------------------------------------------------------------*/ + else { + switch(bootstrap_settings) { + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: + /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ + /* Boot from Small Flash */ + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: + /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */ + /* Boot from PCI */ + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: + /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */ + /* Boot from Nand Flash */ + computed_boot_device = BOOT_FROM_NAND_FLASH0; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: + /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */ + /* Boot from Large Flash or SRAM */ + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: + /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */ + /* Boot from Large Flash or SRAM */ + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6: + /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */ + /* Boot from PCI */ + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: + case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: + /* Default Strap Settings 5-7 */ + /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ + /* Read Serial Device Strap Register1 in PPC440EP */ + mfsdr(sdr_sdstp1, sdr0_sdstp1); + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; + + switch(boot_selection) { + case SDR0_SDSTP1_BOOT_SEL_EBC: + switch(ebc_boot_size) { + case SDR0_SDSTP1_EBC_ROM_BS_16BIT: + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; + break; + case SDR0_SDSTP1_EBC_ROM_BS_8BIT: + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + } + break; + + case SDR0_SDSTP1_BOOT_SEL_PCI: + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_SDSTP1_BOOT_SEL_NDFC: + computed_boot_device = BOOT_FROM_NAND_FLASH0; + break; + } + break; + } + } + + /*-------------------------------------------------------------------------+ + | + | PART 3 : Compute EBC settings depending on selected boot device + | ====== ====================================================== + | + | Resulting EBC init will be among following configurations : + | + | - Boot from EBC 8bits => boot from SMALL FLASH selected + | EBC-CS0 = Small Flash + | EBC-CS1,2,3 = NAND Flash or + | Exp.Slot depending on Soft Config + | EBC-CS4 = SRAM/Large Flash or + | Large Flash/SRAM depending on jumpers + | EBC-CS5 = NVRAM / EPLD + | + | - Boot from EBC 16bits => boot from Large Flash or SRAM selected + | EBC-CS0 = SRAM/Large Flash or + | Large Flash/SRAM depending on jumpers + | EBC-CS1,2,3 = NAND Flash or + | Exp.Slot depending on Software Configuration + | EBC-CS4 = Small Flash + | EBC-CS5 = NVRAM / EPLD + | + | - Boot from NAND Flash + | EBC-CS0 = NAND Flash0 + | EBC-CS1,2,3 = NAND Flash1 + | EBC-CS4 = SRAM/Large Flash or + | Large Flash/SRAM depending on jumpers + | EBC-CS5 = NVRAM / EPLD + | + | - Boot from PCI + | EBC-CS0 = ... + | EBC-CS1,2,3 = NAND Flash or + | Exp.Slot depending on Software Configuration + | EBC-CS4 = SRAM/Large Flash or + | Large Flash/SRAM or + | Small Flash depending on jumpers + | EBC-CS5 = NVRAM / EPLD + | + +-------------------------------------------------------------------------*/ + + switch(computed_boot_device) { + /*------------------------------------------------------------------------- */ + case BOOT_FROM_SMALL_FLASH: + /*------------------------------------------------------------------------- */ + ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH; + ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0; + if ((is_nand_selected()) == TRUE) { + /* NAND Flash */ + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; + ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } else { + /* Expansion Slot */ + ebc0_cs1_bnap_value = 0; + ebc0_cs1_bncr_value = 0; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } + ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; + ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; + + break; + + /*------------------------------------------------------------------------- */ + case BOOT_FROM_LARGE_FLASH_OR_SRAM: + /*------------------------------------------------------------------------- */ + ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; + ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0; + if ((is_nand_selected()) == TRUE) { + /* NAND Flash */ + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } else { + /* Expansion Slot */ + ebc0_cs1_bnap_value = 0; + ebc0_cs1_bncr_value = 0; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } + ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; + ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; + + break; + + /*------------------------------------------------------------------------- */ + case BOOT_FROM_NAND_FLASH0: + /*------------------------------------------------------------------------- */ + ebc0_cs0_bnap_value = 0; + ebc0_cs0_bncr_value = 0; + + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + + /* Large Flash or SRAM */ + ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; + ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; + + break; + + /*------------------------------------------------------------------------- */ + case BOOT_FROM_PCI: + /*------------------------------------------------------------------------- */ + ebc0_cs0_bnap_value = 0; + ebc0_cs0_bncr_value = 0; + + if ((is_nand_selected()) == TRUE) { + /* NAND Flash */ + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } else { + /* Expansion Slot */ + ebc0_cs1_bnap_value = 0; + ebc0_cs1_bncr_value = 0; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } + + if ((config_on_ebc_cs4_is_small_flash()) == TRUE) { + /* Small Flash */ + ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; + ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; + } else { + /* Large Flash or SRAM */ + ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; + ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; + } + + break; + + /*------------------------------------------------------------------------- */ + case BOOT_DEVICE_UNKNOWN: + /*------------------------------------------------------------------------- */ + /* Error */ + break; + + } + + + /*-------------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN | + EBC0_CFG_PTD_ENABLED | + EBC0_CFG_RTC_2048PERCLK | + EBC0_CFG_EMPL_LOW | + EBC0_CFG_EMPH_LOW | + EBC0_CFG_CSTC_DRIVEN | + EBC0_CFG_BPF_ONEDW | + EBC0_CFG_EMS_8BIT | + EBC0_CFG_PME_DISABLED | + EBC0_CFG_PMT_ENCODE(0) ); + + /*-------------------------------------------------------------------------+ + | Initialize EBC Bank 0-4 + +-------------------------------------------------------------------------*/ + /* EBC Bank0 */ + mtebc(pb0ap, ebc0_cs0_bnap_value); + mtebc(pb0cr, ebc0_cs0_bncr_value); + /* EBC Bank1 */ + mtebc(pb1ap, ebc0_cs1_bnap_value); + mtebc(pb1cr, ebc0_cs1_bncr_value); + /* EBC Bank2 */ + mtebc(pb2ap, ebc0_cs2_bnap_value); + mtebc(pb2cr, ebc0_cs2_bncr_value); + /* EBC Bank3 */ + mtebc(pb3ap, ebc0_cs3_bnap_value); + mtebc(pb3cr, ebc0_cs3_bncr_value); + /* EBC Bank4 */ + mtebc(pb4ap, ebc0_cs4_bnap_value); + mtebc(pb4cr, ebc0_cs4_bncr_value); + + return; +} + + +/*----------------------------------------------------------------------------+ + | get_uart_configuration. + +----------------------------------------------------------------------------*/ +uart_config_nb_t get_uart_configuration(void) +{ + return (L4); +} + +/*----------------------------------------------------------------------------+ + | set_phy_configuration_through_fpga => to EPLD + +----------------------------------------------------------------------------*/ +void set_phy_configuration_through_fpga(zmii_config_t config) +{ + + unsigned long fpga_selection_reg; + + fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK; + + switch(config) + { + case ZMII_CONFIGURATION_IS_MII: + fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII; + break; + case ZMII_CONFIGURATION_IS_RMII: + fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII; + break; + case ZMII_CONFIGURATION_IS_SMII: + fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII; + break; + case ZMII_CONFIGURATION_UNKNOWN: + default: + break; + } + out8(FPGA_SELECTION_1_REG,fpga_selection_reg); + +} + +/*----------------------------------------------------------------------------+ + | scp_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void scp_selection_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; + fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | iic1_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void iic1_selection_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; + fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | dma_a_b_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void dma_a_b_selection_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | dma_a_b_unselect_in_fpga. + +----------------------------------------------------------------------------*/ +void dma_a_b_unselect_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | dma_c_d_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void dma_c_d_selection_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | dma_c_d_unselect_in_fpga. + +----------------------------------------------------------------------------*/ +void dma_c_d_unselect_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | usb2_device_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void usb2_device_selection_in_fpga(void) +{ + unsigned long fpga_selection_1_reg; + + fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL; + out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); +} + +/*----------------------------------------------------------------------------+ + | usb2_device_reset_through_fpga. + +----------------------------------------------------------------------------*/ +void usb2_device_reset_through_fpga(void) +{ + /* Perform soft Reset pulse */ + unsigned long fpga_reset_reg; + int i; + + fpga_reset_reg = in8(FPGA_RESET_REG); + out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV); + for (i=0; i<500; i++) + udelay(1000); + out8(FPGA_RESET_REG,fpga_reset_reg); +} + +/*----------------------------------------------------------------------------+ + | usb2_host_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void usb2_host_selection_in_fpga(void) +{ + unsigned long fpga_selection_1_reg; + + fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL; + out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); +} + +/*----------------------------------------------------------------------------+ + | ndfc_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void ndfc_selection_in_fpga(void) +{ + unsigned long fpga_selection_1_reg; + + fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK; + fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1; + fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; + out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); +} + +/*----------------------------------------------------------------------------+ + | uart_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void uart_selection_in_fpga(uart_config_nb_t uart_config) +{ + /* FPGA register */ + unsigned char fpga_selection_3_reg; + + /* Read FPGA Reagister */ + fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG); + + switch (uart_config) + { + case L1: + /* ----------------------------------------------------------------------- */ + /* L1 configuration: UART0 = 8 pins */ + /* ----------------------------------------------------------------------- */ + /* Configure FPGA */ + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1; + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); + + break; + + case L2: + /* ----------------------------------------------------------------------- */ + /* L2 configuration: UART0 = 4 pins */ + /* UART1 = 4 pins */ + /* ----------------------------------------------------------------------- */ + /* Configure FPGA */ + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2; + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); + + break; + + case L3: + /* ----------------------------------------------------------------------- */ + /* L3 configuration: UART0 = 4 pins */ + /* UART1 = 2 pins */ + /* UART2 = 2 pins */ + /* ----------------------------------------------------------------------- */ + /* Configure FPGA */ + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3; + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); + break; + + case L4: + /* Configure FPGA */ + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4; + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); + + break; + + default: + /* Unsupported UART configuration number */ + for (;;) + ; + break; + + } +} + + +/*----------------------------------------------------------------------------+ + | init_default_gpio + +----------------------------------------------------------------------------*/ +void init_default_gpio(void) +{ + int i; + + /* Init GPIO0 */ + for(i=0; i> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT2: + gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT3: + gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); + break; + } + } + if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) || + (gpio_tab[gpio_core][i].in_out == GPIO_BI )) + { + + switch (gpio_tab[gpio_core][i].alt_nb) + { + case GPIO_SEL: + break; + case GPIO_ALT1: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + case GPIO_ALT2: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + case GPIO_ALT3: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + } + } + } +} + +/*----------------------------------------------------------------------------+ + | force_bup_core_selection. + +----------------------------------------------------------------------------*/ +void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P) +{ + /* Pointer invalid */ + if (core_select_P == NULL) + { + printf("Configuration invalid pointer 1\n"); + for (;;) + ; + } + + /* L4 Selection */ + *(core_select_P+UART_CORE0) = CORE_SELECTED; + *(core_select_P+UART_CORE1) = CORE_SELECTED; + *(core_select_P+UART_CORE2) = CORE_SELECTED; + *(core_select_P+UART_CORE3) = CORE_SELECTED; + + /* RMII Selection */ + *(core_select_P+RMII_SEL) = CORE_SELECTED; + + /* External Interrupt 0-9 selection */ + *(core_select_P+UIC_0_3) = CORE_SELECTED; + *(core_select_P+UIC_4_9) = CORE_SELECTED; + + *(core_select_P+SCP_CORE) = CORE_SELECTED; + *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED; + *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED; + *(core_select_P+USB1_DEVICE) = CORE_SELECTED; + + if (is_nand_selected()) { + *(core_select_P+NAND_FLASH) = CORE_SELECTED; + } + + *config_val_P = CONFIG_IS_VALID; + +} + +/*----------------------------------------------------------------------------+ + | configure_ppc440ep_pins. + +----------------------------------------------------------------------------*/ +void configure_ppc440ep_pins(void) +{ + uart_config_nb_t uart_configuration; + config_validity_t config_val = CONFIG_IS_INVALID; + + /* Create Core Selection Table */ + core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] = + { + CORE_NOT_SELECTED, /* IIC_CORE, */ + CORE_NOT_SELECTED, /* SPC_CORE, */ + CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */ + CORE_NOT_SELECTED, /* UIC_4_9, */ + CORE_NOT_SELECTED, /* USB2_HOST, */ + CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */ + CORE_NOT_SELECTED, /* USB2_DEVICE, */ + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */ + CORE_NOT_SELECTED, /* USB1_DEVICE, */ + CORE_NOT_SELECTED, /* EBC_MASTER, */ + CORE_NOT_SELECTED, /* NAND_FLASH, */ + CORE_NOT_SELECTED, /* UART_CORE0, */ + CORE_NOT_SELECTED, /* UART_CORE1, */ + CORE_NOT_SELECTED, /* UART_CORE2, */ + CORE_NOT_SELECTED, /* UART_CORE3, */ + CORE_NOT_SELECTED, /* MII_SEL, */ + CORE_NOT_SELECTED, /* RMII_SEL, */ + CORE_NOT_SELECTED, /* SMII_SEL, */ + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */ + CORE_NOT_SELECTED, /* UIC_0_3 */ + CORE_NOT_SELECTED, /* USB1_HOST */ + CORE_NOT_SELECTED /* PCI_PATCH */ + }; + + + /* Table Default Initialisation + FPGA Access */ + init_default_gpio(); + set_chip_gpio_configuration(GPIO0); + set_chip_gpio_configuration(GPIO1); + + /* Update Table */ + force_bup_core_selection(ppc440ep_core_selection, &config_val); +#if 0 /* test-only */ + /* If we are running PIBS 1, force known configuration */ + update_core_selection_table(ppc440ep_core_selection, &config_val); +#endif + + /*----------------------------------------------------------------------------+ + | SDR + ios table update + fpga initialization + +----------------------------------------------------------------------------*/ + unsigned long sdr0_pfc1 = 0; + unsigned long sdr0_usb0 = 0; + unsigned long sdr0_mfr = 0; + + /* PCI Always selected */ + + /* I2C Selection */ + if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; + iic1_selection_in_fpga(); + } + + /* SCP Selection */ + if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; + scp_selection_in_fpga(); + } + + /* UIC 0:3 Selection */ + if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) + { + update_uic_0_3_irq_ios(); + dma_a_b_unselect_in_fpga(); + } + + /* UIC 4:9 Selection */ + if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; + update_uic_4_9_irq_ios(); + } + + /* DMA AB Selection */ + if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; + update_dma_a_b_ios(); + dma_a_b_selection_in_fpga(); + } + + /* DMA CD Selection */ + if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) + { + update_dma_c_d_ios(); + dma_c_d_selection_in_fpga(); + } + + /* EBC Master Selection */ + if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; + update_ebc_master_ios(); + } + + /* PCI Patch Enable */ + if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; + update_pci_patch_ios(); + } + + /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ + if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED) + { + /* Not Implemented in PowerPC 440EP Pass1-Pass2 */ + printf("Invalid configuration => USB2 Host selected\n"); + for (;;) + ; + /*usb2_host_selection_in_fpga(); */ + } + + /* USB2.0 Device Selection */ + if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) + { + update_usb2_device_ios(); + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; + + mfsdr(sdr_usb0, sdr0_usb0); + sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; + sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL; + mtsdr(sdr_usb0, sdr0_usb0); + + usb2_device_selection_in_fpga(); + } + + /* USB1.1 Device Selection */ + if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED) + { + mfsdr(sdr_usb0, sdr0_usb0); + sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; + sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL; + mtsdr(sdr_usb0, sdr0_usb0); + } + + /* USB1.1 Host Selection */ + if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED) + { + mfsdr(sdr_usb0, sdr0_usb0); + sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK; + sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE; + mtsdr(sdr_usb0, sdr0_usb0); + } + + /* NAND Flash Selection */ + if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) + { + update_ndfc_ios(); + + mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | + SDR0_CUST0_NDFC_ENABLE | + SDR0_CUST0_NDFC_BW_8_BIT | + SDR0_CUST0_NDFC_ARE_MASK | + SDR0_CUST0_CHIPSELGAT_EN1 | + SDR0_CUST0_CHIPSELGAT_EN2); + + ndfc_selection_in_fpga(); + } + else + { + /* Set Mux on EMAC */ + mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL); + } + + /* MII Selection */ + if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) + { + update_zii_ios(); + mfsdr(sdr_mfr, sdr0_mfr); + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; + mtsdr(sdr_mfr, sdr0_mfr); + + set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII); + } + + /* RMII Selection */ + if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) + { + update_zii_ios(); + mfsdr(sdr_mfr, sdr0_mfr); + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; + mtsdr(sdr_mfr, sdr0_mfr); + + set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII); + } + + /* SMII Selection */ + if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) + { + update_zii_ios(); + mfsdr(sdr_mfr, sdr0_mfr); + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; + mtsdr(sdr_mfr, sdr0_mfr); + + set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII); + } + + /* UART Selection */ + uart_configuration = get_uart_configuration(); + switch (uart_configuration) + { + case L1: /* L1 Selection */ + /* UART0 8 pins Only */ + /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS; + break; + case L2: /* L2 Selection */ + /* UART0 and UART1 4 pins */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + break; + case L3: /* L3 Selection */ + /* UART0 4 pins, UART1 and UART2 2 pins */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + break; + case L4: /* L4 Selection */ + /* UART0, UART1, UART2 and UART3 2 pins */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + break; + } + update_uart_ios(uart_configuration); + + /* UART Selection in all cases */ + uart_selection_in_fpga(uart_configuration); + + /* Packet Reject Function Available */ + if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED) + { + /* Set UPR Bit in SDR0_PFC1 Register */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE; + } + + /* Packet Reject Function Enable */ + if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) + { + mfsdr(sdr_mfr, sdr0_mfr); + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; + mtsdr(sdr_mfr, sdr0_mfr); + } + + /* Perform effective access to hardware */ + mtsdr(sdr_pfc1, sdr0_pfc1); + set_chip_gpio_configuration(GPIO0); + set_chip_gpio_configuration(GPIO1); + + /* USB2.0 Device Reset must be done after GPIO setting */ + if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) + usb2_device_reset_through_fpga(); + +} diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h new file mode 100644 index 0000000..5f5fcde --- /dev/null +++ b/board/amcc/bamboo/bamboo.h @@ -0,0 +1,401 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*----------------------------------------------------------------------------+ + | FPGA registers and bit definitions + +----------------------------------------------------------------------------*/ +/* + * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0. + * TLB initialization makes it correspond to logical address 0x80001FF0. + * => Done init_chip.s in bootlib + */ +#define FPGA_BASE_ADDR 0x80002000 + +/*----------------------------------------------------------------------------+ + | Board Jumpers Setting Register + | Board Settings provided by jumpers + +----------------------------------------------------------------------------*/ +#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3) +/* Boot from small flash */ +#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80 +/* Operational Flash versus SRAM position in Memory Map */ +#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40 +#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40 +#define FPGA_SET_REG_SRAM_ABOVE 0x00 +/* Boot From NAND Flash */ +#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40 +#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00 +/* On Board PCI Arbiter Select */ +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10 +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00 + +/*----------------------------------------------------------------------------+ + | Functions Selection Register 1 + +----------------------------------------------------------------------------*/ +#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4) +#define FPGA_SEL_1_REG_PHY_MASK 0xE0 +#define FPGA_SEL_1_REG_MII 0x80 +#define FPGA_SEL_1_REG_RMII 0x40 +#define FPGA_SEL_1_REG_SMII 0x20 +#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */ +#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */ +#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */ +#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */ +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */ +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */ + +/*----------------------------------------------------------------------------+ + | Functions Selection Register 2 + +----------------------------------------------------------------------------*/ +#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5) +#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */ +#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */ +#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */ +#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */ +#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */ +#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */ +#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */ + /* 1 = TC - output from 440EP */ +#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */ + /* 1 = TC (output from 440EP) */ +#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */ +#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */ +#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */ + +/*----------------------------------------------------------------------------+ + | Functions Selection Register 3 + +----------------------------------------------------------------------------*/ +#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6) +#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70 +#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */ +#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */ +#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */ + +/*----------------------------------------------------------------------------+ + | Soft Reset Register + +----------------------------------------------------------------------------*/ +#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7) +#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */ +#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */ +#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */ +#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */ +#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */ +#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */ + + +/*----------------------------------------------------------------------------+ +| SDR Configuration registers ++----------------------------------------------------------------------------*/ +/* Serial Device Strap Reg 0 */ +#define SDR0_SDSTP0 0x0020 +/* Serial Device Strap Reg 1 */ +#define SDR0_SDSTP1 0x0021 +/* Serial Device Strap Reg 2 */ +#define SDR0_SDSTP2 SDR0_STRP2 +/* Serial Device Strap Reg 3 */ +#define SDR0_SDSTP3 SDR0_STRP3 + +#define sdr_pstrp0 0x0040 + +#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */ +#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */ +#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */ +#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ + +#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */ +#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ +#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */ +#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */ + +/* Serial Device Enabled - Addr = 0xA8 */ +#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 +/* Serial Device Enabled - Addr = 0xA4 */ +#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 + +/* Pin Straps Reg */ +#define SDR0_PSTRP0 0x0040 +#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ + +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ + +/*----------------------------------------------------------------------------+ +| EBC Configuration Register - EBC0_CFG ++----------------------------------------------------------------------------*/ +/* External Bus Three-State Control */ +#define EBC0_CFG_EBTC_DRIVEN 0x80000000 +/* Device-Paced Time-out Disable */ +#define EBC0_CFG_PTD_ENABLED 0x00000000 +/* Ready Timeout Count */ +#define EBC0_CFG_RTC_MASK 0x38000000 +#define EBC0_CFG_RTC_16PERCLK 0x00000000 +#define EBC0_CFG_RTC_32PERCLK 0x08000000 +#define EBC0_CFG_RTC_64PERCLK 0x10000000 +#define EBC0_CFG_RTC_128PERCLK 0x18000000 +#define EBC0_CFG_RTC_256PERCLK 0x20000000 +#define EBC0_CFG_RTC_512PERCLK 0x28000000 +#define EBC0_CFG_RTC_1024PERCLK 0x30000000 +#define EBC0_CFG_RTC_2048PERCLK 0x38000000 +/* External Master Priority Low */ +#define EBC0_CFG_EMPL_LOW 0x00000000 +#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000 +#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000 +#define EBC0_CFG_EMPL_HIGH 0x06000000 +/* External Master Priority High */ +#define EBC0_CFG_EMPH_LOW 0x00000000 +#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000 +#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000 +#define EBC0_CFG_EMPH_HIGH 0x01800000 +/* Chip Select Three-State Control */ +#define EBC0_CFG_CSTC_DRIVEN 0x00400000 +/* Burst Prefetch */ +#define EBC0_CFG_BPF_ONEDW 0x00000000 +#define EBC0_CFG_BPF_TWODW 0x00100000 +#define EBC0_CFG_BPF_FOURDW 0x00200000 +/* External Master Size */ +#define EBC0_CFG_EMS_8BIT 0x00000000 +/* Power Management Enable */ +#define EBC0_CFG_PME_DISABLED 0x00000000 +#define EBC0_CFG_PME_ENABLED 0x00020000 +/* Power Management Timer */ +#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) + +/*----------------------------------------------------------------------------+ +| Peripheral Bank Configuration Register - EBC0_BnCR ++----------------------------------------------------------------------------*/ +/* BAS - Base Address Select */ +#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) +/* BS - Bank Size */ +#define EBC0_BNCR_BS_MASK 0x000E0000 +#define EBC0_BNCR_BS_1MB 0x00000000 +#define EBC0_BNCR_BS_2MB 0x00020000 +#define EBC0_BNCR_BS_4MB 0x00040000 +#define EBC0_BNCR_BS_8MB 0x00060000 +#define EBC0_BNCR_BS_16MB 0x00080000 +#define EBC0_BNCR_BS_32MB 0x000A0000 +#define EBC0_BNCR_BS_64MB 0x000C0000 +#define EBC0_BNCR_BS_128MB 0x000E0000 +/* BU - Bank Usage */ +#define EBC0_BNCR_BU_MASK 0x00018000 +#define EBC0_BNCR_BU_RO 0x00008000 +#define EBC0_BNCR_BU_WO 0x00010000 +#define EBC0_BNCR_BU_RW 0x00018000 +/* BW - Bus Width */ +#define EBC0_BNCR_BW_MASK 0x00006000 +#define EBC0_BNCR_BW_8BIT 0x00000000 +#define EBC0_BNCR_BW_16BIT 0x00002000 +#define EBC0_BNCR_BW_32BIT 0x00004000 + +/*----------------------------------------------------------------------------+ +| Peripheral Bank Access Parameters - EBC0_BnAP ++----------------------------------------------------------------------------*/ +/* Burst Mode Enable */ +#define EBC0_BNAP_BME_ENABLED 0x80000000 +#define EBC0_BNAP_BME_DISABLED 0x00000000 +/* Transfert Wait */ +#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */ +/* Chip Select On Timing */ +#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */ +/* Output Enable On Timing */ +#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */ +/* Write Back Enable On Timing */ +#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */ +/* Write Back Enable Off Timing */ +#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */ +/* Transfert Hold */ +#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */ +/* PerReady Enable */ +#define EBC0_BNAP_RE_ENABLED 0x00000100 +#define EBC0_BNAP_RE_DISABLED 0x00000000 +/* Sample On Ready */ +#define EBC0_BNAP_SOR_DELAYED 0x00000000 +#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080 +/* Byte Enable Mode */ +#define EBC0_BNAP_BEM_WRITEONLY 0x00000000 +#define EBC0_BNAP_BEM_RW 0x00000040 +/* Parity Enable */ +#define EBC0_BNAP_PEN_DISABLED 0x00000000 +#define EBC0_BNAP_PEN_ENABLED 0x00000020 + +/*----------------------------------------------------------------------------+ +| Define Boot devices ++----------------------------------------------------------------------------*/ +/* */ +#define BOOT_FROM_SMALL_FLASH 0x00 +#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 +#define BOOT_FROM_NAND_FLASH0 0x02 +#define BOOT_FROM_PCI 0x03 +#define BOOT_DEVICE_UNKNOWN 0x04 + + +#define PVR_POWERPC_440EP_PASS1 0x42221850 +#define PVR_POWERPC_440EP_PASS2 0x422218D3 + +#define TRUE 1 +#define FALSE 0 + +#define GPIO_GROUP_MAX 2 +#define GPIO_MAX 32 +#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ +#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ +#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ +#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ +#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ + /* For the other GPIO number, you must shift */ + +#define GPIO0 0 +#define GPIO1 1 + + +/*#define MAX_SELECTION_NB CORE_NB */ +#define MAX_CORE_SELECT_NB 22 + +/*----------------------------------------------------------------------------+ + | PPC440EP GPIOs addresses. + +----------------------------------------------------------------------------*/ +#define GPIO0_BASE 0xEF600B00 +#define GPIO0_REAL 0xEF600B00 + +#define GPIO1_BASE 0xEF600C00 +#define GPIO1_REAL 0xEF600C00 + +/* Offsets */ +#define GPIOx_OR 0x00 /* GPIO Output Register */ +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ +#define GPIOx_IR 0x1C /* GPIO Input Register */ +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ + +/* GPIO0 */ +#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L) +#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H) +#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L) +#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H) +#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L) +#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L) + +/* GPIO1 */ +#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L) +#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H) +#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L) +#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H) +#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L) +#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L) + +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ + + +/*----------------------------------------------------------------------------+ + | Declare Configuration values + +----------------------------------------------------------------------------*/ +typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; +typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; + +typedef struct { unsigned long add; /* gpio core base address */ + gpio_driver_t in_out; /* Driver Setting */ + gpio_select_t alt_nb; /* Selected Alternate */ +} gpio_param_s; + +/*----------------------------------------------------------------------------+ + | XX XX + | + | XXXXXX XXX XX XXX XXX + | XX XX X XX XX XX + | XX XX X XX XX XX + | XX XX XX XX XX + | XXXXXX XXX XXX XXXX XXXX + +----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ + | Defines + +----------------------------------------------------------------------------*/ +typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN, + ZMII_CONFIGURATION_IS_MII, + ZMII_CONFIGURATION_IS_RMII, + ZMII_CONFIGURATION_IS_SMII +} zmii_config_t; + +/*----------------------------------------------------------------------------+ + | Declare Configuration values + +----------------------------------------------------------------------------*/ +typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t; +typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t; +typedef enum config_list { IIC_CORE, + SCP_CORE, + DMA_CHANNEL_AB, + UIC_4_9, + USB2_HOST, + DMA_CHANNEL_CD, + USB2_DEVICE, + PACKET_REJ_FUNC_AVAIL, + USB1_DEVICE, + EBC_MASTER, + NAND_FLASH, + UART_CORE0, + UART_CORE1, + UART_CORE2, + UART_CORE3, + MII_SEL, + RMII_SEL, + SMII_SEL, + PACKET_REJ_FUNC_EN, + UIC_0_3, + USB1_HOST, + PCI_PATCH, + CORE_NB +} core_list_t; + +typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5, + B3_V6, B3_V7, B3_V8, B3_V9, B3_V10, + B3_V11, B3_V12, B3_V13, B3_V14, B3_V15, + B3_V16, B3_VALUE_UNKNOWN +} block3_value_t; + +typedef enum config_validity { CONFIG_IS_VALID, + CONFIG_IS_INVALID +} config_validity_t; diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk new file mode 100644 index 0000000..35cb655 --- /dev/null +++ b/board/amcc/bamboo/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF80000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c new file mode 100644 index 0000000..a30ab7a --- /dev/null +++ b/board/amcc/bamboo/flash.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2004-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include +#include +#include "bamboo.h" + +#undef DEBUG + +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 + */ +static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { + {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ + {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ + {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */ + {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ + {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ + {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ + {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ + {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ + {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ +}; + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + unsigned long val; + unsigned long ebc_boot_size; + unsigned long boot_selection; + + mfsdr(sdr_pstrp0, val); + index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29; + + if ((index == 5) || (index == 7)) { + /* + * Boot Settings in IIC EEprom address 0xA8 or 0xA4 + * Read Serial Device Strap Register1 in PPC440EP + */ + mfsdr(sdr_sdstp1, val); + boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; + ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; + + switch(boot_selection) { + case SDR0_SDSTP1_BOOT_SEL_EBC: + switch(ebc_boot_size) { + case SDR0_SDSTP1_EBC_ROM_BS_16BIT: + index = 3; + break; + case SDR0_SDSTP1_EBC_ROM_BS_8BIT: + index = 0; + break; + } + break; + + case SDR0_SDSTP1_BOOT_SEL_PCI: + index = 1; + break; + + case SDR0_SDSTP1_BOOT_SEL_NDFC: + index = 2; + break; + } + } else if (index == 0) { + if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) { + index = 8; /* sram below op code flash -> new index 8 */ + } + } + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[i]); +#if defined(CFG_ENV_IS_IN_FLASH) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#endif +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S new file mode 100644 index 0000000..7820107 --- /dev/null +++ b/board/amcc/bamboo/init.S @@ -0,0 +1,113 @@ +/* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds new file mode 100644 index 0000000..176900e --- /dev/null +++ b/board/amcc/bamboo/u-boot.lds @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/bamboo/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile new file mode 100644 index 0000000..f5bda55 --- /dev/null +++ b/board/amcc/bubinga/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c new file mode 100644 index 0000000..fe6ce8a --- /dev/null +++ b/board/amcc/bubinga/bubinga.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +long int spd_sdram(void); + +#include +#include + +int board_early_init_f(void) +{ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000010); + mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */ + mtdcr(uictr, 0x00000010); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Bubinga - AMCC PPC405EP Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/* + * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! + */ +void sdram_init(void) +{ + return; +} + +/* ------------------------------------------------------------------------- + initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of + the necessary info for SDRAM controller configuration + ------------------------------------------------------------------------- */ +long int initdram(int board_type) +{ + long int ret; + + ret = spd_sdram(); + return ret; +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("test: xxx MB - ok\n"); + + return (0); +} diff --git a/board/amcc/bubinga/config.mk b/board/amcc/bubinga/config.mk new file mode 100644 index 0000000..1bdf5e4 --- /dev/null +++ b/board/amcc/bubinga/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c new file mode 100644 index 0000000..e4832eb --- /dev/null +++ b/board/amcc/bubinga/flash.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static void flash_get_offsets(ulong base, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = + flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + if (CFG_MAX_FLASH_BANKS == 1) { + /* Setup offsets */ + flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + size_b1 = 0; + flash_info[0].size = size_b0; + } + + /* 2 banks */ + else { + size_b1 = + flash_get_size((vu_long *) FLASH_BASE1_PRELIM, + &flash_info[1]); + + /* Re-do sizing to get full correct info */ + + if (size_b1) { + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + mtdcr(ebccfga, pb0cr); + base_b1 = -size_b1; + pbcr = (pbcr & 0x0001ffff) | base_b1 | + (((size_b1 / 1024 / 1024) - 1) << 17); + mtdcr(ebccfgd, pbcr); + /* printf("pb1cr = %x\n", pbcr); */ + } + + if (size_b0) { + mtdcr(ebccfga, pb1cr); + pbcr = mfdcr(ebccfgd); + mtdcr(ebccfga, pb1cr); + base_b0 = base_b1 - size_b0; + pbcr = (pbcr & 0x0001ffff) | base_b0 | + (((size_b0 / 1024 / 1024) - 1) << 17); + mtdcr(ebccfgd, pbcr); + /* printf("pb0cr = %x\n", pbcr); */ + } + + size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); + + flash_get_offsets(base_b0, &flash_info[0]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b0 + size_b0 - CFG_MONITOR_LEN, + base_b0 + size_b0 - 1, &flash_info[0]); + /* Also protect sector containing initial power-up instruction */ + /* (flash_protect() checks address range - other call ignored) */ + (void)flash_protect(FLAG_PROTECT_SET, + 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, + 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]); + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = + flash_get_size((vu_long *) base_b1, &flash_info[1]); + + flash_get_offsets(base_b1, &flash_info[1]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b1 + size_b1 - CFG_MONITOR_LEN, + base_b1 + size_b1 - 1, + &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + (void)flash_protect(FLAG_PROTECT_CLEAR, + base_b0 + size_b0 - CFG_MONITOR_LEN, + base_b0 + size_b0 - 1, + &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + } /* else 2 banks */ + return (size_b0 + size_b1); +} + +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } +} diff --git a/board/amcc/bubinga/u-boot.lds b/board/amcc/bubinga/u-boot.lds new file mode 100644 index 0000000..be03092 --- /dev/null +++ b/board/amcc/bubinga/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c new file mode 100644 index 0000000..3a50b09 --- /dev/null +++ b/board/amcc/common/flash.c @@ -0,0 +1,917 @@ +/* + * (C) Copyright 2004-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word(flash_info_t * info, ulong dest, ulong data); +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word_1(flash_info_t * info, ulong dest, ulong data); +static int write_word_2(flash_info_t * info, ulong dest, ulong data); +static int flash_erase_1(flash_info_t * info, int s_first, int s_last); +static int flash_erase_2(flash_info_t * info, int s_first, int s_last); +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); +#endif + +void flash_print_info(flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_STM: + printf("STM "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_SST: + printf("SST "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AMD016: + printf("AM29F016D (16 Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AM033C: + printf("AM29LV033C (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST800A: + printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: + printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_STMW320DT: + printf ("M29W320DT (32 M, top sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); + } + printf("\n"); + return; +} + + +/* + * The following code cannot be run from FLASH! + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + /* bit 0 used for big flash marking */ + if ((ulong)addr & 0x1) { + return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); + } else { + return flash_get_size_1(addr, info); + } +} + +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) +#else +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +#endif +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: + info->flash_id += FLASH_AMD016; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: + info->flash_id += FLASH_AMDLV033C; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +static int wait_for_DQ7_1(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { + return flash_erase_2(info, s_first, s_last); + } else { + return flash_erase_1(info, s_first, s_last); + } +} + +static int flash_erase_1(flash_info_t * info, int s_first, int s_last) +#else +int flash_erase(flash_info_t * info, int s_first, int s_last) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_1(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word(flash_info_t * info, ulong dest, ulong data) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { + return write_word_2(info, dest, data); + } else { + return write_word_1(info, dest, data); + } +} + +static int write_word_1(flash_info_t * info, ulong dest, ulong data) +#else +static int write_word(flash_info_t * info, ulong dest, ulong data) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV + +#undef CFG_FLASH_WORD_SIZE +#define CFG_FLASH_WORD_SIZE unsigned short + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) +{ + short i; + int n; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: + info->flash_id += FLASH_STMW320DT; + info->sector_count = 67; + info->size = 0x00400000; break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + /* 1 x 16k boot sector */ + base -= 16 << 10; + --i; + info->start[i] = base; + /* 2 x 8k boot sectors */ + for (n=0; n<2; ++n) { + base -= 8 << 10; + --i; + info->start[i] = base; + } + /* 1 x 32k boot sector */ + base -= 32 << 10; + --i; + info->start[i] = base; + + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +static int wait_for_DQ7_2(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +static int flash_erase_2(flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_2(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +static int write_word_2(flash_info_t * info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} +#endif /* CFG_FLASH_2ND_16BIT_DEV */ diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile new file mode 100644 index 0000000..4a3927b --- /dev/null +++ b/board/amcc/ebony/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/ebony/config.mk b/board/amcc/ebony/config.mk new file mode 100644 index 0000000..e5722dd --- /dev/null +++ b/board/amcc/ebony/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFFC0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c new file mode 100644 index 0000000..a2595ee --- /dev/null +++ b/board/amcc/ebony/ebony.c @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define BOOT_SMALL_FLASH 32 /* 00100000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +long int fixed_sdram(void); + +int board_early_init_f(void) +{ + uint reg; + unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned char status; + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + + mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */ + mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ + mtebc(pb7ap, 0x01015280); /* FPGA registers */ + mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ + + /* read FPGA_REG0 and set the bus controller */ + status = *fpga_base; + if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { + mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */ + mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ + mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */ + mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ + } else { + mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */ + mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ + + /* set CS2 if FLASH_ONBD_N == 0 */ + if (!(status & FLASH_ONBD_N)) { + mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */ + mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ + } + } + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Ebony - AMCC PPC440GP Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +long int initdram(int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram(0); +#else + dram_size = fixed_sdram(); +#endif + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + * + * Assumes: 128 MB, non-ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +long int fixed_sdram(void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + /* RA=10 RD=3 */ + mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + udelay(400); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + for (;;) { + mfsdram(mem_mcsts, reg); + if (reg & 0x80000000) + break; + } + + return (128 * 1024 * 1024); /* 128 MB */ +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The ebony board is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + strap = mfdcr(cpc0_strp1); + if ((strap & 0x00100000) == 0) { + printf("PCI: CPC0_STRP1[PAE] not set.\n"); + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r(PCIX0_PIM0SA, 0); /* disable */ + out32r(PCIX0_PIM1SA, 0); /* disable */ + out32r(PCIX0_PIM2SA, 0); /* disable */ + out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE); + out32r(PCIX0_PIM0LAH, 0); + out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); + + out32r(PCIX0_BAR0, 0); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); + out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); + + out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* The ebony board is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c new file mode 100644 index 0000000..e8fbbc4 --- /dev/null +++ b/board/amcc/ebony/flash.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define BOOT_SMALL_FLASH 32 /* 00100000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +#define BOOT_SMALL_FLASH_VAL 4 +#define FLASH_ONBD_N_VAL 2 +#define FLASH_SRAM_SEL_VAL 1 + +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { + {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */ + {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */ + {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */ + {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */ + {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */ + {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */ + {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */ + {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */ +}; + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned char switch_status; + unsigned short index = 0; + int i; + + /* read FPGA base register FPGA_REG0 */ + switch_status = *fpga_base; + + /* check the bitmap of switch status */ + if (switch_status & BOOT_SMALL_FLASH) { + index += BOOT_SMALL_FLASH_VAL; + } + if (switch_status & FLASH_ONBD_N) { + index += FLASH_ONBD_N_VAL; + } + if (switch_status & FLASH_SRAM_SEL) { + index += FLASH_SRAM_SEL_VAL; + } + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) + flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[2]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[2]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[2]); +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S new file mode 100644 index 0000000..cc8f8b4 --- /dev/null +++ b/board/amcc/ebony/init.S @@ -0,0 +1,96 @@ +/* +* Copyright (C) 2002 Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/amcc/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds new file mode 100644 index 0000000..5a1c5b1 --- /dev/null +++ b/board/amcc/ebony/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/ebony/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile new file mode 100644 index 0000000..5654f91 --- /dev/null +++ b/board/amcc/luan/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +OBJS += flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk new file mode 100644 index 0000000..f52c206 --- /dev/null +++ b/board/amcc/luan/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFFC0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h new file mode 100644 index 0000000..05362e0 --- /dev/null +++ b/board/amcc/luan/epld.h @@ -0,0 +1,85 @@ +#define EPLD0_FSEL_FB2 0x80 +#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */ +#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */ +#define EPLD0_RAW_CARD_BIT1 0x10 +#define EPLD0_RAW_CARD_BIT2 0x08 +#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */ +#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */ +#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */ + +#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */ +#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */ +#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */ +#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */ +#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */ +#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */ +#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */ +#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */ + +#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */ +#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */ +#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */ +#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */ +#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */ +#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */ +#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */ + +#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */ +#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */ +#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */ +#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */ + +#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */ +#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */ +#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */ +#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */ +#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */ +#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */ +#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */ +#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */ + +#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */ +#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */ +#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */ +#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */ +#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */ +#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */ +#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */ +#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */ + +#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */ +#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */ +#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */ +#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */ +#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */ +#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */ +#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */ +#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */ + +#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */ +#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */ +#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */ +#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */ +#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */ +#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */ +#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */ +#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */ + + +typedef struct { + unsigned char status; /* misc status */ + unsigned char clock; /* clock status, PCI-X clock control */ + unsigned char ethuart; /* Ethernet, UART status */ + unsigned char leds; /* LED register */ + unsigned char vth01; /* PCI0, PCI1 VTH register */ + unsigned char pciints; /* PCI0, PCI1 interrupts */ + unsigned char pci2; /* PCI2 interrupts, clock control */ + unsigned char vth2; /* PCI2 VTH register */ + unsigned char filler1[4096-8]; + unsigned char gpio00; /* GPIO bits 0-7 */ + unsigned char gpio08; /* GPIO bits 8-15 */ + unsigned char gpio16; /* GPIO bits 16-23 */ + unsigned char gpio24; /* GPIO bits 24-31 */ + unsigned char filler2[4096-4]; + unsigned char version; /* EPLD version */ +} epld_t; diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c new file mode 100644 index 0000000..d3c3c0d --- /dev/null +++ b/board/amcc/luan/flash.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = { + {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */ +}; + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + + /* read FPGA base register FPGA_REG0 */ + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) + flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[2]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[2]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[2]); +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S new file mode 100644 index 0000000..7830ebd --- /dev/null +++ b/board/amcc/luan/init.S @@ -0,0 +1,132 @@ +/* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + +#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */ + /* large flash */ + tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + + tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) +#else /* else booting from small flash */ + tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + + tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) +#endif + + tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I ) + +#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */ + tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */ + tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) +#elif (CFG_SMALL_FLASH == 0xfff00000) + tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) +#else + #error DONT KNOW SRAM LOCATION +#endif + + /* internal ram (l2 cache) */ + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /* peripherals at f0000000 */ + tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ +#if (CONFIG_COMMANDS & CFG_CMD_PCI) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I ) +#endif + tlbtab_end diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c new file mode 100644 index 0000000..c6b79a9 --- /dev/null +++ b/board/amcc/luan/luan.c @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2005 + * John Otken, jotken@softadvances.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include "epld.h" + + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +/************************************************************************* + * int board_early_init_f() + * + ************************************************************************/ +int board_early_init_f(void) +{ + volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; + + mtebc( pb0ap, 0x03800000 ); /* set chip selects */ + mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ + mtebc( pb1ap, 0x03800000 ); + mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ + mtebc( pb2ap, 0x03800000 ); + mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ + + mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */ + mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */ + mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */ + mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */ + mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */ + mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */ + mtdcr( uic1sr, 0xffffffff ); + + mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */ + mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */ + mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */ + mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */ + mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */ + mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ + mtdcr( uic0sr, 0xffffffff ); + + x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */ + + return 0; +} + + +/************************************************************************* + * int misc_init_r() + * + ************************************************************************/ +int misc_init_r(void) +{ + volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; + x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */ + + return 0; +} + + +/************************************************************************* + * int checkboard() + * + ************************************************************************/ +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Luan - AMCC PPC440SP Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + + +/************************************************************************* + * long int fixed_sdram() + * + ************************************************************************/ +static long int fixed_sdram(void) +{ /* DDR2 init from BDI2000 script */ + mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */ + mtdcr( 0x11, 0x84000000 ); + mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */ + mtdcr( 0x11, 0x2D122000 ); + mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */ + mtdcr( 0x11, 0x00800026 ); + mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */ + mtdcr( 0x11, 0x82000800 ); + mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */ + mtdcr( 0x11, 0x80000000 ); + mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */ + mtdcr( 0x11, 0x00000201 ); + mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */ + mtdcr( 0x11, 0x00000201 ); + mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */ + mtdcr( 0x11, 0x08200000 ); + mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */ + mtdcr( 0x11, 0x80201000 ); + mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */ + mtdcr( 0x11, 0x42103242 ); + mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */ + mtdcr( 0x11, 0x0C100D14 ); + mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */ + mtdcr( 0x11, 0x00000642 ); + mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */ + mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */ + + mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */ + mtdcr( 0x11, 0x81b80000 ); + mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */ + mtdcr( 0x11, 0x82100400 ); + mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */ + mtdcr( 0x11, 0x80820000 ); + mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */ + mtdcr( 0x11, 0x80830000 ); + mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */ + mtdcr( 0x11, 0x80810000 ); + mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */ + mtdcr( 0x11, 0x80800542 ); + mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */ + mtdcr( 0x11, 0x82100400 ); + mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */ + mtdcr( 0x11, 0x80800442 ); + mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */ + mtdcr( 0x11, 0x80810380 ); + mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */ + mtdcr( 0x11, 0x80810000 ); + udelay( 10*1000 ); + + mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */ + mtdcr( 0x11, 0x28000000 ); /* set DC_EN */ + udelay( 100*1000 ); + + mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */ + mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */ + + mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */ + mtdcr( 0x11, 0x00000000 ); + mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */ + mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */ + mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */ + mtdcr( 0x11, 0x00000200 ); + + return 512 << 20; +} + + +/************************************************************************* + * long int initdram + * + ************************************************************************/ +long int initdram( int board_type ) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (0); +#else + dram_size = fixed_sdram (); +#endif + + return dram_size; +} + + +/************************************************************************* + * int testdram() + * + ************************************************************************/ +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *) 0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + + return 0; +} +#endif + + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init( struct pci_controller *hose ) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The luan board is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ + + +/************************************************************************* + * hw_watchdog_reset + * + * This routine is called to reset (keep alive) the watchdog timer + * + ************************************************************************/ +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ +} +#endif + + +/************************************************************************* + * int on_off() + * + ************************************************************************/ +static int on_off( const char *s ) +{ + if (strcmp(s, "on") == 0) { + return 1; + } else if (strcmp(s, "off") == 0) { + return 0; + } + return -1; +} + + +/************************************************************************* + * void l2cache_disable() + * + ************************************************************************/ +static void l2cache_disable(void) +{ + mtdcr( l2_cache_cfg, 0 ); +} + + +/************************************************************************* + * void l2cache_enable() + * + ************************************************************************/ +static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ +{ + mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ + + mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */ + + mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ + + while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */ + + mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ + + mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ + + mtdcr( l2_cache_snp0, 0 ); /* snoop registers */ + mtdcr( l2_cache_snp1, 0 ); + + __asm__ volatile ("sync"); /* msync */ + + mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */ + + __asm__ volatile ("sync"); +} + + +/************************************************************************* + * int l2cache_status() + * + ************************************************************************/ +static int l2cache_status(void) +{ + return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0; +} + + +/************************************************************************* + * int do_l2cache() + * + ************************************************************************/ +int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + switch (argc) { + case 2: /* on / off */ + switch (on_off(argv[1])) { + case 0: l2cache_disable(); + break; + case 1: l2cache_enable(); + break; + } + /* FALL TROUGH */ + case 1: /* get status */ + printf ("L2 Cache is %s\n", + l2cache_status() ? "ON" : "OFF"); + return 0; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return 0; +} + + +U_BOOT_CMD( + l2cache, 2, 1, do_l2cache, + "l2cache - enable or disable L2 cache\n", + "[on, off]\n" + " - enable or disable L2 cache\n" + ); diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds new file mode 100644 index 0000000..d122f49 --- /dev/null +++ b/board/amcc/luan/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/luan/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile new file mode 100644 index 0000000..af223d2 --- /dev/null +++ b/board/amcc/ocotea/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/ocotea/config.mk b/board/amcc/ocotea/config.mk new file mode 100644 index 0000000..9e18335 --- /dev/null +++ b/board/amcc/ocotea/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AMCC 440GX Reference Platform (Ocotea) board +# + +#TEXT_BASE = 0xFFFE0000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFFC0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c new file mode 100644 index 0000000..5614e20 --- /dev/null +++ b/board/amcc/ocotea/flash.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2004-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +#undef DEBUG + +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define BOOT_SMALL_FLASH 0x40 /* 01000000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +#define BOOT_SMALL_FLASH_VAL 4 +#define FLASH_ONBD_N_VAL 2 +#define FLASH_SRAM_SEL_VAL 1 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { + {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ + {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ + {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ + {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */ + {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */ + {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */ + {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */ + {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */ +}; + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned char switch_status; + unsigned short index = 0; + int i; + + /* read FPGA base register FPGA_REG0 */ + switch_status = *fpga_base; + + /* check the bitmap of switch status */ + if (switch_status & BOOT_SMALL_FLASH) { + index += BOOT_SMALL_FLASH_VAL; + } + if (switch_status & FLASH_ONBD_N) { + index += FLASH_ONBD_N_VAL; + } + if (switch_status & FLASH_SRAM_SEL) { + index += FLASH_SRAM_SEL_VAL; + } + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = + flash_get_size((vu_long *) flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf + ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[i]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S new file mode 100644 index 0000000..e33427a --- /dev/null +++ b/board/amcc/ocotea/init.S @@ -0,0 +1,97 @@ +/* +* Copyright (C) 2002 Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c new file mode 100644 index 0000000..d1a29c5 --- /dev/null +++ b/board/amcc/ocotea/ocotea.c @@ -0,0 +1,528 @@ +/* + * Copyright (C) 2004 PaulReynolds@lhsolutions.com + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include "ocotea.h" +#include +#include +#include + +#define BOOT_SMALL_FLASH 32 /* 00100000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +long int fixed_sdram (void); +void fpga_init (void); + +int board_early_init_f (void) +{ + unsigned long mfr; + unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; + unsigned char switch_status; + unsigned long cs0_base; + unsigned long cs0_size; + unsigned long cs0_twt; + unsigned long cs2_base; + unsigned long cs2_size; + unsigned long cs2_twt; + + /*-------------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------------*/ + mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | + EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | + EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | + EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); + + /*-------------------------------------------------------------------------+ + | FPGA. Initialize bank 7 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /* read FPGA base register FPGA_REG0 */ + switch_status = *fpga_base; + + if (switch_status & 0x40) { + cs0_base = 0xFFE00000; + cs0_size = EBC_BXCR_BS_2MB; + cs0_twt = 8; + cs2_base = 0xFF800000; + cs2_size = EBC_BXCR_BS_4MB; + cs2_twt = 10; + } else { + cs0_base = 0xFFC00000; + cs0_size = EBC_BXCR_BS_4MB; + cs0_twt = 10; + cs2_base = 0xFF800000; + cs2_size = EBC_BXCR_BS_2MB; + cs2_twt = 8; + } + + /*-------------------------------------------------------------------------+ + | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)| + cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /*-------------------------------------------------------------------------+ + | 8KB NVRAM/RTC. Initialize bank 1 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)| + EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /*-------------------------------------------------------------------------+ + | 4 MB FLASH. Initialize bank 2 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)| + cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /*-------------------------------------------------------------------------+ + | FPGA. Initialize bank 7 with default values. + +-------------------------------------------------------------------------*/ + mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + EBC_BXAP_BCE_DISABLE| + EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| + EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| + EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| + EBC_BXAP_BEM_WRITEONLY| + EBC_BXAP_PEN_DISABLED); + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); /* */ + mtdcr (uicb0tr, 0x00000000); /* */ + mtdcr (uicb0vr, 0x00000001); /* */ + mfsdr (sdr_mfr, mfr); + mfr &= ~SDR0_MFR_ECS_MASK; +/* mtsdr(sdr_mfr, mfr); */ + fpga_init(); + + return 0; +} + + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board"); + if (s != NULL) { + puts (", serial# "); + puts (s); + } + putc ('\n'); + + return (0); +} + + +long int initdram (int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (0); +#else + dram_size = fixed_sdram (); +#endif + return dram_size; +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + * + * Assumes: 128 MB, non-ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +long int fixed_sdram (void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + /* RA=10 RD=3 */ + mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + udelay (400); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + for (;;) { + mfsdram (mem_mcsts, reg); + if (reg & 0x80000000) + break; + } + + return (128 * 1024 * 1024); /* 128 MB */ +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The ocotea board is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* The ocotea board is always configured as host. */ + return(1); +} +#endif /* defined(CONFIG_PCI) */ + + +void fpga_init(void) +{ + unsigned long group; + unsigned long sdr0_pfc0; + unsigned long sdr0_pfc1; + unsigned long sdr0_cust0; + unsigned long pvr; + + mfsdr (sdr_pfc0, sdr0_pfc0); + mfsdr (sdr_pfc1, sdr0_pfc1); + group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); + pvr = get_pvr (); + + sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE; + if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) { + sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; + out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | + FPGA_REG2_EXT_INTFACE_ENABLE); + mtsdr (sdr_pfc0, sdr0_pfc0); + mtsdr (sdr_pfc1, sdr0_pfc1); + } else { + sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; + switch (group) + { + case 0: + case 1: + case 2: + /* CPU trace A */ + out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | + FPGA_REG2_EXT_INTFACE_ENABLE); + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; + mtsdr (sdr_pfc0, sdr0_pfc0); + mtsdr (sdr_pfc1, sdr0_pfc1); + break; + case 3: + case 4: + case 5: + case 6: + /* CPU trace B - Over EBMI */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; + mtsdr (sdr_pfc0, sdr0_pfc0); + mtsdr (sdr_pfc1, sdr0_pfc1); + out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | + FPGA_REG2_EXT_INTFACE_DISABLE); + break; + } + } + + /* Initialize the ethernet specific functions in the fpga */ + mfsdr(sdr_pfc1, sdr0_pfc1); + mfsdr(sdr_cust0, sdr0_cust0); + if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && + ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || + (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) + { + if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | + FPGA_REG3_ENET_GROUP7); + } + else + { + if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | + FPGA_REG3_ENET_GROUP7); + } + else + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | + FPGA_REG3_ENET_GROUP8); + } + } + } + else + { + if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | + FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); + } + else + { + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | + FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); + } + } + out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 | + FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 | + FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS); + + /* reset the gigabyte phy if necessary */ + if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3) + { + if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) + { + out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE); + udelay(10000); + out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE); + } + else + { + out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE); + udelay(10000); + out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE); + } + } + + /* + * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset + */ + if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) { + out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE); + udelay(10000); + out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE); + } + + /* Turn off the LED's */ + out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | + FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | + FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB); + + return; +} + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + + return (ctrlc()); +} +#endif diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h new file mode 100644 index 0000000..95ce1fd --- /dev/null +++ b/board/amcc/ocotea/ocotea.h @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Board specific FPGA stuff ... */ +#define FPGA_REG0 (CFG_FPGA_BASE + 0x00) +#define FPGA_REG0_SSCG_MASK 0x80 +#define FPGA_REG0_SSCG_DISABLE 0x00 +#define FPGA_REG0_SSCG_ENABLE 0x80 +#define FPGA_REG0_BOOT_MASK 0x40 +#define FPGA_REG0_BOOT_LARGE_FLASH 0x00 +#define FPGA_REG0_BOOT_SMALL_FLASH 0x40 +#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */ +#define FPGA_REG0_ARBITER_MASK 0x04 +#define FPGA_REG0_ARBITER_EXT 0x00 +#define FPGA_REG0_ARBITER_INT 0x04 +#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02 +#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 +#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 +#define FPGA_REG0_FLASH 0x01 +#define FPGA_REG1 (CFG_FPGA_BASE + 0x01) +#define FPGA_REG1_9772_FSELFBX_MASK 0x80 +#define FPGA_REG1_9772_FSELFBX_6 0x00 +#define FPGA_REG1_9772_FSELFBX_10 0x80 +#define FPGA_REG1_9531_SX_MASK 0x60 +#define FPGA_REG1_9531_SX_33MHZ 0x00 +#define FPGA_REG1_9531_SX_100MHZ 0x20 +#define FPGA_REG1_9531_SX_66MHZ 0x40 +#define FPGA_REG1_9531_SX_133MHZ 0x60 +#define FPGA_REG1_9772_FSELBX_MASK 0x18 +#define FPGA_REG1_9772_FSELBX_4 0x00 +#define FPGA_REG1_9772_FSELBX_6 0x08 +#define FPGA_REG1_9772_FSELBX_8 0x10 +#define FPGA_REG1_9772_FSELBX_10 0x18 +#define FPGA_REG1_SOURCE_MASK 0x07 +#define FPGA_REG1_SOURCE_TC 0x00 +#define FPGA_REG1_SOURCE_66MHZ 0x01 +#define FPGA_REG1_SOURCE_50MHZ 0x02 +#define FPGA_REG1_SOURCE_33MHZ 0x03 +#define FPGA_REG1_SOURCE_25MHZ 0x04 +#define FPGA_REG1_SOURCE_SSDIV1 0x05 +#define FPGA_REG1_SOURCE_SSDIV2 0x06 +#define FPGA_REG1_SOURCE_SSDIV4 0x07 +#define FPGA_REG2 (CFG_FPGA_BASE + 0x02) +#define FPGA_REG2_TC0 0x80 +#define FPGA_REG2_TC1 0x40 +#define FPGA_REG2_TC2 0x20 +#define FPGA_REG2_TC3 0x10 +#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/ +#define FPGA_REG2_EXT_INTFACE_MASK 0x04 +#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00 +#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 +#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/ +#define FPGA_REG2_DEFAULT_UART1_N 0x01 +#define FPGA_REG3 (CFG_FPGA_BASE + 0x03) +#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ +#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ +#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ +#define FPGA_REG3_ENET_GROUP0 0x00 +#define FPGA_REG3_ENET_GROUP1 0x10 +#define FPGA_REG3_ENET_GROUP2 0x20 +#define FPGA_REG3_ENET_GROUP3 0x30 +#define FPGA_REG3_ENET_GROUP4 0x40 +#define FPGA_REG3_ENET_GROUP5 0x50 +#define FPGA_REG3_ENET_GROUP6 0x60 +#define FPGA_REG3_ENET_GROUP7 0x70 +#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/ +#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/ +#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/ +#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/ +#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/ +#define FPGA_REG3_STAT_MASK 0x0F +#define FPGA_REG3_STAT_LED8_ENAB 0x08 +#define FPGA_REG3_STAT_LED4_ENAB 0x04 +#define FPGA_REG3_STAT_LED2_ENAB 0x02 +#define FPGA_REG3_STAT_LED1_ENAB 0x01 +#define FPGA_REG3_STAT_LED8_DISAB 0x00 +#define FPGA_REG3_STAT_LED4_DISAB 0x00 +#define FPGA_REG3_STAT_LED2_DISAB 0x00 +#define FPGA_REG3_STAT_LED1_DISAB 0x00 +#define FPGA_REG4 (CFG_FPGA_BASE + 0x04) +#define FPGA_REG4_GPHY_MODE10 0x80 +#define FPGA_REG4_GPHY_MODE100 0x40 +#define FPGA_REG4_GPHY_MODE1000 0x20 +#define FPGA_REG4_GPHY_FRC_DPLX 0x10 +#define FPGA_REG4_GPHY_ANEG_DIS 0x08 +#define FPGA_REG4_CONNECT_PHYS 0x04 + + +#define SDR0_CUST0_ENET3_MASK 0x00000080 +#define SDR0_CUST0_ENET3_COPPER 0x00000000 +#define SDR0_CUST0_ENET3_FIBER 0x00000080 +#define SDR0_CUST0_RGMII3_MASK 0x00000070 +#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) +#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) +#define SDR0_CUST0_RGMII3_DISAB 0x00000000 +#define SDR0_CUST0_RGMII3_RTBI 0x00000040 +#define SDR0_CUST0_RGMII3_RGMII 0x00000050 +#define SDR0_CUST0_RGMII3_TBI 0x00000060 +#define SDR0_CUST0_RGMII3_GMII 0x00000070 +#define SDR0_CUST0_ENET2_MASK 0x00000008 +#define SDR0_CUST0_ENET2_COPPER 0x00000000 +#define SDR0_CUST0_ENET2_FIBER 0x00000008 +#define SDR0_CUST0_RGMII2_MASK 0x00000007 +#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) +#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) +#define SDR0_CUST0_RGMII2_DISAB 0x00000000 +#define SDR0_CUST0_RGMII2_RTBI 0x00000004 +#define SDR0_CUST0_RGMII2_RGMII 0x00000005 +#define SDR0_CUST0_RGMII2_TBI 0x00000006 +#define SDR0_CUST0_RGMII2_GMII 0x00000007 diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds new file mode 100644 index 0000000..316fee8 --- /dev/null +++ b/board/amcc/ocotea/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/ocotea/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile new file mode 100644 index 0000000..f5bda55 --- /dev/null +++ b/board/amcc/walnut/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/walnut/config.mk b/board/amcc/walnut/config.mk new file mode 100644 index 0000000..1bdf5e4 --- /dev/null +++ b/board/amcc/walnut/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c new file mode 100644 index 0000000..056f9b9 --- /dev/null +++ b/board/amcc/walnut/flash.c @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static void flash_get_offsets(ulong base, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = + flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + if (CFG_MAX_FLASH_BANKS == 1) { + /* Setup offsets */ + flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + size_b1 = 0; + flash_info[0].size = size_b0; + } else { + /* 2 banks */ + size_b1 = + flash_get_size((vu_long *) FLASH_BASE1_PRELIM, + &flash_info[1]); + + /* Re-do sizing to get full correct info */ + + if (size_b1) { + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + mtdcr(ebccfga, pb0cr); + base_b1 = -size_b1; + pbcr = + (pbcr & 0x0001ffff) | base_b1 | + (((size_b1 / 1024 / 1024) - 1) << 17); + mtdcr(ebccfgd, pbcr); + /* printf("pb1cr = %x\n", pbcr); */ + } + + if (size_b0) { + mtdcr(ebccfga, pb1cr); + pbcr = mfdcr(ebccfgd); + mtdcr(ebccfga, pb1cr); + base_b0 = base_b1 - size_b0; + pbcr = + (pbcr & 0x0001ffff) | base_b0 | + (((size_b0 / 1024 / 1024) - 1) << 17); + mtdcr(ebccfgd, pbcr); + /* printf("pb0cr = %x\n", pbcr); */ + } + + size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); + + flash_get_offsets(base_b0, &flash_info[0]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = + flash_get_size((vu_long *) base_b1, &flash_info[1]); + + flash_get_offsets(base_b1, &flash_info[1]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b1 + size_b1 - + monitor_flash_len, + base_b1 + size_b1 - 1, + &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + (void)flash_protect(FLAG_PROTECT_CLEAR, + base_b0 + size_b0 - + monitor_flash_len, + base_b0 + size_b0 - 1, + &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + } /* else 2 banks */ + return (size_b0 + size_b1); +} + + +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } +} diff --git a/board/amcc/walnut/u-boot.lds b/board/amcc/walnut/u-boot.lds new file mode 100644 index 0000000..1dcbab5 --- /dev/null +++ b/board/amcc/walnut/u-boot.lds @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c new file mode 100644 index 0000000..f1a96a6 --- /dev/null +++ b/board/amcc/walnut/walnut.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int board_early_init_f(void) +{ + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the Walnut/Sycamore board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive + | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive + | IRQ 27 (EXT IRQ 2) Not Used + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive + | Note for Walnut board: + | An interrupt taken for the FPGA (IRQ 25) indicates that either + | the Mouse, Keyboard, IRDA, or External Expansion caused the + | interrupt. The FPGA must be read to determine which device + | caused the interrupt. The default setting of the FPGA clears + | + +-------------------------------------------------------------------------*/ + + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* set UART1 control to select CTS/RTS */ +#define FPGA_BRDC 0xF0300004 + *(volatile char *)(FPGA_BRDC) |= 0x1; + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + uint pvr = get_pvr(); + + if (pvr == PVR_405GPR_RB) { + puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); + } else { + puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); + } + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/* + * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! + */ +void sdram_init(void) +{ + return; +} + +/* + * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of + * the necessary info for SDRAM controller configuration + */ +long int initdram(int board_type) +{ + return spd_sdram(0); +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("test: xxx MB - ok\n"); + + return (0); +} diff --git a/board/amcc/yellowstone/Makefile b/board/amcc/yellowstone/Makefile new file mode 100644 index 0000000..47116d3 --- /dev/null +++ b/board/amcc/yellowstone/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/yellowstone/config.mk b/board/amcc/yellowstone/config.mk new file mode 100644 index 0000000..4ab0ea0 --- /dev/null +++ b/board/amcc/yellowstone/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/yellowstone/init.S b/board/amcc/yellowstone/init.S new file mode 100644 index 0000000..425ad08 --- /dev/null +++ b/board/amcc/yellowstone/init.S @@ -0,0 +1,112 @@ +/* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/amcc/yellowstone/u-boot.lds b/board/amcc/yellowstone/u-boot.lds new file mode 100644 index 0000000..a0ba44d --- /dev/null +++ b/board/amcc/yellowstone/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/yellowstone/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c new file mode 100644 index 0000000..8ddf910 --- /dev/null +++ b/board/amcc/yellowstone/yellowstone.c @@ -0,0 +1,553 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +int board_early_init_f(void) +{ + register uint reg; + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + + mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ + mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ + + mtebc(pb1ap, 0x00000000); + mtebc(pb1cr, 0x00000000); + + mtebc(pb2ap, 0x04814500); + /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ + + mtebc(pb3ap, 0x00000000); + mtebc(pb3cr, 0x00000000); + + mtebc(pb4ap, 0x00000000); + mtebc(pb4cr, 0x00000000); + + mtebc(pb5ap, 0x00000000); + mtebc(pb5cr, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + /*CPLD cs */ + /*setup Address lines for flash size 64Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000); + + /*setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /*UART1 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); + + /* external interrupts IRQ0...3 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); + +#if 0 /* test-only */ + /*setup USB 2.0 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); + out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); +#endif + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /*-------------------------------------------------------------------- + * Setup other serial configuration + *-------------------------------------------------------------------*/ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + /*clear tmrclk divisor */ + *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; + + /*enable ethernet */ + *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; + +#if 0 /* test-only */ + /*enable usb 1.1 fs device and remove usb 2.0 reset */ + *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; +#endif + + /*get rid of flash write protect */ + *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; + + return 0; +} + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + uint pbcr; + int size_val = 0; + + /* Re-do sizing to get full correct info */ + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb0cr); + mtdcr(ebccfgd, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * sdram_init -- doesn't use serial presence detect. + * + * Assumes: 256 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +#define NUM_TRIES 64 +#define NUM_READS 10 + +void sdram_tr1_set(int ram_address, int* tr1_value) +{ + int i; + int j, k; + volatile unsigned int* ram_pointer = (unsigned int*)ram_address; + int first_good = -1, last_bad = 0x1ff; + + unsigned long test[NUM_TRIES] = { + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; + + /* go through all possible SDRAM0_TR1[RDCT] values */ + for (i=0; i<=0x1ff; i++) { + /* set the current value for TR1 */ + mtsdram(mem_tr1, (0x80800800 | i)); + + /* write values */ + for (j=0; j PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Bamboo is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * hw_watchdog_reset + * + * This routine is called to reset (keep alive) the watchdog timer + * + ************************************************************************/ +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + +} +#endif diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile new file mode 100644 index 0000000..47116d3 --- /dev/null +++ b/board/amcc/yosemite/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/yosemite/config.mk b/board/amcc/yosemite/config.mk new file mode 100644 index 0000000..4ab0ea0 --- /dev/null +++ b/board/amcc/yosemite/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S new file mode 100644 index 0000000..425ad08 --- /dev/null +++ b/board/amcc/yosemite/init.S @@ -0,0 +1,112 @@ +/* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds new file mode 100644 index 0000000..a9a7b0a --- /dev/null +++ b/board/amcc/yosemite/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/yosemite/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c new file mode 100644 index 0000000..509d8e4 --- /dev/null +++ b/board/amcc/yosemite/yosemite.c @@ -0,0 +1,549 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +int board_early_init_f(void) +{ + register uint reg; + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + + mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ + mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ + + mtebc(pb1ap, 0x00000000); + mtebc(pb1cr, 0x00000000); + + mtebc(pb2ap, 0x04814500); + /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ + + mtebc(pb3ap, 0x00000000); + mtebc(pb3cr, 0x00000000); + + mtebc(pb4ap, 0x00000000); + mtebc(pb4cr, 0x00000000); + + mtebc(pb5ap, 0x00000000); + mtebc(pb5cr, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + /*CPLD cs */ + /*setup Address lines for flash size 64Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000); + + /*setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /*UART1 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); + + /* external interrupts IRQ0...3 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); + + /*setup USB 2.0 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); + out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /*-------------------------------------------------------------------- + * Setup other serial configuration + *-------------------------------------------------------------------*/ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + /*clear tmrclk divisor */ + *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; + + /*enable ethernet */ + *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; + + /*enable usb 1.1 fs device and remove usb 2.0 reset */ + *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; + + /*get rid of flash write protect */ + *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; + + return 0; +} + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + uint pbcr; + int size_val = 0; + + /* Re-do sizing to get full correct info */ + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb0cr); + mtdcr(ebccfgd, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Yosemite - AMCC PPC440EP Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * sdram_init -- doesn't use serial presence detect. + * + * Assumes: 256 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +#define NUM_TRIES 64 +#define NUM_READS 10 + +void sdram_tr1_set(int ram_address, int* tr1_value) +{ + int i; + int j, k; + volatile unsigned int* ram_pointer = (unsigned int*)ram_address; + int first_good = -1, last_bad = 0x1ff; + + unsigned long test[NUM_TRIES] = { + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; + + /* go through all possible SDRAM0_TR1[RDCT] values */ + for (i=0; i<=0x1ff; i++) { + /* set the current value for TR1 */ + mtsdram(mem_tr1, (0x80800800 | i)); + + /* write values */ + for (j=0; j PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Bamboo is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * hw_watchdog_reset + * + * This routine is called to reset (keep alive) the watchdog timer + * + ************************************************************************/ +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + +} +#endif diff --git a/board/amirix/ap1000/Makefile b/board/amirix/ap1000/Makefile new file mode 100644 index 0000000..4e1ef21 --- /dev/null +++ b/board/amirix/ap1000/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c new file mode 100644 index 0000000..dd836ce --- /dev/null +++ b/board/amirix/ap1000/ap1000.c @@ -0,0 +1,699 @@ +/* + * amirix.c: ppcboot platform support for AMIRIX board + * + * Copyright 2002 Mind NV + * Copyright 2003 AMIRIX Systems Inc. + * + * http://www.mind.be/ + * http://www.amirix.com/ + * + * Author : Peter De Schrijver (p2@mind.be) + * Frank Smith (smith@amirix.com) + * + * Derived from : Other platform support files in this tree, ml2 + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#include +#include +#include + +#include "powerspan.h" +#include "ap1000.h" + +int board_pre_init (void) +{ + return 0; +} + +/** serial number and platform display at startup */ +int checkboard (void) +{ + unsigned char *s = getenv ("serial#"); + unsigned char *e; + + /* After a loadace command, the SystemAce control register is left in a wonky state. */ + /* this code did not work in board_pre_init */ + unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE; + + p[SYSACE_CTRLREG0] = 0x0; + + /* add platform and device to banner */ + switch (get_device ()) { + case AP1xx_AP107_TARGET: + puts (AP1xx_AP107_TARGET_STR); + break; + case AP1xx_AP120_TARGET: + puts (AP1xx_AP120_TARGET_STR); + break; + case AP1xx_AP130_TARGET: + puts (AP1xx_AP130_TARGET_STR); + break; + case AP1xx_AP1070_TARGET: + puts (AP1xx_AP1070_TARGET_STR); + break; + case AP1xx_AP1100_TARGET: + puts (AP1xx_AP1100_TARGET_STR); + break; + default: + puts (AP1xx_UNKNOWN_STR); + break; + } + puts (AP1xx_TARGET_STR); + puts (" with "); + + switch (get_platform ()) { + case AP100_BASELINE_PLATFORM: + case AP1000_BASELINE_PLATFORM: + puts (AP1xx_BASELINE_PLATFORM_STR); + break; + case AP1xx_QUADGE_PLATFORM: + puts (AP1xx_QUADGE_PLATFORM_STR); + break; + case AP1xx_MGT_REF_PLATFORM: + puts (AP1xx_MGT_REF_PLATFORM_STR); + break; + case AP1xx_STANDARD_PLATFORM: + puts (AP1xx_STANDARD_PLATFORM_STR); + break; + case AP1xx_DUAL_PLATFORM: + puts (AP1xx_DUAL_PLATFORM_STR); + break; + case AP1xx_BASE_SRAM_PLATFORM: + puts (AP1xx_BASE_SRAM_PLATFORM_STR); + break; + case AP1xx_PCI_PCB_TESTPLATFORM: + case AP1000_PCI_PCB_TESTPLATFORM: + puts (AP1xx_PCI_PCB_TESTPLATFORM_STR); + break; + case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM: + puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR); + break; + case AP1xx_SFP_MEZZ_TESTPLATFORM: + puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR); + break; + default: + puts (AP1xx_UNKNOWN_STR); + break; + } + + if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) { + puts (AP1xx_TESTPLATFORM_STR); + } else { + puts (AP1xx_PLATFORM_STR); + } + + putc ('\n'); + + puts ("Serial#: "); + + if (!s) { + printf ("### No HW ID - assuming AMIRIX"); + } else { + for (e = s; *e; ++e) { + if (*e == ' ') + break; + } + + for (; s < e; ++s) { + putc (*s); + } + } + + putc ('\n'); + + return (0); +} + + +long int initdram (int board_type) +{ + unsigned char *s = getenv ("dramsize"); + + if (s != NULL) { + if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) { + s += 2; + } + return simple_strtoul (s, NULL, 16); + } else { + /* give all 64 MB */ + return 64 * 1024 * 1024; + } +} + +unsigned int get_platform (void) +{ + unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; + + return (*revision_reg_ptr & AP1xx_PLATFORM_MASK); +} + +unsigned int get_device (void) +{ + unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; + + return (*revision_reg_ptr & AP1xx_TARGET_MASK); +} + +#if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */ +/* + This function loads FPGA configurations from the SystemACE CompactFlash +*/ +int do_loadace (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE; + int cfg; + + if ((p[SYSACE_STATREG0] & 0x10) == 0) { + p[SYSACE_CTRLREG0] = 0x80; + printf ("\nNo CompactFlash Detected\n\n"); + p[SYSACE_CTRLREG0] = 0x00; + return 1; + } + + /* reset configuration controller: | 0x80 */ + /* select cpflash & ~0x40 */ + /* cfg start | 0x20 */ + /* wait for cfgstart & ~0x10 */ + /* force cfgmode: | 0x08 */ + /* do no force cfgaddr: & ~0x04 */ + /* clear mpulock: & ~0x02 */ + /* do not force lock request & ~0x01 */ + + p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08; + p[SYSACE_CTRLREG1] = 0x00; + + /* force config address if arg2 exists */ + if (argc == 2) { + cfg = simple_strtoul (argv[1], NULL, 10); + + if (cfg > 7) { + printf ("\nInvalid Configuration\n\n"); + p[SYSACE_CTRLREG0] = 0x00; + return 1; + } + /* Set config address */ + p[SYSACE_CTRLREG1] = (cfg << 5); + /* force cfgaddr */ + p[SYSACE_CTRLREG0] |= 0x04; + + } else { + cfg = (p[SYSACE_STATREG1] & 0xE0) >> 5; + } + + /* release configuration controller */ + printf ("\nLoading V2PRO with config %d...\n", cfg); + p[SYSACE_CTRLREG0] &= ~0x80; + + + while ((p[SYSACE_STATREG1] & 0x01) == 0) { + + if (p[SYSACE_ERRREG0] & 0x80) { + /* attempting to load an invalid configuration makes the cpflash */ + /* appear to be removed. Reset here to avoid that problem */ + p[SYSACE_CTRLREG0] = 0x80; + printf ("\nConfiguration %d Read Error\n\n", cfg); + p[SYSACE_CTRLREG0] = 0x00; + return 1; + } + } + + p[SYSACE_CTRLREG0] |= 0x20; + + return 0; +} +#endif + +/** Console command to display and set the software reconfigure byte + * 
+  * swconfig        - display the current value of the software reconfigure byte
+  * swconfig [#]    - change the software reconfigure byte to #
+  *
+ * @param *cmdtp [IN] as passed by run_command (ignored) + * @param flag [IN] as passed by run_command (ignored) + * @param argc [IN] as passed by run_command if 1, display, if 2 change + * @param *argv[] [IN] contains the parameters to use + * @return + * 
+  *      0 if passed
+  *     -1 if failed
+  *
+ */ +int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned char *sector_buffer = NULL; + unsigned char input_char; + int write_result; + unsigned int input_uint; + + /* display value if no argument */ + if (argc < 2) { + printf ("Software configuration byte is currently: 0x%02x\n", + *((unsigned char *) (SW_BYTE_SECTOR_ADDR + + SW_BYTE_SECTOR_OFFSET))); + return 0; + } else if (argc > 3) { + printf ("Too many arguments\n"); + return -1; + } + + /* if 3 arguments, 3rd argument is the address to use */ + if (argc == 3) { + input_uint = simple_strtoul (argv[1], NULL, 16); + sector_buffer = (unsigned char *) input_uint; + } else { + sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR; + } + + input_char = simple_strtoul (argv[1], NULL, 0); + if ((input_char & ~SW_BYTE_MASK) != 0) { + printf ("Input of 0x%02x will be masked to 0x%02x\n", + input_char, (input_char & SW_BYTE_MASK)); + input_char = input_char & SW_BYTE_MASK; + } + + memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR, + SW_BYTE_SECTOR_SIZE); + sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char; + + + printf ("Erasing Flash..."); + if (flash_sect_erase + (SW_BYTE_SECTOR_ADDR, + (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) { + return -1; + } + + printf ("Writing to Flash... "); + write_result = + flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR, + SW_BYTE_SECTOR_SIZE); + if (write_result != 0) { + flash_perror (write_result); + return -1; + } else { + printf ("done\n"); + printf ("Software configuration byte is now: 0x%02x\n", + *((unsigned char *) (SW_BYTE_SECTOR_ADDR + + SW_BYTE_SECTOR_OFFSET))); + } + + return 0; +} + +#define ONE_SECOND 1000000 + +int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int pause_time; + unsigned int delay_time; + int break_loop = 0; + + /* display value if no argument */ + if (argc < 2) { + pause_time = 1; + } + + else if (argc > 2) { + printf ("Too many arguments\n"); + return -1; + } else { + pause_time = simple_strtoul (argv[1], NULL, 0); + } + + printf ("Pausing with a poll time of %d, press any key to reactivate\n", pause_time); + delay_time = pause_time * ONE_SECOND; + while (break_loop == 0) { + udelay (delay_time); + if (serial_tstc () != 0) { + break_loop = 1; + /* eat user key presses */ + while (serial_tstc () != 0) { + serial_getc (); + } + } + } + + return 0; +} + +int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n", + *((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))); + udelay (1000); + *((unsigned char *) AP1000_CPLD_BASE) = 1; + + return 0; +} + +#define GET_DECIMAL(low_byte) ((low_byte >> 5) * 125) +#define TEMP_BUSY_BIT 0x80 +#define TEMP_LHIGH_BIT 0x40 +#define TEMP_LLOW_BIT 0x20 +#define TEMP_EHIGH_BIT 0x10 +#define TEMP_ELOW_BIT 0x08 +#define TEMP_OPEN_BIT 0x04 +#define TEMP_ETHERM_BIT 0x02 +#define TEMP_LTHERM_BIT 0x01 + +int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + int ret_val = 0; + unsigned char temp_byte; + int temp; + int temp_low; + int low; + int low_low; + int high; + int high_low; + int therm; + unsigned char user_data[4] = { 0 }; + int user_data_count = 0; + int ii; + + if (argc > 1) { + cmd = argv[1][0]; + } else { + cmd = 's'; /* default to status */ + } + + user_data_count = argc - 2; + for (ii = 0; ii < user_data_count; ii++) { + user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0); + } + switch (cmd) { + case 's': + if (I2CAccess + (0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + printf ("Status : 0x%02x ", temp_byte); + if (temp_byte & TEMP_BUSY_BIT) + printf ("BUSY "); + + if (temp_byte & TEMP_LHIGH_BIT) + printf ("LHIGH "); + + if (temp_byte & TEMP_LLOW_BIT) + printf ("LLOW "); + + if (temp_byte & TEMP_EHIGH_BIT) + printf ("EHIGH "); + + if (temp_byte & TEMP_ELOW_BIT) + printf ("ELOW "); + + if (temp_byte & TEMP_OPEN_BIT) + printf ("OPEN "); + + if (temp_byte & TEMP_ETHERM_BIT) + printf ("ETHERM "); + + if (temp_byte & TEMP_LTHERM_BIT) + printf ("LTHERM"); + + printf ("\n"); + + if (I2CAccess + (0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + printf ("Config : 0x%02x ", temp_byte); + + if (I2CAccess + (0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + printf ("\n"); + goto fail; + } + printf ("Conversion: 0x%02x\n", temp_byte); + if (I2CAccess + (0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + printf ("Cons Alert: 0x%02x ", temp_byte); + + if (I2CAccess + (0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + printf ("\n"); + goto fail; + } + printf ("Therm Hyst: %d\n", temp_byte); + + if (I2CAccess + (0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + temp = temp_byte; + if (I2CAccess + (0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + low = temp_byte; + if (I2CAccess + (0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + high = temp_byte; + if (I2CAccess + (0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + therm = temp_byte; + printf ("Local Temp: %2d Low: %2d High: %2d THERM: %2d\n", temp, low, high, therm); + + if (I2CAccess + (0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + temp = temp_byte; + if (I2CAccess + (0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + temp_low = temp_byte; + if (I2CAccess + (0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + low = temp_byte; + if (I2CAccess + (0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + low_low = temp_byte; + if (I2CAccess + (0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + high = temp_byte; + if (I2CAccess + (0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + high_low = temp_byte; + if (I2CAccess + (0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + therm = temp_byte; + if (I2CAccess + (0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &temp_byte, I2C_READ) != 0) { + goto fail; + } + printf ("Ext Temp : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte); + break; + case 'l': /* alter local limits : low, high, therm */ + if (argc < 3) { + goto usage; + } + + /* low */ + if (I2CAccess + (0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[0], I2C_WRITE) != 0) { + goto fail; + } + + if (user_data_count > 1) { + /* high */ + if (I2CAccess + (0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[1], I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 2) { + /* therm */ + if (I2CAccess + (0x20, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[2], + I2C_WRITE) != 0) { + goto fail; + } + } + break; + case 'e': /* alter external limits: low, high, therm, offset */ + if (argc < 3) { + goto usage; + } + + /* low */ + if (I2CAccess + (0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[0], I2C_WRITE) != 0) { + goto fail; + } + + if (user_data_count > 1) { + /* high */ + if (I2CAccess + (0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[1], I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 2) { + /* therm */ + if (I2CAccess + (0x19, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[2], + I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 3) { + /* offset */ + if (I2CAccess + (0x11, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[3], + I2C_WRITE) != 0) { + goto fail; + } + } + break; + case 'c': /* alter config settings: config, conv, cons alert, therm hyst */ + if (argc < 3) { + goto usage; + } + + /* config */ + if (I2CAccess + (0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[0], I2C_WRITE) != 0) { + goto fail; + } + + if (user_data_count > 1) { + /* conversion */ + if (I2CAccess + (0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, + &user_data[1], I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 2) { + /* cons alert */ + if (I2CAccess + (0x22, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[2], + I2C_WRITE) != 0) { + goto fail; + } + } + + if (user_data_count > 3) { + /* therm hyst */ + if (I2CAccess + (0x21, I2C_SENSOR_DEV, + I2C_SENSOR_CHIP_SEL, &user_data[3], + I2C_WRITE) != 0) { + goto fail; + } + } + break; + default: + goto usage; + } + + goto done; +fail: + printf ("Access to sensor failed\n"); + ret_val = -1; + goto done; +usage: + printf ("Usage:\n%s\n", cmdtp->help); + +done: + return ret_val; +} + +U_BOOT_CMD (temp, 6, 0, do_temp_sensor, + "temp - interact with the temperature sensor\n", + "temp [s]\n" + " - Show status.\n" + "temp l LOW [HIGH] [THERM]\n" + " - Set local limits.\n" + "temp e LOW [HIGH] [THERM] [OFFSET]\n" + " - Set external limits.\n" + "temp c CONFIG [CONVERSION] [CONS. ALERT] [THERM HYST]\n" + " - Set config options.\n" + "\n" + "All values can be decimal or hex (hex preceded with 0x).\n" + "Only whole numbers are supported for external limits.\n"); + +#if 0 +U_BOOT_CMD (loadace, 2, 0, do_loadace, + "loadace - load fpga configuration from System ACE compact flash\n", + "N\n" + " - Load configuration N (0-7) from System ACE compact flash\n" + "loadace\n" " - loads default configuration\n"); +#endif + +U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte, + "swconfig- display or modify the software configuration byte\n", + "N [ADDRESS]\n" + " - set software configuration byte to N, optionally use ADDRESS as\n" + " location of buffer for flash copy\n" + "swconfig\n" " - display software configuration byte\n"); + +U_BOOT_CMD (pause, 2, 0, do_pause, + "pause - sleep processor until any key is pressed with poll time of N seconds\n", + "N\n" + " - sleep processor until any key is pressed with poll time of N seconds\n" + "pause\n" + " - sleep processor until any key is pressed with poll time of 1 second\n"); + +U_BOOT_CMD (swrecon, 1, 0, do_swreconfig, + "swrecon - trigger a board reconfigure to the software selected configuration\n", + "\n" + " - trigger a board reconfigure to the software selected configuration\n"); diff --git a/board/amirix/ap1000/ap1000.h b/board/amirix/ap1000/ap1000.h new file mode 100644 index 0000000..118c4d1 --- /dev/null +++ b/board/amirix/ap1000/ap1000.h @@ -0,0 +1,173 @@ +/* + * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally + * + * Author : James MacAulay + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#ifndef __AP1000_H +#define __AP1000_H + +/* + * Revision Register stuff + */ +#define AP1xx_FPGA_REV_ADDR 0x29000000 + +#define AP1xx_PLATFORM_MASK 0xFF000000 +#define AP100_BASELINE_PLATFORM 0x01000000 +#define AP1xx_QUADGE_PLATFORM 0x02000000 +#define AP1xx_MGT_REF_PLATFORM 0x03000000 +#define AP1xx_STANDARD_PLATFORM 0x04000000 +#define AP1xx_DUAL_PLATFORM 0x05000000 +#define AP1xx_BASE_SRAM_PLATFORM 0x06000000 + +#define AP1000_BASELINE_PLATFORM 0x21000000 + +#define AP1xx_TESTPLATFORM_MASK 0xC0000000 +#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000 +#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000 +#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000 + +#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000 + +#define AP1xx_TARGET_MASK 0x00FF0000 +#define AP1xx_AP107_TARGET 0x00010000 +#define AP1xx_AP120_TARGET 0x00020000 +#define AP1xx_AP130_TARGET 0x00030000 +#define AP1xx_AP1070_TARGET 0x00040000 +#define AP1xx_AP1100_TARGET 0x00050000 + +#define AP1xx_UNKNOWN_STR "Unknown" + +#define AP1xx_PLATFORM_STR " Platform" +#define AP1xx_BASELINE_PLATFORM_STR "Baseline" +#define AP1xx_QUADGE_PLATFORM_STR "Quad GE" +#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference" +#define AP1xx_STANDARD_PLATFORM_STR "Standard" +#define AP1xx_DUAL_PLATFORM_STR "Dual" +#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM" + +#define AP1xx_TESTPLATFORM_STR " Test Platform" +#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base" +#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine" +#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine" + +#define AP1xx_TARGET_STR " Board" +#define AP1xx_AP107_TARGET_STR "AP107" +#define AP1xx_AP120_TARGET_STR "AP120" +#define AP1xx_AP130_TARGET_STR "AP130" + +#define AP1xx_AP1070_TARGET_STR "AP1070" +#define AP1xx_AP1100_TARGET_STR "AP1100" + +/* + * Flash Stuff + */ +#define AP1xx_PROGRAM_FLASH_INDEX 0 +#define AP1xx_CONFIG_FLASH_INDEX 1 + +/* + * System Ace Stuff + */ +#define AP1000_SYSACE_REGBASE 0x28000000 + +#define SYSACE_STATREG0 0x04 /* 7:0 */ +#define SYSACE_STATREG1 0x05 /* 15:8 */ +#define SYSACE_STATREG2 0x06 /* 23:16 */ +#define SYSACE_STATREG3 0x07 /* 31:24 */ + +#define SYSACE_ERRREG0 0x08 /* 7:0 */ +#define SYSACE_ERRREG1 0x09 /* 15:8 */ +#define SYSACE_ERRREG2 0x0a /* 23:16 */ +#define SYSACE_ERRREG3 0x0b /* 31:24 */ + +#define SYSACE_CTRLREG0 0x18 /* 7:0 */ +#define SYSACE_CTRLREG1 0x19 /* 15:8 */ +#define SYSACE_CTRLREG2 0x1A /* 23:16 */ +#define SYSACE_CTRLREG3 0x1B /* 31:24 */ + +/* + * Software reconfig thing + */ +#define SW_BYTE_SECTOR_ADDR 0x24FE0000 +#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF +#define SW_BYTE_SECTOR_SIZE 0x00020000 +#define SW_BYTE_MASK 0x00000003 + +#define DEFAULT_TEMP_ADDR 0x00100000 + +#define AP1000_CPLD_BASE 0x26000000 + +/* PowerSpan II Stuff */ +#define PSII_SYNC() asm("eieio") +#define PSPAN_BASEADDR 0x30000000 +#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \ + 0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \ + 0x0, /* Byte 4 - Powerspan reserved - start of short load */ \ + 0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \ + 0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \ + 0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \ + 0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \ + 0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \ + 0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \ + 0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \ + 0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \ + 0x00, /* Byte 15 - Vital Product Data Disabled. */ \ + 0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \ + 0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \ + 0x00, /* Byte 18 - I2O disabled */ \ + 0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \ + 0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \ + 0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \ + 0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \ + 0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \ + 0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \ + 0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \ + /* Long Load Information */ \ + 0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \ + 0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \ + 0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \ + 0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \ + 0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \ + 0x01, /* Byte 39 - Power span revision 1. */ \ + 0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \ + 0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \ + 0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \ + 0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \ + 0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \ + 0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \ + 0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \ + 0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \ + 0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \ + 0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \ + 0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \ + 0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \ + 0x01, /* Byte 59 - PCI-2 class revision 1 */ \ + 0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */ + + +#define EEPROM_LENGTH 64 /* Long Load */ + +#define I2C_SENSOR_DEV 0x9 +#define I2C_SENSOR_CHIP_SEL 0x4 + +/* + * Board Functions + */ +void set_eat_machine_checks(int a_flag); +int get_eat_machine_checks(void); +unsigned int get_platform(void); +unsigned int get_device(void); +void* memcpyb(void * dest,const void *src,size_t count); +int process_bootflag(ulong bootflag); +void user_led_on(void); +void user_led_off(void); + +#endif /* __COMMON_H_ */ diff --git a/board/amirix/ap1000/config.mk b/board/amirix/ap1000/config.mk new file mode 100644 index 0000000..c09783a --- /dev/null +++ b/board/amirix/ap1000/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Start at bottom of RAM, but at an aliased address so that it looks +# like it's not in RAM. This is a bit of voodoo to allow it to be +# run from RAM instead of Flash. +TEXT_BASE = 0x08000000 diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c new file mode 100644 index 0000000..1a3b252 --- /dev/null +++ b/board/amirix/ap1000/flash.c @@ -0,0 +1,903 @@ +/** + * @file flash.c + */ + +/* + * (C) Copyright 2003 + * AMIRIX Systems Inc. + * + * Originated from ppcboot-2.0.0/board/esd/cpci440/strataflash.c + * + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for ppcboot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + +#define FLASH_MAN_CFI 0x01000000 + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char *cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); +static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); +static void flash_write_cmd (flash_info_t * info, int sect, uchar offset, + uchar cmd); +static int flash_isequal (flash_info_t * info, int sect, uchar offset, + uchar cmd); +static int flash_isset (flash_info_t * info, int sect, uchar offset, + uchar cmd); +static int flash_detect_cfi (flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t * info, ulong dest, + cfiword_t cword); +static int flash_full_status_check (flash_info_t * info, ulong sector, + ulong tout, char *prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, + int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +uchar *flash_make_addr (flash_info_t * info, int sect, int offset) +{ + return ((uchar *) (info->start[sect] + (offset * info->chipwidth))); +} + +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +uchar flash_read_uchar (flash_info_t * info, uchar offset) +{ + if (info->portwidth == FLASH_CFI_8BIT) { + volatile uchar *cp; + uchar c; + + cp = flash_make_addr (info, 0, offset); + c = *cp; +#ifdef DEBUG_FLASH + printf ("flash_read_uchar offset=%04x ptr=%08x c=%02x\n", + offset, (unsigned int) cp, c); +#endif + return (c); + + } else if (info->portwidth == FLASH_CFI_16BIT) { + volatile ushort *sp; + ushort s; + uchar c; + + sp = (ushort *) flash_make_addr (info, 0, offset); + s = *sp; + c = (uchar) s; +#ifdef DEBUG_FLASH + printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c); +#endif + return (c); + + } + + return 0; +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort (flash_info_t * info, int sect, uchar offset) +{ + if (info->portwidth == FLASH_CFI_8BIT) { + volatile uchar *cp; + uchar c0, c1; + ushort s; + + cp = flash_make_addr (info, 0, offset); + c1 = cp[2]; + c0 = cp[0]; + s = c1 << 8 | c0; +#ifdef DEBUG_FLASH + printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s); +#endif + return (s); + + } else if (info->portwidth == FLASH_CFI_16BIT) { + volatile ushort *sp; + ushort s; + uchar c0, c1; + + sp = (ushort *) flash_make_addr (info, 0, offset); + s = *sp; + c1 = (uchar) sp[1]; + c0 = (uchar) sp[0]; + s = c1 << 8 | c0; +#ifdef DEBUG_FLASH + printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s); +#endif + return (s); + + } + + return 0; +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long (flash_info_t * info, int sect, uchar offset) +{ + if (info->portwidth == FLASH_CFI_8BIT) { + volatile uchar *cp; + uchar c0, c1, c2, c3; + ulong l; + + cp = flash_make_addr (info, 0, offset); + c3 = cp[6]; + c2 = cp[4]; + c1 = cp[2]; + c0 = cp[0]; + l = c3 << 24 | c2 << 16 | c1 << 8 | c0; +#ifdef DEBUG_FLASH + printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l); +#endif + return (l); + + } else if (info->portwidth == FLASH_CFI_16BIT) { + volatile ushort *sp; + uchar c0, c1, c2, c3; + ulong l; + + sp = (ushort *) flash_make_addr (info, 0, offset); + c3 = (uchar) sp[3]; + c2 = (uchar) sp[2]; + c1 = (uchar) sp[1]; + c0 = (uchar) sp[0]; + l = c3 << 24 | c2 << 16 | c1 << 8 | c0; +#ifdef DEBUG_FLASH + printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l); +#endif + return (l); + + } + + return 0; +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + + size = 0; + + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[0].portwidth = FLASH_CFI_16BIT; + flash_info[0].chipwidth = FLASH_CFI_16BIT; + size += flash_info[0].size = flash_get_size (CFG_PROGFLASH_BASE, 0); + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20); + }; + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].portwidth = FLASH_CFI_8BIT; + flash_info[1].chipwidth = FLASH_CFI_16BIT; + size += flash_info[1].size = flash_get_size (CFG_CONFFLASH_BASE, 1); + if (flash_info[1].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20); + }; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd (info, sect, 0, + FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sect, 0, + FLASH_CMD_BLOCK_ERASE); + flash_write_cmd (info, sect, 0, + FLASH_CMD_ERASE_CONFIRM); + + if (flash_full_status_check + (info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf ("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf ("CFI conformant FLASH (x%d device in x%d mode)", + (info->chipwidth << 3), (info->portwidth << 3)); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n"); + printf (" %08lX%5s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if ((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for (i = 0; i < aln; ++i, ++cp) + flash_add_byte (info, &cword, (*(uchar *) cp)); + + for (; (i < info->portwidth) && (cnt > 0); i++) { + flash_add_byte (info, &cword, *src++); + cnt--; + cp++; + } + for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte (info, &cword, (*(uchar *) cp)); + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp = cp; + } +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while (cnt >= info->portwidth) { + i = info->buffer_size > cnt ? cnt : info->buffer_size; + if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -= i; + } +#else + /* handle the aligned part */ + while (cnt >= info->portwidth) { + cword.l = 0; + for (i = 0; i < info->portwidth; i++) { + flash_add_byte (info, &cword, *src++); + } + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { + flash_add_byte (info, &cword, *src++); + --cnt; + } + for (; i < info->portwidth; ++i, ++cp) { + flash_add_byte (info, &cword, (*(uchar *) cp)); + } + + return flash_write_cfiword (info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); + if (prot) + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if ((retcode = + flash_full_status_check (info, sector, info->erase_blk_tout, + prot ? "protect" : "unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if (prot == 0) { + int i; + + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) + flash_real_protect (info, i, 1); + } + } + } + + return retcode; +} + +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check (flash_info_t * info, ulong sector, ulong tout, + char *prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer (start) > info->erase_blk_tout) { + printf ("Flash %s timeout at address %lx\n", prompt, + info->start[sector]); + flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check (flash_info_t * info, ulong sector, + ulong tout, char *prompt) +{ + int retcode; + + retcode = flash_status_check (info, sector, tout, prompt); + if ((retcode == ERR_OK) + && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf ("Flash %s error at address %lx\n", prompt, + info->start[sector]); + if (flash_isset + (info, sector, 0, + FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { + printf ("Command Sequence Error.\n"); + } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { + printf ("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { + printf ("Locking Error\n"); + } + if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { + printf ("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) + printf ("Vpp Low Error.\n"); + } + flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); + return retcode; +} + +/*----------------------------------------------------------------------- + */ +static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) +{ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +{ + /*int i; */ + uchar *cp = (uchar *) cmdbuf; + + /* for(i=0; i< info->portwidth; i++) */ + /* *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */ + if (info->portwidth == FLASH_CFI_8BIT + && info->chipwidth == FLASH_CFI_16BIT) { + cp[0] = cmd; + } else if (info->portwidth == FLASH_CFI_16BIT + && info->chipwidth == FLASH_CFI_16BIT) { + cp[0] = '\0'; + cp[1] = cmd; + }; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd (flash_info_t * info, int sect, uchar offset, + uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + + addr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal (flash_info_t * info, int sect, uchar offset, + uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + */ +static int flash_isset (flash_info_t * info, int sect, uchar offset, + uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi (flash_info_t * info) +{ + +#if 0 + for (info->portwidth = FLASH_CFI_8BIT; + info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) { + for (info->chipwidth = FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd (info, 0, FLASH_OFFSET_CFI, + FLASH_CMD_CFI); + if (flash_isequal + (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') + && flash_isequal (info, 0, + FLASH_OFFSET_CFI_RESP + 1, 'R') + && flash_isequal (info, 0, + FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } +#endif + flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && + flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { + return 1; + } else { + return 0; + }; +} + +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if (flash_detect_cfi (info)) { +#ifdef DEBUG_FLASH + printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif + size_ratio = 1; /* info->portwidth / info->chipwidth; */ + num_erase_regions = + flash_read_uchar (info, + FLASH_OFFSET_NUM_ERASE_REGIONS); +#ifdef DEBUG_FLASH + printf ("found %d erase regions\n", num_erase_regions); +#endif + sect_cnt = 0; + sector = base; + for (i = 0; i < num_erase_regions; i++) { + if (i > NUM_ERASE_REGIONS) { + printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long (info, 0, + FLASH_OFFSET_ERASE_REGIONS); + erase_region_count = (tmp & 0xffff) + 1; + tmp >>= 16; + erase_region_size = + (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; + for (j = 0; j < erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = + flash_isset (info, sect_cnt, + FLASH_OFFSET_PROTECT, + FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = + (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * + size_ratio; + info->buffer_size = + (1 << + flash_read_ushort (info, 0, + FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = + (tmp * + (1 << + flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = + (tmp * + (1 << + flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT); + info->write_tout = + (tmp * + (1 << + flash_read_uchar (info, + FLASH_OFFSET_WMAX_TOUT))) / 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t * info, ulong dest, + cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr (info, 0, 0); + cptr.cp = (uchar *) dest; + + /* Check if Flash is (sufficiently) erased */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if (!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + return flash_full_status_check (info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector (flash_info_t * info, ulong addr) +{ + int sector; + + for (sector = info->sector_count - 1; sector >= 0; sector--) { + if (addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, + int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector (info, dest); + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if ((retcode = + flash_status_check (info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd (info, sector, 0, + FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = + flash_full_status_check (info, sector, + info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S new file mode 100644 index 0000000..3aaa5c2 --- /dev/null +++ b/board/amirix/ap1000/init.S @@ -0,0 +1,34 @@ +/* + * init.S: Stubs for ppcboot initialization + * + * Copyright 2002 Mind NV + * + * http://www.mind.be/ + * + * Author : Peter De Schrijver (p2@mind.be) + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#include + +#include +#include + +#include +#include + + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + blr + + .globl sdram_init +sdram_init: + blr diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c new file mode 100644 index 0000000..a6436ac --- /dev/null +++ b/board/amirix/ap1000/pci.c @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2003 + * AMIRIX Systems Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define PCI_MEM_82559ER_CSR_BASE 0x30200000 +#define PCI_IO_82559ER_CSR_BASE 0x40000200 + +/** AP1100 specific values */ +#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */ +#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */ +#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */ +#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */ +#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */ +#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */ +#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */ +#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */ + +/* static int G_verbosity_level = 1; */ +#define G_verbosity_level 1 + +void write1 (unsigned long addr, unsigned char val) +{ + volatile unsigned char *p = (volatile unsigned char *) addr; + + if (G_verbosity_level > 1) + printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr, + val); + *p = val; + asm ("eieio"); +} + +unsigned char read1 (unsigned long addr) +{ + unsigned char val; + volatile unsigned char *p = (volatile unsigned char *) addr; + + if (G_verbosity_level > 1) + printf ("read1: addr=%08x ", (unsigned int) addr); + val = *p; + asm ("eieio"); + if (G_verbosity_level > 1) + printf ("val=%08x\n", val); + return val; +} + +void write2 (unsigned long addr, unsigned short val) +{ + volatile unsigned short *p = (volatile unsigned short *) addr; + + if (G_verbosity_level > 1) + printf ("write2: addr=%08x val=%04x -> *p=%04x\n", + (unsigned int) addr, val, + ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8)); + + *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); + asm ("eieio"); +} + +unsigned short read2 (unsigned long addr) +{ + unsigned short val; + volatile unsigned short *p = (volatile unsigned short *) addr; + + if (G_verbosity_level > 1) + printf ("read2: addr=%08x ", (unsigned int) addr); + val = *p; + val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); + asm ("eieio"); + if (G_verbosity_level > 1) + printf ("*p=%04x -> val=%04x\n", + ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val); + return val; +} + +void write4 (unsigned long addr, unsigned long val) +{ + volatile unsigned long *p = (volatile unsigned long *) addr; + + if (G_verbosity_level > 1) + printf ("write4: addr=%08x val=%08x -> *p=%08x\n", + (unsigned int) addr, (unsigned int) val, + (unsigned int) (((val & 0xFF000000) >> 24) | + ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | + ((val & 0x0000FF00) << 8))); + + *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); + asm ("eieio"); +} + +unsigned long read4 (unsigned long addr) +{ + unsigned long val; + volatile unsigned long *p = (volatile unsigned long *) addr; + + if (G_verbosity_level > 1) + printf ("read4: addr=%08x", (unsigned int) addr); + + val = *p; + val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); + asm ("eieio"); + + if (G_verbosity_level > 1) + printf ("*p=%04x -> val=%04x\n", + (unsigned int) (((val & 0xFF000000) >> 24) | + ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | + ((val & 0x0000FF00) << 8)), + (unsigned int) val); + return val; +} + +void write4be (unsigned long addr, unsigned long val) +{ + volatile unsigned long *p = (volatile unsigned long *) addr; + + if (G_verbosity_level > 1) + printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr, + (unsigned int) val); + *p = val; + asm ("eieio"); +} + +/** One byte configuration write on PSII. + * Currently fixes destination PCI bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Address of location for received byte. + * @return Always Zero. + */ +static int psII_read_config_byte (struct pci_controller *hose, + pci_dev_t dev, int reg, u8 * val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + *val = read1 (PSII_CONFIG_DATA + (reg & 0x03)); + return (0); +} + +/** One byte configuration write on PSII. + * Currently fixes destination bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Output byte. + * @return Always Zero. + */ +static int psII_write_config_byte (struct pci_controller *hose, + pci_dev_t dev, int reg, u8 val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val); + + return (0); +} + +/** One word (16 bit) configuration read on PSII. + * Currently fixes destination PCI bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Address of location for received word. + * @return Always Zero. + */ +static int psII_read_config_word (struct pci_controller *hose, + pci_dev_t dev, int reg, u16 * val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + *val = read2 (PSII_CONFIG_DATA + (reg & 0x03)); + return (0); +} + +/** One word (16 bit) configuration write on PSII. + * Currently fixes destination bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Output word. + * @return Always Zero. + */ +static int psII_write_config_word (struct pci_controller *hose, + pci_dev_t dev, int reg, u16 val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val); + + return (0); +} + +/** One DWord (32 bit) configuration read on PSII. + * Currently fixes destination PCI bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Address of location for received byte. + * @return Always Zero. + */ +static int psII_read_config_dword (struct pci_controller *hose, + pci_dev_t dev, int reg, u32 * val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + *val = read4 (PSII_CONFIG_DATA); + return (0); +} + +/** One DWord (32 bit) configuration write on PSII. + * Currently fixes destination bus to PCI2, onboard + * pci. + * @param hose PCI Host controller information. Ignored. + * @param dev Encoded PCI device/Bus and Function value. + * @param reg PCI Configuration register number. + * @param val Output Dword. + * @return Always Zero. + */ +static int psII_write_config_dword (struct pci_controller *hose, + pci_dev_t dev, int reg, u32 val) +{ + write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ + (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ + + write4 (PSII_CONFIG_DATA, (unsigned long) val); + + return (0); +} + +static struct pci_config_table ap1000_config_table[] = { +#ifdef CONFIG_AP1000 + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN), + PCI_FUNC (CFG_ETH_DEV_FN), + pci_cfgfunc_config_device, + {CFG_ETH_IOBASE, CFG_ETH_MEMBASE, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, +#endif + {} +}; + +static struct pci_controller psII_hose = { + config_table:ap1000_config_table, +}; + +void pci_init_board (void) +{ + struct pci_controller *hose = &psII_hose; + + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region (hose->regions + 0, + AP1000_SYS_MEM_START, AP1000_SYS_MEM_START, + AP1000_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI Memory space */ + pci_set_region (hose->regions + 1, + PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE, + PSII_PCI_MEM_SIZE, PCI_REGION_MEM); + + /* No IO Memory space - for now */ + + pci_set_ops (hose, + psII_read_config_byte, + psII_read_config_word, + psII_read_config_dword, + psII_write_config_byte, + psII_write_config_word, psII_write_config_dword); + + hose->region_count = 2; + + pci_register_hose (hose); + + hose->last_busno = pci_hose_scan (hose); +} diff --git a/board/amirix/ap1000/powerspan.c b/board/amirix/ap1000/powerspan.c new file mode 100644 index 0000000..f048155 --- /dev/null +++ b/board/amirix/ap1000/powerspan.c @@ -0,0 +1,750 @@ +/** + * @file powerspan.c Source file for PowerSpan II code. + */ + +/* + * (C) Copyright 2005 + * AMIRIX Systems Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "powerspan.h" +#define tolower(x) x +#include "ap1000.h" + +#ifdef INCLUDE_PCI + +/** Write one byte with byte swapping. + * @param addr [IN] the address to write to + * @param val [IN] the value to write + */ +void write1 (unsigned long addr, unsigned char val) +{ + volatile unsigned char *p = (volatile unsigned char *) addr; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("write1: addr=%08x val=%02x\n", addr, val); + } +#endif + *p = val; + PSII_SYNC (); +} + +/** Read one byte with byte swapping. + * @param addr [IN] the address to read from + * @return the value at addr + */ +unsigned char read1 (unsigned long addr) +{ + unsigned char val; + volatile unsigned char *p = (volatile unsigned char *) addr; + + val = *p; + PSII_SYNC (); +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("read1: addr=%08x val=%02x\n", addr, val); + } +#endif + return val; +} + +/** Write one 2-byte word with byte swapping. + * @param addr [IN] the address to write to + * @param val [IN] the value to write + */ +void write2 (unsigned long addr, unsigned short val) +{ + volatile unsigned short *p = (volatile unsigned short *) addr; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val, + ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8)); + } +#endif + *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); + PSII_SYNC (); +} + +/** Read one 2-byte word with byte swapping. + * @param addr [IN] the address to read from + * @return the value at addr + */ +unsigned short read2 (unsigned long addr) +{ + unsigned short val; + volatile unsigned short *p = (volatile unsigned short *) addr; + + val = *p; + val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); + PSII_SYNC (); +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p, + val); + } +#endif + return val; +} + +/** Write one 4-byte word with byte swapping. + * @param addr [IN] the address to write to + * @param val [IN] the value to write + */ +void write4 (unsigned long addr, unsigned long val) +{ + volatile unsigned long *p = (volatile unsigned long *) addr; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val, + ((val & 0xFF000000) >> 24) | + ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | + ((val & 0x0000FF00) << 8)); + } +#endif + *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); + PSII_SYNC (); +} + +/** Read one 4-byte word with byte swapping. + * @param addr [IN] the address to read from + * @return the value at addr + */ +unsigned long read4 (unsigned long addr) +{ + unsigned long val; + volatile unsigned long *p = (volatile unsigned long *) addr; + + val = *p; + val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | + ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); + PSII_SYNC (); +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p, + val); + } +#endif + return val; +} + +int PCIReadConfig (int bus, int dev, int fn, int reg, int width, + unsigned long *val) +{ + unsigned int conAdrVal; + unsigned int conDataReg = REG_CONFIG_DATA; + unsigned int status; + int ret_val = 0; + + + /* DEST bit hardcoded to 1: local pci is PCI-2 */ + /* TYPE bit is hardcoded to 1: all config cycles are local */ + conAdrVal = (1 << 24) + | ((bus & 0xFF) << 16) + | ((dev & 0xFF) << 11) + | ((fn & 0x07) << 8) + | (reg & 0xFC); + + /* clear any pending master aborts */ + write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); + + /* Load the conAdrVal value first, then read from pb_conf_data */ + write4 (REG_CONFIG_ADDRESS, conAdrVal); + PSII_SYNC (); + + + /* Note: documentation does not match the pspan library code */ + /* Note: *pData comes back as -1 if device is not present */ + switch (width) { + case 4: + *(unsigned int *) val = read4 (conDataReg); + break; + case 2: + *(unsigned short *) val = read2 (conDataReg); + break; + case 1: + *(unsigned char *) val = read1 (conDataReg); + break; + default: + ret_val = ILLEGAL_REG_OFFSET; + break; + } + PSII_SYNC (); + + /* clear any pending master aborts */ + status = read4 (REG_P1_CSR); + if (status & CLEAR_MASTER_ABORT) { + ret_val = NO_DEVICE_FOUND; + write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); + } + + return ret_val; +} + + +int PCIWriteConfig (int bus, int dev, int fn, int reg, int width, + unsigned long val) +{ + unsigned int conAdrVal; + unsigned int conDataReg = REG_CONFIG_DATA; + unsigned int status; + int ret_val = 0; + + + /* DEST bit hardcoded to 1: local pci is PCI-2 */ + /* TYPE bit is hardcoded to 1: all config cycles are local */ + conAdrVal = (1 << 24) + | ((bus & 0xFF) << 16) + | ((dev & 0xFF) << 11) + | ((fn & 0x07) << 8) + | (reg & 0xFC); + + /* clear any pending master aborts */ + write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); + + /* Load the conAdrVal value first, then read from pb_conf_data */ + write4 (REG_CONFIG_ADDRESS, conAdrVal); + PSII_SYNC (); + + + /* Note: documentation does not match the pspan library code */ + /* Note: *pData comes back as -1 if device is not present */ + switch (width) { + case 4: + write4 (conDataReg, val); + break; + case 2: + write2 (conDataReg, val); + break; + case 1: + write1 (conDataReg, val); + break; + default: + ret_val = ILLEGAL_REG_OFFSET; + break; + } + PSII_SYNC (); + + /* clear any pending master aborts */ + status = read4 (REG_P1_CSR); + if (status & CLEAR_MASTER_ABORT) { + ret_val = NO_DEVICE_FOUND; + write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); + } + + return ret_val; +} + + +int pci_read_config_byte (int bus, int dev, int fn, int reg, + unsigned char *val) +{ + unsigned long read_val; + int ret_val; + + ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val); + *val = read_val & 0xFF; + + return ret_val; +} + +int pci_write_config_byte (int bus, int dev, int fn, int reg, + unsigned char val) +{ + return PCIWriteConfig (bus, dev, fn, reg, 1, val); +} + +int pci_read_config_word (int bus, int dev, int fn, int reg, + unsigned short *val) +{ + unsigned long read_val; + int ret_val; + + ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val); + *val = read_val & 0xFFFF; + + return ret_val; +} + +int pci_write_config_word (int bus, int dev, int fn, int reg, + unsigned short val) +{ + return PCIWriteConfig (bus, dev, fn, reg, 2, val); +} + +int pci_read_config_dword (int bus, int dev, int fn, int reg, + unsigned long *val) +{ + return PCIReadConfig (bus, dev, fn, reg, 4, val); +} + +int pci_write_config_dword (int bus, int dev, int fn, int reg, + unsigned long val) +{ + return PCIWriteConfig (bus, dev, fn, reg, 4, val); +} + +#endif /* INCLUDE_PCI */ + +int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode, + unsigned char theChipSel, unsigned char *theValue, int RWFlag) +{ + int ret_val = 0; + unsigned int reg_value; + + reg_value = PowerSpanRead (REG_I2C_CSR); + + if (reg_value & I2C_CSR_ACT) { + printf ("Error: I2C busy\n"); + ret_val = I2C_BUSY; + } else { + reg_value = ((theI2CAddress & 0xFF) << 24) + | ((theDevCode & 0x0F) << 12) + | ((theChipSel & 0x07) << 9) + | I2C_CSR_ERR; + if (RWFlag == I2C_WRITE) { + reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16); + } + + PowerSpanWrite (REG_I2C_CSR, reg_value); + udelay (1); + + do { + reg_value = PowerSpanRead (REG_I2C_CSR); + + if ((reg_value & I2C_CSR_ACT) == 0) { + if (reg_value & I2C_CSR_ERR) { + ret_val = I2C_ERR; + } else { + *theValue = + (reg_value & I2C_CSR_DATA) >> + 16; + } + } + } while (reg_value & I2C_CSR_ACT); + } + + return ret_val; +} + +int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue) +{ + return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, + theValue, I2C_READ); +} + +int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue) +{ + return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, + &theValue, I2C_WRITE); +} + +int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + int ret_val = 0; + unsigned int address = 0; + unsigned char value = 1; + unsigned char read_value; + int ii; + int error = 0; + unsigned char *mem_ptr; + unsigned char default_eeprom[] = EEPROM_DEFAULT; + + if (argc < 2) { + goto usage; + } + + cmd = argv[1][0]; + if (argc > 2) { + address = simple_strtoul (argv[2], NULL, 16); + if (argc > 3) { + value = simple_strtoul (argv[3], NULL, 16) & 0xFF; + } + } + + switch (cmd) { + case 'r': + if (address > 256) { + printf ("Illegal Address\n"); + goto usage; + } + printf ("@0x%x: ", address); + for (ii = 0; ii < value; ii++) { + if (EEPROMRead (address + ii, &read_value) != + 0) { + printf ("Read Error\n"); + } else { + printf ("0x%02x ", read_value); + } + + if (((ii + 1) % 16) == 0) { + printf ("\n"); + } + } + printf ("\n"); + break; + case 'w': + if (address > 256) { + printf ("Illegal Address\n"); + goto usage; + } + if (argc < 4) { + goto usage; + } + if (EEPROMWrite (address, value) != 0) { + printf ("Write Error\n"); + } + break; + case 'g': + if (argc != 3) { + goto usage; + } + mem_ptr = (unsigned char *) address; + for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); + ii++) { + if (EEPROMRead (ii, &read_value) != 0) { + printf ("Read Error\n"); + error = 1; + } else { + *mem_ptr = read_value; + mem_ptr++; + } + } + break; + case 'p': + if (argc != 3) { + goto usage; + } + mem_ptr = (unsigned char *) address; + for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); + ii++) { + if (EEPROMWrite (ii, *mem_ptr) != 0) { + printf ("Write Error\n"); + error = 1; + } + + mem_ptr++; + } + break; + case 'd': + if (argc != 2) { + goto usage; + } + for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); + ii++) { + if (EEPROMWrite (ii, default_eeprom[ii]) != 0) { + printf ("Write Error\n"); + error = 1; + } + } + break; + default: + goto usage; + } + + goto done; + usage: + printf ("Usage:\n%s\n", cmdtp->help); + + done: + return ret_val; + +} + +U_BOOT_CMD (eeprom, 4, 0, do_eeprom, + "eeprom - read/write/copy to/from the PowerSpan II eeprom\n", + "eeprom r OFF [NUM]\n" + " - read NUM words starting at OFF\n" + "eeprom w OFF VAL\n" + " - write word VAL at offset OFF\n" + "eeprom g ADD\n" + " - store contents of eeprom at address ADD\n" + "eeprom p ADD\n" + " - put data stored at address ADD into the eeprom\n" + "eeprom d\n" " - return eeprom to default contents\n"); + +unsigned int PowerSpanRead (unsigned int theOffset) +{ + volatile unsigned int *ptr = + (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); + unsigned int ret_val; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("PowerSpanRead: offset=%08x ", theOffset); + } +#endif + ret_val = *ptr; + PSII_SYNC (); + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("value=%08x\n", ret_val); + } +#endif + + return ret_val; +} + +void PowerSpanWrite (unsigned int theOffset, unsigned int theValue) +{ + volatile unsigned int *ptr = + (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset, + theValue); + } +#endif + *ptr = theValue; + PSII_SYNC (); +} + +/** + * Sets the indicated bits in the indicated register. + * @param theOffset [IN] the register to access. + * @param theMask [IN] bits set in theMask will be set in the register. + */ +void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask) +{ + volatile unsigned int *ptr = + (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); + unsigned int register_value; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("PowerSpanSetBits: offset=%08x mask=%02x\n", + theOffset, theMask); + } +#endif + register_value = *ptr; + PSII_SYNC (); + + register_value |= theMask; + *ptr = register_value; + PSII_SYNC (); +} + +/** + * Clears the indicated bits in the indicated register. + * @param theOffset [IN] the register to access. + * @param theMask [IN] bits set in theMask will be cleared in the register. + */ +void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask) +{ + volatile unsigned int *ptr = + (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); + unsigned int register_value; + +#ifdef VERBOSITY + if (gVerbosityLevel > 1) { + printf ("PowerSpanClearBits: offset=%08x mask=%02x\n", + theOffset, theMask); + } +#endif + register_value = *ptr; + PSII_SYNC (); + + register_value &= ~theMask; + *ptr = register_value; + PSII_SYNC (); +} + +/** + * Configures a slave image on the local bus, based on the parameters and some hardcoded system values. + * Slave Images are images that cause the PowerSpan II to be a master on the PCI bus. Thus, they + * are outgoing from the standpoint of the local bus. + * @param theImageIndex [IN] the PowerSpan II image to set (assumed to be 0-7). + * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]). + * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set. + * @param theEndianness [IN] the endian bits for the image (already shifted, use defines). + * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size). + * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size). + */ +int SetSlaveImage (int theImageIndex, unsigned int theBlockSize, + int theMemIOFlag, int theEndianness, + unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr) +{ + unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF; + unsigned int reg_value = 0; + + /* Make sure that the Slave Image is disabled */ + PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset), + PB_SLAVE_CSR_IMG_EN); + + /* Setup the mask required for requested PB Slave Image configuration */ + reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24); + if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) { + reg_value |= PB_SLAVE_CSR_MEM_IO; + } + + /* hardcoding the following: + TA_EN = 1 + MD_EN = 0 + MODE = 0 + PRKEEP = 0 + RD_AMT = 0 + */ + PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value); + + /* these values are not checked by software */ + PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr); + PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr); + + /* Enable the Slave Image */ + PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset), + PB_SLAVE_CSR_IMG_EN); + + return 0; +} + +/** + * Configures a target image on the local bus, based on the parameters and some hardcoded system values. + * Target Images are used when the PowerSpan II is acting as a target for an access. Thus, they + * are incoming from the standpoint of the local bus. + * In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI + * base address will not be updated; makes sense given that the hosts own memory should be mapped to + * PCI address 0x00000000. + * @param theImageIndex [IN] the PowerSpan II image to set. + * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]). + * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set. + * @param theEndianness [IN] the endian bits for the image (already shifted, use defines). + * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size). + * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size). + */ +int SetTargetImage (int theImageIndex, unsigned int theBlockSize, + int theMemIOFlag, int theEndianness, + unsigned int theLocalBaseAddr, + unsigned int thePCIBaseAddr) +{ + unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF; + unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF; + unsigned int reg_value = 0; + + /* Make sure that the Slave Image is disabled */ + PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset), + PB_SLAVE_CSR_IMG_EN); + + /* Setup the mask required for requested PB Slave Image configuration */ + reg_value = + PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) | + PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness; + if (theMemIOFlag == PX_TGT_USE_MEM_IO) { + reg_value |= PX_TGT_MEM_IO; + } + + /* hardcoding the following: + TA_EN = 1 + BAR_EN = 1 + MD_EN = 0 + MODE = 0 + DEST = 0 + RTT = 01010 + GBL = 0 + CI = 0 + WTT = 00010 + PRKEEP = 0 + MRA = 0 + RD_AMT = 0 + */ + PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value); + + PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset), + theLocalBaseAddr); + + if (thePCIBaseAddr != (unsigned int) NULL) { + PowerSpanWrite ((REGS_P1_BST + pci_reg_offset), + thePCIBaseAddr); + } + + /* Enable the Slave Image */ + PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset), + PB_SLAVE_CSR_IMG_EN); + + return 0; +} + +int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + int ret_val = 1; + unsigned int image_index; + unsigned int block_size; + unsigned int mem_io; + unsigned int local_addr; + unsigned int pci_addr; + int endianness; + + if (argc != 8) { + goto usage; + } + + cmd = argv[1][0]; + image_index = simple_strtoul (argv[2], NULL, 16); + block_size = simple_strtoul (argv[3], NULL, 16); + mem_io = simple_strtoul (argv[4], NULL, 16); + endianness = argv[5][0]; + local_addr = simple_strtoul (argv[6], NULL, 16); + pci_addr = simple_strtoul (argv[7], NULL, 16); + + + switch (cmd) { + case 'i': + if (tolower (endianness) == 'b') { + endianness = PX_TGT_CSR_BIG_END; + } else if (tolower (endianness) == 'l') { + endianness = PX_TGT_CSR_TRUE_LEND; + } else { + goto usage; + } + SetTargetImage (image_index, block_size, mem_io, + endianness, local_addr, pci_addr); + break; + case 'o': + if (tolower (endianness) == 'b') { + endianness = PB_SLAVE_CSR_BIG_END; + } else if (tolower (endianness) == 'l') { + endianness = PB_SLAVE_CSR_TRUE_LEND; + } else { + goto usage; + } + SetSlaveImage (image_index, block_size, mem_io, + endianness, local_addr, pci_addr); + break; + default: + goto usage; + } + + goto done; +usage: + printf ("Usage:\n%s\n", cmdtp->help); + +done: + return ret_val; +} diff --git a/board/amirix/ap1000/powerspan.h b/board/amirix/ap1000/powerspan.h new file mode 100644 index 0000000..4e9a8c1 --- /dev/null +++ b/board/amirix/ap1000/powerspan.h @@ -0,0 +1,170 @@ +/** + * @file powerspan.h Header file for PowerSpan II code. + */ + +/* + * (C) Copyright 2005 + * AMIRIX Systems Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef POWERSPAN_H +#define POWERSPAN_H + +#define CLEAR_MASTER_ABORT 0xdeadbeef +#define NO_DEVICE_FOUND -1 +#define ILLEGAL_REG_OFFSET -2 +#define I2C_BUSY -3 +#define I2C_ERR -4 + +#define REG_P1_CSR 0x004 +#define REGS_P1_BST 0x018 +#define REG_P1_ERR_CSR 0x150 +#define REG_P1_MISC_CSR 0x160 +#define REGS_P1_TGT_CSR 0x100 +#define REGS_P1_TGT_TADDR 0x104 +#define REGS_PB_SLAVE_CSR 0x200 +#define REGS_PB_SLAVE_TADDR 0x204 +#define REGS_PB_SLAVE_BADDR 0x208 +#define REG_CONFIG_ADDRESS 0x290 +#define REG_CONFIG_DATA 0x294 +#define REG_PB_ERR_CSR 0x2B0 +#define REG_PB_MISC_CSR 0x2C0 +#define REG_MISC_CSR 0x400 +#define REG_I2C_CSR 0x408 +#define REG_RESET_CSR 0x40C +#define REG_ISR0 0x410 +#define REG_ISR1 0x414 +#define REG_IER0 0x418 +#define REG_MBOX_MAP 0x420 +#define REG_HW_MAP 0x42C +#define REG_IDR 0x444 + +#define CSR_MEMORY_SPACE_ENABLE 0x00000002 +#define CSR_PCI_MASTER_ENABLE 0x00000004 + +#define P1_BST_OFF 0x04 + +#define PX_ERR_ERR_STATUS 0x01000000 + +#define PX_MISC_CSR_MAX_RETRY_MASK 0x00000F00 +#define PX_MISC_CSR_MAX_RETRY 0x00000F00 +#define PX_MISC_REG_BAR_ENABLE 0x00008000 +#define PB_MISC_TEA_ENABLE 0x00000010 +#define PB_MISC_MAC_TEA 0x00000040 + +#define P1_TGT_IMAGE_OFF 0x010 +#define PX_TGT_CSR_IMG_EN 0x80000000 +#define PX_TGT_CSR_TA_EN 0x40000000 +#define PX_TGT_CSR_BAR_EN 0x20000000 +#define PX_TGT_CSR_MD_EN 0x10000000 +#define PX_TGT_CSR_MODE 0x00800000 +#define PX_TGT_CSR_DEST 0x00400000 +#define PX_TGT_CSR_MEM_IO 0x00200000 +#define PX_TGT_CSR_GBL 0x00080000 +#define PX_TGT_CSR_CL 0x00040000 +#define PX_TGT_CSR_PRKEEP 0x00000080 + +#define PX_TGT_CSR_BS_MASK 0x0F000000 +#define PX_TGT_MEM_IO 0x00200000 +#define PX_TGT_CSR_RTT_MASK 0x001F0000 +#define PX_TGT_CSR_RTT_READ 0x000A0000 +#define PX_TGT_CSR_WTT_MASK 0x00001F00 +#define PX_TGT_CSR_WTT_WFLUSH 0x00000200 +#define PX_TGT_CSR_END_MASK 0x00000060 +#define PX_TGT_CSR_BIG_END 0x00000040 +#define PX_TGT_CSR_TRUE_LEND 0x00000060 +#define PX_TGT_CSR_RDAMT_MASK 0x00000007 + +#define PX_TGT_CSR_BS_64MB 0xa +#define PX_TGT_CSR_BS_16MB 0x8 + +#define PX_TGT_USE_MEM_IO 1 +#define PX_TGT_NOT_MEM_IO 0 + +#define PB_SLAVE_IMAGE_OFF 0x010 +#define PB_SLAVE_CSR_IMG_EN 0x80000000 +#define PB_SLAVE_CSR_TA_EN 0x40000000 +#define PB_SLAVE_CSR_MD_EN 0x20000000 +#define PB_SLAVE_CSR_MODE 0x00800000 +#define PB_SLAVE_CSR_DEST 0x00400000 +#define PB_SLAVE_CSR_MEM_IO 0x00200000 +#define PB_SLAVE_CSR_PRKEEP 0x00000080 + +#define PB_SLAVE_CSR_BS_MASK 0x1F000000 +#define PB_SLAVE_CSR_END_MASK 0x00000060 +#define PB_SLAVE_CSR_BIG_END 0x00000040 +#define PB_SLAVE_CSR_TRUE_LEND 0x00000060 +#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007 + +#define PB_SLAVE_USE_MEM_IO 1 +#define PB_SLAVE_NOT_MEM_IO 0 + + +#define MISC_CSR_PCI1_LOCK 0x00000080 + +#define I2C_CSR_ADDR 0xFF000000 /* Specifies I2C Device Address to be Accessed */ +#define I2C_CSR_DATA 0x00FF0000 /* Specifies the Required Data for a Write */ +#define I2C_CSR_DEV_CODE 0x0000F000 /* Device Select. I2C 4-bit Device Code */ +#define I2C_CSR_CS 0x00000E00 /* Chip Select */ +#define I2C_CSR_RW 0x00000100 /* Read/Write */ +#define I2C_CSR_ACT 0x00000080 /* I2C Interface Active */ +#define I2C_CSR_ERR 0x00000040 /* Error */ + +#define I2C_EEPROM_DEV 0xa +#define I2C_EEPROM_CHIP_SEL 0 + +#define I2C_READ 0 +#define I2C_WRITE 1 + +#define RESET_CSR_EEPROM_LOAD 0x00000010 + +#define ISR_CLEAR_ALL 0xFFFFFFFF + +#define IER0_DMA_INTS_EN 0x0F000000 +#define IER0_PCI_1_EN 0x00400000 +#define IER0_HW_INTS_EN 0x003F0000 +#define IER0_MB_INTS_EN 0x000000FF +#define IER0_DEFAULT (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN) + +#define MBOX_MAP_TO_INT4 0xCCCCCCCC + +#define HW_MAP_HW4_TO_INT4 0x000C0000 + +#define IDR_PCI_A_OUT 0x40000000 +#define IDR_MBOX_OUT 0x10000000 + + +int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val); +int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val); +int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val); +int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val); +int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val); +int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val); + +unsigned int PowerSpanRead(unsigned int theOffset); +void PowerSpanWrite(unsigned int theOffset, unsigned int theValue); + +int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag); + +int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val); +int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val); + +int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr); +int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr); + +#endif diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c new file mode 100644 index 0000000..39c4157 --- /dev/null +++ b/board/amirix/ap1000/serial.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2002 + * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +#include + +#if 0 +#include "serial.h" +#endif + +const NS16550_t COM_PORTS[] = + { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 }; + +#undef CFG_DUART_CHAN +#define CFG_DUART_CHAN gComPort +static int gComPort = 0; + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + + (void) NS16550_init (COM_PORTS[0], clock_divisor); + gComPort = 0; + + return 0; +} + +void serial_putc (const char c) +{ + if (c == '\n') { + NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); + } + + NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); +} + +int serial_getc (void) +{ + return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); +} + +int serial_tstc (void) +{ + return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + NS16550_reinit (COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + NS16550_reinit (COM_PORTS[1], clock_divisor); +#endif +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +void kgdb_serial_init (void) +{ +} + +void putDebugChar (int c) +{ + serial_putc (c); +} + +void putDebugStr (const char *str) +{ + serial_puts (str); +} + +int getDebugChar (void) +{ + return serial_getc (); +} + +void kgdb_interruptible (int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds new file mode 100644 index 0000000..109e7fe --- /dev/null +++ b/board/amirix/ap1000/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amirix/ap1000/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/armadillo/Makefile b/board/armadillo/Makefile new file mode 100644 index 0000000..52ea7f2 --- /dev/null +++ b/board/armadillo/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := armadillo.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/armadillo/armadillo.c b/board/armadillo/armadillo.c new file mode 100644 index 0000000..de04c66 --- /dev/null +++ b/board/armadillo/armadillo.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2005 Rowel Atienza + * Armadillo board HT1070 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Activate LED flasher */ + IO_LEDFLSH = 0x40; + + /* arch number MACH_TYPE_ARMADILLO - not official*/ + gd->bd->bi_arch_number = 83; + + /* location of boot parameters */ + gd->bd->bi_boot_params = 0xc0000100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/armadillo/config.mk b/board/armadillo/config.mk new file mode 100644 index 0000000..23c432f --- /dev/null +++ b/board/armadillo/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +#address where u-boot will be relocated +TEXT_BASE = 0xc0f80000 diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c new file mode 100644 index 0000000..037a643 --- /dev/null +++ b/board/armadillo/flash.c @@ -0,0 +1,338 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2005 Rowel Atienza + * Flash driver for armadillo board HT1070 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define FLASH_BANK_SIZE 0x400000 + +/*value used by hermit is 0x200*/ +/*document says sector size is either 64k in low mem reg and 8k in high mem reg*/ +#define MAIN_SECT_SIZE 0x10000 + +#define UNALIGNED_MASK (3) +#define FL_WORD(addr) (*(volatile unsigned short*)(addr)) +#define FLASH_TIMEOUT 20000000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK); + /*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */ + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = + flashbase + j * MAIN_SECT_SIZE; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (FUJ_MANUFACT & FLASH_VENDMASK): + printf ("Fujitsu: "); + break; + default: + printf ("Unknown Vendor "); + break; + } +/* + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): + printf ("28F128J3 (128Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } +*/ + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +/* +Done: ; +*/ +} + +/* + * * Loop until both write state machines complete. + * */ +static unsigned short flash_status_wait (unsigned long addr, + unsigned short value) +{ + unsigned short status; + long timeout = FLASH_TIMEOUT; + + while (((status = (FL_WORD (addr))) != value) && timeout > 0) { + timeout--; + } + return status; +} + +/* + * Loop until the Write State machine is ready, then do a full error + * check. Clear status and leave the flash in Read Array mode; return + * 0 for no error, -1 for error. + */ +static int flash_status_full_check (unsigned long addr, unsigned short value1, + unsigned short value2) +{ + unsigned short status1, status2; + + status1 = flash_status_wait (addr, value1); + status2 = flash_status_wait (addr + 2, value2); + return (status1 != value1 || status2 != value2) ? -1 : 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + int rc = ERR_OK; + unsigned long base; + unsigned long addr; + + if ((info->flash_id & FLASH_VENDMASK) != + (FUJ_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + printf ("Erasing %d sectors starting at sector %2d.\n" + "This make take some time ... ", + s_last - s_first, sect); + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + /* ARM simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + + addr = sect * MAIN_SECT_SIZE; + addr &= ~(unsigned long) UNALIGNED_MASK; /* word align */ + base = addr & 0xF0000000; + + FL_WORD (base + (0x555 << 1)) = 0xAA; + FL_WORD (base + (0x2AA << 1)) = 0x55; + FL_WORD (base + (0x555 << 1)) = 0x80; + FL_WORD (base + (0x555 << 1)) = 0xAA; + FL_WORD (base + (0x2AA << 1)) = 0x55; + FL_WORD (addr) = 0x30; + if (flash_status_full_check (addr, 0xFFFF, 0xFFFF)) + return ERR_PROTECTED; + } + } + printf ("\nDone.\n"); + if (ctrlc ()) + printf ("User Interrupt!\n"); + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (flag) + enable_interrupts (); + + return rc; +} + + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_word (flash_info_t * info, ulong dest, ushort data) +{ + int flag; + unsigned long base; + + /* Check if Flash is (sufficiently) erased + */ + if ((FL_WORD (dest) & data) != data) + return ERR_NOT_ERASED; + + /*if(dest & UNALIGNED_MASK) return ERR_ALIGN; */ + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + base = dest & 0xF0000000; + FL_WORD (base + (0x555 << 1)) = 0xAA; + FL_WORD (base + (0x2AA << 1)) = 0x55; + FL_WORD (base + (0x555 << 1)) = 0xA0; + FL_WORD (dest) = data; + /*printf("writing 0x%p = 0x%x\n",dest,data); */ + if (flash_status_wait (dest, data) != data) + return ERR_PROG_ERROR; + + if (flag) + enable_interrupts (); + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + ushort data; + int l; + int i, rc; + + wp = (addr & ~1); /* get lower word aligned address */ + printf ("Writing %d short data to 0x%p from 0x%p.\n ", cnt, wp, src); + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + printf ("\nDone.\n"); + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_word (info, wp, data); +} diff --git a/board/armadillo/lowlevel_init.S b/board/armadillo/lowlevel_init.S new file mode 100644 index 0000000..6cf6426 --- /dev/null +++ b/board/armadillo/lowlevel_init.S @@ -0,0 +1,66 @@ +/* + * Initialization stuff - taken from hermit + * (C) Copyright 2005 Rowel Atienza + * Armadillo board HT1070 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ +/* setting up the memory */ +#define SRAM_START 0x60000000 +#define SRAM_SIZE 0x0000c000 + +.globl lowlevel_init +lowlevel_init: + mov r0, #0x70 /* 32-bit code + data, MMU mandatory */ + mcr p15, 0, r0, c1, c0, 0 /* MMU init */ + + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + mov r0, #0x80000000 /* I/O base */ + + mov r1, #0x6 /* CLKCTL_73 in SYSCON3 */ + add r2, r0, #0x2200 /* address of SYSCON3 in r2 */ + str r1, [r2] /* set clock speed to 73.728 MHz */ + + mov r1, #0x81 /* 64KHz DRAM refresh period */ + str r1, [r0, #0x200] /* set DRFPR */ + + mov r1, #0x500 /* permanent enable, 16bits wide */ + add r1, r1, #0x42 /* 128Mbit, CAS lat = 2 SDRAM */ + add r2, r0, #0x2300 /* load address in r2 */ + str r1, [r2] + + mov r1, #0x100 /* SDRAM refresh rate */ + add r2, r0, #0x2340 /* load address in r2 */ + str r1, [r2] + + mov sp, #SRAM_START /* init stack pointer */ + add sp, sp, #SRAM_SIZE + + /* everything is fine now */ + mov pc, lr diff --git a/board/armadillo/u-boot.lds b/board/armadillo/u-boot.lds new file mode 100644 index 0000000..64d946c --- /dev/null +++ b/board/armadillo/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/assabet/Makefile b/board/assabet/Makefile new file mode 100644 index 0000000..c49f1b4 --- /dev/null +++ b/board/assabet/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# 2004 (c) MontaVista Software, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := assabet.o +SOBJS := setup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/assabet/assabet.c b/board/assabet/assabet.c new file mode 100644 index 0000000..d3ccbb5 --- /dev/null +++ b/board/assabet/assabet.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +/* + * Board dependent initialisation + */ + +#define ECOR 0x8000 +#define ECOR_RESET 0x80 +#define ECOR_LEVEL_IRQ 0x40 +#define ECOR_WR_ATTRIB 0x04 +#define ECOR_ENABLE 0x01 + +#define ECSR 0x8002 +#define ECSR_IOIS8 0x20 +#define ECSR_PWRDWN 0x04 +#define ECSR_INT 0x02 +#define SMC_IO_SHIFT 2 +#define NCR_0 (*((volatile u_char *)(0x100000a0))) +#define NCR_ENET_OSC_EN (1<<3) + +static inline u8 +readb(volatile u8 * p) +{ + return *p; +} + +static inline void +writeb(u8 v, volatile u8 * p) +{ + *p = v; +} + +static void +smc_init(void) +{ + u8 ecor; + u8 ecsr; + volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25)); + + NCR_0 |= NCR_ENET_OSC_EN; + udelay(100); + + ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; + writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); + udelay(100); + + /* + * The device will ignore all writes to the enable bit while + * reset is asserted, even if the reset bit is cleared in the + * same write. Must clear reset first, then enable the device. + */ + writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); + writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); + + /* + * Set the appropriate byte/word mode. + */ + ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; + ecsr |= ECSR_IOIS8; + writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); + udelay(100); +} + +static void +neponset_init(void) +{ + smc_init(); +} + +int +board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = MACH_TYPE_ASSABET; + gd->bd->bi_boot_params = 0xc0000100; + + neponset_init(); + + return 0; +} + +int +dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/assabet/config.mk b/board/assabet/config.mk new file mode 100644 index 0000000..74cb419 --- /dev/null +++ b/board/assabet/config.mk @@ -0,0 +1,7 @@ +# +# SA-1110 based Intel Assabet board +# +# The Intel Assabet 1 bank of 32 MiB SDRAM +# + +TEXT_BASE = 0xc1f00000 diff --git a/board/assabet/setup.S b/board/assabet/setup.S new file mode 100644 index 0000000..56ea0dd --- /dev/null +++ b/board/assabet/setup.S @@ -0,0 +1,136 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "config.h" +#include "version.h" + + +/*----------------------------------------------------------------------- + * Board defines: + */ + +#define MDCNFG 0x00 +#define MDCAS00 0x04 +#define MDCAS01 0x08 +#define MDCAS02 0x0C +#define MSC0 0x10 +#define MSC1 0x14 +#define MECR 0x18 +#define MDREFR 0x1C +#define MDCAS20 0x20 +#define MDCAS21 0x24 +#define MDCAS22 0x28 +#define MSC2 0x2C +#define SMCNFG 0x30 + +#define ASSABET_BCR (0x12000000) +#define ASSABET_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17)) +#define ASSABET_SCR_nNEPONSET (1 << 9) +#define NEPONSET_LEDS (0x10000010) + + +/*----------------------------------------------------------------------- + * Setup parameters for the board: + */ + + +MEM_BASE: .long 0xa0000000 +MEM_START: .long 0xc0000000 + +mdcnfg: .long 0x72547254 +mdcas00: .long 0xaaaaaa7f +mdcas01: .long 0xaaaaaaaa +mdcas02: .long 0xaaaaaaaa +msc0: .long 0x4b384370 +msc1: .long 0x22212419 +mecr: .long 0x994a994a +mdrefr: .long 0x04340327 +mdcas20: .long 0xaaaaaa7f +mdcas21: .long 0xaaaaaaaa +mdcas22: .long 0xaaaaaaaa +msc2: .long 0x42196669 +smcnfg: .long 0x00000000 + +BCR: .long ASSABET_BCR +BCR_DB1110: .long ASSABET_BCR_DB1110 +LEDS: .long NEPONSET_LEDS + + + .globl lowlevel_init +lowlevel_init: + + /* Setting up the memory and stuff */ + + ldr r0, MEM_BASE + ldr r1, mdcas00 + str r1, [r0, #MDCAS00] + ldr r1, mdcas01 + str r1, [r0, #MDCAS01] + ldr r1, mdcas02 + str r1, [r0, #MDCAS02] + ldr r1, mdcas20 + str r1, [r0, #MDCAS20] + ldr r1, mdcas21 + str r1, [r0, #MDCAS21] + ldr r1, mdcas22 + str r1, [r0, #MDCAS22] + ldr r1, mdrefr + str r1, [r0, #MDREFR] + ldr r1, mecr + str r1, [r0, #MECR] + ldr r1, msc0 + str r1, [r0, #MSC0] + ldr r1, msc1 + str r1, [r0, #MSC1] + ldr r1, msc2 + str r1, [r0, #MSC2] + ldr r1, smcnfg + str r1, [r0, #SMCNFG] + + ldr r1, mdcnfg + str r1, [r0, #MDCNFG] + + /* Load something to activate bank */ + ldr r2, MEM_START +.rept 8 + ldr r3, [r2] +.endr + + /* Enable SDRAM */ + orr r1, r1, #0x00000001 + str r1, [r0, #MDCNFG] + + ldr r1, BCR + ldr r2, BCR_DB1110 + str r2, [r1] + + ldr r1, LEDS + mov r0, #0x3 + str r0, [r1] + + /* All done... */ + mov pc, lr diff --git a/board/assabet/u-boot.lds b/board/assabet/u-boot.lds new file mode 100644 index 0000000..7a3a9b8 --- /dev/null +++ b/board/assabet/u-boot.lds @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile new file mode 100644 index 0000000..ec77da9 --- /dev/null +++ b/board/at91rm9200dk/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := at91rm9200dk.o at45.o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c new file mode 100644 index 0000000..3c00132 --- /dev/null +++ b/board/at91rm9200dk/at45.c @@ -0,0 +1,621 @@ +/* Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#ifdef CONFIG_HAS_DATAFLASH +#include + +#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to +the Continuous Array Read function */ + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define AT91C_TIMEOUT_WRDY 200000 +#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ +#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ + +void AT91F_SpiInit(void) { + +/*-------------------------------------------------------------------*/ +/* SPI DataFlash Init */ +/*-------------------------------------------------------------------*/ + /* Configure PIOs */ + AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; + /* Enable CLock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; + + /* Reset the SPI */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; + + /* Configure SPI in Master Mode with No CS selected !!! */ + AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; + + /* Configure CS0 and CS3 */ + *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + + *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + +} + +void AT91F_SpiEnable(int cs) { + switch(cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); + break; + case 3: /* Configure SPI CS3 for Serial DataFlash Card */ + /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ + AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; + /* Configure PCS */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); + break; + } + + /* SPI_Enable */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; +} + +/*----------------------------------------------------------------------------*/ +/* \fn AT91F_SpiWrite */ +/* \brief Set the PDC registers for a transfert */ +/*----------------------------------------------------------------------------*/ +unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) +{ + unsigned int timeout; + + pDesc->state = BUSY; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + + /* Initialize the Transmit and Receive Pointer */ + AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; + AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; + + /* Intialize the Transmit and Receive Counters */ + AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; + AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; + + if ( pDesc->tx_data_size != 0 ) { + /* Initialize the Next Transmit and Next Receive Pointer */ + AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; + AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; + + /* Intialize the Next Transmit and Next Receive Counters */ + AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; + AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + timeout = 0; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; + while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + pDesc->state = IDLE; + + if (timeout >= CFG_SPI_WRITE_TOUT){ + printf("Error Timeout\n\r"); + return DATAFLASH_ERROR; + } + + return DATAFLASH_OK; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashSendCommand */ +/* \brief Generic function to send a command to the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashSendCommand( + AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress) +{ + unsigned int adr; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* process the address to obtain page address and byte address */ + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); + + /* fill the command buffer */ + pDataFlash->pDataFlashDesc->command[0] = OpCode; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); + } else { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + } + pDataFlash->pDataFlashDesc->command[5] = 0; + pDataFlash->pDataFlashDesc->command[6] = 0; + pDataFlash->pDataFlashDesc->command[7] = 0; + + /* Initialize the SpiData structure for the spi write fuction */ + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; + + /* send the command and read the data */ + return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashGetStatus */ +/* \brief Read the status register of the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) +{ + AT91S_DataFlashStatus status; + + /* if a transfert is in progress ==> return 0 */ + if( (pDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* first send the read status command (D7H) */ + pDesc->command[0] = DB_STATUS; + pDesc->command[1] = 0; + + pDesc->DataFlash_state = GET_STATUS; + pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ + pDesc->tx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_size = 2 ; + pDesc->tx_cmd_size = 2 ; + status = AT91F_SpiWrite (pDesc); + + pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); + + return status; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashWaitReady */ +/* \brief wait for dataflash ready (bit7 of the status register == 1) */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) +{ + pDataFlashDesc->DataFlash_state = IDLE; + + do { + AT91F_DataFlashGetStatus(pDataFlashDesc); + timeout--; + } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); + + if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) + return DATAFLASH_ERROR; + + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashContinuousRead */ +/* Object : Continuous stream Read */ +/* Input Parameters : DataFlash Service */ +/* : = dataflash address */ +/* : <*dataBuffer> = data buffer pointer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead ) +{ + AT91S_DataFlashStatus status; + /* Test the size to read in the device */ + if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; + + status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); + /* Send the command to the dataflash */ + return(status); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashPagePgmBuf */ +/* Object : Main memory page program through buffer 1 or buffer 2 */ +/* Input Parameters : DataFlash Service */ +/* : <*src> = Source buffer */ +/* : = dataflash destination address */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int SizeToWrite) +{ + int cmdsize; + pDataFlash->pDataFlashDesc->tx_data_pt = src ; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; + pDataFlash->pDataFlashDesc->rx_data_pt = src; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; + + cmdsize = 4; + /* Send the command to the dataflash */ + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_MainMemoryToBufferTransfert */ +/* Object : Read a page in the SRAM Buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); +} + + +/*----------------------------------------------------------------------------- */ +/* Function Name : AT91F_DataFlashWriteBuffer */ +/* Object : Write data to the internal sram buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : = command to write buffer1 or buffer2 */ +/* : <*dataBuffer> = data buffer to write */ +/* : = address in the internal buffer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite ) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) + return DATAFLASH_BAD_COMMAND; + + /* buffer address must be lower than page size */ + if (bufferAddress > pDataFlash->pDevice->pages_size) + return DATAFLASH_BAD_ADDRESS; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* Send first Write Command */ + pDataFlash->pDataFlashDesc->command[0] = BufferCommand; + pDataFlash->pDataFlashDesc->command[1] = 0; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[2] = 0; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + cmdsize = 5; + } else { + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + cmdsize = 4; + } + + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; + + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PageErase */ +/* Object : Erase a page */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_BlockErase */ +/* Object : Erase a Block */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_BlockErase( + AT91PS_DataFlash pDataFlash, + unsigned int block) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_WriteBufferToMain */ +/* Object : Write buffer to the main memory */ +/* Input Parameters : DataFlash Service */ +/* : = command to send to buffer1 or buffer2 */ +/* : = main memory address */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_WriteBufferToMain ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest ) +{ + int cmdsize; + /* Test if the buffer command is correct */ + if ((BufferCommand != DB_BUF1_PAGE_PGM) && + (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && + (BufferCommand != DB_BUF2_PAGE_PGM) && + (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + /* Send the command to the dataflash */ + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PartialPageWrite */ +/* Object : Erase partielly a page */ +/* Input Parameters : = page number */ +/* : = adr to begin the fading */ +/* : = Number of bytes to erase */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PartialPageWrite ( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size) +{ + unsigned int page; + unsigned int AdrInPage; + + page = dest / (pDataFlash->pDevice->pages_size); + AdrInPage = dest % (pDataFlash->pDevice->pages_size); + + /* Read the contents of the page in the Sram Buffer */ + AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + /*Update the SRAM buffer */ + AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Erase page if a 128 Mbits device */ + if (pDataFlash->pDevice->pages_number >= 16384) { + AT91F_PageErase(pDataFlash, page); + /* Rewrite the modified Sram Buffer in the main memory */ + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + } + + /* Rewrite the modified Sram Buffer in the main memory */ + return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashWrite */ +/* Object : */ +/* Input Parameters : <*src> = Source buffer */ +/* : = dataflash adress */ +/* : = data buffer size */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWrite( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ) +{ + unsigned int length; + unsigned int page; + unsigned int status; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + /* If destination does not fit a page start address */ + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { + length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); + + if (size < length) + length = size; + + if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= length; + dest += length; + src += length; + } + + while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { + /* program dataflash page */ + page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); + + status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + status = AT91F_PageErase(pDataFlash, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + if (!status) + return DATAFLASH_ERROR; + + status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); + if(!status) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= pDataFlash->pDevice->pages_size ; + dest += pDataFlash->pDevice->pages_size ; + src += pDataFlash->pDevice->pages_size ; + } + + /* If still some bytes to read */ + if ( size > 0 ) { + /* program dataflash page */ + if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + } + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashRead */ +/* Object : Read a block in dataflash */ +/* Input Parameters : */ +/* Return value : */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataFlashRead( + AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, + char *buffer) +{ + unsigned long SizeToRead; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + while (size) { + SizeToRead = (size < 0x8000)? size:0x8000; + + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) + return -1; + + size -= SizeToRead; + addr += SizeToRead; + buffer += SizeToRead; + } + + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataflashProbe */ +/* Object : */ +/* Input Parameters : */ +/* Return value : Dataflash status register */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) +{ + AT91F_SpiEnable(cs); + AT91F_DataFlashGetStatus(pDesc); + return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); +} + +#endif diff --git a/board/at91rm9200dk/at91rm9200dk.c b/board/at91rm9200dk/at91rm9200dk.c new file mode 100644 index 0000000..77caed3 --- /dev/null +++ b/board/at91rm9200dk/at91rm9200dk.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Enable Ctrlc */ + console_init_f (); + + /* Correct IRDA resistor problem */ + /* Set PA23_TXD in Output */ + (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of AT91RM9200DK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_DRIVER_ETHER +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * at91rm9200_GetPhyInterface + * Description: + * Initialise the interface functions to the PHY + * Arguments: + * None + * Return value: + * None + */ +void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) +{ + p_phyops->Init = dm9161_InitPhy; + p_phyops->IsPhyConnected = dm9161_IsPhyConnected; + p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; + p_phyops->AutoNegotiate = dm9161_AutoNegotiate; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif /* CONFIG_DRIVER_ETHER */ + +/* + * Disk On Chip (NAND) Millenium initialization. + * The NAND lives in the CS2* space + */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +extern ulong nand_probe (ulong physadr); + +#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ +void nand_init (void) +{ + /* Setup Smart Media, fitst enable the address range of CS3 */ + *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia; + /* set the bus interface characteristics based on + tDS Data Set up Time 30 - ns + tDH Data Hold Time 20 - ns + tALS ALE Set up Time 20 - ns + 16ns at 60 MHz ~= 3 */ +/*memory mapping structures */ +#define SM_ID_RWH (5 << 28) +#define SM_RWH (1 << 28) +#define SM_RWS (0 << 24) +#define SM_TDF (1 << 8) +#define SM_NWS (3) + AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS | + AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 | + SM_TDF | AT91C_SMC2_WSEN | SM_NWS); + + /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */ + *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | + AT91C_PC3_BFBAA_SMWE; + *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | + AT91C_PC3_BFBAA_SMWE; + + /* Configure PC2 as input (signal READY of the SmartMedia) */ + *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */ + *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */ + + /* Configure PB1 as input (signal Card Detect of the SmartMedia) */ + *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */ + *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */ + + /* PIOB and PIOC clock enabling */ + *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; + *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; + + if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1) + printf (" No SmartMedia card inserted\n"); +#ifdef DEBUG + printf (" SmartMedia card inserted\n"); + + printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE); +#endif + printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20); +} +#endif diff --git a/board/at91rm9200dk/config.mk b/board/at91rm9200dk/config.mk new file mode 100644 index 0000000..9ce161e --- /dev/null +++ b/board/at91rm9200dk/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x21f00000 diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c new file mode 100644 index 0000000..f6228ef --- /dev/null +++ b/board/at91rm9200dk/flash.c @@ -0,0 +1,504 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +ulong myflush(void); + + +/* Flash Organization Structure */ +typedef struct OrgDef +{ + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgAT49BV16x4[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ + { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ +}; + +OrgDef OrgAT49BV16x4A[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ +}; + +OrgDef OrgAT49BV6416[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ +}; + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/* AT49BV1614A Codes */ +#define FLASH_CODE1 0xAA +#define FLASH_CODE2 0x55 +#define ID_IN_CODE 0x90 +#define ID_OUT_CODE 0xF0 + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 +#define CMD_SECTOR_UNLOCK 0x0070 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ +void flash_identification (flash_info_t * info) +{ + volatile u16 manuf_code, device_code, add_device_code; + + MEM_FLASH_ADDR1 = FLASH_CODE1; + MEM_FLASH_ADDR2 = FLASH_CODE2; + MEM_FLASH_ADDR1 = ID_IN_CODE; + + manuf_code = *(volatile u16 *) CFG_FLASH_BASE; + device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2); + add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1)); + + MEM_FLASH_ADDR1 = FLASH_CODE1; + MEM_FLASH_ADDR2 = FLASH_CODE2; + MEM_FLASH_ADDR1 = ID_OUT_CODE; + + /* Vendor type */ + info->flash_id = ATM_MANUFACT & FLASH_VENDMASK; + printf ("Atmel: "); + + if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { + + if ((add_device_code & FLASH_TYPEMASK) == + (ATM_ID_BV1614A & FLASH_TYPEMASK)) { + info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; + printf ("AT49BV1614A (16Mbit)\n"); + } else { /* AT49BV1614 Flash */ + info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; + printf ("AT49BV1614 (16Mbit)\n"); + } + + } else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { + info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; + printf ("AT49BV6416 (64Mbit)\n"); + } +} + +ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) +{ + int i, nb_sectors = 0; + + for (i=0; istart[sector]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + *addr = CMD_SECTOR_UNLOCK; +} + + +ulong flash_init (void) +{ + int i, j, k; + unsigned int flash_nb_blocks, sector; + unsigned int start_address; + OrgDef *pOrgDef; + + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_identification (&flash_info[i]); + + if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV1614 & FLASH_TYPEMASK)) { + + pOrgDef = OrgAT49BV16x4; + flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); + } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */ + + pOrgDef = OrgAT49BV16x4A; + flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef); + } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ + + pOrgDef = OrgAT49BV6416; + flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); + } else { + flash_nb_blocks = 0; + pOrgDef = OrgAT49BV16x4; + } + + flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); + memset (flash_info[i].protect, 0, flash_info[i].sector_count); + + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + + sector = 0; + start_address = flashbase; + flash_info[i].size = 0; + + for (j = 0; j < flash_nb_blocks; j++) { + for (k = 0; k < pOrgDef[j].sector_number; k++) { + flash_info[i].start[sector++] = start_address; + start_address += pOrgDef[j].sector_size; + flash_info[i].size += pOrgDef[j].sector_size; + } + } + + size += flash_info[i].size; + + if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ + + /* Unlock all sectors at reset */ + for (j=0; jflash_id & FLASH_VENDMASK) { + case (ATM_MANUFACT & FLASH_VENDMASK): + printf ("Atmel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (ATM_ID_BV1614 & FLASH_TYPEMASK): + printf ("AT49BV1614 (16Mbit)\n"); + break; + case (ATM_ID_BV1614A & FLASH_TYPEMASK): + printf ("AT49BV1614A (16Mbit)\n"); + break; + case (ATM_ID_BV6416 & FLASH_TYPEMASK): + printf ("AT49BV6416 (64Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + return; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (ATM_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_word (flash_info_t * info, ulong dest, + ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + }; + + if ((int) src & 1) { + printf ("unaligned source not supported\n"); + return ERR_ALIGN; + }; + + wp = addr; + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << + 8); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + }; + + return ERR_OK; +} diff --git a/board/at91rm9200dk/u-boot.lds b/board/at91rm9200dk/u-boot.lds new file mode 100644 index 0000000..f4fbf96 --- /dev/null +++ b/board/at91rm9200dk/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/atc/Makefile b/board/atc/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/atc/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/atc/atc.c b/board/atc/atc.c new file mode 100644 index 0000000..d2c6b3b --- /dev/null +++ b/board/atc/atc.c @@ -0,0 +1,399 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ + /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ + /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ + /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ + /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ + /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ +#if 1 + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ +#else + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ +#endif + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ + /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ + /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ + /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ + /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ + /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ + /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ +#if 0 + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ +#else + /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */ +#endif + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ + /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ + /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ +#if 0 + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ +#else + /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */ +#endif + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ + } +}; + +/* + * UPMB initialization table + */ +#define _NOT_USED_ 0xFFFFFFFF + +static const uint rtc_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800, + 0xfaf2080, 0xfaf2080, 0xfff2400, 0x1fff6c05, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800, + 0xfaf2080, 0xfaf2080, 0xfaf2400, 0x1fbf6c05, /* last */ + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + printf ("Board: ATC\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +int misc_init_r(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + + upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint)); + memctl->memc_mamr = MxMR_RLFx_6X | MxMR_WLFx_6X | MxMR_OP_NORM; + + return (0); +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + ulong size8, size9; +#endif + long psize; + + psize = 8 * 1024 * 1024; + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CFG_PSRT; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL) "); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL) "); + } + +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/atc/config.mk b/board/atc/config.mk new file mode 100644 index 0000000..eee7a60 --- /dev/null +++ b/board/atc/config.mk @@ -0,0 +1,38 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# ATC boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_atc.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# + +TEXT_BASE := 0xFF000000 + +# RAM version +#TEXT_BASE := 0x100000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/atc/flash.c b/board/atc/flash.c new file mode 100644 index 0000000..2ab60e8 --- /dev/null +++ b/board/atc/flash.c @@ -0,0 +1,663 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static void flash_get_offsets(ulong base, flash_info_t *info); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { +#if 0 + ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; +#else + ulong flashbase = CFG_FLASH_BASE; +#endif + + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + flash_info[i].size = + flash_get_size((FPW *)flashbase, &flash_info[i]); + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", + i, flash_info[i].size); + } + + size += flash_info[i].size; + } + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL + && (info->flash_id & FLASH_BTYPE)) { + int bootsect_size; /* number of bytes/boot sector */ + int sect_size; /* number of bytes/regular sector */ + + bootsect_size = 0x00002000 * (sizeof(FPW)/2); + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < 8; ++i) { + info->start[i] = base + (i * bootsect_size); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i - 7) * sect_size); + } + } + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set up sector start address table (uniform sector type) */ + for( i = 0; i < info->sector_count; i++ ) + info->start[i] = base + (i * sect_size); + } +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->start[0] <= base && base < info->start[0] + info->size) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + char *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM640U: + fmt = "29LV641D (64 Mbit, uniform sectors)\n"; + break; + case FLASH_28F800C3B: + case FLASH_28F800C3T: + fmt = "28F800C3%s (8 Mbit, %s)\n"; + break; + case FLASH_INTEL800B: + case FLASH_INTEL800T: + fmt = "28F800B3%s (8 Mbit, %s)\n"; + break; + case FLASH_28F160C3B: + case FLASH_28F160C3T: + fmt = "28F160C3%s (16 Mbit, %s)\n"; + break; + case FLASH_INTEL160B: + case FLASH_INTEL160T: + fmt = "28F160B3%s (16 Mbit, %s)\n"; + break; + case FLASH_28F320C3B: + case FLASH_28F320C3T: + fmt = "28F320C3%s (32 Mbit, %s)\n"; + break; + case FLASH_INTEL320B: + case FLASH_INTEL320T: + fmt = "28F320B3%s (32 Mbit, %s)\n"; + break; + case FLASH_28F640C3B: + case FLASH_28F640C3T: + fmt = "28F640C3%s (64 Mbit, %s)\n"; + break; + case FLASH_INTEL640B: + case FLASH_INTEL640T: + fmt = "28F640B3%s (64 Mbit, %s)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + /* Write auto select command: read Manufacturer ID */ + + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(100); + switch (addr[0] & 0xff) { + + case (uchar)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { + + case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F800C3B: + info->flash_id += FLASH_28F800C3B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F800B3B: + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F160B3B: + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F320B3B: + info->flash_id += FLASH_INTEL320B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F640B3B: + info->flash_id += FLASH_INTEL640B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets((ulong)addr, info); + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_INTEL800B: + case FLASH_INTEL160B: + case FLASH_INTEL320B: + case FLASH_INTEL640B: + case FLASH_28F800C3B: + case FLASH_28F160C3B: + case FLASH_28F320C3B: + case FLASH_28F640C3B: + case FLASH_AM640U: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + if (intel) { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW)0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) {/* every second */ + putc ('.'); + last = get_timer(0); + } + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { /* every second */ + putc ('.'); + last = get_timer(0); + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + case FLASH_MAN_INTEL: + res = write_word_intel(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for Intel FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + *dest = (FPW)0x00400040; /* program setup */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00B000B0; /* Suspend program */ + res = 1; + } + } + + if (res == 0 && (*dest & (FPW)0x00100010)) + res = 1; /* write failed, time out error is close enough */ + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + + return (res); +} diff --git a/board/atc/u-boot.lds b/board/atc/u-boot.lds new file mode 100644 index 0000000..eee83d0 --- /dev/null +++ b/board/atc/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/barco/Makefile b/board/barco/Makefile new file mode 100644 index 0000000..d6bbf2f --- /dev/null +++ b/board/barco/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/barco/README b/board/barco/README new file mode 100644 index 0000000..d255a3d --- /dev/null +++ b/board/barco/README @@ -0,0 +1,11 @@ +This port of U-Boot is tuned to run on a range of Barco Control Rooms +Streaming Video Solutions, including: + + - Streaming Video Card (SVC) + - Sample Compress Network (SCN) + +For more information, see http://www.barcocontrolrooms.com/ + +Code and configuration are originally based on the Sandpoint board + +Marc Leeman diff --git a/board/barco/barco.c b/board/barco/barco.c new file mode 100644 index 0000000..becbd0a --- /dev/null +++ b/board/barco/barco.c @@ -0,0 +1,363 @@ +/******************************************************************** + * + * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms + * + * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco.c,v $ + * $Revision: 1.4 $ + * $Author: mleeman $ + * $Date: 2005/03/02 16:40:20 $ + * + * Last ChangeLog Entry + * $Log: barco.c,v $ + * Revision 1.4 2005/03/02 16:40:20 mleeman + * remove empty labels (3.4 complains) + * + * Revision 1.3 2005/02/21 12:48:58 mleeman + * update of copyright years (feedback wd) + * + * Revision 1.2 2005/02/21 10:10:53 mleeman + * - split up switch statement to a function call (Linux kernel coding guidelines) + * ( feedback wd) + * + * Revision 1.1 2005/02/14 09:31:07 mleeman + * renaming of files + * + * Revision 1.1 2005/02/14 09:23:46 mleeman + * - moved 'barcohydra' directory to a more generic barco; since we will be + * supporting and adding multiple boards + * + * Revision 1.3 2005/02/10 13:57:32 mleeman + * fixed flash corruption: I should exit from the moment I find the correct value + * + * Revision 1.2 2005/02/09 12:56:23 mleeman + * add generic header to track changes in sources + * + * + *******************************************************************/ + +/* + * (C) Copyright 2004 + * Marc Leeman + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "config.h" +#include "barco_svc.h" + +#define TRY_WORKING (3) +#define BOOT_DEFAULT (2) +#define BOOT_WORKING (1) + +int checkboard (void) +{ + /*TODO: Check processor type */ + + puts ( "Board: Streaming Video Card for Hydra systems " +#ifdef CONFIG_MPC8240 + "8240" +#endif +#ifdef CONFIG_MPC8245 + "8245" +#endif + " Unity ##Test not implemented yet##\n"); + return 0; +} + +long int initdram (int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size (CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg (MEAR1); + emear1 = mpc824x_mpc107_getreg (EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg (MEAR1, mear1); + mpc824x_mpc107_setreg (EMEAR1, emear1); + + return (size); +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_barcohydra_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_barcohydra_config_table, +#endif +}; + +void pci_init_board (void) +{ + pci_mpc824x_init (&hose); +} + +int write_flash (char *addr, char value) +{ + char *adr = (char *)0xFF800000; + int cnt = 0; + char status,oldstatus; + + *(adr+0x55) = 0xAA; udelay (1); + *(adr+0xAA) = 0x55; udelay (1); + *(adr+0x55) = 0xA0; udelay (1); + *addr = value; + + status = *addr; + do { + oldstatus = status; + status = *addr; + + if ((oldstatus & 0x40) == (status & 0x40)) { + return 4; + } + cnt++; + if (cnt > 10000) { + return 2; + } + } while ( (status & 0x20) == 0 ); + + oldstatus = *addr; + status = *addr; + + if ((oldstatus & 0x40) == (status & 0x40)) { + return 0; + } else { + *(adr+0x55) = 0xF0; + return 1; + } +} + +unsigned update_flash (unsigned char *buf) +{ + switch ((*buf) & 0x3) { + case TRY_WORKING: + printf ("found 3 and converted it to 2\n"); + write_flash ((char *)buf, (*buf) & 0xFE); + *((unsigned char *)0xFF800000) = 0xF0; + udelay (100); + printf ("buf [%#010x] %#010x\n", buf, (*buf)); + /* XXX - fall through??? */ + case BOOT_WORKING : + return BOOT_WORKING; + } + return BOOT_DEFAULT; +} + +unsigned scan_flash (void) +{ + char section[] = "kernel"; + int cfgFileLen = (CFG_FLASH_ERASE_SECTOR_LENGTH >> 1); + int sectionPtr = 0; + int foundItem = 0; /* 0: None, 1: section found, 2: "=" found */ + int bufPtr; + unsigned char *buf; + + buf = (unsigned char*)(CFG_FLASH_RANGE_BASE + CFG_FLASH_RANGE_SIZE \ + - CFG_FLASH_ERASE_SECTOR_LENGTH); + for (bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr) { + if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) { + return BOOT_DEFAULT; + } + /* This is the scanning loop, we try to find a particular + * quoted value + */ + switch (foundItem) { + case 0: + if ((section[sectionPtr] == 0)) { + ++foundItem; + } else if (buf[bufPtr] == section[sectionPtr]) { + ++sectionPtr; + } else { + sectionPtr = 0; + } + break; + case 1: + ++foundItem; + break; + case 2: + ++foundItem; + break; + case 3: + default: + return update_flash (&buf[bufPtr - 1]); + } + } + + printf ("Failed to read %s\n",section); + return BOOT_DEFAULT; +} + +TSBootInfo* find_boot_info (void) +{ + unsigned bootimage = scan_flash (); + TSBootInfo* info = (TSBootInfo*)malloc (sizeof(TSBootInfo)); + + switch (bootimage) { + case TRY_WORKING: + info->address = CFG_WORKING_KERNEL_ADDRESS; + break; + case BOOT_WORKING : + info->address = CFG_WORKING_KERNEL_ADDRESS; + break; + case BOOT_DEFAULT: + default: + info->address= CFG_DEFAULT_KERNEL_ADDRESS; + + } + info->size = *((unsigned int *)(info->address )); + + return info; +} + +void barcobcd_boot (void) +{ + TSBootInfo* start; + char *bootm_args[2]; + char *buf; + int cnt; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + + buf = (char *)(0x00800000); + /* make certain there are enough chars to print the command line here! + */ + bootm_args[0] = (char *)malloc (16*sizeof(char)); + bootm_args[1] = (char *)malloc (16*sizeof(char)); + + start = find_boot_info (); + + printf ("Booting kernel at address %#10x with size %#10x\n", + start->address, start->size); + + /* give length of the kernel image to bootm */ + sprintf (bootm_args[0],"%x",start->size); + /* give address of the kernel image to bootm */ + sprintf (bootm_args[1],"%x",buf); + + printf ("flash address: %#10x\n",start->address+8); + printf ("buf address: %#10x\n",buf); + + /* aha, we reserve 8 bytes here... */ + for (cnt = 0; cnt < start->size ; cnt++) { + buf[cnt] = ((char *)start->address)[cnt+8]; + } + + /* initialise RAM memory */ + *((unsigned int *)0xFEC00000) = 0x00141A98; + do_bootm (NULL,0,2,bootm_args); +} + +int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if 0 + if (argc > 1) { + printf ("Usage:\n (%d) %s\n", argc, cmdtp->usage); + return 1; + } +#endif + barcobcd_boot (); + + return 0; +} + +/* Currently, boot_working and boot_default are the same command. This is + * left in here to see what we'll do in the future */ + +U_BOOT_CMD ( + try_working, 1, 1, barcobcd_boot_image, + " try_working - check flash value and boot the appropriate image\n", + "\n" + ); + +U_BOOT_CMD ( + boot_working, 1, 1, barcobcd_boot_image, + " boot_working - check flash value and boot the appropriate image\n", + "\n" + ); + +U_BOOT_CMD ( + boot_default, 1, 1, barcobcd_boot_image, + " boot_default - check flash value and boot the appropriate image\n", + "\n" + ); +/* + * We are not using serial communication, so just provide empty functions + */ +int serial_init (void) +{ + return 0; +} +void serial_setbrg (void) +{ + return; +} +void serial_putc (const char c) +{ + return; +} +void serial_puts (const char *c) +{ + return; +} +void serial_addr (unsigned int i) +{ + return; +} +int serial_getc (void) +{ + return 0; +} +int serial_tstc (void) +{ + return 0; +} + +unsigned long post_word_load (void) +{ + return 0l; +} +void post_word_store (unsigned long val) +{ + return; +} diff --git a/board/barco/barco_svc.h b/board/barco/barco_svc.h new file mode 100644 index 0000000..088f61e --- /dev/null +++ b/board/barco/barco_svc.h @@ -0,0 +1,68 @@ +/******************************************************************** + * + * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms + * + * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco_svc.h,v $ + * $Revision: 1.2 $ + * $Author: mleeman $ + * $Date: 2005/02/21 12:48:58 $ + * + * Last ChangeLog Entry + * $Log: barco_svc.h,v $ + * Revision 1.2 2005/02/21 12:48:58 mleeman + * update of copyright years (feedback wd) + * + * Revision 1.1 2005/02/14 09:31:07 mleeman + * renaming of files + * + * Revision 1.1 2005/02/14 09:23:46 mleeman + * - moved 'barcohydra' directory to a more generic barco; since we will be + * supporting and adding multiple boards + * + * Revision 1.1 2005/02/08 15:40:19 mleeman + * modified and added platform files + * + * Revision 1.2 2005/01/25 08:05:04 mleeman + * more cleanup of the code + * + * Revision 1.1 2004/07/20 08:49:55 mleeman + * Working version of the default and nfs kernel booting. + * + * + *******************************************************************/ + +#ifndef _LOCAL_BARCOHYDRA_H_ +#define _LOCAL_BARCOHYDRA_H_ + +#include +#include + +/* Defines for the barcohydra board */ +#ifndef CFG_FLASH_ERASE_SECTOR_LENGTH +#define CFG_FLASH_ERASE_SECTOR_LENGTH (0x10000) +#endif + +#ifndef CFG_DEFAULT_KERNEL_ADDRESS +#define CFG_DEFAULT_KERNEL_ADDRESS (CFG_FLASH_BASE + 0x30000) +#endif + +#ifndef CFG_WORKING_KERNEL_ADDRESS +#define CFG_WORKING_KERNEL_ADDRESS (0xFFE00000) +#endif + + +typedef struct SBootInfo { + unsigned int address; + unsigned int size; + unsigned char state; +}TSBootInfo; + +/* barcohydra.c */ +int checkboard(void); +long int initdram(int board_type); +void pci_init_board(void); +void check_flash(void); +int write_flash(char *addr, char value); +TSBootInfo* find_boot_info(void); +void final_boot(void); +#endif diff --git a/board/barco/config.mk b/board/barco/config.mk new file mode 100644 index 0000000..f950c07 --- /dev/null +++ b/board/barco/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Barco Hydra/SCN boards +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/barco/early_init.S b/board/barco/early_init.S new file mode 100644 index 0000000..07dafb7 --- /dev/null +++ b/board/barco/early_init.S @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2001 + * Thomas Koeller, tkoeller@gmx.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ 1 +#endif + +#include +#include +#include +#include + +#if defined(USE_DINK32) + /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ + #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) +#else + #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) +#endif + + .text + + /* Values to program into memory controller registers */ +tbl: .long MCCR1, MCCR1VAL + .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT + .long MCCR3 + .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ + (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ + (CFG_RDLAT << MCCR3_RDLAT_SHIFT) + .long MCCR4 + .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ + (CFG_REGISTERD_TYPE_BUFFER << 20) | \ + (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ + ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ + (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ + (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ + ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) + .long MSAR1 + .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMSAR1 + .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MSAR2 + .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMSAR2 + .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MEAR1 + .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMEAR1 + .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MEAR2 + .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMEAR2 + .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long 0 + + + /* + * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This + * must be done in assembly, since we have no stack at this point. + */ + .global early_init_f +early_init_f: + mflr r10 + + /* basic memory controller configuration */ + lis r3, CONFIG_ADDR_HIGH + lis r4, CONFIG_DATA_HIGH + bl lab +lab: mflr r5 + lwzu r0, tbl - lab(r5) +loop: lwz r1, 4(r5) + stwbrx r0, 0, r3 + eieio + stwbrx r1, 0, r4 + eieio + lwzu r0, 8(r5) + cmpli cr0, 0, r0, 0 + bne cr0, loop + + /* set bank enable bits */ + lis r0, MBER@h + ori r0, 0, MBER@l + li r1, CFG_BANK_ENABLE + stwbrx r0, 0, r3 + eieio + stb r1, 0(r4) + eieio + + /* delay loop */ + lis r0, 0x0003 + mtctr r0 +delay: bdnz delay + + /* enable memory controller */ + lis r0, MCCR1@h + ori r0, 0, MCCR1@l + stwbrx r0, 0, r3 + eieio + lwbrx r0, 0, r4 + oris r0, 0, MCCR1_MEMGO@h + stwbrx r0, 0, r4 + eieio + + /* set up stack pointer */ + lis r1, CFG_INIT_SP_OFFSET@h + ori r1, r1, CFG_INIT_SP_OFFSET@l + + mtlr r10 + blr diff --git a/board/barco/flash.c b/board/barco/flash.c new file mode 100644 index 0000000..6cb19b7 --- /dev/null +++ b/board/barco/flash.c @@ -0,0 +1,611 @@ +/******************************************************************** + * + * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms + * + * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/flash.c,v $ + * $Revision: 1.3 $ + * $Author: mleeman $ + * $Date: 2005/02/21 12:48:58 $ + * + * Last ChangeLog Entry + * $Log: flash.c,v $ + * Revision 1.3 2005/02/21 12:48:58 mleeman + * update of copyright years (feedback wd) + * + * Revision 1.2 2005/02/21 11:04:04 mleeman + * remove dead code and Coding style (feedback wd) + * + * Revision 1.1 2005/02/14 09:23:46 mleeman + * - moved 'barcohydra' directory to a more generic barco; since we will be + * supporting and adding multiple boards + * + * Revision 1.2 2005/02/09 12:56:23 mleeman + * add generic header to track changes in sources + * + * + *******************************************************************/ + +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define ROM_CS0_START 0xFF800000 +#define ROM_CS1_START 0xFF000000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*flash command address offsets*/ + +#define ADDR0 (0xAAA) +#define ADDR1 (0x555) +#define ADDR3 (0x001) + +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------- + */ + +static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const)); + +typedef struct{ + FLASH_WORD_SIZE extval; + unsigned short intval; +} map_entry; + +static unsigned long flash_id(unsigned char mfct, unsigned char chip) +{ + static const map_entry mfct_map[] = { + {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, + {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, + {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, + {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, + {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, + {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} + }; + + static const map_entry chip_map[] = { + {AMD_ID_F040B, FLASH_AM040}, + {AMD_ID_F033C, FLASH_AM033}, + {AMD_ID_F065D, FLASH_AM065}, + {ATM_ID_LV040, FLASH_AT040}, + {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} + }; + + const map_entry *p; + unsigned long result = FLASH_UNKNOWN; + + /* find chip id */ + for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++){ + if(p->extval == chip){ + result = FLASH_VENDMASK | p->intval; + break; + } + } + + /* find vendor id */ + for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++){ + if(p->extval == mfct){ + result &= ~FLASH_VENDMASK; + result |= (unsigned long) p->intval << 16; + break; + } + } + + return result; +} + + +unsigned long flash_init(void) +{ + unsigned long i; + unsigned char j; + static const ulong flash_banks[] = CFG_FLASH_BANKS; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++){ + flash_info_t * const pflinfo = &flash_info[i]; + pflinfo->flash_id = FLASH_UNKNOWN; + pflinfo->size = 0; + pflinfo->sector_count = 0; + } + + /* Enable writes to Hydra/Argus flash */ + { + register unsigned int temp; + CONFIG_READ_WORD(PICR1,temp); + temp |= PICR1_FLASH_WR_EN; + CONFIG_WRITE_WORD(PICR1,temp); + } + + for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++){ + flash_info_t * const pflinfo = &flash_info[i]; + const unsigned long base_address = flash_banks[i]; + volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address; + + /* write autoselect sequence */ + flash[0x5555] = 0xaa; + flash[0x2aaa] = 0x55; + flash[0x5555] = 0x90; + __asm__ __volatile__("sync"); + + pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]); + + switch(pflinfo->flash_id & FLASH_TYPEMASK){ + case FLASH_AM033: + pflinfo->size = 0x00200000; + pflinfo->sector_count = 64; + for(j = 0; j < 64; j++){ + pflinfo->start[j] = base_address + 0x00010000 * j; + pflinfo->protect[j] = flash[(j << 16) | 0x2]; + } + break; + case FLASH_AM065: + pflinfo->size = 0x00800000; + pflinfo->sector_count =128; + for(j = 0; j < 128; j++){ + pflinfo->start[j] = base_address + 0x00010000 * j; + pflinfo->protect[j] = flash[(j << 16) | 0x2]; + } + break; + case FLASH_AT040: + pflinfo->size = 0x00080000; + pflinfo->sector_count = 2; + pflinfo->start[0] = base_address ; + pflinfo->start[1] = base_address + 0x00004000; + pflinfo->protect[0] = ((flash[0x02] & 0X01)==0) ? 0X02 : 0X01; + pflinfo->protect[1] = 0X02; + break; + case FLASH_AM040: + pflinfo->size = 0x00080000; + pflinfo->sector_count = 8; + for(j = 0; j < 8; j++){ + pflinfo->start[j] = base_address + 0x00010000 * j; + pflinfo->protect[j] = flash[(j << 16) | 0x2]; + } + break; + case FLASH_STM800AB: + pflinfo->size = 0x00100000; + pflinfo->sector_count = 19; + pflinfo->start[0] = base_address; + pflinfo->start[1] = base_address + 0x4000; + pflinfo->start[2] = base_address + 0x6000; + pflinfo->start[3] = base_address + 0x8000; + for(j = 1; j < 16; j++){ + pflinfo->start[j+3] = base_address + 0x00010000 * j; + } + break; + } + /* Protect monitor and environment sectors */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + /* reset device to read mode */ + flash[0x0000] = 0xf0; + __asm__ __volatile__("sync"); + } + + return flash_info[0].size + flash_info[1].size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + static const char unk[] = "Unknown"; + const char *mfct = unk, *type = unk; + unsigned int i; + + if(info->flash_id != FLASH_UNKNOWN){ + switch(info->flash_id & FLASH_VENDMASK){ + case FLASH_MAN_ATM: + mfct = "Atmel"; + break; + case FLASH_MAN_AMD: + mfct = "AMD"; + break; + case FLASH_MAN_FUJ: + mfct = "FUJITSU"; + break; + case FLASH_MAN_STM: + mfct = "STM"; + break; + case FLASH_MAN_SST: + mfct = "SST"; + break; + case FLASH_MAN_BM: + mfct = "Bright Microelectonics"; + break; + case FLASH_MAN_INTEL: + mfct = "Intel"; + break; + } + + switch(info->flash_id & FLASH_TYPEMASK){ + case FLASH_AT040: + type = "AT49LV040 (512K * 8, uniform sector size)"; + break; + case FLASH_AM033: + type = "AM29F033C (4 Mbit * 8, uniform sector size)"; + break; + case FLASH_AM040: + type = "AM29F040B (512K * 8, uniform sector size)"; + break; + case FLASH_AM065: + type = "AM29F0465D ( 8 MBit * 8, uniform sector size) or part of AM29F652D( 16 MB)"; + break; + case FLASH_AM400B: + type = "AM29LV400B (4 Mbit, bottom boot sect)"; + break; + case FLASH_AM400T: + type = "AM29LV400T (4 Mbit, top boot sector)"; + break; + case FLASH_AM800B: + type = "AM29LV800B (8 Mbit, bottom boot sect)"; + break; + case FLASH_AM800T: + type = "AM29LV800T (8 Mbit, top boot sector)"; + break; + case FLASH_AM160T: + type = "AM29LV160T (16 Mbit, top boot sector)"; + break; + case FLASH_AM320B: + type = "AM29LV320B (32 Mbit, bottom boot sect)"; + break; + case FLASH_AM320T: + type = "AM29LV320T (32 Mbit, top boot sector)"; + break; + case FLASH_STM800AB: + type = "M29W800AB (8 Mbit, bottom boot sect)"; + break; + case FLASH_SST800A: + type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; + break; + case FLASH_SST160A: + type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; + break; + } + } + + printf( + "\n Brand: %s Type: %s\n" + " Size: %lu KB in %d Sectors\n", + mfct, + type, + info->size >> 10, + info->sector_count + ); + + printf (" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; i++){ + unsigned long size; + unsigned int erased; + unsigned long * flash = (unsigned long *) info->start[i]; + + /* + * Check if whole sector is erased + */ + size = + (i != (info->sector_count - 1)) ? + (info->start[i + 1] - info->start[i]) >> 2 : + (info->start[0] + info->size - info->start[i]) >> 2; + + for( + flash = (unsigned long *) info->start[i], erased = 1; + (flash != (unsigned long *) info->start[i] + size) && erased; + flash++ + ){ + erased = *flash == ~0x0UL; + } + + printf( + "%s %08lX %s %s", + (i % 5) ? "" : "\n ", + info->start[i], + erased ? "E" : " ", + info->protect[i] ? "RO" : " " + ); + } + + puts("\n"); + return; +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + unsigned char sh8b; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){ + sh8b = 3; + } + else{ + sh8b = 0; + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FLASH_WORD_SIZE *)(info->start[0] + ( + (info->start[sect] - info->start[0]) << sh8b)); + if (info->flash_id & FLASH_MAN_SST){ + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + udelay(30000); /* wait 30 ms */ + } + else + addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag){ + enable_interrupts(); + } + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0){ + goto DONE; + } + + start = get_timer (0); + last = start; + addr = (FLASH_WORD_SIZE *)(info->start[0] + ( + (info->start[l_sect] - info->start[0]) << sh8b)); + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0]; + volatile FLASH_WORD_SIZE *dest2; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + unsigned char sh8b; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){ + sh8b = 3; + } + else{ + sh8b = 0; + } + + dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) + + info->start[0]); + + /* Check if Flash is (sufficiently) erased */ + if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++){ + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0; + + dest2[i << sh8b] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag){ + enable_interrupts(); + } + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- */ diff --git a/board/barco/speed.h b/board/barco/speed.h new file mode 100644 index 0000000..46860e8 --- /dev/null +++ b/board/barco/speed.h @@ -0,0 +1,78 @@ +/******************************************************************** + * + * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms + * + * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/speed.h,v $ + * $Revision: 1.2 $ + * $Author: mleeman $ + * $Date: 2005/02/21 12:48:58 $ + * + * Last ChangeLog Entry + * $Log: speed.h,v $ + * Revision 1.2 2005/02/21 12:48:58 mleeman + * update of copyright years (feedback wd) + * + * Revision 1.1 2005/02/14 09:23:46 mleeman + * - moved 'barcohydra' directory to a more generic barco; since we will be + * supporting and adding multiple boards + * + * Revision 1.2 2005/02/09 12:56:23 mleeman + * add generic header to track changes in sources + * + * + *******************************************************************/ + +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*----------------------------------------------------------------------- + * Timer value for timer 2, ICLK = 10 + * + * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) + * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 + * + * SPEED_FCOUNT2 timer 2 counting frequency + * GCLK CPU clock + * SPEED_TMR2_PS prescaler + */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ + +/*----------------------------------------------------------------------- + * Timer value for PIT + * + * PIT_TIME = SPEED_PITC / PITRTCLK + * PITRTCLK = 8192 + */ +#define SPEED_PITC (82 << 16) /* start counting from 82 */ + +/* + * The new value for PTA is calculated from + * + * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) + * + * gclk CPU clock (not bus clock !) + * Trefresh Refresh cycle * 4 (four word bursts used) + * DFBRG For normal mode (no clock reduction) always 0 + * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) + * NCS Number of SDRAM banks (chip selects) on this UPM. + */ diff --git a/board/barco/u-boot.lds b/board/barco/u-boot.lds new file mode 100644 index 0000000..7bf8531 --- /dev/null +++ b/board/barco/u-boot.lds @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/bmw/Makefile b/board/bmw/Makefile new file mode 100644 index 0000000..621640b --- /dev/null +++ b/board/bmw/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2002 +# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o + +SOBJS = early_init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/bmw/README b/board/bmw/README new file mode 100644 index 0000000..70bc813 --- /dev/null +++ b/board/bmw/README @@ -0,0 +1,331 @@ +Broadcom 95xx BMW CPCI Platform + +Overview +========= +BMW is an MPC8245 system controller featuring: +* 3U CPCI Form Factor +* BCM5703 Gigabit Ethernet +* M48T59Y NVRAM +* 16MB DOC +* DIP Socket for Socketed DOC up to 1GB +* 64MB SDRAM +* LCD Display +* Configurable Jumper options for 66,85, and 100Mhz memory bus + + +BMW System Address Map +====================== +BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual +(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found +onboard the processor module are listed briefly below: + +0x00000000 - 0x40000000 - 64MB SDRAM SIMM + (Unregistered PC-100 SDRAM DIMM Module) + +0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000 + TSOP 16MB (MD2211-D16-V3) + +0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000 + DIP32 (Socketed 16MB - 1GB ) * + NOTE: this is not populated on all systems. + +0x7c000000 - 0x7c000000 - Reset Register + (Write 0 to reset) + +0x7c000001 - 0x7c000001 - System LED + (Clear Bit 7 to turn on, set to shut off) + +0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3 + (Clear bit 7 to reset, set to assert IRQ3) + +0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register + (Clear bit 7 to make R/W, set to make R/O) + +0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character + 5x7 Dot Matrix Alphanumeric Display + (Each byte sets the appropriate character) + +0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC + NVRAM Memory Region + +0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC + Realtime Clock Registers + +0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom + (AMD AM29F040, ST 29W040B) + +0xFFF00100 - System Reset Vector + + +IO/MMU (BAT) Configuration +====================== +The following Block-Address-Translation (BAT) configuration +is recommended to access all I/O devices. + +#define CFG_IBAT0L (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + + +Interrupt Mappings +====================== +BMW uses MPC8245 discrete mode interrupts. With the following +hardwired mappings: + +BCM5701 10/100/1000 Ethernet IRQ1 +CompactPCI Interrupt A IRQ2 +RTC/Watchdog Interrupt IRQ3 +Internal NS16552 UART IRQ4 + + +Jumper Settings +====================== + +BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus. +A jumper (X) is a 0 bit. + +Hence 66= 10110 + 85= 11000 + 100= 10000 + +Jumper Settings for various Speeds +======================= +J1 J2 J3 J4 J5 + X X 66Mhz +======================= +J1 J2 J3 J4 J5 + X X X 85Mhz +======================= +J1 J2 J3 J4 J5 + X X X X 100Mhz +======================= + +Obviously, 100Mhz memory bus is recommended for optimum performance. + + +U-Boot +=============== +Broadcom BMW board is supported under config_BWM option. +Supported features: + +- NVRAM setenv/getenv (used by Linux Kernel for configuration variables) +- BCM570x TFTP file transfer support +- LCD Display Support +- DOC Support - (underway) + + +U-Boot 1.2.0 (Aug 6 2002 - 17:44:48) + +CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache +Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B) +Built: Aug 6 2002 at 17:44:37 +Local Bus at 66 MHz +DRAM: 64 MB +FLASH: 4095 MB +In: serial +Out: serial +Err: serial +DOC: No DiskOnChip found +Hit any key to stop autoboot: 0 +=>printenv +bootdelay=5 +baudrate=9600 +clocks_in_mhz=1 +hostname=switch-2 +bootcmd=tftp 100000 vmlinux.img;bootm +gateway=10.16.64.1 +ethaddr=00:00:10:18:10:10 +nfsroot=172.16.40.111:/boot/root-fs +filesize=5ec8c +netmask=255.255.240.0 +ipaddr=172.16.40.114 +serverip=172.16.40.111 +root=/dev/nfs +stdin=serial +stdout=serial +stderr=serial + +Environment size: 315/8172 bytes +=>boot + + +DevTools +======== +ELDK + DENX Embedded Linux Development Kit + +ROM Emulator + Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time) + Grammar Engine PL32E 32Pin PLCC Emulation cables + Grammar Engine 3VA8CON (3Volt adapter with Short cables) + Grammar Engine FPNET PromICE Ethernet Adapters + +ICE + WRS/EST VisionICE-II (PPC8240) + + +=>reset + + +U-Boot 1.2.0 (Aug 6 2002 - 17:44:48) + +CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache +Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B) +Built: Aug 6 2002 at 17:44:37 +Local Bus at 66 MHz +DRAM: 64 MB +FLASH: 4095 MB +In: serial +Out: serial +Err: serial +DOC: No DiskOnChip found +Hit any key to stop autoboot: 0 + +Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000 +BCM570x PCI Memory base address @0x80100000 +eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF +eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010 +eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found +eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON +ARP broadcast 1 +TFTP from server 172.16.40.111; our IP address is 172.16.40.114 +Filename 'vmlinux.img'. +Load address: 0x100000 +Loading: ################################################################# + ####################################T ############################# + ###################### +done +Bytes transferred = 777199 (bdbef hex) + +eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline. +## Booting image at 00100000 ... + Image Name: vmlinux.bin.gz + Created: 2002-08-06 6:30:13 UTC + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 777135 Bytes = 758 kB = 0 MB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK +Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb +Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002 +CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000 +U-Boot Environment: 0xc01b08f0 +IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10> +cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e +NOTICE: mounting root file system via NFS +IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111 +On node 0 totalpages: 16384 +zone(0): 16384 pages. +zone(1): 0 pages. +zone(2): 0 pages. +Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111 +root_dev_setup:/dev/nfs or 00:ff +time_init: decrementer frequency = 16.501145 MHz +Calibrating delay loop... 175.71 BogoMIPS +Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem) +Dentry cache hash table entries: 8192 (order: 4, 65536 bytes) +Inode cache hash table entries: 4096 (order: 3, 32768 bytes) +Mount-cache hash table entries: 1024 (order: 1, 8192 bytes) +Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) +Page-cache hash table entries: 16384 (order: 4, 65536 bytes) +POSIX conformance testing by UNIFIX +PCI: Probing PCI hardware +Linux NET4.0 for Linux 2.4 +Based upon Swansea University Computer Society NET3.039 +Initializing RT netlink socket +Starting kswapd +devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au) +devfs: devfs_debug: 0x0 +devfs: boot_options: 0x1 +Installing knfsd (copyright (C) 1996 okir@monad.swb.de). +pty: 256 Unix98 ptys configured +Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled +Testing ttyS0 (0xf7f51500, 0xf7f51500)... +Testing ttyS1 (0xfc004600, 0xfc004600)... +ttyS00 at 0xf7f51500 (irq = 24) is a ST16650 +ttyS01 at 0xfc004600 (irq = 25) is a 16550A +Real Time Clock Driver v1.10e +RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +loop: loaded (max 8 devices) +TFFS 5.1.1 Flash disk driver for DiskOnChip +Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd. +DOC device(s) found: 1 +fl_init: registered device at major: 100 +fl_geninit: registered device at major: 100 +Partition check: + fla: p1 +partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB +partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB +partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB +partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB +Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02) +eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010 +eth0: Broadcom BCM5701 Integrated Copper transceiver found +eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON +bond0 registered without MII link monitoring, in bonding mode. +rtc: unable to get misc minor +NET4: Linux TCP/IP 1.0 for NET4.0 +IP Protocols: ICMP, UDP, TCP, IGMP +IP: routing cache hash table of 512 buckets, 4Kbytes +TCP: Hash tables configured (established 4096 bind 4096) +bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex +IP-Config: Gateway not on directly connected network. +NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. +802.1Q VLAN Support v1.7 Ben Greear +All bugs added by David S. Miller +Looking up port of RPC 100003/2 on 172.16.40.111 +Looking up port of RPC 100005/1 on 172.16.40.111 +VFS: Mounted root (nfs filesystem). +Mounted devfs on /dev +Freeing unused kernel memory: 100k init +INIT: version 2.78 booting +Mounting local filesystems... +not mounted anything +Setting up symlinks in /dev...done. +Setting up extra devices in /dev...done. +Starting devfsd...Started device management daemon for /dev +INIT: Entering runlevel: 2 +Starting internet superserver: inetd. + + +Welcome to Linux/PPC +MPC8245/BMW + + +switch-2 login: root +Password: +PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0) +Last login: Thu Nov 25 11:51:14 1920 on console + + +Welcome to Linux/PPC +MPC8245/BMW + + +login[49]: ROOT LOGIN on `console' + +root@switch-2:~# cat /proc/cpuinfo +cpu : 82xx +revision : 16.20 (pvr 8081 1014) +bogomips : 175.71 +vendor : Broadcom +machine : BMW/MPC8245 +root@switch-2:~# diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c new file mode 100644 index 0000000..485e050 --- /dev/null +++ b/board/bmw/bmw.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2002 + * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bmw.h" +#include "m48t59y.h" +#include + + +int checkboard(void) +{ + ulong busfreq = get_bus_freq(0); + char buf[32]; + + puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n"); + printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + /* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */ + printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); + return 0; +} + +long int initdram(int board_type) +{ + return 64*1024*1024; +} + + +void +get_tod(void) +{ + int year, month, day, hour, minute, second; + + m48_tod_get(&year, + &month, + &day, + &hour, + &minute, + &second); + + printf(" Current date/time: %d/%d/%d %d:%d:%d \n", + month, day, year, hour, minute, second); + +} + +/* + * EPIC, PCI, and I/O devices. + * Initialize Mousse Platform, probe for PCI devices, + * Query configuration parameters if not set. + */ +int misc_init_f (void) +{ +#if 0 + m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */ + printf("RTC: M48T589 TOD/NVRAM (%d) bytes\n", + TOD_NVRAM_SIZE); + get_tod(); +#endif + + sys_led_msg("BOOT"); + return 0; +} + + +/* + * Initialize PCI Devices, report devices found. + */ +struct pci_controller hose; + +void pci_init_board (void) +{ + pci_mpc824x_init(&hose); + /* pci_dev_init(0); */ +} + +/* + * Write characters to LCD display. + * Note that the bytes for the first character is the last address. + */ +void +sys_led_msg(char* msg) +{ + LED_REG(0) = msg[3]; + LED_REG(1) = msg[2]; + LED_REG(2) = msg[1]; + LED_REG(3) = msg[0]; +} + +/* + * Map onboard TSOP-16MB DOC FLASH chip. + */ +void doc_init (void) +{ + doc_probe(DOC_BASE_ADDR); +} + +#define NV_ADDR ((volatile unsigned char *) CFG_ENV_ADDR) + +/* Read from NVRAM */ +void* +nvram_read(void *dest, const long src, size_t count) +{ + int i; + volatile unsigned char* d = (unsigned char*)dest; + volatile unsigned char* s = (unsigned char*)src; + + for( i = 0; i < count;i++) + d[i] = s[i]; + + return dest; +} + +/* Write to NVRAM */ +void +nvram_write(long dest, const void *src, size_t count) +{ + int i; + volatile unsigned char* d = (unsigned char*)dest; + volatile unsigned char* s = (unsigned char*)src; + + SYS_TOD_UNPROTECT(); + + for( i = 0; i < count;i++) + d[i] = s[i]; + + SYS_TOD_PROTECT(); +} diff --git a/board/bmw/bmw.h b/board/bmw/bmw.h new file mode 100644 index 0000000..dd97569 --- /dev/null +++ b/board/bmw/bmw.h @@ -0,0 +1,86 @@ +/* + * BMW/MPC8245 Board definitions. + * For more info, see http://www.vooha.com/ + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * James Dougherty (jfd@broadcom.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BMW_H +#define __BMW_H + +/* System addresses */ + +#define PCI_SPECIAL_BASE 0xfe000000 +#define PCI_SPECIAL_SIZE 0x01000000 + +#define EUMBBAR_VAL 0x80500000 /* Location of EUMB region */ +#define EUMBSIZE 0x00100000 /* Size of EUMB region */ + +/* Extended ROM space devices */ +#define DOC_BASE_ADDR 0xff000000 /* Onboard DOC TSOP 16MB */ +#define DOC2_BASE_ADDR 0x70000000 /* DIP32 socket -> 1GB */ +#define XROM_BASE_ADDR 0x7c000000 /* RCS2 (PAL / Satellite IO) */ +#define PLD_REG_BASE XROM_BASE_ADDR +#define LED_REG_BASE (XROM_BASE_ADDR | 0x2000) +#define TOD_BASE (XROM_BASE_ADDR | 0x4000) +#define LED_REG(x) (*(volatile unsigned char *) \ + (LED_REG_BASE + (x))) +#define XROM_DEV_SIZE 0x00006000 + +#define ENET_DEV_BASE 0x80000000 + +#define PLD_REG(off) (*(volatile unsigned char *)\ + (PLD_REG_BASE + (off))) + +#define PLD_REVID_B1 0x7f /* Fix me */ +#define PLD_REVID_B2 0x01 /* Fix me */ + +#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */ +#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f) +#define SYS_LED_OFF() (PLD_REG(1) |= 0x80) +#define SYS_LED_ON() (PLD_REG(1) &= ~0x80) +#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80) +#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80) +#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80) +#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80) + +#define TOD_REG_BASE (TOD_BASE | 0x1ff0) +#define TOD_NVRAM_BASE TOD_BASE +#define TOD_NVRAM_SIZE 0x1ff0 +#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE) +#define RTC(r) (TOD_BASE + r) + +/* Onboard BCM570x device */ +#define PCI_ENET_IOADDR 0x80000000 +#define PCI_ENET_MEMADDR 0x80000000 + + +#ifndef __ASSEMBLY__ +/* C Function prototypes */ +void sys_led_msg(char* msg); + +#endif /* !__ASSEMBLY__ */ + +#endif /* __BMW_H */ diff --git a/board/bmw/config.mk b/board/bmw/config.mk new file mode 100644 index 0000000..f991549 --- /dev/null +++ b/board/bmw/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# CU824 board +# + +TEXT_BASE = 0xFFF00000 +# NOTE: The flags below affect how the BCM570x driver is compiled +PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\ + -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256\ + -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S new file mode 100644 index 0000000..e6400c3 --- /dev/null +++ b/board/bmw/early_init.S @@ -0,0 +1,1170 @@ +#include +#include +#include +#include +#include + +#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */ + + +/* + * Initialize the MMU using BAT entries and hardwired TLB + * This obviates the need for any code in cpu_init_f which + * configures the BAT registers. +*/ +#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */ + .global iommu_setup + /* Initialize IO/MMU mappings via BAT method Ch. 7, + * PPC Programming Reference + */ +iommu_setup: + +/* initialize the BAT registers (SPRs 528 - 543 */ +#define mtibat0u(x) mtspr 528,(x) /* SPR 528 (IBAT0U) */ +#define mtibat0l(x) mtspr 529,(x) /* SPR 529 (IBAT0L) */ +#define mtibat1u(x) mtspr 530,(x) /* SPR 530 (IBAT1U) */ +#define mtibat1l(x) mtspr 531,(x) /* SPR 531 (IBAT1L) */ +#define mtibat2u(x) mtspr 532,(x) /* SPR 532 (IBAT2U) */ +#define mtibat2l(x) mtspr 533,(x) /* SPR 533 (IBAT2L) */ +#define mtibat3u(x) mtspr 534,(x) /* SPR 534 (IBAT3U) */ +#define mtibat3l(x) mtspr 535,(x) /* SPR 535 (IBAT3L) */ +#define mtdbat0u(x) mtspr 536,(x) /* SPR 536 (DBAT0U) */ +#define mtdbat0l(x) mtspr 537,(x) /* SPR 537 (DBAT0L) */ +#define mtdbat1u(x) mtspr 538,(x) /* SPR 538 (DBAT1U) */ +#define mtdbat1l(x) mtspr 539,(x) /* SPR 539 (DBAT1L) */ +#define mtdbat2u(x) mtspr 540,(x) /* SPR 540 (DBAT2U) */ +#define mtdbat2l(x) mtspr 541,(x) /* SPR 541 (DBAT2L) */ +#define mtdbat3u(x) mtspr 542,(x) /* SPR 542 (DBAT3U) */ +#define mtdbat3l(x) mtspr 543,(x) /* SPR 543 (DBAT3L) */ + + +/* PowerPC processors do not necessarily initialize the BAT + registers on power-up or reset. So they are in an unknown + state. Before programming the BATs for the first time, all + BAT registers MUST have their Vs and Vp bits cleared in the + upper BAT half in order to avoid possibly having 2 BATs + valid and mapping the same memory region. + + The reason for this is that, even with address translation + disabled, multiple BAT hits for an address are treated as + programming errors and can cause unpredictable results. + + It is up to the software to make sure it never has 2 IBAT + mappings or 2 DBAT mappings that are valid for the same + addresses. It is not necessary to perform this code + sequence every time the BATs are programmed, only when + there is a possibility that there may be overlapping BAT + entries. + + When programming the BATs in non-reset scenarios, even if + you are sure that your new mapping will not temporarily + create overlapping regions, it is still a wise idea to + invalidate a BAT entry by setting its upper BAT register to + all 0's before programming it. This will avoid having a + BAT marked valid that is in an unknown or transient state +*/ + + addis r5,0,0x0000 + mtibat0u(r5) + mtibat0l(r5) + mtibat1u(r5) + mtibat1l(r5) + mtibat2u(r5) + mtibat2l(r5) + mtibat3u(r5) + mtibat3l(r5) + mtdbat0u(r5) + mtdbat0l(r5) + mtdbat1u(r5) + mtdbat1l(r5) + mtdbat2u(r5) + mtdbat2l(r5) + mtdbat3u(r5) + mtdbat3l(r5) + isync + +/* + * Set up I/D BAT0 + */ + lis r4, CFG_DBAT0L@h + ori r4, r4, CFG_DBAT0L@l + lis r3, CFG_DBAT0U@h + ori r3, r3, CFG_DBAT0U@l + + mtdbat0l(r4) + isync + mtdbat0u(r3) + isync + sync + + lis r4, CFG_IBAT0L@h + ori r4, r4, CFG_IBAT0L@l + lis r3, CFG_IBAT0U@h + ori r3, r3, CFG_IBAT0U@l + + isync + mtibat0l(r4) + isync + mtibat0u(r3) + isync + +/* + * Set up I/D BAT1 + */ + lis r4, CFG_IBAT1L@h + ori r4, r4, CFG_IBAT1L@l + lis r3, CFG_IBAT1U@h + ori r3, r3, CFG_IBAT1U@l + + isync + mtibat1l(r4) + isync + mtibat1u(r3) + isync + mtdbat1l(r4) + isync + mtdbat1u(r3) + isync + sync + +/* + * Set up I/D BAT2 + */ + lis r4, CFG_IBAT2L@h + ori r4, r4, CFG_IBAT2L@l + lis r3, CFG_IBAT2U@h + ori r3, r3, CFG_IBAT2U@l + + isync + mtibat2l(r4) + isync + mtibat2u(r3) + isync + mtdbat2l(r4) + isync + mtdbat2u(r3) + isync + sync + +/* + * Setup I/D BAT3 + */ + lis r4, CFG_IBAT3L@h + ori r4, r4, CFG_IBAT3L@l + lis r3, CFG_IBAT3U@h + ori r3, r3, CFG_IBAT3U@l + + isync + mtibat3l(r4) + isync + mtibat3u(r3) + isync + mtdbat3l(r4) + isync + mtdbat3u(r3) + isync + sync + + +/* + * Invalidate all 64 TLB's + */ + lis r3, 0 + mtctr r3 + lis r5, 4 + +tlblp: + tlbie r3 + sync + addi r3, r3, 0x1000 + cmplw r3, r5 + blt tlblp + + sync + +/* + * Enable Data Translation + */ + lis r4, MEMORY_MGMT_MSR_BITS@h + ori r4, r4, MEMORY_MGMT_MSR_BITS@l + mfmsr r3 + or r3, r4, r3 + mtmsr r3 + isync + sync + + blr + + +#ifdef USE_V2_INIT +/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */ +/* Macro for hiadjust and lo */ +#define HIADJ(arg) arg@ha +#define HI(arg) arg@h +#define LO(arg) arg@l + +#undef LOADPTR +#define LOADPTR(reg,const32) \ + addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32) + +.globl early_init_f + +early_init_f: +/* MPC8245/BMW CPCI System Init + * Jimmy Blair, Broadcom Corp, 2002. + */ + mflr r11 + /* Zero-out registers */ + + addis r0,r0,0 + mtspr SPRG0,r0 + mtspr SPRG1,r0 + mtspr SPRG2,r0 + mtspr SPRG3,r0 + + /* Set MPU/MSR to a known state. Turn on FP */ + + LOADPTR (r3, MSR_FP) + sync + mtmsr r3 + isync + + /* Init the floating point control/status register */ + + mtfsfi 7,0x0 + mtfsfi 6,0x0 + mtfsfi 5,0x0 + mtfsfi 4,0x0 + mtfsfi 3,0x0 + mtfsfi 2,0x0 + mtfsfi 1,0x0 + mtfsfi 0,0x0 + isync + + /* Set MPU/MSR to a known state. Turn off FP */ + +#if 1 /* Turn off floating point (remove to keep FP on) */ + andi. r3, r3, 0 + sync + mtmsr r3 + isync +#endif + + /* Init the Segment registers */ + + andi. r3, r3, 0 + isync + mtsr 0,r3 + isync + mtsr 1,r3 + isync + mtsr 2,r3 + isync + mtsr 3,r3 + isync + mtsr 4,r3 + isync + mtsr 5,r3 + isync + mtsr 6,r3 + isync + mtsr 7,r3 + isync + mtsr 8,r3 + isync + mtsr 9,r3 + isync + mtsr 10,r3 + isync + mtsr 11,r3 + isync + mtsr 12,r3 + isync + mtsr 13,r3 + isync + mtsr 14,r3 + isync + mtsr 15,r3 + isync + + /* Turn off data and instruction cache control bits */ + + mfspr r3, HID0 + isync + rlwinm r4, r3, 0, 18, 15 /* r4 has ICE and DCE bits cleared */ + sync + isync + mtspr HID0, r4 /* HID0 = r4 */ + isync + + /* Get cpu type */ + + mfspr r28, PVR + rlwinm r28, r28, 16, 16, 31 + + /* invalidate the MPU's data/instruction caches */ + + lis r3, 0x0 + cmpli 0, 0, r28, CPU_TYPE_603 + beq cpuIs603 + cmpli 0, 0, r28, CPU_TYPE_603E + beq cpuIs603 + cmpli 0, 0, r28, CPU_TYPE_603P + beq cpuIs603 + cmpli 0, 0, r28, CPU_TYPE_604R + bne cpuNot604R + +cpuIs604R: + lis r3, 0x0 + mtspr HID0, r3 /* disable the caches */ + isync + ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */ + +cpuNot604R: + ori r3, r3, (HID0_ICFI |HID0_DCI) + +cpuIs603: + ori r3, r3, (HID0_ICE | HID0_DCE) + or r4, r4, r3 /* set bits */ + sync + isync + mtspr HID0, r4 /* HID0 = r4 */ + andc r4, r4, r3 /* clear bits */ + isync + cmpli 0, 0, r28, CPU_TYPE_604 + beq cpuIs604 + cmpli 0, 0, r28, CPU_TYPE_604E + beq cpuIs604 + cmpli 0, 0, r28, CPU_TYPE_604R + beq cpuIs604 + mtspr HID0, r4 + isync + +#ifdef USER_I_CACHE_ENABLE + b instCacheOn603 +#else + b cacheEnableDone +#endif + +cpuIs604: + LOADPTR (r5, 0x1000) /* loop count, 0x1000 */ + mtspr CTR, r5 +loopDelay: + nop + bdnz loopDelay + isync + mtspr HID0, r4 + isync + + /* turn the Instruction cache ON for faster FLASH ROM boots */ + +#ifdef USER_I_CACHE_ENABLE + + ori r4, r4, (HID0_ICE | HID0_ICFI) + isync /* Synchronize for ICE enable */ + b writeReg4 +instCacheOn603: + ori r4, r4, (HID0_ICE | HID0_ICFI) + rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */ + + /* + * The setting of the instruction cache enable (ICE) bit must be + * preceded by an isync instruction to prevent the cache from being + * enabled or disabled while an instruction access is in progress. + */ + isync +writeReg4: + mtspr HID0, r4 /* Enable Instr Cache & Inval cache */ + cmpli 0, 0, r28, CPU_TYPE_604 + beq cacheEnableDone + cmpli 0, 0, r28, CPU_TYPE_604E + beq cacheEnableDone + + mtspr HID0, r3 /* using 2 consec instructions */ + /* PPC603 recommendation */ +#endif +cacheEnableDone: + + /* Detect map A or B */ + + addis r5,r0, HI(CHRP_REG_ADDR) + addis r6,r0, HI(CHRP_REG_DATA) + LOADPTR (r7, KAHLUA_ID) /* Kahlua PCI controller ID */ + LOADPTR (r8, BMC_BASE) + + stwbrx r8,0,(r5) + lwbrx r3,0,(r6) /* Store read value to r3 */ + cmp 0,0,r3,r7 + beq cr0, X4_KAHLUA_START + + /* It's not an 8240, is it an 8245? */ + + LOADPTR (r7, KAHLUA2_ID) /* Kahlua PCI controller ID */ + cmp 0,0,r3,r7 + beq cr0, X4_KAHLUA_START + + /* Save the PCI controller type in r7 */ + mr r7, r3 + + LOADPTR (r5, PREP_REG_ADDR) + LOADPTR (r6, PREP_REG_DATA) + +X4_KAHLUA_START: + /* MPC8245 changes begin here */ + LOADPTR (r3, MPC107_PCI_CMD) /* PCI command reg */ + stwbrx r3,0,r5 + li r4, 6 /* Command register value */ + sthbrx r4, 0, r6 + + LOADPTR (r3, MPC107_PCI_STAT) /* PCI status reg */ + stwbrx r3,0,r5 + li r4, -1 /* Write-to-clear all bits */ + li r3, 2 /* PCI_STATUS is at +2 offset */ + sthbrx r4, r3, r6 + + /*-------PROC_INT1_ADR */ + + LOADPTR (r3, PROC_INT1_ADR) /* Processor I/F Config 1 reg. */ + stwbrx r3,0,r5 + LOADPTR (r4, 0xff141b98) + stwbrx r4,0,r6 + + /*-------PROC_INT2_ADR */ + + LOADPTR (r3, PROC_INT2_ADR) /* Processor I/F Config 2 reg. */ + stwbrx r3,0,r5 + lis r4, 0x2000 /* Flush PCI config writes */ + stwbrx r4,0,r6 + + LOADPTR (r9, KAHLUA2_ID) + cmpl 0, 0, r7, r9 + bne L1not8245 + + /* MIOCR1 -- turn on bit for DLL delay */ + + LOADPTR (r3, MIOCR1_ADR_X) + stwbrx r3,0,r5 + li r4, 0x04 + stb r4, MIOCR1_SHIFT(r6) + + /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ + /* SDRAM_CLK_DEL (0x77)*/ + + LOADPTR (r3, MIOCR2_ADR_X) + stwbrx r3,0,r5 + li r4, 0x10 + stb r4, MIOCR2_SHIFT(r6) + + /* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */ + + LOADPTR (r3, PMCR2_ADR_X) + stwbrx r3,0,r5 + li r4, 0x20 + stb r4, PMCR2_SHIFT(r6) + + /* Initialize EUMBBAR early since 8245 has internal UART in EUMB */ + + LOADPTR (r3, EUMBBAR) + stwbrx r3,0,r5 + LOADPTR (r4, CFG_EUMB_ADDR) + stwbrx r4,0,r6 + +L1not8245: + + /* Toggle the DLL reset bit in AMBOR */ + + LOADPTR (r3, AMBOR) + stwbrx r3,0,r5 + lbz r4, 0(r6) + + andi. r4, r4, 0xdf + stb r4, 0(r6) /* Clear DLL_RESET */ + sync + + ori r4, r4, 0x20 /* Set DLL_RESET */ + stb r4, 0(r6) + sync + + andi. r4, r4, 0xdf + stb r4, 0(r6) /* Clear DLL_RESET */ + + + /* Enable RCS2, use supplied timings */ + LOADPTR (r3, ERCR1) + stwbrx r3,0,r5 + LOADPTR (r4, 0x80408000) + stwbrx r4,0,r6 + + /* Disable RCS3 parameters */ + LOADPTR (r3, ERCR2) + stwbrx r3,0,r5 + LOADPTR (r4, 0x00000000) + stwbrx r4,0,r6 + + /* RCS3 at 0x70000000, 64KBytes */ + LOADPTR (r3, ERCR2) + stwbrx r3,0,r5 + LOADPTR (r4, 0x00000004) + stwbrx r4,0,r6 + + /*-------MCCR1 */ + +#ifdef INCLUDE_ECC +#define MC_ECC 1 +#else /* INCLUDE_ECC */ +#define MC_ECC 0 +#endif /* INCLUDE_ECC */ + +#define MC1_ROMNAL 8 /* 0-15 */ +#define MC1_ROMFAL 11 /* 0-31 */ +#define MC1_DBUS_SIZE 0 /* 0-3, read only */ +#define MC1_BURST 0 /* 0-1 */ +#define MC1_MEMGO 0 /* 0-1 */ +#define MC1_SREN 1 /* 0-1 */ +#define MC1_RAM_TYPE 0 /* 0-1 */ +#define MC1_PCKEN MC_ECC /* 0-1 */ +#define MC1_BANKBITS 0x5555 /* 2 bits/bank 7-0 */ + + LOADPTR (r3, MEM_CONT1_ADR) /* Set MCCR1 (F0) */ + stwbrx r3,0,r5 + LOADPTR(r4, \ + MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \ + MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \ + MC1_MEMGO << 19 | MC1_SREN << 18 | \ + MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 ) + li r3, MC1_BANKBITS + cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ + bne BankBitsAdd + cmpli 0, 0, r3, 0x5555 + beq K2BankBitsHack /* On 8245, 5555 ==> 0 */ +BankBitsAdd: + ori r4, r3, 0 +K2BankBitsHack: + stwbrx r4, 0, r6 + + /*------- MCCR2 */ + +#define MC2_TS_WAIT_TIMER 0 /* 0-7 */ +#define MC2_ASRISE 8 /* 0-15 */ +#define MC2_ASFALL 4 /* 0-15 */ +#define MC2_INLINE_PAR_NOT_ECC 0 /* 0-1 */ +#define MC2_WRITE_PARITY_CHK_EN MC_ECC /* 0-1 */ +#define MC2_INLRD_PARECC_CHK_EN MC_ECC /* 0-1 */ +#define MC2_ECC_EN 0 /* 0-1 */ +#define MC2_EDO 0 /* 0-1 */ +/* +* N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM. +* May need to be decreased for 100 MHz +*/ +#define MC2_REFINT 0x3a5 /* 0-0x3fff */ +#define MC2_RSV_PG 0 /* 0-1 */ +#define MC2_RMW_PAR MC_ECC /* 0-1 */ + + LOADPTR (r3, MEM_CONT2_ADR) /* Set MCCR2 (F4) */ + stwbrx r3,0,r5 + LOADPTR(r4, \ + MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \ + MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \ + MC2_WRITE_PARITY_CHK_EN << 19 | \ + MC2_INLRD_PARECC_CHK_EN << 18 | \ + MC2_ECC_EN << 17 | MC2_EDO << 16 | \ + MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR) + cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ + bne notK2 + /* clear Kahlua2 reserved bits */ + LOADPTR (r3, 0xfffcffff) + and r4, r4, r3 +notK2: + stwbrx r4,0,r6 + + /*------- MCCR3 */ + +#define MC_BSTOPRE 0x079 /* 0-0x7ff */ + +#define MC3_BSTOPRE_U (MC_BSTOPRE >> 4 & 0xf) +#define MC3_REFREC 8 /* 0-15 */ +#define MC3_RDLAT (4+MC_ECC) /* 0-15 */ +#define MC3_CPX 0 /* 0-1 */ +#define MC3_RAS6P 0 /* 0-15 */ +#define MC3_CAS5 0 /* 0-7 */ +#define MC3_CP4 0 /* 0-7 */ +#define MC3_CAS3 0 /* 0-7 */ +#define MC3_RCD2 0 /* 0-7 */ +#define MC3_RP1 0 /* 0-7 */ + + LOADPTR (r3, MEM_CONT3_ADR) /* Set MCCR3 (F8) */ + stwbrx r3,0,r5 + LOADPTR(r4, \ + MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \ + MC3_RDLAT << 20 | MC3_CPX << 19 | \ + MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \ + MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1) + cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ + bne notK2b + /* clear Kahlua2 reserved bits */ + LOADPTR (r3, 0xff000000) + and r4, r4, r3 +notK2b: + stwbrx r4,0,r6 + + /*------- MCCR4 */ + +#define MC4_PRETOACT 3 /* 0-15 */ +#define MC4_ACTOPRE 5 /* 0-15 */ +#define MC4_WMODE 0 /* 0-1 */ +#define MC4_INLINE MC_ECC /* 0-1 */ +#define MC4_REGISTERED (1-MC_ECC) /* 0-1 */ +#define MC4_BSTOPRE_UU (MC_BSTOPRE >> 8 & 3) +#define MC4_REGDIMM 0 /* 0-1 */ +#define MC4_SDMODE_CAS 2 /* 0-7 */ +#define MC4_DBUS_RCS1 1 /* 0-1, 8-bit */ +#define MC4_SDMODE_WRAP 0 /* 0-1 */ +#define MC4_SDMODE_BURST 2 /* 0-7 */ +#define MC4_ACTORW 3 /* 0-15 */ +#define MC4_BSTOPRE_L (MC_BSTOPRE & 0xf) + + LOADPTR (r3, MEM_CONT4_ADR) /* Set MCCR4 (FC) */ + stwbrx r3,0,r5 + LOADPTR(r4, \ + MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \ + MC4_WMODE << 23 | MC4_INLINE << 22 | \ + MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \ + MC4_DBUS_RCS1 << 17 | \ + MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \ + MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \ + MC4_ACTORW << 4 | MC4_BSTOPRE_L) + cmpl 0, 0, r7, r9 /* Check for Kahlua 2 */ + bne notK2c + /* Turn on Kahlua2 extended ROM space */ + LOADPTR (r3, 0x00200000) + or r4, r4, r3 +notK2c: + stwbrx r4,0,r6 + +#ifdef INCLUDE_ECC + /*------- MEM_ERREN1 */ + + LOADPTR (r3, MEM_ERREN1_ADR) /* Set MEM_ERREN1 (c0) */ + stwbrx r3,0,r5 + lwbrx r4,0,r6 + ori r4,r4,4 /* Set MEM_PERR_EN */ + stwbrx r4,0,r6 +#endif /* INCLUDE_ECC */ + + /*------- MSAR/MEAR */ + + LOADPTR (r3, MEM_START1_ADR) /* Set MSAR1 (80) */ + stwbrx r3,0,r5 + LOADPTR (r4, 0xc0804000) + stwbrx r4,0,r6 + + LOADPTR (r3, MEM_START2_ADR) /* Set MSAR2 (84) */ + stwbrx r3,0,r5 + LOADPTR (r4, 0xc0804000) + stwbrx r4,0,r6 + + LOADPTR (r3, XMEM_START1_ADR) /* Set MESAR1 (88) */ + stwbrx r3,0,r5 + LOADPTR (r4, 0x00000000) + stwbrx r4,0,r6 + + LOADPTR (r3, XMEM_START2_ADR) /* Set MESAR2 (8c) */ + stwbrx r3,0,r5 + LOADPTR (r4, 0x01010101) + stwbrx r4,0,r6 + + LOADPTR (r3, MEM_END1_ADR) /* Set MEAR1 (90) */ + stwbrx r3,0,r5 + LOADPTR (r4, 0xffbf7f3f) + stwbrx r4,0,r6 + + LOADPTR (r3, MEM_END2_ADR) /* Set MEAR2 (94) */ + stwbrx r3,0,r5 + LOADPTR (r4, 0xffbf7f3f) + stwbrx r4,0,r6 + + LOADPTR (r3, XMEM_END1_ADR) /* MEEAR1 (98) */ + stwbrx r3,0,r5 + LOADPTR (r4, 0x00000000) + stwbrx r4,0,r6 + + LOADPTR (r3, XMEM_END2_ADR) /* MEEAR2 (9c) */ + stwbrx r3,0,r5 + LOADPTR (r4, 0x01010101) + stwbrx r4,0,r6 + + /*-------ODCR */ + + LOADPTR (r3, ODCR_ADR_X) /* Set ODCR */ + stwbrx r3,0,r5 + + li r4, 0x7f + stb r4, ODCR_SHIFT(r6) /* ODCR is at +3 offset */ + + /*-------MBEN */ + + LOADPTR (r3, MEM_EN_ADR) /* Set MBEN (a0) */ + stwbrx r3,0,r5 + li r4, 0x01 /* Enable bank 0 */ + stb r4, 0(r6) /* MBEN is at +0 offset */ + +#if 0 /* Jimmy: I think page made is broken */ + /*-------PGMAX */ + + LOADPTR (r3, MPM_ADR_X) + stwbrx r3,0,r5 + li r4, 0x32 + stb r4, MPM_SHIFT(r6) /* PAGE_MODE is at +3 offset */ +#endif + + /* Wait before initializing other registers */ + + lis r4,0x0001 + mtctr r4 + +KahluaX4wait200us: + bdnz KahluaX4wait200us + + /* Set MEMGO bit */ + + LOADPTR (r3, MEM_CONT1_ADR) /* MCCR1 (F0) |= PGMAX */ + stwbrx r3,0,r5 + lwbrx r4,0,r6 /* old MCCR1 */ + oris r4,r4,0x0008 /* MEMGO=1 */ + stwbrx r4, 0, r6 + + /* Wait again */ + + addis r4,r0,0x0002 + ori r4,r4,0xffff + + mtctr r4 + +KahluaX4wait8ref: + bdnz KahluaX4wait8ref + + sync + eieio + mtlr r11 + blr + +#else /* USE_V2_INIT */ + + +/* U-Boot works, but memory will not run reliably for all address ranges. + * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not + * initialized correctly. Could work if debugged. + */ +/* PCI Support routines */ + + .globl __pci_config_read_32 +__pci_config_read_32: + lis r4, 0xfec0 + stwbrx r3, r0, r4 + sync + lis r4, 0xfee0 + lwbrx r3, 0, r4 + blr + .globl __pci_config_read_16 +__pci_config_read_16: + lis r4, 0xfec0 + andi. r5, r3, 2 + stwbrx r3, r0, r4 + sync + oris r4, r5, 0xfee0 + lhbrx r3, r0, r4 + blr + .globl __pci_config_read_8 +__pci_config_read_8: + lis r4, 0xfec0 + andi. r5, r3, 3 + stwbrx r3, r0, r4 + sync + oris r4, r5, 0xfee0 + lbz r3, 0(4) + blr + .globl __pci_config_write_32 +__pci_config_write_32: + lis r5, 0xfec0 + stwbrx r3, r0, r5 + sync + lis r5, 0xfee0 + stwbrx r4, r0, r5 + sync + blr + .globl __pci_config_write_16 +__pci_config_write_16: + lis r5, 0xfec0 + andi. r6, r3, 2 + stwbrx r3, r0, 5 + sync + oris r5, r6, 0xfee0 + sthbrx r4, r0, r5 + sync + blr + .globl __pci_config_write_8 +__pci_config_write_8: + lis r5, 0xfec0 + andi. r6, r3, 3 + stwbrx r3, r0, r5 + sync + oris r5, r6, 0xfee0 + stb r4, 0(r5) + sync + blr + .globl in_8 +in_8: + oris r3, r3, 0xfe00 + lbz r3,0(r3) + blr + .globl in_16 +in_16: + oris r3, r3, 0xfe00 + lhbrx r3, 0, r3 + blr + .globl in_16_ne +in_16_ne: + oris r3, r3, 0xfe00 + lhzx r3, 0, r3 + blr + .globl in_32 +in_32: + oris r3, r3, 0xfe00 + lwbrx r3, 0, r3 + blr + .globl out_8 +out_8: + oris r3, r3, 0xfe00 + stb r4, 0(r3) + eieio + blr + .globl out_16 +out_16: + oris r3, r3, 0xfe00 + sthbrx r4, 0, r3 + eieio + blr + .globl out_16_ne +out_16_ne: + oris r3, r3, 0xfe00 + sth r4, 0(r3) + eieio + blr + .globl out_32 +out_32: + oris r3, r3, 0xfe00 + stwbrx r4, 0, r3 + eieio + blr + .globl read_8 +read_8: + lbz r3,0(r3) + blr + .globl read_16 +read_16: + lhbrx r3, 0, r3 + blr + .globl read_32 +read_32: + lwbrx r3, 0, r3 + blr + .globl read_32_ne +read_32_ne: + lwz r3, 0(r3) + blr + .globl write_8 +write_8: + stb r4, 0(r3) + eieio + blr + .globl write_16 +write_16: + sthbrx r4, 0, r3 + eieio + blr + .globl write_32 +write_32: + stwbrx r4, 0, r3 + eieio + blr + .globl write_32_ne +write_32_ne: + stw r4, 0(r3) + eieio + blr + + +.globl early_init_f + +early_init_f: + mflr r11 + lis r10, 0x8000 + + /* PCI Latency Timer */ + li r4, 0x0d + ori r3, r10, PLTR@l + bl __pci_config_write_8 + + /* Cache Line Size */ + li r4, 0x08 + ori r3, r10, PCLSR@l + bl __pci_config_write_8 + + /* PCI Cmd */ + li r4, 6 + ori r3, r10, PCICR@l + bl __pci_config_write_16 + +#if 1 + /* PCI Stat */ + ori r3, r10, PCISR@l + bl __pci_config_read_16 + ori r4, r4, 0xffff + ori r3, r10, PCISR@l + bl __pci_config_write_16 +#endif + + /* PICR1 */ + lis r4, 0xff14 + ori r4, r4, 0x1b98 + ori r3, r10, PICR1@l + bl __pci_config_write_32 + + + /* PICR2 */ + lis r4, 0x0404 + ori r4, r4, 0x0004 + ori r3, r10, PICR2@l + bl __pci_config_write_32 + + /* MIOCR1 */ + li r4, 0x04 + ori r3, r10, MIOCR1@l + bl __pci_config_write_8 + + /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ + /* SDRAM_CLK_DEL (0x77)*/ + li r4, 0x10 + ori r3, r10, MIOCR2@l + bl __pci_config_write_8 + + /* EUMBBAR */ + lis r4, 0xfc00 + ori r3, r10, EUMBBAR@l + bl __pci_config_write_32 + + /* AMBOR */ + + /* Even if Address Map B is not being used (though it should), + * the memory DLL needs to be cleared/set/cleared before using memory. + */ + + ori r3, r10, AMBOR@l + bl __pci_config_read_8 /* get Current bits */ + + andi. r4, r4, 0xffdf + ori r3, r10, AMBOR@l + bl __pci_config_write_16 /* Clear DLL_RESET */ + + ori r4, r4, 0x0020 + ori r3, r10, AMBOR@l + bl __pci_config_write_16 /* Set DLL_RESET */ + + andi. r4, r4, 0xffdf + ori r3, r10, AMBOR@l + bl __pci_config_write_16 /* Clear DLL_RESET */ + + /* ERCR1 */ + lis r4, 0x8040 /* Enable RCS2, use supplied timings */ + ori r4, r4, 0x8000 + ori r3, r10, ERCR1@l + bl __pci_config_write_32 + + /* ERCR2 */ + lis r4, 0x0000 /* Disable RCS3 parms */ + ori r4, r4, 0x0000 + ori r3, r10, ERCR2@l + bl __pci_config_write_32 + + /* ERCR3 */ + lis r4, 0x0000 /* RCS3 at 0x70000000, 64K bytes */ + ori r4, r4, 0x0004 + ori r3, r10, ERCR2@l + bl __pci_config_write_32 + + /* Preserve memgo bit */ + /* MCCR1 */ + +/* lis r4, 0x75a8 / Safe Local ROM = 11+3 clocks */ + lis r4, 0x75a0 /* Safe Local ROM = 11+3 clocks */ +/* lis r4, 0x73a0 / Fast Local ROM = 7+3 clocks */ +/* oris r4, r4, 0x0010 / Burst ROM/Flash enable */ +/* oris r4, r4, 0x0004 / Self-refresh enable */ + +/* ori r4,r4,0xFFFF / 16Mbit 2bank SDRAM */ +/* ori r4,r4,0xAAAA / 256Mbit 4bank SDRAM (8245 only) */ +/* ori r4,r4,0x5555 / 64Mbit 2bank SDRAM */ + ori r4,r4,0x0000 /* 64Mbit 4bank SDRAM */ + + ori r3, r10, MCCR1@l + bl __pci_config_write_32 + + /* MCCR2 */ + + lis r4,0x0000 +/* oris r4,r4,0x4000 / TS_WAIT_TIMER = 3 clocks */ + oris r4,r4,0x1000 /* ASRISE = 8 clocks */ + oris r4,r4,0x0080 /* ASFALL = 8 clocks */ +/* oris r4,r4,0x0010 / SDRAM Parity (else ECC) */ +/* oris r4,r4,0x0008 / Write parity check */ +/* oris r4,r4,0x0004 / SDRAM inline reads */ + + +/* Select a refresh rate; it needs to match the bus speed; if too */ +/* slow, data may be lost; if too fast, performance is lost. We */ +/* use the fastest value so we run at all speeds. */ +/* Refresh = (15600ns/busclk) - (213 (see UM)). */ + +/* ori r4,r4,0x1d2c / 133 MHz mem bus = 1867 */ +/* ori r4,r4,0x150c / 100 MHz mem bus = 1347 */ +/* ori r4,r4,0x10fc / 83 MHz mem bus = 1087 */ +/* ori r4,r4,0x0cc4 / 66 MHz mem bus = 817 */ + ori r4,r4,0x04cc /* 33 MHz mem bus (SAFE) = 307 */ +/* ori r4,r4,0x0002 / Reserve a page */ +/* ori r4,r4,0x0001 / RWM parity */ + + ori r3, r10, MCCR2@l + bl __pci_config_write_32 + + + /* MCCR3 */ + lis r4,0x0000 /* BSTOPRE_M = 7 (see A/N) */ + oris r4,r4,0x0500 /* REFREC = 8 clocks */ + ori r3, r10, MCCR3@l + bl __pci_config_write_32 + + /* MCCR4 */ /* Turn on registered buffer mode */ + lis r4, 0x2000 /* PRETOACT = 3 clocks */ + oris r4,r4,0x0400 /* ACTOPRE = 5 clocks */ +/* oris r4,r4,0x0080 / Enable 8-beat burst (32-bit bus) */ +/* oris r4,r4,0x0040 / Enable Inline ECC/Parity */ + oris r4,r4,0x0020 /* EXTROM enabled */ + oris r4,r4,0x0010 /* Registered buffers */ +/* oris r4,r4,0x0000 / BSTOPRE_U = 0 (see A/N) */ + oris r4,r4,0x0002 /* DBUS_SIZ[2] (8 bit on RCS1) */ + +/* ori r4,r4,0x8000 / Registered DIMMs */ + ori r4,r4,0x2000 /*CAS Latency (CL=3) (see RDLAT) */ +/* ori r4,r4,0x2000 / CAS Latency (CL=2) (see RDLAT) */ +/* ori r4,r4,0x0300 / Sequential wrap/8-beat burst */ + ori r4,r4,0x0200 /* Sequential wrap/4-beat burst */ + ori r4,r4,0x0030 /* ACTORW = 3 clocks */ + ori r4,r4,0x0009 /* BSTOPRE_L = 9 (see A/N) */ + + ori r3, r10, MCCR4@l + bl __pci_config_write_32 + + /* MSAR1 */ + lis r4, 0xc0804000@h + ori r4, r4, 0xc0804000@l + ori r3, r10, MSAR1@l + bl __pci_config_write_32 + + /* MSAR2 */ + lis r4, 0xc0804000@h + ori r4, r4, 0xc0804000@l + ori r3, r10, MSAR2@l + bl __pci_config_write_32 + + /* MESAR1 */ + lis r4, 0x00000000@h + ori r4, r4, 0x00000000@l + ori r3, r10, EMSAR1@l + bl __pci_config_write_32 + + /* MESAR2 */ + lis r4, 0x01010101@h + ori r4, r4, 0x01010101@l + ori r3, r10, EMSAR2@l + bl __pci_config_write_32 + + /* MEAR1 */ + lis r4, 0xffbf7f3f@h + ori r4, r4, 0xffbf7f3f@l + ori r3, r10, MEAR1@l + bl __pci_config_write_32 + + /* MEAR2 */ + lis r4, 0xffbf7f3f@h + ori r4, r4, 0xffbf7f3f@l + ori r3, r10, MEAR2@l + bl __pci_config_write_32 + + /* MEEAR1 */ + lis r4, 0x00000000@h + ori r4, r4, 0x00000000@l + ori r3, r10, EMEAR1@l + bl __pci_config_write_32 + + /* MEEAR2 */ + lis r4, 0x01010101@h + ori r4, r4, 0x01010101@l + ori r3, r10, EMEAR2@l + bl __pci_config_write_32 + + /* ODCR */ + li r4, 0x7f + ori r3, r10, ODCR@l + bl __pci_config_write_8 + + /* MBER */ + li r4, 0x01 + ori r3, r10, MBER@l + bl __pci_config_write_8 + + /* Page CTR aka PGMAX */ + li r4, 0x32 + ori r3, r10, 0x70 + bl __pci_config_write_8 + +#if 0 + /* CLK Drive */ + ori r4, r10, 0xfc01 /* Top bit will be ignored */ + ori r3, r10, 0x74 + bl __pci_config_write_16 +#endif + + /* delay */ + lis r7, 1 + mtctr r7 +label1: bdnz label1 + + /* Set memgo bit */ + /* MCCR1 */ + ori r3, r10, MCCR1@l + bl __pci_config_read_32 + lis r7, 0x0008 + or r4, r3, r7 + ori r3, r10, MCCR1@l + bl __pci_config_write_32 + + /* delay again */ + lis r7, 1 + mtctr r7 +label2: bdnz label2 +#if 0 +/* DEBUG: Infinite loop, write then read */ +loop: + lis r7, 0xffff + mtctr r7 + li r3, 0x5004 + lis r4, 0xa0a0 + ori r4, r4, 0x5050 + bl write_32_ne + li r3, 0x5004 + bl read_32_ne + bdnz loop +#endif + mtlr r11 + blr +#endif diff --git a/board/bmw/flash.c b/board/bmw/flash.c new file mode 100644 index 0000000..7fba174 --- /dev/null +++ b/board/bmw/flash.c @@ -0,0 +1,779 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define ROM_CS0_START 0xFF800000 +#define ROM_CS1_START 0xFF000000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word (flash_info_t * info, ulong dest, ulong data); + +#if 0 +static void flash_get_offsets (ulong base, flash_info_t * info); +#endif /* 0 */ + +/*flash command address offsets*/ + +#if 0 +#define ADDR0 (0x555) +#define ADDR1 (0x2AA) +#define ADDR3 (0x001) +#else +#define ADDR0 (0xAAA) +#define ADDR1 (0x555) +#define ADDR3 (0x001) +#endif + +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------- + */ + +#if 0 +static int byte_parity_odd (unsigned char x) __attribute__ ((const)); +#endif /* 0 */ +static unsigned long flash_id (unsigned char mfct, unsigned char chip) + __attribute__ ((const)); + +typedef struct { + FLASH_WORD_SIZE extval; + unsigned short intval; +} map_entry; + +#if 0 +static int byte_parity_odd (unsigned char x) +{ + x ^= x >> 4; + x ^= x >> 2; + x ^= x >> 1; + return (x & 0x1) != 0; +} +#endif /* 0 */ + + +static unsigned long flash_id (unsigned char mfct, unsigned char chip) +{ + static const map_entry mfct_map[] = { + {(FLASH_WORD_SIZE) AMD_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, + {(FLASH_WORD_SIZE) FUJ_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, + {(FLASH_WORD_SIZE) STM_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, + {(FLASH_WORD_SIZE) MT_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, + {(FLASH_WORD_SIZE) INTEL_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, + {(FLASH_WORD_SIZE) INTEL_ALT_MANU, + (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} + }; + + static const map_entry chip_map[] = { + {AMD_ID_F040B, FLASH_AM040}, + {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} + }; + + const map_entry *p; + unsigned long result = FLASH_UNKNOWN; + + /* find chip id */ + for (p = &chip_map[0]; + p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) + if (p->extval == chip) { + result = FLASH_VENDMASK | p->intval; + break; + } + + /* find vendor id */ + for (p = &mfct_map[0]; + p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) + if (p->extval == mfct) { + result &= ~FLASH_VENDMASK; + result |= (unsigned long) p->intval << 16; + break; + } + + return result; +} + + +unsigned long flash_init (void) +{ + unsigned long i; + unsigned char j; + static const ulong flash_banks[] = CFG_FLASH_BANKS; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info_t *const pflinfo = &flash_info[i]; + + pflinfo->flash_id = FLASH_UNKNOWN; + pflinfo->size = 0; + pflinfo->sector_count = 0; + } + + for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) { + flash_info_t *const pflinfo = &flash_info[i]; + const unsigned long base_address = flash_banks[i]; + volatile FLASH_WORD_SIZE *const flash = + (FLASH_WORD_SIZE *) base_address; +#if 0 + volatile FLASH_WORD_SIZE *addr2; +#endif +#if 0 + /* write autoselect sequence */ + flash[0x5555] = 0xaa; + flash[0x2aaa] = 0x55; + flash[0x5555] = 0x90; +#else + flash[0xAAA << (3 * i)] = 0xaa; + flash[0x555 << (3 * i)] = 0x55; + flash[0xAAA << (3 * i)] = 0x90; +#endif + __asm__ __volatile__ ("sync"); + +#if 0 + pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]); +#else + pflinfo->flash_id = + flash_id (flash[0x0], flash[0x2 + 14 * i]); +#endif + + switch (pflinfo->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + pflinfo->size = 0x00080000; + pflinfo->sector_count = 8; + for (j = 0; j < 8; j++) { + pflinfo->start[j] = + base_address + 0x00010000 * j; + pflinfo->protect[j] = flash[(j << 16) | 0x2]; + } + break; + case FLASH_STM800AB: + pflinfo->size = 0x00100000; + pflinfo->sector_count = 19; + pflinfo->start[0] = base_address; + pflinfo->start[1] = base_address + 0x4000; + pflinfo->start[2] = base_address + 0x6000; + pflinfo->start[3] = base_address + 0x8000; + for (j = 1; j < 16; j++) { + pflinfo->start[j + 3] = + base_address + 0x00010000 * j; + } +#if 0 + /* check for protected sectors */ + for (j = 0; j < pflinfo->sector_count; j++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE + *) (pflinfo->start[j]); + if (pflinfo->flash_id & FLASH_MAN_SST) + pflinfo->protect[j] = 0; + else + pflinfo->protect[j] = addr2[2] & 1; + } +#endif + break; + } + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + /* reset device to read mode */ + flash[0x0000] = 0xf0; + __asm__ __volatile__ ("sync"); + } + + return flash_info[0].size + flash_info[1].size; +} + +#if 0 +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_MAN_SST) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + +} +#endif /* 0 */ + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + static const char unk[] = "Unknown"; + const char *mfct = unk, *type = unk; + unsigned int i; + + if (info->flash_id != FLASH_UNKNOWN) { + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + mfct = "AMD"; + break; + case FLASH_MAN_FUJ: + mfct = "FUJITSU"; + break; + case FLASH_MAN_STM: + mfct = "STM"; + break; + case FLASH_MAN_SST: + mfct = "SST"; + break; + case FLASH_MAN_BM: + mfct = "Bright Microelectonics"; + break; + case FLASH_MAN_INTEL: + mfct = "Intel"; + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + type = "AM29F040B (512K * 8, uniform sector size)"; + break; + case FLASH_AM400B: + type = "AM29LV400B (4 Mbit, bottom boot sect)"; + break; + case FLASH_AM400T: + type = "AM29LV400T (4 Mbit, top boot sector)"; + break; + case FLASH_AM800B: + type = "AM29LV800B (8 Mbit, bottom boot sect)"; + break; + case FLASH_AM800T: + type = "AM29LV800T (8 Mbit, top boot sector)"; + break; + case FLASH_AM160T: + type = "AM29LV160T (16 Mbit, top boot sector)"; + break; + case FLASH_AM320B: + type = "AM29LV320B (32 Mbit, bottom boot sect)"; + break; + case FLASH_AM320T: + type = "AM29LV320T (32 Mbit, top boot sector)"; + break; + case FLASH_STM800AB: + type = "M29W800AB (8 Mbit, bottom boot sect)"; + break; + case FLASH_SST800A: + type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; + break; + case FLASH_SST160A: + type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; + break; + } + } + + printf ("\n Brand: %s Type: %s\n" + " Size: %lu KB in %d Sectors\n", + mfct, type, info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; i++) { + unsigned long size; + unsigned int erased; + unsigned long *flash = (unsigned long *) info->start[i]; + + /* + * Check if whole sector is erased + */ + size = (i != (info->sector_count - 1)) ? + (info->start[i + 1] - info->start[i]) >> 2 : + (info->start[0] + info->size - info->start[i]) >> 2; + + for (flash = (unsigned long *) info->start[i], erased = 1; + (flash != (unsigned long *) info->start[i] + size) + && erased; flash++) + erased = *flash == ~0x0UL; + + printf ("%s %08lX %s %s", + (i % 5) ? "" : "\n ", + info->start[i], + erased ? "E" : " ", info->protect[i] ? "RO" : " "); + } + + puts ("\n"); + return; +} + +#if 0 + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; + + printf ("flash_get_size: \n"); + /* Write auto select command: read Manufacturer ID */ + eieio (); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90; + value = addr2[0]; + + switch (value) { + case (FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + printf ("recognised manufacturer"); + + value = addr2[ADDR3]; /* device ID */ + debug ("\ndev_code=%x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE) SST_ID_xF800A: + info->flash_id += FLASH_SST800A; + info->sector_count = 16; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE) SST_ID_xF160A: + info->flash_id += FLASH_SST160A; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + printf ("flash id %lx; sector count %x, size %lx\n", info->flash_id, + info->sector_count, info->size); + /* set up sector start address table */ + if (info->flash_id & FLASH_MAN_SST) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); + if (info->flash_id & FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *) info->start[0]; + *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +#endif + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + unsigned char sh8b; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) + && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info-> + start + [sect] + - + info-> + start + [0]) << + sh8b)); + if (info->flash_id & FLASH_MAN_SST) { + addr[ADDR0 << sh8b] = + (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = + (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0 << sh8b] = + (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0 << sh8b] = + (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = + (FLASH_WORD_SIZE) 0x00550055; + addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ + udelay (30000); /* wait 30 ms */ + } else + addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - + info-> + start[0]) << sh8b)); + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; + volatile FLASH_WORD_SIZE *dest2; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int flag; + int i; + unsigned char sh8b; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) + && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; + + dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + + info->start[0]); + + /* Check if Flash is (sufficiently) erased */ + if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i << sh8b] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c new file mode 100644 index 0000000..d72c861 --- /dev/null +++ b/board/bmw/m48t59y.c @@ -0,0 +1,322 @@ +/* + * SGS M48-T59Y TOD/NVRAM Driver + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. + * + * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * SGS M48-T59Y TOD/NVRAM Driver + * + * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and + * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD) + * registers which are used to set/get the internal date/time functions. + * + * This module implements Y2K compliance by taking full year numbers + * and translating back and forth from the TOD 2-digit year. + * + * NOTE: for proper interaction with an operating system, the TOD should + * be used to store Universal Coordinated Time (GMT) and timezone + * conversions should be used. + * + * Here is a diagram of the memory layout: + * + * +---------------------------------------------+ 0xffe0a000 + * | Non-volatile memory | . + * | | . + * | (8176 bytes of Non-volatile memory) | . + * | | . + * +---------------------------------------------+ 0xffe0bff0 + * | Flags | + * +---------------------------------------------+ 0xffe0bff1 + * | Unused | + * +---------------------------------------------+ 0xffe0bff2 + * | Alarm Seconds | + * +---------------------------------------------+ 0xffe0bff3 + * | Alarm Minutes | + * +---------------------------------------------+ 0xffe0bff4 + * | Alarm Date | + * +---------------------------------------------+ 0xffe0bff5 + * | Interrupts | + * +---------------------------------------------+ 0xffe0bff6 + * | WatchDog | + * +---------------------------------------------+ 0xffe0bff7 + * | Calibration | + * +---------------------------------------------+ 0xffe0bff8 + * | Seconds | + * +---------------------------------------------+ 0xffe0bff9 + * | Minutes | + * +---------------------------------------------+ 0xffe0bffa + * | Hours | + * +---------------------------------------------+ 0xffe0bffb + * | Day | + * +---------------------------------------------+ 0xffe0bffc + * | Date | + * +---------------------------------------------+ 0xffe0bffd + * | Month | + * +---------------------------------------------+ 0xffe0bffe + * | Year (2 digits only) | + * +---------------------------------------------+ 0xffe0bfff + */ +#include +#include +#include "bmw.h" + +/* + * Imported from mousse.h: + * + * TOD_REG_BASE Base of m48t59y TOD registers + * SYS_TOD_UNPROTECT() Disable NVRAM write protect + * SYS_TOD_PROTECT() Re-enable NVRAM write protect + */ + +#define YEAR 0xf +#define MONTH 0xe +#define DAY 0xd +#define DAY_OF_WEEK 0xc +#define HOUR 0xb +#define MINUTE 0xa +#define SECOND 0x9 +#define CONTROL 0x8 +#define WATCH 0x7 +#define INTCTL 0x6 +#define WD_DATE 0x5 +#define WD_HOUR 0x4 +#define WD_MIN 0x3 +#define WD_SEC 0x2 +#define _UNUSED 0x1 +#define FLAGS 0x0 + +#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE) + +int m48_tod_init(void) +{ + SYS_TOD_UNPROTECT(); + + M48_ADDR[CONTROL] = 0; + M48_ADDR[WATCH] = 0; + M48_ADDR[INTCTL] = 0; + + /* + * If the oscillator is currently stopped (as on a new part shipped + * from the factory), start it running. + * + * Here is an example of the TOD bytes on a brand new M48T59Y part: + * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01 + */ + + if (M48_ADDR[SECOND] & 0x80) + M48_ADDR[SECOND] = 0; + + /* Is battery low */ + if ( M48_ADDR[FLAGS] & 0x10) { + printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n"); + } + + SYS_TOD_PROTECT(); + + return 0; +} + +/* + * m48_tod_set + */ + +static int to_bcd(int value) +{ + return value / 10 * 16 + value % 10; +} + +static int from_bcd(int value) +{ + return value / 16 * 10 + value % 16; +} + +static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */ +{ + static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; + y -= m < 3; + return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7; +} + +/* + * Note: the TOD should store the current GMT + */ + +int m48_tod_set(int year, /* 1980-2079 */ + int month, /* 01-12 */ + int day, /* 01-31 */ + int hour, /* 00-23 */ + int minute, /* 00-59 */ + int second) /* 00-59 */ + +{ + SYS_TOD_UNPROTECT(); + + M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */ + + M48_ADDR[YEAR] = to_bcd(year % 100); + M48_ADDR[MONTH] = to_bcd(month); + M48_ADDR[DAY] = to_bcd(day); + M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1; + M48_ADDR[HOUR] = to_bcd(hour); + M48_ADDR[MINUTE] = to_bcd(minute); + M48_ADDR[SECOND] = to_bcd(second); + + M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */ + + SYS_TOD_PROTECT(); + + return 0; +} + +/* + * Note: the TOD should store the current GMT + */ + +int m48_tod_get(int *year, /* 1980-2079 */ + int *month, /* 01-12 */ + int *day, /* 01-31 */ + int *hour, /* 00-23 */ + int *minute, /* 00-59 */ + int *second) /* 00-59 */ +{ + int y; + + SYS_TOD_UNPROTECT(); + + M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */ + + y = from_bcd(M48_ADDR[YEAR]); + *year = y < 80 ? 2000 + y : 1900 + y; + *month = from_bcd(M48_ADDR[MONTH]); + *day = from_bcd(M48_ADDR[DAY]); + /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */ + *hour = from_bcd(M48_ADDR[HOUR]); + *minute = from_bcd(M48_ADDR[MINUTE]); + *second = from_bcd(M48_ADDR[SECOND] & 0x7f); + + M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */ + + SYS_TOD_PROTECT(); + + return 0; +} + +int m48_tod_get_second(void) +{ + return from_bcd(M48_ADDR[SECOND] & 0x7f); +} + +/* + * Watchdog function + * + * If usec is 0, the watchdog timer is disarmed. + * + * If usec is non-zero, the watchdog timer is armed (or re-armed) for + * approximately usec microseconds (if the exact requested usec is + * not supported by the chip, the next higher available value is used). + * + * Minimum watchdog timeout = 62500 usec + * Maximum watchdog timeout = 124 sec (124000000 usec) + */ + +void m48_watchdog_arm(int usec) +{ + int mpy, res; + + SYS_TOD_UNPROTECT(); + + if (usec == 0) { + res = 0; + mpy = 0; + } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */ + res = 0; + mpy = (usec + 62499) / 62500; + } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */ + res = 1; + mpy = (usec + 249999) / 250000; + } else if (usec < 32000000) { /* Resolution: 1s if below 32s */ + res = 2; + mpy = (usec + 999999) / 1000000; + } else { /* Resolution: 4s up to 124s */ + res = 3; + mpy = (usec + 3999999) / 4000000; + if (mpy > 31) + mpy = 31; + } + + M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */ + mpy << 2 | + res); + + SYS_TOD_PROTECT(); +} + +/* + * U-Boot RTC support. + */ +void +rtc_get( struct rtc_time *tmp ) +{ + m48_tod_get(&tmp->tm_year, + &tmp->tm_mon, + &tmp->tm_mday, + &tmp->tm_hour, + &tmp->tm_min, + &tmp->tm_sec); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + +#ifdef RTC_DEBUG + printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); +#endif +} + +void +rtc_set( struct rtc_time *tmp ) +{ + m48_tod_set(tmp->tm_year, /* 1980-2079 */ + tmp->tm_mon, /* 01-12 */ + tmp->tm_mday, /* 01-31 */ + tmp->tm_hour, /* 00-23 */ + tmp->tm_min, /* 00-59 */ + tmp->tm_sec); /* 00-59 */ + +#ifdef RTC_DEBUG + printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + +} + +void +rtc_reset (void) +{ + m48_tod_init(); +} diff --git a/board/bmw/m48t59y.h b/board/bmw/m48t59y.h new file mode 100644 index 0000000..717300d --- /dev/null +++ b/board/bmw/m48t59y.h @@ -0,0 +1,57 @@ +/* + * SGS M48-T59Y TOD/NVRAM Driver + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. + * + * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __M48_T59_Y_H +#define __M48_T59_Y_H + +/* + * M48 T59Y -Timekeeping Battery backed SRAM. + */ + +int m48_tod_init(void); + +int m48_tod_set(int year, + int month, + int day, + int hour, + int minute, + int second); + +int m48_tod_get(int *year, + int *month, + int *day, + int *hour, + int *minute, + int *second); + +int m48_tod_get_second(void); + +void m48_watchdog_arm(int usec); + +#endif /*!__M48_T59_Y_H */ diff --git a/board/bmw/ns16550.c b/board/bmw/ns16550.c new file mode 100644 index 0000000..7064567 --- /dev/null +++ b/board/bmw/ns16550.c @@ -0,0 +1,57 @@ +/* + * COM1 NS16550 support + * originally from linux source (arch/ppc/boot/ns16550.c) + * modified to use CFG_ISA_MEM and new defines + */ + +#include +#include "ns16550.h" + +typedef struct NS16550 *NS16550_t; + +const NS16550_t COM_PORTS[] = + { (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), +(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) }; + +volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) +{ + volatile struct NS16550 *com_port; + + com_port = (struct NS16550 *) COM_PORTS[chan]; + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; /* Access baud rate */ + com_port->dll = baud_divisor & 0xff; /* 9600 baud */ + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ + com_port->mcr = MCR_RTS; /* RTS/DTR */ + com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ + return (com_port); +} + +void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) +{ + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; /* Access baud rate */ + com_port->dll = baud_divisor & 0xff; /* 9600 baud */ + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ + com_port->mcr = MCR_RTS; /* RTS/DTR */ + com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ +} + +void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c) +{ + while ((com_port->lsr & LSR_THRE) == 0); + com_port->thr = c; +} + +unsigned char NS16550_getc (volatile struct NS16550 *com_port) +{ + while ((com_port->lsr & LSR_DR) == 0); + return (com_port->rbr); +} + +int NS16550_tstc (volatile struct NS16550 *com_port) +{ + return ((com_port->lsr & LSR_DR) != 0); +} diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h new file mode 100644 index 0000000..104f45b --- /dev/null +++ b/board/bmw/ns16550.h @@ -0,0 +1,79 @@ +/* + * NS16550 Serial Port + * originally from linux source (arch/ppc/boot/ns16550.h) + * modified slightly to + * have addresses as offsets from CFG_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + * further modified to support the 8245 duart + * modifications (c) Paul Jimenez, Musenki, Inc. 2001. + */ + + +struct NS16550 { + unsigned char rbrthrdlb; /* 0 */ + unsigned char ierdmb; /* 1 */ + unsigned char iirfcrafr; /* 2 */ + unsigned char lcr; /* 3 */ + unsigned char mcr; /* 4 */ + unsigned char lsr; /* 5 */ + unsigned char msr; /* 6 */ + unsigned char scr; /* 7 */ + unsigned char reserved[2]; /* 8 & 9 */ + unsigned char dsr; /* 10 */ + unsigned char dcr; /* 11 */ +}; + + +#define rbr rbrthrdlb +#define thr rbrthrdlb +#define dll rbrthrdlb +#define ier ierdmb +#define dlm ierdmb +#define iir iirfcrafr +#define fcr iirfcrafr +#define afr iirfcrafr + +#define FCR_FIFO_EN 0x01 /*fifo enable */ +#define FCR_RXSR 0x02 /*reciever soft reset */ +#define FCR_TXSR 0x04 /*transmitter soft reset */ +#define FCR_DMS 0x08 /* DMA Mode Select */ + +#define MCR_RTS 0x02 /* Readyu to Send */ +#define MCR_LOOP 0x10 /* Local loopback mode enable */ +/* #define MCR_DTR 0x01 noton 8245 duart */ +/* #define MCR_DMA_EN 0x04 noton 8245 duart */ +/* #define MCR_TX_DFR 0x08 noton 8245 duart */ + +#define LCR_WLS_MSK 0x03 /* character length slect mask */ +#define LCR_WLS_5 0x00 /* 5 bit character length */ +#define LCR_WLS_6 0x01 /* 6 bit character length */ +#define LCR_WLS_7 0x02 /* 7 bit character length */ +#define LCR_WLS_8 0x03 /* 8 bit character length */ +#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define LCR_PEN 0x08 /* Parity eneble */ +#define LCR_EPS 0x10 /* Even Parity Select */ +#define LCR_STKP 0x20 /* Stick Parity */ +#define LCR_SBRK 0x40 /* Set Break */ +#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */ + +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +/* useful defaults for LCR*/ +#define LCR_8N1 0x03 + + +volatile struct NS16550 *NS16550_init (int chan, int baud_divisor); +void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c); +unsigned char NS16550_getc (volatile struct NS16550 *com_port); +int NS16550_tstc (volatile struct NS16550 *com_port); +void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor); diff --git a/board/bmw/serial.c b/board/bmw/serial.c new file mode 100644 index 0000000..f36a41b --- /dev/null +++ b/board/bmw/serial.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "ns16550.h" + +#if CONFIG_CONS_INDEX == 1 +static struct NS16550 *console = + (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500); +#elif CONFIG_CONS_INDEX == 2 +static struct NS16550 *console = + (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500); +#else +#error no valid console defined +#endif + +extern ulong get_bus_freq (ulong); + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = gd->bus_clk / 16 / gd->baudrate; + + NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor); + + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') { + serial_putc ('\r'); + } + NS16550_putc (console, c); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + + +int serial_getc (void) +{ + return NS16550_getc (console); +} + +int serial_tstc (void) +{ + return NS16550_tstc (console); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate; + + NS16550_reinit (console, clock_divisor); +} diff --git a/board/bmw/u-boot.lds b/board/bmw/u-boot.lds new file mode 100644 index 0000000..eaee3fd --- /dev/null +++ b/board/bmw/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/c2mon/Makefile b/board/c2mon/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/c2mon/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c new file mode 100644 index 0000000..ca8eb0c --- /dev/null +++ b/board/c2mon/c2mon.c @@ -0,0 +1,234 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + unsigned char *s = (unsigned char *)getenv ("serial#"); + + puts ("Board: TTTech C2MON "); + + for (; s && *s; ++s) { + if (*s == ' ') + break; + putc (*s); + } + + putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long reg; + long int size8, size9; + long int size = 0; + + upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 2 the SDRAM bank 2 at physical address 0. + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, + SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, + SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size = size9; +/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + size = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); +/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type + * For types > 128 MBit leave it at the current (fast) rate + */ + if (size < 0x02000000) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping + */ + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + /* + * No bank 1 + * + * invalidate bank + */ + memctl->memc_br3 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + + udelay (10000); + + return (size); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} diff --git a/board/c2mon/config.mk b/board/c2mon/config.mk new file mode 100644 index 0000000..c2d21e2 --- /dev/null +++ b/board/c2mon/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TTTech C2MON boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/c2mon/flash.c b/board/c2mon/flash.c new file mode 100644 index 0000000..b2be21c --- /dev/null +++ b/board/c2mon/flash.c @@ -0,0 +1,570 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifndef CFG_ENV_ADDR +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + + if (size_b1) { + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[1]); +#endif + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds new file mode 100644 index 0000000..cdf550f --- /dev/null +++ b/board/c2mon/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug new file mode 100644 index 0000000..3165d56 --- /dev/null +++ b/board/c2mon/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/canmb/Makefile b/board/canmb/Makefile new file mode 100644 index 0000000..607833f --- /dev/null +++ b/board/canmb/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +#../common/flash.o ../common/vpd.o ../common/am79c874.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c new file mode 100644 index 0000000..1782b31 --- /dev/null +++ b/board/canmb/canmb.c @@ -0,0 +1,251 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m32s2-75.h" +#endif + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +#if defined(CONFIG_MPC5200) +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize + dramsize2; +} + +#elif defined(CONFIG_MGT5100) + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup and enable SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; + __asm__ volatile ("sync"); + + /* find RAM size */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* set SDRAM end address according to size */ + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); + +#else /* CFG_RAMBOOT */ + + /* Retrieve amount of SDRAM available */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif + +int checkboard (void) +{ + puts ("Board: CANMB\n"); + return 0; +} + +int board_early_init_r (void) +{ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + *(vu_long *)MPC5XXX_BOOTCS_START = + *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); + *(vu_long *)MPC5XXX_BOOTCS_STOP = + *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); + return 0; +} diff --git a/board/canmb/config.mk b/board/canmb/config.mk new file mode 100644 index 0000000..a163b34 --- /dev/null +++ b/board/canmb/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2003 +# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# CANMB board +# +# allowed and functional TEXT_BASE values: +# +# 0xfe000000 low boot at 0x00000100 (default board setting) +# 0x00100000 RAM load and test +# + +TEXT_BASE = 0xFE000000 +#TEXT_BASE = 0x00100000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h new file mode 100644 index 0000000..ffdf039 --- /dev/null +++ b/board/canmb/mt48lc16m32s2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/canmb/u-boot.lds b/board/canmb/u-boot.lds new file mode 100644 index 0000000..88dc118 --- /dev/null +++ b/board/canmb/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cds/common/cadmus.c b/board/cds/common/cadmus.c new file mode 100644 index 0000000..5f86de5 --- /dev/null +++ b/board/cds/common/cadmus.c @@ -0,0 +1,95 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include + + +/* + * CADMUS Board System Registers + */ +#ifndef CFG_CADMUS_BASE_REG +#define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) +#endif + +typedef struct cadmus_reg { + u_char cm_ver; /* Board version */ + u_char cm_csr; /* General control/status */ + u_char cm_rst; /* Reset control */ + u_char cm_hsclk; /* High speed clock */ + u_char cm_hsxclk; /* High speed clock extended */ + u_char cm_led; /* LED data */ + u_char cm_pci; /* PCI control/status */ + u_char cm_dma; /* DMA control */ + u_char cm_reserved[248]; /* Total 256 bytes */ +} cadmus_reg_t; + + +unsigned int +get_board_version(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + + return cadmus->cm_ver; +} + + +unsigned long +get_clock_freq(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + + uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ + + if (pci1_speed == 0) { + return 33000000; + } else if (pci1_speed == 1) { + return 66000000; + } else { + /* Really, unknown. Be safe? */ + return 33000000; + } +} + + +unsigned int +get_pci_slot(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + + /* + * PCI slot in USER bits CSR[6:7] by convention. + */ + return ((cadmus->cm_csr >> 6) & 0x3) + 1; +} + + +unsigned int +get_pci_dual(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + + /* + * PCI DUAL in CM_PCI[3] + */ + return cadmus->cm_pci & 0x10; +} diff --git a/board/cds/common/cadmus.h b/board/cds/common/cadmus.h new file mode 100644 index 0000000..217ea64 --- /dev/null +++ b/board/cds/common/cadmus.h @@ -0,0 +1,54 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CADMUS_H_ +#define __CADMUS_H_ + + +/* + * CADMUS Board System Register interface. + */ + +/* + * Returns board version register. + */ +extern unsigned int get_board_version(void); + +/* + * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ. + */ +extern unsigned long get_clock_freq(void); + + +/* + * Returns 1 - 4, as found in the USER CSR[6:7] bits. + */ +extern unsigned int get_pci_slot(void); + + +/* + * Returns PCI DUAL as found in CM_PCI[3]. + */ +extern unsigned int get_pci_dual(void); + + +#endif /* __CADMUS_H_ */ diff --git a/board/cds/common/eeprom.c b/board/cds/common/eeprom.c new file mode 100644 index 0000000..5034e0c --- /dev/null +++ b/board/cds/common/eeprom.c @@ -0,0 +1,60 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#include "eeprom.h" + + +typedef struct { + char idee_pcbid[4]; /* "CCID" for CDC v1.X */ + u8 idee_major; + u8 idee_minor; + char idee_serial[10]; + char idee_errata[2]; + char idee_date[8]; /* yyyymmdd */ + /* The rest of the EEPROM space is reserved */ +} id_eeprom_t; + + +unsigned int +get_cpu_board_revision(void) +{ + uint major = 0; + uint minor = 0; + + id_eeprom_t id_eeprom; + + i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, + (uchar *) &id_eeprom, sizeof(id_eeprom)); + + major = id_eeprom.idee_major; + minor = id_eeprom.idee_minor; + + if (major == 0xff && minor == 0xff) { + major = minor = 0; + } + + return MPC85XX_CPU_BOARD_REV(major,minor); +} diff --git a/board/cds/common/eeprom.h b/board/cds/common/eeprom.h new file mode 100644 index 0000000..12a0789 --- /dev/null +++ b/board/cds/common/eeprom.h @@ -0,0 +1,50 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __EEPROM_H_ +#define __EEPROM_H_ + + +/* + * EEPROM Board System Register interface. + */ + + +/* + * CPU Board Revision + */ +#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff)) +#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff) +#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff) + +#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0) +#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0) +#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1) + +/* + * Returns CPU board revision register as a 16-bit value with + * the Major in the high byte, and Minor in the low byte. + */ +extern unsigned int get_cpu_board_revision(void); + + +#endif /* __CADMUS_H_ */ diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile new file mode 100644 index 0000000..0d4abbd --- /dev/null +++ b/board/cds/mpc8541cds/Makefile @@ -0,0 +1,51 @@ +# +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o \ + ../common/cadmus.o \ + ../common/eeprom.o + +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cds/mpc8541cds/config.mk b/board/cds/mpc8541cds/config.mk new file mode 100644 index 0000000..17cc8bc --- /dev/null +++ b/board/cds/mpc8541cds/config.mk @@ -0,0 +1,30 @@ +# +# Copyright 2004 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8541cds board +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1 diff --git a/board/cds/mpc8541cds/init.S b/board/cds/mpc8541cds/init.S new file mode 100644 index 0000000..53dcd0d --- /dev/null +++ b/board/cds/mpc8541cds/init.S @@ -0,0 +1,255 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) + .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 6 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + entry_end diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c new file mode 100644 index 0000000..6b8aa68 --- /dev/null +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -0,0 +1,504 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/cadmus.h" +#include "../common/eeprom.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + /* PCI slot in USER bits CSR[6:7] by convention. */ + uint pci_slot = get_pci_slot (); + + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + + uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + uint cpu_board_rev = get_cpu_board_revision (); + + printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", + get_board_version (), pci_slot); + + printf ("CPU Board Revision %d.%d (0x%04x)\n", + MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), + MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); + + printf (" PCI1: %d bit, %s MHz, %s\n", + (pci1_32) ? 32 : 64, + (pci1_speed == 33000000) ? "33" : + (pci1_speed == 66000000) ? "66" : "unknown", + pci1_clk_sel ? "sync" : "async"); + + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } + + /* + * Initialize local bus. + */ + local_bus_init (); + + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur= &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + dram_size = spd_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + uint temp_lbcdll; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr |= 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + + } else { + lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + + uint idx; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint cpu_board_rev; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + asm("msync"); + + lbc->br2 = CFG_BR2_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * Determine which address lines to use baed on CPU board rev. + */ + cpu_board_rev = get_cpu_board_revision(); + lsdmr_common = CFG_LBC_LSDMR_COMMON; + if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + } else { + /* + * Assume something unable to identify itself is + * really old, and likely has lines 16/17 mapped. + */ + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + } + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) + +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxcds_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxcds_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif +} diff --git a/board/cds/mpc8541cds/u-boot.lds b/board/cds/mpc8541cds/u-boot.lds new file mode 100644 index 0000000..1bea007 --- /dev/null +++ b/board/cds/mpc8541cds/u-boot.lds @@ -0,0 +1,149 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/cds/mpc8541cds/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/cds/mpc8541cds/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile new file mode 100644 index 0000000..0d4abbd --- /dev/null +++ b/board/cds/mpc8548cds/Makefile @@ -0,0 +1,51 @@ +# +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o \ + ../common/cadmus.o \ + ../common/eeprom.o + +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk new file mode 100644 index 0000000..242a676 --- /dev/null +++ b/board/cds/mpc8548cds/config.mk @@ -0,0 +1,30 @@ +# +# Copyright 2004 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8548cds board +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S new file mode 100644 index 0000000..53dcd0d --- /dev/null +++ b/board/cds/mpc8548cds/init.S @@ -0,0 +1,255 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) + .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 6 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + entry_end diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c new file mode 100644 index 0000000..5bc0890 --- /dev/null +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -0,0 +1,329 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "../common/cadmus.h" +#include "../common/eeprom.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + /* PCI slot in USER bits CSR[6:7] by convention. */ + uint pci_slot = get_pci_slot (); + + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + + uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + uint cpu_board_rev = get_cpu_board_revision (); + + printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", + get_board_version (), pci_slot); + + printf ("CPU Board Revision %d.%d (0x%04x)\n", + MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), + MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); + + printf (" PCI1: %d bit, %s MHz, %s\n", + (pci1_32) ? 32 : 64, + (pci1_speed == 33000000) ? "33" : + (pci1_speed == 66000000) ? "66" : "unknown", + pci1_clk_sel ? "sync" : "async"); + + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } + + /* + * Initialize local bus. + */ + local_bus_init (); + + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur= &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + dram_size = spd_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + clkdiv = (lbc->lcrr & 0x0f) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + + asm("sync;isync;msync"); +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + + uint idx; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint cpu_board_rev; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + asm("msync"); + + lbc->br2 = CFG_BR2_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * MPC8548 uses "new" 15-16 style addressing. + */ + cpu_board_rev = get_cpu_board_revision(); + lsdmr_common = CFG_LBC_LSDMR_COMMON; + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) + +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxcds_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxcds_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif +} diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds new file mode 100644 index 0000000..2c8fe96 --- /dev/null +++ b/board/cds/mpc8548cds/u-boot.lds @@ -0,0 +1,149 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/cds/mpc8548cds/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/cds/mpc8548cds/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile new file mode 100644 index 0000000..0d4abbd --- /dev/null +++ b/board/cds/mpc8555cds/Makefile @@ -0,0 +1,51 @@ +# +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o \ + ../common/cadmus.o \ + ../common/eeprom.o + +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cds/mpc8555cds/config.mk b/board/cds/mpc8555cds/config.mk new file mode 100644 index 0000000..5dcaa77 --- /dev/null +++ b/board/cds/mpc8555cds/config.mk @@ -0,0 +1,30 @@ +# +# Copyright 2004 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8555cds board +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1 diff --git a/board/cds/mpc8555cds/init.S b/board/cds/mpc8555cds/init.S new file mode 100644 index 0000000..53dcd0d --- /dev/null +++ b/board/cds/mpc8555cds/init.S @@ -0,0 +1,255 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) + .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 6 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + entry_end diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c new file mode 100644 index 0000000..18adf5b --- /dev/null +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -0,0 +1,501 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/cadmus.h" +#include "../common/eeprom.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + /* PCI slot in USER bits CSR[6:7] by convention. */ + uint pci_slot = get_pci_slot (); + + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + + uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + uint cpu_board_rev = get_cpu_board_revision (); + + printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", + get_board_version (), pci_slot); + + printf ("CPU Board Revision %d.%d (0x%04x)\n", + MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), + MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); + + printf (" PCI1: %d bit, %s MHz, %s\n", + (pci1_32) ? 32 : 64, + (pci1_speed == 33000000) ? "33" : + (pci1_speed == 66000000) ? "66" : "unknown", + pci1_clk_sel ? "sync" : "async"); + + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } + + /* + * Initialize local bus. + */ + local_bus_init (); + + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur= &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + dram_size = spd_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + uint temp_lbcdll; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr |= 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + + } else { + lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + + uint idx; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint cpu_board_rev; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + asm("msync"); + + lbc->br2 = CFG_BR2_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * Determine which address lines to use baed on CPU board rev. + */ + cpu_board_rev = get_cpu_board_revision(); + lsdmr_common = CFG_LBC_LSDMR_COMMON; + if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + } else { + /* + * Assume something unable to identify itself is + * really old, and likely has lines 16/17 mapped. + */ + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + } + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) + +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxcds_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxcds_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif +} diff --git a/board/cds/mpc8555cds/u-boot.lds b/board/cds/mpc8555cds/u-boot.lds new file mode 100644 index 0000000..2aa2ad7 --- /dev/null +++ b/board/cds/mpc8555cds/u-boot.lds @@ -0,0 +1,149 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/cds/mpc8555cds/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/cds/mpc8555cds/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile new file mode 100644 index 0000000..83e3ba4 --- /dev/null +++ b/board/cerf250/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := cerf250.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c new file mode 100644 index 0000000..cc1bc16 --- /dev/null +++ b/board/cerf250/cerf250.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of cerf PXA Board */ + gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/cerf250/config.mk b/board/cerf250/config.mk new file mode 100644 index 0000000..1a86cc9 --- /dev/null +++ b/board/cerf250/config.mk @@ -0,0 +1,5 @@ +# +# Cerf board with PXA250 cpu +# +# +TEXT_BASE = 0xa3080000 diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c new file mode 100644 index 0000000..ba82892 --- /dev/null +++ b/board/cerf250/flash.c @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0] ); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S new file mode 100644 index 0000000..c9b68d7 --- /dev/null +++ b/board/cerf250/lowlevel_init.S @@ -0,0 +1,411 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field, set SDRAM clocks free running */ + + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + + ldr r0, [r1, #MDREFR_OFFSET] + bic r0, r0, r2 + bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE) + orr r0, r0, r3 + + str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + /* set MDREFR according to user define with exception of a few bits */ + + ldr r4, =CFG_MDREFR_VAL + ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\ + MDREFR_K2RUN |MDREFR_K2DB2) + and r4, r4, r2 + bic r0, r0, r2 + orr r0, r0, r4 + + str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r0, [r1, #MDREFR_OFFSET] + + /* Step 4b: de-assert MDREFR:SLFRSH. */ + + bic r0, r0, #(MDREFR_SLFRSH) + str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r0, [r1, #MDREFR_OFFSET] + + + /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */ + + ldr r4, =CFG_MDREFR_VAL + ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \ + MDREFR_K1FREE | MDREFR_K2FREE) + and r4, r4, r2 + orr r0, r0, r4 + str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r0, [r1, #MDREFR_OFFSET] + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE +.rept 8 + str r2, [r3] +.endr + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + + /* We are finished with Intel's memory controller initialisation */ + + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + + /* default value in case no valid rotary switch setting is found */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size */ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + + /* FIXME */ + +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/cerf250/u-boot.lds b/board/cerf250/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/cerf250/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile new file mode 100644 index 0000000..c66dd71 --- /dev/null +++ b/board/cm4008/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := cm4008.o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c new file mode 100644 index 0000000..4d2013b --- /dev/null +++ b/board/cm4008/cm4008.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2005 + * Greg Ungerer, OpenGear Inc, + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) +#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b) + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ +int env_flash_cmdline (void) +{ + unsigned char *sp = (unsigned char *) 0x0201c020; + unsigned char *ep; + int len; + + /* Check if "erase" push button is depressed */ + if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) { + printf("### Entering network recovery mode...\n"); + setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0"); + setenv("bootcmd", "bootp 0x400000; gofsk 0x400000"); + setenv("bootdelay", "2"); + return 0; + } + + /* Check for flash based kernel boot args to use as default */ + for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++) + ; + + if ((len > 0) && (len <1024)) + setenv("bootargs", sp); + + return 0; +} + +int board_late_init (void) +{ + return 0; +} + + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of CM4008 */ + gd->bd->bi_arch_number = 624; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + /* power down all but port 0 on the switch */ + ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005); + ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005); + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/cm4008/config.mk b/board/cm4008/config.mk new file mode 100644 index 0000000..74eaeb0 --- /dev/null +++ b/board/cm4008/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x00f00000 diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c new file mode 100644 index 0000000..86c8e2a --- /dev/null +++ b/board/cm4008/flash.c @@ -0,0 +1,409 @@ +/* + * (C) Copyright 2005 + * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com + * + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (unsigned char * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, unsigned char data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + /* ignore for now */ + flash_info[i].flash_id = FLASH_UNKNOWN; + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + _bss_start - _armboot_start, + &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) + return; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (unsigned char * addr, flash_info_t * info) +{ + volatile unsigned char value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = 0xAA; + addr[0x2AAA] = 0x55; + addr[0x5555] = 0x90; + + mb (); + value = addr[0]; + + switch (value) { + + case (unsigned char)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = 0xFF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[2]; /* device ID */ + + switch (value) { + + case (unsigned char)INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (unsigned char)INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = 0xFF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + volatile unsigned char *addr; + unsigned char status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + addr = (volatile unsigned char *) (info->start[sect]); + *addr = 0x50; /* clear status register */ + *addr = 0x20; /* erase setup */ + *addr = 0xD0; /* erase confirm */ + + while (((status = *addr) & 0x80) != 0x80) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xB0; /* suspend erase */ + *addr = 0xFF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x50; /* clear status register cmd */ + *addr = 0xFF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + unsigned char data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + wp = addr; + port_width = 1; + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, unsigned char data) +{ + volatile unsigned char *addr = (volatile unsigned char *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = 0x40; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & 0x80) != 0x80) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = 0xFF; /* restore read mode */ + return (1); + } + } + + *addr = 0xFF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/cm4008/u-boot.lds b/board/cm4008/u-boot.lds new file mode 100644 index 0000000..ec09fa2 --- /dev/null +++ b/board/cm4008/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile new file mode 100644 index 0000000..f0d3451 --- /dev/null +++ b/board/cm41xx/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := cm41xx.o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c new file mode 100644 index 0000000..65eaa94 --- /dev/null +++ b/board/cm41xx/cm41xx.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2005 + * Greg Ungerer, OpenGear Inc, + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) +#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b) + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ +int env_flash_cmdline (void) +{ + unsigned char *sp = (unsigned char *) 0x0201c020; + unsigned char *ep; + int len; + + /* Check if "erase" push button is depressed */ + if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) { + printf("### Entering network recovery mode...\n"); + setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0"); + setenv("bootcmd", "bootp 0x400000; gofsk 0x400000"); + setenv("bootdelay", "2"); + return 0; + } + + /* Check for flash based kernel boot args to use as default */ + for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++) + ; + + if ((len > 0) && (len <1024)) + setenv("bootargs", sp); + + return 0; +} + +int board_late_init (void) +{ + return 0; +} + + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of CM41xx */ + gd->bd->bi_arch_number = 672; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + /* power down all but port 0 on the switch */ + ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005); + ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005); + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/cm41xx/config.mk b/board/cm41xx/config.mk new file mode 100644 index 0000000..74eaeb0 --- /dev/null +++ b/board/cm41xx/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x00f00000 diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c new file mode 100644 index 0000000..86c8e2a --- /dev/null +++ b/board/cm41xx/flash.c @@ -0,0 +1,409 @@ +/* + * (C) Copyright 2005 + * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com + * + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (unsigned char * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, unsigned char data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + /* ignore for now */ + flash_info[i].flash_id = FLASH_UNKNOWN; + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + _bss_start - _armboot_start, + &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) + return; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (unsigned char * addr, flash_info_t * info) +{ + volatile unsigned char value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = 0xAA; + addr[0x2AAA] = 0x55; + addr[0x5555] = 0x90; + + mb (); + value = addr[0]; + + switch (value) { + + case (unsigned char)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = 0xFF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[2]; /* device ID */ + + switch (value) { + + case (unsigned char)INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (unsigned char)INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = 0xFF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + volatile unsigned char *addr; + unsigned char status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + addr = (volatile unsigned char *) (info->start[sect]); + *addr = 0x50; /* clear status register */ + *addr = 0x20; /* erase setup */ + *addr = 0xD0; /* erase confirm */ + + while (((status = *addr) & 0x80) != 0x80) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xB0; /* suspend erase */ + *addr = 0xFF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x50; /* clear status register cmd */ + *addr = 0xFF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + unsigned char data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + wp = addr; + port_width = 1; + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, unsigned char data) +{ + volatile unsigned char *addr = (volatile unsigned char *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = 0x40; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & 0x80) != 0x80) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = 0xFF; /* restore read mode */ + return (1); + } + } + + *addr = 0xFF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/cm41xx/u-boot.lds b/board/cm41xx/u-boot.lds new file mode 100644 index 0000000..ec09fa2 --- /dev/null +++ b/board/cm41xx/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile new file mode 100644 index 0000000..d0def05 --- /dev/null +++ b/board/cmc_pu2/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cmc_pu2/at45.c b/board/cmc_pu2/at45.c new file mode 100644 index 0000000..3c00132 --- /dev/null +++ b/board/cmc_pu2/at45.c @@ -0,0 +1,621 @@ +/* Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#ifdef CONFIG_HAS_DATAFLASH +#include + +#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to +the Continuous Array Read function */ + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define AT91C_TIMEOUT_WRDY 200000 +#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ +#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ + +void AT91F_SpiInit(void) { + +/*-------------------------------------------------------------------*/ +/* SPI DataFlash Init */ +/*-------------------------------------------------------------------*/ + /* Configure PIOs */ + AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; + /* Enable CLock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; + + /* Reset the SPI */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; + + /* Configure SPI in Master Mode with No CS selected !!! */ + AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; + + /* Configure CS0 and CS3 */ + *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + + *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + +} + +void AT91F_SpiEnable(int cs) { + switch(cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); + break; + case 3: /* Configure SPI CS3 for Serial DataFlash Card */ + /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ + AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; + /* Configure PCS */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); + break; + } + + /* SPI_Enable */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; +} + +/*----------------------------------------------------------------------------*/ +/* \fn AT91F_SpiWrite */ +/* \brief Set the PDC registers for a transfert */ +/*----------------------------------------------------------------------------*/ +unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) +{ + unsigned int timeout; + + pDesc->state = BUSY; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + + /* Initialize the Transmit and Receive Pointer */ + AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; + AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; + + /* Intialize the Transmit and Receive Counters */ + AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; + AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; + + if ( pDesc->tx_data_size != 0 ) { + /* Initialize the Next Transmit and Next Receive Pointer */ + AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; + AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; + + /* Intialize the Next Transmit and Next Receive Counters */ + AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; + AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + timeout = 0; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; + while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + pDesc->state = IDLE; + + if (timeout >= CFG_SPI_WRITE_TOUT){ + printf("Error Timeout\n\r"); + return DATAFLASH_ERROR; + } + + return DATAFLASH_OK; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashSendCommand */ +/* \brief Generic function to send a command to the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashSendCommand( + AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress) +{ + unsigned int adr; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* process the address to obtain page address and byte address */ + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); + + /* fill the command buffer */ + pDataFlash->pDataFlashDesc->command[0] = OpCode; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); + } else { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + } + pDataFlash->pDataFlashDesc->command[5] = 0; + pDataFlash->pDataFlashDesc->command[6] = 0; + pDataFlash->pDataFlashDesc->command[7] = 0; + + /* Initialize the SpiData structure for the spi write fuction */ + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; + + /* send the command and read the data */ + return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashGetStatus */ +/* \brief Read the status register of the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) +{ + AT91S_DataFlashStatus status; + + /* if a transfert is in progress ==> return 0 */ + if( (pDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* first send the read status command (D7H) */ + pDesc->command[0] = DB_STATUS; + pDesc->command[1] = 0; + + pDesc->DataFlash_state = GET_STATUS; + pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ + pDesc->tx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_size = 2 ; + pDesc->tx_cmd_size = 2 ; + status = AT91F_SpiWrite (pDesc); + + pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); + + return status; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashWaitReady */ +/* \brief wait for dataflash ready (bit7 of the status register == 1) */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) +{ + pDataFlashDesc->DataFlash_state = IDLE; + + do { + AT91F_DataFlashGetStatus(pDataFlashDesc); + timeout--; + } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); + + if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) + return DATAFLASH_ERROR; + + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashContinuousRead */ +/* Object : Continuous stream Read */ +/* Input Parameters : DataFlash Service */ +/* : = dataflash address */ +/* : <*dataBuffer> = data buffer pointer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead ) +{ + AT91S_DataFlashStatus status; + /* Test the size to read in the device */ + if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; + + status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); + /* Send the command to the dataflash */ + return(status); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashPagePgmBuf */ +/* Object : Main memory page program through buffer 1 or buffer 2 */ +/* Input Parameters : DataFlash Service */ +/* : <*src> = Source buffer */ +/* : = dataflash destination address */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int SizeToWrite) +{ + int cmdsize; + pDataFlash->pDataFlashDesc->tx_data_pt = src ; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; + pDataFlash->pDataFlashDesc->rx_data_pt = src; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; + + cmdsize = 4; + /* Send the command to the dataflash */ + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_MainMemoryToBufferTransfert */ +/* Object : Read a page in the SRAM Buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); +} + + +/*----------------------------------------------------------------------------- */ +/* Function Name : AT91F_DataFlashWriteBuffer */ +/* Object : Write data to the internal sram buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : = command to write buffer1 or buffer2 */ +/* : <*dataBuffer> = data buffer to write */ +/* : = address in the internal buffer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite ) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) + return DATAFLASH_BAD_COMMAND; + + /* buffer address must be lower than page size */ + if (bufferAddress > pDataFlash->pDevice->pages_size) + return DATAFLASH_BAD_ADDRESS; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* Send first Write Command */ + pDataFlash->pDataFlashDesc->command[0] = BufferCommand; + pDataFlash->pDataFlashDesc->command[1] = 0; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[2] = 0; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + cmdsize = 5; + } else { + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + cmdsize = 4; + } + + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; + + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PageErase */ +/* Object : Erase a page */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_BlockErase */ +/* Object : Erase a Block */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_BlockErase( + AT91PS_DataFlash pDataFlash, + unsigned int block) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_WriteBufferToMain */ +/* Object : Write buffer to the main memory */ +/* Input Parameters : DataFlash Service */ +/* : = command to send to buffer1 or buffer2 */ +/* : = main memory address */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_WriteBufferToMain ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest ) +{ + int cmdsize; + /* Test if the buffer command is correct */ + if ((BufferCommand != DB_BUF1_PAGE_PGM) && + (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && + (BufferCommand != DB_BUF2_PAGE_PGM) && + (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + /* Send the command to the dataflash */ + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PartialPageWrite */ +/* Object : Erase partielly a page */ +/* Input Parameters : = page number */ +/* : = adr to begin the fading */ +/* : = Number of bytes to erase */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PartialPageWrite ( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size) +{ + unsigned int page; + unsigned int AdrInPage; + + page = dest / (pDataFlash->pDevice->pages_size); + AdrInPage = dest % (pDataFlash->pDevice->pages_size); + + /* Read the contents of the page in the Sram Buffer */ + AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + /*Update the SRAM buffer */ + AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Erase page if a 128 Mbits device */ + if (pDataFlash->pDevice->pages_number >= 16384) { + AT91F_PageErase(pDataFlash, page); + /* Rewrite the modified Sram Buffer in the main memory */ + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + } + + /* Rewrite the modified Sram Buffer in the main memory */ + return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashWrite */ +/* Object : */ +/* Input Parameters : <*src> = Source buffer */ +/* : = dataflash adress */ +/* : = data buffer size */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWrite( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ) +{ + unsigned int length; + unsigned int page; + unsigned int status; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + /* If destination does not fit a page start address */ + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { + length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); + + if (size < length) + length = size; + + if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= length; + dest += length; + src += length; + } + + while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { + /* program dataflash page */ + page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); + + status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + status = AT91F_PageErase(pDataFlash, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + if (!status) + return DATAFLASH_ERROR; + + status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); + if(!status) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= pDataFlash->pDevice->pages_size ; + dest += pDataFlash->pDevice->pages_size ; + src += pDataFlash->pDevice->pages_size ; + } + + /* If still some bytes to read */ + if ( size > 0 ) { + /* program dataflash page */ + if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + } + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashRead */ +/* Object : Read a block in dataflash */ +/* Input Parameters : */ +/* Return value : */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataFlashRead( + AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, + char *buffer) +{ + unsigned long SizeToRead; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + while (size) { + SizeToRead = (size < 0x8000)? size:0x8000; + + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) + return -1; + + size -= SizeToRead; + addr += SizeToRead; + buffer += SizeToRead; + } + + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataflashProbe */ +/* Object : */ +/* Input Parameters : */ +/* Return value : Dataflash status register */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) +{ + AT91F_SpiEnable(cs); + AT91F_DataFlashGetStatus(pDesc); + return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); +} + +#endif diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c new file mode 100644 index 0000000..14168e6 --- /dev/null +++ b/board/cmc_pu2/cmc_pu2.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn + * (2004) garyj@denx.de + * + * Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ +#define CMC_HP_BASIC 1 +#define CMC_PU2 2 +#define CMC_BASIC 4 + +int hw_detect (void); + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + AT91PS_PIO piob = AT91C_BASE_PIOB; + AT91PS_PIO pioc = AT91C_BASE_PIOC; + + /* Enable Ctrlc */ + console_init_f (); + + /* Correct IRDA resistor problem */ + /* Set PA23_TXD in Output */ + /* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */ + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* PIOB and PIOC clock enabling */ + *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; + *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; + + /* + * configure PC0-PC3 as input without pull ups, so RS485 driver enable + * (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated. + */ + pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 | + AT91C_PIO_PC2 | AT91C_PIO_PC3; + pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 | + AT91C_PIO_PC2 | AT91C_PIO_PC3; + pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 | + AT91C_PIO_PC2 | AT91C_PIO_PC3; + + /* + * On CMC-PU2 board configure PB3-PB6 to input without pull ups to + * clear the duo LEDs (the external pull downs assure a proper + * signal). On CMC-BASIC and CMC-HP-BASIC set PB3-PB6 to output and + * drive it high, to configure current measurement on AINx. + */ + if (hw_detect() & CMC_PU2) { + piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | + AT91C_PIO_PB5 | AT91C_PIO_PB6; + } + else if ((hw_detect() & CMC_BASIC) || (hw_detect() & CMC_HP_BASIC)) { + piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | + AT91C_PIO_PB5 | AT91C_PIO_PB6; + piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 | + AT91C_PIO_PB5 | AT91C_PIO_PB6; + } + piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | + AT91C_PIO_PB5 | AT91C_PIO_PB6; + piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 | + AT91C_PIO_PB5 | AT91C_PIO_PB6; + + /* + * arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in + * the linuxarm kernel, yet. + */ + /* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */ + gd->bd->bi_arch_number = 251; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +int checkboard (void) +{ + if (hw_detect() & CMC_PU2) + puts ("Board: CMC-PU2 (Rittal GmbH)\n"); + else if (hw_detect() & CMC_BASIC) + puts ("Board: CMC-BASIC (Rittal GmbH)\n"); + else if (hw_detect() & CMC_HP_BASIC) + puts ("Board: CMC-HP-BASIC (Rittal GmbH)\n"); + else + puts ("Board: unknown\n"); + return 0; +} + +int hw_detect (void) +{ + AT91PS_PIO pio = AT91C_BASE_PIOB; + + /* PIOB clock enabling */ + *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; + + /* configure PB12 as input without pull up */ + pio->PIO_ODR = AT91C_PIO_PB12; + pio->PIO_PPUDR = AT91C_PIO_PB12; + pio->PIO_PER = AT91C_PIO_PB12; + + /* configure PB13 as input without pull up */ + pio->PIO_ODR = AT91C_PIO_PB13; + pio->PIO_PPUDR = AT91C_PIO_PB13; + pio->PIO_PER = AT91C_PIO_PB13; + + /* read board identification pin */ + if (pio->PIO_PDSR & AT91C_PIO_PB12) + return ((pio->PIO_PDSR & AT91C_PIO_PB13) + ? CMC_PU2 : 0); + else + return ((pio->PIO_PDSR & AT91C_PIO_PB13) + ? CMC_HP_BASIC : CMC_BASIC); +} + +#ifdef CONFIG_DRIVER_ETHER +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * at91rm9200_GetPhyInterface + * Description: + * Initialise the interface functions to the PHY + * Arguments: + * None + * Return value: + * None + */ +void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) +{ + p_phyops->Init = dm9161_InitPhy; + p_phyops->IsPhyConnected = dm9161_IsPhyConnected; + p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; + p_phyops->AutoNegotiate = dm9161_AutoNegotiate; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/cmc_pu2/config.mk b/board/cmc_pu2/config.mk new file mode 100644 index 0000000..7116eea --- /dev/null +++ b/board/cmc_pu2/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x20F00000 +## For testing: load at 0x20100000 and "go" at 0x201000A4 +#TEXT_BASE = 0x20100000 diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c new file mode 100644 index 0000000..9983c7b --- /dev/null +++ b/board/cmc_pu2/flash.c @@ -0,0 +1,468 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn + * garyj@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifndef CFG_ENV_ADDR +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02AA + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_short *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_amd(flash_info_t *info, vu_short *dest, ushort data); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + ulong flashbase = CFG_FLASH_BASE; + + /* Init: no FLASHes known */ + memset(&flash_info[0], 0, sizeof(flash_info_t)); + + flash_info[0].size = flash_get_size((vu_short *)flashbase, &flash_info[0]); + + size = flash_info[0].size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + vu_short *base = (vu_short *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = 0x00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = 0x00F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + info = NULL; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_S29GL064M: + printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (vu_short *addr, flash_info_t *info) +{ + int i; + ushort value; + ulong base = (ulong)addr; + + /* Write auto select command sequence */ + addr[FLASH_CYCLE1] = 0x00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = 0x0055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = 0x0090; /* selects Intel or AMD */ + + /* read Manufacturer ID */ + udelay(100); + value = addr[0]; + debug ("Manufacturer ID: %04X\n", value); + + switch (value) { + + case (AMD_MANUFACT & 0xFFFF): + debug ("Manufacturer: AMD (Spansion)\n"); + info->flash_id = FLASH_MAN_AMD; + break; + + case (INTEL_MANUFACT & 0xFFFF): + debug ("Manufacturer: Intel (not supported yet)\n"); + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + printf ("Unknown Manufacturer ID: %04X\n", value); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + goto out; + } + + value = addr[1]; + debug ("Device ID: %04X\n", value); + + switch (addr[1]) { + + case (AMD_ID_MIRROR & 0xFFFF): + debug ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n", + addr[14], addr[15]); + + switch(addr[14]) { + case (AMD_ID_GL064M_2 & 0xFFFF): + if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) { + printf ("Chip: S29GLxxxM -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + } else { + debug ("Chip: S29GL064M-R6\n"); + info->flash_id += FLASH_S29GL064M; + info->sector_count = 128; + info->size = 0x00800000; + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x10000; + } + } + break; /* => 16 MB */ + default: + printf ("Chip: *** unknown ***\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + break; + + default: + printf ("Unknown Device ID: %04X\n", value); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + +out: + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_short *addr = (vu_short *)(info->start[0]); + int flag, prot, sect, ssect, l_sect; + ulong now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* + * Start erase on unprotected sectors. + * Since the flash can erase multiple sectors with one command + * we take advantage of that by doing the erase in chunks of + * 3 sectors. + */ + for (sect = s_first; sect <= s_last; ) { + l_sect = -1; + + addr[FLASH_CYCLE1] = 0x00AA; + addr[FLASH_CYCLE2] = 0x0055; + addr[FLASH_CYCLE1] = 0x0080; + addr[FLASH_CYCLE1] = 0x00AA; + addr[FLASH_CYCLE2] = 0x0055; + + /* do the erase in chunks of at most 3 sectors */ + for (ssect = 0; ssect < 3; ssect++) { + if ((sect + ssect) > s_last) + break; + if (info->protect[sect + ssect] == 0) { /* not protected */ + addr = (vu_short *)(info->start[sect + ssect]); + addr[0] = 0x0030; + l_sect = sect + ssect; + } + } + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + reset_timer_masked (); + last = 0; + addr = (vu_short *)(info->start[l_sect]); + while ((addr[0] & 0x0080) != 0x0080) { + if ((now = get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + addr = (vu_short *)info->start[0]; + addr[0] = 0x00F0; /* reset bank */ + sect += ssect; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + +DONE: + /* reset to read mode */ + addr = (vu_short *)info->start[0]; + addr[0] = 0x00F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + }; + + if ((int) src & 1) { + printf ("unaligned source not supported\n"); + return ERR_ALIGN; + }; + + wp = addr; + + while (cnt >= 2) { + data = *((vu_short *)src); + if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) { +printf ("write_buff 1: write_word_amd() rc=%d\n", rc); + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return (ERR_OK); + } + + if (cnt == 1) { + data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << 8); + if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) { +printf ("write_buff 1: write_word_amd() rc=%d\n", rc); + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data) +{ + int flag; + vu_short *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + base = (vu_short *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = 0x00AA; /* unlock */ + base[FLASH_CYCLE2] = 0x0055; /* unlock */ + base[FLASH_CYCLE1] = 0x00A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + reset_timer_masked (); + + /* data polling for D7 */ + while ((*dest & 0x0080) != (data & 0x0080)) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *dest = 0x00F0; /* reset bank */ + return (1); + } + } + return (0); +} diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c new file mode 100644 index 0000000..94aa30d --- /dev/null +++ b/board/cmc_pu2/load_sernum_ethaddr.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include + +#define I2C_CHIP 0x50 /* I2C bus address of onboard EEPROM */ +#define I2C_ALEN 1 /* length of EEPROM addresses in bytes */ +#define I2C_OFFSET 0x0 /* start address of manufacturere data block + * in EEPROM */ + +/* 64 Byte manufacturer data block in EEPROM */ +struct manufacturer_data { + unsigned int serial_number; /* serial number (0...999999) */ + unsigned short hardware; /* hardware version (e.g. V1.02) */ + unsigned short manuf_date; /* manufacture date (e.g. 25/02) */ + unsigned char name[20]; /* device name (in CHIP.INI) */ + unsigned char macadr[6]; /* MAC address */ + signed char a_kal[4]; /* calibration value for U */ + signed char i_kal[4]; /* calibration value for I */ + unsigned char reserve[18]; /* reserved */ + unsigned short save_nr; /* save count */ + unsigned short chksum; /* checksum */ +}; + + +int i2c_read (unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); + +/*----------------------------------------------------------------------- + * Process manufacturer data block in EEPROM: + * + * If we boot on a system fresh from factory, check if the manufacturer data + * in the EEPROM is valid and save some information it contains. + * + * CMC manufacturer data is defined as follows: + * + * - located in the onboard EEPROM + * - starts at offset 0x0 + * - size 0x00000040 + * + * Internal structure: see struct definition + */ + +void load_sernum_ethaddr (void) +{ + struct manufacturer_data data; + unsigned char serial [9]; + unsigned char ethaddr[18]; + unsigned short chksum; + unsigned char *p; + unsigned short i, is, id; + +#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C) +#error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C) +#endif + if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data, + sizeof(data)) != 0) { + puts ("Error reading manufacturer data from EEPROM\n"); + return; + } + + /* check if manufacturer data block is valid */ + p = (unsigned char *)&data; + chksum = 0; + for (i = 0; i < (sizeof(data) - sizeof(data.chksum)); i++) + chksum += *p++; + + debug ("checksum of manufacturer data block: %#.4x\n", chksum); + + if (chksum != data.chksum) { + puts ("Error: manufacturer data block has invalid checksum\n"); + return; + } + + /* copy MAC address */ + is = 0; + id = 0; + for (i = 0; i < 6; i++) { + sprintf (ðaddr[id], "%02x", data.macadr[is++]); + id += 2; + if (is < 6) + ethaddr[id++] = ':'; + } + ethaddr[id] = '\0'; /* just to be sure */ + + /* copy serial number */ + sprintf (serial, "%d", data.serial_number); + + /* set serial# and ethaddr if not yet defined */ + if (getenv("serial#") == NULL) { + setenv ("serial#", serial); + } + + if (getenv("ethaddr") == NULL) { + setenv ("ethaddr", ethaddr); + } +} diff --git a/board/cmc_pu2/u-boot.lds b/board/cmc_pu2/u-boot.lds new file mode 100644 index 0000000..f4fbf96 --- /dev/null +++ b/board/cmc_pu2/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/cmi/Makefile b/board/cmi/Makefile new file mode 100644 index 0000000..2324d87 --- /dev/null +++ b/board/cmi/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := flash.o cmi.o +SOBJS := + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c new file mode 100644 index 0000000..cbf34f7 --- /dev/null +++ b/board/cmi/cmi.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2003 + * Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * File: cmi.c + * + * Discription: For generic board specific functions + * + */ + + +#include +#include + +#define SRAM_SIZE 1024000L /* 1M RAM available*/ + +#if defined(__APPLE__) +/* Leading underscore on symbols */ +# define SYM_CHAR "_" +#else /* No leading character on symbols */ +# define SYM_CHAR +#endif + +/* + * Macros to generate global absolutes. + */ +#define GEN_SYMNAME(str) SYM_CHAR #str +#define GEN_VALUE(str) #str +#define GEN_ABS(name, value) \ + asm (".globl " GEN_SYMNAME(name)); \ + asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) + +/* + * Check the board + */ +int checkboard(void) +{ + puts ("Board: ### No HW ID - assuming CMI board\n"); + return (0); +} + +/* + * Get RAM size. + */ +long int initdram(int board_type) +{ + return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */ +} + +/* + * Absolute environment address for linker file. + */ +GEN_ABS(env_start, CFG_ENV_OFFSET + CFG_FLASH_BASE); diff --git a/board/cmi/config.mk b/board/cmi/config.mk new file mode 100644 index 0000000..564f638 --- /dev/null +++ b/board/cmi/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003 +# Martin Winistoerfer, martinwinistoerfer@gmx.ch. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EPQ Board Configuration +# + +# Boot from flash at location 0x00000000 +TEXT_BASE = 0x02000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cmi/flash.c b/board/cmi/flash.c new file mode 100644 index 0000000..f7c25f4 --- /dev/null +++ b/board/cmi/flash.c @@ -0,0 +1,517 @@ +/* + * (C) Copyright 2003 + * Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * File: flash.c + * + * Discription: This Driver is for 28F320J3A, 28F640J3A and + * 28F128J3A Intel flashs working in 16 Bit mode. + * They are single bank flashs. + * + * Most of this code is taken from existing u-boot + * source code. + */ + + +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#define FLASH_ID_MASK 0xFFFF +#define FLASH_BLOCK_SIZE 0x00010000 +#define FLASH_CMD_READ_ID 0x0090 +#define FLASH_CMD_RESET 0x00ff +#define FLASH_CMD_BLOCK_ERASE 0x0020 +#define FLASH_CMD_ERASE_CONFIRM 0x00D0 +#define FLASH_CMD_CLEAR_STATUS 0x0050 +#define FLASH_CMD_SUSPEND_ERASE 0x00B0 +#define FLASH_CMD_WRITE 0x0040 +#define FLASH_CMD_PROTECT 0x0060 +#define FLASH_CMD_PROTECT_SET 0x0001 +#define FLASH_CMD_PROTECT_CLEAR 0x00D0 +#define FLASH_STATUS_DONE 0x0080 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/* + * Local function prototypes + */ +static ulong flash_get_size (vu_short *addr, flash_info_t *info); +static int write_short (flash_info_t *info, ulong dest, ushort data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/* + * Initialize flash + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + + return size_b0; +} + +/* + * Compute start adress of each sector (block) + */ + +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + i * FLASH_BLOCK_SIZE; + } + return; + + default: + printf ("Don't know sector offsets for flash type 0x%lx\n", + info->flash_id); + return; + } +} + +/* + * Print flash information + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("Fujitsu "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_MT: printf ("MT "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: printf ("28F320J3A (32Mbit) 16-Bit\n"); + break; + case FLASH_28F640J3A: printf ("28F640J3A (64Mbit) 16-Bit\n"); + break; + case FLASH_28F128J3A: printf ("28F128J3A (128Mbit) 16-Bit\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >= (1 << 20)) { + i = 20; + } else { + i = 10; + } + printf (" Size: %ld %cB in %d Sectors\n", + info->size >> i, + (i == 20) ? 'M' : 'k', + info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * Get size of flash in bytes. + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_short *addr, flash_info_t *info) +{ + vu_short value; + + /* Read Manufacturer ID */ + addr[0] = FLASH_CMD_READ_ID; + value = addr[0]; + + switch (value) { + case (AMD_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_FUJ; + break; + case (SST_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_SST; + break; + case (STM_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_STM; + break; + case (INTEL_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = FLASH_CMD_RESET; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case (INTEL_ID_28F320J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 32 MBit */ + + case (INTEL_ID_28F640J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 64 MBit */ + + case (INTEL_ID_28F128J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 128 MBit */ + + default: + info->flash_id = FLASH_UNKNOWN; + addr[0] = FLASH_CMD_RESET; /* restore read mode */ + return (0); /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = FLASH_CMD_RESET; /* restore read mode */ + + return (info->size); +} + + +/* + * Erase unprotected sectors + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *)(info->start[sect]); + unsigned long status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + +#ifdef DEBUG + printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]); +#endif + + *addr = FLASH_CMD_CLEAR_STATUS; + *addr = FLASH_CMD_BLOCK_ERASE; + *addr = FLASH_CMD_ERASE_CONFIRM; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Flash erase timeout at address %lx\n", info->start[sect]); + *addr = FLASH_CMD_SUSPEND_ERASE; + *addr = FLASH_CMD_RESET; + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + *addr = FLASH_CMD_RESET; + } + } + printf (" done\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + ushort data; + int i, rc; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start byte + */ + + if (addr - wp) { + data = 0; + data = (data << 8) | *src++; + --cnt; + if ((rc = write_short(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + + while (cnt >= 2) { + data = 0; + for (i=0; i<2; ++i) { + data = (data << 8) | *src++; + } + + if ((rc = write_short(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + + data = 0; + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<2; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_short(info, wp, data)); + +} + +/* + * Write 16 bit (short) to flash + */ + +static int write_short (flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_short *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if (!(info->flash_id & FLASH_VENDMASK)) { + return 4; + } + *addr = FLASH_CMD_ERASE_CONFIRM; + *addr = FLASH_CMD_WRITE; + + *((vu_short *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + /* data polling for D7 */ + start = get_timer (0); + + /* wait for error or finish */ + while(!(addr[0] & FLASH_STATUS_DONE)){ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + addr[0] = FLASH_CMD_RESET; + return (1); + } + } + + *addr = FLASH_CMD_RESET; + return (0); +} + +/* + * Protects a flash sector + */ + +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + vu_short *addr = (vu_short*)(info->start[sector]); + ulong start; + + *addr = FLASH_CMD_CLEAR_STATUS; + *addr = FLASH_CMD_PROTECT; + + if(prot) { + *addr = FLASH_CMD_PROTECT_SET; + } else { + *addr = FLASH_CMD_PROTECT_CLEAR; + } + + /* wait for error or finish */ + start = get_timer (0); + while(!(addr[0] & FLASH_STATUS_DONE)){ + if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + printf("Flash protect timeout at address %lx\n", info->start[sector]); + addr[0] = FLASH_CMD_RESET; + return (1); + } + } + /* Set software protect flag */ + info->protect[sector] = prot; + *addr = FLASH_CMD_RESET; + return (0); +} diff --git a/board/cmi/u-boot.lds b/board/cmi/u-boot.lds new file mode 100644 index 0000000..5b03fef --- /dev/null +++ b/board/cmi/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de + * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +/* . = env_start; + .ppcenv : + { + common/environment.o (.ppcenv) + } +*/ +} diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile new file mode 100644 index 0000000..e5d8446 --- /dev/null +++ b/board/cobra5272/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cobra5272/bdm/cobra5272_uboot.gdb b/board/cobra5272/bdm/cobra5272_uboot.gdb new file mode 100644 index 0000000..61e778e --- /dev/null +++ b/board/cobra5272/bdm/cobra5272_uboot.gdb @@ -0,0 +1,169 @@ +# +# GDB Init script for the Coldfire 5272 processor. +# +# The main purpose of this script is to configure the +# DRAM controller so code can be loaded. +# +# This file was changed to suite the senTec COBRA5272 board. +# + +define addresses + +set $mbar = 0x10000001 +set $scr = $mbar - 1 + 0x004 +set $spr = $mbar - 1 + 0x006 +set $pmr = $mbar - 1 + 0x008 +set $apmr = $mbar - 1 + 0x00e +set $dir = $mbar - 1 + 0x010 +set $icr1 = $mbar - 1 + 0x020 +set $icr2 = $mbar - 1 + 0x024 +set $icr3 = $mbar - 1 + 0x028 +set $icr4 = $mbar - 1 + 0x02c +set $isr = $mbar - 1 + 0x030 +set $pitr = $mbar - 1 + 0x034 +set $piwr = $mbar - 1 + 0x038 +set $pivr = $mbar - 1 + 0x03f +set $csbr0 = $mbar - 1 + 0x040 +set $csor0 = $mbar - 1 + 0x044 +set $csbr1 = $mbar - 1 + 0x048 +set $csor1 = $mbar - 1 + 0x04c +set $csbr2 = $mbar - 1 + 0x050 +set $csor2 = $mbar - 1 + 0x054 +set $csbr3 = $mbar - 1 + 0x058 +set $csor3 = $mbar - 1 + 0x05c +set $csbr4 = $mbar - 1 + 0x060 +set $csor4 = $mbar - 1 + 0x064 +set $csbr5 = $mbar - 1 + 0x068 +set $csor5 = $mbar - 1 + 0x06c +set $csbr6 = $mbar - 1 + 0x070 +set $csor6 = $mbar - 1 + 0x074 +set $csbr7 = $mbar - 1 + 0x078 +set $csor7 = $mbar - 1 + 0x07c +set $pacnt = $mbar - 1 + 0x080 +set $paddr = $mbar - 1 + 0x084 +set $padat = $mbar - 1 + 0x086 +set $pbcnt = $mbar - 1 + 0x088 +set $pbddr = $mbar - 1 + 0x08c +set $pbdat = $mbar - 1 + 0x08e +set $pcddr = $mbar - 1 + 0x094 +set $pcdat = $mbar - 1 + 0x096 +set $pdcnt = $mbar - 1 + 0x098 +set $sdcr = $mbar - 1 + 0x180 +set $sdtr = $mbar - 1 + 0x184 +set $wrrr = $mbar - 1 + 0x280 +set $wirr = $mbar - 1 + 0x283 +set $wcr = $mbar - 1 + 0x288 +set $wer = $mbar - 1 + 0x28c + +end + + +# +# Setup system configuration +# +define setup-sys +set *((unsigned short *) $scr) = 0x0003 +set *((unsigned short *) $spr) = 0xffff +set *((unsigned char *) $pivr) = 0x4f +end + + +# +# Setup Chip Selects (as per Motorola M5272C3 board) +# +define setup-cs + +# CS0 -- FLASH +set *((unsigned long *) $csbr0) = 0xffe00201 +set *((unsigned long *) $csor0) = 0xffe00014 + +# CS1 -- external bus test +set *((unsigned long *) $csbr1) = 0x0 +set *((unsigned long *) $csor1) = 0x0 + +# CS2 -- Optional FSRAM +set *((unsigned long *) $csbr2) = 0x30000001 +set *((unsigned long *) $csor2) = 0xfff80000 + +# CS3 -- not used +set *((unsigned long *) $csbr3) = 0x0 +set *((unsigned long *) $csor3) = 0x0 + +# CS4 -- not used +set *((unsigned long *) $csbr4) = 0x0 +set *((unsigned long *) $csor4) = 0x0 + +# CS5 -- PLI socket0 +set *((unsigned long *) $csbr5) = 0x0 +set *((unsigned long *) $csor5) = 0x0 + +# CS6 -- PLI socket1 +set *((unsigned long *) $csbr6) = 0x0 +set *((unsigned long *) $csor6) = 0x0 + +# CS7 -- SDRAM +set *((unsigned long *) $csbr7) = 0x00000701 +set *((unsigned long *) $csor7) = 0xff00007c + +end + + +# +# Setup the DRAM controller. +# + +define setup-dram +set *((unsigned long *) $sdtr) = 0x0000f539 +set *((unsigned long *) $sdcr) = 0x00004211 + +# Dummy write to start SDRAM +set *((unsigned long *) 0) = 0 +end + + +# +# Setup for GPIO pins +# +define setup-ppio + +# PORT A -- the LED's +set *((unsigned long *) $pacnt) = 0x00000000 +# lower 8 bits for output: +set *((unsigned short *) $paddr) = 0xff +# LED's off: +set *((unsigned short *) $padat) = 0xff + +# PORT B +set *((unsigned long *) $pbcnt) = 0x55554155 +set *((unsigned short *) $pbddr) = 0x0000 +set *((unsigned short *) $pbdat) = 0x17ea + +# PORT C +#set *((unsigned short *) $pcddr) = 0x0000 +#set *((unsigned short *) $pcdat) = 0x1898 + +# PORT D +set *((unsigned long *) $pdcnt) = 0x00000000 + +end + + +# +# Added for uClinux-coldfire target... +# +target bdm /dev/bdm + +addresses +setup-sys +setup-cs +setup-dram +setup-ppio +set print pretty +set print asm-demangle +display/i $pc + + +# +load u-boot +set $pc=0x20000 +c diff --git a/board/cobra5272/bdm/gdbinit.reset b/board/cobra5272/bdm/gdbinit.reset new file mode 100644 index 0000000..5f1e482 --- /dev/null +++ b/board/cobra5272/bdm/gdbinit.reset @@ -0,0 +1,2 @@ +target bdm /dev/bdmcf0 +q diff --git a/board/cobra5272/bdm/load-cobra_uboot b/board/cobra5272/bdm/load-cobra_uboot new file mode 100644 index 0000000..933c7e7 --- /dev/null +++ b/board/cobra5272/bdm/load-cobra_uboot @@ -0,0 +1,2 @@ +m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot + diff --git a/board/cobra5272/bdm/reset b/board/cobra5272/bdm/reset new file mode 100644 index 0000000..8bef00b --- /dev/null +++ b/board/cobra5272/bdm/reset @@ -0,0 +1,2 @@ +m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset + diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c new file mode 100644 index 0000000..26adb4a --- /dev/null +++ b/board/cobra5272/cobra5272.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + + +int checkboard (void) +{ + puts ("Board: "); + puts ("senTec COBRA5272 Board\n"); + return 0; +}; + +long int initdram (int board_type) +{ + volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR); + + sdp->sdram_sdtr = 0xf539; + sdp->sdram_sdcr = 0x4211; + + /* Dummy write to start SDRAM */ + *((volatile unsigned long *) 0) = 0; + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/cobra5272/config.mk b/board/cobra5272/config.mk new file mode 100644 index 0000000..ccb2cf7 --- /dev/null +++ b/board/cobra5272/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c new file mode 100644 index 0000000..6f5874a --- /dev/null +++ b/board/cobra5272/flash.c @@ -0,0 +1,378 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x200000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_PL160CB & FLASH_TYPEMASK): + printf ("AM29PL160CB (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: +} + + +unsigned long flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_PL160CB & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured to many flash banks!\n"); + + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j == 0) { + /* 1st is 16 KiB */ + flash_info[i].start[j] = flashbase; + } + if ((j >= 1) && (j <= 2)) { + /* 2nd and 3rd are 8 KiB */ + flash_info[i].start[j] = + flashbase + 0x4000 + 0x2000 * (j - 1); + } + if (j == 3) { + /* 4th is 224 KiB */ + flash_info[i].start[j] = flashbase + 0x8000; + } + if ((j >= 4) && (j <= 10)) { + /* rest is 256 KiB */ + flash_info[i].start[j] = + flashbase + 0x40000 + 0x40000 * (j - + 4); + } + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + 0x3ffff, &flash_info[0]); + + return size; +} + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + printf ("\n"); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = + (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + udelay (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + + +volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + } + +#if 0 + if (cnt & 1) { + printf ("odd transfer sizes not supported\n"); + return ERR_ALIGN; + } +#endif + + wp = addr; + + if (addr & 1) { + data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) + src); + if ((rc = write_word (info, wp - 1, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src) << 8) | + *((volatile u8 *) (wp + 1)); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + return ERR_OK; +} diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds new file mode 100644 index 0000000..872f094 --- /dev/null +++ b/board/cobra5272/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + cpu/mcf52x2/start.o (.text) + cpu/mcf52x2/cpu_init.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cogent/Makefile b/board/cogent/Makefile new file mode 100644 index 0000000..4084c7e --- /dev/null +++ b/board/cogent/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o +SOBJS := + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cogent/README b/board/cogent/README new file mode 100644 index 0000000..e6eef66 --- /dev/null +++ b/board/cogent/README @@ -0,0 +1,118 @@ +Cogent Modular Architecture configuration +----------------------------------------- + +As the name suggests, the Cogent platform is a modular system where +you have a motherboard into which plugs a cpu module and one or more +i/o modules. This provides very nice flexibility, but makes the +configuration task somewhat harder. + +The possible Cogent motherboards are: + +Code Config Variable Description +---- --------------- ----------- + +CMA101 CONFIG_CMA101 32MB ram, 2 ser, 1 par, rtc, dipsw, + 2x16 lcd, eth(?) +CMA102 CONFIG_CMA102 32MB ram, 2 ser, 1 par, rtc, dipsw, + 2x16 lcd +CMA111 CONFIG_CMA111 32MB ram, 1MB flash, 4 ser, 1 par, + rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI, + 10/100TP eth +CMA120 CONFIG_CMA120 32MB ram, 1MB flash, 4 ser, 1 par, + rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI, + 10/100TP eth, 2xPCMCIA, video/lcd-panel +CMA150 CONFIG_CMA150 8MB ram, 1MB flash, 2 ser, 1 par, rtc, + ps/2 kbd/mse, 2x16 lcd + +The possible Cogent PowerPC CPU modules are: + +Code Config Variable Description +---- --------------- ----------- + +CMA278-603EV CONFIG_CMA278_603EV PPC603ev CPU, 66MHz clock, 512K EPROM, + JTAG/COP +CMA278-603ER CONFIG_CMA278_603ER PPC603er CPU, 66MHz clock, 512K EPROM, + JTAG/COP +CMA278-740 CONFIG_CMA278_740 PPC740 CPU, 66MHz clock, 512K EPROM, + JTAG/COP +CMA280-509 CONFIG_CMA280_509 MPC505/509 CPU, 50MHz clock, + 512K EPROM, BDM +CMA282 CONFIG_CMA282 MPC8260 CPU, 66MHz clock, 512K EPROM, + JTAG, 16M RAM, 1 x ser (SMC2), + 1 x 10baseT PHY (SCC4), 1 x 10/100 TP + PHY (FCC1), 2 x 48pin DIN (FCC2 + TDM1) +CMA285 CONFIG_CMA285 MPC801 CPU, 33MHz clock, 512K EPROM, + BDM +CMA286-21 CONFIG_CMA286_21 MPC821 CPU, 66MHz clock, 512K EPROM, + BDM, 16M RAM, 2 x ser (SMC1 + SMC2), + 1 x 10baseT PHY (SCC2) +CMA286-60-OLD CONFIG_CMA286_60_OLD MPC860 CPU, 33MHz clock, 128K EPROM, + BDM +CMA286-60 CONFIG_CMA286_60 MPC860 CPU, 66MHz clock, 512K EPROM, + BDM, 16M RAM, 2 x ser (SMC1 + SMC2), + 1 x 10baseT PHY (SCC2) +CMA286-60P CONFIG_CMA286_60P MPC860P CPU, 66MHz clock, 512K EPROM, + BDM, 16M RAM, 2 x ser (SMC1 + SMC2), + 1 x 10baseT PHY (SCC2) +CMA287-23 CONFIG_CMA287_23 MPC823 CPU, 33MHz clock, 512K EPROM, + BDM +CMA287-50 CONFIG_CMA287_50 MPC850 CPU, 33MHz clock, 512K EPROM, + BDM + +(there are a lot of other cpu modules with ARM, MIPS and M-CORE CPUs, +but we'll worry about those later). + +The possible Cogent CMA I/O Modules are: + +Code Config Variable Description +---- --------------- ----------- + +CMA302 CONFIG_CMA302 up to 16M flash, ps/2 keyboard/mouse +CMA352 CONFIG_CMA352 CMAbus <=> PCI + +Currently supported: + + Motherboards: CMA102 + CPU Modules: CMA286-60-OLD + I/O Modules: CMA302 I/O module + +To configure, perform the usual U-Boot configuration task of editing +"include/config_cogent_mpc8xx.h" and reviewing all the options and +settings in there. In particular, check the chip select values +installed into the memory controller's various option and base +registers - these are set by the defines CFG_CMA_CSn_{BASE,SIZE} and +CFG_{B,O}Rn_PRELIM. Also be careful of the clock settings installed +into the SCCR - via the define CFG_SCCR. Finally, decide whether you +want the serial console on motherboard serial port A or on one of the +8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly +(NONE means use Cogent motherboard serial port A). + +Then edit the file "cogent/config.mk". Firstly, set TEXT_BASE to be +the base address of the EPROM for the CPU module. This should be the +same as the value selected for CFG_MONITOR_BASE in +"include/config_cogent_*.h" (in fact, I have made this automatic via +the -DTEXT_BASE=... option in CPPFLAGS). + +Finally, set the values of the make variables $(CMA_MB) and $(CMA_IOMS). + +$(CMA_MB) is the name of the directory that contains support for your +motherboard. At this stage, only "cma10x" exists, which supports the +CMA101 and CMA102 motherboards - but only selected devices, namely +serial, lcd and dipsw. + +$(CMA_IOMS) is a list of zero or more directories that contain +support for the i/o modules you have installed. At this stage, only +"cma302" exists, which supports the CMA302 flash i/o module - but +only the flash part, not the ps/2 keyboard and mouse interfaces. + +There should be a make variable for each of the above directories, +which is the directory name with "_O" appended. This make variable is +a list of object files to compile from that directory and include in +the library. + + e.g. cma10x_O = serial.o ... + +That's it. Good Luck. + +Murray.Jensen@cmst.csiro.au +August 31, 2000. diff --git a/board/cogent/README.cma286 b/board/cogent/README.cma286 new file mode 100644 index 0000000..0345fea --- /dev/null +++ b/board/cogent/README.cma286 @@ -0,0 +1,69 @@ +CPU module revisions +-------------------- + +My cpu module has the model number "CMA286-60-990526-01". My motherboard +has the model number "CMA102-32M-990526-01". These are both fairly old, +and may not reflect current design. In particular, I can see from the +Cogent web site that the CMA286 has been significantly redesigned - it +now has on board RAM (4M), ethernet 10baseT PHY (on SCC2), 2 serial ports +(SMC1 and SMC2), and 48pin DIN for the FEC (if present i.e. MPC860T), and +also the EPROM is 512K. + +My CMA286-60 has none of this, and only 128K EPROM. In addition, the CPU +clock is listed as 66MHz, whereas mine is 33.333MHz. + +Clocks +------ + +Quote from my "CMA286 MPC860/821 User's Manual": + +"When setting up the Periodic Interrupt Timer (PIT), be aware that the +CMA286 places the MPC860/821 in PLL X1 Mode. This means that we feed +a 25MHz clock directly into the MPC860/821. This mode sets the divisor +for the PIT to be 512. In addition, the Time Base Register (TMB) +divisor is set to 16." + +I interpreted this information to mean that EXTCLK is 25MHz and that at +power on reset, MODCK1=1 and MODCK2=0, which selects EXTCLK as the +source for OSCCLK and PITRTCLK, sets RTDIV to 512 and sets MF (the +multiplication factor) to 1 (I assume this is what they mean by X1 +mode above). MF=1 means the cpus internal clock runs at the same +rate as EXTCLK i.e. 25MHz. + +Furthermore, since SCCR[TBS] (the Time Base Source selector bit in the +System Clock and Reset Control register) is set in the cpu initialisation +code, the TMBCLK source is forced to be GCLK2 and the TMBCLK prescale is +forced to be 16. This results in TMBCLK=1562500. + +One problem - since PITRTCLK source is EXTCLK (25Mhz) and RTDIV is 512, +PITRTCLK will be 48828.125 (huh?). Another quote from the MPC860 Users +Manual: + +"When used by the real-time clock (RTC), the PITRTCLK source is first +divided as determined by RTDIV, and then divided in the RTC circuits by +either 8192 or 9600. Therefore, in order for the RTC to count in +seconds, the clock source must satisfy: + + (EXTCLK or OSCM) / [(4 or 512) x (8192 or 9600)] = 1 + +The RTC will operate with other frequencies, but it will not count in +units of seconds." + +Therefore, the internal RTC of the MPC860 is not going to count in +seconds, so we must use the motherboard RTC (if we need a RTC). + +I presume this means that they do not provide a fixed oscillator for +OSCM. The code in get_gclk_freq() assumes PITRTCLK source is OSCM, +RTDIV is 4, and that OSCM/4 is 8192 (i.e. a ~32KHz oscillator). Since +the CMA286-60 doesn't have this (at least mine doesn't) we can't use +the code in get_gclk_freq(). + +Finally, it appears that the internal clock in my CMA286-60 is actually +33.333MHz. Which makes TMBCLK=2083312.5 (another huh?) and +PITRTCLK=65103.515625 (bloody hell!). + +If anyone finds anything wrong with the stuff above, I would appreciate +an email about it. + +Murray Jensen +21-Aug-00 diff --git a/board/cogent/config.mk b/board/cogent/config.mk new file mode 100644 index 0000000..ee77939 --- /dev/null +++ b/board/cogent/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Cogent Modular Architecture +# + +# Boot EPROM location +TEXT_BASE = 0xfff00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cogent/dipsw.c b/board/cogent/dipsw.c new file mode 100644 index 0000000..d2027c9 --- /dev/null +++ b/board/cogent/dipsw.c @@ -0,0 +1,50 @@ +#include +#include + +unsigned char +dipsw_raw(void) +{ + return cma_mb_reg_read(&((cma_mb_dipsw *)CMA_MB_DIPSW_BASE)->dip_val); +} + +unsigned char +dipsw_cooked(void) +{ + unsigned char val1, val2, mask1, mask2; + + val1 = dipsw_raw(); + + /* + * we want to mirror the bits because the low bit is switch 1 and high + * bit is switch 8 and also invert them because 1=off and 0=on, according + * to manual. + * + * this makes the value more intuitive i.e. + * - left most, or high, or top, bit is left most switch (1); + * - right most, or low, or bottom, bit is right most switch (8) + * - a set bit means "on" and a clear bit means "off" + */ + + val2 = 0; + for (mask1 = 1 << 7, mask2 = 1; mask1 > 0; mask1 >>= 1, mask2 <<= 1) + if ((val1 & mask1) == 0) + val2 |= mask2; + + return (val2); +} + +void +dipsw_init(void) +{ + unsigned char val, mask; + + val = dipsw_cooked(); + + printf("|"); + for (mask = 1 << 7; mask > 0; mask >>= 1) + if (val & mask) + printf("on |"); + else + printf("off|"); + printf("\n"); +} diff --git a/board/cogent/dipsw.h b/board/cogent/dipsw.h new file mode 100644 index 0000000..4f52fd4 --- /dev/null +++ b/board/cogent/dipsw.h @@ -0,0 +1,3 @@ +extern unsigned char dipsw_raw(void); +extern unsigned char dipsw_cooked(void); +extern void dipsw_init(void); diff --git a/board/cogent/flash.c b/board/cogent/flash.c new file mode 100644 index 0000000..969520d --- /dev/null +++ b/board/cogent/flash.c @@ -0,0 +1,648 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + + +#if defined(CONFIG_CMA302) + +/* + * probe for the existence of flash at address "addr" + * 0 = yes, 1 = bad Manufacturer's Id, 2 = bad Device Id + */ +static int +c302f_probe_word(c302f_addr_t addr) +{ + /* reset the flash */ + *addr = C302F_BNK_CMD_RST; + + /* check the manufacturer id */ + *addr = C302F_BNK_CMD_RD_ID; + if (*C302F_BNK_ADDR_MAN(addr) != C302F_BNK_RD_ID_MAN) + return 1; + + /* check the device id */ + *addr = C302F_BNK_CMD_RD_ID; + if (*C302F_BNK_ADDR_DEV(addr) != C302F_BNK_RD_ID_DEV) + return 2; + +#ifdef FLASH_DEBUG + { + int i; + + printf("\nMaster Lock Config = 0x%08lx\n", + *C302F_BNK_ADDR_CFGM(addr)); + for (i = 0; i < C302F_BNK_NBLOCKS; i++) + printf("Block %2d Lock Config = 0x%08lx\n", + i, *C302F_BNK_ADDR_CFG(i, addr)); + } +#endif + + /* reset the flash again */ + *addr = C302F_BNK_CMD_RST; + + return 0; +} + +/* + * probe for Cogent CMA302 flash module at address "base" and store + * info for any found into flash_info entry "fip". Must find at least + * one bank. + */ +static void +c302f_probe(flash_info_t *fip, c302f_addr_t base) +{ + c302f_addr_t addr, eaddr; + int nbanks; + + fip->size = 0L; + fip->sector_count = 0; + + addr = base; + eaddr = C302F_BNK_ADDR_BASE(addr, C302F_MAX_BANKS); + nbanks = 0; + + while (addr < eaddr) { + c302f_addr_t addrw, eaddrw, addrb; + int i, osc, nsc; + + addrw = addr; + eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw); + + while (addrw < eaddrw) + if (c302f_probe_word(addrw++) != 0) + goto out; + + /* bank exists - append info for this bank to *fip */ + fip->flash_id = FLASH_MAN_INTEL|FLASH_28F008S5; + fip->size += C302F_BNK_SIZE; + osc = fip->sector_count; + fip->sector_count += C302F_BNK_NBLOCKS; + if ((nsc = fip->sector_count) >= CFG_MAX_FLASH_SECT) + panic("Too many sectors in flash at address 0x%08lx\n", + (unsigned long)base); + + addrb = addr; + for (i = osc; i < nsc; i++) { + fip->start[i] = (ulong)addrb; + fip->protect[i] = 0; + addrb = C302F_BNK_ADDR_NEXT_BLK(addrb); + } + + addr = C302F_BNK_ADDR_NEXT_BNK(addr); + nbanks++; + } + +out: + if (nbanks == 0) + panic("ERROR: no flash found at address 0x%08lx\n", + (unsigned long)base); +} + +static void +c302f_reset(flash_info_t *info, int sect) +{ + c302f_addr_t addrw, eaddrw; + + addrw = (c302f_addr_t)info->start[sect]; + eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw); + + while (addrw < eaddrw) { +#ifdef FLASH_DEBUG + printf(" writing reset cmd to addr 0x%08lx\n", + (unsigned long)addrw); +#endif + *addrw = C302F_BNK_CMD_RST; + addrw++; + } +} + +static void +c302f_erase_init(flash_info_t *info, int sect) +{ + c302f_addr_t addrw, saddrw, eaddrw; + int flag; + +#ifdef FLASH_DEBUG + printf("0x%08lx C302F_BNK_CMD_PROG\n", C302F_BNK_CMD_PROG); + printf("0x%08lx C302F_BNK_CMD_ERASE1\n", C302F_BNK_CMD_ERASE1); + printf("0x%08lx C302F_BNK_CMD_ERASE2\n", C302F_BNK_CMD_ERASE2); + printf("0x%08lx C302F_BNK_CMD_CLR_STAT\n", C302F_BNK_CMD_CLR_STAT); + printf("0x%08lx C302F_BNK_CMD_RST\n", C302F_BNK_CMD_RST); + printf("0x%08lx C302F_BNK_STAT_RDY\n", C302F_BNK_STAT_RDY); + printf("0x%08lx C302F_BNK_STAT_ERR\n", C302F_BNK_STAT_ERR); +#endif + + saddrw = (c302f_addr_t)info->start[sect]; + eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw); + +#ifdef FLASH_DEBUG + printf("erasing sector %d, start addr = 0x%08lx " + "(bank next word addr = 0x%08lx)\n", sect, + (unsigned long)saddrw, (unsigned long)eaddrw); +#endif + + /* Disable intrs which might cause a timeout here */ + flag = disable_interrupts(); + + for (addrw = saddrw; addrw < eaddrw; addrw++) { +#ifdef FLASH_DEBUG + printf(" writing erase cmd to addr 0x%08lx\n", + (unsigned long)addrw); +#endif + *addrw = C302F_BNK_CMD_ERASE1; + *addrw = C302F_BNK_CMD_ERASE2; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); +} + +static int +c302f_erase_poll(flash_info_t *info, int sect) +{ + c302f_addr_t addrw, saddrw, eaddrw; + int sectdone, haderr; + + saddrw = (c302f_addr_t)info->start[sect]; + eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw); + + sectdone = 1; + haderr = 0; + + for (addrw = saddrw; addrw < eaddrw; addrw++) { + c302f_word_t stat = *addrw; + +#ifdef FLASH_DEBUG + printf(" checking status at addr " + "0x%08lx [0x%08lx]\n", + (unsigned long)addrw, stat); +#endif + if ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY) + sectdone = 0; + else if ((stat & C302F_BNK_STAT_ERR) != 0) { + printf(" failed on sector %d " + "(stat = 0x%08lx) at " + "address 0x%08lx\n", + sect, stat, + (unsigned long)addrw); + *addrw = C302F_BNK_CMD_CLR_STAT; + haderr = 1; + } + } + + if (haderr) + return (-1); + else + return (sectdone); +} + +static int +c302f_write_word(c302f_addr_t addr, c302f_word_t value) +{ + c302f_word_t stat; + ulong start; + int flag, retval; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = C302F_BNK_CMD_PROG; + + *addr = value; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + retval = 0; + + /* data polling for D7 */ + start = get_timer (0); + do { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + retval = 1; + goto done; + } + stat = *addr; + } while ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY); + + if ((stat & C302F_BNK_STAT_ERR) != 0) { + printf("flash program failed (stat = 0x%08lx) " + "at address 0x%08lx\n", (ulong)stat, (ulong)addr); + *addr = C302F_BNK_CMD_CLR_STAT; + retval = 3; + } + +done: + /* reset to read mode */ + *addr = C302F_BNK_CMD_RST; + + return (retval); +} + +#endif /* CONFIG_CMA302 */ + +unsigned long +flash_init(void) +{ + unsigned long total; + int i; + flash_info_t *fip; + + /* Init: no FLASHes known */ + for (i=0; isize; + fip++; +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) + /* not yet ... + cmbf_probe(fip, (cmbf_addr_t)CMA_MB_FLASH_BASE); + total += fip->size; + fip++; + */ +#endif + + /* + * protect monitor and environment sectors + */ + +#if CFG_MONITOR_BASE == CFG_FLASH_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + return total; +} + +/*----------------------------------------------------------------------- + */ +void +flash_print_info(flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F008S5: printf ("28F008S5\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 4) == 0) + printf ("\n "); + printf (" %2d - %08lX%s", i, + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +int +flash_erase(flash_info_t *info, int s_first, int s_last) +{ + int prot, sect, haderr; + ulong start, now, last; + void (*erase_init)(flash_info_t *, int); + int (*erase_poll)(flash_info_t *, int); + void (*reset)(flash_info_t *, int); + int rcode = 0; + +#ifdef FLASH_DEBUG + printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" + " Bank # %d: ", s_last - s_first + 1, s_first, s_last, + (info - flash_info) + 1); + flash_print_info(info); +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id) { + +#if defined(CONFIG_CMA302) + case FLASH_MAN_INTEL|FLASH_28F008S5: + erase_init = c302f_erase_init; + erase_poll = c302f_erase_poll; + reset = c302f_reset; + break; +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) + case FLASH_MAN_INTEL|FLASH_28F800_B: + case FLASH_MAN_AMD|FLASH_AM29F800B: + /* not yet ... + erase_init = cmbf_erase_init; + erase_poll = cmbf_erase_poll; + reset = cmbf_reset; + break; + */ +#endif + + default: + printf ("Flash type %08lx not supported - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sector%s will not be erased!\n", + prot, (prot > 1 ? "s" : "")); + } + + start = get_timer (0); + last = 0; + haderr = 0; + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + ulong estart; + int sectdone; + + (*erase_init)(info, sect); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + estart = get_timer(start); + + do { + now = get_timer(start); + + if (now - estart > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout (sect %d)\n", sect); + haderr = 1; + break; + } + +#ifndef FLASH_DEBUG + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } +#endif + + sectdone = (*erase_poll)(info, sect); + + if (sectdone < 0) { + haderr = 1; + break; + } + + } while (!sectdone); + + if (haderr) + break; + } + } + + if (haderr > 0) { + printf (" failed\n"); + rcode = 1; + } + else + printf (" done\n"); + + /* reset to read mode */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + (*reset)(info, sect); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 3 - write error + */ + +int +write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + ulong start, now, last; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + start = get_timer (0); + last = 0; + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + + /* show that we're waiting */ + now = get_timer(start); + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 3 - write error + */ +static int +write_word(flash_info_t *info, ulong dest, ulong data) +{ + int retval; + + /* Check if Flash is (sufficiently) erased */ + if ((*(ulong *)dest & data) != data) { + return (2); + } + + switch (info->flash_id) { + +#if defined(CONFIG_CMA302) + case FLASH_MAN_INTEL|FLASH_28F008S5: + retval = c302f_write_word((c302f_addr_t)dest, (c302f_word_t)data); + break; +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) + case FLASH_MAN_INTEL|FLASH_28F800_B: + case FLASH_MAN_AMD|FLASH_AM29F800B: + /* not yet ... + retval = cmbf_write_word((cmbf_addr_t)dest, (cmbf_word_t)data); + */ + retval = 3; + break; +#endif + + default: + printf ("Flash type %08lx not supported - aborted\n", + info->flash_id); + retval = 3; + break; + } + + return (retval); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/cogent/flash.h b/board/cogent/flash.h new file mode 100644 index 0000000..0b8d6aa --- /dev/null +++ b/board/cogent/flash.h @@ -0,0 +1,305 @@ +/**************** DEFINES for Intel 28F008S5 FLASH chip **********************/ + +/* register addresses, valid only following a I8S5_CMD_RD_ID command */ +#define I8S5_ADDR_MAN 0x00000 /* manufacturer's id */ +#define I8S5_ADDR_DEV 0x00001 /* device id */ +#define I8S5_ADDR_CFGM 0x00003 /* master lock configuration */ +#define I8S5_ADDR_CFG(b) (((b)<<16)|2) /* block lock configuration */ + +/* Commands */ +#define I8S5_CMD_RST 0xFF /* reset flash */ +#define I8S5_CMD_RD_ID 0x90 /* read the id and lock bits */ +#define I8S5_CMD_RD_STAT 0x70 /* read the status register */ +#define I8S5_CMD_CLR_STAT 0x50 /* clear the staus register */ +#define I8S5_CMD_ERASE1 0x20 /* first word for block erase */ +#define I8S5_CMD_ERASE2 0xD0 /* second word for block erase */ +#define I8S5_CMD_PROG 0x40 /* program word command */ +#define I8S5_CMD_LOCK 0x60 /* first word for all lock commands */ +#define I8S5_CMD_SET_LOCK_BLK 0x01 /* 2nd word for set block lock bit */ +#define I8S5_CMD_SET_LOCK_MSTR 0xF1 /* 2nd word for set master lock bit */ +#define I8S5_CMD_CLR_LOCK_BLK 0xD0 /* 2nd word for clear block lock bit */ + +/* status register bits */ +#define I8S5_STAT_DPS 0x02 /* Device Protect Status */ +#define I8S5_STAT_PSS 0x04 /* Program Suspend Status */ +#define I8S5_STAT_VPPS 0x08 /* VPP Status */ +#define I8S5_STAT_PSLBS 0x10 /* Program and Set Lock Bit Status */ +#define I8S5_STAT_ECLBS 0x20 /* Erase and Clear Lock Bit Status */ +#define I8S5_STAT_ESS 0x40 /* Erase Suspend Status */ +#define I8S5_STAT_RDY 0x80 /* Write State Machine Status, 1=rdy */ + +#define I8S5_STAT_ERR (I8S5_STAT_VPPS | I8S5_STAT_DPS | \ + I8S5_STAT_ECLBS | I8S5_STAT_PSLBS) + +/* ID and Lock Configuration */ +#define I8S5_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ +#define I8S5_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ +#define I8S5_RD_ID_DEV 0xA6 /* Device code = 0xA6, 28F008S5 */ + +/* dimensions */ +#define I8S5_NBLOCKS 16 /* a 28F008S5 consists of 16 blocks */ +#define I8S5_BLKSZ (64*1024) /* of 64Kbyte each */ +#define I8S5_SIZE (I8S5_BLKSZ * I8S5_NBLOCKS) + +/**************** DEFINES for Intel 28F800B5 FLASH chip **********************/ + +/* register addresses, valid only following a I8S5_CMD_RD_ID command */ +#define I8B5_ADDR_MAN 0x00000 /* manufacturer's id */ +#define I8B5_ADDR_DEV 0x00001 /* device id */ + +/* Commands */ +#define I8B5_CMD_RST 0xFF /* reset flash */ +#define I8B5_CMD_RD_ID 0x90 /* read the id and lock bits */ +#define I8B5_CMD_RD_STAT 0x70 /* read the status register */ +#define I8B5_CMD_CLR_STAT 0x50 /* clear the staus register */ +#define I8B5_CMD_ERASE1 0x20 /* first word for block erase */ +#define I8B5_CMD_ERASE2 0xD0 /* second word for block erase */ +#define I8B5_CMD_PROG 0x40 /* program word command */ + +/* status register bits */ +#define I8B5_STAT_VPPS 0x08 /* VPP Status */ +#define I8B5_STAT_DWS 0x10 /* Program and Set Lock Bit Status */ +#define I8B5_STAT_ES 0x20 /* Erase and Clear Lock Bit Status */ +#define I8B5_STAT_ESS 0x40 /* Erase Suspend Status */ +#define I8B5_STAT_RDY 0x80 /* Write State Machine Status, 1=rdy */ + +#define I8B5_STAT_ERR (I8B5_STAT_VPPS | I8B5_STAT_DWS | I8B5_STAT_ES) + +/* ID Configuration */ +#define I8B5_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ +#define I8B5_RD_ID_DEV1 0x889D /* Device code = 0x889D, 28F800B5 */ + +/* dimensions */ +#define I8B5_NBLOCKS 8 /* a 28F008S5 consists of 16 blocks */ +#define I8B5_BLKSZ (128*1024) /* of 64Kbyte each */ +#define I8B5_SIZE (I8B5_BLKSZ * I8B5_NBLOCKS) + +/****************** DEFINES for Cogent CMA302 Flash **************************/ + +/* + * Quoted from the CMA302 manual: + * + * Although the CMA302 supports 64-bit reads, all writes must be done with + * word size only. When programming the CMA302, the FLASH devices appear as 2 + * banks of interleaved, 32-bit wide FLASH. Each 32-bit word consists of four + * 28F008S5 devices. The first bank is accessed when the word address is even, + * while the second bank is accessed when the word address is odd. This must + * be taken into account when programming the desired word. Also, when locking + * blocks, software must lock both banks. The CMA302 does not directly support + * byte writing. Programming and/or erasing individual bytes is done with + * selective use of the Write Command. By not placing the Write Command value + * on a particular byte lane, that byte will not be written with the following + * Write Data. Also, remember that within a byte lane (i.e. D0-7), there are + * two 28F008S5 devices, one for each bank or every other word. + * + * End quote. + * + * Each 28F008S5 is 8Mbit, with 8 bit wide data. i.e. each is 1Mbyte. The + * chips are arranged on the CMA302 in multiples of two banks, each bank having + * 4 chips. Each bank must be accessed as a single 32 bit wide device (i.e. + * aligned on a 32 bit boundary), with each byte lane within the 32 bits (0-3) + * going to each of the 4 chips and the word address selecting the bank, even + * being the low bank and odd the high bank. For 64bit reads, both banks are + * read simultaneously with the second bank on byte lanes 4-7. Each 28F008S5 + * consists of 16 64Kbyte "block"s. Before programming a byte, the block that + * the byte resides within must be erased. So if you want to program contiguous + * memory locations, you must erase all 8 chips at the same time. i.e. the + * flash on the CMA302 can be viewed as a number of 512Kbyte blocks. + * + * Note: I am going to treat banks as 8 Mbytes (1Meg of 64bit words), whereas + * the example code treats them as a pair of interleaved 1 Mbyte x 32bit banks. + */ + +typedef unsigned long c302f_word_t; /* 32 or 64 bit unsigned integer */ +typedef volatile c302f_word_t *c302f_addr_t; +typedef unsigned long c302f_size_t; /* want this big - at least 32 bit */ + +/* layout of banks on cma302 board */ +#define C302F_BNK_WIDTH 8 /* each bank is 8 chips wide */ +#define C302F_BNK_WSHIFT 3 /* log base 2 of C302F_BNK_WIDTH */ +#define C302F_BNK_NBLOCKS I8S5_NBLOCKS +#define C302F_BNK_BLKSZ (I8S5_BLKSZ * C302F_BNK_WIDTH) +#define C302F_BNK_SIZE (I8S5_SIZE * C302F_BNK_WIDTH) + +#define C302F_MAX_BANKS 2 /* up to 2 banks (8M each) on CMA302 */ + +/* align addresses and sizes to bank boundaries */ +#define C302F_BNK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ + & ~(C302F_BNK_WIDTH - 1))) +#define C302F_BNK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BNK_ADDR_ALIGN( \ + (c302f_size_t)(s) + (C302F_BNK_WIDTH - 1))) + +/* align addresses and sizes to block boundaries */ +#define C302F_BLK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ + & ~(C302F_BNK_BLKSZ - 1))) +#define C302F_BLK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BLK_ADDR_ALIGN( \ + (c302f_size_t)(s) + (C302F_BNK_BLKSZ - 1))) + +/* add a byte offset to a flash address */ +#define C302F_ADDR_ADD_BYTEOFF(a,o) \ + (c302f_addr_t)((c302f_size_t)(a) + (o)) + +/* get base address of bank b, given flash base address a */ +#define C302F_BNK_ADDR_BASE(a,b) \ + C302F_ADDR_ADD_BYTEOFF((a), \ + (c302f_size_t)(b) * C302F_BNK_SIZE) + +/* adjust an address a (within a bank) to next word, block or bank */ +#define C302F_BNK_ADDR_NEXT_WORD(a) \ + C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_WIDTH) +#define C302F_BNK_ADDR_NEXT_BLK(a) \ + C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_BLKSZ) +#define C302F_BNK_ADDR_NEXT_BNK(a) \ + C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_SIZE) + +/* get bank address of chip register r given a bank base address a */ +#define C302F_BNK_ADDR_I8S5REG(a,r) \ + C302F_ADDR_ADD_BYTEOFF((a), \ + (r) << C302F_BNK_WSHIFT) + +/* make a bank representation for each chip address */ + +#define C302F_BNK_ADDR_MAN(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_MAN) +#define C302F_BNK_ADDR_DEV(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_DEV) +#define C302F_BNK_ADDR_CFGM(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFGM) +#define C302F_BNK_ADDR_CFG(b,a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG(b)) + +/* + * replicate a chip cmd/stat/rd value into each byte position within a word + * so that multiple chips are accessed in a single word i/o operation + * + * this must be as wide as the c302f_word_t type + */ +#define C302F_FILL_WORD(o) (((unsigned long)(o) << 24) | \ + ((unsigned long)(o) << 16) | \ + ((unsigned long)(o) << 8) | \ + (unsigned long)(o)) + +/* make a bank representation for each chip cmd/stat/rd value */ + +/* Commands */ +#define C302F_BNK_CMD_RST C302F_FILL_WORD(I8S5_CMD_RST) +#define C302F_BNK_CMD_RD_ID C302F_FILL_WORD(I8S5_CMD_RD_ID) +#define C302F_BNK_CMD_RD_STAT C302F_FILL_WORD(I8S5_CMD_RD_STAT) +#define C302F_BNK_CMD_CLR_STAT C302F_FILL_WORD(I8S5_CMD_CLR_STAT) +#define C302F_BNK_CMD_ERASE1 C302F_FILL_WORD(I8S5_CMD_ERASE1) +#define C302F_BNK_CMD_ERASE2 C302F_FILL_WORD(I8S5_CMD_ERASE2) +#define C302F_BNK_CMD_PROG C302F_FILL_WORD(I8S5_CMD_PROG) +#define C302F_BNK_CMD_LOCK C302F_FILL_WORD(I8S5_CMD_LOCK) +#define C302F_BNK_CMD_SET_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_SET_LOCK_BLK) +#define C302F_BNK_CMD_SET_LOCK_MSTR C302F_FILL_WORD(I8S5_CMD_SET_LOCK_MSTR) +#define C302F_BNK_CMD_CLR_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_CLR_LOCK_BLK) + +/* status register bits */ +#define C302F_BNK_STAT_DPS C302F_FILL_WORD(I8S5_STAT_DPS) +#define C302F_BNK_STAT_PSS C302F_FILL_WORD(I8S5_STAT_PSS) +#define C302F_BNK_STAT_VPPS C302F_FILL_WORD(I8S5_STAT_VPPS) +#define C302F_BNK_STAT_PSLBS C302F_FILL_WORD(I8S5_STAT_PSLBS) +#define C302F_BNK_STAT_ECLBS C302F_FILL_WORD(I8S5_STAT_ECLBS) +#define C302F_BNK_STAT_ESS C302F_FILL_WORD(I8S5_STAT_ESS) +#define C302F_BNK_STAT_RDY C302F_FILL_WORD(I8S5_STAT_RDY) + +#define C302F_BNK_STAT_ERR C302F_FILL_WORD(I8S5_STAT_ERR) + +/* ID and Lock Configuration */ +#define C302F_BNK_RD_ID_LOCK C302F_FILL_WORD(I8S5_RD_ID_LOCK) +#define C302F_BNK_RD_ID_MAN C302F_FILL_WORD(I8S5_RD_ID_MAN) +#define C302F_BNK_RD_ID_DEV C302F_FILL_WORD(I8S5_RD_ID_DEV) + +/*************** DEFINES for Cogent Motherboard Flash ************************/ + +typedef unsigned short cmbf_word_t; /* 16 bit unsigned integer */ +typedef volatile cmbf_word_t *cmbf_addr_t; +typedef unsigned long cmbf_size_t; /* want this big - at least 32 bit */ + +/* layout of banks on cogent motherboard - only 1 bank, 16 bit wide */ +#define CMBF_BNK_WIDTH 1 /* each bank is one chip wide */ +#define CMBF_BNK_WSHIFT 0 /* log base 2 of CMBF_BNK_WIDTH */ +#define CMBF_BNK_NBLOCKS I8B5_NBLOCKS +#define CMBF_BNK_BLKSZ (I8B5_BLKSZ * CMBF_BNK_WIDTH) +#define CMBF_BNK_SIZE (I8B5_SIZE * CMBF_BNK_WIDTH) + +#define CMBF_MAX_BANKS 1 /* only 1 x 1Mbyte bank on cogent m/b */ + +/* align addresses and sizes to bank boundaries */ +#define CMBF_BNK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ + & ~(CMBF_BNK_WIDTH - 1))) +#define CMBF_BNK_SIZE_ALIGN(s) ((c302f_size_t)CMBF_BNK_ADDR_ALIGN( \ + (c302f_size_t)(s) + (CMBF_BNK_WIDTH - 1))) + +/* align addresses and sizes to block boundaries */ +#define CMBF_BLK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ + & ~(CMBF_BNK_BLKSZ - 1))) +#define CMBF_BLK_SIZE_ALIGN(s) ((c302f_size_t)CMBF_BLK_ADDR_ALIGN( \ + (c302f_size_t)(s) + (CMBF_BNK_BLKSZ - 1))) + +/* add a byte offset to a flash address */ +#define CMBF_ADDR_ADD_BYTEOFF(a,o) \ + (c302f_addr_t)((c302f_size_t)(a) + (o)) + +/* get base address of bank b, given flash base address a */ +#define CMBF_BNK_ADDR_BASE(a,b) \ + CMBF_ADDR_ADD_BYTEOFF((a), \ + (c302f_size_t)(b) * CMBF_BNK_SIZE) + +/* adjust an address a (within a bank) to next word, block or bank */ +#define CMBF_BNK_ADDR_NEXT_WORD(a) \ + CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_WIDTH) +#define CMBF_BNK_ADDR_NEXT_BLK(a) \ + CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_BLKSZ) +#define CMBF_BNK_ADDR_NEXT_BNK(a) \ + CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_SIZE) + +/* get bank address of chip register r given a bank base address a */ +#define CMBF_BNK_ADDR_I8B5REG(a,r) \ + CMBF_ADDR_ADD_BYTEOFF((a), \ + (r) << CMBF_BNK_WSHIFT) + +/* make a bank representation for each chip address */ + +#define CMBF_BNK_ADDR_MAN(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_MAN) +#define CMBF_BNK_ADDR_DEV(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_DEV) +#define CMBF_BNK_ADDR_CFGM(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFGM) +#define CMBF_BNK_ADDR_CFG(b,a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG(b)) + +/* + * replicate a chip cmd/stat/rd value into each byte position within a word + * so that multiple chips are accessed in a single word i/o operation + * + * this must be as wide as the c302f_word_t type + */ +#define CMBF_FILL_WORD(o) (((unsigned long)(o) << 24) | \ + ((unsigned long)(o) << 16) | \ + ((unsigned long)(o) << 8) | \ + (unsigned long)(o)) + +/* make a bank representation for each chip cmd/stat/rd value */ + +/* Commands */ +#define CMBF_BNK_CMD_RST CMBF_FILL_WORD(I8B5_CMD_RST) +#define CMBF_BNK_CMD_RD_ID CMBF_FILL_WORD(I8B5_CMD_RD_ID) +#define CMBF_BNK_CMD_RD_STAT CMBF_FILL_WORD(I8B5_CMD_RD_STAT) +#define CMBF_BNK_CMD_CLR_STAT CMBF_FILL_WORD(I8B5_CMD_CLR_STAT) +#define CMBF_BNK_CMD_ERASE1 CMBF_FILL_WORD(I8B5_CMD_ERASE1) +#define CMBF_BNK_CMD_ERASE2 CMBF_FILL_WORD(I8B5_CMD_ERASE2) +#define CMBF_BNK_CMD_PROG CMBF_FILL_WORD(I8B5_CMD_PROG) +#define CMBF_BNK_CMD_LOCK CMBF_FILL_WORD(I8B5_CMD_LOCK) +#define CMBF_BNK_CMD_SET_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_BLK) +#define CMBF_BNK_CMD_SET_LOCK_MSTR CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_MSTR) +#define CMBF_BNK_CMD_CLR_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_CLR_LOCK_BLK) + +/* status register bits */ +#define CMBF_BNK_STAT_DPS CMBF_FILL_WORD(I8B5_STAT_DPS) +#define CMBF_BNK_STAT_PSS CMBF_FILL_WORD(I8B5_STAT_PSS) +#define CMBF_BNK_STAT_VPPS CMBF_FILL_WORD(I8B5_STAT_VPPS) +#define CMBF_BNK_STAT_PSLBS CMBF_FILL_WORD(I8B5_STAT_PSLBS) +#define CMBF_BNK_STAT_ECLBS CMBF_FILL_WORD(I8B5_STAT_ECLBS) +#define CMBF_BNK_STAT_ESS CMBF_FILL_WORD(I8B5_STAT_ESS) +#define CMBF_BNK_STAT_RDY CMBF_FILL_WORD(I8B5_STAT_RDY) + +#define CMBF_BNK_STAT_ERR CMBF_FILL_WORD(I8B5_STAT_ERR) + +/* ID and Lock Configuration */ +#define CMBF_BNK_RD_ID_LOCK CMBF_FILL_WORD(I8B5_RD_ID_LOCK) +#define CMBF_BNK_RD_ID_MAN CMBF_FILL_WORD(I8B5_RD_ID_MAN) +#define CMBF_BNK_RD_ID_DEV CMBF_FILL_WORD(I8B5_RD_ID_DEV) diff --git a/board/cogent/kbm.c b/board/cogent/kbm.c new file mode 100644 index 0000000..8496402 --- /dev/null +++ b/board/cogent/kbm.c @@ -0,0 +1,3 @@ +/* keyboard/mouse not implemented yet */ + +int cma_kbm_not_implemented = 1; diff --git a/board/cogent/kbm.h b/board/cogent/kbm.h new file mode 100644 index 0000000..7eb419c --- /dev/null +++ b/board/cogent/kbm.h @@ -0,0 +1,79 @@ +/* keyboard/mouse not implemented yet */ + +extern int cma_kbm_not_implemented; + +/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/ + +/* + * note the auxillary port is used to control the mouse + */ + +/* 8542B Commands (Sent to the Command Port) */ +#define HT8542_CMD_SET_BYTE 0x60 /* Set the command byte */ +#define HT8542_CMD_GET_BYTE 0x20 /* Get the command byte */ +#define HT8542_CMD_KBD_OBUFF 0xD2 /* Write to HT8542 Kbd Output Buffer */ +#define HT8542_CMD_AUX_OBUFF 0xD3 /* Write to HT8542 Mse Output Buffer */ +#define HT8542_CMD_AUX_WRITE 0xD4 /* Write to Mouse Port */ +#define HT8542_CMD_AUX_OFF 0xA7 /* Disable Mouse Port */ +#define HT8542_CMD_AUX_ON 0xA8 /* Re-Enable Mouse Port */ +#define HT8542_CMD_AUX_TEST 0xA9 /* Test for the presence of a Mouse */ +#define HT8542_CMD_DIAG 0xAA /* Start Diagnostics */ +#define HT8542_CMD_KBD_TEST 0xAB /* Test for presence of a keyboard */ +#define HT8542_CMD_KBD_OFF 0xAD /* Disable Kbd Port (use KBD_DAT_ON) */ +#define HT8542_CMD_KBD_ON 0xAE /* Enable Kbd Port (use KBD_DAT_OFF) */ + +/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */ +#define HT8542_CMD_BYTE_TRANS 0x40 +#define HT8542_CMD_BYTE_AUX_OFF 0x20 /* 1 = mse port disabled, 0 = enabled */ +#define HT8542_CMD_BYTE_KBD_OFF 0x10 /* 1 = kbd port disabled, 0 = enabled */ +#define HT8542_CMD_BYTE_OVER 0x08 /* 1 = override keyboard lock */ +#define HT8542_CMD_BYTE_RES 0x04 /* reserved */ +#define HT8542_CMD_BYTE_AUX_INT 0x02 /* 1 = enable mouse interrupt */ +#define HT8542_CMD_BYTE_KBD_INT 0x01 /* 1 = enable keyboard interrupt */ + +/* Keyboard Commands (Sent to the Data Port) */ +#define KBD_CMD_LED 0xED /* Set Keyboard LEDS with next byte */ +#define KBD_CMD_ECHO 0xEE /* Echo - we get 0xFA, 0xEE back */ +#define KBD_CMD_MODE 0xF0 /* set scan code mode with next byte */ +#define KBD_CMD_ID 0xF2 /* get keyboard/mouse ID */ +#define KBD_CMD_RPT 0xF3 /* Set Repeat Rate and Delay 2nd Byte */ +#define KBD_CMD_ON 0xF4 /* Enable keyboard */ +#define KBD_CMD_OFF 0xF5 /* Disables Scanning, Resets to Def */ +#define KBD_CMD_DEF 0xF6 /* Reverts kbd to default settings */ +#define KBD_CMD_RST 0xFF /* Reset - should get 0xFA, 0xAA back */ + +/* Set LED second bit defines */ +#define KBD_CMD_LED_SCROLL 0x01 /* Set SCROLL LOCK LED on */ +#define KBD_CMD_LED_NUM 0x02 /* Set NUM LOCK LED on */ +#define KBD_CMD_LED_CAPS 0x04 /* Set CAPS LOCK LED on */ + +/* Set Mode second byte defines */ +#define KBD_CMD_MODE_STAT 0x00 /* get current scan code mode */ +#define KBD_CMD_MODE_SCAN1 0x01 /* set mode to scan code 1 */ +#define KBD_CMD_MODE_SCAN2 0x02 /* set mode to scan code 2 */ +#define KBD_CMD_MODE_SCAN3 0x03 /* set mode to scan code 3 */ + +/* Keyboard/Mouse ID Codes */ +#define KBD_CMD_ID_1ST 0xAB /* 1st byte is 0xAB, 2nd is actual ID */ +#define KBD_CMD_ID_KBD 0x83 /* Keyboard */ +#define KBD_CMD_ID_MOUSE 0x00 /* Mouse */ + +/* Keyboard Data Return Defines */ +#define KBD_STAT_OVER 0x00 /* Buffer Overrun */ +#define KBD_STAT_DIAG_OK 0x55 /* Internal Self Test OK */ +#define KBD_STAT_RST_OK 0xAA /* Reset Complete */ +#define KBD_STAT_ECHO 0xEE /* Echo Command Return */ +#define KBD_STAT_BRK 0xF0 /* Prefix for Break Key Code */ +#define KBD_STAT_ACK 0xFA /* Received after all commands */ +#define KBD_STAT_DIAG_FAIL 0xFD /* Internal Self Test Failed */ +#define KBD_STAT_RESEND 0xFE /* Resend Last Command */ + +/* HT8542B Status Register Bit Defines */ +#define HT8542_STAT_OBF 0x01 /* 1 = output buffer is full */ +#define HT8542_STAT_IBF 0x02 /* 1 = input buffer is full */ +#define HT8542_STAT_SYS 0x04 /* system flag - unused */ +#define HT8542_STAT_CMD 0x08 /* 1 = cmd in input buffer, 0 = data */ +#define HT8542_STAT_INH 0x10 /* 1 = Inhibit - unused */ +#define HT8542_STAT_TX 0x20 /* 1 = Transmit Timeout has occured */ +#define HT8542_STAT_RX 0x40 /* 1 = Receive Timeout has occured */ +#define HT8542_STAT_PERR 0x80 /* 1 = Parity Error from Keyboard */ diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c new file mode 100644 index 0000000..814b4c8 --- /dev/null +++ b/board/cogent/lcd.c @@ -0,0 +1,245 @@ +/* most of this is taken from the file */ +/* hal/powerpc/cogent/current/src/hal_diag.c in the */ +/* Cygnus eCos source. Here is the copyright notice: */ +/* */ +/*============================================================================= */ +/* */ +/* hal_diag.c */ +/* */ +/* HAL diagnostic output code */ +/* */ +/*============================================================================= */ +/*####COPYRIGHTBEGIN#### */ +/* */ +/* ------------------------------------------- */ +/* The contents of this file are subject to the Cygnus eCos Public License */ +/* Version 1.0 (the "License"); you may not use this file except in */ +/* compliance with the License. You may obtain a copy of the License at */ +/* http://sourceware.cygnus.com/ecos */ +/* */ +/* Software distributed under the License is distributed on an "AS IS" */ +/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */ +/* License for the specific language governing rights and limitations under */ +/* the License. */ +/* */ +/* The Original Code is eCos - Embedded Cygnus Operating System, released */ +/* September 30, 1998. */ +/* */ +/* The Initial Developer of the Original Code is Cygnus. Portions created */ +/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */ +/* ------------------------------------------- */ +/* */ +/*####COPYRIGHTEND#### */ +/*============================================================================= */ +/*#####DESCRIPTIONBEGIN#### */ +/* */ +/* Author(s): nickg, jskov */ +/* Contributors: nickg, jskov */ +/* Date: 1999-03-23 */ +/* Purpose: HAL diagnostic output */ +/* Description: Implementations of HAL diagnostic output support. */ +/* */ +/*####DESCRIPTIONEND#### */ +/* */ +/*============================================================================= */ + +/*----------------------------------------------------------------------------- */ +/* Cogent board specific LCD code */ + +#include +#include +#include + +static char lines[2][LCD_LINE_LENGTH+1]; +static int curline; +static int linepos; +static int heartbeat_active; +/* make the next two strings exactly LCD_LINE_LENGTH (16) chars long */ +/* pad to the right with spaces if necessary */ +static char init_line0[LCD_LINE_LENGTH+1] = "U-Boot Cogent "; +static char init_line1[LCD_LINE_LENGTH+1] = "mjj, 11 Aug 2000"; + +static inline unsigned char +lcd_read_status(cma_mb_lcd *clp) +{ + /* read the Busy Status Register */ + return (cma_mb_reg_read(&clp->lcd_bsr)); +} + +static inline void +lcd_wait_not_busy(cma_mb_lcd *clp) +{ + /* + * wait for not busy + * Note: It seems that the LCD isn't quite ready to process commands + * when it clears the BUSY flag. Reading the status address an extra + * time seems to give it enough breathing room. + */ + + while (lcd_read_status(clp) & LCD_STAT_BUSY) + ; + + (void)lcd_read_status(clp); +} + +static inline void +lcd_write_command(cma_mb_lcd *clp, unsigned char cmd) +{ + lcd_wait_not_busy(clp); + + /* write the Command Register */ + cma_mb_reg_write(&clp->lcd_cmd, cmd); +} + +static inline void +lcd_write_data(cma_mb_lcd *clp, unsigned char data) +{ + lcd_wait_not_busy(clp); + + /* write the Current Character Register */ + cma_mb_reg_write(&clp->lcd_ccr, data); +} + +static inline void +lcd_dis(int addr, char *string) +{ + cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE; + int pos, linelen; + + linelen = LCD_LINE_LENGTH; + if (heartbeat_active && addr == LCD_LINE0) + linelen--; + + lcd_write_command(clp, LCD_CMD_ADD + addr); + for (pos = 0; *string != '\0' && pos < linelen; pos++) + lcd_write_data(clp, *string++); +} + +void +lcd_init(void) +{ + cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE; + int i; + + /* configure the lcd for 8 bits/char, 2 lines and 5x7 dot matrix */ + lcd_write_command(clp, LCD_CMD_MODE); + + /* turn the LCD display on */ + lcd_write_command(clp, LCD_CMD_DON); + + curline = 0; + linepos = 0; + + for (i = 0; i < LCD_LINE_LENGTH; i++) { + lines[0][i] = init_line0[i]; + lines[1][i] = init_line1[i]; + } + + lines[0][LCD_LINE_LENGTH] = lines[1][LCD_LINE_LENGTH] = 0; + + lcd_dis(LCD_LINE0, lines[0]); + lcd_dis(LCD_LINE1, lines[1]); + + printf("HD44780 2 line x %d char display\n", LCD_LINE_LENGTH); +} + +void +lcd_write_char(const char c) +{ + int i, linelen; + + /* ignore CR */ + if (c == '\r') + return; + + linelen = LCD_LINE_LENGTH; + if (heartbeat_active && curline == 0) + linelen--; + + if (c == '\n') { + lcd_dis(LCD_LINE0, &lines[curline^1][0]); + lcd_dis(LCD_LINE1, &lines[curline][0]); + + /* Do a line feed */ + curline ^= 1; + linelen = LCD_LINE_LENGTH; + if (heartbeat_active && curline == 0) + linelen--; + linepos = 0; + + for (i = 0; i < linelen; i++) + lines[curline][i] = ' '; + + return; + } + + /* Only allow to be output if there is room on the LCD line */ + if (linepos < linelen) + lines[curline][linepos++] = c; +} + +void +lcd_flush(void) +{ + lcd_dis(LCD_LINE1, &lines[curline][0]); +} + +void +lcd_write_string(const char *s) +{ + char *p; + + for (p = (char *)s; *p != '\0'; p++) + lcd_write_char(*p); +} + +void +lcd_printf(const char *fmt, ...) +{ + va_list args; + char buf[CFG_PBSIZE]; + + va_start(args, fmt); + (void)vsprintf(buf, fmt, args); + va_end(args); + + lcd_write_string(buf); +} + +void +lcd_heartbeat(void) +{ + cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE; +#if 0 + static char rotchars[] = { '|', '/', '-', '\\' }; +#else + /* HD44780 Rom Code A00 has no backslash */ + static char rotchars[] = { '|', '/', '-', '\315' }; +#endif + static int rotator_index = 0; + + heartbeat_active = 1; + + /* write the address */ + lcd_write_command(clp, LCD_CMD_ADD + LCD_LINE0 + (LCD_LINE_LENGTH - 1)); + + /* write the next char in the sequence */ + lcd_write_data(clp, rotchars[rotator_index]); + + if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0])) + rotator_index = 0; +} + +#ifdef CONFIG_SHOW_ACTIVITY +void board_show_activity (ulong timestamp) +{ +#ifdef CONFIG_STATUS_LED + if ((timestamp % (CFG_HZ / 2) == 0) + lcd_heartbeat (); +#endif +} + +void show_activity(int arg) +{ +} +#endif diff --git a/board/cogent/lcd.h b/board/cogent/lcd.h new file mode 100644 index 0000000..1056eea --- /dev/null +++ b/board/cogent/lcd.h @@ -0,0 +1,84 @@ +/* most of this is taken from the file */ +/* hal/powerpc/cogent/current/src/hal_diag.c in the */ +/* Cygnus eCos source. Here is the copyright notice: */ +/* */ +/*============================================================================= */ +/* */ +/* hal_diag.c */ +/* */ +/* HAL diagnostic output code */ +/* */ +/*============================================================================= */ +/*####COPYRIGHTBEGIN#### */ +/* */ +/* ------------------------------------------- */ +/* The contents of this file are subject to the Cygnus eCos Public License */ +/* Version 1.0 (the "License"); you may not use this file except in */ +/* compliance with the License. You may obtain a copy of the License at */ +/* http://sourceware.cygnus.com/ecos */ +/* */ +/* Software distributed under the License is distributed on an "AS IS" */ +/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */ +/* License for the specific language governing rights and limitations under */ +/* the License. */ +/* */ +/* The Original Code is eCos - Embedded Cygnus Operating System, released */ +/* September 30, 1998. */ +/* */ +/* The Initial Developer of the Original Code is Cygnus. Portions created */ +/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */ +/* ------------------------------------------- */ +/* */ +/*####COPYRIGHTEND#### */ +/*============================================================================= */ +/*#####DESCRIPTIONBEGIN#### */ +/* */ +/* Author(s): nickg, jskov */ +/* Contributors: nickg, jskov */ +/* Date: 1999-03-23 */ +/* Purpose: HAL diagnostic output */ +/* Description: Implementations of HAL diagnostic output support. */ +/* */ +/*####DESCRIPTIONEND#### */ +/* */ +/*============================================================================= */ + +/* FEMA 162B 16 character x 2 line LCD */ + +/* status register bit definitions */ +#define LCD_STAT_BUSY 0x80 /* 1 = display busy */ +#define LCD_STAT_ADD 0x7F /* bits 0-6 return current display address */ + +/* command register definitions */ +#define LCD_CMD_RST 0x01 /* clear entire display and reset display addr */ +#define LCD_CMD_HOME 0x02 /* reset display address and reset any shifting */ +#define LCD_CMD_ECL 0x04 /* move cursor left one pos on next data write */ +#define LCD_CMD_ESL 0x05 /* shift display left one pos on next data write */ +#define LCD_CMD_ECR 0x06 /* move cursor right one pos on next data write */ +#define LCD_CMD_ESR 0x07 /* shift disp right one pos on next data write */ +#define LCD_CMD_DOFF 0x08 /* display off, cursor off, blinking off */ +#define LCD_CMD_BL 0x09 /* blink character at current cursor position */ +#define LCD_CMD_CUR 0x0A /* enable cursor on */ +#define LCD_CMD_DON 0x0C /* turn display on */ +#define LCD_CMD_CL 0x10 /* move cursor left one position */ +#define LCD_CMD_SL 0x14 /* shift display left one position */ +#define LCD_CMD_CR 0x18 /* move cursor right one position */ +#define LCD_CMD_SR 0x1C /* shift display right one position */ +#define LCD_CMD_MODE 0x38 /* sets 8 bits, 2 lines, 5x7 characters */ +#define LCD_CMD_ACG 0x40 /* bits 0-5 sets character generator address */ +#define LCD_CMD_ADD 0x80 /* bits 0-6 sets display data addr to line 1 + */ + +/* LCD status values */ +#define LCD_OK 0x00 +#define LCD_ERR 0x01 + +#define LCD_LINE0 0x00 +#define LCD_LINE1 0x40 + +#define LCD_LINE_LENGTH 16 + +extern void lcd_init(void); +extern void lcd_write_char(const char); +extern void lcd_flush(void); +extern void lcd_write_string(const char *); +extern void lcd_printf(const char *, ...); diff --git a/board/cogent/mb.c b/board/cogent/mb.c new file mode 100644 index 0000000..917132b --- /dev/null +++ b/board/cogent/mb.c @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_8260) + +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ {0, 0, 0, 0, 0, 0}, + /* PA30 */ {0, 0, 0, 0, 0, 0}, + /* PA29 */ {0, 0, 0, 0, 0, 0}, + /* PA28 */ {0, 0, 0, 0, 0, 0}, + /* PA27 */ {0, 0, 0, 0, 0, 0}, + /* PA26 */ {0, 0, 0, 0, 0, 0}, + /* PA25 */ {0, 0, 0, 0, 0, 0}, + /* PA24 */ {0, 0, 0, 0, 0, 0}, + /* PA23 */ {0, 0, 0, 0, 0, 0}, + /* PA22 */ {0, 0, 0, 0, 0, 0}, + /* PA21 */ {0, 0, 0, 0, 0, 0}, + /* PA20 */ {0, 0, 0, 0, 0, 0}, + /* PA19 */ {0, 0, 0, 0, 0, 0}, + /* PA18 */ {0, 0, 0, 0, 0, 0}, + /* PA17 */ {0, 0, 0, 0, 0, 0}, + /* PA16 */ {0, 0, 0, 0, 0, 0}, + /* PA15 */ {0, 0, 0, 0, 0, 0}, + /* PA14 */ {0, 0, 0, 0, 0, 0}, + /* PA13 */ {0, 0, 0, 0, 0, 0}, + /* PA12 */ {0, 0, 0, 0, 0, 0}, + /* PA11 */ {0, 0, 0, 0, 0, 0}, + /* PA10 */ {0, 0, 0, 0, 0, 0}, + /* PA9 */ {1, 1, 0, 1, 0, 0}, + /* SMC2 TXD */ + /* PA8 */ {1, 1, 0, 0, 0, 0}, + /* SMC2 RXD */ + /* PA7 */ {0, 0, 0, 0, 0, 0}, + /* PA6 */ {0, 0, 0, 0, 0, 0}, + /* PA5 */ {0, 0, 0, 0, 0, 0}, + /* PA4 */ {0, 0, 0, 0, 0, 0}, + /* PA3 */ {0, 0, 0, 0, 0, 0}, + /* PA2 */ {0, 0, 0, 0, 0, 0}, + /* PA1 */ {0, 0, 0, 0, 0, 0}, + /* PA0 */ {0, 0, 0, 0, 0, 0} + }, + + + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ {0, 0, 0, 0, 0, 0}, + /* PB30 */ {0, 0, 0, 0, 0, 0}, + /* PB29 */ {0, 0, 0, 0, 0, 0}, + /* PB28 */ {0, 0, 0, 0, 0, 0}, + /* PB27 */ {0, 0, 0, 0, 0, 0}, + /* PB26 */ {0, 0, 0, 0, 0, 0}, + /* PB25 */ {0, 0, 0, 0, 0, 0}, + /* PB24 */ {0, 0, 0, 0, 0, 0}, + /* PB23 */ {0, 0, 0, 0, 0, 0}, + /* PB22 */ {0, 0, 0, 0, 0, 0}, + /* PB21 */ {0, 0, 0, 0, 0, 0}, + /* PB20 */ {0, 0, 0, 0, 0, 0}, + /* PB19 */ {0, 0, 0, 0, 0, 0}, + /* PB18 */ {0, 0, 0, 0, 0, 0}, + /* PB17 */ {0, 0, 0, 0, 0, 0}, + /* PB16 */ {0, 0, 0, 0, 0, 0}, + /* PB15 */ {0, 0, 0, 0, 0, 0}, + /* PB14 */ {0, 0, 0, 0, 0, 0}, + /* PB13 */ {0, 0, 0, 0, 0, 0}, + /* PB12 */ {0, 0, 0, 0, 0, 0}, + /* PB11 */ {0, 0, 0, 0, 0, 0}, + /* PB10 */ {0, 0, 0, 0, 0, 0}, + /* PB9 */ {0, 0, 0, 0, 0, 0}, + /* PB8 */ {0, 0, 0, 0, 0, 0}, + /* PB7 */ {0, 0, 0, 0, 0, 0}, + /* PB6 */ {0, 0, 0, 0, 0, 0}, + /* PB5 */ {0, 0, 0, 0, 0, 0}, + /* PB4 */ {0, 0, 0, 0, 0, 0}, + /* PB3 */ {0, 0, 0, 0, 0, 0}, + /* pin doesn't exist */ + /* PB2 */ {0, 0, 0, 0, 0, 0}, + /* pin doesn't exist */ + /* PB1 */ {0, 0, 0, 0, 0, 0}, + /* pin doesn't exist */ + /* PB0 */ {0, 0, 0, 0, 0, 0} + /* pin doesn't exist */ + }, + + + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ {0, 0, 0, 0, 0, 0}, + /* PC30 */ {0, 0, 0, 0, 0, 0}, + /* PC29 */ {0, 0, 0, 0, 0, 0}, + /* PC28 */ {0, 0, 0, 0, 0, 0}, + /* PC27 */ {0, 0, 0, 0, 0, 0}, + /* PC26 */ {0, 0, 0, 0, 0, 0}, + /* PC25 */ {0, 0, 0, 0, 0, 0}, + /* PC24 */ {0, 0, 0, 0, 0, 0}, + /* PC23 */ {0, 0, 0, 0, 0, 0}, + /* PC22 */ {0, 0, 0, 0, 0, 0}, + /* PC21 */ {0, 0, 0, 0, 0, 0}, + /* PC20 */ {0, 0, 0, 0, 0, 0}, + /* PC19 */ {0, 0, 0, 0, 0, 0}, + /* PC18 */ {0, 0, 0, 0, 0, 0}, + /* PC17 */ {0, 0, 0, 0, 0, 0}, + /* PC16 */ {0, 0, 0, 0, 0, 0}, + /* PC15 */ {0, 0, 0, 0, 0, 0}, + /* PC14 */ {0, 0, 0, 0, 0, 0}, + /* PC13 */ {0, 0, 0, 0, 0, 0}, + /* PC12 */ {0, 0, 0, 0, 0, 0}, + /* PC11 */ {0, 0, 0, 0, 0, 0}, + /* PC10 */ {0, 0, 0, 0, 0, 0}, + /* PC9 */ {0, 0, 0, 0, 0, 0}, + /* PC8 */ {0, 0, 0, 0, 0, 0}, + /* PC7 */ {0, 0, 0, 0, 0, 0}, + /* PC6 */ {0, 0, 0, 0, 0, 0}, + /* PC5 */ {0, 0, 0, 0, 0, 0}, + /* PC4 */ {0, 0, 0, 0, 0, 0}, + /* PC3 */ {0, 0, 0, 0, 0, 0}, + /* PC2 */ {0, 0, 0, 0, 0, 0}, + /* PC1 */ {0, 0, 0, 0, 0, 0}, + /* PC0 */ {0, 0, 0, 0, 0, 0} + }, + + + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ {0, 0, 0, 0, 0, 0}, + /* PD30 */ {0, 0, 0, 0, 0, 0}, + /* PD29 */ {0, 0, 0, 0, 0, 0}, + /* PD28 */ {0, 0, 0, 0, 0, 0}, + /* PD27 */ {0, 0, 0, 0, 0, 0}, + /* PD26 */ {0, 0, 0, 0, 0, 0}, + /* PD25 */ {0, 0, 0, 0, 0, 0}, + /* PD24 */ {0, 0, 0, 0, 0, 0}, + /* PD23 */ {0, 0, 0, 0, 0, 0}, + /* PD22 */ {0, 0, 0, 0, 0, 0}, + /* PD21 */ {0, 0, 0, 0, 0, 0}, + /* PD20 */ {0, 0, 0, 0, 0, 0}, + /* PD19 */ {0, 0, 0, 0, 0, 0}, + /* PD18 */ {0, 0, 0, 0, 0, 0}, + /* PD17 */ {0, 0, 0, 0, 0, 0}, + /* PD16 */ {0, 0, 0, 0, 0, 0}, + /* PD15 */ {1, 1, 1, 0, 0, 0}, + /* I2C SDA */ + /* PD14 */ {1, 1, 1, 0, 0, 0}, + /* I2C SCL */ + /* PD13 */ {0, 0, 0, 0, 0, 0}, + /* PD12 */ {0, 0, 0, 0, 0, 0}, + /* PD11 */ {0, 0, 0, 0, 0, 0}, + /* PD10 */ {0, 0, 0, 0, 0, 0}, + /* PD9 */ {1, 1, 0, 1, 0, 0}, + /* SMC1 TXD */ + /* PD8 */ {1, 1, 0, 0, 0, 0}, + /* SMC1 RXD */ + /* PD7 */ {0, 0, 0, 0, 0, 0}, + /* PD6 */ {0, 0, 0, 0, 0, 0}, + /* PD5 */ {0, 0, 0, 0, 0, 0}, + /* PD4 */ {0, 0, 0, 0, 0, 0}, + /* PD3 */ {0, 0, 0, 0, 0, 0}, + /* pin doesn't exist */ + /* PD2 */ {0, 0, 0, 0, 0, 0}, + /* pin doesn't exist */ + /* PD1 */ {0, 0, 0, 0, 0, 0}, + /* pin doesn't exist */ + /* PD0 */ {0, 0, 0, 0, 0, 0} + /* pin doesn't exist */ + } +}; + +#endif /* CONFIG_8260 */ + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a " + COGENT_CPU_MODULE " CPU Module\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations while still + * running in flash + */ + +int misc_init_f (void) +{ + printf ("DIPSW: "); + dipsw_init (); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ +#ifdef CONFIG_CMA111 + return (32L * 1024L * 1024L); +#else + unsigned char dipsw_val; + int dual, size0, size1; + long int memsize; + + dipsw_val = dipsw_cooked (); + + dual = dipsw_val & 0x01; + size0 = (dipsw_val & 0x08) >> 3; + size1 = (dipsw_val & 0x04) >> 2; + + if (size0) + if (size1) + memsize = 16L * 1024L * 1024L; + else + memsize = 1L * 1024L * 1024L; + else if (size1) + memsize = 4L * 1024L * 1024L; + else { + printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] "); + memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */ + } + + if (dual) + memsize *= 2L; + + return (memsize); +#endif +} + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations after monitor + * has been relocated into ram + */ + +int misc_init_r (void) +{ + printf ("LCD: "); + lcd_init (); + +#if 0 + printf ("RTC: "); + rtc_init (); + + printf ("PAR: "); + par_init (); + + printf ("KBM: "); + kbm_init (); + + printf ("PCI: "); + pci_init (); +#endif + return (0); +} diff --git a/board/cogent/mb.h b/board/cogent/mb.h new file mode 100644 index 0000000..f6eaf0a --- /dev/null +++ b/board/cogent/mb.h @@ -0,0 +1,529 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * defines for Cogent Motherboards + */ + +#ifndef _COGENT_MB_H +#define _COGENT_MB_H + +/* + * Cogent Motherboard Address Map + * + * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits). + * + * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following + * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and + * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3). + * Most other motherboard devices have registers mapped into the area + * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF + * is free for whatever. + * + * The location of the motherboard address space in the physical address space + * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu + * module plugged into the motherboard and is configured above. + * + * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF) + * generally only use byte lane 0 (D0-7) for their transfers, i.e. only + * 8 bit, or 1 byte, transfers can take place, so all the registers are + * only 8 bits wide. The exceptions are the motherboard flash, which uses + * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space. + * + * I/O registers within the mapped motherboard devices are 64 bit aligned + * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register + * will be at byte 7 (the address + 7). For little endian addressing, the + * register will be at byte 0 (the address + 0). To learn the endianess + * we must include + * + * Take the CMA102 and CMA111 motherboards as examples... + * + * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3 + * CMABus slots are each mapped directly onto the three general I/O slots. + * + * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI + * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard + * PCI Bus space is mapped onto general I/O slot 2, with a small area at the + * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF). + * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area + * 0xA000000-0xDFFFFFF. + */ + +#define CMA_MB_RAM_BASE (CFG_CMA_MB_BASE+0x0000000) +#define CMA_MB_RAM_SIZE 0x2000000 /* dip sws set actual size */ + +#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1) +#define CMA_MB_SLOT1_BASE (CFG_CMA_MB_BASE+0x2000000) +#define CMA_MB_SLOT1_SIZE 0x2000000 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) +#define CMA_MB_SLOT2_BASE (CFG_CMA_MB_BASE+0x4000000) +#define CMA_MB_SLOT2_SIZE 0x2000000 +#endif +#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) +#define CMA_MB_STDPCI_BASE (CFG_CMA_MB_BASE+0x4000000) +#define CMA_MB_STDPCI_SIZE 0x1ff0000 +#define CMA_MB_V360EPC_BASE (CFG_CMA_MB_BASE+0x5ff0000) +#define CMA_MB_V360EPC_SIZE 0x10000 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3) +#define CMA_MB_SLOT3_BASE (CFG_CMA_MB_BASE+0x6000000) +#define CMA_MB_SLOT3_SIZE 0x2000000 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) +#define CMA_MB_EXTPCI_BASE (CFG_CMA_MB_BASE+0xa000000) +#define CMA_MB_EXTPCI_SIZE 0x4000000 +#endif + +#define CMA_MB_ROMLOW_BASE (CFG_CMA_MB_BASE+0xe000000) +#define CMA_MB_ROMLOW_SIZE 0x800000 +#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) +#define CMA_MB_FLLOW_EXEC_BASE (CFG_CMA_MB_BASE+0xe000000) +#define CMA_MB_FLLOW_EXEC_SIZE 0x100000 +#define CMA_MB_FLLOW_RDWR_BASE (CFG_CMA_MB_BASE+0xe400000) +#define CMA_MB_FLLOW_RDWR_SIZE 0x400000 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_RTC) +#define CMA_MB_RTC_BASE (CFG_CMA_MB_BASE+0xe800000) +#define CMA_MB_RTC_SIZE 0x4000 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) +#define CMA_MB_SERPAR_BASE (CFG_CMA_MB_BASE+0xe900000) +#define CMA_MB_SERIALB_BASE (CMA_MB_SERPAR_BASE+0x00) +#define CMA_MB_SERIALA_BASE (CMA_MB_SERPAR_BASE+0x40) +#define CMA_MB_PARALLEL_BASE (CMA_MB_SERPAR_BASE+0x80) +#define CMA_MB_SERPAR_SIZE 0xa0 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) +#define CMA_MB_PKBM_BASE (CFG_CMA_MB_BASE+0xe900100) +#define CMA_MB_PKBM_SIZE 0x10 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_LCD) +#define CMA_MB_LCD_BASE (CFG_CMA_MB_BASE+0xeb00000) +#define CMA_MB_LCD_SIZE 0x10 +#endif + +#define CMA_MB_DIPSW_BASE (CFG_CMA_MB_BASE+0xec00000) +#define CMA_MB_DIPSW_SIZE 0x10 + +#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM)) +#define CMA_MB_SLOT1CFG_BASE (CFG_CMA_MB_BASE+0xf100000) +#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) +#define CMA_MB_SER2_BASE (CMA_MB_SLOT1CFG_BASE+0x80) +#define CMA_MB_SER2B_BASE (CMA_MB_SER2_BASE+0x00) +#define CMA_MB_SER2A_BASE (CMA_MB_SER2_BASE+0x40) +#endif +#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1) +#define CMA_MB_S1KBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200) +#endif +#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150) +#define CMA_MB_IREQ1STAT_BASE (CMA_MB_SLOT1CFG_BASE+0x100) +#define CMA_MB_AKBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200) +#define CMA_MB_IREQ1MASK_BASE (CMA_MB_SLOT1CFG_BASE+0x300) +#endif +#define CMA_MB_SLOT1CFG_SIZE 0x400 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) +#define CMA_MB_SLOT2CFG_BASE (CFG_CMA_MB_BASE+0xf200000) +#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2) +#define CMA_MB_S2KBM_BASE (CMA_MB_SLOT2CFG_BASE+0x200) +#endif +#define CMA_MB_SLOT2CFG_SIZE 0x400 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) +#define CMA_MB_PCICTL_BASE (CFG_CMA_MB_BASE+0xf200000) +#define CMA_MB_PCI_V3CTL_BASE (CMA_MB_PCICTL_BASE+0x100) +#define CMA_MB_PCI_IDSEL_BASE (CMA_MB_PCICTL_BASE+0x200) +#define CMA_MB_PCI_IMASK_BASE (CMA_MB_PCICTL_BASE+0x300) +#define CMA_MB_PCI_ISTAT_BASE (CMA_MB_PCICTL_BASE+0x400) +#define CMA_MB_PCI_MBID_BASE (CMA_MB_PCICTL_BASE+0x500) +#define CMA_MB_PCI_MBREV_BASE (CMA_MB_PCICTL_BASE+0x600) +#define CMA_MB_PCICTL_SIZE 0x700 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3) +#define CMA_MB_SLOT3CFG_BASE (CFG_CMA_MB_BASE+0xf300000) +#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3) +#define CMA_MB_S3KBM_BASE (CMA_MB_SLOT3CFG_BASE+0x200) +#endif +#define CMA_MB_SLOT3CFG_SIZE 0x400 +#endif + +#define CMA_MB_ROMHIGH_BASE (CFG_CMA_MB_BASE+0xf800000) +#define CMA_MB_ROMHIGH_SIZE 0x800000 +#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) +#define CMA_MB_FLHIGH_EXEC_BASE (CFG_CMA_MB_BASE+0xf800000) +#define CMA_MB_FLHIGH_EXEC_SIZE 0x100000 +#define CMA_MB_FLHIGH_RDWR_BASE (CFG_CMA_MB_BASE+0xfc00000) +#define CMA_MB_FLHIGH_RDWR_SIZE 0x400000 +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) + +/* PCI Control Register bits */ + +/* V360EPC Control register bits */ +#define CMA_MB_PCI_V3CTL_RESET 0x01 +#define CMA_MB_PCI_V3CTL_EXTADD 0x08 + +/* PCI ID Select register bits */ +#define CMA_MB_PCI_IDSEL_SLOTA 0x01 +#define CMA_MB_PCI_IDSEL_SLOTB 0x02 +#define CMA_MB_PCI_IDSEL_GD82559 0x04 +#define CMA_MB_PCI_IDSEL_B69000 0x08 +#define CMA_MB_PCI_IDSEL_PD6832 0x10 + +/* PCI Interrupt Mask/Status register bits */ +#define CMA_MB_PCI_IMS_INTA 0x01 +#define CMA_MB_PCI_IMS_INTB 0x02 +#define CMA_MB_PCI_IMS_INTC 0x04 +#define CMA_MB_PCI_IMS_INTD 0x08 +#define CMA_MB_PCI_IMS_CBINT 0x10 +#define CMA_MB_PCI_IMS_V3LINT 0x80 + +#endif + +#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150) + +/* + * IREQ1 Interrupt Mask/Status register bits + * (Note: not available on CMA150 - must poll HT6542B interrupt register) + */ + +#define IREQ1_MINT 0x01 +#define IREQ1_KINT 0x02 +#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) +#define IREQ1_SINT2 0x04 +#define IREQ1_SINT3 0x08 +#endif + +#endif + +#ifndef __ASSEMBLY__ + +#ifdef USE_HOSTCC +#include /* avoid using private kernel header files */ +#else +#include /* use U-Boot provided headers */ +#endif + +/* a single CMA10x motherboard i/o register */ +typedef + struct { +#if __BYTE_ORDER == __LITTLE_ENDIAN + unsigned char value; +#endif + unsigned char filler[7]; +#if __BYTE_ORDER == __BIG_ENDIAN + unsigned char value; +#endif + } +cma_mb_reg; + +extern __inline__ unsigned char +cma_mb_reg_read(volatile cma_mb_reg *reg) +{ + unsigned char data = reg->value; + __asm__ __volatile__ ("eieio" : : : "memory"); + return data; +} + +extern __inline__ void +cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data) +{ + reg->value = data; + __asm__ __volatile__ ("eieio" : : : "memory"); +} + +#if (CMA_MB_CAPS & CMA_MB_CAP_RTC) + +/* MK48T02 RTC registers */ +typedef + struct { + cma_mb_reg sram[2040];/* Battery-Backed SRAM */ + cma_mb_reg clk_ctl; /* Clock Control Register */ + cma_mb_reg clk_sec; /* Clock Seconds Register */ + cma_mb_reg clk_min; /* Clock Minutes Register */ + cma_mb_reg clk_hour; /* Clock Hour Register */ + cma_mb_reg clk_day; /* Clock Day Register */ + cma_mb_reg clk_date; /* Clock Date Register */ + cma_mb_reg clk_month; /* Clock Month Register */ + cma_mb_reg clk_year; /* Clock Year Register */ + } +cma_mb_rtc; + +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) + +/* ST16C522 Serial I/O */ +typedef + struct { + cma_mb_reg ser_rhr; /* Receive Holding Register (R, DLAB=0) */ + cma_mb_reg ser_ier; /* Interrupt Enable Register (R/W, DLAB=0) */ + cma_mb_reg ser_isr; /* Interrupt Status Register (R) */ + cma_mb_reg ser_lcr; /* Line Control Register (R/W) */ + cma_mb_reg ser_mcr; /* Modem Control Register (R/W) */ + cma_mb_reg ser_lsr; /* Line Status Register (R) */ + cma_mb_reg ser_msr; /* Modem Status Register (R/W) */ + cma_mb_reg ser_spr; /* Scratch Pad Register (R/W) */ + } +cma_mb_serial; + +#define ser_thr ser_rhr /* Transmit Holding Register (W, DLAB=0) */ +#define ser_brl ser_rhr /* Baud Rate Divisor Low Byte (R/W, DLAB=1) */ +#define ser_brh ser_ier /* Baud Rate Divisor High Byte (R/W, DLAB=1) */ +#define ser_fcr ser_isr /* FIFO Control Register (W) */ +#define ser_nop ser_lsr /* No Operation (W) */ + +/* ST16C522 Parallel I/O */ +typedef + struct { + cma_mb_reg par_rdr; /* Port Read Data Register (R) */ + cma_mb_reg par_sr; /* Status Register (R) */ + cma_mb_reg par_cmd; /* Command Register (R) */ + } +cma_mb_parallel; + +#define par_wdr par_rdr /* Port Write Data Register (W) */ +#define par_ios par_sr /* I/O Select Register (W) */ +#define par_ctl par_cmd /* Control Register (W) */ + +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302) + +/* HT6542B PS/2 Keyboard/Mouse Controller */ +typedef + struct { + cma_mb_reg kbm_rdr; /* Read Data Register (R) */ + cma_mb_reg kbm_sr; /* Status Register (R) */ + } +cma_mb_kbm; + +#define kbm_wdr kbm_rdr /* Write Data Register (W) */ +#define kbm_cmd kbm_sr /* Command Register (W) */ + +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_LCD) + +/* HD44780 LCD Display */ +typedef + struct { + cma_mb_reg lcd_ccr; /* Current Character Register (R/W) */ + cma_mb_reg lcd_bsr; /* Busy Status Register (R) */ + } +cma_mb_lcd; + +#define lcd_cmd lcd_bsr /* Command Register (W) */ + +#endif + +/* 8-Position Configuration Switch */ +typedef + struct { + cma_mb_reg dip_val; /* Dip Switch value (R) */ + } +cma_mb_dipsw; + +#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) + +/* V360EPC PCI Bridge */ +typedef + struct { +#if __BYTE_ORDER == __LITTLE_ENDIAN + unsigned short v3_pci_vendor; /* 0x00 */ + unsigned short v3_pci_device; + unsigned short v3_pci_cmd; /* 0x04 */ + unsigned short v3_pci_stat; + unsigned long v3_pci_cc_rev; /* 0x08 */ + unsigned long v3_pci_hdr_cfg; /* 0x0c */ + unsigned long v3_pci_io_base; /* 0x10 */ + unsigned long v3_pci_base0; /* 0x14 */ + unsigned long v3_pci_base1; /* 0x18 */ + unsigned long reserved1[4]; /* 0x1c */ + unsigned short v3_pci_sub_vendor; /* 0x2c */ + unsigned short v3_pci_sub_id; + unsigned long v3_pci_rom; /* 0x30 */ + unsigned long reserved2[2]; /* 0x34 */ + unsigned long v3_pci_bparam; /* 0x3c */ + unsigned long v3_pci_map0; /* 0x40 */ + unsigned long v3_pci_map1; /* 0x44 */ + unsigned long v3_pci_int_stat; /* 0x48 */ + unsigned long v3_pci_int_cfg; /* 0x4c */ + unsigned long reserved3[1]; /* 0x50 */ + unsigned long v3_lb_base0; /* 0x54 */ + unsigned long v3_lb_base1; /* 0x58 */ + unsigned short reserved4; /* 0x5c */ + unsigned short v3_lb_map0; + unsigned short reserved5; /* 0x60 */ + unsigned short v3_lb_map1; + unsigned short v3_lb_base2; /* 0x64 */ + unsigned short v3_lb_map2; + unsigned long v3_lb_size; /* 0x68 */ + unsigned short reserved6; /* 0x6c */ + unsigned short v3_lb_io_base; + unsigned short v3_fifo_cfg; /* 0x70 */ + unsigned short v3_fifo_priority; + unsigned short v3_fifo_stat; /* 0x74 */ + unsigned char v3_lb_istat; + unsigned char v3_lb_imask; + unsigned short v3_system; /* 0x78 */ + unsigned short v3_lb_cfg; + unsigned short v3_pci_cfg; /* 0x7c */ + unsigned short reserved7; + unsigned long v3_dma_pci_addr0; /* 0x80 */ + unsigned long v3_dma_local_addr0; /* 0x84 */ + unsigned long v3_dma_length0:24; /* 0x88 */ + unsigned long v3_dma_csr0:8; + unsigned long v3_dma_ctlb_adr0; /* 0x8c */ + unsigned long v3_dma_pci_addr1; /* 0x90 */ + unsigned long v3_dma_local_addr1; /* 0x94 */ + unsigned long v3_dma_length1:24; /* 0x98 */ + unsigned long v3_dma_csr1:8; + unsigned long v3_dma_ctlb_adr1; /* 0x9c */ + unsigned long v3_i20_mups[8]; /* 0xa0 */ + unsigned char v3_mail_data0; /* 0xc0 */ + unsigned char v3_mail_data1; + unsigned char v3_mail_data2; + unsigned char v3_mail_data3; + unsigned char v3_mail_data4; /* 0xc4 */ + unsigned char v3_mail_data5; + unsigned char v3_mail_data6; + unsigned char v3_mail_data7; + unsigned char v3_mail_data8; /* 0xc8 */ + unsigned char v3_mail_data9; + unsigned char v3_mail_data10; + unsigned char v3_mail_data11; + unsigned char v3_mail_data12; /* 0xcc */ + unsigned char v3_mail_data13; + unsigned char v3_mail_data14; + unsigned char v3_mail_data15; + unsigned short v3_pci_mail_iewr; /* 0xd0 */ + unsigned short v3_pci_mail_ierd; + unsigned short v3_lb_mail_iewr; /* 0xd4 */ + unsigned short v3_lb_mail_ierd; + unsigned short v3_mail_wr_stat; /* 0xd8 */ + unsigned short v3_mail_rd_stat; + unsigned long v3_qba_map; /* 0xdc */ + unsigned long v3_dma_delay:8; /* 0xe0 */ + unsigned long reserved8:24; + unsigned long reserved9[7]; /* 0xe4 */ +#endif +#if __BYTE_ORDER == __BIG_ENDIAN + unsigned short v3_pci_device; /* 0x00 */ + unsigned short v3_pci_vendor; + unsigned short v3_pci_stat; /* 0x04 */ + unsigned short v3_pci_cmd; + unsigned long v3_pci_cc_rev; /* 0x08 */ + unsigned long v3_pci_hdr_cfg; /* 0x0c */ + unsigned long v3_pci_io_base; /* 0x10 */ + unsigned long v3_pci_base0; /* 0x14 */ + unsigned long v3_pci_base1; /* 0x18 */ + unsigned long reserved1[4]; /* 0x1c */ + unsigned short v3_pci_sub_id; /* 0x2c */ + unsigned short v3_pci_sub_vendor; + unsigned long v3_pci_rom; /* 0x30 */ + unsigned long reserved2[2]; /* 0x34 */ + unsigned long v3_pci_bparam; /* 0x3c */ + unsigned long v3_pci_map0; /* 0x40 */ + unsigned long v3_pci_map1; /* 0x44 */ + unsigned long v3_pci_int_stat; /* 0x48 */ + unsigned long v3_pci_int_cfg; /* 0x4c */ + unsigned long reserved3; /* 0x50 */ + unsigned long v3_lb_base0; /* 0x54 */ + unsigned long v3_lb_base1; /* 0x58 */ + unsigned short v3_lb_map0; /* 0x5c */ + unsigned short reserved4; + unsigned short v3_lb_map1; /* 0x60 */ + unsigned short reserved5; + unsigned short v3_lb_map2; /* 0x64 */ + unsigned short v3_lb_base2; + unsigned long v3_lb_size; /* 0x68 */ + unsigned short v3_lb_io_base; /* 0x6c */ + unsigned short reserved6; + unsigned short v3_fifo_priority; /* 0x70 */ + unsigned short v3_fifo_cfg; + unsigned char v3_lb_imask; /* 0x74 */ + unsigned char v3_lb_istat; + unsigned short v3_fifo_stat; + unsigned short v3_lb_cfg; /* 0x78 */ + unsigned short v3_system; + unsigned short reserved7; /* 0x7c */ + unsigned short v3_pci_cfg; + unsigned long v3_dma_pci_addr0; /* 0x80 */ + unsigned long v3_dma_local_addr0; /* 0x84 */ + unsigned long v3_dma_csr0:8; /* 0x88 */ + unsigned long v3_dma_length0:24; + unsigned long v3_dma_ctlb_adr0; /* 0x8c */ + unsigned long v3_dma_pci_addr1; /* 0x90 */ + unsigned long v3_dma_local_addr1; /* 0x94 */ + unsigned long v3_dma_csr1:8; /* 0x98 */ + unsigned long v3_dma_length1:24; + unsigned long v3_dma_ctlb_adr1; /* 0x9c */ + unsigned long v3_i20_mups[8]; /* 0xa0 */ + unsigned char v3_mail_data3; /* 0xc0 */ + unsigned char v3_mail_data2; + unsigned char v3_mail_data1; + unsigned char v3_mail_data0; + unsigned char v3_mail_data7; /* 0xc4 */ + unsigned char v3_mail_data6; + unsigned char v3_mail_data5; + unsigned char v3_mail_data4; + unsigned char v3_mail_data11; /* 0xc8 */ + unsigned char v3_mail_data10; + unsigned char v3_mail_data9; + unsigned char v3_mail_data8; + unsigned char v3_mail_data15; /* 0xcc */ + unsigned char v3_mail_data14; + unsigned char v3_mail_data13; + unsigned char v3_mail_data12; + unsigned short v3_pci_mail_ierd; /* 0xd0 */ + unsigned short v3_pci_mail_iewr; + unsigned short v3_lb_mail_ierd; /* 0xd4 */ + unsigned short v3_lb_mail_iewr; + unsigned short v3_mail_rd_stat; /* 0xd8 */ + unsigned short v3_mail_wr_stat; + unsigned long v3_qba_map; /* 0xdc */ + unsigned long reserved8:24; /* 0xe0 */ + unsigned long v3_dma_delay:8; + unsigned long reserved9[7]; /* 0xe4 */ +#endif + } /* 0x100 */ +cma_mb_v360epc; + +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* _COGENT_MB_H */ diff --git a/board/cogent/par.c b/board/cogent/par.c new file mode 100644 index 0000000..a03c0f1 --- /dev/null +++ b/board/cogent/par.c @@ -0,0 +1,3 @@ +/* parallel not implemented yet */ + +int cma_parallel_not_implemented = 1; diff --git a/board/cogent/par.h b/board/cogent/par.h new file mode 100644 index 0000000..664ae4a --- /dev/null +++ b/board/cogent/par.h @@ -0,0 +1,3 @@ +/* parallel not implemented yet */ + +extern int cma_parallel_not_implemented; diff --git a/board/cogent/pci.c b/board/cogent/pci.c new file mode 100644 index 0000000..0a57c0c --- /dev/null +++ b/board/cogent/pci.c @@ -0,0 +1,3 @@ +/* pci not implemented yet */ + +int cma_pci_not_implemented = 1; diff --git a/board/cogent/pci.h b/board/cogent/pci.h new file mode 100644 index 0000000..35aa354 --- /dev/null +++ b/board/cogent/pci.h @@ -0,0 +1,3 @@ +/* pci not implemented yet */ + +extern int cma_pci_not_implemented; diff --git a/board/cogent/rtc.c b/board/cogent/rtc.c new file mode 100644 index 0000000..ace9193 --- /dev/null +++ b/board/cogent/rtc.c @@ -0,0 +1,3 @@ +/* rtc not implemented yet */ + +int cma_rtc_not_implemented = 1; diff --git a/board/cogent/rtc.h b/board/cogent/rtc.h new file mode 100644 index 0000000..4b55bd2 --- /dev/null +++ b/board/cogent/rtc.h @@ -0,0 +1,3 @@ +/* rtc not implemented yet */ + +extern int cma_rtc_not_implemented; diff --git a/board/cogent/serial.c b/board/cogent/serial.c new file mode 100644 index 0000000..4c20017 --- /dev/null +++ b/board/cogent/serial.c @@ -0,0 +1,190 @@ +/* + * Simple serial driver for Cogent motherboard serial ports + * for use during boot + */ + +#include +#include + +#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) + +#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \ + (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE)) + +#if CONFIG_CONS_INDEX == 1 +#define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE +#elif CONFIG_CONS_INDEX == 2 +#define CMA_MB_SERIAL_BASE CMA_MB_SERIALB_BASE +#elif CONFIG_CONS_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) +#define CMA_MB_SERIAL_BASE CMA_MB_SER2A_BASE +#elif CONFIG_CONS_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) +#define CMA_MB_SERIAL_BASE CMA_MB_SER2B_BASE +#else +#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial +#endif + +int serial_init (void) +{ +/* DECLARE_GLOBAL_DATA_PTR; */ + + cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; + + cma_mb_reg_write(&mbsp->ser_ier, 0x00); /* turn off interrupts */ + serial_setbrg (); + cma_mb_reg_write(&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ + cma_mb_reg_write(&mbsp->ser_mcr, 0x03); /* RTS/DTR */ + cma_mb_reg_write(&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ + + return (0); +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; + unsigned int divisor; + unsigned char lcr; + + if ((divisor = br_to_div(gd->baudrate)) == 0) + divisor = DEFDIV; + + lcr = cma_mb_reg_read(&mbsp->ser_lcr); + cma_mb_reg_write(&mbsp->ser_lcr, lcr|0x80);/* Access baud rate(set DLAB)*/ + cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff); + cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff); + cma_mb_reg_write(&mbsp->ser_lcr, lcr); /* unset DLAB */ +} + +void +serial_putc(const char c) +{ + cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; + + if (c == '\n') + serial_putc('\r'); + + while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0) + ; + + cma_mb_reg_write(&mbsp->ser_thr, c); +} + +void +serial_puts(const char *s) +{ + while (*s != '\0') + serial_putc(*s++); +} + +int +serial_getc(void) +{ + cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; + + while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0) + ; + + return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f); +} + +int +serial_tstc(void) +{ + cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; + + return ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) != 0); +} + +#endif /* CONS_NONE */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && \ + defined(CONFIG_KGDB_NONE) + +#if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX +#error Console and kgdb are on the same serial port - this is not supported +#endif + +#if CONFIG_KGDB_INDEX == 1 +#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALA_BASE +#elif CONFIG_KGDB_INDEX == 2 +#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALB_BASE +#elif CONFIG_KGDB_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) +#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2A_BASE +#elif CONFIG_KGDB_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) +#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2B_BASE +#else +#error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial +#endif + +void +kgdb_serial_init(void) +{ + cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; + unsigned int divisor; + + if ((divisor = br_to_div(CONFIG_KGDB_BAUDRATE)) == 0) + divisor = DEFDIV; + + cma_mb_reg_write(&mbsp->ser_ier, 0x00); /* turn off interrupts */ + cma_mb_reg_write(&mbsp->ser_lcr, 0x80); /* Access baud rate(set DLAB)*/ + cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff); + cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff); + cma_mb_reg_write(&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ + cma_mb_reg_write(&mbsp->ser_mcr, 0x03); /* RTS/DTR */ + cma_mb_reg_write(&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ + + printf("[on cma10x serial port B] "); +} + +void +putDebugChar(int c) +{ + cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; + + while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0) + ; + + cma_mb_reg_write(&mbsp->ser_thr, c & 0xff); +} + +void +putDebugStr(const char *str) +{ + while (*str != '\0') { + if (*str == '\n') + putDebugChar('\r'); + putDebugChar(*str++); + } +} + +int +getDebugChar(void) +{ + cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; + + while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0) + ; + + return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f); +} + +void +kgdb_interruptible(int yes) +{ + cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; + + if (yes == 1) { + printf("kgdb: turning serial ints on\n"); + cma_mb_reg_write(&mbsp->ser_ier, 0xf); + } + else { + printf("kgdb: turning serial ints off\n"); + cma_mb_reg_write(&mbsp->ser_ier, 0x0); + } +} + +#endif /* KGDB && KGDB_NONE */ + +#endif /* CAPS & SERPAR */ diff --git a/board/cogent/serial.h b/board/cogent/serial.h new file mode 100644 index 0000000..89962d8 --- /dev/null +++ b/board/cogent/serial.h @@ -0,0 +1,15 @@ +/* Line Status Register bits */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +#define CLKRATE 3686400 /* cogent motherboard serial clk = 3.6864MHz */ +#define DEFDIV 1 /* default to 230400 bps */ + +#define br_to_div(br) (CLKRATE / (16 * (br))) +#define div_to_br(div) (CLKRATE / (16 * (div))) diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds new file mode 100644 index 0000000..5ce2694 --- /dev/null +++ b/board/cogent/u-boot.lds @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug new file mode 100644 index 0000000..ddd4678 --- /dev/null +++ b/board/cogent/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile new file mode 100644 index 0000000..ccb811b --- /dev/null +++ b/board/cpc45/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o plx9030.o pd67290.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cpc45/config.mk b/board/cpc45/config.mk new file mode 100644 index 0000000..bf9d9de --- /dev/null +++ b/board/cpc45/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2001-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# CPC45 board +# + + +ifeq ($(CONFIG_BOOT_ROM),y) + TEXT_BASE := 0xFFF00000 + PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM +else + TEXT_BASE := 0xFFF00000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c new file mode 100644 index 0000000..51b0085 --- /dev/null +++ b/board/cpc45/cpc45.c @@ -0,0 +1,275 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +int sysControlDisplay(int digit, uchar ascii_code); +extern void Plx9030Init(void); +extern void SPD67290Init(void); + + /* We have to clear the initial data area here. Couldn't have done it + * earlier because DRAM had not been initialized. + */ +int board_early_init_f(void) +{ + + /* enable DUAL UART Mode on CPC45 */ + *(uchar*)DUART_DCR |= 0x1; /* set DCM bit */ + + return 0; +} + +int checkboard(void) +{ +/* + char revision = BOARD_REV; +*/ + ulong busfreq = get_bus_freq(0); + char buf[32]; + + puts ("CPC45 "); +/* + printf("Revision %d ", revision); +*/ + printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); + + return 0; +} + +long int initdram (int board_type) +{ + int m, row, col, bank, i, ref; + unsigned long start, end; + uint32_t mccr1, mccr2; + uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; + uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; + uint8_t mber = 0; + unsigned int tmp; + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + if (i2c_reg_read (0x50, 2) != 0x04) + return 0; /* Memory type */ + + m = i2c_reg_read (0x50, 5); /* # of physical banks */ + row = i2c_reg_read (0x50, 3); /* # of rows */ + col = i2c_reg_read (0x50, 4); /* # of columns */ + bank = i2c_reg_read (0x50, 17); /* # of logical banks */ + ref = i2c_reg_read (0x50, 12); /* refresh rate / type */ + + CONFIG_READ_WORD(MCCR1, mccr1); + mccr1 &= 0xffff0000; + + CONFIG_READ_WORD(MCCR2, mccr2); + mccr2 &= 0xffff0000; + + start = CFG_SDRAM_BASE; + end = start + (1 << (col + row + 3) ) * bank - 1; + + for (i = 0; i < m; i++) { + mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; + if (i < 4) { + msar1 |= ((start >> 20) & 0xff) << i * 8; + emsar1 |= ((start >> 28) & 0xff) << i * 8; + mear1 |= ((end >> 20) & 0xff) << i * 8; + emear1 |= ((end >> 28) & 0xff) << i * 8; + } else { + msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; + emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; + mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; + emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; + } + mber |= 1 << i; + start += (1 << (col + row + 3) ) * bank; + end += (1 << (col + row + 3) ) * bank; + } + for (; i < 8; i++) { + if (i < 4) { + msar1 |= 0xff << i * 8; + emsar1 |= 0x30 << i * 8; + mear1 |= 0xff << i * 8; + emear1 |= 0x30 << i * 8; + } else { + msar2 |= 0xff << (i-4) * 8; + emsar2 |= 0x30 << (i-4) * 8; + mear2 |= 0xff << (i-4) * 8; + emear2 |= 0x30 << (i-4) * 8; + } + } + + switch(ref) { + case 0x00: + case 0x80: + tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22; + break; + case 0x01: + case 0x81: + tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22; + break; + case 0x02: + case 0x82: + tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22; + break; + case 0x03: + case 0x83: + tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22; + break; + case 0x04: + case 0x84: + tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22; + break; + case 0x05: + case 0x85: + tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22; + break; + default: + tmp = 0x512; + break; + } + + CONFIG_WRITE_WORD(MCCR1, mccr1); + CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT); + CONFIG_WRITE_WORD(MSAR1, msar1); + CONFIG_WRITE_WORD(EMSAR1, emsar1); + CONFIG_WRITE_WORD(MEAR1, mear1); + CONFIG_WRITE_WORD(EMEAR1, emear1); + CONFIG_WRITE_WORD(MSAR2, msar2); + CONFIG_WRITE_WORD(EMSAR2, emsar2); + CONFIG_WRITE_WORD(MEAR2, mear2); + CONFIG_WRITE_WORD(EMEAR2, emear2); + CONFIG_WRITE_BYTE(MBER, mber); + + return (1 << (col + row + 3) ) * bank * m; +} + + +/* + * Initialize PCI Devices, report devices found. + */ + +static struct pci_config_table pci_cpc45_config_table[] = { +#ifndef CONFIG_PCI_PNP + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR, + PCI_PLX9030_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCMCIA_IO_BASE, + PCMCIA_IO_BASE, + PCI_COMMAND_MEMORY | PCI_COMMAND_IO }}, +#endif /*CONFIG_PCI_PNP*/ + { } +}; + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_cpc45_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); + + /* init PCI_to_LOCAL Bus BRIDGE */ + Plx9030Init(); + + /* Clear Display */ + DISP_CWORD = 0x0; + + sysControlDisplay(0,' '); + sysControlDisplay(1,'C'); + sysControlDisplay(2,'P'); + sysControlDisplay(3,'C'); + sysControlDisplay(4,' '); + sysControlDisplay(5,'4'); + sysControlDisplay(6,'5'); + sysControlDisplay(7,' '); + +} + +/************************************************************************** +* +* sysControlDisplay - controls one of the Alphanum. Display digits. +* +* This routine will write an ASCII character to the display digit requested. +* +* SEE ALSO: +* +* RETURNS: NA +*/ + +int sysControlDisplay (int digit, /* number of digit 0..7 */ + uchar ascii_code /* ASCII code */ + ) +{ + if ((digit < 0) || (digit > 7)) + return (-1); + + *((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code; + + return (0); +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) + +#ifdef CFG_PCMCIA_MEM_ADDR +volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; +#endif + +int pcmcia_init(void) +{ + u_int rc; + + debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + rc = i82365_init(); + + return rc; +} + +#endif /* CFG_CMD_PCMCIA */ + +# ifdef CONFIG_IDE_LED +void ide_led (uchar led, uchar status) +{ + u_char val; + /* We have one PCMCIA slot and use LED H4 for the IDE Interface */ + val = readb(BCSR_BASE + 0x04); + if (status) { /* led on */ + val |= B_CTRL_LED0; + } else { + val &= ~B_CTRL_LED0; + } + writeb(val, BCSR_BASE + 0x04); +} +# endif diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c new file mode 100644 index 0000000..37dd182 --- /dev/null +++ b/board/cpc45/flash.c @@ -0,0 +1,522 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#define FLASH_BANK_SIZE 0x800000 +#define MAIN_SECT_SIZE 0x40000 +#define PARAM_SECT_SIZE 0x8000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static int write_data (flash_info_t * info, ulong dest, ulong * data); +static void write_via_fpu (vu_long * addr, ulong * data); +static __inline__ unsigned long get_msr (void); +static __inline__ void set_msr (unsigned long msr); + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +/*---------------------------------------------------------------------*/ +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i, j; + ulong size = 0; + uchar tempChar; + vu_long *tmpaddr; + + /* Enable flash writes on CPC45 */ + + tempChar = BOARD_CTRL; + + tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1); + + tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0); + + BOARD_CTRL = tempChar; + + __asm__ volatile ("sync\n eieio"); + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + + addr[0] = 0x00900090; + + __asm__ volatile ("sync\n eieio"); + + udelay (100); + + DEBUGF ("Flash bank # %d:\n" + "\tManuf. ID @ 0x%08lX: 0x%08lX\n" + "\tDevice ID @ 0x%08lX: 0x%08lX\n", + i, + (ulong) (&addr[0]), addr[0], + (ulong) (&addr[2]), addr[2]); + + + if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && + (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) { + + flash_info[i].flash_id = + (FLASH_MAN_INTEL & FLASH_VENDMASK) | + (INTEL_ID_28F160F3T & FLASH_TYPEMASK); + + } else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) + && (addr[2] == addr[3]) + && (addr[2] == INTEL_ID_28F160C3T)) { + + flash_info[i].flash_id = + (FLASH_MAN_INTEL & FLASH_VENDMASK) | + (INTEL_ID_28F160C3T & FLASH_TYPEMASK); + + } else { + flash_info[i].flash_id = FLASH_UNKNOWN; + addr[0] = 0xFFFFFFFF; + goto Done; + } + + DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); + + addr[0] = 0xFFFFFFFF; + + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j > 30) { + flash_info[i].start[j] = CFG_FLASH_BASE + + i * FLASH_BANK_SIZE + + (MAIN_SECT_SIZE * 31) + (j - + 31) * + PARAM_SECT_SIZE; + } else { + flash_info[i].start[j] = CFG_FLASH_BASE + + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE; + } + } + + /* unlock sectors, if 160C3T */ + + for (j = 0; j < flash_info[i].sector_count; j++) { + tmpaddr = (vu_long *) flash_info[i].start[j]; + + if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) { + tmpaddr[0] = 0x00600060; + tmpaddr[0] = 0x00D000D0; + tmpaddr[1] = 0x00600060; + tmpaddr[1] = 0x00D000D0; + } + } + + size += flash_info[i].size; + + addr[0] = 0x00FF00FF; + addr[1] = 0x00FF00FF; + } + + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[1]); +#else + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); +#else + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif +#endif + +Done: + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch ((i = info->flash_id & FLASH_VENDMASK)) { + case (FLASH_MAN_INTEL & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor 0x%04x ", i); + break; + } + + switch ((i = info->flash_id & FLASH_TYPEMASK)) { + case (INTEL_ID_28F160F3T & FLASH_TYPEMASK): + printf ("28F160F3T (16Mbit)\n"); + break; + + case (INTEL_ID_28F160C3T & FLASH_TYPEMASK): + printf ("28F160C3T (16Mbit)\n"); + break; + + default: + printf ("Unknown Chip Type 0x%04x\n", i); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: + return; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + DEBUGF ("Erase flash bank %d sect %d ... %d\n", + info - &flash_info[0], s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (FLASH_MAN_INTEL & FLASH_VENDMASK)) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *) (info->start[sect]); + + DEBUGF ("Erase sect %d @ 0x%08lX\n", + sect, (ulong) addr); + + /* Disable interrupts which might cause a timeout + * here. + */ + flag = disable_interrupts (); + + addr[0] = 0x00500050; /* clear status register */ + addr[0] = 0x00200020; /* erase setup */ + addr[0] = 0x00D000D0; /* erase confirm */ + + addr[1] = 0x00500050; /* clear status register */ + addr[1] = 0x00200020; /* erase setup */ + addr[1] = 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((addr[0] & 0x00800080) != 0x00800080) || + ((addr[1] & 0x00800080) != 0x00800080)) { + if ((now = get_timer (start)) > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + addr[0] = 0x00B000B0; /* suspend erase */ + addr[0] = 0x00FF00FF; /* to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + addr[0] = 0x00FF00FF; + } + } + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 8 /* flash bus width in bytes */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, cp, msr; + int l, rc, i; + ulong data[2]; + ulong *datah = &data[0]; + ulong *datal = &data[1]; + + DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", + addr, (ulong) src, cnt); + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + msr = get_msr (); + set_msr (msr | MSR_FP); + + wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + *datah = *datal = 0; + + for (i = 0, cp = wp; i < l; i++, cp++) { + if (i >= 4) { + *datah = (*datah << 8) | + ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | (*(uchar *) cp); + } + for (; i < FLASH_WIDTH && cnt > 0; ++i) { + char tmp = *src++; + + if (i >= 4) { + *datah = (*datah << 8) | + ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | tmp; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { + if (i >= 4) { + *datah = (*datah << 8) | + ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datah << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, data)) != 0) { + set_msr (msr); + return (rc); + } + + wp += FLASH_WIDTH; + } + + /* + * handle FLASH_WIDTH aligned part + */ + while (cnt >= FLASH_WIDTH) { + *datah = *(ulong *) src; + *datal = *(ulong *) (src + 4); + if ((rc = write_data (info, wp, data)) != 0) { + set_msr (msr); + return (rc); + } + wp += FLASH_WIDTH; + cnt -= FLASH_WIDTH; + src += FLASH_WIDTH; + } + + if (cnt == 0) { + set_msr (msr); + return (0); + } + + /* + * handle unaligned tail bytes + */ + *datah = *datal = 0; + for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { + char tmp = *src++; + + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> + 24); + } + + *datal = (*datal << 8) | tmp; + --cnt; + } + + for (; i < FLASH_WIDTH; ++i, ++cp) { + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> + 24); + } + + *datal = (*datal << 8) | (*(uchar *) cp); + } + + rc = write_data (info, wp, data); + set_msr (msr); + + return (rc); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, ulong * data) +{ + vu_long *addr = (vu_long *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if (((addr[0] & data[0]) != data[0]) || + ((addr[1] & data[1]) != data[1])) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr[0] = 0x00400040; /* write setup */ + write_via_fpu (addr, data); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + + while (((addr[0] & 0x00800080) != 0x00800080) || + ((addr[1] & 0x00800080) != 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + addr[0] = 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + addr[0] = 0x00FF00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + */ +static void write_via_fpu (vu_long * addr, ulong * data) +{ + __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); + __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); +} + +/*----------------------------------------------------------------------- + */ +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + return msr; +} + +static __inline__ void set_msr (unsigned long msr) +{ + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); +} diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c new file mode 100644 index 0000000..c84fbae --- /dev/null +++ b/board/cpc45/pd67290.c @@ -0,0 +1,68 @@ +/* pd67290.c - system configuration module for SPD67290 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * (C) 2004 DENX Software Engineering, Heiko Schocher + */ + +#include +#include +#include +#include +#include + +/* imports */ +#include + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729}, + {} +}; + +/*************************************************************************** +* +* SPD67290Init - +* +* RETURNS: -1 on error, 0 if OK +*/ + +int SPD67290Init (void) +{ + pci_dev_t devno; + int idx = 0; /* general index */ + ulong membaseCsr; /* base address of device memory space */ + + /* find PD67290 device */ + if ((devno = pci_find_devices (supported, idx++)) < 0) { + printf ("No PD67290 device found !!\n"); + return -1; + } + /* - 0xfe000000 see MPC 8245 Users Manual Adress Map B */ + membaseCsr = PCMCIA_IO_BASE - 0xfe000000; + + /* set base address */ + pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, membaseCsr); + + /* enable mapped memory and IO addresses */ + pci_write_config_dword (devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | + PCI_COMMAND_IO | PCI_COMMAND_WAIT); + return 0; +} diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c new file mode 100644 index 0000000..99ec39a --- /dev/null +++ b/board/cpc45/plx9030.c @@ -0,0 +1,173 @@ +/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */ +/* + * (C) Copyright 2002-2003 + * Josef Wagner, MicroSys GmbH, wagner@microsys.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Date Modification by + * ------- ---------------------------------------------- --- + * 30sep02 converted from VxWorks to LINUX wa +*/ + + +/* +DESCRIPTION + +This is the configuration module for the PLX9030 PCI to Local Bus Bridge. +It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local +registers (CS3) on CPC45. +*/ + +/* includes */ + +#include +#include +#include +#include +#include + +/* imports */ + + +/* defines */ +#define PLX9030_VENDOR_ID 0x10B5 +#define PLX9030_DEVICE_ID 0x9030 + +#undef PLX_DEBUG + +/* PLX9030 register offsets */ +#define P9030_LAS0RR 0x00 +#define P9030_LAS1RR 0x04 +#define P9030_LAS2RR 0x08 +#define P9030_LAS3RR 0x0c +#define P9030_EROMRR 0x10 +#define P9030_LAS0BA 0x14 +#define P9030_LAS1BA 0x18 +#define P9030_LAS2BA 0x1c +#define P9030_LAS3BA 0x20 +#define P9030_EROMBA 0x24 +#define P9030_LAS0BRD 0x28 +#define P9030_LAS1BRD 0x2c +#define P9030_LAS2BRD 0x30 +#define P9030_LAS3BRD 0x34 +#define P9030_EROMBRD 0x38 +#define P9030_CS0BASE 0x3C +#define P9030_CS1BASE 0x40 +#define P9030_CS2BASE 0x44 +#define P9030_CS3BASE 0x48 +#define P9030_INTCSR 0x4c +#define P9030_CNTRL 0x50 +#define P9030_GPIOC 0x54 + +/* typedefs */ + + +/* locals */ + +static struct pci_device_id supported[] = { + { PLX9030_VENDOR_ID, PLX9030_DEVICE_ID }, + { } +}; + +/* forward declarations */ +void sysOutLong(ulong address, ulong value); + + +/*************************************************************************** +* +* Plx9030Init - init CS0..CS3 for CPC45 +* +* +* RETURNS: N/A +*/ + +void Plx9030Init (void) +{ + pci_dev_t devno; + ulong membaseCsr; /* base address of device memory space */ + int idx = 0; /* general index */ + + + /* find plx9030 device */ + + if ((devno = pci_find_devices(supported, idx++)) < 0) + { + printf("No PLX9030 device found !!\n"); + return; + } + + +#ifdef PLX_DEBUG + printf("PLX 9030 device found ! devno = 0x%x\n",devno); +#endif + + membaseCsr = PCI_PLX9030_MEMADDR; + + /* set base address */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr); + + /* enable mapped memory and IO addresses */ + pci_write_config_dword(devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + + + /* configure GBIOC */ + sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */ + + /* configure CS0 (SRAM) */ + sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */ + sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */ + sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */ + sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */ + /* remap CS0 (SRAM) */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE); + + /* configure CS1 (ST16552 / CHAN A) */ + sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */ + sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */ + sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */ + sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */ + /* remap CS1 (ST16552 / CHAN A) */ + /* remap CS1 (ST16552 / CHAN A) */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE); + + /* configure CS2 (ST16552 / CHAN B) */ + sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */ + sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */ + sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */ + sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */ + /* remap CS2 (ST16552 / CHAN B) */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE); + + /* configure CS3 (BCSR) */ + sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */ + sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */ + sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */ + sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */ + /* remap CS3 (DISPLAY and BCSR) */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE); +} + +void sysOutLong(ulong address, ulong value) +{ + *(ulong*)address = cpu_to_le32(value); +} diff --git a/board/cpc45/u-boot.lds b/board/cpc45/u-boot.lds new file mode 100644 index 0000000..9ea26aa --- /dev/null +++ b/board/cpc45/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cpu86/Makefile b/board/cpu86/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/cpu86/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cpu86/config.mk b/board/cpu86/config.mk new file mode 100644 index 0000000..00354c4 --- /dev/null +++ b/board/cpu86/config.mk @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# CPU86 boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_CPU86.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# + +ifeq ($(CONFIG_BOOT_ROM),y) + TEXT_BASE := 0xFF800000 + PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM +else + TEXT_BASE := 0xFF000000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c new file mode 100644 index 0000000..3eb5b35 --- /dev/null +++ b/board/cpu86/cpu86.c @@ -0,0 +1,321 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "cpu86.h" + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ + /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ + /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ + /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ + /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ + /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ + /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ + /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ + /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ + /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ + /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ + /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ + /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + ulong size8, size9; +#endif + long psize; + + psize = 32 * 1024 * 1024; + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CFG_PSRT; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL) "); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL) "); + } + +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h new file mode 100644 index 0000000..cf7852c --- /dev/null +++ b/board/cpu86/cpu86.h @@ -0,0 +1,27 @@ +#ifndef __BOARD_CPU86__ +#define __BOARD_CPU86__ + +#include + +#define REG8(x) (*(volatile unsigned char *)(x)) + +/* CPU86 register definitions */ +#define CPU86_VME_EAC REG8(CFG_BCRS_BASE + 0x00) +#define CPU86_VME_SAC REG8(CFG_BCRS_BASE + 0x01) +#define CPU86_VME_MAC REG8(CFG_BCRS_BASE + 0x02) +#define CPU86_BCR REG8(CFG_BCRS_BASE + 0x03) +#define CPU86_BSR REG8(CFG_BCRS_BASE + 0x04) +#define CPU86_WDOG_RPORT REG8(CFG_BCRS_BASE + 0x05) +#define CPU86_MBOX_IRQ REG8(CFG_BCRS_BASE + 0x04) +#define CPU86_REV REG8(CFG_BCRS_BASE + 0x07) +#define CPU86_VME_IRQMASK REG8(CFG_BCRS_BASE + 0x80) +#define CPU86_VME_IRQSTATUS REG8(CFG_BCRS_BASE + 0x81) +#define CPU86_LOCAL_IRQMASK REG8(CFG_BCRS_BASE + 0x82) +#define CPU86_LOCAL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x83) +#define CPU86_PMCL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x84) + +/* Board Control Register bits */ +#define CPU86_BCR_FWPT 0x01 +#define CPU86_BCR_FWRE 0x02 + +#endif /* __BOARD_CPU86__ */ diff --git a/board/cpu86/flash.c b/board/cpu86/flash.c new file mode 100644 index 0000000..1535a6b --- /dev/null +++ b/board/cpu86/flash.c @@ -0,0 +1,615 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for Intel devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "cpu86.h" + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + */ +ulong flash_int_get_size (volatile unsigned long *baseaddr, + flash_info_t * info) +{ + short i; + unsigned long flashtest_h, flashtest_l; + + info->sector_count = info->size = 0; + info->flash_id = FLASH_UNKNOWN; + + /* Write identify command sequence and test FLASH answer + */ + baseaddr[0] = 0x00900090; + baseaddr[1] = 0x00900090; + + flashtest_h = baseaddr[0]; /* manufacturer ID */ + flashtest_l = baseaddr[1]; + + if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) + return (0); /* no or unknown flash */ + + flashtest_h = baseaddr[2]; /* device ID */ + flashtest_l = baseaddr[3]; + + if (flashtest_h != flashtest_l) + return (0); + + switch (flashtest_h) { + case INTEL_ID_28F160C3B: + info->flash_id = FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + case INTEL_ID_28F160F3B: + info->flash_id = FLASH_28F160F3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + default: + return (0); /* no or unknown flash */ + } + + info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ + + if (info->flash_id & FLASH_BTYPE) { + volatile unsigned long *tmp = baseaddr; + + /* set up sector start adress table (bottom sector type) + * AND unlock the sectors (if our chip is 160C3) + */ + for (i = 0; i < info->sector_count; i++) { + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) { + tmp[0] = 0x00600060; + tmp[1] = 0x00600060; + tmp[0] = 0x00D000D0; + tmp[1] = 0x00D000D0; + } + info->start[i] = (uint) tmp; + tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ + } + } + + memset (info->protect, 0, info->sector_count); + + baseaddr[0] = 0x00FF00FF; + baseaddr[1] = 0x00FF00FF; + + return (info->size); +} + +static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info) +{ + short i; + uchar vendor, devid; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x90; + + udelay(1000); + + vendor = addr[0]; + devid = addr[1] & 0xff; + + /* only support AMD */ + if (vendor != 0x01) { + return 0; + } + + vendor &= 0xf; + devid &= 0xff; + + if (devid == AMD_ID_F040B) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 8; + info->size = info->sector_count * 0x10000; + } + else if (devid == AMD_ID_F080B) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 16; + info->size = 4 * info->sector_count * 0x10000; + } + else if (devid == AMD_ID_F016D) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 32; + info->size = 4 * info->sector_count * 0x10000; + } + else { + printf ("## Unknown Flash Type: %02x\n", devid); + return 0; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* sector base address */ + info->start[i] = base + i * (info->size / info->sector_count); + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + unsigned long size_b1 = 0; + int i; + + /* Init: no FLASHes known + */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Disable flash protection */ + CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE); + + /* Static FLASH Bank configuration here (only one bank) */ + + size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]); + size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]); + + if (size_b0 > 0 || size_b1 > 0) { + + printf("("); + + if (size_b0 > 0) { + puts ("Bank#1 - "); + print_size (size_b0, (size_b1 > 0) ? ", " : ") "); + } + + if (size_b1 > 0) { + puts ("Bank#2 - "); + print_size (size_b1, ") "); + } + } + else { + printf ("## No FLASH found.\n"); + return 0; + } + /* protect monitor and environment sectors + */ + +#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE + if (size_b1) { + /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE + * but we shouldn't protect it. + */ + + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] + ); + } +#else +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] + ); +#endif +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE + if (size_b1) { + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); + } +# else + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +# endif +#endif + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case 0x89: + printf ("INTEL "); + break; + case 0x1: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + printf ("28F160C3B (16 Mbit, bottom sector)\n"); + break; + case FLASH_28F160F3B: + printf ("28F160F3B (16 Mbit, bottom sector)\n"); + break; + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + if (info->size < 0x100000) + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + else + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Check the type of erased flash + */ + if (info->flash_id >> 16 == 0x1) { + /* Erase AMD flash + */ + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *)(info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto AMD_DONE; + + start = get_timer (0); + last = start; + addr = (vu_char *)(info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +AMD_DONE: + /* reset to read mode */ + addr = (volatile unsigned char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + } else { + /* Erase Intel flash + */ + + /* Start erase on unprotected sectors + */ + for (sect = s_first; sect <= s_last; sect++) { + volatile ulong *addr = + (volatile unsigned long *) info->start[sect]; + + start = get_timer (0); + last = start; + if (info->protect[sect] == 0) { + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + /* Erase the block + */ + addr[0] = 0x00200020; + addr[1] = 0x00200020; + addr[0] = 0x00D000D0; + addr[1] = 0x00D000D0; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms + */ + udelay (1000); + + last = start; + while ((addr[0] & 0x00800080) != 0x00800080 || + (addr[1] & 0x00800080) != 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout (erase suspended!)\n"); + /* Suspend erase + */ + addr[0] = 0x00B000B0; + addr[1] = 0x00B000B0; + goto DONE; + } + /* show that we're waiting + */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { + printf ("*** ERROR: erase failed!\n"); + goto DONE; + } + } + /* Clear status register and reset to read mode + */ + addr[0] = 0x00500050; + addr[1] = 0x00500050; + addr[0] = 0x00FF00FF; + addr[1] = 0x00FF00FF; + } + } + + printf (" done\n"); + +DONE: + return 0; +} + +static int write_word (flash_info_t *, volatile unsigned long *, ulong); +static int write_byte (flash_info_t *info, ulong dest, uchar data); + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong v; + int i, l, rc, cc = cnt, res = 0; + + if (info->flash_id >> 16 == 0x1) { + + /* Write to AMD 8-bit flash + */ + while (cnt > 0) { + if ((rc = write_byte(info, addr, *src)) != 0) { + return (rc); + } + addr++; + src++; + cnt--; + } + + return (0); + } else { + + /* Write to Intel 64-bit flash + */ + for (v=0; cc > 0; addr += 4, cc -= 4 - l) { + l = (addr & 3); + addr &= ~3; + + for (i = 0; i < 4; i++) { + v = (v << 8) + (i < l || i - l >= cc ? + *((unsigned char *) addr + i) : *src++); + } + + if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, volatile unsigned long *addr, + ulong data) +{ + int flag, res = 0; + ulong start; + + /* Check if Flash is (sufficiently) erased + */ + if ((*addr & data) != data) + return (2); + + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + *addr = 0x00400040; + *addr = data; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + while ((*addr & 0x00800080) != 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + /* Suspend program + */ + *addr = 0x00B000B0; + res = 1; + goto OUT; + } + } + + if (*addr & 0x00220022) { + printf ("*** ERROR: program failed!\n"); + res = 1; + } + +OUT: + /* Clear status register and reset to read mode + */ + *addr = 0x00500050; + *addr = 0x00FF00FF; + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a byte to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte (flash_info_t *info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((vu_char *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/cpu86/u-boot.lds b/board/cpu86/u-boot.lds new file mode 100644 index 0000000..05f29c6 --- /dev/null +++ b/board/cpu86/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cpu87/Makefile b/board/cpu87/Makefile new file mode 100644 index 0000000..26f53ed --- /dev/null +++ b/board/cpu87/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cpu87/config.mk b/board/cpu87/config.mk new file mode 100644 index 0000000..6384c78 --- /dev/null +++ b/board/cpu87/config.mk @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# CPU87 board +# + +# This should be equal to the CFG_FLASH_BASE define in configs/cpu87.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# + +ifeq ($(CONFIG_BOOT_ROM),y) + TEXT_BASE := 0xFF800000 + PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM +else + TEXT_BASE := 0xFF000000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c new file mode 100644 index 0000000..8363d86 --- /dev/null +++ b/board/cpu87/cpu87.c @@ -0,0 +1,333 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "cpu87.h" +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ + /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ + /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ + /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ + /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ + /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ + /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ + /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ + /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ + /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ + /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ + /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ + /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + ulong size8, size9; +#endif + long psize; + + psize = 32 * 1024 * 1024; + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CFG_PSRT; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL) "); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL) "); + } + +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/cpu87/cpu87.h b/board/cpu87/cpu87.h new file mode 100644 index 0000000..5dbd4ae --- /dev/null +++ b/board/cpu87/cpu87.h @@ -0,0 +1,27 @@ +#ifndef __BOARD_CPU87__ +#define __BOARD_CPU87__ + +#include + +#define REG8(x) (*(volatile unsigned char *)(x)) + +/* CPU86 register definitions */ +#define CPU86_VME_EAC REG8(CFG_BCRS_BASE + 0x00) +#define CPU86_VME_SAC REG8(CFG_BCRS_BASE + 0x01) +#define CPU86_VME_MAC REG8(CFG_BCRS_BASE + 0x02) +#define CPU86_BCR REG8(CFG_BCRS_BASE + 0x03) +#define CPU86_BSR REG8(CFG_BCRS_BASE + 0x04) +#define CPU86_WDOG_RPORT REG8(CFG_BCRS_BASE + 0x05) +#define CPU86_MBOX_IRQ REG8(CFG_BCRS_BASE + 0x04) +#define CPU86_REV REG8(CFG_BCRS_BASE + 0x07) +#define CPU86_VME_IRQMASK REG8(CFG_BCRS_BASE + 0x80) +#define CPU86_VME_IRQSTATUS REG8(CFG_BCRS_BASE + 0x81) +#define CPU86_LOCAL_IRQMASK REG8(CFG_BCRS_BASE + 0x82) +#define CPU86_LOCAL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x83) +#define CPU86_PMCL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x84) + +/* Board Control Register bits */ +#define CPU86_BCR_FWPT 0x01 +#define CPU86_BCR_FWRE 0x02 + +#endif /* __BOARD_CPU87__ */ diff --git a/board/cpu87/flash.c b/board/cpu87/flash.c new file mode 100644 index 0000000..076c2f9 --- /dev/null +++ b/board/cpu87/flash.c @@ -0,0 +1,624 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for Intel devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "cpu87.h" + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + */ +ulong flash_int_get_size (volatile unsigned long *baseaddr, + flash_info_t * info) +{ + short i; + unsigned long flashtest_h, flashtest_l; + + info->sector_count = info->size = 0; + info->flash_id = FLASH_UNKNOWN; + + /* Write identify command sequence and test FLASH answer + */ + baseaddr[0] = 0x00900090; + baseaddr[1] = 0x00900090; + + flashtest_h = baseaddr[0]; /* manufacturer ID */ + flashtest_l = baseaddr[1]; + + if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) + return (0); /* no or unknown flash */ + + flashtest_h = baseaddr[2]; /* device ID */ + flashtest_l = baseaddr[3]; + + if (flashtest_h != flashtest_l) + return (0); + + switch (flashtest_h) { + case INTEL_ID_28F160C3B: + info->flash_id = FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + case INTEL_ID_28F160F3B: + info->flash_id = FLASH_28F160F3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + case INTEL_ID_28F640C3B: + info->flash_id = FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ + break; + default: + return (0); /* no or unknown flash */ + } + + info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ + + if (info->flash_id & FLASH_BTYPE) { + volatile unsigned long *tmp = baseaddr; + + /* set up sector start adress table (bottom sector type) + * AND unlock the sectors (if our chip is 160C3) + */ + for (i = 0; i < info->sector_count; i++) { + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { + tmp[0] = 0x00600060; + tmp[1] = 0x00600060; + tmp[0] = 0x00D000D0; + tmp[1] = 0x00D000D0; + } + info->start[i] = (uint) tmp; + tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ + } + } + + memset (info->protect, 0, info->sector_count); + + baseaddr[0] = 0x00FF00FF; + baseaddr[1] = 0x00FF00FF; + + return (info->size); +} + +static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info) +{ + short i; + uchar vendor, devid; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x90; + + udelay(1000); + + vendor = addr[0]; + devid = addr[1] & 0xff; + + /* only support AMD */ + if (vendor != 0x01) { + return 0; + } + + vendor &= 0xf; + devid &= 0xff; + + if (devid == AMD_ID_F040B) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 8; + info->size = info->sector_count * 0x10000; + } + else if (devid == AMD_ID_F080B) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 16; + info->size = 4 * info->sector_count * 0x10000; + } + else if (devid == AMD_ID_F016D) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 32; + info->size = 4 * info->sector_count * 0x10000; + } + else { + printf ("## Unknown Flash Type: %02x\n", devid); + return 0; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* sector base address */ + info->start[i] = base + i * (info->size / info->sector_count); + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + unsigned long size_b1 = 0; + int i; + + /* Init: no FLASHes known + */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Disable flash protection */ + CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE); + + /* Static FLASH Bank configuration here (only one bank) */ + + size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]); + size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]); + + if (size_b0 > 0 || size_b1 > 0) { + + printf("("); + + if (size_b0 > 0) { + puts ("Bank#1 - "); + print_size (size_b0, (size_b1 > 0) ? ", " : ") "); + } + + if (size_b1 > 0) { + puts ("Bank#2 - "); + print_size (size_b1, ") "); + } + } + else { + printf ("## No FLASH found.\n"); + return 0; + } + /* protect monitor and environment sectors + */ + +#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE + if (size_b1) { + /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE + * but we shouldn't protect it. + */ + + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] + ); + } +#else +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] + ); +#endif +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE + if (size_b1) { + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); + } +# else + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +# endif +#endif + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case 0x89: + printf ("INTEL "); + break; + case 0x1: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + printf ("28F160C3B (16 Mbit, bottom sector)\n"); + break; + case FLASH_28F160F3B: + printf ("28F160F3B (16 Mbit, bottom sector)\n"); + break; + case FLASH_28F640C3B: + printf ("28F640C3B (64 M, bottom sector)\n"); + break; + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + if (info->size < 0x100000) + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + else + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Check the type of erased flash + */ + if (info->flash_id >> 16 == 0x1) { + /* Erase AMD flash + */ + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *)(info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto AMD_DONE; + + start = get_timer (0); + last = start; + addr = (vu_char *)(info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +AMD_DONE: + /* reset to read mode */ + addr = (volatile unsigned char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + } else { + /* Erase Intel flash + */ + + /* Start erase on unprotected sectors + */ + for (sect = s_first; sect <= s_last; sect++) { + volatile ulong *addr = + (volatile unsigned long *) info->start[sect]; + + start = get_timer (0); + last = start; + if (info->protect[sect] == 0) { + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + /* Erase the block + */ + addr[0] = 0x00200020; + addr[1] = 0x00200020; + addr[0] = 0x00D000D0; + addr[1] = 0x00D000D0; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms + */ + udelay (1000); + + last = start; + while ((addr[0] & 0x00800080) != 0x00800080 || + (addr[1] & 0x00800080) != 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout (erase suspended!)\n"); + /* Suspend erase + */ + addr[0] = 0x00B000B0; + addr[1] = 0x00B000B0; + goto DONE; + } + /* show that we're waiting + */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { + printf ("*** ERROR: erase failed!\n"); + goto DONE; + } + } + /* Clear status register and reset to read mode + */ + addr[0] = 0x00500050; + addr[1] = 0x00500050; + addr[0] = 0x00FF00FF; + addr[1] = 0x00FF00FF; + } + } + + printf (" done\n"); + +DONE: + return 0; +} + +static int write_word (flash_info_t *, volatile unsigned long *, ulong); +static int write_byte (flash_info_t *info, ulong dest, uchar data); + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong v; + int i, l, rc, cc = cnt, res = 0; + + if (info->flash_id >> 16 == 0x1) { + + /* Write to AMD 8-bit flash + */ + while (cnt > 0) { + if ((rc = write_byte(info, addr, *src)) != 0) { + return (rc); + } + addr++; + src++; + cnt--; + } + + return (0); + } else { + + /* Write to Intel 64-bit flash + */ + for (v=0; cc > 0; addr += 4, cc -= 4 - l) { + l = (addr & 3); + addr &= ~3; + + for (i = 0; i < 4; i++) { + v = (v << 8) + (i < l || i - l >= cc ? + *((unsigned char *) addr + i) : *src++); + } + + if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, volatile unsigned long *addr, + ulong data) +{ + int flag, res = 0; + ulong start; + + /* Check if Flash is (sufficiently) erased + */ + if ((*addr & data) != data) + return (2); + + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + *addr = 0x00400040; + *addr = data; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + while ((*addr & 0x00800080) != 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + /* Suspend program + */ + *addr = 0x00B000B0; + res = 1; + goto OUT; + } + } + + if (*addr & 0x00220022) { + printf ("*** ERROR: program failed!\n"); + res = 1; + } + +OUT: + /* Clear status register and reset to read mode + */ + *addr = 0x00500050; + *addr = 0x00FF00FF; + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a byte to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte (flash_info_t *info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((vu_char *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/cpu87/u-boot.lds b/board/cpu87/u-boot.lds new file mode 100644 index 0000000..fb7e665 --- /dev/null +++ b/board/cpu87/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cradle/Makefile b/board/cradle/Makefile new file mode 100644 index 0000000..265d500 --- /dev/null +++ b/board/cradle/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := cradle.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cradle/config.mk b/board/cradle/config.mk new file mode 100644 index 0000000..aa40388 --- /dev/null +++ b/board/cradle/config.mk @@ -0,0 +1,2 @@ +TEXT_BASE = 0xa0f80000 +#TEXT_BASE = 0 diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c new file mode 100644 index 0000000..6f65f32 --- /dev/null +++ b/board/cradle/cradle.c @@ -0,0 +1,227 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + + +/* local prototypes */ +void set_led (int led, int color); +void error_code_halt (int code); +int init_sio (int led, unsigned long base); +inline void cradle_outb (unsigned short val, unsigned long base, + unsigned long reg); +inline unsigned char cradle_inb (unsigned long base, unsigned long reg); +inline void sleep (int i); + +inline void +/**********************************************************/ +sleep (int i) +/**********************************************************/ +{ + while (i--) { + udelay (1000000); + } +} + +void +/**********************************************************/ +error_code_halt (int code) +/**********************************************************/ +{ + while (1) { + led_code (code, RED); + sleep (1); + led_code (0, OFF); + sleep (1); + } +} + +void +/**********************************************************/ +led_code (int code, int color) +/**********************************************************/ +{ + int i; + + code &= 0xf; /* only 4 leds */ + + for (i = 0; i < 4; i++) { + if (code & (1 << i)) { + set_led (i, color); + } else { + set_led (i, OFF); + } + } +} + +void +/**********************************************************/ +set_led (int led, int color) +/**********************************************************/ +{ + int shift = led * 2; + unsigned long mask = 0x3 << shift; + + CRADLE_LED_CLR_REG = mask; /* clear bits */ + CRADLE_LED_SET_REG = (color << shift); /* set bits */ + udelay (5000); +} + +inline void +/**********************************************************/ +cradle_outb (unsigned short val, unsigned long base, unsigned long reg) +/**********************************************************/ +{ + *(volatile unsigned short *) (base + (reg * 2)) = val; +} + +inline unsigned char +/**********************************************************/ +cradle_inb (unsigned long base, unsigned long reg) +/**********************************************************/ +{ + unsigned short val; + + val = *(volatile unsigned short *) (base + (reg * 2)); + return (val & 0xff); +} + +int +/**********************************************************/ +init_sio (int led, unsigned long base) +/**********************************************************/ +{ + unsigned char val; + + set_led (led, YELLOW); + val = cradle_inb (base, CRADLE_SIO_INDEX); + val = cradle_inb (base, CRADLE_SIO_INDEX); + if (val != 0) { + set_led (led, RED); + return -1; + } + + /* map SCC2 to COM1 */ + cradle_outb (0x01, base, CRADLE_SIO_INDEX); + cradle_outb (0x00, base, CRADLE_SIO_DATA); + + /* enable SCC2 extended regs */ + cradle_outb (0x40, base, CRADLE_SIO_INDEX); + cradle_outb (0xa0, base, CRADLE_SIO_DATA); + + /* enable SCC2 clock multiplier */ + cradle_outb (0x51, base, CRADLE_SIO_INDEX); + cradle_outb (0x04, base, CRADLE_SIO_DATA); + + /* enable SCC2 */ + cradle_outb (0x00, base, CRADLE_SIO_INDEX); + cradle_outb (0x04, base, CRADLE_SIO_DATA); + + /* map SCC2 DMA to channel 0 */ + cradle_outb (0x4f, base, CRADLE_SIO_INDEX); + cradle_outb (0x09, base, CRADLE_SIO_DATA); + + /* read ID from SIO to check operation */ + cradle_outb (0xe4, base, 0x3f8 + 0x3); + val = cradle_inb (base, 0x3f8 + 0x0); + if ((val & 0xf0) != 0x20) { + set_led (led, RED); + /* disable SCC2 */ + cradle_outb (0, base, CRADLE_SIO_INDEX); + cradle_outb (0, base, CRADLE_SIO_DATA); + return -1; + } + /* set back to bank 0 */ + cradle_outb (0, base, 0x3f8 + 0x3); + set_led (led, GREEN); + return 0; +} + +/* + * Miscelaneous platform dependent initialisations + */ + +int +/**********************************************************/ +board_late_init (void) +/**********************************************************/ +{ + return (0); +} + +int +/**********************************************************/ +board_init (void) +/**********************************************************/ +{ + DECLARE_GLOBAL_DATA_PTR; + + led_code (0xf, YELLOW); + + /* arch number of HHP Cradle */ + gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + /* Init SIOs to enable SCC2 */ + udelay (100000); /* delay makes it look neat */ + init_sio (0, CRADLE_SIO1_PHYS); + udelay (100000); + init_sio (1, CRADLE_SIO2_PHYS); + udelay (100000); + init_sio (2, CRADLE_SIO3_PHYS); + udelay (100000); + set_led (3, GREEN); + + return 1; +} + +int +/**********************************************************/ +dram_init (void) +/**********************************************************/ +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return (PHYS_SDRAM_1_SIZE + + PHYS_SDRAM_2_SIZE + + PHYS_SDRAM_3_SIZE + + PHYS_SDRAM_4_SIZE ); +} diff --git a/board/cradle/flash.c b/board/cradle/flash.c new file mode 100644 index 0000000..f3f9a8c --- /dev/null +++ b/board/cradle/flash.c @@ -0,0 +1,359 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define FLASH_BANK_SIZE 0x400000 +#define MAIN_SECT_SIZE 0x20000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F128J3 & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) { + case 0: + flashbase = PHYS_FLASH_1; + break; + case 1: + flashbase = PHYS_FLASH_2; + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = + flashbase + j * MAIN_SECT_SIZE; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i, j; + + for (j = 0; j < CFG_MAX_FLASH_BANKS; j++) { + switch (info->flash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F320J3A & FLASH_TYPEMASK): + printf ("28F320J3A (32Mbit)\n"); + break; + case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): + printf ("28F128J3 (128Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + info++; + } + +Done: ; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + int rc = ERR_OK; + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (INTEL_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + + *addr = 0x20; /* erase setup */ + *addr = 0xD0; /* erase confirm */ + + while ((*addr & 0x80) != 0x80) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + *addr = 0xB0; /* suspend erase */ + *addr = 0xFF; /* reset to read mode */ + rc = ERR_TIMOUT; + goto outahere; + } + } + + /* clear status register command */ + *addr = 0x50; + /* reset to read mode */ + *addr = 0xFF; + } + printf ("ok.\n"); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + +outahere: + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (flag) + enable_interrupts (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_word (flash_info_t * info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest, val; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased + */ + if ((*addr & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* clear status register command */ + *addr = 0x50; + + /* program set-up command */ + *addr = 0x40; + + /* latch address/data */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((val = *addr) & 0x80) != 0x80) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + rc = ERR_TIMOUT; + /* suspend program command */ + *addr = 0xB0; + goto outahere; + } + } + + if (val & 0x1A) { /* check for error */ + printf ("\nFlash write error %02x at address %08lx\n", + (int) val, (unsigned long) dest); + if (val & (1 << 3)) { + printf ("Voltage range error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + if (val & (1 << 1)) { + printf ("Device protect error.\n"); + rc = ERR_PROTECTED; + goto outahere; + } + if (val & (1 << 4)) { + printf ("Programming error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + rc = ERR_PROG_ERROR; + goto outahere; + } + +outahere: + /* read array command */ + *addr = 0xFF; + + if (flag) + enable_interrupts (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + ushort data; + int l; + int i, rc; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_word (info, wp, data); +} diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S new file mode 100644 index 0000000..2fd307f --- /dev/null +++ b/board/cradle/lowlevel_init.S @@ -0,0 +1,515 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + .macro SET_LED val + ldr r6, =CRADLE_LED_CLR_REG + ldr r7, =0 + str r7, [r6] + ldr r6, =CRADLE_LED_SET_REG + ldr r7, =\val + str r7, [r6] + .endm + + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + + /* Set up GPIO pins first */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + /* enable GPIO pins */ + ldr r0, =PSSR + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + SET_LED 1 + + ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */ + ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */ + str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */ + ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */ + + +/********************************************************************* + Initlialize Memory Controller + + See PXA250 Operating System Developer's Guide + + pause for 200 uSecs- allow internal clocks to settle + *Note: only need this if hard reset... doing it anyway for now +*/ + + @ Step 1 + @ ---- Wait 200 usec + ldr r3, =OSCR @ reset the OS Timer Count to zero + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + SET_LED 2 + +mem_init: + @ get memory controller base address + ldr r1, =MEMC_BASE + + +@**************************************************************************** +@ Step 2 +@ + + @ Step 2a + @ write msc0, read back to ensure data latches + @ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] + + @ write msc1 + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + @ write msc2 + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + @ Step 2b + @ write mecr + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + + @ write mcmem0 + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + + @ write mcmem1 + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + + @ write mcatt0 + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + + @ write mcatt1 + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + + @ write mcio0 + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + + @ write mcio1 + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + + /*SET_LED 3 */ + + @ Step 2c + @ fly-by-dma is defeatured on this part + @ write flycnfg + @ldr r2, =CFG_FLYCNFG_VAL + @str r2, [r1, #FLYCNFG_OFFSET] + +/* FIXME Does this sequence really make sense */ +#ifdef REDBOOT_WAY + @ Step 2d + @ get the mdrefr settings + ldr r3, =CFG_MDREFR_VAL + + @ extract DRI field (we need a valid DRI field) + @ + ldr r2, =0xFFF + + @ valid DRI field in r3 + @ + and r3, r3, r2 + + @ get the reset state of MDREFR + @ + ldr r4, [r1, #MDREFR_OFFSET] + + @ clear the DRI field + @ + bic r4, r4, r2 + + @ insert the valid DRI field loaded above + @ + orr r4, r4, r3 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ *Note: preserve the mdrefr value in r4 * + + /*SET_LED 4 */ + +@**************************************************************************** +@ Step 3 +@ +@ NO SRAM + + mov pc, r10 + + +@**************************************************************************** +@ Step 4 +@ + + @ Assumes previous mdrefr value in r4, if not then read current mdrefr + + @ clear the free-running clock bits + @ (clear K0Free, K1Free, K2Free + @ + bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000) + + @ set K0RUN for CPLD clock + @ + orr r4, r4, #0x00002000 + + @ set K1RUN if bank 0 installed + @ + orr r4, r4, #0x00010000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + @ deassert SLFRSH + @ + bic r4, r4, #0x00400000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ assert E1PIN + @ + orr r4, r4, #0x00008000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + nop + nop +#else + @ Step 2d + @ get the mdrefr settings + ldr r3, =CFG_MDREFR_VAL + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ Step 4 + + @ set K0RUN for CPLD clock + @ + orr r4, r4, #0x00002000 + + @ set K1RUN for bank 0 + @ + orr r4, r4, #0x00010000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + @ deassert SLFRSH + @ + bic r4, r4, #0x00400000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ assert E1PIN + @ + orr r4, r4, #0x00008000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + nop + nop +#endif + + @ Step 4d + @ fetch platform value of mdcnfg + @ + ldr r2, =CFG_MDCNFG_VAL + + @ disable all sdram banks + @ + bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) + bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) + + @ program banks 0/1 for bus width + @ + bic r2, r2, #MDCNFG_DWID0 @0=32-bit + + @ write initial value of mdcnfg, w/o enabling sdram banks + @ + str r2, [r1, #MDCNFG_OFFSET] + + @ Step 4e + @ pause for 200 uSecs + @ + ldr r3, =OSCR @ reset the OS Timer Count to zero + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + /*SET_LED 5 */ + + /* Why is this here??? */ + mov r0, #0x78 @turn everything off + mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.) + + @ Step 4f + @ Access memory *not yet enabled* for CBR refresh cycles (8) + @ - CBR is generated for all banks + + ldr r2, =CFG_DRAM_BASE + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + + @ Step 4g + @get memory controller base address + @ + ldr r1, =MEMC_BASE + + @fetch current mdcnfg value + @ + ldr r3, [r1, #MDCNFG_OFFSET] + + @enable sdram bank 0 if installed (must do for any populated bank) + @ + orr r3, r3, #MDCNFG_DE0 + + @write back mdcnfg, enabling the sdram bank(s) + @ + str r3, [r1, #MDCNFG_OFFSET] + + @ Step 4h + @ write mdmrs + @ + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + @ Done Memory Init + + /*SET_LED 6 */ + + @******************************************************************** + @ Disable (mask) all interrupts at the interrupt controller + @ + + @ clear the interrupt level register (use IRQ, not FIQ) + @ + mov r1, #0 + ldr r2, =ICLR + str r1, [r2] + + @ Set interrupt mask register + @ + ldr r1, =CFG_ICMR_VAL + ldr r2, =ICMR + str r1, [r2] + + @ ******************************************************************** + @ Disable the peripheral clocks, and set the core clock + @ + + @ Turn Off ALL on-chip peripheral clocks for re-configuration + @ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + @ set core clocks + @ + ldr r2, =CFG_CCCR_VAL + ldr r1, =CCCR + str r2, [r1] + +#ifdef ENABLE32KHZ + @ enable the 32Khz oscillator for RTC and PowerManager + @ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + @ NOTE: spin here until OSCC.OOK get set, + @ meaning the PLL has settled. + @ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + @ Turn on needed clocks + @ + ldr r1, =CKEN + ldr r2, =CFG_CKEN_VAL + str r2, [r1] + + /*SET_LED 7 */ + +/* Is this needed???? */ +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + +#endif + + /*SET_LED 8 */ + + mov pc, r10 + +@ End lowlevel_init diff --git a/board/cradle/u-boot.lds b/board/cradle/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/cradle/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c new file mode 100644 index 0000000..a7114eb --- /dev/null +++ b/board/cray/L1/L1.c @@ -0,0 +1,365 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include <405gp_i2c.h> +#include +#include +#include +#include +#include + +#define L1_MEMSIZE (32*1024*1024) + +/* the std. DHCP stufff */ +#define DHCP_ROUTER 3 +#define DHCP_NETMASK 1 +#define DHCP_BOOTFILE 67 +#define DHCP_ROOTPATH 17 +#define DHCP_HOSTNAME 12 + +/* some extras used by CRAY + * + * on the server this looks like: + * + * option L1-initrd-image code 224 = string; + * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image" + */ +#define DHCP_L1_INITRD 224 + +/* new, [better?] way via official vendor-extensions, defining an option + * space. + * on the server this looks like: + * + * option space CRAYL1; + * option CRAYL1.initrd code 3 = string; + * ..etc... + */ +#define DHCP_VENDOR_SPECX 43 +#define DHCP_VX_INITRD 3 +#define DHCP_VX_BOOTCMD 4 +#define DHCP_VX_BOOTARGS 5 +#define DHCP_VX_ROOTDEV 6 +#define DHCP_VX_FROMFLASH 7 +#define DHCP_VX_BOOTSCRIPT 8 +#define DHCP_VX_RCFILE 9 +#define DHCP_VX_MAGIC 10 + +/* Things DHCP server can tellme about. If there's no flash address, then + * they dont participate in 'update' to flash, and we force their values + * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I + * know this is a pain... + * + * If I get no bootfile, boot from flash. If rootpath, use that. If no + * rootpath use initrd in flash. + */ +typedef struct dhcp_item_s { + u8 dhcp_option; + u8 dhcp_vendor_option; + char *dhcpvalue; + char *envname; +} dhcp_item_t; +static dhcp_item_t Things[] = { + {DHCP_ROUTER, 0, NULL, "gateway"}, + {DHCP_NETMASK, 0, NULL, "netmask"}, + {DHCP_BOOTFILE, 0, NULL, "bootfile"}, + {DHCP_ROOTPATH, 0, NULL, "rootpath"}, + {DHCP_HOSTNAME, 0, NULL, "hostname"}, + {DHCP_L1_INITRD, 0, NULL, "initrd"}, +/* and the other way.. */ + {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"}, + {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"}, + {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"}, + {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"}, + {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"}, + {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"}, + {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL}, + {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL} +}; + +#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t))) + +extern char bootscript[]; + +/* Here is the boot logic as HUSH script. Overridden by any TFP provided + * bootscript file. + */ + +static void init_sdram (void); + +/* ------------------------------------------------------------------------- */ +int board_early_init_f (void) +{ + /* Running from ROM: global data is still READONLY */ + init_sdram (); + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + return 0; +} + +/* ------------------------------------------------------------------------- */ +int checkboard (void) +{ + return (0); +} +/* ------------------------------------------------------------------------- */ + +/* ------------------------------------------------------------------------- */ +int misc_init_r (void) +{ + char *s, *e; + image_header_t *hdr; + time_t timestamp; + struct rtc_time tm; + char bootcmd[32]; + + hdr = (image_header_t *) (CFG_MONITOR_BASE - sizeof (image_header_t)); + timestamp = (time_t) hdr->ih_time; + to_tm (timestamp, &tm); + printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); + +#define FACTORY_SETTINGS 0xFFFC0000 + if ((s = getenv ("ethaddr")) == NULL) { + e = (char *) (FACTORY_SETTINGS); + if (*(e + 0) != '0' + || *(e + 1) != '0' + || *(e + 2) != ':' + || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') { + printf ("No valid MAC address in flash location 0x3C0000!\n"); + } else { + printf ("Factory MAC: %s\n", e); + setenv ("ethaddr", e); + } + } + sprintf (bootcmd,"autoscript %X",(unsigned)bootscript); + setenv ("bootcmd", bootcmd); + return (0); +} + +/* ------------------------------------------------------------------------- */ +long int initdram (int board_type) +{ + return (L1_MEMSIZE); +} + +/* ------------------------------------------------------------------------- */ +/* stubs so we can print dates w/o any nvram RTC.*/ +void rtc_get (struct rtc_time *tmp) +{ + return; +} +void rtc_set (struct rtc_time *tmp) +{ + return; +} +void rtc_reset (void) +{ + return; +} + +/* ------------------------------------------------------------------------- */ +/* Do sdram bank init in C so I can read it..no console to print to yet! + */ +static void init_sdram (void) +{ + unsigned long tmp; + + /* write SDRAM bank 0 register */ + mtdcr (memcfga, mem_mb0cf); + mtdcr (memcfgd, 0x00062001); + +/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ +/* To set the appropriate timings, we need to know the SDRAM speed. */ +/* We can use the PLB speed since the SDRAM speed is the same as */ +/* the PLB speed. The PLB speed is the FBK divider times the */ +/* 405GP reference clock, which on the L1 is 25Mhz. */ +/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is */ +/* 150Mhz; if FBK is 3, SDRAM is 150Mhz. */ + + /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ + +/* write SDRAM timing for 100Mhz. */ + mtdcr (memcfga, mem_sdtr1); + mtdcr (memcfgd, 0x0086400D); + +/* write SDRAM refresh interval register */ + mtdcr (memcfga, mem_rtr); + mtdcr (memcfgd, 0x05F00000); + udelay (200); + +/* sdram controller.*/ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x90800000); + udelay (200); + +/* initially, disable ECC on all banks */ + udelay (200); + mtdcr (memcfga, mem_ecccf); + tmp = mfdcr (memcfgd); + tmp &= 0xff0fffff; + mtdcr (memcfga, mem_ecccf); + mtdcr (memcfgd, tmp); + + return; +} + +extern int memory_post_test (int flags); + +int testdram (void) +{ + unsigned long tmp; + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) L1_MEMSIZE; + uint *p; + + if (getenv_r("booted",NULL,0) <= 0) + { + printf ("testdram.."); + /*AA*/ + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", + (uint) p, *p, 0xaaaaaaaa); + return 1; + } + } + /*55*/ + for (p = pstart; p < pend; p++) + *p = 0x55555555; + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", + (uint) p, *p, 0x55555555); + return 1; + } + } + /*addr*/ + for (p = pstart; p < pend; p++) + *p = (unsigned)p; + for (p = pstart; p < pend; p++) { + if (*p != (unsigned)p) { + printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", + (uint) p, *p, (uint)p); + return 1; + } + } + printf ("Success. "); + } + printf ("Enable ECC.."); + + mtdcr (memcfga, mem_mcopt1); + tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, tmp); + udelay (600); + for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) + ; + udelay (400); + mtdcr (memcfga, mem_ecccf); + tmp = mfdcr (memcfgd); + tmp |= 0x00800000; + mtdcr (memcfgd, tmp); + udelay (400); + printf ("enabled.\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ +static u8 *dhcp_env_update (u8 thing, u8 * pop) +{ + u8 i, oplen; + + oplen = *(pop + 1); + + if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) { + printf ("Whoops! failed to malloc space for DHCP thing %s\n", + Things[thing].envname); + return NULL; + } + for (i = 0; (i < oplen); i++) + if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ') + break; + *(Things[thing].dhcpvalue + i) = '\0'; + +/* set env. */ + if (Things[thing].envname) + { + setenv (Things[thing].envname, Things[thing].dhcpvalue); + } + return ((u8 *)(Things[thing].dhcpvalue)); +} + +/* ------------------------------------------------------------------------- */ +u8 *dhcp_vendorex_prep (u8 * e) +{ + u8 thing; + +/* ask for the things I want. */ + *e++ = 55; /* Parameter Request List */ + *e++ = N_THINGS; + for (thing = 0; thing < N_THINGS; thing++) + *e++ = Things[thing].dhcp_option; + *e++ = 255; + + return e; +} + +/* ------------------------------------------------------------------------- */ +/* .. return NULL means it wasnt mine, non-null means I got it..*/ +u8 *dhcp_vendorex_proc (u8 * pop) +{ + u8 oplen, *sub_op, sub_oplen, *retval; + u8 thing = 0; + + retval = NULL; + oplen = *(pop + 1); +/* if pop is vender spec indicator, there are sub-options. */ + if (*pop == DHCP_VENDOR_SPECX) { + for (sub_op = pop + 2; + oplen && (sub_oplen = *(sub_op + 1)); + oplen -= sub_oplen, sub_op += (sub_oplen + 2)) { + for (thing = 0; thing < N_THINGS; thing++) { + if (*sub_op == Things[thing].dhcp_vendor_option) { + if (!(retval = dhcp_env_update (thing, sub_op))) { + return NULL; + } + } + } + } + } else { + for (thing = 0; thing < N_THINGS; thing++) { + if (*pop == Things[thing].dhcp_option) + if (!(retval = dhcp_env_update (thing, pop))) + return NULL; + } + } + return (pop); +} diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h new file mode 100644 index 0000000..1b41824 --- /dev/null +++ b/board/cray/L1/L1.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip + * + * Start Address Length + * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash ----------------- + * | Failsafe Linux Image | (1M) + * +=======================+ 0xFFD0_0000 + * | (Reserved FlashFiles) | (1M) + * +=======================+ 0xFFE0_0000 + * | Failsafe RootFS | (1M) + * +=======================+ 0xFFF0_0000 + * | | + * | U N U S E D | + * | | + * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes) + * | environment settings | (64k) + * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes) + * | U-Boot | 0xFFFE_0040 _start of U-Boot + * | | 0xFFFE_FFFC reset vector - branch to _start + * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash ----------------- + *****************************************************************************/ diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile new file mode 100644 index 0000000..bfe0922 --- /dev/null +++ b/board/cray/L1/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = init.o + +# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not +# built in the depend stage. So... put bootscript.o here, not in OBJS +$(LIB): $(OBJS) $(SOBJS) bootscript.o + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) bootscript.c bootscript.image bootscript.o + +distclean: clean + rm -f $(LIB) core *.bak .depend + +$(BOARD).o : $(BOARD).c bootscript.o + +bootscript.c: bootscript.image + od -t x1 -v -A x $^ | awk -f x2c.awk > $@ + +bootscript.image: bootscript.hush Makefile + -$(TOPDIR)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d bootscript.hush $@ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cray/L1/bootscript.hush b/board/cray/L1/bootscript.hush new file mode 100644 index 0000000..ec4839b --- /dev/null +++ b/board/cray/L1/bootscript.hush @@ -0,0 +1,117 @@ +# $Header$ +# hush bootscript for PPCBOOT on L1 +# note: all #s are in hex, do _NOT_ prefix it with 0x + +flash_rfs=ffc00000 +flash_krl=fff00000 +tftp_addr=100000 +tftp2_addr=1000000 + +if printenv booted +then + echo already booted before +else + echo first boot in environment, create and save settings + setenv booted OK + saveenv +fi + +setenv autoload no +# clear out stale env stuff, so we get fresh from dhcp. +for setting in initrd fromflash kernel rootfs rootpath +do +setenv $setting +done + +dhcp + +# if host provides us with a different bootscript, us it. +if printenv bootscript + then + tftp $tftp_addr $bootcript + if imi $tftp_addr + then + autoscript $tftp_addr + fi +fi + +# default base kernel arguments. +setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120 + +# Have a kernel in flash? +if imi $flash_krl +then + echo ok kernel to boot from $flash_krl + setenv kernel $flash_krl +else + echo no kernel to boot from $flash_krl, need tftp +fi + +# Have a rootfs in flash? +echo test for SQUASHfs at $flash_rfs + +if imi $flash_rfs +then + echo appears to be a good initrd image at base of flash OK + setenv rootfs $flash_rfs +else + echo no image at base of flash, need nfsroot or initrd +fi + +# I boot from flash if told to and I can. +if printenv fromflash && printenv kernel && printenv rootfs +then + echo booting entirely from flash + setenv bootargs root=/dev/ram0 rw $bootargs + bootm $kernel $rootfs + echo oh no failed so I try some other stuff +fi + +# TFTP down a kernel +if printenv bootfile +then + tftp $tftp_addr $bootfile + setenv kernel $tftp_addr + echo I will boot the TFTP kernel +else + if printenv kernel + then + echo no bootfile specified, will use one from flash + else + setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image + echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile + tftp $tftp_addr $bootfile + setenv kernel $tftp_addr + fi +fi + +# the rootfs. +if printenv rootpath +then + echo rootpath is $rootpath + if printenv initrd + then + echo initrd is also specified, so use $initrd + tftp $tftp2_addr $initrd + setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs + bootm $kernel $tftp2_addr + else + echo initrd is not specified, so use NFSROOT $rootpat + setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs + bootm $kernel + fi +else + echo we have no rootpath check for one in flash + if printenv rootfs + then + echo I will use the one in flash + setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs + bootm $kernel + else + setenv rootpath /export/crayl1 + echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath + setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs + bootm $kernel + fi +fi +reset diff --git a/board/cray/L1/config.mk b/board/cray/L1/config.mk new file mode 100644 index 0000000..b69fe8e --- /dev/null +++ b/board/cray/L1/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Note: I make an "image" from U-Boot itself, which prefixes 0x40 bytes of +# header info, hence start address is thus shifted. +TEXT_BASE = 0xFFFD0040 diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c new file mode 100644 index 0000000..f313274 --- /dev/null +++ b/board/cray/L1/flash.c @@ -0,0 +1,470 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +/* + * Modified July 20, 2001 + * Strip down to support ONLY the AMD29F032B. + * Dave Updegraff - Cray, Inc. dave@cray.com + */ + +#include +#include +#include + +/* The flash chip we use... */ +#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */ +#define FLASH_AM320B 0x0009 + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; isector_count; i++) + info->start[i] = base + (i * 0x00010000); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; + + value = addr2[0]; + + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_F032B: + info->flash_id += FLASH_AM320B; + info->sector_count = 64; + info->size = 0x0400000; /* => 4 MB */ + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + printf("Erasing sector %p\n", addr2); + + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *)dest) & + (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) + { + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S new file mode 100644 index 0000000..72a10d3 --- /dev/null +++ b/board/cray/L1/init.S @@ -0,0 +1,147 @@ +/*------------------------------------------------------------------------------+ */ +/* */ +/* This source code has been made available to you by IBM on an AS-IS */ +/* basis. Anyone receiving this source is licensed under IBM */ +/* copyrights to use it in any way he or she deems fit, including */ +/* copying it, modifying it, compiling it, and redistributing it either */ +/* with or without modifications. No license under IBM patents or */ +/* patent applications is to be implied by the copyright license. */ +/* */ +/* Any user of this software should understand that IBM cannot provide */ +/* technical support for this software and will not be responsible for */ +/* any consequences resulting from the use of this software. */ +/* */ +/* Any person who transfers this source code or any derivative work */ +/* must include the IBM copyright notice, this paragraph, and the */ +/* preceding two paragraphs in the transferred software. */ +/* */ +/* COPYRIGHT I B M CORPORATION 1995 */ +/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ +/*------------------------------------------------------------------------------- */ + +/*----------------------------------------------------------------------------- */ +/* Function: ext_bus_cntlr_init */ +/* Description: Initializes the External Bus Controller for the external */ +/* peripherals. IMPORTANT: For pass1 this code must run from */ +/* cache since you can not reliably change a peripheral banks */ +/* timing register (pbxap) while running code from that bank. */ +/* For ex., since we are running from ROM on bank 0, we can NOT */ +/* execute the code that modifies bank 0 timings from ROM, so */ +/* we run it from cache. */ +/* Bank 0 - Flash and SRAM */ +/* Bank 1 - NVRAM/RTC */ +/* Bank 2 - Keyboard/Mouse controller */ +/* Bank 3 - IR controller */ +/* Bank 4 - not used */ +/* Bank 5 - not used */ +/* Bank 6 - not used */ +/* Bank 7 - FPGA registers */ +/*-----------------------------------------------------------------------------#include */ +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ +/* except for #1 which we use for DMA'ing to IOCA-like things, so the */ +/* control registers to set that up are determined by what we've */ +/* empirically discovered work there. */ + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + mflr r4 /* save link register */ + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 10; used to prefetch */ + mtctr r4 /* 10 cache lines to fit this function */ + /* in cache (gives us 8x10=80 instrctns) */ +..ebcloop: + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 10 cache lines */ + + /*------------------------------------------------------------------- */ + /* Delay to ensure all accesses to ROM are complete before changing */ + /* bank 0 timings. 200usec should be enough. */ + /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ + /*------------------------------------------------------------------- */ + addis r3,0,0x0 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + + /*---------------------------------------------------------------------- */ + /* Peripheral Bank 0 (Flash) initialization */ + /*---------------------------------------------------------------------- */ + /* 0x7F8FFE80 slowest boot */ + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,0x9B01 + ori r4,r4,0x5480 + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ + ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ + mtdcr ebccfgd,r4 + + blr + + /*---------------------------------------------------------------------- */ + /* Peripheral Bank 1 (NVRAM/RTC) initialization */ + /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ + /* and we do DMA on it. The ConfigurationRegister part is threfore */ + /* almost arbitrary, except that our linux driver needs to know the */ + /* address, but it can query, it.. */ + /* */ + /* The AccessParameter is CRITICAL, */ + /* thouch, since it needs to agree with the electrical timings on the */ + /* IOCA parallel interface. That value is: 0x0185,4380 */ + /* BurstModeEnable BME=0 */ + /* TransferWait TWT=3 */ + /* ChipSelectOnTiming CSN=1 */ + /* OutputEnableOnTimimg OEN=1 */ + /* WriteByteEnableOnTiming WBN=1 */ + /* WriteByteEnableOffTiming WBF=0 */ + /* TransferHold TH=1 */ + /* ReadyEnable RE=1 */ + /* SampleOnReady SOR=1 */ + /* ByteEnableMode BEM=0 */ + /* ParityEnable PEN=0 */ + /* all reserved bits=0 */ + /*---------------------------------------------------------------------- */ + /*---------------------------------------------------------------------- */ + addi r4,0,pb1ap + mtdcr ebccfga,r4 + addis r4,0,0x0185 /* hiword */ + ori r4,r4,0x4380 /* loword */ + mtdcr ebccfgd,r4 + + addi r4,0,pb1cr + mtdcr ebccfga,r4 + addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ + ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ + mtdcr ebccfgd,r4 + + blr + +/*----------------------------------------------------------------------------- */ +/* Function: sdram_init */ +/* Description: Configures SDRAM memory banks. */ +/* NOTE: for CrayL1 we have ECC memory, so enable it. */ +/*....now done in C in L1.c:init_sdram for readability. */ +/*----------------------------------------------------------------------------- */ + .globl sdram_init + +sdram_init: + blr diff --git a/board/cray/L1/patchme b/board/cray/L1/patchme new file mode 100644 index 0000000..e77ee7e --- /dev/null +++ b/board/cray/L1/patchme @@ -0,0 +1,30 @@ +# master confi.mk +echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk + +# patch the examples/Makefile to ignore return value from OBJCOPY +sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile + +# add a built target for mkimage on the target architecture +sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile + +cat <>tools/makefile +mkimage.ppc : mkimage.o.ppc crc32.o.ppc + powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^ + powerpc-linux-strip $@ + +XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes" +mkimage.o.ppc: mkimage.c + powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ + +crc32.o.ppc: crc32.c + powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ + +EOF + +# make an image by default out of the u-boot image +sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile +cat <>makefile +u-boot.image: u-boot.bin + tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@ + +EOF diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds new file mode 100644 index 0000000..cf4bbb9 --- /dev/null +++ b/board/cray/L1/u-boot.lds @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/cray/L1/init.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/*. = env_offset;*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug new file mode 100644 index 0000000..1608f8c --- /dev/null +++ b/board/cray/L1/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cray/L1/x2c.awk b/board/cray/L1/x2c.awk new file mode 100644 index 0000000..9235e6c --- /dev/null +++ b/board/cray/L1/x2c.awk @@ -0,0 +1,6 @@ +#!/bin/awk +BEGIN { print "unsigned char bootscript[] = { \n"} +{ for (i = 2; i <= NF ; i++ ) printf "0x"$i"," + print "" +} +END { print "\n};\n" } diff --git a/board/csb226/Makefile b/board/csb226/Makefile new file mode 100644 index 0000000..5b311a9 --- /dev/null +++ b/board/csb226/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := csb226.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/csb226/config.mk b/board/csb226/config.mk new file mode 100644 index 0000000..2354392 --- /dev/null +++ b/board/csb226/config.mk @@ -0,0 +1,15 @@ +# +# Linux-Kernel is expected to be at c000'8000, entry c000'8000 +# +# we load ourself to c170'0000, the upper 1 MB of second bank +# +# download areas is c800'0000 +# + +# This is the address where U-Boot lives in flash: +#TEXT_BASE = 0 + +# FIXME: armboot does only work correctly when being compiled +# for the addresses _after_ relocation to RAM!! Otherwhise the +# .bss segment is assumed in flash... +TEXT_BASE = 0xa1fe0000 diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c new file mode 100644 index 0000000..c99a715 --- /dev/null +++ b/board/csb226/csb226.c @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2002 + * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de + * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net + * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +/** + * misc_init_r: - misc initialisation routines + */ + +int misc_init_r(void) +{ +#if 0 + uchar *str; + + /* determine if the software update key is pressed during startup */ + /* not ported yet... */ + if (GPLR0 & 0x00000800) { + printf("using bootcmd_normal (sw-update button not pressed)\n"); + str = getenv("bootcmd_normal"); + } else { + printf("using bootcmd_update (sw-update button pressed)\n"); + str = getenv("bootcmd_update"); + } + + setenv("bootcmd",str); +#endif + return 0; +} + + +/** + * board_init: - setup some data structures + * + * @return: 0 in case of success + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of CSB226 board */ + gd->bd->bi_arch_number = MACH_TYPE_CSB226; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + + +/** + * dram_init: - setup dynamic RAM + * + * @return: 0 in case of success + */ + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + + +/** + * csb226_set_led: - switch LEDs on or off + * + * @param led: LED to switch (0,1,2) + * @param state: switch on (1) or off (0) + */ + +void csb226_set_led(int led, int state) +{ + switch(led) { + + case 0: if (state==1) { + GPCR0 |= CSB226_USER_LED0; + } else if (state==0) { + GPSR0 |= CSB226_USER_LED0; + } + break; + + case 1: if (state==1) { + GPCR0 |= CSB226_USER_LED1; + } else if (state==0) { + GPSR0 |= CSB226_USER_LED1; + } + break; + + case 2: if (state==1) { + GPCR0 |= CSB226_USER_LED2; + } else if (state==0) { + GPSR0 |= CSB226_USER_LED2; + } + break; + } + + return; +} + + +/** + * show_boot_progress: - indicate state of the boot process + * + * @param status: Status number - see README for details. + * + * The CSB226 does only have 3 LEDs, so we switch them on at the most + * important states (1, 5, 15). + */ + +void show_boot_progress (int status) +{ + switch(status) { + case 1: csb226_set_led(0,1); break; + case 5: csb226_set_led(1,1); break; + case 15: csb226_set_led(2,1); break; + } + + return; +} diff --git a/board/csb226/flash.c b/board/csb226/flash.c new file mode 100644 index 0000000..f6dfd96 --- /dev/null +++ b/board/csb226/flash.c @@ -0,0 +1,366 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Robert Schwebel, Pengutronix, + * + * (C) Copyright 2003 (2 x 16 bit Flash bank patches) + * Rolf Peukert, IMMS gGmbH, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define FLASH_BANK_SIZE 0x02000000 +#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +/** + * flash_init: - initialize data structures for flash chips + * + * @return: size of the flash + */ + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F128J3 & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + + switch (i) { + case 0: + flashbase = PHYS_FLASH_1; + break; + default: + panic("configured too many flash banks!\n"); + break; + } + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + + return size; +} + + +/** + * flash_print_info: - print information about the flash situation + */ + +void flash_print_info (flash_info_t *info) +{ + int i, j; + + for (j=0; jflash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): + printf("28F128J3 (128Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) printf ("\n "); + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + info++; + } +} + + +/** + * flash_erase: - erase flash sectors + */ + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + int rc = ERR_OK; + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) prot++; + } + + if (prot) return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { + + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + if (info->protect[sect] == 0) { /* not protected */ + u32 * volatile addr = (u32 * volatile)(info->start[sect]); + + /* erase sector: */ + /* The strata flashs are aligned side by side on */ + /* the data bus, so we have to write the commands */ + /* to both chips here: */ + + *addr = 0x00200020; /* erase setup */ + *addr = 0x00D000D0; /* erase confirm */ + + while ((*addr & 0x00800080) != 0x00800080) { + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + *addr = 0x00B000B0; /* suspend erase*/ + *addr = 0x00FF00FF; /* read mode */ + rc = ERR_TIMOUT; + goto outahere; + } + } + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* reset to read mode */ + } + printf("ok.\n"); + } + if (ctrlc()) printf("User Interrupt!\n"); + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked(10000); + + if (flag) enable_interrupts(); + + return rc; +} + +/** + * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each + */ + +static int write_long (flash_info_t *info, ulong dest, ulong data) +{ + u32 * volatile addr = (u32 * volatile)dest, val; + int rc = ERR_OK; + int flag; + + /* read array command - just for the case... */ + *addr = 0x00FF00FF; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts(); + + /* clear status register command */ + *addr = 0x00500050; + + /* program set-up command */ + *addr = 0x00400040; + + /* latch address/data */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + /* wait while polling the status register */ + while(((val = *addr) & 0x00800080) != 0x00800080) { + if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { + rc = ERR_TIMOUT; + /* suspend program command */ + *addr = 0x00B000B0; + goto outahere; + } + } + + /* check for errors */ + if(val & 0x001A001A) { + printf("\nFlash write error %02x at address %08lx\n", + (int)val, (unsigned long)dest); + if(val & 0x00080008) { + printf("Voltage range error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + if(val & 0x00020002) { + printf("Device protect error.\n"); + rc = ERR_PROTECTED; + goto outahere; + } + if(val & 0x00100010) { + printf("Programming error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + rc = ERR_PROG_ERROR; + goto outahere; + } + +outahere: + /* read array command */ + *addr = 0x00FF00FF; + if (flag) enable_interrupts(); + + return rc; +} + + +/** + * write_buf: - Copy memory to flash. + * + * @param info: + * @param src: source of copy transaction + * @param addr: where to copy to + * @param cnt: number of bytes to copy + * + * @return error code + */ + +/* "long" version, uses 32bit words */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + ulong data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 24); + } + for (; i<4 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + if ((rc = write_long(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = *((ulong*)src); + if ((rc = write_long(info, wp, data)) != 0) { + return (rc); + } + src += 4; + wp += 4; + cnt -= 4; + } + + if (cnt == 0) return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + return write_long(info, wp, data); +} diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S new file mode 100644 index 0000000..aa9dcba --- /dev/null +++ b/board/csb226/lowlevel_init.S @@ -0,0 +1,437 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + +_TEXT_BASE: + .word TEXT_BASE + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + +/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ +/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ +/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ +/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ +/* */ +/* ldr r1, =LED_BLANK */ +/* mov r0, #0xFF */ +/* str r0, [r1] / turn on hex leds */ +/* */ +/*loop: */ +/* */ +/* ldr r0, =0xB0070001 */ +/* ldr r1, =_LED */ +/* str r0, [r1] / hex display */ + + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ + adr r3, mem_init /* r0 <- current position of code */ + ldr r2, =mem_init + cmp r3, r2 /* skip init if in place */ + beq initirqs + + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + /* Step 4a: assert MDREFR:K?RUN and configure */ + /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ + + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4b: de-assert MDREFR:SLFRSH. */ + + bic r4, r4, #(MDREFR_SLFRSH) + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4c: assert MDREFR:E1PIN and E0PIO */ + + orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + /* There should 9 writes, since the first write doesn't */ + /* trigger a refresh cycle on PXA250. See Intel PXA250 and */ + /* PXA210 Processors Specification Update, */ + /* Jan 2003, Errata #116, page 30. */ + + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + + /* We are finished with Intel's memory controller initialisation */ + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + /* (hard-coding at 398.12MHz for now). */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + + /* default value in case no valid rotary switch setting is found */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + + /* enable the 32Khz oscillator for RTC and PowerManager */ +/* + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] +*/ + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size */ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + + /* FIXME */ + +#ifndef DEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/csb226/u-boot.lds b/board/csb226/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/csb226/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/csb272/Makefile b/board/csb272/Makefile new file mode 100644 index 0000000..926e065 --- /dev/null +++ b/board/csb272/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +#OBJS = $(BOARD).o flash.o +#OBJS = $(BOARD).o strataflash.o +OBJS = $(BOARD).o + +SOBJS = init.o + + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/csb272/config.mk b/board/csb272/config.mk new file mode 100644 index 0000000..4672f08 --- /dev/null +++ b/board/csb272/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2004 +# Tolunay Orkun, NextIO Inc., torkun@nextio.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Cogent CSB272 board +# + +LDFLAGS += $(LINKER_UNDEFS) + +TEXT_BASE := 0xFFFC0000 +#TEXT_BASE := 0x00100000 + +PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS) diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c new file mode 100644 index 0000000..24c6f0d --- /dev/null +++ b/board/csb272/csb272.c @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2004 + * Tolunay Orkun, Nextio Inc., torkun@nextio.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* + * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator + * + * CLKA output => Epson LCD Controller + * CLKB output => Not Connected + * CLKC output => Ethernet + * CLKD output => UART external clock + * + * Note: these values are obtained from device after init by micromonitor +*/ +uchar pll_fs6377_regs[16] = { + 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80, + 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 }; + +/* + * pll_init: Initialize AMIS IC FS6377-01 PLL + * + * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock + * + */ +int pll_init(void) +{ + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + return i2c_write(CFG_I2C_PLL_ADDR, 0, 1, + (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs)); +} + +/* + * board_early_init_f: do early board initialization + * + */ +int board_early_init_f(void) +{ + /* initialize PLL so UART, LCD, Ethernet clocked at correctly */ + (void) get_clocks(); + pll_init(); + + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the Walnut board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive + | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive + | IRQ 27 (EXT IRQ 2) Not Used + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive + | Note for Walnut board: + | An interrupt taken for the FPGA (IRQ 25) indicates that either + | the Mouse, Keyboard, IRDA, or External Expansion caused the + | interrupt. The FPGA must be read to determine which device + | caused the interrupt. The default setting of the FPGA clears + | + +-------------------------------------------------------------------------*/ + + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + mtebc (epcr, 0xa8400000); /* EBC always driven */ + + return 0; /* success */ +} + +/* + * checkboard: identify/verify the board we are running + * + * Remark: we just assume it is correct board here! + * + */ +int checkboard(void) +{ + printf("BOARD: Cogent CSB272\n"); + + return 0; /* success */ +} + +/* + * initram: Determine the size of mounted DRAM + * + * Size is determined by reading SDRAM configuration registers as + * configured by initialization code + * + */ +long initdram (int board_type) +{ + ulong tot_size; + ulong bank_size; + ulong tmp; + + tot_size = 0; + + mtdcr (memcfga, mem_mb0cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + mtdcr (memcfga, mem_mb1cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + mtdcr (memcfga, mem_mb2cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + mtdcr (memcfga, mem_mb3cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + return tot_size; +} + +/* + * last_stage_init: final configurations (such as PHY etc) + * + */ +int last_stage_init(void) +{ + /* initialize the PHY */ + miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); + + /* AUTO neg */ + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + + /* LEDs */ + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); + + + return 0; /* success */ +} diff --git a/board/csb272/init.S b/board/csb272/init.S new file mode 100644 index 0000000..e00ebf8 --- /dev/null +++ b/board/csb272/init.S @@ -0,0 +1,216 @@ +/****************************************************************************** + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + * + *****************************************************************************/ +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#define LI32(reg,val) \ + addis reg,0,val@h;\ + ori reg,reg,val@l + +#define WDCR_EBC(reg,val) \ + addi r4,0,reg;\ + mtdcr ebccfga,r4;\ + addis r4,0,val@h;\ + ori r4,r4,val@l;\ + mtdcr ebccfgd,r4 + +#define WDCR_SDRAM(reg,val) \ + addi r4,0,reg;\ + mtdcr memcfga,r4;\ + addis r4,0,val@h;\ + ori r4,r4,val@l;\ + mtdcr memcfgd,r4 + +/****************************************************************************** + * Function: ext_bus_cntlr_init + * + * Description: Configures EBC Controller and a few basic chip selects. + * + * CS0 is setup to get the Boot Flash out of the addresss range + * so that we may setup a stack. CS7 is setup so that we can + * access and reset the hardware watchdog. + * + * IMPORTANT: For pass1 this code must run from + * cache since you can not reliably change a peripheral banks + * timing register (pbxap) while running code from that bank. + * For ex., since we are running from ROM on bank 0, we can NOT + * execute the code that modifies bank 0 timings from ROM, so + * we run it from cache. + * + * Notes: Does NOT use the stack. + *****************************************************************************/ + .section ".text" + .align 2 + .globl ext_bus_cntlr_init + .type ext_bus_cntlr_init, @function +ext_bus_cntlr_init: + mflr r0 + /******************************************************************** + * Prefetch entire ext_bus_cntrl_init function into the icache. + * This is necessary because we are going to change the same CS we + * are executing from. Otherwise a CPU lockup may occur. + *******************************************************************/ + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + + /* Calculate number of cache lines for this function */ + addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) + mtctr r4 +..ebcloop: + icbt r0, r3 /* prefetch cache line for addr in r3*/ + addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ + bdnz ..ebcloop /* continue for $CTR cache lines */ + + /******************************************************************** + * Delay to ensure all accesses to ROM are complete before changing + * bank 0 timings. 200usec should be enough. + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. + *******************************************************************/ + addis r3, 0, 0x0 + ori r3, r3, 0xA000 /* wait 200us from reset */ + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + /******************************************************************** + * SETUP CPC0_CR0 + *******************************************************************/ + LI32(r4, 0x007000c0) + mtdcr cntrl0, r4 + + /******************************************************************** + * Setup CPC0_CR1: Change PCIINT signal to PerWE + *******************************************************************/ + mfdcr r4, cntrl1 + ori r4, r4, 0x4000 + mtdcr cntrl1, r4 + + /******************************************************************** + * Setup External Bus Controller (EBC). + *******************************************************************/ + WDCR_EBC(epcr, 0xd84c0000) + /******************************************************************** + * Memory Bank 0 (Intel 28F128J3 Flash) initialization + *******************************************************************/ + /*WDCR_EBC(pb0ap, 0x02869200)*/ + WDCR_EBC(pb0ap, 0x07869200) + WDCR_EBC(pb0cr, 0xfe0bc000) + /******************************************************************** + * Memory Bank 1 (Holtek HT6542B PS/2) initialization + *******************************************************************/ + WDCR_EBC(pb1ap, 0x1f869200) + WDCR_EBC(pb1cr, 0xf0818000) + /******************************************************************** + * Memory Bank 2 (Epson S1D13506) initialization + *******************************************************************/ + WDCR_EBC(pb2ap, 0x05860300) + WDCR_EBC(pb2cr, 0xf045a000) + /******************************************************************** + * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization + *******************************************************************/ + WDCR_EBC(pb3ap, 0x0387d200) + WDCR_EBC(pb3cr, 0xf021c000) + /******************************************************************** + * Memory Bank 4-7 (Unused) initialization + *******************************************************************/ + WDCR_EBC(pb4ap, 0) + WDCR_EBC(pb4cr, 0) + WDCR_EBC(pb5ap, 0) + WDCR_EBC(pb5cr, 0) + WDCR_EBC(pb6ap, 0) + WDCR_EBC(pb6cr, 0) + WDCR_EBC(pb7ap, 0) + WDCR_EBC(pb7cr, 0) + + /* We are all done */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ +.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init +/* end ext_bus_cntlr_init() */ + +/****************************************************************************** + * Function: sdram_init + * + * Description: Configures SDRAM memory banks. + * + * Notes: Does NOT use the stack. + *****************************************************************************/ + .section ".text" + .align 2 + .globl sdram_init + .type sdram_init, @function +sdram_init: + + /* + * Disable memory controller to allow + * values to be changed. + */ + WDCR_SDRAM(mem_mcopt1, 0x00000000) + + /* + * Configure Memory Banks + */ + WDCR_SDRAM(mem_mb0cf, 0x00084001) + WDCR_SDRAM(mem_mb1cf, 0x00000000) + WDCR_SDRAM(mem_mb2cf, 0x00000000) + WDCR_SDRAM(mem_mb3cf, 0x00000000) + + /* + * Set up SDTR1 (SDRAM Timing Register) + */ + WDCR_SDRAM(mem_sdtr1, 0x00854009) + + /* + * Set RTR (Refresh Timing Register) + */ + WDCR_SDRAM(mem_rtr, 0x10000000) + /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ + + /******************************************************************** + * Delay to ensure 200usec have elapsed since reset. Assume worst + * case that the core is running 200Mhz: + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + *******************************************************************/ + addis r3, 0, 0x0000 + ori r3, r3, 0xA000 /* Wait >200us from reset */ + mtctr r3 +..spinlp2: + bdnz ..spinlp2 /* spin loop */ + + /******************************************************************** + * Set memory controller options reg, MCOPT1. + *******************************************************************/ + WDCR_SDRAM(mem_mcopt1,0x80800000) + +..sdri_done: + blr /* Return to calling function */ +.Lfe1: .size sdram_init,.Lfe1-sdram_init +/* end sdram_init() */ diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds new file mode 100644 index 0000000..d75d6d1 --- /dev/null +++ b/board/csb272/u-boot.lds @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/csb272/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + + lib_ppc/extable.o (.text) + lib_ppc/board.o (.text) + lib_generic/zlib.o (.text) +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/csb472/Makefile b/board/csb472/Makefile new file mode 100644 index 0000000..926e065 --- /dev/null +++ b/board/csb472/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +#OBJS = $(BOARD).o flash.o +#OBJS = $(BOARD).o strataflash.o +OBJS = $(BOARD).o + +SOBJS = init.o + + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/csb472/config.mk b/board/csb472/config.mk new file mode 100644 index 0000000..04aefd1 --- /dev/null +++ b/board/csb472/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2004 +# Tolunay Orkun, NextIO Inc., torkun@nextio.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Cogent CSB472 board +# + +LDFLAGS += $(LINKER_UNDEFS) + +TEXT_BASE := 0xFFFC0000 +#TEXT_BASE := 0x00100000 + +PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS) diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c new file mode 100644 index 0000000..833bbce --- /dev/null +++ b/board/csb472/csb472.c @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2004 + * Tolunay Orkun, Nextio Inc., torkun@nextio.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* + * board_early_init_f: do early board initialization + * + */ +int board_early_init_f(void) +{ + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the Walnut board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive + | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive + | IRQ 27 (EXT IRQ 2) Not Used + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive + | Note for Walnut board: + | An interrupt taken for the FPGA (IRQ 25) indicates that either + | the Mouse, Keyboard, IRDA, or External Expansion caused the + | interrupt. The FPGA must be read to determine which device + | caused the interrupt. The default setting of the FPGA clears + | + +-------------------------------------------------------------------------*/ + + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + mtebc (epcr, 0xa8400000); /* EBC always driven */ + + return 0; /* success */ +} + +/* + * checkboard: identify/verify the board we are running + * + * Remark: we just assume it is correct board here! + * + */ +int checkboard(void) +{ + printf("BOARD: Cogent CSB472\n"); + + return 0; /* success */ +} + +/* + * initram: Determine the size of mounted DRAM + * + * Size is determined by reading SDRAM configuration registers as + * configured by initialization code + * + */ +long initdram (int board_type) +{ + ulong tot_size; + ulong bank_size; + ulong tmp; + + tot_size = 0; + + mtdcr (memcfga, mem_mb0cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + mtdcr (memcfga, mem_mb1cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + mtdcr (memcfga, mem_mb2cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + mtdcr (memcfga, mem_mb3cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + return tot_size; +} + +/* + * last_stage_init: final configurations (such as PHY etc) + * + */ +int last_stage_init(void) +{ + /* initialize the PHY */ + miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); + + /* AUTO neg */ + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + + /* LEDs */ + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); + + return 0; /* success */ +} diff --git a/board/csb472/init.S b/board/csb472/init.S new file mode 100644 index 0000000..aec42a1 --- /dev/null +++ b/board/csb472/init.S @@ -0,0 +1,212 @@ +/****************************************************************************** + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + * + *****************************************************************************/ +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#define LI32(reg,val) \ + addis reg,0,val@h;\ + ori reg,reg,val@l + +#define WDCR_EBC(reg,val) \ + addi r4,0,reg;\ + mtdcr ebccfga,r4;\ + addis r4,0,val@h;\ + ori r4,r4,val@l;\ + mtdcr ebccfgd,r4 + +#define WDCR_SDRAM(reg,val) \ + addi r4,0,reg;\ + mtdcr memcfga,r4;\ + addis r4,0,val@h;\ + ori r4,r4,val@l;\ + mtdcr memcfgd,r4 + +/****************************************************************************** + * Function: ext_bus_cntlr_init + * + * Description: Configures EBC Controller and a few basic chip selects. + * + * CS0 is setup to get the Boot Flash out of the addresss range + * so that we may setup a stack. CS7 is setup so that we can + * access and reset the hardware watchdog. + * + * IMPORTANT: For pass1 this code must run from + * cache since you can not reliably change a peripheral banks + * timing register (pbxap) while running code from that bank. + * For ex., since we are running from ROM on bank 0, we can NOT + * execute the code that modifies bank 0 timings from ROM, so + * we run it from cache. + * + * Notes: Does NOT use the stack. + *****************************************************************************/ + .section ".text" + .align 2 + .globl ext_bus_cntlr_init + .type ext_bus_cntlr_init, @function +ext_bus_cntlr_init: + mflr r0 + /******************************************************************** + * Prefetch entire ext_bus_cntrl_init function into the icache. + * This is necessary because we are going to change the same CS we + * are executing from. Otherwise a CPU lockup may occur. + *******************************************************************/ + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + + /* Calculate number of cache lines for this function */ + addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) + mtctr r4 +..ebcloop: + icbt r0, r3 /* prefetch cache line for addr in r3*/ + addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ + bdnz ..ebcloop /* continue for $CTR cache lines */ + + /******************************************************************** + * Delay to ensure all accesses to ROM are complete before changing + * bank 0 timings. 200usec should be enough. + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. + *******************************************************************/ + addis r3, 0, 0x0 + ori r3, r3, 0xA000 /* wait 200us from reset */ + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + /******************************************************************** + * SETUP CPC0_CR0 + *******************************************************************/ + LI32(r4, 0x00c01030) + mtdcr cntrl0, r4 + + /******************************************************************** + * Setup CPC0_CR1: Change PCIINT signal to PerWE + *******************************************************************/ + mfdcr r4, cntrl1 + ori r4, r4, 0x4000 + mtdcr cntrl1, r4 + + /******************************************************************** + * Setup External Bus Controller (EBC). + *******************************************************************/ + WDCR_EBC(epcr, 0xd84c0000) + /******************************************************************** + * Memory Bank 0 (Intel 28F640J3 Flash) initialization + *******************************************************************/ + /*WDCR_EBC(pb0ap, 0x03055200)*/ + /*WDCR_EBC(pb0ap, 0x04055200)*/ + WDCR_EBC(pb0ap, 0x08055200) + WDCR_EBC(pb0cr, 0xff87a000) + /******************************************************************** + * Memory Bank 3 (Xilinx XC95144 CPLD) initialization + *******************************************************************/ + /*WDCR_EBC(pb3ap, 0x07869200)*/ + WDCR_EBC(pb3ap, 0x04055200) + WDCR_EBC(pb3cr, 0xf081c000) + /******************************************************************** + * Memory Bank 1,2,4-7 (Unused) initialization + *******************************************************************/ + WDCR_EBC(pb1ap, 0) + WDCR_EBC(pb1cr, 0) + WDCR_EBC(pb2ap, 0) + WDCR_EBC(pb2cr, 0) + WDCR_EBC(pb4ap, 0) + WDCR_EBC(pb4cr, 0) + WDCR_EBC(pb5ap, 0) + WDCR_EBC(pb5cr, 0) + WDCR_EBC(pb6ap, 0) + WDCR_EBC(pb6cr, 0) + WDCR_EBC(pb7ap, 0) + WDCR_EBC(pb7cr, 0) + + /* We are all done */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ +.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init +/* end ext_bus_cntlr_init() */ + +/****************************************************************************** + * Function: sdram_init + * + * Description: Configures SDRAM memory banks. + * + * Notes: Does NOT use the stack. + *****************************************************************************/ + .section ".text" + .align 2 + .globl sdram_init + .type sdram_init, @function +sdram_init: + + /* + * Disable memory controller to allow + * values to be changed. + */ + WDCR_SDRAM(mem_mcopt1, 0x00000000) + + /* + * Configure Memory Banks + */ + WDCR_SDRAM(mem_mb0cf, 0x00062001) + WDCR_SDRAM(mem_mb1cf, 0x00000000) + WDCR_SDRAM(mem_mb2cf, 0x00000000) + WDCR_SDRAM(mem_mb3cf, 0x00000000) + + /* + * Set up SDTR1 (SDRAM Timing Register) + */ + WDCR_SDRAM(mem_sdtr1, 0x00854009) + + /* + * Set RTR (Refresh Timing Register) + */ + WDCR_SDRAM(mem_rtr, 0x10000000) + /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ + + /******************************************************************** + * Delay to ensure 200usec have elapsed since reset. Assume worst + * case that the core is running 200Mhz: + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + *******************************************************************/ + addis r3, 0, 0x0000 + ori r3, r3, 0xA000 /* Wait >200us from reset */ + mtctr r3 +..spinlp2: + bdnz ..spinlp2 /* spin loop */ + + /******************************************************************** + * Set memory controller options reg, MCOPT1. + *******************************************************************/ + WDCR_SDRAM(mem_mcopt1,0x80800000) + +..sdri_done: + blr /* Return to calling function */ +.Lfe1: .size sdram_init,.Lfe1-sdram_init +/* end sdram_init() */ diff --git a/board/csb472/u-boot.lds b/board/csb472/u-boot.lds new file mode 100644 index 0000000..14ac3fb --- /dev/null +++ b/board/csb472/u-boot.lds @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/csb472/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + + lib_ppc/extable.o (.text) + lib_ppc/board.o (.text) + lib_generic/zlib.o (.text) +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/csb637/Makefile b/board/csb637/Makefile new file mode 100644 index 0000000..61d5a35 --- /dev/null +++ b/board/csb637/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := csb637.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/csb637/config.mk b/board/csb637/config.mk new file mode 100644 index 0000000..4c6f631 --- /dev/null +++ b/board/csb637/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23fc0000 diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c new file mode 100644 index 0000000..6100a53 --- /dev/null +++ b/board/csb637/csb637.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2005 REA Elektronik GmbH + * Anders Larsen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Enable Ctrlc */ + console_init_f (); + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of CSB637-Board */ + gd->bd->bi_arch_number = MACH_TYPE_CSB637; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_DRIVER_ETHER +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * at91rm9200_GetPhyInterface + * Description: + * Initialise the interface functions to the PHY + * Arguments: + * None + * Return value: + * None + */ +void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) +{ + p_phyops->Init = bcm5221_InitPhy; + p_phyops->IsPhyConnected = bcm5221_IsPhyConnected; + p_phyops->GetLinkSpeed = bcm5221_GetLinkSpeed; + p_phyops->AutoNegotiate = bcm5221_AutoNegotiate; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/csb637/u-boot.lds b/board/csb637/u-boot.lds new file mode 100644 index 0000000..76df6b2 --- /dev/null +++ b/board/csb637/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/cu824/Makefile b/board/cu824/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/cu824/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cu824/README b/board/cu824/README new file mode 100644 index 0000000..cc0d207 --- /dev/null +++ b/board/cu824/README @@ -0,0 +1,453 @@ +ppcboot for a CU824 board +--------------------------- + +CU824 has two banks of flash 8MB each. In board's notation, bank 0 is +the one at the address of 0xFF800000 and bank 1 is the one at the +address of 0xFF000000. On power-up the processor jumps to the address +of 0xFFF00100, the last megabyte of the bank 0 of flash. Thus, +U-Boot is configured to reside in flash starting at the address of +0xFFF00000. The environment space is not embedded in the U-Boot code +and is located in flash separately from U-Boot, at the address of +0xFF008000. + + +U-Boot test results +-------------------- + +x.x Operation on all available serial consoles + +x.x.x CONFIG_CONS_INDEX 1 + + +ppcboot 0.9.2 (May 13 2001 - 17:56:46) + +Initializing... + CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache + Board: CU824 Revision 1 Local Bus at 99 MHz + DRAM: 64 MB + FLASH: 16 MB + In: serial + Out: serial + Err: serial + +Hit any key to stop autoboot: 0 +=> +=>he +go - start application at address 'addr' +run - run commands in an environment variable +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +tftpboot- boot image via network using TFTP protocol + and env variables ipaddr and serverip +rarpboot- boot image via network using RARP/TFTP protocol +bootd - boot default, i.e., run 'bootcmd' +loads - load S-Record file over serial line +loadb - load binary file over serial line (kermit mode) +md - memory display +mm - memory modify (auto-incrementing) +nm - memory modify (constant address) +mw - memory write (fill) +cp - memory copy +cmp - memory compare +crc32 - checksum calculation +base - print or set address offset +printenv- print environment variables +setenv - set environment variables +saveenv - save environment variables to persistent storage +protect - enable or disable FLASH write protection +erase - erase FLASH memory +flinfo - print FLASH memory information +bdinfo - print Board Info structure +iminfo - print header information for application image +coninfo - print console devices and informations +loop - infinite loop on address range +mtest - simple RAM test +icache - enable or disable instruction cache +dcache - enable or disable data cache +reset - Perform RESET of the CPU +echo - echo args to console +version - print monitor version +help - print online help +? - alias for 'help' +=> + + +x.x.x CONFIG_CONS_INDEX 2 + +**** NOT TESTED **** + +x.x Flash Driver Operation + +x.x.x Erase Operation + + +ppcboot 0.9.2 (May 13 2001 - 17:56:46) + +Initializing... + CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache + Board: CU824 Revision 1 Local Bus at 99 MHz + DRAM: 64 MB + FLASH: 16 MB + In: serial + Out: serial + Err: serial + +Hit any key to stop autoboot: 0 +=> +=> +=> +=>md ff000000 +ff000000: 27051956 70706362 6f6f7420 302e382e '..Vppcboot 0.8. +ff000010: 3320284d 61792031 31203230 3031202d 3 (May 11 2001 - +ff000020: 2031343a 35373a30 33290000 00000000 14:57:03)...... +ff000030: 00000000 00000000 00000000 00000000 ................ +ff000040: 00000000 00000000 00000000 00000000 ................ +ff000050: 00000000 00000000 00000000 00000000 ................ +ff000060: 00000000 00000000 00000000 00000000 ................ +ff000070: 00000000 00000000 00000000 00000000 ................ +ff000080: 00000000 00000000 00000000 00000000 ................ +ff000090: 00000000 00000000 00000000 00000000 ................ +ff0000a0: 00000000 00000000 00000000 00000000 ................ +ff0000b0: 00000000 00000000 00000000 00000000 ................ +ff0000c0: 00000000 00000000 00000000 00000000 ................ +ff0000d0: 00000000 00000000 00000000 00000000 ................ +ff0000e0: 00000000 00000000 00000000 00000000 ................ +ff0000f0: 00000000 00000000 00000000 00000000 ................ +=>erase ff000000 ff007fff +Erase Flash from 0xff000000 to 0xff007fff + done +Erased 1 sectors +=>md ff000000 +ff000000: ffffffff ffffffff ffffffff ffffffff ................ +ff000010: ffffffff ffffffff ffffffff ffffffff ................ +ff000020: ffffffff ffffffff ffffffff ffffffff ................ +ff000030: ffffffff ffffffff ffffffff ffffffff ................ +ff000040: ffffffff ffffffff ffffffff ffffffff ................ +ff000050: ffffffff ffffffff ffffffff ffffffff ................ +ff000060: ffffffff ffffffff ffffffff ffffffff ................ +ff000070: ffffffff ffffffff ffffffff ffffffff ................ +ff000080: ffffffff ffffffff ffffffff ffffffff ................ +ff000090: ffffffff ffffffff ffffffff ffffffff ................ +ff0000a0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000b0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000c0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000d0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000e0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000f0: ffffffff ffffffff ffffffff ffffffff ................ +=> + +x.x.x Information + + +ppcboot 0.9.2 (May 13 2001 - 17:56:46) + +Initializing... + CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache + Board: CU824 Revision 1 Local Bus at 99 MHz + DRAM: 64 MB + FLASH: 16 MB + In: serial + Out: serial + Err: serial + +Hit any key to stop autoboot: 0 +=> +=> +=> +=> +=>flinfo + +Bank # 1: Intel: 28F160F3B (16Mbit) + Size: 8 MB in 39 Sectors + Sector Start Addresses: + FF000000 FF008000 (RO) FF010000 FF018000 FF020000 + FF028000 FF030000 FF038000 FF040000 FF080000 + FF0C0000 FF100000 FF140000 FF180000 FF1C0000 + FF200000 FF240000 FF280000 FF2C0000 FF300000 + FF340000 FF380000 FF3C0000 FF400000 FF440000 + FF480000 FF4C0000 FF500000 FF540000 FF580000 + FF5C0000 FF600000 FF640000 FF680000 FF6C0000 + FF700000 FF740000 FF780000 FF7C0000 + +Bank # 2: Intel: 28F160F3B (16Mbit) + Size: 8 MB in 39 Sectors + Sector Start Addresses: + FF800000 FF808000 FF810000 FF818000 FF820000 + FF828000 FF830000 FF838000 FF840000 FF880000 + FF8C0000 FF900000 FF940000 FF980000 FF9C0000 + FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000 + FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000 + FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000 + FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000 + FFF00000 (RO) FFF40000 FFF80000 FFFC0000 +=> + +x.x.x Flash Programming + + +ppcboot 0.9.2 (May 13 2001 - 17:56:46) + +Initializing... + CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache + Board: CU824 Revision 1 Local Bus at 99 MHz + DRAM: 64 MB + FLASH: 16 MB + In: serial + Out: serial + Err: serial + +Hit any key to stop autoboot: 0 +=> +=> +=> +=> +=>cp 0 ff000000 20 +Copy to Flash... done +=>md 0 +00000000: 0ec08ce0 03f9800c 00000001 040c0000 ................ +00000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................ +00000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4. +00000030: 03fcd5bc 03fcdabc 00000000 00000000 ................ +00000040: 00000000 00000000 00000000 00000000 ................ +00000050: 00000000 00000000 00000000 00000000 ................ +00000060: 00000000 00000000 00000000 00000000 ................ +00000070: 00000000 00000000 00000000 00000000 ................ +00000080: 00000000 00000000 00000000 00000000 ................ +00000090: 00000000 00000000 00000000 00000000 ................ +000000a0: 00000000 00000000 00000000 00000000 ................ +000000b0: 00000000 00000000 00000000 00000000 ................ +000000c0: 00000000 00000000 00000000 00000000 ................ +000000d0: 00000000 00000000 00000000 00000000 ................ +000000e0: 00000000 00000000 00000000 00000000 ................ +000000f0: 00000000 00000000 00000000 00000000 ................ +=>md ff000000 +ff000000: 0ec08ce0 03f9800c 00000001 040c0000 ................ +ff000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................ +ff000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4. +ff000030: 03fcd5bc 03fcdabc 00000000 00000000 ................ +ff000040: 00000000 00000000 00000000 00000000 ................ +ff000050: 00000000 00000000 00000000 00000000 ................ +ff000060: 00000000 00000000 00000000 00000000 ................ +ff000070: 00000000 00000000 00000000 00000000 ................ +ff000080: ffffffff ffffffff ffffffff ffffffff ................ +ff000090: ffffffff ffffffff ffffffff ffffffff ................ +ff0000a0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000b0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000c0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000d0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000e0: ffffffff ffffffff ffffffff ffffffff ................ +ff0000f0: ffffffff ffffffff ffffffff ffffffff ................ +=> + +x.x.x Storage of environment variables in flash + + +ppcboot 0.9.2 (May 13 2001 - 17:56:46) + +Initializing... + CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache + Board: CU824 Revision 1 Local Bus at 99 MHz + DRAM: 64 MB + FLASH: 16 MB + In: serial + Out: serial + Err: serial + +Hit any key to stop autoboot: 0 +=> +=>printenv +bootargs= +bootcmd=bootm FE020000 +bootdelay=5 +baudrate=9600 +ipaddr=192.168.4.2 +serverip=192.168.4.1 +ethaddr=00:40:42:01:00:a0 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 167/32764 bytes +=>setenv myvar 1234 +=>save_env +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Saving Environment to Flash... +Protected 1 sectors +=>reset + + +ppcboot 0.9.2 (May 13 2001 - 17:56:46) + +Initializing... + CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache + Board: CU824 Revision 1 Local Bus at 99 MHz + DRAM: 64 MB + FLASH: 16 MB + In: serial + Out: serial + Err: serial + +Hit any key to stop autoboot: 0 +=> +=>printenv +bootargs= +bootcmd=bootm FE020000 +bootdelay=5 +baudrate=9600 +ipaddr=192.168.4.2 +serverip=192.168.4.1 +ethaddr=00:40:42:01:00:a0 +myvar=1234 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 178/32764 bytes +=> + +x.x Image Download and run over serial port + + +ppcboot 0.9.2 (May 13 2001 - 17:56:46) + +Initializing... + CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache + Board: CU824 Revision 1 Local Bus at 99 MHz + DRAM: 64 MB + FLASH: 16 MB + In: serial + Out: serial + Err: serial + +Hit any key to stop autoboot: 0 +=> +=> +=>mw 40000 0 10000 +=>md 40000 +00040000: 00000000 00000000 00000000 00000000 ................ +00040010: 00000000 00000000 00000000 00000000 ................ +00040020: 00000000 00000000 00000000 00000000 ................ +00040030: 00000000 00000000 00000000 00000000 ................ +00040040: 00000000 00000000 00000000 00000000 ................ +00040050: 00000000 00000000 00000000 00000000 ................ +00040060: 00000000 00000000 00000000 00000000 ................ +00040070: 00000000 00000000 00000000 00000000 ................ +00040080: 00000000 00000000 00000000 00000000 ................ +00040090: 00000000 00000000 00000000 00000000 ................ +000400a0: 00000000 00000000 00000000 00000000 ................ +000400b0: 00000000 00000000 00000000 00000000 ................ +000400c0: 00000000 00000000 00000000 00000000 ................ +000400d0: 00000000 00000000 00000000 00000000 ................ +000400e0: 00000000 00000000 00000000 00000000 ................ +000400f0: 00000000 00000000 00000000 00000000 ................ +=>loads +## Ready for S-Record download ... + +(Back at xpert.denx.de) +[vlad@xpert vlad]$ cat hello_world.srec >/dev/ttyS0 +[vlad@xpert vlad]$ kermit -l /dev/ttyS0 -b 9600 -c +Connecting to /dev/ttyS0, speed 9600. +The escape character is Ctrl-\ (ASCII 28, FS) +Type the escape character followed by C to get back, +or followed by ? to see other options. +md 40000 +00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. +00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... +00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x +00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. +00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x +00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! +00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8 +00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... +00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. +00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... +000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|... +000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|... +000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8 +000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8 +000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! +000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. +=>go 40004 +## Starting application at 0x00040004 ... +Hello World +argc = 1 +argv[0] = "40004" +argv[1] = "" +Hit any key to exit ... + +## Application terminated, rc = 0x0 +=> + +x.x Image download and run over ethernet interface + + +ppcboot 0.9.2 (May 13 2001 - 17:56:46) + +Initializing... + CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache + Board: CU824 Revision 1 Local Bus at 99 MHz + DRAM: 64 MB + FLASH: 16 MB + In: serial + Out: serial + Err: serial + +Hit any key to stop autoboot: 0 +=> +=> +=>mw 40000 0 10000 +=>md 40000 +00040000: 00000000 00000000 00000000 00000000 ................ +00040010: 00000000 00000000 00000000 00000000 ................ +00040020: 00000000 00000000 00000000 00000000 ................ +00040030: 00000000 00000000 00000000 00000000 ................ +00040040: 00000000 00000000 00000000 00000000 ................ +00040050: 00000000 00000000 00000000 00000000 ................ +00040060: 00000000 00000000 00000000 00000000 ................ +00040070: 00000000 00000000 00000000 00000000 ................ +00040080: 00000000 00000000 00000000 00000000 ................ +00040090: 00000000 00000000 00000000 00000000 ................ +000400a0: 00000000 00000000 00000000 00000000 ................ +000400b0: 00000000 00000000 00000000 00000000 ................ +000400c0: 00000000 00000000 00000000 00000000 ................ +000400d0: 00000000 00000000 00000000 00000000 ................ +000400e0: 00000000 00000000 00000000 00000000 ................ +000400f0: 00000000 00000000 00000000 00000000 ................ +=>tftpboot 40000 hello_world.bin +ARP broadcast 1 +TFTP from server 192.168.4.1; our IP address is 192.168.4.2 +Filename 'hello_world.bin'. +Load address: 0x40000 +Loading: ############# +done +Bytes transferred = 65912 (10178 hex) +=>md 40000 +00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. +00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... +00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x +00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. +00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x +00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! +00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8 +00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... +00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. +00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... +000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|... +000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|... +000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8 +000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8 +000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! +000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. +=>go 40004 +## Starting application at 0x00040004 ... +Hello World +argc = 1 +argv[0] = "40004" +argv[1] = "" +Hit any key to exit ... + +## Application terminated, rc = 0x0 +=> diff --git a/board/cu824/config.mk b/board/cu824/config.mk new file mode 100644 index 0000000..18673e1 --- /dev/null +++ b/board/cu824/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# CU824 board +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c new file mode 100644 index 0000000..5844a5c --- /dev/null +++ b/board/cu824/cu824.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define BOARD_REV_REG 0xFE80002B + +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char revision = *(volatile char *)(BOARD_REV_REG); + char buf[32]; + + puts ("Board: CU824 "); + printf("Revision %d ", revision); + printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk)); + + return 0; +} + +long int initdram(int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_sandpoint_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_sandpoint_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} diff --git a/board/cu824/flash.c b/board/cu824/flash.c new file mode 100644 index 0000000..7368176 --- /dev/null +++ b/board/cu824/flash.c @@ -0,0 +1,486 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#define FLASH_BANK_SIZE 0x800000 +#define MAIN_SECT_SIZE 0x40000 +#define PARAM_SECT_SIZE 0x8000 + +#define BOARD_CTRL_REG 0xFE800013 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static int write_data (flash_info_t *info, ulong dest, ulong *data); +static void write_via_fpu(vu_long *addr, ulong *data); +static __inline__ unsigned long get_msr(void); +static __inline__ void set_msr(unsigned long msr); + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +/*---------------------------------------------------------------------*/ +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + int i, j; + ulong size = 0; + volatile unsigned char *bcr = (volatile unsigned char *)(BOARD_CTRL_REG); + + DEBUGF("Write protect was: 0x%02X\n", *bcr); + *bcr &= 0x1; /* FWPT must be 0 */ + *bcr |= 0x6; /* FWP0 = FWP1 = 1 */ + DEBUGF("Write protect is: 0x%02X\n", *bcr); + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + + addr[0] = 0x00900090; + + DEBUGF ("Flash bank # %d:\n" + "\tManuf. ID @ 0x%08lX: 0x%08lX\n" + "\tDevice ID @ 0x%08lX: 0x%08lX\n", + i, + (ulong)(&addr[0]), addr[0], + (ulong)(&addr[2]), addr[2]); + + if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && + (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B)) + { + flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) | + (INTEL_ID_28F160F3B & FLASH_TYPEMASK); + } else { + flash_info[i].flash_id = FLASH_UNKNOWN; + addr[0] = 0xFFFFFFFF; + goto Done; + } + + DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); + + addr[0] = 0xFFFFFFFF; + + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j <= 7) { + flash_info[i].start[j] = CFG_FLASH_BASE + + i * FLASH_BANK_SIZE + + j * PARAM_SECT_SIZE; + } else { + flash_info[i].start[j] = CFG_FLASH_BASE + + i * FLASH_BANK_SIZE + + (j - 7)*MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[1]); +#else + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[1]); +#else + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif +#endif + +Done: + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch ((i = info->flash_id & FLASH_VENDMASK)) { + case (FLASH_MAN_INTEL & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor 0x%04x ", i); + break; + } + + switch ((i = info->flash_id & FLASH_TYPEMASK)) { + case (INTEL_ID_28F160F3B & FLASH_TYPEMASK): + printf ("28F160F3B (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type 0x%04x\n", i); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: + return; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + DEBUGF ("Erase flash bank %d sect %d ... %d\n", + info - &flash_info[0], s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (FLASH_MAN_INTEL & FLASH_VENDMASK)) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + + DEBUGF ("Erase sect %d @ 0x%08lX\n", + sect, (ulong)addr); + + /* Disable interrupts which might cause a timeout + * here. + */ + flag = disable_interrupts(); + + addr[0] = 0x00500050; /* clear status register */ + addr[0] = 0x00200020; /* erase setup */ + addr[0] = 0x00D000D0; /* erase confirm */ + + addr[1] = 0x00500050; /* clear status register */ + addr[1] = 0x00200020; /* erase setup */ + addr[1] = 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((addr[0] & 0x00800080) != 0x00800080) || + ((addr[1] & 0x00800080) != 0x00800080) ) { + if ((now=get_timer(start)) > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + addr[0] = 0x00B000B0; /* suspend erase */ + addr[0] = 0x00FF00FF; /* to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + addr[0] = 0x00FF00FF; + } + } + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 8 /* flash bus width in bytes */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp, cp, msr; + int l, rc, i; + ulong data[2]; + ulong *datah = &data[0]; + ulong *datal = &data[1]; + + DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", + addr, (ulong)src, cnt); + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + msr = get_msr(); + set_msr(msr | MSR_FP); + + wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + *datah = *datal = 0; + + for (i = 0, cp = wp; i < l; i++, cp++) { + if (i >= 4) { + *datah = (*datah << 8) | + ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | (*(uchar *)cp); + } + for (; i < FLASH_WIDTH && cnt > 0; ++i) { + char tmp; + + tmp = *src; + + src++; + + if (i >= 4) { + *datah = (*datah << 8) | + ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | tmp; + + --cnt; ++cp; + } + + for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { + if (i >= 4) { + *datah = (*datah << 8) | + ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datah << 8) | (*(uchar *)cp); + } + + if ((rc = write_data(info, wp, data)) != 0) { + set_msr(msr); + return (rc); + } + + wp += FLASH_WIDTH; + } + + /* + * handle FLASH_WIDTH aligned part + */ + while (cnt >= FLASH_WIDTH) { + *datah = *(ulong *)src; + *datal = *(ulong *)(src + 4); + if ((rc = write_data(info, wp, data)) != 0) { + set_msr(msr); + return (rc); + } + wp += FLASH_WIDTH; + cnt -= FLASH_WIDTH; + src += FLASH_WIDTH; + } + + if (cnt == 0) { + set_msr(msr); + return (0); + } + + /* + * handle unaligned tail bytes + */ + *datah = *datal = 0; + for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { + char tmp; + + tmp = *src; + + src++; + + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | tmp; + + --cnt; + } + + for (; i < FLASH_WIDTH; ++i, ++cp) { + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | (*(uchar *)cp); + } + + rc = write_data(info, wp, data); + set_msr(msr); + + return (rc); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, ulong *data) +{ + vu_long *addr = (vu_long *)dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if (((addr[0] & data[0]) != data[0]) || + ((addr[1] & data[1]) != data[1]) ) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0] = 0x00400040; /* write setup */ + write_via_fpu(addr, data); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (((addr[0] & 0x00800080) != 0x00800080) || + ((addr[1] & 0x00800080) != 0x00800080) ) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + addr[0] = 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + addr[0] = 0x00FF00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + */ +static void write_via_fpu(vu_long *addr, ulong *data) +{ + __asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data)); + __asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr)); +} +/*----------------------------------------------------------------------- + */ +static __inline__ unsigned long get_msr(void) +{ + unsigned long msr; + + __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr(unsigned long msr) +{ + __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); +} diff --git a/board/cu824/u-boot.lds b/board/cu824/u-boot.lds new file mode 100644 index 0000000..7be85e4 --- /dev/null +++ b/board/cu824/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/dave/B2/B2.c b/board/dave/B2/B2.c new file mode 100644 index 0000000..29676b8 --- /dev/null +++ b/board/dave/B2/B2.c @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * Miscelaneous platform dependent initialization + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + u32 temp; + + /* Configuration Port Control Register*/ + /* Port A */ + PCONA = 0x3ff; + + /* Port B */ + PCONB = 0xff; + PDATB = 0xFFFF; + + /* Port C */ + /* + PCONC = 0xff55ff15; + PDATC = 0x0; + PUPC = 0xffff; + */ + + /* Port D */ + /* + PCOND = 0xaaaa; + PUPD = 0xff; + */ + + /* Port E */ + PCONE = 0x0001aaa9; + PDATE = 0x0; + PUPE = 0xff; + + /* Port F */ + PCONF = 0x124955; + PDATF = 0xff; /* B2-eth_reset tied high level */ + /* + PUPF = 0x1e3; + */ + + /* Port G */ + PUPG = 0x1; + PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/ + + INTMSK = 0x03fffeff; + INTCON = 0x05; + + /* + Configure chip ethernet interrupt as High level + Port G EINT 0-7 EINT0 -> CHIP ETHERNET + */ + temp = EXTINT; + temp &= ~0x7; + temp |= 0x1; /*LEVEL_HIGH*/ + EXTINT = temp; + + /* + Reset SMSC LAN91C96 chip + */ + temp= PCONF; + temp |= 0x00000040; + PCONF = temp; + + /* Reset high */ + temp = PDATF; + temp |= (1 << 3); + PDATF = temp; + + /* Short delay */ + for (temp=0;temp<10;temp++) + { + /* NOP */ + } + + /* Reset low */ + temp = PDATF; + temp &= ~(1 << 3); + PDATF = temp; + + /* arch number MACH_TYPE_MBA44B0 */ + gd->bd->bi_arch_number = MACH_TYPE_S3C44B0; + + /* location of boot parameters */ + gd->bd->bi_boot_params = 0x0c000100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/dave/B2/Makefile b/board/dave/B2/Makefile new file mode 100644 index 0000000..548fd52 --- /dev/null +++ b/board/dave/B2/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := B2.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/dave/B2/config.mk b/board/dave/B2/config.mk new file mode 100644 index 0000000..5216622 --- /dev/null +++ b/board/dave/B2/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x0C100000 + +PLATFORM_CPPFLAGS += -Uarm diff --git a/board/dave/B2/flash.c b/board/dave/B2/flash.c new file mode 100644 index 0000000..ad67e86 --- /dev/null +++ b/board/dave/B2/flash.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ +#ifdef __DEBUG_START_FROM_SRAM__ + return CFG_DUMMY_FLASH_SIZE; +#else + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; i $@ + +sinclude .depend + +######################################################################### diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c new file mode 100644 index 0000000..5f2c705 --- /dev/null +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2003 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); + +int board_early_init_f (void) +{ + out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */ + out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) + * IRQ 26 (EXT IRQ 1) + * IRQ 27 (EXT IRQ 2) + * IRQ 28 (EXT IRQ 3) + * IRQ 29 (EXT IRQ 4) + * IRQ 30 (EXT IRQ 5) + * IRQ 31 (EXT IRQ 6) + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ +#if 1 /* test-only */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ +#else + mtebc (epcr, 0x28400000); /* ebc in high-z */ +#endif + return 0; +} + +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* adjust flash start and size as well as the offset */ + gd->bd->bi_flashstart = 0 - flash_info[0].size; + gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN; +#if 0 + volatile unsigned short *fpga_mode = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned char *duart0_mcr = + (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = + (unsigned char *)((ulong)DUART1_BA + 4); + + bd_t *bd = gd->bd; + char * tmp; /* Temporary char pointer */ + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + unsigned long cntrl0Reg; + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); + + /* + * Reset FPGA via FPGA_DATA pin + */ + SET_FPGA(FPGA_PRG | FPGA_CLK); + udelay(1000); /* wait 1ms */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); + udelay(1000); /* wait 1ms */ +#endif + +#if 0 + /* + * Enable power on PS/2 interface + */ + *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; + + /* + * Enable interrupts in exar duart mcr[3] + */ + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; +#endif + return (0); +} + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming PPChameleonEVB"); + } else { + puts(str); + } + + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 /* test-only */ + for (;;) { + NAND_DISABLE_CE(1); + udelay(100); + NAND_ENABLE_CE(1); + udelay(100); + } +#endif +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +extern ulong +nand_probe(ulong physadr); + +void +nand_init(void) +{ + ulong totlen = 0; + +/* + The HI model is equipped with a large block NAND chip not supported yet + by U-Boot + (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) +*/ + +#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) + debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); + totlen += nand_probe (CFG_NAND0_BASE); +#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */ + + debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE); + totlen += nand_probe (CFG_NAND1_BASE); + + printf ("%3lu MB\n", totlen >>20); +} +#endif + +#ifdef CONFIG_CFB_CONSOLE +# ifdef CONFIG_CONSOLE_EXTRA_INFO +# include +extern GraphicDevice smi; + +void video_get_info_str (int line_number, char *info) +{ + uint pvr = get_pvr (); + + /* init video info strings for graphic console */ + switch (line_number) { + case 1: + switch (pvr) { + case PVR_405EP_RB: + sprintf (info, " AMCC PowerPC 405EP Rev. B"); + break; + default: + sprintf (info, " AMCC PowerPC 405EP Rev. "); + break; + } + return; + case 2: + sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it"); + return; + case 3: + sprintf (info, " %s", smi.modeIdent); + return; + } + + /* no more info lines */ + *info = 0; + return; +} +# endif /* CONFIG_CONSOLE_EXTRA_INFO */ +#endif /* CONFIG_CFB_CONSOLE */ diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk new file mode 100644 index 0000000..5856aec --- /dev/null +++ b/board/dave/PPChameleonEVB/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Reserve 256 kB for Monitor +TEXT_BASE = 0xFFFC0000 + +# Reserve 320 kB for Monitor +#TEXT_BASE = 0xFFFB0000 diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c new file mode 100644 index 0000000..692d275 --- /dev/null +++ b/board/dave/PPChameleonEVB/flash.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ +#ifdef __DEBUG_START_FROM_SRAM__ + return CFG_DUMMY_FLASH_SIZE; +#else + unsigned long size; + int i; + uint pbcr; + unsigned long base; + int size_val = 0; + + debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__); + debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info); + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + . = 0xFFFF8000; + .ppcenv : + { + common/environment.o(.ppcenv); + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c new file mode 100644 index 0000000..bf0f2bf --- /dev/null +++ b/board/dave/common/flash.c @@ -0,0 +1,706 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + short n; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { + /* set sector offsets for bottom boot block type */ + for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ + info->start[i] = base; + base += 8 << 10; + } + while (i < info->sector_count) { /* 64k regular sectors */ + info->start[i] = base; + base += 64 << 10; + ++i; + } + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ + base -= 8 << 10; + --i; + info->start[i] = base; + } + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("ST "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); + break; + case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); + break; + case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); + break; + case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n"); + break; + case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_STMW320DT: printf ("M29W320DT (32 M, top sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); +#endif + + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + short n; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; + + debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; + + value = addr2[CFG_FLASH_READ0]; + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[CFG_FLASH_READ1]; /* device ID */ + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: + info->flash_id += FLASH_STMW320DT; + info->sector_count = 67; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: + info->flash_id += FLASH_AMDL322B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U: + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000; break; /* => 8 MB */ + + case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A: + info->flash_id += FLASH_SST800A; + info->sector_count = 16; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A: + info->flash_id += FLASH_SST160A; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { + /* set sector offsets for bottom boot block type */ + for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ + info->start[i] = base; + base += 8 << 10; + } + while (i < info->sector_count) { /* 64k regular sectors */ + info->start[i] = base; + base += 64 << 10; + ++i; + } + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ + base -= 8 << 10; + --i; + info->start[i] = base; + } + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + /* 1 x 16k boot sector */ + base -= 16 << 10; + --i; + info->start[i] = base; + /* 2 x 8k boot sectors */ + for (n=0; n<2; ++n) { + base -= 8 << 10; + --i; + info->start[i] = base; + } + /* 1 x 32k boot sector */ + base -= 32 << 10; + --i; + info->start[i] = base; + + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[CFG_FLASH_READ2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + ulong start, now, last; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */ + for (i=0; i<50; i++) + udelay(1000); /* wait 1 ms */ + } else { + if (sect == s_first) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + } + addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + } + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { +#ifdef CONFIG_B2 + data = data | ((*src++)<<(8*i)); +#else + data = (data << 8) | *src++; +#endif + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { +#ifdef CONFIG_B2 + data = data | ((*(uchar *)cp)<<(8*i)); +#else + data = (data << 8) | (*(uchar *)cp); +#endif + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; +#ifdef CONFIG_B2 + data = (*(ulong*)src); + src += 4; +#else + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } +#endif + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { +#ifdef CONFIG_B2 + data = data | ((*src++)<<(8*i)); +#else + data = (data << 8) | *src++; +#endif + --cnt; + } + for (; i<4; ++i, ++cp) { +#ifdef CONFIG_B2 + data = data | ((*(uchar *)cp)<<(8*i)); +#else + data = (data << 8) | (*(uchar *)cp); +#endif + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile ulong *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) + { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c new file mode 100644 index 0000000..5b5b5e9 --- /dev/null +++ b/board/dave/common/fpga.c @@ -0,0 +1,256 @@ +/* + * (C) Copyright 2001-2003 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#ifdef FPGA_DEBUG +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif /* DEBUG */ + +#define MAX_ONES 226 + +#ifdef CFG_FPGA_PRG +# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/ +# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ +# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ +# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ +# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ +#else +# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ +# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ +#endif + +#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ +#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ +#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ + +#define SET_FPGA(data) out32(GPIO0_OR, data) + +#define FPGA_WRITE_1 { \ + SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ + SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ + +#define FPGA_WRITE_0 { \ + SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ + SET_FPGA(FPGA_PRG); /* set data to 0 */ \ + SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ + +#if 0 +static int fpga_boot (unsigned char *fpgadata, int size) +{ + int i, index, len; + int count; + +#ifdef CFG_FPGA_SPARTAN2 + int j; +#else + unsigned char b; + int bit; +#endif + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + DBG ("FPGA: %s\n", &(fpgadata[index + 1])); + index += len + 3; + } + +#ifdef CFG_FPGA_SPARTAN2 + /* search for preamble 0xFFFFFFFF */ + while (1) { + if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) + && (fpgadata[index + 2] == 0xff) + && (fpgadata[index + 3] == 0xff)) + break; /* preamble found */ + else + index++; + } +#else + /* search for preamble 0xFF2X */ + for (index = 0; index < size - 1; index++) { + if ((fpgadata[index] == 0xff) + && ((fpgadata[index + 1] & 0xf0) == 0x30)) + break; + } + index += 2; +#endif + + DBG ("FPGA: configdata starts at position 0x%x\n", index); + DBG ("FPGA: length of fpga-data %d\n", size - index); + + /* + * Setup port pins for fpga programming + */ + out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ + out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */ + + DBG ("%s, ", + ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); + DBG ("%s\n", + ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); + + /* + * Init fpga by asserting and deasserting PROGRAM* + */ + SET_FPGA (FPGA_CLK | FPGA_DATA); + + /* Wait for FPGA init line low */ + count = 0; + while (in32 (GPIO0_IR) & FPGA_INIT) { + udelay (1000); /* wait 1ms */ + /* Check for timeout - 100us max, so use 3ms */ + if (count++ > 3) { + DBG ("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_LOW; + } + } + + DBG ("%s, ", + ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); + DBG ("%s\n", + ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); + + /* deassert PROGRAM* */ + SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); + + /* Wait for FPGA end of init period . */ + count = 0; + while (!(in32 (GPIO0_IR) & FPGA_INIT)) { + udelay (1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) { + DBG ("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_HIGH; + } + } + + DBG ("%s, ", + ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); + DBG ("%s\n", + ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); + + DBG ("write configuration data into fpga\n"); + /* write configuration-data into fpga... */ + +#ifdef CFG_FPGA_SPARTAN2 + /* + * Load uncompressed image into fpga + */ + for (i = index; i < size; i++) { + for (j = 0; j < 8; j++) { + if ((fpgadata[i] & 0x80) == 0x80) { + FPGA_WRITE_1; + } else { + FPGA_WRITE_0; + } + fpgadata[i] <<= 1; + } + } +#else /* ! CFG_FPGA_SPARTAN2 */ + /* send 0xff 0x20 */ + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_0; + FPGA_WRITE_0; + FPGA_WRITE_1; + FPGA_WRITE_0; + FPGA_WRITE_0; + FPGA_WRITE_0; + FPGA_WRITE_0; + FPGA_WRITE_0; + + /* + ** Bit_DeCompression + ** Code 1 .. maxOnes : n '1's followed by '0' + ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' + ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' + ** 255 : '1' + */ + + for (i = index; i < size; i++) { + b = fpgadata[i]; + if ((b >= 1) && (b <= MAX_ONES)) { + for (bit = 0; bit < b; bit++) { + FPGA_WRITE_1; + } + FPGA_WRITE_0; + } else if (b == (MAX_ONES + 1)) { + for (bit = 1; bit < b; bit++) { + FPGA_WRITE_1; + } + } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { + for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { + FPGA_WRITE_0; + } + FPGA_WRITE_1; + } else if (b == 255) { + FPGA_WRITE_1; + } + } +#endif /* CFG_FPGA_SPARTAN2 */ + + DBG ("%s, ", + ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); + DBG ("%s\n", + ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); + + /* + * Check if fpga's DONE signal - correctly booted ? + */ + + /* Wait for FPGA end of programming period . */ + count = 0; + while (!(in32 (GPIO0_IR) & FPGA_DONE)) { + udelay (1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) { + DBG ("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_DONE; + } + } + + DBG ("FPGA: Booting successful!\n"); + return 0; +} +#endif /* 0 */ diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c new file mode 100644 index 0000000..f8f180c --- /dev/null +++ b/board/dave/common/pci.c @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +u_long pci9054_iobase; + + +#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ +#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ + + +/*-----------------------------------------------------------------------------+ +| Subroutine: pci9054_read_config_dword +| Description: Read a PCI configuration register +| Inputs: +| hose PCI Controller +| dev PCI Bus+Device+Function number +| offset Configuration register number +| value Address of the configuration register value +| Return value: +| 0 Successful ++-----------------------------------------------------------------------------*/ +int pci9054_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32* value) +{ + unsigned long conAdrVal; + unsigned long val; + + /* generate coded value for CON_ADR register */ + conAdrVal = dev | (offset & 0xfc) | 0x80000000; + + /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ + *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; + + /* Note: *pResult comes back as -1 if machine check happened */ + val = in32r(PCI_PRIMARY_CDR); + + *value = (unsigned long) val; + + out32r(PCI_PRIMARY_CAR, 0); + + if ((*(unsigned long *)0x50000304) & 0x60000000) + { + /* clear pci master/target abort bits */ + *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; + } + + return 0; +} + +/*-----------------------------------------------------------------------------+ +| Subroutine: pci9054_write_config_dword +| Description: Write a PCI configuration register. +| Inputs: +| hose PCI Controller +| dev PCI Bus+Device+Function number +| offset Configuration register number +| Value Configuration register value +| Return value: +| 0 Successful +| Updated for pass2 errata #6. Need to disable interrupts and clear the +| PCICFGADR reg after writing the PCICFGDATA reg. ++-----------------------------------------------------------------------------*/ +int pci9054_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + unsigned long conAdrVal; + + conAdrVal = dev | (offset & 0xfc) | 0x80000000; + + *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; + + out32r(PCI_PRIMARY_CDR, value); + + out32r(PCI_PRIMARY_CAR, 0); + + /* clear pci master/target abort bits */ + *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; + + return (0); +} + +/*----------------------------------------------------------------------- + */ + +#ifdef CONFIG_DASA_SIM +static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *_) +{ + unsigned int iobase; + unsigned short status = 0; + unsigned char timer; + + /* + * Configure PLX PCI9054 + */ + pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status); + status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status); + + /* Check the latency timer for values >= 0x60. + */ + pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); + if (timer < 0x60) + { + pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); + } + + /* Set I/O base register. + */ + pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE); + pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); + + pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); + + if (pci9054_iobase == 0xffffffff) + { + printf("Error: Can not set I/O base register.\n"); + return; + } +} +#endif + +static struct pci_config_table pci9054_config_table[] = { +#ifndef CONFIG_PCI_PNP + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), + pci_cfgfunc_config_device, { CFG_ETH_IOBASE, + CFG_ETH_IOBASE, + PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, +#ifdef CONFIG_DASA_SIM + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN), + pci_dasa_sim_config_pci9054 }, +#endif +#endif + { } +}; + +static struct pci_controller pci9054_hose = { + config_table: pci9054_config_table, +}; + +void pci_init(void) +{ + struct pci_controller *hose = &pci9054_hose; + + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region(hose->regions + 0, + 0x00000000, 0x00000000, 0x01000000, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI Memory space */ + pci_set_region(hose->regions + 1, + 0x00000000, 0xc0000000, 0x10000000, + PCI_REGION_MEM); + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + pci9054_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + pci9054_write_config_dword); + + hose->region_count = 2; + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); +} diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile new file mode 100644 index 0000000..d9b0e2d --- /dev/null +++ b/board/dbau1x00/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = lowlevel_init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/dbau1x00/README b/board/dbau1x00/README new file mode 100644 index 0000000..b37ff36 --- /dev/null +++ b/board/dbau1x00/README @@ -0,0 +1,63 @@ +By Thomas.Lange@corelatus.se 2004-Oct-05 +---------------------------------------- +DbAu1xx0 are development boards from AMD containing +an Alchemy AU1xx0 series cpu with mips32 core. +Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 + +Limitations & comments +---------------------- +Support was originally big endian only. +I have not tested, but several u-boot users report working +configurations in little endian mode. + +I named the board dbau1x00, to allow +support for all three development boards +( dbau1000, dbau1100 and dbau1500 ). +Now there is a new board called dbau1550 also, which +should be supported RSN. + +I only have a dbau1000, so my testing is limited +to this board. + +The board has two different flash banks, that can +be selected via dip switch. This makes it possible +to test new bootloaders without thrashing the YAMON +boot loader delivered with board. + +NOTE! When you switch between the two boot flashes, the +base addresses will be swapped. +Have this in mind when you compile u-boot. TEXT_BASE has +to match the address where u-boot is located when you +actually launch. + +Ethernet only supported for mac0. + +PCMCIA only supported for slot 0, only 3.3V. + +PCMCIA IDE tested with Sandisk Compact Flash and +IBM microdrive. + +################################### +######## NOTE!!!!!! ######### +################################### +If you partition a disk on another system (e.g. laptop), +all bytes will be swapped on 16bit level when using +PCMCIA and running cpu in big endian mode!!!! + +This is probably due to an error in Au1000 chip. + +Solution: + +a) Boot via network and partition disk directly from +dbau1x00. The endian will then be correct. + +b) Partition disk on "laptop" and fill it with all files +you need. Then write a simple program that endian swaps +whole disk, + +Example: +Original "laptop" byte order: +B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... + +Dbau1000 byte order will then be: +B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... diff --git a/board/dbau1x00/config.mk b/board/dbau1x00/config.mk new file mode 100644 index 0000000..39eb60a --- /dev/null +++ b/board/dbau1x00/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AMD development board AMD Alchemy DbAu1x00, MIPS32 core +# + +# ROM version +TEXT_BASE = 0xbfc00000 + +# RAM version +#TEXT_BASE = 0x80100000 diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c new file mode 100644 index 0000000..d29e8d5 --- /dev/null +++ b/board/dbau1x00/dbau1x00.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2003 + * Thomas.Lange@corelatus.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +long int initdram(int board_type) +{ + /* Sdram is setup by assembler code */ + /* If memory could be changed, we should return the true value here */ + return MEM_SIZE*1024*1024; +} + +#define BCSR_PCMCIA_PC0DRVEN 0x0010 +#define BCSR_PCMCIA_PC0RST 0x0080 + +/* In cpu/mips/cpu.c */ +void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); + +int checkboard (void) +{ +#ifdef CONFIG_IDE_PCMCIA + u16 status; + volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10); +#endif /* CONFIG_IDE_PCMCIA */ + volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC); + volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; + u32 proc_id; + + *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ + + proc_id = read_32bit_cp0_register(CP0_PRID); + + switch (proc_id >> 24) { + case 0: + puts ("Board: Merlot (DbAu1000)\n"); + printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", + (proc_id >> 8) & 0xFF, proc_id & 0xFF); + break; + case 1: + puts ("Board: DbAu1500\n"); + printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", + (proc_id >> 8) & 0xFF, proc_id & 0xFF); + break; + case 2: + puts ("Board: DbAu1100\n"); + printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", + (proc_id >> 8) & 0xFF, proc_id & 0xFF); + break; + case 3: + puts ("Board: DbAu1550\n"); + printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n", + (proc_id >> 8) & 0xFF, proc_id & 0xFF); + break; + default: + printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); + } +#ifdef CONFIG_IDE_PCMCIA + /* Enable 3.3 V on slot 0 ( VCC ) + No 5V */ + status = 4; + *pcmcia_bcsr = status; + + status |= BCSR_PCMCIA_PC0DRVEN; + *pcmcia_bcsr = status; + au_sync(); + + udelay(300*1000); + + status |= BCSR_PCMCIA_PC0RST; + *pcmcia_bcsr = status; + au_sync(); + + udelay(100*1000); + + /* PCMCIA is on a 36 bit physical address. + We need to map it into a 32 bit addresses */ + +#if 0 + /* We dont need theese unless we run whole pcmcia package */ + write_one_tlb(20, /* index */ + 0x01ffe000, /* Pagemask, 16 MB pages */ + CFG_PCMCIA_IO_BASE, /* Hi */ + 0x3C000017, /* Lo0 */ + 0x3C200017); /* Lo1 */ + + write_one_tlb(21, /* index */ + 0x01ffe000, /* Pagemask, 16 MB pages */ + CFG_PCMCIA_ATTR_BASE, /* Hi */ + 0x3D000017, /* Lo0 */ + 0x3D200017); /* Lo1 */ +#endif /* 0 */ + write_one_tlb(22, /* index */ + 0x01ffe000, /* Pagemask, 16 MB pages */ + CFG_PCMCIA_MEM_ADDR, /* Hi */ + 0x3E000017, /* Lo0 */ + 0x3E200017); /* Lo1 */ +#endif /* CONFIG_IDE_PCMCIA */ + + /* Release reset of ethernet PHY chips */ + /* Always do this, because linux does not know about it */ + *phy = 3; + + return 0; +} diff --git a/board/dbau1x00/flash.c b/board/dbau1x00/flash.c new file mode 100644 index 0000000..3cf29e8 --- /dev/null +++ b/board/dbau1x00/flash.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + printf ("Skipping flash_init\n"); + return (0); +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + printf ("write_buff not implemented\n"); + return (-1); +} diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S new file mode 100644 index 0000000..7afd584 --- /dev/null +++ b/board/dbau1x00/lowlevel_init.S @@ -0,0 +1,587 @@ +/* Memory sub-system initialization code */ + +#include +#include +#include +#include +#include + +#define AU1500_SYS_ADDR 0xB1900000 +#define sys_endian 0x0038 +#define CP0_Config0 $16 +#define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */ +#define MEM_1MS ((CFG_MHZ) * 1000) + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + /* + * Step 1) Establish CPU endian mode. + * Db1500-specific: + * Switch S1.1 Off(bit7 reads 1) is Little Endian + * Switch S1.1 On (bit7 reads 0) is Big Endian + */ +#ifdef CONFIG_DBAU1550 + li t0, MEM_STCFG2 + li t1, 0x00000040 + sw t1, 0(t0) + + li t0, MEM_STTIME2 + li t1, 0x22080a20 + sw t1, 0(t0) + + li t0, MEM_STADDR2 + li t1, 0x10c03f00 + sw t1, 0(t0) +#else + li t0, MEM_STCFG1 + li t1, 0x00000080 + sw t1, 0(t0) + + li t0, MEM_STTIME1 + li t1, 0x22080a20 + sw t1, 0(t0) + + li t0, MEM_STADDR1 + li t1, 0x10c03f00 + sw t1, 0(t0) +#endif + + li t0, DB1XX0_BCSR_ADDR + lw t1,8(t0) + andi t1,t1,0x80 + beq zero,t1,big_endian + nop +little_endian: + + /* Change Au1 core to little endian */ + li t0, AU1500_SYS_ADDR + li t1, 1 + sw t1, sys_endian(t0) + mfc0 t2, CP0_CONFIG + mtc0 t2, CP0_CONFIG + nop + nop + + /* Big Endian is default so nothing to do but fall through */ + +big_endian: + + /* + * Step 2) Establish Status Register + * (set BEV, clear ERL, clear EXL, clear IE) + */ + li t1, 0x00400000 + mtc0 t1, CP0_STATUS + + /* + * Step 3) Establish CP0 Config0 + * (set OD, set K0=3) + */ + li t1, 0x00080003 + mtc0 t1, CP0_CONFIG + + /* + * Step 4) Disable Watchpoint facilities + */ + li t1, 0x00000000 + mtc0 t1, CP0_WATCHLO + mtc0 t1, CP0_IWATCHLO + /* + * Step 5) Disable the performance counters + */ + mtc0 zero, CP0_PERFORMANCE + nop + + /* + * Step 6) Establish EJTAG Debug register + */ + mtc0 zero, CP0_DEBUG + nop + + /* + * Step 7) Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + +#ifdef CONFIG_DBAU1550 + /* No workaround if running from ram */ + lui t0, 0xffc0 + lui t3, 0xbfc0 + and t1, ra, t0 + bne t1, t3, noCacheJump + nop + + /*** From AMD YAMON ***/ + /* + * Step 8) Initialize the caches + */ + li t0, (16*1024) + li t1, 32 + li t2, 0x80000000 + addu t3, t0, t2 +cacheloop: + cache 0, 0(t2) + cache 1, 0(t2) + addu t2, t1 + bne t2, t3, cacheloop + nop + + /* Save return address */ + move t3, ra + + /* Run from cacheable space now */ + bal cachehere + nop +cachehere: + li t1, ~0x20000000 /* convert to KSEG0 */ + and t0, ra, t1 + addi t0, 5*4 /* 5 insns beyond cachehere */ + jr t0 + nop + + /* Restore return address */ + move ra, t3 + + /* + * Step 9) Initialize the TLB + */ + li t0, 0 # index value + li t1, 0x00000000 # entryhi value + li t2, 32 # 32 entries + +tlbloop: + /* Probe TLB for matching EntryHi */ + mtc0 t1, CP0_ENTRYHI + tlbp + nop + + /* Examine Index[P], 1=no matching entry */ + mfc0 t3, CP0_INDEX + li t4, 0x80000000 + and t3, t4, t3 + addiu t1, t1, 1 # increment t1 (asid) + beq zero, t3, tlbloop + nop + + /* Initialize the TLB entry */ + mtc0 t0, CP0_INDEX + mtc0 zero, CP0_ENTRYLO0 + mtc0 zero, CP0_ENTRYLO1 + mtc0 zero, CP0_PAGEMASK + tlbwi + + /* Do it again */ + addiu t0, t0, 1 + bne t0, t2, tlbloop + nop + + /* First setup pll:s to make serial work ok */ + /* We have a 12 MHz crystal */ + li t0, SYS_CPUPLL + li t1, CPU_SCALE /* CPU clock */ + sw t1, 0(t0) + sync + nop + nop + + /* wait 1mS for clocks to settle */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + /* Setup AUX PLL */ + li t0, SYS_AUXPLL + li t1, 0x20 /* 96 MHz */ + sw t1, 0(t0) /* aux pll */ + sync + + /* Static memory controller */ + /* RCE0 - can not change while fetching, do so from icache */ + move t2, ra /* Store return address */ + bal getAddr + nop + +getAddr: + move t1, ra + move ra, t2 /* Move return addess back */ + + cache 0x14,0(t1) + cache 0x14,32(t1) + /*** /From YAMON ***/ + +noCacheJump: +#endif /* CONFIG_DBAU1550 */ + +#ifdef CONFIG_DBAU1550 + li t0, MEM_STTIME0 + li t1, 0x040181D7 + sw t1, 0(t0) + + /* RCE0 AMD MirrorBit Flash (?) */ + li t0, MEM_STCFG0 + li t1, 0x00000003 + sw t1, 0(t0) + + li t0, MEM_STADDR0 + li t1, 0x11803E00 + sw t1, 0(t0) +#else /* CONFIG_DBAU1550 */ + li t0, MEM_STTIME0 + li t1, 0x00014C0F + sw t1, 0(t0) + + /* RCE0 AMD 29LV640M MirrorBit Flash */ + li t0, MEM_STCFG0 + li t1, 0x00000013 + sw t1, 0(t0) + + li t0, MEM_STADDR0 + li t1, 0x11E03F80 + sw t1, 0(t0) +#endif /* CONFIG_DBAU1550 */ + + /* RCE1 CPLD Board Logic */ + li t0, MEM_STCFG1 + li t1, 0x00000080 + sw t1, 0(t0) + + li t0, MEM_STTIME1 + li t1, 0x22080a20 + sw t1, 0(t0) + + li t0, MEM_STADDR1 + li t1, 0x10c03f00 + sw t1, 0(t0) + +#ifdef CONFIG_DBAU1550 + /* RCE2 CPLD Board Logic */ + li t0, MEM_STCFG2 + li t1, 0x00000040 + sw t1, 0(t0) + + li t0, MEM_STTIME2 + li t1, 0x22080a20 + sw t1, 0(t0) + + li t0, MEM_STADDR2 + li t1, 0x10c03f00 + sw t1, 0(t0) +#else + li t0, MEM_STCFG2 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_STTIME2 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_STADDR2 + li t1, 0x00000000 + sw t1, 0(t0) +#endif + + /* RCE3 PCMCIA 250ns */ + li t0, MEM_STCFG3 + li t1, 0x00000002 + sw t1, 0(t0) + + li t0, MEM_STTIME3 + li t1, 0x280E3E07 + sw t1, 0(t0) + + li t0, MEM_STADDR3 + li t1, 0x10000000 + sw t1, 0(t0) + + sync + + /* Set peripherals to a known state */ + li t0, IC0_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC0_CFG0CLR + sw t1, 0(t0) + + li t0, IC0_CFG1CLR + sw t1, 0(t0) + + li t0, IC0_CFG2CLR + sw t1, 0(t0) + + li t0, IC0_SRCSET + sw t1, 0(t0) + + li t0, IC0_ASSIGNSET + sw t1, 0(t0) + + li t0, IC0_WAKECLR + sw t1, 0(t0) + + li t0, IC0_RISINGCLR + sw t1, 0(t0) + + li t0, IC0_FALLINGCLR + sw t1, 0(t0) + + li t0, IC0_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, IC1_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC1_CFG0CLR + sw t1, 0(t0) + + li t0, IC1_CFG1CLR + sw t1, 0(t0) + + li t0, IC1_CFG2CLR + sw t1, 0(t0) + + li t0, IC1_SRCSET + sw t1, 0(t0) + + li t0, IC1_ASSIGNSET + sw t1, 0(t0) + + li t0, IC1_WAKECLR + sw t1, 0(t0) + + li t0, IC1_RISINGCLR + sw t1, 0(t0) + + li t0, IC1_FALLINGCLR + sw t1, 0(t0) + + li t0, IC1_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, SYS_FREQCTRL0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_FREQCTRL1 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_CLKSRC + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_PININPUTEN + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, 0xB1100100 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, 0xB1400100 + li t1, 0x00000000 + sw t1, 0(t0) + + + li t0, SYS_WAKEMSK + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_WAKESRC + li t1, 0x00000000 + sw t1, 0(t0) + + /* wait 1mS before setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + +#ifdef CONFIG_DBAU1550 +/* SDCS 0,1,2 DDR SDRAM */ + li t0, MEM_SDMODE0 + li t1, 0x04276221 + sw t1, 0(t0) + + li t0, MEM_SDMODE1 + li t1, 0x04276221 + sw t1, 0(t0) + + li t0, MEM_SDMODE2 + li t1, 0x04276221 + sw t1, 0(t0) + + li t0, MEM_SDADDR0 + li t1, 0xe21003f0 + sw t1, 0(t0) + + li t0, MEM_SDADDR1 + li t1, 0xe21043f0 + sw t1, 0(t0) + + li t0, MEM_SDADDR2 + li t1, 0xe21083f0 + sw t1, 0(t0) + + sync + + li t0, MEM_SDCONFIGA + li t1, 0x9030060a /* Program refresh - disabled */ + sw t1, 0(t0) + sync + + li t0, MEM_SDCONFIGB + li t1, 0x00028000 + sw t1, 0(t0) + sync + + li t0, MEM_SDPRECMD /* Precharge all */ + li t1, 0 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD0 + li t1, 0x40000000 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD1 + li t1, 0x40000000 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD2 + li t1, 0x40000000 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD0 + li t1, 0x00000063 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD1 + li t1, 0x00000063 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD2 + li t1, 0x00000063 + sw t1, 0(t0) + sync + + li t0, MEM_SDPRECMD /* Precharge all */ + sw zero, 0(t0) + sync + + /* Issue 2 autoref */ + li t0, MEM_SDAUTOREF + sw zero, 0(t0) + sync + + li t0, MEM_SDAUTOREF + sw zero, 0(t0) + sync + + /* Enable refresh */ + li t0, MEM_SDCONFIGA + li t1, 0x9830060a /* Program refresh - enabled */ + sw t1, 0(t0) + sync + +#else /* CONFIG_DBAU1550 */ +/* SDCS 0,1 SDRAM */ + li t0, MEM_SDMODE0 + li t1, 0x005522AA + sw t1, 0(t0) + + li t0, MEM_SDMODE1 + li t1, 0x005522AA + sw t1, 0(t0) + + li t0, MEM_SDMODE2 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_SDADDR0 + li t1, 0x001003F8 + sw t1, 0(t0) + + + li t0, MEM_SDADDR1 + li t1, 0x001023F8 + sw t1, 0(t0) + + li t0, MEM_SDADDR2 + li t1, 0x00000000 + sw t1, 0(t0) + + sync + + li t0, MEM_SDREFCFG + li t1, 0x64000C24 /* Disable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDPRECMD + sw zero, 0(t0) + sync + + li t0, MEM_SDAUTOREF + sw zero, 0(t0) + sync + sw zero, 0(t0) + sync + + li t0, MEM_SDREFCFG + li t1, 0x66000C24 /* Enable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD0 + li t1, 0x00000033 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD1 + li t1, 0x00000033 + sw t1, 0(t0) + sync + +#endif /* CONFIG_DBAU1550 */ + /* wait 1mS after setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + + li t0, SYS_PINFUNC + li t1, 0x00008080 + sw t1, 0(t0) + + li t0, SYS_TRIOUTCLR + li t1, 0x00001FFF + sw t1, 0(t0) + + li t0, SYS_OUTPUTCLR + li t1, 0x00008000 + sw t1, 0(t0) + sync + + j ra + nop diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds new file mode 100644 index 0000000..10c9917 --- /dev/null +++ b/board/dbau1x00/u-boot.lds @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/board/dnp1110/Makefile b/board/dnp1110/Makefile new file mode 100644 index 0000000..eaa38bc --- /dev/null +++ b/board/dnp1110/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := dnp1110.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/dnp1110/config.mk b/board/dnp1110/config.mk new file mode 100644 index 0000000..4f6af46 --- /dev/null +++ b/board/dnp1110/config.mk @@ -0,0 +1,17 @@ +# +# DNP/1110 board with SA1100 cpu +# +# http://www.dilnetpc.com +# + +# +# DILNETPC has 1 banks of 32 MB DRAM +# +# c000'0000 +# +# Linux-Kernel is expected to be at c000'8000, entry c000'8000 +# +# we load ourself to c1f8'0000, the upper 1 MB of the first (only) bank +# + +TEXT_BASE = 0xc1f80000 diff --git a/board/dnp1110/dnp1110.c b/board/dnp1110/dnp1110.c new file mode 100644 index 0000000..24c3e00 --- /dev/null +++ b/board/dnp1110/dnp1110.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of DNP1110-Board */ + gd->bd->bi_arch_number = MACH_TYPE_DNP1110; + + /* flash vpp on */ + PPDR |= 0x80; /* assumes LCD controller is off */ + PPSR |= 0x80; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/dnp1110/flash.c b/board/dnp1110/flash.c new file mode 100644 index 0000000..60874ba --- /dev/null +++ b/board/dnp1110/flash.c @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel(void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + switch (i) + { + case 0: + flash_get_size((FPW *)PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets(PHYS_FLASH_1, &flash_info[i]); + break; + default: + panic("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); break; + default: printf ("Unknown Chip Type\n"); break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW)0x00AA00AA; + addr[0x2AAA] = (FPW)0x00550055; + addr[0x5555] = (FPW)0x00900090; + + mb(); + value = addr[0]; + + switch (value) { + + case (FPW)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW)0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb(); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW)INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW)0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *)(info->start[sect]); + FPW status; + + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + + while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW)0x00B000B0; /* suspend erase */ + *addr = (FPW)0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = (FPW)0x00500050; /* clear status register cmd. */ + *addr = (FPW)0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= port_width) { + data = 0; + for (i=0; i 0x800) + { + spin_wheel(); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i CFG_FLASH_WRITE_TOUT) { + *addr = (FPW)0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW)0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline +spin_wheel(void) +{ + static int p=0; + static char w[] = "\\/-"; + + printf("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/dnp1110/lowlevel_init.S b/board/dnp1110/lowlevel_init.S new file mode 100644 index 0000000..7730be3 --- /dev/null +++ b/board/dnp1110/lowlevel_init.S @@ -0,0 +1,135 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "config.h" +#include "version.h" + + +/* some parameters for the board */ + +MEM_BASE: .long 0xa0000000 +MEM_START: .long 0xc0000000 + +#define MDCNFG 0x00 +#define MDCAS00 0x04 /* CAS waveform rotate reg 0 */ +#define MDCAS01 0x08 /* CAS waveform rotate reg 1 bank */ +#define MDCAS02 0x0C /* CAS waveform rotate reg 2 bank */ +#define MDREFR 0x1C /* DRAM refresh control reg */ +#define MDCAS20 0x20 /* CAS waveform rotate reg 0 bank */ +#define MDCAS21 0x24 /* CAS waveform rotate reg 1 bank */ +#define MDCAS22 0x28 /* CAS waveform rotate reg 2 bank */ +#define MECR 0x18 /* Expansion memory (PCMCIA) bus configuration register */ +#define MSC0 0x10 /* static memory control reg 0 */ +#define MSC1 0x14 /* static memory control reg 1 */ +#define MSC2 0x2C /* static memory control reg 2 */ +#define SMCNFG 0x30 /* SMROM configuration reg */ + +mdcas00: .long 0x5555557F +mdcas01: .long 0x55555555 +mdcas02: .long 0x55555555 +mdcas20: .long 0x5555557F +mdcas21: .long 0x55555555 +mdcas22: .long 0x55555555 +mdcnfg: .long 0x0000B25C +mdrefr: .long 0x007000C1 +mecr: .long 0x10841084 +msc0: .long 0x00004774 +msc1: .long 0x00000000 +msc2: .long 0x00000000 +smcnfg: .long 0x00000000 + +/* setting up the memory */ + +.globl lowlevel_init +lowlevel_init: + + ldr r0, MEM_BASE + + /* Set up the DRAM */ + + /* MDCAS00 */ + ldr r1, mdcas00 + str r1, [r0, #MDCAS00] + + /* MDCAS01 */ + ldr r1, mdcas01 + str r1, [r0, #MDCAS01] + + /* MDCAS02 */ + ldr r1, mdcas02 + str r1, [r0, #MDCAS02] + + /* MDCAS20 */ + ldr r1, mdcas20 + str r1, [r0, #MDCAS20] + + /* MDCAS21 */ + ldr r1, mdcas21 + str r1, [r0, #MDCAS21] + + /* MDCAS22 */ + ldr r1, mdcas22 + str r1, [r0, #MDCAS22] + + /* MDREFR */ + ldr r1, mdrefr + str r1, [r0, #MDREFR] + + /* Set up PCMCIA space */ + ldr r1, mecr + str r1, [r0, #MECR] + + /* Setup the flash memory and other */ + ldr r1, msc0 + str r1, [r0, #MSC0] + + ldr r1, msc1 + str r1, [r0, #MSC1] + + ldr r1, msc2 + str r1, [r0, #MSC2] + + ldr r1, smcnfg + str r1, [r0, #SMCNFG] + + /* MDCNFG */ + ldr r1, mdcnfg + bic r1, r1, #0x00000001 + str r1, [r0, #MDCNFG] + + /* Load something to activate bank */ + ldr r2, MEM_START +.rept 8 + ldr r1, [r2] +.endr + + /* MDCNFG */ + ldr r1, mdcnfg + orr r1, r1, #0x00000001 + str r1, [r0, #MDCNFG] + + /* everything is fine now */ + mov pc, lr diff --git a/board/dnp1110/u-boot.lds b/board/dnp1110/u-boot.lds new file mode 100644 index 0000000..258bece --- /dev/null +++ b/board/dnp1110/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/eXalion/Makefile b/board/eXalion/Makefile new file mode 100644 index 0000000..cfbf465 --- /dev/null +++ b/board/eXalion/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +SOBJS = + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/eXalion/config.mk b/board/eXalion/config.mk new file mode 100644 index 0000000..b3f65eb --- /dev/null +++ b/board/eXalion/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Sandpoint boards +# + +#TEXT_BASE = 0x00090000 +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c new file mode 100644 index 0000000..2e3f519 --- /dev/null +++ b/board/eXalion/eXalion.c @@ -0,0 +1,292 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include "piix_pci.h" +#include "eXalion.h" + +int checkboard (void) +{ + ulong busfreq = get_bus_freq (0); + char buf[32]; + + printf ("Board: eXalion MPC824x - CHRP (MAP B)\n"); + printf ("Built: %s at %s\n", __DATE__, __TIME__); + printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); + + return 0; +} + +int checkflash (void) +{ + printf ("checkflash\n"); + flash_init (); + return (0); +} + +long int initdram (int board_type) +{ + int i, cnt; + volatile uchar *base = CFG_SDRAM_BASE; + volatile ulong *addr; + ulong save[32]; + ulong val, ret = 0; + + for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0; + cnt >>= 1) { + addr = (volatile ulong *) base + cnt; + save[i++] = *addr; + *addr = ~cnt; + } + + addr = (volatile ulong *) base; + save[i] = *addr; + *addr = 0; + + if (*addr != 0) { + *addr = save[i]; + goto Done; + } + + for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) { + addr = (volatile ulong *) base + cnt; + val = *addr; + *addr = save[--i]; + if (val != ~cnt) { + ulong new_bank0_end = cnt * sizeof (long) - 1; + ulong mear1 = mpc824x_mpc107_getreg (MEAR1); + ulong emear1 = mpc824x_mpc107_getreg (EMEAR1); + + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> + MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> + MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg (MEAR1, mear1); + mpc824x_mpc107_setreg (EMEAR1, emear1); + + ret = cnt * sizeof (long); + goto Done; + } + } + + ret = CFG_MAX_RAM_SIZE; + Done: + return ret; +} + +int misc_init_r (void) +{ + pci_dev_t bdf; + u32 val32; + u8 val8; + + puts ("ISA: "); + bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0); + if (bdf == -1) { + puts ("Unable to find PIIX4 ISA bridge !\n"); + hang (); + } + + /* set device for normal ISA instead EIO */ + pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32); + val32 |= 0x00000001; + pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32); + printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf), + PCI_DEV (bdf), PCI_FUNC (bdf)); + + puts ("ISA: "); + bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0); + if (bdf == -1) { + puts ("Unable to find PIIX4 IDE controller !\n"); + hang (); + } + + /* Init BMIBA register */ + /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */ + /* val32 |= 0x1000; */ + /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */ + + /* Enable BUS master and IO access */ + val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_dword (bdf, PCI_COMMAND, val32); + + /* Set latency */ + pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8); + val8 = 0x40; + pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8); + + /* Enable Primary ATA/IDE */ + pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32); + /* val32 = 0xa307a307; */ + val32 = 0x00008000; + pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32); + + + printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf), + PCI_DEV (bdf), PCI_FUNC (bdf)); + + /* Try to get FAT working... */ + /* fat_register_read(ide_read); */ + + + return (0); +} + +/* + * Show/Init PCI devices on the specified bus number. + */ + +void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char line; + + switch (PCI_DEV (dev)) { + case 16: + line = PCI_INT_A; + break; + case 17: + line = PCI_INT_B; + break; + case 18: + line = PCI_INT_C; + break; + case 19: + line = PCI_INT_D; + break; +#if defined (CONFIG_MPC8245) + case 20: + line = PCI_INT_A; + break; + case 21: + line = PCI_INT_B; + break; + case 22: + line = PCI_INT_NA; + break; +#endif + default: + line = PCI_INT_A; + break; + } + pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line); +} + + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP +#if defined (CONFIG_MPC8240) +static struct pci_config_table pci_eXalion_config_table[] = { + { + /* Intel 82559ER ethernet controller */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + { + /* Intel 82371AB PIIX4 PCI to ISA bridge */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, + pci_cfgfunc_config_device, {0, + 0, + PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, + { + /* Intel 82371AB PIIX4 IDE controller */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01, + pci_cfgfunc_config_device, {0, + 0, + PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, + {} +}; +#elif defined (CONFIG_MPC8245) +static struct pci_config_table pci_eXalion_config_table[] = { + { + /* Intel 82559ER ethernet controller */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + { + /* Intel 82559ER ethernet controller */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, + pci_cfgfunc_config_device, {PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + { + /* Broadcom BCM5690 Gigabit switch */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, + pci_cfgfunc_config_device, {PCI_ENET2_IOADDR, + PCI_ENET2_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + { + /* Broadcom BCM5690 Gigabit switch */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00, + pci_cfgfunc_config_device, {PCI_ENET3_IOADDR, + PCI_ENET3_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + { + /* Intel 82371AB PIIX4 PCI to ISA bridge */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00, + pci_cfgfunc_config_device, {0, + 0, + PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, + { + /* Intel 82371AB PIIX4 IDE controller */ + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01, + pci_cfgfunc_config_device, {0, + 0, + PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, + {} +}; +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif + +#endif /* #ifndef CONFIG_PCI_PNP */ + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_eXalion_config_table, + fixup_irq:pci_eXalion_fixup_irq, +#endif +}; + +void pci_init_board (void) +{ + pci_mpc824x_init (&hose); +} diff --git a/board/eXalion/eXalion.h b/board/eXalion/eXalion.h new file mode 100644 index 0000000..8dccabb --- /dev/null +++ b/board/eXalion/eXalion.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * James Dougherty (jfd@broadcom.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __EXALION_H +#define __EXALION_H + +/* IRQ settings */ +#define PCI_INT_NA (0xff) /* PCI Intr. not used */ +#define PCI_INT_A (0x09) /* PCI Intr. A Interrupt Request Line Nr. */ +#define PCI_INT_B (0x0a) /* PCI Intr. B Interrupt Request Line Nr. */ +#define PCI_INT_C (0x0b) /* PCI Intr. C Interrupt Request Line Nr. */ +#define PCI_INT_D (0x0c) /* PCI Intr. D Interrupt Request Line Nr. */ +#if defined (CPU_MPC8245) +#define LN_1_INT PCI_INT_B /* ethernet interrupt level */ +#define LN_2_INT PCI_INT_C /* ethernet interrupt level */ +#define BCM_1_INT PCI_INT_A /* BCM5690 interrupt level */ +#define BCM_2_INT PCI_INT_B /* BCM5690 interrupt level */ +#elif defined (CPU_MPC8240) +#define BCM_INT PCI_INT_B /* BCM5600 interrupt level */ +#define LN_INT PCI_INT_C /* ethernet interrupt level */ +#endif + +#ifndef __ASSEMBLY__ +#endif /* !__ASSEMBLY__ */ + +#endif /* __EXALION_H */ diff --git a/board/eXalion/piix_pci.h b/board/eXalion/piix_pci.h new file mode 100644 index 0000000..b3c9c16 --- /dev/null +++ b/board/eXalion/piix_pci.h @@ -0,0 +1,172 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _PIIX4_PCI_H +#define _PIIX4_PCI_H + +#include +#include +#include +#include +#include + +#define PIIX4_VENDOR_ID 0x8086 +#define PIIX4_ISA_DEV_ID 0x7110 +#define PIIX4_IDE_DEV_ID 0x7111 + +/* Function 0 ISA Bridge */ +#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ +#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ +#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ +#define PCI_CFG_PIIX4_SERIRQ 0x64 +#define PCI_CFG_PIIX4_TOM 0x69 +#define PCI_CFG_PIIX4_MSTAT 0x6A +#define PCI_CFG_PIIX4_MBDMA 0x76 +#define PCI_CFG_PIIX4_APICBS 0x80 +#define PCI_CFG_PIIX4_DLC 0x82 +#define PCI_CFG_PIIX4_PDMACFG 0x90 +#define PCI_CFG_PIIX4_DDMABS 0x92 +#define PCI_CFG_PIIX4_GENCFG 0xB0 +#define PCI_CFG_PIIX4_RTCCFG 0xCB + +/* IO Addresses */ +#define PIIX4_ISA_DMA1_CH0BA 0x00 +#define PIIX4_ISA_DMA1_CH0CA 0x01 +#define PIIX4_ISA_DMA1_CH1BA 0x02 +#define PIIX4_ISA_DMA1_CH1CA 0x03 +#define PIIX4_ISA_DMA1_CH2BA 0x04 +#define PIIX4_ISA_DMA1_CH2CA 0x05 +#define PIIX4_ISA_DMA1_CH3BA 0x06 +#define PIIX4_ISA_DMA1_CH3CA 0x07 +#define PIIX4_ISA_DMA1_CMDST 0x08 +#define PIIX4_ISA_DMA1_REQ 0x09 +#define PIIX4_ISA_DMA1_WSBM 0x0A +#define PIIX4_ISA_DMA1_CH_MOD 0x0B +#define PIIX4_ISA_DMA1_CLR_PT 0x0C +#define PIIX4_ISA_DMA1_M_CLR 0x0D +#define PIIX4_ISA_DMA1_CLR_M 0x0E +#define PIIX4_ISA_DMA1_RWAMB 0x0F + +#define PIIX4_ISA_DMA2_CH0BA 0xC0 +#define PIIX4_ISA_DMA2_CH0CA 0xC1 +#define PIIX4_ISA_DMA2_CH1BA 0xC2 +#define PIIX4_ISA_DMA2_CH1CA 0xC3 +#define PIIX4_ISA_DMA2_CH2BA 0xC4 +#define PIIX4_ISA_DMA2_CH2CA 0xC5 +#define PIIX4_ISA_DMA2_CH3BA 0xC6 +#define PIIX4_ISA_DMA2_CH3CA 0xC7 +#define PIIX4_ISA_DMA2_CMDST 0xD0 +#define PIIX4_ISA_DMA2_REQ 0xD2 +#define PIIX4_ISA_DMA2_WSBM 0xD4 +#define PIIX4_ISA_DMA2_CH_MOD 0xD6 +#define PIIX4_ISA_DMA2_CLR_PT 0xD8 +#define PIIX4_ISA_DMA2_M_CLR 0xDA +#define PIIX4_ISA_DMA2_CLR_M 0xDC +#define PIIX4_ISA_DMA2_RWAMB 0xDE + +#define PIIX4_ISA_INT1_ICW1 0x20 +#define PIIX4_ISA_INT1_OCW2 0x20 +#define PIIX4_ISA_INT1_OCW3 0x20 +#define PIIX4_ISA_INT1_ICW2 0x21 +#define PIIX4_ISA_INT1_ICW3 0x21 +#define PIIX4_ISA_INT1_ICW4 0x21 +#define PIIX4_ISA_INT1_OCW1 0x21 + +#define PIIX4_ISA_INT1_ELCR 0x4D0 + +#define PIIX4_ISA_INT2_ICW1 0xA0 +#define PIIX4_ISA_INT2_OCW2 0xA0 +#define PIIX4_ISA_INT2_OCW3 0xA0 +#define PIIX4_ISA_INT2_ICW2 0xA1 +#define PIIX4_ISA_INT2_ICW3 0xA1 +#define PIIX4_ISA_INT2_ICW4 0xA1 +#define PIIX4_ISA_INT2_OCW1 0xA1 +#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ + +#define PIIX4_ISA_INT2_ELCR 0x4D1 + +#define PIIX4_ISA_TMR0_CNT_ST 0x40 +#define PIIX4_ISA_TMR1_CNT_ST 0x41 +#define PIIX4_ISA_TMR2_CNT_ST 0x42 +#define PIIX4_ISA_TMR_TCW 0x43 + +#define PIIX4_ISA_RST_XBUS 0x60 + +#define PIIX4_ISA_NMI_CNT_ST 0x61 +#define PIIX4_ISA_NMI_ENABLE 0x70 + +#define PIIX4_ISA_RTC_INDEX 0x70 +#define PIIX4_ISA_RTC_DATA 0x71 +#define PIIX4_ISA_RTCEXT_IND 0x70 +#define PIIX4_ISA_RTCEXT_DATA 0x71 + +#define PIIX4_ISA_DMA1_CH2LPG 0x81 +#define PIIX4_ISA_DMA1_CH3LPG 0x82 +#define PIIX4_ISA_DMA1_CH1LPG 0x83 +#define PIIX4_ISA_DMA1_CH0LPG 0x87 +#define PIIX4_ISA_DMA2_CH2LPG 0x89 +#define PIIX4_ISA_DMA2_CH3LPG 0x8A +#define PIIX4_ISA_DMA2_CH1LPG 0x8B +#define PIIX4_ISA_DMA2_LPGRFR 0x8F + +#define PIIX4_ISA_PORT_92 0x92 + +#define PIIX4_ISA_APM_CONTRL 0xB2 +#define PIIX4_ISA_APM_STATUS 0xB3 + +#define PIIX4_ISA_COCPU_ERROR 0xF0 + +/* Function 1 IDE Controller */ +#define PCI_CFG_PIIX4_BMIBA 0x20 +#define PCI_CFG_PIIX4_IDETIM 0x40 +#define PCI_CFG_PIIX4_SIDETIM 0x44 +#define PCI_CFG_PIIX4_UDMACTL 0x48 +#define PCI_CFG_PIIX4_UDMATIM 0x4A + +/* Function 2 USB Controller */ +#define PCI_CFG_PIIX4_SBRNUM 0x60 +#define PCI_CFG_PIIX4_LEGSUP 0xC0 + +/* Function 3 Power Management */ +#define PCI_CFG_PIIX4_PMAB 0x40 +#define PCI_CFG_PIIX4_CNTA 0x44 +#define PCI_CFG_PIIX4_CNTB 0x48 +#define PCI_CFG_PIIX4_GPICTL 0x4C +#define PCI_CFG_PIIX4_DEVRESD 0x50 +#define PCI_CFG_PIIX4_DEVACTA 0x54 +#define PCI_CFG_PIIX4_DEVACTB 0x58 +#define PCI_CFG_PIIX4_DEVRESA 0x5C +#define PCI_CFG_PIIX4_DEVRESB 0x60 +#define PCI_CFG_PIIX4_DEVRESC 0x64 +#define PCI_CFG_PIIX4_DEVRESE 0x68 +#define PCI_CFG_PIIX4_DEVRESF 0x6C +#define PCI_CFG_PIIX4_DEVRESG 0x70 +#define PCI_CFG_PIIX4_DEVRESH 0x74 +#define PCI_CFG_PIIX4_DEVRESI 0x78 +#define PCI_CFG_PIIX4_PMMISC 0x80 +#define PCI_CFG_PIIX4_SMBBA 0x90 + + +#endif /* _PIIX4_PCI_H */ diff --git a/board/eXalion/u-boot.lds b/board/eXalion/u-boot.lds new file mode 100644 index 0000000..eaee3fd --- /dev/null +++ b/board/eXalion/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/eltec/bab7xx/Makefile b/board/eltec/bab7xx/Makefile new file mode 100644 index 0000000..7d8ed26 --- /dev/null +++ b/board/eltec/bab7xx/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o + +SOBJS = asm_init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/eltec/bab7xx/asm_init.S b/board/eltec/bab7xx/asm_init.S new file mode 100644 index 0000000..2a9b33e --- /dev/null +++ b/board/eltec/bab7xx/asm_init.S @@ -0,0 +1,1476 @@ +/* + * (C) Copyright 2001 ELTEC Elektronik AG + * Frank Gottschling + * + * ELTEC BAB PPC RAM initialization + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include <74xx_7xx.h> +#include +#include + +#include +#include + +/* + * This following contains the entry code for the initialization code + * for the MPC 106, a PCI Bridge/Memory Controller. + * Register usage: + * r0 = ramtest scratch register, toggleError loop counter + * r1 = 0xfec0 0cf8 CONFIG_ADDRESS + * r2 = 0xfee0 0cfc CONFIG_DATA + * r3 = scratch register, subroutine argument and return value, ramtest size + * r4 = scratch register, spdRead clock mask, OutHex loop count + * r5 = ramtest scratch register + * r6 = toggleError 1st value, spdRead port mask + * r7 = toggleError 2nd value, ramtest scratch register, + * spdRead scratch register (0x00) + * r8 = ramtest scratch register, spdRead scratch register (0x80) + * r9 = ramtest scratch register, toggleError loop end, OutHex digit + * r10 = ramtest scratch register, spdWriteByte parameter, + * spdReadByte return value, printf pointer to COM1 + * r11 = startType + * r12 = ramtest scratch register, spdRead data mask + * r13 = pointer to message block + * r14 = pointer to GOT + * r15 = scratch register, SPD save + * r16 = bank0 size, total memory size + * r17 = bank1 size + * r18 = bank2 size + * r19 = bank3 size + * r20 = MCCR1, MSAR1 + * r21 = MCCR3, MEAR1 + * r22 = MCCR4, MBER + * r23 = EMSAR1 + * r24 = EMEAR1 + * r25 = save link register 1st level + * r26 = save link register 2nd level + * r27 = save link register 3rd level + * r30 = pointer to GPIO for spdRead + */ + + +.globl board_asm_init +board_asm_init: +/* + * setup pointer to message block + */ + mflr r25 /* save away link register */ + bl get_lnk_reg /* r3=addr of next instruction */ + subi r4, r3, 8 /* r4=board_asm_init addr */ + addi r13, r4, (MessageBlock-board_asm_init) +/* + * dcache_disable + */ + mfspr r3, HID0 + li r4, HID0_DCE + andc r3, r3, r4 + mr r2, r3 + ori r3, r3, HID0_DCI + sync + mtspr HID0, r3 + mtspr HID0, r2 + isync + sync +/* + * icache_disable + */ + mfspr r3, HID0 + li r4, 0 + ori r4, r4, HID0_ICE + andc r3, r3, r4 + sync + mtspr HID0, r3 +/* + * invalidate caches + */ + ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE) + or r4, r4, r3 + isync + mtspr HID0, r4 + andc r4, r4, r3 + isync + mtspr HID0, r4 + isync +/* + * icache_enable + */ + mfspr r3, HID0 + ori r3, r3, (HID0_ICE | HID0_ICFI) + sync + mtspr HID0, r3 + + lis r1, 0xfec0 + ori r1, r1, 0x0cf8 + lis r2, 0xfee0 + ori r2, r2, 0xcfc + +#ifdef CFG_ADDRESS_MAP_A +/* + * Switch to address map A if necessary. + */ + lis r3, MPC106_REG@h + ori r3, r3, PCI_PICR1 + stwbrx r3, 0, r1 + sync + lwbrx r4, 0, r2 + sync + lis r0, PICR1_XIO_MODE@h + ori r0, r0, PICR1_XIO_MODE@l + andc r4, r4, r0 + lis r0, PICR1_ADDRESS_MAP@h + ori r0, r0, PICR1_ADDRESS_MAP@l + or r4, r4, r0 + stwbrx r4, 0, r2 + sync +#endif + +/* + * Do the init for the SIO. + */ + bl .sioInit + + addi r3, r13, (MinitLogo-MessageBlock) + bl Printf + + addi r3, r13, (Mspd01-MessageBlock) + bl Printf +/* + * Memory cofiguration using SPD information stored on the SODIMMs + */ + li r17, 0 + li r18, 0 + li r19, 0 + + li r3, 0x0002 /* get RAM type from spd for bank0/1 */ + bl spdRead + + cmpi 0, 0, r3, -1 /* error ? */ + bne noSpdError + + addi r3, r13, (Mfail-MessageBlock) + bl Printf + + li r6, 0xe0 /* error codes in r6 and r7 */ + li r7, 0x00 + b toggleError /* fail - loop forever */ + +noSpdError: + mr r15, r3 /* save r3 */ + + addi r3, r13, (Mok-MessageBlock) + bl Printf + + cmpli 0, 0, r15, 0x0001 /* FPM ? */ + beq configFPM + cmpli 0, 0, r15, 0x0002 /* EDO ? */ + beq configEDO + cmpli 0, 0, r15, 0x0004 /* SDRAM ? */ + beq configSDRAM + + li r6, 0xe0 /* error codes in r6 and r7 */ + li r7, 0x01 + b toggleError /* fail - loop forever */ + +configSDRAM: + addi r3, r13, (MsdRam-MessageBlock) + bl Printf +/* + * set the Memory Configuration Reg. 1 + */ + li r3, 0x001f /* get bank size from spd bank0/1 */ + bl spdRead + + andi. r3, r3, 0x0038 + beq SD16MB2B + + li r3, 0x0011 /* get number of internal banks */ + /* from spd for bank0/1 */ + bl spdRead + + cmpli 0, 0, r3, 0x02 + beq SD64MB2B + + cmpli 0, 0, r3, 0x04 + beq SD64MB4B + + li r6, 0xe0 /* error codes in r6 and r7 */ + li r7, 0x02 + b toggleError /* fail - loop forever */ + +SD64MB2B: + li r20, 0x0005 /* 64-Mbit SDRAM 2 banks */ + b SDRow2nd + +SD64MB4B: + li r20, 0x0000 /* 64-Mbit SDRAM 4 banks */ + b SDRow2nd + +SD16MB2B: + li r20, 0x000f /* 16-Mbit SDRAM 2 banks */ + +SDRow2nd: + li r3, 0x0102 /* get RAM type spd for bank2/3 */ + bl spdRead + + cmpli 0, 0, r3, 0x0004 + bne S2D64MB4B /* bank2/3 isn't present or no SDRAM */ + + li r3, 0x011f /* get bank size from spd bank2/3 */ + bl spdRead + + andi. r3, r3, 0x0038 + beq S2D16MB2B +/* + * set the Memory Configuration Reg. 2 + */ + li r3, 0x0111 /* get number of internal banks */ + /* from spd for bank2/3 */ + bl spdRead + + cmpli 0, 0, r3, 0x02 + beq S2D64MB2B + + cmpli 0, 0, r3, 0x04 + beq S2D64MB4B + + li r6, 0xe0 /* error codes in r6 and r7 */ + li r7, 0x03 + b toggleError /* fail - loop forever */ + +S2D64MB2B: + ori r20, r20, 0x0050 /* 64-Mbit SDRAM 2 banks */ + b S2D64MB4B + +S2D16MB2B: + ori r20, r20, 0x00f0 /* 16-Mbit SDRAM 2 banks */ + +/* + * set the Memory Configuration Reg. 3 + */ +S2D64MB4B: + lis r21, 0x8630 /* BSTOPRE = 0x80, REFREC = 6, */ + /* RDLAT = 3 */ + +/* + * set the Memory Configuration Reg. 4 + */ + lis r22, 0x2430 /* PRETOACT = 2, ACTOPRE = 4, */ + /* WCBUF = 1, RCBUF = 1 */ + ori r22, r22, 0x2220 /* SDMODE = 0x022, ACTORW = 2 */ + +/* + * get the size of bank 0-3 + */ + li r3, 0x001f /* get bank size from spd bank0/1 */ + bl spdRead + + rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte */ + /* (128 MB max.) */ + + li r3, 0x0005 /* get number of banks from spd */ + /* for bank0/1 */ + bl spdRead + + cmpi 0, 0, r3, 2 /* 2 banks ? */ + bne SDRAMnobank1 + + mr r17, r16 + +SDRAMnobank1: + addi r3, r13, (Mspd23-MessageBlock) + bl Printf + + li r3, 0x0102 /* get RAM type spd for bank2/3 */ + bl spdRead + + cmpli 0, 0, r3, 0x0001 /* FPM ? */ + bne noFPM23 /* handle as EDO */ + addi r3, r13, (Mok-MessageBlock) + bl Printf + addi r3, r13, (MfpmRam-MessageBlock) + bl Printf + b configRAMcommon +noFPM23: + cmpli 0, 0, r3, 0x0002 /* EDO ? */ + bne noEDO23 + addi r3, r13, (Mok-MessageBlock) + bl Printf + addi r3, r13, (MedoRam-MessageBlock) + bl Printf + b configRAMcommon +noEDO23: + cmpli 0, 0, r3, 0x0004 /* SDRAM ? */ + bne noSDRAM23 + addi r3, r13, (Mok-MessageBlock) + bl Printf + addi r3, r13, (MsdRam-MessageBlock) + bl Printf + b configSDRAM23 +noSDRAM23: + addi r3, r13, (Mna-MessageBlock) + bl Printf + b configRAMcommon /* bank2/3 isn't present or no SDRAM */ + +configSDRAM23: + li r3, 0x011f /* get bank size from spd bank2/3 */ + bl spdRead + + rlwinm r18, r3, 2, 24, 29 /* calculate size in MByte */ + /* (128 MB max.) */ + + li r3, 0x0105 /* get number of banks from */ + /* spd bank0/1 */ + bl spdRead + + cmpi 0, 0, r3, 2 /* 2 banks ? */ + bne SDRAMnobank3 + + mr r19, r18 + +SDRAMnobank3: + b configRAMcommon + +configFPM: + addi r3, r13, (MfpmRam-MessageBlock) + bl Printf + b configEDO0 +/* + * set the Memory Configuration Reg. 1 + */ +configEDO: + addi r3, r13, (MedoRam-MessageBlock) + bl Printf +configEDO0: + lis r20, MCCR1_TYPE_EDO@h + +getSpdRowBank01: + li r3, 0x0003 /* get number of row bits from */ + /* spd from bank0/1 */ + bl spdRead + ori r20, r20, (MCCR1_BK0_9BITS | MCCR1_BK1_9BITS) + cmpli 0, 0, r3, 0x0009 /* bank0 - 9 row bits */ + beq getSpdRowBank23 + + ori r20, r20, (MCCR1_BK0_10BITS | MCCR1_BK1_10BITS) + cmpli 0, 0, r3, 0x000a /* bank0 - 10 row bits */ + beq getSpdRowBank23 + + ori r20, r20, (MCCR1_BK0_11BITS | MCCR1_BK1_11BITS) + cmpli 0, 0, r3, 0x000b /* bank0 - 11 row bits */ + beq getSpdRowBank23 + + ori r20, r20, (MCCR1_BK0_12BITS | MCCR1_BK1_12BITS) + cmpli 0, 0, r3, 0x000c /* bank0 - 12 row bits */ + beq getSpdRowBank23 + + cmpli 0, 0, r3, 0x000d /* bank0 - 13 row bits */ + beq getSpdRowBank23 + + li r6, 0xe0 /* error codes in r6 and r7 */ + li r7, 0x10 + b toggleError /* fail - loop forever */ + +getSpdRowBank23: + li r3, 0x0103 /* get number of row bits from */ + /* spd for bank2/3 */ + bl spdRead + + ori r20, r20, (MCCR1_BK2_9BITS | MCCR1_BK3_9BITS) + cmpli 0, 0, r3, 0x0009 /* bank0 - 9 row bits */ + beq writeRowBits + + ori r20, r20, (MCCR1_BK2_10BITS | MCCR1_BK3_10BITS) + cmpli 0, 0, r3, 0x000a /* bank0 - 10 row bits */ + beq writeRowBits + + ori r20, r20, (MCCR1_BK2_11BITS | MCCR1_BK3_11BITS) + cmpli 0, 0, r3, 0x000b /* bank0 - 11 row bits */ + beq writeRowBits + + ori r20, r20, (MCCR1_BK2_12BITS | MCCR1_BK3_12BITS) + +/* + * set the Memory Configuration Reg. 3 + */ +writeRowBits: + lis r21, 0x000a /* CPX = 1, RAS6P = 4 */ + ori r21, r21, 0x2293 /* CAS5 = 2, CP4 = 1, */ + /* CAS3 = 2, RCD2 = 2, RP = 3 */ +/* + * set the Memory Configuration Reg. 4 + */ + lis r22, 0x0010 /* all SDRAM parameter 0, */ + /* WCBUF flow through, */ + /* RCBUF registered */ +/* + * get the size of bank 0-3 + */ + li r3, 0x0003 /* get row bits from spd bank0/1 */ + bl spdRead + + li r16, 0 /* bank size is: */ + /* (8*2^row*2^column)/0x100000 MB */ + ori r16, r16, 0x8000 + rlwnm r16, r16, r3, 0, 31 + + li r3, 0x0004 /* get column bits from spd bank0/1 */ + bl spdRead + + rlwnm r16, r16, r3, 0, 31 + + li r3, 0x0005 /* get number of banks from */ + /* spd for bank0/1 */ + bl spdRead + + cmpi 0, 0, r3, 2 /* 2 banks ? */ + bne EDOnobank1 + + mr r17, r16 + +EDOnobank1: + addi r3, r13, (Mspd23-MessageBlock) + bl Printf + + li r3, 0x0102 /* get RAM type spd for bank2/3 */ + bl spdRead + + cmpli 0, 0, r3, 0x0001 /* FPM ? */ + bne noFPM231 /* handle as EDO */ + addi r3, r13, (Mok-MessageBlock) + bl Printf + addi r3, r13, (MfpmRam-MessageBlock) + bl Printf + b EDObank2 +noFPM231: + cmpli 0, 0, r3, 0x0002 /* EDO ? */ + bne noEDO231 + addi r3, r13, (Mok-MessageBlock) + bl Printf + addi r3, r13, (MedoRam-MessageBlock) + bl Printf + b EDObank2 +noEDO231: + cmpli 0, 0, r3, 0x0004 /* SDRAM ? */ + bne noSDRAM231 + addi r3, r13, (Mok-MessageBlock) + bl Printf + addi r3, r13, (MsdRam-MessageBlock) + bl Printf + b configRAMcommon +noSDRAM231: + addi r3, r13, (Mfail-MessageBlock) + bl Printf + b configRAMcommon /* bank2/3 isn't present or no SDRAM */ + +EDObank2: + li r3, 0x0103 /* get row bits from spd for bank2/3 */ + bl spdRead + + li r18, 0 /* bank size is: */ + /* (8*2^row*2^column)/0x100000 MB */ + ori r18, r18, 0x8000 + rlwnm r18, r18, r3, 0, 31 + + li r3, 0x0104 /* get column bits from spd bank2/3 */ + bl spdRead + + rlwnm r18, r18, r3, 0, 31 + + li r3, 0x0105 /* get number of banks from */ + /* spd for bank2/3 */ + bl spdRead + + cmpi 0, 0, r3, 2 /* 2 banks ? */ + bne configRAMcommon + + mr r19, r18 + +configRAMcommon: + lis r1, MPC106_REG_ADDR@h + ori r1, r1, MPC106_REG_ADDR@l + lis r2, MPC106_REG_DATA@h + ori r2, r2, MPC106_REG_DATA@l + + li r0, 0 + +/* + * If we are already running in RAM (debug mode), we should + * NOT reset the MEMGO flag. Otherwise we will stop all memory + * accesses. + */ +#ifdef IN_RAM + lis r4, MCCR1_MEMGO@h + ori r4, r4, MCCR1_MEMGO@l + or r20, r20, r4 +#endif + +/* + * set the Memory Configuration Reg. 1 + */ + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_MCCR1 /* register number 0xf0 */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stwbrx r20, r0, r2 /* write data to CONFIG_DATA */ +/* + * set the Memory Configuration Reg. 3 + */ + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_MCCR3 /* register number 0xf8 */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stwbrx r21, r0, r2 /* write data to CONFIG_DATA */ +/* + * set the Memory Configuration Reg. 4 + */ + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_MCCR4 /* register number 0xfc */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stwbrx r22, r0, r2 /* write data to CONFIG_DATA */ +/* + * set the memory boundary registers for bank 0-3 + */ + li r20, 0 + li r23, 0 + li r24, 0 + subi r21, r16, 1 /* calculate end address bank0 */ + li r22, (MBER_BANK0) + + cmpi 0, 0, r17, 0 /* bank1 present ? */ + beq nobank1 + + rlwinm r3, r16, 8, 16, 23 /* calculate start address of bank1 */ + or r20, r20, r3 + add r16, r16, r17 /* add to total memory size */ + subi r3, r16, 1 /* calculate end address of bank1 */ + rlwinm r3, r3, 8, 16, 23 + or r21, r21, r3 + ori r22, r22, (MBER_BANK1) /* enable bank1 */ + b bank2 + +nobank1: + ori r23, r23, 0x0300 /* set bank1 start to unused area */ + ori r24, r24, 0x0300 /* set bank1 end to unused area */ + +bank2: + cmpi 0, 0, r18, 0 /* bank2 present ? */ + beq nobank2 + + andi. r3, r16, 0x00ff /* calculate start address of bank2 */ + andi. r4, r16, 0x0300 + rlwinm r3, r3, 16, 8, 15 + or r20, r20, r3 + rlwinm r3, r4, 8, 8, 15 + or r23, r23, r3 + add r16, r16, r18 /* add to total memory size */ + subi r3, r16, 1 /* calculate end address of bank2 */ + andi. r4, r3, 0x0300 + andi. r3, r3, 0x00ff + rlwinm r3, r3, 16, 8, 15 + or r21, r21, r3 + rlwinm r3, r4, 8, 8, 15 + or r24, r24, r3 + ori r22, r22, (MBER_BANK2) /* enable bank2 */ + b bank3 + +nobank2: + lis r3, 0x0003 + or r23, r23, r3 /* set bank2 start to unused area */ + or r24, r24, r3 /* set bank2 end to unused area */ + +bank3: + cmpi 0, 0, r19, 0 /* bank3 present ? */ + beq nobank3 + + andi. r3, r16, 0x00ff /* calculate start address of bank3 */ + andi. r4, r16, 0x0300 + rlwinm r3, r3, 24, 0, 7 + or r20, r20, r3 + rlwinm r3, r4, 16, 0, 7 + or r23, r23, r3 + add r16, r16, r19 /* add to total memory size */ + subi r3, r16, 1 /* calculate end address of bank3 */ + andi. r4, r3, 0x0300 + andi. r3, r3, 0x00ff + rlwinm r3, r3, 24, 0, 7 + or r21, r21, r3 + rlwinm r3, r4, 16, 0, 7 + or r24, r24, r3 + ori r22, r22, (MBER_BANK3) /* enable bank3 */ + b writebound + +nobank3: + lis r3, 0x0300 + or r23, r23, r3 /* set bank3 start to unused area */ + or r24, r24, r3 /* set bank3 end to unused area */ + +writebound: + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_MSAR1 /* register number 0x80 */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stwbrx r20, r0, r2 /* write data to CONFIG_DATA */ + + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_MEAR1 /* register number 0x90 */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stwbrx r21, r0, r2 /* write data to CONFIG_DATA */ + + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_EMSAR1 /* register number 0x88 */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stwbrx r23, r0, r2 /* write data to CONFIG_DATA */ + + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_EMEAR1 /* register number 0x98 */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stwbrx r24, r0, r2 /* write data to CONFIG_DATA */ + +/* + * set boundaries of unused banks to unused address space + */ + lis r4, 0x0303 + ori r4, r4, 0x0303 /* bank 4-7 start and end adresses */ + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_EMSAR2 /* register number 0x8C */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stwbrx r4, r0, r2 /* write data to CONFIG_DATA */ + + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_EMEAR2 /* register number 0x9C */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stwbrx r4, r0, r2 /* write data to CONFIG_DATA */ + +/* + * set the Memory Configuration Reg. 2 + */ + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_MCCR2 /* register number 0xf4 */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + + li r3, 0x000c /* get refresh from spd for bank0/1 */ + bl spdRead + + cmpi 0, 0, r3, -1 /* error ? */ + bne common1 + + li r6, 0xe0 /* error codes in r6 and r7 */ + li r7, 0x20 + b toggleError /* fail - loop forever */ + +common1: + andi. r15, r3, 0x007f /* mask selfrefresh bit */ + li r3, 0x010c /* get refresh from spd for bank2/3 */ + bl spdRead + + cmpi 0, 0, r3, -1 /* error ? */ + beq common2 + andi. r3, r3, 0x007f /* mask selfrefresh bit */ + cmp 0, 0, r3, r15 /* find the lower */ + blt common3 + +common2: + mr r3, r15 + +common3: + li r4, 0x1010 /* refesh cycle 1028 clocks */ + /* left shifted 2 */ + cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */ + beq writeRefresh + + li r4, 0x0808 /* refesh cycle 514 clocks */ + /* left shifted 2 */ + cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */ + beq writeRefresh + + li r4, 0x2020 /* refesh cycle 2056 clocks */ + /* left shifted 2 */ + cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */ + beq writeRefresh + + li r4, 0x4040 /* refesh cycle 4112 clocks */ + /* left shifted 2 */ + cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */ + beq writeRefresh + + li r4, 0 + ori r4, r4, 0x8080 /* refesh cycle 8224 clocks */ + /* left shifted 2 */ + cmpli 0, 0, r3, 0x0005 /* 125 us ? */ + beq writeRefresh + + li r6, 0xe0 /* error codes in r6 and r7 */ + li r7, 0x21 + b toggleError /* fail - loop forever */ + +writeRefresh: + stwbrx r4, r0, r2 /* write data to CONFIG_DATA */ + +/* + * DRAM BANKS SHOULD BE ENABLED + */ + addi r3, r13, (Mactivate-MessageBlock) + bl Printf + mr r3, r16 + bl OutDec + addi r3, r13, (Mmbyte-MessageBlock) + bl Printf + + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_MBER /* register number 0xa0 */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + stb r22, 0(r2) /* write data to CONFIG_DATA */ + li r8, 0x63 /* PGMAX = 99 */ + stb r8, 3(r2) /* write data to CONFIG_DATA */ + +/* + * DRAM SHOULD NOW BE CONFIGURED AND ENABLED + * MUST WAIT 200us BEFORE ACCESSING + */ + li r0, 0x7800 + mtctr r0 + +wait200us: + bdnz wait200us + + lis r3, MPC106_REG@h /* start building new reg number */ + ori r3, r3, MPC106_MCCR1 /* register number 0xf0 */ + stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ + eieio /* make sure mem. access is complete */ + + lwbrx r4, r0, r2 /* load r4 from CONFIG_DATA */ + + lis r0, MCCR1_MEMGO@h /* MEMGO=1 */ + ori r0, r0, MCCR1_MEMGO@l + or r4, r4, r0 /* set the MEMGO bit */ + stwbrx r4, r0, r2 /* write mdfd data to CONFIG_DATA */ + + li r0, 0x7000 + mtctr r0 + +wait8ref: + bdnz wait8ref + + addi r3, r13, (Mok-MessageBlock) + bl Printf + + mtlr r25 + blr + +/* + * Infinite loop called in case of an error during RAM initialisation. + * error codes in r6 and r7. + */ +toggleError: + li r0, 0 + lis r9, 127 + ori r9, r9, 65535 +toggleError1: + addic r0, r0, 1 + cmpw cr1, r0, r9 + ble cr1, toggleError1 + li r0, 0 + lis r9, 127 + ori r9, r9, 65535 +toggleError2: + addic r0, r0, 1 + cmpw cr1, r0, r9 + ble cr1, toggleError2 + b toggleError + + +/****************************************************************************** + * This function performs a basic initialisation of the superio chip + * to enable basic console output and SPD access during RAM initialisation. + * + * Upon completion, SIO resource registers are mapped as follows: + * Resource Enabled Address + * UART1 Yes 3F8-3FF COM1 + * UART2 Yes 2F8-2FF COM2 + * GPIO Yes 220-227 + */ +.set SIO_LUNINDEX, 0x07 /* SIO LUN index register */ +.set SIO_CNFG1, 0x21 /* SIO configuration #1 register */ +.set SIO_PCSCI, 0x23 /* SIO PCS configuration index reg */ +.set SIO_PCSCD, 0x24 /* SIO PCS configuration data reg */ +.set SIO_ACTIVATE, 0x30 /* SIO activate register */ +.set SIO_IOBASEHI, 0x60 /* SIO I/O port base address, 15:8 */ +.set SIO_IOBASELO, 0x61 /* SIO I/O port base address, 7:0 */ +.set SIO_LUNENABLE, 0x01 /* SIO LUN enable */ + +.sioInit: + mfspr r7, 8 /* save link register */ + +.sioInit_87308: + +/* + * Get base addr of ISA I/O space + */ + lis r6, CFG_ISA_IO@h + ori r6, r6, CFG_ISA_IO@l + +/* + * Set offset to base address for config registers. + */ +#if defined(CFG_NS87308_BADDR_0x) + addi r4, r0, 0x0279 +#elif defined(CFG_NS87308_BADDR_10) + addi r4, r0, 0x015C +#elif defined(CFG_NS87308_BADDR_11) + addi r4, r0, 0x002E +#endif + add r6, r6, r4 /* add offset to base */ + or r3, r6, r6 /* make a copy */ + +/* + * PMC (LUN 8) + */ + addi r4, r0, SIO_LUNINDEX /* select PMC LUN */ + addi r5, r0, 0x8 + bl .sio_bw + addi r4, r0, SIO_IOBASEHI /* initialize PMC address to 0x460 */ + addi r5, r0, 0x04 + bl .sio_bw + addi r4, r0, SIO_IOBASELO + addi r5, r0, 0x60 + bl .sio_bw + addi r4, r0, SIO_ACTIVATE /* enable PMC */ + addi r5, r0, SIO_LUNENABLE + bl .sio_bw + + lis r8, CFG_ISA_IO@h + ori r8, r8, 0x0460 + li r9, 0x03 + stb r9, 0(r8) /* select PMC2 register */ + eieio + li r9, 0x00 + stb r9, 1(r8) /* SuperI/O clock src: 24MHz via X1 */ + eieio + +/* + * map UART1 (LUN 6) or UART2 (LUN 5) to COM1 (0x3F8) + */ + addi r4, r0, SIO_LUNINDEX /* select COM1 LUN */ + addi r5, r0, 0x6 + bl .sio_bw + + addi r4, r0, SIO_IOBASEHI /* initialize COM1 address to 0x3F8 */ + addi r5, r0, 0x03 + bl .sio_bw + + addi r4, r0, SIO_IOBASELO + addi r5, r0, 0xF8 + bl .sio_bw + + addi r4, r0, SIO_ACTIVATE /* enable COM1 */ + addi r5, r0, SIO_LUNENABLE + bl .sio_bw + +/* + * Init COM1 for polled output + */ + lis r8, CFG_ISA_IO@h + ori r8, r8, 0x03f8 + li r9, 0x00 + stb r9, 1(r8) /* int disabled */ + eieio + li r9, 0x00 + stb r9, 4(r8) /* modem ctrl */ + eieio + li r9, 0x80 + stb r9, 3(r8) /* link ctrl, bank select */ + eieio + li r9, 115200/CONFIG_BAUDRATE + stb r9, 0(r8) /* baud rate (LSB)*/ + eieio + rotrwi r9, r9, 8 + stb r9, 1(r8) /* baud rate (MSB) */ + eieio + li r9, 0x03 + stb r9, 3(r8) /* 8 data bits, 1 stop bit, */ + /* no parity */ + eieio + li r9, 0x0b + stb r9, 4(r8) /* enable the receiver and transmitter */ + eieio + +waitEmpty: + lbz r9, 5(r8) /* transmit empty */ + andi. r9, r9, 0x40 + beq waitEmpty + li r9, 0x47 + stb r9, 3(r8) /* send break, 8 data bits, */ + /* 2 stop bits, no parity */ + eieio + + lis r0, 0x0001 + mtctr r0 + +waitCOM1: + lwz r0, 5(r8) /* load from port for delay */ + bdnz waitCOM1 + +waitEmpty1: + lbz r9, 5(r8) /* transmit empty */ + andi. r9, r9, 0x40 + beq waitEmpty1 + li r9, 0x07 + stb r9, 3(r8) /* 8 data bits, 2 stop bits, */ + /* no parity */ + eieio + +/* + * GPIO (LUN 7) + */ + addi r4, r0, SIO_LUNINDEX /* select GPIO LUN */ + addi r5, r0, 0x7 + bl .sio_bw + + addi r4, r0, SIO_IOBASEHI /* initialize GPIO address to 0x220 */ + addi r5, r0, 0x02 + bl .sio_bw + + addi r4, r0, SIO_IOBASELO + addi r5, r0, 0x20 + bl .sio_bw + + addi r4, r0, SIO_ACTIVATE /* enable GPIO */ + addi r5, r0, SIO_LUNENABLE + bl .sio_bw + +.sioInit_done: + +/* + * Get base addr of ISA I/O space + */ + lis r3, CFG_ISA_IO@h + ori r3, r3, CFG_ISA_IO@l + + addi r3, r3, 0x015C /* adjust to superI/O 87308 base */ + or r6, r3, r3 /* make a copy */ +/* + * CS0 + */ + addi r4, r0, SIO_PCSCI /* select PCSCIR */ + addi r5, r0, 0x00 + bl .sio_bw + addi r4, r0, SIO_PCSCD /* select PCSCDR */ + addi r5, r0, 0x00 + bl .sio_bw + addi r4, r0, SIO_PCSCI /* select PCSCIR */ + addi r5, r0, 0x01 + bl .sio_bw + addi r4, r0, SIO_PCSCD /* select PCSCDR */ + addi r5, r0, 0x76 + bl .sio_bw + addi r4, r0, SIO_PCSCI /* select PCSCIR */ + addi r5, r0, 0x02 + bl .sio_bw + addi r4, r0, SIO_PCSCD /* select PCSCDR */ + addi r5, r0, 0x40 + bl .sio_bw +/* + * CS1 + */ + addi r4, r0, SIO_PCSCI /* select PCSCIR */ + addi r5, r0, 0x05 + bl .sio_bw + addi r4, r0, SIO_PCSCD /* select PCSCDR */ + addi r5, r0, 0x00 + bl .sio_bw + addi r4, r0, SIO_PCSCI /* select PCSCIR */ + addi r5, r0, 0x05 + bl .sio_bw + addi r4, r0, SIO_PCSCD /* select PCSCDR */ + addi r5, r0, 0x70 + bl .sio_bw + addi r4, r0, SIO_PCSCI /* select PCSCIR */ + addi r5, r0, 0x06 + bl .sio_bw + addi r4, r0, SIO_PCSCD /* select PCSCDR */ + addi r5, r0, 0x1C + bl .sio_bw +/* + * CS2 + */ + addi r4, r0, SIO_PCSCI /* select PCSCIR */ + addi r5, r0, 0x08 + bl .sio_bw + addi r4, r0, SIO_PCSCD /* select PCSCDR */ + addi r5, r0, 0x00 + bl .sio_bw + addi r4, r0, SIO_PCSCI /* select PCSCIR */ + addi r5, r0, 0x09 + bl .sio_bw + addi r4, r0, SIO_PCSCD /* select PCSCDR */ + addi r5, r0, 0x71 + bl .sio_bw + addi r4, r0, SIO_PCSCI /* select PCSCIR */ + addi r5, r0, 0x0A + bl .sio_bw + addi r4, r0, SIO_PCSCD /* select PCSCDR */ + addi r5, r0, 0x1C + bl .sio_bw + + mtspr 8, r7 /* restore link register */ + bclr 20, 0 /* return to caller */ + +/* + * this function writes a register to the SIO chip + */ +.sio_bw: + stb r4, 0(r3) /* write index register with register offset */ + eieio + sync + stb r5, 1(r3) /* 1st write */ + eieio + sync + stb r5, 1(r3) /* 2nd write */ + eieio + sync + bclr 20, 0 /* return to caller */ +/* + * this function reads a register from the SIO chip + */ +.sio_br: + stb r4, 0(r3) /* write index register with register offset */ + eieio + sync + lbz r3, 1(r3) /* retrieve specified reg offset contents */ + eieio + sync + bclr 20, 0 /* return to caller */ + +/* + * Print a message to COM1 in polling mode + * r10=COM1 port, r3=(char*)string + */ +.globl Printf +Printf: + lis r10, CFG_ISA_IO@h /* COM1 port */ + ori r10, r10, 0x03f8 + +WaitChr: + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, WaitChr /* wait till empty */ + lbzx r0, r0, r3 /* get char */ + stb r0, 0(r10) /* write to transmit reg */ + eieio + addi r3, r3, 1 /* next char */ + lbzx r0, r0, r3 /* get char */ + cmpwi cr1, r0, 0 /* end of string ? */ + bne cr1, WaitChr + blr + +/* + * Print 8/4/2 digits hex value to COM1 in polling mode + * r10=COM1 port, r3=val + */ +OutHex2: + li r9, 4 /* shift reg for 2 digits */ + b OHstart +OutHex4: + li r9, 12 /* shift reg for 4 digits */ + b OHstart + .globl OutHex +OutHex: + li r9, 28 /* shift reg for 8 digits */ +OHstart: + lis r10, CFG_ISA_IO@h /* COM1 port */ + ori r10, r10, 0x03f8 +OutDig: + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutDig + sraw r0, r3, r9 + clrlwi r0, r0, 28 + cmpwi cr1, r0, 9 + ble cr1, digIsNum + addic r0, r0, 55 + b nextDig +digIsNum: + addic r0, r0, 48 +nextDig: + stb r0, 0(r10) /* write to transmit reg */ + eieio + addic. r9, r9, -4 + bge OutDig + blr +/* + * Print 3 digits hdec value to COM1 in polling mode + * r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch + */ +.globl OutDec +OutDec: + li r6, 10 + divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */ + mullw r10, r0, r6 + subf r9, r10, r3 + + mr r3, r0 + divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */ + mullw r10, r0, r6 + subf r8, r10, r3 + + mr r3, r0 + divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */ + mullw r10, r0, r6 + subf r7, r10, r3 + + lis r10, CFG_ISA_IO@h /* COM1 port */ + ori r10, r10, 0x03f8 + + or. r7, r7, r7 + bne noblank1 + li r3, 0x20 + b OutDec4 + +noblank1: + addi r3, r7, 48 /* convert to ASCII */ + +OutDec4: + lbz r0, 0(r13) /* slow down dummy read */ + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutDec4 + stb r3, 0(r10) /* x00 to transmit */ + eieio + + or. r7, r7, r8 + beq OutDec5 + + addi r3, r8, 48 /* convert to ASCII */ +OutDec5: + lbz r0, 0(r13) /* slow down dummy read */ + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutDec5 + stb r3, 0(r10) /* x0 to transmit */ + eieio + + addi r3, r9, 48 /* convert to ASCII */ +OutDec6: + lbz r0, 0(r13) /* slow down dummy read */ + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutDec6 + stb r3, 0(r10) /* x to transmit */ + eieio + blr +/* + * Print a char to COM1 in polling mode + * r10=COM1 port, r3=char + */ +.globl OutChr +OutChr: + lis r10, CFG_ISA_IO@h /* COM1 port */ + ori r10, r10, 0x03f8 + +OutChr1: + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutChr1 /* wait till empty */ + stb r3, 0(r10) /* write to transmit reg */ + eieio + blr +/* + * Input: r3 adr to read + * Output: r3 val or -1 for error + */ +spdRead: + mfspr r26, 8 /* save link register */ + + lis r30, CFG_ISA_IO@h + ori r30, r30, 0x220 /* GPIO Port 1 */ + li r7, 0x00 + li r8, 0x100 + and. r5, r3, r8 + beq spdbank0 + li r12, 0x08 + li r4, 0x10 + li r6, 0x18 + b spdRead1 + +spdbank0: + li r12, 0x20 /* set I2C data */ + li r4, 0x40 /* set I2C clock */ + li r6, 0x60 /* set I2C clock and data */ + +spdRead1: + li r8, 0x80 + + bl spdStart /* access I2C bus as master */ + li r10, 0xa0 /* write to SPD */ + bl spdWriteByte + bl spdReadAck /* ACK returns in r10 */ + cmpw cr0, r10, r7 + bne AckErr /* r10 must be 0, if ACK received */ + mr r10, r3 /* adr to read */ + bl spdWriteByte + bl spdReadAck + cmpw cr0, r10, r7 + bne AckErr + bl spdStart + li r10, 0xa1 /* read from SPD */ + bl spdWriteByte + bl spdReadAck + cmpw cr0, r10, r7 + bne AckErr + bl spdReadByte /* return val in r10 */ + bl spdWriteAck + bl spdStop /* release I2C bus */ + mr r3, r10 + mtspr 8, r26 /* restore link register */ + blr +/* + * ACK error occurred + */ +AckErr: + bl spdStop + orc r3, r0, r0 /* return -1 */ + mtspr 8, r26 /* restore link register */ + blr + +/* + * Routines to read from RAM spd. + * r30 - GPIO Port1 address in all cases. + * r4 - clock mask for SPD + * r6 - port mask for SPD + * r12 - data mask for SPD + */ +waitSpd: + li r0, 0x1000 + mtctr r0 +wSpd: + bdnz wSpd + bclr 20, 0 /* return to caller */ + +/* + * establish START condition on I2C bus + */ +spdStart: + mfspr r27, 8 /* save link register */ + stb r6, 0(r30) /* set SDA and SCL */ + eieio + stb r6, 1(r30) /* switch GPIO to output */ + eieio + bl waitSpd + stb r4, 0(r30) /* reset SDA */ + eieio + bl waitSpd + stb r7, 0(r30) /* reset SCL */ + eieio + bl waitSpd + mtspr 8, r27 + bclr 20, 0 /* return to caller */ + +/* + * establish STOP condition on I2C bus + */ +spdStop: + mfspr r27, 8 /* save link register */ + stb r7, 0(r30) /* reset SCL and SDA */ + eieio + stb r6, 1(r30) /* switch GPIO to output */ + eieio + bl waitSpd + stb r4, 0(r30) /* set SCL */ + eieio + bl waitSpd + stb r6, 0(r30) /* set SDA and SCL */ + eieio + bl waitSpd + stb r7, 1(r30) /* switch GPIO to input */ + eieio + mtspr 8, r27 + bclr 20, 0 /* return to caller */ + +spdReadByte: + mfspr r27, 8 + stb r4, 1(r30) /* set GPIO for SCL output */ + eieio + li r9, 0x08 + li r10, 0x00 +loopRB: + stb r7, 0(r30) /* reset SDA and SCL */ + eieio + bl waitSpd + stb r4, 0(r30) /* set SCL */ + eieio + bl waitSpd + lbz r5, 0(r30) /* read from GPIO Port1 */ + rlwinm r10, r10, 1, 0, 31 + and. r5, r5, r12 + beq clearBit + ori r10, r10, 0x01 /* append _1_ */ +clearBit: + stb r7, 0(r30) /* reset SCL */ + eieio + bl waitSpd + addic. r9, r9, -1 + bne loopRB + mtspr 8, r27 + bclr 20, 0 /* return (r10) to caller */ + +/* + * spdWriteByte writes bits 24 - 31 of r10 to I2C. + * r8 contains bit mask 0x80 + */ +spdWriteByte: + mfspr r27, 8 /* save link register */ + li r9, 0x08 /* write octet */ + and. r5, r10, r8 + bne sWB1 + stb r7, 0(r30) /* set SDA to _0_ */ + eieio + b sWB2 +sWB1: + stb r12, 0(r30) /* set SDA to _1_ */ + eieio +sWB2: + stb r6, 1(r30) /* set GPIO to output */ + eieio +loopWB: + and. r5, r10, r8 + bne sWB3 + stb r7, 0(r30) /* set SDA to _0_ */ + eieio + b sWB4 +sWB3: + stb r12, 0(r30) /* set SDA to _1_ */ + eieio +sWB4: + bl waitSpd + and. r5, r10, r8 + bne sWB5 + stb r4, 0(r30) /* set SDA to _0_ and SCL */ + eieio + b sWB6 +sWB5: + stb r6, 0(r30) /* set SDA to _1_ and SCL */ + eieio +sWB6: + bl waitSpd + and. r5, r10, r8 + bne sWB7 + stb r7, 0(r30) /* set SDA to _0_ and reset SCL */ + eieio + b sWB8 +sWB7: + stb r12, 0(r30) /* set SDA to _1_ and reset SCL */ + eieio +sWB8: + bl waitSpd + rlwinm r10, r10, 1, 0, 31 /* next bit */ + addic. r9, r9, -1 + bne loopWB + mtspr 8, r27 + bclr 20, 0 /* return to caller */ + +/* + * Read ACK from SPD, return value in r10 + */ +spdReadAck: + mfspr r27, 8 /* save link register */ + stb r4, 1(r30) /* set GPIO to output */ + eieio + stb r7, 0(r30) /* reset SDA and SCL */ + eieio + bl waitSpd + stb r4, 0(r30) /* set SCL */ + eieio + bl waitSpd + lbz r10, 0(r30) /* read GPIO Port 1 and mask SDA */ + and r10, r10, r12 + bl waitSpd + stb r7, 0(r30) /* reset SDA and SCL */ + eieio + bl waitSpd + mtspr 8, r27 + bclr 20, 0 /* return (r10) to caller */ + +spdWriteAck: + mfspr r27, 8 + stb r12, 0(r30) /* set SCL */ + eieio + stb r6, 1(r30) /* set GPIO to output */ + eieio + bl waitSpd + stb r6, 0(r30) /* SDA and SCL */ + eieio + bl waitSpd + stb r12, 0(r30) /* reset SCL */ + eieio + bl waitSpd + mtspr 8, r27 + bclr 20, 0 /* return to caller */ + +get_lnk_reg: + mflr r3 /* return link reg */ + blr + +/* + * Messages for console output + */ +.globl MessageBlock +MessageBlock: +Mok: + .ascii "OK\015\012\000" +Mfail: + .ascii "FAILED\015\012\000" +Mna: + .ascii "NA\015\012\000" +MinitLogo: + .ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012" + .ascii "\015\012Initialising RAM\015\012\000" +Mspd01: + .ascii " Reading SPD of bank0/1 ..... \000" +Mspd23: + .ascii " Reading SPD of bank2/3 ..... \000" +MfpmRam: + .ascii " RAM-Type: FPM \015\012\000" +MedoRam: + .ascii " RAM-Type: EDO \015\012\000" +MsdRam: + .ascii " RAM-Type: SDRAM \015\012\000" +Mactivate: + .ascii " Activating \000" +Mmbyte: + .ascii " MB .......... \000" + .align 4 diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c new file mode 100644 index 0000000..fc48ed5 --- /dev/null +++ b/board/eltec/bab7xx/bab7xx.c @@ -0,0 +1,246 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * (C) Copyright 2001 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include <74xx_7xx.h> +#include +#include + +/*---------------------------------------------------------------------------*/ +/* + * Get Bus clock frequency + */ +ulong bab7xx_get_bus_freq (void) +{ + /* + * The GPIO Port 1 on BAB7xx reflects the bus speed. + */ + volatile struct GPIO *gpio = + (struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE); + + unsigned char data = gpio->dta1; + + if (data & 0x02) + return 66666666; + + return 83333333; +} + +/*---------------------------------------------------------------------------*/ + +/* + * Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz) + */ +ulong bab7xx_get_gclk_freq (void) +{ + static const int pllratio_to_factor[] = { + 00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35, + 00, + }; + + return pllratio_to_factor[get_hid1 () >> 28] * + (bab7xx_get_bus_freq () / 10); +} + +/*----------------------------------------------------------------------------*/ + +int checkcpu (void) +{ + uint pvr = get_pvr (); + + printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF); + printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000, + bab7xx_get_bus_freq () / 1000000); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +int checkboard (void) +{ +#ifdef CFG_ADDRESS_MAP_A + puts ("Board: ELTEC BAB7xx PReP\n"); +#else + puts ("Board: ELTEC BAB7xx CHRP\n"); +#endif + return (0); +} + +/* ------------------------------------------------------------------------- */ + +int checkflash (void) +{ + /* TODO: XXX XXX XXX */ + printf ("2 MB ## Test not implemented yet ##\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + + +static unsigned int mpc106_read_cfg_dword (unsigned int reg) +{ + unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC); + + out32r (MPC106_REG_ADDR, reg_addr); + + return (in32r (MPC106_REG_DATA | (reg & 0x3))); +} + +/* ------------------------------------------------------------------------- */ + +long int dram_size (int board_type) +{ + /* No actual initialisation to do - done when setting up + * PICRs MCCRs ME/SARs etc in ram_init.S. + */ + + register unsigned long i, msar1, mear1, memSize; + +#if defined(CFG_MEMTEST) + register unsigned long reg; + + printf ("Testing DRAM\n"); + + /* write each mem addr with it's address */ + for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) + *reg = reg; + + for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) { + if (*reg != reg) + return -1; + } +#endif + + /* + * Since MPC106 memory controller chip has already been set to + * control all memory, just read and interpret its memory boundery register. + */ + memSize = 0; + msar1 = mpc106_read_cfg_dword (MPC106_MSAR1); + mear1 = mpc106_read_cfg_dword (MPC106_MEAR1); + i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf; + + do { + if (i & 0x01) /* is bank enabled ? */ + memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1; + msar1 >>= 8; + mear1 >>= 8; + i >>= 1; + } while (i); + + return (memSize * 0x100000); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + return dram_size (board_type); +} + +/* ------------------------------------------------------------------------- */ + +void after_reloc (ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* + * Jump to the main U-Boot board init code + */ + board_init_r ((gd_t *) gd, dest_addr); +} + +/* ------------------------------------------------------------------------- */ + +/* + * do_reset is done here because in this case it is board specific, since the + * 7xx CPUs can only be reset by external HW (the RTC in this case). + */ +void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_RTC_MK48T59) + /* trigger watchdog immediately */ + rtc_set_watchdog (1, RTC_WD_RB_16TH); +#else +#error "You must define the macro CONFIG_RTC_MK48T59." +#endif +} + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_WATCHDOG) +/* + * Since the 7xx CPUs don't have an internal watchdog, this function is + * board specific. We use the RTC here. + */ +void watchdog_reset (void) +{ +#if defined(CONFIG_RTC_MK48T59) + /* we use a 32 sec watchdog timer */ + rtc_set_watchdog (8, RTC_WD_RB_4); +#else +#error "You must define the macro CONFIG_RTC_MK48T59." +#endif +} +#endif /* CONFIG_WATCHDOG */ + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +extern GraphicDevice smi; + +void video_get_info_str (int line_number, char *info) +{ + /* init video info strings for graphic console */ + switch (line_number) { + case 1: + sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz", + (get_pvr () >> 8) & 0xFF, + get_pvr () & 0xFF, + bab7xx_get_gclk_freq () / 1000000, + bab7xx_get_bus_freq () / 1000000); + return; + case 2: + sprintf (info, + " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH", + dram_size (0) / 0x100000, flash_init () / 0x100000); + return; + case 3: + sprintf (info, " %s", smi.modeIdent); + return; + } + + /* no more info lines */ + *info = 0; + return; +} +#endif + +/*---------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/config.mk b/board/eltec/bab7xx/config.mk new file mode 100644 index 0000000..aa463c5 --- /dev/null +++ b/board/eltec/bab7xx/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/eltec/bab7xx/dc_srom.c b/board/eltec/bab7xx/dc_srom.c new file mode 100644 index 0000000..a44af6e --- /dev/null +++ b/board/eltec/bab7xx/dc_srom.c @@ -0,0 +1,291 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * SRom I/O routines. + */ + +#include +#include +#include "srom.h" + +#define SROM_RD 0x00004000 /* Read from Boot ROM */ +#define SROM_WR 0x00002000 /* Write to Boot ROM */ +#define SROM_SR 0x00000800 /* Select Serial ROM when set */ + +#define DT_IN 0x00000004 /* Serial Data In */ +#define DT_CLK 0x00000002 /* Serial ROM Clock */ +#define DT_CS 0x00000001 /* Serial ROM Chip Select */ + +static u_int dc_srom_iobase; + +/*----------------------------------------------------------------------------*/ + +static int inl(u_long addr) +{ + return le32_to_cpu(*(volatile u_long *)(addr)); +} + +/*----------------------------------------------------------------------------*/ + +static void outl (int command, u_long addr) +{ + *(volatile u_long *)(addr) = cpu_to_le32(command); +} + +/*----------------------------------------------------------------------------*/ + +static void sendto_srom(u_int command, u_long addr) +{ + outl(command, addr); + udelay(1); + + return; +} + +/*----------------------------------------------------------------------------*/ + +static int getfrom_srom(u_long addr) +{ + s32 tmp; + + tmp = inl(addr); + udelay(1); + + return tmp; +} + +/*----------------------------------------------------------------------------*/ + +static void srom_latch (u_int command, u_long addr) +{ + sendto_srom (command, addr); + sendto_srom (command | DT_CLK, addr); + sendto_srom (command, addr); + + return; +} + +/*----------------------------------------------------------------------------*/ + +static void srom_command_rd (u_int command, u_long addr) +{ + srom_latch (command, addr); + srom_latch (command, addr); + srom_latch ((command & 0x0000ff00) | DT_CS, addr); + + return; +} + +/*----------------------------------------------------------------------------*/ + +static void srom_command_wr (u_int command, u_long addr) +{ + srom_latch (command, addr); + srom_latch ((command & 0x0000ff00) | DT_CS, addr); + srom_latch (command, addr); + + return; +} + +/*----------------------------------------------------------------------------*/ + +static void srom_address(u_int command, u_long addr, u_char offset) +{ + int i; + signed char a; + + a = (char)(offset << 2); + for (i=0; i<6; i++, a <<= 1) + { + srom_latch(command | ((a < 0) ? DT_IN : 0), addr); + } + udelay(1); + + i = (getfrom_srom(addr) >> 3) & 0x01; + + return; +} +/*----------------------------------------------------------------------------*/ + +static short srom_data_rd (u_int command, u_long addr) +{ + int i; + short word = 0; + s32 tmp; + + for (i=0; i<16; i++) + { + sendto_srom(command | DT_CLK, addr); + tmp = getfrom_srom(addr); + sendto_srom(command, addr); + + word = (word << 1) | ((tmp >> 3) & 0x01); + } + + sendto_srom(command & 0x0000ff00, addr); + + return word; +} + +/*----------------------------------------------------------------------------*/ + +static int srom_data_wr (u_int command, u_long addr, short val) +{ + int i; + u_long longVal; + s32 tmp; + + longVal = (u_long)(le16_to_cpu(val)); + + for (i=0; i<16; i++) + { + tmp = (longVal & 0x8000)>>13; + + sendto_srom (tmp | command, addr); + sendto_srom (tmp | command | DT_CLK, addr); + sendto_srom (tmp | command, addr); + + longVal = longVal<<1; + } + + sendto_srom(command & 0x0000ff00, addr); + sendto_srom(command, addr); + + tmp = 100; + do + { + if ((getfrom_srom(dc_srom_iobase) & 0x8) == 0x8) + break; + udelay(1000); + } while (--tmp); + + if (tmp == 0) + { + printf("Write DEC21143 SRom timed out !\n"); + return (-1); + } + + return 0; +} + + +/*----------------------------------------------------------------------------*/ +static short srom_rd (u_long addr, u_char offset) +{ + sendto_srom (SROM_RD | SROM_SR, addr); + srom_latch (SROM_RD | SROM_SR | DT_CS, addr); + + srom_command_rd (SROM_RD | SROM_SR | DT_IN | DT_CS, addr); + + srom_address (SROM_RD | SROM_SR | DT_CS, addr, offset); + + return srom_data_rd (SROM_RD | SROM_SR | DT_CS, addr); +} + +/*----------------------------------------------------------------------------*/ + +static void srom_wr_enable (u_long addr) +{ + int i; + + sendto_srom (SROM_WR | SROM_SR, addr); + srom_latch (SROM_WR | SROM_SR | DT_CS, addr); + + srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr); + srom_latch (SROM_WR | SROM_SR | DT_CS, addr); + srom_latch (SROM_WR | SROM_SR | DT_CS, addr); + + for (i=0; i<6; i++) + { + srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr); + } +} + +/*----------------------------------------------------------------------------*/ + +static int srom_wr (u_long addr, u_char offset, short val) +{ + srom_wr_enable (addr); + + sendto_srom (SROM_WR | SROM_SR, addr); + srom_latch (SROM_WR | SROM_SR | DT_CS, addr); + + srom_command_wr (SROM_WR | SROM_SR | DT_IN | DT_CS, addr); + + srom_address (SROM_WR | SROM_SR | DT_CS, addr, offset); + + return srom_data_wr (SROM_WR | SROM_SR | DT_CS, addr, val); +} + +/*----------------------------------------------------------------------------*/ +/* + * load data from the srom + */ +int dc_srom_load (u_short *dest) +{ + int offset; + short tmp; + + /* get srom iobase from local network controller */ + pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase); + dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK; + dc_srom_iobase = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase); + dc_srom_iobase += 0x48; /* io offset for srom access */ + + memset (dest, 0, 128); + for (offset=0; offset<64; offset++) + { + tmp = srom_rd (dc_srom_iobase, offset); + *dest++ = le16_to_cpu(tmp); + } + + return (0); +} + +/*----------------------------------------------------------------------------*/ + +/* + * store data into the srom + */ +int dc_srom_store (u_short *src) +{ + int offset; + + /* get srom iobase from local network controller */ + pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase); + dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK; + dc_srom_iobase = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase); + dc_srom_iobase += 0x48; /* io offset for srom access */ + + for (offset=0; offset<64; offset++) + { + if (srom_wr (dc_srom_iobase, offset, *src) == -1) + return (-1); + src++; + } + + return (0); +} + +/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/el_srom.c b/board/eltec/bab7xx/el_srom.c new file mode 100644 index 0000000..73f8066 --- /dev/null +++ b/board/eltec/bab7xx/el_srom.c @@ -0,0 +1,292 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "srom.h" + +/*----------------------------------------------------------------------------*/ +/* + * START sequence + * _ _________ + * SCLK _> \____ + * _ ____ + * SDIO _> \_________ + * : : : + */ +static void eepStart (void) +{ + out8(I2C_BUS_DAT, 0x60); /* SCLK = high SDIO = high */ + out8(I2C_BUS_DIR, 0x60); /* set output direction for SCLK/SDIO */ + udelay(10); + out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = low */ + udelay(10); + out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = low */ + udelay(10); +} + +/*----------------------------------------------------------------------------*/ +/* + * STOP sequence + * _______ + * SCLK _____/ + * _ ___ + * SDIO _>_______/ + * : : : + */ +static void eepStop (void) +{ + out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = low */ + out8(I2C_BUS_DIR, 0x60); /* set output direction for SCLK/SDIO */ + udelay(10); + out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = low */ + udelay(10); + out8(I2C_BUS_DAT, 0x60); /* SCLK = high SDIO = high */ + udelay(10); + out8(I2C_BUS_DIR, 0x00); /* reset to input direction */ +} + +/*----------------------------------------------------------------------------*/ +/* + * Read one byte from EEPROM + * ___ ___ ___ ___ ___ ___ ___ ___ + * SCLK ___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \ + * _________________________________________________________________ + * SDIO > ^ ^ ^ ^ ^ ^ ^ ^ + * : : : : : : : : : : : : : : : : : + */ +static unsigned char eepReadByte (void) +{ + register unsigned char buf = 0x00; + register int i; + + out8(I2C_BUS_DIR, 0x40); + + for (i = 0; i < 8; i++) + { + out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */ + udelay(10); + out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = high */ + udelay(15); + buf <<= 1; + buf = (in8(I2C_BUS_DAT) & 0x20) ? (buf | 0x01) : (buf & 0xFE); + out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */ + udelay(10); + } + return(buf); +} + +/*----------------------------------------------------------------------------*/ +/* + * Write one byte to EEPROM + * ___ ___ ___ ___ ___ ___ ___ ___ + * SCLK __/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \__ + * _______ _______ _______ _______ _______ _______ _______ ________ + * SDIO X_______X_______X_______X_______X_______X_______X_______X________ + * : 7 : 6 : 5 : 4 : 3 : 2 : 1 : 0 + */ +static void eepWriteByte (register unsigned char buf) +{ + register int i; + + (buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = data */ + out8(I2C_BUS_DIR, 0x60); + + for (i = 7; i >= 0; i--) + { + (buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low SDIO=data */ + udelay(10); + (buf & 0x80) ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK=high SDIO=data */ + udelay(15); + (buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low SDIO=data */ + udelay(10); + buf <<= 1; + } +} + +/*----------------------------------------------------------------------------*/ +/* + * Read data acknowledge of EEPROM + * _______ + * SCLK ____/ \___ + * _______________ + * SDIO > + * : : ^ : + */ +static int eepReadAck (void) +{ + int retval; + + out8(I2C_BUS_DIR, 0x40); + out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */ + udelay(10); + out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = high */ + udelay(10); + retval = (in8(I2C_BUS_DAT) & 0x20) ? ERROR : 0; + udelay(10); + out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */ + udelay(10); + + return(retval); +} + +/*----------------------------------------------------------------------------*/ +/* + * Write data acknowledge to EEPROM + * _______ + * SCLK ____/ \___ + * + * SDIO >_______________ + * : : : + */ +static void eepWriteAck (unsigned char ack) +{ + ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = ack */ + out8(I2C_BUS_DIR, 0x60); + udelay(10); + ack ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = ack */ + udelay(15); + ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = ack */ + udelay(10); +} + +/*----------------------------------------------------------------------------*/ +/* + * Read bytes from EEPROM + */ +int el_srom_load (addr, buf, cnt, device, block) +unsigned char addr; +unsigned char *buf; +int cnt; +unsigned char device; +unsigned char block; +{ + register int i; + + for (i=0;i>= 1; accu ^= f; + byte >>= 1; + } + } + return(accu); +} + +/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/flash.c b/board/eltec/bab7xx/flash.c new file mode 100644 index 0000000..442dd00 --- /dev/null +++ b/board/eltec/bab7xx/flash.c @@ -0,0 +1,512 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC). + * fixed monitor protection part + * + * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage + * of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use + * any other. + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*flash command address offsets*/ + +#define ADDR0 (0x555) +#define ADDR1 (0x2AA) +#define ADDR3 (0x001) + +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------------*/ + +unsigned long flash_init (void) +{ + unsigned long size1, size2; + int i; + + /* Init: no FLASHes known */ + for (i=0; iflash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + flash_init(); + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + case AMD_ID_F016D: + printf ("AM29F016D (16 Mbit)\n"); + break; + case AMD_ID_F032B: + printf ("AM29F032B (32 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >= (1 << 20)) { + printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + } else { + printf (" Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count); + } + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------------*/ +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong vendor, devid; + ulong base = (ulong)addr; + volatile unsigned char *caddr = (unsigned char *)addr; + +#ifdef DEBUG + printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr); +#endif + + /* Write auto select command: read Manufacturer ID */ + caddr[0] = 0xF0; /* reset bank */ + udelay(10); + + eieio(); + caddr[0x555] = 0xAA; + udelay(10); + caddr[0x2AA] = 0x55; + udelay(10); + caddr[0x555] = 0x90; + + udelay(10); + + vendor = caddr[0]; + devid = caddr[1]; + +#ifdef DEBUG + printf("Manufacturer: 0x%lx\n", vendor); +#endif + + vendor &= 0xff; + devid &= 0xff; + + /* We accept only two AMD types */ + switch (vendor) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + switch (devid) { + case (FLASH_WORD_SIZE)AMD_ID_F040B: + info->flash_id |= AMD_ID_F040B; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_F016D: + info->flash_id |= AMD_ID_F016D; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_F032B: + info->flash_id |= AMD_ID_F032B; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + +#ifdef DEBUG + printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size); +#endif + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* sector base address */ + info->start[i] = base + i * (info->size / info->sector_count); + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (volatile unsigned char *)info->start[0]; + caddr[0] = 0xF0; /* reset bank */ + } + + return (info->size); +} + +/*----------------------------------------------------------------------------*/ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + int rc = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FLASH_WORD_SIZE *)(info->start[sect]); + if (info->flash_id & FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + udelay(30000); /* wait 30 ms */ + } + else + addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return rc; +} + +/*----------------------------------------------------------------------------*/ +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------------*/ +/* Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *)dest) & + (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) + { + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/l2cache.c b/board/eltec/bab7xx/l2cache.c new file mode 100644 index 0000000..1e75377 --- /dev/null +++ b/board/eltec/bab7xx/l2cache.c @@ -0,0 +1,159 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CFG_L2_BAB7xx) + +#include +#include +#include + +/* defines L2CR register for MPC750 */ + +#define L2CR_E 0x80000000 +#define L2CR_256K 0x10000000 +#define L2CR_512K 0x20000000 +#define L2CR_1024K 0x30000000 +#define L2CR_I 0x00200000 +#define L2CR_SL 0x00008000 +#define L2CR_IP 0x00000001 + +/*----------------------------------------------------------------------------*/ + +static int dummy (int dummy) +{ + return (dummy+1); +} + +/*----------------------------------------------------------------------------*/ + +int l2_cache_enable (int l2control) +{ + if (l2control) /* BAB750 */ + { + mtspr(SPRN_L2CR, l2control); + mtspr(SPRN_L2CR, (l2control | L2CR_I)); + while (mfspr(SPRN_L2CR) & L2CR_IP) + ; + mtspr(SPRN_L2CR, (l2control | L2CR_E)); + return (0); + } + else /* BAB740 */ + { + int picr1, picr2, mask; + int picr2CacheSize, cacheSize; + int *d; + int devbusfn; + u32 reg32; + + devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA, + PCI_DEVICE_ID_MOTOROLA_MPC106, 0); + if (devbusfn == -1) + return (-1); + + pci_read_config_dword (devbusfn, PCI_PICR2, ®32); + reg32 &= ~PICR2_L2_EN; + pci_write_config_dword (devbusfn, PCI_PICR2, reg32); + + /* cache size */ + if (*(volatile unsigned char *) (CFG_ISA_IO + 0x220) & 0x04) + { + /* cache size is 512 KB */ + picr2CacheSize = PICR2_L2_SIZE_512K; + cacheSize = 0x80000; + } + else + { + /* cache size is 256 KB */ + picr2CacheSize = PICR2_L2_SIZE_256K; + cacheSize = 0x40000; + } + + /* setup PICR1 */ + mask = + ~(PICR1_CF_BREAD_WS(1) | + PICR1_CF_BREAD_WS(2) | + PICR1_CF_CBA(0xff) | + PICR1_CF_CACHE_1G | + PICR1_CF_DPARK | + PICR1_CF_APARK | + PICR1_CF_L2_CACHE_MASK); + + picr1 = + (PICR1_CF_CBA(0x3f) | + PICR1_CF_CACHE_1G | + PICR1_CF_APARK | + PICR1_CF_DPARK | + PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */ + + pci_read_config_dword (devbusfn, PCI_PICR1, ®32); + reg32 &= mask; + reg32 |= picr1; + pci_write_config_dword (devbusfn, PCI_PICR1, reg32); + + /* + * invalidate all L2 cache + */ + picr2 = + (PICR2_CF_INV_MODE | + PICR2_CF_HIT_HIGH | + PICR2_CF_MOD_HIGH | + PICR2_CF_L2_HIT_DELAY(1) | + PICR2_CF_APHASE_WS(1) | + picr2CacheSize); + + pci_write_config_dword (devbusfn, PCI_PICR2, picr2); + + /* + * dummy transactions + */ + for (d=0; d<(int *)(2*cacheSize); d++) + dummy(*d); + + pci_write_config_dword (devbusfn, PCI_PICR2, + (picr2 | PICR2_CF_FLUSH_L2)); + + /* setup PICR2 */ + picr2 = + (PICR2_CF_FAST_CASTOUT | + PICR2_CF_WDATA | + PICR2_CF_ADDR_ONLY_DISABLE | + PICR2_CF_HIT_HIGH | + PICR2_CF_MOD_HIGH | + PICR2_L2_UPDATE_EN | + PICR2_L2_EN | + PICR2_CF_APHASE_WS(1) | + PICR2_CF_DATA_RAM_PBURST | + PICR2_CF_L2_HIT_DELAY(1) | + PICR2_CF_SNOOP_WS(2) | + picr2CacheSize); + + pci_write_config_dword (devbusfn, PCI_PICR2, picr2); + } + return (0); +} + +/*----------------------------------------------------------------------------*/ + +#endif /* (CFG_L2_BAB7xx) */ diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c new file mode 100644 index 0000000..6a24807 --- /dev/null +++ b/board/eltec/bab7xx/misc.c @@ -0,0 +1,547 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* includes */ +#include +#include +#include +#include +#include +#include +#include "srom.h" + +/* imports */ +extern char console_buffer[CFG_CBSIZE]; +extern int l2_cache_enable (int l2control); +extern void *nvram_read (void *dest, const short src, size_t count); +extern void nvram_write (short dest, const void *src, size_t count); + +/* globals */ +unsigned int ata_reset_time = 60; +unsigned int scsi_reset_time = 10; +unsigned int eltec_board; + +/* BAB750 uses SYM53C875(default) and BAB740 uses SYM53C860 + * values fixed after board identification + */ +unsigned short scsi_dev_id = PCI_DEVICE_ID_NCR_53C875; +unsigned int scsi_max_scsi_id = 15; +unsigned char scsi_sym53c8xx_ccf = 0x13; + +/*----------------------------------------------------------------------------*/ +/* + * handle sroms on BAB740/750 + * fix ether address + * L2 cache initialization + * ide dma control + */ +int misc_init_r (void) +{ + revinfo eerev; + char *ptr; + u_int i, l, initSrom, copyNv; + char buf[256]; + char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, + 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 }; + pci_dev_t bdf; + + char sromSYM[] = { +#ifdef TULIP_BUG + /* 10BaseT, 100BaseTx no full duplex modes */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08, + 0x02, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00, + 0x88, 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xe8 +#endif + /* 10BaseT, 10BaseT-FD, 100BaseTx, 100BaseTx-FD */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08, + 0x04, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00, + 0x86, 0x02, 0x04, 0xaf, 0x08, 0xa5, 0x00, 0x88, + 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61, 0x80, + 0x88, 0x04, 0x05, 0x27, 0x08, 0x25, 0x00, 0x61, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x77 + }; + + char sromMII[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x5b, 0x00, + 0x2e, 0x4d, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08, + 0x01, 0x95, 0x03, 0x00, 0x00, 0x04, 0x01, 0x08, + 0x00, 0x00, 0x02, 0x08, 0x02, 0x00, 0x00, 0x78, + 0xe0, 0x01, 0x00, 0x50, 0x00, 0x18, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xde, 0x41 + }; + + /* + * Check/Remake revision info + */ + initSrom = 0; + copyNv = 0; + + /* read out current revision srom contens */ + el_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo), + SECOND_DEVICE, FIRST_BLOCK); + + /* read out current nvram shadow image */ + nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE); + + if (strcmp (eerev.magic, "ELTEC") != 0) + { + /* srom is not initialized -> create a default revision info */ + for (i = 0, ptr = (char *)&eerev; i < sizeof(revinfo); i++) + *ptr++ = 0x00; + strcpy(eerev.magic, "ELTEC"); + eerev.revrev[0] = 1; + eerev.revrev[1] = 0; + eerev.size = 0x00E0; + eerev.category[0] = 0x01; + + /* node id from dead e128 as default */ + eerev.etheraddr[0] = 0x00; + eerev.etheraddr[1] = 0x00; + eerev.etheraddr[2] = 0x5B; + eerev.etheraddr[3] = 0x00; + eerev.etheraddr[4] = 0x2E; + eerev.etheraddr[5] = 0x4D; + + /* cache config word for bab750 */ + *(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH; + + initSrom = 1; /* force dialog */ + copyNv = 1; /* copy to nvram */ + } + + if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) != + el_srom_checksum((u_char*)buf, CFG_SROM_SIZE))) + { + printf ("Invalid revision info copy in nvram !\n"); + printf ("Press key:\n to copy current revision info to nvram.\n"); + printf (" to reenter revision info.\n"); + printf ("=> "); + if (0 != readline (NULL)) + { + switch ((char)toupper(console_buffer[0])) + { + case 'C': + copyNv = 1; + break; + case 'R': + copyNv = 1; + initSrom = 1; + break; + } + } + } + + if (initSrom) + { + memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */ + printf ("Enter revision number (0-9): %c ", eerev.revision[0][0]); + if (0 != readline (NULL)) + { + eerev.revision[0][0] = (char)toupper(console_buffer[0]); + memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */ + } + + printf ("Enter revision character (A-Z): %c ", eerev.revision[0][1]); + if (1 == readline (NULL)) + { + eerev.revision[0][1] = (char)toupper(console_buffer[0]); + } + + printf ("Enter board name (V-XXXX-XXXX): %s ", (char *)&eerev.board); + if (11 == readline (NULL)) + { + for (i=0; i<11; i++) + eerev.board[i] = (char)toupper(console_buffer[i]); + eerev.board[11] = '\0'; + } + + printf ("Enter serial number: %s ", (char *)&eerev.serial ); + if (6 == readline (NULL)) + { + for (i=0; i<6; i++) + eerev.serial[i] = console_buffer[i]; + eerev.serial[6] = '\0'; + } + + printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", + eerev.etheraddr[0], eerev.etheraddr[1], + eerev.etheraddr[2], eerev.etheraddr[3], + eerev.etheraddr[4], eerev.etheraddr[5]); + if (12 == readline (NULL)) + { + for (i=0; i<12; i+=2) + eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] + + hex[toupper(console_buffer[i+1])-'0']); + } + + l = strlen ((char *)&eerev.text); + printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text ); + if (0 != readline (NULL)) + { + for (i = l; i<63; i++) + eerev.text[i] = console_buffer[i-l]; + eerev.text[63] = '\0'; + } + + if (strstr ((char *)&eerev.board, "75") != NULL) + eltec_board = 750; + else + eltec_board = 740; + + if (eltec_board == 750) + { + if (CPU_TYPE == CPU_TYPE_750) + *(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH; + else + *(int*)&eerev.res[0] = CLK2P5TO1_1MB_PB_0P5DH; + + printf("Enter L2Cache config word with leading zero (HEX): %08X ", + *(int*)&eerev.res[0] ); + if (0 != readline (NULL)) + { + for (i=0; i<7; i+=2) + { + eerev.res[i>>1] = + (char)(16*hex[toupper(console_buffer[i])-'0'] + + hex[toupper(console_buffer[i+1])-'0']); + } + } + + /* prepare network eeprom */ + sromMII[20] = eerev.etheraddr[0]; + sromMII[21] = eerev.etheraddr[1]; + sromMII[22] = eerev.etheraddr[2]; + sromMII[23] = eerev.etheraddr[3]; + sromMII[24] = eerev.etheraddr[4]; + sromMII[25] = eerev.etheraddr[5]; + printf("\nSRom: Writing DEC21143 MII info .. "); + + if (dc_srom_store ((u_short *)sromMII) == -1) + printf("FAILED\n"); + else + printf("OK\n"); + } + + if (eltec_board == 740) + { + *(int *)&eerev.res[0] = 0; + sromSYM[20] = eerev.etheraddr[0]; + sromSYM[21] = eerev.etheraddr[1]; + sromSYM[22] = eerev.etheraddr[2]; + sromSYM[23] = eerev.etheraddr[3]; + sromSYM[24] = eerev.etheraddr[4]; + sromSYM[25] = eerev.etheraddr[5]; + printf("\nSRom: Writing DEC21143 SYM info .. "); + + if (dc_srom_store ((u_short *)sromSYM) == -1) + printf("FAILED\n"); + else + printf("OK\n"); + } + + /* update CRC */ + eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size); + + /* write new values */ + printf("\nSRom: Writing revision info ...... "); + if (el_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev, + sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1) + printf("FAILED\n\n"); + else + printf("OK\n\n"); + + /* write new values as shadow image to nvram */ + nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE); + + } /*if (initSrom) */ + + /* copy current values as shadow image to nvram */ + if (initSrom == 0 && copyNv == 1) + nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE); + + /* update environment */ + sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", + eerev.etheraddr[0], eerev.etheraddr[1], + eerev.etheraddr[2], eerev.etheraddr[3], + eerev.etheraddr[4], eerev.etheraddr[5]); + setenv ("ethaddr", buf); + + /* print actual board identification */ + printf("Ident: %s Ser %s Rev %c%c\n", + eerev.board, (char *)&eerev.serial, + eerev.revision[0][0], eerev.revision[0][1]); + + /* global board ident */ + if (strstr ((char *)&eerev.board, "75") != NULL) + eltec_board = 750; + else + eltec_board = 740; + + /* + * L2 cache configuration + */ +#if defined(CFG_L2_BAB7xx) + ptr = getenv("l2cache"); + if (*ptr == '0') + { + printf ("Cache: L2 NOT activated on BAB%d\n", eltec_board); + } + else + { + printf ("Cache: L2 activated on BAB%d\n", eltec_board); + l2_cache_enable(*(int*)&eerev.res[0]); + } +#endif + + /* + * Reconfig ata reset timeout from environment + */ + if ((ptr = getenv ("ata_reset_time")) != NULL) + { + ata_reset_time = (int)simple_strtoul (ptr, NULL, 10); + } + else + { + sprintf (buf, "%d", ata_reset_time); + setenv ("ata_reset_time", buf); + } + + /* + * Reconfig scsi reset timeout from environment + */ + if ((ptr = getenv ("scsi_reset_time")) != NULL) + { + scsi_reset_time = (int)simple_strtoul (ptr, NULL, 10); + } + else + { + sprintf (buf, "%d", scsi_reset_time); + setenv ("scsi_reset_time", buf); + } + + + if ((bdf = pci_find_device(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, 0)) > 0) + { + if (pci_find_device(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, 0) > 0) + { + /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 Mhz */ + scsi_dev_id = PCI_DEVICE_ID_NCR_53C860; + scsi_max_scsi_id = 7; + scsi_sym53c8xx_ccf = 0x15; + pci_write_config_byte (bdf, WINBOND_IDEIRCR, 0xb0); + } + + if ((ptr = getenv ("ide_dma_off")) != NULL) + { + u_long dma_off = simple_strtoul (ptr, NULL, 10); + /* + * setup user defined registers + * s.a. linux/drivers/ide/sl82c105.c + */ + bdf |= PCI_BDF(0,0,1); /* ide user reg at bdf function 1 */ + if (dma_off & 1) + { + pci_write_config_byte (bdf, 0x46, 1); + printf("IDE: DMA off flag set: Bus 0 : Dev 0\n"); + } + if (dma_off & 2) + { + pci_write_config_byte (bdf, 0x4a, 1); + printf("IDE: DMA off flag set: Bus 0 : Dev 1\n"); + } + if (dma_off & 4) + { + pci_write_config_byte (bdf, 0x4e, 1); + printf("IDE: DMA off flag set: Bus 1 : Dev 0\n"); + } + if (dma_off & 8) + { + pci_write_config_byte (bdf, 0x52, 1); + printf("IDE: DMA off flag set: Bus 1 : Dev 1\n"); + } + } + } + return (0); +} + +/*----------------------------------------------------------------------------*/ +/* + * BAB740 uses KENDIN KS8761 modem chip with not common setup values + */ +#ifdef CONFIG_TULIP_SELECT_MEDIA + +/* Register bits. + */ +#define BMR_SWR 0x00000001 /* Software Reset */ +#define STS_TS 0x00700000 /* Transmit Process State */ +#define STS_RS 0x000e0000 /* Receive Process State */ +#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ +#define OMR_SR 0x00000002 /* Start/Stop Receive */ +#define OMR_PS 0x00040000 /* Port Select */ +#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ +#define OMR_PM 0x00000080 /* Pass All Multicast */ +#define OMR_PR 0x00000040 /* Promiscuous Mode */ +#define OMR_PCS 0x00800000 /* PCS Function */ +#define OMR_TTM 0x00400000 /* Transmit Threshold Mode */ + +/* Ethernet chip registers. + */ +#define DE4X5_BMR 0x000 /* Bus Mode Register */ +#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ +#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ +#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ +#define DE4X5_STS 0x028 /* Status Register */ +#define DE4X5_OMR 0x030 /* Operation Mode Register */ +#define DE4X5_SISR 0x060 /* SIA Status Register */ +#define DE4X5_SICR 0x068 /* SIA Connectivity Register */ +#define DE4X5_TXRX 0x070 /* SIA Transmit and Receive Register */ +#define DE4X5_GPPR 0x078 /* General Purpose Port register */ +#define DE4X5_APROM 0x048 /* Ethernet Address PROM */ + +/*----------------------------------------------------------------------------*/ + +static int INL(struct eth_device* dev, u_long addr) +{ + return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); +} + +/*----------------------------------------------------------------------------*/ + +static void OUTL(struct eth_device* dev, int command, u_long addr) +{ + *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); +} + +/*----------------------------------------------------------------------------*/ + +static void media_reg_init ( + struct eth_device* dev, + u32 csr14, + u32 csr15_dir, + u32 csr15_v0, + u32 csr15_v1, + u32 csr6 ) +{ + OUTL(dev, 0, DE4X5_OMR); /* CSR6 */ + udelay(10 * 1000); + OUTL(dev, 0, DE4X5_SICR); /* CSR13 */ + OUTL(dev, 1, DE4X5_SICR); /* CSR13 */ + udelay(10 * 1000); + OUTL(dev, csr14, DE4X5_TXRX); /* CSR14 */ + OUTL(dev, csr15_dir, DE4X5_GPPR); /* CSR15 */ + OUTL(dev, csr15_v0, DE4X5_GPPR); /* CSR15 */ + udelay(10 * 1000); + OUTL(dev, csr15_v1, DE4X5_GPPR); /* CSR15 */ + OUTL(dev, 0x00000301, DE4X5_SISR); /* CSR12 */ + OUTL(dev, csr6, DE4X5_OMR); /* CSR6 */ +} + +/*----------------------------------------------------------------------------*/ + +void dc21x4x_select_media(struct eth_device* dev) +{ + int i, status, ext; + extern unsigned int eltec_board; + + if (eltec_board == 740) + { + printf("SYM media select "); /* BAB740 */ + /* start autoneg. with 10 mbit */ + media_reg_init (dev, 0x3ffff, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400080); + ext = status = 0; + for (i=0; i<2000+ext; i++) + { + status = INL(dev, DE4X5_SISR); + udelay(1000); + if (status & 0x2000) ext = 2000; + if ((status & 0x7000) == 0x5000) break; + } + + /* autoneg. ok -> 100MB FD */ + if ((status & 0x0100f000) == 0x0100d000) + { + media_reg_init (dev, 0x37f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40280); + printf("100baseTx-FD\n"); + } + /* autoneg. ok -> 100MB HD */ + else if ((status & 0x0080f000) == 0x0080d000) + { + media_reg_init (dev, 0x17f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40080); + printf("100baseTx\n"); + } + /* autoneg. ok -> 10MB FD */ + else if ((status & 0x0040f000) == 0x0040d000) + { + media_reg_init (dev, 0x07f7f, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400280); + printf("10baseT-FD\n"); + } + /* autoneg. fail -> 10MB HD */ + else + { + media_reg_init (dev, 0x7f7f, 0x08af0008, 0x00a10008, 0x00a50008, + (OMR_SDP | OMR_TTM | OMR_PM)); + printf("10baseT\n"); + } + } + else + { + printf("MII media selected\n"); /* BAB750 */ + OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); /* CSR6 */ + } +} +#endif /* CONFIG_TULIP_SELECT_MEDIA */ + +/*---------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/pci.c b/board/eltec/bab7xx/pci.c new file mode 100644 index 0000000..edbd3dd --- /dev/null +++ b/board/eltec/bab7xx/pci.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI initialisation for the MPC10x. + */ + +#include +#include +#include + +#ifdef CONFIG_PCI + +struct pci_controller local_hose; + +void pci_init_board(void) +{ + struct pci_controller* hose = (struct pci_controller *)&local_hose; + u32 reg32; + u16 reg16; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + /* + * Attention: pci_hose_phys_to_bus() failes in address compare, + * so we need (CFG_PCI_MEMORY_SIZE-1) + */ + CFG_PCI_MEMORY_SIZE-1, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI_MEM_BUS, + CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 2, + CFG_ISA_MEM_BUS, + CFG_ISA_MEM_PHYS, + CFG_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 3, + CFG_PCI_IO_BUS, + CFG_PCI_IO_PHYS, + CFG_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 4, + CFG_ISA_IO_BUS, + CFG_ISA_IO_PHYS, + CFG_ISA_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 5; + + pci_setup_indirect(hose, + MPC106_REG_ADDR, + MPC106_REG_DATA); + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); + + /* Initialises the MPC10x PCI Configuration regs. */ + pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, ®32); + reg32 |= PICR2_CF_SNOOP_WS(3) | + PICR2_CF_FLUSH_L2 | + PICR2_CF_L2_HIT_DELAY(3) | + PICR2_CF_APHASE_WS(3); + reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN); + pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32); + + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + + /* Clear non-reserved bits in status register */ + pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + + pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, ®32); + reg32 |= PICR1_CF_CBA(63) | + PICR1_CF_BREAD_WS(2) | + PICR1_MCP_EN | + PICR1_CF_DPARK | + PICR1_PROC_TYPE_604 | + PICR1_CF_LOOP_SNOOP | + PICR1_CF_APARK; + pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32); +} + +#endif /* CONFIG_PCI */ diff --git a/board/eltec/bab7xx/srom.h b/board/eltec/bab7xx/srom.h new file mode 100644 index 0000000..c18ab91 --- /dev/null +++ b/board/eltec/bab7xx/srom.h @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* common srom defs */ +#define FIRST_DEVICE 0x00 +#define SECOND_DEVICE 0x04 +#define FIRST_BLOCK 0x00 +#define SECOND_BLOCK 0x02 +#define BLOCK_SIZE 0x100 +#define ERROR (-1) + +#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100 +#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100 + +#define CPU_TYPE_740 0x08 +#define CPU_TYPE_750 0x08 +#define CPU_TYPE ((get_pvr()>>16)&0xffff) + +#define ABS(x) ((x<0)?-x:x) +#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8) + +/* bab7xx ELTEC srom */ +#define I2C_BUS_DAT (CFG_ISA_IO + 0x220) +#define I2C_BUS_DIR (CFG_ISA_IO + 0x221) + +/* srom at mpc107 */ +#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */ +#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */ +#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */ +#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */ +#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */ +#define MPC107_I2C_TIMEOUT 10000000 + +/* i82559 */ +#define EE_ADDR_BITS 6 +#define EE_SIZE 0x40 /* 0x40 words */ +#define EE_CHECKSUM 0xBABA + +/* dc21143 */ +#define DEC_SROM_SIZE 128 + + +/* + * structure of revision srom + */ +typedef struct { + char magic[8]; /* 000 - Magic number */ + char revrev[2]; /* 008 - Revision of structure */ + unsigned short size; /* 00A - Size of CRC area */ + unsigned long crc; /* 00C - CRC */ + char board[16]; /* 010 - Board Revision information */ + char option[4][16]; /* 020 - Option Revision information */ + char serial[8]; /* 060 - Board serial number */ + char etheraddr[6]; /* 068 - Ethernet node addresse */ + char reserved[2]; /* 06E - Reserved */ + char revision[7][2]; /* 070 - Revision codes */ + char category[2]; /* 07E - Category codes */ + char text[64]; /* 080 - Text field */ + char res[64]; /* 0C0 - Reserved */ +} revinfo; + +unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size); +int el_srom_load (unsigned char addr, unsigned char *buf, int cnt, + unsigned char device, unsigned char block); +int el_srom_store (unsigned char addr, unsigned char *buf, int cnt, + unsigned char device, unsigned char block); + +int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider); +int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset); +int mpc107_i2c_write_byte (unsigned char device, unsigned char block, + unsigned char offset, unsigned char val); +int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt, + unsigned char device, unsigned char block); +int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt, + unsigned char device, unsigned char block); + +int dc_srom_load (unsigned short *dest); +int dc_srom_store (unsigned short *src); + +unsigned short eepro100_srom_checksum (unsigned short *sromdata); +void eepro100_srom_load (unsigned short *destination); +int eepro100_srom_store (unsigned short *source); diff --git a/board/eltec/bab7xx/u-boot.lds b/board/eltec/bab7xx/u-boot.lds new file mode 100644 index 0000000..d89eb6c --- /dev/null +++ b/board/eltec/bab7xx/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile new file mode 100644 index 0000000..76b2cfe --- /dev/null +++ b/board/eltec/elppc/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o + +SOBJS = asm_init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S new file mode 100644 index 0000000..1b8d399 --- /dev/null +++ b/board/eltec/elppc/asm_init.S @@ -0,0 +1,878 @@ +/* + * (C) Copyright 2001 ELTEC Elektronik AG + * Frank Gottschling + * + * ELTEC ELPPC RAM initialization + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include +#include + +.globl board_asm_init +board_asm_init: + +/* + * setup pointer to message block + */ + mflr r13 /* save away link register */ + bl get_lnk_reg /* r3=addr of next instruction */ + subi r4, r3, 8 /* r4=board_asm_init addr */ + addi r29, r4, (MessageBlock-board_asm_init) + +/* + * dcache_disable + */ + mfspr r3, HID0 + li r4, HID0_DCE + andc r3, r3, r4 + mr r2, r3 + ori r3, r3, HID0_DCI + sync + mtspr HID0, r3 + mtspr HID0, r2 + isync + sync +/* + * icache_disable + */ + mfspr r3, HID0 + li r4, 0 + ori r4, r4, HID0_ICE + andc r3, r3, r4 + sync + mtspr HID0, r3 +/* + * invalidate caches + */ + ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE) + or r4, r4, r3 + isync + mtspr HID0, r4 + andc r4, r4, r3 + isync + mtspr HID0, r4 + isync +/* + * icache_enable + */ + mfspr r3, HID0 + ori r3, r3, (HID0_ICE | HID0_ICFI) + sync + mtspr HID0, r3 + + +/* + * setup memory controller + */ + lis r1, MPC106_REG_ADDR@h + ori r1, r1, MPC106_REG_ADDR@l + lis r2, MPC106_REG_DATA@h + ori r2, r2, MPC106_REG_DATA@l + + /* Configure PICR1 */ + lis r3, MPC106_REG@h + ori r3, r3, PCI_PICR1 + stwbrx r3, 0, r1 + addis r3, r0, 0xFF14 + ori r3, r3, 0x1CC8 + eieio + stwbrx r3, 0, r2 + + /* Configure PICR2 */ + lis r3, MPC106_REG@h + ori r3, r3, PCI_PICR2 + stwbrx r3, 0, r1 + addis r3, r0, 0x0000 + ori r3, r3, 0x0000 + eieio + stwbrx r3, 0, r2 + + /* Configure EUMBAR */ + lis r3, MPC106_REG@h + ori r3, r3, 0x0078 /* offest of EUMBAR in PCI config space */ + stwbrx r3, 0, r1 + lis r3, MPC107_EUMB_ADDR@h + eieio + stwbrx r3, 0, r2 + + /* Configure Address Map B Option Reg */ + lis r3, MPC106_REG@h + ori r3, r3, 0x00e0 /* offest of AMBOR in PCI config space */ + stwbrx r3, 0, r1 + lis r3, 0 + eieio + stwbrx r3, 0, r2 + + /* Configure I2C Controller */ + lis r14, MPC107_I2C_ADDR@h /* base of I2C controller */ + ori r14, r14, MPC107_I2C_ADDR@l + lis r3, 0x2b10 /* I2C clock = 100MHz/1024 */ + stw r3, 4(r14) + li r3, 0 /* clear arbitration */ + eieio + stw r3, 12(r14) + + /* Configure MCCR1 */ + lis r3, MPC106_REG@h + ori r3, r3, MPC106_MCCR1 + stwbrx r3, 0, r1 + addis r3, r0, 0x0660 /* don't set MEMGO now ! */ + ori r3, r3, 0x0000 + eieio + stwbrx r3, 0, r2 + + /* Configure MCCR2 */ + lis r3, MPC106_REG@h + ori r3, r3, MPC106_MCCR2 + stwbrx r3, 0, r1 + addis r3, r0, 0x0400 + ori r3, r3, 0x1800 + eieio + stwbrx r3, 0, r2 + + + /* Configure MCCR3 */ + lis r3, MPC106_REG@h + ori r3, r3, MPC106_MCCR3 + stwbrx r3, 0, r1 + addis r3, r0, 0x0230 + ori r3, r3, 0x0000 + eieio + stwbrx r3, 0, r2 + + /* Configure MCCR4 */ + lis r3, MPC106_REG@h + ori r3, r3, MPC106_MCCR4 + stwbrx r3, 0, r1 + addis r3, r0, 0x2532 + ori r3, r3, 0x2220 + eieio + stwbrx r3, 0, r2 + +/* + * configure memory interface (MICRs) + */ + addis r3, r0, 0x8000 /* ADDR_80 */ + ori r3, r3, 0x0080 /* SMEMADD1 */ + stwbrx r3, 0, r1 + addis r3, r0, 0xFFFF + ori r3, r3, 0x4000 + eieio + stwbrx r3, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_84 */ + ori r3, r3, 0x0084 /* SMEMADD2 */ + stwbrx r3, 0, r1 + addis r3, r0, 0xFFFF + ori r3, r3, 0xFFFF + eieio + stwbrx r3, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_88 */ + ori r3, r3, 0x0088 /* EXTSMEM1 */ + stwbrx r3, 0, r1 + addis r3, r0, 0x0303 + ori r3, r3, 0x0000 + eieio + stwbrx r3, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_8C */ + ori r3, r3, 0x008c /* EXTSMEM2 */ + stwbrx r3, 0, r1 + addis r3, r0, 0x0303 + ori r3, r3, 0x0303 + eieio + stwbrx r3, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_90 */ + ori r3, r3, 0x0090 /* EMEMADD1 */ + stwbrx r3, 0, r1 + addis r3, r0, 0xFFFF + ori r3, r3, 0x7F3F + eieio + stwbrx r3, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_94 */ + ori r3, r3, 0x0094 /* EMEMADD2 */ + stwbrx r3, 0, r1 + addis r3, r0, 0xFFFF + ori r3, r3, 0xFFFF + eieio + stwbrx r3, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_98 */ + ori r3, r3, 0x0098 /* EXTEMEM1 */ + stwbrx r3, 0, r1 + addis r3, r0, 0x0303 + ori r3, r3, 0x0000 + eieio + stwbrx r3, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_9C */ + ori r3, r3, 0x009c /* EXTEMEM2 */ + stwbrx r3, 0, r1 + addis r3, r0, 0x0303 + ori r3, r3, 0x0303 + eieio + stwbrx r3, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_A0 */ + ori r3, r3, 0x00a0 /* MEMBNKEN */ + stwbrx r3, 0, r1 + addis r3, r0, 0x0000 + ori r3, r3, 0x0003 + eieio + stwbrx r3, 0, r2 + +/* + * must wait at least 100us after HRESET to issue a MEMGO + */ + lis r0, 1 + mtctr r0 +memStartWait: + bdnz memStartWait + +/* + * enable RAM Operations through MCCR1 (MEMGO) + */ + lis r3, 0x8000 + ori r3, r3, 0x00f0 + stwbrx r3, r0, r1 + sync + lwbrx r3, 0, r2 + lis r0, 0x0008 + or r3, r0, r3 + stwbrx r3, 0, r2 + sync + +/* + * set LEDs first time + */ + li r3, 0x1 + lis r30, CFG_USR_LED_BASE@h + stb r3, 2(r30) + sync + +/* + * init COM1 for polled output + */ + lis r8, CFG_NS16550_COM1@h /* COM1 base address*/ + ori r8, r8, CFG_NS16550_COM1@l + li r9, 0x00 + stb r9, 1(r8) /* int disabled */ + eieio + li r9, 0x00 + stb r9, 4(r8) /* modem ctrl */ + eieio + li r9, 0x80 + stb r9, 3(r8) /* link ctrl */ + eieio + li r9, (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) + stb r9, 0(r8) /* baud rate (LSB)*/ + eieio + li r9, ((CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8) + stb r9, 1(r8) /* baud rate (MSB) */ + eieio + li r9, 0x07 + stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ + eieio + li r9, 0x0b + stb r9, 4(r8) /* enable the receiver and transmitter (modem ctrl) */ + eieio +waitEmpty: + lbz r9, 5(r8) /* transmit empty */ + andi. r9, r9, 0x40 + beq waitEmpty + li r9, 0x47 + stb r9, 3(r8) /* send break, 8 data bits, 2 stop bit, no parity */ + eieio + + lis r0, 0x0001 + mtctr r0 +waitCOM1: + lwz r0, 5(r8) /* load from port for delay */ + bdnz waitCOM1 + +waitEmpty1: + lbz r9, 5(r8) /* transmit empty */ + andi. r9, r9, 0x40 + beq waitEmpty1 + li r9, 0x07 + stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ + eieio + +/* + * intro message from message block + */ + addi r3, r29, (MnewLine-MessageBlock) + bl Printf + addi r3, r29, (MinitLogo-MessageBlock) + bl Printf + +/* + * memory cofiguration using SPD information stored on the SODIMMs + */ + addi r3, r29, (Mspd01-MessageBlock) + bl Printf + + li r17, 0 + + li r3, 0x0002 /* get RAM type from spd for bank0/1 */ + bl spdRead + + cmpi 0, 0, r3, -1 /* error ? */ + bne noSpdError + + addi r3, r29, (Mfail-MessageBlock) + bl Printf + + li r6, 0xe /* error codes in r6 and r7 */ + li r7, 0x0 + b toggleError /* fail - loop forever */ + +noSpdError: + mr r15, r3 /* save r3 */ + + addi r3, r29, (Mok-MessageBlock) + bl Printf + + cmpli 0, 0, r15, 0x0004 /* SDRAM ? */ + beq isSDRAM + + addi r3, r29, (MramTyp-MessageBlock) + bl Printf + + li r6, 0xd /* error codes in r6 and r7 */ + li r7, 0x0 + b toggleError /* fail - loop forever */ + +isSDRAM: + li r3, 0x0012 /* get supported CAS latencies from byte 18 */ + bl spdRead + mr r15, r3 + li r3, 0x09 + andi. r0, r15, 0x04 + bne maxCLis3 + li r3, 0x17 +maxCLis3: + andi. r0, r15, 0x02 + bne CL2 + + addi r3, r29, (MramTyp-MessageBlock) + bl Printf + + li r6, 0xc /* error codes in r6 and r7 */ + li r7, 0x0 + b toggleError /* fail - loop forever */ +CL2: + bl spdRead + cmpli 0, 0, r3, 0xa1 /* cycle time must be 10ns max. */ + blt speedOk + + addi r3, r29, (MramTyp-MessageBlock) + bl Printf + + li r6, 0xb /* error codes in r6 and r7 */ + li r7, 0x0 + b toggleError /* fail - loop forever */ +speedOk: + lis r20, 0x06e8 /* preset MCR1 value */ + + li r3, 0x0011 /* get number of internal banks from spd for bank0/1 */ + bl spdRead + + cmpli 0, 0, r3, 0x02 + beq SD_2B + cmpli 0, 0, r3, 0x04 + beq SD_4B +memConfErr: + addi r3, r29, (MramConfErr-MessageBlock) + bl Printf + + li r6, 0xa /* error codes in r6 and r7 */ + li r7, 0x0 + b toggleError /* fail - loop forever */ + +SD_2B: + li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ + bl spdRead + cmpli 0, 0, r3, 0x0b + beq row11x2 + cmpli 0, 0, r3, 0x0c + beq row12x2or13x2 + cmpli 0, 0, r3, 0x0d + beq row12x2or13x2 + b memConfErr +SD_4B: + li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ + bl spdRead + cmpli 0, 0, r3, 0x0b + beq row11x4or12x4 + cmpli 0, 0, r3, 0x0c + beq row11x4or12x4 + cmpli 0, 0, r3, 0x0d + beq row13x4 + b memConfErr +row12x2or13x2: + ori r20, r20, 0x05 + b row11x4or12x4 +row13x4: + ori r20, r20, 0x0a + b row11x4or12x4 +row11x2: + ori r20, r20, 0x0f +row11x4or12x4: + /* get the size of bank 0-1 */ + + li r3, 0x001f /* get bank size from spd for bank0/1 */ + bl spdRead + + rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte (128 MB max.) */ + + li r3, 0x0005 /* get number of banks from spd for bank0/1 */ + bl spdRead + + cmpi 0, 0, r3, 2 /* 2 banks ? */ + bne SDRAMnobank1 + + mr r17, r16 + +SDRAMnobank1: + li r3, 0x000c /* get refresh from spd for bank0/1 */ + bl spdRead + andi. r3, r3, 0x007f /* mask selfrefresh bit */ + li r4, 0x1800 /* refesh cycle 1536 clocks left shifted 2 */ + cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */ + beq writeRefresh + + li r4, 0x0c00 /* refesh cycle 768 clocks left shifted 2 */ + cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */ + beq writeRefresh + + li r4, 0x3000 /* refesh cycle 3072 clocks left shifted 2 */ + cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */ + beq writeRefresh + + li r4, 0x6000 /* refesh cycle 6144 clocks left shifted 2 */ + cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */ + beq writeRefresh + + li r4, 0 + ori r4, r4, 0xc000 /* refesh cycle 8224 clocks left shifted 2 */ + cmpli 0, 0, r3, 0x0005 /* 125 us ? */ + beq writeRefresh + + b memConfErr + +writeRefresh: + lis r21, 0x0400 /* preset MCCR2 value */ + or r21, r21, r4 + + /* Overwrite MCCR1 */ + lis r3, MPC106_REG@h + ori r3, r3, MPC106_MCCR1 + stwbrx r3, 0, r1 + eieio + stwbrx r20, 0, r2 + + /* Overwrite MCCR2 */ + lis r3, MPC106_REG@h + ori r3, r3, MPC106_MCCR2 + stwbrx r3, 0, r1 + eieio + stwbrx r21, 0, r2 + + /* set the memory boundary registers for bank 0-3 */ + li r20, 0 + lis r23, 0x0303 + lis r24, 0x0303 + subi r21, r16, 1 /* calculate end address bank0 */ + li r22, 1 + + cmpi 0, 0, r17, 0 /* bank1 present ? */ + beq nobank1 + + andi. r3, r16, 0x00ff /* calculate start address of bank1 */ + andi. r4, r16, 0x0300 + rlwinm r3, r3, 8, 16, 23 + or r20, r20, r3 + or r23, r23, r4 + + add r16, r16, r17 /* add to total memory size */ + + subi r3, r16, 1 /* calculate end address of bank1 */ + andi. r4, r3, 0x0300 + andi. r3, r3, 0x00ff + rlwinm r3, r3, 8, 16, 23 + or r21, r21, r3 + or r24, r24, r4 + + ori r22, r22, 2 /* enable bank1 */ + b bankOk +nobank1: + ori r23, r23, 0x0300 /* set bank1 start to unused area */ + ori r24, r24, 0x0300 /* set bank1 end to unused area */ +bankOk: + addi r3, r29, (Mactivate-MessageBlock) + bl Printf + mr r3, r16 + bl OutDec + addi r3, r29, (Mact0123e-MessageBlock) + bl Printf + +/* + * overwrite MSAR1, MEAR1, EMSAR1, and EMEAR1 + */ + addis r3, r0, 0x8000 /* ADDR_80 */ + ori r3, r3, 0x0080 /* MSAR1 */ + stwbrx r3, 0, r1 + eieio + stwbrx r20, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_88 */ + ori r3, r3, 0x0088 /* EMSAR1 */ + stwbrx r3, 0, r1 + eieio + stwbrx r23, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_90 */ + ori r3, r3, 0x0090 /* MEAR1 */ + stwbrx r3, 0, r1 + eieio + stwbrx r21, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_98 */ + ori r3, r3, 0x0098 /* EMEAR1 */ + stwbrx r3, 0, r1 + eieio + stwbrx r24, 0, r2 + + addis r3, r0, 0x8000 /* ADDR_A0 */ + ori r3, r3, 0x00a0 /* MBER */ + stwbrx r3, 0, r1 + eieio + stwbrx r22, 0, r2 + +/* + * delay to let SDRAM go through several initialization/refresh cycles + */ + lis r3, 3 + mtctr r3 +memStartWait_1: + bdnz memStartWait_1 + eieio + +/* + * set LEDs end + */ + li r3, 0xf + lis r30, CFG_USR_LED_BASE@h + stb r3, 2(r30) + sync + + mtlr r13 + blr /* EXIT board_asm_init ... */ + +/*----------------------------------------------------------------------------*/ +/* + * print a message to COM1 in polling mode (r10=COM1 port, r3=(char*)string) + */ + +Printf: + lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ + ori r10, r10, CFG_NS16550_COM1@l +WaitChr: + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, WaitChr /* wait till empty */ + lbzx r0, r0, r3 /* get char */ + stb r0, 0(r10) /* write to transmit reg */ + eieio + addi r3, r3, 1 /* next char */ + lbzx r0, r0, r3 /* get char */ + cmpwi cr1, r0, 0 /* end of string ? */ + bne cr1, WaitChr + blr + +/* + * print a char to COM1 in polling mode (r10=COM1 port, r3=char) + */ +OutChr: + lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ + ori r10, r10, CFG_NS16550_COM1@l +OutChr1: + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutChr1 /* wait till empty */ + stb r3, 0(r10) /* write to transmit reg */ + eieio + blr + +/* + * print 8/4/2 digits hex value to COM1 in polling mode (r10=COM1 port, r3=val) + */ +OutHex2: + li r9, 4 /* shift reg for 2 digits */ + b OHstart +OutHex4: + li r9, 12 /* shift reg for 4 digits */ + b OHstart +OutHex: + li r9, 28 /* shift reg for 8 digits */ +OHstart: + lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ + ori r10, r10, CFG_NS16550_COM1@l +OutDig: + lbz r0, 0(r29) /* slow down dummy read */ + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutDig + sraw r0, r3, r9 + clrlwi r0, r0, 28 + cmpwi cr1, r0, 9 + ble cr1, digIsNum + addic r0, r0, 55 + b nextDig +digIsNum: + addic r0, r0, 48 +nextDig: + stb r0, 0(r10) /* write to transmit reg */ + eieio + addic. r9, r9, -4 + bge OutDig + blr + +/* + * print 3 digits hdec value to COM1 in polling mode + * (r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch) + */ +OutDec: + li r6, 10 + divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */ + mullw r10, r0, r6 + subf r9, r10, r3 + mr r3, r0 + divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */ + mullw r10, r0, r6 + subf r8, r10, r3 + mr r3, r0 + divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */ + mullw r10, r0, r6 + subf r7, r10, r3 + lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ + ori r10, r10, CFG_NS16550_COM1@l + or. r7, r7, r7 + bne noblank1 + li r3, 0x20 + b OutDec4 +noblank1: + addi r3, r7, 48 /* convert to ASCII */ +OutDec4: + lbz r0, 0(r29) /* slow down dummy read */ + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutDec4 + stb r3, 0(r10) /* x00 to transmit */ + eieio + or. r7, r7, r8 + beq OutDec5 + addi r3, r8, 48 /* convert to ASCII */ +OutDec5: + lbz r0, 0(r29) /* slow down dummy read */ + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutDec5 + stb r3, 0(r10) /* x0 to transmit */ + eieio + addi r3, r9, 48 /* convert to ASCII */ +OutDec6: + lbz r0, 0(r29) /* slow down dummy read */ + lbz r0, 5(r10) /* read link status */ + eieio + andi. r0, r0, 0x40 /* mask transmitter empty bit */ + beq cr0, OutDec6 + stb r3, 0(r10) /* x to transmit */ + eieio + blr + +/* + * hang endless loop + */ +toggleError: /* fail type in r6, r7=0xff, toggle LEDs */ + stb r7, 2(r30) /* r7 to LED */ + li r0, 0 + lis r9, 127 + ori r9, r9, 65535 +toggleError1: + addic r0, r0, 1 + cmpw cr1, r0, r9 + ble cr1, toggleError1 + stb r6, 2(r30) /* r6 to LED */ + li r0, 0 + lis r9, 127 + ori r9, r9, 65535 +toggleError2: + addic r0, r0, 1 + cmpw cr1, r0, r9 + ble cr1, toggleError2 + b toggleError + +/* + * routines to read from ram spd + */ +spdWaitIdle: + lis r0, 0x1 /* timeout for about 100us */ + mtctr r0 +iSpd: + lbz r10, 12(r14) + andi. r10, r10, 0x20 /* mask and test MBB */ + beq idle + bdnz iSpd + orc. r10, r0, r0 /* return -1 to caller */ +idle: + bclr 20, 0 /* return to caller */ + +waitSpd: + lis r0, 0x10 /* timeout for about 1.5ms */ + mtctr r0 +wSpd: + lbz r10, 12(r14) + andi. r10, r10, 0x82 + cmpli 0, 0, r10, 0x82 /* test MCF and MIF set */ + beq wend + bdnz wSpd + orc. r10, r0, r0 /* return -1 to caller */ + bclr 20, 0 /* return to caller */ + +wend: + li r10, 0 + stb r10, 12(r14) /* clear status */ + bclr 20, 0 /* return to caller */ + +/* + * spdread + * in: r3 adr to read + * out: r3 val or -1 for error + * uses r10, assumes that r14 points to I2C controller + */ +spdRead: + mfspr r25, 8 /* save link register */ + + bl spdWaitIdle + bne spdErr + + li r10, 0x80 /* start with MEN */ + stb r10, 8(r14) + eieio + + li r10, 0xb0 /* start as master */ + stb r10, 8(r14) + eieio + + li r10, 0xa0 /* write device 0xA0 */ + stb r10, 16(r14) + eieio + bl waitSpd + bne spdErr + + lbz r10, 12(r14) /* test ACK */ + andi. r10, r10, 0x01 + bne gotNoAck + + stb r3, 16(r14) /* data address */ + eieio + bl waitSpd + bne spdErr + + + li r10, 0xb4 /* switch to read - restart */ + stb r10, 8(r14) + eieio + + li r10, 0xa1 /* read device 0xA0 */ + stb r10, 16(r14) + eieio + bl waitSpd + bne spdErr + + li r10, 0xa8 /* no ACK */ + stb r10, 8(r14) + eieio + + lbz r10, 16(r14) /* trigger read next byte */ + eieio + bl waitSpd + bne spdErr + + li r10, 0x88 /* generate STOP condition */ + stb r10, 8(r14) + eieio + + lbz r3, 16(r14) /* return read byte */ + + mtspr 8, r25 /* restore link register */ + blr + +gotNoAck: + li r10, 0x80 /* generate STOP condition */ + stb r10, 8(r14) + eieio +spdErr: + orc r3, r0, r0 /* return -1 */ + mtspr 8, r25 /* restore link register */ + blr + +get_lnk_reg: + mflr r3 /* return link reg */ + blr + +MessageBlock: + +MinitLogo: + .ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012" + .ascii "\015\012Initialising RAM\015\012\000" +Mspd01: + .ascii " Reading SPD of SODIMM ...... \000" +MramTyp: + .ascii "\015\012\SDRAM with CL=2 at 100 MHz required!\015\012\000" +MramConfErr: + .ascii "\015\012\Unsupported SODIMM Configuration!\015\012\000" +Mactivate: + .ascii " Activating \000" +Mact0123e: + .ascii " MByte.\015\012\000" +Mok: + .ascii "OK \015\012\000" +Mfail: + .ascii "FAILED \015\012\000" +MnewLine: + .ascii "\015\012\000" + .align 4 diff --git a/board/eltec/elppc/config.mk b/board/eltec/elppc/config.mk new file mode 100644 index 0000000..aa463c5 --- /dev/null +++ b/board/eltec/elppc/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/eltec/elppc/eepro100_srom.c b/board/eltec/elppc/eepro100_srom.c new file mode 100644 index 0000000..f021c50 --- /dev/null +++ b/board/eltec/elppc/eepro100_srom.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Local network srom writing for first time run + */ + +/* includes */ +#include +#include +#include +#include "srom.h" + +extern int eepro100_write_eeprom (struct eth_device* dev, + int location, int addr_len, unsigned short data); + +/*----------------------------------------------------------------------------*/ + +unsigned short eepro100_srom_checksum (unsigned short *sromdata) +{ + unsigned short sum = 0; + unsigned int i; + + for (i = 0; i < (EE_SIZE-1); i++) + { + sum += sromdata[i]; + } + return (EE_CHECKSUM - sum); +} + +/*----------------------------------------------------------------------------*/ + +int eepro100_srom_store (unsigned short *source) +{ + int count; + struct eth_device onboard_dev; + + /* get onboard network iobase */ + pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0, + (unsigned int *)&onboard_dev.iobase); + onboard_dev.iobase &= ~0xf; + + source[63] = eepro100_srom_checksum (source); + + for (count=0; count < EE_SIZE; count++) + { + if ( eepro100_write_eeprom ((struct eth_device*)&onboard_dev, + count, EE_ADDR_BITS, SROM_SHORT(source)) == -1 ) + return -1; + source++; + } + return 0; +} + +/*----------------------------------------------------------------------------*/ + +#ifdef EEPRO100_SROM_CHECK + +extern int read_eeprom (struct eth_device* dev, int location, int addr_len); + +void eepro100_srom_load (unsigned short *destination) +{ + int count; + struct eth_device onboard_dev; +#ifdef DEBUG + int lr = 0; + printf ("eepro100_srom_download:\n"); +#endif + + /* get onboard network iobase */ + pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0, + &onboard_dev.iobase); + onboard_dev.iobase &= ~0xf; + + memset (destination, 0x65, 128); + + for (count=0; count < 0x40; count++) + { + *destination++ = read_eeprom (struct eth_device*)&onboard_dev, + count, EE_ADDR_BITS); +#ifdef DEBUG + printf ("%04x ", *(destination - 1)); + if (lr++ == 7) + { + printf("\n"); + lr = 0; + } +#endif + } +} +#endif /* EEPRO100_SROM_CHECK */ + +/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c new file mode 100644 index 0000000..a9dbeb2 --- /dev/null +++ b/board/eltec/elppc/elppc.c @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +int checkboard (void) +{ + puts ("Board: ELTEC PowerPC\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +int checkflash (void) +{ + /* TODO */ + printf ("Test not implemented !\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +static unsigned int mpc106_read_cfg_dword (unsigned int reg) +{ + unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC); + + out32r (MPC106_REG_ADDR, reg_addr); + + return (in32r (MPC106_REG_DATA | (reg & 0x3))); +} + +/* ------------------------------------------------------------------------- */ + +long int dram_size (int board_type) +{ + /* + * No actual initialisation to do - done when setting up + * PICRs MCCRs ME/SARs etc in asm_init.S. + */ + + register unsigned long i, msar1, mear1, memSize; + +#if defined(CFG_MEMTEST) + register unsigned long reg; + + printf ("Testing DRAM\n"); + + /* write each mem addr with it's address */ + for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) + *reg = reg; + + for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) { + if (*reg != reg) + return -1; + } +#endif + + /* + * Since MPC107 memory controller chip has already been set to + * control all memory, just read and interpret its memory boundery register. + */ + memSize = 0; + msar1 = mpc106_read_cfg_dword (MPC106_MSAR1); + mear1 = mpc106_read_cfg_dword (MPC106_MEAR1); + i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf; + + do { + if (i & 0x01) /* is bank enabled ? */ + memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1; + msar1 >>= 8; + mear1 >>= 8; + i >>= 1; + } while (i); + + return (memSize * 0x100000); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + return dram_size (board_type); +} + +/* ------------------------------------------------------------------------- */ + +/* + * The BAB 911 can be reset by writing bit 0 of the Processor Initialization + * Register PI in the MPC 107 (at offset 0x41090 of the Embedded Utilities + * Memory Block). + */ +int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + out8 (MPC107_EUMB_PI, 1); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_WATCHDOG) + +/* + * Since the 7xx CPUs don't have an internal watchdog, this function is + * board specific. + */ +void watchdog_reset (void) +{ +} +#endif /* CONFIG_WATCHDOG */ + +/* ------------------------------------------------------------------------- */ + +void after_reloc (ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* + * Jump to the main U-Boot board init code + */ + board_init_r ((gd_t *)gd, dest_addr); +} + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +extern GraphicDevice smi; + +void video_get_info_str (int line_number, char *info) +{ + /* init video info strings for graphic console */ + switch (line_number) { + case 1: + sprintf (info, " MPC7xx V%d.%d at %d / %d MHz", + (get_pvr () >> 8) & 0xFF, get_pvr () & 0xFF, 400, 100); + return; + case 2: + sprintf (info, " ELTEC ELPPC with %ld MB DRAM and %ld MB FLASH", + dram_size (0) / 0x100000, flash_init () / 0x100000); + return; + case 3: + sprintf (info, " %s", smi.modeIdent); + return; + } + + /* no more info lines */ + *info = 0; + return; +} +#endif diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c new file mode 100644 index 0000000..442dd00 --- /dev/null +++ b/board/eltec/elppc/flash.c @@ -0,0 +1,512 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC). + * fixed monitor protection part + * + * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage + * of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use + * any other. + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*flash command address offsets*/ + +#define ADDR0 (0x555) +#define ADDR1 (0x2AA) +#define ADDR3 (0x001) + +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------------*/ + +unsigned long flash_init (void) +{ + unsigned long size1, size2; + int i; + + /* Init: no FLASHes known */ + for (i=0; iflash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + flash_init(); + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + case AMD_ID_F016D: + printf ("AM29F016D (16 Mbit)\n"); + break; + case AMD_ID_F032B: + printf ("AM29F032B (32 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >= (1 << 20)) { + printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + } else { + printf (" Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count); + } + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------------*/ +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong vendor, devid; + ulong base = (ulong)addr; + volatile unsigned char *caddr = (unsigned char *)addr; + +#ifdef DEBUG + printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr); +#endif + + /* Write auto select command: read Manufacturer ID */ + caddr[0] = 0xF0; /* reset bank */ + udelay(10); + + eieio(); + caddr[0x555] = 0xAA; + udelay(10); + caddr[0x2AA] = 0x55; + udelay(10); + caddr[0x555] = 0x90; + + udelay(10); + + vendor = caddr[0]; + devid = caddr[1]; + +#ifdef DEBUG + printf("Manufacturer: 0x%lx\n", vendor); +#endif + + vendor &= 0xff; + devid &= 0xff; + + /* We accept only two AMD types */ + switch (vendor) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + switch (devid) { + case (FLASH_WORD_SIZE)AMD_ID_F040B: + info->flash_id |= AMD_ID_F040B; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_F016D: + info->flash_id |= AMD_ID_F016D; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_F032B: + info->flash_id |= AMD_ID_F032B; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + +#ifdef DEBUG + printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size); +#endif + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* sector base address */ + info->start[i] = base + i * (info->size / info->sector_count); + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (volatile unsigned char *)info->start[0]; + caddr[0] = 0xF0; /* reset bank */ + } + + return (info->size); +} + +/*----------------------------------------------------------------------------*/ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + int rc = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FLASH_WORD_SIZE *)(info->start[sect]); + if (info->flash_id & FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + udelay(30000); /* wait 30 ms */ + } + else + addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return rc; +} + +/*----------------------------------------------------------------------------*/ +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------------*/ +/* Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *)dest) & + (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) + { + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c new file mode 100644 index 0000000..5fb20ae --- /dev/null +++ b/board/eltec/elppc/misc.c @@ -0,0 +1,261 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* includes */ +#include +#include +#include +#include +#include "srom.h" + +/* imports */ +extern char console_buffer[CFG_CBSIZE]; +extern int l2_cache_enable (int l2control); +extern int eepro100_write_eeprom (struct eth_device *dev, int location, + int addr_len, unsigned short data); +extern int read_eeprom (struct eth_device *dev, int location, int addr_len); + +/*----------------------------------------------------------------------------*/ +/* + * read/write to nvram is only byte access + */ +void *nvram_read (void *dest, const long src, size_t count) +{ + uchar *d = (uchar *) dest; + uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src); + + while (count--) + *d++ = *s++; + + return dest; +} + +void nvram_write (long dest, const void *src, size_t count) +{ + uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest); + uchar *s = (uchar *) src; + + while (count--) + *d++ = *s++; +} + +/*----------------------------------------------------------------------------*/ +/* + * handle sroms on ELPPC + * fix ether address + * set serial console as default + */ +int misc_init_r (void) +{ + revinfo eerev; + u_char *ptr; + u_int i, l, initSrom, copyNv; + char buf[256]; + char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, + 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 + }; + + /* Clock setting for MPC107 i2c */ + mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b); + + /* Reset the EPIC */ + out32r (MPC107_EUMB_GCR, 0xa0000000); + while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */ + out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */ + while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */ + + /* + * Check/Remake revision info + */ + initSrom = 0; + copyNv = 0; + + /* read out current revision srom contens */ + mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo), + SECOND_DEVICE, FIRST_BLOCK); + + /* read out current nvram shadow image */ + nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE); + + if (strcmp (eerev.magic, "ELTEC") != 0) { + /* srom is not initialized -> create a default revision info */ + for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo); + i++) + *ptr++ = 0x00; + strcpy (eerev.magic, "ELTEC"); + eerev.revrev[0] = 1; + eerev.revrev[1] = 0; + eerev.size = 0x00E0; + eerev.category[0] = 0x01; + + /* node id from dead e128 as default */ + eerev.etheraddr[0] = 0x00; + eerev.etheraddr[1] = 0x00; + eerev.etheraddr[2] = 0x5B; + eerev.etheraddr[3] = 0x00; + eerev.etheraddr[4] = 0x2E; + eerev.etheraddr[5] = 0x4D; + + /* cache config word for ELPPC */ + *(int *) &eerev.res[0] = 0; + + initSrom = 1; /* force dialog */ + copyNv = 1; /* copy to nvram */ + } + + if ((copyNv == 0) + && (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) != + el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) { + printf ("Invalid revision info copy in nvram !\n"); + printf ("Press key:\n to copy current revision info to nvram.\n"); + printf (" to reenter revision info.\n"); + printf ("=> "); + if (0 != readline (NULL)) { + switch ((char) toupper (console_buffer[0])) { + case 'C': + copyNv = 1; + break; + case 'R': + copyNv = 1; + initSrom = 1; + break; + } + } + } + + if (initSrom) { + memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */ + printf ("Enter revision number (0-9): %c ", + eerev.revision[0][0]); + if (0 != readline (NULL)) { + eerev.revision[0][0] = + (char) toupper (console_buffer[0]); + memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */ + } + + printf ("Enter revision character (A-Z): %c ", + eerev.revision[0][1]); + if (1 == readline (NULL)) { + eerev.revision[0][1] = + (char) toupper (console_buffer[0]); + } + + printf ("Enter board name (V-XXXX-XXXX): %s ", + (char *) &eerev.board); + if (11 == readline (NULL)) { + for (i = 0; i < 11; i++) + eerev.board[i] = + (char) toupper (console_buffer[i]); + eerev.board[11] = '\0'; + } + + printf ("Enter serial number: %s ", (char *) &eerev.serial); + if (6 == readline (NULL)) { + for (i = 0; i < 6; i++) + eerev.serial[i] = console_buffer[i]; + eerev.serial[6] = '\0'; + } + + printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]); + if (12 == readline (NULL)) { + for (i = 0; i < 12; i += 2) + eerev.etheraddr[i >> 1] = + (char) (16 * + hex[toupper + (console_buffer[i]) - + '0'] + + hex[toupper + (console_buffer[i + 1]) - + '0']); + } + + l = strlen ((char *) &eerev.text); + printf ("Add to text section (max 64 chr): %s ", + (char *) &eerev.text); + if (0 != readline (NULL)) { + for (i = l; i < 63; i++) + eerev.text[i] = console_buffer[i - l]; + eerev.text[63] = '\0'; + } + + /* prepare network eeprom */ + memset (buf, 0, 128); + + buf[0] = eerev.etheraddr[1]; + buf[1] = eerev.etheraddr[0]; + buf[2] = eerev.etheraddr[3]; + buf[3] = eerev.etheraddr[2]; + buf[4] = eerev.etheraddr[5]; + buf[5] = eerev.etheraddr[4]; + + *(unsigned short *) &buf[20] = 0x48B2; + *(unsigned short *) &buf[22] = 0x0004; + *(unsigned short *) &buf[24] = 0x1433; + + printf ("\nSRom: Writing i82559 info ........ "); + if (eepro100_srom_store ((unsigned short *) buf) == -1) + printf ("FAILED\n"); + else + printf ("OK\n"); + + /* update CRC */ + eerev.crc = + el_srom_checksum ((u_char *) eerev.board, eerev.size); + + /* write new values */ + printf ("\nSRom: Writing revision info ...... "); + if (mpc107_srom_store + ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev, + sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1) + printf ("FAILED\n\n"); + else + printf ("OK\n\n"); + + /* write new values as shadow image to nvram */ + nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev, + CFG_SROM_SIZE); + + } + + /*if (initSrom) */ + /* copy current values as shadow image to nvram */ + if (initSrom == 0 && copyNv == 1) + nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev, + CFG_SROM_SIZE); + + /* update environment */ + sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", + eerev.etheraddr[0], eerev.etheraddr[1], + eerev.etheraddr[2], eerev.etheraddr[3], + eerev.etheraddr[4], eerev.etheraddr[5]); + setenv ("ethaddr", buf); + + /* print actual board identification */ + printf ("Ident: %s Ser %s Rev %c%c\n", + eerev.board, (char *) &eerev.serial, + eerev.revision[0][0], eerev.revision[0][1]); + + return (0); +} + +/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/mpc107_i2c.c b/board/eltec/elppc/mpc107_i2c.c new file mode 100644 index 0000000..ae6642e --- /dev/null +++ b/board/eltec/elppc/mpc107_i2c.c @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* includes */ +#include +#include "srom.h" + +/* locals */ +static unsigned long mpc107_eumb_addr = 0; + +/*----------------------------------------------------------------------------*/ + +/* + * calculate checksum for ELTEC revision srom + */ +unsigned long el_srom_checksum (ptr, size) +register unsigned char *ptr; +unsigned long size; +{ + u_long f, accu = 0; + u_int i; + u_char byte; + + for (; size; size--) + { + byte = *ptr++; + for (i = 8; i; i--) + { + f = ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0; + accu >>= 1; accu ^= f; + byte >>= 1; + } + } + return(accu); +} + +/*----------------------------------------------------------------------------*/ + +static int mpc107_i2c_wait ( unsigned long timeout ) +{ + unsigned long x; + + while (((x = in32r(MPC107_I2CSR)) & 0x82) != 0x82) + { + if (!timeout--) + return -1; + } + + if (x & 0x10) + { + return -1; + } + out32r(MPC107_I2CSR, 0); + + return 0; +} + +/*----------------------------------------------------------------------------*/ + +static int mpc107_i2c_wait_idle ( unsigned long timeout ) +{ + while (in32r(MPC107_I2CSR) & 0x20) + { + if (!timeout--) + return -1; + } + return 0; +} + + +/*----------------------------------------------------------------------------*/ + +int mpc107_i2c_read_byte ( + unsigned char device, + unsigned char block, + unsigned char offset ) +{ + unsigned long timeout = MPC107_I2C_TIMEOUT; + int data; + + if (!mpc107_eumb_addr) + return -6; + + mpc107_i2c_wait_idle (timeout); + + /* Start with MEN */ + out32r(MPC107_I2CCR, 0x80); + + /* Start as master */ + out32r(MPC107_I2CCR, 0xB0); + out32r(MPC107_I2CDR, (0xA0 | device | block)); + + if (mpc107_i2c_wait(timeout) < 0) + { + printf("mpc107_i2c_read Error 1\n"); + return -2; + } + + if (in32r(MPC107_I2CSR)&0x1) + { + /* Generate STOP condition; device busy or not existing */ + out32r(MPC107_I2CCR, 0x80); + return -1; + } + + /* Data address */ + out32r(MPC107_I2CDR, offset); + + if (mpc107_i2c_wait(timeout) < 0) + { + printf("mpc107_i2c_read Error 2\n"); + return -3; + } + + /* Switch to read - restart */ + out32r(MPC107_I2CCR, 0xB4); + out32r(MPC107_I2CDR, (0xA1 | device | block)); + + if (mpc107_i2c_wait(timeout) < 0) + { + printf("mpc107_i2c_read Error 3\n"); + return -4; + } + + out32r(MPC107_I2CCR, 0xA8); /* no ACK */ + in32r(MPC107_I2CDR); + + if (mpc107_i2c_wait(timeout) < 0) + { + printf("mpc107_i2c_read Error 4\n"); + return -5; + } + /* Generate STOP condition */ + out32r(MPC107_I2CCR, 0x88); + + /* read */ + data = in32r(MPC107_I2CDR); + + return (data); +} + +/*----------------------------------------------------------------------------*/ + +int mpc107_i2c_write_byte ( + unsigned char device, + unsigned char block, + unsigned char offset, + unsigned char val ) +{ + + unsigned long timeout = MPC107_I2C_TIMEOUT; + + if (!mpc107_eumb_addr) + return -6; + + mpc107_i2c_wait_idle(timeout); + + /* Start with MEN */ + out32r(MPC107_I2CCR, 0x80); + + /* Start as master */ + out32r(MPC107_I2CCR, 0xB0); + out32r(MPC107_I2CDR, (0xA0 | device | block)); + + if (mpc107_i2c_wait(timeout) < 0) + { + printf("mpc107_i2c_write Error 1\n"); + return -1; + } + + /* Data address */ + out32r(MPC107_I2CDR, offset); + + if (mpc107_i2c_wait(timeout) < 0) + { + printf("mpc107_i2c_write Error 2\n"); + return -1; + } + + /* Write */ + out32r(MPC107_I2CDR, val); + if (mpc107_i2c_wait(timeout) < 0) + { + printf("mpc107_i2c_write Error 3\n"); + return -1; + } + + /* Generate Stop Condition */ + out32r(MPC107_I2CCR, 0x80); + + /* Return ACK or no ACK */ + return (in32r(MPC107_I2CSR) & 0x01); +} + +/*----------------------------------------------------------------------------*/ + +int mpc107_srom_load ( + unsigned char addr, + unsigned char *pBuf, + int cnt, + unsigned char device, + unsigned char block ) +{ + register int i; + int val; + int timeout; + + for (i = 0; i < cnt; i++) + { + timeout=100; + do + { + val = mpc107_i2c_read_byte (device, block, addr); + if (val < -1) + { + printf("i2c_read_error %d at dev %x block %x addr %x\n", + val, device, block, addr); + return -1; + } + else if (timeout==0) + { + printf ("i2c_read_error: timeout at dev %x block %x addr %x\n", + device, block, addr); + return -1; + } + timeout--; + } while (val == -1); /* if no ack: try again! */ + + *pBuf++ = (unsigned char)val; + addr++; + + if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */ + { + if (block == FIRST_BLOCK) + block = SECOND_BLOCK; + else + { + printf ("ic2_read_error: read beyond 2. block !\n"); + return -1; + } + } + } + udelay(100000); + return (cnt); +} + +/*----------------------------------------------------------------------------*/ + +int mpc107_srom_store ( + unsigned char addr, + unsigned char *pBuf, + int cnt, + unsigned char device, + unsigned char block ) +{ + register int i; + + for (i = 0; i < cnt; i++) + { + while (mpc107_i2c_write_byte (device,block,addr,*pBuf) == 1); + addr++; + pBuf++; + + if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */ + { + if (block == FIRST_BLOCK) + block = SECOND_BLOCK; + else + { + printf ("ic2_write_error: write beyond 2. block !\n"); + return -1; + } + } + } + udelay(100000); + return(cnt); +} + +/*----------------------------------------------------------------------------*/ + +int mpc107_i2c_init ( unsigned long eumb_addr, unsigned long divider ) +{ + unsigned long x; + + if (eumb_addr) + mpc107_eumb_addr = eumb_addr; + else + return -1; + + /* Set I2C clock */ + x = in32r(MPC107_I2CFDR) & 0xffffff00; + out32r(MPC107_I2CFDR, (x | divider)); + + /* Clear arbitration */ + out32r(MPC107_I2CSR, 0); + + return mpc107_eumb_addr; +} + +/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c new file mode 100644 index 0000000..5b115ea --- /dev/null +++ b/board/eltec/elppc/pci.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI initialisation for the MPC10x. + */ + +#include +#include +#include + +#ifdef CONFIG_PCI + +struct pci_controller local_hose; + +void pci_init_board(void) +{ + struct pci_controller* hose = (struct pci_controller *)&local_hose; + u16 reg16; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI_MEM_BUS, + CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 2, + CFG_ISA_MEM_BUS, + CFG_ISA_MEM_PHYS, + CFG_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 3, + CFG_PCI_IO_BUS, + CFG_PCI_IO_PHYS, + CFG_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 4, + CFG_ISA_IO_BUS, + CFG_ISA_IO_PHYS, + CFG_ISA_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 5; + + pci_setup_indirect(hose, + MPC106_REG_ADDR, + MPC106_REG_DATA); + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); + + /* Initialises the MPC10x PCI Configuration regs. */ + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + + /* Clear non-reserved bits in status register */ + pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); +} + +#endif /* CONFIG_PCI */ diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h new file mode 100644 index 0000000..c18ab91 --- /dev/null +++ b/board/eltec/elppc/srom.h @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* common srom defs */ +#define FIRST_DEVICE 0x00 +#define SECOND_DEVICE 0x04 +#define FIRST_BLOCK 0x00 +#define SECOND_BLOCK 0x02 +#define BLOCK_SIZE 0x100 +#define ERROR (-1) + +#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100 +#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100 + +#define CPU_TYPE_740 0x08 +#define CPU_TYPE_750 0x08 +#define CPU_TYPE ((get_pvr()>>16)&0xffff) + +#define ABS(x) ((x<0)?-x:x) +#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8) + +/* bab7xx ELTEC srom */ +#define I2C_BUS_DAT (CFG_ISA_IO + 0x220) +#define I2C_BUS_DIR (CFG_ISA_IO + 0x221) + +/* srom at mpc107 */ +#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */ +#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */ +#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */ +#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */ +#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */ +#define MPC107_I2C_TIMEOUT 10000000 + +/* i82559 */ +#define EE_ADDR_BITS 6 +#define EE_SIZE 0x40 /* 0x40 words */ +#define EE_CHECKSUM 0xBABA + +/* dc21143 */ +#define DEC_SROM_SIZE 128 + + +/* + * structure of revision srom + */ +typedef struct { + char magic[8]; /* 000 - Magic number */ + char revrev[2]; /* 008 - Revision of structure */ + unsigned short size; /* 00A - Size of CRC area */ + unsigned long crc; /* 00C - CRC */ + char board[16]; /* 010 - Board Revision information */ + char option[4][16]; /* 020 - Option Revision information */ + char serial[8]; /* 060 - Board serial number */ + char etheraddr[6]; /* 068 - Ethernet node addresse */ + char reserved[2]; /* 06E - Reserved */ + char revision[7][2]; /* 070 - Revision codes */ + char category[2]; /* 07E - Category codes */ + char text[64]; /* 080 - Text field */ + char res[64]; /* 0C0 - Reserved */ +} revinfo; + +unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size); +int el_srom_load (unsigned char addr, unsigned char *buf, int cnt, + unsigned char device, unsigned char block); +int el_srom_store (unsigned char addr, unsigned char *buf, int cnt, + unsigned char device, unsigned char block); + +int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider); +int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset); +int mpc107_i2c_write_byte (unsigned char device, unsigned char block, + unsigned char offset, unsigned char val); +int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt, + unsigned char device, unsigned char block); +int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt, + unsigned char device, unsigned char block); + +int dc_srom_load (unsigned short *dest); +int dc_srom_store (unsigned short *src); + +unsigned short eepro100_srom_checksum (unsigned short *sromdata); +void eepro100_srom_load (unsigned short *destination); +int eepro100_srom_store (unsigned short *source); diff --git a/board/eltec/elppc/u-boot.lds b/board/eltec/elppc/u-boot.lds new file mode 100644 index 0000000..d89eb6c --- /dev/null +++ b/board/eltec/elppc/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/eltec/mhpc/Makefile b/board/eltec/mhpc/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/eltec/mhpc/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/eltec/mhpc/config.mk b/board/eltec/mhpc/config.mk new file mode 100644 index 0000000..03934de --- /dev/null +++ b/board/eltec/mhpc/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MHPC boards +# + +TEXT_BASE = 0xfe000000 +/*TEXT_BASE = 0x00200000 */ diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c new file mode 100644 index 0000000..4cc66a9 --- /dev/null +++ b/board/eltec/mhpc/flash.c @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE+monitor_flash_len-1, + &flash_info[0]); + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000); + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F640J5 : + printf ("28F640J5 \n"); break; + default: printf ("Unknown Chip Type=0x%lXh\n", + info->flash_id & FLASH_TYPEMASK); break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW)0xAA00AA00; + addr[0x2AAA] = (FPW)0x55005500; + addr[0x5555] = (FPW)0x90009000; + + value = SWAP(addr[0]); + + switch (value) { + case (FPW)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW)0xFF00FF00; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + value = SWAP(addr[1]); /* device ID no swap !*/ + + switch (value) { + case (FPW)INTEL_ID_28F640J5 : + info->flash_id += FLASH_28F640J5 ; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW)0xFF00FF00; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, now, last; + int rc = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *)(info->start[sect]); + FPW status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = (FPW)0x50005000; /* clear status register */ + *addr = (FPW)0x20002000; /* erase setup */ + *addr = (FPW)0xD000D000; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW)0xB000B000; /* suspend erase */ + *addr = (FPW)0xFF00FF00; /* reset to read mode */ + rc = 1; + break; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = (FPW)0xFF00FF00; /* reset to read mode */ + printf (" done\n"); + } + } + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= port_width) { + data = 0; + for (i=0; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i CFG_FLASH_WRITE_TOUT) { + *addr = (FPW)0xFF00FF00; /* restore read mode */ + return (1); + } + } + + *addr = (FPW)0xFF00FF00; /* restore read mode */ + + return (0); +} diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c new file mode 100644 index 0000000..0ffbdf0 --- /dev/null +++ b/board/eltec/mhpc/mhpc.c @@ -0,0 +1,483 @@ +/* + * (C) Copyright 2001 + * ELTEC Elektronik AG + * Frank Gottschling + * + * Board specific routines for the miniHiPerCam + * + * - initialisation (eeprom) + * - memory controller + * - serial io initialisation + * - ethernet io initialisation + * + * ----------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include "mpc8xx.h" +#include + +/* imports from common/main.c */ +extern char console_buffer[CFG_CBSIZE]; + +extern void eeprom_init (void); +extern int eeprom_read (unsigned dev_addr, unsigned offset, + unsigned char *buffer, unsigned cnt); +extern int eeprom_write (unsigned dev_addr, unsigned offset, + unsigned char *buffer, unsigned cnt); + +/* globals */ +void *video_hw_init (void); +void video_set_lut (unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ); + +GraphicDevice gdev; + +/* locals */ +static void video_circle (char *center, int radius, int color, int pitch); +static void video_test_image (void); +static void video_default_lut (unsigned int clut_type); + +/* revision info foer MHPC EEPROM offset 480 */ +typedef struct { + char board[12]; /* 000 - Board Revision information */ + char sensor; /* 012 - Sensor Type information */ + char serial[8]; /* 013 - Board serial number */ + char etheraddr[6]; /* 021 - Ethernet node addresse */ + char revision[2]; /* 027 - Revision code */ + char option[3]; /* 029 - resevered for options */ +} revinfo; + +/* ------------------------------------------------------------------------- */ + +static const unsigned int sdram_table[] = { + /* read single beat cycle */ + 0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00, + 0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35, + + /* read burst cycle */ + 0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00, + 0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* write single beat cycle */ + 0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* write burst cycle */ + 0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440, + 0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* periodic timer expired */ + 0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84, + 0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05, + 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, + + /* exception */ + 0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04 +}; + +/* ------------------------------------------------------------------------- */ + +int board_early_init_f (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport); + + /* reset the port A s.a. cpm-routines */ + ip->iop_padat = 0x0000; + ip->iop_papar = 0x0000; + ip->iop_padir = 0x0800; + ip->iop_paodr = 0x0000; + + /* reset the port B for digital and LCD output */ + cp->cp_pbdat = 0x0300; + cp->cp_pbpar = 0x5001; + cp->cp_pbdir = 0x5301; + cp->cp_pbodr = 0x0000; + + /* reset the port C configured for SMC1 serial port and aqc. control */ + ip->iop_pcdat = 0x0800; + ip->iop_pcpar = 0x0000; + ip->iop_pcdir = 0x0e30; + ip->iop_pcso = 0x0000; + + /* Config port D for LCD output */ + ip->iop_pdpar = 0x1fff; + ip->iop_pddir = 0x1fff; + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity + */ +int checkboard (void) +{ + puts ("Board: ELTEC miniHiperCam\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +int misc_init_r (void) +{ + revinfo mhpcRevInfo; + char nid[32]; + char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color", + "OMNIVISON OV7110 b&w", NULL + }; + char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, + 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 + }; + int i; + + /* check revision data */ + eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32); + + if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) { + printf ("Enter revision number (0-9): %c ", + mhpcRevInfo.revision[0]); + if (0 != readline (NULL)) { + mhpcRevInfo.revision[0] = + (char) toupper (console_buffer[0]); + } + + printf ("Enter revision character (A-Z): %c ", + mhpcRevInfo.revision[1]); + if (1 == readline (NULL)) { + mhpcRevInfo.revision[1] = + (char) toupper (console_buffer[0]); + } + + printf ("Enter board name (V-XXXX-XXXX): %s ", + (char *) &mhpcRevInfo.board); + if (11 == readline (NULL)) { + for (i = 0; i < 11; i++) { + mhpcRevInfo.board[i] = + (char) toupper (console_buffer[i]); + mhpcRevInfo.board[11] = '\0'; + } + } + + printf ("Supported sensor types:\n"); + i = 0; + do { + printf ("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]); + } while (mhpcSensorTypes[++i] != NULL); + + do { + printf ("\nEnter sensor number (0-255): %d ", + (int) mhpcRevInfo.sensor); + if (0 != readline (NULL)) { + mhpcRevInfo.sensor = + (unsigned char) + simple_strtoul (console_buffer, NULL, + 10); + } + } while (mhpcRevInfo.sensor >= i); + + printf ("Enter serial number: %s ", + (char *) &mhpcRevInfo.serial); + if (6 == readline (NULL)) { + for (i = 0; i < 6; i++) { + mhpcRevInfo.serial[i] = console_buffer[i]; + } + mhpcRevInfo.serial[6] = '\0'; + } + + printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); + if (12 == readline (NULL)) { + for (i = 0; i < 12; i += 2) { + mhpcRevInfo.etheraddr[i >> 1] = + (char) (16 * + hex[toupper + (console_buffer[i]) - + '0'] + + hex[toupper + (console_buffer[i + 1]) - + '0']); + } + } + + /* setup new revision data */ + eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, + 32); + } + + /* set environment */ + sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x", + mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], + mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], + mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); + setenv ("ethaddr", nid); + + /* print actual board identification */ + printf ("Ident: %s %s Ser %s Rev %c%c\n", + mhpcRevInfo.board, + (mhpcRevInfo.sensor == 0 ? "color" : "b&w"), + (char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0], + mhpcRevInfo.revision[1]); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */ + memctl->memc_mptpr = MPTPR_PTP_DIV64; + memctl->memc_mar = 0x00008800; + + /* + * Map controller SDRAM bank 0 + */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + udelay (200); + + /* + * Map controller SDRAM bank 1 + */ + memctl->memc_or2 = CFG_OR2; + memctl->memc_br2 = CFG_BR2; + + /* + * Perform SDRAM initializsation sequence + */ + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */ + udelay (1); + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (10000); + + /* leave place for framebuffers */ + return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE); +} + +/* ------------------------------------------------------------------------- */ + +static void video_circle (char *center, int radius, int color, int pitch) +{ + int x, y, d, dE, dSE; + + x = 0; + y = radius; + d = 1 - radius; + dE = 3; + dSE = -2 * radius + 5; + + *(center + x + y * pitch) = color; + *(center + y + x * pitch) = color; + *(center + y - x * pitch) = color; + *(center + x - y * pitch) = color; + *(center - x - y * pitch) = color; + *(center - y - x * pitch) = color; + *(center - y + x * pitch) = color; + *(center - x + y * pitch) = color; + while (y > x) { + if (d < 0) { + d += dE; + dE += 2; + dSE += 2; + x++; + } else { + d += dSE; + dE += 2; + dSE += 4; + x++; + y--; + } + *(center + x + y * pitch) = color; + *(center + y + x * pitch) = color; + *(center + y - x * pitch) = color; + *(center + x - y * pitch) = color; + *(center - x - y * pitch) = color; + *(center - y - x * pitch) = color; + *(center - y + x * pitch) = color; + *(center - x + y * pitch) = color; + } +} + +/* ------------------------------------------------------------------------- */ + +static void video_test_image (void) +{ + char *di; + int i, n; + + /* draw raster */ + for (i = 0; i < LCD_VIDEO_ROWS; i += 32) { + memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS), + LCD_VIDEO_FG, LCD_VIDEO_COLS); + for (n = i + 1; n < i + 32; n++) + memset ((char *) (LCD_VIDEO_ADDR + + n * LCD_VIDEO_COLS), LCD_VIDEO_BG, + LCD_VIDEO_COLS); + } + + for (i = 0; i < LCD_VIDEO_COLS; i += 32) { + for (n = 0; n < LCD_VIDEO_ROWS; n++) + *(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) = + LCD_VIDEO_FG; + } + + /* draw gray bar */ + di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 + + 97 * LCD_VIDEO_COLS); + for (n = 0; n < 63; n++) { + for (i = 0; i < 256; i++) { + *di++ = (char) i; + *(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255; + } + di += LCD_VIDEO_COLS - 256; + } + + video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 + + LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2, + LCD_VIDEO_FG, LCD_VIDEO_COLS); +} + +/* ------------------------------------------------------------------------- */ + +static void video_default_lut (unsigned int clut_type) +{ + unsigned int i; + unsigned char RGB[] = { + 0x00, 0x00, 0x00, /* black */ + 0x80, 0x80, 0x80, /* gray */ + 0xff, 0x00, 0x00, /* red */ + 0x00, 0xff, 0x00, /* green */ + 0x00, 0x00, 0xff, /* blue */ + 0x00, 0xff, 0xff, /* cyan */ + 0xff, 0x00, 0xff, /* magenta */ + 0xff, 0xff, 0x00, /* yellow */ + 0x80, 0x00, 0x00, /* dark red */ + 0x00, 0x80, 0x00, /* dark green */ + 0x00, 0x00, 0x80, /* dark blue */ + 0x00, 0x80, 0x80, /* dark cyan */ + 0x80, 0x00, 0x80, /* dark magenta */ + 0x80, 0x80, 0x00, /* dark yellow */ + 0xc0, 0xc0, 0xc0, /* light gray */ + 0xff, 0xff, 0xff, /* white */ + }; + + switch (clut_type) { + case 1: + for (i = 0; i < 240; i++) + video_set_lut (i, i, i, i); + for (i = 0; i < 16; i++) + video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1], + RGB[i * 3 + 2]); + break; + default: + for (i = 0; i < 256; i++) + video_set_lut (i, i, i, i); + } +} + +/* ------------------------------------------------------------------------- */ + +void *video_hw_init (void) +{ + unsigned int clut = 0; + unsigned char *penv; + immap_t *immr = (immap_t *) CFG_IMMR; + + /* enable video only on CLUT value */ + if ((penv = (uchar *)getenv ("clut")) != NULL) + clut = (u_int) simple_strtoul ((char *)penv, NULL, 10); + else + return NULL; + + /* disable graphic before write LCD regs. */ + immr->im_lcd.lcd_lccr = 0x96000866; + + /* config LCD regs. */ + immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR; + immr->im_lcd.lcd_lchcr = 0x010a0093; + immr->im_lcd.lcd_lcvcr = 0x900f0024; + + printf ("Video: 640x480 8Bit Index Lut %s\n", + (clut == 1 ? "240/16 (gray/vga)" : "256(gray)")); + + video_default_lut (clut); + + /* clear framebuffer */ + memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG, + LCD_VIDEO_ROWS * LCD_VIDEO_COLS); + + /* enable graphic */ + immr->im_lcd.lcd_lccr = 0x96000867; + + /* fill in Graphic Device */ + gdev.frameAdrs = LCD_VIDEO_ADDR; + gdev.winSizeX = LCD_VIDEO_COLS; + gdev.winSizeY = LCD_VIDEO_ROWS; + gdev.gdfBytesPP = 1; + gdev.gdfIndex = GDF__8BIT_INDEX; + + if (clut > 1) + /* return Graphic Device for console */ + return (void *) &gdev; + else + /* just graphic enabled - draw something beautiful */ + video_test_image (); + + return NULL; /* this disabels cfb - console */ +} + +/* ------------------------------------------------------------------------- */ + +void video_set_lut (unsigned int index, + unsigned char r, unsigned char g, unsigned char b) +{ + unsigned int lum; + unsigned short *pLut = (unsigned short *) (CFG_IMMR + 0x0e00); + + /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */ + /* y = 0.299*R + 0.587*G + 0.114*B */ + lum = (2990 * r + 5870 * g + 1140 * b) / 10000; + pLut[index] = + ((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum & + 0x3f); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds new file mode 100644 index 0000000..7099fc4 --- /dev/null +++ b/board/eltec/mhpc/u-boot.lds @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug new file mode 100644 index 0000000..3165d56 --- /dev/null +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/emk/common/am79c874.c b/board/emk/common/am79c874.c new file mode 100644 index 0000000..552813e --- /dev/null +++ b/board/emk/common/am79c874.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2003 + * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/***************************************************************************** + * check fiber optic link present, and then copper link present. do auto switch + * between both + *****************************************************************************/ diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c new file mode 100644 index 0000000..d6161bf --- /dev/null +++ b/board/emk/common/flash.c @@ -0,0 +1,591 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined (CONFIG_TOP860) + typedef unsigned short FLASH_PORT_WIDTH; + typedef volatile unsigned short FLASH_PORT_WIDTHV; + #define FLASH_ID_MASK 0xFF + + #define FPW FLASH_PORT_WIDTH + #define FPWV FLASH_PORT_WIDTHV + + #define FLASH_CYCLE1 0x0555 + #define FLASH_CYCLE2 0x02aa + #define FLASH_ID1 0 + #define FLASH_ID2 1 + #define FLASH_ID3 0x0e + #define FLASH_ID4 0x0F +#endif + +#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200) + typedef unsigned char FLASH_PORT_WIDTH; + typedef volatile unsigned char FLASH_PORT_WIDTHV; + #define FLASH_ID_MASK 0xFF + + #define FPW FLASH_PORT_WIDTH + #define FPWV FLASH_PORT_WIDTHV + + #define FLASH_CYCLE1 0x0aaa + #define FLASH_CYCLE2 0x0555 + #define FLASH_ID1 0 + #define FLASH_ID2 2 + #define FLASH_ID3 0x1c + #define FLASH_ID4 0x1E +#endif + +#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200) + typedef unsigned char FLASH_PORT_WIDTH; + typedef volatile unsigned char FLASH_PORT_WIDTHV; + #define FLASH_ID_MASK 0xFF + + #define FPW FLASH_PORT_WIDTH + #define FPWV FLASH_PORT_WIDTHV + + #define FLASH_CYCLE1 0x0555 + #define FLASH_CYCLE2 0x02aa + #define FLASH_ID1 0 + #define FLASH_ID2 1 + #define FLASH_ID3 0x0E + #define FLASH_ID4 0x0F +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i = 0; + extern void flash_preinit(void); + extern void flash_afterinit(uint, ulong, ulong); + ulong flashbase = CFG_FLASH_BASE; + + flash_preinit(); + + /* There is only ONE FLASH device */ + memset(&flash_info[i], 0, sizeof(flash_info_t)); + flash_info[i].size = + flash_get_size((FPW *)flashbase, &flash_info[i]); + size += flash_info[i].size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + + flash_afterinit(i, flash_info[i].start[0], flash_info[i].size); + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && + info->start[0] <= base && base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + char *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; +#if 0 + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; +#endif + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM160T: + case FLASH_AM160B: + fmt = "29LV160%s (16 Mbit, %s)\n"; + break; + case FLASH_AMLV640U: + fmt = "29LV640M (64 Mbit)\n"; + break; + case FLASH_AMDLV065D: + fmt = "29LV065D (64 Mbit)\n"; + break; + case FLASH_AMLV256U: + fmt = "29LV256M (256 Mbit)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + ulong size; + int erased; + ulong *flash = (unsigned long *) info->start[i]; + + if ((i % 5) == 0) { + printf ("\n "); + } + + /* + * Check if whole sector is erased + */ + size = + (i != (info->sector_count - 1)) ? + (info->start[i + 1] - info->start[i]) >> 2 : + (info->start[0] + info->size - info->start[i]) >> 2; + + for ( + flash = (unsigned long *) info->start[i], erased = 1; + (flash != (unsigned long *) info->start[i] + size) && erased; + flash++ + ) + erased = *flash == ~0x0UL; + + printf (" %08lX %s %s", + info->start[i], + erased ? "E": " ", + info->protect[i] ? "(RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + int i; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(100); + switch (addr[FLASH_ID1] & 0xff) { + + case (uchar)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + +#if 0 + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; +#endif + + default: + printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) { + + case (FPW)AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + info->start[0] = (ulong)addr; + info->start[1] = (ulong)addr + 0x4000; + info->start[2] = (ulong)addr + 0x6000; + info->start[3] = (ulong)addr + 0x8000; + for (i = 4; i < info->sector_count; i++) + { + info->start[i] = (ulong)addr + 0x10000 * (i-3); + } + break; + + case (FPW)AMD_ID_LV065D: + info->flash_id += FLASH_AMDLV065D; + info->sector_count = 128; + info->size = 0x00800000; + for (i = 0; i < info->sector_count; i++) + { + info->start[i] = (ulong)addr + 0x10000 * i; + } + break; + + case (FPW)AMD_ID_MIRROR: + /* MIRROR BIT FLASH, read more ID bytes */ + if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 && + (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3) + { + info->flash_id += FLASH_AMLV640U; + info->sector_count = 128; + info->size = 0x00800000; + for (i = 0; i < info->sector_count; i++) + { + info->start[i] = (ulong)addr + 0x10000 * i; + } + break; + } + if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 && + (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3) + { + /* attention: only the first 16 MB will be used in u-boot */ + info->flash_id += FLASH_AMLV256U; + info->sector_count = 256; + info->size = 0x01000000; + for (i = 0; i < info->sector_count; i++) + { + info->start[i] = (ulong)addr + 0x10000 * i; + } + break; + } + + /* fall thru to here ! */ + default: + printf ("unknown AMD device=%x %x %x", + (FPW)addr[FLASH_ID2], + (FPW)addr[FLASH_ID3], + (FPW)addr[FLASH_ID4]); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0x800000; + break; + } + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM160B: + case FLASH_AMLV640U: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + if (intel) { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW)0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) {/* every second */ + putc ('.'); + last = get_timer(0); + } + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { /* every second */ + putc ('.'); + last = get_timer(0); + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} diff --git a/board/emk/common/vpd.c b/board/emk/common/vpd.c new file mode 100644 index 0000000..8a3a12b --- /dev/null +++ b/board/emk/common/vpd.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2003 + * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/***************************************************************************** + * read "factory" part of EEPROM and set some environment variables + *****************************************************************************/ +void read_factory_r (void) +{ + /* read 'factory' part of EEPROM */ + uchar buf[81]; + uchar *p; + uint length; + uint addr; + uint len; + + /* get length first */ + addr = CFG_FACT_OFFSET; + if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2)) { + bailout: + printf ("cannot read factory configuration\n"); + printf ("be sure to set ethaddr yourself!\n"); + return; + } + length = buf[0] + (buf[1] << 8); + addr += 2; + + /* sanity check */ + if (length < 20 || length > CFG_FACT_SIZE - 2) + goto bailout; + + /* read lines */ + while (length > 0) { + /* read one line */ + len = length > 80 ? 80 : length; + if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len)) + goto bailout; + /* mark end of buffer */ + buf[len] = 0; + /* search end of line */ + for (p = buf; *p && *p != 0x0a; p++); + if (!*p) + goto bailout; + *p++ = 0; + /* advance to next line start */ + length -= p - buf; + addr += p - buf; + /*printf ("%s\n", buf); */ + /* search for our specific entry */ + if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) { + setenv ("ethaddr", (char *)(buf + 19)); + } else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) { + setenv ("serial#", (char *)(buf + 15)); + } else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) { + setenv ("board_id", (char *)(buf + 13)); + } + } +} diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile new file mode 100644 index 0000000..986608b --- /dev/null +++ b/board/emk/top5200/Makefile @@ -0,0 +1,47 @@ + +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/emk/top5200/config.mk b/board/emk/top5200/config.mk new file mode 100644 index 0000000..84131fe --- /dev/null +++ b/board/emk/top5200/config.mk @@ -0,0 +1,41 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2003 +# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TOP5200 board, on optional MINI5200 and EVAL5200 boards +# +# allowed and functional TEXT_BASE values: +# +# 0xff000000 low boot at 0x00000100 (default board setting) +# 0xfff00000 high boot at 0xfff00100 (board needs modification) +# 0x00100000 RAM load and test +# + +TEXT_BASE = 0xff000000 +#TEXT_BASE = 0xfff00000 +#TEXT_BASE = 0x00100000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c new file mode 100644 index 0000000..4508438 --- /dev/null +++ b/board/emk/top5200/top5200.c @@ -0,0 +1,210 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/***************************************************************************** + * initialize SDRAM/DDRAM controller. + * TBD: get data from I2C EEPROM + *****************************************************************************/ +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT +#if 0 + ulong t; + ulong tap_del; +#endif + + #define MODE_EN 0x80000000 + #define SOFT_PRE 2 + #define SOFT_REF 4 + + /* configure SDRAM start/end */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE; + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN; + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE; +#ifdef CFG_DRAM_DDR + /* set extended mode register */ + *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE; +#endif + /* set mode register */ + *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400; + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE; + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF; + /* set mode register */ + *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE; + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL; + /* write default TAP delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24; + +#if 0 + for (tap_del = 0; tap_del < 32; tap_del++) + { + *(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24; + + printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG); + for (t = 0; t < 0x04000000; t+=4) + *(vu_long *) t = t; + printf ("Checking DRAM...\n"); + for (t = 0; t < 0x04000000; t+=4) + { + ulong rval = *(vu_long *) t; + if (rval != t) + { + printf ("mismatch at %x: ", t); + printf (" 1.read %x", rval); + printf (" 2.read %x", *(vu_long *) t); + printf (" 3.read %x", *(vu_long *) t); + break; + } + } + } +#endif +#endif /* CFG_RAMBOOT */ + + dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20); + + /* return total ram size */ + return dramsize; +} + +/***************************************************************************** + * print board identification + *****************************************************************************/ +int checkboard (void) +{ +#if defined (CONFIG_EVAL5200) + puts ("Board: EMK TOP5200 on EVAL5200\n"); +#else +#if defined (CONFIG_LITE5200) + puts ("Board: LITE5200\n"); +#else +#if defined (CONFIG_MINI5200) + puts ("Board: EMK TOP5200 on MINI5200\n"); +#else + puts ("Board: EMK TOP5200\n"); +#endif +#endif +#endif + return 0; +} + +/***************************************************************************** + * prepare for FLASH detection + *****************************************************************************/ +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + +/***************************************************************************** + * finalize FLASH setup + *****************************************************************************/ +void flash_afterinit(uint bank, ulong start, ulong size) +{ + if (bank == 0) { /* adjust mapping */ + *(vu_long *)MPC5XXX_BOOTCS_START = + *(vu_long *)MPC5XXX_CS0_START = START_REG(start); + *(vu_long *)MPC5XXX_BOOTCS_STOP = + *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size); + } +} + +/***************************************************************************** + * otherinits after RAM is there and we are relocated to RAM + * note: though this is an int function, nobody cares for the result! + *****************************************************************************/ +int misc_init_r (void) +{ +#if !defined (CONFIG_LITE5200) + /* read 'factory' part of EEPROM */ + extern void read_factory_r (void); + read_factory_r (); +#endif + return (0); +} + +/***************************************************************************** + * initialize the PCI system + *****************************************************************************/ +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +/***************************************************************************** + * provide the IDE Reset Function + *****************************************************************************/ +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + } +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/emk/top5200/u-boot.lds b/board/emk/top5200/u-boot.lds new file mode 100644 index 0000000..f23432e --- /dev/null +++ b/board/emk/top5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile new file mode 100644 index 0000000..a74dd2f --- /dev/null +++ b/board/emk/top860/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/emk/top860/config.mk b/board/emk/top860/config.mk new file mode 100644 index 0000000..7b940cb --- /dev/null +++ b/board/emk/top860/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TOP860 board +# + +TEXT_BASE = 0x80000000 diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c new file mode 100644 index 0000000..84afaaa --- /dev/null +++ b/board/emk/top860/top860.c @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2003 + * EMK Elektronik GmbH + * Reinhard Meyer + * + * Board specific routines for the TOP860 + * + * - initialisation + * - interface to VPD data (mac address, clock speeds) + * - memory controller + * - serial io initialisation + * - ethernet io initialisation + * + * ----------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/***************************************************************************** + * UPM table for 60ns EDO RAM at 25 MHz bus/external clock + *****************************************************************************/ +static const uint edo_60ns_25MHz_tbl[] = { + +/* single read (offset 0x00 in upm ram) */ + 0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00, + 0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05, +/* burst read (offset 0x08 in upm ram) */ + 0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40, + 0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48, + 0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05, + 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, +/* single write (offset 0x18 in upm ram) */ + 0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07, + 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, +/* burst write (offset 0x20 in upm ram) */ + 0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c, + 0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c, + 0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05, + 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, +/* refresh (offset 0x30 in upm ram) */ + 0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04, + 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, + 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, +/* exception (offset 0x3C in upm ram) */ + 0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05, +}; + +/***************************************************************************** + * Print Board Identity + *****************************************************************************/ +int checkboard (void) +{ + puts ("Board:"CONFIG_IDENT_STRING"\n"); + return (0); +} + +/***************************************************************************** + * Initialize DRAM controller + *****************************************************************************/ +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* + * Only initialize memory controller when running from FLASH. + * When running from RAM, don't touch it. + */ + if ((ulong) initdram & 0xff000000) { + volatile uint *addr1, *addr2; + uint i, j; + + upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl, + sizeof (edo_60ns_25MHz_tbl) / sizeof (uint)); + memctl->memc_mptpr = 0x0200; + memctl->memc_mamr = 0x0ca20330; + memctl->memc_or2 = -CFG_DRAM_MAX | OR_CSNT_SAM; + memctl->memc_br2 = CFG_DRAM_BASE | BR_MS_UPMA | BR_V; + /* + * Do 8 read accesses to DRAM + */ + addr1 = (volatile uint *) 0; + addr2 = (volatile uint *) 0x00400000; + for (i = 0, j = 0; i < 8; i++) + j = addr1[0]; + + /* + * Now check whether we got 4MB or 16MB populated + */ + addr1[0] = 0x12345678; + addr1[1] = 0x9abcdef0; + addr2[0] = 0xfeedc0de; + addr2[1] = 0x47110815; + if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) { + /* only 4MB populated */ + memctl->memc_or2 = -(CFG_DRAM_MAX / 4) | OR_CSNT_SAM; + } + } + + return -(memctl->memc_or2 & 0xffff0000); +} + +/***************************************************************************** + * prepare for FLASH detection + *****************************************************************************/ +void flash_preinit(void) +{ +} + +/***************************************************************************** + * finalize FLASH setup + *****************************************************************************/ +void flash_afterinit(uint bank, ulong start, ulong size) +{ +} + +/***************************************************************************** + * otherinits after RAM is there and we are relocated to RAM + * note: though this is an int function, nobody cares for the result! + *****************************************************************************/ +int misc_init_r (void) +{ + /* read 'factory' part of EEPROM */ + extern void read_factory_r (void); + read_factory_r (); + + return (0); +} diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds new file mode 100644 index 0000000..b3747e4 --- /dev/null +++ b/board/emk/top860/u-boot.lds @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug new file mode 100644 index 0000000..580575a --- /dev/null +++ b/board/emk/top860/u-boot.lds.debug @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ep7312/Makefile b/board/ep7312/Makefile new file mode 100644 index 0000000..c53a3c7 --- /dev/null +++ b/board/ep7312/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := ep7312.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ep7312/config.mk b/board/ep7312/config.mk new file mode 100644 index 0000000..0ae16a2 --- /dev/null +++ b/board/ep7312/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xc0f80000 diff --git a/board/ep7312/ep7312.c b/board/ep7312/ep7312.c new file mode 100644 index 0000000..11eab23 --- /dev/null +++ b/board/ep7312/ep7312.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Activate LED flasher */ + IO_LEDFLSH = 0x40; + + /* arch number MACH_TYPE_EDB7312 */ + gd->bd->bi_arch_number = MACH_TYPE_EDB7312; + + /* location of boot parameters */ + gd->bd->bi_boot_params = 0xc0020100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/ep7312/flash.c b/board/ep7312/flash.c new file mode 100644 index 0000000..272a9e5 --- /dev/null +++ b/board/ep7312/flash.c @@ -0,0 +1,341 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define FLASH_BANK_SIZE 0x1000000 +#define MAIN_SECT_SIZE 0x20000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F128J3 & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): + printf ("28F128J3 (128Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: ; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + int rc = ERR_OK; + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (INTEL_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + + *addr = 0x20; /* erase setup */ + *addr = 0xD0; /* erase confirm */ + + while ((*addr & 0x80) != 0x80) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + *addr = 0xB0; /* suspend erase */ + *addr = 0xFF; /* reset to read mode */ + rc = ERR_TIMOUT; + goto outahere; + } + } + + /* clear status register command */ + *addr = 0x50; + /* reset to read mode */ + *addr = 0xFF; + } + printf ("ok.\n"); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (flag) + enable_interrupts (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_word (flash_info_t * info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest, val; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased + */ + if ((*addr & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* clear status register command */ + *addr = 0x50; + + /* program set-up command */ + *addr = 0x40; + + /* latch address/data */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((val = *addr) & 0x80) != 0x80) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + rc = ERR_TIMOUT; + /* suspend program command */ + *addr = 0xB0; + goto outahere; + } + } + + if (val & 0x1A) { /* check for error */ + printf ("\nFlash write error %02x at address %08lx\n", + (int) val, (unsigned long) dest); + if (val & (1 << 3)) { + printf ("Voltage range error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + if (val & (1 << 1)) { + printf ("Device protect error.\n"); + rc = ERR_PROTECTED; + goto outahere; + } + if (val & (1 << 4)) { + printf ("Programming error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + rc = ERR_PROG_ERROR; + goto outahere; + } + + outahere: + /* read array command */ + *addr = 0xFF; + + if (flag) + enable_interrupts (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + ushort data; + int l; + int i, rc; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_word (info, wp, data); +} diff --git a/board/ep7312/lowlevel_init.S b/board/ep7312/lowlevel_init.S new file mode 100644 index 0000000..5dadb31 --- /dev/null +++ b/board/ep7312/lowlevel_init.S @@ -0,0 +1,95 @@ +/* + * Memory Setup stuff - taken from ??? + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +SYSCON1: .long 0x80000100 +SYSCON2: .long 0x80001100 +SYSCON3: .long 0x80002200 +MEMCFG1: .long 0x80000180 +MEMCFG2: .long 0x800001C0 +SDCONF: .long 0x80002300 +SDRFPR: .long 0x80002340 + +syscon1_val: .long 0x00040100 +syscon2_val: .long 0x00000102 +syscon3_val: .long 0x0000020E +memcfg1_val: .long 0x1f101710 +memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits +memcfg2_val: .long 0x00001f13 @ upper 16 bits are reserved for CS7 + CS6 +sdrfpr_val: .long 0x00000240 +sdconf_val: .long 0x00000522 +/* setting up the memory */ + +.globl lowlevel_init +lowlevel_init: + /* + * SYSCON1-3 + */ + ldr r0, SYSCON1 + ldr r1, syscon1_val + str r1, [r0] + + ldr r0, SYSCON2 + ldr r1, syscon2_val + str r1, [r0] + + ldr r0, SYSCON3 + ldr r1, syscon3_val + str r1, [r0] + + /* + * MEMCFG1 + */ + ldr r0, MEMCFG1 + ldr r1, memcfg1_val + str r1, [r0] + + /* + * MEMCFG2 + */ + ldr r0, MEMCFG2 + ldr r2, [r0] + ldr r1, memcfg2_mask + bic r2, r2, r1 + ldr r1, memcfg2_val + orr r2, r2, r1 + str r2, [r0] + + /* + * SDRFPR,SDCONF + */ + ldr r0, SDCONF + ldr r1, sdconf_val + str r1, [r0] + + ldr r0, SDRFPR + ldr r1, sdrfpr_val + str r1, [r0] + + /* everything is fine now */ + mov pc, lr diff --git a/board/ep7312/u-boot.lds b/board/ep7312/u-boot.lds new file mode 100644 index 0000000..1122d75 --- /dev/null +++ b/board/ep7312/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile new file mode 100644 index 0000000..8b10993 --- /dev/null +++ b/board/ep8248/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ep8248/config.mk b/board/ep8248/config.mk new file mode 100644 index 0000000..eda523b --- /dev/null +++ b/board/ep8248/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Yuli Barcohen, Arabella Software Ltd. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EP82xx series boards by Embedded Planet +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c new file mode 100644 index 0000000..69975ca --- /dev/null +++ b/board/ep8248/ep8248.c @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen + * + * Support for Embedded Planet EP8248 boards. + * Tested on EP8248E. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */ + /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ + /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */ + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ + /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ + /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + } +}; + +int board_early_init_f (void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + bcsr[4] |= 0x30; /* Turn the LEDs off */ + +#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC) + bcsr[6] |= 0x10; +#endif +#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC) + bcsr[7] |= 0x10; +#endif + +#if CFG_FCC1 + bcsr[8] |= 0xC0; +#endif /* CFG_FCC1 */ +#if CFG_FCC2 + bcsr[8] |= 0x30; +#endif /* CFG_FCC2 */ + + return 0; +} + +long int initdram(int board_type) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + long int msize = 16L << (bcsr[2] & 3); + +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; + uchar c = 0xFF; + uint psdmr = CFG_PSDMR; + int i; + + immap->im_siu_conf.sc_ppc_acr = 0x02; + immap->im_siu_conf.sc_ppc_alrh = 0x30126745; + immap->im_siu_conf.sc_tescr1 = 0x00004000; + + memctl->memc_mptpr = CFG_MPTPR; + + /* Initialise 60x bus SDRAM */ + memctl->memc_psrt = CFG_PSRT; + memctl->memc_or1 = CFG_SDRAM_OR; + memctl->memc_br1 = CFG_SDRAM_BR; + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + for (i = 0; i < 8; i++) + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ + *ramaddr = c; +#endif /* !CFG_RAMBOOT */ + + /* Return total 60x bus SDRAM size */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + puts("Board: "); + switch (bcsr[0]) { + case 0x0C: + printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]); + break; + default: + printf("unknown: ID=%02X\n", bcsr[0]); + } + + return 0; +} diff --git a/board/ep8248/u-boot.lds b/board/ep8248/u-boot.lds new file mode 100644 index 0000000..18c4b46 --- /dev/null +++ b/board/ep8248/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/ep8260/Makefile b/board/ep8260/Makefile new file mode 100644 index 0000000..477e5ee --- /dev/null +++ b/board/ep8260/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o mii_phy.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/ep8260/config.mk b/board/ep8260/config.mk new file mode 100644 index 0000000..eaf1560 --- /dev/null +++ b/board/ep8260/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EP8260 boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_ep8260.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# +#TEXT_BASE = 0x00100000 +#TEXT_BASE = 0xFF000000 +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c new file mode 100644 index 0000000..b9e1df4 --- /dev/null +++ b/board/ep8260/ep8260.c @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Frank Panno , Delphin Technology AG + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "ep8260.h" +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */ + /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */ + /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */ + /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */ + /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */ + /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */ + /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Setup CS4 to enable the Board Control/Status registers. + * Otherwise the smcs won't work. +*/ +int board_early_init_f (void) +{ + volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + + memctl->memc_br4 = CFG_BR4_PRELIM; + memctl->memc_or4 = CFG_OR4_PRELIM; + regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */ + regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */ + return 0; +} + +void reset_phy (void) +{ + volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE; + + regs->bcsr4 = 0xC0; +} + +/* + * Check Board Identity: + * I don' know, how the next board revisions will be coded. + * Thats why its a static interpretation ... +*/ + +int checkboard (void) +{ + volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE; + uint major = 0, minor = 0; + + switch (regs->bcsr0) { + case 0x02: + major = 1; + break; + case 0x03: + major = 1; + minor = 1; + break; + case 0x06: + major = 1; + minor = 3; + break; + default: + break; + } + printf ("Board: Embedded Planet EP8260, Revision %d.%d\n", + major, minor); + return 0; +} + + +/* ------------------------------------------------------------------------- */ + + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0; + volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110; + +/* + ulong psdmr = CFG_PSDMR; +#ifdef CFG_LSDRAM + ulong lsdmr = CFG_LSDMR; +#endif +*/ + long size = CFG_SDRAM0_SIZE; + int i; + + +/* +* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): +* +* "At system reset, initialization software must set up the +* programmable parameters in the memory controller banks registers +* (ORx, BRx, P/LSDMR). After all memory parameters are configured, +* system software should execute the following initialization sequence +* for each SDRAM device. +* +* 1. Issue a PRECHARGE-ALL-BANKS command +* 2. Issue eight CBR REFRESH commands +* 3. Issue a MODE-SET command to initialize the mode register +* +* The initial commands are executed by setting P/LSDMR[OP] and +* accessing the SDRAM with a single-byte transaction." +* +* The appropriate BRx/ORx registers have already been set when we +* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. +*/ + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + +#ifndef CFG_RAMBOOT +#ifdef CFG_LSDRAM + size += CFG_SDRAM1_SIZE; + ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c; + memctl->memc_lsrt = CFG_LSRT; + + memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; +#endif /* CFG_LSDRAM */ +#endif /* CFG_RAMBOOT */ + return (size * 1024 * 1024); +} diff --git a/board/ep8260/ep8260.h b/board/ep8260/ep8260.h new file mode 100644 index 0000000..3032b14 --- /dev/null +++ b/board/ep8260/ep8260.h @@ -0,0 +1,24 @@ +#ifndef __EP8260_H__ +#define __EP8260_H__ + +typedef struct tt_ep_regs { + volatile unsigned char bcsr0; + volatile unsigned char bcsr1; + volatile unsigned char bcsr2; + volatile unsigned char bcsr3; + volatile unsigned char bcsr4; + volatile unsigned char bcsr5; + volatile unsigned char bcsr6; + volatile unsigned char bcsr7; + volatile unsigned char bcsr8; + volatile unsigned char bcsr9; + volatile unsigned char bcsr10; + volatile unsigned char bcsr11; + volatile unsigned char bcsr12; + volatile unsigned char bcsr13; + volatile unsigned char bcsr14; + volatile unsigned char bcsr15; +} t_ep_regs; +typedef t_ep_regs *tp_ep_regs; + +#endif diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c new file mode 100644 index 0000000..278d606 --- /dev/null +++ b/board/ep8260/flash.c @@ -0,0 +1,411 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Frank Panno , Delphin Technology AG + * + * Flash Routines for AMD device AM29DL323DB on the EP8260 board. + * + * This file is based on board/tqm8260/flash.c. + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define V_ULONG(a) (*(volatile unsigned long *)( a )) +#define V_BYTE(a) (*(volatile unsigned char *)( a )) + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +/*----------------------------------------------------------------------- + */ +void flash_reset(void) +{ + if( flash_info[0].flash_id != FLASH_UNKNOWN ) { + V_ULONG( flash_info[0].start[0] ) = 0x00F000F0; + V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0; + } +} + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size( ulong baseaddr, flash_info_t *info ) +{ + short i; + unsigned long flashtest_h, flashtest_l; + + /* Write auto select command sequence and test FLASH answer */ + V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA; + V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055; + V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090; + V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA; + V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055; + V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090; + + flashtest_h = V_ULONG(baseaddr); /* manufacturer ID */ + flashtest_l = V_ULONG(baseaddr + 4); + + if ((int)flashtest_h == AMD_MANUFACT) { + info->flash_id = FLASH_MAN_AMD; + } else { + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + flashtest_h = V_ULONG(baseaddr + 8); /* device ID */ + flashtest_l = V_ULONG(baseaddr + 12); + if (flashtest_h != flashtest_l) { + info->flash_id = FLASH_UNKNOWN; + return(0); + } + + switch((int)flashtest_h) { + case AMD_ID_DL323B: + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x01000000; /* 4 * 4 MB = 16 MB */ + break; + case AMD_ID_LV640U: /* AMDLV640 and AMDLV641 have same ID */ + info->flash_id += FLASH_AMLV640U; + info->sector_count = 128; + info->size = 0x02000000; /* 4 * 8 MB = 32 MB */ + break; + default: + info->flash_id = FLASH_UNKNOWN; + return(0); /* no or unknown flash */ + } + + if(flashtest_h == AMD_ID_LV640U) { + /* set up sector start adress table (uniform sector type) */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = baseaddr + (i * 0x00040000); + } else { + /* set up sector start adress table (bottom sector type) */ + for (i = 0; i < 8; i++) { + info->start[i] = baseaddr + (i * 0x00008000); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000; + } + } + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) || + (V_ULONG( info->start[i] + 20 ) & 0x00010001)) { + info->protect[i] = 1; /* D0 = 1 if protected */ + } else { + info->protect[i] = 0; + } + } + + flash_reset(); + return(info->size); +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + int i; + + /* Init: no FLASHes known */ + for (i=0; i>20); + } + + /* + * protect monitor and environment sectors + */ + +#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case FLASH_MAN_AMD: printf ("AMD "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n"); + break; + case FLASH_AMLV640U: printf ("29LV640U (64 M, uniform sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; + V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; + V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080; + V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; + V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; + V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; + V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; + V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080; + V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; + V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; + udelay (1000); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + V_ULONG( info->start[sect] ) = 0x00300030; + V_ULONG( info->start[sect] + 4 ) = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 || + (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080) + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + flash_reset (); + + printf (" done\n"); + return 0; +} + +static int write_dword (flash_info_t *, ulong, unsigned char *); + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong dp; + static unsigned char bb[8]; + int i, l, rc, cc = cnt; + + dp = (addr & ~7); /* get lower dword aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - dp) != 0) { + for (i = 0; i < 8; i++) + bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++; + if ((rc = write_dword(info, dp, bb)) != 0) + { + return (rc); + } + dp += 8; + cc -= 8 - l; + } + + /* + * handle word aligned part + */ + while (cc >= 8) { + if ((rc = write_dword(info, dp, src)) != 0) { + return (rc); + } + dp += 8; + src += 8; + cc -= 8; + } + + if (cc <= 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + for (i = 0; i < 8; i++) { + bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i); + } + return (write_dword(info, dp, bb)); +} + +/*----------------------------------------------------------------------- + * Write a dword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata) +{ + ulong start; + ulong cl = 0, ch =0; + int flag, i; + + for (ch=0, i=0; i < 4; i++) + ch = (ch << 8) + *pdata++; /* high word */ + for (cl=0, i=0; i < 4; i++) + cl = (cl << 8) + *pdata++; /* low word */ + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & ch) != ch + ||(*((vu_long *)(dest + 4)) & cl) != cl) + { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; + V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; + V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0; + V_ULONG( dest ) = ch; + V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; + V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; + V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0; + V_ULONG( dest + 4 ) = cl; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) || + ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/ep8260/mii_phy.c b/board/ep8260/mii_phy.c new file mode 100644 index 0000000..813f020 --- /dev/null +++ b/board/ep8260/mii_phy.c @@ -0,0 +1,107 @@ +#include +#include +#include "ep8260.h" + +#define MII_MDIO 0x01 +#define MII_MDCK 0x02 +#define MII_MDIR 0x04 + +void +mii_discover_phy(void) +{ + int known; + unsigned short phy_reg; + unsigned long phy_id; + + known = 0; + printf("Discovering phy @ 0: "); + phy_id = mii_phy_read(2) << 16; + phy_id |= mii_phy_read(3); + if ((phy_id & 0xFFFFFC00) == 0x00137800) { + printf("Level One "); + if ((phy_id & 0x000003F0) == 0xE0) { + printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); + known = 1; + } + else printf("unknown type\n"); + } + else printf("unknown OUI = 0x%08lX\n", phy_id); + + phy_reg = mii_phy_read(1); + if (!(phy_reg & 0x0004)) printf("Link is down\n"); + if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); + if (phy_reg & 0x0002) printf("Jabber condition detected\n"); + if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); + + if (known) { + phy_reg = mii_phy_read(17); + if (phy_reg & 0x0400) + printf("Phy operating at %d MBit/s in %s-duplex mode\n", + phy_reg & 0x4000 ? 100 : 10, + phy_reg & 0x0200 ? "full" : "half"); + else + printf("bad link!!\n"); +/* +left off: no link, green 100MBit, yellow 10MBit +right off: no activity, green full-duplex, yellow half-duplex +*/ + mii_phy_write(20, 0x0452); + } +} + +unsigned short +mii_phy_read(unsigned short reg) +{ + int i; + unsigned short tmp, val = 0, adr = 0; + t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE; + + tmp = 0x6002 | (adr << 7) | (reg << 2); + regs->bcsr4 = 0xC3; + for (i = 0; i < 64; i++) { + regs->bcsr4 ^= MII_MDCK; + } + for (i = 0; i < 16; i++) { + regs->bcsr4 &= ~MII_MDCK; + if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; + else regs->bcsr4 &= ~MII_MDIO; + regs->bcsr4 |= MII_MDCK; + tmp <<= 1; + } + regs->bcsr4 |= MII_MDIR; + for (i = 0; i < 16; i++) { + val <<= 1; + regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); + if (regs->bcsr4 & MII_MDIO) val |= 1; + regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); + } + return val; +} + +void +mii_phy_write(unsigned short reg, unsigned short val) +{ + int i; + unsigned short tmp, adr = 0; + t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE; + + tmp = 0x5002 | (adr << 7) | (reg << 2); + regs->bcsr4 = 0xC3; + for (i = 0; i < 64; i++) { + regs->bcsr4 ^= MII_MDCK; + } + for (i = 0; i < 16; i++) { + regs->bcsr4 &= ~MII_MDCK; + if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; + else regs->bcsr4 &= ~MII_MDIO; + regs->bcsr4 |= MII_MDCK; + tmp <<= 1; + } + for (i = 0; i < 16; i++) { + regs->bcsr4 &= ~MII_MDCK; + if (val & 0x8000) regs->bcsr4 |= MII_MDIO; + else regs->bcsr4 &= ~MII_MDIO; + regs->bcsr4 |= MII_MDCK; + val <<= 1; + } +} diff --git a/board/ep8260/u-boot.lds b/board/ep8260/u-boot.lds new file mode 100644 index 0000000..4250e83 --- /dev/null +++ b/board/ep8260/u-boot.lds @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2001, 2002, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/opt/cross/lib); SEARCH_DIR(/opt/cross/powerpc-linux/lib); +/* SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); */ +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) +/* common/environment.o(.text) */ + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/eric/Makefile b/board/eric/Makefile new file mode 100644 index 0000000..f55e7e2 --- /dev/null +++ b/board/eric/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/eric/config.mk b/board/eric/config.mk new file mode 100644 index 0000000..dd0b412 --- /dev/null +++ b/board/eric/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFF80000 +TEXT_BASE = 0xFFFC0000 diff --git a/board/eric/eric.c b/board/eric/eric.c new file mode 100644 index 0000000..5413ae1 --- /dev/null +++ b/board/eric/eric.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "eric.h" +#include + +#define PPC405GP_GPIO0_OR 0xef600700 /* GPIO Output */ +#define PPC405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */ +#define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */ +#define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */ + +int board_early_init_f (void) +{ + + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the ERIC board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive + | IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive + | IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive + | indicates NO Power or HOST RESET active + | check GPIO7 (HOST RESET#) and GPIO8 (NO Power#) + | for real IRQ source + | IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive + | IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive + | -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting + | PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR, + | else tristate) + | Note for ERIC board: + | An interrupt taken for the HOST (IRQ 28) indicates that + | the HOST wrote a "1" to one of the following locations + | - VGA CRT_GPIO0 (if R1216 is loaded) + | - VGA CRT_GPIO1 (if R1217 is loaded) + | + +-------------------------------------------------------------------------*/ + + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all SMI to be non-critical */ + mtdcr (uicpr, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */ + mtdcr (uictr, 0x10000000); /* set int trigger levels, UART0 is EDGE */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ + + out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */ + out32 (PPC405GP_GPIO0_TCR, 0x7E400000); + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char *s = getenv ("serial#"); + char *e; + + puts ("Board: "); + + if (!s || strncmp (s, "ERIC", 9)) { + puts ("### No HW ID - assuming ERIC"); + } else { + for (e = s; *e; ++e) { + if (*e == ' ') + break; + } + + for (; s < e; ++s) { + putc (*s); + } + } + + + putc ('\n'); + + return (0); +} + + +/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- */ +/* + initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of + the necessary info for SDRAM controller configuration +*/ +/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- */ +long int initdram (int board_type) +{ +#ifndef CONFIG_ERIC + int i; + unsigned char datain[128]; + int TotalSize; +#endif + + +#ifdef CONFIG_ERIC + /* + * we have no EEPROM on ERIC + * so let init.S do the init job for SDRAM + * and simply return 32MByte here + */ + return (CFG_SDRAM_SIZE * 1024 * 1024); +#else + + /* Read Serial Presence Detect Information */ + for (i = 0; i < 128; i++) + datain[i] = 127; + i2c_send (SPD_EEPROM_ADDRESS, 0, 1, datain, 128); + printf ("\nReading DIMM...\n"); +#if 0 + for (i = 0; i < 128; i++) { + printf ("%d=0x%x ", i, datain[i]); + if (((i + 1) % 10) == 0) + printf ("\n"); + } + printf ("\n"); +#endif + + /*****************************/ + /* Retrieve interesting data */ + /*****************************/ + /* size of a SDRAM bank */ + /* Number of bytes per side / number of banks per side */ + if (datain[31] == 0x08) + TotalSize = 32; + else if (datain[31] == 0x10) + TotalSize = 64; + else { + printf ("IIC READ ERROR!!!\n"); + TotalSize = 32; + } + + /* single-sided DIMM or double-sided DIMM? */ + if (datain[5] != 1) { + /* double-sided DIMM => SDRAM banks 0..3 are valid */ + printf ("double-sided DIMM\n"); + TotalSize *= 2; + } + /* else single-sided DIMM => SDRAM bank 0 and bank 2 are valid */ + else { + printf ("single-sided DIMM\n"); + } + + + /* return size in Mb unit => *(1024*1024) */ + return (TotalSize * 1024 * 1024); +#endif +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: xxx MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/eric/eric.h b/board/eric/eric.h new file mode 100644 index 0000000..b50d521 --- /dev/null +++ b/board/eric/eric.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/board/eric/flash.c b/board/eric/flash.c new file mode 100644 index 0000000..c08a760 --- /dev/null +++ b/board/eric/flash.c @@ -0,0 +1,1128 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +#ifdef CFG_FLASH_16BIT +#define FLASH_WORD_SIZE unsigned short +#define FLASH_ID_MASK 0xFFFF +#else +#define FLASH_WORD_SIZE unsigned long +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +/* stolen from esteem192e/flash.c */ +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); + +#ifndef CFG_FLASH_16BIT +static int write_word (flash_info_t *info, ulong dest, ulong data); +#else +static int write_short (flash_info_t *info, ulong dest, ushort data); +#endif +static void flash_get_offsets (ulong base, flash_info_t *info); + + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i=0; iflash_id & FLASH_TYPEMASK) == FLASH_28F320J3A || + (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A || + (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * info->size/info->sector_count); + } + } else if (info->flash_id & FLASH_BTYPE) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CFG_FLASH_16BIT + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00008000; + info->start[3] = base + 0x0000C000; + info->start[4] = base + 0x00010000; + info->start[5] = base + 0x00014000; + info->start[6] = base + 0x00018000; + info->start[7] = base + 0x0001C000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x000E0000; + } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } +#else + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000A000; + info->start[6] = base + 0x0000C000; + info->start[7] = base + 0x0000E000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00070000; + } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } +#endif + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CFG_FLASH_16BIT + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00014000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x0001C000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + + } else { + + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +#else + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000A000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x0000E000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + + } else { + + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } +#endif + } + + +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar botboot[]=", bottom boot sect)\n"; + uchar topboot[]=", top boot sector)\n"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + if (info->flash_id & 0x0001 ) { + boottype = botboot; + } else { + boottype = topboot; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype); + break; + case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype); + break; + case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype); + break; + case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype); + break; + case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype); + break; + case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype); + break; + case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype); + break; + +#if 0 /* enable when devices are available */ + + case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype); + break; + case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype); + break; +#endif + case FLASH_28F320J3A: printf ("INTEL28F320J3A (32 Mbit%s",boottype); + break; + case FLASH_28F640J3A: printf ("INTEL28F640J3A (64 Mbit%s",boottype); + break; + case FLASH_28F128J3A: printf ("INTEL28F128J3A (128 Mbit%s",boottype); + break; + + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) +{ + short i; + ulong base = (ulong)addr; + FLASH_WORD_SIZE value; + + /* Write auto select command: read Manufacturer ID */ + + +#ifndef CFG_FLASH_16BIT + + /* + * Note: if it is an AMD flash and the word at addr[0000] + * is 0x00890089 this routine will think it is an Intel + * flash device and may(most likely) cause trouble. + */ + + addr[0x0000] = 0x00900090; + if(addr[0x0000] != 0x00890089){ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; +#else + + /* + * Note: if it is an AMD flash and the word at addr[0000] + * is 0x0089 this routine will think it is an Intel + * flash device and may(most likely) cause trouble. + */ + + addr[0x0000] = 0x0090; + + if(addr[0x0000] != 0x0089){ + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0090; +#endif + } + value = addr[0]; + + switch (value) { + case (AMD_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_FUJ; + break; + case (STM_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_STM; + break; + case (SST_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_SST; + break; + case (INTEL_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + + } + + value = addr[1]; /* device ID */ + + switch (value) { + + case (AMD_ID_LV400T & FLASH_ID_MASK): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV400B & FLASH_ID_MASK): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800T & FLASH_ID_MASK): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV800B & FLASH_ID_MASK): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160T & FLASH_ID_MASK): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV160B & FLASH_ID_MASK): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & FLASH_ID_MASK): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (AMD_ID_LV320B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + + case (INTEL_ID_28F800B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL800T; + info->sector_count = 23; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (INTEL_ID_28F800B3B & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (INTEL_ID_28F160B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL160T; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (INTEL_ID_28F160B3B & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (INTEL_ID_28F320B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL320T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (INTEL_ID_28F320B3B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + +#if 0 /* enable when devices are available */ + case (INTEL_ID_28F320B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL320T; + info->sector_count = 135; + info->size = 0x01000000; + break; /* => 16 MB */ + + case (INTEL_ID_28F320B3B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 135; + info->size = 0x01000000; + break; /* => 16 MB */ +#endif + case (INTEL_ID_28F320J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 32 MBit */ + case (INTEL_ID_28F640J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 64 MBit */ + case (INTEL_ID_28F128J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 128 MBit */ + + default: + /* FIXME*/ + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets(base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){ + *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { + *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ + } + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + + volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); + int flag, prot, sect, l_sect, barf; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + ((info->flash_id > FLASH_AMD_COMP) && + ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){ + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + if(info->flash_id < FLASH_AMD_COMP) { +#ifndef CFG_FLASH_16BIT + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; +#else + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0080; + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; +#endif + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); + addr[0] = (0x00300030 & FLASH_ID_MASK); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); + while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != + (0x00800080&FLASH_ID_MASK) ) + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + barf = 0; +#ifndef CFG_FLASH_16BIT + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00200020; + addr[0] = 0x00D000D0; + while(!(addr[0] & 0x00800080)); /* wait for error or finish */ + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; + } + } +#else + addr = (vu_short*)(info->start[sect]); + addr[0] = 0x0020; + addr[0] = 0x00D0; + while(!(addr[0] & 0x0080)); /* wait for error or finish */ + if( addr[0] & 0x003A) /* check for error */ + barf = addr[0] & 0x003A; +#endif + if(barf) { + printf("\nFlash error in sector at %lx\n",(unsigned long)addr); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if((barf & 0x0030) == 0x0030) + printf("Command Sequence error.\n"); + if((barf & 0x0030) == 0x0020) + printf("Block Erase error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + rcode = 1; + } else printf("."); + l_sect = sect; + } + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ + + } + + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ + +/*flash_info_t *addr2info (ulong addr) +{ + flash_info_t *info; + int i; + + for (i=0, info=&flash_info[0]; i= info->start[0]) && + (addr < (info->start[0] + info->size)) ) { + return (info); + } + } + + return (NULL); +} +*/ +/*----------------------------------------------------------------------- + * Copy memory to flash. + * Make sure all target addresses are within Flash bounds, + * and no protected sectors are hit. + * Returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - target range includes protected sectors + * 8 - target address not in Flash memory + */ + +/*int flash_write (uchar *src, ulong addr, ulong cnt) +{ + int i; + ulong end = addr + cnt - 1; + flash_info_t *info_first = addr2info (addr); + flash_info_t *info_last = addr2info (end ); + flash_info_t *info; + + if (cnt == 0) { + return (0); + } + + if (!info_first || !info_last) { + return (8); + } + + for (info = info_first; info <= info_last; ++info) { + ulong b_end = info->start[0] + info->size;*/ /* bank end addr */ +/* short s_end = info->sector_count - 1; + for (i=0; isector_count; ++i) { + ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; + + if ((end >= info->start[i]) && (addr < e_addr) && + (info->protect[i] != 0) ) { + return (4); + } + } + } + +*/ /* finally write data to flash */ +/* for (info = info_first; info <= info_last && cnt>0; ++info) { + ulong len; + + len = info->start[0] + info->size - addr; + if (len > cnt) + len = cnt; + if ((i = write_buff(info, src, addr, len)) != 0) { + return (i); + } + cnt -= len; + addr += len; + src += len; + } + return (0); +} +*/ +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ +#ifndef CFG_FLASH_16BIT + ulong cp, wp, data; + int l; +#else + ulong cp, wp; + ushort data; +#endif + int i, rc; + +#ifndef CFG_FLASH_16BIT + + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); + +#else + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start byte + */ + if (addr - wp) { + data = 0; + data = (data << 8) | *src++; + --cnt; + if ((rc = write_short(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ +/* l = 0; used for debuging */ + while (cnt >= 2) { + data = 0; + for (i=0; i<2; ++i) { + data = (data << 8) | *src++; + } + +/* if(!l){ + printf("%x",data); + l = 1; + } used for debuging */ + + if ((rc = write_short(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<2; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_short(info, wp, data)); + + +#endif +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifndef CFG_FLASH_16BIT +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start,barf; + int flag; + + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if(info->flash_id > FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + } else { + /* intel stuff */ + *addr = 0x00400040; + } + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + + if(info->flash_id > FLASH_AMD_COMP) { + + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + } else { + + while(!(addr[0] & 0x00800080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; + } + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + + + } + + return (0); + +} + +#else + +static int write_short (flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short*)(info->start[0]); + ulong start,barf; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_short *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x00A0; + } else { + /* intel stuff */ + *addr = 0x00D0; + *addr = 0x0040; + } + *((vu_short *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + } else { + /* intel stuff */ + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + + if( addr[0] & 0x003A) { /* check for error */ + barf = addr[0] & 0x003A; + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + *addr = 0x00B0; + *addr = 0x0070; + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + + *addr = 0x00FF; + + } + + return (0); + +} + + +#endif + +/*----------------------------------------------------------------------- + */ diff --git a/board/eric/init.S b/board/eric/init.S new file mode 100644 index 0000000..9d4e7ff --- /dev/null +++ b/board/eric/init.S @@ -0,0 +1,355 @@ +/*------------------------------------------------------------------------------+ */ +/* */ +/* This source code has been made available to you by IBM on an AS-IS */ +/* basis. Anyone receiving this source is licensed under IBM */ +/* copyrights to use it in any way he or she deems fit, including */ +/* copying it, modifying it, compiling it, and redistributing it either */ +/* with or without modifications. No license under IBM patents or */ +/* patent applications is to be implied by the copyright license. */ +/* */ +/* Any user of this software should understand that IBM cannot provide */ +/* technical support for this software and will not be responsible for */ +/* any consequences resulting from the use of this software. */ +/* */ +/* Any person who transfers this source code or any derivative work */ +/* must include the IBM copyright notice, this paragraph, and the */ +/* preceding two paragraphs in the transferred software. */ +/* */ +/* COPYRIGHT I B M CORPORATION 1995 */ +/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ +/*------------------------------------------------------------------------------- */ + +/*----------------------------------------------------------------------------- */ +/* Function: ext_bus_cntlr_init */ +/* Description: Initializes the External Bus Controller for the external */ +/* peripherals. IMPORTANT: For pass1 this code must run from */ +/* cache since you can not reliably change a peripheral banks */ +/* timing register (pbxap) while running code from that bank. */ +/* For ex., since we are running from ROM on bank 0, we can NOT */ +/* execute the code that modifies bank 0 timings from ROM, so */ +/* we run it from cache. */ +/* */ +/*----------------------------------------------------------------------------- */ +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + mflr r4 /* save link register */ + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 10; used to prefetch */ + mtctr r4 /* 10 cache lines to fit this function */ + /* in cache (gives us 8x10=80 instrctns) */ +..ebcloop: + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 10 cache lines */ + + /*------------------------------------------------------------------- */ + /* Delay to ensure all accesses to ROM are complete before changing */ + /* bank 0 timings. 200usec should be enough. */ + /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ + /*------------------------------------------------------------------- */ + addis r3,0,0x0 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + /*----------------------------------------------------------------------- */ + /* Memory Bank 0 (Flash) initialization (from openbios) */ + /*----------------------------------------------------------------------- */ + + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,CS0_AP@h + ori r4,r4,CS0_AP@l + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + addis r4,0,CS0_CR@h + ori r4,r4,CS0_CR@l + mtdcr ebccfgd,r4 + + /*----------------------------------------------------------------------- */ + /* Memory Bank 1 (NVRAM/RTC) initialization */ + /*----------------------------------------------------------------------- */ + + addi r4,0,pb1ap + mtdcr ebccfga,r4 + addis r4,0,CS1_AP@h + ori r4,r4,CS1_AP@l + mtdcr ebccfgd,r4 + + addi r4,0,pb1cr + mtdcr ebccfga,r4 + addis r4,0,CS1_CR@h + ori r4,r4,CS1_CR@l + mtdcr ebccfgd,r4 + + /*----------------------------------------------------------------------- */ + /* Memory Bank 2 (A/D converter) initialization */ + /*----------------------------------------------------------------------- */ + + addi r4,0,pb2ap + mtdcr ebccfga,r4 + addis r4,0,CS2_AP@h + ori r4,r4,CS2_AP@l + mtdcr ebccfgd,r4 + + addi r4,0,pb2cr + mtdcr ebccfga,r4 + addis r4,0,CS2_CR@h + ori r4,r4,CS2_CR@l + mtdcr ebccfgd,r4 + + /*----------------------------------------------------------------------- */ + /* Memory Bank 3 (Ethernet PHY Reset) initialization */ + /*----------------------------------------------------------------------- */ + + addi r4,0,pb3ap + mtdcr ebccfga,r4 + addis r4,0,CS3_AP@h + ori r4,r4,CS3_AP@l + mtdcr ebccfgd,r4 + + addi r4,0,pb3cr + mtdcr ebccfga,r4 + addis r4,0,CS3_CR@h + ori r4,r4,CS3_CR@l + mtdcr ebccfgd,r4 + + /*----------------------------------------------------------------------- */ + /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */ + /*----------------------------------------------------------------------- */ + + addi r4,0,pb4ap + mtdcr ebccfga,r4 + addis r4,0,CS4_AP@h + ori r4,r4,CS4_AP@l + mtdcr ebccfgd,r4 + + addi r4,0,pb4cr + mtdcr ebccfga,r4 + addis r4,0,CS4_CR@h + ori r4,r4,CS4_CR@l + mtdcr ebccfgd,r4 + + /*----------------------------------------------------------------------- */ + /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */ + /*----------------------------------------------------------------------- */ + + addi r4,0,pb5ap + mtdcr ebccfga,r4 + addis r4,0,CS5_AP@h + ori r4,r4,CS5_AP@l + mtdcr ebccfgd,r4 + + addi r4,0,pb5cr + mtdcr ebccfga,r4 + addis r4,0,CS5_CR@h + ori r4,r4,CS5_CR@l + mtdcr ebccfgd,r4 + + /*----------------------------------------------------------------------- */ + /* Memory Bank 6 (CPU LED0) initialization */ + /*----------------------------------------------------------------------- */ + + addi r4,0,pb6ap + mtdcr ebccfga,r4 + addis r4,0,CS6_AP@h + ori r4,r4,CS6_AP@l + mtdcr ebccfgd,r4 + + addi r4,0,pb6cr + mtdcr ebccfga,r4 + addis r4,0,CS6_CR@h + ori r4,r4,CS5_CR@l + mtdcr ebccfgd,r4 + + /*----------------------------------------------------------------------- */ + /* Memory Bank 7 (CPU LED1) initialization */ + /*----------------------------------------------------------------------- */ + + addi r4,0,pb7ap + mtdcr ebccfga,r4 + addis r4,0,CS7_AP@h + ori r4,r4,CS7_AP@l + mtdcr ebccfgd,r4 + + addi r4,0,pb7cr + mtdcr ebccfga,r4 + addis r4,0,CS7_CR@h + ori r4,r4,CS7_CR@l + mtdcr ebccfgd,r4 + +/* addis r4,r0,FPGA_BRDC@h */ +/* ori r4,r4,FPGA_BRDC@l */ +/* lbz r3,0(r4) /###*get FPGA board control reg */ +/* eieio */ +/* ori r3,r3,0x01 /###*set UART1 control to select CTS/RTS */ +/* stb r3,0(r4) */ + + nop /* pass2 DCR errata #8 */ + blr + +/*----------------------------------------------------------------------------- */ +/* Function: sdram_init */ +/* Description: Configures SDRAM memory banks on ERIC. */ +/* We do manually init our SDRAM. */ +/* If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */ +/* It is assumed that a 32MB 12x8(2) SDRAM is used. */ +/*----------------------------------------------------------------------------- */ + .globl sdram_init + +sdram_init: + + mflr r31 + +#ifdef CFG_SDRAM_MANUALLY + /*------------------------------------------------------------------- */ + /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */ + /*------------------------------------------------------------------- */ + + addi r4,0,mem_mb0cf + mtdcr memcfga,r4 + addis r4,0,MB0CF@h + ori r4,r4,MB0CF@l + mtdcr memcfgd,r4 + + /*------------------------------------------------------------------- */ + /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */ + /*------------------------------------------------------------------- */ + + addi r4,0,mem_mb1cf + mtdcr memcfga,r4 + addis r4,0,MB1CF@h + ori r4,r4,MB1CF@l + mtdcr memcfgd,r4 + + /*------------------------------------------------------------------- */ + /* Set MB2CF for bank 2. off */ + /*------------------------------------------------------------------- */ + + addi r4,0,mem_mb2cf + mtdcr memcfga,r4 + addis r4,0,MB2CF@h + ori r4,r4,MB2CF@l + mtdcr memcfgd,r4 + + /*------------------------------------------------------------------- */ + /* Set MB3CF for bank 3. off */ + /*------------------------------------------------------------------- */ + + addi r4,0,mem_mb3cf + mtdcr memcfga,r4 + addis r4,0,MB3CF@h + ori r4,r4,MB3CF@l + mtdcr memcfgd,r4 + + /*------------------------------------------------------------------- */ + /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ + /* To set the appropriate timings, we need to know the SDRAM speed. */ + /* We can use the PLB speed since the SDRAM speed is the same as */ + /* the PLB speed. The PLB speed is the FBK divider times the */ + /* 405GP reference clock, which on the Walnut board is 33Mhz. */ + /* Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is */ + /* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */ + /* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */ + /* maybe 133Mhz. */ + /*------------------------------------------------------------------- */ + + mfdcr r5,strap /* determine FBK divider */ + /* via STRAP reg to calc PLB speed. */ + /* SDRAM speed is the same as the PLB */ + /* speed. */ + rlwinm r4,r5,4,0x3 /* get FBK divide bits */ + +..chk_66: + cmpi %cr0,0,r4,0x1 + bne ..chk_100 + addis r6,0,SDTR_66@h /* SDTR1 value for 66Mhz */ + ori r6,r6,SDTR_66@l + addis r7,0,RTR_66 /* RTR value for 66Mhz */ + b ..sdram_ok +..chk_100: + cmpi %cr0,0,r4,0x2 + bne ..chk_133 + addis r6,0,SDTR_100@h /* SDTR1 value for 100Mhz */ + ori r6,r6,SDTR_100@l + addis r7,0,RTR_100 /* RTR value for 100Mhz */ + b ..sdram_ok +..chk_133: + addis r6,0,0x0107 /* SDTR1 value for 133Mhz */ + ori r6,r6,0x4015 + addis r7,0,0x07F0 /* RTR value for 133Mhz */ + +..sdram_ok: + /*------------------------------------------------------------------- */ + /* Set SDTR1 */ + /*------------------------------------------------------------------- */ + addi r4,0,mem_sdtr1 + mtdcr memcfga,r4 + mtdcr memcfgd,r6 + + /*------------------------------------------------------------------- */ + /* Set RTR */ + /*------------------------------------------------------------------- */ + addi r4,0,mem_rtr + mtdcr memcfga,r4 + mtdcr memcfgd,r7 + + /*------------------------------------------------------------------- */ + /* Delay to ensure 200usec have elapsed since reset. Assume worst */ + /* case that the core is running 200Mhz: */ + /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ + /*------------------------------------------------------------------- */ + addis r3,0,0x0000 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 +..spinlp2: + bdnz ..spinlp2 /* spin loop */ + + /*------------------------------------------------------------------- */ + /* Set memory controller options reg, MCOPT1. */ + /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ + /* read/prefetch. */ + /*------------------------------------------------------------------- */ + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x8080 /* set DC_EN=1 */ + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + /*------------------------------------------------------------------- */ + /* Delay to ensure 10msec have elapsed since reset. This is */ + /* required for the MPC952 to stabalize. Assume worst */ + /* case that the core is running 200Mhz: */ + /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */ + /* This delay should occur before accessing SDRAM. */ + /*------------------------------------------------------------------- */ + addis r3,0,0x001E + ori r3,r3,0x8480 /* ensure 10msec have passed since reset */ + mtctr r3 +..spinlp3: + bdnz ..spinlp3 /* spin loop */ + +#else +/*fixme: do SDRAM Autoconfig from EEPROM here */ + +#endif + mtlr r31 /* restore lr */ + blr diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds new file mode 100644 index 0000000..4a0e5b4 --- /dev/null +++ b/board/eric/u-boot.lds @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/eric/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile new file mode 100644 index 0000000..67cf29b --- /dev/null +++ b/board/esd/adciop/Makefile @@ -0,0 +1,47 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/pci.o + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c new file mode 100644 index 0000000..7a11a12 --- /dev/null +++ b/board/esd/adciop/adciop.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "adciop.h" + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +/* ------------------------------------------------------------------------- */ + + +int board_early_init_f (void) +{ + /* + * Set port pin in escc2 to keep living, and configure user led output + */ + *(unsigned char *) 0x2000033e = 0x77; /* ESCC2: PCR bit3=pwr on, bit7=led out */ + *(unsigned char *) 0x2000033c = 0x88; /* ESCC2: PVR pwr on, led off */ + + /* + * Init pci regs + */ + *(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */ + *(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */ + *(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */ + *(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */ + *(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */ + *(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */ + *(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */ + + return 0; +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (!i || strncmp (str, "ADCIOP", 6)) { + puts ("### No HW ID - assuming ADCIOP\n"); + return (1); + } + + puts (str); + + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + return (16 * 1024 * 1024); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/adciop/adciop.h b/board/esd/adciop/adciop.h new file mode 100644 index 0000000..5fc313a --- /dev/null +++ b/board/esd/adciop/adciop.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/board/esd/adciop/config.mk b/board/esd/adciop/config.mk new file mode 100644 index 0000000..747f29f --- /dev/null +++ b/board/esd/adciop/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +# FLASH: +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFFD0000 + +# SDRAM: +#TEXT_BASE = 0x00FE0000 diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c new file mode 100644 index 0000000..d9eccba --- /dev/null +++ b/board/esd/adciop/flash.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + + flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM+size_b0-monitor_flash_len, + FLASH_BASE0_PRELIM+size_b0-1, + &flash_info[0]); + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(FLASH_BASE0_PRELIM + size_b0), + &flash_info[1]); + + flash_get_offsets (FLASH_BASE0_PRELIM + size_b0, &flash_info[1]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len, + FLASH_BASE0_PRELIM+size_b0+size_b1-1, + &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + flash_protect(FLAG_PROTECT_CLEAR, + FLASH_BASE0_PRELIM+size_b0-monitor_flash_len, + FLASH_BASE0_PRELIM+size_b0-1, + &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} diff --git a/board/esd/adciop/u-boot.lds b/board/esd/adciop/u-boot.lds new file mode 100644 index 0000000..ef937dd --- /dev/null +++ b/board/esd/adciop/u-boot.lds @@ -0,0 +1,139 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile new file mode 100644 index 0000000..8529ec7 --- /dev/null +++ b/board/esd/apc405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o strataflash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c new file mode 100644 index 0000000..4b2b07a --- /dev/null +++ b/board/esd/apc405/apc405.c @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#if 0 +#define FPGA_DEBUG +#endif + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); + +/* fpga configuration data - gzip compressed and generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); + + +#ifdef CONFIG_LCD_USED +/* logo bitmap data - gzip compressed and generated by bin2c */ +unsigned char logo_bmp[] = +{ +#include CFG_LCD_LOGO_NAME +}; + +/* + * include common lcd code (for esd boards) + */ +#include "../common/lcd.c" + +#include CFG_LCD_HEADER_NAME +#endif /* CONFIG_LCD_USED */ + + +int board_revision(void) +{ + unsigned long cntrl0Reg; + unsigned long value; + + /* + * Get version of APC405 board from GPIO's + */ + + /* + * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x03000000); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ + + /* + * Restore GPIO settings + */ + mtdcr(cntrl0, cntrl0Reg); + + switch (value) { + case 0x00180000: + /* CS2==1 && CS3==1 -> version <= 1.2 */ + return 2; + case 0x00080000: + /* CS2==0 && CS3==1 -> version 1.3 */ + return 3; +#if 0 /* not yet manufactured ! */ + case 0x00100000: + /* CS2==1 && CS3==0 -> version 1.4 */ + return 4; + case 0x00000000: + /* CS2==0 && CS3==0 -> version 1.5 */ + return 5; +#endif + default: + /* should not be reached! */ + return 0; + } +} + + +int board_early_init_f (void) +{ + /* + * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) + */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ + out32(GPIO0_OR, 0); /* pull prg low */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ +#if 1 /* test-only */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ +#else + mtebc (epcr, 0x28400000); /* ebc in high-z */ +#endif + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile unsigned short *fpga_mode = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *fpga_ctrl2 = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); + volatile unsigned char *duart0_mcr = + (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = + (unsigned char *)((ulong)DUART1_BA + 4); + volatile unsigned short *fuji_lcdbl_pwm = + (unsigned short *)((ulong)0xf0100200 + 0xa0); + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + unsigned long cntrl0Reg; + + /* + * Setup GPIO pins (CS6+CS7 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00300000); + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + /* restore gpio/cs settings */ + mtdcr(cntrl0, cntrl0Reg); + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); + + /* + * Reset FPGA via FPGA_DATA pin + */ + SET_FPGA(FPGA_PRG | FPGA_CLK); + udelay(1000); /* wait 1ms */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); + udelay(1000); /* wait 1ms */ + + /* + * Write board revision in FPGA + */ + *fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f); + + /* + * Enable power on PS/2 interface (with reset) + */ + *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; + for (i=0;i<100;i++) + udelay(1000); + udelay(1000); + *fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET; + + /* + * Enable interrupts in exar duart mcr[3] + */ + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; + + /* + * Init lcd interface and display logo + */ + lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + regs_13806_640_480_16bpp, + sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), + logo_bmp, sizeof(logo_bmp)); + + /* + * Reset microcontroller and setup backlight PWM controller + */ + *fpga_mode |= 0x0014; + for (i=0;i<10;i++) + udelay(1000); + *fpga_mode |= 0x001c; + *fuji_lcdbl_pwm = 0x00ff; + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming APC405"); + } else { + puts(str); + } + + gd->board_type = board_revision(); + printf(", Rev 1.%ld\n", gd->board_type); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_IDE_RESET + +void ide_set_reset(int on) +{ + volatile unsigned short *fpga_mode = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { /* assert RESET */ + *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + } else { /* release RESET */ + *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + } +} + +#endif /* CONFIG_IDE_RESET */ + +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/apc405/config.mk b/board/esd/apc405/config.mk new file mode 100644 index 0000000..11faad2 --- /dev/null +++ b/board/esd/apc405/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ABG405 boards +# + +TEXT_BASE = 0xFFF80000 diff --git a/board/esd/apc405/fpgadata.c b/board/esd/apc405/fpgadata.c new file mode 100644 index 0000000..c31625a --- /dev/null +++ b/board/esd/apc405/fpgadata.c @@ -0,0 +1,2280 @@ + 0x1f,0x8b,0x08,0x08,0x30,0x6a,0x41,0x42,0x00,0x03,0x61,0x62,0x67,0x34,0x30,0x35, + 0x5f,0x31,0x5f,0x30,0x32,0x2e,0x62,0x69,0x74,0x00,0xed,0xbd,0x0b,0x74,0x1c,0xd5, + 0x95,0x2e,0xbc,0xeb,0x54,0x49,0x2e,0x75,0xb7,0xd4,0xa5,0x87,0x89,0x00,0x63,0x4a, + 0x2d,0xd9,0xb4,0x3d,0x6d,0xb9,0x2d,0x1b,0x59,0x08,0x59,0x2a,0x3d,0x20,0x1d,0xec, + 0x60,0x41,0x98,0xc4,0x93,0x9f,0xcb,0x34,0xc4,0xc9,0x78,0xb2,0x9c,0x5c,0x43,0x72, + 0xe7,0x3a,0x8f,0x21,0x47,0x0f,0xdb,0x6d,0xcb,0xe0,0xb6,0x71,0x12,0x67,0xe2,0x24, + 0xed,0x07,0x60,0x88,0x27,0xd3,0x96,0x0d,0x96,0x31,0x81,0x92,0x11,0x20,0x1b,0x61, + 0x2b,0x84,0x49,0xcc,0x23,0xd0,0x26,0x82,0x08,0x22,0x8c,0x30,0x0e,0x91,0xdf,0xff, + 0xde,0xa7,0xba,0xaa,0xab,0x65,0x67,0xee,0xcc,0xbd,0x97,0xb5,0xfe,0xf5,0xaf,0x74, + 0xd6,0x4c,0x76,0xaa,0x8e,0x4b,0x55,0xa7,0x4e,0xed,0xfd,0x9d,0xbd,0xbf,0xbd,0x37, + 0xe4,0xf9,0x47,0xad,0xff,0x00,0x48,0x77,0x82,0x76,0xe7,0x5d,0xff,0x30,0x27,0x7c, + 0xed,0xdf,0xcf,0xfa,0xfb,0x70,0x55,0xe5,0xd7,0xbf,0xb4,0x18,0xee,0x02,0x4f,0xd5, + 0x37,0xae,0x0d,0x7f,0xe5,0x1f,0xaa,0xae,0xad,0x86,0x2f,0x81,0xb7,0x2a,0x1c,0xbe, + 0x76,0x66,0x78,0xf6,0xcc,0xaa,0xd9,0xb0,0x18,0xf2,0x66,0xcd,0xa9,0x0d,0xd7,0xd4, + 0x86,0x67,0xc1,0x97,0x41,0x2a,0xf4,0x5d,0xc0,0xdf,0xa3,0x3f,0xfa,0xdb,0xaf,0x84, + 0x81,0x4b,0x00,0x30,0x21,0x2c,0x45,0xe9,0xbf,0xbd,0x61,0x49,0x97,0x80,0x37,0xcc, + 0x08,0x83,0x49,0xff,0x1b,0xd2,0xe7,0xf3,0xc2,0xa0,0xbb,0xff,0xb7,0x14,0x06,0x03, + 0x5a,0xa1,0x5e,0x81,0x22,0xf8,0x5f,0xff,0x24,0x50,0xb8,0x2d,0xff,0x57,0xc7,0xb3, + 0xff,0xc4,0x78,0xfc,0xfd,0x6f,0x8f,0xff,0xcf,0xdc,0x0f,0x80,0xf2,0xbf,0x3d,0x5e, + 0xfb,0xcf,0x8d,0xb7,0x85,0x0b,0x1a,0xfe,0x8b,0x1c,0x90,0x68,0x76,0x4b,0xfe,0x92, + 0x60,0x34,0xf4,0xd9,0xd7,0x37,0x73,0xce,0xc3,0x05,0xde,0x90,0xf2,0x9f,0x95,0xbf, + 0xc5,0x5f,0x08,0xef,0x1d,0x58,0x30,0xd6,0xfc,0x12,0xfb,0x00,0xe6,0xa6,0xfc,0xfd, + 0xf2,0xbd,0xd0,0xd7,0x3e,0xfb,0xb0,0x6f,0x4c,0x1e,0x85,0x65,0xe9,0xf1,0x5c,0x3b, + 0x0e,0xfb,0x79,0x65,0xca,0x1b,0x66,0xff,0x68,0xac,0xbb,0xa7,0x7c,0x40,0xed,0xc9, + 0x7d,0x07,0xd6,0xf1,0x40,0xca,0x1b,0x63,0x21,0xd8,0xc1,0x03,0x83,0x6a,0x0f,0x4b, + 0x29,0xe1,0xf4,0xf8,0x58,0xce,0x00,0xec,0x86,0x90,0xe9,0xad,0x62,0xc1,0xd8,0x36, + 0x49,0x37,0x63,0x61,0x96,0x82,0x6d,0x9a,0x6e,0xfe,0x98,0x07,0x16,0xe0,0x34,0xea, + 0xfd,0xd3,0xc3,0xec,0x2d,0xc9,0xbe,0xbe,0x39,0x71,0x27,0xec,0x87,0xca,0x5e,0x6f, + 0x92,0x4d,0x97,0x7f,0x0e,0x01,0x53,0x4d,0x06,0x52,0xbc,0x0b,0x02,0xbd,0x5e,0x2e, + 0xae,0xbf,0xd5,0xf4,0x24,0x9b,0x46,0x95,0xa8,0xfd,0xc0,0x85,0x23,0xa5,0x67,0xa0, + 0xde,0xf4,0x27,0x65,0x43,0xff,0xa3,0x54,0x6d,0x4e,0x4a,0xb2,0x67,0xe0,0xf7,0x50, + 0xdd,0xeb,0x5f,0x2b,0x2f,0x80,0x43,0x66,0xd8,0x2c,0x48,0xca,0xa6,0xd2,0x9a,0x1e, + 0x9e,0x92,0x9e,0x84,0x0b,0xd0,0x60,0x8a,0xaf,0xe0,0x4d,0x14,0xbe,0x37,0x8a,0x4f, + 0x77,0x46,0xc2,0x23,0x87,0xe4,0xb3,0xfa,0x79,0xbc,0x54,0xfe,0xa8,0x3c,0x06,0xf6, + 0xf5,0x0d,0x6d,0x27,0xa4,0xaf,0x5f,0xa6,0x7d,0x89,0xce,0x26,0xe5,0x63,0xf0,0x82, + 0x56,0x65,0xfa,0x3b,0xe5,0xa5,0xf0,0xaa,0x5e,0x4b,0xd7,0x6f,0x55,0xf4,0xf4,0xf8, + 0xfe,0x9c,0x90,0x86,0xf7,0x6f,0x7a,0x93,0xde,0x28,0xac,0x53,0x66,0xe2,0x3f,0x64, + 0x29,0x69,0x1d,0xaf,0x36,0x3f,0x03,0x72,0x08,0xda,0x53,0xe5,0x2f,0x2b,0x49,0x76, + 0x02,0x57,0x7f,0xfa,0x7e,0x72,0x16,0x58,0xf3,0x93,0x64,0x0a,0x0a,0x95,0xbd,0xf3, + 0xc3,0x45,0xfd,0xd0,0x91,0xd0,0x4d,0x2f,0xe4,0xfa,0x20,0xce,0x83,0xa6,0x1c,0x66, + 0x63,0x60,0xdf,0x7f,0x54,0x9a,0x0c,0x7b,0xf9,0x8c,0x54,0xd7,0x77,0xd8,0x65,0x2d, + 0x3f,0x4c,0xcc,0x18,0xf2,0x2e,0x6f,0x3f,0x01,0xab,0xf8,0x94,0x61,0x6f,0x7f,0xee, + 0x53,0xbc,0x93,0x97,0xa5,0xd4,0xe5,0x97,0xf5,0x3b,0xd7,0x8f,0xa8,0x3e,0xbc,0x6c, + 0x9d,0xe9,0xaf,0x65,0x01,0xfe,0x51,0x22,0xd4,0xe7,0xbf,0x4e,0xee,0x65,0x1d,0x4a, + 0x78,0xe4,0x6a,0xc9,0x5b,0xa9,0x0e,0x42,0x8d,0xe9,0x0f,0xcb,0xb7,0x3a,0xab,0xde, + 0xb8,0x2a,0x3d,0x3f,0x49,0x39,0x05,0x1f,0x68,0x0d,0x7d,0x05,0xa3,0xe5,0xa3,0xc6, + 0x05,0x4f,0xbd,0x79,0x9f,0x81,0xcf,0x7b,0xce,0x3a,0x35,0x98,0x6b,0xcf,0xcf,0x8e, + 0x9c,0x91,0xf4,0xfc,0x48,0x2a,0x4e,0x4b,0xfd,0x09,0x1f,0xce,0x36,0xfc,0x1a,0x6a, + 0xcd,0x7c,0x2e,0x1f,0x87,0xa3,0x7c,0x36,0xcd,0xcf,0x7b,0xce,0xfa,0x89,0x14,0x6e, + 0x86,0xbd,0x30,0xa3,0xd7,0xbb,0x2c,0x58,0xca,0x56,0x69,0xf3,0x8e,0x5e,0xb1,0x4c, + 0x1e,0x84,0x87,0xb5,0x69,0xa6,0xd7,0x60,0x67,0x61,0x25,0x94,0x1d,0xf5,0x2e,0x63, + 0x2f,0x39,0xf3,0x6f,0xc2,0x4f,0xc5,0xf3,0x7a,0xc7,0x58,0x2d,0x3e,0x66,0x08,0x9f, + 0x2e,0x70,0x42,0x5a,0x95,0x98,0x96,0xca,0x8b,0xb0,0x37,0xe0,0x07,0xed,0xf8,0xe0, + 0xcb,0xd9,0x28,0xd8,0xf3,0x1f,0x29,0x19,0xb0,0xe7,0x53,0xe5,0x1d,0x10,0x34,0x3d, + 0x61,0xc6,0xd7,0x6f,0x93,0xa6,0x9b,0xde,0xeb,0xd8,0x00,0xb4,0x97,0x4e,0x35,0x71, + 0xe9,0xbe,0xe4,0xac,0xcf,0xe1,0x89,0x3b,0xe0,0x34,0xd4,0x73,0x6f,0x42,0xbe,0x9e, + 0x1f,0x82,0x4a,0xee,0x4b,0xb0,0xd3,0xfc,0x00,0xd4,0xf2,0xfc,0x14,0x1b,0x86,0x37, + 0x5a,0xfe,0x89,0xdf,0x9f,0x90,0x4f,0x2b,0xce,0xfd,0x43,0x0a,0xc6,0xa0,0x1e,0xfc, + 0x1c,0xe7,0x67,0x4c,0x49,0x0b,0xc3,0x74,0xa4,0x5d,0x3e,0xa6,0x8e,0xc1,0x13,0x1a, + 0x1e,0x79,0xc9,0xb9,0x1f,0x55,0x1b,0x82,0x53,0x50,0x6f,0xf8,0xe3,0xf2,0x76,0x38, + 0x08,0xb5,0xc6,0xba,0x78,0xf9,0x76,0xf5,0x15,0xe8,0x6e,0xbc,0x2f,0x2e,0xe3,0x29, + 0xa3,0x32,0xea,0x8b,0xcb,0x07,0x9c,0xfb,0xe1,0xca,0x62,0xd8,0x07,0x95,0x86,0x37, + 0xee,0xa9,0x50,0x57,0xc3,0x57,0x8d,0xae,0x38,0xeb,0x83,0x57,0x78,0xc0,0xf0,0xc5, + 0xd9,0x90,0x74,0x9d,0x59,0xb9,0x3c,0x18,0xc7,0x15,0x65,0xab,0x85,0xd2,0x9c,0x8a, + 0xf4,0x78,0x5c,0x3f,0x6d,0xec,0x2b,0x8d,0x5e,0x1a,0xf6,0x23,0x3d,0x60,0xe4,0x25, + 0xd9,0xdb,0xf0,0x63,0xb5,0xa0,0x45,0x8d,0xb3,0xe7,0x9c,0xf5,0xa0,0x2a,0x0a,0xec, + 0x82,0x90,0xe1,0xd5,0x8a,0x94,0xf6,0xb6,0x40,0x30,0x32,0x5f,0xcb,0x1d,0x82,0xf5, + 0x65,0x01,0x43,0xd5,0x58,0x9f,0x8a,0xa7,0x22,0x41,0x8d,0x1d,0x90,0xec,0xf5,0xd0, + 0x93,0x1f,0x15,0xcf,0xeb,0x5d,0x21,0x97,0x19,0xb1,0xdb,0xaa,0x4b,0x8e,0xf0,0x09, + 0x29,0x38,0x0a,0x55,0x80,0xef,0xf7,0x98,0xd1,0x03,0xf5,0x25,0x3e,0x7c,0xd1,0x92, + 0xbd,0x3e,0x37,0x5d,0x95,0x7e,0xde,0x56,0xf9,0xa4,0x71,0xaa,0xe8,0xeb,0x2d,0xde, + 0x78,0xf1,0x49,0x38,0x55,0x58,0x6f,0x14,0x0c,0xe2,0xf3,0xfe,0x09,0xea,0x5b,0x70, + 0x2a,0xde,0xc9,0xb5,0xe7,0x73,0x53,0x8e,0x3d,0x3f,0xde,0x29,0xfa,0xc1,0x68,0x7d, + 0x8b,0x0f,0x87,0xf9,0x5e,0xf4,0x74,0xd3,0x8c,0x7d,0xd3,0x78,0x1b,0xe6,0x36,0x15, + 0xc4,0xe5,0xe7,0x9c,0xf5,0x53,0xa3,0xa5,0xa0,0x07,0x2a,0x41,0x06,0x8f,0xd4,0x16, + 0xbb,0xab,0xb6,0x34,0xc6,0x51,0x9f,0x8c,0x19,0x01,0x40,0xfd,0x00,0x5a,0x0f,0x04, + 0x34,0x14,0x0e,0x3b,0xf3,0xa9,0xde,0xd0,0x67,0x3d,0x6f,0x51,0x3b,0xce,0x4f,0x4b, + 0xa8,0x55,0xd5,0x02,0xef,0xc0,0x16,0xd0,0x69,0xc6,0xfa,0xf8,0x2e,0xa8,0x68,0xba, + 0x52,0x2b,0x3a,0xe0,0xe8,0x9f,0xd2,0x89,0xdb,0xad,0xf9,0xd4,0xd8,0x14,0x58,0x9d, + 0x13,0x34,0xd4,0x78,0x60,0xb1,0xb1,0x1f,0x02,0x86,0x77,0x3d,0xc3,0xa9,0xce,0x9b, + 0x4e,0xff,0xf0,0x39,0x47,0xff,0x24,0x26,0x3a,0xef,0xb7,0x02,0x56,0xa3,0x10,0x8a, + 0x37,0xf7,0xc1,0xbb,0xac,0xca,0xf0,0x6f,0xec,0x18,0x82,0x0f,0x3b,0xab,0x0d,0xbc, + 0xff,0x61,0x47,0x3f,0x04,0xa5,0xed,0xf6,0xf8,0xbe,0xdc,0x53,0xb8,0x1e,0x68,0x36, + 0xb4,0x77,0xad,0x23,0x78,0x29,0xb3,0xba,0xe9,0xea,0xb8,0x7c,0xc8,0x59,0x3f,0x41, + 0x2d,0x21,0xe6,0xff,0x6a,0xfe,0x39,0x1d,0xfa,0xa1,0x96,0xa6,0x5d,0x67,0x63,0x93, + 0xaa,0x00,0xf5,0x4f,0x0a,0xfa,0x55,0xf1,0x22,0x0e,0x65,0xae,0x9f,0x13,0x84,0x27, + 0x70,0x19,0x7b,0x13,0x2c,0xa8,0xac,0x81,0x00,0x57,0x77,0xb0,0x1d,0xf0,0x79,0x5e, + 0xcd,0xbd,0x3a,0x3b,0x65,0xdc,0xcf,0xcb,0x93,0xc1,0x44,0xd1,0x21,0xfb,0xf5,0xe2, + 0xf8,0xb4,0xfe,0x09,0x37,0xf9,0xa0,0x03,0x74,0xf3,0xf2,0x52,0xe6,0x83,0xee,0xb6, + 0x68,0xaf,0x37,0x9c,0x7b,0x40,0xed,0x30,0xf5,0x51,0x35,0x8c,0xe3,0xed,0xf7,0x9b, + 0x90,0x26,0xd1,0xf7,0x6b,0x76,0x7d,0x83,0x4d,0xe2,0x1d,0x89,0xb2,0x3e,0x75,0x51, + 0xfb,0x93,0xec,0x07,0x6c,0x8a,0xe9,0x5d,0x96,0xfb,0x6b,0x75,0x95,0x5a,0xf6,0x96, + 0xba,0x8c,0xf5,0x6b,0xf6,0x7a,0xdb,0xa1,0x4e,0x86,0x3f,0xf3,0x79,0x29,0xfc,0x48, + 0x27,0xc3,0xf3,0x3b,0xc2,0xa9,0xfc,0x45,0xf2,0x64,0xed,0x63,0x3e,0xeb,0x98,0x7f, + 0xb9,0xfc,0x1b,0xf6,0x3c,0x9f,0x9d,0x08,0x2d,0x97,0x0f,0x39,0xfa,0x47,0xbd,0xca, + 0xd2,0xb7,0xeb,0x92,0x1d,0xef,0x37,0xfd,0xf8,0x96,0x5f,0x1c,0xf0,0x6b,0xb3,0x07, + 0x60,0x99,0x54,0x6f,0x2e,0x4c,0xca,0xa3,0xea,0x69,0x78,0x8a,0xf4,0xc9,0x01,0x47, + 0xff,0x18,0xb6,0xfd,0x3a,0x25,0x7d,0xcf,0xf8,0xa0,0xb3,0x2a,0xb5,0xae,0x74,0xc2, + 0xbd,0xe6,0x7c,0x7e,0x7d,0x6a,0x5d,0x8f,0x7c,0x5a,0x3a,0xb8,0x61,0x76,0xca,0x3f, + 0x86,0x1a,0xc6,0x7e,0xbf,0x3b,0x6c,0xfd,0xd3,0xc3,0x0a,0xf8,0x3a,0x28,0x1b,0x2e, + 0xa8,0x61,0x9b,0x8d,0xdf,0x24,0xf4,0x11,0xef,0xb7,0x8b,0x5e,0x80,0x07,0x13,0x77, + 0x9a,0x78,0xab,0xef,0x39,0xef,0x57,0x03,0x31,0xde,0xf4,0x2c,0xcb,0x7d,0xdd,0x78, + 0x58,0x2b,0xeb,0x9f,0xdf,0xca,0xea,0x7a,0x76,0x07,0xa6,0xf5,0xcf,0xbf,0x27,0xf7, + 0xa8,0xba,0x4e,0x47,0xc5,0xb5,0xac,0xc9,0x74,0xde,0x57,0x34,0xa3,0x7f,0x42,0x2a, + 0xcd,0xa7,0x27,0x9c,0xbb,0x16,0xba,0x21,0x4a,0x6a,0xa7,0x1f,0xb6,0xa1,0x46,0x42, + 0xe1,0xa8,0xb3,0x3e,0x77,0x4c,0xb4,0x9e,0xb7,0x60,0xf4,0x73,0xdf,0x9d,0xf4,0x01, + 0xec,0x36,0xfd,0xf1,0xe2,0xaf,0x19,0x27,0x50,0x7f,0x0a,0x0d,0x7c,0xb0,0xaf,0x16, + 0x50,0xc8,0xdc,0x4f,0x1c,0x6c,0x7d,0x2b,0x8f,0xf8,0x50,0xe8,0xf5,0xc6,0xe5,0x11, + 0xed,0x0a,0x03,0x8f,0xec,0x6a,0xff,0x10,0xce,0x68,0x0f,0x69,0xe2,0x1f,0xda,0xd7, + 0x8f,0x6b,0x67,0xd3,0xf6,0x4e,0x1e,0x51,0x3f,0x40,0x61,0xc5,0xa0,0x7c,0x56,0x39, + 0x6f,0xce,0xa6,0x23,0x49,0xed,0xe9,0xbc,0x86,0x84,0x6f,0x54,0x36,0x5b,0xec,0xf1, + 0x6d,0xca,0x52,0xb4,0xbf,0x53,0xcd,0xae,0xa4,0x27,0x04,0x3f,0x27,0x43,0x16,0x67, + 0x03,0x6c,0x0d,0xa0,0xfe,0x0c,0xcb,0x5b,0xd5,0x27,0xda,0x43,0x89,0x20,0x5a,0x34, + 0xc3,0xd6,0x3f,0x3c,0x27,0x04,0x96,0xbd,0x03,0x31,0x1e,0xef,0x27,0x30,0x22,0x3d, + 0xc1,0x02,0x78,0x24,0x77,0x2b,0xec,0xe3,0x95,0x9b,0x54,0x1c,0xef,0xac,0x1f,0x55, + 0xf1,0x59,0xf3,0x33,0x8b,0xf9,0xe2,0xdb,0xb4,0x90,0xd9,0x55,0xcd,0x46,0xa4,0x76, + 0x9c,0x16,0xa9,0xbb,0x8a,0xeb,0xbb,0xd4,0x10,0x57,0xab,0xd8,0x01,0x67,0x7d,0xf2, + 0xfc,0xa5,0xd6,0xf3,0x9e,0x28,0xfe,0x65,0xea,0x03,0x40,0x7b,0xba,0xf1,0xf7,0x23, + 0xa8,0xb1,0xab,0xfa,0xfc,0xc9,0x8e,0x84,0x79,0xa6,0xa2,0x9e,0xfb,0xba,0x3b,0x4c, + 0x66,0xdf,0x4f,0xe2,0x2a,0x7a,0xde,0xb9,0xa6,0xff,0x71,0x79,0x84,0x5f,0x98,0xd2, + 0xd0,0xe7,0x1f,0x2d,0x7e,0x1d,0xce,0x6b,0xf5,0x03,0xf8,0xbc,0x1c,0xfe,0x0c,0x0d, + 0x1c,0xe7,0x67,0xd8,0xd1,0x3f,0x0e,0xfe,0xd9,0x27,0xef,0xd4,0x8e,0xc0,0xb6,0xfe, + 0xfc,0x0f,0xe5,0x6a,0xed,0x37,0x07,0xea,0x69,0xd9,0x8c,0x74,0x1e,0x89,0xe3,0xfa, + 0xe9,0x91,0x47,0x59,0x06,0xff,0xfc,0x42,0xe0,0x1f,0x39,0xc9,0xa6,0xb4,0x76,0x99, + 0xb3,0x5f,0xf6,0x7d,0xcc,0xa6,0xc2,0xa3,0x80,0xf8,0xa7,0x87,0x9d,0x83,0x2e,0x5d, + 0x08,0x99,0xf9,0x8f,0x29,0x36,0xfe,0x29,0x52,0x95,0xae,0x92,0x60,0xaf,0x3a,0x87, + 0x25,0x94,0xfd,0x65,0x41,0xb3,0x2b,0xcc,0x06,0x52,0xdb,0x74,0xdd,0xbc,0x29,0x1c, + 0xf8,0xbd,0x1b,0xff,0x58,0xf8,0x21,0xcc,0xf4,0x92,0x2e,0xa3,0xd2,0xcc,0x4b,0x7a, + 0xb6,0x4a,0x8f,0xaa,0x01,0x73,0x7e,0x92,0x8d,0xe0,0xfa,0xd9,0x8a,0x13,0xeb,0xc2, + 0x3f,0xc6,0x44,0x67,0x3d,0x54,0xb6,0xf7,0x17,0xd6,0x9a,0xa1,0xa4,0xdc,0x0e,0x27, + 0x4a,0xac,0x15,0x02,0x7f,0x84,0x2a,0xfc,0x5e,0xd8,0xa0,0x63,0xbf,0x6c,0xfc,0xb3, + 0x70,0x54,0xfe,0x4a,0x64,0x8c,0x2f,0xc3,0x85,0x27,0x2f,0x83,0xf3,0x6d,0x62,0x85, + 0xbc,0xce,0xde,0xb4,0x96,0xca,0xc5,0xf8,0xe7,0xea,0x5d,0x37,0xf4,0x43,0x7f,0x63, + 0xb5,0x19,0x0a,0x4f,0x48,0x44,0x4f,0x37,0xd1,0xf5,0x8b,0x47,0xe0,0x35,0xa8,0x16, + 0x78,0xe0,0x62,0xfc,0xd3,0x83,0x86,0x92,0x2b,0x72,0xaf,0x3a,0x8a,0x37,0xfd,0x2a, + 0xe2,0x31,0x5c,0x21,0x67,0xa1,0x0b,0x08,0x2f,0x35,0x5d,0x02,0xff,0xd4,0x32,0x13, + 0xda,0x41,0x31,0x51,0xdb,0xac,0x80,0x00,0xd3,0x69,0x06,0xd6,0xc2,0x03,0x42,0x35, + 0xe5,0x66,0xf0,0x8f,0x9e,0xc6,0x3f,0xf8,0x91,0xbe,0xc4,0x57,0xf2,0xb2,0x61,0x75, + 0x39,0xfb,0x81,0xf4,0xd3,0xce,0x29,0xa9,0xf9,0xcb,0xd9,0x61,0xfe,0x30,0x02,0x03, + 0xcf,0x72,0x96,0x8d,0x7f,0x3e,0x42,0xfc,0xe3,0xad,0x61,0x07,0x70,0x59,0xcd,0x19, + 0xf6,0xf5,0x30,0x5e,0xb4,0x35,0x51,0x33,0xe2,0xaf,0x91,0xef,0xe7,0xbf,0xde,0xfe, + 0x4d,0xd3,0x7f,0x3d,0xda,0x6b,0xfb,0xe7,0xe0,0x9f,0x5d,0xf8,0x11,0x9d,0x87,0x86, + 0xe7,0x50,0x11,0x1d,0xa5,0xf5,0x23,0xbe,0x20,0x48,0xcf,0xcf,0xa0,0x33,0xff,0x19, + 0xfc,0x83,0x67,0x4f,0xf3,0xee,0x57,0xd7,0xee,0xe9,0x48,0x40,0x3f,0xaf,0x42,0x0d, + 0x26,0x1f,0xe7,0x2f,0x58,0xa7,0x2e,0xc2,0x3f,0x66,0xc1,0x32,0xf6,0xba,0xf2,0x38, + 0x94,0xf7,0x7f,0x76,0x94,0x69,0x6c,0x25,0x5c,0x8b,0x6a,0x84,0xbd,0x9e,0x58,0x85, + 0xa7,0x08,0xff,0x38,0xd7,0x77,0xf0,0xcf,0x72,0xf6,0x86,0xd2,0xbd,0xa6,0x2c,0xe5, + 0x39,0xdd,0xf4,0x00,0xfc,0x00,0x61,0x1e,0x3e,0xe6,0x1b,0xc6,0x2a,0xeb,0xd4,0x25, + 0xf0,0x4f,0x98,0xbd,0x08,0xdd,0xa9,0x00,0x09,0x0c,0xda,0xb9,0x98,0xcf,0x01,0xd4, + 0xf0,0xa1,0x4b,0xe3,0x1f,0x7f,0x02,0x5f,0xfa,0x79,0xb3,0x8a,0x17,0x24,0x8a,0x7f, + 0xa4,0xbe,0x71,0x67,0x00,0x05,0x79,0x18,0x0e,0x59,0xa7,0x4e,0x3b,0xf7,0x63,0xe3, + 0x1f,0x0f,0x5a,0x1f,0x9d,0x84,0x1c,0x01,0x84,0xd2,0x88,0x28,0x37,0x2d,0xbc,0xe4, + 0xac,0xff,0x0c,0xfe,0xf9,0x9c,0x25,0xf8,0xe2,0xcd,0x15,0xfa,0x41,0x4f,0xbd,0xb1, + 0x50,0xd8,0x3b,0x45,0x18,0xbe,0x4b,0xe0,0x9f,0xef,0xb3,0x21,0x65,0x9f,0x54,0x69, + 0x78,0xe2,0xec,0x21,0x63,0xb5,0x85,0x70,0x86,0x6c,0xa8,0x93,0x82,0x4b,0xe0,0x1f, + 0x3c,0xab,0x54,0x12,0x8c,0xa9,0x60,0xe3,0xc7,0x5f,0x0a,0xff,0x90,0xf5,0xaf,0x08, + 0x45,0x6e,0x2a,0x62,0x9d,0xa8,0xf5,0xec,0x23,0xd6,0xa9,0x8b,0xf1,0x8f,0xff,0x41, + 0x44,0x3b,0x28,0x94,0x2c,0x58,0x51,0xae,0x83,0xd9,0x2a,0x1e,0xb3,0xd7,0x18,0xbb, + 0x4d,0x08,0xc7,0xe5,0x8b,0xf0,0x4f,0x1c,0xf1,0xcf,0x39,0xad,0xfe,0x06,0xff,0x7a, + 0xf9,0x65,0xe5,0x1c,0xb3,0xec,0xbb,0x91,0x3e,0x95,0xc1,0x3f,0xa5,0x36,0xfe,0x19, + 0x6c,0x7e,0x5f,0xdf,0xc7,0x6a,0x5b,0x7d,0x1b,0x0e,0xcc,0x51,0x0f,0x42,0x15,0xc1, + 0x86,0xa1,0x96,0xeb,0xac,0xf1,0x17,0xe3,0x1f,0x04,0x39,0xa9,0xce,0x9e,0x5b,0x43, + 0xa5,0xf9,0x2b,0x19,0x01,0x83,0x00,0x44,0x38,0x43,0x3c,0xa6,0xd3,0x29,0x70,0xe1, + 0x1f,0x70,0xf0,0x0f,0x0a,0x4a,0x68,0x91,0xaa,0xdd,0xaf,0xb0,0xb6,0xd8,0x56,0x63, + 0x0d,0x3d,0xef,0x16,0x35,0xfd,0xbc,0xe3,0xf0,0x4f,0xe3,0x95,0xd6,0xec,0x85,0x8c, + 0xbc,0xb8,0x98,0x4f,0xc4,0x87,0x04,0x2c,0xf7,0xb1,0xca,0xbf,0x84,0x7f,0x8a,0xde, + 0x8e,0x13,0x9e,0x51,0xe3,0x72,0x6e,0xf4,0x20,0xb7,0xee,0x5f,0x39,0x25,0x89,0xfb, + 0x1f,0x76,0xf4,0x4f,0x06,0xff,0x34,0x0f,0x69,0x28,0x34,0xfa,0x35,0xf9,0x1d,0x78, + 0x57,0xb3,0xf1,0x8f,0x38,0x55,0x7c,0xc8,0xd1,0x3f,0x36,0xfe,0xf1,0xf3,0x6b,0xca, + 0x94,0xe5,0xca,0xbd,0x80,0x68,0xf3,0x98,0x85,0xb7,0xc5,0xc2,0x63,0xf5,0x92,0xff, + 0x52,0xf8,0x47,0x7e,0xc7,0x13,0x54,0x6b,0x81,0xf1,0x9b,0x12,0xec,0x0c,0xac,0x81, + 0x7b,0x11,0x11,0xdd,0x3a,0x9c,0x86,0x46,0xf2,0x1a,0x67,0x3d,0x38,0xf8,0xa7,0x8a, + 0x91,0x61,0x0a,0x9a,0xa5,0xf8,0xe1,0xb4,0xfd,0xdc,0xd2,0xc0,0xce,0xa7,0x74,0x31, + 0xfe,0xf1,0x2e,0x62,0x93,0x60,0x37,0x2f,0x33,0xd7,0xdc,0xc3,0x5e,0x91,0x56,0x09, + 0x18,0xc0,0x5e,0x5f,0xbb,0x57,0x17,0xdf,0xef,0x0e,0xe7,0xfa,0x36,0xfe,0xf1,0x0f, + 0xb3,0xc9,0xfc,0xcf,0xfc,0xba,0xb7,0x7c,0xdf,0x93,0xdf,0x50,0xfe,0x90,0x9c,0x91, + 0x42,0xfc,0xf3,0x66,0xde,0x9f,0xb7,0xcf,0x23,0xe1,0xbd,0x0c,0xfe,0xc9,0x4f,0xef, + 0x37,0xd1,0xac,0x93,0x70,0xd6,0xff,0x78,0x73,0x3f,0x9a,0x75,0x4b,0xc3,0xac,0x4f, + 0x0b,0x19,0xfc,0x03,0xb6,0xfd,0x1a,0x9b,0x72,0x3e,0xfa,0x42,0xfc,0xfa,0x54,0xc1, + 0x98,0x7c,0x1e,0x9e,0xe7,0xd7,0x90,0xfd,0xba,0x60,0x5c,0x30,0x05,0xfe,0x31,0xc7, + 0xe3,0x1f,0xd3,0xfb,0x55,0xf9,0xa9,0x08,0xee,0xa7,0x4c,0xb5,0x96,0xbd,0xae,0x75, + 0x28,0xd3,0x46,0xbc,0xe1,0xa2,0x37,0xf8,0x7e,0xad,0x8c,0xee,0x3f,0x83,0x37,0x20, + 0x8d,0x7f,0xbc,0x4d,0xec,0xf5,0xd8,0xc3,0x3a,0x6a,0x9b,0x7b,0x70,0x9b,0xb6,0x4e, + 0x9d,0x66,0x76,0xe1,0xf3,0xe2,0x29,0x31,0x3e,0x83,0x7f,0x74,0x5b,0xff,0x00,0x58, + 0xda,0x26,0x2f,0x9c,0xfb,0x1c,0x3c,0x60,0x12,0xec,0x09,0x8c,0xe0,0x29,0xa1,0x88, + 0xfa,0x2f,0xc2,0x3f,0xde,0x24,0xde,0xf6,0x1f,0x2d,0xed,0x7a,0x9c,0x1d,0xe9,0x24, + 0xfc,0x53,0x4e,0xa6,0x7c,0x2b,0xed,0xa0,0x33,0xf7,0xc3,0x6d,0xfc,0x13,0x97,0x77, + 0x46,0xce,0xa0,0x62,0xbf,0x19,0xad,0x79,0xe3,0x1f,0xf5,0x2b,0x2c,0x0d,0x9c,0x56, + 0xc5,0x19,0xfb,0x2b,0xa5,0xf1,0x4f,0x41,0x4a,0xfe,0x2e,0x0a,0xdf,0x41,0x7b,0x27, + 0xd5,0xc1,0x9b,0xd2,0x5c,0xfa,0x43,0x67,0xe1,0x88,0xf5,0x17,0x8d,0x71,0xf8,0x47, + 0xc0,0x9e,0x11,0x14,0x6a,0x4d,0x4f,0x92,0xad,0x41,0x20,0x57,0x45,0x88,0x6e,0x44, + 0x7b,0x4d,0x40,0x9d,0x4b,0xe0,0x9f,0x2b,0x93,0x62,0xfc,0x74,0xb4,0x5f,0x6c,0x67, + 0xe3,0x8f,0x95,0xe9,0xe4,0xc1,0x18,0x91,0xba,0xd2,0xe3,0x5d,0xfa,0x27,0x8d,0x7f, + 0xca,0xd8,0x00,0xdf,0xad,0xe2,0xfe,0x74,0x4e,0xfb,0x4e,0x1c,0xa6,0x0f,0xa0,0x99, + 0x1b,0xe0,0x0f,0x18,0x02,0x1a,0x65,0xf4,0x0f,0xd8,0xf8,0x87,0xb3,0x91,0xd4,0x19, + 0xb8,0xce,0x54,0x4f,0xca,0x3b,0xe1,0xcd,0xd6,0xda,0x7e,0xff,0x1e,0x71,0xff,0x96, + 0xeb,0xc3,0xd1,0x3f,0x89,0x3c,0xeb,0x79,0xaf,0xee,0xc0,0xd9,0x40,0xe1,0x90,0xbf, + 0xbb,0xf8,0x75,0x76,0xa1,0xec,0x89,0x01,0xff,0x89,0x6d,0xef,0xeb,0x17,0x74,0x7c, + 0xde,0x13,0xf2,0xb0,0x83,0x67,0xcc,0x15,0x62,0xfd,0x98,0xf9,0x1f,0x77,0xe0,0x3f, + 0xe4,0x75,0x7a,0x41,0xb7,0xfc,0x06,0x1c,0xe0,0x73,0x53,0xbe,0xe4,0x03,0x75,0xea, + 0x6b,0xd0,0x30,0xba,0x6e,0x4c,0x1e,0xcd,0xe0,0x13,0xe1,0xff,0x99,0x89,0xb7,0xa1, + 0x5f,0x40,0xa1,0x76,0x8b,0xef,0x54,0xd1,0x71,0xe8,0xe2,0xd3,0x53,0xf7,0x9d,0xe0, + 0xbf,0x80,0x2e,0x93,0x4c,0x3f,0x4b,0xe5,0xda,0xf3,0xd9,0x0f,0x03,0xca,0x6e,0x29, + 0x64,0xae,0xae,0x42,0x7b,0x84,0x0f,0x0e,0x5d,0xe1,0xc0,0x4e,0x48,0xe0,0x0c,0x7c, + 0xa6,0x0a,0x81,0xf1,0xee,0xa2,0x50,0x3f,0xee,0xd0,0xb7,0x3a,0xef,0x2b,0xed,0xff, + 0x41,0xd8,0x73,0xeb,0x48,0x29,0x0a,0xed,0x79,0xc9,0xc0,0xfb,0xc6,0x0e,0x98,0xde, + 0x9b,0x97,0xbc,0x71,0xa7,0x85,0x48,0x11,0xff,0x48,0xf6,0x7a,0x90,0xd2,0xf8,0x27, + 0x1f,0xdf,0xbe,0x8a,0x42,0xaa,0x20,0x59,0xfc,0x0b,0x15,0xf5,0x83,0xb9,0x36,0x29, + 0xef,0x54,0x05,0xb4,0x4e,0xca,0xbc,0xc5,0x85,0x7f,0x14,0xb1,0x1e,0x46,0xc5,0xfc, + 0x5c,0xff,0x48,0x01,0x2d,0xbc,0xdf,0x41,0x43,0x2f,0x02,0x45,0xb2,0xef,0x57,0x67, + 0xe3,0x9f,0xdb,0x32,0xfe,0x9f,0x90,0xfa,0x1a,0xab,0x46,0xf4,0xd8,0x3c,0x03,0xc6, + 0xd4,0x2a,0x71,0xc4,0x3e,0x35,0xe8,0xf8,0xdf,0xfa,0xc5,0x7a,0x98,0x39,0xe8,0x1d, + 0xf5,0xd4,0x41,0x57,0x6e,0xa8,0x2d,0x7f,0x14,0x61,0x0c,0x97,0x74,0xf3,0xca,0x51, + 0x36,0xa9,0x70,0x9d,0xb5,0x1e,0xb2,0xf0,0x8f,0xb6,0x1b,0x2a,0xfb,0x6d,0xeb,0xcc, + 0xf3,0xc2,0xb8,0x91,0xaf,0xe2,0x09,0x44,0xe0,0xc6,0xcd,0x91,0x6d,0xb9,0x3e,0xdc, + 0x88,0xa1,0x7d,0xb7,0xd7,0x5b,0xd2,0xc6,0x3f,0xd7,0xb3,0x3b,0xcc,0x1f,0xf2,0x99, + 0xdb,0xf3,0xbe,0x95,0xfb,0x14,0xdc,0x1f,0x9f,0x96,0xf2,0xd6,0x14,0xdd,0xc1,0x27, + 0xb4,0x09,0x3c,0x70,0x54,0xb1,0xc7,0x47,0x22,0x3e,0x75,0x37,0xd4,0xf5,0xf9,0x6b, + 0xe5,0xc3,0xf0,0xeb,0xb2,0xba,0x47,0x67,0xd6,0xca,0x3e,0x18,0x1d,0x4b,0x0e,0xe1, + 0x15,0x6e,0xe6,0x1f,0xc5,0xeb,0x4c,0x04,0x42,0x2f,0x39,0xf8,0xd9,0xc1,0x3f,0x7f, + 0x92,0x9f,0x34,0xf0,0x7b,0x8c,0xf9,0xff,0xd4,0x7c,0x16,0x81,0xdb,0xdc,0x5e,0xff, + 0x49,0xef,0x93,0x46,0x7a,0x2b,0x31,0x98,0xd1,0xcf,0x8a,0x98,0x9f,0xc3,0x88,0x9f, + 0x43,0x88,0x76,0xea,0xda,0x7c,0x4f,0x94,0x57,0xc2,0xa0,0x35,0x2d,0xc7,0x23,0xaf, + 0x59,0xc2,0x81,0x0c,0x3e,0x4c,0xeb,0x93,0xae,0x7b,0xaa,0xf2,0x13,0xbf,0x85,0x19, + 0x84,0xf6,0x27,0xc1,0x49,0x40,0xfd,0xf9,0x4d,0xf6,0x06,0x5f,0x95,0x22,0xfd,0x09, + 0x19,0xff,0x89,0xa1,0x59,0xf8,0xc7,0x53,0x33,0x75,0x32,0x3c,0xcc,0x67,0x26,0x62, + 0xdf,0x62,0xf5,0xb0,0xd6,0x9c,0x91,0xfa,0xcc,0xb7,0x73,0xdf,0x80,0x55,0x09,0xf1, + 0xbc,0xfd,0xce,0xf5,0x23,0x25,0x6b,0xd3,0x4a,0xdb,0xe3,0x53,0x11,0x3d,0x76,0xe3, + 0xf7,0xa8,0x2a,0x49,0xd8,0x81,0xd3,0x7e,0x19,0xcd,0xb0,0x50,0xec,0xaf,0x3a,0xd7, + 0xb7,0xf1,0x0f,0xa2,0x9d,0x20,0xbc,0x07,0xf3,0x36,0x84,0x12,0xc5,0xb5,0xea,0x61, + 0x3c,0xb2,0x30,0x51,0x9e,0xc1,0x3f,0x19,0xfc,0x66,0xe1,0x1f,0x72,0xf2,0x98,0x0e, + 0xec,0x31,0xc6,0x8c,0xa7,0x48,0x38,0xe6,0x19,0xb6,0xf1,0x8f,0x3d,0x3f,0x2e,0xff, + 0xcf,0x10,0x3b,0x88,0xd6,0x90,0xcc,0xa2,0x7e,0x0a,0xaa,0x85,0xc7,0xa0,0xe5,0x16, + 0x34,0xf4,0x88,0x88,0x0e,0x38,0xf7,0x93,0xc6,0x3f,0x4d,0xde,0x78,0xd3,0x90,0x80, + 0x31,0x64,0x76,0x61,0x97,0x14,0x68,0xc4,0x8d,0xde,0x83,0xda,0x3e,0xb6,0x95,0x8e, + 0xfc,0x05,0xfc,0x83,0xe3,0x5b,0x3d,0xf8,0x0f,0xa5,0x7d,0xb0,0x95,0x8e,0x54,0x5c, + 0xfe,0x23,0x98,0x4e,0xe3,0x0f,0x2b,0xf6,0x7a,0x4b,0xe3,0x9f,0x88,0xb7,0x08,0xad, + 0x7f,0x1b,0xda,0x77,0xb5,0xa8,0xa8,0x0f,0x57,0xac,0x8e,0x08,0x81,0x75,0xf2,0x5d, + 0xfa,0x0e,0x42,0x50,0x87,0x1c,0xfd,0x33,0x96,0x23,0xf0,0x4f,0x89,0x7f,0x05,0x79, + 0x1b,0x10,0x78,0x14,0x58,0x78,0xaf,0x0a,0xf0,0x48,0x10,0x8e,0xb2,0xda,0x92,0x10, + 0x97,0xcf,0x3b,0xfe,0x9f,0x98,0x85,0x07,0x5a,0x10,0xf6,0x0c,0xb5,0x9c,0xc2,0xfd, + 0x5a,0xce,0xfa,0xe6,0x97,0xd5,0x73,0x04,0x03,0xd6,0x97,0x77,0x1a,0xaf,0x68,0xe2, + 0xc1,0xdf,0x52,0xdc,0xf8,0xe7,0x15,0x68,0x68,0xf2,0xc5,0x3b,0x10,0x16,0x42,0x43, + 0x63,0x41,0xbc,0x63,0xc8,0xf3,0xa2,0x72,0x0d,0x4e,0x4b,0xc7,0x1c,0xfd,0x94,0x6a, + 0xe1,0x25,0x69,0x3c,0xfe,0x51,0x3b,0x8b,0xca,0x20,0x86,0x42,0x90,0xfc,0x3f,0x31, + 0xc4,0x3f,0xc1,0x4e,0x28,0xc3,0x53,0xb5,0x12,0xf9,0x7f,0x1c,0xfd,0x13,0xc9,0x11, + 0xf8,0xe7,0x26,0xb5,0xe8,0xa1,0x4e,0xd6,0xc6,0x04,0x3e,0x1c,0x82,0x36,0xa8,0x30, + 0x3c,0x45,0x6b,0x14,0x65,0x8b,0xb2,0xf4,0x26,0xc4,0x3f,0x2f,0x39,0xfa,0x64,0x93, + 0x85,0x7f,0x4c,0x9c,0xb4,0xed,0x9a,0x35,0xff,0x4d,0x38,0xb1,0x5a,0xa0,0xf1,0x0a, + 0xad,0x09,0xa7,0x9a,0x09,0xff,0xcf,0x3b,0xce,0xfb,0x4a,0x94,0x90,0x37,0x8f,0x60, + 0xed,0xb4,0xed,0xca,0x41,0xa5,0x0e,0xf1,0xaa,0xfc,0xac,0x7e,0x30,0x7a,0x19,0xbe, + 0xe8,0xe2,0x0a,0xb0,0x1c,0x3b,0xc5,0x19,0xfc,0xb3,0x04,0xe8,0xfa,0x75,0xc6,0xcc, + 0xb8,0xdc,0x02,0xa7,0x2c,0x58,0xf8,0x07,0xb1,0x42,0xbe,0x86,0x0b,0x43,0x4b,0x7b, + 0x84,0x5e,0x1a,0x8f,0x7f,0x7c,0x0b,0xf8,0xe7,0xa2,0x38,0xff,0xf5,0x16,0xfe,0xe9, + 0xbf,0xa1,0x1a,0xfe,0x9e,0x17,0xeb,0x70,0xd4,0x5a,0x6f,0x99,0xef,0x2b,0xa8,0x10, + 0xfe,0x99,0xc9,0xd5,0x04,0x1b,0x56,0xd6,0xc0,0xcc,0xc7,0xf2,0x51,0x60,0x88,0x11, + 0x79,0x57,0xa2,0x68,0x7f,0x34,0xed,0x1a,0x3a,0x94,0xc1,0x3f,0xca,0x02,0xda,0x64, + 0xc5,0xd5,0x24,0x2c,0x60,0xa8,0x7f,0x96,0xe1,0xf7,0x32,0xc0,0xda,0xd5,0x0a,0x72, + 0x3b,0x4f,0x48,0x7f,0x4a,0x77,0x1d,0x72,0xd6,0x9b,0x0e,0xb7,0xc3,0x0f,0xf1,0xfb, + 0x55,0xef,0xc9,0x1d,0x00,0xdc,0xad,0x34,0x7f,0x66,0x19,0xe2,0x81,0x4e,0xfa,0x7e, + 0xef,0x2e,0xda,0xa8,0xe2,0xa7,0x3d,0x80,0x78,0x20,0xe5,0xe8,0x9f,0x60,0xec,0x0e, + 0xfc,0x7e,0xeb,0x52,0xa1,0xef,0xc9,0x77,0x20,0x2c,0x99,0x17,0xed,0x5c,0x8e,0xf6, + 0xe5,0x39,0x7e,0x6d,0xca,0x7b,0x5a,0x2e,0x52,0xbf,0xc0,0x05,0xfe,0x79,0x2b,0xe0, + 0xe0,0x55,0x81,0x7f,0x50,0xc9,0x3c,0x25,0xac,0x79,0x9d,0x81,0xda,0x63,0x00,0x46, + 0x71,0x9b,0xb9,0x2e,0x59,0x9e,0x82,0x33,0x0a,0x6e,0xcc,0x51,0x9f,0x64,0xf6,0xa7, + 0x39,0xe7,0x0d,0x6b,0xff,0x2e,0x55,0xc2,0x11,0xbc,0x7e,0xc1,0xbe,0xf2,0x37,0xe0, + 0xf9,0x64,0x35,0x45,0x34,0x2a,0xe1,0x83,0x95,0x96,0xff,0x67,0xab,0x3d,0x3f,0x8f, + 0x5a,0xf8,0xa7,0x0f,0xf7,0x9b,0x05,0xe6,0x6f,0x13,0x33,0x5a,0xd4,0xe5,0x81,0xd7, + 0xa3,0x7d,0x25,0xfa,0x88,0xff,0x1e,0xf9,0x46,0x58,0xc5,0xee,0x24,0xfd,0xf0,0x1e, + 0xb3,0xc7,0x23,0xfe,0xc1,0x87,0x9a,0xc6,0xbd,0xdf,0x62,0xb7,0xc3,0x2a,0x6d,0x46, + 0xab,0x87,0xf0,0xcf,0x0f,0xca,0xa6,0x3c,0xeb,0x5d,0x96,0x5b,0x82,0x33,0x40,0x8e, + 0x2f,0xd6,0x77,0xb1,0xff,0x27,0x7c,0xd9,0x02,0xed,0x01,0x16,0x8a,0xe2,0x7c,0x1e, + 0xa6,0x30,0x07,0x6d,0x63,0x5b,0x26,0x74,0xc0,0x43,0xc2,0xff,0xe3,0x8c,0xdf,0x21, + 0xec,0x57,0x2d,0x29,0xd5,0xa5,0xca,0x0b,0x4a,0xa8,0x14,0xed,0xd1,0x07,0xc6,0x60, + 0x6b,0x35,0x1d,0xa9,0x40,0x44,0x34,0x57,0x28,0x52,0x67,0xfd,0x70,0x49,0xe8,0xdb, + 0xb8,0x3f,0xf9,0xb9,0xb5,0x24,0x70,0x01,0x7b,0xc6,0x0c,0x11,0x86,0x78,0xdb,0xba, + 0x14,0x45,0x28,0xec,0xf9,0x91,0xb4,0x27,0x55,0xdb,0xff,0x83,0xd6,0xed,0x7b,0x46, + 0x01,0xc1,0x9e,0x11,0x28,0x37,0x7f,0xb6,0xac,0xb9,0x04,0x9e,0x81,0xd9,0xa6,0x6f, + 0x94,0x65,0xfc,0x93,0x69,0xfc,0x33,0x4a,0xe8,0x05,0x77,0xeb,0x5f,0x1f,0xcd,0x4f, + 0xb2,0x01,0x6d,0x47,0x8c,0xfc,0x39,0xf2,0x14,0xb4,0x80,0x5b,0x4d,0x35,0xc9,0x86, + 0x5d,0xf8,0x47,0x8c,0x8f,0xd2,0x78,0xe5,0xc7,0x50,0xb9,0xcc,0x93,0x6c,0x1a,0x81, + 0x1d,0xfc,0x51,0xb4,0x5f,0x2c,0xa4,0x77,0xb1,0xbb,0x4c,0xf5,0x12,0xf8,0xc7,0xc8, + 0x9b,0x8d,0x68,0x07,0xd7,0x5b,0x4b,0x5e,0x78,0xc3,0x08,0x24,0xb4,0xe0,0x4b,0xde, + 0x39,0x4c,0xd1,0x1f,0xc0,0x89,0x52,0x67,0xb9,0xfc,0x3f,0x10,0x23,0x7b,0x8a,0x9f, + 0xc9,0x3d,0x1d,0xef,0x73,0x44,0x5f,0x86,0x67,0x17,0x3e,0xc8,0x70,0x4e,0xed,0xd1, + 0xf9,0xdf,0xf4,0x4e,0x89,0xcc,0xd7,0xba,0xc9,0xe3,0x91,0xf1,0x87,0x5b,0xfe,0x9f, + 0x06,0xf0,0x9f,0x28,0x3f,0x97,0x3c,0x53,0xd8,0x10,0x41,0xb4,0x83,0xf6,0xab,0x6c, + 0x2f,0x79,0x3c,0x36,0x72,0x1b,0xff,0xe4,0x64,0xfc,0x2d,0x69,0xfc,0xbc,0x5b,0xd6, + 0xe1,0x0f,0xd0,0xd0,0xef,0x53,0xe5,0x27,0x97,0x1c,0x81,0xda,0xd7,0x70,0xd9,0x1c, + 0x6f,0x7a,0x13,0xc4,0xfa,0xc9,0xe0,0x1f,0x5e,0x9a,0x8e,0x7f,0x7d,0xe8,0x99,0xda, + 0xda,0x35,0x38,0xf3,0xa4,0x1a,0x63,0x4f,0xf2,0x7f,0xbb,0x7d,0x0b,0xc2,0x1e,0x79, + 0x27,0x5f,0xd7,0x36,0x9d,0xfc,0x3f,0xa3,0xce,0xfa,0x71,0xe2,0x5f,0x61,0xc6,0x61, + 0x1b,0x02,0xa1,0x2b,0x80,0xad,0x8d,0x3f,0xa0,0xeb,0xc2,0xe2,0xf3,0xdd,0x9a,0xc0, + 0xc3,0x27,0x24,0x7b,0xbc,0x99,0xb3,0x33,0xed,0x4f,0x2b,0x4a,0x00,0xa1,0xc7,0xe9, + 0x9d,0xb8,0x31,0xf9,0xb9,0x32,0x5d,0xe0,0x4f,0xc4,0x3f,0xd3,0x05,0xfe,0x71,0xd6, + 0x0f,0xe4,0x10,0xec,0x14,0x46,0x36,0x00,0x7f,0x64,0xf5,0xe6,0xe4,0xd5,0xb3,0x77, + 0xc2,0x0b,0x52,0x2d,0x0e,0x93,0x68,0x69,0x09,0xa0,0xd2,0x67,0xd8,0xdf,0x97,0xed, + 0xff,0x39,0x92,0x2c,0x5e,0xcc,0x49,0xc8,0x37,0x8b,0xd3,0x1e,0xb3,0xd1,0xf2,0x27, + 0xb5,0xb4,0x7f,0x63,0xd4,0x7e,0x5d,0xf8,0xde,0xd2,0xfe,0xc9,0xb0,0x1c,0x5a,0xf2, + 0x02,0x5e,0x0d,0xf5,0xcf,0x4e,0x5c,0x96,0xf5,0xbd,0x84,0xb8,0xe0,0x23,0xeb,0x4f, + 0x6f,0x76,0xee,0xc7,0xf1,0xff,0xfc,0xc9,0x53,0x00,0xeb,0xa0,0xec,0x75,0x9f,0xe7, + 0x8a,0x3a,0x65,0x1d,0xc2,0xaa,0x02,0xba,0xff,0x06,0xf1,0x68,0xf2,0x13,0xce,0xeb, + 0x35,0x15,0x6b,0xff,0xe5,0xa9,0x31,0xf2,0xa0,0x43,0xd2,0x53,0x72,0x6e,0x60,0x01, + 0x3e,0x66,0x05,0x05,0x6e,0x46,0xb4,0x62,0x58,0x4c,0xf3,0x93,0x74,0xf4,0x4f,0x54, + 0xbb,0x23,0xed,0x0f,0x09,0x4c,0x86,0x55,0xe4,0x06,0x99,0x9f,0x7b,0x07,0x0a,0xd3, + 0x84,0x87,0x84,0x5b,0xa7,0x60,0x8f,0x83,0xc7,0x22,0xea,0x02,0x11,0xff,0x2a,0xa8, + 0x69,0xf7,0xb0,0x8e,0x44,0xd8,0xf4,0x7b,0xe5,0xa5,0xf0,0x7b,0x3d,0x94,0x5a,0x14, + 0x2e,0x3e,0x1c,0xff,0x08,0xe6,0x50,0xfc,0x6b,0x83,0x73,0x3f,0xc6,0xc4,0x34,0xfe, + 0x39,0x31,0x61,0xac,0xf1,0x69,0x6d,0x52,0x5f,0x88,0x37,0xcf,0x33,0xce,0x44,0x1a, + 0x68,0x99,0x9d,0x35,0xce,0x68,0xe4,0x51,0x44,0xfc,0x63,0x3f,0xaf,0x6a,0xfb,0x7f, + 0xf6,0xe0,0xfa,0x39,0xd3,0x5e,0xf5,0x92,0x12,0x93,0xff,0xbb,0xf1,0x47,0xb3,0xba, + 0xdf,0x9f,0xfc,0x14,0x22,0xd2,0x56,0x31,0x3f,0xed,0x19,0xff,0xcc,0xe5,0xe9,0xfd, + 0xd4,0x3f,0x75,0xdc,0x56,0xb2,0x57,0x29,0xeb,0xbd,0x69,0x19,0xe2,0x9f,0x55,0x81, + 0x32,0x52,0x9b,0xb8,0x9f,0x0a,0x8a,0xfd,0xe3,0x89,0xcc,0x7e,0xca,0xf6,0xff,0xd4, + 0xb0,0xc9,0xb0,0x3b,0x5e,0x31,0x34,0x7f,0xa4,0xe8,0x0e,0x65,0x5b,0xdb,0x9d,0x23, + 0xf3,0xf1,0x79,0xb5,0xb4,0x6b,0xc8,0x74,0xbe,0xdf,0x25,0x8a,0xe3,0x7f,0x5e,0x88, + 0x42,0x85,0xe9,0xad,0x68,0x5a,0x20,0x1c,0xfb,0xee,0xfd,0xac,0xdb,0xff,0x33,0x6c, + 0xfb,0x7f,0x6a,0x51,0xa8,0xe6,0x5f,0x4b,0x15,0x2f,0x91,0xdf,0x83,0x6e,0x3a,0x32, + 0x2c,0xa5,0x4f,0x7d,0x94,0xb9,0x7f,0xc9,0xde,0x8f,0xcb,0xc7,0xa2,0x63,0x46,0x8d, + 0x84,0xeb,0x21,0xa1,0x8d,0x41,0xad,0x00,0x42,0x4a,0x8f,0x38,0x35,0xc1,0x1d,0xff, + 0x4a,0xef,0xf7,0x37,0x16,0x57,0x28,0xa7,0xda,0xea,0xa3,0xf9,0xf1,0x07,0x10,0x21, + 0x48,0xf6,0x7e,0xdf,0x12,0x9e,0x19,0x8f,0x7f,0x8c,0xae,0xf8,0xfd,0x53,0xb5,0x7d, + 0xe1,0xca,0x68,0x30,0x5e,0x44,0x8e,0x9d,0x5a,0xe3,0xef,0x33,0xfe,0x9c,0x40,0x06, + 0xff,0xd4,0xa4,0xf1,0x0f,0xc2,0x9e,0xc5,0x09,0x14,0x5a,0xbc,0xeb,0xd9,0x50,0xc9, + 0x3e,0x69,0xfa,0x38,0xff,0x8f,0xfd,0x0b,0x96,0xa4,0xfd,0x3f,0x45,0xac,0xa5,0x73, + 0x97,0x1e,0x8a,0xe4,0x69,0x53,0xfb,0x10,0xf6,0x04,0x23,0x1e,0x0d,0xd5,0x38,0x1e, + 0x31,0xe4,0x4b,0xf9,0x7f,0x0a,0x56,0x04,0xa2,0x40,0x4f,0x97,0xcf,0xe5,0xde,0xc8, + 0x58,0x6b,0x6d,0x89,0x97,0x5b,0x1e,0x21,0x7a,0xf0,0x8f,0x9d,0xfb,0xd9,0x64,0xfb, + 0x43,0xd6,0xcb,0x7b,0x8c,0x53,0x5a,0x7d,0x4b,0xc1,0x32,0x79,0xa8,0xf5,0x94,0x56, + 0x4b,0x61,0xaf,0x93,0x70,0xaa,0x88,0x9e,0xb7,0xfc,0x2d,0x44,0x55,0xe9,0xf1,0x12, + 0xe1,0x1f,0xf2,0xff,0xb4,0xcd,0xd1,0xcf,0xa9,0xf3,0x3e,0x53,0x30,0x28,0x2f,0x46, + 0xd8,0x53,0x84,0x88,0x08,0x11,0xd4,0xbb,0x70,0xaf,0xc0,0x4b,0xce,0x7e,0xad,0xa6, + 0x94,0xa2,0x8d,0x95,0xe0,0x25,0x06,0x47,0x8d,0x81,0x40,0x88,0xa3,0xae,0xe9,0x31, + 0xa6,0x6b,0xb9,0x02,0x08,0xb5,0x7e,0x9d,0x5c,0x43,0xcf,0x39,0xfb,0xa9,0x08,0xda, + 0xe6,0xf5,0xf4,0xbc,0x55,0xed,0x9d,0xf4,0xe0,0xad,0x8b,0xe2,0xac,0xa5,0x62,0x57, + 0x70,0xc9,0x4d,0x14,0xef,0x6b,0xdb,0x62,0x39,0xbe,0x5e,0x75,0xc6,0x97,0x2a,0xdb, + 0xe1,0x11,0x9c,0xb4,0xf9,0xf1,0xa6,0xb7,0xc5,0xec,0xa9,0x1b,0x58,0x05,0xfe,0x43, + 0x8f,0x88,0x97,0x89,0x53,0xde,0x38,0x1c,0x77,0xee,0x1f,0xf1,0x8f,0x75,0xff,0x71, + 0xf9,0x61,0xf1,0xe0,0x95,0x9a,0xbc,0x18,0x5f,0xeb,0x15,0x8d,0x74,0xff,0x88,0x7f, + 0x2a,0x85,0xff,0x87,0x67,0xd6,0xcf,0xf6,0x34,0x28,0xba,0x73,0xb1,0x91,0xc6,0x3f, + 0x43,0x0a,0xfd,0x43,0x02,0xc6,0xf6,0xa5,0x5e,0x72,0xc6,0xab,0x69,0xff,0x4f,0x3e, + 0x7c,0x2a,0xa1,0x8c,0xa9,0x61,0xc5,0xb7,0xf2,0x4b,0x3a,0xf4,0x2b,0x55,0x04,0x84, + 0x10,0x88,0xe6,0x54,0x09,0xfc,0x93,0x89,0x97,0x49,0x96,0xff,0xa7,0x20,0xc5,0x6a, + 0xe1,0x29,0x63,0x2e,0x0f,0xa6,0x8a,0x82,0xda,0xab,0xb8,0x8c,0x05,0x22,0xaa,0x85, + 0x00,0xe1,0x9f,0x8c,0x7d,0xb1,0xfd,0x3f,0x79,0x61,0xed,0x3e,0x7d,0x57,0xab,0x7e, + 0x34,0x4f,0x63,0x14,0x08,0xcb,0xed,0x8d,0x84,0x8b,0x06,0x60,0xb6,0xf5,0xe1,0x3c, + 0xe3,0x8c,0xe7,0x85,0x96,0xff,0xc7,0x63,0xb0,0xab,0xe0,0xb1,0xce,0x2f,0xf3,0xbc, + 0xc1,0x35,0x93,0xfb,0x10,0x11,0xf5,0xa9,0xf8,0xfd,0xf2,0xd9,0xdc,0xf2,0x87,0x18, + 0xf6,0xfd,0xc4,0xd4,0x9f,0x0a,0xff,0x4f,0xde,0x72,0xf6,0x53,0xe5,0x4f,0x6d,0xb3, + 0x52,0xf9,0x8b,0xca,0xeb,0x9b,0x9e,0x31,0xe7,0x0c,0xfb,0xf0,0xfb,0xc5,0x53,0xb3, + 0x08,0xff,0x3c,0x63,0x0f,0x07,0xd5,0x8e,0x07,0x25,0xca,0x97,0xc2,0x87,0xb4,0xf0, + 0xb4,0x66,0xd4,0x30,0x9e,0xea,0x03,0x33,0x93,0xf2,0x39,0x7e,0x06,0x9e,0x22,0x7d, + 0x92,0xf1,0x8f,0x19,0xf0,0x94,0x65,0xbf,0x36,0xe1,0x47,0x7b,0x3e,0xde,0x30,0xe4, + 0x3b,0x2a,0xd7,0xc3,0x91,0x78,0x7d,0xca,0x77,0xaa,0xfc,0x83,0xf0,0x91,0x78,0x43, + 0x6a,0x61,0x4f,0xf9,0x20,0xb7,0xc7,0xef,0x28,0xdd,0x0c,0x7f,0x26,0xfd,0xf3,0x19, + 0xf9,0x8b,0xd0,0x1d,0x9e,0xb1,0x23,0x3f,0x22,0xbf,0x2e,0xb6,0x51,0xf9,0xdf,0x96, + 0x7f,0x6a,0xa2,0x60,0x7a,0xbf,0xcd,0xde,0x6b,0xb7,0x6f,0xc8,0x8e,0x7f,0x79,0xb5, + 0xa6,0x4d,0xb0,0x07,0xbe,0x66,0x7a,0x4e,0x36,0xf9,0xe0,0x61,0x7d,0x46,0x7f,0x8c, + 0x80,0xdf,0x2a,0x82,0x52,0xf7,0xa0,0xe9,0xb7,0xc7,0x47,0x95,0xf4,0xfe,0x4b,0x67, + 0x9f,0x85,0x24,0xbe,0x24,0x2f,0xa0,0xda,0xd9,0x86,0x47,0x54,0xb7,0xff,0x39,0x83, + 0x9f,0xc5,0x7e,0x1f,0x95,0x64,0x42,0xfe,0x57,0x5c,0x3f,0x93,0xcd,0x82,0x4e,0xb9, + 0x8e,0x51,0xa0,0x4a,0x45,0x7d,0xeb,0x49,0xfb,0xcf,0x7f,0x9f,0xd1,0x0f,0x40,0x41, + 0x8d,0x7a,0x73,0x21,0x97,0xfb,0x70,0x1b,0x55,0x6f,0x86,0xda,0x3e,0x37,0x02,0xaf, + 0x49,0xf5,0xbd,0xeb,0x70,0xbf,0x6f,0x85,0x2a,0x92,0xcd,0x43,0x99,0xeb,0x6b,0x67, + 0x81,0xae,0xe6,0x5f,0x26,0xd7,0xc1,0x00,0xd4,0xa5,0x7c,0x66,0xf1,0x66,0x04,0x42, + 0x82,0xe6,0x61,0x19,0x3e,0x04,0x06,0xc7,0x9c,0xf7,0xf5,0x20,0xe2,0x9f,0x3f,0xa2, + 0x91,0xea,0xda,0xe3,0x79,0x08,0x62,0xa9,0xca,0xbb,0x54,0x5f,0x7b,0x88,0x0c,0x71, + 0xaf,0x37,0x99,0x3b,0x92,0xa6,0x76,0xb0,0x51,0x7b,0x3a,0x85,0xff,0x47,0x38,0x25, + 0x78,0xfb,0x74,0x88,0xf1,0xca,0x98,0xa7,0x87,0xed,0x84,0x1f,0x5b,0xc3,0x46,0xd2, + 0xa6,0x9c,0xa5,0x24,0xc3,0x7e,0xbf,0x25,0x3e,0x31,0x1b,0x5e,0xa9,0x88,0x73,0x8e, + 0xfb,0xfd,0x9b,0xda,0x69,0xbd,0xe9,0x34,0x2d,0xed,0x88,0x07,0x74,0xe1,0x8a,0xcc, + 0xe8,0x1f,0x8a,0x7f,0xd1,0xf3,0xfa,0x37,0xc8,0xd3,0x8c,0x7e,0xad,0x1e,0x2a,0x77, + 0xc9,0x4f,0x96,0xbe,0xa9,0x37,0xf4,0xfd,0x24,0xc9,0xce,0xc1,0x99,0x20,0x02,0xc5, + 0xee,0x8e,0x94,0x33,0x3e,0x31,0xf1,0xac,0x24,0xec,0xd7,0x47,0x68,0xad,0x9e,0x84, + 0x7a,0x25,0x3f,0x17,0x1f,0x13,0xcd,0xd6,0xc0,0xd5,0x49,0xf9,0x77,0x09,0x01,0xad, + 0x47,0xcb,0x53,0x15,0x17,0xc5,0xbf,0x36,0x15,0x1f,0x57,0xcf,0x6a,0x88,0x7f,0xba, + 0xa5,0x97,0xe0,0x1c,0xaf,0x7f,0xc1,0xdf,0x2f,0xcf,0x40,0x44,0xdd,0x60,0xe1,0x1f, + 0xfb,0x81,0xc9,0xff,0xf3,0x47,0xc2,0x3f,0x9b,0x9a,0x10,0x08,0xe9,0x73,0x47,0x3d, + 0x67,0xd9,0x7b,0xb0,0x9a,0x97,0x8f,0x76,0xc4,0x02,0xf3,0x78,0x17,0x9e,0x9a,0xdf, + 0x23,0x27,0x99,0xcb,0xff,0x63,0xad,0x07,0x0d,0xdf,0x7e,0x12,0x42,0x7d,0xea,0x1c, + 0xf6,0x5e,0xee,0x3e,0x3c,0xd2,0xc5,0x59,0xbe,0xbd,0x1e,0x5c,0xf8,0x67,0x62,0xda, + 0xc9,0x13,0x2f,0xc2,0xd9,0xe6,0x5f,0x37,0x3d,0xc9,0xa2,0x11,0xbc,0x7e,0xc0,0xcc, + 0x8b,0x15,0xf9,0xb4,0x2e,0x45,0x40,0xa3,0x64,0x06,0xff,0x14,0x8e,0x68,0x76,0xfc, + 0x45,0x3d,0xc5,0xeb,0x7b,0x7d,0xf8,0x75,0x34,0x9d,0x41,0xc1,0xef,0xeb,0x0a,0xb1, + 0xf9,0x4c,0xe0,0x8d,0x5e,0xc3,0xe1,0xff,0x34,0x3e,0xa9,0x7c,0x20,0xbc,0x3d,0x34, + 0x2d,0x84,0x8e,0xc8,0xdb,0x73,0x8e,0xf0,0x8f,0x29,0x3b,0xa1,0xd2,0xb1,0x4c,0x7c, + 0xcd,0xf6,0xff,0x6c,0xea,0x38,0x5e,0x38,0x06,0x35,0x66,0x7e,0xb2,0x79,0x58,0x7a, + 0x57,0x9b,0xda,0xef,0x23,0xfe,0xcf,0x0b,0xb6,0xff,0xc7,0xbe,0x9f,0xfe,0xb4,0x3f, + 0x30,0x6f,0xa3,0x4c,0x0b,0xbb,0x1c,0xd1,0xf5,0x5d,0xc3,0xf0,0xab,0xb6,0xb9,0x83, + 0xf9,0x9c,0x9d,0x65,0x74,0xff,0x08,0x84,0x3e,0x76,0xe2,0xe3,0x4e,0xfc,0x4b,0x63, + 0x9f,0xe5,0xdd,0x42,0x11,0x35,0x45,0x20,0xc1,0xf5,0x93,0x11,0x35,0xb0,0x40,0x4d, + 0xcf,0xcf,0xa8,0xfd,0xb4,0x88,0xdf,0x2c,0xff,0x4f,0xde,0x17,0x73,0x7f,0xaa,0x3e, + 0x9e,0xf8,0xf2,0x70,0xe9,0xb7,0xd9,0x69,0x58,0xb1,0x61,0x71,0xea,0x33,0x4b,0xd8, + 0x1b,0x7d,0x0f,0xa3,0xfd,0x46,0x3c,0x30,0xe2,0xc2,0x3f,0x16,0xff,0xc7,0x7b,0x05, + 0xbb,0x19,0xba,0x13,0x75,0x66,0x7e,0x4d,0x33,0x5e,0xdf,0x08,0xbf,0xab,0x4a,0x1d, + 0x5f,0xe7,0xcf,0x10,0x35,0x28,0x2c,0xbf,0x94,0x6b,0x8f,0x37,0xf2,0x2d,0xfc,0x23, + 0xfd,0x4a,0x7e,0xb2,0xf1,0xbc,0x76,0x7d,0xbf,0x7f,0x0f,0xee,0x2e,0x3e,0x54,0x1a, + 0x8e,0xfa,0x53,0xf2,0x59,0x95,0xfc,0x63,0x05,0xa3,0xae,0xe7,0xb5,0xe3,0x5f,0x05, + 0x49,0xe1,0x4f,0xab,0x7f,0x59,0x7d,0xa2,0xcc,0x03,0x07,0x21,0x3c,0xb4,0x80,0x37, + 0x1f,0x7f,0xeb,0x19,0xde,0x3d,0xce,0xff,0x93,0xf6,0x3f,0x07,0x2d,0xef,0x71,0x68, + 0x40,0xad,0x62,0xa5,0xb0,0x42,0x99,0x76,0x50,0x8d,0x5e,0x76,0x96,0xaf,0xb2,0xfc, + 0xc9,0x27,0x9c,0xe7,0x6d,0x13,0xf8,0x67,0x66,0xca,0xb3,0x08,0xb5,0xe5,0xe3,0xf8, + 0xe0,0x9b,0xbe,0x15,0xa8,0x85,0xfb,0x62,0x65,0x29,0xb6,0xc8,0x78,0x83,0xff,0x10, + 0x11,0x20,0xf9,0x7f,0x2e,0x8a,0x7f,0xa9,0xa5,0x81,0x01,0xa5,0x5b,0x27,0xb5,0xe3, + 0x51,0xf5,0xb6,0xb7,0x96,0x98,0x57,0x54,0xe0,0x0a,0x7c,0xc0,0xd2,0xe7,0xaf,0x3a, + 0xf7,0x93,0xf1,0xff,0xb0,0x61,0x38,0x6f,0xd4,0xf3,0x50,0x42,0xbe,0xde,0x73,0xd8, + 0xac,0x6a,0xab,0x5c,0x2c,0x0f,0xc3,0xab,0x50,0x45,0xf8,0xe7,0x4c,0xc6,0xbf,0x64, + 0xf3,0x7f,0xda,0xe4,0x94,0x6a,0xfb,0x7f,0x16,0x8c,0x19,0xf5,0x5a,0x0e,0x7f,0x20, + 0xa5,0x0c,0x5f,0x8c,0x7f,0x2c,0x3c,0x50,0xb0,0x89,0xcc,0x22,0x1a,0xe2,0x82,0x78, + 0x39,0x9a,0x45,0x72,0x83,0xac,0xc7,0xfd,0x5d,0xda,0x35,0xf4,0x8c,0x73,0x7d,0xc4, + 0x3f,0x8a,0x30,0xbb,0x1b,0xd9,0x50,0x29,0x45,0x5b,0x44,0xd8,0x65,0x57,0x7b,0x60, + 0x99,0x97,0x3c,0x12,0x14,0xe1,0x12,0xf1,0x2f,0xfb,0x67,0xf9,0x7f,0x42,0x86,0xe7, + 0xfb,0xec,0x0f,0xb4,0xf0,0x28,0x5e,0x46,0xb0,0x67,0xea,0xdf,0x92,0xff,0xc7,0xc6, + 0x3f,0x87,0xc7,0xc5,0xbf,0x2a,0xd3,0x6c,0x1f,0xc4,0x3f,0x88,0x34,0x84,0xff,0x27, + 0x82,0x2b,0xb0,0x33,0x1d,0xff,0x6a,0x3a,0x94,0x63,0x5f,0x5f,0xe0,0x1f,0x56,0x97, + 0x76,0xfb,0xdc,0x5a,0x2f,0x91,0xe0,0x1b,0x86,0x6a,0x7a,0xf0,0x32,0x1b,0xff,0x9c, + 0x9f,0xe0,0xf0,0x79,0xf2,0xed,0x78,0x96,0x7c,0x52,0x3b,0x87,0xf8,0xa7,0x6b,0x7d, + 0xf1,0x49,0xf8,0x93,0xf4,0x54,0x0b,0x1e,0x41,0x20,0x24,0x9e,0xb7,0xfc,0x3d,0x67, + 0x3f,0x1b,0x4b,0xc7,0xbf,0xf2,0xe3,0x72,0x1f,0x9c,0x8a,0xd6,0x1b,0xca,0x86,0xae, + 0x0a,0xf8,0x1d,0xcc,0x35,0x7c,0xad,0xf2,0x94,0x4d,0xe7,0xa0,0x8a,0x2e,0x75,0xd8, + 0xd1,0x3f,0xe4,0xff,0x19,0x23,0xff,0x0f,0x2f,0x1a,0x25,0x47,0x90,0x16,0xe9,0xf4, + 0xe8,0xb0,0x03,0x6f,0x83,0x25,0xd8,0x96,0xb6,0x31,0x10,0x44,0xa0,0xe7,0x58,0xb6, + 0xff,0x67,0xa6,0x91,0xd7,0xaa,0xbd,0x0e,0xbb,0xa2,0xa1,0xd6,0x4d,0x1a,0xab,0x90, + 0x56,0xe7,0xea,0xad,0x9e,0xb8,0xe7,0x06,0x3c,0xb5,0xd8,0x10,0xfe,0x1f,0x7b,0xfe, + 0x29,0xfe,0x45,0x20,0x47,0x1d,0x64,0x27,0x61,0x9f,0x51,0xd9,0x88,0xf3,0x5f,0x21, + 0x3d,0xa2,0x57,0x1a,0x3b,0xc8,0x11,0xf4,0x88,0x92,0x9b,0xed,0xff,0xd9,0x3a,0x91, + 0x66,0x1b,0xef,0x7f,0x7d,0x3a,0x7a,0x15,0x8a,0xb3,0x29,0xd1,0x5e,0x08,0x1b,0x05, + 0x04,0x84,0xf6,0x31,0xf2,0x77,0xe1,0xd2,0xb2,0xc7,0x2f,0x71,0xe2,0x5f,0x1d,0x84, + 0x7e,0xeb,0x0c,0xbf,0x26,0x0f,0xb1,0x34,0xff,0x67,0xbb,0x76,0x0a,0x9e,0x10,0xf8, + 0x27,0xe3,0xcf,0x11,0xf8,0xc7,0x9a,0xff,0xb0,0x2a,0x60,0x76,0x39,0xe2,0x1f,0xbd, + 0x4a,0xf5,0xf3,0x62,0x9d,0xa5,0xfd,0x3f,0xec,0xa2,0xf8,0x97,0xba,0x63,0xc3,0xbb, + 0xda,0x1a,0x0b,0xed,0xa8,0xda,0xfd,0x66,0x79,0xf2,0xca,0x44,0x7b,0x50,0x69,0x57, + 0xc8,0xff,0xd3,0x94,0x21,0xb9,0x5a,0xf8,0x07,0xf1,0x4c,0xb4,0xe8,0x15,0x75,0x9b, + 0xf5,0x75,0xf8,0x60,0x43,0x4b,0x82,0x7b,0xc3,0x01,0x9f,0xad,0x9f,0x99,0x83,0x6f, + 0xb7,0x88,0xf8,0xd7,0x4c,0xfa,0x7e,0xcf,0xc3,0xc3,0xed,0xe2,0x6b,0xad,0x63,0x3f, + 0x30,0xca,0x34,0xef,0x20,0xee,0x50,0x28,0x7e,0x8d,0x1b,0x13,0xc8,0xc4,0x77,0x44, + 0xfc,0xab,0x2e,0x55,0x40,0x6e,0x9f,0x0f,0xcc,0x5d,0x29,0x7f,0x8d,0x3c,0x19,0x7e, + 0xcb,0x67,0xe9,0xde,0xe5,0x72,0x01,0x7f,0xde,0xf2,0xff,0xb0,0xa9,0xf6,0xf5,0x6d, + 0xfe,0x8f,0x88,0xee,0xbd,0xa6,0x5f,0x46,0xc4,0xc2,0x05,0x6c,0x1b,0x3d,0x66,0xd2, + 0x3b,0xd2,0x2a,0x4c,0x61,0x58,0x3e,0xd0,0x69,0xaf,0x07,0xdc,0xbf,0x0b,0xff,0x8f, + 0x6f,0x9f,0x5c,0x69,0x5c,0x30,0x1b,0x52,0x0b,0x4e,0x7d,0xfa,0x0d,0xf3,0xc8,0x86, + 0xea,0x28,0x9a,0xad,0x7f,0x53,0x8f,0x58,0xd4,0x8e,0xa3,0x19,0xfc,0x93,0xd6,0x3f, + 0xea,0xb7,0xe4,0x2f,0xe0,0x83,0xe7,0x0f,0xa9,0xcb,0xe5,0xdb,0xa3,0xbf,0xe5,0x8f, + 0x85,0xbc,0xcb,0x8b,0x85,0x3f,0xd9,0x2c,0x58,0x8e,0x16,0xca,0x59,0x0f,0xb0,0x59, + 0xdb,0x4b,0xfe,0xc0,0x97,0xf0,0xe9,0xf6,0x1a,0x21,0x93,0x60,0x4f,0xec,0x67,0xd1, + 0x29,0x92,0x77,0x74,0xeb,0x66,0xbe,0x4a,0x13,0xfb,0x35,0x53,0xb7,0xc7,0xdb,0xfe, + 0x9f,0x60,0x98,0x59,0x8a,0x1d,0x61,0xcf,0x7d,0xf0,0x80,0x54,0x01,0xde,0x9a,0x76, + 0x0b,0xff,0xe0,0xc6,0x36,0xb3,0x7f,0x1c,0xcb,0x11,0xcf,0xcb,0x7d,0xc9,0xe2,0x90, + 0x76,0x81,0xf0,0x4c,0x92,0xbd,0x08,0xaf,0x19,0x3f,0x90,0xfc,0x4f,0xca,0x4f,0x0a, + 0xfb,0xe2,0x75,0xf3,0x07,0xac,0xf8,0x57,0x1d,0xf7,0x6f,0x94,0xdf,0x4f,0x87,0x05, + 0x11,0x28,0x9e,0xa1,0x78,0x74,0xb2,0x79,0xa4,0xe4,0x8c,0x54,0x6f,0x4e,0x4e,0xca, + 0xc3,0x2e,0xfe,0x80,0x30,0x6a,0xdc,0x77,0x12,0x77,0x1f,0x17,0xa4,0xbb,0xd1,0x1e, + 0xc9,0x67,0x2b,0xde,0x84,0x79,0x80,0x42,0x48,0xc4,0xbf,0x3e,0x3d,0xda,0xdc,0xdf, + 0x62,0xdf,0x4f,0xda,0xff,0xc3,0xd5,0x3d,0xed,0x1f,0x20,0x8c,0x09,0x50,0xfc,0x6b, + 0x44,0xd9,0x16,0x0b,0x80,0x27,0x3c,0x61,0x29,0xd9,0x2f,0x04,0x42,0x81,0xe1,0xf1, + 0xf1,0x2f,0xae,0xf2,0xa6,0x14,0xdf,0x2d,0x11,0x5f,0x17,0x61,0xcf,0x8f,0xf9,0xf4, + 0x52,0xb5,0xbb,0x69,0x81,0xea,0xc4,0xbf,0xb2,0xf9,0x3f,0x95,0x09,0xb5,0xaa,0x68, + 0xc0,0x7c,0x40,0x0b,0xf6,0x07,0xab,0xd8,0x08,0x6b,0x9b,0xa2,0xab,0xf8,0x87,0x16, + 0x58,0x40,0x08,0xf1,0x8f,0xa3,0x7f,0xda,0xf3,0x97,0xaa,0x62,0x7e,0xf6,0x74,0xbc, + 0x4f,0xd1,0xc0,0x03,0xbe,0xdd,0x1d,0x88,0xf7,0xca,0x6a,0x4b,0x7c,0xdd,0xde,0x3a, + 0x78,0x81,0xe1,0x0c,0x74,0xcb,0xa6,0xb3,0xa0,0x13,0x3f,0x39,0xab,0xd1,0xf3,0xce, + 0xbc,0xab,0x63,0xcc,0xf8,0x99,0x4e,0xe8,0xa8,0xf8,0x2c,0x7c,0x54,0x72,0xbd,0xcf, + 0x3f,0x4b,0x3e,0x1b,0x3d,0x53,0x88,0xf6,0xfd,0xc3,0xe6,0xe1,0xce,0xf1,0xf8,0xa7, + 0xe0,0x84,0xfc,0x24,0x1f,0x69,0xab,0x7a,0xd6,0xa7,0x96,0x2f,0x37,0xce,0xe8,0x0d, + 0xcf,0x14,0x10,0xed,0xe7,0x85,0xb4,0xff,0xc7,0x99,0x7f,0x2b,0xfe,0x85,0xeb,0xe1, + 0x43,0x56,0x67,0xc6,0x78,0xa0,0x57,0x8d,0xb1,0x20,0x7f,0x3a,0x3e,0xb3,0xff,0x70, + 0x0f,0xfb,0xa3,0xb2,0xce,0x08,0xa4,0xee,0xef,0x61,0xa3,0xce,0xfa,0xef,0x4f,0xfb, + 0x7f,0xf0,0xa5,0xaf,0x0d,0xef,0x80,0xa8,0xe9,0xe1,0x2c,0xa2,0x75,0x48,0xa1,0x03, + 0x5d,0x61,0x36,0x6c,0x74,0x34,0x05,0xcd,0xf9,0xe1,0xc0,0x89,0xf1,0xfc,0x67,0x9c, + 0xc6,0x2b,0x42,0xa8,0x88,0x9a,0xcc,0x47,0xdb,0x61,0xba,0xbe,0x1f,0xbe,0x4e,0xd3, + 0x38,0x8c,0x40,0xf4,0x51,0x7a,0x23,0x29,0xe7,0xfd,0x2a,0x13,0x1d,0xfb,0xbb,0x13, + 0x86,0x59,0xb8,0x37,0x57,0xd9,0xf6,0x55,0x0b,0x21,0x0b,0xa2,0xb2,0xf0,0x07,0x16, + 0xa7,0x1c,0xfd,0x60,0xfb,0x7f,0xd6,0x51,0x74,0x75,0xb3,0xfa,0x74,0x6f,0xbe,0xd9, + 0x3c,0xe6,0xb3,0x22,0x62,0xcd,0xc3,0x9a,0xe5,0x08,0x92,0x8f,0xb6,0xda,0xe3,0x6d, + 0xfc,0xe3,0x0b,0xcb,0xa1,0xa6,0x17,0xe0,0xde,0x7e,0x54,0x3b,0x8f,0xe0,0xb4,0x08, + 0xa0,0xf5,0x8f,0xf0,0x8c,0x15,0x08,0xcb,0xe0,0x01,0x33,0xed,0xff,0x51,0x47,0x59, + 0xbd,0x22,0x99,0x33,0xfb,0xbd,0xf7,0x05,0x96,0x94,0xae,0x43,0x8d,0xa1,0x26,0xa5, + 0xfe,0xd8,0x9b,0x06,0x39,0x12,0x8b,0x3e,0x1e,0xc7,0xff,0xa9,0xa4,0xef,0xa5,0x12, + 0xb8,0x19,0x1a,0xf4,0xe6,0xa1,0x35,0xef,0x50,0xc4,0x87,0x73,0x83,0xde,0xd1,0xa8, + 0xe3,0xfc,0xa0,0x85,0xb6,0xd7,0xcf,0x68,0x1a,0xff,0xa8,0xcb,0x59,0x81,0xd1,0x19, + 0x9b,0x31,0x34,0xff,0x20,0x7b,0x55,0x5a,0xc5,0xbf,0x86,0x1f,0x32,0x22,0x04,0xc4, + 0x03,0xc3,0xde,0xe5,0x55,0x67,0x75,0xfb,0xfa,0x16,0xff,0x07,0xef,0xff,0xfa,0xd9, + 0x05,0x86,0xa9,0x85,0x46,0xbc,0xd3,0xe4,0x1d,0xf0,0x4c,0xa2,0x7e,0xc4,0x57,0x23, + 0xdf,0x0c,0x2f,0x6c,0x0f,0x0f,0x5f,0x7d,0x7d,0xf1,0x4b,0x19,0xfe,0x73,0xbe,0xcd, + 0x0f,0x97,0xcf,0xa1,0x36,0x6e,0x20,0x58,0x58,0x03,0x17,0x5a,0x1b,0xcc,0x7f,0x1b, + 0x2d,0xc6,0x53,0xba,0xe5,0xff,0x61,0xf6,0xfc,0x67,0xf8,0x3f,0x1d,0x23,0xbc,0x1f, + 0x67,0x7b,0x6d,0x5c,0x0e,0x4b,0x67,0x78,0xd5,0xa0,0x2f,0xf9,0xa9,0x14,0x9c,0x49, + 0x89,0xf9,0xc9,0xd8,0x3b,0x1b,0xff,0x78,0xff,0x89,0x9d,0xd3,0x3a,0x61,0xc6,0x51, + 0xd5,0x28,0xda,0x04,0xbb,0xa3,0x65,0x87,0x66,0x2c,0x43,0x6d,0xfe,0xc3,0x25,0x16, + 0xfe,0xa9,0xb0,0xaf,0xcf,0x1d,0xfe,0x4f,0xd5,0x1b,0x9d,0xab,0x62,0x4b,0x53,0x6a, + 0x3f,0xfb,0xa2,0xb2,0x37,0x31,0x05,0x9f,0x37,0xf7,0x55,0xd8,0xcd,0x1f,0x4c,0x5d, + 0xb1,0x1c,0xbf,0x2f,0x7b,0xfe,0x2d,0xfc,0x93,0x66,0x2f,0xb4,0x19,0x38,0xb1,0xaa, + 0x70,0xfb,0x54,0x20,0xb0,0x64,0x07,0xf5,0x07,0x58,0x85,0x79,0x25,0xed,0xbf,0xb2, + 0xf9,0x3f,0x95,0xc2,0xdb,0x03,0x87,0x11,0xff,0xf8,0x16,0xcb,0xcb,0x95,0xd3,0x4a, + 0x35,0x11,0xa1,0x4f,0x09,0x8f,0x50,0x41,0x02,0xf5,0x8f,0x7d,0x3f,0x19,0xfe,0x73, + 0x53,0x2f,0x1b,0xab,0xa8,0x97,0xfc,0x2b,0xbe,0x94,0x88,0x92,0xff,0x87,0x2c,0xd4, + 0xc4,0xb4,0x23,0xe8,0xc0,0x45,0xfc,0x9f,0x19,0xc4,0x8f,0x25,0x5a,0x48,0xfe,0xc6, + 0x0e,0xb2,0x80,0x75,0xc6,0xd7,0xe3,0xf2,0x1f,0x94,0x34,0xfe,0xc9,0x8c,0xb7,0xfd, + 0x3f,0x68,0x76,0x1f,0x94,0xdb,0xb4,0xea,0x56,0x04,0x42,0x08,0x63,0x72,0x2b,0x8d, + 0x17,0xe3,0x81,0x77,0x60,0x9f,0xfa,0x17,0xf8,0x3f,0x44,0xfb,0x81,0xd5,0x70,0x57, + 0xd3,0xea,0x78,0xee,0x90,0x7d,0x85,0x11,0xe2,0x1f,0x5a,0x7c,0x15,0xfb,0xfd,0xda, + 0xfc,0x1f,0x95,0xa2,0x5d,0x6d,0x50,0x11,0x51,0xc3,0xb9,0x2d,0x5c,0x00,0x21,0xc1, + 0xff,0xd1,0x2f,0xcd,0xff,0x29,0xf1,0xad,0xc0,0xfd,0x57,0x4c,0xaa,0x2a,0xb9,0x8f, + 0xcb,0xc7,0x22,0x68,0x91,0x4b,0x3c,0x04,0x84,0xc6,0x2c,0x22,0xd0,0x71,0x67,0xfd, + 0x6c,0xba,0xdc,0xf1,0xff,0x0c,0x19,0x4f,0xb3,0xfa,0x96,0x75,0xcb,0xe4,0x3d,0x2d, + 0xa7,0x8a,0x26,0x0b,0xff,0x0f,0x79,0x84,0xe8,0x79,0x4f,0xc8,0x0e,0x5e,0x2a,0x4c, + 0xd3,0xa2,0xd6,0xcb,0xd7,0xf2,0xb7,0xa1,0x61,0xc1,0x67,0x11,0xf6,0x74,0x9e,0x0a, + 0x56,0xb5,0xfa,0xc8,0x5f,0xf4,0xa2,0x51,0x65,0xac,0xcb,0xf2,0xff,0x88,0xf8,0x57, + 0xbd,0xaa,0xae,0xb8,0xab,0x8c,0xc7,0x24,0xe1,0xff,0x29,0xe3,0x3d,0x46,0x40,0x42, + 0xe1,0x58,0x13,0x05,0xc2,0xae,0xe4,0xf8,0x21,0x8c,0x8b,0x7f,0x35,0xe1,0xf3,0xde, + 0xa0,0x6d,0x81,0xd0,0x22,0x9c,0x96,0x1c,0x3c,0x92,0x68,0x55,0xb5,0xa2,0x3e,0x68, + 0x6b,0x89,0x1a,0x57,0x5e,0x82,0xff,0x43,0xb3,0xb7,0x98,0xb6,0xbd,0x28,0x40,0x85, + 0xbe,0x8f,0x05,0x04,0xfe,0x69,0x5c,0x2d,0x05,0xc6,0xf1,0x7f,0x72,0x2c,0xfc,0x83, + 0x77,0xbb,0x18,0xde,0x35,0x11,0xff,0x6c,0x92,0xa7,0xe2,0x13,0x51,0x58,0x53,0x7e, + 0x47,0x21,0x22,0x93,0x37,0x2e,0x0f,0x57,0xd8,0xeb,0xd3,0xc2,0x3f,0xb5,0xc6,0x4c, + 0x4d,0xee,0x84,0x53,0x3a,0xe2,0x9f,0x1f,0xcd,0xff,0x07,0xf5,0x43,0xb1,0x0c,0x18, + 0x22,0x40,0xdf,0x53,0x34,0x3f,0xaf,0x3a,0xfe,0x9f,0x20,0x58,0xfe,0x1f,0x1f,0x97, + 0xa3,0x04,0x7b,0xe0,0x6a,0x2e,0x5b,0x47,0x42,0xbc,0x39,0x65,0x10,0xfe,0x59,0xc8, + 0x8b,0x0f,0x75,0x3a,0xe3,0x05,0xfe,0xa9,0x25,0x6f,0xcf,0x75,0x45,0xf7,0x1b,0x5f, + 0xe0,0xde,0x68,0x51,0x50,0x12,0x88,0x28,0x21,0x3f,0x01,0x87,0xdb,0x2a,0x09,0xea, + 0x1f,0x72,0xb2,0x6a,0x82,0x92,0xa3,0x7f,0xe6,0xeb,0x71,0x49,0xdf,0xe2,0x55,0x03, + 0x6b,0x55,0x3a,0x22,0x02,0x37,0x3f,0x36,0x04,0xff,0x70,0x3c,0xff,0x67,0x9a,0xa9, + 0xd6,0xb0,0x3c,0xd8,0xcc,0xa7,0x34,0x79,0xcd,0xf6,0xcd,0x7c,0x2f,0x7c,0x6d,0x40, + 0x5d,0x96,0xbb,0x51,0x5b,0x65,0x08,0x3c,0xd0,0x6f,0x18,0xb6,0x7e,0x10,0xf8,0x07, + 0xf1,0xc9,0x3d,0xf2,0x17,0xd9,0x6f,0x78,0x59,0xc2,0xbb,0xbc,0xf9,0x67,0x14,0x11, + 0x1b,0xf2,0x21,0x22,0x2a,0xf9,0xf7,0x76,0x81,0x7f,0x0e,0xd9,0xb7,0x9f,0xc6,0x3f, + 0xb5,0x43,0xfe,0xa7,0xf0,0x7b,0xdc,0xc1,0x70,0x75,0x25,0xe4,0xa5,0x9c,0x88,0xbe, + 0xe4,0xc6,0xd7,0x4e,0x29,0x42,0xd5,0x67,0xf0,0x8f,0xcd,0x7f,0xf6,0xfd,0xf2,0x99, + 0x80,0xd1,0x17,0x9f,0x5b,0xe1,0xf7,0xca,0x17,0x70,0xdb,0x5e,0x3f,0xe4,0x1b,0x93, + 0x9f,0x33,0xde,0xec,0x9c,0x4b,0xf8,0x67,0xb0,0x3d,0x9b,0xff,0x33,0xb3,0x4f,0xed, + 0x91,0x6f,0x8a,0x77,0xc6,0xca,0x7a,0xbd,0x11,0xf9,0x76,0x78,0x18,0xea,0xfb,0xf1, + 0xfe,0x9f,0x33,0xd6,0xb5,0x22,0x02,0xac,0x91,0x7f,0x6e,0xd8,0xd7,0xb7,0xfd,0x3f, + 0xd3,0xbe,0xcd,0x14,0xf3,0x17,0xe1,0x32,0xc9,0xfb,0x8d,0xdc,0xd7,0x71,0xfc,0x8c, + 0xfe,0xbc,0x65,0xec,0xe5,0xc4,0x0f,0xe1,0x41,0xd3,0x7b,0x0f,0xcb,0xf8,0x5b,0x6c, + 0xfc,0x93,0x47,0x61,0xc4,0x04,0xdf,0x4a,0xfe,0x9f,0x85,0xc2,0xe3,0x81,0x47,0x9e, + 0x43,0xfc,0x53,0x41,0xaa,0xe9,0xc7,0x8e,0x7d,0x4c,0x4c,0xb4,0xe2,0x7d,0xf9,0xa3, + 0x72,0x10,0x8e,0x99,0xb8,0xdb,0x6a,0x7b,0xe0,0x9c,0x4e,0x44,0xa0,0xbc,0xa4,0x7c, + 0x98,0xf8,0xa5,0xf8,0xe0,0xcd,0xef,0x39,0xcf,0x6b,0xf3,0x7f,0x6e,0x4e,0xc2,0x12, + 0x6d,0x53,0x05,0x69,0x9b,0xe2,0x11,0xe9,0x3b,0xac,0xd6,0xac,0x24,0xda,0xcf,0x19, + 0x49,0xc4,0xbf,0x86,0x32,0xfa,0x24,0xc3,0x7f,0x5e,0xae,0x1d,0x91,0x66,0xb7,0x2d, + 0x30,0xcb,0x37,0xeb,0x6f,0x2a,0xe2,0x2f,0x9e,0x84,0x37,0xb9,0xb0,0x77,0x29,0x87, + 0xff,0xd3,0x69,0xf3,0x7f,0x92,0x2c,0xe6,0x59,0x03,0xd5,0x86,0xaa,0x32,0xcb,0x23, + 0x71,0x65,0x92,0xbd,0xa5,0x77,0x00,0xb3,0xfc,0x3f,0xe3,0xf9,0x3f,0x68,0xdf,0x75, + 0x72,0x53,0x30,0xcf,0x5a,0x0a,0x9c,0xb1,0x4a,0xf3,0xf2,0x24,0x6e,0x13,0x7e,0xac, + 0x4f,0x25,0x22,0x74,0xca,0x7e,0xbd,0x76,0xfc,0xab,0x17,0x41,0xce,0xea,0xce,0x36, + 0xb5,0x82,0xdf,0xd4,0xd6,0xbe,0x16,0xb6,0x69,0xbe,0x81,0xf9,0x61,0x66,0x9a,0xc2, + 0x51,0x3f,0xab,0xfd,0x40,0x9b,0x3d,0xde,0xe6,0x3f,0x17,0xfc,0x69,0xdb,0x14,0xfe, + 0x82,0x54,0x05,0x95,0xed,0xf2,0xeb,0x68,0xd6,0x1b,0xfa,0xf3,0x92,0xc5,0x6f,0xc7, + 0x5f,0xd3,0xaa,0x07,0xfd,0x8f,0xcb,0x19,0x7c,0x95,0xb8,0x3c,0xfd,0xbc,0x27,0x28, + 0x5a,0x01,0x57,0x1f,0xc8,0x3f,0x20,0xe2,0x3b,0x0d,0x03,0xfe,0x13,0x1d,0xa3,0xad, + 0xe7,0xe1,0xfa,0x43,0xfe,0xd1,0xf2,0xe1,0x15,0xd9,0xf8,0xe7,0x7a,0xd3,0xdf,0x23, + 0x8f,0xf0,0x37,0x35,0x81,0x76,0x9e,0x82,0x0b,0xe1,0x2a,0x5c,0x96,0xcd,0x4b,0xf9, + 0xf3,0x14,0x1f,0xec,0x91,0xc3,0x99,0xf8,0x23,0x20,0xfe,0x81,0xc0,0x49,0x62,0x3b, + 0xa7,0xfc,0x30,0x3d,0x85,0xe8,0xb4,0x12,0x7a,0x0c,0x4f,0xd4,0xd7,0x13,0x98,0x47, + 0x81,0x78,0x53,0xed,0x61,0x89,0x0c,0xff,0x59,0xe0,0x9f,0x60,0x6f,0x9a,0xdf,0x92, + 0xde,0x5f,0xec,0xbe,0x41,0xef,0xc5,0xf9,0xfc,0x2c,0x1e,0x49,0xd0,0x87,0x36,0x7d, + 0x1c,0xfe,0x11,0x20,0x81,0xe2,0x8f,0x22,0xec,0x15,0xc2,0x2f,0x7a,0xba,0x51,0xb8, + 0x09,0xf1,0xe1,0x9a,0x18,0x21,0xcc,0xa6,0x64,0x86,0x9f,0x96,0x33,0x62,0x07,0x3d, + 0x89,0x8d,0x4c,0xd6,0xd6,0x8b,0x2b,0x0a,0xd5,0x66,0x57,0x5d,0xc7,0x52,0xf6,0x0c, + 0xef,0x36,0xd4,0xa4,0x0c,0x19,0xfc,0x53,0x48,0xfc,0x9f,0x34,0x9b,0xf7,0x7b,0xd6, + 0xc2,0x78,0x12,0x31,0x72,0x43,0xa3,0x8f,0xec,0xfb,0x79,0xa8,0x33,0x67,0x8e,0xca, + 0x63,0x8e,0x3f,0xd0,0xc1,0x3f,0x78,0x7d,0xf9,0x05,0xa8,0xea,0xf3,0x89,0xb0,0xd7, + 0x0d,0xf5,0xc6,0xc2,0xc7,0xbd,0x21,0xfd,0x05,0x22,0x3a,0x5e,0xec,0xff,0x21,0xb4, + 0x43,0x34,0x39,0x08,0xa4,0x08,0x0f,0x6b,0x4f,0xe0,0x46,0xbe,0xa0,0x87,0xd5,0xa9, + 0xaf,0xf2,0x00,0x3d,0x6f,0xc6,0xbf,0x61,0xe2,0x7a,0xd8,0x6f,0x6d,0x13,0x28,0xba, + 0x57,0x41,0xe3,0x69,0xc6,0x96,0x9a,0xde,0x6b,0x85,0x7f,0x2c,0x41,0x4b,0x2b,0xe3, + 0xff,0xd1,0x61,0x32,0xcc,0xb5,0xf0,0xcf,0x1b,0xbc,0xa3,0x73,0x4a,0x4a,0x25,0x1a, + 0xcc,0x63,0x89,0x19,0x4b,0xbc,0xdf,0x66,0x93,0xcd,0x1f,0x26,0xca,0xf0,0x08,0x22, + 0x28,0xfb,0x17,0x29,0xb5,0xf8,0xcf,0xbe,0x9a,0x2f,0x1d,0x56,0xb6,0xc1,0x9c,0x54, + 0xb0,0x56,0x1e,0x80,0x8f,0xda,0xbf,0x7b,0xcc,0x5f,0xdb,0x5c,0x99,0x7a,0x26,0x11, + 0x36,0x2b,0x6b,0xdd,0xfe,0x9f,0x49,0x0e,0xfe,0x19,0x81,0x37,0xd5,0xeb,0xcc,0x09, + 0x49,0xe1,0x16,0xab,0x37,0x0a,0x52,0xc5,0x67,0xef,0xc1,0x53,0x7d,0xfe,0x0f,0xe5, + 0x41,0x67,0x7f,0xa4,0x66,0xe6,0xff,0x78,0xea,0xb5,0x48,0xfd,0x31,0x9f,0x45,0x3b, + 0xef,0x8e,0xa2,0xf0,0x35,0x5c,0xa8,0xdd,0x86,0x8f,0xe2,0xf5,0x0e,0x7f,0x46,0xe8, + 0x4f,0x01,0x72,0x5e,0x6f,0x9f,0xa0,0xe3,0x46,0x8c,0x1c,0x41,0x8f,0x41,0x99,0xe1, + 0x59,0xc6,0x7c,0xdb,0x57,0xc1,0xb5,0x74,0xe4,0x55,0x07,0x6f,0x58,0xf1,0xaf,0x74, + 0x74,0x6f,0xd5,0x8a,0x6b,0x8e,0x95,0x12,0xcc,0x7b,0x98,0x97,0x2f,0xcb,0x1b,0x63, + 0x77,0xc4,0xb7,0xf1,0x60,0x14,0xa7,0x22,0xc3,0x3f,0x5c,0x22,0xf4,0x8f,0x8e,0xeb, + 0x2d,0x80,0xeb,0x4d,0x4a,0xbb,0x9d,0xf7,0x2b,0xba,0xd1,0x75,0x2d,0x2e,0xbc,0x2e, + 0x4b,0xd5,0xbb,0xe2,0x5f,0x39,0x84,0x7f,0x6a,0x2d,0xfc,0x73,0x08,0xd1,0x4e,0x88, + 0x84,0xe3,0x50,0x95,0xc8,0x1b,0x91,0x97,0xb0,0xe3,0x6a,0x6d,0xc2,0x97,0x90,0xcf, + 0x64,0xf0,0x55,0xa1,0x9d,0x8f,0x33,0x21,0x9d,0xf6,0xc5,0x8b,0x2d,0x44,0x54,0xc0, + 0x3b,0xd0,0x34,0x1b,0xd5,0x0a,0xf1,0x7f,0x9c,0xf5,0x60,0xc5,0xbf,0x04,0xe9,0x45, + 0xf0,0x5d,0xa3,0x7e,0xf2,0xff,0x9c,0xc2,0x69,0xc9,0xff,0x97,0x2b,0x11,0x11,0x6d, + 0xab,0x32,0xd6,0xc6,0x5d,0xfe,0x31,0x0e,0x84,0x67,0xc8,0xc8,0xa2,0x12,0xfb,0x11, + 0xa3,0x40,0x98,0xf0,0xe7,0x04,0x8c,0xfb,0x27,0xc9,0x5f,0x86,0x47,0xda,0x03,0xe4, + 0xe1,0x19,0x76,0xde,0x2f,0xe1,0x9f,0x5d,0x69,0xfe,0x8f,0x24,0xe2,0x5f,0x71,0xb6, + 0x3d,0x67,0xbf,0x14,0x30,0xae,0xdc,0x18,0x50,0x12,0xab,0xd5,0x00,0x79,0x30,0x0e, + 0x3b,0xe3,0x2d,0xfc,0x13,0x24,0x6f,0x4f,0xdf,0x5a,0x0b,0xed,0x5c,0x46,0x61,0x2f, + 0x1d,0x05,0x68,0xe1,0x5b,0x74,0x9d,0x02,0x61,0x2e,0xfc,0x73,0x55,0x14,0x46,0x6d, + 0xb6,0x73,0xcd,0x2d,0x95,0xb0,0x6e,0x45,0x59,0x02,0x8f,0x88,0xb4,0xa3,0xb2,0x48, + 0x7f,0x6b,0x37,0xe5,0x7f,0xbd,0x93,0xab,0x39,0xe3,0xe9,0xe9,0xaa,0x11,0xed,0x34, + 0x6f,0x6f,0x7d,0x45,0x9b,0x47,0xe8,0x65,0x08,0xce,0x69,0x57,0x19,0x6b,0x5b,0xe5, + 0xa1,0xc8,0x39,0xed,0x69,0x91,0xff,0xe5,0xe0,0xe7,0x1a,0xe1,0xff,0xa9,0xbd,0x89, + 0xe6,0x47,0xff,0x16,0xcc,0x26,0x62,0x70,0x05,0x9c,0x5a,0x4c,0x19,0x64,0xcd,0x73, + 0x8c,0x17,0x83,0x55,0x5f,0xcc,0x1f,0x94,0x0f,0x39,0xe3,0x4b,0x81,0xf0,0x4f,0x35, + 0x25,0x79,0x1d,0xd3,0x7a,0x74,0x06,0xde,0xf6,0x22,0x1d,0x7a,0xa2,0x95,0xe0,0x4d, + 0x30,0xde,0xbe,0x23,0x1a,0xd0,0xd4,0xf1,0xf1,0xaf,0x5d,0xc1,0xa0,0x60,0x77,0x27, + 0xd6,0x47,0xe8,0x31,0xdb,0x15,0x69,0x57,0x4b,0xa8,0x71,0x3e,0x01,0xa1,0x36,0x55, + 0x37,0xf2,0xb2,0xfc,0x3f,0x25,0xdb,0x55,0x6b,0xfe,0x03,0x43,0x0a,0x0a,0x8d,0x5e, + 0x02,0x96,0xfb,0x4a,0x70,0x86,0x93,0x6c,0x3b,0x3c,0xa2,0x6d,0x25,0x46,0xf4,0x73, + 0xce,0xfb,0x4a,0x28,0xf4,0x7e,0xa7,0x5b,0xd1,0xcc,0xbf,0x23,0x6f,0x55,0xdc,0x9b, + 0x76,0xeb,0x6d,0x24,0xc4,0x8b,0x47,0xf2,0x11,0xff,0x38,0xfe,0x81,0x25,0x76,0x3c, + 0x94,0xc6,0x7f,0x08,0x4f,0x65,0x68,0xcf,0xeb,0x36,0x93,0x07,0x8c,0xd7,0x51,0x20, + 0xec,0xa5,0x0c,0x9e,0x71,0xf8,0xcf,0x82,0x7f,0x55,0x95,0xa6,0x3d,0x5b,0x47,0x12, + 0xba,0x09,0x22,0x10,0x96,0xc1,0x3f,0xaa,0xe2,0xe4,0x7f,0x0d,0xb3,0x35,0x10,0xd8, + 0xe6,0x4d,0x14,0x0d,0x2b,0xe2,0xc8,0xe2,0xe2,0x6f,0xc1,0x2f,0xd0,0x22,0x7b,0xdc, + 0xf1,0x2f,0x15,0xf7,0x5f,0xfb,0x2d,0x27,0x0f,0x85,0x69,0x2a,0x0c,0x21,0x88,0xb4, + 0x8b,0xd9,0xec,0x3e,0xe8,0xe0,0x3a,0x7d,0x41,0x07,0x5c,0xf9,0x17,0xf8,0xfd,0x5a, + 0x24,0xe7,0x37,0x8c,0x87,0xa5,0x29,0x86,0xf7,0x1b,0xec,0x75,0x49,0x1c,0x89,0xb2, + 0xdb,0xf5,0x6d,0x6a,0x59,0x9f,0xc7,0x8d,0x7f,0x82,0xa5,0x88,0x7f,0xfa,0x05,0xc8, + 0x39,0x5c,0xf1,0x41,0xf7,0x94,0x63,0xfe,0x6f,0x77,0xbc,0xa1,0xfe,0xf6,0xd0,0xbc, + 0xd4,0xc2,0xe5,0xe5,0x3f,0x85,0xe7,0xf9,0xec,0x14,0x02,0xa1,0x4c,0x3e,0x9a,0xe0, + 0xff,0xa4,0x68,0x3f,0xf5,0xe9,0x0f,0xd6,0xbe,0xd6,0xfa,0x44,0x9a,0xd6,0x2b,0x55, + 0x92,0xb0,0x53,0x39,0x63,0xf3,0x09,0xed,0xf5,0x10,0xcd,0x49,0xc7,0xbf,0x4e,0xc9, + 0xf7,0x1a,0x67,0x92,0xb3,0x53,0x0b,0xc6,0xca,0xc9,0xa2,0xcd,0x1e,0xc2,0xbf,0x78, + 0xaf,0x79,0x84,0xef,0x46,0x90,0x2e,0xbb,0xf8,0x36,0x52,0x7a,0xff,0xf5,0x6d,0x76, + 0x07,0xff,0xc3,0xe3,0xd0,0xa2,0x5e,0x8f,0xfa,0xe7,0xf7,0x30,0x6d,0x38,0xaf,0x2a, + 0xf7,0xa7,0xd0,0xa5,0xff,0x8d,0x99,0xbf,0x8c,0xbd,0x97,0x89,0x2f,0x10,0xfe,0xe1, + 0x38,0xfe,0x6e,0x76,0x07,0xfe,0xc3,0x72,0x53,0xbd,0xc7,0xa2,0x3d,0xf7,0x77,0x2d, + 0x2b,0x52,0xfb,0x56,0xc1,0x97,0x0f,0xa0,0xbe,0xca,0xec,0xbf,0x0c,0x87,0x7f,0x88, + 0xd6,0x8a,0xfc,0x69,0xa4,0x7f,0xa4,0x6d,0x6a,0x70,0x28,0x2f,0xdc,0x3e,0x40,0x0c, + 0xab,0x14,0x02,0x21,0xb7,0xff,0x7c,0x27,0x08,0x7b,0x94,0x04,0xe2,0x27,0x77,0x1b, + 0xa1,0x51,0x18,0xd1,0x2e,0x1c,0x08,0x10,0x2d,0x73,0x29,0x6e,0x54,0x89,0x88,0xcb, + 0x32,0xfb,0xaf,0x84,0x36,0x22,0xd9,0xf1,0x0e,0x9a,0x0d,0xc3,0x9a,0x1f,0xad,0xde, + 0xcc,0xdf,0x35,0x81,0x0c,0x9f,0x98,0xb1,0x61,0x87,0x7f,0x25,0x65,0xf0,0x0f,0x09, + 0xd7,0x47,0xf2,0xad,0xc0,0x07,0x1d,0xf9,0xd2,0x1e,0x38,0x8c,0x1a,0x3e,0x74,0x71, + 0xfe,0x97,0x15,0xbd,0xd2,0x2c,0x62,0x8f,0x6c,0x21,0x9c,0xf9,0x4f,0x7a,0x42,0xda, + 0xa3,0x37,0x05,0xcc,0x08,0xe2,0x9f,0xf1,0xfc,0x9f,0x4c,0xb4,0x2b,0x8f,0x04,0xaf, + 0xc8,0x00,0x62,0x6b,0xa3,0x5d,0x5a,0xc0,0xe2,0xff,0x38,0xef,0x17,0x7c,0x4e,0x7e, + 0x4a,0xdb,0xee,0x0a,0xd4,0x3f,0xd5,0xa8,0xa8,0x77,0x97,0x84,0xfa,0xbd,0x73,0x58, + 0xfe,0x0f,0x1e,0xb1,0xf0,0x40,0xc6,0xff,0x03,0xa5,0x4b,0xf1,0xb6,0xf1,0xed,0xef, + 0x2d,0x3e,0x57,0xf1,0xe7,0x8a,0xda,0xc1,0xfb,0x3e,0xee,0x18,0x81,0x23,0xc6,0xe4, + 0xa3,0xde,0x3d,0x68,0xe8,0x0f,0x19,0xdd,0xa6,0xef,0x31,0xd9,0xcc,0x75,0xf0,0xcf, + 0x55,0x67,0xe1,0x69,0x91,0xbf,0x53,0x3e,0xc2,0x2f,0x94,0xcc,0xbb,0xc9,0xdb,0xcd, + 0xea,0x94,0xef,0x41,0xfd,0xe1,0x09,0x83,0xe5,0xef,0xc7,0xce,0x07,0x05,0xb5,0xc3, + 0xcd,0xff,0x39,0x1b,0x7d,0x96,0x23,0xc8,0x31,0xe5,0x6a,0xf6,0x2a,0xdf,0x0f,0x37, + 0x9f,0x90,0x6f,0x85,0x37,0xf5,0xb9,0xa9,0xc9,0xa7,0xe4,0x2a,0x38,0x02,0xdf,0x89, + 0x4e,0x72,0xc7,0xbf,0x38,0xbc,0x8f,0x46,0x24,0xf0,0x86,0x0a,0x45,0x3e,0xb6,0x06, + 0xb7,0x29,0xea,0x29,0xf6,0x16,0xac,0x2b,0x25,0x20,0xc4,0xa2,0x9d,0xff,0x26,0xd5, + 0x22,0x10,0x62,0xa3,0xb9,0x6e,0xfc,0xb3,0x3a,0x84,0xcb,0x80,0x33,0x45,0x59,0xc3, + 0xa6,0x03,0x5a,0x73,0x13,0x76,0xeb,0x4b,0x4c,0x6f,0x55,0x00,0x82,0xdb,0x20,0xd8, + 0x58,0x3a,0x2e,0xfe,0xc5,0xba,0x10,0x24,0x44,0xb8,0x47,0xe1,0x6b,0x8c,0xc0,0x2d, + 0x38,0x7b,0xbf,0x17,0xb4,0x1f,0x39,0xe9,0x89,0x56,0xfc,0x9c,0xf8,0x9c,0x49,0x96, + 0xcd,0xff,0x41,0x10,0x62,0x86,0xd6,0xa2,0xda,0x3c,0xc4,0x6b,0x35,0x44,0x23,0x6f, + 0xf9,0xce,0x28,0xc2,0x22,0xe7,0xa1,0x21,0xae,0x21,0xfb,0xdb,0xeb,0xe2,0x3f,0xef, + 0x64,0x17,0x50,0xed,0x2c,0xec,0x65,0xe7,0x95,0x91,0xa6,0x86,0x18,0xb1,0x7d,0x34, + 0x3f,0x5c,0x2f,0xf2,0x01,0x01,0x81,0x71,0xcb,0xcc,0xac,0xfc,0x2f,0xd8,0xa9,0x11, + 0xec,0xc9,0x7f,0xd0,0x5b,0x21,0x1d,0x32,0x6a,0xe9,0x6a,0x29,0xe3,0x23,0xa9,0x8a, + 0xfc,0x4b,0xc3,0xf0,0x5a,0x51,0x7d,0x23,0xe2,0x73,0x17,0xfe,0xb9,0xe1,0x2a,0xe8, + 0x68,0x0b,0x7c,0x53,0x0d,0xa2,0xda,0xec,0x88,0x05,0x71,0xbd,0x31,0xb3,0x74,0x1d, + 0xdc,0x2b,0x12,0xe1,0x61,0x5d,0x63,0xe5,0x12,0xbc,0xc3,0xa4,0xe3,0xff,0x41,0xfc, + 0xa3,0x77,0x24,0x02,0x66,0x1e,0x5c,0xd1,0x09,0x9c,0x2f,0x81,0xeb,0xc2,0xb9,0xa6, + 0x15,0x21,0x4d,0xb2,0xbe,0xb6,0xdd,0xea,0xd2,0x26,0xdc,0x7f,0x8d,0xba,0xf8,0x87, + 0x93,0x61,0x1d,0x2f,0x4b,0xed,0xb8,0x29,0xf7,0x32,0x58,0x9b,0x9c,0x96,0xb8,0xfc, + 0xdb,0x53,0x4f,0xc0,0x36,0x3e,0x6d,0x78,0xcd,0xf2,0xdc,0x8f,0x8d,0x09,0x2b,0x66, + 0x44,0x3d,0xdf,0x66,0x4f,0x66,0xf8,0xcf,0x88,0x7f,0x3a,0x22,0x61,0x33,0xbf,0x92, + 0xad,0x6c,0xe2,0xf1,0x1e,0x63,0x46,0xad,0x6c,0x2a,0xdb,0xb4,0xa5,0xc3,0xde,0x59, + 0xf2,0x01,0xfe,0x6b,0x98,0x64,0xf8,0x6b,0xdd,0xfc,0xe7,0x49,0x4f,0x32,0xf1,0xbd, + 0xb4,0xc9,0x43,0x45,0x27,0x61,0x2e,0x79,0x7b,0xc6,0xd4,0x23,0x9f,0xae,0x24,0xa1, + 0x0f,0x2e,0x18,0x0d,0x86,0xf0,0x77,0xd9,0xf3,0xa3,0x4e,0xb4,0x48,0x56,0xf9,0x66, + 0xf3,0x62,0x18,0x55,0xae,0x83,0x82,0x27,0xbb,0x2a,0xd2,0x1e,0xa1,0x66,0x7c,0x35, + 0x51,0xf1,0x85,0x66,0xf8,0x09,0x11,0x69,0x33,0x7f,0x1c,0xca,0x8d,0xe0,0xe0,0x84, + 0x12,0x6d,0x0f,0x94,0x71,0xf5,0x9f,0x58,0x89,0x4a,0xfa,0x73,0x3e,0xee,0xa7,0x60, + 0x55,0x74,0x86,0x41,0xfe,0x1f,0x07,0x8f,0xe1,0xf3,0x9a,0x7b,0x29,0xa9,0x7f,0x29, + 0xfb,0xbc,0xba,0xd3,0x2c,0xbf,0x6b,0x7a,0x0d,0xbb,0x63,0xda,0xde,0x8d,0x33,0x52, + 0x1d,0xcb,0xd9,0xab,0x2c,0x9d,0xff,0xd5,0x9f,0x85,0x7f,0xba,0x23,0x89,0xa8,0x5a, + 0x8d,0xfb,0xf7,0xe4,0xc1,0xc0,0xa8,0x1a,0x0e,0x2c,0xd4,0xd3,0x5f,0xdc,0x3b,0xe4, + 0x7f,0x8e,0x8e,0xe3,0x3f,0x0f,0xc3,0xc7,0xb8,0xed,0x9a,0x34,0x32,0x61,0x89,0x7a, + 0x9c,0xef,0xef,0xac,0x4c,0x94,0x7f,0xcb,0x66,0x04,0x9d,0xe6,0x87,0xa0,0xbe,0x5d, + 0xc4,0xbf,0x32,0xf8,0x0d,0xed,0x91,0x56,0xaf,0x14,0x88,0x6d,0x38,0xa3,0xdd,0x77, + 0x7a,0x3f,0xbe,0x50,0x18,0x26,0xa3,0x5e,0x1b,0xc7,0x7f,0x5e,0x69,0x1c,0x84,0xa2, + 0xa8,0x4f,0xbb,0x72,0xb1,0xf1,0x8a,0x59,0x65,0x84,0xd0,0xfa,0xf3,0x57,0x6c,0x0b, + 0x78,0x50,0x13,0x89,0x42,0x59,0xf1,0x2f,0xa0,0x6c,0xa3,0x25,0x71,0x56,0xa1,0xb7, + 0xb5,0x55,0x37,0x06,0xe3,0x45,0xef,0x00,0x25,0x82,0xa1,0xd9,0x7d,0x5b,0x5f,0xcd, + 0xf5,0xe8,0x78,0xfe,0x33,0x5b,0x0d,0xc1,0x16,0x4f,0x1c,0x81,0xd3,0x8f,0xd2,0x69, + 0x4a,0x69,0x46,0x90,0x20,0xfa,0x06,0xf0,0x54,0x56,0xfc,0x8b,0xdc,0x3e,0xc1,0x88, + 0xa7,0xc8,0x43,0xfe,0xa2,0x8a,0x88,0x5a,0x94,0xa6,0xfd,0x20,0xfe,0xe9,0x83,0x36, + 0x3d,0x21,0xf8,0xcf,0x99,0xf8,0xd7,0x55,0x77,0x1a,0x66,0xeb,0x13,0x25,0x05,0x94, + 0xff,0xfe,0x2a,0x54,0x11,0xdb,0x39,0x05,0x47,0x6f,0xc5,0xe7,0x5d,0x51,0x7e,0xac, + 0xe9,0x50,0x6b,0x15,0xc7,0xa9,0x38,0xef,0xe4,0x5f,0xf4,0x5c,0x3e,0x64,0x9c,0x83, + 0xb9,0x2d,0xf7,0xfd,0x4a,0xde,0xa3,0x9c,0x63,0x0d,0x44,0x84,0x3e,0x09,0xe4,0xf6, + 0x41,0x18,0xf0,0x32,0x0a,0x0d,0xd9,0xfc,0xe7,0x1a,0xe5,0xa4,0x7e,0x50,0xaa,0x6a, + 0x82,0xc1,0x67,0xbe,0xa9,0xbe,0xa8,0xcc,0xbd,0xc1,0x17,0x97,0x4e,0x6a,0x07,0x7d, + 0xb3,0x1b,0x71,0xd8,0x9f,0xa4,0x83,0x30,0x91,0xfe,0xe1,0x3b,0x0e,0x7e,0x2e,0x05, + 0x13,0xff,0x53,0x4e,0xd9,0x5e,0xba,0x1a,0x93,0x2a,0x4b,0xd4,0x15,0x38,0xff,0x1c, + 0xa6,0x83,0xdc,0xce,0x52,0x6d,0x47,0xef,0x0e,0x80,0xca,0xe5,0xfb,0x33,0xfc,0x67, + 0xa5,0x13,0x56,0x40,0x59,0xd3,0x74,0xed,0xa1,0xc5,0x95,0x6d,0xb0,0x38,0x22,0xf8, + 0xcf,0x5b,0xf2,0x04,0x10,0xc2,0xe7,0x55,0x2b,0x04,0xfe,0x71,0xd6,0x43,0x69,0x49, + 0x27,0x5b,0x81,0xeb,0xd3,0xf2,0xa7,0xa9,0x95,0x11,0x35,0x5e,0xb4,0x9d,0x3d,0x82, + 0x6a,0x07,0xe7,0x7f,0x28,0x6f,0x35,0xed,0xef,0xe2,0xec,0xa1,0x0c,0xbf,0x42,0xd9, + 0x03,0x2f,0x12,0xc8,0xdf,0x24,0xdf,0x08,0x07,0x8d,0xea,0x25,0x21,0xca,0x56,0x9b, + 0x86,0x2f,0x82,0xde,0x6f,0xe7,0x6a,0xa8,0x8e,0xe6,0xbb,0xf3,0xbf,0x10,0xff,0xe8, + 0xef,0x42,0x9d,0xb1,0xee,0x47,0xf2,0x1f,0xd4,0x53,0x65,0xa1,0x28,0xa1,0x41,0xe3, + 0x57,0x36,0x43,0xfe,0x23,0x55,0xd4,0x07,0xc8,0xe2,0x3f,0x33,0xa2,0xe1,0x20,0xda, + 0x8c,0xea,0xfd,0x91,0xfa,0x12,0x5c,0x5d,0x3a,0xae,0x37,0x11,0x7f,0x3c,0xa6,0x1c, + 0x85,0x2a,0xe5,0x30,0x2f,0x3f,0xe0,0xf2,0xef,0x4d,0x83,0x35,0xa5,0xe5,0x31,0xf2, + 0xff,0xc0,0xfd,0x06,0xd5,0x73,0x68,0x9a,0x0e,0x69,0xda,0xcf,0x69,0x78,0x94,0x97, + 0x25,0x54,0x37,0xff,0x59,0xcd,0x89,0x00,0x3f,0x90,0x80,0xbc,0x1a,0xe6,0xcf,0xdd, + 0x62,0x2c,0x25,0x37,0x45,0xae,0xb1,0xdb,0x72,0x53,0xbc,0x57,0xb6,0xcd,0xd4,0x0d, + 0x95,0xf2,0xbf,0x1c,0xfd,0x23,0x4d,0xe2,0xab,0xe6,0xa0,0x3e,0x5f,0xb6,0xf2,0x2a, + 0x78,0x90,0x36,0x7a,0xcb,0xd9,0x24,0x98,0x5b,0x74,0x67,0xaf,0xf7,0x1e,0x76,0x34, + 0xf8,0x90,0x5a,0x0e,0x84,0x07,0x9c,0xfd,0x45,0xb0,0xb4,0x28,0xde,0xd9,0x39,0x2b, + 0x91,0x3f,0xe6,0xad,0x85,0x77,0xf8,0xbc,0xa1,0x7c,0x8a,0x7f,0xfd,0x99,0x5f,0x9b, + 0xf2,0x7f,0xb7,0xe3,0x34,0x3b,0xc0,0x67,0xe9,0x3e,0xe2,0x3f,0x3b,0xf1,0xaf,0xfc, + 0x87,0x8c,0x33,0x9c,0x76,0x97,0x1d,0x3b,0xd8,0x51,0x8a,0xce,0x27,0x11,0x06,0x9c, + 0xf1,0x08,0x86,0x21,0xee,0x50,0xd4,0xa7,0x60,0x66,0xb2,0xd8,0x85,0x7f,0x94,0xa7, + 0xe0,0x48,0x67,0x43,0x22,0xff,0xb4,0x7c,0xda,0xe8,0xfb,0xfe,0x9c,0xa1,0xfc,0x7d, + 0xf2,0x1b,0xc6,0x0b,0xf1,0x59,0xa9,0xb5,0x3d,0xd7,0x9c,0xe6,0xef,0xb5,0xcf,0x8e, + 0xfe,0x6c,0xac,0x38,0x93,0xaf,0xb1,0x03,0x36,0xdd,0xda,0x09,0x33,0x5a,0x62,0xb5, + 0x4d,0x87,0x78,0xa7,0x56,0x36,0xec,0xa9,0x91,0x37,0xc3,0xba,0xed,0xc1,0x11,0x75, + 0x79,0xee,0x7b,0xe6,0xca,0x44,0x59,0xb0,0xa0,0x86,0xbd,0xb7,0xd2,0x7e,0xbf,0x00, + 0x1b,0x61,0x55,0xe9,0x8c,0x04,0x3e,0xd4,0x20,0xbb,0x1f,0xfe,0x41,0xec,0xd7,0x0a, + 0x57,0x41,0xd9,0xc0,0x67,0x96,0xb1,0x57,0xfa,0x37,0x86,0xa7,0xf8,0xb2,0xf8,0xcf, + 0x46,0x09,0x47,0x35,0x1e,0xba,0x53,0xdd,0xb3,0x35,0x05,0xbc,0x6c,0x71,0x1f,0x05, + 0x3e,0x80,0x0a,0x71,0xe4,0x51,0xfe,0x7b,0x5c,0xa9,0x20,0x0b,0xe8,0xc2,0x63,0x39, + 0xdb,0xa1,0xcb,0xac,0x0f,0x86,0xf6,0xc8,0xc7,0x03,0xbc,0xad,0x3a,0xb5,0x20,0x59, + 0x7e,0xbc,0xe3,0x08,0x6a,0xd4,0x19,0xa3,0xf2,0xef,0xd9,0x69,0xf6,0xb8,0x9e,0xe5, + 0x3f,0x4f,0x68,0x43,0xa4,0x6d,0xcc,0x9b,0x7b,0x88,0xf6,0xdc,0x59,0xdb,0x7c,0xa3, + 0x48,0xfc,0xc9,0x21,0x8f,0x90,0xfc,0x16,0x82,0xa3,0xda,0xe4,0xd5,0x49,0xdc,0x61, + 0xd9,0xcf,0x2b,0x69,0x27,0xf9,0x85,0x60,0x03,0xf7,0x8f,0xfa,0xeb,0x34,0x5c,0x48, + 0x43,0xbe,0xd1,0x4f,0x9d,0xe7,0xbf,0x45,0x20,0x77,0x35,0x25,0x3e,0x1f,0x86,0xb9, + 0xb0,0x30,0x9b,0xff,0xbc,0x98,0xf7,0xe8,0x84,0xf6,0xab,0x43,0x10,0xeb,0xac,0x37, + 0x3c,0xb4,0x1f,0xff,0x39,0xea,0xc8,0xab,0x93,0x4c,0xd6,0x62,0x50,0x1d,0x46,0x44, + 0xf4,0x88,0x0b,0xff,0x44,0x45,0xfc,0xcb,0xb3,0xa9,0x28,0xa8,0xc7,0x62,0xb8,0x30, + 0x92,0x45,0x23,0x4a,0x17,0x14,0x98,0x5d,0xe1,0xdc,0xf7,0xf4,0x76,0x1e,0xd0,0x3d, + 0x59,0xfc,0x67,0xfc,0xbf,0x24,0x05,0xd9,0xc3,0x6c,0x75,0x8c,0x17,0x86,0xfa,0x6b, + 0x28,0x2d,0x6e,0x9b,0x4f,0x1f,0xf4,0x84,0x8b,0xa6,0xad,0xe7,0x89,0x0a,0x40,0x20, + 0xd4,0x9e,0xc1,0x3f,0x60,0xe4,0x51,0xbc,0xaf,0x60,0x90,0x49,0x7a,0x4c,0x9a,0x6d, + 0x86,0xba,0xdb,0x71,0x63,0xce,0x2a,0x8f,0x7a,0x4f,0x34,0x2f,0xc9,0x35,0xa7,0x55, + 0xb1,0x85,0xc9,0x6d,0x29,0xd9,0xe1,0x3f,0x5f,0x3e,0x4a,0xde,0x0c,0xc3,0xbf,0xab, + 0x3d,0xba,0xe6,0xac,0x88,0x56,0x50,0x62,0x97,0x52,0x3f,0xb8,0xf0,0x43,0x79,0xc4, + 0x3c,0x2b,0x51,0x3d,0x81,0xe6,0x1d,0x65,0xf6,0xfc,0xf4,0xda,0xfc,0xe7,0x31,0xf9, + 0x5e,0xf8,0x40,0x45,0x61,0x34,0x70,0x1e,0xce,0xe9,0xd7,0x9b,0x08,0x9b,0xeb,0xf4, + 0x23,0x66,0x43,0x36,0xff,0xd9,0xd4,0x7e,0x61,0xf1,0x7f,0x7a,0x58,0x25,0x7c,0x60, + 0xa2,0x70,0x96,0x1d,0x87,0x7d,0xad,0xe5,0x2f,0x79,0x7a,0xb4,0x5f,0x2a,0xaf,0x01, + 0x9d,0x2a,0x4a,0x39,0xfe,0x81,0x7e,0xc5,0x21,0x9d,0x2e,0xf0,0x09,0x61,0x0e,0xce, + 0x27,0xee,0xc8,0x06,0xfe,0x31,0xcc,0x7c,0x5b,0x2d,0xe2,0x13,0x7b,0x4b,0xb2,0xc7, + 0x13,0xff,0xd9,0x4a,0xf2,0x62,0x02,0x76,0xf6,0x52,0xda,0xbb,0xb6,0x0b,0xf1,0x0f, + 0x4e,0xe3,0x4e,0xe5,0xc7,0x8a,0xc5,0xbf,0x72,0xee,0xe7,0x96,0x4c,0xfe,0x75,0x9a, + 0x28,0x25,0xf8,0xf0,0x50,0x6b,0xfa,0xc2,0x78,0x05,0x87,0x9f,0x33,0x3e,0xff,0x9d, + 0xf0,0xb0,0xf4,0x81,0x55,0xcd,0x06,0xe7,0x27,0x3e,0xc7,0x5c,0x38,0xfa,0xa5,0x0c, + 0xff,0xc7,0x79,0x5f,0x88,0x7f,0x14,0x0a,0xaa,0xa6,0xd9,0x65,0xf7,0x50,0xa0,0x27, + 0x04,0x63,0x6a,0xad,0x99,0x9f,0x9c,0x10,0xf2,0x39,0xd7,0xb7,0xdf,0xd6,0xd1,0x89, + 0xe9,0x7a,0x08,0xf4,0xd7,0x9f,0xd6,0x03,0xbd,0x05,0xa3,0x9e,0x10,0x5c,0xcf,0xca, + 0xf1,0xfe,0xe5,0x3a,0xf8,0xb9,0x72,0x71,0xfe,0x97,0x3d,0x3f,0x6b,0x69,0xff,0x85, + 0x42,0x91,0xaf,0xf0,0x01,0x45,0x45,0x18,0xdc,0xb4,0x53,0xeb,0x50,0x16,0x9b,0x97, + 0xce,0xff,0x1a,0xcb,0x9d,0x0c,0xbb,0xf9,0x94,0x14,0xa2,0x1d,0x14,0xda,0xca,0x86, + 0x3c,0xcb,0xaf,0xb8,0x19,0x1e,0xb6,0xf1,0x80,0x83,0x7f,0xec,0xfa,0x3f,0x49,0xf9, + 0x7e,0xf3,0x23,0xbc,0xbe,0x9f,0xf2,0xbf,0x7e,0xad,0xd7,0x0c,0xab,0xb3,0xf0,0x2f, + 0x3e,0xa3,0x0b,0xfe,0xb3,0x0b,0xff,0xd8,0xf1,0x2f,0x8b,0xcf,0xb3,0x9f,0x88,0x64, + 0xdf,0x15,0x3b,0x94,0x82,0x65,0xf2,0x4e,0x27,0xff,0xcb,0xc9,0x3f,0x4d,0xe7,0x7f, + 0xa5,0xb7,0x69,0x4b,0x6a,0xcd,0xf9,0xdd,0xb8,0x5f,0x18,0x83,0x7f,0x1a,0x44,0xa0, + 0xb8,0x73,0xeb,0x7c,0x8b,0x7f,0x9e,0xf1,0xff,0xf4,0x6b,0xe9,0xfd,0x17,0xb9,0x7d, + 0x76,0x47,0xcb,0xcc,0xbc,0xb9,0xa8,0x3f,0xf7,0x4a,0xfa,0xa1,0xfb,0x96,0xb1,0x17, + 0xe1,0xb7,0x96,0x6b,0xe8,0xa5,0x4c,0x7d,0x0f,0xf8,0xa9,0x4d,0x72,0x7e,0x43,0xda, + 0xdb,0x36,0x8d,0xd2,0xfc,0x27,0x43,0xb2,0xef,0xcb,0x23,0x31,0x72,0x04,0xad,0xba, + 0x98,0xff,0xb3,0xd6,0xf2,0xaf,0x5a,0x6c,0x67,0x9d,0xd4,0x8e,0x4f,0x78,0x14,0xa7, + 0x85,0x9b,0x06,0xe0,0xc7,0x69,0xfe,0xcf,0xb8,0xf8,0x17,0xa1,0x1d,0x36,0x0c,0xa7, + 0x19,0x39,0x82,0xbc,0x41,0x38,0x6f,0x52,0xfc,0x4b,0x1e,0x2e,0x3d,0x64,0x11,0xa1, + 0xff,0x52,0xfd,0x1f,0x8b,0x0f,0x8c,0xc2,0x62,0x3a,0xc2,0x9c,0x53,0x97,0xce,0xff, + 0xe2,0x1f,0x92,0x7f,0x40,0x23,0xda,0x4f,0x5f,0x95,0xe1,0xdb,0x48,0xf8,0x47,0x78, + 0x0c,0xdc,0xfe,0x1f,0xa7,0xfe,0x4f,0xee,0x50,0xda,0x11,0xc1,0xb6,0xc3,0xbe,0x44, + 0xb5,0x31,0x9d,0xf0,0xcc,0x23,0x56,0x62,0xd7,0xa5,0xf2,0xbf,0x9a,0x2c,0x37,0x91, + 0x55,0xa6,0x06,0x85,0x18,0xc5,0x53,0x56,0xb3,0xc0,0xa5,0xf8,0x3f,0x56,0xb6,0xbb, + 0x26,0xdc,0x3e,0x55,0xac,0x13,0xf1,0x4f,0x45,0xc4,0x83,0xf8,0x87,0x8b,0xc2,0x38, + 0x9a,0x6b,0xff,0x35,0x66,0xe7,0xbf,0x5b,0x4f,0xd7,0x0d,0x96,0xfd,0x6d,0xad,0x2a, + 0xf1,0xf1,0xe2,0x63,0xad,0x66,0x6b,0x55,0x76,0xfe,0x7b,0xcc,0xc9,0x7f,0xc7,0xbb, + 0x15,0xd1,0xae,0xf5,0xc2,0xff,0x43,0x66,0xbd,0x78,0xe8,0xa6,0xf4,0x54,0xfc,0x21, + 0x3b,0xff,0x8b,0x59,0x7c,0x21,0x38,0xa7,0xe2,0x6c,0xb4,0x76,0x6c,0xa7,0xf1,0x11, + 0xdf,0xa0,0x3c,0x85,0x1f,0xb4,0x5c,0x67,0xcf,0x65,0xe5,0x7f,0x8d,0x31,0x2b,0xff, + 0x1d,0x7a,0x88,0xed,0xd3,0xc9,0x84,0xff,0xa7,0x64,0x0a,0x22,0x22,0x7e,0x54,0x17, + 0xfc,0x9f,0xec,0xfc,0xaf,0xf5,0xe9,0xe7,0xc5,0x07,0xd7,0x49,0xf1,0xe2,0xf3,0x1a, + 0x4b,0x89,0xff,0x9c,0x13,0x6f,0x53,0x13,0x82,0xff,0xe3,0xac,0x9f,0x4d,0x69,0xfe, + 0x8f,0xd7,0x76,0xbb,0x75,0x25,0x69,0x3e,0x25,0x4a,0x84,0xbf,0xa9,0x02,0xd6,0x2b, + 0x56,0xfc,0xcb,0xc5,0x5f,0x1d,0x42,0xd8,0x89,0x9b,0x20,0xf1,0xbc,0xd0,0x6d,0x15, + 0x7a,0xa2,0xc7,0x54,0xe3,0x69,0xff,0xcf,0xba,0x2c,0xfc,0x23,0x6d,0x57,0x5d,0xfe, + 0x1f,0x9b,0x08,0x24,0x04,0xa9,0xcf,0x5e,0x2a,0x17,0xe5,0x7f,0xd1,0x24,0xa7,0x5f, + 0x04,0xa4,0x85,0x49,0xb8,0xf0,0xd4,0x7e,0x0b,0x08,0x65,0xe7,0xbf,0xd7,0xa6,0xfd, + 0x3f,0xf0,0x04,0x47,0x21,0xc5,0x82,0xf0,0x14,0x59,0xa8,0xc5,0x78,0xe4,0x51,0x0b, + 0x08,0x65,0xe7,0x7f,0xcd,0xb6,0xf4,0x4f,0x8b,0xb1,0x4b,0xc3,0x0f,0x07,0x88,0xb8, + 0x12,0x0f,0x99,0x57,0xe4,0x10,0x5f,0x45,0xd1,0xc7,0xe5,0xbf,0xc3,0xed,0xf6,0xf7, + 0xfb,0x32,0x3c,0x86,0x82,0xdc,0x1a,0x10,0x8c,0xe8,0x7e,0x8f,0x51,0x35,0x10,0x7b, + 0x18,0x24,0x53,0xe4,0x7f,0xd9,0xf7,0xbf,0x23,0x76,0x87,0x95,0xff,0xbe,0x5c,0xbe, + 0x03,0xfe,0x44,0xc2,0x22,0xf9,0x0e,0xe5,0x63,0xde,0xf0,0x9e,0x67,0x89,0xfc,0x46, + 0xfc,0x08,0xdf,0x35,0x2e,0xff,0xfd,0xaa,0x9d,0x0e,0x9f,0x93,0xf2,0xe3,0x9c,0x44, + 0xf8,0xd7,0xd7,0x25,0xe4,0x91,0xe8,0x99,0x92,0xda,0x6c,0xff,0x8f,0x93,0xff,0x7e, + 0x4a,0xfe,0x8d,0x71,0x84,0x37,0x0c,0x2d,0x0c,0x16,0xdf,0x0b,0xdf,0x89,0x37,0xa4, + 0xee,0x3b,0x25,0x9f,0xd7,0xde,0xec,0x6b,0xb0,0xf2,0xdf,0xed,0xf9,0x79,0x44,0x4a, + 0xf3,0x9f,0x97,0xb3,0xe7,0xf8,0xbf,0x93,0x70,0x9d,0x8c,0x4f,0x94,0x08,0xa5,0xf2, + 0xef,0x66,0x6f,0xf4,0xa7,0xeb,0x6f,0x64,0xf8,0x3f,0x4e,0xfe,0xfb,0x3d,0xec,0xe5, + 0x36,0x4a,0x7c,0x9b,0xdf,0x8a,0xfa,0x6a,0x8f,0x3a,0xc3,0x2c,0xbd,0x9b,0xbd,0xce, + 0xd3,0xe3,0xb3,0xf3,0xdf,0xb7,0x59,0xf3,0x29,0x16,0x9e,0xe9,0xd5,0x02,0x0b,0xa4, + 0x5d,0xbd,0x56,0x44,0xcc,0xe6,0x73,0x66,0xf4,0x15,0xe5,0x7f,0x09,0xfe,0x73,0x18, + 0xd7,0xcf,0xaf,0x88,0xed,0x43,0x65,0xee,0x4e,0xc5,0x1b,0x4c,0x84,0xa9,0x67,0xd9, + 0x9b,0xe9,0xfa,0x21,0x99,0xfc,0x77,0xc9,0xd1,0xb7,0x62,0xd9,0x98,0xfe,0x8d,0x34, + 0x51,0xf0,0x5d,0xf3,0xea,0xed,0xf2,0x80,0xed,0x1f,0x73,0xe7,0xbf,0xdb,0xf6,0xae, + 0xfc,0xbb,0x70,0x0e,0x66,0x9b,0xf8,0xa1,0x51,0x98,0xa3,0xc1,0xf4,0x0d,0xe3,0xfe, + 0x34,0x9d,0xff,0xde,0x7f,0x29,0xff,0x4f,0x08,0xf6,0x29,0xd5,0xa6,0x77,0xb3,0xbc, + 0x53,0xd9,0x2f,0x55,0x9a,0x05,0x0f,0xb1,0x11,0xf5,0xe7,0x7f,0x29,0xff,0x1d,0x0f, + 0x2e,0x96,0x44,0xe0,0xa6,0x87,0xc2,0xee,0x5a,0xa5,0xa9,0x6e,0x11,0x19,0x64,0xe3, + 0xf2,0xdf,0x3d,0x8a,0xe3,0xff,0x21,0x45,0x54,0x41,0x6e,0xc6,0x01,0xd2,0x48,0xe6, + 0x95,0x3a,0x1b,0xe0,0xe9,0xa9,0xcb,0xec,0xbf,0x58,0x0e,0xc5,0xbf,0x84,0xf7,0xef, + 0xcb,0xc6,0x7e,0xcb,0x9a,0xa0,0x7d,0xd7,0xe7,0xf5,0xa3,0x7e,0x3e,0x0b,0x47,0x14, + 0xf1,0xbc,0xa6,0xa3,0x7f,0xb6,0xa6,0xe3,0x5f,0xeb,0xf6,0xc8,0xb4,0x11,0x6b,0x30, + 0xaf,0xfe,0x08,0x9f,0x17,0xf5,0xc9,0xe1,0x82,0x54,0xf9,0x88,0x6d,0xbf,0xde,0x75, + 0xbe,0x47,0x8a,0x7f,0x9d,0xe3,0xb8,0xbf,0x50,0x71,0x93,0xf5,0x22,0x9f,0x3b,0x74, + 0xc3,0x58,0xf1,0x59,0xf5,0xc5,0xf8,0x53,0xb4,0x6c,0xa6,0xc2,0x1b,0xd2,0x6e,0x23, + 0x7f,0x5c,0xfc,0x4b,0xdd,0xcf,0x03,0x51,0x35,0x16,0x78,0x07,0x1e,0xe1,0x81,0x7e, + 0x6f,0x37,0x3b,0x07,0xab,0xa9,0xec,0x4f,0x92,0x4d,0x55,0xda,0x21,0x90,0x8a,0x84, + 0x3d,0x7a,0xc6,0xff,0x33,0x71,0x00,0xe7,0x67,0x3b,0xcf,0x03,0x5c,0x0f,0x1d,0x50, + 0xd1,0xef,0x0d,0xb7,0xbf,0x28,0x3d,0x22,0x05,0xcd,0x35,0x61,0x56,0xe1,0xeb,0xb6, + 0xfc,0x39,0x81,0xac,0xf8,0xd7,0x13,0x7c,0xaa,0xa9,0xc6,0xee,0x1a,0x32,0x7e,0x4e, + 0x65,0x0f,0x11,0xff,0xd0,0xfe,0x8b,0xa6,0xb1,0x82,0x4f,0x6f,0x9f,0x9e,0x8a,0x10, + 0xbb,0xda,0x9e,0x4f,0x28,0x1c,0x81,0x0f,0x79,0x75,0x4d,0xfe,0xce,0xf2,0x77,0x94, + 0x17,0xb4,0x6a,0xf3,0x3e,0x9a,0x9f,0x63,0xf1,0xc9,0x34,0x2d,0xca,0xe5,0xa7,0x79, + 0xed,0xf2,0xfc,0xb0,0x0c,0x59,0xf8,0xe7,0x1c,0x5c,0xbf,0x78,0x9d,0xb9,0xed,0x63, + 0x9c,0xa8,0x99,0x02,0x08,0xe9,0x56,0x18,0xb4,0xf9,0x63,0xe9,0x0d,0xe5,0xf1,0x03, + 0x17,0xd5,0xff,0xf9,0x23,0xaf,0xe2,0xbe,0xed,0xf2,0xf6,0x68,0x9a,0x4d,0x34,0x80, + 0x6a,0x4d,0xd0,0xae,0x86,0xf4,0xd7,0xa0,0xea,0x96,0x82,0xa4,0x57,0xcb,0x8e,0x7f, + 0x19,0xfa,0xa0,0xba,0xb6,0xf9,0x06,0xd8,0xd6,0x1a,0x30,0x5f,0x48,0xde,0x75,0x4e, + 0x7b,0x85,0x96,0xc1,0x93,0xec,0x6d,0xd8,0xcf,0x81,0x22,0x5c,0x55,0x59,0xf8,0x67, + 0x0b,0x24,0x36,0x04,0xf3,0x8b,0xf2,0xb5,0x36,0x58,0x42,0xd3,0x32,0xa0,0xad,0xb7, + 0xfc,0x3f,0xcf,0x2a,0x9b,0xee,0x4a,0xe8,0xb8,0x5f,0xa8,0x71,0xd7,0x3f,0x94,0xf6, + 0x9a,0xfa,0x96,0x60,0x3f,0xbb,0x17,0xfe,0x35,0x2e,0xac,0xff,0x1b,0xf0,0xfd,0xb8, + 0x40,0x08,0xbf,0x31,0x1e,0x8f,0x97,0x45,0xd5,0x6f,0x33,0x35,0x53,0xff,0x07,0x7c, + 0xf0,0x7b,0x08,0xf3,0x60,0x9e,0xfc,0x0b,0xe3,0x19,0xa3,0x66,0xd8,0x5f,0x23,0x8f, + 0x68,0xbf,0x4a,0x7e,0x77,0xc4,0x7f,0x7d,0xc7,0x73,0x7c,0x70,0x47,0x38,0x50,0x59, + 0x2b,0x17,0x65,0xf8,0x3f,0x13,0x9f,0x34,0x3e,0x86,0xab,0x3b,0xc9,0xff,0xa3,0xfd, + 0x99,0xa2,0x5d,0xc9,0x09,0x67,0xf5,0x73,0x85,0xf7,0xd2,0x44,0x0d,0x29,0x67,0xe1, + 0xe9,0x3e,0xef,0x2e,0x77,0xfd,0xc3,0x1b,0x46,0xd4,0x8f,0x38,0xa1,0x05,0xdc,0x74, + 0x9c,0xe1,0xb5,0x29,0x5f,0xd2,0x1b,0xd2,0xd1,0x6c,0x51,0x3e,0xc2,0x71,0x76,0x28, + 0x37,0xdc,0x88,0x47,0xa6,0x8f,0xab,0xff,0x83,0xdb,0x84,0x56,0xa1,0x3f,0x11,0x16, + 0x8e,0xa2,0x3e,0x79,0xd0,0x82,0x3d,0x2f,0xc3,0x4a,0x78,0xc4,0x9c,0x3e,0xca,0x8a, + 0x9c,0x7c,0xed,0x5e,0x11,0xff,0xc2,0x4d,0x6b,0x84,0xfd,0x46,0x7d,0xda,0x14,0xd5, + 0x8d,0x0a,0xf8,0x0a,0x84,0x3d,0x5d,0xf8,0xe0,0xfa,0xaa,0x8e,0x6b,0xa2,0x08,0x84, + 0xc2,0x2e,0xfc,0x83,0xda,0x5b,0xd3,0x7f,0xa5,0x4e,0xbe,0xab,0x0f,0x92,0x5c,0x27, + 0xd8,0xec,0x53,0x1f,0xa1,0xfa,0x3f,0x49,0x34,0x5b,0x5d,0x8d,0xa1,0x14,0x1e,0x29, + 0xca,0xaa,0xff,0x73,0x7e,0x70,0x36,0x0f,0xbd,0x43,0xf9,0x23,0xbc,0x96,0x1f,0x4e, + 0x94,0x07,0xe1,0x50,0xac,0x9a,0xa3,0xbe,0x7d,0x4f,0x3b,0x9c,0xb8,0x36,0x11,0x4a, + 0xc8,0xb5,0xd9,0xf5,0x7f,0x8c,0xa7,0xd8,0xcc,0x4e,0x39,0xd5,0x32,0x16,0x11,0xf5, + 0x7f,0x8e,0x59,0x86,0xa9,0x93,0x84,0xb2,0x5a,0x65,0x7c,0xfd,0x1f,0x95,0xd8,0x3e, + 0x9e,0x0d,0x54,0xfd,0x26,0x2e,0xd8,0xbf,0x88,0x7f,0xa4,0x6e,0x32,0x8b,0x28,0xf0, + 0x2a,0xaa,0xef,0xd7,0x9e,0xa9,0xff,0xd3,0xb2,0x98,0xca,0xf8,0x2c,0x0f,0x6e,0xde, + 0xfa,0x36,0xdf,0x67,0x54,0x1a,0x72,0xfc,0x8a,0x1c,0x4e,0x1e,0x21,0xef,0x06,0x36, + 0x15,0xf6,0xc5,0x03,0xc4,0x60,0xd1,0xb3,0xf1,0x0f,0xaf,0x8c,0xe0,0xa2,0xb2,0xdc, + 0x3e,0x54,0xaf,0x46,0x38,0x82,0xbc,0x1b,0x3c,0x15,0x7c,0x1f,0x6c,0x8d,0x7a,0xe2, + 0x45,0x2b,0xc7,0xe3,0x1f,0xc1,0xf6,0xa1,0x7a,0x38,0x64,0xfd,0x15,0xde,0x26,0x60, + 0x4f,0x2e,0x9e,0xd2,0xa3,0x91,0x48,0x9c,0xb1,0x42,0x7b,0x3d,0x10,0xff,0x07,0xf1, + 0x21,0xa5,0xb9,0xa5,0xd4,0xd3,0x56,0x22,0x7c,0x99,0x31,0x88,0xb0,0xc7,0xbb,0x42, + 0x0a,0x8a,0x40,0x58,0xc1,0x0a,0xf9,0x17,0xce,0xfe,0x8b,0xea,0xff,0xa0,0xda,0x69, + 0xc9,0x1f,0x2c,0x3b,0x09,0x7f,0x82,0xca,0xc6,0x7c,0x4a,0xe3,0xfa,0x1d,0x9a,0x75, + 0x84,0x0d,0x2f,0xc3,0x85,0xc2,0xab,0x89,0x08,0xfd,0xce,0x04,0x7b,0x3e,0x29,0x5f, + 0xfe,0xdf,0x61,0x76,0x53,0xc1,0x60,0xf9,0x6d,0xf8,0x0f,0xbb,0x09,0x08,0xcd,0xd1, + 0x09,0x18,0xac,0x23,0x44,0xf4,0x27,0x6d,0x17,0x11,0x69,0x9e,0x53,0x5c,0xf8,0x47, + 0xe9,0x81,0xad,0x14,0xe4,0x42,0xfc,0x23,0x05,0xa0,0x40,0xe4,0x7f,0xa5,0x2b,0x02, + 0x41,0xac,0x35,0x50,0x12,0xcc,0xaa,0x7f,0x88,0xf8,0x27,0x0d,0xea,0x16,0xe0,0x36, + 0x4a,0x6f,0x8e,0x68,0x6b,0x94,0xc4,0xae,0x69,0xf4,0xe0,0xb8,0x91,0x5c,0x5f,0xa6, + 0x1b,0x6a,0x51,0xbb,0x8b,0xff,0x93,0x43,0xfc,0x1f,0x54,0xe3,0x1b,0xe0,0x1d,0x14, + 0x18,0xb9,0xd1,0x08,0x4f,0x16,0xa4,0x2b,0x0c,0xe8,0xc2,0xc3,0xf6,0x9c,0xa3,0x1f, + 0xb6,0x4a,0x43,0x6a,0xef,0xb2,0x70,0xd4,0x1f,0x2f,0x5c,0xac,0x7c,0xb8,0xab,0xaa, + 0x31,0x57,0xbc,0x56,0x69,0xb2,0xb1,0x90,0x0a,0x21,0x9e,0x32,0xab,0xa2,0xbe,0xb8, + 0x94,0xe1,0x3f,0x53,0xfd,0x9f,0xeb,0xa0,0xfe,0x26,0xdf,0x26,0x86,0x0b,0xa3,0xd3, + 0xae,0x87,0x60,0x88,0x34,0xb1,0x21,0x7c,0xf0,0xb3,0xcb,0x66,0x66,0xd5,0x3f,0x24, + 0xfe,0xcf,0xb2,0x2a,0x58,0xc0,0x9b,0x75,0x18,0x2e,0x15,0x65,0x36,0x13,0xca,0x98, + 0x22,0x60,0x67,0x54,0x19,0x8b,0x76,0x2b,0x3e,0xde,0xec,0xae,0x67,0x88,0x68,0xc7, + 0xd8,0x96,0x4c,0xa4,0xe4,0xe5,0xea,0xfd,0x8d,0x88,0x7f,0x86,0xdb,0x4f,0x6f,0x7a, + 0x42,0xa9,0x26,0x20,0x54,0xa3,0x3c,0x65,0x94,0x73,0xe1,0xff,0x71,0xc6,0x4f,0x5c, + 0x00,0x0f,0x70,0xbd,0x75,0x87,0x1e,0xe8,0x44,0x8b,0x85,0x6a,0x67,0x47,0xd1,0x1a, + 0xb4,0x50,0x6a,0x2f,0x65,0x30,0xa9,0xbb,0xa1,0x22,0x15,0x0c,0x17,0x1d,0x72,0xea, + 0xc7,0x5a,0xfc,0xe7,0x84,0xa6,0x2e,0xda,0x7a,0x0f,0x74,0x82,0x08,0x7b,0x1d,0x85, + 0xa7,0x93,0x0f,0x12,0xa2,0x98,0xa4,0xee,0x85,0x29,0xe6,0xa6,0xf1,0xf5,0x0f,0x3f, + 0x16,0x4e,0x1e,0xb6,0x01,0x86,0xf8,0xbc,0xa1,0x09,0x4b,0x9a,0xff,0x05,0xfe,0x1c, + 0xbf,0x8e,0xea,0xeb,0xde,0x01,0xff,0xa3,0xf3,0xda,0x68,0x68,0x79,0x47,0x76,0xfd, + 0xc3,0xd7,0xe8,0x6b,0xd2,0xca,0xc5,0x6e,0xa2,0xcf,0x4f,0x66,0xee,0x4c,0x54,0x30, + 0xa2,0xd1,0xd0,0x2f,0xa9,0x35,0xbc,0xbb,0x9b,0x33,0xf5,0x7f,0xd0,0x7e,0xb5,0xfe, + 0x99,0x7f,0x43,0xf7,0xf5,0xcb,0x8f,0xc7,0xc7,0xe2,0xb3,0x8f,0x2d,0x78,0xb7,0xfc, + 0x25,0x4a,0xdb,0x19,0xf2,0x0f,0xcb,0xd5,0xc6,0x9b,0x7c,0x36,0x42,0xa3,0xe2,0x41, + 0xcd,0xc5,0xff,0x89,0xec,0x85,0x32,0x55,0x5d,0x84,0xa0,0x77,0x4f,0xa2,0xce,0x54, + 0x67,0x06,0x06,0x61,0x9b,0x54,0x46,0xf9,0xc8,0x3f,0x50,0x3a,0x50,0x75,0x67,0xd5, + 0xff,0xd1,0x60,0xb3,0xfa,0xb8,0xa6,0xc3,0x67,0x6e,0x6b,0x1f,0x84,0xc7,0x35,0xdc, + 0xaf,0xdd,0x85,0xcb,0xf8,0x67,0x20,0xea,0xb5,0xd6,0xf1,0xef,0x97,0xfe,0x6b,0x8b, + 0x77,0x59,0x91,0xa9,0xd9,0xef,0x8b,0xf8,0x3f,0xdd,0x86,0x5e,0x9a,0x57,0x8a,0x20, + 0xa7,0xdb,0xa8,0x30,0x57,0xeb,0xf8,0xa1,0x91,0x3f,0xed,0xc7,0x80,0xfb,0xcd,0x1f, + 0x41,0x68,0xb1,0xa8,0x7f,0x68,0x7f,0x2f,0xc3,0x68,0xef,0x70,0x5b,0x04,0x33,0x36, + 0xcd,0x7e,0x0b,0xc6,0x5a,0xbe,0x61,0xce,0xe0,0xb8,0xcc,0xde,0xd4,0xe9,0x79,0xcb, + 0x15,0x78,0x8d,0xd7,0xc7,0x11,0xba,0xb8,0xeb,0x1f,0x2e,0x45,0xa5,0xf1,0x24,0xe0, + 0xb2,0xf9,0xbd,0x32,0xa6,0xe1,0xb6,0x94,0xcb,0x43,0xbe,0x3f,0x32,0x32,0x4c,0x13, + 0xde,0x36,0x86,0x1b,0xab,0x5a,0xb3,0xf0,0x8f,0xa9,0x9d,0x85,0xf3,0xfd,0xe5,0xdc, + 0x37,0x5a,0x3c,0xaa,0x9e,0x5f,0x83,0x66,0x6e,0x40,0x9e,0x83,0x86,0x6f,0xb7,0xe9, + 0x3f,0x54,0x7c,0x12,0x5e,0xc4,0x4f,0xef,0xe6,0xd1,0xe2,0x4c,0xfd,0x9f,0x15,0x88, + 0x7f,0xf6,0xb5,0x05,0x12,0xea,0x26,0xf6,0x5e,0xac,0x3b,0xb2,0xd5,0xf4,0x2a,0x57, + 0x94,0xeb,0xbb,0xa1,0xda,0xbc,0x32,0xc6,0xfe,0x10,0x38,0xda,0xa6,0x47,0x29,0x9e, + 0xd5,0xea,0xc6,0x3f,0xfb,0x60,0x7a,0x62,0xc9,0xa6,0xa6,0xb7,0xa0,0x47,0x0b,0x98, + 0x32,0xc2,0x00,0xb8,0x5e,0x9a,0x4a,0x40,0xee,0x1d,0xad,0xcb,0xf6,0xff,0xb8,0xf8, + 0xcf,0xca,0x6e,0x1e,0xe4,0x9e,0x2b,0x98,0x19,0x49,0xaa,0xba,0x79,0xe5,0x9c,0x76, + 0x45,0xdd,0xcf,0x16,0x1f,0x9d,0x1f,0x0e,0x3c,0x5b,0xb1,0x0b,0xa2,0x46,0x2c,0xec, + 0xce,0xff,0xf2,0x11,0xfe,0xa9,0xe5,0xbe,0x07,0x2e,0x4b,0xf1,0xd3,0x70,0x6d,0x9f, + 0xf7,0xf1,0x4f,0xeb,0x70,0x41,0xab,0x1a,0xf4,0x76,0xca,0xef,0xf3,0x67,0xb5,0xaa, + 0xdb,0x0a,0x4e,0xca,0x46,0x86,0xff,0x9c,0xff,0xa4,0x76,0x01,0x2d,0x46,0xfe,0x7a, + 0x79,0xb8,0xef,0x63,0x68,0xe8,0xc7,0xd9,0x18,0x85,0x3f,0xeb,0xb5,0x7d,0xfe,0xa6, + 0x8e,0xfe,0xb5,0x2f,0xea,0x4f,0x47,0x56,0x8d,0x3e,0x33,0xec,0xe4,0x6b,0x1c,0xc8, + 0x79,0x4a,0xb9,0xd0,0xd6,0x90,0xf2,0x8e,0xc9,0xe7,0xd5,0x0b,0x73,0x66,0xeb,0xbe, + 0x31,0xb9,0x1e,0x86,0xd5,0x6b,0xcd,0xd0,0x09,0xf9,0x6c,0x4c,0x14,0x82,0x1e,0x9f, + 0xff,0xb5,0xdf,0xf2,0xff,0x1c,0xc7,0x0f,0xad,0x3a,0xaa,0x76,0x77,0x84,0xf4,0x18, + 0x04,0x46,0xd5,0xb3,0x08,0x84,0xde,0x5c,0x50,0x8d,0xa7,0xe4,0x0c,0xff,0xa7,0x5f, + 0x59,0x2b,0xed,0xb6,0xe3,0xcb,0xfb,0x8d,0x00,0x47,0x6b,0xee,0xc3,0x6d,0x66,0xa8, + 0x2f,0x32,0x87,0xea,0x1f,0xde,0xa9,0x53,0x21,0x44,0x97,0xff,0x67,0xe2,0x48,0x26, + 0x9e,0xf8,0x84,0x36,0xb5,0x5f,0x25,0x5a,0xf8,0x6a,0xd5,0x22,0x96,0xb3,0x07,0xe0, + 0x2b,0x74,0xaa,0xc7,0x89,0xdf,0x35,0x6a,0x2e,0xff,0xc3,0x29,0x34,0x73,0xd3,0x29, + 0x5e,0x39,0x6c,0x12,0x63,0x47,0x1a,0xd1,0xfe,0x28,0x10,0xa3,0x94,0xc9,0xc7,0x3c, + 0x06,0x76,0x3d,0x84,0xf2,0xb3,0xda,0xa9,0x18,0xf9,0xbb,0x10,0x1f,0x8e,0xed,0x10, + 0x47,0x46,0xd2,0x81,0x51,0xb9,0xe7,0x22,0xfe,0x8f,0x75,0x7d,0xe3,0x71,0x6e,0xf9, + 0x63,0x8d,0x5a,0xbc,0xfe,0x04,0x9f,0xf2,0x1a,0x3c,0x4e,0xa7,0x32,0xfe,0xcc,0xa3, + 0x8a,0x5d,0xff,0x19,0xc7,0xef,0x52,0x03,0x69,0x47,0x16,0xbb,0xf6,0x58,0xfe,0x68, + 0xd3,0x93,0xc4,0x08,0xa2,0x53,0xdd,0xf6,0xeb,0x42,0xbc,0xe4,0xf8,0x7f,0x10,0x06, + 0x73,0x1d,0xbc,0xf4,0xbc,0x4f,0x98,0xc1,0xb7,0x6a,0x08,0x08,0xed,0x16,0xfb,0xaf, + 0xdc,0x0c,0xff,0xe7,0x04,0xe1,0x1f,0x3e,0x23,0x75,0xe5,0xb7,0xd9,0x4f,0xf9,0x63, + 0x7c,0x4b,0xf4,0xca,0xe5,0x6c,0x72,0xc9,0xde,0xad,0xd3,0x86,0xf3,0x6a,0xd8,0x1b, + 0xf1,0x87,0x85,0x3f,0xa4,0x89,0x3b,0xe3,0x97,0xa4,0xeb,0x1f,0xfa,0x6b,0xd8,0x61, + 0xbe,0x0b,0x92,0x80,0x77,0xbb,0x00,0x4e,0xec,0x08,0xbe,0xa7,0x86,0x9b,0x0e,0xf3, + 0x6f,0x40,0xb8,0xcf,0x1f,0x96,0x5c,0xfc,0x9f,0xab,0x32,0xfe,0x31,0xe3,0x1c,0xbf, + 0xde,0xf0,0xdb,0x69,0x92,0xfe,0xd1,0x07,0x9e,0x34,0xde,0xb4,0x02,0x85,0x19,0xfe, + 0x4f,0xb6,0xff,0x47,0xb7,0xf1,0x39,0xab,0xef,0xf5,0x3d,0x8e,0xeb,0xf3,0x8f,0x16, + 0x3f,0xfc,0xe2,0xfa,0x3f,0x7e,0x91,0xff,0xa5,0x5a,0x44,0x20,0x78,0x2c,0x77,0xde, + 0x98,0xfa,0x8d,0xc0,0xeb,0xe6,0x2a,0x51,0x08,0x51,0xde,0xe0,0x8c,0x6f,0x74,0xd5, + 0x3f,0x44,0x61,0xca,0x56,0x21,0x3c,0x6e,0xce,0xa0,0x8c,0xda,0x37,0x22,0x0f,0xc7, + 0xcb,0xc6,0xc7,0xbf,0xd6,0xda,0x7c,0xfb,0x01,0xd8,0x6d,0x54,0x1c,0xf5,0x12,0xb1, + 0x6a,0xb7,0x12,0xb4,0xf3,0x4f,0x85,0x63,0x3f,0x73,0x7d,0x57,0xfd,0xe7,0x61,0x38, + 0x9f,0x98,0x1b,0xb7,0x04,0xdc,0x38,0xcf,0x48,0x34,0x0f,0xe7,0xbd,0xc7,0x44,0xfe, + 0xd7,0x09,0xc7,0x9e,0x66,0xf9,0x7f,0x46,0x23,0x4f,0x64,0x1c,0x41,0x0b,0x79,0x73, + 0x4a,0x19,0xb5,0xfd,0x3f,0xf6,0xf5,0xdd,0xfe,0x1f,0x41,0x8b,0x2d,0x10,0x6e,0x01, + 0x25,0x1c,0x25,0xc3,0x27,0xfd,0x07,0xfe,0x1f,0xc2,0x33,0x86,0x20,0x02,0x2d,0xc6, + 0x8d,0x61,0xa0,0x99,0x02,0x5b,0xf2,0x6a,0xcb,0x23,0x14,0xcd,0xd4,0x7f,0x56,0x32, + 0xf5,0x7f,0x54,0x51,0xa6,0x58,0x04,0x6e,0xf4,0xad,0x2d,0x20,0xfc,0x3f,0x10,0xc8, + 0xce,0x7f,0x57,0x21,0xe3,0xff,0x91,0x10,0xed,0x90,0xd0,0x02,0xeb,0x75,0x3d,0x12, + 0x2c,0x6a,0xea,0x8b,0xb7,0x95,0x09,0xa8,0xd0,0xe4,0xf8,0x33,0xc7,0x4a,0xa3,0x22, + 0xdf,0xca,0x4b,0x8f,0x79,0xa2,0x55,0x94,0xfd,0x29,0x33,0xfa,0x51,0xa8,0xe4,0xcd, + 0xbd,0x2d,0xbc,0x55,0x78,0x84,0x3e,0x76,0xfc,0x87,0x19,0xff,0x8f,0x70,0xfb,0x3c, + 0x9d,0x16,0x0a,0xeb,0x44,0x45,0x20,0x9b,0xff,0xfc,0xd6,0x45,0xf9,0x5f,0x08,0x7b, + 0x2a,0x94,0x7f,0xe6,0x14,0x36,0x92,0x70,0x7c,0xb4,0x21,0x42,0xf9,0xe3,0x91,0x57, + 0x82,0xd5,0x16,0x3f,0x3c,0x1b,0xff,0xd0,0xfd,0x78,0x10,0x0f,0x8c,0x6e,0xe5,0x04, + 0x7b,0x12,0x3d,0x7a,0x65,0x49,0x84,0xc3,0x31,0x83,0x47,0xad,0xfc,0xaf,0x0c,0x1e, + 0xce,0xe9,0xb3,0x9f,0x57,0x81,0xf5,0xaa,0x2e,0x0a,0x21,0x2a,0xbb,0xee,0x5c,0x6a, + 0x4c,0x2b,0x61,0x7d,0xed,0x6d,0x1e,0xf1,0xbc,0xaf,0x3a,0xfa,0x76,0x93,0x5d,0xff, + 0x19,0x61,0x8f,0xf6,0x08,0x0b,0x44,0x2c,0xfe,0x15,0x17,0xc0,0x72,0x88,0xa5,0xe7, + 0xf3,0x78,0x96,0xff,0xc7,0xa9,0xff,0xfc,0x0a,0x74,0xb7,0x7a,0xe9,0xfe,0xf7,0xe9, + 0xf5,0xc6,0x7d,0xf1,0xe2,0x21,0xe5,0x15,0x78,0x3c,0x3b,0xff,0x3d,0x93,0xff,0x25, + 0xb2,0xe3,0x6d,0xfe,0x8f,0x42,0xb4,0x1f,0xc4,0x4b,0x1f,0x8e,0xcf,0x7f,0xcf,0xe2, + 0xff,0x8c,0xfa,0xaa,0x34,0x02,0xa2,0xca,0x98,0x45,0xfb,0xd1,0x45,0x21,0x6e,0xe2, + 0xdb,0x67,0xc6,0xdb,0xf5,0x9f,0x75,0x36,0x0c,0x4f,0xc1,0x56,0x44,0x3b,0xc5,0xc3, + 0x50,0x9f,0xea,0x20,0xda,0xcf,0x0e,0x78,0x14,0xaa,0x45,0xfe,0xbb,0xf3,0x7e,0x83, + 0x9d,0xbe,0x8c,0xfe,0xd9,0x6d,0x5a,0x7c,0x15,0xe8,0x8e,0x56,0x0c,0xa9,0x61,0xe6, + 0xb3,0x19,0x9b,0x19,0xbe,0x50,0x19,0x4c,0xca,0xf8,0x6f,0x1f,0x33,0xca,0x53,0xea, + 0x3d,0x6c,0x33,0xdf,0xcb,0x2b,0xf8,0x4d,0x35,0x28,0x3c,0xac,0x4d,0xb1,0xf2,0xdf, + 0x9d,0xeb,0xc7,0x26,0x6b,0x7f,0xe6,0xa2,0xda,0xe1,0x1b,0x70,0x81,0xef,0x4a,0x85, + 0xa8,0x6c,0xe9,0x89,0xf6,0x6b,0x13,0xbe,0xe5,0x72,0x7d,0xc5,0xf3,0xb1,0xbb,0xe9, + 0xd4,0x01,0xfb,0xf6,0x41,0x9d,0xe4,0xf2,0xff,0x8c,0xa9,0x75,0xbd,0xfe,0x5d,0x1d, + 0x23,0xfc,0x0c,0x88,0x32,0xc8,0xef,0x9b,0x7f,0x8c,0x8a,0x53,0x87,0x9c,0xf8,0x94, + 0x69,0xd7,0xff,0x19,0x93,0x8f,0xa3,0xbe,0xda,0x9d,0x92,0x7b,0xe4,0x7a,0xfd,0x69, + 0x5e,0xff,0x65,0x85,0x0c,0xd9,0x91,0xce,0xd9,0x43,0x54,0xff,0xc7,0x99,0x9f,0x47, + 0x0b,0x37,0x1b,0x7b,0xb5,0x19,0x54,0xdd,0xe8,0x30,0xec,0xd5,0xb6,0x98,0xde,0x6f, + 0xcb,0xb7,0xc3,0x0f,0xcb,0x42,0xa1,0xd0,0x32,0x54,0x8c,0xbf,0x05,0x51,0xc8,0x31, + 0x13,0xff,0xda,0x24,0xf2,0xbf,0xac,0xe7,0x45,0x7d,0x3b,0x85,0x1c,0x41,0x93,0xe0, + 0x31,0x69,0x86,0xba,0x9a,0x0a,0x77,0xfc,0x10,0xca,0x7a,0xaf,0x5c,0xe6,0xca,0xef, + 0xbb,0x2b,0x53,0x7f,0x95,0x84,0xed,0xa4,0xff,0x17,0x48,0x0f,0x44,0x43,0xa0,0x86, + 0x8b,0x96,0x2a,0x3f,0xb6,0xea,0x3f,0x67,0xf2,0xbf,0x4e,0x97,0xd8,0xfa,0x13,0xd5, + 0xd4,0x19,0xa3,0x7a,0x10,0xb5,0x6b,0x1d,0x69,0x24,0x23,0x9f,0xe2,0x05,0x6f,0x5a, + 0x1e,0x8f,0xb7,0xb2,0xf2,0xdf,0xad,0xf1,0x13,0x46,0xd4,0x53,0x15,0x55,0x07,0xd2, + 0xc4,0x57,0x5c,0x21,0x61,0x77,0xfd,0x43,0x7b,0x7c,0xaf,0x96,0xd1,0xe7,0x68,0xf8, + 0x44,0xd9,0xe7,0x3a,0x38,0xaf,0xcf,0x0b,0xfb,0xe8,0xfa,0x47,0xac,0x23,0x19,0xfb, + 0xd8,0xdb,0xe9,0xe2,0xf3,0x24,0x2d,0xb7,0x03,0x79,0x00,0x2a,0x25,0x35,0x29,0xef, + 0x64,0x5d,0x08,0x84,0x28,0xfe,0xe2,0xbc,0x5f,0x97,0xff,0x67,0x04,0xf6,0x31,0x51, + 0xa6,0x98,0x8e,0x90,0x5b,0x23,0x40,0x89,0xf3,0x01,0xcb,0xff,0x63,0xff,0x5c,0xfe, + 0x9f,0x01,0xbe,0x1b,0xf7,0xfb,0x54,0xa8,0x0d,0xb6,0x19,0x21,0x75,0x89,0x15,0x28, + 0x14,0xfa,0x39,0x83,0x7f,0xd2,0xf9,0x5f,0xc2,0x9e,0x1a,0x7f,0xc2,0xab,0xa1,0xe1, + 0xa8,0x23,0xfb,0xab,0xe0,0xfd,0x4f,0x82,0xe7,0xad,0xf9,0x71,0xd5,0x7f,0xfe,0x89, + 0xe5,0xff,0x99,0x30,0xda,0x71,0xd6,0x14,0xfe,0x8d,0x93,0x32,0x55,0x00,0x98,0x57, + 0x3a,0x03,0x0d,0x7d,0x22,0x3d,0x15,0x99,0xfa,0x84,0xe4,0xff,0xf9,0x13,0x9f,0xbd, + 0x18,0xaf,0x16,0xe2,0x17,0xda,0x71,0x21,0xb5,0xcb,0xe7,0x8d,0x23,0xb8,0x91,0xf7, + 0x9f,0x28,0xaf,0x84,0xd7,0x61,0x76,0x2a,0xff,0xa2,0xfc,0xaf,0x0a,0xbd,0x1f,0x1e, + 0xff,0x7c,0xa5,0x48,0x04,0xf3,0xae,0x2d,0xdf,0xa9,0xfe,0x9c,0xfa,0x5f,0x7c,0x58, + 0xb4,0x13,0xee,0x97,0x02,0x29,0xd5,0xcd,0xff,0xe9,0xcf,0x19,0x50,0x76,0x79,0x02, + 0x91,0xbc,0x39,0xed,0x3e,0x43,0x3c,0xb8,0xc4,0x06,0xda,0xba,0xac,0x65,0xb0,0x16, + 0xe1,0xec,0x56,0xaa,0xf8,0x97,0xa9,0xf7,0x42,0xfe,0x9f,0x5d,0x78,0xb5,0x3c,0x6b, + 0x1a,0x11,0x46,0xae,0x14,0xc4,0x60,0x31,0x8d,0xff,0x46,0xfa,0x3c,0xa6,0xba,0xe3, + 0x5f,0x06,0xad,0x1f,0x33,0x99,0x9a,0x91,0xf4,0x54,0x46,0xd2,0x89,0x93,0x23,0xca, + 0x0b,0xc4,0xff,0x09,0xcb,0xab,0x48,0x3f,0xbc,0x84,0x0b,0xc9,0x74,0xf8,0x3f,0x88, + 0x7f,0xe0,0x02,0x6b,0xa0,0x68,0xe9,0x88,0x26,0x26,0xca,0x94,0xed,0x15,0xd2,0x71, + 0x12,0x4e,0x4b,0x33,0x53,0xde,0x71,0xfe,0x1f,0xfc,0x1e,0xab,0xcd,0x82,0x5d,0xa2, + 0xbe,0x1f,0x5e,0xbf,0x5d,0xb6,0x57,0xec,0x84,0x0a,0x30,0x75,0xc1,0x88,0xfe,0x95, + 0x63,0xbf,0x04,0xfe,0x39,0x1a,0xe8,0x57,0xcf,0x05,0x66,0x70,0xe1,0x2d,0xec,0x64, + 0xe9,0x15,0x72,0x52,0x5e,0xcc,0xd6,0x48,0xa2,0x7e,0x54,0x26,0xff,0x6b,0x18,0xf1, + 0xcf,0x2e,0xa8,0x38,0x81,0x07,0x6f,0x26,0x76,0xca,0x90,0x17,0x9a,0x46,0xa4,0xfd, + 0x34,0x3f,0x75,0x90,0xdf,0x96,0xe8,0x0c,0x70,0xd5,0x1d,0xff,0xfa,0x50,0x9a,0x0c, + 0x4f,0xc7,0xa9,0xc9,0x05,0x9b,0x0c,0x0f,0x27,0x66,0x1c,0xf3,0x1e,0x24,0x62,0x5e, + 0xbb,0x40,0x08,0x93,0x0f,0x3d,0xc4,0xb7,0x8c,0xaa,0xcb,0xe1,0x6c,0x86,0xff,0x23, + 0xf0,0xcf,0x9c,0xc1,0x50,0x8d,0xf7,0x46,0xf3,0x99,0x44,0x88,0x68,0x75,0x03,0xf0, + 0x91,0x56,0x37,0xe2,0x4f,0xb6,0x57,0xf2,0x54,0x5e,0xb8,0x33,0x14,0x96,0x5f,0x1d, + 0x5f,0xff,0x90,0xd8,0x3e,0x27,0x95,0x0b,0x94,0x5f,0x39,0xab,0xf9,0x49,0x0b,0x16, + 0x26,0xbd,0x67,0x23,0xaf,0xc0,0x3c,0x7e,0x51,0xfd,0xe7,0xd3,0xbc,0xda,0xf4,0xed, + 0xb2,0xab,0x41,0xf2,0xb4,0xb0,0xf0,0xb1,0x67,0x46,0xa4,0xfe,0xc5,0x55,0x7c,0x9d, + 0x9b,0xff,0x63,0xe5,0x7f,0x95,0xf1,0xb5,0xa3,0x1e,0x0a,0x7b,0x5d,0x87,0xdb,0x28, + 0x39,0xed,0x51,0xbf,0x47,0xde,0x0c,0x0f,0xe5,0x95,0x11,0xff,0xe7,0xb4,0x83,0xaf, + 0x28,0xff,0xeb,0xf1,0xf6,0x2f,0x11,0xa9,0xfb,0x32,0xfb,0x31,0xdf,0xb0,0x10,0xd1, + 0xb7,0xd9,0x79,0xe8,0x34,0xa7,0x24,0x05,0xfe,0xb1,0x7f,0x56,0xfe,0x57,0x62,0x8f, + 0x1a,0xb6,0xfa,0x89,0x10,0xba,0xb6,0x10,0x66,0x57,0x92,0xfd,0x31,0xb8,0x95,0x57, + 0xa4,0xb2,0xea,0x6f,0x08,0xff,0x4f,0x74,0x16,0x0f,0x25,0x58,0xd0,0x0a,0x84,0xa5, + 0x64,0xa7,0x22,0xd0,0x19,0xfe,0xdc,0x33,0x7b,0xf7,0xac,0xbb,0x28,0xfe,0xa5,0x52, + 0xb6,0x57,0x39,0x75,0xbb,0x48,0x97,0xfd,0xb1,0xf9,0xa8,0x30,0x16,0xa9,0xbd,0x64, + 0xfc,0xab,0x89,0xca,0x3e,0x53,0xe0,0x63,0xf1,0xe4,0xc2,0x74,0x7c,0x04,0xf1,0xc0, + 0x62,0x78,0x97,0x93,0x7f,0x60,0x3c,0xfe,0x31,0x28,0xed,0xc8,0x33,0x05,0x0d,0xf1, + 0xd7,0xef,0x54,0xe3,0x4d,0x15,0x92,0x65,0x91,0xe5,0xa9,0xc6,0xdf,0x41,0x70,0x99, + 0x2f,0xce,0x52,0x9a,0xdb,0xff,0xb3,0x5f,0xad,0x34,0x82,0x08,0x7b,0x7c,0x8f,0x40, + 0x41,0xab,0x27,0x9e,0xbb,0x5d,0xdb,0x07,0x53,0xc9,0x4c,0x2f,0x86,0x3c,0xed,0xae, + 0x45,0x6a,0x56,0xfc,0x0b,0x9c,0xfc,0x2f,0x85,0xef,0x62,0x95,0x46,0xa4,0x48,0x38, + 0xa2,0x43,0x8d,0x5e,0x12,0x7e,0xa4,0x07,0x8d,0x9a,0x2c,0xfe,0x8f,0x4f,0xf0,0x9f, + 0x29,0xff,0x2b,0x48,0x40,0xa8,0xc4,0x93,0x90,0xb7,0x44,0x7a,0xa0,0x9a,0x3a,0x62, + 0xdc,0xd9,0xf4,0x56,0xab,0x30,0xc4,0xe7,0xb3,0xfd,0x3f,0x6c,0x1e,0x3e,0xdd,0xa7, + 0x4e,0x1a,0x94,0x18,0xe5,0xbf,0xc5,0x2e,0x6b,0xbc,0x1e,0xdf,0xef,0xfb,0x5a,0x83, + 0x91,0x8b,0xf8,0xc7,0xa9,0x9f,0x43,0xf8,0xe7,0x1c,0x63,0x86,0xef,0x07,0xf2,0x49, + 0xf5,0x20,0x05,0xee,0x07,0x3b,0x1e,0x4c,0x23,0xa2,0x8e,0x39,0xc6,0x8b,0x25,0xb3, + 0x44,0xfd,0x43,0x67,0x3f,0x65,0xe1,0x1f,0x1d,0xd4,0xe7,0xd8,0x31,0xf5,0xa8,0x54, + 0xa9,0x7a,0x3b,0x03,0x09,0x2e,0x10,0x11,0x15,0x82,0x5e,0x73,0xcb,0xc5,0xf1,0xaf, + 0xbc,0x5d,0xc4,0xe7,0xb9,0x2d,0xf0,0x2c,0xb4,0x41,0xa8,0x89,0xd2,0xfc,0x2d,0x44, + 0x14,0x6e,0xaf,0xe0,0x6d,0x65,0x7a,0xf4,0xa2,0xfc,0xf7,0x5d,0xed,0xdb,0x0c,0x75, + 0x30,0x30,0x82,0xbb,0xf5,0x4a,0xe3,0xc7,0xf1,0xad,0x36,0x22,0xf2,0x54,0xb0,0x36, + 0x25,0x10,0xb9,0x28,0xff,0xfd,0x1c,0x9f,0x6d,0x04,0xe9,0x26,0x0f,0xd2,0x6d,0x6b, + 0xcd,0x0e,0xc2,0x99,0x02,0x07,0x4d,0x11,0x11,0x73,0xc7,0xbf,0x04,0x3b,0xba,0x69, + 0x61,0x5c,0xee,0xe3,0xa7,0xa0,0xb2,0xd9,0xbf,0x41,0xb6,0x32,0xc8,0xd2,0xfd,0x2f, + 0xc4,0xa9,0xf1,0xf1,0xaf,0x06,0xf0,0x99,0xb2,0xae,0xa6,0x13,0xc1,0x74,0x6d,0x2c, + 0x97,0xc2,0x5e,0xcd,0xba,0xde,0x2f,0x80,0x10,0x3b,0x90,0x15,0xff,0x7a,0xa2,0x34, + 0x94,0x54,0x87,0xd9,0x75,0x54,0x08,0x31,0xa1,0xbe,0xcb,0x76,0x68,0x02,0x11,0xa5, + 0x58,0x29,0xdc,0xaf,0x6c,0x5b,0x9f,0xc5,0xff,0xa1,0xfc,0xf7,0x6e,0x33,0x14,0x56, + 0x55,0xa6,0x72,0x91,0xb8,0x34,0x8f,0xf2,0x53,0x72,0x51,0x51,0x27,0x98,0x9f,0xf2, + 0x2f,0x46,0xf3,0xdc,0xfc,0x9f,0x32,0x09,0xad,0xbf,0x3e,0xe3,0x80,0x5a,0xd3,0x3e, + 0x89,0x80,0xc1,0x68,0x9e,0xce,0x10,0x51,0x88,0x8e,0x36,0xec,0x72,0x58,0x05,0xf2, + 0x68,0x5e,0x56,0xfd,0x43,0xca,0xff,0x32,0xe7,0x05,0x43,0x11,0xef,0x64,0xf8,0x9f, + 0x6d,0x0d,0x89,0x19,0x11,0x9b,0xff,0xa3,0xca,0xf5,0xec,0x08,0xbf,0x3b,0x95,0x9f, + 0xc5,0xff,0xb9,0x6a,0x27,0x8c,0x71,0x51,0xe4,0x70,0x44,0xd9,0x8f,0x0f,0x5e,0x80, + 0xfa,0x5c,0x4f,0x9b,0xf5,0x61,0x46,0x42,0x65,0xf2,0x73,0xd9,0xf5,0x0f,0xd1,0x7e, + 0xbd,0xe5,0x7f,0x44,0xbe,0x09,0x3e,0x88,0x37,0x6c,0xf7,0x7d,0x46,0x7e,0x0a,0x05, + 0xbc,0xc2,0xc1,0xbf,0x29,0x37,0x8e,0xac,0x6f,0x18,0xf2,0xf7,0x14,0xc7,0x33,0xf1, + 0x26,0xc4,0x3f,0x8f,0x41,0x99,0xe6,0x5d,0xc4,0x5e,0xe5,0x1d,0xda,0x8c,0x84,0x7a, + 0x13,0xde,0xff,0xaa,0xc4,0x8c,0x61,0x3c,0xb2,0x81,0x34,0x2a,0x69,0x98,0x0c,0xfe, + 0x89,0xc3,0xe6,0xc8,0x1e,0x98,0x72,0xc0,0xfb,0x55,0xf6,0xba,0xf1,0x70,0xd1,0x8c, + 0x98,0x6a,0x4c,0x7d,0xdd,0xaa,0xa0,0x68,0xb0,0x52,0xbe,0x2a,0x3c,0xe3,0xa8,0x77, + 0x59,0x53,0x67,0x16,0xff,0x30,0xc9,0x2b,0x74,0x5c,0x54,0xfd,0x20,0x43,0x08,0x82, + 0x60,0xf3,0xc9,0x35,0x16,0xd3,0xb7,0xb5,0x2c,0xed,0x1b,0x57,0xff,0x70,0x27,0x9c, + 0xe0,0xd5,0x29,0x7f,0xa2,0x58,0xf0,0x37,0xc8,0xdb,0x79,0xd6,0x86,0x31,0xba,0xfa, + 0x0c,0xab,0x4b,0xa2,0xf0,0xa8,0xb3,0x7e,0xa8,0xff,0xc5,0xa9,0x30,0x2a,0x99,0xf8, + 0xec,0xc5,0x39,0x69,0x7d,0x2b,0xea,0xd1,0x99,0x57,0x27,0xe5,0x28,0x9c,0x0e,0xd7, + 0x0f,0x8a,0xd0,0x98,0x3d,0x3f,0x6d,0x1a,0xe5,0x83,0xcf,0x3e,0xb0,0x20,0x45,0x66, + 0x4e,0x9a,0xdb,0xf9,0xd9,0x43,0x56,0x3e,0x14,0xf1,0x57,0x4f,0xb0,0x37,0x61,0xb6, + 0xe1,0x1b,0x75,0xf5,0x67,0x31,0x11,0xff,0xf4,0x40,0x20,0x1c,0xdc,0x04,0x53,0xd1, + 0x6c,0x51,0x35,0xad,0xa6,0x11,0xdc,0xbf,0x57,0x9a,0x79,0xbb,0x3a,0x52,0xed,0xab, + 0x73,0xab,0x29,0x7e,0xf1,0xae,0x9b,0xff,0xac,0xee,0x03,0xbd,0x4f,0x2d,0xc3,0x4f, + 0xf0,0xe7,0x52,0x25,0x97,0x78,0xd1,0x48,0xe1,0x8f,0xa9,0xec,0x4c,0x5c,0x37,0x79, + 0x17,0x0f,0x8c,0x5e,0x54,0xff,0x10,0xc7,0x43,0xac,0x64,0x0d,0xc0,0x6e,0x2d,0xc4, + 0xbd,0xb9,0x04,0x14,0xcb,0x7c,0x7d,0x79,0x1a,0x33,0xf9,0x9a,0xed,0x53,0x0f,0x40, + 0x15,0x3b,0xb0,0x02,0xec,0xeb,0xe7,0x2d,0xa5,0x6a,0xab,0xa6,0x6f,0xbb,0xbc,0xd3, + 0x3c,0x03,0x95,0xb1,0xfb,0x56,0xb2,0xd7,0xb5,0xd7,0x82,0xf5,0xfd,0x9f,0xde,0x20, + 0x8f,0xa6,0x5e,0x08,0x56,0x1d,0xf4,0x75,0xcb,0xa9,0x4c,0xfd,0xe7,0xfc,0xb3,0x25, + 0x4f,0x4a,0x0d,0x80,0xfb,0xa9,0x0f,0xf9,0xd3,0x7a,0x9d,0xe2,0xef,0x10,0xf3,0x39, + 0x73,0x00,0xf5,0x4f,0x9c,0x8b,0x88,0xea,0x87,0xf2,0xf0,0xc5,0xf5,0x7f,0x10,0x3f, + 0xdb,0xc2,0x79,0x38,0xb7,0xbe,0x3a,0x71,0xff,0x51,0x99,0x4e,0xcd,0x4b,0x65,0xf5, + 0xff,0x32,0xe3,0x2e,0xff,0xcf,0x0b,0xb6,0xb0,0x4f,0x0f,0x24,0xbc,0x9b,0xd8,0xd2, + 0x18,0x9d,0xf2,0xb8,0xfb,0x5f,0xf4,0x83,0xc3,0x87,0x1f,0x50,0x76,0x83,0x8a,0xc2, + 0x8d,0x03,0x94,0x6f,0x02,0x54,0x11,0x48,0x10,0x53,0x4b,0xb3,0xfb,0x7f,0x8d,0xd8, + 0xfd,0xbf,0x32,0x8e,0x20,0x0a,0x2c,0xea,0x56,0x45,0x6e,0x9c,0x58,0x4f,0x92,0x65, + 0xea,0xf3,0x48,0x13,0x45,0xd9,0xe7,0xb4,0xff,0xc1,0x4e,0x04,0x3b,0xa5,0x54,0xe9, + 0x94,0xd1,0x46,0xa5,0x12,0x4c,0xd1,0x91,0xca,0x7e,0xbf,0x76,0xfd,0x67,0x77,0xf5, + 0x6f,0xb1,0x1e,0x0c,0xff,0x87,0x1d,0xdf,0x4d,0x03,0xa1,0xe2,0x31,0xa7,0x1e,0x42, + 0x8b,0x66,0xad,0xae,0x02,0x57,0x75,0x71,0xbc,0xbe,0x5e,0xaf,0xe5,0xa7,0x8f,0x1c, + 0x08,0xb9,0xf3,0xbf,0x8e,0x3a,0x78,0x38,0x30,0xa2,0x66,0x88,0xf1,0xb1,0x4a,0xc4, + 0xf3,0x24,0xdc,0x5d,0x79,0xd4,0x93,0x74,0xe5,0x7f,0xa5,0xdc,0xfe,0x1f,0xcb,0x71, + 0x91,0x3b,0x80,0x16,0x70,0x29,0x17,0x1b,0xb1,0xdd,0x5c,0x04,0x8e,0x33,0xfe,0x1f, + 0x3b,0xff,0x3d,0x03,0x03,0x50,0x50,0x1f,0x6b,0x9b,0xb1,0x2d,0x6f,0x79,0xe0,0x0d, + 0xd5,0x3a,0x52,0xe4,0xc2,0x03,0x2a,0xc5,0xbf,0xea,0xa8,0x7e,0xe3,0x61,0x8b,0x08, + 0x14,0x46,0xfc,0xf3,0x21,0xd4,0x25,0x7d,0xe1,0x0e,0x04,0x42,0x85,0x75,0xe6,0x8c, + 0xac,0xfa,0x3f,0x57,0x51,0x91,0x67,0x2b,0x2c,0x68,0xb8,0x12,0x07,0x08,0xf6,0xb0, + 0x74,0x29,0xf5,0x4b,0xf9,0x7f,0xae,0xb6,0xe7,0x47,0x4c,0xd4,0x29,0xa8,0xd3,0xd5, + 0x9a,0x2b,0x43,0xea,0x77,0xa4,0x7a,0xca,0x20,0xfb,0x0b,0xfc,0x1f,0x47,0xf8,0x83, + 0xf4,0x35,0xc8,0xb7,0xf6,0x53,0x33,0xcc,0x3c,0x77,0xfe,0x57,0xc6,0xff,0xd3,0x64, + 0x3d,0x2f,0xb5,0xbd,0x80,0xc7,0xf8,0xcc,0x70,0x84,0x10,0xe0,0xde,0xf1,0xfc,0xe7, + 0x4c,0xfd,0x67,0xe6,0xda,0x88,0x6d,0xe3,0x21,0x2d,0xaf,0x86,0x89,0x8a,0xd0,0x34, + 0x9f,0x97,0xec,0x7f,0x31,0x2c,0x12,0xe1,0x45,0x21,0xa0,0xd3,0xfc,0x7b,0x49,0x5f, + 0xa2,0x23,0x08,0x27,0xec,0xfa,0xcf,0xce,0xf5,0x1d,0xff,0x4f,0xb1,0x9b,0x08,0xa4, + 0xd5,0x33,0xd1,0x8f,0xe9,0x28,0xe0,0xc2,0xc8,0xce,0xff,0x1a,0xb2,0xf9,0x1e,0x56, + 0xe2,0x33,0x0a,0x6f,0x93,0x05,0xbc,0xd3,0xb2,0x77,0xbc,0xd6,0xb8,0x18,0xff,0x58, + 0x45,0xf6,0x9c,0xea,0x85,0xef,0x10,0x22,0x5a,0x4c,0x1e,0x1e,0xe5,0x3a,0xae,0x2f, + 0xf2,0x5c,0x5c,0xff,0x27,0xbb,0xdb,0xc5,0x90,0x9d,0x26,0x3f,0x84,0x78,0x66,0xba, + 0x15,0xaf,0xb1,0x7f,0x6e,0xfe,0x8f,0x10,0xae,0xb4,0x05,0x87,0x21,0x43,0xf9,0x5f, + 0xce,0xf8,0x0c,0xff,0x47,0x76,0x39,0x22,0x44,0xdb,0x8b,0x04,0xd5,0x3f,0x94,0x6a, + 0xc9,0x22,0x1f,0xcf,0xbd,0xa4,0xff,0xc7,0x12,0x26,0x50,0x44,0x6c,0x26,0xe2,0x19, + 0x70,0x4e,0x1d,0xcf,0xbd,0xc8,0xff,0xe3,0xaa,0xfe,0x47,0x69,0xef,0x04,0x84,0x8a, + 0x2b,0x8c,0xfb,0xf0,0xc3,0xc4,0xf9,0x39,0x24,0x5d,0xec,0xff,0x11,0xfc,0x1f,0x51, + 0xed,0x30,0xa5,0x1e,0xc5,0x23,0x5d,0x9c,0xe9,0x5a,0x4c,0xa9,0xa5,0x8a,0xd0,0xae, + 0xfc,0xaf,0x9c,0xbe,0xec,0xe7,0x15,0x42,0x9b,0x14,0x32,0x24,0xcd,0xd3,0xc9,0x49, + 0x88,0x5d,0xa2,0xfe,0xb3,0xe5,0x4f,0x23,0xda,0x79,0x7a,0x1a,0x2b,0x3f,0x23,0x88, + 0x58,0xab,0xc1,0x23,0xe6,0x33,0x93,0xff,0x35,0x31,0xeb,0xfe,0xad,0x30,0x16,0xac, + 0xee,0x24,0x20,0x54,0xbc,0x9d,0x51,0x45,0x68,0xbc,0xff,0x4b,0xd5,0xff,0x91,0xb3, + 0x27,0x8a,0xd6,0xc3,0x62,0x54,0x5c,0xb5,0xc4,0xf7,0x7e,0xb5,0xd3,0x9e,0x7f,0xc4, + 0x3f,0x6a,0x66,0xda,0x15,0x72,0x33,0x4a,0x84,0xc0,0xed,0x23,0x2a,0x2e,0x3c,0x77, + 0xfe,0x97,0xab,0xff,0x97,0xdd,0xed,0x02,0xd1,0xcb,0x53,0xbc,0xb2,0x6d,0xfe,0x10, + 0x1b,0x2e,0x79,0x2a,0x31,0x33,0x46,0xfe,0x1f,0xdd,0xb9,0x7e,0xe7,0x82,0x4b,0x7c, + 0x2f,0xbb,0x8d,0x90,0x39,0xbf,0x82,0x8f,0x10,0x34,0xb2,0xfc,0x3f,0x4e,0xfc,0x2b, + 0xc3,0xff,0x71,0xbe,0xdf,0xdf,0xc1,0xe3,0xc6,0x8c,0x66,0x6f,0x94,0xbd,0xce,0xd3, + 0x47,0x5c,0xf9,0xef,0xb1,0x3b,0xb4,0x34,0xff,0xe7,0x0d,0x9b,0x08,0xf4,0x1b,0xf8, + 0x73,0xfb,0xbc,0xa8,0x77,0x49,0xf9,0x9b,0xfc,0x63,0x3c,0x72,0xf5,0x72,0xf9,0x90, + 0xa3,0x7f,0x10,0xff,0x48,0x2e,0x7d,0x2e,0x14,0xcb,0x10,0x9c,0x26,0xb3,0x95,0x40, + 0x43,0x73,0x0a,0x2d,0x6c,0x56,0xff,0x0b,0xc7,0x7e,0xf5,0xc8,0xc7,0x6d,0x47,0xd0, + 0xe3,0x70,0x36,0x5e,0x1f,0xf5,0x0d,0xcb,0x95,0xf0,0x5d,0x3e,0x7b,0x68,0x7c,0xfe, + 0x17,0xa1,0x35,0x73,0xfe,0xb7,0x49,0x7f,0x6a,0x69,0x22,0xd3,0xe3,0xdb,0xbf,0xf6, + 0xf6,0x67,0xa3,0xf2,0xe4,0xfe,0x3d,0xc6,0xb5,0xd9,0xf9,0x5f,0x1a,0x4f,0xeb,0xab, + 0xbb,0xd9,0xeb,0xab,0xd3,0x4f,0xb7,0x11,0xf6,0xe8,0x33,0xa9,0xc2,0xc9,0xed,0xf0, + 0x10,0x94,0x99,0x59,0xf9,0x5f,0x7a,0xb6,0xff,0xc7,0x22,0x02,0x49,0xdd,0xf1,0x50, + 0xab,0x14,0x06,0x1f,0x24,0xad,0x42,0x1c,0x19,0x7b,0x31,0x36,0xd1,0xde,0x4d,0x17, + 0x8f,0xd8,0x8d,0x30,0xb6,0xa3,0x85,0xad,0x6f,0x55,0xf4,0xf2,0xef,0xe2,0x17,0x17, + 0xa6,0x8c,0x9b,0x4c,0xfe,0x17,0x97,0x32,0xfe,0x9f,0x0c,0x11,0x68,0xcc,0xa8,0x37, + 0xd7,0x75,0x8a,0x42,0xd0,0x16,0x50,0x74,0xf4,0x9b,0x99,0xed,0xff,0x11,0xc2,0xc7, + 0xc6,0x79,0x98,0xfd,0x7b,0xdc,0xe8,0xd5,0x09,0xaa,0x70,0x56,0xff,0xaf,0x15,0x69, + 0xfe,0x4f,0x97,0xcb,0xfe,0x0e,0x41,0xb2,0x77,0xfa,0xe2,0xab,0xdb,0x58,0x88,0x3e, + 0xbd,0x13,0xbe,0xec,0xfc,0x2f,0xc7,0xff,0xb3,0x34,0x33,0xbe,0x27,0x16,0xe8,0xf5, + 0x6e,0x2f,0x0a,0xa9,0x3d,0x7a,0x65,0x2a,0x3b,0xff,0x4b,0xf8,0x7f,0x2a,0x88,0x9f, + 0xf9,0xa2,0x9d,0x96,0xd2,0x87,0x1f,0xb2,0x1e,0x89,0x51,0xe1,0xcd,0xa4,0x95,0x0a, + 0xed,0xf2,0xff,0x5c,0x95,0xee,0x7f,0xd1,0x2d,0xbf,0xcf,0x89,0x28,0xf5,0xf7,0x54, + 0xdd,0xb1,0x07,0xaa,0x6e,0x9b,0x9f,0x2c,0x0e,0xf1,0x31,0x49,0xa4,0x66,0xbb,0xf2, + 0xbf,0xd2,0xfe,0x1f,0xff,0x87,0xe5,0x67,0xe3,0xe9,0xe7,0x3d,0x89,0xfa,0x79,0xde, + 0x80,0xbf,0x15,0x2d,0xda,0x49,0x98,0x47,0xf6,0x2b,0x13,0xff,0xb2,0xd7,0x4f,0xbe, + 0x48,0x7b,0xd7,0xab,0x53,0x0b,0xe2,0xcd,0x4f,0xc1,0x6b,0x7c,0x77,0x6a,0x5d,0xb7, + 0x7c,0xde,0xf8,0x68,0xc5,0xdc,0xe8,0x82,0xb1,0xe6,0xd1,0x56,0x87,0xff,0x93,0xae, + 0xff,0xac,0x22,0xec,0x29,0x7d,0xda,0x0c,0xa4,0x54,0x4e,0xfc,0x52,0xf2,0xff,0x9c, + 0x0d,0x8c,0xf0,0xfd,0xed,0x81,0xa8,0xda,0x23,0x27,0x1d,0xfb,0x68,0xd7,0x7f,0xce, + 0xb3,0x3e,0x2b,0x3d,0x11,0xd3,0x3c,0x6b,0x45,0x86,0xb2,0x3c,0x87,0x0d,0xe0,0x13, + 0x55,0x18,0x79,0x54,0xff,0x47,0x77,0xee,0xc7,0xae,0xff,0x23,0xe6,0xff,0xd1,0x54, + 0x70,0x93,0xf0,0x9f,0x90,0xff,0x07,0x08,0x48,0x4c,0x35,0xf2,0xb2,0xea,0x1f,0xba, + 0xfa,0x5f,0x50,0x22,0x12,0x5f,0xb0,0xf6,0x81,0x9d,0xf0,0x9a,0xc8,0xcf,0x6a,0x1e, + 0x81,0x8f,0xcc,0x39,0x08,0x3c,0xca,0x4d,0x57,0xfe,0x57,0x66,0x3d,0xc0,0x9f,0x45, + 0xd9,0x43,0xe9,0xac,0xfe,0x34,0x35,0x2a,0x1d,0x6d,0xc6,0xd5,0x00,0xd7,0x1b,0x05, + 0xa3,0xe5,0x2e,0xfe,0xb3,0x3b,0xfe,0x85,0x42,0xc2,0xb7,0xc1,0x1b,0x92,0xd2,0xb4, + 0x67,0xe1,0xe8,0x18,0xb8,0x44,0xfd,0xc3,0x50,0xbf,0x80,0x6d,0x4f,0x2b,0x3e,0x53, + 0xdd,0xc8,0x66,0xc2,0xaf,0x89,0xc1,0x35,0x8a,0x0f,0x72,0x1d,0x04,0x46,0x6f,0x4e, + 0xde,0x9a,0xf1,0xff,0xd8,0xf5,0x9f,0xbd,0xe1,0x2a,0x31,0x51,0x54,0xf8,0xce,0x9f, + 0x61,0x44,0xef,0x86,0xc4,0x32,0xaa,0x0f,0x79,0x71,0xfd,0xe7,0x6f,0x93,0xdb,0x87, + 0xff,0xf7,0x51,0xf5,0x3b,0x1e,0xe1,0x08,0x1a,0xf6,0xd6,0x00,0x7e,0xd1,0xf1,0xb2, + 0xe8,0x15,0xcb,0x99,0xdb,0xff,0xb3,0xc0,0xea,0xff,0x55,0x2b,0x1f,0x36,0x11,0xff, + 0x84,0x7c,0x3f,0x2a,0xf6,0x05,0x76,0xf3,0xba,0x61,0xff,0xf5,0xf2,0xfd,0xf0,0x51, + 0xb2,0xd4,0xb8,0xfa,0x7a,0x37,0xff,0x39,0x27,0x3d,0x3f,0x1f,0x0a,0xd8,0x3c,0xcf, + 0x7c,0x9a,0xa6,0xe5,0x4d,0xa0,0x46,0xa8,0xde,0x3a,0x3c,0x75,0xa5,0x91,0xd5,0xff, + 0x82,0xf2,0xdf,0x5f,0x73,0xe6,0xbf,0x08,0xd5,0x72,0x1c,0xd5,0x8e,0x98,0x9f,0xbd, + 0x1d,0x23,0xda,0x47,0x30,0xe7,0x4e,0x5f,0x56,0xfe,0xd7,0xe5,0x6e,0xfc,0x43,0xfa, + 0x67,0x94,0x6d,0xc6,0x6d,0xe3,0x75,0xa6,0x6c,0x69,0xd4,0x69,0x86,0x9a,0x9d,0xff, + 0x65,0xe3,0x9f,0x5c,0x81,0xee,0xa2,0xde,0x45,0x45,0x77,0x68,0x0f,0x67,0x10,0xe0, + 0x83,0xa9,0xe9,0x59,0xf1,0x2f,0x25,0x5b,0xff,0x0c,0xce,0xdf,0xc3,0xa8,0x7e,0x5a, + 0xd0,0x3a,0xd2,0xcd,0x82,0x94,0x91,0x91,0x9d,0xff,0xe5,0xc2,0x3f,0x0d,0xdc,0xff, + 0xb6,0x77,0x09,0xbc,0x97,0x3e,0xa2,0x9e,0x1f,0xad,0x4e,0x14,0x50,0xfe,0x97,0xfd, + 0xbc,0xae,0xfa,0xcf,0xb6,0x3d,0x2a,0x4f,0xc0,0x26,0x91,0x11,0xdf,0x6c,0x39,0x82, + 0x72,0xc8,0xff,0x63,0xaf,0xb7,0x74,0xfd,0xe7,0xd6,0x34,0x3f,0x96,0x1c,0x41,0xde, + 0xc5,0x56,0x1b,0x2c,0xad,0xb8,0x42,0x44,0xc4,0xc6,0xd7,0x3f,0x24,0xfb,0x1b,0xf5, + 0xda,0xfd,0xa7,0xd4,0x8d,0x6b,0xae,0x71,0x22,0x32,0xd2,0x87,0x22,0x22,0xe6,0xea, + 0x7f,0x5a,0xe3,0xc6,0x3f,0x8f,0x40,0x65,0x63,0x70,0xbd,0xe7,0xcb,0xe2,0xc8,0xff, + 0x23,0x88,0x2b,0x38,0xbe,0xcb,0xed,0xff,0x71,0xea,0x3f,0x5b,0xd5,0x9e,0x2b,0xa3, + 0xe4,0x08,0x82,0x59,0xb0,0xd4,0xf0,0x16,0x7d,0x55,0xb1,0xa9,0x32,0xe3,0xea,0x1f, + 0xda,0xcf,0x4b,0xf9,0xfe,0xea,0x0a,0xb9,0x31,0x5d,0xf6,0xb0,0xb9,0xcc,0xe8,0xb1, + 0xe2,0x2f,0x99,0xfc,0xaf,0x4d,0x6e,0x3c,0xb0,0x4f,0x6b,0x30,0x16,0xfe,0x2a,0x5d, + 0xdf,0x98,0xe2,0x5f,0xca,0x39,0x78,0x3a,0x3b,0xfe,0x65,0x8d,0x6f,0x48,0xc3,0x00, + 0x7d,0x9e,0xe1,0xff,0x95,0x3c,0x05,0x5e,0x4c,0x5f,0xa1,0xe5,0x7d,0x91,0x11,0xef, + 0xca,0xff,0xca,0xe0,0x1f,0x99,0xf0,0xcf,0x57,0xc0,0xbf,0x82,0x41,0x7b,0xcc,0xe1, + 0xff,0xc0,0xf4,0x71,0xfe,0x1f,0x48,0x7b,0x7b,0xb4,0x5c,0x7c,0x5e,0x43,0x14,0xbe, + 0x56,0xc8,0x11,0x64,0x78,0x4b,0x58,0x1f,0xdf,0xd7,0xae,0x1b,0xf3,0xb3,0xf2,0xbf, + 0x14,0x1b,0xff,0xe4,0x5a,0xc2,0x4d,0x71,0x8f,0x02,0xe9,0x7e,0x6a,0x7d,0xd2,0x23, + 0xda,0x74,0xe3,0xca,0x38,0xb8,0xfa,0x5f,0x28,0x16,0x9e,0x59,0x47,0x78,0xe9,0x14, + 0x35,0x2e,0xd9,0xe0,0xad,0xb0,0x1c,0x41,0x76,0xc4,0x33,0xab,0xff,0x45,0x24,0x1b, + 0xff,0x54,0x93,0xbf,0x68,0xc4,0x85,0xa0,0x58,0x7d,0x24,0x8b,0xff,0xac,0x5a,0xf5, + 0x7f,0x14,0xbf,0xf5,0xbc,0x55,0x9a,0xaf,0xb3,0x2b,0x2a,0x1a,0xa1,0x8a,0x23,0x47, + 0xe1,0x9f,0x58,0x76,0xff,0x0b,0x0b,0xff,0x24,0xf2,0x2c,0xfc,0x53,0x1e,0x53,0x53, + 0xec,0x51,0xed,0x50,0x1a,0x11,0x29,0xb9,0x0f,0xfe,0xcd,0x8e,0x6c,0xfe,0xf3,0xc4, + 0x05,0xc4,0x4f,0xa0,0xa4,0xc8,0x01,0x6d,0x36,0x8b,0x8e,0xa9,0x73,0x98,0x09,0x0f, + 0xd8,0xdf,0x4b,0x1b,0xe8,0xe1,0xf9,0xe1,0xa6,0x8c,0xff,0xc7,0xae,0xff,0x9c,0x27, + 0xbe,0x56,0x4a,0xcc,0x0c,0x07,0xd6,0x8b,0xb2,0x87,0x57,0xe2,0x11,0x69,0x05,0xfc, + 0xab,0x91,0xd5,0xff,0x22,0xe6,0xf4,0x3f,0x45,0xfc,0xf3,0x11,0x9f,0x95,0xf2,0x2d, + 0xf2,0xbe,0x11,0xf8,0x2d,0xbf,0x8e,0x80,0xd0,0x05,0xde,0xd7,0xfe,0x98,0xee,0xcf, + 0xf2,0xff,0xa4,0xf1,0x40,0xbe,0x15,0xd6,0xb9,0x97,0xcf,0x8c,0xcb,0x4b,0x33,0x1a, + 0x38,0x45,0x3b,0x88,0x2c,0xff,0x4f,0x09,0xe5,0xbf,0xcf,0x4d,0x15,0xf4,0xd0,0xfe, + 0x3d,0xfe,0xbd,0x25,0xfe,0x7d,0xde,0xd3,0x1a,0xd5,0xff,0x41,0x20,0xf4,0x81,0xf1, + 0x01,0xdf,0x1b,0x45,0xfc,0xe3,0xf2,0x57,0x6b,0x16,0xfe,0xf1,0xd7,0x16,0x1d,0x8e, + 0x89,0xc4,0xf6,0x11,0xa6,0xe5,0xac,0x82,0xd0,0x30,0xde,0xf6,0x61,0xd8,0x8b,0xf8, + 0x47,0x0d,0xcb,0x8f,0x3a,0xf1,0xb2,0xd2,0x0c,0xff,0x59,0xa0,0x3b,0x75,0xfe,0xad, + 0x01,0xb1,0x4d,0xeb,0x17,0x1a,0xec,0x21,0xb8,0x86,0xf4,0x95,0xbb,0xff,0x45,0xf6, + 0xfe,0x2b,0xe1,0x95,0x8a,0x7c,0xe9,0x36,0x8e,0xa4,0x7f,0xf4,0x0a,0xb2,0xef,0x9b, + 0x9c,0xf7,0xd5,0x53,0x68,0x79,0xcb,0x27,0xa7,0xed,0xcb,0x98,0x7f,0x53,0x40,0xf7, + 0x50,0xfd,0xe4,0x85,0xc9,0xe2,0xb3,0xa8,0x88,0xaa,0x09,0xff,0xb8,0xfa,0x5f,0xa4, + 0xe3,0x5f,0xe9,0xf1,0xf7,0xf6,0xe7,0x6f,0x94,0x1f,0x4c,0xfb,0x7f,0x10,0x1a,0x9d, + 0x36,0x51,0xd5,0x24,0x9b,0xb7,0x68,0xf6,0xf3,0x26,0x44,0xfe,0xfb,0xf7,0x52,0xc4, + 0xf7,0x10,0x85,0x10,0x17,0xb6,0x6e,0xab,0x33,0x8e,0xc0,0xf5,0xa8,0x78,0x51,0xb1, + 0x9f,0x47,0x9b,0xec,0x77,0xfb,0x7f,0xb6,0x58,0xf8,0xa7,0x6f,0x5d,0x52,0x17,0xc2, + 0xa6,0x67,0x36,0x7b,0x2b,0xd8,0x6b,0x02,0x98,0xa1,0x45,0xee,0xe6,0x81,0x65,0xfe, + 0xec,0xfe,0x17,0x21,0x67,0x9b,0x2f,0x51,0x76,0xb6,0xbc,0x89,0x49,0xa2,0xfe,0x8f, + 0x47,0x30,0x58,0xf4,0xc0,0x5d,0x94,0x18,0x9e,0xf1,0xff,0xdc,0xe6,0xb3,0xf9,0x09, + 0x0b,0xf8,0x6c,0x3d,0x34,0xe8,0x55,0x3c,0x2d,0xf0,0x80,0x16,0x3a,0x40,0xfd,0xbf, + 0xf4,0x6e,0xd2,0x3f,0x73,0x9a,0xdc,0xfc,0x9f,0x90,0x4a,0xfc,0x67,0xef,0xae,0x03, + 0xef,0x9b,0x7f,0x84,0xda,0x56,0xff,0x06,0xaf,0x2f,0xa7,0x4b,0xa9,0x25,0xb3,0x7b, + 0x0e,0x4e,0x6b,0xf8,0x7d,0xed,0x91,0x53,0x4e,0xff,0x9d,0xc4,0x44,0x51,0xff,0x90, + 0xec,0xfb,0x77,0xcd,0x33,0x5a,0x43,0xbf,0xff,0x65,0xef,0x93,0xf0,0x41,0xc5,0x77, + 0xfa,0x29,0x11,0x2c,0xf1,0x71,0xc5,0x3c,0xea,0x00,0x32,0x3c,0xf5,0x22,0xff,0x0f, + 0x95,0xf1,0xb1,0xf0,0xb3,0x74,0x36,0x71,0x76,0x4e,0x38,0x0a,0x11,0x39,0x00,0xdf, + 0xe3,0xb3,0xa3,0xb8,0x3e,0xc3,0x17,0xfb,0x7f,0x92,0x8c,0xe2,0x5f,0xf5,0xc4,0xf7, + 0x7e,0x9f,0x27,0x0d,0x16,0x9d,0xd4,0x73,0x57,0x40,0xdd,0xcf,0xa7,0x47,0xf1,0x48, + 0x32,0xb3,0xbf,0xce,0xf8,0x7f,0xa8,0x11,0x95,0xb5,0x0c,0xf4,0x9e,0x96,0xa8,0xa1, + 0xea,0x0c,0x7c,0xbb,0xe9,0x79,0x93,0x9e,0x2a,0x67,0x7f,0x97,0x9a,0xe8,0x14,0xd9, + 0x16,0x61,0x44,0x6b,0xda,0x7b,0xca,0x02,0x37,0xe6,0x25,0xdb,0x03,0xd2,0xfe,0xd6, + 0xf4,0xf5,0xed,0xf7,0xbb,0x65,0xa2,0x5d,0xff,0xb9,0x23,0x24,0x88,0xe2,0x82,0x78, + 0x73,0x3a,0xda,0x1d,0x0d,0x56,0x78,0xcb,0xe1,0x44,0x6f,0xd5,0x92,0x75,0x3d,0x1d, + 0xe0,0xc4,0xbb,0x1d,0xfc,0x13,0xf6,0xda,0x81,0x42,0x99,0x96,0x41,0x43,0x2a,0x34, + 0x5a,0x3c,0x26,0x5d,0x88,0x35,0xd0,0x7a,0xc8,0xae,0xff,0x23,0xd2,0xca,0xe2,0x99, + 0x6e,0x5f,0x23,0xf0,0x5e,0xa4,0xf6,0xa8,0x2f,0x21,0xff,0x23,0xbc,0xd7,0x54,0x6f, + 0xf8,0xf6,0xca,0x85,0xee,0xfa,0x87,0x16,0x0c,0xde,0x50,0x24,0x84,0x03,0xa2,0x10, + 0x90,0xac,0xeb,0xfd,0x88,0x18,0xa7,0xc1,0x13,0x4d,0x95,0x5f,0xc9,0xd7,0x58,0xb5, + 0x7d,0x3b,0x82,0xff,0x93,0x26,0xbd,0x8b,0x85,0x91,0x12,0xc4,0x95,0x04,0x1a,0x6e, + 0x15,0x9a,0x1a,0xf9,0x36,0x5e,0x91,0x2a,0x9d,0x93,0x7b,0x9d,0xb3,0xff,0x4a,0x66, + 0xfc,0x3f,0x42,0x38,0xa6,0xd2,0x46,0xa6,0x73,0xfd,0x94,0x61,0xf5,0x9f,0x6f,0x2c, + 0x82,0xbd,0xb1,0x19,0xd1,0xbc,0xe1,0xdc,0x90,0xc3,0x1f,0x5e,0x92,0xf6,0xff,0xf8, + 0x83,0xde,0x02,0x93,0x0a,0x21,0xfe,0xac,0x16,0xef,0x7f,0x6b,0xb2,0x6e,0x38,0x14, + 0xee,0x68,0x7a,0xf9,0xf7,0x6c,0x8e,0xb1,0x20,0xec,0x75,0xf1,0x9f,0x6d,0xfe,0x4f, + 0x4a,0xe4,0x7f,0x11,0x10,0xc2,0xfb,0x3f,0xaf,0xd7,0x0e,0x78,0x4f,0xca,0xa3,0xea, + 0x05,0x6d,0x1e,0x41,0x23,0x57,0xfe,0xbb,0xcd,0xff,0x49,0x38,0xf3,0x83,0x1b,0x99, + 0x31,0x8a,0x88,0x3d,0x29,0x07,0xd5,0x59,0x7a,0x15,0xf7,0x85,0xe5,0x0c,0xff,0xb9, + 0x3f,0x9e,0xd6,0x27,0x3a,0x73,0x88,0x04,0xb7,0xf3,0x73,0xd6,0x36,0xaa,0x54,0x30, + 0x82,0x50,0xa8,0xca,0xd4,0xdf,0xb6,0xf1,0xcf,0xa2,0x8c,0xb7,0xe7,0x0d,0xe3,0x71, + 0x7e,0x4d,0xea,0xf2,0xef,0xb2,0x2b,0xa4,0x9f,0xb5,0x95,0x1d,0x53,0xcf,0x32,0x3d, + 0xdb,0xff,0xa3,0xe0,0x7c,0x6e,0xbe,0xc9,0xa7,0xa4,0xd7,0xdb,0x52,0xd8,0xa6,0xe9, + 0x6b,0xf3,0xe6,0x78,0x0a,0xf4,0xdd,0x45,0xba,0xb9,0x63,0x8e,0x9b,0xff,0x5c,0x92, + 0xf6,0xff,0xbc,0x27,0x93,0xe1,0x48,0x03,0xa1,0xa7,0xf8,0x5c,0xfe,0xaf,0x3b,0xa5, + 0xeb,0xf9,0x4b,0xe6,0xae,0xb8,0x6f,0x89,0x77,0x1c,0xff,0x59,0x58,0xff,0x8e,0x54, + 0x26,0x31,0xa7,0xa7,0xad,0x5e,0xf3,0xf1,0x8e,0x63,0x30,0x16,0xa9,0x2f,0xf2,0xaf, + 0xcc,0xe2,0x3f,0xa7,0xed,0xdd,0x66,0xbb,0x2c,0x4c,0xfc,0xd3,0x43,0xec,0x15,0xa8, + 0x8f,0xa0,0x5a,0x5b,0x4c,0x88,0x3d,0xea,0xdb,0x04,0xec,0xe2,0xfe,0xa7,0x9b,0x3d, + 0x16,0xb0,0x91,0x05,0xed,0x76,0x7d,0x28,0x8a,0xc0,0xf8,0x6d,0xd8,0xd7,0x52,0xbd, + 0x4c,0xfd,0x49,0xbb,0x7e,0x89,0xfc,0xaf,0xf6,0xec,0x46,0x60,0x46,0x6c,0x13,0x1b, + 0xe1,0xfb,0x1a,0x05,0x5f,0x7a,0xa5,0xb3,0xde,0x1c,0xff,0x4f,0xa1,0xc7,0xd5,0x08, + 0xb5,0x4d,0x0f,0x99,0xa5,0x9a,0x48,0xc4,0x98,0x6a,0x04,0xe3,0xac,0xdd,0xd1,0x3f, + 0x8e,0xff,0x67,0x65,0x97,0x6e,0x35,0x02,0xa3,0x36,0xa3,0xfd,0xb7,0xd5,0xa3,0x6a, + 0x97,0x53,0x1a,0x11,0x51,0x16,0x70,0xef,0x2f,0x32,0xf5,0xde,0xd3,0xfe,0x9f,0x75, + 0x2f,0xa1,0x35,0xff,0x96,0x00,0x06,0xd2,0x90,0xf1,0x7e,0xe1,0x3c,0x4a,0x7c,0x3b, + 0xab,0x9d,0x82,0x79,0xc6,0xba,0xd1,0xf2,0xaf,0x64,0xea,0xf9,0xd8,0xfe,0x9f,0x5f, + 0xc9,0x73,0x94,0x83,0x16,0x10,0x7a,0xbb,0xf3,0xc5,0xc6,0xb9,0x86,0x3a,0x28,0xef, + 0x51,0x67,0xd0,0x0a,0x6c,0x95,0x99,0xb3,0x7e,0x96,0xdb,0xf8,0xe7,0x41,0xa6,0x33, + 0x1b,0xf6,0xf0,0x98,0xd5,0xff,0x54,0x47,0xfc,0x53,0x0f,0xf3,0xb9,0xa7,0x20,0xc3, + 0xd7,0xb2,0xfd,0x3f,0x69,0xd8,0x43,0xdd,0xbe,0x9e,0xe5,0x6d,0xd1,0x0a,0xa3,0x26, + 0xce,0x14,0x95,0xfc,0x3f,0x38,0x63,0x45,0x52,0x06,0x8f,0x51,0xf4,0xd0,0x42,0x9b, + 0x69,0xd8,0x53,0x34,0x24,0xad,0x5e,0x79,0x97,0x11,0xd9,0xe4,0xa9,0x90,0x56,0xab, + 0xd3,0x5b,0xbc,0x9b,0x20,0x37,0x53,0xff,0xb0,0xc4,0xf5,0x7e,0x1d,0xd8,0x73,0x50, + 0x9f,0xb3,0xc0,0xb7,0xa1,0x78,0x0a,0x3b,0xd8,0x58,0xd9,0xe4,0x2f,0x91,0x82,0x99, + 0xfe,0x2c,0xb0,0x5d,0x4c,0x8b,0xbf,0x68,0x9b,0x03,0x14,0xfb,0xd8,0x87,0x50,0x1f, + 0x5d,0x17,0x97,0x11,0x18,0x6f,0x12,0x47,0x5c,0xf5,0x0f,0xb5,0x84,0x68,0x3b,0xe2, + 0xef,0xf4,0x8a,0xf9,0xa7,0x6e,0xa7,0x29,0xb5,0x5f,0xaf,0xf7,0x85,0x3a,0xa4,0xb7, + 0x60,0xac,0xb1,0x8a,0x1d,0xe9,0x94,0x3d,0xe3,0xfa,0x7f,0x89,0x68,0x97,0xea,0x38, + 0x82,0xd4,0xfb,0x8d,0x99,0xf1,0x25,0x4b,0x9a,0x5e,0x25,0xfe,0x73,0xc2,0x3b,0x24, + 0xdf,0x64,0x0f,0xb7,0xfb,0x7f,0x51,0x5a,0xae,0xd5,0x98,0xc9,0xaa,0xff,0xf3,0x72, + 0x28,0x95,0xa7,0x05,0x06,0x24,0xd1,0xaf,0x73,0x2a,0x5b,0x93,0xa9,0xff,0x93,0xf1, + 0xff,0x88,0xef,0xf7,0x00,0x0a,0x03,0x6c,0x23,0xcc,0x30,0xf2,0x5a,0xd9,0x7f,0x23, + 0x44,0x74,0x00,0xff,0xb4,0xab,0xfe,0x0f,0xf9,0x7f,0xda,0xe6,0xa5,0x16,0x06,0x29, + 0xec,0xd5,0x39,0x2f,0x2a,0x1c,0x41,0xbf,0xc5,0x0f,0x79,0x86,0x70,0x04,0xf1,0x5d, + 0xa9,0x85,0x4b,0xbc,0x5d,0x17,0xf5,0x7f,0xc7,0xcf,0x30,0xcd,0xc6,0x24,0x7d,0x3b, + 0x4c,0x1e,0xec,0x84,0x3c,0xa4,0x7e,0x64,0x9d,0x6a,0xca,0xe4,0x87,0x66,0xf8,0x3f, + 0xf5,0x24,0x50,0xd9,0xe7,0xf3,0x3a,0x0a,0x43,0xbe,0xbf,0x93,0xab,0x61,0x2e,0xf9, + 0x7f,0x96,0x78,0x35,0x77,0xff,0x53,0xc3,0xba,0x7f,0xf9,0x0e,0x8e,0xfb,0x2f,0xe3, + 0xca,0x30,0x7b,0xdd,0x48,0x1a,0x33,0x86,0x83,0xad,0xf2,0x6d,0xb0,0x57,0x2f,0xdb, + 0xa8,0x46,0xd9,0x74,0x07,0x5f,0x01,0xdf,0x9c,0xe7,0xa8,0x29,0x14,0x0c,0xdb,0xf1, + 0xd5,0xa7,0x7e,0x73,0xeb,0x44,0xf8,0x61,0x5e,0xb9,0x89,0xe3,0x75,0x17,0xfe,0x19, + 0xb0,0xd5,0xce,0x02,0xd5,0x99,0xcf,0x64,0x20,0x14,0x57,0x6b,0x58,0xa7,0xba,0xbb, + 0xbd,0x22,0xa5,0x56,0xb0,0x52,0x57,0xff,0x53,0x0b,0xcf,0x4c,0x20,0x5a,0xe6,0x7e, + 0xab,0x9e,0xcf,0x59,0xd8,0x6f,0xd4,0xb5,0xee,0xd8,0xc4,0xae,0x81,0x5f,0xc7,0xab, + 0x96,0xf8,0x1e,0x91,0xa7,0x5f,0x9c,0xff,0xa5,0x15,0xbb,0xe2,0x11,0x67,0x8c,0xfa, + 0x96,0xab,0x36,0xca,0x5f,0x36,0xc6,0x8c,0xda,0x97,0x44,0xab,0xbe,0x8b,0xf2,0xbf, + 0x8e,0x09,0x36,0x51,0x83,0xc5,0xe7,0x3c,0x67,0x36,0x34,0xf9,0x46,0xe5,0x39,0xc4, + 0xff,0xa1,0xd6,0xb4,0x70,0x71,0xfe,0x57,0x82,0x89,0xb6,0x17,0x16,0x31,0x69,0x9f, + 0x51,0x59,0x13,0xa9,0x79,0x46,0x16,0x8d,0x18,0xbc,0xd7,0xe3,0xd7,0xee,0x8a,0x7f, + 0xa5,0xdd,0x3e,0xb9,0x21,0x6a,0x7b,0x61,0x08,0x20,0x84,0x5f,0x68,0x54,0xdd,0xc4, + 0xca,0xb5,0x2e,0x33,0xd0,0x8f,0x97,0x4a,0xd8,0xb3,0x69,0xf3,0x7f,0x7a,0xbd,0x5a, + 0x81,0x2f,0xda,0xe1,0xcc,0x4f,0x4b,0x65,0x24,0x12,0x0e,0x44,0x73,0x57,0x43,0xc2, + 0xec,0x02,0x57,0xfe,0x3b,0xb3,0xfa,0x7f,0x51,0xf5,0x83,0x19,0x40,0xfd,0xbf,0xfc, + 0xbb,0x2c,0x37,0xd7,0x02,0x35,0xf9,0xa9,0xb2,0x92,0x17,0x94,0x2a,0x73,0x61,0xa2, + 0x9c,0x67,0xd5,0xff,0x11,0xcf,0x7b,0x4f,0x87,0xb0,0x5f,0x46,0xc1,0x09,0xe9,0x2c, + 0x3c,0x09,0x75,0x3e,0xaa,0x6f,0x93,0x38,0x47,0x81,0x8c,0x94,0xbc,0x24,0xe7,0x22, + 0xfc,0x33,0xe6,0x9d,0x64,0x9c,0xe1,0x0d,0xbc,0x60,0x58,0x2e,0xa2,0x44,0x30,0x82, + 0xcd,0x78,0xaa,0x73,0xde,0x31,0xe2,0xff,0x64,0xf2,0xc5,0xe0,0xb8,0x9d,0xff,0x1e, + 0x22,0x20,0x94,0x50,0x77,0x14,0x4d,0x85,0x47,0x78,0x65,0xb4,0xa0,0x87,0x1d,0x57, + 0xf6,0x77,0x0a,0xd7,0xd0,0xa8,0xee,0xe2,0xff,0x08,0xfc,0xd3,0x1c,0x0e,0xac,0xed, + 0xdc,0x2d,0x85,0x60,0x4d,0x02,0x57,0x4b,0x1b,0x3e,0xc8,0x22,0xaa,0x50,0xb7,0x4d, + 0xa4,0x2a,0x37,0x65,0xf3,0x7f,0xd2,0x49,0x76,0xbf,0xa0,0xf9,0x4c,0xaa,0x09,0x86, + 0xd7,0x87,0x9b,0xd3,0x81,0xa4,0xdc,0x71,0xf9,0xef,0x3c,0xd3,0xff,0x7d,0x3b,0x09, + 0x7a,0x65,0x52,0xd6,0xe1,0x10,0xcc,0x69,0xf4,0x89,0x0a,0x51,0x0a,0x15,0x82,0x2e, + 0x36,0x0d,0x7b,0xfc,0x68,0xc6,0xff,0xf3,0x4d,0x14,0xea,0x2c,0xff,0xd8,0x1b,0x4a, + 0xc3,0xe2,0x82,0x51,0xc4,0xdb,0x4f,0xb3,0x86,0x03,0xbe,0xd1,0xe6,0x8b,0xfb,0xbf, + 0x0b,0x37,0xe3,0x0b,0x50,0xef,0xf3,0xed,0x12,0xd7,0xb7,0x3d,0x90,0xca,0x64,0xf2, + 0xbf,0x65,0xf8,0x6c,0x4e,0xfc,0x8b,0xf2,0x19,0xbb,0x94,0x4a,0xc3,0x73,0x1d,0x2a, + 0xde,0x35,0x76,0x20,0xec,0x7a,0x16,0x1a,0x5d,0xed,0xe6,0xff,0x64,0xc5,0xbf,0x70, + 0x3d,0x8c,0xaa,0x15,0x01,0x8f,0xb5,0x3f,0xb5,0x3d,0xa8,0x52,0x98,0x8d,0x3a,0xf8, + 0x6d,0xb4,0xd0,0x81,0x01,0xe7,0x61,0x15,0x9f,0x31,0xe4,0x59,0xc2,0x1a,0x60,0x05, + 0x39,0x46,0xd2,0x11,0xb1,0x03,0x79,0xcb,0x9b,0x8e,0x67,0xfa,0x5f,0x40,0x9a,0xff, + 0x7c,0xbd,0x7c,0x18,0x9e,0xe1,0x75,0x86,0xef,0x6f,0xbc,0xaa,0xde,0x0b,0x75,0x29, + 0xff,0x2c,0x76,0xd8,0xfc,0x48,0xab,0xeb,0xf3,0x65,0xf1,0x9f,0x45,0xff,0xaf,0xab, + 0xc5,0x67,0x65,0x5c,0x28,0x6c,0xe8,0x5d,0x17,0x95,0xcf,0xb6,0x9c,0x8b,0x53,0xc5, + 0xc8,0x66,0xd1,0xe1,0xa2,0xbf,0x20,0x59,0x9c,0xd5,0xff,0x42,0x4c,0xb2,0xed,0x1f, + 0x03,0x5f,0x72,0xc2,0x7b,0x70,0x88,0x57,0x19,0xae,0x7e,0xc4,0x13,0x5c,0xfc,0x9f, + 0xf5,0xe3,0xe2,0x5f,0x54,0x4f,0x03,0xed,0xf3,0x96,0xb4,0x62,0x61,0x82,0x3f,0x79, + 0xc2,0xe9,0x1f,0x97,0xa9,0xff,0xcc,0xde,0x44,0x21,0x94,0x88,0x2c,0x87,0x57,0xe1, + 0x7e,0x5e,0x96,0x15,0x01,0xbc,0xb8,0xff,0x85,0x3d,0x7b,0x7d,0xd3,0x49,0x68,0xdf, + 0x1a,0x4d,0xcf,0x27,0x0b,0x99,0x97,0xec,0x7f,0xea,0xa7,0x22,0xcf,0xa7,0xa1,0x21, + 0xbe,0x40,0xa7,0xb6,0xa7,0x89,0xaa,0x44,0xda,0x23,0x64,0x11,0x81,0x2e,0x11,0xff, + 0xb2,0x68,0xcf,0x2c,0x2f,0x36,0xe1,0x18,0x9c,0xb5,0x77,0xe8,0xe9,0xc2,0x2c,0x99, + 0xf8,0x9a,0x8b,0xff,0xdc,0x87,0xf6,0x51,0x44,0x43,0x16,0xdb,0x6d,0xc1,0x87,0xa4, + 0x4b,0xf5,0xbf,0xc8,0x86,0x31,0x10,0x2f,0x9a,0xd2,0x39,0x3e,0xc2,0x95,0xf1,0xff, + 0x58,0xf8,0xc7,0xea,0xf6,0xa5,0x59,0xe3,0x03,0xd5,0xf0,0x4b,0x14,0xae,0xb4,0x3b, + 0xc2,0xff,0xc5,0xfc,0xf7,0xf6,0x36,0x45,0x24,0x82,0x95,0xc0,0x63,0xae,0x08,0x91, + 0x79,0x09,0xff,0x8f,0xf0,0x36,0x20,0xec,0x11,0xfc,0x13,0x6f,0x94,0x9e,0xd7,0x9a, + 0x81,0x1a,0xbb,0xff,0x85,0xad,0x7f,0xfa,0x5d,0xfd,0xdf,0x5b,0x4f,0x41,0x43,0xcb, + 0xbf,0xd1,0x83,0x7f,0xa8,0xd8,0x1e,0x1e,0xab,0xdf,0x7d,0xa6,0x9e,0xc9,0xa6,0x1c, + 0xbb,0xff,0x97,0x68,0x0b,0x4b,0xfe,0x31,0xaa,0x17,0x94,0xf1,0x90,0x88,0x7f,0x78, + 0x38,0xc7,0x85,0x7f,0xd4,0x74,0xfc,0xab,0x17,0x36,0x51,0xff,0x53,0x93,0x65,0x3a, + 0xc2,0x53,0xff,0xd3,0xec,0xfe,0x5f,0x6a,0x4e,0x9f,0x64,0xe5,0xbf,0x17,0xf5,0x55, + 0xec,0x42,0xfb,0x55,0xda,0x6a,0x3d,0x66,0x63,0x97,0xd6,0x84,0x82,0x24,0x9e,0x37, + 0x13,0xff,0x2a,0x75,0xc5,0xbf,0x94,0x1f,0xb1,0xca,0x88,0x3a,0x98,0x15,0x58,0x84, + 0xf1,0xfd,0x4f,0x27,0xe2,0xfd,0x8b,0x87,0x92,0xe8,0x6e,0xeb,0xa2,0xbe,0x74,0x3c, + 0x2b,0xea,0x8e,0x70,0xb9,0xe2,0x5f,0xf0,0x17,0xe2,0x5f,0xcb,0xac,0xf5,0xc0,0xd2, + 0xfd,0x4f,0xed,0xf1,0x41,0x4d,0x4f,0xaf,0xb7,0xcf,0xa5,0xa0,0x5f,0xaa,0x87,0x7c, + 0x53,0x14,0x42,0x74,0x79,0xe4,0xb2,0xfb,0x7f,0xa5,0xf1,0x4f,0x17,0xc2,0x1e,0x6d, + 0x8d,0x54,0x29,0xca,0x98,0xdf,0x7a,0x7f,0x26,0x22,0x36,0x93,0xfa,0x5f,0x5c,0xdc, + 0xff,0xcb,0xd2,0x3f,0x52,0xa8,0xf7,0x33,0x41,0x5c,0x2d,0xed,0x4e,0xe0,0x38,0x37, + 0xa4,0xe2,0xc6,0xfc,0x80,0xe3,0xcf,0x71,0xfa,0xbf,0x2f,0xcb,0x7d,0x83,0xaf,0x82, + 0x10,0x5a,0xfc,0xf6,0x5f,0xc3,0x4a,0x71,0x24,0x20,0xbe,0x68,0x20,0xfe,0xb3,0x33, + 0x7e,0x47,0x8c,0xf4,0x95,0x15,0xff,0xd2,0x9f,0xe7,0x57,0xa5,0xf2,0x97,0xc8,0xaf, + 0xc2,0x73,0xb6,0x47,0xe8,0x0f,0x7c,0x1e,0xf9,0x7f,0x0e,0x8c,0xeb,0x7f,0x21,0xb2, + 0x77,0xdf,0x37,0x49,0x9f,0xe0,0xd7,0xd7,0x07,0xa7,0xa5,0x8c,0x86,0x41,0xc5,0xe2, + 0xaa,0xff,0xe3,0xe0,0x9f,0x53,0x82,0xb6,0x5a,0x3f,0xf4,0xd9,0x58,0xf9,0xab,0xa8, + 0x7f,0x44,0xdb,0x8b,0xf3,0xea,0x99,0xf8,0x5c,0x1d,0x11,0x51,0xa9,0xa3,0xcf,0xa9, + 0xff,0xe9,0x1f,0xe8,0x6e,0x6b,0xd9,0x71,0x72,0x5b,0x05,0xd5,0x02,0x36,0x68,0x3c, + 0x94,0x08,0xa5,0x0a,0x96,0xb3,0xc3,0x1c,0xf5,0x89,0xe1,0x3d,0xcd,0xa6,0xbb,0xfb, + 0x7f,0xa9,0xd6,0xf3,0x4e,0x7d,0x9d,0xc6,0x1f,0x50,0x6f,0x42,0x35,0xb5,0x52,0xb7, + 0x3d,0x42,0x3a,0x3e,0xef,0x09,0x8f,0xe9,0xc6,0x3f,0xf6,0x7e,0x56,0xe8,0x73,0x44, + 0xa1,0xb9,0x7d,0xb0,0xd5,0x0c,0xf5,0xd9,0x1a,0xc9,0x10,0xfc,0xe7,0x0c,0xfe,0x71, + 0xec,0xcb,0x59,0xf6,0x02,0x2a,0xea,0xb5,0x49,0xf9,0x5d,0x38,0xb4,0xcc,0x79,0x5e, + 0xea,0xb8,0xed,0xea,0x7f,0x11,0x07,0x7b,0xfc,0xe7,0x2c,0x7d,0x5b,0xb0,0xa7,0xf8, + 0x58,0xfc,0xb4,0x4d,0x3c,0xf8,0x0e,0xd4,0xdf,0x32,0x21,0xc9,0x82,0x99,0x7c,0xb1, + 0x4c,0xfd,0xc3,0xd7,0x45,0xb7,0x74,0x61,0xdd,0xce,0x5b,0xb4,0x67,0x71,0x6a,0x87, + 0xc8,0x7f,0xb7,0xef,0x9f,0x2b,0x2e,0x3e,0x73,0x17,0x4c,0x05,0x35,0x09,0x7f,0xd0, + 0xbb,0x2d,0xfe,0x2d,0x45,0x64,0x0a,0x08,0xe1,0x5c,0xd4,0xff,0xc2,0xa2,0x49,0x77, + 0x59,0x8d,0x83,0xdf,0x82,0x27,0xd8,0x54,0xab,0x10,0xe2,0xcf,0x61,0xaa,0xe6,0x4d, + 0x16,0xa5,0x34,0x57,0xfe,0x97,0xb5,0xde,0xaa,0x11,0x36,0x77,0x34,0x55,0xa8,0xa8, + 0x7f,0x4c,0x72,0x8b,0x0d,0x7a,0xab,0x68,0x7e,0xa8,0x10,0x59,0x16,0xff,0xc7,0xee, + 0xff,0xfe,0xb8,0xfc,0xcb,0xe8,0x0b,0x46,0xfd,0x21,0xdf,0x7a,0xf2,0x6f,0xe8,0x8f, + 0x1f,0x9d,0x9f,0x2c,0xa7,0xfc,0x1a,0x5c,0x21,0xdd,0xe3,0xea,0x1f,0x8a,0xe7,0xdd, + 0x2d,0xf6,0xef,0x73,0xc1,0xff,0x6b,0xd4,0x27,0xe7,0xb5,0xda,0x01,0xff,0x49,0xf9, + 0xfd,0x84,0x68,0x8d,0xba,0xab,0x70,0x78,0x4a,0x36,0xfe,0x99,0xcd,0x7d,0x47,0xe5, + 0xd3,0x38,0x7e,0x76,0x8b,0xef,0x18,0xae,0x96,0x81,0x8a,0x6b,0xa3,0x0b,0x8f,0xa1, + 0x99,0x1e,0xa0,0xfa,0x9c,0xfd,0x6e,0xff,0x8f,0xc8,0xff,0xaa,0x06,0x35,0xde,0x34, + 0x0c,0x6b,0xf4,0xea,0xdb,0x62,0x0f,0x06,0xa6,0x43,0x2c,0x1e,0x88,0x7a,0x13,0x9e, + 0x4a,0x88,0xf1,0xe9,0xa9,0x82,0x58,0x40,0x07,0x37,0xfe,0xd9,0x0f,0x3a,0x57,0x89, + 0x0f,0xb6,0x4d,0x0d,0x44,0x22,0x01,0x16,0x62,0x49,0xe1,0x66,0xf7,0xec,0xcc,0x8b, + 0x51,0x85,0x16,0xb8,0x2c,0x2b,0xff,0xbd,0x64,0xbf,0x36,0x55,0x57,0x37,0xb0,0x81, + 0xc0,0x8f,0x28,0x7f,0x01,0x94,0x4a,0x7d,0x13,0xc7,0xeb,0x27,0x61,0x69,0x59,0x0c, + 0xa1,0x17,0x8b,0xe5,0x86,0xb3,0xfa,0x5f,0xec,0x86,0xaa,0xc4,0xda,0xb8,0x7c,0x0c, + 0xfe,0x1c,0x2f,0x37,0x42,0xef,0x78,0x6b,0x61,0x34,0x55,0x95,0xf2,0x6f,0x95,0x5f, + 0x84,0xfe,0xe6,0xaa,0xb1,0x7c,0x1f,0x73,0xd5,0x7f,0xb6,0xf0,0x0f,0xcc,0x3c,0x2a, + 0x8f,0xc2,0x1f,0xa1,0xa1,0xd5,0x7f,0xf6,0xd7,0x63,0x30,0x22,0x5d,0x6f,0xfa,0xdf, + 0x93,0x9f,0x86,0xb3,0xea,0xf5,0x07,0xfc,0xe6,0xf8,0xfa,0xcf,0x52,0xfd,0xa6,0x09, + 0x44,0x62,0x7c,0x41,0x7b,0x7c,0x99,0x6f,0x8f,0xfc,0x20,0xbc,0xaa,0xd5,0x0f,0xae, + 0xdd,0x28,0x07,0xf9,0x30,0x29,0x3a,0x2e,0xb7,0x8e,0xe7,0xff,0x04,0xbc,0xdf,0x67, + 0xef,0x22,0x5a,0x4e,0x24,0x83,0x7b,0x70,0x63,0xb5,0xa6,0xb5,0x72,0x58,0xa5,0x8a, + 0x49,0xdd,0x50,0x63,0x74,0xc5,0x3a,0xee,0xb1,0x5f,0xaf,0xdd,0xff,0x22,0xee,0x2d, + 0x65,0x87,0xa8,0xda,0x2a,0xa8,0xf9,0x9e,0x08,0x6c,0xe0,0xa1,0x94,0xba,0xe5,0xe6, + 0x75,0x90,0xe0,0x21,0x3c,0x95,0x9b,0xc9,0x7f,0xa7,0xfe,0x5f,0x8f,0xf1,0x19,0x15, + 0x79,0x8b,0xd8,0x6b,0xb0,0x32,0x5e,0x3e,0x27,0xb8,0x88,0xdd,0xab,0xaf,0xe4,0x33, + 0x53,0x35,0xdf,0x65,0x3f,0x6d,0xdc,0xc3,0xa7,0x25,0xbc,0x11,0x16,0x71,0xfc,0x3f, + 0x82,0xff,0xac,0xd5,0x81,0x3f,0xdc,0xf1,0x9e,0xfe,0x0c,0x24,0xe1,0xf6,0x0d,0x4d, + 0x0b,0xe0,0x25,0x3d,0x94,0xf2,0xc5,0x9b,0xd7,0x06,0x53,0x2a,0x42,0x23,0x45,0x2e, + 0xca,0xca,0xff,0x3a,0x67,0x6d,0x13,0xce,0x35,0x5d,0x80,0xeb,0xf8,0xcc,0x41,0xb9, + 0xce,0xb8,0x20,0x35,0x98,0x13,0x3e,0x94,0xbe,0x8b,0x0b,0xa9,0xa1,0xcf,0x6f,0x8c, + 0xe3,0x3f,0x8b,0xb0,0x60,0x5c,0x2e,0x83,0x17,0xa4,0x24,0xb9,0x05,0x40,0xea,0x87, + 0xba,0x5e,0x5f,0xbc,0xfc,0x66,0x52,0xd4,0xa6,0x2f,0x2e,0xb9,0xfc,0x3f,0xa8,0x7f, + 0x1e,0x83,0x99,0x10,0x1b,0x64,0x1a,0x5b,0x47,0xf5,0x0f,0x47,0xe5,0xdb,0x61,0x05, + 0xaa,0x75,0x95,0x12,0xe1,0x57,0xa0,0x85,0x52,0x0d,0xb6,0xc1,0xb9,0x7e,0x1b,0xfc, + 0x54,0xd9,0xdb,0x36,0x23,0x59,0xba,0x9c,0x5d,0x81,0x78,0xaf,0x5c,0x57,0xbf,0xcb, + 0x2e,0x83,0x95,0xbd,0xc2,0x23,0x54,0x8f,0xc0,0xef,0xbf,0x2f,0x53,0x87,0xb3,0xf2, + 0xdf,0x45,0x35,0x89,0x54,0x30,0x7c,0x85,0x9f,0x77,0x45,0xf4,0x84,0x1a,0x6e,0x5f, + 0x00,0x1d,0x06,0x4e,0x63,0x92,0x15,0x30,0x14,0x0c,0x15,0xd8,0x03,0x6e,0xfe,0x8f, + 0x72,0x5a,0x69,0xa0,0x22,0xcf,0x41,0x7e,0xb8,0x71,0x76,0xc2,0x37,0x2c,0x5f,0xc1, + 0x0e,0x1b,0x0d,0x9d,0xeb,0x50,0x43,0x1b,0x87,0xf5,0x79,0xc9,0x50,0x74,0x7c,0xfe, + 0xbb,0x95,0xed,0x9e,0xb2,0xfc,0x21,0x0a,0xf5,0x7f,0xa7,0x7e,0x04,0xb1,0xe2,0x63, + 0xad,0x63,0x7a,0x7d,0xd1,0xf8,0xfc,0x77,0x0a,0x82,0xb4,0xfa,0xd7,0xe3,0xfe,0xe5, + 0x60,0x3c,0xbc,0x2c,0x14,0xbf,0x72,0x2a,0x1c,0xfc,0x89,0x20,0x3a,0x56,0x18,0xa7, + 0xda,0xaa,0x0c,0xdf,0x66,0xd9,0xe5,0xff,0xe9,0x5c,0x0c,0xbb,0xd8,0xf4,0x65,0xde, + 0xcd,0x9e,0xa9,0xb0,0x9a,0x6d,0x5d,0x46,0xd5,0xf6,0xd8,0x6a,0x08,0x2d,0x0e,0xc6, + 0xdb,0x1f,0xe4,0xbb,0xa0,0x9a,0x36,0x56,0xe3,0xfd,0x3f,0x81,0x03,0x94,0xdf,0x44, + 0xd9,0x49,0x66,0x6c,0x7d,0x7b,0x05,0x47,0x20,0x64,0x96,0xc6,0x3d,0x15,0xb0,0xbf, + 0x30,0x10,0xc1,0x2b,0x38,0xaf,0x57,0xe0,0x9f,0x7d,0x56,0xfd,0x67,0x05,0x3a,0x74, + 0x9d,0xea,0x1f,0x6e,0x6f,0x6f,0xab,0x08,0x19,0x91,0x22,0x0f,0x9d,0xaa,0x20,0x2a, + 0x35,0xcb,0xd4,0x7f,0x16,0xf8,0xa7,0xaa,0xc4,0xff,0x60,0xb9,0x64,0xf4,0xdf,0x52, + 0xb5,0x71,0x60,0x05,0xfe,0x75,0x01,0x84,0x56,0x14,0x93,0x69,0xae,0xe2,0x88,0x88, + 0x2a,0x9d,0xf8,0xa9,0x9d,0xff,0xee,0x1f,0xf4,0x8a,0xfc,0xaf,0x16,0xff,0xaf,0x9a, + 0x4f,0x1a,0xe7,0x28,0x10,0xf6,0x21,0x55,0xf8,0x81,0x79,0x86,0xbf,0x55,0x7e,0xc7, + 0xf1,0x17,0xc5,0x72,0xb6,0x4b,0x1f,0xd2,0x7a,0x7b,0x99,0xb2,0xdd,0x59,0x55,0xab, + 0xef,0x65,0xdc,0x96,0xfe,0x0e,0xe6,0x99,0xf0,0x31,0x28,0xbe,0x5f,0xb2,0xd9,0xb4, + 0x14,0x99,0x3b,0xfe,0x45,0x68,0x47,0x15,0x6e,0x9f,0x1e,0x7d,0x2b,0xa8,0x3a,0x3b, + 0xa6,0xac,0x31,0x0a,0x40,0x6d,0x67,0xd4,0x88,0x96,0xf8,0xcf,0xf2,0xfd,0x19,0xff, + 0x8f,0x42,0x20,0xc7,0x77,0xab,0x57,0x0b,0xf4,0xe9,0xbb,0x16,0x40,0xab,0x5a,0xc2, + 0x6e,0x80,0xb6,0x96,0x02,0x43,0xad,0xa6,0x8c,0x30,0xd0,0x29,0xf4,0xd3,0x54,0xe8, + 0xe4,0xbf,0x4f,0xdc,0x4e,0xfd,0xd7,0x9a,0x10,0xe4,0xbc,0xdd,0xb6,0xdf,0xc0,0xf9, + 0x59,0x6f,0x01,0xd1,0x03,0xc1,0x0d,0x81,0xed,0xf0,0x08,0xed,0x67,0x93,0xb0,0x32, + 0xe3,0xff,0xb1,0xfa,0x7f,0x45,0x45,0x99,0xa3,0x53,0x2d,0x55,0x4b,0x42,0xf1,0xe2, + 0x8a,0xbb,0x5e,0x31,0x42,0xad,0xbe,0x8d,0xf2,0x35,0xfc,0x47,0x46,0x77,0xd4,0xff, + 0x93,0xb6,0x25,0x39,0xf6,0xf7,0x2b,0xf8,0x3f,0x14,0xe4,0xda,0x24,0xbf,0x43,0x6c, + 0xe7,0x94,0xbf,0x54,0xde,0xae,0x9e,0xd2,0x29,0x1e,0x2a,0x8f,0x70,0x42,0x80,0x88, + 0x7f,0x0e,0x8d,0xcb,0xff,0xaa,0x02,0xff,0xea,0x6b,0x74,0x3e,0x18,0xa9,0xd2,0x7c, + 0xb1,0x62,0x9d,0x0d,0x7f,0xa6,0xb6,0xd0,0xd7,0x49,0xf9,0x5f,0x8d,0xb8,0xf0,0x3a, + 0x2f,0xe2,0xff,0xfc,0x4d,0xcc,0x9b,0xa2,0xfa,0x87,0x6a,0x20,0x11,0x1c,0x2e,0x52, + 0x83,0xf7,0xab,0xb3,0x77,0xa8,0x29,0x36,0xcd,0x5c,0x99,0x98,0xc9,0xd5,0x3b,0x8b, + 0x5c,0xf9,0xef,0x2b,0x16,0x88,0x32,0x59,0x38,0x09,0x05,0x94,0x08,0x3f,0x16,0xa9, + 0x09,0x14,0x20,0x10,0x0a,0x1e,0x0c,0x56,0xb4,0xa3,0xc0,0x43,0xa6,0x3a,0x87,0x1d, + 0xd2,0x1d,0xfe,0x0f,0xe2,0x9f,0xa7,0xf9,0x34,0xf3,0xca,0x25,0x9e,0xab,0xe1,0x87, + 0x90,0x38,0x10,0x5b,0xb6,0x72,0x0e,0x0e,0xbb,0xc6,0xf4,0xa4,0x8a,0xae,0x28,0xc1, + 0xef,0x57,0x57,0xc7,0xf5,0xbf,0xd0,0xfe,0xcc,0x67,0x25,0xfc,0x47,0x59,0x3d,0xfb, + 0x4d,0xdb,0xac,0xb7,0x7c,0xcb,0xbd,0x97,0xc1,0xf3,0xfc,0x3a,0x2a,0xfb,0x7c,0x59, + 0x60,0x45,0xfb,0x3c,0x7d,0xc1,0xf2,0xe6,0xac,0xfc,0x77,0x4d,0xb4,0x35,0xe7,0xf2, + 0x88,0xe7,0x3d,0xa8,0x2f,0xf5,0x27,0x3f,0x35,0x00,0xdf,0xc9,0xad,0x6d,0xcc,0xd7, + 0xbd,0xc7,0xe0,0x5d,0xa8,0x83,0x6c,0xfe,0x4f,0xba,0xff,0x57,0xc1,0x58,0xf9,0xc7, + 0x70,0xb8,0x6d,0x56,0x34,0x34,0x56,0x7c,0x59,0xeb,0xf3,0x6d,0xb3,0x77,0x7e,0xaa, + 0x5f,0xaa,0x85,0x3f,0xf1,0x59,0xa9,0xb5,0xfd,0xf2,0x45,0xfe,0x1f,0x43,0x5d,0x22, + 0x1f,0x32,0xef,0xd7,0xcb,0x0c,0x75,0x31,0x4c,0x1a,0x7e,0x28,0x90,0x48,0x78,0xdf, + 0x62,0x45,0xc6,0xdb,0x30,0x4d,0xf1,0xdc,0xc9,0x1e,0x75,0xf0,0x52,0x1a,0xff,0x6c, + 0xf0,0xb4,0xe6,0xbe,0xce,0x3a,0x29,0xda,0xd5,0xca,0xea,0x94,0xef,0x43,0x59,0xec, + 0xc7,0xad,0x45,0x1a,0x3c,0x66,0x94,0x01,0x4e,0x6c,0xd4,0xd5,0xff,0x74,0xc0,0xea, + 0x6f,0xa5,0xb3,0x47,0x14,0x6e,0x28,0x7a,0x4c,0x61,0x39,0x2c,0x69,0xe8,0xaa,0x77, + 0x3b,0x63,0x13,0x77,0xc5,0x83,0xe0,0xa9,0x68,0x3f,0xea,0xaa,0x3f,0x2f,0xf0,0x4c, + 0xb4,0x00,0x37,0x35,0xb9,0x87,0x0e,0xcc,0x79,0xc9,0xd7,0xb3,0xe6,0x1a,0xf6,0x2f, + 0x46,0xc0,0xf4,0x3f,0x19,0x98,0xa1,0x53,0xc5,0x30,0x35,0x24,0x7f,0xd5,0x59,0x6f, + 0x1b,0x29,0xfe,0xc5,0xeb,0x35,0x84,0x85,0xa3,0x30,0xa6,0x3d,0xf1,0x92,0xbf,0xa4, + 0x63,0x00,0xde,0x35,0xea,0x07,0xd7,0x7d,0xdf,0x1b,0x8d,0xa3,0x3d,0x0a,0xfb,0xb7, + 0xb8,0xf2,0xaf,0xad,0xfe,0x5f,0xf5,0x7c,0xd2,0x60,0xf1,0x6c,0xfd,0x70,0x70,0x76, + 0xbf,0xef,0x3d,0xb9,0x4e,0x3f,0xbc,0xa3,0x61,0xd8,0x37,0xba,0xad,0x8a,0x2a,0x02, + 0x81,0x3f,0x25,0x67,0xfc,0x3f,0xbc,0x84,0xfc,0x39,0x33,0x7b,0xd4,0xd6,0xf6,0x24, + 0xdf,0x6e,0x6e,0xab,0x09,0x0e,0x78,0x2a,0x94,0x57,0xcc,0xd0,0xb2,0xe0,0x66,0xb9, + 0x1c,0x7a,0x78,0x75,0xb8,0x6b,0x87,0xbc,0x6c,0x3c,0xfe,0x89,0xaa,0x3b,0x28,0xfb, + 0x00,0xa6,0xf3,0x58,0x92,0x85,0x1a,0xd7,0xa8,0xa8,0x7f,0x62,0x07,0x42,0x5b,0x1e, + 0xe1,0x01,0xdd,0xbb,0xc3,0x55,0x4d,0x29,0x8d,0x7f,0x40,0xdd,0x5a,0xc4,0x83,0x1c, + 0x02,0x68,0xdf,0x99,0x22,0xc5,0xa1,0x72,0x01,0x0a,0xc0,0x93,0xbc,0x02,0xbc,0x7a, + 0x6e,0x93,0x33,0x3e,0x8d,0x7f,0xb8,0x1a,0xef,0x00,0xb3,0x1f,0xc7,0xaf,0x05,0x56, + 0x01,0xfd,0xac,0x72,0x50,0x24,0x02,0xbc,0x4b,0x9f,0x46,0xa2,0x19,0x1c,0x7d,0x98, + 0xc8,0xb7,0xfa,0x7f,0xad,0x4b,0xca,0xa9,0xf8,0x59,0x89,0x1a,0x4f,0x7d,0xe9,0x2c, + 0x2e,0x9a,0xfa,0x96,0x85,0x66,0x6e,0xa2,0xf5,0xbb,0x0a,0xe2,0x9f,0xa8,0x2b,0x1f, + 0xc1,0x9c,0xf8,0x06,0x1c,0x06,0x51,0x84,0x7c,0x52,0x29,0xe2,0x9f,0x7e,0xdf,0xa0, + 0x3c,0x67,0xf0,0x79,0xcb,0xa3,0x78,0x16,0x44,0xfd,0x84,0x1e,0x39,0xec,0xf0,0x67, + 0x38,0xe2,0x9f,0x35,0x5c,0x24,0x79,0x55,0x6a,0xfb,0x07,0xcb,0x4f,0x7a,0x36,0x17, + 0xe9,0x66,0x97,0xe5,0x11,0xba,0xa0,0xfe,0x5c,0x9d,0x6e,0x7a,0x7b,0x02,0x99,0xf8, + 0x17,0xf1,0x7f,0xa8,0x88,0xba,0x27,0xcc,0x22,0xb0,0x5b,0xd2,0xcd,0x98,0x12,0x78, + 0x88,0xa7,0xcb,0x40,0x0d,0x18,0xa8,0x81,0x09,0x3a,0x56,0x65,0xf9,0x7f,0xc8,0xc9, + 0xe6,0xe9,0x61,0x5f,0x55,0xf6,0xb3,0x40,0xaf,0xba,0xb6,0x69,0xbb,0xd1,0xa5,0x57, + 0xf6,0xca,0x84,0x27,0xb7,0xc1,0x74,0xea,0xbf,0x96,0xcd,0xff,0x39,0xc0,0xc3,0xc4, + 0xef,0xfd,0x3a,0x7c,0x24,0x85,0xcd,0x50,0x4f,0xf1,0x54,0x76,0xd0,0x76,0x0c,0x92, + 0x7f,0x0c,0xa1,0x32,0x38,0xfe,0x1f,0xc2,0x3f,0xe7,0xad,0x7e,0x2b,0x69,0x47,0x10, + 0xb5,0x29,0x3c,0xc7,0x33,0x44,0x68,0x72,0x74,0xb8,0xfd,0x3f,0xbf,0xd0,0x5f,0x28, + 0xad,0x7a,0xcb,0x97,0x14,0xdd,0x4e,0xbb,0xc9,0xfb,0x8a,0xf6,0x0b,0xaa,0xe9,0xfa, + 0x03,0x76,0x6b,0x8c,0x8c,0xff,0xa7,0x3f,0x27,0x1f,0xba,0xcc,0xc0,0xa0,0xda,0xcd, + 0x2a,0xf5,0x75,0x6a,0x79,0x6a,0x7e,0x02,0x72,0x85,0x61,0xf2,0x52,0x20,0x2c,0x4d, + 0x6d,0xca,0xe6,0xff,0x88,0x26,0x20,0x35,0xcc,0xa7,0xe3,0x44,0xa5,0xbc,0x1a,0x38, + 0x69,0x80,0x56,0xe2,0x40,0x1e,0xf1,0xbd,0xdd,0xfc,0x9f,0x55,0x94,0xff,0x75,0xb6, + 0xe9,0x8e,0xce,0x55,0x66,0xd9,0xc9,0x2b,0x3f,0xc3,0x2e,0x6b,0x5d,0xe7,0xf6,0x87, + 0xe4,0x2d,0x67,0xe7,0xb3,0xf8,0x3f,0xcf,0x40,0xd8,0xf4,0x85,0xbd,0x9e,0xf6,0x67, + 0xb4,0xf0,0x7b,0x7e,0xaf,0xbc,0xb6,0xe9,0x19,0x6a,0xfb,0x7e,0x3d,0xde,0xff,0xaf, + 0xb7,0xd6,0x0f,0xe7,0x5f,0xe7,0xce,0xff,0x9a,0xf8,0x24,0xfc,0x19,0xad,0x8f,0x3f, + 0x29,0xed,0x30,0x44,0xfd,0x1f,0x2e,0x9f,0x34,0xec,0x8e,0x21,0xfa,0x05,0xc4,0x3f, + 0x95,0xee,0xfc,0x2f,0xd1,0xff,0x82,0x57,0x51,0x5a,0x59,0x08,0xce,0xb0,0x7b,0x5f, + 0xc5,0x3f,0x14,0x12,0x6d,0xe9,0xf2,0x93,0xf2,0x71,0xea,0x0f,0x92,0xf2,0x25,0x9b, + 0x33,0xfc,0x04,0x8b,0xff,0x73,0xad,0xe3,0x3f,0xef,0x57,0xa3,0x6c,0x92,0xba,0x0a, + 0xc8,0xed,0x43,0x85,0x58,0xad,0x40,0xd8,0x09,0x67,0x3c,0xf1,0x7f,0x76,0x9b,0x53, + 0xd2,0xf1,0xbe,0x78,0x68,0x68,0xcd,0x12,0x76,0xbf,0xb2,0xca,0x4a,0x04,0x3b,0xcc, + 0x29,0xdf,0x5f,0xbd,0x98,0xff,0x53,0x61,0xce,0xd7,0x8a,0x26,0xc4,0x44,0xa0,0x79, + 0x56,0xd1,0xbf,0xe2,0x0a,0xac,0x30,0xd3,0x15,0x26,0x45,0x86,0x6f,0x86,0x9f,0x4c, + 0xfc,0x9f,0xf3,0xbc,0x9a,0x9c,0x3c,0xd7,0xd3,0x36,0x93,0xfc,0x9f,0x3d,0xc6,0xa1, + 0x44,0x3d,0xcf,0x4f,0x94,0x0f,0x6b,0xef,0x91,0x7d,0xbf,0xa8,0xfe,0xb3,0xd8,0x74, + 0x7b,0x09,0xf6,0xd4,0xc1,0x67,0x63,0x2c,0x9a,0x6b,0x33,0x84,0x59,0xe9,0xc5,0xf5, + 0x0f,0x5d,0xfb,0x7d,0x8a,0x8f,0x14,0x68,0x5f,0xaa,0x68,0xca,0xf0,0x43,0xe4,0x02, + 0x2a,0x04,0x74,0x49,0xff,0x4f,0x1f,0xbc,0x22,0xfa,0x9f,0x7a,0xa6,0x6a,0xab,0xc7, + 0xfb,0x7f,0x32,0xfd,0xdf,0x25,0xc2,0x3f,0x5f,0xcf,0xf8,0x8b,0x54,0x3b,0x70,0x23, + 0xbb,0xc6,0x8f,0xe3,0xff,0x88,0x6a,0xcf,0x45,0x43,0xf1,0xf5,0xa2,0xff,0xa9,0x27, + 0x97,0xb7,0xd9,0x81,0xb0,0xb4,0x6b,0xe8,0x2f,0xf0,0x7f,0xfa,0x45,0xdb,0x29,0xb9, + 0xac,0xc9,0xf6,0x3f,0xa8,0x63,0xb7,0xd4,0x95,0xac,0x1b,0xcf,0xff,0xb9,0xa0,0x59, + 0xf5,0x0c,0x45,0xff,0xf7,0x75,0xbf,0x2a,0x46,0xfc,0x93,0x7e,0xde,0x88,0x45,0x95, + 0x71,0xf3,0x7f,0x72,0x70,0x7e,0x82,0xc2,0xed,0x3f,0xc4,0x0f,0x22,0x0c,0xf0,0xbd, + 0xd4,0x51,0xa7,0x1f,0xb4,0x89,0xd0,0x07,0x2d,0xd7,0x8a,0xab,0x5f,0x06,0xf5,0x7f, + 0x37,0x84,0xb7,0xe7,0x98,0x16,0x83,0x99,0x25,0x6a,0x67,0x53,0x26,0x10,0x06,0x31, + 0xbd,0x52,0x2d,0xe0,0xec,0x70,0xa6,0xff,0xa9,0xb2,0x51,0x79,0x8c,0xe1,0xa6,0xbe, + 0x95,0xfd,0x3b,0xac,0x30,0x66,0xd0,0xfc,0xac,0xd5,0xdb,0x98,0x78,0xcc,0x67,0xa1, + 0x4d,0x15,0x19,0x61,0xae,0xfc,0x2f,0x65,0x3b,0xfc,0xab,0x36,0xd3,0xf0,0xbe,0xc4, + 0x4e,0x1a,0xf7,0xc1,0x4c,0x43,0xdd,0xec,0xb1,0x03,0x61,0xe9,0x19,0xf6,0x50,0x23, + 0x36,0x7b,0xbc,0x13,0xff,0xda,0xc4,0x86,0x02,0x07,0x25,0xea,0x7f,0x2a,0x57,0xb4, + 0x1f,0x74,0xbf,0xf1,0xac,0xfc,0x2f,0xd1,0xff,0x9d,0xd3,0x78,0xc2,0x3f,0xe9,0x61, + 0x65,0xb6,0xc0,0x2e,0xaa,0x7f,0xa8,0x6a,0x49,0x38,0x6b,0xcc,0x86,0x02,0x53,0x8e, + 0xc3,0x00,0xed,0x67,0x71,0xfe,0xb5,0x7e,0x97,0x07,0x92,0x88,0x58,0x4d,0xe3,0xf8, + 0x3f,0xd3,0xc9,0xc9,0x83,0xfb,0x53,0xdc,0x78,0x7a,0xa3,0xac,0x86,0xad,0x01,0xea, + 0x70,0x87,0x9f,0x89,0xc3,0x88,0x76,0xd6,0x43,0x8e,0x01,0xa4,0x4d,0x3d,0x80,0xdb, + 0x70,0x4e,0xdb,0x52,0xfd,0xc6,0x50,0x61,0x87,0xe2,0xcb,0x62,0xf0,0x66,0xf3,0x7f, + 0x76,0xf3,0x69,0x96,0xff,0xb6,0x83,0x97,0x99,0x57,0xea,0x05,0x25,0xb0,0x2a,0xe3, + 0xd1,0xcd,0x1f,0x20,0xfe,0x8f,0x93,0x9f,0x18,0x53,0x8b,0xe0,0x24,0x9f,0xa5,0x17, + 0x44,0xe4,0x03,0xac,0x93,0x5f,0x1b,0xf5,0x2f,0x91,0xeb,0xd5,0xe7,0x1d,0x46,0x74, + 0xec,0xaa,0xb7,0x50,0xb8,0x4b,0x1f,0xcf,0xff,0xc9,0x78,0x8f,0x13,0x08,0xa4,0x9d, + 0xc4,0x8a,0x33,0xba,0xc8,0x6f,0x72,0xf5,0xff,0x52,0xba,0xe1,0x2c,0x6f,0xd0,0xfd, + 0x07,0xe5,0x0d,0x70,0x34,0xde,0x10,0xf5,0xbf,0xeb,0xad,0xd7,0x8e,0xd8,0x89,0x3c, + 0x17,0x36,0xd5,0x0f,0xad,0xa3,0xfc,0x77,0x7b,0x3c,0xf5,0x7f,0x17,0xfe,0x9c,0xb1, + 0x76,0x1f,0xee,0xa7,0x42,0xe6,0x0b,0x41,0x56,0xd2,0x44,0xf7,0x5f,0x10,0x66,0x6f, + 0x98,0xbb,0x13,0xa1,0xd4,0xfc,0x6f,0x07,0xde,0xbb,0xd1,0x9e,0x4f,0x0d,0xe2,0xb0, + 0x87,0x9c,0x5a,0x07,0x58,0x9c,0xea,0x1d,0x19,0xde,0xbb,0x18,0xf5,0x0b,0x9b,0x62, + 0x3d,0xef,0x0f,0xf5,0x19,0xfd,0xde,0x7b,0xdc,0xfc,0x1f,0xea,0xff,0xce,0xd3,0x7c, + 0x06,0x61,0xe6,0x82,0xec,0x46,0x63,0x9b,0xc5,0x78,0x19,0x49,0xcf,0x67,0x53,0xc6, + 0xff,0xbc,0x63,0x22,0xea,0x93,0x98,0x78,0x89,0x09,0xcb,0xad,0xf7,0x8b,0xe2,0xa5, + 0xec,0x8f,0x69,0x22,0x81,0xfa,0xa6,0x68,0x55,0xe9,0xe2,0xff,0xc4,0x9d,0xfc,0x77, + 0x38,0xae,0xfd,0x11,0x0a,0xf0,0xb5,0x36,0x6f,0xd7,0xff,0x1f,0x10,0xf5,0x9f,0xa9, + 0x51,0x88,0xe8,0x88,0x9a,0x72,0xd6,0x4f,0x52,0x13,0xf5,0x90,0x01,0x37,0xf5,0xa3, + 0x13,0xcf,0xa2,0xf5,0x5f,0x17,0xed,0xf8,0x17,0xe6,0x24,0xfe,0xbc,0x29,0x04,0x29, + 0x8b,0xff,0xa3,0xd8,0xfe,0x1f,0x12,0x36,0x78,0x13,0x72,0x94,0x91,0x63,0x67,0x42, + 0x32,0x53,0xcf,0xd0,0xed,0xff,0xd1,0xdd,0xde,0x57,0xd1,0x86,0xa6,0x82,0xd3,0x30, + 0xd9,0xc5,0xa0,0x4e,0x64,0xfc,0xcf,0x25,0x99,0xfc,0xf7,0xc8,0xee,0xf2,0x10,0xf7, + 0xea,0xed,0x37,0xb2,0x0e,0x2b,0x02,0x3b,0xc2,0xb7,0xe9,0xa1,0x03,0xde,0xaa,0x5c, + 0xb7,0xff,0xc7,0xaa,0xbf,0x41,0xfe,0x67,0xe8,0x99,0x86,0xc0,0x6f,0x9b,0xbc,0xd6, + 0xe2,0x97,0xee,0x21,0x7b,0x54,0xd3,0x30,0xe0,0xdf,0xdd,0x91,0xc8,0xe4,0x7f,0x4d, + 0x4c,0xf7,0xbf,0xd8,0x63,0x59,0xf3,0x35,0x7e,0xbd,0x78,0x8f,0x95,0xb6,0x73,0x82, + 0x18,0x65,0x7a,0x43,0xbf,0xbf,0x5b,0x1e,0x76,0xf0,0x8c,0xa8,0x7f,0x88,0x20,0xd0, + 0x67,0xca,0x97,0x91,0xff,0xc7,0xf0,0x3d,0x23,0xd7,0xc0,0xeb,0x7c,0x6e,0x0a,0x67, + 0x6c,0x32,0xa5,0xc6,0x53,0x20,0x2c,0x9c,0xc1,0x93,0x71,0xd1,0xff,0x4b,0x0f,0x72, + 0x16,0xd2,0x9e,0x86,0x40,0x34,0x92,0x9b,0x1b,0x34,0xd0,0xbe,0x1f,0xb8,0x32,0x56, + 0x34,0x1d,0xf6,0x21,0xde,0x23,0x28,0x98,0xe1,0x03,0xe4,0xac,0x25,0x76,0x37,0x6d, + 0xba,0x7d,0xa2,0xbf,0x8c,0x8a,0x9b,0xb9,0x64,0x3c,0x88,0xf6,0x08,0x81,0x1f,0xa5, + 0xc2,0x51,0x7d,0xf5,0x80,0x64,0xcf,0xbf,0xc8,0xff,0x8a,0x6d,0x6d,0x57,0x77,0x1c, + 0x08,0xf1,0x1f,0xc3,0x56,0x43,0xdd,0xc5,0x42,0xfa,0x9a,0xf6,0x80,0x99,0x17,0x2f, + 0x9a,0x49,0x7f,0x3a,0x9a,0x97,0x70,0xed,0xf7,0xa5,0x89,0x23,0xda,0x05,0x3e,0x7b, + 0x8f,0xaf,0x9f,0xec,0xaf,0x54,0xb5,0x38,0xd4,0xd7,0x3e,0x4d,0x3b,0xca,0xab,0x7b, + 0xe7,0xc3,0x35,0x33,0xb5,0x0f,0x79,0x38,0xe5,0xd3,0x64,0x70,0xfa,0xbf,0x8f,0x4a, + 0x54,0xff,0x07,0x97,0x19,0x85,0xbd,0x2e,0xc0,0xbc,0x5e,0xff,0x60,0xf1,0x08,0xed, + 0x58,0x4d,0xff,0x10,0x05,0x46,0xf5,0x06,0xee,0xbb,0xa8,0xff,0x7b,0xaa,0x6a,0xd0, + 0xd7,0x6e,0xf1,0x5b,0x0c,0xff,0x56,0x79,0x9a,0x46,0xf8,0x27,0x64,0xca,0xef,0xc7, + 0x5f,0xa0,0xd4,0x3c,0x77,0xfd,0x43,0xf2,0xff,0xec,0x36,0x75,0xae,0x6e,0x65,0x21, + 0xb4,0xe6,0x95,0xe6,0xfc,0xa7,0x3c,0x33,0xf4,0xd7,0xa8,0x7e,0x51,0x77,0xd3,0x71, + 0xfe,0x1a,0xf5,0x43,0xd9,0x33,0xae,0xfe,0x21,0xee,0xbf,0x20,0xd8,0x89,0xf3,0xf3, + 0x73,0xb6,0x24,0xea,0x5d,0xcb,0xa6,0x6b,0xb1,0x7e,0x34,0xd3,0xaa,0xc5,0x3f,0x5c, + 0x8a,0x1b,0x55,0x7b,0x36,0xed,0xfc,0xaf,0xb2,0xe9,0xb1,0xaf,0xb2,0x06,0xbe,0x8a, + 0xcf,0xf8,0x8a,0xf7,0x1f,0x8b,0xae,0x84,0x9f,0xf0,0x3b,0x87,0xd4,0xef,0x36,0x9d, + 0x87,0x1f,0xb6,0x97,0x27,0xd4,0x61,0xa6,0x66,0xf5,0x7f,0x3f,0x03,0x61,0x43,0x5d, + 0x23,0xe7,0xf2,0xdf,0xeb,0x75,0x2d,0x5e,0x4d,0x56,0xc0,0xd4,0xba,0x87,0x43,0x8a, + 0x7c,0xd8,0xec,0x15,0xd0,0x48,0xbe,0x62,0x5c,0xfd,0x9f,0x9f,0xf5,0xfb,0x8f,0xc9, + 0x67,0x8d,0x0f,0xd4,0x86,0x96,0x85,0xa3,0x82,0x36,0x4f,0x65,0x7f,0x28,0xff,0x8b, + 0xf8,0x3f,0x77,0xba,0xf0,0x5e,0x50,0xd9,0xa9,0x9c,0x51,0xaa,0x24,0x1f,0xc8,0x21, + 0xf6,0x82,0x4e,0x68,0xd0,0x5b,0x27,0x2a,0xb4,0xfb,0x56,0x5a,0x6f,0x84,0x77,0x6e, + 0xc2,0x57,0x6e,0x8f,0xb7,0xf2,0xbf,0x74,0x20,0xd8,0x03,0x0f,0x4f,0x9b,0x61,0x7a, + 0x96,0xc9,0x93,0xc8,0x23,0x84,0x40,0x85,0x89,0xd4,0x78,0xb3,0x60,0x19,0xbb,0xc2, + 0xd9,0x31,0x34,0xc2,0x4f,0x95,0xd9,0x04,0x72,0x06,0xd8,0x4f,0xf5,0x55,0xa8,0x9d, + 0x4a,0x6b,0xd8,0x1d,0x73,0x1e,0xeb,0xfc,0x5a,0x6a,0x5a,0x84,0x4d,0xd6,0xf7,0xc6, + 0xca,0xdf,0x52,0xcf,0x32,0x75,0x5c,0xfe,0x17,0xce,0x5e,0x45,0xfb,0x43,0x50,0x4e, + 0x6a,0x67,0x8e,0x27,0x5f,0xdf,0x45,0xf9,0x98,0x35,0x6c,0x9d,0xbe,0x9b,0xeb,0xef, + 0xa2,0x22,0x2a,0xca,0x8a,0x7f,0x7d,0xbc,0x6c,0x16,0x0f,0x8d,0x78,0x77,0x50,0x58, + 0x33,0x16,0xfa,0xbd,0xbc,0x1c,0xce,0xb7,0xd6,0xf3,0xcf,0x3e,0x2a,0x5f,0x07,0x27, + 0xa0,0x3c,0xee,0x1b,0xf1,0xd6,0x8e,0x8b,0x7f,0x3d,0x05,0xfe,0x4e,0x34,0xc9,0xc4, + 0x7f,0x26,0x47,0x90,0xc8,0xd0,0x29,0x00,0x39,0xa5,0x2d,0x87,0xa7,0xb4,0x82,0x95, + 0xcd,0x59,0xf9,0x5f,0x54,0xe4,0x30,0xea,0x2b,0xf5,0x4e,0x8d,0xfc,0x4a,0x0a,0x2f, + 0xf1,0x95,0x10,0x11,0x08,0x11,0x02,0xc2,0x66,0x04,0xd2,0xac,0x6a,0x89,0xef,0x5f, + 0xc6,0xe7,0x7f,0x99,0x81,0x6f,0x06,0x37,0xb2,0xa9,0xb0,0x5a,0x0a,0x10,0xed,0x67, + 0x0a,0xec,0xeb,0xa5,0x46,0xe4,0xf2,0x8d,0xca,0x6a,0x75,0xce,0x12,0x75,0xc3,0xf8, + 0xfc,0xaf,0xd2,0x40,0xb3,0xba,0x9e,0xd9,0xfd,0x2f,0xda,0xa7,0x14,0x52,0xe2,0x52, + 0xe9,0x26,0x36,0xc5,0x58,0x5d,0x26,0xfa,0x35,0x64,0xc7,0xbf,0xf6,0x59,0x6e,0x9f, + 0x5c,0x68,0xd3,0xf5,0xcf,0x2c,0xa1,0x44,0xf8,0xdd,0x4a,0xc8,0x08,0x16,0x35,0x2d, + 0x86,0x36,0x36,0x95,0xfc,0x3f,0x19,0xfc,0x23,0xf8,0x3f,0xad,0xf8,0x7e,0x1f,0x94, + 0xcb,0x8c,0xa3,0xad,0x5b,0xc1,0xb7,0xc2,0x53,0x66,0x8c,0xb5,0xd6,0x97,0x90,0xea, + 0x42,0x8b,0x7a,0x8f,0x95,0xff,0x6e,0x7f,0x5f,0x94,0xff,0x75,0x4e,0xfb,0x59,0xcb, + 0xc2,0x5f,0xc1,0xcb,0xca,0x29,0xad,0xa1,0xc5,0xff,0xab,0xc2,0x93,0xc6,0x2f,0x05, + 0xff,0x99,0x9d,0x54,0xfe,0xa4,0xfc,0x33,0xf1,0x79,0xb2,0xfb,0xbf,0xff,0x8e,0xbc, + 0xf1,0x2f,0xc9,0xdf,0x84,0x77,0xc3,0x38,0x2d,0xb8,0xff,0x32,0xfe,0x44,0x89,0xc0, + 0x1b,0xe4,0x39,0xf0,0x22,0xcc,0xa2,0x23,0x87,0xb3,0xfa,0x9f,0xd6,0xa8,0x77,0x29, + 0xde,0xf6,0x76,0x3d,0x16,0x0b,0xd7,0xe2,0x66,0xac,0x5d,0x37,0x7a,0x82,0x95,0x6a, + 0xb0,0x0d,0x77,0xa0,0x3b,0x18,0xf5,0xbf,0x18,0xd7,0xff,0x7d,0xbd,0xa6,0x1b,0xf3, + 0x8b,0x99,0xa2,0xb7,0x95,0x85,0x0c,0xb5,0xd0,0xe3,0x23,0x04,0x38,0x5f,0xa5,0xc2, + 0x47,0x54,0xf8,0x51,0xd5,0x5c,0xfd,0x70,0x37,0x4d,0xdc,0x9e,0xb3,0x0f,0xb6,0x46, + 0xbc,0x1b,0x72,0x17,0x37,0xad,0x86,0xe9,0xc6,0x1a,0xc4,0x93,0x51,0x82,0x91,0x91, + 0x78,0x60,0x31,0xfc,0x9c,0x07,0x50,0x60,0xef,0x38,0xf1,0xb2,0xc4,0xf7,0x87,0xe0, + 0x95,0x29,0x81,0xcf,0xf9,0xff,0xc5,0x5b,0xa1,0x11,0xda,0xf1,0xfd,0xcc,0x7b,0x0d, + 0x9c,0x8a,0xd5,0x1b,0x0b,0xe2,0x5d,0x5f,0xe1,0xbd,0xd0,0x7d,0x9b,0x6f,0xd3,0xb8, + 0xfc,0xaf,0x34,0xdb,0x67,0x3b,0xbc,0x02,0x35,0x44,0x2c,0x1c,0x52,0x44,0x61,0xcc, + 0xa4,0xbc,0x3d,0x7a,0x4a,0xaa,0x8f,0xce,0xdc,0x50,0x9c,0xdd,0xff,0x7d,0x38,0x52, + 0x55,0x14,0xe2,0xe5,0x16,0x10,0x2d,0xc0,0xfd,0xb1,0x3e,0xd6,0x44,0x5f,0xdc,0x03, + 0x5b,0x60,0x79,0x81,0x88,0x48,0x66,0xf7,0x7f,0x7f,0x8a,0x6f,0x4b,0xa8,0xc7,0x3d, + 0x35,0x84,0x76,0xda,0xbd,0xef,0xb2,0xeb,0xe0,0xb8,0x12,0xa0,0xb2,0x87,0xa5,0xfa, + 0x53,0x91,0x19,0x3c,0x7f,0x88,0xb9,0xfa,0xbf,0xe3,0xfe,0xab,0xdc,0x48,0x0c,0xaa, + 0x4f,0x6e,0xd8,0x61,0xf3,0x0f,0xf3,0x51,0xc0,0x65,0x03,0xec,0x7e,0x54,0x65,0xa1, + 0x95,0x79,0xd5,0xee,0xfe,0xef,0xc4,0xff,0x51,0xcb,0x46,0x83,0xe1,0xdc,0xcd,0x22, + 0x7f,0x41,0xfe,0x26,0x7e,0xc8,0xff,0xc6,0xcb,0xfa,0x55,0x63,0x65,0x89,0x68,0x0d, + 0x9f,0xb7,0x84,0x65,0xf6,0xe3,0x54,0xff,0xf9,0x7d,0x54,0xc2,0xea,0x72,0xf9,0x07, + 0xf0,0xe7,0xc4,0xbc,0xb7,0x0a,0xc6,0xe4,0x2b,0xb4,0x3d,0x7c,0x77,0x2a,0x14,0x6c, + 0xff,0xa9,0xa0,0x46,0xe7,0x2f,0x97,0x59,0x06,0xff,0x38,0xfd,0xdf,0xa1,0x82,0x1c, + 0x17,0x84,0x76,0x44,0x62,0x66,0x9f,0xff,0x21,0xd9,0x02,0x42,0xd9,0xfd,0xdf,0x73, + 0xce,0xa3,0xfe,0xbf,0x1e,0x8d,0x54,0xf3,0x74,0x2a,0x7b,0x98,0x0a,0x8d,0x79,0xab, + 0xe1,0x42,0xe7,0xbd,0xc7,0xd0,0x22,0x3c,0x45,0x1b,0x5b,0x91,0xff,0xe5,0xf8,0xd3, + 0x1e,0xb1,0xea,0x6f,0x18,0x6a,0x95,0xe7,0x7e,0xd1,0xbd,0x5d,0x6d,0x25,0xda,0x61, + 0x70,0x6a,0x4a,0xbd,0x55,0xe6,0xd1,0xc7,0xb4,0x19,0xb7,0x07,0x97,0xb1,0xb7,0x9a, + 0xec,0xf1,0xd4,0xff,0xf4,0x31,0x75,0x5a,0xab,0xba,0xec,0x89,0x8d,0xb1,0x09,0x14, + 0xff,0x8a,0xb2,0xdb,0xa2,0x7b,0x8c,0xaf,0x99,0x6a,0x4b,0xae,0x55,0x01,0xbb,0x74, + 0x5c,0xfd,0x67,0x75,0x97,0xaa,0x47,0xd5,0x7f,0x61,0x8a,0xe8,0xf6,0xa5,0xae,0xc0, + 0x8d,0x7f,0x37,0x9b,0x6a,0xaa,0x5a,0xae,0xa9,0xe3,0xfe,0xa2,0x55,0x75,0xd7,0xff, + 0x19,0x46,0x7b,0x77,0xca,0xac,0x1d,0x0b,0x3d,0x29,0x3f,0x84,0xf6,0xa2,0x3e,0xe5, + 0x7b,0x4c,0xfa,0x9a,0xb1,0x1b,0xed,0x11,0x6e,0x34,0xde,0x21,0x57,0x4f,0x4a,0xbd, + 0xaa,0xc3,0x15,0xff,0x92,0x76,0xc2,0x29,0xe3,0x49,0xb2,0xef,0x43,0xc6,0x47,0x4a, + 0xbd,0xb9,0x2e,0x21,0x3f,0x08,0x63,0x4d,0xd5,0x66,0xbe,0x4a,0x0c,0x90,0xbe,0xfa, + 0x61,0x81,0xb7,0x9d,0xf9,0xd1,0x9e,0x14,0x65,0xa2,0x51,0xdb,0xcc,0x31,0xfe,0x3b, + 0xcc,0xea,0xf7,0xbd,0x2a,0xd7,0xf2,0x11,0x69,0xb6,0xe9,0x4b,0x79,0xc3,0xc2,0xd5, + 0xef,0x3b,0x29,0xab,0x4e,0xfc,0x6b,0x05,0x2c,0x85,0x5f,0xa6,0x2a,0xa3,0xea,0xeb, + 0x72,0x0b,0xc2,0x1e,0xb4,0xef,0x7d,0x4d,0x01,0x1e,0x4b,0x05,0xcc,0xcf,0x3e,0x22, + 0x7f,0x89,0xef,0xeb,0x0d,0x2d,0xf3,0x25,0xdb,0x83,0x59,0xfe,0x9f,0x7d,0x9c,0xd8, + 0x3e,0x1b,0xa6,0x88,0x6a,0x3f,0x68,0xdd,0x80,0x3e,0x13,0x33,0xc2,0x73,0xa7,0xc2, + 0xbe,0xb6,0xca,0x94,0xa8,0xd7,0xea,0x8a,0x7f,0x49,0x38,0x09,0x51,0xfa,0xfa,0x38, + 0x6e,0xfc,0x7b,0x83,0x70,0x33,0x48,0x31,0xd0,0x07,0xf3,0x34,0x0f,0x42,0x71,0xdc, + 0x98,0x4c,0xd3,0x3c,0xcc,0xb1,0x5f,0xed,0xf9,0x4b,0xe9,0xfe,0x25,0xdf,0x7a,0xb9, + 0xc2,0xa0,0xeb,0xa3,0xa1,0xc1,0xcf,0x5c,0xa9,0x3a,0x8a,0x6a,0xa7,0x4c,0x24,0x92, + 0xe0,0xa3,0x81,0x93,0x7f,0xba,0xf5,0xaa,0xb3,0xf0,0x5d,0x8a,0xef,0xbc,0x24,0x6f, + 0x34,0xdf,0x24,0xfb,0x6e,0xb2,0x51,0x15,0x11,0xe0,0x51,0x6a,0x74,0x25,0xfc,0xcf, + 0xc4,0x7f,0x76,0xd5,0x7f,0x26,0x98,0x34,0x9b,0xba,0x55,0x96,0xc2,0x11,0xaa,0xff, + 0x13,0xf3,0x2e,0x17,0x65,0x7f,0x10,0x3f,0x7f,0x1d,0x44,0xff,0xf7,0x1e,0x04,0x6b, + 0x99,0xf8,0xd7,0x08,0x3c,0xa1,0x50,0x35,0x42,0x4f,0x90,0xd0,0x60,0xca,0x1b,0xbb, + 0x75,0x7a,0x6b,0x17,0x9f,0x9e,0xf2,0xf6,0x34,0xf9,0xf4,0x75,0x94,0x08,0xd6,0xd3, + 0x14,0x76,0xf1,0x7f,0xfa,0xc8,0xed,0x63,0x94,0x86,0xd1,0x48,0x09,0x98,0x97,0x10, + 0x8e,0x7a,0xab,0x11,0x2a,0xef,0xb0,0x12,0x0d,0xee,0xc9,0xf8,0x7f,0x0a,0x77,0x8a, + 0x6c,0x32,0xb5,0x27,0x77,0x3a,0xce,0xff,0xd7,0x4d,0x6f,0x0c,0x55,0x5a,0x97,0x99, + 0x6e,0x84,0x9a,0xee,0x88,0xba,0x3c,0x53,0x0f,0x8a,0xf8,0x3f,0x3c,0xb9,0x04,0xd7, + 0xcf,0x74,0xf5,0x85,0x38,0xae,0x87,0x90,0x3c,0x1d,0x5e,0x31,0xab,0xac,0xfc,0x2c, + 0xab,0x62,0xb3,0x6c,0x38,0xf1,0xac,0x14,0xae,0x9f,0xf3,0x16,0xe8,0x4d,0xe7,0x03, + 0xa6,0xe4,0x4d,0x38,0x5f,0x4f,0xe3,0x11,0x2f,0x41,0xc7,0xbd,0x24,0xf4,0x44,0xed, + 0xf1,0x2d,0xb8,0x7f,0x7f,0x81,0xba,0x39,0xf7,0xc8,0x41,0x0b,0x76,0x26,0xe4,0xa5, + 0x2c,0xed,0xff,0x39,0x2e,0x8e,0x50,0xfd,0x1f,0x37,0xff,0x27,0xb7,0x43,0xdf,0x6a, + 0x06,0x6b,0xf0,0x6e,0x5f,0xb3,0x89,0x64,0x1d,0xbc,0x9a,0x1e,0x73,0x44,0x5d,0x85, + 0x47,0xae,0x0a,0x37,0x65,0xf8,0x3c,0x84,0x7f,0x3a,0x78,0xf4,0x68,0x9e,0xc6,0x96, + 0x58,0xd5,0xd1,0x81,0x45,0xd4,0x0e,0xbe,0x5d,0x8c,0x17,0x33,0x46,0xf5,0x7f,0x1c, + 0x7e,0x7b,0x52,0x9a,0xcc,0x57,0xc6,0xcb,0x86,0xf2,0x4e,0x79,0xbe,0x0d,0x3f,0x4c, + 0xcc,0x48,0x5d,0x19,0xd9,0x7a,0x05,0xac,0xe3,0x53,0x52,0x57,0x2e,0x67,0x6f,0xe4, + 0xad,0x4a,0xcc,0x24,0xff,0xcf,0x59,0xfb,0xf2,0x88,0x7f,0x14,0xba,0x7f,0xf3,0xb3, + 0x05,0x9e,0x08,0x3c,0xa3,0x13,0x11,0x5a,0xc6,0xbf,0xa8,0x8a,0xb6,0x17,0xc4,0x08, + 0xaa,0x4f,0x45,0xae,0x97,0x5f,0x75,0xc6,0x23,0xfe,0xe1,0x02,0x2d,0x2f,0xf3,0xf6, + 0xd0,0x46,0xde,0x9c,0xa0,0xcb,0x47,0x2d,0x47,0x50,0x92,0x3a,0xea,0x32,0xab,0xff, + 0x85,0x8b,0xff,0x43,0x65,0x10,0xba,0x53,0xbe,0xb8,0x1c,0xbc,0x51,0xcc,0x4f,0x10, + 0x27,0xea,0x19,0xab,0x2c,0x15,0x9e,0xda,0x52,0x45,0xd4,0xbe,0x43,0x0e,0x9f,0x87, + 0xf8,0x3f,0xed,0x96,0x93,0x67,0xb2,0xb5,0x6d,0x8c,0xa2,0xfe,0x59,0x05,0x5b,0xac, + 0xfd,0xd4,0x36,0xab,0x22,0x62,0x86,0x0f,0xc6,0xe1,0x71,0x0a,0x7b,0xa5,0xd4,0xa3, + 0xec,0x8a,0x04,0xe2,0xbd,0x63,0xde,0xe1,0x40,0x81,0xdd,0xf6,0xe2,0x0d,0xf8,0x61, + 0xb2,0x2c,0x35,0x7f,0x79,0x91,0xe9,0xc2,0x3f,0x08,0x1a,0x35,0x7d,0x13,0x82,0xc6, + 0x09,0xfa,0x6a,0xb1,0x11,0x6b,0xcf,0xe7,0xa2,0x8c,0x9b,0xd5,0x58,0x36,0x7a,0x31, + 0xff,0xe7,0x30,0x9f,0x1d,0xf7,0x0d,0x21,0xda,0x21,0xb7,0x8f,0xff,0x1d,0xf9,0xfa, + 0xc0,0x73,0x46,0x95,0x45,0x84,0x7e,0xd5,0xea,0x7f,0xf1,0x91,0xab,0x9f,0x66,0x8a, + 0x11,0xfe,0x99,0xc9,0xbd,0x66,0x7a,0xf7,0x3d,0xff,0x98,0xe2,0xe4,0x23,0x0f,0x5f, + 0xa2,0xfe,0xa1,0x66,0x65,0x7b,0xa5,0xbb,0x21,0xf8,0x7f,0x24,0x88,0x40,0xd5,0xd4, + 0xdf,0x6a,0xb1,0x94,0x26,0x02,0x3d,0x93,0x79,0xde,0x8c,0xff,0xe7,0x5a,0xab,0x7a, + 0xe1,0x26,0xf6,0x07,0x96,0x67,0x95,0xdd,0x73,0x18,0xce,0xa9,0x9c,0x8b,0xf9,0xcf, + 0x6c,0x71,0x70,0xb5,0x16,0xa0,0xe8,0xfc,0x50,0x67,0x1e,0x4c,0x6d,0xa4,0x23,0x54, + 0x38,0xa8,0xd1,0x3b,0x2e,0xff,0xdd,0x6a,0xf2,0x5e,0x14,0x68,0x49,0x97,0x7d,0x66, + 0x7d,0xb1,0xd5,0x7a,0x82,0xae,0x60,0xbb,0x86,0x72,0x33,0xfc,0x90,0x9e,0xfc,0x3b, + 0x8d,0xb1,0x5b,0x45,0xd9,0xe7,0x46,0xea,0x76,0x4a,0x4f,0x37,0x0c,0xfd,0x4c,0xd0, + 0x9c,0x1a,0x8d,0x1e,0xeb,0x79,0x3f,0x76,0xec,0x5d,0xff,0x55,0x2f,0x1b,0xe7,0xb4, + 0x79,0x86,0xff,0x16,0xef,0x9e,0xa6,0x73,0xe9,0x32,0xce,0x78,0xe4,0xa7,0x96,0x3f, + 0xe7,0x54,0xc9,0xb8,0xfa,0x87,0xa5,0x13,0x4f,0xea,0xef,0xab,0xa8,0x84,0x07,0x3b, + 0x08,0xed,0xcc,0x16,0x8e,0x23,0xfe,0x22,0x25,0x46,0xa1,0xd0,0xf4,0x3b,0x8b,0x1a, + 0x94,0xe9,0xff,0xbe,0xbc,0x34,0x05,0x6b,0x0c,0xea,0x66,0x8e,0x9b,0xca,0x98,0x88, + 0x76,0xb1,0x14,0xa3,0x32,0x38,0x22,0x22,0xd6,0xdf,0x5a,0x39,0x9e,0xff,0x63,0xf1, + 0x31,0xd4,0xee,0x76,0x45,0xfd,0xb1,0xd5,0xff,0xe2,0x79,0x58,0x6f,0x54,0xd0,0x83, + 0x0f,0x41,0xda,0xf1,0x95,0x59,0x0f,0xa5,0x39,0xdb,0x95,0xd5,0x94,0x76,0x17,0xf7, + 0xac,0x64,0x3f,0xd2,0x71,0x3e,0x37,0x92,0xdb,0xc7,0x4a,0xbb,0x1b,0x92,0x7e,0x64, + 0x4d,0xb5,0xab,0xfe,0x61,0xc9,0x49,0xe3,0x7d,0x68,0x68,0x0d,0xc5,0xa5,0x6a,0xe5, + 0xdf,0xa9,0x7e,0xf5,0xf7,0xe5,0xb7,0xe1,0x15,0xa3,0xda,0x66,0x7c,0xd5,0x8f,0xab, + 0x7f,0x08,0x9d,0x60,0x95,0x01,0x17,0xf5,0x0f,0xeb,0x8d,0x09,0x9b,0xe4,0xe7,0xdd, + 0x15,0x11,0xf1,0x48,0x36,0xff,0x27,0x41,0x45,0xcc,0xb4,0x50,0x67,0xb9,0x15,0x76, + 0x24,0xbc,0xad,0xa7,0xdb,0x5e,0xe8,0x56,0x68,0x6c,0x3c,0xff,0x67,0x0d,0x94,0x73, + 0x55,0x67,0xb5,0x44,0x3b,0xe4,0xde,0x54,0xee,0x69,0x68,0xd7,0x45,0xdb,0x8b,0x20, + 0x88,0x42,0xd0,0x89,0x80,0xab,0xfe,0x61,0x0e,0xf1,0x9f,0xd3,0x65,0x0f,0xa9,0x5f, + 0xf0,0xfc,0x6a,0xf6,0xa2,0x91,0xf6,0x97,0xfa,0xd2,0xa1,0x31,0x17,0x5f,0x48,0x97, + 0x26,0xc5,0x57,0x24,0xb6,0xc4,0xd4,0xd1,0xdc,0xdf,0x99,0xab,0xc2,0xc2,0xed,0x33, + 0x80,0xdf,0x6f,0x19,0xd5,0x7f,0x2e,0xc1,0xfd,0xc5,0x45,0xf5,0x0f,0xeb,0xe3,0x6f, + 0x26,0x66,0x8f,0x2d,0x58,0xee,0x3d,0x04,0xcf,0x0a,0xb7,0x0f,0x7b,0x95,0x3d,0x4f, + 0xf5,0x7f,0x96,0x8b,0x42,0x40,0xb3,0xc6,0xd5,0x3f,0xbc,0xea,0x17,0xc6,0x75,0xf1, + 0xfa,0x84,0x3f,0xec,0x9d,0xce,0x4e,0x71,0x2b,0x9b,0x1b,0x3e,0xb2,0x60,0xcf,0x90, + 0x7e,0x46,0xa1,0x46,0x8a,0xe5,0x87,0x5c,0xfc,0x9f,0x8f,0x8d,0xdf,0xb5,0xa1,0xfd, + 0x3a,0x2a,0x57,0xc3,0xb9,0xf6,0x59,0x29,0xdf,0xb0,0x7c,0x5e,0x7d,0x51,0x94,0x7d, + 0x96,0xcf,0xc3,0x91,0xf8,0xf5,0xa2,0xff,0xbb,0x33,0xfe,0xd1,0xc2,0x3d,0x83,0xcf, + 0x42,0x19,0xa8,0xa3,0x4d,0x97,0xc5,0xde,0x85,0xb2,0x61,0x75,0x04,0xf1,0xdb,0x2a, + 0xab,0x23,0xc6,0xeb,0xb0,0x2e,0xa1,0x8f,0x74,0x2d,0x67,0x5f,0x75,0xde,0x17,0xc0, + 0x46,0xf5,0x3e,0xc4,0x4b,0x79,0xad,0x4c,0xe3,0x8f,0xa9,0x53,0x06,0x54,0xb3,0x69, + 0x33,0xac,0x50,0xc5,0x63,0xbe,0x81,0x88,0x45,0x10,0x81,0x46,0x5c,0xfc,0x9f,0x3e, + 0xb5,0x8d,0xeb,0x5a,0x5e,0x98,0x95,0xf1,0x2d,0x38,0x8d,0x6a,0x05,0xf8,0xd4,0x8e, + 0x88,0xf0,0x78,0x8c,0xb0,0xb4,0x63,0xbf,0xd5,0x99,0xff,0x1d,0x13,0x3b,0x51,0x7f, + 0x86,0x21,0x3f,0x29,0x07,0xe0,0x23,0x4a,0x1b,0xd9,0x5e,0xde,0x09,0xcf,0x98,0x55, + 0xbd,0x56,0xfc,0xc2,0x72,0x85,0xbd,0xe5,0xea,0x8f,0xfc,0x10,0xed,0x9e,0x94,0x82, + 0xdd,0xf2,0xef,0xe1,0x8f,0xf0,0x6d,0xd3,0xbf,0xe3,0x99,0xed,0xba,0x55,0xf8,0xa5, + 0x78,0x28,0xdd,0xff,0xbd,0x29,0xd3,0x8f,0x5e,0xd2,0x3e,0x86,0x23,0x6a,0x43,0x55, + 0xfe,0x32,0xb9,0x4a,0xc2,0xef,0xab,0x77,0x61,0xaa,0x7c,0x0e,0x99,0xf5,0x5e,0x77, + 0x05,0x98,0x21,0x17,0xff,0x87,0xfa,0x09,0x56,0x02,0x35,0x65,0x10,0x61,0x8b,0xd5, + 0x21,0xf9,0x0f,0x02,0xd8,0xac,0xa3,0xc4,0xf6,0xd7,0xf0,0x0f,0x89,0xfe,0xef,0xf6, + 0xfd,0xf3,0x9c,0xc5,0x86,0x18,0x1f,0xc7,0xe7,0x15,0x61,0x8e,0x1d,0x6c,0x6a,0xc5, + 0x6a,0x78,0xc7,0x66,0x10,0x4d,0x37,0xe7,0x27,0x03,0x29,0x67,0x36,0xa9,0xfe,0x18, + 0x7e,0x74,0xba,0x3a,0x8b,0x41,0xa2,0x0d,0x52,0xfd,0x79,0x3a,0xaa,0xb5,0x2e,0xd8, + 0x6e,0xde,0x84,0x2b,0xd0,0xf7,0x40,0x69,0x70,0xc0,0x3b,0xc7,0x55,0x9f,0x13,0xd4, + 0xc5,0xf8,0x11,0x85,0x20,0x14,0x97,0x75,0xbe,0x5a,0xab,0x32,0xbd,0x0f,0xa1,0x3d, + 0x25,0xfb,0xeb,0xed,0x96,0x7f,0x67,0xbc,0x10,0xbd,0xe2,0x80,0xa8,0xf7,0xe8,0xc4, + 0xbf,0xae,0xa2,0xb2,0xf3,0x0d,0xe0,0x3f,0x81,0x07,0x51,0xff,0xf4,0xe5,0x6f,0xeb, + 0x78,0x9d,0x1a,0xbf,0x9a,0xfe,0x5d,0xf8,0xbc,0xdf,0xc1,0xf9,0x99,0xf0,0x61,0x20, + 0x95,0xc5,0xff,0xc1,0x45,0x38,0xe4,0x7b,0x1d,0x57,0xe3,0x61,0x2a,0x84,0x78,0x42, + 0xae,0x82,0xc3,0xca,0x5c,0x6a,0xd4,0x72,0x5e,0x3a,0x42,0xfc,0x9f,0xec,0xfa,0x87, + 0x23,0xb0,0xaf,0x2c,0xd0,0x18,0xd9,0x50,0x14,0x4a,0xae,0xf1,0x4c,0x8f,0x04,0xff, + 0x14,0x98,0x0e,0x6b,0xda,0x02,0xa9,0xf9,0x3d,0x81,0xe3,0xd0,0x85,0xd0,0x85,0xea, + 0xff,0xb8,0xf2,0xc1,0x07,0xf4,0x27,0x54,0xbd,0x1f,0x37,0xad,0x3e,0xde,0xce,0xa2, + 0x86,0xa7,0xaa,0x1d,0x51,0x1d,0x2e,0x83,0x2b,0x2d,0xfb,0x2e,0x3e,0xbd,0xf7,0x24, + 0x7b,0x3c,0xe2,0x1f,0xdf,0x3e,0x9e,0x30,0xd5,0x4d,0x4d,0x3e,0x1c,0x26,0xda,0x7e, + 0x85,0xe8,0xb2,0x56,0x63,0x11,0x7a,0x11,0xa2,0xfe,0x8f,0xb3,0x3e,0x11,0xff,0xec, + 0x4a,0x55,0x99,0x21,0x5f,0x57,0x05,0x5b,0xc3,0xaa,0x8c,0x9b,0x47,0xbd,0xc0,0x9f, + 0xc1,0x85,0x74,0xf5,0x93,0xf2,0xdb,0xb8,0xde,0xaa,0x44,0x7d,0x00,0x17,0xfe,0x79, + 0x52,0x11,0xde,0x9e,0xc1,0xe2,0x73,0x0a,0x02,0xa1,0xd6,0xfc,0xd1,0xe6,0xd3,0x4b, + 0xd2,0x65,0x9f,0x3f,0xe6,0x17,0xd4,0x86,0x03,0x59,0xf9,0x5f,0xad,0xda,0x4e,0xb4, + 0x5f,0xb8,0x2c,0x29,0xff,0xeb,0x90,0x8e,0xf6,0x2b,0x8c,0x6a,0xe7,0x35,0x43,0xd8, + 0xf7,0x29,0xca,0x99,0x9c,0xfa,0x67,0xfd,0xd9,0xf1,0x2f,0xaa,0x07,0x5e,0x6d,0xc6, + 0xe2,0x78,0xdb,0xaf,0xc6,0x02,0x94,0xdf,0x3d,0x53,0xdf,0xdf,0x2e,0xe2,0x5f,0x0a, + 0xec,0x37,0x42,0xa3,0xde,0xac,0xfa,0x3f,0x92,0xa8,0x7f,0x88,0xbb,0x03,0xd4,0x36, + 0x1b,0xa8,0x6c,0x5d,0x98,0xe5,0x40,0x72,0x99,0x4e,0x19,0x52,0x8e,0xab,0x70,0xd4, + 0x19,0x3f,0x2c,0x4d,0x36,0x7e,0xd9,0xf6,0x0f,0xd1,0xc8,0x22,0x56,0x5f,0xf2,0xd3, + 0xf8,0x94,0xc5,0x5d,0xd7,0x7d,0xf1,0x32,0xf5,0x31,0xc2,0x03,0xc3,0xac,0xc8,0xe1, + 0x03,0xbb,0xfd,0x3f,0xea,0x87,0x30,0xc7,0x0c,0xc5,0xbd,0x3e,0x78,0x09,0xe6,0xd0, + 0xfd,0x03,0x9c,0x80,0x70,0xdf,0xc2,0x70,0xb3,0xcf,0xf8,0x28,0x47,0x54,0x04,0x7a, + 0x35,0x93,0xff,0xf5,0x59,0xc1,0xff,0x31,0x27,0x0c,0xe2,0x6a,0xf9,0x18,0xf6,0x37, + 0x2e,0x1c,0x6d,0x26,0x47,0x59,0x43,0xaf,0x68,0x14,0x9b,0x2e,0x8d,0x98,0x8d,0x7f, + 0xd0,0xac,0xf7,0x52,0xfd,0x4c,0x38,0xc4,0xaa,0xa2,0xbe,0xbd,0xcf,0x84,0xd4,0x8f, + 0x3a,0xab,0x2d,0xc6,0xf8,0x19,0xa8,0x4b,0xf9,0xc6,0xd7,0x3f,0x5c,0x41,0xf8,0xa7, + 0xb5,0x68,0x12,0xac,0xa4,0x8d,0xd8,0x3d,0xcc,0xe9,0x08,0x3f,0x68,0x33,0xa2,0x5f, + 0x72,0x7d,0xef,0x3f,0x85,0x15,0x3c,0x5d,0xef,0x71,0x25,0x2f,0x8b,0x7a,0x6a,0x8a, + 0xae,0x90,0xf6,0x72,0x11,0x11,0xfb,0xad,0x78,0xde,0xac,0xfe,0xef,0x88,0x7f,0xd8, + 0xea,0xd4,0xd6,0xbe,0xe0,0x65,0x9e,0x50,0x53,0x3b,0x24,0x8c,0xe9,0xa8,0xc6,0x8d, + 0xdd,0xd4,0xff,0x62,0x0e,0x33,0x95,0xd9,0x16,0x9e,0x7c,0x35,0xab,0xfe,0xf3,0x61, + 0xb5,0x2a,0x81,0xf8,0x67,0x3a,0x1c,0x86,0x2a,0x5e,0x90,0x90,0xaf,0x40,0x84,0x8c, + 0x66,0xe2,0x98,0x4c,0x85,0x0e,0xeb,0xa9,0x23,0x7c,0x06,0x8f,0x5d,0xa2,0xff,0xd7, + 0x95,0xc7,0x60,0x6c,0x10,0x8f,0xb4,0x65,0x1a,0x73,0x8f,0xaf,0xff,0x5c,0x25,0xd8, + 0x3e,0x76,0xb7,0xaf,0xa9,0x56,0x04,0x24,0x5d,0xef,0x6e,0x89,0xa8,0x6f,0xec,0x3c, + 0xaf,0xf2,0x65,0x4a,0x5a,0xbf,0x25,0x46,0x6e,0x9f,0x36,0x83,0xba,0x7d,0x79,0xa6, + 0x9a,0xab,0x53,0x76,0x45,0x1a,0x2e,0x52,0xe3,0x53,0xce,0x7a,0x40,0xfc,0xa3,0xef, + 0x53,0x03,0x4d,0xaa,0xb6,0xa6,0x42,0x5f,0xad,0xa6,0xeb,0x3f,0xff,0xbc,0x10,0x61, + 0x8f,0x48,0xdc,0x50,0x05,0x95,0x65,0x7c,0xfd,0x9f,0x04,0x39,0x79,0x70,0x1b,0xa2, + 0xe8,0xe9,0xc4,0x28,0x84,0x3d,0xf3,0x5d,0x15,0x72,0xdc,0xf8,0xa7,0xd1,0x18,0x6d, + 0x0d,0x97,0xf8,0x72,0x64,0xa9,0xd5,0x44,0xe1,0xc8,0x0a,0x59,0x57,0x86,0x9d,0x19, + 0x90,0xea,0xb3,0xeb,0x3f,0xa7,0xf9,0x3f,0xe9,0x7e,0x5e,0x24,0x50,0xff,0xd3,0x73, + 0xe9,0x88,0x98,0x8d,0xf7,0xde,0x72,0xea,0xff,0x6c,0xca,0x19,0x32,0x70,0x5a,0x5a, + 0x7d,0x7b,0x9a,0x1f,0x84,0x83,0x46,0x55,0xab,0x7f,0x63,0x47,0x09,0xfc,0x2e,0x58, + 0x6d,0xac,0x8b,0xc3,0x50,0xde,0xef,0x2c,0xfe,0xf3,0x01,0x97,0xff,0xe7,0xad,0xc2, + 0xd8,0x83,0x81,0x69,0xea,0x1a,0x16,0x50,0xd6,0xf2,0x00,0xcc,0xef,0x0c,0x04,0x95, + 0x98,0x61,0x01,0x21,0x29,0xed,0x8a,0xcf,0xaa,0xff,0x83,0x66,0xab,0xdc,0x40,0xfc, + 0xbc,0xa7,0x74,0x85,0x68,0x73,0xef,0xa9,0x80,0x07,0x94,0x0a,0x43,0xc6,0xe7,0xf5, + 0xed,0xa2,0xc4,0xff,0x2c,0xfc,0x33,0xb1,0x93,0x3d,0xd6,0xb2,0x8d,0x68,0xcf,0x73, + 0xf8,0x7d,0x08,0x3b,0x3b,0xe2,0xb7,0x56,0xc0,0x6a,0xd3,0xc2,0x3f,0xe4,0xcf,0xbf, + 0xb8,0xfe,0xf3,0x3e,0x25,0x6c,0x84,0xe2,0xc5,0x9d,0xb8,0x2d,0xea,0x8e,0x8a,0xb2, + 0x87,0xaf,0x20,0x7e,0xf3,0x52,0x63,0x2f,0xab,0xb0,0xa1,0x94,0x6a,0xb3,0xef,0x9f, + 0xfc,0x3f,0x04,0x8a,0x8e,0xc4,0x8b,0x05,0xed,0xf9,0x33,0x08,0x8c,0x05,0xf1,0xbb, + 0x71,0x1d,0xf5,0x83,0x3b,0xa5,0xa6,0xeb,0x3f,0xdb,0xf3,0x6f,0xf3,0x7f,0x44,0xb5, + 0xe7,0x01,0x14,0xf2,0x71,0xdb,0x6b,0x35,0x82,0xef,0x94,0xa3,0xea,0x58,0x4e,0x95, + 0x94,0x8d,0x7f,0x44,0xfc,0x2b,0xc0,0x4b,0x75,0x44,0x3b,0xf7,0x13,0xbf,0x22,0x11, + 0xb8,0x22,0xf6,0x1b,0xb6,0xd5,0xe2,0x3f,0x53,0xfe,0x97,0x3f,0xab,0xfe,0x33,0xf9, + 0x9f,0xb9,0x9e,0x8a,0xd5,0x34,0x15,0xc0,0x1a,0x6e,0x11,0x81,0x58,0xba,0xec,0x33, + 0xed,0x17,0x3a,0xcd,0xac,0xfa,0xcf,0x82,0xff,0x6c,0x94,0x0d,0xaa,0xdf,0x64,0x57, + 0xa9,0x2b,0x8d,0xb2,0x61,0xcf,0x3d,0x9e,0x1a,0x54,0xe3,0x77,0xe2,0xf7,0xdb,0xf4, + 0x3a,0x3c,0xce,0xa7,0x1c,0xc8,0xc2,0x3f,0x3b,0x54,0xfc,0x9a,0xf8,0xee,0x44,0x70, + 0xd8,0x5b,0xcb,0xa8,0x1b,0xbb,0xff,0x74,0x07,0x7d,0xc8,0xb3,0x8e,0xf9,0x97,0x37, + 0xbf,0xa1,0xec,0x5d,0x71,0xed,0x16,0x81,0x7f,0x9c,0xef,0xe5,0x2a,0x57,0x3d,0x2e, + 0x6a,0xfb,0x95,0x4f,0xd6,0x8d,0x3c,0x18,0xeb,0x08,0x0f,0x7c,0x84,0xf6,0xb7,0xc0, + 0x5d,0x4f,0xde,0xb0,0xea,0xf7,0x46,0xd1,0x5a,0x3d,0x0e,0x67,0x3b,0x1b,0x3e,0xcc, + 0x1f,0xeb,0xa8,0x57,0xfe,0xd4,0x3e,0x3b,0xb5,0xf0,0x54,0xf3,0x79,0xed,0x0f,0x5c, + 0x6c,0xe4,0x07,0x1d,0x3e,0xf3,0x0e,0xe2,0x1f,0x6a,0x5b,0x8c,0xae,0x56,0x56,0xb2, + 0x78,0x0f,0x6a,0x9b,0xc8,0xb2,0xa2,0x49,0x06,0xea,0x9f,0x3e,0xaa,0xf0,0x03,0x7b, + 0xb5,0xb2,0xbe,0x82,0x65,0xec,0x3d,0x07,0xff,0x68,0xb0,0x09,0x9e,0x54,0xa7,0x30, + 0x6f,0x1f,0x6a,0xa7,0xc7,0xf8,0xcc,0x3e,0xd4,0x4e,0xad,0xfa,0x93,0x42,0x5f,0x89, + 0x42,0x88,0x5b,0xb8,0xd7,0x5d,0xff,0x79,0x49,0x49,0x3f,0x24,0x8d,0x0a,0xf0,0xaa, + 0xcc,0x10,0x44,0x44,0x04,0x12,0xcd,0xb0,0x2b,0x62,0xcd,0x67,0x94,0xf0,0xa4,0xc7, + 0xed,0xff,0xe9,0x99,0x88,0xfb,0x7d,0xa3,0xda,0x8a,0xf7,0x3d,0x01,0x0d,0x29,0xdf, + 0x28,0xfb,0x0a,0x9c,0x41,0xfb,0x22,0x77,0x0b,0x3e,0xf3,0x25,0xeb,0x3f,0x3f,0x41, + 0xd6,0x7c,0x27,0x4d,0x54,0xdf,0xe4,0xa4,0x37,0x41,0x82,0x93,0x08,0x46,0xf3,0x93, + 0xa9,0x47,0xc4,0xb5,0x31,0x38,0xae,0xce,0xa6,0xa4,0xa7,0x31,0x11,0x06,0x52,0x47, + 0x3f,0x55,0x17,0x3c,0x6f,0xa6,0xe3,0x5f,0x2f,0x52,0xc5,0x0f,0x77,0xfd,0x67,0xae, + 0x2c,0xc7,0x1d,0xe7,0x36,0xca,0x1f,0x1c,0x83,0x0f,0xd8,0x4c,0x33,0x36,0xca,0x02, + 0xc6,0x13,0x65,0x95,0x78,0xd9,0xc0,0x00,0x7e,0x08,0xf5,0x51,0xc2,0x3f,0x2d,0xf6, + 0xfb,0xe5,0x52,0x48,0xd9,0x27,0x9a,0x0c,0x16,0x6d,0xd7,0x7a,0xc8,0xdf,0x9e,0xcc, + 0xad,0x70,0x31,0xa8,0xad,0x54,0xf1,0x61,0x67,0xfd,0x58,0xf5,0x0f,0xa3,0x56,0xb6, + 0x05,0x55,0xfb,0xb9,0x22,0x5c,0xa4,0x40,0x37,0xf8,0x32,0xfb,0x7d,0x8a,0xb7,0x66, + 0xf2,0xdf,0xf3,0x97,0xd0,0xfa,0x97,0x44,0xfd,0xb1,0x7d,0x78,0xff,0x95,0xcb,0x3c, + 0xba,0x78,0x5e,0xaa,0x38,0x47,0x44,0x17,0xe2,0x87,0x9b,0x99,0xf5,0x79,0xd5,0x58, + 0xa1,0x1d,0xef,0x83,0xf7,0x61,0x9e,0x79,0xdf,0xe8,0x84,0x51,0xe1,0xf1,0x28,0x10, + 0x89,0x6f,0x56,0xff,0x82,0x54,0xc6,0xff,0x23,0xb9,0xfa,0x9f,0x5e,0xe0,0xd5,0x87, + 0x7c,0xdd,0xf2,0xc7,0xea,0x11,0x7d,0x76,0x4a,0xd4,0xc7,0x1e,0xa3,0xd6,0x2d,0x47, + 0x3f,0x97,0xc1,0x3f,0x5c,0xb5,0xeb,0x1f,0x16,0x91,0x30,0x7d,0x54,0xfd,0x57,0x14, + 0x54,0xc4,0x3f,0xea,0x0e,0x56,0x69,0xf4,0x28,0x01,0xf0,0x6c,0x42,0x7c,0xe2,0xe6, + 0xff,0xb8,0xf2,0x71,0x74,0x32,0xf4,0xb8,0xd1,0x30,0x74,0x03,0x11,0xa0,0x4f,0x74, + 0x30,0x54,0xb5,0xa6,0x13,0x19,0xfe,0x73,0xba,0xfe,0x8f,0x37,0xd9,0x24,0xea,0xff, + 0x98,0x6a,0xb2,0xe9,0x03,0x86,0x1b,0x3d,0x33,0x98,0xf0,0x84,0xa0,0x87,0x07,0xf4, + 0x2b,0xe2,0xae,0xfa,0x87,0x90,0xc9,0xff,0x5a,0x4a,0x85,0x8e,0x17,0x2b,0x49,0xf9, + 0x39,0x78,0x21,0x1e,0x4e,0xf9,0x2e,0x97,0xaf,0x31,0x3e,0x84,0xaa,0x46,0x5f,0xb2, + 0xd8,0x1c,0xcf,0x7f,0xb6,0xd9,0x3e,0x73,0x0d,0x7f,0xa2,0x79,0x0c,0x4e,0x49,0x0d, + 0xc3,0x94,0x81,0x62,0x53,0x7f,0xc7,0xf1,0x9f,0x5d,0xf1,0xe8,0xa8,0x2f,0x3e,0x61, + 0x06,0x02,0x75,0x5c,0x96,0x71,0xef,0x14,0xe3,0x20,0xaf,0xa2,0x44,0xe6,0x97,0xc7, + 0xd5,0xff,0xb1,0xcb,0x1e,0x42,0x6d,0xa3,0x9a,0x2c,0x22,0x44,0x14,0x38,0x88,0x6a, + 0x73,0x2a,0x8e,0xaf,0x6e,0xc5,0x27,0xca,0xe0,0x1f,0x53,0x59,0xa0,0xba,0xf3,0x95, + 0xe8,0xeb,0x10,0xdb,0xae,0x14,0xe2,0xc3,0x3c,0xd8,0x10,0x0d,0xc4,0xf3,0x00,0xf1, + 0x92,0xed,0xff,0x89,0x1a,0x77,0x64,0xd5,0x3f,0x1c,0xf6,0x2c,0xf1,0x4c,0x46,0xb5, + 0x73,0x67,0x0a,0xf7,0x4b,0x57,0xc0,0xca,0xc4,0x35,0x89,0xbc,0x9b,0xd8,0x59,0x6e, + 0xa4,0xc7,0x47,0xc0,0xaa,0xff,0x73,0x35,0x95,0x3d,0x44,0x61,0xc4,0x53,0xca,0x28, + 0x23,0x2c,0x6c,0x2e,0xac,0x2d,0x56,0xd9,0xab,0x89,0x30,0xff,0x89,0xc7,0x8d,0x7f, + 0xd2,0xf9,0xef,0xa2,0x2c,0xc0,0x19,0xb8,0xae,0x37,0x5f,0xd4,0x07,0xd0,0x1a,0xcc, + 0x75,0x88,0x07,0x1a,0xcf,0x6b,0xf5,0xbc,0xe0,0xa0,0xab,0xff,0x97,0x9a,0xe9,0x3f, + 0xeb,0x08,0x05,0xb4,0xa3,0x49,0xf9,0xc2,0x72,0xa5,0x70,0x04,0xf9,0x12,0xf8,0xfd, + 0x3a,0xfc,0x87,0xcb,0xc7,0xe5,0x7f,0x79,0x29,0x10,0xd6,0x21,0x09,0x8f,0x90,0x4f, + 0x6c,0x24,0x3d,0x51,0x76,0xc2,0x79,0xbf,0x99,0xfa,0x3f,0xd6,0xf3,0x8e,0x7a,0x4b, + 0xd9,0x64,0x6d,0x02,0x22,0xa2,0x3c,0x42,0x44,0xeb,0xf8,0x96,0x94,0xba,0xc4,0x55, + 0x7f,0x4c,0xf0,0x7f,0xa4,0xcc,0x7c,0xa6,0xbc,0x61,0x4f,0x3e,0xef,0x88,0xea,0x43, + 0x79,0xd5,0x2c,0x9f,0x0b,0xfc,0x1c,0x44,0xfc,0x93,0xe1,0x3f,0x67,0xd5,0xff,0xc1, + 0x8d,0x67,0x4a,0xbe,0x0e,0x0e,0x1b,0xdd,0x3c,0xff,0x1d,0xf9,0x7a,0x76,0x88,0xf8, + 0x3f,0x8f,0xca,0xa7,0x9d,0x7a,0xc5,0xd9,0xf5,0x7f,0xe0,0x5e,0xc9,0x0f,0x32,0xa9, + 0x8a,0x7a,0xb1,0xd5,0x36,0xc6,0xda,0xea,0xf5,0x19,0xe6,0xc5,0xf5,0x7f,0x32,0xf9, + 0x3e,0x0b,0xe3,0x13,0xd2,0x89,0xf0,0xa2,0x11,0x2a,0xdc,0xf3,0x97,0xea,0x1f,0xa6, + 0xd9,0x3b,0xf3,0x37,0xe6,0x3a,0x1e,0x1e,0x6a,0xf5,0x55,0x6d,0xa8,0x71,0x70,0xf1, + 0x7f,0x2e,0xae,0x7f,0x98,0x49,0x84,0xc7,0x85,0x67,0x96,0x1b,0xc1,0x51,0x17,0xfe, + 0xc9,0xae,0xff,0x03,0xa1,0x25,0x02,0xff,0xec,0x4a,0x90,0x47,0xc8,0xa3,0xf0,0xc7, + 0x94,0x29,0xc4,0xf0,0x74,0xe1,0x1f,0x9f,0x9e,0x8d,0xf7,0xfc,0xbc,0xc8,0x39,0x42, + 0x8d,0x50,0xf5,0x12,0x9f,0x29,0x1f,0xcf,0xe0,0x9f,0x9c,0xac,0xb4,0x26,0x8a,0x7f, + 0x79,0x09,0xff,0x34,0x50,0x86,0xfb,0x49,0x23,0x7d,0xea,0x1d,0x37,0xfe,0xb1,0xcb, + 0x1e,0x8a,0x7f,0x18,0x29,0xa0,0x7a,0xc8,0x1f,0x52,0x23,0xd4,0x0d,0x72,0x05,0x7f, + 0x51,0x9b,0xd7,0xe2,0xd3,0x70,0x6b,0xec,0xe0,0x9f,0xd2,0xac,0xfa,0x87,0x95,0x5a, + 0x64,0x05,0x09,0x86,0x68,0x84,0x3a,0x0b,0x62,0x50,0xa9,0xaa,0x9c,0xb9,0xf2,0xdf, + 0x9d,0xfa,0x3f,0xa2,0x1f,0xe5,0x8c,0x96,0xd8,0xa2,0x22,0x0a,0x5b,0x94,0x19,0xde, + 0xdb,0xd8,0x55,0x08,0xfc,0x04,0x63,0x2a,0x93,0xff,0x5e,0xaa,0xd8,0xf9,0xef,0xa2, + 0xfe,0xe4,0x4c,0x43,0x7d,0x09,0xf7,0x93,0xbf,0x84,0x72,0xc3,0x8b,0x88,0xc8,0x66, + 0x58,0xb9,0xf2,0xdf,0x27,0x2e,0x2e,0x75,0xdf,0xbf,0x51,0xb9,0x59,0x08,0x1b,0x5a, + 0x50,0x3f,0x54,0x30,0x11,0x11,0xd3,0xbc,0x99,0xfc,0xf7,0x88,0xd5,0xff,0xcb,0x1e, + 0x5f,0x27,0x88,0x40,0x06,0x45,0xc4,0x70,0x3d,0xf4,0x09,0xfc,0x33,0xd3,0x9d,0xff, + 0xae,0x6a,0x89,0xf1,0x78,0x7b,0x02,0x4e,0xbb,0xe8,0xff,0x55,0x1c,0x66,0xfd,0x5a, + 0x15,0x31,0xb2,0x3c,0x59,0xf1,0x2f,0x8b,0xe4,0x93,0x6b,0xd5,0x3f,0x8c,0x24,0x58, + 0x90,0x3f,0x81,0x78,0xbe,0x6b,0x2b,0x21,0x22,0xe3,0x5a,0xae,0xa6,0x98,0xc7,0x1e, + 0xee,0xca,0xff,0x6a,0x4a,0x17,0x6a,0xab,0xa1,0xb0,0x17,0x0c,0x9b,0x57,0xd6,0x30, + 0x15,0xe2,0xa6,0xde,0xa2,0xea,0xb9,0x1e,0x47,0xff,0xd8,0xf5,0x7f,0xd2,0xdf,0x6f, + 0xc8,0x88,0x7d,0x97,0x51,0x46,0x83,0x48,0x0c,0x2f,0x45,0x60,0x73,0x8d,0x81,0xd7, + 0x57,0x1d,0xfe,0xb3,0x5d,0xff,0xc7,0x4f,0xdf,0x2f,0x0a,0x89,0xfc,0xa0,0xe7,0xa7, + 0xf0,0x31,0xd5,0xff,0xa9,0xf1,0x7a,0xe0,0x08,0xdf,0x15,0x5d,0xb0,0xc4,0xeb,0xc9, + 0xf0,0x9f,0xc7,0xf1,0x7f,0xa4,0x9f,0x25,0x64,0x51,0x01,0xd8,0xb0,0x02,0x61,0x84, + 0x9f,0x13,0x2e,0xfe,0xb3,0x55,0xff,0xc7,0xca,0xf6,0x82,0x0b,0x71,0x14,0x36,0x95, + 0x7f,0x0c,0xcf,0x23,0xec,0xc9,0x3f,0x8a,0xb0,0xf0,0x75,0x7e,0xed,0x90,0x6f,0x18, + 0xf7,0xa7,0x0e,0xff,0x39,0x5d,0xff,0x47,0x78,0x7b,0x50,0x9f,0xb4,0x78,0xbf,0x28, + 0x6f,0x8c,0xae,0xa0,0xf5,0xd0,0xca,0x5e,0xe2,0x9d,0x30,0x63,0x40,0xd5,0x5d,0xfd, + 0xbf,0xdc,0xf5,0x7f,0x60,0xaf,0x3e,0x83,0x7b,0x9b,0x9a,0x4e,0xc2,0x4a,0x63,0x8b, + 0x99,0x87,0xe3,0x8d,0x4e,0xb8,0x86,0xf2,0xdf,0x87,0x5c,0xfe,0x9f,0xec,0xfa,0x3f, + 0xe0,0x85,0xf6,0x67,0x19,0x27,0x9a,0x7d,0x09,0x6e,0xd3,0x62,0xc4,0xff,0x0c,0x05, + 0x32,0xfc,0xe7,0x1e,0xf7,0xf3,0x9e,0xa6,0x7c,0xf3,0x27,0xcb,0xff,0x48,0x1e,0xfb, + 0x47,0xf2,0xb7,0x17,0x8f,0xc0,0x21,0xa9,0x9a,0x8f,0x3c,0x5c,0x7e,0xdc,0x89,0xf7, + 0x65,0xfa,0x5f,0x88,0xf1,0x38,0x1b,0x3d,0xf2,0x0e,0x38,0xc5,0xeb,0x61,0x42,0x42, + 0x1e,0xf1,0xbd,0xd7,0x38,0xd9,0x5c,0x48,0x85,0x29,0xec,0xeb,0x27,0x32,0xf9,0x5f, + 0xa2,0xcc,0x8b,0x00,0x42,0xfa,0x79,0xb8,0x9e,0xfb,0x52,0x1d,0x67,0xe1,0xb8,0x54, + 0xde,0xe9,0x4b,0xc9,0x15,0x0e,0xff,0x79,0x4b,0xa6,0xff,0x29,0xe2,0xb1,0xa8,0xe0, + 0xf3,0xbc,0xcb,0x11,0xd8,0x94,0x46,0xa8,0xff,0xe9,0x13,0xa9,0xc0,0x51,0x9c,0x9f, + 0xb0,0x13,0xaf,0xcc,0xea,0x7f,0xf1,0x04,0x09,0xb4,0x3b,0xa3,0x8e,0xf0,0xf8,0x19, + 0x0e,0x69,0x3d,0x7c,0x3a,0xb9,0x6a,0x9d,0xe5,0x96,0xe1,0xff,0x54,0x89,0x6a,0x48, + 0xa1,0xd6,0xf9,0x5a,0xbb,0x89,0x5f,0x68,0x25,0x4e,0x0d,0x7b,0xae,0x2c,0xa9,0x05, + 0xcd,0x60,0x59,0x53,0x26,0x3e,0xcb,0xd3,0xfd,0x2f,0xec,0xe7,0x8d,0xfb,0x57,0xe1, + 0x87,0x70,0x5a,0xaa,0xe5,0xa1,0x15,0xf2,0x10,0xa7,0x1e,0xbf,0xbe,0x84,0x57,0xcf, + 0xf4,0xbf,0x98,0x68,0xd7,0x3f,0xc4,0xe7,0x3d,0xad,0x7d,0x8f,0x80,0xd0,0xa0,0xc5, + 0x80,0x3a,0x80,0x1b,0xb1,0xb3,0xfa,0x5c,0xd3,0xff,0x16,0x1b,0xce,0xc4,0xb3,0xa4, + 0xb1,0x8a,0xb3,0x65,0xb3,0xc1,0x1c,0xfc,0x9b,0x5a,0xf5,0x79,0xfe,0x3d,0xdd,0xbf, + 0xac,0xbc,0x5e,0x3b,0x6f,0xc5,0xbf,0xc8,0x35,0x64,0xf5,0x7f,0x77,0xf9,0x7f,0xde, + 0x83,0x1e,0x33,0xa0,0xa9,0x97,0xe1,0xd7,0xd1,0xd5,0x36,0x75,0xcb,0xfc,0x31,0x56, + 0x4f,0xb4,0x1c,0x1b,0x11,0x09,0x22,0xb4,0xab,0xfe,0x73,0x0e,0xe2,0x61,0x2d,0x7a, + 0x85,0xaa,0xb4,0x07,0x4b,0x3a,0x60,0xa9,0xee,0x25,0xd8,0xd3,0x1d,0x24,0x3c,0x5c, + 0x34,0x60,0x9b,0x7e,0x77,0xfd,0xe7,0x1d,0x7a,0x8f,0x4a,0x41,0xfc,0x40,0x90,0xf2, + 0xc7,0xcb,0x28,0xb1,0x4e,0xdb,0x4f,0xfe,0x1f,0x0b,0x11,0x89,0xa9,0xce,0xe0,0x1f, + 0xb3,0x64,0x9f,0x76,0xd2,0x98,0xdd,0x12,0x1a,0x95,0x83,0xec,0x05,0xa8,0xd4,0xfd, + 0xa3,0x4d,0x75,0x70,0xd6,0xe8,0xb6,0x66,0x6c,0xbf,0x55,0xc1,0x20,0xe3,0x1f,0x38, + 0x06,0x3d,0xea,0xd9,0xc0,0x53,0x51,0x41,0x72,0x46,0xfc,0xd3,0xe6,0x1f,0xfd,0x9b, + 0xef,0xc2,0x9f,0xe1,0x69,0xf3,0xef,0x33,0xfc,0x67,0x39,0x53,0xff,0xb9,0x55,0x7b, + 0x04,0xfa,0x8d,0xb0,0xe1,0x4b,0x34,0x07,0x95,0xd7,0xa4,0x6a,0xd5,0x1f,0x6e,0x0e, + 0xe1,0x8b,0xa8,0x72,0xf2,0x13,0xcd,0xec,0xfa,0x87,0x4a,0x10,0x62,0x26,0x1a,0xa9, + 0x87,0x68,0x7e,0xa0,0x4a,0xf6,0x8e,0xae,0x09,0x99,0xfb,0xad,0xb6,0x29,0x54,0xda, + 0x28,0x80,0x40,0xda,0xe5,0xff,0x19,0x96,0x16,0xb0,0x8e,0xfe,0x0a,0xbe,0x64,0xf3, + 0x1a,0x95,0x3d,0xc0,0xf4,0x84,0xb7,0x06,0xe7,0x67,0x17,0xe8,0xa2,0x1e,0x14,0xec, + 0x5e,0x56,0x91,0xed,0xff,0x39,0xd1,0x46,0xd1,0x9f,0x07,0x13,0xea,0xdf,0x21,0xda, + 0xf9,0x21,0x2f,0xdb,0xee,0xfd,0x16,0xc2,0x80,0x5f,0xf2,0x29,0x6f,0xa7,0x11,0x42, + 0x19,0x55,0x48,0xce,0xae,0xff,0xfc,0x4c,0x70,0x4e,0xcc,0x27,0x35,0xa9,0xca,0xaf, + 0xb5,0x24,0xb5,0x89,0xc1,0xeb,0x47,0xc3,0xa6,0x7f,0x96,0x3c,0x60,0x7e,0x04,0x56, + 0xff,0x77,0x17,0xff,0x67,0xa7,0xf1,0x11,0xf5,0xc3,0x5a,0x8d,0xda,0xe6,0xe7,0x4a, + 0xbd,0x44,0x61,0x2c,0xd2,0xcf,0xc2,0x1f,0xdb,0x7a,0x46,0xb3,0xfa,0xdd,0x3b,0xfc, + 0x9c,0x1d,0x39,0x23,0xda,0x0b,0xb0,0x81,0x9c,0x6c,0x41,0x41,0xd4,0xf7,0x25,0xdb, + 0x42,0x04,0x3b,0x11,0x3f,0x97,0x3b,0x9f,0xaa,0xab,0xfe,0xf3,0x7a,0x62,0x77,0x97, + 0x23,0xda,0xf1,0x94,0xaa,0x73,0xc9,0xdb,0x33,0x47,0xbe,0x5d,0xd9,0x0b,0xd3,0x4c, + 0xcf,0x32,0xe6,0x94,0x16,0xc9,0xd4,0x7f,0x26,0xff,0x0f,0x45,0xbb,0xa6,0x2d,0xc5, + 0xe7,0xdd,0xcb,0x67,0xea,0xea,0xf2,0xdc,0xc9,0xfc,0x69,0xcb,0x23,0xf4,0x17,0xf2, + 0xdf,0x69,0xf7,0x7a,0xb9,0xee,0x09,0xd2,0x87,0xa6,0xa9,0xd4,0xff,0x62,0x7f,0x49, + 0x50,0x54,0xdc,0xd2,0xd2,0xeb,0x2d,0xab,0xfe,0x33,0x82,0x9c,0xee,0x78,0xde,0xb0, + 0x5c,0x83,0xaf,0x75,0x1e,0x5f,0x9b,0x28,0x0e,0xe2,0x8e,0x75,0xab,0xe8,0xff,0x2e, + 0x2a,0x42,0xaf,0x4b,0xb0,0xd3,0x0e,0xdf,0x23,0x02,0x22,0xec,0xc5,0x0a,0x4c,0xcb, + 0x1e,0x69,0x33,0xd3,0xfc,0x1f,0x2d,0xd3,0xa1,0x9b,0xf2,0xdf,0x33,0xf8,0x67,0x08, + 0x7a,0x13,0xdd,0xc6,0x52,0x6d,0xbe,0xb0,0x86,0x4d,0x68,0xcd,0xaf,0x51,0x4e,0x41, + 0x55,0x34,0x5f,0x10,0x3f,0xe0,0x5e,0x63,0x7c,0xff,0x2f,0x6d,0x35,0x91,0x4c,0x36, + 0x06,0x88,0x76,0x5b,0xdf,0x8a,0xd6,0xb6,0x5a,0xd9,0x07,0x77,0xdd,0xf8,0x17,0xf2, + 0xdf,0x95,0x0a,0x76,0x9f,0x51,0x66,0xa8,0x83,0xed,0x16,0x4d,0x37,0xb8,0xfe,0x2d, + 0xc2,0x3f,0x53,0xb3,0xf8,0xd2,0x59,0xfd,0xbf,0xf8,0x0a,0xbd,0x2c,0x52,0x7a,0x2b, + 0xb9,0x7d,0x94,0x90,0x69,0x35,0xc2,0xd0,0xf5,0x34,0x22,0x62,0x69,0xff,0x8f,0x7d, + 0x3f,0x3d,0x2a,0x55,0xdb,0xeb,0x2e,0xf1,0xdd,0x40,0x6d,0xbf,0x44,0xfe,0x3b,0xa5, + 0x7d,0xb5,0x3e,0x0e,0xe9,0x8a,0x7c,0x44,0x4d,0xbc,0x26,0x53,0xff,0xb9,0xff,0x72, + 0xd1,0xe4,0xab,0xc5,0xbf,0xbe,0x99,0xd2,0xd8,0xaf,0x33,0xbc,0xeb,0xaf,0x1c,0x32, + 0xfe,0x99,0x22,0x62,0xf1,0xf2,0x74,0x28,0x30,0x8e,0x78,0x29,0xc3,0xff,0x79,0x87, + 0x9f,0x4b,0x14,0xdd,0x15,0xda,0xfc,0xcc,0xb3,0xb4,0x1b,0x35,0x0a,0x06,0x3b,0x3e, + 0x86,0x83,0xc1,0x06,0xea,0x9f,0x4e,0xf1,0x20,0x91,0x0f,0x7e,0xc8,0x55,0xff,0xe7, + 0x58,0x0b,0x6e,0x9a,0x6a,0xd5,0x01,0x51,0xed,0xb0,0x56,0x52,0x3b,0x8b,0x50,0x40, + 0x45,0x6d,0xf0,0x80,0x93,0x08,0x3f,0xae,0xfe,0x33,0xcd,0x0f,0xa5,0xbd,0x53,0xd9, + 0x0d,0x8f,0x56,0x44,0xb4,0x67,0xd1,0x31,0xc4,0xf1,0x77,0xb9,0xea,0x1f,0x8a,0xfc, + 0x77,0xdc,0xa6,0x0d,0xb6,0x13,0xdb,0x79,0xba,0x11,0x8b,0x07,0x50,0x28,0x21,0xfe, + 0x15,0x1b,0x92,0xec,0xf9,0x1c,0x57,0xff,0xb9,0xdb,0x10,0x69,0xef,0xab,0x09,0xbf, + 0xc5,0x8b,0x29,0xec,0x35,0x49,0x1c,0x51,0xec,0xfc,0x77,0x6e,0xcf,0xff,0x57,0xa5, + 0xed,0x0a,0x35,0xf9,0xfa,0x37,0x8b,0xed,0x5c,0xdb,0x42,0x40,0x28,0x70,0xaa,0x3d, + 0x8d,0x88,0xce,0x58,0xe3,0x5f,0xcd,0xe4,0x73,0x09,0xfc,0x73,0x2f,0x2c,0xe8,0x93, + 0x89,0x6d,0x45,0xd5,0xc5,0x3b,0x52,0x5a,0xbf,0x15,0xf6,0xc2,0x15,0xa8,0x8b,0xf5, + 0x96,0x9d,0xff,0x45,0xdd,0xeb,0xd4,0x94,0xf0,0xff,0xcc,0x58,0x15,0x1b,0x42,0x45, + 0xf7,0x2a,0x94,0x0b,0xff,0x8f,0x96,0xae,0x70,0xd5,0xee,0xac,0x07,0xca,0xff,0xda, + 0x35,0x1a,0x32,0x77,0xe8,0xb8,0xbb,0x6c,0xc7,0xfd,0x42,0x5e,0x09,0x7b,0x91,0xea, + 0x1f,0xb6,0xa4,0x3b,0x82,0x8d,0xab,0xff,0x2c,0xfa,0x5f,0xd0,0x67,0xbb,0x24,0x50, + 0x67,0xac,0x84,0x99,0xa6,0xda,0xda,0xbe,0x11,0xd6,0x25,0xfe,0x11,0x44,0xfe,0xfb, + 0x1e,0x43,0x7c,0xbf,0xb1,0x16,0xc3,0xbe,0x7e,0x6c,0xb2,0xf2,0xa7,0xce,0x99,0xf8, + 0x89,0xc8,0x93,0xdb,0x9f,0xe3,0xf3,0x8e,0xe5,0x2f,0x62,0x87,0xe1,0x87,0xa9,0x69, + 0xba,0x53,0x11,0x7a,0xe1,0xf2,0xf2,0x4c,0x3e,0x9a,0x7a,0xf9,0x4e,0x78,0x97,0x09, + 0x12,0xef,0x07,0xea,0x69,0xdc,0xb8,0x1d,0x89,0x97,0x8f,0xb0,0x8f,0x00,0xd7,0x1b, + 0xe9,0x93,0x31,0x23,0xed,0xff,0xb1,0xbf,0x47,0x63,0xe2,0x79,0x43,0x90,0x7c,0x86, + 0xa1,0xa1,0x75,0x65,0x7c,0xdb,0x90,0xff,0x15,0xf9,0x0a,0xe3,0x79,0x3e,0x97,0xea, + 0x1f,0x9e,0x6f,0x3d,0x6f,0x0a,0xfb,0x95,0xa9,0xff,0xfc,0xa8,0xb4,0xd9,0x78,0x4c, + 0x99,0x31,0x10,0xbc,0x8b,0x3d,0x79,0x20,0x17,0xca,0x0e,0x7b,0x6f,0x09,0x94,0x98, + 0xab,0x60,0xd7,0xc6,0x02,0x44,0x74,0xc6,0xe3,0x70,0x1d,0xf1,0x0f,0xdf,0x73,0xde, + 0x6f,0x1c,0x36,0x6b,0x8f,0x69,0x33,0xcc,0x48,0x4d,0xee,0x1d,0xe4,0xaf,0xe6,0x5d, + 0x06,0x2b,0x2d,0x5a,0x87,0xf3,0x40,0x08,0x30,0xf2,0xb8,0xa5,0xaf,0x52,0x2e,0xfc, + 0x23,0xf2,0x4f,0x7b,0xd5,0x9e,0xa6,0xb5,0x38,0x9f,0x89,0x94,0x17,0x6e,0xf2,0x41, + 0x87,0x52,0x01,0x14,0x61,0x54,0xba,0x41,0x28,0xa2,0x8c,0xbd,0xe8,0xc1,0xfd,0xe3, + 0x87,0xc4,0x6f,0x59,0x23,0xd7,0x01,0xee,0xb6,0x86,0xfc,0x1a,0x0b,0xa9,0x47,0x8e, + 0x86,0x21,0xbd,0x83,0xb6,0xfa,0xbf,0x3b,0xfc,0x3d,0x0e,0x3b,0x09,0x66,0xa3,0xb6, + 0xf1,0x8e,0x28,0x88,0x07,0x06,0x17,0xc6,0x71,0x19,0x9c,0x61,0xb5,0xb0,0x4e,0xcc, + 0x8f,0xe5,0x1f,0xcb,0xd4,0x7f,0x5e,0xcf,0xc9,0xe9,0xb1,0xab,0xd0,0xf7,0xab,0x8e, + 0x3a,0x9c,0xf8,0x06,0xe2,0x9b,0x55,0xa3,0xbd,0x9b,0x0d,0x9b,0xd1,0xde,0x29,0x17, + 0x12,0xc2,0xde,0x65,0xea,0x3f,0x9b,0x2d,0x4b,0xe1,0x09,0xb3,0x5c,0x53,0x07,0x71, + 0xf7,0xb4,0x06,0x2a,0xdf,0xf2,0xae,0x47,0xf4,0xf2,0x34,0x04,0xc2,0xa2,0x22,0xf1, + 0x70,0x3a,0xfe,0x95,0xcd,0xff,0x31,0x19,0x88,0x32,0xc8,0x6b,0x88,0x0f,0x13,0x67, + 0xd3,0x38,0x9a,0x39,0x25,0x96,0x2c,0x1a,0x51,0x7a,0x58,0x65,0x76,0xff,0x2f,0xc2, + 0x3f,0xbb,0x88,0xef,0x0a,0x1e,0x8a,0xef,0x50,0x35,0x80,0xe9,0x40,0xb4,0x04,0x31, + 0x3f,0x6a,0xc2,0xe2,0xc3,0x64,0xf6,0x5f,0xfc,0x2a,0xe2,0xff,0x84,0x61,0x41,0xbc, + 0xb8,0x4e,0x94,0x9d,0xc1,0xaf,0x5b,0x57,0xce,0x40,0x37,0xa8,0xa2,0x43,0x9c,0x35, + 0x3f,0x66,0x16,0xfe,0xf9,0x25,0xa3,0xfe,0x17,0xe5,0x02,0xef,0x19,0x7e,0xf3,0xd3, + 0xa3,0xda,0x85,0x1c,0x3c,0x42,0xf5,0x6d,0x46,0x2c,0xff,0xcf,0xc5,0xf5,0x9f,0x05, + 0xda,0x39,0xc3,0x1b,0x46,0xfd,0x63,0xe5,0xe7,0x15,0x01,0xa4,0x05,0x7f,0x9e,0xcf, + 0x3e,0x76,0xb5,0x1b,0xff,0x50,0xfe,0x17,0x15,0xf9,0xf1,0xf6,0x94,0xff,0x02,0x61, + 0x49,0x65,0x6f,0x17,0xf5,0xbf,0xd8,0xaf,0xa7,0x1b,0x61,0x10,0x71,0x8e,0xf0,0xcf, + 0x78,0xff,0x4f,0x6f,0x57,0x1a,0x0f,0xf7,0x53,0xa1,0x63,0x65,0x77,0x85,0x85,0x90, + 0x7d,0xbb,0x95,0x44,0xaf,0x27,0x1b,0xff,0x38,0xfe,0x9f,0x9d,0x6e,0x47,0x8a,0x25, + 0xe4,0xed,0xb6,0x3a,0xc2,0x8f,0x66,0xfb,0x7f,0x72,0x2c,0x7c,0xa8,0x64,0x36,0x0e, + 0xdc,0x16,0x44,0xfe,0x17,0xe2,0x13,0x77,0xfe,0x17,0x81,0x1c,0x6f,0x1a,0xed,0xf4, + 0x52,0x61,0x4c,0x7a,0xde,0xb4,0x47,0x48,0xb1,0xf0,0xcf,0xa5,0xea,0xff,0x5c,0xec, + 0xe8,0x58,0x0a,0x67,0xca,0x28,0x50,0xdb,0x3c,0xbe,0xfe,0x73,0xe6,0xb6,0x53,0x96, + 0xa0,0xd8,0x15,0x1d,0x1b,0x11,0x28,0x92,0xff,0xc7,0x5e,0xcf,0x17,0xf5,0xbf,0xe8, + 0x0a,0x83,0xed,0x31,0x2b,0x5a,0x80,0xcb,0x54,0x4f,0xe1,0xa9,0xb1,0x4c,0xfd,0xb1, + 0xac,0xfe,0x17,0x89,0xec,0x46,0x18,0x93,0x0d,0xc2,0x3f,0x57,0x12,0x1e,0xb0,0xaf, + 0x6f,0xf5,0xff,0xaa,0xeb,0xb3,0xda,0x7e,0xf1,0xba,0xe7,0x44,0xda,0x97,0xa8,0x08, + 0x54,0x25,0xdf,0x8c,0x50,0x27,0x79,0x80,0xf0,0xcf,0xc5,0xf5,0x0f,0xd3,0xf3,0xd3, + 0x67,0x09,0x1a,0x1e,0x59,0x46,0xdf,0x0b,0xa4,0xf1,0x8f,0x3d,0x3f,0x3b,0xc6,0xfb, + 0x7f,0xec,0x42,0xdc,0x94,0x11,0x56,0xc0,0x44,0xc6,0x9c,0xbb,0x7e,0x85,0xd5,0xff, + 0x7d,0x86,0x95,0xed,0x45,0x42,0x97,0x68,0xa4,0x28,0x95,0x51,0xff,0xa0,0xcd,0x16, + 0x91,0x80,0xe2,0x5f,0xf6,0xf5,0xcd,0x71,0xfe,0x9f,0x94,0x03,0xf3,0x44,0x46,0xd8, + 0xaa,0xce,0x69,0x24,0x8c,0x66,0xd7,0xff,0x51,0x9c,0xea,0xd9,0x53,0xad,0x89,0xdd, + 0x6f,0x39,0xf6,0xd7,0xda,0xfd,0x1c,0xff,0x62,0xff,0x0b,0x4a,0xfb,0x22,0x21,0x21, + 0x68,0x3f,0x41,0x38,0xc4,0x6a,0x45,0xff,0x8b,0x4b,0xd4,0x3f,0x4c,0xf7,0x83,0x98, + 0x90,0x71,0x8c,0x38,0x42,0xf1,0xf8,0xfc,0x77,0x7b,0xbf,0x2f,0xd5,0x37,0xfa,0x5c, + 0x65,0x81,0x51,0xd0,0xd2,0xfd,0x4f,0x9d,0xfc,0xd3,0xf1,0xfe,0x9f,0xa0,0x10,0xb4, + 0x80,0x7d,0x24,0x10,0xcd,0xca,0xff,0xba,0xa8,0xff,0x45,0xcc,0x29,0x53,0xb3,0x09, + 0x85,0x59,0xca,0xd6,0x88,0xc0,0x3f,0xf6,0x7a,0xc8,0xee,0x7f,0x81,0x13,0x15,0xb1, + 0x60,0x40,0xd0,0xf6,0x08,0x09,0x20,0x94,0xa9,0xbf,0x9a,0x95,0xff,0x45,0xf9,0xfe, + 0x3e,0xd1,0x88,0xb3,0x35,0xdd,0xf8,0x75,0x59,0x6b,0x55,0x09,0x0a,0xc7,0x33,0xf9, + 0x5f,0xe9,0xfa,0x3f,0xf3,0x5d,0xd6,0x9f,0xdc,0xaa,0x14,0xcf,0x12,0x0f,0x4e,0x1d, + 0x3f,0x59,0xc6,0xff,0x53,0x9a,0xe5,0x2f,0x92,0x1a,0x5a,0xd7,0x8a,0xf1,0x46,0x95, + 0x15,0x41,0x7b,0xd1,0x98,0xdd,0xea,0x1f,0xd7,0xff,0x5d,0x80,0x9c,0x82,0xb4,0xff, + 0x87,0xbc,0x3d,0x29,0xb5,0x47,0x4f,0x13,0x81,0xb8,0x1e,0xa0,0xd4,0xf8,0xec,0xfe, + 0xef,0x6e,0x7f,0x97,0x39,0x4c,0xc2,0xbe,0x34,0xf1,0x09,0x11,0x51,0xc2,0x7a,0x5e, + 0x57,0xfe,0xbb,0x98,0x46,0x8f,0x53,0x7f,0xdb,0xea,0x7f,0x2a,0x3c,0xfc,0xc4,0x17, + 0x4a,0xf7,0x93,0xb5,0xd7,0x83,0x93,0xff,0x65,0xfb,0x7f,0xc4,0xfb,0xfd,0x10,0xba, + 0xed,0xfc,0xaf,0x2a,0xab,0xfe,0x8f,0x7d,0xfd,0xa0,0xab,0xfe,0x8f,0x96,0xf5,0x0f, + 0x6d,0x41,0xe4,0xbf,0x8f,0xeb,0xff,0x95,0xb5,0xba,0x1a,0x33,0xeb,0x4d,0x1b,0xe3, + 0x02,0x08,0xb9,0xfa,0xc5,0x2b,0x59,0xfd,0x2f,0x66,0xa6,0xc3,0x5e,0xa9,0xca,0x36, + 0x14,0x8e,0xc2,0x53,0x14,0xda,0x18,0xdf,0xff,0xeb,0x12,0xfd,0x2f,0xfa,0x45,0x59, + 0xa4,0x7e,0xdc,0x2f,0xe8,0x83,0xde,0x30,0x64,0xfa,0xbf,0xeb,0x52,0x96,0xff,0x47, + 0xb4,0xfd,0x4a,0x3b,0x72,0x5b,0xf1,0xfa,0xe9,0x40,0xf6,0x70,0xe6,0xfa,0x8e,0xff, + 0x27,0xd3,0xff,0xc2,0x11,0x5e,0x25,0xea,0x05,0x55,0x44,0x7c,0xef,0xe2,0xfa,0x87, + 0x97,0xd2,0xb7,0xc3,0x69,0xa1,0xdc,0x55,0xff,0x70,0x62,0x56,0xfc,0xa2,0x7e,0xb1, + 0xaf,0xa7,0xfc,0x5e,0x38,0xc7,0xaf,0x4f,0xf9,0x37,0xc9,0xa7,0xd9,0xa1,0x38,0xf1, + 0x37,0x26,0x98,0x19,0xff,0x8f,0xed,0x7f,0x0e,0x5b,0xb7,0x3d,0xa4,0xd6,0xe2,0xb6, + 0xeb,0x31,0x03,0xf5,0xcf,0x17,0x03,0xfd,0xb0,0x2a,0x51,0xd6,0xab,0x7e,0xdb,0xe5, + 0xff,0x01,0xc8,0xf6,0x57,0x47,0x3c,0xf7,0x88,0x6d,0x9a,0x68,0x84,0x7a,0x14,0x56, + 0xea,0x22,0x82,0xef,0xaa,0xff,0x93,0x5d,0x7f,0xbe,0xd2,0xb4,0xf6,0x5f,0x56,0xc7, + 0x87,0x7e,0x8b,0x21,0x8c,0x82,0xab,0xfe,0xa1,0xf3,0xbc,0x4b,0x4b,0x68,0xff,0xb8, + 0x80,0xcc,0x8a,0x15,0xcf,0x6a,0x1e,0xa6,0xf5,0xc3,0xa9,0xff,0x45,0xa6,0xfe,0x21, + 0xb8,0xad,0x8f,0x88,0xfe,0x50,0xd9,0xe7,0x3e,0x41,0x73,0x1d,0xa6,0x56,0x3b,0x6d, + 0x0b,0x93,0x5f,0x72,0xd7,0x3f,0x3c,0x5b,0x9a,0x36,0x6a,0x96,0xbd,0xdb,0x88,0x42, + 0x29,0xd5,0xff,0x99,0x30,0xda,0x3c,0x26,0xfd,0x77,0x4a,0x7d,0x72,0xe3,0x9f,0x36, + 0x65,0x69,0xa6,0x6d,0x13,0x95,0xa1,0xbe,0x21,0x19,0x20,0xc7,0x8e,0x30,0xbb,0xc3, + 0xda,0x6b,0x3c,0xc0,0xd5,0x64,0x53,0xca,0xdd,0xff,0x2b,0x6d,0xef,0x40,0xd8,0x3b, + 0xe9,0x26,0x11,0x76,0x87,0xe9,0x66,0x57,0x37,0x2e,0x03,0xea,0x08,0x1f,0x49,0x16, + 0xb9,0xfa,0x7f,0x41,0xda,0xff,0x33,0x2b,0x77,0x40,0x7b,0xa0,0x28,0xb4,0x63,0xcd, + 0x9c,0x76,0x42,0x8c,0x41,0x6a,0xd4,0xd8,0x4f,0xf5,0x28,0x52,0x6a,0x55,0x7b,0x46, + 0xff,0x80,0x8a,0xd7,0x77,0xea,0xcb,0x19,0x75,0x9f,0xb9,0xe9,0xf1,0xf2,0x11,0xe5, + 0x23,0xe5,0x0a,0xd3,0xdf,0xdd,0x31,0x6c,0xdc,0xa5,0x86,0x0d,0x5f,0xb7,0x64,0x66, + 0xf2,0xbf,0xae,0xa2,0x24,0x37,0x7c,0xde,0x13,0x94,0xdd,0xa6,0x37,0xf4,0xe5,0xdb, + 0xfd,0xbb,0xd7,0x8d,0xca,0x47,0xf9,0x07,0x56,0x45,0xcd,0x61,0x47,0xff,0xc0,0xb3, + 0x39,0xf2,0xdd,0xc6,0xed,0xad,0x73,0x73,0xaf,0x7a,0x16,0xee,0x36,0x5e,0xd7,0xe6, + 0x96,0xe4,0x3f,0x3b,0xf1,0x6e,0xb8,0x1d,0x3e,0x35,0x29,0xa7,0x57,0xba,0xbb,0xf1, + 0x75,0xed,0x53,0x4a,0xbe,0x39,0xcb,0xb9,0x9f,0x1b,0x6e,0x54,0x66,0x49,0x3e,0xa3, + 0x59,0xbb,0xaa,0x4f,0xba,0xbb,0xed,0xbf,0x19,0x9f,0xd3,0x26,0xf6,0xe5,0xce,0x82, + 0xb5,0x8d,0xff,0x53,0x83,0x3e,0x98,0x25,0xdd,0x6e,0x7c,0x41,0xcb,0x31,0x0b,0xed, + 0xfb,0x81,0x4e,0x56,0x76,0x77,0xec,0xf6,0xe8,0xa7,0x7c,0x4a,0xbb,0x54,0xc6,0x23, + 0x7a,0x89,0xaa,0xac,0x94,0xee,0xe6,0x8b,0xf4,0xa2,0xd2,0x9c,0x03,0x28,0x44,0xf4, + 0x22,0x55,0x71,0xd1,0xcd,0xb8,0x52,0x16,0x55,0x17,0x79,0x2e,0x83,0x9c,0x4e,0xdc, + 0x74,0x97,0xb2,0xcb,0xb4,0x1b,0x38,0x1e,0x89,0x40,0xae,0xfe,0x7d,0x3e,0x25,0x2a, + 0x2d,0x82,0xcf,0x43,0x0e,0x0f,0x1b,0xce,0xfd,0x2f,0xca,0xa9,0x6a,0xbb,0x8a,0x7f, + 0x6e,0xd6,0xc4,0xa3,0x4a,0x95,0x74,0x15,0x6f,0x5e,0x52,0x72,0x54,0x0a,0x68,0xb7, + 0x6f,0xfc,0x42,0x14,0x62,0xd2,0x3d,0xd2,0xed,0xf1,0x4f,0xeb,0xee,0xfb,0x79,0xd6, + 0x88,0xea,0x50,0x5a,0x81,0x1f,0x1c,0x37,0x50,0x50,0x98,0x04,0xbc,0xa5,0x4c,0x2a, + 0x85,0x5c,0x49,0xe3,0xb8,0xcc,0x50,0x50,0x0a,0x79,0xa1,0x73,0x3f,0xcf,0x46,0x94, + 0xbb,0x24,0x95,0xdf,0x18,0xd6,0xd6,0x90,0x60,0xde,0xa8,0x17,0xb6,0x2b,0x65,0x6d, + 0x2a,0x34,0x41,0x2b,0x2f,0x09,0x08,0x41,0xe3,0x99,0xf9,0x79,0x76,0x7e,0xce,0xad, + 0xbd,0xad,0x89,0xbf,0xc5,0x0d,0x94,0x22,0x84,0x9a,0x89,0x4d,0xf8,0x27,0x5a,0xef, + 0x2e,0x51,0x73,0x98,0xd4,0x64,0xb6,0x46,0x4b,0xd4,0x89,0x90,0xb9,0x1f,0x3e,0x49, + 0xfa,0x14,0xdc,0x60,0x4e,0x5c,0xb6,0xe2,0x76,0x4b,0x58,0x9e,0x73,0xbb,0xf4,0x05, + 0x68,0x1c,0x2c,0x5c,0xa6,0x4c,0x92,0x26,0xc0,0x6d,0x78,0x4a,0x81,0xcc,0xf3,0x72, + 0xaa,0xfd,0x92,0xab,0x2a,0x9a,0xa4,0xc7,0x51,0x88,0x2a,0x71,0x29,0x08,0x8d,0x92, + 0x66,0x34,0x72,0x71,0x5e,0x31,0x15,0x5c,0xf5,0x99,0xf9,0x7c,0x96,0xf8,0xc5,0x2b, + 0x15,0x9d,0xc7,0x74,0x1d,0x05,0x40,0xa1,0x82,0xe5,0x49,0xed,0x50,0x16,0x2f,0xd5, + 0x73,0x55,0xc4,0xe0,0x3a,0x2f,0x95,0x5c,0xf3,0xd3,0x9a,0xb3,0x58,0x7a,0x05,0x2e, + 0x33,0x26,0xc6,0x27,0x2c,0x96,0xfe,0x8e,0x7d,0xde,0xc8,0x11,0x02,0x7c,0xde,0x98, + 0x14,0x9f,0x50,0x81,0xf3,0xff,0x4f,0xc6,0x44,0xf7,0xf3,0x1a,0xf2,0x32,0x78,0x1d, + 0xe6,0x12,0x31,0x21,0x0a,0x47,0x51,0xc8,0x8b,0xa1,0x35,0x59,0x04,0x97,0xc1,0x44, + 0x53,0x5a,0x26,0x1d,0xe5,0x97,0xe1,0x29,0xd7,0xfa,0x69,0x52,0xa2,0x6d,0xa5,0x81, + 0x1b,0x55,0xad,0x49,0x09,0xb7,0xf9,0x50,0x88,0x1f,0x50,0xca,0x78,0xec,0xee,0xf2, + 0x60,0x5e,0x3b,0x44,0xdb,0x7c,0x7a,0xb3,0x0a,0xae,0xf7,0x05,0x14,0x03,0xa3,0xda, + 0x10,0x08,0x85,0xa8,0x83,0x0e,0x09,0x9a,0xe0,0x43,0x80,0x11,0xd3,0x74,0x10,0xf9, + 0x00,0xa6,0x96,0x99,0x1f,0x26,0x85,0xf9,0x02,0xbd,0x58,0x55,0x0e,0x38,0x42,0x4e, + 0x95,0x19,0x49,0xa0,0xf0,0x42,0x4e,0xb8,0x6d,0x41,0xf8,0x73,0x21,0xc5,0x2c,0xcb, + 0xdc,0x7f,0x53,0x4e,0xb4,0x6d,0x91,0xfe,0x79,0x75,0x62,0x47,0x5a,0x28,0x6c,0xcf, + 0x89,0x9a,0x91,0xf0,0x17,0xd4,0x9c,0x0e,0x7c,0x71,0x8b,0xc2,0x37,0xfa,0x14,0xae, + 0xb9,0xd6,0x8f,0x7d,0x3f,0x9c,0xca,0x5a,0x01,0xa3,0x29,0x0c,0xb7,0xa9,0x34,0x97, + 0x1c,0xa7,0x59,0xd5,0x65,0xd5,0xbd,0x1e,0x6e,0xb8,0x55,0x59,0xdc,0x76,0xb9,0x7e, + 0x63,0xa4,0xf0,0x01,0x5b,0x68,0x57,0xe6,0xb4,0xe5,0xe9,0x4d,0x11,0x63,0x83,0x52, + 0xc1,0x2f,0xd7,0x9b,0x23,0x9a,0x7b,0xbd,0x45,0x73,0x16,0x49,0x9f,0x87,0x1b,0xf8, + 0x44,0x4b,0xf8,0x5b,0x5e,0x48,0x8b,0xb2,0x09,0x0a,0xf1,0xef,0x49,0x2a,0xae,0xfe, + 0x42,0x5e,0x62,0xb8,0xd6,0x4f,0xae,0x74,0x0b,0x6f,0x8d,0x4e,0xdc,0x94,0x93,0x16, + 0x4a,0x73,0x6e,0x84,0x3c,0x7e,0xeb,0x9d,0x25,0xa5,0x4a,0xae,0xd4,0x88,0x47,0x4a, + 0x4a,0x73,0x32,0xf9,0x38,0xc0,0x8b,0x24,0xc5,0x34,0x74,0x2d,0xa2,0x14,0x81,0xc2, + 0x1b,0x49,0x60,0x85,0x8a,0xd4,0x08,0x5a,0x04,0xf0,0x54,0xa7,0x38,0x02,0x19,0xfd, + 0xf3,0xec,0x8d,0xec,0x16,0xfe,0xef,0xd1,0x29,0xa5,0xf9,0x37,0xb2,0x42,0x14,0xca, + 0x23,0x6a,0x0b,0x93,0xa4,0xbe,0xe8,0x44,0xad,0xf4,0xc6,0x4f,0xdd,0xc2,0x5f,0x8e, + 0x5e,0x5b,0x7a,0x95,0x31,0x2b,0x33,0x3f,0x37,0xe6,0xdc,0xdd,0x76,0xbb,0xfe,0x05, + 0x75,0xe2,0x73,0x39,0x77,0xf3,0xdb,0x71,0x3e,0x73,0x56,0xe6,0xde,0xdd,0xb6,0x28, + 0xfa,0x0f,0xa5,0x57,0x3d,0x37,0x01,0x4f,0x45,0xff,0x67,0xe9,0x44,0xb3,0xd0,0xb9, + 0x9f,0x1b,0x9a,0x50,0x09,0xfc,0x4e,0x9f,0x5b,0x9a,0xdf,0x2e,0xdf,0xcd,0xff,0x9b, + 0x3e,0x77,0x51,0xfe,0x73,0x0a,0x0d,0xfb,0x54,0x69,0xce,0x73,0x78,0x64,0x73,0xf4, + 0x0b,0xa5,0xf9,0x66,0xa1,0xf3,0x7e,0x6f,0xb8,0x31,0x67,0x16,0x9e,0xfd,0xc2,0xa2, + 0xdb,0x9e,0xa3,0x3f,0x14,0x2d,0x2a,0x9d,0xf8,0x9c,0x72,0x6d,0xe7,0x7d,0xd1,0x2f, + 0xd1,0xea,0xa6,0x53,0x9f,0x2e,0xcd,0x5a,0x3f,0x4c,0x8a,0xf2,0x48,0x18,0x95,0x4c, + 0xbb,0xa4,0x93,0xb6,0xc1,0xa7,0x96,0x96,0x11,0x3f,0x18,0x14,0x5a,0xfb,0x11,0x5c, + 0x21,0xb8,0xab,0xcb,0xac,0xb6,0x5c,0xe9,0x4e,0xbe,0xe8,0xce,0xcb,0x4a,0x73,0x56, + 0x92,0x10,0x4d,0x0b,0x11,0xfc,0x43,0x25,0x2b,0x73,0xca,0x78,0x29,0x1e,0x51,0x78, + 0x66,0xf8,0x0d,0xc6,0xb5,0xcb,0xa4,0xdb,0xe1,0x0b,0x50,0x62,0xae,0x20,0xe1,0x56, + 0xd0,0x70,0xa1,0x4a,0x0b,0xe0,0x0b,0x4c,0x41,0xb3,0x88,0x47,0x3e,0x05,0xee,0xfb, + 0xb9,0xa1,0x89,0x47,0x79,0x69,0x90,0xbe,0x3c,0x12,0x74,0xe6,0x41,0x81,0x96,0x4d, + 0xae,0x47,0x6b,0xc7,0xf5,0x43,0x1f,0xa5,0x7b,0x3d,0xdc,0xd0,0xd4,0xa9,0xe3,0xea, + 0x6a,0xc2,0x65,0x69,0x09,0x9e,0x42,0xbc,0x6d,0x71,0x44,0x6b,0x2f,0x21,0x81,0xa9, + 0x85,0x59,0xe3,0x73,0x8c,0xb6,0xd6,0xc0,0x6d,0xea,0x44,0x12,0xb4,0xd9,0xad,0xbe, + 0x89,0xcd,0x53,0x48,0xd7,0x95,0xf8,0x5a,0x8a,0x25,0x68,0x6b,0xd5,0x6f,0xf3,0x4d, + 0x34,0xb2,0xe6,0xa7,0x95,0xdf,0x16,0x9e,0xe8,0x53,0x9a,0xd2,0xc2,0x8a,0x66,0x14, + 0x5a,0xf4,0x42,0x35,0x27,0x7d,0x44,0xcd,0x31,0x32,0xdf,0x57,0x8e,0x6a,0xdc,0x05, + 0x5a,0x27,0x2a,0x99,0x08,0x09,0x8a,0x22,0x81,0x61,0x18,0x12,0x2e,0x25,0x09,0x17, + 0x0d,0xe9,0x42,0x5a,0x3d,0x99,0xfb,0x69,0xbc,0xb5,0xa9,0x82,0xb7,0xe9,0xfa,0xb4, + 0x58,0x53,0x3b,0x70,0xbe,0x15,0x6a,0x62,0x93,0x99,0xb2,0xba,0x33,0x50,0xf6,0xc5, + 0xd2,0x22,0x03,0x48,0x2d,0xa9,0xa5,0xe0,0xec,0xef,0x40,0x32,0x3e,0x1d,0xbd,0x7c, + 0x91,0x72,0x59,0x53,0x4e,0xfc,0x86,0xa8,0xb4,0x09,0x7e,0xd3,0xfc,0x7d,0xde,0x1c, + 0x9d,0xb5,0x48,0xfd,0x3c,0x2a,0xf7,0x1b,0x48,0xff,0x57,0xc3,0x44,0xd7,0xf3,0xae, + 0x30,0x1a,0xa3,0xda,0x51,0xa8,0x66,0xf7,0xe1,0x30,0x38,0x2a,0x57,0xcb,0x39,0xf8, + 0x7e,0xaf,0x53,0xd5,0x5c,0x28,0xc1,0xe5,0x8d,0x9f,0xce,0xa7,0x51,0xff,0x80,0xeb, + 0x57,0xb1,0x2c,0xcf,0xe7,0x69,0x36,0x5a,0x07,0x2b,0xc2,0x92,0x0f,0x9a,0x0d,0x6e, + 0x56,0x44,0x55,0x55,0x0d,0x28,0x31,0xae,0x93,0x3e,0xf9,0x0a,0x7d,0xda,0x99,0x5f, + 0x09,0x4c,0x81,0x7c,0x43,0x06,0x78,0xd9,0xb8,0x16,0xf2,0x41,0xbe,0x95,0xbf,0xcc, + 0x2b,0x20,0xcf,0x60,0xb7,0x40,0x1c,0xa6,0xf0,0x7c,0x60,0x46,0xd6,0xf8,0x8a,0xb6, + 0xeb,0xf8,0xcd,0x5f,0x2c,0x2e,0x51,0xfa,0xa4,0x59,0xfc,0xe6,0xd6,0xe2,0x49,0xca, + 0xdb,0x53,0xae,0x0b,0xe2,0xc2,0xdb,0xa8,0x6c,0xcf,0x29,0x53,0x16,0xb4,0xca,0x9a, + 0x7b,0xfd,0x40,0xf9,0x8a,0x25,0x6d,0x5f,0x5c,0xf2,0xf9,0xb5,0x13,0xcb,0x73,0x96, + 0x34,0x7e,0x51,0xff,0xfc,0xe6,0x89,0x0f,0xe5,0x2c,0x69,0x9b,0x1c,0xfe,0x7c,0xac, + 0x70,0xab,0xb4,0xa4,0xf7,0x8b,0xe1,0xcb,0xd6,0xe6,0x64,0xdf,0x8f,0xb8,0x8d,0x28, + 0x6c,0x04,0xbc,0x0d,0x8e,0xc2,0x26,0x98,0x03,0x97,0x03,0xbb,0x0d,0x06,0x95,0x6b, + 0x21,0x0f,0xef,0x47,0x73,0x8f,0xcf,0x5b,0x5c,0x25,0xf9,0x3a,0x9b,0xa5,0xc2,0x58, + 0xcb,0x5d,0x52,0xa9,0x82,0x42,0x67,0x4b,0x98,0x2c,0x9a,0xa4,0x99,0x2d,0x55,0x52, + 0x69,0x27,0xe9,0x0d,0xd7,0x78,0xe5,0x06,0x6d,0x56,0xcb,0x4d,0xb7,0x48,0x85,0x8d, + 0x37,0xb4,0x16,0xde,0x96,0x73,0x0b,0x4c,0x34,0x1a,0xb5,0xab,0x5a,0x94,0x1c,0x49, + 0x31,0x0c,0xad,0xd0,0x50,0x26,0x4a,0x13,0x0d,0xd7,0x78,0xb5,0xac,0x49,0x6d,0xc5, + 0x95,0x28,0x45,0x24,0x34,0x89,0xb1,0x89,0xba,0xa2,0x6e,0x61,0xc1,0xdb,0x3a,0x4a, + 0xca,0xb8,0x3a,0xeb,0x56,0x85,0x4e,0xad,0x70,0x8f,0xf7,0xdc,0xc9,0xe2,0xc6,0x76, + 0x6d,0x3a,0x78,0x24,0xc6,0x8d,0x04,0x04,0x4b,0x3c,0x85,0xac,0xcd,0x48,0x68,0x41, + 0x43,0x1c,0xd9,0xa1,0x85,0xdc,0x6f,0x0b,0x7c,0xcd,0x9f,0x83,0x97,0xfb,0xae,0xad, + 0x52,0x17,0xc8,0x28,0x98,0x65,0xf8,0x6d,0xb1,0xcf,0x49,0x1b,0xcd,0x89,0xe1,0xd2, + 0x05,0xb9,0x9f,0x83,0xdb,0xfa,0xaf,0x0d,0x97,0xba,0xaf,0x9f,0x37,0x81,0x8c,0xfe, + 0x17,0x02,0x39,0x07,0x73,0xee,0x01,0x84,0x01,0x15,0x13,0xfb,0xe5,0x7b,0xca,0x6e, + 0xef,0xfc,0x07,0xfd,0xf2,0x7e,0xef,0x3d,0xd2,0xe6,0xd8,0x3f,0x54,0x4c,0x34,0xdd, + 0xf3,0xaf,0x1a,0x07,0x8a,0xc2,0x9d,0xbe,0xc6,0x72,0x30,0x4c,0x2d,0xdc,0xe2,0x93, + 0x64,0xad,0x05,0x05,0x05,0x05,0x3c,0x52,0x44,0x82,0xfb,0x7e,0x1a,0x2e,0x2c,0xbc, + 0xf0,0xeb,0xf3,0x27,0x2f,0xfc,0x4e,0x08,0x17,0x4e,0x5e,0x38,0x77,0xb1,0x00,0xff, + 0x07,0xbf,0xfa,0x37,0x17,0xee,0xc5,0xeb,0xef,0xfd,0x1d,0x09,0x2f,0xbd,0x89,0x57, + 0x43,0x01,0x2f,0x9b,0x3c,0xf3,0xcf,0xa1,0xd7,0xfc,0x78,0x24,0xb9,0x7b,0x69,0xd6, + 0xfd,0x34,0x2c,0x3c,0x82,0xe3,0x8f,0xfc,0x4e,0x08,0x0d,0x74,0x1b,0x0d,0x34,0xbe, + 0xef,0xec,0xb9,0xd9,0x75,0x74,0xa4,0x6f,0xe0,0x43,0xf7,0xf8,0xf2,0xd2,0x9b,0x9f, + 0x2b,0xaa,0xef,0x5c,0xfb,0xdf,0xca,0xaf,0xbe,0xf9,0xf9,0x0d,0x0d,0x9d,0xeb,0xce, + 0x95,0x2f,0x8f,0x3c,0x57,0xbc,0xab,0x73,0xed,0x9d,0x78,0xea,0xf9,0x07,0xf6,0xa2, + 0xe0,0x1e,0x2f,0xb1,0xbb,0x8d,0xcd,0xda,0x04,0x25,0xaf,0x8f,0x84,0xd6,0x4f,0x97, + 0xe4,0x3d,0xcb,0x96,0x19,0x93,0x5a,0x27,0x94,0x48,0xcf,0x2a,0x77,0x93,0x70,0x79, + 0x9e,0x7b,0x3e,0x15,0x85,0x40,0xe0,0xff,0xd4,0x6e,0x78,0x36,0xe7,0x6e,0x09,0x15, + 0x35,0xe2,0xc3,0x1c,0xc4,0x93,0x78,0x44,0x20,0x46,0x5f,0xb4,0x19,0xf1,0xa1,0x6b, + 0x3c,0x43,0x6d,0x2c,0x40,0xe0,0x4a,0xd2,0xcf,0xa8,0x66,0x6d,0x01,0x84,0x80,0x86, + 0x00,0xf1,0xa1,0xfb,0x86,0xf4,0x3b,0x39,0x82,0x34,0x90,0x38,0xdc,0x09,0x42,0x40, + 0xd8,0x00,0xa4,0x36,0x25,0xae,0xdc,0x79,0x79,0x29,0xbb,0x51,0x93,0xdc,0xe3,0x55, + 0xe5,0x1e,0x69,0x12,0xff,0xb4,0x2e,0xf5,0xb7,0x90,0x30,0x41,0x2f,0xec,0x4f,0x1f, + 0x29,0x3c,0x48,0xc2,0x9a,0xe6,0x59,0x92,0xfb,0x7e,0x00,0x04,0x08,0x04,0x54,0xb3, + 0x51,0xfa,0x43,0x78,0xd9,0xf4,0x11,0xfa,0x43,0x0a,0x22,0x46,0x32,0xc5,0x99,0x5f, + 0xa9,0x32,0x55,0xca,0x83,0x26,0x43,0x8b,0x2b,0x15,0x28,0xb0,0xa8,0xb6,0x49,0x29, + 0xb7,0x8e,0x6c,0xa6,0x23,0x46,0x53,0x6b,0xd6,0xf7,0xf8,0x37,0xca,0x4d,0xbd,0xb8, + 0xa8,0x62,0x85,0xd3,0x95,0x9b,0xda,0x8a,0xc2,0x2d,0x3b,0xd2,0x82,0xb2,0x56,0xfa, + 0x1b,0xf8,0x0c,0x2f,0xd2,0xf1,0x94,0xeb,0xee,0xcd,0x10,0xcc,0x56,0x15,0x53,0x0a, + 0x43,0x0e,0xdc,0x42,0xf1,0x5a,0x02,0x41,0x9f,0x43,0x6b,0x83,0xc2,0x02,0xb8,0x92, + 0x5f,0x36,0x98,0x13,0x76,0x99,0x77,0x84,0x42,0xa8,0x21,0x72,0x50,0xad,0xa1,0x76, + 0x6a,0x41,0x4d,0xdc,0x68,0xe0,0xc9,0xc6,0xb6,0x42,0x14,0xb4,0xdb,0x94,0x4f,0xa9, + 0x85,0xc7,0x68,0x2f,0x1b,0xce,0x5c,0xdf,0x60,0x25,0x6a,0x27,0x94,0x41,0x69,0x69, + 0x80,0xa1,0x22,0x2b,0xb3,0xc0,0x0d,0x90,0x40,0xff,0x94,0x30,0x56,0x69,0xd6,0x78, + 0x88,0x16,0x96,0xc2,0x8d,0xa4,0xe8,0xa3,0x88,0x47,0x72,0x2d,0x81,0x8e,0xe0,0xfc, + 0x47,0xcb,0x36,0xa1,0xfe,0xd4,0xb8,0x33,0x5e,0x6b,0x34,0xd8,0x37,0xb5,0x4d,0x38, + 0x2c,0x2f,0xce,0x48,0x55,0xa1,0xc0,0x19,0x29,0x76,0x7a,0x83,0xec,0x2e,0x1d,0xdf, + 0x08,0x5c,0xde,0xee,0xdc,0xbf,0x81,0x78,0x89,0x40,0xe0,0x97,0x54,0x38,0xa0,0x54, + 0x09,0x41,0x3b,0xa0,0x84,0x57,0x93,0x50,0x7a,0x40,0x99,0x73,0xf0,0xf2,0xf0,0x8d, + 0xaa,0x6a,0x3a,0x78,0xcc,0x68,0xc4,0x05,0xa1,0x09,0x76,0xac,0x69,0xe0,0xd4,0x74, + 0xca,0x02,0x28,0xd2,0x91,0x32,0x81,0x18,0xf1,0x69,0xf0,0x94,0x83,0x1f,0x0c,0x7c, + 0xb8,0x30,0x17,0x6c,0xf5,0x03,0x96,0xa0,0x92,0x10,0xb3,0x8f,0x10,0xfe,0x0c,0x41, + 0x66,0x3d,0x58,0xf7,0x53,0x1a,0xfe,0xb4,0x0f,0xda,0x2d,0x01,0x0d,0xb1,0x82,0x0b, + 0x03,0x8f,0xac,0x3f,0xa0,0x44,0x7b,0x4b,0xf5,0x1b,0x7d,0x68,0xaf,0x9d,0xfb,0x91, + 0x04,0x3e,0x14,0x46,0x1c,0x84,0x59,0xb7,0x20,0x36,0x09,0xb8,0x7e,0x04,0x5e,0x55, + 0x5d,0xf6,0xa2,0x55,0x12,0x78,0x58,0x58,0xf3,0xb4,0x60,0x5d,0x1f,0x0d,0xbd,0x38, + 0x42,0x78,0x18,0x2f,0xa5,0x39,0xcf,0x6b,0x28,0xad,0x79,0x25,0xf8,0x62,0x35,0x4d, + 0x69,0x95,0x48,0x40,0x95,0x6c,0x09,0x80,0x02,0x08,0xec,0xc6,0x9c,0xf9,0x89,0x48, + 0xb9,0xd0,0xc8,0x35,0x5c,0xb7,0x7f,0x51,0x80,0x52,0x09,0x9c,0x78,0x62,0x44,0xa1, + 0xdd,0x8a,0xa1,0xb7,0xaa,0x62,0x67,0x14,0x29,0x4b,0x0b,0x74,0xa4,0xc4,0x12,0x5c, + 0xd5,0x25,0x68,0x7e,0x6e,0x94,0xd3,0x20,0xf0,0xf3,0x69,0x21,0xff,0xc6,0x6c,0xa1, + 0x6c,0xd1,0x55,0x2e,0xbc,0x91,0x73,0x23,0xa2,0xbb,0x49,0x08,0xd2,0xa4,0x03,0x25, + 0x96,0x50,0xf8,0x9c,0xf2,0x4d,0x6e,0x0b,0x6d,0x9b,0xa3,0xff,0xa0,0x16,0xba,0xe6, + 0x5f,0xba,0x11,0x96,0x21,0x08,0x9c,0x50,0x9a,0x7f,0x80,0xdd,0xcd,0x5f,0x2f,0x9b, + 0x5b,0x9a,0xf7,0x1c,0x2c,0xc3,0x61,0x13,0x54,0xe9,0x39,0x3c,0x32,0x49,0x9f,0x50, + 0x7a,0x79,0x66,0x7c,0xeb,0x0d,0x02,0x7f,0x12,0x1a,0x24,0x7c,0xb8,0x00,0x85,0x89, + 0xcf,0x49,0xff,0x03,0x8f,0x94,0x97,0x2e,0x7a,0x2e,0xe7,0x7f,0x90,0xfe,0x29,0x85, + 0xf6,0xcc,0xfb,0x42,0xd0,0x5b,0xc1,0x3f,0xa3,0xb3,0x48,0xce,0x06,0x14,0xfe,0x4e, + 0xbf,0x2c,0x22,0x80,0xe2,0x67,0x10,0x9f,0x03,0x1e,0x31,0xff,0x5b,0xf8,0x53,0x11, + 0x25,0xf3,0xbe,0x0c,0x5c,0xb7,0xa8,0x7f,0x68,0x53,0xf5,0x50,0x5a,0x90,0x56,0xda, + 0x47,0x50,0x68,0x2b,0x8d,0xde,0xb8,0xc9,0x8d,0x07,0x6e,0x88,0x2a,0xcb,0xa5,0xc9, + 0xf0,0x69,0x9e,0x93,0xea,0x5c,0x2e,0x15,0xa0,0xa0,0xa5,0x94,0x1a,0x75,0xb2,0xf4, + 0xe9,0xf6,0xc2,0x14,0x9e,0xf2,0xb0,0x26,0xae,0x99,0xae,0xf5,0x73,0x2b,0x2c,0xc6, + 0x4d,0x41,0x6e,0x44,0xdb,0x80,0x42,0x1e,0x0a,0x94,0x2d,0x23,0x8e,0x48,0xd6,0x11, + 0x16,0x71,0x5d,0xdf,0xc0,0xf5,0x63,0xe3,0x43,0x25,0x40,0xeb,0x27,0x28,0xd6,0x0f, + 0x59,0x65,0xc2,0x93,0xd6,0x29,0xee,0xfa,0xbe,0x9a,0x14,0x63,0xb5,0xa6,0x2b,0xbe, + 0x42,0xa6,0x18,0xbd,0x25,0x01,0x14,0x9a,0x95,0xd6,0x36,0x3c,0xa2,0x4a,0xac,0xc4, + 0x10,0x9f,0x4c,0xa1,0xe1,0x9a,0x1f,0x46,0xfb,0xdc,0x70,0x8e,0x2a,0x35,0x43,0x15, + 0x2f,0xd1,0x73,0x82,0x28,0xb4,0x9a,0x28,0xa8,0x64,0xef,0x4d,0x3a,0x05,0x19,0x7c, + 0x68,0xe0,0x07,0xd7,0xa4,0x95,0x72,0x54,0x3d,0xaa,0xa1,0x81,0xb6,0x82,0xd6,0xa3, + 0xd2,0xa4,0xa1,0x92,0x90,0x0a,0x71,0xa0,0x84,0x88,0xd1,0xfa,0x4a,0x9c,0xfb,0x69, + 0x82,0x38,0x0f,0x23,0x08,0x64,0x5b,0x35,0x8e,0x08,0x4c,0x55,0x3d,0x00,0x31,0xaa, + 0x84,0xab,0x32,0xc6,0x62,0x7c,0x87,0xae,0x6e,0x32,0x34,0xd7,0xf7,0x95,0x9b,0xd1, + 0x36,0x39,0x24,0x14,0x5a,0xdb,0x76,0x4b,0x98,0x5d,0xaa,0x7c,0xc5,0xad,0x9f,0x71, + 0x3c,0x5b,0x0c,0x3f,0x02,0x66,0xa0,0xfe,0x59,0x0c,0x3f,0x41,0xe1,0xf2,0x78,0xfa, + 0x88,0x1a,0x87,0xc5,0xd7,0xfd,0x44,0x99,0x60,0x94,0xba,0xc6,0xdf,0x10,0xad,0xa8, + 0xc9,0x2b,0x80,0xbb,0x38,0x24,0xb6,0xd7,0x48,0x1e,0xb8,0xab,0x93,0xde,0x57,0x21, + 0x1d,0x29,0x4d,0x40,0x8d,0x7a,0x05,0xbb,0x71,0x05,0x64,0xbe,0xf7,0x56,0x7c,0xbc, + 0x59,0xa6,0x6f,0x19,0x53,0x60,0x15,0xf5,0x6a,0x6d,0x45,0xe1,0x59,0x2a,0x5a,0xd1, + 0xca,0x4a,0xa0,0x03,0x05,0x0f,0x09,0xee,0xf5,0xa3,0x10,0x7e,0x33,0xe4,0x56,0xf8, + 0x3e,0x0a,0x9f,0x8d,0x22,0x6c,0xfb,0x77,0x7e,0x6d,0x4b,0xbe,0xc1,0x5a,0x61,0xa3, + 0x76,0xed,0xc1,0xfc,0xd6,0xe6,0x3b,0xb4,0xf6,0xcc,0xf7,0x8e,0xef,0x6b,0x71,0x6f, + 0x29,0x6e,0x42,0xa5,0x07,0x50,0xdb,0x5c,0xbe,0x0c,0x85,0x55,0x9d,0xe2,0xc8,0xed, + 0x85,0x1d,0x0a,0x2d,0xbc,0x1b,0x27,0x49,0xd9,0xfa,0x67,0x16,0x6a,0x6e,0x86,0x18, + 0xdd,0xde,0xa8,0xc6,0x48,0x97,0xb7,0xa2,0x1a,0xec,0x84,0x00,0xf8,0xe2,0x32,0xea, + 0x67,0x07,0xd1,0x18,0x52,0xa4,0xa5,0x5a,0x2a,0x45,0x34,0x58,0xb8,0x49,0x89,0x16, + 0x5e,0x8e,0x82,0xc4,0x17,0x7f,0x85,0x8e,0x44,0x0b,0x63,0x4a,0xb4,0xd4,0x47,0x88, + 0xd1,0x3d,0x3f,0x46,0x8b,0x56,0x58,0x82,0x68,0xb0,0xd0,0x68,0x69,0xb5,0x84,0x96, + 0x96,0xd6,0xc6,0x12,0x5f,0x4e,0xa1,0x84,0x47,0x94,0x1c,0x8f,0x24,0xb7,0x19,0x90, + 0x59,0x3f,0xb8,0x00,0x41,0xac,0x44,0x03,0x77,0x07,0x25,0x6b,0x14,0x04,0x8a,0x70, + 0x2b,0xad,0x4d,0xe1,0x3b,0x29,0x2d,0x11,0xa7,0x32,0xfb,0xbb,0x34,0x2c,0x6c,0x0d, + 0x2a,0x24,0xc0,0xf6,0xb4,0x60,0x6c,0x6f,0x9d,0x66,0x1d,0x49,0x6a,0xd3,0x14,0x70, + 0xad,0xe7,0xcf,0xca,0x9f,0x33,0x5e,0x1e,0xbc,0x76,0x4e,0x69,0x3e,0x0a,0x9d,0x28, + 0xe4,0x7d,0x96,0x7d,0xce,0xe8,0x7b,0xf9,0xda,0x6b,0xf3,0x3f,0xdb,0xf6,0x39,0x43, + 0x19,0x2c,0x9b,0xb3,0xc9,0x90,0x32,0xf3,0x13,0x51,0xee,0x01,0xb4,0xfe,0x60,0xc3, + 0x00,0xc8,0xe9,0x47,0xa0,0xb8,0x88,0xf0,0x80,0xb9,0x72,0x99,0x34,0xa9,0xed,0x2b, + 0x7a,0x96,0x7d,0xb7,0x60,0x61,0x1a,0x0d,0x6a,0x08,0x14,0xa5,0x62,0xcd,0x38,0xa0, + 0xcd,0xea,0xf4,0xdd,0x92,0x06,0x8a,0x0b,0xca,0x5c,0xc3,0xe1,0x3f,0x80,0x85,0xff, + 0x57,0xf0,0x21,0x81,0xc0,0x5f,0xbf,0x8f,0x20,0xb0,0xfe,0xcd,0xf9,0x73,0x7f,0xfd, + 0xfe,0xc9,0xdd,0xff,0x8c,0xf8,0xf0,0xfc,0x33,0xef,0x9f,0x3c,0xf3,0xcf,0x97,0xbc, + 0xbe,0x00,0x81,0x1f,0x21,0x08,0x6c,0x68,0x58,0x80,0xc2,0xc9,0x01,0x81,0x0f,0x8b, + 0x3f,0x3a,0x79,0xf6,0xd2,0xf7,0x73,0x7d,0xe9,0xc2,0xe7,0x7f,0x4d,0x68,0xb0,0xe1, + 0xea,0xc8,0xf3,0x0f,0x7c,0xd8,0xb9,0xf6,0x5b,0xe5,0xf7,0x2e,0xbc,0xf0,0xc0,0xae, + 0xce,0xb3,0x77,0x5e,0x3f,0x39,0x72,0xbe,0x68,0xee,0x38,0x7c,0xc8,0x56,0x85,0xb7, + 0x40,0xf0,0x1b,0x1e,0x2a,0xa7,0xb2,0x25,0x16,0xac,0xf2,0x68,0x07,0x56,0x06,0x13, + 0x0b,0x7c,0x77,0x7b,0xb4,0xa6,0x4e,0xc0,0x53,0x86,0x47,0x73,0x8f,0xb7,0xed,0x89, + 0xa6,0xe2,0xfb,0x6c,0xe1,0xcd,0xba,0x16,0xcb,0x99,0x0e,0x66,0x5b,0xa3,0xde,0xda, + 0x2f,0x8c,0x97,0x01,0x59,0xe3,0xa1,0x53,0x40,0x11,0xa6,0xc1,0x0d,0x30,0x2b,0xa6, + 0x34,0xe5,0x6a,0xbd,0x1d,0xe1,0x32,0x5f,0xa8,0x49,0x2a,0x31,0x9d,0x53,0xee,0xdf, + 0x84,0x30,0x5e,0xe4,0x1b,0xba,0x06,0x39,0x3e,0xd4,0x11,0x8d,0xd0,0x6a,0xe0,0x65, + 0x3b,0x94,0xbb,0x71,0x3f,0x78,0xc9,0xeb,0x73,0xfb,0x3b,0xe9,0x40,0x2d,0xa4,0x52, + 0x6d,0x14,0xd4,0x42,0xed,0x93,0x80,0xa9,0xa6,0x73,0xca,0xfd,0xbc,0xae,0x7f,0xc1, + 0x69,0x27,0x85,0x08,0x56,0x23,0x5f,0xa2,0xea,0x6b,0xb7,0x4f,0x39,0xee,0x5e,0x92, + 0x33,0xa3,0x59,0x38,0xe2,0x63,0x92,0x11,0x63,0x01,0xfd,0xb3,0xf7,0x41,0xc0,0x67, + 0x5a,0x2d,0xab,0x02,0xae,0xbf,0xa0,0x3a,0xbe,0x25,0x21,0x88,0x3b,0x88,0x21,0x30, + 0x6b,0xc4,0xaf,0x59,0x8d,0xd9,0xa7,0xdc,0xe3,0x3d,0xab,0xaa,0xb6,0xc0,0x0e,0x63, + 0xba,0xe6,0xe9,0x2c,0xd8,0x02,0x3b,0x0d,0x6f,0x89,0xe7,0xf9,0x82,0x2d,0xbe,0x1d, + 0xd2,0xf4,0xd2,0x35,0x9d,0x2c,0x01,0x3b,0x60,0xba,0xe6,0x7e,0x02,0x67,0xfe,0x6b, + 0x2c,0x01,0xb4,0xc4,0x0d,0xa4,0xb3,0x8a,0xf3,0x4a,0x22,0x78,0xa4,0x93,0xdf,0xa9, + 0xbb,0xf0,0xaa,0x6a,0xcd,0xbf,0x42,0x93,0x4c,0x42,0x9e,0x21,0xdf,0x66,0x4c,0x80, + 0xb2,0xcf,0xaa,0xc5,0xd2,0x22,0x8e,0x47,0x3a,0xd5,0x3b,0x99,0x96,0xa9,0xd7,0xaa, + 0x6a,0x34,0xff,0x03,0xf0,0x0d,0x98,0x64,0x4e,0x98,0x83,0x02,0x6a,0xfc,0x3b,0x11, + 0x67,0xe4,0x29,0xb7,0x36,0x4e,0xa2,0x17,0x21,0x4e,0x65,0xf2,0x8f,0xf0,0xfa,0xab, + 0xc2,0xe2,0x25,0x4e,0x4a,0x75,0x2a,0x65,0xfd,0xbe,0x6f,0xc8,0xda,0x5d,0xcf,0x6a, + 0x85,0x92,0x4a,0x09,0xc7,0x78,0xfd,0x01,0xf5,0x1b,0x2c,0xeb,0xfe,0x51,0xc1,0x8a, + 0xd9,0xd1,0x8a,0x40,0xe5,0x94,0x47,0x01,0xe6,0xa7,0x27,0xb5,0x36,0xe9,0x65,0xbd, + 0x4a,0x13,0x58,0x05,0x7d,0xb2,0xde,0x17,0xa4,0xf5,0xa0,0x46,0xee,0xb9,0x88,0x8a, + 0x3b,0x79,0xfe,0xac,0xae,0xc7,0x94,0xa2,0x26,0xe0,0xdc,0x5a,0x3f,0xee,0xd1,0x1a, + 0x97,0x2d,0xf0,0xea,0x33,0xf1,0xff,0xf5,0xc3,0xec,0x1c,0x40,0x70,0x29,0x1c,0x7d, + 0xaa,0x35,0x2d,0xb3,0xf1,0xff,0x32,0xf9,0xa7,0xee,0x7f,0x09,0x86,0x18,0xa1,0xa5, + 0xcb,0xbd,0xc5,0xf9,0xc5,0x83,0xea,0xea,0xdc,0xe3,0xb9,0x40,0xee,0x68,0xf6,0x50, + 0x08,0x6b,0x83,0xce,0x78,0xbf,0xff,0xe2,0x7f,0x89,0x6b,0xb8,0xb7,0xc3,0xbc,0x1c, + 0xc7,0xc8,0x0f,0xbf,0xba,0x08,0xa6,0xf4,0x2c,0x38,0x64,0x5e,0x62,0x54,0xe6,0xc7, + 0xda,0xdb,0xdb,0xc5,0x15,0x03,0x1b,0x7f,0x1a,0x80,0xca,0x39,0x77,0xbd,0x7b,0x89, + 0xfb,0x71,0xfd,0x8a,0xca,0x8a,0x4a,0xc5,0xa3,0xb3,0x22,0xa6,0x84,0x3b,0xd7,0x17, + 0x2a,0x97,0x1c,0xd6,0x70,0xe1,0xc2,0x05,0xf3,0x7f,0x21,0xfc,0x2f,0xc6,0x9f,0xbb, + 0xf0,0xf4,0x7f,0x65,0xfc,0xbc,0x0b,0x17,0x8e,0xff,0x57,0xc6,0x5f,0xfd,0x9f,0xbc, + 0x9f,0x0f,0xd2,0xc2,0xcc,0xff,0xe2,0xfd,0x5f,0x7d,0xc4,0x39,0xf2,0xc1,0xc5,0xe3, + 0x99,0xad,0xf4,0xfe,0x03,0xc1,0x3d,0xde,0xa5,0x0f,0xdd,0x02,0x64,0x8e,0xfc,0x25, + 0x7d,0xf8,0x1f,0x08,0xee,0x9f,0xa3,0xf4,0xfe,0x03,0xc1,0xfd,0xcb,0xe8,0xab,0x4b, + 0x0b,0xb3,0xff,0x03,0x7d,0xf8,0x17,0x04,0xd7,0xd3,0x5a,0x87,0x48,0xe9,0x01,0x69, + 0x3f,0x95,0x12,0xa0,0xac,0x23,0xcc,0x12,0xe8,0x9f,0xfd,0x45,0x7d,0xf8,0x17,0x84, + 0x2c,0x7d,0xd8,0xc9,0x50,0x1f,0x7e,0x83,0xf4,0x21,0x13,0x8a,0x71,0xd2,0x21,0xd4, + 0x90,0x03,0x42,0x43,0xda,0xc2,0x25,0xf5,0xe1,0x7f,0x20,0x64,0xdd,0xff,0x7f,0x62, + 0xfe,0x5d,0xf7,0x23,0x26,0x39,0xad,0x0f,0xc3,0x97,0x14,0x8c,0x71,0xfa,0xf0,0xbf, + 0x74,0xfd,0xff,0xea,0xfc,0xff,0x27,0xde,0x6f,0xb6,0xbd,0xcb,0xf2,0x5d,0xfc,0xc5, + 0xdf,0xa5,0xf4,0xe1,0x7f,0xea,0xe7,0xd2,0x87,0xff,0xc1,0xef,0x92,0xfa,0xf0,0xff, + 0x23,0xbf,0xff,0x0b,0xfa,0xf0,0xff,0xd7,0xe3,0xff,0x6b,0xbf,0x30,0xe8,0x12,0x13, + 0xff,0xdd,0xec,0xfb,0x3f,0xbb,0xd2,0x5f,0x7f,0x7f,0xfd,0xfd,0xf5,0xf7,0xd7,0xdf, + 0x5f,0x7f,0x7f,0xfd,0xfd,0xf5,0xf7,0xd7,0xdf,0x5f,0x7f,0x7f,0xfd,0xfd,0xf5,0xf7, + 0xff,0xe7,0x9f,0xd8,0x3b,0x30,0xb1,0x77,0x70,0x1f,0xce,0xa9,0xb9,0xe3,0xef,0x8c, + 0x86,0xfa,0xef,0xfc,0xdd,0x27,0xf4,0x67,0x83,0xcf,0x43,0xc8,0x28,0x6f,0x81,0x12, + 0xf3,0x93,0xb9,0xbe,0xe2,0x59,0xf2,0x23,0xee,0x9d,0xb8,0x3f,0xf2,0xc9,0x5c,0x1e, + 0x1a,0x8e,0xd0,0xfd,0x1b,0xd0,0x60,0x7e,0x32,0xd7,0x57,0xf4,0x8d,0x5b,0xcc,0x2b, + 0x5e,0xbe,0x2f,0xf6,0xc9,0x5c,0x1e,0xc2,0x47,0xc2,0x23,0x46,0xf9,0x32,0x33,0x6c, + 0x7e,0x32,0xd7,0xcf,0x9f,0xfb,0xcf,0x2b,0xcc,0x49,0xff,0xf6,0xa5,0x85,0x9f,0xcc, + 0xe5,0x71,0xfe,0xad,0xfb,0xff,0xa4,0xe6,0xdf,0x77,0xcd,0x66,0x0e,0x75,0x9f,0x4a, + 0x7c,0x72,0xf3,0xef,0xc7,0xf5,0xb3,0x10,0x3e,0xa9,0xf9,0x2f,0x98,0xda,0x33,0x0a, + 0x57,0xfe,0xed,0x63,0x9f,0xf9,0x64,0x2e,0x8f,0xf3,0x6f,0xdd,0xff,0x27,0xb6,0xfe, + 0x2b,0x27,0x3e,0x6a,0x78,0xbf,0xb1,0x51,0xfd,0x5f,0x0f,0xfd,0xdf,0xfa,0x85,0x8f, + 0x34,0xe0,0xfa,0xf9,0xde,0x27,0xb7,0xfe,0x35,0xa9,0x1a,0xa6,0xe4,0x4d,0xfb,0xe4, + 0xd6,0xbf,0x75,0xff,0x9f,0xd4,0xfc,0xe7,0x97,0xb5,0xdc,0x08,0x55,0x27,0xa7,0x7e, + 0x52,0xeb,0x27,0x7c,0xc1,0x24,0xfd,0x19,0x1e,0x35,0x3f,0x99,0xeb,0x2b,0xea,0xdd, + 0xdf,0x37,0xab,0x77,0x6f,0xfc,0xc4,0xf4,0x7f,0xfa,0xfe,0xff,0x4f,0x5d,0x77,0x7f, + 0xe9,0xa7,0x94,0x6f,0xfc,0x57,0xb3,0xfc,0x53,0x1b,0x3e,0x31,0xfd,0x73,0x61,0x94, + 0xf4,0xe7,0xe8,0x27,0x35,0xff,0xfe,0xfa,0xdf,0x7f,0x60,0x5e,0xfb,0xea,0x17,0x8e, + 0x7c,0x32,0x97,0xc7,0xf9,0xb7,0xee,0xff,0x13,0x9b,0xff,0xfa,0xb5,0x3f,0xe5,0xb3, + 0x3f,0xb5,0x33,0xef,0x93,0xb9,0x3c,0xce,0xff,0x11,0xd2,0x9f,0x9f,0xd8,0xfa,0xcf, + 0x9d,0xfc,0xaf,0x5f,0xe5,0x53,0x7f,0xf9,0x5a,0xcb,0xff,0x7a,0xe8,0xff,0xd6,0xaf, + 0x21,0x7d,0xff,0x9f,0xd8,0xfc,0x4f,0xf9,0xdb,0xc7,0x41,0x9f,0xf8,0x93,0x4f,0x4e, + 0xff,0x5c,0x20,0xfd,0xf9,0xc9,0xad,0xff,0x2b,0x72,0xca,0x8c,0xfa,0x9d,0xf9,0x2f, + 0x7c,0x32,0x97,0xa7,0xa8,0x81,0xb8,0xff,0xff,0xab,0xf3,0x1f,0x06,0x0a,0x6d,0xde, + 0x25,0x85,0x41,0x70,0x9d,0xe4,0x30,0x18,0xff,0xe5,0x78,0x42,0xfa,0xdf,0xe6,0x84, + 0x21,0x21,0x65,0xae,0x79,0xec,0x8b,0xe3,0xc7,0xfd,0xbf,0xcd,0x20,0xf7,0xae,0x58, + 0x11,0x01,0x00, diff --git a/board/esd/apc405/logo_640_480_24bpp.c b/board/esd/apc405/logo_640_480_24bpp.c new file mode 100644 index 0000000..c52a430 --- /dev/null +++ b/board/esd/apc405/logo_640_480_24bpp.c @@ -0,0 +1,235 @@ + 0x1f,0x8b,0x08,0x08,0x85,0xd1,0x0f,0x40,0x00,0x03,0x61,0x62,0x67,0x5f,0x6c,0x6f, + 0x67,0x6f,0x5f,0x36,0x34,0x30,0x5f,0x34,0x38,0x30,0x2e,0x62,0x6d,0x70,0x00,0xed, + 0xd9,0xcb,0x91,0x25,0x3b,0x15,0x05,0xd0,0x02,0x03,0x08,0x86,0x98,0x80,0x05,0x18, + 0xc0,0x1c,0x9f,0x30,0x05,0x53,0x18,0x60,0x08,0x9e,0x14,0x8f,0xe6,0x17,0x74,0xd5, + 0xad,0xca,0x94,0xce,0x2f,0x33,0xd7,0x8a,0x7c,0x13,0x78,0x71,0xb4,0x25,0xdd,0xd6, + 0x8e,0x86,0x3f,0xfe,0xe9,0x0f,0xbf,0xfd,0xcd,0xdb,0x3f,0xfd,0xe1,0x97,0x7f,0x7e, + 0xff,0xcb,0x3f,0x7f,0xfe,0xf5,0xdb,0xdb,0xdf,0x7f,0xf5,0xf6,0xf6,0xab,0xb7,0xdf, + 0xfd,0xf8,0xcf,0xdf,0x7e,0xf9,0xef,0xff,0xf6,0xcb,0xbf,0xf2,0xb7,0x7f,0xfd,0x6b, + 0x3f,0xfc,0xf9,0x2f,0x7f,0xf9,0x2b,0x00,0x50,0xeb,0x0d,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x62,0xbc,0xbf,0xf8,0x00,0x80,0x35,0xaf,0xba,0x35,0xf0, + 0x03,0x80,0x67,0x2a,0x28,0x59,0xed,0x0c,0x00,0x6f,0xdd,0xad,0xaa,0x94,0x01,0x78, + 0x82,0xf6,0xc6,0xd4,0xc8,0x00,0x3c,0xca,0x25,0x4a,0x70,0x48,0x0c,0x00,0xd8,0x34, + 0xad,0x61,0x5b,0x76,0x04,0x00,0x35,0xee,0x57,0xbb,0x9f,0xba,0x7a,0x7e,0x00,0x6e, + 0xe3,0xf6,0x9d,0xfb,0xb5,0x5b,0x6e,0x0a,0x80,0xc9,0x1e,0xde,0xbc,0x1f,0x3d,0x64, + 0x9b,0x00,0xb4,0x50,0xb8,0x07,0x3d,0x7c,0xfb,0x00,0x84,0xf0,0x57,0xdd,0x05,0x4e, + 0x03,0x80,0x1d,0x9a,0x77,0x93,0x93,0x01,0xe0,0x2c,0xe5,0x1b,0xcb,0x11,0x01,0xf0, + 0x35,0xb5,0x9b,0xca,0xa1,0x01,0xf0,0x13,0x7f,0xe7,0x2d,0xe6,0x00,0x01,0xd0,0xbc, + 0x5d,0x1c,0x26,0xc0,0x63,0x29,0xdf,0x5e,0x4e,0x15,0xe0,0x81,0x34,0xef,0x10,0x4e, + 0x18,0xe0,0x39,0x34,0xef,0x34,0x4e,0x1b,0xe0,0xde,0xfc,0x6f,0xce,0xf3,0x39,0x76, + 0x80,0xfb,0x51,0xbe,0x57,0xe1,0xfc,0x01,0x6e,0x43,0xf9,0x5e,0x8b,0x5b,0x00,0xb8, + 0x01,0xcd,0x0b,0x00,0xc5,0xfc,0xcd,0x17,0x00,0x8a,0x29,0x5f,0x00,0x28,0xa6,0x7c, + 0x81,0x73,0xde,0x3f,0xe8,0x4e,0x04,0x97,0xa3,0x79,0x81,0xa3,0x3e,0xd6,0xee,0xa7, + 0xba,0x63,0xc2,0x25,0x3c,0xa7,0x7f,0x43,0xfe,0x9a,0x7f,0xbf,0x63,0xb9,0xb3,0x83, + 0x65,0xa1,0x3b,0x0e,0xda,0x39,0x4c,0xb7,0x00,0x1f,0xa4,0x16,0xcd,0xb4,0xca,0x1b, + 0x15,0xe6,0xa2,0x09,0xaf,0x64,0xa1,0x2f,0x8e,0xbf,0xfc,0x6b,0xc3,0xdf,0x37,0x2a, + 0x69,0x73,0xb9,0x96,0xc3,0xfc,0x6f,0x80,0xae,0xd8,0x30,0x55,0xf6,0x1b,0x5e,0xd9, + 0x26,0x47,0xfe,0xc0,0x8e,0x0a,0x73,0xd1,0x84,0x57,0xb2,0xd3,0x17,0x49,0xc3,0xdf, + 0xcb,0xfb,0xf7,0xe3,0xba,0x35,0xc7,0xf8,0xd3,0xd2,0x65,0x69,0xe1,0x0a,0x6e,0xd6, + 0x77,0xd3,0xf2,0x74,0x5d,0x4a,0x76,0xc2,0x2b,0x59,0x2e,0x8b,0xbc,0xe1,0xef,0x7d, + 0xfd,0xfb,0xbe,0x54,0x6a,0xf5,0x21,0x97,0xa3,0xc2,0x75,0xdc,0xac,0xef,0x0e,0xfe, + 0x81,0x1d,0x15,0xa6,0xfd,0xd0,0x7e,0x5a,0xf7,0x6e,0x52,0x5f,0xfe,0xfd,0x66,0x59, + 0x9e,0xb0,0x29,0xfb,0x00,0x8b,0x43,0xc2,0x05,0x15,0x54,0x4c,0x65,0x95,0x0c,0x8c, + 0xd4,0x75,0x2f,0x6b,0x09,0x77,0x32,0xcf,0x95,0xf7,0xf2,0xef,0x37,0xcb,0xf2,0x84, + 0x4d,0xd9,0x1b,0xac,0x0c,0x09,0x17,0x54,0x56,0x2e,0x95,0x6d,0x72,0x24,0xd5,0xa8, + 0x30,0xa3,0x12,0x86,0x84,0x1f,0x27,0xef,0xf1,0xdf,0x9f,0xbc,0x36,0x21,0x4a,0xd2, + 0x06,0xcb,0xe2,0xc1,0x65,0x95,0x35,0x4b,0x65,0x9b,0x1c,0x09,0x36,0x2a,0x4c,0x7b, + 0xc8,0x6f,0x17,0xbd,0xbc,0xbc,0xc7,0x7f,0x7f,0xf2,0xda,0x84,0x40,0xe1,0xbb,0xab, + 0xc9,0x06,0x57,0x56,0xd9,0x2c,0x95,0x7d,0x77,0x24,0xd8,0xa8,0x30,0xd3,0x42,0xc6, + 0xee,0x62,0x84,0xbc,0xc7,0x7f,0x7f,0xf2,0xda,0x84,0x40,0xe1,0xbb,0xab,0xc9,0x06, + 0x57,0x56,0x59,0x2b,0x95,0x55,0x72,0x30,0xde,0x9c,0x24,0xed,0x09,0xdf,0x8f,0xad, + 0x7b,0x61,0x79,0x8f,0xff,0xfe,0xe4,0xb5,0x09,0xb1,0x62,0x77,0x57,0x10,0x0c,0x2e, + 0xae,0xb2,0x56,0x2a,0xab,0xe4,0x60,0xbc,0x39,0x49,0xda,0x13,0xbe,0x1f,0x5e,0xf7, + 0xc2,0x92,0x1e,0xff,0xfd,0x5a,0x59,0x9b,0x10,0x2b,0x70,0x6b,0xb1,0x02,0x2e,0x1e, + 0x26,0x2a,0xee,0x94,0xca,0x36,0x39,0x92,0x70,0x54,0x98,0x69,0x09,0xc3,0xf7,0xd2, + 0x2f,0xe9,0xf1,0xdf,0x1f,0xbb,0x30,0x21,0x5c,0xc8,0xbe,0x32,0x04,0x5c,0x3c,0x8c, + 0x53,0x5f,0x28,0x95,0x6d,0x72,0x24,0xe1,0xa8,0x30,0xed,0x21,0x4f,0xad,0x7b,0x49, + 0x19,0x8f,0x7f,0x48,0xa7,0xac,0x0d,0xc9,0x30,0x30,0x55,0xe4,0x2f,0x00,0xa6,0xa8, + 0x2f,0x94,0xca,0xbe,0x3b,0x92,0x70,0x54,0x98,0x69,0x21,0xb3,0xf7,0xd5,0xa0,0xbb, + 0x49,0xfe,0xe7,0x12,0xc1,0xba,0xb3,0xfc,0x5b,0xe1,0x0f,0x04,0xca,0xd4,0x17,0x4a, + 0x65,0x95,0x1c,0x0c,0x39,0x27,0x49,0x7b,0xc2,0x8f,0x21,0xb3,0xb7,0x56,0xad,0xbb, + 0x49,0xfe,0x27,0x24,0x58,0xc6,0x06,0xa3,0xa6,0x05,0x66,0x0b,0xfc,0x01,0xc0,0x18, + 0xf5,0x85,0x52,0x59,0x25,0x07,0x43,0xce,0x49,0xd2,0x9e,0xf0,0x55,0xc8,0xd4,0xdd, + 0x95,0xda,0x29,0x94,0x58,0x21,0xc1,0x32,0xf6,0x18,0x32,0x2a,0xf6,0xfc,0xf7,0xef, + 0x1d,0xe6,0xb9,0x7d,0x9b,0x1c,0xc9,0x39,0x27,0x49,0x7b,0xc2,0x2f,0x42,0xa6,0x6e, + 0xb0,0xd4,0x72,0xa7,0x04,0x8a,0x4a,0x95,0xb1,0xc7,0x90,0x39,0xb1,0xc1,0x76,0xae, + 0x1b,0xa6,0xba,0x7d,0x9b,0x1c,0xc9,0x39,0x2a,0xcc,0xd8,0x84,0xd9,0xbf,0x8a,0x3a, + 0xcb,0x9d,0x12,0x28,0x2a,0x55,0xc6,0x1e,0x43,0xe6,0xc4,0x06,0xdb,0xb9,0x6e,0x98, + 0xaa,0xbe,0x4a,0x36,0x17,0xcd,0x88,0x3a,0x27,0xc9,0x84,0x84,0x5f,0x87,0x4c,0xfd, + 0x61,0x14,0x59,0xee,0x94,0x40,0x51,0xa9,0x32,0xb6,0x19,0x3e,0x24,0x75,0x9b,0x70, + 0x59,0xc5,0x3d,0xb2,0xb9,0x68,0x5e,0xda,0x39,0x49,0x26,0x9c,0xd8,0x7e,0x98,0xd1, + 0x96,0x3b,0x25,0x50,0x54,0xaa,0x8c,0x6d,0x86,0x0f,0x49,0xdd,0x26,0x5c,0x56,0x71, + 0x8f,0x6c,0x2e,0x9a,0x97,0x76,0x4e,0x92,0xf6,0x84,0x51,0xc7,0x35,0xd7,0x72,0xa7, + 0x04,0x8a,0x4a,0x95,0xb1,0xcd,0xf0,0x21,0xa9,0xdb,0x84,0xcb,0xaa,0xef,0x91,0xcd, + 0x75,0x1b,0x0b,0xa5,0x2c,0xcc,0xfc,0x84,0x35,0x3f,0x92,0x44,0xcb,0xb5,0x12,0x25, + 0x2a,0x52,0xc6,0x36,0x43,0x0e,0x2a,0x2f,0x12,0xdc,0x45,0x71,0x89,0xec,0xaf,0xdb, + 0x5b,0x28,0x35,0x61,0xae,0x12,0xb2,0xe0,0x77,0x92,0x65,0xb9,0x56,0x42,0x04,0x46, + 0xca,0xd8,0x66,0xc8,0x41,0xe5,0x45,0x82,0xbb,0xa8,0x2f,0x91,0xcd,0x75,0x93,0x02, + 0xcf,0x49,0x72,0xad,0x90,0x05,0x3f,0x95,0x14,0xcb,0xb5,0x12,0x22,0x30,0x52,0xc6, + 0x36,0x43,0x0e,0x2a,0x2f,0x12,0xdc,0x45,0x7d,0x89,0x6c,0xae,0x9b,0x17,0x78,0x4e, + 0x92,0xf6,0x84,0xa7,0x42,0x16,0xfc,0x5a,0xe2,0x2d,0xd7,0x4a,0x88,0xc0,0x48,0x19, + 0xdb,0x0c,0x39,0xa8,0xbc,0x48,0x70,0x17,0xf5,0x25,0xb2,0xb9,0x6e,0x5e,0xe0,0x51, + 0x61,0x2e,0x94,0xb0,0xe6,0x07,0x13,0x6c,0xb9,0x56,0x42,0x04,0x46,0xca,0xd8,0x66, + 0xc8,0x41,0xe5,0x45,0x82,0x1b,0xa9,0x6c,0x90,0xfd,0x75,0xf3,0x0a,0x65,0x54,0x98, + 0x6b,0x25,0x2c,0xfb,0xcd,0x84,0x59,0xae,0x95,0x10,0x81,0x91,0x32,0xf6,0x18,0x3e, + 0x24,0x75,0x9b,0x70,0x65,0x95,0x0d,0xb2,0xbf,0x6e,0x5e,0xa1,0x8c,0x0a,0x73,0xb9, + 0x84,0x65,0x3f,0x9b,0x30,0xcb,0xcd,0xb2,0x29,0x36,0x4f,0xc6,0x06,0xc3,0x87,0xa4, + 0x6e,0x13,0xae,0xac,0xb2,0x41,0xf6,0xd7,0xcd,0xeb,0x94,0x39,0x49,0xae,0x98,0xb0, + 0xf2,0x97,0x13,0x23,0xa4,0x02,0x02,0xab,0x64,0x61,0xd4,0x17,0xd3,0x96,0x07,0xbe, + 0x27,0xf4,0xef,0xf2,0x90,0x4f,0xa7,0xc1,0x8d,0x54,0x36,0xc8,0xfe,0xba,0xa9,0x9d, + 0x32,0x2a,0xcc,0x8d,0xe3,0x8d,0x10,0x52,0x01,0x81,0x55,0xb2,0x30,0x2a,0x7c,0xda, + 0xc7,0x99,0xbd,0x43,0x3e,0x9d,0x06,0x37,0x52,0xf6,0x3e,0x87,0xac,0x9b,0xda,0x29, + 0xa3,0xc2,0x5c,0x2e,0xde,0xa9,0x84,0xfd,0x42,0x2a,0x20,0xb0,0x4a,0x16,0x46,0x85, + 0x4f,0xfb,0x38,0xb3,0x77,0xc8,0xa7,0xd3,0xe0,0x46,0x2a,0xdf,0xe7,0xfd,0x75,0x53, + 0x3b,0x65,0x54,0x98,0xcb,0xc5,0x3b,0x9b,0xb0,0x59,0x48,0x05,0x04,0x56,0xc9,0xc2, + 0xa8,0xc0,0x54,0xaf,0x06,0x86,0xcc,0xd9,0xc9,0xf3,0x69,0x2a,0xb8,0x8b,0xca,0xf7, + 0x39,0x64,0xe9,0xbc,0x4e,0x19,0x15,0xa6,0xf1,0xa0,0x76,0xee,0xb7,0xfe,0x57,0xb4, + 0x91,0x75,0xbb,0x02,0x02,0x7b,0xe4,0xec,0xa8,0x57,0x03,0xd7,0xe6,0x84,0x4f,0x8b, + 0x8a,0xf4,0x2a,0x18,0xdc,0x45,0xe5,0xfb,0xbc,0xb9,0x6e,0x6a,0xad,0xcc,0x49,0x32, + 0xfc,0xa0,0xa2,0xd2,0x36,0xdb,0xaf,0x80,0xc0,0x1e,0x39,0x3b,0x2a,0x43,0x60,0xaa, + 0xd8,0xad,0xed,0xdc,0x32,0xcc,0x56,0xff,0x44,0xef,0xac,0x9b,0x5a,0x2b,0xf5,0x91, + 0x66,0x7e,0x65,0xd7,0xda,0x69,0xbf,0x02,0x02,0x7b,0xe4,0xec,0xa8,0x0c,0x81,0xa9, + 0x62,0xb7,0xb6,0x73,0xcb,0x30,0x5b,0xfd,0x13,0xbd,0xb3,0x6e,0x6a,0xad,0xb4,0x17, + 0xdf,0x90,0xaf,0xf2,0x66,0xdb,0xec,0x57,0x40,0x60,0x8f,0x9c,0x1d,0x15,0x2e,0x36, + 0x55,0xec,0xd6,0x96,0xaf,0x18,0xae,0xa0,0xfe,0x89,0x5e,0x5e,0x37,0xb5,0x56,0xda, + 0x8b,0x6f,0xc8,0x57,0x7c,0xb3,0x3d,0x36,0x5b,0x20,0xb6,0x47,0x16,0xa6,0x05,0x0a, + 0x4f,0x15,0xbb,0xb5,0x9d,0x5b,0x86,0xf1,0x5a,0x9e,0xe8,0xb5,0x75,0x53,0x6b,0xa5, + 0xbd,0xf8,0x26,0x7c,0xf5,0x37,0xdb,0x63,0xb3,0x05,0x62,0x4b,0xe4,0xec,0xb4,0x40, + 0x19,0xa9,0x62,0xb7,0xb6,0x76,0xbf,0x70,0x11,0x5d,0x0f,0xf5,0xb4,0x72,0x69,0xef, + 0xbe,0x09,0x5f,0x94,0x96,0x45,0x4f,0x46,0xdc,0x68,0x81,0xd8,0x12,0x39,0x3b,0x2d, + 0x4a,0x52,0xaa,0xd8,0xad,0x2d,0xdc,0x2c,0x5c,0x4a,0xcb,0x43,0x3d,0xb0,0x5c,0xda, + 0xeb,0xaf,0xf7,0x0b,0xd4,0xb8,0xf4,0xe1,0x88,0x1b,0x2d,0x10,0x5b,0x22,0x67,0xa7, + 0xed,0x0b,0x3f,0x9f,0x57,0xc3,0x6b,0xa2,0xc2,0xc5,0xd5,0x3f,0x98,0x03,0xfb,0xa5, + 0xbd,0x01,0x1b,0xbf,0x58,0xed,0x01,0x0e,0x44,0xdc,0x68,0x81,0xd8,0x12,0x39,0x3b, + 0x6d,0x53,0xc6,0xf9,0xbc,0x9a,0x5f,0x96,0x16,0xae,0xac,0xe5,0xb5,0x9c,0x56,0x31, + 0xed,0x25,0xd8,0xf8,0x85,0x6b,0x0f,0xf0,0x5d,0xbe,0x8d,0x16,0x88,0x2d,0x91,0xb3, + 0xd3,0xf6,0x85,0x9f,0xcf,0xab,0xe1,0x35,0x51,0xe1,0xe2,0x5a,0x5e,0xcb,0x69,0x15, + 0xd3,0x5e,0x82,0x2d,0x5f,0x92,0x21,0x31,0x5e,0xe7,0xdb,0x68,0x81,0xd8,0x12,0x39, + 0x3b,0x2d,0x4a,0x52,0xaa,0xd8,0xad,0x2d,0xdc,0x2c,0x5c,0x4d,0xcb,0xbb,0x3d,0xad, + 0x6b,0xda,0xab,0x70,0xda,0x81,0x14,0xdf,0x6f,0xa9,0x9d,0x16,0x88,0x6d,0x90,0x53, + 0xd3,0x62,0x65,0xa4,0xda,0xba,0x15,0x78,0xa8,0xfa,0xd7,0x7b,0x60,0xdd,0xb4,0x17, + 0xe2,0x9c,0xa3,0xd8,0x37,0x30,0xd2,0xff,0xe7,0x5b,0xea,0x94,0xf0,0x3e,0x3a,0x3b, + 0x30,0x56,0x78,0xaa,0x80,0x8b,0x81,0x27,0x2a,0x7e,0x30,0x07,0x96,0x4e,0x7b,0x2d, + 0x4e,0x38,0x84,0x28,0x93,0xb3,0xfd,0xc8,0xb7,0x54,0x2b,0xe1,0x7d,0x74,0x76,0x60, + 0xac,0xf0,0x54,0x31,0x77,0x03,0x4f,0x54,0xfc,0x5a,0x4e,0xab,0x9e,0xf6,0x72,0x6c, + 0x3f,0x81,0x58,0xa3,0x13,0xae,0xd5,0x4a,0x78,0x1f,0x9d,0x1d,0xf8,0xe9,0xd8,0xb5, + 0x21,0x5f,0x24,0x8c,0x9d,0x06,0x1c,0x50,0xfc,0x54,0x4e,0x2b,0xa0,0xf6,0x7e,0x1c, + 0x72,0x0e,0x51,0xc6,0x06,0xfb,0x11,0x6e,0xa9,0x56,0xc2,0xfb,0xe8,0xec,0xc0,0x57, + 0x63,0xd7,0xe6,0xbc,0x4a,0x18,0x3b,0x0d,0x38,0xa6,0xf2,0xb5,0x9c,0xd6,0x3b,0xed, + 0xb5,0x38,0xed,0x40,0xea,0xef,0xb7,0xce,0x5a,0xad,0x84,0x97,0xd1,0xa9,0x81,0xdf, + 0x4e,0x8e,0x9a,0xb6,0x36,0xe7,0x8b,0x60,0xc0,0x01,0x95,0x0f,0xe6,0xc0,0xba,0x69, + 0x2f,0xc4,0x81,0x67,0x52,0x7c,0xbf,0x45,0xd6,0x6a,0x25,0xbc,0x8c,0x4e,0x0d,0xfc, + 0x76,0x72,0xd4,0xb4,0xb5,0x39,0x05,0xc1,0xe0,0xee,0xca,0x5e,0xcb,0x81,0x5d,0xd3, + 0xde,0x86,0x5d,0x5f,0x92,0x51,0x61,0x3e,0x84,0x3b,0x5f,0x04,0xe1,0xf5,0x71,0xb2, + 0x91,0xbe,0x99,0x1c,0x35,0x6d,0x6d,0x4e,0x41,0x30,0x78,0x80,0xb2,0xd7,0x72,0x5a, + 0xcb,0xb4,0xf7,0x60,0xe3,0x97,0x61,0x4e,0x92,0xcf,0xc2,0x9d,0x2f,0x82,0xf0,0xfa, + 0x38,0xd9,0x48,0xdf,0x4c,0x8e,0x9a,0xb6,0x36,0xa7,0x20,0x18,0x3c,0x43,0xcd,0x83, + 0x39,0xad,0x65,0xda,0x4b,0xb0,0xfd,0x8b,0x35,0x21,0xc3,0xeb,0x70,0xe7,0x8b,0x20, + 0xbc,0x3e,0x4e,0x36,0xd2,0x37,0x93,0xa3,0xa6,0xad,0xcd,0x29,0x08,0x06,0x8f,0x51, + 0xf0,0x60,0x4e,0xeb,0x97,0x51,0x61,0x66,0x1e,0xd1,0x29,0x13,0x32,0xbc,0x0e,0x77, + 0xb2,0x0b,0x32,0xba,0xe3,0xd4,0xcc,0x6f,0x87,0x47,0x4d,0x5b,0x9b,0x53,0x10,0x0c, + 0x1e,0xa3,0xe0,0xb5,0x1c,0x58,0x2e,0xa3,0xc2,0x74,0x1d,0x54,0x94,0xf6,0x00,0x5f, + 0x86,0x3b,0xd9,0x05,0x19,0xdd,0x71,0x6a,0xe6,0xb7,0xc3,0xa3,0xa6,0xad,0xcd,0x29, + 0x08,0x06,0x4f,0x92,0xfd,0x60,0x16,0xd7,0xca,0x91,0x9c,0xa3,0xc2,0x5c,0x28,0x5b, + 0x6c,0xe6,0x0a,0x67,0xbb,0x20,0xa3,0x3b,0x4e,0xcd,0xfc,0x76,0x78,0xd4,0xb4,0xb5, + 0x39,0x05,0xc1,0xe0,0x49,0x0a,0xde,0xcc,0xca,0x4e,0x39,0x12,0x72,0x54,0x98,0xc6, + 0x78,0x51,0xda,0x03,0x7c,0x19,0xee,0x4c,0x17,0x64,0x74,0xc7,0xc9,0x46,0xfa,0x66, + 0x78,0xd4,0xb4,0xb5,0x39,0x05,0xc1,0xe0,0x61,0x6e,0x53,0x28,0x07,0x43,0xce,0x49, + 0xd2,0x9e,0x30,0x44,0xef,0xea,0xdf,0x85,0x3b,0xd3,0x05,0x19,0xdd,0x71,0xb2,0x91, + 0xbe,0x19,0x1e,0x35,0x6d,0x6d,0x4e,0x41,0x30,0x78,0x9e,0xd4,0x37,0xb3,0xb2,0xef, + 0x8e,0x84,0x1c,0x15,0xa6,0x3d,0xe1,0xbe,0xc6,0xa5,0x0f,0x84,0x3b,0xd3,0x05,0x19, + 0xdd,0x71,0xb2,0x91,0xbe,0x19,0x1e,0x35,0x6d,0x6d,0x4e,0x41,0x30,0x78,0xa4,0xbc, + 0x67,0xb3,0xb8,0xef,0x8e,0x24,0x1c,0x15,0xe6,0x72,0xf1,0xa2,0xd2,0x56,0x38,0xd5, + 0x05,0x19,0xc5,0x71,0xbe,0x94,0xbe,0x9a,0x1f,0x35,0x6d,0x6d,0x4e,0x41,0x30,0x78, + 0xa4,0xbc,0x97,0xb3,0xb2,0x4d,0x0e,0xc6,0x1b,0x15,0xa6,0x37,0xe1,0xbe,0xc6,0xa5, + 0x0f,0x84,0x3b,0xd3,0x05,0x19,0xc5,0x71,0xbe,0x94,0x5e,0xce,0x5f,0x1b,0xf5,0xe9, + 0xb4,0xc0,0x51,0xe1,0xd3,0xe0,0x91,0xf2,0x1e,0xcf,0xca,0xbe,0x3b,0x12,0x6f,0x4e, + 0x92,0x09,0x21,0x37,0x75,0xad,0x7b,0x2c,0x5c,0x8e,0xec,0x00,0xb1,0x5b,0x08,0x3f, + 0x99,0x8c,0x39,0xf0,0x78,0x49,0x8f,0x67,0x65,0xdf,0x1d,0x89,0x37,0x27,0xc9,0x84, + 0x90,0x9b,0xba,0xd6,0x3d,0x9c,0x2f,0x41,0xef,0xea,0x67,0x5d,0x2b,0x18,0x3c,0x5b, + 0xf8,0xfb,0x59,0xd9,0x77,0x47,0xb2,0x8d,0x0a,0x33,0x21,0xe4,0x8e,0xae,0x75,0x0f, + 0xe7,0x6b,0x2d,0x8e,0x8c,0xd5,0xcf,0x1a,0x9b,0x2d,0xe2,0x7a,0xe1,0x7e,0x62,0xdf, + 0xcf,0xe2,0xbe,0x3b,0x12,0x6c,0x54,0x98,0x8b,0x26,0xdc,0xcf,0x59,0xa1,0xb7,0x35, + 0xc2,0x57,0x5f,0x30,0x36,0xdb,0xf6,0xdd,0xc2,0x5d,0xc5,0x3e,0xa1,0x95,0x6d,0x72, + 0x24,0xd5,0xa8,0x30,0x17,0x4d,0xb8,0x9f,0xb3,0x42,0x6f,0x6b,0x84,0xaf,0x1e,0x9b, + 0x76,0x6c,0x30,0x78,0xbc,0xc0,0x57,0xb4,0xb2,0x4d,0x8e,0xa4,0x9a,0x93,0xe4,0xba, + 0x09,0xf7,0x73,0x56,0xe8,0x2d,0x8e,0xf0,0xd5,0x63,0xa3,0x4e,0xce,0x06,0x8f,0x17, + 0xf5,0x90,0x56,0xb6,0xc9,0x91,0x48,0x73,0x92,0xb4,0xc7,0xdb,0x7c,0x09,0xbb,0xd6, + 0x3d,0x9c,0xaf,0xb5,0x38,0xc2,0x57,0x0f,0x8f,0x3a,0x36,0x18,0x70,0xc1,0xbe,0x9b, + 0x96,0x27,0xef,0xcc,0x1b,0x13,0x86,0x44,0x2d,0xd2,0xd8,0x1d,0xb1,0x4b,0x27,0x45, + 0x1d,0x1b,0x0c,0x88,0x78,0x4e,0x8b,0x0b,0xe5,0xc8,0x1f,0xf0,0x39,0x49,0xe6,0x9f, + 0x55,0x52,0xda,0x22,0x8d,0xc5,0x11,0xb8,0xf4,0x6d,0x72,0x9e,0xcd,0x06,0x6c,0x3f, + 0xa7,0xd3,0x6a,0x65,0x4e,0x92,0xe1,0x07,0x95,0x17,0xb5,0x48,0x63,0x77,0x04,0x2e, + 0x9d,0x9a,0xb3,0x2c,0xea,0x42,0x30,0xe0,0x87,0x9d,0x17,0x75,0x5a,0xad,0xcc,0x49, + 0xd2,0x78,0x44,0x9b,0x3d,0xd8,0xb5,0xee,0xc9,0x94,0x7d,0xf5,0x11,0xb8,0x74,0x52, + 0xc2,0xca,0xb4,0x3b,0xd9,0x80,0x8d,0x77,0x75,0x5a,0xad,0x74,0x95,0xdd,0xc0,0x2f, + 0xf5,0xc7,0x90,0xb1,0xee,0xc9,0x94,0x7d,0x0d,0x12,0xb8,0x74,0x52,0xc2,0x9a,0xc0, + 0x9b,0xa9,0x80,0xff,0x58,0x7b,0x5a,0xa7,0xd5,0x4a,0x7b,0xeb,0xcd,0xf9,0x52,0x7f, + 0x09,0x19,0xeb,0x9e,0x4c,0xd9,0xd7,0x23,0x81,0x4b,0x87,0x67,0x2b,0x8b,0x1d,0x18, + 0x0c,0x58,0x7a,0x5d,0xa7,0xd5,0x4a,0x7b,0xeb,0xcd,0xf9,0x52,0x7f,0x06,0x19,0xeb, + 0x9e,0x4c,0xd9,0xd7,0x23,0x51,0x4b,0x87,0x07,0xab,0x49,0x9e,0x11,0x0c,0x58,0x7a, + 0x5d,0xa7,0x35,0x4b,0x7b,0xf1,0x4d,0xf8,0x52,0x7f,0x03,0x49,0xeb,0x52,0x4a,0xe7, + 0xc2,0x3c,0x67,0x1f,0xd8,0x69,0xe5,0xd2,0xde,0x7d,0x13,0xbe,0xa4,0xdb,0xcf,0x5b, + 0x97,0x1e,0x9a,0x17,0xe6,0x39,0xfe,0xc0,0x4e,0x2b,0x97,0xf6,0xee,0x6b,0xff,0x32, + 0xee,0xbd,0x60,0x69,0x00,0xfe,0xeb,0xc8,0x03,0x3b,0xad,0x5f,0xda,0xeb,0xaf,0xfd, + 0x0b,0xbc,0xee,0xb2,0xa5,0x01,0xf8,0xc9,0x91,0x37,0x76,0x5a,0xc5,0xb4,0x37,0x60, + 0xe3,0x17,0x7b,0xd7,0x95,0xab,0x03,0xf0,0xd1,0xd7,0x6f,0xec,0xb4,0x96,0x69,0x2f, + 0xc1,0xae,0x2f,0xf0,0x96,0x5b,0x02,0x00,0xf0,0xd1,0x17,0x6f,0xec,0xb4,0xa2,0x69, + 0xef,0xc1,0x96,0x2f,0xea,0x7e,0xbb,0x02,0x00,0xf0,0xca,0xab,0x67,0x76,0x5a,0xd7, + 0xb4,0x57,0xe1,0xb4,0x03,0x39,0x78,0xb3,0x8d,0x01,0x00,0x58,0x30,0xb0,0x6e,0xda, + 0x0b,0x71,0xd4,0x69,0x14,0x1c,0x17,0x00,0x2d,0xa6,0x95,0x4e,0x7b,0x27,0x4e,0x38, + 0x84,0xca,0xbb,0x03,0xa0,0xc5,0xb4,0xea,0x69,0x6f,0xc6,0xc6,0xbd,0xb7,0xdc,0x1d, + 0x00,0x2d,0xa6,0x75,0x50,0x7b,0x45,0xb6,0xec,0xba,0xeb,0xe2,0x00,0xe8,0x32,0xad, + 0x89,0xda,0x8b,0xf2,0x12,0x8d,0x76,0xad,0xb4,0x00,0x7c,0x74,0xd7,0x86,0xba,0x31, + 0x17,0x01,0x00,0xc5,0x94,0x2f,0x00,0x14,0x53,0xbe,0x00,0x50,0xcc,0xff,0x05,0x00, + 0x00,0xc5,0x94,0x2f,0xc0,0xa3,0x78,0xcc,0x27,0x08,0x2c,0x5f,0x57,0x06,0x70,0x15, + 0xde,0xf3,0x5e,0xca,0x17,0xe0,0xc9,0x3c,0xec,0x2d,0x94,0x2f,0x00,0xff,0xe2,0x79, + 0xaf,0x11,0xdb,0xbc,0x6e,0x07,0xe0,0x1e,0xbc,0xf3,0xa9,0x94,0x2f,0x00,0x5f,0xf3, + 0xe0,0x87,0x53,0xbe,0x00,0x1c,0xe4,0xf1,0x0f,0xa1,0x79,0x01,0x58,0xa0,0x0b,0x96, + 0x85,0x37,0xaf,0x33,0x07,0x78,0x1a,0x8d,0x70,0x8a,0xda,0x05,0x20,0x8a,0x82,0x38, + 0xc2,0xdf,0x79,0x01,0x48,0xa5,0x32,0x7e,0xa2,0x79,0x01,0x28,0xa3,0x3b,0xde,0xd2, + 0x9a,0xf7,0x39,0x07,0x08,0xc0,0xb2,0xa7,0xb5,0x49,0x5e,0xe7,0xde,0xef,0xac,0x00, + 0x28,0x70,0xfb,0x5a,0xd1,0xbc,0x00,0x8c,0x75,0xcb,0xc6,0x51,0xbb,0x00,0x5c,0xc5, + 0x0d,0x3a,0xc8,0x5f,0x78,0x01,0xb8,0x81,0xc9,0xdd,0x94,0x5d,0xb5,0x3a,0x17,0x80, + 0x76,0xed,0xcd,0x55,0xd6,0xb6,0x6a,0x17,0x80,0xb1,0xea,0xdb,0x50,0xf3,0x02,0xc0, + 0x47,0xed,0xa5,0xa9,0x73,0x01,0x78,0xb2,0xf6,0x26,0x55,0xb5,0x00,0xd0,0xde,0xb6, + 0x3a,0x17,0x00,0x3e,0xa5,0x5e,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xea,0xfc,0x03,0x26, + 0x84,0x0a,0xd6,0x36,0x10,0x0e,0x00, diff --git a/board/esd/apc405/strataflash.c b/board/esd/apc405/strataflash.c new file mode 100644 index 0000000..ad7a71d --- /dev/null +++ b/board/esd/apc405/strataflash.c @@ -0,0 +1,789 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for ppcboot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + +#define FLASH_MAN_CFI 0x01000000 + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char * cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *)(info->start[sect] + (offset * info->portwidth))); +} +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | + (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + unsigned long address; + + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif +#else + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + - CFG_MONITOR_LEN, + - 1, &flash_info[1]); +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if( info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3 ), (info->chipwidth << 3 )); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + int k; + int size; + int erased; + volatile unsigned long *flash; + + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); +#endif + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for(i=0;iportwidth) && (cnt > 0) ; i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *)cp)); + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while(cnt >= info->portwidth) { + i = info->buffer_size > cnt? cnt: info->buffer_size; + if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + /* handle the aligned part */ + while(cnt >= info->portwidth) { + cword.l = 0; + for(i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; iportwidth; ++i, ++cp) { + flash_add_byte(info, & cword, (*(uchar *)cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if(prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, + prot?"protect":"unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if(prot == 0) { + int i; + for(i = 0 ; isector_count; i++) { + if(info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt,info->start[sector]); + if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ + printf("Command Sequence Error.\n"); + } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) +{ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) +{ + int i; + uchar *cp = (uchar *)cmdbuf; + for(i=0; i< info->portwidth; i++) + *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi(flash_info_t * info) +{ + + for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; + info->portwidth <<= 1) { + for(info->chipwidth =FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } + return 0; +} +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t * info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if(flash_detect_cfi(info)){ +#ifdef DEBUG_FLASH + printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif + sect_cnt = 0; + sector = base; + for(i = 0 ; i < num_erase_regions; i++) { + if(i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) +1; + for(j = 0; j< erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *)dest; + + + /* Check if Flash is (sufficiently) erased */ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if(!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if(flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t *info, ulong addr) +{ + int sector; + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *)dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar)cnt-1); + while(cnt-- > 0) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check(info, sector, info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds new file mode 100644 index 0000000..f7a20d1 --- /dev/null +++ b/board/esd/apc405/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile new file mode 100644 index 0000000..a60495a --- /dev/null +++ b/board/esd/ar405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c new file mode 100644 index 0000000..3aac3c6 --- /dev/null +++ b/board/esd/ar405/ar405.c @@ -0,0 +1,438 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "ar405.h" +#include +#include + +/*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); + +/* ------------------------------------------------------------------------- */ + +#if 0 +#define FPGA_DEBUG +#endif + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = { +#include "fpgadata.c" +}; + +const unsigned char fpgadata_xl30[] = { +#include "fpgadata_xl30.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +int board_early_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int index, len, i; + int status; + +#ifdef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + + /* + * Boot onboard FPGA + */ + /* first try 40er image */ + gd->board_type = 40; + status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); + if (status != 0) { + /* try xl30er image */ + gd->board_type = 30; + status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30)); + if (status != 0) { + /* booting FPGA failed */ +#ifndef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + printf ("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf ("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("FPGA: %s\n", &(fpgadata[index + 1])); + index += len + 3; + } + putc ('\n'); + /* delayed reboot */ + for (i = 20; i > 0; i--) { + printf ("Rebooting in %2d seconds \r", i); + for (index = 0; index < 1000; index++) + udelay (1000); + } + putc ('\n'); + do_reset (NULL, 0, 0, NULL); + } + } + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + *(ushort *) 0xf03000ec = 0x0fff; /* enable all interrupts in fpga */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int index; + int len; + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + const unsigned char *fpga; + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming AR405"); + } else { + puts(str); + } + + puts ("\nFPGA: "); + + /* display infos on fpgaimage */ + if (gd->board_type == 30) { + fpga = fpgadata_xl30; + } else { + fpga = fpgadata; + } + index = 15; + for (i = 0; i < 4; i++) { + len = fpga[index]; + printf ("%s ", &(fpga[index + 1])); + index += len + 3; + } + + putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + + +#if 1 /* test-only: some internal test routines... */ +/* + * Some test routines + */ +int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile uchar *digen = (volatile uchar *)0xf03000b4; + volatile ushort *digout = (volatile ushort *)0xf03000b0; + volatile ushort *digin = (volatile ushort *)0xf03000a0; + int i; + int k; + int start; + int end; + + if (argc != 3) { + puts("Usage: digtest n_start n_end (digtest 0 7)\n"); + return 0; + } + + start = simple_strtol (argv[1], NULL, 10); + end = simple_strtol (argv[2], NULL, 10); + + /* + * Enable digital outputs + */ + *digen = 0x08; + + printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n", + start, end); + + /* + * Set outputs one by one + */ + for (;;) { + for (i=start; i<=end; i++) { + *digout = 0x0001 << i; + for (k=0; k<200; k++) + udelay(1000); + + if (*digin != (0x0001 << i)) { + printf("ERROR: OUT=0x%04X, IN=0x%04X\n", 0x0001 << i, *digin); + return 0; + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + } + } + + return 0; +} +U_BOOT_CMD( + digtest, 3, 1, do_digtest, + "digtest - Test digital in-/output\n", + NULL + ); + + +#define ERROR_DELTA 256 + +struct io { + volatile short val; + short dummy; +}; + +int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile short val; + int i; + int volt; + struct io *out; + struct io *in; + + out = (struct io *)0xf0300090; + in = (struct io *)0xf0300000; + + i = simple_strtol (argv[1], NULL, 10); + + volt = 0; + printf("Setting Channel %d to %dV...\n", i, volt); + out[i].val = (volt * 0x7fff) / 10; + udelay(10000); + val = in[i*2].val; + printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff); + if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || + (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { + printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, + ((volt * 0x7fff) / 40) + ERROR_DELTA); + return -1; + } + val = in[i*2+1].val; + printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff); + if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || + (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { + printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, + ((volt * 0x7fff) / 40) + ERROR_DELTA); + return -1; + } + + volt = 5; + printf("Setting Channel %d to %dV...\n", i, volt); + out[i].val = (volt * 0x7fff) / 10; + udelay(10000); + val = in[i*2].val; + printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff); + if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || + (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { + printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, + ((volt * 0x7fff) / 40) + ERROR_DELTA); + return -1; + } + val = in[i*2+1].val; + printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff); + if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || + (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { + printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, + ((volt * 0x7fff) / 40) + ERROR_DELTA); + return -1; + } + + volt = 10; + printf("Setting Channel %d to %dV...\n", i, volt); + out[i].val = (volt * 0x7fff) / 10; + udelay(10000); + val = in[i*2].val; + printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff); + if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || + (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { + printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, + ((volt * 0x7fff) / 40) + ERROR_DELTA); + return -1; + } + val = in[i*2+1].val; + printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff); + if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || + (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { + printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, + ((volt * 0x7fff) / 40) + ERROR_DELTA); + return -1; + } + + printf("Channel %d OK!\n", i); + + return 0; +} +U_BOOT_CMD( + anatest, 2, 1, do_anatest, + "anatest - Test analog in-/output\n", + NULL + ); + + +int counter = 0; + +void cyclicInt(void *ptr) +{ + *(ushort *)0xf03000e8 = 0x0800; /* ack int */ + counter++; +} + + +int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile uchar *digout = (volatile uchar *)0xf03000b4; + volatile ulong *incin; + int i; + + incin = (volatile ulong *)0xf0300040; + + /* + * Clear inc counter + */ + incin[0] = 0; + incin[1] = 0; + incin[2] = 0; + incin[3] = 0; + + incin = (volatile ulong *)0xf0300050; + + /* + * Inc a little + */ + for (i=0; i<10000; i++) { + switch (i & 0x03) { + case 0: + *digout = 0x02; + break; + case 1: + *digout = 0x03; + break; + case 2: + *digout = 0x01; + break; + case 3: + *digout = 0x00; + break; + } + udelay(10); + } + + printf("Inc 0 = %ld\n", incin[0]); + printf("Inc 1 = %ld\n", incin[1]); + printf("Inc 2 = %ld\n", incin[2]); + printf("Inc 3 = %ld\n", incin[3]); + + *(ushort *)0xf03000e0 = 0x0c80-1; /* set counter */ + *(ushort *)0xf03000ec |= 0x0800; /* enable int */ + irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL); + printf("counter=%d\n", counter); + + return 0; +} +U_BOOT_CMD( + inctest, 3, 1, do_inctest, + "inctest - Test incremental encoder inputs\n", + NULL + ); +#endif diff --git a/board/esd/ar405/ar405.h b/board/esd/ar405/ar405.h new file mode 100644 index 0000000..5fc313a --- /dev/null +++ b/board/esd/ar405/ar405.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/board/esd/ar405/config.mk b/board/esd/ar405/config.mk new file mode 100644 index 0000000..3e8baf6 --- /dev/null +++ b/board/esd/ar405/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd AR405 boards +# + +#TEXT_BASE = 0xFFFE0000 +#TEXT_BASE = 0xFFFD0000 +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/ar405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile new file mode 100644 index 0000000..a60495a --- /dev/null +++ b/board/esd/ash405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c new file mode 100644 index 0000000..03ae7fd --- /dev/null +++ b/board/esd/ash405/ash405.c @@ -0,0 +1,252 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#if 0 +#define FPGA_DEBUG +#endif + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* fpga configuration data - gzip compressed and generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4); + volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4); + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); + + /* + * Reset FPGA via FPGA_DATA pin + */ + SET_FPGA(FPGA_PRG | FPGA_CLK); + udelay(1000); /* wait 1ms */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); + udelay(1000); /* wait 1ms */ + + /* + * Reset external DUARTs + */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + udelay(10); /* wait 10us */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + udelay(1000); /* wait 1ms */ + + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + + /* + * Enable interrupts in exar duart mcr[3] + */ + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; + *duart2_mcr = 0x08; + *duart3_mcr = 0x08; + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming ASH405"); + } else { + puts(str); + } + + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif diff --git a/board/esd/ash405/config.mk b/board/esd/ash405/config.mk new file mode 100644 index 0000000..1d743a9 --- /dev/null +++ b/board/esd/ash405/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ASH405 boards +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/ash405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/canbt/Makefile b/board/esd/canbt/Makefile new file mode 100644 index 0000000..a60495a --- /dev/null +++ b/board/esd/canbt/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c new file mode 100644 index 0000000..2ced6cb --- /dev/null +++ b/board/esd/canbt/canbt.c @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2001 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "canbt.h" +#include +#include + + +/*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + + +/* ------------------------------------------------------------------------- */ + +#if 0 +#define FPGA_DEBUG +#endif + +/* fpga configuration data */ +const unsigned char fpgadata[] = { +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +int board_early_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long cntrl0Reg; + int index, len, i; + int status; + + /* + * Setup GPIO pins + */ + cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff; + cntrl0Reg |= 0x0070f000; + mtdcr (cntrl0, cntrl0Reg); + +#ifdef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + + /* + * Boot onboard FPGA + */ + status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); + if (status != 0) { + /* booting FPGA failed */ +#ifndef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + printf ("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf ("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("FPGA: %s\n", &(fpgadata[index + 1])); + index += len + 3; + } + putc ('\n'); + /* delayed reboot */ + for (i = 20; i > 0; i--) { + printf ("Rebooting in %2d seconds \r", i); + for (index = 0; index < 1000; index++) + udelay (1000); + } + putc ('\n'); + do_reset (NULL, 0, 0, NULL); + } + + /* + * Setup port pins for normal operation + */ + out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32 (GPIO0_TCR, 0x07038100); /* setup for output */ + out32 (GPIO0_OR, 0x07030100); /* set output pins to high (default) */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + int index; + int len; + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (!i || strncmp (str, "CANBT", 5)) { + puts ("### No HW ID - assuming CANBT\n"); + return (0); + } + + puts (str); + + puts ("\nFPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("%s ", &(fpgadata[index + 1])); + index += len + 3; + } + + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + return (16 * 1024 * 1024); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/canbt/canbt.h b/board/esd/canbt/canbt.h new file mode 100644 index 0000000..5fc313a --- /dev/null +++ b/board/esd/canbt/canbt.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/board/esd/canbt/config.mk b/board/esd/canbt/config.mk new file mode 100644 index 0000000..80076cd --- /dev/null +++ b/board/esd/canbt/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +TEXT_BASE = 0xFFFE0000 +#TEXT_BASE = 0xFFFD0000 diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c new file mode 100644 index 0000000..de847f9 --- /dev/null +++ b/board/esd/canbt/flash.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile new file mode 100644 index 0000000..a11ee82 --- /dev/null +++ b/board/esd/cms700/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +# Objects for Xilinx JTAG programming (CPLD) +CPLD = ../common/xilinx_jtag/lenval.o \ + ../common/xilinx_jtag/micro.o \ + ../common/xilinx_jtag/ports.o + +OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c new file mode 100644 index 0000000..649619d --- /dev/null +++ b/board/esd/cms700/cms700.c @@ -0,0 +1,262 @@ +/* + * (C) Copyright 2005 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +extern void lxt971_no_sleep(void); + + +/* fpga configuration data - not compressed, generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; +int filesize = sizeof(fpgadata); + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + /* + * Reset CPLD via GPIO12 (CS3) pin + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET); + udelay(1000); /* wait 1ms */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET); + udelay(1000); /* wait 1ms */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Setup and enable EEPROM write protection + */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + unsigned char str[64]; + int flashcnt; + int delay; + volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000); + volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001); + + puts ("Board: "); + + if (getenv_r("serial#", str, sizeof(str)) == -1) { + puts ("### No HW ID - assuming CMS700"); + } else { + puts(str); + } + + printf(" (PLD-Version=%02d)\n", *ver_reg); + + /* + * Flash LEDs + */ + for (flashcnt = 0; flashcnt < 3; flashcnt++) { + *led_reg = 0x00; /* LEDs off */ + for (delay = 0; delay < 100; delay++) + udelay(1000); + *led_reg = 0x0f; /* LEDs on */ + for (delay = 0; delay < 50; delay++) + udelay(1000); + } + *led_reg = 0x70; + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +#if defined(CFG_EEPROM_WREN) +/* Input: I2C address of EEPROM device to enable. + * -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if was -1. + */ +int eeprom_write_enable (unsigned dev_addr, int state) +{ + if (CFG_I2C_EEPROM_ADDR != dev_addr) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + break; + } + } + return state; +} + +int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int query = argc == 1; + int state = 0; + + if (query) { + /* Query write access state. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + if (state < 0) { + puts ("Query of write access state failed.\n"); + } else { + printf ("Write access for device 0x%0x is %sabled.\n", + CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + state = 0; + } + } else { + if ('0' == argv[1][0]) { + /* Disable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + } else { + /* Enable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + } + if (state < 0) { + puts ("Setup of write access state failed.\n"); + } + } + + return state; +} + +U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL); +#endif /* #if defined(CFG_EEPROM_WREN) */ + +/* ------------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif + +void reset_phy(void) +{ +#ifdef CONFIG_LXT971_NO_SLEEP + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif +} diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk new file mode 100644 index 0000000..5c3c01c --- /dev/null +++ b/board/esd/cms700/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd CMS405 boards +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/cms700/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c new file mode 100644 index 0000000..d48e972 --- /dev/null +++ b/board/esd/common/auto_update.c @@ -0,0 +1,556 @@ +/* + * (C) Copyright 2003-2004 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de. + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "auto_update.h" + +#ifdef CONFIG_AUTO_UPDATE + +#if !(CONFIG_COMMANDS & CFG_CMD_FAT) +#error "must define CFG_CMD_FAT" +#endif + +extern au_image_t au_image[]; +extern int N_AU_IMAGES; + +#define AU_DEBUG +#undef AU_DEBUG + +#undef debug +#ifdef AU_DEBUG +#define debug(fmt,args...) printf (fmt ,##args) +#else +#define debug(fmt,args...) +#endif /* AU_DEBUG */ + + +#define LOAD_ADDR ((unsigned char *)0x100000) /* where to load files into memory */ +#define MAX_LOADSZ 0x1e00000 + +/* externals */ +extern int fat_register_device(block_dev_desc_t *, int); +extern int file_fat_detectfs(void); +extern long file_fat_read(const char *, void *, unsigned long); +long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols); +#ifdef CONFIG_VFD +extern int trab_vfd (ulong); +extern int transfer_pic(unsigned char, unsigned char *, int, int); +#endif +extern int flash_sect_erase(ulong, ulong); +extern int flash_sect_protect (int, ulong, ulong); +extern int flash_write (char *, ulong, ulong); +/* change char* to void* to shutup the compiler */ +extern block_dev_desc_t *get_dev (char*, int); + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +/* references to names in cmd_nand.c */ +#define NANDRW_READ 0x01 +#define NANDRW_WRITE 0x00 +#define NANDRW_JFFS2 0x02 +#define NANDRW_JFFS2_SKIP 0x04 +extern struct nand_chip nand_dev_desc[]; +extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, + size_t * retlen, u_char * buf); +extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + +extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; + + +int au_check_cksum_valid(int i, long nbytes) +{ + image_header_t *hdr; + unsigned long checksum; + + hdr = (image_header_t *)LOAD_ADDR; + + if ((au_image[i].type == AU_FIRMWARE) && (au_image[i].size != ntohl(hdr->ih_size))) { + printf ("Image %s has wrong size\n", au_image[i].name); + return -1; + } + + if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) { + printf ("Image %s bad total SIZE\n", au_image[i].name); + return -1; + } + /* check the data CRC */ + checksum = ntohl(hdr->ih_dcrc); + + if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) + != checksum) { + printf ("Image %s bad data checksum\n", au_image[i].name); + return -1; + } + return 0; +} + + +int au_check_header_valid(int i, long nbytes) +{ + image_header_t *hdr; + unsigned long checksum; + + hdr = (image_header_t *)LOAD_ADDR; + /* check the easy ones first */ +#undef CHECK_VALID_DEBUG +#ifdef CHECK_VALID_DEBUG + printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC); + printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_PPC); + printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes); + printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL); +#endif + if (nbytes < sizeof(*hdr)) + { + printf ("Image %s bad header SIZE\n", au_image[i].name); + return -1; + } + if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) + { + printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name); + return -1; + } + /* check the hdr CRC */ + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) { + printf ("Image %s bad header checksum\n", au_image[i].name); + return -1; + } + hdr->ih_hcrc = htonl(checksum); + + /* check the type - could do this all in one gigantic if() */ + if ((au_image[i].type == AU_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) { + printf ("Image %s wrong type\n", au_image[i].name); + return -1; + } + if ((au_image[i].type == AU_SCRIPT) && (hdr->ih_type != IH_TYPE_SCRIPT)) { + printf ("Image %s wrong type\n", au_image[i].name); + return -1; + } + + /* recycle checksum */ + checksum = ntohl(hdr->ih_size); + +#if 0 /* test-only */ + /* for kernel and app the image header must also fit into flash */ + if (idx != IDX_DISK) + checksum += sizeof(*hdr); + /* check the size does not exceed space in flash. HUSH scripts */ + /* all have ausize[] set to 0 */ + if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { + printf ("Image %s is bigger than FLASH\n", au_image[i].name); + return -1; + } +#endif + + return 0; +} + + +int au_do_update(int i, long sz) +{ + image_header_t *hdr; + char *addr; + long start, end; + int off, rc; + uint nbytes; + int k; +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + int total; +#endif + + hdr = (image_header_t *)LOAD_ADDR; + + switch (au_image[i].type) { + case AU_SCRIPT: + printf("Executing script %s\n", au_image[i].name); + + /* execute a script */ + if (hdr->ih_type == IH_TYPE_SCRIPT) { + addr = (char *)((char *)hdr + sizeof(*hdr)); + /* stick a NULL at the end of the script, otherwise */ + /* parse_string_outer() runs off the end. */ + addr[ntohl(hdr->ih_size)] = 0; + addr += 8; + + /* + * Replace cr/lf with ; + */ + k = 0; + while (addr[k] != 0) { + if ((addr[k] == 10) || (addr[k] == 13)) { + addr[k] = ';'; + } + k++; + } + + run_command(addr, 0); + return 0; + } + + break; + + case AU_FIRMWARE: + case AU_NOR: + case AU_NAND: + start = au_image[i].start; + end = au_image[i].start + au_image[i].size - 1; + + /* + * do not update firmware when image is already in flash. + */ + if (au_image[i].type == AU_FIRMWARE) { + char *orig = (char*)start; + char *new = (char *)((char *)hdr + sizeof(*hdr)); + nbytes = ntohl(hdr->ih_size); + + while(--nbytes) { + if (*orig++ != *new++) { + break; + } + } + if (!nbytes) { + printf("Skipping firmware update - images are identical\n"); + break; + } + } + + /* unprotect the address range */ + /* this assumes that ONLY the firmware is protected! */ + if (au_image[i].type == AU_FIRMWARE) { + flash_sect_protect(0, start, end); + } + + /* + * erase the address range. + */ + if (au_image[i].type != AU_NAND) { + printf("Updating NOR FLASH with image %s\n", au_image[i].name); + debug ("flash_sect_erase(%lx, %lx);\n", start, end); + flash_sect_erase(start, end); + } else { +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + printf("Updating NAND FLASH with image %s\n", au_image[i].name); + debug ("nand_erase(%lx, %lx);\n", start, end); + rc = nand_erase (nand_dev_desc, start, end - start + 1, 0); + debug ("nand_erase returned %x\n", rc); +#endif + } + + udelay(10000); + + /* strip the header - except for the kernel and ramdisk */ + if (au_image[i].type != AU_FIRMWARE) { + addr = (char *)hdr; + off = sizeof(*hdr); + nbytes = sizeof(*hdr) + ntohl(hdr->ih_size); + } else { + addr = (char *)((char *)hdr + sizeof(*hdr)); + off = 0; + nbytes = ntohl(hdr->ih_size); + } + + /* + * copy the data from RAM to FLASH + */ + if (au_image[i].type != AU_NAND) { + debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); + rc = flash_write((uchar *)addr, start, nbytes); + } else { +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes); + rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, + start, nbytes, (size_t *)&total, (uchar *)addr); + debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); +#endif + } + if (rc != 0) { + printf("Flashing failed due to error %d\n", rc); + return -1; + } + + /* + * check the dcrc of the copy + */ + if (au_image[i].type != AU_NAND) { + rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)); + } else { +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, + start, nbytes, (size_t *)&total, (uchar *)addr); + rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size)); +#endif + } + if (rc != ntohl(hdr->ih_dcrc)) { + printf ("Image %s Bad Data Checksum After COPY\n", au_image[i].name); + return -1; + } + + /* protect the address range */ + /* this assumes that ONLY the firmware is protected! */ + if (au_image[i].type == AU_FIRMWARE) { + flash_sect_protect(1, start, end); + } + + break; + + default: + printf("Wrong image type selected!\n"); + } + + return 0; +} + + +static void process_macros (const char *input, char *output) +{ + char c, prev; + const char *varname_start = NULL; + int inputcnt = strlen (input); + int outputcnt = CFG_CBSIZE; + int state = 0; /* 0 = waiting for '$' */ + /* 1 = waiting for '(' or '{' */ + /* 2 = waiting for ')' or '}' */ + /* 3 = waiting for ''' */ +#ifdef DEBUG_PARSER + char *output_start = output; + + printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input); +#endif + + prev = '\0'; /* previous character */ + + while (inputcnt && outputcnt) { + c = *input++; + inputcnt--; + + if (state!=3) { + /* remove one level of escape characters */ + if ((c == '\\') && (prev != '\\')) { + if (inputcnt-- == 0) + break; + prev = c; + c = *input++; + } + } + + switch (state) { + case 0: /* Waiting for (unescaped) $ */ + if ((c == '\'') && (prev != '\\')) { + state = 3; + break; + } + if ((c == '$') && (prev != '\\')) { + state++; + } else { + *(output++) = c; + outputcnt--; + } + break; + case 1: /* Waiting for ( */ + if (c == '(' || c == '{') { + state++; + varname_start = input; + } else { + state = 0; + *(output++) = '$'; + outputcnt--; + + if (outputcnt) { + *(output++) = c; + outputcnt--; + } + } + break; + case 2: /* Waiting for ) */ + if (c == ')' || c == '}') { + int i; + char envname[CFG_CBSIZE], *envval; + int envcnt = input-varname_start-1; /* Varname # of chars */ + + /* Get the varname */ + for (i = 0; i < envcnt; i++) { + envname[i] = varname_start[i]; + } + envname[i] = 0; + + /* Get its value */ + envval = getenv (envname); + + /* Copy into the line if it exists */ + if (envval != NULL) + while ((*envval) && outputcnt) { + *(output++) = *(envval++); + outputcnt--; + } + /* Look for another '$' */ + state = 0; + } + break; + case 3: /* Waiting for ' */ + if ((c == '\'') && (prev != '\\')) { + state = 0; + } else { + *(output++) = c; + outputcnt--; + } + break; + } + prev = c; + } + + if (outputcnt) + *output = 0; + +#ifdef DEBUG_PARSER + printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", + strlen(output_start), output_start); +#endif +} + + +/* + * this is called from board_init() after the hardware has been set up + * and is usable. That seems like a good time to do this. + * Right now the return value is ignored. + */ +int do_auto_update(void) +{ + block_dev_desc_t *stor_dev; + long sz; + int i, res, cnt, old_ctrlc, got_ctrlc; + char buffer[32]; + char str[80]; + + /* + * Check whether a CompactFlash is inserted + */ + if (ide_dev_desc[0].type == DEV_TYPE_UNKNOWN) { + return -1; /* no disk detected! */ + } + + /* check whether it has a partition table */ + stor_dev = get_dev("ide", 0); + if (stor_dev == NULL) { + debug ("Uknown device type\n"); + return -1; + } + if (fat_register_device(stor_dev, 1) != 0) { + debug ("Unable to register ide disk 0:1 for fatls\n"); + return -1; + } + + /* + * Check if magic file is present + */ + if (do_fat_read(AU_MAGIC_FILE, buffer, sizeof(buffer), LS_NO) <= 0) { + return -1; + } + +#ifdef CONFIG_AUTO_UPDATE_SHOW + board_auto_update_show(1); +#endif + puts("\nAutoUpdate Disk detected! Trying to update system...\n"); + + /* make sure that we see CTRL-C and save the old state */ + old_ctrlc = disable_ctrlc(0); + + /* just loop thru all the possible files */ + for (i = 0; i < N_AU_IMAGES; i++) { + /* + * Try to expand the environment var in the fname + */ + process_macros(au_image[i].name, str); + strcpy(au_image[i].name, str); + + printf("Reading %s ...", au_image[i].name); + /* just read the header */ + sz = do_fat_read(au_image[i].name, LOAD_ADDR, sizeof(image_header_t), LS_NO); + debug ("read %s sz %ld hdr %d\n", + au_image[i].name, sz, sizeof(image_header_t)); + if (sz <= 0 || sz < sizeof(image_header_t)) { + puts(" not found\n"); + continue; + } + if (au_check_header_valid(i, sz) < 0) { + puts(" header not valid\n"); + continue; + } + sz = do_fat_read(au_image[i].name, LOAD_ADDR, MAX_LOADSZ, LS_NO); + debug ("read %s sz %ld hdr %d\n", + au_image[i].name, sz, sizeof(image_header_t)); + if (sz <= 0 || sz <= sizeof(image_header_t)) { + puts(" not found\n"); + continue; + } + if (au_check_cksum_valid(i, sz) < 0) { + puts(" checksum not valid\n"); + continue; + } + puts(" done\n"); + + do { + res = au_do_update(i, sz); + /* let the user break out of the loop */ + if (ctrlc() || had_ctrlc()) { + clear_ctrlc(); + if (res < 0) + got_ctrlc = 1; + break; + } + cnt++; + } while (res < 0); + } + + /* restore the old state */ + disable_ctrlc(old_ctrlc); + + puts("AutoUpdate finished\n\n"); +#ifdef CONFIG_AUTO_UPDATE_SHOW + board_auto_update_show(0); +#endif + + return 0; +} + + +int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + do_auto_update(); + + return 0; +} +U_BOOT_CMD( + autoupd, 1, 1, auto_update, + "autoupd - Automatically update images\n", + NULL +); +#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h new file mode 100644 index 0000000..e2af3c7 --- /dev/null +++ b/board/esd/common/auto_update.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _AUTO_UPDATE_H_ +#define _AUTO_UPDATE_H_ + +#define MBR_MAGIC 0x07081967 +#define MBR_MAGIC_ADDR 0x100 /* offset 0x100 should be free space */ + +#define AU_MAGIC_FILE "__auto_update" + +#define AU_SCRIPT 1 +#define AU_FIRMWARE 2 +#define AU_NOR 3 +#define AU_NAND 4 + +struct au_image_s { + char name[80]; + ulong start; + ulong size; + int type; +}; + +typedef struct au_image_s au_image_t; + +int do_auto_update(void); +#ifdef CONFIG_AUTO_UPDATE_SHOW +void board_auto_update_show(int au_active); +#endif + +#endif /* #ifndef _AUTO_UPDATE_H_ */ diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c new file mode 100644 index 0000000..dca10be --- /dev/null +++ b/board/esd/common/flash.c @@ -0,0 +1,672 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + short n; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { + /* set sector offsets for bottom boot block type */ + for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ + info->start[i] = base; + base += 8 << 10; + } + while (i < info->sector_count) { /* 64k regular sectors */ + info->start[i] = base; + base += 64 << 10; + ++i; + } + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ + base -= 8 << 10; + --i; + info->start[i] = base; + } + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); + break; + case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); + break; + case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); + break; + case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n"); + break; + case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_SST320: printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n"); + break; + case FLASH_SST640: printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); +#endif + + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + short n; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; + + value = addr2[CFG_FLASH_READ0]; + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: + info->flash_id = FLASH_MAN_EXCEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[CFG_FLASH_READ1]; /* device ID */ + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: + info->flash_id += FLASH_AMDL322B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U: + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000; break; /* => 8 MB */ + +#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM)) + case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A: + info->flash_id += FLASH_SST800A; + info->sector_count = 16; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A: + case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601: + case (CFG_FLASH_WORD_SIZE)SST_ID_xF1602: + info->flash_id += FLASH_SST160A; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE)SST_ID_xF3201: + case (CFG_FLASH_WORD_SIZE)SST_ID_xF3202: + info->flash_id += FLASH_SST320; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)SST_ID_xF6401: + case (CFG_FLASH_WORD_SIZE)SST_ID_xF6402: + info->flash_id += FLASH_SST640; + info->sector_count = 128; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { + /* set sector offsets for bottom boot block type */ + for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ + info->start[i] = base; + base += 8 << 10; + } + while (i < info->sector_count) { /* 64k regular sectors */ + info->start[i] = base; + base += 64 << 10; + ++i; + } + } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ + base -= 8 << 10; + --i; + info->start[i] = base; + } + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) + info->protect[i] = 0; + else + info->protect[i] = addr2[CFG_FLASH_READ2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + ulong start, now, last; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */ + for (i=0; i<50; i++) + udelay(1000); /* wait 1 ms */ + } else { + if (sect == s_first) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + } + addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + } + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) + { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c new file mode 100644 index 0000000..ad56402 --- /dev/null +++ b/board/esd/common/fpga.c @@ -0,0 +1,282 @@ +/* + * (C) Copyright 2001-2004 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#ifdef FPGA_DEBUG +#define DBG(x...) printf(x) +#else +#define DBG(x...) +#endif /* DEBUG */ + +#define MAX_ONES 226 + +#ifdef CFG_FPGA_PRG +# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/ +# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ +# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ +# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ +# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ +#else +# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ +# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ +#endif + +#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ +#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ +#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ + +#ifndef SET_FPGA +# define SET_FPGA(data) out32(GPIO0_OR, data) +#endif + +#ifdef FPGA_PROG_ACTIVE_HIGH +# define FPGA_PRG_LOW FPGA_PRG +# define FPGA_PRG_HIGH 0 +#else +# define FPGA_PRG_LOW 0 +# define FPGA_PRG_HIGH FPGA_PRG +#endif + +#define FPGA_CLK_LOW 0 +#define FPGA_CLK_HIGH FPGA_CLK + +#define FPGA_DATA_LOW 0 +#define FPGA_DATA_HIGH FPGA_DATA + +#define FPGA_WRITE_1 { \ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ + +#define FPGA_WRITE_0 { \ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ + +#ifndef FPGA_DONE_STATE +# define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE) +#endif +#ifndef FPGA_INIT_STATE +# define FPGA_INIT_STATE (in32(GPIO0_IR) & FPGA_INIT) +#endif + + +static int fpga_boot(unsigned char *fpgadata, int size) +{ + int i,index,len; + int count; +#ifdef CFG_FPGA_SPARTAN2 + int j; +#else + unsigned char b; + int bit; +#endif + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) + { + len = fpgadata[index]; + DBG("FPGA: %s\n", &(fpgadata[index+1])); + index += len+3; + } + +#ifdef CFG_FPGA_SPARTAN2 + /* search for preamble 0xFFFFFFFF */ + while (1) + { + if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) && + (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff)) + break; /* preamble found */ + else + index++; + } +#else + /* search for preamble 0xFF2X */ + for (index = 0; index < size-1 ; index++) + { + if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30)) + break; + } + index += 2; +#endif + + DBG("FPGA: configdata starts at position 0x%x\n",index); + DBG("FPGA: length of fpga-data %d\n", size-index); + + /* + * Setup port pins for fpga programming + */ +#ifndef CONFIG_M5249 + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ +#endif + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */ + + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); + + /* + * Init fpga by asserting and deasserting PROGRAM* + */ + SET_FPGA(FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */ + + /* Wait for FPGA init line low */ + count = 0; + while (FPGA_INIT_STATE) + { + udelay(1000); /* wait 1ms */ + /* Check for timeout - 100us max, so use 3ms */ + if (count++ > 3) + { + DBG("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_LOW; + } + } + + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); + + /* deassert PROGRAM* */ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */ + + /* Wait for FPGA end of init period . */ + count = 0; + while (!(FPGA_INIT_STATE)) + { + udelay(1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) + { + DBG("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_HIGH; + } + } + + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); + + DBG("write configuration data into fpga\n"); + /* write configuration-data into fpga... */ + +#ifdef CFG_FPGA_SPARTAN2 + /* + * Load uncompressed image into fpga + */ + for (i=index; i= 1) && (b <= MAX_ONES)) + { + for(bit=0; bit= (MAX_ONES+2)) && (b <= 254)) + { + for(bit=0; bit<(b-(MAX_ONES+2)); bit++) + { + FPGA_WRITE_0; + } + FPGA_WRITE_1; + } + else if (b == 255) + { + FPGA_WRITE_1; + } + } +#endif + + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); + + /* + * Check if fpga's DONE signal - correctly booted ? + */ + + /* Wait for FPGA end of programming period . */ + count = 0; + while (!(FPGA_DONE_STATE)) + { + udelay(1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) + { + DBG("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_DONE; + } + } + + DBG("FPGA: Booting successful!\n"); + return 0; +} diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c new file mode 100644 index 0000000..0edc083 --- /dev/null +++ b/board/esd/common/lcd.c @@ -0,0 +1,334 @@ +/* + * (C) Copyright 2003-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "lcd.h" + + +extern int video_display_bitmap (ulong, int, int); + + +int palette_index; +int palette_value; +int lcd_depth; +unsigned char *glob_lcd_reg; +unsigned char *glob_lcd_mem; + +#ifdef CFG_LCD_ENDIAN +void lcd_setup(int lcd, int config) +{ + if (lcd == 0) { + /* + * Set endianess and reset lcd controller 0 (small) + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ + udelay(10); /* wait 10us */ + if (config == 1) { + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ + } else { + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ + } + udelay(10); /* wait 10us */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ + } else { + /* + * Set endianess and reset lcd controller 1 (big) + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ + udelay(10); /* wait 10us */ + if (config == 1) { + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ + } else { + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ + } + udelay(10); /* wait 10us */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ + } + + /* + * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive + */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */ +} +#endif /* #ifdef CFG_LCD_ENDIAN */ + + +void lcd_bmp(uchar *logo_bmp) +{ + int i; + uchar *ptr; + ushort *ptr2; + ushort val; + unsigned char *dst = NULL; + int x, y; + int width, height, bpp, colors, line_size; + int header_size; + unsigned char *bmp; + unsigned char r, g, b; + BITMAPINFOHEADER *bm_info; + ulong len; + + /* + * Check for bmp mark 'BM' + */ + if (*(ushort *)logo_bmp != 0x424d) { + + /* + * Decompress bmp image + */ + len = CFG_VIDEO_LOGO_MAX_SIZE; + dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); + if (dst == NULL) { + printf("Error: malloc in gunzip failed!\n"); + return; + } + if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) { + return; + } + if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); + } + + /* + * Check for bmp mark 'BM' + */ + if (*(ushort *)dst != 0x424d) { + printf("LCD: Unknown image format!\n"); + free(dst); + return; + } + } else { + /* + * Uncompressed BMP image, just use this pointer + */ + dst = (uchar *)logo_bmp; + } + + /* + * Get image info from bmp-header + */ + bm_info = (BITMAPINFOHEADER *)(dst + 14); + bpp = LOAD_SHORT(bm_info->biBitCount); + width = LOAD_LONG(bm_info->biWidth); + height = LOAD_LONG(bm_info->biHeight); + switch (bpp) { + case 1: + colors = 1; + line_size = width >> 3; + break; + case 4: + colors = 16; + line_size = width >> 1; + break; + case 8: + colors = 256; + line_size = width; + break; + case 24: + colors = 0; + line_size = width * 3; + break; + default: + printf("LCD: Unknown bpp (%d) im image!\n", bpp); + if ((dst != NULL) && (dst != (uchar *)logo_bmp)) { + free(dst); + } + return; + } + printf(" (%d*%d, %dbpp)\n", width, height, bpp); + + /* + * Write color palette + */ + if ((colors <= 256) && (lcd_depth <= 8)) { + ptr = (unsigned char *)(dst + 14 + 40); + for (i=0; i> 3; + g = *bmp++ >> 2; + r = *bmp++ >> 3; + val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); + *ptr2++ = val; + } + } else if (bpp == 8) { + for (x=0; x> 3; + g = *ptr++ >> 2; + r = *ptr++ >> 3; + val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); + *ptr2++ = val; + } + } + } else { + for (x=0; xusage); + return 1; + } + + addr = simple_strtoul(argv[1], NULL, 16); + + str = getenv("bd_type"); + if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) { + /* + * SM501 available, use standard bmp command + */ + return (video_display_bitmap(addr, 0, 0)); + } else { + /* + * No SM501 available, use esd epson bmp command + */ + lcd_bmp((uchar *)addr); + return 0; + } +} + +U_BOOT_CMD( + esdbmp, 2, 1, do_esdbmp, + "esdbmp - display BMP image\n", + " - display image\n" +); +#endif diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h new file mode 100644 index 0000000..3169e6b --- /dev/null +++ b/board/esd/common/lcd.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2003-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Neutralize little endians. + */ +#define SWAP_LONG(data) ((unsigned long) \ + (((unsigned long)(data) >> 24) | \ + ((unsigned long)(data) << 24) | \ + (((unsigned long)(data) >> 8) & 0x0000ff00 ) | \ + (((unsigned long)(data) << 8) & 0x00ff0000 ))) +#define SWAP_SHORT(data) ((unsigned short) \ + (((unsigned short)(data) >> 8 ) | \ + ((unsigned short)(data) << 8 ))) +#define LOAD_LONG(data) SWAP_LONG(data) +#define LOAD_SHORT(data) SWAP_SHORT(data) + +#ifndef FALSE +#define FALSE 0 +#define TRUE (!FALSE) +#endif + +#define S1D_WRITE_PALETTE(p,i,r,g,b) \ + { \ + ((volatile uchar*)(p))[palette_index] = (uchar)(i); \ + ((volatile uchar*)(p))[palette_value] = (uchar)(r); \ + ((volatile uchar*)(p))[palette_value] = (uchar)(g); \ + ((volatile uchar*)(p))[palette_value] = (uchar)(b); \ + } + +typedef struct +{ + ushort Index; + uchar Value; +} S1D_REGS; + +typedef struct /**** BMP file info structure ****/ +{ + unsigned int biSize; /* Size of info header */ + int biWidth; /* Width of image */ + int biHeight; /* Height of image */ + unsigned short biPlanes; /* Number of color planes */ + unsigned short biBitCount; /* Number of bits per pixel */ + unsigned int biCompression; /* Type of compression to use */ + unsigned int biSizeImage; /* Size of image data */ + int biXPelsPerMeter; /* X pixels per meter */ + int biYPelsPerMeter; /* Y pixels per meter */ + unsigned int biClrUsed; /* Number of colors used */ + unsigned int biClrImportant; /* Number of important colors */ +} BITMAPINFOHEADER; diff --git a/board/esd/common/misc.c b/board/esd/common/misc.c new file mode 100644 index 0000000..48b4b7c --- /dev/null +++ b/board/esd/common/misc.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_LXT971_NO_SLEEP +#include +#endif + + +#ifdef CONFIG_LXT971_NO_SLEEP +void lxt971_no_sleep(void) +{ + unsigned short reg; + + miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, ®); + reg &= ~0x0040; /* disable sleep mode */ + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg); +} +#endif /* CONFIG_LXT971_NO_SLEEP */ diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c new file mode 100644 index 0000000..f711205 --- /dev/null +++ b/board/esd/common/pci.c @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +u_long pci9054_iobase; + + +#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ +#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ + + +/*-----------------------------------------------------------------------------+ +| Subroutine: pci9054_read_config_dword +| Description: Read a PCI configuration register +| Inputs: +| hose PCI Controller +| dev PCI Bus+Device+Function number +| offset Configuration register number +| value Address of the configuration register value +| Return value: +| 0 Successful ++-----------------------------------------------------------------------------*/ +int pci9054_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32* value) +{ + unsigned long conAdrVal; + unsigned long val; + + /* generate coded value for CON_ADR register */ + conAdrVal = dev | (offset & 0xfc) | 0x80000000; + + /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ + *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; + + /* Note: *pResult comes back as -1 if machine check happened */ + val = in32r(PCI_PRIMARY_CDR); + + *value = (unsigned long) val; + + out32r(PCI_PRIMARY_CAR, 0); + + if ((*(unsigned long *)0x50000304) & 0x60000000) + { + /* clear pci master/target abort bits */ + *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; + } + + return 0; +} + +/*-----------------------------------------------------------------------------+ +| Subroutine: pci9054_write_config_dword +| Description: Write a PCI configuration register. +| Inputs: +| hose PCI Controller +| dev PCI Bus+Device+Function number +| offset Configuration register number +| Value Configuration register value +| Return value: +| 0 Successful +| Updated for pass2 errata #6. Need to disable interrupts and clear the +| PCICFGADR reg after writing the PCICFGDATA reg. ++-----------------------------------------------------------------------------*/ +int pci9054_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + unsigned long conAdrVal; + + conAdrVal = dev | (offset & 0xfc) | 0x80000000; + + *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; + + out32r(PCI_PRIMARY_CDR, value); + + out32r(PCI_PRIMARY_CAR, 0); + + /* clear pci master/target abort bits */ + *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; + + return (0); +} + +/*----------------------------------------------------------------------- + */ + +#ifdef CONFIG_DASA_SIM +static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *_) +{ + unsigned int iobase; + unsigned short status = 0; + unsigned char timer; + + /* + * Configure PLX PCI9054 + */ + pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status); + status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status); + + /* Check the latency timer for values >= 0x60. + */ + pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); + if (timer < 0x60) + { + pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); + } + + /* Set I/O base register. + */ + pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE); + pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); + + pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); + + if (pci9054_iobase == 0xffffffff) + { + printf("Error: Can not set I/O base register.\n"); + return; + } +} +#endif + +static struct pci_config_table pci9054_config_table[] = { +#ifndef CONFIG_PCI_PNP + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), + pci_cfgfunc_config_device, { CFG_ETH_IOBASE, + CFG_ETH_IOBASE, + PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, +#ifdef CONFIG_DASA_SIM + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN), + pci_dasa_sim_config_pci9054 }, +#endif +#endif + { } +}; + +static struct pci_controller pci9054_hose = { + config_table: pci9054_config_table, +}; + +void pci_init_board(void) +{ + struct pci_controller *hose = &pci9054_hose; + + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region(hose->regions + 0, + 0x00000000, 0x00000000, 0x01000000, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI Memory space */ + pci_set_region(hose->regions + 1, + 0x00000000, 0xc0000000, 0x10000000, + PCI_REGION_MEM); + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + pci9054_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + pci9054_write_config_dword); + + hose->region_count = 2; + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); +} diff --git a/board/esd/common/s1d13704_320_240_4bpp.h b/board/esd/common/s1d13704_320_240_4bpp.h new file mode 100644 index 0000000..77c8a46 --- /dev/null +++ b/board/esd/common/s1d13704_320_240_4bpp.h @@ -0,0 +1,53 @@ +/* + * + * Generic Header information generated by 13704CFG.EXE (Build 10) + * + * Copyright (c) 2000,2001 Epson Research and Development, Inc. + * All rights reserved. + * + * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz) + * + * This file defines the configuration environment and registers, + * which can be used by any software, such as display drivers. + * + * PLEASE NOTE: If you FTP this file to a non-Windows platform, make + * sure you transfer this file using ASCII, not BINARY + * mode. + * + */ + +static S1D_REGS regs_13704_320_240_4bpp[] = +{ + { 0x00, 0x00 }, /* Revision Code Register */ + { 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */ + { 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */ + { 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */ + { 0x04, 0x27 }, /* Horizontal Panel Size Register */ + { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ + { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ + { 0x07, 0x00 }, /* FPLINE Start Position Register */ + { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ + { 0x09, 0x00 }, /* FPFRAME Start Position Register */ + { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ + { 0x0B, 0x00 }, /* MOD Rate Register */ + { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ + { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ + { 0x0E, 0x00 }, /* Not Used */ + { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ + { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ + { 0x11, 0x00 }, /* Not Used */ + { 0x12, 0x00 }, /* Memory Address Offset Register */ + { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ + { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ + { 0x15, 0x00 }, /* Look-Up Table Address Register */ + { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ + { 0x17, 0x00 }, /* Look-Up Table Data Register */ + { 0x18, 0x01 }, /* GPIO Configuration Control Register */ + { 0x19, 0x01 }, /* GPIO Status/Control Register */ + { 0x1A, 0x00 }, /* Scratch Pad Register */ + { 0x1B, 0x00 }, /* SwivelView Mode Register */ + { 0x1C, 0xA0 }, /* Line Byte Count Register */ + { 0x1D, 0x00 }, /* Not Used */ + { 0x1E, 0x00 }, /* Not Used */ + { 0x1F, 0x00 }, /* Not Used */ +}; diff --git a/board/esd/common/s1d13705_320_240_8bpp.h b/board/esd/common/s1d13705_320_240_8bpp.h new file mode 100644 index 0000000..60843ac --- /dev/null +++ b/board/esd/common/s1d13705_320_240_8bpp.h @@ -0,0 +1,53 @@ +/* + * + * Generic Header information generated by 13704CFG.EXE (Build 10) + * + * Copyright (c) 2000,2001 Epson Research and Development, Inc. + * All rights reserved. + * + * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz) + * + * This file defines the configuration environment and registers, + * which can be used by any software, such as display drivers. + * + * PLEASE NOTE: If you FTP this file to a non-Windows platform, make + * sure you transfer this file using ASCII, not BINARY + * mode. + * + */ + +static S1D_REGS regs_13705_320_240_8bpp[] = +{ + { 0x00, 0x00 }, /* Revision Code Register */ + { 0x01, 0x23 }, /* Mode Register 0 Register */ + { 0x02, 0xE0 }, /* Mode Register 1 Register */ + { 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */ + { 0x04, 0x27 }, /* Horizontal Panel Size Register */ + { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ + { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ + { 0x07, 0x00 }, /* FPLINE Start Position Register */ + { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ + { 0x09, 0x01 }, /* FPFRAME Start Position Register */ + { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ + { 0x0B, 0x00 }, /* MOD Rate Register */ + { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ + { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ + { 0x0E, 0x00 }, /* Not Used */ + { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ + { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ + { 0x11, 0x00 }, /* Not Used */ + { 0x12, 0x00 }, /* Memory Address Offset Register */ + { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ + { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ + { 0x15, 0x00 }, /* Look-Up Table Address Register */ + { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ + { 0x17, 0x00 }, /* Look-Up Table Data Register */ + { 0x18, 0x01 }, /* GPIO Configuration Control Register */ + { 0x19, 0x01 }, /* GPIO Status/Control Register */ + { 0x1A, 0x00 }, /* Scratch Pad Register */ + { 0x1B, 0x00 }, /* SwivelView Mode Register */ + { 0x1C, 0xFF }, /* Line Byte Count Register */ + { 0x1D, 0x00 }, /* Not Used */ + { 0x1E, 0x00 }, /* Not Used */ + { 0x1F, 0x00 }, /* Not Used */ +}; diff --git a/board/esd/common/s1d13806_1024_768_8bpp.h b/board/esd/common/s1d13806_1024_768_8bpp.h new file mode 100644 index 0000000..68801bf --- /dev/null +++ b/board/esd/common/s1d13806_1024_768_8bpp.h @@ -0,0 +1,125 @@ +/* + * + * File generated by S1D13806CFG.EXE + * + * Copyright (c) 2000,2001 Epson Research and Development, Inc. + * All rights reserved. + * + * PLEASE NOTE: If you FTP this file to a non-Windows platform, make + * sure you transfer this file using ASCII, not BINARY mode. + * + * Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz) + * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz) + * + */ + +static S1D_REGS regs_13806_1024_768_8bpp[] = +{ + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x00}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ + {0x0008,0x00}, /* General IO Pins Control Register 0 */ + {0x0009,0x00}, /* General IO Pins Control Register 1 */ + {0x0010,0x00}, /* Memory Clock Configuration Register */ + {0x0014,0x01}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x03}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x55}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x7F}, /* LCD Horizontal Display Width Register */ + {0x0034,0x12}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x01}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xFF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x02}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x03}, /* LCD Display Mode Register */ + {0x0041,0x00}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x00}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x10}, /* TV Output Control Register */ + {0x0060,0x03}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x00}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01F0,0x10}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ +}; diff --git a/board/esd/common/s1d13806_320_240_4bpp.h b/board/esd/common/s1d13806_320_240_4bpp.h new file mode 100644 index 0000000..24d7350 --- /dev/null +++ b/board/esd/common/s1d13806_320_240_4bpp.h @@ -0,0 +1,125 @@ +/* + * + * File generated by S1D13806CFG.EXE + * + * Copyright (c) 2000,2001 Epson Research and Development, Inc. + * All rights reserved. + * + * PLEASE NOTE: If you FTP this file to a non-Windows platform, make + * sure you transfer this file using ASCII, not BINARY mode. + * + * Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz) + * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz) + * + */ + +static S1D_REGS regs_13806_320_240_4bpp[] = +{ + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x08}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x08}, /* General IO Pins Configuration Register 1 */ + {0x0008,0x08}, /* General IO Pins Control Register 0 */ + {0x0009,0x00}, /* General IO Pins Control Register 1 */ + {0x0010,0x00}, /* Memory Clock Configuration Register */ + {0x0014,0x32}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x03}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x00}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x27}, /* LCD Horizontal Display Width Register */ + {0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x01}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x00}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x02}, /* LCD Display Mode Register */ + {0x0041,0x00}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x50}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x00}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x10}, /* TV Output Control Register */ + {0x0060,0x03}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x00}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01F0,0x10}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ +}; diff --git a/board/esd/common/s1d13806_640_480_16bpp.h b/board/esd/common/s1d13806_640_480_16bpp.h new file mode 100644 index 0000000..178f1a9 --- /dev/null +++ b/board/esd/common/s1d13806_640_480_16bpp.h @@ -0,0 +1,125 @@ +/* + * + * File generated by S1D13806CFG.EXE + * + * Copyright (c) 2000,2001 Epson Research and Development, Inc. + * All rights reserved. + * + * PLEASE NOTE: If you FTP this file to a non-Windows platform, make + * sure you transfer this file using ASCII, not BINARY mode. + * + * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) + * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) + * + */ + +static S1D_REGS regs_13806_640_480_16bpp[] = +{ + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ + {0x0008,0x18}, /* General IO Pins Control Register 0 */ + {0x0009,0x00}, /* General IO Pins Control Register 1 */ + {0x0010,0x00}, /* Memory Clock Configuration Register */ + {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x03}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x25}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ + {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x00}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x05}, /* LCD Display Mode Register */ + {0x0041,0x00}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x10}, /* TV Output Control Register */ + {0x0060,0x05}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x00}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01F0,0x10}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ +}; diff --git a/board/esd/common/s1d13806_640_480_8bpp.h b/board/esd/common/s1d13806_640_480_8bpp.h new file mode 100644 index 0000000..c1f5b2b --- /dev/null +++ b/board/esd/common/s1d13806_640_480_8bpp.h @@ -0,0 +1,125 @@ +/* + * + * File generated by S1D13806CFG.EXE + * + * Copyright (c) 2000,2001 Epson Research and Development, Inc. + * All rights reserved. + * + * PLEASE NOTE: If you FTP this file to a non-Windows platform, make + * sure you transfer this file using ASCII, not BINARY mode. + * + * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) + * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) + * + */ + +static S1D_REGS regs_13806_640_320_16bpp[] = +{ + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ + {0x0008,0x18}, /* General IO Pins Control Register 0 */ + {0x0009,0x00}, /* General IO Pins Control Register 1 */ + {0x0010,0x00}, /* Memory Clock Configuration Register */ + {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x03}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x25}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ + {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x00}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x03}, /* LCD Display Mode Register (8bpp) */ + {0x0041,0x00}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x10}, /* TV Output Control Register */ + {0x0060,0x05}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x00}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01F0,0x10}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ +}; diff --git a/board/esd/common/xilinx_jtag/lenval.c b/board/esd/common/xilinx_jtag/lenval.c new file mode 100644 index 0000000..7316266 --- /dev/null +++ b/board/esd/common/xilinx_jtag/lenval.c @@ -0,0 +1,217 @@ +/* + * (C) Copyright 2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*******************************************************/ +/* file: lenval.c */ +/* abstract: This file contains routines for using */ +/* the lenVal data structure. */ +/*******************************************************/ + +#include +#include + +#include "lenval.h" +#include "ports.h" + + +/***************************************************************************** + * Function: value + * Description: Extract the long value from the lenval array. + * Parameters: plvValue - ptr to lenval. + * Returns: long - the extracted value. + *****************************************************************************/ +long value( lenVal* plvValue ) +{ + long lValue; /* result to hold the accumulated result */ + short sIndex; + + lValue = 0; + for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex ) + { + lValue <<= 8; /* shift the accumulated result */ + lValue |= plvValue->val[ sIndex]; /* get the last byte first */ + } + + return( lValue ); +} + +/***************************************************************************** + * Function: initLenVal + * Description: Initialize the lenval array with the given value. + * Assumes lValue is less than 256. + * Parameters: plv - ptr to lenval. + * lValue - the value to set. + * Returns: void. + *****************************************************************************/ +void initLenVal( lenVal* plv, + long lValue ) +{ + plv->len = 1; + plv->val[0] = (unsigned char)lValue; +} + +/***************************************************************************** + * Function: EqualLenVal + * Description: Compare two lenval arrays with an optional mask. + * Parameters: plvTdoExpected - ptr to lenval #1. + * plvTdoCaptured - ptr to lenval #2. + * plvTdoMask - optional ptr to mask (=0 if no mask). + * Returns: short - 0 = mismatch; 1 = equal. + *****************************************************************************/ +short EqualLenVal( lenVal* plvTdoExpected, + lenVal* plvTdoCaptured, + lenVal* plvTdoMask ) +{ + short sEqual; + short sIndex; + unsigned char ucByteVal1; + unsigned char ucByteVal2; + unsigned char ucByteMask; + + sEqual = 1; + sIndex = plvTdoExpected->len; + + while ( sEqual && sIndex-- ) + { + ucByteVal1 = plvTdoExpected->val[ sIndex ]; + ucByteVal2 = plvTdoCaptured->val[ sIndex ]; + if ( plvTdoMask ) + { + ucByteMask = plvTdoMask->val[ sIndex ]; + ucByteVal1 &= ucByteMask; + ucByteVal2 &= ucByteMask; + } + if ( ucByteVal1 != ucByteVal2 ) + { + sEqual = 0; + } + } + + return( sEqual ); +} + + +/***************************************************************************** + * Function: RetBit + * Description: return the (byte, bit) of lv (reading from left to right). + * Parameters: plv - ptr to lenval. + * iByte - the byte to get the bit from. + * iBit - the bit number (0=msb) + * Returns: short - the bit value. + *****************************************************************************/ +short RetBit( lenVal* plv, + int iByte, + int iBit ) +{ + /* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */ + /* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */ + return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) ); +} + +/***************************************************************************** + * Function: SetBit + * Description: set the (byte, bit) of lv equal to val + * Example: SetBit("00000000",byte, 1) equals "01000000". + * Parameters: plv - ptr to lenval. + * iByte - the byte to get the bit from. + * iBit - the bit number (0=msb). + * sVal - the bit value to set. + * Returns: void. + *****************************************************************************/ +void SetBit( lenVal* plv, + int iByte, + int iBit, + short sVal ) +{ + unsigned char ucByteVal; + unsigned char ucBitMask; + + ucBitMask = (unsigned char)(1 << ( 7 - iBit )); + ucByteVal = (unsigned char)(plv->val[ iByte ] & (~ucBitMask)); + + if ( sVal ) + { + ucByteVal |= ucBitMask; + } + plv->val[ iByte ] = ucByteVal; +} + +/***************************************************************************** + * Function: AddVal + * Description: add val1 to val2 and store in resVal; + * assumes val1 and val2 are of equal length. + * Parameters: plvResVal - ptr to result. + * plvVal1 - ptr of addendum. + * plvVal2 - ptr of addendum. + * Returns: void. + *****************************************************************************/ +void addVal( lenVal* plvResVal, + lenVal* plvVal1, + lenVal* plvVal2 ) +{ + unsigned char ucCarry; + unsigned short usSum; + unsigned short usVal1; + unsigned short usVal2; + short sIndex; + + plvResVal->len = plvVal1->len; /* set up length of result */ + + /* start at least significant bit and add bytes */ + ucCarry = 0; + sIndex = plvVal1->len; + while ( sIndex-- ) + { + usVal1 = plvVal1->val[ sIndex ]; /* i'th byte of val1 */ + usVal2 = plvVal2->val[ sIndex ]; /* i'th byte of val2 */ + + /* add the two bytes plus carry from previous addition */ + usSum = (unsigned short)( usVal1 + usVal2 + ucCarry ); + + /* set up carry for next byte */ + ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 ); + + /* set the i'th byte of the result */ + plvResVal->val[ sIndex ] = (unsigned char)usSum; + } +} + +/***************************************************************************** + * Function: readVal + * Description: read from XSVF numBytes bytes of data into x. + * Parameters: plv - ptr to lenval in which to put the bytes read. + * sNumBytes - the number of bytes to read. + * Returns: void. + *****************************************************************************/ +void readVal( lenVal* plv, + short sNumBytes ) +{ + unsigned char* pucVal; + + plv->len = sNumBytes; /* set the length of the lenVal */ + for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal ) + { + /* read a byte of data into the lenVal */ + readByte( pucVal ); + } +} diff --git a/board/esd/common/xilinx_jtag/lenval.h b/board/esd/common/xilinx_jtag/lenval.h new file mode 100644 index 0000000..6bec4ea --- /dev/null +++ b/board/esd/common/xilinx_jtag/lenval.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*******************************************************/ +/* file: lenval.h */ +/* abstract: This file contains a description of the */ +/* data structure "lenval". */ +/*******************************************************/ + +#ifndef lenval_dot_h +#define lenval_dot_h + +/* the lenVal structure is a byte oriented type used to store an */ +/* arbitrary length binary value. As an example, the hex value */ +/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes */ +/* and val[0]=0e and val[1]=3d. val[2-MAX_LEN] are undefined */ + +/* maximum length (in bytes) of value to read in */ +/* this needs to be at least 4, and longer than the */ +/* length of the longest SDR instruction. If there is, */ +/* only 1 device in the chain, MAX_LEN must be at least */ +/* ceil(27/8) == 4. For 6 devices in a chain, MAX_LEN */ +/* must be 5, for 14 devices MAX_LEN must be 6, for 20 */ +/* devices MAX_LEN must be 7, etc.. */ +/* You can safely set MAX_LEN to a smaller number if you*/ +/* know how many devices will be in your chain. */ +#define MAX_LEN 7000 + + +typedef struct var_len_byte +{ + short len; /* number of chars in this value */ + unsigned char val[MAX_LEN+1]; /* bytes of data */ +} lenVal; + + +/* return the long representation of a lenVal */ +extern long value(lenVal *x); + +/* set lenVal equal to value */ +extern void initLenVal(lenVal *x, long value); + +/* check if expected equals actual (taking the mask into account) */ +extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask); + +/* add val1+val2 and put the result in resVal */ +extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2); + +/* return the (byte, bit) of lv (reading from left to right) */ +extern short RetBit(lenVal *lv, int byte, int bit); + +/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1) + equals "01000000" */ +extern void SetBit(lenVal *lv, int byte, int bit, short val); + +/* read from XSVF numBytes bytes of data into x */ +extern void readVal(lenVal *x, short numBytes); + +#endif diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c new file mode 100644 index 0000000..318f229 --- /dev/null +++ b/board/esd/common/xilinx_jtag/micro.c @@ -0,0 +1,1864 @@ +/* + * (C) Copyright 2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/***************************************************************************** + * file: micro.c + * abstract: This file contains the function, xsvfExecute(), + * call for interpreting the XSVF commands. + * Usage: Call xsvfExecute() to process XSVF data. + * The XSVF data is retrieved by readByte() in ports.c + * Remove the main function if you already have one. + * Options: XSVF_SUPPORT_COMPRESSION + * This define supports the XC9500/XL compression scheme. + * This define adds support for XSDRINC and XSETSDRMASKS. + * XSVF_SUPPORT_ERRORCODES + * This define causes the xsvfExecute function to return + * an error code for specific errors. See error codes below. + * If this is not defined, the return value defaults to the + * legacy values for backward compatibility: + * 1 = success; 0 = failure. + * Debugging: DEBUG_MODE (Legacy name) + * Define DEBUG_MODE to compile with debugging features. + * Both micro.c and ports.c must be compiled with the DEBUG_MODE + * defined to enable the standalone main implementation in + * micro.c that reads XSVF from a file. + * History: v2.00 - Original XSVF implementation. + * v4.04 - Added delay at end of XSIR for XC18v00 support. + * Added new commands for CoolRunner support: + * XSTATE, XENDIR, XENDDR + * v4.05 - Cleanup micro.c but leave ports.c intact. + * v4.06 - Fix xsvfGotoTapState for retry transition. + * v4.07 - Update example waitTime implementations for + * compatibility with Virtex-II. + * v4.10 - Add new XSIR2 command that supports a 2-byte + * IR-length parameter for IR shifts > 255 bits. + * v4.11 - No change. Update version to match SVF2XSVF xlator. + * v4.14 - Added XCOMMENT. + * v5.00 - Improve XSTATE support. + * Added XWAIT. + *****************************************************************************/ + +#include +#include +#include + +#include "micro.h" +#include "lenval.h" +#include "ports.h" + + +extern const unsigned char fpgadata[]; +extern int filesize; + + +/*============================================================================ + * XSVF #define + ============================================================================*/ + +#define XSVF_VERSION "5.00" + +/***************************************************************************** + * Define: XSVF_SUPPORT_COMPRESSION + * Description: Define this to support the XC9500/XL XSVF data compression + * scheme. + * Code size can be reduced by NOT supporting this feature. + * However, you must use the -nc (no compress) option when + * translating SVF to XSVF using the SVF2XSVF translator. + * Corresponding, uncompressed XSVF may be larger. + *****************************************************************************/ +#ifndef XSVF_SUPPORT_COMPRESSION +#define XSVF_SUPPORT_COMPRESSION 1 +#endif + +/***************************************************************************** + * Define: XSVF_SUPPORT_ERRORCODES + * Description: Define this to support the new XSVF error codes. + * (The original XSVF player just returned 1 for success and + * 0 for an unspecified failure.) + *****************************************************************************/ +#ifndef XSVF_SUPPORT_ERRORCODES +#define XSVF_SUPPORT_ERRORCODES 1 +#endif + +#ifdef XSVF_SUPPORT_ERRORCODES +#define XSVF_ERRORCODE(errorCode) errorCode +#else /* Use legacy error code */ +#define XSVF_ERRORCODE(errorCode) ((errorCode==XSVF_ERROR_NONE)?1:0) +#endif /* XSVF_SUPPORT_ERRORCODES */ + + +/*============================================================================ + * DEBUG_MODE #define + ============================================================================*/ +#define DEBUG_MODE + +#ifdef DEBUG_MODE +#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \ + { if ( xsvf_iDebugLevel >= iDebugLevel ) \ + printf( pzFormat ); } +#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \ + { if ( xsvf_iDebugLevel >= iDebugLevel ) \ + printf( pzFormat, arg1 ); } +#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \ + { if ( xsvf_iDebugLevel >= iDebugLevel ) \ + printf( pzFormat, arg1, arg2 ); } +#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \ + { if ( xsvf_iDebugLevel >= iDebugLevel ) \ + printf( pzFormat, arg1, arg2, arg3 ); } +#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \ + { if ( xsvf_iDebugLevel >= iDebugLevel ) \ + xsvfPrintLenVal(plenVal); } +#else /* !DEBUG_MODE */ +#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) +#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) +#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) +#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) +#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) +#endif /* DEBUG_MODE */ + + +/*============================================================================ + * XSVF Type Declarations + ============================================================================*/ + +/***************************************************************************** + * Struct: SXsvfInfo + * Description: This structure contains all of the data used during the + * execution of the XSVF. Some data is persistent, predefined + * information (e.g. lRunTestTime). The bulk of this struct's + * size is due to the lenVal structs (defined in lenval.h) + * which contain buffers for the active shift data. The MAX_LEN + * #define in lenval.h defines the size of these buffers. + * These buffers must be large enough to store the longest + * shift data in your XSVF file. For example: + * MAX_LEN >= ( longest_shift_data_in_bits / 8 ) + * Because the lenVal struct dominates the space usage of this + * struct, the rough size of this struct is: + * sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals) + * xsvfInitialize() contains initialization code for the data + * in this struct. + * xsvfCleanup() contains cleanup code for the data in this + * struct. + *****************************************************************************/ +typedef struct tagSXsvfInfo +{ + /* XSVF status information */ + unsigned char ucComplete; /* 0 = running; 1 = complete */ + unsigned char ucCommand; /* Current XSVF command byte */ + long lCommandCount; /* Number of commands processed */ + int iErrorCode; /* An error code. 0 = no error. */ + + /* TAP state/sequencing information */ + unsigned char ucTapState; /* Current TAP state */ + unsigned char ucEndIR; /* ENDIR TAP state (See SVF) */ + unsigned char ucEndDR; /* ENDDR TAP state (See SVF) */ + + /* RUNTEST information */ + unsigned char ucMaxRepeat; /* Max repeat loops (for xc9500/xl) */ + long lRunTestTime; /* Pre-specified RUNTEST time (usec) */ + + /* Shift Data Info and Buffers */ + long lShiftLengthBits; /* Len. current shift data in bits */ + short sShiftLengthBytes; /* Len. current shift data in bytes */ + + lenVal lvTdi; /* Current TDI shift data */ + lenVal lvTdoExpected; /* Expected TDO shift data */ + lenVal lvTdoCaptured; /* Captured TDO shift data */ + lenVal lvTdoMask; /* TDO mask: 0=dontcare; 1=compare */ + +#ifdef XSVF_SUPPORT_COMPRESSION + /* XSDRINC Data Buffers */ + lenVal lvAddressMask; /* Address mask for XSDRINC */ + lenVal lvDataMask; /* Data mask for XSDRINC */ + lenVal lvNextData; /* Next data for XSDRINC */ +#endif /* XSVF_SUPPORT_COMPRESSION */ +} SXsvfInfo; + +/* Declare pointer to functions that perform XSVF commands */ +typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* ); + +/*============================================================================ + * XSVF Command Bytes + ============================================================================*/ + +/* encodings of xsvf instructions */ +#define XCOMPLETE 0 +#define XTDOMASK 1 +#define XSIR 2 +#define XSDR 3 +#define XRUNTEST 4 +/* Reserved 5 */ +/* Reserved 6 */ +#define XREPEAT 7 +#define XSDRSIZE 8 +#define XSDRTDO 9 +#define XSETSDRMASKS 10 +#define XSDRINC 11 +#define XSDRB 12 +#define XSDRC 13 +#define XSDRE 14 +#define XSDRTDOB 15 +#define XSDRTDOC 16 +#define XSDRTDOE 17 +#define XSTATE 18 /* 4.00 */ +#define XENDIR 19 /* 4.04 */ +#define XENDDR 20 /* 4.04 */ +#define XSIR2 21 /* 4.10 */ +#define XCOMMENT 22 /* 4.14 */ +#define XWAIT 23 /* 5.00 */ +/* Insert new commands here */ +/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */ +#define XLASTCMD 24 /* Last command marker */ + + +/*============================================================================ + * XSVF Command Parameter Values + ============================================================================*/ + +#define XSTATE_RESET 0 /* 4.00 parameter for XSTATE */ +#define XSTATE_RUNTEST 1 /* 4.00 parameter for XSTATE */ + +#define XENDXR_RUNTEST 0 /* 4.04 parameter for XENDIR/DR */ +#define XENDXR_PAUSE 1 /* 4.04 parameter for XENDIR/DR */ + +/* TAP states */ +#define XTAPSTATE_RESET 0x00 +#define XTAPSTATE_RUNTEST 0x01 /* a.k.a. IDLE */ +#define XTAPSTATE_SELECTDR 0x02 +#define XTAPSTATE_CAPTUREDR 0x03 +#define XTAPSTATE_SHIFTDR 0x04 +#define XTAPSTATE_EXIT1DR 0x05 +#define XTAPSTATE_PAUSEDR 0x06 +#define XTAPSTATE_EXIT2DR 0x07 +#define XTAPSTATE_UPDATEDR 0x08 +#define XTAPSTATE_IRSTATES 0x09 /* All IR states begin here */ +#define XTAPSTATE_SELECTIR 0x09 +#define XTAPSTATE_CAPTUREIR 0x0A +#define XTAPSTATE_SHIFTIR 0x0B +#define XTAPSTATE_EXIT1IR 0x0C +#define XTAPSTATE_PAUSEIR 0x0D +#define XTAPSTATE_EXIT2IR 0x0E +#define XTAPSTATE_UPDATEIR 0x0F + +/*============================================================================ + * XSVF Function Prototypes + ============================================================================*/ + +int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ); /* Illegal command function */ +int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo ); +int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSIR( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSDR( SXsvfInfo* pXsvfInfo ); +int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo ); +int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo ); +int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo ); +int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo ); +int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo ); +int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo ); +/* Insert new command functions here */ + +/*============================================================================ + * XSVF Global Variables + ============================================================================*/ + +/* Array of XSVF command functions. Must follow command byte value order! */ +/* If your compiler cannot take this form, then convert to a switch statement*/ +TXsvfDoCmdFuncPtr xsvf_pfDoCmd[] = +{ + xsvfDoXCOMPLETE, /* 0 */ + xsvfDoXTDOMASK, /* 1 */ + xsvfDoXSIR, /* 2 */ + xsvfDoXSDR, /* 3 */ + xsvfDoXRUNTEST, /* 4 */ + xsvfDoIllegalCmd, /* 5 */ + xsvfDoIllegalCmd, /* 6 */ + xsvfDoXREPEAT, /* 7 */ + xsvfDoXSDRSIZE, /* 8 */ + xsvfDoXSDRTDO, /* 9 */ +#ifdef XSVF_SUPPORT_COMPRESSION + xsvfDoXSETSDRMASKS, /* 10 */ + xsvfDoXSDRINC, /* 11 */ +#else + xsvfDoIllegalCmd, /* 10 */ + xsvfDoIllegalCmd, /* 11 */ +#endif /* XSVF_SUPPORT_COMPRESSION */ + xsvfDoXSDRBCE, /* 12 */ + xsvfDoXSDRBCE, /* 13 */ + xsvfDoXSDRBCE, /* 14 */ + xsvfDoXSDRTDOBCE, /* 15 */ + xsvfDoXSDRTDOBCE, /* 16 */ + xsvfDoXSDRTDOBCE, /* 17 */ + xsvfDoXSTATE, /* 18 */ + xsvfDoXENDXR, /* 19 */ + xsvfDoXENDXR, /* 20 */ + xsvfDoXSIR2, /* 21 */ + xsvfDoXCOMMENT, /* 22 */ + xsvfDoXWAIT /* 23 */ +/* Insert new command functions here */ +}; + +#ifdef DEBUG_MODE +char* xsvf_pzCommandName[] = +{ + "XCOMPLETE", + "XTDOMASK", + "XSIR", + "XSDR", + "XRUNTEST", + "Reserved5", + "Reserved6", + "XREPEAT", + "XSDRSIZE", + "XSDRTDO", + "XSETSDRMASKS", + "XSDRINC", + "XSDRB", + "XSDRC", + "XSDRE", + "XSDRTDOB", + "XSDRTDOC", + "XSDRTDOE", + "XSTATE", + "XENDIR", + "XENDDR", + "XSIR2", + "XCOMMENT", + "XWAIT" +}; + +char* xsvf_pzErrorName[] = +{ + "No error", + "ERROR: Unknown", + "ERROR: TDO mismatch", + "ERROR: TDO mismatch and exceeded max retries", + "ERROR: Unsupported XSVF command", + "ERROR: Illegal state specification", + "ERROR: Data overflows allocated MAX_LEN buffer size" +}; + +char* xsvf_pzTapState[] = +{ + "RESET", /* 0x00 */ + "RUNTEST/IDLE", /* 0x01 */ + "DRSELECT", /* 0x02 */ + "DRCAPTURE", /* 0x03 */ + "DRSHIFT", /* 0x04 */ + "DREXIT1", /* 0x05 */ + "DRPAUSE", /* 0x06 */ + "DREXIT2", /* 0x07 */ + "DRUPDATE", /* 0x08 */ + "IRSELECT", /* 0x09 */ + "IRCAPTURE", /* 0x0A */ + "IRSHIFT", /* 0x0B */ + "IREXIT1", /* 0x0C */ + "IRPAUSE", /* 0x0D */ + "IREXIT2", /* 0x0E */ + "IRUPDATE" /* 0x0F */ +}; +#endif /* DEBUG_MODE */ + +/*#ifdef DEBUG_MODE */ +/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */ +int xsvf_iDebugLevel; +/*#endif /XXX* DEBUG_MODE */ + +/*============================================================================ + * Utility Functions + ============================================================================*/ + +/***************************************************************************** + * Function: xsvfPrintLenVal + * Description: Print the lenval value in hex. + * Parameters: plv - ptr to lenval. + * Returns: void. + *****************************************************************************/ +#ifdef DEBUG_MODE +void xsvfPrintLenVal( lenVal *plv ) +{ + int i; + + if ( plv ) + { + printf( "0x" ); + for ( i = 0; i < plv->len; ++i ) + { + printf( "%02x", ((unsigned int)(plv->val[ i ])) ); + } + } +} +#endif /* DEBUG_MODE */ + + +/***************************************************************************** + * Function: xsvfInfoInit + * Description: Initialize the xsvfInfo data. + * Parameters: pXsvfInfo - ptr to the XSVF info structure. + * Returns: int - 0 = success; otherwise error. + *****************************************************************************/ +int xsvfInfoInit( SXsvfInfo* pXsvfInfo ) +{ + XSVFDBG_PRINTF1( 4, " sizeof( SXsvfInfo ) = %d bytes\n", + sizeof( SXsvfInfo ) ); + + pXsvfInfo->ucComplete = 0; + pXsvfInfo->ucCommand = XCOMPLETE; + pXsvfInfo->lCommandCount = 0; + pXsvfInfo->iErrorCode = XSVF_ERROR_NONE; + pXsvfInfo->ucMaxRepeat = 0; + pXsvfInfo->ucTapState = XTAPSTATE_RESET; + pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST; + pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST; + pXsvfInfo->lShiftLengthBits = 0L; + pXsvfInfo->sShiftLengthBytes= 0; + pXsvfInfo->lRunTestTime = 0L; + + return( 0 ); +} + +/***************************************************************************** + * Function: xsvfInfoCleanup + * Description: Cleanup the xsvfInfo data. + * Parameters: pXsvfInfo - ptr to the XSVF info structure. + * Returns: void. + *****************************************************************************/ +void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo ) +{ +} + +/***************************************************************************** + * Function: xsvfGetAsNumBytes + * Description: Calculate the number of bytes the given number of bits + * consumes. + * Parameters: lNumBits - the number of bits. + * Returns: short - the number of bytes to store the number of bits. + *****************************************************************************/ +short xsvfGetAsNumBytes( long lNumBits ) +{ + return( (short)( ( lNumBits + 7L ) / 8L ) ); +} + +/***************************************************************************** + * Function: xsvfTmsTransition + * Description: Apply TMS and transition TAP controller by applying one TCK + * cycle. + * Parameters: sTms - new TMS value. + * Returns: void. + *****************************************************************************/ +void xsvfTmsTransition( short sTms ) +{ + setPort( TMS, sTms ); + setPort( TCK, 0 ); + setPort( TCK, 1 ); +} + +/***************************************************************************** + * Function: xsvfGotoTapState + * Description: From the current TAP state, go to the named TAP state. + * A target state of RESET ALWAYS causes TMS reset sequence. + * All SVF standard stable state paths are supported. + * All state transitions are supported except for the following + * which cause an XSVF_ERROR_ILLEGALSTATE: + * - Target==DREXIT2; Start!=DRPAUSE + * - Target==IREXIT2; Start!=IRPAUSE + * Parameters: pucTapState - Current TAP state; returns final TAP state. + * ucTargetState - New target TAP state. + * Returns: int - 0 = success; otherwise error. + *****************************************************************************/ +int xsvfGotoTapState( unsigned char* pucTapState, + unsigned char ucTargetState ) +{ + int i; + int iErrorCode; + + iErrorCode = XSVF_ERROR_NONE; + if ( ucTargetState == XTAPSTATE_RESET ) + { + /* If RESET, always perform TMS reset sequence to reset/sync TAPs */ + xsvfTmsTransition( 1 ); + for ( i = 0; i < 5; ++i ) + { + setPort( TCK, 0 ); + setPort( TCK, 1 ); + } + *pucTapState = XTAPSTATE_RESET; + XSVFDBG_PRINTF( 3, " TMS Reset Sequence -> Test-Logic-Reset\n" ); + XSVFDBG_PRINTF1( 3, " TAP State = %s\n", + xsvf_pzTapState[ *pucTapState ] ); + } else if ( ( ucTargetState != *pucTapState ) && + ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) || + ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) ) + { + /* Trap illegal TAP state path specification */ + iErrorCode = XSVF_ERROR_ILLEGALSTATE; + } else { + if ( ucTargetState == *pucTapState ) + { + /* Already in target state. Do nothing except when in DRPAUSE + or in IRPAUSE to comply with SVF standard */ + if ( ucTargetState == XTAPSTATE_PAUSEDR ) + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_EXIT2DR; + XSVFDBG_PRINTF1( 3, " TAP State = %s\n", + xsvf_pzTapState[ *pucTapState ] ); + } + else if ( ucTargetState == XTAPSTATE_PAUSEIR ) + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_EXIT2IR; + XSVFDBG_PRINTF1( 3, " TAP State = %s\n", + xsvf_pzTapState[ *pucTapState ] ); + } + } + + /* Perform TAP state transitions to get to the target state */ + while ( ucTargetState != *pucTapState ) + { + switch ( *pucTapState ) + { + case XTAPSTATE_RESET: + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_RUNTEST; + break; + case XTAPSTATE_RUNTEST: + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_SELECTDR; + break; + case XTAPSTATE_SELECTDR: + if ( ucTargetState >= XTAPSTATE_IRSTATES ) + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_SELECTIR; + } + else + { + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_CAPTUREDR; + } + break; + case XTAPSTATE_CAPTUREDR: + if ( ucTargetState == XTAPSTATE_SHIFTDR ) + { + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_SHIFTDR; + } + else + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_EXIT1DR; + } + break; + case XTAPSTATE_SHIFTDR: + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_EXIT1DR; + break; + case XTAPSTATE_EXIT1DR: + if ( ucTargetState == XTAPSTATE_PAUSEDR ) + { + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_PAUSEDR; + } + else + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_UPDATEDR; + } + break; + case XTAPSTATE_PAUSEDR: + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_EXIT2DR; + break; + case XTAPSTATE_EXIT2DR: + if ( ucTargetState == XTAPSTATE_SHIFTDR ) + { + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_SHIFTDR; + } + else + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_UPDATEDR; + } + break; + case XTAPSTATE_UPDATEDR: + if ( ucTargetState == XTAPSTATE_RUNTEST ) + { + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_RUNTEST; + } + else + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_SELECTDR; + } + break; + case XTAPSTATE_SELECTIR: + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_CAPTUREIR; + break; + case XTAPSTATE_CAPTUREIR: + if ( ucTargetState == XTAPSTATE_SHIFTIR ) + { + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_SHIFTIR; + } + else + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_EXIT1IR; + } + break; + case XTAPSTATE_SHIFTIR: + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_EXIT1IR; + break; + case XTAPSTATE_EXIT1IR: + if ( ucTargetState == XTAPSTATE_PAUSEIR ) + { + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_PAUSEIR; + } + else + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_UPDATEIR; + } + break; + case XTAPSTATE_PAUSEIR: + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_EXIT2IR; + break; + case XTAPSTATE_EXIT2IR: + if ( ucTargetState == XTAPSTATE_SHIFTIR ) + { + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_SHIFTIR; + } + else + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_UPDATEIR; + } + break; + case XTAPSTATE_UPDATEIR: + if ( ucTargetState == XTAPSTATE_RUNTEST ) + { + xsvfTmsTransition( 0 ); + *pucTapState = XTAPSTATE_RUNTEST; + } + else + { + xsvfTmsTransition( 1 ); + *pucTapState = XTAPSTATE_SELECTDR; + } + break; + default: + iErrorCode = XSVF_ERROR_ILLEGALSTATE; + *pucTapState = ucTargetState; /* Exit while loop */ + break; + } + XSVFDBG_PRINTF1( 3, " TAP State = %s\n", + xsvf_pzTapState[ *pucTapState ] ); + } + } + + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfShiftOnly + * Description: Assumes that starting TAP state is SHIFT-DR or SHIFT-IR. + * Shift the given TDI data into the JTAG scan chain. + * Optionally, save the TDO data shifted out of the scan chain. + * Last shift cycle is special: capture last TDO, set last TDI, + * but does not pulse TCK. Caller must pulse TCK and optionally + * set TMS=1 to exit shift state. + * Parameters: lNumBits - number of bits to shift. + * plvTdi - ptr to lenval for TDI data. + * plvTdoCaptured - ptr to lenval for storing captured TDO data. + * iExitShift - 1=exit at end of shift; 0=stay in Shift-DR. + * Returns: void. + *****************************************************************************/ +void xsvfShiftOnly( long lNumBits, + lenVal* plvTdi, + lenVal* plvTdoCaptured, + int iExitShift ) +{ + unsigned char* pucTdi; + unsigned char* pucTdo; + unsigned char ucTdiByte; + unsigned char ucTdoByte; + unsigned char ucTdoBit; + int i; + + /* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */ + + /* Initialize TDO storage len == TDI len */ + pucTdo = 0; + if ( plvTdoCaptured ) + { + plvTdoCaptured->len = plvTdi->len; + pucTdo = plvTdoCaptured->val + plvTdi->len; + } + + /* Shift LSB first. val[N-1] == LSB. val[0] == MSB. */ + pucTdi = plvTdi->val + plvTdi->len; + while ( lNumBits ) + { + /* Process on a byte-basis */ + ucTdiByte = (*(--pucTdi)); + ucTdoByte = 0; + for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i ) + { + --lNumBits; + if ( iExitShift && !lNumBits ) + { + /* Exit Shift-DR state */ + setPort( TMS, 1 ); + } + + /* Set the new TDI value */ + setPort( TDI, (short)(ucTdiByte & 1) ); + ucTdiByte >>= 1; + + /* Set TCK low */ + setPort( TCK, 0 ); + + if ( pucTdo ) + { + /* Save the TDO value */ + ucTdoBit = readTDOBit(); + ucTdoByte |= ( ucTdoBit << i ); + } + + /* Set TCK high */ + setPort( TCK, 1 ); + } + + /* Save the TDO byte value */ + if ( pucTdo ) + { + (*(--pucTdo)) = ucTdoByte; + } + } +} + +/***************************************************************************** + * Function: xsvfShift + * Description: Goes to the given starting TAP state. + * Calls xsvfShiftOnly to shift in the given TDI data and + * optionally capture the TDO data. + * Compares the TDO captured data against the TDO expected + * data. + * If a data mismatch occurs, then executes the exception + * handling loop upto ucMaxRepeat times. + * Parameters: pucTapState - Ptr to current TAP state. + * ucStartState - Starting shift state: Shift-DR or Shift-IR. + * lNumBits - number of bits to shift. + * plvTdi - ptr to lenval for TDI data. + * plvTdoCaptured - ptr to lenval for storing TDO data. + * plvTdoExpected - ptr to expected TDO data. + * plvTdoMask - ptr to TDO mask. + * ucEndState - state in which to end the shift. + * lRunTestTime - amount of time to wait after the shift. + * ucMaxRepeat - Maximum number of retries on TDO mismatch. + * Returns: int - 0 = success; otherwise TDO mismatch. + * Notes: XC9500XL-only Optimization: + * Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1] + * is NOT all zeros and sMatch==1. + *****************************************************************************/ +int xsvfShift( unsigned char* pucTapState, + unsigned char ucStartState, + long lNumBits, + lenVal* plvTdi, + lenVal* plvTdoCaptured, + lenVal* plvTdoExpected, + lenVal* plvTdoMask, + unsigned char ucEndState, + long lRunTestTime, + unsigned char ucMaxRepeat ) +{ + int iErrorCode; + int iMismatch; + unsigned char ucRepeat; + int iExitShift; + + iErrorCode = XSVF_ERROR_NONE; + iMismatch = 0; + ucRepeat = 0; + iExitShift = ( ucStartState != ucEndState ); + + XSVFDBG_PRINTF1( 3, " Shift Length = %ld\n", lNumBits ); + XSVFDBG_PRINTF( 4, " TDI = "); + XSVFDBG_PRINTLENVAL( 4, plvTdi ); + XSVFDBG_PRINTF( 4, "\n"); + XSVFDBG_PRINTF( 4, " TDO Expected = "); + XSVFDBG_PRINTLENVAL( 4, plvTdoExpected ); + XSVFDBG_PRINTF( 4, "\n"); + + if ( !lNumBits ) + { + /* Compatibility with XSVF2.00: XSDR 0 = no shift, but wait in RTI */ + if ( lRunTestTime ) + { + /* Wait for prespecified XRUNTEST time */ + xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST ); + XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime ); + waitTime( lRunTestTime ); + } + } + else + { + do + { + /* Goto Shift-DR or Shift-IR */ + xsvfGotoTapState( pucTapState, ucStartState ); + + /* Shift TDI and capture TDO */ + xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift ); + + if ( plvTdoExpected ) + { + /* Compare TDO data to expected TDO data */ + iMismatch = !EqualLenVal( plvTdoExpected, + plvTdoCaptured, + plvTdoMask ); + } + + if ( iExitShift ) + { + /* Update TAP state: Shift->Exit */ + ++(*pucTapState); + XSVFDBG_PRINTF1( 3, " TAP State = %s\n", + xsvf_pzTapState[ *pucTapState ] ); + + if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) ) + { + XSVFDBG_PRINTF( 4, " TDO Expected = "); + XSVFDBG_PRINTLENVAL( 4, plvTdoExpected ); + XSVFDBG_PRINTF( 4, "\n"); + XSVFDBG_PRINTF( 4, " TDO Captured = "); + XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured ); + XSVFDBG_PRINTF( 4, "\n"); + XSVFDBG_PRINTF( 4, " TDO Mask = "); + XSVFDBG_PRINTLENVAL( 4, plvTdoMask ); + XSVFDBG_PRINTF( 4, "\n"); + XSVFDBG_PRINTF1( 3, " Retry #%d\n", ( ucRepeat + 1 ) ); + /* Do exception handling retry - ShiftDR only */ + xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR ); + /* Shift 1 extra bit */ + xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR ); + /* Increment RUNTEST time by an additional 25% */ + lRunTestTime += ( lRunTestTime >> 2 ); + } + else + { + /* Do normal exit from Shift-XR */ + xsvfGotoTapState( pucTapState, ucEndState ); + } + + if ( lRunTestTime ) + { + /* Wait for prespecified XRUNTEST time */ + xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST ); + XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime ); + waitTime( lRunTestTime ); + } + } + } while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) ); + } + + if ( iMismatch ) + { + XSVFDBG_PRINTF( 1, " TDO Expected = "); + XSVFDBG_PRINTLENVAL( 1, plvTdoExpected ); + XSVFDBG_PRINTF( 1, "\n"); + XSVFDBG_PRINTF( 1, " TDO Captured = "); + XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured ); + XSVFDBG_PRINTF( 1, "\n"); + XSVFDBG_PRINTF( 1, " TDO Mask = "); + XSVFDBG_PRINTLENVAL( 1, plvTdoMask ); + XSVFDBG_PRINTF( 1, "\n"); + if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) ) + { + iErrorCode = XSVF_ERROR_MAXRETRIES; + } + else + { + iErrorCode = XSVF_ERROR_TDOMISMATCH; + } + } + + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfBasicXSDRTDO + * Description: Get the XSDRTDO parameters and execute the XSDRTDO command. + * This is the common function for all XSDRTDO commands. + * Parameters: pucTapState - Current TAP state. + * lShiftLengthBits - number of bits to shift. + * sShiftLengthBytes - number of bytes to read. + * plvTdi - ptr to lenval for TDI data. + * lvTdoCaptured - ptr to lenval for storing TDO data. + * iEndState - state in which to end the shift. + * lRunTestTime - amount of time to wait after the shift. + * ucMaxRepeat - maximum xc9500/xl retries. + * Returns: int - 0 = success; otherwise TDO mismatch. + *****************************************************************************/ +int xsvfBasicXSDRTDO( unsigned char* pucTapState, + long lShiftLengthBits, + short sShiftLengthBytes, + lenVal* plvTdi, + lenVal* plvTdoCaptured, + lenVal* plvTdoExpected, + lenVal* plvTdoMask, + unsigned char ucEndState, + long lRunTestTime, + unsigned char ucMaxRepeat ) +{ + readVal( plvTdi, sShiftLengthBytes ); + if ( plvTdoExpected ) + { + readVal( plvTdoExpected, sShiftLengthBytes ); + } + return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits, + plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask, + ucEndState, lRunTestTime, ucMaxRepeat ) ); +} + +/***************************************************************************** + * Function: xsvfDoSDRMasking + * Description: Update the data value with the next XSDRINC data and address. + * Example: dataVal=0x01ff, nextData=0xab, addressMask=0x0100, + * dataMask=0x00ff, should set dataVal to 0x02ab + * Parameters: plvTdi - The current TDI value. + * plvNextData - the next data value. + * plvAddressMask - the address mask. + * plvDataMask - the data mask. + * Returns: void. + *****************************************************************************/ +#ifdef XSVF_SUPPORT_COMPRESSION +void xsvfDoSDRMasking( lenVal* plvTdi, + lenVal* plvNextData, + lenVal* plvAddressMask, + lenVal* plvDataMask ) +{ + int i; + unsigned char ucTdi; + unsigned char ucTdiMask; + unsigned char ucDataMask; + unsigned char ucNextData; + unsigned char ucNextMask; + short sNextData; + + /* add the address Mask to dataVal and return as a new dataVal */ + addVal( plvTdi, plvTdi, plvAddressMask ); + + ucNextData = 0; + ucNextMask = 0; + sNextData = plvNextData->len; + for ( i = plvDataMask->len - 1; i >= 0; --i ) + { + /* Go through data mask in reverse order looking for mask (1) bits */ + ucDataMask = plvDataMask->val[ i ]; + if ( ucDataMask ) + { + /* Retrieve the corresponding TDI byte value */ + ucTdi = plvTdi->val[ i ]; + + /* For each bit in the data mask byte, look for 1's */ + ucTdiMask = 1; + while ( ucDataMask ) + { + if ( ucDataMask & 1 ) + { + if ( !ucNextMask ) + { + /* Get the next data byte */ + ucNextData = plvNextData->val[ --sNextData ]; + ucNextMask = 1; + } + + /* Set or clear the data bit according to the next data */ + if ( ucNextData & ucNextMask ) + { + ucTdi |= ucTdiMask; /* Set bit */ + } + else + { + ucTdi &= ( ~ucTdiMask ); /* Clear bit */ + } + + /* Update the next data */ + ucNextMask <<= 1; + } + ucTdiMask <<= 1; + ucDataMask >>= 1; + } + + /* Update the TDI value */ + plvTdi->val[ i ] = ucTdi; + } + } +} +#endif /* XSVF_SUPPORT_COMPRESSION */ + +/*============================================================================ + * XSVF Command Functions (type = TXsvfDoCmdFuncPtr) + * These functions update pXsvfInfo->iErrorCode only on an error. + * Otherwise, the error code is left alone. + * The function returns the error code from the function. + ============================================================================*/ + +/***************************************************************************** + * Function: xsvfDoIllegalCmd + * Description: Function place holder for illegal/unsupported commands. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ) +{ + XSVFDBG_PRINTF2( 0, "ERROR: Encountered unsupported command #%d (%s)\n", + ((unsigned int)(pXsvfInfo->ucCommand)), + ((pXsvfInfo->ucCommand < XLASTCMD) + ? (xsvf_pzCommandName[pXsvfInfo->ucCommand]) + : "Unknown") ); + pXsvfInfo->iErrorCode = XSVF_ERROR_ILLEGALCMD; + return( pXsvfInfo->iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXCOMPLETE + * Description: XCOMPLETE (no parameters) + * Update complete status for XSVF player. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo ) +{ + pXsvfInfo->ucComplete = 1; + return( XSVF_ERROR_NONE ); +} + +/***************************************************************************** + * Function: xsvfDoXTDOMASK + * Description: XTDOMASK + * Prespecify the TDO compare mask. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo ) +{ + readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes ); + XSVFDBG_PRINTF( 4, " TDO Mask = "); + XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) ); + XSVFDBG_PRINTF( 4, "\n"); + return( XSVF_ERROR_NONE ); +} + +/***************************************************************************** + * Function: xsvfDoXSIR + * Description: XSIR <(byte)shiftlen> + * Get the instruction and shift the instruction into the TAP. + * If prespecified XRUNTEST!=0, goto RUNTEST and wait after + * the shift for XRUNTEST usec. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXSIR( SXsvfInfo* pXsvfInfo ) +{ + unsigned char ucShiftIrBits; + short sShiftIrBytes; + int iErrorCode; + + /* Get the shift length and store */ + readByte( &ucShiftIrBits ); + sShiftIrBytes = xsvfGetAsNumBytes( ucShiftIrBits ); + XSVFDBG_PRINTF1( 3, " XSIR length = %d\n", + ((unsigned int)ucShiftIrBits) ); + + if ( sShiftIrBytes > MAX_LEN ) + { + iErrorCode = XSVF_ERROR_DATAOVERFLOW; + } + else + { + /* Get and store instruction to shift in */ + readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) ); + + /* Shift the data */ + iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR, + ucShiftIrBits, &(pXsvfInfo->lvTdi), + /*plvTdoCaptured*/0, /*plvTdoExpected*/0, + /*plvTdoMask*/0, pXsvfInfo->ucEndIR, + pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 ); + } + + if ( iErrorCode != XSVF_ERROR_NONE ) + { + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXSIR2 + * Description: XSIR <(2-byte)shiftlen> + * Get the instruction and shift the instruction into the TAP. + * If prespecified XRUNTEST!=0, goto RUNTEST and wait after + * the shift for XRUNTEST usec. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo ) +{ + long lShiftIrBits; + short sShiftIrBytes; + int iErrorCode; + + /* Get the shift length and store */ + readVal( &(pXsvfInfo->lvTdi), 2 ); + lShiftIrBits = value( &(pXsvfInfo->lvTdi) ); + sShiftIrBytes = xsvfGetAsNumBytes( lShiftIrBits ); + XSVFDBG_PRINTF1( 3, " XSIR2 length = %d\n", (int)lShiftIrBits); + + if ( sShiftIrBytes > MAX_LEN ) + { + iErrorCode = XSVF_ERROR_DATAOVERFLOW; + } + else + { + /* Get and store instruction to shift in */ + readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) ); + + /* Shift the data */ + iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR, + lShiftIrBits, &(pXsvfInfo->lvTdi), + /*plvTdoCaptured*/0, /*plvTdoExpected*/0, + /*plvTdoMask*/0, pXsvfInfo->ucEndIR, + pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 ); + } + + if ( iErrorCode != XSVF_ERROR_NONE ) + { + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXSDR + * Description: XSDR + * Shift the given TDI data into the JTAG scan chain. + * Compare the captured TDO with the expected TDO from the + * previous XSDRTDO command using the previously specified + * XTDOMASK. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXSDR( SXsvfInfo* pXsvfInfo ) +{ + int iErrorCode; + readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes ); + /* use TDOExpected from last XSDRTDO instruction */ + iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR, + pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi), + &(pXsvfInfo->lvTdoCaptured), + &(pXsvfInfo->lvTdoExpected), + &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR, + pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat ); + if ( iErrorCode != XSVF_ERROR_NONE ) + { + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXRUNTEST + * Description: XRUNTEST + * Prespecify the XRUNTEST wait time for shift operations. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo ) +{ + readVal( &(pXsvfInfo->lvTdi), 4 ); + pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) ); + XSVFDBG_PRINTF1( 3, " XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime ); + return( XSVF_ERROR_NONE ); +} + +/***************************************************************************** + * Function: xsvfDoXREPEAT + * Description: XREPEAT + * Prespecify the maximum number of XC9500/XL retries. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo ) +{ + readByte( &(pXsvfInfo->ucMaxRepeat) ); + XSVFDBG_PRINTF1( 3, " XREPEAT = %d\n", + ((unsigned int)(pXsvfInfo->ucMaxRepeat)) ); + return( XSVF_ERROR_NONE ); +} + +/***************************************************************************** + * Function: xsvfDoXSDRSIZE + * Description: XSDRSIZE + * Prespecify the XRUNTEST wait time for shift operations. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo ) +{ + int iErrorCode; + iErrorCode = XSVF_ERROR_NONE; + readVal( &(pXsvfInfo->lvTdi), 4 ); + pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) ); + pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits ); + XSVFDBG_PRINTF1( 3, " XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits ); + if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN ) + { + iErrorCode = XSVF_ERROR_DATAOVERFLOW; + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXSDRTDO + * Description: XSDRTDO + * Get the TDI and expected TDO values. Then, shift. + * Compare the expected TDO with the captured TDO using the + * prespecified XTDOMASK. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo ) +{ + int iErrorCode; + iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), + pXsvfInfo->lShiftLengthBits, + pXsvfInfo->sShiftLengthBytes, + &(pXsvfInfo->lvTdi), + &(pXsvfInfo->lvTdoCaptured), + &(pXsvfInfo->lvTdoExpected), + &(pXsvfInfo->lvTdoMask), + pXsvfInfo->ucEndDR, + pXsvfInfo->lRunTestTime, + pXsvfInfo->ucMaxRepeat ); + if ( iErrorCode != XSVF_ERROR_NONE ) + { + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXSETSDRMASKS + * Description: XSETSDRMASKS + * + * Get the prespecified address and data mask for the XSDRINC + * command. + * Used for xc9500/xl compressed XSVF data. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +#ifdef XSVF_SUPPORT_COMPRESSION +int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo ) +{ + /* read the addressMask */ + readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes ); + /* read the dataMask */ + readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes ); + + XSVFDBG_PRINTF( 4, " Address Mask = " ); + XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) ); + XSVFDBG_PRINTF( 4, "\n" ); + XSVFDBG_PRINTF( 4, " Data Mask = " ); + XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) ); + XSVFDBG_PRINTF( 4, "\n" ); + + return( XSVF_ERROR_NONE ); +} +#endif /* XSVF_SUPPORT_COMPRESSION */ + +/***************************************************************************** + * Function: xsvfDoXSDRINC + * Description: XSDRINC + * ... + * Get the XSDRINC parameters and execute the XSDRINC command. + * XSDRINC starts by loading the first TDI shift value. + * Then, for numTimes, XSDRINC gets the next piece of data, + * replaces the bits from the starting TDI as defined by the + * XSETSDRMASKS.dataMask, adds the address mask from + * XSETSDRMASKS.addressMask, shifts the new TDI value, + * and compares the TDO to the expected TDO from the previous + * XSDRTDO command using the XTDOMASK. + * Used for xc9500/xl compressed XSVF data. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +#ifdef XSVF_SUPPORT_COMPRESSION +int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo ) +{ + int iErrorCode; + int iDataMaskLen; + unsigned char ucDataMask; + unsigned char ucNumTimes; + unsigned char i; + + readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes ); + iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR, + pXsvfInfo->lShiftLengthBits, + &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured), + &(pXsvfInfo->lvTdoExpected), + &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR, + pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat ); + if ( !iErrorCode ) + { + /* Calculate number of data mask bits */ + iDataMaskLen = 0; + for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i ) + { + ucDataMask = pXsvfInfo->lvDataMask.val[ i ]; + while ( ucDataMask ) + { + iDataMaskLen += ( ucDataMask & 1 ); + ucDataMask >>= 1; + } + } + + /* Get the number of data pieces, i.e. number of times to shift */ + readByte( &ucNumTimes ); + + /* For numTimes, get data, fix TDI, and shift */ + for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i ) + { + readVal( &(pXsvfInfo->lvNextData), + xsvfGetAsNumBytes( iDataMaskLen ) ); + xsvfDoSDRMasking( &(pXsvfInfo->lvTdi), + &(pXsvfInfo->lvNextData), + &(pXsvfInfo->lvAddressMask), + &(pXsvfInfo->lvDataMask) ); + iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), + XTAPSTATE_SHIFTDR, + pXsvfInfo->lShiftLengthBits, + &(pXsvfInfo->lvTdi), + &(pXsvfInfo->lvTdoCaptured), + &(pXsvfInfo->lvTdoExpected), + &(pXsvfInfo->lvTdoMask), + pXsvfInfo->ucEndDR, + pXsvfInfo->lRunTestTime, + pXsvfInfo->ucMaxRepeat ); + } + } + if ( iErrorCode != XSVF_ERROR_NONE ) + { + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} +#endif /* XSVF_SUPPORT_COMPRESSION */ + +/***************************************************************************** + * Function: xsvfDoXSDRBCE + * Description: XSDRB/XSDRC/XSDRE + * If not already in SHIFTDR, goto SHIFTDR. + * Shift the given TDI data into the JTAG scan chain. + * Ignore TDO. + * If cmd==XSDRE, then goto ENDDR. Otherwise, stay in ShiftDR. + * XSDRB, XSDRC, and XSDRE are the same implementation. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo ) +{ + unsigned char ucEndDR; + int iErrorCode; + ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ? + pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR); + iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), + pXsvfInfo->lShiftLengthBits, + pXsvfInfo->sShiftLengthBytes, + &(pXsvfInfo->lvTdi), + /*plvTdoCaptured*/0, /*plvTdoExpected*/0, + /*plvTdoMask*/0, ucEndDR, + /*lRunTestTime*/0, /*ucMaxRepeat*/0 ); + if ( iErrorCode != XSVF_ERROR_NONE ) + { + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXSDRTDOBCE + * Description: XSDRB/XSDRC/XSDRE + * If not already in SHIFTDR, goto SHIFTDR. + * Shift the given TDI data into the JTAG scan chain. + * Compare TDO, but do NOT use XTDOMASK. + * If cmd==XSDRTDOE, then goto ENDDR. Otherwise, stay in ShiftDR. + * XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo ) +{ + unsigned char ucEndDR; + int iErrorCode; + ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ? + pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR); + iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), + pXsvfInfo->lShiftLengthBits, + pXsvfInfo->sShiftLengthBytes, + &(pXsvfInfo->lvTdi), + &(pXsvfInfo->lvTdoCaptured), + &(pXsvfInfo->lvTdoExpected), + /*plvTdoMask*/0, ucEndDR, + /*lRunTestTime*/0, /*ucMaxRepeat*/0 ); + if ( iErrorCode != XSVF_ERROR_NONE ) + { + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXSTATE + * Description: XSTATE + * == XTAPSTATE; + * Get the state parameter and transition the TAP to that state. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo ) +{ + unsigned char ucNextState; + int iErrorCode; + readByte( &ucNextState ); + iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState ); + if ( iErrorCode != XSVF_ERROR_NONE ) + { + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXENDXR + * Description: XENDIR/XENDDR + * : 0 = RUNTEST; 1 = PAUSE. + * Get the prespecified XENDIR or XENDDR. + * Both XENDIR and XENDDR use the same implementation. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo ) +{ + int iErrorCode; + unsigned char ucEndState; + + iErrorCode = XSVF_ERROR_NONE; + readByte( &ucEndState ); + if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) ) + { + iErrorCode = XSVF_ERROR_ILLEGALSTATE; + } + else + { + + if ( pXsvfInfo->ucCommand == XENDIR ) + { + if ( ucEndState == XENDXR_RUNTEST ) + { + pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST; + } + else + { + pXsvfInfo->ucEndIR = XTAPSTATE_PAUSEIR; + } + XSVFDBG_PRINTF1( 3, " ENDIR State = %s\n", + xsvf_pzTapState[ pXsvfInfo->ucEndIR ] ); + } + else /* XENDDR */ + { + if ( ucEndState == XENDXR_RUNTEST ) + { + pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST; + } + else + { + pXsvfInfo->ucEndDR = XTAPSTATE_PAUSEDR; + } + XSVFDBG_PRINTF1( 3, " ENDDR State = %s\n", + xsvf_pzTapState[ pXsvfInfo->ucEndDR ] ); + } + } + + if ( iErrorCode != XSVF_ERROR_NONE ) + { + pXsvfInfo->iErrorCode = iErrorCode; + } + return( iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXCOMMENT + * Description: XCOMMENT + * == text comment; + * Arbitrary comment embedded in the XSVF. + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo ) +{ + /* Use the comment for debugging */ + /* Otherwise, read through the comment to the end '\0' and ignore */ + unsigned char ucText; + + if ( xsvf_iDebugLevel > 0 ) + { + putc( ' ' ); + } + + do + { + readByte( &ucText ); + if ( xsvf_iDebugLevel > 0 ) + { + putc( ucText ? ucText : '\n' ); + } + } while ( ucText ); + + pXsvfInfo->iErrorCode = XSVF_ERROR_NONE; + + return( pXsvfInfo->iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfDoXWAIT + * Description: XWAIT + * If not already in , then go to . + * Wait in for microseconds. + * Finally, if not already in , then goto . + * Parameters: pXsvfInfo - XSVF information pointer. + * Returns: int - 0 = success; non-zero = error. + *****************************************************************************/ +int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo ) +{ + unsigned char ucWaitState; + unsigned char ucEndState; + long lWaitTime; + + /* Get Parameters */ + /* */ + readVal( &(pXsvfInfo->lvTdi), 1 ); + ucWaitState = pXsvfInfo->lvTdi.val[0]; + + /* */ + readVal( &(pXsvfInfo->lvTdi), 1 ); + ucEndState = pXsvfInfo->lvTdi.val[0]; + + /* */ + readVal( &(pXsvfInfo->lvTdi), 4 ); + lWaitTime = value( &(pXsvfInfo->lvTdi) ); + XSVFDBG_PRINTF2( 3, " XWAIT: state = %s; time = %ld\n", + xsvf_pzTapState[ ucWaitState ], lWaitTime ); + + /* If not already in , go to */ + if ( pXsvfInfo->ucTapState != ucWaitState ) + { + xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState ); + } + + /* Wait for microseconds */ + waitTime( lWaitTime ); + + /* If not already in , go to */ + if ( pXsvfInfo->ucTapState != ucEndState ) + { + xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState ); + } + + return( XSVF_ERROR_NONE ); +} + + +/*============================================================================ + * Execution Control Functions + ============================================================================*/ + +/***************************************************************************** + * Function: xsvfInitialize + * Description: Initialize the xsvf player. + * Call this before running the player to initialize the data + * in the SXsvfInfo struct. + * xsvfCleanup is called to clean up the data in SXsvfInfo + * after the XSVF is played. + * Parameters: pXsvfInfo - ptr to the XSVF information. + * Returns: int - 0 = success; otherwise error. + *****************************************************************************/ +int xsvfInitialize( SXsvfInfo* pXsvfInfo ) +{ + /* Initialize values */ + pXsvfInfo->iErrorCode = xsvfInfoInit( pXsvfInfo ); + + if ( !pXsvfInfo->iErrorCode ) + { + /* Initialize the TAPs */ + pXsvfInfo->iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), + XTAPSTATE_RESET ); + } + + return( pXsvfInfo->iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfRun + * Description: Run the xsvf player for a single command and return. + * First, call xsvfInitialize. + * Then, repeatedly call this function until an error is detected + * or until the pXsvfInfo->ucComplete variable is non-zero. + * Finally, call xsvfCleanup to cleanup any remnants. + * Parameters: pXsvfInfo - ptr to the XSVF information. + * Returns: int - 0 = success; otherwise error. + *****************************************************************************/ +int xsvfRun( SXsvfInfo* pXsvfInfo ) +{ + /* Process the XSVF commands */ + if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) ) + { + /* read 1 byte for the instruction */ + readByte( &(pXsvfInfo->ucCommand) ); + ++(pXsvfInfo->lCommandCount); + + if ( pXsvfInfo->ucCommand < XLASTCMD ) + { + /* Execute the command. Func sets error code. */ + XSVFDBG_PRINTF1( 2, " %s\n", + xsvf_pzCommandName[pXsvfInfo->ucCommand] ); + /* If your compiler cannot take this form, + then convert to a switch statement */ +#if 0 /* test-only */ + xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo ); +#else + switch (pXsvfInfo->ucCommand) { + case 0: + xsvfDoXCOMPLETE(pXsvfInfo); /* 0 */ + break; + case 1: + xsvfDoXTDOMASK(pXsvfInfo); /* 1 */ + break; + case 2: + xsvfDoXSIR(pXsvfInfo); /* 2 */ + break; + case 3: + xsvfDoXSDR(pXsvfInfo); /* 3 */ + break; + case 4: + xsvfDoXRUNTEST(pXsvfInfo); /* 4 */ + break; + case 5: + xsvfDoIllegalCmd(pXsvfInfo); /* 5 */ + break; + case 6: + xsvfDoIllegalCmd(pXsvfInfo); /* 6 */ + break; + case 7: + xsvfDoXREPEAT(pXsvfInfo); /* 7 */ + break; + case 8: + xsvfDoXSDRSIZE(pXsvfInfo); /* 8 */ + break; + case 9: + xsvfDoXSDRTDO(pXsvfInfo); /* 9 */ + break; +#ifdef XSVF_SUPPORT_COMPRESSION + case 10: + xsvfDoXSETSDRMASKS(pXsvfInfo); /* 10 */ + break; + case 11: + xsvfDoXSDRINC(pXsvfInfo); /* 11 */ + break; +#else + case 10: + xsvfDoIllegalCmd(pXsvfInfo); /* 10 */ + break; + case 11: + xsvfDoIllegalCmd(pXsvfInfo); /* 11 */ + break; +#endif /* XSVF_SUPPORT_COMPRESSION */ + case 12: + xsvfDoXSDRBCE(pXsvfInfo); /* 12 */ + break; + case 13: + xsvfDoXSDRBCE(pXsvfInfo); /* 13 */ + break; + case 14: + xsvfDoXSDRBCE(pXsvfInfo); /* 14 */ + break; + case 15: + xsvfDoXSDRTDOBCE(pXsvfInfo); /* 15 */ + break; + case 16: + xsvfDoXSDRTDOBCE(pXsvfInfo); /* 16 */ + break; + case 17: + xsvfDoXSDRTDOBCE(pXsvfInfo); /* 17 */ + break; + case 18: + xsvfDoXSTATE(pXsvfInfo); /* 18 */ + break; + case 19: + xsvfDoXENDXR(pXsvfInfo); /* 19 */ + break; + case 20: + xsvfDoXENDXR(pXsvfInfo); /* 20 */ + break; + case 21: + xsvfDoXSIR2(pXsvfInfo); /* 21 */ + break; + case 22: + xsvfDoXCOMMENT(pXsvfInfo); /* 22 */ + break; + case 23: + xsvfDoXWAIT(pXsvfInfo); /* 23 */ + break; + } +#endif + } + else + { + /* Illegal command value. Func sets error code. */ + xsvfDoIllegalCmd( pXsvfInfo ); + } + } + + return( pXsvfInfo->iErrorCode ); +} + +/***************************************************************************** + * Function: xsvfCleanup + * Description: cleanup remnants of the xsvf player. + * Parameters: pXsvfInfo - ptr to the XSVF information. + * Returns: void. + *****************************************************************************/ +void xsvfCleanup( SXsvfInfo* pXsvfInfo ) +{ + xsvfInfoCleanup( pXsvfInfo ); +} + + +/*============================================================================ + * xsvfExecute() - The primary entry point to the XSVF player + ============================================================================*/ + +/***************************************************************************** + * Function: xsvfExecute + * Description: Process, interpret, and apply the XSVF commands. + * See port.c:readByte for source of XSVF data. + * Parameters: none. + * Returns: int - Legacy result values: 1 == success; 0 == failed. + *****************************************************************************/ +int xsvfExecute(void) +{ + SXsvfInfo xsvfInfo; + + xsvfInitialize( &xsvfInfo ); + + while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) ) + { + xsvfRun( &xsvfInfo ); + } + + if ( xsvfInfo.iErrorCode ) + { + XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[ + ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST ) + ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] ); + XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld. See line #%ld in the XSVF ASCII file.\n", + xsvfInfo.lCommandCount, xsvfInfo.lCommandCount ); + } + else + { + XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" ); + } + + xsvfCleanup( &xsvfInfo ); + + return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) ); +} + + +/***************************************************************************** + * Function: do_cpld + * Description: main function. + * Specified here for creating stand-alone debug executable. + * Embedded users should call xsvfExecute() directly. + * Parameters: iArgc - number of command-line arguments. + * ppzArgv - array of ptrs to strings (command-line arguments). + * Returns: int - Legacy return value: 1 = success; 0 = error. + *****************************************************************************/ +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int iErrorCode; + char* pzXsvfFileName; + unsigned long duration; + unsigned long long startClock, endClock; + + iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE ); + pzXsvfFileName = 0; + xsvf_iDebugLevel = 0; + + printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION); + printf("XSVF Filesize = %d bytes\n", filesize); + + /* Initialize the I/O. SetPort initializes I/O on first call */ + setPort( TMS, 1 ); + + /* Execute the XSVF in the file */ + startClock = get_ticks(); + iErrorCode = xsvfExecute(); + endClock = get_ticks(); + duration = (unsigned long)(endClock - startClock); + printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk())); + + return( iErrorCode ); +} +U_BOOT_CMD( + cpld, 1, 1, do_cpld, + "cpld - Program onboard CPLD\n", + NULL + ); diff --git a/board/esd/common/xilinx_jtag/micro.h b/board/esd/common/xilinx_jtag/micro.h new file mode 100644 index 0000000..3c463ab --- /dev/null +++ b/board/esd/common/xilinx_jtag/micro.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/***************************************************************************** + * File: micro.h + * Description: This header file contains the function prototype to the + * primary interface function for the XSVF player. + * Usage: FIRST - PORTS.C + * Customize the ports.c function implementations to establish + * the correct protocol for communicating with your JTAG ports + * (setPort() and readTDOBit()) and tune the waitTime() delay + * function. Also, establish access to the XSVF data source + * in the readByte() function. + * FINALLY - Call xsvfExecute(). + *****************************************************************************/ +#ifndef XSVF_MICRO_H +#define XSVF_MICRO_H + +/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */ +#define XSVF_LEGACY_SUCCESS 1 +#define XSVF_LEGACY_ERROR 0 + +/* 4.04 [NEW] Error codes for xsvfExecute. */ +/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */ +#define XSVF_ERROR_NONE 0 +#define XSVF_ERROR_UNKNOWN 1 +#define XSVF_ERROR_TDOMISMATCH 2 +#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */ +#define XSVF_ERROR_ILLEGALCMD 4 +#define XSVF_ERROR_ILLEGALSTATE 5 +#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/ +/* Insert new errors here */ +#define XSVF_ERROR_LAST 7 + +/***************************************************************************** + * Function: xsvfExecute + * Description: Process, interpret, and apply the XSVF commands. + * See port.c:readByte for source of XSVF data. + * Parameters: none. + * Returns: int - For error codes see above. + *****************************************************************************/ +int xsvfExecute(void); + +#endif /* XSVF_MICRO_H */ diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c new file mode 100644 index 0000000..3ad94a5 --- /dev/null +++ b/board/esd/common/xilinx_jtag/ports.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*******************************************************/ +/* file: ports.c */ +/* abstract: This file contains the routines to */ +/* output values on the JTAG ports, to read */ +/* the TDO bit, and to read a byte of data */ +/* from the prom */ +/* */ +/*******************************************************/ + +#include +#include + +#include "ports.h" + +static unsigned long output = 0; +static int filepos = 0; +static int oldstate = 0; +static int newstate = 0; +static int readptr = 0; + +extern long filesize; +extern const unsigned char fpgadata[]; + + +/* if in debugging mode, then just set the variables */ +void setPort(short p,short val) +{ + if (p==TMS) { + if (val) { + output |= JTAG_TMS; + } else { + output &= ~JTAG_TMS; + } + } + if (p==TDI) { + if (val) { + output |= JTAG_TDI; + } else { + output &= ~JTAG_TDI; + } + } + if (p==TCK) { + if (val) { + output |= JTAG_TCK; + } else { + output &= ~JTAG_TCK; + } + out32(GPIO0_OR, output); + } +} + + +/* toggle tck LH */ +void pulseClock(void) +{ + setPort(TCK,0); /* set the TCK port to low */ + setPort(TCK,1); /* set the TCK port to high */ +} + + +/* read in a byte of data from the prom */ +void readByte(unsigned char *data) +{ + /* pretend reading using a file */ + *data = fpgadata[readptr++]; + newstate = (100 * filepos++) / filesize; + if (newstate != oldstate) { + printf("%4d\r\r\r\r", newstate); + oldstate = newstate; + } +} + +/* read the TDO bit from port */ +unsigned char readTDOBit(void) +{ + unsigned long inputs; + + inputs = in32(GPIO0_IR); + if (inputs & JTAG_TDO) + return 1; + else + return 0; +} + + +/* Wait at least the specified number of microsec. */ +/* Use a timer if possible; otherwise estimate the number of instructions */ +/* necessary to be run based on the microcontroller speed. For this example */ +/* we pulse the TCK port a number of times based on the processor speed. */ +void waitTime(long microsec) +{ + udelay(microsec); /* esd */ +} diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h new file mode 100644 index 0000000..0e38990 --- /dev/null +++ b/board/esd/common/xilinx_jtag/ports.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*******************************************************/ +/* file: ports.h */ +/* abstract: This file contains extern declarations */ +/* for providing stimulus to the JTAG ports.*/ +/*******************************************************/ + +#ifndef ports_dot_h +#define ports_dot_h + +/* these constants are used to send the appropriate ports to setPort */ +/* they should be enumerated types, but some of the microcontroller */ +/* compilers don't like enumerated types */ +#define TCK (short) 0 +#define TMS (short) 1 +#define TDI (short) 2 + +/* + * Use CFG_FPGA_xxx defines from board include file. + */ +#define JTAG_TMS CFG_FPGA_PRG /* output */ +#define JTAG_TCK CFG_FPGA_CLK /* output */ +#define JTAG_TDI CFG_FPGA_DATA /* output */ +#define JTAG_TDO CFG_FPGA_DONE /* input */ + +/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */ +void setPort(short p, short val); + +/* read the TDO bit and store it in val */ +unsigned char readTDOBit(void); + +/* make clock go down->up->down*/ +void pulseClock(void); + +/* read the next byte of data from the xsvf file */ +void readByte(unsigned char *data); + +void waitTime(long microsec); + +#endif diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile new file mode 100644 index 0000000..a60495a --- /dev/null +++ b/board/esd/cpci2dp/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/cpci2dp/config.mk b/board/esd/cpci2dp/config.mk new file mode 100644 index 0000000..2da4c9f --- /dev/null +++ b/board/esd/cpci2dp/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd CPCI2DP board +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c new file mode 100644 index 0000000..df10c0e --- /dev/null +++ b/board/esd/cpci2dp/cpci2dp.c @@ -0,0 +1,214 @@ +/* + * (C) Copyright 2005 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +int board_early_init_f (void) +{ + unsigned long cntrl0Reg; + + /* + * Setup GPIO pins (CS4+CS7 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00900000); + + /* set output pins to high */ + out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED); + /* INTA# is open drain */ + out32(GPIO0_ODR, CFG_INTA_FAKE); + /* setup for output */ + out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) unused + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long cntrl0Reg; + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Select cts (and not dsr) on uart1 + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00001000); + + return (0); +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming CPCI2DP"); + } else { + puts(str); + } + + printf(" (Ver 1.0)"); + + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 64 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +#if defined(CFG_EEPROM_WREN) +/* Input: I2C address of EEPROM device to enable. + * -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if was -1. + */ +int eeprom_write_enable (unsigned dev_addr, int state) { + if (CFG_I2C_EEPROM_ADDR != dev_addr) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + break; + } + } + return state; +} +#endif + +#if defined(CFG_EEPROM_WREN) +int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int query = argc == 1; + int state = 0; + + if (query) { + /* Query write access state. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + if (state < 0) { + puts ("Query of write access state failed.\n"); + } else { + printf ("Write access for device 0x%0x is %sabled.\n", + CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + state = 0; + } + } else { + if ('0' == argv[1][0]) { + /* Disable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + } else { + /* Enable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + } + if (state < 0) { + puts ("Setup of write access state failed.\n"); + } + } + + return state; +} + +U_BOOT_CMD( + eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL + ); +#endif /* #if defined(CFG_EEPROM_WREN) */ diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c new file mode 100644 index 0000000..de847f9 --- /dev/null +++ b/board/esd/cpci2dp/flash.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile new file mode 100644 index 0000000..9340a32 --- /dev/null +++ b/board/esd/cpci405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk new file mode 100644 index 0000000..0be45c7 --- /dev/null +++ b/board/esd/cpci405/config.mk @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd CPCI405 boards +# + +ifeq ($(BOARD_REVISION),CPCI4052) +TEXT_BASE = 0xFFFC0000 +else +ifeq ($(BOARD_REVISION),CPCI405DT) +TEXT_BASE = 0xFFFC0000 +else +ifeq ($(BOARD_REVISION),CPCI405AB) +TEXT_BASE = 0xFFFC0000 +else +TEXT_BASE = 0xFFFD0000 +endif +endif +endif diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c new file mode 100644 index 0000000..2ab9673 --- /dev/null +++ b/board/esd/cpci405/cpci405.c @@ -0,0 +1,799 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ +#if 0 +#define FPGA_DEBUG +#endif + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = +{ +#ifdef CONFIG_CPCI405_VER2 +# ifdef CONFIG_CPCI405AB +# include "fpgadata_cpci405ab.c" +# else +# include "fpgadata_cpci4052.c" +# endif +#else +# include "fpgadata_cpci405.c" +#endif +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +#include "../common/auto_update.h" + +#ifdef CONFIG_CPCI405AB +au_image_t au_image[] = { + {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT}, + {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR}, + {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, + {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, + {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT}, +}; +#else +#ifdef CONFIG_CPCI405_VER2 +au_image_t au_image[] = { + {"cpci4052/preinst.img", 0, -1, AU_SCRIPT}, + {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR}, + {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, + {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, + {"cpci4052/postinst.img", 0, 0, AU_SCRIPT}, +}; +#else +au_image_t au_image[] = { + {"cpci405/preinst.img", 0, -1, AU_SCRIPT}, + {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR}, + {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR}, + {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE}, + {"cpci405/postinst.img", 0, 0, AU_SCRIPT}, +}; +#endif +#endif + +int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); + + +/* Prototypes */ +int cpci405_version(void); +int gunzip(void *, int, unsigned char *, unsigned long *); +void lxt971_no_sleep(void); + + +int board_early_init_f (void) +{ +#ifndef CONFIG_CPCI405_VER2 + int index, len, i; + int status; +#endif + +#ifdef FPGA_DEBUG + DECLARE_GLOBAL_DATA_PTR; + + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f(); +#endif + + /* + * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) + */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ + out32(GPIO0_OR, 0); /* pull prg low */ + + /* + * Boot onboard FPGA + */ +#ifndef CONFIG_CPCI405_VER2 + if (cpci405_version() == 1) { + status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata)); + if (status != 0) { + /* booting FPGA failed */ +#ifndef FPGA_DEBUG + DECLARE_GLOBAL_DATA_PTR; + + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f(); +#endif + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = fpgadata[index]; + printf("FPGA: %s\n", &(fpgadata[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + } +#endif /* !CONFIG_CPCI405_VER2 */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + if (cpci405_version() == 3) { + mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ + } else { + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + } + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int ctermm2(void) +{ +#ifdef CONFIG_CPCI405_VER2 + return 0; /* no, board is cpci405 */ +#else + if ((*(unsigned char *)0xf0000400 == 0x00) && + (*(unsigned char *)0xf0000401 == 0x01)) + return 0; /* no, board is cpci405 */ + else + return -1; /* yes, board is cterm-m2 */ +#endif +} + + +int cpci405_host(void) +{ + if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + return -1; /* yes, board is cpci405 host */ + else + return 0; /* no, board is cpci405 adapter */ +} + + +int cpci405_version(void) +{ + unsigned long cntrl0Reg; + unsigned long value; + + /* + * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x03000000); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ + + /* + * Restore GPIO settings + */ + mtdcr(cntrl0, cntrl0Reg); + + switch (value) { + case 0x00180000: + /* CS2==1 && CS3==1 -> version 1 */ + return 1; + case 0x00080000: + /* CS2==0 && CS3==1 -> version 2 */ + return 2; + case 0x00100000: + /* CS2==1 && CS3==0 -> version 3 */ + return 3; + case 0x00000000: + /* CS2==0 && CS3==0 -> version 4 */ + return 4; + default: + /* should not be reached! */ + return 2; + } +} + + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long cntrl0Reg; + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + +#ifdef CONFIG_CPCI405_VER2 + { + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + + /* + * On CPCI-405 version 2 the environment is saved in eeprom! + * FPGA can be gzip compressed (malloc) and booted this late. + */ + + if (cpci405_version() >= 2) { + /* + * Setup GPIO pins (CS6+CS7 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00300000); + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + /* restore gpio/cs settings */ + mtdcr(cntrl0, cntrl0Reg); + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); + + /* + * Reset FPGA via FPGA_DATA pin + */ + SET_FPGA(FPGA_PRG | FPGA_CLK); + udelay(1000); /* wait 1ms */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); + udelay(1000); /* wait 1ms */ + + if (cpci405_version() == 3) { + volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; + volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR; + + /* + * Enable outputs in fpga on version 3 board + */ + *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT; + + /* + * Set outputs to 0 + */ + *leds = 0x00; + + /* + * Reset external DUART + */ + *fpga_mode |= CFG_FPGA_MODE_DUART_RESET; + udelay(100); + *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET); + } + } + else { + puts("\n*** U-Boot Version does not match Board Version!\n"); + puts("*** CPCI-405 Version 1.x detected!\n"); + puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n"); + } + } + +#else /* CONFIG_CPCI405_VER2 */ + +#if 0 /* test-only: code-plug now not relavant for ip-address any more */ + /* + * Generate last byte of ip-addr from code-plug @ 0xf0000400 + */ + if (ctermm2()) { + char str[32]; + unsigned char ipbyte = *(unsigned char *)0xf0000400; + + /* + * Only overwrite ip-addr with allowed values + */ + if ((ipbyte != 0x00) && (ipbyte != 0xff)) { + bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte; + sprintf(str, "%ld.%ld.%ld.%ld", + (bd->bi_ip_addr & 0xff000000) >> 24, + (bd->bi_ip_addr & 0x00ff0000) >> 16, + (bd->bi_ip_addr & 0x0000ff00) >> 8, + (bd->bi_ip_addr & 0x000000ff)); + setenv("ipaddr", str); + } + } +#endif + + if (cpci405_version() >= 2) { + puts("\n*** U-Boot Version does not match Board Version!\n"); + puts("*** CPCI-405 Board Version 2.x detected!\n"); + puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n"); + } + +#endif /* CONFIG_CPCI405_VER2 */ + + /* + * Select cts (and not dsr) on uart1 + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00001000); + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ +#ifndef CONFIG_CPCI405_VER2 + int index; + int len; +#endif + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + unsigned short ver; + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming CPCI405"); + } else { + puts(str); + } + + ver = cpci405_version(); + printf(" (Ver %d.x, ", ver); + +#if 0 /* test-only */ + if (ver >= 2) { + volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1; + + if (*fpga_status & CFG_FPGA_STATUS_FLASH) { + puts ("FLASH Bank B, "); + } else { + puts ("FLASH Bank A, "); + } + } +#endif + + if (ctermm2()) { + char str[4]; + + /* + * Read board-id and save in env-variable + */ + sprintf(str, "%d", *(unsigned char *)0xf0000400); + setenv("boardid", str); + printf("CTERM-M2 - Id=%s)", str); + } else { + if (cpci405_host()) { + puts ("PCI Host Version)"); + } else { + puts ("PCI Adapter Version)"); + } + } + +#ifndef CONFIG_CPCI405_VER2 + puts ("\nFPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = fpgadata[index]; + printf("%s ", &(fpgadata[index+1])); + index += len+3; + } +#endif + + putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_CPCI405_VER2 +#ifdef CONFIG_IDE_RESET + +void ide_set_reset(int on) +{ + volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; + + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { /* assert RESET */ + *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET); + } else { /* release RESET */ + *fpga_mode |= CFG_FPGA_MODE_CF_RESET; + } +} + +#endif /* CONFIG_IDE_RESET */ +#endif /* CONFIG_CPCI405_VER2 */ + + +#ifdef CONFIG_CPCI405AB + +#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ + |= CFG_FPGA_MODE_1WIRE_DIR) +#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ + &= ~CFG_FPGA_MODE_1WIRE_DIR) +#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ + & CFG_FPGA_MODE_1WIRE) + +/* + * Generate a 1-wire reset, return 1 if no presence detect was found, + * return 0 otherwise. + * (NOTE: Does not handle alarm presence from DS2404/DS1994) + */ +int OWTouchReset(void) +{ + int result; + + ONE_WIRE_CLEAR; + udelay(480); + ONE_WIRE_SET; + udelay(70); + + result = ONE_WIRE_GET; + + udelay(410); + return result; +} + + +/* + * Send 1 a 1-wire write bit. + * Provide 10us recovery time. + */ +void OWWriteBit(int bit) +{ + if (bit) { + /* + * write '1' bit + */ + ONE_WIRE_CLEAR; + udelay(6); + ONE_WIRE_SET; + udelay(64); + } else { + /* + * write '0' bit + */ + ONE_WIRE_CLEAR; + udelay(60); + ONE_WIRE_SET; + udelay(10); + } +} + + +/* + * Read a bit from the 1-wire bus and return it. + * Provide 10us recovery time. + */ +int OWReadBit(void) +{ + int result; + + ONE_WIRE_CLEAR; + udelay(6); + ONE_WIRE_SET; + udelay(9); + + result = ONE_WIRE_GET; + + udelay(55); + return result; +} + + +void OWWriteByte(int data) +{ + int loop; + + for (loop=0; loop<8; loop++) { + OWWriteBit(data & 0x01); + data >>= 1; + } +} + + +int OWReadByte(void) +{ + int loop, result = 0; + + for (loop=0; loop<8; loop++) { + result >>= 1; + if (OWReadBit()) { + result |= 0x80; + } + } + + return result; +} + + +int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile unsigned short val; + int result; + int i; + unsigned char ow_id[6]; + char str[32]; + unsigned char ow_crc; + + /* + * Clear 1-wire bit (open drain with pull-up) + */ + val = *(volatile unsigned short *)0xf0400000; + val &= ~0x1000; /* clear 1-wire bit */ + *(volatile unsigned short *)0xf0400000 = val; + + result = OWTouchReset(); + if (result != 0) { + puts("No 1-wire device detected!\n"); + } + + OWWriteByte(0x33); /* send read rom command */ + OWReadByte(); /* skip family code ( == 0x01) */ + for (i=0; i<6; i++) { + ow_id[i] = OWReadByte(); + } + ow_crc = OWReadByte(); /* read crc */ + + sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]); + printf("Setting environment variable 'ow_id' to %s\n", str); + setenv("ow_id", str); + + return 0; +} +U_BOOT_CMD( + onewire, 1, 1, do_onewire, + "onewire - Read 1-write ID\n", + NULL + ); + + +#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ +#define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ + +/* + * Write backplane ip-address... + */ +int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd = gd->bd; + char *buf; + ulong crc; + char str[32]; + char *ptr; + IPaddr_t ipaddr; + + buf = malloc(CFG_ENV_SIZE_2); + if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) { + puts("\nError reading backplane EEPROM!\n"); + } else { + crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4); + if (crc != *(ulong *)buf) { + printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf); + return -1; + } + + /* + * Find bp_ip + */ + ptr = strstr(buf+4, "bp_ip="); + if (ptr == NULL) { + printf("ERROR: bp_ip not found!\n"); + return -1; + } + ptr += 6; + ipaddr = string_to_ip(ptr); + + /* + * Update whole ip-addr + */ + bd->bi_ip_addr = ipaddr; + sprintf(str, "%ld.%ld.%ld.%ld", + (bd->bi_ip_addr & 0xff000000) >> 24, + (bd->bi_ip_addr & 0x00ff0000) >> 16, + (bd->bi_ip_addr & 0x0000ff00) >> 8, + (bd->bi_ip_addr & 0x000000ff)); + setenv("ipaddr", str); + printf("Updated ip_addr from bp_eeprom to %s!\n", str); + } + + free(buf); + + return 0; +} +U_BOOT_CMD( + getbpip, 1, 1, do_get_bpip, + "getbpip - Update IP-Address with Backplane IP-Address\n", + NULL + ); + +/* + * Set and print backplane ip... + */ +int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *buf; + char str[32]; + ulong crc; + + if (argc < 2) { + puts("ERROR!\n"); + return -1; + } + + printf("Setting bp_ip to %s\n", argv[1]); + buf = malloc(CFG_ENV_SIZE_2); + memset(buf, 0, CFG_ENV_SIZE_2); + sprintf(str, "bp_ip=%s", argv[1]); + strcpy(buf+4, str); + crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4); + *(ulong *)buf = crc; + + if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) { + puts("\nError writing backplane EEPROM!\n"); + } + + free(buf); + + return 0; +} +U_BOOT_CMD( + setbpip, 2, 1, do_set_bpip, + "setbpip - Write Backplane IP-Address\n", + NULL + ); + +#endif /* CONFIG_CPCI405AB */ diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c new file mode 100644 index 0000000..e766895 --- /dev/null +++ b/board/esd/cpci405/flash.c @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long calc_size(unsigned long size) +{ + switch (size) { + case 1 << 20: + return 0; + case 2 << 20: + return 1; + case 4 << 20: + return 2; + case 8 << 20: + return 3; + case 16 << 20: + return 4; + default: + return 0; + } +} + + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + base_b0 = FLASH_BASE0_PRELIM; + size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + base_b1 = FLASH_BASE1_PRELIM; + size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); + + /* Re-do sizing to get full correct info */ + + if (size_b1) { + if (size_b1 < (1 << 20)) { + /* minimum CS size on PPC405GP is 1MB !!! */ + size_b1 = 1 << 20; + } + base_b1 = -size_b1; + mtdcr (ebccfga, pb0cr); + pbcr = mfdcr (ebccfgd); + mtdcr (ebccfga, pb0cr); + pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17); + mtdcr (ebccfgd, pbcr); +#if 0 /* test-only */ + printf("size_b1=%x base_b1=%x pb1cr = %x\n", + size_b1, base_b1, pbcr); /* test-only */ +#endif + } + + if (size_b0) { + if (size_b0 < (1 << 20)) { + /* minimum CS size on PPC405GP is 1MB !!! */ + size_b0 = 1 << 20; + } + base_b0 = base_b1 - size_b0; + mtdcr (ebccfga, pb1cr); + pbcr = mfdcr (ebccfgd); + mtdcr (ebccfga, pb1cr); + pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17); + mtdcr (ebccfgd, pbcr); +#if 0 /* test-only */ + printf("size_b0=%x base_b0=%x pb0cr = %x\n", + size_b0, base_b0, pbcr); /* test-only */ +#endif + } + + size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); + + flash_get_offsets (base_b0, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); + + flash_get_offsets (base_b1, &flash_info[1]); + + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + base_b1 + size_b1 - monitor_flash_len, + base_b1 + size_b1 - 1, &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + flash_protect (FLAG_PROTECT_CLEAR, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} diff --git a/board/esd/cpci405/fpgadata_cpci405.c b/board/esd/cpci405/fpgadata_cpci405.c new file mode 100644 index 0000000..20e61c1 --- /dev/null +++ b/board/esd/cpci405/fpgadata_cpci405.c @@ -0,0 +1,342 @@ + 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d, + 0x63,0x70,0x63,0x69,0x34,0x30,0x35,0x32,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b, + 0x73,0x30,0x35,0x78,0x6c,0x76,0x71,0x31,0x30,0x30,0x00,0x63,0x00,0x0b,0x32,0x30, + 0x30,0x31,0x2f,0x30,0x35,0x2f,0x31,0x30,0x00,0x64,0x00,0x09,0x31,0x35,0x3a,0x31, + 0x35,0x3a,0x32,0x33,0x00,0x65,0xe2,0x01,0x00,0x00,0x15,0x08,0xff,0x30,0xe8,0x01, + 0x01,0x01,0x01,0xe7,0xe6,0x04,0x01,0x02,0x11,0x05,0x03,0x05,0x03,0x05,0x03,0x05, + 0x03,0x04,0x04,0x0b,0x02,0x02,0x01,0x04,0x02,0x01,0x0b,0x07,0x01,0x01,0x0d,0x03, + 0x05,0x09,0x03,0x05,0x03,0x05,0x03,0x0b,0x13,0x01,0x06,0xe5,0xe5,0x02,0x03,0x0c, + 0x01,0xe6,0x11,0x08,0x13,0x16,0x08,0x1e,0x0b,0xe5,0xe6,0x0e,0x09,0x09,0x09,0x09, + 0x0b,0x07,0xe6,0x08,0x02,0xe5,0x04,0x01,0xe6,0x04,0x0e,0x01,0x01,0x14,0x09,0x09, + 0x09,0x09,0x05,0x05,0xe5,0xe6,0x04,0x03,0x05,0xe5,0x01,0x05,0xe5,0x07,0x0c,0xe5, + 0x5b,0x01,0x01,0x05,0x01,0x11,0x02,0xe5,0xe5,0x48,0x13,0x1a,0x01,0xe6,0x3e,0x0b, + 0x10,0x03,0x05,0x13,0x03,0x01,0x28,0x14,0x11,0x24,0x03,0xe5,0xe6,0xe5,0x5d,0x01, + 0x17,0xe5,0x01,0x01,0x0b,0xe5,0x12,0x09,0x49,0x03,0x01,0x01,0x0d,0x31,0x0a,0x2f, + 0x01,0xe6,0x28,0x15,0x1e,0x1b,0xe5,0x01,0x10,0x09,0x09,0x09,0x09,0x0b,0x09,0x09, + 0x09,0x09,0x05,0x02,0x04,0x03,0x10,0x09,0x09,0x04,0x04,0x09,0x01,0x05,0x03,0x09, + 0x13,0x05,0x03,0x0e,0x01,0xe5,0x0c,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5, + 0x04,0x02,0xe5,0x04,0x03,0xe6,0x07,0xe5,0x04,0x02,0xe5,0x05,0x01,0xe5,0xe5,0x05, + 0xe5,0x0e,0x03,0x10,0x09,0x09,0x09,0x09,0x06,0x0d,0x0a,0xe5,0x06,0x0a,0x0e,0x01, + 0xe5,0x05,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x09,0xe5,0x07, + 0xe5,0x02,0x04,0xe5,0xe5,0x01,0x03,0xe5,0x07,0xe5,0x07,0x02,0x05,0xe6,0x0e,0x09, + 0x09,0x09,0x09,0x0d,0x13,0x03,0x05,0x02,0xe5,0x02,0x08,0x05,0xe8,0x0c,0x07,0x01, + 0x09,0x09,0x06,0x02,0x05,0x03,0x01,0x02,0x02,0x01,0x01,0x06,0x02,0x02,0x06,0x02, + 0x06,0x0a,0x06,0xe5,0xe5,0x0c,0x02,0x06,0x02,0x06,0x02,0x04,0x01,0x02,0x06,0x02, + 0x06,0x01,0x02,0x06,0x02,0x06,0x01,0xe6,0x02,0xe6,0xe6,0x05,0x02,0x0d,0x02,0xe5, + 0x02,0x2b,0x01,0x06,0x0b,0x0c,0x06,0x01,0x01,0xe5,0x14,0x02,0x03,0xe5,0xe6,0x13, + 0x23,0x0a,0x14,0x04,0x1c,0xe5,0xe6,0x27,0x01,0x0e,0x0a,0x03,0x13,0x1d,0x02,0xe5, + 0x0d,0x04,0xe7,0x14,0x0e,0x05,0xe5,0x05,0x0c,0x03,0x0a,0x01,0x09,0x0a,0x01,0x10, + 0x04,0xe5,0x02,0x09,0x09,0x09,0x09,0xe6,0x08,0x09,0x09,0xe5,0x07,0x0e,0xe5,0xe5, + 0x32,0x0d,0x10,0x02,0x02,0x03,0x02,0x02,0x03,0x15,0xe6,0x47,0x09,0x02,0x09,0x07, + 0x12,0xe5,0xe6,0x24,0x1c,0x12,0x09,0x16,0x03,0xe5,0x01,0x06,0x27,0x16,0x04,0x08, + 0x22,0x05,0x01,0x47,0x15,0x09,0x05,0x0c,0x02,0xe5,0x40,0xe5,0x11,0xe6,0x06,0x01, + 0x18,0xe8,0x05,0x3e,0x0f,0x0c,0x18,0x01,0xe5,0x2f,0x0f,0x13,0x08,0xe6,0x19,0xe6, + 0xe5,0x0b,0x2b,0x15,0x14,0x05,0x10,0x01,0xe6,0x3f,0x28,0x07,0x0a,0xe6,0x09,0x2e, + 0x2d,0x12,0xe8,0x59,0x08,0x0f,0xe5,0x04,0x01,0x01,0x23,0x07,0x01,0x01,0x17,0x2c, + 0x05,0xe8,0x22,0x09,0x02,0x28,0x0a,0x15,0xe6,0xe5,0x12,0x0d,0xe5,0x01,0x06,0x2e, + 0x09,0x16,0xe8,0x74,0xe5,0xe5,0xe7,0x01,0x01,0x50,0xe5,0x1d,0x01,0x02,0x01,0x01, + 0x04,0x52,0x18,0x01,0x02,0x01,0x03,0xe7,0x01,0x52,0x1a,0x06,0x02,0x03,0x57,0x11, + 0x01,0x05,0x06,0xe5,0x03,0x02,0x52,0x03,0x01,0x02,0x0a,0x01,0x01,0x06,0x02,0x02, + 0x01,0xe7,0x55,0x11,0x01,0x0b,0x02,0xe5,0x01,0x55,0x13,0x01,0x0e,0xe5,0xe6,0x04, + 0xe5,0x01,0x02,0x6c,0xe7,0xe5,0x04,0x04,0x6f,0xe6,0xe6,0x09,0x03,0x09,0x09,0x09, + 0x09,0x0b,0x09,0x09,0x09,0x09,0x06,0x06,0xe6,0xe6,0x01,0x6c,0x02,0x09,0xe6,0x6e, + 0x08,0x01,0xe5,0xe6,0x22,0x09,0x4e,0x01,0x23,0xe5,0x07,0xe5,0x4a,0xe9,0x1e,0x02, + 0x09,0x4d,0x01,0xe5,0x14,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x07,0xe5, + 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0x02,0x09,0x19,0x09, + 0x50,0x23,0x09,0x4c,0xe5,0x01,0x23,0x09,0x4c,0x02,0xe5,0x08,0x19,0x09,0x4c,0xe5, + 0xe6,0x1e,0x59,0x02,0xe6,0x10,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,0x01,0x05,0x01, + 0x07,0x01,0x09,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0xe6,0xe5, + 0x77,0x02,0x02,0xe5,0x28,0x04,0x03,0x08,0x03,0x13,0x24,0xe6,0xe6,0x3e,0x3b,0xe5, + 0xe6,0x22,0x1a,0x39,0x02,0xe6,0x3e,0x3a,0x01,0x01,0xe5,0x11,0x2b,0x1b,0x1d,0xe5, + 0x02,0x3f,0x32,0x07,0xe5,0xe6,0x07,0x36,0x3c,0x01,0x1a,0x24,0xe5,0x38,0xe6,0xe5, + 0x0a,0x0a,0x28,0x3c,0x01,0x1b,0x5f,0xe7,0x7a,0xe7,0x7a,0x02,0x01,0x01,0x73,0xe5, + 0x02,0xe6,0x01,0x72,0x01,0x03,0xe7,0x03,0x6b,0x01,0x02,0x01,0x02,0x01,0xe7,0xe5, + 0x6b,0xe5,0x05,0x02,0x03,0xe5,0x77,0x02,0xe7,0xe5,0x73,0x03,0xe8,0x77,0x01,0xe8, + 0x78,0xe6,0xe5,0x78,0xe5,0x01,0xe5,0x7a,0xe8,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09, + 0x09,0x09,0x09,0x0d,0xe5,0xe7,0x01,0x77,0xe8,0x77,0x01,0x02,0xe5,0x6f,0x0d,0x7a, + 0x01,0xe6,0x78,0xe5,0xe5,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x7a,0xe5,0xe5,0x79, + 0x01,0xe6,0x79,0x01,0x01,0x7e,0x7c,0xe6,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x01,0x07,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x07,0x01, + 0x02,0x05,0x04,0xe5,0x7b,0xe7,0x1e,0x29,0x08,0x25,0xe9,0x3e,0x3c,0x01,0x03,0xe5, + 0x39,0x3d,0xe7,0x3c,0x3b,0x02,0xe5,0x2f,0x0d,0x3b,0xe5,0xe6,0x3d,0x3a,0x01,0x01, + 0x3f,0x3c,0xe7,0x03,0x25,0xe6,0x10,0x1f,0xe6,0x1a,0xe5,0x2d,0x10,0x21,0x18,0xe5, + 0xe6,0x15,0x63,0xe6,0xe5,0x13,0x22,0x41,0xe7,0xe5,0x36,0x42,0x01,0x01,0x01,0x76, + 0xe5,0x01,0xe6,0x01,0x01,0x70,0x01,0x06,0x01,0xe5,0xe5,0x6f,0x04,0xe5,0x01,0x02, + 0x74,0x06,0xe5,0x0a,0x6e,0x01,0xe5,0xe6,0x06,0xe6,0x69,0x04,0x01,0x02,0x76,0xe9, + 0x79,0xe5,0xe7,0x7a,0x01,0x63,0x16,0xe9,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,0x09, + 0x09,0x09,0x04,0x01,0x06,0x02,0xe6,0x71,0x04,0x02,0x02,0xe5,0xe5,0x60,0x0b,0x0b, + 0xe5,0xe5,0x36,0x27,0x01,0x16,0x03,0x01,0x37,0xe5,0x25,0x01,0x01,0x16,0x01,0xe7, + 0x26,0x0e,0x27,0x01,0x03,0x14,0xe5,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x01,0x05,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x09,0xe5, + 0x2d,0x08,0x2a,0x17,0xe6,0xe5,0x2d,0x08,0x2a,0x18,0xe5,0xe5,0x08,0x2d,0x08,0x39, + 0x02,0xe5,0x2d,0x08,0x2c,0x19,0xe5,0x12,0xe5,0x63,0x01,0xe6,0x05,0x0a,0x01,0x07, + 0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x07,0x01,0x0a,0xe5,0xe6,0xe5,0x06,0x4a,0x0e,0x16,0xe9,0x32,0x09,0x13, + 0x13,0x12,0xe5,0x02,0x0a,0x33,0xe6,0x12,0x09,0x1b,0x01,0x01,0xe5,0x07,0x06,0x03, + 0x1a,0x1a,0x16,0x17,0x01,0x02,0x13,0x2b,0xe5,0x0e,0x2b,0x01,0xe5,0x0a,0x32,0x03, + 0x17,0x03,0xe6,0x16,0x02,0x01,0x26,0x02,0x01,0x07,0x0b,0x01,0xe6,0x04,0x15,0x01, + 0x18,0xe8,0x08,0x1e,0x02,0x13,0x3a,0x03,0x05,0x02,0x36,0x15,0xe5,0x06,0xe7,0x17, + 0xe5,0xe6,0x38,0x05,0x15,0x02,0x07,0x1a,0x02,0x02,0x13,0x16,0x2a,0x0e,0x03,0x12, + 0x19,0x04,0x0d,0x03,0x0b,0x2d,0xe5,0x11,0x19,0x20,0x2f,0x11,0x01,0x01,0x49,0x02, + 0xe6,0x0d,0x02,0xe5,0x04,0x0e,0x03,0x01,0x02,0x01,0x41,0x04,0x03,0xe5,0x0d,0x02, + 0x06,0x0b,0x01,0x03,0x02,0x01,0xe5,0xe5,0x22,0xe5,0x05,0x1a,0x10,0x01,0xe5,0xe5, + 0x01,0x04,0x02,0x08,0x04,0x01,0x01,0x02,0x48,0x10,0xe5,0xe5,0xe5,0x06,0xe6,0xe5, + 0xe6,0x05,0x02,0xe9,0x04,0x05,0x20,0x04,0x01,0x0c,0x01,0x07,0x0e,0x04,0x01,0xe5, + 0x05,0x02,0x03,0x01,0x06,0xe5,0xe5,0xe5,0xe6,0x07,0x23,0x01,0x02,0x0c,0x01,0x01, + 0x05,0x03,0x0f,0x01,0xe5,0x05,0x03,0x04,0x04,0x02,0xe8,0x01,0x3e,0x01,0x07,0x0d, + 0x02,0x01,0xe5,0xe5,0x06,0x05,0xe6,0x06,0xe7,0xe5,0x40,0x01,0x07,0x10,0x01,0xe5, + 0xe6,0x05,0x01,0xe5,0x02,0x0a,0x01,0xe6,0x1b,0x02,0x10,0x26,0x09,0x09,0x04,0x07, + 0x01,0xe7,0x01,0x1b,0xe5,0x13,0x23,0xe5,0x0b,0x09,0xe5,0x09,0x01,0xe5,0x0d,0x09, + 0x09,0x04,0x01,0x02,0x09,0x0b,0x09,0x09,0xe6,0x06,0xe5,0x02,0xe6,0x01,0xe5,0xe5, + 0xe5,0xe5,0x05,0x01,0x02,0x16,0x13,0x33,0x13,0x04,0x02,0xe5,0xe6,0xe5,0x10,0x14, + 0x32,0x14,0x0b,0xe6,0x16,0x01,0x11,0x01,0x24,0x05,0xe5,0x04,0x01,0xe5,0x05,0x01, + 0xe6,0x0d,0x01,0x16,0xe5,0xe6,0x0f,0x01,0xe5,0x29,0x05,0x01,0x07,0x01,0x0f,0xe8, + 0x15,0x01,0x11,0x01,0x2a,0x08,0x07,0x01,0x01,0x0c,0xe5,0xe6,0x03,0x10,0xe6,0xe5, + 0x04,0x09,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0x02,0x06,0x01,0xe5,0x06,0xe7,0xe5, + 0x02,0x01,0xe6,0xe5,0x04,0xe5,0x08,0x01,0x17,0x01,0x05,0x0b,0x01,0x0f,0x09,0x0b, + 0x04,0xe5,0x04,0x01,0x09,0x0f,0xe5,0xe5,0x16,0x01,0x06,0x0a,0x01,0x30,0xe5,0xe5, + 0x05,0xe5,0xe5,0x0d,0x01,0xe7,0x17,0x05,0x0b,0x01,0x0f,0x02,0x08,0x07,0x01,0x08, + 0x04,0x03,0x01,0x16,0x17,0x01,0x03,0xe5,0x0d,0x0d,0x15,0x08,0x01,0x01,0xe5,0xe5, + 0x03,0xe6,0x10,0xe6,0xe5,0x10,0x1c,0x03,0x18,0x13,0xe5,0xe5,0x05,0x14,0x11,0x01, + 0x01,0x05,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x02,0x04,0x01,0x04, + 0x02,0x01,0x07,0x01,0x03,0x03,0x01,0x03,0x03,0x01,0x0b,0xe7,0xe5,0x12,0x15,0x05, + 0x0a,0x10,0xe5,0x17,0x03,0xe5,0x0c,0x01,0xe7,0x48,0x03,0x0e,0x0c,0x03,0x01,0x08, + 0x04,0x05,0x02,0x0b,0x0b,0x09,0x08,0xe5,0x03,0x05,0x0b,0x01,0x02,0x0b,0x0e,0x01, + 0x0c,0x01,0xe6,0xe5,0x01,0x0f,0x02,0xe6,0x03,0x0e,0x03,0x18,0x0d,0x20,0xea,0x01, + 0x06,0x20,0x03,0x0f,0x05,0x21,0x14,0x01,0xe5,0x15,0x1f,0x07,0x09,0x1b,0x13,0x04, + 0xe5,0x06,0x04,0x0c,0x0a,0xe5,0x09,0x04,0x06,0xe6,0x24,0x03,0x01,0x0e,0x01,0xe6, + 0x0a,0x03,0x17,0xe5,0x15,0x11,0x11,0x09,0x0c,0x02,0xe6,0x06,0x02,0x0b,0xe6,0x17, + 0x09,0x02,0x07,0x12,0x04,0xe6,0x06,0xe5,0xe6,0x0c,0xe7,0x18,0x15,0xe5,0x0d,0x10, + 0x11,0x06,0x01,0x0e,0x01,0xe6,0x3c,0x06,0x03,0x22,0x0e,0x01,0xe6,0x09,0x04,0x58, + 0x11,0x02,0xe5,0x08,0x05,0x2a,0x01,0x1c,0x0f,0x10,0xe6,0xe5,0xe5,0x01,0x05,0xe5, + 0xe5,0x01,0xe5,0x01,0x01,0x03,0xe5,0x11,0x09,0x02,0xe5,0x06,0xe5,0x22,0x0e,0x01, + 0x03,0x02,0x06,0xe5,0x01,0xe6,0x21,0xe5,0xe5,0x2f,0x01,0xe5,0x0a,0x01,0x06,0x01, + 0xe5,0xe5,0x04,0x01,0xe5,0xe5,0xe5,0x08,0x1b,0x02,0x0a,0x23,0x06,0xe5,0x02,0x06, + 0x01,0xe5,0xe5,0x06,0x02,0x27,0x33,0x05,0xe5,0x05,0x02,0x02,0xe6,0x09,0x01,0x01, + 0x27,0x06,0x25,0x04,0x01,0x02,0x09,0xe5,0xe6,0xe8,0x09,0x01,0x01,0x02,0x01,0x1e, + 0x03,0x02,0xe6,0x29,0x01,0x01,0x09,0x02,0x03,0x02,0x0a,0x01,0x18,0x01,0x07,0x01, + 0x02,0x04,0x01,0x07,0x01,0x20,0x01,0x01,0x06,0x02,0x04,0x01,0xe5,0xe5,0x09,0x01, + 0x18,0x01,0x0a,0x12,0xe5,0x18,0x05,0x01,0x0e,0xe8,0xe5,0x10,0x02,0x24,0xe5,0x0b, + 0x07,0xe5,0x07,0x06,0x02,0xe5,0x04,0x02,0x02,0x06,0xe7,0xe5,0x13,0x3d,0x09,0x01, + 0x03,0xe5,0x01,0x05,0xe5,0x01,0xe5,0x0b,0xe5,0x0a,0x02,0x02,0xe6,0xe5,0x01,0x09, + 0x09,0x04,0x01,0x02,0x0b,0x09,0x03,0x05,0x05,0x03,0xe5,0x01,0x05,0xe6,0x03,0x06, + 0x01,0xe5,0xe5,0x0a,0xe5,0x08,0x27,0x32,0xe5,0x03,0x03,0x01,0xe5,0xe5,0x08,0x07, + 0x27,0x27,0x0b,0x0b,0xe5,0xe5,0x0c,0x01,0x04,0x04,0x1a,0xe5,0xe5,0x08,0x01,0x07, + 0x01,0x07,0x01,0x04,0x02,0x01,0xe5,0x05,0x01,0xe6,0x0f,0x02,0x0a,0x01,0xe5,0x05, + 0x02,0x1a,0x01,0xe5,0x07,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6, + 0x01,0x01,0xe5,0xe7,0x0b,0xe5,0x01,0xe5,0x0a,0xe5,0xe5,0x08,0x03,0x13,0x05,0x03, + 0xe5,0x03,0x01,0x25,0x01,0xe5,0x07,0x04,0x03,0x0d,0x01,0x05,0xe6,0x04,0xe5,0xe5, + 0x07,0xe5,0x07,0xe6,0x04,0x01,0xe5,0x01,0x01,0x05,0xe5,0x07,0xe5,0x06,0xe6,0x05, + 0xe5,0xe6,0xe5,0x04,0xe5,0x0a,0x09,0x05,0x09,0xe5,0x02,0x05,0xe5,0x07,0x08,0x05, + 0x05,0xe6,0x02,0x01,0x01,0x05,0x01,0x01,0xe5,0x02,0x02,0x01,0xe5,0x02,0x02,0x01, + 0x0e,0xe8,0x03,0x08,0x01,0x07,0x02,0x05,0x14,0x05,0x05,0x09,0x01,0x07,0x01,0x06, + 0xe5,0xe6,0x04,0xe5,0xe5,0x0f,0xe6,0x08,0x03,0x01,0x09,0x03,0x01,0xe5,0x0c,0x08, + 0x05,0x02,0x02,0x05,0x09,0x04,0x05,0x06,0x01,0xe5,0x01,0x0e,0x03,0x04,0x08,0x01, + 0x07,0x02,0x02,0xe5,0x04,0x09,0x06,0x02,0x02,0x05,0x02,0x13,0x03,0x07,0xe6,0x01, + 0x01,0x02,0x0b,0x02,0xe6,0x02,0x08,0x01,0xe5,0x0c,0x19,0x0f,0x1a,0x05,0x01,0xe5, + 0x0b,0x01,0x01,0xe5,0x02,0x02,0x07,0x02,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01, + 0x01,0x05,0x01,0x04,0x04,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x02,0x02, + 0x01,0x0b,0x02,0x01,0x01,0x07,0x14,0x0c,0x01,0x05,0x07,0xe5,0x06,0x03,0x0c,0xe6, + 0x06,0xe6,0x13,0x01,0x02,0xe6,0x06,0x24,0xe5,0x01,0x02,0x04,0x02,0x12,0x01,0x02, + 0xe5,0xe5,0x06,0x08,0x07,0x08,0xe6,0xe6,0x08,0x14,0x01,0x07,0x01,0x0e,0x02,0xe7, + 0x0f,0x0f,0x19,0xe5,0xe6,0x03,0x08,0x06,0x10,0x0e,0xe5,0x03,0x08,0x01,0x1f,0xe6, + 0xe5,0x03,0x0a,0x02,0x01,0xe5,0x01,0x0c,0x16,0xe5,0x07,0xe5,0x03,0x05,0x01,0xe6, + 0x03,0x01,0x15,0x08,0x04,0x0e,0xe5,0xe6,0x11,0x01,0x02,0xe5,0x1b,0xe5,0x06,0x03, + 0x05,0x05,0x0b,0x1d,0xe7,0xe6,0x06,0x03,0x0d,0x0e,0x0b,0x01,0x01,0xe6,0x02,0x01, + 0xe7,0x05,0x1d,0x11,0x02,0x28,0x06,0x03,0x07,0xe5,0x01,0x0b,0x18,0x06,0x06,0x07, + 0x03,0xe5,0x1e,0x01,0x07,0x07,0x0c,0x07,0x02,0xe5,0xe5,0x02,0x02,0xe6,0x06,0x15, + 0x05,0x02,0xe5,0x1c,0x05,0x10,0x05,0x04,0x05,0x12,0x01,0x15,0x09,0x02,0xe5,0x0b, + 0x07,0x0e,0x04,0xe5,0x02,0x02,0x10,0x01,0xe5,0xe5,0xe5,0x0b,0xe6,0x01,0x01,0x1d, + 0xe6,0xe5,0xe5,0x0f,0x09,0x05,0xe6,0x06,0xe5,0x04,0x03,0x0b,0x0b,0x07,0xe5,0x03, + 0x0a,0x02,0x01,0x07,0x04,0xe8,0x11,0x01,0x0d,0x05,0x04,0x09,0x02,0x01,0x05,0x03, + 0xe5,0x0e,0x04,0x0e,0x03,0x0a,0xe5,0xe6,0x01,0x0e,0x06,0xe5,0xe5,0x0f,0x02,0x12, + 0x03,0x10,0x08,0xe6,0x10,0x02,0x03,0xe5,0xe5,0x03,0x01,0xe6,0x02,0x03,0x07,0x0b, + 0x07,0x01,0x12,0x02,0x09,0xe5,0x04,0x0a,0x08,0x05,0x0b,0xe5,0xe7,0x17,0xe5,0x07, + 0xe5,0x07,0xe5,0x04,0x02,0x02,0xe5,0x06,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x04,0x17, + 0xe5,0x01,0xe5,0xe5,0x01,0x01,0x01,0x06,0xe5,0x0a,0x08,0xe5,0x05,0xe5,0x01,0x05, + 0xe6,0x09,0xe5,0x09,0x09,0x10,0x0b,0x01,0x02,0x01,0xe6,0x03,0x01,0x08,0x0e,0x01, + 0x0c,0x07,0x01,0x02,0x08,0x01,0x05,0x13,0x06,0x01,0xe5,0xe5,0x03,0x01,0x02,0x01, + 0x03,0x01,0xe5,0x0c,0x1d,0x05,0xe5,0x01,0x01,0x0b,0x09,0x1b,0x01,0x04,0x06,0x02, + 0x03,0x0f,0x06,0xe5,0xe5,0x09,0x08,0x06,0xe5,0xe6,0x04,0x02,0x08,0x03,0x03,0x01, + 0x0a,0x08,0xe5,0xe5,0x03,0xe6,0x04,0xe5,0x02,0xe5,0x01,0x02,0x07,0x03,0x03,0x01, + 0x01,0x01,0x07,0x01,0x05,0x03,0x03,0x01,0x01,0xe5,0x03,0xe5,0x03,0x01,0x03,0xe5, + 0x05,0x02,0x11,0xe7,0xe5,0xe5,0x01,0x01,0x01,0x02,0x06,0x01,0x0d,0x07,0x01,0x03, + 0xe5,0x0d,0x07,0x01,0x04,0xe6,0x01,0x07,0x15,0x09,0x01,0x0b,0x02,0xe5,0x01,0x0d, + 0x09,0x01,0x04,0x01,0x03,0x06,0x09,0x02,0x03,0x06,0x25,0x01,0x10,0xe6,0x08,0x1d, + 0x02,0x06,0x06,0x02,0x01,0xe5,0x11,0x02,0x10,0x02,0x06,0xe5,0x01,0xe5,0x03,0x04, + 0x0a,0x01,0x1b,0x09,0x01,0x13,0xe5,0x07,0x10,0xe5,0xe5,0x08,0x03,0x06,0x02,0xe5, + 0x07,0x05,0x09,0x06,0x02,0x02,0x02,0x03,0x03,0x05,0xe5,0x04,0x04,0x09,0x04,0xe6, + 0x01,0x04,0x01,0x02,0x03,0x05,0x03,0x02,0x06,0x01,0xe7,0x01,0x1a,0x02,0x13,0x08, + 0xe5,0x1e,0x09,0x06,0x0a,0x01,0xe6,0x1e,0x13,0x07,0x21,0x07,0x12,0x02,0xe7,0xe5, + 0x0a,0x01,0x15,0x05,0x01,0x07,0x01,0xe5,0x07,0x01,0x13,0x04,0x02,0x01,0x07,0x01, + 0x0f,0xe5,0xe5,0x0c,0x01,0xe5,0x16,0x02,0x01,0x01,0x04,0xe5,0xe5,0x05,0x02,0x01, + 0xe5,0x08,0x06,0x01,0xe5,0x05,0x01,0x01,0x01,0x02,0xe5,0xe6,0x0c,0xe5,0xe6,0x0c, + 0x01,0x0d,0x07,0x0c,0x04,0x09,0x01,0x13,0x09,0x07,0x01,0x0d,0xe6,0x01,0x0d,0x01, + 0x03,0xe7,0x05,0xe7,0x05,0xe6,0xe5,0x04,0xe8,0xe5,0x03,0xe6,0x01,0x01,0x03,0x02, + 0x06,0xe5,0xe6,0xe5,0x02,0xe8,0x06,0xe5,0x01,0x05,0xe5,0x07,0x02,0x13,0xe5,0xe5, + 0x02,0xe5,0xe5,0x05,0x04,0x01,0x01,0x04,0x02,0x01,0xe5,0x07,0x01,0xe5,0x08,0xe5, + 0x0e,0x01,0x07,0x01,0x0e,0xe5,0xe6,0x14,0xe5,0x06,0x01,0x07,0x01,0xe5,0xe5,0x05, + 0xe5,0xe5,0x05,0x04,0x03,0x02,0x07,0x01,0x09,0xe5,0xe5,0x08,0x0e,0xe5,0x01,0xe5, + 0x0a,0x08,0x09,0x01,0x02,0x02,0x01,0x07,0x01,0xe6,0xe6,0x02,0xe5,0x01,0xe5,0xe6, + 0x03,0xe6,0xe5,0x02,0x01,0x07,0xe6,0x0a,0x01,0x0e,0xe8,0x13,0x05,0x03,0xe6,0x02, + 0x03,0x02,0x04,0xe5,0xe5,0xe5,0xe6,0x01,0x01,0xe5,0x01,0x01,0xe5,0x01,0xe5,0x01, + 0x01,0xe5,0x02,0x01,0x07,0xe6,0x04,0x06,0x0e,0x02,0xe5,0x01,0x07,0x16,0x0d,0xe5, + 0x03,0x02,0xe5,0x08,0xe5,0x05,0x02,0x10,0x02,0x06,0x02,0x0c,0xe6,0xe6,0x10,0x01, + 0xe5,0x05,0x01,0xe5,0x02,0x02,0x01,0x01,0x05,0x01,0x04,0x02,0x01,0x04,0x04,0x01, + 0x02,0x01,0x01,0xe7,0x06,0x01,0x03,0x03,0x01,0x04,0x02,0x01,0xe5,0x0a,0xe6,0xe5, + 0x20,0xe5,0x07,0xe5,0x05,0x02,0x05,0x04,0xe5,0xe5,0x03,0x01,0x11,0x09,0x0e,0x05, + 0xe5,0x0a,0x07,0x0a,0x03,0x01,0x01,0x03,0x01,0x06,0xe5,0x01,0x0a,0x0e,0x13,0x12, + 0xe9,0x03,0x05,0x16,0x05,0x02,0x11,0x02,0x01,0x03,0x07,0x02,0x03,0x11,0x13,0x03, + 0xe5,0x0a,0xe7,0x03,0x0e,0x04,0x0b,0xe7,0xe5,0x05,0xe7,0x03,0x02,0x01,0x07,0x01, + 0x05,0x01,0xe5,0x16,0xe5,0x02,0xe5,0x35,0x08,0x01,0x03,0x05,0x01,0x08,0xe5,0x03, + 0x1e,0xe8,0x07,0x03,0x05,0x04,0xe5,0x02,0x02,0xe7,0x01,0x05,0xe5,0x02,0xe6,0x06, + 0x01,0xe6,0x02,0x0d,0x05,0x0f,0x11,0xe9,0x20,0x09,0x0c,0x06,0x01,0x01,0x02,0x0b, + 0x02,0x05,0x11,0x0c,0x02,0xe5,0x0b,0x16,0x02,0x03,0x02,0x05,0x0a,0xe5,0x03,0x01, + 0x0a,0x05,0xe6,0xe5,0x07,0x15,0x02,0xe5,0x0c,0xe5,0x15,0x02,0x07,0x03,0xe5,0x08, + 0x07,0x02,0x0b,0x02,0x15,0x0a,0xe6,0xe5,0x03,0x05,0x05,0x24,0x06,0xe5,0xe6,0x03, + 0x09,0x03,0x04,0x25,0x0e,0x05,0x02,0x01,0x02,0x07,0x02,0x0f,0x02,0x08,0x04,0x02, + 0x01,0x04,0xe5,0x03,0xe5,0x20,0xe7,0x08,0x0f,0x01,0x0d,0x01,0x01,0x03,0x04,0xe5, + 0xe5,0x01,0x03,0xe5,0xe5,0x08,0x09,0x23,0x01,0xe5,0x01,0x15,0x1d,0x04,0x05,0x0a, + 0x03,0x06,0x22,0xe6,0xe5,0x0c,0x09,0x09,0x18,0xe6,0x03,0x02,0xe6,0xe5,0xe5,0x02, + 0x03,0xe5,0x05,0x07,0xe6,0x06,0x01,0x08,0xe5,0xe5,0x01,0xe5,0x03,0x08,0x09,0xe5, + 0x07,0xe5,0x17,0xe5,0x03,0x05,0xe5,0x06,0x01,0xe5,0x0e,0x05,0xe5,0x02,0x06,0x01, + 0x02,0xe5,0xe6,0x03,0x08,0x05,0xe5,0x03,0x04,0xe5,0x02,0x03,0xe5,0x08,0x01,0x02, + 0x04,0x01,0x02,0x01,0x01,0xe5,0xe6,0xe5,0x0b,0x12,0x04,0xe5,0x02,0x01,0x02,0x01, + 0x01,0x02,0x0a,0x06,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,0x02,0x06,0x04,0x01,0x07, + 0x0a,0x01,0x10,0x0d,0x03,0xe8,0x04,0x05,0xe5,0x08,0x01,0x06,0x02,0x03,0x01,0xe6, + 0xe6,0xe6,0xe6,0x04,0x02,0xe5,0x01,0x01,0x11,0x04,0x10,0x06,0x05,0xe6,0x01,0xe5, + 0x01,0x07,0xe7,0x02,0x05,0x01,0x01,0x01,0x01,0xe6,0x05,0x01,0xe5,0x01,0x05,0x05, + 0x01,0xe6,0x01,0x01,0x01,0x09,0x07,0x04,0x01,0x0a,0x03,0x03,0xe5,0x03,0x02,0xe5, + 0x01,0xe5,0x0b,0x09,0x01,0x09,0x07,0x01,0x02,0x01,0xe5,0x02,0x09,0x01,0x07,0x06, + 0x01,0xe5,0x02,0x02,0x0e,0x05,0x05,0x02,0x02,0xe5,0x0c,0x09,0x01,0x07,0x09,0x01, + 0xe6,0x01,0xe5,0xe5,0x0a,0x01,0x07,0x05,0xe5,0x03,0x03,0xe6,0x0a,0x05,0xe5,0x08, + 0x03,0xe5,0x07,0x13,0x09,0xe5,0x04,0x04,0x04,0x02,0x0b,0x09,0x09,0x02,0x1a,0xe9, + 0x0b,0x13,0x04,0x0a,0x01,0xe5,0x07,0xe6,0x08,0xe6,0x06,0xe6,0x03,0x20,0x01,0xe7, + 0x0d,0x09,0x09,0x06,0x02,0xe5,0x07,0x06,0x04,0x09,0x04,0x01,0x02,0xe5,0xe5,0x05, + 0x09,0x0d,0x04,0x27,0x0c,0x08,0xe5,0x0a,0x09,0x1d,0x08,0x01,0xe5,0xe5,0x2e,0x0b, + 0x09,0x0b,0x1b,0x08,0x01,0x01,0x01,0x1e,0x0c,0x01,0xe5,0x05,0x01,0xe5,0x07,0x01, + 0x06,0xe5,0xe5,0x08,0x01,0x16,0x01,0x09,0xe6,0x19,0x0a,0x01,0x03,0x01,0x01,0x02, + 0x01,0xe5,0xe7,0x06,0x01,0xe5,0x05,0x01,0xe5,0x08,0xe5,0xe5,0x1e,0x01,0xe6,0x07, + 0x0c,0xe5,0x05,0x08,0x03,0x01,0x09,0x06,0x02,0x01,0x07,0x01,0x04,0x01,0x04,0x1f, + 0x03,0xe6,0x12,0xe7,0x06,0x09,0xe6,0xe5,0x03,0xe7,0xe5,0x02,0xe5,0xe5,0x01,0x01, + 0x04,0xe7,0xe5,0x02,0xe7,0x05,0x02,0x08,0xe5,0x07,0xe5,0x06,0xe8,0x0f,0x03,0x01, + 0x08,0x01,0x01,0x06,0x03,0xe5,0x02,0xe6,0xe6,0x09,0xe5,0x04,0xe5,0xe5,0x09,0x22, + 0xe5,0xe5,0x0f,0x04,0xe5,0x08,0xe5,0xe5,0x04,0xe5,0x06,0x01,0xe5,0xe6,0x04,0x02, + 0x01,0x04,0xe7,0xe5,0x03,0xe6,0x02,0x05,0x1b,0x01,0x01,0x15,0x01,0x07,0x09,0x09, + 0x01,0x01,0x03,0xe7,0xe6,0xe6,0x03,0x03,0x03,0x01,0xe5,0x05,0x01,0xe5,0x1a,0xe5, + 0x01,0x10,0x02,0x03,0x05,0xe5,0x06,0xe6,0x01,0x02,0x01,0xe6,0x01,0x01,0xe5,0xe7, + 0x03,0x01,0xe5,0x01,0xe5,0x01,0x01,0xe5,0x02,0x07,0xe6,0x1c,0xe5,0x01,0x0d,0x01, + 0xe5,0x05,0x02,0x09,0x07,0x01,0x12,0x01,0xe5,0x05,0xe5,0xe5,0x1d,0x0b,0xe5,0xe5, + 0xe5,0x08,0xe5,0x02,0x02,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04, + 0x01,0x02,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x0b,0x02, + 0x0b,0x09,0x01,0x09,0x0f,0x05,0xe5,0x09,0xe5,0x06,0x03,0x08,0x08,0x15,0x03,0x01, + 0xe5,0x06,0x15,0x17,0x07,0x02,0x02,0x09,0xe5,0x0d,0x01,0x05,0x12,0x03,0xe5,0x02, + 0x0f,0xe5,0x05,0x0b,0xe5,0x05,0x06,0x08,0x03,0x15,0x0e,0x04,0x08,0x04,0x01,0xe6, + 0x08,0x12,0x03,0x01,0x07,0x01,0x04,0x02,0x01,0xe5,0x07,0xe7,0x0e,0xe7,0x03,0x12, + 0xe5,0x07,0x01,0xe5,0xe5,0x0a,0x05,0x0d,0x01,0x01,0x08,0x01,0x07,0xe5,0x06,0xe5, + 0xe5,0x02,0x0e,0x27,0xe6,0x07,0x09,0x04,0xe5,0x02,0xe5,0x0c,0xe5,0x01,0x0a,0x03, + 0xe5,0x01,0x04,0x0a,0x03,0x05,0x11,0x09,0xe5,0x02,0x24,0x16,0x03,0x02,0x01,0x0a, + 0x05,0x01,0x1d,0x05,0xe5,0xe5,0x02,0x22,0x09,0x0e,0xe5,0x03,0x03,0x06,0x07,0x21, + 0xe5,0x01,0x08,0x0f,0x0e,0x0b,0x0a,0xe5,0x04,0x02,0x01,0x09,0x03,0x19,0x01,0x06, + 0x02,0x13,0x04,0x19,0xe5,0x04,0x02,0x02,0x19,0x1b,0x05,0xe7,0x04,0x22,0x12,0x09, + 0xe5,0x05,0x0e,0x21,0x06,0x03,0x1a,0x1d,0x03,0x05,0x01,0xe5,0x11,0x04,0x13,0x01, + 0x05,0x0b,0x13,0x1c,0x08,0x01,0x26,0x05,0xe6,0xe5,0xe5,0x17,0xe6,0xe5,0xe5,0x02, + 0xe5,0x15,0x01,0x05,0xe5,0x01,0xe5,0x03,0xe5,0x0e,0x05,0xe5,0x01,0x02,0xe5,0x09, + 0xe8,0xe5,0x01,0x01,0x15,0x02,0xe5,0x01,0xe5,0x01,0x02,0xe5,0x10,0xe5,0x03,0xe5, + 0x11,0xe5,0x07,0x06,0x01,0xe5,0x0a,0x01,0x02,0xe5,0x01,0x04,0x05,0xe5,0xe5,0xe5, + 0x12,0x1d,0x01,0x01,0x01,0xe5,0x03,0x01,0x05,0x01,0x07,0x09,0x03,0x07,0x08,0x02, + 0x0a,0x01,0x11,0x1f,0x01,0x09,0x07,0x01,0x07,0x09,0x0d,0x03,0x02,0xe5,0x08,0x01, + 0x0a,0x01,0x09,0x06,0xe5,0xe5,0x12,0x01,0x03,0x02,0xe5,0xe6,0x05,0x01,0x06,0xe5, + 0x08,0x0a,0x06,0x01,0xe5,0x01,0x06,0x02,0x04,0x05,0x01,0x01,0x05,0x03,0x03,0xe6, + 0xe5,0xe5,0x10,0x03,0x05,0x01,0x07,0x01,0x01,0x02,0xe7,0x02,0x05,0x03,0x06,0x02, + 0x02,0x01,0x01,0xe5,0x0b,0x01,0x07,0x01,0x04,0x04,0x05,0x01,0x01,0x13,0x01,0x07, + 0x01,0x07,0x01,0x07,0x06,0x02,0x0a,0x04,0x02,0xe6,0x0c,0x01,0x07,0x01,0x04,0xe5, + 0xe5,0x08,0x01,0x13,0x01,0x07,0x01,0x07,0x01,0x07,0x05,0xe6,0xe5,0x0f,0xe5,0xe7, + 0x07,0xe5,0x13,0x2e,0x02,0x02,0x06,0x22,0x02,0x4f,0x09,0x01,0x1b,0xe5,0x01,0xe5, + 0x0a,0x02,0x09,0x06,0x02,0x09,0x09,0x04,0x01,0x04,0x02,0x01,0x01,0x02,0x04,0xe6, + 0x01,0x03,0x05,0x09,0x0d,0xe5,0xe7,0x01,0x06,0x02,0x12,0xe5,0x1c,0x0b,0x2c,0x04, + 0xe6,0x08,0x13,0x1d,0x0b,0x32,0x01,0x01,0x0f,0x10,0x02,0x1f,0x07,0x01,0xe5,0x05, + 0x01,0x04,0x1d,0xe5,0x01,0x0d,0x02,0x10,0x02,0x19,0x02,0x02,0x06,0x01,0xe5,0x04, + 0xe5,0xe6,0x24,0x0f,0x04,0x0e,0x18,0x01,0x04,0x07,0x01,0x09,0x21,0xe5,0x01,0xe5, + 0x0c,0x05,0xe5,0xe5,0x07,0xe6,0x04,0xe5,0xe5,0x06,0xe6,0x07,0xe5,0x01,0x05,0x02, + 0xe5,0x04,0x02,0xe5,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe6,0xe6,0x0e,0x03,0xe5, + 0x04,0xe5,0x06,0x1d,0x01,0xe6,0x04,0x01,0x07,0x01,0x0a,0xe5,0x15,0xe5,0x01,0x0d, + 0x08,0x0a,0x05,0x02,0x09,0x0c,0x08,0xe5,0xe5,0x06,0x01,0x22,0x03,0x0f,0x05,0xe5, + 0x0b,0x04,0xe6,0x06,0x01,0x0c,0x01,0x03,0x01,0xe6,0xe5,0x02,0x01,0x01,0x01,0x22, + 0xe6,0xe5,0x0c,0x06,0x05,0x06,0x02,0x02,0x06,0x03,0x0e,0x02,0x02,0xe5,0x01,0x01, + 0x07,0x01,0x0a,0x1a,0xe5,0x40,0xe5,0xe5,0x19,0x01,0xe5,0x05,0x01,0xe5,0x0b,0x01, + 0x01,0xe5,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0xe5,0x04, + 0xe7,0x06,0x01,0x03,0x03,0x01,0x07,0x01,0x0b,0x01,0xe5,0x22,0x0d,0x01,0xe5,0x08, + 0x03,0x07,0x02,0xe5,0x18,0x01,0x0a,0x05,0xe8,0x0a,0x16,0xe5,0x21,0xe5,0x01,0x26, + 0x06,0x01,0x01,0xe5,0x30,0x06,0x03,0x02,0x0d,0x0b,0x24,0xe5,0x03,0x2c,0x05,0x06, + 0x03,0x04,0x02,0xe5,0x01,0x05,0x01,0x18,0x09,0xe8,0x04,0x05,0x07,0x0b,0x1f,0xe5, + 0x0f,0x06,0x03,0x1b,0x01,0x03,0xe5,0xe5,0x19,0x07,0x0b,0x09,0x03,0xe6,0x07,0x04, + 0x03,0x01,0x24,0x03,0x01,0x03,0x1a,0x17,0x06,0x12,0x1c,0x0a,0xe6,0xe5,0x05,0x0e, + 0x06,0x01,0x07,0x09,0x0d,0xe5,0x10,0x16,0x12,0xe7,0x12,0x02,0x09,0x09,0x08,0xe5, + 0x09,0xe5,0x08,0x04,0x2c,0xe6,0x27,0x13,0xe5,0xe6,0x05,0x33,0x02,0x09,0x01,0x05, + 0x01,0x09,0xe5,0x07,0x1b,0x02,0x06,0x09,0x22,0xe8,0x31,0x10,0x08,0xe5,0x07,0xe5, + 0x05,0x0e,0x0b,0xe5,0xe7,0x07,0x15,0x10,0x0e,0x02,0xe5,0x09,0x09,0x17,0x0a,0xe5, + 0x01,0xe6,0x48,0x09,0x22,0xe5,0x01,0xe6,0x01,0x01,0x46,0xe6,0x01,0x04,0x1f,0x01, + 0x02,0x03,0x04,0x43,0x01,0x02,0x04,0x01,0x02,0x0e,0xe5,0xe5,0xe5,0x08,0x04,0x02, + 0xe5,0x01,0x45,0x04,0x09,0x0e,0x02,0x01,0x0b,0x02,0xe6,0xe5,0x48,0x01,0x01,0x07, + 0x11,0x14,0x01,0x02,0x48,0x01,0x01,0x05,0x03,0x13,0x09,0x02,0x02,0xe6,0x4b,0x09, + 0x04,0x0c,0x01,0x08,0x04,0xe6,0x01,0x31,0xe5,0x19,0x09,0x05,0x0b,0x01,0x10,0xe6, + 0x08,0x47,0x02,0x06,0x02,0x15,0x06,0xe7,0x09,0x01,0x45,0xe5,0x07,0x1d,0x03,0xe5, + 0x07,0x05,0x09,0x09,0x09,0x09,0x0b,0x04,0x01,0x02,0x09,0x05,0x03,0x09,0x0d,0x01, + 0xe7,0x01,0x47,0x09,0x22,0x04,0xe6,0x46,0x09,0x28,0xe5,0xe6,0x42,0x06,0x02,0x07, + 0x01,0x20,0x03,0x01,0x43,0xe5,0x08,0x08,0xe5,0x20,0x03,0xe5,0x41,0x06,0x07,0x02, + 0x28,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x05,0xe5,0x01,0x05, + 0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe6,0xe5,0x2d,0xe5,0x12,0x13,0xe6, + 0x1f,0x02,0xe5,0x42,0x11,0x01,0x22,0xe5,0x01,0x43,0x13,0x21,0xe7,0xe5,0x2d,0x14, + 0x11,0x02,0x1c,0xe5,0x03,0x02,0x4b,0x01,0xe5,0x05,0x23,0xe7,0xe5,0x10,0x01,0x07, + 0x01,0x07,0x01,0x07,0xe6,0x06,0x01,0x09,0x01,0x02,0xe5,0x02,0x01,0x04,0x02,0x01, + 0x07,0x01,0x07,0x01,0x01,0x03,0xe5,0x06,0x2f,0x2e,0x1c,0x02,0xe5,0x1e,0x28,0x1e, + 0x10,0xe6,0xe6,0x1a,0x14,0x0e,0x09,0xe5,0x2a,0x03,0x02,0xe6,0x08,0x14,0x19,0x05, + 0x07,0x03,0xe6,0x06,0x06,0x17,0x06,0xe7,0x3e,0x0b,0x0b,0x22,0xe9,0x07,0x09,0x09, + 0x10,0x09,0x04,0x01,0x04,0xe6,0x27,0x0a,0x02,0xe5,0x29,0x14,0x0a,0x2a,0x04,0x02, + 0xe5,0x0a,0x12,0x20,0x3a,0xe5,0xe6,0x0a,0x07,0x10,0x18,0x01,0x05,0x0b,0x08,0x19, + 0x06,0xe5,0xe5,0x1b,0x13,0x0e,0xe5,0x0d,0x09,0x21,0x02,0x32,0x1c,0x2a,0x01,0x01, + 0x0a,0x2f,0x15,0x0b,0x1c,0xe5,0xe7,0x09,0x27,0x41,0x06,0xe9,0x4f,0xe5,0xe5,0x02, + 0xe5,0x1c,0xe5,0x01,0x01,0x02,0x01,0x4c,0xe5,0x21,0x01,0x03,0xe5,0xe5,0x03,0x0e, + 0xe5,0x01,0x01,0x17,0xe5,0x01,0x01,0x1d,0x03,0x1b,0x05,0x01,0xe5,0x01,0x11,0xe5, + 0xe5,0xe5,0x17,0xe5,0xe5,0xe5,0x3e,0x02,0xe8,0x54,0x04,0x03,0x1c,0x02,0x02,0x18, + 0x1d,0x20,0x01,0xe6,0x17,0x03,0x01,0xe6,0x15,0x01,0x1b,0x01,0x1d,0x23,0xe5,0x01, + 0xe5,0x16,0x01,0x1b,0x01,0x22,0x1f,0x03,0x09,0x02,0x4e,0x1e,0xe8,0xe5,0x59,0x01, + 0x1d,0xe7,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x03,0x05,0x09,0x0d,0x01,0x01, + 0xe5,0x01,0x74,0x04,0xe6,0x7a,0xe5,0xe5,0x79,0xe5,0xe6,0x53,0x03,0xe5,0x1f,0xe9, + 0x53,0x01,0x21,0xe5,0x01,0xe5,0x08,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07, + 0xe5,0x09,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0x02,0x55, + 0x01,0x26,0x55,0x01,0x22,0x03,0x40,0x14,0x01,0x23,0x02,0x04,0x50,0x01,0x02,0x22, + 0xe5,0x01,0x0e,0x43,0x1b,0x0b,0xe5,0x02,0xe5,0x0b,0x01,0x07,0x01,0x07,0x01,0xe5, + 0x05,0x01,0x07,0x01,0x04,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x04,0xe5,0xe5, + 0x06,0x01,0x02,0x05,0x04,0xe5,0x53,0x01,0x27,0xe5,0x72,0x04,0xe7,0xe5,0x2f,0x0e, + 0xe5,0x11,0x0a,0x09,0x11,0x03,0xe5,0x1b,0x1b,0x1b,0x01,0x01,0x14,0x0e,0xe5,0x1c, + 0x13,0x07,0x05,0xe5,0x16,0x15,0x0b,0xe5,0x01,0xe5,0x0c,0xe5,0xe5,0x17,0x02,0x0a, + 0x06,0xe5,0x05,0x0d,0x1a,0x0a,0x01,0xe5,0x12,0x17,0xe5,0x11,0x0f,0x17,0x12,0x01, + 0xe6,0x1b,0x10,0x11,0x19,0x20,0xe5,0x01,0x1e,0x20,0x3e,0x3f,0x24,0x19,0x02,0x0a, + 0x01,0x30,0xe5,0xe5,0x28,0x0d,0xe5,0xe5,0x0e,0x33,0x2c,0x08,0x02,0xe6,0x0e,0x17, + 0x1a,0x37,0xe5,0xe6,0x02,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe7,0x07,0xe5,0x06, + 0xe8,0x05,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x0b,0xe6,0xe6,0x0f,0x09,0x09,0x07, + 0x01,0x09,0x09,0x01,0x05,0x01,0x01,0x07,0x01,0x09,0x07,0x01,0x01,0x0b,0xe6,0xe5, + 0x0e,0x0a,0x03,0x04,0xe5,0x07,0x0a,0x07,0x02,0x01,0x02,0x04,0x09,0x05,0xe5,0x01, + 0x04,0x04,0x10,0x01,0x11,0x4b,0x1c,0xe6,0xe5,0x18,0x09,0x04,0x06,0x07,0x01,0x09, + 0x09,0x09,0x09,0x09,0x02,0x0b,0x02,0xe5,0x0c,0xe6,0x05,0xe6,0x01,0x05,0xe5,0x07, + 0xe6,0x06,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x06,0x04, + 0x03,0x02,0x03,0x09,0x09,0x01,0x07,0x01,0x07,0x09,0x01,0x05,0x03,0x09,0x09,0x09, + 0x09,0x11,0x02,0x0e,0xe5,0x07,0x09,0x09,0xe5,0x07,0x0b,0x02,0x06,0xe5,0xe5,0x05, + 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x0e,0xe5,0x0d,0x09,0x09,0x09,0x09,0x0b, + 0x09,0x09,0x09,0x09,0x0f,0xe5,0x01,0x12,0x06,0x09,0xe5,0x11,0x05,0x05,0xe5,0x37, + 0xe5,0x0d,0x06,0x02,0x09,0x09,0x09,0x08,0x02,0x09,0x09,0x09,0x09,0x0f,0xe8,0x3e, + 0x1d,0x20,0x10,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x0d,0x02,0xe5,0x03, + 0x04,0x1f,0x33,0x20,0x3f,0x3b,0xe5,0xe5,0x17,0x1d,0x08,0x02,0x33,0x05,0xe6,0x03, + 0x13,0x06,0x02,0x13,0x06,0x0b,0x16,0x06,0x13,0x01,0xe5,0x03,0x4c,0x0c,0x1b,0xe5, + 0x01,0x17,0x08,0x14,0x08,0xe5,0x1e,0x13,0x06,0x01,0xe6,0x20,0x1d,0x34,0x06,0xe5, + 0xe5,0x48,0x15,0x07,0x12,0xe8,0x13,0x02,0xe5,0x04,0xe8,0x04,0x09,0x02,0xe5,0x04, + 0xe6,0x08,0xe6,0x06,0x09,0x02,0xe5,0x04,0xe6,0x06,0x09,0xe8,0x0d,0xe5,0x06,0xe6, + 0x05,0xe7,0x08,0x07,0xe6,0x05,0xe5,0x01,0xe5,0x05,0x02,0x09,0x07,0xe6,0x05,0x02, + 0x0e,0xe8,0x25,0x18,0x3b,0x01,0xe5,0x14,0x05,0x03,0x09,0x01,0x07,0x05,0x03,0x07, + 0x03,0x01,0x03,0x05,0x03,0x0d,0x01,0x03,0x0c,0x01,0xe6,0x0a,0x03,0x02,0x01,0x06, + 0xe5,0x07,0x02,0x03,0x03,0x01,0x07,0x08,0x0b,0x04,0x05,0x03,0x0e,0x04,0xe9,0x03, + 0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff, diff --git a/board/esd/cpci405/fpgadata_cpci4052.c b/board/esd/cpci405/fpgadata_cpci4052.c new file mode 100644 index 0000000..7204028 --- /dev/null +++ b/board/esd/cpci405/fpgadata_cpci4052.c @@ -0,0 +1,765 @@ + 0x1f,0x8b,0x08,0x08,0xe9,0xf4,0x75,0x3e,0x00,0x03,0x63,0x70,0x63,0x69,0x34,0x30, + 0x35,0x5f,0x32,0x5f,0x30,0x34,0x2e,0x62,0x69,0x74,0x00,0xed,0x7c,0x0f,0x74,0x14, + 0xd7,0x79,0xef,0x37,0x77,0x66,0xc5,0x68,0x77,0xa5,0x1d,0xad,0x56,0xce,0xda,0x16, + 0xf2,0x68,0x25,0xc8,0xa2,0xae,0xc4,0xb2,0xc2,0x58,0x96,0xc5,0x6a,0xb4,0x92,0xe9, + 0xda,0xe0,0xb0,0x26,0x6e,0xc3,0x6b,0xfd,0x92,0xc5,0x26,0xad,0xfa,0x0e,0x71,0x85, + 0xd3,0xe6,0xa9,0x6e,0x5f,0xdf,0xd5,0x6a,0x31,0x02,0x61,0x58,0xff,0x69,0xa3,0xb8, + 0x24,0x59,0x88,0xda,0x28,0x2e,0xc9,0x5b,0x04,0x01,0x61,0x1c,0x7b,0x50,0x65,0x2c, + 0x40,0x06,0x85,0xfa,0xbc,0x87,0x6d,0x6a,0x2f,0x8e,0xea,0xa7,0x60,0x99,0xca,0x40, + 0x1d,0xf1,0xcf,0x7a,0xdf,0x9d,0x7f,0xbb,0x22,0x89,0xdb,0xd3,0xd7,0x73,0xfa,0xce, + 0x79,0x9e,0xc4,0xc7,0xd7,0xba,0xba,0x33,0xf7,0x7e,0xf3,0xdd,0xdf,0xf7,0xfb,0x7d, + 0xdf,0x1d,0x41,0xa1,0x6b,0x5a,0xff,0x1f,0x00,0xb7,0x0e,0x4a,0x1e,0xed,0x78,0xf4, + 0x0f,0x96,0x06,0xef,0xfc,0x4a,0xe8,0x2b,0xc1,0xa5,0x75,0x8f,0x3d,0xba,0x1e,0x1e, + 0x01,0x7b,0xe8,0xeb,0x4b,0xee,0xfc,0xa3,0x8d,0x4b,0x96,0x2e,0x85,0x47,0xc1,0x11, + 0x0a,0x06,0xeb,0x17,0xe3,0xff,0x97,0xdc,0x05,0xeb,0xa1,0x70,0xc9,0x5d,0x8d,0x4b, + 0x96,0x35,0x2e,0x0d,0xc2,0x57,0x01,0xe2,0x3d,0xb3,0x78,0xbd,0xf0,0xad,0xdf,0xfa, + 0xbd,0x20,0x50,0x0e,0x00,0xe6,0x05,0xb9,0x38,0xfb,0x77,0x41,0x90,0x93,0x39,0xa0, + 0xcd,0xb5,0x41,0x50,0xd9,0x7f,0x83,0xd1,0x5f,0x18,0x04,0x39,0xff,0xbf,0xb9,0x20, + 0x28,0x10,0x03,0xcf,0xd7,0xc0,0x1d,0x84,0x9b,0x2e,0x0e,0x04,0xaa,0xb7,0x3e,0xad, + 0x8f,0xdc,0xdc,0xc5,0xae,0x7f,0x45,0x9f,0xfb,0x57,0x74,0x09,0xff,0xd6,0x3e,0xfd, + 0x5f,0xb3,0x6e,0xf0,0xe0,0xcc,0x38,0x6d,0x45,0x60,0x63,0x0d,0xa9,0x79,0x44,0x1f, + 0xa7,0xda,0x2e,0xc1,0x58,0x72,0x99,0xbc,0x6a,0x0b,0xa9,0x22,0x63,0xea,0x37,0x82, + 0xae,0x3e,0x3e,0x08,0x1d,0xfa,0x8c,0xa4,0xf7,0x68,0xcf,0x80,0xcf,0x27,0x8a,0xa4, + 0x1a,0x7a,0x40,0xa6,0x8e,0xe7,0x13,0x69,0xd0,0xd7,0xdc,0x63,0x9b,0xa4,0xbb,0x64, + 0x19,0x44,0x72,0x9b,0xd8,0xd5,0x93,0x96,0xa3,0x0e,0x42,0x7c,0x9c,0x3e,0x4e,0x2d, + 0x19,0x20,0x3f,0x00,0xec,0x03,0xe2,0xe4,0x7a,0x38,0x9f,0xea,0xa0,0x24,0x23,0xc4, + 0xf5,0xc9,0x94,0xa9,0x70,0x1e,0x0e,0xa8,0x81,0xdd,0xbc,0x0c,0xc3,0x64,0x19,0xb8, + 0x32,0xbc,0x24,0xe8,0xe3,0xb2,0x5c,0x1a,0xde,0x81,0x57,0x54,0x57,0x96,0xbf,0x0c, + 0x7f,0x0e,0x77,0x50,0xd7,0x34,0x3f,0x03,0xfa,0x38,0x45,0x1a,0x80,0x13,0x10,0xca, + 0x16,0x0d,0xf0,0x7e,0xbc,0x41,0x48,0x71,0xa6,0x71,0x9c,0xac,0xf5,0x8d,0xda,0xfc, + 0xf0,0x1b,0x31,0x5f,0x56,0x1c,0x20,0x01,0x38,0x2f,0xf8,0x54,0x31,0xcd,0x3f,0x8e, + 0xef,0x4f,0xbb,0xa7,0xad,0x0d,0x7a,0x14,0x19,0x0a,0x25,0x02,0xb6,0x5d,0xd0,0xce, + 0x89,0x29,0x32,0x84,0x76,0x60,0x97,0xcc,0x2d,0xa3,0x7b,0xd2,0x95,0xd5,0xe2,0xef, + 0x92,0x5b,0x1e,0xfa,0x21,0xad,0x4c,0x8b,0x6b,0xc9,0x5a,0x63,0x5c,0x34,0xea,0x4a, + 0x1d,0x49,0xef,0x5e,0x54,0x74,0x9b,0xc3,0x4e,0xcf,0xa5,0x83,0x71,0x67,0x0f,0x6f, + 0x9a,0x58,0x99,0xbf,0x47,0xf9,0x67,0x29,0x0c,0xae,0xf1,0xd6,0xeb,0xb0,0x44,0x6a, + 0x3e,0xb6,0x78,0xb4,0x7e,0xbc,0x40,0x9f,0xe7,0x80,0x6d,0x02,0x8e,0xc3,0x8b,0xaa, + 0x33,0xc3,0xfb,0xe0,0x44,0x32,0x24,0x07,0x32,0x55,0x35,0x86,0x3d,0xa3,0x25,0xcf, + 0x09,0x4f,0x42,0xa5,0x2a,0x4e,0x47,0x96,0xc2,0x66,0xa8,0xa2,0xe2,0x34,0x71,0x1b, + 0x76,0x51,0xe1,0x3b,0xf0,0x4d,0xba,0x28,0xdb,0xde,0x59,0xf0,0xbc,0x63,0x33,0xad, + 0x8c,0x17,0xb6,0x93,0x0e,0xd0,0xd7,0x17,0xf5,0x4c,0x91,0xc3,0xd4,0x77,0x56,0xbc, + 0xbb,0xc0,0x09,0xdd,0x20,0xab,0x85,0x7e,0xfb,0x1a,0x41,0x7f,0x0f,0x93,0x65,0x93, + 0xf0,0xd6,0xae,0xc6,0xcc,0xb6,0xf4,0x3c,0xbf,0x70,0x9c,0x84,0x68,0xd1,0x0b,0xfc, + 0x13,0xc6,0x3d,0xa3,0x90,0x26,0x3d,0x80,0xf3,0xa4,0x8e,0x2c,0xcc,0x60,0xa3,0x58, + 0xe5,0x9f,0x31,0xde,0x9f,0x28,0x4d,0x90,0x63,0x74,0x50,0x81,0x14,0x59,0x0f,0x3f, + 0x87,0x70,0xcb,0xbc,0xa7,0x79,0x62,0xdc,0x93,0x0a,0xeb,0x61,0x0b,0xec,0x8e,0x89, + 0xcf,0xe1,0x7b,0x3f,0x24,0xd4,0x29,0x8e,0x9d,0x44,0x06,0x49,0xeb,0xf3,0xda,0x96, + 0x92,0xa7,0xe4,0x2a,0xc5,0x1e,0xb3,0xef,0x17,0x7f,0x02,0x8b,0x15,0x47,0xac,0xa0, + 0xc0,0xb0,0x99,0x28,0x78,0x60,0x13,0x54,0xc6,0xed,0x6b,0x89,0x07,0x7e,0x0c,0xb5, + 0xca,0xed,0x6b,0x09,0xe1,0x74,0x9b,0x0d,0x15,0x1d,0x51,0xd4,0x35,0x41,0x4f,0xdd, + 0x26,0x7e,0x57,0x5b,0x76,0x4d,0xd8,0xe3,0x7a,0xd5,0x51,0xc7,0xeb,0x76,0xe9,0x9b, + 0x3f,0x51,0x70,0x05,0xc2,0x4a,0x51,0x6a,0xe5,0x7a,0x60,0x8d,0x95,0x29,0xfe,0xfd, + 0x82,0x0e,0xe3,0x79,0x97,0xe1,0x86,0x50,0xaf,0xdc,0x31,0xce,0x57,0xc3,0x35,0x21, + 0xac,0xb8,0xc6,0xf9,0x85,0x86,0x3d,0x1b,0xa4,0x6c,0x72,0x08,0x88,0x28,0x26,0x88, + 0x4c,0x87,0xe4,0x3a,0xd1,0xb1,0x9b,0x6c,0x37,0xd6,0x20,0xda,0x46,0xe4,0xbd,0x7e, + 0x39,0x62,0x97,0x12,0x82,0xbc,0x57,0x0c,0x3c,0xe2,0x90,0x12,0xc4,0xf0,0x4f,0x6f, + 0x59,0xbf,0x77,0xaf,0x22,0x2b,0xd1,0x4c,0xc1,0x42,0xe9,0x10,0x14,0x2b,0x0e,0x89, + 0x3c,0x69,0xd8,0x2c,0x2d,0xf5,0xe3,0x14,0x7c,0x8a,0x2b,0xe5,0xa8,0x16,0xaf,0x10, + 0x7c,0xde,0x73,0xbc,0xdf,0xf0,0x33,0x3f,0xfc,0x8d,0x72,0x05,0x5e,0x56,0xe6,0xa5, + 0xf8,0x09,0x6d,0x9e,0xae,0x14,0x7f,0xdc,0x78,0x47,0x7e,0x29,0x1d,0x1f,0x85,0x10, + 0xda,0x9a,0x4f,0xa3,0xad,0xb1,0x91,0x74,0xd8,0xcd,0x71,0xc2,0xdd,0xb0,0x1d,0xaa, + 0xba,0xc4,0x2c,0xfa,0xee,0x8b,0x9c,0x8f,0xae,0xcc,0x46,0xec,0x86,0x2f,0xf9,0x6d, + 0x5f,0xe0,0xba,0x21,0xad,0x8a,0x19,0xb2,0x0d,0xf6,0x81,0x5f,0xc5,0xb9,0xd8,0x2d, + 0xff,0x0c,0x73,0xe8,0x2f,0x8a,0x18,0x73,0x97,0xf7,0x1c,0x4c,0x2f,0x1a,0xbd,0x3d, + 0x46,0x44,0xc3,0xd6,0x7e,0xb1,0x02,0x4e,0xd1,0xfa,0x74,0xf1,0x24,0xff,0x5d,0x3a, + 0x9b,0xbe,0x7b,0xe6,0x2b,0x93,0xa5,0x76,0x03,0x57,0xc4,0xf9,0xdb,0x4a,0xaf,0xe2, + 0xeb,0x7e,0x99,0xf2,0x53,0x70,0x4f,0x6c,0xd9,0xb0,0x2b,0xcd,0x0f,0x1b,0xfe,0xa9, + 0xd8,0x3e,0x81,0x13,0xa9,0xaf,0x4f,0x3a,0x0f,0xb9,0x4f,0xc1,0xa9,0x9f,0x86,0x27, + 0x9c,0x7d,0xfc,0xb8,0x61,0xcf,0x81,0x92,0xff,0x41,0x13,0xe9,0xaa,0xf5,0xb8,0x0d, + 0x2a,0x68,0x37,0xad,0xcd,0x62,0xe3,0xbc,0xb9,0x6f,0x61,0xe7,0xf0,0x0e,0xa9,0x92, + 0x16,0x3e,0xe2,0x5b,0xde,0xb3,0x19,0x16,0x8f,0xae,0x5d,0x4f,0x46,0xa8,0xbe,0xbe, + 0xb8,0x67,0xcc,0x9d,0x40,0x3b,0x14,0x52,0xe2,0x14,0xba,0x21,0xa0,0x8a,0x7e,0x72, + 0x26,0xa9,0xbf,0x87,0x81,0xb2,0x34,0x1c,0x83,0x41,0xf5,0x81,0x0c,0xff,0x67,0xde, + 0x53,0x64,0x39,0xdb,0x18,0x17,0x92,0xfa,0x3d,0x29,0x9c,0x83,0x2b,0x4a,0x78,0xbc, + 0x78,0xbf,0x63,0x0a,0xde,0x86,0x70,0xd6,0xb5,0xb7,0x34,0x6b,0xf8,0x27,0x17,0xbb, + 0x24,0x9d,0xa2,0xfb,0xb2,0xab,0x2e,0xb6,0x36,0x09,0xa7,0xa0,0x59,0x15,0x66,0xf8, + 0x89,0x36,0xbd,0xaf,0x4b,0x58,0x07,0xbd,0x3d,0xbe,0xa3,0xfe,0x21,0xe2,0x84,0x5e, + 0xa8,0x3b,0x12,0xdd,0x9f,0xc8,0x2a,0xba,0x7f,0x52,0xdb,0x2a,0xe8,0x5a,0x20,0xab, + 0x7d,0x19,0x7b,0x80,0xf5,0xa9,0xf6,0x41,0x92,0x35,0xec,0x29,0x0a,0x45,0x72,0xd7, + 0x7a,0x79,0x54,0x0c,0x92,0x5a,0xb9,0x5b,0xae,0x3b,0xb3,0x35,0x44,0x86,0x8d,0xd5, + 0x41,0xe1,0xd7,0xe0,0x44,0x74,0xf0,0x2d,0xe7,0x32,0x7e,0xb9,0x70,0x6a,0x7d,0xf3, + 0x78,0xf1,0x81,0xee,0x2c,0xd1,0xef,0x99,0x9e,0x3f,0x95,0xf8,0x85,0x5c,0x71,0xdc, + 0xf5,0xf1,0xf7,0xae,0xd3,0x6b,0x4d,0xcb,0xcf,0x14,0x5d,0xec,0x9e,0x34,0xfc,0x53, + 0xb5,0x4d,0x29,0xef,0x76,0x85,0xcf,0xb9,0x2e,0x95,0x7e,0xa2,0x5c,0xa3,0xf5,0xd9, + 0x3b,0x66,0xf8,0x69,0x0b,0x3f,0x6f,0x24,0x0f,0x27,0xea,0xb2,0x2b,0xbf,0x4e,0xc6, + 0xe8,0xe1,0x17,0x7c,0x59,0xc7,0x10,0xc9,0x0a,0x26,0x7e,0x8e,0x29,0xfb,0xd0,0x54, + 0x8e,0x20,0xf6,0xed,0x13,0xd2,0xac,0xf1,0x9e,0x89,0x9f,0x65,0x7b,0xe0,0x30,0x4e, + 0x7d,0x65,0x86,0x4c,0xc1,0x3e,0xc4,0x4f,0x6c,0x4c,0x1b,0xef,0x41,0x29,0x9b,0x92, + 0xd0,0x54,0xea,0xea,0x0c,0x37,0x05,0xd7,0x20,0x84,0x7d,0xad,0xe3,0x16,0x7e,0xbe, + 0x04,0xaf,0xa0,0xa9,0x5c,0xd3,0x55,0xd7,0x61,0x56,0x6b,0xe4,0xe1,0xe7,0x1e,0xee, + 0x03,0x1c,0xe7,0xcc,0x94,0x4e,0x91,0x13,0xd8,0xa8,0xcb,0xf0,0xe3,0x46,0x7c,0x18, + 0xb5,0x35,0x31,0x53,0x4d,0xd8,0xa7,0x49,0x40,0xc4,0xc6,0x2f,0x8a,0x32,0xe4,0xa2, + 0x85,0x9f,0xab,0xe0,0x7b,0x10,0xc8,0x16,0x06,0xc9,0x2a,0x78,0x56,0x0e,0xa8,0xde, + 0x20,0x99,0xb1,0xfc,0xb3,0xa2,0x67,0x73,0xa2,0x36,0xeb,0xf8,0x13,0x52,0x01,0xdf, + 0x4c,0xd5,0x66,0xb9,0x4e,0x32,0x6a,0xe2,0xa7,0x58,0x07,0xdf,0xa3,0x4d,0xef,0x15, + 0x35,0x96,0x7e,0x61,0xfc,0xef,0xd3,0x4d,0x53,0xce,0x7b,0xf8,0xd3,0x86,0x7f,0x2a, + 0xf3,0x7f,0x08,0xd7,0xa4,0x26,0xf5,0x64,0x86,0xdf,0x00,0x1f,0x40,0x93,0x8a,0x31, + 0x20,0x87,0x9f,0x17,0x12,0x27,0x84,0xb0,0xfa,0xc0,0x8b,0x2b,0x03,0xda,0xfa,0xb0, + 0xef,0xbc,0x85,0x9f,0x4f,0x51,0x74,0x3d,0x55,0xbc,0x9c,0x28,0x87,0x83,0xb0,0x48, + 0x75,0x74,0x90,0xd3,0x39,0xfc,0xa4,0x9b,0xe9,0xe2,0x6c,0xe1,0x13,0x91,0x0a,0x38, + 0x48,0x2b,0xb3,0x8e,0x4e,0x32,0x6d,0xbc,0xda,0xa8,0x67,0x0c,0x61,0x33,0x70,0x24, + 0x1a,0x8c,0x38,0xd1,0xb0,0x7e,0x66,0xeb,0xd3,0x16,0x7e,0x0e,0x20,0x5e,0x87,0x69, + 0x51,0x1a,0xf7,0xe6,0x55,0xf0,0x51,0xdc,0x2b,0x57,0x2d,0xfc,0xd4,0x61,0x13,0xf7, + 0xb4,0xd6,0x90,0x5c,0xb4,0xf4,0x74,0x0e,0x3f,0xe1,0x0a,0x1f,0x56,0x8a,0x75,0x2c, + 0x08,0xad,0x47,0x2c,0x18,0xce,0xc3,0xcf,0x43,0x5c,0xa0,0x03,0x43,0xcd,0x04,0x1c, + 0x82,0xdd,0x8a,0x23,0x85,0x3e,0x68,0xe2,0x27,0x42,0x2a,0xd4,0xad,0xb5,0xeb,0x7d, + 0x3e,0xd6,0x77,0xd4,0xc2,0x4f,0x81,0x2e,0x11,0x02,0x8a,0xe8,0x26,0x23,0xb0,0x17, + 0x71,0x1e,0xb1,0x60,0xd8,0xc2,0xcf,0x75,0x4a,0x27,0xce,0x65,0xfb,0x26,0xfe,0x9c, + 0x32,0x1d,0x63,0x40,0xf3,0xe8,0x05,0x5e,0x7f,0x0f,0x88,0x9f,0xca,0x15,0x06,0x8d, + 0x4f,0xb3,0xb9,0xcc,0x0b,0x33,0x80,0xca,0xe1,0xe7,0x84,0x7c,0x0c,0x9a,0x95,0xd5, + 0xa9,0xee,0x09,0xb8,0xa1,0xd4,0x2b,0xce,0x14,0x7f,0xd4,0xc2,0xcf,0x73,0x89,0x1e, + 0x52,0x07,0x7c,0x32,0x92,0x45,0xfc,0xac,0x01,0x91,0x92,0x93,0x79,0xf8,0xd9,0x05, + 0x7e,0xc5,0xe1,0x4e,0x20,0x90,0x82,0xac,0x88,0x6c,0x2e,0xc6,0x3d,0x4b,0xfa,0xc5, + 0x2d,0x50,0xc7,0xa6,0x3e,0x21,0xee,0xc5,0x86,0x1f,0xd7,0x60,0xe2,0x67,0xd9,0x04, + 0xee,0xf7,0x46,0x06,0xe1,0x13,0xc2,0x15,0x16,0xa7,0x53,0xfc,0xa4,0xe1,0x9f,0x7e, + 0x2e,0x09,0x1a,0xa4,0xea,0x36,0x6b,0xd4,0xf1,0x53,0x5f,0x3b,0xe2,0xa7,0x30,0xc3, + 0x85,0x61,0x35,0x45,0x5e,0x30,0x4a,0x31,0x56,0x51,0xfe,0xb8,0x89,0x9f,0x18,0xdf, + 0x5f,0x84,0xc5,0x83,0x8e,0x34,0xf1,0x0b,0xef,0x70,0xb5,0x43,0xd1,0x34,0xb1,0xc6, + 0xa1,0x7f,0xe2,0x3e,0xea,0xc1,0x57,0x8a,0xb1,0x51,0x0a,0x44,0xec,0xc1,0xc8,0x71, + 0xc3,0x3f,0xd3,0x5c,0xb9,0x78,0x17,0xa9,0xa5,0x8e,0x06,0x7c,0xe8,0x37,0xa1,0x96, + 0xfa,0x3b,0xc8,0xa4,0x31,0x6e,0x40,0xac,0x48,0xff,0x82,0x2e,0xcf,0xba,0x3a,0xf9, + 0x70,0xfa,0x35,0xba,0x5c,0x2e,0xee,0xe4,0xcf,0x5b,0xf8,0xf9,0x43,0x7a,0x8d,0x84, + 0x8f,0xb8,0x0e,0xf0,0x1f,0x0a,0xd7,0xa0,0x89,0x71,0x94,0x61,0xa2,0xaf,0x0f,0x6c, + 0x9f,0xc4,0x4f,0x25,0xc3,0xe9,0xd5,0x3f,0xe9,0xfe,0x91,0x72,0x32,0x15,0x92,0x8b, + 0x86,0x78,0xd5,0xc2,0xcf,0xef,0x24,0xba,0x9f,0xae,0x4d,0xe3,0xf3,0xea,0xc8,0x8e, + 0x4d,0x7e,0x59,0xbc,0x27,0x1f,0x3f,0x61,0xb3,0x1b,0xe7,0x12,0x24,0x3b,0xe9,0x93, + 0x72,0x25,0x6c,0xe9,0x70,0xab,0x92,0xbe,0x3e,0x59,0xf7,0x4f,0xaa,0xaf,0x01,0xc3, + 0x0c,0x02,0xd4,0xa8,0x60,0xe2,0xe7,0x4b,0xc8,0x7b,0xc2,0x48,0x85,0xaa,0x5e,0x42, + 0xc3,0xfa,0x00,0xf7,0xa6,0x79,0x4f,0x0a,0x53,0xe2,0x35,0x2e,0x9c,0x5a,0x9d,0xe1, + 0xa7,0xd0,0xd6,0x68,0xbc,0x4c,0x0e,0x3f,0x25,0x84,0x00,0xae,0x99,0xee,0x98,0xe6, + 0xaf,0xc3,0x0d,0xb8,0x0b,0xec,0xd3,0xbc,0x6a,0xe1,0xe7,0x06,0x86,0x2f,0xff,0xd3, + 0x81,0xf8,0x22,0x1c,0xc2,0x01,0x18,0x7c,0x72,0xf8,0x19,0x80,0xc3,0x5c,0x5d,0x17, + 0xeb,0x83,0x41,0xea,0xbb,0xd5,0x8e,0x7d,0x96,0x7f,0x3a,0x95,0xfa,0x78,0xa0,0xd7, + 0xb1,0x74,0x78,0x2c,0xbe,0x4f,0x96,0x9d,0xf6,0x65,0x96,0x7f,0x42,0xd1,0xc3,0xf2, + 0x35,0x08,0xf7,0xb8,0x2e,0xf2,0x37,0xe8,0x55,0xf4,0xcf,0xe2,0x0c,0xaf,0x1a,0xfe, + 0x99,0xbe,0x15,0xa1,0x4a,0x6a,0xb6,0xf3,0x17,0x79,0xc4,0xcf,0xf5,0x77,0x4b,0x45, + 0x1f,0xf1,0x39,0xfc,0xfc,0x04,0x66,0x4b,0xee,0x91,0x1f,0xb8,0x54,0x58,0xa7,0x8e, + 0xd1,0x3f,0x9f,0x71,0x36,0xe4,0xe1,0xe7,0x8f,0xa4,0x83,0x1d,0xbe,0xb8,0xe3,0x12, + 0x59,0x10,0xeb,0x95,0xeb,0x46,0xec,0x43,0x88,0x83,0x06,0x7e,0x0a,0x63,0x80,0x53, + 0xc8,0xa2,0xcd,0x44,0xd2,0x5d,0x18,0xf8,0x39,0xda,0xec,0x62,0x3e,0x7e,0x0a,0x08, + 0xb7,0x19,0xe2,0x23,0xbd,0xb4,0xf8,0x55,0x7b,0x0e,0x3f,0xc1,0xa6,0xc1,0x66,0x1c, + 0x5f,0x69,0x00,0x56,0x8e,0xd6,0xa5,0x31,0x1e,0xa9,0x26,0x7e,0x96,0xbc,0x24,0xce, + 0xc2,0x2b,0x0a,0xc2,0xe6,0x04,0xcc,0xf2,0xcb,0xe7,0xf2,0xcf,0x3d,0x26,0x1c,0x8d, + 0x49,0xf8,0x42,0xba,0x9c,0x99,0x3c,0xfe,0x19,0x10,0x5f,0x01,0x7c,0xde,0x34,0xee, + 0x69,0xc4,0xcf,0x2e,0x7c,0x47,0x21,0xc3,0x66,0xaa,0xc0,0x20,0x47,0xce,0xde,0x9e, + 0x29,0xd0,0x80,0xb4,0x45,0x0c,0xba,0x1b,0x4c,0xfc,0x94,0x2a,0xfa,0x10,0xaa,0x26, + 0x11,0xaa,0xde,0x69,0xfb,0x3e,0x0d,0xb4,0x17,0x3e,0x41,0x9a,0x24,0x7d,0x5c,0x54, + 0x2c,0xa6,0xfb,0x20,0x78,0xde,0x15,0xe4,0x8f,0xd3,0x9f,0xa5,0x9b,0xda,0x9d,0x8d, + 0xbc,0xdb,0xc4,0x4f,0xcf,0x4b,0x38,0x97,0x57,0x46,0x5c,0x97,0xbb,0x26,0x0b,0xde, + 0x96,0x9a,0x95,0x3c,0xfc,0x14,0xd9,0xfa,0x64,0xf4,0xdd,0x41,0x86,0xad,0x5c,0xe8, + 0x08,0xce,0xf3,0xbc,0xb1,0xbe,0x28,0xb7,0x13,0x0e,0x46,0x6b,0x55,0x47,0x08,0xfd, + 0x6c,0x07,0x04,0xd5,0xad,0x1d,0xe4,0xa2,0x61,0x17,0x19,0xf9,0xe7,0xc1,0x34,0x62, + 0xf9,0x13,0xe4,0xcb,0xf0,0x7d,0xfa,0xd5,0xac,0xd8,0x89,0xef,0x5d,0x5f,0x5f,0x3b, + 0xfa,0xa7,0x11,0xab,0x9c,0x52,0x37,0x95,0x55,0x7b,0x1e,0x7e,0x0a,0x03,0x08,0x9b, + 0xcd,0x0c,0x36,0x3b,0xe1,0x42,0xf4,0xae,0x64,0x00,0xf1,0xd3,0xb0,0x59,0x54,0x62, + 0x54,0x28,0x2c,0x23,0x7e,0xbe,0x07,0x33,0xa2,0x06,0xa4,0x39,0xfc,0xec,0x87,0x37, + 0xa1,0xb1,0xbd,0x48,0xe2,0x93,0x70,0x4c,0x08,0x22,0x4e,0x70,0xc3,0x60,0xe2,0x67, + 0x35,0xec,0xe5,0xe4,0x38,0xe2,0x67,0x35,0x74,0x91,0xdd,0x8a,0x78,0x33,0x7e,0xd6, + 0x28,0x85,0x29,0xd2,0x0f,0x5b,0x38,0x5f,0x8b,0x38,0x07,0x3f,0x61,0x6f,0xb5,0x8f, + 0xe1,0xa7,0x40,0xb7,0x40,0x3c,0x2a,0xe6,0xe1,0xe7,0xfc,0x38,0xcc,0xc4,0x1a,0xa1, + 0x08,0xf9,0xa7,0x32,0x1a,0x0b,0x79,0x02,0x94,0x37,0xf1,0x73,0x68,0x3e,0xc2,0x91, + 0xd4,0x7c,0x04,0xf1,0xf3,0xf2,0x1a,0x8c,0x9b,0x6d,0xae,0x1c,0x7e,0x36,0x20,0x9f, + 0x7f,0xb3,0xa5,0x19,0x29,0x62,0x62,0x22,0x7d,0x9f,0xb4,0x6c,0xd4,0x39,0xee,0x7b, + 0xdf,0xf0,0x4f,0x2f,0x64,0xa5,0x21,0xa5,0x0e,0x1c,0x4f,0x26,0x14,0x4a,0x41,0xb6, + 0xfb,0x73,0xf8,0x19,0xb5,0x25,0x61,0x6f,0x3c,0xa0,0xdc,0x8a,0x58,0x9e,0x46,0x32, + 0xbd,0x4a,0x94,0xe0,0xb4,0x89,0x9f,0x9e,0x7e,0x16,0x03,0xe2,0x2b,0x53,0xc2,0x7a, + 0xb2,0x05,0x63,0x80,0x37,0x0f,0x3f,0x85,0x7e,0xef,0x9b,0x10,0x8e,0x17,0xa5,0xd6, + 0xfd,0xe3,0xd2,0x23,0xc9,0x6f,0xb4,0xac,0x4a,0xb5,0x9a,0xf8,0xd9,0x2e,0xb1,0x71, + 0x1a,0x7e,0xb6,0x49,0x48,0x9c,0x58,0xe3,0x2d,0xc3,0xd6,0x7e,0xcd,0xd6,0x3e,0xa9, + 0x88,0xb6,0x56,0xc2,0x68,0x24,0x04,0x47,0x69,0x95,0x89,0x9f,0xa2,0xe0,0x87,0x97, + 0xc1,0x37,0x20,0x66,0x89,0x1f,0xb6,0x62,0x8c,0x2b,0xce,0x5a,0xf8,0x29,0x22,0x7e, + 0x3e,0x8b,0xfe,0x89,0xf1,0x7d,0x1b,0x62,0x4f,0x8d,0x5a,0x28,0x93,0xe3,0x56,0x7c, + 0x2f,0x17,0x0e,0xa6,0xab,0xb2,0x85,0x9d,0xe4,0x2c,0x6c,0x96,0x17,0x8d,0x88,0x71, + 0x0b,0x3f,0xfd,0xde,0x0a,0xd8,0x37,0x50,0x9f,0x7d,0xe0,0x4f,0xab,0xbe,0x4b,0x5f, + 0x7b,0xe1,0xee,0xac,0xab,0x3d,0x0f,0x3f,0x71,0xff,0x75,0xbc,0xac,0x16,0x0f,0xf2, + 0xb5,0xe8,0xa8,0xcb,0xc6,0x17,0xe7,0xf8,0x67,0x5c,0xf8,0x11,0x30,0x9a,0xb4,0xe3, + 0x4a,0xf7,0xac,0xf2,0x41,0x5f,0xf3,0xe5,0x40,0x7b,0x95,0x64,0xe2,0xa7,0xb4,0x7d, + 0xe4,0x20,0x95,0x27,0x0b,0x67,0x48,0xb8,0xba,0x9b,0x2e,0x9e,0xf4,0xb6,0x93,0x9a, + 0x3c,0xfc,0xfc,0xa6,0x5c,0x39,0x8a,0x7b,0x0c,0x9d,0x18,0x6a,0x55,0x31,0x5e,0x53, + 0x60,0xf8,0xa7,0xe2,0xd9,0x26,0xec,0x23,0xb2,0xda,0x1b,0x24,0xc5,0x52,0xa9,0x8a, + 0xfc,0x53,0x26,0x5e,0x13,0x3f,0x6d,0x7b,0xe0,0x5d,0x08,0xbd,0x31,0x6f,0x9a,0x7f, + 0x19,0x66,0xa3,0xcd,0xaa,0x33,0x7d,0x7b,0x9d,0xc5,0xf5,0x19,0x16,0x84,0xd5,0xa2, + 0x0c,0xbf,0x07,0x18,0x39,0x72,0xa5,0xe7,0xe0,0xe7,0x35,0x68,0xce,0xba,0xa6,0xed, + 0xe5,0xe4,0x54,0xe1,0x72,0x15,0x8d,0x67,0x72,0x37,0x03,0x3f,0x55,0xc4,0x17,0xe4, + 0x98,0xa4,0x4e,0x2d,0x4a,0xfb,0x4c,0xff,0xa4,0x36,0xd6,0x57,0x33,0x82,0x5b,0x64, + 0x0f,0x72,0xa9,0xc7,0x54,0x7b,0x3a,0x87,0x9f,0x92,0x53,0xde,0x27,0x06,0x46,0x1d, + 0xa1,0x82,0x6d,0xe9,0xee,0x75,0x81,0x9f,0xf2,0x0b,0x13,0x16,0x7e,0x8a,0x1b,0x90, + 0xbb,0x35,0xaa,0xc5,0x17,0xb9,0x9f,0xa8,0xa7,0xe4,0xe6,0xd1,0xe2,0x7e,0x3e,0x6b, + 0xe2,0x67,0xd9,0x75,0x79,0x16,0xc2,0x6b,0x90,0x1e,0x6f,0x10,0x67,0xe3,0xe1,0x31, + 0x24,0x2b,0x93,0x11,0x0b,0x3f,0x3d,0xd3,0xc9,0xc3,0x72,0x51,0x94,0x34,0xc0,0x25, + 0x7a,0x57,0xb6,0x18,0xf9,0xa7,0xe1,0x2f,0x14,0x2e,0x88,0x43,0xd4,0x27,0xa3,0x5b, + 0xfa,0x00,0x05,0x24,0xe3,0x9f,0xd3,0x96,0x7e,0x1f,0x83,0x0c,0x0b,0x35,0x80,0x12, + 0x71,0x1f,0xf4,0xb3,0xcd,0x9d,0x8f,0x9f,0x38,0xce,0x27,0xf6,0x3c,0x33,0x00,0xf7, + 0x80,0x8f,0x2d,0x34,0x1f,0x3f,0xaf,0xa4,0x1b,0x82,0x45,0x4e,0xfe,0x07,0x70,0x09, + 0x96,0xa9,0xc5,0x19,0x62,0xea,0x07,0xc4,0x4f,0xe7,0x75,0x68,0xe6,0x76,0x8c,0xf3, + 0x7f,0x60,0xf2,0xcf,0xeb,0x79,0xf8,0x89,0xfb,0x1d,0x9c,0xc9,0xee,0x01,0x8d,0x7f, + 0xba,0x32,0xe4,0x0d,0xe3,0xfd,0x21,0x7e,0x52,0x4a,0x6b,0x0a,0xc4,0xe7,0xc9,0x00, + 0xe2,0xa7,0xf6,0xbc,0x8b,0x39,0xfc,0x14,0x52,0x6e,0x3f,0xe2,0xa1,0xd2,0x83,0xf8, + 0xa9,0x71,0x37,0x93,0xd7,0xc9,0x4a,0x05,0x6c,0xa3,0x8b,0x64,0xf1,0x18,0x79,0x3e, + 0xf9,0x7d,0x06,0xa4,0x4f,0xc0,0x75,0xa3,0x2f,0xea,0x75,0xc2,0x78,0xba,0x41,0x0e, + 0xd8,0xf9,0xde,0xe4,0xcf,0x92,0x0d,0x93,0x2e,0xe4,0x9f,0x05,0x7a,0x9f,0x52,0xbe, + 0x13,0xae,0x56,0x2e,0x87,0x1d,0x09,0x7e,0x52,0x79,0x1b,0x8d,0xee,0x42,0x0e,0x5d, + 0x60,0xec,0x95,0xb2,0x29,0x61,0x1a,0x96,0xb5,0x6c,0xa5,0x3c,0x03,0xfc,0x85,0x0c, + 0xf0,0x87,0x4d,0xfe,0x79,0x5f,0x39,0xec,0x27,0x95,0x8a,0x4d,0x25,0x5e,0xf4,0xc1, + 0x4a,0xe4,0x9f,0x70,0xd1,0x58,0x9f,0x0c,0x15,0xb0,0x9f,0x2e,0x96,0xed,0x51,0x82, + 0x40,0x4a,0x17,0x30,0xfe,0x79,0xc6,0x98,0x4b,0x3b,0xc6,0xaa,0xcc,0x1a,0x7f,0x62, + 0x4b,0x6d,0x82,0xd9,0xba,0x9a,0xad,0xe1,0xad,0x3c,0xfe,0xf9,0xb1,0xba,0xbc,0xa7, + 0x22,0xcb,0x7f,0x4b,0xbe,0x0a,0xcb,0xa8,0x83,0xe1,0xa7,0x3e,0x17,0xd4,0xef,0x30, + 0x24,0x2e,0x2c,0xb9,0x23,0x59,0x1a,0x4f,0xcd,0xa0,0xf1,0x5c,0xb4,0xea,0xb4,0xb9, + 0xa7,0x19,0xff,0x4c,0x84,0x62,0xfc,0xf3,0x7c,0xb5,0x74,0x2c,0xb2,0x90,0x71,0xbe, + 0x61,0xa3,0x8f,0x0a,0x0b,0x94,0x43,0xf4,0x85,0xb5,0x3d,0x5e,0xc4,0xcf,0x5d,0xd4, + 0xa7,0xf3,0x4f,0xfd,0xd2,0xf0,0x53,0xaa,0x41,0x48,0xb5,0x57,0x9b,0x24,0x6e,0x0e, + 0x7e,0x22,0xb6,0x8a,0x92,0xbd,0x3a,0x59,0xc9,0xc8,0x1f,0xc3,0x4f,0xfd,0x9e,0x43, + 0xf3,0xdb,0x11,0xe7,0x1b,0xa1,0xf6,0xaf,0x19,0x3f,0xd3,0x49,0xf1,0x85,0x79,0x39, + 0xfc,0xbc,0x01,0xcb,0x95,0xa2,0x71,0xfe,0xb2,0xf2,0x11,0xdc,0xc2,0xe6,0x72,0xc1, + 0xc2,0xcf,0xfd,0xf0,0x0f,0x64,0xb9,0xe2,0x8c,0x71,0xd5,0xf2,0x3f,0x40,0x85,0x72, + 0x47,0xaa,0xea,0x82,0xe1,0x83,0x88,0x9f,0x30,0x84,0xae,0x59,0x44,0xa1,0x12,0x7a, + 0x00,0x81,0x94,0xe2,0x5c,0x0c,0xfc,0x14,0x92,0xc2,0xb7,0xa0,0x5a,0xf1,0xbb,0x13, + 0xd5,0xe4,0x69,0x08,0x28,0x76,0x89,0x9c,0x36,0xe6,0xe2,0x8d,0xf5,0x6b,0xd4,0xb9, + 0x10,0xd7,0x40,0xd9,0x1a,0x56,0x32,0xfc,0xd4,0xfb,0xd2,0x6d,0xfd,0xc2,0x4f,0xe9, + 0xd2,0x3f,0xf1,0x78,0xb9,0x6a,0x74,0xb8,0x3f,0x67,0x18,0x39,0x69,0xc6,0xb1,0x12, + 0xd4,0xf6,0xfe,0x70,0xc7,0x1d,0xcf,0x39,0x18,0xff,0xd4,0xfa,0xde,0x32,0x39,0xa6, + 0x24,0xcb,0xa8,0xdf,0xbd,0x2e,0xda,0x9a,0xd6,0xd6,0xf7,0x54,0x8e,0x7f,0x8a,0xb6, + 0x46,0x28,0x56,0xaa,0x32,0xf6,0xf7,0x71,0xaf,0xbc,0xd3,0x56,0x87,0xbf,0x12,0x31, + 0x75,0xa3,0x68,0x5b,0x01,0x5d,0x0f,0xca,0x9b,0x6e,0x0d,0x24,0x9c,0xb0,0x3b,0xab, + 0x05,0xc9,0xe1,0x9c,0x3e,0xf2,0x3d,0x05,0xeb,0x90,0x7a,0x91,0x97,0xe0,0x2f,0x8b, + 0xbe,0xc6,0xf4,0xca,0xa8,0x89,0xd7,0x5e,0x37,0x42,0xf4,0x12,0xb9,0xa8,0x93,0xaf, + 0x80,0x09,0x3a,0x3f,0xfb,0xed,0x4e,0x2b,0x97,0x20,0xce,0xa7,0x30,0x8d,0x88,0xbd, + 0x38,0x33,0x6f,0x4c,0x9a,0x81,0x0a,0x14,0x7b,0x7c,0xe4,0x16,0x7d,0x5c,0x5c,0x78, + 0x1e,0xa6,0xe8,0x8b,0xeb,0xeb,0x3a,0xab,0x2a,0x50,0xc8,0x37,0x4f,0xb8,0x66,0xf8, + 0x33,0xc6,0x3c,0x07,0xa0,0x2f,0x99,0x94,0x97,0xca,0x45,0x41,0x7b,0x31,0xdd,0xbc, + 0x2b,0x90,0x45,0x22,0x7a,0x9e,0xc8,0x86,0xd3,0xa7,0x0a,0xf6,0xc0,0x22,0xa7,0xe3, + 0x23,0xd2,0x44,0x37,0x05,0x6b,0x47,0x71,0x2e,0x47,0x15,0xbd,0x4f,0xf1,0x50,0xa0, + 0x4a,0xbf,0x5c,0xb8,0x94,0x14,0x91,0x2e,0x2d,0xd0,0xfb,0xc6,0x0d,0x6d,0x3f,0x80, + 0x9c,0x3d,0xab,0x36,0x90,0xe2,0xfd,0xbc,0x8b,0x24,0x04,0xb6,0x6f,0xf9,0x0b,0x54, + 0x9f,0x4b,0x1a,0x7d,0x70,0x26,0x16,0x96,0x16,0xff,0x98,0x9f,0x52,0xae,0x46,0xc2, + 0xea,0x8e,0x4c,0xd5,0xa4,0xa5,0xdf,0xa7,0x85,0x29,0xb1,0x5e,0x2e,0x9a,0x7e,0xf6, + 0xba,0x7c,0x76,0x77,0x95,0xba,0x7a,0xba,0x34,0x6e,0x70,0xcc,0x2e,0xe1,0x11,0x18, + 0x18,0xf5,0x85,0x6a,0xfb,0xc8,0x14,0xe9,0x39,0x57,0x83,0xfb,0xdd,0x97,0xe3,0x9f, + 0xd8,0x97,0xd8,0x2d,0x2e,0x7a,0x09,0xfb,0x86,0xa0,0xe6,0x48,0x61,0xc6,0x9d,0xd3, + 0xef,0xf8,0x4c,0x48,0x17,0xde,0xb7,0x84,0x7c,0x88,0xe4,0xbe,0x7d,0xd4,0xb1,0xb4, + 0x60,0x58,0x30,0x1d,0x5b,0x86,0xc9,0x58,0xe8,0xb6,0xa2,0xfd,0xa5,0x1f,0xd2,0x19, + 0xa9,0xf1,0x9d,0xa2,0x03,0x5d,0x71,0xd9,0xd4,0xef,0xd3,0x70,0x19,0x96,0xdb,0x71, + 0x0a,0x53,0x23,0x67,0xdd,0xe1,0x51,0xdc,0xef,0x66,0x4c,0x55,0x6d,0xff,0x04,0xa7, + 0x68,0x48,0x2d,0x7c,0x89,0x7f,0x5f,0x79,0x97,0x86,0xc7,0x03,0x43,0x16,0xff,0x54, + 0xa5,0x09,0xd2,0xdd,0x53,0x75,0x19,0xa9,0xe5,0x18,0xf4,0xd2,0xba,0x37,0xc4,0x21, + 0xc8,0x5a,0xf1,0x7d,0x8a,0x7e,0x4f,0x4e,0x33,0x2e,0x35,0x46,0x9f,0x85,0xc0,0xe8, + 0xad,0xf9,0xfa,0xbd,0xbf,0xfc,0x6f,0x11,0xc6,0xc4,0x4c,0xc1,0x94,0xd4,0xcb,0xd5, + 0xa9,0x85,0x39,0xfc,0xa4,0x65,0x23,0x18,0x6a,0x42,0x68,0x2a,0xfe,0x82,0x26,0xe4, + 0x31,0xf8,0x98,0xfa,0x21,0xcb,0xed,0x17,0xde,0x25,0xcb,0x19,0x6c,0xce,0x22,0x7e, + 0x2e,0x57,0x8b,0x91,0x7f,0x9a,0xba,0x1f,0x63,0xff,0x35,0x18,0x44,0xb8,0xd5,0x63, + 0xd5,0x11,0xc6,0xf9,0x8c,0xf7,0xde,0x83,0x7b,0xfa,0xf0,0xd6,0x2a,0x7c,0xde,0x1a, + 0x96,0xf3,0x58,0x7c,0xc4,0x31,0x47,0xbf,0x8b,0xc8,0x3f,0x91,0xb2,0x45,0xa6,0x18, + 0xff,0x3c,0x92,0x87,0x9f,0xe9,0xae,0x5b,0xd4,0x83,0x29,0xf9,0x9c,0xd8,0xe9,0xfe, + 0xf2,0xc8,0x66,0x5a,0x8b,0xf8,0x49,0xce,0x18,0xf6,0x8c,0x46,0x8b,0xe1,0x52,0x26, + 0x98,0x2d,0x6e,0xe0,0x4f,0xc2,0xcf,0x68,0xd3,0xa4,0xab,0x31,0x4f,0xbf,0xef,0x67, + 0xb1,0x71,0x1c,0xa7,0xb0,0x47,0xc2,0xc0,0x34,0xec,0xda,0x6b,0xcd,0x65,0xc0,0x36, + 0x51,0x78,0x02,0x06,0xb1,0xaf,0x4a,0xcb,0x33,0x64,0x8b,0xf2,0xf0,0xf3,0xe9,0xe7, + 0xb8,0xcd,0x50,0x79,0x06,0x5d,0x0f,0xf9,0x04,0x2c,0x1e,0x15,0x51,0xbf,0x1b,0xfb, + 0x81,0xc2,0x01,0xd8,0x9c,0xd4,0x64,0xfb,0x27,0x12,0xce,0x85,0x91,0x8e,0x51,0x2b, + 0xff,0xf9,0x7e,0xe4,0x6f,0x99,0x1c,0x66,0xef,0x41,0xcb,0x2f,0xcd,0xc1,0x4f,0xe9, + 0x38,0x0a,0x15,0xe4,0x9f,0x93,0xa6,0x90,0xbf,0xca,0xe9,0xf7,0x64,0xfa,0x7d,0xad, + 0xa1,0xdf,0x15,0x43,0xc8,0x9b,0xf9,0x02,0x2d,0xff,0x09,0xa1,0x16,0x17,0xd3,0xe1, + 0xc7,0x74,0x52,0x95,0xc3,0xcf,0xf5,0xb0,0x85,0x68,0xb0,0x39,0x42,0xb6,0x70,0x8f, + 0xdd,0x84,0x9f,0xe2,0x16,0x5d,0xb6,0x4f,0xc0,0xcd,0xf8,0xd9,0x26,0x40,0x17,0xa4, + 0xa3,0x08,0x9b,0x13,0xd0,0xc5,0x05,0xa2,0x73,0xf5,0x7b,0x4c,0x65,0xb2,0x9d,0xe9, + 0xf7,0x51,0xa8,0xf3,0xec,0xc8,0xe1,0xe7,0xe8,0xfc,0x37,0x58,0x3a,0xb1,0x6d,0x75, + 0xaa,0xf5,0x0d,0x91,0x35,0x5c,0x39,0xfc,0xf4,0xda,0x5e,0x45,0x6c,0x0d,0x99,0x9a, + 0x39,0x7c,0xbf,0x8b,0xe1,0xa7,0xde,0xd7,0x29,0x21,0x7e,0xca,0xbb,0x19,0x6c,0x62, + 0x03,0xea,0xbc,0x0e,0xea,0x36,0xf1,0x13,0xf5,0x3b,0xec,0x15,0xe5,0x18,0xf2,0x56, + 0xa6,0xdf,0x03,0x11,0x9c,0xcb,0x69,0xc3,0x9e,0xde,0xb2,0x7e,0xc4,0x79,0x63,0x0d, + 0x87,0x8c,0x35,0x98,0xf8,0xe9,0x61,0xf9,0x4f,0xed,0x79,0xef,0x03,0x4b,0x2a,0xec, + 0xc8,0xc3,0x4f,0xe8,0x37,0xd2,0x9e,0x8f,0x4e,0x28,0x46,0xfe,0x33,0x87,0x9f,0x08, + 0x9b,0x74,0x90,0x99,0xd8,0x8a,0x0f,0x96,0x7e,0x47,0xfe,0xb9,0x1d,0x69,0x27,0xd3, + 0xef,0xf0,0x82,0x50,0xc7,0x1a,0x26,0x7e,0x32,0xfd,0xde,0xad,0xbd,0x5b,0x9f,0x9e, + 0x3b,0x9c,0x83,0x9f,0x61,0xba,0x99,0x85,0xd9,0x4e,0xd4,0xef,0xdf,0x87,0xda,0x57, + 0x35,0xfc,0xd4,0x6d,0xed,0x17,0x2b,0xc8,0x29,0xba,0x24,0xeb,0xba,0xc6,0x87,0x55, + 0xd4,0xef,0x93,0xae,0xce,0xaa,0xe3,0x46,0x7c,0x47,0xfe,0x49,0x19,0xaf,0x43,0x0d, + 0xf4,0xa1,0xde,0xc8,0xe4,0xe5,0x3f,0xff,0x29,0x7e,0x72,0x33,0xe3,0x9f,0x3f,0x43, + 0xe1,0x49,0x91,0xe0,0xcd,0x94,0x9e,0x31,0xd6,0x87,0xfa,0xdd,0xb7,0x15,0xee,0x3c, + 0xe2,0xe8,0x8c,0x9c,0xad,0xde,0x47,0x6b,0xa7,0x56,0xfe,0xa9,0xfb,0xbc,0xb1,0x06, + 0xa0,0x3b,0xe9,0x76,0x2d,0xe4,0xa3,0xef,0x1e,0x14,0x10,0x3f,0x1f,0x27,0x23,0x06, + 0x7e,0xc6,0x3d,0x27,0x91,0x56,0x57,0xb3,0x6d,0x87,0x42,0x49,0xa8,0x53,0x57,0x06, + 0x89,0xb5,0x1f,0xca,0x5e,0x96,0x8e,0x31,0xdd,0xc8,0xa8,0xd0,0x35,0x61,0x31,0xce, + 0xe5,0x8b,0xe7,0x2d,0x9f,0x9f,0x92,0x8c,0xe9,0xe9,0x44,0x94,0x35,0x84,0x1c,0xff, + 0xbc,0x01,0xf5,0x6c,0x5c,0x93,0xc6,0xa5,0x9c,0xd3,0x7c,0xb6,0xcd,0xd4,0x47,0x8c, + 0x63,0x32,0x9a,0xb4,0x66,0x0f,0x13,0xeb,0x2a,0xea,0xdb,0x73,0x16,0x7e,0x6e,0x80, + 0x43,0x3d,0x3e,0x9d,0x9b,0x32,0x92,0xca,0xb4,0xbd,0x89,0x9f,0x80,0xfc,0x93,0xd9, + 0x3a,0xe3,0x7e,0x4a,0xd8,0x57,0x55,0x37,0x8c,0x24,0x35,0xc7,0x3f,0xff,0x33,0xbd, + 0x22,0x85,0x46,0x5c,0xff,0x5c,0xba,0x1c,0xae,0x29,0xe1,0xf1,0x6d,0xfb,0xf8,0xac, + 0xb1,0xdf,0xd3,0xf3,0xaf,0xa7,0x67,0xab,0x9b,0x8f,0xb9,0xf6,0x31,0xfd,0xde,0x10, + 0x3e,0xe1,0x3a,0x90,0xd3,0xef,0xdc,0x27,0xc8,0xe7,0x97,0xc7,0x5d,0x43,0x7c,0x0d, + 0x8c,0xe1,0xfe,0xbb,0x63,0xc8,0xaa,0x1f,0xa9,0xe2,0x05,0x38,0x9c,0x40,0xf7,0xca, + 0x90,0x1a,0x78,0xab,0xab,0x8e,0xf1,0x4f,0x99,0xe8,0x6b,0x18,0x45,0xfe,0xb9,0x8f, + 0x6c,0x50,0xf0,0x75,0xfb,0xc0,0x78,0xef,0x16,0x7e,0xda,0x98,0x7e,0x7f,0x2c,0xae, + 0xe9,0xf7,0xbf,0x82,0xba,0x11,0x96,0xff,0x34,0x6c,0x26,0x95,0x69,0xa6,0x92,0x4f, + 0x05,0x79,0x3b,0x8c,0x46,0xc3,0x69,0x47,0xc6,0x91,0x97,0xff,0xf4,0xa2,0xa9,0x50, + 0xbf,0x3b,0x66,0xe0,0x13,0x96,0x4f,0x9e,0x76,0x34,0x18,0xe3,0x62,0x9a,0x7e,0x47, + 0xfd,0xa7,0xd5,0x65,0x20,0x34,0xd2,0x94,0xc3,0x4f,0xa6,0xdf,0xd1,0x54,0xdf,0x10, + 0x87,0x50,0x53,0xf6,0xc2,0xb2,0xac,0x18,0x8c,0xe4,0xf8,0x27,0xcb,0x2f,0xf9,0x95, + 0xc2,0x06,0x22,0x72,0x5d,0x44,0x90,0xc5,0x20,0x4c,0x73,0xba,0x3d,0xa7,0xe1,0xcb, + 0xf4,0x20,0xad,0x5d,0x8f,0x52,0xf9,0xf9,0xae,0x1d,0x5d,0x0b,0x3a,0xb1,0x31,0x2a, + 0xe9,0xef,0x21,0x0a,0x5f,0xa0,0x97,0x52,0x0d,0x3f,0x7f,0x60,0xa8,0x97,0xd0,0x13, + 0x74,0xe9,0xa4,0x88,0xfc,0xd3,0x30,0xb5,0x32,0x1f,0xf5,0xbb,0x3b,0xcc,0x64,0xbb, + 0xaa,0xbd,0xf7,0x53,0x37,0xe9,0x77,0x5c,0xdf,0xfc,0x0c,0xef,0x87,0x63,0x34,0x24, + 0x3b,0x73,0xf8,0x39,0x7a,0xab,0x26,0x7d,0x94,0xb5,0xd3,0xfc,0x5a,0xf8,0x5f,0x50, + 0xa9,0xf4,0x74,0xf8,0x4e,0x1b,0xe3,0x34,0xfd,0x8e,0xfc,0xf3,0xbe,0xce,0xd0,0x60, + 0x10,0x35,0x3a,0xd3,0xef,0x3d,0xe6,0xbe,0x45,0xfe,0x79,0x18,0x02,0x31,0x31,0x68, + 0x3f,0x8e,0x62,0x2f,0xad,0xfa,0x11,0x3f,0x21,0x57,0x3f,0x42,0xfd,0x3e,0x84,0xb0, + 0x39,0x04,0x27,0xa1,0x9e,0x3a,0xd3,0xfc,0x8b,0x56,0xbe,0x40,0xd3,0xef,0x6e,0x17, + 0x25,0x8f,0x98,0x89,0x50,0x13,0xaf,0x45,0xad,0x4e,0x12,0x8a,0xbb,0xfa,0x4a,0xab, + 0x7f,0x15,0x7e,0x1e,0x22,0xbe,0x0e,0x47,0x9f,0x4f,0x80,0x2d,0x2d,0x75,0xb1,0xbc, + 0xfc,0x67,0x83,0xa6,0xdf,0x7d,0x6b,0x1d,0x6e,0xe4,0xa6,0x5b,0x0a,0xeb,0x22,0xd8, + 0x77,0xd2,0xdc,0xd3,0x1e,0x01,0xfb,0x64,0xa5,0x57,0x22,0x0b,0xa1,0x4b,0xd6,0xf0, + 0xf3,0xb8,0x4d,0xb7,0xd9,0x50,0x51,0x5c,0x98,0x81,0xc1,0x32,0xc4,0x4f,0x59,0x62, + 0xf8,0xb2,0x23,0xa7,0xdf,0xfb,0xca,0x18,0x34,0x2e,0x67,0x35,0x9b,0x37,0x0a,0x6e, + 0x48,0xba,0x7e,0x37,0x6c,0xd6,0x67,0x63,0x7d,0xcd,0x8a,0x73,0xbc,0x4a,0x90,0x8e, + 0x89,0xe1,0xfb,0x9d,0xe3,0xfc,0x51,0xc3,0xcf,0x1a,0xbc,0x1a,0x6c,0x8a,0x48,0xf5, + 0xe2,0xd0,0xd3,0xb2,0x58,0x62,0xf9,0xcf,0x02,0x23,0xbe,0x03,0xea,0x77,0x08,0xb4, + 0xde,0x16,0xa2,0xfb,0xc5,0x4d,0x5d,0xb5,0x71,0x91,0xf1,0x4f,0x7d,0xed,0x5e,0x81, + 0xf1,0xcf,0xc7,0x94,0xdb,0x53,0x35,0x13,0xbb,0x9f,0x92,0x17,0x47,0xb5,0x1c,0x84, + 0xb1,0x57,0xca,0x26,0xa4,0x2b,0xd0,0xa4,0x6c,0x4f,0xb1,0xbc,0x46,0x4b,0x38,0x16, + 0xc8,0xe5,0x3f,0xa3,0x9c,0x86,0x9f,0xeb,0x8b,0x52,0x3c,0xab,0x73,0x35,0x31,0x9b, + 0xe5,0xec,0xa9,0xd9,0x1a,0xee,0xa0,0xa5,0x95,0xc2,0x28,0xd4,0x43,0x80,0x5a,0xf6, + 0x34,0xf2,0x9f,0x03,0x8e,0x2c,0x68,0xfa,0x3d,0x2d,0xfe,0x52,0xfe,0xf3,0x1c,0x9f, + 0x89,0x38,0xa5,0xee,0x84,0x4c,0x31,0x36,0x9a,0xfa,0x9d,0x96,0x94,0x6b,0x52,0x19, + 0x31,0x6b,0x29,0xd9,0xac,0x56,0x26,0x30,0xde,0x66,0x05,0x7d,0x5c,0x8f,0x58,0x01, + 0x2c,0xff,0xe9,0xe8,0x74,0xdc,0x06,0xc3,0x34,0x93,0x75,0x76,0xf2,0xef,0x99,0xfa, + 0xbd,0x6c,0x8f,0x0e,0x47,0xcb,0xfe,0x2e,0x2b,0x5e,0x45,0xae,0xf1,0x5d,0xe6,0x83, + 0xfa,0x3c,0x15,0xa6,0xdf,0x91,0x76,0x3a,0xaf,0xf0,0x61,0xee,0x18,0xad,0xaf,0x76, + 0x75,0xf2,0x60,0xe2,0xa7,0x77,0xbb,0x70,0x30,0x5d,0x37,0xd9,0xd3,0xe9,0xbb,0x25, + 0xdd,0x95,0xa9,0xf4,0x23,0x70,0xd7,0x18,0xba,0x0a,0xf5,0xbb,0x84,0x73,0x19,0x16, + 0x1f,0x27,0xde,0x48,0x52,0xae,0x8c,0xe3,0xa4,0xcc,0x71,0x71,0x61,0x9b,0xb4,0x0f, + 0xea,0xa6,0x11,0xaa,0x98,0xf3,0x60,0xd0,0x0a,0x12,0xd1,0xe8,0x1b,0xd2,0xe7,0xf2, + 0x6a,0x20,0xb3,0xb2,0x16,0x4e,0xd0,0xc1,0x94,0x2b,0xe3,0x30,0x73,0x02,0x49,0xd0, + 0xf6,0x0a,0xc5,0x7d,0x34,0x21,0x5c,0xa2,0x4d,0xac,0x61,0xea,0xf7,0xb4,0xa4,0x95, + 0x40,0x46,0x9d,0x33,0x7c,0x83,0x7c,0x1c,0xea,0x87,0x11,0x3f,0x47,0x0d,0xfc,0xdc, + 0xa5,0xeb,0xf7,0x71,0x84,0x4d,0x8a,0xf1,0x88,0x11,0x35,0x32,0x99,0xcb,0x7f,0x0a, + 0x87,0x85,0xba,0x61,0x71,0x10,0xf1,0x73,0x0b,0xe7,0xd3,0x72,0xa3,0xb9,0xfc,0x27, + 0xdd,0xe7,0x0b,0x14,0xda,0xdd,0xa4,0x3f,0xb9,0x2b,0x22,0x83,0xbf,0x9e,0x0c,0x1b, + 0xfe,0x49,0x8b,0x36,0x28,0x08,0x8d,0xef,0x3a,0x3f,0xae,0xf2,0x2b,0xa3,0xf1,0xc1, + 0xb5,0xab,0x06,0xab,0xac,0xfc,0xe7,0xb7,0xaf,0xab,0xb3,0x72,0xf8,0x98,0xab,0xbe, + 0x5b,0x55,0xaf,0xc7,0xc3,0x5f,0x40,0x20,0xb5,0xf8,0x67,0xd9,0x75,0xd8,0x80,0xdb, + 0xbc,0x68,0x94,0x0f,0xb3,0x78,0x74,0xbf,0x33,0xa7,0xdf,0x55,0xef,0xac,0xb0,0x95, + 0xca,0x8f,0x38,0x7a,0x48,0x40,0x3e,0x4c,0xeb,0xa6,0xed,0x39,0xfd,0x3e,0x6a,0x7b, + 0x5d,0xf4,0xa3,0x8d,0x1c,0x90,0x70,0x6e,0xd9,0xa7,0x73,0x22,0x4b,0xbf,0x73,0x7b, + 0x98,0x9b,0x28,0xc8,0x0b,0xf4,0x18,0x60,0xcf,0xf8,0x4c,0x1e,0x29,0x21,0xbe,0x9c, + 0x83,0x10,0x9a,0xca,0xc1,0xfa,0x2a,0x58,0x3d,0x6e,0xd4,0xe2,0x9f,0x2f,0x31,0x9b, + 0x0d,0x6b,0xb1,0x6a,0x96,0x2c,0x9f,0xce,0xcf,0x7f,0xc2,0x1e,0xe5,0xcd,0x92,0x50, + 0x7a,0xd5,0x10,0xcf,0xea,0x32,0x8c,0x43,0xf3,0xa6,0x7e,0x3f,0x63,0x2b,0x47,0x7a, + 0xec,0xcb,0x22,0x7e,0x06,0x90,0x9b,0xd6,0x4d,0xcf,0xe1,0x9f,0x0f,0xd4,0x64,0x84, + 0x6a,0xc9,0x4f,0xc9,0x36,0x09,0xbd,0xfa,0x72,0x1e,0xff,0x9c,0xe6,0x2a,0x60,0x7b, + 0x7a,0x41,0xbb,0x18,0x2d,0x60,0xe0,0x55,0x9b,0xe5,0x3b,0x23,0x9f,0x18,0x7d,0x51, + 0xd1,0xa9,0x4c,0xd3,0xa5,0x72,0xa0,0x87,0xdf,0xae,0xe2,0xbb,0x55,0x5d,0x4b,0xf8, + 0xb7,0x4c,0xfd,0x3e,0xff,0x29,0xf8,0x98,0xbb,0x47,0x71,0xa9,0x8e,0x3f,0x83,0x0f, + 0x24,0x2d,0xcf,0x60,0xea,0xf7,0x01,0x96,0x9f,0x40,0x9f,0x98,0xff,0x22,0x72,0x53, + 0x23,0xa6,0x1e,0x37,0xf1,0xb3,0x64,0xa7,0x70,0x90,0xd5,0x8f,0x36,0xda,0xad,0x8d, + 0x71,0x51,0xd2,0xd7,0x47,0xe1,0x3b,0x23,0x3f,0x4e,0xd6,0xa6,0xa3,0x9d,0xa4,0x42, + 0x9b,0x0b,0xfa,0xae,0x6a,0xf1,0x4f,0x2d,0xff,0x39,0x21,0xde,0x4d,0x9c,0xac,0x91, + 0x9d,0x53,0x3f,0xea,0x81,0xab,0x42,0x98,0xd6,0xee,0x21,0xac,0xb6,0x1b,0x1e,0x70, + 0xe5,0xeb,0xf7,0xac,0x30,0x43,0x19,0x6c,0x76,0xc7,0x2d,0xfc,0xcc,0xe9,0x77,0xf2, + 0x73,0x84,0xcd,0x55,0xcf,0xf3,0x8c,0x7f,0x36,0x29,0x81,0x9b,0xf8,0x27,0x57,0x17, + 0x8b,0xee,0x24,0x13,0x02,0x72,0xcc,0x87,0xc5,0x39,0xfc,0x93,0xfc,0x80,0xd6,0x2a, + 0x85,0xe3,0xee,0x11,0x8d,0x7f,0xce,0xc9,0x7f,0x3a,0xe9,0x26,0xa8,0x8d,0xfb,0xd7, + 0x92,0x91,0x5b,0x50,0xc7,0xcd,0xc9,0x7f,0x16,0xc5,0x61,0x12,0xc2,0x9e,0x55,0xf7, + 0x7e,0x1e,0xf9,0x27,0x17,0x06,0x67,0x8e,0x7f,0x6a,0xf5,0x23,0xb0,0xea,0x32,0xcd, + 0xf9,0xfc,0xb3,0xcf,0x76,0x99,0xbc,0x0e,0xf7,0xb4,0x39,0xc7,0x1d,0xd5,0xac,0xef, + 0x7e,0x04,0xaf,0x0b,0xb9,0xfa,0x11,0xca,0x76,0xd4,0xef,0x04,0x71,0x07,0x81,0x94, + 0xe1,0xa7,0xa5,0xdf,0x6d,0x23,0x0a,0xab,0x1f,0xd9,0xdd,0x3e,0x21,0x8d,0x40,0xaa, + 0x14,0xce,0xe1,0x9f,0x25,0x5b,0x10,0xe7,0x11,0xde,0xab,0xb9,0x43,0xc6,0x1a,0x4c, + 0xfe,0xc9,0xea,0x47,0x42,0xa3,0x52,0xc3,0x72,0xbf,0xc8,0x3f,0x5b,0xbe,0x8d,0xf8, + 0x69,0xf8,0x75,0x3b,0xab,0x1f,0xe1,0x3c,0x9d,0x38,0x4f,0xe9,0x8a,0xd0,0x14,0xbd, + 0x99,0x7f,0x42,0x98,0xab,0x65,0xfc,0x13,0x6d,0x2d,0x14,0xe5,0xf1,0x4f,0xae,0x81, + 0x0c,0xd3,0xc5,0xd4,0x99,0x25,0x7e,0xee,0x45,0x6e,0x31,0x15,0x6f,0xe2,0x9f,0x29, + 0xb6,0x7d,0xec,0x4e,0x89,0xbd,0x5b,0x7f,0x30,0x32,0x6c,0xd5,0x8f,0x24,0x94,0x29, + 0x68,0xeb,0x18,0x29,0xa7,0x07,0x71,0x0d,0x62,0x07,0x98,0xfc,0x73,0x40,0x2c,0x86, + 0xd7,0x68,0x73,0x3a,0xd0,0x7e,0xfb,0x1d,0xe8,0x2f,0xcb,0x11,0x3f,0x2b,0x2d,0xfe, + 0x79,0x2b,0xd3,0x6a,0x61,0xa5,0x38,0xcd,0x7f,0x98,0xbe,0xc6,0xce,0x5d,0x64,0xe6, + 0xd4,0xdf,0xaf,0xd1,0xe6,0x89,0x00,0xe2,0x27,0xd3,0xef,0xd9,0xa2,0x7c,0xfe,0x99, + 0x81,0xee,0x3e,0x0c,0x35,0x7d,0xf6,0x3a,0xd2,0x4d,0x6b,0xdb,0xc5,0x3f,0xe1,0xcf, + 0x9b,0x36,0x83,0x97,0xe0,0xfb,0x25,0xb5,0x3d,0x3d,0x8f,0x90,0x72,0xf1,0x9b,0x72, + 0xed,0xf1,0xff,0xb4,0x31,0xaf,0xfe,0x3e,0xc2,0xd2,0x90,0xb1,0x68,0x5a,0xab,0x1f, + 0x05,0xe4,0x1e,0xe6,0x9f,0x7a,0x1f,0xc3,0xcf,0x0f,0x28,0xab,0xfb,0x3a,0x9a,0xe0, + 0x6d,0xa1,0x89,0xe9,0xb1,0x1c,0xff,0x9c,0x64,0xdb,0x75,0xd8,0xf5,0x1c,0xf2,0xcf, + 0x0f,0x40,0x23,0x24,0x7b,0xcc,0x1a,0xa6,0xf4,0x09,0x9c,0x92,0xef,0x4a,0x6f,0x9b, + 0xbe,0x9d,0xf1,0x4f,0xbc,0xc1,0x74,0xa9,0xc5,0x3f,0x61,0x15,0xdb,0xef,0x13,0xe2, + 0xfe,0x52,0x0d,0x5f,0x64,0x3f,0x6a,0xf4,0x1c,0x7e,0x2a,0xbd,0xb0,0x10,0x21,0x35, + 0xa1,0x15,0xb1,0xb3,0x22,0x6a,0x7b,0xc3,0x9e,0x76,0x41,0x84,0x5e,0x8f,0xfc,0x9a, + 0xdf,0x93,0xd8,0x46,0xf7,0x31,0xff,0x0c,0x5a,0xef,0x01,0xf1,0x93,0x9c,0xa8,0x5e, + 0xda,0x13,0x38,0xc0,0xbf,0x24,0x5c,0x5b,0x17,0x8e,0xb6,0x0d,0xf2,0xd9,0x02,0x43, + 0xbf,0x7f,0x1b,0xb9,0x70,0x50,0x83,0x9c,0x40,0x7c,0xb6,0x21,0x2c,0xac,0xde,0xdb, + 0x3a,0xf9,0x64,0x5e,0xfd,0x88,0x86,0xd3,0xc8,0x3f,0xb3,0xa8,0xc4,0x43,0x59,0x57, + 0x9e,0x7e,0x07,0xe4,0x9f,0xdd,0x75,0xbb,0x1c,0x43,0xca,0x05,0xd8,0x42,0x77,0x6b, + 0xf9,0x4f,0x21,0x8f,0x7f,0xea,0x35,0xb7,0x31,0x76,0xb6,0xe9,0xe6,0xfc,0x27,0x4e, + 0x3d,0xa5,0xd5,0xc0,0xb6,0xfc,0x72,0xfe,0x13,0x5f,0x69,0x46,0x0b,0x35,0xea,0xa8, + 0x56,0x10,0xca,0xe6,0xea,0x47,0x5a,0xcc,0x71,0x4c,0x93,0xeb,0xc2,0x4f,0x52,0xcd, + 0xea,0xea,0x9b,0xeb,0x47,0xe1,0x94,0xc6,0xf5,0x67,0x94,0x65,0x5a,0xcd,0xdb,0xd0, + 0xda,0xaa,0x2d,0x60,0xe6,0x93,0xc7,0x18,0x39,0xd2,0x9e,0x67,0xf8,0xd9,0xa8,0xe0, + 0x34,0xe6,0xe9,0x56,0xa5,0x8c,0x9e,0x3b,0xbc,0x0a,0x26,0xff,0xac,0x60,0xfc,0xd3, + 0x8f,0xb2,0xfd,0x1d,0x78,0x89,0xd5,0xbc,0x9f,0x20,0xd7,0x65,0x7d,0x5c,0xd4,0x5b, + 0x4c,0x11,0x36,0x07,0xbe,0xd2,0xd8,0x7a,0x12,0xa6,0xfb,0x97,0x4e,0xe5,0xeb,0xf7, + 0xf2,0x3d,0xec,0x95,0x26,0x5d,0x1f,0xf1,0xd7,0x5b,0xa6,0x19,0x7e,0x7e,0xc4,0x8f, + 0x3f,0xa9,0xcf,0x13,0xf9,0xa7,0xf8,0x75,0xca,0xe2,0x43,0x6b,0x16,0x1f,0xa0,0xd7, + 0xdf,0xa9,0x81,0x9f,0xac,0x7e,0x04,0x95,0xb4,0x97,0x69,0xa0,0xfd,0x28,0x86,0x7e, + 0x17,0xf1,0xb3,0x5a,0x1f,0xa7,0xf3,0xcf,0xca,0x34,0xab,0x65,0xc1,0x01,0xbd,0xfe, + 0x3e,0xb7,0x7e,0x24,0x0f,0x6b,0xb6,0xce,0xe8,0xb6,0xb6,0xf0,0x13,0x58,0xfd,0x68, + 0x5f,0xca,0x91,0x46,0x53,0x7d,0x92,0x0e,0xcd,0xa9,0xbf,0x1b,0x9c,0x68,0x9e,0x56, + 0x7f,0x17,0x1a,0x6f,0xae,0x1f,0xe5,0x61,0xd6,0x32,0x65,0x4e,0xfd,0x1d,0x39,0x26, + 0xa9,0x6b,0xd9,0xce,0xf4,0xed,0xde,0x5f,0x59,0x7f,0x37,0xb5,0xef,0xcd,0xf5,0x77, + 0xd8,0x2b,0x68,0xa9,0xc6,0x11,0x7a,0x48,0x07,0xa8,0x5c,0xfd,0x48,0x3f,0x0b,0x70, + 0x3b,0x6d,0x65,0x0d,0xb7,0x96,0xff,0xe4,0x25,0xa3,0x4f,0x83,0x4d,0xb5,0x38,0xc5, + 0x5f,0x8e,0xde,0xd0,0x27,0x75,0x71,0x9e,0xbe,0x86,0x21,0x1b,0xcb,0x8d,0x86,0x55, + 0x84,0xcd,0xcb,0xf2,0xeb,0x28,0xac,0x8b,0x73,0xdc,0x54,0xcb,0x7f,0x42,0x1d,0x2b, + 0xbb,0x9f,0x43,0xb2,0x5e,0xc3,0x0e,0xd0,0xbc,0x63,0xe2,0xa7,0xc6,0x3f,0xeb,0x18, + 0x6c,0x1e,0x05,0x06,0x96,0x5a,0xfe,0xd3,0xaa,0x1f,0x49,0x6c,0x0d,0xde,0x94,0xef, + 0x7d,0xd8,0x22,0x6b,0xc5,0xb0,0xbc,0xfa,0x91,0x78,0xc5,0x16,0x8e,0x3f,0x95,0x2a, + 0x9d,0x90,0x8e,0xe8,0xcf,0xb3,0xea,0x47,0x31,0xcd,0x66,0xf7,0x9e,0xd2,0x6c,0x46, + 0x7f,0x45,0xfd,0x88,0x1d,0x71,0xd0,0xce,0x3a,0x84,0xf2,0xf5,0xbb,0x28,0xf8,0xc5, + 0x17,0x99,0x0f,0xa6,0x23,0xa3,0xf0,0x22,0xa9,0x62,0xfa,0x3d,0xbf,0x7e,0x64,0x9e, + 0x63,0x61,0xb9,0x6d,0xb6,0xa1,0xf2,0xea,0x47,0x92,0x11,0x66,0x51,0x33,0xc3,0x02, + 0x8a,0x8d,0x49,0x83,0x7f,0xb2,0xfa,0x91,0x51,0x7f,0x7f,0x07,0x1b,0x77,0xa6,0xb1, + 0x71,0x5e,0x7f,0x1c,0x88,0x45,0x3a,0xff,0xd4,0xf6,0xdf,0x25,0x68,0x44,0x67,0x2c, + 0x1d,0xf6,0xe8,0xf3,0x8c,0x0b,0x9f,0xc0,0xe1,0xae,0xdf,0xc8,0xce,0x1b,0xc2,0x30, + 0x74,0x2a,0x15,0xea,0x77,0x0e,0xe5,0xce,0x2f,0xc1,0xf6,0x24,0xca,0xf6,0xf7,0x99, + 0x0f,0x2a,0xdd,0x78,0x4f,0xd4,0x40,0xe7,0x8d,0xb3,0x46,0x12,0xec,0x54,0xf4,0xb9, + 0x44,0x5e,0x6f,0xdb,0x01,0xeb,0x7a,0xec,0x1d,0x05,0x23,0x73,0xe3,0x3b,0x5b,0xc3, + 0x49,0xe8,0x56,0xfa,0x29,0xea,0xe2,0x33,0x79,0xf5,0x23,0xd4,0x8d,0x59,0x6d,0xdf, + 0x9e,0x48,0x85,0x28,0x62,0xf9,0x05,0xc3,0xd6,0x19,0xbd,0x7e,0x34,0xcc,0xfa,0xa2, + 0xd7,0xa4,0x30,0xb5,0xe5,0xf8,0x67,0x97,0x74,0xdd,0x66,0xc8,0xf6,0xb3,0x70,0x0a, + 0x75,0x15,0x2b,0x2a,0x9b,0xf5,0xa3,0x24,0xf2,0xcf,0x82,0x00,0x93,0xed,0x53,0x88, + 0xd7,0xbb,0xf1,0x9e,0x24,0xaf,0x7e,0xc4,0xf8,0x27,0xa3,0xa4,0x53,0xac,0x16,0x42, + 0xf3,0xeb,0xef,0x18,0xb4,0xf7,0x29,0x48,0xe7,0x42,0x89,0xb1,0xd1,0x5e,0x31,0xfd, + 0x4c,0x9e,0x7e,0xa7,0xde,0x0d,0xea,0xe1,0x68,0x78,0x64,0xd5,0x41,0xfe,0x43,0x7a, + 0x22,0x1e,0xea,0x2b,0xfe,0xf1,0xf7,0xac,0xfa,0xd1,0xb7,0xa7,0x46,0x70,0xbf,0x9f, + 0x61,0xb5,0x79,0xf1,0x92,0x7f,0x39,0x2d,0xbe,0x98,0x57,0x7f,0xbf,0x4c,0x5e,0x4d, + 0x35,0x83,0xf3,0xbd,0xee,0x26,0xe9,0x94,0x96,0x0f,0xe1,0xa7,0x13,0xfa,0xfa,0x54, + 0xe9,0x43,0xb9,0x57,0xc6,0xb9,0x24,0xc9,0x62,0x96,0xff,0xd4,0xf0,0x33,0x61,0xe2, + 0x67,0x56,0xed,0x96,0x03,0x6a,0x21,0x90,0x2d,0xa6,0x7e,0xbf,0xc8,0xe9,0xf6,0x54, + 0xcb,0x58,0x19,0xa7,0x6e,0xda,0x9f,0xbe,0x3f,0xcd,0xf5,0x6a,0xc0,0xe6,0x9b,0x36, + 0x6c,0x4d,0x3d,0x54,0x39,0x91,0x0a,0x67,0x8b,0xf6,0x74,0xbf,0x40,0x4e,0xe8,0xf9, + 0x64,0xd5,0xc8,0xa3,0x7c,0x04,0x2f,0x88,0xb3,0xec,0x38,0xd0,0x5b,0xfc,0x13,0x8a, + 0x51,0x3f,0x9a,0x36,0x73,0xd4,0x52,0x3f,0x41,0xd9,0x3e,0xee,0xa4,0xa5,0x4e,0xd6, + 0x60,0xe3,0xce,0x9a,0xfc,0x53,0x58,0x3e,0x8a,0xa6,0x7a,0x43,0xfc,0x6b,0x14,0xce, + 0xbd,0xb0,0x9b,0x39,0xce,0x55,0xdd,0x2c,0xec,0xfc,0x27,0x61,0xf9,0x25,0xa4,0x18, + 0xc5,0xac,0xd0,0xa9,0xd5,0x8f,0xa8,0xde,0x97,0xe1,0x2a,0x84,0x1d,0xb4,0x72,0x42, + 0x7c,0xd3,0x5e,0x01,0xdf,0xd5,0x31,0xeb,0x63,0xa3,0xef,0x7e,0x91,0x90,0xbf,0x23, + 0x41,0x75,0x55,0xb0,0x54,0x84,0xb7,0xa5,0xe0,0x11,0xe4,0x9f,0xa6,0x7e,0x8f,0xcc, + 0x1f,0x52,0x66,0xa5,0x97,0xd5,0xc5,0x1d,0xfc,0x99,0xf8,0x3f,0x69,0xf3,0x2c,0x1d, + 0x37,0x63,0xf8,0x6f,0x4d,0xb2,0xf3,0x1a,0x6a,0x45,0xaa,0xd4,0x8f,0x8d,0x46,0xbd, + 0x7e,0xa4,0xf7,0x8d,0x3e,0xfd,0x7c,0x62,0x33,0x59,0xac,0x16,0xc5,0x88,0x9d,0x6e, + 0x36,0xf8,0xa7,0xc9,0xf9,0xe0,0x9b,0x0a,0x3b,0xbf,0x74,0x7f,0xc3,0x6d,0x15,0xb0, + 0x99,0x2e,0xd2,0xf8,0xa7,0x64,0xfa,0xe7,0xeb,0xd0,0x4d,0x02,0xd3,0x62,0x70,0x77, + 0xb1,0xc8,0xc3,0x06,0x1d,0x3f,0xf5,0xbe,0x49,0xdb,0x10,0x1c,0xa7,0x77,0x64,0xec, + 0xd9,0xaa,0x7b,0x0a,0xee,0x67,0x7b,0x25,0xcd,0x5f,0xb4,0xf8,0xa7,0x2a,0xcf,0x48, + 0x61,0x27,0x6e,0x65,0x35,0x6e,0xe9,0x77,0xd9,0xf0,0xa5,0xf7,0xe9,0x31,0xa2,0x71, + 0xa9,0x85,0xc8,0x3f,0xeb,0x34,0xfc,0x34,0xdf,0x91,0xf0,0xfb,0xf6,0x2d,0xf3,0xd8, + 0xb1,0x1e,0xfb,0x42,0x33,0xc7,0x99,0x35,0xd6,0xee,0x15,0x16,0xe0,0x8f,0x02,0x5a, + 0x8d,0x48,0xb1,0xf2,0x9f,0x60,0xdc,0x53,0x48,0x68,0xb4,0xd3,0x4d,0xb4,0xc6,0x1c, + 0xfc,0x14,0xd7,0x45,0x46,0xd7,0x84,0x3d,0x7d,0x9b,0xea,0xad,0xfc,0xe0,0xc7,0xc4, + 0xc8,0x7f,0x16,0xbd,0x81,0xb0,0xd9,0x3c,0x82,0x61,0xe8,0xb2,0x49,0x44,0xdf,0x9b, + 0xa7,0xfb,0xa7,0xc8,0x7d,0xac,0x1e,0x83,0x65,0x6d,0xce,0x3e,0xfe,0x1b,0x5a,0x9e, + 0x81,0x60,0x1f,0x31,0xf3,0x9f,0x3f,0x23,0x54,0x0c,0x08,0xe2,0x30,0x72,0xef,0x9b, + 0xeb,0x47,0xb6,0x11,0x95,0x4d,0xa1,0xe7,0xa1,0x84,0x0d,0x76,0xe9,0x73,0x79,0xcb, + 0xe2,0x9f,0x7f,0x0d,0x3f,0xa0,0x75,0x4a,0xcf,0x69,0x7b,0x35,0xfc,0x40,0x5b,0x03, + 0x32,0x05,0xbd,0x2f,0xfd,0x17,0x13,0xe4,0x18,0x17,0x6e,0xf3,0x3f,0xc7,0x2f,0x20, + 0x7f,0x00,0xe1,0x96,0xef,0xe4,0xe7,0x3f,0x93,0xca,0x9b,0xd0,0x14,0x77,0x79,0xf9, + 0xa3,0xf4,0x4d,0xed,0x20,0x53,0xd5,0x69,0x83,0x83,0x21,0x7e,0x26,0xd8,0xf9,0x4f, + 0x27,0x85,0x4a,0xa2,0xaf,0xaf,0x6a,0xd8,0xec,0xc3,0xd0,0xb5,0x95,0xf3,0x75,0x21, + 0xed,0xac,0x41,0x61,0xd6,0xa8,0xe5,0x3f,0xab,0x75,0xbb,0xf8,0x6d,0x0f,0x70,0xa5, + 0xcc,0x3f,0x1b,0xdc,0xdb,0x59,0x7e,0x5e,0xcf,0x7f,0xea,0x57,0x25,0x57,0xee,0xdb, + 0x9c,0xae,0xa4,0xfe,0xf5,0xe4,0x29,0xf8,0xbe,0x76,0xde,0x2d,0xa2,0x2a,0xc6,0xb8, + 0x9e,0x30,0x79,0x8d,0x2e,0xc9,0x3a,0x67,0x7a,0xbf,0x43,0xfe,0x37,0x02,0xe9,0x6b, + 0x9d,0x55,0xc3,0xb2,0xf1,0x1e,0xe6,0x23,0xff,0x0c,0x17,0x53,0xd7,0xee,0xd6,0x0d, + 0xec,0x5c,0xa5,0xa6,0x81,0x92,0xc6,0x3e,0xb2,0x7d,0x1c,0x79,0x1b,0x69,0x27,0xda, + 0x33,0x0c,0xda,0x7e,0x1f,0xaa,0x1a,0xdf,0xad,0xf7,0xfd,0xa0,0x64,0x73,0x7a,0x33, + 0xad,0xed,0x11,0xa3,0x89,0x72,0x46,0x7c,0xd5,0x95,0x4f,0x90,0xf3,0x92,0xe9,0x9f, + 0x49,0xcd,0x65,0xa3,0x31,0xf2,0xb0,0xfc,0x7d,0xe6,0xbb,0x1b,0xc9,0x94,0x95,0xff, + 0x9c,0x92,0x7a,0x21,0x90,0x11,0x81,0x7c,0x01,0xb1,0xc0,0x89,0x6b,0x88,0x98,0xfe, + 0x39,0x50,0x36,0x85,0xf0,0x57,0xa7,0xfa,0x97,0x3a,0x1e,0x23,0x1f,0xa0,0xde,0x74, + 0x65,0xbe,0xf8,0x9e,0xe9,0x67,0x68,0xfc,0x0f,0x12,0xe1,0x27,0xd1,0x65,0x11,0x64, + 0x49,0x58,0xbd,0x03,0x85,0xbc,0xd1,0xc7,0xc5,0xae,0x8b,0xef,0x72,0x21,0xfc,0x51, + 0x77,0x00,0x4e,0x69,0x7b,0x4c,0xce,0x1a,0xcf,0x53,0x85,0xaf,0xe2,0xf3,0x76,0xa3, + 0x19,0xed,0x4e,0x5c,0x9f,0x46,0x9c,0xa6,0x0d,0xbb,0x50,0xa8,0x86,0xbf,0x62,0x14, + 0x2a,0x45,0x02,0xb4,0x57,0x3b,0x44,0xe9,0x36,0x7d,0x57,0x84,0xea,0x23,0xdd,0x10, + 0xa7,0x9a,0x2e,0x7e,0x56,0xb3,0xf5,0x33,0xa6,0x7f,0x2a,0xe2,0x57,0x07,0xde,0x85, + 0xd0,0x11,0x47,0x0a,0xf5,0xad,0x5e,0x9f,0xe6,0x4d,0xde,0xba,0x7b,0xfe,0x14,0xcc, + 0x4a,0xcd,0x5d,0xae,0x23,0xfc,0x65,0xa3,0xae,0xfd,0x68,0xb6,0xd2,0xd4,0xda,0x17, + 0x30,0x7c,0x0d,0x9e,0xab,0x53,0xf9,0x10,0x1c,0xe3,0xea,0xb3,0x81,0x99,0xbc,0xfa, + 0xd1,0x05,0x89,0x95,0xdd,0x31,0xbe,0xa7,0x71,0xd3,0x1c,0x40,0x81,0xac,0x64,0x21, + 0xc7,0x3f,0xd9,0x51,0x44,0x3b,0x52,0x09,0xa9,0xdb,0xd6,0x7e,0x44,0x0c,0x16,0xcc, + 0x39,0xff,0x49,0x6b,0x46,0x06,0x20,0x42,0x9d,0x5b,0x68,0x31,0x12,0xbf,0x1c,0xff, + 0x44,0x7b,0x5e,0x3a,0xd6,0x78,0x66,0x7b,0xc6,0xe1,0x23,0x47,0x68,0x03,0x3b,0xd0, + 0x69,0xd6,0x8f,0xa6,0x35,0xfd,0x7e,0x50,0x5d,0x7d,0xbd,0xfb,0x17,0xd2,0x0d,0xb8, + 0x4b,0x3b,0xff,0x69,0xd5,0x8f,0xd0,0xc4,0xde,0x90,0xea,0xdc,0xef,0xa8,0x84,0xb7, + 0xe5,0xd0,0xb0,0x2b,0x77,0x7e,0xe9,0x8c,0x2d,0x20,0x1e,0x52,0x14,0x8c,0x39,0x76, + 0x36,0xcf,0xd0,0xf8,0xca,0x4c,0xde,0xf9,0xf9,0x55,0x30,0x08,0x69,0x75,0x91,0x44, + 0x04,0x78,0xfa,0xa1,0x6d,0x4c,0xbf,0x77,0x18,0xf6,0x64,0xfa,0xfd,0x95,0x74,0x55, + 0xf6,0xd6,0xdb,0x12,0x07,0x94,0xcd,0xbb,0x17,0x4d,0x3a,0x66,0x0a,0xa2,0x46,0x5f, + 0x14,0xf5,0xd1,0xc5,0xb4,0x9c,0xbd,0xf7,0x36,0x87,0x1d,0xde,0xa2,0x4d,0x59,0xd7, + 0x8b,0xfc,0x1a,0x4b,0xbf,0xef,0x51,0x5e,0x2c,0x59,0x3e,0x56,0xfc,0x2c,0x7f,0xa6, + 0xed,0x2a,0x87,0x5c,0x78,0x6f,0xbe,0x7e,0x17,0xae,0x32,0x5c,0xca,0x38,0x64,0x78, + 0x1d,0x06,0xd5,0xd5,0x0d,0xad,0x24,0xa7,0xdf,0x3d,0x2c,0xff,0x29,0x4a,0x05,0x3b, + 0xdd,0x9b,0xf5,0x64,0xbc,0xdb,0xd2,0x32,0xdf,0x41,0xda,0xf9,0xb5,0x20,0x74,0x92, + 0x10,0x74,0xd3,0x75,0xd9,0xdb,0x3b,0xad,0x1c,0x12,0x8b,0xef,0x83,0x10,0x58,0xeb, + 0x3f,0x44,0x06,0x8c,0x62,0x03,0xb9,0xcd,0xe4,0x9f,0x25,0x03,0xf0,0x09,0x34,0x67, + 0x9c,0x53,0x8e,0x7b,0xe8,0x49,0xbd,0x90,0xd4,0x98,0x57,0x3f,0xd2,0x61,0xb3,0x3b, + 0x2b,0xeb,0x42,0x9e,0x9f,0x53,0x7f,0x87,0x70,0xfb,0xaa,0x3e,0x9e,0xe5,0x3f,0x1f, + 0x67,0x40,0x7a,0xd3,0xf9,0x4f,0xe5,0x0f,0xfb,0xe4,0x6a,0xa1,0x4b,0x68,0x57,0xc4, + 0x9b,0xea,0xef,0x50,0x17,0x13,0x0f,0x90,0x00,0xc1,0xa0,0x15,0xbd,0xf9,0xfc,0x12, + 0x45,0xa8,0x7a,0x06,0x6d,0xdd,0x85,0xbc,0xce,0x9f,0x57,0x7f,0x2f,0xd2,0x53,0x08, + 0xce,0x4d,0x8e,0xca,0xc8,0xe8,0x83,0x3e,0x6e,0xae,0x7e,0x87,0xff,0xc6,0x2d,0x57, + 0x5c,0x3f,0xe5,0xdf,0x80,0x1b,0x52,0xb3,0xb2,0x78,0xae,0x7e,0x3f,0x05,0xac,0xfe, + 0xde,0x5b,0x0d,0x4f,0x79,0xeb,0x95,0xd5,0xe3,0xfc,0x49,0x4b,0xbf,0xc7,0x35,0xd8, + 0xec,0x49,0x46,0xfc,0x64,0xab,0x5c,0x73,0x13,0x7e,0xb2,0x3c,0x99,0xd2,0xee,0x4e, + 0x08,0xbb,0xb6,0xc8,0x1a,0x17,0xce,0xaf,0x1f,0x6d,0x81,0x62,0xc5,0x9f,0xd1,0xce, + 0x59,0xd5,0x28,0xb7,0xcf,0xd1,0xef,0xc2,0xb1,0x3f,0xaa,0x88,0x6c,0x4b,0x15,0x2e, + 0x94,0x8e,0xc5,0x06,0x5b,0x56,0xe7,0xe1,0x27,0xd7,0x4f,0x0e,0x31,0xd8,0x7c,0xbe, + 0xea,0x7d,0xf8,0x15,0xf5,0xa3,0x19,0x25,0x24,0x39,0xe9,0x17,0x71,0xa1,0xca,0xa0, + 0xe0,0xcc,0x3f,0xff,0x29,0x0a,0x2f,0xb7,0x2c,0xda,0x62,0x9f,0x70,0xfb,0xe1,0x00, + 0x54,0xa5,0x0a,0xe6,0xea,0xf7,0xbd,0xb2,0x9f,0x8a,0x83,0x8c,0x7f,0x52,0xf9,0xf4, + 0x96,0x5c,0xfd,0x28,0xcd,0x95,0xc3,0xc1,0xe4,0x62,0x6a,0x8f,0x93,0xf2,0xfb,0xf6, + 0x8b,0x95,0xe7,0xde,0xca,0xd5,0xdf,0x07,0xc4,0x0a,0xf8,0x31,0xbd,0x3b,0xbb,0x6a, + 0x6d,0xd5,0x3b,0xf0,0xdf,0xe9,0xc6,0xac,0xad,0x93,0xcf,0xab,0x1f,0x31,0xda,0xa9, + 0x3a,0xfe,0x86,0x9f,0x92,0x67,0xc0,0xc3,0xce,0x87,0xe4,0xeb,0xf7,0xe7,0xd2,0x0d, + 0xfd,0x5f,0xf8,0x09,0xff,0x58,0xdb,0x6b,0xcf,0x86,0x26,0x9d,0x0d,0x2b,0xbd,0x26, + 0xd6,0x71,0xdf,0x19,0x19,0x1c,0xaf,0x4c,0x8b,0x35,0xa4,0x4e,0x7e,0x32,0x2d,0xf7, + 0xfb,0x1b,0xed,0x35,0x96,0x7e,0xdf,0x09,0x7f,0x21,0x2e,0x3a,0xe3,0x28,0x21,0xe5, + 0x9b,0x76,0x70,0x9f,0x57,0x1d,0x8f,0x13,0x6a,0xe6,0x3f,0x99,0x7f,0x72,0xb2,0x5a, + 0xb8,0x88,0x38,0x0b,0x12,0xb0,0x10,0xd0,0x3f,0x53,0xa6,0x7e,0x2f,0xd1,0xce,0xcd, + 0x8c,0xef,0x18,0xa8,0x59,0x0e,0xc7,0xd3,0x07,0x94,0x3f,0xcc,0xf0,0x2f,0xe4,0xce, + 0x7f,0xc2,0x95,0xf5,0x61,0xb5,0xb8,0x1f,0xf1,0x73,0x46,0x69,0x54,0xc4,0x0c,0xd7, + 0x6e,0x9e,0xa1,0x93,0xae,0x73,0x37,0xa0,0x5e,0x79,0x20,0x66,0x6b,0x92,0x4f,0xc2, + 0xe7,0xe3,0xce,0xe9,0x56,0x35,0xaf,0x7e,0xb4,0x57,0x4d,0x77,0x6e,0xef,0xbf,0x2d, + 0x00,0x54,0x59,0x16,0x2f,0x9a,0x7b,0xfe,0xf3,0x10,0xf5,0xc5,0xa3,0xec,0x7b,0x84, + 0x17,0x94,0xba,0xa8,0x88,0xf8,0x59,0x62,0xf8,0xa7,0xc7,0x09,0x43,0x1e,0xdf,0x4a, + 0x7b,0x95,0xfd,0x29,0x92,0x40,0xc7,0xb9,0x35,0x4f,0xbf,0xdb,0x36,0x28,0x87,0x94, + 0xd0,0x5a,0xe7,0xe9,0x82,0x97,0x92,0xe7,0xe5,0xf0,0x1a,0xe7,0x01,0x5e,0x9d,0x67, + 0xe8,0xf7,0x07,0xa7,0x94,0x99,0x78,0x73,0xa4,0xf8,0xfd,0xd2,0x3f,0x53,0xae,0x96, + 0xdf,0x69,0x77,0x7d,0x9c,0x77,0x7e,0x7e,0x1a,0x35,0x60,0x3d,0xb8,0x54,0xbe,0x03, + 0xc6,0x58,0x00,0x1d,0xe7,0x83,0x29,0xe3,0xfc,0x92,0xf7,0x3c,0xf4,0x50,0x9f,0xec, + 0xe8,0x21,0x3e,0x6c,0xd4,0xc8,0xf6,0x3e,0x12,0x34,0x6b,0xde,0x90,0x86,0x5d,0x44, + 0x86,0x95,0xe0,0xd3,0x41,0xbf,0x30,0x48,0x42,0xc6,0x5e,0x51,0x85,0x01,0x3f,0xca, + 0x76,0x74,0x67,0x0c,0x5e,0xe8,0xe0,0x82,0x3d,0xe3,0x36,0xc7,0x71,0x65,0xe7,0xd8, + 0xe7,0x43,0xf1,0xd5,0x19,0xc7,0x42,0x72,0x8c,0x2e,0x8b,0xa3,0x9f,0x81,0x11,0x57, + 0xb2,0x5c,0x1f,0x7c,0x0c,0xcd,0xeb,0x11,0x36,0x3f,0x56,0xfe,0x39,0xd5,0x18,0x77, + 0x29,0x8e,0x1c,0xff,0xdc,0x25,0x5f,0xf3,0x84,0x14,0x67,0x90,0x17,0x84,0x37,0x49, + 0x50,0x09,0xa4,0x79,0x8f,0x75,0x7e,0xa9,0xa6,0xaf,0x37,0xe1,0x53,0xc4,0x21,0x56, + 0xd3,0x40,0x4d,0x89,0x81,0xbe,0x91,0x82,0x31,0x97,0x7b,0x49,0x86,0xca,0x54,0xe4, + 0x50,0xe1,0x3d,0x03,0xd8,0x90,0x48,0x83,0xd1,0x17,0x97,0xbe,0x0c,0x94,0xca,0x69, + 0x51,0x24,0x2f,0x8a,0x09,0xf6,0xfd,0x91,0xb7,0x20,0x9c,0xd4,0xfb,0xa2,0xe2,0x0a, + 0xf8,0x88,0x06,0x69,0x80,0x73,0x0c,0xc0,0x69,0xc8,0xa4,0x9d,0x4b,0x1c,0xb7,0x99, + 0xfa,0xbd,0x6c,0x9b,0x7a,0x45,0x0e,0x27,0xe7,0x51,0xae,0x5d,0xb9,0x8a,0xba,0xc3, + 0x75,0xa8,0x75,0xdc,0xd2,0x6a,0xfd,0xce,0x61,0x08,0x65,0xd9,0x67,0x16,0xec,0xfb, + 0x23,0x15,0x31,0x6b,0xd8,0x38,0x03,0x12,0x15,0xb7,0xc1,0x93,0xb0,0x4b,0x15,0xf5, + 0xfa,0x3b,0xe2,0xa7,0x42,0x4c,0xae,0x28,0xc3,0x5f,0x92,0xcd,0x7a,0xd9,0x08,0x35, + 0x10,0xe3,0xc2,0xed,0x56,0xfe,0xb3,0x5d,0xd8,0x86,0x3f,0x92,0xc7,0xc5,0x26,0x56, + 0x7f,0x57,0xe4,0x33,0x8e,0x7e,0x0b,0x0b,0x26,0xcb,0x46,0xc9,0x71,0x94,0xed,0x81, + 0x17,0xf8,0x9f,0xa3,0xf0,0x1b,0x4c,0xb9,0xb2,0x39,0xfe,0xa9,0xd7,0x8f,0x88,0x8e, + 0x9f,0x62,0x13,0xec,0x50,0xbb,0x2d,0xfe,0x89,0x7c,0xfe,0x1c,0xab,0x33,0xbb,0xf9, + 0x6a,0x0d,0x0b,0x56,0xa5,0x4a,0x89,0x64,0xbe,0xbf,0xf5,0x9a,0x19,0x1d,0x7d,0x3e, + 0x5d,0xac,0x23,0x46,0xca,0x46,0xae,0xa4,0xc1,0xb6,0x14,0x7e,0x28,0x57,0x29,0x8e, + 0x71,0xb2,0x14,0xd8,0xf7,0x47,0xe2,0x38,0x31,0xb6,0x2d,0xf2,0x2c,0x0f,0xdd,0x24, + 0x57,0x46,0x1d,0x6b,0x88,0x87,0xfe,0x58,0xae,0x8d,0x8a,0xa7,0xed,0xe6,0xf7,0x47, + 0x33,0xf3,0x59,0xfe,0x93,0xd5,0xa7,0x1d,0x5a,0x7e,0x10,0xa3,0x3f,0xbf,0xcc,0x18, + 0xd7,0x33,0x7f,0xe2,0xa1,0x2b,0x9e,0x70,0x9b,0xeb,0xe9,0xd6,0x89,0x98,0xde,0xe0, + 0xdf,0x13,0x4c,0xfc,0x7c,0x83,0xbe,0x2e,0x87,0x23,0xae,0xd3,0xdd,0x13,0x70,0x9f, + 0xd8,0x8c,0x98,0xd5,0xed,0x23,0xb9,0xfa,0xd1,0x56,0x46,0x3b,0x93,0x91,0x2c,0xf3, + 0xb3,0xb2,0xde,0x24,0x79,0xd2,0xd2,0xef,0x9b,0xa0,0xab,0x2d,0xa0,0xf0,0x12,0x79, + 0xd5,0xd3,0xc5,0x69,0xfc,0xf3,0x36,0x63,0xed,0x7d,0x42,0x3f,0xd1,0xa9,0x73,0x44, + 0x3f,0x43,0xd0,0x9b,0x22,0x3f,0x32,0xf9,0x27,0xcb,0x7f,0xea,0x47,0x3b,0xd9,0x01, + 0x05,0x6c,0xf4,0xf1,0x7e,0xcb,0x9e,0x49,0xe1,0x0a,0x67,0xe5,0x3c,0xb0,0xf1,0x0c, + 0x6f,0xf2,0x4f,0x56,0x3f,0x3a,0xa3,0x0c,0xb2,0xb2,0x11,0x2e,0x96,0x60,0xac,0x02, + 0x9e,0x98,0xdf,0x26,0xd9,0xee,0x86,0xad,0x5d,0x3e,0x2a,0x0e,0xb0,0x1c,0x35,0xd4, + 0x51,0x47,0x96,0x8f,0x98,0xfc,0x53,0xb8,0x8f,0x3e,0x9b,0x42,0xfe,0x79,0xb7,0x4f, + 0xcb,0x7f,0xaa,0x2b,0x65,0x62,0x8e,0xa3,0xd2,0x5a,0xd0,0x7d,0xa2,0xa0,0x9c,0xd3, + 0xc4,0xb3,0x4c,0x14,0xc5,0xb0,0x59,0xcf,0xef,0xc0,0xdf,0xa3,0x9b,0x38,0x3b,0x1d, + 0x86,0x90,0x6f,0xe7,0xcd,0xa3,0x46,0x62,0xd9,0x80,0x70,0x8d,0x43,0x0a,0x15,0xe4, + 0xa7,0xc4,0x3f,0xd5,0xce,0x55,0x5a,0xb9,0x6d,0xc5,0xf6,0x42,0xc4,0x90,0x99,0x9f, + 0xc0,0x6c,0x6a,0x79,0x56,0x9c,0xe4,0xc7,0x8d,0x81,0x2f,0xdc,0xba,0x55,0xdd,0x2c, + 0x6b,0x47,0x93,0xce,0x6a,0xf9,0xf9,0xbe,0x47,0x42,0xe7,0x8d,0xfd,0x27,0x41,0x5f, + 0x6a,0xb3,0x50,0xab,0xf6,0x76,0x90,0x87,0xe1,0x60,0x41,0xad,0x2a,0xae,0x77,0x4f, + 0x50,0xd3,0x3f,0xb7,0x6a,0x12,0x74,0xa5,0x9e,0x83,0x60,0xdf,0x1f,0x85,0x2c,0x3d, + 0x56,0xf6,0xde,0x02,0x43,0x66,0x6e,0xd0,0x92,0x0a,0xce,0x3d,0x7f,0x67,0xf2,0xcf, + 0x14,0x37,0x80,0x3f,0x6a,0xd2,0xeb,0xef,0x97,0x70,0xc2,0x8b,0xd3,0xf3,0xfe,0xd1, + 0x7c,0x0f,0x52,0x4a,0x3a,0x95,0x46,0xfd,0xde,0xc1,0x97,0x3b,0x4f,0x91,0x25,0xaa, + 0x98,0x2d,0x9d,0x34,0xe6,0xb2,0x0b,0x43,0x3a,0xca,0x61,0xa6,0xd1,0x03,0xc8,0x3f, + 0x7d,0x47,0x8a,0xd2,0x6b,0x66,0xda,0xf4,0xb5,0xd3,0x16,0x39,0xd8,0x0b,0xff,0x45, + 0x8d,0xee,0x2d,0x08,0x68,0x67,0x19,0xb5,0xf3,0x9f,0x86,0x5d,0x3c,0x4e,0x59,0x3f, + 0xbe,0x82,0xbc,0x15,0xb5,0xe8,0x78,0xaf,0xec,0xce,0xe5,0x3f,0xd7,0x25,0x7a,0x95, + 0x46,0x35,0x90,0xe1,0x03,0x02,0x3b,0x40,0x53,0x9c,0xe6,0xcd,0x9c,0x40,0xba,0xec, + 0x6c,0xfa,0x86,0x1f,0x69,0xe7,0x38,0xaf,0x7f,0xd7,0xf3,0x54,0x96,0xcf,0x26,0x4d, + 0xfc,0xbc,0x00,0x33,0x05,0xf5,0xba,0x3d,0xaf,0x41,0xbd,0xea,0xcc,0xff,0xfe,0xe8, + 0x02,0x0c,0x15,0xb0,0x63,0x9f,0xca,0x05,0x78,0x85,0x7e,0x4f,0x15,0xe7,0x7c,0x7f, + 0x04,0x19,0xa2,0x7d,0x76,0x34,0xe6,0x65,0x87,0x67,0xc5,0xb9,0xdf,0x1f,0x0d,0xe9, + 0x32,0x7a,0x8a,0x1d,0x5e,0x67,0x0b,0x9d,0x36,0xf2,0x36,0x8c,0x7f,0xce,0xe8,0x69, + 0xcf,0x29,0xf1,0x1a,0x09,0xb1,0x09,0xe7,0xd5,0xdf,0x3d,0x9f,0x1c,0xd5,0x8f,0x7d, + 0x7a,0xb5,0xda,0xcb,0xdc,0xfc,0xe7,0x01,0x39,0x64,0xd8,0x1a,0x79,0x9d,0x7f,0x4e, + 0xfd,0x1d,0xdd,0x52,0x4b,0x7b,0x4e,0x09,0x48,0x28,0x8f,0x88,0x99,0x48,0xde,0xf9, + 0x25,0x29,0xa3,0x68,0x67,0x7b,0xf1,0xdd,0x26,0x31,0x48,0xe6,0xbe,0x3f,0x8a,0xb7, + 0x54,0xc0,0x81,0xcc,0x2e,0x26,0x95,0xdf,0xa1,0x07,0x53,0x95,0x53,0x85,0xf9,0xdf, + 0x1f,0x15,0xab,0x57,0xd2,0xc1,0xec,0x8e,0x06,0xfe,0xa4,0x72,0x29,0x15,0xcc,0x16, + 0xe5,0x7f,0x7f,0xc4,0xce,0xcf,0x37,0x33,0xda,0xa9,0x25,0x70,0x8e,0x14,0xe7,0x7f, + 0x7f,0x84,0x31,0x55,0x1c,0x34,0xce,0x64,0xc8,0xa1,0xd1,0x40,0xfe,0xf7,0x47,0xe5, + 0x82,0x7e,0xec,0xd3,0x7d,0x56,0x7c,0x25,0xe6,0x7f,0x43,0x9c,0xf3,0xfd,0x11,0x32, + 0x6f,0x2d,0x85,0xf0,0x0e,0x92,0xe2,0x05,0x93,0x22,0xfb,0xfe,0x48,0x5f,0x9f,0x96, + 0x5f,0x3a,0x22,0x9b,0x39,0xb2,0x3a,0x66,0xeb,0xfc,0xef,0x8f,0xae,0xd2,0x90,0x7e, + 0x7e,0xe9,0x22,0x2c,0x63,0xf5,0xf7,0x39,0xdf,0x1f,0x55,0x5a,0xdf,0x1f,0xdd,0x94, + 0xff,0x9c,0x80,0x6b,0xca,0xa0,0xb2,0x3a,0xd5,0x3a,0xe1,0xd1,0xbf,0xb3,0x69,0x9d, + 0xc3,0x3f,0x61,0xb7,0xf2,0x57,0x5a,0x8e,0x53,0x62,0xe7,0xe7,0xf9,0x74,0x5e,0xfe, + 0x73,0x2f,0xa9,0x51,0x56,0x22,0xf6,0x70,0x87,0x14,0x8c,0x55,0xa9,0x48,0x3e,0xff, + 0xdc,0x27,0x6b,0xc7,0x3e,0x47,0x90,0x54,0xc9,0x51,0xe4,0x9f,0x89,0xbc,0xfa,0xd1, + 0x74,0x8c,0x51,0xc4,0xd6,0x2c,0x74,0x42,0xc8,0xe3,0xcc,0xe5,0x3f,0xfb,0xb4,0xf3, + 0xf3,0xcb,0x10,0xcf,0x18,0x2e,0x49,0xe1,0xb6,0x1d,0x29,0xfe,0x6f,0x8c,0xfc,0x27, + 0xab,0xbf,0xdf,0xf0,0xb3,0x73,0x56,0xd8,0x77,0x43,0xd4,0x0e,0x16,0xe5,0xbe,0x3f, + 0xca,0xc2,0x50,0x7c,0x10,0xef,0xe9,0x63,0x89,0x50,0xdf,0xfc,0xde,0x39,0xdf,0x1f, + 0xc1,0x5e,0xa7,0x46,0x3b,0x47,0xa4,0xbd,0x20,0x47,0x1c,0x79,0xdf,0x1f,0x21,0xff, + 0x3c,0x14,0x5f,0x38,0x37,0x87,0x9b,0xf7,0xfd,0xd1,0x15,0x45,0x3f,0x2f,0x25,0x5c, + 0x81,0x41,0xed,0xfc,0xa7,0xf5,0xfd,0x51,0x3f,0x5c,0x11,0x1a,0xf3,0xf0,0x93,0x7d, + 0x7f,0xa4,0x8f,0x33,0xf8,0xa7,0x66,0x6b,0xef,0x8c,0x26,0xe4,0xe7,0x7c,0x7f,0xf4, + 0x72,0x0f,0xd3,0x9b,0xee,0x49,0x38,0x90,0xf2,0xd1,0x9b,0xea,0xef,0x87,0xa9,0xf1, + 0x6e,0x07,0xb1,0xd1,0x93,0xcb,0x7f,0x32,0xfe,0x79,0xc0,0x3c,0x33,0x74,0x40,0xac, + 0x9c,0x14,0x3b,0xdc,0x79,0xdf,0x1f,0xc1,0x2c,0x3b,0xbf,0xc4,0xf2,0x9f,0x97,0x92, + 0xf5,0x33,0x81,0xce,0x39,0xe7,0xe7,0xaf,0x02,0x3b,0x4e,0xa9,0xf9,0xe7,0xcb,0x6f, + 0xcd,0x39,0xbf,0x74,0x01,0x6e,0xd0,0x30,0xee,0xf7,0x79,0xfa,0xf7,0x86,0xb8,0xdf, + 0xf3,0xbe,0x3f,0xa2,0xfb,0xd3,0x81,0x49,0x47,0xe3,0x2d,0x27,0xe1,0x60,0x56,0x9e, + 0x14,0x1b,0xad,0x6f,0x85,0x90,0x7f,0xd2,0x83,0x0c,0x5b,0x1f,0x77,0x9f,0xa5,0x07, + 0x25,0x79,0x54,0x7c,0xdc,0x8a,0xef,0x1a,0xff,0xa4,0x7a,0x0e,0x57,0x60,0x07,0x84, + 0xe6,0x7c,0x7f,0xb4,0x87,0x1d,0x01,0xd0,0xf7,0xfb,0x47,0xb0,0x8f,0xed,0x77,0xf3, + 0x9e,0x29,0xe4,0x9f,0x48,0x3f,0x8c,0xbd,0xd2,0xc2,0x3e,0x4a,0xb4,0xf2,0x9f,0x94, + 0xd5,0xdf,0x49,0xbd,0x71,0xee,0x89,0xe1,0xd2,0xdc,0xef,0x8f,0x5e,0x54,0x7c,0x47, + 0x7a,0x33,0xbe,0x29,0xe1,0xb0,0xca,0xea,0xef,0xbe,0x7c,0xfe,0x99,0x51,0x16,0x1a, + 0xd8,0x43,0x65,0x75,0x6e,0xfd,0x5d,0xcd,0x04,0xe5,0x31,0x76,0xe6,0xb2,0x6b,0x5f, + 0x95,0x3c,0x3a,0x19,0xb4,0xce,0xcf,0xd3,0xa2,0x0d,0xe9,0x6b,0x10,0x1a,0x75,0x1d, + 0xec,0xfe,0x30,0x73,0xcd,0x5d,0x3f,0xee,0x3c,0x58,0x6a,0xd5,0xdf,0xe7,0x5f,0x4f, + 0x5e,0x8d,0x37,0x8f,0x9d,0x1a,0x6c,0x9d,0x4a,0xcf,0x06,0xc3,0x27,0x5d,0x83,0x56, + 0xfe,0x13,0xd4,0x16,0x5b,0x87,0x72,0x56,0xfa,0x9c,0x60,0x7b,0x95,0xdb,0xb8,0xe5, + 0xe1,0xe8,0x97,0x84,0xf9,0xaa,0x3e,0x4d,0x80,0x57,0xdb,0x6c,0x1b,0x61,0x55,0xcb, + 0xe7,0xa4,0xb2,0xa3,0x05,0x72,0xb0,0x7c,0x55,0x95,0x64,0x53,0x97,0xc4,0x8c,0x71, + 0x11,0x0e,0xc9,0x9c,0xec,0x16,0x85,0x27,0x5b,0xe4,0xfd,0xd1,0x0d,0x44,0x14,0xa8, + 0x71,0xde,0x14,0xf9,0x28,0x2a,0xc8,0xb5,0x70,0x0b,0xd8,0x68,0x65,0x47,0x61,0xd4, + 0xee,0x96,0x6d,0xd4,0xba,0x67,0x94,0x7b,0x1c,0x1e,0xa6,0x9f,0x93,0x6d,0xa3,0x9b, + 0xfe,0xb8,0xe1,0xbe,0xa5,0xee,0xf5,0x1e,0x6a,0xde,0xf3,0xd5,0x18,0xc4,0x39,0x2f, + 0xac,0x80,0x12,0x0a,0xf1,0x07,0x45,0x21,0xc2,0x01,0x5d,0x62,0x8e,0x53,0x40,0xe6, + 0x44,0x88,0x80,0x44,0x85,0x2a,0x4e,0xa4,0xac,0x61,0xf5,0x7d,0xb1,0x4c,0xe9,0x8a, + 0xc9,0x0f,0x89,0x65,0x3c,0x17,0xc9,0x2a,0x93,0x92,0xb7,0x0c,0x4a,0x8c,0x7b,0x52, + 0x27,0xf7,0x39,0x68,0x51,0xa5,0x0e,0xc1,0xc9,0xdd,0x29,0xb7,0xac,0x95,0xbe,0x21, + 0x40,0xa5,0x31,0x8e,0x2a,0x02,0x9b,0x31,0xb3,0xae,0x70,0x2b,0x67,0x8f,0x22,0x41, + 0xe5,0x8c,0xfa,0x11,0xbc,0x1a,0x27,0x5e,0x2e,0x81,0xbf,0x83,0xce,0xee,0x05,0x22, + 0x41,0xd2,0xcb,0x99,0xf3,0x3c,0x12,0xe3,0xd6,0xc3,0x7d,0xb0,0x46,0x29,0xa7,0xb6, + 0xf5,0xdc,0x7d,0xa8,0x7e,0x1f,0xa2,0xe6,0x3d,0x5f,0x85,0x42,0xb6,0xf6,0x65,0x50, + 0x44,0x39,0x56,0x2e,0x5d,0x83,0x46,0xb0,0xe6,0x19,0x29,0x08,0x76,0x39,0x65,0x5e, + 0x04,0x74,0x67,0x34,0x1e,0xd2,0x11,0xcb,0x9e,0x49,0x31,0x16,0x62,0xa2,0x8f,0x65, + 0x07,0x65,0x41,0x64,0x7f,0x23,0x41,0xb5,0xec,0xe9,0xe0,0x42,0xea,0x2a,0x2d,0x32, + 0x72,0x41,0x1a,0x45,0xa3,0xb7,0xa9,0xb2,0x79,0xcf,0xd6,0x05,0x71,0x35,0x1a,0xbc, + 0xc5,0x29,0x74,0xdb,0x3a,0xb4,0x3e,0x5b,0xce,0x9e,0x11,0x78,0xbc,0x4b,0x94,0x57, + 0xf8,0x25,0xb4,0x27,0xa0,0xf1,0xc4,0x3c,0x9b,0xad,0x11,0x16,0x76,0x15,0xa6,0x23, + 0xed,0xd2,0xf3,0x42,0x35,0x2d,0x0c,0x46,0xa2,0x79,0x7d,0xf8,0x16,0xb8,0x08,0xc4, + 0xa8,0x47,0x36,0x1b,0x60,0xde,0x93,0x16,0x70,0x2d,0x34,0x16,0xf7,0x78,0x6d,0x05, + 0xdc,0x7d,0x94,0xc4,0x25,0xaf,0x79,0x02,0x19,0xfb,0xdc,0x36,0x01,0x09,0x80,0x14, + 0x15,0x9e,0x31,0x1a,0xa6,0x44,0xc0,0x7b,0xae,0xe0,0x1f,0xa4,0x6f,0xc4,0xff,0xd8, + 0x3b,0x9f,0x35,0x70,0x3a,0x5e,0x50,0xac,0x79,0xae,0x28,0xdc,0xd8,0x75,0x36,0xfe, + 0x25,0x6f,0xd9,0x51,0x5b,0x47,0xd7,0xc3,0xf2,0x7f,0xf5,0x96,0x59,0x73,0xb9,0x37, + 0xc2,0x6d,0xa4,0x67,0xe3,0x77,0x79,0x8b,0x8e,0x72,0x1d,0xf4,0x6c,0xe5,0x5d,0xe2, + 0x7c,0xb5,0xc4,0xec,0x5b,0x51,0xb0,0x84,0x3a,0xe3,0xf3,0xbc,0xca,0xd1,0x82,0x3f, + 0xa6,0x45,0xf1,0x2a,0xaf,0x48,0xcd,0xf7,0x0e,0x84,0x7b,0x84,0xf9,0xa7,0x1f,0xb6, + 0xa2,0xa3,0x3a,0xe5,0x5b,0xd0,0x3f,0x8d,0x7d,0x04,0x50,0xc0,0x55,0x25,0xa3,0xd3, + 0xee,0x06,0x61,0x3b,0x57,0x49,0xd7,0xc6,0xdd,0x5e,0xec,0x33,0xef,0xa9,0x94,0x75, + 0xc0,0x2a,0x28,0x05,0x41,0xb5,0x75,0xc8,0x51,0xc2,0x1a,0xe6,0x3d,0xef,0x8d,0x40, + 0x1c,0xed,0x89,0x66,0x4c,0x40,0x3c,0x2d,0xfa,0x89,0x5d,0xa2,0xd6,0x5c,0x22,0x82, + 0xdc,0xe5,0x95,0x57,0x88,0x25,0x09,0x01,0x37,0x06,0xf6,0x95,0xe4,0xf5,0x55,0x2a, + 0x47,0x1e,0x0a,0xde,0xeb,0x2c,0x8b,0x70,0x4a,0x97,0x22,0xbb,0x9d,0x36,0x25,0x6f, + 0x9e,0x31,0xfa,0x90,0x5c,0x26,0xda,0x22,0xd8,0x50,0xe4,0x12,0x71,0x93,0x39,0x4b, + 0x96,0xb1,0x53,0x30,0x6e,0x15,0x40,0x8b,0x28,0x20,0x3e,0x08,0xc0,0x71,0x56,0xd7, + 0xbd,0x11,0x22,0x77,0x51,0x39,0x2e,0x7a,0xdd,0x09,0x61,0x80,0x5b,0x08,0xa2,0xd7, + 0xf2,0xf9,0x7b,0x95,0x79,0x71,0x65,0x2d,0xfc,0xb6,0x50,0xd6,0x75,0x6f,0xbc,0x04, + 0x35,0x29,0x94,0x59,0x73,0x79,0x55,0xe1,0x82,0xa0,0x67,0x6a,0x5b,0x64,0xf9,0x4c, + 0xd1,0x2d,0x50,0x6e,0xad,0x1d,0x0d,0x83,0xaf,0x8b,0xa2,0xeb,0xf5,0x2c,0x94,0xfd, + 0x62,0x41,0x81,0x00,0xb9,0x3e,0x89,0x89,0x4c,0x20,0x0a,0xc2,0xde,0x02,0xa9,0x30, + 0x4e,0x62,0x79,0x7d,0x02,0xb7,0x04,0xa2,0x8a,0x5b,0x12,0xfa,0xb9,0x45,0x70,0xbf, + 0x52,0x5a,0xee,0x51,0xad,0xbe,0x2a,0x5b,0xbb,0xfa,0x3b,0xc1,0x5b,0xb6,0xd9,0x76, + 0xdb,0xda,0xe9,0xfd,0x71,0xf7,0xce,0x92,0x39,0xf7,0xe4,0x0a,0x21,0xa2,0x48,0x29, + 0xb8,0x53,0xd1,0x6e,0x9e,0xeb,0x13,0x85,0x78,0x89,0x57,0x58,0xc1,0x95,0xf4,0xb4, + 0x05,0x25,0xb1,0x80,0x70,0x4f,0xe7,0xcd,0xb3,0x25,0x56,0xe2,0x11,0x7e,0x8b,0x2b, + 0x53,0x5a,0xa4,0x12,0x45,0x78,0x90,0xb3,0xe5,0xd9,0xac,0x32,0x22,0x3e,0x94,0x28, + 0x93,0x37,0x45,0x2b,0x23,0x7e,0x05,0x1b,0xc9,0xdc,0x30,0x3b,0x47,0xa8,0x92,0x96, + 0xfc,0x60,0x5f,0x80,0x8d,0xdd,0x8a,0x3f,0xd7,0x05,0x4e,0xfe,0x41,0xee,0x39,0x15, + 0xfd,0xb9,0x8d,0xff,0x22,0xcb,0x6b,0x06,0xbd,0x79,0xf7,0x9c,0x87,0x98,0x05,0x5f, + 0x92,0xcb,0x46,0x6d,0x8f,0x97,0x3c,0x9c,0xf8,0x92,0xaf,0x2c,0xb7,0x3e,0x94,0xcf, + 0xaa,0x14,0x44,0x74,0xa9,0x32,0x1b,0xb9,0x7b,0x36,0xcf,0xae,0x9e,0xfd,0xfb,0xd9, + 0xcb,0xb3,0x37,0xac,0x06,0xfc,0xab,0xae,0x65,0x6f,0x3b,0x96,0x0d,0xbf,0x9e,0xd9, + 0xb7,0x21,0xf0,0xae,0x3e,0x6e,0x2a,0xd7,0xf7,0xf9,0xa6,0x55,0xa7,0x4a,0xeb,0x47, + 0xc6,0x3e,0xaa,0x6f,0xd6,0xfb,0x3e,0xca,0x7b,0x9e,0x37,0x7a,0xd4,0xbd,0x24,0xb9, + 0x6d,0xdd,0x3d,0x66,0x23,0xd7,0x67,0x23,0x1b,0x95,0x9d,0xb1,0x79,0x9e,0xc2,0x57, + 0x59,0xa3,0xe3,0x2e,0x4f,0x61,0x6e,0x0d,0xc2,0xbc,0x8d,0xdc,0xc3,0xb8,0xff,0x6c, + 0x23,0x1c,0x36,0xf0,0x45,0x96,0xe4,0xfa,0x0a,0x70,0xfb,0x44,0x81,0xe1,0x3c,0xee, + 0x95,0xe8,0x9c,0xbd,0x82,0x20,0xb5,0x0e,0xf7,0xf1,0x0a,0x89,0xd3,0x37,0x74,0x01, + 0xe4,0xb0,0x00,0xdf,0xdf,0xe3,0xe8,0x5a,0xbf,0x29,0x73,0xa3,0x08,0x42,0xe5,0xb4, + 0xd4,0x9f,0x77,0x4f,0x80,0x75,0x1c,0xfb,0x75,0xdc,0x2b,0x6c,0xdc,0x0a,0xe0,0x72, + 0xf7,0xf4,0x08,0x0b,0xba,0x34,0x9f,0x78,0x4e,0x58,0xc8,0x15,0x2a,0x91,0x3f,0x92, + 0x72,0x7d,0x55,0x10,0xed,0x72,0x83,0xd0,0x57,0xe2,0x13,0xee,0xe7,0xdc,0xf2,0xbd, + 0x03,0x25,0xd6,0xd3,0x54,0x27,0xee,0x59,0x94,0x03,0x0d,0xe0,0x04,0x9e,0x22,0x1f, + 0x0d,0x72,0x46,0x48,0xc5,0x9f,0xde,0x02,0x65,0xc0,0x65,0x85,0x98,0x72,0x8b,0x64, + 0x63,0xb1,0x29,0xc6,0x19,0x61,0x1a,0xc7,0x29,0x88,0xed,0x2c,0x13,0xc5,0xe6,0x03, + 0x3a,0x4e,0xe6,0xfa,0x84,0x38,0xc6,0x9c,0xdf,0x63,0x31,0x47,0x0f,0x3e,0x25,0x66, + 0x1c,0x93,0x38,0xc5,0x13,0xb7,0x79,0x69,0x01,0x14,0xb2,0x31,0x7d,0xf8,0x4b,0x85, + 0x09,0xe3,0x71,0x0a,0x62,0x81,0xd4,0xb5,0x4d,0x6e,0x15,0x25,0xa4,0xa4,0x1a,0xe0, + 0x4b,0x26,0x86,0x28,0x78,0xfb,0x10,0x9b,0x22,0xc3,0xf9,0x20,0x63,0x59,0x8c,0x3b, + 0x1b,0xe3,0x14,0x07,0x84,0x54,0x67,0xb0,0x95,0x65,0xe0,0x83,0xd4,0x99,0x69,0x15, + 0x8d,0xbf,0xd2,0xc3,0xee,0xd9,0x0a,0x1d,0x48,0x4c,0x7e,0x5b,0xfb,0x0b,0x28,0x5d, + 0xde,0x20,0x02,0x0d,0xb5,0xee,0x89,0xb8,0x84,0x58,0x87,0x8f,0xd1,0xb0,0x47,0x26, + 0xa2,0xb5,0x8f,0x62,0x08,0xdf,0xec,0x47,0x2b,0xb4,0x3e,0x04,0xa8,0x88,0x68,0xed, + 0x3f,0xe5,0x5e,0x3d,0xfe,0x71,0xa0,0x61,0x8b,0x07,0x9b,0x0f,0x46,0x8c,0x7b,0x46, + 0x19,0xea,0x50,0x29,0x2e,0x78,0x39,0xbd,0x21,0x79,0x2d,0xbf,0x8e,0x2a,0xc4,0x06, + 0x08,0x63,0x92,0x28,0x60,0x83,0x6a,0x0d,0xb0,0xe6,0xa9,0xe3,0xfc,0x9d,0xde,0x22, + 0xd6,0x18,0x89,0x7f,0xd5,0x5b,0x94,0xc3,0xba,0x15,0xb0,0xb1,0xab,0x3c,0xfe,0xfb, + 0xde,0x92,0xa3,0xc2,0xc6,0xae,0x55,0xf1,0xdf,0xf4,0x5a,0x3e,0xa1,0x70,0x2b,0x60, + 0x09,0xdd,0x19,0xff,0x9c,0xf7,0xd6,0xa3,0x05,0x1b,0xbb,0x76,0xc6,0x3f,0xef,0xb5, + 0xfc,0x33,0xa6,0xe1,0xbc,0x88,0xbf,0x1e,0x3d,0x0a,0x4b,0xba,0x1e,0xc6,0xc8,0x5c, + 0x36,0x6c,0xae,0x9d,0x73,0x73,0xd5,0xf4,0x3e,0xb9,0x94,0x05,0x6f,0xd6,0x70,0x47, + 0x05,0x13,0xe7,0x15,0x5c,0x43,0x25,0x8e,0x5b,0xe1,0x85,0x27,0xa1,0xb2,0xcb,0xcb, + 0x22,0x3a,0x35,0xbe,0x2f,0x86,0x7b,0xe3,0x42,0x27,0x14,0xc3,0x6f,0x52,0x29,0x2b, + 0x34,0x70,0xc5,0xe8,0x33,0xb9,0x77,0xc4,0xad,0x81,0xf5,0x5d,0x85,0x72,0x81,0x7e, + 0xcf,0x42,0x39,0x12,0x45,0x3e,0x67,0xcc,0xd3,0x46,0x4c,0x33,0x26,0x84,0x47,0x74, + 0xc0,0xb7,0xfa,0x30,0x3e,0x28,0x47,0x3c,0x32,0x42,0x40,0xab,0x10,0x53,0x3d,0x08, + 0xf8,0x25,0x4a,0xde,0x3b,0xc2,0x30,0x1a,0xb4,0x89,0xf8,0x42,0xd6,0x60,0x60,0xb5, + 0x39,0xd1,0x3f,0x8d,0x3e,0x41,0xc3,0x79,0xaa,0x19,0x51,0xd1,0x5f,0x86,0x69,0x6b, + 0xbc,0x27,0x01,0xc4,0x79,0x59,0xf4,0x92,0x02,0x99,0x22,0xe0,0xfb,0x45,0xb0,0xe6, + 0x09,0x05,0x8c,0x2f,0xfd,0x1e,0xba,0xa5,0x60,0x11,0x27,0xd3,0x9e,0xa0,0xe1,0xf5, + 0x3c,0xc5,0x3b,0x4e,0xaa,0xe1,0x5b,0xf0,0x88,0x52,0x98,0x7b,0xef,0xf1,0x02,0x91, + 0xb3,0xc3,0x0a,0x8a,0x32,0xdf,0x8f,0x6b,0xf7,0xe5,0xd6,0x1e,0x13,0x38,0xa8,0x8c, + 0x89,0x31,0x52,0xc6,0xfe,0x94,0x4d,0xcc,0xf9,0x10,0xf1,0xa0,0x7f,0x9a,0xf6,0x6c, + 0x03,0x1b,0x14,0x76,0xb4,0xc6,0x3c,0x6f,0xc0,0x02,0x28,0x8a,0x93,0xdf,0x86,0x61, + 0x6b,0xed,0xad,0x42,0x5c,0x91,0xa4,0xb6,0xf2,0x92,0x6e,0x14,0xa6,0x5e,0x69,0x45, + 0x45,0xce,0x3f,0x39,0x9d,0xbb,0x61,0x5c,0x49,0x0a,0xda,0x9f,0x45,0x92,0xc1,0x7a, + 0x47,0x9c,0xd8,0x86,0x38,0x4f,0x11,0xe7,0xe9,0x7a,0x1d,0xf0,0x9f,0xce,0xd9,0x53, + 0x51,0x62,0x1b,0x3d,0x60,0xb3,0x71,0x2d,0x23,0xb1,0x07,0x3d,0x82,0x4d,0xca,0xd9, + 0x53,0x10,0xd3,0x11,0xd1,0xb3,0x55,0xa8,0xec,0x42,0x9c,0x07,0xcf,0x93,0x36,0x19, + 0xed,0x69,0xbc,0x5b,0xce,0x6e,0x23,0xda,0xda,0x04,0x0d,0xf0,0xf7,0x80,0xdf,0xc2, + 0x25,0xe5,0xde,0x07,0xf8,0x2f,0x2a,0xc9,0xd3,0x77,0x2e,0x5d,0xfb,0xc0,0xbc,0x52, + 0xe5,0xb9,0xb3,0xeb,0x96,0x16,0x5a,0xf7,0xe4,0xa2,0xf2,0xe3,0x95,0x3b,0xe1,0xf7, + 0x71,0x2e,0x6d,0x8f,0x94,0x3c,0x2c,0xcc,0x83,0x3c,0x9c,0xd7,0xe1,0x1d,0x21,0xb5, + 0xca,0x1b,0x1d,0x61,0xd8,0xfa,0xef,0x80,0xf3,0xb5,0x9f,0x32,0xae,0xfe,0x53,0xfa, + 0x18,0xbc,0x97,0x1e,0xd4,0xe7,0xf2,0xda,0x33,0x4b,0x92,0x4f,0x5d,0xc9,0xf5,0x91, + 0x24,0xec,0x62,0x07,0x0f,0x25,0xab,0x91,0xeb,0xc3,0x0d,0xcb,0x19,0x1b,0xd6,0x68, + 0xe4,0x4d,0x26,0x89,0xbc,0x58,0x64,0x68,0x68,0x35,0x72,0xd7,0x5c,0xd7,0x54,0x20, + 0xbf,0x0f,0xc1,0x73,0x4c,0x7b,0xb9,0xdd,0x41,0xa3,0x91,0x9b,0x8b,0xd6,0x0b,0x62, + 0xae,0x61,0xcd,0x84,0xf1,0x0c,0x59,0x3b,0x3e,0x69,0xfd,0x0a,0xb1,0xfa,0xd8,0x7f, + 0x8d,0x69,0x3f,0xe6,0x43,0x7a,0x7f,0xae,0xcf,0x9e,0x24,0xbb,0x60,0x40,0xa9,0x91, + 0xf4,0x06,0xd4,0x48,0xb9,0x27,0xde,0xb4,0xbe,0xca,0xdc,0xfa,0xc4,0x9b,0xd7,0x57, + 0x49,0xac,0x71,0xa2,0xc4,0xfe,0x3e,0xda,0x18,0x2e,0xab,0x5c,0xc5,0x86,0xb6,0x3e, + 0x22,0x58,0xe3,0x36,0x07,0xf1,0xd7,0xbf,0x8e,0xe3,0xcc,0x46,0xee,0x79,0x84,0x11, + 0x24,0x59,0x11,0x73,0x8d,0x39,0xf6,0x94,0xd9,0xf3,0xf2,0x1a,0xe6,0x25,0x51,0x9e, + 0x85,0x91,0x7a,0xfc,0x87,0x37,0x75,0x91,0xf9,0x9d,0xcd,0xa7,0x5c,0x4d,0x4d,0xbf, + 0xfc,0x33,0x97,0xeb,0x5f,0x1c,0xf6,0x7f,0x71,0x35,0xcf,0xce,0xce,0xaa,0x73,0x1a, + 0xff,0x6f,0xf6,0x7d,0x9a,0xcf,0x03,0x73,0x05,0xc8,0xf9,0x3c,0xfc,0x3b,0xf9,0x7c, + 0xbe,0x57,0xe7,0x79,0xe0,0xa7,0xfa,0xbc,0x68,0xfa,0xbc,0xd5,0x98,0xeb,0xf3,0x73, + 0x47,0xfe,0x1a,0x9f,0x1f,0x1b,0xf8,0x7a,0x4d,0xf9,0x70,0x6e,0xdc,0xaf,0xdd,0xd3, + 0xbf,0xe4,0xf3,0xca,0x1c,0x9f,0xb7,0x96,0xa5,0x39,0xff,0xd7,0xa1,0x7c,0x58,0xf8, + 0x97,0xc7,0x7d,0xda,0x9e,0xfe,0x34,0xbb,0x40,0x1e,0x8b,0xcb,0x59,0x58,0xfe,0xe5, + 0x9f,0xdd,0x74,0x7d,0xe6,0xf3,0xbf,0xae,0xef,0xd7,0x5f,0xec,0x6f,0x39,0x12,0xed, + 0xdf,0x2d,0xaf,0xfd,0x6b,0xc7,0x7c,0x76,0x7d,0x76,0x7d,0x76,0x7d,0x76,0x7d,0x76, + 0x7d,0x76,0xfd,0xff,0x72,0x69,0x71,0x92,0x68,0x71,0x52,0xfd,0x8f,0x9e,0xcb,0x67, + 0xd7,0x67,0xd7,0x67,0xd7,0x67,0xd7,0x67,0xd7,0x67,0xd7,0x7f,0xc4,0x15,0x64,0x65, + 0x00,0xd8,0xfb,0xb2,0xf1,0xf7,0xff,0xf9,0x20,0x28,0xf3,0x3e,0xfd,0xf7,0xb5,0xdf, + 0xb3,0x05,0x21,0xcd,0xe5,0xc6,0xf7,0xa7,0x6e,0x9e,0xeb,0xff,0x01,0x51,0x16,0x5f, + 0xd0,0xd5,0x60,0x00,0x00, diff --git a/board/esd/cpci405/fpgadata_cpci405ab.c b/board/esd/cpci405/fpgadata_cpci405ab.c new file mode 100644 index 0000000..3f78473 --- /dev/null +++ b/board/esd/cpci405/fpgadata_cpci405ab.c @@ -0,0 +1,1285 @@ + 0x1f,0x8b,0x08,0x08,0x73,0xed,0xb5,0x40,0x00,0x03,0x63,0x70,0x63,0x69,0x34,0x30, + 0x35,0x5f,0x32,0x5f,0x30,0x35,0x2e,0x62,0x69,0x74,0x00,0xed,0xbd,0x0b,0x74,0x1c, + 0xd5,0x95,0x36,0xba,0xeb,0x54,0xb5,0x54,0xea,0x6e,0xa9,0x4b,0x2d,0x89,0x08,0xfc, + 0xa0,0xd4,0x92,0x8d,0xec,0xb4,0xe4,0x76,0xdb,0x18,0x23,0x84,0x54,0x6e,0x09,0xa7, + 0x01,0x83,0x15,0x1e,0x09,0x33,0xc3,0xcd,0xb4,0xc1,0x99,0xf1,0xcc,0x72,0x66,0x84, + 0x93,0x95,0x31,0x24,0x93,0x39,0x7a,0xd8,0x16,0x96,0xc1,0x6d,0xe3,0x99,0x98,0xc0, + 0xe5,0x6f,0x3f,0x48,0x0c,0x71,0xf2,0xb7,0x65,0xc0,0xe2,0x31,0x50,0x12,0xc2,0xb4, + 0x1f,0xd8,0x0a,0xf0,0xcf,0x98,0xc7,0x98,0x36,0x51,0x88,0x00,0x01,0xf2,0xe3,0x27, + 0x32,0x96,0xad,0xbb,0xcf,0x39,0x55,0xd5,0x2d,0xc9,0x64,0x32,0x6b,0xcd,0xba,0x8f, + 0x75,0xe9,0xac,0x95,0xec,0x94,0x8e,0xab,0xcf,0xa9,0x53,0x67,0x7f,0xfb,0xdb,0xfb, + 0x3b,0xa7,0x21,0xcf,0x37,0x2c,0xfe,0x03,0x20,0x2d,0x83,0xc2,0xbb,0x9b,0xef,0xfe, + 0x9b,0xf9,0xa1,0x2b,0xff,0x32,0xfc,0x97,0xa1,0x2b,0xab,0xff,0xee,0xee,0xe5,0x70, + 0x17,0xb8,0xc3,0xdf,0x9f,0x17,0xfa,0xc1,0x3d,0x73,0xe7,0xcf,0x87,0xbb,0xc1,0x13, + 0x0e,0x85,0xe6,0xcf,0x09,0x5d,0x39,0x27,0x7c,0x15,0x2c,0x87,0xbc,0xb9,0x57,0xd6, + 0xcc,0x9b,0x5b,0x13,0x5a,0x08,0xdf,0x05,0xd8,0xd9,0x3c,0x86,0x9f,0x27,0x1f,0xbe, + 0xfd,0xaf,0x42,0x40,0x25,0x00,0xc8,0x0d,0x49,0x31,0xf6,0xbf,0x6a,0x48,0xd2,0x25, + 0xa0,0xf5,0x55,0x21,0x30,0xd9,0xff,0x07,0xeb,0xef,0x79,0x21,0xd0,0xb3,0xff,0xbf, + 0x14,0x02,0x03,0x9a,0xa0,0xe2,0x6e,0xf0,0x87,0xe0,0xcb,0x3e,0x12,0x28,0x94,0x1b, + 0x7f,0x4a,0x1b,0xf2,0xa5,0x4d,0xd8,0xe7,0x4f,0x6f,0xe3,0xff,0x63,0x4d,0x94,0xff, + 0xae,0x36,0xfc,0xbf,0xc7,0xfc,0x50,0x8c,0xa6,0xc4,0x9e,0x44,0x31,0xb8,0xc6,0x1b, + 0xf5,0x7d,0xfc,0x3e,0xa6,0xeb,0x82,0x31,0x46,0xeb,0x0e,0xfb,0x4e,0xc9,0xaf,0x47, + 0x8e,0x42,0x67,0xff,0xd2,0xb3,0x72,0xd0,0x3c,0x0a,0xf3,0x52,0xdf,0x1b,0x69,0x18, + 0x86,0x66,0xde,0x71,0x6d,0xc8,0xfb,0x7c,0x7b,0xd5,0x6b,0x9e,0x93,0x24,0x4d,0x37, + 0xf6,0x95,0xf7,0x79,0x36,0x93,0x6b,0x8d,0x8d,0xfd,0x5f,0xff,0xdf,0x4b,0xba,0x49, + 0x5a,0xe1,0x0f,0xaf,0xc3,0x75,0xb8,0x63,0x2f,0x04,0x53,0x9e,0x50,0xdc,0xec,0x68, + 0x33,0x2a,0x53,0xd8,0x66,0x09,0x6d,0x83,0x4a,0x53,0x0d,0x45,0xde,0x97,0xf8,0x7d, + 0xcc,0xc2,0xdd,0xca,0xf3,0x50,0x6d,0x7a,0x92,0xe4,0x03,0xe8,0x24,0x01,0xd3,0x13, + 0x9f,0xbd,0x12,0x3c,0x78,0x45,0x4d,0x92,0x61,0x25,0xc6,0x3b,0x5d,0x38,0x04,0xe7, + 0x48,0x9d,0xe9,0x4b,0xca,0xbf,0x85,0x43,0x50,0x63,0xfa,0x34,0x79,0x25,0x74,0xa2, + 0x31,0x35,0x19,0xe8,0x57,0xf8,0x7d,0xd2,0xd2,0x0b,0x30,0x46,0xea,0xcd,0x8d,0xc3, + 0x0d,0xc3,0xa5,0xcc,0xf0,0xf5,0xcb,0xbb,0xe1,0x0f,0x70,0xb5,0x79,0xf9,0xb0,0x3c, + 0x02,0xfc,0x3e,0x86,0xb6,0x1b,0xce,0x49,0x75,0x66,0x30,0x29,0x97,0xc1,0x3b,0x6a, + 0xd8,0xf4,0x26,0xe5,0xc3,0xea,0x21,0x8d,0xdf,0xb9,0x5f,0xd1,0x59,0x9b,0x94,0x2b, + 0x08,0xcf,0xc3,0x1c,0xb3,0x74,0x38,0x37,0x56,0xfc,0xea,0xe1,0x72,0x53,0x8d,0x93, + 0x51,0xf5,0x28,0x9d,0xc2,0x7a,0x78,0x0a,0x5f,0x20,0xf6,0x5d,0xae,0x25,0x80,0xe3, + 0xc2,0x51,0x04,0x74,0xf2,0x50,0xaf,0x6e,0x96,0x86,0xc8,0x61,0xd8,0x01,0xde,0x1e, + 0x4f,0x88,0x8c,0xe0,0xf3,0xc4,0x8f,0x2e,0x4d,0x5f,0xb4,0x8f,0x56,0xa5,0xd5,0xd5, + 0x64,0x15,0xb4,0x6d,0x59,0x96,0x56,0xff,0x2c,0x70,0x1c,0xf0,0xca,0xa0,0xe7,0x3e, + 0x72,0x4c,0xdc,0x27,0xaa,0x16,0xd0,0xd3,0x50,0x3b,0xa8,0x3e,0x1b,0x20,0xbd,0x6f, + 0x48,0xe1,0xc1,0xe0,0x14,0xf9,0x48,0xde,0x6f,0x1f,0xaf,0x3d,0xe1,0xab,0x91,0x5f, + 0x17,0x2f,0x8e,0x31,0xed,0x05,0x63,0x0c,0xea,0xdf,0xf4,0xe1,0xb8,0x60,0x4c,0xad, + 0xff,0x37,0xdf,0x26,0x79,0x14,0x0e,0x69,0xd7,0xf4,0x5e,0x8e,0x7d,0xf6,0xf3,0x71, + 0xed,0x72,0x7d,0x8a,0x8f,0xa5,0xee,0x4d,0xfa,0x54,0x5b,0x1a,0xce,0x41,0x78,0xb8, + 0x63,0x2b,0xf9,0xac,0xfd,0xe3,0x9e,0xf0,0x01,0x1c,0xd7,0x47,0x62,0xbe,0xa2,0x85, + 0x8f,0xc2,0x3a,0xa5,0x2a,0xa5,0xfe,0x80,0xf4,0xc3,0xbe,0x70,0x59,0x4a,0x6d,0x22, + 0xb5,0x46,0x5b,0xa8,0xec,0xa0,0xa7,0x99,0xbc,0x2e,0x9e,0xb3,0x09,0x8f,0xc1,0x4f, + 0x69,0x30,0xad,0xde,0x17,0x78,0x5d,0xdf,0x4b,0x13,0x69,0xf7,0xea,0xc8,0xf4,0xd4, + 0x2f,0x92,0x65,0x83,0x9e,0xd5,0x64,0x18,0xf8,0xf3,0x89,0x16,0x1f,0x86,0x87,0x70, + 0xec,0xd1,0x10,0x39,0xd0,0xbe,0x17,0x74,0xd3,0xad,0x91,0x25,0xd0,0x06,0x31,0xd3, + 0x13,0xf2,0xbf,0x2e,0xe6,0x7d,0xb0,0x70,0x17,0xbc,0x0d,0x75,0x74,0x49,0x42,0x3e, + 0x0b,0xa7,0x20,0x4c,0x1f,0x4c,0xb4,0x55,0xc2,0x47,0x68,0x5c,0x9e,0x90,0xbf,0x10, + 0xdf,0x15,0x85,0x34,0x0c,0x42,0x2d,0xf8,0xa8,0x9c,0x56,0x47,0x8c,0x3a,0x90,0xa8, + 0x9c,0x80,0x11,0xa8,0x83,0xa5,0x54,0x7e,0x1d,0xf8,0x7d,0x54,0x6d,0x00,0xce,0xc2, + 0x4f,0x0c,0x6f,0xbc,0xa8,0x02,0xde,0xd2,0xc2,0xc6,0xd1,0xb8,0x3c,0xa0,0x9d,0x85, + 0x3a,0xc3,0x13,0x97,0x7b,0xc5,0x77,0x51,0x74,0x13,0xcf,0x42,0xb5,0x91,0x1f,0x2f, + 0x5a,0xae,0xdc,0xbf,0x3d,0xc0,0xfe,0xb4,0x13,0x9e,0xa5,0xd5,0x68,0x90,0x18,0x68, + 0xac,0x4d,0xa9,0xab,0x42,0x62,0x6d,0x54,0x8d,0x78,0xf3,0x1e,0x26,0xac,0x0d,0x19, + 0x80,0x67,0x75,0xd6,0x26,0xb2,0x5f,0xcc,0x85,0x5a,0xdc,0x0e,0x7b,0x94,0x60,0x34, + 0xcf,0x4f,0x1a,0x41,0xaa,0xd0,0xa3,0x1e,0x8d,0xf4,0xd1,0x3d,0x7a,0x90,0x19,0x11, + 0xee,0x46,0xa0,0x3b,0x7f,0x91,0x31,0x02,0xd5,0xc5,0xde,0x35,0x72,0x99,0x71,0x07, + 0x74,0x95,0xf8,0x5c,0x77,0x9f,0x30,0x46,0x48,0x1d,0x6c,0xa4,0xf2,0xa7,0x32,0x9f, + 0xf7,0xad,0x25,0xd8,0x67,0xa5,0xee,0x3a,0xdf,0xa6,0x79,0xa3,0x70,0x56,0xab,0x6b, + 0xc4,0xf7,0x70,0xa7,0xc1,0x8d,0xb8,0xfc,0x41,0x4e,0xb3,0xe8,0xcf,0x00,0xbc,0x45, + 0xea,0x22,0xbe,0xf8,0x26,0x05,0x7e,0xa5,0x2e,0x88,0x6c,0xc0,0x71,0x55,0x9e,0xd7, + 0xeb,0xae,0x67,0x6d,0xc4,0x7c,0x2d,0xd4,0xd2,0xd0,0x4d,0xaa,0xc1,0x43,0xdd,0xba, + 0xd6,0xdd,0x58,0x59,0xaa,0xb6,0x12,0xbc,0x62,0x54,0x6b,0x1e,0x4a,0x8e,0x88,0xb1, + 0xab,0xae,0x3e,0x7d,0x13,0x04,0x23,0x1e,0x7f,0xab,0x92,0xd8,0x06,0x15,0x11,0x55, + 0xdb,0xde,0xa7,0xef,0xd5,0x82,0x8d,0xd8,0xe7,0x5e,0xb1,0xbe,0x4a,0x4b,0xf0,0x69, + 0x28,0xfc,0x69,0xec,0xa4,0xec,0x21,0xac,0xd8,0x44,0x06,0x14,0x66,0xb0,0xb1,0x8b, + 0xb9,0x48,0x14,0xef,0x84,0xb7,0xa0,0x6e,0x91,0x2f,0x2e,0xcd,0x80,0x0f,0x61,0x81, + 0xa1,0x6c,0x15,0xcf,0x19,0xaf,0xc8,0x83,0x62,0x5d,0x54,0xc2,0x4e,0xfe,0xe4,0x71, + 0xe9,0x2d,0xc7,0x01,0x3e,0x67,0xf8,0xb0,0x0d,0xf0,0x2b,0x71,0xf9,0xa0,0x78,0x37, + 0x2a,0xb5,0x04,0xa4,0x70,0x06,0x7d,0xb4,0xa1,0x4c,0x19,0x41,0xb7,0xec,0xc5,0xc9, + 0x85,0x11,0xb5,0x0e,0xd0,0x38,0x68,0xdd,0x47,0xa9,0x24,0x6e,0xa8,0xa6,0x9e,0x04, + 0xa9,0x84,0xb5,0xad,0x01,0xaa,0x26,0xc8,0x60,0xf1,0x8b,0x46,0x41,0x4b,0x47,0x82, + 0x1c,0x14,0x9e,0xaa,0xd2,0xb5,0x44,0x91,0xf1,0x1d,0xf3,0x84,0xb4,0x0d,0xb0,0x07, + 0xf4,0x1e,0x37,0x5b,0x5f,0x49,0xf0,0x9a,0xb3,0x42,0xd8,0xc6,0x5e,0x5f,0x34,0x17, + 0xaa,0x52,0x9e,0x7b,0xc8,0x8b,0xb4,0xdd,0xd8,0xd6,0xe7,0x6e,0xce,0x79,0x97,0x3e, + 0x03,0xf9,0xe9,0xbc,0x66,0x92,0x12,0x73,0x5a,0xa9,0xd6,0xd3,0x57,0xe9,0xb5,0x43, + 0xbe,0x6b,0xe4,0xc7,0xf4,0xcf,0xe9,0xdc,0xc1,0x99,0x3f,0x92,0x8f,0xc3,0xe7,0x74, + 0x6a,0xfa,0xa6,0xd5,0xe5,0x07,0xc5,0xfa,0x52,0xf3,0x77,0xeb,0xe7,0xa0,0xee,0x5d, + 0xdf,0x53,0xf2,0xca,0xd4,0x30,0xd4,0xbd,0x95,0xbf,0x57,0x1e,0x82,0x2f,0xa0,0xce, + 0x2c,0x48,0xca,0xbd,0x39,0xc2,0x6f,0xb8,0x2e,0x68,0x63,0xb4,0x3e,0xed,0x7d,0x56, + 0xfe,0xd4,0x38,0x13,0x0f,0x9f,0xd9,0x38,0xf2,0x8d,0xba,0xd8,0x1f,0xe8,0xbc,0x13, + 0xbe,0x11,0xb9,0x5f,0xcc,0xd7,0x2e,0x69,0x03,0xec,0x43,0xbf,0x51,0xb9,0x90,0x1c, + 0xa1,0x4f,0xcd,0xad,0x1c,0xf4,0x74,0xb7,0x4e,0x35,0xf6,0x26,0x57,0x98,0x9e,0xab, + 0x8b,0x9e,0xb4,0xfc,0x18,0x3c,0x8a,0x6d,0xaa,0x4c,0xec,0xe1,0xbb,0xf0,0x14,0x2c, + 0xeb,0xf3,0x34,0x47,0xee,0x54,0xf7,0x41,0x99,0xe9,0xb9,0x27,0xd2,0x27,0x9e,0x61, + 0x0c,0xd7,0xd7,0x5e,0x29,0x68,0xe6,0x85,0x70,0x59,0x25,0xa5,0x4a,0xb3,0x33,0x14, + 0x59,0x89,0x57,0x2a,0xf1,0x69,0x90,0x9f,0x89,0x79,0xdf,0x55,0xf2,0x02,0x2e,0xf3, + 0x7a,0x33,0x7f,0x58,0x1e,0x33,0x86,0x61,0x5e,0x8f,0x6f,0xf8,0xeb,0x3f,0xc6,0x3e, + 0x87,0xd1,0x47,0xc9,0x1f,0xb5,0xc7,0xc4,0xba,0x18,0x52,0x70,0x5c,0xe6,0x83,0xc9, + 0xf2,0x21,0x03,0xd7,0x17,0x73,0x71,0xbb,0xe1,0x0b,0x99,0x1b,0x3b,0xc5,0xfa,0x92, + 0xb4,0x51,0x40,0xdf,0x62,0xfa,0x86,0xd1,0xa5,0x8c,0x2a,0x57,0x09,0xe3,0x88,0xb8, + 0x12,0x5b,0xce,0xdb,0xb4,0x28,0x2b,0xe1,0x11,0xf4,0xc6,0x9d,0x49,0x9c,0x82,0x63, + 0xe6,0x76,0xe6,0x06,0x87,0x60,0x3d,0xe5,0x1e,0x3b,0x6d,0xf0,0xf5,0x45,0xa5,0x95, + 0x20,0x7c,0xb8,0x7f,0x08,0xba,0x3b,0x7e,0x6e,0xb5,0xe9,0xa8,0xee,0x59,0x8f,0x6d, + 0xc4,0x7c,0xa9,0xc5,0xf9,0xdc,0x6f,0x4c,0x09,0xfb,0x87,0x22,0x71,0xd0,0x8f,0x79, + 0x42,0xad,0x87,0xa1,0xd5,0xc0,0x91,0x2e,0x20,0xbd,0x02,0x9b,0x40,0xfa,0x31,0x1f, + 0x97,0xef,0xe4,0x43,0xa3,0x74,0x04,0xb0,0x3f,0x67,0xe4,0x21,0xe5,0xe0,0xca,0xba, + 0x37,0x1f,0x7c,0xa6,0x2d,0x46,0xf8,0x77,0x25,0x4a,0x46,0xe1,0x3d,0xa8,0xef,0xf5, + 0x9c,0x92,0x47,0xcd,0x51,0xa8,0xff,0x8d,0xaf,0xab,0x6d,0x74,0xfb,0x17,0x50,0x8f, + 0xbe,0xae,0x68,0x50,0x60,0x01,0xc3,0xaf,0xcf,0x8c,0x79,0x87,0x0b,0x4e,0xb6,0xfd, + 0x6b,0xeb,0xd1,0xbf,0x99,0xf7,0x56,0xfe,0x9e,0xa2,0x5a,0xe3,0x63,0x6d,0xde,0xd1, + 0x60,0x97,0xdc,0x2c,0x59,0xf8,0x75,0xb8,0x7d,0x9d,0x51,0xfe,0xa6,0xf7,0x8c,0x31, + 0xd5,0xd8,0x68,0xec,0xe8,0xf7,0xfc,0x90,0xfc,0x2b,0x7d,0xa9,0xf9,0xeb,0xfd,0xea, + 0x19,0xaa,0xdb,0xf8,0x35,0x04,0x3b,0x42,0xe8,0xe2,0x42,0xb0,0x81,0xb6,0xe9,0xfa, + 0x31,0xec,0xaa,0xd7,0xdc,0xab,0xe8,0xa9,0xe8,0x3c,0x08,0x88,0x67,0x68,0x96,0x6c, + 0x40,0x24,0xd2,0xcd,0xbc,0x24,0x09,0xaa,0x9d,0x4a,0x80,0x4d,0xd3,0x6e,0x78,0xde, + 0x35,0x9b,0xe1,0x57,0xb3,0x98,0x77,0xa3,0x64,0x08,0x3e,0x26,0x61,0x7c,0xa3,0xf0, + 0x4f,0x87,0x70,0x9a,0xf2,0x93,0x0d,0xc1,0xfc,0x8f,0x25,0x3f,0x02,0x90,0x47,0xcb, + 0xe0,0xd7,0x1f,0xe0,0x25,0xb3,0x60,0xb8,0x61,0x54,0xfd,0x83,0x3d,0x29,0x63,0xae, + 0x7a,0x36,0x5f,0xdd,0x0e,0x7e,0xd1,0x43,0x6a,0xf8,0x70,0x7e,0x52,0xde,0x00,0x1f, + 0x2b,0x0b,0xf0,0x9f,0x17,0x05,0xb5,0x73,0x7a,0xb8,0x77,0x43,0x72,0x47,0xdc,0xc6, + 0xaf,0x39,0xda,0x46,0xd8,0x31,0xdc,0x31,0xea,0xae,0xa5,0x1b,0xf5,0xf2,0x94,0xeb, + 0x14,0xa9,0xa5,0x2f,0x99,0xe5,0x3d,0xea,0x30,0x09,0xdb,0xf8,0xb5,0x14,0xda,0x34, + 0xbd,0x3f,0xef,0x39,0xe2,0x6b,0xdf,0x71,0xa2,0x62,0x84,0x84,0x89,0xb7,0xe5,0x97, + 0xe6,0xec,0x3e,0x75,0x0f,0xe9,0x76,0xd6,0x17,0xac,0x4b,0x94,0x9d,0xc8,0xbb,0x26, + 0x67,0x7a,0xd3,0x3a,0x3a,0x6b,0x90,0xdc,0x47,0xa6,0xc3,0xde,0x44,0xde,0x40,0xe5, + 0x7d,0x44,0xd5,0x2c,0xfc,0xf2,0x26,0xda,0x70,0x38,0x55,0x0b,0x77,0x14,0x74,0x60, + 0x7f,0xd2,0xb3,0x6b,0x3c,0x5e,0x38,0x7d,0xff,0xcf,0x5e,0xf1,0xd6,0xc8,0x9b,0x6d, + 0xfc,0xda,0x4d,0xc6,0x56,0xd4,0xf7,0x15,0x74,0xc9,0xdf,0xd3,0xff,0x49,0x5d,0x80, + 0x63,0xc7,0x71,0x9d,0x83,0x05,0x6f,0x32,0xcc,0x25,0x16,0x7e,0x0d,0xc1,0xa1,0x45, + 0x5d,0x47,0xbd,0x7b,0xa5,0x5f,0xc1,0xc7,0xee,0x05,0x47,0xf2,0x9f,0xe9,0xac,0x32, + 0x0e,0x11,0x7f,0xbf,0xb7,0xcb,0x33,0xdb,0xc1,0x2f,0xd5,0x07,0x7a,0x4a,0x5d,0xd5, + 0x3a,0x95,0xae,0xab,0x28,0x33,0x1f,0x58,0x45,0xa6,0xea,0x1b,0x57,0x94,0xf5,0xab, + 0x73,0xc9,0x66,0x07,0xbf,0x4a,0xaf,0x48,0x94,0x0d,0x22,0xe6,0x3e,0x86,0x50,0xbb, + 0x6c,0x50,0xbd,0xd7,0xf8,0x0e,0xac,0xa3,0x55,0x27,0x3a,0x7e,0x44,0xac,0x70,0x2e, + 0x5a,0x3c,0x04,0xbf,0xc4,0xf9,0x2a,0x4d,0x92,0x0d,0xf8,0x42,0x26,0xd8,0x42,0x5b, + 0x49,0xda,0x60,0xb7,0x59,0x99,0xc4,0xfb,0x08,0xfc,0x2a,0xd9,0x45,0x18,0x5a,0xad, + 0x4c,0xc8,0xbb,0xd8,0xb2,0xa2,0xde,0x84,0xbc,0x42,0x3a,0xa8,0xd4,0xa1,0x51,0x54, + 0x63,0xe3,0xd7,0x09,0xa5,0x14,0xea,0x34,0x5f,0xbb,0xb4,0x4c,0x1b,0x84,0x1a,0x74, + 0xd4,0x0c,0xbf,0x0c,0xc2,0x10,0xcd,0xc1,0xaf,0x0f,0xe2,0x07,0x12,0x0b,0x1a,0xf3, + 0x7f,0x76,0x45,0x8e,0xf1,0x56,0x3c,0xdc,0xf8,0x77,0xf1,0x45,0x3f,0xa7,0x07,0x34, + 0xfd,0xbb,0x4b,0xb6,0x36,0xb4,0x5a,0xf8,0xa5,0xfc,0x35,0xdc,0x4f,0x03,0x4d,0xea, + 0xa3,0x39,0x33,0xe0,0x7e,0x23,0xd0,0x54,0x1a,0x27,0x57,0xc0,0xfd,0xe6,0x82,0x66, + 0xf5,0x51,0xb7,0xee,0xe0,0x17,0xdc,0x0f,0x15,0x46,0x5e,0x3c,0x52,0xa1,0x6e,0xca, + 0x4b,0x7c,0x53,0xf5,0xf7,0xee,0xd4,0x5b,0x60,0x76,0x43,0xe5,0xbf,0x90,0xb5,0x16, + 0x7e,0x29,0x8a,0x82,0xaf,0xe8,0xf5,0xaa,0xdf,0xaf,0xb4,0xb4,0x04,0xf4,0xa8,0xdb, + 0xff,0x57,0x4a,0xbc,0x45,0xf7,0x46,0x55,0x7f,0x84,0xd8,0xf8,0x75,0x7d,0x24,0xd5, + 0xf4,0xcc,0x96,0xfc,0x19,0xee,0x3c,0xa3,0xbf,0x29,0x54,0xec,0x76,0xc9,0x2d,0x91, + 0x83,0xb7,0x96,0x32,0x44,0xfb,0xb5,0xcc,0xbf,0x6b,0xeb,0x34,0xf4,0xfc,0xc5,0x75, + 0x8d,0x4b,0x37,0xc1,0x80,0x71,0xb6,0xb0,0xae,0xf1,0xa6,0x4d,0xf2,0x72,0xe3,0xde, + 0xe2,0x05,0x8d,0xb9,0x9b,0xe4,0x0f,0x72,0x63,0x16,0x7e,0x91,0x03,0x95,0xe1,0x1b, + 0xbc,0xf1,0xb6,0x81,0xfd,0x6f,0xdd,0xd5,0xd5,0x98,0xbf,0x45,0xae,0xa8,0x3c,0xb0, + 0x28,0xdc,0x84,0x57,0x72,0x6c,0xfc,0x32,0xa1,0x23,0xa6,0x97,0xaa,0x4a,0xa4,0x07, + 0x3a,0xf4,0x40,0x71,0x55,0x3b,0xd9,0x46,0xa8,0x9e,0x00,0x75,0xbf,0xbb,0xc0,0x7a, + 0x3e,0xae,0x37,0x13,0x6b,0xd4,0xb2,0x88,0x7a,0x4b,0xeb,0x9b,0xe6,0x3f,0x2f,0x2b, + 0x8b,0x96,0x7e,0x8b,0x4c,0x4d,0xac,0x31,0xca,0x9a,0xf2,0x9a,0xb6,0x13,0x97,0x85, + 0x5f,0x4f,0xc1,0x03,0x52,0xb9,0xa1,0xf6,0x93,0x33,0xf0,0x00,0x94,0x2d,0xba,0xb4, + 0x3f,0x8c,0x57,0xe0,0x6e,0xe3,0x89,0x26,0x92,0x63,0xe1,0x17,0x62,0xee,0x01,0x08, + 0x1b,0xc1,0x78,0x39,0x02,0xab,0x14,0x36,0x36,0xb0,0x80,0x81,0x5d,0xb9,0x29,0x1e, + 0xa8,0x14,0xeb,0xab,0x52,0xda,0x89,0x68,0xf5,0x02,0xa2,0x55,0xd1,0x00,0x61,0xb0, + 0xb5,0x54,0x2b,0xef,0xd3,0x4e,0xa2,0xf1,0x60,0xdc,0x73,0x50,0xac,0xaf,0x4a,0x2d, + 0x59,0xd8,0x07,0xd7,0xc0,0x06,0xb3,0x21,0xa4,0x1e,0x26,0xdf,0x47,0xc0,0xf9,0x7a, + 0x08,0x0e,0xc3,0x5c,0x28,0x30,0x65,0xb7,0x85,0x5f,0xae,0x59,0xb7,0xac,0xd7,0x03, + 0x5b,0x2a,0x13,0xee,0xca,0x9c,0xf5,0x52,0x80,0x6e,0x78,0x3c,0x52,0x89,0xd1,0xce, + 0xf6,0x7f,0x56,0xb7,0xcb,0x6e,0x0b,0x77,0x5c,0x3f,0x86,0x75,0xed,0xb3,0x4c,0xb5, + 0x39,0xa7,0x16,0x36,0xc2,0x32,0x74,0xf8,0xee,0xa9,0xda,0x4f,0xe9,0x0c,0xd3,0xdd, + 0x8c,0xe0,0xc7,0xd7,0x57,0x42,0x9a,0x0a,0xeb,0xd0,0xf3,0xab,0xab,0x2f,0xb1,0x0c, + 0xde,0xc6,0x98,0x81,0x06,0x59,0x21,0xee,0xb3,0x4b,0x9d,0x8e,0x91,0xc5,0xd5,0x18, + 0x43,0x16,0x4d,0x87,0x97,0x5b,0xf4,0xf4,0x4d,0x23,0xb7,0x16,0xc0,0xbf,0xd3,0x2b, + 0xd3,0x05,0x23,0xb8,0x2e,0x04,0x7e,0x4d,0x13,0x51,0xd3,0x46,0x5a,0xc4,0x02,0x86, + 0x17,0xa5,0x39,0xb4,0x1c,0x31,0x17,0x5f,0x48,0x5f,0x3b,0xbe,0x63,0x02,0x77,0x5c, + 0x5f,0x18,0xaf,0xd1,0x05,0x09,0x44,0xab,0xba,0xbe,0xcf,0x5a,0xaf,0x3a,0x91,0x3f, + 0xe8,0x9f,0xa9,0xbe,0xb6,0xa9,0x3e,0xf1,0xc0,0x7f,0x78,0xc0,0xc2,0xaf,0xc2,0x17, + 0xb5,0x75,0x1a,0x46,0x7a,0x35,0x45,0x7f,0x0f,0x1b,0x0d,0x3d,0xad,0xde,0x9b,0x33, + 0xdd,0xfc,0x03,0x9d,0x33,0xa8,0xfe,0x88,0x38,0xf8,0xb5,0x95,0xae,0x81,0x19,0x1d, + 0x0d,0xb8,0xf4,0x52,0xbf,0x80,0xb2,0x14,0x9b,0x57,0xba,0x46,0xaf,0xea,0xc8,0xbb, + 0x05,0x57,0x3b,0x7f,0x3e,0x7a,0x71,0x9a,0x50,0x7c,0x54,0x1e,0xc8,0x31,0xa0,0x03, + 0xb6,0xc3,0x9f,0x51,0xbf,0xae,0x24,0x94,0x20,0xec,0x02,0xd2,0x61,0xe3,0xd7,0x4e, + 0x38,0x88,0x61,0x06,0x46,0x4d,0x3a,0x0c,0x2a,0x61,0xf0,0xc6,0x3d,0x95,0xb0,0x1e, + 0x23,0xbd,0xfc,0x44,0xf9,0x6c,0xc5,0xb0,0xf0,0x0b,0x63,0xfe,0x17,0x4d,0xdf,0x7c, + 0x84,0xe3,0x73,0x18,0xea,0x23,0x1c,0xa3,0xe1,0x62,0xf8,0x85,0x23,0xb5,0xf0,0xeb, + 0x0c,0x39,0x02,0xf3,0x0c,0x5f,0x87,0xbc,0xaa,0xfd,0xb0,0x14,0xae,0x5c,0xd9,0x4f, + 0x16,0x32,0xfc,0x32,0xbc,0x31,0x99,0x36,0x5a,0xf8,0x15,0xc3,0xf7,0x30,0x00,0x97, + 0x3e,0x48,0xca,0xa1,0x63,0x51,0xc0,0xef,0x66,0xfd,0x39,0x76,0x7d,0x35,0xac,0x6f, + 0x6f,0xd5,0x2d,0xfc,0x72,0xe9,0x06,0x85,0xed,0x8a,0xa7,0x85,0x18,0xa4,0x83,0x06, + 0x24,0xb5,0x85,0x24,0xb0,0xbf,0x41,0x45,0xa5,0x68,0x58,0xeb,0xcb,0x8b,0xcc,0x45, + 0x4f,0x79,0xc2,0x7e,0x34,0x14,0xfd,0x35,0x77,0x98,0x3c,0xa8,0x3e,0xa4,0x06,0x4d, + 0xf7,0xfc,0x56,0x6b,0x7d,0x41,0x7e,0x0c,0x7d,0x50,0x18,0x6e,0xa4,0x2f,0xc7,0x62, + 0x29,0x34,0xbc,0xed,0x32,0xa5,0x29,0xa3,0x4e,0xf5,0xe6,0xc8,0x54,0xc4,0x87,0x89, + 0x69,0x69,0x03,0x61,0xcb,0x95,0x4f,0x31,0x56,0x1f,0x85,0x67,0xbc,0xbe,0xb5,0x9d, + 0xcd,0xc6,0xb1,0xca,0x6a,0x65,0x69,0xab,0x3c,0x28,0xe2,0x43,0x53,0xba,0x00,0xef, + 0xd1,0x6b,0x2b,0xaa,0xee,0x97,0x5a,0xe1,0xf7,0x14,0xfd,0xfc,0x48,0xf9,0x05,0x18, + 0xa3,0xf3,0xd2,0xbe,0x93,0xf2,0xb0,0x85,0x5f,0xa5,0x9f,0xc2,0xf3,0xb4,0x5a,0x55, + 0xa9,0x3b,0x00,0x9d,0xb4,0x7c,0x58,0xed,0xda,0x3e,0x94,0x78,0xbe,0x22,0xd0,0xeb, + 0xf9,0x9c,0x0c,0xe7,0x58,0xf8,0xb5,0x01,0x79,0x4a,0x35,0xa8,0xad,0x39,0x54,0xdb, + 0xa1,0x54,0xf4,0xe7,0x85,0x02,0x87,0xe9,0x5e,0x15,0x47,0x31,0x8f,0x9c,0x92,0x84, + 0xcf,0x44,0xdf,0x8b,0xd8,0x1d,0x50,0x29,0x22,0x5a,0x67,0x2c,0x80,0x6e,0x30,0x87, + 0x5d,0x09,0x30,0x10,0xb7,0x62,0x7e,0xa3,0x64,0x25,0xbc,0x03,0xc1,0x90,0x17,0xe4, + 0xed,0x65,0x1f,0x9b,0x0b,0xcc,0x07,0x18,0xbe,0x23,0xd1,0xe8,0x59,0x9a,0x6c,0xe8, + 0x6f,0x74,0xf0,0xeb,0x9f,0xa0,0x5e,0xf2,0x1d,0xc0,0x1e,0x8e,0xd1,0x6b,0x4d,0x0f, + 0xc7,0x2f,0xa8,0xef,0xf1,0x25,0xcb,0xb3,0xf9,0x17,0x46,0x95,0x0f,0x52,0x79,0x99, + 0x76,0xd0,0x60,0xf7,0x41,0x1e,0xc7,0xa2,0x14,0xc4,0x02,0x2d,0x9b,0x7f,0x61,0x9f, + 0x13,0x01,0x13,0x51,0xf9,0x2a,0x16,0xd2,0xec,0x16,0xd1,0xc5,0x30,0x59,0x20,0xe6, + 0xc2,0x54,0x38,0xff,0x02,0x37,0x90,0x08,0xb4,0x35,0xed,0x14,0xc1,0xd2,0xf3,0xb0, + 0x92,0x81,0x6f,0x48,0xf8,0x4c,0x5d,0xfb,0x0e,0x42,0xc0,0x1c,0x5d,0xbd,0x9e,0x9c, + 0x4a,0xcc,0xa1,0x8f,0x0f,0x7a,0xee,0x0d,0x20,0x28,0x24,0xaa,0xd2,0xf2,0x7d,0xa4, + 0x5a,0xd1,0x04,0x7e,0x2d,0x81,0xd3,0x78,0x9f,0x02,0x8f,0x1c,0xf1,0xbe,0x0c,0xf3, + 0x07,0xa5,0x1a,0x79,0x89,0x7a,0x9a,0xd6,0x9a,0xbe,0x85,0xb2,0x5f,0xc4,0x1b,0x46, + 0xc9,0x0b,0xae,0x31,0xb6,0xbe,0x4c,0xc6,0xbf,0xa0,0xbe,0x1f,0x71,0x79,0x88,0x19, + 0x7d,0x1b,0x4f,0xb6,0xf5,0x8b,0x75,0xa1,0xba,0xf8,0x2b,0x0a,0xc1,0x38,0xae,0xa6, + 0xd3,0x10,0x3e,0xe6,0xeb,0x6e,0x08,0x12,0x64,0x64,0x66,0xf0,0xc5,0x4e,0x62,0xf1, + 0xa6,0x4b,0x59,0xec,0x37,0x07,0x54,0x13,0xef,0xfb,0xef,0xf0,0x44,0x0a,0x87,0x83, + 0x8c,0x0c,0xa3,0x41,0xf5,0x14,0x09,0xe7,0x88,0xb5,0x83,0xfc,0x6b,0x5f,0x4b,0xd5, + 0xb6,0x8e,0xe8,0x4c,0x3f,0x3c,0x4d,0xcb,0x06,0x90,0x76,0x21,0x0a,0xb7,0x54,0x9d, + 0x50,0x57,0xe7,0xa8,0xe2,0x3e,0x2b,0x94,0xc3,0x6c,0xec,0x9a,0xaa,0xac,0x2d,0x30, + 0x1e,0x52,0x59,0x58,0x98,0xb3,0x1b,0xf9,0x17,0xf2,0xe5,0x10,0xa9,0x11,0x6d,0x10, + 0xbf,0x10,0xb6,0xea,0xe9,0xd4,0x58,0xee,0xd5,0xf0,0x79,0x6f,0x98,0xfa,0x58,0xb0, + 0x7d,0x10,0x18,0x7e,0xc9,0x35,0xc2,0x1f,0x32,0xfe,0x85,0x7e,0xc3,0x7b,0x79,0x4b, + 0x6e,0x5a,0x19,0x29,0x14,0x44,0x8c,0x7b,0x12,0x8e,0x5f,0x62,0x5c,0x9a,0x88,0xf0, + 0xbd,0xf1,0xf2,0x99,0xa1,0x03,0xda,0x73,0x68,0xc8,0xcc,0xd3,0xd6,0xa1,0x83,0x45, + 0xfe,0xa5,0x0b,0xfc,0x5a,0xae,0x72,0x6e,0x15,0x27,0x8a,0xf1,0x04,0x0d,0x18,0x1d, + 0x8c,0x5b,0xdd,0x2f,0xae,0xa4,0xc5,0x5c,0x2c,0x44,0xfc,0x7a,0x16,0x82,0x06,0x46, + 0x44,0x15,0xfa,0xfd,0x79,0xb3,0xd9,0x9f,0xec,0x36,0x81,0x23,0x96,0xcf,0x2c,0x56, + 0x30,0xd4,0x0f,0xe2,0x3f,0x77,0x57,0xc0,0x36,0xd0,0xa3,0x95,0xc8,0xbf,0xa0,0x05, + 0xaf,0xe8,0x7e,0x72,0xd0,0x65,0xe1,0x57,0x0c,0x46,0xa4,0xba,0xe2,0xe0,0x1a,0xf4, + 0x1b,0x29,0x1c,0xad,0x77,0x4d,0x51,0x0f,0x22,0x5a,0x6d,0xb1,0xb2,0x46,0xbe,0x90, + 0xc5,0xbf,0xd0,0x03,0x78,0xfa,0xf1,0xf5,0xfb,0x47,0xe0,0xb4,0xcb,0xe2,0x29,0x9b, + 0xe4,0xf7,0xc1,0xe1,0x5f,0x67,0xa1,0xd6,0xc8,0x2d,0x96,0xe7,0xc3,0x7f,0x40,0x17, + 0xa3,0x30,0x33,0xe0,0xac,0x51,0x63,0xf8,0x36,0xb7,0xe6,0x88,0xf5,0xb5,0xb0,0x34, + 0xad,0x76,0xf3,0xf7,0x10,0x51,0xb8,0x03,0x02,0xc5,0x9e,0x56,0xa2,0xd3,0x6e,0xa9, + 0xda,0xe3,0x59,0xeb,0x2e,0x20,0x62,0x4e,0x5d,0xc8,0x19,0xa1,0xfa,0x06,0xb7,0xdf, + 0x5f,0x21,0x3f,0x44,0x2b,0x8c,0x47,0xb4,0xd6,0xc6,0x8e,0x3d,0x65,0x95,0xc6,0x8d, + 0x5a,0xab,0xdf,0xc5,0xdb,0x94,0x2a,0x3b,0xd9,0xf3,0x69,0x52,0xfd,0xa4,0xc2,0xb8, + 0x9f,0xce,0x34,0x3c,0xda,0x0d,0x82,0xb1,0x7a,0xb4,0xc8,0x4c,0x31,0x5f,0x09,0xce, + 0x19,0x6b,0x9b,0x0b,0xb6,0xc8,0x0a,0x12,0xb1,0x05,0xac,0x3f,0x48,0xb2,0xa0,0x86, + 0x19,0x16,0x7e,0x45,0x39,0x7e,0xd5,0x35,0xb3,0xe1,0x84,0xac,0x3f,0xed,0xe4,0xec, + 0x18,0x0d,0x67,0xbe,0x12,0xec,0xf9,0x40,0x3e,0x2d,0x8a,0xa9,0x23,0xe8,0x7f,0xac, + 0x39,0xe5,0x06,0xb1,0xf1,0xab,0x12,0x9e,0x43,0xfe,0x15,0x4d,0x90,0x1a,0x7d,0xad, + 0x32,0xbb,0x05,0x89,0xd8,0x20,0x5e,0x09,0x30,0x46,0xb6,0xde,0xc6,0x2f,0x91,0xdf, + 0x28,0x0d,0xf9,0x6f,0xd0,0xb6,0xeb,0x8c,0x88,0x11,0xf6,0xd6,0xe9,0x68,0xdc,0xb5, + 0x5e,0xcc,0x29,0x2d,0x9c,0xaa,0xe1,0xfb,0x9c,0xaa,0x3c,0xe5,0xd7,0x10,0xe3,0xaa, + 0xcc,0x29,0xab,0xc8,0xbb,0xf1,0xab,0xe8,0x32,0xd3,0xb3,0x0a,0x7d,0xa6,0xf0,0x3f, + 0x88,0x5f,0x7f,0xa0,0xd7,0x0e,0x7a,0x7f,0x24,0xdf,0x82,0x7e,0xec,0xda,0xb4,0x07, + 0xf9,0x97,0xf1,0x4f,0xe9,0xb9,0x83,0x4b,0x6b,0xda,0x02,0x3a,0xbf,0x8f,0x5a,0xb2, + 0x9b,0xf1,0x94,0x63,0xe8,0xde,0x4d,0xf2,0x5b,0xf4,0xf3,0x4b,0x9f,0x29,0x1a,0x32, + 0xce,0xc1,0x63,0xff,0xb6,0x74,0x8f,0x1c,0xb1,0x70,0x47,0xf9,0x35,0x8c,0x6d,0xba, + 0xfc,0x54,0xde,0x73,0xeb,0x7b,0xe1,0xb3,0xd6,0x9a,0xb4,0xaf,0xbb,0xed,0x02,0x9c, + 0x8b,0xd7,0xa4,0x37,0x3e,0x2b,0x9b,0xe2,0x19,0xee,0x2a,0x7d,0xcc,0xdc,0xa7,0x55, + 0xa5,0x11,0xad,0xfc,0xb8,0xbe,0xb6,0x0d,0xde,0xb8,0x90,0x1c,0x47,0xfe,0x55,0x35, + 0xe8,0x5b,0x48,0x3e,0x12,0xeb,0x8b,0xf3,0x2f,0x69,0x8e,0x99,0x37,0x1c,0x88,0xc3, + 0xff,0x34,0x66,0xf5,0x21,0x11,0x7b,0xd4,0xd8,0xa7,0x23,0x8b,0x6c,0xce,0x31,0x75, + 0xb1,0x06,0x95,0x0d,0x22,0xb7,0x73,0xb5,0x1b,0xf4,0x87,0xf8,0x90,0xd9,0xd8,0x09, + 0x7b,0x08,0x81,0x94,0xf5,0x5d,0x25,0xcc,0x8f,0xd5,0x7f,0x90,0x3f,0x4c,0xb6,0xb5, + 0x3e,0xd9,0x57,0x83,0x37,0x94,0x5f,0x40,0x9f,0x70,0x0d,0xcb,0x35,0x7d,0x24,0xe6, + 0x8b,0xe3,0x17,0x7a,0x80,0x8d,0x49,0x79,0x1b,0x9c,0xa3,0x75,0xe6,0xe5,0x48,0xc4, + 0x78,0xf6,0x09,0x47,0x9a,0x16,0xf3,0x55,0x86,0xfc,0xeb,0x33,0x0c,0xf5,0xbd,0xc3, + 0x6d,0xcd,0xf8,0x1e,0xce,0x33,0x5f,0x1b,0x5e,0xf5,0x63,0x75,0x4c,0x99,0xc3,0x98, + 0x5d,0xaa,0x91,0x7f,0xd7,0x36,0x60,0xdc,0x2a,0x68,0x56,0x86,0xe4,0x48,0xeb,0x1b, + 0x2d,0x01,0xc1,0xad,0x1e,0x81,0x99,0x8c,0x6d,0x0d,0x5a,0x73,0x21,0x71,0x9f,0xc9, + 0x18,0xc7,0x5f,0xb9,0x1f,0xa1,0x01,0xd3,0x9d,0xcc,0x59,0xa9,0x3e,0x0f,0x7f,0xc7, + 0x58,0x5b,0xda,0xc1,0xaf,0x16,0xc4,0x02,0x33,0xba,0x27,0x10,0x33,0xf9,0xb8,0xc2, + 0x39,0x87,0xd5,0x87,0xa2,0x4a,0xca,0xb3,0x00,0x7a,0xc5,0xfa,0x82,0xfc,0x95,0x89, + 0x8f,0xa1,0x3e,0xe5,0xfd,0x5c,0x8e,0xd1,0x77,0x20,0x9c,0xca,0x3f,0x25,0x23,0x23, + 0x8b,0x5d,0x9e,0xca,0x3f,0xd3,0x60,0xda,0xf8,0xc5,0xbc,0x7a,0x6d,0xbf,0xef,0x87, + 0x53,0x86,0x4d,0xe4,0x29,0x47,0x96,0x7e,0xde,0x36,0x14,0x65,0xfe,0x10,0xc9,0xda, + 0x60,0xbb,0x85,0x5f,0xe9,0xd4,0x50,0xac,0xde,0x9b,0xbf,0x56,0xd6,0xe9,0xe1,0x50, + 0x5d,0xbe,0xb7,0x45,0x0e,0x19,0x29,0x3d,0x5c,0x8a,0x0e,0x24,0x64,0xe7,0x0f,0x4f, + 0x98,0x1d,0xa1,0xea,0x62,0x75,0x0d,0x29,0x83,0x8e,0x6f,0x56,0x17,0xbb,0xd7,0x92, + 0xb2,0x78,0xc7,0xea,0x40,0x9f,0xba,0x80,0x38,0xfc,0xeb,0x30,0xdd,0xa1,0x07,0x53, + 0x53,0xc2,0x24,0x5f,0x6f,0xd3,0x83,0x07,0x2e,0x9b,0xef,0x7f,0xa0,0xa3,0xad,0x4c, + 0x4f,0x75,0x94,0xb5,0xde,0x65,0xe5,0x0f,0x4b,0x12,0xd0,0xa1,0xfc,0x9d,0x74,0x03, + 0xf8,0xd1,0x40,0x67,0x5e,0x49,0x73,0x12,0x1a,0x2e,0x58,0x7c,0x1a,0x11,0x8b,0x7f, + 0x41,0xc9,0x09,0x18,0x64,0x3e,0x7c,0x43,0x5b,0xb9,0x91,0x22,0x75,0xe4,0xe6,0x96, + 0xa2,0x04,0xa4,0xb4,0x2e,0x0c,0x3c,0xe4,0x26,0x85,0x8f,0x2b,0x2d,0x75,0xa8,0x8c, + 0x0b,0x57,0x6d,0xf0,0x34,0x91,0x0b,0x50,0x3f,0xc3,0x77,0xc7,0x5f,0x2c,0x21,0x67, + 0x5b,0x6b,0xcd,0x39,0xcd,0x1e,0x87,0x7f,0x21,0x3d,0x61,0x68,0xf5,0x54,0x79,0x15, + 0x02,0x22,0x23,0x74,0x72,0x10,0x5e,0x46,0x03,0xfd,0xaa,0x83,0x5f,0x95,0xc8,0x07, + 0x11,0xad,0x68,0x20,0xa1,0x3c,0x07,0x35,0x92,0x1c,0x47,0x62,0x78,0xbf,0xc2,0xf9, + 0xa0,0xc3,0xbf,0x0c,0x48,0xa0,0x6f,0xf1,0xb0,0xd7,0x24,0x09,0x15,0x08,0x64,0x61, + 0x93,0x50,0xe4,0x5c,0xaa,0x86,0x01,0x8c,0xe0,0x5f,0x85,0x97,0x40,0x3b,0xad,0xaa, + 0xe8,0x64,0x5c,0x66,0x4f,0xeb,0xac,0xf4,0x8d,0xb3,0xc9,0x2d,0x8d,0x6b,0xdb,0x67, + 0x0d,0xa9,0xf7,0x91,0x52,0x27,0x7f,0x08,0xbf,0x25,0xb5,0x43,0xbe,0x1a,0x79,0x23, + 0x7d,0xa3,0x71,0xfe,0x60,0x4e,0x8d,0x7c,0xb3,0xf9,0x72,0x8b,0x36,0x14,0xac,0x44, + 0xfc,0xe2,0x43,0x37,0x30,0x7e,0xc6,0x78,0x03,0x7c,0x7b,0xc8,0x10,0x3d,0xaf,0xd5, + 0xf5,0xf9,0xd2,0x9e,0x24,0x5c,0x60,0xf3,0x75,0x56,0xee,0x17,0xf9,0x8d,0x5d,0x25, + 0x69,0x48,0x21,0x7e,0x79,0x69,0x03,0xf3,0x75,0x61,0x58,0x82,0x81,0x99,0x92,0x52, + 0xc2,0x12,0x3e,0x1f,0x9b,0x7f,0x5d,0x3a,0x15,0x59,0x92,0xde,0x53,0x39,0x2c,0xdf, + 0x09,0xbf,0x40,0x6e,0xae,0x86,0xe4,0x25,0xf0,0x06,0xcc,0x37,0xf3,0x43,0xb2,0x5f, + 0x3c,0x1f,0x91,0x3f,0x9c,0xc5,0x72,0x9e,0x37,0x4b,0x0f,0xb5,0x73,0x03,0xf1,0x8b, + 0xce,0x48,0xe7,0xad,0x40,0x5c,0x16,0x3e,0x53,0x79,0x17,0x7e,0x0a,0xcb,0x06,0x30, + 0xca,0xbd,0x93,0xa5,0x43,0x4d,0xf5,0x07,0xe4,0xce,0xca,0x9f,0xc6,0x66,0xb0,0xac, + 0x88,0xdf,0xe6,0x5f,0x1f,0xc1,0x9f,0x0f,0xd7,0x6c,0xf1,0x26,0xae,0xa8,0x54,0xdf, + 0xd6,0x6b,0x10,0xb6,0x72,0x2b,0x2b,0x0e,0x36,0x2e,0xa0,0xf9,0x09,0x8f,0xc3,0xbf, + 0x92,0xc6,0x10,0x1b,0x97,0x99,0x1b,0x87,0x01,0x98,0x01,0x4b,0x8d,0xdc,0x7e,0x6d, + 0x54,0xb9,0x16,0x7c,0x86,0xbc,0xd9,0xe6,0x5f,0x7d,0x6a,0x0f,0xcc,0x5f,0xe4,0xd5, + 0xe4,0x0a,0xe5,0x80,0x12,0x36,0xf2,0xe3,0x0f,0x2d,0x87,0x1e,0xe4,0x05,0x4b,0xe2, + 0xe8,0x0f,0x2d,0xfe,0xb5,0x1c,0xee,0x57,0x02,0x46,0x34,0x7e,0x17,0x23,0x59,0x01, + 0xe3,0x86,0x38,0xa9,0x50,0x9e,0x90,0x66,0x2f,0x52,0xe3,0xf8,0x46,0x59,0xfc,0xab, + 0x16,0x19,0xc7,0x1c,0xc6,0x41,0xe6,0x93,0x5f,0xc1,0x0e,0x23,0xaf,0xdf,0x3d,0x1f, + 0x59,0xc9,0x0e,0xa3,0xb4,0x9f,0xe4,0xd8,0xeb,0xab,0xb8,0x75,0x8d,0xfe,0xc4,0xf5, + 0x95,0xb7,0xcc,0x2e,0xa6,0x8f,0xeb,0x65,0x51,0xf7,0x2d,0xee,0xe2,0xf6,0xc7,0xf5, + 0x59,0xd1,0xca,0x5b,0xdc,0xad,0x99,0xfc,0x61,0xaa,0xa9,0x0e,0xd9,0x56,0x79,0x99, + 0x31,0xd8,0x14,0x2e,0xce,0x5f,0xd3,0x50,0x86,0x57,0xc2,0xc5,0x4b,0x5e,0x91,0xab, + 0x25,0x81,0x5f,0xd3,0x90,0x76,0x69,0x97,0x34,0x22,0x5a,0x0d,0x19,0xef,0x20,0xff, + 0xca,0xdf,0xd4,0x30,0x10,0x65,0xf9,0xc3,0x8d,0xc8,0xbf,0x2e,0xb1,0xf1,0xcb,0xf8, + 0x10,0xa1,0xcd,0xbb,0xb9,0xed,0x77,0xfa,0x01,0x35,0xbc,0xf8,0xe6,0xb8,0x67,0xa7, + 0x71,0x20,0xba,0xaa,0x69,0xc9,0x26,0x79,0xa6,0xcd,0xbf,0x3e,0x34,0x3a,0x9a,0xaa, + 0xb7,0xe4,0xaf,0x25,0x88,0xef,0x80,0x8f,0x6e,0x9d,0x7f,0x56,0xe3,0xdb,0xfa,0x6c, + 0x4d,0xa5,0xfe,0x02,0x27,0x7f,0x48,0xb7,0xa9,0xc1,0xa8,0xaa,0x6d,0xee,0x93,0xb6, + 0xa9,0x7a,0xf4,0x46,0x6d,0x73,0x7b,0x7b,0x0b,0xc4,0x9a,0xd4,0x4b,0x48,0xab,0x93, + 0x3f,0xec,0xb8,0x3f,0x16,0x8c,0x3e,0xbc,0x39,0x32,0x80,0xb0,0x35,0xf3,0xfa,0xbc, + 0x2d,0xa4,0x02,0x1e,0x96,0x66,0x37,0xa9,0x5b,0xc8,0x5a,0x3b,0x7f,0xf8,0x38,0x60, + 0x7f,0x9a,0xbc,0x9b,0x8b,0x3e,0xd0,0x3e,0x84,0x70,0xd3,0xf4,0xad,0xf2,0x2f,0xe0, + 0x80,0x41,0x62,0x4b,0xb6,0x7a,0x76,0xd9,0xf9,0xc3,0x76,0xaf,0xc8,0x16,0x16,0x0d, + 0xd0,0xb3,0xdb,0x5f,0x88,0x15,0xf8,0x8b,0xfa,0xe8,0xd9,0xc6,0xda,0xe8,0x1c,0xbf, + 0x7c,0x83,0x9d,0x3f,0xdc,0x46,0x8e,0x19,0x5d,0x5a,0xb0,0xfd,0x6b,0x94,0x98,0x39, + 0x61,0xad,0x9a,0xca,0x65,0x24,0x65,0x74,0xb1,0x44,0xa2,0xdb,0xc9,0x1f,0x22,0x53, + 0x08,0xd0,0x1b,0x90,0x7f,0xe1,0xba,0x61,0xf9,0x43,0x46,0xc4,0x90,0xa4,0x57,0x26, + 0x22,0x6e,0xe1,0xc6,0x18,0x7e,0x31,0x17,0x87,0x61,0xa1,0x97,0x1b,0x51,0x66,0x74, + 0x42,0xa5,0xe9,0x0e,0xe9,0x6e,0x3b,0xbf,0x31,0xd5,0x58,0x47,0xcb,0xfa,0x3c,0xf7, + 0x92,0xa9,0xc6,0x43,0xe1,0x32,0x33,0xda,0x4c,0xa6,0xd2,0x75,0xd2,0xac,0x94,0x7a, + 0x0f,0xe9,0xb0,0xf3,0x87,0x05,0xe6,0x7b,0xc3,0xa1,0xc1,0xfc,0x85,0xee,0x3a,0xfa, + 0xef,0xc9,0x64,0x1a,0xe3,0xf0,0x82,0xc4,0xcb,0xe9,0x6b,0x86,0x0a,0x46,0xda,0xdc, + 0x56,0xfe,0x70,0xda,0xaf,0xd0,0xcf,0x57,0xf7,0x3f,0xf8,0x54,0xf9,0x4a,0xfd,0x63, + 0xa3,0xee,0xb0,0xef,0x19,0xf9,0x93,0xfe,0x73,0xb0,0xe0,0x5d,0x8c,0x7b,0x23,0x22, + 0xbf,0x61,0xb8,0x2e,0xc0,0x51,0x7a,0xcd,0xb0,0xf7,0xbc,0xfc,0x13,0xe3,0x28,0xdd, + 0x31,0xa2,0xbc,0xb8,0xa3,0xce,0x38,0xd4,0x7f,0x15,0xcb,0x28,0x6a,0x36,0xff,0x7a, + 0x41,0x5b,0xa7,0xe8,0x66,0xfe,0x6a,0xf9,0x3b,0x4d,0xc8,0xad,0x3e,0x89,0xde,0x4b, + 0xbc,0xe6,0xba,0x9d,0x48,0x0c,0xef,0x25,0xb3,0x33,0xf9,0x43,0x5e,0x3d,0x59,0x15, + 0x99,0xda,0xb2,0x4e,0x9b,0x61,0x5e,0x7f,0x0f,0x79,0xb4,0xe0,0xa7,0xfa,0x77,0xfb, + 0xdc,0xcd,0x9a,0x62,0xe7,0x0f,0x5f,0xc3,0x90,0x58,0x1f,0xce,0x9b,0x4b,0x96,0x34, + 0xfe,0x52,0xab,0x38,0x35,0x65,0x61,0xc1,0xee,0xf8,0x43,0x6e,0xbd,0x77,0x76,0xa8, + 0xf5,0x32,0x9b,0x7f,0xfd,0x2b,0x3d,0x0a,0xcf,0xef,0xf7,0x0e,0x97,0xd7,0xc2,0x51, + 0x5c,0xcb,0x55,0x67,0xe4,0x97,0xe8,0x7b,0xd2,0x55,0xc3,0x05,0xa3,0xee,0x4a,0xf1, + 0x5d,0x88,0x5f,0xeb,0x39,0x7e,0x85,0xda,0x86,0x2a,0xce,0xa9,0x0b,0xfb,0x3a,0xf6, + 0xca,0x2b,0xb5,0x8f,0x8b,0x6b,0xfa,0x5c,0x7b,0x1a,0xac,0xb8,0x4e,0xd2,0xde,0x85, + 0xf7,0xd4,0xb9,0x18,0xc6,0x97,0xaf,0x84,0xa5,0x2c,0xaf,0xd5,0xfc,0xfd,0x5a,0xf5, + 0x55,0x98,0x6b,0x7a,0x43,0xb2,0x6e,0xf3,0x2f,0x56,0xa9,0x61,0x90,0x44,0x76,0x43, + 0x27,0xd9,0xce,0x0d,0xc2,0x12,0x65,0xeb,0x93,0x72,0x22,0x66,0xf1,0xaf,0x95,0x38, + 0x4d,0x01,0x73,0x56,0xd2,0xef,0x85,0x5f,0x72,0xd7,0x1d,0x08,0xaa,0x9d,0xc0,0x7d, + 0xa6,0x6e,0xe5,0x0f,0x21,0xd8,0xd8,0x06,0x09,0xf3,0x86,0xf9,0x64,0x43,0xeb,0x0e, + 0x88,0xa5,0x2e,0x9b,0x0b,0x1b,0xa4,0x36,0x18,0x34,0xdd,0xf3,0x9c,0xfc,0xa1,0xfa, + 0x63,0x78,0x4f,0x9a,0xf7,0x4a,0xfe,0x19,0xb9,0x56,0xff,0x3d,0x94,0xbf,0x7b,0xd3, + 0x2a,0x79,0xaa,0xf1,0xea,0xdd,0x57,0xff,0x2f,0xef,0x70,0x83,0x6e,0xe5,0x0f,0xa7, + 0x8d,0xd2,0x31,0xb8,0x2a,0xe5,0xdb,0x2b,0x0f,0xe9,0xef,0x01,0xfa,0xc3,0xd3,0x32, + 0x5e,0x59,0x71,0x85,0xb9,0xf1,0xb4,0xbc,0xcb,0xce,0x1f,0x62,0xbc,0x41,0xeb,0xd3, + 0xd3,0xbb,0xe5,0xf7,0x8d,0x23,0x10,0x8a,0x79,0xbb,0x65,0x16,0x6f,0x84,0xd3,0xde, + 0x6e,0xa7,0xfe,0x25,0xf8,0x57,0xba,0xb3,0xdb,0x9f,0x56,0xdf,0xa2,0x81,0x88,0xda, + 0x4d,0xf0,0x8a,0xbe,0xa0,0x57,0xed,0x8e,0x0c,0x5b,0xf1,0x8f,0x88,0xd5,0xcd,0xcb, + 0x42,0x24,0xcd,0xc8,0x63,0x14,0x43,0xf4,0xc3,0xae,0x3d,0x44,0x4f,0xa1,0x71,0xca, + 0x65,0x7d,0x97,0x60,0x37,0x53,0x92,0xe4,0x7d,0x78,0x84,0xea,0x4d,0x08,0x5b,0x43, + 0xda,0xb3,0x5a,0x85,0x19,0x75,0xea,0x5f,0x2c,0x7f,0x78,0x4e,0x64,0xa4,0x5f,0x86, + 0x43,0x2d,0xe1,0xc6,0x20,0xe3,0xc2,0x67,0x61,0x15,0xab,0x64,0x65,0xd7,0xbf,0x18, + 0xdb,0x1a,0x6e,0x1b,0x66,0x01,0x70,0x8c,0xe7,0x0f,0xcf,0x03,0xab,0x88,0xc9,0xe3, + 0xf9,0x97,0x99,0x9f,0xbc,0x75,0x19,0x4b,0xc1,0x35,0x09,0x4e,0xcd,0xf9,0x57,0xc3, + 0x9b,0x59,0xfc,0x8b,0x54,0x0f,0xba,0x5f,0xf8,0x73,0x1d,0xf6,0x1a,0x01,0x16,0xb4, + 0x0f,0x59,0xd9,0x5d,0xbb,0xfe,0x65,0xf1,0xaf,0x5e,0xf5,0x6a,0x62,0x40,0x17,0xbe, + 0x77,0x3c,0x3f,0xff,0x2c,0xcf,0xd8,0x93,0x2f,0xac,0xf5,0xc5,0xf9,0x57,0xd5,0xa0, + 0xfb,0x3e,0x8c,0xc7,0xf6,0x99,0x3b,0x74,0x84,0xad,0xe3,0x2d,0x4f,0xb7,0x54,0xb1, + 0x5a,0xd2,0x90,0x9d,0x3f,0xbc,0x19,0x58,0xfd,0xcb,0x7b,0x8d,0xdc,0x80,0xc6,0x7c, + 0xbd,0xa0,0x46,0x3e,0x42,0x4f,0xc6,0x6b,0x07,0x7d,0xd7,0x60,0x4c,0x6b,0xe1,0x17, + 0xab,0x7f,0x5d,0x6b,0x16,0x84,0xe4,0x34,0x1a,0x2f,0x2a,0x48,0x81,0xc5,0xb8,0x70, + 0x80,0xe3,0xf8,0x17,0x67,0x91,0xef,0xc3,0x21,0x98,0x4f,0xf9,0xb8,0xce,0x92,0x3a, + 0x56,0xe0,0xb3,0xeb,0x5f,0x97,0x8a,0xdc,0xbb,0xa7,0xf9,0xae,0x7e,0x8c,0x0f,0xcb, + 0xa8,0x9b,0x25,0xe1,0x9f,0xce,0x99,0x63,0xaa,0xcd,0xb7,0x9c,0x12,0xf7,0xe1,0xfc, + 0x8b,0x56,0xa5,0xdd,0xab,0xc9,0xe7,0xda,0x3a,0x7a,0x45,0x02,0x8d,0xe3,0xf0,0xb4, + 0xc9,0xab,0x78,0xe9,0x71,0xfc,0x8b,0x8d,0x34,0xc5,0x7c,0x4b,0xe2,0x67,0x6c,0xec, + 0x7b,0x04,0xff,0x7a,0xdd,0xc9,0x1f,0xb2,0x0a,0x02,0x2d,0x48,0xe4,0x9e,0xa5,0x47, + 0xe0,0xaa,0x6d,0x05,0x09,0x79,0x10,0xbe,0xa0,0x75,0x34,0x98,0xa9,0x7f,0x49,0x36, + 0xdb,0xca,0x45,0x83,0xd6,0x28,0xb9,0xe3,0xf8,0x97,0x85,0x5f,0xbc,0x2e,0x63,0x14, + 0x3c,0x2c,0xef,0x5c,0x78,0x16,0x61,0xab,0x20,0x7e,0x37,0x63,0x2e,0x0b,0x18,0x11, + 0xeb,0xcd,0xe0,0x17,0xb2,0x89,0x66,0x4f,0x31,0xba,0xe5,0x3d,0x24,0xc1,0xb9,0x95, + 0xf2,0x2c,0x99,0xcc,0xbf,0xaa,0x17,0x7b,0x10,0xda,0xd0,0xb8,0xcb,0x70,0xf3,0xfa, + 0x17,0xcc,0x64,0x6d,0xf6,0x8f,0xe7,0x5f,0x1e,0xcd,0x8d,0x86,0x1e,0x60,0xc5,0xb2, + 0x3e,0x7e,0x45,0x65,0xb5,0x24,0x0b,0xbf,0x62,0xa2,0x87,0x09,0xb9,0xcc,0x40,0x5a, + 0x51,0xfc,0x20,0xef,0xf3,0x2d,0x0b,0x8a,0x83,0xe3,0xeb,0x5f,0xd8,0xe7,0xcb,0xe3, + 0xf2,0x9b,0xf0,0xbf,0xb5,0x7a,0x63,0x23,0x12,0x16,0xf5,0xbc,0xa8,0x13,0x65,0xd5, + 0xbf,0x18,0x47,0xf3,0xf5,0x37,0xcc,0x80,0xdf,0x55,0x86,0x9b,0xf2,0x39,0x47,0x33, + 0xc2,0x4d,0x2b,0xe3,0xf2,0x7e,0xb0,0xf9,0x97,0xc2,0xf8,0x97,0x87,0xa2,0x9f,0x5d, + 0x6f,0xcc,0x06,0x95,0xb2,0xfa,0x97,0x1e,0x40,0xa3,0xc8,0xaa,0x7f,0x45,0xa1,0xdd, + 0xee,0x73,0x23,0xdd,0x83,0x20,0x9e,0xc7,0xfa,0xbc,0xad,0x0c,0x17,0x9a,0x46,0x5e, + 0xb7,0xf0,0x4b,0xd9,0xc9,0xc6,0xbe,0x08,0xdf,0xde,0xef,0xc2,0xc3,0xda,0x6c,0xa3, + 0x34,0x6e,0xe0,0xd8,0x5b,0x75,0x1c,0xbb,0x53,0xff,0xb2,0xfa,0x9c,0x1b,0x97,0xbf, + 0x0b,0x27,0x0d,0x16,0x27,0x60,0x7f,0x3e,0xc4,0x07,0xe5,0x65,0xf5,0xaf,0x6c,0xfe, + 0xc5,0x46,0xf1,0x0b,0xf8,0x90,0x72,0x83,0xfd,0xab,0x0b,0x8b,0x7c,0xf1,0x86,0x9f, + 0x65,0xf1,0x2f,0xe0,0xd5,0xae,0x18,0x86,0x97,0x0b,0x90,0x88,0x59,0x73,0x1a,0xcc, + 0xd4,0xbf,0x38,0xff,0x9a,0x93,0x74,0xc7,0x90,0x92,0x3f,0x08,0x3a,0x23,0x62,0x83, + 0x9c,0x91,0xa9,0xac,0xfe,0x25,0xe6,0x42,0xf0,0x2f,0xd5,0x3d,0x9b,0xac,0x04,0x9a, + 0xaa,0x10,0xf5,0xe5,0xe7,0x79,0xc5,0xd9,0xae,0x7f,0x21,0xff,0x82,0xab,0xa0,0x2a, + 0xe4,0x36,0x36,0x4f,0x35,0xd7,0x80,0xc4,0xd2,0x86,0xef,0xb2,0x37,0xbc,0xaf,0xa3, + 0x19,0x6f,0xc8,0xef,0xd3,0xa1,0x3e,0xc6,0xf8,0x57,0xa2,0x20,0x2a,0x7f,0x87,0xf6, + 0xd1,0xab,0x86,0xbd,0xab,0xe5,0xe3,0xf0,0x87,0x74,0xfd,0xc0,0x86,0xd5,0xf2,0x47, + 0x16,0x7e,0x95,0xec,0xd6,0xce,0xb1,0x3a,0x2c,0xc8,0x9f,0x28,0x38,0xc0,0x63,0xd5, + 0xb8,0x76,0xf0,0x4a,0x5d,0x3f,0xae,0xa6,0x5e,0x81,0x5f,0xa0,0xbc,0x88,0xfe,0xf0, + 0x5a,0xdd,0x1b,0x95,0x5f,0x32,0x2e,0xd0,0x3d,0x67,0x5c,0xdd,0xe5,0x17,0xd0,0xfb, + 0xd5,0x23,0x45,0x2e,0x32,0x35,0x81,0x5f,0xa5,0xc8,0xa4,0x30,0xfc,0xce,0xbf,0xc1, + 0x3f,0x1d,0x3e,0xd7,0xaf,0x1c,0x54,0xef,0x93,0x37,0xc0,0xbe,0x78,0x95,0x99,0x7f, + 0x2f,0xf9,0x48,0x3c,0x1f,0xab,0xfe,0x65,0xa8,0x8b,0xc8,0xa3,0xf0,0x0c,0x29,0x4f, + 0xe5,0xad,0x12,0x7d,0x66,0x9d,0x37,0xc5,0xf3,0xb1,0xf8,0x17,0xe4,0x01,0xf1,0xd1, + 0xed,0xfd,0x15,0x0c,0xc4,0xf1,0x8a,0x8b,0x57,0xc4,0x52,0x36,0x7e,0x31,0x3f,0x56, + 0x0b,0x5e,0x90,0x5f,0xd0,0xbb,0xcd,0xbd,0xe8,0xd0,0xca,0x59,0x4e,0xe6,0x9f,0xf8, + 0x7a,0x77,0xf0,0x8b,0xf9,0x04,0xed,0x28,0xfd,0xfa,0x6e,0x60,0xf5,0x2f,0xe1,0xeb, + 0x24,0x46,0xc4,0x64,0x2b,0x7f,0x58,0x26,0xea,0x5f,0xe0,0xed,0x41,0x9a,0x73,0x78, + 0xeb,0x3c,0x24,0x62,0x3c,0x67,0x35,0x0f,0x7d,0x4b,0x83,0x29,0xf0,0x4b,0xf0,0xaf, + 0xea,0x79,0xee,0x76,0xcf,0x12,0x25,0x81,0x00,0x94,0xcf,0xfc,0xe1,0x5e,0x91,0x1f, + 0xb3,0xd6,0x17,0x15,0x39,0x2b,0x1d,0x5f,0xd1,0x95,0xca,0x56,0x95,0xf3,0xaf,0x21, + 0xf8,0x25,0xc7,0xb8,0x9c,0x0c,0xff,0x52,0x70,0x5c,0x8a,0xbb,0x18,0xe7,0x34,0xa1, + 0x6c,0x7f,0x79,0x4a,0x38,0x8c,0x73,0x7a,0x7d,0xc2,0xf4,0xcc,0xdd,0xdc,0x6b,0xe7, + 0x0f,0xd9,0x77,0xd5,0x69,0xde,0xb5,0xf2,0x3f,0x9a,0xc7,0xa4,0x79,0xef,0x16,0xec, + 0x91,0x3f,0x81,0x8f,0x8d,0x42,0x56,0x2b,0x31,0x25,0x9b,0x7f,0x25,0xb0,0xcf,0xaa, + 0x6f,0x6d,0xd1,0x50,0xe3,0x19,0xa8,0x4b,0xe5,0x7f,0xde,0xc0,0xaf,0x98,0x4b,0x87, + 0xe5,0x4c,0xfd,0x8b,0xe3,0x97,0xef,0x59,0xf9,0x20,0x0c,0xd1,0x9a,0x3e,0xef,0x88, + 0x3c,0xda,0x3e,0x16,0xb8,0xb2,0x02,0x0d,0x47,0xbf,0x21,0xf0,0xeb,0xc6,0x2e,0xed, + 0x23,0x38,0x46,0xb7,0xbd,0xab,0x76,0xb5,0x8e,0xc6,0x5e,0x8a,0xe3,0x42,0x4b,0xb6, + 0x66,0xf4,0x1b,0xc2,0xd7,0x85,0xf5,0xc1,0x4b,0x76,0x41,0x65,0x8f,0x1a,0x0a,0x6c, + 0xa0,0x7b,0x61,0xb9,0xda,0x11,0xce,0xb1,0xf5,0x1b,0x25,0xac,0xda,0xc5,0xd0,0x21, + 0x32,0xa8,0x6e,0xd5,0x03,0xe6,0x8a,0x24,0x0c,0x15,0x5e,0x03,0x95,0xd7,0x67,0xe9, + 0x37,0x4a,0x9c,0x2c,0xdf,0x21,0x33,0xad,0xd6,0xb0,0x69,0xda,0xad,0x9e,0x23,0x0b, + 0x12,0xde,0x89,0xf8,0x25,0xd0,0x6a,0x94,0xda,0xf5,0x2f,0x0c,0x4e,0xe6,0x4c,0xc2, + 0xaf,0xa5,0xc9,0xa2,0x0f,0x03,0xa9,0x45,0x4c,0xc8,0xc1,0x38,0x35,0x59,0xc0,0x1c, + 0xfe,0x38,0xfd,0x46,0xb5,0x79,0x63,0x32,0x30,0x88,0x5c,0xe6,0xef,0x7b,0xb0,0x1b, + 0xa3,0xea,0x3e,0x3d,0xd0,0x93,0x9f,0x94,0xbb,0xc6,0xe9,0x37,0x7a,0x3a,0xd9,0x1b, + 0x45,0x85,0xeb,0xc6,0x91,0xa6,0x39,0x90,0x65,0xf4,0x1b,0x1c,0x0b,0x30,0x3e,0xbc, + 0xd0,0x84,0x44,0x8c,0x15,0x95,0x8e,0xc3,0xde,0x96,0xf2,0x0a,0x69,0xb5,0xb6,0xd5, + 0xe6,0x5f,0x5e,0x86,0x5f,0x26,0xf2,0xaf,0x83,0x09,0x80,0x60,0x1a,0x81,0xec,0xb0, + 0x7a,0x3a,0x19,0x82,0x82,0x6c,0xfd,0x06,0x8e,0x02,0xc7,0x7e,0x52,0x1e,0xa1,0xa3, + 0xc0,0x6b,0xac,0x9f,0xe8,0x63,0xe4,0x79,0x03,0xaf,0xd8,0xfc,0xcb,0x35,0x54,0xca, + 0x9f,0x4f,0xb7,0x5c,0x09,0x27,0xa0,0xeb,0x30,0x3e,0xa8,0x4f,0xe0,0x5c,0xf4,0x27, + 0x65,0x18,0x78,0x64,0xea,0x5f,0x16,0x7e,0x45,0x4a,0xb5,0x76,0x28,0xeb,0xf5,0xe0, + 0x7a,0xa7,0xfb,0xf4,0xbf,0x37,0xd4,0x61,0xe4,0x4d,0xfc,0x3e,0xa6,0x85,0x5f,0x88, + 0xb0,0x61,0x78,0xa1,0xbd,0xec,0x43,0x46,0x1e,0x29,0xae,0xc1,0xb9,0x95,0xab,0x1d, + 0xfe,0x55,0xec,0xe0,0x57,0x5e,0xac,0x95,0xb2,0xfc,0xc6,0x62,0x7e,0xa5,0x19,0x1f, + 0x82,0xc3,0xbf,0x06,0x39,0x7e,0xf9,0x12,0xb9,0xa5,0x70,0xc1,0x64,0xf9,0x43,0x59, + 0x64,0x14,0x97,0x24,0xca,0x1d,0xfe,0x95,0x50,0x58,0xae,0x69,0x29,0x95,0x4f,0x68, + 0x23,0xa1,0x1f,0xc3,0x4d,0xb4,0x88,0x11,0x8d,0x3a,0x75,0x29,0xcd,0x1d,0xa7,0xdf, + 0xe0,0x7e,0xf5,0x03,0xe3,0x00,0xc2,0xd6,0x91,0x78,0xa4,0x0f,0x79,0x41,0x98,0x39, + 0xcf,0xf1,0xf8,0x65,0xe4,0xc5,0xc9,0x07,0xb4,0x05,0xf9,0x57,0x20,0x1e,0x58,0xae, + 0xb4,0x98,0x81,0x45,0x1e,0x07,0xbf,0x4a,0x05,0x7e,0x09,0xd9,0xc6,0xfd,0x1c,0xb6, + 0xfc,0x03,0x9c,0xac,0x79,0x1c,0xfc,0x52,0x15,0x81,0x05,0x08,0x01,0x03,0x24,0x8f, + 0xe8,0x51,0xb7,0x46,0x1a,0x1f,0x6a,0xab,0xd0,0x0d,0x4f,0x06,0xbf,0xbc,0x16,0xc2, + 0xba,0xd0,0x03,0x44,0x61,0x41,0x71,0xc1,0x1a,0xf9,0x44,0x53,0x0a,0xba,0x8a,0x7d, + 0x6b,0x1c,0xfc,0x9a,0x66,0xfb,0xf9,0xc2,0x37,0xe1,0xbc,0x82,0xfc,0x0b,0xfd,0x3c, + 0x32,0x32,0x44,0xab,0x78,0x79,0xb6,0x7e,0x43,0x70,0x99,0x1f,0x28,0x3d,0x24,0xdc, + 0x58,0x80,0xa4,0xc6,0x38,0x9f,0x17,0x32,0x36,0x60,0x1b,0x47,0xbf,0xa1,0x75,0x2b, + 0xd5,0x92,0xa7,0x95,0xa4,0x55,0x96,0x3f,0xac,0x84,0x48,0xcf,0x6d,0xdd,0x46,0x40, + 0xca,0x6f,0x85,0x8c,0x7e,0xc3,0xc2,0xaf,0xd6,0x3e,0xf2,0x04,0xc6,0x87,0x51,0x34, + 0xe8,0x1e,0x08,0xdc,0x80,0x46,0xb6,0x7e,0xc3,0x1a,0x3b,0x7d,0xa2,0x69,0xbb,0x01, + 0x02,0xbb,0x03,0xac,0x1a,0x98,0xd1,0x6f,0x28,0x6f,0x91,0x3a,0x63,0x69,0xfc,0xd6, + 0xef,0x6e,0x3d,0x21,0x85,0x8d,0x9c,0xf8,0xad,0x03,0xca,0x59,0xe2,0xbf,0xc5,0x1b, + 0x2f,0xca,0xe8,0x37,0xf0,0x5f,0xb1,0x3e,0x13,0xd6,0xf9,0x5a,0x36,0x9c,0x01,0xed, + 0x24,0xfc,0x7a,0xd1,0xe5,0xf1,0xdc,0x2c,0xfd,0x86,0x15,0x81,0x24,0xd4,0x54,0x4e, + 0x98,0xe1,0x97,0x8e,0x2b,0xca,0xd2,0x6f,0xf0,0x67,0xc8,0xf8,0x17,0xa2,0x15,0x4b, + 0x1b,0x4e,0x31,0x9f,0x14,0x69,0x43,0x04,0xb2,0x74,0x10,0xf1,0xcb,0x9f,0xd1,0x6f, + 0xd8,0xef,0x98,0xa4,0xc9,0x36,0x11,0x6b,0x29,0xe3,0x8a,0x29,0x47,0xbf,0x31,0x55, + 0xbc,0xcf,0xab,0x49,0x29,0xbc,0x04,0x33,0xfa,0xe4,0xfb,0x10,0x38,0xda,0xc9,0x9c, + 0xbe,0xca,0x55,0x19,0xfd,0x06,0xcf,0x1f,0xa6,0x7d,0x23,0x6d,0x9b,0xe1,0x55,0x3a, + 0x77,0xc8,0x75,0x5f,0xdb,0x74,0x63,0x3f,0x9d,0x96,0xf6,0xde,0x2b,0xdb,0xfa,0x8d, + 0x69,0xc2,0x27,0xf8,0x9e,0x92,0x4d,0xf5,0x63,0x78,0x0e,0x61,0xcb,0xf3,0x49,0x74, + 0x44,0xa9,0xeb,0xf7,0xec,0xcd,0xe8,0x37,0x3e,0xb5,0xfc,0x61,0xdb,0x7e,0xe3,0x3d, + 0x5a,0x33,0xb0,0xf1,0xd9,0x1d,0x75,0x8d,0xa9,0xd6,0xf0,0x30,0xae,0x2f,0x87,0x7f, + 0x3d,0xc6,0xfa,0x83,0xd1,0xa9,0xff,0x75,0x58,0xa7,0xcf,0x4a,0x7b,0x9e,0x0b,0x3c, + 0xa6,0xd1,0xe4,0xac,0xc1,0xfc,0x1a,0xb7,0xcd,0xbf,0x0c,0xbe,0x06,0x53,0xb8,0xf4, + 0xfa,0xe9,0xff,0x50,0x66,0x31,0x63,0x89,0xb1,0x65,0xee,0x15,0xa9,0x4b,0x57,0x91, + 0xf6,0x2c,0xfd,0x86,0x18,0x7b,0x0f,0xec,0xe0,0xf9,0x79,0xc4,0x8b,0x38,0xd9,0xdd, + 0x8f,0x0f,0x61,0x6b,0x36,0x7e,0xd5,0x31,0x57,0x60,0xde,0xf5,0x4e,0xfa,0x1a,0x66, + 0xfc,0x98,0x1c,0xc3,0x30,0x79,0xc9,0xb0,0xfc,0xeb,0x71,0xf8,0x85,0x3e,0xb3,0xfc, + 0x84,0xfa,0x08,0xbc,0x88,0x4e,0x4f,0xde,0x0d,0x83,0x50,0x83,0xf8,0x25,0x2d,0x9b, + 0xa4,0xdf,0x18,0x86,0xf7,0xd0,0xb7,0x5c,0x3e,0x0c,0xa3,0x70,0x18,0xe6,0xf5,0x22, + 0x90,0xa5,0x33,0xfc,0xcb,0x8a,0xde,0xdf,0xd7,0xdf,0x80,0x05,0xe6,0x23,0x88,0x5f, + 0xe8,0xf4,0x76,0x99,0x1d,0x88,0x5f,0xb1,0x09,0xfa,0x0d,0xc6,0x41,0x24,0x4b,0xbf, + 0xb1,0x2b,0xc6,0x88,0x98,0xdf,0xd6,0x6f,0x20,0xda,0xce,0x63,0xfa,0x8d,0x05,0xc4, + 0x8c,0x3c,0x02,0x15,0x08,0x0a,0xfe,0xc3,0x89,0x04,0xcc,0xee,0xc5,0xbe,0x38,0xfc, + 0x8b,0xfb,0xf9,0x94,0xef,0x94,0x9c,0x6e,0x7d,0x07,0xae,0x3a,0xe6,0x19,0x2e,0x1a, + 0x6d,0x1d,0x5c,0x3d,0x2f,0xe5,0xfd,0x07,0x39,0x6d,0xf1,0xaf,0x4b,0xcf,0x33,0x7f, + 0xd8,0xef,0xfb,0xbc,0x68,0xb8,0xef,0x1f,0xa0,0xfe,0x88,0xe7,0xf3,0x97,0x87,0x94, + 0x37,0x03,0xd7,0x9a,0x7f,0xff,0xb9,0x3c,0xe8,0xca,0xc6,0xaf,0x01,0xdf,0x08,0xd2, + 0xae,0x31,0x13,0x27,0x8e,0xf3,0x2f,0x6d,0x1e,0x33,0xc6,0xe3,0x57,0xca,0x83,0xb4, + 0x4b,0x79,0x5e,0xaf,0x4e,0x7b,0x92,0x9b,0x87,0xf4,0x97,0x20,0x90,0xf6,0x64,0xeb, + 0x0f,0xed,0xb9,0xb0,0x81,0x8c,0x1c,0xa6,0x7b,0x2b,0x78,0x52,0x37,0x1b,0xbf,0x2c, + 0xed,0x8a,0x2d,0x44,0xcc,0xd4,0xbf,0xc6,0xf3,0x2f,0x1f,0x0b,0x21,0x9e,0x17,0x49, + 0x5d,0x5e,0xff,0x12,0xba,0xc1,0x71,0xf8,0x65,0xc1,0xd6,0x78,0x63,0x02,0x7e,0xb1, + 0xfb,0x28,0xe7,0x94,0xe9,0xe2,0x86,0xa7,0x99,0xa0,0x71,0x12,0x7e,0x21,0x9e,0x3a, + 0xb4,0x6b,0x08,0x17,0xc8,0xf6,0x8b,0xe8,0x0f,0x33,0xe3,0xca,0xe4,0xe7,0x27,0xe0, + 0xd7,0x89,0xce,0x7b,0xc9,0x71,0xca,0x65,0x87,0x0c,0xbf,0x5e,0x8a,0x97,0xa5,0x3d, + 0xf7,0xd9,0xeb,0xcb,0xc1,0xaf,0xab,0x1b,0x8e,0x30,0x21,0x62,0xda,0xb7,0x50,0x3e, + 0x0c,0xe7,0x12,0x0b,0xcd,0x6c,0xfd,0xe1,0x6e,0x31,0x8a,0x64,0xc3,0x90,0x31,0x26, + 0x3a,0x3f,0x6a,0x9c,0xb3,0x34,0x93,0x0e,0x7e,0x89,0x71,0x2d,0xcc,0x0d,0x66,0x1e, + 0xd4,0xb9,0x8e,0x1f,0xa2,0xb1,0xe8,0xa3,0x89,0xf8,0x95,0x63,0x2d,0x7c,0x16,0xaf, + 0xbe,0x64,0x2c,0x33,0xc7,0xeb,0x0f,0x2d,0xfc,0x9a,0xae,0x59,0xc6,0x71,0xd8,0xd7, + 0x5e,0x76,0x62,0xbc,0xfe,0x70,0xaf,0x12,0x34,0x65,0xe6,0x52,0xf8,0xd8,0x93,0x99, + 0xb1,0x4f,0xe0,0x5f,0xbe,0x84,0xa7,0xd2,0x32,0x18,0xff,0x82,0x05,0xcc,0xc8,0xd2, + 0x1f,0x5a,0x6a,0x43,0x87,0x76,0x4d,0xe6,0x5f,0x8e,0xc2,0x4d,0x18,0x88,0x05,0x15, + 0xaa,0x75,0x65,0x02,0x7e,0x09,0x49,0xa1,0xc4,0x65,0x75,0x15,0x9a,0x75,0xe5,0x62, + 0xf8,0x65,0x19,0xce,0x15,0x07,0xbf,0x6c,0xfe,0x45,0xfa,0xb2,0x89,0x58,0x30,0x1b, + 0xbf,0x04,0xff,0x2a,0x16,0x5d,0x6d,0xaa,0x83,0x07,0x98,0x10,0x71,0xe4,0x36,0xde, + 0x67,0x07,0xbf,0x26,0xf4,0xf9,0x26,0x6e,0x68,0x13,0xf9,0x17,0xc7,0xaf,0x7e,0xf6, + 0x27,0xc2,0x4b,0x63,0x68,0xdc,0xcc,0xdb,0xec,0xcf,0xd2,0x1f,0x42,0xb5,0xea,0x61, + 0xb4,0x2b,0xc9,0x93,0xd5,0x18,0xa2,0x27,0x0d,0xc6,0xc8,0x26,0xe0,0x57,0x44,0xf4, + 0x59,0x45,0xf0,0xf5,0x47,0xfa,0x12,0xd6,0x28,0x26,0xe1,0x17,0x0c,0x64,0x3d,0x04, + 0xa5,0x80,0x8f,0x3d,0xc3,0xbf,0xde,0xca,0xee,0xb3,0x65,0x4c,0x67,0x62,0xce,0xc1, + 0x8c,0x7e,0xe3,0xde,0xf1,0x6d,0x8a,0xb2,0xf4,0x87,0xb1,0x6c,0xfc,0xe2,0xfc,0x6b, + 0x04,0x16,0xb0,0xc7,0xc2,0xf3,0xd8,0x50,0x30,0x81,0x7f,0x31,0xb6,0x15,0x11,0x65, + 0xaf,0x1b,0x19,0x7e,0xad,0x17,0x46,0x16,0xff,0x7a,0x48,0xb0,0x2d,0xb6,0xd0,0x2a, + 0x98,0xac,0xd7,0x0b,0x2c,0xfb,0xed,0x71,0xf8,0x57,0x42,0xe0,0x57,0x5a,0xd0,0x2e, + 0x5a,0x66,0xca,0xf7,0x92,0xe9,0xdf,0x5c,0x97,0x98,0xc5,0xde,0xe7,0xc1,0x8c,0x7e, + 0xe3,0x0f,0xe8,0xc7,0x90,0x76,0x7d,0x07,0xfe,0xd0,0x71,0x65,0xda,0xb7,0x5a,0x9e, + 0xae,0xbf,0x9a,0x98,0x9b,0xde,0x98,0xe1,0x5f,0xd3,0x76,0x4b,0xb8,0x64,0x0e,0x0b, + 0x9f,0xa0,0xe3,0xda,0xe9,0x92,0x87,0xda,0xcf,0x2d,0x7f,0x86,0x2d,0x22,0x0b,0xbf, + 0x40,0xe8,0xb1,0x07,0xbc,0x67,0x65,0x34,0x3a,0xe6,0x0d,0xf8,0xce,0xcb,0x9f,0x1a, + 0x47,0x53,0xf3,0xd2,0x9d,0x23,0xb2,0xe9,0xe0,0x17,0xe5,0xfd,0x61,0xfa,0xc3,0x97, + 0xca,0x74,0xb6,0xde,0x2f,0x18,0xeb,0xda,0xcb,0x06,0x0b,0x7e,0x44,0x3e,0x72,0xf2, + 0x87,0x06,0xd7,0x1f,0x72,0xda,0x45,0x66,0x88,0x35,0xf8,0x53,0x28,0x43,0x20,0x0b, + 0x98,0xb6,0x7e,0x43,0xb8,0x94,0xbc,0x2c,0x97,0x72,0x98,0x27,0x51,0x71,0xa1,0x8d, + 0xe3,0x5f,0xf5,0x66,0x55,0x92,0x97,0xc2,0xbb,0x58,0xd0,0x3e,0x4a,0xde,0x53,0xfc, + 0x5c,0x7f,0x38,0x1e,0xbf,0x0a,0xd0,0x6f,0x30,0xa3,0x87,0xfb,0x84,0x8f,0xc1,0xaa, + 0x7f,0x65,0xf0,0x4b,0x72,0x5c,0xe5,0x3f,0xa1,0x51,0x34,0x2a,0x14,0x80,0xc3,0x32, + 0x8c,0xc7,0xaf,0x1b,0xd1,0x3f,0x4b,0xcf,0x2b,0x75,0xb6,0x7f,0xae,0x36,0x6f,0x4e, + 0xca,0x09,0x5b,0xbf,0x11,0xb4,0x73,0x68,0xb6,0xcf,0x9c,0xe9,0x38,0x4f,0x3d,0xa3, + 0xdf,0x10,0x5a,0xf4,0x08,0x2b,0xe7,0x55,0xa6,0x0e,0x31,0xfd,0xe1,0x5e,0x3d,0x98, + 0x72,0x77,0xf9,0x5b,0x33,0xfc,0xeb,0x1c,0x5c,0xdb,0xeb,0xdb,0x27,0x7f,0x42,0x5f, + 0x82,0xea,0x37,0x59,0x6e,0x10,0xc6,0x98,0x78,0xf2,0x69,0x19,0xac,0xfa,0xd7,0xa5, + 0xcc,0x0d,0x62,0x0f,0x9f,0x91,0x87,0xd2,0x63,0x4a,0x5d,0x9f,0xaf,0xab,0x01,0xfd, + 0xe1,0xc2,0xba,0xbe,0x82,0x67,0xe4,0x5d,0x96,0x7e,0xc3,0xf5,0x22,0x7c,0xb6,0xb6, + 0x0e,0xe3,0x16,0xf9,0x45,0x72,0x34,0x30,0xaf,0x1f,0x8d,0x21,0x38,0xea,0xaa,0x4f, + 0x2d,0x3d,0xeb,0x71,0xea,0x5f,0x9f,0xba,0x18,0xff,0x42,0xd8,0xfa,0x54,0xdb,0x78, + 0x5f,0x79,0x3f,0x76,0x75,0x0c,0x3a,0xfb,0xe7,0x0c,0xdc,0xd8,0x15,0xb0,0xeb,0x5f, + 0x56,0xae,0xc9,0x1d,0x66,0x14,0x18,0x2a,0x8e,0xb1,0xb9,0x88,0xb6,0x09,0x20,0xdb, + 0x3e,0x11,0xbf,0xf8,0xd8,0x67,0x73,0x20,0xcb,0xe9,0x84,0xea,0x1e,0x4f,0x32,0x27, + 0x64,0xe1,0x57,0xa1,0x93,0x3f,0xdc,0xed,0x3d,0x07,0xab,0xd8,0x34,0x0d,0x31,0xc5, + 0x38,0x7b,0xc7,0xe2,0x13,0xf1,0xeb,0xee,0x51,0xfd,0x55,0x0c,0x45,0xbe,0x21,0x74, + 0x0e,0x75,0x93,0xf0,0x2b,0x6c,0x3a,0x69,0x43,0x37,0x1a,0xe4,0x90,0xc2,0xf3,0x6c, + 0xe3,0xf0,0x8b,0xa1,0xa7,0xfc,0x20,0xad,0x87,0x39,0xc8,0xbf,0x02,0xc7,0x61,0x23, + 0xcc,0x61,0xb9,0xdc,0x71,0xf8,0x65,0x97,0x56,0x61,0xa5,0x79,0x03,0x1a,0xc6,0x0e, + 0x12,0x34,0xa3,0x49,0x25,0x83,0x5f,0xd2,0x4b,0x09,0xae,0x3c,0x7f,0xac,0x1d,0xb1, + 0x60,0x88,0xf3,0x2f,0xae,0xa8,0xbf,0x2f,0xe2,0xe0,0x57,0x81,0x79,0x2e,0x91,0xfc, + 0xf0,0xc1,0x1a,0xf9,0x08,0x9c,0xa6,0x75,0x43,0x05,0x0b,0x1b,0x8e,0x98,0xbf,0x5d, + 0x53,0x3b,0x14,0xac,0x91,0xb2,0xf9,0x97,0x56,0xdf,0xc7,0xd2,0x86,0xaa,0x90,0xa3, + 0xc8,0xe7,0xe1,0x46,0x36,0xd2,0x3d,0xd9,0xfa,0x43,0x36,0x9c,0xcb,0xbb,0x65,0xc4, + 0xaf,0x85,0x75,0x29,0x36,0x40,0x7a,0x8e,0xd4,0xbd,0xee,0x9b,0xcc,0xbf,0x86,0x09, + 0x5b,0xf8,0xc1,0x37,0xec,0x7c,0xcb,0x31,0x4f,0xb3,0x3b,0xab,0xfe,0x25,0x60,0x6b, + 0xd5,0xf4,0xd2,0x5f,0xec,0x14,0x9c,0xd1,0xdc,0x97,0xe4,0x40,0x96,0x54,0x6c,0xfc, + 0x52,0x04,0x64,0x47,0xbc,0xd6,0x26,0x02,0x01,0xe2,0xcc,0xb7,0x6c,0x9e,0x88,0x5f, + 0xc8,0x07,0x3f,0x92,0x58,0xda,0xb0,0x41,0x30,0xb2,0xa5,0x09,0xf9,0xb9,0xf1,0xf8, + 0xe5,0xc0,0xd6,0x37,0x28,0x2f,0xf4,0xb0,0x2b,0xd2,0x2d,0x93,0xf1,0x8b,0xe5,0x76, + 0x8c,0x95,0x68,0xd0,0x93,0xca,0xc5,0xf8,0x17,0x7a,0xe3,0xe5,0x29,0x2b,0x6d,0xf8, + 0x01,0xe2,0xd7,0xec,0x2f,0xc5,0x2f,0x29,0xb8,0x48,0xb5,0x39,0xc8,0x45,0xf1,0xab, + 0x11,0xf6,0x04,0x82,0xd1,0x94,0xd0,0xcf,0x57,0x46,0x27,0xe1,0x17,0x20,0xdb,0xe2, + 0xf8,0x55,0xbc,0x61,0x8d,0xad,0x4f,0x70,0xc9,0x9f,0x4a,0xe3,0xf1,0xab,0xbf,0x68, + 0xb9,0xd0,0xcf,0x23,0x4f,0x71,0xf4,0xf3,0xe2,0x5d,0x2d,0x95,0x44,0x9b,0xa5,0x71, + 0xf9,0x07,0x70,0x00,0x6a,0xd8,0x9f,0xce,0xc0,0x59,0x7d,0x15,0xc7,0x2f,0x25,0x1b, + 0xbf,0xc0,0x43,0x70,0x14,0xbb,0xf4,0x00,0x20,0x11,0x3b,0xb1,0xa8,0x5b,0x5a,0xa0, + 0xa1,0xe1,0xe0,0x57,0xa3,0xc3,0xbf,0xa0,0x25,0xaa,0xdf,0xc1,0x8d,0x3d,0x86,0xde, + 0xe4,0xb9,0x28,0xff,0x92,0x9e,0x90,0x02,0x86,0xcc,0xc6,0x7e,0x35,0x99,0x29,0xc6, + 0xee,0xe0,0x97,0xc5,0x73,0x07,0xe0,0x80,0x54,0x23,0x40,0x8a,0x3d,0x1f,0xa6,0x9f, + 0x07,0x07,0xbf,0x32,0xd0,0x46,0x5e,0xe4,0x79,0x51,0x38,0x79,0x51,0xfc,0x62,0xb4, + 0xcb,0x1c,0x86,0x9f,0xb0,0xb2,0x97,0x6e,0xcf,0xb2,0xcd,0xd1,0x38,0x7e,0x15,0x30, + 0xda,0x35,0x05,0x8d,0x9f,0xb0,0xb4,0xa1,0x40,0xb4,0x86,0x44,0xc3,0x04,0xfd,0xc6, + 0xc3,0x21,0x92,0xc3,0x5f,0x36,0x77,0x88,0x28,0x3c,0x6a,0x62,0xf8,0xa5,0x64,0xe3, + 0x97,0x89,0xd1,0xa0,0x06,0xfb,0x34,0x95,0x25,0xbd,0xd9,0x95,0x7c,0xb3,0xb3,0x99, + 0xec,0xca,0xc6,0xaf,0x6b,0xd3,0x37,0xdd,0xd7,0x76,0x19,0x1a,0xf9,0xe9,0xe9,0x67, + 0xe5,0x4b,0xf2,0x38,0x23,0x5b,0x2d,0x7d,0x94,0xcd,0xbf,0xa6,0xb3,0xd5,0x94,0x86, + 0x73,0xee,0xba,0xfe,0xfc,0xae,0xaf,0x0f,0x88,0x20,0xf0,0x99,0xb6,0x0c,0x7e,0x01, + 0xc3,0x2f,0xdf,0xb3,0x32,0x31,0x8e,0xb6,0x84,0x3f,0x47,0x42,0xf7,0xb9,0x71,0x94, + 0x29,0xea,0xcf,0x3e,0xe4,0xe0,0xd7,0x83,0xb0,0x77,0x3b,0x86,0xa9,0x0b,0x67,0x13, + 0xfa,0x06,0xe8,0xe9,0x29,0x0b,0x71,0x7d,0xed,0x48,0x06,0xcd,0xca,0x1a,0x7f,0x06, + 0xbf,0xb4,0x7d,0x7a,0x95,0xe9,0x1e,0x26,0x4d,0xb0,0x4e,0x2b,0x33,0x6f,0x6c,0x26, + 0x7d,0xca,0x3a,0x7f,0x90,0xe7,0x0f,0xb3,0xf1,0x8b,0x2b,0xc1,0x0c,0xe4,0x32,0xdc, + 0xc9,0xf4,0xc1,0x0e,0xae,0x66,0xc9,0xc2,0x2f,0x0c,0xbf,0xd1,0x1f,0x0e,0xcb,0x06, + 0x1c,0x85,0xbd,0xe8,0xe2,0x70,0x4e,0x99,0x3f,0xf4,0x0e,0x4f,0xc4,0x2f,0x0c,0xf5, + 0x13,0x3c,0x6d,0x88,0x7e,0xc3,0x1a,0x17,0xe3,0x44,0x13,0xf8,0x57,0xf9,0x30,0x7c, + 0x06,0xf3,0x18,0x0e,0x2e,0x00,0x91,0x8b,0x0b,0x98,0x93,0xf8,0xd7,0x6f,0x95,0x4e, + 0x0c,0xe3,0x0b,0x92,0xe4,0xd7,0xf6,0x95,0xf4,0x78,0xfc,0xc2,0x98,0xff,0x7d,0x9d, + 0xd5,0xbf,0xb0,0xcf,0x15,0xd4,0x6e,0xe3,0xe0,0x97,0xbe,0x57,0x0d,0xf6,0x79,0xe6, + 0x13,0xd3,0xc4,0x50,0xe4,0xf0,0xc1,0x30,0x59,0xa3,0xe2,0x15,0xd3,0x33,0x8f,0x38, + 0xf9,0xc3,0xef,0x99,0xcf,0x37,0x23,0xff,0xfa,0x5c,0x4e,0xd3,0xdf,0x37,0x21,0xee, + 0x7c,0xfe,0xb5,0x19,0xda,0xb9,0x50,0xdd,0x9b,0x4b,0x87,0xcb,0x1d,0xfd,0x06,0x1b, + 0x57,0xfd,0x31,0xdf,0x0f,0x1b,0x86,0xcd,0x31,0x7d,0xce,0x2b,0x05,0x7b,0xdb,0x46, + 0xe3,0xe7,0xca,0xea,0x0f,0x20,0xa2,0xd9,0xfa,0x43,0x31,0x5f,0x69,0xce,0xbf,0x5e, + 0x12,0x44,0xec,0xd7,0xf0,0x39,0x63,0xd0,0x4e,0xfe,0xd0,0xb4,0xf2,0x87,0x9e,0xae, + 0x56,0x87,0x88,0x0d,0xd1,0xe7,0xf0,0x4a,0x1e,0xf2,0x2f,0xf1,0x7c,0xa2,0x4e,0xfe, + 0x90,0x6c,0x50,0xe7,0x59,0x3c,0x45,0xef,0x12,0xc6,0x47,0x93,0xf9,0x57,0x06,0xc8, + 0x9e,0x13,0x86,0xc5,0xbf,0x68,0x86,0x7f,0x09,0x02,0x75,0x79,0xd2,0xda,0xa3,0x81, + 0x57,0x2c,0x4d,0x4e,0x06,0xbf,0x1a,0x46,0xad,0x29,0x40,0xec,0xbe,0xc0,0x77,0x49, + 0x34,0x8c,0x08,0x2d,0x0d,0xc3,0xaf,0x8f,0x1d,0xfe,0x05,0x82,0x7f,0x15,0x7f,0x41, + 0xfd,0x59,0xfc,0xab,0xc3,0x15,0xa4,0x59,0x78,0xea,0xf4,0x67,0x22,0xff,0xda,0x31, + 0x89,0x7f,0x75,0x09,0x44,0x1b,0x16,0x53,0x91,0x68,0x99,0x4e,0x05,0x16,0xe4,0xd8, + 0xfc,0x2b,0x70,0x9c,0xbe,0x48,0xcb,0x18,0x16,0x1c,0xa3,0xbc,0x0d,0xdb,0xff,0xf5, + 0x5b,0xe0,0xfa,0x8d,0x23,0xc6,0x69,0xad,0x76,0xd0,0x87,0xf8,0x45,0x4f,0xc5,0x43, + 0x8c,0x88,0xbd,0x9d,0xc3,0xdb,0x88,0xfc,0x21,0xdb,0x13,0x51,0x64,0xbd,0x6c,0x7b, + 0x70,0x5c,0x5f,0x48,0x88,0x68,0x88,0x5f,0x42,0xd7,0xb4,0xcb,0x75,0x58,0x3d,0x24, + 0xf2,0x87,0x41,0xce,0x4f,0x79,0xac,0x75,0x50,0x18,0xbd,0x16,0x7e,0x6d,0x12,0x6a, + 0x43,0x0b,0xbf,0x2c,0xfe,0xb5,0x56,0x18,0xaf,0xdb,0xef,0xfc,0x63,0x4c,0x2d,0xcf, + 0xf9,0x17,0x38,0xfc,0x6b,0x2d,0x1a,0x37,0xae,0xb6,0xe3,0x43,0xc4,0x2f,0xd2,0x26, + 0x86,0xec,0x95,0xac,0xb1,0x0f,0x41,0x2b,0x78,0xb3,0xf9,0x57,0x61,0x07,0x30,0xb5, + 0x3c,0x97,0x1d,0x7e,0x81,0xae,0x29,0x37,0x41,0x06,0xc9,0x83,0x84,0xef,0xfa,0xf9, + 0x42,0xf8,0xba,0x49,0xf8,0x35,0x8e,0x7f,0x89,0xb9,0x60,0xf8,0x75,0x60,0x22,0x2f, + 0x50,0x0e,0xc4,0x2d,0xfe,0xc5,0xdb,0x20,0x7e,0x11,0xa6,0x24,0xf4,0xc5,0xc3,0x36, + 0xbf,0xf0,0x0f,0x28,0x6f,0x91,0x1a,0x81,0x5f,0xfc,0x23,0xf4,0xf3,0x36,0x7e,0x11, + 0x27,0x91,0x68,0xf1,0x2f,0xe1,0xc7,0x14,0x45,0x6b,0xc9,0xf0,0xaf,0x95,0x8b,0x1e, + 0x41,0x43,0xdb,0x24,0xae,0x44,0x44,0x1b,0x86,0x5f,0x6c,0x7f,0x93,0x67,0x0d,0x87, + 0xda,0x9f,0x14,0x6f,0xa4,0x72,0xcf,0xa2,0x14,0xfc,0x04,0x2e,0x47,0xfe,0x25,0xf2, + 0x1b,0xa9,0x7c,0xd1,0xd5,0x02,0xab,0xcf,0x8b,0x38,0x36,0x9d,0x17,0x82,0xbd,0x4f, + 0x2d,0xfe,0x25,0x21,0x5a,0x49,0xfc,0x4f,0x03,0xd2,0x59,0xa9,0xfa,0x9b,0x68,0x3c, + 0x2e,0xbd,0x06,0x1c,0x97,0x2d,0xbe,0xbc,0xda,0xc2,0xaf,0xcb,0x81,0x58,0x40,0x46, + 0x89,0xde,0xda,0x01,0x01,0x66,0xec,0xb7,0xf5,0xf3,0x99,0xfc,0x21,0x1a,0x15,0x62, + 0x93,0x57,0x0b,0xf0,0x9c,0xe7,0xeb,0x62,0xbe,0x4a,0x6f,0x17,0xf8,0xb5,0x3e,0xc3, + 0x3d,0xfd,0x15,0xca,0x2c,0xc4,0xa6,0x97,0xe3,0xe1,0xfd,0xe2,0x19,0x26,0x8a,0x77, + 0x7a,0x59,0x7f,0x3c,0x02,0xb6,0x18,0xb4,0xc9,0xed,0xf8,0x7c,0x78,0x7f,0x06,0x85, + 0x2e,0x6e,0x85,0x93,0x3f,0x74,0xe6,0x82,0x89,0xed,0xe1,0x45,0x76,0xe5,0x6d,0x8b, + 0x5b,0x39,0xfb,0xbf,0x8a,0x74,0xc5,0x9e,0x53,0x6e,0x60,0x9f,0x33,0xfb,0xbf,0x40, + 0xec,0xff,0x8a,0x30,0xd8,0xaa,0x61,0xb4,0x6b,0x50,0xeb,0xa2,0xec,0x4a,0xb8,0x57, + 0x3c,0xe7,0x4a,0x57,0xa3,0xc4,0xde,0xb1,0x29,0xe3,0x38,0xfe,0x1e,0x1a,0x34,0x6f, + 0x0c,0xf9,0x7b,0xed,0xf8,0xf0,0x12,0xfe,0x3e,0x77,0xde,0x97,0xf5,0x3e,0xd3,0xa7, + 0x55,0x66,0xe8,0x29,0x83,0xaf,0xd3,0x4a,0xf5,0x12,0xf2,0x2a,0x43,0xab,0x7f,0x92, + 0xa7,0x2b,0x7f,0x68,0x67,0xb0,0x25,0x1f,0x4f,0x0a,0xfc,0x92,0x0f,0x8a,0xf5,0xa5, + 0x4e,0x6b,0xcf,0x4a,0x59,0x48,0x97,0xf5,0x31,0x83,0x71,0xfc,0x2c,0xfe,0x65,0x94, + 0x7c,0x6e,0xd7,0x53,0x3e,0xe5,0x8e,0xd1,0x8b,0x8e,0x51,0x7f,0x1a,0x1f,0x00,0xfa, + 0xc3,0x63,0x96,0x26,0xf0,0xd2,0x76,0xd1,0x8d,0x85,0x91,0x23,0x48,0xc4,0xaa,0x19, + 0x11,0x7b,0x17,0xf6,0x3c,0x85,0x3e,0x61,0x21,0xf9,0x58,0xb4,0x01,0xba,0x25,0xd3, + 0xd5,0x7d,0x1a,0xdb,0x08,0x16,0x79,0xd7,0xf8,0x57,0x9d,0x03,0xd9,0x4e,0x2b,0x7f, + 0xa8,0xf4,0x65,0xa7,0x74,0xaa,0x33,0x44,0xec,0x91,0x10,0xfc,0x46,0xb1,0xd6,0xfb, + 0x4e,0xde,0x67,0xcf,0x30,0x07,0x29,0x46,0xc4,0xa4,0x51,0xec,0x33,0xcf,0x47,0x3d, + 0x09,0xd6,0x5a,0x1e,0xb2,0x6a,0x25,0x56,0xac,0xfe,0xa0,0xd0,0x0c,0x58,0xde,0x4f, + 0xe0,0x17,0x7c,0xce,0x5d,0x4a,0x81,0x90,0x2f,0xd6,0xdb,0xf5,0x2f,0x46,0xc4,0xe4, + 0xf4,0x72,0x2b,0x3e,0x5c,0x99,0x71,0x83,0x1f,0x4b,0xd5,0xa2,0xb6,0x85,0x2f,0x52, + 0x0f,0x02,0xd9,0x49,0x7b,0xff,0xd7,0xf2,0xf1,0x3e,0xb3,0x94,0x19,0xcf,0x72,0x32, + 0x42,0xd2,0x12,0x9f,0x0b,0x15,0xf2,0xd9,0xb8,0xfa,0x59,0xda,0x90,0xee,0x50,0x56, + 0x9a,0xee,0x05,0x6c,0x4e,0xb5,0x60,0x9f,0x3b,0xec,0xb7,0xe6,0x1d,0xd4,0xe5,0x62, + 0x2e,0x4e,0xb7,0x0d,0xc5,0xd0,0x8f,0x1d,0xf3,0x3e,0x45,0xce,0xc3,0xd9,0x15,0x78, + 0x65,0xaf,0x9c,0xce,0xb5,0xf5,0x1b,0xac,0xab,0x29,0xce,0x19,0x3f,0x23,0xf5,0x47, + 0x98,0x3f,0xdc,0x75,0x4e,0xaf,0x4f,0x15,0xec,0x2d,0x72,0xf0,0xeb,0xd7,0xf0,0x0e, + 0xce,0x57,0xfe,0x88,0xa7,0x8e,0x1c,0x5e,0x36,0xcf,0xfb,0xe0,0xb3,0x2c,0x7f,0x48, + 0xeb,0xb3,0xf2,0x87,0x66,0xe9,0xa7,0xda,0xf3,0xb4,0x86,0x65,0x0b,0xab,0xbd,0xeb, + 0x43,0x7a,0xbe,0xda,0x55,0xf4,0x6b,0x51,0x11,0x43,0xfc,0x12,0xfa,0xf9,0x54,0xe3, + 0x61,0xe5,0x21,0xc2,0x5f,0xbf,0x0d,0xb0,0x0d,0x2a,0x4c,0x77,0x96,0xc3,0x7f,0xdf, + 0xd6,0xcf,0x3b,0xfc,0x2b,0xa8,0x26,0x20,0x07,0x2a,0x93,0x11,0xbc,0x22,0x15,0x30, + 0x34,0xb7,0xb4,0xfa,0x80,0xf8,0xf5,0x0e,0x86,0x10,0xf9,0x21,0xf4,0xcf,0x83,0xf0, + 0xb9,0xb6,0x38,0xa3,0xbb,0x18,0x9f,0x3f,0xbc,0x06,0xe7,0x54,0x1a,0x85,0x77,0xe0, + 0x6a,0xea,0x63,0xc6,0xf8,0xfc,0xe1,0x6d,0x9c,0x7f,0xfd,0xc4,0xf4,0x76,0x31,0x7a, + 0x82,0xbc,0x3b,0xdf,0xbe,0xcf,0xc6,0x49,0xf9,0x43,0xf5,0xa9,0xd6,0xa3,0x8c,0x88, + 0x51,0x95,0xd5,0xc8,0x26,0xe9,0x37,0x34,0xce,0xf1,0x6b,0xc9,0x51,0xf4,0x24,0x95, + 0xe0,0x61,0xbb,0x5c,0xac,0xa8,0x69,0x58,0xc4,0xfc,0xc3,0xda,0x77,0x38,0x6c,0xe5, + 0xdd,0x47,0x8e,0x97,0x3d,0x43,0x67,0x2d,0x6f,0x65,0x42,0xc4,0xab,0x12,0x55,0x3c, + 0x7f,0x68,0xeb,0xe7,0x6f,0xa6,0xa7,0x93,0xc1,0xc1,0x7c,0xc4,0x2f,0xf3,0x24,0x2c, + 0x1c,0xfc,0xcb,0x85,0xc8,0x4f,0x4f,0x27,0x6a,0x45,0xfe,0x50,0x13,0x6b,0x67,0x37, + 0xd3,0x6f,0xf4,0x55,0xef,0xc1,0xae,0x8e,0x4a,0x3f,0x34,0xc4,0xfe,0x2f,0x96,0x3f, + 0xdc,0x93,0xa5,0xdf,0x50,0x7e,0xa4,0xd4,0xf0,0x1c,0x23,0xa7,0x03,0xf9,0xc9,0x22, + 0x5e,0x83,0xc6,0x2b,0x77,0xf7,0x8a,0xe7,0x93,0x72,0xf4,0x1b,0x2c,0x6d,0x08,0x7a, + 0x5f,0x47,0xb3,0xec,0x5c,0x79,0x3d,0x5b,0xbf,0x31,0x8b,0x63,0x2e,0xcb,0xc9,0xbc, + 0xbf,0x62,0xb5,0xd8,0x73,0xcd,0x80,0x2c,0xe5,0xe8,0x37,0x34,0x31,0x83,0x39,0x87, + 0xf1,0x9f,0x97,0xa7,0x3b,0x78,0x7d,0x59,0xcc,0xe9,0xdb,0x90,0x55,0xff,0xaa,0x41, + 0xfc,0x2a,0x4a,0xc1,0x17,0xc3,0x7c,0xff,0x97,0x5d,0x11,0x93,0xbf,0xb0,0xf0,0x54, + 0x4a,0x64,0x60,0xeb,0x0c,0xf6,0xe8,0x66,0x7b,0xff,0xf2,0xe5,0x59,0xfa,0x79,0x2b, + 0xe6,0x7f,0x38,0xf7,0xf7,0x7c,0x3b,0x92,0x37,0x0b,0xc8,0x7a,0x45,0x7f,0x1c,0xfe, + 0xf5,0x33,0xc2,0x38,0xda,0x76,0xa3,0x52,0x38,0xea,0xba,0x2c,0xfe,0xb5,0x50,0xca, + 0xf0,0x2f,0xfd,0x61,0xe0,0x7b,0xd2,0x9d,0x64,0xda,0x11,0xb1,0x5f,0xc6,0xd6,0x6f, + 0x1c,0x62,0xf8,0xf5,0xb4,0x5e,0x16,0x55,0x33,0x89,0xc4,0x71,0xfa,0x79,0xde,0x67, + 0xbc,0x73,0xea,0x96,0x79,0x36,0xff,0x1a,0x97,0x3f,0x2c,0xb1,0xf9,0x17,0x76,0xf5, + 0x2d,0x26,0x3b,0x14,0x7d,0xae,0x61,0x84,0xc5,0xe2,0x5f,0x5b,0x1d,0xfd,0x06,0x42, + 0xdb,0x81,0xca,0xf0,0xe2,0x9b,0x37,0x65,0xc6,0xe5,0xe8,0x37,0x62,0x36,0x6c,0xa5, + 0x61,0x7d,0x0c,0xdf,0xc3,0xd6,0x0c,0x90,0x1d,0x11,0x71,0x0b,0xd7,0x6f,0x10,0x81, + 0xb9,0xa4,0x45,0xd5,0xc7,0xf5,0xf9,0x75,0x89,0xb7,0xb1,0xf4,0x1b,0x36,0x64,0xb3, + 0xfd,0x05,0x81,0x81,0x4c,0xee,0x94,0xb7,0xb1,0xf9,0x17,0xc7,0xa6,0x03,0x66,0xe0, + 0x07,0xd9,0xcf,0x39,0xa3,0xdf,0x28,0xb5,0xdb,0x90,0x93,0xfe,0x17,0x8d,0xaa,0xac, + 0x36,0xaf,0x4f,0xd0,0x6f,0xb4,0x20,0xed,0x3a,0x66,0x24,0xb5,0x20,0x95,0x18,0x90, + 0x4d,0x67,0xcf,0xa7,0xd7,0xc9,0x1f,0x2a,0x3c,0x7f,0x38,0x80,0xfc,0x6b,0xbd,0x12, + 0xc8,0xf0,0x2f,0xcf,0x44,0xfd,0x86,0xa9,0x56,0xb4,0x4a,0xe1,0x87,0x90,0x83,0x48, + 0x0e,0x90,0x8d,0xd3,0x6f,0xf0,0x7c,0x5d,0xd4,0x5d,0xa8,0xae,0x2b,0x2b,0x4b,0xe5, + 0xad,0xce,0x24,0xc6,0xd3,0x62,0x4e,0x2d,0xfd,0x7c,0xda,0x7b,0x87,0x7c,0x19,0xdc, + 0x9a,0x48,0x0e,0x56,0x8d,0x78,0xac,0x8a,0xd8,0x6a,0xf9,0x7d,0xb1,0x07,0x41,0x15, + 0x5a,0x08,0xd3,0x07,0xb2,0x09,0xe7,0x6e,0xa9,0xfb,0x5f,0x05,0x4f,0x89,0x84,0x9b, + 0x99,0x8b,0xf8,0x65,0xe5,0x7f,0xae,0x7b,0xb1,0x71,0xac,0x15,0xf9,0x57,0x54,0xf6, + 0xc3,0x7b,0xe9,0x79,0xa3,0x1b,0xce,0xb7,0x59,0x15,0xb1,0x11,0x47,0x3f,0x7f,0xe9, + 0x63,0x74,0x5f,0x22,0x98,0x9e,0x52,0x20,0x47,0x3a,0x5e,0xdd,0xaa,0x7f,0x52,0x70, + 0x9f,0x5d,0x38,0xb8,0xcf,0xd6,0xcf,0xab,0x4c,0xbf,0x81,0xfc,0xcb,0x13,0x21,0x9a, + 0xf9,0x53,0xa5,0x2c,0x25,0xaf,0x62,0x40,0x06,0xdf,0x4b,0x79,0x56,0xd9,0xfc,0x2b, + 0xc6,0xf4,0x1b,0x8c,0x69,0x82,0xdb,0x80,0xb6,0x25,0x89,0xbe,0x6c,0x9f,0x99,0xd1, + 0xcf,0x8b,0xd5,0x0d,0x32,0xc0,0x7b,0x74,0xef,0x70,0xd5,0x30,0x62,0x2e,0xf3,0x6c, + 0xbe,0x64,0xf9,0x47,0x62,0xec,0x71,0x18,0x92,0xb8,0x67,0x63,0xeb,0xeb,0xb4,0x52, + 0xd7,0x6b,0xf9,0x3a,0xd6,0xc6,0xce,0x1f,0x26,0x34,0x0b,0xad,0xcc,0xa2,0x66,0xf5, + 0x1d,0x08,0x99,0xc1,0x61,0xb9,0x16,0xde,0x83,0x39,0x8c,0x88,0xa5,0xc6,0xe9,0x37, + 0x4c,0xcf,0x86,0x29,0x77,0x6b,0x4c,0x52,0xa8,0xb1,0x3d,0x47,0x96,0x3f,0x1c,0x74, + 0xf8,0x97,0xf2,0xbc,0x54,0xdd,0xe3,0xe9,0xf0,0xdf,0x15,0x7a,0x04,0xf9,0x97,0x14, + 0x82,0x20,0x4f,0xa6,0xc9,0x19,0xfe,0x55,0x8c,0xe1,0xee,0xa2,0xe0,0x6f,0x3c,0xd0, + 0x6a,0xb0,0x23,0x2c,0x0e,0x5c,0xb6,0xc0,0xbd,0x84,0xee,0x35,0x56,0xa6,0x3c,0x73, + 0x89,0xa5,0x9f,0xa7,0xf9,0x2b,0x53,0xe7,0x62,0xd5,0x6f,0xf9,0xda,0xe4,0xe5,0x03, + 0xef,0xe9,0xf3,0x0e,0x7b,0x87,0xdb,0x82,0xf4,0x9d,0x15,0xc8,0xc8,0x92,0xb2,0xcd, + 0xbf,0xfe,0x79,0xa8,0xff,0x5c,0xac,0xfe,0xf0,0xd2,0xd6,0xc2,0x74,0xfc,0x5c,0x71, + 0xdd,0xe1,0x9b,0xba,0xe4,0x17,0x8c,0x73,0x65,0x75,0x7d,0x8c,0x7f,0x59,0xd8,0xe4, + 0x1a,0xad,0x3c,0xa2,0xcf,0x8d,0x79,0xb6,0x62,0xbc,0x31,0x0a,0x75,0xe9,0xa5,0x23, + 0xe5,0x0b,0x00,0x6f,0x98,0x2e,0x40,0xfe,0x45,0x2d,0xfc,0x1a,0x62,0xdb,0x45,0x6d, + 0xcc,0x9d,0xc9,0x01,0x08,0xfe,0xa7,0x31,0x3b,0x3d,0xa5,0xdb,0xae,0x95,0xa4,0x5c, + 0x1b,0x80,0x6a,0xfa,0x38,0x9e,0x12,0x84,0x36,0x7f,0x0c,0x81,0x2c,0x72,0x4a,0xac, + 0x2f,0x53,0xd9,0x4d,0x3a,0x0d,0x64,0x37,0x7b,0xd8,0x7d,0x4c,0x7c,0x2c,0x21,0x77, + 0x10,0x7e,0x29,0xb0,0x7b,0x44,0xbc,0xf3,0x52,0xc9,0x60,0xef,0x41,0x8c,0xaf,0x3d, + 0xdd,0x6c,0x0a,0x4c,0x0e,0x5b,0x05,0x06,0xdb,0xc8,0x3c,0x1d,0xc7,0x65,0xf0,0x36, + 0x69,0xe9,0x49,0x38,0xcf,0x8e,0xdd,0x18,0x61,0x21,0x84,0xbd,0x97,0x5c,0x6c,0x64, + 0x6e,0x18,0x11,0x6d,0x0c,0xad,0x83,0xa4,0x0c,0x76,0xec,0x86,0x27,0x08,0x1f,0x1b, + 0xfc,0x20,0x8e,0x21,0xbe,0x21,0x1a,0x6f,0xf8,0x1b,0xd1,0xe7,0x63,0xae,0x85,0xd0, + 0x09,0x0b,0x58,0xb6,0xd0,0xd9,0xd4,0x30,0x04,0x1b,0x69,0x80,0x15,0x2e,0x3f,0xe7, + 0x8f,0x19,0x4c,0x88,0x92,0x0e,0x8c,0x88,0x54,0xb6,0xac,0x76,0x28,0x95,0x22,0x87, + 0xd6,0xa6,0x55,0x70,0xfc,0x12,0x79,0xa4,0x11,0xed,0x16,0xf2,0x00,0xbd,0x82,0x4b, + 0xd0,0x0d,0x91,0x36,0x24,0xc7,0xa5,0x75,0xfd,0x33,0x18,0x16,0x8c,0x52,0x7e,0x9f, + 0xa8,0x1a,0x25,0xbd,0xf8,0xda,0x78,0xbb,0x65,0x24,0x62,0x04,0xe3,0xba,0x1a,0x96, + 0xcf,0x4c,0x3c,0x65,0x7a,0xae,0x71,0xf8,0x57,0x49,0x37,0x8e,0xa2,0xce,0xbc,0xe2, + 0xa4,0x3c,0xaa,0x8d,0xc1,0xe5,0x7d,0x9e,0x93,0x3c,0x2f,0xca,0x8b,0xb6,0x16,0xff, + 0x52,0x95,0xdd,0xea,0x01,0xb6,0x0b,0x20,0x59,0x54,0xad,0x1c,0xa2,0x4c,0x26,0x8a, + 0x40,0x7f,0xd4,0xe0,0xe3,0x3a,0x28,0xd6,0x69,0xaa,0xf4,0xb1,0xd6,0x35,0x7c,0x9b, + 0x27,0x99,0xaa,0xae,0xb3,0x0c,0x58,0xa7,0x96,0xb1,0xf5,0x7e,0xca,0xca,0x5d,0x60, + 0x34,0xbd,0x96,0x96,0x0d,0x5b,0xb2,0xf9,0x32,0x4b,0x3f,0x9f,0xe4,0x9c,0xd1,0x5a, + 0x5f,0x83,0xca,0x03,0x46,0x1b,0xb2,0xd1,0xca,0x85,0x6e,0xaf,0xdc,0x66,0x26,0xcc, + 0xca,0x90,0xbb,0x20,0xc2,0x94,0xb1,0x1c,0xbf,0x44,0x9b,0x92,0x2f,0xe0,0x88,0x81, + 0xb0,0xf5,0xa4,0x5c,0x09,0x47,0x68,0x18,0x7d,0x94,0xcc,0xf6,0x7f,0x71,0x21,0x87, + 0xf5,0x5d,0x51,0x89,0xea,0x23,0xba,0x4d,0xbb,0x34,0xcb,0x18,0xb6,0xeb,0x5f,0x62, + 0x5c,0x88,0x5f,0x3d,0xd0,0xc5,0x60,0xab,0x02,0xce,0xaa,0xac,0xfe,0xd5,0x20,0x76, + 0xda,0x8e,0xc3,0x2f,0x85,0x6d,0x5b,0x56,0xb7,0x90,0x19,0xf0,0x6c,0xa4,0xba,0xc9, + 0xb3,0x25,0xf0,0x3b,0xf6,0x66,0x72,0xfc,0x12,0x75,0x61,0xa6,0x3f,0xbc,0x5f,0x0d, + 0x44,0x54,0xad,0xb5,0x42,0x7f,0x56,0xad,0x8e,0x78,0xe2,0xad,0x7d,0x3a,0x5e,0xc9, + 0xe2,0x5f,0x88,0x5f,0xb4,0x45,0xd7,0x99,0xda,0xd0,0x29,0x7b,0x21,0x28,0xe8,0x42, + 0xbf,0x21,0xbe,0x6b,0x24,0x7f,0x99,0x61,0x36,0x85,0x8a,0xbd,0x2e,0x8f,0x64,0x0c, + 0x7f,0xb3,0xb6,0x78,0xa3,0x4b,0xee,0x69,0x34,0x9b,0xba,0x58,0x9f,0x3f,0x17,0x58, + 0xd9,0x51,0xf2,0x66,0xe4,0xbc,0x56,0x6f,0xcc,0x61,0xf8,0xc5,0x8c,0x8d,0x0c,0xa4, + 0xce,0x6a,0x8c,0x21,0x16,0xbd,0x6f,0xe3,0x17,0xc2,0x31,0x0d,0x1b,0xca,0x16,0x79, + 0x06,0x1b,0x4e,0x53,0x70,0x8b,0xfc,0x3b,0xa6,0x3f,0x64,0xe3,0xda,0x4e,0x2c,0xfc, + 0xea,0x31,0x3b,0xf4,0x80,0xaa,0x22,0xed,0x82,0x0e,0x9d,0xe9,0x0f,0x03,0x69,0x78, + 0xca,0xd8,0x9e,0xc5,0xbf,0x10,0xbf,0xe8,0x9a,0x68,0x59,0x83,0xfa,0x3a,0x29,0x5e, + 0xbb,0x26,0x5a,0x6e,0xa8,0xb7,0x90,0x37,0xe9,0xd3,0x31,0xd6,0xe7,0x9c,0x9f,0x89, + 0x36,0x5b,0x95,0x9d,0xc6,0x9a,0xd8,0x36,0xa3,0xf2,0x75,0x77,0x31,0x3c,0x40,0xbf, + 0xce,0x37,0x32,0xd3,0x7f,0x15,0xb9,0xd3,0x4f,0x45,0x0c,0x89,0xf8,0x45,0x78,0x78, + 0xa0,0xe1,0x73,0x3e,0xa0,0x86,0x0c,0x95,0x27,0x6c,0x45,0x9e,0x76,0x97,0x3d,0x5f, + 0x3f,0x87,0xb3,0x54,0xec,0xff,0xb2,0xd3,0x86,0x8e,0xf1,0x3a,0xb5,0xe6,0x8b,0x76, + 0xb0,0x6d,0xa7,0x1b,0xd8,0x16,0xe0,0x94,0xd1,0x05,0x5e,0x9a,0xab,0x63,0x64,0xc7, + 0xf7,0x7f,0xf5,0x8a,0x36,0x2c,0x7f,0xb8,0x9e,0xcb,0xe6,0x73,0x06,0xc9,0x7a,0x1a, + 0x68,0xe1,0xf8,0xf5,0x6b,0xba,0x00,0x89,0x98,0xdc,0x5a,0x21,0xe6,0x42,0xb9,0x09, + 0xda,0x68,0x65,0x1a,0x97,0xd5,0x11,0x56,0xf6,0x62,0x5c,0xa6,0x00,0x5a,0x5b,0x99, + 0x27,0xb1,0x63,0x75,0xaa,0xbd,0x5b,0x9c,0x6b,0xcc,0xfa,0x0d,0xbe,0xc6,0xff,0xa1, + 0xe1,0x6b,0xdc,0xaf,0xfe,0x98,0x5c,0x2e,0xfd,0x3c,0x8f,0x17,0x95,0x52,0xdc,0x65, + 0x42,0x47,0xc7,0x77,0xc8,0x11,0xfa,0x7c,0x22,0xb8,0x22,0xf0,0x05,0xb9,0x99,0x96, + 0x27,0x82,0x83,0xee,0x1a,0xf2,0x6a,0xeb,0x5c,0xce,0xbf,0x78,0x77,0x38,0x7e,0xb1, + 0xca,0xec,0xfd,0x59,0x21,0xd6,0x20,0x06,0xc0,0xdc,0xc9,0xb4,0xb6,0x0b,0xbf,0xa1, + 0x3c,0x49,0x5f,0x6b,0x99,0xb7,0xfc,0x86,0x67,0xe5,0x0f,0xe0,0x3c,0x5d,0xb0,0xdc, + 0xbb,0xd5,0xb3,0x00,0x46,0xe2,0x61,0x16,0xcf,0xf7,0x6f,0xe7,0x6d,0x9e,0x2c,0xfd, + 0x99,0xb9,0x06,0xca,0x57,0xe2,0x92,0xf9,0x37,0xf3,0x69,0x28,0x5b,0xa1,0x5e,0x46, + 0x2e,0x89,0x77,0x27,0xca,0x4e,0x78,0x6a,0xc8,0x47,0xe2,0x19,0x6a,0xb0,0x35,0xb4, + 0x05,0xca,0xd5,0x47,0xee,0x6a,0xed,0xcf,0x7b,0x4a,0x2d,0x83,0xbc,0x5e,0xd2,0x14, + 0x7b,0x9a,0x96,0xb1,0xcd,0x6b,0x03,0x36,0x7e,0x75,0x40,0x7c,0x58,0xd7,0x0b,0x77, + 0xe1,0x8a,0xeb,0xc6,0x67,0x26,0x51,0x02,0xc5,0x7b,0x44,0x6e,0xa7,0x5f,0xb4,0xe9, + 0x2e,0xf9,0x14,0xde,0x30,0xba,0xde,0xf7,0x6d,0x65,0xdb,0x60,0x7b,0xc2,0xe6,0xaf, + 0x92,0x9e,0x95,0x85,0xcf,0x61,0x40,0x8e,0xf1,0xea,0x07,0xd6,0xba,0x90,0x76,0x13, + 0x96,0x6b,0xba,0x39,0x9e,0xd9,0xbf,0xbc,0x1b,0x4e,0xf1,0x58,0x3d,0xd7,0xd2,0x12, + 0x27,0xb4,0x47,0x71,0x55,0xee,0xa5,0xbe,0x9e,0xdc,0x85,0x70,0x41,0xbd,0x8a,0xfa, + 0xd2,0xf2,0x42,0x5b,0x7f,0x98,0x16,0x3e,0x73,0x27,0xe2,0x17,0x9b,0x2f,0x0f,0x95, + 0x59,0x98,0x11,0x16,0x7a,0x9b,0xe7,0xd1,0x43,0xde,0x98,0x24,0x67,0x96,0x8b,0xb9, + 0xc0,0x39,0x65,0xa1,0x91,0x9b,0x95,0x95,0x9f,0x80,0xd9,0xc6,0x8d,0x68,0x48,0xbb, + 0x78,0x15,0xc6,0x9f,0x16,0xf3,0xe5,0x2e,0x56,0xe9,0xfd,0xa0,0xdf,0xe0,0xb9,0xc4, + 0x7d,0x5d,0x7c,0x0f,0x54,0xde,0xe1,0x29,0x9e,0xad,0x24,0x92,0xa1,0x8a,0x14,0x46, + 0xc2,0xf6,0x9c,0xe6,0x47,0x13,0x29,0x29,0xac,0x16,0xe0,0x3b,0x4f,0xd3,0xb0,0x50, + 0xf5,0xb5,0xb6,0xe9,0x70,0x36,0x16,0x4e,0xf9,0xf6,0xc9,0x56,0x2c,0x9a,0xd8,0x34, + 0x42,0x46,0x99,0x97,0x78,0x39,0x37,0x69,0x8c,0xc2,0xbc,0x52,0x9f,0x81,0x7f,0x3a, + 0xbf,0xac,0xfe,0x95,0x8d,0xa7,0x8b,0xd2,0x15,0x16,0x7e,0xf1,0xe8,0x22,0x96,0xbf, + 0x55,0x0e,0x08,0xbe,0xcc,0x62,0xfe,0x43,0x2c,0xa3,0x88,0xfc,0xcb,0x15,0x13,0x3e, + 0x9c,0xa7,0x0d,0x63,0x6a,0x77,0x20,0xa1,0x74,0x42,0x75,0xaf,0x3a,0x4c,0x2e,0x60, + 0x9b,0x6a,0x64,0x64,0x72,0x52,0xf0,0xd3,0x14,0xcf,0x1f,0x72,0x6d,0x58,0x0e,0xec, + 0xa8,0x0c,0xa6,0xf2,0x42,0x7e,0x8b,0x91,0x85,0xc8,0x29,0x89,0xb7,0xb1,0xf2,0x87, + 0x51,0x75,0xab,0xff,0xe7,0x78,0x9f,0x20,0x3b,0xc6,0x61,0x48,0xec,0xc0,0x4a,0x92, + 0xa4,0xa5,0x3b,0xe5,0xf5,0x9d,0xda,0x58,0xfe,0x54,0x39,0x47,0xf9,0x58,0xaa,0xeb, + 0xf1,0x32,0xdc,0xb1,0xde,0x31,0x2b,0xff,0x9c,0x2e,0xe4,0xe7,0x47,0xa5,0x59,0x4c, + 0xab,0x7f,0xc6,0x05,0x0f,0xf2,0x50,0x60,0x3c,0xff,0x6a,0xd2,0x76,0x63,0x94,0x52, + 0x17,0x29,0x88,0x7b,0x2a,0x08,0x23,0x74,0x1b,0x11,0xc8,0x88,0x75,0x9f,0xdf,0xd8, + 0x98,0x1b,0xd4,0xb0,0x3f,0x23,0x18,0xa2,0xcf,0x0c,0xb1,0x6e,0xf8,0x86,0xc9,0xb4, + 0x38,0x1a,0x1f,0xf2,0xfd,0xd4,0x7c,0x61,0x98,0x0a,0x8f,0x06,0x9b,0xdd,0xa5,0x24, + 0x8f,0x17,0x9a,0x71,0x38,0xaf,0x81,0x95,0x55,0x1b,0x11,0xf9,0x79,0x16,0x75,0x22, + 0x6c,0xad,0x50,0xcf,0xaf,0xbd,0x8c,0xae,0x8b,0x33,0x21,0x7d,0xc1,0x71,0x63,0x1d, + 0xc6,0x63,0xf2,0xea,0x9c,0x51,0xab,0xfe,0x55,0x5a,0x00,0x7b,0x93,0xb5,0x2b,0x0a, + 0x2e,0x6b,0xa8,0x86,0x37,0xa0,0x76,0xd0,0xc3,0x88,0xd8,0xcb,0x49,0xa6,0x9f,0xcf, + 0xb5,0xeb,0x5f,0x53,0xd9,0xbe,0xec,0x5a,0xc3,0x17,0xc2,0x65,0x25,0xca,0x79,0x6d, + 0xb5,0x7c,0xff,0x32,0xc7,0x2f,0x3e,0x2e,0xd5,0x75,0x84,0x3d,0x0d,0xc3,0xa7,0x7a, + 0x2a,0x70,0x0a,0xc2,0xac,0x06,0x1d,0x34,0x0f,0x01,0x9f,0x38,0x2b,0x1f,0x95,0x92, + 0x78,0xfe,0xd0,0xf0,0x18,0xe4,0x29,0x7e,0x5e,0x41,0xde,0x3d,0xc4,0x6b,0xfc,0x54, + 0x68,0x77,0xb3,0xf4,0xf3,0xd8,0xc3,0x98,0x27,0x45,0x2e,0xe1,0xf8,0x85,0xa1,0xe3, + 0x74,0xfa,0x53,0x04,0xdf,0xbc,0xd5,0x11,0x5b,0x3f,0x5f,0x7c,0x58,0x8c,0x34,0x8f, + 0xac,0x41,0x23,0xc0,0xb5,0x61,0x84,0x3d,0x84,0x59,0x99,0xfc,0xa1,0xb4,0x0b,0xc3, + 0xe4,0x5a,0x5c,0x0e,0xb9,0x0b,0x23,0x02,0xb6,0xf8,0xfe,0xe5,0x6a,0x9a,0x97,0xd1, + 0x6f,0x68,0xec,0xfc,0xa8,0xba,0x62,0xdf,0x06,0x5c,0x29,0x23,0xf0,0x22,0xba,0x65, + 0x0f,0xdf,0xe5,0xa7,0x15,0x8c,0xd3,0xcf,0x63,0x84,0x1f,0x43,0xfc,0xfa,0x80,0x1e, + 0x40,0x0a,0x73,0x38,0xfe,0xfd,0xe5,0xd1,0x03,0x62,0x53,0xf0,0xf8,0xfa,0x57,0x34, + 0xff,0x5f,0xc8,0x07,0xf6,0xb6,0xe5,0x5c,0x5c,0x29,0xd5,0xcd,0x93,0xea,0x5f,0x8d, + 0x6a,0xd2,0xdf,0x07,0xf7,0x4b,0xec,0x20,0x29,0x77,0x85,0xf4,0xf0,0x44,0xfd,0x46, + 0xa9,0xa5,0x3f,0x44,0xd8,0x42,0xa3,0xd2,0x4f,0x94,0xd6,0x4d,0x30,0x4e,0xbf,0x31, + 0x2d,0x66,0xe9,0x13,0x8a,0x4e,0x44,0xcc,0x5b,0x6a,0x8a,0x97,0xb8,0x1a,0x90,0x68, + 0x30,0xa7,0xe7,0xf0,0xaf,0xee,0x69,0x8c,0xdd,0x30,0x6e,0x55,0x78,0xc6,0xde,0xb6, + 0xcc,0x76,0x7b,0xd5,0x66,0xe9,0x37,0xba,0x4b,0xce,0xd8,0xfc,0xeb,0x07,0x3c,0x41, + 0xba,0x71,0x73,0xdb,0x99,0xc4,0x01,0x76,0xc5,0x39,0x3f,0xaa,0x14,0x32,0x69,0x43, + 0x65,0x17,0x13,0x72,0xac,0x25,0x27,0xa0,0xc3,0xe2,0x5f,0x13,0xf5,0xf3,0x64,0xb9, + 0xde,0xa2,0x32,0x21,0x47,0xab,0xd8,0x73,0xed,0x99,0xa8,0x9f,0x37,0x3d,0xf1,0xc8, + 0x4e,0xfd,0x09,0x1c,0xb2,0x6c,0xe5,0x4e,0xcd,0x2c,0xfd,0x06,0xf0,0xe7,0xdc,0xe8, + 0xd3,0xe4,0x46,0xec,0xcf,0xdf,0x09,0x92,0x65,0x65,0x6e,0x07,0xc5,0x3e,0xe8,0x15, + 0xa2,0x4d,0xcc,0xf7,0xa8,0xbc,0xdc,0x96,0xd0,0xf4,0xd9,0xfc,0xeb,0x6d,0xab,0xfe, + 0x05,0x8e,0x7e,0xa3,0xcc,0x4a,0x24,0x32,0xfd,0x21,0xd4,0x29,0x3e,0x47,0xbf,0xa1, + 0x02,0xd7,0xcf,0x6f,0xcf,0xff,0xa4,0x68,0xb5,0xb6,0x5e,0xd0,0xae,0x85,0xd2,0x7a, + 0x32,0x27,0x91,0xe1,0x5f,0x6a,0x09,0xe7,0x5f,0x46,0xa9,0xa6,0xa9,0x0a,0x7b,0xd9, + 0xe4,0x10,0xc9,0xc9,0x69,0x53,0xb2,0xf9,0x97,0x2e,0x4d,0x95,0xf6,0xc1,0x9c,0xf4, + 0xfd,0x3f,0x20,0x77,0xc2,0x3a,0x9d,0x17,0xc2,0x4a,0xf5,0x75,0x42,0xa1,0x64,0xe9, + 0x37,0x2a,0x4b,0xb9,0x7e,0x23,0x81,0xfc,0x2b,0x1c,0x79,0x95,0xfe,0xe3,0x80,0xaf, + 0xc6,0x73,0x19,0xbe,0xd8,0x9c,0x7f,0x8d,0xab,0x7f,0xe1,0x32,0x0f,0xc9,0x9f,0xd0, + 0x73,0x35,0x75,0xfd,0xbe,0x3d,0x9d,0x29,0x3b,0xb7,0x63,0xe9,0xe7,0x63,0x5c,0x3f, + 0x5f,0x9f,0xf2,0xdd,0x5b,0x5e,0x43,0xdf,0x8b,0xd7,0xbf,0xbf,0xf1,0x59,0x79,0x3a, + 0x1c,0x8a,0xf3,0x8c,0xa2,0x7d,0x7e,0x14,0x72,0x2b,0x1e,0xa2,0xaf,0x76,0xff,0x0f, + 0xb6,0xd0,0xd2,0x9e,0x11,0xa2,0x1a,0xbf,0xa0,0x55,0x66,0xc1,0x6a,0x5b,0xbf,0xe1, + 0x17,0xfa,0xf9,0x76,0x64,0x5b,0xa1,0xc6,0x9f,0x92,0x2a,0xb6,0xd5,0xfa,0x0e,0xd1, + 0xf9,0x55,0xa4,0xcf,0xce,0xcf,0x6f,0x60,0xf9,0x8d,0xb4,0x67,0x21,0x79,0x40,0xed, + 0xe4,0xb9,0x53,0x77,0x94,0x55,0x2b,0x0c,0x24,0x62,0x6f,0x8b,0x79,0xdf,0x2e,0x71, + 0xce,0xd8,0xea,0x83,0xce,0x59,0xec,0x30,0x25,0xe6,0xe2,0x56,0xa0,0xcf,0xfc,0xb1, + 0xe1,0x73,0xf4,0x1b,0x09,0x6d,0x48,0x39,0x47,0xea,0xe2,0x1b,0x93,0x45,0x1f,0xda, + 0xc3,0xb9,0x9f,0x9d,0xc2,0xc7,0x36,0x0d,0x0d,0x88,0xf5,0xd5,0x22,0xea,0x5f,0x74, + 0x49,0xbf,0xdc,0x5c,0xf9,0x1e,0x61,0xb0,0x25,0x2f,0x8c,0x1c,0x85,0x7a,0x3d,0x7f, + 0xb8,0xc8,0xd2,0xe0,0x59,0xf5,0xaf,0x64,0xd5,0x53,0x97,0xe5,0xa1,0xab,0xe4,0x65, + 0x94,0x59,0xcc,0x3f,0x2b,0x97,0x65,0xf4,0xf3,0x42,0x7f,0x98,0xb8,0xfe,0x29,0xb2, + 0x82,0x6f,0x16,0xb3,0xdb,0xb0,0xcd,0x47,0x16,0xff,0x72,0x17,0x7b,0x8d,0xbd,0xb0, + 0xb2,0xe5,0xe1,0xb0,0xbb,0x32,0x86,0x9c,0xba,0xdf,0x13,0x46,0xe7,0xd9,0x36,0x33, + 0xd8,0xe4,0x9e,0x6b,0xaf,0x2f,0x76,0x1f,0xec,0x6a,0x7b,0xfe,0x3e,0xb9,0x59,0x3d, + 0xaa,0xcc,0x33,0x37,0x9e,0x6a,0xab,0x84,0x43,0xa1,0x3a,0xcd,0x9b,0x6c,0x4b,0x8b, + 0xf5,0xb5,0xbd,0x64,0x34,0xfe,0xd2,0xac,0xfa,0x0e,0xdf,0x9e,0xa2,0x54,0x7c,0x0c, + 0xa6,0xff,0xc6,0x77,0xaa,0x73,0x84,0x8e,0x85,0xea,0x01,0x39,0xa3,0x73,0xfe,0x86, + 0xc5,0x8e,0xbb,0x91,0x7f,0x7d,0x82,0xf1,0x3c,0x2f,0x84,0x7d,0x6c,0xe1,0x97,0xa5, + 0xdf,0x80,0x21,0x51,0xff,0x62,0xdb,0xbe,0x3a,0x69,0x40,0x18,0xe2,0x4a,0x64,0x70, + 0x92,0xfe,0x90,0x71,0xb4,0x0a,0x41,0xc4,0x76,0xd8,0xf9,0xc3,0xc9,0xfa,0x8d,0x47, + 0xe8,0xcc,0x71,0x85,0xa7,0x11,0xab,0xee,0x59,0x9c,0xd1,0x0d,0xc2,0x69,0x84,0x7e, + 0x47,0x4b,0xe3,0x41,0xfc,0x12,0xeb,0xe2,0x04,0x64,0xe9,0x0f,0x3f,0x13,0xf4,0xc4, + 0x29,0x84,0x8d,0xc4,0x78,0x9b,0x6c,0xfd,0xe1,0x24,0xc3,0xce,0x1f,0x2a,0x41,0xc8, + 0xca,0xe5,0xd6,0x65,0xf7,0x47,0xee,0xe2,0xbd,0x41,0x7c,0x5f,0x92,0x19,0xd7,0x44, + 0x21,0xa2,0xa5,0xdf,0x88,0x49,0x59,0x25,0x24,0x91,0x94,0x63,0x46,0xa2,0xea,0x84, + 0xbc,0x9a,0x58,0xfa,0xf9,0x15,0x50,0xa0,0x59,0xb2,0xc3,0x23,0xe6,0x69,0x2d,0x98, + 0xc6,0x45,0x74,0x18,0x4e,0x27,0xf8,0x15,0x1b,0xbf,0xfe,0x8f,0x17,0x84,0xde,0xe6, + 0x24,0x1f,0x4e,0x5d,0x96,0xae,0xf2,0xe4,0x78,0xfd,0x61,0x6d,0xda,0x6b,0x0f,0xc7, + 0x23,0x0c,0x76,0xa5,0xe1,0x7d,0x47,0xbf,0x21,0x59,0x3b,0x4d,0xde,0x55,0x9c,0x44, + 0xe2,0x3e,0xb8,0x9a,0x5d,0xc9,0xd6,0x1f,0xb6,0xb3,0xdd,0x5e,0xdf,0x3a,0x6e,0xe9, + 0x0f,0x23,0xc7,0x8b,0xf7,0xb5,0x7f,0x0f,0xf1,0xcb,0xe6,0xd4,0x2b,0x2c,0x7d,0x94, + 0x6a,0xe7,0xe7,0xad,0xb1,0x57,0x32,0x20,0x9b,0xa0,0x3f,0x0c,0x5a,0x31,0x6d,0x8b, + 0xcf,0x36,0xaa,0x26,0xe9,0x0f,0x27,0xd7,0xbf,0x32,0xf8,0xd5,0x31,0x59,0x7f,0x98, + 0x9b,0xc9,0x1f,0x7e,0x89,0xfe,0x30,0x3b,0x37,0x68,0xe3,0x97,0x32,0x41,0x7f,0x98, + 0x97,0xd5,0x66,0xbf,0x9d,0x9f,0xcf,0xd6,0x1f,0x92,0x6a,0x6b,0xff,0x97,0x22,0xf0, + 0x4b,0xcc,0x7b,0xb7,0xba,0xcc,0x18,0xd7,0xd5,0x07,0x58,0x72,0xcf,0xc9,0x1f,0xf2, + 0xef,0xda,0x3a,0xed,0x4c,0xa6,0xcf,0xe7,0xc9,0xf8,0xe2,0x9d,0x85,0x5f,0x1d,0xec, + 0xfc,0x28,0x8e,0x5f,0x18,0x6f,0x9c,0x73,0x12,0x77,0xe2,0x4a,0xc0,0xd1,0x1f,0xea, + 0x16,0x5a,0xe9,0x4e,0x22,0x91,0x74,0x48,0xdc,0x70,0xf6,0x2f,0x0f,0xd0,0x16,0x91, + 0x3f,0xcc,0xea,0xbc,0x85,0x5f,0x11,0x47,0xbf,0x21,0x3d,0x31,0x5e,0x72,0x19,0x71, + 0x6a,0x7f,0x8b,0x2d,0x5f,0xb7,0xa5,0x1d,0x0e,0xb8,0x78,0x3d,0xae,0x82,0x91,0x2c, + 0x81,0x4d,0x16,0x7e,0xad,0xc8,0xe8,0xe7,0x85,0x46,0xd1,0x83,0xc3,0x89,0x8f,0x1b, + 0x97,0x67,0xbd,0xc5,0xad,0xb4,0xc4,0x97,0xd7,0x34,0x33,0xf5,0x2f,0xe5,0x23,0x06, + 0x5b,0x3a,0x19,0x54,0xac,0xb4,0xe1,0x88,0xfa,0x9c,0xb8,0x62,0x71,0x22,0x96,0x3f, + 0x9c,0x37,0x61,0x59,0xa5,0x26,0xe4,0x0f,0xcb,0xa4,0xa9,0xf0,0x8b,0xcc,0x6b,0x5c, + 0x65,0xca,0xcd,0x4c,0x41,0x2e,0xae,0x38,0xf5,0x2f,0x27,0x5b,0x78,0xdc,0x36,0xde, + 0xb6,0x8c,0xf2,0x83,0xe2,0xb0,0x58,0xf5,0xd2,0x17,0x8c,0x8c,0x26,0x59,0x18,0x83, + 0x0e,0x7e,0x39,0xe7,0x1f,0xda,0xd9,0xc2,0x17,0x8d,0xb1,0x38,0x77,0x8c,0x5f,0xc0, + 0xb9,0xf8,0xb5,0xe9,0xfc,0x6e,0x62,0xe3,0x17,0xd7,0x47,0x61,0x0f,0xbf,0xc0,0x90, + 0x8f,0x77,0xe3,0x47,0xac,0x3f,0x09,0x5c,0x71,0x3f,0xca,0xb5,0xce,0x8f,0xda,0x6c, + 0x9d,0x7f,0xe8,0x39,0x49,0xd0,0xe0,0xa5,0x3a,0x74,0x05,0xfb,0x34,0x76,0x52,0x96, + 0xcd,0xbf,0xfe,0xb6,0x78,0xc8,0xd2,0x47,0xb1,0x94,0x29,0x15,0x63,0xe7,0x19,0x7b, + 0x08,0x05,0x2c,0xfd,0xfc,0x93,0x25,0x2f,0xc0,0x8f,0xc4,0xae,0xd5,0xdd,0xfc,0x6c, + 0x0d,0xec,0xea,0xae,0x62,0x46,0xb2,0x2a,0x92,0xc4,0x3a,0xff,0x30,0x0e,0x19,0x17, + 0x27,0x8d,0x1b,0xd7,0xd2,0xa4,0xfc,0xb8,0x58,0x5f,0x54,0x1b,0xd5,0x8e,0x5a,0x3e, + 0x53,0x75,0x42,0x7d,0xcb,0xb0,0xea,0x5f,0x3d,0x7c,0xff,0xb2,0xd0,0x1f,0x3a,0x69, + 0x43,0x78,0x5e,0x12,0xfa,0x84,0x8c,0x7e,0xa3,0x73,0x82,0x66,0x60,0x90,0x1b,0xee, + 0xa4,0x5d,0x83,0x66,0xfa,0x79,0x11,0xe1,0xb7,0x1e,0x66,0x42,0xc4,0x3e,0xc4,0x2f, + 0x9c,0x53,0xdd,0x6b,0xe6,0x85,0xed,0xf5,0x45,0xbd,0x2b,0x8d,0x43,0x6c,0x4b,0xf2, + 0x3e,0xf9,0x13,0x33,0xd3,0x67,0xa3,0xee,0xcd,0x82,0xa7,0x1d,0xfd,0xbc,0xa8,0x7f, + 0x1d,0xf0,0x75,0x15,0x0d,0xf5,0xf3,0x42,0xd8,0x49,0xd6,0xe7,0x15,0xdc,0xc8,0xd2, + 0x6f,0x70,0x75,0x4d,0xb7,0x67,0x17,0x1a,0x75,0xe9,0xaa,0x11,0x9c,0x2f,0x7e,0x65, + 0x44,0x6e,0x56,0x1c,0xfd,0x46,0x27,0xa2,0x95,0x1a,0x2a,0x5f,0x29,0x8c,0x6e,0x32, + 0xa4,0x58,0x86,0x9e,0xe1,0x5f,0xac,0xcf,0x6a,0x32,0xa7,0x43,0x6b,0x83,0x95,0xac, + 0xfe,0x75,0x90,0x5f,0x41,0x5f,0x17,0xc8,0xe0,0x17,0x1b,0xfb,0xd6,0x4d,0x05,0x2b, + 0x75,0x66,0xf8,0x93,0xd8,0x86,0x19,0x79,0x49,0x12,0xb2,0x78,0x53,0x89,0x50,0x1b, + 0x7a,0x43,0xf2,0x36,0x6e,0x14,0x24,0x1b,0x06,0xb9,0x91,0x9f,0xcc,0xb5,0xf6,0x5f, + 0xa4,0xa5,0x17,0x08,0x7b,0xf2,0x73,0x46,0x3c,0xc3,0xdc,0x08,0xda,0x73,0x51,0x3d, + 0xec,0x99,0xa4,0x9f,0xf7,0x54,0x72,0x4e,0xcd,0x53,0xc1,0x16,0xff,0xea,0xb7,0xf3, + 0x87,0x5e,0xbe,0x53,0xb2,0x33,0x1e,0xf9,0x7a,0xf4,0x79,0x51,0x3b,0x1e,0x84,0x4e, + 0xf1,0x46,0x4d,0xd4,0xcf,0x2f,0x24,0x7f,0xcb,0x5d,0x77,0x03,0xbe,0x63,0x92,0x45, + 0xc4,0x86,0x45,0x6d,0x2b,0x29,0xf0,0x6b,0x00,0xc3,0xc2,0xef,0x58,0x42,0x8e,0xc0, + 0x05,0x69,0x1d,0xcd,0xe7,0xb5,0x24,0xbb,0xfe,0xe5,0x35,0xc4,0xfe,0xaf,0xce,0x1b, + 0x12,0xa7,0x61,0x21,0x83,0xad,0x14,0xbc,0x21,0xce,0x8f,0xb2,0xeb,0x5f,0xd3,0x5e, + 0xd0,0x18,0x6c,0x6d,0xec,0x2f,0xe7,0x40,0xc6,0x68,0x57,0xca,0xc1,0x2f,0x65,0x1c, + 0x7e,0x05,0x93,0x18,0xee,0x1e,0xb2,0x71,0xf9,0x65,0x1a,0xce,0xd2,0x6f,0xa4,0x70, + 0x7d,0x5d,0x25,0xf0,0x4b,0x21,0xbc,0xf0,0xdd,0x4c,0x46,0x09,0x23,0x62,0xac,0xfe, + 0x25,0xd6,0x29,0x85,0xc7,0x54,0x71,0xe6,0xb0,0x7f,0x8a,0x64,0x09,0x39,0xde,0x11, + 0x44,0xcc,0xa9,0x7f,0xd9,0xfb,0xbf,0x3a,0xf6,0xdc,0x10,0xb4,0x29,0xe7,0x20,0xdb, + 0x9c,0x3e,0xae,0xfe,0x25,0xf0,0xcb,0xbb,0x4b,0x5e,0xc8,0x8f,0x8d,0xf2,0xb1,0x83, + 0x7c,0x0f,0x42,0x97,0xd0,0xcf,0x37,0x4f,0xc4,0x2f,0x6a,0x89,0xd6,0x6c,0xfd,0xe1, + 0xc4,0xf3,0xa3,0x7c,0x9b,0xe5,0x0a,0x6a,0x0b,0x39,0x6c,0x5e,0x90,0xd1,0x6f,0x08, + 0xb7,0xbc,0x35,0x30,0x93,0x0b,0x39,0xe4,0x2c,0x6d,0xc6,0x24,0xfd,0xa1,0x3b,0x4b, + 0xc8,0x61,0x19,0x47,0x26,0xea,0x0f,0xdd,0x0a,0x6d,0x99,0x80,0x05,0x13,0xeb,0x5f, + 0x2e,0xb9,0xcc,0xb0,0xf8,0xc5,0x09,0xdb,0x98,0xa8,0x9f,0xef,0x97,0xcf,0x18,0x42, + 0x64,0xd8,0xe0,0x20,0x9a,0xcd,0xad,0x5c,0x67,0x38,0x5a,0xe5,0xf7,0xcb,0x4f,0xab, + 0xcc,0x08,0xc6,0xe5,0xdf,0xc1,0x6b,0x02,0xbf,0xec,0xf3,0xa3,0x90,0x9f,0x32,0xfc, + 0xea,0x6c,0x25,0x09,0x6e,0xb0,0xfd,0xcb,0xad,0x02,0xd1,0xe4,0x82,0x1c,0x4b,0x1f, + 0x25,0x7a,0x98,0xa7,0xad,0x5f,0xc3,0x0d,0x86,0xb9,0x5b,0xac,0x3e,0xfb,0x33,0xfa, + 0x43,0x36,0xd2,0x4e,0x7f,0x60,0x27,0xb1,0xf8,0x69,0x5f,0xc2,0x1a,0x7b,0x8e,0x93, + 0x3f,0xe4,0x68,0x95,0x1f,0x2f,0xfa,0x39,0x7f,0xbc,0x5e,0xd6,0x1f,0xeb,0x39,0x5b, + 0xe7,0x47,0xad,0x90,0x76,0x12,0x9b,0x76,0x51,0x66,0xcc,0x61,0xe5,0xbc,0xf1,0xf5, + 0xaf,0x0c,0x7e,0x15,0xe9,0xad,0x29,0x1b,0xbf,0x52,0xa4,0x6e,0x5c,0xfd,0x4b,0xd5, + 0x18,0x5a,0xc9,0xef,0x93,0x6b,0x2a,0xd7,0x43,0x90,0x4e,0x61,0xfb,0x97,0xd7,0x5b, + 0xf8,0x35,0xbe,0xfe,0xe5,0x09,0xbb,0x0b,0x94,0x36,0xc9,0x02,0xb2,0x87,0x14,0xae, + 0xe8,0x18,0xaf,0x9f,0xef,0xf1,0x34,0x91,0x52,0x21,0x4c,0x42,0x20,0x33,0x7f,0x0a, + 0xf9,0x59,0xf5,0xaf,0x5d,0xce,0xfe,0x2f,0xb9,0x00,0x98,0x90,0x83,0x69,0xda,0xc9, + 0xb7,0xed,0xfa,0x97,0xf0,0xab,0xd3,0x76,0x0b,0xc9,0x53,0x1c,0x23,0x73,0xcb,0x67, + 0x7e,0x92,0xb0,0x54,0x5e,0xbd,0xf6,0xf9,0x87,0x9f,0x8a,0xd3,0xf3,0xba,0xcb,0x67, + 0x1b,0x47,0x45,0x18,0x7f,0xc1,0x78,0xb9,0x3d,0x3c,0xe0,0x5b,0xe8,0xb1,0xce,0x2d, + 0x64,0xfa,0xf9,0x97,0x68,0xd9,0x90,0xe7,0x2f,0x88,0x1f,0xd6,0x91,0xaa,0x21,0x4f, + 0x0d,0x39,0x4e,0xdf,0x48,0x6c,0x1b,0xf4,0xd4,0xb8,0x67,0x3b,0xe7,0x47,0x19,0x2f, + 0x49,0x65,0xa9,0x29,0xcd,0x44,0xa5,0xbc,0xcf,0xf7,0x90,0x51,0xe4,0x5f,0x33,0x18, + 0xff,0x72,0xce,0x3f,0xb4,0x64,0xf3,0x5b,0x89,0x44,0xac,0x50,0xff,0x88,0xfe,0x90, + 0xd8,0x44,0xa0,0x3a,0xf5,0x2f,0x95,0x95,0xef,0x71,0x5d,0x54,0x19,0xd6,0x7a,0x1f, + 0x6b,0x39,0x04,0x4c,0xf3,0xef,0x99,0x3d,0x61,0xff,0x57,0xfc,0xeb,0x83,0xf0,0x17, + 0x99,0x58,0xbd,0x26,0xab,0xfe,0xe5,0xe8,0x0f,0xcf,0xc8,0xc5,0xc0,0x80,0xec,0xf2, + 0x61,0xe2,0x68,0x06,0xac,0xfa,0x17,0xb5,0xeb,0x5f,0x5b,0xe4,0xbb,0x26,0x83,0xd4, + 0x78,0xfd,0xa1,0x3b,0xd1,0x3a,0x7b,0x52,0x9b,0x6c,0xfd,0x21,0x3b,0x0a,0x0c,0xb6, + 0x1b,0xbd,0x6d,0x24,0xd8,0xcb,0xf6,0x52,0xc1,0xde,0x90,0xd0,0x1f,0x3a,0xe7,0x47, + 0xd1,0x73,0x7a,0xdd,0xc1,0x82,0x32,0x59,0xa7,0x38,0xae,0x63,0x9e,0x3d,0xf2,0x68, + 0x07,0xdb,0x11,0xb6,0xb4,0x6b,0x87,0x29,0x83,0x85,0x5f,0x2a,0xaf,0xfe,0xf7,0xca, + 0x49,0x73,0x4c,0xa9,0x3f,0xe8,0x3b,0x5d,0x7e,0xd8,0x18,0x8b,0xa1,0x63,0x3c,0x25, + 0x0f,0x4a,0x0e,0x7e,0xbd,0x27,0xe2,0x8d,0x5a,0xf8,0x8c,0xe2,0xb2,0xa2,0x3c,0x7f, + 0x58,0x3f,0x6e,0xff,0xd7,0x10,0x87,0x2d,0xec,0x61,0x05,0xeb,0x33,0x45,0x63,0xd4, + 0xf8,0xa5,0x35,0x2e,0x87,0x7f,0x69,0x0f,0xd9,0xb1,0xc4,0x0e,0x09,0x97,0x15,0x10, + 0x81,0x68,0x53,0x32,0xfc,0xeb,0xf6,0x0d,0xd6,0x90,0xdd,0x15,0x84,0xdf,0x67,0x1b, + 0x61,0x27,0xc4,0x4e,0xe4,0x5f,0x1c,0x65,0x42,0x72,0xb5,0x81,0xaf,0xd6,0x4a,0xdf, + 0x7a,0xc9,0xd1,0xcf,0x4f,0xe6,0x5f,0x7d,0xcc,0xe8,0x15,0x3c,0x85,0x8c,0xaf,0x7f, + 0x65,0xf4,0x87,0xfa,0xa1,0x52,0x1e,0xea,0x1f,0x86,0x73,0x6a,0x5d,0x6f,0x36,0xff, + 0xaa,0x32,0xac,0x29,0x18,0x80,0x4e,0xa3,0xba,0x5b,0x7d,0x1c,0xe7,0x14,0x79,0xe5, + 0x29,0x24,0x98,0xa7,0xc4,0x63,0x46,0xfc,0x32,0xac,0x57,0xeb,0x15,0x36,0x9c,0x10, + 0xbe,0x6a,0xaf,0xc5,0x70,0xc5,0x9d,0xf4,0x2c,0x6c,0x1d,0xc9,0xec,0xaf,0x5c,0x27, + 0xf6,0x2f,0x1f,0x4f,0xac,0xa3,0xc1,0x98,0x7a,0x07,0xe3,0x5f,0xad,0xfc,0xfc,0xc3, + 0x63,0x94,0xcf,0x69,0x54,0x0d,0x1a,0xbf,0xe5,0xf8,0x55,0xbe,0x9f,0xbe,0x0c,0xb5, + 0x89,0x02,0xb6,0xff,0xeb,0x74,0x47,0xad,0x99,0x5b,0xd3,0x36,0xfe,0xfc,0x79,0xa6, + 0x71,0x1d,0xcd,0x19,0x13,0x42,0xdf,0xf3,0xb1,0x89,0xfc,0xeb,0x53,0xb0,0xf4,0x87, + 0x3f,0x67,0xe7,0x93,0x80,0xb7,0x43,0xfe,0x35,0x65,0x85,0xb0,0x25,0xdd,0x72,0xc0, + 0xe6,0x5f,0x2f,0x64,0xf4,0x87,0x08,0x5b,0xa0,0xf6,0xb3,0xf3,0x76,0x08,0x2f,0x84, + 0x39,0xfb,0x97,0x5f,0x14,0x7d,0x1e,0x21,0xff,0x86,0x86,0x94,0x76,0x8f,0x90,0xc7, + 0xe0,0x17,0x74,0xc6,0x09,0x75,0x35,0x49,0x66,0xf0,0xcb,0x82,0xad,0x25,0xa4,0x0d, + 0xb6,0xbf,0x3e,0x9b,0xe5,0x0f,0x77,0xc0,0x4e,0x56,0x08,0xf3,0x67,0xf8,0xd7,0x41, + 0xbb,0x94,0xb0,0x1e,0xe6,0xc5,0x0b,0xd2,0xe5,0xbb,0xe0,0x23,0x58,0xc0,0x84,0x1c, + 0x93,0xf5,0xf3,0xc2,0xe9,0xe5,0x31,0x5f,0xb7,0x95,0x9d,0x9b,0x9a,0xd1,0xcf,0x37, + 0x4d,0xe0,0x5f,0x1d,0xb6,0xe1,0xb9,0x08,0xff,0x0a,0xfc,0x8e,0xd7,0xbf,0xa6,0x6d, + 0xb1,0x0c,0xcf,0x96,0x0c,0xff,0x9a,0x99,0xd1,0x6f,0xb0,0xfa,0xd7,0xdf,0x6e,0xb1, + 0x0c,0x4f,0xbc,0xd5,0xd6,0x1f,0x66,0xf1,0x2f,0xba,0x07,0xaa,0xa3,0x6e,0x3f,0x37, + 0xc6,0xe5,0x0f,0x91,0x7f,0x75,0x0b,0xfd,0x7c,0x8f,0x31,0xdc,0x54,0x5b,0xbc,0xde, + 0x36,0x98,0x7e,0x9e,0x8c,0xc7,0xaf,0x38,0xc7,0xaf,0xfa,0xc6,0xfc,0xdf,0x14,0x0d, + 0x18,0x36,0x7e,0xe5,0xf2,0xb9,0x50,0x5d,0x0e,0xa2,0xcd,0x48,0x88,0x83,0x9b,0xda, + 0x2a,0xf8,0x09,0x4e,0x78,0xe5,0x7d,0xe7,0xfc,0x5e,0x7d,0x50,0xe8,0xe7,0x59,0xfd, + 0xab,0x1a,0x3a,0x7e,0xee,0xd6,0x15,0x66,0xe4,0xf5,0x66,0x9d,0x3f,0xdf,0x61,0xe9, + 0x0f,0xb7,0xc0,0xe3,0x6a,0x55,0xb3,0xda,0xd4,0x5a,0xa2,0xa3,0x61,0x78,0x9a,0x1c, + 0xfd,0xbc,0xa5,0x3f,0x44,0x5c,0x7e,0x0a,0x7e,0x05,0x73,0xf0,0x3d,0xcc,0x99,0xcf, + 0x4f,0xd3,0xca,0xeb,0x77,0xf2,0x87,0x5b,0x1c,0x6d,0xfc,0x4e,0xd6,0x0d,0x23,0xb8, + 0x45,0xe2,0xfd,0xc1,0x2b,0x52,0xd6,0xfe,0x65,0x71,0x45,0x6e,0xb4,0xf6,0x2f,0x67, + 0xf2,0x87,0x07,0x6d,0xfe,0xb5,0x9d,0x9f,0xf3,0xe6,0x6b,0x95,0x99,0xa0,0x69,0x1e, + 0x82,0x89,0x2c,0x94,0x4d,0x5e,0xb3,0xcc,0x2d,0x6a,0x49,0x95,0xca,0x42,0x9e,0x49, + 0xf6,0xd8,0xdb,0xbe,0x78,0xfd,0xeb,0x6d,0x8a,0x46,0x9a,0x64,0x9d,0x1f,0x55,0xce, + 0xde,0xb1,0xf9,0x50,0x00,0x6d,0x94,0xd7,0xbf,0xf0,0xad,0x23,0xdc,0x58,0xaf,0x5b, + 0xfc,0x6b,0xba,0x0d,0x5b,0x85,0xd0,0x6e,0x2e,0xd3,0xd4,0x46,0x62,0xc2,0x96,0x8e, + 0xb2,0x90,0xba,0x84,0x74,0x38,0xfa,0x43,0x71,0xec,0xe1,0x6a,0x04,0x93,0x23,0x74, + 0x6f,0x22,0x38,0xe8,0x79,0x1b,0x8e,0xd0,0x79,0xcc,0x58,0x6f,0xe1,0xd7,0xa5,0x6c, + 0xff,0xd7,0x74,0x21,0x2f,0x17,0xc3,0xc1,0xb1,0x5b,0xc2,0xd1,0x88,0xcd,0xbf,0xbe, + 0x30,0xb8,0x1e,0xfb,0x43,0xf9,0x73,0xe3,0x93,0x96,0xab,0x62,0xca,0x5b,0x72,0x35, + 0xbc,0x46,0xeb,0x97,0x7b,0xdf,0x72,0xf2,0x87,0x62,0xff,0xd7,0x60,0x67,0x25,0xf9, + 0x88,0xae,0x45,0x5c,0x56,0xff,0x96,0xf8,0xcd,0x9f,0x27,0xe7,0xec,0x42,0xc3,0xd1, + 0xb4,0xc7,0x29,0xdf,0xbf,0x7c,0x17,0x19,0xd6,0x77,0x42,0x95,0xa6,0x46,0x48,0x94, + 0xb6,0xc3,0x1c,0x55,0x8d,0x92,0x01,0xf1,0x0c,0x9d,0xfd,0xcb,0x3a,0xaf,0xfd,0x61, + 0xf0,0x3f,0xbf,0x75,0xb9,0x5a,0x2e,0x32,0x1e,0xc7,0x26,0xec,0x5f,0x4e,0xca,0x9f, + 0xaa,0xbf,0x64,0x81,0x7d,0xb2,0x68,0x39,0xf7,0x00,0xd1,0x64,0xf9,0xe0,0xc4,0xfd, + 0xcb,0x82,0x02,0xeb,0x3e,0x55,0xde,0xc5,0x17,0x5a,0x3d,0xcd,0x3a,0xbf,0xd7,0xf6, + 0x99,0xc7,0xe0,0x38,0xe1,0x0b,0x36,0x64,0x3c,0x88,0x2d,0x7c,0xe9,0x72,0x6b,0xff, + 0x72,0x4f,0x46,0x7f,0x28,0x42,0xbe,0xce,0x38,0x09,0x5a,0xb1,0xdf,0x2d,0xb6,0xfe, + 0x50,0xa9,0x14,0x6d,0x12,0xd8,0xc6,0x4a,0xcb,0xef,0x84,0x27,0xec,0x18,0xd2,0x5a, + 0x5f,0xbc,0xe6,0x92,0xc2,0x71,0xa5,0x62,0xad,0x24,0x48,0x3b,0xf5,0xb5,0x1d,0x81, + 0xed,0x52,0xb0,0x55,0xae,0x88,0x5b,0xfc,0xcb,0x50,0x63,0xed,0xe7,0x08,0x7a,0xe3, + 0x6d,0x18,0xd3,0x1e,0x63,0x87,0x7b,0xaf,0xf5,0x24,0xe8,0xa0,0x56,0xa7,0xfa,0xd6, + 0x96,0x3b,0xfc,0xcb,0xda,0xff,0xb5,0x4d,0x1e,0xa2,0x63,0x70,0xf9,0x41,0x5f,0x57, + 0xdb,0x8f,0xe1,0x1d,0x44,0xb4,0x8d,0x5d,0x45,0x93,0xf4,0xf3,0x77,0x3b,0xc4,0xf9, + 0x7d,0x72,0x94,0x45,0x20,0x23,0xf2,0xb0,0xa5,0x1b,0xb4,0xf5,0xf3,0xdd,0x60,0x1b, + 0xd8,0xd5,0x4e,0x98,0xcd,0x8d,0x1c,0x9b,0x7f,0xa9,0xec,0xb7,0x00,0x6e,0x0c,0x19, + 0x68,0x08,0xa7,0x97,0x06,0x2b,0x56,0x7f,0x7f,0x5c,0xfd,0x8b,0x43,0xb6,0xe6,0x40, + 0x76,0xa7,0xd0,0x6f,0x0c,0x5b,0xbc,0xa9,0x64,0x72,0xba,0xef,0x65,0x7e,0x6e,0xe1, + 0x1f,0xdf,0xbf,0x7c,0xfa,0x8f,0xec,0x5f,0xb6,0x8d,0x13,0xfc,0x20,0xc4,0x0c,0x7e, + 0x1d,0x63,0x5a,0x1a,0x71,0xfe,0x86,0x08,0x21,0x7c,0x9c,0x7f,0xd1,0x40,0x96,0xfe, + 0x70,0xd0,0xc9,0x1f,0xe6,0x38,0xf9,0x8d,0x57,0xe9,0x43,0x54,0xcf,0xd2,0x1f,0x22, + 0xff,0xb2,0xd4,0x47,0x77,0xf1,0x5c,0xdc,0x20,0x3b,0x94,0x89,0xae,0xa3,0xcb,0xf0, + 0x4a,0x8e,0xc3,0xbf,0x0a,0xde,0xdc,0x0b,0xb5,0x83,0x4c,0x3f,0x6f,0xb2,0x83,0xa4, + 0x3c,0x0b,0xe5,0xfd,0x15,0xef,0x74,0x24,0x07,0xb3,0xf4,0x87,0xd3,0x76,0x73,0xda, + 0x75,0x39,0x8e,0x4b,0xe1,0xfc,0x6b,0x0f,0x2e,0x99,0x73,0x96,0x91,0xcd,0xbf,0xd8, + 0xfe,0x65,0x8f,0xf8,0x81,0x98,0xdc,0xcc,0x00,0x17,0x65,0xf1,0x2f,0x2b,0xbb,0x92, + 0xa5,0x9f,0xb7,0xf5,0x87,0x39,0x86,0x78,0xe7,0x99,0xfe,0xf0,0x7b,0x2c,0x4c,0xfd, + 0x0e,0x3b,0xc8,0x37,0x2d,0xaf,0x46,0x20,0x1b,0xaf,0x3f,0x44,0xfc,0xb2,0xa7,0x72, + 0x89,0xb5,0xd1,0x32,0xf0,0xe9,0x24,0xfd,0xa1,0xb3,0xff,0x6b,0x85,0x6d,0x9c,0x35, + 0x85,0x41,0x26,0xe7,0x0f,0x9d,0x9f,0x4d,0x49,0xb3,0x83,0x6e,0x04,0xff,0x12,0x7e, + 0x5e,0x1b,0x90,0xc6,0xe1,0x17,0x13,0x78,0x4b,0x07,0xec,0xfd,0x5f,0xba,0x8d,0x5f, + 0x0f,0x67,0xe7,0x06,0xf9,0x01,0x11,0x2d,0x46,0x80,0x15,0x91,0xd3,0xd2,0x04,0xfe, + 0x95,0x49,0x1b,0x0e,0x11,0xeb,0xfc,0x8d,0x49,0xfc,0xcb,0x92,0xf0,0xb9,0x99,0x71, + 0x3f,0x24,0x26,0xf0,0xaf,0xee,0xec,0xb4,0x98,0x87,0xf1,0xaf,0xf5,0x4d,0x4c,0x9f, + 0x90,0xfb,0xa9,0x88,0x0f,0x19,0x7e,0x4d,0xdc,0x0b,0xcc,0xf4,0xf3,0x02,0xbf,0x2c, + 0x4c,0xb1,0xf6,0x7f,0x6d,0xec,0x97,0x2b,0x2c,0xb2,0xe6,0x99,0x6f,0x9c,0xd7,0xf8, + 0xb8,0xf6,0xbb,0x1c,0xfe,0x25,0xd2,0x86,0x6e,0x3d,0xdb,0x08,0x67,0xd7,0xbf,0x1c, + 0xfd,0x7c,0x26,0x7f,0x98,0x43,0xf7,0x08,0xcd,0xc9,0xeb,0x62,0x9d,0x66,0xed,0xff, + 0x72,0x1e,0x02,0x43,0xf3,0xed,0x17,0xd7,0x1f,0x56,0x64,0x8c,0x93,0x96,0x7e,0x1e, + 0x6c,0xfe,0x35,0x3e,0x96,0xf0,0xd9,0xba,0xca,0x8b,0xf1,0xaf,0xec,0xfc,0x61,0x4a, + 0x15,0xfa,0x8d,0xec,0xfd,0x5f,0x22,0x7f,0xc8,0xf5,0xf3,0x68,0x9c,0x55,0x1f,0xec, + 0x09,0x5c,0x44,0x7f,0xf8,0x48,0x56,0xfe,0xf0,0x28,0x6d,0xd3,0x62,0xe6,0x45,0xf6, + 0x7f,0x89,0xd7,0x98,0x6f,0x5b,0x7e,0x0f,0xd6,0x88,0x7c,0xc2,0x44,0xfe,0x65,0xe7, + 0x0f,0xa7,0xac,0x96,0x2f,0x20,0x90,0xed,0xc9,0xd6,0x1f,0x4e,0x9b,0xec,0x13,0x46, + 0x59,0xe7,0x59,0x12,0x3e,0xc3,0xbf,0x8c,0x73,0x6c,0x1b,0x51,0xb7,0xfc,0x29,0xdf, + 0xc8,0xec,0x3b,0x2b,0x7f,0xc1,0x70,0x30,0x5b,0x7f,0x58,0xf8,0x20,0xdd,0xb7,0x9d, + 0xe9,0xe7,0xf1,0x8d,0xda,0x27,0x0a,0x58,0x6f,0x42,0x6b,0x02,0x7d,0x42,0x8d,0xfc, + 0x64,0xd6,0xf9,0xbd,0x7a,0x55,0xcf,0x8d,0x5c,0x3f,0xcf,0x80,0x6c,0x15,0x39,0x06, + 0x3f,0xd7,0xcb,0xcc,0x8c,0xfe,0x50,0xcf,0x9c,0xbf,0x61,0x1f,0xdb,0x8b,0x71,0xd4, + 0x76,0xe1,0x33,0x3b,0xb2,0xcf,0xef,0xe5,0x27,0xc9,0x33,0xd9,0x21,0xef,0xf3,0xef, + 0x31,0x32,0x67,0xfa,0x8d,0x89,0xfb,0xbf,0xb2,0xc7,0xf5,0x01,0xfc,0x99,0x30,0x12, + 0xe3,0xf6,0x2f,0xf7,0x64,0xfb,0xcc,0x33,0xca,0x85,0xf1,0xfc,0xcb,0xc1,0xaf,0x00, + 0x2b,0xd9,0x70,0xff,0xfc,0x7b,0xf6,0x42,0x66,0xf3,0x2f,0x29,0xab,0xe6,0x62,0x51, + 0x8f,0x4f,0xf5,0xe7,0xec,0xfc,0xa1,0xb5,0xbe,0xbc,0x74,0xaf,0xca,0xf4,0xf3,0xa2, + 0x84,0xd4,0xdf,0x19,0xda,0xfe,0x0a,0xf0,0xbd,0x54,0x73,0xb3,0xf8,0x57,0x9a,0x6d, + 0xb5,0x5e,0xfa,0x4c,0xf9,0x27,0x26,0x27,0x1a,0x5d,0x6c,0x9f,0xd4,0x7d,0xec,0x2c, + 0xaf,0xb6,0x71,0xe7,0xf7,0xd6,0xa7,0x7c,0xa7,0x5f,0x1e,0x35,0x3f,0x63,0xe7,0x99, + 0x77,0x3d,0xf4,0x26,0x3d,0xa5,0xd7,0x33,0x0e,0xe2,0x9c,0x1f,0x35,0x0a,0xaf,0xea, + 0x7b,0x79,0xd9,0x4b,0xb2,0x0e,0xfe,0x5a,0x50,0x7a,0xd8,0x98,0xd7,0xe4,0x1d,0x2c, + 0x67,0x67,0x15,0x83,0x38,0xff,0xb0,0x33,0x96,0x29,0x7b,0xe9,0x6a,0x47,0x60,0x26, + 0x3b,0x77,0xd7,0xe8,0x48,0xb4,0xda,0xe7,0x1f,0xc2,0x06,0x68,0x2d,0x75,0xf4,0x87, + 0x18,0x43,0xc6,0x91,0x02,0x53,0x5d,0x8f,0xaa,0x81,0x88,0x7d,0xfe,0x3c,0xec,0x56, + 0xd7,0xab,0x01,0x67,0xff,0x57,0x40,0xdd,0x4a,0x2a,0x49,0x87,0xba,0xdd,0xc0,0xc0, + 0x6c,0x44,0xcc,0x97,0x74,0x3b,0xb2,0x2d,0xa3,0xcb,0xb4,0xce,0xdf,0xe0,0x07,0x7f, + 0x29,0xca,0x81,0xfe,0xc0,0x80,0x37,0x51,0x9e,0xb2,0xf5,0x87,0x8f,0xc2,0x1f,0xb4, + 0x97,0x1c,0xfc,0x02,0x9f,0x59,0x7e,0x06,0x9d,0x79,0x6d,0x4f,0x7d,0xfa,0xee,0x2c, + 0xfe,0x75,0x50,0xcc,0xf2,0x90,0xfa,0xb1,0xab,0x8e,0x1d,0x6f,0x5b,0x89,0x6b,0xb0, + 0xcb,0x40,0x5e,0xd0,0x6f,0xeb,0x37,0x6a,0xe9,0x83,0x60,0xe9,0x2a,0x3f,0x26,0xd5, + 0xa0,0xc6,0x31,0x3e,0xdc,0x8b,0xe3,0x52,0x77,0x6f,0xfe,0x5c,0xe8,0xd9,0xd8,0xf9, + 0x87,0xad,0x6a,0x96,0xae,0x52,0xd5,0x89,0xa2,0x74,0x81,0xde,0x83,0x86,0xc5,0xd1, + 0x62,0xda,0x77,0x8c,0x07,0xe9,0x32,0xbb,0xfe,0x55,0x95,0x56,0x57,0x90,0x4b,0xe0, + 0x19,0xbc,0xa2,0xae,0x8c,0x38,0xfa,0xc3,0x25,0xd0,0x03,0x21,0xd3,0x37,0x97,0xd1, + 0x2e,0xa8,0xed,0x53,0xc3,0xb2,0x0a,0xa7,0xf5,0x90,0x19,0xd4,0xe5,0xb7,0xc5,0x7d, + 0x8c,0x92,0x0d,0xc4,0x3a,0xa1,0x71,0xc8,0x26,0x8f,0x1f,0x89,0x8c,0x7d,0xc2,0xc6, + 0x5c,0x55,0x79,0x4c,0x3d,0x28,0x50,0x78,0x08,0x4e,0xd3,0x1a,0xd3,0xa7,0xcb,0x39, + 0x90,0x62,0xf9,0xc3,0x84,0xec,0x2e,0xe6,0x6d,0xa2,0xa5,0xff,0x27,0xb4,0x9a,0xdb, + 0xec,0xf5,0x8e,0x4b,0x26,0x16,0x29,0x86,0x56,0x66,0xa4,0x49,0x58,0xac,0x65,0x1d, + 0x1e,0xa3,0xeb,0x12,0xdb,0xb2,0x6a,0x76,0x23,0xe4,0x32,0x58,0x63,0x96,0xc5,0x3c, + 0x2b,0xdc,0x60,0xeb,0xe7,0x19,0x5f,0x4e,0xd8,0x63,0xe7,0x0f,0x41,0x85,0xb6,0x98, + 0x1e,0x43,0x47,0xe4,0xb7,0xf5,0x87,0x83,0x70,0x44,0xa8,0x0d,0x85,0x8f,0xc2,0xfe, + 0x54,0xc2,0x11,0xb3,0xab,0xd5,0x97,0x96,0xc3,0xb6,0x9e,0x0d,0xa7,0x57,0x1b,0xe7, + 0xeb,0xa6,0x0c,0x93,0x89,0xfb,0xbf,0xd0,0x67,0xc6,0xc3,0xe3,0xf6,0x1c,0xcd,0x6c, + 0xb7,0x4e,0x81,0xb0,0xce,0x33,0x37,0x19,0xff,0xe2,0x6a,0x43,0x3f,0xc7,0x26,0xa4, + 0x5d,0x91,0x2b,0xc4,0x26,0xaf,0x52,0xb7,0xe5,0x35,0x16,0x5e,0x57,0xa1,0x3d,0xab, + 0x06,0xb2,0xf0,0xab,0x9f,0xcc,0x17,0xbf,0x81,0xb5,0x89,0x08,0x99,0x27,0xd7,0x1f, + 0xee,0xd1,0x13,0x36,0x7e,0x55,0xc5,0x3c,0xc7,0xc8,0x25,0xca,0x9e,0xb2,0x60,0x14, + 0xff,0x95,0xf5,0x1b,0x7e,0x23,0x2c,0x7f,0xd8,0x24,0x8e,0x55,0xcf,0xb3,0xba,0x1a, + 0xe2,0x1b,0x99,0x91,0x91,0x2d,0xb0,0xf5,0x87,0x03,0x88,0x44,0x59,0x7e,0x7e,0x69, + 0xd2,0xc3,0x85,0x88,0xd7,0xf9,0xfa,0xe5,0xf7,0x73,0x2c,0xfd,0xe1,0x19,0x7a,0x3e, + 0xdd,0xc5,0xe1,0x98,0x43,0x1b,0xd7,0xab,0x5f,0x5f,0xc9,0x7e,0x3f,0x45,0x0e,0x08, + 0xcd,0xc0,0xc2,0x52,0xc4,0x2f,0x1a,0x10,0xfa,0x79,0x86,0x5f,0x1d,0xcc,0x60,0xbf, + 0x64,0xa1,0x9a,0xd8,0x67,0x4b,0xbf,0xb1,0x86,0xed,0x56,0xb6,0xfb,0x5c,0x6d,0xa8, + 0x4d,0xe4,0x0c,0xac,0x51,0xcb,0x9a,0xd4,0x5b,0x5a,0x2f,0x93,0xf8,0xe8,0xb7,0x2a, + 0x3b,0xe1,0x79,0x3d,0x20,0xca,0x5e,0xec,0x20,0x44,0xa6,0x3f,0x0c,0xac,0x6b,0x64, + 0xbc,0xdb,0x5f,0x6d,0xed,0xff,0xba,0x7d,0x80,0xa9,0xbc,0x32,0x7d,0xf6,0x6e,0x69, + 0xe8,0x33,0x0e,0x40,0x38,0xe6,0xc5,0x97,0x5f,0xb7,0xe6,0x6b,0xa7,0x72,0x52,0x79, + 0x31,0xd3,0x86,0xe5,0x0f,0xd1,0x78,0x31,0x3a,0x27,0xee,0x71,0xf4,0x87,0x88,0x5f, + 0xba,0x75,0xec,0xfc,0xa0,0x10,0x72,0x9c,0x80,0x11,0x05,0x0d,0xb3,0x88,0xd8,0xfa, + 0xc3,0xd9,0xfa,0x8b,0x94,0xa3,0xd5,0xa0,0xf6,0x1c,0x04,0x99,0xfe,0xd0,0x3a,0xff, + 0x30,0x4d,0x88,0x26,0xda,0x28,0x8d,0xb0,0xd7,0x4c,0x64,0xad,0x2f,0x16,0x28,0x22, + 0x40,0xa7,0x71,0x7d,0x59,0x73,0x41,0xb5,0xdb,0xe0,0x19,0xa1,0x9e,0x65,0x67,0x59, + 0xcc,0xe1,0x85,0x5d,0x78,0x5a,0xaa,0xea,0xc7,0xfb,0x08,0x97,0x09,0x1d,0x1d,0xdf, + 0xc2,0xf0,0x7b,0x8f,0xc0,0x2f,0x24,0x62,0x09,0xef,0x0a,0x84,0xda,0xff,0x8d,0x01, + 0x79,0x30,0x25,0x8b,0x57,0x1e,0xd4,0x92,0x9d,0xd9,0x7e,0xbe,0x96,0xce,0x49,0x60, + 0xe7,0xd9,0x3e,0xa9,0x5c,0xea,0x39,0x68,0xeb,0x0f,0xff,0xe5,0x16,0x2b,0x7a,0x47, + 0x7f,0x18,0xaf,0x1f,0xdc,0xb8,0x3a,0xb7,0xce,0x38,0x4f,0xeb,0x63,0xbe,0x41,0xb9, + 0x5f,0x8c,0xeb,0xc9,0xd2,0x2d,0xb0,0x56,0xb3,0xfa,0xf3,0x07,0x0e,0xac,0xf2,0x9d, + 0xc6,0xd3,0x5a,0x55,0x63,0x5e,0x8c,0x7c,0xb4,0x98,0xb7,0xd1,0x60,0x8b,0xd6,0x02, + 0x76,0x9f,0xa5,0xaa,0x8e,0xce,0x65,0x6e,0x2d,0xfa,0x34,0xe3,0xcb,0xd7,0xa3,0xb7, + 0xe1,0x6d,0x62,0x4a,0x3b,0x62,0x8f,0xe5,0x5b,0x90,0x76,0x31,0x7c,0x27,0xf0,0x2c, + 0x0d,0x1a,0x79,0x10,0xb6,0xbe,0x6b,0x17,0xcb,0xf7,0xea,0x5d,0xa2,0xcc,0xcd,0x63, + 0xec,0x38,0xa9,0xd2,0xbf,0x68,0xab,0xa3,0x1e,0x76,0x02,0x2a,0x7f,0x37,0xe2,0x18, + 0x6f,0x58,0x3f,0xfb,0x65,0xd5,0xf5,0xe2,0x48,0x58,0xbe,0x30,0xea,0xe2,0xb9,0x4f, + 0xc9,0x03,0xb6,0xfe,0xf0,0x29,0x38,0x6f,0xec,0x75,0x7c,0x26,0xf5,0xa5,0xca,0x87, + 0xd5,0x0b,0xbd,0x73,0xa9,0xb7,0x5f,0xb6,0xf4,0x87,0x8f,0xe3,0xfa,0x4a,0x1a,0xdb, + 0x9d,0x94,0x20,0xf5,0x74,0x60,0x58,0xf8,0x9c,0x11,0x88,0xab,0x5b,0x22,0x27,0x97, + 0x59,0xf9,0x43,0x16,0x11,0x05,0xb2,0xd2,0x86,0x9b,0x91,0x8c,0x3c,0x07,0x01,0x88, + 0x26,0x03,0x69,0x31,0x5f,0x88,0x5f,0x90,0x84,0x6c,0x2d,0xba,0x86,0xc6,0x73,0xf8, + 0x92,0x22,0xaf,0x74,0xf4,0x87,0xcb,0xed,0x53,0x95,0x38,0xe6,0x32,0x59,0x54,0xba, + 0xf4,0x39,0x29,0x0c,0xc1,0xb8,0x9c,0x6e,0x75,0xea,0x5f,0x17,0xb2,0x78,0x0a,0xdd, + 0x68,0xde,0x35,0x8c,0x98,0xfb,0x12,0xf8,0xfa,0xbf,0x9f,0x9e,0x69,0xe9,0x37,0x1c, + 0xda,0x75,0xc1,0x16,0x72,0x4c,0xdc,0xff,0x45,0x1d,0xfe,0x45,0xec,0x83,0x7c,0xc9, + 0xa7,0xda,0xf3,0xed,0xd5,0x27,0x3c,0xdd,0x91,0xec,0xf3,0xa3,0x64,0x7e,0x32,0xc3, + 0x61,0x76,0x04,0x25,0x1a,0x77,0x65,0xed,0xff,0x12,0xdf,0x55,0x28,0xf8,0x57,0xa7, + 0xcd,0xbf,0xa6,0x64,0x1d,0xdc,0xe4,0x9c,0x7f,0x38,0xb9,0x16,0x29,0xce,0xa2,0x5c, + 0x9a,0x2c,0x9a,0x74,0x7e,0xaf,0x3c,0x7a,0xe9,0x38,0x22,0xe6,0xb9,0x08,0xff,0x6a, + 0x18,0x1a,0xf7,0xa0,0xb2,0xf5,0x1b,0x56,0x2e,0x57,0x16,0x3f,0xd1,0xb2,0x20,0x3b, + 0x97,0x1b,0xb9,0xf8,0xf9,0x51,0xe3,0x37,0x08,0x64,0xf4,0x1b,0x71,0x06,0x5b,0x53, + 0xee,0x23,0xc7,0xe3,0x2f,0xd1,0x19,0xe2,0xfc,0xa8,0x7d,0xdb,0xaa,0x4e,0x70,0x2e, + 0xc3,0xef,0xc3,0x7f,0xbf,0x32,0x59,0xdb,0xc7,0xf9,0xd7,0x39,0x08,0x0d,0xfa,0xae, + 0x66,0x40,0x46,0x6b,0xcd,0x8d,0xd7,0x64,0x9d,0x1f,0xd5,0x78,0x4e,0x6c,0x5b,0x1e, + 0x6a,0xfa,0x98,0x15,0x37,0x93,0xdf,0x18,0xb5,0x37,0xd4,0x67,0xeb,0x37,0x14,0x8c, + 0x5b,0xf8,0x71,0x8e,0xca,0xb8,0xa0,0xab,0x61,0xd2,0xf9,0x51,0x19,0xda,0xf5,0xee, + 0x84,0xfd,0x5f,0xb6,0x7e,0xc3,0xc1,0x5c,0xc7,0x98,0x32,0xfe,0xfc,0xa8,0x49,0x7b, + 0xb7,0xf7,0x8a,0x22,0xc5,0xa4,0xf3,0xa3,0x2c,0x4d,0xf2,0xc6,0x44,0xd1,0xa0,0xf7, + 0x0b,0x91,0xa0,0xf8,0x4f,0xf5,0x1b,0x7f,0xe4,0xfc,0xa8,0xa5,0xd9,0xfb,0xbf,0x2e, + 0xa6,0xdf,0xc8,0x18,0x35,0x7f,0xec,0xfc,0xa8,0x22,0xcb,0x58,0xf4,0x65,0xe7,0x47, + 0x29,0x0e,0x11,0xab,0xcc,0xce,0x1f,0x66,0xef,0xff,0x9a,0xd8,0xe7,0x8b,0x9e,0x1f, + 0x45,0xc6,0xf3,0x14,0x4b,0xbf,0xb1,0x55,0x1a,0xb8,0x28,0x97,0xb9,0xc8,0xf9,0x51, + 0x92,0x83,0x5f,0xd9,0xc6,0x11,0xc1,0xdf,0x33,0xfb,0x97,0x2d,0xce,0xd8,0xa6,0x45, + 0x9c,0x2b,0x17,0x39,0x7f,0x63,0xb2,0x76,0xc5,0xca,0x1f,0x16,0xda,0xdf,0xde,0x30, + 0xb9,0x3f,0x59,0xe7,0x47,0x89,0x29,0xb8,0x48,0xe7,0x0f,0xfe,0x31,0xfe,0x35,0x41, + 0xbf,0x61,0xf3,0x2f,0x76,0x24,0xe6,0x73,0x8a,0xd8,0xbf,0xfc,0x25,0xfb,0xbf,0xa6, + 0x4c,0x38,0x9f,0x2d,0x5b,0xbf,0x91,0xc5,0xbf,0x1e,0xb5,0xf9,0x97,0xf3,0x3e,0x0f, + 0x8a,0xf3,0xb1,0x33,0xfc,0xeb,0xd6,0xe3,0x59,0x44,0xac,0x7d,0xb2,0xfe,0x90,0xad, + 0x14,0xc9,0x3e,0x67,0xa9,0xc8,0xf1,0x09,0x19,0xfd,0x86,0xc8,0x1f,0xf2,0xf3,0xa3, + 0x18,0x11,0x3b,0xcb,0x89,0x18,0x37,0x32,0xe7,0x6f,0xd0,0xbd,0xec,0xfc,0xc3,0x6b, + 0x08,0xdb,0xbf,0x1c,0xe4,0xeb,0x9d,0xb2,0xdf,0x4b,0xf2,0xac,0x8e,0x58,0x9c,0xa8, + 0x14,0xac,0xf3,0x0f,0xad,0x63,0x7b,0xb9,0x21,0xed,0xd3,0xaa,0xb2,0xf7,0x7f,0x39, + 0xeb,0xcb,0x9f,0x19,0xbb,0xad,0xe8,0xb0,0xce,0xdf,0x48,0x38,0xfc,0xab,0x7c,0x32, + 0xc9,0xfa,0x23,0xfc,0x2b,0x2b,0xa3,0x68,0xeb,0x37,0x60,0x4c,0x19,0xcf,0xbf,0x18, + 0x23,0xfb,0x11,0x3f,0x59,0x71,0xe2,0xf9,0x1b,0x19,0xfe,0x35,0xa4,0xb2,0x8a,0x61, + 0x27,0x62,0xd3,0x45,0xf8,0xd7,0x44,0xc3,0xe1,0x5f,0xf9,0x99,0xa9,0x44,0xfe,0x75, + 0x50,0xd4,0xbf,0x58,0x45,0x6c,0xbe,0xa3,0x3f,0xcc,0x5f,0xc9,0xab,0x5d,0x1b,0x9f, + 0xf1,0x73,0xfd,0x06,0x3f,0x64,0x3e,0x71,0xae,0xb6,0x06,0xb9,0x55,0xe6,0xf7,0x53, + 0x86,0x8c,0xb1,0x59,0xf5,0x7d,0xbe,0xbd,0x6d,0x43,0x7d,0x9f,0x41,0xdd,0x41,0xdf, + 0x33,0x6c,0x3f,0x6c,0xa0,0x86,0x9d,0x60,0x39,0xe8,0xe7,0x73,0x01,0xaf,0x2c,0x92, + 0x9b,0x8d,0x3b,0xb5,0xab,0x94,0xfc,0x1e,0x89,0x19,0x5f,0xcb,0xc9,0x7f,0x45,0xba, + 0x27,0xef,0x4e,0xf5,0xaa,0xb2,0x7c,0x73,0x2e,0x88,0x36,0x8d,0xb9,0xf7,0x48,0x77, + 0x1a,0x5f,0xd3,0x4a,0xfa,0xb8,0xf1,0x6d,0xad,0xc4,0x54,0xe6,0xc2,0x06,0xe3,0x1b, + 0xc5,0x8a,0x59,0xd8,0x24,0x3a,0x44,0x24,0x9d,0x46,0x75,0xbf,0xaa,0xb4,0x0a,0xc3, + 0x8b,0xc6,0x3d,0x54,0xd5,0x8b,0x54,0x97,0x08,0x25,0xd8,0x83,0x46,0x22,0x76,0x07, + 0x5c,0x02,0x2e,0x2a,0xc5,0xa4,0x3b,0xe0,0x36,0x34,0x1e,0x8f,0xa9,0x51,0x7e,0xc5, + 0x6a,0xf3,0x4a,0xd4,0xb5,0x4a,0xba,0x93,0x7e,0x4d,0x2f,0x49,0x71,0xe3,0xdb,0xdf, + 0x2d,0x4e,0xb9,0x7e,0x50,0x1b,0xed,0xfb,0xf6,0x32,0xe7,0xbb,0x5e,0x69,0xc2,0x45, + 0x54,0x0a,0x8b,0x15,0xa9,0x85,0x1b,0x39,0x12,0x6d,0x85,0xd8,0x26,0x15,0x8d,0x38, + 0xb5,0xfb,0x6c,0x28,0x01,0x49,0x85,0x88,0xae,0x51,0x45,0xe7,0x46,0x21,0x2d,0xc6, + 0x2b,0x66,0x04,0x34,0xa7,0xcd,0xad,0x52,0xa4,0xa7,0x49,0xbf,0x2d,0x58,0x42,0x24, + 0x83,0x36,0x95,0x15,0x2f,0xbc,0x3d,0x22,0x45,0xa0,0x29,0x79,0x5b,0x69,0x09,0xd8, + 0xe3,0xf2,0x4a,0x45,0x70,0x9d,0xa9,0x35,0xbb,0x96,0x48,0x5f,0x33,0x6e,0x33,0x4b, + 0x7e,0xa0,0x78,0xa5,0xdb,0x4d,0xa3,0xbf,0xb0,0xd9,0xfa,0x19,0x04,0x36,0x2e,0x74, + 0x9e,0x8c,0xaf,0x49,0xa0,0xf8,0xf1,0xf6,0x4a,0x1c,0x54,0xb8,0x1e,0x54,0x43,0xda, + 0x0a,0x92,0x3d,0xae,0x18,0x29,0x85,0xb5,0x10,0xc3,0x27,0x42,0x4a,0x8d,0x56,0xd0, + 0xdb,0xd1,0x50,0x0d,0x02,0x65,0xb4,0x54,0x72,0xc6,0xe5,0x8a,0x49,0x6f,0xc1,0xb7, + 0x8c,0x19,0xd4,0xb5,0x5c,0x3a,0x06,0x3f,0x34,0x8a,0x69,0xee,0x72,0x29,0x85,0x57, + 0x8a,0x33,0xe3,0xca,0x8b,0xc1,0x31,0x7c,0x62,0xf9,0x54,0xba,0x0b,0xee,0xa0,0x97, + 0xc0,0xb4,0x0e,0xa9,0x59,0x8a,0xc2,0x02,0x98,0xe6,0xb4,0x89,0xe4,0x84,0x5a,0xbc, + 0x7a,0x83,0xaa,0xbd,0x7c,0x49,0xe8,0x15,0x66,0x94,0xbe,0xac,0xb0,0x6f,0x6e,0xf0, + 0x82,0x39,0xd7,0x1a,0x97,0x6a,0x84,0x58,0xd0,0x8c,0x30,0x8e,0x6f,0xb8,0x17,0xbb, + 0x8e,0x98,0xc6,0x72,0xd7,0x78,0xc5,0xb0,0xc7,0xe5,0x91,0x42,0x74,0x49,0xb2,0x48, + 0x55,0x0e,0x4a,0xa1,0x96,0x25,0xa1,0x5b,0x55,0xa5,0xd7,0x15,0xc2,0xc9,0x2d,0x52, + 0x8b,0x4d,0xf1,0x9b,0x4a,0xf0,0x4a,0xc3,0x8c,0xe6,0x96,0x3b,0x42,0x7e,0xb5,0xa4, + 0xcd,0xd5,0xdc,0x73,0x87,0xfe,0x2d,0xd5,0xd5,0xe6,0x8a,0xd1,0x52,0x34,0x4a,0xa8, + 0xf5,0x5d,0xaf,0x44,0x40,0xc7,0x6f,0x8f,0xa8,0x48,0x02,0x63,0xac,0x30,0xa6,0x6a, + 0x14,0x42,0x12,0x7b,0x00,0x40,0x43,0x56,0x9f,0x6f,0x51,0xe6,0xb7,0x5c,0x8a,0x6d, + 0x0a,0x37,0x2b,0x7a,0x8b,0x37,0xd9,0xb0,0xe2,0x9b,0xeb,0xf1,0x4a,0x9e,0xbe,0x38, + 0xaa,0xd1,0x42,0xfb,0x19,0x4a,0xa5,0xd2,0xb7,0xa0,0x89,0x96,0xa0,0x01,0x8b,0xa1, + 0x90,0xba,0xd8,0x95,0x08,0xdc,0x4e,0x15,0xc3,0x9e,0xaf,0x1c,0x69,0x11,0x6d,0x8a, + 0x15,0x97,0xba,0x2c,0x63,0xab,0x6b,0xb1,0x74,0x3d,0x8d,0x30,0x03,0xac,0x0f,0xf5, + 0xbb,0x14,0xba,0x48,0x6f,0x52,0x15,0xbf,0x0b,0xa8,0xa1,0x6b,0x51,0x85,0x14,0x2a, + 0x2d,0x8b,0xd0,0x60,0x73,0x28,0xbe,0x6b,0xb1,0xfc,0x4d,0xfa,0x66,0xec,0xca,0x52, + 0xaf,0x6d,0xa8,0x39,0x68,0x28,0x68,0x94,0x1a,0x21,0x6b,0x5c,0x8b,0x5d,0xf7,0xd0, + 0x3b,0x63,0xdf,0x2e,0x75,0xad,0x45,0xe3,0xdd,0xf4,0x3f,0xa8,0x25,0xfb,0x73,0xf1, + 0x69,0xe8,0xdf,0x56,0x4b,0xec,0xb5,0x73,0x5d,0x04,0x57,0xc1,0xbb,0xb1,0xaf,0x95, + 0xe6,0xef,0x47,0xe3,0xce,0x13,0x57,0xa9,0x68,0x34,0xb7,0xdc,0x19,0x43,0xc3,0xb4, + 0xc6,0x75,0xdd,0xe2,0x9c,0xb9,0x78,0xa5,0xa1,0xf4,0xf6,0xfd,0x68,0x78,0x97,0xc9, + 0x77,0x14,0xee,0x57,0xae,0x6c,0xcf,0x8b,0x7d,0xfb,0x0e,0xa0,0xd6,0xb8,0x80,0x48, + 0xcd,0xf8,0xe4,0x09,0xae,0x2f,0x7c,0x98,0x77,0xea,0x5f,0xc3,0xb9,0xe0,0x57,0x70, + 0xc5,0x51,0x6b,0x5c,0x52,0x8e,0xb4,0x8c,0xde,0x81,0x2f,0x1a,0x8e,0xbd,0xac,0xe5, + 0x8e,0xe1,0x6f,0x2d,0x74,0x6d,0x74,0x2d,0x6b,0x89,0xc6,0x2e,0x29,0xc5,0x36,0x86, + 0xf8,0x2e,0xa3,0xa4,0x59,0xba,0x13,0x8a,0xa0,0xd8,0x74,0x35,0x4b,0x4b,0xe2,0xdf, + 0xe6,0x06,0xc6,0x18,0xdf,0x26,0xce,0xfa,0x72,0x45,0x80,0xcd,0xa0,0x35,0x5f,0xaa, + 0x9e,0xe3,0x66,0xc6,0x36,0x34,0x0a,0x9c,0xb9,0xb8,0x2e,0x82,0xd3,0xa4,0xea,0x8b, + 0xd5,0xc2,0x56,0x34,0xb0,0xf1,0x6c,0x66,0x6c,0x63,0xb3,0x5c,0x98,0x69,0x53,0x66, + 0xb4,0x34,0x85,0x6e,0xf7,0x96,0x44,0x24,0xc3,0xbc,0xad,0xac,0x58,0x65,0x46,0x87, + 0xc1,0xde,0x0d,0xc3,0x19,0x17,0xce,0xe7,0x6d,0x7a,0x89,0xd7,0x15,0x91,0x9a,0xcc, + 0xdb,0x42,0x25,0x95,0xed,0x0d,0x52,0x13,0x6d,0xd4,0x0b,0xbd,0x0a,0x88,0x98,0x84, + 0x7d,0xee,0xe2,0x2b,0x4c,0x52,0x15,0x43,0xc1,0xf5,0x25,0xe1,0x7b,0x6a,0x14,0xa3, + 0x33,0x95,0xec,0xbf,0xe3,0x77,0x11,0x9d,0x52,0x5d,0xaf,0x54,0x09,0x21,0x68,0x80, + 0xda,0xe1,0x27,0x4a,0x07,0x04,0xca,0xbc,0x5b,0xed,0xb5,0x7c,0x9d,0x91,0xcb,0xdc, + 0xce,0x0f,0xd1,0xdb,0xe0,0x8b,0x73,0x0c,0xbe,0x95,0x53,0x4c,0xbf,0x11,0x9b,0x9b, + 0x52,0xbf,0x05,0xc5,0x76,0x9f,0xd7,0x18,0x12,0xdb,0x27,0xc1,0x0e,0x24,0x46,0xdf, + 0x72,0x27,0x7c,0x8d,0xe4,0x51,0xb9,0xf9,0xea,0xa8,0xfa,0x2d,0x32,0x95,0x3a,0xdf, + 0x96,0xa3,0x4b,0x5e,0xec,0xb9,0x66,0xa2,0x81,0x6f,0x62,0x85,0x96,0xd2,0x63,0xd1, + 0x8e,0x52,0x99,0xa8,0x4e,0x1b,0x0d,0xbd,0x43,0x3e,0xb6,0x81,0x7e,0xa8,0x60,0x47, + 0xcc,0xfb,0x69,0x3f,0xcc,0xd0,0x54,0x76,0xb6,0x9f,0xd3,0x46,0x91,0xca,0x60,0x89, + 0xe1,0x2f,0x56,0xfa,0xa4,0xb2,0x45,0x4b,0x9a,0x6e,0x2d,0x56,0x7e,0x37,0xe3,0xea, + 0xd4,0x92,0xa6,0xa2,0xcb,0x9c,0x39,0x85,0x72,0xd7,0x8a,0x9e,0x3f,0x0f,0x5d,0xb2, + 0xa1,0x64,0x07,0x37,0xbe,0xb5,0xa1,0x64,0xbb,0xeb,0x6f,0xe8,0x0d,0xa1,0x4b,0x1e, + 0x93,0x9c,0x36,0xa5,0xf8,0x5d,0x79,0xe8,0xe2,0x20,0x0e,0x33,0xd9,0x77,0x69,0x68, + 0xcc,0x47,0xa7,0x47,0x0c,0xcd,0x69,0xa3,0x2a,0x77,0x15,0x96,0x2a,0x8b,0xa5,0xc2, + 0x8e,0xc6,0x58,0x61,0x69,0xfb,0xe2,0x42,0x34,0x42,0x85,0x6a,0x7b,0x8e,0xb4,0x29, + 0x33,0xae,0x45,0x4d,0x85,0xb7,0x29,0xb7,0x4b,0x25,0xc6,0xa2,0x26,0xed,0x36,0xa5, + 0x84,0x19,0x9a,0x66,0xe0,0x15,0x97,0xe1,0xdc,0xa7,0x2c,0xc2,0x6b,0xaf,0x6b,0xa2, + 0x68,0xdc,0x46,0x8a,0xd1,0x91,0x6d,0x8b,0xa0,0x47,0x43,0xc3,0xb9,0x8d,0xdb,0x45, + 0xa8,0x91,0x44,0x72,0xcd,0x0c,0xe4,0x7e,0xb3,0xc1,0xbd,0x08,0x8d,0x5d,0x5a,0xa5, + 0xd3,0x04,0xbc,0xf2,0xad,0xf0,0xa6,0xb9,0x2c,0xa4,0x32,0xa3,0xdd,0xbc,0x32,0xac, + 0x36,0x7e,0xe3,0x56,0x5d,0x49,0x95,0x84,0xb6,0x66,0xbe,0x8b,0x41,0x40,0xfc,0xdb, + 0xba,0x2b,0x25,0xad,0x82,0x77,0xe1,0x1f,0x94,0x7f,0x46,0x50,0x28,0x7b,0xb7,0xfd, + 0xaf,0xf5,0x12,0xd3,0x6e,0x23,0x43,0xb4,0x57,0x0b,0x29,0xde,0x65,0xe5,0x60,0xf4, + 0xf9,0xe7,0x2a,0xde,0xb2,0x72,0xcd,0x30,0xfd,0xa1,0x76,0x6f,0xe6,0xe5,0xa8,0x1f, + 0x5b,0x3a,0xf6,0xc6,0xd8,0x99,0xb1,0xf3,0x93,0x0d,0xf8,0xaf,0x7c,0x16,0xbc,0xe3, + 0x59,0xd0,0xfb,0x5a,0x72,0xef,0xca,0xa0,0x30,0xc6,0x86,0x82,0xef,0x2d,0x1d,0x7b, + 0xfd,0x3d,0x34,0x9c,0x36,0x57,0xd4,0x2e,0x39,0x5a,0x34,0xaf,0xef,0xf0,0xc9,0x79, + 0xc2,0x18,0x3b,0x39,0xaf,0x1e,0xbf,0xab,0x1e,0x8d,0x4c,0x7f,0x4a,0x6f,0x7e,0x75, + 0xf3,0xdc,0xf6,0x07,0xce,0x5e,0x53,0x1a,0x3d,0x5e,0xb4,0xaf,0x7d,0xc3,0xbd,0xd7, + 0xac,0x8e,0xee,0x2f,0xda,0x33,0xb0,0x61,0x99,0xd3,0xc6,0x45,0x9a,0x8d,0xa9,0xcd, + 0x57,0x28,0x79,0xaf,0xc0,0x3d,0x68,0x2c,0xb0,0x0c,0xed,0x8a,0xe2,0x4b,0x9d,0xb1, + 0x2b,0x36,0x1c,0xf7,0x7d,0x8d,0x19,0x45,0xda,0xed,0x7d,0xae,0x7b,0xa4,0x77,0xf1, + 0xca,0x34,0xa7,0x0d,0xc7,0x65,0xc8,0xe0,0xb2,0xaa,0xac,0x15,0x06,0x28,0xd4,0xb9, + 0x8f,0x80,0x51,0x90,0xda,0x61,0x99,0x54,0x6a,0x2c,0x06,0x89,0x2a,0xcb,0xd8,0x15, + 0x35,0xf3,0x8e,0xb9,0x95,0x55,0xd2,0x54,0xfa,0x0d,0x5d,0x3b,0x64,0x19,0x85,0x29, + 0x65,0xd5,0x22,0x66,0x48,0xce,0x77,0x81,0x05,0xc7,0xf8,0x86,0xa3,0x03,0x61,0x37, + 0x6c,0xb5,0xef,0xec,0xdc,0xa7,0x50,0x29,0x97,0xf2,0x4c,0x84,0xe3,0x2d,0x4a,0x85, + 0xc4,0x5e,0x5a,0x2d,0xae,0xcc,0x68,0x51,0x69,0xa4,0x39,0xb3,0x2e,0xca,0xe1,0x86, + 0x1e,0x7f,0xa2,0x71,0x57,0xe1,0xdd,0x10,0xe5,0xbf,0xe9,0x5a,0x88,0xfc,0xde,0xf4, + 0x0f,0x37,0xee,0xb2,0xe7,0x54,0x35,0x55,0x28,0xa2,0x8a,0x89,0x30,0xb2,0x44,0x38, + 0x33,0x06,0x62,0xb7,0x82,0x62,0x4a,0xf3,0x25,0xc3,0x72,0x1b,0x66,0x31,0x14,0x02, + 0xdb,0x03,0x28,0x15,0x23,0x60,0x16,0xd2,0x9c,0x52,0xec,0xcb,0x75,0x2e,0x05,0x9d, + 0x80,0x24,0xc2,0x3a,0xbc,0x8f,0x81,0xab,0xa5,0x5d,0x42,0x7f,0xc1,0x96,0x0d,0xeb, + 0x81,0xca,0x16,0x6d,0x3b,0x94,0x29,0x6a,0xa6,0x4d,0x71,0xcc,0xb5,0x15,0x22,0xec, + 0x16,0x31,0xb2,0x95,0x23,0x4f,0x8e,0x80,0xa0,0x32,0x0b,0xbf,0x34,0xc9,0xc0,0x91, + 0x6e,0x65,0xcb,0x8f,0x92,0xbb,0xa0,0x94,0xe6,0x40,0x5e,0x87,0xc2,0xc6,0x3e,0x13, + 0x2e,0x6d,0x15,0x31,0xb6,0x71,0x9d,0x83,0xcb,0xbd,0x8e,0xa1,0x84,0x5a,0x36,0x30, + 0xc3,0xf2,0xf3,0x06,0xa8,0x1c,0x8e,0x1d,0x5c,0x96,0x81,0xff,0xce,0xab,0x30,0xc4, + 0xb8,0x0c,0xf0,0x40,0x88,0x7a,0xcb,0x64,0x15,0x0e,0x41,0xa8,0xc7,0x1b,0x6a,0x50, + 0x0d,0xfe,0xcb,0x70,0xba,0xac,0x2a,0x20,0xfc,0x98,0x71,0x5d,0x83,0xd2,0x8c,0x6e, + 0x19,0xfd,0x73,0x9b,0xd2,0xdc,0x53,0x1a,0x62,0x06,0xc4,0x7a,0xd8,0x15,0x89,0x8a, + 0x7d,0xeb,0x86,0x14,0x11,0xf1,0x88,0x85,0xcb,0xf8,0xcf,0xd1,0x08,0xa1,0xe7,0x67, + 0xb8,0x2c,0xda,0x34,0x49,0x11,0xee,0xde,0x2d,0x3f,0xcf,0xfa,0x5c,0x88,0x6d,0xb8, + 0xe7,0xb7,0xe7,0xd4,0xb8,0xce,0xc0,0xf1,0x17,0xc3,0x75,0x50,0x68,0x08,0x37,0x0d, + 0xc5,0x80,0xb4,0xcb,0xc0,0x5b,0x14,0x46,0xc4,0xb8,0xa2,0xf8,0x0e,0x2c,0xa2,0x5a, + 0x4c,0x29,0x95,0xf6,0xdb,0x86,0x73,0xc5,0x9a,0xd3,0x28,0x10,0x01,0xc7,0x38,0x03, + 0x92,0x30,0x10,0x97,0xa1,0x85,0x1b,0x16,0x2e,0x1b,0xd7,0x39,0x70,0xbc,0x9f,0x1b, + 0x57,0x95,0xe6,0xdb,0x57,0xf2,0x6d,0x4c,0x91,0x16,0x2b,0xf7,0xb4,0x4c,0x8d,0xe5, + 0x96,0x22,0x8c,0xde,0x43,0x1f,0x8d,0xfd,0x35,0x7e,0x29,0x61,0x57,0xbe,0x51,0x2a, + 0x99,0xa2,0xce,0x68,0x48,0x8b,0x81,0xfd,0xe9,0x0a,0x35,0x4f,0xb4,0xc9,0x2d,0xcd, + 0xe3,0x00,0x1d,0xbb,0xa2,0x34,0xcf,0x7a,0x9f,0x9b,0x2c,0x5c,0xfe,0x76,0x69,0xc9, + 0x7e,0x05,0x71,0x19,0x01,0x1a,0x8d,0x7b,0x5a,0x1e,0x65,0x57,0x7a,0xed,0xf9,0xf2, + 0x43,0x05,0xbd,0x9e,0x2d,0xab,0xcd,0x88,0xcb,0x77,0xe8,0x5f,0x8b,0xe2,0x42,0x9b, + 0xcf,0xae,0x44,0x15,0x6a,0xf5,0x19,0xc7,0x8e,0x51,0x5e,0x2c,0xa7,0x54,0x5a,0xab, + 0x94,0x21,0x1c,0x2f,0x66,0xc6,0x32,0x71,0xc5,0x7e,0xe7,0xaf,0x8b,0x29,0xab,0xa5, + 0xe9,0x52,0x43,0xab,0x96,0x46,0xe3,0x06,0x68,0xa0,0xdc,0x98,0x0e,0xdf,0xa0,0x9a, + 0x85,0xcb,0x86,0x74,0x0b,0x2c,0xa7,0x97,0xb2,0xd9,0xd9,0x2c,0x26,0x2e,0x8a,0xf3, + 0xc5,0xae,0xe4,0x44,0xed,0xb5,0x63,0xf0,0xf9,0x52,0x13,0x62,0xbe,0xd6,0xe0,0xc4, + 0x55,0xf2,0x89,0x13,0xb8,0x6c,0xcf,0x57,0x04,0x8c,0x16,0x2d,0x74,0x9d,0xb7,0x10, + 0x0d,0x53,0x0b,0xb9,0xb8,0x41,0x35,0xbd,0xd1,0x5b,0x68,0xd8,0xe3,0x62,0xb8,0x5c, + 0x9c,0x70,0x79,0x59,0x40,0x6c,0x16,0x87,0x5c,0x95,0x52,0x03,0xbb,0xa2,0xe3,0x15, + 0xc3,0xba,0x0f,0x62,0x4a,0x04,0xe7,0x59,0x91,0x18,0x2e,0x5b,0x00,0x0d,0x11,0x09, + 0x01,0x1a,0x67,0xcb,0x9e,0xaf,0x08,0x81,0x2c,0x5c,0x4e,0xe8,0xaa,0xda,0x8a,0x57, + 0x3a,0xd8,0x15,0xb0,0xc7,0x65,0x28,0x76,0x40,0xc7,0x8d,0xbf,0xca,0xac,0xaf,0x42, + 0x6a,0xcf,0x17,0x2b,0x0a,0x3c,0x0c,0x33,0x8d,0x3c,0x8a,0x78,0x3a,0x0d,0x72,0xd1, + 0x50,0x7e,0x80,0xab,0x65,0xa6,0x71,0xbd,0x33,0xae,0x58,0x4e,0xa5,0x54,0xc0,0x1f, + 0x5d,0x4e,0xa5,0xeb,0x32,0x58,0x8c,0x46,0xf1,0x0a,0x69,0xbd,0xd6,0xe0,0x3c,0xc3, + 0x26,0x8c,0x1d,0x74,0xc3,0xdb,0x24,0x6f,0x81,0x1e,0x28,0x6b,0x42,0x00,0x2b,0x61, + 0x86,0xa1,0x6a,0x72,0x09,0x98,0xf6,0xb8,0x14,0x28,0x83,0xfc,0x45,0xf2,0x6d,0xd0, + 0x07,0x33,0x16,0xe5,0x37,0x35,0x34,0xc1,0x2b,0x70,0x25,0xa8,0x4d,0x78,0xa5,0xd7, + 0x5e,0xcb,0x0d,0x0a,0xae,0xa6,0xe6,0xc5,0x5e,0x5c,0x5f,0xdc,0x98,0x2a,0xd6,0x57, + 0x08,0x0d,0xea,0x8c,0x0b,0xb8,0x5f,0x09,0xe1,0xec,0x94,0x1b,0x2a,0xfb,0x79,0x21, + 0xca,0xe4,0x68,0x40,0x2a,0x90,0x50,0x5a,0xf3,0x15,0x6d,0xe4,0xb8,0xac,0x09,0x5c, + 0x56,0x18,0x2e,0x1b,0x77,0x49,0x08,0xd0,0x52,0xa1,0xdd,0xe6,0x3a,0xc3,0x68,0x2a, + 0x2c,0x5e,0x7c,0xdd,0xa2,0x4d,0x86,0xd9,0xa4,0x15,0x17,0xbb,0xa4,0x42,0xe3,0x3a, + 0x68,0x2a,0x56,0xd8,0x8a,0x73,0xfc,0x46,0x22,0x82,0x5e,0xc4,0xc5,0x03,0xed,0xd2, + 0xe2,0xb5,0x2e,0x1d,0x5f,0xb4,0x48,0xa9,0x86,0x93,0x8f,0xfe,0x50,0xcc,0x98,0xe1, + 0xee,0x41,0x5c,0x4e,0x08,0x5c,0x6e,0x81,0x84,0x81,0x86,0x44,0x5a,0x8c,0x04,0xc7, + 0x65,0xf1,0x9c,0xaf,0xbb,0xe9,0xe5,0x5b,0x63,0x6f,0xf6,0x97,0xcd,0x57,0xf3,0x8b, + 0x6e,0x35,0xda,0xd1,0xc8,0xbb,0x49,0xbe,0xd5,0x78,0xb3,0xff,0xca,0xf9,0xaa,0xe1, + 0x8c,0x6b,0x6d,0xf3,0x8c,0xa9,0xad,0xb9,0x4a,0xa1,0x59,0x81,0x58,0x00,0xdf,0x28, + 0x2b,0x49,0x91,0x55,0x85,0x53,0xdb,0x11,0x14,0x4c,0x7b,0x35,0x97,0x0b,0x5c,0x5e, + 0xb2,0xac,0xbc,0x34,0xba,0xdf,0x3f,0xb7,0x7d,0x03,0x1a,0x06,0x37,0xfe,0xfb,0x71, + 0xb9,0x6a,0xec,0xc6,0x9f,0xbc,0x3c,0x76,0xe6,0xdc,0xca,0xaa,0xb1,0xa5,0xfb,0xde, + 0xf8,0xe4,0x4c,0x06,0x97,0x33,0xf7,0x99,0x37,0xb6,0x64,0xac,0x68,0xec,0xcc,0xe8, + 0xc9,0x79,0x63,0x4b,0x8f,0xbe,0x71,0xfa,0x4c,0x06,0x97,0x33,0x6d,0xae,0xe1,0xb8, + 0x3c,0x20,0x70,0xd9,0x7f,0x15,0xc7,0xe5,0x9b,0x19,0x2e,0x3f,0x70,0xd6,0x69,0x43, + 0xda,0x61,0x1b,0x54,0x1a,0xee,0xa9,0xbd,0x96,0xa1,0xb1,0x2b,0x87,0x99,0xe1,0xb4, + 0x41,0xbf,0xe5,0x38,0xb0,0x09,0x46,0xa6,0xd3,0xed,0xec,0x55,0xe0,0xe8,0x33,0xc9, + 0x70,0x3e,0xdc,0xed,0x19,0x30,0xd5,0xb4,0x0c,0xbe,0xc6,0x0e,0x73,0xc3,0xf9,0x50, + 0xf1,0x92,0x4d,0x36,0xbc,0xa6,0xd3,0xe7,0x2f,0x6f,0x65,0xf7,0x98,0x31,0x78,0xfe, + 0xeb,0xc3,0x20,0x8e,0xa1,0xc8,0x6e,0x4a,0xec,0x36,0x17,0xfd,0x1a,0x6e,0x78,0x7b, + 0xed,0x36,0xee,0x76,0xb2,0x0d,0x76,0x19,0xb3,0x35,0xf7,0xba,0x30,0x37,0xa6,0x1e, + 0xb4,0xaf,0x90,0x3f,0xfd,0xf9,0xa8,0x93,0x9f,0x4f,0xe6,0x8a,0xdd,0x1f,0x0d,0x72, + 0x43,0xf8,0x34,0xbe,0x8f,0xcf,0x87,0x1b,0xce,0xf3,0xf9,0x3e,0x30,0x99,0x85,0x75, + 0x9f,0x75,0xa1,0x2f,0x7b,0xce,0x4e,0x7f,0xb0,0xf1,0x7f,0xf2,0x7c,0xf8,0x7c,0x7d, + 0xc9,0x73,0x76,0x5a,0x68,0xac,0x46,0xf7,0x65,0x1f,0x91,0xd3,0xfb,0x53,0x3e,0xb5, + 0xb5,0x7f,0xe4,0x8f,0x3e,0xdf,0x9f,0x7a,0x9b,0xff,0xc6,0x4f,0xfd,0xd8,0xd8,0x98, + 0x79,0x71,0xe3,0xff,0xd3,0x6d,0x48,0xf6,0x12,0x1e,0x6f,0x64,0x1a,0x89,0xa5,0x37, + 0xf1,0x5d,0x1d,0xbf,0x06,0xff,0x0b,0x6b,0x59,0xbb,0x88,0xe1,0x7c,0xbe,0x74,0x2d, + 0xdb,0x0d,0xbe,0x7c,0x05,0x66,0x5a,0xa9,0x99,0x25,0xac,0x4e,0x58,0xd4,0x81,0x3f, + 0x65,0x2d,0x67,0xda,0x88,0xb5,0xfc,0x7d,0x5c,0xcb,0xd6,0x12,0x9e,0xb4,0x96,0xd5, + 0x3f,0xb6,0x96,0x9d,0x36,0x7f,0xe4,0xf9,0x8c,0x5b,0xcb,0xc0,0xd7,0xb2,0xb5,0x84, + 0xad,0x45,0x8d,0x46,0xaf,0xf2,0x27,0xdf,0xe7,0x4f,0xf1,0x75,0x7f,0xca,0x73,0x86, + 0x0c,0x71,0xbe,0xc8,0xe7,0xab,0xb5,0xfc,0xff,0xbe,0x36,0xff,0xf9,0x27,0x04,0xba, + 0x44,0xf8,0xff,0x46,0xae,0xff,0x2f,0xfe,0xd3,0xaf,0x3e,0x5f,0x7d,0xbe,0xfa,0x7c, + 0xf5,0xf9,0xea,0xf3,0xd5,0xe7,0xab,0xcf,0x57,0x9f,0xff,0x5f,0x7c,0x78,0xbc,0x44, + 0x78,0xbc,0x64,0xfc,0x3f,0xdd,0x97,0xaf,0x3e,0x5f,0x7d,0xbe,0xfa,0x7c,0xf5,0xf9, + 0xea,0xf3,0xd5,0xe7,0xab,0xcf,0x57,0x9f,0xff,0xbb,0x3f,0x21,0x2e,0x0c,0x7b,0xa3, + 0x36,0x04,0xbc,0xa8,0x2b,0x87,0xc0,0xc8,0xfb,0xd3,0xfe,0x1d,0x6f,0xef,0x0a,0x41, + 0x42,0xca,0xdc,0xa7,0xe7,0x1f,0x27,0xf6,0xf5,0xff,0x02,0xd6,0x2c,0x67,0x26,0xbd, + 0xa4,0x00,0x00, diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds new file mode 100644 index 0000000..f7a20d1 --- /dev/null +++ b/board/esd/cpci405/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/cpci440/Makefile b/board/esd/cpci440/Makefile new file mode 100644 index 0000000..84d44fb --- /dev/null +++ b/board/esd/cpci440/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o strataflash.o ../common/misc.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/cpci440/config.mk b/board/esd/cpci440/config.mk new file mode 100644 index 0000000..8e5f63f --- /dev/null +++ b/board/esd/cpci440/config.mk @@ -0,0 +1,45 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0x01fc0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/esd/cpci440/cpci440.c b/board/esd/cpci440/cpci440.c new file mode 100644 index 0000000..43d8a3b --- /dev/null +++ b/board/esd/cpci440/cpci440.c @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2002 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +extern void lxt971_no_sleep(void); + + +long int fixed_sdram( void ); + +int board_early_init_f (void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr( ebccfga, xbcfg ); + reg = mfdcr( ebccfgd ); + mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */ + + mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */ + mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */ + /* test-only: other regs still missing... */ + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr( uic0sr, 0xffffffff ); /* clear all */ + mtdcr( uic0er, 0x00000000 ); /* disable all */ + mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */ + mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */ + mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */ + mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */ + mtdcr( uic0sr, 0xffffffff ); /* clear all */ + + mtdcr( uic1sr, 0xffffffff ); /* clear all */ + mtdcr( uic1er, 0x00000000 ); /* disable all */ + mtdcr( uic1cr, 0x00000000 ); /* all non-critical */ + mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */ + mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */ + mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */ + mtdcr( uic1sr, 0xffffffff ); /* clear all */ + + return 0; +} + + +int checkboard (void) +{ + sys_info_t sysinfo; + get_sys_info(&sysinfo); + + printf("Board: esd CPCI-440\n"); + printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000); + printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000); + printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000); + printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000); + printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return (0); +} + + +long int initdram (int board_type) +{ + long dram_size = 0; + + dram_size = fixed_sdram(); + return dram_size; +} + + +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + * + * Assumes: 64 MB, non-ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +long int fixed_sdram( void ) +{ + uint reg; + +#if 1 /* test-only */ + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */ + mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */ + mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */ + mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */ + mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/ + mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + /* RA=10 RD=3 */ + mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */ + udelay( 400 ); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */ + for(;;) + { + mfsdram( mem_mcsts, reg ); + if( reg & 0x80000000 ) + break; + } + + return( 64 * 1024 * 1024 ); /* 64 MB */ +#else + return( 32 * 1024 * 1024 ); /* 64 MB */ +#endif +} diff --git a/board/esd/cpci440/init.S b/board/esd/cpci440/init.S new file mode 100644 index 0000000..82f37fd --- /dev/null +++ b/board/esd/cpci440/init.S @@ -0,0 +1,94 @@ +/* +* Copyright (C) 2002 Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X ) + tlbtab_end diff --git a/board/esd/cpci440/strataflash.c b/board/esd/cpci440/strataflash.c new file mode 100644 index 0000000..2f055c2 --- /dev/null +++ b/board/esd/cpci440/strataflash.c @@ -0,0 +1,755 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + + +#define FLASH_MAN_CFI 0x01000000 + + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char * cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +/*----------------------------------------------------------------------- + * Functions + */ + + +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *)(info->start[sect] + (offset * info->portwidth))); +} +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | + (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + unsigned long address; + + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if( info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3 ), (info->chipwidth << 3 )); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n"); + printf (" %08lX%5s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for(i=0;iportwidth) && (cnt > 0) ; i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *)cp)); + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while(cnt >= info->portwidth) { + i = info->buffer_size > cnt? cnt: info->buffer_size; + if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + /* handle the aligned part */ + while(cnt >= info->portwidth) { + cword.l = 0; + for(i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; iportwidth; ++i, ++cp) { + flash_add_byte(info, & cword, (*(uchar *)cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if(prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, + prot?"protect":"unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if(prot == 0) { + int i; + for(i = 0 ; isector_count; i++) { + if(info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt,info->start[sector]); + if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ + printf("Command Sequence Error.\n"); + } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) +{ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) +{ + int i; + uchar *cp = (uchar *)cmdbuf; + for(i=0; i< info->portwidth; i++) + *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * + */ +static int flash_detect_cfi(flash_info_t * info) +{ + + for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; + info->portwidth <<= 1) { + for(info->chipwidth =FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } + return 0; +} +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t * info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if(flash_detect_cfi(info)){ +#ifdef DEBUG_FLASH + printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif + sect_cnt = 0; + sector = base; + for(i = 0 ; i < num_erase_regions; i++) { + if(i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) +1; + for(j = 0; j< erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *)dest; + + + /* Check if Flash is (sufficiently) erased */ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if(!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if(flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t *info, ulong addr) +{ + int sector; + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *)dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar)cnt-1); + while(cnt-- > 0) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check(info, sector, info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci440/u-boot.lds b/board/esd/cpci440/u-boot.lds new file mode 100644 index 0000000..57220d3 --- /dev/null +++ b/board/esd/cpci440/u-boot.lds @@ -0,0 +1,159 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : +/* .resetvec 0x01FFFFFC :*/ + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : +/* .bootpg 0x01FFF000 :*/ + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/esd/cpci440/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile new file mode 100644 index 0000000..2ca73a9 --- /dev/null +++ b/board/esd/cpci5200/Makefile @@ -0,0 +1,53 @@ + +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +# Objects for Xilinx JTAG programming (CPLD) +# CPLD = ../common/xilinx_jtag/lenval.o \ +# ../common/xilinx_jtag/micro.o \ +# ../common/xilinx_jtag/ports.o + +# OBJS = $(BOARD).o flash.o $(CPLD) +OBJS = $(BOARD).o strataflash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/esd/cpci5200/config.mk b/board/esd/cpci5200/config.mk new file mode 100644 index 0000000..07b5de1 --- /dev/null +++ b/board/esd/cpci5200/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# IceCube board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFF000000 boot low for 16 MiB boards +# 0xFF800000 boot low for 8 MiB boards +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c new file mode 100644 index 0000000..6c98f13 --- /dev/null +++ b/board/esd/cpci5200/cpci5200.c @@ -0,0 +1,295 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * cpci5200.c - main board support/init for the esd cpci5200. + */ + +#include +#include +#include +#include + +#include "mt46v16m16-75.h" + +void init_ata_reset(void); + +static void sdram_start(int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = + SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = + SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register: extended mode */ + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = + SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = + SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram(int board_type) +{ + ulong dramsize = 0; + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + + /* set tap delay */ + *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = + 0x13 + __builtin_ffs(dramsize >> 20) - 1; + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ + } else { +#if 0 + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ +#else + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = + 0x13 + __builtin_ffs(0x08000000 >> 20) - 1; + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */ +#endif + } + +#if 0 + /* find RAM size using SDRAM CS1 only */ + sdram_start(0); + get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + sdram_start(1); + get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + sdram_start(0); +#endif + /* set SDRAM CS1 size according to the amount of RAM found */ + + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + + init_ata_reset(); + return (dramsize); +} + +int checkboard(void) +{ + puts("Board: esd CPCI5200 (cpci5200)\n"); + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + +void flash_afterinit(ulong size) +{ + if (size == 0x02000000) { + /* adjust mapping */ + *(vu_long *) MPC5XXX_BOOTCS_START = + *(vu_long *) MPC5XXX_CS0_START = + START_REG(CFG_BOOTCS_START | size); + *(vu_long *) MPC5XXX_BOOTCS_STOP = + *(vu_long *) MPC5XXX_CS0_STOP = + STOP_REG(CFG_BOOTCS_START | size, size); + } +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void + ) { + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL + +void init_ide_reset(void) +{ + debug("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; +} + +void ide_set_reset(int idereset) +{ + debug("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + } +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) +#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) +#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010) +#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014) + +#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020) +#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028) +#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C) +#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C) + +#define GPIO_WU6 0x40000000UL +#define GPIO_USB0 0x00010000UL +#define GPIO_USB9 0x08000000UL +#define GPIO_USB9S 0x00080000UL + +void init_ata_reset(void) +{ + debug("init_ata_reset\n"); + + /* Configure GPIO_WU6 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; + __asm__ volatile ("sync"); + + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0; + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0; + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0; + __asm__ volatile ("sync"); + + *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; + *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9; + __asm__ volatile ("sync"); + + if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; + __asm__ volatile ("sync"); + } +} + +int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int addr; + unsigned int size; + int i; + volatile unsigned long *ptr; + + addr = simple_strtol(argv[1], NULL, 16); + size = simple_strtol(argv[2], NULL, 16); + + printf("\nWriting at addr %08x, size %08x.\n", addr, size); + + while (1) { + ptr = (volatile unsigned long *)addr; + for (i = 0; i < (size >> 2); i++) { + *ptr++ = i; + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + putc('.'); + } + return 0; +} + +U_BOOT_CMD(writepci, 3, 1, do_writepci, + "writepci- Write some data to pcibus\n", + " \n" " - Write some data to pcibus.\n"); diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h new file mode 100644 index 0000000..22d0a55 --- /dev/null +++ b/board/esd/cpci5200/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x705f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c new file mode 100644 index 0000000..d76af02 --- /dev/null +++ b/board/esd/cpci5200/strataflash.c @@ -0,0 +1,804 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + +#define FLASH_MAN_CFI 0x01000000 + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char *cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, + uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, + uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size(ulong base, int banknum); +static int flash_write_cfiword(flash_info_t * info, ulong dest, + cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, + ulong tout, char *prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, + int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *) (info->start[sect] + (offset * info->portwidth))); +} + +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar *addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2 * info->portwidth) - 1] << 8) | + addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar *addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2 * info->portwidth) - 1] << 24) | + (addr[(info->portwidth) - 1] << 16) | + (addr[(4 * info->portwidth) - 1] << 8) | + addr[(3 * info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init(void) +{ + unsigned long size; + int i; + unsigned long address; + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + size += flash_info[i].size = flash_get_size(address, i); + address += CFG_FLASH_INCREMENT; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf + ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, flash_info[0].size, flash_info[i].size << 20); + } + } + +#if 0 /* test-only */ + /* Monitor protection ON by default */ +#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) + for (i = 0; + flash_info[0].start[i] < CFG_MONITOR_BASE + monitor_flash_len - 1; + i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if (info->flash_id != FLASH_MAN_CFI) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if (flash_full_status_check + (info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf(" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3), (info->chipwidth << 3)); + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf + (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, + info->buffer_size); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n"); + printf(" %08lX%5s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if ((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for (i = 0; i < aln; ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *) cp)); + + for (; (i < info->portwidth) && (cnt > 0); i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *) cp)); + if ((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while (cnt >= info->portwidth) { + i = info->buffer_size > cnt ? cnt : info->buffer_size; + if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -= i; + } +#else + /* handle the aligned part */ + while (cnt >= info->portwidth) { + cword.l = 0; + for (i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if ((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; i < info->portwidth; ++i, ++cp) { + flash_add_byte(info, &cword, (*(uchar *) cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if (prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if ((retcode = + flash_full_status_check(info, sector, info->erase_blk_tout, + prot ? "protect" : "unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if (prot == 0) { + int i; + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} + +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, + char *prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer(0); + while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, + info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, + ulong tout, char *prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if ((retcode == ERR_OK) + && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt, + info->start[sector]); + if (flash_isset + (info, sector, 0, + FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { + printf("Command Sequence Error.\n"); + } else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) { + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) { + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} + +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c) +{ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf) +{ + int i; + uchar *cp = (uchar *) cmdbuf; + for (i = 0; i < info->portwidth; i++) + *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, + uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * + */ +static int flash_detect_cfi(flash_info_t * info) +{ + + for (info->portwidth = FLASH_CFI_8BIT; + info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) { + for (info->chipwidth = FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, + FLASH_CMD_CFI); + if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') + && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, + 'R') + && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, + 'Y')) + return 1; + } + } + return 0; +} + +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size(ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio = 0; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; +#if 0 + invalidate_dcache_range(base, base + 0x400); +#endif + if (flash_detect_cfi(info)) { + + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = + flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); + + sect_cnt = 0; + sector = base; + for (i = 0; i < num_erase_regions; i++) { + if (i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = + flash_read_long(info, 0, + FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = + (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) + 1; + for (j = 0; j < erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = + flash_isset(info, sect_cnt, + FLASH_OFFSET_PROTECT, + FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = + (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * + size_ratio; + info->buffer_size = + (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = + (tmp * + (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = + (tmp * + (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = + (tmp * + (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) / + 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); +#ifdef DEBUG_FLASH + printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif +#ifdef DEBUG_FLASH + printf("size=%08x sectors=%08x \n", info->size, info->sector_count); +#endif + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *) dest; + + /* Check if Flash is (sufficiently) erased */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if (!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t * info, ulong addr) +{ + int sector; + for (sector = info->sector_count - 1; sector >= 0; sector--) { + if (addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, + int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if ((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, + FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = + flash_full_status_check(info, sector, + info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci5200/u-boot.lds b/board/esd/cpci5200/u-boot.lds new file mode 100644 index 0000000..f23432e --- /dev/null +++ b/board/esd/cpci5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/cpci750/64360.h b/board/esd/cpci750/64360.h new file mode 100644 index 0000000..262abf3 --- /dev/null +++ b/board/esd/cpci750/64360.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * for cpci750 Reinhard Arlt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * main board support/init for the cpci750. + */ + +#ifndef __64360_H__ +#define __64360_H__ + +/* CPU Configuration bits */ +#define CPU_CONF_ADDR_MISS_EN (1 << 8) +#define CPU_CONF_SINGLE_CPU (1 << 11) +#define CPU_CONF_ENDIANESS (1 << 12) +#define CPU_CONF_PIPELINE (1 << 13) +#define CPU_CONF_STOP_RETRY (1 << 17) +#define CPU_CONF_MULTI_DECODE (1 << 18) +#define CPU_CONF_DP_VALID (1 << 19) +#define CPU_CONF_PERR_PROP (1 << 22) +#define CPU_CONF_AACK_DELAY_2 (1 << 25) +#define CPU_CONF_AP_VALID (1 << 26) +#define CPU_CONF_REMAP_WR_DIS (1 << 27) + +/* CPU Master Control bits */ +#define CPU_MAST_CTL_ARB_EN (1 << 8) +#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) +#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) +#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) +#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) +#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) + +#endif /* __64360_H__ */ diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile new file mode 100644 index 0000000..0486729 --- /dev/null +++ b/board/esd/cpci750/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001 +# Josh Huber , Mission Critical Linux, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +SOBJS = misc.o + +OBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \ + mv_eth.o mpsc.o i2c.o \ + sdram_init.o strataflash.o ide.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/cpci750/config.mk b/board/esd/cpci750/config.mk new file mode 100644 index 0000000..7795dfa --- /dev/null +++ b/board/esd/cpci750/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2004 +# Reinhard Arlt +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# cpci750 board +# + +TEXT_BASE = 0xfff00000 diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c new file mode 100644 index 0000000..e4b062b --- /dev/null +++ b/board/esd/cpci750/cpci750.c @@ -0,0 +1,885 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com + * modifications for the cpci750 by reinhard.arlt@esd-electronics.com + */ + +/* + * cpci750.c - main board support/init for the esd cpci750. + */ + +#include +#include <74xx_7xx.h> +#include "../../Marvell/include/memory.h" +#include "../../Marvell/include/pci.h" +#include "../../Marvell/include/mv_gen_reg.h" +#include + +#include "eth.h" +#include "mpsc.h" +#include "i2c.h" +#include "64360.h" +#include "mv_regs.h" + +#undef DEBUG +/*#define DEBUG */ + +#ifdef CONFIG_PCI +#define MAP_PCI +#endif /* of CONFIG_PCI */ + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +extern void flush_data_cache (void); +extern void invalidate_l1_instruction_cache (void); + +/* ------------------------------------------------------------------------- */ + +/* this is the current GT register space location */ +/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ + +/* Unfortunately, we cant change it while we are in flash, so we initialize it + * to the "final" value. This means that any debug_led calls before + * board_early_init_f wont work right (like in cpu_init_f). + * See also my_remap_gt_regs below. (NTL) + */ + +void board_prebootm_init (void); +unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +int display_mem_map (void); + +/* ------------------------------------------------------------------------- */ + +/* + * This is a version of the GT register space remapping function that + * doesn't touch globals (meaning, it's ok to run from flash.) + * + * Unfortunately, this has the side effect that a writable + * INTERNAL_REG_BASE_ADDR is impossible. Oh well. + */ + +void my_remap_gt_regs (u32 cur_loc, u32 new_loc) +{ + u32 temp; + + /* check and see if it's already moved */ + +/* original ppcboot 1.1.6 source + + temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 20) + return; + + temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 20); + + out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); + + while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); +original ppcboot 1.1.6 source end */ + + temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 16) + return; + + temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 16); + + out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); + + while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); +} + +#ifdef CONFIG_PCI + +static void gt_pci_config (void) +{ + unsigned int stat; + unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ + + /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's + * config registers by writing ones to the bus and device. + * We then update the Virtual register with the correct value for the bus and device. + */ + if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ + GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); + + GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); + + GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); + GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, + (stat & 0xffff0000) | CFG_PCI_IDSEL); + + } + if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ + GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); + GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); + + GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); + GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, + (stat & 0xffff0000) | CFG_PCI_IDSEL); + } + + /* Enable master */ + PCI_MASTER_ENABLE (0, SELF); + PCI_MASTER_ENABLE (1, SELF); + + /* Enable PCI0/1 Mem0 and IO 0 disable all others */ + GT_REG_READ (BASE_ADDR_ENABLE, &stat); + stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 + << + 18); + stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); + GT_REG_WRITE (BASE_ADDR_ENABLE, stat); + + /* ronen- add write to pci remap registers for 64460. + in 64360 when writing to pci base go and overide remap automaticaly, + in 64460 it doesn't */ + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + + /* PCI interface settings */ + /* Timeout set to retry forever */ + GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); + GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); + + /* ronen - enable only CS0 and Internal reg!! */ + GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); + GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); + +/*ronen update the pci internal registers base address.*/ +#ifdef MAP_PCI + for (stat = 0; stat <= PCI_HOST1; stat++) + pciWriteConfigReg (stat, + PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, + SELF, CFG_GT_REGS); +#endif + +} +#endif + +/* Setup CPU interface paramaters */ +static void gt_cpu_config (void) +{ + cpu_t cpu = get_cpu_type (); + ulong tmp; + + /* cpu configuration register */ + tmp = GTREGREAD (CPU_CONFIGURATION); + + /* set the SINGLE_CPU bit see MV64360 P.399 */ +#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ + tmp |= CPU_CONF_SINGLE_CPU; +#endif + + tmp &= ~CPU_CONF_AACK_DELAY_2; + + tmp |= CPU_CONF_DP_VALID; + tmp |= CPU_CONF_AP_VALID; + + tmp |= CPU_CONF_PIPELINE; + + GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ + + /* CPU master control register */ + tmp = GTREGREAD (CPU_MASTER_CONTROL); + + tmp |= CPU_MAST_CTL_ARB_EN; + + if ((cpu == CPU_7400) || + (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { + + tmp |= CPU_MAST_CTL_CLEAN_BLK; + tmp |= CPU_MAST_CTL_FLUSH_BLK; + + } else { + /* cleanblock must be cleared for CPUs + * that do not support this command (603e, 750) + * see Res#1 */ + tmp &= ~CPU_MAST_CTL_CLEAN_BLK; + tmp &= ~CPU_MAST_CTL_FLUSH_BLK; + } + GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); +} + +/* + * board_early_init_f. + * + * set up gal. device mappings, etc. + */ +int board_early_init_f (void) +{ + + /* + * set up the GT the way the kernel wants it + * the call to move the GT register space will obviously + * fail if it has already been done, but we're going to assume + * that if it's not at the power-on location, it's where we put + * it last time. (huber) + */ + + my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + + /* No PCI in first release of Port To_do: enable it. */ +#ifdef CONFIG_PCI + gt_pci_config (); +#endif + /* mask all external interrupt sources */ + GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); + /* new in MV6436x */ + GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); + /* --------------------- */ + GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); + GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); + GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); + /* does not exist in MV6436x + GT_REG_WRITE(CPU_INT_0_MASK, 0); + GT_REG_WRITE(CPU_INT_1_MASK, 0); + GT_REG_WRITE(CPU_INT_2_MASK, 0); + GT_REG_WRITE(CPU_INT_3_MASK, 0); + --------------------- */ + + + /* ----- DEVICE BUS SETTINGS ------ */ + + /* + * EVB + * 0 - SRAM ???? + * 1 - RTC ???? + * 2 - UART ???? + * 3 - Flash checked 32Bit Intel Strata + * boot - BootCS checked 8Bit 29LV040B + * + */ + + /* + * the dual 7450 module requires burst access to the boot + * device, so the serial rom copies the boot device to the + * on-board sram on the eval board, and updates the correct + * registers to boot from the sram. (device0) + */ + + memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + + + /* configure device timing */ + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR); + +#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ + /* detect if we are booting from the 32 bit flash */ + if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { + /* 32 bit boot flash */ + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, + CFG_32BIT_BOOT_PAR); + } else { + /* 8 bit boot flash */ + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + } +#else + /* 8 bit boot flash only */ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +#endif + + + gt_cpu_config (); + + /* MPP setup */ + GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + + GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + DEBUG_LED0_ON (); + DEBUG_LED1_ON (); + DEBUG_LED2_ON (); + + return 0; +} + +/* various things to do after relocation */ + +int misc_init_r () +{ + icache_enable (); +#ifdef CFG_L2 + l2cache_enable (); +#endif +#ifdef CONFIG_MPSC + + mpsc_sdma_init (); + mpsc_init2 (); +#endif + +#if 0 + /* disable the dcache and MMU */ + dcache_lock (); +#endif + return 0; +} + +void after_reloc (ulong dest_addr, gd_t * gd) +{ + + memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE); + + display_mem_map (); + /* now, jump to the main ppcboot board init code */ + board_init_r (gd, dest_addr); + /* NOTREACHED */ +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + * + * right now, assume borad type. (there is just one...after all) + */ + +int checkboard (void) +{ + int l_type = 0; + + printf ("BOARD: %s\n", CFG_BOARD_NAME); + return (l_type); +} + +/* utility functions */ +void debug_led (int led, int mode) +{ +} + +int display_mem_map (void) +{ + int i, j; + unsigned int base, size, width; + + /* SDRAM */ + printf ("SD (DDR) RAM\n"); + for (i = 0; i <= BANK3; i++) { + base = memoryGetBankBaseAddress (i); + size = memoryGetBankSize (i); + if (size != 0) { + printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", + i, base, size >> 20); + } + } +#ifdef CONFIG_PCI + /* CPU's PCI windows */ + for (i = 0; i <= PCI_HOST1; i++) { + printf ("\nCPU's PCI %d windows\n", i); + base = pciGetSpaceBase (i, PCI_IO); + size = pciGetSpaceSize (i, PCI_IO); + printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, + size >> 20); + for (j = 0; + j <= + PCI_REGION0 + /*ronen currently only first PCI MEM is used 3 */ ; + j++) { + base = pciGetSpaceBase (i, j); + size = pciGetSpaceSize (i, j); + printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); + } + } +#endif /* of CONFIG_PCI */ + /* Devices */ + printf ("\nDEVICES\n"); + for (i = 0; i <= DEVICE3; i++) { + base = memoryGetDeviceBaseAddress (i); + size = memoryGetDeviceSize (i); + width = memoryGetDeviceWidth (i) * 8; + printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); + if (i == 0) + printf ("\t- FLASH\n"); + else if (i == 1) + printf ("\t- FLASH\n"); + else if (i == 2) + printf ("\t- FLASH\n"); + else + printf ("\t- RTC/REGS/CAN\n"); + } + + /* Bootrom */ + base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ + size = memoryGetDeviceSize (BOOT_DEVICE); + width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; + printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n", + base, size >> 20, width); + return (0); +} + +/* DRAM check routines copied from gw8260 */ + +#if defined (CFG_DRAM_TEST) + +/*********************************************************************/ +/* NAME: move64() - moves a double word (64-bit) */ +/* */ +/* DESCRIPTION: */ +/* this function performs a double word move from the data at */ +/* the source pointer to the location at the destination pointer. */ +/* */ +/* INPUTS: */ +/* unsigned long long *src - pointer to data to move */ +/* */ +/* OUTPUTS: */ +/* unsigned long long *dest - pointer to locate to move data */ +/* */ +/* RETURNS: */ +/* None */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* May cloober fr0. */ +/* */ +/*********************************************************************/ +static void move64 (unsigned long long *src, unsigned long long *dest) +{ + asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : : "fr0"); /* Clobbers fr0 */ + return; +} + + +#if defined (CFG_DRAM_TEST_DATA) + +unsigned long long pattern[] = { + 0xaaaaaaaaaaaaaaaaLL, + 0xccccccccccccccccLL, + 0xf0f0f0f0f0f0f0f0LL, + 0xff00ff00ff00ff00LL, + 0xffff0000ffff0000LL, + 0xffffffff00000000LL, + 0x00000000ffffffffLL, + 0x0000ffff0000ffffLL, + 0x00ff00ff00ff00ffLL, + 0x0f0f0f0f0f0f0f0fLL, + 0x3333333333333333LL, + 0x5555555555555555LL, +}; + +/*********************************************************************/ +/* NAME: mem_test_data() - test data lines for shorts and opens */ +/* */ +/* DESCRIPTION: */ +/* Tests data lines for shorts and opens by forcing adjacent data */ +/* to opposite states. Because the data lines could be routed in */ +/* an arbitrary manner the must ensure test patterns ensure that */ +/* every case is tested. By using the following series of binary */ +/* patterns every combination of adjacent bits is test regardless */ +/* of routing. */ +/* */ +/* ...101010101010101010101010 */ +/* ...110011001100110011001100 */ +/* ...111100001111000011110000 */ +/* ...111111110000000011111111 */ +/* */ +/* Carrying this out, gives us six hex patterns as follows: */ +/* */ +/* 0xaaaaaaaaaaaaaaaa */ +/* 0xcccccccccccccccc */ +/* 0xf0f0f0f0f0f0f0f0 */ +/* 0xff00ff00ff00ff00 */ +/* 0xffff0000ffff0000 */ +/* 0xffffffff00000000 */ +/* */ +/* The number test patterns will always be given by: */ +/* */ +/* log(base 2)(number data bits) = log2 (64) = 6 */ +/* */ +/* To test for short and opens to other signals on our boards. we */ +/* simply */ +/* test with the 1's complemnt of the paterns as well. */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* Assumes only one one SDRAM bank */ +/* */ +/*********************************************************************/ +int mem_test_data (void) +{ + unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long temp64 = 0; + int num_patterns = sizeof (pattern) / sizeof (pattern[0]); + int i; + unsigned int hi, lo; + + for (i = 0; i < num_patterns; i++) { + move64 (&(pattern[i]), pmem); + move64 (pmem, &temp64); + + /* hi = (temp64>>32) & 0xffffffff; */ + /* lo = temp64 & 0xffffffff; */ + /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ + + hi = (pattern[i] >> 32) & 0xffffffff; + lo = pattern[i] & 0xffffffff; + /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ + + if (temp64 != pattern[i]) { + printf ("\n Data Test Failed, pattern 0x%08x%08x", + hi, lo); + return 1; + } + } + + return 0; +} +#endif /* CFG_DRAM_TEST_DATA */ + +#if defined (CFG_DRAM_TEST_ADDRESS) +/*********************************************************************/ +/* NAME: mem_test_address() - test address lines */ +/* */ +/* DESCRIPTION: */ +/* This function performs a test to verify that each word im */ +/* memory is uniquly addressable. The test sequence is as follows: */ +/* */ +/* 1) write the address of each word to each word. */ +/* 2) verify that each location equals its address */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_address (void) +{ + volatile unsigned int *pmem = + (volatile unsigned int *) CFG_MEMTEST_START; + const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + unsigned int i; + + /* write address to each location */ + for (i = 0; i < size; i++) { + pmem[i] = i; + } + + /* verify each loaction */ + for (i = 0; i < size; i++) { + if (pmem[i] != i) { + printf ("\n Address Test Failed at 0x%x", i); + return 1; + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_ADDRESS */ + +#if defined (CFG_DRAM_TEST_WALK) +/*********************************************************************/ +/* NAME: mem_march() - memory march */ +/* */ +/* DESCRIPTION: */ +/* Marches up through memory. At each location verifies rmask if */ +/* read = 1. At each location write wmask if write = 1. Displays */ +/* failing address and pattern. */ +/* */ +/* INPUTS: */ +/* volatile unsigned long long * base - start address of test */ +/* unsigned int size - number of dwords(64-bit) to test */ +/* unsigned long long rmask - read verify mask */ +/* unsigned long long wmask - wrtie verify mask */ +/* short read - verifies rmask if read = 1 */ +/* short write - writes wmask if write = 1 */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_march (volatile unsigned long long *base, + unsigned int size, + unsigned long long rmask, + unsigned long long wmask, short read, short write) +{ + unsigned int i; + unsigned long long temp = 0; + unsigned int hitemp, lotemp, himask, lomask; + + for (i = 0; i < size; i++) { + if (read != 0) { + /* temp = base[i]; */ + move64 ((unsigned long long *) &(base[i]), &temp); + if (rmask != temp) { + hitemp = (temp >> 32) & 0xffffffff; + lotemp = temp & 0xffffffff; + himask = (rmask >> 32) & 0xffffffff; + lomask = rmask & 0xffffffff; + + printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); + return 1; + } + } + if (write != 0) { + /* base[i] = wmask; */ + move64 (&wmask, (unsigned long long *) &(base[i])); + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_WALK */ + +/*********************************************************************/ +/* NAME: mem_test_walk() - a simple walking ones test */ +/* */ +/* DESCRIPTION: */ +/* Performs a walking ones through entire physical memory. The */ +/* test uses as series of memory marches, mem_march(), to verify */ +/* and write the test patterns to memory. The test sequence is as */ +/* follows: */ +/* 1) march writing 0000...0001 */ +/* 2) march verifying 0000...0001 , writing 0000...0010 */ +/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ +/* the write mask equals 1000...0000 */ +/* 4) march verifying 1000...0000 */ +/* The test fails if any of the memory marches return a failure. */ +/* */ +/* OUTPUTS: */ +/* Displays which pass on the memory test is executing */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_walk (void) +{ + unsigned long long mask; + volatile unsigned long long *pmem = + (volatile unsigned long long *) CFG_MEMTEST_START; + const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + + unsigned int i; + + mask = 0x01; + + printf ("Initial Pass"); + mem_march (pmem, size, 0x0, 0x1, 0, 1); + + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + + for (i = 0; i < 63; i++) { + printf ("Pass %2d", i + 2); + if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { + /*printf("mask: 0x%x, pass: %d, ", mask, i); */ + return 1; + } + mask = mask << 1; + printf ("\b\b\b\b\b\b\b"); + } + + printf ("Last Pass"); + if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { + /* printf("mask: 0x%x", mask); */ + return 1; + } + printf ("\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b"); + + return 0; +} + +/*********************************************************************/ +/* NAME: testdram() - calls any enabled memory tests */ +/* */ +/* DESCRIPTION: */ +/* Runs memory tests if the environment test variables are set to */ +/* 'y'. */ +/* */ +/* INPUTS: */ +/* testdramdata - If set to 'y', data test is run. */ +/* testdramaddress - If set to 'y', address test is run. */ +/* testdramwalk - If set to 'y', walking ones test is run */ +/* */ +/* OUTPUTS: */ +/* None */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int testdram (void) +{ + char *s; + int rundata = 0; + int runaddress = 0; + int runwalk = 0; + +#ifdef CFG_DRAM_TEST_DATA + s = getenv ("testdramdata"); + rundata = (s && (*s == 'y')) ? 1 : 0; +#endif +#ifdef CFG_DRAM_TEST_ADDRESS + s = getenv ("testdramaddress"); + runaddress = (s && (*s == 'y')) ? 1 : 0; +#endif +#ifdef CFG_DRAM_TEST_WALK + s = getenv ("testdramwalk"); + runwalk = (s && (*s == 'y')) ? 1 : 0; +#endif + + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + } +#ifdef CFG_DRAM_TEST_DATA + if (rundata == 1) { + printf ("Test DATA ... "); + if (mem_test_data () == 1) { + printf ("failed \n"); + return 1; + } else + printf ("ok \n"); + } +#endif +#ifdef CFG_DRAM_TEST_ADDRESS + if (runaddress == 1) { + printf ("Test ADDRESS ... "); + if (mem_test_address () == 1) { + printf ("failed \n"); + return 1; + } else + printf ("ok \n"); + } +#endif +#ifdef CFG_DRAM_TEST_WALK + if (runwalk == 1) { + printf ("Test WALKING ONEs ... "); + if (mem_test_walk () == 1) { + printf ("failed \n"); + return 1; + } else + printf ("ok \n"); + } +#endif + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf ("passed\n"); + } + return 0; + +} +#endif /* CFG_DRAM_TEST */ + +/* ronen - the below functions are used by the bootm function */ +/* - we map the base register to fbe00000 (same mapping as in the LSP) */ +/* - we turn off the RX gig dmas - to prevent the dma from overunning */ +/* the kernel data areas. */ +/* - we diable and invalidate the icache and dcache. */ +void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) +{ + u32 temp; + + temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 16) + return; + + temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 16); + + out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); + + while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | + new_loc | + (INTERNAL_SPACE_DECODE))))) + != temp); + +} + +void board_prebootm_init () +{ + +/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ + GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); + +/* Stop GigE Rx DMA engines */ + GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); +/* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */ +/* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */ + +/* Relocate MV64360 internal regs */ + my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS); + + icache_disable (); + invalidate_l1_instruction_cache (); + flush_data_cache (); + dcache_disable (); +} diff --git a/board/esd/cpci750/eth.h b/board/esd/cpci750/eth.h new file mode 100644 index 0000000..aab32d2 --- /dev/null +++ b/board/esd/cpci750/eth.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * eth.h - header file for the polled mode GT ethernet driver + */ + +#ifndef __EVB64360_ETH_H__ +#define __EVB64360_ETH_H__ + +#include +#include +#include +#include + + +int db64360_eth0_poll(void); +int db64360_eth0_transmit(unsigned int s, volatile char *p); +void db64360_eth0_disable(void); +bool network_start(bd_t *bis); + + +#endif /* __EVB64360_ETH_H__ */ diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c new file mode 100644 index 0000000..5b1bc01 --- /dev/null +++ b/board/esd/cpci750/i2c.c @@ -0,0 +1,487 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the DB64360 board by Ingo.Assmus@keymile.com + * extra improvments by Brain Waite + * for cpci750 by reinhard.arlt@esd-electronics.com + */ +#include +#include +#include +#include "../../Marvell/include/mv_gen_reg.h" +#include "../../Marvell/include/core.h" + +#define I2C_DELAY 100 +#undef DEBUG_I2C + +#ifdef DEBUG_I2C +#define DP(x) x +#else +#define DP(x) +#endif + +/* Assuming that there is only one master on the bus (us) */ + +static void i2c_init (int speed, int slaveaddr) +{ + unsigned int n, m, freq, margin, power; + unsigned int actualN = 0, actualM = 0; + unsigned int minMargin = 0xffffffff; + unsigned int tclk = CFG_TCLK; + unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ + + DP (puts ("i2c_init\n")); +/* gtI2cMasterInit */ + for (n = 0; n < 8; n++) { + for (m = 0; m < 16; m++) { + power = 2 << n; /* power = 2^(n+1) */ + freq = tclk / (10 * (m + 1) * power); + if (i2cFreq > freq) + margin = i2cFreq - freq; + else + margin = freq - i2cFreq; + if (margin < minMargin) { + minMargin = margin; + actualN = n; + actualM = m; + } + } + } + + DP (puts ("setup i2c bus\n")); + + /* Setup bus */ + /* gtI2cReset */ + GT_REG_WRITE (I2C_SOFT_RESET, 0); + asm(" sync"); + GT_REG_WRITE (I2C_CONTROL, 0); + asm(" sync"); + + DP (puts ("set baudrate\n")); + + GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); + asm(" sync"); + + DP (puts ("udelay...\n")); + + udelay (I2C_DELAY); + + GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); + asm(" sync"); +} + + +static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit) +{ + unsigned int status, data, bits = 7; + unsigned int control; + int count = 0; + + DP (puts ("i2c_select_device\n")); + + /* Output slave address */ + + if (ten_bit) { + bits = 10; + } + + GT_REG_READ (I2C_CONTROL, &control); + control |= (0x1 << 2); + GT_REG_WRITE (I2C_CONTROL, control); + asm(" sync"); + + GT_REG_READ (I2C_CONTROL, &control); + control |= (0x1 << 5); /* generate the I2C_START_BIT */ + GT_REG_WRITE (I2C_CONTROL, control); + asm(" sync"); + RESET_REG_BITS (I2C_CONTROL, (0x01 << 3)); + asm(" sync"); + + GT_REG_READ (I2C_CONTROL, &status); + while ((status & 0x08) != 0x08) { + GT_REG_READ (I2C_CONTROL, &status); + } + + + count = 0; + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){ + if (count > 200) { +#ifdef DEBUG_I2C + printf ("Failed to set startbit: 0x%02x\n", status); +#endif + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + asm(" sync"); + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + + DP (puts ("i2c_select_device:write addr byte\n")); + + /* assert the address */ + + data = (dev_addr << 1); + /* set the read bit */ + data |= read; + GT_REG_WRITE (I2C_DATA, data); + asm(" sync"); + RESET_REG_BITS (I2C_CONTROL, BIT3); + asm(" sync"); + + GT_REG_READ (I2C_CONTROL, &status); + while ((status & 0x08) != 0x08) { + GT_REG_READ (I2C_CONTROL, &status); + } + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count = 0; + while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { + if (count > 200) { +#ifdef DEBUG_I2C + printf ("Failed to write address: 0x%02x\n", status); +#endif + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + asm(" sync"); + count++; + } + + if (bits == 10) { + printf ("10 bit I2C addressing not yet implemented\n"); + return (0xff); + } + + return (0); +} + +static uchar i2c_get_data (uchar * return_data, int len) +{ + + unsigned int data, status; + int count = 0; + + DP (puts ("i2c_get_data\n")); + + while (len) { + + RESET_REG_BITS (I2C_CONTROL, BIT3); + asm(" sync"); + + /* Get and return the data */ + + GT_REG_READ (I2C_CONTROL, &status); + while ((status & 0x08) != 0x08) { + GT_REG_READ (I2C_CONTROL, &status); + } + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x50) { + if (count > 20) { +#ifdef DEBUG_I2C + printf ("Failed to get data len status: 0x%02x\n", status); +#endif + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + asm(" sync"); + return 0; + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + GT_REG_READ (I2C_DATA, &data); + len--; + *return_data = (uchar) data; + return_data++; + + } + RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3); + asm(" sync"); + count = 0; + + GT_REG_READ (I2C_CONTROL, &status); + while ((status & 0x08) != 0x08) { + GT_REG_READ (I2C_CONTROL, &status); + } + + while ((status & 0xff) != 0x58) { + if (count > 2000) { + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */ + asm(" sync"); + RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); + asm(" sync"); + + return (0); +} + + +static uchar i2c_write_data (unsigned int *data, int len) +{ + unsigned int status; + int count; + unsigned int temp; + unsigned int *temp_ptr = data; + + DP (puts ("i2c_write_data\n")); + + while (len) { + count = 0; + temp = (unsigned int) (*temp_ptr); + GT_REG_WRITE (I2C_DATA, temp); + asm(" sync"); + RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); + asm(" sync"); + + GT_REG_READ (I2C_CONTROL, &status); + while ((status & 0x08) != 0x08) { + GT_REG_READ (I2C_CONTROL, &status); + } + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x28) { + if (count > 200) { + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + asm(" sync"); + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + len--; + temp_ptr++; + } + return (0); +} + + +static uchar i2c_write_byte (unsigned char *data, int len) +{ + unsigned int status; + int count; + unsigned int temp; + unsigned char *temp_ptr = data; + + DP (puts ("i2c_write_byte\n")); + + while (len) { + count = 0; + /* Set and assert the data */ + temp = *temp_ptr; + GT_REG_WRITE (I2C_DATA, temp); + asm(" sync"); + RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); + asm(" sync"); + + + GT_REG_READ (I2C_CONTROL, &status); + while ((status & 0x08) != 0x08) { + GT_REG_READ (I2C_CONTROL, &status); + } + + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x28) { + if (count > 200) { + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ + asm(" sync"); + return (status); + } + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); + count++; + } + len--; + temp_ptr++; + } + return (0); +} + +static uchar +i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit, + int alen) +{ + uchar status; + unsigned int table[2]; + + table[1] = (offset ) & 0x0ff; /* low byte */ + table[0] = (offset >> 8) & 0x0ff; /* high byte */ + + DP (puts ("i2c_set_dev_offset\n")); + + status = i2c_select_device (dev_addr, 0, ten_bit); + if (status) { +#ifdef DEBUG_I2C +22 printf ("Failed to select device setting offset: 0x%02x\n", + status); +#endif + return status; + } +/* check the address offset length */ + if (alen == 0) + /* no address offset */ + return (0); + else if (alen == 1) { + /* 1 byte address offset */ + status = i2c_write_data (&offset, 1); + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to write data: 0x%02x\n", status); +#endif + return status; + } + } else if (alen == 2) { + /* 2 bytes address offset */ + status = i2c_write_data (table, 2); + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to write data: 0x%02x\n", status); +#endif + return status; + } + } else { + /* address offset unknown or not supported */ + printf ("Address length offset %d is not supported\n", alen); + return 1; + } + return 0; /* sucessful completion */ +} + +uchar +i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, + int len) +{ + uchar status = 0; + unsigned int i2cFreq = CFG_I2C_SPEED; + + DP (puts ("i2c_read\n")); + + i2c_init (i2cFreq, 0); /* set the i2c frequency */ + + status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to set slave address & offset: 0x%02x\n", + status); +#endif + return status; + } + + status = i2c_select_device (dev_addr, 1, 0); + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to select device for data read: 0x%02x\n", + status); +#endif + return status; + } + + status = i2c_get_data (data, len); + if (status) { +#ifdef DEBUG_I2C + printf ("Data not read: 0x%02x\n", status); +#endif + return status; + } + + return 0; +} + + +void i2c_stop (void) +{ + GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); + asm(" sync"); +} + + +uchar +i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, + int len) +{ + uchar status = 0; + unsigned int i2cFreq = CFG_I2C_SPEED; + + DP (puts ("i2c_write\n")); + + i2c_init (i2cFreq, 0); /* set the i2c frequency */ + + status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to set slave address & offset: 0x%02x\n", + status); +#endif + return status; + } + + + status = i2c_write_byte (data, len); /* write the data */ + if (status) { +#ifdef DEBUG_I2C + printf ("Data not written: 0x%02x\n", status); +#endif + return status; + } + /* issue a stop bit */ + i2c_stop (); + return 0; +} + + +int i2c_probe (uchar chip) +{ + +#ifdef DEBUG_I2C + unsigned int i2c_status; +#endif + uchar status = 0; + unsigned int i2cFreq = CFG_I2C_SPEED; + + DP (puts ("i2c_probe\n")); + + i2c_init (i2cFreq, 0); /* set the i2c frequency */ + + status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */ + if (status) { +#ifdef DEBUG_I2C + printf ("Failed to set slave address: 0x%02x\n", status); +#endif + return (int) status; + } +#ifdef DEBUG_I2C + GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status); + printf ("address %#x returned %#x\n", chip, i2c_status); +#endif + /* issue a stop bit */ + i2c_stop (); + return 0; /* successful completion */ +} diff --git a/board/esd/cpci750/i2c.h b/board/esd/cpci750/i2c.h new file mode 100644 index 0000000..b669ff0 --- /dev/null +++ b/board/esd/cpci750/i2c.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the DB64360 board by Ingo.Assmus@keymile.com + */ + +#ifndef __I2C_H__ +#define __I2C_H__ + +/* function declarations */ +uchar i2c_read(uchar, unsigned int, int, uchar*, int); + +#endif diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c new file mode 100644 index 0000000..bea99ce --- /dev/null +++ b/board/esd/cpci750/ide.c @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* ide.c - ide support functions */ + + +#include +#ifdef CFG_CMD_IDE +#include +#include +#include + +extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; + +int ide_preinit (void) +{ + int status; + pci_dev_t devbusfn; + int l; + + status = 1; + for (l = 0; l < CFG_IDE_MAXBUS; l++) { + ide_bus_offset[l] = -ATA_STATUS; + } + devbusfn = pci_find_device (0x1103, 0x0004, 0); + if (devbusfn != -1) { + status = 0; + + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, + (u32 *) & ide_bus_offset[0]); + ide_bus_offset[0] &= 0xfffffffe; + ide_bus_offset[0] += CFG_PCI0_IO_SPACE; + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, + (u32 *) & ide_bus_offset[1]); + ide_bus_offset[1] &= 0xfffffffe; + ide_bus_offset[1] += CFG_PCI0_IO_SPACE; + } + return (status); +} + +void ide_set_reset (int flag) { + return; +} + +#endif /* of CONFIG_CMDS_IDE */ diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h new file mode 100644 index 0000000..bca0e1f --- /dev/null +++ b/board/esd/cpci750/local.h @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * include/local.h - local configuration options, board specific + */ + +#ifndef __LOCAL_H +#define __LOCAL_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +/* This tells PPCBoot that the config options are compiled in */ +/* #undef ENV_IS_EMBEDDED */ +/* Don't touch this! PPCBOOT figures this out based on other + * magic. */ + +/* Uncomment and define any of the below options */ + +/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ +#define CONFIG_750FX /* The 750FX doesn't support as many things in L2CR like 750CX*/ + +/* These want string arguments */ +/* #define CONFIG_BOOTARGS */ +/* #define CONFIG_BOOTCOMMAND */ +/* #define CONFIG_RAMBOOTCOMMAND */ +/* #define CONFIG_NFSBOOTCOMMAND */ +/* #define CFG_AUTOLOAD */ +/* #define CONFIG_PREBOOT */ + +/* These don't */ + +/* #define CONFIG_BOOTDELAY */ +/* #define CONFIG_BAUDRATE */ +/* #define CONFIG_LOADS_ECHO */ +/* #define CONFIG_ETHADDR */ +/* #define CONFIG_ETH2ADDR */ +/* #define CONFIG_ETH3ADDR */ +/* #define CONFIG_IPADDR */ +/* #define CONFIG_SERVERIP */ +/* #define CONFIG_ROOTPATH */ +/* #define CONFIG_GATEWAYIP */ +/* #define CONFIG_NETMASK */ +/* #define CONFIG_HOSTNAME */ +/* #define CONFIG_BOOTFILE */ +/* #define CONFIG_LOADADDR */ + +/* these hardware addresses are pretty bogus, please change them to + suit your needs */ + +/* first ethernet */ +/* #define CONFIG_ETHADDR 86:06:2d:7e:c6:53 */ +#define CONFIG_ETHADDR 64:36:00:00:00:01 + +/* next two ethernet hwaddrs */ +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 86:06:2d:7e:c6:54 +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 86:06:2d:7e:c6:55 + +#define CONFIG_ENV_OVERWRITE +#endif /* __CONFIG_H */ diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S new file mode 100644 index 0000000..160b1d3 --- /dev/null +++ b/board/esd/cpci750/misc.S @@ -0,0 +1,245 @@ +#include +#include <74xx_7xx.h> +#include "version.h" + +#include +#include + +#include +#include + +#include "../../Marvell/include/mv_gen_reg.h" + +#ifdef CONFIG_ECC + /* Galileo specific asm code for initializing ECC */ + .globl board_relocate_rom +board_relocate_rom: + mflr r7 + /* update the location of the GT registers */ + lis r11, CFG_GT_REGS@h + /* if we're using ECC, we must use the DMA engine to copy ourselves */ + bl start_idma_transfer_0 + bl wait_for_idma_0 + bl stop_idma_engine_0 + + mtlr r7 + blr + + .globl board_init_ecc +board_init_ecc: + mflr r7 + /* NOTE: r10 still contains the location we've been relocated to + * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + + /* now that we're running from ram, init the rest of main memory + * for ECC use */ + lis r8, CFG_MONITOR_LEN@h + ori r8, r8, CFG_MONITOR_LEN@l + + divw r3, r10, r8 + + /* set up the counter, and init the starting address */ + mtctr r3 + li r12, 0 + + /* bytes per transfer */ + mr r5, r8 +about_to_init_ecc: +1: mr r3, r12 + mr r4, r12 + bl start_idma_transfer_0 + bl wait_for_idma_0 + bl stop_idma_engine_0 + add r12, r12, r8 + bdnz 1b + + mtlr r7 + blr + + /* r3: dest addr + * r4: source addr + * r5: byte count + * r11: gt regbase + * trashes: r6, r5 + */ +start_idma_transfer_0: + /* set the byte count, including the OWN bit */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_BYTE_COUNT + stwbrx r5, 0, (r6) + + /* set the source address */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS + stwbrx r4, 0, (r6) + + /* set the dest address */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS + stwbrx r3, 0, (r6) + + /* set the next record pointer */ + li r5, 0 + mr r6, r11 + ori r6, r6, CHANNEL0NEXT_RECORD_POINTER + stwbrx r5, 0, (r6) + + /* set the low control register */ + /* bit 9 is NON chained mode, bit 31 is new style descriptors. + bit 12 is channel enable */ + ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) + /* 15 shifted by 16 (oris) == bit 31 */ + oris r5, r5, (1 << 15) + mr r6, r11 + ori r6, r6, CHANNEL0CONTROL + stwbrx r5, 0, (r6) + + blr + + /* this waits for the bytecount to return to zero, indicating + * that the trasfer is complete */ +wait_for_idma_0: + mr r5, r11 + lis r6, 0xff + ori r6, r6, 0xffff + ori r5, r5, CHANNEL0_DMA_BYTE_COUNT +1: lwbrx r4, 0, (r5) + and. r4, r4, r6 + bne 1b + + blr + + /* this turns off channel 0 of the idma engine */ +stop_idma_engine_0: + /* shut off the DMA engine */ + li r5, 0 + mr r6, r11 + ori r6, r6, CHANNEL0CONTROL + stwbrx r5, 0, (r6) + + blr +#endif + +#ifdef CFG_BOARD_ASM_INIT + /* NOTE: trashes r3-r7 */ + .globl board_asm_init +board_asm_init: + /* just move the GT registers to where they belong */ + lis r3, CFG_DFL_GT_REGS@h + ori r3, r3, CFG_DFL_GT_REGS@l + lis r4, CFG_GT_REGS@h + ori r4, r4, CFG_GT_REGS@l + li r5, INTERNAL_SPACE_DECODE + + /* test to see if we've already moved */ + lwbrx r6, r5, r4 + andi. r6, r6, 0xffff + /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ +/* rlwinm r7, r4, 8, 16, 31 + rlwinm r7, r4, 12, 16, 31 */ /* original */ + rlwinm r7, r4, 16, 16, 31 + /* -----------------------------------------------------*/ + cmp cr0, r7, r6 + beqlr + + /* nope, have to move the registers */ + lwbrx r6, r5, r3 + andis. r6, r6, 0xffff + or r6, r6, r7 + stwbrx r6, r5, r3 + + /* now, poll for the change */ +1: lwbrx r7, r5, r4 + cmp cr0, r7, r6 + bne 1b + + lis r3, CFG_INT_SRAM_BASE@h + ori r3, r3, CFG_INT_SRAM_BASE@l + rlwinm r3, r3, 16, 16, 31 + lis r4, CFG_GT_REGS@h + ori r4, r4, CFG_GT_REGS@l + li r5, INTEGRATED_SRAM_BASE_ADDR + stwbrx r3, r5, r4 + +2: lwbrx r6, r5, r4 + cmp cr0, r3, r6 + bne 2b + + /* done! */ + blr +#endif + +/* For use of the debug LEDs */ + .global led_on0_relocated +led_on0_relocated: + xor r21, r21, r21 + xor r18, r18, r18 + lis r18, 0xFC80 + ori r18, r18, 0x8000 +/* stw r21, 0x0(r18) */ + sync + blr + + .global led_off0_relocated +led_off0_relocated: + xor r21, r21, r21 + xor r18, r18, r18 + lis r18, 0xFC81 + ori r18, r18, 0x4000 +/* stw r21, 0x0(r18) */ + sync + blr + + .global led_on0 +led_on0: + xor r18, r18, r18 + lis r18, 0x1c80 + ori r18, r18, 0x8000 +/* stw r18, 0x0(r18) */ + sync + blr + + .global led_off0 +led_off0: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0x4000 +/* stw r18, 0x0(r18) */ + sync + blr + + .global led_on1 +led_on1: + xor r18, r18, r18 + lis r18, 0x1c80 + ori r18, r18, 0xc000 +/* stw r18, 0x0(r18) */ + sync + blr + + .global led_off1 +led_off1: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0x8000 +/* stw r18, 0x0(r18) */ + sync + blr + + .global led_on2 +led_on2: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0x0000 +/* stw r18, 0x0(r18) */ + sync + blr + + .global led_off2 +led_off2: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0xc000 +/* stw r18, 0x0(r18) */ + sync + blr diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c new file mode 100644 index 0000000..52398b2 --- /dev/null +++ b/board/esd/cpci750/mpsc.c @@ -0,0 +1,1018 @@ +/* + * (C) Copyright 2001 + * John Clemens , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * changes for Marvell DB64360 eval board 2003 by Ingo Assmus + * + ************************************************************************/ + +/* + * mpsc.c - driver for console over the MPSC. + */ + + +#include +#include +#include + +#include +#include "mpsc.h" + +#include "mv_regs.h" + +#include "../../Marvell/include/memory.h" + +/* Define this if you wish to use the MPSC as a register based UART. + * This will force the serial port to not use the SDMA engine at all. + */ + +#undef CONFIG_MPSC_DEBUG_PORT + + +int (*mpsc_putchar) (char ch) = mpsc_putchar_early; +char (*mpsc_getchar) (void) = mpsc_getchar_debug; +int (*mpsc_test_char) (void) = mpsc_test_char_debug; + + +static volatile unsigned int *rx_desc_base = NULL; +static unsigned int rx_desc_index = 0; +static volatile unsigned int *tx_desc_base = NULL; +static unsigned int tx_desc_index = 0; + +/* local function declarations */ +static int galmpsc_connect (int channel, int connect); +static int galmpsc_route_rx_clock (int channel, int brg); +static int galmpsc_route_tx_clock (int channel, int brg); +static int galmpsc_write_config_regs (int mpsc, int mode); +static int galmpsc_config_channel_regs (int mpsc); +static int galmpsc_set_char_length (int mpsc, int value); +static int galmpsc_set_stop_bit_length (int mpsc, int value); +static int galmpsc_set_parity (int mpsc, int value); +static int galmpsc_enter_hunt (int mpsc); +static int galmpsc_set_brkcnt (int mpsc, int value); +static int galmpsc_set_tcschar (int mpsc, int value); +static int galmpsc_set_snoop (int mpsc, int value); +static int galmpsc_shutdown (int mpsc); + +static int galsdma_set_RFT (int channel); +static int galsdma_set_SFM (int channel); +static int galsdma_set_rxle (int channel); +static int galsdma_set_txle (int channel); +static int galsdma_set_burstsize (int channel, unsigned int value); +static int galsdma_set_RC (int channel, unsigned int value); + +static int galbrg_set_CDV (int channel, int value); +static int galbrg_enable (int channel); +static int galbrg_disable (int channel); +static int galbrg_set_clksrc (int channel, int value); +static int galbrg_set_CUV (int channel, int value); + +static void galsdma_enable_rx (void); +static int galsdma_set_mem_space (unsigned int memSpace, + unsigned int memSpaceTarget, + unsigned int memSpaceAttr, + unsigned int baseAddress, + unsigned int size); + + +#define SOFTWARE_CACHE_MANAGEMENT + +#ifdef SOFTWARE_CACHE_MANAGEMENT +#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} +#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} +#else +#define FLUSH_DCACHE(a,b) +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) +#define INVALIDATE_DCACHE(a,b) +#endif + +#ifdef CONFIG_MPSC_DEBUG_PORT +static void mpsc_debug_init (void) +{ + + volatile unsigned int temp; + + /* Clear the CFR (CHR4) */ + /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ + temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); + temp &= 0xffffff00; + temp |= BIT29; + GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), + temp); + + /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ + temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); + temp |= (BIT12 | BIT15); + GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), + temp); + + /* Set int mask */ + temp = GTREGREAD (GALMPSC_0_INT_MASK); + temp |= BIT6; + GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); +} +#endif + +char mpsc_getchar_debug (void) +{ + volatile int temp; + volatile unsigned int cause; + + cause = GTREGREAD (GALMPSC_0_INT_CAUSE); + while ((cause & BIT6) == 0) { + cause = GTREGREAD (GALMPSC_0_INT_CAUSE); + } + + temp = GTREGREAD (GALMPSC_CHANNELREG_10 + + (CHANNEL * GALMPSC_REG_GAP)); + /* By writing 1's to the set bits, the register is cleared */ + GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), + temp); + GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); + return (temp >> 16) & 0xff; +} + +/* special function for running out of flash. doesn't modify any + * global variables [josh] */ +int mpsc_putchar_early (char ch) +{ + DECLARE_GLOBAL_DATA_PTR; + int mpsc = CHANNEL; + int temp = + GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + galmpsc_set_tcschar (mpsc, ch); + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), + temp | 0x200); + +#define MAGIC_FACTOR (10*1000000) + + udelay (MAGIC_FACTOR / gd->baudrate); + return 0; +} + +/* This is used after relocation, see serial.c and mpsc_init2 */ +static int mpsc_putchar_sdma (char ch) +{ + volatile unsigned int *p; + unsigned int temp; + + + /* align the descriptor */ + p = tx_desc_base; + memset ((void *) p, 0, 8 * sizeof (unsigned int)); + + /* fill one 64 bit buffer */ + /* word swap, pad with 0 */ + p[4] = 0; /* x */ + p[5] = (unsigned int) ch; /* x */ + + /* CHANGED completely according to GT64260A dox - NTL */ + p[0] = 0x00010001; /* 0 */ + p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ + p[2] = 0; /* 8 */ + p[3] = (unsigned int) &p[4]; /* c */ + +#if 0 + p[9] = DESC_FIRST | DESC_LAST; + p[10] = (unsigned int) &p[0]; + p[11] = (unsigned int) &p[12]; +#endif + + FLUSH_DCACHE (&p[0], &p[8]); + + GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), + (unsigned int) &p[0]); + GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), + (unsigned int) &p[0]); + + temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); + temp |= (TX_DEMAND | TX_STOP); + GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); + + INVALIDATE_DCACHE (&p[1], &p[2]); + + while (p[1] & DESC_OWNER_BIT) { + udelay (100); + INVALIDATE_DCACHE (&p[1], &p[2]); + } + return 0; +} + +char mpsc_getchar_sdma (void) +{ + static unsigned int done = 0; + volatile char ch; + unsigned int len = 0, idx = 0, temp; + + volatile unsigned int *p; + + + do { + p = &rx_desc_base[rx_desc_index * 8]; + + INVALIDATE_DCACHE (&p[0], &p[1]); + /* Wait for character */ + while (p[1] & DESC_OWNER_BIT) { + udelay (100); + INVALIDATE_DCACHE (&p[0], &p[1]); + } + + /* Handle error case */ + if (p[1] & (1 << 15)) { + printf ("oops, error: %08x\n", p[1]); + + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + + (CHANNEL * GALMPSC_REG_GAP)); + temp |= (1 << 23); + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + + (CHANNEL * GALMPSC_REG_GAP), temp); + + /* Can't poll on abort bit, so we just wait. */ + udelay (100); + + galsdma_enable_rx (); + } + + /* Number of bytes left in this descriptor */ + len = p[0] & 0xffff; + + if (len) { + /* Where to look */ + idx = 5; + if (done > 3) + idx = 4; + if (done > 7) + idx = 7; + if (done > 11) + idx = 6; + + INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); + ch = p[idx] & 0xff; + done++; + } + + if (done < len) { + /* this descriptor has more bytes still + * shift down the char we just read, and leave the + * buffer in place for the next time around + */ + p[idx] = p[idx] >> 8; + FLUSH_DCACHE (&p[idx], &p[idx + 1]); + } + + if (done == len) { + /* nothing left in this descriptor. + * go to next one + */ + p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; + p[0] = 0x00100000; + FLUSH_DCACHE (&p[0], &p[1]); + /* Next descriptor */ + rx_desc_index = (rx_desc_index + 1) % RX_DESC; + done = 0; + } + } while (len == 0); /* galileo bug.. len might be zero */ + + return ch; +} + + +int mpsc_test_char_debug (void) +{ + if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) + return 0; + else { + return 1; + } +} + + +int mpsc_test_char_sdma (void) +{ + volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; + + INVALIDATE_DCACHE (&p[1], &p[2]); + + if (p[1] & DESC_OWNER_BIT) + return 0; + else + return 1; +} + +int mpsc_init (int baud) +{ + /* BRG CONFIG */ + galbrg_set_baudrate (CHANNEL, baud); + galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ + galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ + galbrg_enable (CHANNEL); /* Enable BRG */ + + /* Set up clock routing */ + galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ + + galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ + galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ + + /* reset MPSC state */ + galmpsc_shutdown (CHANNEL); + + /* SDMA CONFIG */ + galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ + galsdma_set_txle (CHANNEL); + galsdma_set_rxle (CHANNEL); + galsdma_set_RC (CHANNEL, 0xf); + galsdma_set_SFM (CHANNEL); + galsdma_set_RFT (CHANNEL); + + /* MPSC CONFIG */ + galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); + galmpsc_config_channel_regs (CHANNEL); + galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ + galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ + galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ + +#ifdef CONFIG_MPSC_DEBUG_PORT + mpsc_debug_init (); +#endif + + /* COMM_MPSC CONFIG */ +#ifdef SOFTWARE_CACHE_MANAGEMENT + galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ +#else + galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ +#endif + + return 0; +} + + +void mpsc_sdma_init (void) +{ +/* Setup SDMA channel0 SDMA_CONFIG_REG*/ + GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); + +/* Enable MPSC-Window0 for DRAM Bank0 */ + if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT, + MV64360_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_0_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK0)) != true) + printf ("%s: SDMA_Window0 memory setup failed !!! \n", + __FUNCTION__); + + +/* Disable MPSC-Window1 */ + if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT, + MV64360_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_1_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK3)) != true) + printf ("%s: SDMA_Window1 memory setup failed !!! \n", + __FUNCTION__); + + +/* Disable MPSC-Window2 */ + if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT, + MV64360_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_2_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK3)) != true) + printf ("%s: SDMA_Window2 memory setup failed !!! \n", + __FUNCTION__); + + +/* Disable MPSC-Window3 */ + if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT, + MV64360_SDMA_DRAM_CS_0_TARGET, + 0, + memoryGetBankBaseAddress + (CS_3_LOW_DECODE_ADDRESS), + memoryGetBankSize (BANK3)) != true) + printf ("%s: SDMA_Window3 memory setup failed !!! \n", + __FUNCTION__); + +/* Setup MPSC0 access mode Window0 full access */ + GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, + (MV64360_SDMA_WIN_ACCESS_FULL << + (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); + +/* Setup MPSC1 access mode Window1 full access */ + GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, + (MV64360_SDMA_WIN_ACCESS_FULL << + (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); + +/* Setup MPSC internal address space base address */ + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + +/* no high address remap*/ + GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); + GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); + +/* clear interrupt cause register for MPSC (fault register)*/ + GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); +} + + +void mpsc_init2 (void) +{ + int i; + +#ifndef CONFIG_MPSC_DEBUG_PORT + mpsc_putchar = mpsc_putchar_sdma; + mpsc_getchar = mpsc_getchar_sdma; + mpsc_test_char = mpsc_test_char_sdma; +#endif + /* RX descriptors */ + rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * + sizeof (unsigned int)); + + /* align descriptors */ + rx_desc_base = (unsigned int *) + (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); + + rx_desc_index = 0; + + memset ((void *) rx_desc_base, 0, + (RX_DESC * 8) * sizeof (unsigned int)); + + for (i = 0; i < RX_DESC; i++) { + rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ + rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ + rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ + rx_desc_base[i * 8] = 0x00100000; + } + rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; + + FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); + GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), + (unsigned int) &rx_desc_base[0]); + + /* TX descriptors */ + tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * + sizeof (unsigned int)); + + /* align descriptors */ + tx_desc_base = (unsigned int *) + (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); + + tx_desc_index = -1; + + memset ((void *) tx_desc_base, 0, + (TX_DESC * 8) * sizeof (unsigned int)); + + for (i = 0; i < TX_DESC; i++) { + tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; + tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; + tx_desc_base[i * 8 + 3] = + (unsigned int) &tx_desc_base[i * 8 + 4]; + tx_desc_base[i * 8 + 2] = + (unsigned int) &tx_desc_base[(i + 1) * 8]; + tx_desc_base[i * 8 + 1] = + DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; + + /* set sbytecnt and shadow byte cnt to 1 */ + tx_desc_base[i * 8] = 0x00010001; + } + tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; + + FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); + + udelay (100); + + galsdma_enable_rx (); + + return; +} + +int galbrg_set_baudrate (int channel, int rate) +{ + DECLARE_GLOBAL_DATA_PTR; + int clock; + + galbrg_disable (channel); /*ok */ + +#ifdef ZUMA_NTL + /* from tclk */ + clock = (CFG_TCLK / (16 * rate)) - 1; +#else + clock = (CFG_TCLK / (16 * rate)) - 1; +#endif + + galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ + + galbrg_enable (channel); + + gd->baudrate = rate; + + return 0; +} + +/* ------------------------------------------------------------------ */ + +/* Below are all the private functions that no one else needs */ + +static int galbrg_set_CDV (int channel, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp &= 0xFFFF0000; + temp |= (value & 0x0000FFFF); + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} + +static int galbrg_enable (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp |= 0x00010000; + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} + +static int galbrg_disable (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp &= 0xFFFEFFFF; + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} + +static int galbrg_set_clksrc (int channel, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ + temp |= (value << 18); + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + return 0; +} + +static int galbrg_set_CUV (int channel, int value) +{ + /* set CountUpValue */ + GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); + + return 0; +} + +#if 0 +static int galbrg_reset (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp |= 0x20000; + GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} +#endif + +static int galsdma_set_RFT (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000001; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_SFM (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000002; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_rxle (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000040; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_txle (int channel) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp |= 0x00000080; + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_RC (int channel, unsigned int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp &= ~0x0000003c; + temp |= (value << 2); + GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), + temp); + + return 0; +} + +static int galsdma_set_burstsize (int channel, unsigned int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); + temp &= 0xFFFFCFFF; + switch (value) { + case 8: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x3 << 12))); + break; + + case 4: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x2 << 12))); + break; + + case 2: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x1 << 12))); + break; + + case 1: + GT_REG_WRITE (GALSDMA_0_CONF_REG + + (channel * GALSDMA_REG_DIFF), + (temp | (0x0 << 12))); + break; + + default: + return -1; + break; + } + + return 0; +} + +static int galmpsc_connect (int channel, int connect) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); + + if ((channel == 0) && connect) + temp &= ~0x00000007; + else if ((channel == 1) && connect) + temp &= ~(0x00000007 << 6); + else if ((channel == 0) && !connect) + temp |= 0x00000007; + else + temp |= (0x00000007 << 6); + + /* Just in case... */ + temp &= 0x3fffffff; + + GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); + + return 0; +} + +static int galmpsc_route_rx_clock (int channel, int brg) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_RxC_ROUTE); + + if (channel == 0) { + temp &= ~0x0000000F; + temp |= brg; + } else { + temp &= ~0x00000F00; + temp |= (brg << 8); + } + + GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); + + return 0; +} + +static int galmpsc_route_tx_clock (int channel, int brg) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_TxC_ROUTE); + + if (channel == 0) { + temp &= ~0x0000000F; + temp |= brg; + } else { + temp &= ~0x00000F00; + temp |= (brg << 8); + } + + GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); + + return 0; +} + +static int galmpsc_write_config_regs (int mpsc, int mode) +{ + if (mode == GALMPSC_UART) { + /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ + GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), + 0x000004c4); + + /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ + GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), + 0x024003f8); + /* 22 2222 1111 */ + /* 54 3210 9876 */ + /* 0000 0010 0000 0000 */ + /* 1 */ + /* 098 7654 3210 */ + /* 0000 0011 1111 1000 */ + } else + return -1; + + return 0; +} + +static int galmpsc_config_channel_regs (int mpsc) +{ + GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); + GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); + GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); + + galmpsc_set_brkcnt (mpsc, 0x3); + galmpsc_set_tcschar (mpsc, 0xab); + + return 0; +} + +static int galmpsc_set_brkcnt (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); + temp &= 0x0000FFFF; + temp |= (value << 16); + GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_tcschar (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); + temp &= 0xFFFF0000; + temp |= value; + GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_char_length (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); + temp &= 0xFFFFCFFF; + temp |= (value << 12); + GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_stop_bit_length (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); + temp &= 0xFFFFBFFF; + temp |= (value << 14); + GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_set_parity (int mpsc, int value) +{ + unsigned int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + if (value != -1) { + temp &= 0xFFF3FFF3; + temp |= ((value << 18) | (value << 2)); + temp |= ((value << 17) | (value << 1)); + } else { + temp &= 0xFFF1FFF1; + } + + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); + + return 0; +} + +static int galmpsc_enter_hunt (int mpsc) +{ + int temp; + + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + temp |= 0x80000000; + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); + + while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & + MPSC_ENTER_HUNT) { + udelay (1); + } + return 0; +} + + +static int galmpsc_shutdown (int mpsc) +{ + unsigned int temp; + + /* cause RX abort (clears RX) */ + temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); + temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; + temp &= ~MPSC_ENTER_HUNT; + GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); + + GT_REG_WRITE (GALSDMA_0_COM_REG, 0); + GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); + + /* shut down the MPSC */ + GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); + GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); + GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); + + udelay (100); + + /* shut down the sdma engines. */ + /* reset config to default */ + GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); + + udelay (100); + + /* clear the SDMA current and first TX and RX pointers */ + GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); + GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); + GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); + + udelay (100); + + return 0; +} + +static void galsdma_enable_rx (void) +{ + int temp; + + /* Enable RX processing */ + temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); + temp |= RX_ENABLE; + GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); + + galmpsc_enter_hunt (CHANNEL); +} + +static int galmpsc_set_snoop (int mpsc, int value) +{ + int reg = + mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : + MPSC_0_ADDRESS_CONTROL_LOW; + int temp = GTREGREAD (reg); + + if (value) + temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); + else + temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); + GT_REG_WRITE (reg, temp); + return 0; +} + +/******************************************************************************* +* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map. +* +* DESCRIPTION: +* the MV64360 SDMA has its own address decoding map that is de-coupled +* from the CPU interface address decoding windows. The SDMA channels +* share four address windows. Each region can be individually configured +* by this function by associating it to a target interface and setting +* base and size values. +* +* NOTE!!! +* The size must be in 64Kbyte granularity. +* The base address must be aligned to the size. +* The size must be a series of 1s followed by a series of zeros +* +* OUTPUT: +* None. +* +* RETURN: +* True for success, false otherwise. +* +*******************************************************************************/ + +static int galsdma_set_mem_space (unsigned int memSpace, + unsigned int memSpaceTarget, + unsigned int memSpaceAttr, + unsigned int baseAddress, unsigned int size) +{ + unsigned int temp; + + if (size == 0) { + GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, + 1 << memSpace); + return true; + } + + /* The base address must be aligned to the size. */ + if (baseAddress % size != 0) { + return false; + } + if (size < 0x10000) { + return false; + } + + /* Align size and base to 64K */ + baseAddress &= 0xffff0000; + size &= 0xffff0000; + temp = size >> 16; + + /* Checking that the size is a sequence of '1' followed by a + sequence of '0' starting from LSB to MSB. */ + while ((temp > 0) && (temp & 0x1)) { + temp = temp >> 1; + } + + if (temp != 0) { + GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8, + (baseAddress | memSpaceTarget | memSpaceAttr)); + GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8), + (size - 1) & 0xffff0000); + GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, + 1 << memSpace); + } else { + /* An invalid size was specified */ + return false; + } + return true; +} diff --git a/board/esd/cpci750/mpsc.h b/board/esd/cpci750/mpsc.h new file mode 100644 index 0000000..a03d1cc --- /dev/null +++ b/board/esd/cpci750/mpsc.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2001 + * John Clemens , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * changes for Marvell DB64360 eval board 2003 by Ingo Assmus + * + ************************************************************************/ + + +/* + * mpsc.h - header file for MPSC in uart mode (console driver) + */ + +#ifndef __MPSC_H__ +#define __MPSC_H__ + +/* include actual Galileo defines */ +#include "../../Marvell/include/mv_gen_reg.h" + +/* driver related defines */ + +int mpsc_init(int baud); +void mpsc_sdma_init(void); +void mpsc_init2(void); +int galbrg_set_baudrate(int channel, int rate); + +int mpsc_putchar_early(char ch); +char mpsc_getchar_debug(void); +int mpsc_test_char_debug(void); + +int mpsc_test_char_sdma(void); + +extern int (*mpsc_putchar)(char ch); +extern char (*mpsc_getchar)(void); +extern int (*mpsc_test_char)(void); + +#define CHANNEL CONFIG_MPSC_PORT + +#define TX_DESC 5 +#define RX_DESC 20 + +#define DESC_FIRST 0x00010000 +#define DESC_LAST 0x00020000 +#define DESC_OWNER_BIT 0x80000000 + +#define TX_DEMAND 0x00800000 +#define TX_STOP 0x00010000 +#define RX_ENABLE 0x00000080 + +#define SDMA_RX_ABORT (1 << 15) +#define SDMA_TX_ABORT (1 << 31) +#define MPSC_TX_ABORT (1 << 7) +#define MPSC_RX_ABORT (1 << 23) +#define MPSC_ENTER_HUNT (1 << 31) + +/* MPSC defines */ + +#define GALMPSC_CONNECT 0x1 +#define GALMPSC_DISCONNECT 0x0 + +#define GALMPSC_UART 0x1 + +#define GALMPSC_STOP_BITS_1 0x0 +#define GALMPSC_STOP_BITS_2 0x1 +#define GALMPSC_CHAR_LENGTH_8 0x3 +#define GALMPSC_CHAR_LENGTH_7 0x2 + +#define GALMPSC_PARITY_ODD 0x0 +#define GALMPSC_PARITY_EVEN 0x2 +#define GALMPSC_PARITY_MARK 0x3 +#define GALMPSC_PARITY_SPACE 0x1 +#define GALMPSC_PARITY_NONE -1 + +#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ +#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ +#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ +#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ +#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ +#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ +#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ + +#define GALMPSC_REG_GAP 0x1000 + +#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ +#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ +#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ +#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ +#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ +#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ +#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ +#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ +#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ +#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ +#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ +#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ + +#define GALSDMA_COMMAND_FIRST (1 << 16) +#define GALSDMA_COMMAND_LAST (1 << 17) +#define GALSDMA_COMMAND_ENABLEINT (1 << 23) +#define GALSDMA_COMMAND_AUTO (1 << 30) +#define GALSDMA_COMMAND_OWNER (1 << 31) + +#define GALSDMA_RX 0 +#define GALSDMA_TX 1 + +/* CHANNEL2 should be CHANNEL1, according to documentation, + * but to work with the current GTREGS file... + */ +#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ +#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ +#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ +#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ +#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ +#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ +#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ +#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ +#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ +#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ +#define GALSDMA_REG_DIFF 0x2000 + +/* WRONG in gt64260R.h */ +#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ +#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ +#define GALMPSC_0_INT_CAUSE 0xb804 +#define GALMPSC_0_INT_MASK 0xb884 + +#define GALSDMA_MODE_UART 0 +#define GALSDMA_MODE_BISYNC 1 +#define GALSDMA_MODE_HDLC 2 +#define GALSDMA_MODE_TRANSPARENT 3 + +#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ +#define GALBRG_REG_GAP 0x0008 +#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ + +#endif /* __MPSC_H__ */ diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c new file mode 100644 index 0000000..be176dc --- /dev/null +++ b/board/esd/cpci750/mv_eth.c @@ -0,0 +1,3184 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mv_eth.c - header file for the polled mode GT ethernet driver + */ +#include +#include +#include + +#include "mv_eth.h" + +/* enable Debug outputs */ + +#undef DEBUG_MV_ETH + +#ifdef DEBUG_MV_ETH +#define DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +#undef MV64360_CHECKSUM_OFFLOAD +/************************************************************************* +************************************************************************** +************************************************************************** +* The first part is the high level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ + +/* Definition for configuring driver */ +/* #define UPDATE_STATS_BY_SOFTWARE */ +#undef MV64360_RX_QUEUE_FILL_ON_TASK + + +/* Constants */ +#define MAGIC_ETH_RUNNING 8031971 +#define MV64360_INTERNAL_SRAM_SIZE _256K +#define EXTRA_BYTES 32 +#define WRAP ETH_HLEN + 2 + 4 + 16 +#define BUFFER_MTU dev->mtu + WRAP +#define INT_CAUSE_UNMASK_ALL 0x0007ffff +#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff +#ifdef MV64360_RX_FILL_ON_TASK +#define INT_CAUSE_MASK_ALL 0x00000000 +#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL +#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT +#endif + +/* Read/Write to/from MV64360 internal registers */ +#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) +#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) +#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) +#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) + +/* Static function declarations */ +static int mv64360_eth_real_open (struct eth_device *eth); +static int mv64360_eth_real_stop (struct eth_device *eth); +static struct net_device_stats *mv64360_eth_get_stats (struct eth_device + *dev); +static void eth_port_init_mac_tables (ETH_PORT eth_port_num); +static void mv64360_eth_update_stat (struct eth_device *dev); +bool db64360_eth_start (struct eth_device *eth); +unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, + unsigned int mib_offset); +int mv64360_eth_receive (struct eth_device *dev); + +int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); + +#ifndef UPDATE_STATS_BY_SOFTWARE +static void mv64360_eth_print_stat (struct eth_device *dev); +#endif +/* Processes a received packet */ +extern void NetReceive (volatile uchar *, int); + +extern unsigned int INTERNAL_REG_BASE_ADDR; + +/************************************************* + *Helper functions - used inside the driver only * + *************************************************/ +#ifdef DEBUG_MV_ETH +void print_globals (struct eth_device *dev) +{ + printf ("Ethernet PRINT_Globals-Debug function\n"); + printf ("Base Address for ETH_PORT_INFO: %08x\n", + (unsigned int) dev->priv); + printf ("Base Address for mv64360_eth_priv: %08x\n", + (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> + port_private)); + + printf ("GT Internal Base Address: %08x\n", + INTERNAL_REG_BASE_ADDR); + printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); + printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); + printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", + (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> + p_rx_buffer_base[0], + (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); + printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", + (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> + p_tx_buffer_base[0], + (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); +} +#endif + +#define my_cpu_to_le32(x) my_le32_to_cpu((x)) + +unsigned long my_le32_to_cpu (unsigned long x) +{ + return (((x & 0x000000ffU) << 24) | + ((x & 0x0000ff00U) << 8) | + ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); +} + + +/********************************************************************** + * mv64360_eth_print_phy_status + * + * Prints gigabit ethenret phy status + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + **********************************************************************/ + +static void mv64360_eth_print_phy_status (struct eth_device *dev) +{ + struct mv64360_eth_priv *port_private; + unsigned int port_num; + ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; + unsigned int port_status, phy_reg_data; + + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Check Link status on phy */ + eth_port_read_smi_reg (port_num, 1, &phy_reg_data); + if (!(phy_reg_data & 0x20)) { + printf ("Ethernet port changed link status to DOWN\n"); + } else { + port_status = + MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); + printf ("Ethernet status port %d: Link up", port_num); + printf (", %s", + (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); + if (port_status & BIT4) + printf (", Speed 1 Gbps"); + else + printf (", %s", + (port_status & BIT5) ? "Speed 100 Mbps" : + "Speed 10 Mbps"); + printf ("\n"); + } +} + +/********************************************************************** + * u-boot entry functions for mv64360_eth + * + **********************************************************************/ +int db64360_eth_probe (struct eth_device *dev) +{ + return ((int) db64360_eth_start (dev)); +} + +int db64360_eth_poll (struct eth_device *dev) +{ + return mv64360_eth_receive (dev); +} + +int db64360_eth_transmit (struct eth_device *dev, volatile void *packet, + int length) +{ + mv64360_eth_xmit (dev, packet, length); + return 0; +} + +void db64360_eth_disable (struct eth_device *dev) +{ + mv64360_eth_stop (dev); +} + + +void mv6436x_eth_initialize (bd_t * bis) +{ + struct eth_device *dev; + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + int devnum, x, temp; + char *s, *e, buf[64]; + + for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { + dev = calloc (sizeof (*dev), 1); + if (!dev) { + printf ("%s: mv_enet%d allocation failure, %s\n", + __FUNCTION__, devnum, "eth_device structure"); + return; + } + + /* must be less than NAMESIZE (16) */ + sprintf (dev->name, "mv_enet%d", devnum); + +#ifdef DEBUG + printf ("Initializing %s\n", dev->name); +#endif + + /* Extract the MAC address from the environment */ + switch (devnum) { + case 0: + s = "ethaddr"; + break; + + case 1: + s = "eth1addr"; + break; + + case 2: + s = "eth2addr"; + break; + + default: /* this should never happen */ + printf ("%s: Invalid device number %d\n", + __FUNCTION__, devnum); + return; + } + + temp = getenv_r (s, buf, sizeof (buf)); + s = (temp > 0) ? buf : NULL; + +#ifdef DEBUG + printf ("Setting MAC %d to %s\n", devnum, s); +#endif + for (x = 0; x < 6; ++x) { + dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + /* ronen - set the MAC addr in the HW */ + eth_port_uc_addr_set (devnum, dev->enetaddr, 0); + + dev->init = (void *) db64360_eth_probe; + dev->halt = (void *) ethernet_phy_reset; + dev->send = (void *) db64360_eth_transmit; + dev->recv = (void *) db64360_eth_poll; + + ethernet_private = + calloc (sizeof (*ethernet_private), 1); + dev->priv = (void *) ethernet_private; + if (!ethernet_private) { + printf ("%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, + "Private Device Structure"); + free (dev); + return; + } + /* start with an zeroed ETH_PORT_INFO */ + memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); + memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); + + /* set pointer to memory for stats data structure etc... */ + port_private = + calloc (sizeof (*ethernet_private), 1); + ethernet_private->port_private = (void *)port_private; + if (!port_private) { + printf ("%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, + "Port Private Device Structure"); + + free (ethernet_private); + free (dev); + return; + } + + port_private->stats = + calloc (sizeof (struct net_device_stats), 1); + if (!port_private->stats) { + printf ("%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, + "Net stat Structure"); + + free (port_private); + free (ethernet_private); + free (dev); + return; + } + memset (ethernet_private->port_private, 0, + sizeof (struct mv64360_eth_priv)); + switch (devnum) { + case 0: + ethernet_private->port_num = ETH_0; + break; + case 1: + ethernet_private->port_num = ETH_1; + break; + case 2: + ethernet_private->port_num = ETH_2; + break; + default: + printf ("Invalid device number %d\n", devnum); + break; + }; + + port_private->port_num = devnum; + /* + * Read MIB counter on the GT in order to reset them, + * then zero all the stats fields in memory + */ + mv64360_eth_update_stat (dev); + memset (port_private->stats, 0, + sizeof (struct net_device_stats)); + /* Extract the MAC address from the environment */ + switch (devnum) { + case 0: + s = "ethaddr"; + break; + + case 1: + s = "eth1addr"; + break; + + case 2: + s = "eth2addr"; + break; + + default: /* this should never happen */ + printf ("%s: Invalid device number %d\n", + __FUNCTION__, devnum); + return; + } + + temp = getenv_r (s, buf, sizeof (buf)); + s = (temp > 0) ? buf : NULL; + +#ifdef DEBUG + printf ("Setting MAC %d to %s\n", devnum, s); +#endif + for (x = 0; x < 6; ++x) { + dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + DP (printf ("Allocating descriptor and buffer rings\n")); + + ethernet_private->p_rx_desc_area_base[0] = + (ETH_RX_DESC *) memalign (16, + RX_DESC_ALIGNED_SIZE * + MV64360_RX_QUEUE_SIZE + 1); + ethernet_private->p_tx_desc_area_base[0] = + (ETH_TX_DESC *) memalign (16, + TX_DESC_ALIGNED_SIZE * + MV64360_TX_QUEUE_SIZE + 1); + + ethernet_private->p_rx_buffer_base[0] = + (char *) memalign (16, + MV64360_RX_QUEUE_SIZE * + MV64360_TX_BUFFER_SIZE + 1); + ethernet_private->p_tx_buffer_base[0] = + (char *) memalign (16, + MV64360_RX_QUEUE_SIZE * + MV64360_TX_BUFFER_SIZE + 1); + +#ifdef DEBUG_MV_ETH + /* DEBUG OUTPUT prints adresses of globals */ + print_globals (dev); +#endif + eth_register (dev); + + } + DP (printf ("%s: exit\n", __FUNCTION__)); + +} + +/********************************************************************** + * mv64360_eth_open + * + * This function is called when openning the network device. The function + * should initialize all the hardware, initialize cyclic Rx/Tx + * descriptors chain and buffers and allocate an IRQ to the network + * device. + * + * Input : a pointer to the network device structure + * / / ronen - changed the output to match net/eth.c needs + * Output : nonzero of success , zero if fails. + * under construction + **********************************************************************/ + +int mv64360_eth_open (struct eth_device *dev) +{ + return (mv64360_eth_real_open (dev)); +} + +/* Helper function for mv64360_eth_open */ +static int mv64360_eth_real_open (struct eth_device *dev) +{ + + unsigned int queue; + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + u32 port_status, phy_reg_data; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + /* ronen - when we update the MAC env params we only update dev->enetaddr + see ./net/eth.c eth_set_enetaddr() */ + memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); + + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Stop RX Queues */ + MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), + 0x0000ff00); + + /* Clear the ethernet port interrupts */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); + MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); + + /* Unmask RX buffer and TX end interrupt */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), + INT_CAUSE_UNMASK_ALL); + + /* Unmask phy and link status changes interrupts */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), + INT_CAUSE_UNMASK_ALL_EXT); + + /* Set phy address of the port */ + ethernet_private->port_phy_addr = 0x8 + port_num; + + /* Activate the DMA channels etc */ + eth_port_init (ethernet_private); + + + /* "Allocate" setup TX rings */ + + for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { + unsigned int size; + + port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; + size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ + ethernet_private->tx_desc_area_size[queue] = size; + + /* first clear desc area completely */ + memset ((void *) ethernet_private->p_tx_desc_area_base[queue], + 0, ethernet_private->tx_desc_area_size[queue]); + + /* initialize tx desc ring with low level driver */ + if (ether_init_tx_desc_ring + (ethernet_private, ETH_Q0, + port_private->tx_ring_size[queue], + MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , + (unsigned int) ethernet_private-> + p_tx_desc_area_base[queue], + (unsigned int) ethernet_private-> + p_tx_buffer_base[queue]) == false) + printf ("### Error initializing TX Ring\n"); + } + + /* "Allocate" setup RX rings */ + for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { + unsigned int size; + + /* Meantime RX Ring are fixed - but must be configurable by user */ + port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; + size = (port_private->rx_ring_size[queue] * + RX_DESC_ALIGNED_SIZE); + ethernet_private->rx_desc_area_size[queue] = size; + + /* first clear desc area completely */ + memset ((void *) ethernet_private->p_rx_desc_area_base[queue], + 0, ethernet_private->rx_desc_area_size[queue]); + if ((ether_init_rx_desc_ring + (ethernet_private, ETH_Q0, + port_private->rx_ring_size[queue], + MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , + (unsigned int) ethernet_private-> + p_rx_desc_area_base[queue], + (unsigned int) ethernet_private-> + p_rx_buffer_base[queue])) == false) + printf ("### Error initializing RX Ring\n"); + } + + eth_port_start (ethernet_private); + + /* Set maximum receive buffer to 9700 bytes */ + MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), + (0x5 << 17) | + (MV_REG_READ + (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) + & 0xfff1ffff)); + + /* + * Set ethernet MTU for leaky bucket mechanism to 0 - this will + * disable the leaky bucket mechanism . + */ + + MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); + port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); + + /* Check Link status on phy */ + eth_port_read_smi_reg (port_num, 1, &phy_reg_data); + if (!(phy_reg_data & 0x20)) { + /* Reset PHY */ + if ((ethernet_phy_reset (port_num)) != true) { + printf ("$$ Warnning: No link on port %d \n", + port_num); + return 0; + } else { + eth_port_read_smi_reg (port_num, 1, &phy_reg_data); + if (!(phy_reg_data & 0x20)) { + printf ("### Error: Phy is not active\n"); + return 0; + } + } + } else { + mv64360_eth_print_phy_status (dev); + } + port_private->eth_running = MAGIC_ETH_RUNNING; + return 1; +} + + +static int mv64360_eth_free_tx_rings (struct eth_device *dev) +{ + unsigned int queue; + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + volatile ETH_TX_DESC *p_tx_curr_desc; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Stop Tx Queues */ + MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), + 0x0000ff00); + + /* Free TX rings */ + DP (printf ("Clearing previously allocated TX queues... ")); + for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { + /* Free on TX rings */ + for (p_tx_curr_desc = + ethernet_private->p_tx_desc_area_base[queue]; + ((unsigned int) p_tx_curr_desc <= (unsigned int) + ethernet_private->p_tx_desc_area_base[queue] + + ethernet_private->tx_desc_area_size[queue]); + p_tx_curr_desc = + (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + + TX_DESC_ALIGNED_SIZE)) { + /* this is inside for loop */ + if (p_tx_curr_desc->return_info != 0) { + p_tx_curr_desc->return_info = 0; + DP (printf ("freed\n")); + } + } + DP (printf ("Done\n")); + } + return 0; +} + +static int mv64360_eth_free_rx_rings (struct eth_device *dev) +{ + unsigned int queue; + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + volatile ETH_RX_DESC *p_rx_curr_desc; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + + /* Stop RX Queues */ + MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), + 0x0000ff00); + + /* Free RX rings */ + DP (printf ("Clearing previously allocated RX queues... ")); + for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { + /* Free preallocated skb's on RX rings */ + for (p_rx_curr_desc = + ethernet_private->p_rx_desc_area_base[queue]; + (((unsigned int) p_rx_curr_desc < + ((unsigned int) ethernet_private-> + p_rx_desc_area_base[queue] + + ethernet_private->rx_desc_area_size[queue]))); + p_rx_curr_desc = + (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + + RX_DESC_ALIGNED_SIZE)) { + if (p_rx_curr_desc->return_info != 0) { + p_rx_curr_desc->return_info = 0; + DP (printf ("freed\n")); + } + } + DP (printf ("Done\n")); + } + return 0; +} + +/********************************************************************** + * mv64360_eth_stop + * + * This function is used when closing the network device. + * It updates the hardware, + * release all memory that holds buffers and descriptors and release the IRQ. + * Input : a pointer to the device structure + * Output : zero if success , nonzero if fails + *********************************************************************/ + +int mv64360_eth_stop (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + /* Disable all gigE address decoder */ + MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); + DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); + mv64360_eth_real_stop (dev); + + return 0; +}; + +/* Helper function for mv64360_eth_stop */ + +static int mv64360_eth_real_stop (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + + mv64360_eth_free_tx_rings (dev); + mv64360_eth_free_rx_rings (dev); + + eth_port_reset (ethernet_private->port_num); + /* Disable ethernet port interrupts */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); + MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); + /* Mask RX buffer and TX end interrupt */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); + /* Mask phy and link status changes interrupts */ + MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); + MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, + BIT0 << port_num); + /* Print Network statistics */ +#ifndef UPDATE_STATS_BY_SOFTWARE + /* + * Print statistics (only if ethernet is running), + * then zero all the stats fields in memory + */ + if (port_private->eth_running == MAGIC_ETH_RUNNING) { + port_private->eth_running = 0; + mv64360_eth_print_stat (dev); + } + memset (port_private->stats, 0, sizeof (struct net_device_stats)); +#endif + DP (printf ("\nEthernet stopped ... \n")); + return 0; +} + + +/********************************************************************** + * mv64360_eth_start_xmit + * + * This function is queues a packet in the Tx descriptor for + * required port. + * + * Input : skb - a pointer to socket buffer + * dev - a pointer to the required port + * + * Output : zero upon success + **********************************************************************/ + +int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, + int dataSize) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + PKT_INFO pkt_info; + ETH_FUNC_RET_STATUS status; + struct net_device_stats *stats; + ETH_FUNC_RET_STATUS release_result; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + stats = port_private->stats; + + /* Update packet info data structure */ + pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ + pkt_info.byte_cnt = dataSize; + pkt_info.buf_ptr = (unsigned int) dataPtr; + + status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); + if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { + printf ("Error on transmitting packet .."); + if (status == ETH_QUEUE_FULL) + printf ("ETH Queue is full. \n"); + if (status == ETH_QUEUE_LAST_RESOURCE) + printf ("ETH Queue: using last available resource. \n"); + goto error; + } + + /* Update statistics and start of transmittion time */ + stats->tx_bytes += dataSize; + stats->tx_packets++; + + /* Check if packet(s) is(are) transmitted correctly (release everything) */ + do { + release_result = + eth_tx_return_desc (ethernet_private, ETH_Q0, + &pkt_info); + switch (release_result) { + case ETH_OK: + DP (printf ("descriptor released\n")); + if (pkt_info.cmd_sts & BIT0) { + printf ("Error in TX\n"); + stats->tx_errors++; + + } + break; + case ETH_RETRY: + DP (printf ("transmission still in process\n")); + break; + + case ETH_ERROR: + printf ("routine can not access Tx desc ring\n"); + break; + + case ETH_END_OF_JOB: + DP (printf ("the routine has nothing to release\n")); + break; + default: /* should not happen */ + break; + } + } while (release_result == ETH_OK); + + + return 0; /* success */ + error: + return 1; /* Failed - higher layers will free the skb */ +} + +/********************************************************************** + * mv64360_eth_receive + * + * This function is forward packets that are received from the port's + * queues toward kernel core or FastRoute them to another interface. + * + * Input : dev - a pointer to the required interface + * max - maximum number to receive (0 means unlimted) + * + * Output : number of served packets + **********************************************************************/ + +int mv64360_eth_receive (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + PKT_INFO pkt_info; + struct net_device_stats *stats; + + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + stats = port_private->stats; + + while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == + ETH_OK)) { + +#ifdef DEBUG_MV_ETH + if (pkt_info.byte_cnt != 0) { + printf ("%s: Received %d byte Packet @ 0x%x\n", + __FUNCTION__, pkt_info.byte_cnt, + pkt_info.buf_ptr); + } +#endif + /* Update statistics. Note byte count includes 4 byte CRC count */ + stats->rx_packets++; + stats->rx_bytes += pkt_info.byte_cnt; + + /* + * In case received a packet without first / last bits on OR the error + * summary bit is on, the packets needs to be dropeed. + */ + if (((pkt_info. + cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != + (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) + || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { + stats->rx_dropped++; + + printf ("Received packet spread on multiple descriptors\n"); + + /* Is this caused by an error ? */ + if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { + stats->rx_errors++; + } + + /* free these descriptors again without forwarding them to the higher layers */ + pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ + pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ + + if (eth_rx_return_buff + (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { + printf ("Error while returning the RX Desc to Ring\n"); + } else { + DP (printf ("RX Desc returned to Ring\n")); + } + /* /free these descriptors again */ + } else { + +/* !!! call higher layer processing */ +#ifdef DEBUG_MV_ETH + printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); +#endif + /* let the upper layer handle the packet */ + NetReceive ((uchar *) pkt_info.buf_ptr, + (int) pkt_info.byte_cnt); + +/* **************************************************************** */ +/* free descriptor */ + pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ + pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ + DP (printf + ("RX: pkt_info.buf_ptr = %x\n", + pkt_info.buf_ptr)); + if (eth_rx_return_buff + (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { + printf ("Error while returning the RX Desc to Ring\n"); + } else { + DP (printf ("RX Desc returned to Ring\n")); + } + +/* **************************************************************** */ + + } + } + mv64360_eth_get_stats (dev); /* update statistics */ + return 1; +} + +/********************************************************************** + * mv64360_eth_get_stats + * + * Returns a pointer to the interface statistics. + * + * Input : dev - a pointer to the required interface + * + * Output : a pointer to the interface's statistics + **********************************************************************/ + +static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + + mv64360_eth_update_stat (dev); + + return port_private->stats; +} + + +/********************************************************************** + * mv64360_eth_update_stat + * + * Update the statistics structure in the private data structure + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + **********************************************************************/ + +static void mv64360_eth_update_stat (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + struct net_device_stats *stats; + unsigned int port_num; + volatile unsigned int dummy; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + stats = port_private->stats; + + /* These are false updates */ + stats->rx_packets += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_FRAMES_RECEIVED); + stats->tx_packets += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_FRAMES_SENT); + stats->rx_bytes += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); + /* + * Ideally this should be as follows - + * + * stats->rx_bytes += stats->rx_bytes + + * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , + * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); + * + * But the unsigned long in PowerPC and MIPS are 32bit. So the next read + * is just a dummy read for proper work of the GigE port + */ + dummy = eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); + stats->tx_bytes += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_SENT_LOW); + dummy = eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_GOOD_OCTETS_SENT_HIGH); + stats->rx_errors += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_MAC_RECEIVE_ERROR); + + /* Rx dropped is for received packet with CRC error */ + stats->rx_dropped += + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_BAD_CRC_EVENT); + stats->multicast += (unsigned long) + eth_read_mib_counter (ethernet_private->port_num, + ETH_MIB_MULTICAST_FRAMES_RECEIVED); + stats->collisions += + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_COLLISION) + + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_LATE_COLLISION); + /* detailed rx errors */ + stats->rx_length_errors += + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_UNDERSIZE_RECEIVED) + + + (unsigned long) eth_read_mib_counter (ethernet_private-> + port_num, + ETH_MIB_OVERSIZE_RECEIVED); + /* detailed tx errors */ +} + +#ifndef UPDATE_STATS_BY_SOFTWARE +/********************************************************************** + * mv64360_eth_print_stat + * + * Update the statistics structure in the private data structure + * + * Input : pointer to ethernet interface network device structure + * Output : N/A + **********************************************************************/ + +static void mv64360_eth_print_stat (struct eth_device *dev) +{ + ETH_PORT_INFO *ethernet_private; + struct mv64360_eth_priv *port_private; + struct net_device_stats *stats; + unsigned int port_num; + + ethernet_private = (ETH_PORT_INFO *) dev->priv; + port_private = + (struct mv64360_eth_priv *) ethernet_private->port_private; + port_num = port_private->port_num; + stats = port_private->stats; + + /* These are false updates */ + printf ("\n### Network statistics: ###\n"); + printf ("--------------------------\n"); + printf (" Packets received: %ld\n", stats->rx_packets); + printf (" Packets send: %ld\n", stats->tx_packets); + printf (" Received bytes: %ld\n", stats->rx_bytes); + printf (" Send bytes: %ld\n", stats->tx_bytes); + if (stats->rx_errors != 0) + printf (" Rx Errors: %ld\n", + stats->rx_errors); + if (stats->rx_dropped != 0) + printf (" Rx dropped (CRC Errors): %ld\n", + stats->rx_dropped); + if (stats->multicast != 0) + printf (" Rx mulicast frames: %ld\n", + stats->multicast); + if (stats->collisions != 0) + printf (" No. of collisions: %ld\n", + stats->collisions); + if (stats->rx_length_errors != 0) + printf (" Rx length errors: %ld\n", + stats->rx_length_errors); +} +#endif + +/************************************************************************** + *network_start - Network Kick Off Routine UBoot + *Inputs : + *Outputs : + **************************************************************************/ + +bool db64360_eth_start (struct eth_device *dev) +{ + return (mv64360_eth_open (dev)); /* calls real open */ +} + +/************************************************************************* +************************************************************************** +************************************************************************** +* The second part is the low level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ +/* + * based on Linux code + * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + */ + +/******************************************************************************** + * Marvell's Gigabit Ethernet controller low level driver + * + * DESCRIPTION: + * This file introduce low level API to Marvell's Gigabit Ethernet + * controller. This Gigabit Ethernet Controller driver API controls + * 1) Operations (i.e. port init, start, reset etc'). + * 2) Data flow (i.e. port send, receive etc'). + * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO + * struct. + * This struct includes user configuration information as well as + * driver internal data needed for its operations. + * + * Supported Features: + * - This low level driver is OS independent. Allocating memory for + * the descriptor rings and buffers are not within the scope of + * this driver. + * - The user is free from Rx/Tx queue managing. + * - This low level driver introduce functionality API that enable + * the to operate Marvell's Gigabit Ethernet Controller in a + * convenient way. + * - Simple Gigabit Ethernet port operation API. + * - Simple Gigabit Ethernet port data flow API. + * - Data flow and operation API support per queue functionality. + * - Support cached descriptors for better performance. + * - Enable access to all four DRAM banks and internal SRAM memory + * spaces. + * - PHY access and control API. + * - Port control register configuration API. + * - Full control over Unicast and Multicast MAC configurations. + * + * Operation flow: + * + * Initialization phase + * This phase complete the initialization of the ETH_PORT_INFO + * struct. + * User information regarding port configuration has to be set + * prior to calling the port initialization routine. For example, + * the user has to assign the port_phy_addr field which is board + * depended parameter. + * In this phase any port Tx/Rx activity is halted, MIB counters + * are cleared, PHY address is set according to user parameter and + * access to DRAM and internal SRAM memory spaces. + * + * Driver ring initialization + * Allocating memory for the descriptor rings and buffers is not + * within the scope of this driver. Thus, the user is required to + * allocate memory for the descriptors ring and buffers. Those + * memory parameters are used by the Rx and Tx ring initialization + * routines in order to curve the descriptor linked list in a form + * of a ring. + * Note: Pay special attention to alignment issues when using + * cached descriptors/buffers. In this phase the driver store + * information in the ETH_PORT_INFO struct regarding each queue + * ring. + * + * Driver start + * This phase prepares the Ethernet port for Rx and Tx activity. + * It uses the information stored in the ETH_PORT_INFO struct to + * initialize the various port registers. + * + * Data flow: + * All packet references to/from the driver are done using PKT_INFO + * struct. + * This struct is a unified struct used with Rx and Tx operations. + * This way the user is not required to be familiar with neither + * Tx nor Rx descriptors structures. + * The driver's descriptors rings are management by indexes. + * Those indexes controls the ring resources and used to indicate + * a SW resource error: + * 'current' + * This index points to the current available resource for use. For + * example in Rx process this index will point to the descriptor + * that will be passed to the user upon calling the receive routine. + * In Tx process, this index will point to the descriptor + * that will be assigned with the user packet info and transmitted. + * 'used' + * This index points to the descriptor that need to restore its + * resources. For example in Rx process, using the Rx buffer return + * API will attach the buffer returned in packet info to the + * descriptor pointed by 'used'. In Tx process, using the Tx + * descriptor return will merely return the user packet info with + * the command status of the transmitted buffer pointed by the + * 'used' index. Nevertheless, it is essential to use this routine + * to update the 'used' index. + * 'first' + * This index supports Tx Scatter-Gather. It points to the first + * descriptor of a packet assembled of multiple buffers. For example + * when in middle of Such packet we have a Tx resource error the + * 'curr' index get the value of 'first' to indicate that the ring + * returned to its state before trying to transmit this packet. + * + * Receive operation: + * The eth_port_receive API set the packet information struct, + * passed by the caller, with received information from the + * 'current' SDMA descriptor. + * It is the user responsibility to return this resource back + * to the Rx descriptor ring to enable the reuse of this source. + * Return Rx resource is done using the eth_rx_return_buff API. + * + * Transmit operation: + * The eth_port_send API supports Scatter-Gather which enables to + * send a packet spanned over multiple buffers. This means that + * for each packet info structure given by the user and put into + * the Tx descriptors ring, will be transmitted only if the 'LAST' + * bit will be set in the packet info command status field. This + * API also consider restriction regarding buffer alignments and + * sizes. + * The user must return a Tx resource after ensuring the buffer + * has been transmitted to enable the Tx ring indexes to update. + * + * BOARD LAYOUT + * This device is on-board. No jumper diagram is necessary. + * + * EXTERNAL INTERFACE + * + * Prior to calling the initialization routine eth_port_init() the user + * must set the following fields under ETH_PORT_INFO struct: + * port_num User Ethernet port number. + * port_phy_addr User PHY address of Ethernet port. + * port_mac_addr[6] User defined port MAC address. + * port_config User port configuration value. + * port_config_extend User port config extend value. + * port_sdma_config User port SDMA config value. + * port_serial_control User port serial control value. + * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. + * *port_private User scratch pad for user specific data structures. + * + * This driver introduce a set of default values: + * PORT_CONFIG_VALUE Default port configuration value + * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value + * PORT_SDMA_CONFIG_VALUE Default sdma control value + * PORT_SERIAL_CONTROL_VALUE Default port serial control value + * + * This driver data flow is done using the PKT_INFO struct which is + * a unified struct for Rx and Tx operations: + * byte_cnt Tx/Rx descriptor buffer byte count. + * l4i_chk CPU provided TCP Checksum. For Tx operation only. + * cmd_sts Tx/Rx descriptor command status. + * buf_ptr Tx/Rx descriptor buffer pointer. + * return_info Tx/Rx user resource return information. + * + * + * EXTERNAL SUPPORT REQUIREMENTS + * + * This driver requires the following external support: + * + * D_CACHE_FLUSH_LINE (address, address offset) + * + * This macro applies assembly code to flush and invalidate cache + * line. + * address - address base. + * address offset - address offset + * + * + * CPU_PIPE_FLUSH + * + * This macro applies assembly code to flush the CPU pipeline. + * + *******************************************************************************/ +/* includes */ + +/* defines */ +/* SDMA command macros */ +#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ + MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) + +#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ + MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ + (1 << (8 + tx_queue))) + +#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ +MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) + +#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ +MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) + +#define CURR_RFD_GET(p_curr_desc, queue) \ + ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) + +#define CURR_RFD_SET(p_curr_desc, queue) \ + (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) + +#define USED_RFD_GET(p_used_desc, queue) \ + ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) + +#define USED_RFD_SET(p_used_desc, queue)\ +(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) + + +#define CURR_TFD_GET(p_curr_desc, queue) \ + ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) + +#define CURR_TFD_SET(p_curr_desc, queue) \ + (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) + +#define USED_TFD_GET(p_used_desc, queue) \ + ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) + +#define USED_TFD_SET(p_used_desc, queue) \ + (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) + +#define FIRST_TFD_GET(p_first_desc, queue) \ + ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) + +#define FIRST_TFD_SET(p_first_desc, queue) \ + (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) + + +/* Macros that save access to desc in order to find next desc pointer */ +#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + +#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + +#define LINK_UP_TIMEOUT 100000 +#define PHY_BUSY_TIMEOUT 10000000 + +/* locals */ + +/* PHY routines */ +static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); +static int ethernet_phy_get (ETH_PORT eth_port_num); + +/* Ethernet Port routines */ +static void eth_set_access_control (ETH_PORT eth_port_num, + ETH_WIN_PARAM * param); +static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, + ETH_QUEUE queue, int option); +#if 0 /* FIXME */ +static bool eth_port_smc_addr (ETH_PORT eth_port_num, + unsigned char mc_byte, + ETH_QUEUE queue, int option); +static bool eth_port_omc_addr (ETH_PORT eth_port_num, + unsigned char crc8, + ETH_QUEUE queue, int option); +#endif + +static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, + int byte_count); + +void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); + + +typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; +u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) +{ + u32 result = 0; + u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); + + if (enable & (1 << bank)) + return 0; + if (bank == BANK0) + result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); + if (bank == BANK1) + result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); + if (bank == BANK2) + result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); + if (bank == BANK3) + result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); + result &= 0x0000ffff; + result = result << 16; + return result; +} + +u32 mv_get_dram_bank_size (MEMORY_BANK bank) +{ + u32 result = 0; + u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); + + if (enable & (1 << bank)) + return 0; + if (bank == BANK0) + result = MV_REG_READ (MV64360_CS_0_SIZE); + if (bank == BANK1) + result = MV_REG_READ (MV64360_CS_1_SIZE); + if (bank == BANK2) + result = MV_REG_READ (MV64360_CS_2_SIZE); + if (bank == BANK3) + result = MV_REG_READ (MV64360_CS_3_SIZE); + result += 1; + result &= 0x0000ffff; + result = result << 16; + return result; +} + +u32 mv_get_internal_sram_base (void) +{ + u32 result; + + result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); + result &= 0x0000ffff; + result = result << 16; + return result; +} + +/******************************************************************************* +* eth_port_init - Initialize the Ethernet port driver +* +* DESCRIPTION: +* This function prepares the ethernet port to start its activity: +* 1) Completes the ethernet port driver struct initialization toward port +* start routine. +* 2) Resets the device to a quiescent state in case of warm reboot. +* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. +* 4) Clean MAC tables. The reset status of those tables is unknown. +* 5) Set PHY address. +* Note: Call this routine prior to eth_port_start routine and after setting +* user values in the user fields of Ethernet port control struct (i.e. +* port_phy_addr). +* +* INPUT: +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* +* OUTPUT: +* See description. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) +{ + int queue; + ETH_WIN_PARAM win_param; + + p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; + p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; + p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; + p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; + + p_eth_port_ctrl->port_rx_queue_command = 0; + p_eth_port_ctrl->port_tx_queue_command = 0; + + /* Zero out SW structs */ + for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { + CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); + USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); + p_eth_port_ctrl->rx_resource_err[queue] = false; + } + + for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { + CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); + USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); + FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); + p_eth_port_ctrl->tx_resource_err[queue] = false; + } + + eth_port_reset (p_eth_port_ctrl->port_num); + + /* Set access parameters for DRAM bank 0 */ + win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); + win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for DRAM bank 1 */ + win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); + win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for DRAM bank 2 */ + win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); + win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for DRAM bank 3 */ + win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ + win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ + win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ +#ifndef CONFIG_NOT_COHERENT_CACHE + win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; +#endif + win_param.high_addr = 0; + /* Get bank base */ + win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); + win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ + if (win_param.size == 0) + win_param.enable = 0; + else + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + /* Set access parameters for Internal SRAM */ + win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ + win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ + win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; + win_param.high_addr = 0; + win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ + win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ + win_param.enable = 1; /* Enable the access */ + win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ + + /* Set the access control for address window (EPAPR) READ & WRITE */ + eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); + + eth_port_init_mac_tables (p_eth_port_ctrl->port_num); + + ethernet_phy_set (p_eth_port_ctrl->port_num, + p_eth_port_ctrl->port_phy_addr); + + return; + +} + +/******************************************************************************* +* eth_port_start - Start the Ethernet port activity. +* +* DESCRIPTION: +* This routine prepares the Ethernet port for Rx and Tx activity: +* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that +* has been initialized a descriptor's ring (using ether_init_tx_desc_ring +* for Tx and ether_init_rx_desc_ring for Rx) +* 2. Initialize and enable the Ethernet configuration port by writing to +* the port's configuration and command registers. +* 3. Initialize and enable the SDMA by writing to the SDMA's +* configuration and command registers. +* After completing these steps, the ethernet port SDMA can starts to +* perform Rx and Tx activities. +* +* Note: Each Rx and Tx queue descriptor's list must be initialized prior +* to calling this function (use ether_init_tx_desc_ring for Tx queues and +* ether_init_rx_desc_ring for Rx queues). +* +* INPUT: +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* +* OUTPUT: +* Ethernet port is ready to receive and transmit. +* +* RETURN: +* false if the port PHY is not up. +* true otherwise. +* +*******************************************************************************/ +static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) +{ + int queue; + volatile ETH_TX_DESC *p_tx_curr_desc; + volatile ETH_RX_DESC *p_rx_curr_desc; + unsigned int phy_reg_data; + ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; + + + /* Assignment of Tx CTRP of given queue */ + for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { + CURR_TFD_GET (p_tx_curr_desc, queue); + MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 + (eth_port_num) + + (4 * queue)), + ((unsigned int) p_tx_curr_desc)); + + } + + /* Assignment of Rx CRDP of given queue */ + for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { + CURR_RFD_GET (p_rx_curr_desc, queue); + MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 + (eth_port_num) + + (4 * queue)), + ((unsigned int) p_rx_curr_desc)); + + if (p_rx_curr_desc != NULL) + /* Add the assigned Ethernet address to the port's address table */ + eth_port_uc_addr_set (p_eth_port_ctrl->port_num, + p_eth_port_ctrl->port_mac_addr, + queue); + } + + /* Assign port configuration and command. */ + MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), + p_eth_port_ctrl->port_config); + + MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), + p_eth_port_ctrl->port_config_extend); + + MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), + p_eth_port_ctrl->port_serial_control); + + MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), + ETH_SERIAL_PORT_ENABLE); + + /* Assign port SDMA configuration */ + MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), + p_eth_port_ctrl->port_sdma_config); + + MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT + (eth_port_num), 0x3fffffff); + MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG + (eth_port_num), 0x03fffcff); + /* Turn off the port/queue bandwidth limitation */ + MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); + + /* Enable port Rx. */ + MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), + p_eth_port_ctrl->port_rx_queue_command); + + /* Check if link is up */ + eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); + + if (!(phy_reg_data & 0x20)) + return false; + + return true; +} + +/******************************************************************************* +* eth_port_uc_addr_set - This function Set the port Unicast address. +* +* DESCRIPTION: +* This function Set the port Ethernet MAC address. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* char * p_addr Address to be set +* ETH_QUEUE queue Rx queue number for this MAC address. +* +* OUTPUT: +* Set MAC address low and high registers. also calls eth_port_uc_addr() +* To set the unicast table with the proper information. +* +* RETURN: +* N/A. +* +*******************************************************************************/ +static void eth_port_uc_addr_set (ETH_PORT eth_port_num, + unsigned char *p_addr, ETH_QUEUE queue) +{ + unsigned int mac_h; + unsigned int mac_l; + + mac_l = (p_addr[4] << 8) | (p_addr[5]); + mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | + (p_addr[2] << 8) | (p_addr[3] << 0); + + MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); + MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); + + /* Accept frames of this address */ + eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); + + return; +} + +/******************************************************************************* +* eth_port_uc_addr - This function Set the port unicast address table +* +* DESCRIPTION: +* This function locates the proper entry in the Unicast table for the +* specified MAC nibble and sets its properties according to function +* parameters. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char uc_nibble Unicast MAC Address last nibble. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* This function add/removes MAC addresses from the port unicast address +* table. +* +* RETURN: +* true is output succeeded. +* false if option parameter is invalid. +* +*******************************************************************************/ +static bool eth_port_uc_addr (ETH_PORT eth_port_num, + unsigned char uc_nibble, + ETH_QUEUE queue, int option) +{ + unsigned int unicast_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the Unicast table entry */ + uc_nibble = (0xf & uc_nibble); + tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ + reg_offset = uc_nibble % 4; /* Entry offset within the above register */ + + switch (option) { + case REJECT_MAC_ADDR: + /* Clear accepts frame bit at specified unicast DA table entry */ + unicast_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset)); + + unicast_reg &= (0x0E << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset), unicast_reg); + break; + + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at unicast DA filter table entry */ + unicast_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset)); + + unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + + tbl_offset), unicast_reg); + + break; + + default: + return false; + } + return true; +} + +#if 0 /* FIXME */ +/******************************************************************************* +* eth_port_mc_addr - Multicast address settings. +* +* DESCRIPTION: +* This API controls the MV device MAC multicast support. +* The MV device supports multicast using two tables: +* 1) Special Multicast Table for MAC addresses of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* In this case, the function calls eth_port_smc_addr() routine to set the +* Special Multicast Table. +* 2) Other Multicast Table for multicast of another type. A CRC-8bit +* is used as an index to the Other Multicast Table entries in the +* DA-Filter table. +* In this case, the function calculates the CRC-8bit value and calls +* eth_port_omc_addr() routine to set the Other Multicast Table. +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char *p_addr Unicast MAC Address. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* true is output succeeded. +* false if add_address_table_entry( ) failed. +* +*******************************************************************************/ +static void eth_port_mc_addr (ETH_PORT eth_port_num, + unsigned char *p_addr, + ETH_QUEUE queue, int option) +{ + unsigned int mac_h; + unsigned int mac_l; + unsigned char crc_result = 0; + int mac_array[48]; + int crc[8]; + int i; + + + if ((p_addr[0] == 0x01) && + (p_addr[1] == 0x00) && + (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) + + eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); + else { + /* Calculate CRC-8 out of the given address */ + mac_h = (p_addr[0] << 8) | (p_addr[1]); + mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | + (p_addr[4] << 8) | (p_addr[5] << 0); + + for (i = 0; i < 32; i++) + mac_array[i] = (mac_l >> i) & 0x1; + for (i = 32; i < 48; i++) + mac_array[i] = (mac_h >> (i - 32)) & 0x1; + + + crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ + mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ + mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ + mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ + mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ + mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ + mac_array[6] ^ mac_array[0]; + + crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ + mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ + mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ + mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ + mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ + mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ + mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ + mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ + mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ + mac_array[0]; + + crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ + mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ + mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ + mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ + mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ + mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ + mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ + mac_array[2] ^ mac_array[1] ^ mac_array[0]; + + crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ + mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ + mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ + mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ + mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ + mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ + mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ + mac_array[2] ^ mac_array[1]; + + crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ + mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ + mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ + mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ + mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ + mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ + mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ + mac_array[2]; + + crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ + mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ + mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ + mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ + mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ + mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ + mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ + mac_array[3]; + + crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ + mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ + mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ + mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ + mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ + mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ + mac_array[6] ^ mac_array[5] ^ mac_array[4]; + + crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ + mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ + mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ + mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ + mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ + mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ + mac_array[6] ^ mac_array[5]; + + for (i = 0; i < 8; i++) + crc_result = crc_result | (crc[i] << i); + + eth_port_omc_addr (eth_port_num, crc_result, queue, option); + } + return; +} + +/******************************************************************************* +* eth_port_smc_addr - Special Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device special MAC multicast support. +* The Special Multicast Table for MAC addresses supports MAC of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* This function set the Special Multicast Table appropriate entry +* according to the argument given. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* true is output succeeded. +* false if option parameter is invalid. +* +*******************************************************************************/ +static bool eth_port_smc_addr (ETH_PORT eth_port_num, + unsigned char mc_byte, + ETH_QUEUE queue, int option) +{ + unsigned int smc_table_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the SMC table entry */ + tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ + reg_offset = mc_byte % 4; /* Entry offset within the above register */ + queue &= 0x7; + + switch (option) { + case REJECT_MAC_ADDR: + /* Clear accepts frame bit at specified Special DA table entry */ + smc_table_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + smc_table_reg &= (0x0E << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); + break; + + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at specified Special DA table entry */ + smc_table_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); + break; + + default: + return false; + } + return true; +} + +/******************************************************************************* +* eth_port_omc_addr - Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device Other MAC multicast support. +* The Other Multicast Table is used for multicast of another type. +* A CRC-8bit is used as an index to the Other Multicast Table entries +* in the DA-Filter table. +* The function gets the CRC-8bit value from the calling routine and +* set the Other Multicast Table appropriate entry according to the +* CRC-8 argument given. +* +* INPUT: +* ETH_PORT eth_port_num Port number. +* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* true is output succeeded. +* false if option parameter is invalid. +* +*******************************************************************************/ +static bool eth_port_omc_addr (ETH_PORT eth_port_num, + unsigned char crc8, + ETH_QUEUE queue, int option) +{ + unsigned int omc_table_reg; + unsigned int tbl_offset; + unsigned int reg_offset; + + /* Locate the OMC table entry */ + tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ + reg_offset = crc8 % 4; /* Entry offset within the above register */ + queue &= 0x7; + + switch (option) { + case REJECT_MAC_ADDR: + /* Clear accepts frame bit at specified Other DA table entry */ + omc_table_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + omc_table_reg &= (0x0E << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); + break; + + case ACCEPT_MAC_ADDR: + /* Set accepts frame bit at specified Other DA table entry */ + omc_table_reg = + MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); + omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); + + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); + break; + + default: + return false; + } + return true; +} +#endif + +/******************************************************************************* +* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables +* +* DESCRIPTION: +* Go through all the DA filter tables (Unicast, Special Multicast & Other +* Multicast) and set each entry to 0. +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* +* OUTPUT: +* Multicast and Unicast packets are rejected. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void eth_port_init_mac_tables (ETH_PORT eth_port_num) +{ + int table_index; + + /* Clear DA filter unicast table (Ex_dFUT) */ + for (table_index = 0; table_index <= 0xC; table_index += 4) + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE + (eth_port_num) + table_index), 0); + + for (table_index = 0; table_index <= 0xFC; table_index += 4) { + /* Clear DA filter special multicast table (Ex_dFSMT) */ + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); + /* Clear DA filter other multicast table (Ex_dFOMT) */ + MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); + } +} + +/******************************************************************************* +* eth_clear_mib_counters - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters of a specific ethernet port. +* A read from the MIB counter will reset the counter. +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* +* OUTPUT: +* After reading all MIB counters, the counters resets. +* +* RETURN: +* MIB counter value. +* +*******************************************************************************/ +static void eth_clear_mib_counters (ETH_PORT eth_port_num) +{ + int i; + unsigned int dummy; + + /* Perform dummy reads from MIB counters */ + for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; + i += 4) + dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE + (eth_port_num) + i)); + + return; +} + +/******************************************************************************* +* eth_read_mib_counter - Read a MIB counter +* +* DESCRIPTION: +* This function reads a MIB counter of a specific ethernet port. +* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the +* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH +* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and +* ETH_MIB_GOOD_OCTETS_SENT_HIGH +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). +* +* OUTPUT: +* After reading the MIB counter, the counter resets. +* +* RETURN: +* MIB counter value. +* +*******************************************************************************/ +unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, + unsigned int mib_offset) +{ + return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) + + mib_offset)); +} + +/******************************************************************************* +* ethernet_phy_set - Set the ethernet port PHY address. +* +* DESCRIPTION: +* This routine set the ethernet port PHY address according to given +* parameter. +* +* INPUT: +* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. +* +* OUTPUT: +* Set PHY Address Register with given PHY address parameter. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) +{ + unsigned int reg_data; + + reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); + + reg_data &= ~(0x1F << (5 * eth_port_num)); + reg_data |= (phy_addr << (5 * eth_port_num)); + + MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); + + return; +} + +/******************************************************************************* + * ethernet_phy_get - Get the ethernet port PHY address. + * + * DESCRIPTION: + * This routine returns the given ethernet port PHY address. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * None. + * + * RETURN: + * PHY address. + * + *******************************************************************************/ +static int ethernet_phy_get (ETH_PORT eth_port_num) +{ + unsigned int reg_data; + + reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); + + return ((reg_data >> (5 * eth_port_num)) & 0x1f); +} + +/******************************************************************************* + * ethernet_phy_reset - Reset Ethernet port PHY. + * + * DESCRIPTION: + * This routine utilize the SMI interface to reset the ethernet port PHY. + * The routine waits until the link is up again or link up is timeout. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * The ethernet port PHY renew its link. + * + * RETURN: + * None. + * +*******************************************************************************/ +static bool ethernet_phy_reset (ETH_PORT eth_port_num) +{ + unsigned int time_out = 50; + unsigned int phy_reg_data; + + /* Reset the PHY */ + eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); + phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ + eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); + + /* Poll on the PHY LINK */ + do { + eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); + + if (time_out-- == 0) + return false; + } + while (!(phy_reg_data & 0x20)); + + return true; +} + +/******************************************************************************* + * eth_port_reset - Reset Ethernet port + * + * DESCRIPTION: + * This routine resets the chip by aborting any SDMA engine activity and + * clearing the MIB counters. The Receiver and the Transmit unit are in + * idle state after this command is performed and the port is disabled. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * Channel activity is halted. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void eth_port_reset (ETH_PORT eth_port_num) +{ + unsigned int reg_data; + + /* Stop Tx port activity. Check port Tx activity. */ + reg_data = + MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG + (eth_port_num)); + + if (reg_data & 0xFF) { + /* Issue stop command for active channels only */ + MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG + (eth_port_num), (reg_data << 8)); + + /* Wait for all Tx activity to terminate. */ + do { + /* Check port cause register that all Tx queues are stopped */ + reg_data = + MV_REG_READ + (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG + (eth_port_num)); + } + while (reg_data & 0xFF); + } + + /* Stop Rx port activity. Check port Rx activity. */ + reg_data = + MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG + (eth_port_num)); + + if (reg_data & 0xFF) { + /* Issue stop command for active channels only */ + MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG + (eth_port_num), (reg_data << 8)); + + /* Wait for all Rx activity to terminate. */ + do { + /* Check port cause register that all Rx queues are stopped */ + reg_data = + MV_REG_READ + (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG + (eth_port_num)); + } + while (reg_data & 0xFF); + } + + + /* Clear all MIB counters */ + eth_clear_mib_counters (eth_port_num); + + /* Reset the Enable bit in the Configuration Register */ + reg_data = + MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG + (eth_port_num)); + reg_data &= ~ETH_SERIAL_PORT_ENABLE; + MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), + reg_data); + + return; +} + +#if 0 /* Not needed here */ +/******************************************************************************* + * ethernet_set_config_reg - Set specified bits in configuration register. + * + * DESCRIPTION: + * This function sets specified bits in the given ethernet + * configuration register. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int value 32 bit value. + * + * OUTPUT: + * The set bits in the value parameter are set in the configuration + * register. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void ethernet_set_config_reg (ETH_PORT eth_port_num, + unsigned int value) +{ + unsigned int eth_config_reg; + + eth_config_reg = + MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); + eth_config_reg |= value; + MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), + eth_config_reg); + + return; +} +#endif + +#if 0 /* FIXME */ +/******************************************************************************* + * ethernet_reset_config_reg - Reset specified bits in configuration register. + * + * DESCRIPTION: + * This function resets specified bits in the given Ethernet + * configuration register. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int value 32 bit value. + * + * OUTPUT: + * The set bits in the value parameter are reset in the configuration + * register. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void ethernet_reset_config_reg (ETH_PORT eth_port_num, + unsigned int value) +{ + unsigned int eth_config_reg; + + eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG + (eth_port_num)); + eth_config_reg &= ~value; + MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), + eth_config_reg); + + return; +} +#endif + +#if 0 /* Not needed here */ +/******************************************************************************* + * ethernet_get_config_reg - Get the port configuration register + * + * DESCRIPTION: + * This function returns the configuration register value of the given + * ethernet port. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * + * OUTPUT: + * None. + * + * RETURN: + * Port configuration register value. + * + *******************************************************************************/ +static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) +{ + unsigned int eth_config_reg; + + eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG + (eth_port_num)); + return eth_config_reg; +} + +#endif + +/******************************************************************************* + * eth_port_read_smi_reg - Read PHY registers + * + * DESCRIPTION: + * This routine utilize the SMI interface to interact with the PHY in + * order to perform PHY register read. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int phy_reg PHY register address offset. + * unsigned int *value Register value buffer. + * + * OUTPUT: + * Write the value of a specified PHY register into given buffer. + * + * RETURN: + * false if the PHY is busy or read data is not in valid state. + * true otherwise. + * + *******************************************************************************/ +static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, + unsigned int phy_reg, unsigned int *value) +{ + unsigned int reg_value; + unsigned int time_out = PHY_BUSY_TIMEOUT; + int phy_addr; + + phy_addr = ethernet_phy_get (eth_port_num); +/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ + + /* first check that it is not busy */ + do { + reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); + if (time_out-- == 0) { + return false; + } + } + while (reg_value & ETH_SMI_BUSY); + + /* not busy */ + + MV_REG_WRITE (MV64360_ETH_SMI_REG, + (phy_addr << 16) | (phy_reg << 21) | + ETH_SMI_OPCODE_READ); + + time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ + + do { + reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); + if (time_out-- == 0) { + return false; + } + } + while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ + + /* Wait for the data to update in the SMI register */ +#define PHY_UPDATE_TIMEOUT 10000 + for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); + + reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); + + *value = reg_value & 0xffff; + + return true; +} + +/******************************************************************************* + * eth_port_write_smi_reg - Write to PHY registers + * + * DESCRIPTION: + * This routine utilize the SMI interface to interact with the PHY in + * order to perform writes to PHY registers. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * unsigned int phy_reg PHY register address offset. + * unsigned int value Register value. + * + * OUTPUT: + * Write the given value to the specified PHY register. + * + * RETURN: + * false if the PHY is busy. + * true otherwise. + * + *******************************************************************************/ +static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, + unsigned int phy_reg, unsigned int value) +{ + unsigned int reg_value; + unsigned int time_out = PHY_BUSY_TIMEOUT; + int phy_addr; + + phy_addr = ethernet_phy_get (eth_port_num); + + /* first check that it is not busy */ + do { + reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); + if (time_out-- == 0) { + return false; + } + } + while (reg_value & ETH_SMI_BUSY); + + /* not busy */ + MV_REG_WRITE (MV64360_ETH_SMI_REG, + (phy_addr << 16) | (phy_reg << 21) | + ETH_SMI_OPCODE_WRITE | (value & 0xffff)); + return true; +} + +/******************************************************************************* + * eth_set_access_control - Config address decode parameters for Ethernet unit + * + * DESCRIPTION: + * This function configures the address decode parameters for the Gigabit + * Ethernet Controller according the given parameters struct. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. + * ETH_WIN_PARAM *param Address decode parameter struct. + * + * OUTPUT: + * An access window is opened using the given access parameters. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void eth_set_access_control (ETH_PORT eth_port_num, + ETH_WIN_PARAM * param) +{ + unsigned int access_prot_reg; + + /* Set access control register */ + access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG + (eth_port_num)); + access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ + access_prot_reg |= (param->access_ctrl << (param->win * 2)); + MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), + access_prot_reg); + + /* Set window Size reg (SR) */ + MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + + (ETH_SIZE_REG_GAP * param->win)), + (((param->size / 0x10000) - 1) << 16)); + + /* Set window Base address reg (BA) */ + MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), + (param->target | param->attributes | param->base_addr)); + /* High address remap reg (HARR) */ + if (param->win < 4) + MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + + (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), + param->high_addr); + + /* Base address enable reg (BARER) */ + if (param->enable == 1) + MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, + (1 << param->win)); + else + MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, + (1 << param->win)); +} + +/******************************************************************************* + * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. + * + * DESCRIPTION: + * This function prepares a Rx chained list of descriptors and packet + * buffers in a form of a ring. The routine must be called after port + * initialization routine and before port start routine. + * The Ethernet SDMA engine uses CPU bus addresses to access the various + * devices in the system (i.e. DRAM). This function uses the ethernet + * struct 'virtual to physical' routine (set by the user) to set the ring + * with physical addresses. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE rx_queue Number of Rx queue. + * int rx_desc_num Number of Rx descriptors + * int rx_buff_size Size of Rx buffer + * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. + * unsigned int rx_buff_base_addr Rx buffer memory area base addr. + * + * OUTPUT: + * The routine updates the Ethernet port control struct with information + * regarding the Rx descriptors and buffers. + * + * RETURN: + * false if the given descriptors memory area is not aligned according to + * Ethernet SDMA specifications. + * true otherwise. + * + *******************************************************************************/ +static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE rx_queue, + int rx_desc_num, + int rx_buff_size, + unsigned int rx_desc_base_addr, + unsigned int rx_buff_base_addr) +{ + ETH_RX_DESC *p_rx_desc; + ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ + unsigned int buffer_addr; + int ix; /* a counter */ + + + p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; + p_rx_prev_desc = p_rx_desc; + buffer_addr = rx_buff_base_addr; + + /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ + if (rx_buff_base_addr & 0xF) + return false; + + /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ + if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) + return false; + + /* Rx buffers must be 64-bit aligned. */ + if ((rx_buff_base_addr + rx_buff_size) & 0x7) + return false; + + /* initialize the Rx descriptors ring */ + for (ix = 0; ix < rx_desc_num; ix++) { + p_rx_desc->buf_size = rx_buff_size; + p_rx_desc->byte_cnt = 0x0000; + p_rx_desc->cmd_sts = + ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; + p_rx_desc->next_desc_ptr = + ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; + p_rx_desc->buf_ptr = buffer_addr; + p_rx_desc->return_info = 0x00000000; + D_CACHE_FLUSH_LINE (p_rx_desc, 0); + buffer_addr += rx_buff_size; + p_rx_prev_desc = p_rx_desc; + p_rx_desc = (ETH_RX_DESC *) + ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); + } + + /* Closing Rx descriptors ring */ + p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); + D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); + + /* Save Rx desc pointer to driver struct. */ + CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); + USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); + + p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = + (ETH_RX_DESC *) rx_desc_base_addr; + p_eth_port_ctrl->rx_desc_area_size[rx_queue] = + rx_desc_num * RX_DESC_ALIGNED_SIZE; + + p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); + + return true; +} + +/******************************************************************************* + * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. + * + * DESCRIPTION: + * This function prepares a Tx chained list of descriptors and packet + * buffers in a form of a ring. The routine must be called after port + * initialization routine and before port start routine. + * The Ethernet SDMA engine uses CPU bus addresses to access the various + * devices in the system (i.e. DRAM). This function uses the ethernet + * struct 'virtual to physical' routine (set by the user) to set the ring + * with physical addresses. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE tx_queue Number of Tx queue. + * int tx_desc_num Number of Tx descriptors + * int tx_buff_size Size of Tx buffer + * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. + * unsigned int tx_buff_base_addr Tx buffer memory area base addr. + * + * OUTPUT: + * The routine updates the Ethernet port control struct with information + * regarding the Tx descriptors and buffers. + * + * RETURN: + * false if the given descriptors memory area is not aligned according to + * Ethernet SDMA specifications. + * true otherwise. + * + *******************************************************************************/ +static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE tx_queue, + int tx_desc_num, + int tx_buff_size, + unsigned int tx_desc_base_addr, + unsigned int tx_buff_base_addr) +{ + + ETH_TX_DESC *p_tx_desc; + ETH_TX_DESC *p_tx_prev_desc; + unsigned int buffer_addr; + int ix; /* a counter */ + + + /* save the first desc pointer to link with the last descriptor */ + p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; + p_tx_prev_desc = p_tx_desc; + buffer_addr = tx_buff_base_addr; + + /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ + if (tx_buff_base_addr & 0xF) + return false; + + /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ + if ((tx_buff_size > TX_BUFFER_MAX_SIZE) + || (tx_buff_size < TX_BUFFER_MIN_SIZE)) + return false; + + /* Initialize the Tx descriptors ring */ + for (ix = 0; ix < tx_desc_num; ix++) { + p_tx_desc->byte_cnt = 0x0000; + p_tx_desc->l4i_chk = 0x0000; + p_tx_desc->cmd_sts = 0x00000000; + p_tx_desc->next_desc_ptr = + ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; + + p_tx_desc->buf_ptr = buffer_addr; + p_tx_desc->return_info = 0x00000000; + D_CACHE_FLUSH_LINE (p_tx_desc, 0); + buffer_addr += tx_buff_size; + p_tx_prev_desc = p_tx_desc; + p_tx_desc = (ETH_TX_DESC *) + ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); + + } + /* Closing Tx descriptors ring */ + p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; + D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); + /* Set Tx desc pointer in driver struct. */ + CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); + USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); + + /* Init Tx ring base and size parameters */ + p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = + (ETH_TX_DESC *) tx_desc_base_addr; + p_eth_port_ctrl->tx_desc_area_size[tx_queue] = + (tx_desc_num * TX_DESC_ALIGNED_SIZE); + + /* Add the queue to the list of Tx queues of this port */ + p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); + + return true; +} + +/******************************************************************************* + * eth_port_send - Send an Ethernet packet + * + * DESCRIPTION: + * This routine send a given packet described by p_pktinfo parameter. It + * supports transmitting of a packet spaned over multiple buffers. The + * routine updates 'curr' and 'first' indexes according to the packet + * segment passed to the routine. In case the packet segment is first, + * the 'first' index is update. In any case, the 'curr' index is updated. + * If the routine get into Tx resource error it assigns 'curr' index as + * 'first'. This way the function can abort Tx process of multiple + * descriptors per packet. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE tx_queue Number of Tx queue. + * PKT_INFO *p_pkt_info User packet buffer. + * + * OUTPUT: + * Tx ring 'curr' and 'first' indexes are updated. + * + * RETURN: + * ETH_QUEUE_FULL in case of Tx resource error. + * ETH_ERROR in case the routine can not access Tx desc ring. + * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_TX_DESC *p_tx_desc_first; + volatile ETH_TX_DESC *p_tx_desc_curr; + volatile ETH_TX_DESC *p_tx_next_desc_curr; + volatile ETH_TX_DESC *p_tx_desc_used; + unsigned int command_status; + + /* Do not process Tx ring in case of Tx ring resource error */ + if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) + return ETH_QUEUE_FULL; + + /* Get the Tx Desc ring indexes */ + CURR_TFD_GET (p_tx_desc_curr, tx_queue); + USED_TFD_GET (p_tx_desc_used, tx_queue); + + if (p_tx_desc_curr == NULL) + return ETH_ERROR; + + /* The following parameters are used to save readings from memory */ + p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); + command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; + + if (command_status & (ETH_TX_FIRST_DESC)) { + /* Update first desc */ + FIRST_TFD_SET (p_tx_desc_curr, tx_queue); + p_tx_desc_first = p_tx_desc_curr; + } else { + FIRST_TFD_GET (p_tx_desc_first, tx_queue); + command_status |= ETH_BUFFER_OWNED_BY_DMA; + } + + /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ + /* boundary. We use the memory allocated for Tx descriptor. This memory */ + /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ + if (p_pkt_info->byte_cnt <= 8) { + printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ + return ETH_ERROR; + + p_tx_desc_curr->buf_ptr = + (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; + eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, + p_pkt_info->byte_cnt); + } else + p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; + + p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; + p_tx_desc_curr->return_info = p_pkt_info->return_info; + + if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { + /* Set last desc with DMA ownership and interrupt enable. */ + p_tx_desc_curr->cmd_sts = command_status | + ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; + + if (p_tx_desc_curr != p_tx_desc_first) + p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; + + /* Flush CPU pipe */ + + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); + CPU_PIPE_FLUSH; + + /* Apply send command */ + ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); + + /* Finish Tx packet. Update first desc in case of Tx resource error */ + p_tx_desc_first = p_tx_next_desc_curr; + FIRST_TFD_SET (p_tx_desc_first, tx_queue); + + } else { + p_tx_desc_curr->cmd_sts = command_status; + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); + } + + /* Check for ring index overlap in the Tx desc ring */ + if (p_tx_next_desc_curr == p_tx_desc_used) { + /* Update the current descriptor */ + CURR_TFD_SET (p_tx_desc_first, tx_queue); + + p_eth_port_ctrl->tx_resource_err[tx_queue] = true; + return ETH_QUEUE_LAST_RESOURCE; + } else { + /* Update the current descriptor */ + CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); + return ETH_OK; + } +} + +/******************************************************************************* + * eth_tx_return_desc - Free all used Tx descriptors + * + * DESCRIPTION: + * This routine returns the transmitted packet information to the caller. + * It uses the 'first' index to support Tx desc return in case a transmit + * of a packet spanned over multiple buffer still in process. + * In case the Tx queue was in "resource error" condition, where there are + * no available Tx resources, the function resets the resource error flag. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE tx_queue Number of Tx queue. + * PKT_INFO *p_pkt_info User packet buffer. + * + * OUTPUT: + * Tx ring 'first' and 'used' indexes are updated. + * + * RETURN: + * ETH_ERROR in case the routine can not access Tx desc ring. + * ETH_RETRY in case there is transmission in process. + * ETH_END_OF_JOB if the routine has nothing to release. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * + p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_TX_DESC *p_tx_desc_used = NULL; + volatile ETH_TX_DESC *p_tx_desc_first = NULL; + unsigned int command_status; + + + /* Get the Tx Desc ring indexes */ + USED_TFD_GET (p_tx_desc_used, tx_queue); + FIRST_TFD_GET (p_tx_desc_first, tx_queue); + + + /* Sanity check */ + if (p_tx_desc_used == NULL) + return ETH_ERROR; + + command_status = p_tx_desc_used->cmd_sts; + + /* Still transmitting... */ + if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); + return ETH_RETRY; + } + + /* Stop release. About to overlap the current available Tx descriptor */ + if ((p_tx_desc_used == p_tx_desc_first) && + (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); + return ETH_END_OF_JOB; + } + + /* Pass the packet information to the caller */ + p_pkt_info->cmd_sts = command_status; + p_pkt_info->return_info = p_tx_desc_used->return_info; + p_tx_desc_used->return_info = 0; + + /* Update the next descriptor to release. */ + USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); + + /* Any Tx return cancels the Tx resource error status */ + if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) + p_eth_port_ctrl->tx_resource_err[tx_queue] = false; + + D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); + + return ETH_OK; + +} + +/******************************************************************************* + * eth_port_receive - Get received information from Rx ring. + * + * DESCRIPTION: + * This routine returns the received data to the caller. There is no + * data copying during routine operation. All information is returned + * using pointer to packet information struct passed from the caller. + * If the routine exhausts Rx ring resources then the resource error flag + * is set. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE rx_queue Number of Rx queue. + * PKT_INFO *p_pkt_info User packet buffer. + * + * OUTPUT: + * Rx ring current and used indexes are updated. + * + * RETURN: + * ETH_ERROR in case the routine can not access Rx desc ring. + * ETH_QUEUE_FULL if Rx ring resources are exhausted. + * ETH_END_OF_JOB if there is no received data. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_RX_DESC *p_rx_curr_desc; + volatile ETH_RX_DESC *p_rx_next_curr_desc; + volatile ETH_RX_DESC *p_rx_used_desc; + unsigned int command_status; + + /* Do not process Rx ring in case of Rx ring resource error */ + if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { + printf ("\nRx Queue is full ...\n"); + return ETH_QUEUE_FULL; + } + + /* Get the Rx Desc ring 'curr and 'used' indexes */ + CURR_RFD_GET (p_rx_curr_desc, rx_queue); + USED_RFD_GET (p_rx_used_desc, rx_queue); + + /* Sanity check */ + if (p_rx_curr_desc == NULL) + return ETH_ERROR; + + /* The following parameters are used to save readings from memory */ + p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); + command_status = p_rx_curr_desc->cmd_sts; + + /* Nothing to receive... */ + if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { +/* DP(printf("Rx: command_status: %08x\n", command_status)); */ + D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); +/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ + return ETH_END_OF_JOB; + } + + p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; + p_pkt_info->cmd_sts = command_status; + p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; + p_pkt_info->return_info = p_rx_curr_desc->return_info; + p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ + + /* Clean the return info field to indicate that the packet has been */ + /* moved to the upper layers */ + p_rx_curr_desc->return_info = 0; + + /* Update 'curr' in data structure */ + CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); + + /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ + if (p_rx_next_curr_desc == p_rx_used_desc) + p_eth_port_ctrl->rx_resource_err[rx_queue] = true; + + D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); + CPU_PIPE_FLUSH; + return ETH_OK; +} + +/******************************************************************************* + * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. + * + * DESCRIPTION: + * This routine returns a Rx buffer back to the Rx ring. It retrieves the + * next 'used' descriptor and attached the returned buffer to it. + * In case the Rx ring was in "resource error" condition, where there are + * no available Rx resources, the function resets the resource error flag. + * + * INPUT: + * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. + * ETH_QUEUE rx_queue Number of Rx queue. + * PKT_INFO *p_pkt_info Information on the returned buffer. + * + * OUTPUT: + * New available Rx resource in Rx descriptor ring. + * + * RETURN: + * ETH_ERROR in case the routine can not access Rx desc ring. + * ETH_OK otherwise. + * + *******************************************************************************/ +static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * + p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO * p_pkt_info) +{ + volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ + + /* Get 'used' Rx descriptor */ + USED_RFD_GET (p_used_rx_desc, rx_queue); + + /* Sanity check */ + if (p_used_rx_desc == NULL) + return ETH_ERROR; + + p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; + p_used_rx_desc->return_info = p_pkt_info->return_info; + p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; + p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ + + /* Flush the write pipe */ + CPU_PIPE_FLUSH; + + /* Return the descriptor to DMA ownership */ + p_used_rx_desc->cmd_sts = + ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; + + /* Flush descriptor and CPU pipe */ + D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); + CPU_PIPE_FLUSH; + + /* Move the used descriptor pointer to the next descriptor */ + USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); + + /* Any Rx return cancels the Rx resource error status */ + if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) + p_eth_port_ctrl->rx_resource_err[rx_queue] = false; + + return ETH_OK; +} + +/******************************************************************************* + * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path + * + * DESCRIPTION: + * This routine sets the RX coalescing interrupt mechanism parameter. + * This parameter is a timeout counter, that counts in 64 t_clk + * chunks ; that when timeout event occurs a maskable interrupt + * occurs. + * The parameter is calculated using the tClk of the MV-643xx chip + * , and the required delay of the interrupt in usec. + * + * INPUT: + * ETH_PORT eth_port_num Ethernet port number + * unsigned int t_clk t_clk of the MV-643xx chip in HZ units + * unsigned int delay Delay in usec + * + * OUTPUT: + * Interrupt coalescing mechanism value is set in MV-643xx chip. + * + * RETURN: + * The interrupt coalescing value set in the gigE port. + * + *******************************************************************************/ +#if 0 /* FIXME */ +static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, + unsigned int t_clk, + unsigned int delay) +{ + unsigned int coal; + + coal = ((t_clk / 1000000) * delay) / 64; + /* Set RX Coalescing mechanism */ + MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), + ((coal & 0x3fff) << 8) | + (MV_REG_READ + (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) + & 0xffc000ff)); + return coal; +} + +#endif +/******************************************************************************* + * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path + * + * DESCRIPTION: + * This routine sets the TX coalescing interrupt mechanism parameter. + * This parameter is a timeout counter, that counts in 64 t_clk + * chunks ; that when timeout event occurs a maskable interrupt + * occurs. + * The parameter is calculated using the t_cLK frequency of the + * MV-643xx chip and the required delay in the interrupt in uSec + * + * INPUT: + * ETH_PORT eth_port_num Ethernet port number + * unsigned int t_clk t_clk of the MV-643xx chip in HZ units + * unsigned int delay Delay in uSeconds + * + * OUTPUT: + * Interrupt coalescing mechanism value is set in MV-643xx chip. + * + * RETURN: + * The interrupt coalescing value set in the gigE port. + * + *******************************************************************************/ +#if 0 /* FIXME */ +static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, + unsigned int t_clk, + unsigned int delay) +{ + unsigned int coal; + + coal = ((t_clk / 1000000) * delay) / 64; + /* Set TX Coalescing mechanism */ + MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), + coal << 4); + return coal; +} +#endif + +/******************************************************************************* + * eth_b_copy - Copy bytes from source to destination + * + * DESCRIPTION: + * This function supports the eight bytes limitation on Tx buffer size. + * The routine will zero eight bytes starting from the destination address + * followed by copying bytes from the source address to the destination. + * + * INPUT: + * unsigned int src_addr 32 bit source address. + * unsigned int dst_addr 32 bit destination address. + * int byte_count Number of bytes to copy. + * + * OUTPUT: + * See description. + * + * RETURN: + * None. + * + *******************************************************************************/ +static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, + int byte_count) +{ + /* Zero the dst_addr area */ + *(unsigned int *) dst_addr = 0x0; + + while (byte_count != 0) { + *(char *) dst_addr = *(char *) src_addr; + dst_addr++; + src_addr++; + byte_count--; + } +} diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h new file mode 100644 index 0000000..c57e679 --- /dev/null +++ b/board/esd/cpci750/mv_eth.h @@ -0,0 +1,844 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mv_eth.h - header file for the polled mode GT ethernet driver + */ + +#ifndef __DB64360_ETH_H__ +#define __DB64360_ETH_H__ + +#include +#include +#include +#include +#include +#include "mv_regs.h" +#include "../../Marvell/common/ppc_error_no.h" + + +/************************************************************************* +************************************************************************** +************************************************************************** +* The first part is the high level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ +#ifndef MAX_SKB_FRAGS +#define MAX_SKB_FRAGS 0 +#endif + +/* Port attributes */ +/*#define MAX_RX_QUEUE_NUM 8*/ +/*#define MAX_TX_QUEUE_NUM 8*/ +#define MAX_RX_QUEUE_NUM 1 +#define MAX_TX_QUEUE_NUM 1 + + +/* Use one TX queue and one RX queue */ +#define MV64360_TX_QUEUE_NUM 1 +#define MV64360_RX_QUEUE_NUM 1 + +/* + * Number of RX / TX descriptors on RX / TX rings. + * Note that allocating RX descriptors is done by allocating the RX + * ring AND a preallocated RX buffers (skb's) for each descriptor. + * The TX descriptors only allocates the TX descriptors ring, + * with no pre allocated TX buffers (skb's are allocated by higher layers. + */ + +/* Default TX ring size is 10 descriptors */ +#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE +#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE +#else +#define MV64360_TX_QUEUE_SIZE 4 +#endif + +/* Default RX ring size is 4 descriptors */ +#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE +#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE +#else +#define MV64360_RX_QUEUE_SIZE 4 +#endif + +#ifdef CONFIG_RX_BUFFER_SIZE +#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE +#else +#define MV64360_RX_BUFFER_SIZE 1600 +#endif + +#ifdef CONFIG_TX_BUFFER_SIZE +#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE +#else +#define MV64360_TX_BUFFER_SIZE 1600 +#endif + + +/* + * Network device statistics. Akin to the 2.0 ether stats but + * with byte counters. + */ + +struct net_device_stats +{ + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_errors; /* bad packets received */ + unsigned long tx_errors; /* packet transmit problems */ + unsigned long rx_dropped; /* no space in linux buffers */ + unsigned long tx_dropped; /* no space available in linux */ + unsigned long multicast; /* multicast packets received */ + unsigned long collisions; + + /* detailed rx_errors: */ + unsigned long rx_length_errors; + unsigned long rx_over_errors; /* receiver ring buff overflow */ + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_frame_errors; /* recv'd frame alignment error */ + unsigned long rx_fifo_errors; /* recv'r fifo overrun */ + unsigned long rx_missed_errors; /* receiver missed packet */ + + /* detailed tx_errors */ + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; + + /* for cslip etc */ + unsigned long rx_compressed; + unsigned long tx_compressed; +}; + + +/* Private data structure used for ethernet device */ +struct mv64360_eth_priv { + unsigned int port_num; + struct net_device_stats *stats; + +/* to buffer area aligned */ + char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ + char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ + + /* Size of Tx Ring per queue */ + unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; + + + /* Size of Rx Ring per queue */ + unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; + + /* Magic Number for Ethernet running */ + unsigned int eth_running; + +}; + + +int mv64360_eth_init (struct eth_device *dev); +int mv64360_eth_stop (struct eth_device *dev); +int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length); +/* return db64360_eth0_poll(); */ + +int mv64360_eth_open (struct eth_device *dev); + + +/************************************************************************* +************************************************************************** +************************************************************************** +* The second part is the low level driver of the gigE ethernet ports. * +************************************************************************** +************************************************************************** +*************************************************************************/ + + +/******************************************************************************** + * Header File for : MV-643xx network interface header + * + * DESCRIPTION: + * This header file contains macros typedefs and function declaration for + * the Marvell Gig Bit Ethernet Controller. + * + * DEPENDENCIES: + * None. + * + *******************************************************************************/ + + +#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY +#ifdef CONFIG_MV64360_SRAM_CACHEABLE +/* In case SRAM is cacheable but not cache coherent */ +#define D_CACHE_FLUSH_LINE(addr, offset) \ +{ \ + __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ +} +#else +/* In case SRAM is cache coherent or non-cacheable */ +#define D_CACHE_FLUSH_LINE(addr, offset) ; +#endif +#else +#ifdef CONFIG_NOT_COHERENT_CACHE +/* In case of descriptors on DDR but not cache coherent */ +#define D_CACHE_FLUSH_LINE(addr, offset) \ +{ \ + __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ +} +#else +/* In case of descriptors on DDR and cache coherent */ +#define D_CACHE_FLUSH_LINE(addr, offset) ; +#endif /* CONFIG_NOT_COHERENT_CACHE */ +#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ + + +#define CPU_PIPE_FLUSH \ +{ \ + __asm__ __volatile__ ("eieio"); \ +} + + +/* defines */ + +/* Default port configuration value */ +#define PORT_CONFIG_VALUE \ + ETH_UNICAST_NORMAL_MODE | \ + ETH_DEFAULT_RX_QUEUE_0 | \ + ETH_DEFAULT_RX_ARP_QUEUE_0 | \ + ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ + ETH_RECEIVE_BC_IF_IP | \ + ETH_RECEIVE_BC_IF_ARP | \ + ETH_CAPTURE_TCP_FRAMES_DIS | \ + ETH_CAPTURE_UDP_FRAMES_DIS | \ + ETH_DEFAULT_RX_TCP_QUEUE_0 | \ + ETH_DEFAULT_RX_UDP_QUEUE_0 | \ + ETH_DEFAULT_RX_BPDU_QUEUE_0 + +/* Default port extend configuration value */ +#define PORT_CONFIG_EXTEND_VALUE \ + ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ + ETH_PARTITION_DISABLE + + +/* Default sdma control value */ +#ifdef CONFIG_NOT_COHERENT_CACHE +#define PORT_SDMA_CONFIG_VALUE \ + ETH_RX_BURST_SIZE_16_64BIT | \ + GT_ETH_IPG_INT_RX(0) | \ + ETH_TX_BURST_SIZE_16_64BIT; +#else +#define PORT_SDMA_CONFIG_VALUE \ + ETH_RX_BURST_SIZE_4_64BIT | \ + GT_ETH_IPG_INT_RX(0) | \ + ETH_TX_BURST_SIZE_4_64BIT; +#endif + +#define GT_ETH_IPG_INT_RX(value) \ + ((value & 0x3fff) << 8) + +/* Default port serial control value */ +#define PORT_SERIAL_CONTROL_VALUE \ + ETH_FORCE_LINK_PASS | \ + ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ + ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ + ETH_ADV_SYMMETRIC_FLOW_CTRL | \ + ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + ETH_FORCE_BP_MODE_NO_JAM | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL | \ + ETH_RETRANSMIT_16_ETTEMPTS | \ + ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ + ETH_DTE_ADV_0 | \ + ETH_DISABLE_AUTO_NEG_BYPASS | \ + ETH_AUTO_NEG_NO_CHANGE | \ + ETH_MAX_RX_PACKET_1552BYTE | \ + ETH_CLR_EXT_LOOPBACK | \ + ETH_SET_FULL_DUPLEX_MODE | \ + ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; + +#define RX_BUFFER_MAX_SIZE 0xFFFF +#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ + +#define RX_BUFFER_MIN_SIZE 0x8 +#define TX_BUFFER_MIN_SIZE 0x8 + +/* Tx WRR confoguration macros */ +#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ +#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ +#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ + +/* MAC accepet/reject macros */ +#define ACCEPT_MAC_ADDR 0 +#define REJECT_MAC_ADDR 1 + +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define RX_DESC_ALIGNED_SIZE 0x20 +#define TX_DESC_ALIGNED_SIZE 0x20 + +/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ +#define TX_BUF_OFFSET_IN_DESC 0x18 +/* Buffer offset from buffer pointer */ +#define RX_BUF_OFFSET 0x2 + +/* Gap define */ +#define ETH_BAR_GAP 0x8 +#define ETH_SIZE_REG_GAP 0x8 +#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 +#define ETH_PORT_ACCESS_CTRL_GAP 0x4 + +/* Gigabit Ethernet Unit Global Registers */ + +/* MIB Counters register definitions */ +#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 +#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 +#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 +#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc +#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 +#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 +#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 +#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c +#define ETH_MIB_FRAMES_64_OCTETS 0x20 +#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 +#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 +#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c +#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 +#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 +#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 +#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c +#define ETH_MIB_GOOD_FRAMES_SENT 0x40 +#define ETH_MIB_EXCESSIVE_COLLISION 0x44 +#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 +#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c +#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 +#define ETH_MIB_FC_SENT 0x54 +#define ETH_MIB_GOOD_FC_RECEIVED 0x58 +#define ETH_MIB_BAD_FC_RECEIVED 0x5c +#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 +#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 +#define ETH_MIB_OVERSIZE_RECEIVED 0x68 +#define ETH_MIB_JABBER_RECEIVED 0x6c +#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 +#define ETH_MIB_BAD_CRC_EVENT 0x74 +#define ETH_MIB_COLLISION 0x78 +#define ETH_MIB_LATE_COLLISION 0x7c + +/* Port serial status reg (PSR) */ +#define ETH_INTERFACE_GMII_MII 0 +#define ETH_INTERFACE_PCM BIT0 +#define ETH_LINK_IS_DOWN 0 +#define ETH_LINK_IS_UP BIT1 +#define ETH_PORT_AT_HALF_DUPLEX 0 +#define ETH_PORT_AT_FULL_DUPLEX BIT2 +#define ETH_RX_FLOW_CTRL_DISABLED 0 +#define ETH_RX_FLOW_CTRL_ENBALED BIT3 +#define ETH_GMII_SPEED_100_10 0 +#define ETH_GMII_SPEED_1000 BIT4 +#define ETH_MII_SPEED_10 0 +#define ETH_MII_SPEED_100 BIT5 +#define ETH_NO_TX 0 +#define ETH_TX_IN_PROGRESS BIT7 +#define ETH_BYPASS_NO_ACTIVE 0 +#define ETH_BYPASS_ACTIVE BIT8 +#define ETH_PORT_NOT_AT_PARTITION_STATE 0 +#define ETH_PORT_AT_PARTITION_STATE BIT9 +#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 +#define ETH_PORT_TX_FIFO_EMPTY BIT10 + + +/* These macros describes the Port configuration reg (Px_cR) bits */ +#define ETH_UNICAST_NORMAL_MODE 0 +#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 +#define ETH_DEFAULT_RX_QUEUE_0 0 +#define ETH_DEFAULT_RX_QUEUE_1 BIT1 +#define ETH_DEFAULT_RX_QUEUE_2 BIT2 +#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) +#define ETH_DEFAULT_RX_QUEUE_4 BIT3 +#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) +#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) +#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) +#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 +#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 +#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 +#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) +#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 +#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) +#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) +#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) +#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 +#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 +#define ETH_RECEIVE_BC_IF_IP 0 +#define ETH_REJECT_BC_IF_IP BIT8 +#define ETH_RECEIVE_BC_IF_ARP 0 +#define ETH_REJECT_BC_IF_ARP BIT9 +#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 +#define ETH_CAPTURE_TCP_FRAMES_DIS 0 +#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 +#define ETH_CAPTURE_UDP_FRAMES_DIS 0 +#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 +#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 +#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 +#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 +#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) +#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 +#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) +#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) +#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) +#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 +#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 +#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 +#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) +#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 +#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) +#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) +#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) +#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 +#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 +#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 +#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) +#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 +#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) +#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) +#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) + + +/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ +#define ETH_CLASSIFY_EN BIT0 +#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 +#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 +#define ETH_PARTITION_DISABLE 0 +#define ETH_PARTITION_ENABLE BIT2 + + +/* Tx/Rx queue command reg (RQCR/TQCR)*/ +#define ETH_QUEUE_0_ENABLE BIT0 +#define ETH_QUEUE_1_ENABLE BIT1 +#define ETH_QUEUE_2_ENABLE BIT2 +#define ETH_QUEUE_3_ENABLE BIT3 +#define ETH_QUEUE_4_ENABLE BIT4 +#define ETH_QUEUE_5_ENABLE BIT5 +#define ETH_QUEUE_6_ENABLE BIT6 +#define ETH_QUEUE_7_ENABLE BIT7 +#define ETH_QUEUE_0_DISABLE BIT8 +#define ETH_QUEUE_1_DISABLE BIT9 +#define ETH_QUEUE_2_DISABLE BIT10 +#define ETH_QUEUE_3_DISABLE BIT11 +#define ETH_QUEUE_4_DISABLE BIT12 +#define ETH_QUEUE_5_DISABLE BIT13 +#define ETH_QUEUE_6_DISABLE BIT14 +#define ETH_QUEUE_7_DISABLE BIT15 + + +/* These macros describes the Port Sdma configuration reg (SDCR) bits */ +#define ETH_RIFB BIT0 +#define ETH_RX_BURST_SIZE_1_64BIT 0 +#define ETH_RX_BURST_SIZE_2_64BIT BIT1 +#define ETH_RX_BURST_SIZE_4_64BIT BIT2 +#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) +#define ETH_RX_BURST_SIZE_16_64BIT BIT3 +#define ETH_BLM_RX_NO_SWAP BIT4 +#define ETH_BLM_RX_BYTE_SWAP 0 +#define ETH_BLM_TX_NO_SWAP BIT5 +#define ETH_BLM_TX_BYTE_SWAP 0 +#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 +#define ETH_DESCRIPTORS_NO_SWAP 0 +#define ETH_TX_BURST_SIZE_1_64BIT 0 +#define ETH_TX_BURST_SIZE_2_64BIT BIT22 +#define ETH_TX_BURST_SIZE_4_64BIT BIT23 +#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) +#define ETH_TX_BURST_SIZE_16_64BIT BIT24 + + +/* These macros describes the Port serial control reg (PSCR) bits */ +#define ETH_SERIAL_PORT_DISABLE 0 +#define ETH_SERIAL_PORT_ENABLE BIT0 +#define ETH_FORCE_LINK_PASS BIT1 +#define ETH_DO_NOT_FORCE_LINK_PASS 0 +#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 +#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 +#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 +#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 +#define ETH_ADV_NO_FLOW_CTRL 0 +#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 +#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 +#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 +#define ETH_FORCE_BP_MODE_NO_JAM 0 +#define ETH_FORCE_BP_MODE_JAM_TX BIT7 +#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 +#define ETH_FORCE_LINK_FAIL 0 +#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 +#define ETH_RETRANSMIT_16_ETTEMPTS 0 +#define ETH_RETRANSMIT_FOREVER BIT11 +#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 +#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 +#define ETH_DTE_ADV_0 0 +#define ETH_DTE_ADV_1 BIT14 +#define ETH_DISABLE_AUTO_NEG_BYPASS 0 +#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 +#define ETH_AUTO_NEG_NO_CHANGE 0 +#define ETH_RESTART_AUTO_NEG BIT16 +#define ETH_MAX_RX_PACKET_1518BYTE 0 +#define ETH_MAX_RX_PACKET_1522BYTE BIT17 +#define ETH_MAX_RX_PACKET_1552BYTE BIT18 +#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) +#define ETH_MAX_RX_PACKET_9192BYTE BIT19 +#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) +#define ETH_SET_EXT_LOOPBACK BIT20 +#define ETH_CLR_EXT_LOOPBACK 0 +#define ETH_SET_FULL_DUPLEX_MODE BIT21 +#define ETH_SET_HALF_DUPLEX_MODE 0 +#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 +#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 +#define ETH_SET_GMII_SPEED_TO_10_100 0 +#define ETH_SET_GMII_SPEED_TO_1000 BIT23 +#define ETH_SET_MII_SPEED_TO_10 0 +#define ETH_SET_MII_SPEED_TO_100 BIT24 + + +/* SMI reg */ +#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ +#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ +#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ +#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ + +/* SDMA command status fields macros */ + +/* Tx & Rx descriptors status */ +#define ETH_ERROR_SUMMARY (BIT0) + +/* Tx & Rx descriptors command */ +#define ETH_BUFFER_OWNED_BY_DMA (BIT31) + +/* Tx descriptors status */ +#define ETH_LC_ERROR (0 ) +#define ETH_UR_ERROR (BIT1 ) +#define ETH_RL_ERROR (BIT2 ) +#define ETH_LLC_SNAP_FORMAT (BIT9 ) + +/* Rx descriptors status */ +#define ETH_CRC_ERROR (0 ) +#define ETH_OVERRUN_ERROR (BIT1 ) +#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) +#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) +#define ETH_VLAN_TAGGED (BIT19) +#define ETH_BPDU_FRAME (BIT20) +#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) +#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) +#define ETH_OTHER_FRAME_TYPE (BIT22) +#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) +#define ETH_FRAME_TYPE_IP_V_4 (BIT24) +#define ETH_FRAME_HEADER_OK (BIT25) +#define ETH_RX_LAST_DESC (BIT26) +#define ETH_RX_FIRST_DESC (BIT27) +#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) +#define ETH_RX_ENABLE_INTERRUPT (BIT29) +#define ETH_LAYER_4_CHECKSUM_OK (BIT30) + +/* Rx descriptors byte count */ +#define ETH_FRAME_FRAGMENTED (BIT2) + +/* Tx descriptors command */ +#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) +#define ETH_FRAME_SET_TO_VLAN (BIT15) +#define ETH_TCP_FRAME (0 ) +#define ETH_UDP_FRAME (BIT16) +#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) +#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) +#define ETH_ZERO_PADDING (BIT19) +#define ETH_TX_LAST_DESC (BIT20) +#define ETH_TX_FIRST_DESC (BIT21) +#define ETH_GEN_CRC (BIT22) +#define ETH_TX_ENABLE_INTERRUPT (BIT23) +#define ETH_AUTO_MODE (BIT30) + +/* Address decode parameters */ +/* Ethernet Base Address Register bits */ +#define EBAR_TARGET_DRAM 0x00000000 +#define EBAR_TARGET_DEVICE 0x00000001 +#define EBAR_TARGET_CBS 0x00000002 +#define EBAR_TARGET_PCI0 0x00000003 +#define EBAR_TARGET_PCI1 0x00000004 +#define EBAR_TARGET_CUNIT 0x00000005 +#define EBAR_TARGET_AUNIT 0x00000006 +#define EBAR_TARGET_GUNIT 0x00000007 + +/* Window attributes */ +#define EBAR_ATTR_DRAM_CS0 0x00000E00 +#define EBAR_ATTR_DRAM_CS1 0x00000D00 +#define EBAR_ATTR_DRAM_CS2 0x00000B00 +#define EBAR_ATTR_DRAM_CS3 0x00000700 + +/* DRAM Target interface */ +#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 +#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 +#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 + +/* Device Bus Target interface */ +#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 +#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 +#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 +#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 +#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 + +/* PCI Target interface */ +#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 +#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 +#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 +#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 +#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 +#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 +#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 +#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 +#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 +#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 + +/* CPU 60x bus or internal SRAM interface */ +#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 +#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 +#define EBAR_ATTR_CBS_SRAM 0x00000000 +#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 + +/* Window access control */ +#define EWIN_ACCESS_NOT_ALLOWED 0 +#define EWIN_ACCESS_READ_ONLY BIT0 +#define EWIN_ACCESS_FULL (BIT1 | BIT0) +#define EWIN0_ACCESS_MASK 0x0003 +#define EWIN1_ACCESS_MASK 0x000C +#define EWIN2_ACCESS_MASK 0x0030 +#define EWIN3_ACCESS_MASK 0x00C0 + +/* typedefs */ + +typedef enum _eth_port +{ + ETH_0 = 0, + ETH_1 = 1, + ETH_2 = 2 +}ETH_PORT; + +typedef enum _eth_func_ret_status +{ + ETH_OK, /* Returned as expected. */ + ETH_ERROR, /* Fundamental error. */ + ETH_RETRY, /* Could not process request. Try later. */ + ETH_END_OF_JOB, /* Ring has nothing to process. */ + ETH_QUEUE_FULL, /* Ring resource error. */ + ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ +}ETH_FUNC_RET_STATUS; + +typedef enum _eth_queue +{ + ETH_Q0 = 0, + ETH_Q1 = 1, + ETH_Q2 = 2, + ETH_Q3 = 3, + ETH_Q4 = 4, + ETH_Q5 = 5, + ETH_Q6 = 6, + ETH_Q7 = 7 +} ETH_QUEUE; + +typedef enum _addr_win +{ + ETH_WIN0, + ETH_WIN1, + ETH_WIN2, + ETH_WIN3, + ETH_WIN4, + ETH_WIN5 +} ETH_ADDR_WIN; + +typedef enum _eth_target +{ + ETH_TARGET_DRAM , + ETH_TARGET_DEVICE, + ETH_TARGET_CBS , + ETH_TARGET_PCI0 , + ETH_TARGET_PCI1 +}ETH_TARGET; + +typedef struct _eth_rx_desc +{ + unsigned short byte_cnt ; /* Descriptor buffer byte count */ + unsigned short buf_size ; /* Buffer size */ + unsigned int cmd_sts ; /* Descriptor command status */ + unsigned int next_desc_ptr; /* Next descriptor pointer */ + unsigned int buf_ptr ; /* Descriptor buffer pointer */ + unsigned int return_info ; /* User resource return information */ +} ETH_RX_DESC; + + +typedef struct _eth_tx_desc +{ + unsigned short byte_cnt ; /* Descriptor buffer byte count */ + unsigned short l4i_chk ; /* CPU provided TCP Checksum */ + unsigned int cmd_sts ; /* Descriptor command status */ + unsigned int next_desc_ptr; /* Next descriptor pointer */ + unsigned int buf_ptr ; /* Descriptor buffer pointer */ + unsigned int return_info ; /* User resource return information */ +} ETH_TX_DESC; + +/* Unified struct for Rx and Tx operations. The user is not required to */ +/* be familier with neither Tx nor Rx descriptors. */ +typedef struct _pkt_info +{ + unsigned short byte_cnt ; /* Descriptor buffer byte count */ + unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ + unsigned int cmd_sts ; /* Descriptor command status */ + unsigned int buf_ptr ; /* Descriptor buffer pointer */ + unsigned int return_info ; /* User resource return information */ +} PKT_INFO; + + +typedef struct _eth_win_param +{ + ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ + ETH_TARGET target; /* System targets. See ETH_TARGET enum */ + unsigned short attributes; /* BAR attributes. See above macros. */ + unsigned int base_addr; /* Window base address in unsigned int form */ + unsigned int high_addr; /* Window high address in unsigned int form */ + unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ + bool enable; /* Enable/disable access to the window. */ + unsigned short access_ctrl; /* Access ctrl register. see above macros */ +} ETH_WIN_PARAM; + + +/* Ethernet port specific infomation */ + +typedef struct _eth_port_ctrl +{ + ETH_PORT port_num; /* User Ethernet port number */ + int port_phy_addr; /* User phy address of Ethrnet port */ + unsigned char port_mac_addr[6]; /* User defined port MAC address. */ + unsigned int port_config; /* User port configuration value */ + unsigned int port_config_extend; /* User port config extend value */ + unsigned int port_sdma_config; /* User port SDMA config value */ + unsigned int port_serial_control; /* User port serial control value */ + unsigned int port_tx_queue_command; /* Port active Tx queues summary */ + unsigned int port_rx_queue_command; /* Port active Rx queues summary */ + + /* User function to cast virtual address to CPU bus address */ + unsigned int (*port_virt_to_phys)(unsigned int addr); + /* User scratch pad for user specific data structures */ + void *port_private; + + bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ + bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ + + /* Tx/Rx rings managment indexes fields. For driver use */ + + /* Next available Rx resource */ + volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; + /* Returning Rx resource */ + volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; + + /* Next available Tx resource */ + volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; + /* Returning Tx resource */ + volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; + /* An extra Tx index to support transmit of multiple buffers per packet */ + volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; + + /* Tx/Rx rings size and base variables fields. For driver use */ + + volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; + unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; + char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; + + volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; + unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; + char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; + +} ETH_PORT_INFO; + + +/* ethernet.h API list */ + +/* Port operation control routines */ +static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); +static void eth_port_reset(ETH_PORT eth_port_num); +static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); + + +/* Port MAC address routines */ +static void eth_port_uc_addr_set (ETH_PORT eth_port_num, + unsigned char *p_addr, + ETH_QUEUE queue); +#if 0 /* FIXME */ +static void eth_port_mc_addr (ETH_PORT eth_port_num, + unsigned char *p_addr, + ETH_QUEUE queue, + int option); +#endif + +/* PHY and MIB routines */ +static bool ethernet_phy_reset(ETH_PORT eth_port_num); + +static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, + unsigned int phy_reg, + unsigned int value); + +static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, + unsigned int phy_reg, + unsigned int* value); + +static void eth_clear_mib_counters(ETH_PORT eth_port_num); + +/* Port data flow control routines */ +static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO *p_pkt_info); +static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE tx_queue, + PKT_INFO *p_pkt_info); +static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO *p_pkt_info); +static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE rx_queue, + PKT_INFO *p_pkt_info); + + +static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE tx_queue, + int tx_desc_num, + int tx_buff_size, + unsigned int tx_desc_base_addr, + unsigned int tx_buff_base_addr); + +static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, + ETH_QUEUE rx_queue, + int rx_desc_num, + int rx_buff_size, + unsigned int rx_desc_base_addr, + unsigned int rx_buff_base_addr); + +#endif /* MV64360_ETH_ */ diff --git a/board/esd/cpci750/mv_regs.h b/board/esd/cpci750/mv_regs.h new file mode 100644 index 0000000..0d6370b --- /dev/null +++ b/board/esd/cpci750/mv_regs.h @@ -0,0 +1,1124 @@ +/* + * (C) Copyright 2003 + * Ingo Assmus + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/******************************************************************************** +* gt64360r.h - GT-64360 Internal registers definition file. +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv_regsh +#define __INCmv_regsh + +#define MV64360 + +/* Supported by the Atlantis */ +#define MV64360_INCLUDE_PCI_1 +#define MV64360_INCLUDE_PCI_0_ARBITER +#define MV64360_INCLUDE_PCI_1_ARBITER +#define MV64360_INCLUDE_SNOOP_SUPPORT +#define MV64360_INCLUDE_P2P +#define MV64360_INCLUDE_ETH_PORT_2 +#define MV64360_INCLUDE_CPU_MAPPING +#define MV64360_INCLUDE_MPSC + +/* Not supported features */ +#undef INCLUDE_CNTMR_4_7 +#undef INCLUDE_DMA_4_7 + +/****************************************/ +/* Processor Address Space */ +/****************************************/ + +/* DDR SDRAM BAR and size registers */ + +#define MV64360_CS_0_BASE_ADDR 0x008 +#define MV64360_CS_0_SIZE 0x010 +#define MV64360_CS_1_BASE_ADDR 0x208 +#define MV64360_CS_1_SIZE 0x210 +#define MV64360_CS_2_BASE_ADDR 0x018 +#define MV64360_CS_2_SIZE 0x020 +#define MV64360_CS_3_BASE_ADDR 0x218 +#define MV64360_CS_3_SIZE 0x220 + +/* Devices BAR and size registers */ + +#define MV64360_DEV_CS0_BASE_ADDR 0x028 +#define MV64360_DEV_CS0_SIZE 0x030 +#define MV64360_DEV_CS1_BASE_ADDR 0x228 +#define MV64360_DEV_CS1_SIZE 0x230 +#define MV64360_DEV_CS2_BASE_ADDR 0x248 +#define MV64360_DEV_CS2_SIZE 0x250 +#define MV64360_DEV_CS3_BASE_ADDR 0x038 +#define MV64360_DEV_CS3_SIZE 0x040 +#define MV64360_BOOTCS_BASE_ADDR 0x238 +#define MV64360_BOOTCS_SIZE 0x240 + +/* PCI 0 BAR and size registers */ + +#define MV64360_PCI_0_IO_BASE_ADDR 0x048 +#define MV64360_PCI_0_IO_SIZE 0x050 +#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058 +#define MV64360_PCI_0_MEMORY0_SIZE 0x060 +#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080 +#define MV64360_PCI_0_MEMORY1_SIZE 0x088 +#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258 +#define MV64360_PCI_0_MEMORY2_SIZE 0x260 +#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280 +#define MV64360_PCI_0_MEMORY3_SIZE 0x288 + +/* PCI 1 BAR and size registers */ +#define MV64360_PCI_1_IO_BASE_ADDR 0x090 +#define MV64360_PCI_1_IO_SIZE 0x098 +#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0 +#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8 +#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0 +#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8 +#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0 +#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8 +#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0 +#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8 + +/* SRAM base address */ +#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268 + +/* internal registers space base address */ +#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068 + +/* Enables the CS , DEV_CS , PCI 0 and PCI 1 + windows above */ +#define MV64360_BASE_ADDR_ENABLE 0x278 + +/****************************************/ +/* PCI remap registers */ +/****************************************/ + /* PCI 0 */ +#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0 +#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 +#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 +#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 +#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 +#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 +#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 +#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 +#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 + /* PCI 1 */ +#define MV64360_PCI_1_IO_ADDR_REMAP 0x108 +#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 +#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 +#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 +#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 +#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 +#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 +#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 +#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 + +#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 +#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 +#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 +#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 +#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 +#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 +#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 +#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 + +/****************************************/ +/* CPU Control Registers */ +/****************************************/ + +#define MV64360_CPU_CONFIG 0x000 +#define MV64360_CPU_MODE 0x120 +#define MV64360_CPU_MASTER_CONTROL 0x160 +#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150 +#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158 +#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168 + +/****************************************/ +/* SMP RegisterS */ +/****************************************/ + +#define MV64360_SMP_WHO_AM_I 0x200 +#define MV64360_SMP_CPU0_DOORBELL 0x214 +#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C +#define MV64360_SMP_CPU1_DOORBELL 0x224 +#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C +#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234 +#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C +#define MV64360_SMP_SEMAPHOR0 0x244 +#define MV64360_SMP_SEMAPHOR1 0x24c +#define MV64360_SMP_SEMAPHOR2 0x254 +#define MV64360_SMP_SEMAPHOR3 0x25c +#define MV64360_SMP_SEMAPHOR4 0x264 +#define MV64360_SMP_SEMAPHOR5 0x26c +#define MV64360_SMP_SEMAPHOR6 0x274 +#define MV64360_SMP_SEMAPHOR7 0x27c + +/****************************************/ +/* CPU Sync Barrier Register */ +/****************************************/ + +#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 +#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 +#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 +#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 + +/****************************************/ +/* CPU Access Protect */ +/****************************************/ + +#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 +#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188 +#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 +#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198 +#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 +#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 +#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 +#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 + + +/****************************************/ +/* CPU Error Report */ +/****************************************/ + +#define MV64360_CPU_ERROR_ADDR_LOW 0x070 +#define MV64360_CPU_ERROR_ADDR_HIGH 0x078 +#define MV64360_CPU_ERROR_DATA_LOW 0x128 +#define MV64360_CPU_ERROR_DATA_HIGH 0x130 +#define MV64360_CPU_ERROR_PARITY 0x138 +#define MV64360_CPU_ERROR_CAUSE 0x140 +#define MV64360_CPU_ERROR_MASK 0x148 + +/****************************************/ +/* CPU Interface Debug Registers */ +/****************************************/ + +#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360 +#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368 +#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370 +#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378 +#define MV64360_PUNIT_MMASK 0x3e4 + +/****************************************/ +/* Integrated SRAM Registers */ +/****************************************/ + +#define MV64360_SRAM_CONFIG 0x380 +#define MV64360_SRAM_TEST_MODE 0X3F4 +#define MV64360_SRAM_ERROR_CAUSE 0x388 +#define MV64360_SRAM_ERROR_ADDR 0x390 +#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8 +#define MV64360_SRAM_ERROR_DATA_LOW 0x398 +#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0 +#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8 + +/****************************************/ +/* SDRAM Configuration */ +/****************************************/ + +#define MV64360_SDRAM_CONFIG 0x1400 +#define MV64360_D_UNIT_CONTROL_LOW 0x1404 +#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 +#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408 +#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c +#define MV64360_SDRAM_ADDR_CONTROL 0x1410 +#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414 +#define MV64360_SDRAM_OPERATION 0x1418 +#define MV64360_SDRAM_MODE 0x141c +#define MV64360_EXTENDED_DRAM_MODE 0x1420 +#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 +#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 +#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438 +#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 +#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4 + +/****************************************/ +/* SDRAM Error Report */ +/****************************************/ + +#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444 +#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440 +#define MV64360_SDRAM_ERROR_ADDR 0x1450 +#define MV64360_SDRAM_RECEIVED_ECC 0x1448 +#define MV64360_SDRAM_CALCULATED_ECC 0x144c +#define MV64360_SDRAM_ECC_CONTROL 0x1454 +#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458 + +/******************************************/ +/* Controlled Delay Line (CDL) Registers */ +/******************************************/ + +#define MV64360_DFCDL_CONFIG0 0x1480 +#define MV64360_DFCDL_CONFIG1 0x1484 +#define MV64360_DLL_WRITE 0x1488 +#define MV64360_DLL_READ 0x148c +#define MV64360_SRAM_ADDR 0x1490 +#define MV64360_SRAM_DATA0 0x1494 +#define MV64360_SRAM_DATA1 0x1498 +#define MV64360_SRAM_DATA2 0x149c +#define MV64360_DFCL_PROBE 0x14a0 + +/******************************************/ +/* Debug Registers */ +/******************************************/ + +#define MV64360_DUNIT_DEBUG_LOW 0x1460 +#define MV64360_DUNIT_DEBUG_HIGH 0x1464 +#define MV64360_DUNIT_MMASK 0X1b40 + +/****************************************/ +/* Device Parameters */ +/****************************************/ + +#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c +#define MV64360_DEVICE_BANK1_PARAMETERS 0x460 +#define MV64360_DEVICE_BANK2_PARAMETERS 0x464 +#define MV64360_DEVICE_BANK3_PARAMETERS 0x468 +#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c +#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0 +#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 +#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc +#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 + +/****************************************/ +/* Device interrupt registers */ +/****************************************/ + +#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0 +#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4 +#define MV64360_DEVICE_ERROR_ADDR 0x4d8 +#define MV64360_DEVICE_ERROR_DATA 0x4dc +#define MV64360_DEVICE_ERROR_PARITY 0x4e0 + +/****************************************/ +/* Device debug registers */ +/****************************************/ + +#define MV64360_DEVICE_DEBUG_LOW 0x4e4 +#define MV64360_DEVICE_DEBUG_HIGH 0x4e8 +#define MV64360_RUNIT_MMASK 0x4f0 + +/****************************************/ +/* PCI Slave Address Decoding registers */ +/****************************************/ + +#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08 +#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88 +#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08 +#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88 +#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c +#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c +#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c +#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c +#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10 +#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90 +#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10 +#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90 +#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18 +#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98 +#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14 +#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94 +#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 +#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 +#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c +#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c +#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 +#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 +#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24 +#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4 +#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28 +#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8 +#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 +#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 +#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c +#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c +#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c +#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc +#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 +#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 +#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 +#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 +#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c +#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc +#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c +#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc +#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 +#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 +#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 +#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 +#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C +#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C +#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 +#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 +#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 +#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 +#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 +#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 +#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 +#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 +#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 +#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 +#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 +#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 +#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c +#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc +#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 +#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 +#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 +#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 +#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 +#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 +#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c +#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec +#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 +#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 +#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 +#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 +#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 +#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 +#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 +#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 +#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c +#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc +#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 +#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 +#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44 +#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4 +#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48 +#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 + +/***********************************/ +/* PCI Control Register Map */ +/***********************************/ + +#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 +#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 +#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C +#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C +#define MV64360_PCI_0_COMMAND 0xc00 +#define MV64360_PCI_1_COMMAND 0xc80 +#define MV64360_PCI_0_MODE 0xd00 +#define MV64360_PCI_1_MODE 0xd80 +#define MV64360_PCI_0_RETRY 0xc04 +#define MV64360_PCI_1_RETRY 0xc84 +#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 +#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 +#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38 +#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8 +#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00 +#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80 +#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 +#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 +#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c +#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c +#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 +#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 +#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 +#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 +#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 +#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 +#define MV64360_PCI_0_P2P_CONFIG 0x1d14 +#define MV64360_PCI_1_P2P_CONFIG 0x1d94 + +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 +#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 +#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 + +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 +#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 +#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 + +/****************************************/ +/* PCI Configuration Access Registers */ +/****************************************/ + +#define MV64360_PCI_0_CONFIG_ADDR 0xcf8 +#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc +#define MV64360_PCI_1_CONFIG_ADDR 0xc78 +#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c +#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 +#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 + +/****************************************/ +/* PCI Error Report Registers */ +/****************************************/ + +#define MV64360_PCI_0_SERR_MASK 0xc28 +#define MV64360_PCI_1_SERR_MASK 0xca8 +#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40 +#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0 +#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44 +#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4 +#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48 +#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8 +#define MV64360_PCI_0_ERROR_COMMAND 0x1d50 +#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0 +#define MV64360_PCI_0_ERROR_CAUSE 0x1d58 +#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8 +#define MV64360_PCI_0_ERROR_MASK 0x1d5c +#define MV64360_PCI_1_ERROR_MASK 0x1ddc + +/****************************************/ +/* PCI Debug Registers */ +/****************************************/ + +#define MV64360_PCI_0_MMASK 0X1D24 +#define MV64360_PCI_1_MMASK 0X1DA4 + +/*********************************************/ +/* PCI Configuration, Function 0, Registers */ +/*********************************************/ + +#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000 +#define MV64360_PCI_STATUS_AND_COMMAND 0x004 +#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C + +#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010 +#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014 +#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018 +#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C +#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 +#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 +#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c +#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034 +#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C + /* capability list */ +#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define MV64360_PCI_VPD_ADDR 0x048 +#define MV64360_PCI_VPD_DATA 0x04c +#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050 +#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054 +#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 +#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c +#define MV64360_PCI_X_COMMAND 0x060 +#define MV64360_PCI_X_STATUS 0x064 +#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068 + +/***********************************************/ +/* PCI Configuration, Function 1, Registers */ +/***********************************************/ + +#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110 +#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114 +#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118 +#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c +#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 +#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 + +/***********************************************/ +/* PCI Configuration, Function 2, Registers */ +/***********************************************/ + +#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 +#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 +#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 +#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c +#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 +#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 3, Registers */ +/***********************************************/ + +#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 +#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 +#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 +#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c +#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220 +#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224 + +/***********************************************/ +/* PCI Configuration, Function 4, Registers */ +/***********************************************/ + +#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 +#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 +#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 +#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c +#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420 +#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 + +/****************************************/ +/* Messaging Unit Registers (I20) */ +/****************************************/ + +#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 +#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C +#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 +#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 +#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 +#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C +#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 +#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 +#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 +#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 +#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 +#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 +#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 +#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 +#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 +#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C +#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 +#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 +#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 +#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC + +#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 +#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C +#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 +#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 +#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 +#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC +#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 +#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 +#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 +#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 +#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 +#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 +#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 +#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 +#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 +#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC +#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 +#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 +#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 +#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C + +#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 +#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C +#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 +#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 +#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 +#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C +#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 +#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 +#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 +#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 +#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 +#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 +#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 +#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 +#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 +#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C +#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 +#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 +#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 +#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC +#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 +#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 +#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C +#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 +#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 +#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 +#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC +#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 +#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 +#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 +#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 +#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 +#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 +#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 +#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 +#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 +#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC +#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 +#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 +#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 +#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ + +#define MV64360_ETH_PHY_ADDR_REG 0x2000 +#define MV64360_ETH_SMI_REG 0x2004 +#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 +#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c +#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 +#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 +#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc +#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094 +#define MV64360_ETH_BAR_0 0x2200 +#define MV64360_ETH_BAR_1 0x2208 +#define MV64360_ETH_BAR_2 0x2210 +#define MV64360_ETH_BAR_3 0x2218 +#define MV64360_ETH_BAR_4 0x2220 +#define MV64360_ETH_BAR_5 0x2228 +#define MV64360_ETH_SIZE_REG_0 0x2204 +#define MV64360_ETH_SIZE_REG_1 0x220c +#define MV64360_ETH_SIZE_REG_2 0x2214 +#define MV64360_ETH_SIZE_REG_3 0x221c +#define MV64360_ETH_SIZE_REG_4 0x2224 +#define MV64360_ETH_SIZE_REG_5 0x222c +#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230 +#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 +#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 +#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 +#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 +#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c +#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290 +#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) +#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) +#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) +#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) +#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) +#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) +#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) +#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) +#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) +#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) +#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10)) +#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10)) +#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10)) +#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10)) +#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10)) +#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10)) +#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10)) +#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) +#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) +#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) +#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) +#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) +#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) +#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) +#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) +#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) +#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) +#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) +#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) +#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) +#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) +#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) +#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) +#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) +#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) +#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) +#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) +#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) +#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) +#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) +#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) +#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) +#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) +#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) +#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) +#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) + +/*******************************************/ +/* CUNIT Registers */ +/*******************************************/ + + /* Address Decoding Register Map */ + +#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200 +#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208 +#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210 +#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218 +#define MV64360_CUNIT_SIZE0 0xf204 +#define MV64360_CUNIT_SIZE1 0xf20c +#define MV64360_CUNIT_SIZE2 0xf214 +#define MV64360_CUNIT_SIZE3 0xf21c +#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 +#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 +#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 +#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254 +#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258 +#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C + + /* Error Report Registers */ + +#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310 +#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314 +#define MV64360_CUNIT_ERROR_ADDR 0xf318 + + /* Cunit Control Registers */ + +#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300 +#define MV64360_CUNIT_CONFIG_REG 0xb40c +#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 + + /* Cunit Debug Registers */ + +#define MV64360_CUNIT_DEBUG_LOW 0xf340 +#define MV64360_CUNIT_DEBUG_HIGH 0xf344 +#define MV64360_CUNIT_MMASK 0xf380 + + /* Cunit Base Address Enable Window Bits*/ +#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 +#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 +#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 +#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 + + /* MPSCs Clocks Routing Registers */ + +#define MV64360_MPSC_ROUTING_REG 0xb400 +#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404 +#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408 + + /* MPSCs Interrupts Registers */ + +#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) +#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3)) + +#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) +#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) +#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) +#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) + + /* MPSC0 Registers */ + + +/***************************************/ +/* SDMA Registers */ +/***************************************/ + +#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) +#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) +#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) +#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) +#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) + +#define MV64360_SDMA_CAUSE_REG 0xb800 +#define MV64360_SDMA_MASK_REG 0xb880 + + +/****************************************/ +/* SDMA Address Space Targets */ +/****************************************/ + +#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00 +#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00 +#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00 +#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700 + +#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01 +#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01 +#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01 +#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701 + +#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00 + +#define MV64360_SDMA_SRAM_TARGET 0x0003 +#define MV64360_SDMA_60X_BUS_TARGET 0x4003 + +#define MV64360_PCI_0_TARGET 0x0003 +#define MV64360_PCI_1_TARGET 0x0004 + + +/* Devices BAR and size registers */ + +#define MV64360_DEV_CS0_BASE_ADDR 0x028 +#define MV64360_DEV_CS0_SIZE 0x030 +#define MV64360_DEV_CS1_BASE_ADDR 0x228 +#define MV64360_DEV_CS1_SIZE 0x230 +#define MV64360_DEV_CS2_BASE_ADDR 0x248 +#define MV64360_DEV_CS2_SIZE 0x250 +#define MV64360_DEV_CS3_BASE_ADDR 0x038 +#define MV64360_DEV_CS3_SIZE 0x040 +#define MV64360_BOOTCS_BASE_ADDR 0x238 +#define MV64360_BOOTCS_SIZE 0x240 + +/* SDMA Window access protection */ +#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0 +#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1 +#define MV64360_SDMA_WIN_ACCESS_FULL 2 + +/* BRG Interrupts */ + +#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) +#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) +#define MV64360_BRG_CAUSE_REG 0xb834 +#define MV64360_BRG_MASK_REG 0xb8b4 + +/****************************************/ +/* DMA Channel Control */ +/****************************************/ + +#define MV64360_DMA_CHANNEL0_CONTROL 0x840 +#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880 +#define MV64360_DMA_CHANNEL1_CONTROL 0x844 +#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884 +#define MV64360_DMA_CHANNEL2_CONTROL 0x848 +#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888 +#define MV64360_DMA_CHANNEL3_CONTROL 0x84C +#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C + + +/****************************************/ +/* IDMA Registers */ +/****************************************/ + +#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800 +#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804 +#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808 +#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C +#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810 +#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814 +#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818 +#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c +#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820 +#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824 +#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828 +#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C +#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 +#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 +#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 +#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C +#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 +#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 +#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 +#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C + + /* IDMA Address Decoding Base Address Registers */ + +#define MV64360_DMA_BASE_ADDR_REG0 0xa00 +#define MV64360_DMA_BASE_ADDR_REG1 0xa08 +#define MV64360_DMA_BASE_ADDR_REG2 0xa10 +#define MV64360_DMA_BASE_ADDR_REG3 0xa18 +#define MV64360_DMA_BASE_ADDR_REG4 0xa20 +#define MV64360_DMA_BASE_ADDR_REG5 0xa28 +#define MV64360_DMA_BASE_ADDR_REG6 0xa30 +#define MV64360_DMA_BASE_ADDR_REG7 0xa38 + + /* IDMA Address Decoding Size Address Register */ + +#define MV64360_DMA_SIZE_REG0 0xa04 +#define MV64360_DMA_SIZE_REG1 0xa0c +#define MV64360_DMA_SIZE_REG2 0xa14 +#define MV64360_DMA_SIZE_REG3 0xa1c +#define MV64360_DMA_SIZE_REG4 0xa24 +#define MV64360_DMA_SIZE_REG5 0xa2c +#define MV64360_DMA_SIZE_REG6 0xa34 +#define MV64360_DMA_SIZE_REG7 0xa3C + + /* IDMA Address Decoding High Address Remap and Access + Protection Registers */ + +#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60 +#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64 +#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68 +#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C +#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80 +#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 +#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 +#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 +#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c +#define MV64360_DMA_ARBITER_CONTROL 0x860 +#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0 + + /* IDMA Headers Retarget Registers */ + +#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84 +#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88 + + /* IDMA Interrupt Register */ + +#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0 +#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4 +#define MV64360_DMA_ERROR_ADDR 0x8c8 +#define MV64360_DMA_ERROR_SELECT 0x8cc + + /* IDMA Debug Register ( for internal use ) */ + +#define MV64360_DMA_DEBUG_LOW 0x8e0 +#define MV64360_DMA_DEBUG_HIGH 0x8e4 +#define MV64360_DMA_SPARE 0xA8C + +/****************************************/ +/* Timer_Counter */ +/****************************************/ + +#define MV64360_TIMER_COUNTER0 0x850 +#define MV64360_TIMER_COUNTER1 0x854 +#define MV64360_TIMER_COUNTER2 0x858 +#define MV64360_TIMER_COUNTER3 0x85C +#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864 +#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 +#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c + +/****************************************/ +/* Watchdog registers */ +/****************************************/ + +#define MV64360_WATCHDOG_CONFIG_REG 0xb410 +#define MV64360_WATCHDOG_VALUE_REG 0xb414 + +/****************************************/ +/* I2C Registers */ +/****************************************/ + +#define MV64360_I2C_SLAVE_ADDR 0xc000 +#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010 +#define MV64360_I2C_DATA 0xc004 +#define MV64360_I2C_CONTROL 0xc008 +#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C +#define MV64360_I2C_SOFT_RESET 0xc01c + +/****************************************/ +/* GPP Interface Registers */ +/****************************************/ + +#define MV64360_GPP_IO_CONTROL 0xf100 +#define MV64360_GPP_LEVEL_CONTROL 0xf110 +#define MV64360_GPP_VALUE 0xf104 +#define MV64360_GPP_INTERRUPT_CAUSE 0xf108 +#define MV64360_GPP_INTERRUPT_MASK0 0xf10c +#define MV64360_GPP_INTERRUPT_MASK1 0xf114 +#define MV64360_GPP_VALUE_SET 0xf118 +#define MV64360_GPP_VALUE_CLEAR 0xf11c + +/****************************************/ +/* Interrupt Controller Registers */ +/****************************************/ + +/****************************************/ +/* Interrupts */ +/****************************************/ + +#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004 +#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c +#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014 +#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c +#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024 +#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034 +#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c +#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044 +#define MV64360_INTERRUPT0_MASK_0_LOW 0x054 +#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c +#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064 +#define MV64360_INTERRUPT1_MASK_0_LOW 0x074 +#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c +#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084 + +/****************************************/ +/* MPP Interface Registers */ +/****************************************/ + +#define MV64360_MPP_CONTROL0 0xf000 +#define MV64360_MPP_CONTROL1 0xf004 +#define MV64360_MPP_CONTROL2 0xf008 +#define MV64360_MPP_CONTROL3 0xf00c + +/****************************************/ +/* Serial Initialization registers */ +/****************************************/ + +#define MV64360_SERIAL_INIT_LAST_DATA 0xf324 +#define MV64360_SERIAL_INIT_CONTROL 0xf328 +#define MV64360_SERIAL_INIT_STATUS 0xf32c + + +#endif /* __INCgt64360rh */ diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c new file mode 100644 index 0000000..3e44fb9 --- /dev/null +++ b/board/esd/cpci750/pci.c @@ -0,0 +1,961 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* PCI.c - PCI functions */ + + +#include +#ifdef CONFIG_PCI +#include + +#ifdef CONFIG_PCI_PNP +void pciauto_config_init(struct pci_controller *hose); +int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar); +#endif + +#include "../../Marvell/include/pci.h" + +#undef DEBUG +#undef IDE_SET_NATIVE_MODE +static unsigned int local_buses[] = { 0, 0 }; + +static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { + {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, + {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, +}; + + +#ifdef DEBUG +static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; +static void gt_pci_bus_mode_display (PCI_HOST host) +{ + unsigned int mode; + + + mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; + switch (mode) { + case 0: + printf ("PCI %d bus mode: Conventional PCI\n", host); + break; + case 1: + printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + break; + case 2: + printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + break; + case 3: + printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + break; + default: + printf ("Unknown BUS %d\n", mode); + } +} +#endif + +static const unsigned int pci_p2p_configuration_reg[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION +}; + +static const unsigned int pci_configuration_address[] = { + PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS +}; + +static const unsigned int pci_configuration_data[] = { + PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, + PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER +}; + +static const unsigned int pci_error_cause_reg[] = { + PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE +}; + +static const unsigned int pci_arbiter_control[] = { + PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL +}; + +static const unsigned int pci_address_space_en[] = { + PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE +}; + +static const unsigned int pci_snoop_control_base_0_low[] = { + PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW +}; +static const unsigned int pci_snoop_control_top_0[] = { + PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 +}; + +static const unsigned int pci_access_control_base_0_low[] = { + PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW +}; +static const unsigned int pci_access_control_top_0[] = { + PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 +}; + +static const unsigned int pci_scs_bank_size[2][4] = { + {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, + PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, + {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, + PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} +}; + +static const unsigned int pci_p2p_configuration[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION +}; + + +/******************************************************************** +* pciWriteConfigReg - Write to a PCI configuration register +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* +* +* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum, unsigned int data) +{ + volatile unsigned int DataForAddrReg; + unsigned int functionNum; + unsigned int busNum = 0; + unsigned int addr; + + if (pciDevNum > 32) /* illegal device Number */ + return; + if (pciDevNum == SELF) { /* configure our configuration space. */ + pciDevNum = + (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & + 0x1f; + busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & + 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = + (regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); + GT_REG_READ (pci_configuration_address[host], &addr); + if (addr != DataForAddrReg) + return; + GT_REG_WRITE (pci_configuration_data[host], data); +} + +/******************************************************************** +* pciReadConfigReg - Read from a PCI0 configuration register +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec) +* pciDevNum: The device number needs to be addressed. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum) +{ + volatile unsigned int DataForAddrReg; + unsigned int data; + unsigned int functionNum; + unsigned int busNum = 0; + + if (pciDevNum > 32) /* illegal device Number */ + return 0xffffffff; + if (pciDevNum == SELF) { /* configure our configuration space. */ + pciDevNum = + (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & + 0x1f; + busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & + 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = + (regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); + GT_REG_READ (pci_configuration_address[host], &data); + if (data != DataForAddrReg) + return 0xffffffff; + GT_REG_READ (pci_configuration_data[host], &data); + return data; +} + +/******************************************************************** +* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. +* +* Inputs: unsigned int regOffset - The register offset as it apears in the +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +* The configuration Address is configure as type-I (bits[1:0] = '01') due to +* PCI spec referring to P2P. +* +*********************************************************************/ +void pciOverBridgeWriteConfigReg (PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum, unsigned int data) +{ + unsigned int DataForReg; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if (pciDevNum == SELF) { /* This board */ + DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; + } else { + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | + BIT31 | BIT0; + } + GT_REG_WRITE (pci_configuration_address[host], DataForReg); + GT_REG_WRITE (pci_configuration_data[host], data); +} + + +/******************************************************************** +* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum) +{ + unsigned int DataForReg; + unsigned int data; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if (pciDevNum == SELF) { /* This board */ + DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; + } else { /* agent on another bus */ + + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | + BIT0 | BIT31; + } + GT_REG_WRITE (pci_configuration_address[host], DataForReg); + GT_REG_READ (pci_configuration_data[host], &data); + return data; +} + + +/******************************************************************** +* pciGetRegOffset - Gets the register offset for this region config. +* +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI register base address +*********************************************************************/ +static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) +{ + switch (host) { + case PCI_HOST0: + switch (region) { + case PCI_IO: + return PCI_0I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: + return PCI_0MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: + return PCI_0MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: + return PCI_0MEMORY3_LOW_DECODE_ADDRESS; + } + case PCI_HOST1: + switch (region) { + case PCI_IO: + return PCI_1I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: + return PCI_1MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: + return PCI_1MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: + return PCI_1MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: + return PCI_1MEMORY3_LOW_DECODE_ADDRESS; + } + } + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; +} + +static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) +{ + switch (host) { + case PCI_HOST0: + switch (region) { + case PCI_IO: + return PCI_0I_O_ADDRESS_REMAP; + case PCI_REGION0: + return PCI_0MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: + return PCI_0MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: + return PCI_0MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: + return PCI_0MEMORY3_ADDRESS_REMAP; + } + case PCI_HOST1: + switch (region) { + case PCI_IO: + return PCI_1I_O_ADDRESS_REMAP; + case PCI_REGION0: + return PCI_1MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: + return PCI_1MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: + return PCI_1MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: + return PCI_1MEMORY3_ADDRESS_REMAP; + } + } + return PCI_0MEMORY0_ADDRESS_REMAP; +} + +/******************************************************************** +* pciGetBaseAddress - Gets the base address of a PCI. +* - If the PCI size is 0 then this base address has no meaning!!! +* +* +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI base address. +*********************************************************************/ +unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) +{ + unsigned int regBase; + unsigned int regEnd; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, ®Base); + GT_REG_READ (regOffset + 8, ®End); + + if (regEnd <= regBase) + return 0xffffffff; /* ERROR !!! */ + + regBase = regBase << 16; + return regBase; +} + +bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, + unsigned int bankBase, unsigned int bankLength) +{ + unsigned int low = 0xfff; + unsigned int high = 0x0; + unsigned int regOffset = pciGetRegOffset (host, region); + unsigned int remapOffset = pciGetRemapOffset (host, region); + + if (bankLength != 0) { + low = (bankBase >> 16) & 0xffff; + high = ((bankBase + bankLength) >> 16) - 1; + } + + GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ + GT_REG_WRITE (regOffset + 8, high); + + if (bankLength != 0) { /* must do AFTER writing maps */ + GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. + dont support upper 32 + in this driver */ + } + return true; +} + +unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) +{ + unsigned int low; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, &low); + return (low & 0xffff) << 16; +} + +unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) +{ + unsigned int low, high; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, &low); + GT_REG_READ (regOffset + 8, &high); + return ((high & 0xffff) + 1) << 16; +} + + +/* ronen - 7/Dec/03*/ +/******************************************************************** +* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. +* Inputs: one of the PCI BAR +*********************************************************************/ +void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) +{ + RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); +} + +void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) +{ + SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); +} + +/******************************************************************** +* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. +* +* Inputs: base and size of PCI SCS +*********************************************************************/ +void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, + unsigned int pciDramBase, unsigned int pciDramSize) +{ + /*ronen different function for 3rd bank. */ + unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; + + pciDramBase = pciDramBase & 0xfffff000; + pciDramBase = pciDramBase | (pciReadConfigReg (host, + PCI_SCS_0_BASE_ADDRESS + + offset, + SELF) & 0x00000fff); + pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, + pciDramBase); + if (pciDramSize == 0) + pciDramSize++; + GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); + gtPciEnableInternalBAR (host, bank); +} + +/******************************************************************** +* pciSetRegionFeatures - This function modifys one of the 8 regions with +* feature bits given as an input. +* - Be advised to check the spec before modifying them. +* Inputs: PCI_PROTECT_REGION region - one of the eight regions. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. +* Returns: false if one of the parameters is erroneous true otherwise. +*********************************************************************/ +bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, + unsigned int features, unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int accessLow; + unsigned int accessHigh; + unsigned int accessTop = baseAddress + regionLength; + + if (regionLength == 0) { /* close the region. */ + pciDisableAccessRegion (host, region); + return true; + } + /* base Address is store is bits [11:0] */ + accessLow = (baseAddress & 0xfff00000) >> 20; + /* All the features are update according to the defines in pci.h (to be on + the safe side we disable bits: [11:0] */ + accessLow = accessLow | (features & 0xfffff000); + /* write to the Low Access Region register */ + GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, + accessLow); + + accessHigh = (accessTop & 0xfff00000) >> 20; + + /* write to the High Access Region register */ + GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, + accessHigh - 1); + return true; +} + +/******************************************************************** +* pciDisableAccessRegion - Disable The given Region by writing MAX size +* to its low Address and MIN size to its high Address. +* +* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. +* Returns: N/A. +*********************************************************************/ +void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) +{ + /* writing back the registers default values. */ + GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, + 0x01001fff); + GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); +} + +/******************************************************************** +* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true. +*********************************************************************/ +bool pciArbiterEnable (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); + return true; +} + +/******************************************************************** +* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true +*********************************************************************/ +bool pciArbiterDisable (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); + return true; +} + +/******************************************************************** +* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) +* +* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. +* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. +* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. +* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. +* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. +* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. +* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. +* Returns: true +*********************************************************************/ +bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, + PCI_AGENT_PRIO externalAgent0, + PCI_AGENT_PRIO externalAgent1, + PCI_AGENT_PRIO externalAgent2, + PCI_AGENT_PRIO externalAgent3, + PCI_AGENT_PRIO externalAgent4, + PCI_AGENT_PRIO externalAgent5) +{ + unsigned int regData; + unsigned int writeData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + writeData = (internalAgent << 7) + (externalAgent0 << 8) + + (externalAgent1 << 9) + (externalAgent2 << 10) + + (externalAgent3 << 11) + (externalAgent4 << 12) + + (externalAgent5 << 13); + regData = (regData & 0xffffc07f) | writeData; + GT_REG_WRITE (pci_arbiter_control[host], regData & regData); + return true; +} + +/******************************************************************** +* pciParkingDisable - Park on last option disable, with this function you can +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. +* +* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* Returns: true +*********************************************************************/ +bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, + PCI_AGENT_PARK externalAgent0, + PCI_AGENT_PARK externalAgent1, + PCI_AGENT_PARK externalAgent2, + PCI_AGENT_PARK externalAgent3, + PCI_AGENT_PARK externalAgent4, + PCI_AGENT_PARK externalAgent5) +{ + unsigned int regData; + unsigned int writeData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + writeData = (internalAgent << 14) + (externalAgent0 << 15) + + (externalAgent1 << 16) + (externalAgent2 << 17) + + (externalAgent3 << 18) + (externalAgent4 << 19) + + (externalAgent5 << 20); + regData = (regData & ~(0x7f << 14)) | writeData; + GT_REG_WRITE (pci_arbiter_control[host], regData); + return true; +} + +/******************************************************************** +* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to +* respond to grant assertion within a window specified in +* the input value: 'brokenValue'. +* +* Inputs: unsigned char brokenValue - A value which limits the Master to hold the +* grant without asserting frame. +* Returns: Error for illegal broken value otherwise true. +*********************************************************************/ +bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) +{ + unsigned int data; + unsigned int regData; + + if (brokenValue > 0xf) + return false; /* brokenValue must be 4 bit */ + data = brokenValue << 3; + GT_REG_READ (pci_arbiter_control[host], ®Data); + regData = (regData & 0xffffff87) | data; + GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); + return true; +} + +/******************************************************************** +* pciDisableBrokenAgentDetection - This function disable the Broken agent +* Detection mechanism. +* NOTE: This operation may cause a dead lock on the +* pci0 arbitration. +* +* Inputs: N/A +* Returns: true. +*********************************************************************/ +bool pciDisableBrokenAgentDetection (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + regData = regData & 0xfffffffd; + GT_REG_WRITE (pci_arbiter_control[host], regData); + return true; +} + +/******************************************************************** +* pciP2PConfig - This function set the PCI_n P2P configurate. +* For more information on the P2P read PCI spec. +* +* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. +* +* Returns: true. +*********************************************************************/ +bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, + unsigned int SecondBusHigh, + unsigned int busNum, unsigned int devNum) +{ + unsigned int regData; + + regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | + ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); + GT_REG_WRITE (pci_p2p_configuration[host], regData); + return true; +} + +/******************************************************************** +* pciSetRegionSnoopMode - This function modifys one of the 4 regions which +* supports Cache Coherency in the PCI_n interface. +* Inputs: region - One of the four regions. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. +* Returns: false if one of the parameters is wrong otherwise return true. +*********************************************************************/ +bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, + PCI_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int snoopXbaseAddress; + unsigned int snoopXtopAddress; + unsigned int data; + unsigned int snoopHigh = baseAddress + regionLength; + + if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) + return false; + snoopXbaseAddress = + pci_snoop_control_base_0_low[host] + 0x10 * region; + snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; + if (regionLength == 0) { /* closing the region */ + GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); + GT_REG_WRITE (snoopXtopAddress, 0); + return true; + } + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + data = (baseAddress >> 20) | snoopType << 12; + GT_REG_WRITE (snoopXbaseAddress, data); + snoopHigh = (snoopHigh & 0xfff00000) >> 20; + GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); + return true; +} + +static int gt_read_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 * value) +{ + int bus = PCI_BUS (dev); + + if ((bus == local_buses[0]) || (bus == local_buses[1])) { + *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, + PCI_DEV (dev)); + } else { + *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> + cfg_addr, offset, + PCI_DEV (dev), bus); + } + + return 0; +} + +static int gt_write_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + int bus = PCI_BUS (dev); + + if ((bus == local_buses[0]) || (bus == local_buses[1])) { + pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, + PCI_DEV (dev), value); + } else { + pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, + offset, PCI_DEV (dev), bus, + value); + } + return 0; +} + + +static void gt_setup_ide (struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; + u32 bar_response, bar_value; + int bar; + + for (bar = 0; bar < 6; bar++) { + /*ronen different function for 3rd bank. */ + unsigned int offset = + (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; + + pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, + 0x0); + pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, + &bar_response); + + pciauto_region_allocate (bar_response & + PCI_BASE_ADDRESS_SPACE_IO ? hose-> + pci_io : hose->pci_mem, ide_bar[bar], + &bar_value); + + pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, + bar_value); + } +} + + +/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ +/* and is curently not called *. */ +#if 0 +static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char pin, irq; + + pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); + + if (pin == 1) { /* only allow INT A */ + irq = pci_irq_swizzle[(PCI_HOST) hose-> + cfg_addr][PCI_DEV (dev)]; + if (irq) + pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); + } +} +#endif + +struct pci_config_table gt_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, + + {} +}; + +struct pci_controller pci0_hose = { +/* fixup_irq: gt_fixup_irq, */ + config_table:gt_config_table, +}; + +struct pci_controller pci1_hose = { +/* fixup_irq: gt_fixup_irq, */ + config_table:gt_config_table, +}; + +void pci_init_board (void) +{ + unsigned int command; +#ifdef CONFIG_PCI_PNP + unsigned int bar; +#endif + +#ifdef DEBUG + gt_pci_bus_mode_display (PCI_HOST0); +#endif + + pci0_hose.first_busno = 0; + pci0_hose.last_busno = 0xff; + local_buses[0] = pci0_hose.first_busno; + + /* PCI memory space */ + pci_set_region (pci0_hose.regions + 0, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (pci0_hose.regions + 1, + CFG_PCI0_IO_SPACE_PCI, + CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + + pci_set_ops (&pci0_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + pci0_hose.region_count = 2; + + pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; + + pci_register_hose (&pci0_hose); + pciArbiterEnable (PCI_HOST0); + pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + +#ifdef CONFIG_PCI_PNP + pciauto_config_init(&pci0_hose); + pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar); +#endif +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno); + +#ifdef DEBUG + gt_pci_bus_mode_display (PCI_HOST1); +#endif + pci1_hose.first_busno = pci0_hose.last_busno + 1; + pci1_hose.last_busno = 0xff; + pci1_hose.current_busno = pci1_hose.first_busno; + local_buses[1] = pci1_hose.first_busno; + + /* PCI memory space */ + pci_set_region (pci1_hose.regions + 0, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (pci1_hose.regions + 1, + CFG_PCI1_IO_SPACE_PCI, + CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + + pci_set_ops (&pci1_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + + pci1_hose.region_count = 2; + + pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; + + pci_register_hose (&pci1_hose); + + pciArbiterEnable (PCI_HOST1); + pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); + + command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); + +#ifdef CONFIG_PCI_PNP + pciauto_config_init(&pci1_hose); + pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar); +#endif + pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno); + + command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); + +} +#endif /* of CONFIG_PCI */ diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c new file mode 100644 index 0000000..db545ef --- /dev/null +++ b/board/esd/cpci750/sdram_init.c @@ -0,0 +1,1683 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * adaption for the Marvell DB64360 Board + * Ingo Assmus (ingo.assmus@keymile.com) + * + * adaption for the cpci750 Board + * Reinhard Arlt (reinhard.arlt@esd-electronics.com) + *************************************************************************/ + + +/* sdram_init.c - automatic memory sizing */ + +#include +#include <74xx_7xx.h> +#include "../../Marvell/include/memory.h" +#include "../../Marvell/include/pci.h" +#include "../../Marvell/include/mv_gen_reg.h" +#include + +#include "eth.h" +#include "mpsc.h" +#include "../../Marvell/common/i2c.h" +#include "64360.h" +#include "mv_regs.h" + + +#undef DEBUG +/* #define DEBUG */ +#ifdef CONFIG_PCI +#define MAP_PCI +#endif /* of CONFIG_PCI */ + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +int set_dfcdlInit(void); /* setup delay line of Mv64360 */ + +/* ------------------------------------------------------------------------- */ + +int +memory_map_bank(unsigned int bankNo, + unsigned int bankBase, + unsigned int bankLength) +{ +#ifdef MAP_PCI + PCI_HOST host; +#endif + + +#ifdef DEBUG + if (bankLength > 0) { + printf("mapping bank %d at %08x - %08x\n", + bankNo, bankBase, bankBase + bankLength - 1); + } else { + printf("unmapping bank %d\n", bankNo); + } +#endif + + memoryMapBank(bankNo, bankBase, bankLength); + +#ifdef MAP_PCI + for (host=PCI_HOST0;host<=PCI_HOST1;host++) { + const int features= + PREFETCH_ENABLE | + DELAYED_READ_ENABLE | + AGGRESSIVE_PREFETCH | + READ_LINE_AGGRESSIVE_PREFETCH | + READ_MULTI_AGGRESSIVE_PREFETCH | + MAX_BURST_4 | + PCI_NO_SWAP; + + pciMapMemoryBank(host, bankNo, bankBase, bankLength); + + pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase, + bankLength); + + pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength); + } +#endif + return 0; +} + +#define GB (1 << 30) + +/* much of this code is based on (or is) the code in the pip405 port */ +/* thanks go to the authors of said port - Josh */ + +/* structure to store the relevant information about an sdram bank */ +typedef struct sdram_info { + uchar drb_size; + uchar registered, ecc; + uchar tpar; + uchar tras_clocks; + uchar burst_len; + uchar banks, slot; +} sdram_info_t; + +/* Typedefs for 'gtAuxilGetDIMMinfo' function */ + +typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE; + +typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, + SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, + } VOLTAGE_INTERFACE; + +typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR; +typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD; + + +/* SDRAM/DDR information struct */ +typedef struct _gtMemoryDimmInfo +{ + MEMORY_TYPE memoryType; + unsigned int numOfRowAddresses; + unsigned int numOfColAddresses; + unsigned int numOfModuleBanks; + unsigned int dataWidth; + VOLTAGE_INTERFACE voltageInterface; + unsigned int errorCheckType; /* ECC , PARITY..*/ + unsigned int sdramWidth; /* 4,8,16 or 32 */; + unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ + unsigned int minClkDelay; + unsigned int burstLengthSupported; + unsigned int numOfBanksOnEachDevice; + unsigned int suportedCasLatencies; + unsigned int RefreshInterval; + unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ + unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns)*/ + MAX_CL_SUPPORTED_DDR maxClSupported_DDR; + MAX_CL_SUPPORTED_SD maxClSupported_SD; + unsigned int moduleBankDensity; + /* module attributes (true for yes) */ + bool bufferedAddrAndControlInputs; + bool registeredAddrAndControlInputs; + bool onCardPLL; + bool bufferedDQMBinputs; + bool registeredDQMBinputs; + bool differentialClockInput; + bool redundantRowAddressing; + + /* module general attributes */ + bool suportedAutoPreCharge; + bool suportedPreChargeAll; + bool suportedEarlyRasPreCharge; + bool suportedWrite1ReadBurst; + bool suported5PercentLowVCC; + bool suported5PercentUpperVCC; + /* module timing parameters */ + unsigned int minRasToCasDelay; + unsigned int minRowActiveRowActiveDelay; + unsigned int minRasPulseWidth; + unsigned int minRowPrechargeTime; /* measured in ns */ + + int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ + int addrAndCommandSetupTime; /* (measured in ns/100) */ + int dataInputSetupTime; /* LoP left of point (measured in ns) */ + int dataInputHoldTime; /* LoP left of point (measured in ns) */ +/* tAC times for highest 2nd and 3rd highest CAS Latency values */ + unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns)*/ + unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns)*/ + unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns)*/ + + unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns)*/ + + unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns)*/ + + unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns)*/ + + /* Parameters calculated from + the extracted DIMM information */ + unsigned int size; + unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ + unsigned int numberOfDevices; + uchar drb_size; /* DRAM size in n*64Mbit */ + uchar slot; /* Slot Number this module is inserted in */ + uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ +#ifdef DEBUG + uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ + uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ + uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ + unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ + unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ + unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ + uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ + +#endif +} AUX_MEM_DIMM_INFO; + + +/* + * translate ns.ns/10 coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short +NS10to10PS(unsigned char spd_byte) +{ + unsigned short ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + return(ns*100 + ns10*10); +} + +/* + * translate ns coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short +NSto10PS(unsigned char spd_byte) +{ + return(spd_byte*100); +} + +/* This code reads the SPD chip on the sdram and populates + * the array which is passed in with the relevant information */ +/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ +static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long spd_checksum; + + uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; + int ret; + unsigned int i, j, density = 1, devicesForErrCheck = 0; + +#ifdef DEBUG + unsigned int k; +#endif + unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; + int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; + uchar supp_cal, cal_val; + ulong memclk, tmemclk; + ulong tmp; + uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar data[128]; + + memclk = gd->bus_clk; + tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ + + memset (data, 0, sizeof (data)); + + + ret = 0; + + DP (puts ("before i2c read\n")); + + ret = i2c_read (addr, 0, 2, data, 128); + + DP (puts ("after i2c read\n")); + + if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd') + || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm') + || (data[70] != 'b') || (data[71] != 'h')) { + ret = -1; + } + + if ((ret != 0) && (slot == 0)) { + memset (data, 0, sizeof (data)); + data[0] = 0x80; + data[1] = 0x08; + data[2] = 0x07; + data[3] = 0x0c; + data[4] = 0x09; + data[5] = 0x01; + data[6] = 0x48; + data[7] = 0x00; + data[8] = 0x04; + data[9] = 0x75; + data[10] = 0x80; + data[11] = 0x02; + data[12] = 0x80; + data[13] = 0x10; + data[14] = 0x08; + data[15] = 0x01; + data[16] = 0x0e; + data[17] = 0x04; + data[18] = 0x0c; + data[19] = 0x01; + data[20] = 0x02; + data[21] = 0x20; + data[22] = 0x00; + data[23] = 0xa0; + data[24] = 0x80; + data[25] = 0x00; + data[26] = 0x00; + data[27] = 0x50; + data[28] = 0x3c; + data[29] = 0x50; + data[30] = 0x32; + data[31] = 0x10; + data[32] = 0xb0; + data[33] = 0xb0; + data[34] = 0x60; + data[35] = 0x60; + data[64] = 'e'; + data[65] = 's'; + data[66] = 'd'; + data[67] = '-'; + data[68] = 'g'; + data[69] = 'm'; + data[70] = 'b'; + data[71] = 'h'; + ret = 0; + } + + /* zero all the values */ + memset (dimmInfo, 0, sizeof (*dimmInfo)); + + /* copy the SPD content 1:1 into the dimmInfo structure */ + for (i = 0; i <= 127; i++) { + dimmInfo->spd_raw_data[i] = data[i]; + } + + if (ret) { + DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + return 0; + } else + dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ + +#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT + + for (i = 0; i <= 127; i++) { + printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], + data[i]); + } + +#endif +#ifdef DEBUG + /* find Manufacturer of Dimm Module */ + for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { + dimmInfo->manufactura[i] = data[64 + i]; + } + printf ("\nThis RAM-Module is produced by: %s\n", + dimmInfo->manufactura); + + /* find Manul-ID of Dimm Module */ + for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { + dimmInfo->modul_id[i] = data[73 + i]; + } + printf ("The Module-ID of this RAM-Module is: %s\n", + dimmInfo->modul_id); + + /* find Vendor-Data of Dimm Module */ + for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { + dimmInfo->vendor_data[i] = data[99 + i]; + } + printf ("Vendor Data of this RAM-Module is: %s\n", + dimmInfo->vendor_data); + + /* find modul_serial_no of Dimm Module */ + dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); + printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", + dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); + + /* find Manufac-Data of Dimm Module */ + dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); + printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ + + /* find modul_revision of Dimm Module */ + dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); + printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ + + /* find manufac_place of Dimm Module */ + dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); + printf ("manufac_place of this RAM-Module is: %d\n", + dimmInfo->manufac_place); + +#endif +/*------------------------------------------------------------------------------------------------------------------------------*/ +/* calculate SPD checksum */ +/*------------------------------------------------------------------------------------------------------------------------------*/ + spd_checksum = 0; +#if 0 /* test-only */ + for (i = 0; i <= 62; i++) { + spd_checksum += data[i]; + } + + if ((spd_checksum & 0xff) != data[63]) { + printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); + hang (); + } + + else + printf ("SPD Checksum ok!\n"); +#endif /* test-only */ + +/*------------------------------------------------------------------------------------------------------------------------------*/ + for (i = 2; i <= 35; i++) { + switch (i) { + case 2: /* Memory type (DDR / SDRAM) */ + dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; +#ifdef DEBUG + if (dimmInfo->memoryType == 0) + DP (printf + ("Dram_type in slot %d is: SDRAM\n", + dimmInfo->slot)); + if (dimmInfo->memoryType == 1) + DP (printf + ("Dram_type in slot %d is: DDRAM\n", + dimmInfo->slot)); +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 3: /* Number Of Row Addresses */ + dimmInfo->numOfRowAddresses = data[i]; + DP (printf + ("Module Number of row addresses: %d\n", + dimmInfo->numOfRowAddresses)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 4: /* Number Of Column Addresses */ + dimmInfo->numOfColAddresses = data[i]; + DP (printf + ("Module Number of col addresses: %d\n", + dimmInfo->numOfColAddresses)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 5: /* Number Of Module Banks */ + dimmInfo->numOfModuleBanks = data[i]; + DP (printf + ("Number of Banks on Mod. : %d\n", + dimmInfo->numOfModuleBanks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 6: /* Data Width */ + dimmInfo->dataWidth = data[i]; + DP (printf + ("Module Data Width: %d\n", + dimmInfo->dataWidth)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 8: /* Voltage Interface */ + switch (data[i]) { + case 0x0: + dimmInfo->voltageInterface = TTL_5V_TOLERANT; + DP (printf + ("Module is TTL_5V_TOLERANT\n")); + break; + case 0x1: + dimmInfo->voltageInterface = LVTTL; + DP (printf + ("Module is LVTTL\n")); + break; + case 0x2: + dimmInfo->voltageInterface = HSTL_1_5V; + DP (printf + ("Module is TTL_5V_TOLERANT\n")); + break; + case 0x3: + dimmInfo->voltageInterface = SSTL_3_3V; + DP (printf + ("Module is HSTL_1_5V\n")); + break; + case 0x4: + dimmInfo->voltageInterface = SSTL_2_5V; + DP (printf + ("Module is SSTL_2_5V\n")); + break; + default: + dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; + DP (printf + ("Module is VOLTAGE_UNKNOWN\n")); + break; + } + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 9: /* Minimum Cycle Time At Max CasLatancy */ + shift = (dimmInfo->memoryType == DDR) ? 4 : 2; + mult = (dimmInfo->memoryType == DDR) ? 10 : 25; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf : 0x03; + leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; + rightOfPoint = (data[i] & maskRightOfPoint) * mult; + dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = + leftOfPoint; + dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = + rightOfPoint; + DP (printf + ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", + leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 10: /* Clock To Data Out */ + div = (dimmInfo->memoryType == DDR) ? 100 : 10; + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + dimmInfo->clockToDataOut_LoP = leftOfPoint; + dimmInfo->clockToDataOut_RoP = rightOfPoint; + DP (printf + ("Clock To Data Out: %d.%2d [ns]\n", + leftOfPoint, rightOfPoint)); + /*dimmInfo->clockToDataOut */ + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + +#ifdef CONFIG_ECC + case 11: /* Error Check Type */ + dimmInfo->errorCheckType = data[i]; + DP (printf + ("Error Check Type (0=NONE): %d\n", + dimmInfo->errorCheckType)); + break; +#endif +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 12: /* Refresh Interval */ + dimmInfo->RefreshInterval = data[i]; + DP (printf + ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", + dimmInfo->RefreshInterval)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 13: /* Sdram Width */ + dimmInfo->sdramWidth = data[i]; + DP (printf + ("Sdram Width: %d\n", + dimmInfo->sdramWidth)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 14: /* Error Check Data Width */ + dimmInfo->errorCheckDataWidth = data[i]; + DP (printf + ("Error Check Data Width: %d\n", + dimmInfo->errorCheckDataWidth)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 15: /* Minimum Clock Delay */ + dimmInfo->minClkDelay = data[i]; + DP (printf + ("Minimum Clock Delay: %d\n", + dimmInfo->minClkDelay)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 16: /* Burst Length Supported */ + /******-******-******-******* + * bit3 | bit2 | bit1 | bit0 * + *******-******-******-******* + burst length = * 8 | 4 | 2 | 1 * + ***************************** + + If for example bit0 and bit2 are set, the burst + length supported are 1 and 4. */ + + dimmInfo->burstLengthSupported = data[i]; +#ifdef DEBUG + DP (printf + ("Burst Length Supported: ")); + if (dimmInfo->burstLengthSupported & 0x01) + DP (printf ("1, ")); + if (dimmInfo->burstLengthSupported & 0x02) + DP (printf ("2, ")); + if (dimmInfo->burstLengthSupported & 0x04) + DP (printf ("4, ")); + if (dimmInfo->burstLengthSupported & 0x08) + DP (printf ("8, ")); + DP (printf (" Bit \n")); +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 17: /* Number Of Banks On Each Device */ + dimmInfo->numOfBanksOnEachDevice = data[i]; + DP (printf + ("Number Of Banks On Each Chip: %d\n", + dimmInfo->numOfBanksOnEachDevice)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 18: /* Suported Cas Latencies */ + + /* DDR: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + ********************************************************* + SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + dimmInfo->suportedCasLatencies = data[i]; +#ifdef DEBUG + DP (printf + ("Suported Cas Latencies: (CL) ")); + if (dimmInfo->memoryType == 0) { /* SDRAM */ + for (k = 0; k <= 7; k++) { + if (dimmInfo-> + suportedCasLatencies & (1 << k)) + DP (printf + ("%d, ", + k + 1)); + } + + } else { /* DDR-RAM */ + + if (dimmInfo->suportedCasLatencies & 1) + DP (printf ("1, ")); + if (dimmInfo->suportedCasLatencies & 2) + DP (printf ("1.5, ")); + if (dimmInfo->suportedCasLatencies & 4) + DP (printf ("2, ")); + if (dimmInfo->suportedCasLatencies & 8) + DP (printf ("2.5, ")); + if (dimmInfo->suportedCasLatencies & 16) + DP (printf ("3, ")); + if (dimmInfo->suportedCasLatencies & 32) + DP (printf ("3.5, ")); + + } + DP (printf ("\n")); +#endif + /* Calculating MAX CAS latency */ + for (j = 7; j > 0; j--) { + if (((dimmInfo-> + suportedCasLatencies >> j) & 0x1) == + 1) { + switch (dimmInfo->memoryType) { + case DDR: + /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ + switch (j) { + case 7: + DP (printf + ("Max. Cas Latencies (DDR): ERROR !!!\n")); + dimmInfo-> + maxClSupported_DDR + = + DDR_CL_FAULT; + hang (); + break; + case 6: + DP (printf + ("Max. Cas Latencies (DDR): ERROR !!!\n")); + dimmInfo-> + maxClSupported_DDR + = + DDR_CL_FAULT; + hang (); + break; + case 5: + DP (printf + ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_3_5; + break; + case 4: + DP (printf + ("Max. Cas Latencies (DDR): 3 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_3; + break; + case 3: + DP (printf + ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_2_5; + break; + case 2: + DP (printf + ("Max. Cas Latencies (DDR): 2 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_2; + break; + case 1: + DP (printf + ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + dimmInfo-> + maxClSupported_DDR + = DDR_CL_1_5; + break; + } + dimmInfo-> + maxCASlatencySupported_LoP + = + 1 + + (int) (5 * j / 10); + if (((5 * j) % 10) != 0) + dimmInfo-> + maxCASlatencySupported_RoP + = 5; + else + dimmInfo-> + maxCASlatencySupported_RoP + = 0; + DP (printf + ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + dimmInfo-> + maxCASlatencySupported_LoP, + dimmInfo-> + maxCASlatencySupported_RoP)); + break; + case SDRAM: + /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ + dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ + DP (printf + ("Max. Cas Latencies (SD): %d\n", + dimmInfo-> + maxClSupported_SD)); + dimmInfo-> + maxCASlatencySupported_LoP + = j; + dimmInfo-> + maxCASlatencySupported_RoP + = 0; + DP (printf + ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + dimmInfo-> + maxCASlatencySupported_LoP, + dimmInfo-> + maxCASlatencySupported_RoP)); + break; + } + break; + } + } + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 21: /* Buffered Address And Control Inputs */ + DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + dimmInfo->bufferedAddrAndControlInputs = + data[i] & BIT0; + dimmInfo->registeredAddrAndControlInputs = + (data[i] & BIT1) >> 1; + dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; + dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; + dimmInfo->registeredDQMBinputs = + (data[i] & BIT4) >> 4; + dimmInfo->differentialClockInput = + (data[i] & BIT5) >> 5; + dimmInfo->redundantRowAddressing = + (data[i] & BIT6) >> 6; +#ifdef DEBUG + if (dimmInfo->bufferedAddrAndControlInputs == 1) + DP (printf + (" - Buffered Address/Control Input: Yes \n")); + else + DP (printf + (" - Buffered Address/Control Input: No \n")); + + if (dimmInfo->registeredAddrAndControlInputs == 1) + DP (printf + (" - Registered Address/Control Input: Yes \n")); + else + DP (printf + (" - Registered Address/Control Input: No \n")); + + if (dimmInfo->onCardPLL == 1) + DP (printf + (" - On-Card PLL (clock): Yes \n")); + else + DP (printf + (" - On-Card PLL (clock): No \n")); + + if (dimmInfo->bufferedDQMBinputs == 1) + DP (printf + (" - Bufferd DQMB Inputs: Yes \n")); + else + DP (printf + (" - Bufferd DQMB Inputs: No \n")); + + if (dimmInfo->registeredDQMBinputs == 1) + DP (printf + (" - Registered DQMB Inputs: Yes \n")); + else + DP (printf + (" - Registered DQMB Inputs: No \n")); + + if (dimmInfo->differentialClockInput == 1) + DP (printf + (" - Differential Clock Input: Yes \n")); + else + DP (printf + (" - Differential Clock Input: No \n")); + + if (dimmInfo->redundantRowAddressing == 1) + DP (printf + (" - redundant Row Addressing: Yes \n")); + else + DP (printf + (" - redundant Row Addressing: No \n")); + +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 22: /* Suported AutoPreCharge */ + DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; + dimmInfo->suportedAutoPreCharge = + (data[i] & BIT1) >> 1; + dimmInfo->suportedPreChargeAll = + (data[i] & BIT2) >> 2; + dimmInfo->suportedWrite1ReadBurst = + (data[i] & BIT3) >> 3; + dimmInfo->suported5PercentLowVCC = + (data[i] & BIT4) >> 4; + dimmInfo->suported5PercentUpperVCC = + (data[i] & BIT5) >> 5; +#ifdef DEBUG + if (dimmInfo->suportedEarlyRasPreCharge == 1) + DP (printf + (" - Early Ras Precharge: Yes \n")); + else + DP (printf + (" - Early Ras Precharge: No \n")); + + if (dimmInfo->suportedAutoPreCharge == 1) + DP (printf + (" - AutoPreCharge: Yes \n")); + else + DP (printf + (" - AutoPreCharge: No \n")); + + if (dimmInfo->suportedPreChargeAll == 1) + DP (printf + (" - Precharge All: Yes \n")); + else + DP (printf + (" - Precharge All: No \n")); + + if (dimmInfo->suportedWrite1ReadBurst == 1) + DP (printf + (" - Write 1/ReadBurst: Yes \n")); + else + DP (printf + (" - Write 1/ReadBurst: No \n")); + + if (dimmInfo->suported5PercentLowVCC == 1) + DP (printf + (" - lower VCC tolerance: 5 Percent \n")); + else + DP (printf + (" - lower VCC tolerance: 10 Percent \n")); + + if (dimmInfo->suported5PercentUpperVCC == 1) + DP (printf + (" - upper VCC tolerance: 5 Percent \n")); + else + DP (printf + (" - upper VCC tolerance: 10 Percent \n")); + +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ + shift = (dimmInfo->memoryType == DDR) ? 4 : 2; + mult = (dimmInfo->memoryType == DDR) ? 10 : 25; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf : 0x03; + leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; + rightOfPoint = (data[i] & maskRightOfPoint) * mult; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = + leftOfPoint; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = + rightOfPoint; + DP (printf + ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint)); + /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ + div = (dimmInfo->memoryType == DDR) ? 100 : 10; + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; + dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; + DP (printf + ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ + shift = (dimmInfo->memoryType == DDR) ? 4 : 2; + mult = (dimmInfo->memoryType == DDR) ? 10 : 25; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0xf : 0x03; + leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; + rightOfPoint = (data[i] & maskRightOfPoint) * mult; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = + leftOfPoint; + dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = + rightOfPoint; + DP (printf + ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint)); + /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ + div = (dimmInfo->memoryType == DDR) ? 100 : 10; + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; + dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; + DP (printf + ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 27: /* Minimum Row Precharge Time */ + shift = (dimmInfo->memoryType == DDR) ? 2 : 0; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; + leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (data[i] & maskRightOfPoint) * 25; + + dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ + trp_clocks = + (dimmInfo->minRowPrechargeTime + + (tmemclk - 1)) / tmemclk; + DP (printf + ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", + tmemclk, tmemclk / 100, tmemclk % 100)); + DP (printf + ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 28: /* Minimum Row Active to Row Active Time */ + shift = (dimmInfo->memoryType == DDR) ? 2 : 0; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; + leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (data[i] & maskRightOfPoint) * 25; + + dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ + trrd_clocks = + (dimmInfo->minRowActiveRowActiveDelay + + (tmemclk - 1)) / tmemclk; + DP (printf + ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 29: /* Minimum Ras-To-Cas Delay */ + shift = (dimmInfo->memoryType == DDR) ? 2 : 0; + maskLeftOfPoint = + (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; + maskRightOfPoint = + (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; + leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (data[i] & maskRightOfPoint) * 25; + + dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ + trcd_clocks = + (dimmInfo->minRowActiveRowActiveDelay + + (tmemclk - 1)) / tmemclk; + DP (printf + ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 30: /* Minimum Ras Pulse Width */ + dimmInfo->minRasPulseWidth = data[i]; + tras_clocks = + (NSto10PS (data[i]) + + (tmemclk - 1)) / tmemclk; + DP (printf + ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", + dimmInfo->minRasPulseWidth, tras_clocks)); + + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 31: /* Module Bank Density */ + dimmInfo->moduleBankDensity = data[i]; + DP (printf + ("Module Bank Density: %d\n", + dimmInfo->moduleBankDensity)); +#ifdef DEBUG + DP (printf + ("*** Offered Densities (more than 1 = Multisize-Module): ")); + { + if (dimmInfo->moduleBankDensity & 1) + DP (printf ("4MB, ")); + if (dimmInfo->moduleBankDensity & 2) + DP (printf ("8MB, ")); + if (dimmInfo->moduleBankDensity & 4) + DP (printf ("16MB, ")); + if (dimmInfo->moduleBankDensity & 8) + DP (printf ("32MB, ")); + if (dimmInfo->moduleBankDensity & 16) + DP (printf ("64MB, ")); + if (dimmInfo->moduleBankDensity & 32) + DP (printf ("128MB, ")); + if ((dimmInfo->moduleBankDensity & 64) + || (dimmInfo->moduleBankDensity & 128)) { + DP (printf ("ERROR, ")); + hang (); + } + } + DP (printf ("\n")); +#endif + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 32: /* Address And Command Setup Time (measured in ns/1000) */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->addrAndCommandSetupTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Address And Command Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 33: /* Address And Command Hold Time */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->addrAndCommandHoldTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Address And Command Hold Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 34: /* Data Input Setup Time */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->dataInputSetupTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Data Input Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + + case 35: /* Data Input Hold Time */ + sign = 1; + switch (dimmInfo->memoryType) { + case DDR: + time_tmp = + (((data[i] & 0xf0) >> 4) * 10) + + ((data[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + break; + case SDRAM: + leftOfPoint = (data[i] & 0xf0) >> 4; + if (leftOfPoint > 7) { + leftOfPoint = data[i] & 0x70 >> 4; + sign = -1; + } + rightOfPoint = (data[i] & 0x0f); + break; + } + dimmInfo->dataInputHoldTime = + (leftOfPoint * 100 + rightOfPoint) * sign; + DP (printf + ("Data Input Hold Time [ns]: %d.%d\n\n", + sign * leftOfPoint, rightOfPoint)); + break; +/*------------------------------------------------------------------------------------------------------------------------------*/ + } + } + /* calculating the sdram density */ + for (i = 0; + i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; + i++) { + density = density * 2; + } + dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * + dimmInfo->sdramWidth; + dimmInfo->numberOfDevices = + (dimmInfo->dataWidth / dimmInfo->sdramWidth) * + dimmInfo->numOfModuleBanks; + devicesForErrCheck = + (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; + if ((dimmInfo->errorCheckType == 0x1) + || (dimmInfo->errorCheckType == 0x2) + || (dimmInfo->errorCheckType == 0x3)) { + dimmInfo->size = + (dimmInfo->deviceDensity / 8) * + (dimmInfo->numberOfDevices - devicesForErrCheck); + } else { + dimmInfo->size = + (dimmInfo->deviceDensity / 8) * + dimmInfo->numberOfDevices; + } + + /* compute the module DRB size */ + tmp = (1 << + (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); + tmp *= dimmInfo->numOfModuleBanks; + tmp *= dimmInfo->sdramWidth; + tmp = tmp >> 24; /* div by 0x4000000 (64M) */ + dimmInfo->drb_size = (uchar) tmp; + DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + + /* try a CAS latency of 3 first... */ + + /* bit 1 is CL2, bit 2 is CL3 */ + supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1; + + cal_val = 0; + if (supp_cal & 8) { + if (NS10to10PS (data[9]) <= tmemclk) + cal_val = 6; + } + if (supp_cal & 4) { + if (NS10to10PS (data[9]) <= tmemclk) + cal_val = 5; + } + + /* then 2... */ + if (supp_cal & 2) { + if (NS10to10PS (data[23]) <= tmemclk) + cal_val = 4; + } + + DP (printf ("cal_val = %d\n", cal_val * 5)); + + /* bummer, did't work... */ + if (cal_val == 0) { + DP (printf ("Couldn't find a good CAS latency\n")); + hang (); + return 0; + } + + return true; +} + +/* sets up the GT properly with information passed in */ +int setup_sdram (AUX_MEM_DIMM_INFO * info) +{ + ulong tmp, check; + ulong tmp_sdram_mode = 0; /* 0x141c */ + ulong tmp_dunit_control_low = 0; /* 0x1404 */ + int i; + + /* sanity checking */ + if (!info->numOfModuleBanks) { + printf ("setup_sdram called with 0 banks\n"); + return 1; + } + + /* delay line */ + + /* Program the GT with the discovered data */ + if (info->registeredAddrAndControlInputs == true) + DP (printf + ("Module is registered, but we do not support registered Modules !!!\n")); + + + /* delay line */ + set_dfcdlInit (); /* may be its not needed */ + DP (printf ("Delay line set done\n")); + + /* set SDRAM mode NOP */ /* To_do check it */ + GT_REG_WRITE (SDRAM_OPERATION, 0x5); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + } + + /* SDRAM configuration */ + GT_REG_WRITE (SDRAM_CONFIG, 0x58200400); + DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); + + /* SDRAM open pages controll keep open as much as I can */ + GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); + DP (printf + ("sdram_open_pages_controll 0x1414: %08x\n", + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + + + /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ + tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ + if (tmp == 0) + DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + else + DP (printf + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + + /* SDRAM set CAS Lentency according to SPD information */ + switch (info->memoryType) { + case SDRAM: + DP (printf ("### SD-RAM not supported yet !!!\n")); + hang (); + /* ToDo fill SD-RAM if needed !!!!! */ + break; + + case DDR: + DP (printf ("### SET-CL for DDR-RAM\n")); + + switch (info->maxClSupported_DDR) { + case DDR_CL_3: + tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */ + tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ + DP (printf + ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + break; + + case DDR_CL_2_5: + if (tmp == 1) { /* clocks sync */ + tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */ + tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ + DP (printf + ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } else { /* clk sync. bypassed */ + + tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ + tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ + DP (printf + ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + + case DDR_CL_2: + if (tmp == 1) { /* Sync */ + tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ + tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ + DP (printf + ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } else { /* Not sync. */ + + tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */ + tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ + DP (printf + ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + + case DDR_CL_1_5: + if (tmp == 1) { /* Sync */ + tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */ + tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ + DP (printf + ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } else { /* not sync */ + + tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */ + tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ + DP (printf + ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low)); + } + break; + + default: + printf ("Max. CL is out of range %d\n", + info->maxClSupported_DDR); + hang (); + break; + } + break; + } + + /* Write results of CL detection procedure */ + GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); + /* set SDRAM mode SetCommand 0x1418 */ + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + } + + + /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ + tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ + if (tmp != 1) { /*clocks are not sync */ + /* asyncmode */ + GT_REG_WRITE (D_UNIT_CONTROL_LOW, + (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) | + 0x18110780 | tmp_dunit_control_low); + } else { + /* syncmode */ + GT_REG_WRITE (D_UNIT_CONTROL_LOW, + (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) | + 0x00110000 | tmp_dunit_control_low); + } + + /* set SDRAM mode SetCommand 0x1418 */ + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + } + +/*------------------------------------------------------------------------------ */ + + + /* bank parameters */ + /* SDRAM address decode register */ + /* program this with the default value */ + tmp = 0x02; + + + DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + switch (info->drb_size) { + case 1: /* 64 Mbit */ + case 2: /* 128 Mbit */ + DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + tmp |= (0x00 << 4); + break; + case 4: /* 256 Mbit */ + case 8: /* 512 Mbit */ + DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + tmp |= (0x01 << 4); + break; + case 16: /* 1 Gbit */ + case 32: /* 2 Gbit */ + DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + tmp |= (0x02 << 4); + break; + default: + printf ("Error in dram size calculation\n"); + DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n")); + tmp |= (0x02 << 4); + return 1; + } + + /* SDRAM bank parameters */ + /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ + DP (printf + ("setting up slot %d config with: %08lx \n", info->slot, tmp)); + GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); + +/* ------------------------------------------------------------------------------ */ + + DP (printf + ("setting up sdram_timing_control_low with: %08x \n", + 0x11511220)); + GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); + + +/* ------------------------------------------------------------------------------ */ + + /* SDRAM configuration */ + tmp = GTREGREAD (SDRAM_CONFIG); + + if (info->registeredAddrAndControlInputs + || info->registeredDQMBinputs) { + tmp |= (1 << 17); + DP (printf + ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", + info->registeredAddrAndControlInputs, + info->registeredDQMBinputs)); + } + + /* Use buffer 1 to return read data to the CPU + * Page 426 MV64360 */ + tmp |= (1 << 26); + DP (printf + ("Before Buffer assignment - sdram_conf: %08x\n", + GTREGREAD (SDRAM_CONFIG))); + DP (printf + ("After Buffer assignment - sdram_conf: %08x\n", + GTREGREAD (SDRAM_CONFIG))); + + /* SDRAM timing To_do: */ + + + tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH); + DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp)); + + /* SDRAM address decode register */ + /* program this with the default value */ + tmp = GTREGREAD (SDRAM_ADDR_CONTROL); + DP (printf + ("SDRAM address control (before: decode): %08x ", + GTREGREAD (SDRAM_ADDR_CONTROL))); + GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2)); + DP (printf + ("SDRAM address control (after: decode): %08x\n", + GTREGREAD (SDRAM_ADDR_CONTROL))); + + /* set the SDRAM configuration for each bank */ + +/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ + { + i = info->slot; + DP (printf + ("\n*** Running a MRS cycle for bank %d ***\n", i)); + + /* map the bank */ + memory_map_bank (i, 0, GB / 4); +#if 1 /* test only */ + /* set SDRAM mode */ /* To_do check it */ + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + check = GTREGREAD (SDRAM_OPERATION); + DP (printf + ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", + check)); + + + /* switch back to normal operation mode */ + GT_REG_WRITE (SDRAM_OPERATION, 0); + check = GTREGREAD (SDRAM_OPERATION); + DP (printf + ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", + check)); +#endif /* test only */ + /* unmap the bank */ + memory_map_bank (i, 0, 0); + } + + return 0; +} + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +long int +dram_size(long int *base, long int maxsize) +{ + volatile long int *addr, *b=base; + long int cnt, val, save1, save2; + +#define STARTVAL (1<<20) /* start test at 1M */ + for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + save1=*addr; /* save contents of addr */ + save2=*b; /* save contents of base */ + + *addr=cnt; /* write cnt to addr */ + *b=0; /* put null at base */ + + /* check at base address */ + if ((*b) != 0) { + *addr=save1; /* restore *addr */ + *b=save2; /* restore *b */ + return (0); + } + val = *addr; /* read *addr */ + val = *addr; /* read *addr */ + + *addr=save1; + *b=save2; + + if (val != cnt) { + DP(printf("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr)); + /* fix boundary condition.. STARTVAL means zero */ + if(cnt==STARTVAL/sizeof(long)) cnt=0; + return (cnt * sizeof(long)); + } + } + return maxsize; +} + +/* ------------------------------------------------------------------------- */ + +/* ppcboot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int +initdram(int board_type) +{ + int s0 = 0, s1 = 0; + int checkbank[4] = { [0 ... 3] = 0 }; + ulong bank_no, realsize, total, check; + AUX_MEM_DIMM_INFO dimmInfo1; + AUX_MEM_DIMM_INFO dimmInfo2; + int nhr; + + /* first, use the SPD to get info about the SDRAM/ DDRRAM */ + + /* check the NHR bit and skip mem init if it's already done */ + nhr = get_hid0() & (1 << 16); + + if (nhr) { + printf("Skipping SD- DDRRAM setup due to NHR bit being set\n"); + } else { + /* DIMM0 */ + s0 = check_dimm(0, &dimmInfo1); + + /* DIMM1 */ + s1 = check_dimm(1, &dimmInfo2); + + memory_map_bank(0, 0, 0); + memory_map_bank(1, 0, 0); + memory_map_bank(2, 0, 0); + memory_map_bank(3, 0, 0); + + if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) { + printf("Setup for DIMM1 failed.\n"); + } + + if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) { + printf("Setup for DIMM2 failed.\n"); + } + + /* set the NHR bit */ + set_hid0(get_hid0() | (1 << 16)); + } + /* next, size the SDRAM banks */ + + realsize = total = 0; + check = GB/4; + if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");} + if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");} + if (dimmInfo1.numOfModuleBanks > 2) + printf("Error, SPD claims DIMM1 has >2 banks\n"); + + if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");} + if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");} + if (dimmInfo2.numOfModuleBanks > 2) + printf("Error, SPD claims DIMM2 has >2 banks\n"); + + for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + /* skip over banks that are not populated */ + if (! checkbank[bank_no]) + continue; + + if ((total + check) > CFG_GT_REGS) + check = CFG_GT_REGS - total; + + memory_map_bank(bank_no, total, check); + realsize = dram_size((long int *)total, check); + memory_map_bank(bank_no, total, realsize); + + total += realsize; + } + +/* Setup Ethernet DMA Adress window to DRAM Area */ + return(total); +} + +/* *************************************************************************************** +! * SDRAM INIT * +! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * +! * This procedure fits only the Atlantis * +! * * +! *************************************************************************************** */ + + +/* *************************************************************************************** +! * DFCDL initialize MV643xx Design Considerations * +! * * +! *************************************************************************************** */ +int set_dfcdlInit (void) +{ + int i; + unsigned int dfcdl_word = 0x0000014f; + + for (i = 0; i < 64; i++) { + GT_REG_WRITE (SRAM_DATA0, dfcdl_word); + } + GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ + + + return (0); +} diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c new file mode 100644 index 0000000..44de052 --- /dev/null +++ b/board/esd/cpci750/serial.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * modified for marvell db64360 eval board by + * Ingo Assmus + * + * modified for cpci750 board by + * Reinhard Arlt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * serial.c - serial support for esd cpci750 board + */ + +/* supports the MPSC */ + +#include +#include +#include "../../Marvell/include/memory.h" +#include "serial.h" + + +#include "mpsc.h" + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + mpsc_init (gd->baudrate); + + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') + mpsc_putchar ('\r'); + + mpsc_putchar (c); +} + +int serial_getc (void) +{ + return mpsc_getchar (); +} + +int serial_tstc (void) +{ + return mpsc_test_char (); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); +} + + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +void kgdb_serial_init (void) +{ +} + +void putDebugChar (int c) +{ + serial_putc (c); +} + +void putDebugStr (const char *str) +{ + serial_puts (str); +} + +int getDebugChar (void) +{ + return serial_getc (); +} + +void kgdb_interruptible (int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ diff --git a/board/esd/cpci750/serial.h b/board/esd/cpci750/serial.h new file mode 100644 index 0000000..c7fc8c1 --- /dev/null +++ b/board/esd/cpci750/serial.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * modified for marvell db64360 eval board by + * Ingo Assmus + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* serial.h - mostly useful for DUART serial_init in serial.c */ + +#ifndef __SERIAL_H__ +#define __SERIAL_H__ + +#if 0 + +#define B230400 1 +#define B115200 2 +#define B57600 4 +#define B38400 82 +#define B19200 163 +#define B9600 24 +#define B4800 651 +#define B2400 1302 +#define B1200 2604 +#define B600 5208 +#define B300 10417 +#define B150 20833 +#define B110 28409 +#define BDEFAULT B115200 + + /* this stuff is important to initialize + the DUART channels */ + +#define Scale 0x01L /* distance between port addresses */ +#define COM1 0x000003f8 /* Keyboard */ +#define COM2 0x000002f8 /* Host */ + + +/* Port Definitions relative to base COM port addresses */ +#define DataIn (0x00*Scale) /* data input port */ +#define DataOut (0x00*Scale) /* data output port */ +#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ +#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ +#define Ier (0x01*Scale) /* interrupt enable register */ +#define Iir (0x02*Scale) /* interrupt identification register */ +#define Lcr (0x03*Scale) /* line control register */ +#define Mcr (0x04*Scale) /* modem control register */ +#define Lsr (0x05*Scale) /* line status register */ +#define Msr (0x06*Scale) /* modem status register */ + +/* Bit Definitions for above ports */ +#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ +#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ + +#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ +#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ +#define McrDflt (McrRts|McrDtr) + +#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ + /* b6: transmitter empty */ +#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ + +#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ +#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ +#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ + +#define IerRda 0xf /* b0: Enable received data available interrupt */ + +#endif + +#endif /* __SERIAL_H__ */ diff --git a/board/esd/cpci750/strataflash.c b/board/esd/cpci750/strataflash.c new file mode 100644 index 0000000..c22fe5d --- /dev/null +++ b/board/esd/cpci750/strataflash.c @@ -0,0 +1,763 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + + +#define FLASH_MAN_CFI 0x01000000 + + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char * cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +/*----------------------------------------------------------------------- + * Functions + */ + + +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *)(info->start[sect] + (offset * info->portwidth))); +} +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | + (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + unsigned long address; + + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if( info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3 ), (info->chipwidth << 3 )); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n"); + printf (" %08lX%5s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for(i=0;iportwidth) && (cnt > 0) ; i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *)cp)); + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while(cnt >= info->portwidth) { + i = info->buffer_size > cnt? cnt: info->buffer_size; + if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + /* handle the aligned part */ + while(cnt >= info->portwidth) { + cword.l = 0; + for(i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; iportwidth; ++i, ++cp) { + flash_add_byte(info, & cword, (*(uchar *)cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if(prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, + prot?"protect":"unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if(prot == 0) { + int i; + for(i = 0 ; isector_count; i++) { + if(info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt,info->start[sector]); + if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ + printf("Command Sequence Error.\n"); + } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) +{ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) +{ + int i; + uchar *cp = (uchar *)cmdbuf; + for(i=0; i< info->portwidth; i++) + *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * + */ +static int flash_detect_cfi(flash_info_t * info) +{ + + for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; + info->portwidth <<= 1) { + for(info->chipwidth =FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } + return 0; +} +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t * info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio = 0; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + invalidate_dcache_range(base, base+0x400); + + if(flash_detect_cfi(info)){ + + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); + + sect_cnt = 0; + sector = base; + for(i = 0 ; i < num_erase_regions; i++) { + if(i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) +1; + for(j = 0; j< erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); +#ifdef DEBUG_FLASH + printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif +#ifdef DEBUG_FLASH + printf("size=%08x sectors=%08x \n", info->size, info->sector_count); +#endif + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *)dest; + + + /* Check if Flash is (sufficiently) erased */ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if(!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if(flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t *info, ulong addr) +{ + int sector; + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *)dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar)cnt-1); + while(cnt-- > 0) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check(info, sector, info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci750/u-boot.lds b/board/esd/cpci750/u-boot.lds new file mode 100644 index 0000000..d89eb6c --- /dev/null +++ b/board/esd/cpci750/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile new file mode 100644 index 0000000..a60495a --- /dev/null +++ b/board/esd/cpciiser4/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/cpciiser4/config.mk b/board/esd/cpciiser4/config.mk new file mode 100644 index 0000000..58574cb --- /dev/null +++ b/board/esd/cpciiser4/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd CPCIISER4 boards +# + +#TEXT_BASE = 0xFFFE0000 +#TEXT_BASE = 0xFFFD0000 +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c new file mode 100644 index 0000000..7bf7bb5 --- /dev/null +++ b/board/esd/cpciiser4/cpciiser4.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2000 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "cpciiser4.h" +#include +#include + +/*cmd_boot.c*/ + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); + + +/* ------------------------------------------------------------------------- */ + +#if 0 +#define FPGA_DEBUG +#endif + +#if 0 +#define FPGA_DEBUG2 +#endif + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = { +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +int board_early_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int index, len, i; + volatile unsigned char dummy; + int status; + +#ifdef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + + /* + * Boot onboard FPGA + */ + status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); + if (status != 0) { + /* booting FPGA failed */ +#ifndef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + printf ("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf ("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("FPGA: %s\n", &(fpgadata[index + 1])); + index += len + 3; + } + putc ('\n'); + /* delayed reboot */ + for (i = 20; i > 0; i--) { + printf ("Rebooting in %2d seconds \r", i); + for (index = 0; index < 1000; index++) + udelay (1000); + } + putc ('\n'); + do_reset (NULL, 0, 0, NULL); + } + + /* + * Init FPGA via RESET (read access on CS3) + */ + dummy = *(unsigned char *) 0xf0200000; + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + /* mtdcr(uicpr, 0xFFFFFF81); / set int polarities */ + mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + int index; + int len; + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming AR405"); + } else { + puts(str); + } + + puts ("\nFPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("%s ", &(fpgadata[index + 1])); + index += len + 3; + } + + putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + return (16 * 1024 * 1024); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/cpciiser4/cpciiser4.h b/board/esd/cpciiser4/cpciiser4.h new file mode 100644 index 0000000..5fc313a --- /dev/null +++ b/board/esd/cpciiser4/cpciiser4.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c new file mode 100644 index 0000000..de847f9 --- /dev/null +++ b/board/esd/cpciiser4/flash.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile new file mode 100644 index 0000000..e3b1c87 --- /dev/null +++ b/board/esd/dasa_sim/Makefile @@ -0,0 +1,47 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c new file mode 100644 index 0000000..89a4aaf --- /dev/null +++ b/board/esd/dasa_sim/cmd_dasa_sim.c @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#define OK 0 +#define ERROR (-1) + +#define TRUE 1 +#define FALSE 0 + + +extern u_long pci9054_iobase; + + +/*************************************************************************** + * + * Routines for PLX PCI9054 eeprom access + * + */ + +static unsigned int PciEepromReadLongVPD (int offs) +{ + unsigned int value; + unsigned int ret; + int count; + + pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c, + (offs << 16) | 0x0003); + count = 0; + + for (;;) { + udelay (10 * 1000); + pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret); + if ((ret & 0x80000000) != 0) { + break; + } else { + count++; + if (count > 10) { + printf ("\nTimeout: ret=%08x - Please try again!\n", ret); + break; + } + } + } + + pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x50, &value); + + return value; +} + + +static int PciEepromWriteLongVPD (int offs, unsigned int value) +{ + unsigned int ret; + int count; + + pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x50, value); + pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c, + (offs << 16) | 0x80000003); + count = 0; + + for (;;) { + udelay (10 * 1000); + pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret); + if ((ret & 0x80000000) == 0) { + break; + } else { + count++; + if (count > 10) { + printf ("\nTimeout: ret=%08x - Please try again!\n", ret); + break; + } + } + } + + return TRUE; +} + + +static void showPci9054 (void) +{ + int val; + int l, i; + + /* read 9054-values */ + for (l = 0; l < 6; l++) { + printf ("%02x: ", l * 0x10); + for (i = 0; i < 4; i++) { + pci_read_config_dword (CFG_PCI9054_DEV_FN, + l * 16 + i * 4, + (unsigned int *)&val); + printf ("%08x ", val); + } + printf ("\n"); + } + printf ("\n"); + + for (l = 0; l < 7; l++) { + printf ("%02x: ", l * 0x10); + for (i = 0; i < 4; i++) + printf ("%08x ", + PciEepromReadLongVPD ((i + l * 4) * 4)); + printf ("\n"); + } + printf ("\n"); +} + + +static void updatePci9054 (void) +{ + int val; + + /* + * Set EEPROM write-protect register to 0 + */ + out32 (pci9054_iobase + 0x0c, + in32 (pci9054_iobase + 0x0c) & 0xffff00ff); + + /* Long Serial EEPROM Load Registers... */ + val = PciEepromWriteLongVPD (0x00, 0x905410b5); + val = PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ + val = PciEepromWriteLongVPD (0x08, 0x28140100); + + val = PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ + val = PciEepromWriteLongVPD (0x10, 0x00000000); + + /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */ + val = PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ + val = PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ + + val = PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ + val = PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ + + val = PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ + val = PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ + + val = PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ + + val = PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ + val = PciEepromWriteLongVPD (0x34, 0x00000000); + val = PciEepromWriteLongVPD (0x38, 0x00000000); + + val = PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ + val = PciEepromWriteLongVPD (0x40, 0x00000000); + + /* Extra Long Serial EEPROM Load Registers... */ + val = PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ + + /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */ + /* Offset to LAS1: Group 1: 0x00040000 */ + /* Group 2: 0x00080000 */ + /* Group 3: 0x000c0000 */ + val = PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ + val = PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ + val = PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ + + val = PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ + + printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n"); +} + + +static void clearPci9054 (void) +{ + int val; + + /* + * Set EEPROM write-protect register to 0 + */ + out32 (pci9054_iobase + 0x0c, + in32 (pci9054_iobase + 0x0c) & 0xffff00ff); + + /* Long Serial EEPROM Load Registers... */ + val = PciEepromWriteLongVPD (0x00, 0xffffffff); + val = PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ + + printf ("Finished clearing PLX PCI9054 EEPROM!\n"); +} + + +/* ------------------------------------------------------------------------- */ +int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc, + char *argv[]) +{ + if (strcmp (argv[1], "info") == 0) { + showPci9054 (); + return 0; + } + + if (strcmp (argv[1], "update") == 0) { + updatePci9054 (); + return 0; + } + + if (strcmp (argv[1], "clear") == 0) { + clearPci9054 (); + return 0; + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + +} + +U_BOOT_CMD( + pci9054, 3, 1, do_pci9054, + "pci9054 - PLX PCI9054 EEPROM access\n", + "pci9054 info - print EEPROM values\n" + "pci9054 update - updates EEPROM with default values\n" +); + +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/dasa_sim/config.mk b/board/esd/dasa_sim/config.mk new file mode 100644 index 0000000..747f29f --- /dev/null +++ b/board/esd/dasa_sim/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +# FLASH: +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFFD0000 + +# SDRAM: +#TEXT_BASE = 0x00FE0000 diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c new file mode 100644 index 0000000..2f8ab1a --- /dev/null +++ b/board/esd/dasa_sim/dasa_sim.c @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "dasa_sim.h" + +/* ------------------------------------------------------------------------- */ + +#undef FPGA_DEBUG + +#define _NOT_USED_ 0xFFFFFFFF + +/* ------------------------------------------------------------------------- */ + +/* fpga configuration data - generated by bit2inc */ +static unsigned char fpgadata[] = { +#include "fpgadata.c" +}; + +#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */ +#define LOAD_LONG(a) a + + +/****************************************************************************** + * + * sysFpgaBoot - Load fpga-image into fpga + * + */ +static int fpgaBoot (void) +{ + int i, j, index, len; + unsigned char b; + int imageSize; + + imageSize = sizeof (fpgadata); + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + index += len + 3; + } + + /* search for preamble 0xFF2X */ + for (index = 0; index < imageSize - 1; index++) { + if ((fpgadata[index] == 0xff) + && ((fpgadata[index + 1] & 0xf0) == 0x20)) + break; + } + + /* enable cs1 instead of user0... */ + *(unsigned long *) 0x50000084 &= ~0x00000002; + +#ifdef FPGA_DEBUG + printf ("%s\n", + ((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE"); +#endif + + /* init fpga by asserting and deasserting PROGRAM* (USER2)... */ + *(unsigned long *) 0x50000084 &= ~0x00000400; + udelay (FPGA_PRG_SLEEP * 1000); + + *(unsigned long *) 0x50000084 |= 0x00000400; + udelay (FPGA_PRG_SLEEP * 1000); + +#ifdef FPGA_DEBUG + printf ("%s\n", + ((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE"); +#endif + + /* cs1: disable burst, disable ready */ + *(unsigned long *) 0x50000114 &= ~0x00000300; + + /* cs1: set write timing */ + *(unsigned long *) 0x50000118 |= 0x00010900; + + /* write configuration-data into fpga... */ + for (i = index; i < imageSize; i++) { + b = fpgadata[i]; + for (j = 0; j < 8; j++) { + *(unsigned long *) 0x30000000 = + ((b & 0x80) == 0x80) + ? LOAD_LONG (0x03030101) + : LOAD_LONG (0x02020000); + b <<= 1; + } + } + +#ifdef FPGA_DEBUG + printf ("%s\n", + ((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE"); +#endif + + /* set cs1 to 32 bit data-width, disable burst, enable ready */ + *(unsigned long *) 0x50000114 |= 0x00000202; + *(unsigned long *) 0x50000114 &= ~0x00000100; + + /* cs1: set iop access to little endian */ + *(unsigned long *) 0x50000114 &= ~0x00000010; + + /* cs1: set read and write timing */ + *(unsigned long *) 0x50000118 = 0x00010000; + *(unsigned long *) 0x5000011c = 0x00010001; + +#ifdef FPGA_DEBUG + printf ("%s\n", + ((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE"); +#endif + + /* wait for 30 ms... */ + udelay (30 * 1000); + /* check if fpga's DONE signal - correctly booted ? */ + if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0) + return -1; + + return 0; +} + + +int board_early_init_f (void) +{ + /* + * Init pci regs + */ + *(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */ + *(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */ + *(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */ + *(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */ + *(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */ + *(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */ + *(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */ + + return 0; +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + int index; + int len; + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + int fpga; + unsigned short val; + + puts ("Board: "); + + /* + * Boot onboard FPGA + */ + fpga = fpgaBoot (); + + if (!i || strncmp (str, "DASA_SIM", 8)) { + puts ("### No HW ID - assuming DASA_SIM"); + } + + puts (str); + + if (fpga == 0) { + val = *(unsigned short *) 0x30000202; + printf (" (Id=%d Version=%d Revision=%d)", + (val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1); + + puts ("\nFPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("%s ", &(fpgadata[index + 1])); + index += len + 3; + } + } else { + puts ("\nFPGA: Booting failed!"); + } + + putc ('\n'); + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + return (16 * 1024 * 1024); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/dasa_sim/dasa_sim.h b/board/esd/dasa_sim/dasa_sim.h new file mode 100644 index 0000000..5fc313a --- /dev/null +++ b/board/esd/dasa_sim/dasa_sim.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/board/esd/dasa_sim/eeprom.c b/board/esd/dasa_sim/eeprom.c new file mode 100644 index 0000000..1b4c7b3 --- /dev/null +++ b/board/esd/dasa_sim/eeprom.c @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include + + +#define EEPROM_CAP 0x50000358 +#define EEPROM_DATA 0x5000035c + + +unsigned int eepromReadLong(int offs) +{ + unsigned int value; + volatile unsigned short ret; + int count; + + *(unsigned short *)EEPROM_CAP = offs; + + count = 0; + + for (;;) + { + count++; + ret = *(unsigned short *)EEPROM_CAP; + + if ((ret & 0x8000) != 0) + break; + } + + value = *(unsigned long *)EEPROM_DATA; + + return value; +} + + +unsigned char eepromReadByte(int offs) +{ + unsigned int valueLong; + unsigned char *ptr; + + valueLong = eepromReadLong(offs & ~3); + ptr = (unsigned char *)&valueLong; + + return ptr[offs & 3]; +} + + +void eepromWriteLong(int offs, unsigned int value) +{ + volatile unsigned short ret; + int count; + + count = 0; + + *(unsigned long *)EEPROM_DATA = value; + *(unsigned short *)EEPROM_CAP = 0x8000 + offs; + + for (;;) + { + count++; + ret = *(unsigned short *)EEPROM_CAP; + + if ((ret & 0x8000) == 0) + break; + } +} + + +void eepromWriteByte(int offs, unsigned char valueByte) +{ + unsigned int valueLong; + unsigned char *ptr; + + valueLong = eepromReadLong(offs & ~3); + ptr = (unsigned char *)&valueLong; + + ptr[offs & 3] = valueByte; + + eepromWriteLong(offs & ~3, valueLong); +} + + +void i2c_read (uchar *addr, int alen, uchar *buffer, int len) +{ + int i; + int len2, ptr; + + /* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */ + + ptr = *(short *)addr; + + /* + * Read till lword boundary + */ + len2 = 4 - (*(short *)addr & 0x0003); + for (i=0; i> 2; + for (i=0; i> 2; + for (i=0; i +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static void flash_get_offsets (ulong base, flash_info_t *info); + + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + unsigned long base_b0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile new file mode 100644 index 0000000..a11ee82 --- /dev/null +++ b/board/esd/dp405/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +# Objects for Xilinx JTAG programming (CPLD) +CPLD = ../common/xilinx_jtag/lenval.o \ + ../common/xilinx_jtag/micro.o \ + ../common/xilinx_jtag/ports.o + +OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/dp405/config.mk b/board/esd/dp405/config.mk new file mode 100644 index 0000000..3041b77 --- /dev/null +++ b/board/esd/dp405/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd VOH405 boards +# + +TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0x00FC0000 diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c new file mode 100644 index 0000000..fd51f7f --- /dev/null +++ b/board/esd/dp405/dp405.c @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +/* fpga configuration data - not compressed, generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; +int filesize = sizeof(fpgadata); + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + /* + * Reset CPLD via GPIO13 (CS4) pin + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 13)); + udelay(1000); /* wait 1ms */ + out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 13)); + udelay(1000); /* wait 1ms */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe, + 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf}; + unsigned char id1, id2; + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming DP405"); + } else { + puts(str); + } + + id1 = trans[(~(in32(GPIO0_IR) >> 5)) & 0x0000000f]; + id2 = trans[(~(in32(GPIO0_IR) >> 9)) & 0x0000000f]; + printf(" (ID=0x%1X%1X, PLD=0x%02X)\n", id2, id1, in8(0xf0001000)); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/dp405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile new file mode 100644 index 0000000..5ec4a4f --- /dev/null +++ b/board/esd/du405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/du405/config.mk b/board/esd/du405/config.mk new file mode 100644 index 0000000..d091d96 --- /dev/null +++ b/board/esd/du405/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd CPCIISER4 boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFFD0000 +#TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c new file mode 100644 index 0000000..26e8341 --- /dev/null +++ b/board/esd/du405/du405.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2000, 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "du405.h" +#include +#include +#include <405gp_i2c.h> +#include + +/*cmd_boot.c*/ + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); + + +#if 0 +#define FPGA_DEBUG +#endif + +#if 0 +#define FPGA_DEBUG2 +#endif + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = { +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +int board_early_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int index, len, i; + int status; + +#ifdef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + + /* + * Boot onboard FPGA + */ + status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); + if (status != 0) { + /* booting FPGA failed */ +#ifndef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + printf ("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf ("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("FPGA: %s\n", &(fpgadata[index + 1])); + index += len + 3; + } + putc ('\n'); + /* delayed reboot */ + for (i = 20; i > 0; i--) { + printf ("Rebooting in %2d seconds \r", i); + for (index = 0; index < 1000; index++) + udelay (1000); + } + putc ('\n'); + do_reset (NULL, 0, 0, NULL); + } + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive + * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive + * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive + * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive + * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 100 us + */ + mtebc (epcr, 0xb8400000); + + return 0; +} + + +int misc_init_r (void) +{ + unsigned long cntrl0Reg; + + /* + * Setup UART1 handshaking: use CTS instead of DSR + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00001000); + + return (0); +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + int index; + int len; + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming DU405"); + } else { + puts (str); + } + + puts ("\nFPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("%s ", &(fpgadata[index + 1])); + index += len + 3; + } + + putc ('\n'); + + /* + * Reset external DUART via FPGA + */ + *(volatile unsigned char *) FPGA_MODE_REG = 0xff; /* reset high active */ + *(volatile unsigned char *) FPGA_MODE_REG = 0x00; /* low again */ + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + + +long int initdram (int board_type) +{ + return (16 * 1024 * 1024); +} + + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} diff --git a/board/esd/du405/du405.h b/board/esd/du405/du405.h new file mode 100644 index 0000000..768e843 --- /dev/null +++ b/board/esd/du405/du405.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c new file mode 100644 index 0000000..14549c0 --- /dev/null +++ b/board/esd/du405/flash.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + base_b0 = FLASH_BASE0_PRELIM; + size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + base_b1 = FLASH_BASE1_PRELIM; + size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); + + /* Re-do sizing to get full correct info */ + + if (size_b1) { + mtdcr (ebccfga, pb0cr); + pbcr = mfdcr (ebccfgd); + mtdcr (ebccfga, pb0cr); + base_b1 = -size_b1; + pbcr = (pbcr & 0x0001ffff) | base_b1 | + (((size_b1 / 1024 / 1024) - 1) << 17); + mtdcr (ebccfgd, pbcr); + /* printf("pb1cr = %x\n", pbcr); */ + } + + if (size_b0) { + mtdcr (ebccfga, pb1cr); + pbcr = mfdcr (ebccfgd); + mtdcr (ebccfga, pb1cr); + base_b0 = base_b1 - size_b0; + pbcr = (pbcr & 0x0001ffff) | base_b0 | + (((size_b0 / 1024 / 1024) - 1) << 17); + mtdcr (ebccfgd, pbcr); + /* printf("pb0cr = %x\n", pbcr); */ + } + + size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); + + flash_get_offsets (base_b0, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); + + flash_get_offsets (base_b1, &flash_info[1]); + + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + base_b1 + size_b1 - monitor_flash_len, + base_b1 + size_b1 - 1, &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + flash_protect (FLAG_PROTECT_CLEAR, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} diff --git a/board/esd/du405/fpgadata.c b/board/esd/du405/fpgadata.c new file mode 100644 index 0000000..fd80d2c --- /dev/null +++ b/board/esd/du405/fpgadata.c @@ -0,0 +1,703 @@ + 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d, + 0x64,0x75,0x72,0x61,0x67,0x34,0x30,0x35,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b, + 0x73,0x32,0x30,0x78,0x6c,0x74,0x71,0x31,0x34,0x34,0x00,0x63,0x00,0x0b,0x32,0x30, + 0x30,0x32,0x2f,0x30,0x32,0x2f,0x32,0x31,0x00,0x64,0x00,0x09,0x31,0x32,0x3a,0x35, + 0x31,0x3a,0x30,0x38,0x00,0x65,0xe2,0x01,0x00,0x00,0x2b,0x98,0xff,0x30,0xe6,0xe5, + 0xe5,0x02,0x04,0x01,0xe6,0x04,0x01,0x0d,0x04,0x04,0x02,0x01,0x04,0x04,0x03,0x07, + 0x01,0x03,0x01,0x04,0x11,0x01,0x06,0x02,0x15,0x09,0x02,0x05,0x07,0x02,0x02,0x01, + 0x09,0x03,0x07,0x01,0x03,0x01,0x0b,0x05,0x03,0x01,0x07,0x08,0xe5,0xe5,0x24,0x05, + 0x09,0x11,0x01,0x03,0x03,0x05,0x0d,0x09,0x0b,0x09,0x01,0x1d,0x09,0x13,0x03,0x05, + 0x12,0xe6,0x11,0x01,0x03,0x02,0x02,0x03,0x03,0x01,0x15,0x01,0x02,0x28,0x01,0x05, + 0x02,0xe5,0xe5,0x02,0x02,0x02,0x0d,0x02,0x02,0x03,0x02,0xe5,0xe5,0x14,0x01,0x02, + 0xe5,0x12,0x0b,0x03,0x0f,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x06,0x02,0x09, + 0x06,0xe7,0x05,0x04,0x06,0x02,0x06,0x02,0x09,0x07,0xe6,0x08,0x09,0x07,0xe6,0x08, + 0x09,0x0e,0xe5,0xe6,0x0d,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x07,0x09,0xe5, + 0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0x03,0x05,0xe8,0x04,0xe6,0x02,0x05,0xe6,0xe5, + 0x04,0xe6,0x06,0x03,0x05,0xe5,0xe6,0x04,0xe5,0x07,0x09,0xe5,0xe6,0x04,0x09,0x09, + 0x09,0xe8,0x46,0x09,0x14,0xe5,0x06,0x0b,0x09,0x15,0x1d,0x24,0x02,0xe5,0xe5,0x45, + 0x08,0x15,0x33,0x1d,0x28,0x70,0xe5,0x09,0x09,0x14,0x42,0x02,0xe5,0x30,0x27,0x01, + 0x15,0x1b,0x1d,0x32,0x01,0x01,0x5b,0x0c,0x51,0x24,0x01,0xe5,0xe5,0x28,0xe5,0x1c, + 0x25,0x53,0x19,0xe5,0x01,0x2b,0x45,0x6c,0xe5,0xe6,0x35,0x09,0x07,0x01,0x09,0x09, + 0x12,0x63,0x09,0x02,0x03,0x0c,0x09,0x09,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x01, + 0x07,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x02,0xe5,0x02,0x0c, + 0x09,0x09,0x09,0x06,0x02,0x05,0xe5,0x01,0x07,0x01,0x05,0x03,0x07,0x01,0x09,0x0b, + 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe5,0x01,0x05,0x07,0xe5,0x05, + 0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x03,0x05,0xe5,0x07,0x09,0xe5,0x07,0x09,0xe5, + 0x07,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07, + 0xe5,0x07,0xe5,0x04,0x02,0xe5,0x12,0x04,0x0b,0x05,0x02,0xe5,0x07,0xe5,0x08,0x09, + 0x08,0xe5,0x08,0x09,0x09,0x09,0x06,0x03,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x07,0xe5, + 0x08,0x09,0x04,0x03,0xe5,0x08,0x09,0x0d,0x01,0xe6,0x05,0x06,0xe5,0x07,0xe5,0xe5, + 0x05,0xe5,0xe5,0x01,0x03,0xe5,0x14,0x06,0x09,0x13,0xe5,0x09,0xe5,0xe5,0x05,0xe5, + 0xe5,0x05,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0x07,0xe5,0x07,0xe5,0xe5, + 0x05,0xe5,0x07,0xe5,0x07,0x02,0x03,0xe8,0x0e,0x01,0x09,0x09,0x07,0x08,0xe5,0x07, + 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x01,0x0b,0x09,0x07,0x0b,0x09,0x07,0x09,0x13, + 0x09,0x0e,0x02,0xe5,0x0c,0x09,0x03,0x05,0x09,0x12,0x09,0xe5,0x08,0x13,0x09,0x01, + 0x09,0x09,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x09,0x10,0xe8,0x03,0x08,0x02,0x03, + 0x02,0x02,0x06,0x02,0x03,0x02,0x02,0x06,0x02,0x09,0x06,0x02,0x06,0x02,0x06,0x02, + 0x06,0x02,0x04,0x01,0x01,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0x06, + 0x02,0x06,0x02,0x06,0x02,0x03,0x02,0x02,0x06,0x02,0x0d,0x01,0x01,0x03,0xe5,0x09, + 0x09,0x09,0xe5,0x0f,0xe5,0x25,0x0b,0x04,0xe5,0x01,0x02,0x06,0x02,0x13,0x09,0x36, + 0x0d,0x23,0x35,0x82,0x01,0x03,0x10,0x09,0x02,0x06,0x11,0x09,0x1c,0xe5,0x0a,0x03, + 0xe6,0xe5,0x02,0x03,0x05,0x0d,0x05,0x03,0x05,0x17,0x27,0x02,0xe5,0x29,0x50,0x27, + 0x11,0x28,0xe5,0x01,0x10,0x09,0x09,0x09,0x09,0x04,0x04,0xe5,0x07,0xe5,0x07,0x09, + 0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,0xe7,0x0e,0xe5,0x02, + 0x02,0x02,0x06,0x02,0x10,0xe5,0xe5,0x38,0x1e,0x06,0x02,0x13,0x01,0xe5,0x2c,0xe6, + 0x17,0x09,0x06,0x09,0x01,0x10,0x19,0x24,0x13,0x13,0x02,0x11,0x16,0x05,0x02,0x03, + 0x01,0x10,0xe5,0x08,0x70,0x09,0x3f,0x01,0x02,0xe5,0x02,0x26,0x11,0x09,0x28,0x02, + 0x6c,0xe5,0xe5,0x13,0xca,0x02,0x0d,0x01,0x07,0x01,0x07,0x1d,0x01,0x04,0x0e,0x07, + 0x01,0x13,0x01,0x07,0xe6,0x10,0xe5,0x03,0x46,0x01,0x01,0x0d,0x01,0x07,0x02,0x03, + 0x05,0x1d,0x10,0x09,0x02,0x0e,0x02,0xe5,0x01,0x07,0x35,0x29,0xe6,0xe5,0x18,0x12, + 0xe5,0x10,0x08,0x1a,0x2c,0x09,0x43,0xe5,0xe6,0x14,0x01,0xe6,0x04,0x04,0x23,0x04, + 0x12,0x0b,0x09,0x63,0x03,0x02,0xe5,0x71,0x30,0x3c,0x01,0x17,0xe5,0xe5,0x29,0x35, + 0x5e,0x03,0x03,0x09,0x0f,0x0b,0x20,0x27,0x71,0x01,0x0f,0x04,0x03,0x05,0x02,0x01, + 0x04,0x09,0x09,0x32,0x02,0x65,0x01,0x03,0x01,0xe6,0x0d,0xe5,0x10,0x01,0x27,0x02, + 0x09,0x89,0x0e,0x03,0x33,0x03,0x03,0x29,0x03,0x04,0x2c,0x2f,0xe6,0xe7,0xd9,0xe7, + 0xe6,0x01,0x01,0x23,0xe5,0xae,0x01,0x03,0x02,0x04,0xd4,0x08,0x02,0xd8,0x03,0x01, + 0xe5,0x16,0x01,0x11,0x01,0xb2,0x01,0x01,0x15,0x01,0x01,0x0f,0x01,0x01,0xab,0x06, + 0x17,0x01,0x11,0x01,0xaf,0xe5,0xe5,0xe5,0x16,0x01,0x11,0x01,0xb1,0x02,0x4f,0xe5, + 0x86,0x06,0x01,0xe5,0x4f,0xe5,0x8b,0x03,0xe5,0x0d,0x09,0x09,0x09,0x09,0x09,0x06, + 0x02,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x02, + 0xe6,0x01,0x44,0xe5,0x91,0x03,0x01,0xe5,0x44,0x9a,0x01,0x0f,0x13,0x24,0xe5,0xe5, + 0x91,0xe5,0x01,0x0f,0xe5,0x11,0xe5,0x23,0x01,0xe5,0x92,0xe7,0x0d,0x13,0x25,0x01, + 0x91,0xe6,0x01,0x09,0x05,0x03,0xe7,0x05,0xe7,0x01,0x04,0xe6,0x05,0xe7,0x07,0xe5, + 0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07, + 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07, + 0x01,0xe5,0x0e,0x04,0x05,0x03,0x04,0x04,0x08,0x17,0x01,0x92,0x02,0xe5,0x0e,0x06, + 0x03,0x02,0x02,0x02,0x06,0x07,0x01,0x16,0x8b,0x05,0xe5,0x01,0xe6,0x0d,0x03,0x01, + 0x09,0x03,0x05,0x09,0x15,0x28,0x64,0x04,0xe7,0x01,0x03,0x0b,0x03,0xe7,0x02,0x02, + 0x01,0xe5,0x01,0x03,0xe7,0x02,0x03,0xe6,0x13,0x01,0x90,0x04,0xe5,0xd9,0x03,0xe5, + 0xe6,0x10,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x04,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01, + 0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01, + 0x0b,0xe7,0x4e,0x8e,0xe6,0xe6,0x12,0x3c,0x1e,0x0b,0x13,0x09,0x19,0x16,0x11,0xe9, + 0x03,0x19,0x32,0x0a,0x09,0x09,0xe5,0x4f,0x09,0x08,0xe5,0x01,0x08,0xe6,0x46,0x01, + 0x26,0x08,0x5d,0x08,0x4a,0xe5,0x01,0x22,0x37,0x03,0x0a,0x21,0x04,0xe5,0xe6,0x08, + 0x0b,0x03,0x15,0x40,0x3f,0x2d,0x02,0x0c,0x36,0x2d,0xe5,0x08,0x32,0xe5,0x2f,0xe5, + 0x45,0x28,0x01,0x3d,0x30,0xe6,0x04,0x04,0x66,0x01,0xe5,0x05,0x62,0xe8,0x70,0x03, + 0x68,0x03,0x72,0x01,0x3a,0x01,0x2c,0x01,0x01,0xb3,0x20,0x08,0xe5,0x02,0x05,0x6c, + 0x06,0x0c,0x2e,0x28,0x01,0xe6,0xe5,0xd9,0xe6,0xe5,0xe5,0xe5,0x01,0xd4,0x01,0x02, + 0x01,0x01,0x04,0xa7,0xe5,0x2a,0x04,0xe5,0xe6,0x01,0xa9,0xe5,0xe5,0x2a,0x02,0x02, + 0xe6,0x0a,0xa2,0x01,0x25,0x06,0x02,0xe5,0xe5,0x07,0xe6,0xa1,0x01,0x01,0x02,0x01, + 0x23,0x04,0xe5,0x4f,0x01,0x5c,0x01,0x2c,0x01,0x01,0xaf,0x01,0x2d,0xe8,0xe0,0xe0, + 0x01,0xe5,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09, + 0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x06,0xe5,0xe5,0xe5,0xd2,0x02,0x04,0x05,0xe5, + 0xd4,0x09,0x02,0x46,0x6a,0x2c,0x02,0xe5,0xae,0x01,0xe5,0x2a,0x01,0x01,0xe5,0xaf, + 0x2d,0xe5,0xe5,0x08,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe5,0xe7, + 0x4b,0xe5,0x27,0x3a,0x2c,0xe8,0x75,0x38,0x01,0x2d,0x01,0xe6,0xaf,0x2c,0x02,0xe5, + 0x02,0x48,0x29,0x38,0x01,0x2c,0xe5,0x01,0xaf,0x2d,0xe6,0xe6,0x09,0x06,0x01,0x01, + 0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01, + 0x01,0x05,0x01,0x07,0x01,0x02,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x03,0x07,0x02,0x4f,0x8f, + 0xe5,0xe6,0x12,0x15,0x13,0x08,0x08,0x57,0x0a,0x24,0x04,0x02,0x01,0x04,0xe5,0x04, + 0xe5,0x40,0x22,0x09,0x66,0x02,0xe6,0x02,0x68,0x13,0x4e,0x08,0xe7,0xe6,0xe5,0x6d, + 0x6f,0xe6,0x0a,0x23,0x32,0x09,0x03,0x10,0x5a,0x02,0xe7,0x08,0x0f,0x56,0x62,0x04, + 0x04,0xe5,0xe6,0x45,0x2a,0x6d,0x01,0xe6,0x6f,0x61,0x0a,0xe5,0x01,0x71,0x46,0x11, + 0x15,0x01,0x51,0x8c,0x03,0xe1,0xe5,0x0b,0x6a,0x67,0xe7,0xe5,0x4c,0xe5,0x8a,0x02, + 0x02,0x01,0x02,0x4b,0xe5,0x61,0x24,0x02,0x03,0xe6,0x03,0xa6,0xe5,0x01,0x01,0x22, + 0x01,0x02,0x06,0x01,0x02,0xa9,0xe5,0xe5,0xe5,0x21,0x06,0x06,0xe5,0x03,0xcf,0x02, + 0x04,0x01,0x01,0xe5,0xe5,0x02,0x04,0x01,0xa6,0x28,0x02,0xe5,0xe5,0x4f,0x5e,0x01, + 0x2f,0xe5,0x4f,0xe5,0x5c,0x01,0x2c,0x01,0xe7,0x03,0x4b,0x8b,0xe9,0xdd,0x01,0xe7, + 0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09, + 0x09,0x09,0x09,0x09,0x06,0x06,0x01,0xe7,0xd4,0x08,0x01,0x01,0xdf,0x02,0xdf,0x01, + 0xe5,0x4f,0x8a,0x02,0x01,0xe7,0xdd,0x01,0xe5,0x08,0x0b,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x05,0xe7,0xe5,0x4b,0xe5,0x8d,0x02,0xe7,0xdd,0x02,0xe6,0xdb,0x01,0xe7, + 0x02,0x48,0x09,0x87,0x01,0xe7,0x26,0xb6,0xe5,0xe5,0x10,0x01,0x01,0x05,0x01,0x07, + 0x01,0x06,0xe5,0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x02,0x06,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe5,0x0d,0x04,0x21,0x28,0x8a,0x03, + 0x02,0xe6,0x14,0x11,0x32,0x09,0x09,0x0b,0x50,0x10,0xe5,0xe7,0xe5,0x38,0x12,0x22, + 0xe5,0x64,0x06,0x02,0x04,0x03,0x68,0x6b,0x01,0xe8,0x01,0x6d,0x6e,0x01,0xe5,0x1a, + 0x14,0x3f,0x5d,0x0d,0xe5,0x01,0xe6,0x19,0x0b,0x49,0x32,0x0e,0x19,0x01,0x0f,0x02, + 0x0a,0x12,0x28,0x2a,0x30,0x27,0x05,0x01,0x0c,0xe8,0x33,0x01,0x39,0xe5,0x5f,0x0b, + 0x01,0xe5,0x2f,0x14,0x2b,0x6c,0x02,0xe5,0x2c,0x0b,0x38,0x45,0x26,0xe5,0xe5,0xe5, + 0x2a,0x1e,0x84,0x0c,0x01,0x01,0x2b,0xe5,0xa5,0x0b,0xe9,0x5a,0x7e,0x01,0x01,0x01, + 0x02,0x01,0x49,0x0e,0x7b,0x01,0x03,0xe5,0xe5,0x03,0x33,0x0b,0x18,0x01,0x74,0x01, + 0x02,0x04,0x02,0xe5,0x01,0x36,0x20,0xe5,0xe5,0xe5,0x73,0x06,0x02,0x03,0x5d,0x6f, + 0x01,0x05,0x07,0xe5,0x02,0x02,0x3f,0x09,0x10,0x03,0x6b,0x01,0x01,0x09,0x03,0xe5, + 0xe6,0x3a,0x01,0x03,0x09,0x10,0x01,0x6d,0x01,0x0d,0xe6,0xe6,0x3b,0x01,0x1e,0x01, + 0x6d,0x01,0x0f,0xe7,0x44,0x09,0x09,0x83,0xe5,0x02,0x39,0x08,0x03,0x01,0x03,0x03, + 0x01,0x09,0x81,0x02,0xe6,0x0d,0x09,0x09,0x04,0x01,0x02,0x09,0x09,0xe5,0x01,0x05, + 0xe5,0x01,0x02,0x02,0x04,0x01,0x02,0x02,0x06,0x0b,0x09,0x09,0x09,0x09,0x09,0x09, + 0x09,0x09,0x09,0x0d,0x01,0xe5,0xe5,0x01,0x27,0x0e,0xe5,0x13,0x0c,0x7e,0x02,0xe5, + 0x01,0x27,0x11,0x1f,0x86,0xe6,0xe5,0x27,0x02,0x0c,0x03,0x16,0x07,0x01,0x7e,0x02, + 0xe5,0x2c,0xe5,0x09,0x08,0x09,0x05,0xe5,0x01,0x06,0x01,0xe5,0x7c,0x02,0xe5,0x2c, + 0x1a,0x0a,0x01,0x07,0x01,0x7e,0xe8,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x09,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x06,0xe6,0xe5,0x2c,0x0a,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x82,0x01, + 0x2b,0x0c,0x06,0x01,0x07,0x01,0x07,0x01,0x09,0x7e,0x03,0x2d,0x27,0x07,0x14,0x6b, + 0x02,0xe5,0x2a,0x0e,0x18,0x0b,0x12,0x6b,0x01,0xe6,0x2e,0x27,0x08,0x04,0x7a,0xe6, + 0xe5,0x0e,0x01,0x01,0x05,0x01,0x07,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0xe6,0xe5, + 0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x02,0x02,0x27, + 0x02,0x0c,0xe5,0x0c,0x07,0x01,0x0c,0x82,0x01,0xe5,0x14,0x08,0x08,0x0c,0x01,0x02, + 0x03,0x09,0x09,0x0e,0x7b,0xe5,0x01,0xe5,0x08,0x20,0x06,0x1a,0x24,0x6f,0xe5,0x04, + 0x0a,0x09,0x09,0x06,0x01,0xe5,0x04,0x20,0x09,0xe5,0x0f,0x6d,0x01,0xe5,0x04,0x28, + 0x0b,0x03,0x09,0x14,0x13,0x6d,0x01,0xe5,0x01,0x06,0x21,0x05,0x08,0x18,0x19,0x15, + 0x5a,0x01,0xe6,0x04,0x0d,0x0d,0x2e,0x07,0x18,0x5a,0x11,0xe6,0xe5,0x09,0xe5,0x16, + 0x01,0x1d,0x02,0x06,0x0c,0x16,0x30,0x2f,0x0b,0xe5,0xe6,0x0c,0xe6,0x06,0xe6,0x05, + 0xe6,0x07,0x09,0x01,0x07,0xe5,0x03,0x2b,0xe5,0x5f,0xe5,0x04,0x04,0xe7,0x0e,0x0a, + 0x02,0x03,0x02,0x02,0x02,0xe5,0x12,0xe5,0x2f,0x6d,0x02,0x09,0x19,0x0d,0x05,0x1a, + 0x1f,0x45,0x26,0xe8,0x13,0xe5,0x0a,0x06,0x0d,0xe5,0x15,0x84,0x08,0xe9,0x34,0x01, + 0x17,0x8e,0x01,0x01,0xe6,0x07,0x01,0x04,0x02,0xe5,0x04,0x02,0xe5,0x04,0x02,0xe5, + 0x04,0x09,0x09,0x09,0x08,0xe5,0x11,0xe5,0x6f,0xe5,0x01,0x01,0x02,0x01,0x05,0xe5, + 0x03,0x02,0xe5,0x04,0x03,0xe5,0x06,0xe5,0x05,0x09,0x08,0x09,0x0a,0x13,0x06,0x66, + 0x01,0x02,0xe5,0xe6,0x03,0x0b,0x09,0x02,0xe5,0x03,0x01,0x08,0x06,0x01,0xe5,0x02, + 0xe5,0xe5,0xe6,0x02,0xe5,0xe5,0xe6,0x8b,0x04,0xe5,0xe6,0x01,0x17,0x02,0xe5,0x01, + 0x0c,0x03,0x02,0x01,0x04,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0xe5,0x8e,0x03,0x02,0x11, + 0xe5,0x08,0x04,0x04,0x09,0x02,0x05,0x05,0x01,0x01,0xe5,0x03,0x01,0x01,0xe5,0x22, + 0x6c,0x02,0x02,0x1e,0x01,0x01,0x02,0x01,0x0e,0x05,0x01,0x02,0x04,0x01,0x02,0x8c, + 0x03,0xe5,0xe6,0x0f,0x02,0x0c,0x06,0x08,0xe5,0x01,0x01,0x0e,0x01,0x11,0x09,0x78, + 0xe5,0xe5,0xe5,0x11,0x02,0x05,0xe7,0x01,0x01,0x01,0xe5,0xe6,0x04,0xe5,0xe5,0xe6, + 0xe5,0x02,0xe5,0x06,0x01,0x01,0x05,0xe6,0x08,0xe5,0x07,0xe5,0x77,0xe5,0x01,0x05, + 0x03,0x02,0x03,0x01,0x07,0x01,0xe5,0x05,0x01,0x02,0x04,0x01,0x13,0x09,0x0c,0x09, + 0x7a,0xe6,0x09,0xe5,0x03,0xe5,0x07,0xe5,0x01,0x01,0x03,0xe5,0x07,0xe5,0x08,0xa4, + 0x03,0xe5,0x0d,0xe6,0x06,0xe5,0x01,0xe5,0xe5,0x01,0xe5,0xe5,0x05,0xe5,0x07,0x09, + 0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x05, + 0xe6,0x02,0x02,0x0f,0x09,0x03,0x05,0x09,0x08,0xe5,0x08,0x09,0x86,0x05,0x04,0xe6, + 0xe5,0x18,0x01,0x07,0x09,0x09,0xa7,0xe5,0x0f,0xe6,0x02,0xe5,0x01,0x01,0x03,0x03, + 0x01,0x07,0xe6,0x05,0x02,0x04,0x04,0x04,0x04,0x04,0x01,0x07,0x01,0x7c,0x01,0xe6, + 0xe5,0x10,0x02,0x04,0xe6,0x01,0x02,0x02,0xe5,0x01,0x06,0x02,0x04,0xe6,0x01,0x04, + 0x01,0x02,0x04,0x01,0x05,0x01,0xe5,0x05,0x01,0xe5,0x7d,0xe5,0xe6,0x07,0x09,0x09, + 0x10,0x08,0x07,0x09,0x09,0x01,0x07,0x01,0x0d,0x70,0x01,0xe6,0x0f,0x02,0xe5,0xe5, + 0x05,0xe5,0xe6,0x04,0xe5,0xe5,0x05,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0x01,0x04,0x01, + 0x02,0x04,0xe7,0xe5,0x03,0xe7,0xe5,0x02,0xe5,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x06,0x01,0x01,0x10,0x06,0x01,0xe6,0x04,0x02,0xe5,0x07,0xe5,0x06,0xe5,0x01,0xe5, + 0x01,0x09,0x0c,0xe5,0x01,0x05,0xe5,0xe5,0x7a,0xe5,0xe5,0x12,0x02,0xe5,0xe5,0x02, + 0x02,0x02,0x04,0x01,0x06,0x02,0x02,0xe5,0x04,0x02,0x06,0x02,0x06,0x09,0x07,0x01, + 0x77,0xe5,0xe6,0x0f,0xe5,0x01,0xe6,0x01,0x01,0x02,0xe7,0xe5,0xe5,0xe5,0xe6,0x03, + 0x02,0xe6,0x01,0x05,0xe6,0x05,0xe7,0x05,0x01,0x09,0x08,0xe5,0x0a,0x6b,0x01,0xe6, + 0x12,0x03,0x05,0x03,0x01,0x04,0x08,0x05,0x02,0x01,0x04,0x02,0xe6,0x03,0x02,0x01, + 0x05,0x03,0x05,0x02,0xe5,0x0c,0x6c,0xe8,0x1f,0x02,0x0a,0xa5,0x07,0x02,0x01,0x0b, + 0x05,0x01,0x07,0x01,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01, + 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0xe5,0xe5,0x05,0x01,0x02,0x04,0x01, + 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x03,0x08,0x01,0x0f,0xe5,0xe5,0x05,0xe5,0x04,0xe5,0xe5,0x02,0x05,0x09,0xe5,0x15, + 0x05,0xe5,0x03,0x0d,0xe5,0x72,0xe5,0xe7,0x0b,0x01,0x06,0xe5,0xe5,0x02,0x0a,0x0c, + 0x01,0x04,0x17,0x05,0x71,0x10,0xe5,0x02,0x22,0x07,0x01,0x03,0x09,0x02,0x05,0x02, + 0x06,0x07,0x11,0x01,0x07,0x6d,0x02,0xe5,0xe5,0x13,0x01,0x07,0xe5,0x0b,0x03,0x0e, + 0x09,0x05,0xe5,0x01,0x06,0x14,0x65,0x04,0x01,0x02,0x17,0x01,0x02,0x02,0x09,0x25, + 0x06,0x09,0x10,0x08,0x65,0xe7,0x1b,0x04,0xe5,0x0b,0x07,0x08,0x09,0x03,0x06,0x01, + 0x12,0xe5,0x32,0x30,0x0b,0x01,0xe7,0x10,0xe5,0x0d,0x01,0x1b,0xe5,0x06,0xe5,0x11, + 0x05,0x0e,0xe5,0x02,0x13,0x55,0x01,0x3f,0x03,0x02,0x04,0xe5,0x23,0x30,0x2f,0x0b, + 0xe5,0x01,0x05,0x10,0x09,0x05,0x03,0x13,0x09,0x07,0x01,0x09,0x10,0x03,0x6c,0x02, + 0xe5,0x33,0x1c,0x1f,0x6c,0xe6,0xe6,0x14,0x23,0x04,0x01,0x01,0x0b,0x03,0x01,0x05, + 0x5c,0x21,0x02,0xe5,0x01,0xe5,0x16,0x01,0x01,0xe5,0x06,0x20,0x05,0x09,0xe6,0x15, + 0x71,0xe6,0x4a,0x09,0x84,0x05,0x01,0x01,0x15,0x09,0x0c,0x0a,0xe5,0xe6,0xe5,0x01, + 0xe5,0x01,0xe5,0x0a,0x02,0x01,0x1a,0x06,0x01,0x03,0xe5,0x59,0x05,0x01,0x1f,0x09, + 0xe5,0x0b,0x02,0xe5,0xe7,0x03,0xe5,0x01,0xe5,0x06,0xe6,0x1c,0x05,0xe5,0x5d,0x02, + 0x03,0xe6,0x02,0xe5,0x11,0x01,0x04,0xe5,0x05,0x06,0x0a,0x02,0xe5,0x01,0x03,0x02, + 0xe5,0x02,0x03,0xe5,0x01,0x01,0x1d,0x0d,0x52,0x01,0x02,0x05,0x02,0xe5,0xe5,0x13, + 0x06,0x0c,0x13,0x09,0x01,0x07,0x1f,0x60,0x06,0x03,0xe8,0x15,0x02,0x04,0x01,0x02, + 0x08,0x04,0x01,0x04,0xe5,0x03,0x01,0x09,0x03,0x02,0xe5,0xe5,0x1c,0x61,0x07,0x04, + 0xe6,0x1b,0x01,0xe5,0x08,0x03,0x01,0x02,0x0a,0x01,0x01,0x07,0x01,0x04,0xe5,0xe5, + 0xe5,0xe5,0x01,0x16,0x03,0x64,0x02,0x01,0xe5,0x16,0x01,0x07,0x01,0x04,0x04,0x0b, + 0x05,0x01,0x07,0x01,0x05,0x01,0x01,0x03,0xe5,0x07,0xe5,0x0d,0x64,0x05,0x01,0xe7, + 0x15,0x02,0x02,0xe5,0x01,0x01,0xe5,0x02,0xe7,0x05,0x01,0x05,0x01,0x01,0xe5,0xe5, + 0x08,0x07,0x05,0xe5,0x07,0xe5,0x0d,0x6b,0xe7,0x04,0x17,0x02,0x06,0xe5,0x10,0x0a, + 0x13,0x02,0x06,0x02,0x76,0xe5,0x02,0x1e,0x1b,0x0b,0xe6,0x06,0xe5,0x11,0xe5,0x1d, + 0x59,0x01,0xe7,0x0d,0x09,0xe5,0x01,0x05,0xe5,0x07,0x09,0x06,0x02,0x09,0x06,0x02, + 0x09,0x09,0x0b,0x09,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x06, + 0x04,0x20,0x1a,0x13,0x86,0x07,0xe8,0x1e,0xb5,0x08,0xe8,0x16,0x01,0xe6,0x04,0x01, + 0xe6,0x18,0x01,0x07,0x01,0x09,0x26,0x61,0x01,0xe6,0x16,0x01,0x07,0x01,0x15,0x04, + 0xe5,0xe6,0x05,0x01,0xe5,0x08,0x03,0x05,0x1f,0x5d,0xe5,0x01,0xe5,0x17,0x01,0x07, + 0x01,0x19,0x01,0x07,0x09,0x08,0x20,0x01,0x5d,0xe9,0x08,0x0b,0xe5,0x01,0x05,0xe6, + 0x06,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe6,0x06,0xe6,0x04,0x01,0xe5,0x07,0xe5, + 0x05,0xe6,0x09,0xe5,0xe5,0xe5,0x03,0xe5,0x08,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x02,0xe5,0x20,0x1d,0x01, + 0x07,0x01,0x05,0x01,0x01,0x05,0x04,0xe5,0x0c,0x0a,0x02,0x01,0x19,0x09,0x3a,0x01, + 0x01,0x23,0x1b,0x01,0x07,0x01,0x07,0x01,0x1a,0x0b,0xe5,0xe5,0x05,0x57,0xe8,0x18, + 0x25,0x01,0x09,0x05,0x07,0x01,0x01,0x01,0x0d,0xe6,0x01,0x0a,0x01,0x04,0x12,0x01, + 0x07,0x01,0x3b,0xe7,0x18,0x20,0x04,0x0b,0xe5,0x01,0x09,0x03,0x01,0xe5,0x0b,0xe5, + 0x02,0x0a,0x01,0x17,0x09,0x3c,0x03,0xe5,0x01,0x15,0xe5,0x02,0x04,0xe5,0x19,0x09, + 0x01,0xe5,0x08,0x1c,0x69,0x01,0xe7,0x0b,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x04,0x02,0x01,0xe5,0xe6,0x02,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01, + 0x06,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x0b,0xe5,0xe5,0x12,0x08,0x0d,0x0c,0xe5,0x15,0x01,0xe6, + 0x8d,0xe5,0x14,0x06,0x15,0x02,0x05,0x1d,0x01,0x31,0x28,0x25,0x03,0xe5,0x1b,0x1a, + 0x0b,0x0a,0x03,0x09,0x09,0x09,0xe5,0x09,0x09,0x09,0x09,0x44,0xe7,0x03,0xe5,0x12, + 0x09,0x1b,0x04,0x04,0x02,0x04,0x03,0x03,0x03,0x01,0x0e,0x02,0x0b,0x3f,0x1f,0x01, + 0xe8,0x03,0x2a,0x09,0x03,0x02,0x0a,0x01,0x04,0x05,0x05,0x11,0x0e,0x5d,0x01,0xe7, + 0x01,0x05,0x06,0x06,0x09,0x01,0x01,0xe5,0x0a,0x08,0x0e,0xe5,0x10,0x0b,0x08,0x0d, + 0x1b,0xe5,0x1c,0x21,0xe5,0xe8,0x03,0x1b,0x1d,0x01,0x07,0x1d,0x09,0x22,0x24,0x25, + 0x02,0x23,0xe5,0xe5,0x16,0x04,0x02,0x04,0x15,0x07,0xe5,0x05,0x47,0x02,0x23,0x01, + 0xe5,0x1a,0x0a,0x25,0x23,0x31,0x31,0x02,0x05,0x03,0x15,0x1d,0x23,0x09,0x0f,0xe5, + 0x1a,0x27,0x13,0x13,0xe8,0x19,0x26,0x09,0x01,0x11,0xe5,0x39,0x01,0x1a,0x07,0x21, + 0x1c,0x02,0x08,0x18,0x08,0xe6,0x1f,0x2f,0x41,0x02,0x3f,0x01,0x09,0x0e,0x02,0x10, + 0x2d,0x2d,0x13,0xea,0x17,0xe5,0x0b,0x01,0x14,0x02,0xe5,0x01,0x01,0x05,0x0e,0x3d, + 0x19,0xe5,0x24,0x01,0x02,0xe5,0x01,0x01,0x16,0x0b,0xe5,0x10,0x01,0x01,0x01,0xe5, + 0x02,0xe5,0x02,0xe5,0x11,0x03,0x09,0x2e,0xe6,0x17,0x01,0x20,0x02,0x03,0xe6,0x03, + 0x36,0xe5,0x01,0x01,0x01,0x07,0xe5,0x12,0x3a,0x01,0x1e,0x17,0x01,0x02,0x04,0x01, + 0x01,0x02,0x3c,0x01,0x09,0x01,0x0c,0xe5,0x3e,0x01,0x1f,0x16,0x06,0x02,0x01,0xe6, + 0x20,0x01,0x1b,0x01,0x06,0xe5,0xe6,0xe5,0x0d,0x01,0xe8,0x01,0xe5,0xe5,0x32,0x1b, + 0x1b,0x07,0x01,0x01,0xe5,0xe5,0x1e,0x01,0x01,0x12,0x06,0x01,0x01,0x03,0xe6,0xe6, + 0xe5,0x11,0xe5,0xe5,0xe6,0xe5,0xe5,0x30,0x01,0x19,0x03,0x1a,0x03,0x01,0x01,0xe6, + 0x20,0x01,0x14,0x06,0x01,0x05,0x01,0x01,0xe5,0x16,0x01,0xe5,0xe5,0x32,0x1b,0x06, + 0x01,0x1c,0x02,0x21,0x01,0x1b,0x01,0x07,0x01,0xe5,0x12,0x03,0x01,0xe5,0xe5,0x32, + 0x1b,0xe5,0x03,0xe5,0x1e,0xe6,0x04,0x17,0x02,0x2d,0x13,0xe5,0x01,0x57,0x1e,0x01, + 0x02,0x38,0x0d,0xe5,0x03,0xe6,0x11,0x02,0x59,0x1f,0xe5,0x01,0xe5,0x0d,0x09,0x09, + 0x02,0x06,0x09,0xe5,0x04,0x02,0x09,0xe5,0xe5,0x05,0x09,0x01,0x03,0x03,0x0b,0x09, + 0x09,0x09,0x09,0x02,0x06,0x09,0x09,0x09,0x09,0x0d,0x02,0x01,0x02,0x3a,0xe5,0x0d, + 0xe5,0x0c,0x05,0x73,0x08,0xe7,0x3a,0x11,0x0b,0x79,0x0a,0x01,0x01,0x21,0x01,0x07, + 0x01,0x06,0xe5,0x08,0x09,0x01,0x01,0x0f,0x3c,0xe5,0x1c,0x01,0xe6,0x1f,0xe5,0x01, + 0x1a,0x06,0x01,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x08,0x06,0x01,0xe6,0x0b,0x04,0x01, + 0x39,0x02,0x19,0xe5,0xe5,0xe5,0x20,0x01,0xe5,0x16,0x01,0x07,0x01,0x07,0x01,0x07, + 0x08,0x09,0xe5,0xe5,0x16,0x37,0x1d,0x01,0x03,0x1d,0xe5,0xe8,0x13,0x01,0x01,0x03, + 0xe6,0xe5,0xe5,0x02,0x01,0x01,0x01,0x03,0xe6,0x02,0x05,0xe5,0x07,0xe6,0xe6,0x03, + 0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe6, + 0x06,0xe5,0x07,0xe5,0x07,0xe6,0xe6,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x02,0xe5, + 0x14,0x07,0x01,0x07,0x01,0x07,0x01,0x17,0xe5,0x0f,0x3d,0x1f,0xe6,0x20,0xe7,0x08, + 0x0c,0x09,0x09,0x07,0x01,0x16,0xe5,0x11,0x3b,0x1d,0x28,0xe5,0x13,0x01,0x01,0x04, + 0xe5,0x08,0x09,0x17,0x11,0x14,0x28,0x1f,0x23,0x02,0x03,0x0f,0x03,0x01,0x03,0xe5, + 0x07,0x06,0x02,0xe5,0x17,0x02,0x0e,0x01,0x02,0x38,0x1d,0x04,0x1f,0x01,0x01,0xe5, + 0x3d,0xe5,0xe5,0x05,0x02,0x10,0x02,0xe5,0x38,0x01,0xe5,0x19,0x01,0xe5,0x1f,0x04, + 0x0a,0x06,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x07,0x01,0x04,0x02, + 0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x01,0x02,0x04,0x01,0x04,0x04,0x01,0x07,0x01, + 0x07,0x01,0xe5,0x05,0x01,0x04,0x02,0x01,0x07,0x01,0x01,0x05,0x01,0x04,0x02,0x01, + 0x07,0x01,0x02,0x04,0x01,0x0a,0x02,0xe5,0x12,0x05,0xe5,0x01,0x20,0x0a,0xe8,0xe5, + 0x0a,0x01,0x01,0xe6,0x35,0x1b,0x06,0xe5,0x21,0xe5,0xe6,0x09,0x0a,0x09,0x3c,0x14, + 0x4c,0xe5,0x1b,0x04,0x03,0x12,0xe5,0xe5,0x01,0x03,0x09,0x05,0x03,0x14,0x01,0x02, + 0x0d,0x01,0x12,0x41,0x05,0x01,0x22,0xe5,0x01,0x04,0x1c,0xe6,0x03,0x02,0x09,0x01, + 0x05,0x01,0x02,0x08,0xe5,0x08,0x0d,0x09,0x03,0x44,0x01,0x1e,0x04,0xe5,0xe8,0x01, + 0x0f,0x0e,0x0a,0x05,0x04,0x02,0x06,0x07,0x10,0x07,0x0d,0x4a,0x1b,0x05,0xe5,0x01, + 0xe5,0x07,0x13,0x09,0x06,0x06,0x02,0x1d,0x08,0x0d,0x03,0x12,0x2b,0xe5,0x0b,0x05, + 0xe5,0x15,0xeb,0x10,0x08,0x22,0x0d,0x04,0x0a,0x05,0x0e,0x04,0x0c,0x06,0x05,0x0d, + 0x13,0x10,0x01,0xe5,0x04,0x0b,0x05,0xe5,0x01,0x1c,0x09,0x12,0x0c,0x19,0x05,0x0a, + 0x44,0x1d,0x0d,0xe5,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x0e,0x04,0x01,0x1c,0x02, + 0xe5,0x03,0x09,0x03,0xe5,0x4f,0xe5,0x19,0xe7,0x0f,0x02,0x06,0x09,0x11,0x0c,0x0a, + 0x11,0x10,0xe5,0x52,0x18,0xe5,0xe5,0x01,0x0b,0x09,0x09,0x0a,0x29,0x06,0x01,0x14, + 0x2d,0x0b,0x01,0x12,0x1a,0x02,0x2b,0xe6,0x21,0x0f,0x03,0x0d,0xe5,0xe5,0x2b,0x0e, + 0x09,0x23,0xe5,0xe5,0x3a,0x25,0x01,0x02,0x0c,0x3c,0x0a,0x22,0x01,0x01,0xe6,0x07, + 0xe5,0x05,0x09,0x04,0x04,0x04,0x24,0xe5,0x89,0xe6,0x01,0xe5,0x01,0x01,0x04,0xe5, + 0x0b,0xe5,0x07,0x09,0x46,0x3c,0xe6,0x10,0xe5,0x11,0x01,0x01,0x02,0xe8,0x03,0x0f, + 0x02,0x06,0x04,0x07,0x06,0xe5,0xe5,0xe5,0x21,0xe5,0x02,0x02,0x4c,0x04,0x06,0x02, + 0x06,0x11,0x01,0x07,0xe5,0x01,0x11,0x01,0x02,0x04,0x01,0x02,0x07,0x06,0xe5,0xe5, + 0xe5,0x21,0xe5,0x4f,0x02,0x06,0x0c,0x17,0x02,0x02,0xe5,0x11,0x01,0x01,0x02,0x02, + 0xe5,0x01,0xe5,0x03,0x04,0x09,0x01,0x02,0x24,0x02,0x01,0x01,0x0b,0x3a,0x08,0xe6, + 0x05,0x02,0xe5,0xe5,0x01,0x01,0x01,0x12,0x01,0xe5,0x01,0x13,0xe5,0x03,0x04,0x04, + 0x04,0x03,0x05,0x01,0x02,0x24,0x01,0xe6,0x01,0x48,0x01,0x01,0x01,0x02,0x04,0x05, + 0x01,0x02,0x01,0x01,0x0b,0x02,0x03,0xe8,0x03,0x0b,0xe5,0x01,0x01,0x0b,0x07,0x0f, + 0xe5,0x71,0x01,0x09,0x07,0x01,0x17,0xe6,0xe6,0x18,0x09,0x07,0x0e,0x24,0x4f,0x13, + 0x01,0x18,0x02,0xe5,0x0c,0x04,0x04,0x04,0xe5,0x07,0xe5,0x11,0x27,0x65,0xe6,0x0c, + 0x07,0xe6,0x09,0x12,0xe5,0x07,0xe5,0x3a,0x51,0x09,0x07,0x01,0x14,0xe5,0xe6,0x09, + 0x03,0x07,0x01,0x07,0x01,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,0x0b,0x09,0x09, + 0x09,0x09,0x09,0x09,0x05,0xe5,0x01,0x03,0x05,0x03,0x05,0x06,0x06,0x02,0x01,0x02, + 0x14,0x01,0x02,0x04,0x01,0x02,0x13,0x27,0x54,0xe5,0x1b,0xe5,0x03,0x02,0x01,0xe6, + 0x19,0x09,0x92,0x1c,0x0a,0x01,0xe5,0xe5,0x2a,0x07,0x04,0x04,0x01,0x07,0x01,0x0e, + 0x1a,0x39,0x01,0x06,0x0a,0x01,0x16,0x03,0x01,0x0c,0x03,0xe5,0x08,0x09,0x07,0xe5, + 0x02,0x04,0x01,0x05,0x01,0xe5,0x05,0x01,0xe5,0x12,0xe5,0x12,0xe5,0x37,0x01,0xe5, + 0x08,0x06,0x01,0xe6,0x17,0x01,0x17,0x01,0x07,0x01,0x09,0x07,0x09,0x01,0x07,0x01, + 0x10,0xe5,0x11,0x04,0x38,0x02,0x09,0x07,0x01,0x03,0x14,0xe5,0x01,0x13,0x01,0x01, + 0x01,0x03,0x01,0x01,0x01,0x04,0xe5,0x02,0x03,0xe6,0x02,0x04,0x01,0xe5,0xe5,0x02, + 0xe5,0xe6,0xe5,0x03,0xe6,0x06,0xe6,0x08,0x08,0xe5,0x03,0x05,0xe5,0x07,0xe5,0x07, + 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07, + 0xe5,0x06,0xe5,0xe6,0x0c,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x03,0x03,0xe6, + 0xe5,0x0f,0x09,0x0e,0x15,0x39,0x01,0x11,0x01,0x18,0xe5,0xe6,0x0c,0x01,0x06,0xe5, + 0xe5,0x05,0xe5,0xe5,0x05,0x02,0x06,0x02,0x06,0x09,0x09,0x07,0x01,0x09,0x0e,0x39, + 0x01,0x11,0x01,0x1b,0xe5,0x0c,0x01,0x03,0x01,0x07,0x01,0x08,0xe5,0x02,0x05,0x01, + 0x06,0xe6,0x05,0x01,0xe5,0x08,0x09,0x04,0x03,0xe5,0x0a,0x02,0x3b,0x15,0x18,0x01, + 0x04,0x08,0x01,0x02,0xe6,0x06,0xe6,0x06,0xe6,0x03,0x03,0x05,0x02,0xe6,0x07,0xe5, + 0x08,0x05,0x03,0x08,0xe5,0x0c,0x02,0x3b,0x29,0x03,0x02,0xe5,0x02,0x1e,0xe5,0x06, + 0x01,0x2e,0x02,0x4e,0x01,0xe5,0x05,0x03,0x1f,0xe5,0x02,0x03,0x05,0x07,0x01,0x01, + 0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x01,0x05,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01, + 0x05,0x01,0x07,0x01,0x04,0x02,0x01,0x02,0xe5,0x02,0xe6,0x06,0x01,0x07,0x01,0x0e, + 0x08,0x12,0x09,0x02,0x26,0x01,0x0b,0xe5,0x01,0x01,0x72,0x07,0x03,0xe5,0x14,0x05, + 0x02,0x09,0x0a,0x13,0x47,0x1b,0x0a,0x25,0x01,0xe5,0xe5,0xe5,0x0d,0xe5,0x03,0x03, + 0x05,0x09,0x05,0x1c,0xe5,0x21,0x27,0x05,0x3f,0xe5,0xe6,0x0b,0x01,0x07,0xe5,0x09, + 0x1b,0x02,0x06,0x02,0x03,0x01,0x05,0xe5,0x04,0x0e,0x33,0x13,0x02,0x09,0xe6,0x16, + 0xe5,0x02,0x0a,0x02,0x02,0x01,0x08,0x25,0x09,0x0c,0x0b,0xe5,0x0a,0x31,0x18,0x21, + 0xe9,0x07,0x17,0x02,0x16,0x05,0x09,0x02,0x07,0x06,0x1a,0x32,0x09,0x06,0x06,0x0e, + 0x0a,0x02,0x01,0x04,0x07,0x2b,0x06,0xe5,0x03,0x03,0x13,0x02,0x10,0x3d,0x01,0x30, + 0x39,0x05,0x09,0x02,0x0b,0x06,0x11,0xe5,0x4a,0x15,0x09,0x02,0xe5,0x07,0x01,0x05, + 0x02,0x10,0x19,0x07,0x01,0x01,0x07,0x09,0x0a,0xe5,0x03,0x03,0x3d,0xe6,0x14,0xe5, + 0x15,0x01,0xe5,0x13,0x13,0x08,0x1a,0x0c,0x0f,0x07,0x40,0x2c,0xe8,0x0d,0x22,0x09, + 0x02,0x01,0x1b,0x01,0x08,0x03,0x0a,0x39,0x09,0xe5,0x1f,0x03,0xe5,0x0e,0x0a,0x0c, + 0x2a,0x0c,0x03,0x0e,0x3e,0x06,0x02,0x22,0x02,0xe5,0x0c,0x01,0x4f,0x01,0x4d,0x01, + 0x07,0xe5,0x1c,0x08,0xe5,0xe5,0x0a,0x10,0xe5,0x0d,0x03,0x01,0x03,0xe5,0x07,0xe5, + 0x01,0xe5,0xe5,0x01,0xe6,0x1a,0xe6,0xe5,0xe5,0x44,0x01,0x04,0x1e,0x01,0x03,0x01, + 0x02,0x08,0x22,0x01,0xe5,0x0a,0xe6,0xe5,0x04,0xe6,0x17,0x01,0x03,0x03,0x01,0x45, + 0xe5,0x20,0x02,0x02,0xe7,0x03,0x08,0x1d,0x01,0x0b,0x02,0x01,0x06,0xe5,0x01,0x01, + 0x01,0x0c,0xe5,0x3b,0x01,0xe5,0xe5,0x03,0x01,0x07,0xe5,0xe5,0xe5,0x09,0xe5,0x1a, + 0x07,0xe5,0x01,0x0a,0x1a,0xe5,0xe5,0xe5,0x10,0x01,0x09,0x0e,0x3d,0xe5,0xe5,0xe5, + 0x08,0x04,0x02,0x0d,0x15,0xe5,0x05,0x02,0xe5,0xe7,0x08,0x01,0xe5,0x30,0x01,0x07, + 0x01,0x04,0x01,0x08,0x03,0xe5,0x46,0x02,0x01,0xe6,0xe6,0x04,0x24,0x01,0x02,0x02, + 0x0a,0x03,0x1d,0x0f,0x01,0x01,0x01,0x02,0x02,0x01,0x04,0x13,0x38,0x0c,0x01,0xe5, + 0x05,0xe6,0x21,0x02,0xe9,0x0b,0x05,0xe5,0x15,0x01,0x04,0x01,0x0a,0x01,0x02,0x04, + 0x01,0x05,0x08,0x01,0x08,0x35,0x01,0x11,0x01,0x2b,0xe7,0xe5,0x0c,0x06,0x16,0x01, + 0x11,0x01,0x07,0x01,0x4f,0x01,0x09,0xe5,0x05,0x02,0x0b,0x1f,0xe5,0x01,0xe5,0x13, + 0x39,0x13,0x02,0x41,0x09,0x02,0x02,0x05,0x18,0xe5,0x03,0x02,0x01,0x50,0x01,0x11, + 0x47,0x09,0x21,0x05,0x03,0xe5,0x0d,0x09,0x09,0x09,0x09,0x09,0x02,0x06,0x05,0x03, + 0x06,0x02,0x03,0x05,0x0b,0x09,0x09,0x09,0x09,0x09,0xe5,0x03,0x03,0xe5,0x01,0xe5, + 0xe5,0x01,0x09,0x09,0x0b,0x01,0x01,0x01,0xe5,0x58,0x02,0x47,0x09,0x0f,0x1f,0xe5, + 0x01,0x5b,0x45,0x0b,0x30,0xe5,0x01,0x0f,0x07,0x01,0x25,0x01,0x06,0xe5,0xe5,0x13, + 0x05,0xe5,0xe5,0x30,0x01,0x07,0x02,0x09,0xe5,0x01,0x02,0x01,0x02,0x22,0xe5,0x0e, + 0xe5,0x05,0x01,0xe5,0x22,0xe5,0xe6,0x05,0x01,0xe5,0x19,0x01,0xe5,0x2f,0x01,0xe5, + 0x07,0x0e,0x02,0x01,0x01,0x21,0x01,0xe5,0x0e,0x07,0x01,0x17,0x0d,0x01,0x25,0x01, + 0x31,0x01,0x14,0x06,0x01,0x03,0x1d,0x03,0xe6,0x0d,0x03,0xe8,0xe5,0x02,0xe5,0xe5, + 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x05,0x01,0xe5,0x07,0xe5, + 0x01,0x05,0xe6,0xe5,0x02,0xe6,0x09,0xe5,0x07,0xe5,0x08,0xe5,0x06,0xe7,0xe5,0x02, + 0x01,0xe5,0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x02,0x0f, + 0xe6,0x01,0x09,0x13,0x0c,0x09,0x01,0xe5,0x03,0x04,0xe5,0x02,0x13,0x29,0xe5,0x05, + 0x01,0x15,0x01,0x23,0x02,0x0f,0x03,0x02,0x09,0x07,0x01,0x09,0x0a,0x09,0x01,0xe5, + 0x1f,0x02,0x09,0x01,0x09,0x34,0x22,0xe8,0x0e,0x05,0x07,0x01,0xe5,0x05,0x01,0xe5, + 0x05,0x01,0xe5,0x09,0x09,0x01,0x03,0x01,0x09,0x12,0xe5,0x01,0x11,0x13,0xe5,0x08, + 0x0b,0x09,0x01,0x23,0x01,0xe5,0x0b,0x02,0xe5,0x01,0xe7,0x05,0xe5,0x04,0x02,0xe5, + 0x07,0x0d,0x09,0x01,0xe5,0x01,0x06,0x02,0x10,0x02,0x08,0x03,0x09,0x12,0xe5,0x07, + 0x19,0x02,0x1f,0x03,0xe5,0x0b,0xe5,0xe5,0x27,0x05,0x06,0x02,0x13,0x02,0x44,0x01, + 0xe5,0x06,0x01,0x04,0x05,0x21,0x01,0xe5,0x10,0x01,0x02,0x04,0x01,0x07,0x01,0x07, + 0x01,0x01,0x05,0x01,0x03,0x03,0x01,0x01,0x05,0x01,0x02,0x04,0x01,0x01,0x05,0xe6, + 0x06,0x01,0x01,0x02,0x04,0x01,0xe6,0x04,0x01,0xe5,0x05,0x01,0xe6,0x04,0x01,0x07, + 0x01,0xe5,0x02,0x02,0x01,0xe6,0x04,0x01,0xe5,0xe5,0x03,0x01,0x07,0x01,0x07,0x01, + 0x0a,0xe5,0x01,0x0e,0x11,0x20,0x08,0x04,0x0d,0xe5,0x38,0x09,0x04,0xe5,0x0b,0x05, + 0xe5,0x20,0x02,0xe6,0x0a,0x1c,0x04,0x0e,0x05,0x04,0x27,0x01,0x11,0x14,0x05,0x0d, + 0x0a,0x01,0x07,0x1a,0x01,0xe7,0x01,0x19,0x23,0x02,0x0e,0x09,0x09,0x09,0xe5,0x09, + 0x09,0x09,0x09,0x0a,0x01,0x01,0x11,0x22,0x01,0x01,0x0a,0x0c,0xe6,0x1f,0x09,0x06, + 0x04,0xe5,0x0c,0x07,0xe6,0xe5,0x2e,0x02,0x06,0x02,0x06,0xe7,0x05,0x01,0x0d,0x15, + 0x01,0xe5,0x07,0x0e,0x21,0x10,0x12,0x09,0x09,0x2b,0x0a,0x06,0x0b,0x21,0x01,0x01, + 0xe5,0x08,0x09,0x09,0x09,0x1d,0x0e,0xe5,0x0c,0x09,0xe5,0x01,0x06,0x23,0xe5,0x03, + 0xe5,0x03,0x08,0x04,0x02,0x04,0xe5,0x08,0x13,0xe7,0xe5,0x08,0x0c,0x03,0x13,0x0b, + 0x07,0x09,0xe5,0x09,0x07,0x10,0x24,0x04,0x04,0x04,0x0e,0x04,0x01,0x0a,0x16,0x01, + 0xe7,0x3d,0x0e,0xe6,0x06,0x15,0x03,0xe5,0x29,0x09,0x0a,0x05,0x05,0x13,0x01,0x03, + 0x09,0x06,0x01,0x0a,0x0c,0x08,0xe5,0x07,0xe5,0x1e,0x0c,0x0f,0x29,0xe5,0x07,0xe5, + 0x07,0xe5,0x05,0x20,0x04,0x02,0xe6,0x02,0x1a,0x09,0x09,0x15,0x0b,0x03,0x0b,0x0c, + 0x29,0x01,0x07,0x01,0x01,0x02,0x02,0x01,0x01,0x24,0x06,0x02,0x35,0x01,0x1a,0xe5, + 0xe5,0x04,0x1d,0x09,0x09,0x0b,0x03,0x02,0xe5,0x06,0x01,0x09,0x05,0x1e,0x06,0xe6, + 0x19,0x1d,0x0d,0x04,0xe5,0x02,0x03,0xe5,0x16,0x2d,0xe5,0x08,0x10,0x02,0xe5,0x22, + 0xe6,0x53,0x18,0x2f,0x09,0x11,0x01,0x1e,0x03,0xe5,0x01,0x01,0x26,0xe5,0x03,0xe5, + 0x01,0xe5,0x03,0x03,0x01,0x0a,0x02,0x09,0xe5,0x0e,0x37,0xe5,0x03,0x09,0x06,0x01, + 0x04,0xe5,0x19,0x02,0x03,0xe7,0xe5,0xe5,0x22,0x01,0x07,0xe5,0xe5,0x05,0x01,0xe7, + 0x06,0x06,0x01,0xe5,0x12,0x33,0x03,0xe5,0x04,0x08,0xe6,0x03,0x01,0x02,0x01,0x1d, + 0x02,0x01,0xe6,0x03,0x0f,0x01,0xe5,0xe5,0x14,0x0c,0xe5,0xe5,0x08,0x0d,0x0f,0x30, + 0x01,0x02,0x18,0x01,0xe5,0x01,0x24,0xe5,0x01,0x14,0x01,0x1b,0x06,0x02,0x01,0x07, + 0x05,0xe5,0x01,0x13,0x44,0x02,0x06,0x04,0xe5,0x1a,0x02,0x01,0xe5,0xe5,0xe6,0x07, + 0x02,0x2b,0x02,0x01,0xe5,0x01,0x07,0x10,0x01,0x0a,0x40,0x01,0x02,0x01,0x01,0x02, + 0x02,0xe6,0xe5,0x03,0x01,0x1a,0xe6,0xe6,0xe5,0x02,0x15,0x19,0x06,0x01,0xe5,0xe5, + 0xe5,0x03,0xe5,0x02,0x05,0x03,0x04,0x0a,0x03,0x2f,0x02,0xe5,0xe5,0x01,0x04,0xe5, + 0x02,0xe5,0xe5,0x01,0xe5,0xe6,0x01,0x03,0x02,0x18,0x01,0x01,0xe7,0x16,0x01,0x04, + 0x13,0x09,0x01,0xe5,0x06,0x01,0x06,0x02,0x07,0x0b,0x36,0x0e,0x01,0x01,0x0c,0x1e, + 0xe6,0xe6,0x16,0x01,0x03,0xe6,0x10,0xe6,0xe5,0x01,0x06,0x01,0x07,0x05,0xe6,0xe5, + 0x12,0x40,0x06,0x01,0x0c,0x1e,0xe6,0x01,0xe5,0x36,0x0c,0x02,0x57,0xe5,0x01,0x05, + 0xe5,0x01,0x05,0xe5,0x07,0x1f,0x02,0xe5,0x3b,0x09,0xe5,0x55,0xe6,0x0a,0xe5,0x05, + 0x03,0x04,0x02,0x20,0xe6,0x0d,0x09,0x09,0x09,0x06,0x02,0xe5,0x01,0x05,0x02,0x06, + 0x09,0x02,0x06,0x09,0x0b,0x09,0x09,0x09,0x09,0xe6,0x01,0x01,0x02,0x06,0x02,0x09, + 0x05,0x03,0x09,0x0d,0x03,0xe5,0x01,0x2e,0x0c,0x5b,0x05,0x0a,0x02,0x0f,0x1c,0x03, + 0x01,0xe5,0x3c,0x59,0x14,0x32,0xe7,0x16,0x01,0x1d,0xe6,0x18,0x01,0x42,0x04,0x02, + 0x10,0x04,0x07,0x23,0x17,0x01,0xe5,0x18,0xe5,0xe5,0x05,0x03,0x0f,0xe5,0xe6,0x40, + 0x04,0xe6,0x08,0x05,0x02,0xe5,0x01,0x06,0x01,0x1e,0xe5,0x01,0x17,0x01,0x1d,0x1b, + 0x01,0x47,0x06,0xe5,0x04,0x09,0xe5,0x01,0x05,0x16,0x07,0x03,0x13,0x01,0xe6,0xe5, + 0x02,0xe5,0xe5,0x05,0x02,0x06,0xe5,0xe5,0x01,0xe5,0x03,0xe5,0x07,0xe5,0x07,0xe6, + 0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01, + 0x05,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x02,0xe5,0x15, + 0x03,0xe5,0x01,0x0f,0xe5,0x06,0x07,0x15,0xe5,0x43,0x1d,0x24,0x03,0x15,0xe5,0x05, + 0x02,0x09,0x06,0x02,0xe5,0x0a,0x13,0xe5,0x43,0x01,0x41,0x02,0x13,0x01,0x09,0xe5, + 0x05,0x01,0xe5,0x06,0xe6,0x01,0x1d,0x1c,0x28,0x01,0x41,0x02,0x0c,0x06,0xe5,0x04, + 0x02,0xe5,0x07,0xe5,0x04,0x02,0x10,0x12,0xe5,0x43,0x01,0x02,0x09,0x04,0x04,0x04, + 0x04,0x1f,0xe5,0xe7,0x30,0x05,0x03,0x02,0x09,0x04,0x02,0x01,0xe5,0xe5,0xe5,0x0d, + 0xe5,0xe5,0x2f,0x02,0xe5,0x04,0x01,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x1f,0xe6, + 0x01,0x11,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x03,0x01,0x02,0x04,0x01,0x07,0x01,0x01, + 0x05,0x01,0xe5,0x02,0x02,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x04,0x04,0x01, + 0x07,0x01,0x07,0x01,0x07,0x01,0x03,0x03,0xe6,0x03,0x02,0x01,0x04,0x02,0x01,0x02, + 0xe5,0x02,0x01,0x07,0x01,0x07,0x01,0x0d,0xe5,0x34,0x0a,0x02,0x04,0x0e,0x10,0x27, + 0x09,0xe5,0xe7,0x03,0x02,0xe5,0x04,0x06,0x07,0x23,0xe6,0x03,0x10,0x12,0x14,0x06, + 0x10,0x03,0x0b,0x07,0x2d,0xe5,0x0d,0x08,0x02,0x05,0x1e,0xe6,0xe6,0x08,0x0b,0x06, + 0x02,0x05,0x01,0x08,0x13,0x07,0x0c,0x09,0x0d,0x32,0xe5,0xe5,0x05,0x0f,0x1f,0x01, + 0x01,0xe5,0x03,0x0b,0x05,0x01,0x01,0x04,0x16,0x04,0x02,0x01,0x0e,0x02,0x01,0x18, + 0x2c,0x06,0x02,0x0b,0xe6,0x01,0x01,0xe7,0x0f,0x12,0x02,0x02,0x02,0x11,0x02,0x0e, + 0x07,0x03,0x04,0x03,0x03,0x01,0xe5,0x0d,0xe5,0x04,0x06,0x0e,0x2c,0x09,0x02,0x04, + 0x09,0x23,0xe5,0xe7,0x07,0xe5,0x14,0x06,0xe5,0xe5,0x0b,0x03,0x03,0x02,0x09,0x0c, + 0x09,0x05,0x07,0x04,0x22,0x0c,0xe5,0x07,0xe6,0x07,0x03,0x13,0x0c,0x01,0x04,0xe5, + 0x0d,0x07,0x18,0xe6,0x03,0xe5,0x04,0x1c,0x06,0x09,0x18,0x1d,0x0b,0x04,0xe5,0x05, + 0x1e,0x01,0x1e,0x09,0x0a,0xe5,0x17,0x16,0x02,0x02,0x06,0x2f,0x16,0x02,0x16,0x01, + 0x03,0x07,0xe6,0x12,0x08,0x03,0x09,0x18,0x0b,0x12,0x0e,0x02,0x38,0x01,0xe5,0x07, + 0xe5,0xe5,0x1a,0x07,0x01,0x47,0x29,0x02,0x2a,0x04,0x06,0xe5,0x01,0xe5,0x01,0x05, + 0xe5,0x1c,0x05,0x03,0x09,0x07,0x01,0x09,0x08,0xe6,0x05,0x02,0x04,0x06,0x02,0x0a, + 0x01,0x1f,0x06,0x31,0x09,0x03,0xe5,0x13,0x12,0xe6,0xe5,0x07,0x2d,0xe5,0x0a,0xe5, + 0x03,0x01,0x07,0x01,0x02,0x06,0x14,0xe5,0x27,0x07,0xe5,0xe5,0x03,0xe5,0xe5,0x06, + 0x01,0x01,0x1f,0xe5,0x02,0x37,0x07,0x05,0x19,0x14,0x05,0x24,0x07,0x07,0x0d,0x20, + 0xe8,0x35,0x01,0x09,0x10,0x02,0x07,0x6f,0xe5,0xe5,0x0c,0x01,0xe5,0x01,0x01,0xe5, + 0x03,0xe5,0x29,0x1d,0x89,0x03,0xe6,0x25,0xe5,0x0d,0xe5,0x01,0x01,0xe5,0x01,0xe5, + 0x18,0x09,0x36,0x1a,0x05,0xe5,0x1a,0xe6,0xe7,0x01,0x01,0x05,0x01,0x14,0xe5,0x15, + 0x02,0x01,0xe7,0x11,0xe5,0x06,0x09,0xe6,0x37,0xe5,0xe5,0x03,0x04,0xe6,0x0d,0x01, + 0x16,0x01,0x03,0x02,0x04,0x04,0xe5,0x01,0x01,0x03,0xe5,0x01,0x01,0x09,0x07,0x01, + 0x0e,0x01,0xe5,0xe5,0xe5,0x07,0x02,0xe5,0x01,0x01,0x07,0x01,0x07,0x01,0xe5,0x36, + 0xe5,0xe5,0x05,0xe5,0x03,0x01,0x24,0x04,0x01,0xe6,0x01,0x07,0x02,0x01,0x04,0x02, + 0x01,0x07,0x06,0x02,0x01,0x13,0x11,0x01,0x07,0x01,0x07,0x01,0x38,0x02,0x06,0x02, + 0x01,0x04,0xe5,0xe5,0x20,0x05,0xe5,0x0a,0x09,0x0d,0x05,0x0b,0x01,0x07,0x05,0x02, + 0x04,0x07,0x07,0x02,0x06,0x03,0xe5,0x35,0x01,0x02,0x04,0xe6,0xe5,0xe5,0x07,0x02, + 0x02,0x1b,0x01,0x01,0x01,0x03,0x0b,0x09,0x05,0x03,0x04,0x04,0x05,0x01,0x01,0x05, + 0x01,0x01,0x11,0x01,0x05,0x02,0x06,0x04,0x38,0x02,0x02,0x01,0xe6,0xe5,0xe5,0x03, + 0x04,0x02,0x01,0x18,0x02,0xe8,0x0c,0x01,0x07,0x01,0x03,0xe5,0x03,0x03,0xe6,0xe5, + 0xe5,0x06,0x01,0x04,0x01,0xe5,0x05,0x01,0x05,0x01,0x01,0xe5,0xe5,0x06,0x01,0x07, + 0x06,0x1f,0x01,0x10,0xe5,0x01,0x09,0x01,0x04,0xe6,0x1e,0x04,0x01,0xe7,0x01,0x0a, + 0x01,0x07,0x01,0x04,0x01,0xe5,0x05,0x01,0xe5,0xe5,0x06,0x01,0x03,0xe5,0x01,0x01, + 0x03,0xe5,0x08,0x01,0xe5,0xe5,0x06,0x01,0xe5,0x05,0x06,0xe5,0x1c,0xe5,0x12,0x01, + 0xe5,0x01,0x06,0x01,0x04,0x01,0x03,0x23,0xe6,0x01,0x02,0x03,0x3b,0x02,0x05,0xe6, + 0x0e,0x02,0xe5,0x06,0x02,0x38,0x02,0xe5,0x04,0x02,0x02,0x26,0x01,0xe5,0x09,0x01, + 0x39,0xe5,0x07,0xe5,0x19,0x3b,0x0a,0x0c,0x1e,0xe5,0xe6,0x07,0x05,0x09,0x09,0x09, + 0x09,0x09,0x06,0x02,0x09,0x02,0x01,0x01,0x02,0x02,0x03,0x02,0x0b,0x09,0x09,0x09, + 0x09,0x04,0x01,0x02,0xe5,0x07,0x09,0x03,0x05,0x09,0x0d,0xe7,0xe5,0x01,0x3b,0x06, + 0x08,0x03,0x10,0x40,0x09,0x04,0xe5,0x25,0x03,0xe7,0x3a,0x13,0x51,0x09,0x32,0x03, + 0x17,0x01,0x04,0x13,0x04,0x06,0x0a,0x01,0x09,0x07,0x01,0xe6,0x04,0x01,0x0b,0x0e, + 0x22,0xe6,0x07,0xe5,0x04,0x01,0x01,0x02,0x1b,0x01,0x03,0x17,0x01,0xe5,0x1b,0xe5, + 0x08,0x03,0x02,0x01,0x01,0x08,0x06,0x01,0x07,0x01,0xe6,0x08,0xe5,0x2c,0xe5,0x07, + 0x04,0x01,0x05,0x24,0x01,0x14,0x02,0x01,0x1a,0x02,0x04,0x08,0x03,0x01,0x09,0x09, + 0x07,0x01,0x03,0x02,0x04,0x31,0x0a,0x08,0xe5,0x20,0x02,0xe6,0x12,0xe7,0xe5,0x02, + 0x01,0xe5,0x07,0xe5,0x05,0xe7,0x01,0x03,0xe7,0x01,0x05,0xe6,0xe5,0x04,0xe5,0x07, + 0xe6,0x01,0x03,0xe7,0xe5,0x04,0xe5,0x03,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe6,0x01,0x04,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe5, + 0x01,0x1a,0xe5,0xe5,0x05,0xe5,0x0a,0x05,0xe6,0x01,0x05,0xe5,0x04,0x01,0x13,0x07, + 0x0d,0xe5,0x12,0xe5,0x1a,0x36,0x03,0x14,0x01,0x1b,0x01,0x02,0x06,0x0a,0x01,0x09, + 0x09,0x06,0x02,0x0b,0xe5,0x2d,0x38,0x02,0xe6,0x1d,0x13,0x03,0x03,0x01,0x0d,0x13, + 0x04,0xe5,0xe5,0x09,0x02,0x31,0x07,0x2e,0x01,0x01,0x10,0x03,0x01,0x03,0x02,0x01, + 0x04,0x09,0x03,0xe6,0x01,0xe5,0x03,0xe5,0x02,0x0b,0x06,0x0d,0xe7,0x01,0x02,0x08, + 0xe5,0x12,0x26,0x02,0x11,0x1b,0xe5,0x3d,0x03,0x09,0x03,0x01,0x07,0x01,0x01,0xe5, + 0x08,0x3a,0x09,0x09,0xe5,0xe5,0x1f,0xe5,0x01,0xe5,0x10,0x01,0x01,0x05,0x01,0x07, + 0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x02,0x04,0x01,0x03,0x02,0xe5,0xe5,0xe5, + 0xe5,0x02,0x01,0xe5,0x05,0x01,0x04,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x01,0x05,0x01,0x07,0x01,0x02, + 0x09,0xe6,0x07,0x02,0x09,0x13,0x0d,0x08,0x03,0x08,0x19,0x06,0x37,0x0f,0x27,0x01, + 0x01,0xe5,0x0a,0x09,0x05,0x07,0x19,0x05,0x02,0x0a,0x03,0xe5,0x12,0x52,0x1e,0x04, + 0x05,0x2a,0x05,0x03,0x28,0x09,0x03,0x43,0x28,0x01,0x01,0xe5,0x06,0x0e,0xe6,0x0d, + 0xe5,0x14,0x09,0x01,0x01,0x02,0x02,0x01,0x07,0x0b,0x38,0x02,0xe7,0x05,0x01,0x07, + 0x24,0x03,0x18,0x06,0x1d,0x03,0x05,0x04,0x02,0x05,0x0a,0x06,0x03,0x01,0x03,0x07, + 0x2c,0x0a,0x04,0x04,0x24,0x01,0xe5,0x0f,0x01,0x09,0x1d,0xe5,0x03,0x03,0xe5,0x01, + 0xe6,0x06,0x07,0x03,0x11,0xe5,0x0e,0x11,0x16,0x03,0x19,0x08,0x0b,0x01,0xe6,0x1e, + 0x06,0xe5,0x07,0x07,0x06,0xe5,0xe5,0x04,0xe5,0x0d,0x02,0x02,0x07,0x0a,0x4a,0x19, + 0x09,0x01,0x26,0x18,0x03,0x07,0x02,0x09,0x18,0x37,0x31,0x02,0xe5,0x01,0x08,0x16, + 0x09,0x15,0xe6,0x03,0x01,0x06,0x02,0x18,0x05,0xe5,0x3a,0xe6,0x0b,0x22,0x01,0x01, + 0x1a,0x1e,0x06,0x01,0x0b,0x06,0x0a,0x0e,0x38,0x04,0x01,0x20,0xe5,0x0c,0xe5,0x3d, + 0x03,0x02,0x05,0x59,0x01,0xe5,0x2f,0x04,0x02,0xe5,0xe5,0x07,0x1b,0x09,0x09,0x0f, + 0xe6,0x17,0x4e,0x28,0x01,0xe5,0xe5,0xe5,0x02,0x18,0x09,0x1b,0x06,0x02,0xe5,0x08, + 0x1d,0x3b,0x2a,0x03,0x01,0x01,0x3b,0x04,0x04,0x02,0x55,0x01,0x0f,0x27,0x01,0xe5, + 0xe6,0xe5,0x3c,0xe5,0x07,0xe6,0x15,0x3f,0x01,0x0a,0xe5,0x27,0x01,0x02,0x01,0xe6, + 0x03,0x37,0xe5,0xe5,0xe5,0x06,0x01,0x56,0xe5,0x03,0x03,0x01,0xe5,0x28,0x04,0xe9, + 0xe5,0x37,0xe5,0x01,0x01,0x03,0xe5,0x01,0x01,0x56,0x04,0xe5,0x02,0x04,0x22,0xe5, + 0x04,0x02,0xe6,0xe6,0x3d,0x01,0x02,0x01,0x01,0x02,0x11,0x01,0x43,0x06,0x02,0xe5, + 0x01,0x02,0x01,0x01,0x24,0x02,0xe8,0x02,0x39,0x04,0xe5,0x01,0x02,0x01,0x0f,0x01, + 0x01,0x48,0xe5,0xe7,0x03,0x03,0x22,0x03,0x02,0x05,0x39,0x01,0x02,0x04,0x01,0x04, + 0x01,0x0a,0x01,0x4f,0x04,0x02,0x25,0xe7,0xe6,0x26,0x01,0x14,0x09,0x01,0x04,0x01, + 0x0a,0x01,0x47,0x09,0x2c,0xe8,0x04,0x03,0x3a,0xe5,0x01,0x06,0x02,0x57,0xe5,0x07, + 0xe6,0x25,0xe5,0xe7,0x09,0x01,0xa1,0x2f,0x01,0x01,0xe5,0x07,0x05,0x09,0x09,0x09, + 0x09,0x06,0x02,0x04,0x01,0x02,0x02,0x06,0x09,0x02,0x06,0x0b,0x09,0x09,0x09,0x09, + 0x09,0x06,0x02,0x09,0x09,0x09,0x06,0x06,0x02,0x01,0x3b,0x02,0x05,0x03,0x61,0x02, + 0xe5,0x04,0x1e,0x02,0x04,0x03,0x01,0xe5,0x3c,0x09,0x65,0x26,0x0d,0x3c,0x0b,0x66, + 0x2e,0x01,0xe6,0x1d,0x24,0x05,0x01,0xe5,0x5b,0x07,0x01,0x2a,0x02,0xe6,0xaa,0x33, + 0xe6,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x01,0x01,0x09,0x1a,0xe5, + 0x7e,0x09,0x32,0x41,0x07,0x01,0x59,0x0b,0x2e,0xe6,0x3e,0x32,0x3c,0x2e,0xe6,0xe5, + 0x23,0x1c,0x02,0x65,0x06,0x02,0x2b,0x01,0xe5,0x3d,0x09,0xe5,0xe5,0x57,0xe5,0xe5, + 0x09,0x2a,0x01,0x01,0x11,0x01,0x07,0x01,0x01,0x04,0xe5,0xe5,0x06,0x01,0x02,0x04, + 0x01,0x07,0xe6,0x02,0x03,0x01,0x02,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x02,0x01, + 0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x0a,0x02,0xe5,0x3d,0x01,0x24,0x3e,0x39,0x01,0x01,0xe5, + 0x09,0x0a,0x13,0x1c,0xe5,0x12,0x03,0x05,0x4d,0x28,0xe5,0x01,0xe5,0x2f,0x09,0x09, + 0x2c,0x6d,0x02,0xe5,0x3a,0x02,0xe5,0x09,0x59,0x02,0x06,0x01,0x04,0x26,0x02,0x01, + 0x1d,0x09,0x08,0x0a,0x01,0x08,0xe5,0xe5,0x16,0x0f,0x36,0x08,0x2d,0x02,0xe5,0x3e, + 0xe5,0x0c,0x06,0x16,0x03,0x2c,0x0b,0x04,0xe6,0x03,0x1a,0x0b,0x01,0xe7,0x07,0x09, + 0x13,0x13,0x03,0xe5,0xe5,0x01,0x03,0x09,0x17,0x06,0xe5,0x0c,0x13,0x49,0x02,0xe5, + 0x3b,0x07,0x09,0x09,0x18,0x42,0x2a,0xe7,0x46,0x07,0x21,0x47,0xe5,0x22,0xe6,0xe5, + 0x70,0x47,0x01,0x23,0xe7,0x3e,0x01,0x6d,0x01,0xe5,0x05,0x01,0x22,0xe5,0xe6,0x40, + 0xe5,0x6d,0x09,0x23,0xe7,0x3f,0x02,0x01,0x63,0x06,0x02,0x07,0x23,0x01,0xe7,0x10, + 0xe5,0x29,0x7d,0x1e,0xe6,0xe5,0xe5,0x01,0x01,0x0f,0x01,0x2a,0x02,0x71,0xe5,0x20, + 0x01,0x02,0xe6,0xe5,0x03,0x19,0xe5,0xe5,0xe5,0x1a,0x6c,0x01,0x02,0xe5,0x09,0x1b, + 0x04,0xe8,0x01,0x1e,0x01,0x18,0xe5,0x02,0x6a,0x02,0x2b,0x02,0x01,0x01,0x46,0x01, + 0x64,0x03,0x01,0xe6,0x01,0x05,0x1f,0x01,0x01,0x02,0x22,0x1d,0x04,0x66,0x04,0x26, + 0x03,0xe5,0xe6,0x1f,0x01,0x1d,0x05,0x1c,0x01,0x48,0x04,0x01,0x01,0x04,0x1f,0x01, + 0x01,0xe5,0x20,0x01,0x1b,0x23,0xe5,0x4b,0x04,0x01,0x29,0x45,0x02,0x6b,0x09,0x20, + 0xe7,0x45,0x6c,0x0a,0x1f,0x03,0xe5,0x0d,0x09,0x09,0x09,0x09,0x06,0x02,0x03,0x05, + 0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x06,0x02,0x06,0x02,0x09,0x09,0x0d, + 0xe6,0xe6,0x01,0x3a,0x6f,0xe5,0x04,0xe5,0x07,0x1c,0x02,0x02,0xe5,0xac,0x31,0x02, + 0x01,0x1f,0x01,0x11,0x01,0x07,0x01,0x11,0x01,0x07,0x01,0x4f,0x0e,0x1d,0x01,0x01, + 0x01,0x21,0x01,0xe5,0x0f,0x01,0xe5,0x07,0xe5,0x0f,0x01,0xe5,0x05,0x01,0xe5,0x50, + 0xe5,0xe5,0x06,0x1d,0x02,0xe5,0x01,0x21,0x01,0x11,0x01,0x06,0xe5,0xe5,0x10,0x01, + 0x07,0x01,0x4c,0x02,0x0f,0x21,0xe5,0x14,0xe5,0x05,0xe8,0xe5,0x02,0xe7,0x05,0x01, + 0xe6,0xe5,0x03,0xe7,0xe5,0x02,0x01,0xe5,0x07,0xe6,0xe5,0x02,0x01,0xe6,0xe5,0x02, + 0xe7,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07, + 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe5,0x01,0x16,0x09,0x06,0xe5,0xe5,0x08, + 0x07,0x01,0xe5,0xe6,0x04,0x10,0x06,0xe5,0x03,0x48,0x09,0x02,0x1f,0x03,0xe6,0x14, + 0xe5,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x03,0x01,0xe5,0x07,0x09,0x08, + 0xe6,0x76,0x02,0xe5,0x14,0x09,0x09,0x07,0x01,0x09,0x01,0x01,0xe5,0x03,0x09,0x09, + 0x07,0x01,0x0c,0x3c,0x09,0x02,0x25,0x1a,0x02,0xe5,0x08,0x08,0xe5,0x07,0xe5,0x01, + 0x01,0xe5,0x01,0xe5,0x07,0x09,0x06,0x02,0xe5,0x4e,0x09,0x23,0xde,0x02,0xe5,0xe5, + 0x0e,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0xe5,0xe5,0x03,0x01,0x02, + 0x04,0x01,0xe5,0xe5,0x03,0x01,0x07,0x01,0x07,0x01,0x04,0x04,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08, + 0x01,0xe6,0xe5,0x15,0x1c,0x0d,0xe5,0x21,0x55,0xe6,0x1b,0x04,0x01,0xe6,0x0a,0x08, + 0x29,0x01,0x0e,0x0f,0xe5,0x01,0x54,0x23,0xe5,0xe5,0xe5,0x39,0x36,0x48,0x23,0x03, + 0x05,0x1b,0x01,0x0a,0x08,0x0a,0x03,0x05,0x06,0x02,0x06,0x01,0x59,0x01,0x22,0xe8, + 0x04,0x02,0x18,0x01,0x03,0x09,0x03,0x07,0x06,0x02,0x0e,0x02,0xe5,0x01,0x01,0x11, + 0x43,0x03,0x02,0x21,0xe8,0x12,0x09,0x1d,0x09,0x2b,0x0e,0x27,0x01,0x1b,0x18,0x02, + 0x02,0x02,0x0a,0x09,0x27,0xe5,0x04,0x27,0xe5,0x20,0x27,0x13,0x0f,0xe6,0x02,0x02, + 0x35,0x06,0x05,0x04,0x02,0x06,0x18,0x6c,0x01,0x01,0x3f,0xe6,0xe6,0x09,0x01,0x1f, + 0x6c,0xe6,0xe5,0x02,0x3e,0x01,0x12,0x19,0x41,0xe5,0x28,0xe5,0x01,0x28,0x18,0x22, + 0x09,0x6c,0x02,0x03,0xe5,0x3f,0x07,0x01,0x01,0x8f,0xe7,0xe5,0x31,0x0c,0x01,0x38, + 0x63,0x02,0xe5,0xe5,0x35,0x06,0x02,0xe5,0x14,0xe5,0x04,0xe5,0x76,0x02,0x05,0x01, + 0x02,0x3c,0xe5,0x06,0xe5,0x0c,0xe5,0x7f,0x02,0x01,0xe6,0x03,0x26,0x01,0x0d,0xe5, + 0x08,0xe5,0xe5,0xe5,0x01,0x12,0x7c,0x01,0xe6,0x01,0x25,0x02,0x01,0x18,0xe5,0xe5, + 0xe5,0x8b,0x02,0x01,0x02,0xe7,0x08,0x01,0x1c,0x15,0x09,0x93,0x02,0xe6,0xe5,0x06, + 0x02,0x22,0x11,0x01,0x01,0x02,0xe5,0x02,0x8d,0x01,0x01,0xe5,0xe5,0x2a,0x01,0x0d, + 0xe5,0x07,0xe5,0x01,0x01,0x91,0xe7,0xe5,0xe6,0x27,0x01,0x0e,0x01,0x07,0x02,0x01, + 0x91,0x01,0xe8,0x07,0x02,0x38,0x01,0xe5,0x19,0x7b,0xe7,0x63,0x01,0x77,0xe9,0x0d, + 0x09,0x09,0x09,0x09,0x09,0x02,0x06,0x09,0x09,0x05,0x03,0x0b,0x09,0x09,0x09,0x09, + 0x09,0x09,0x09,0x09,0x09,0x06,0x06,0xe6,0xe6,0x3d,0x94,0x02,0x04,0x04,0x01,0x3d, + 0x96,0x09,0xe5,0xe6,0x3e,0x01,0x06,0xe5,0x11,0xe5,0xe5,0x7f,0xe6,0x3e,0x01,0xe5, + 0x05,0x02,0x10,0x01,0xe5,0x7d,0xe8,0x3f,0x07,0x94,0xe6,0xe5,0x13,0xe6,0x07,0xe5, + 0x07,0xe5,0x06,0xe6,0x05,0xe7,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x05,0xe7,0x07,0xe5, + 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe5,0x09,0xe5,0x31,0x0c,0x01,0xe6,0x18,0x01,0x7f,0xe7,0x15,0x1d, + 0x09,0xe5,0xe5,0x1a,0x01,0x06,0x77,0x03,0xe5,0x12,0x0a,0x13,0x07,0xe6,0xe5,0xe5, + 0x20,0xe6,0x77,0x03,0x03,0x10,0x01,0x06,0x01,0x11,0x01,0xe5,0x05,0x01,0xe6,0xe6, + 0x1f,0x01,0xe5,0x71,0x05,0xe7,0x48,0xe5,0xe5,0x8b,0x04,0xe5,0xe6,0x10,0x01,0xe6, + 0x04,0x01,0x07,0x01,0xe5,0xe5,0x03,0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x01,0x07, + 0x01,0x07,0x01,0x02,0x04,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x06,0x04,0xe5,0xe5,0x4e,0x8f, + 0xe8,0x14,0x2c,0x18,0x80,0xe5,0x01,0xe5,0x44,0x06,0x24,0x6c,0xe5,0xe7,0x3d,0xe5, + 0x06,0xe7,0x0a,0x19,0x6b,0x01,0xe7,0x26,0x1b,0x06,0x22,0x03,0x61,0x02,0x08,0x01, + 0xe6,0xe5,0x0f,0x23,0xe5,0x03,0x0c,0xe5,0x02,0x04,0xe5,0x1a,0x39,0x10,0x20,0xe6, + 0xe6,0x0f,0x25,0x12,0x09,0x01,0x02,0x18,0x63,0x0b,0xe5,0x05,0x0a,0x13,0x25,0x02, + 0x22,0x6c,0xe5,0x01,0x05,0x37,0x14,0x1e,0x6d,0x02,0x44,0x2c,0x6c,0x03,0x09,0x68, + 0x62,0x09,0xe7,0x01,0x1b,0x23,0x05,0xe5,0xe5,0x02,0x22,0x6b,0xe8,0xe5,0x09,0x57, + 0x79,0xe8,0xe5,0x07,0x01,0x03,0xe5,0x01,0xe5,0x03,0xe5,0x07,0xe5,0xb5,0x04,0xe5, + 0xe5,0x01,0x04,0xe5,0x12,0xe5,0x2d,0x8a,0x01,0x03,0xe7,0x03,0x0c,0x09,0x09,0x15, + 0xe5,0x01,0x01,0x04,0xe5,0x90,0x04,0x03,0x02,0x39,0x02,0x01,0x04,0xe5,0xe5,0x05, + 0xe5,0x88,0x01,0x02,0x01,0xe5,0x07,0x02,0x28,0x01,0x05,0x11,0x02,0x06,0x02,0x80, + 0xe5,0xe5,0xe5,0x01,0x06,0x02,0x28,0x01,0x01,0x09,0x09,0x02,0x01,0x04,0x02,0x01, + 0x7e,0x02,0xe9,0x33,0x01,0x07,0x01,0x09,0x91,0x03,0xe5,0x34,0x01,0x07,0x01,0x07, + 0x09,0x87,0x01,0xea,0x03,0xe5,0x01,0x02,0xcf,0x01,0x01,0xe6,0x04,0x04,0x45,0x8c, + 0xe6,0xe7,0x07,0x05,0x09,0x09,0x09,0x09,0x02,0x06,0x09,0x03,0xe5,0xe5,0x01,0x09, + 0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x04,0xdb,0x02,0xe5, + 0xe6,0xdd,0xe8,0x4a,0x09,0x88,0xe5,0x01,0x48,0x03,0x09,0x87,0x01,0x01,0xe5,0x50, + 0x02,0x88,0xe5,0x01,0x13,0x01,0xe5,0x06,0xe6,0x06,0xe6,0x07,0xe5,0x07,0xe5,0x05, + 0xe7,0x05,0x01,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07, + 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0a, + 0x46,0x0e,0x88,0x01,0x01,0x20,0x09,0x1d,0x95,0xe8,0x12,0x01,0x08,0x09,0xe5,0x1a, + 0x01,0x07,0x01,0x03,0x03,0x01,0x82,0x01,0xe6,0x12,0x01,0x0a,0x06,0x01,0xe5,0x19, + 0x01,0xe5,0x05,0x01,0x07,0x01,0x84,0xe6,0x4a,0xe5,0x07,0xe5,0x87,0xe5,0xe5,0x10, + 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0xe6,0xe5,0x51,0x13,0x78,0x02,0xe5,0x0a, + 0x09,0x36,0x16,0x15,0x62,0x01,0xe7,0x1d,0x52,0x6b,0xe5,0x01,0xe6,0x42,0x04,0x01, + 0x25,0x6e,0x01,0x43,0x05,0x02,0x24,0x6b,0x01,0x02,0xe5,0x11,0x31,0x2b,0x36,0x15, + 0x12,0x0b,0xe6,0xe6,0x4c,0x0e,0x14,0xe5,0x68,0xe6,0xe5,0xe5,0x70,0x61,0x0a,0x03, + 0x4c,0x0e,0x15,0x6d,0x02,0x01,0x6f,0x70,0x0a,0xd6,0xe5,0xde,0x02,0x46,0x09,0x07, + 0x82,0x03,0xe9,0xd9,0xe5,0x01,0xe6,0x01,0x01,0xd4,0x01,0x02,0x03,0x04,0xd4,0x07, + 0xe5,0x01,0xd8,0x02,0x01,0x01,0xe1,0xe5,0x01,0xd8,0x02,0x03,0xe5,0xdb,0xe5,0x02, + 0x02,0xdb,0xe5,0xe6,0xe5,0x4c,0x02,0x8d,0x01,0x50,0xe5,0x8c,0x01,0xe6,0x0d,0x09, + 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09, + 0x09,0x09,0x0d,0xe6,0xe6,0x01,0xd8,0x03,0xe7,0xdd,0xe6,0xe5,0xe5,0x46,0x01,0x90, + 0x01,0x02,0xe5,0x48,0x01,0xe5,0x92,0x01,0xe3,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x08,0x01,0x49,0x01,0x92,0xe8,0x48,0x01,0x94,0x01,0xde,0xe5,0xe6,0xda, + 0x03,0xe7,0xdd,0xe5,0xe6,0xe5,0x0e,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x07,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08, + 0x01,0xe6,0xe5,0x5b,0x81,0x02,0xe6,0x50,0x31,0x50,0x07,0xe5,0x01,0xe5,0xe5,0x6e, + 0x6e,0xe6,0x70,0x6c,0x01,0xe6,0x70,0x6c,0xe6,0xe5,0x12,0x5d,0x36,0x15,0x21,0xe6, + 0x70,0x6c,0x02,0xe5,0x70,0x6c,0x01,0xe6,0x4c,0x23,0x6e,0xe6,0x02,0x6d,0x6c,0x03, + 0x4d,0x91,0x02,0xe5,0xdb,0xe9,0x01,0xdb,0xe5,0x01,0xe6,0xd9,0xe6,0x01,0xe5,0x01, + 0x01,0xd4,0x01,0x05,0xe5,0x03,0xd4,0x04,0xe8,0x01,0xd8,0x02,0xe6,0xe5,0xdf,0xe6, + 0x01,0xd8,0x05,0xe6,0xdb,0x03,0xe5,0xdd,0xe5,0x01,0xde,0x01,0xe6,0xdd,0xe6,0xe6, + 0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09, + 0x09,0x09,0x09,0x09,0x0d,0xe6,0x01,0x02,0xd8,0x03,0x01,0xe5,0xde,0xe5,0xe5,0xe5, + 0xd9,0x01,0xe6,0xe5,0xdd,0x01,0xe6,0xde,0xe5,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x08,0x01,0xdf,0x02,0xe1,0xe5,0xdd,0xe8,0xdd,0x01,0xe6,0x02,0xdb,0xe7, + 0xe5,0x09,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x01,0xe6,0xe5,0x51, + 0x13,0x79,0x01,0xe5,0x14,0x4d,0x17,0x11,0x4e,0xe6,0x01,0x71,0x6c,0x01,0xe6,0x70, + 0x6c,0x01,0xe6,0x70,0x6c,0xe6,0xe5,0x12,0x31,0x2b,0x4a,0x15,0x0f,0x31,0x3f,0x6d, + 0xe7,0x70,0x68,0x03,0xe5,0xe6,0xe5,0x6e,0x6c,0xe8,0x70,0x6e,0x01,0x02,0xdf,0xe5, + 0x08,0xd2,0x01,0x01,0xe5,0xdf,0x01,0xe6,0xd9,0x01,0xe6,0xe5,0x01,0x01,0xd4,0x01, + 0x03,0x02,0x04,0xce,0xe5,0x03,0x05,0xe7,0xd3,0x06,0x02,0x03,0xd5,0x07,0xe5,0xe7, + 0xda,0x03,0x01,0xe5,0xdc,0xe9,0xdd,0x02,0xe5,0x08,0xd3,0x04,0x0a,0x01,0xd1,0xe5, + 0xe7,0x07,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09, + 0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe6,0xe6,0x01,0xd3,0x04,0x02,0x03,0xd5,0x08, + 0x01,0x01,0xe0,0x01,0xde,0xe5,0xe6,0xdf,0x01,0xe5,0x13,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x09,0xe5,0xdd,0x03,0xe0,0x01,0xe5,0xdc,0xe8,0xdf,0x01,0xdf,0xe5,0xe5, + 0x10,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07, + 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0c,0xe6,0xdd,0xe9,0x50, + 0x33,0x56,0x01,0x02,0x01,0x03,0x2c,0x3e,0x6c,0xe5,0xe7,0x6f,0x6b,0x01,0xe5,0xe5, + 0x12,0x5d,0x6e,0xe7,0x08,0x1f,0x09,0x3c,0x4a,0x15,0x0a,0xe9,0x70,0x6c,0x02,0xe5, + 0x05,0x6a,0x6c,0xe6,0xe5,0x70,0x6e,0xe6,0x70,0x6d,0xe7,0x09,0x09,0x09,0xbf,0x01, + 0x01,0xde,0xe5,0xe6,0x26,0xba,0xdc,0x01,0x01,0xe6,0x01,0x01,0xd4,0x01,0x03,0xe7, + 0x03,0xcf,0xe5,0x02,0x04,0x02,0xe5,0xe6,0xd7,0x03,0x01,0xe6,0xe5,0x06,0x01,0xd0, + 0x02,0xe6,0xda,0x02,0xe5,0x01,0xdd,0xe6,0xe6,0xda,0xe5,0x02,0xe7,0x07,0xd3,0x01, + 0xe7,0x09,0x01,0xd5,0xe5,0x07,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09, + 0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x06,0xe9,0xd5,0x04, + 0x05,0xe5,0xd2,0x0a,0x02,0xe5,0xdf,0x01,0xdf,0xe8,0xdd,0x01,0xe5,0x14,0xe5,0x07, + 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07, + 0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07, + 0xe5,0x07,0xe5,0x07,0xe5,0x07,0x01,0xe5,0xd8,0x05,0xe7,0xde,0xe5,0xe6,0xdc,0x02, + 0xe5,0x02,0x08,0xd3,0x01,0x32,0xab,0xe6,0xe5,0x10,0x01,0x02,0x04,0x01,0x07,0x01, + 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01, + 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x07,0x01,0x0a,0x02,0xe5,0xde,0x02,0xe5,0x64,0x15,0x13,0x4c,0x02,0xe6,0x70,0x6d, + 0xe5,0xe6,0x6f,0x6b,0x02,0x01,0x13,0x5d,0x64,0x07,0xe5,0xe7,0x43,0x2b,0x61,0x09, + 0xe5,0x02,0x25,0x4b,0x6e,0x01,0x06,0x20,0x49,0x6d,0xe5,0xe5,0x70,0x6c,0x03,0x03, + 0x6d,0x6e,0xe6,0xe1,0xdc,0x01,0xe5,0x01,0xe3,0xe7,0xd9,0x03,0xe6,0x01,0x01,0xd4, + 0x01,0x02,0x01,0x01,0x04,0xd4,0x06,0x01,0xd4,0xe5,0x04,0x02,0x01,0xe6,0xdc,0x01, + 0x02,0x02,0xd8,0x03,0x02,0x01,0xdb,0x01,0xe5,0xe5,0xdd,0xe5,0x01,0xdd,0x01,0xe7, + 0xdf,0xe7,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09, + 0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x02,0x01,0x02,0xd8,0x04,0xe6,0xdd,0x02,0xe5, + 0xdd,0x01,0xe6,0xdd,0xe5,0x01,0xe5,0xde,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07, + 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07, + 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07, + 0xe5,0x06,0x01,0x01,0xde,0x01,0x01,0xe3,0xe6,0xdc,0xe5,0x01,0xdf,0xe7,0x3b,0x10, + 0x92,0xe6,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07, + 0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01, + 0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x0d, + 0xe5,0x50,0x34,0x58,0x02,0xe5,0x50,0x8a,0xe9,0xe5,0x02,0x5f,0x0a,0xe5,0x09,0x12, + 0x51,0xe5,0x03,0x49,0x22,0x14,0x13,0x42,0xe5,0x01,0xe6,0x01,0x6d,0x6f,0xe6,0x2b, + 0x24,0x1e,0x52,0xe5,0x0b,0x0a,0xe5,0x01,0xe6,0x23,0x05,0x01,0x3f,0x03,0x6c,0xe5, + 0xe6,0x26,0x06,0x42,0x6c,0x01,0xe7,0x6f,0x6d,0xe7,0x70,0x6d,0x01,0xe5,0x30,0x3d, + 0x5f,0x0e,0x01,0x01,0x2d,0x97,0x08,0xe5,0x0d,0xe5,0x01,0x09,0x23,0x44,0x52,0x08, + 0x11,0xe6,0x02,0x0b,0xe5,0x01,0x06,0x06,0xe7,0x07,0xe5,0x05,0xe7,0x05,0xe7,0x05, + 0xe7,0xe5,0x05,0xe5,0x08,0x08,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07, + 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0b,0x02,0xe6,0x0d,0x01, + 0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x02,0x02,0x01, + 0x01,0x08,0xe5,0x0d,0x02,0x01,0x0b,0x09,0x09,0x09,0x07,0x01,0x01,0xe5,0x05,0x09, + 0x09,0x02,0x06,0x09,0x0d,0x02,0xe5,0x0f,0x08,0x13,0x09,0x1d,0x09,0x04,0x04,0x08, + 0x02,0x04,0x04,0x09,0x04,0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x02,0x14,0x41, + 0x87,0x01,0xe6,0x18,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x13,0x0b,0x09,0x04,0x04, + 0x09,0x04,0x04,0x02,0x06,0x09,0x09,0x09,0x09,0x0e,0x01,0x01,0x0d,0xe5,0x07,0xe6, + 0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5, + 0x01,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5, + 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0e,0xe8,0x02,0x05,0x03,0x09,0x01,0x04,0x02,0x01, + 0x07,0x09,0x09,0x01,0x07,0x01,0x07,0x09,0x07,0x01,0x0b,0x09,0x09,0x09,0x09,0x09, + 0x09,0x09,0x09,0x09,0x14,0x0e,0x09,0x09,0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09, + 0x09,0xe5,0xe5,0x05,0x09,0xe5,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5, + 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05, + 0xe5,0xe5,0x05,0xe5,0xe5,0x0f,0x0e,0x09,0x01,0x07,0x09,0x09,0x09,0x09,0x09,0x09, + 0x01,0x07,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x01,0xe6,0x47, + 0x11,0x76,0x0c,0x01,0x01,0x0e,0x05,0x03,0x05,0x03,0x09,0x05,0x03,0x09,0x09,0x09, + 0x09,0x09,0x06,0x01,0x02,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0f, + 0xe8,0x0f,0x13,0x1d,0x09,0x24,0x70,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03, + 0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,0x01,0xe5,0x46, + 0x96,0x02,0xe5,0x70,0x6e,0x01,0x22,0x1d,0x09,0x13,0x11,0xe5,0x67,0x06,0xe5,0x06, + 0x06,0x06,0x02,0x06,0x02,0x06,0x16,0x06,0x02,0x13,0x06,0x79,0xe5,0xe5,0x3a,0x1d, + 0x33,0x1d,0x09,0x2a,0xe6,0x06,0x05,0x08,0xe5,0x07,0xe5,0x07,0x14,0x08,0xe5,0x12, + 0x08,0x0a,0x65,0x06,0x03,0x71,0x66,0x05,0xe5,0xe6,0xdd,0xe5,0xe6,0x0c,0xe5,0x04, + 0xe8,0x04,0xe8,0x04,0xe6,0x06,0x09,0x02,0xe5,0x04,0xe8,0x04,0x09,0x02,0xe5,0x04, + 0xe6,0x06,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x01,0xe6,0x0c, + 0xe6,0x05,0xe7,0x05,0xe7,0x05,0x01,0xe5,0x08,0x07,0xe6,0x05,0xe7,0x08,0x07,0xe6, + 0x05,0x02,0x07,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x08,0xe5,0x07,0xe5,0x0e, + 0xe5,0xe5,0x33,0x2d,0x0e,0x10,0x13,0x48,0x02,0x11,0x03,0x05,0x03,0x05,0x03,0x05, + 0x03,0x01,0x0d,0x03,0x05,0x03,0x01,0x0d,0x03,0x01,0x03,0x07,0x09,0x09,0x09,0x09, + 0x03,0x05,0x09,0x09,0x11,0x13,0x01,0xe5,0x0a,0x06,0x09,0x09,0x04,0x01,0x02,0x01, + 0x03,0x07,0x05,0x09,0x01,0x03,0x07,0x0e,0xe5,0x02,0x06,0xe5,0x02,0x04,0x04,0x01, + 0x07,0x04,0x04,0x05,0x03,0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x02,0x04,0x04,0x06, + 0x01,0x03,0xe5,0xe5,0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff, diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds new file mode 100644 index 0000000..1cf375f --- /dev/null +++ b/board/esd/du405/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile new file mode 100644 index 0000000..9340a32 --- /dev/null +++ b/board/esd/hh405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/hh405/config.mk b/board/esd/hh405/config.mk new file mode 100644 index 0000000..7129ad5 --- /dev/null +++ b/board/esd/hh405/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd VOH405 boards +# + +#TEXT_BASE = 0xFFF00000 +TEXT_BASE = 0xFFF80000 +#TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0x00FC0000 diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/hh405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i +#include +#include +#include +#include +#include + + +#ifdef CONFIG_VIDEO_SM501 + +#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ + (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) + +#ifdef CONFIG_VIDEO_SM501_8BPP +#error CONFIG_VIDEO_SM501_8BPP not supported. +#endif /* CONFIG_VIDEO_SM501_8BPP */ + +#ifdef CONFIG_VIDEO_SM501_16BPP +#define BPP 16 + +/* + * 800x600 display B084SN03: PCLK = 40MHz + * => 2*PCLK = 80MHz + * 336/4 = 84MHz + * => PCLK = 84MHz + */ +static const SMI_REGS init_regs_800x600 [] = +{ +#if 1 /* test-only */ + {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */ +#else + {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */ +#endif + {0x00004, SWAP32(0x00000000)}, + /* clocks for pm1... */ + {0x00048, SWAP32(0x00021807)}, + {0x0004C, SWAP32(0x221a0a01)}, + {0x00054, SWAP32(0x00000001)}, + /* clocks for pm0... */ + {0x00040, SWAP32(0x00021807)}, + {0x00044, SWAP32(0x221a0a01)}, + {0x00054, SWAP32(0x00000000)}, + /* panel control regs... */ + {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ + {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ + {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */ + {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ + {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ + {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ + {0x80020, SWAP32(0x02580320)}, /* panel plane br location */ + {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */ + {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */ + {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */ + {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */ + {0x80200, SWAP32(0x00010000)}, /* crt display control */ + {0, 0} +}; + +/* + * 1024x768 display G150XG02: PCLK = 65MHz + * => 2*PCLK = 130MHz + * 288/2 = 144MHz + * => PCLK = 72MHz + */ +static const SMI_REGS init_regs_1024x768 [] = +{ + {0x00004, SWAP32(0x00000000)}, + /* clocks for pm1... */ + {0x00048, SWAP32(0x00021807)}, + {0x0004C, SWAP32(0x011a0a01)}, + {0x00054, SWAP32(0x00000001)}, + /* clocks for pm0... */ + {0x00040, SWAP32(0x00021807)}, + {0x00044, SWAP32(0x011a0a01)}, + {0x00054, SWAP32(0x00000000)}, + /* panel control regs... */ + {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ + {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ + {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */ + {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ + {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ + {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ + {0x80020, SWAP32(0x03000400)}, /* panel plane br location */ + {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */ + {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */ + {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */ + {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */ + {0x80200, SWAP32(0x00010000)}, /* crt display control */ + {0, 0} +}; + +#endif /* CONFIG_VIDEO_SM501_16BPP */ + +#ifdef CONFIG_VIDEO_SM501_32BPP +#define BPP 32 + +/* + * 800x600 display B084SN03: PCLK = 40MHz + * => 2*PCLK = 80MHz + * 336/4 = 84MHz + * => PCLK = 84MHz + */ +static const SMI_REGS init_regs_800x600 [] = +{ +#if 0 /* test-only */ + {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */ +#else + {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */ +#endif + {0x00004, SWAP32(0x00000000)}, + /* clocks for pm1... */ + {0x00048, SWAP32(0x00021807)}, + {0x0004C, SWAP32(0x221a0a01)}, + {0x00054, SWAP32(0x00000001)}, + /* clocks for pm0... */ + {0x00040, SWAP32(0x00021807)}, + {0x00044, SWAP32(0x221a0a01)}, + {0x00054, SWAP32(0x00000000)}, + /* panel control regs... */ + {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ + {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ + {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */ + {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ + {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ + {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ + {0x80020, SWAP32(0x02580320)}, /* panel plane br location */ + {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */ + {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */ + {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */ + {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */ + {0x80200, SWAP32(0x00010000)}, /* crt display control */ + {0, 0} +}; + +/* + * 1024x768 display G150XG02: PCLK = 65MHz + * => 2*PCLK = 130MHz + * 288/2 = 144MHz + * => PCLK = 72MHz + */ +static const SMI_REGS init_regs_1024x768 [] = +{ + {0x00004, SWAP32(0x00000000)}, + /* clocks for pm1... */ + {0x00048, SWAP32(0x00021807)}, + {0x0004C, SWAP32(0x011a0a01)}, + {0x00054, SWAP32(0x00000001)}, + /* clocks for pm0... */ + {0x00040, SWAP32(0x00021807)}, + {0x00044, SWAP32(0x011a0a01)}, + {0x00054, SWAP32(0x00000000)}, + /* panel control regs... */ + {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ + {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ + {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */ + {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ + {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ + {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ + {0x80020, SWAP32(0x03000400)}, /* panel plane br location */ + {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */ + {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */ + {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */ + {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */ + {0x80200, SWAP32(0x00010000)}, /* crt display control */ + {0, 0} +}; + +#endif /* CONFIG_VIDEO_SM501_32BPP */ + +#endif /* CONFIG_VIDEO_SM501 */ + +#if 0 +#define FPGA_DEBUG +#endif + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); + +/* fpga configuration data - gzip compressed and generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); + + +/* logo bitmap data - gzip compressed and generated by bin2c */ +unsigned char logo_bmp_320[] = +{ +#include "logo_320_240_4bpp.c" +}; + +unsigned char logo_bmp_320_8bpp[] = +{ +#include "logo_320_240_8bpp.c" +}; + +unsigned char logo_bmp_640[] = +{ +#include "logo_640_480_24bpp.c" +}; + +unsigned char logo_bmp_1024[] = +{ +#include "logo_1024_768_8bpp.c" +}; + + +/* + * include common lcd code (for esd boards) + */ +#include "../common/lcd.c" + +#include "../common/s1d13704_320_240_4bpp.h" +#include "../common/s1d13705_320_240_8bpp.h" +#include "../common/s1d13806_640_480_16bpp.h" +#include "../common/s1d13806_1024_768_8bpp.h" + + +/* + * include common auto-update code (for esd boards) + */ +#include "../common/auto_update.h" + +au_image_t au_image[] = { + {"hh405/preinst.img", 0, -1, AU_SCRIPT}, + {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE}, + {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND}, + {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND}, + {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND}, + {"hh405/postinst.img", 0, 0, AU_SCRIPT}, +}; + +int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); + + +int board_revision(void) +{ + unsigned long osrh_reg; + unsigned long isr1h_reg; + unsigned long tcr_reg; + unsigned long value; + + /* + * Get version of HH405 board from GPIO's + */ + + /* + * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO) + */ + osrh_reg = in32(GPIO0_OSRH); + isr1h_reg = in32(GPIO0_ISR1H); + tcr_reg = in32(GPIO0_TCR); + out32(GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */ + out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */ + out32(GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */ + + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x80400000; /* get config bits */ + + /* + * Restore GPIO settings + */ + out32(GPIO0_OSRH, osrh_reg); /* output select */ + out32(GPIO0_ISR1H, isr1h_reg); /* input select */ + out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ + + if (value & 0x80000000) { + /* Revision 1.0 or 1.1 detected */ + return 0x0101; + } else { + if (value & 0x00400000) { + /* unused */ + return 0x0103; + } else { + /* Revision >= 2.0 detected */ + /* rev. 2.x uses four SM501 GPIOs for revision coding */ + return 0x0200; + } + } +} + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + return 0; +} + + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile unsigned short *fpga_ctrl = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *lcd_contrast = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4); + volatile unsigned short *lcd_backlight = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6); + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + char *str; + unsigned long contrast0 = 0xffffffff; + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); + + /* + * Reset FPGA via FPGA_INIT pin + */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */ + udelay(1000); /* wait 1ms */ + out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */ + udelay(1000); /* wait 1ms */ + + /* + * Write Board revision into FPGA + */ + *fpga_ctrl |= gd->board_type & 0x0003; + if (gd->board_type >= 0x0200) { + *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; + } + + /* + * Setup and enable EEPROM write protection + */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + + /* + * Reset touch-screen controller + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST); + udelay(1000); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST); + + /* + * Enable power on PS/2 interface (with reset) + */ + *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR); + for (i=0;i<500;i++) + udelay(1000); + *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR); + + /* + * Get contrast value from environment variable + */ + str = getenv("contrast0"); + if (str) { + contrast0 = simple_strtol(str, NULL, 16); + if (contrast0 > 255) { + printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0); + contrast0 = 0; + } + } + + /* + * Init lcd interface and display logo + */ + + str = getenv("bd_type"); + if (strcmp(str, "ppc230") == 0) { + /* + * Switch backlight on + */ + *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL; + *lcd_backlight = 0x0000; + + lcd_setup(1, 0); + lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + regs_13806_1024_768_8bpp, + sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]), + logo_bmp_1024, sizeof(logo_bmp_1024)); + } else if (strcmp(str, "ppc220") == 0) { + /* + * Switch backlight on + */ + *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL; + *lcd_backlight = 0x0000; + + lcd_setup(1, 0); + lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + regs_13806_640_480_16bpp, + sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), + logo_bmp_640, sizeof(logo_bmp_640)); + } else if (strcmp(str, "ppc215") == 0) { + /* + * Set default display contrast voltage + */ + if (contrast0 == 0xffffffff) { + *lcd_contrast = 0x0082; + } else { + *lcd_contrast = contrast0; + } + *lcd_backlight = 0xffff; + /* + * Switch backlight on + */ + *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; + /* + * Set lcd clock (small epson) + */ + *fpga_ctrl |= LCD_CLK_06250; + udelay(100); /* wait for 100 us */ + + lcd_setup(0, 1); + lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + regs_13705_320_240_8bpp, + sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]), + logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp)); + } else if (strcmp(str, "ppc210") == 0) { + /* + * Set default display contrast voltage + */ + if (contrast0 == 0xffffffff) { + *lcd_contrast = 0x0060; + } else { + *lcd_contrast = contrast0; + } + *lcd_backlight = 0xffff; + /* + * Switch backlight on + */ + *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; + /* + * Set lcd clock (small epson) + */ + *fpga_ctrl |= LCD_CLK_08330; + + lcd_setup(0, 1); + lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + regs_13704_320_240_4bpp, + sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), + logo_bmp_320, sizeof(logo_bmp_320)); +#ifdef CONFIG_VIDEO_SM501 + } else { + pci_dev_t devbusfn; + + /* + * Is SM501 connected (ppc221/ppc231)? + */ + devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); + if (devbusfn != -1) { + puts("VGA: SM501 with 8 MB "); + if (strcmp(str, "ppc221") == 0) { + printf("(800*600, %dbpp)\n", BPP); + } else if (strcmp(str, "ppc231") == 0) { + printf("(1024*768, %dbpp)\n", BPP); + } else { + printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); + return 0; + } + } else { + printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); + return 0; + } +#endif /* CONFIG_VIDEO_SM501 */ + } + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming HH405"); + } else { + puts(str); + } + + if (getenv_r("bd_type", str, sizeof(str)) != -1) { + printf(" (%s", str); + } else { + puts(" (Missing bd_type!"); + } + + gd->board_type = board_revision(); + printf(", Rev %ld.%ld)\n", + (gd->board_type >> 8) & 0xff, + gd->board_type & 0xff); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + + +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) +{ + volatile unsigned short *fpga_mode = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { /* assert RESET */ + *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + } else { /* release RESET */ + *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + } +} +#endif /* CONFIG_IDE_RESET */ + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif + + +#if defined(CFG_EEPROM_WREN) +/* Input: I2C address of EEPROM device to enable. + * -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if was -1. + */ +int eeprom_write_enable (unsigned dev_addr, int state) +{ + if (CFG_I2C_EEPROM_ADDR != dev_addr) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO_SINT2. */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + break; + } + } + return state; +} + +int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int query = argc == 1; + int state = 0; + + if (query) { + /* Query write access state. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + if (state < 0) { + puts ("Query of write access state failed.\n"); + } else { + printf ("Write access for device 0x%0x is %sabled.\n", + CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + state = 0; + } + } else { + if ('0' == argv[1][0]) { + /* Disable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + } else { + /* Enable write access. */ + state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + } + if (state < 0) { + puts ("Setup of write access state failed.\n"); + } + } + + return state; +} + +U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL); +#endif /* #if defined(CFG_EEPROM_WREN) */ + + +#ifdef CONFIG_VIDEO_SM501 +#ifdef CONFIG_CONSOLE_EXTRA_INFO +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str (int line_number, char *info) +{ + DECLARE_GLOBAL_DATA_PTR; + + char str[64]; + char str2[64]; + int i = getenv_r("serial#", str2, sizeof(str)); + + if (line_number == 1) { + sprintf(str, " Board: "); + + if (i == -1) { + strcat(str, "### No HW ID - assuming HH405"); + } else { + strcat(str, str2); + } + + if (getenv_r("bd_type", str2, sizeof(str2)) != -1) { + strcat(str, " ("); + strcat(str, str2); + } else { + strcat(str, " (Missing bd_type!"); + } + + sprintf(str2, ", Rev %ld.%ld)", + (gd->board_type >> 8) & 0xff, gd->board_type & 0xff); + strcat(str, str2); + strcpy(info, str); + } else { + info [0] = '\0'; + } +} +#endif /* CONFIG_CONSOLE_EXTRA_INFO */ + +/* + * Returns SM501 register base address. First thing called in the driver. + */ +unsigned int board_video_init (void) +{ + pci_dev_t devbusfn; + u32 addr; + + /* + * Is SM501 connected (ppc221/ppc231)? + */ + devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); + if (devbusfn != -1) { + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr); + return (addr & 0xfffffffe); + } + + return 0; +} + +/* + * Returns SM501 framebuffer address + */ +unsigned int board_video_get_fb (void) +{ + pci_dev_t devbusfn; + u32 addr; + + /* + * Is SM501 connected (ppc221/ppc231)? + */ + devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); + if (devbusfn != -1) { + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr); + return (addr & 0xfffffffe); + } + + return 0; +} + +/* + * Called after initializing the SM501 and before clearing the screen. + */ +void board_validate_screen (unsigned int base) +{ +} + +/* + * Return a pointer to the initialization sequence. + */ +const SMI_REGS *board_get_regs (void) +{ + char *str; + + str = getenv("bd_type"); + if (strcmp(str, "ppc221") == 0) { + return init_regs_800x600; + } else { + return init_regs_1024x768; + } +} + +int board_get_width (void) +{ + char *str; + + str = getenv("bd_type"); + if (strcmp(str, "ppc221") == 0) { + return 800; + } else { + return 1024; + } +} + +int board_get_height (void) +{ + char *str; + + str = getenv("bd_type"); + if (strcmp(str, "ppc221") == 0) { + return 600; + } else { + return 768; + } +} + +#endif /* CONFIG_VIDEO_SM501 */ diff --git a/board/esd/hh405/logo_1024_768_8bpp.c b/board/esd/hh405/logo_1024_768_8bpp.c new file mode 100644 index 0000000..2195547 --- /dev/null +++ b/board/esd/hh405/logo_1024_768_8bpp.c @@ -0,0 +1,2544 @@ + 0x1f,0x8b,0x08,0x08,0x20,0xb5,0x06,0x40,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x2d,0x48, + 0x65,0x72,0x5f,0x64,0x74,0x5f,0x33,0x43,0x5f,0x31,0x30,0x32,0x34,0x78,0x37,0x36, + 0x38,0x5f,0x32,0x35,0x36,0x2e,0x62,0x6d,0x70,0x00,0xec,0xbd,0x0b,0x74,0x23,0xd7, + 0x79,0xa0,0x59,0x14,0x0d,0x1d,0x71,0xb6,0xc9,0x43,0x37,0xe4,0xe4,0xa8,0xa2,0x0c, + 0x80,0x58,0xeb,0x14,0x48,0x77,0x7a,0xe2,0xb4,0x2c,0xcb,0x56,0x4b,0xed,0xb6,0x8e, + 0xc2,0x84,0x4e,0x6d,0x83,0x05,0x80,0x8b,0x09,0x0c,0xec,0x28,0x1c,0xc3,0x69,0x39, + 0x41,0x4f,0xec,0xc4,0xde,0x44,0xc1,0x60,0x6d,0xb5,0xdb,0x8c,0x9b,0x09,0x99,0x75, + 0xbc,0xd3,0xed,0xce,0x64,0xc6,0x36,0xd0,0x72,0xa4,0x90,0x9d,0x50,0x4b,0xb5,0x12, + 0xef,0x78,0x26,0xb6,0x3c,0x93,0x2c,0x8f,0x93,0x33,0x50,0x9e,0x92,0x10,0xc2,0xe3, + 0xcd,0x61,0x98,0xd6,0x63,0x77,0x04,0xd2,0x40,0x09,0x38,0x7b,0xef,0xad,0xd7,0x7d, + 0x15,0x50,0x20,0xd9,0x0f,0xa9,0xff,0x0f,0x20,0x88,0x47,0xbd,0xeb,0xfe,0x8f,0xfb, + 0xdf,0xff,0xde,0x7b,0xfc,0xa7,0xde,0xfd,0x96,0x03,0x0a,0xe6,0xdd,0x6f,0x51,0x14, + 0x0d,0xbf,0x41,0xff,0x95,0x61,0x45,0x19,0x52,0x6e,0x53,0x1c,0xde,0xfe,0x23,0xd6, + 0x9f,0xc3,0x5b,0x6e,0x79,0x8b,0xf2,0xe8,0xa7,0x1e,0x55,0xee,0x3c,0xfe,0x98,0xf2, + 0xf5,0x3f,0xfe,0x9a,0xf2,0x53,0x8f,0xfd,0x89,0xf2,0xfe,0x0f,0x3c,0xa8,0xdc,0x35, + 0xf7,0x5f,0x94,0xf2,0x97,0xd6,0x95,0xb7,0xfe,0xd0,0x43,0xca,0x0b,0xdf,0x79,0x41, + 0x79,0xf0,0xe1,0xc7,0x94,0x7f,0xf7,0xcd,0x2d,0x25,0xfb,0xf0,0x9c,0x72,0xe1,0x4b, + 0x17,0x94,0x3b,0x7f,0xe8,0x4e,0xe5,0xe4,0x57,0xbe,0xab,0x1c,0xf9,0xd4,0x15,0xe5, + 0x87,0x3e,0x50,0x50,0xde,0xf6,0xae,0x82,0xf2,0x8e,0x5f,0xfc,0xae,0x72,0xd7,0xcc, + 0x57,0x94,0x8f,0x3e,0xf6,0xb8,0xf2,0xcd,0x3f,0xfb,0x7b,0xe5,0x9f,0xcd,0x3d,0xae, + 0xfc,0x6f,0xab,0xff,0xa0,0xdc,0xfa,0xd6,0xbb,0x94,0xff,0xfe,0xda,0x6b,0xca,0x4f, + 0xfe,0xef,0x57,0x94,0x77,0x7f,0xec,0x4f,0x94,0xd8,0xcc,0xbc,0x72,0xd7,0x91,0x1f, + 0x57,0xfe,0xbc,0xf6,0x9c,0xf2,0x63,0x3f,0x76,0x44,0x39,0xfb,0x9b,0x9f,0x57,0x7e, + 0x74,0xe6,0x51,0xe5,0xc4,0xa3,0x8f,0x2b,0x3f,0xfb,0x85,0xff,0xac,0xac,0xd4,0xfe, + 0xbb,0x72,0xe1,0xc9,0xff,0xa2,0x7c,0xf3,0x3b,0xaf,0x2b,0x2b,0xab,0x4f,0x29,0xb7, + 0xdf,0x7e,0xbb,0x72,0xc2,0x48,0x2a,0x1f,0xfd,0x85,0x8f,0x2b,0xbf,0xfa,0xd4,0x6b, + 0xca,0x0f,0xff,0xc2,0xf3,0xca,0xcf,0x7c,0xe5,0x35,0xe5,0x07,0x3f,0xf0,0xcb,0xca, + 0xe3,0x7f,0xfc,0x82,0xb2,0xf4,0xc7,0x3b,0x4a,0xf8,0xed,0xef,0x51,0xee,0xfb,0xb5, + 0x2b,0xca,0x1d,0xef,0xfb,0x59,0xe5,0xae,0x87,0xff,0x48,0x31,0xce,0x5f,0x51,0x3e, + 0x79,0xfa,0x8b,0x4a,0xed,0x85,0x4d,0xe5,0x6d,0x93,0x3f,0xa9,0x9c,0xf9,0xc2,0x13, + 0x4a,0xf6,0xc3,0x8f,0x29,0x5f,0xf8,0xf2,0x53,0xca,0xdb,0x67,0xce,0x2b,0xb1,0xe9, + 0x79,0xe5,0x03,0x9f,0xfe,0x1b,0xe5,0x7f,0xfc,0xe9,0x27,0x94,0xb1,0x1f,0xd0,0xd0, + 0xf1,0xff,0xb4,0xf2,0xc2,0xdf,0xb7,0x94,0xd0,0xc8,0xdb,0x94,0x7b,0x7e,0x3c,0xa3, + 0xdc,0x75,0xf2,0x39,0x25,0xf9,0x2f,0x7f,0x59,0x79,0xbd,0xfb,0xba,0x72,0x71,0xed, + 0x4f,0x94,0x5f,0xfc,0xea,0xa6,0xf2,0xc3,0xbf,0x7c,0x45,0xf9,0xd0,0xe7,0xff,0x5a, + 0xf9,0xfc,0xa5,0x3f,0x57,0xfe,0xe6,0xf9,0x17,0x94,0x7f,0xbf,0xfe,0xba,0x72,0xe7, + 0x7d,0x9f,0x54,0x7e,0xed,0x73,0x67,0x95,0x6f,0xfe,0xe9,0xba,0xf2,0x8f,0x57,0xae, + 0x28,0xef,0x7c,0xe7,0x3b,0x95,0x7b,0xdf,0x77,0x9f,0xf2,0x03,0x77,0xde,0xa9,0x1c, + 0xf9,0x95,0xbf,0x55,0xfe,0xd3,0x8b,0xaf,0x2b,0x5f,0x7d,0xe2,0x49,0xe5,0xc7,0x3e, + 0xfd,0x9a,0x72,0xf6,0xff,0xdc,0x52,0xbe,0xf0,0xc5,0x0b,0xca,0x8f,0x4e,0xfd,0x92, + 0x92,0xf9,0xe9,0xac,0xf2,0xf1,0x5f,0xfc,0xa4,0xf2,0xe9,0x3f,0x7a,0x4d,0x29,0x7d, + 0xfe,0x19,0xe5,0xae,0xec,0x65,0xe5,0x77,0x9e,0xf9,0x2b,0x65,0xee,0x67,0xfe,0xa5, + 0x72,0xef,0x47,0x9f,0x50,0xde,0xf7,0xf1,0x3f,0x54,0x9e,0xf9,0xa3,0xaf,0x29,0x3f, + 0xf6,0xc8,0x33,0x4a,0xfa,0xc2,0x6b,0xca,0xdb,0xde,0xf9,0x3f,0x2b,0x6f,0xff,0xe0, + 0xbf,0x51,0xa6,0x3f,0xf7,0x37,0x8a,0xfa,0xbe,0xac,0xf2,0x33,0x5f,0xfc,0x1b,0x65, + 0x7a,0xfa,0x83,0x8a,0xf6,0xc8,0x9f,0x2a,0xef,0xf9,0xa9,0x93,0xca,0x07,0x7f,0xeb, + 0x35,0xe5,0x81,0x5f,0xf9,0x13,0xe5,0x83,0xa9,0x39,0xe5,0xa9,0xbf,0x7d,0x5d,0x39, + 0x92,0xfe,0xbc,0x32,0xf6,0x83,0xf7,0x28,0x87,0x4b,0xaf,0x29,0xbf,0xf0,0x95,0xe7, + 0x95,0xcd,0xff,0xef,0x75,0xe5,0x03,0x9f,0x7b,0x4d,0x99,0xfb,0xa5,0xc7,0x94,0xfa, + 0x95,0xd7,0x95,0x03,0xff,0xc3,0x01,0xe5,0x7f,0x2a,0x9e,0x53,0x9e,0xfb,0xcb,0x17, + 0x94,0x1f,0xfd,0x99,0x0b,0x8a,0xfe,0xa1,0x47,0x95,0xe2,0xaf,0xfe,0x1b,0xe5,0xc7, + 0x3f,0x74,0x46,0xf9,0xbf,0xff,0xf4,0x39,0xe5,0x17,0x3e,0xf7,0xbb,0xca,0xd1,0xfb, + 0x1f,0x54,0x0e,0xff,0xc8,0x11,0xe5,0xa3,0x3f,0xff,0x71,0xe5,0x6b,0x7f,0xd1,0x56, + 0x2e,0xfc,0xc1,0x5f,0x2b,0x9f,0xfa,0xdc,0x17,0x94,0x27,0x97,0x9f,0x52,0x96,0x7e, + 0xfb,0x19,0xe5,0x27,0x1f,0xfd,0x43,0xe5,0x8b,0x17,0xbe,0xa2,0x7c,0xed,0xff,0xfa, + 0xa6,0xf2,0x2f,0x7e,0x7e,0x5e,0x29,0x7c,0xee,0x29,0xc5,0xf8,0xb5,0x75,0xe5,0xf7, + 0xd6,0xff,0x51,0x39,0x92,0x9d,0x57,0x1e,0xf8,0xe9,0xff,0x55,0xf9,0xf9,0x27,0x5f, + 0x53,0xb2,0xb9,0x39,0x25,0xfc,0x8e,0xa4,0x52,0xfa,0xed,0x6f,0x29,0x1f,0xd4,0x93, + 0xca,0x67,0x2e,0xbd,0xa0,0x5c,0xfe,0x0f,0x7f,0xad,0x9c,0xbe,0xf8,0x57,0xca,0x07, + 0x3f,0xfc,0x79,0xe5,0x67,0x9f,0xb8,0xa2,0xdc,0xf9,0x23,0xf7,0x29,0xf1,0xec,0x17, + 0x95,0xa5,0xaf,0x6d,0x29,0x9f,0xfc,0x95,0x47,0x95,0x47,0x1e,0xf9,0xa8,0xf2,0xb5, + 0x3f,0x5e,0x57,0x9e,0xff,0x6f,0xe8,0x9e,0xbe,0xfd,0x9d,0x4a,0xf2,0x17,0x1e,0x55, + 0xa2,0x0f,0x7d,0x5e,0xb9,0xf3,0xdd,0x1f,0x57,0x6e,0xfb,0xbe,0x23,0xca,0xa3,0xa5, + 0xc7,0x94,0xc7,0x3e,0x73,0x56,0x79,0xf0,0xa1,0x0f,0x2a,0x27,0x7e,0xe6,0x33,0xca, + 0x07,0x1f,0xfe,0xa8,0xf2,0xe5,0xca,0x93,0xca,0x3d,0xef,0xbe,0x4f,0xf9,0xfd,0xbf, + 0x78,0x5d,0x79,0x6a,0xed,0x6b,0xca,0xdb,0xbe,0xef,0x4e,0x25,0x95,0xce,0x2a,0xff, + 0xf4,0x9f,0xde,0xa5,0x2c,0xfe,0xee,0xba,0xf2,0xdc,0xd6,0xeb,0xca,0xd7,0xfe,0xf4, + 0x05,0xe5,0x7f,0x39,0xf5,0x79,0xe5,0xa3,0x9f,0x79,0x0a,0x1d,0xd3,0x07,0x95,0x3f, + 0xfe,0xcb,0x4d,0xe5,0xb1,0x3f,0xbc,0xa2,0xdc,0xf5,0xde,0x0f,0x2a,0x8f,0xff,0xc1, + 0x37,0x95,0xd8,0x4f,0x3e,0xaa,0xbc,0x75,0xec,0x76,0xe5,0x41,0x3d,0xab,0xfc,0xca, + 0xf2,0xa6,0xf2,0xa3,0xfa,0x27,0x94,0xc7,0xd1,0xb1,0xde,0x9b,0x3b,0xaf,0x3c,0xfa, + 0xbb,0x2f,0x28,0xeb,0xdf,0x7e,0x4e,0x59,0xfe,0xd6,0x77,0x95,0xfb,0x3e,0x73,0x45, + 0xf9,0xd1,0x07,0x0b,0xca,0xb1,0x0f,0x3f,0xae,0xa4,0x7e,0xeb,0x1f,0x94,0x43,0xc6, + 0x19,0xe5,0xf3,0xbf,0x75,0x4e,0x39,0x66,0xfc,0xa2,0x92,0x7b,0xb4,0xaa,0x7c,0xfb, + 0xff,0x79,0x5d,0xf9,0xc3,0x6f,0xfc,0xa5,0x72,0xe1,0x5b,0x6d,0xe5,0xc1,0xb3,0x57, + 0x94,0x1f,0x3e,0xfa,0xb3,0xca,0xa1,0xb9,0xcb,0x4a,0xee,0xb7,0xb7,0x94,0xb3,0x9f, + 0xf9,0xbc,0xf2,0x42,0xfd,0xbb,0xca,0x7b,0x72,0x5f,0x51,0x8e,0x94,0xfe,0x51,0x59, + 0x5f,0x5f,0x57,0x8e,0xfe,0xea,0xdf,0x2a,0x0b,0x5f,0x6b,0x2a,0x53,0x3f,0xff,0x15, + 0x25,0xf5,0xeb,0x7f,0xad,0x68,0xef,0xfb,0x69,0xe5,0xe7,0xfe,0xed,0x0b,0xca,0x4b, + 0x2f,0xbf,0xa6,0xfc,0xeb,0x5f,0xff,0xaa,0x72,0xf6,0xd7,0x3f,0xaf,0xcc,0x2d,0xfc, + 0x67,0xe5,0xce,0x87,0x3e,0xa7,0xfc,0xc0,0xbb,0x1f,0x51,0xee,0x4a,0x3f,0xa1,0xfc, + 0x93,0xef,0xfb,0x61,0xe5,0xae,0x9f,0xff,0x6b,0x65,0xf1,0x4b,0xdf,0x54,0xee,0x3b, + 0x79,0x41,0x59,0x5c,0x7b,0x41,0x39,0x7a,0xfa,0x35,0x65,0x67,0xfb,0x75,0xe5,0x9b, + 0xdf,0x5a,0x57,0xbe,0xfb,0xf7,0x57,0x94,0x77,0xbc,0xe3,0x9d,0xca,0xa7,0x3e,0xfd, + 0x98,0xf2,0x9f,0xbe,0xf1,0x4d,0xa5,0xf1,0xdf,0xd0,0x71,0xcf,0x9d,0x55,0xfe,0xfd, + 0x97,0xbf,0xa2,0xbc,0xfd,0xed,0x77,0x29,0x73,0x5f,0xbe,0xa2,0x4c,0x01,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x37,0x34,0x85, + 0x09,0x8f,0xec,0x54,0xf3,0x7a,0x1f,0x0e,0x00,0x00,0xd7,0x90,0x9a,0xe2,0x31,0x77, + 0xbd,0x0f,0x06,0x00,0x80,0x6b,0x0a,0x2d,0xff,0xd5,0xeb,0x7d,0x30,0x00,0x00,0x5c, + 0x53,0xc0,0xfe,0x03,0xc0,0xcd,0x4b,0x8c,0xb6,0xff,0xea,0xf5,0x3e,0x1a,0x00,0x00, + 0xae,0x25,0x60,0xff,0x01,0xe0,0xe6,0x05,0xe4,0x1f,0x00,0x6e,0x5e,0x40,0xfe,0x01, + 0xe0,0xe6,0x85,0xa9,0xff,0x5f,0xef,0x83,0x01,0x00,0xe0,0x9a,0x02,0xf6,0x1f,0x00, + 0x6e,0x5e,0x40,0xfe,0x01,0xe0,0xe6,0x05,0xf2,0x7f,0x00,0xe0,0xe6,0x05,0xec,0x3f, + 0x00,0xdc,0xbc,0x40,0xfe,0x0f,0x00,0xdc,0xbc,0x80,0xfd,0x07,0x80,0x9b,0x97,0x18, + 0xc8,0x3f,0x00,0xdc,0xb4,0x80,0xfc,0x03,0xc0,0x9b,0x10,0x55,0x35,0x4c,0x53,0xd7, + 0x4d,0xc3,0xe8,0x59,0xab,0x97,0xc7,0xff,0x55,0x63,0x07,0xaf,0x1a,0x3c,0x1e,0x40, + 0x76,0x36,0xd2,0x6f,0x67,0xfb,0x86,0x8a,0xf6,0x66,0x1a,0xd7,0x64,0x57,0x03,0xa1, + 0x1a,0x86,0x3e,0x12,0xf8,0x1a,0xb8,0x77,0x28,0xe8,0xf2,0x2a,0x59,0x1e,0xdd,0x97, + 0x37,0x40,0xa0,0x06,0x5d,0x8a,0x00,0xc5,0x0f,0xb8,0x0a,0x18,0xba,0x96,0xa8,0x4e, + 0xa4,0x92,0xdd,0x6e,0x3a,0x9d,0xee,0x26,0x53,0x13,0xd5,0xec,0xb0,0xe9,0xb3,0xac, + 0xa4,0xfe,0x6f,0x66,0xf2,0xc5,0xe8,0x18,0x5e,0x33,0x34,0x97,0x6d,0xf4,0xbd,0x7d, + 0xaa,0xae,0xb5,0x72,0xc5,0x28,0xd9,0x57,0x37,0x55,0x3c,0xd0,0xd2,0x74,0x7e,0x9d, + 0x1d,0x13,0x95,0xf4,0x9e,0x18,0xb4,0x14,0x18,0xde,0xe2,0x92,0xd2,0xa3,0x46,0xb2, + 0x73,0xa1,0xe4,0x18,0x3a,0xbc,0x62,0x45,0x73,0x4f,0xcb,0x40,0xc5,0xcd,0x5a,0x8d, + 0x96,0x26,0x73,0xc7,0xdd,0x03,0xb3,0x21,0x6a,0x07,0xbc,0xf0,0xa9,0xf8,0xb7,0x1d, + 0x72,0x44,0x26,0xbf,0x73,0x63,0xc7,0x3b,0x5e,0xf1,0x42,0xe8,0x5a,0x85,0x5c,0x86, + 0x64,0x6a,0x6e,0x34,0xe2,0x6e,0xce,0x3e,0x2c,0xc3,0xdc,0x61,0x76,0x32,0xdc,0xa9, + 0xe4,0x42,0xd1,0xe4,0x98,0x75,0x83,0x2a,0x99,0x48,0x9f,0xeb,0xac,0x46,0x3a,0xf9, + 0x89,0x54,0x17,0x2f,0x3f,0xd6,0x8d,0x16,0x73,0xad,0x4c,0xc3,0x3d,0xf2,0x3e,0xd7, + 0x6b,0xc7,0x3d,0x66,0xe6,0x64,0x55,0xeb,0x3b,0xf1,0x22,0x18,0xf6,0x0f,0x86,0x29, + 0x53,0xb1,0x86,0xfb,0xa3,0xbf,0x02,0xd6,0x0b,0xb1,0x39,0x74,0x29,0xba,0xb8,0x44, + 0x44,0x43,0x39,0xf9,0xd9,0xb9,0x17,0xc6,0x67,0x37,0xce,0x39,0xed,0xf8,0x15,0x5d, + 0x40,0xc2,0x4e,0x23,0x3b,0x97,0x8a,0x97,0x14,0x8e,0x52,0x37,0x37,0xaa,0xcb,0x96, + 0x17,0xe4,0x5f,0x6f,0x25,0xe9,0xb5,0xe3,0xa1,0x6c,0xcf,0xeb,0x5f,0x8e,0x15,0xc7, + 0xf8,0x9d,0xa5,0x43,0x2d,0x46,0x6d,0x44,0x92,0xa8,0xcc,0xf6,0x79,0xa6,0xbb,0x29, + 0xb7,0x14,0xe4,0xbc,0xaf,0xbb,0xc3,0xdc,0xfe,0x8c,0x4c,0x31,0x4d,0x9d,0x56,0xb4, + 0x62,0x9d,0x95,0x3a,0xd7,0xc5,0x82,0x81,0x57,0x2a,0x7a,0xbb,0x6e,0x50,0x3b,0x9e, + 0xa0,0x8e,0xc8,0xef,0x7b,0x4c,0xcc,0x3d,0xa0,0xb1,0xee,0x28,0xfb,0x93,0x5a,0xf4, + 0x8e,0xf8,0xb3,0x11,0xee,0xb7,0x46,0x35,0x49,0x5f,0x82,0x5c,0xc1,0xda,0x6e,0xa7, + 0x6b,0x6d,0xaa,0x3b,0x96,0x74,0x4e,0xa5,0xde,0xa9,0x86,0xc6,0xf8,0x3b,0x14,0x0f, + 0x25,0xb8,0x2d,0xd2,0xe8,0x89,0x50,0x5a,0xe1,0xd7,0x48,0x25,0xec,0x5f,0x27,0xa9, + 0xeb,0x95,0x11,0xd6,0x6d,0x91,0xef,0xad,0x53,0xca,0x52,0xdf,0x2f,0x74,0xc9,0xa1, + 0x91,0x15,0xe7,0xa9,0xef,0xd7,0xf1,0xc5,0x19,0x7b,0x86,0xac,0x70,0x40,0xd8,0x9a, + 0x19,0x25,0xab,0x91,0xbd,0x85,0xa4,0x0a,0xc0,0xec,0xe4,0xba,0xc2,0xd9,0x45,0x27, + 0x0b,0xdc,0xc2,0xe6,0x99,0x31,0xeb,0xc2,0x60,0xab,0x21,0x14,0x31,0xb5,0x68,0x5f, + 0x35,0xf4,0x8c,0xf6,0xb8,0x30,0x00,0xcb,0x68,0x34,0xce,0x97,0x13,0x97,0xee,0xa4, + 0xe4,0x42,0x72,0xf2,0xaf,0x8e,0x26,0x85,0xf5,0x52,0x19,0x5f,0xdb,0xd4,0xa8,0x0a, + 0xc2,0x6f,0xdf,0xf0,0x62,0xc7,0xbb,0xdf,0x6d,0xff,0x63,0xa2,0x48,0x3b,0x85,0x40, + 0x0d,0x79,0x5f,0x96,0x0a,0xcc,0xfe,0xd4,0x42,0x88,0x5f,0xad,0x9b,0xc0,0x3b,0x32, + 0xa2,0xde,0xe1,0x7a,0x47,0x5b,0xa0,0xca,0x61,0x88,0x3a,0x89,0x36,0xf5,0x7d,0x8a, + 0x3b,0xb9,0x21,0x6a,0xdb,0x31,0xf6,0x27,0x83,0xba,0x36,0xf1,0x06,0xf3,0x53,0xa4, + 0xca,0x9f,0x63,0x3c,0x47,0xae,0x76,0xc5,0x3b,0x95,0xb6,0x64,0x0f,0x34,0x63,0xb2, + 0xfb,0x43,0x36,0x9e,0x97,0x5f,0x65,0x47,0xd3,0x4d,0x50,0xdf,0x75,0x84,0xb5,0x27, + 0xa9,0x5f,0x13,0xd4,0xf7,0xa3,0xd4,0xf7,0x39,0xea,0xfb,0x61,0xea,0xe2,0x14,0x85, + 0x3b,0x1f,0xa1,0xce,0x33,0x29,0x73,0x82,0x5a,0x62,0x01,0xb2,0x4e,0x3f,0x15,0x63, + 0x0c,0x90,0x4e,0x9d,0x53,0x5a,0x30,0x4d,0xcc,0xa5,0x06,0xf9,0x0f,0x4c,0xcb,0xa7, + 0x6c,0xd9,0xd7,0x39,0x2f,0x5c,0x68,0xb6,0xfe,0x6f,0xe4,0x05,0xcf,0x01,0xdf,0xba, + 0xaa,0xdc,0x05,0x30,0x87,0x04,0xa3,0x44,0x11,0x72,0xca,0xfb,0x54,0x23,0x90,0xfc, + 0x8f,0xc9,0xe4,0x5f,0x61,0xe4,0xdf,0x68,0xc9,0xb6,0x54,0x44,0xa2,0x68,0x76,0xbd, + 0xfd,0x7a,0x65,0x96,0x2e,0xca,0x29,0xca,0xfe,0xb4,0x7d,0xbe,0xe7,0xaf,0x60,0x82, + 0xfd,0x89,0x52,0x32,0x4a,0x89,0x91,0x7f,0x8d,0xfa,0xc5,0xa5,0x8b,0x65,0x71,0xce, + 0xfd,0xe8,0x6a,0x8c,0x84,0xef,0x25,0xe8,0xd6,0x24,0x16,0x55,0xcd,0xfa,0x48,0x94, + 0x32,0x61,0x2f,0x91,0xa3,0xbe,0x1b,0x15,0xd6,0xcf,0x53,0xbf,0xb6,0xa8,0xef,0x3b, + 0x92,0x2d,0x61,0xb6,0xa9,0x6b,0x1c,0x12,0xe5,0x9f,0xba,0xe5,0x5d,0xd1,0x6c,0xfb, + 0x1e,0x2b,0x26,0x49,0x1f,0x9c,0xee,0xdd,0x31,0x99,0xfc,0x47,0xbd,0x5f,0xd9,0x4b, + 0x0d,0xf4,0x22,0xdb,0xe3,0xf2,0x63,0x52,0x05,0x6e,0x05,0xc6,0xfe,0x9b,0x55,0x9f, + 0xd5,0x8a,0xb2,0xba,0x43,0x3b,0xd5,0x7b,0x5f,0xae,0xf4,0x34,0x64,0x4a,0x45,0x20, + 0xed,0x54,0x90,0x9b,0x7e,0xf2,0x6f,0xcc,0xc9,0xd7,0x8c,0x16,0xa6,0x74,0xaf,0x58, + 0x52,0x65,0x79,0xc9,0xc7,0xce,0xd3,0xf2,0x1f,0xe5,0x8a,0xf8,0xb2,0xec,0x0c,0xec, + 0xfd,0x47,0xbd,0x9f,0xe2,0x33,0xde,0xf7,0xcd,0xac,0x5c,0xc1,0xc5,0x13,0x2a,0x65, + 0x9b,0xd3,0x8e,0x19,0xeb,0x71,0x8f,0x4a,0x55,0x41,0x01,0x98,0x73,0xbe,0x57,0xcf, + 0x69,0xaf,0xd9,0x5f,0xf9,0x6f,0xfb,0x38,0x4d,0x16,0x3a,0x75,0xaa,0x82,0xfc,0xeb, + 0xf4,0x91,0x48,0xc8,0x51,0xe3,0x4b,0x07,0x97,0xff,0x38,0xc8,0x7f,0x60,0xb4,0x7e, + 0xa2,0x16,0x1f,0x65,0x6f,0x29,0x2d,0xff,0x39,0x1f,0xf9,0x42,0x14,0x47,0x84,0x5d, + 0xad,0xf6,0x32,0xfe,0x18,0xd7,0x7b,0x0e,0xe6,0xff,0x4b,0xed,0x3f,0xed,0xff,0xab, + 0x7e,0xda,0x49,0x89,0x46,0x28,0x17,0x83,0xaa,0xb3,0x0e,0x07,0x90,0xff,0x7d,0xf0, + 0xff,0x33,0x7e,0xe7,0x17,0xcf,0x1a,0x45,0xf7,0x43,0xd7,0x29,0xe4,0x1d,0x9f,0xa5, + 0xad,0xa3,0xe7,0x14,0x80,0x5e,0xf4,0x5f,0xd6,0x6e,0xaf,0x69,0xd2,0x52,0x27,0xfa, + 0xff,0xf3,0xd4,0xaf,0xb4,0x42,0x5b,0xa4,0xbe,0xa7,0xfd,0xff,0xf6,0xae,0xfd,0xff, + 0x7e,0x06,0x81,0xd9,0x0d,0x2d,0xff,0x63,0xbd,0xfd,0x7f,0x90,0xff,0xc0,0xb4,0xfb, + 0x9a,0xda,0x78,0x96,0x59,0x81,0x6e,0xff,0xef,0x25,0xa6,0x7c,0xb9,0x54,0x33,0xfd, + 0xc4,0x9f,0xb2,0xff,0x81,0xe4,0xff,0x99,0x7e,0xfe,0x7f,0xcd,0xff,0xdc,0x42,0x9a, + 0xb7,0x0b,0xaa,0x17,0x93,0x9f,0x9c,0xd3,0x0a,0x69,0xef,0xfe,0x7f,0xc4,0xdf,0xe7, + 0x8d,0x6b,0xde,0xb9,0xb8,0xd2,0xb2,0xd6,0xf3,0x1e,0x55,0xd8,0x86,0x8a,0x1e,0xe2, + 0xaf,0x54,0xec,0x85,0x68,0xf9,0x67,0xef,0x2e,0x26,0x88,0xfd,0xa7,0x05,0x33,0xb8, + 0xff,0xcf,0xc9,0x7f,0xa3,0x97,0xef,0x2f,0xec,0xa6,0xde,0xdb,0xfe,0x53,0xdb,0x02, + 0xff,0x3f,0x38,0x91,0xbe,0x52,0xa9,0xa4,0x99,0x2a,0x40,0xad,0xef,0xf2,0xf6,0x4d, + 0xa8,0xb1,0x3b,0x2a,0xf4,0xdf,0x91,0x67,0xff,0x03,0xf9,0xff,0xfd,0xec,0x3f,0x6d, + 0x30,0x04,0x8a,0xde,0x2e,0x2a,0xde,0x41,0x06,0xf1,0xff,0x79,0xfb,0xdf,0xcb,0xff, + 0x97,0x1a,0x25,0xd5,0xdf,0x6b,0x42,0x9e,0x89,0x77,0xd0,0x51,0x47,0xd1,0xf4,0x76, + 0x87,0xe2,0x74,0x04,0xdf,0xe8,0xe9,0x50,0x3b,0x87,0x17,0xdc,0xfe,0x07,0x91,0x7f, + 0xc6,0xff,0x17,0xb6,0x16,0xf1,0xf5,0xff,0x23,0xd1,0x5e,0xc7,0x2a,0xec,0x86,0x8e, + 0xff,0x75,0xc1,0xfe,0xef,0x13,0x66,0x2f,0x21,0xb1,0x89,0xd2,0x57,0x3b,0xa8,0xfc, + 0x2b,0x5d,0x26,0x0a,0xab,0xf3,0x37,0xbb,0x94,0x4e,0xa6,0x52,0x4f,0x25,0xd3,0x54, + 0xe1,0x19,0xd0,0xfe,0xa7,0x5d,0x43,0x2c,0xb7,0xff,0x5c,0x68,0x33,0xde,0x8d,0xa6, + 0xa2,0x42,0x33,0x9a,0xc2,0x94,0xf1,0x40,0xfe,0x3f,0x67,0xff,0x7b,0xf9,0xff,0xd4, + 0x49,0x7b,0x85,0xb2,0xcd,0x6a,0xc2,0x12,0x3a,0xae,0x54,0x57,0x72,0xc6,0xae,0xfc, + 0x3b,0x97,0xa3,0x14,0x4f,0xa2,0x45,0x93,0xfc,0xa2,0x74,0xab,0x9a,0x7f,0xa8,0x90, + 0x3e,0xbc,0xde,0xf1,0x7f,0xda,0xfe,0xd3,0x0a,0x6d,0x77,0xf5,0xff,0xb2,0x9f,0xfd, + 0x37,0xe8,0xa3,0x20,0xa7,0x87,0x4b,0x44,0x2a,0x49,0xb7,0x05,0xe6,0xa8,0xcd,0xf5, + 0xa9,0xff,0x83,0xfc,0xef,0x0a,0xaa,0x88,0x96,0xe2,0x63,0xc9,0x68,0xf2,0x19,0x89, + 0x84,0x50,0x16,0x92,0xf1,0xff,0x9d,0xbb,0x31,0xd1,0x1a,0x5d,0x4c,0xe4,0x78,0x4d, + 0x32,0x49,0xad,0xc5,0xd9,0xbc,0x52,0xaa,0x35,0x5c,0x36,0x54,0xd5,0xd8,0x29,0x17, + 0x62,0x39,0x27,0x7f,0xc0,0x2d,0x6c,0xc1,0xec,0x7f,0xb7,0xb7,0xff,0x4f,0x0b,0x1f, + 0x12,0xa6,0x44,0xdb,0x54,0x37,0x8d,0xba,0x56,0x15,0xfc,0x10,0xaa,0x8c,0x07,0xb2, + 0xff,0x9c,0xfc,0xf7,0xb2,0xff,0x9f,0xa5,0x4e,0xd9,0x2d,0x94,0x15,0x6a,0x05,0x25, + 0x3d,0xa7,0xe9,0x86,0xba,0x69,0x36,0x12,0x42,0x5d,0xd8,0x95,0x25,0x52,0xf2,0xd3, + 0xc5,0x56,0x26,0x62,0xe2,0x45,0x23,0xa3,0x45,0xe6,0xfa,0x94,0x34,0x77,0x87,0xdb, + 0x7c,0xbb,0x5f,0x3c,0x54,0xdd,0xea,0x2c,0xc6,0xf2,0x45,0x72,0x8d,0x1d,0x59,0xbf, + 0x4c,0x2d,0x21,0xc6,0xff,0xe8,0xf6,0xbf,0xab,0x68,0xff,0x13,0xec,0x4d,0x8e,0xe6, + 0x33,0x65,0x53,0x45,0xa7,0xa7,0xb7,0x47,0xab,0x4e,0x89,0x80,0xfa,0xff,0xd5,0xc6, + 0x96,0x9d,0x52,0x32,0x97,0x28,0x44,0xea,0xc6,0x8e,0xa9,0x37,0x6a,0x13,0xbc,0x88, + 0xd0,0xa6,0x5c,0x90,0xff,0xf8,0x64,0xc3,0x8a,0xd2,0x96,0x2b,0xec,0x7a,0x69,0x6a, + 0x2d,0x36,0xcc,0x18,0xca,0x6c,0x52,0x87,0xd0,0x34,0x33,0xe7,0xc8,0x9a,0xae,0xf5, + 0x5c,0x67,0x37,0xd4,0x8d,0x65,0x6b,0xb5,0x6c,0x2d,0xcb,0xd1,0x71,0xe4,0xa3,0x29, + 0xf5,0xff,0x19,0x25,0x32,0xe7,0x15,0x98,0x46,0x8e,0xd3,0x2e,0x54,0x0d,0x78,0xaf, + 0xf1,0xbf,0x20,0xfe,0x3f,0xa3,0xad,0xa2,0x9e,0xbb,0x62,0x26,0xb8,0xcb,0xee,0xca, + 0x7f,0xbd,0xfb,0x6c,0x28,0x41,0x67,0xc4,0x6d,0x76,0x18,0x5d,0xeb,0x76,0xc3,0x50, + 0x39,0xef,0x3f,0x5d,0xdd,0x36,0x9c,0x6b,0x3c,0xdc,0x4a,0xb9,0x35,0x85,0xde,0xfe, + 0xbf,0x5f,0xfb,0x7f,0x10,0xf9,0x97,0xc4,0xff,0x7c,0xda,0xff,0xca,0xcc,0x29,0x24, + 0x6b,0xb4,0x6a,0x68,0x1a,0x85,0x49,0xe2,0x06,0xec,0xce,0xfe,0x43,0xfd,0x7f,0x00, + 0x70,0x59,0x88,0xe6,0x0b,0xcc,0xe5,0x6f,0xe4,0x39,0x1f,0x93,0x2a,0x06,0xbc,0xff, + 0xdf,0xed,0x78,0x6d,0x34,0x19,0xd6,0x05,0x18,0x72,0x7f,0x50,0xe9,0xa8,0x54,0xa9, + 0x22,0x36,0x5a,0xaf,0xe3,0x2c,0x10,0x77,0x2f,0x5c,0xe0,0xbe,0x94,0x10,0x96,0x67, + 0x90,0xdb,0x7f,0xba,0xb8,0x16,0x99,0x3c,0xd6,0x21,0x56,0x01,0x50,0xf2,0xbf,0xdf, + 0xf6,0x3f,0xea,0xfd,0xe4,0xca,0x3f,0x53,0x8e,0x99,0xd0,0x8a,0xf6,0x3d,0xe6,0xb8, + 0x5c,0x59,0xda,0x1c,0xd2,0x36,0xb9,0x53,0x66,0x5a,0x10,0xdc,0x8a,0xc2,0x30,0x7b, + 0xdb,0xbc,0x84,0x0a,0xeb,0x68,0x96,0x9c,0x9b,0x4c,0x7b,0xde,0xbb,0x6b,0xff,0xf3, + 0xb5,0xff,0x81,0xe3,0x7f,0xb4,0x96,0x51,0x72,0x62,0x73,0x71,0x3d,0x9b,0x2a,0xf9, + 0xda,0x7f,0xa8,0xff,0xef,0x1b,0x93,0xa5,0x50,0x47,0xcc,0xd6,0x59,0x8b,0xd2,0xb7, + 0x87,0xae,0x62,0x72,0xf2,0xcf,0x44,0x9f,0xa6,0x16,0x98,0x02,0xe8,0x65,0x69,0xd2, + 0xe6,0xbf,0x94,0x90,0x66,0x07,0xd6,0x13,0x49,0xaf,0xf6,0xbc,0xc3,0xd6,0x0d,0xe3, + 0xab,0x3d,0x4f,0x41,0x2e,0xff,0x74,0xf5,0x5f,0x63,0x97,0xcf,0x33,0x5b,0xa7,0x24, + 0x60,0xbf,0xeb,0xff,0x32,0xa3,0x44,0x07,0x37,0xe6,0xd8,0x4b,0xb1,0xc0,0x78,0x00, + 0x13,0x53,0xfe,0x30,0x4d,0x78,0x8e,0xa3,0xc5,0x99,0xff,0x09,0x69,0xfe,0x36,0x86, + 0xf6,0xff,0xf7,0xd7,0xfe,0x07,0xf6,0xff,0xe9,0x68,0x9e,0x32,0x27,0xcd,0x0b,0xde, + 0xe9,0xa4,0xe8,0x0e,0xa6,0xf4,0x1a,0x7d,0xfc,0x7f,0xc8,0xff,0x0b,0xce,0xda,0x82, + 0x54,0x1c,0x1b,0x51,0xba,0x28,0x51,0x57,0x94,0x93,0xff,0x16,0xb3,0x96,0xca,0xa4, + 0xaa,0x7a,0xbe,0x38,0x5d,0xfb,0x9f,0xf4,0x4b,0x0e,0xd6,0xa9,0x9b,0xaa,0xb3,0x69, + 0xbb,0x63,0x6d,0x9f,0x75,0xac,0xbd,0x4a,0xe5,0x9f,0xb2,0xcb,0xbc,0xbb,0x68,0x30, + 0x5b,0xa7,0x34,0xd8,0x7e,0xc7,0xff,0xa9,0x8b,0xe8,0x1a,0x25,0x7a,0x5b,0x7c,0xe3, + 0x1b,0x13,0xbe,0xe3,0x3b,0x1a,0x30,0x30,0x39,0x41,0xf6,0xd5,0x61,0x64,0x4a,0x49, + 0xf9,0x8a,0x7f,0x1f,0xff,0x7f,0xe0,0xfc,0x9f,0xdd,0xb4,0xff,0xd1,0xc5,0x48,0xde, + 0x2d,0x60,0x0a,0xf7,0x4d,0xa1,0x3e,0x80,0xff,0x7f,0x4d,0xe9,0x30,0x4e,0xb2,0x57, + 0x4a,0xd8,0xfa,0x3f,0xdf,0x11,0xc3,0x8c,0xd2,0xbf,0x3a,0xa5,0x47,0xa7,0x6e,0x4e, + 0x8f,0x62,0x49,0xc3,0xb5,0x0d,0xf7,0xec,0xd2,0x21,0x97,0x7f,0x4a,0x15,0x09,0x79, + 0xe7,0x4c,0x38,0x42,0xf3,0xbe,0xdf,0xab,0xfd,0xef,0x51,0xff,0x2f,0x49,0xe4,0xbf, + 0xc4,0x0b,0x1f,0x73,0xf9,0x72,0x53,0x3d,0xa0,0x85,0xd1,0xe9,0x28,0xc0,0xa8,0xe6, + 0x38,0x9f,0xb8,0x49,0x11,0xdc,0xff,0x1f,0xb8,0xfe,0x2f,0x6c,0x4d,0x6e,0xff,0xe9, + 0x5b,0x16,0xd0,0x5d,0xa7,0xe5,0xff,0x19,0xf0,0xff,0xaf,0x36,0x9b,0x8c,0x8d,0xf4, + 0xaa,0xf2,0xac,0xfd,0x17,0xb2,0x47,0x98,0x46,0x37,0xa7,0x06,0xab,0xf5,0x30,0x79, + 0x7e,0x70,0xf9,0x02,0x92,0x7c,0x42,0x17,0x79,0xfe,0x2f,0x65,0x4b,0x05,0x73,0xc1, + 0x68,0x0c,0xcd,0xfb,0x7e,0x37,0xf5,0xff,0x80,0xf9,0x3f,0x6e,0xa1,0x6c,0x50,0x27, + 0xc6,0xe5,0x48,0xb0,0x0e,0x40,0xae,0x97,0xfd,0xa7,0x17,0xb4,0xfd,0x2c,0x95,0xa9, + 0x34,0xf5,0x1a,0x9b,0x31,0xb8,0xff,0xbf,0xf7,0xfa,0xbf,0x2e,0x8d,0xff,0xd1,0x5e, + 0x41,0xc0,0x51,0xa4,0xfb,0xc4,0xff,0xa9,0x4b,0x0d,0xf6,0x7f,0x3f,0x60,0x9a,0xa9, + 0xbc,0xd2,0xc4,0xc8,0xbf,0x18,0x87,0x61,0x42,0xf7,0x8e,0xdd,0xad,0xf4,0x5a,0xc3, + 0x8f,0x0e,0x1b,0xcc,0x9a,0xf3,0x2f,0xcf,0xf2,0xfc,0x9f,0x55,0x6a,0x65,0xc1,0x16, + 0xd2,0xe2,0xa3,0x79,0x5f,0xef,0xb7,0xfd,0x97,0xb5,0xff,0x99,0x94,0xa5,0x12,0x8a, + 0x3e,0xad,0x1c,0x7a,0x8d,0xae,0x64,0xd2,0x0a,0xcc,0xb6,0xff,0xf4,0x86,0x95,0x78, + 0xaf,0x1a,0x53,0xf0,0xfc,0xff,0x40,0xf6,0x9f,0xba,0x51,0x41,0xf3,0x7f,0x33,0xc2, + 0xd1,0xf7,0x05,0xda,0xff,0xaf,0x2d,0x74,0x77,0x4f,0xaa,0xbe,0xc7,0xc8,0xbf,0x58, + 0x44,0xd5,0x4b,0x62,0x21,0xa4,0xa3,0xff,0x3d,0x9d,0x5a,0x76,0x4b,0x5c,0x03,0xf1, + 0x90,0xbf,0x02,0x90,0xda,0xff,0x1e,0x71,0x36,0x56,0xd0,0x29,0xe5,0x70,0x2d,0xe2, + 0xff,0xb4,0x63,0x95,0xe4,0xab,0x35,0x06,0x95,0x05,0xd0,0xc3,0x2e,0x1a,0x4c,0x04, + 0xd3,0x8e,0xce,0x30,0x69,0x82,0xa2,0x20,0x52,0xec,0xdd,0xfe,0x0f,0xd0,0xff,0x47, + 0x6a,0xff,0x29,0x8b,0x10,0xf5,0xab,0xfd,0xf3,0x1b,0x82,0xf6,0xff,0x6b,0x0a,0x13, + 0x61,0x2a,0xca,0xed,0xbf,0x58,0x78,0xd8,0xce,0xea,0x1a,0xf9,0x8a,0xbe,0x37,0x31, + 0x71,0x0d,0x3f,0x54,0xa6,0x89,0x48,0x29,0xf9,0xd6,0x1c,0x7c,0xf2,0x7f,0xe8,0x12, + 0xc1,0x8f,0x72,0x51,0xf7,0x4a,0x25,0xdd,0x63,0xe8,0x2a,0xd6,0xff,0xbd,0x42,0x49, + 0xcb,0x2e,0xdf,0x7d,0x8f,0x8e,0xeb,0xfb,0xca,0xbf,0x5a,0x60,0x93,0xfc,0xa3,0x96, + 0x58,0xd1,0xfd,0x73,0x94,0x15,0xbf,0x95,0x31,0x7b,0xef,0xff,0xb7,0xc7,0xf8,0x7f, + 0x93,0xaa,0xaa,0xf4,0x70,0xec,0x18,0xc0,0xfe,0x5f,0x5b,0x18,0xe9,0x93,0xcb,0xbf, + 0xec,0x42,0x67,0xe8,0xd5,0x2c,0x69,0xa7,0x2a,0x7b,0x38,0x57,0x4d,0x45,0x0f,0xf2, + 0xc2,0x3f,0xac,0x17,0x0f,0x2e,0x99,0x3d,0xad,0xf9,0x1c,0xa9,0x3c,0xff,0x87,0xc9, + 0x63,0xef,0x6a,0x6c,0x29,0xa3,0xd3,0x1e,0x29,0xff,0xf3,0x2a,0xda,0x7f,0xaf,0x52, + 0x4a,0x0f,0x32,0x22,0xe4,0x42,0x50,0x86,0x51,0x2e,0xff,0x6a,0x24,0x5b,0xe4,0xb2, + 0x33,0x6c,0x2f,0x8c,0x56,0x44,0x25,0x7e,0x18,0x24,0x86,0xab,0xd7,0xfe,0xd7,0x3b, + 0xff,0xc7,0xf5,0xff,0x55,0xea,0xc2,0xb4,0xa6,0xc8,0xad,0x97,0x15,0x08,0xa6,0x3c, + 0x40,0xfb,0xff,0x35,0xa5,0x4e,0xdd,0x22,0xfa,0x7e,0xd3,0xf2,0x2f,0x8e,0xe7,0xc0, + 0xe5,0xee,0x5b,0x89,0xc3,0x4c,0x03,0x51,0x6e,0x22,0x97,0x23,0x7f,0x3c,0xe4,0x3b, + 0xb6,0x33,0x5b,0x9d,0x6d,0x05,0xec,0xfa,0xdc,0x57,0x9f,0xfe,0x7f,0xcc,0x91,0xc4, + 0xab,0xcc,0x08,0x63,0xd4,0x2a,0x03,0xdb,0x7f,0xae,0x88,0xf7,0x8a,0xff,0x49,0x0b, + 0xe5,0x26,0x63,0xbd,0x8b,0x19,0x46,0x03,0x50,0x81,0x09,0x89,0xfc,0x1b,0xed,0x84, + 0x90,0x9c,0xe9,0xb6,0x22,0xd0,0x8d,0xac,0xa2,0x81,0xa4,0xb9,0x8a,0xf6,0xbf,0x67, + 0xfe,0xbf,0x5b,0x5e,0xe8,0x5e,0x27,0xa9,0x09,0x79,0x79,0xb0,0x99,0x74,0x2e,0x0f, + 0xb4,0xff,0x5d,0x4b,0xd8,0x96,0x7c,0x2a,0x97,0x9f,0x6e,0xff,0xe3,0x45,0x01,0x43, + 0xd7,0xf7,0xec,0x22,0xdc,0x77,0x8c,0x01,0xdf,0xf2,0xc3,0x75,0x11,0xf3,0x69,0x3b, + 0xf4,0xb1,0xff,0x4d,0xb6,0xcf,0x41,0xba,0x18,0x1b,0xd6,0x0d,0x43,0x25,0x50,0xdd, + 0xec,0x69,0x53,0x79,0x2d,0xea,0xff,0x7c,0xf7,0xff,0x52,0xaa,0xa2,0xe1,0xc4,0x7e, + 0x8b,0x1e,0xf2,0xaf,0xb6,0x2b,0x29,0x59,0xc7,0x28,0xbb,0xf9,0x9c,0xc9,0xb1,0xec, + 0x5d,0xa9,0xbe,0xa6,0xf6,0x5f,0x16,0xff,0xd3,0xfb,0x77,0x06,0x75,0x70,0x75,0x06, + 0xd4,0xff,0xaf,0x25,0xdc,0x08,0x35,0x5e,0xb5,0x9d,0xb6,0xff,0xb2,0x20,0x13,0x13, + 0x85,0xb6,0x3c,0xd3,0xdd,0xcb,0xff,0xd4,0x12,0xdb,0xa1,0x65,0x42,0x3a,0xae,0x98, + 0x5f,0xff,0x7f,0x9d,0xef,0x5f,0x8e,0x7b,0x98,0x15,0x09,0x21,0xef,0xf4,0x68,0xfb, + 0x5f,0xb8,0x7a,0xf5,0x7f,0xca,0x28,0x89,0xe3,0x92,0xc4,0x93,0xa9,0x90,0x75,0x60, + 0xbe,0x8d,0x03,0x86,0xc6,0xbb,0xfd,0xce,0xba,0x0b,0x92,0xab,0x20,0xda,0x61,0x9a, + 0x6b,0x5a,0xff,0x97,0xd9,0xff,0x72,0x70,0xf9,0x77,0x4d,0x3d,0xd4,0xff,0xaf,0x1d, + 0x66,0x85,0x2d,0x6b,0x94,0x8c,0xd0,0xf6,0x5f,0x96,0xa1,0xca,0x74,0xbb,0xb3,0x8a, + 0x49,0xcf,0xf1,0x6b,0x58,0x84,0x72,0xbb,0xca,0x1e,0x88,0xbc,0x55,0xdb,0x6f,0xfc, + 0xcf,0xb5,0x20,0xc5,0x6c,0xaf,0xf1,0xbf,0x41,0xdb,0xff,0xf1,0xe5,0xbd,0x10,0xe4, + 0x5a,0x30,0xf2,0xdf,0x98,0xf0,0x51,0xa2,0x25,0x47,0x44,0x19,0xf9,0xef,0x19,0xfe, + 0xdf,0x07,0xfb,0x1f,0x3c,0xfe,0x2f,0xad,0xff,0x07,0xeb,0xe0,0x6d,0xad,0x23,0x93, + 0x7f,0x49,0xfd,0x3f,0xea,0xfd,0x0a,0xf2,0xbf,0x37,0xd4,0x4c,0x8a,0x2b,0x6c,0x3e, + 0x89,0x9b,0xb2,0x0c,0x55,0x89,0xfc,0x67,0x82,0xdb,0x7f,0x71,0x8b,0x5b,0x6c,0x5f, + 0xd7,0x96,0xb0,0xc3,0x5e,0xe3,0x7f,0x6a,0x01,0x46,0x37,0x28,0xed,0xb1,0xfd,0x8f, + 0xb6,0xff,0x15,0xf6,0x27,0x5f,0xa3,0xa4,0xf3,0x7d,0xdf,0x65,0x54,0xa9,0xc1,0xef, + 0x56,0xfd,0x86,0xca,0x29,0xb9,0xcd,0xa2,0x03,0xc8,0xff,0xde,0xf3,0x7f,0xfd,0xec, + 0xbf,0x58,0x23,0x94,0xda,0xff,0x41,0xe4,0x5f,0xe6,0xff,0x83,0xfd,0xbf,0x7a,0x98, + 0x99,0x90,0x70,0x77,0x28,0x53,0xc4,0xd8,0x7f,0x99,0xff,0x1f,0xa5,0x16,0xb0,0x86, + 0xd6,0x5b,0x08,0x7c,0xb3,0x25,0xe9,0x01,0x4d,0x76,0x84,0xe1,0xb8,0xe8,0xaf,0xfa, + 0x8f,0xff,0x39,0x35,0xb5,0x5d,0xec,0xab,0x7b,0xe8,0xf8,0x7f,0x10,0xfb,0xdf,0x6b, + 0xfc,0x4f,0x5e,0xfe,0xa9,0x6b,0xc1,0x16,0xca,0x1d,0xbe,0x87,0xa5,0x04,0xea,0xa2, + 0x77,0xfc,0x1c,0x99,0xee,0xa8,0xab,0x24,0x76,0x69,0xff,0xc5,0x56,0xd5,0xbd,0xd8, + 0x7f,0x31,0xee,0x20,0x8d,0xff,0x95,0x83,0xcb,0xbf,0x7b,0xb9,0x69,0xf9,0x8f,0x43, + 0xfc,0xef,0xea,0xa0,0x46,0x86,0xa2,0xa2,0xc4,0xd0,0xc9,0x64,0x4c,0xc7,0x0d,0x99, + 0xfc,0xd3,0x26,0xd7,0xaa,0xff,0x17,0x82,0xdb,0xff,0x49,0x71,0x83,0x9b,0x5c,0x18, + 0x4f,0xcc,0x6b,0xf7,0xb7,0xff,0xa8,0x5c,0xd4,0xa2,0x7d,0x76,0x39,0xa8,0xfd,0xe7, + 0x3b,0x13,0xd0,0xf6,0x9f,0x0b,0xd9,0xf5,0x28,0x94,0x6a,0xc1,0xcf,0xa1,0x97,0x6c, + 0xcc,0x6f,0xc0,0xc0,0x74,0x95,0xca,0x1f,0x62,0x32,0xaf,0x64,0x91,0x59,0x0f,0xda, + 0xfe,0x0f,0x09,0xbf,0xee,0xc5,0xfe,0x8b,0x2d,0x42,0xf2,0xf8,0x9f,0xcf,0x2c,0x10, + 0x12,0x42,0x52,0xf9,0x17,0x72,0x06,0xc1,0xfe,0xef,0x03,0xa6,0x96,0x93,0x1a,0x1a, + 0x3a,0x45,0x83,0xb6,0xff,0xb2,0xf9,0x1c,0x18,0xd7,0x2e,0x2f,0x7e,0xd5,0x1b,0x59, + 0x4f,0x7f,0x6e,0x48,0x4b,0xb1,0x2b,0x90,0x4f,0xfc,0xdf,0x59,0xbd,0x53,0xec,0x59, + 0x0b,0xa0,0xe3,0xff,0x41,0xec,0x3f,0xef,0x7b,0xd2,0xf5,0x7f,0x2e,0x65,0xbf,0x67, + 0xa5,0x74,0x73,0xb8,0x9a,0xec,0xa9,0x02,0x5c,0xf9,0x97,0x0f,0x18,0x58,0x4a,0xe6, + 0x1b,0x4d,0x7a,0x83,0xb4,0x54,0xf7,0x4e,0xb3,0xa6,0xed,0xbf,0x98,0xc2,0xb9,0x97, + 0xf8,0xbf,0xd8,0xf5,0x56,0xea,0xff,0xef,0xf4,0x1d,0xf9,0x53,0xdc,0x13,0x33,0x9c, + 0xa3,0xc6,0xef,0x06,0xec,0xff,0x9e,0x89,0x24,0x24,0xa6,0x1f,0xc3,0x64,0xa9,0xf6, + 0xcb,0xff,0x61,0x06,0xab,0xb5,0x8a,0x0f,0xad,0xed,0x8b,0xd5,0x39,0xf2,0xb0,0xff, + 0x91,0x37,0xd4,0xcf,0xe2,0x6c,0x54,0xf8,0xc0,0x9e,0x62,0x0e,0x27,0xc4,0x77,0x05, + 0xea,0x65,0xff,0x31,0xcd,0x48,0x67,0x32,0x94,0x4c,0x97,0xe4,0x67,0x37,0xa8,0xfd, + 0xe7,0x4f,0x9a,0x96,0x7f,0xce,0x21,0xea,0x53,0x28,0x9b,0x66,0xa1,0x35,0x11,0x4d, + 0x8b,0x93,0xaf,0x59,0xb8,0xf2,0xbf,0x2d,0x2a,0xe5,0x52,0x72,0x2e,0xc3,0x2b,0x5f, + 0xda,0x6e,0xf7,0x36,0x81,0xb4,0xa6,0x10,0x7d,0xb8,0xbd,0x8c,0xff,0x29,0x5e,0xfe, + 0x86,0x2c,0xff,0x4f,0xa5,0xd2,0x9c,0x53,0xb8,0x18,0xcc,0x79,0xe5,0x01,0x97,0x88, + 0xa8,0xf7,0xb3,0x5b,0xa5,0x62,0xe4,0x5f,0xb0,0x13,0xd0,0xff,0x7f,0x8f,0x34,0x26, + 0xfd,0x7c,0xb2,0x34,0x13,0x22,0x62,0xfa,0xff,0x4a,0x52,0x72,0x99,0x2e,0xec,0xd6, + 0x9a,0x3b,0xd4,0xed,0x14,0x04,0xbc,0x49,0xe7,0xc3,0xf8,0xf4,0x05,0x69,0xb3,0x06, + 0x9c,0x1f,0x5a,0xdc,0x67,0xfc,0x4f,0x76,0x37,0x66,0x64,0x38,0xb3,0x18,0x4b,0x24, + 0x2a,0xf9,0x4a,0xa5,0x92,0xcf,0x7b,0x5b,0x1c,0xd4,0xfe,0x97,0xb8,0x53,0xa0,0xc5, + 0x2e,0xc9,0xaa,0xa6,0x00,0x41,0xe9,0xa6,0xa1,0xb7,0xb5,0x4e,0x2d,0x91,0x18,0xc2, + 0x87,0x55,0xa9,0x50,0xbe,0x8e,0x5b,0x17,0xe2,0x07,0xf5,0x2c,0x45,0xf3,0x9a,0xd9, + 0x14,0x36,0xc5,0x64,0x66,0xf7,0xec,0x66,0x49,0xcb,0x7f,0x52,0xf0,0x14,0xe8,0x5f, + 0x07,0xb5,0xff,0xa2,0x60,0xb6,0xa5,0xfd,0x7f,0xa8,0x7d,0x54,0xa6,0xb8,0x53,0x69, + 0x4e,0x35,0xa9,0x6b,0xea,0x9e,0x08,0x23,0xff,0x42,0x9c,0x88,0x1e,0x1d,0x1c,0xec, + 0xff,0xc0,0xe8,0x15,0xdf,0xa6,0xb2,0x67,0xd9,0x94,0x7d,0xa6,0x94,0x1d,0x10,0xab, + 0x99,0x74,0xe9,0x71,0x44,0x8b,0x8a,0x76,0x4b,0x1c,0x7c,0x4a,0x4a,0xc6,0xea,0xf2, + 0xc3,0xe3,0xe6,0x0e,0x60,0xb3,0x04,0xfb,0xda,0x7f,0x09,0xaa,0x5c,0xe7,0xf8,0xda, + 0x7f,0xba,0x06,0xc3,0x35,0x41,0xd0,0xee,0x32,0x27,0xe4,0xbb,0x70,0x4a,0x29,0xf5, + 0xea,0x58,0xbe,0x26,0x37,0x18,0x52,0x4e,0xdb,0x91,0xae,0xca,0x84,0x59,0x7a,0x0e, + 0x1e,0xc2,0x6c,0x50,0xb8,0x60,0x74,0x75,0x2b,0x90,0xfd,0xa7,0x2f,0x8e,0xb0,0xdf, + 0x35,0xea,0x47,0x2f,0x3a,0xb0,0x22,0xdf,0x94,0x83,0x57,0x88,0xbc,0xc1,0x4d,0x19, + 0xf9,0x17,0x6a,0x9e,0x74,0x46,0x11,0xd4,0xff,0x07,0x44,0xed,0xf8,0xd7,0xc7,0xd2, + 0xa3,0xac,0x7a,0xee,0xd3,0xff,0x97,0xb9,0x4b,0x4e,0x55,0x99,0xba,0xdb,0x92,0x94, + 0x01,0xaa,0x86,0xe8,0x1b,0xb6,0x62,0xa7,0xf2,0xe0,0xe6,0x16,0xe8,0x5d,0xff,0x97, + 0xb2,0x19,0x95,0x96,0x96,0x20,0xf6,0x9f,0x3f,0x05,0xa6,0x72,0xce,0x9a,0x5d,0x73, + 0x70,0xf9,0xa7,0x6a,0x13,0x4e,0x64,0x8e,0x1b,0xc8,0x58,0xf3,0x5b,0x95,0xbd,0xf4, + 0xbd,0x76,0xc7,0xf4,0xab,0xe0,0x43,0xae,0x9b,0xf4,0xee,0x06,0x8d,0xff,0x33,0x83, + 0xbe,0x12,0xe8,0x6e,0xa4,0x9e,0xd4,0x52,0x29,0x61,0x51,0x31,0x88,0x44,0x9d,0xb1, + 0x17,0x6d,0x61,0x4e,0x8f,0x1a,0xf3,0xd8,0x3e,0x08,0x4a,0x09,0x81,0xfc,0x0f,0x86, + 0x39,0xe9,0x1f,0xa0,0x4b,0x69,0xdc,0xc2,0xec,0xf8,0x1f,0x42,0x77,0x3e,0x66,0xd8, + 0x20,0xa7,0xa9,0x9c,0xb2,0x4c,0x62,0xe6,0x26,0x5d,0xae,0x24,0xe1,0x7f,0x8b,0x26, + 0x3b,0x66,0x27,0xdb,0x9f,0x6f,0x17,0xf6,0xdf,0xf4,0x2a,0x3b,0x74,0x3c,0x2f,0x48, + 0xfd,0x5f,0x19,0x63,0x8a,0x38,0x3b,0xea,0x06,0x1b,0x00,0xa4,0x63,0x5f,0x82,0x60, + 0xc8,0xa1,0xb4,0x89,0xa3,0xe4,0x46,0x18,0xb9,0xf6,0xef,0x2d,0xcf,0x1e,0x49,0xbe, + 0xc7,0x4e,0xe8,0xf8,0x1f,0x5f,0x67,0x61,0x63,0xf3,0xb4,0x3e,0x0b,0xe4,0xff,0x0b, + 0x25,0x82,0x76,0x8f,0xbc,0xd6,0x41,0x4a,0x98,0x25,0x1a,0x9b,0x8a,0x19,0x78,0xe1, + 0x09,0x76,0x3a,0x17,0x3e,0x6c,0x49,0xab,0x99,0x80,0x97,0x1a,0xb0,0xe8,0x31,0x09, + 0x63,0xba,0x22,0x28,0x67,0x76,0xfc,0xaf,0x28,0x57,0x78,0xd8,0x91,0xf5,0x1c,0x71, + 0xa6,0xed,0xa0,0x30,0xe4,0x0d,0x5d,0x6c,0xa5,0xe1,0x3f,0x6b,0x29,0x36,0x06,0xde, + 0xa5,0xc5,0xa0,0x47,0xfb,0xbf,0x1f,0x94,0x46,0x4a,0x52,0xd1,0x84,0x40,0xf6,0x9f, + 0x35,0xf2,0x06,0xe3,0x3a,0xb1,0xba,0x81,0xf6,0xc8,0x83,0x0d,0x7c,0x42,0xf7,0xff, + 0xd7,0xec,0xef,0xe8,0xaa,0x2d,0x3d,0x59,0xa1,0x00,0x73,0x6b,0x7a,0x28,0x0a,0xd6, + 0xfe,0xf3,0x12,0xcb,0x74,0xe0,0xd4,0xa8,0x1f,0x82,0xc9,0x3f,0x97,0x01,0xb0,0x49, + 0x4f,0x6b,0xe0,0x65,0x25,0xd0,0x75,0x1a,0x31,0xa7,0x93,0x72,0x82,0xbc,0x8c,0x0a, + 0x56,0xfe,0x79,0xff,0x86,0x2e,0x1e,0xb2,0x66,0x29,0xc0,0x0f,0xff,0x29,0xa3,0xe2, + 0x73,0xed,0x3e,0x51,0x26,0x64,0x66,0xd8,0x9b,0x97,0x65,0xca,0x82,0x1b,0x38,0xa4, + 0x42,0xca,0x51,0x5e,0x0e,0x28,0xcf,0x6d,0xac,0xec,0x7f,0x98,0x26,0x5b,0x0b,0xa6, + 0x5b,0x01,0xfd,0xe6,0xff,0x44,0xe8,0x9a,0x7c,0x6b,0x54,0x37,0x5b,0x5a,0xce,0x03, + 0xd9,0x7f,0x76,0xd0,0x43,0xae,0x71,0x93,0xc9,0x00,0xa2,0x9b,0x06,0xd8,0x42,0xa9, + 0x4a,0xc6,0x5c,0xe6,0x2e,0x86,0xdb,0xc6,0xcd,0x14,0x7c,0x5f,0x0f,0x69,0x8a,0x9f, + 0xcb,0x4d,0x68,0x26,0xf1,0x60,0xec,0x3f,0x37,0x51,0x13,0x23,0x49,0x4c,0xa5,0x25, + 0x90,0xff,0xcf,0x87,0x47,0x98,0xe0,0x00,0xa5,0x35,0x28,0x7b,0x1d,0xe7,0xfb,0x2a, + 0x53,0x29,0x64,0x94,0x9f,0xcf,0x4d,0xe7,0xc6,0x7a,0x5a,0x4c,0x57,0x8f,0xa0,0x23, + 0x8a,0x00,0x53,0x53,0x4c,0xac,0x95,0x21,0x5d,0x6d,0xcb,0x6a,0xe3,0xdc,0xfc,0x1f, + 0xec,0xec,0xa0,0xec,0xa8,0x9d,0x9e,0xc9,0xa3,0x0d,0x21,0xa7,0x31,0xe8,0x69,0xa0, + 0x7a,0x0e,0x0e,0xa4,0xb3,0x13,0xe4,0xd0,0x5d,0x81,0xfc,0xed,0x7f,0x21,0x5d,0x95, + 0xd9,0x5d,0xdd,0xa7,0x9b,0x4d,0x30,0xfb,0x4f,0xd7,0x8a,0xf9,0xcb,0x97,0xa6,0x0a, + 0xb3,0x49,0x1f,0x31,0xdb,0xce,0x66,0xa4,0x8a,0x05,0xc9,0xd5,0xa5,0xbd,0x1c,0x57, + 0x61,0x30,0x3d,0xaa,0x7a,0x0d,0x0a,0xd8,0x64,0x35,0xb9,0xd0,0x4c,0xe2,0xc2,0x69, + 0xfc,0x1c,0xbd,0x20,0x23,0xb0,0x4c,0x3a,0x4f,0xa0,0xf8,0x1f,0x37,0xf0,0x28,0x3b, + 0x24,0x39,0x75,0xdd,0x68,0x69,0x2e,0xb2,0x07,0xaa,0xd2,0x83,0x03,0x99,0xd2,0x35, + 0x10,0xa5,0x18,0x7d,0x25,0x98,0x26,0x92,0x5e,0x03,0xa7,0x01,0x1c,0xf2,0xb9,0xa8, + 0x4b,0xa9,0xc4,0xba,0xbc,0xa4,0xf1,0xf3,0x7f,0xc4,0xb3,0xde,0x72,0x0d,0xb6,0xbf, + 0xbe,0x77,0x1f,0xa8,0xee,0xb6,0xdc,0xf8,0xff,0x6a,0xc5,0x13,0x2d,0xbe,0x65,0x8d, + 0xa3,0xcd,0x06,0x29,0x3d,0xb7,0xb1,0x47,0xfd,0x5f,0x2b,0x29,0xc9,0x84,0x60,0x08, + 0x19,0x97,0x87,0x4e,0x28,0x0e,0x66,0xff,0x95,0xb8,0xd7,0x22,0x3a,0xcc,0xb7,0x9b, + 0xa4,0x5c,0x6b,0xaa,0x32,0x63,0xa1,0xb2,0x85,0xd2,0xe8,0xe2,0x11,0x09,0xf8,0xe3, + 0x52,0x47,0xa9,0x9b,0xe1,0x46,0xd2,0xe9,0xc6,0x72,0x25,0x3e,0xd3,0xe3,0x0a,0xad, + 0xb1,0xf7,0x72,0x82,0x4b,0x39,0x74,0xdf,0xb1,0xf6,0x1f,0x5d,0x4a,0x4f,0xca,0x46, + 0x98,0x64,0x2b,0x46,0x69,0x05,0xf3,0xff,0xf1,0x58,0x2b,0xde,0x6f,0xac,0x3f,0x48, + 0xdf,0x1b,0x3a,0x2e,0xc0,0x8e,0x82,0x44,0x0f,0xfc,0x48,0x65,0x27,0xf2,0xd3,0xb9, + 0xc6,0x29,0x05,0xc0,0x0e,0x16,0xdb,0x67,0xba,0x18,0x80,0x82,0xad,0xb0,0x3b,0x77, + 0x70,0x4e,0xf3,0xb5,0x1d,0xc2,0xfc,0x9f,0xa5,0xaa,0x3d,0x35,0x95,0x31,0xca,0x0a, + 0x68,0x5c,0xf3,0xd6,0x5a,0xa5,0x1b,0xd0,0x27,0x3d,0x93,0x3c,0x42,0x67,0xf7,0x7b, + 0x7e,0x9b,0xa1,0x65,0x6c,0xe8,0x37,0xdc,0x1c,0x82,0x6e,0x05,0xb7,0x47,0xfd,0x9f, + 0x54,0x66,0xa3,0x43,0x0d,0x36,0x2c,0x47,0x8b,0x3f,0x93,0x2c,0x12,0xd0,0xfe,0x2b, + 0xf1,0x84,0x69,0x1f,0xa7,0xd8,0x70,0x12,0xb5,0x87,0x1a,0x32,0x13,0x8c,0x34,0xb2, + 0x71,0x0f,0x62,0xd3,0xd3,0xdc,0x65,0x36,0x62,0x74,0x31,0xf6,0x4a,0x31,0x33,0x12, + 0x53,0x88,0xf1,0xd6,0x8d,0x46,0x82,0xae,0x08,0x71,0x86,0x3d,0xd9,0xd2,0x5d,0x25, + 0x12,0xc9,0xce,0xc9,0x5a,0xdf,0xed,0x8d,0xda,0xc7,0xac,0x36,0xd8,0x5c,0xcb,0x65, + 0x7a,0x5f,0x01,0xfd,0x7f,0x74,0x75,0x5a,0xf6,0x0d,0x1e,0x61,0x2f,0x01,0x93,0x6a, + 0x10,0x79,0x86,0xde,0x9c,0xa7,0xa9,0x8c,0x1a,0xb5,0x0e,0x1d,0xc9,0x13,0xa6,0x73, + 0x2e,0x39,0x0a,0x54,0xcd,0x30,0x77,0x41,0xa8,0x4f,0x00,0xfe,0x88,0x7d,0xf3,0x4a, + 0xa1,0x58,0x8f,0x6a,0xb8,0x74,0xfe,0xcf,0x5c,0x2c,0x53,0x18,0xad,0xf0,0x9d,0x06, + 0xe9,0x3e,0x28,0x6c,0x6c,0x3a,0xda,0x9a,0x31,0xf1,0x20,0x1c,0x91,0x1a,0x6d,0xda, + 0xa8,0x01,0xfe,0x1a,0x38,0x27,0xce,0x7a,0xe2,0x97,0x92,0xfb,0x9e,0x5e,0xdc,0x95, + 0xf4,0x1e,0xf6,0xdf,0x0e,0x66,0xc5,0x8b,0xad,0x82,0x6e,0x0d,0xb1,0xa1,0x17,0xf2, + 0x4c,0x69,0x61,0x7a,0xca,0x04,0xb4,0xff,0xf8,0x14,0x26,0x47,0x0b,0x99,0xd8,0x84, + 0xcc,0x79,0x8a,0x17,0x13,0x99,0x42,0xa7,0xc2,0x56,0x57,0xb8,0x8c,0x75,0xbb,0x97, + 0x44,0x29,0x35,0x99,0x89,0x18,0xc6,0x14,0x3a,0xae,0x91,0x46,0x8d,0x51,0xc5,0xf4, + 0x78,0x21,0xcc,0xde,0x93,0xad,0x06,0x39,0x13,0xc3,0x6c,0x64,0x26,0x53,0xf1,0x12, + 0xed,0xbf,0xb4,0x79,0x19,0x19,0xcb,0xb5,0x32,0x85,0x42,0xa6,0x36,0x59,0x4c,0x53, + 0xc2,0xc4,0xdb,0x7f,0x7c,0xd3,0x2b,0x9d,0x82,0x16,0xe3,0xd2,0xbf,0x59,0x49,0x0a, + 0xe8,0xff,0x93,0x63,0x3c,0x50,0xd3,0x84,0x4b,0xc0,0x56,0xef,0x9a,0xcc,0x00,0x33, + 0x63,0x93,0x05,0x93,0xdc,0x9d,0x0e,0xd3,0x61,0x6b,0x92,0x8a,0x3f,0x49,0xa6,0x73, + 0x4f,0x4f,0xa0,0x82,0x97,0x69,0x85,0xd8,0xbb,0xc3,0x77,0xd0,0x04,0x7a,0xc0,0x9b, + 0x82,0xd2,0x44,0xa6,0xf7,0xe5,0xf3,0x99,0xff,0x5b,0xd2,0x69,0x48,0xa3,0x57,0x6b, + 0x3f,0xc3,0xfe,0x98,0x2c,0x4e,0x14,0xb9,0xd1,0x6c,0xa8,0x6a,0xe0,0x76,0x80,0x1e, + 0x03,0x54,0xa4,0x8f,0x2e,0x67,0xac,0xfc,0x7b,0x63,0x62,0x96,0xd2,0xd1,0xd0,0xc4, + 0x44,0x31,0xca,0xe5,0xdc,0xb3,0x53,0x70,0x04,0xb5,0xff,0x3e,0xa7,0xdc,0xe3,0x37, + 0x6e,0x8e,0x1b,0xdd,0xbd,0x1c,0xa5,0x78,0x32,0x84,0xaf,0x05,0x3f,0xad,0x37,0x55, + 0xd1,0x37,0x39,0x39,0x8a,0x47,0x8b,0x13,0x13,0x21,0x67,0xce,0x70,0x26,0x7c,0x2f, + 0x9b,0xff,0xdb,0x39,0x16,0x2f,0xd1,0x51,0x1e,0xf1,0x15,0xcf,0x27,0xb4,0x49,0x6f, + 0x3b,0xa8,0xff,0xef,0xb7,0x35,0xae,0xcd,0x9e,0x3b,0xab,0x78,0x37,0x84,0xae,0x02, + 0x9b,0x83,0xfa,0x3d,0xda,0xd7,0x91,0xc8,0xbf,0x7c,0x3f,0xb2,0x2e,0xe2,0x80,0x1c, + 0x7e,0x88,0x9c,0xd4,0x6a,0xbf,0xd1,0x58,0x29,0xfb,0x5f,0xea,0x39,0xbc,0x46,0x95, + 0xcb,0x1b,0xea,0xd7,0xdd,0x8d,0x6e,0xb0,0x92,0x98,0x14,0x11,0xa9,0xfd,0xe7,0xe2, + 0xff,0x3e,0xda,0xca,0x83,0x35,0x16,0x01,0xec,0x7f,0xc9,0xff,0xd0,0xd2,0x3d,0x7a, + 0xf5,0x73,0x75,0xd2,0x48,0xbf,0x0e,0x70,0x4c,0x14,0x2d,0xdb,0xeb,0xda,0x31,0x2d, + 0x0e,0xfe,0x8d,0x39,0x0a,0xd5,0x98,0x47,0xdb,0xff,0x1e,0x9b,0xe6,0xa6,0x27,0x0a, + 0x22,0xff,0xbd,0x0e,0x94,0x9f,0xe6,0x6b,0xad,0xdf,0x4d,0x66,0x5c,0x1b,0x26,0x2f, + 0xa1,0xd7,0x6e,0x82,0xcf,0x30,0x01,0x30,0x05,0x1e,0x71,0xa0,0xff,0xb5,0xa3,0x24, + 0x2a,0xdd,0xea,0x71,0x07,0xf9,0xb1,0xfa,0xb8,0xd1,0xbc,0xc5,0x9b,0x4d,0x57,0x90, + 0x83,0xf4,0x18,0x0c,0xe4,0xff,0x4b,0x6a,0x2b,0x0c,0xac,0x93,0x12,0xc4,0xfe,0xa7, + 0x13,0xbe,0xc7,0x96,0xe7,0x9a,0x28,0x28,0xf8,0x42,0x19,0xe9,0x77,0x82,0xcc,0x2c, + 0x89,0x46,0xaf,0xe1,0x42,0xd8,0xc0,0x62,0x5d,0x16,0xcf,0xb1,0x71,0x75,0x10,0xad, + 0x24,0xaa,0x72,0xb3,0x8a,0xe1,0xe2,0xf2,0x01,0xea,0xff,0xa5,0x8a,0xff,0x79,0x09, + 0x29,0x7b,0xbd,0xd5,0x9a,0xc2,0x27,0x06,0xd0,0xf6,0x7f,0xd2,0x3f,0x5f,0x55,0x3a, + 0x42,0x0c,0xe0,0x03,0x33,0xc8,0xbf,0xcf,0xf0,0x7a,0x2c,0x94,0xfc,0x8f,0xad,0x0f, + 0xf9,0xde,0xc1,0x6e,0x9b,0x5f,0xd1,0x98,0xeb,0xe9,0x30,0x33,0x39,0xfd,0x8d,0x7e, + 0xce,0x82,0xe2,0x27,0xff,0x9c,0xfd,0x5f,0xf6,0x5f,0x9f,0xd0,0x62,0x9d,0x94,0x00, + 0xf6,0x7f,0x2c,0xd2,0xf2,0x39,0xb8,0xa8,0x3e,0x55,0xf0,0x13,0x26,0x3e,0x2b,0xae, + 0x9f,0x82,0x0b,0xb1,0x77,0x62,0x3d,0xea,0xbf,0x28,0xd7,0x68,0x5a,0x2e,0xfa,0x2e, + 0xe9,0x7a,0x0a,0xcc,0xf8,0x1f,0x1d,0xbf,0x43,0xe1,0x33,0x88,0x02,0xd8,0xff,0x52, + 0x3b,0xe6,0x7b,0xe7,0xc4,0x79,0x5f,0x9b,0x7e,0x57,0xd2,0xde,0x07,0x57,0x65,0xa2, + 0xbc,0xcd,0x8e,0xe6,0xeb,0x7a,0x16,0xa1,0xf6,0x3f,0x00,0x4c,0x13,0x55,0xaf,0x94, + 0x31,0x17,0xda,0xfe,0xeb,0x86,0x5f,0xf2,0x40,0x52,0x13,0xd7,0x34,0xf2,0xfe,0xb7, + 0x3b,0xde,0x62,0x4a,0xc7,0x76,0x00,0xf9,0x57,0xdc,0xea,0x6c,0x0f,0xfb,0x3f,0xe4, + 0xbb,0x36,0xa6,0xc4,0xa7,0x9e,0x05,0xb0,0xff,0x5d,0x9d,0x6e,0xb2,0xa4,0x48,0xaf, + 0xa1,0x05,0x57,0xe5,0xe5,0x32,0xc7,0x17,0xca,0x3e,0x01,0x8e,0x14,0x9f,0xc1,0xda, + 0x88,0xfa,0x2e,0xcb,0x77,0xe0,0xad,0xe7,0xfc,0x2e,0x9e,0x2b,0xb4,0xb4,0xfd,0xef, + 0x34,0x47,0xe5,0xc7,0x2c,0x8c,0xb4,0x14,0x40,0xfe,0xe3,0x6d,0xd5,0xcf,0x3d,0x2a, + 0x4a,0x6c,0x8b,0x5a,0xf3,0xaf,0x41,0x96,0xe6,0xb8,0x15,0x68,0xfb,0x3f,0x3a,0xb5, + 0xea,0x53,0x81,0xfa,0x2c,0xe4,0xfe,0x0f,0x02,0x33,0xc9,0x5f,0xcf,0x3e,0x63,0x0e, + 0x8c,0xfc,0x4f,0x19,0x72,0x87,0x2f,0x24,0xd5,0x24,0x6a,0xd6,0xcf,0x3c,0x26,0x3b, + 0xac,0x1d,0x1e,0xcc,0xff,0x9f,0x3a,0x43,0x7d,0xcd,0xca,0x7f,0xb6,0x57,0x88,0x22, + 0xdd,0xe2,0x4f,0x38,0x88,0xfd,0xd7,0xa7,0xd4,0x84,0x64,0xab,0xe9,0x55,0xb2,0xa4, + 0xa4,0x41,0x10,0x95,0x7d,0xa1,0x5a,0x15,0x89,0xf6,0x3a,0xb3,0x09,0xb1,0x01,0xa6, + 0xec,0x2b,0xd5,0x42,0xb6,0x9b,0xb1,0xe5,0x73,0x99,0xdd,0xa6,0x0e,0x2e,0xfd,0x41, + 0x93,0x1d,0x4c,0x3a,0xc6,0xe7,0x7e,0x06,0xf1,0xff,0xdb,0x53,0xea,0xa2,0x74,0xef, + 0x13,0xf2,0x9a,0xe5,0x9a,0x5f,0x8d,0x29,0xdd,0xda,0xe4,0x16,0xa5,0xe5,0xbf,0x83, + 0xd6,0x94,0x1d,0xb4,0x12,0x0d,0x62,0xc2,0x00,0x17,0xc6,0x7e,0xf7,0xea,0x32,0xe2, + 0x42,0xd5,0xa8,0x71,0x5f,0x9e,0x66,0x46,0xbc,0x0f,0x92,0x5e,0x03,0x36,0x91,0x39, + 0x99,0x60,0xa7,0xab,0x7c,0x79,0x0f,0x12,0xff,0x0b,0x54,0xff,0x6f,0x36,0x96,0xf9, + 0x66,0x49,0x77,0xfd,0xa2,0xd8,0x55,0xc0,0xd7,0xfe,0x53,0x39,0xca,0x75,0xb4,0xd5, + 0xc2,0x19,0x7e,0xa3,0x29,0x67,0x63,0xe2,0x29,0x96,0xe6,0x24,0x65,0xbf,0x3e,0x7a, + 0xc1,0x6f,0xdc,0x8f,0x68,0x4c,0xe6,0xc2,0x1a,0x8b,0x3e,0x27,0x22,0xc9,0x76,0x6f, + 0x54,0xa5,0x6a,0xcf,0xd5,0x14,0xfc,0xfc,0xdf,0xe5,0xaa,0x70,0xbd,0x25,0xdd,0x0c, + 0x03,0xb4,0xff,0x91,0x9c,0x8c,0x6d,0x71,0x64,0xb3,0xf8,0xa4,0x5f,0x89,0xa8,0x0f, + 0x3d,0xc3,0x2f,0x8c,0x97,0xcf,0x89,0x72,0xcc,0xc9,0xff,0x94,0x2e,0x1e,0x74,0x29, + 0x07,0x3d,0x7f,0x06,0x83,0xb1,0xff,0x81,0xe4,0xbf,0x93,0x76,0xb1,0x52,0xf9,0x75, + 0x76,0xd8,0xa0,0x52,0x72,0xb2,0x21,0xf6,0x1a,0x70,0x50,0xb7,0xe9,0xb1,0x5d,0xc8, + 0xad,0x8e,0x0e,0x89,0x2e,0xdb,0x7a,0x32,0xdd,0x17,0x2a,0xc2,0x30,0x41,0x7d,0x2b, + 0x24,0x7f,0x18,0x4b,0xad,0x62,0x57,0x48,0x1e,0x48,0x9e,0xd3,0x24,0xde,0x8e,0x9f, + 0xfd,0x6f,0x74,0xdd,0x1d,0xa4,0x48,0x36,0xe1,0x4e,0xed,0x29,0x7a,0x93,0x9f,0x6d, + 0x79,0x03,0x17,0xa8,0x6b,0x4c,0x2b,0x7a,0x29,0xd4,0x91,0xbb,0x55,0x6a,0xa4,0x96, + 0x8b,0x0a,0xba,0x22,0x1d,0xaa,0xf9,0x8c,0x81,0x30,0x65,0x2e,0x16,0xd3,0x42,0xaa, + 0x4d,0xb7,0xd8,0x92,0x68,0x0b,0xb5,0x91,0xff,0xac,0x70,0xca,0xdd,0x39,0x67,0x49, + 0x21,0xfd,0x51,0x6d,0xcf,0x31,0x1a,0x23,0xda,0x92,0x1c,0x44,0x86,0xba,0xf8,0x74, + 0xd2,0x34,0x75,0x71,0xac,0x19,0x9a,0xd4,0x0c,0x3b,0x49,0x51,0x7a,0x62,0xd8,0xbf, + 0x44,0x4c,0x45,0x5a,0xdc,0x55,0x28,0x25,0xab,0xb2,0xdc,0x68,0x33,0xea,0xed,0x9e, + 0x24,0x8a,0xaa,0x4b,0x73,0x4c,0x25,0x20,0x1e,0xea,0xdb,0x78,0x05,0x70,0xf4,0x48, + 0x51,0xf5,0xc1,0x28,0x47,0x30,0xf8,0x55,0xb7,0xef,0xaa,0xa9,0xe5,0x2f,0x25,0xc7, + 0xe2,0xa5,0x74,0x3a,0x59,0xac,0x66,0xfa,0x35,0x21,0xd4,0xb5,0xa1,0x62,0xb4,0x9b, + 0x8e,0x3f,0x8b,0x16,0x4f,0xcd,0x25,0xda,0xb2,0xc1,0x2c,0x54,0x6b,0x27,0xbd,0x28, + 0x47,0xbc,0x9b,0xad,0x97,0xad,0x03,0xc2,0x7f,0xb2,0x92,0xa6,0xea,0x6b,0x89,0xea, + 0x25,0xbc,0xd3,0x52,0x1c,0xef,0x35,0xd7,0xd2,0xe4,0x47,0xe9,0x67,0xff,0xa9,0xe3, + 0x71,0x56,0x34,0xb4,0x7c,0xe8,0x7b,0xe9,0x78,0x1c,0x6d,0xae,0xca,0x0d,0xc5,0xd5, + 0x6c,0x20,0xc9,0xee,0x92,0xdf,0x8a,0xf9,0x42,0x8f,0x78,0x54,0xd3,0x6c,0x2f,0xe6, + 0x27,0x52,0xdd,0xb1,0x34,0x3e,0xae,0x6e,0xaa,0x98,0xef,0x34,0x7a,0x15,0x61,0x35, + 0xb2,0x58,0x2d,0x26,0xf1,0x69,0xa0,0xa5,0xa3,0xa9,0xcb,0x95,0xd1,0xed,0xba,0xdf, + 0xf2,0xe6,0xf0,0x0a,0xda,0x32,0x3a,0x08,0x7c,0xc6,0xd1,0xd0,0x5c,0x42,0xf3,0x16, + 0x95,0x8c,0xff,0xdf,0x8c,0x74,0xce,0xa5,0x92,0xf8,0x98,0xbb,0x21,0xfe,0x7c,0x9c, + 0x33,0x2e,0x3b,0x37,0x3e,0x52,0xa6,0x17,0x50,0xa9,0x12,0x61,0xef,0x42,0x6d,0xd4, + 0xe6,0xc8,0xd6,0xe2,0xdd,0xe8,0xc4,0x56,0xcf,0x73,0x42,0xec,0xe0,0x43,0x4d,0x92, + 0xb3,0xfa,0x5e,0x6a,0xa2,0xa5,0xf9,0xf8,0x0a,0xde,0x3d,0x28,0xdb,0xd7,0xb4,0xa9, + 0x77,0xaa,0x67,0xc8,0x6e,0xc6,0x92,0xc5,0xa1,0x25,0x88,0xfc,0x0d,0x0c,0x13,0xff, + 0xdf,0x43,0xe2,0x94,0x6a,0x96,0x23,0x8d,0x75,0xdd,0xd8,0x0c,0xb4,0x74,0xd3,0xd0, + 0x23,0x8d,0x06,0x2a,0x45,0xea,0x35,0x54,0xd8,0x2a,0xda,0xe9,0x7a,0x03,0x95,0x51, + 0xd3,0x7f,0xa7,0x7e,0xf6,0xdf,0x67,0x8b,0x26,0x3a,0xe7,0x88,0x7c,0x73,0x46,0x3d, + 0x42,0x4e,0xb0,0xff,0x71,0x35,0xc9,0xb5,0xc3,0x0b,0x1b,0x41,0xae,0x86,0xba,0x43, + 0xae,0x5d,0xa4,0x1e,0x60,0xdb,0xe8,0x20,0xf0,0xb2,0x7a,0x9d,0xdb,0x32,0x6d,0xff, + 0xa9,0xfe,0x5b,0x9b,0x78,0xcb,0xbd,0x2e,0xcf,0x20,0x34,0x0d,0xb3,0x8c,0xf7,0x1d, + 0xe8,0xa4,0x48,0x89,0xc0,0x37,0xc7,0x54,0x7b,0x78,0x0a,0x52,0xec,0x92,0x27,0x19, + 0x0f,0x0d,0xe8,0x0f,0x6d,0xf0,0xd8,0x9c,0x93,0x9b,0x12,0x3f,0xfb,0xff,0x26,0xa3, + 0xf7,0xfc,0x3f,0xc0,0xcd,0x03,0x3b,0x11,0x5b,0xaf,0xce,0xa5,0x37,0x05,0x83,0xd9, + 0xff,0x37,0x2c,0x39,0x90,0x7f,0x80,0xc0,0x4c,0x1a,0xcb,0x75,0xcd,0xb5,0x97,0xb8, + 0x99,0x6a,0x55,0x37,0x89,0xfd,0xf7,0xeb,0xfe,0x0c,0xdc,0x74,0xb0,0x1d,0x46,0xe2, + 0x7c,0x30,0x79,0x44,0xab,0x8a,0x8d,0xd7,0x6f,0x5e,0x6e,0x12,0xfb,0x4f,0xb7,0xff, + 0x81,0xfd,0xbf,0xa9,0x59,0xe7,0xf2,0xa8,0x42,0xa3,0x6e,0x0c,0xb7,0xde,0xc8,0x56, + 0xa3,0xa5,0x9b,0x6a,0x34,0xd5,0x9b,0xd0,0xfe,0x83,0xfc,0xdf,0xdc,0x08,0x73,0x4b, + 0x8d,0x15,0xab,0x43,0xad,0xa1,0xc9,0x5c,0xc8,0xee,0x91,0x1a,0x70,0x44,0xed,0xeb, + 0x8a,0x3a,0xa5,0x5a,0x4c,0xed,0x4d,0x68,0x6f,0x12,0xfb,0x4f,0xc7,0xff,0x06,0xf1, + 0xff,0xc9,0x05,0xc6,0xd7,0xf8,0xcd,0x7b,0x69,0x6e,0x3a,0xd6,0xfd,0xfb,0x7f,0xbd, + 0x51,0x2c,0x44,0xb3,0x95,0xf3,0xd8,0x53,0x06,0x18,0xd8,0xff,0x1e,0xb4,0x9d,0x4b, + 0x3c,0x91,0xcb,0x09,0xa3,0x38,0x03,0x6f,0x54,0xfc,0x7b,0x6c,0xd9,0xdc,0xf0,0xc3, + 0xa9,0xed,0x62,0xfc,0x7f,0x1f,0x6e,0x42,0xfb,0x1f,0x5c,0xfe,0x17,0xa9,0xb5,0x7a, + 0x8e,0xd4,0x0a,0xbc,0x91,0x50,0xab,0x7d,0xe4,0xbf,0xd7,0x90,0xd3,0x37,0x06,0x54, + 0x27,0x92,0xbd,0xd5,0x56,0xc0,0xfe,0xf7,0xc0,0x2f,0xff,0x1f,0x78,0x63,0x63,0xf6, + 0x1a,0x33,0x46,0x91,0x4e,0xd9,0x75,0x63,0x01,0xf6,0x7f,0x40,0x76,0x57,0xff,0xf7, + 0xeb,0xff,0x07,0xbc,0xc1,0xd9,0x11,0x7b,0x52,0xd1,0x88,0x33,0x44,0xdf,0x60,0xec, + 0x62,0xfe,0x1f,0x1f,0xc0,0xfe,0xf7,0x00,0xec,0xff,0x9b,0x15,0xb5,0xd6,0x2b,0x08, + 0x98,0xbc,0xe1,0x33,0x80,0xc0,0xfe,0x0f,0xc6,0xde,0xed,0x3f,0xc8,0xff,0x9b,0x8b, + 0x75,0x79,0x8f,0x71,0xc2,0x0d,0x3f,0xa0,0xe2,0xfe,0xf9,0xff,0x60,0xff,0x7b,0x00, + 0xf2,0xff,0x26,0xa6,0xd9,0xc8,0x47,0x65,0x0d,0x01,0xa5,0x6e,0x6e,0xf4,0x46,0x17, + 0x04,0x66,0xfc,0x3f,0x6d,0x2f,0x5b,0xba,0x49,0xec,0xff,0xee,0xf2,0x7f,0xa1,0xfe, + 0xff,0xe6,0xc6,0x5c,0xab,0x14,0x93,0xce,0xa0,0x34,0xa5,0x52,0x29,0x9d,0x3c,0x33, + 0x17,0x2b,0xec,0x53,0x77,0xd0,0xab,0x0a,0xd8,0xff,0xc1,0xd8,0x5d,0xfe,0x2f,0xd8, + 0xff,0x37,0x3d,0x4d,0xb3,0x51,0x58,0xad,0x25,0x12,0xb1,0x6c,0x47,0x6b,0xfb,0xf4, + 0x6c,0xbf,0xf1,0xe8,0x31,0xfe,0xef,0x80,0xd0,0xf2,0xcf,0x0f,0x57,0xff,0xe6,0xa1, + 0x09,0xfe,0x3f,0xf0,0x26,0x62,0xff,0xea,0xff,0xed,0x9b,0xc3,0xfe,0x83,0xff,0x0f, + 0xbc,0x89,0x68,0x56,0xa3,0x2e,0xa9,0xed,0xbd,0x6c,0x89,0xae,0xff,0xdf,0xf0,0xcd, + 0x9e,0xbb,0x67,0x77,0xf6,0x5f,0xf3,0xae,0x72,0x74,0xa8,0xff,0xe2,0x00,0x70,0x8d, + 0x50,0x37,0x55,0x43,0xdd,0x34,0x54,0xfc,0xd8,0xd3,0x86,0xda,0xc9,0x6e,0x3a,0x3d, + 0x86,0x9f,0x63,0xe9,0x40,0xa3,0xa1,0xbf,0x31,0x99,0x4f,0x8f,0x3d,0x83,0x4f,0x33, + 0xdd,0x4d,0x77,0x7b,0xcf,0xb9,0xce,0x60,0xe0,0xeb,0x4c,0x2e,0xf3,0xe6,0x9b,0xf7, + 0xda,0x00,0x37,0x31,0x4d,0x3d,0xa2,0xeb,0x65,0xfc,0x2c,0x97,0x03,0xcc,0x85,0xf4, + 0x46,0x65,0xc7,0x3e,0x4d,0xfc,0x02,0x92,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x4d, + 0x85,0xaa,0x1a,0x23,0x91,0x76,0x41,0xc3,0x14,0xe0,0x79,0xd3,0x5f,0x87,0x5d,0x9c, + 0xbf,0xfd,0x1f,0xb1,0xd4,0xbe,0xd8,0xbe,0x48,0xb0,0xff,0x79,0xfc,0x95,0xe4,0x9d, + 0x0f,0x7d,0x17,0xb8,0x86,0xac,0xbf,0xe7,0x71,0xa3,0xd9,0x6c,0x5e,0x6f,0x29,0xdd, + 0x77,0x88,0xd4,0x6b,0xd9,0x44,0x35,0x17,0x8a,0x76,0xd3,0x25,0x00,0xd8,0x3b,0xf1, + 0x67,0x9f,0x7e,0xe5,0x13,0xef,0xba,0xed,0xde,0x93,0x27,0x4f,0x1e,0x27,0x0f,0xeb, + 0xc5,0x1f,0xb2,0x04,0xf5,0x9f,0xfd,0xc9,0xfe,0x9a,0xfe,0x51,0xfa,0xd1,0x5d,0x9e, + 0xdd,0xce,0xf1,0x93,0xec,0x92,0xf4,0xcf,0xb2,0xbd,0x49,0xd6,0x42,0x6f,0x7f,0xee, + 0xcf,0x9e,0xfb,0xd4,0x6f,0xde,0xf3,0xde,0x77,0x14,0x4e,0xbf,0xc7,0xdc,0x7c,0x93, + 0xcc,0x80,0x6e,0x14,0x86,0x90,0xd4,0xc7,0x4b,0x0a,0x00,0x5c,0x05,0x9e,0xbd,0xe3, + 0xf7,0x3e,0x71,0xdb,0xd7,0xcf,0x9f,0x47,0xcf,0xdb,0xd0,0x83,0xbc,0x7c,0x1d,0x3d, + 0xbf,0x8e,0x9e,0xe8,0x05,0xbd,0xb3,0xdf,0x5b,0x9f,0xbd,0xff,0xf7,0x9e,0x77,0xff, + 0x39,0xdf,0x93,0xb7,0xee,0xc2,0xee,0x4a,0x5f,0xc7,0xdb,0xb0,0x36,0x69,0x3d,0x98, + 0xed,0xd8,0xdf,0xdf,0x4b,0x76,0x46,0x7d,0x6f,0xaf,0xe7,0x7c,0xbe,0xd7,0x5a,0x84, + 0xfa,0xfd,0xfc,0xbd,0xe8,0x89,0xbf,0xb0,0x0e,0xfc,0xeb,0xd6,0x4e,0xf0,0x89,0x60, + 0x4d,0xf0,0xaf,0x7e,0xff,0x1f,0x2e,0x1a,0x6f,0x74,0x5f,0x40,0xcf,0x54,0xa3,0x20, + 0xf9,0xc0,0x55,0xe6,0xc1,0x3b,0x5e,0xb9,0x0d,0xc9,0xce,0xf9,0x93,0x44,0xe4,0x4e, + 0x7e,0x9d,0xbc,0xb1,0x44,0xe9,0xde,0xf3,0x44,0x35,0xa0,0xef,0x2c,0x9c,0xff,0xec, + 0x5b,0x11,0xe6,0xc7,0x7b,0xed,0xbf,0xf3,0xde,0xff,0x7b,0xe9,0xe5,0xa8,0xdf,0xee, + 0x3d,0xcf,0xc2,0xef,0x44,0xd8,0xa9,0xb5,0x0e,0xd6,0x43,0xf6,0xb1,0x92,0xc3,0xc6, + 0x8a,0xe1,0xfc,0xf1,0x0f,0x7d,0xfa,0x27,0xcc,0x37,0xac,0x0a,0x30,0x22,0xd9,0x5c, + 0xf7,0x7a,0x97,0x0c,0xe0,0x66,0xe1,0x41,0xe2,0x05,0x60,0x41,0xc7,0x56,0xf5,0xfc, + 0x49,0xf4,0xc0,0x4f,0xcc,0x49,0x4f,0xda,0x4e,0x52,0xff,0x99,0x5f,0xa9,0x65,0x24, + 0x1f,0x99,0xf5,0x7a,0x2d,0xe7,0xb7,0xbc,0xdf,0x7f,0xe7,0x93,0xf3,0xf9,0xde,0xf3, + 0xb6,0x06,0x23,0x9e,0xc2,0xbd,0xe7,0x4f,0xbe,0xf5,0x37,0xef,0x7b,0xcf,0x1b,0xb0, + 0x26,0x60,0xb4,0x13,0xa1,0xf4,0xf5,0x2e,0x12,0xc0,0xcd,0xc5,0x1d,0x9f,0xb8,0xed, + 0xa4,0x25,0x4c,0xae,0xf4,0x9f,0xdc,0x8f,0x87,0xbd,0xb5,0x93,0xf4,0x16,0xed,0xaf, + 0xa9,0x5f,0xa9,0xa5,0x82,0x3f,0x5c,0x2d,0x45,0x7f,0xa4,0x74,0x17,0x76,0x09,0x7e, + 0xee,0xc7,0xdf,0xfb,0x57,0x6f,0x2c,0x15,0x10,0xc9,0xa7,0xc0,0xeb,0x07,0xae,0x3d, + 0x0f,0xbe,0x72,0x9b,0x17,0x4e,0x3b,0x7f,0xb0,0x57,0x38,0x70,0x60,0xce,0xe3,0x17, + 0x9f,0x4d,0x1e,0x64,0xfe,0x0d,0xc0,0xc1,0xf3,0xf8,0x79,0xd2,0xd2,0x25,0xee,0x9e, + 0x78,0xe5,0x70,0xfe,0xe7,0x9e,0xbb,0xa7,0x7c,0xbd,0x85,0x3a,0x30,0x7a,0x65,0xec, + 0x7a,0x97,0x03,0xe0,0x66,0xa5,0x74,0xc7,0x6d,0xbe,0xc2,0xb6,0x07,0x0e,0xee,0x46, + 0xb8,0x07,0xdd,0xbe,0xf5,0xa0,0xf6,0x84,0x9d,0x0a,0xa7,0xb2,0xf0,0xd6,0x7b,0xea, + 0xd7,0x5b,0xb0,0x03,0x31,0x92,0x48,0x5e,0xef,0x32,0x00,0xdc,0xd4,0x20,0x0d,0x70, + 0x10,0xcb,0xd3,0x71,0x22,0x4d,0x07,0x8f,0x1f,0x1f,0xfc,0x69,0x3f,0xac,0x95,0xf1, + 0x2b,0x81,0xbc,0xb1,0x17,0x39,0x69,0xff,0x80,0x97,0x71,0x9f,0xcc,0x12,0x81,0x9e, + 0x94,0xd4,0xf3,0xfa,0xc0,0x53,0x02,0xb6,0x23,0xf0,0xaf,0xfe,0xc1,0xbc,0xde,0xc2, + 0xdd,0x17,0xa3,0x16,0xbd,0xde,0xb7,0x1f,0xb8,0xe9,0x79,0xe5,0xeb,0x58,0x03,0x1c, + 0x44,0x12,0x7c,0x4d,0x78,0x69,0x9f,0xb7,0x67,0xe9,0x05,0x41,0x09,0x9c,0x3f,0xff, + 0xdc,0xe2,0xce,0xf5,0x16,0xf0,0x9e,0x18,0xa3,0x50,0xef,0x07,0x6e,0x00,0x4a,0xbf, + 0x77,0x12,0x4b,0xe5,0x4b,0x7b,0x15,0xcd,0x97,0xdc,0x57,0xbf,0x3f,0xd9,0x37,0x83, + 0xf0,0xa4,0xbb,0x15,0xf6,0x3f,0x86,0x71,0x0d,0xac,0x98,0xc0,0x73,0xef,0xb8,0x71, + 0x73,0x02,0x8c,0x4c,0x11,0xa4,0x1f,0xb8,0x31,0x28,0xdd,0x76,0xf0,0xc4,0x91,0x97, + 0x9e,0x7c,0xe9,0xa5,0x27,0x91,0x88,0x3d,0xf9,0xd2,0xc1,0x27,0x07,0x7c,0xbc,0x84, + 0x56,0x21,0x7f,0xfd,0x56,0x7e,0xc9,0xfe,0xdb,0xdd,0xe3,0xa5,0x83,0x47,0x5e,0xb2, + 0x0e,0xf0,0x04,0x3a,0x52,0xfc,0x87,0x3e,0x1d,0xc1,0x7b,0xb7,0xf5,0xc0,0x71,0xc7, + 0x15,0x20,0x79,0x82,0xe7,0xcf,0x1f,0xff,0xd4,0x37,0x36,0x6f,0x48,0x0d,0xa0,0x16, + 0x26,0xe2,0xd7,0xfb,0xa6,0x03,0x80,0xcb,0x1d,0x27,0x9f,0x3c,0xb1,0x4f,0x3c,0x49, + 0xbf,0xdd,0xb7,0xad,0xb2,0x1b,0x7f,0xd2,0x7d,0x12,0xb0,0x0a,0x78,0xe9,0xa5,0x97, + 0x5e,0x72,0x1c,0x01,0xaf,0x16,0x70,0xfc,0x7d,0x17,0x6f,0x40,0x05,0x60,0x4c,0x82, + 0xf4,0x03,0x37,0x14,0xa5,0xdb,0x90,0x34,0x1d,0x46,0xcf,0xc3,0xe8,0xf5,0xf0,0x80, + 0xcf,0x5b,0xf0,0x8b,0xf5,0x06,0xbd,0x92,0x2d,0x58,0x8f,0xc3,0xe4,0xfb,0x13,0xee, + 0x57,0xc2,0xef,0x03,0xef,0x87,0x3c,0xbc,0xa7,0x07,0xf6,0x06,0x90,0x0b,0x63,0x57, + 0x06,0x9c,0xba,0xc0,0xf9,0xf3,0x2f,0x3d,0xfa,0x81,0xeb,0x2d,0xee,0x3c,0x91,0xe2, + 0xf5,0xbe,0xdb,0x00,0xc0,0xf3,0xca,0x4b,0xb7,0xdc,0x72,0xe5,0x96,0xdd,0xb3,0x97, + 0x75,0x07,0xe6,0xb0,0xf5,0x77,0x18,0x3d,0x4e,0x58,0x2a,0x01,0x7b,0x05,0x4f,0x3a, + 0x6e,0xc0,0x4b,0x07,0x8f,0x7b,0x11,0xc1,0x4f,0x7d,0xdf,0xf5,0x16,0x78,0x96,0x42, + 0x54,0x81,0xaa,0x3f,0x70,0xc3,0xf1,0xec,0xf1,0x2b,0xb7,0x5c,0xb9,0xff,0xca,0xd5, + 0xe0,0x96,0xab,0xb2,0xd5,0x2b,0x57,0xee,0xbf,0x05,0x6f,0xdb,0x52,0x08,0x27,0xb0, + 0x77,0x81,0x95,0xc0,0xc1,0x83,0x47,0x6c,0x27,0x00,0xab,0x80,0xf3,0xe7,0x4f,0xfe, + 0xd9,0x4f,0x5c,0x6f,0x91,0xa7,0x50,0x6b,0xe9,0x92,0x52,0x02,0x0d,0x00,0xdc,0x78, + 0xdc,0x7b,0xe5,0x91,0x27,0xd0,0xe3,0x11,0xf2,0x3a,0xe8,0x03,0xad,0xe5,0xac,0x4c, + 0xfe,0x59,0xff,0x9d,0xdf,0x9c,0x4f,0xde,0xc7,0xdd,0x3d,0xbc,0xcd,0x5a,0x5c,0x79, + 0xc2,0xd5,0x31,0x96,0x12,0xb0,0x55,0x80,0xd5,0x34,0x60,0xab,0x80,0xbf,0x7d,0xef, + 0x0d,0x93,0x12,0xbc,0x53,0x89,0x83,0xec,0x03,0x37,0x28,0x9f,0xb8,0x72,0x14,0x0b, + 0xe7,0x23,0xb7,0xef,0xe2,0x71,0xf4,0x91,0xa3,0xce,0x1b,0xf7,0xcb,0xa3,0xd2,0x05, + 0x77,0xb3,0x75,0x6f,0x2f,0x64,0x4f,0x8f,0xb8,0x58,0x8a,0xe7,0x09,0xe2,0xb8,0xdc, + 0x8f,0x75,0xc0,0x61,0x5b,0x05,0x3c,0x49,0x69,0x80,0x83,0x9f,0xbe,0x41,0x5a,0x02, + 0xcb,0xb9,0x12,0x48,0x3f,0x70,0xc3,0xf2,0xca,0x2d,0x2f,0xbf,0x7c,0xfb,0xd5,0x67, + 0xbf,0xf6,0xf1,0x08,0xfe,0x3b,0x7a,0xd4,0xf1,0x27,0x1c,0x37,0x80,0x68,0x80,0x23, + 0x76,0x8a,0x81,0xd5,0x16,0xf0,0xfb,0xe5,0xa9,0x1b,0x40,0x03,0x0c,0x87,0x4a,0x25, + 0xf0,0xfe,0x81,0x1b,0x97,0x3b,0x4e,0x1c,0x3b,0xf6,0x30,0x92,0xcf,0x97,0x6f,0x3f, + 0x86,0x5e,0x5e,0x26,0x6f,0x6e,0x47,0xcf,0x63,0xf8,0x3f,0xfe,0xa3,0xde,0xba,0xff, + 0xf0,0xc2,0xf6,0x0a,0xb7,0x93,0x17,0xfc,0x03,0xfe,0x85,0xbc,0x7f,0xf9,0x65,0x67, + 0x1b,0xe4,0xf1,0xb2,0x25,0xfd,0xc7,0x6e,0xf7,0xb6,0x60,0xbd,0xbe,0xcc,0x6c,0x93, + 0x7a,0x58,0xdf,0x91,0x05,0xad,0xed,0x59,0x4f,0xeb,0x4b,0x57,0x15,0x20,0x2d,0x70, + 0x14,0x79,0x02,0xf7,0x13,0x15,0x40,0x62,0x01,0x4e,0x6b,0x00,0x51,0x01,0x1f,0xba, + 0x78,0xbd,0x85,0x7f,0x4a,0xcd,0x74,0x2d,0xf1,0x47,0x80,0x06,0x00,0x6e,0x48,0xee, + 0x38,0x7c,0xec,0x61,0x82,0xfd,0x2f,0x08,0xc7,0x84,0x37,0xb2,0x1f,0xf7,0x8f,0x63, + 0xce,0x66,0x8f,0xe1,0xe7,0xcb,0x0f,0x5b,0xfa,0x06,0xe9,0x00,0xe2,0x08,0x5c,0x79, + 0x02,0x57,0x04,0x0e,0x5b,0xf9,0x07,0x24,0x16,0x78,0xf2,0xf8,0xc9,0x83,0xe7,0xff, + 0xf6,0xbe,0xeb,0x1c,0x04,0x50,0x13,0xe9,0x38,0x19,0x8d,0xed,0x7a,0xdf,0x62,0x00, + 0xf0,0xe7,0xc1,0x5b,0xee,0x7e,0xf8,0x6e,0x24,0x5b,0xb7,0x92,0x57,0xcc,0xdd,0xbe, + 0x82,0x78,0x9d,0xb8,0x55,0xfc,0x0a,0xa9,0x01,0xcb,0xb1,0x78,0xe4,0x76,0x12,0x0e, + 0xc0,0x5e,0xc0,0x61,0xab,0x49,0xd0,0x49,0x08,0x38,0xfe,0xb6,0xeb,0x9a,0x09,0xa0, + 0xe6,0xe3,0x96,0xf8,0x63,0xf9,0x07,0x1d,0x00,0xdc,0xa8,0x3c,0x7b,0xcb,0xad,0x98, + 0x87,0xd1,0xdf,0xdd,0xe4,0xdd,0xdd,0xe4,0xef,0x6e,0xf7,0x9d,0xfd,0xf5,0xad,0xd4, + 0x1b,0xea,0x1d,0xff,0xc1,0xfd,0x78,0xb7,0xf8,0x8b,0xfb,0xeb,0xdd,0xec,0x62,0xe2, + 0xd2,0x77,0xf3,0x6b,0x90,0xff,0x0f,0xdf,0x7a,0x37,0xad,0x9c,0x48,0xad,0xe0,0xf6, + 0xdb,0x8f,0x12,0x2f,0xc0,0xd6,0x00,0x27,0x9e,0xb4,0xf2,0x02,0x71,0x1d,0xe0,0x51, + 0xe3,0xfa,0x89,0x7f,0x33,0x86,0xc4,0x3f,0x6e,0x89,0x3f,0x48,0x3f,0x70,0x03,0xf3, + 0xec,0xfd,0xb7,0xde,0x7a,0xea,0xd6,0x87,0x44,0x51,0xc5,0x9c,0x72,0x5f,0x7a,0xd0, + 0xef,0x77,0xd9,0x0a,0x3d,0xd6,0x39,0xc5,0x2e,0x46,0x9e,0xec,0xe2,0xae,0x1a,0x38, + 0x66,0x85,0x04,0xb0,0x0a,0x78,0x02,0x6b,0x00,0x92,0x1a,0x78,0xf0,0x84,0xed,0x03, + 0xdc,0x73,0xfd,0xaa,0x00,0x99,0x6e,0xdc,0xb6,0xff,0x0a,0x38,0x00,0xc0,0x0d,0xcd, + 0x1d,0x8f,0x9c,0x7a,0x08,0xc9,0xff,0x43,0x84,0x5b,0xed,0x3f,0xfa,0xed,0xad,0xce, + 0x53,0xf6,0xce,0x7a,0x9e,0x22,0x4f,0xe6,0x37,0xd9,0x62,0x92,0xaf,0xa4,0x4b,0x3b, + 0x1f,0xc9,0x66,0xc9,0x57,0xf8,0x41,0xb4,0xd4,0x29,0x5e,0x09,0x10,0x27,0x00,0xc7, + 0x02,0xae,0xd8,0x1a,0xc0,0x8e,0x02,0x1c,0x3c,0xf9,0xd2,0xaf,0x5f,0x2f,0x05,0xd0, + 0x8e,0xc6,0xe3,0xae,0x03,0x00,0xc2,0x0f,0xdc,0xd0,0xbc,0xf2,0xf2,0xab,0xaf,0x3e, + 0xf4,0xd0,0xab,0xf8,0x85,0xf0,0x2a,0x79,0x50,0xbc,0x4a,0x7e,0xf4,0x9e,0xd6,0xe3, + 0xd5,0x57,0xb9,0x05,0x5f,0x75,0xb7,0x41,0x7e,0xb1,0x9e,0xec,0x9a,0xaf,0xca,0xb7, + 0xe9,0xec,0xd2,0xde,0x1c,0xb3,0x2c,0x77,0x2c,0x96,0x2e,0x70,0x74,0x80,0xe5,0x05, + 0xe0,0x36,0x07,0x1c,0x0c,0x74,0x35,0x00,0xc9,0x07,0x3a,0x79,0xf2,0xad,0xd7,0x29, + 0x15,0x50,0x0f,0xa5,0xe3,0x4f,0x5b,0x0a,0x00,0xa4,0x1f,0xb8,0xe1,0x79,0xff,0xc3, + 0xaf,0x86,0x5f,0x25,0xd8,0xff,0xdc,0xf7,0x61,0xf6,0x2b,0x29,0x61,0x67,0x49,0x6a, + 0xbd,0x9e,0x8b,0xf7,0x5e,0x24,0x2c,0x7d,0xeb,0x62,0xeb,0x85,0x53,0x8e,0x1f,0x40, + 0x69,0x80,0xdb,0x71,0x1c,0x00,0x87,0x01,0x9e,0x7c,0xf2,0x88,0xa5,0x00,0x3e,0xf4, + 0x57,0xd7,0x43,0xfc,0xcd,0x1c,0x92,0xfd,0xb4,0xe3,0x00,0x80,0x06,0x00,0x6e,0x74, + 0xee,0x3d,0xf5,0xea,0xab,0x87,0x0e,0xd9,0xa2,0x19,0x76,0xc5,0xde,0x53,0x0a,0xec, + 0x93,0xfb,0x82,0xd1,0x15,0xee,0xbb,0xb0,0xb8,0x20,0xb5,0x59,0xf9,0x06,0xc9,0xbb, + 0x43,0xaf,0x7a,0xfb,0xa6,0x37,0xc8,0x68,0x01,0xdb,0x13,0x38,0xe5,0x38,0x01,0x2f, + 0x63,0x0d,0x80,0xe3,0x00,0x57,0x48,0x62,0x30,0x19,0x37,0xe0,0xe0,0xf1,0x83,0xcf, + 0x5d,0x87,0x91,0x01,0x8d,0x4a,0x1a,0x61,0x39,0x00,0x90,0x00,0x04,0xbc,0x11,0x38, + 0x78,0x28,0x1c,0x46,0x1a,0x20,0xfc,0x2a,0xf5,0xb0,0x3e,0xa1,0x7f,0xec,0xd7,0xec, + 0x83,0x2c,0x77,0x88,0xff,0x6a,0xf0,0x07,0xbd,0xde,0x21,0x67,0xa7,0xce,0x57,0xf6, + 0x5e,0x0e,0x61,0xe5,0x10,0x66,0x74,0x00,0x12,0xff,0x87,0x6c,0x27,0xc0,0x6e,0x0c, + 0x78,0xe2,0x91,0xfb,0x89,0x06,0xb0,0x9a,0x01,0x0e,0xbe,0xef,0x9a,0x0f,0x0b,0xa6, + 0x6e,0x75,0x9f,0x7e,0x3a,0x9d,0x7e,0x3a,0x1d,0xb7,0x14,0xc0,0xf5,0xbe,0xb5,0x00, + 0xd0,0x9f,0xfb,0x91,0xd0,0x85,0x2d,0xb9,0xbb,0x31,0x71,0x8e,0xeb,0x55,0x5b,0xd9, + 0xb8,0x4a,0xc0,0x8e,0x06,0x60,0x15,0x70,0xbb,0x13,0x06,0xb0,0x9a,0x02,0x0f,0x3e, + 0x89,0x3c,0x80,0x4f,0x6f,0x5e,0x63,0xf9,0x5f,0x4d,0x62,0xf3,0xff,0x34,0xf1,0x00, + 0x4a,0xa0,0x00,0x80,0x37,0x04,0x77,0x3c,0x7c,0x5d,0xa5,0x7b,0x30,0x88,0x77,0xe0, + 0x78,0x02,0x96,0x17,0x60,0x35,0x07,0x1c,0x23,0x95,0x00,0xa2,0x00,0x0e,0xe3,0x96, + 0x40,0x5c,0x07,0x78,0xef,0xb5,0xed,0x09,0xd0,0x4e,0xa5,0x9f,0x49,0x77,0x49,0x0d, + 0xc0,0xab,0x00,0xdc,0xe0,0xc4,0xd3,0xd1,0xe2,0x5c,0xa5,0xb5,0xb2,0x95,0x68,0xe5, + 0xe7,0x8a,0x4f,0x8d,0xc1,0x78,0x45,0x37,0x1f,0x9f,0x78,0x28,0x3c,0x8d,0x44,0x0b, + 0xff,0xa1,0x17,0xf2,0xcf,0x7e,0xb5,0xbf,0x98,0x66,0x7f,0x9f,0xf6,0x16,0x98,0x76, + 0x57,0xa1,0xbf,0x76,0x5e,0xa6,0xc3,0xee,0x8a,0xce,0xa7,0x69,0xe6,0x17,0x77,0x77, + 0xde,0x1e,0xb9,0xcf,0xee,0x47,0x4e,0x0b,0xbc,0x7a,0xc8,0xd5,0x00,0x0f,0xe1,0x14, + 0x26,0xa2,0x01,0x6e,0x77,0x34,0x00,0xf6,0x00,0x90,0x02,0x38,0xb2,0x70,0x2d,0xc5, + 0x5f,0xbf,0x14,0x1f,0x1b,0x1b,0xeb,0x76,0xbf,0x6a,0xd7,0x00,0x6c,0xf9,0xbf,0x71, + 0x55,0x40,0xa9,0x7b,0x39,0xb1,0xa4,0x1b,0xaa,0xa3,0x25,0x9b,0xaa,0xa1,0x2f,0xc5, + 0x2e,0x77,0x6f,0xdc,0x23,0x06,0xae,0x0a,0x47,0xb0,0xa0,0x4d,0x53,0xd2,0xc8,0x0b, + 0xa5,0x27,0xea,0xf2,0xef,0x99,0xf5,0x28,0xe9,0x17,0xde,0x49,0x56,0x65,0x75,0xca, + 0x34,0xa5,0x71,0xa6,0x25,0xd2,0x3f,0xed,0x28,0x80,0x43,0x76,0x4d,0xc0,0xd6,0x00, + 0x77,0xdb,0x61,0x00,0x4f,0x01,0xe0,0x28,0xc0,0x5b,0xff,0xed,0xb5,0x13,0x7f,0xb5, + 0x8a,0x44,0xbf,0xfb,0xd5,0xb1,0xee,0x58,0x37,0xed,0xb4,0x00,0x58,0x97,0xf7,0xc6, + 0x94,0xa7,0xe4,0x5c,0x47,0x17,0x92,0x24,0x90,0x2a,0x50,0xeb,0x99,0x2a,0x4c,0x56, + 0x72,0x53,0xf1,0xe0,0xcb,0x8e,0x59,0x9e,0xa5,0xe4,0x6c,0x9a,0x12,0xce,0x69,0x1f, + 0x59,0x95,0x6a,0x00,0x66,0x61,0x46,0xe2,0xa7,0xd9,0x6d,0xb0,0x4a,0x85,0x11,0xf6, + 0x69,0xc9,0xc2,0x9c,0x76,0x42,0x3a,0xc0,0x89,0x03,0x38,0x6d,0x01,0x24,0x1f,0x88, + 0xe4,0x02,0xd8,0x1e,0xc0,0xff,0xf1,0xf8,0x35,0x93,0xff,0x42,0x12,0xd9,0xfe,0x6e, + 0x37,0x89,0x55,0x40,0x3a,0xcd,0xe4,0x00,0x06,0xa0,0x74,0x20,0x91,0x68,0xa1,0xc7, + 0xca,0x4a,0xc2,0x7a,0x38,0x9c,0xf3,0x59,0x21,0xd9,0x22,0x3f,0xaf,0xe0,0x55,0xdc, + 0xe5,0xd1,0xbf,0x95,0x54,0x90,0xdd,0xc5,0x43,0x59,0xdd,0xbf,0x72,0xd4,0x34,0x3b, + 0x17,0xfa,0x57,0x04,0x8a,0x78,0x8f,0x2d,0xee,0x70,0xe9,0xb7,0x3c,0x15,0x67,0xee, + 0xd3,0x68,0xc2,0x5a,0xa7,0xb5,0xe2,0xad,0xc1,0xaf,0xb7,0xc2,0x7d,0xf0,0xce,0x30, + 0x91,0x1f,0xb8,0x92,0x12,0x6d,0xe1,0x35,0xf1,0x15,0x5b,0x61,0xb6,0xdb,0x8a,0xfa, + 0xac,0x90,0x23,0x37,0x43,0x64,0x4e,0xbc,0x9d,0xe9,0x8a,0xb5,0xa9,0x44,0x62,0x65, + 0x45,0x7a,0xf6,0x2b,0xd4,0x3b,0xea,0x7d,0x4b,0xb8,0x51,0xb9,0x96,0x64,0x1d,0x44, + 0xd5,0xa7,0x0c,0x15,0x49,0x91,0x59,0x61,0xce,0x09,0x95,0x87,0x44,0x65,0xe0,0xeb, + 0xf3,0xae,0x57,0xa7,0x89,0x9c,0xb9,0xcc,0x62,0x7f,0xc0,0x7e,0xe3,0x3c,0x66,0xbd, + 0x8f,0xd4,0x02,0xe8,0x6b,0xe7,0xb3,0xfd,0x7e,0xd6,0x5a,0x64,0x76,0x9a,0x5a,0x94, + 0x5a,0xd2,0xdb,0x86,0xfd,0x93,0xb3,0xaa,0xb5,0xb0,0xfd,0x9c,0x0d,0x7b,0xeb,0x61, + 0xc8,0x1a,0xbc,0x33,0xe0,0xf9,0x00,0xa7,0xec,0x38,0xe0,0x31,0x92,0x11,0x8c,0xbb, + 0x05,0xda,0xfd,0x01,0xee,0xbb,0x56,0xe2,0xaf,0xe6,0x88,0xf0,0x27,0xf1,0xcb,0x18, + 0x09,0x01,0x0c,0xd4,0x03,0x30,0xdd,0x30,0x75,0xdd,0x34,0x54,0xc1,0x22,0x47,0x7c, + 0x66,0x0b,0xaf,0x1a,0xba,0x5e,0x37,0x55,0x55,0x90,0xe2,0x5a,0xff,0x9d,0xc5,0x27, + 0xb4,0xcd,0x7e,0xa7,0x53,0x98,0xeb,0x53,0x8a,0x4a,0x9a,0x51,0x46,0x47,0x6c,0x04, + 0x4f,0xb4,0x6c,0xe6,0xec,0x55,0x5b,0xf8,0xd8,0x07,0x59,0x93,0x65,0xf3,0x52,0xe0, + 0xcb,0x6a,0x53,0x51,0x23,0x65,0x73,0xc7,0x68,0x0a,0x7b,0x5c,0xf6,0xb9,0x40,0x05, + 0x13,0x9f,0xdb,0xa6,0xb0,0xbc,0x2e,0x7a,0x46,0x45,0x43,0x47,0xcb,0x6e,0x8a,0x37, + 0xa2,0x1f,0x09,0x61,0xa7,0x3b,0x11,0x6b,0xa7,0xdc,0xa6,0xcc,0xa8,0xf4,0x20,0xd3, + 0x11,0x43,0x52,0x5e,0xd0,0xca,0x6a,0x68,0xd0,0xeb,0xa3,0x9c,0x38,0x34,0xed,0x0a, + 0x34,0xcf,0xac,0xfb,0x32,0xcd,0xbe,0xe3,0xbe,0x12,0x17,0xe1,0xff,0x4b,0xde,0x30, + 0x1f,0x85,0x4d,0x5b,0x5a,0xc6,0x39,0xb2,0xb0,0xa5,0x07,0x68,0x05,0x40,0xda,0x05, + 0xdd,0x40,0xe0,0xc3,0x96,0x0b,0x80,0xf3,0x81,0x6f,0x39,0x7c,0x0b,0xe9,0x12,0xf8, + 0xdc,0x7f,0x1c,0xf4,0xb6,0xec,0x92,0x4c,0xb2,0xfb,0xbd,0xef,0x75,0x93,0x08,0xa4, + 0x07,0xc6,0xe8,0x00,0x60,0x20,0x25,0x10,0x6f,0x17,0x5a,0x5b,0xab,0x85,0x88,0xc9, + 0x97,0x23,0x49,0x89,0x23,0x1c,0x30,0x13,0x2b,0xd9,0x85,0xb6,0x2e,0x48,0xd1,0x68, + 0xbf,0x5d,0x95,0x8a,0x0b,0x41,0xba,0x47,0xa9,0x4b,0xb9,0x9e,0x47,0x5e,0xca,0xb4, + 0x5b,0x89,0x8e,0xe4,0x88,0xfd,0xa9,0xda,0xab,0x56,0xf4,0x56,0x62,0x71,0xa1,0x51, + 0x17,0xe5,0x2b,0x10,0xea,0x44,0x90,0x2b,0x4a,0x53,0x19,0x49,0x24,0xb2,0x5a,0xa3, + 0x2e,0x5c,0x2c,0x5e,0x06,0x6d,0xe2,0xc3,0x1a,0xba,0x1b,0x4b,0x91,0x1d,0xfe,0x42, + 0x99,0x12,0xf9,0x37,0x6b,0x2b,0xb5,0x85,0x6d,0xf1,0x46,0xf4,0x23,0xcb,0x5f,0xd0, + 0xf6,0xd2,0xd0,0x59,0x72,0x41,0xb9,0x05,0x37,0xe5,0x2e,0xdd,0x84,0xda,0x46,0x47, + 0xb8,0xc9,0x2e,0xdb,0x9c,0x32,0x54,0x7d,0xf0,0x39,0xe6,0x9f,0xbd,0xdb,0x15,0xaf, + 0x69,0xfb,0x39,0x6b,0x5b,0x6a,0x4f,0x2e,0xc3,0xac,0xc5,0x77,0x2d,0xfd,0x34,0x25, + 0x9c,0x8e,0x1d,0x9f,0x76,0xcd,0xb9,0x2d,0xba,0xee,0xb6,0xdc,0x5f,0xad,0x6f,0x1c, + 0x11,0x0f,0x3b,0x0b,0x7a,0xde,0x81,0x77,0x20,0x5e,0x3d,0xc2,0xde,0x83,0x57,0x11, + 0xc0,0xb5,0x80,0xb0,0x5b,0x09,0xb0,0xda,0x01,0x70,0x97,0x20,0xd2,0x0e,0x88,0xaa, + 0x00,0xff,0x70,0x6d,0xda,0x00,0xcc,0x62,0x97,0x08,0xbf,0xa5,0x00,0xbe,0x3a,0x96, + 0x1e,0xb0,0x05,0x20,0x5e,0x28,0x2c,0x27,0x16,0x0b,0xeb,0x26,0xaf,0xd1,0x7d,0x94, + 0xbf,0x32,0x61,0x6e,0x2d,0xc7,0x32,0x17,0xa9,0xf0,0x9d,0x4d,0xa6,0xcf,0x1e,0x93, + 0xd9,0xa0,0x9d,0x23,0x37,0x33,0xbd,0xea,0x12,0xa5,0x4c,0xa3,0xf2,0xe2,0xa2,0xb6, + 0x5e,0x97,0xd8,0x20,0x1f,0xe6,0xed,0x55,0xab,0x23,0x2b,0x2d,0x22,0x32,0xbb,0xbb, + 0x37,0xcd,0x03,0xc1,0xae,0xa9,0xc7,0x7c,0xbd,0x85,0x76,0x78,0x51,0xdc,0xe1,0x96, + 0xcf,0xb9,0x0d,0x6b,0xcb,0x52,0xdd,0x26,0x11,0xc5,0x90,0x11,0x5b,0xae,0xad,0x4a, + 0x14,0x71,0x3f,0x16,0xf9,0x2d,0x0d,0xb7,0x2b,0x67,0x3b,0x6b,0x62,0x11,0x68,0xca, + 0x87,0x91,0xcf,0x18,0xda,0x76,0x59,0xb8,0xfd,0xaa,0x11,0xc4,0x03,0x14,0x38,0x79, + 0x28,0xec,0x48,0xac,0x2b,0x89,0xd3,0xb4,0x14,0x7a,0x4e,0x7a,0x78,0xda,0xfb,0x79, + 0xd6,0x15,0xd9,0x69,0x6a,0x71,0x47,0xca,0x69,0xc3,0x4d,0xfd,0xc8,0x2e,0x4f,0x43, + 0x2f,0x18,0xf6,0xfe,0xcd,0xf2,0x55,0x11,0xc6,0x0d,0xb0,0xe3,0x00,0x96,0x06,0xf0, + 0x82,0x00,0x76,0x15,0xe0,0x70,0xf9,0x9a,0x28,0x80,0x2c,0x76,0xfd,0x93,0x9f,0x8d, + 0x7e,0xc9,0x56,0x00,0x71,0x77,0x08,0x90,0x60,0x2a,0xa0,0x54,0x28,0x54,0x2c,0xf9, + 0xe7,0x36,0xbc,0xe3,0x23,0x83,0x45,0x3d,0xd6,0xaa,0x65,0x24,0xc5,0x4e,0xeb,0xbd, + 0xbb,0xb9,0xc6,0x54,0xf0,0x01,0xd2,0xea,0xbd,0xaa,0xda,0xa3,0xeb,0x43,0x2b,0xc8, + 0x8a,0x9b,0xc1,0xad,0x78,0xc5,0x39,0x86,0x91,0x04,0x12,0xc7,0x36,0x16,0xc7,0x5d, + 0xdd,0x9c,0xaa,0xff,0x41,0xf9,0x9c,0x74,0x3d,0x81,0x6c,0x74,0x5b,0xb4,0xff,0x3e, + 0xce,0x52,0x49,0x2b,0xc8,0x45,0x51,0x22,0xff,0x29,0xb3,0x36,0x14,0x43,0x37,0x62, + 0x67,0x50,0xf9,0xe7,0x15,0x75,0x49,0x6b,0x54,0x56,0x16,0xd7,0x1a,0xc2,0x4e,0xa7, + 0xa4,0xf2,0xdf,0xad,0x47,0xd6,0xd6,0x85,0x33,0x6a,0xaa,0xea,0xe6,0x6e,0x66,0x9d, + 0x78,0xf0,0xe8,0x74,0x98,0xd2,0x00,0x9e,0x39,0x77,0x45,0x72,0x36,0xec,0x49,0x3d, + 0x25,0x9b,0xae,0x1e,0xa0,0x3e,0xb2,0xb5,0x7e,0x6f,0xe1,0x30,0xa5,0x13,0x6c,0xdb, + 0xef,0xca,0x33,0x13,0x57,0x70,0xa3,0x08,0xb3,0xd3,0xd3,0x8c,0x0e,0x99,0xf5,0x8e, + 0x8c,0x52,0x01,0x87,0xec,0x28,0x80,0xdd,0x2f,0x88,0x54,0x01,0x1e,0x21,0x1e,0xc0, + 0x91,0x83,0x2f,0x7d,0x7a,0xf0,0x9a,0xd9,0xe0,0xe8,0x21,0x64,0xfd,0xbf,0x14,0xc5, + 0x7c,0x29,0x4a,0x6a,0x00,0x4f,0x33,0xf6,0xbf,0xaf,0x0a,0x20,0x37,0x3f,0x2b,0xb9, + 0xf9,0x7e,0x95,0xb9,0x94,0x5e,0x5b,0x8e,0xad,0xb6,0x23,0x82,0x01,0x58,0xea,0x55, + 0x6f,0x1f,0xab,0x19,0x53,0xcd,0x01,0xae,0x47,0x33,0xe3,0xdf,0x14,0x90,0x8d,0x2c, + 0xa3,0x23,0xde,0xae,0x07,0x75,0x27,0x9a,0x53,0x2d,0x7b,0xcd,0x9c,0x99,0x58,0xae, + 0x11,0xdf,0x25,0xf8,0x91,0xd0,0xe4,0xfb,0x5d,0x4d,0x9e,0x09,0xa2,0x70,0x2e,0x8a, + 0x0a,0x67,0x55,0x7e,0x63,0x4a,0x9d,0xe1,0x65,0x24,0x8a,0xeb,0x82,0xfd,0x97,0xdc, + 0x8d,0xa8,0x99,0x5d,0xc6,0x75,0x05,0xe1,0x46,0xf4,0x63,0x8d,0xdf,0xf7,0x28,0x2e, + 0x02,0xda,0x69,0x93,0xbf,0xa0,0x6e,0xdc,0x84,0xa1,0xaa,0x0e,0x2f,0x95,0x05,0x73, + 0xa1,0x1a,0x6a,0x63,0x57,0x39,0x1c,0xef,0x3a,0x34,0xcd,0x8a,0xba,0x23,0x7d,0xe4, + 0x93,0x6b,0xcf,0x67,0x29,0x6f,0xc0,0x5e,0x86,0x96,0x58,0x46,0x4f,0xb8,0xda,0x63, + 0xd6,0xae,0x0a,0x50,0x51,0x42,0x4f,0x75,0x38,0x72,0x2d,0x84,0x0f,0xbc,0xbd,0xbb, + 0x1a,0x80,0xab,0x24,0x78,0x2a,0xe0,0x50,0xd8,0x4d,0x0a,0xc6,0xed,0x00,0x58,0x01, + 0xe0,0xc1,0xc1,0x0e,0x9f,0x78,0xf2,0xe0,0x35,0x19,0x0f,0x30,0xd1,0xfd,0x5e,0x32, + 0x6a,0x43,0x1c,0x80,0xb1,0x78,0x3a,0x3e,0x48,0x17,0xa0,0x52,0xa7,0x81,0xfc,0x7f, + 0x6d,0x5d,0xb0,0xa6,0xaa,0x8f,0x36,0x4f,0x59,0xc5,0xae,0x2c,0xc8,0x50,0xaf,0xdb, + 0x1f,0x2d,0xa8,0x53,0x03,0xca,0xdc,0xba,0xaf,0x35,0x49,0x44,0x5a,0x2b,0x59,0x54, + 0x8b,0x0f,0xee,0xc5,0x3b,0x8e,0xe9,0x84,0x91,0x68,0xc5,0x16,0xda,0xe2,0xb1,0x07, + 0xa2,0x39,0x35,0x14,0xec,0x9a,0x7a,0x14,0xcd,0x04,0x76,0x96,0xc4,0x1d,0xfa,0x39, + 0x4b,0xd9,0x06,0xf2,0xc6,0x90,0x28,0x0a,0x77,0x43,0x0c,0x3d,0x24,0xeb,0xa3,0xe8, + 0x46,0x14,0x06,0x3f,0x99,0x36,0xbf,0xef,0x5a,0x04,0xdb,0xff,0x19,0xd1,0xa1,0x9a, + 0x93,0x1c,0x61,0x49,0x33,0xd7,0x24,0x41,0x07,0x75,0xb3,0xd9,0x92,0x2c,0x1d,0x80, + 0xa3,0x61,0xda,0xe0,0x0b,0x0e,0xbc,0x6b,0x8d,0x5d,0x15,0xe1,0x85,0x03,0x1c,0x7b, + 0xee,0x48,0xf4,0xec,0x34,0xad,0x21,0xc2,0xd3,0xb4,0xec,0x3a,0xba,0x40,0xf0,0xe9, + 0xc3,0x94,0x3b,0x30,0x4b,0xad,0x45,0x1d,0x8e,0xa7,0x8e,0x9c,0x8d,0x7b,0x2e,0x00, + 0x69,0x09,0x20,0x83,0x04,0xdc,0x8d,0x83,0x00,0x76,0x7f,0x20,0x5c,0x05,0xf8,0xd7, + 0x57,0x7f,0x28,0x80,0x46,0x0a,0x09,0x7d,0x34,0x9a,0xc2,0x20,0x0f,0x00,0x57,0x00, + 0xdc,0x3e,0x00,0x01,0x23,0x80,0xd9,0xc6,0x72,0x6b,0x14,0x4b,0x13,0x7f,0x43,0x7d, + 0x82,0x5d,0x51,0xdd,0x2a,0x76,0x82,0xc3,0x10,0xf1,0x8f,0xfe,0x14,0x1b,0x53,0x92, + 0x06,0x83,0x29,0xec,0x35,0xe2,0x07,0x7a,0x4e,0x35,0xa7,0x78,0x13,0x69,0xfa,0x35, + 0x3f,0x55,0x74,0x5c,0xa9,0x6e,0xe8,0x72,0xff,0x5f,0xb6,0x9b,0x8e,0xbd,0xa6,0x57, + 0x65,0x1e,0xdc,0x35,0xc3,0x6b,0xf8,0x44,0xed,0xfc,0x09,0x99,0xc8,0x59,0xca,0x2c, + 0xe9,0x82,0xb9,0x6c,0xfb,0x28,0xcb,0x44,0x03,0xdb,0xff,0x86,0x10,0xdb,0x90,0x98, + 0xe2,0xb1,0x48,0x67,0x79,0xab,0xb3,0x14,0xd9,0x19,0xf4,0x64,0x04,0x45,0x9d,0xd0, + 0x97,0x57,0x6a,0xda,0xb6,0xa8,0x50,0x65,0xfe,0x4e,0x74,0x27,0x82,0xac,0x05,0xbf, + 0x68,0x53,0xdd,0x34,0x02,0x35,0x00,0x8b,0x7c,0xe2,0x55,0x56,0x64,0xd9,0x00,0x9e, + 0xf7,0x8b,0x2b,0xf8,0xb3,0xfc,0x37,0xb3,0x9c,0x08,0x33,0x91,0x40,0xea,0x0d,0x5d, + 0x05,0x90,0x35,0x27,0xb8,0xbf,0xda,0x7b,0x98,0xf5,0x5c,0x7e,0x26,0x1a,0xc1,0xb6, + 0x09,0x1e,0x3a,0xe4,0xd4,0x01,0x88,0x02,0xb0,0x5b,0x01,0x4e,0x9c,0x78,0xe9,0xc4, + 0x37,0x06,0xbb,0x2f,0x83,0xd3,0xac,0xb8,0xe2,0x7f,0x06,0xfd,0x11,0x07,0x20,0xfd, + 0xf4,0x60,0x19,0x00,0x09,0xe4,0x4d,0xbf,0x57,0x9b,0xd1,0x05,0xff,0x5f,0xea,0xfc, + 0x29,0xca,0xf7,0xf4,0x4e,0xc5,0x2a,0x76,0xdc,0xc1,0x94,0xc7,0xfc,0x76,0x91,0xd3, + 0xa7,0x24,0x12,0xd7,0x44,0x3a,0x41,0x55,0x0d,0x1b,0x55,0x94,0x66,0xa3,0xf2,0xac, + 0x74,0x73,0x93,0x7a,0xcb,0x0a,0x7c,0xfb,0x5c,0x14,0xe4,0x69,0x60,0x8d,0x62,0xfd, + 0xe1,0x0f,0x6e,0x8d,0x17,0x55,0x99,0x91,0xee,0xea,0x61,0xff,0x55,0x6b,0x5d,0x55, + 0xb5,0xf4,0x92,0x6a,0x29,0x27,0x02,0x3a,0xda,0xc1,0x03,0x5c,0x78,0x87,0x31,0xd9, + 0x0e,0xfd,0x9c,0xa5,0xa1,0x08,0xae,0x8d,0x6d,0x0b,0xae,0xb8,0x24,0xf4,0x90,0x8e, + 0x64,0xe4,0x37,0xc2,0xbe,0x0c,0xaa,0x7d,0x3a,0xce,0xa3,0x49,0xce,0x0c,0xbd,0x13, + 0x14,0x35,0x52,0xa8,0xd6,0x4e,0xf9,0x7b,0x24,0x6b,0xa5,0xac,0xa8,0x05,0x51,0xe7, + 0x34,0x91,0xfb,0x3f,0xbc,0xdb,0x74,0xb3,0x47,0x68,0x33,0x4f,0x07,0x01,0x9d,0x0a, + 0x00,0x6d,0xee,0x3d,0x19,0xa7,0x7d,0x00,0x46,0x84,0x5d,0xb1,0x9d,0xa6,0xb4,0x01, + 0x15,0xdb,0xa7,0x43,0x0c,0x61,0xf7,0x2d,0xd3,0x4c,0x40,0x2d,0x3d,0xeb,0x56,0x30, + 0x5c,0xd3,0x3f,0xcd,0x06,0x02,0x3d,0x05,0x70,0x2b,0xc9,0x05,0xc4,0xa9,0x80,0x44, + 0x01,0xfc,0x93,0xab,0xdd,0x11,0xb0,0xfd,0xd4,0xf7,0xbe,0x94,0x24,0xc2,0x1f,0x3a, + 0x43,0x3c,0x00,0x2c,0xff,0xe9,0xb8,0x3b,0x08,0x70,0x10,0x17,0xa0,0x85,0xa5,0x09, + 0x2b,0x7f,0xde,0xe2,0xf8,0x04,0xbb,0xc6,0x22,0x19,0x6c,0x76,0xd6,0x85,0x26,0x2a, + 0xbf,0x06,0x43,0x65,0x4e,0x6f,0x4a,0x04,0x0e,0x95,0xc4,0x4d,0x63,0xc7,0xac,0xd7, + 0x75,0xbd,0xac,0xd7,0xeb,0xb8,0x41,0xdf,0x52,0x41,0x5e,0xc9,0x52,0x87,0xa4,0x47, + 0x3f,0x67,0xae,0x58,0x95,0x6a,0x89,0xe1,0xc3,0xc2,0xba,0xb9,0x69,0xe0,0x07,0x52, + 0x2d,0xa8,0x54,0xe2,0xff,0xcd,0x82,0xbd,0x1d,0x5c,0x65,0x8e,0xe1,0xe6,0x35,0x69, + 0xd3,0x01,0x11,0x79,0xa2,0x8c,0x36,0x0d,0xfa,0x9f,0xa3,0xa1,0x8c,0x66,0x47,0x76, + 0x38,0xbd,0xc0,0xce,0x12,0xda,0x61,0x59,0xb0,0xd1,0x0d,0x1f,0x67,0xa9,0xa2,0x57, + 0xac,0xba,0x0d,0x7f,0x80,0xa2,0x29,0x8e,0x37,0xb4,0x8a,0xd5,0x6c,0x27,0xc9,0xa6, + 0x54,0xad,0xeb,0xe0,0x5d,0x03,0xfc,0x44,0x7f,0xe8,0xad,0x1a,0x79,0x86,0xdb,0x52, + 0xde,0xb4,0x15,0x2a,0x7f,0x3d,0x63,0xe2,0x01,0xc6,0xdb,0x75,0x59,0x7b,0x26,0xba, + 0x38,0x03,0x07,0x47,0x1c,0xde,0xf5,0x2a,0x65,0xaf,0x67,0xa7,0x69,0x01,0xf6,0x6c, + 0x39,0x1b,0x13,0xa4,0x65,0x97,0x8e,0xe4,0x51,0x3f,0xcf,0x7a,0x6b,0xb2,0x75,0x0b, + 0xc6,0xa9,0xe7,0x32,0x03,0x3c,0xff,0x62,0x96,0x51,0x45,0xb3,0x9e,0xba,0xa0,0xdc, + 0x0f,0xfc,0x24,0x1d,0x87,0xc3,0xac,0x02,0x40,0x55,0x00,0x5c,0x03,0x38,0x72,0xe2, + 0xd7,0x25,0xa5,0x6c,0x1f,0x51,0xab,0xdd,0x64,0xf4,0xa9,0x54,0x2a,0x44,0x20,0xf2, + 0x8f,0x15,0x80,0xeb,0xff,0x07,0x52,0xc8,0xf9,0x11,0xeb,0xe6,0x0b,0xa5,0xc8,0xe7, + 0x7e,0xa6,0x1b,0x99,0xe5,0x17,0x3b,0x85,0x75,0xc1,0xec,0x48,0x9a,0xa8,0x09,0x39, + 0x1d,0x15,0x3b,0x51,0x52,0x51,0x79,0x34,0xeb,0x91,0xf5,0xc6,0xf6,0xc5,0xf6,0xc5, + 0xed,0xed,0x46,0xa4,0x5c,0x7f,0xdc,0xe0,0x93,0x59,0x36,0xa5,0x19,0x65,0x38,0x8a, + 0x17,0xb3,0xa2,0xf8,0xc2,0x46,0xd1,0x56,0x77,0x4c,0xd3,0x1c,0x31,0xeb,0x23,0x75, + 0xac,0x5b,0xea,0xba,0x89,0x54,0x8b,0x23,0xff,0x49,0x7d,0xb4,0x82,0x8f,0xbd,0xbe, + 0x29,0x56,0x13,0x9a,0x58,0x1f,0xa1,0x55,0xb1,0x42,0xaa,0x63,0xd0,0xba,0x75,0x07, + 0xfc,0x4e,0xd7,0xd5,0x85,0x41,0x4d,0x5c,0xd2,0xad,0x2c,0x71,0x7b,0xf3,0xab,0x2c, + 0xe5,0x75,0x12,0xdb,0xd0,0x85,0x0b,0x26,0x9a,0xe2,0xf8,0x8c,0x36,0xb4,0xd2,0x59, + 0x93,0xc9,0x3f,0x3e,0x15,0xeb,0x5c,0xd0,0x45,0xd0,0x4d,0xdd,0x7a,0x43,0xde,0xd7, + 0xeb,0x86,0xce,0x67,0x76,0x55,0xcd,0x56,0x2b,0x8b,0x8a,0x80,0xe0,0x82,0x49,0xfc, + 0x9d,0x90,0xd1,0x40,0xbb,0xe4,0xe5,0x1f,0x69,0x1b,0xbf,0xdb,0x1f,0x80,0x63,0x61, + 0x4e,0xd8,0x59,0x7b,0x4e,0x09,0xac,0x63,0x7a,0xe9,0x25,0xa9,0xa8,0xdd,0x2c,0xa3, + 0x25,0xc2,0x94,0x1d,0xa7,0xf4,0x05,0xb5,0x29,0xa6,0xfa,0x4f,0xbb,0xfb,0x9e,0xa8, + 0xd3,0xaa,0xc8,0xab,0x0a,0xb8,0x4b,0xda,0x6e,0x80,0x13,0x04,0x20,0x55,0x00,0xdc, + 0x0a,0x78,0x3f,0xce,0x04,0x3e,0xf1,0x5f,0x47,0x84,0x3b,0xb3,0x9f,0x14,0xa2,0xc4, + 0xf9,0x0f,0x85,0x2e,0x5d,0xba,0x84,0x14,0xc0,0x99,0x14,0x92,0x7f,0x2f,0x03,0x20, + 0xe0,0x2c,0x20,0xe8,0xe6,0xaf,0xc4,0x2c,0xe5,0xcf,0x96,0x39,0x9f,0x70,0x4e,0xbc, + 0xad,0x0d,0x25,0x16,0x91,0xd9,0xe1,0x4b,0x8b,0x4f,0x83,0x61,0x11,0x89,0xbf,0xc1, + 0x8b,0x1b,0x36,0xb4,0x66,0x7d,0x7d,0x66,0xa9,0xb0,0xb6,0x90,0x41,0x8f,0x85,0xb5, + 0x42,0xfb,0x74,0xa4,0x6e,0xe7,0x21,0x52,0x1e,0x40,0x5e,0x72,0x02,0x13,0x46,0x02, + 0x1d,0xf1,0x92,0x24,0x8a,0xaf,0x36,0x8d,0x1d,0xbd,0xbc,0xde,0x68,0x9c,0x9e,0x99, + 0x39,0xbd,0xdd,0xd8,0x6e,0x9c,0x6e,0xe0,0xff,0xa6,0x53,0xdb,0x1e,0xd3,0x3b,0xa8, + 0x7a,0xad,0x9d,0x96,0x36,0x00,0xe0,0x43,0x2a,0x97,0xd7,0xf1,0x9a,0x48,0x1f,0x6d, + 0xcf,0x34,0xf0,0xff,0x19,0xe7,0x89,0xd9,0x19,0xd8,0xc5,0x7d,0xc6,0xf6,0xd1,0x85, + 0x7c,0x39,0x41,0x06,0x6d,0xe6,0x48,0x6c,0x43,0xf4,0xc6,0x24,0xa1,0x87,0x52,0x7b, + 0x98,0xb4,0x15,0x3e,0xbe,0x29,0x3b,0x95,0x11,0x3d,0xb2,0xbe,0x8e,0x4e,0x03,0x1d, + 0x3c,0xba,0x18,0xe8,0x6c,0x66,0xf0,0x39,0x9d,0x46,0x57,0x46,0xdf,0x89,0x72,0x5b, + 0xca,0x19,0x2b,0x56,0xb3,0x28,0xbf,0x53,0x89,0xbf,0x93,0x50,0xd7,0x24,0xd5,0x99, + 0xa6,0xd1,0x37,0xfd,0xa3,0x07,0xf7,0x86,0x05,0xb9,0xa4,0x7c,0x78,0xc7,0x85,0x0f, + 0xbb,0x96,0x98,0x56,0x0b,0x64,0x71,0x2a,0x28,0x48,0x6f,0xc3,0x5d,0x9d,0x72,0x0c, + 0x3c,0x01,0xef,0x4b,0x98,0xf6,0x1d,0xbc,0x30,0x64,0xd8,0x0b,0x33,0x7a,0x95,0x00, + 0x41,0x01,0x90,0x18,0xe0,0x91,0x7f,0x21,0x16,0xb3,0x7d,0x04,0xd5,0xfe,0x2d,0xf1, + 0x2f,0x16,0x2f,0x14,0x2f,0x5d,0x3a,0x83,0x23,0x00,0x5d,0xb7,0x0f,0x80,0x12,0x6c, + 0x1c,0xe0,0x39,0x1c,0xa2,0x5e,0x95,0x44,0x74,0xfd,0x52,0xd4,0x0a,0x05,0x64,0x43, + 0x25,0x4d,0x54,0x86,0xb4,0xc1,0x30,0x1a,0x51,0x4d,0xd1,0x51,0x47,0xf6,0x49,0x2f, + 0x37,0x96,0x16,0x56,0x3b,0x8b,0x35,0xc2,0x62,0x67,0x41,0x5b,0xda,0x2e,0xd7,0x91, + 0xaa,0x60,0x8e,0xc3,0x90,0x84,0xa0,0x8b,0x23,0xb1,0xe5,0x98,0x2c,0x03,0x01,0xf9, + 0x14,0x3b,0xfa,0x7a,0xbb,0xb0,0xa6,0x69,0x6b,0x0b,0xe4,0x6f,0x81,0xfc,0x45,0x1c, + 0x6f,0x3b,0xad,0x77,0x2a,0xe8,0x64,0xdb,0x65,0x49,0xee,0x40,0x53,0xdd,0x34,0xcb, + 0x78,0x65,0xb4,0x86,0xb6,0x40,0xd0,0xd0,0xff,0x35,0xf2,0x24,0x9f,0x16,0x74,0x21, + 0x72,0xde,0x0f,0xe4,0x2c,0x55,0x62,0xa8,0xb2,0x24,0xd8,0x7f,0x7f,0x67,0x09,0x7b, + 0x63,0x92,0x16,0x4a,0xd1,0x14,0x97,0xb4,0x36,0xce,0x83,0x12,0x15,0x31,0xe9,0x4f, + 0x59,0xde,0x5e,0xc2,0x97,0x01,0x3f,0xc8,0xa5,0x40,0x0f,0xf2,0xaa,0xad,0xb5,0x85, + 0xcc,0xae,0x09,0x73,0xab,0x55,0xcb,0x5c,0x7c,0x8f,0xb0,0xd3,0x8c,0xe4,0x84,0xf4, + 0x35,0xa4,0x3e,0xf9,0xa6,0xdc,0x4d,0x55,0x95,0xb5,0x15,0x04,0xe4,0xc1,0xbb,0x3d, + 0x01,0x77,0x83,0xfd,0x54,0x62,0xbf,0xf3,0xe5,0xac,0x53,0x43,0xa0,0xd5,0x02,0x23, + 0xb0,0xac,0x89,0x67,0x72,0x02,0xdd,0x60,0xe1,0xb4,0xd3,0x0c,0x40,0xfb,0x04,0x52, + 0x17,0x80,0x51,0x34,0xee,0x0e,0xec,0x2f,0xbc,0x16,0x04,0x4b,0x01,0x38,0xdd,0x01, + 0x48,0x1e,0x00,0xee,0x0b,0x80,0x15,0xc0,0x63,0x9b,0x7c,0x31,0xdb,0x47,0x8c,0x22, + 0x36,0xff,0x44,0xfa,0x11,0x45,0xe4,0x02,0x20,0x07,0xe0,0x7b,0x56,0x00,0x20,0x78, + 0x0d,0x20,0xa7,0x93,0x9c,0x18,0x51,0xa7,0xfb,0x04,0xbb,0x4a,0x85,0x76,0x85,0x34, + 0x51,0xf3,0xee,0xb7,0xb4,0xc1,0x70,0xac,0xa0,0xea,0x82,0xf1,0x6b,0x12,0x39,0x5d, + 0xd2,0x56,0x17,0x6b,0x67,0x13,0x2b,0x2b,0xcb,0xad,0x95,0x95,0x95,0xad,0xd8,0x62, + 0x66,0xad,0xbd,0xae,0xf3,0xae,0x65,0x5d,0xdc,0x6a,0xca,0xac,0xb5,0x62,0x19,0x49, + 0x1b,0x34,0x2e,0xf7,0xeb,0x85,0x85,0xd5,0xc5,0xc5,0xc5,0x6c,0x36,0x8b,0xff,0x30, + 0x8b,0xb5,0x25,0xc7,0xdb,0x8e,0x47,0x32,0xf9,0xe5,0xad,0x8e,0xd6,0xb0,0x8e,0x89, + 0x3d,0x01,0xd5,0xa8,0x97,0xdb,0x6b,0x99,0x55,0xb4,0x42,0xb6,0x96,0x45,0xcf,0x9a, + 0x0b,0xf9,0x5c,0xcb,0x36,0xfc,0xa2,0xf6,0xbe,0x90,0x3a,0x3a,0x72,0x96,0x1e,0xe7, + 0xfd,0x79,0xc1,0x06,0xdb,0x14,0xf5,0xc4,0x32,0xbe,0x1b,0x42,0x5a,0xbf,0x90,0xb4, + 0x87,0x5b,0x6e,0xad,0xb4,0x9d,0x4d,0xbe,0x60,0x34,0x55,0x13,0x9d,0x09,0xd2,0xad, + 0xce,0x25,0x60,0x58,0x10,0x02,0xf5,0xb8,0x95,0xd2,0x6a,0x16,0xe5,0x76,0x2a,0xb6, + 0x52,0x4e,0xa8,0x6d,0x49,0xc4,0x41,0x35,0x54,0xdd,0x37,0xfa,0x1b,0x80,0x23,0x61, + 0x2f,0x2e,0xef,0xb9,0xdb,0x8e,0xe5,0x0e,0xd3,0x5f,0x92,0x77,0xae,0x5f,0x3e,0x4b, + 0xfb,0xe5,0x7c,0x74,0xc0,0x75,0xe2,0xa9,0xf8,0x21,0xab,0x22,0xe8,0xaa,0x83,0x67, + 0xf1,0xa9,0x0c,0x00,0xcf,0xd7,0x70,0x74,0x13,0xa5,0x75,0xc2,0x82,0x07,0x80,0x47, + 0x0e,0xbf,0xd5,0x6e,0x04,0x20,0x35,0x80,0xc3,0xa7,0xf9,0x7b,0xb3,0x8f,0xb4,0x91, + 0xfb,0x8f,0xad,0xff,0x85,0x09,0xcc,0x85,0x22,0x91,0x7f,0xdc,0x09,0x88,0xee,0x03, + 0xd8,0x57,0x03,0xd8,0xd6,0x54,0xbc,0xf9,0x1d,0x9f,0x14,0x15,0xad,0x3d,0xb4,0x42, + 0x12,0x06,0xf8,0xe3,0x91,0x34,0x18,0x96,0x62,0xaa,0x29,0x36,0x2b,0x21,0x4b,0xab, + 0x6f,0x17,0x32,0x8b,0xb1,0x44,0x6b,0x39,0x4f,0xa8,0x54,0x96,0x57,0x56,0x6a,0x8b, + 0x99,0x42,0x03,0xb7,0x2b,0x32,0xa5,0xab,0xf1,0x3d,0x7e,0xa3,0x51,0x12,0x54,0xc7, + 0x19,0x08,0x42,0xc2,0x3a,0x2a,0xf7,0x0b,0x8b,0x35,0xdc,0x23,0x8e,0x46,0x33,0x6d, + 0x6f,0x3b,0xbe,0xad,0x4d,0xe6,0x57,0x6a,0xab,0x05,0x31,0x7f,0x0d,0x2b,0x0f,0x73, + 0x7d,0x69,0xa1,0x53,0xdb,0x4a,0xac,0x60,0x85,0xd4,0xb2,0x57,0x6e,0x79,0x9f,0xb4, + 0x1e,0x4d,0x9c,0x72,0xe2,0xed,0xb5,0x4a,0x82,0xd4,0xd1,0xb9,0xbd,0xc9,0x9d,0x25, + 0x54,0xbd,0xd6,0x13,0x72,0x57,0x5c,0xe2,0x5e,0x93,0x3c,0xa8,0x85,0xd3,0x42,0x65, + 0x1c,0x9d,0x49,0xbd,0xb1,0xb6,0x9a,0xdd,0x5a,0xa1,0xae,0x83,0xf7,0x36,0x2b,0x28, + 0xea,0x94,0x11,0x6b,0x91,0x22,0xc0,0xdf,0xd2,0x25,0x61,0xa7,0xa3,0x86,0xcc,0xfd, + 0x57,0x0d,0xa1,0x53,0xc1,0x40,0xbc,0xff,0x10,0x25,0x5d,0x5e,0xa4,0x9f,0x16,0x36, + 0x4a,0xb2,0xa7,0x3d,0xf1,0x73,0x7f,0x9d,0x9d,0xf6,0x7c,0x7b,0x5a,0xb4,0x6d,0x8f, + 0x21,0xcc,0xaf,0xec,0x1a,0x79,0xaf,0xa2,0x41,0x39,0x1c,0x61,0xaa,0xd6,0xe0,0x55, + 0x44,0xa6,0xdd,0xdf,0xdd,0x1d,0x91,0x3f,0xba,0x0a,0x60,0x75,0x08,0xb6,0x5a,0x01, + 0xb1,0x03,0x70,0x35,0x2b,0x00,0x2d,0x62,0xfe,0x8b,0xc5,0x89,0x6f,0xe5,0x72,0x97, + 0x2f,0x63,0x05,0x60,0xb7,0x00,0x3c,0x3d,0x48,0x1f,0x80,0x10,0xb6,0xa6,0xb2,0x7c, + 0x1e,0xbf,0x0a,0xdd,0x68,0x03,0xa7,0xdf,0x89,0x9d,0x68,0x64,0x0d,0x86,0x07,0x50, + 0x95,0x9a,0x17,0x53,0x54,0xf7,0x37,0xcb,0xdb,0xa8,0x7c,0x9e,0x45,0xd2,0x3f,0x39, + 0x39,0x59,0xad,0xce,0x23,0xf2,0xf9,0xe5,0x95,0xb3,0xd9,0xd5,0xb5,0x8b,0xc4,0xba, + 0xd0,0x1a,0xa3,0xc3,0x1b,0x5d,0x12,0x54,0x93,0x35,0x7c,0x21,0xbb,0x17,0x59,0x5a, + 0xad,0x25,0x96,0x2b,0xf9,0x4a,0xde,0x7a,0x56,0xf0,0xdb,0x8e,0xd3,0x34,0x51,0x1a, + 0x5e,0x9b,0xcc,0x57,0x12,0xd9,0x85,0xa5,0x88,0x24,0x81,0xd5,0x30,0x23,0x48,0x7b, + 0xc4,0x56,0x5a,0x68,0x25,0x01,0xfc,0x55,0x26,0x32,0xa8,0x91,0x2b,0x0d,0x93,0x7c, + 0x3e,0x49,0x76,0xa5,0x4f,0x57,0xc2,0x14,0x49,0x18,0xba,0x18,0x11,0xee,0x86,0x24, + 0xf4,0x90,0x88,0x0c,0x91,0x1b,0x21,0x56,0x83,0x76,0xf4,0xed,0x85,0x45,0xa2,0x5c, + 0x2b,0xf6,0xc3,0x3e,0x07,0xfc,0x48,0x98,0xbc,0xa2,0xb6,0x14,0x6a,0x5b,0xdc,0xa9, + 0xd0,0x4a,0xd9,0xd5,0x75,0x49,0xe3,0xff,0x14,0xba,0xc5,0xbb,0xc9,0xfd,0xf5,0x38, + 0x3a,0x3d,0xed,0xba,0x00,0x9c,0xc0,0xb1,0xf9,0xf7,0x94,0xec,0x3a,0xd2,0xef,0x75, + 0xe4,0x71,0x7b,0xf0,0x52,0x71,0x3d,0x4f,0x03,0xd0,0x61,0x04,0x46,0xa9,0x84,0xd9, + 0xf7,0x54,0x5a,0x11,0x95,0x82,0x38,0x4b,0x39,0x14,0x54,0x4c,0x91,0xaa,0x3d,0x84, + 0xc9,0xd8,0x40,0xa7,0x48,0x5f,0x00,0x3b,0x04,0x70,0xf8,0xc4,0xbf,0xdb,0xe4,0x6f, + 0xce,0xbe,0x61,0x4c,0x58,0xde,0xff,0xc4,0xe5,0xcb,0xe7,0x2c,0x05,0x40,0x22,0x80, + 0x76,0x06,0x40,0xdc,0x69,0x01,0xec,0xe7,0x03,0x44,0x47,0x6a,0x2d,0x69,0x9b,0xb8, + 0x5f,0x8a,0x1a,0xce,0x16,0x93,0x66,0x8b,0x8a,0x35,0xc0,0xcf,0x46,0x0c,0x49,0xac, + 0x78,0x13,0x15,0xcf,0xb5,0x4e,0x6d,0x65,0x19,0x4b,0x28,0x96,0x7f,0xa4,0x01,0xb0, + 0x0e,0x40,0x1a,0xa0,0xd6,0x59,0xbb,0xc8,0x67,0x16,0xa9,0x7c,0x43,0x64,0x57,0xef, + 0x2c,0x27,0x56,0x65,0xf2,0x8f,0x2c,0xb8,0xd6,0xd9,0x42,0xc5,0xbe,0x3a,0x39,0x6f, + 0x31,0x89,0x37,0x5c,0x73,0x6a,0xbc,0x25,0x6d,0xb8,0x8a,0x76,0x73,0x76,0x51,0x6b, + 0x47,0x1e,0x17,0x15,0x00,0x3e,0xae,0xd5,0xda,0x4a,0x05,0x1d,0x14,0x5e,0xb7,0x3a, + 0xef,0x32,0x49,0x3e,0x75,0x7c,0x9b,0x38,0xfd,0x28,0x65,0xda,0xcb,0xc4,0x59,0xe2, + 0x23,0xa0,0x7e,0xf2,0x12,0x1d,0x41,0xa6,0x58,0x96,0xa1,0x24,0x09,0x3d,0x24,0xf4, + 0x21,0x79,0x5b,0x21,0xaa,0x06,0x5d,0x5c,0x40,0xe7,0x91,0x9f,0x97,0xb1,0x6c,0xf2, + 0x8a,0x3a,0x69,0x35,0x8b,0x96,0x85,0x66,0x1a,0xc1,0xdf,0x99,0xc3,0x8d,0xff,0xbc, + 0x32,0x6b,0xaa,0x9b,0xea,0xc0,0x9e,0x11,0xcb,0xc9,0xb0,0x6b,0xa1,0x67,0xbd,0xea, + 0xbe,0x17,0x7d,0x9b,0xa5,0xdc,0x77,0xe7,0x9b,0x30,0x25,0x83,0x94,0x62,0x60,0x71, + 0xd3,0x09,0xbd,0x58,0x80,0x97,0xde,0xeb,0x55,0x05,0xbc,0xf4,0x21,0x5a,0x3f,0x84, + 0xe9,0xad,0x78,0xe1,0x3f,0xc7,0x3f,0x70,0xf7,0x68,0xb7,0x02,0x90,0x4e,0xc1,0x76, + 0x08,0xe0,0xd8,0xed,0x47,0x49,0x1a,0xd0,0x37,0xd7,0xa7,0xae,0x16,0x8d,0x68,0x32, + 0x85,0xcc,0xff,0xc4,0xe5,0xdc,0xb9,0x73,0x73,0x07,0xce,0xe5,0x26,0x8a,0x97,0xac, + 0x0a,0x80,0x37,0x0a,0x50,0x10,0xfb,0x1f,0x1d,0x59,0x24,0xf9,0xbc,0x26,0xdf,0xfd, + 0x7b,0xdb,0x2f,0x45,0x8d,0xa4,0xdf,0x6e,0x8b,0x29,0x6a,0x42,0x83,0x61,0x69,0x74, + 0x33,0x52,0xe6,0xe3,0x84,0xb8,0x92,0xbe,0x5d,0x40,0x6e,0x76,0x2c,0x33,0xdc,0xd0, + 0x75,0x3d,0xd2,0xd0,0x62,0x15,0xa2,0x03,0xe6,0xf3,0x95,0x95,0xd8,0xaa,0xb6,0xcd, + 0x37,0xcf,0x97,0xa3,0xec,0x66,0xd3,0xba,0x93,0xf8,0x22,0xb4,0x2a,0xd4,0xd7,0xd7, + 0x16,0x13,0x95,0xc9,0xf9,0xaa,0x07,0x7a,0xbf,0x55,0x77,0x6a,0xbc,0x99,0x36,0xfa, + 0x22,0xdf,0xda,0x5a,0xd4,0x2e,0x0a,0x8a,0xc9,0x72,0x00,0x34,0x64,0x37,0xf3,0x93, + 0x78,0xad,0x79,0x67,0xfd,0x79,0x67,0x3b,0x35,0xbf,0x3e,0x91,0xbe,0x94,0x46,0x1b, + 0xc8,0xdd,0xc0,0xc1,0x12,0xee,0xe6,0xa9,0x97,0xe5,0x2b,0x24,0xf5,0xac,0xdc,0x14, + 0x4b,0x42,0x0f,0x43,0xf5,0x65,0x54,0x57,0x98,0xd1,0x85,0xd6,0x15,0xd5,0x88,0xb4, + 0x57,0x6b,0xf8,0x34,0xbc,0x6b,0xe0,0x51,0x31,0x79,0x45,0x9d,0x34,0x3b,0x15,0xdc, + 0x07,0x5c,0xd8,0x29,0xdf,0xa1,0xd7,0xce,0xfd,0x15,0xea,0x73,0x86,0x5f,0x63,0x51, + 0x50,0xde,0x7f,0x8a,0xe4,0xd5,0x78,0x52,0x47,0x39,0xff,0x52,0xbb,0x4b,0x35,0xf4, + 0xb9,0xe1,0x01,0xcf,0x81,0x60,0xea,0xff,0x5e,0xf8,0xc0,0x11,0x7a,0x77,0x43,0xd3, + 0xb4,0x5e,0xf0,0x92,0x83,0xbd,0x1a,0x03,0x5b,0x01,0x61,0xe2,0x01,0xd3,0xee,0xca, + 0x61,0x37,0x0c,0x70,0xc8,0x76,0x00,0x6e,0xc5,0x35,0x00,0xac,0x00,0x4e,0xdc,0xf2, + 0xff,0x4e,0x5d,0x2d,0x62,0xc4,0xfc,0x4f,0x4c,0xe4,0xce,0xfd,0xc1,0xdc,0x1f,0x1c, + 0x98,0x3b,0x77,0x19,0x29,0x00,0x52,0x01,0x48,0xa7,0x07,0x99,0x06,0x20,0xe9,0x97, + 0xcf,0xe7,0x9b,0xa2,0x46,0x42,0xd4,0x12,0xb3,0x23,0x64,0xc7,0x4f,0x18,0x65,0x71, + 0x31,0x2c,0x65,0x4b,0x9d,0xce,0x42,0xc4,0x30,0x1b,0x99,0xc4,0x50,0xab,0xa6,0x45, + 0x8c,0x91,0xe1,0xc4,0xfc,0x1c,0x2a,0x9a,0xbf,0x89,0xa3,0xf3,0xa8,0x84,0x71,0x0a, + 0x60,0x91,0x3d,0x8b,0xf4,0x7a,0xa6,0x92,0x58,0x5d,0x93,0x0c,0x00,0x40,0x24,0x78, + 0x2d,0x93,0xe9,0xb0,0x68,0x6e,0xc4,0x6b,0xb4,0x81,0xab,0x1b,0x95,0x95,0x84,0xc4, + 0xcf,0xb0,0xd6,0xd7,0xd7,0x1b,0x85,0xc2,0x5a,0x46,0x5b,0xc0,0xad,0x92,0xe4,0x05, + 0xb7,0x4f,0x66,0x32,0x5a,0x66,0x41,0x1b,0x36,0xa2,0x83,0x16,0xec,0x2c,0xe9,0x5d, + 0x71,0x5a,0x94,0x19,0x9f,0x70,0x79,0x57,0xcf,0x5a,0x03,0x00,0xf0,0xe7,0x26,0x31, + 0xb0,0x93,0x5e,0x6f,0x66,0x5e,0x01,0x98,0x7a,0xa3,0xa0,0x65,0x3a,0xab,0xdc,0x85, + 0xe8,0x8c,0xa2,0x67,0xc6,0xe0,0x15,0x75,0xb7,0x8c,0x1d,0xaa,0x82,0xa0,0xaa,0x85, + 0x56,0xca,0xe4,0x88,0xbc,0xeb,0x9f,0xb1,0x8b,0x91,0x3f,0x58,0x8e,0xba,0x22,0x46, + 0x49,0x18,0x67,0xdb,0x59,0xd1,0xa3,0x24,0x92,0xce,0xcc,0xa7,0xa0,0x43,0x00,0xee, + 0x3f,0xb6,0x23,0x9f,0xa7,0x23,0x98,0x0a,0x3f,0x5b,0x63,0xf0,0x16,0x75,0xfb,0x06, + 0x86,0x3d,0xcf,0xc2,0xaa,0x67,0x38,0x83,0x02,0xbc,0x4a,0x62,0x00,0xcf,0x5b,0x35, + 0x00,0xdc,0x15,0xf0,0x5f,0x5f,0xad,0x4e,0x80,0x6a,0x0e,0x99,0xff,0x4b,0xc5,0x6f, + 0xe5,0xce,0x1d,0x98,0xab,0xce,0xcd,0xff,0x01,0x52,0x00,0x56,0x04,0xb0,0xeb,0xb5, + 0x00,0x04,0x69,0xff,0xeb,0x46,0x56,0x97,0x5f,0xec,0x2c,0x89,0x21,0x2a,0xdf,0x14, + 0x95,0x11,0x9f,0x6c,0x11,0x3e,0x5b,0x2c,0x5d,0xd8,0x69,0x0b,0x42,0x8a,0x2b,0xff, + 0x4b,0xda,0x9a,0x6e,0xb4,0x2b,0x29,0x4b,0xc1,0x94,0xd2,0xc5,0x58,0xc4,0x68,0x27, + 0x88,0x0b,0xb0,0x8c,0x3c,0x00,0x21,0x3a,0x67,0xb0,0x15,0xd6,0x78,0xbb,0x80,0x83, + 0xea,0xeb,0x62,0x16,0x9f,0x19,0x89,0xe8,0xe2,0x43,0x8f,0x0c,0x3b,0x7e,0xfb,0xf2, + 0x4e,0x0d,0xef,0x05,0xf9,0x19,0x9d,0xc2,0xb6,0xce,0x28,0x00,0xb3,0xbd,0xdd,0x6e, + 0x37,0xda,0x3d,0xc9,0xf8,0xb4,0xda,0xfb,0x83,0xeb,0xe8,0xb5,0xb5,0x99,0xfa,0x26, + 0x77,0xa4,0xcd,0x79,0xf9,0xf2,0xe9,0x06,0x31,0xc5,0x62,0xdb,0x46,0x59,0xbc,0x1b, + 0x73,0xa6,0x4f,0x5b,0xe1,0xa6,0x7d,0xda,0xcc,0x35,0x70,0x5f,0xf4,0x06,0x5f,0xff, + 0x8f,0xfb,0x65,0x12,0x9b,0x5c,0xec,0xb5,0xa2,0xae,0x2d,0x49,0x7a,0xfe,0x6f,0xaa, + 0x03,0x37,0x8c,0xf2,0x1c,0x77,0x7d,0x71,0xa6,0x99,0xdf,0x92,0xae,0x59,0xef,0x17, + 0xde,0x51,0xa7,0xcd,0xb7,0x27,0xd3,0x54,0x58,0x8f,0x1a,0xe9,0xcb,0xab,0x1f,0xf4, + 0x88,0x29,0x7a,0xdb,0xb4,0x1b,0x09,0x29,0xef,0xc0,0x79,0x75,0xf4,0x02,0xdd,0x5a, + 0x68,0x57,0x01,0xc2,0x76,0x2b,0xa0,0xd5,0x08,0x78,0xff,0x95,0x5b,0xfe,0x6b,0x79, + 0xea,0xea,0x10,0x49,0xe1,0xe0,0xdf,0x85,0xcb,0xe7,0xe6,0x48,0x45,0x15,0xd5,0x00, + 0x90,0x03,0x80,0xe5,0xff,0xab,0x48,0xfe,0x9f,0x8e,0x3f,0x6b,0xb7,0x00,0xf4,0xcd, + 0x02,0x4a,0x37,0x16,0x96,0xb1,0x35,0x15,0xa4,0x49,0x52,0xe2,0x08,0x55,0xbf,0x6c, + 0x51,0xbe,0xc1,0x30,0xa7,0x36,0xf8,0x71,0x22,0x9a,0xb8,0x95,0xad,0x31,0xdc,0x30, + 0x1a,0x55,0x66,0xeb,0xdd,0x8a,0x6e,0x66,0xe6,0x2d,0xd1,0xac,0x2d,0x2c,0xa1,0xca, + 0x39,0xb3,0xf1,0x02,0xe3,0x8a,0x90,0x21,0x0b,0x48,0x06,0x02,0x77,0x00,0xc6,0x04, + 0xd2,0x7c,0xe8,0x41,0x5e,0xe2,0xee,0x5b,0xf4,0x74,0x56,0x8d,0x67,0x8c,0x98,0xad, + 0x00,0x78,0x3f,0x43,0x2f,0x92,0x5a,0x13,0x7a,0x3e,0x5b,0xb2,0x66,0x52,0x7d,0xd6, + 0xfe,0xc3,0xba,0x14,0xbd,0x21,0x53,0x2b,0x0e,0x4a,0x02,0x39,0x4b,0x8b,0x92,0xec, + 0x6a,0xbf,0xae,0x84,0x38,0xbb,0x72,0xab,0x53,0x28,0x0b,0x77,0x43,0x92,0x30,0x94, + 0xf3,0xcb,0xdc,0xc8,0x74,0x85,0xeb,0x40,0x7f,0x14,0xfc,0xba,0x78,0x43,0x5b,0x3e, + 0x4b,0xb2,0x14,0x7a,0xb7,0x52,0xc6,0x0b,0xe6,0x9a,0x98,0x76,0x89,0xcc,0xbf,0x3b, + 0xc0,0xc2,0xae,0xf9,0xbd,0x57,0xc3,0xb6,0x3d,0x75,0x24,0x8c,0x1e,0xe3,0x87,0xb3, + 0xf1,0x54,0x37,0x3f,0xd7,0x25,0x77,0x8c,0xbb,0xe7,0x07,0x84,0xa9,0x35,0xb9,0xfa, + 0x01,0x9b,0x3e,0x4c,0x8b,0x34,0x93,0x36,0xec,0xec,0x8d,0x5e,0x38,0xcc,0x6e,0xdc, + 0x0d,0x5b,0xb8,0xad,0x00,0x56,0x08,0xe0,0x79,0x52,0x03,0x40,0xf2,0x7f,0xcb,0x3b, + 0xa6,0xae,0x0e,0x8b,0x24,0xf8,0x3f,0x81,0xac,0x3f,0xaa,0x38,0xe3,0x68,0xd5,0xb9, + 0xdc,0xe5,0x22,0x15,0x00,0x78,0x36,0xa0,0xff,0x9f,0x1e,0xc6,0x37,0x5f,0x32,0x00, + 0x88,0xef,0x00,0x60,0x23,0x2f,0x92,0x26,0x2a,0xc1,0xfe,0xf3,0x6e,0xfa,0xf0,0x4e, + 0x41,0xe8,0xa4,0x8b,0x43,0xf4,0xa8,0xc4,0xd6,0x84,0x40,0x7a,0x32,0x8b,0x3c,0x82, + 0x2a,0x89,0xce,0x65,0x49,0xfb,0x3c,0xbd,0x16,0xdb,0xb4,0x50,0xd2,0x48,0x50,0x5d, + 0xd2,0x49,0xb6,0x7f,0x10,0x7a,0x6c,0xcd,0x6c,0xa1,0xbd,0x4c,0x56,0x12,0xb5,0xcc, + 0xd2,0x69,0x46,0x01,0x2c,0x0d,0x6c,0xdc,0x03,0x50,0x31,0xed,0xca,0x12,0x7f,0xfb, + 0xfc,0xb2,0xab,0xda,0x99,0xe5,0x18,0xf1,0xc6,0xfa,0x27,0x0c,0x14,0x0d,0x27,0x73, + 0xa3,0x6f,0xb3,0x7d,0x6f,0x4a,0x6d,0x67,0x0c,0x18,0xfe,0x82,0xb2,0x99,0x02,0x29, + 0xa3,0x81,0x73,0xa7,0x79,0xf7,0x7f,0xd3,0xf0,0xcb,0x66,0x18,0xe0,0x10,0xee,0xa6, + 0x42,0x7b,0xae,0x7d,0xa5,0x05,0xd3,0x91,0x5d,0xaa,0xf6,0x4f,0xa5,0xe6,0xb9,0x4b, + 0x52,0x95,0x7f,0x26,0x83,0x80,0xef,0xc6,0xe3,0x56,0xfe,0x3d,0xbf,0x83,0x0b,0x39, + 0xd0,0x6e,0x3f,0x0d,0xb5,0x6d,0x4a,0x45,0xb9,0x11,0x00,0x1c,0x02,0xb8,0xf5,0x94, + 0xdd,0x06,0xf0,0xc8,0x2d,0xb7,0xfc,0xc5,0xd5,0xa9,0x00,0xa8,0xd5,0x64,0x34,0x74, + 0xe9,0x42,0x0e,0x99,0xff,0x49,0xdc,0xb2,0x33,0x89,0x14,0xc0,0xe5,0x62,0x31,0x95, + 0x22,0x01,0x80,0xa7,0xbd,0x0a,0x40,0x3f,0x1d,0x10,0x2f,0x14,0x86,0xc8,0xcd,0xe7, + 0xef,0xab,0x5f,0x8a,0xda,0x84,0x19,0x4b,0x64,0x65,0x29,0xaa,0x5c,0x83,0xe1,0x39, + 0x63,0x5b,0x2c,0x52,0xc8,0xfc,0xaf,0x1b,0xe6,0xa4,0xe4,0x90,0xe2,0x55,0xbd,0x51, + 0xa9,0x4e,0x56,0x49,0xfb,0x7c,0x84,0x0b,0x98,0x33,0x0e,0x00,0x1e,0x00,0x8c,0x0c, + 0x59,0xc2,0x87,0xab,0xe5,0xe3,0x55,0xb0,0x24,0x67,0xf4,0x65,0x54,0xd3,0xc0,0x6d, + 0x0d,0x0b,0x05,0xdc,0x0a,0xe8,0x6d,0x43,0xdb,0x5b,0x0c,0x5b,0x4a,0xd5,0x4c,0x6c, + 0x2d,0xca,0x82,0x25,0x92,0xae,0x35,0x98,0x92,0x35,0x1c,0xa3,0xe8,0xff,0x4b,0x42, + 0x0f,0x21,0xd3,0x6e,0xb6,0xe7,0x97,0x2d,0x0c,0x2a,0xff,0xc3,0x6d,0xf9,0x18,0x50, + 0x9c,0x42,0x6d,0x59,0xee,0x3f,0xbf,0x90,0x31,0xb0,0xc2,0x91,0x70,0x8b,0x5b,0xa7, + 0xa6,0x4d,0x2b,0x5b,0x03,0xe7,0x84,0xd7,0x5d,0x4a,0xd0,0x13,0xb4,0x1d,0xf7,0xec, + 0x79,0xd8,0xa9,0xbf,0xd3,0xed,0x89,0x5e,0xd7,0xa0,0xd9,0x30,0xbb,0x19,0x37,0x13, + 0x91,0x8f,0x28,0x7a,0x2d,0x09,0x4e,0xd5,0xc4,0xa9,0x03,0x84,0x9d,0x46,0x40,0xec, + 0x00,0x3c,0x7c,0x3b,0x09,0x01,0x7e,0xe1,0x3d,0x53,0x57,0x03,0xfd,0x0c,0x31,0xff, + 0xb9,0x03,0x48,0xfc,0x2b,0x95,0x47,0x91,0x02,0xa8,0x1e,0x38,0x77,0xc1,0x75,0x00, + 0xdc,0x51,0x80,0xfa,0x0e,0x03,0x54,0x2a,0x38,0x4d,0xd4,0xdc,0x1e,0xfc,0xfa,0x73, + 0x17,0x47,0x16,0xb7,0x16,0x65,0x7d,0xc0,0xd8,0x52,0x10,0xd7,0x4c,0x4d,0xb0,0x4d, + 0x4d,0x75,0xa7,0x6c,0xd4,0x7d,0xc4,0x74,0x22,0x82,0x14,0x40,0x35,0x8f,0x8a,0xe2, + 0xc2,0x36,0x37,0xaa,0xd5,0x26,0x53,0x65,0xed,0xa0,0x4a,0xf5,0x22,0xaa,0x54,0x07, + 0xe8,0x24,0x2f,0x92,0x8a,0x44,0x2a,0x44,0x01,0x20,0x25,0x66,0x45,0x1a,0xdc,0x69, + 0x48,0x46,0xf7,0x7f,0x12,0xa2,0x39,0xb3,0x16,0x43,0x55,0x95,0x91,0x4d,0xfe,0xfe, + 0xf9,0x0d,0x00,0x56,0x68,0x9f,0xcd,0x2e,0x48,0x46,0x57,0x52,0x25,0x03,0x80,0x19, + 0x31,0x9f,0xce,0xc5,0x83,0xca,0xbf,0x66,0xb7,0x52,0xf6,0x1e,0x00,0x10,0xe7,0xfe, + 0x8a,0xb7,0x1d,0x47,0xff,0x06,0x1e,0x17,0x4d,0xe4,0x38,0x95,0x02,0x18,0x76,0x83, + 0x6b,0x6c,0xb8,0x9e,0xd2,0x04,0x9c,0x00,0xb3,0xce,0x00,0x15,0xd6,0x63,0x84,0x9c, + 0x92,0x69,0x5a,0x45,0x78,0x9e,0xbe,0x53,0x05,0xa1,0x0e,0x40,0xba,0x2a,0xdd,0xdf, + 0xc0,0x89,0x0b,0x38,0x31,0x00,0xa7,0x11,0xf0,0x79,0xd2,0x06,0x88,0x6a,0x00,0x3f, + 0xc1,0xdf,0xfa,0x7d,0x21,0x83,0xdc,0xff,0x4b,0xa8,0xf6,0x8f,0x3c,0xe6,0x47,0x97, + 0x5b,0xcb,0xcb,0xf9,0xdf,0xad,0xce,0xe5,0xac,0x00,0x40,0xd7,0x6b,0x01,0x0c,0x50, + 0x05,0xb0,0xbc,0x69,0xed,0xb4,0x38,0xe4,0x9c,0x5f,0x8a,0x9a,0x99,0x59,0x44,0xbe, + 0xb3,0xd8,0x45,0x9d,0x35,0x3b,0x21,0x73,0x5b,0x0c,0x12,0x34,0x0d,0xd3,0x30,0x7c, + 0x4b,0x4b,0x11,0x2b,0x00,0x54,0x03,0xa8,0xad,0x2e,0x45,0xb8,0xcd,0x33,0xc9,0x88, + 0x24,0xf1,0x4d,0x13,0x07,0xc9,0x08,0x36,0x3e,0x5f,0x71,0xa4,0x9d,0xc7,0x75,0xa6, + 0xe5,0xc4,0x62,0xa6,0xbd,0x4e,0xb7,0x02,0xaa,0x89,0x7d,0x9f,0x31,0x65,0xc2,0xe8, + 0x2c,0x2e,0x2c,0x89,0xce,0x95,0xef,0x00,0x60,0x99,0x46,0xb6,0x43,0xc6,0xd7,0x09, + 0x30,0x00,0x98,0x91,0x45,0x75,0x85,0x76,0x79,0x87,0x6f,0xb9,0x8d,0x0c,0xaa,0xc7, + 0xb0,0x43,0x25,0x1b,0x03,0x8a,0x55,0xa8,0x45,0x6b,0xdc,0x5f,0xc1,0xfd,0x57,0xcd, + 0x7d,0xa8,0x39,0xbd,0xff,0x90,0x63,0xcc,0xa9,0x9a,0xbd,0xd0,0x61,0x37,0xcc,0xfa, + 0xe2,0xb3,0xac,0x00,0x3b,0x99,0x3a,0x5e,0xfa,0x00,0xdb,0x06,0x40,0x47,0xec,0x3d, + 0x15,0xc1,0xb4,0xfe,0xb3,0x29,0x82,0xb4,0xef,0xc0,0x19,0x7c,0xca,0x25,0xf1,0xf4, + 0x92,0x5b,0x05,0xb0,0xf3,0x80,0x89,0x02,0x78,0xdb,0x55,0xa9,0x00,0x54,0x3e,0x9b, + 0x3a,0x83,0xcc,0xff,0xdc,0x7c,0xbe,0xd2,0xc2,0x2c,0xe7,0x49,0x05,0x20,0x74,0xc6, + 0x6a,0x01,0xa4,0x73,0x80,0x7b,0x87,0x00,0x49,0x1a,0x79,0x76,0xed,0xb4,0x38,0x00, + 0x90,0xef,0x00,0x60,0xc3,0x0b,0x6b,0x8d,0xb2,0x50,0x10,0xb8,0x06,0xc3,0x84,0xa1, + 0x89,0xe3,0x58,0xe0,0x7e,0xe8,0x3d,0x84,0x2c,0x67,0x6a,0x93,0xd5,0xc9,0x65,0x49, + 0xc4,0x8c,0x69,0x79,0x5f,0x41,0xf2,0x8f,0x7c,0x84,0x91,0x40,0xe3,0xd5,0x88,0x1c, + 0x30,0x0b,0x93,0x24,0xd2,0xb0,0x85,0xf3,0x80,0xe8,0x42,0xbf,0x59,0xd9,0x6f,0x05, + 0x50,0x34,0xd7,0x16,0x0a,0x0d,0xb1,0x0b,0x84,0x9f,0xcb,0x5c,0xea,0xe8,0xb8,0x1b, + 0x84,0x24,0xa7,0x47,0x32,0x00,0x98,0xbe,0x58,0xb1,0x06,0x00,0xe4,0x96,0x1d,0x38, + 0x19,0x27,0x8b,0x1d,0x2a,0x6d,0x46,0xa8,0x50,0xb1,0xad,0x94,0x59,0x63,0xa9,0x51, + 0x17,0x14,0x53,0xd3,0xf0,0xcb,0x14,0x1f,0x88,0xd2,0xdd,0x94,0x24,0x7b,0xb5,0x6e, + 0xb7,0xd3,0xbd,0x2b,0x6e,0xb4,0x81,0xa7,0x84,0x9a,0xaa,0xb8,0xbb,0xf5,0xff,0xf0, + 0xb4,0xe7,0xed,0xf3,0xb6,0xde,0x4d,0xfa,0xa7,0x25,0x9e,0xdb,0x03,0x25,0xfb,0xd4, + 0x00,0xc4,0xb4,0x42,0xb0,0xfe,0x8d,0xbb,0x9d,0x8f,0x5d,0xf9,0x77,0x42,0x80,0x48, + 0xfe,0xff,0xf4,0x6a,0x8c,0x02,0xa2,0xce,0x25,0x91,0xfb,0x7f,0xf9,0xdc,0xdc,0x64, + 0x7e,0xb9,0x95,0xb8,0x27,0x41,0x14,0xc0,0x81,0x8f,0x5f,0xb8,0x74,0xe6,0x29,0xd7, + 0x01,0x08,0x38,0x0a,0x18,0xbe,0xf9,0x32,0x6b,0xda,0xf4,0x1b,0x00,0xcc,0x8c,0x2c, + 0x35,0x22,0x75,0x71,0xe2,0x09,0xa6,0xd8,0xa5,0x1b,0x11,0xdc,0x44,0xcf,0x29,0x09, + 0x24,0xfe,0xc3,0x3d,0x8c,0x45,0xa9,0x62,0x64,0x71,0x7e,0x0e,0xee,0xa2,0xc7,0x35, + 0x46,0xd1,0xa2,0x3d,0x54,0x1e,0xc2,0x03,0x80,0xd5,0x37,0xf9,0x6e,0x68,0x3e,0xb3, + 0x6a,0xf0,0xe4,0x8d,0x0c,0x49,0x37,0x5a,0x41,0x0a,0x60,0x9b,0x49,0x03,0x90,0x75, + 0x37,0xdc,0x13,0x21,0xa3,0xd1,0x3e,0x5d,0xde,0x11,0xbb,0x2a,0xfa,0x75,0x25,0xce, + 0x9a,0xed,0xed,0x88,0x28,0x65,0xb2,0xba,0x4d,0xd7,0xce,0xdc,0x10,0xdb,0x0a,0x07, + 0x4d,0x53,0xb6,0x32,0x89,0x67,0x46,0x7a,0x3a,0x54,0x63,0x11,0x13,0x1f,0x99,0xd8, + 0x93,0x7b,0xf0,0x69,0x11,0x64,0x1c,0xb5,0xbd,0xed,0xf0,0x74,0xd8,0x0b,0xcb,0xd1, + 0x32,0xee,0x39,0xec,0xb3,0x9e,0x91,0x0f,0x3b,0x2d,0x03,0x5e,0x98,0x8f,0x91,0x65, + 0x57,0xd8,0x3d,0xe3,0x1e,0xe6,0x1e,0x8e,0x47,0xc0,0x37,0x0e,0x3a,0xb5,0x00,0x6f, + 0xa0,0xd1,0xe9,0x69,0x7b,0xba,0xc2,0x69,0xae,0x27,0x90,0xab,0x13,0x58,0x05,0x70, + 0xec,0xd8,0x51,0xe4,0x00,0x1c,0xad,0xf3,0xf7,0x7e,0x1f,0x50,0x27,0x90,0xfb,0x5f, + 0x44,0xb5,0x7f,0x24,0xfe,0xf7,0x24,0xb6,0xb6,0x48,0x2e,0xfd,0xdc,0x39,0xa7,0x02, + 0xd0,0xb5,0x5b,0x00,0x82,0x54,0x00,0xf0,0x00,0x60,0x48,0xf9,0xd3,0x35,0x61,0x6b, + 0x17,0x3e,0xb5,0xe9,0xa4,0x6e,0xba,0x3d,0xf5,0x19,0xca,0xb4,0x64,0x17,0x0d,0x8d, + 0x8c,0x7b,0xc3,0x17,0x16,0xa3,0x67,0x61,0x49,0x6b,0x7a,0x6b,0x7e,0x72,0xf9,0xac, + 0x38,0xac,0x05,0x1d,0x01,0x9c,0x1c,0xf1,0x69,0xf8,0x0e,0x38,0x3e,0x5f,0xa9,0x65, + 0x74,0x70,0xb6,0x41,0x7e,0xe5,0xc5,0x55,0xa4,0x00,0x68,0xe9,0x34,0xf7,0x96,0xc7, + 0x2e,0x90,0x32,0x74,0x5d,0x7f,0x5c,0x32,0x52,0x91,0x5f,0x76,0x55,0x4d,0x8d,0xc8, + 0xa7,0x28,0x12,0x35,0x53,0xda,0x19,0x89,0x49,0x98,0xba,0x61,0xd0,0x34,0xe5,0xa1, + 0xfa,0xb2,0x74,0x0c,0x28,0x46,0xa1,0xe6,0x54,0x5d,0xa6,0x98,0xd4,0xbd,0xe6,0xfe, + 0xda,0x1c,0x0e,0x87,0x69,0x59,0x62,0xec,0xb4,0x13,0x12,0x70,0x84,0x98,0x6a,0xe7, + 0x77,0x17,0x67,0xf2,0x71,0xbc,0x66,0x7f,0xb7,0x0a,0x4f,0x8d,0x29,0x3c,0x2d,0x67, + 0x76,0x9a,0x56,0x26,0xdc,0x0f,0xde,0xd7,0x54,0x2f,0xa5,0xf0,0x38,0xbd,0x80,0xf5, + 0x95,0xa7,0x00,0x9e,0x27,0x4d,0x00,0xf7,0xff,0xd2,0xf7,0x09,0xf7,0x72,0xef,0xec, + 0x14,0xa3,0x67,0x2e,0x5d,0xc8,0xcd,0xfd,0x6e,0xbe,0xb5,0xb2,0xb5,0x15,0x8b,0x9d, + 0x45,0x0a,0x60,0x12,0x55,0x00,0x2e,0x84,0xbc,0x51,0xc0,0xa8,0x08,0x40,0xaf,0x2a, + 0x40,0x2b,0x82,0x07,0x00,0x9b,0x11,0x87,0x9c,0xf1,0xa9,0x4d,0x77,0x23,0x9b,0x78, + 0xb0,0x2e,0x71,0x34,0x6f,0xa6,0x89,0x3a,0xb1,0xb3,0xda,0x59,0xd2,0xb9,0x34,0x36, + 0x54,0x50,0x85,0xde,0x3c,0x2c,0xa1,0x11,0x6d,0x72,0x3e,0x9f,0x58,0x5c,0x38,0xcd, + 0x59,0x1a,0x7a,0x74,0x11,0x77,0x00,0xb0,0x7e,0x19,0x08,0x7e,0xc4,0xb3,0xc8,0xcf, + 0x20,0x69,0x00,0x5b,0x9d,0xb5,0x19,0xa6,0x15,0xb0,0x7c,0x26,0xe0,0x36,0x82,0x11, + 0x35,0x0d,0xac,0x2a,0x45,0xf9,0xf7,0x13,0x9a,0x98,0x4a,0x46,0x42,0x13,0xeb,0x8c, + 0xfe,0x03,0x80,0x3d,0xce,0x4b,0xed,0xc0,0xcd,0x71,0x76,0x4a,0x97,0xd8,0x4a,0x49, + 0x4f,0x53,0x92,0x51,0x91,0x62,0x12,0x0a,0x49,0x73,0x17,0xa3,0x22,0x4a,0x39,0x19, + 0xa6,0x0c,0xbe,0x37,0x92,0x0f,0x1d,0x82,0xe3,0xad,0xba,0x23,0xf0,0xd3,0xde,0x4a, + 0xf4,0x42,0xae,0xdf,0xee,0x55,0x0a,0xc2,0xec,0x47,0xda,0x03,0x60,0xaa,0x15,0x4c, + 0x2e,0x11,0xbd,0xc2,0xac,0xb7,0x51,0xc4,0x78,0x98,0x96,0xfd,0xf0,0x34,0x1d,0x01, + 0x38,0xe5,0x46,0x00,0xae,0xc6,0x5c,0xc0,0x7a,0x0a,0x57,0xff,0xcf,0xe1,0x76,0xac, + 0xb3,0x5b,0xb5,0x5a,0x2d,0xb6,0x95,0x40,0x15,0x80,0x73,0xb9,0x0b,0x5e,0x04,0x10, + 0xe7,0x00,0x05,0xe9,0x06,0x98,0xb7,0x86,0xd3,0x0c,0x32,0xe4,0x1c,0x21,0xdd,0x50, + 0x65,0x05,0x9a,0x35,0x3b,0xf1,0xe1,0x48,0x56,0xb4,0xd0,0x4d,0xd5,0xe8,0x67,0x5f, + 0x13,0x46,0x02,0x57,0x00,0xc4,0x2e,0xb0,0x94,0x36,0x22,0x89,0x2f,0xd2,0x4e,0xb2, + 0xc1,0x8a,0x1a,0xce,0x03,0x32,0x13,0xf3,0x56,0xb6,0xd1,0xea,0xda,0x4c,0xdd,0xa4, + 0x86,0x1d,0x6a,0x44,0x83,0x6e,0x24,0x08,0x49,0xdd,0xe7,0x62,0xf9,0x4d,0xaf,0xd8, + 0x9a,0xda,0x54,0xc5,0xe9,0x02,0xa7,0xa4,0x03,0x80,0x35,0x48,0x1e,0x14,0x92,0xff, + 0xde,0xcd,0xf6,0xfd,0xc1,0x03,0x80,0xf5,0x4b,0xe9,0x4a,0x9a,0x9b,0xa8,0x36,0x27, + 0x1b,0x37,0x69,0xaf,0xb9,0xbf,0x16,0x9f,0x38,0xe4,0xb5,0xaf,0x31,0x42,0xee,0xd5, + 0xed,0xd9,0x66,0x01,0xce,0x63,0x67,0xeb,0xeb,0x7c,0xa2,0x0e,0x15,0x13,0x70,0x27, + 0xff,0xa5,0xe4,0xdd,0xfd,0xc8,0xbc,0x9d,0xa6,0xdd,0x0b,0x6f,0x93,0xd3,0x9c,0x0b, + 0x41,0x1d,0x2f,0x56,0x10,0xb3,0x96,0x02,0xb8,0x13,0x55,0x00,0x9e,0x27,0xf2,0x7f, + 0x35,0x1a,0x00,0x1a,0xa9,0x54,0xe8,0xc2,0xe5,0x39,0x24,0x2a,0x89,0x58,0x6d,0x31, + 0xbb,0x58,0x8b,0x9d,0x5d,0xa9,0xcc,0x57,0xad,0x16,0x80,0xcf,0x92,0x08,0xe0,0xd3, + 0x5e,0x0d,0xa0,0x67,0x25,0x60,0xd2,0x6f,0x52,0x2c,0xbf,0x01,0xc0,0x1a,0x3e,0x13, + 0x79,0xd0,0x66,0x27,0xaa,0xaf,0x49,0x2c,0xb4,0x3a,0xa5,0xf5,0x0b,0x4d,0x47,0x23, + 0xc3,0x93,0x79,0xd2,0x1b,0x8d,0xab,0xd6,0x52,0x01,0x73,0x6b,0x18,0x7f,0xc9,0x00, + 0x60,0xc1,0xdb,0xa1,0xbb,0x05,0x92,0x07,0x94,0x47,0x0a,0x20,0xc3,0x45,0xb5,0x0a, + 0xfb,0x99,0x07,0x34,0xa6,0xfb,0x4c,0x7b,0x52,0xf6,0xd9,0x4b,0x5e,0xf5,0x59,0x41, + 0x36,0x00,0x58,0x01,0xd5,0xdc,0x64,0xcd,0xf6,0x83,0x4a,0xe4,0x01,0xc3,0x9e,0xa6, + 0x8c,0x6f,0x49,0xa0,0x06,0x00,0xab,0xe2,0x3c,0x5f,0xc9,0xe8,0xea,0xcd,0x81,0x07, + 0x45,0x91,0xf3,0xca,0x43,0x61,0x46,0x6c,0x5d,0x0f,0x80,0xd1,0x00,0x4c,0x3c,0xc0, + 0x8b,0xdf,0xd1,0x06,0xdc,0x5e,0xdd,0xf3,0x07,0x66,0x29,0xcd,0xe1,0xba,0xee,0x8e, + 0xe0,0xd2,0x3b,0x65,0xf5,0x85,0xf5,0xbd,0x1b,0xef,0xf7,0x76,0x49,0x8d,0x1a,0x12, + 0xa6,0xbe,0x76,0xf6,0x1a,0xde,0x38,0x64,0x3b,0x00,0x77,0x3f,0x7c,0x0c,0x29,0x80, + 0xa3,0x5f,0x94,0xdd,0xce,0x3d,0x52,0x88,0x22,0xf9,0xcf,0x1d,0x98,0xac,0xac,0x9c, + 0xad,0x65,0x17,0x47,0x17,0xb3,0xb5,0xd8,0x0a,0x76,0x00,0x70,0x05,0xc0,0x1b,0x05, + 0x2c,0x5e,0x0a,0x30,0x17,0xd0,0x9c,0x89,0x87,0xd3,0x93,0xd4,0xa6,0x63,0xf2,0x15, + 0xd2,0x6d,0x9f,0x63,0xa2,0xc7,0xb4,0x98,0x30,0x3a,0xd9,0x85,0x99,0x3a,0x9b,0xc5, + 0xd3,0x6c,0x06,0x68,0x29,0x8e,0x99,0xad,0xbc,0xed,0xd6,0x32,0x07,0x44,0x39,0xcc, + 0x21,0xd3,0x19,0xb2,0x84,0x3b,0x82,0x01,0xf2,0x50,0xa2,0x8d,0xf2,0x10,0x4e,0x04, + 0x5c,0xc6,0x89,0x80,0xeb,0x4c,0x7b,0x5b,0x66,0xd7,0xf5,0xd9,0x92,0x30,0xe4,0x72, + 0x37,0xe2,0x73,0xb1,0x48,0x83,0x86,0x70,0xb8,0x25,0x65,0xd2,0xef,0x8e,0x8b,0x09, + 0x43,0x78,0x00,0xb0,0x04,0x19,0x00,0x28,0x78,0x1e,0xa4,0x3c,0x1c,0x3c,0x61,0x8d, + 0x3a,0xd0,0x6b,0xd4,0x91,0x78,0xa1,0x29,0x93,0xfe,0xa9,0xa9,0xbd,0xe7,0xfe,0x5a, + 0x3c,0xf8,0x11,0xaf,0x1a,0xcf,0x39,0xfc,0xd4,0xac,0xdc,0xb3,0x6e,0xf5,0xde,0x4b, + 0xf3,0xb3,0xeb,0xf4,0xae,0xb0,0xd3,0xb2,0xee,0x05,0x10,0xc3,0x5e,0x1d,0x21,0xec, + 0xfd,0xa3,0x5e,0xc3,0xae,0xc0,0xdb,0xff,0xe8,0x74,0xe3,0x69,0x4e,0x4d,0xb8,0xbd, + 0x01,0x3c,0x0d,0xe0,0x84,0x2d,0xa9,0x8e,0x80,0x77,0x93,0x0a,0xc0,0xd5,0x18,0x03, + 0x24,0x13,0x4d,0x5d,0x9a,0xc8,0xe1,0xb6,0xb2,0x58,0x76,0xb1,0x73,0x5f,0xa7,0x93, + 0x8d,0x6d,0xb5,0x2a,0xf3,0x07,0xce,0x5d,0xb8,0x64,0x0d,0x02,0xf0,0x4c,0x9a,0x0e, + 0x01,0xf6,0x72,0x00,0x7c,0xbd,0x69,0x3d,0x93,0xc9,0xac,0xb2,0x4f,0xf2,0xe7,0x37, + 0xef,0x16,0x5d,0xec,0x5a,0x66,0xad,0xb6,0x26,0xd6,0x29,0xea,0xfd,0x23,0x53,0x29, + 0x33,0x33,0x69,0x17,0x6b,0xa6,0xb8,0x51,0xe9,0x48,0x21,0x77,0x54,0xfd,0x41,0xa6, + 0x20,0xe3,0xf7,0x13,0x59,0xcf,0xdb,0xf9,0xc6,0x19,0x76,0x38,0x90,0x66,0x6d,0x37, + 0x16,0x2d,0xde,0xc2,0xfd,0x0e,0x33,0x9d,0xd5,0x4c,0x07,0x5d,0x25,0xf7,0x8a,0xc9, + 0x5c,0x79,0xb2,0x93,0x42,0x86,0x5e,0xcc,0x79,0x76,0x1a,0x7e,0x77,0x7c,0x51,0x54, + 0x16,0x99,0xed,0xe5,0xc4,0xa2,0xa4,0x73,0xf1,0x54,0x5b,0xd8,0xae,0xf3,0xc4,0xc7, + 0xd6,0xc9,0xf2,0x0a,0xae,0x88,0x14,0xaa,0x74,0x0c,0x38,0x4f,0xa1,0x46,0x7d,0xef, + 0xfa,0x2e,0xa7,0xfd,0x10,0xce,0xe6,0x61,0xc7,0xce,0xba,0x63,0x77,0xd3,0x75,0xfb, + 0x69,0xf6,0x9d,0xf7,0xc9,0x79,0x15,0xcd,0x31,0x63,0xcc,0xa9,0x6f,0x19,0xa8,0x6e, + 0x3d,0xb3,0xdc,0x97,0xcc,0x9b,0x30,0x6d,0xfa,0x85,0xd5,0x99,0xe6,0xc2,0x0d,0x3c, + 0x33,0xa8,0xe5,0x00,0xe0,0x0a,0xc0,0xd1,0xff,0x70,0x15,0x12,0x00,0x6a,0xd1,0x33, + 0xa1,0xcb,0xe7,0x90,0xfb,0x7f,0xb6,0xb6,0xd8,0x59,0x45,0xf7,0x74,0x31,0xbb,0xb5, + 0x52,0x99,0xac,0x9e,0x9b,0xb8,0x60,0xa5,0x00,0x5a,0x5d,0x40,0x6c,0x07,0xa0,0x67, + 0x00,0xb0,0x48,0xac,0xe9,0xc5,0xb2,0xe0,0xfc,0x0d,0x0a,0xd5,0x0e,0x54,0xca,0x44, + 0x70,0xdb,0x1a,0x3f,0xec,0x45,0x33,0x80,0x81,0x2e,0x69,0x91,0x4a,0x85,0x24,0x24, + 0xb1,0xa5,0x91,0x1a,0x5e,0xc4,0x1e,0xc6,0x5f,0x9c,0x55,0xc7,0x6f,0xc8,0x02,0x29, + 0x13,0x23,0x6d,0x27,0x0d,0x60,0x81,0xcd,0x03,0x6a,0xb6,0x76,0xd1,0xa0,0x9d,0x34, + 0xf5,0xf5,0xb2,0x69,0xe0,0x1a,0xcf,0x55,0x49,0xf8,0x90,0xc4,0x36,0xb2,0x78,0xde, + 0x2e,0x6d,0x46,0x1c,0x8f,0xa7,0x0f,0x42,0xfd,0x80,0x64,0x12,0xcb,0x14,0x6a,0x63, + 0xa2,0x58,0x2c,0x5e,0x42,0x8f,0x62,0xcd,0x6f,0x63,0xfb,0x90,0xfb,0x6b,0x41,0x77, + 0x01,0xf6,0x9c,0x00,0xd7,0x96,0x7b,0xf5,0x7a,0xaa,0x7d,0x9e,0xf6,0xea,0xc3,0x8e, + 0x20,0x52,0x4b,0xcc,0x3a,0xff,0x68,0x39,0x67,0x5e,0x7d,0x34,0x00,0x2f,0xe1,0xec, + 0x17,0xcc,0xc2,0x4c,0x8a,0x91,0xd5,0x02,0x40,0x6a,0x00,0xa7,0x4e,0x9d,0x42,0xf2, + 0x7f,0xec,0xd8,0xd1,0xab,0xd1,0x03,0xa0,0x15,0x3d,0x53,0xfc,0x16,0xaa,0xfe,0x63, + 0xf3,0xbf,0x9a,0x59,0x58,0x5d,0xbd,0x2f,0x5b,0x3b,0xbb,0x8c,0x1c,0x80,0xcb,0x4e, + 0x0a,0xc0,0x33,0x6e,0x0d,0x40,0xa1,0xda,0x00,0x3c,0xdc,0x8f,0xa1,0x11,0xcb,0x9a, + 0x0a,0xd2,0x34,0x30,0x5e,0x83,0x61,0xbc,0xdd,0x4e,0xc8,0xda,0x14,0x83,0x4c,0xa0, + 0x57,0x35,0x12,0x95,0x56,0x4d,0x9c,0xdf,0x73,0xc5,0x5d,0x22,0x89,0x3b,0xc9,0x77, + 0x24,0xb3,0x6a,0x44,0x9e,0x1e,0xa4,0xc0,0xcd,0x99,0x85,0xaa,0x33,0x1c,0x48,0x9b, + 0x19,0x77,0x50,0x9d,0x1f,0xbc,0x50,0xe3,0x51,0x89,0x6a,0x1d,0x49,0xe6,0xfe,0x3e, + 0x21,0x49,0xea,0xf7,0x46,0x62,0x1a,0xac,0x84,0x09,0x99,0x1d,0x51,0xb3,0xd6,0xda, + 0x92,0x55,0xa8,0xec,0xb9,0x8f,0x36,0xe5,0xb3,0xb7,0x11,0x7c,0x3a,0x32,0x0f,0xce, + 0xfd,0xd3,0xb4,0x8f,0x3d,0x1b,0xf6,0x9e,0xb4,0x11,0xa6,0x05,0xcf,0xa9,0xd7,0xdb, + 0xa6,0x7f,0x96,0x75,0x0f,0x9c,0x6f,0x39,0x41,0xa6,0x64,0x57,0x3e,0x66,0xc0,0x2c, + 0xfb,0x46,0xbe,0x20,0xed,0x59,0xd8,0x87,0x30,0x4b,0x1a,0x03,0x37,0xec,0x34,0x20, + 0x24,0xff,0x87,0xac,0x26,0xc0,0xa3,0xdf,0xdd,0xdc,0xc5,0xed,0xee,0xc3,0x64,0x2a, + 0x54,0x3c,0x77,0x60,0x7e,0xf9,0x9e,0x18,0x12,0x7f,0x3c,0x5a,0xc5,0x6a,0xa7,0x86, + 0x23,0x80,0x73,0xe7,0x26,0x2e,0xb9,0x0e,0x80,0x55,0x03,0x70,0x67,0x03,0xe5,0xeb, + 0x7e,0xce,0xa4,0x58,0x7a,0x16,0x4f,0x8a,0xb7,0xcb,0x49,0x31,0x29,0x28,0x0b,0xdd, + 0x8d,0x68,0x78,0xd8,0x8b,0x3a,0xdf,0xf9,0xdf,0x67,0xd4,0x1b,0x86,0x94,0xd9,0xc1, + 0xc5,0x7a,0x9b,0xef,0x68,0xe6,0x19,0x40,0x2c,0x6a,0x67,0x65,0xa2,0x36,0xe0,0x20, + 0xb4,0x15,0x83,0xf4,0x39,0xce,0x7b,0xc3,0x81,0x38,0x87,0x6b,0x04,0xe9,0x49,0xc0, + 0x92,0x8e,0xac,0x0e,0xbd,0xb8,0x9b,0xe9,0xf8,0x02,0x22,0xe9,0x62,0xdf,0xd2,0xf1, + 0x00,0xa0,0x33,0x03,0x4c,0x84,0x6a,0x21,0xe4,0x12,0x45,0x8d,0x6c,0x05,0xcf,0x8b, + 0x24,0x9b,0xa7,0xa5,0x0f,0xea,0xe4,0x7e,0x75,0x9a,0x38,0x1c,0x1e,0x77,0x84,0x99, + 0x97,0xb7,0x59,0x4e,0x8c,0xf9,0xcf,0xd3,0x8c,0x35,0xe6,0x4d,0xb9,0x5f,0x7b,0x3f, + 0xaf,0x07,0x7a,0xc9,0xbb,0xbb,0x61,0x4a,0xc7,0x6c,0x50,0x31,0xc6,0x0d,0x7a,0x73, + 0x48,0xfc,0x67,0x67,0x89,0x03,0x80,0x73,0x80,0x6e,0xff,0xf3,0xfd,0x4f,0x00,0x6c, + 0xce,0x45,0x43,0xc5,0xdc,0x5c,0x7e,0x39,0x51,0x5b,0x44,0xe2,0x8f,0x58,0xe8,0x2c, + 0xd6,0x12,0xcb,0x79,0x2b,0x05,0x80,0x44,0x00,0xc6,0x48,0x1b,0xa0,0xa7,0x00,0xfc, + 0x4c,0x5a,0x6a,0x64,0xd4,0x8e,0xb7,0xef,0xb1,0xe0,0x52,0x03,0x80,0x45,0x47,0x3a, + 0xd6,0x8c,0x72,0x5c,0xfa,0x5f,0x34,0x40,0x39,0x88,0x6f,0xb7,0x2b,0xb2,0xe9,0x28, + 0xbd,0x0c,0x20,0x32,0x00,0xd8,0xaa,0x38,0x10,0xdd,0xa0,0x89,0x2f,0xa5,0x84,0x31, + 0x8a,0x63,0x80,0x79,0x9c,0x06,0x80,0xf3,0x80,0xbc,0x2d,0x49,0x86,0x1d,0xef,0x43, + 0xba,0xa1,0x55,0xb6,0x16,0x0b,0x91,0x9d,0x41,0xad,0x71,0x40,0x24,0x09,0x43,0x43, + 0x26,0xee,0xc5,0x38,0x23,0xb6,0xdc,0xf6,0x41,0x18,0xa9,0xb1,0x6b,0x76,0x96,0xa5, + 0x99,0xc4,0x01,0x50,0x97,0x72,0xfb,0x53,0x03,0x60,0x12,0x80,0x7c,0x65,0x35,0xd0, + 0x22,0x9e,0x40,0x5b,0xef,0xc6,0xd9,0xc0,0xc0,0xac,0xb0,0xa8,0xcf,0xb6,0x25,0x95, + 0x02,0x67,0x5d,0x3a,0xf8,0x60,0x2f,0xb2,0x81,0x9f,0xe8,0xed,0x06,0xf2,0xff,0xc3, + 0x56,0x05,0xe0,0xf9,0xbb,0xbf,0xff,0xd8,0xed,0x7f,0xb7,0xff,0x3d,0x00,0x8d,0x09, + 0x1c,0xfe,0xaf,0x4e,0x2e,0x6f,0xd5,0x3a,0x99,0x85,0x6f,0x68,0x6b,0xda,0x42,0xa6, + 0x53,0xdb,0x5a,0x21,0x29,0x00,0x9e,0x03,0x80,0x07,0x02,0xb6,0x47,0x02,0xf1,0xe4, + 0x9f,0xbf,0x5b,0x49,0x64,0x4d,0x63,0xbb,0xbc,0xf9,0x2c,0x9e,0x77,0x9f,0x32,0xb3, + 0x96,0x08,0xb3,0xb2,0xe0,0x37,0xeb,0x0d,0xcb,0x68,0xd9,0x1e,0xd7,0x92,0x5d,0x79, + 0xdd,0x8d,0x5a,0xe1,0xc4,0x37,0x6b,0xc8,0x12,0xee,0x00,0x76,0x06,0x4c,0x7c,0x8b, + 0x67,0x8d,0x1a,0x19,0x0d,0xc0,0x1a,0x0f,0x88,0xc9,0x03,0x1a,0x34,0xac,0x85,0x07, + 0xd1,0x48,0xc8,0xc6,0x51,0xd8,0x27,0xd6,0x65,0x03,0x80,0xd9,0x99,0x1b,0x83,0x2a, + 0x1c,0x3e,0xb3,0x63,0x8c,0x64,0x12,0x17,0xc4,0x0a,0x55,0x20,0xd4,0xcc,0x53,0x03, + 0x5e,0x2b,0x29,0x07,0x39,0xa1,0xa3,0x9f,0x32,0x61,0xe5,0x5d,0xf5,0x5e,0xfa,0x81, + 0xdf,0x90,0x5c,0xae,0x59,0xf5,0xc0,0x56,0x14,0x58,0x55,0x40,0x27,0x23,0xda,0xc2, + 0x3f,0x8b,0xfb,0x01,0x90,0x3f,0x1c,0x02,0x9c,0x3d,0x44,0x1c,0x00,0x1c,0x01,0xfc, + 0xf2,0xdf,0xed,0x7f,0x02,0xa0,0x59,0x8c,0x5e,0xba,0x90,0xc3,0x19,0xec,0xd9,0xd5, + 0xcc,0x5a,0xa1,0x50,0x40,0x0a,0x60,0x75,0x31,0x96,0x58,0xb6,0x22,0x80,0xa4,0x13, + 0x50,0xd7,0x4e,0x02,0xa0,0x1a,0x01,0xa5,0x4e,0x40,0xd7,0x1e,0x4e,0x53,0x36,0x8f, + 0x9c,0x43,0x93,0xfd,0xf3,0x29,0x25,0x5e,0xb6,0xd8,0x84,0x19,0x93,0x25,0x94,0x4a, + 0xca,0xb0,0x84,0xbc,0xb9,0x82,0xb3,0xd1,0xf9,0x95,0x3d,0xe5,0x81,0x07,0x00,0xb3, + 0x44,0x8d,0x9f,0x82,0x68,0xd0,0x82,0x98,0xd6,0x8c,0x44,0x75,0x7e,0x7e,0x72,0x19, + 0x0f,0x3a,0xd0,0x60,0x14,0xc0,0xf6,0x67,0x07,0xdb,0x14,0x19,0x95,0x8c,0x8c,0x4a, + 0xa4,0x3a,0xd7,0x6c,0x5f,0xfd,0x00,0xc9,0xd8,0xe3,0x56,0x1e,0xa4,0x24,0x73,0xc3, + 0xa3,0xe9,0xdc,0x2e,0xe7,0x68,0xc8,0x2b,0x1f,0x86,0x41,0xbe,0xcb,0xf2,0x56,0xe7, + 0x27,0xc4,0x9e,0x04,0xfc,0xc6,0x7c,0x4e,0x49,0xf7,0x9b,0xaa,0x7d,0x10,0x8e,0x4f, + 0x87,0xc7,0xd9,0x0a,0xbe,0x44,0x56,0xf9,0xa0,0x9b,0x4f,0x40,0x9e,0x16,0xf7,0x59, + 0xc9,0x02,0x4c,0xfb,0xc0,0xac,0xe4,0x97,0x40,0xe0,0x65,0x37,0x88,0xeb,0x3f,0x4e, + 0xed,0x72,0xc3,0xea,0x0b,0x8c,0x1c,0x80,0x3b,0x4f,0x7d,0x04,0x47,0x00,0xbf,0xbc, + 0xff,0x09,0x80,0x7a,0x28,0x75,0xe9,0xc2,0x39,0x3c,0x56,0xc6,0xe2,0xaa,0xa6,0x15, + 0x96,0x0a,0x4b,0x6b,0xc8,0x01,0xc8,0x6e,0xb5,0xf2,0xf3,0x73,0x97,0x89,0x03,0x10, + 0x75,0x23,0x00,0x8e,0x03,0xe0,0x57,0x03,0x18,0x23,0xd6,0x74,0x49,0x9c,0xd0,0x93, + 0xbf,0xf7,0xee,0x9f,0x1f,0x5e,0xb6,0x18,0x69,0x50,0x16,0x73,0x0a,0x82,0xa5,0x8a, + 0xe4,0x8c,0x58,0x62,0x51,0x6b,0xf0,0xd2,0xed,0x75,0x01,0x2c,0x15,0x0a,0xcb,0x09, + 0x5a,0xd4,0x1c,0x06,0x9f,0x82,0xbe,0x3b,0xac,0xb7,0xec,0xe1,0x40,0xd0,0x25,0xa8, + 0xd3,0x69,0xcd,0xda,0x60,0x79,0x40,0x78,0x1c,0x85,0x84,0x3b,0x2f,0x92,0xab,0x03, + 0x54,0xe7,0xea,0xf9,0x5e,0xb8,0x26,0x59,0xba,0x69,0xbf,0xf1,0xbd,0x09,0x75,0x9f, + 0x01,0xc0,0x32,0xdb,0x62,0xda,0x8e,0xb7,0x65,0xf6,0x9d,0xa3,0x02,0xf8,0x5c,0x82, + 0xf8,0x8c,0x86,0xed,0x7f,0xe4,0x71,0xbf,0x46,0x3e,0x6a,0x63,0x4d,0xe6,0x93,0x8d, + 0x9a,0xd8,0x7b,0x14,0x80,0x8c,0x00,0xe0,0x2b,0x7e,0x81,0xe4,0x52,0x74,0xe6,0x65, + 0xc2,0x3f,0xc8,0x36,0xd9,0xac,0x42,0x37,0xd6,0x47,0xe2,0xfc,0xde,0x52,0x1b,0x61, + 0x5b,0x05,0xb8,0x81,0x80,0xb0,0xe3,0x00,0xe0,0x16,0x80,0xfd,0x4f,0x00,0x8c,0x9c, + 0x49,0x85,0x26,0xce,0x91,0x71,0x2c,0x33,0xdf,0x28,0x2c,0x2d,0xb5,0xf1,0x44,0x9a, + 0xc8,0x01,0x58,0x59,0x9e,0xb7,0x9b,0x00,0xf1,0x4c,0x60,0x9e,0x02,0xa0,0x67,0x04, + 0xe7,0x49,0xb7,0xb5,0x21,0x9f,0x79,0xa4,0xc9,0xad,0x75,0x1e,0xde,0x0b,0x79,0x48, + 0x4a,0xdc,0xa8,0xbb,0xf5,0x1c,0xc9,0x29,0x12,0x72,0x0a,0x82,0xb5,0xcf,0x87,0x46, + 0x16,0x65,0xcd,0xda,0x94,0xfc,0x5b,0x89,0x2f,0x92,0x51,0xb5,0x07,0xef,0xbd,0x93, + 0x6a,0x44,0x2a,0x64,0xee,0x81,0xb3,0xd9,0x4c,0x21,0xc2,0xe4,0x01,0x75,0x06,0xcb, + 0x03,0xb2,0x86,0xfa,0x47,0xd2,0x48,0xd2,0xf7,0x55,0x72,0xb1,0xec,0x6b,0xe5,0x8f, + 0x73,0x2d,0x55,0x7b,0x05,0xdf,0x6b,0x2b,0xab,0xdb,0x20,0x2d,0xbb,0x52,0xbb,0x4f, + 0x36,0x11,0xa2,0xb7,0xed,0x26,0x75,0xe7,0xf0,0x93,0x1c,0x0e,0x9f,0xb1,0x1f,0x1f, + 0x2e,0x60,0xf9,0x17,0x15,0xaa,0xbb,0x21,0x6b,0x13,0x4d,0xef,0x10,0x39,0x9a,0x03, + 0x5e,0x2c,0x09,0xc7,0x37,0x38,0x21,0xf6,0xf5,0xfe,0x05,0xb7,0x9f,0xf7,0xed,0x45, + 0xa9,0x67,0x72,0x03,0xbd,0x57,0x7a,0x16,0x01,0x26,0x57,0x88,0x6e,0x4f,0xa0,0x16, + 0xa2,0x46,0x09,0x22,0xe1,0xfe,0x71,0xbc,0xa7,0x71,0xdc,0x0f,0x08,0xd7,0xfb,0xd1, + 0x3b,0xec,0x0e,0xa0,0x2f,0x91,0x2a,0x9b,0x25,0x11,0x00,0xe4,0x00,0xfc,0xdd,0xb1, + 0x3f,0xec,0x51,0x00,0x76,0x87,0x1e,0x3a,0x73,0x69,0xe2,0x5c,0xb5,0x82,0x6e,0x7f, + 0x46,0x2b,0xb4,0x2f,0xb6,0x91,0x02,0xd0,0x70,0x04,0xc0,0xca,0x01,0x74,0x1c,0x00, + 0xa7,0x11,0xd0,0x0d,0x01,0xc8,0xea,0x00,0xe8,0xe6,0x2f,0x4b,0xbd,0xe9,0xa9,0x29, + 0x6b,0x1a,0x79,0xc3,0x20,0x4f,0x6b,0x2e,0x79,0xc3,0x20,0xf3,0xc8,0xab,0xb2,0x42, + 0xea,0xa5,0xe8,0x56,0xf1,0x8c,0x72,0xa4,0x4d,0x91,0x59,0x2a,0x98,0xfd,0x8f,0xea, + 0x19,0x6b,0x7a,0x0f,0xb6,0x94,0x79,0x3d,0x80,0xf0,0x00,0x60,0x44,0xfe,0x85,0xb1, + 0x28,0x76,0xd1,0x13,0xb5,0xa8,0x37,0xf2,0xd5,0xea,0x64,0xa5,0x75,0x76,0x71,0x61, + 0x29,0x32,0xb2,0xa9,0x7a,0xd6,0xb2,0xf6,0xec,0x00,0xdb,0xc1,0x43,0xfd,0xaf,0xd4, + 0x32,0x6d,0x3c,0x87,0xa9,0x7b,0xb9,0xf0,0x9b,0x4d,0x55,0x9a,0x36,0x4f,0xd2,0x21, + 0xc9,0xd5,0xa5,0x2f,0x2e,0xb9,0xbe,0xaa,0x6c,0x79,0xd9,0x00,0x60,0x78,0x00,0x40, + 0x59,0xb3,0xdd,0x94,0xd5,0x72,0xb7,0xb9,0x69,0x58,0xdb,0xdc,0x74,0x8f,0x07,0xbf, + 0x37,0x54,0x7e,0x5e,0x5f,0xec,0xbb,0xe0,0x11,0x95,0xc5,0x4c,0x22,0xab,0x0c,0x6c, + 0xaa,0xf6,0x31,0x3a,0xe7,0xa4,0x8a,0xf7,0x7f,0x71,0xaf,0x0a,0xe0,0xb8,0x6f,0xfc, + 0x4f,0xf0,0xfe,0xfd,0x9a,0xee,0xb8,0x65,0xdd,0xf7,0x61,0xcf,0x66,0x87,0x9d,0x4a, + 0xfb,0xac,0x97,0xd7,0xef,0xa9,0x00,0xbb,0x0a,0xe0,0xfc,0x1a,0x96,0x56,0x11,0x1c, + 0x23,0x4f,0xfe,0x8f,0x5b,0x95,0x00,0xf7,0x2b,0xcb,0x0d,0xd8,0xc0,0x0e,0xc0,0xa1, + 0x3b,0xef,0x44,0x0a,0xe0,0xf9,0x63,0x7f,0xf7,0x39,0xd9,0xdd,0xdf,0x13,0x66,0x31, + 0x75,0x69,0x62,0x6e,0x7e,0x39,0x51,0xeb,0x2c,0xac,0x2d,0xb5,0xb7,0xdb,0x8d,0x8b, + 0x4b,0xd8,0x01,0xa8,0xe1,0x4e,0x00,0xc4,0x01,0xb0,0x42,0x80,0x63,0x69,0x3a,0x0f, + 0x58,0xee,0x00,0xc4,0x5d,0xc7,0x55,0x28,0x43,0x78,0x22,0xe9,0x1d,0x3c,0x8d,0xbc, + 0xee,0x3c,0x74,0xfc,0xbe,0x5e,0x37,0x65,0xfd,0x7f,0xa7,0x34,0x57,0x5e,0x72,0x23, + 0x89,0x4a,0x4c,0x1c,0xc6,0x2e,0x58,0x4f,0xd1,0xa8,0xbe,0x6a,0xe7,0x23,0x31,0x07, + 0xe3,0x39,0xf7,0xa5,0x4e,0xc3,0x1a,0xaf,0x42,0x38,0x86,0x73,0x83,0x17,0xbb,0x92, + 0x95,0x07,0x34,0x89,0xd3,0x00,0x16,0xda,0xcc,0xac,0x20,0xea,0x40,0x79,0x40,0xd9, + 0x48,0xa5,0x85,0x47,0x15,0x8e,0x94,0xeb,0xf8,0x3a,0x59,0x97,0x4b,0xaf,0x8f,0xd4, + 0x4d,0x24,0x31,0x32,0x05,0x80,0xe4,0x8a,0x5c,0x5c,0xef,0xea,0x92,0xf5,0x4c,0xf3, + 0x71,0x43,0xe2,0xd1,0x4b,0x92,0xfa,0x53,0x46,0x6d,0x88,0xb4,0xdc,0x8a,0x1d,0x86, + 0x90,0x80,0xe2,0x6d,0xeb,0xe2,0xc3,0xd4,0xeb,0x2a,0x9f,0x4b,0x54,0xd2,0x6c,0x85, + 0x2a,0x6a,0x12,0x32,0x53,0xfb,0x8e,0x8e,0x57,0xd3,0xed,0x23,0x35,0x31,0xe2,0xfd, + 0xaf,0xed,0x31,0x06,0x70,0x3c,0xbc,0xc1,0x8d,0xd9,0x23,0xd1,0x00,0x3d,0xd5,0x83, + 0xe8,0xff,0x0b,0x5d,0x79,0x65,0xb5,0x03,0xff,0xfa,0xff,0xac,0xf5,0x71,0x43,0x58, + 0x2c,0x6c,0x7d,0xc7,0xfc,0x80,0x8c,0xff,0x86,0x15,0x0f,0xc0,0xe7,0x61,0x47,0x00, + 0x3f,0xf2,0x91,0xe7,0x9f,0xff,0xfe,0x7f,0x26,0xb9,0xf9,0x7b,0x43,0xcd,0xa5,0x2e, + 0x5d,0x9e,0x9b,0xaf,0x9c,0xcd,0xae,0x22,0xf9,0xdf,0x9e,0x69,0x6c,0x23,0x0f,0x40, + 0xcb,0x2c,0x5a,0x4d,0x00,0x38,0x07,0x28,0xf5,0x54,0xd2,0x76,0x00,0x9e,0xc6,0x8d, + 0x80,0x4e,0x0c,0x80,0xcb,0x50,0x27,0x1a,0x41,0x6b,0xb7,0xce,0xca,0x6a,0xd3,0xd6, + 0x34,0xdd,0xfa,0xfa,0x7a,0xa3,0x7d,0xba,0x81,0xa7,0x92,0x27,0x2f,0xdb,0x8d,0xc6, + 0xf6,0x0c,0x2a,0xe3,0x92,0xc5,0xbd,0x16,0xba,0x9c,0xd9,0x5a,0xde,0x12,0xb7,0x19, + 0x2c,0xfe,0x8f,0xec,0x3f,0x9e,0x5f,0xa0,0x87,0xfc,0x93,0x01,0xc0,0xf0,0x3c,0xd4, + 0xfc,0x11,0xec,0x66,0x20,0xba,0x52,0xd5,0xd0,0x26,0x71,0x23,0x00,0x92,0xde,0x85, + 0x8b,0xb8,0xfd,0xce,0xdd,0xf1,0xe6,0x20,0x71,0xad,0x58,0x64,0x19,0x57,0x22,0xb0, + 0x3a,0x9e,0x69,0x9c,0x26,0x17,0x0b,0x5f,0xb3,0xd3,0xeb,0xb8,0x43,0xbf,0x44,0x01, + 0xe0,0xf9,0x86,0xca,0xe5,0xf5,0x19,0x44,0xc3,0x59,0x1a,0xaf,0xb6,0xbe,0x5e,0xd6, + 0x85,0xc9,0xc9,0x38,0xf9,0xb7,0x0e,0x2b,0x6a,0x2e,0xb6,0xe4,0x99,0x5b,0x78,0x86, + 0xe5,0x7a,0xf9,0x34,0x3a,0x8c,0x19,0xfb,0xbe,0x59,0xff,0x4e,0x6f,0xe3,0x1b,0xb8, + 0xc3,0xf7,0xc2,0x42,0x0a,0x75,0x19,0x4f,0x53,0xa4,0x8b,0x2e,0x20,0xd2,0x23,0x75, + 0x3d,0x72,0xfa,0xf4,0xb6,0xb5,0x05,0xfc,0x77,0x7a,0x66,0x3d,0x52,0xc6,0xd5,0x1c, + 0x2e,0xb9,0x23,0xd8,0xe8,0x4b,0xf2,0x7b,0x80,0xfe,0x8e,0x58,0x62,0xe4,0x64,0xd3, + 0x58,0x4f,0x2f,0x24,0x60,0x3b,0xde,0x6c,0x54,0xde,0x9b,0x2d,0x5c,0x9a,0x1b,0xec, + 0xac,0xe7,0xd5,0x13,0xc6,0xa7,0xed,0x46,0x3a,0x4b,0x62,0xed,0xd7,0x59,0xf7,0x03, + 0x85,0xb5,0x28,0xa5,0x01,0xb0,0x7f,0x1f,0xde,0x20,0xc3,0xfd,0x6c,0x38,0x3f,0xb9, + 0x51,0xff,0x71,0xcb,0x0b,0xb0,0xc4,0x1f,0x37,0x01,0x62,0x0f,0xe0,0x4e,0xe4,0x01, + 0x7c,0xe4,0xfb,0xbf,0xff,0x3f,0x0a,0xf7,0x7e,0xaf,0xa8,0x73,0xa9,0x22,0xaa,0xff, + 0xb7,0x90,0xfc,0x6b,0x85,0x8b,0xdb,0x33,0xeb,0x48,0x28,0x97,0x0a,0x0b,0xab,0xd9, + 0xad,0x44,0x85,0x0c,0x03,0x70,0x29,0x95,0xa2,0xda,0x00,0xac,0x44,0xe0,0x67,0xa9, + 0xc1,0x00,0xa8,0x72,0x8d,0xbc,0x69,0xc7,0xfe,0x8b,0x23,0xbb,0xd7,0x23,0xdb,0x85, + 0xb5,0xb5,0x85,0x85,0x05,0x6d,0xc1,0x42,0xd3,0x16,0x70,0xc0,0x51,0x3a,0x46,0xcd, + 0xb6,0x6b,0xde,0x27,0xf4,0xad,0x0a,0x19,0xa2,0x93,0xeb,0xc4,0x1f,0x0d,0x52,0x18, + 0x52,0xba,0xb6,0x28,0x19,0x68,0x92,0x1a,0x02,0x2c,0x51,0x5e,0x26,0x2d,0x04,0x82, + 0x0a,0xda,0x55,0x11,0x2c,0x91,0x3c,0x20,0xa2,0x00,0x70,0x1a,0x00,0x5d,0xab,0xd8, + 0x19,0xa0,0x6d,0x3b,0xa1,0x57,0x2a,0xa4,0x3d,0x66,0xc1,0x41,0xc3,0x4f,0x7c,0xb1, + 0xca,0xa6,0x64,0x04,0x10,0x3c,0x0b,0xf2,0x0c,0x8e,0xdb,0x2c,0xb8,0x97,0x57,0xc3, + 0x8f,0x35,0x3c,0x0d,0xba,0x98,0x45,0xc0,0xd5,0x6d,0xf0,0x71,0x25,0x47,0x16,0xe5, + 0x03,0x80,0x22,0x65,0xb9,0xa3,0x37,0xda,0x68,0xdb,0x9a,0xb7,0x75,0xfb,0x0e,0xa2, + 0xef,0xca,0x7c,0x2e,0x11,0x56,0xa8,0xa8,0x08,0x48,0x1c,0x2a,0xbb,0x08,0x14,0x34, + 0xfa,0x9c,0xb4,0x42,0xe1,0x62,0x43,0x1f,0xe1,0x2b,0x68,0x7e,0x73,0x1a,0x07,0xe4, + 0x70,0x98,0x88,0xce,0x38,0x2d,0x80,0xe3,0xec,0x7b,0x52,0xe7,0x76,0x85,0x7f,0xdc, + 0x4e,0xb9,0xb3,0xc4,0x7a,0x9c,0x89,0x19,0x8c,0xcf,0xba,0x52,0x3d,0xee,0x1a,0x6a, + 0xd7,0x49,0xa7,0xcc,0xf6,0xac,0xf8,0xc1,0x8b,0x3b,0x58,0x62,0x8f,0x95,0xcc,0xc6, + 0xac,0xbb,0xa3,0x0d,0xa7,0xa6,0x30,0xee,0x38,0xfb,0x8e,0xd5,0xdf,0xc0,0xf2,0x3f, + 0x8e,0x75,0xc0,0xc6,0x2c,0x09,0x01,0xde,0x89,0x1c,0x80,0xe7,0x9f,0xff,0xc8,0x55, + 0x18,0x00,0x28,0x9f,0x0a,0x5d,0xc6,0xfe,0x3f,0xb2,0xff,0x85,0xf6,0x4c,0x03,0xd9, + 0xe8,0x06,0x76,0x00,0x3a,0xb5,0x17,0x71,0x13,0x80,0xd5,0x0d,0xd8,0x52,0x00,0x63, + 0xe9,0xa7,0xdd,0x2a,0x80,0xa8,0x01,0x4a,0xe4,0xe6,0xb7,0x70,0xbc,0x5d,0x18,0xd8, + 0x1d,0x8f,0xd6,0x19,0xc1,0xf3,0xc8,0x67,0x17,0xb3,0xe8,0x49,0x1e,0x35,0xf4,0x40, + 0x64,0xd6,0xda,0xe2,0xc4,0x9e,0x94,0x7b,0x1f,0x32,0x63,0x15,0x6b,0x92,0x10,0x66, + 0x19,0xbf,0x21,0x85,0x58,0x42,0x46,0x26,0x23,0x8c,0x6a,0xd5,0xa4,0x93,0x7b,0x86, + 0xf4,0x15,0x3c,0xf3,0xb5,0x38,0x05,0x41,0xc0,0x01,0xc0,0x38,0xe2,0x31,0x63,0xd1, + 0xee,0x0c,0x4c,0x66,0x05,0xa1,0x64,0x4f,0x0f,0x1e,0x51,0xac,0xe8,0xcb,0x93,0xcb, + 0xcb,0x89,0xad,0x5a,0xcd,0xbe,0x5a,0x8b,0xe4,0xba,0x2d,0x76,0x70,0x9d,0x40,0x2a, + 0x59,0xfa,0xe9,0xc2,0x42,0xa7,0x63,0x5f,0x57,0xbc,0x42,0x0d,0xaf,0xd0,0x41,0xb7, + 0xf4,0xb4,0x18,0xd3,0x93,0x5c,0xbb,0xae,0xde,0xc1,0x53,0x37,0x8b,0x53,0xb7,0x90, + 0x59,0x56,0x96,0x50,0x7d,0xd0,0xbb,0x71,0x78,0x17,0xe4,0x78,0xd0,0x1d,0x6c,0x08, + 0xb9,0x44,0xd6,0x34,0x25,0x33,0xe2,0x00,0x20,0x4d,0x32,0x57,0x73,0xa6,0xb3,0x38, + 0xea,0x6c,0x29,0x8b,0xcf,0x69,0x35,0x53,0xb8,0xb8,0x2e,0x58,0x80,0xf6,0x9e,0x42, + 0x00,0x87,0x5d,0x09,0x1c,0x0f,0xd3,0x4a,0x40,0x68,0xb8,0x67,0x35,0xc3,0x34,0x35, + 0x06,0xcf,0x06,0xab,0x31,0xd8,0xc6,0xc0,0x0d,0xdb,0x0b,0x40,0xff,0xb1,0x07,0xb0, + 0xd1,0xe3,0xd5,0x7a,0x71,0x96,0xb5,0xd5,0xc6,0x86,0xe3,0x05,0x90,0x18,0x9f,0xad, + 0x1d,0xc8,0x91,0xd8,0x7a,0x6b,0xdc,0x0a,0x00,0x8e,0x63,0xeb,0x3f,0x6d,0x2b,0x00, + 0x6c,0xff,0x7f,0xe3,0x03,0xfc,0x55,0xdd,0x3b,0x2b,0x56,0xfd,0x7f,0x6b,0x31,0xa3, + 0x15,0x90,0xf9,0x5f,0x8f,0xac,0xaf,0x6f,0xe3,0x08,0x40,0xb6,0xb6,0x62,0xe5,0x00, + 0x58,0x93,0x81,0x27,0xbb,0x63,0x5d,0xab,0x06,0x80,0x83,0x80,0x74,0x26,0x90,0x57, + 0x0b,0x28,0x25,0x88,0xfc,0x9f,0x96,0xcd,0x23,0x5b,0x6f,0x14,0x90,0x4f,0x71,0x76, + 0x25,0xf1,0xe2,0x0a,0x45,0xa2,0x86,0xe5,0x44,0x74,0x00,0x3c,0xf7,0x3e,0x3a,0x92, + 0xb5,0x46,0xf1,0xe3,0xa4,0x38,0x90,0x7c,0xe6,0x8c,0x8c,0x26,0x8e,0x80,0xab,0x8e, + 0x78,0x95,0x87,0x49,0xbd,0x95,0x90,0x54,0x11,0x02,0x0f,0x00,0xc6,0x13,0xef,0x18, + 0xb1,0x79,0xac,0x00,0x12,0xb5,0xd5,0x82,0x35,0x2b,0x88,0xb3,0xf3,0x48,0xe0,0x26, + 0xc5,0xaa,0x3e,0x84,0x7c,0x88,0xe5,0xd6,0x0a,0x4b,0x02,0xb9,0x04,0x85,0xd3,0x92, + 0x49,0xfa,0x36,0xcd,0x72,0x7b,0x01,0x67,0x6d,0xf3,0x2b,0xd4,0xf0,0xec,0xa4,0xa2, + 0x4c,0x8b,0x75,0x1b,0xdc,0x72,0x6b,0x4f,0x16,0xc0,0x5d,0x2b,0xd5,0x28,0xb7,0xd7, + 0x3a,0xb5,0x2d,0xf6,0xbe,0x59,0x9b,0x5f,0x59,0x29,0x08,0x71,0x98,0x21,0x1d,0x17, + 0x01,0x21,0x5f,0x93,0x14,0x81,0xd3,0x56,0x11,0x78,0x11,0xaf,0xb9,0xb2,0x82,0x0f, + 0x37,0x81,0xcf,0x09,0x77,0x99,0xe0,0xf4,0x6f,0x73,0x72,0x77,0x97,0xdf,0xe2,0x07, + 0x37,0xc2,0xe3,0xae,0xf5,0x65,0x82,0xff,0x1b,0x9e,0x35,0x1e,0x9f,0x9d,0x66,0x6c, + 0xb6,0x25,0xd9,0x74,0x35,0xdd,0x15,0x5f,0x5b,0x9e,0xa9,0x56,0x7a,0x5b,0x76,0xdd, + 0x85,0x5c,0xd9,0xb6,0xff,0x5b,0xea,0xc3,0x59,0xdf,0xd9,0x88,0xf7,0x9e,0x71,0x20, + 0x36,0xdc,0xbf,0x0d,0x4b,0xf6,0x37,0x1c,0x55,0x80,0xd4,0xd7,0xc6,0x06,0xf6,0xff, + 0x49,0x05,0xe0,0x23,0x1f,0xf9,0x8d,0xcd,0xa9,0x7d,0x27,0x8b,0xe4,0xff,0x1c,0xb1, + 0xff,0xa8,0xfa,0x8f,0xaa,0x63,0x91,0xc8,0x3a,0xaa,0x01,0x68,0x0b,0x38,0x07,0xc0, + 0x0e,0x01,0xe2,0x7e,0xc0,0x6e,0x0c,0x10,0xc7,0x00,0xe2,0x25,0x2f,0x11,0x80,0x1e, + 0x11,0x20,0xa1,0x5b,0xf6,0x5f,0x98,0xd0,0x1b,0xcf,0xd4,0xbb,0xb0,0xb8,0xd5,0x5a, + 0x26,0x33,0xc8,0x2f,0xe7,0x2b,0x95,0x0a,0x7a,0xcd,0x2f,0x23,0x2b,0xb7,0xb8,0x20, + 0x8c,0xd0,0x49,0xcf,0x18,0x94,0x8c,0x64,0xf2,0x38,0x00,0x10,0x31,0x37,0x99,0xb6, + 0xa2,0x40,0x9d,0xc5,0x2a,0xc6,0x42,0x61,0x7d,0x87,0x1f,0x39,0x9c,0xb6,0x2e,0x55, + 0x2b,0xf1,0xe5,0x3d,0x42,0xe2,0x4b,0x76,0x97,0x65,0x6f,0x4c,0x1b,0xd9,0xc2,0x0a, + 0x00,0x55,0x2b,0x56,0x97,0x1a,0x75,0x3a,0x13,0x78,0x29,0x68,0x4e,0xe1,0x81,0x91, + 0xd6,0xfc,0xe4,0x64,0x1e,0x4f,0xc6,0x52,0xb1,0x9e,0xe4,0xdd,0x32,0xaa,0xa4,0xe1, + 0x49,0x7a,0x25,0xce,0xd5,0x7a,0x61,0x35,0xb6,0xd2,0xb2,0x2f,0x2b,0xf9,0xab,0xe0, + 0x8b,0xbb,0x12,0xcb,0xe0,0x09,0x50,0xfa,0x0f,0x6e,0x1c,0x27,0x69,0x3b,0x92,0xc9, + 0x82,0xb0,0xd5,0x5e,0xca,0xd4,0xce,0xe2,0x3b,0xb7,0x4c,0x8e,0x63,0xd9,0x7e,0x90, + 0xf7,0x19,0x21,0x97,0x08,0x4f,0x53,0xb4,0x28,0xe9,0x49,0x80,0xdd,0xff,0x86,0x86, + 0x8b,0x80,0x73,0x7c,0x64,0x53,0x48,0xc9,0xd5,0xf0,0xc0,0x69,0xfc,0x49,0xf9,0x0d, + 0x6a,0x14,0x88,0x2f,0x4f,0x0b,0x02,0x49,0x9c,0xed,0x0d,0x4a,0x03,0x84,0x3d,0xc3, + 0x3e,0x4e,0x2f,0xe6,0xfa,0xea,0xcc,0x9a,0x94,0x84,0x4e,0xd3,0x1e,0x03,0x53,0x0d, + 0x10,0x3e,0xd2,0x8c,0x7b,0x5a,0xc0,0x5e,0x6c,0xdc,0xd6,0x11,0xd8,0xc9,0x1f,0x77, + 0x9d,0x01,0xdb,0xfe,0x5b,0x15,0x00,0xe2,0xb3,0xcc,0x6e,0xcc,0x22,0xf9,0x9f,0xc5, + 0xf2,0xff,0x8f,0x57,0x21,0x1f,0x3c,0x63,0xcb,0x3f,0xb2,0xff,0x4b,0xed,0x48,0x24, + 0x52,0x2e,0x23,0x05,0xd0,0x5e,0xd3,0x56,0x71,0x2f,0x00,0x1c,0x01,0xc0,0x35,0x00, + 0x3b,0x04,0x60,0xc5,0x00,0xbc,0x4c,0x40,0x47,0x01,0x38,0xf6,0xbf,0xa2,0x27,0x48, + 0xc3,0xb5,0xe0,0x4d,0xab,0x3b,0x48,0xfe,0x91,0x43,0x91,0xcf,0x4f,0x5a,0xcc,0x93, + 0x67,0x1e,0x8f,0x3a,0x40,0xdc,0x4e,0xce,0xec,0xe8,0x51,0xb7,0x64,0xce,0x14,0x48, + 0x27,0xfe,0x19,0x2e,0x37,0x2d,0x50,0x00,0x70,0x74,0x67,0xad,0xcd,0x8f,0x1c,0x38, + 0xa5,0x36,0xa9,0x0e,0x70,0x07,0x46,0x12,0x2b,0xf2,0x01,0xc0,0x76,0x1b,0x83,0x8e, + 0x0e,0x23,0xeb,0x3d,0x3f,0x99,0x5f,0x7e,0xd1,0x9e,0x15,0xc4,0xcb,0xd8,0x09,0x9a, + 0x07,0x34,0x61,0xb6,0xf0,0x64,0xe1,0x93,0x14,0xf9,0x79,0x74,0xe5,0x96,0x71,0xab, + 0xa0,0xd8,0x57,0x19,0xc9,0xe8,0x7a,0xa1,0xb3,0xd5,0xca,0xbb,0x57,0xd7,0x5e,0x87, + 0xf4,0x47,0x94,0xb4,0xc6,0x88,0xc3,0x31,0xe1,0x01,0xc0,0xa4,0x69,0x7b,0x58,0xfe, + 0xb1,0x6e,0x41,0x9b,0x66,0x37,0x3e,0x49,0x3e,0x2f,0x0a,0xb7,0x81,0xcc,0xe9,0xa8, + 0x49,0x7a,0x12,0x20,0x47,0x62,0x7b,0x21,0x7b,0x16,0x15,0x81,0x79,0xf6,0x18,0xf1, + 0xb8,0x49,0xa2,0x93,0xb2,0x87,0xce,0x80,0xa5,0xbb,0x69,0x49,0x73,0xe5,0xd6,0x0a, + 0xa6,0x39,0x1a,0x60,0xc3,0xd1,0x08,0x58,0xba,0x39,0xf3,0x8c,0x7f,0x70,0xdb,0xef, + 0xdd,0x3a,0x39,0x5d,0xf5,0x1f,0x77,0x6b,0x0e,0xce,0x3b,0xf7,0xe3,0xb8,0xfb,0x81, + 0xf9,0x4f,0x29,0x08,0x2c,0xf5,0x1b,0x6e,0x38,0xc1,0xaa,0x01,0x58,0x31,0x7f,0xe2, + 0xf4,0x6f,0x7c,0xd2,0xfe,0x4f,0xfe,0xb0,0xfd,0x1f,0x47,0x0a,0x80,0xd8,0xff,0xbb, + 0xf8,0x3b,0xb9,0x0f,0xb4,0x89,0xfc,0x57,0x90,0xfd,0xd7,0x88,0xfd,0xd7,0x91,0x02, + 0x38,0x8d,0x6b,0x00,0x1d,0xac,0xac,0xe7,0xab,0x56,0x12,0xc0,0x53,0x51,0xab,0x23, + 0xc0,0x33,0x4e,0x22,0x10,0x35,0x1e,0x80,0xa7,0x04,0xf2,0x23,0x89,0x44,0x76,0x41, + 0xec,0xac,0x8b,0xe5,0xbf,0x8d,0xe4,0xbf,0x32,0x89,0x8b,0xf5,0x3c,0xa6,0x3a,0x89, + 0xff,0x26,0xf3,0x2d,0xd2,0xb8,0xc7,0x2b,0x0c,0xba,0x85,0x3e,0x82,0xac,0x04,0x6e, + 0x9b,0x66,0xe5,0x58,0x0d,0x30,0xbe,0x76,0xba,0xa1,0x0f,0xaf,0x8f,0x08,0x23,0x07, + 0xd2,0x33,0xe6,0xe4,0x0c,0x22,0xff,0x65,0x61,0x0c,0xf2,0xdd,0x77,0x46,0x0f,0x45, + 0x22,0x43,0x38,0x06,0x88,0x47,0x03,0x58,0x5a,0x67,0xe2,0x75,0x7d,0x86,0x2c,0x75, + 0x28,0x5a,0x43,0x0a,0xce,0xcf,0x4f,0x5a,0xd7,0xc9,0xfe,0x9f,0xb7,0x2e,0x96,0xd0, + 0x5e,0x86,0x64,0xf4,0xf4,0x5a,0x67,0x6b,0x19,0x09,0xe4,0xbc,0x0b,0xe9,0x8d,0x54, + 0xb1,0xba,0x4e,0xf3,0x56,0x43,0xac,0xdb,0xc4,0x87,0x0b,0x2d,0x79,0xda,0xce,0xa6, + 0x19,0x59,0x5a,0x8d,0xb5,0x98,0x6d,0x5b,0xf7,0x0f,0x1f,0x61,0x56,0xe8,0x27,0x75, + 0x00,0x5d,0x50,0xe9,0x9c,0x6e,0x4d,0xec,0x02,0x66,0x57,0x90,0xfb,0x47,0xce,0xac, + 0x6a,0x95,0x01,0x54,0x02,0xb0,0x77,0xc7,0x8f,0xd1,0x1a,0x34,0xc1,0x43,0xca,0xb3, + 0xa7,0xc2,0x94,0x71,0x75,0x23,0x6a,0x76,0x8d,0xda,0xf7,0xc1,0xfe,0xc3,0x06,0x98, + 0xc0,0x6f,0xc4,0xd9,0x32,0xed,0xf6,0x6f,0x78,0x6a,0x81,0xfd,0xc2,0xb5,0xf6,0xce, + 0xee,0xa7,0xbd,0xc8,0xa4,0x65,0xe9,0xad,0xad,0x62,0x7d,0x60,0x45,0xfe,0xed,0xaf, + 0x36,0xec,0x20,0xc0,0xf8,0xc6,0x2c,0x52,0x00,0x1b,0x44,0x01,0x7c,0xec,0x23,0xbf, + 0x73,0x15,0xec,0x7f,0x23,0x14,0x22,0xf6,0xbf,0x46,0xfc,0xff,0x72,0x04,0xc9,0x7f, + 0x39,0xd2,0xd8,0x2e,0x68,0xb8,0x1f,0x30,0x09,0x01,0x5e,0x2e,0xe2,0x91,0x80,0xa2, + 0x4e,0x2b,0x20,0x51,0x00,0x4f,0x13,0xf1,0xa7,0xc2,0x00,0xe4,0x59,0x35,0x63,0x64, + 0x42,0x6f,0x31,0x8d,0xbc,0xb9,0x53,0x8f,0x6c,0x2f,0xd9,0x61,0x64,0x8d,0x74,0x33, + 0xd4,0xd0,0x07,0x6d,0xcb,0xca,0x16,0xdd,0xe4,0x16,0xa7,0xd2,0x6f,0x5b,0x23,0xad, + 0x3c,0x9e,0xca,0x9b,0x0f,0x7c,0x05,0x98,0x2a,0x22,0x64,0x34,0xf8,0xe9,0xbf,0x48, + 0x7b,0x36,0x35,0xce,0x14,0xe9,0x5e,0xb0,0xd0,0x7e,0xcf,0x5e,0x06,0x00,0xe3,0x29, + 0xea,0x0d,0x54,0x71,0x9a,0xac,0x90,0x49,0x01,0x98,0xe0,0x66,0x33,0x16,0x2c,0x6d, + 0xd1,0x18,0x5e,0x20,0x57,0xc8,0x8e,0xb5,0x93,0x60,0x3e,0xfa,0x9c,0x20,0x13,0xfa, + 0x09,0x95,0xa5,0xa6,0x8a,0xd4,0x6b,0xa4,0x5d,0x58,0xd3,0xac,0x05,0xad,0xeb,0x8b, + 0x58,0x24,0x93,0x9b,0x88,0xbe,0x8d,0x38,0xcc,0x6e,0xa9,0xd0,0x46,0xea,0x0a,0x4f, + 0xdd,0x28,0x0e,0xca,0xbd,0xa3,0xaf,0xb7,0x97,0xd6,0xec,0xcd,0xae,0x59,0x07,0xb3, + 0x60,0xef,0xa4,0xcd,0xcc,0xa6,0x82,0xb1,0x14,0xaa,0x64,0xa7,0x2a,0x8e,0xff,0x37, + 0x96,0xec,0x43,0x23,0x85,0x60,0x35,0x86,0xae,0x13,0xce,0x97,0x94,0xb4,0xd1,0xec, + 0xa1,0x09,0xe0,0xfd,0x87,0xac,0xba,0x33,0x91,0xce,0x0d,0x1c,0x0b,0x60,0xed,0x7b, + 0xd0,0x87,0x6b,0xb3,0xe9,0xfa,0xfb,0x74,0xcf,0xcd,0xf8,0x7f,0x69,0x2b,0x88,0x0d, + 0x4b,0x15,0x58,0xb2,0x6d,0xeb,0x04,0xfc,0xfa,0x49,0xf2,0xdb,0xf8,0xc6,0x3f,0xc7, + 0x2a,0x60,0x63,0x7c,0xfc,0x93,0x64,0x21,0xcb,0x07,0x18,0x9f,0x7d,0x60,0x76,0xf6, + 0x63,0xb3,0x77,0x7e,0xf8,0x23,0xfb,0x9f,0xfe,0x83,0x13,0x00,0x43,0xb8,0xff,0x0f, + 0x8e,0xc3,0x2c,0x35,0x70,0x0b,0xb3,0xae,0xa3,0x1a,0x00,0x72,0x00,0x34,0xd2,0x0d, + 0x88,0xb4,0x01,0x5c,0x08,0x59,0x31,0x40,0x32,0x18,0xc8,0x18,0x89,0x02,0x3e,0x6d, + 0x45,0x01,0xe2,0x94,0x0f,0x80,0x1b,0xeb,0x63,0x2b,0xd2,0x68,0x9a,0x39,0xdc,0x1e, + 0x1e,0x76,0xfe,0xda,0xc3,0xed,0x36,0x7e,0x41,0xef,0x8c,0x42,0x4b,0x32,0x42,0x3f, + 0x33,0x00,0x50,0xce,0x88,0x4d,0x2e,0x6f,0x65,0xd7,0xf8,0xad,0xd6,0xf9,0x92,0x27, + 0x52,0xd9,0x8c,0x44,0xf8,0xda,0xff,0x14,0x3b,0xcb,0x44,0xc8,0xac,0xa1,0xfa,0xff, + 0x92,0x38,0x4b,0xd6,0x1e,0xec,0x4f,0xe9,0x80,0x59,0xa8,0xe0,0xb9,0x54,0x57,0xb6, + 0x3a,0x58,0x01,0x50,0xce,0x8d,0xba,0x1c,0x44,0xad,0x24,0x33,0xc3,0xec,0xf5,0xc2, + 0x57,0xab,0x30,0x6c,0x68,0xcb,0x56,0x5f,0x65,0x5e,0x46,0x1b,0xee,0x72,0xc3,0xce, + 0xd5,0x45,0x7f,0xc3,0x11,0x33,0x91,0x88,0x2d,0xcc,0x88,0xba,0x4d,0x54,0x9d,0xa5, + 0x4c,0xa3,0x25,0xed,0x07,0x31,0x15,0xc1,0x9b,0xb4,0x8e,0xc0,0x7e,0xd8,0xef,0xd1, + 0x01,0xa1,0xf7,0xa3,0xe2,0x00,0x60,0x35,0x6b,0x0c,0x38,0x7e,0xec,0x51,0xa3,0x6d, + 0x1d,0xdf,0x70,0xc1,0xd9,0x0e,0x5a,0x48,0x1f,0xad,0x10,0x27,0xe5,0xb4,0x2e,0xec, + 0x78,0x85,0x3f,0xc6,0xc0,0xbc,0xcb,0xaa,0xd3,0x6f,0x8c,0xdb,0x8d,0xe8,0x96,0x85, + 0x75,0x85,0x6d,0x7c,0xda,0x8a,0xb1,0xb9,0xe2,0xe7,0xbc,0x30,0x82,0x69,0x89,0x1f, + 0x79,0x10,0xdf,0x7c,0xc3,0x5a,0x60,0xdc,0xb1,0xd0,0xe3,0x8c,0x4f,0xe1,0xfe,0x6d, + 0x50,0x32,0x6d,0x7f,0x61,0x6f,0xd1,0x6e,0xcf,0x9b,0xf6,0x0e,0xc9,0x72,0x25,0xb0, + 0xc4,0x7f,0x12,0x3d,0xad,0x1d,0x20,0xc3,0x4f,0xaa,0xff,0xe3,0x88,0x0d,0xeb,0x6f, + 0xf6,0xdb,0x1b,0x48,0x01,0x7c,0xe7,0x63,0x77,0x7e,0xec,0xc3,0xfb,0x9f,0xfe,0x83, + 0x5c,0xed,0x89,0x10,0xee,0xff,0x73,0x4f,0x0d,0xc9,0xff,0xcc,0x7a,0xa4,0x6e,0x29, + 0x00,0xe4,0x00,0xac,0x91,0x6e,0x40,0x43,0xf3,0xd5,0xdc,0xe5,0x0b,0x76,0x08,0x20, + 0xd9,0xb5,0xfa,0x02,0x59,0xdd,0x81,0xa9,0x38,0xa0,0x9d,0x0e,0x3c,0x61,0xd6,0xc8, + 0x74,0x1a,0x82,0x89,0xca,0x8c,0xc5,0x49,0xb5,0xc1,0x7e,0x8d,0xdb,0xef,0xc7,0x0a, + 0x33,0x2d,0x92,0xdc,0xb3,0xc9,0x2d,0xef,0x88,0x68,0x89,0xe4,0xf0,0x20,0x49,0xc2, + 0x15,0x00,0xae,0x70,0x26,0xec,0x05,0xe8,0x04,0x04,0xf7,0x3f,0x7e,0x17,0x6f,0x1b, + 0x65,0xa1,0x69,0x01,0x19,0x4b,0xdb,0x66,0x91,0x85,0x52,0x23,0x59,0xdc,0x5f,0x47, + 0xd4,0x58,0x8d,0xa7,0xb9,0x8d,0x97,0x64,0x4f,0x6f,0xb7,0x25,0x7a,0xa1,0x49,0x43, + 0x43,0x15,0xe6,0xca,0xf2,0x4a,0x0c,0xc7,0xb6,0x98,0xe1,0x40,0xaa,0x25,0xf7,0xf8, + 0x58,0x09,0xa4,0x37,0x19,0x67,0xae,0x92,0x7d,0xd1,0x92,0xed,0xc2,0x32,0x76,0x96, + 0x84,0xae,0xb5,0x6a,0x31,0xed,0x2d,0x4b,0x61,0xbb,0xe2,0xd2,0xd8,0x06,0x93,0xb9, + 0x51,0xb2,0x9a,0xed,0x3b,0x92,0xcc,0xcd,0x66,0x95,0xdd,0x26,0xb5,0x13,0xfc,0x3f, + 0x4d,0xcd,0x0a,0x6b,0x1d,0x7e,0x71,0xc4,0xa7,0x08,0xb4,0xbb,0xf6,0xa9,0xb8,0x1b, + 0x4c,0x27,0x73,0x9a,0xa1,0x55,0x90,0x53,0xb3,0xd6,0x10,0xdb,0x0b,0x0a,0x25,0x7a, + 0xb3,0x72,0xb5,0xc9,0xfd,0x60,0xbf,0x3f,0x1e,0xc6,0xf2,0x35,0xee,0x54,0xc6,0x37, + 0x88,0x49,0xa5,0x64,0x72,0xc3,0x09,0xbb,0x09,0x41,0x39,0x2f,0x0a,0x4f,0xd9,0x7f, + 0xc7,0x79,0xb7,0x1d,0x74,0x4a,0x41,0xd0,0x72,0x3e,0xed,0x68,0x1b,0x5e,0x37,0xd8, + 0x1f,0x9d,0x03,0xd8,0xa0,0x35,0xc4,0x86,0xe3,0xfc,0x6f,0x58,0x0e,0x3f,0x11,0x78, + 0xfc,0x1b,0x31,0xfd,0xe3,0x0e,0x0f,0x8c,0x7f,0xe7,0x3b,0xdf,0xf9,0xd8,0xc7,0x3e, + 0xf6,0xe1,0xab,0x31,0xff,0xc7,0xe6,0x81,0x54,0x31,0x47,0xe6,0xca,0x5e,0x28,0x6c, + 0xa3,0xea,0x7f,0xbd,0x6e,0xd6,0xb1,0x02,0x68,0x17,0x70,0x08,0xf0,0x2c,0x69,0x03, + 0xc0,0x0a,0x20,0xe4,0x54,0x01,0x48,0x33,0x00,0x19,0x12,0x10,0x27,0x03,0x32,0x71, + 0xc0,0xa2,0x99,0x4d,0x58,0xd1,0x34,0xae,0x88,0xd2,0xd1,0x34,0xfa,0xed,0x28,0x32, + 0x3b,0x24,0xfd,0x9e,0x8f,0x16,0x1f,0x70,0x17,0x89,0x0f,0xb7,0x2b,0x56,0x20,0x8b, + 0x2b,0xc8,0xe5,0x28,0xbb,0xc9,0x12,0xbf,0xf5,0x09,0xc3,0x94,0xcc,0x7e,0x69,0xa8, + 0xc3,0x94,0xcd,0x8a,0xe2,0x86,0xef,0x05,0x49,0xe2,0x9b,0x1b,0xd8,0xf6,0x2d,0x7c, + 0x8a,0xff,0x0f,0xf1,0x21,0x03,0x29,0xad,0x4a,0x65,0x05,0xf7,0x04,0x60,0x23,0x10, + 0x3b,0x13,0xa5,0x3e,0x6b,0xd3,0xbf,0xd3,0xea,0x27,0x3e,0x3c,0x8c,0xc7,0x2a,0x13, + 0x6d,0x34,0xdd,0x57,0x89,0xde,0x66,0xd1,0xc0,0x75,0x9b,0x6d,0x71,0x2c,0xbe,0x82, + 0x70,0x37,0x4a,0xb5,0xc8,0x4a,0x82,0xc4,0x0a,0x79,0xdf,0x62,0x5e,0x61,0x75,0x05, + 0xb7,0x13,0xe1,0xea,0xa4,0x8c,0xac,0xdd,0x93,0x80,0x3b,0x4a,0xe9,0x34,0x45,0xe9, + 0x96,0xa1,0xe1,0x61,0x93,0xcb,0x82,0x05,0x98,0xaa,0x73,0x2d,0x0b,0xbd,0x6e,0x02, + 0x7b,0x40,0x87,0xc7,0x6d,0x41,0xb4,0xa4,0x16,0x0b,0x19,0x19,0x44,0xeb,0xd0,0x2c, + 0x7a,0x33,0xee,0x35,0xb0,0x3b,0xe6,0x5f,0x78,0x88,0xdf,0x4f,0x8f,0x5b,0x5b,0xdb, + 0xf0,0xc4,0x5b,0x0c,0x2b,0xb0,0x3a,0x81,0x0e,0x37,0xb8,0xff,0xdd,0x8f,0xae,0xde, + 0xb0,0x57,0xb1,0x7c,0x0b,0xeb,0xb0,0x88,0x36,0x70,0xf8,0xf6,0x03,0xdf,0x7e,0x00, + 0x29,0x80,0x07,0x1e,0x40,0xf2,0xff,0x1b,0x57,0x63,0x02,0x70,0xb5,0x7a,0xa6,0x78, + 0x19,0xc9,0x7f,0xac,0x83,0xe4,0x1f,0xd9,0xff,0x3a,0xce,0x23,0xc7,0x6d,0x00,0x24, + 0x0b,0x10,0x27,0x01,0xcc,0xcf,0xe1,0xa1,0x80,0xb0,0x07,0xf0,0x59,0xa2,0x00,0xc6, + 0x9c,0x20,0x80,0xdd,0x21,0x30,0xee,0x36,0x06,0x86,0xf4,0xc5,0x15,0xf9,0xe8,0xaf, + 0x71,0xe1,0x16,0x92,0x52,0x95,0x8d,0xd8,0x21,0x6a,0x7e,0x85,0x39,0xf7,0xbe,0x96, + 0xc8,0x30,0xde,0x89,0xf7,0x66,0x2e,0xf2,0x53,0x59,0xd3,0x95,0x69,0x51,0xbf,0x94, + 0x4a,0x19,0xd5,0x14,0xb2,0x65,0x9b,0xaa,0xc1,0xa4,0x97,0x27,0xf5,0x4c,0xab,0x46, + 0x86,0x2c,0xe1,0x16,0x64,0x03,0xdb,0xfd,0x0a,0x5f,0x89,0x7d,0x8b,0x87,0x03,0xe9, + 0xe0,0xf6,0xb7,0x04,0xf2,0xaa,0x1a,0x65,0x26,0xb8,0xad,0x17,0xf9,0xb5,0xe5,0x1a, + 0x46,0xf8,0x2a,0xae,0xb5,0x71,0x8c,0x2e,0x22,0x73,0x96,0x28,0x11,0xf5,0xb6,0x16, + 0x32,0x6a,0xf2,0xb6,0x8d,0xb6,0x38,0x8e,0x7b,0x42,0x6f,0x9d,0xc5,0xa9,0x92,0x82, + 0x1b,0xee,0x76,0xf0,0x67,0x0e,0x54,0x18,0x05,0xca,0xfd,0x10,0x35,0xb2,0xd8,0xfe, + 0x8b,0x4a,0xc7,0xcb,0x14,0x70,0x37,0x53,0xc2,0xd3,0xa7,0x18,0x9d,0xce,0x9a,0x64, + 0x32,0xd0,0xa9,0xcd,0x14,0x7f,0x19,0xfc,0xdc,0x2f,0x67,0x31,0xe7,0xd8,0xbe,0x6c, + 0x3b,0xec,0x96,0xdb,0xbd,0x71,0xe8,0xd4,0xd1,0x23,0x5f,0xff,0xc4,0x2b,0x77,0xbc, + 0x72,0xdb,0xc9,0xc3,0x2f,0x1f,0xb2,0x7c,0xf4,0xf0,0x38,0x15,0xaa,0x97,0x35,0xd6, + 0xf1,0x5f,0x6f,0x4c,0xdb,0xf9,0x39,0x8e,0x43,0xcf,0xd4,0x17,0xdc,0x76,0x7b,0x89, + 0x07,0xb0,0xc1,0x54,0x30,0x48,0x7d,0xde,0xaa,0x49,0x38,0x9a,0x85,0xc8,0xbb,0xe5, + 0x05,0x8c,0xb3,0xfc,0xf3,0xf1,0x6f,0x63,0x0d,0x80,0x55,0xc0,0x03,0x0f,0xbc,0x05, + 0xc9,0xff,0xe3,0x53,0x57,0x81,0x56,0xaa,0x78,0x79,0x6e,0x92,0xc8,0xff,0xc5,0x75, + 0xcb,0xfe,0x63,0x05,0x80,0xdb,0x00,0x32,0xab,0xd9,0x2d,0x9c,0x05,0x84,0x43,0x00, + 0x97,0xec,0x2a,0x40,0x72,0xac,0x6b,0xd7,0x01,0x9e,0x76,0x7c,0x80,0x92,0xa3,0x02, + 0x52,0x66,0x87,0xc8,0xbf,0x60,0x4d,0x9d,0x16,0x77,0x2e,0x69,0xb8,0x14,0xc3,0x09, + 0x43,0xe8,0xf6,0x6f,0x72,0xed,0x05,0xcd,0xbc,0x77,0x77,0x27,0x8c,0x6c,0x1e,0x27, + 0xd4,0x16,0xf8,0xbc,0x22,0xb3,0x28,0xfa,0xb1,0x54,0x69,0x9c,0x30,0x0c,0x59,0x16, + 0x8a,0xe1,0xa4,0xbf,0x91,0x85,0x2c,0xf9,0x97,0x64,0x20,0x98,0x49,0xca,0xa9,0xa0, + 0x8b,0xad,0xf7,0xe7,0xa7,0x14,0xf0,0x82,0x69,0xcd,0xe8,0x24,0xb6,0x12,0xb5,0xc5, + 0xd5,0xb5,0x8b,0x24,0x06,0xe1,0x9d,0x5f,0x23,0xa5,0x48,0x57,0xa7,0x1a,0x52,0x4a, + 0xe2,0x97,0x56,0x1d,0x5d,0xda,0xbb,0xc2,0xcb,0xe7,0x63,0x6a,0x2b,0xd8,0x14,0xa3, + 0x7a,0x93,0xd0,0xfd,0x09,0x1d,0x41,0x9a,0xd9,0x09,0xde,0xe5,0x90,0xb9,0x42,0x32, + 0xb7,0x84,0x96,0xdb,0x15,0xb9,0xac,0xd1,0xef,0x98,0x2a,0x40,0xd2,0x5c,0xc5,0xf6, + 0x5f,0x68,0x75,0xc5,0x23,0x2a,0xb2,0x57,0xd4,0xfa,0x54,0x34,0xb6,0xd1,0x15,0x12, + 0x67,0x35,0x9f,0x9a,0x62,0x1c,0x25,0x5f,0xff,0x9f,0xf3,0x4e,0xb0,0x4a,0x39,0x45, + 0x24,0xc9,0x12,0xb4,0xe9,0x43,0xc7,0x8e,0xdf,0xe1,0xad,0xf0,0xe0,0x2b,0x27,0xee, + 0x26,0x06,0x16,0x8b,0x97,0x6d,0x7c,0x65,0x48,0xbe,0xb5,0x6a,0xe6,0x96,0x97,0xbe, + 0xb1,0x61,0x59,0xec,0x0d,0xf6,0x85,0xfc,0x64,0x3d,0x37,0xdc,0xf7,0x4e,0x26,0xaf, + 0x67,0xe2,0x2d,0x23,0xef,0x46,0x19,0x36,0x78,0xb1,0xc7,0x82,0x8f,0x9f,0x48,0xf4, + 0x91,0xf0,0x7f,0x7b,0xfc,0x81,0x1f,0x7b,0xe0,0x81,0x8f,0x62,0x07,0xe0,0x1f,0x37, + 0x85,0x8b,0xb4,0x0f,0x68,0x56,0x07,0x80,0x2d,0x9c,0x8a,0x8b,0xe3,0x7f,0xa6,0xb9, + 0x63,0x62,0x05,0xd0,0xd8,0x5e,0x23,0x1d,0x81,0x57,0x2a,0xf9,0xea,0x39,0xab,0x11, + 0xc0,0x0e,0x02,0x22,0x15,0x40,0xb9,0x00,0xf1,0x67,0xf1,0xfc,0xc0,0x24,0x27,0x38, + 0x6a,0x66,0x56,0xa4,0xd1,0x34,0x54,0xe2,0xa8,0x9b,0xe8,0xa9,0xf0,0x96,0x9e,0x38, + 0x9b,0x5d,0x9b,0x11,0xe5,0xb4,0xe5,0x2c,0x56,0x52,0xc6,0x1a,0xed,0x7c,0x05,0xe7, + 0x27,0xb4,0xcb,0xdc,0x44,0x1e,0x4b,0x5d,0xef,0xfe,0x53,0x26,0xcd,0xfa,0x26,0xbd, + 0xd6,0x14,0x7b,0x96,0xa9,0x48,0xfe,0xf5,0x24,0xa5,0x84,0xd2,0x11,0x6d,0x65,0x4b, + 0x96,0xf8,0xea,0xce,0xaa,0xe1,0xb5,0x6e,0xb2,0xd2,0x4f,0x9f,0x88,0xf7,0xe2,0x7e, + 0x18,0x1b,0x36,0xb4,0x6c,0x67,0x71,0x55,0x2b,0x34,0x70,0xf3,0x26,0x7d,0x3d,0x96, + 0x92,0xa5,0x92,0x22,0xae,0xcf,0x95,0x6a,0xfc,0x1d,0x55,0xae,0x71,0x1d,0xbd,0x91, + 0xb0,0xea,0xe8,0x7c,0x65,0xa9,0xca,0x1d,0x81,0xb5,0x85,0x12,0x1e,0x3a,0xb1,0x26, + 0x9b,0xdc,0xc8,0x35,0xc5,0xde,0x7e,0x2b,0x66,0x82,0xb4,0x15,0x0a,0x72,0x58,0xe3, + 0x4e,0x95,0xba,0x26,0xde,0x55,0xf7,0xae,0x67,0xa9,0xab,0x67,0x56,0x62,0xc8,0xa1, + 0x17,0xae,0xbd,0xd9,0x65,0x16,0x77,0x6e,0x5b,0xbc,0x61,0x92,0x36,0x12,0xde,0xfc, + 0x37,0x2d,0x17,0xd0,0xbb,0xec,0xd2,0xa7,0x77,0x2f,0xbc,0x8b,0xf8,0x89,0x59,0x22, + 0x68,0xdf,0x26,0x42,0x76,0xec,0x5e,0x5e,0x73,0xdc,0x71,0xe4,0xd4,0xb4,0x55,0xcd, + 0xb6,0xa5,0x7c,0x5a,0xf2,0xa0,0x05,0xd4,0xfd,0xce,0xf1,0xd6,0xc7,0x9d,0xf5,0xd9, + 0x97,0x0d,0xda,0xc8,0x8f,0xbb,0xee,0xfc,0xb7,0x3d,0x65,0x34,0x4e,0xef,0x74,0x83, + 0x11,0x77,0xee,0x8d,0x2b,0xfc,0x98,0xbf,0xf9,0xf6,0x47,0x91,0x06,0x78,0xcb,0x03, + 0xbf,0xf1,0x3b,0xbf,0x3c,0x75,0x15,0xd0,0x8b,0x64,0x00,0x10,0xdc,0xe1,0xac,0xdd, + 0x40,0xf6,0xdf,0x7c,0xdc,0x34,0x49,0x08,0x60,0xbb,0x5d,0xc0,0x1d,0x81,0xb7,0x56, + 0xf2,0x58,0x01,0x50,0x1e,0x40,0xd7,0x69,0x08,0x24,0xd9,0x80,0xd8,0x05,0x78,0x96, + 0xf4,0x09,0x2a,0x45,0xcb,0x19,0x54,0xff,0x17,0x26,0xeb,0x45,0x25,0xee,0x19,0x6f, + 0xc8,0x00,0xaf,0xe8,0x94,0x4a,0xa4,0xd8,0xe1,0xd1,0x3d,0xf9,0xdb,0xbf,0xe5,0x2d, + 0x5a,0xaa,0x8d,0x24,0xf2,0x95,0x95,0xd8,0x2a,0x49,0x13,0x63,0xb6,0x8c,0x6a,0x00, + 0xec,0x16,0xa9,0x37,0x43,0x4d,0x71,0xba,0x3c,0xdc,0x51,0x6e,0x6a,0xd4,0x6b,0xb0, + 0x28,0x95,0xd2,0x33,0x05,0x92,0xf8,0x2e,0xcc,0x7c,0x69,0xa4,0xa4,0x62,0xed,0xf3, + 0xa0,0x7f,0xb7,0x0b,0x65,0xb4,0x61,0x16,0xd6,0xb4,0x25,0x54,0xa7,0xd2,0x77,0xb8, + 0x94,0xdd,0x85,0xae,0xe2,0xbb,0xb6,0x75,0xca,0x5e,0xa1,0xa7,0xba,0x59,0xd4,0xf4, + 0x56,0x0c,0x77,0xad,0xd9,0xe4,0xef,0xe0,0x3c,0x23,0x51,0xee,0x4b,0x72,0xc4,0xf2, + 0xc6,0x04,0xdd,0x56,0xee,0xb2,0x7b,0x42,0x2f,0xd5,0x91,0x2d,0x67,0x98,0x75,0x96, + 0xd1,0x12,0x7f,0x74,0x8e,0xbc,0x89,0xa7,0x40,0xb4,0x75,0x64,0x81,0xd4,0xff,0x77, + 0xf8,0x48,0x22,0x52,0xa8,0xac,0xa0,0xda,0x17,0x56,0x33,0xca,0xa6,0x6c,0xb4,0x60, + 0xb5,0xc2,0x5c,0x54,0xff,0x6b,0x4f,0x2f,0x83,0xff,0x1f,0x1f,0x1f,0x77,0xe4,0xfb, + 0x63,0x27,0xac,0x7e,0xe4,0xcf,0xbe,0xff,0xb6,0x7b,0xef,0xbd,0xf7,0x13,0xaf,0x58, + 0x1a,0xe0,0xfd,0xb7,0xff,0xff,0xb4,0x5d,0x5d,0x6c,0x1b,0x57,0x76,0xd6,0x56,0x21, + 0xb0,0x46,0x77,0x1d,0xba,0x7d,0x48,0x32,0x74,0x3a,0xe4,0x3e,0x71,0x28,0xaf,0x03, + 0x84,0xae,0x90,0x05,0xd6,0xf6,0x26,0x70,0x01,0xd6,0x09,0x06,0x25,0x87,0xa4,0x4a, + 0x86,0x90,0xf2,0xa0,0x84,0xf1,0xc2,0x09,0x5d,0x06,0xd8,0x20,0x25,0xca,0x32,0x0f, + 0x42,0xe2,0xc2,0x02,0x48,0x20,0x05,0x6c,0x40,0x41,0x81,0x75,0x49,0x79,0x1f,0x2a, + 0x19,0xa0,0x41,0xd9,0x4f,0x8b,0x05,0x96,0x30,0xd0,0xaa,0x04,0x0c,0x3e,0x11,0xf1, + 0xb2,0x61,0x0d,0xd7,0x06,0xf7,0x61,0x1f,0x1a,0x89,0x16,0x07,0xa4,0x7b,0xce,0xb9, + 0x77,0x7e,0x38,0x73,0x65,0xd1,0x8b,0xea,0xcc,0x90,0x73,0x67,0xe6,0xfe,0xcd,0xbd, + 0xf7,0x3b,0xe7,0xdc,0x7f,0x52,0xba,0x59,0x1b,0x9b,0x50,0xfe,0x33,0xd5,0x5c,0xa0, + 0x13,0x70,0x6d,0x9d,0xc9,0xf7,0xc9,0x63,0x3f,0x1f,0xde,0xf6,0x8a,0x54,0x7b,0xaf, + 0x57,0xf4,0xc8,0xe4,0x00,0x80,0x7d,0x6f,0x1a,0xb1,0x1f,0x06,0xea,0x5c,0xf4,0x5d, + 0xbc,0x78,0xf1,0xec,0x0b,0x2f,0xfc,0xa7,0x2b,0x91,0xfe,0x3f,0x48,0x9a,0xf3,0xac, + 0x5d,0xbb,0xbc,0xb4,0x99,0x19,0x35,0x2a,0x34,0x1d,0x77,0x30,0x00,0x15,0xe0,0x08, + 0xeb,0x04,0x5c,0x1d,0x61,0x27,0x20,0xb6,0x01,0xda,0x19,0x00,0x28,0x00,0x47,0xd9, + 0x58,0x20,0xac,0x03,0xf0,0xc5,0xc1,0xe1,0x8c,0xcb,0x8d,0x4d,0xd6,0xf8,0xe3,0xc8, + 0xcf,0x52,0x9c,0x0b,0x91,0xe2,0x64,0x7e,0x2d,0x91,0xd8,0x01,0xfd,0xdf,0x35,0xfc, + 0xd6,0x66,0x31,0xa4,0xa7,0x96,0xaa,0xd5,0x28,0x8d,0xa6,0x99,0x94,0xa4,0x52,0x55, + 0xb1,0x95,0x0c,0xe3,0xc2,0x1d,0x09,0x56,0x9a,0xdf,0x91,0x74,0x5d,0x5a,0xb4,0x39, + 0x98,0x51,0x66,0x2b,0xa0,0xff,0x67,0xdd,0xf2,0x5f,0xf3,0xb8,0x3d,0x16,0x95,0x77, + 0xce,0x47,0x5c,0xe1,0x17,0x8b,0x1e,0x55,0xeb,0xf5,0x56,0x64,0xb9,0xeb,0xde,0xec, + 0xb2,0x9c,0xb4,0x00,0x5b,0x9c,0x74,0x3d,0xe9,0xfb,0x04,0x53,0x88,0xaa,0x51,0x6a, + 0xa3,0x73,0xc9,0xe8,0xbd,0xa2,0xe5,0x91,0x0d,0xd5,0x71,0x79,0x75,0x13,0xea,0x36, + 0xee,0xd1,0x95,0xdd,0xb8,0x15,0x00,0xbf,0x2e,0xeb,0x81,0x4d,0xa1,0xfc,0xaf,0xdb, + 0xbe,0x69,0x22,0x10,0x11,0x2c,0x11,0xff,0xbd,0x2c,0xc9,0x7f,0x57,0x15,0x50,0xf3, + 0x9b,0xd1,0xb3,0xfb,0xa4,0xcc,0xee,0x0c,0x44,0x2b,0x40,0x48,0x91,0xaa,0x19,0xbd, + 0x29,0xc1,0xcf,0xfd,0x3f,0xd3,0x32,0xf0,0x75,0xe9,0xd7,0xa4,0xf3,0x7f,0xff,0xb5, + 0x6f,0x2e,0x2d,0x78,0x17,0xde,0x5e,0xb8,0xf4,0xb3,0x53,0xc4,0x02,0xce,0xbd,0xf6, + 0xe7,0x22,0xec,0x4d,0x4b,0x69,0x87,0xa0,0x9e,0xce,0x89,0x9b,0x44,0x1a,0x80,0xed, + 0x01,0xa0,0x3f,0x1d,0x2e,0x00,0xfc,0x3b,0x9d,0x8b,0x17,0xef,0x9d,0xfd,0xea,0x85, + 0xdf,0x1f,0xc2,0xec,0x1f,0xa4,0x11,0x6b,0x00,0x6c,0xff,0x34,0x55,0xd9,0x25,0xfd, + 0x1f,0x57,0xea,0x18,0x50,0x0d,0xa0,0x42,0x8b,0x81,0x5e,0xd9,0x58,0xb2,0x18,0xc0, + 0x2d,0x62,0x00,0xd8,0x11,0x68,0x6b,0x07,0xa4,0x49,0x01,0xcd,0xe6,0x18,0x32,0x1f, + 0xe4,0xbf,0x7b,0x39,0x5d,0xd5,0x6f,0xf6,0x12,0x58,0x08,0x99,0xc1,0x01,0x43,0x28, + 0x76,0x04,0xa3,0xc5,0x46,0xca,0x8c,0xb9,0xd2,0x90,0x92,0x55,0xab,0xac,0x2f,0x6d, + 0x97,0x55,0x2b,0xad,0xd2,0xac,0x5d,0x56,0xcc,0xf2,0x49,0x38,0x34,0x4a,0x96,0x47, + 0x16,0xac,0x9a,0x89,0x43,0x50,0x1e,0xf7,0xc6,0x2c,0x0a,0x86,0xdf,0xc3,0x28,0xc8, + 0x7f,0xf7,0x92,0x45,0x52,0xce,0x8e,0xa6,0xa2,0xed,0xc2,0x5d,0xdb,0xa1,0xeb,0x2c, + 0xd8,0x06,0xdf,0xd2,0x40,0x91,0xa2,0x4d,0xb8,0x1d,0x11,0xd9,0x89,0x6e,0x39,0x1d, + 0x1a,0x71,0xda,0x87,0xd0,0xc2,0x9e,0x1e,0xc5,0x4d,0xc6,0xdd,0xca,0x52,0xb4,0x58, + 0x2c,0xda,0x7d,0xe3,0xe7,0x1d,0xa8,0xdb,0xb4,0x49,0x15,0x77,0x38,0x18,0xf8,0x27, + 0xbe,0x04,0x29,0x34,0x68,0x47,0x69,0xac,0x90,0x33,0xd1,0x82,0x8a,0xe0,0xcb,0x26, + 0xbf,0xdc,0xfe,0x57,0x54,0x62,0xd9,0x4d,0xe1,0x4c,0x42,0xc9,0xe3,0x60,0x67,0xcc, + 0x07,0xbf,0x2a,0xde,0xd5,0x58,0x8a,0x2c,0x59,0xb9,0x34,0x0d,0x19,0xfe,0x2a,0xdf, + 0xb4,0x38,0x80,0x2e,0x7d,0x8a,0x60,0x7f,0xfd,0xfa,0xc2,0xdb,0xd8,0x8e,0xc6,0x20, + 0x76,0xfc,0x4f,0x90,0x03,0x14,0x8f,0x2d,0x88,0xc5,0xef,0xb3,0x10,0xdc,0x72,0x21, + 0xd4,0x7e,0x1e,0x84,0xfd,0x74,0x8b,0xfd,0xa5,0x5b,0x22,0x1b,0xfc,0x39,0x58,0x0d, + 0xc3,0x01,0xd0,0x87,0x33,0xcc,0x84,0x7f,0xa7,0xe3,0xeb,0xbc,0xd3,0x79,0xf8,0xf0, + 0xe2,0x57,0x87,0x31,0xfa,0x0f,0x49,0xbe,0x99,0xbb,0xbd,0xbc,0xb4,0xd7,0xe7,0x1d, + 0x00,0x28,0xff,0xe1,0xe8,0x76,0x4b,0xd8,0x07,0xd0,0xc0,0x89,0x40,0x57,0x2c,0x0d, + 0xe0,0x0b,0x5b,0x1d,0x80,0x31,0x00,0xde,0x17,0x88,0x34,0x1e,0x56,0x58,0x6f,0x8e, + 0x33,0xf3,0xbb,0x09,0x71,0xa6,0x5d,0xd3,0xdb,0x0c,0xff,0xce,0xd1,0x22,0x29,0xdb, + 0xd0,0x82,0x62,0x4d,0x2b,0x57,0x97,0x70,0x86,0x52,0x76,0xdb,0x59,0x03,0xd0,0x36, + 0x92,0x22,0xac,0xe4,0x7a,0x3b,0xee,0x95,0x6c,0x50,0xfb,0x57,0xa5,0xbd,0x09,0xbb, + 0x4a,0xaa,0x87,0x53,0x75,0x05,0x03,0xdf,0x17,0x0f,0x2a,0x6e,0x07,0x92,0x52,0xa3, + 0xe5,0xcd,0x24,0xc9,0xbd,0x0d,0x2f,0x28,0x2e,0x07,0xbb,0x77,0xd2,0xd2,0x91,0x7e, + 0xbf,0x2c,0xc2,0x7f,0x5b,0x6c,0x3f,0xc9,0xb5,0x31,0xd7,0xb7,0x3d,0x76,0xe7,0x46, + 0x88,0x65,0x84,0xbb,0xad,0xa0,0x72,0x70,0x44,0x27,0x92,0x42,0x19,0xee,0x1a,0x53, + 0x3a,0x26,0x59,0x09,0x32,0x54,0x81,0xb3,0x8d,0x88,0x7b,0x09,0x40,0xb4,0x2d,0x45, + 0x6a,0x4e,0xaf,0xa7,0xa3,0xd7,0x17,0x5a,0x04,0xed,0xd6,0xf1,0xef,0x93,0xa8,0xff, + 0x71,0xeb,0xdb,0x96,0x97,0x35,0xa4,0x13,0xd8,0x3e,0xfc,0x39,0x72,0x85,0xd7,0x18, + 0xf2,0x5a,0x5e,0x31,0x78,0xdd,0x20,0x7d,0x5e,0x89,0xbf,0x0f,0x23,0xb0,0xaa,0xfa, + 0x14,0xa9,0x74,0x2b,0xed,0x35,0x23,0x17,0xc6,0xb3,0xe5,0x65,0xd5,0xfe,0x02,0xa0, + 0xbf,0x10,0x06,0xec,0xfb,0x7c,0x9d,0x7b,0xf7,0xde,0x79,0xf8,0xf0,0xe1,0x57,0x87, + 0xa3,0xfe,0x63,0x0f,0x20,0xcd,0x00,0xc2,0x06,0xc0,0xf5,0xed,0x52,0xb7,0x3b,0xd0, + 0x06,0x9a,0x8e,0x6b,0x3e,0x95,0x56,0x70,0x14,0x00,0xeb,0x04,0x58,0x9a,0xa3,0x46, + 0xc0,0x1c,0xf5,0x03,0x62,0x47,0x20,0x70,0x00,0x3e,0x25,0xd0,0xe2,0x00,0xe3,0xd9, + 0xe1,0x15,0xc4,0xbf,0x4b,0xe3,0xd4,0x3c,0x94,0x37,0x4d,0x73,0xc8,0x30,0xa7,0xdb, + 0x47,0x32,0x57,0x32,0xa2,0x62,0x17,0xb4,0xc3,0x3a,0xde,0xeb,0x6d,0x2c,0x6d,0x50, + 0x67,0xba,0xab,0xa9,0x48,0x1a,0xdd,0x72,0x96,0x50,0x45,0x59,0x2e,0x09,0xbf,0x53, + 0xd2,0x4b,0x83,0x23,0x93,0x65,0x5f,0x49,0xc9,0x38,0xb8,0xd8,0xdd,0xa8,0xbe,0x53, + 0x33,0x6c,0x88,0x8b,0xd9,0x34,0xf8,0x55,0xaa,0x84,0x7e,0xd1,0x22,0x9c,0x5a,0xcd, + 0xe6,0xc1,0x94,0xbc,0x60,0x4e,0x0f,0xf4,0x47,0xa2,0xa1,0x72,0x65,0xbb,0x07,0x96, + 0x39,0xd9,0xab,0x6c,0x52,0xdf,0xa6,0x6b,0x57,0x5f,0x8f,0xcb,0xef,0x9c,0x96,0x89, + 0x0a,0xc7,0x0a,0xf7,0x92,0x4d,0x97,0x65,0xe7,0x67,0x4e,0xdc,0x64,0xb7,0x71,0x05, + 0x74,0xf7,0x94,0x0e,0x21,0x43,0x6d,0x86,0xba,0xc2,0x25,0x4a,0xb1,0xed,0x26,0xf4, + 0x7c,0x2c,0x92,0xdb,0x56,0x4e,0x71,0x34,0x2d,0xbc,0x85,0x8d,0x7d,0xd7,0xb9,0x98, + 0x0f,0x33,0xe8,0x61,0xbd,0x7a,0xe1,0x6f,0x90,0x2f,0x9c,0x6e,0x71,0x9c,0xb7,0x0c, + 0xb1,0x3c,0x71,0xf2,0x57,0xec,0xe0,0x00,0x45,0xa1,0xec,0xe5,0xa2,0x3a,0x6d,0x3c, + 0xe7,0x27,0xf3,0xdc,0x10,0xf2,0xad,0xb4,0xe1,0x71,0xcb,0x16,0x06,0x37,0x18,0x66, + 0x66,0x9f,0x6c,0xa4,0xcd,0x70,0xf0,0x2f,0xdc,0xe2,0xc2,0xbf,0x03,0xd2,0xdf,0xe7, + 0xbb,0x07,0xf4,0xce,0xbd,0x87,0xbf,0x7f,0xe7,0x90,0xd4,0x7f,0x90,0x1f,0x34,0x02, + 0xf8,0x0a,0x8d,0x00,0x86,0x0a,0xc0,0x00,0x08,0xeb,0x00,0x5d,0xb5,0xb4,0xbd,0x3b, + 0x6c,0xac,0xa6,0xca,0xc4,0x00,0x50,0x03,0x60,0x03,0x81,0x68,0x41,0x90,0x38,0x2e, + 0x0b,0xcc,0xe7,0x04,0x12,0x03,0x00,0x16,0x30,0xce,0xf6,0x50,0xfe,0xbb,0x87,0xa8, + 0x22,0xf3,0x57,0xec,0x59,0xc5,0x4e,0x10,0x3b,0x65,0xb1,0xd8,0x19,0xde,0xb1,0xac, + 0x29,0xca,0x9c,0x36,0xaa,0xe2,0xc2,0xda,0xb4,0xa8,0x8e,0xb3,0xf8,0xcb,0xb5,0x31, + 0x1f,0x89,0x4c,0x25,0x55,0x51,0x6e,0xb5,0x35,0xf7,0x22,0xd9,0x3b,0x34,0x92,0x5d, + 0x95,0xda,0xc9,0x89,0x88,0x28,0x23,0x39,0xda,0xaf,0x0b,0x16,0x00,0x8d,0x2c,0x59, + 0xf6,0xac,0xf8,0x5a,0x17,0xeb,0x7b,0x14,0xeb,0xbd,0x19,0x63,0x6e,0x2b,0x19,0xd8, + 0x37,0xcd,0xf5,0x45,0xa5,0xa8,0x58,0x5d,0xa7,0x07,0x95,0x75,0x6c,0x5f,0xfd,0x81, + 0x9e,0x89,0x96,0xdd,0xbb,0x19,0x90,0xb2,0x64,0x8f,0x98,0x61,0x4a,0xce,0x0e,0x37, + 0xdb,0xee,0xf5,0x4f,0x20,0x37,0xd6,0x8a,0x4e,0x07,0x9e,0xc1,0xe8,0x0a,0x1b,0x2b, + 0xe8,0xec,0xb6,0x1f,0x63,0x92,0xd2,0x29,0x3c,0x9c,0xe9,0xc1,0x18,0xaa,0x20,0xd0, + 0xc8,0x35,0xb7,0xeb,0xf1,0x65,0x55,0x9c,0x3a,0xb8,0x4e,0x68,0x02,0x33,0xd4,0x3e, + 0xbe,0xe4,0x59,0xb0,0x37,0xa7,0xa3,0x28,0xff,0xd5,0x22,0xed,0xd9,0x7b,0x06,0xaa, + 0x1b,0xaf,0x7c,0xfe,0xad,0xf7,0xf8,0xab,0xa7,0x7f,0xf1,0x0d,0x13,0xaa,0xde,0x85, + 0xd3,0xa7,0x4f,0xbf,0xfa,0xe1,0xc2,0x6b,0xc0,0x00,0xfe,0x70,0xa9,0xc5,0xd4,0x6c, + 0xaf,0xe8,0x08,0xd3,0x73,0xd4,0xc4,0x51,0x24,0xf3,0x67,0xc4,0x18,0x40,0x3f,0x47, + 0xa3,0xf9,0x67,0x9e,0xde,0x82,0x97,0xfe,0xc2,0x4c,0x87,0x0f,0x33,0x9b,0x69,0xf6, + 0x96,0xbc,0xb1,0x3c,0x32,0x7d,0x68,0x71,0x7b,0x2c,0xce,0x9c,0xd2,0xf0,0x8c,0x49, + 0xff,0x8e,0x2f,0xcf,0xf1,0xff,0xf1,0x3b,0x0f,0x0f,0x4b,0xfd,0x07,0x1e,0x9f,0xcb, + 0xd1,0x0e,0x00,0xf5,0x60,0x36,0x26,0x97,0xd4,0xc1,0x00,0x97,0x76,0x1d,0x20,0x03, + 0xa0,0x61,0x40,0xc1,0x3a,0x54,0x01,0x36,0xf7,0x88,0x01,0x2c,0xae,0xe5,0xb0,0x11, + 0x80,0x37,0x03,0x8e,0xe3,0x16,0x07,0xd8,0x02,0x0e,0x90,0x0c,0xca,0xd1,0xb6,0x68, + 0x88,0xba,0x74,0xbb,0xd9,0x34,0x73,0xd3,0x40,0x09,0xdc,0x79,0xf4,0x3a,0x17,0x3b, + 0xce,0x0e,0xc3,0x31,0x5a,0xa0,0x13,0xfe,0xe2,0x31,0x79,0xaf,0x5a,0xdd,0xdc,0xcc, + 0xd4,0x1b,0xb1,0xd2,0xc0,0xb5,0x9e,0x47,0xa5,0xe6,0x4f,0xd2,0x48,0x44,0xa5,0xa9, + 0x24,0x13,0x7b,0xb2,0xf0,0x23,0x77,0x1e,0x6b,0xaa,0xac,0xab,0x1e,0x5b,0x34,0xd0, + 0xfb,0x80,0x8a,0x33,0x9f,0x04,0x03,0xdf,0xab,0x64,0xab,0x59,0x74,0x17,0x77,0x8a, + 0xb9,0x52,0xbc,0xb3,0x58,0x23,0x5a,0x86,0x83,0xfe,0x26,0x0f,0x7c,0x56,0xab,0xee, + 0x53,0xbe,0x23,0xd8,0xed,0xd2,0xe4,0xb8,0x66,0xc1,0x3c,0xfb,0xc4,0x58,0x2f,0x02, + 0xfe,0x47,0x41,0xc1,0xec,0xaa,0x46,0x92,0xfb,0xa2,0x58,0xff,0x80,0x06,0x25,0x1b, + 0x8b,0x92,0x28,0x76,0x75,0x83,0x2c,0x2a,0x66,0x1a,0x90,0xf7,0xc5,0x66,0x02,0x32, + 0x22,0x23,0x1a,0x2b,0x34,0xd8,0xc3,0x15,0x1b,0xf6,0xa1,0xea,0x52,0x35,0x44,0x79, + 0x64,0xa5,0x10,0x32,0x54,0xc2,0xbf,0xbb,0x25,0xd1,0xe9,0x7a,0xa3,0xdd,0x13,0xa9, + 0xfe,0x40,0x7f,0x2f,0x69,0x8f,0xd5,0x78,0x93,0x25,0x8f,0x2d,0x19,0x9a,0x93,0x86, + 0x26,0xcb,0xca,0xa6,0xf1,0x21,0xc8,0xa9,0xde,0x5c,0x20,0x98,0xa5,0x8f,0xbf,0x02, + 0xd5,0xfc,0x33,0x00,0xb1,0x33,0x00,0xf6,0x3f,0x6b,0x21,0xd0,0x18,0x4f,0x38,0xf7, + 0xb3,0x16,0xa9,0x06,0x6f,0xa1,0xbd,0x30,0x80,0xad,0xd5,0x6a,0x4d,0x22,0xb9,0xc5, + 0x60,0x89,0x52,0xb9,0x80,0xb2,0xb9,0x65,0x81,0x98,0x1e,0x85,0x5b,0x84,0x75,0xf6, + 0x82,0xec,0xe1,0xd9,0xe2,0x30,0x66,0x3c,0x00,0x19,0x48,0x81,0x9e,0xf0,0x0b,0xe2, + 0x3b,0x6d,0xb0,0x8a,0x30,0xf7,0x8b,0x18,0x05,0x5a,0xa0,0x58,0x80,0x27,0xcc,0x40, + 0xe0,0x07,0xe9,0x8f,0xe8,0x9f,0x9f,0x9f,0xbf,0x0f,0x04,0x0c,0xe0,0xb0,0xd4,0x7f, + 0x9c,0x4b,0x7b,0x33,0xb4,0x3c,0xb7,0x11,0x28,0xd3,0x08,0xa0,0xae,0x0e,0xf8,0x1f, + 0x3c,0x06,0x06,0xd0,0xed,0x96,0x4a,0x2b,0x96,0x06,0xb0,0x71,0xb9,0xb6,0xbc,0x78, + 0x1b,0x1b,0x01,0x4c,0x15,0x80,0xe1,0x7f,0x4c,0x6b,0x03,0x21,0xa5,0xe4,0x40,0x3b, + 0x95,0x75,0x8f,0xe6,0x94,0x96,0xa9,0x81,0x50,0xe1,0x65,0x1d,0x87,0x0c,0x60,0x9f, + 0xa1,0xf2,0x05,0xc7,0xbf,0xbb,0xc3,0x30,0xde,0x6c,0xb2,0x7e,0x45,0x12,0x3e,0x35, + 0x2d,0x85,0x4d,0x80,0x7d,0x9c,0x52,0xaf,0x0a,0x16,0xa9,0x2a,0x8d,0x6a,0x6b,0xb7, + 0xbe,0xf4,0x27,0x42,0x4b,0xab,0xfb,0x2c,0x91,0x86,0x6d,0x7f,0xdb,0xb2,0x14,0x50, + 0x78,0xf8,0x45,0x1a,0xbc,0xac,0x28,0x51,0xb5,0x1f,0x18,0x35,0xb6,0xdd,0xeb,0x55, + 0xed,0x51,0xf0,0xcd,0x49,0x52,0xf8,0x89,0x9e,0xe4,0x70,0x7c,0x11,0x35,0xee,0xed, + 0x60,0x0d,0xdf,0x79,0x60,0x15,0xc8,0xdd,0x06,0x61,0xa3,0xa8,0x62,0xf3,0x5e,0x39, + 0xe8,0x80,0x08,0x83,0xb2,0x14,0x00,0x65,0xe9,0x0d,0x17,0xb3,0xac,0x8c,0x5d,0x11, + 0x45,0x27,0x5b,0x20,0x8a,0xdb,0x75,0xd1,0x80,0xe1,0x65,0x7b,0xc0,0x98,0x12,0x8a, + 0x5f,0x0d,0x82,0xfc,0x5f,0x17,0xee,0xdb,0xb5,0xff,0x96,0x23,0xf0,0x85,0xbd,0x24, + 0xf9,0x60,0x7a,0xa8,0x64,0x90,0xa1,0x8a,0xd7,0x80,0x9f,0x5a,0x80,0x49,0x9a,0x2e, + 0x05,0xb7,0x8a,0x46,0x6a,0xbb,0xd3,0xc8,0xba,0x70,0x53,0x91,0x0a,0x14,0xfc,0x8e, + 0x01,0xe0,0x10,0x6d,0xa7,0x00,0xe2,0xa7,0x10,0x79,0xbf,0x05,0xc3,0x47,0xa4,0x53, + 0xb7,0x8e,0xbf,0x09,0xe6,0x9f,0x83,0x82,0x7d,0x09,0x0c,0xc5,0xbf,0xe4,0x32,0x97, + 0x41,0xce,0x41,0x5e,0x2e,0x95,0x6d,0x0f,0x00,0x96,0xec,0x99,0xd0,0x01,0xb1,0x80, + 0x34,0x86,0x13,0x36,0xd8,0x86,0x69,0x93,0xf1,0x08,0x06,0xf1,0xb0,0xd7,0xf2,0x10, + 0x0f,0x23,0x18,0xcb,0x6b,0xd6,0xe6,0x0f,0x2c,0xc0,0x07,0x74,0x81,0xe0,0xff,0xf4, + 0x11,0x30,0x80,0xc3,0x18,0xfc,0xcb,0xa9,0xef,0x09,0x5d,0xab,0xd1,0x12,0x40,0xc3, + 0x58,0x49,0xd5,0x41,0x01,0x40,0x42,0x0d,0x00,0x3b,0x01,0x70,0x26,0x40,0x3d,0x83, + 0xeb,0xcb,0xd0,0x50,0x60,0x5c,0x11,0x8c,0x35,0x03,0x32,0x0e,0xc0,0xaa,0x01,0x47, + 0xb1,0x25,0xe0,0x4e,0xa6,0x14,0x68,0x8b,0x98,0xbf,0x54,0x73,0xce,0x22,0x61,0x94, + 0x38,0x92,0xea,0x0b,0xc5,0x8e,0xea,0x6f,0x9a,0x83,0x8b,0x80,0x9e,0x04,0x8f,0x04, + 0xaa,0x1b,0xb4,0x47,0x69,0x05,0xfb,0xd3,0xd1,0xba,0x73,0x7e,0x99,0xae,0xaa,0xee, + 0xae,0x71,0x4e,0x3b,0x6c,0xf6,0xa9,0xd6,0xf3,0x5b,0x63,0x96,0x98,0xcf,0x55,0xbd, + 0x8d,0xfa,0xbf,0x73,0x7f,0x61,0xa8,0x14,0x59,0xa1,0x8b,0x29,0xa4,0xa7,0x32,0xa9, + 0x8a,0x68,0xa5,0xeb,0xe9,0xa8,0xbc,0xf5,0x0c,0xcf,0x45,0x94,0xd3,0x46,0xe2,0xca, + 0x52,0x6f,0x2c,0x8e,0xe8,0x88,0xa0,0x58,0xea,0x3a,0x53,0x65,0x67,0xc9,0x6e,0x8b, + 0x9c,0xfa,0x71,0x9b,0x65,0x51,0x46,0x1c,0x44,0xf2,0x13,0x5b,0x36,0x21,0x45,0xf5, + 0x7e,0xa0,0x9e,0x5d,0x79,0xd6,0x1e,0x70,0xcf,0x26,0xc8,0xab,0xc7,0x7a,0x37,0x52, + 0x7d,0xce,0xd4,0x61,0xd1,0xb8,0xf3,0x12,0xa1,0x29,0x8c,0xe2,0xff,0x95,0xe3,0x20, + 0xa5,0x5b,0x5c,0xfe,0x23,0xee,0x50,0xef,0x6f,0x7e,0x88,0x92,0xf7,0x34,0x32,0x85, + 0x6f,0xc3,0xac,0xae,0xcd,0x40,0x3b,0x71,0x32,0x9a,0xb8,0x65,0xaa,0x81,0x71,0x9f, + 0xb6,0xdb,0x33,0x4c,0xe1,0x96,0xa1,0x0b,0xd8,0xd8,0x82,0x69,0x2b,0x6d,0x59,0xb6, + 0x33,0x90,0xf0,0xa4,0x81,0x49,0xfe,0x02,0xd4,0xfb,0x41,0xfa,0xcf,0xcf,0x5f,0xb8, + 0x7f,0xe1,0xe9,0xfd,0x47,0xf7,0x1f,0x7d,0xfc,0xf1,0x7f,0x1c,0xca,0xe0,0x1f,0x46, + 0xc3,0x1c,0xeb,0x01,0xac,0xe3,0x12,0x40,0x6a,0xf7,0x06,0xdf,0xa7,0x03,0xbb,0xaf, + 0x64,0x1c,0x06,0x10,0xc4,0xc5,0x00,0x70,0x2e,0xd0,0xd2,0xe5,0xe5,0x65,0x6c,0x04, + 0xa0,0x3a,0xc0,0xad,0x49,0x0e,0x30,0x4e,0x8e,0xc7,0x81,0x6e,0x3b,0x83,0x53,0xf5, + 0x9d,0xdd,0x48,0x54,0xe2,0xa0,0xbc,0xd3,0xc4,0x41,0xfe,0xc3,0x4b,0x82,0x15,0x3b, + 0xf7,0x68,0xb1,0x6e,0x82,0x65,0xa8,0x61,0x3f,0xa4,0xc6,0xf6,0xaa,0x7b,0x7b,0x9b, + 0x26,0x03,0x78,0xae,0xca,0x10,0x4e,0xfa,0xd3,0xe5,0xf5,0x92,0x36,0x97,0xb4,0xf9, + 0x89,0x71,0xd8,0x9a,0xd3,0xdb,0xed,0x91,0x68,0xfe,0x59,0x39,0xa9,0x58,0xf1,0xe4, + 0xd7,0x2d,0xeb,0x81,0x82,0x75,0x97,0x7e,0x39,0xf8,0x47,0x40,0x86,0x53,0x2a,0x89, + 0xe1,0x4f,0x5d,0xb4,0xb7,0x14,0x8f,0x36,0xea,0x0b,0xf1,0x2f,0xc7,0x15,0x91,0x3f, + 0x5b,0x19,0xb5,0xdf,0xa6,0x85,0x13,0x9c,0x89,0xb5,0x61,0xda,0xdf,0xe2,0xf3,0xf1, + 0xe2,0x72,0x16,0xe4,0xbf,0x60,0xac,0xd0,0x41,0xa4,0x7e,0x49,0x7e,0x19,0x89,0xa5, + 0x28,0x7b,0x7a,0xa0,0xfd,0xd3,0xac,0xa0,0x41,0x65,0x6a,0x82,0xcc,0x02,0x19,0xe4, + 0x21,0x0f,0xa7,0x48,0x1f,0x23,0x3b,0xc9,0xfc,0xcb,0x05,0xc0,0xd0,0x77,0x2d,0x42, + 0xfd,0x6b,0xd8,0x8a,0x4e,0xa6,0x8f,0xbc,0xdf,0x01,0xbc,0x90,0x27,0xcc,0x9c,0x42, + 0xa9,0xeb,0x5d,0x78,0x1d,0xd9,0x83,0x01,0xcf,0xb4,0xeb,0x34,0x11,0xcb,0xcf,0xb0, + 0x01,0xd3,0xef,0xcc,0xd7,0x96,0xfa,0x1f,0x36,0xe5,0xbc,0x43,0x1f,0x48,0x0b,0x38, + 0x00,0xab,0x06,0xa4,0xbf,0x6b,0xb1,0x7a,0x3e,0x36,0xf3,0xe3,0xf9,0x1d,0xeb,0xed, + 0x43,0xf4,0x17,0x3a,0xd8,0xe7,0x07,0xf0,0x9f,0xbf,0x70,0xe1,0xc2,0xc9,0xfb,0x4f, + 0x81,0x5e,0xfc,0xec,0xd1,0xc7,0x87,0x31,0xf7,0xd7,0x20,0xed,0x5a,0xee,0xf6,0x0f, + 0xa8,0x07,0x00,0x2a,0x00,0xd4,0x03,0xa8,0xd1,0x6e,0x32,0xd4,0x09,0x20,0x63,0x23, + 0x20,0xf6,0x02,0x04,0x90,0x01,0xcc,0xd5,0xae,0x91,0x0a,0xc0,0x7b,0x02,0x19,0x07, + 0xe0,0x0c,0x60,0x3c,0x8e,0x02,0x9a,0xea,0x15,0x41,0xe6,0x6f,0xe0,0xba,0x61,0x40, + 0x54,0xe2,0xb7,0x78,0xa9,0xdb,0x02,0xb1,0x93,0x05,0xf9,0x8f,0x53,0xd4,0x1c,0x0c, + 0x43,0xf7,0x60,0xde,0xb3,0x05,0xc7,0xd1,0x80,0x13,0xc5,0x40,0x01,0xd8,0xbc,0xd2, + 0xae,0xaf,0x56,0x7a,0xb8,0x64,0xfc,0xf4,0x5f,0xb7,0x83,0xbb,0x0f,0x74,0xb7,0x87, + 0xbb,0x52,0x2a,0xce,0xc2,0x57,0x58,0x7b,0x25,0x06,0x51,0xd3,0xda,0xed,0xb2,0x60, + 0xfd,0x99,0xc8,0x2a,0x0b,0x7c,0x4b,0x7c,0x82,0x37,0x1e,0x3d,0x85,0x70,0x74,0xf3, + 0xae,0x29,0x29,0x38,0xa6,0x08,0x4c,0x79,0x40,0xa8,0x1e,0x75,0x15,0x13,0xcb,0x3d, + 0x9f,0xbf,0xe4,0x57,0x84,0x8e,0x02,0x7a,0x5f,0x9c,0x1b,0x51,0xcb,0x4e,0x92,0xf2, + 0x62,0x6b,0x2c,0x57,0xa0,0xfe,0x2f,0x18,0x2b,0x70,0x10,0x11,0xa3,0xde,0xe2,0x58, + 0xc5,0xfc,0xad,0x6a,0x01,0x60,0xa8,0xb2,0xbb,0x42,0x35,0x1d,0x41,0x66,0x69,0x83, + 0x92,0x2c,0x65,0xc7,0x2c,0x7e,0x82,0xcf,0x4a,0xda,0xfe,0x9d,0xc7,0x8f,0x00,0x46, + 0xe9,0x70,0xc7,0xfb,0x4b,0x5c,0x06,0x08,0x51,0x9b,0x46,0xfd,0xff,0x2d,0x04,0x99, + 0x97,0x9a,0xfd,0x3e,0x69,0x11,0xe6,0x90,0x2b,0xfc,0xa2,0xc5,0x54,0xf0,0xb0,0x9b, + 0x38,0x2c,0x2d,0x4a,0x17,0x5a,0x05,0xb2,0xcb,0x14,0xf9,0x70,0x78,0x42,0x86,0x03, + 0x96,0x0b,0x4c,0x84,0xb3,0xb6,0xfb,0x34,0x73,0x84,0xf7,0x05,0x8a,0x10,0x56,0xec, + 0x0d,0x9f,0x99,0xa8,0x2f,0xf0,0xa0,0xd9,0x7b,0xb8,0x16,0x08,0xfb,0xd8,0xdf,0xdf, + 0x29,0x74,0xf2,0xbe,0x7c,0x1e,0x85,0xff,0xd3,0xa7,0x27,0x4f,0x9e,0xbf,0xfa,0xf4, + 0xc5,0x17,0x1f,0x3d,0x3a,0xb4,0xd6,0x7f,0xa4,0x4d,0xec,0x01,0xa8,0x52,0x0f,0x40, + 0x0c,0x7b,0x00,0x70,0x6b,0x26,0x89,0x18,0x00,0xcd,0x05,0xc4,0x1d,0x01,0x52,0xa3, + 0x72,0xfb,0x77,0xd4,0x0d,0x00,0x75,0x80,0xdb,0x6b,0x6b,0x37,0x71,0x3e,0x80,0xc9, + 0x01,0x40,0x09,0xc0,0xb6,0x80,0x4d,0x3d,0x03,0xf5,0x7f,0xc1,0x92,0x73,0x7d,0xde, + 0x46,0x68,0x10,0x33,0x6d,0xf9,0x7b,0x95,0x7e,0x39,0x25,0x98,0x7e,0x33,0xc8,0xa1, + 0x1d,0xb0,0xf5,0x26,0xb7,0x1d,0x0f,0xea,0x19,0x54,0x00,0x70,0x9f,0xa2,0xca,0x4a, + 0x49,0xb8,0x6b,0xd0,0x7e,0xf4,0xf8,0xf1,0x40,0x95,0xd7,0x2b,0x7a,0xc9,0x63,0x06, + 0xaf,0x18,0x51,0xa8,0x0d,0x32,0x38,0xb2,0xd8,0x3d,0xf0,0xad,0x71,0x94,0xac,0x4c, + 0x9e,0xd6,0x91,0x4c,0x26,0xf4,0xd5,0xfe,0x48,0x24,0x8e,0xa7,0xa4,0xca,0xd8,0x4c, + 0x90,0xad,0xa9,0x8e,0x84,0x1a,0x24,0xf9,0xef,0xaa,0xa3,0x77,0x13,0x49,0x51,0x44, + 0x93,0xc4,0x8d,0x45,0xb9,0xd1,0xb6,0xe5,0x03,0x1c,0x5b,0x5b,0xc9,0x78,0x6c,0x57, + 0xac,0x88,0x1d,0x44,0x37,0x3c,0xec,0x2b,0xcc,0xac,0x5d,0xd2,0x70,0x4d,0xe7,0x9e, + 0x63,0xb9,0xd6,0x69,0x49,0x8a,0x68,0xb8,0xe1,0x80,0x2a,0xd5,0xec,0xe5,0x64,0x32, + 0x91,0xec,0xa7,0xf5,0x98,0xe8,0x57,0x1f,0x20,0x8a,0xc2,0xe1,0x1f,0xff,0x61,0x66, + 0xe6,0x27,0x67,0x09,0x50,0x67,0x08,0xff,0x80,0xde,0x0f,0xce,0x81,0xe9,0x55,0x14, + 0xb9,0x00,0xb5,0x4b,0x4d,0xe2,0x0a,0x4c,0xe0,0x0a,0x18,0x40,0xb8,0x20,0x7a,0x5c, + 0x98,0xb8,0xb8,0xde,0x15,0x1c,0x76,0x0a,0xb6,0x77,0xec,0x7d,0x61,0xc2,0x63,0x66, + 0x48,0xdb,0x1c,0x81,0xe6,0xef,0x2b,0xa0,0xe6,0x4f,0xc2,0xff,0xfe,0xc9,0xa7,0x57, + 0x9f,0x9e,0xbf,0x7a,0xfe,0xfc,0xf9,0x17,0x1f,0x1d,0xce,0xd8,0x7f,0x83,0x86,0xd8, + 0x03,0x70,0x99,0xcf,0x01,0x56,0xb1,0x05,0x90,0x76,0x69,0xc3,0x6e,0x00,0x9c,0x09, + 0xb0,0xc2,0x34,0x80,0x1f,0xb6,0xfb,0xd1,0x0d,0xea,0x08,0x64,0x2a,0xc0,0xcd,0x2f, + 0x0c,0x1d,0xe0,0x4b,0xde,0x1b,0xf0,0x3d,0xbd,0x8c,0xa3,0x74,0xdc,0x12,0x27,0x33, + 0x4e,0x8a,0x28,0xbe,0x3b,0xc4,0xbd,0xb2,0xdc,0x9d,0x7a,0x5a,0xc8,0x61,0x73,0xec, + 0x91,0x55,0x08,0x7c,0x73,0xb3,0x8f,0x0c,0x00,0xf7,0xc1,0x98,0x46,0x54,0xa1,0x0d, + 0xa8,0xfa,0xdf,0x50,0xb7,0x87,0x59,0x55,0xaf,0x61,0x24,0x68,0xcc,0xd2,0x1d,0xd3, + 0xdf,0x65,0xad,0xdc,0x1e,0x09,0xd6,0x9f,0x8a,0x0c,0x9f,0x4c,0x5a,0x74,0x51,0x42, + 0x6d,0x04,0xca,0x82,0xe5,0xc5,0xa7,0xa5,0x5e,0x7c,0x7f,0xbf,0xc5,0x01,0xca,0x59, + 0xc8,0x20,0x41,0x85,0xa3,0x7b,0x53,0xec,0xa0,0xca,0xf1,0xef,0xca,0x8d,0xb2,0x95, + 0x1b,0xfc,0x03,0xc7,0xb3,0xb1,0x3e,0xc9,0x7f,0x2d,0xf2,0xec,0x3d,0x86,0x9d,0xa4, + 0xe5,0xd0,0xb9,0x0d,0xa6,0x35,0x2d,0xd3,0x1e,0xe1,0xc2,0xa7,0xcf,0x99,0x2a,0x94, + 0x55,0xa4,0xa9,0xc9,0xbd,0x75,0x2d,0x36,0x65,0xe2,0x98,0x01,0xbf,0x49,0xdf,0x72, + 0x8c,0x35,0x9d,0x87,0x3f,0x44,0xf5,0x9f,0x44,0x6a,0xe7,0x0c,0x29,0xfd,0x85,0x30, + 0xb5,0x08,0x7e,0xff,0x2c,0xd6,0xae,0xc3,0x9d,0xc2,0xd9,0x7f,0x9b,0x99,0xf9,0xb4, + 0x05,0x70,0x2b,0x74,0xc0,0x96,0x80,0xc2,0xae,0xc7,0x61,0xfe,0x14,0x9d,0xd3,0xdb, + 0xc9,0xd3,0xe4,0x01,0x78,0xd3,0x29,0x98,0x60,0x67,0xa6,0x8e,0x93,0x1f,0xf0,0x87, + 0x1d,0xce,0x37,0xf0,0xbd,0x0f,0x6e,0xf3,0x1d,0x42,0xff,0xbd,0x0b,0xf3,0xf3,0x4f, + 0x4f,0x82,0xf0,0xbf,0x0a,0x74,0xf7,0xfc,0xf9,0x7f,0x79,0x74,0x78,0xad,0xff,0x48, + 0x52,0xd5,0x13,0xba,0x36,0xb7,0x61,0x28,0x00,0xd4,0x02,0x48,0xf0,0xd7,0x06,0x37, + 0x78,0x15,0x80,0x86,0x02,0x67,0xfa,0x51,0x6c,0x04,0x00,0x06,0xb0,0x68,0x71,0x00, + 0x6c,0x07,0xe0,0x5a,0xc0,0x92,0x56,0x2e,0xd7,0x69,0xd5,0xdb,0x89,0x12,0xb4,0x13, + 0x19,0x19,0x2d,0x04,0xe3,0x3b,0x47,0xe1,0x72,0x94,0xfe,0xc7,0xc9,0xf8,0xb0,0x17, + 0xc0,0x6a,0xa7,0x63,0xfa,0x0d,0x28,0x81,0xd7,0xd0,0x22,0xfe,0xd0,0x22,0x3a,0x18, + 0x2f,0x1f,0xe9,0x45,0x71,0x4d,0xfc,0x7e,0xa6,0x8c,0x2b,0x95,0x74,0x07,0x9a,0x60, + 0x60,0x9d,0x93,0x76,0x68,0xfb,0x3a,0x75,0xa5,0x12,0xec,0x69,0xed,0x78,0x92,0xfc, + 0x42,0xef,0x78,0x7d,0xe5,0xce,0xd1,0x45,0xbd,0x4e,0xf2,0xdf,0xdd,0x03,0x49,0x4b, + 0x1d,0x8c,0xf7,0xa3,0xe4,0xd8,0xaf,0x56,0x68,0x81,0xbf,0x3f,0x56,0xfe,0xf7,0xfc, + 0x18,0x97,0x3b,0xfb,0x86,0xe0,0x0a,0xf1,0x16,0xe0,0x1f,0x19,0x8e,0x9b,0x59,0xe6, + 0x04,0xd6,0x21,0xea,0x4b,0x00,0x45,0xc8,0x0d,0xe7,0x0a,0xa8,0x91,0x48,0xdd,0x08, + 0xf7,0x28,0xff,0x25,0x9f,0x64,0xe5,0x00,0x6e,0x5a,0x28,0x6a,0xff,0x7f,0x06,0x41, + 0x46,0x2d,0x52,0x1e,0x99,0x27,0x31,0x54,0x61,0x82,0x4e,0xe1,0x1b,0x4e,0xcf,0xec, + 0x96,0x76,0xb3,0xb2,0x54,0xc3,0x14,0x4e,0x26,0xa7,0x48,0x16,0x23,0x60,0x28,0x52, + 0x77,0x7e,0xf5,0x3e,0x87,0xd5,0x75,0xc0,0xfa,0x4b,0x0c,0x68,0xaf,0xa2,0xfc,0x5f, + 0x38,0xfb,0xed,0xfb,0x20,0xfe,0x8b,0xd7,0x5b,0x34,0xaa,0x06,0xde,0xbc,0x85,0x0d, + 0x00,0x85,0x0e,0x47,0x65,0x87,0xc6,0xda,0x84,0x59,0xc3,0x3b,0x5e,0x09,0x90,0xcc, + 0x40,0x0c,0xa3,0xc3,0x9d,0x75,0x38,0xf8,0x99,0x0b,0xfb,0x81,0xe1,0x1a,0x2f,0x0a, + 0xdc,0x41,0x81,0xdc,0xa2,0x4e,0x4f,0xa2,0x1d,0x1e,0xf8,0x38,0x47,0xe8,0x30,0x16, + 0x01,0xa7,0x0f,0x71,0x1f,0x46,0xf4,0x77,0x68,0xb4,0x1f,0xc0,0xff,0x02,0x08,0xff, + 0x93,0x27,0x39,0xf8,0xaf,0xde,0xbd,0x7b,0xfe,0xee,0x67,0x77,0x0f,0x55,0xfd,0x8f, + 0x44,0x76,0x73,0x21,0x63,0x11,0x20,0xde,0x05,0x48,0x0a,0x00,0xd6,0x01,0x74,0x63, + 0x39,0x10,0xea,0x07,0x6c,0xf7,0x37,0x37,0x4c,0x0e,0x90,0xcb,0xb1,0xae,0x80,0x84, + 0xc1,0x01,0xe6,0xb0,0x4d,0xfc,0xaf,0x51,0x9a,0x4a,0xb4,0xd2,0xae,0x44,0x5d,0x60, + 0x50,0x10,0x52,0x71,0x61,0xe6,0xc5,0x67,0x7b,0x6d,0x3e,0xaa,0x8f,0xed,0x56,0xbd, + 0xc3,0x87,0x83,0x62,0x01,0x70,0xda,0xad,0x6a,0xb3,0xd1,0xcd,0xcd,0xe8,0x95,0x00, + 0x6e,0x55,0x3a,0x8c,0xa9,0x5d,0xb6,0x3f,0x36,0x95,0x1c,0x77,0x59,0xa2,0x53,0xc2, + 0x3d,0x27,0x55,0x79,0x37,0x1b,0x1c,0x3e,0x4e,0xf9,0x45,0x31,0x08,0xe9,0xa9,0x76, + 0x9d,0xa4,0xb8,0xb4,0x13,0x31,0xe2,0x80,0xd7,0x6d,0xa1,0x75,0x1b,0xf9,0xe5,0x21, + 0xc0,0x71,0x9d,0x46,0xba,0xd1,0x3e,0xd6,0x6c,0xf7,0x6d,0x6b,0x9b,0x73,0x63,0x3b, + 0x6e,0xfe,0x2f,0x39,0xcc,0x72,0x62,0x8a,0xd2,0x3d,0x11,0x60,0x6f,0x68,0x6e,0xe8, + 0x61,0xdb,0x3c,0x5b,0x8a,0x3c,0x0e,0x09,0xed,0x1f,0xad,0x69,0xa0,0x8d,0x61,0xdb, + 0x86,0x24,0x49,0xf6,0xd8,0x45,0x82,0xae,0xdc,0x78,0x92,0x92,0xdb,0x99,0x54,0x45, + 0x66,0x39,0xe7,0xfc,0x8c,0xc9,0xc8,0x5b,0x06,0xb4,0xb9,0xe8,0xf0,0x69,0x51,0x1b, + 0xb5,0x8d,0xa9,0x9a,0x3b,0x96,0x0b,0xee,0x68,0xc7,0x91,0x50,0x11,0xea,0x3c,0x65, + 0x7b,0x82,0x63,0x83,0x73,0x57,0x96,0x87,0x0d,0xc8,0x2b,0x71,0x71,0x79,0x16,0x21, + 0x1b,0xfb,0xab,0xb3,0x88,0x36,0x5f,0x07,0x85,0x7e,0xf1,0xc3,0xb0,0x0f,0xa1,0x87, + 0xf2,0xbf,0xf9,0xe9,0xeb,0x6c,0xf2,0xdf,0x4f,0x8e,0xbd,0xe4,0x45,0x88,0xfb,0xc2, + 0xc7,0x66,0x66,0xce,0x1d,0xa7,0x01,0x76,0xe0,0xc0,0x40,0xb9,0x8f,0x80,0x88,0xa7, + 0x0f,0xbb,0xdf,0xf1,0x81,0x0f,0xa1,0xec,0x0b,0xb3,0x46,0xf9,0x4e,0xc7,0x40,0xb6, + 0x71,0x74,0xf8,0xbd,0x79,0xe5,0xaf,0x39,0xf7,0x30,0xd8,0x06,0x31,0x92,0x4e,0x87, + 0xb3,0x03,0xae,0x09,0xf0,0x1b,0x1c,0xe5,0x1b,0xce,0x63,0x98,0x28,0xf9,0x7d,0xa0, + 0xf7,0x43,0xc5,0x9f,0xc3,0xff,0xe5,0xab,0x27,0x4e,0xdc,0x3d,0x71,0xf7,0xfc,0x67, + 0xff,0x7c,0xb8,0xf0,0x8f,0x44,0xf6,0x72,0xb4,0x0b,0x90,0xd9,0x05,0x48,0x0d,0x00, + 0x6c,0x8f,0x6e,0x6c,0x04,0x2c,0x6d,0xe3,0xbe,0xc0,0x41,0x6c,0x04,0x08,0x44,0xf7, + 0x36,0x96,0xe6,0x0c,0x0e,0xb0,0x76,0xd3,0x43,0xe3,0x01,0x12,0x7e,0x54,0x03,0x6a, + 0x83,0x14,0xc8,0xff,0x18,0x62,0x82,0x46,0xbe,0x9b,0x94,0x75,0xa2,0x89,0x65,0xb0, + 0x3f,0x08,0x62,0x27,0x55,0xd9,0xc6,0x3d,0x40,0x69,0x87,0x70,0xd3,0xc1,0x92,0xa0, + 0xfc,0x47,0xb5,0x6c,0x14,0x15,0x80,0x40,0xbb,0x5e,0x6f,0x54,0x30,0x9a,0xc8,0xa2, + 0xf6,0xef,0x9c,0x26,0xf4,0xeb,0xa5,0xed,0x61,0x63,0xb5,0xa2,0xcd,0x7e,0x01,0x41, + 0x52,0x43,0xe5,0x93,0xf1,0xd8,0x6c,0xb0,0x1c,0x87,0xba,0xab,0x6d,0xda,0x81,0x46, + 0x9b,0x8c,0xf1,0xce,0x81,0xf0,0xf4,0xf7,0x76,0x03,0xc8,0xbb,0x70,0x4b,0xce,0xe7, + 0x26,0xe0,0x19,0xaa,0x67,0x6c,0x8f,0xc8,0xc1,0x74,0xab,0x87,0xcc,0x72,0xb8,0xdd, + 0xd5,0x9c,0xbe,0x2d,0x8b,0x1d,0xd4,0x08,0x8a,0x3d,0x6a,0x2c,0xb1,0xa7,0x6f,0x64, + 0x18,0x77,0xe2,0x2b,0x9e,0x52,0xa9,0x6b,0x85,0x78,0xea,0x54,0xf1,0x47,0x42,0x8c, + 0x2f,0x3b,0xbc,0x0a,0x69,0x75,0xd0,0x22,0x77,0x6d,0x81,0x3e,0x93,0x34,0xe3,0x82, + 0x8d,0x4d,0x2a,0xb0,0xea,0x4a,0x30,0xa8,0xab,0xa4,0xd0,0x18,0xc3,0xcb,0xa6,0x23, + 0x1c,0x8f,0xfe,0x12,0xa2,0x19,0x65,0xeb,0x6f,0x19,0xba,0xb9,0xd1,0x4e,0xc5,0x8f, + 0xfe,0x1b,0x65,0x2f,0xb2,0x85,0x73,0x1f,0xc0,0xb5,0x43,0xa8,0x46,0x00,0x76,0xf2, + 0x28,0x9f,0x41,0x03,0x2f,0xf8,0x8c,0xc7,0xfc,0x2c,0xe0,0x73,0x78,0x8d,0xef,0xc3, + 0x93,0xcf,0xad,0x1b,0x46,0x86,0x91,0x14,0x08,0x88,0x0d,0x3a,0xe0,0x21,0x58,0x3c, + 0x80,0x98,0x0b,0x3c,0xc5,0x40,0x59,0xd8,0x06,0xf8,0xb1,0xde,0x3f,0x7f,0xe1,0x29, + 0x97,0xfd,0x27,0x80,0xde,0x3d,0xf1,0xf2,0xcb,0x77,0xcf,0xff,0xef,0x3f,0x1c,0x36, + 0xfe,0xe5,0xd0,0xda,0x35,0x63,0x15,0x40,0xea,0x02,0x60,0x9b,0xb3,0x33,0x0d,0x00, + 0x47,0x02,0xe2,0x6c,0xc0,0x2c,0xd5,0x01,0x40,0x05,0x30,0x38,0xc0,0x6d,0xa8,0x05, + 0xe0,0x78,0x20,0xae,0x05,0x24,0x6a,0x7a,0x30,0x93,0x6a,0xac,0xcb,0x6c,0x12,0xa1, + 0x86,0x33,0x09,0x34,0xbc,0x48,0x43,0x56,0x3f,0xc0,0x46,0x82,0x89,0x2b,0x16,0xbb, + 0x7a,0x76,0xa5,0x64,0x39,0xa0,0xa1,0xc7,0xda,0xce,0xf7,0xe2,0x6e,0xf2,0xb7,0xb5, + 0xd9,0x3e,0x28,0x00,0xd1,0x00,0x38,0x5a,0xa5,0xd5,0x4a,0x74,0x4d,0xb4,0x83,0x7c, + 0x84,0x84,0x0b,0xa1,0x1f,0x85,0x7f,0x23,0x95,0xd5,0x86,0x39,0x33,0xcc,0x27,0x76, + 0x3f,0x73,0x7a,0x03,0x1b,0x14,0xb6,0x55,0x5d,0x1f,0x50,0xf0,0x74,0x82,0x59,0xf7, + 0x08,0x62,0x30,0x11,0x9b,0xe1,0x36,0x40,0x06,0x98,0x5d,0x17,0x62,0x8c,0x73,0xa6, + 0xe8,0x03,0x28,0xfe,0xe8,0x09,0xbb,0xb5,0x9f,0xe4,0x35,0x37,0x62,0xba,0xe4,0x0e, + 0x08,0xc0,0x15,0xe0,0x2c,0x05,0xc8,0x13,0x8b,0x05,0x81,0xc1,0x6a,0x52,0x4d,0xec, + 0x60,0x59,0xab,0xb7,0x47,0xc1,0xf5,0x6d,0x95,0x5b,0xd5,0xd8,0x17,0xea,0x52,0x2f, + 0x31,0x76,0xda,0xcd,0xe8,0x98,0x11,0xbb,0x25,0x55,0xbb,0x31,0x60,0xa4,0xd9,0xbe, + 0xc4,0x1e,0xf3,0x81,0x99,0xb5,0x78,0x23,0x55,0xe3,0x56,0xa6,0x22,0x85,0x34,0x64, + 0xa8,0x15,0x6a,0x45,0xd6,0x79,0x24,0xd1,0x8d,0x3e,0xe0,0xf7,0x46,0x6a,0x98,0x19, + 0x0e,0xb9,0x84,0xd3,0x4d,0x54,0x1c,0x6e,0x0e,0xb5,0xcc,0x94,0xaa,0xcd,0x91,0x4f, + 0xae,0x38,0x3e,0x8b,0x90,0x5b,0xfc,0xcf,0x59,0x6a,0x3c,0x03,0x05,0x80,0xd0,0x4d, + 0x26,0xdf,0x19,0x63,0xe6,0xf9,0xcc,0x39,0xc6,0x01,0x8e,0x61,0x2d,0xbb,0xf3,0x23, + 0xd4,0x10,0x18,0xd8,0xf1,0xe8,0x98,0x3f,0x3a,0xf8,0xc3,0x3c,0x36,0xc5,0xd3,0x41, + 0xb8,0xce,0x23,0x5a,0xf1,0x04,0x6e,0xe0,0xe3,0x17,0xeb,0xcf,0x78,0x80,0x76,0xf3, + 0x78,0x63,0xd9,0x60,0x46,0x84,0x39,0xfc,0x00,0xf0,0x05,0x54,0x2c,0x38,0x53,0xe1, + 0x3a,0xbf,0x6f,0xde,0x77,0x81,0x64,0xff,0xfd,0x93,0x17,0x2c,0xf4,0x9f,0x78,0x00, + 0x1c,0xe0,0xe5,0xaf,0xbf,0xfe,0xa7,0xc3,0x86,0x7f,0x24,0xd2,0x06,0x05,0x60,0xc9, + 0x6a,0x01,0xd0,0x09,0x59,0x08,0x7f,0x89,0x0f,0x05,0xc6,0x6e,0x00,0xdc,0x18,0x10, + 0x54,0x80,0x7e,0x94,0x2a,0x01,0x97,0x97,0x91,0x03,0xac,0x85,0xd6,0x72,0xb9,0x9b, + 0xc8,0x01,0x3c,0x89,0x65,0x3d,0x58,0x1e,0xe1,0x3e,0x22,0xa5,0x92,0xfa,0x06,0xee, + 0x59,0xaf,0xca,0x2a,0x92,0x26,0x27,0x38,0x03,0xf0,0xd3,0x69,0x16,0xe9,0x91,0x9a, + 0x21,0x07,0x32,0x38,0x28,0xbd,0x81,0x9b,0x8f,0xa0,0xbb,0x92,0x2e,0x45,0x27,0x4a, + 0x3e,0xbf,0x26,0xda,0x5a,0x2c,0x10,0xbd,0xd2,0xc7,0x9d,0x31,0xa1,0x0e,0x40,0xeb, + 0x95,0xe2,0x68,0x45,0x10,0xd7,0x5c,0xdb,0x8c,0x30,0x8d,0x13,0xab,0xfd,0xc8,0xb7, + 0x4a,0x25,0xea,0xba,0x18,0x6a,0xc3,0x90,0xdf,0x1e,0xae,0x45,0x39,0x75,0xb6,0x8d, + 0xe3,0x1e,0x7b,0x2c,0xa2,0x10,0x83,0x2e,0x1c,0x38,0x0b,0xfa,0x20,0x78,0x12,0x1c, + 0x57,0x71,0xca,0x04,0xc6,0x9d,0x1c,0x33,0xa7,0x25,0x95,0x6e,0xc9,0x64,0x3b,0xd9, + 0x63,0xb4,0x01,0xdf,0xd9,0x05,0xce,0x15,0x7a,0x9e,0xf2,0x8d,0x01,0x66,0x65,0x4c, + 0x2c,0xd0,0xcf,0xb8,0x5f,0xfc,0xaf,0x4b,0x18,0x14,0xd0,0xa2,0x96,0x2a,0x97,0x83, + 0xc8,0xcf,0x29,0x86,0x14,0x31,0x19,0xd2,0xd7,0xca,0x0d,0x33,0x75,0xbf,0x6c,0x03, + 0xfe,0x47,0xb4,0x02,0x34,0xff,0x12,0xd5,0xfe,0x25,0x3c,0xe2,0x5d,0x16,0x1e,0x19, + 0xc8,0x08,0x61,0xef,0xc5,0x27,0x72,0x34,0x1e,0x1a,0x04,0x31,0x41,0x87,0x58,0x04, + 0x54,0xd3,0x0b,0xc3,0xb1,0x65,0x2e,0x19,0xde,0xb0,0xc7,0xb8,0xed,0xe4,0x10,0x8a, + 0x57,0x2a,0x15,0xd3,0xa2,0xc2,0x9c,0x3a,0x30,0x79,0xfc,0xff,0x98,0x67,0x98,0xea, + 0x74,0x5e,0x45,0x74,0x13,0xe6,0x48,0xfe,0xbf,0xfe,0xf9,0xbf,0x5f,0xff,0xfc,0xfa, + 0xf5,0xeb,0xc7,0xb0,0x12,0xf0,0xca,0x27,0xc0,0x17,0xf2,0xa7,0x80,0x43,0x7c,0x02, + 0xc8,0xc3,0xf9,0x75,0x04,0xc1,0x09,0xca,0x77,0xf8,0x1b,0x1f,0x7b,0xcd,0x2d,0xe0, + 0x78,0x7c,0xe6,0x80,0x58,0x0b,0xfe,0x17,0xf8,0x3f,0xb3,0x54,0xc8,0x9b,0x36,0xe9, + 0x71,0x1e,0xf9,0x11,0x59,0x61,0x3c,0xa0,0x80,0x82,0x1e,0x19,0x0a,0xf1,0x11,0x1e, + 0x16,0xb6,0xf6,0xe7,0x7d,0xf3,0x88,0x7d,0x5e,0xef,0x3f,0xc9,0xc0,0xff,0xde,0x7b, + 0x0f,0xde,0xfb,0xcd,0x6f,0xde,0x7d,0xf9,0xee,0xbf,0x1e,0x6a,0xe3,0x3f,0xa3,0xee, + 0x22,0xb6,0x00,0x44,0x03,0xb8,0x0d,0xf0,0x4a,0x49,0xbd,0x61,0x29,0x00,0xc4,0x00, + 0xa8,0x15,0xb0,0xb7,0x9b,0xcd,0x36,0x98,0x0a,0x10,0xc5,0xcd,0xbc,0xa8,0x33,0xf0, + 0xda,0xed,0x50,0x88,0x58,0xc0,0xcd,0x2f,0x3c,0xcb,0x5a,0x36,0x53,0x4f,0x05,0xb3, + 0x43,0xdc,0x80,0x3e,0x06,0x27,0xfd,0x62,0x31,0x5d,0xf6,0xf8,0xdd,0x04,0x59,0xf6, + 0xc3,0x2e,0x14,0x69,0x40,0xf2,0x3a,0x5a,0xdb,0x85,0x63,0x85,0xfe,0xb7,0xb5,0x8c, + 0xc0,0xbe,0xdf,0x9f,0x68,0xeb,0x72,0x39,0xda,0xbf,0x02,0x0c,0x00,0x77,0xb7,0x6d, + 0x54,0xa0,0x98,0x91,0xe4,0xd6,0x26,0x2a,0x1c,0xd4,0x70,0x89,0xcd,0x16,0xb1,0x61, + 0xa3,0x51,0x4f,0xed,0x22,0xfc,0x19,0x7d,0xe9,0xf4,0x31,0xa7,0x56,0x48,0x99,0xa8, + 0xac,0xef,0x62,0xc0,0x10,0x89,0xde,0x2e,0xfe,0x54,0x6d,0x51,0x18,0x03,0x1b,0x05, + 0x41,0x77,0x19,0x61,0x1c,0xd6,0xc1,0x09,0x45,0xdb,0x3c,0x56,0xe8,0x7f,0xf2,0x5c, + 0xc1,0x34,0xb1,0xee,0xe5,0x83,0x03,0x70,0x7e,0x7c,0xaa,0x84,0x51,0xcd,0x42,0x80, + 0xcc,0xfb,0x15,0x16,0xd2,0xb6,0xb4,0x27,0x76,0xb0,0x88,0x50,0xc4,0x6d,0xdd,0xd7, + 0xe1,0x83,0x7a,0x2c,0x62,0x2b,0x10,0xd3,0x6e,0xc9,0x9d,0x1b,0x6d,0x7d,0x04,0x2c, + 0x35,0xc8,0xfc,0x06,0x4b,0xb1,0x15,0x7b,0x18,0x2b,0xae,0xcf,0xe1,0x79,0xbb,0x2d, + 0x45,0x1d,0x1e,0x85,0x8e,0x64,0x79,0x2c,0x8d,0x64,0x88,0xd9,0x5d,0x99,0x66,0x96, + 0x62,0x90,0xdf,0xe8,0xf7,0x70,0xb7,0x42,0xfb,0x97,0xa4,0xea,0x75,0x59,0xca,0x24, + 0x9e,0x33,0x61,0x38,0xfd,0x1d,0x4d,0x97,0x41,0x3d,0x3a,0xff,0x39,0xe0,0xfc,0x7a, + 0x9e,0xcc,0xd8,0xfe,0x77,0x8a,0x50,0x06,0x77,0xef,0x37,0x81,0x31,0xbc,0x0f,0x37, + 0x9d,0xbf,0x98,0x99,0x79,0xf3,0x6c,0x9e,0x3f,0xcf,0xfb,0x8c,0x83,0xdb,0x63,0xda, + 0x38,0x37,0xb3,0xe7,0x82,0xd3,0x79,0x47,0xee,0xf2,0x79,0xcb,0xbd,0x79,0xcd,0x1b, + 0x61,0xb0,0xab,0xcf,0x0a,0x04,0x80,0xef,0x9b,0xc7,0xde,0x3e,0xec,0xef,0x37,0x5a, + 0xfd,0x18,0xf8,0xdf,0x7b,0xf0,0xe0,0xc1,0x9f,0x3e,0x78,0xf0,0xee,0xbb,0x5f,0xff, + 0xed,0xe1,0xc3,0x3f,0x12,0x19,0xe5,0x6e,0xd7,0x2e,0x33,0x05,0x80,0xcb,0x55,0xc4, + 0x3e,0x0d,0x03,0x78,0x0c,0xda,0x5b,0xf7,0x08,0x36,0x02,0x50,0x1d,0x80,0x73,0x80, + 0x3d,0xdc,0xce,0xef,0x72,0x0d,0xaa,0x01,0xc8,0x02,0xd6,0xd6,0x72,0x6b,0x37,0x97, + 0xf5,0x0a,0xe2,0x32,0xd8,0x68,0x64,0x91,0xf0,0xbf,0x92,0x85,0x9b,0x92,0xba,0x76, + 0x0b,0x47,0x0c,0x62,0x1d,0x01,0x4f,0x32,0x22,0x65,0xf4,0x72,0xa6,0x5c,0x4f,0x35, + 0xd0,0x05,0x1e,0x74,0x56,0x1a,0x59,0x6d,0x94,0xe0,0x16,0xfd,0xec,0xc7,0x9c,0xfb, + 0x3d,0x51,0xfd,0xc8,0x6a,0xa0,0xdd,0x86,0x1a,0x40,0x66,0x54,0x4f,0x21,0xfa,0x62, + 0x20,0x69,0xba,0xc4,0x03,0x34,0x8a,0x2a,0x1b,0xb6,0xc4,0x36,0x31,0x01,0xd5,0x3f, + 0x95,0xda,0xd6,0x82,0x21,0xc3,0x27,0x46,0x7e,0xf3,0xe7,0xcf,0xc9,0xbb,0x99,0xcc, + 0x28,0xb5,0xba,0x8a,0x11,0x30,0x62,0x00,0xbf,0x15,0x6d,0x39,0xe1,0x20,0xbf,0xe3, + 0x26,0xd8,0xcd,0x60,0xdc,0x21,0xea,0xec,0x3b,0x27,0xa8,0xe2,0x7a,0xe2,0x78,0x1f, + 0xd3,0x6a,0xf6,0xa8,0x98,0x09,0x33,0x19,0x8c,0x49,0xf0,0xed,0x8e,0x00,0x4d,0x9f, + 0x2a,0xda,0xef,0xdc,0x31,0x44,0x63,0x68,0xd0,0x00,0x0e,0x95,0x5a,0x9d,0x74,0x80, + 0xb9,0x11,0xb2,0x25,0x01,0xfb,0x45,0xb5,0x72,0x19,0xb8,0x19,0x5a,0xa5,0x54,0xb0, + 0xdb,0xff,0xbf,0xf6,0xce,0x2e,0x34,0xae,0x24,0xbb,0xe3,0x6b,0x14,0x13,0x36,0x9e, + 0x61,0xc9,0x4b,0x18,0xda,0xb0,0x8d,0x92,0x6d,0xd4,0x2b,0x1b,0x13,0xed,0x83,0x76, + 0x13,0xe6,0x65,0x50,0x96,0xf5,0x86,0xa4,0x45,0xeb,0xb2,0x41,0xcd,0x2a,0x2d,0x2d, + 0x51,0xd2,0x08,0x26,0x63,0xd6,0x44,0x84,0x35,0xd1,0xae,0x48,0xf0,0x4e,0xa4,0xb8, + 0x33,0xea,0x64,0xbc,0xb1,0x89,0x97,0x30,0x61,0x24,0x7b,0xf2,0xd0,0x3d,0x44,0xa8, + 0xc7,0xac,0x5e,0xf2,0x01,0xf9,0x20,0xca,0x43,0xd2,0xc4,0xe8,0xc1,0x16,0x34,0x7a, + 0xd8,0x8e,0x5e,0x16,0x12,0x46,0xa2,0xbb,0xd3,0x71,0xea,0x9c,0xfa,0xae,0x7b,0x5b, + 0x1f,0x1e,0x4b,0xf6,0x86,0xff,0xef,0xde,0xbe,0xb7,0x6e,0xd5,0xa9,0x53,0xa7,0xea, + 0x76,0xd5,0xad,0xfb,0x55,0x57,0x2f,0xe2,0x99,0x28,0x95,0xa2,0x57,0xe9,0xea,0xaf, + 0x63,0xe7,0xb5,0x5c,0x47,0xd4,0x7f,0xfb,0x1f,0x88,0x47,0x89,0x21,0x92,0xe4,0x0f, + 0x0b,0xad,0xaf,0xaf,0x88,0xce,0x7f,0x23,0x31,0xff,0xe1,0xae,0xb3,0xe5,0xa2,0xcb, + 0xee,0xfc,0x3b,0x17,0x2f,0xce,0x51,0xf5,0x13,0x1d,0xe9,0xdf,0xfa,0xf6,0xa7,0x3e, + 0xf5,0xeb,0xa2,0x5e,0x99,0xfa,0x7f,0x9d,0xba,0xd7,0xd7,0x2f,0xbe,0x49,0x63,0x02, + 0xfc,0xe6,0xf5,0xeb,0xa3,0x6f,0xbe,0x21,0x7a,0x05,0x17,0x59,0xf6,0xe2,0xf5,0x39, + 0x55,0x3f,0xaf,0x73,0xed,0x55,0x55,0x75,0xd4,0xd4,0xdb,0xd1,0xeb,0xb6,0x82,0x3b, + 0x0e,0xcf,0xe9,0x54,0xf3,0x8b,0x36,0xd4,0xb4,0x01,0xa4,0x63,0x94,0x8c,0x90,0xdb, + 0xa3,0x2a,0x85,0x51,0x32,0x6b,0x74,0xee,0xfa,0x9c,0x3a,0xe9,0x57,0xb5,0xff,0x8e, + 0x3c,0xf4,0x8f,0x8c,0x8c,0x50,0xf5,0x7f,0xff,0xeb,0x17,0x4e,0xed,0xcd,0x3f,0x97, + 0x83,0x35,0xfe,0x0e,0xc0,0x60,0xaf,0x50,0xef,0x4c,0xa4,0xbf,0x94,0x7b,0x40,0xe7, + 0xed,0xea,0x70,0xda,0x92,0xe7,0x00,0xfc,0x24,0x00,0xb5,0x00,0x05,0xdd,0x07,0xa0, + 0xcf,0xb9,0xad,0x51,0x27,0x80,0x2e,0x05,0x0c,0xdf,0x9b,0xed,0xde,0x5f,0xe9,0x51, + 0xbd,0x14,0xa8,0x45,0x81,0xd6,0xcd,0x5c,0xf1,0xfc,0xdb,0x3c,0x9d,0xff,0x1a,0xcd, + 0x66,0x6a,0x44,0xbd,0x29,0x8e,0x21,0x20,0xd1,0x82,0x8c,0x51,0x38,0xc8,0x6a,0xc1, + 0xb7,0xdd,0x18,0x82,0xe9,0x74,0xd4,0x59,0x11,0xd5,0xbf,0x21,0xfe,0xae,0xeb,0x54, + 0x19,0x44,0x67,0xa3,0xc9,0x3d,0xdc,0x1d,0xf9,0xed,0x02,0xea,0x4e,0x0a,0x43,0x9b, + 0x1d,0xba,0x63,0xb1,0xbe,0x5e,0xef,0x46,0xbd,0x61,0x19,0xf9,0x6b,0x9e,0x4e,0xa9, + 0xee,0x5a,0x73,0xab,0x21,0x2c,0x58,0x57,0xc9,0x2b,0x0b,0xca,0x85,0x4a,0xb4,0xe4, + 0xa6,0xab,0x16,0xae,0x45,0xe7,0x0b,0xd4,0x76,0x91,0x0d,0x6c,0xb3,0x8d,0xaa,0x36, + 0x43,0x2f,0xa5,0x5c,0x2f,0x4a,0xd1,0xaa,0x56,0x29,0xb5,0xbf,0x7d,0xde,0xaa,0xf7, + 0x0b,0x49,0x79,0x9f,0xef,0xc9,0x04,0x1d,0xbd,0x9c,0x52,0x36,0x7a,0xd5,0x35,0xd3, + 0xaa,0x1c,0xee,0x56,0x1a,0x3a,0x42,0xd9,0xc9,0x5f,0xb3,0x5b,0x3c,0xef,0x25,0x2d, + 0x16,0xed,0x68,0xbd,0xc1,0x99,0x31,0xc6,0x97,0x8f,0x9c,0x48,0x28,0x2a,0x70,0x31, + 0x4a,0xb3,0xe9,0x37,0xbc,0x48,0x0d,0x2a,0x6b,0x8a,0x67,0xbe,0x9c,0xa0,0x57,0x79, + 0xae,0xaf,0xf7,0x7a,0xbd,0x52,0xd4,0xcd,0xf3,0x1b,0xe6,0x09,0xd9,0xd7,0xff,0x80, + 0xaf,0x9d,0x77,0x0b,0xe7,0xfc,0xdb,0x6f,0xab,0x8c,0xfc,0xbe,0x38,0x7d,0xa6,0xda, + 0x44,0x47,0x53,0xae,0xde,0x6f,0x52,0xb5,0x1a,0xfd,0x77,0x7a,0xfe,0x97,0xae,0xaa, + 0x51,0xd8,0xc5,0x5f,0xa0,0xe3,0xff,0xbf,0xc9,0x06,0xe2,0xa7,0x2f,0x4a,0x61,0xfe, + 0xc9,0xa8,0x73,0xe4,0x45,0x35,0x92,0xe7,0x51,0xa9,0xf0,0xa2,0xf6,0x1a,0xe5,0x33, + 0x74,0x25,0xa8,0x43,0x47,0x9d,0xa5,0x74,0x71,0x44,0x0e,0xbd,0x4e,0x5e,0x9c,0x8a, + 0x4c,0x46,0xeb,0xe0,0xb5,0xdc,0x1a,0xe5,0xab,0xfd,0x8f,0x4d,0xe5,0xe7,0x83,0xbf, + 0xa8,0xfd,0x23,0x92,0xed,0xf7,0xc5,0xf1,0xff,0x94,0xef,0xfd,0x69,0xb2,0xf7,0x1e, + 0xde,0x5d,0xaa,0xf2,0x25,0x40,0x1e,0x08,0x58,0x9d,0x01,0xa8,0x8b,0x80,0xd4,0x00, + 0xa8,0x2e,0x40,0xa5,0x9e,0xe5,0xcb,0x00,0xb2,0x05,0xa0,0x0b,0x01,0x6b,0x6b,0xaf, + 0x70,0x1b,0xb0,0x96,0x6b,0xae,0xf7,0xd6,0x7b,0x85,0xc2,0x3a,0xcd,0x62,0x92,0x73, + 0x6f,0xbf,0x3b,0x7b,0xed,0xfc,0xb5,0xf3,0x1f,0x7e,0xf8,0xe1,0xf9,0x6b,0xce,0x74, + 0xfe,0xda,0x60,0xb4,0x2e,0xfe,0xa1,0xe2,0x8f,0xd7,0x63,0xd1,0x5e,0x41,0xce,0x85, + 0x6e,0xe9,0xda,0xb5,0xf3,0xd7,0x02,0x61,0x5a,0x7c,0x78,0x6d,0xad,0x14,0xe5,0xca, + 0x2b,0x0d,0x71,0x28,0xa4,0x16,0x80,0x8f,0xdc,0x15,0xd1,0x7b,0x6f,0x36,0xb7,0xb6, + 0xd2,0x5b,0x69,0x71,0x1e,0xb9,0xd5,0x6c,0xde,0xef,0xb0,0x91,0xe2,0x7f,0xd5,0x6c, + 0xe5,0xf2,0x1c,0xf7,0x7c,0x82,0x3e,0x31,0x0f,0x37,0xd3,0xa4,0x87,0x0d,0x60,0x7a, + 0x3c,0xad,0x97,0xa2,0x73,0x1f,0x9e,0xf7,0xd3,0x76,0x27,0xca,0x47,0xa1,0x2b,0xdb, + 0x2e,0x1d,0x53,0x45,0x75,0x3c,0xa4,0x97,0xe3,0xdb,0x5b,0x37,0x8b,0x7a,0xd4,0x96, + 0x6a,0x92,0xa7,0x04,0xaf,0x0f,0x7b,0x51,0x4f,0xd8,0xba,0xbe,0xe2,0x98,0x49,0xa5, + 0x56,0x88,0xd6,0x63,0x71,0x59,0x71,0xb1,0xdb,0xe1,0x32,0xd2,0x76,0xb0,0xb4,0x28, + 0xdf,0x4e,0x34,0xab,0x13,0x36,0x06,0xb4,0xa3,0xf2,0x14,0xcb,0xf6,0x1c,0xdb,0x79, + 0x2e,0xac,0xbb,0x79,0x30,0x79,0x51,0x89,0x47,0x59,0xba,0x07,0xec,0x24,0x3e,0x9c, + 0xde,0x9a,0x52,0x89,0xae,0x9b,0x98,0x56,0x83,0x53,0x4c,0x72,0x55,0x50,0x5e,0x82, + 0x72,0xae,0x95,0x9e,0x66,0x6d,0xfd,0x4a,0xa5,0xdf,0x24,0xb2,0xf1,0xf0,0x4d,0x7a, + 0x59,0x66,0x8e,0x7e,0x8f,0xe7,0x46,0x7f,0x5b,0x9c,0xde,0xbf,0x33,0x3a,0xfa,0x78, + 0x74,0xee,0x67,0xe9,0x92,0xdf,0x63,0x7e,0x9c,0x6e,0x6e,0xf4,0x27,0x3e,0xa2,0xd3, + 0xfe,0xb9,0xc7,0xa3,0xbf,0x4e,0xed,0xc0,0xe8,0x63,0x2d,0x2e,0x7e,0x8f,0x65,0xbd, + 0x95,0x2e,0xe5,0x3b,0x2a,0x83,0xd5,0x82,0xb6,0x84,0x4a,0x19,0x22,0x9d,0xde,0x6c, + 0x84,0xe7,0xf4,0xa6,0xf2,0x14,0x8b,0xc7,0xba,0x55,0x18,0x9d,0x53,0xc2,0x32,0xfc, + 0xf1,0xdc,0x53,0xe7,0xc8,0xaf,0x7b,0xfe,0xbb,0x54,0xfd,0x2f,0x6c,0x6f,0x8b,0xe3, + 0xff,0xc8,0xfb,0x5f,0x3f,0xf5,0x7b,0x7f,0x8a,0xd6,0xb4,0xe8,0x00,0x2c,0xb5,0xf7, + 0xe4,0x97,0x80,0xed,0x4d,0x40,0xdb,0x02,0xec,0x70,0xb7,0x9a,0x4e,0x02,0xea,0x74, + 0x68,0x15,0x7d,0x80,0xc1,0x5b,0xb5,0x5a,0x95,0x7b,0x01,0xd4,0x0d,0x98,0x5d,0xca, + 0x6d,0xad,0x3b,0xc8,0x1d,0x2c,0xf6,0x74,0xe5,0xe0,0xd2,0xb5,0xe1,0x7b,0xc3,0xf4, + 0x13,0x8b,0x6b,0x74,0xbd,0x60,0x98,0x57,0x7b,0x51,0x99,0xaa,0x7f,0x4f,0xfd,0x03, + 0xcc,0x9f,0x25,0xd7,0x29,0x0a,0xd1,0x7b,0x2c,0x7c,0x8f,0xa3,0xc9,0x88,0xf7,0x84, + 0xd7,0xec,0x54,0x37,0x6a,0x16,0x74,0xa5,0xa5,0x63,0x88,0xe8,0x04,0x88,0x6e,0xb0, + 0x38,0x77,0x15,0xd3,0x7e,0x47,0x1c,0xf8,0x85,0x7d,0xe2,0x34,0xa5,0x50,0xa8,0x74, + 0xa3,0xca,0x25,0x19,0x97,0x74,0x49,0x15,0xfc,0x13,0x8a,0x68,0xba,0x56,0xec,0xe4, + 0x28,0xfd,0x15,0xf5,0xa7,0xec,0xe9,0x75,0xb6,0x95,0x57,0x62,0xd7,0xa4,0xa0,0x36, + 0x86,0x97,0xac,0x6a,0x25,0x5a,0xa7,0x88,0x14,0xc5,0xb1,0x5e,0x67,0x45,0xb2,0x2e, + 0x03,0xad,0x72,0xb3,0xc8,0x46,0x7b,0x52,0xcd,0x3d,0x47,0xab,0xdd,0x0a,0x7f,0xb4, + 0x7c,0xf5,0x60,0x9d,0xd3,0xf3,0x12,0x12,0x05,0xdc,0xcd,0x0e,0xcb,0x42,0xba,0xa6, + 0xed,0xa5,0xa2,0xbd,0x77,0xaf,0x98,0x6b,0x8a,0xc2,0x5d,0x5f,0xf1,0x8d,0x5a,0x17, + 0x47,0xd9,0x69,0xca,0x99,0x14,0x53,0xd1,0x44,0xfd,0xf7,0x75,0xeb,0x6c,0x19,0x97, + 0x3f,0x29,0xbf,0xf5,0x4f,0x97,0xec,0xce,0x61,0x2b,0x8b,0xe9,0x34,0xed,0xd1,0x15, + 0x47,0xc1,0xba,0xa3,0xc1,0x4d,0xc1,0xd5,0x25,0x8e,0xfd,0xe9,0x54,0xb7,0x30,0xab, + 0x76,0x4b,0x72,0x01,0xf0,0x7f,0xe1,0xda,0xb0,0xb3,0x63,0xb4,0xff,0xf0,0xf0,0x77, + 0xae,0x5c,0x11,0x35,0x49,0x1c,0x4a,0xe9,0xa5,0x99,0x2b,0xff,0x45,0xb5,0x7e,0xf4, + 0xca,0xdc,0x95,0xb9,0xef,0xd1,0xf3,0x3f,0xef,0xbe,0xf9,0xee,0xbb,0xef,0xbe,0xf9, + 0x5b,0xff,0xf5,0x0b,0x74,0x31,0xf0,0x57,0xe6,0x1e,0x53,0xff,0xe0,0x8d,0x37,0x45, + 0x30,0xd5,0xbf,0xb9,0x2b,0x4f,0xb9,0x16,0xd2,0x61,0xf8,0xa9,0x88,0x21,0x9c,0xa4, + 0x82,0xea,0xa5,0x58,0x3e,0x56,0x42,0x14,0x42,0xd7,0xe6,0x85,0x38,0xbb,0x95,0xd3, + 0x99,0x59,0x92,0xd7,0x4f,0xd5,0xe6,0x9c,0x8c,0x28,0xa2,0x89,0x6d,0xd1,0xc5,0x1f, + 0xbd,0xc2,0x2f,0xf4,0xcd,0x49,0x55,0xaa,0xde,0xcb,0x0b,0x7e,0xfa,0x82,0xff,0x0c, + 0x1f,0xfb,0xb7,0x05,0xe3,0xdb,0x17,0xc6,0xb7,0x47,0xde,0x7f,0xff,0xeb,0xa7,0x7e, + 0xef,0x4f,0xd3,0x19,0x1e,0xbe,0x2b,0xbf,0x04,0x54,0xa7,0xab,0xda,0x3b,0xdd,0x83, + 0x96,0xb9,0xb7,0x2d,0xdf,0x08,0xee,0xaa,0x16,0x80,0xfa,0xd6,0x59,0xd9,0x02,0x50, + 0x27,0xa0,0x4d,0xbd,0x80,0x4b,0xe2,0x4c,0x60,0x7a,0x31,0x57,0x28,0x73,0x67,0x5e, + 0x1d,0xfe,0x55,0x3b,0x30,0x10,0xb5,0x8b,0x0f,0x69,0xfa,0x9d,0x87,0x82,0x62,0x91, + 0x66,0xb1,0x1e,0x2e,0xe6,0xa3,0xba,0x3d,0x4e,0xd2,0x8a,0x5a,0x8b,0x42,0xaf,0xb0, + 0xd8,0x9c,0x25,0x01,0x31,0xe9,0x85,0x8a,0x47,0xeb,0xbb,0xab,0xa5,0x56,0xb4,0x5f, + 0xa0,0x3f,0x0e,0x1d,0x82,0xe8,0x4c,0x23,0x2b,0x4f,0x5c,0xe9,0x54,0x92,0xc8,0x66, + 0xc9,0xb3,0xd4,0x4d,0xe5,0xa6,0x66,0x8b,0x32,0xae,0x52,0xa4,0x94,0x15,0xd5,0xf4, + 0xb0,0xb8,0xbf,0xa3,0x8e,0xcc,0xde,0xd1,0x49,0x54,0xcf,0xa9,0x87,0x0f,0x8d,0x50, + 0x18,0x4d,0x38,0x87,0x8b,0xaf,0x46,0x05,0x7d,0xb8,0xec,0x05,0xc7,0xc8,0xe0,0xf8, + 0x5f,0x88,0x1f,0xff,0xd7,0xcb,0xa9,0x57,0x13,0x54,0xfb,0x59,0xb6,0xc9,0x71,0xd6, + 0xa7,0xa2,0xac,0x31,0xd2,0x4d,0xa8,0xdb,0x29,0xda,0xd8,0x45,0x53,0x4c,0xc5,0xd9, + 0x9d,0xb4,0x96,0x2a,0xb8,0x56,0x95,0x52,0x55,0x99,0xb7,0x61,0x1b,0xad,0x9d,0xca, + 0xda,0x12,0x70,0xb3,0x14,0xcb,0x9b,0x3f,0xe5,0x9a,0x77,0x79,0x47,0x2a,0x0b,0x8a, + 0xc3,0xaf,0xa4,0x73,0xa6,0x7b,0xe0,0x76,0x81,0xfa,0x1c,0xff,0x65,0x2f,0xa2,0x4c, + 0x2f,0x0c,0x74,0x4b,0xab,0x45,0x95,0xef,0x62,0x42,0x09,0xf8,0x7b,0xc3,0xf1,0xe4, + 0x7f,0xd2,0x9f,0x8c,0x9a,0xea,0x24,0x6a,0xdf,0xd3,0x5f,0xf9,0xdd,0x4f,0x7d,0xea, + 0xf3,0xef,0xd0,0x06,0xd5,0xff,0x6f,0xff,0xe8,0xa3,0x1f,0xbd,0xf1,0xc6,0x47,0x3c, + 0x18,0xf8,0xb7,0xbf,0xf7,0xf4,0xca,0x53,0xea,0x14,0xfc,0x93,0x13,0xc1,0xc2,0x4f, + 0xdd,0x3e,0x95,0x2b,0x2f,0x40,0x6d,0x78,0x5e,0x49,0x3c,0xbd,0x62,0xa2,0xfa,0x7a, + 0xe3,0x72,0xa6,0xe6,0xfb,0x95,0x7f,0x64,0x7b,0x64,0x7c,0x7b,0x9c,0xe7,0x0b,0xe2, + 0xf0,0x9f,0x39,0xab,0xea,0x7f,0x35,0x55,0xe3,0x87,0x80,0x6a,0x8d,0x5e,0xb6,0xde, + 0xb9,0x99,0x36,0xef,0x01,0x98,0x16,0xa0,0xa5,0xae,0xac,0xf1,0xf3,0xc0,0xb2,0x05, + 0x10,0x5d,0xe0,0xc6,0xa0,0xe8,0x05,0xb4,0xdb,0xd5,0xea,0xf4,0x74,0x35,0xdd,0x6d, + 0xd2,0x11,0x98,0xb9,0xcf,0xdf,0xa1,0xed,0x54,0xc4,0x2f,0x9d,0x6a,0xcf,0x4a,0xc4, + 0x79,0x02,0x4d,0x02,0xb1,0x7a,0x65,0xf6,0x56,0xd4,0x1c,0xa8,0x74,0x2a,0x2c,0xa4, + 0x21,0xf7,0x4e,0x7a,0x4d,0x84,0xcf,0x4a,0x31,0x9a,0x8a,0x14,0xb9,0xa8,0x22,0xcf, + 0x2e,0xed,0x35,0x53,0xd1,0xcd,0x92,0x3a,0xa1,0x2c,0xab,0x6f,0x8a,0xd3,0x55,0xc4, + 0x6c,0xbd,0xcc,0xdf,0xa8,0x2e,0x94,0x3a,0xb9,0x54,0xb7,0x3c,0x3d,0xfb,0xca,0x5d, + 0x95,0xa0,0x56,0xa6,0x66,0x65,0xc4,0x6c,0x27,0x52,0x49,0xfa,0x34,0x53,0x3d,0x13, + 0x4d,0x99,0xe0,0x29,0x12,0xb6,0xaf,0xa4,0xf6,0x4d,0x44,0x4f,0x41,0x4c,0x9b,0xf2, + 0x18,0x70,0x16,0x03,0xfb,0xa9,0xf5,0x59,0x5d,0x0e,0x4e,0x91,0x98,0xf4,0xe4,0x7c, + 0x57,0xc1,0x69,0x4e,0x45,0xcd,0xca,0x80,0xd5,0x5e,0x91,0x8a,0x3a,0x9d,0x83,0xce, + 0x9a,0xb1,0x52,0x8b,0x93,0xee,0xb5,0x74,0x57,0x48,0x54,0x94,0x6c,0x85,0xa4,0x39, + 0xfe,0x56,0x2a,0x4f,0xf6,0x7b,0x05,0xdc,0x4e,0xa5,0x79,0x47,0x28,0xf3,0x2a,0xa1, + 0xed,0x7d,0xb2,0xd4,0xe9,0xa6,0xd7,0xdc,0x54,0x85,0xca,0x66,0xd7,0xa6,0x79,0x34, + 0x03,0x03,0x9d,0x66,0x3a,0x27,0xfe,0x65,0x8b,0x85,0xea,0x1a,0x17,0xec,0x5d,0x5b, + 0x2c,0x5e,0xfe,0x9d,0x7d,0x37,0x7b,0xf7,0x15,0x31,0xd1,0x82,0xb8,0xfb,0xca,0xec, + 0x2b,0x5f,0xf9,0xdc,0x9d,0x2b,0x3c,0xbd,0xc7,0xcb,0x3b,0x57,0xfe,0x47,0xd4,0xf0, + 0xcf,0xbe,0x25,0xdc,0xdf,0xf3,0x9f,0xff,0xf9,0xfc,0x37,0x1f,0x5f,0xb9,0xf3,0x8e, + 0x38,0x0d,0xf8,0xd1,0xbb,0x4f,0xa9,0xde,0x91,0xec,0x9d,0xf7,0xae,0xdc,0x79,0xaa, + 0x26,0xda,0x7e,0x8f,0x7f,0xe4,0x27,0xd6,0x57,0x94,0x42,0xde,0x96,0x4b,0x39,0xbd, + 0x27,0x64,0xe2,0x4b,0x11,0x4f,0x49,0xab,0x88,0x4f,0xb5,0x53,0x2b,0x72,0x2a,0xfd, + 0x1d,0x75,0xb5,0x4f,0x76,0xfb,0x77,0x65,0xdd,0x17,0x07,0xfe,0xf1,0xcc,0xb8,0x98, + 0x6f,0x73,0xfd,0xbf,0x70,0x06,0xf7,0xfe,0x34,0xb9,0xb5,0x7b,0xe2,0x0c,0xa0,0x46, + 0xf7,0x00,0xf8,0x8e,0xb8,0x7a,0x11,0xd0,0x3c,0xab,0x45,0x37,0x02,0xf8,0x69,0x40, + 0xd1,0x05,0x50,0x67,0x01,0x74,0x14,0xe6,0x5e,0x80,0xe8,0x06,0x88,0x53,0x81,0x7d, + 0xba,0x65,0xd0,0x12,0x33,0x9f,0x31,0xa4,0xe4,0x38,0x02,0x62,0xea,0xe6,0x97,0xd6, + 0x96,0xc4,0x39,0x02,0x2f,0x1d,0x6a,0x5d,0x7e,0xc2,0x20,0x4a,0xc9,0x2b,0xf7,0x6a, + 0xdc,0x01,0x11,0xbb,0x79,0x49,0x4b,0xae,0x39,0x4b,0xb9,0x5e,0x13,0x8b,0xd5,0xa9, + 0x66,0xaa,0x95,0x6b,0xd6,0x65,0xdd,0x17,0x86,0xc8,0xea,0x2f,0x7e,0xf4,0x75,0xf9, + 0x3a,0x7d,0xd1,0xaf,0x5b,0xaa,0x4d,0x7b,0x3a,0x94,0x73,0x4d,0x69,0x91,0x9b,0x65, + 0x4a,0x96,0x2e,0x71,0xb6,0xa4,0x05,0xea,0x1e,0x42,0x14,0xf5,0x9c,0xb4,0x55,0x14, + 0x47,0x8f,0x70,0x0d,0x72,0xd6,0xf4,0x42,0x47,0x34,0x1b,0x8e,0xb2,0x94,0x74,0xb4, + 0xdc,0x45,0x2a,0xea,0x69,0x95,0x6b,0x4b,0x7e,0x5e,0xe3,0xc5,0x24,0xc5,0x06,0x23, + 0xcf,0x44,0xf9,0xa3,0x92,0x1b,0x30,0x22,0x46,0x9c,0x37,0x3a,0xa6,0xfc,0x75,0xb9, + 0xaa,0x82,0xce,0xab,0x24,0xac,0x05,0xd5,0x9c,0x2c,0x85,0x48,0x16,0x44,0xcb,0xb1, + 0xdf,0xe6,0xaa,0xe5,0xa5,0x2c,0xa7,0x66,0x68,0x67,0x29,0xe5,0x14,0x89,0x96,0x76, + 0xca,0xd5,0x57,0x43,0x06,0x75,0x73,0x9d,0x42,0x7e,0xd5,0xec,0x95,0x35,0x27,0xcf, + 0x61,0x11,0x04,0xe5,0x23,0x1c,0x32,0xa7,0xdf,0x7d,0xef,0x8e,0xcf,0x5b,0x5f,0xa0, + 0x43,0xbc,0xa8,0x8f,0xdf,0xf9,0x82,0xe0,0x83,0x2f,0x7c,0xf0,0x01,0x2d,0x3f,0xfb, + 0xcd,0x9f,0x13,0x95,0xfa,0x73,0x7f,0x29,0xc2,0xfe,0xec,0xca,0x9d,0x24,0x42,0x3d, + 0xa7,0x89,0xad,0xfa,0x33,0x54,0xfb,0xa9,0xfa,0x8f,0x8f,0x8c,0x4b,0x32,0xe3,0x1b, + 0x5c,0xfd,0xff,0xfb,0x4c,0xee,0xfd,0x69,0xf6,0x8b,0x7c,0x06,0xb0,0xb7,0x52,0x28, + 0x57,0xe8,0x1a,0x20,0x3d,0x5f,0xe7,0xf4,0x00,0x5a,0xf2,0x3a,0x20,0xb5,0x00,0x8b, + 0xdc,0x02,0x0c,0xd0,0x79,0xb6,0xe8,0x05,0xaf,0x70,0x13,0x30,0xb8,0xb7,0xd7,0x10, + 0xae,0x29,0xe1,0x9e,0x12,0x93,0x60,0x70,0x50,0xcc,0xcc,0x2a,0x0f,0x23,0xb7,0xaa, + 0x07,0x93,0x33,0x9b,0x4f,0x28,0xb0,0x21,0xc5,0x1a,0x4a,0x98,0x54,0xd5,0x58,0x62, + 0x95,0x7e,0x4e,0x84,0x69,0xe3,0x3b,0xbd,0x5a,0x9d,0xea,0x88,0xc6,0xa3,0x9b,0xee, + 0x0c,0x94,0xe4,0x4d,0xab,0xba,0xba,0x87,0x58,0x69,0x2e,0x8a,0xbf,0x72,0x3a,0x9b, + 0x37,0xc3,0xd4,0xad,0x6a,0x1d,0x62,0xae,0xb2,0x0e,0xe1,0xac,0x4a,0xd5,0xf4,0x38, + 0x71,0x23,0x2f,0x2c,0xd8,0x13,0xa9,0xef,0x49,0x53,0xf6,0x84,0x0d,0x7b,0x24,0x58, + 0x95,0x56,0xea,0x38,0xab,0xc6,0x6e,0x36,0x60,0xcf,0x58,0x3e,0x68,0xb3,0xca,0x0e, + 0xa1,0xcc,0x4c,0x83,0x7b,0xac,0x4f,0x06,0x52,0x22,0x62,0xc9,0x11,0xaa,0x46,0x77, + 0x55,0x9a,0x46,0x8e,0x69,0xb7,0x94,0x94,0x5b,0x26,0x27,0x42,0xf7,0x54,0x5c,0x9b, + 0xcc,0x20,0x2b,0xac,0xad,0x4e,0xbb,0xf6,0xa9,0x42,0x5b,0x5d,0xa5,0xbc,0xed,0xa9, + 0x1d,0x20,0x92,0x6e,0x0c,0x2a,0x05,0xf9,0xea,0xb4,0x91,0x53,0xd3,0x6a,0x9e,0x43, + 0xa5,0x7e,0xf1,0x23,0xbd,0x0d,0x55,0x2a,0x7a,0x0f,0x35,0x54,0x0e,0x1a,0x52,0x90, + 0x33,0xd7,0x68,0x3b,0x5a,0x98,0x5a,0xbe,0xa1,0x22,0x88,0x83,0x82,0x13,0x51,0x2a, + 0x6f,0xe8,0x02,0x50,0x1a,0xc4,0x76,0x3e,0x5f,0x5d,0x5d,0x9d,0x76,0x4c,0xd7,0x3b, + 0xbd,0xea,0xe4,0x7f,0x55,0xfe,0x17,0xec,0x9f,0xc0,0xfa,0x8a,0xe9,0x8b,0xef,0x5d, + 0x96,0xdc,0x31,0xf3,0x3b,0x74,0xab,0xff,0x7f,0x7e,0xf9,0xf2,0x2f,0xff,0xf0,0x87, + 0x6f,0x7d,0xe6,0xad,0x1f,0x3e,0x16,0xab,0x1f,0x7e,0xe6,0x33,0x54,0xdd,0xde,0xfa, + 0x6d,0xee,0x1b,0xb0,0xf4,0x9d,0xcb,0x47,0xcc,0x97,0xad,0x62,0x82,0x1e,0xc8,0x97, + 0xee,0x64,0xe9,0x3b,0x8e,0x6c,0xe0,0xbc,0xac,0x13,0xf4,0x98,0x91,0xf7,0xf9,0xf9, + 0x5a,0x3f,0x75,0xf9,0x05,0x1b,0x99,0x0d,0x31,0x8b,0x26,0x60,0x7b,0xfb,0xc2,0xee, + 0x99,0x56,0xff,0xab,0x57,0xb3,0x0f,0xc5,0x19,0xc0,0x6a,0x6d,0x70,0x45,0x1c,0x42, + 0xe9,0x1a,0xe0,0x0e,0x37,0x00,0xba,0x0b,0xd0,0x32,0x77,0x02,0x72,0xd4,0x02,0xdc, + 0xdc,0xdf,0xe7,0xeb,0xec,0x74,0xa1,0x5d,0x75,0x03,0xa8,0x23,0xb0,0x77,0x2b,0x9f, + 0xa7,0xce,0x80,0xa4,0xdd,0x6e,0xd3,0xcf,0x2c,0x6a,0x3c,0xc9,0x8d,0x9a,0xf2,0xd1, + 0xc1,0xee,0xba,0xea,0x47,0xf3,0x02,0x55,0x78,0xad,0x51,0x6e,0x1e,0xf0,0x68,0x51, + 0xf4,0x74,0xf2,0x7e,0x53,0x40,0x4f,0x04,0x0b,0x9f,0xdc,0xc0,0xca,0x9e,0x14,0x57, + 0x51,0x6a,0xb5,0x20,0xbe,0x9b,0x4c,0xad,0xea,0x24,0xa0,0x23,0x05,0xb2,0x35,0x2f, + 0x92,0x6f,0x50,0xad,0x1d,0xdb,0xac,0x39,0x3a,0x6a,0x6e,0xb6,0x3d,0xb5,0xb5,0xb8, + 0x5b,0x47,0xd6,0x45,0x63,0x8b,0x4d,0xfb,0xdb,0xd0,0x43,0xcc,0x65,0x99,0x6a,0x10, + 0xdf,0x4a,0x56,0xdd,0xa2,0x77,0xa2,0x54,0x13,0x8a,0xc8,0xec,0xaf,0x24,0x4c,0xb1, + 0x3a,0xe9,0x78,0x76,0x27,0xe4,0xd5,0x0f,0x72,0xf2,0x11,0xb7,0xd3,0x13,0xb6,0x26, + 0xd7,0x82,0xd0,0x5b,0xff,0x32,0x73,0x39,0xe4,0xb5,0x9f,0xa2,0x93,0xfd,0x3f,0xfb, + 0x8c,0xaa,0x63,0x7c,0x8c,0xe5,0xe9,0x73,0x9f,0x15,0x01,0x1f,0xfd,0x29,0x6f,0xc4, + 0xa3,0xf5,0x25,0x14,0x9d,0x49,0x9a,0xe5,0x6a,0xc6,0x4a,0xcf,0x84,0x91,0x9c,0x49, + 0xa4,0xbe,0x4b,0x75,0x9f,0xbb,0xfd,0x74,0xc1,0x8f,0x0e,0xfb,0x1b,0x1b,0xb2,0xfa, + 0x67,0xc6,0x33,0xb7,0xb7,0x2f,0xbc,0x9f,0x39,0x93,0x5b,0xff,0x96,0x8f,0xa7,0x86, + 0x8b,0xb3,0x3c,0xd4,0x76,0xa1,0x5e,0xda,0x6f,0x2e,0x2e,0xca,0x53,0x00,0xe7,0x1c, + 0x80,0xfb,0xb2,0x0f,0xf8,0x42,0xa0,0x38,0x0d,0xa0,0xdb,0xec,0x15,0xbe,0xda,0x4e, + 0x97,0xfc,0xe8,0xf2,0xb4,0x38,0xfe,0x37,0x56,0xa8,0x59,0xe7,0x03,0x07,0x1f,0xfd, + 0x08,0xeb,0x32,0xe4,0xf7,0xf6,0x9e,0xb0,0xe3,0x89,0xf6,0x79,0xe2,0x86,0x1d,0x83, + 0x27,0x7b,0x83,0x53,0xeb,0xe6,0x0d,0x1c,0xb9,0x38,0xc8,0xed,0xd7,0x57,0x1a,0xa1, + 0x64,0x7e,0x30,0x29,0x7e,0xa2,0xca,0x44,0x7b,0xfa,0x0b,0xc7,0xb6,0x93,0x23,0x29, + 0xbd,0x4f,0x62,0xbe,0x49,0x89,0x25,0xe5,0xfe,0x09,0xe7,0x60,0xd0,0x4b,0xe6,0xf0, + 0xf2,0x8a,0x65,0x39,0x48,0xdc,0x8f,0xf3,0x24,0x3f,0xd8,0xa7,0x8c,0xac,0xdc,0x2d, + 0x67,0x19,0xb7,0xcd,0x13,0xf6,0xb2,0x75,0xcb,0xf1,0x92,0xb2,0x56,0xe7,0x93,0x3c, + 0x05,0x1c,0x67,0x7f,0xe7,0x63,0x36,0xdf,0xe2,0xcd,0xc1,0xc1,0x1f,0x50,0x35,0xe2, + 0xaa,0x64,0x99,0xf9,0xc7,0xdf,0xa1,0xf3,0xfd,0x2f,0x7f,0x8e,0x0e,0xb0,0x33,0x2a, + 0x70,0xe6,0xf2,0x6b,0xdf,0xa1,0xce,0xff,0x47,0xff,0x31,0x13,0x8b,0xd0,0x8f,0x50, + 0xaf,0x5e,0xce,0xb8,0xce,0x5d,0xab,0xcf,0xac,0x66,0xd4,0xd2,0x4e,0xbe,0x36,0x7d, + 0x8b,0x5f,0x5e,0xec,0x17,0x55,0x7f,0x9c,0x2a,0x7f,0x66,0x79,0x7e,0x39,0x33,0x2f, + 0xd6,0xd4,0xfd,0xbf,0x7d,0x86,0x27,0xff,0x92,0x54,0x7e,0x98,0x2e,0x01,0xd4,0xe8, + 0xf9,0xfa,0x0a,0xbd,0x09,0xa4,0x07,0x03,0xb2,0x17,0x01,0xd4,0x4b,0x81,0xea,0x4a, + 0xe0,0x96,0x38,0xf2,0x56,0x54,0x1b,0x50,0xa6,0x73,0x01,0xbe,0xac,0xbb,0x42,0x77, + 0xaa,0xc5,0xb9,0x80,0x98,0x78,0xa1,0x1c,0xb4,0x66,0xb4,0xe7,0x14,0xdd,0xc8,0x57, + 0xae,0x29,0x19,0xb8,0xa2,0xb6,0xcd,0x52,0xfb,0xe9,0x10,0x8e,0xa5,0x82,0xe8,0x74, + 0x63,0xa5,0xd7,0x2b,0x67,0x4b,0xa5,0x81,0x81,0x52,0x29,0x5b,0x28,0xf4,0x56,0x5e, + 0xd5,0x51,0x8d,0x16,0xa3,0xc9,0xd1,0x60,0xbc,0xa7,0x6c,0x02,0x76,0x8b,0x5b,0x31, + 0xad,0xc4,0x11,0x77,0x32,0xe0,0x84,0xba,0x86,0x9a,0x84,0x9d,0x85,0x93,0x8a,0x6b, + 0xc6,0xd4,0x94,0x67,0x88,0xcc,0x94,0xab,0x63,0x65,0xca,0xd7,0x3e,0x15,0x2a,0xd3, + 0x45,0xe8,0x18,0x67,0xb3,0xd8,0x50,0xc5,0xbb,0x12,0xa4,0x4e,0x8b,0xc6,0x54,0x58, + 0x0e,0x2b,0x3a,0xfd,0x84,0x62,0xb2,0x16,0xab,0xdd,0xe5,0xef,0x90,0x70,0x27,0x79, + 0x65,0x6a,0xa3,0xd9,0xe2,0x8b,0xed,0xef,0x86,0x36,0xe3,0x55,0x27,0x41,0x27,0x71, + 0x6f,0x0f,0x78,0x7b,0x83,0x16,0x3f,0x18,0x19,0xd1,0x95,0xc9,0xb0,0xbb,0x3d,0xf2, + 0xfd,0x6f,0xd2,0x07,0x04,0x3f,0xfa,0xeb,0x3f,0x9f,0x61,0x0f,0x9a,0x5f,0xfb,0xee, + 0x97,0x7f,0x49,0x56,0x7f,0xe5,0x75,0x0c,0xb6,0x77,0x8f,0x2d,0x7a,0x02,0xb6,0x69, + 0xe2,0x9a,0x7f,0x5b,0x9e,0xed,0xf3,0x81,0x7f,0x79,0x7e,0x9e,0x67,0x3a,0xfe,0x8b, + 0xc3,0xff,0xf6,0x99,0x57,0x7f,0xfa,0xa2,0xd6,0xf0,0xdd,0xb5,0x4b,0xed,0x5b,0xf4, + 0x92,0x7d,0x65,0x82,0x7a,0x00,0xfc,0x2a,0x80,0xf7,0xce,0xa6,0xbc,0x17,0xc8,0x77, + 0x03,0xb9,0x0d,0x68,0x36,0xf9,0x4c,0x60,0x40,0x3e,0xc8,0x59,0x2e,0xeb,0x1b,0x80, + 0x9f,0x8c,0xde,0x31,0x7c,0xfb,0xa5,0x91,0x1c,0xf7,0x39,0xd0,0x4b,0x74,0x3e,0x27, + 0x8d,0x9f,0x58,0xca,0xc8,0x3e,0x93,0x6d,0xa7,0x56,0x68,0x9f,0x20,0xed,0x5e,0x62, + 0xa0,0xb9,0x45,0x49,0xbf,0xbf,0x1f,0x19,0x17,0x95,0x85,0x8f,0xa1,0xde,0xb4,0xfd, + 0xfe,0x57,0xf8,0x8e,0xdf,0x47,0x5f,0xfe,0x93,0x6f,0x7c,0xeb,0xbf,0xbf,0xff,0xfd, + 0x9f,0xfc,0xd3,0xaf,0xfc,0xe5,0xe7,0xc9,0xe3,0x83,0xef,0x52,0x28,0x8b,0x48,0xd1, + 0x30,0xa6,0xa3,0xc3,0x48,0x6c,0x5b,0x41,0x76,0x6f,0x4b,0x1d,0x76,0xad,0x7f,0x4a, + 0xf7,0xf8,0xb8,0xeb,0x39,0x2e,0x2b,0xbb,0x42,0xea,0xd1,0xc8,0x1e,0xff,0xb2,0xa8, + 0xfc,0x93,0x93,0x62,0x9e,0xa4,0x16,0x40,0x74,0xff,0x45,0xfb,0x70,0x46,0x0f,0xfe, + 0xf9,0xe4,0xd6,0x86,0x67,0xd7,0xa6,0xdb,0xb7,0xa6,0xd6,0x0b,0xa2,0x07,0x20,0x9f, + 0x03,0x70,0x2e,0x02,0x9a,0x93,0x00,0xba,0x19,0x48,0x6f,0x6d,0xf2,0x79,0x00,0xf5, + 0x02,0xe8,0xbe,0x9f,0x68,0x04,0x2a,0xf2,0x5a,0x5c,0x56,0x5e,0x92,0x2f,0x8b,0x5e, + 0x01,0xb5,0x09,0xb4,0x12,0x1e,0xe5,0xac,0x72,0xd1,0x8a,0xb7,0x79,0x6d,0xdc,0x75, + 0xe9,0x2e,0x93,0xab,0x6e,0x5c,0x1c,0x85,0xb6,0xe5,0xdd,0x3d,0xbe,0xc1,0x57,0xd7, + 0xf1,0xca,0xf2,0x86,0x9f,0x54,0x4b,0xbe,0xf2,0xc7,0x4e,0xa5,0x57,0x2b,0x95,0x0e, + 0xed,0xd4,0xa9,0xd6,0xb3,0x3a,0xba,0x4c,0x81,0x6e,0x25,0x2a,0x47,0xd9,0x58,0xae, + 0x75,0xd5,0xcb,0x3a,0x29,0x65,0x97,0x34,0x4c,0x7b,0xb0,0x09,0xd2,0xc0,0xb2,0x2b, + 0x56,0x37,0xfa,0x74,0xfe,0xb2,0x32,0x9d,0xba,0x4d,0x42,0x9a,0xa7,0xe2,0xd6,0x95, + 0x89,0xca,0x47,0xfe,0xca,0xda,0x48,0xb3,0x50,0xc5,0x9b,0x75,0xf3,0x5a,0x77,0xec, + 0x55,0x92,0xb2,0xb4,0xf4,0x0e,0x90,0xdb,0x59,0x5d,0x2c,0x65,0x9d,0xc1,0xba,0x63, + 0x88,0x0a,0x52,0x06,0x94,0xb5,0xc1,0x75,0x93,0x6b,0x93,0x4d,0xbb,0x37,0xcb,0xaa, + 0x10,0xeb,0xd6,0x4f,0xe5,0x57,0xa6,0x67,0x0b,0x39,0xab,0xf7,0x5d,0xdd,0x96,0x83, + 0xab,0x46,0x97,0x19,0x4b,0x1b,0xb3,0xf4,0x5c,0x2f,0x9b,0xb2,0x14,0xbf,0xaf,0xde, + 0x56,0x17,0xcc,0xe3,0x5c,0xf8,0xee,0x1f,0xaa,0xbb,0x7e,0xbf,0xf6,0xc6,0x07,0xff, + 0xfb,0xd1,0xb7,0xe5,0xc7,0xc0,0xbf,0xfc,0x03,0xbe,0xc1,0x66,0x7e,0x87,0x92,0x09, + 0x1c,0x4e,0xc4,0xcc,0xb8,0x5d,0x67,0x62,0x02,0x41,0x64,0x72,0xde,0x76,0xbc,0x45, + 0x67,0x9f,0x4f,0xf6,0x09,0x51,0xe1,0x27,0x2d,0xf3,0x54,0xfd,0x37,0x32,0xdb,0x17, + 0x2e,0x3c,0x7a,0x11,0xd5,0xff,0xea,0xd5,0x9b,0xb3,0x0f,0xef,0x2e,0xad,0xb6,0xf7, + 0xf8,0x14,0x80,0x9f,0x04,0xee,0x3e,0x88,0x82,0x16,0xa0,0x95,0xd2,0x9f,0x08,0xa0, + 0xf3,0x00,0x6a,0x02,0xb8,0x11,0xe0,0x56,0x80,0x9e,0xc0,0x13,0x0d,0x81,0x68,0x09, + 0x4a,0xa5,0xca,0x80,0x98,0xed,0x82,0x66,0xc7,0xa5,0xc2,0xe9,0xad,0x10,0x21,0x5c, + 0xe1,0x9f,0x11,0x75,0x5e,0xa3,0xa1,0x10,0x9a,0xad,0x1f,0x39,0x49,0xac,0xc4,0xf2, + 0xe4,0x57,0xe1,0x57,0x61,0x64,0x10,0xfd,0x06,0xd8,0x63,0x40,0x29,0x60,0xfd,0xa5, + 0x8a,0x4a,0x5f,0xb9,0x59,0x66,0xa0,0x2e,0x23,0x0e,0x68,0xbd,0x52,0x95,0x8c,0xae, + 0x6c,0xb2,0xf1,0xb4,0x58,0x45,0x5b,0x32,0xe0,0x98,0xa0,0x23,0x57,0xb4,0x6d,0x15, + 0x6d,0xa8,0xb6,0x42,0x65,0x4f,0x59,0x4b,0xc9,0xc8,0x5f,0xc5,0xa6,0x67,0xf2,0xac, + 0xed,0xb5,0x6f,0xcc,0xa8,0x72,0x19,0xa8,0xe8,0xf0,0x01,0x55,0x76,0xf5,0xd0,0x3e, + 0xb3,0x5d,0x1f,0x90,0xc9,0xeb,0x04,0x28,0xa4,0xae,0x82,0x4b,0x7a,0x47,0x68,0x63, + 0x75,0x99,0x56,0xb8,0x20,0x07,0x6c,0xb1,0x57,0x6c,0x2e,0xb5,0xa8,0x7a,0xbf,0x49, + 0xca,0xeb,0xcc,0x4a,0x83,0x8c,0x0d,0x32,0xf2,0x80,0xde,0xaf,0x32,0xbf,0x03,0xa6, + 0x4c,0x4d,0x31,0xe8,0xc2,0xac,0xa8,0x02,0xad,0x38,0x89,0x18,0x5d,0xee,0xda,0x7d, + 0x97,0xa8,0x72,0x7b,0x23,0x09,0x55,0xb7,0xfe,0xe8,0xaf,0x3e,0x08,0xc6,0xff,0xf8, + 0xbb,0x2f,0xea,0x08,0xcb,0x99,0xc4,0x98,0xfd,0x59,0x3e,0xa1,0x7c,0x8c,0xf1,0x65, + 0x6d,0x17,0xf5,0xf5,0x37,0x44,0x47,0x9f,0xab,0xbe,0xae,0xfd,0x8f,0xe4,0x6a,0x59, + 0x1c,0xfd,0x37,0xc4,0xc9,0xff,0x19,0x5f,0xfa,0xb7,0x94,0x8a,0xa2,0x01,0x98,0xae, + 0x71,0x03,0x50,0xba,0x7f,0x33,0xad,0x3e,0x09,0xe2,0x8f,0xe9,0x23,0x6f,0x3d,0xab, + 0xb1,0x1b,0xe8,0x44,0x80,0x6f,0x09,0x2c,0x36,0xc5,0xd9,0xc0,0xcd,0xe6,0xfe,0xcd, + 0x26,0xbd,0x71,0x2a,0xe6,0x0e,0x3f,0x0f,0xc4,0x7d,0x03,0xbd,0x26,0x97,0xdc,0x6e, + 0xaa,0x2d,0x29,0xd3,0x71,0x7e,0x2c,0xdb,0xec,0x34,0xf7,0x95,0xb0,0x5a,0x93,0x20, + 0xb7,0x30,0x1c,0x57,0xba,0x45,0x90,0x7c,0xe6,0xa8,0xa9,0x34,0x9a,0x74,0x38,0x66, + 0xd3,0x68,0x50,0xfe,0x4a,0xbf,0x9e,0xb4,0xdb,0x11,0xd4,0xf6,0x68,0xcf,0xc0,0x2e, + 0x19,0xd8,0xd4,0x76,0xab,0xdf,0xbe,0x13,0xd1,0x78,0x39,0x32,0xfb,0xd6,0xbf,0x63, + 0xf3,0xe0,0xe8,0xb1,0x89,0xdb,0x4c,0xea,0xa8,0x6e,0x39,0x72,0x86,0x6d,0xb8,0x13, + 0xdf,0xda,0x67,0xe5,0x3a,0xa6,0x48,0x94,0xb7,0x8c,0xe1,0xc9,0xeb,0x75,0xd3,0xc8, + 0x37,0x3b,0x5e,0xde,0x3a,0x89,0xfa,0x9d,0xe2,0x30,0x65,0x27,0x7f,0x5e,0x7e,0x9c, + 0xe8,0xde,0x7e,0x76,0xec,0x6e,0x1a,0x9b,0x92,0xf6,0x8f,0xc9,0x7f,0x53,0xea,0xa6, + 0xd5,0x3e,0x17,0xc1,0x84,0x70,0x64,0xe6,0x97,0x45,0x8f,0x99,0x3a,0xcd,0xc1,0x6f, + 0x79,0x79,0x52,0x04,0x65,0x7e,0xe3,0x0f,0xde,0x7e,0xc3,0x3c,0xfc,0xf3,0xc1,0xc3, + 0xff,0xbc,0x2d,0x42,0x39,0x58,0x2c,0xe7,0x13,0x23,0x7a,0xbf,0x65,0x29,0x43,0x4e, + 0x3a,0x30,0x4f,0xea,0x2d,0x15,0xee,0x6c,0xc8,0x69,0x59,0xea,0xa6,0xca,0xad,0xb6, + 0x85,0x21,0xac,0x84,0x27,0x0d,0x6f,0xb9,0x3c,0xe2,0xda,0xcf,0x2d,0x80,0x68,0x66, + 0x32,0x54,0xfd,0xcf,0xf8,0xd2,0xbf,0x43,0x61,0xb8,0x38,0x2b,0x1a,0x80,0x5b,0x0d, + 0x3a,0x05,0xe8,0xd0,0x37,0x01,0x77,0x78,0x74,0x9c,0x60,0xa0,0x2b,0x7e,0x86,0xa3, + 0xc5,0x97,0x02,0x76,0xa8,0x09,0xd8,0xa1,0xd1,0x1c,0xa8,0x27,0xb0,0x48,0x6f,0xe2, + 0xf0,0xeb,0x38,0xf4,0x52,0x4e,0x93,0x5e,0xc9,0xd9,0x3a,0x9c,0xa3,0xc2,0xfb,0xcb, + 0x9e,0x24,0xe6,0xf3,0x49,0xff,0x74,0x14,0x9c,0x40,0x5f,0x93,0xa7,0x67,0x51,0x71, + 0x64,0xac,0xe3,0x64,0xa3,0x99,0xe8,0x7c,0x36,0x9a,0x87,0x6e,0xfa,0xfe,0x4e,0xb6, + 0xf9,0x2f,0xd5,0xa4,0xbf,0xd8,0xe4,0xd1,0xfc,0xcc,0x6f,0xfc,0xe2,0xef,0xfd,0xf5, + 0x3f,0xdc,0xfb,0x87,0xaf,0xfc,0xc1,0x1f,0xff,0xfc,0xf2,0x31,0xe4,0x9f,0x0b,0x8f, + 0x0e,0x0f,0x1e,0xe2,0x89,0xab,0xbd,0x64,0xf2,0x91,0x6a,0x02,0xe6,0xe7,0x37,0x32, + 0xb7,0xc7,0xb7,0x47,0xce,0xfa,0xce,0x9f,0xcb,0x8d,0xa9,0xe1,0xe2,0x5d,0x6e,0x00, + 0xe8,0xca,0x3a,0x0d,0x0a,0xb3,0x43,0x63,0x4e,0x45,0xc1,0x75,0x40,0x7d,0x16,0xa0, + 0x3e,0x17,0x2a,0x1a,0x01,0xd1,0x0a,0xe8,0x66,0x40,0xb6,0x05,0xdc,0x1e,0x88,0x5f, + 0x7a,0xf1,0xf0,0x69,0xf1,0x88,0xf0,0xfe,0xb2,0x27,0x89,0xf9,0x7c,0xd2,0x3f,0x2d, + 0x0d,0xc7,0xd7,0x27,0x79,0x16,0x0d,0x47,0xc5,0x3a,0x4e,0x2e,0x16,0x4f,0x28,0x7f, + 0x92,0xf4,0xfa,0xe9,0x5b,0x74,0x72,0xad,0x66,0x76,0x7f,0x69,0x88,0x78,0x34,0x39, + 0xd4,0x8f,0x47,0x4a,0x40,0xf0,0x60,0x48,0x56,0xb2,0xbe,0xb2,0xcf,0xc6,0x24,0xa7, + 0x3f,0x39,0x64,0x67,0xf2,0x24,0xaf,0x47,0x93,0x32,0xc0,0xb3,0xef,0x91,0x5e,0x8a, + 0x4a,0x4f,0x3f,0xb9,0xd0,0x6d,0x80,0x3c,0xfa,0x8f,0x8f,0x8c,0xdc,0x7e,0x81,0xd5, + 0xff,0xea,0xd5,0xd4,0x4a,0xb1,0x48,0xcf,0x01,0xd1,0x07,0xf7,0xb2,0xf2,0x1c,0x60, + 0x67,0x47,0x7e,0x17,0x30,0x36,0xd8,0xa5,0xbc,0x18,0xa8,0xee,0x09,0x10,0xd4,0x17, + 0xe0,0x76,0x40,0x2f,0xa5,0xeb,0x50,0x8e,0x21,0xd2,0x47,0xf6,0x24,0x31,0x9f,0x4f, + 0xfa,0xa7,0xa7,0xe2,0xd8,0xfa,0x72,0xc7,0x49,0x2e,0x51,0xe2,0x88,0x68,0xc7,0xc9, + 0x44,0xae,0xef,0xc6,0xc9,0x89,0x45,0xef,0xa7,0x4f,0xfd,0x8f,0x74,0xc6,0x69,0xb0, + 0x87,0x5c,0xae,0x3b,0xf6,0xe8,0xf8,0x0c,0xc5,0xea,0xdb,0xf3,0x60,0xf3,0xd0,0x04, + 0x13,0x85,0x37,0xd5,0xa4,0x3c,0x16,0x8c,0x12,0x3a,0xfa,0x2f,0xd3,0xd1,0x7f,0xe4, + 0x42,0xe6,0xcc,0x5e,0xfa,0x4b,0xe6,0xe3,0xfa,0x6c,0x71,0x76,0x6d,0xba,0x56,0x93, + 0x83,0x63,0xd1,0x20,0x3b,0x39,0xdd,0x00,0x84,0x03,0xbb,0x46,0x29,0xf7,0x29,0x6f, + 0x39,0x28,0x25,0xcf,0x0f,0x44,0x53,0xf0,0x40,0xb4,0x07,0xb2,0x59,0x38,0x94,0x63, + 0x88,0xf4,0x91,0x3d,0x49,0xcc,0xe7,0x93,0xfe,0xe9,0xa9,0x38,0xb6,0x3e,0xd1,0xd5, + 0xa2,0xde,0xd6,0x11,0x0a,0x92,0x24,0x8e,0xb0,0x32,0x29,0x4e,0xe8,0xe5,0xc9,0x1c, + 0x6d,0xc6,0xe1,0xe9,0x1d,0xc7,0x00,0x2d,0xf8,0x80,0x67,0xcd,0x83,0xee,0x83,0xb1, + 0x05,0xc1,0x26,0x2d,0xd8,0x95,0xc8,0x66,0xdf,0x90,0x67,0x61,0x93,0xf4,0x6d,0xba, + 0xdb,0x0b,0xca,0xc7,0xf7,0x74,0x3c,0x28,0xca,0xa6,0xc5,0x73,0x3f,0x12,0x5b,0x8f, + 0x36,0xc7,0x36,0x75,0xf5,0x9f,0x5c,0xce,0x64,0xc4,0xd1,0x7f,0xfb,0x05,0x9e,0xfb, + 0x6b,0x9a,0xd3,0xd4,0x00,0x54,0xf3,0x7b,0x3c,0x2a,0x54,0x87,0x6e,0x04,0x1e,0xd2, + 0x02,0xa8,0xaf,0x85,0x58,0x78,0x60,0xd7,0x48,0x8e,0xfe,0x7b,0x00,0xc0,0x73,0x44, + 0x8e,0x22,0x7c,0x70,0xf0,0x5c,0x6b,0xf6,0xf1,0xb8,0x21,0x26,0x9a,0xed,0xf6,0x09, + 0x88,0x35,0x45,0x9b,0xb2,0x75,0x10,0xc7,0xff,0x31,0x59,0xfd,0xe9,0x1e,0xc1,0xed, + 0x91,0xed,0x07,0x2f,0xbe,0xfa,0x5f,0xbd,0xda,0x6d,0x8b,0x06,0xe0,0x52,0x95,0x6e, + 0x03,0xf0,0x39,0xc0,0xc4,0x16,0xb5,0x00,0x0f,0x64,0xb5,0xa6,0x77,0xfc,0x54,0xd5, + 0xd7,0x4d,0x40,0x2a,0xd2,0x1f,0x0c,0x08,0xdf,0xfb,0x72,0x5e,0x7b,0xd3,0x93,0xf7, + 0x3a,0x59,0xec,0x45,0xb3,0x96,0x8d,0xa2,0xa3,0xb9,0xaf,0x07,0x7a,0xeb,0xd0,0x33, + 0x31,0x0d,0xf3,0x7a,0x9e,0x11,0xf0,0x12,0x38,0x4e,0xfa,0xfe,0x2b,0x70,0xad,0xd0, + 0x1d,0xaa,0x88,0xa2,0xd0,0x80,0x96,0x93,0x92,0xb3,0x65,0xac,0x0d,0xf2,0xe9,0xd9, + 0xeb,0xe4,0x29,0x7c,0x9d,0xce,0x8b,0x9f,0x94,0x25,0x27,0x69,0x3f,0x7e,0x60,0x8a, + 0xf3,0x76,0x9e,0x5b,0x82,0x6e,0x3e,0xfd,0x8c,0xfa,0xb9,0x76,0x4d,0xf4,0x33,0x1c, + 0xec,0x7c,0xaf,0xf8,0xbc,0x7d,0xe8,0x67,0xc8,0xdb,0x8d,0xae,0x7d,0x72,0xa4,0xc7, + 0x56,0x4b,0xd4,0x3e,0xaa,0x8e,0x37,0x0e,0x63,0x41,0xfe,0x62,0x42,0x87,0xc7,0x4a, + 0x56,0xb4,0x70,0xc3,0x54,0xff,0x1b,0x66,0x5a,0x58,0xd0,0x89,0xf8,0x01,0x2a,0x52, + 0x6c,0x52,0x8d,0x86,0x69,0x37,0x36,0xc7,0x16,0xb8,0xfb,0x3f,0x34,0x44,0x0f,0xfe, + 0x6c,0x64,0xe8,0x49,0xa1,0x17,0xdc,0xf7,0xd7,0xb4,0x5e,0xbd,0x5b,0x5c,0xbb,0xb4, + 0x5a,0xbb,0x45,0xc3,0xdc,0xd2,0x98,0xbe,0x13,0x3c,0xca,0x5e,0xf7,0x81,0xda,0x01, + 0x51,0x42,0x27,0x40,0x2f,0xe4,0xee,0xd5,0x4d,0x02,0xef,0x48,0xf3,0xa2,0xaf,0x16, + 0x90,0xef,0x89,0xa6,0x28,0xa4,0xa5,0x3d,0x64,0xb0,0x0d,0x57,0xb7,0x19,0x53,0x52, + 0x41,0x4b,0x46,0x96,0x52,0x6a,0xa9,0x13,0x35,0xfa,0x65,0x7c,0xeb,0x63,0xa4,0xb5, + 0x3e,0xcf,0xcc,0x94,0x36,0xee,0xa8,0xf4,0xad,0xe1,0x8e,0xfd,0xa1,0xd3,0x28,0xd6, + 0x93,0x8a,0xa0,0xdf,0x70,0xd6,0x59,0x6d,0x85,0x46,0xb7,0x6c,0x92,0x8e,0xa5,0xae, + 0x7e,0x9b,0x29,0x25,0xa2,0x0b,0x2e,0x2c,0x52,0xed,0x6f,0x2c,0x69,0x59,0xb5,0x4e, + 0x76,0x53,0xc6,0xc7,0x14,0xae,0x55,0xeb,0xe6,0xd9,0x7a,0xb5,0xa2,0x40,0xb1,0xd9, + 0x6c,0x79,0x91,0x74,0xbc,0xc8,0x4d,0xc3,0xdf,0xfd,0xd6,0x10,0xfd,0x1f,0xb1,0xe2, + 0x36,0xb3,0x66,0x4f,0xe9,0xfd,0xe3,0xe6,0xe1,0xa4,0x35,0xf8,0x6c,0x59,0x48,0xda, + 0x74,0x1a,0x11,0x53,0xff,0xf9,0xd8,0x2f,0x2f,0xfc,0xd3,0x53,0x42,0x17,0x46,0x32, + 0x2f,0xe0,0xa1,0xdf,0x64,0x3e,0xce,0xce,0xde,0xe5,0x73,0x80,0xc1,0x95,0x15,0xbe, + 0x13,0xd8,0xd9,0x4a,0xa7,0x73,0x39,0x7d,0x2f,0x80,0xfe,0x0f,0xfa,0x99,0x80,0x16, + 0x0f,0x15,0xec,0x76,0x04,0xe4,0x7e,0xe3,0x46,0xdb,0xfe,0x1d,0xdc,0x7d,0xea,0x54, + 0x11,0x5f,0x22,0x15,0x6e,0x7a,0x51,0xf8,0xcf,0x62,0xfe,0xd7,0x81,0x96,0x20,0xaa, + 0x17,0xd6,0x0a,0x43,0xe3,0xe6,0x1c,0x9a,0xbe,0x0d,0x74,0xea,0x85,0x53,0x19,0x3c, + 0x53,0x12,0xcc,0x4b,0x85,0x3a,0xfd,0x76,0x25,0x15,0x57,0x95,0x60,0x9b,0x2b,0xd2, + 0xaf,0x48,0x6d,0x76,0xfd,0xb8,0x47,0xfa,0xc4,0xd5,0xb6,0x4c,0xcd,0xb4,0xba,0x83, + 0x48,0x2d,0x5f,0x65,0xac,0xac,0xe2,0x7a,0xbd,0x12,0x69,0x45,0x4e,0x29,0x26,0xab, + 0xf3,0xf2,0xa6,0x7c,0x5a,0xa9,0xb3,0xaf,0xd2,0xcf,0xc2,0xc7,0x71,0x2f,0xbf,0x05, + 0x10,0xbd,0x7f,0x71,0xf0,0x9f,0x1c,0xa2,0x2b,0x7f,0xe3,0x74,0xe1,0x7f,0xfe,0x65, + 0xe8,0xfb,0x6b,0x9a,0x97,0xf8,0x1c,0xa0,0xbd,0xd7,0xe0,0x71,0xa7,0x2b,0x9d,0x89, + 0x9b,0x69,0xbe,0x15,0xd0,0x95,0x4f,0x04,0x45,0x72,0xb4,0x88,0x94,0x19,0x28,0x98, + 0x1a,0x81,0xc8,0x99,0x38,0x44,0x35,0x09,0xee,0x1c,0xf9,0x62,0xce,0x66,0xcb,0x6e, + 0x86,0xeb,0x20,0x58,0x6f,0x44,0xc1,0x56,0x2b,0x14,0x70,0xc5,0x62,0xd6,0x85,0xe6, + 0x24,0xa7,0x1f,0x9a,0x91,0x64,0x7b,0xdf,0xf4,0xe3,0xa6,0x7a,0x0a,0x82,0x90,0xd0, + 0xbc,0x84,0x42,0x38,0x2a,0x0f,0x09,0x0a,0x12,0xf2,0xe0,0x9b,0x95,0xa4,0x50,0xee, + 0x58,0x57,0xae,0x8f,0x9a,0x84,0xe2,0x39,0x34,0x3c,0x9c,0x5a,0xf1,0x40,0x3b,0x87, + 0xde,0x34,0xc2,0xcc,0xd9,0xd7,0xe4,0xe7,0x89,0xa9,0xfe,0x9b,0xa6,0xeb,0x2f,0xce, + 0xfc,0x6f,0x8f,0x6f,0xef,0x6e,0x8f,0xbd,0x4c,0xd5,0xff,0xea,0xd5,0x9d,0x76,0xf1, + 0xee,0xda,0x12,0x5d,0x06,0xe4,0x61,0xfa,0xf9,0x43,0x1d,0xa2,0x05,0xc8,0xd1,0x07, + 0x72,0xba,0xea,0x12,0x5f,0x64,0x47,0x98,0x49,0x99,0x2e,0x5c,0xca,0x74,0xad,0xc3, + 0x13,0xd9,0xf8,0x6c,0x4f,0x35,0xc3,0x13,0xe1,0xe0,0x7c,0xd1,0x39,0x1d,0x4f,0x56, + 0xe9,0x68,0x48,0x39,0x91,0xc2,0x53,0xcf,0xf0,0x0a,0x41,0x28,0x74,0x1a,0xe9,0xfb, + 0x09,0x87,0xd1,0x93,0xd4,0x84,0x25,0xd4,0xd2,0x43,0xf3,0xc4,0xdc,0x09,0xd1,0x93, + 0x13,0x71,0xb2,0xa0,0x34,0xf8,0x99,0x76,0x4f,0xf6,0x53,0x6e,0x8e,0x3d,0xb9,0x98, + 0x59,0x8e,0x6f,0x2a,0xc9,0x00,0x2f,0xef,0x89,0x81,0x3a,0x72,0x4c,0x4c,0x4f,0x29, + 0xa9,0x59,0x7a,0xa7,0x5e,0x74,0x05,0xfe,0x04,0xd8,0x43,0xff,0xa3,0x05,0xd1,0xf5, + 0xa7,0x67,0x05,0x44,0xdf,0x3f,0xc3,0xcf,0xfc,0xec,0x66,0x5e,0xb2,0xea,0x7f,0xf5, + 0x6a,0x34,0x35,0x2b,0x2f,0x03,0xe6,0x1b,0xa2,0x05,0x28,0x53,0x1f,0x60,0x7f,0x62, + 0x4b,0x7d,0xdc,0x49,0x75,0x03,0x6c,0x2b,0xe0,0xd3,0x52,0xd7,0x6b,0x5a,0xea,0xc7, + 0x32,0x07,0xce,0xcf,0xfc,0x23,0x79,0x33,0x72,0x9d,0x32,0xe8,0xc0,0xc4,0x77,0xea, + 0x63,0xe4,0x44,0x8e,0x02,0x45,0x56,0xc3,0x81,0x0a,0x8d,0x7c,0x7f,0xe3,0xe1,0x59, + 0x13,0x05,0x52,0xb1,0xf4,0x6d,0x8c,0x67,0x49,0x5f,0xbb,0x3c,0x43,0xbc,0xf8,0x61, + 0xbb,0xa4,0x17,0xd6,0x40,0x2f,0x7e,0x14,0x25,0xc8,0x78,0x5a,0x83,0xb8,0xb1,0x2c, + 0xd8,0x7d,0xa4,0x2c,0x8a,0x42,0x65,0x91,0x31,0x2f,0x0a,0xcd,0x72,0x4b,0xad,0xe5, + 0xfb,0x1d,0x98,0x62,0x0b,0x72,0xe4,0xee,0x89,0x58,0x73,0x60,0x92,0xb4,0x49,0x18, + 0x6b,0x4c,0x76,0x23,0xdd,0x3a,0xdd,0x78,0x86,0xeb,0x77,0x9f,0xac,0xca,0x7e,0x12, + 0xec,0x29,0x80,0x77,0xc3,0x80,0xee,0xfb,0xd3,0x73,0x41,0xa2,0xf2,0x6f,0xf0,0xeb, + 0x41,0xdb,0x23,0xef,0xbf,0xe8,0xbb,0xfe,0x89,0x6c,0xd5,0x66,0xb9,0x0b,0xc0,0x2d, + 0x00,0x8d,0xb5,0x5d,0x11,0xa7,0x01,0x13,0xfc,0xc5,0x0d,0x7e,0x14,0x43,0xde,0xec, + 0x97,0x5f,0x89,0xd4,0x6d,0x81,0xc2,0xdb,0xb0,0xfb,0x31,0x46,0x2b,0xfe,0xd7,0x3e, + 0xf0,0x82,0x9c,0xea,0xe9,0xab,0xf1,0x55,0xaa,0x7f,0x8d,0x17,0xc1,0xd6,0xca,0x28, + 0x1e,0xe0,0xc5,0x3c,0xbd,0xf4,0x8d,0xab,0x15,0xc6,0x69,0xb9,0x31,0x43,0x45,0x07, + 0xbe,0x9c,0x1b,0xdf,0xb8,0x83,0x22,0x4e,0xb4,0xca,0xd5,0x71,0x10,0x99,0xd8,0xad, + 0xd0,0xd6,0x78,0x66,0x5a,0x9e,0x02,0x2f,0x7f,0x7e,0x40,0xe8,0x15,0xda,0xe5,0xb5, + 0x00,0x31,0x9b,0xc3,0x52,0x90,0xf6,0xf8,0x62,0x07,0x72,0xfb,0x80,0xae,0xfb,0x3b, + 0x57,0xe2,0xcf,0x82,0x1b,0x0b,0x0b,0xe1,0x55,0xfc,0xf0,0x36,0x40,0x10,0x18,0x33, + 0xcc,0xf7,0xe2,0x6e,0x3f,0xf5,0xfb,0xa9,0xe7,0x4f,0xef,0xfa,0x8f,0x8f,0xd3,0x90, + 0x00,0x43,0x2f,0xba,0xaa,0x27,0x93,0xda,0x6f,0xcf,0xce,0xae,0x2d,0xad,0x56,0x6b, + 0x7b,0x83,0x74,0x16,0x50,0xae,0x97,0x2a,0x95,0x7d,0xd1,0x0b,0x48,0xcb,0x36,0x80, + 0x5a,0x01,0xf9,0x74,0x86,0x68,0x08,0x1e,0xd0,0xb8,0x00,0xdc,0x24,0xc8,0x2d,0xfd, + 0x2c,0x90,0xf6,0x51,0xab,0xc4,0xa9,0x1b,0xca,0xf4,0x13,0xe8,0x3f,0x9d,0x30,0xe2, + 0x59,0xa5,0x6f,0xa2,0x1f,0x19,0xd3,0xdb,0x0c,0xbc,0xdd,0xf8,0xc6,0x7d,0x10,0x14, + 0x70,0xa0,0xe4,0x30,0x4b,0x7c,0x7b,0xd4,0x56,0x52,0xb4,0xbe,0xf9,0x3b,0x56,0x56, + 0x12,0x05,0x1e,0x24,0x5b,0x2a,0x30,0x21,0x07,0xae,0x22,0x89,0x48,0xb0,0xf5,0xe8, + 0x6c,0x2a,0xfd,0x69,0x21,0xfa,0xfc,0x63,0xba,0xf2,0xcf,0xcf,0xcf,0x67,0xe6,0x33, + 0x34,0x7a,0xc1,0xc8,0x85,0xed,0xa1,0x97,0xad,0xeb,0x6f,0x49,0x55,0xce,0xcd,0xce, + 0x2e,0x2d,0x4d,0xb7,0x6b,0x7b,0x8d,0x06,0x7d,0x72,0x23,0x5b,0x97,0x5f,0xa1,0x6c, + 0x8a,0x36,0x80,0x1e,0xc5,0xce,0xed,0x2c,0xca,0x47,0x32,0x77,0x3e,0x4d,0x8d,0x01, + 0x3d,0x01,0x4c,0xb3,0x71,0xa8,0xd9,0xae,0x13,0xfc,0x0f,0x0b,0x39,0xd4,0xa7,0xaf, + 0xda,0x30,0x62,0x77,0x27,0xb0,0xc2,0x8b,0x76,0x94,0x76,0x57,0xcb,0xb3,0xa5,0x9f, + 0x98,0x8d,0xe4,0x28,0x7d,0x8a,0xab,0x5f,0x92,0xf1,0x2c,0x1d,0xd7,0xc0,0x3e,0x19, + 0x3f,0xb2,0x1c,0xe2,0x16,0x74,0xe5,0xfe,0x3e,0x34,0x33,0x87,0x5b,0x18,0xfb,0xbf, + 0x78,0x19,0xfc,0xb4,0x98,0x1e,0x8c,0x8d,0x89,0xea,0xff,0x68,0x93,0x9e,0x9a,0x3b, + 0x4d,0xc4,0x11,0x7a,0x8c,0x1e,0xcb,0xa3,0x07,0xf4,0xa8,0xa7,0x2e,0x16,0x63,0x63, + 0xe2,0x27,0x66,0xf6,0x1e,0xa3,0xdb,0xf6,0x0b,0xb4,0x16,0x95,0x79,0xc1,0xfb,0x91, + 0x34,0x4d,0x6c,0xe1,0xd8,0x26,0xe9,0xd8,0x54,0xcf,0xfb,0xaa,0xc7,0x7c,0xe5,0x29, + 0x3f,0xbd,0x7c,0x28,0x4e,0xfb,0x79,0x98,0x90,0xdd,0x97,0xe2,0x89,0xbf,0xc3,0x68, + 0xd5,0x57,0x67,0xd7,0xd6,0x96,0xaa,0xe2,0x2c,0x60,0xaf,0xc1,0x9f,0xdd,0xca,0xd2, + 0x67,0xb7,0x2a,0xf7,0xe9,0x93,0xb2,0xcd,0x74,0x3a,0xad,0x5f,0x4b,0xc9,0xd1,0x2b, + 0x3f,0xb4,0xa6,0x39,0x9d,0x53,0x0e,0xf9,0x9d,0x67,0xbd,0xca,0x2d,0x26,0xf9,0x3b, + 0xde,0x9e,0x98,0x23,0xeb,0x2a,0x71,0x25,0x93,0x74,0x86,0x21,0xb9,0xc5,0xc5,0xc5, + 0x20,0x11,0x37,0x20,0x6e,0x44,0x3c,0x0d,0x16,0x4d,0xb2,0xf4,0x98,0xe9,0xf7,0xcd, + 0xb2,0x9f,0x23,0xb3,0x61,0x43,0x62,0x32,0xa1,0x55,0x89,0x3a,0x92,0xc4,0x42,0xaf, + 0x30,0xf7,0x81,0x5f,0x62,0xc2,0x09,0xaa,0x83,0xc2,0x89,0x67,0x26,0x56,0x42,0x09, + 0xfa,0x17,0x43,0x2b,0x5c,0x69,0xfa,0x4e,0xf8,0x97,0xc6,0x86,0x9e,0xf7,0xf3,0xfb, + 0xc7,0x65,0xc8,0xbc,0x40,0x30,0xf4,0xc8,0x73,0x1e,0x5f,0x83,0x7c,0x59,0x88,0x5f, + 0xff,0x9b,0x9f,0xdf,0x98,0xdf,0xd8,0x90,0x95,0x7f,0x64,0x77,0x77,0x64,0xf2,0xa5, + 0xb9,0xe7,0xdf,0x97,0x28,0x3b,0x4d,0x2d,0xc0,0x74,0xb5,0x56,0xdb,0x6b,0xc8,0x2f, + 0xef,0x65,0xb3,0x34,0x94,0x44,0xa7,0x73,0xff,0xfe,0xfe,0x7e,0x73,0x42,0xb4,0x03, + 0xfa,0x75,0xcd,0x34,0xbf,0xfe,0x4b,0x7d,0x03,0xf9,0x49,0x3e,0xb9,0xe6,0x17,0x82, + 0xbd,0x95,0x72,0xa5,0xdd,0x85,0xf6,0x73,0x42,0x7c,0x71,0xa5,0x3b,0x41,0xaa,0x6f, + 0x7c,0xe5,0xf6,0x94,0x39,0x86,0x79,0xe9,0x7b,0xea,0x1c,0x03,0xd4,0xec,0x67,0xe5, + 0x98,0xe9,0xbb,0xe5,0xe0,0x05,0x6f,0x05,0x4e,0xdf,0xcb,0x3a,0x02,0x2b,0xb6,0x82, + 0xed,0xb4,0xa3,0xe3,0x30,0xd5,0xe9,0x78,0x4c,0x2f,0xf7,0xbe,0x95,0xae,0x77,0xb2, + 0x5d,0xb1,0x88,0xfd,0x83,0xb6,0xb6,0x7c,0xe5,0x89,0xc5,0x98,0x56,0xf6,0x84,0xb9, + 0x4d,0x37,0xd3,0xcd,0xe6,0xe2,0xdf,0x4c,0x4e,0xda,0x1a,0x34,0xf4,0xfc,0x5f,0xd9, + 0x4d,0x7e,0x43,0xd7,0xbc,0xd2,0xa7,0xeb,0xef,0x90,0x7a,0xd9,0x4f,0x86,0x0f,0x25, + 0x4f,0x43,0xea,0x5d,0xc0,0x98,0xa5,0xd4,0xe5,0xdf,0x90,0xe3,0x7b,0x66,0xa8,0xf2, + 0xd3,0xd0,0x82,0x3f,0x06,0xb5,0x9f,0x38,0x28,0x2c,0xdd,0x9d,0x15,0x2d,0xc0,0xaa, + 0xe8,0x04,0xe4,0x1b,0xa2,0x0d,0xe0,0xaf,0xc5,0x66,0xf9,0xe3,0x7b,0xa5,0x0a,0x7f, + 0x61,0x66,0x5f,0x9c,0x14,0x08,0xee,0xd3,0x08,0x11,0xfb,0x3c,0x22,0x18,0x7d,0xdc, + 0x7d,0xc2,0x6c,0x9b,0xf5,0x3e,0x7f,0x05,0x7e,0x9f,0x02,0xf7,0xd5,0x40,0x0e,0x36, + 0xbc,0xa3,0x42,0x1d,0x6f,0xe3,0xa2,0x40,0xbb,0xe1,0xea,0x63,0x77,0x27,0x90,0x31, + 0xe1,0xf7,0x79,0x63,0x62,0xc2,0x28,0x97,0x5a,0x3b,0x81,0xfa,0x8e,0x1b,0xfd,0xf9, + 0xa5,0xdf,0x49,0x8e,0xc1,0x62,0x13,0xd6,0x73,0xc2,0x8a,0x4f,0xb8,0xf6,0xb9,0xe9, + 0xc7,0x92,0x24,0x59,0x0a,0xf7,0x32,0x31,0xb1,0x2f,0x7d,0x8c,0xe7,0x7d,0x99,0xb3, + 0x09,0x47,0x51,0x42,0xe6,0x4c,0xfe,0x3b,0x61,0xf9,0xa9,0xad,0x89,0x30,0x82,0xca, + 0x84,0xb7,0x7f,0x9d,0x22,0x0e,0xb4,0x38,0xc5,0x3d,0x91,0x18,0xde,0x99,0xe8,0xc8, + 0x8d,0xfb,0x26,0x84,0xa4,0x27,0x26,0x6e,0xfe,0xcc,0xdf,0xcc,0x4f,0xda,0xf1,0x33, + 0xce,0x94,0xd8,0xc0,0x1d,0xd6,0x11,0x9f,0x28,0xc4,0x19,0xec,0xc3,0xc4,0xdc,0x98, + 0xcf,0xd8,0x41,0x84,0xe4,0xe8,0x80,0x54,0xf9,0x77,0x77,0x37,0x5e,0xc6,0x8b,0xfe, + 0xc9,0x3c,0x28,0x9f,0x5b,0x13,0x9d,0x80,0x69,0xea,0x04,0x88,0xf3,0x00,0xf5,0x09, + 0x6e,0xfa,0x00,0x97,0xfc,0xf8,0x8e,0xfa,0xe4,0x3b,0x0d,0xd2,0x54,0x57,0xc3,0x48, + 0x55,0x4a,0x5f,0x2d,0x69,0x17,0x0f,0xcf,0xa5,0xc7,0xde,0x92,0xd3,0x57,0x4b,0xfe, + 0xb6,0x95,0x2b,0xd9,0xd1,0xa1,0xe2,0x02,0xfd,0x27,0x3f,0x7e,0x2c,0x50,0xc7,0x97, + 0xdb,0xb1,0xd4,0x4f,0x39,0xfd,0x78,0xfc,0x58,0xd8,0x91,0xf1,0x8f,0x33,0x25,0xc5, + 0x0f,0x12,0x7f,0x26,0xfb,0xbd,0x72,0x39,0x5e,0xfc,0xe4,0xcc,0x97,0xc2,0x50,0x99, + 0x77,0xfe,0xa9,0xd8,0x4a,0x48,0x6e,0xde,0xff,0xd7,0x4c,0x26,0x43,0xa3,0xe2,0x7f, + 0xd2,0x11,0xb8,0x4e,0x80,0x1a,0x8a,0x3f,0xd1,0xff,0x28,0x43,0x32,0x74,0x5d,0x6f, + 0xde,0x0a,0x6a,0x71,0x35,0x22,0x20,0x8d,0x07,0xca,0x75,0x7f,0x77,0xe4,0xc7,0xa8, + 0xf6,0x13,0xa9,0x5c,0x36,0x3f,0x4d,0xa7,0x01,0xd3,0xf4,0xfd,0x8d,0xfc,0xde,0x60, + 0x43,0x7e,0x86,0xdb,0x7c,0xef,0x3d,0x11,0x33,0x48,0x64,0xd6,0x19,0xe5,0xd1,0x8c, + 0x3e,0x99,0xf5,0xc4,0xcc,0xa8,0x93,0x59,0x3d,0x34,0xa5,0xe3,0x63,0x06,0xba,0x74, + 0xc7,0x9d,0x2c,0x7b,0xc1,0x59,0x47,0x77,0xd6,0x55,0x6a,0x13,0xf1,0x2d,0x0a,0xcc, + 0xf4,0x2c,0x2e,0x07,0x91,0xad,0xe4,0x71,0xd3,0x0f,0x92,0x8f,0x67,0xc5,0x37,0x31, + 0x96,0x5b,0xcf,0x20,0x5f,0xd8,0x2d,0xbb,0x20,0x2c,0x30,0xdf,0x19,0xc2,0xd4,0x75, + 0x79,0x39,0x8f,0xe7,0x20,0x29,0x53,0x59,0x37,0xe5,0x6c,0x98,0x7e,0x90,0xb6,0x27, + 0xe7,0x8c,0x11,0xaa,0x2d,0x73,0x06,0x49,0x75,0x34,0x14,0xd8,0xbb,0x90,0xd5,0x83, + 0x84,0x96,0xeb,0xff,0xfc,0xaf,0xb7,0xf9,0x7b,0x58,0x6a,0x20,0xcd,0xb3,0x99,0xa8, + 0xae,0x66,0x36,0xd4,0xc8,0x9d,0xbc,0xb5,0xa1,0x8c,0x38,0x7c,0xdc,0xd0,0x8c,0x36, + 0x75,0xdc,0x8e,0x10,0xaa,0x90,0xc3,0x03,0xcb,0x91,0xc7,0xe9,0x6b,0x7f,0xdb,0xf3, + 0x0b,0x2f,0xf7,0x55,0xbf,0x44,0x3e,0xee,0x76,0xa6,0x56,0xd7,0x96,0xd6,0x2e,0x89, + 0x13,0x01,0x3a,0x13,0xa0,0x46,0xa0,0x41,0x03,0xb8,0x53,0x43,0x40,0x1f,0x00,0xd1, + 0x9f,0xf3,0xb6,0x5f,0x78,0x5e,0x31,0xdf,0x8b,0xf5,0xbe,0xfd,0xea,0x7e,0x06,0xb6, + 0x97,0xb0,0x72,0xc3,0xfa,0xc4,0xf3,0x57,0x61,0x58,0xbf,0x38,0x7d,0xd2,0x38,0xcd, + 0xf4,0xfb,0xe7,0xdb,0x93,0xed,0xf5,0x89,0xd9,0x4f,0x55,0xbf,0x8c,0xf6,0x13,0x89, + 0x25,0xdb,0xc7,0xb8,0x23,0xca,0xef,0xf5,0xbe,0x85,0x15,0xfb,0x52,0x78,0xa2,0xe6, + 0xd7,0xe3,0x5f,0x01,0x37,0x2b,0x11,0xf6,0x7a,0x6f,0xe5,0xf5,0xf5,0x95,0xd7,0x29, + 0x99,0xf2,0xdf,0xff,0xb3,0x1a,0x3a,0x7b,0x64,0x44,0x1e,0x38,0xb7,0xcf,0x04,0x99, + 0xce,0x08,0x8d,0xde,0x4d,0x1f,0xe5,0xa3,0x6f,0xf2,0x8e,0x48,0x97,0x72,0x5b,0x46, + 0xdc,0xc5,0x38,0x8f,0xeb,0x2f,0x05,0x59,0x8f,0x5c,0x8c,0xd3,0x88,0xff,0xf2,0xc3, + 0x04,0x23,0xf2,0x23,0x20,0xe3,0x93,0x3f,0x5e,0x47,0x7e,0x8f,0x68,0xab,0xd0,0x5e, + 0xe2,0x36,0x40,0x34,0x02,0xf4,0x75,0xad,0x7c,0x8d,0xbe,0xc5,0x22,0xbf,0x9f,0xd7, + 0xe0,0x6f,0xc4,0x81,0x97,0x93,0x97,0x7c,0xcf,0x38,0xe6,0x4d,0xad,0xbc,0xfe,0x83, + 0x5f,0xfd,0x5b,0xea,0x24,0xef,0xea,0x9a,0xf3,0xfc,0xbf,0xc3,0xd1,0x87,0x5d,0xf3, + 0xc9,0x8f,0x5d,0xb3,0x18,0x09,0x5c,0xbb,0x7e,0xb0,0x2f,0xa8,0x14,0x28,0x21,0xce, + 0x03,0x7d,0x86,0x88,0x3e,0xfa,0x75,0x79,0x66,0x24,0xf3,0x92,0xdf,0xee,0x3b,0x06, + 0xa9,0x5c,0x7d,0xb0,0x4d,0x5f,0x68,0xbc,0x24,0x3f,0x63,0x29,0xda,0x01,0x31,0xd1, + 0xa7,0xf1,0x78,0x62,0xe8,0x2b,0x80,0x6d,0xfb,0x29,0xc0,0x38,0x22,0x4c,0x8a,0xba, + 0x4b,0xbb,0xe6,0xc8,0x71,0x81,0xbc,0x27,0x9b,0x3f,0x56,0x7c,0x47,0x36,0x31,0xbe, + 0xef,0x97,0x90,0xbe,0x23,0x70,0x82,0xf4,0x6b,0x49,0xf1,0xad,0x4c,0xde,0xf7,0x0b, + 0xe1,0xe4,0x63,0xfa,0xbd,0xa5,0x5b,0xba,0x31,0x4d,0xed,0xb8,0x7e,0x93,0xdb,0x78, + 0xbe,0x13,0x0c,0x69,0xd7,0xe2,0x36,0x93,0x0e,0xb7,0x5c,0xdb,0xb5,0xbc,0x93,0x9a, + 0x15,0xcc,0xc7,0x8c,0xb5,0x36,0xc4,0xfe,0x14,0xc6,0x0c,0x55,0xc2,0xb7,0x06,0xbf, + 0xf1,0xc7,0x7f,0xf1,0x8f,0xaf,0xe9,0x6f,0xf4,0x9d,0xe0,0x3b,0x7d,0xa7,0xc2,0x4c, + 0x82,0xeb,0xf2,0x6e,0xc2,0xc2,0x95,0x9b,0xb1,0xbe,0xc2,0xf9,0x75,0xfe,0xfa,0x9f, + 0x38,0xf2,0x6f,0x6f,0xfc,0x38,0xf6,0xfa,0x13,0xa1,0xaf,0xed,0xa5,0xf7,0x4b,0x85, + 0x5e,0x63,0x2f,0xdf,0xa6,0x2f,0xb1,0x12,0xd5,0xea,0xea,0xb9,0xaa,0x58,0xb7,0x69, + 0x12,0xcd,0x42,0xb5,0x2d,0xb6,0xab,0xe7,0xc4,0x44,0xdb,0xf4,0x23,0xb7,0x58,0x55, + 0xcf,0x59,0x8f,0xf6,0x39,0x13,0x22,0xd7,0x9e,0xb8,0xb7,0x14,0x61,0xa4,0x97,0xc3, + 0xce,0x55,0x7d,0xf1,0xfe,0xf1,0xcf,0xc9,0x75,0x75,0x35,0x39,0xbe,0x95,0xd3,0xa6, + 0x48,0x8f,0x78,0xe2,0x27,0x4c,0x3f,0x6e,0xbc,0x51,0x4f,0xf9,0x57,0x92,0xe7,0xaa, + 0xee,0x64,0x93,0x0f,0x4b,0x20,0x49,0x8f,0x1f,0x2f,0x8c,0xaf,0xc5,0x0f,0xd7,0x6b, + 0x97,0x81,0xfa,0x23,0xf7,0x0b,0xaf,0x57,0xdb,0x26,0xbe,0x0a,0xa8,0xea,0x94,0x7d, + 0x7f,0x37,0xbe,0xa7,0xe1,0x1c,0xfd,0x47,0xaa,0x74,0x4d,0xa9,0xf6,0xc5,0xff,0xfc, + 0xc6,0x9f,0x7f,0xeb,0x5b,0xa2,0xee,0xbb,0x1f,0xcb,0x0d,0x3f,0x9b,0xfb,0xc2,0x78, + 0xcd,0x3a,0xef,0x24,0x2c,0x3c,0xf8,0x9b,0xc0,0x14,0x61,0x46,0x9c,0xeb,0x8f,0x6f, + 0x2c,0x0f,0x8d,0x2d,0x7c,0x7c,0xe3,0xff,0x4b,0xdd,0xf7,0xf9,0x38,0x8a,0xe8,0x13, + 0x00,0x06,0x6f,0xe3,0x25,0xe2,0x65,0xb5,0x4b,0xf3,0xac,0xf6,0xbd,0xec,0xf9,0x3a, + 0x1e,0x3b,0x3b,0xf4,0x84,0xdf,0x18,0x0d,0xe7,0x47,0x4f,0xd8,0x09,0xc6,0x36,0x79, + 0x83,0xde,0x93,0x97,0x7e,0x67,0x35,0x6d,0x06,0x3f,0x3d,0xf1,0x53,0x7f,0xbc,0x1e, + 0xdb,0x4c,0x5a,0x6c,0xca,0x30,0xf9,0x90,0xa0,0x7c,0x78,0x70,0x61,0xe1,0xc6,0xc7, + 0xff,0x3f,0x6b,0x3d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x4e,0xc4,0xff,0x01,0x76,0x49,0x09,0x1b,0x36,0x04, + 0x0c,0x00, diff --git a/board/esd/hh405/logo_320_240_4bpp.c b/board/esd/hh405/logo_320_240_4bpp.c new file mode 100644 index 0000000..ddf0d0b --- /dev/null +++ b/board/esd/hh405/logo_320_240_4bpp.c @@ -0,0 +1,227 @@ + 0x1f,0x8b,0x08,0x08,0x9c,0x03,0x94,0x3f,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x48,0x65, + 0x72,0x5f,0x4c,0x6f,0x67,0x6f,0x5f,0x33,0x32,0x30,0x78,0x32,0x34,0x30,0x5f,0x6d, + 0x69,0x74,0x74,0x65,0x5f,0x31,0x36,0x67,0x2e,0x62,0x6d,0x70,0x00,0xed,0x9c,0xfd, + 0x6b,0x1b,0x47,0x1a,0xc7,0x9f,0xae,0xa2,0xe8,0x8c,0x4b,0x42,0xff,0x03,0xb1,0x26, + 0x2f,0x26,0xa5,0x67,0x2c,0x52,0xd7,0xf8,0xb8,0x1e,0xb1,0xfb,0x62,0xc2,0x81,0xa9, + 0xa3,0xe6,0x42,0x43,0x02,0x21,0xf1,0x35,0x57,0x38,0x4c,0x8a,0xbd,0x71,0x1d,0xe2, + 0xa3,0x70,0x89,0x4c,0x8f,0x62,0xdc,0x4b,0xed,0x8d,0x84,0xfd,0xd3,0x71,0x77,0x0e, + 0x94,0x90,0x50,0x7c,0x3a,0x09,0x29,0xb4,0xe4,0x87,0x9c,0x85,0xfc,0x17,0x14,0x42, + 0x8a,0x31,0xc5,0x62,0xd7,0xb4,0x04,0x63,0x24,0x76,0xee,0x79,0x66,0x66,0x57,0x2b, + 0xeb,0xd5,0x24,0x75,0x0b,0x9d,0x2f,0x28,0xfb,0x36,0x3b,0xf3,0xd9,0x67,0xe6,0x79, + 0x66,0x76,0x66,0x9d,0x13,0xbf,0x1f,0xff,0x1c,0xb8,0xc6,0xf1,0x77,0x14,0x7f,0xbf, + 0x7b,0x01,0x60,0x13,0xb7,0x2f,0xc0,0x3e,0x70,0x15,0x6b,0x17,0x3f,0xbf,0x5e,0x7a, + 0xe9,0x25,0xd0,0x75,0x1d,0x22,0x91,0x08,0x0c,0x0c,0x0c,0x40,0x34,0x1a,0x85,0x91, + 0x91,0x11,0x30,0x0c,0x03,0x62,0xb1,0x18,0x98,0xa6,0x09,0x4b,0x4b,0x4b,0x90,0x4a, + 0xa5,0x20,0x97,0xcb,0xc1,0x37,0xdf,0x7c,0x03,0x96,0x65,0x01,0x63,0x8c,0x7e,0x4a, + 0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a, + 0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a, + 0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0xbf,0x6c,0x95,0x72, + 0xf9,0x9f,0x1a,0xa1,0xa1,0xbe,0x87,0xd0,0x4f,0x8d,0xd0,0x50,0x9b,0x8a,0xef,0x99, + 0xa4,0xf8,0xb8,0x9c,0xdd,0xdf,0xe1,0xd8,0xb4,0x21,0x3e,0xb1,0x87,0xb2,0xaa,0x53, + 0xd9,0x55,0xa7,0x76,0xc8,0xb2,0x5b,0x48,0xe9,0xd8,0x56,0xd3,0x8c,0x2a,0xf5,0x34, + 0x0c,0x10,0xc8,0x72,0xbe,0xfb,0x00,0xbf,0xa1,0x3c,0x70,0x0b,0x93,0xec,0x07,0x9d, + 0x6b,0x75,0x5b,0x3f,0xc6,0x9c,0xaf,0x00,0x12,0xf7,0xf4,0x29,0xa7,0x5b,0xb7,0xd9, + 0x6c,0x47,0x96,0x6d,0x77,0x77,0x32,0xf6,0xad,0x7e,0x8e,0x15,0xaf,0x80,0xb6,0x3a, + 0x7b,0x88,0x3d,0x04,0x71,0xf3,0xc6,0x10,0x40,0x90,0xe9,0x3a,0xe6,0xf8,0x8e,0x3e, + 0xc5,0x66,0x71,0xe7,0x89,0xfe,0x3a,0x63,0x9f,0xe9,0xbf,0xc6,0x47,0xc0,0x8b,0x81, + 0x38,0x2b,0xe9,0x47,0xb0,0x14,0xbd,0xa3,0x25,0x52,0xfa,0x93,0x1d,0x02,0xdc,0x84, + 0x20,0xee,0x68,0x98,0xef,0x53,0xfe,0x67,0x3a,0x18,0x70,0xb8,0xec,0x2d,0x68,0x67, + 0x5b,0xf4,0x10,0x33,0x30,0xe5,0xe0,0x31,0x9b,0xd1,0x16,0xd9,0x76,0xb8,0x8d,0xb1, + 0x27,0x70,0x0e,0x7f,0x00,0x47,0x46,0x83,0xec,0x01,0xdd,0x7c,0x9d,0xb1,0x2e,0x20, + 0x3e,0x00,0xcc,0x67,0x08,0xce,0xb3,0x19,0x58,0xc4,0x9c,0x11,0x6d,0x16,0x0e,0x32, + 0xe7,0x0a,0x2f,0x8b,0x95,0x20,0x68,0x33,0x07,0xb4,0x16,0xf9,0x0e,0x75,0x03,0x1c, + 0x20,0x4e,0x2d,0x1a,0xc6,0xbc,0xb1,0x88,0x4e,0x73,0x8c,0xf3,0x91,0xfd,0xec,0x6d, + 0xe4,0xdb,0x84,0x80,0x89,0x25,0x2f,0x56,0xf1,0x39,0x43,0xd0,0x33,0x07,0xd8,0x34, + 0x1e,0xf7,0x24,0x47,0xf1,0x66,0x7c,0xb6,0xd0,0x87,0x15,0x7c,0x59,0xf6,0xd8,0xe5, + 0x2b,0x02,0x4c,0xcc,0x0d,0x69,0xc4,0xc7,0x5a,0xe7,0xeb,0x4d,0x27,0xc3,0xf0,0x22, + 0xf1,0xf5,0x59,0x33,0xa0,0x61,0x2e,0x58,0x7e,0x61,0x88,0xfd,0x80,0xb9,0x99,0xa6, + 0xc9,0xf9,0x1e,0x40,0x1f,0xbb,0x5f,0x93,0xaf,0x0b,0x32,0xf8,0x0b,0xb1,0xb5,0x3c, + 0xde,0xa0,0xb1,0xaf,0x20,0x30,0x55,0x34,0xed,0xda,0x7c,0x6b,0x64,0xb7,0xf5,0x8e, + 0xdd,0xf1,0x15,0x31,0xd5,0xd7,0x10,0xb2,0x91,0x8f,0x8a,0x00,0xcc,0xa5,0x1d,0xef, + 0x2e,0xb0,0x62,0x17,0xbc,0x4c,0x09,0x88,0xef,0x2e,0x16,0x83,0x6c,0x8b,0xac,0x8a, + 0x2f,0x0c,0x96,0xbd,0x4e,0xae,0x45,0x09,0xc1,0x19,0xc5,0x27,0x45,0x27,0xa8,0xcd, + 0x77,0x17,0xae,0x3b,0xcc,0xd9,0xd8,0x1d,0x9f,0x40,0x08,0xac,0x6e,0xe2,0xd3,0xb3, + 0x52,0x17,0xac,0x8e,0x52,0x76,0xa4,0xef,0x09,0x46,0xf0,0x3d,0x80,0x29,0xaa,0xf7, + 0x6c,0x2d,0xfb,0x61,0x53,0xea,0xe2,0xa1,0x89,0x1e,0x2e,0x8c,0x4c,0xa8,0x1d,0x7c, + 0x07,0x05,0xdf,0x90,0xfc,0xfb,0xb1,0x12,0x85,0xb2,0xdd,0xf0,0x6d,0x71,0xbe,0x00, + 0xde,0x34,0x04,0xd9,0x51,0x78,0xdd,0xe2,0x61,0x60,0x9b,0x0c,0x26,0xf8,0x1e,0x63, + 0xfd,0x62,0xf6,0xd5,0x7c,0x74,0x12,0xc9,0x89,0xaf,0x70,0x17,0x9f,0x10,0xe8,0x41, + 0xea,0xf0,0x61,0x85,0x60,0xbe,0x8e,0x6d,0xef,0x9a,0x0f,0x5b,0xb6,0x2d,0xe2,0x33, + 0xfa,0xdb,0x90,0xf0,0xdb,0x73,0x0c,0x63,0x86,0x26,0xf9,0xc8,0x7f,0x23,0xc0,0xf9, + 0x58,0x25,0xdf,0x63,0x74,0xab,0x48,0x18,0xeb,0xf7,0x1d,0xbc,0xe7,0x98,0x00,0xab, + 0xe2,0x13,0xf5,0xbb,0x1d,0x16,0x39,0x4f,0xb9,0xf5,0xdb,0x2a,0xde,0x32,0x70,0x17, + 0xad,0xe2,0x73,0x78,0x31,0xc4,0xe7,0xdc,0xe5,0xe7,0x6a,0xd8,0xaf,0xc8,0x93,0x87, + 0xc8,0xd8,0x10,0xca,0xd4,0xe1,0x93,0xf6,0x93,0x7c,0x8b,0xbb,0x6b,0x7f,0x5b,0x14, + 0xb2,0xce,0x33,0x5e,0xbf,0x16,0xaf,0xdf,0xdf,0x5a,0xd6,0x77,0xbc,0x9e,0xbe,0x86, + 0xe0,0x2a,0xe7,0x63,0x8e,0x95,0x5b,0xa1,0xaa,0xe4,0x7c,0x78,0x6d,0x1b,0x2d,0x6e, + 0x7d,0x4b,0x0f,0xc1,0xac,0x95,0xd4,0x50,0x08,0xdb,0x7e,0xe0,0xba,0xcd,0xca,0xf5, + 0x3b,0x45,0xed,0xd5,0xc7,0x37,0x03,0x07,0x4b,0x43,0xf4,0x77,0x8c,0x8f,0x21,0x5b, + 0x22,0xb4,0x96,0xf9,0xee,0x8a,0xb0,0xbc,0x49,0x55,0x87,0x4d,0x64,0x75,0x06,0x5e, + 0xa1,0x16,0xb9,0xc8,0xab,0x96,0xa3,0xb4,0x8b,0x84,0x5e,0xfb,0x43,0x2c,0xf2,0x28, + 0x6e,0x3f,0x92,0xc3,0xf9,0x8e,0x51,0x71,0x5d,0xf0,0xba,0xe0,0x3b,0xcf,0xb8,0xaf, + 0x08,0xbe,0x03,0xd4,0x84,0x0e,0xa2,0x73,0xe3,0xa5,0x07,0x80,0xed,0x0f,0x56,0x5b, + 0x8f,0x2f,0x64,0xf5,0x04,0xef,0x47,0x6c,0x8c,0x2d,0x60,0x3f,0xa4,0xec,0xee,0x63, + 0x0e,0xbc,0x9c,0x03,0x82,0x8f,0xb2,0x0a,0xc3,0xaa,0xe4,0x7b,0x19,0xf9,0xb1,0x92, + 0xc9,0xab,0xa9,0xb7,0x75,0xb0,0xb2,0x67,0x84,0xe1,0x46,0xe9,0x66,0x7e,0x9f,0xcd, + 0x8d,0x48,0x7c,0x9b,0xd0,0x46,0x0f,0x47,0xf1,0x25,0xc3,0x9c,0x19,0x40,0xff,0xc5, + 0x2b,0x25,0x08,0xb4,0xda,0xbf,0xf5,0xd8,0x62,0x1b,0x9c,0x18,0xc2,0x46,0xeb,0x74, + 0x69,0xd7,0x1e,0xe1,0x76,0x3b,0x1a,0x1d,0xee,0xc2,0x6a,0xe4,0x7c,0x57,0x4e,0xe7, + 0x6e,0xe1,0xbe,0xe4,0x03,0xea,0x4c,0x42,0x26,0xc0,0x02,0xdb,0xd2,0x26,0xb1,0xe2, + 0x0f,0x60,0x60,0x0e,0x26,0x96,0xcf,0xb2,0x6f,0x01,0x7a,0xe7,0xce,0x22,0x9a,0x76, + 0x66,0x8c,0xac,0x24,0xec,0x07,0x3d,0xb7,0x00,0x0d,0xbb,0x05,0xc1,0xdc,0x3d,0xde, + 0xbf,0x61,0x51,0x5d,0x44,0xdd,0x82,0x1e,0x43,0x20,0x23,0x38,0x35,0xd1,0xd2,0xc9, + 0x9b,0xbb,0xb1,0x05,0x6f,0xf1,0xc6,0x1c,0x14,0xf6,0x1b,0x85,0xe3,0x80,0x19,0x4a, + 0xbe,0x30,0x26,0xd5,0x00,0x0d,0x9f,0x21,0x43,0x0e,0x03,0xda,0x06,0x83,0xdf,0xa1, + 0xae,0x17,0xb9,0x9b,0x84,0xdb,0x91,0x8f,0x92,0x04,0x6c,0x97,0x8f,0xbb,0x2d,0x71, + 0x1d,0xc7,0xce,0x13,0xb7,0x1a,0x15,0xd6,0xd7,0x12,0xdf,0x03,0x19,0x8e,0x37,0xa1, + 0x13,0x8d,0x82,0x1d,0x10,0x0f,0x26,0x98,0xad,0xe4,0xe3,0xf6,0xc3,0x5a,0x41,0xa2, + 0xf3,0x92,0x2f,0xb4,0x8e,0x07,0x0b,0x33,0x3c,0x35,0x0f,0x1a,0x21,0x6c,0x0c,0x14, + 0x5f,0xf0,0x41,0x3e,0x03,0x7a,0x0e,0x00,0x1a,0x03,0x65,0xe8,0xb9,0x16,0x91,0xef, + 0x74,0x58,0xd0,0x7c,0x49,0x69,0x2d,0xe4,0x6b,0xc3,0x9b,0x5b,0x74,0x0f,0x97,0x6f, + 0xcb,0xb8,0xf6,0xdd,0x3b,0x87,0xa6,0x70,0xcf,0x59,0xeb,0xee,0x98,0xb4,0xd8,0xb6, + 0x41,0x9a,0x60,0x45,0x63,0x12,0x87,0x4d,0x63,0xdd,0x91,0x04,0xf7,0x4f,0x9b,0x2d, + 0x4f,0xd8,0x63,0x1d,0x7d,0xf6,0xf6,0x70,0x07,0x02,0x38,0x1b,0x51,0xfd,0x38,0x8e, + 0x5b,0x58,0x61,0x58,0xef,0xa1,0xed,0x97,0xdd,0xc7,0x27,0x31,0x59,0xe6,0xbe,0x7e, + 0x1a,0x8f,0x96,0x8d,0x55,0xb6,0x6e,0x2c,0x2c,0x77,0x1f,0xa7,0x21,0xa5,0x3d,0xa6, + 0x1f,0x5f,0xc0,0xad,0x31,0x59,0xfc,0x50,0xbf,0xd6,0x1a,0x1f,0xf7,0x7e,0xa9,0x62, + 0x5a,0x6c,0x93,0xa9,0xea,0x74,0xfc,0x9c,0x23,0xba,0x3c,0x56,0x8a,0x67,0x91,0x59, + 0xa4,0x2e,0xa5,0x56,0xc5,0xcd,0xa9,0x2c,0x3f,0x4c,0x66,0xc9,0x35,0xb2,0xee,0x69, + 0xc6,0x47,0xac,0xa9,0x2c,0x1f,0xb6,0xf2,0xfb,0x48,0x76,0xb1,0x46,0x11,0x75,0xf8, + 0xda,0x1c,0x7b,0x25,0xdb,0x5a,0x62,0xde,0x7f,0xb4,0x20,0x19,0xa6,0x9f,0x87,0x70, + 0x14,0xd0,0x31,0x2c,0x7a,0xf5,0xda,0x2a,0x9a,0x09,0x6f,0xdf,0xb5,0x5f,0x33,0x79, + 0x7c,0x49,0x73,0xb5,0x61,0xc2,0xe6,0xc2,0xa8,0x09,0x20,0xa2,0x6a,0x6d,0x79,0xf1, + 0x59,0x14,0xbc,0x3b,0xbe,0x51,0x1e,0xe7,0x9f,0x49,0x3f,0x70,0xbe,0xfa,0xc5,0x6e, + 0xf9,0xf8,0x76,0x6d,0xbf,0x99,0x67,0xe7,0x73,0x96,0x87,0x8f,0x4f,0x34,0xa8,0x05, + 0xbf,0xfd,0x70,0x38,0xba,0xe7,0xf6,0x6b,0x2a,0x9f,0xf3,0x38,0x63,0xd1,0x96,0xf8, + 0xa2,0x51,0xf9,0xc0,0x85,0xdc,0x2e,0x5f,0x27,0x9f,0x51,0xcd,0x5f,0x83,0xb9,0xac, + 0xea,0x17,0x68,0x25,0x25,0x25,0xa5,0x5f,0x9e,0xf6,0x36,0x42,0x3f,0x77,0xd5,0x9e, + 0x51,0x75,0x0a,0x49,0xe3,0x47,0xd7,0x55,0xb3,0xb9,0xe2,0x59,0xab,0xba,0x53,0x2a, + 0xde,0x82,0x3d,0x92,0x3e,0x10,0x69,0xa6,0xee,0x23,0xf1,0x1d,0x80,0xc5,0xa1,0xbd, + 0xc2,0x23,0xc0,0xa6,0x8a,0x44,0xae,0x55,0xe0,0xf1,0x19,0x8d,0x3d,0x93,0xf6,0xe6, + 0x48,0x63,0x5d,0x42,0xc2,0x41,0xff,0xb4,0xf9,0x95,0xbd,0xc4,0x03,0x38,0x6c,0x18, + 0x7f,0x6c,0xd0,0x48,0x47,0x46,0x2e,0x0e,0xf4,0xeb,0x9f,0x96,0xf9,0xd6,0xf7,0x16, + 0x0f,0xb4,0xf7,0x63,0x8d,0x74,0x13,0x09,0x07,0x22,0x9d,0xde,0x88,0xac,0xa8,0xef, + 0x31,0x1f,0xec,0x6f,0xc8,0x87,0x32,0x46,0x06,0xfa,0x5f,0x76,0x0d,0xf8,0xf5,0x9e, + 0xf3,0x35,0x31,0x20,0x6a,0xfc,0x52,0xff,0xab,0x72,0xc4,0xed,0xe8,0xe1,0xbd,0xe6, + 0x6b,0x6e,0xc0,0x98,0x71,0xb1,0x5f,0xce,0x7a,0xaf,0x77,0xef,0x3d,0x9f,0x76,0xb9, + 0x19,0xdf,0xcd,0xf1,0x8b,0xaf,0xf1,0x16,0xb8,0x1d,0xe9,0x6e,0x94,0x53,0xcf,0x84, + 0x11,0xfe,0x31,0x00,0xe7,0x9b,0x03,0xf6,0x0f,0x12,0xdf,0x53,0x1f,0x1f,0xfd,0x2f, + 0x73,0x74,0x33,0x6e,0x25,0x54,0x67,0x96,0xb1,0xe5,0x2e,0xef,0xaa,0xce,0xaf,0x68, + 0xba,0xee,0xed,0xbb,0xe5,0xc9,0x03,0xff,0xd6,0x4d,0xe1,0x65,0xe7,0xbf,0xa1,0x69, + 0x05,0xc7,0xc6,0xfb,0x5f,0x25,0x0f,0x59,0x1b,0xf6,0xf8,0xda,0x32,0x16,0x2d,0xd8, + 0x41,0x5b,0x9a,0x66,0x85,0x49,0x21,0xee,0x43,0xeb,0x3c,0xd7,0x5e,0xbc,0x4a,0x7a, + 0x02,0x67,0xf2,0x96,0xd4,0x9a,0x7b,0x6b,0x2f,0x9e,0x7a,0x40,0xcf,0xb3,0x60,0x59, + 0x5b,0x88,0x34,0xe9,0xa6,0x98,0x11,0xd9,0xd2,0x74,0x5c,0x27,0x1e,0x6e,0xba,0x37, + 0x34,0xad,0xe0,0xd8,0x8d,0x8b,0x27,0xc8,0x3b,0x6e,0x95,0xf9,0xda,0xb3,0xf4,0xfe, + 0x4c,0x19,0xca,0x55,0xc2,0x3e,0xe9,0xe2,0x7c,0xca,0xb7,0x37,0x2b,0x0e,0xbe,0x87, + 0x5e,0x2f,0x74,0x3e,0x2d,0xf3,0x31,0x3e,0xed,0x18,0x5a,0xa0,0xf9,0x05,0xd0,0xbc, + 0xb9,0x32,0xe2,0xcb,0x8a,0x39,0xed,0x84,0x38,0x14,0x6a,0xee,0x21,0xb1,0xf1,0x81, + 0x4f,0xb1,0xe8,0xb1,0x53,0x7a,0x5d,0xbe,0x45,0x46,0x6f,0xae,0xb6,0xc8,0xb6,0x37, + 0xe3,0xf1,0x49,0xc7,0xb7,0xec,0x2d,0xf7,0xd6,0xd7,0x7c,0x7c,0xdb,0x64,0xbf,0x6a, + 0x3e,0x2d,0xed,0xce,0xed,0x90,0xf6,0xb5,0xc0,0x77,0xea,0x24,0x3e,0xec,0x78,0x99, + 0x8f,0x32,0x9a,0xf1,0xf1,0x75,0x62,0x21,0x85,0x54,0x3c,0xed,0xf0,0x49,0x51,0xce, + 0xb7,0x92,0x4a,0xdd,0x13,0x7b,0x56,0x0a,0xf5,0xa5,0x7b,0xeb,0x91,0x4a,0x3e,0x78, + 0x8f,0x66,0xc9,0x31,0x71,0xaa,0xcc,0x17,0xca,0x33,0xe6,0x3d,0x4f,0x2b,0x0d,0xf0, + 0xc6,0xc8,0x80,0x5d,0x9b,0x2f,0xcd,0x67,0xd9,0x00,0xcb,0x72,0xb6,0x71,0x44,0x96, + 0xe1,0xcb,0x31,0x3d,0x44,0x95,0x34,0xcd,0x59,0xe8,0xa1,0x79,0x48,0x8b,0xc6,0x6a, + 0xb7,0x1a,0xf1,0x95,0x30,0xb1,0x39,0x2a,0xb2,0xc5,0xb6,0xd9,0x6e,0x33,0x77,0x09, + 0xb9,0x35,0xbe,0x9b,0x23,0xfd,0xd8,0xf6,0x8d,0x53,0xe1,0x7a,0x7c,0x18,0x7f,0x9c, + 0xa4,0x11,0x33,0x13,0xb6,0xb3,0x56,0xc1,0xc7,0x87,0x67,0x54,0xfa,0x5f,0x77,0xf2, + 0xed,0xf7,0xf1,0x15,0x2a,0xf9,0x5e,0xb4,0x65,0xab,0x11,0x6a,0xee,0x20,0xe8,0xc1, + 0x36,0x4b,0xce,0xf9,0xf8,0x32,0xb4,0xec,0x84,0x46,0x48,0xf3,0x49,0xb6,0x10,0xf2, + 0xad,0x63,0x6c,0x39,0x1d,0xe7,0x6b,0xa9,0x47,0xf0,0xaa,0xf0,0xd7,0x80,0x99,0xb1, + 0x7d,0x35,0xc5,0x9b,0x7b,0x46,0xf0,0x05,0x91,0xaf,0x88,0xdb,0x93,0x7c,0x6a,0xba, + 0xfc,0xd8,0x78,0xed,0x15,0xc6,0x31,0xbd,0x27,0x6a,0xc1,0x80,0x17,0x17,0x1c,0x73, + 0x07,0x1f,0x4d,0xb3,0xff,0x4a,0xf0,0xd1,0xfa,0x0f,0x95,0x19,0x98,0xc8,0xd0,0x5a, + 0x0c,0xf1,0x49,0x7f,0x9d,0x88,0x5b,0x4e,0xe5,0x98,0x2c,0x98,0x17,0xc6,0x09,0x66, + 0x04,0x5f,0x5f,0x35,0xdf,0x39,0xbf,0xfb,0xe2,0x13,0x4d,0xb7,0xc0,0xf7,0xe7,0x9a, + 0x7c,0xed,0x16,0x27,0xc1,0x31,0xac,0xc3,0x43,0x73,0x5b,0x82,0xec,0x7a,0xe4,0x0b, + 0xaf,0x7d,0x07,0xd1,0x80,0x4e,0x05,0x5f,0x48,0x56,0x1e,0xd9,0xbc,0x24,0xf9,0xdc, + 0x7c,0x89,0xef,0x09,0x2d,0xdc,0x95,0x4f,0xa1,0xb4,0xe6,0xf6,0x8b,0x8d,0x9c,0x2c, + 0x99,0x73,0xd1,0xb2,0x7f,0x64,0x68,0x05,0x50,0xb4,0xe4,0xa7,0x10,0x48,0x08,0x53, + 0x60,0xa1,0x09,0x9b,0x3d,0xe4,0x55,0x27,0xf9,0x34,0x03,0xcf,0x54,0xbc,0x12,0xd0, + 0x52,0xe7,0xa6,0xe4,0x74,0x6a,0xf2,0xb5,0xd9,0x6e,0x76,0xbb,0xe0,0xeb,0x2b,0xc5, + 0xe7,0x2e,0xf9,0xfa,0x0f,0xc6,0x36,0xb0,0x4d,0xd3,0x8a,0xc4,0x16,0x04,0xd3,0x72, + 0xaa,0x17,0x02,0x9f,0xd0,0xda,0x74,0x50,0x36,0x7d,0x52,0x0f,0x56,0xf9,0xb6,0x57, + 0xd2,0x19,0x93,0xcf,0x98,0x93,0xab,0xc7,0x25,0xdf,0x31,0x4b,0x38,0x90,0xf9,0x19, + 0x5f,0x65,0x65,0x6b,0x3a,0x35,0xbf,0xfb,0xfe,0x47,0x6a,0x81,0x6f,0x7c,0xb0,0x94, + 0xfa,0xcf,0x58,0x05,0x9f,0xf7,0x4a,0xc2,0xbd,0x44,0xc4,0x03,0x8a,0xb6,0xa5,0x0a, + 0x3e,0x6d,0x22,0x61,0x39,0xae,0x7d,0xb4,0x1d,0x0b,0x2b,0x2e,0x1f,0xd7,0x9a,0xe0, + 0x73,0x28,0xca,0x3b,0xbb,0xe7,0x2b,0xa6,0x92,0x8d,0xf8,0x64,0x3c,0x78,0x8f,0x56, + 0x67,0xfd,0x7c,0xd0,0x1b,0x77,0xec,0x2b,0xbb,0xe0,0x13,0x17,0x36,0x86,0x76,0xc9, + 0x77,0x79,0x23,0x95,0x34,0x3c,0xbe,0xd0,0x17,0x8c,0x7f,0x70,0xe4,0x58,0x44,0x12, + 0x8a,0x7b,0x7c,0x7d,0xc4,0x17,0xf0,0xf3,0x05,0x27,0xd2,0x9e,0x87,0x68,0x93,0xf2, + 0x23,0x25,0xc7,0xe2,0x9d,0x21,0x9d,0x6f,0xcb,0xcb,0xe3,0x2d,0x11,0x73,0x28,0x5b, + 0xca,0xb5,0x6b,0x57,0x7c,0xc6,0xe5,0x52,0x2a,0x79,0x33,0xe2,0xf1,0x51,0x46,0x05, + 0xec,0x94,0xf2,0x3b,0xf8,0xce,0x52,0xb4,0x08,0x2c,0xd8,0xbe,0x06,0xde,0x63,0x5a, + 0x6c,0xd4,0xe5,0x13,0xb7,0xf0,0x2e,0x2f,0x63,0x7b,0x7c,0x4e,0x11,0x8f,0x1f,0x4a, + 0x3e,0xca,0xd6,0x12,0xe3,0x84,0xd6,0xf9,0x6e,0x5e,0x2e,0xa5,0x57,0xe6,0x87,0xc3, + 0x7e,0xbe,0x47,0xa2,0x95,0x17,0xc3,0xc1,0xdb,0xb6,0x1b,0xef,0xae,0x93,0xeb,0x55, + 0xf2,0x05,0xe7,0xd2,0x76,0x49,0x56,0xd7,0x1f,0xa8,0x0f,0x24,0xf7,0x94,0x0e,0xe2, + 0xf2,0x3d,0x12,0x3d,0x20,0xe7,0x23,0xbf,0x4b,0xf8,0x06,0x3c,0xad,0xf1,0x7d,0xe0, + 0xa4,0x57,0xcc,0x61,0xdd,0xc7,0xe7,0xd0,0x2c,0x0c,0xf1,0x75,0x05,0x4d,0x5b,0xc6, + 0x13,0x8d,0x77,0x0a,0x5a,0x05,0x9f,0x46,0x89,0xa4,0x35,0x4e,0xe3,0x2d,0x69,0x5b, + 0xdc,0xfa,0x49,0x99,0xaf,0xb0,0x8c,0xc7,0x63,0x82,0xcf,0x79,0x64,0x18,0x57,0xe3, + 0xbe,0x06,0xd2,0x52,0x7c,0xe1,0x7c,0xc9,0x31,0x3f,0x1f,0x11,0x04,0x38,0x5f,0xc0, + 0xcc,0xb3,0x12,0x37,0x2d,0x85,0xd6,0x2d,0xd0,0x12,0x36,0x0f,0xbd,0x52,0x87,0xcc, + 0xbc,0x0c,0x3f,0xbc,0xb4,0xb4,0x7c,0x98,0xf7,0xca,0x7c,0xb3,0xf2,0xda,0x3e,0x6a, + 0xb8,0x98,0x51,0x47,0xc2,0x1f,0x01,0x91,0x6f,0x7a,0xde,0x6c,0x02,0xf8,0x01,0x4b, + 0x17,0x52,0x63,0x11,0x59,0xc1,0x6e,0xe7,0xa9,0x21,0x1f,0xd6,0xdd,0x60,0x5a,0xb6, + 0x17,0xfa,0x82,0x60,0x96,0xf3,0xf9,0x3b,0x8d,0x78,0xde,0xdf,0x5f,0x25,0xaa,0xf9, + 0xdc,0x8b,0x01,0xc9,0x07,0x79,0xbe,0xde,0xe4,0x52,0xc7,0x3e,0xd7,0xbb,0xb5,0xcb, + 0x8d,0xdf,0x43,0xae,0xb3,0x5c,0x21,0x35,0xe7,0xe7,0x2b,0x49,0x3e,0x67,0x08,0x63, + 0x08,0xe3,0x5f,0xcb,0xd1,0x7a,0x35,0x1e,0xc2,0x0e,0xbe,0xb3,0x16,0x73,0x57,0xea, + 0x7d,0x7c,0xb2,0xe3,0xa5,0x50,0xe5,0xfa,0x02,0x6f,0xb8,0x54,0x84,0xed,0xe7,0xdb, + 0x3f,0x3d,0x7b,0x24,0x76,0xe1,0x68,0x63,0xfb,0x7d,0xca,0x0a,0x56,0xce,0x8c,0xca, + 0x37,0x4c,0xde,0x50,0xb8,0x69,0x6c,0x1a,0xe9,0x06,0xb1,0x06,0x69,0xe0,0x77,0x86, + 0x5c,0x13,0xcf,0x5e,0xf3,0xf5,0xf9,0x20,0x96,0xe3,0x4b,0x5e,0x40,0x4b,0xd8,0xa2, + 0x6d,0xc9,0x8e,0x8d,0xf8,0xee,0xf9,0xf9,0x30,0xb0,0x1c,0x62,0xcc,0xd7,0x40,0xde, + 0xbe,0x81,0x6c,0x23,0x17,0x1a,0xc0,0x99,0xf3,0xb1,0x3c,0xf2,0x15,0x92,0x6e,0x05, + 0x7b,0x7c,0xe8,0xb9,0x14,0x3c,0xae,0x62,0xa3,0x2a,0x1a,0xa7,0xe9,0xb1,0xbf,0xab, + 0xe0,0x8b,0xe7,0x50,0x2b,0x14,0x72,0x3d,0x03,0xde,0xa9,0xe6,0x2b,0xe0,0x3b,0x53, + 0x6e,0x05,0xb8,0x63,0x61,0x28,0xcc,0x53,0xc8,0x2e,0xfb,0xc7,0xd5,0x8f,0x8f,0xbe, + 0x39,0xaf,0xff,0xbd,0xfe,0x30,0x70,0xda,0x34,0x63,0xd8,0xce,0x2c,0x2b,0x65,0x48, + 0x0f,0xa6,0x11,0x01,0xe7,0xfb,0x48,0xf2,0xc5,0x99,0x5c,0x60,0x73,0x1e,0x56,0xf0, + 0xa5,0xbd,0xbe,0xc2,0xe3,0x8b,0x57,0xf3,0xb9,0x9d,0x09,0xf1,0xb9,0xf2,0x5e,0xf8, + 0x20,0x76,0xe1,0xed,0x37,0xcd,0x7d,0x9f,0xbf,0x5d,0xdf,0x7c,0xa6,0x79,0x13,0x0d, + 0x9e,0xb7,0x56,0x4c,0x69,0xc0,0x80,0xdb,0xc2,0x3e,0x12,0xaf,0x44,0xc1,0xe9,0x84, + 0xc8,0xd9,0x79,0x44,0x71,0x7f,0xd2,0xe3,0x4b,0xd4,0xe4,0xe3,0xbe,0x79,0x6c,0x95, + 0x7f,0xd2,0xd9,0x96,0x2e,0xf3,0x41,0xc2,0xe5,0x73,0x0a,0x5e,0x7c,0xd6,0x62,0x27, + 0x62,0x03,0x17,0xde,0x32,0x0f,0xd7,0x73,0x10,0xd3,0xbc,0xbd,0x34,0x8d,0xb7,0xe4, + 0xb1,0x82,0x0d,0xf1,0x8e,0x19,0xc0,0x61,0xa7,0x4d,0x3b,0x13,0x79,0xc7,0x26,0xef, + 0x9b,0x30,0x33,0x54,0x29,0x4e,0x91,0x37,0xa5,0xc9,0xbc,0xb8,0x4a,0x30,0xf4,0xc1, + 0x1d,0xfd,0xbc,0x01,0x7b,0x7c,0xd5,0xda,0xa0,0x6d,0x27,0x26,0x22,0xbe,0x94,0x4d, + 0x9d,0x9d,0xc8,0xef,0x6f,0x16,0xef,0x34,0x2d,0xab,0x94,0xf4,0xda,0xeb,0xfe,0xf9, + 0xfe,0xd8,0x89,0xee,0xf0,0x74,0x3d,0x3e,0xb4,0xde,0xd2,0x12,0x05,0x76,0xac,0x60, + 0x34,0x20,0x07,0xd4,0xe8,0xf3,0x4d,0xce,0x87,0xfd,0x00,0x75,0x5e,0x01,0xc3,0xa4, + 0xa6,0x96,0xfa,0x07,0x37,0xef,0x19,0x79,0x15,0xa0,0x3c,0x99,0xed,0x05,0x18,0x53, + 0x5e,0x6c,0xc3,0x2d,0xff,0x96,0xc8,0x95,0xc8,0x4e,0xea,0x2f,0x5e,0xf5,0x0e,0xc6, + 0x2e,0xbc,0xff,0x96,0xf9,0x71,0xec,0xe8,0x7c,0x6c,0xc7,0xfc,0xb8,0x68,0x7a,0xe6, + 0xed,0x3b,0xa9,0xa4,0x2d,0xf8,0x72,0xc9,0xb9,0xe1,0x88,0xee,0xe3,0x3b,0x23,0x5e, + 0x6c,0x00,0x8e,0x4e,0x9b,0xd8,0x6f,0x9a,0x62,0xa4,0xf2,0xec,0x7c,0x63,0xe5,0xe1, + 0xc1,0xc4,0xf4,0xc7,0x83,0x51,0xe3,0xc4,0x8d,0xc1,0xf9,0xe9,0xda,0xd3,0xf8,0x4b, + 0xa9,0x54,0x92,0x37,0x0a,0xb4,0xfb,0x4a,0x72,0x2e,0x1a,0xd1,0xc3,0xf4,0x81,0x12, + 0xff,0xa6,0x09,0xff,0x91,0x7d,0x4a,0x10,0xf3,0x36,0x64,0xae,0x9a,0xbc,0x0a,0x10, + 0xf6,0x8a,0x09,0x97,0x77,0x34,0x37,0x91,0xd8,0x96,0xd3,0xf8,0x92,0x7b,0xda,0x67, + 0x9a,0xff,0xc4,0xf8,0x32,0x7d,0xe1,0xdf,0x75,0xe9,0x52,0xff,0xcd,0xb8,0x7c,0x85, + 0x95,0x79,0x23,0x1a,0xe9,0xf6,0xa6,0x7d,0x08,0x4e,0xcc,0xea,0x84,0x03,0x11,0xf4, + 0x1d,0xbd,0x4a,0x6e,0x91,0xd5,0x57,0xe4,0x75,0x7f,0x0a,0x77,0xb7,0x3c,0xaf,0x04, + 0x97,0x6f,0x9b,0x4b,0x57,0xfe,0x74,0xe7,0x5f,0x87,0x97,0xb0,0x99,0xd5,0x10,0xbd, + 0xfc,0xa7,0xa4,0x73,0x0a,0x03,0x8e,0x9d,0x8a,0x44,0xea,0x95,0xf6,0xdc,0xd5,0x11, + 0x5f,0x4a,0xdd,0xb9,0x7f,0xd8,0x38,0x31,0x78,0xa7,0x1e,0x5c,0x7a,0x25,0x23,0xdd, + 0x9e,0xa6,0x99,0x56,0x52,0xa6,0x71,0x29,0x1a,0x8d,0x9e,0xda,0xb1,0x12,0xf1,0xc6, + 0x40,0x74,0x20,0xfa,0x46,0xf3,0x15,0x8b,0x5d,0xea,0x24,0x47,0x48,0xc6,0x52,0x75, + 0x94,0xcb,0x61,0x64,0x77,0x3f,0x21,0x71,0x78,0x0d,0x23,0xa0,0x61,0x8c,0x10,0x23, + 0xca,0x5b,0x8a,0x88,0xbe,0x1b,0x8d,0x5e,0x92,0x27,0xbd,0x2b,0xb8,0x79,0x57,0xae, + 0x54,0xb8,0x2b,0x16,0xd1,0x2a,0xbd,0xeb,0xe6,0x50,0xb1,0x2b,0xee,0x7f,0x3f,0x4d, + 0x1d,0xd0,0xff,0x72,0xf5,0x85,0xdd,0x5a,0xda,0x8b,0xea,0x18,0xa8,0x1c,0x22,0x4c, + 0xd6,0x6e,0xab,0xcf,0x5f,0x19,0xab,0xb9,0x7c,0xdf,0xa1,0x38,0xc4,0x67,0xe5,0xea, + 0x19,0xfb,0xf9,0xab,0x05,0xbc,0x42,0xa6,0xcc,0xc7,0x24,0x31,0x75,0xfa,0x3f,0x3e, + 0x5c,0x2e,0x97,0x6f,0x48,0x56,0x65,0x3e,0xd9,0x04,0x7f,0x4e,0x2a,0xec,0xfc,0xd3, + 0xb6,0x9f,0x1b,0x60,0xf5,0x12,0x3b,0x75,0xf8,0x96,0xe8,0xc8,0x6d,0xb7,0x3f,0x77, + 0xc4,0x38,0xc0,0xf2,0x6f,0x7c,0xe7,0x9d,0xca,0xf3,0x4d,0x2f,0x57,0xca,0xa9,0x95, + 0xab,0xd8,0x54,0xc1,0xb9,0x88,0x75,0x2e,0x3c,0x2f,0x59,0xf4,0xed,0x01,0xfe,0x53, + 0x63,0x81,0x5c,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49, + 0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49, + 0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49, + 0xe9,0x67,0xac,0xff,0x03,0xdc,0x41,0xd4,0x19,0x76,0x96,0x00,0x00, diff --git a/board/esd/hh405/logo_320_240_8bpp.c b/board/esd/hh405/logo_320_240_8bpp.c new file mode 100644 index 0000000..c2c59c6 --- /dev/null +++ b/board/esd/hh405/logo_320_240_8bpp.c @@ -0,0 +1,521 @@ + 0x1f,0x8b,0x08,0x08,0x72,0xd1,0xe2,0x40,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x2d,0x48, + 0x65,0x72,0x5f,0x64,0x74,0x5f,0x33,0x43,0x5f,0x33,0x32,0x30,0x78,0x32,0x34,0x30, + 0x5f,0x38,0x62,0x70,0x70,0x2e,0x62,0x6d,0x70,0x00,0xec,0x5d,0x0f,0x6c,0x1b,0xd7, + 0x79,0xff,0x12,0x09,0xc5,0xc4,0xd2,0x01,0x26,0x0a,0x03,0x56,0x88,0x1e,0x59,0xa9, + 0x14,0x43,0xa8,0xb6,0x10,0x08,0x72,0x4d,0x10,0xf4,0xe6,0x28,0x09,0x90,0x2a,0x02, + 0x1c,0x69,0xe2,0x98,0x6a,0xbc,0xcd,0xa3,0x38,0x33,0x64,0x4c,0xd7,0x54,0xe4,0x36, + 0xd3,0x6c,0xd4,0x70,0x9a,0xc0,0xf0,0xcc,0xce,0x73,0xb3,0x2d,0xd1,0x42,0x25,0xd0, + 0x1c,0x29,0x11,0x27,0x42,0x15,0x25,0x81,0xf3,0x5a,0x36,0x54,0x77,0x66,0xa8,0x0e, + 0x72,0xed,0x25,0x59,0x24,0xb4,0x69,0xfe,0xac,0x68,0xa7,0x85,0x4a,0x42,0xbb,0x89, + 0x77,0x20,0xf6,0xbd,0x3f,0x47,0x1e,0x29,0xc9,0x8a,0x5d,0x2b,0x8e,0x8b,0xf7,0x3b, + 0xfe,0xb9,0xf7,0xee,0xbd,0xef,0xde,0xfb,0xbd,0xdf,0xfb,0xbe,0x77,0xf4,0x9d,0xbc, + 0xfb,0x81,0xb6,0x96,0xdb,0x80,0xa0,0xad,0x1a,0xc0,0x8a,0xdf,0x7f,0x88,0xc9,0x15, + 0xfc,0xbe,0x0d,0x7e,0x87,0xe6,0x43,0xf3,0x6d,0xd0,0xb0,0x0d,0xe8,0x1b,0x58,0x51, + 0xa8,0xbe,0xbd,0x1a,0x5a,0x8f,0x2e,0x43,0xfd,0xee,0x41,0x18,0x7a,0xfa,0x9f,0xa0, + 0xfb,0xc1,0x6e,0x18,0xf9,0x8f,0x2b,0xd0,0xbc,0x77,0x04,0xbc,0x67,0x3e,0x84,0xba, + 0x2f,0xee,0x84,0xc1,0xa3,0xc7,0xe0,0xe2,0xc5,0x57,0x61,0x64,0x7a,0x1e,0x9a,0xef, + 0x6c,0x86,0xfa,0x7b,0x9e,0x84,0xc6,0xbd,0x73,0xd0,0xf1,0xd4,0x7b,0x70,0xf1,0x57, + 0x0a,0x34,0x1e,0xbc,0x08,0x75,0x4d,0x3d,0x70,0xf6,0xdf,0x52,0xa0,0xaf,0x33,0x43, + 0xf7,0xc1,0x13,0xd0,0xdc,0xf5,0x04,0x1c,0x4b,0xe6,0xa1,0xfd,0x1b,0x67,0xa1,0xfb, + 0xe8,0x1c,0xcc,0x2d,0x2c,0x41,0xf0,0xd9,0x25,0x70,0xdc,0x7d,0x2f,0x34,0x3e,0xfa, + 0x36,0xd4,0x7f,0xc5,0x0b,0x43,0x2f,0x9e,0x85,0xe5,0xf7,0x72,0x50,0xff,0x85,0x7a, + 0x38,0x36,0x7a,0x11,0x96,0x7e,0xfe,0x36,0x0c,0xfd,0xeb,0xcf,0xa0,0xe3,0xe4,0x12, + 0x9c,0xf8,0x9b,0x53,0xd0,0xfb,0xe7,0x7b,0xa1,0xb5,0x6d,0x07,0xe8,0x7f,0x7f,0x3b, + 0x04,0x1f,0x09,0xc1,0xd9,0x9f,0x2a,0xd0,0xf1,0xe0,0x1f,0x43,0xfd,0x17,0x9b,0xe0, + 0xec,0xbf,0x5f,0x84,0xc6,0x9e,0x97,0xa0,0xf1,0xb1,0x65,0xe8,0x9f,0xcc,0x43,0xfd, + 0xfd,0x27,0xa0,0xf7,0x1f,0xde,0x84,0xe5,0xcb,0x1f,0x43,0xfb,0xe3,0xff,0x05,0x8d, + 0x0f,0xcf,0x43,0xf5,0xe7,0x6b,0xa1,0xdd,0x77,0x02,0xea,0xda,0x82,0xf0,0xce,0xbb, + 0xef,0xc2,0xd0,0xb9,0x8f,0xa1,0xff,0xd0,0x37,0xe1,0xec,0x1b,0x0a,0x8c,0xbf,0x14, + 0x83,0xa1,0xe7,0x47,0xa0,0x7f,0xf4,0x2d,0xe8,0x3f,0x79,0x16,0xea,0xb6,0xf5,0x42, + 0xfb,0xfd,0x5f,0x85,0xba,0x2f,0x98,0xe0,0xc4,0xcb,0x79,0xe8,0xf6,0x61,0x1f,0xbf, + 0x36,0x0e,0xcd,0x9d,0xc7,0xc0,0x71,0x7c,0x19,0xa6,0x5e,0x55,0xa0,0x75,0xff,0x14, + 0x9c,0x7d,0x79,0x0e,0x2e,0xbe,0xfb,0x31,0x38,0xec,0x0e,0xa8,0xb7,0x39,0xa0,0xf5, + 0xaf,0xdf,0xc4,0x73,0x9f,0x06,0xef,0xb3,0x6f,0x42,0xdd,0x1d,0x75,0x30,0xfe,0xca, + 0x0a,0xb4,0x3e,0x18,0x84,0xee,0x1e,0x17,0x34,0x6f,0xdb,0x06,0xad,0x07,0xd1,0xb6, + 0xa1,0x0e,0xbc,0x78,0x8e,0xf9,0x57,0xb1,0x5f,0xa7,0xfe,0x0e,0x7a,0x7d,0x41,0x50, + 0x0a,0x0a,0xe8,0xf5,0x7a,0x70,0x1c,0xfd,0x29,0x4c,0xfd,0xe4,0x23,0x70,0x3c,0x3c, + 0x0e,0x75,0xb6,0x76,0x38,0xf6,0xed,0xe3,0x70,0xf1,0x8d,0x45,0x98,0x9a,0x49,0x42, + 0x73,0xdf,0x59,0x78,0xe7,0x57,0xbf,0x84,0xf9,0x85,0xf3,0x70,0xec,0x29,0x6c,0xcb, + 0xc0,0xcf,0x61,0xf9,0x83,0x0f,0x40,0xbf,0x75,0x07,0x34,0xda,0xb6,0xc1,0xfc,0x2b, + 0x3f,0x86,0xc6,0x47,0xfe,0x13,0xea,0x9d,0x21,0x18,0x79,0xe5,0xff,0x60,0xf0,0xf0, + 0xb7,0x60,0x7c,0x72,0x0a,0x86,0xce,0x4c,0x41,0xdd,0x5d,0x5e,0x68,0xfc,0xd3,0x59, + 0xe8,0x8d,0x7e,0x08,0xcd,0xbb,0xbd,0xd0,0x8a,0xf6,0x83,0xff,0x92,0x07,0xbd,0xa5, + 0x1d,0xba,0x9f,0xcd,0x43,0x63,0xd7,0x3f,0x42,0xc7,0xbd,0x1d,0xd0,0xe8,0xfc,0x13, + 0xe8,0xde,0x3f,0x04,0xed,0x78,0xfc,0xd8,0x74,0x1e,0x8e,0x3d,0x3f,0x0f,0x8e,0x07, + 0x07,0xa1,0xfb,0x3b,0x6f,0x82,0xf7,0xe1,0x20,0x78,0x8f,0x4e,0xc1,0xe0,0x53,0x67, + 0xa1,0xfd,0xa1,0x7e,0x70,0x1c,0x5e,0x82,0x66,0x67,0x37,0xb4,0x23,0x1f,0xc7,0xbe, + 0x33,0x0a,0xa7,0xff,0xfe,0x69,0x98,0x7f,0x5b,0x81,0xd3,0x67,0xe6,0x60,0xf0,0xf8, + 0x10,0x0c,0x4d,0xce,0x41,0xeb,0xfd,0xdf,0x80,0xd3,0x49,0x1c,0x13,0x3c,0x57,0xeb, + 0x63,0x17,0xe1,0x9d,0x0f,0x14,0xac,0x37,0x0f,0x43,0x2f,0x2f,0x43,0xf0,0x60,0x3f, + 0x74,0x1c,0x47,0x1b,0x7d,0x53,0xd0,0x7e,0x12,0x35,0xb7,0xf5,0x0f,0xc0,0xe1,0x74, + 0x42,0xff,0xd1,0x21,0xe8,0x3e,0x7e,0x11,0xba,0x07,0xc6,0xe1,0x9d,0xf7,0x50,0x4f, + 0xbb,0x83,0x30,0x3e,0x3d,0x07,0x8d,0xf7,0x9e,0x00,0xef,0x5e,0x2f,0xcc,0x9d,0x7b, + 0x05,0x3a,0x8e,0xa2,0xf6,0x02,0x3f,0x80,0x8e,0xbd,0x83,0xd0,0xd1,0xf1,0x00,0x9c, + 0x4e,0x7f,0x08,0xbd,0x0f,0xf5,0x42,0xeb,0x5d,0xad,0xd0,0x7b,0xea,0x22,0x1c,0x3b, + 0x7e,0x02,0xda,0x0f,0x4e,0xc1,0xc8,0x8b,0xe3,0x30,0xf7,0xf2,0x8f,0xe0,0xf4,0xa9, + 0xef,0xc2,0xd2,0x1b,0x4b,0x90,0xff,0x20,0x0f,0x75,0x5b,0xb7,0x83,0xfe,0x73,0x7a, + 0x18,0x3f,0x7f,0x05,0x82,0x2f,0xe2,0xd8,0x3e,0x8d,0x9c,0x84,0xcf,0xe3,0xf8,0x61, + 0x5f,0xee,0xb9,0x07,0x1a,0xed,0x7f,0x06,0x23,0xc9,0x25,0x68,0xfc,0xd2,0x97,0xa0, + 0xf9,0xaf,0x96,0x61,0xf0,0x7b,0x39,0x68,0x7c,0xe0,0x49,0xc8,0x7f,0x74,0x19,0x75, + 0x7a,0x00,0x06,0x1f,0x1b,0x84,0xb9,0x37,0xf2,0x30,0x32,0x32,0x02,0xf5,0x77,0xf5, + 0x42,0xb3,0x67,0x14,0x1c,0x07,0xc7,0x61,0xe9,0xbf,0x91,0xc7,0xaf,0x7e,0x17,0x46, + 0xce,0x8c,0x83,0xf7,0xb9,0xf7,0xa1,0xae,0xf1,0x7e,0xe8,0xf0,0x0c,0x42,0xab,0x6f, + 0x1c,0x3a,0x4e,0xfd,0x2f,0xd4,0xdf,0x7b,0x1a,0x1a,0x7d,0xf3,0xb0,0x84,0x73,0xe4, + 0xc4,0x59,0x2c,0x3b,0xb0,0x0c,0x4b,0x6f,0x2d,0xc3,0xdc,0xcf,0x14,0xe8,0x7f,0x11, + 0xfb,0xbf,0xad,0x03,0x5a,0x0f,0x2f,0x43,0x6b,0x0f,0xf2,0xfd,0x90,0x17,0xf5,0x82, + 0x7a,0x7a,0x74,0x1e,0xea,0x7e,0xaf,0x11,0xbc,0xa7,0xe6,0x41,0x7f,0x47,0x3d,0x38, + 0xbe,0xbd,0x0c,0xf3,0x3f,0x59,0x82,0x63,0xa7,0xa6,0x90,0x8f,0x41,0x68,0xde,0x3f, + 0x0f,0xa7,0x7f,0x84,0x5a,0xdc,0x3b,0x04,0x5e,0x9f,0x0f,0xa6,0x26,0x13,0xd8,0xa6, + 0x20,0x9c,0x98,0x5e,0x86,0xf6,0x07,0xfb,0xa1,0x1f,0x39,0x6e,0xdc,0xda,0x08,0xed, + 0xce,0x76,0xd4,0xea,0x3c,0x6a,0xe9,0x1d,0xd4,0x8c,0x82,0x1a,0x19,0x84,0x11,0x1c, + 0x9f,0xea,0xcf,0xe1,0x7c,0x47,0x9b,0x43,0xcf,0x3e,0x0f,0x5e,0xe4,0xc2,0x23,0x20, + 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, + 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, + 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, + 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, + 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, + 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0xf0,0x19,0xc2,0x58,0x2c,0x16,0x73,0xde,0xec, + 0x46,0xdc,0xc2,0x70,0x02,0x40,0xef,0xcd,0x6e,0xc4,0x2d,0x0c,0xc2,0xdf,0xf4,0xcd, + 0x6e,0xc4,0x2d,0x8c,0x7e,0xe4,0xcf,0x72,0xb3,0x1b,0x71,0x0b,0x43,0xcc,0xdf,0x6b, + 0x46,0x70,0xc6,0xef,0xd7,0xed,0xe3,0x09,0x36,0x7f,0xe5,0x86,0x90,0xce,0x54,0x2a, + 0x21,0x37,0x60,0x09,0x9e,0x96,0x65,0xf5,0x45,0x53,0xec,0x0b,0x77,0xfa,0x42,0x0d, + 0x6c,0x47,0x9b,0x2d,0xab,0x47,0x3d,0x95,0x3b,0x26,0x9d,0xdf,0x54,0x2c,0x8e,0xa9, + 0x90,0xdf,0xae,0x39,0x5f,0x5f,0xc8,0x3f,0x63,0xd2,0x16,0x57,0x2d,0x69,0x0c,0x55, + 0x18,0xf4,0x78,0x66,0x49,0xad,0x75,0x4f,0xb8,0x59,0xc8,0xa6,0x2e,0x49,0xa0,0x48, + 0xee,0x54,0x81,0x9e,0x88,0xce,0x5f,0x43,0xa7,0xa4,0x48,0xd1,0x3c,0xe7,0x74,0x9f, + 0x57,0xdf,0x95,0x04,0xc9,0x1c,0x9b,0xc2,0x36,0x5a,0xf5,0x69,0x75,0x1b,0x96,0x3d, + 0x3a,0x57,0x5a,0xef,0x25,0xad,0xac,0xd2,0x4b,0x49,0x69,0xd8,0x20,0xc7,0xf5,0x69, + 0xa7,0xc7,0xa3,0xd3,0xb3,0x6c,0x9b,0x3e,0x1d,0x27,0xb4,0x98,0xac,0x7a,0x7d,0x8e, + 0x98,0x72,0x62,0xb5,0x15,0xfc,0xb6,0x8f,0xba,0x93,0x8a,0x39,0x67,0x5f,0x49,0xeb, + 0xad,0x41,0x8f,0xc1,0xea,0xc6,0xf3,0x75,0x75,0xb2,0x16,0x78,0xec,0xf9,0xb4,0xa4, + 0x28,0x92,0xb9,0xe0,0x99,0x71,0xe9,0xd3,0x19,0x9a,0xd7,0xa4,0xd7,0x5b,0x4d,0xc4, + 0xb0,0x3e,0x4d,0x0c,0x67,0xd2,0x7a,0x17,0x1d,0x2e,0xbf,0x5e,0xaf,0x9f,0xa4,0x25, + 0xfc,0xa3,0x51,0x29,0xa9,0x48,0xe9,0xd1,0x10,0x39,0x0f,0x36,0xc0,0x49,0xb3,0xe3, + 0x69,0x7d,0xcf,0xa6,0xf2,0x67,0x03,0x15,0x29,0xd2,0x55,0xa2,0xbf,0x94,0xc4,0x32, + 0xe2,0x54,0x21,0xa1,0xb4,0x5a,0x40,0xb2,0x7b,0x82,0xee,0x62,0x71,0x30,0xcb,0x1e, + 0x7f,0x12,0xc0,0x46,0x8c,0x28,0xac,0x40,0x04,0x6b,0x62,0xbb,0xfd,0x0a,0xcb,0xae, + 0xc6,0x2c,0xd2,0x4d,0x3b,0xd6,0x8a,0x11,0x5b,0x11,0x2c,0x94,0xc5,0xf4,0x7e,0x66, + 0xc1,0x95,0xa1,0x56,0xb2,0xaa,0xc5,0x51,0x59,0x7b,0xbe,0x69,0x8f,0x0e,0xcd,0x8f, + 0xd2,0x56,0xa6,0x00,0xdc,0xd8,0x3c,0x3f,0x30,0xc3,0xa3,0x68,0x78,0x86,0xe4,0x8f, + 0xe1,0x99,0xf2,0x64,0xa7,0x4a,0x52,0x8d,0x0c,0x63,0x6a,0x17,0x7e,0x17,0x48,0xb6, + 0x8c,0x67,0xee,0xdc,0x54,0xfe,0xbc,0xd8,0x14,0xb3,0x39,0x49,0xce,0x1c,0xc3,0xe6, + 0x3b,0x29,0x13,0xee,0xcb,0x7a,0xf2,0x3d,0x41,0xfa,0x6e,0xc6,0x9d,0x74,0x93,0xad, + 0x3a,0x4d,0xb8,0x30,0x11,0xfe,0x14,0xe9,0x17,0x12,0x22,0x2d,0x7b,0x42,0x8c,0xa8, + 0x04,0x56,0x97,0xaa,0x6d,0xc3,0x49,0x62,0xc6,0x87,0x14,0x00,0xeb,0x15,0xf2,0xd7, + 0x55,0xc6,0x5f,0x15,0xe3,0x6f,0x94,0x98,0x1c,0x1d,0x45,0x8b,0xf8,0x2d,0x7b,0x7c, + 0x49,0x7d,0x93,0x8d,0x0e,0x5a,0x15,0x96,0x25,0xf4,0x25,0xf5,0x29,0xbd,0x54,0xf0, + 0xe8,0xd0,0x7c,0xae,0xc8,0x1f,0x4e,0x07,0x1d,0xe7,0xaf,0x09,0xcf,0xa7,0xa3,0xfc, + 0xf1,0x33,0x91,0x66,0x27,0xad,0x39,0x5b,0xca,0x4d,0xf9,0x2b,0x14,0xf9,0xeb,0x42, + 0xfe,0x36,0x75,0x06,0x67,0x63,0x59,0xbb,0x2c,0xeb,0x72,0x84,0xb6,0x04,0xd3,0x1f, + 0x51,0xa2,0x6c,0x49,0xb2,0x36,0xa2,0x3e,0x95,0xcc,0x2c,0x69,0x8a,0xa1,0xda,0x4e, + 0x29,0x01,0xf3,0x98,0x9d,0x02,0x89,0x62,0xfa,0xab,0xc1,0x4c,0x32,0x2d,0x0b,0x84, + 0x83,0x0e,0x8f,0x4a,0xab,0xa7,0x99,0x6a,0x76,0x95,0xfe,0x64,0x3d,0x80,0x1e,0xb5, + 0x6d,0x22,0xc6,0xf4,0x78,0x38,0xe1,0xe1,0x7d,0xc6,0x42,0x0e,0x72,0x02,0x03,0x76, + 0x79,0xa6,0xc1,0xe3,0x97,0xb4,0xfc,0xad,0xa5,0x3f,0x32,0x72,0xc8,0x9f,0x8c,0xa4, + 0xbb,0xfb,0x49,0x86,0xa9,0x2a,0xa7,0xe5,0xcf,0x23,0x6d,0xb6,0xfe,0xd4,0xc1,0x39, + 0x82,0xa7,0xac,0x61,0x03,0xe9,0xd6,0xa9,0x19,0x16,0x8f,0xc9,0xcc,0x74,0xa9,0x16, + 0x35,0xc5,0x31,0xfb,0x72,0x90,0x57,0xe2,0x13,0x35,0xc3,0xe7,0xa9,0x67,0x02,0x0f, + 0x8e,0xb1,0x6e,0x72,0xfd,0x49,0x6b,0xe8,0x4f,0xbe,0x04,0xd0,0x4c,0x92,0x0d,0x6e, + 0xca,0x1f,0x03,0xd1,0x56,0x5c,0x9e,0x4d,0xf3,0xb1,0xa0,0x59,0x65,0xf3,0x57,0xa3, + 0x3f,0xc2,0x5f,0x1f,0xc9,0xe7,0xf3,0xd7,0xc7,0xb4,0x5b,0x44,0x99,0xfe,0xac,0x37, + 0x92,0xae,0x75,0x11,0x06,0x3a,0xd6,0x4e,0xe0,0x5d,0xa5,0x6d,0x68,0xa2,0x0d,0xcc, + 0x6a,0xcb,0xcd,0xa4,0xf9,0xc4,0x26,0xe0,0xfa,0xcb,0xaa,0x8b,0x6e,0xb2,0xe3,0x2f, + 0x66,0xaf,0x9e,0xbf,0xdc,0xff,0x21,0x1b,0x66,0x2a,0x9f,0x18,0x52,0xc6,0x2c,0xc9, + 0xba,0x18,0x3d,0x33,0x61,0x28,0xad,0x8e,0x69,0xf9,0xfc,0x35,0x95,0xf4,0xd7,0xa4, + 0xf5,0x7f,0x0e,0xda,0x78,0x77,0x83,0xa6,0x91,0xbb,0xe0,0x53,0x9b,0xbf,0x1c,0xb3, + 0x2e,0xa6,0x19,0x12,0x7f,0x59,0xc8,0x4b,0x60,0xd3,0x52,0x94,0x4f,0x0c,0x76,0x2e, + 0x3d,0xd9,0xe2,0xa4,0x8d,0x63,0xc4,0x05,0x86,0x59,0x2d,0xae,0x3f,0x13,0x0a,0x2a, + 0xd9,0x93,0x35,0x24,0x08,0x3f,0xa1,0x52,0x37,0x9b,0xd7,0xd6,0x9f,0x27,0x8b,0xd5, + 0xa2,0x19,0x67,0xa2,0xe3,0x08,0xe7,0x6f,0x26,0x6c,0xa5,0xfe,0xbf,0x8a,0x2a,0x49, + 0x1d,0x1d,0x8f,0x4e,0xaa,0x88,0x1f,0x5a,0xfd,0x31,0xff,0xc7,0xe6,0xef,0x28,0x71, + 0x99,0x2e,0xde,0xcc,0x89,0x4a,0xff,0xf7,0x29,0xb0,0x67,0xb0,0x92,0x78,0xe1,0x64, + 0xfa,0x9b,0x2c,0x36,0x7e,0xb8,0x14,0x1b,0x69,0x7c,0xa5,0x63,0xee,0xc4,0x03,0x49, + 0xda,0xba,0xa2,0xd0,0x12,0xe9,0x52,0x21,0x3f,0xf3,0x7f,0xea,0xfc,0x5d,0xc3,0xff, + 0xa1,0x5e,0x08,0x5b,0x2c,0x66,0x13,0xfe,0x22,0x2c,0x78,0x4a,0x36,0xd9,0x43,0xfe, + 0x77,0xbc,0xd1,0x22,0x7f,0x4a,0xc5,0xfc,0xd5,0xea,0x8f,0xf2,0x97,0x60,0xa3,0xde, + 0xa3,0x6d,0x65,0x67,0xa5,0xff,0xdb,0x6c,0xfd,0xd9,0x2d,0x71,0x7a,0x62,0x57,0x90, + 0xf1,0x47,0x17,0x04,0x1e,0x03,0xee,0x1d,0xf1,0xf8,0xb0,0x0b,0xf1,0xcb,0x29,0xdc, + 0xd2,0xac,0x0b,0x88,0x5e,0x64,0xcd,0x6d,0x20,0x7b,0xea,0x42,0xc5,0xb3,0xcf,0x12, + 0x4b,0xbb,0xdd,0x6e,0x6c,0xad,0x12,0x2a,0xc5,0x0f,0xe4,0x4f,0x21,0xdd,0xdc,0xa7, + 0xae,0x22,0xb8,0xfe,0xb0,0x84,0xcd,0x1a,0xc5,0xf2,0x49,0xca,0xdf,0x18,0xa5,0xcf, + 0xdc,0x64,0xe0,0x67,0x8d,0x15,0xf9,0x93,0xd4,0xc4,0x6a,0xfd,0x91,0x38,0xc5,0x26, + 0x49,0x9e,0x06,0xb9,0xe4,0x30,0x36,0x32,0x75,0xb9,0x8b,0xd6,0x28,0x30,0x67,0xfe, + 0xa9,0xe8,0x6f,0xd6,0x62,0x66,0xe3,0x96,0x46,0xe5,0x50,0xfe,0xe2,0x74,0xc0,0x2c, + 0xb8,0xf7,0x84,0x67,0x46,0x52,0x47,0x12,0xdb,0xe8,0x62,0x35,0xe4,0x3c,0x1e,0x8a, + 0x12,0x62,0x54,0xfd,0xd1,0x5c,0x93,0xdd,0x8e,0xb5,0x93,0xfe,0x92,0x4c,0xaa,0x99, + 0xa6,0x3d,0x0d,0x68,0xc4,0x4c,0x16,0x93,0xaa,0xfe,0x08,0x4c,0x58,0xbe,0x99,0xf6, + 0x8e,0x84,0x6f,0xbd,0x93,0x5d,0xdf,0x60,0x51,0xc5,0xad,0x5e,0xfa,0x10,0xfd,0x45, + 0x69,0x22,0x5e,0xee,0xff,0x08,0x7f,0x64,0x1d,0x4d,0xa7,0x3b,0xfa,0xbf,0x69,0xee, + 0x68,0x3d,0x9e,0x34,0x4d,0x17,0xd4,0x51,0x30,0x6d,0xba,0xfe,0xe4,0x1e,0x36,0x8f, + 0xdc,0x36,0x7a,0x01,0x45,0xe2,0xaf,0x42,0xfa,0x6c,0x72,0xb1,0x39,0x80,0x5f,0x29, + 0xd2,0x80,0xa0,0x5e,0xf5,0xe5,0xa4,0x0e,0x51,0xab,0x49,0xa3,0x3f,0x1d,0x3b,0x30, + 0xc9,0x26,0xac,0x3a,0x7f,0x91,0x1e,0x20,0xab,0xff,0x84,0x6a,0x94,0x2c,0xd6,0x71, + 0x7d,0xe8,0xb1,0xb3,0x8b,0x35,0x19,0x69,0xa9,0xf6,0x78,0xc8,0x70,0x44,0x54,0xd3, + 0x9d,0x25,0xef,0x4a,0xe3,0x2f,0x3d,0x42,0x02,0xf5,0xa5,0x60,0xd9,0xfa,0x8f,0xae, + 0x80,0xe8,0x6a,0xc7,0xc2,0x88,0xa6,0xbf,0x7a,0x24,0x24,0x7a,0x82,0x02,0x56,0x4c, + 0x92,0x0b,0x11,0x9f,0x56,0xce,0x9b,0x82,0x08,0xa5,0x4f,0xef,0xe5,0xe1,0x8b,0xae, + 0xff,0xdc,0x91,0x19,0x3f,0x5d,0xe8,0xd9,0xe9,0xd0,0x02,0x52,0x6b,0xc7,0x26,0x27, + 0x71,0x9d,0xe6,0x8b,0x44,0x22,0x55,0x11,0xaf,0xc4,0xa2,0xb5,0xaa,0xbf,0xa0,0xbe, + 0xc7,0x30,0x2b,0xcb,0x2b,0x66,0x26,0x5e,0xad,0xfe,0x94,0xf0,0x8c,0xff,0x32,0x31, + 0x1a,0x75,0xda,0x9d,0x24,0xf4,0x90,0x75,0xc7,0x4a,0xd4,0x8b,0x57,0xaa,0xf6,0x3c, + 0xeb,0x3d,0x39,0x05,0x59,0x72,0xce,0x38,0x65,0x16,0xc2,0x93,0x39,0xbf,0xdd,0x5f, + 0x25,0x53,0x5a,0xc0,0x3d,0xdd,0x40,0x63,0xf3,0x11,0x4f,0xb9,0xfe,0x20,0x95,0xb0, + 0x67,0xd1,0xa0,0x42,0xa6,0x3d,0x16,0xe8,0x2a,0xcc,0xca,0x21,0x17,0xe3,0xb5,0x40, + 0xe7,0x93,0xd3,0x9e,0xd0,0xab,0x42,0xdd,0x2c,0xd0,0xf1,0x8e,0x3a,0x8b,0x12,0x27, + 0xfa,0x8b,0xaa,0xbe,0x9d,0x9e,0x99,0x74,0x3e,0xd9,0x9e,0xe4,0x7e,0x5d,0xe3,0xa9, + 0x63,0x25,0xfd,0xcd,0x46,0xc9,0x55,0x0c,0x75,0x63,0x64,0x1d,0xa3,0x89,0x1f,0xee, + 0x2e,0x66,0x2b,0x39,0xcc,0x6b,0xd1,0xd5,0xd8,0x14,0xe1,0x85,0x5e,0xf4,0x10,0xaf, + 0xd6,0x40,0x1c,0x88,0x62,0xee,0x52,0xc8,0x1c,0x97,0x27,0xd4,0x60,0xb5,0x8f,0xfa, + 0x3f,0x37,0x6b,0x0a,0xd3,0xaf,0x36,0xfe,0x76,0xf1,0x72,0xd4,0xdb,0xe8,0xc8,0xc8, + 0x48,0xc4,0x4e,0x12,0xaf,0xd2,0x29,0x7f,0xdc,0x2b,0x41,0x97,0x6e,0x33,0xf9,0x23, + 0xeb,0xe3,0xa4,0xaf,0x94,0x26,0xfa,0xcb,0xb2,0xbe,0x26,0xd9,0x74,0xdd,0x17,0x63, + 0x3d,0x48,0x4e,0x04,0x19,0x25,0x1a,0xfe,0x8a,0xfa,0x73,0xf1,0xbc,0x64,0x8e,0x5e, + 0xc2,0x26,0x8b,0xeb,0x97,0x78,0x96,0x5e,0x31,0x2b,0x36,0x13,0x33,0xe3,0xa6,0xd7, + 0x1a,0x2b,0xea,0xd5,0x6a,0x3b,0x5d,0x2a,0x1b,0xa2,0x9c,0x32,0x32,0xad,0x83,0xa3, + 0x3c,0x1a,0xeb,0xa8,0xfe,0x9a,0x32,0x2c,0x49,0x0d,0x6b,0xe2,0x6f,0xd4,0xc9,0x08, + 0x32,0x53,0x83,0x9e,0xc4,0x7e,0xd6,0xca,0x2e,0xba,0x0e,0x25,0xfc,0xf5,0xb3,0xa0, + 0x28,0x45,0x3c,0x9b,0x09,0xca,0x9f,0x66,0x84,0x74,0xe1,0x4c,0xb8,0x6f,0x76,0x3a, + 0xe6,0xea,0xa4,0xe1,0x90,0x40,0x5e,0x69,0xea,0x74,0x75,0xda,0x18,0xc9,0xd9,0x4c, + 0x26,0xe3,0x08,0x67,0x08,0x30,0x10,0x34,0xe0,0x1e,0x65,0xc0,0xe4,0xcc,0xa7,0xe2, + 0xae,0x94,0x8d,0xd5,0x51,0xf5,0x97,0xcd,0x38,0x22,0x1e,0xbf,0xad,0x33,0x1e,0xc3, + 0xb2,0x72,0xb6,0x3a,0x6e,0xcd,0x85,0xf8,0x69,0x22,0x13,0x9d,0x2e,0x6b,0xcc,0x3b, + 0xc3,0x92,0x76,0x4b,0x2c,0xee,0x1a,0x9e,0xb0,0xb0,0xc0,0x31,0x66,0x1b,0x8e,0xc7, + 0x53,0x79,0x3b,0x5f,0xff,0x19,0x46,0xad,0xf1,0x6a,0x16,0x75,0xec,0xe1,0x8c,0x83, + 0x9c,0xcf,0x99,0xc9,0x4c,0xca,0x0d,0xe1,0x94,0xab,0x33,0xdf,0xa7,0x76,0x64,0x3a, + 0x86,0x95,0x6a,0x58,0x57,0xfc,0xd8,0x3c,0xbb,0x29,0x82,0x39,0xc5,0x5e,0x6c,0x12, + 0x88,0x0b,0x57,0xd6,0xf8,0xc1,0x59,0x2e,0x0f,0x5a,0x9f,0x24,0x84,0x95,0xaa,0xa8, + 0x32,0xa9,0xac,0x5d,0x6e,0xb4,0xc2,0x66,0xf9,0x31,0x9a,0x2a,0xae,0xff,0xd6,0x3b, + 0x7d,0x45,0x23,0x57,0x15,0xfb,0x14,0xae,0x3c,0x32,0x44,0xe3,0xe1,0x90,0xce,0x60, + 0x49,0x5d,0x8f,0xa3,0x58,0xb3,0x85,0xaa,0xfe,0x7e,0x53,0x94,0xae,0x7f,0x3f,0xbb, + 0xb0,0x97,0x2e,0x1d,0xae,0x5d,0xea,0xfe,0x74,0x34,0x1a,0x5e,0x23,0xbb,0x42,0x7f, + 0xd7,0x8b,0xd2,0xf5,0x87,0x9a,0x11,0x5d,0xf3,0x7c,0x37,0x15,0x7e,0xab,0xca,0x5f, + 0xd5,0xc6,0x85,0x2b,0xeb,0x26,0xd7,0x24,0xea,0x86,0xe9,0x4f,0xaa,0xe4,0xef,0x06, + 0x0d,0xcc,0x0d,0xc5,0x6c,0xb6,0xda,0x15,0xbd,0xe4,0x4a,0x65,0xfa,0x36,0x2e,0x5b, + 0x01,0xf5,0x42,0xad,0x02,0x37,0x52,0x7f,0x39,0x6d,0xc6,0x8d,0x32,0x7c,0xa3,0x21, + 0x9b,0x82,0xd7,0xe5,0x6a,0x67,0xaa,0x63,0xb1,0x35,0xd6,0x07,0x7e,0x49,0x92,0x6e, + 0x8c,0xfe,0x24,0xa9,0x8c,0xbf,0x99,0xd8,0x9a,0xe7,0xfb,0x6d,0x83,0x6c,0xb7,0xdb, + 0x4d,0x1b,0x17,0xfb,0xd4,0xec,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08, + 0x5c,0x37,0x82,0xf6,0x90,0xcf,0xe9,0x9c,0x2a,0x7f,0xa9,0xd0,0x66,0x4c,0xad,0xca, + 0x9c,0x52,0x13,0xb8,0x4d,0xb1,0x2f,0x6d,0x4d,0x35,0x67,0xbd,0x97,0x73,0x8d,0x9c, + 0xf5,0x8a,0xac,0x55,0xbd,0x7f,0xe5,0x8c,0xef,0x8c,0x8a,0xd2,0x5e,0x65,0xce,0xea, + 0x23,0xc5,0x12,0xdb,0x3e,0xda,0xf7,0x1b,0xfd,0xa4,0x15,0x5c,0xc9,0xa5,0xdd,0x92, + 0xa2,0xd0,0x1f,0xe8,0x8b,0x2f,0x2d,0x2a,0x92,0xab,0xa1,0x68,0xb6,0x0d,0x4a,0xf3, + 0x42,0x1b,0x64,0x5c,0xc5,0x48,0x45,0x69,0x50,0x94,0xba,0x3b,0x2f,0x5c,0xa8,0xfd, + 0x0b,0xba,0xd5,0x5e,0xa8,0x25,0xfb,0x17,0x6a,0xd9,0x86,0x19,0xf8,0xbe,0xc0,0xde, + 0x9a,0xd7,0x05,0x56,0xb4,0x96,0x16,0xa8,0xfd,0xc1,0xfc,0x0f,0x1f,0x3f,0xf9,0xcb, + 0xeb,0x64,0xcf,0x17,0x73,0xaf,0xd3,0xd0,0x5b,0x09,0x75,0x8f,0xd4,0xee,0x26,0x1b, + 0xa2,0x76,0xf7,0x7c,0x71,0x4f,0xcd,0xac,0xad,0x48,0x14,0xf7,0x6a,0xe9,0x17,0x25, + 0xf2,0x9b,0xcf,0x5d,0xfb,0x4f,0x25,0x9e,0x44,0x6a,0x43,0x6d,0xdd,0x22,0xa8,0xbb, + 0x30,0xf0,0xfe,0xc0,0xc0,0xfc,0xc0,0xc0,0xd6,0x01,0xc4,0xce,0x79,0xdc,0xdd,0x49, + 0xf6,0x71,0x6f,0x60,0x7e,0x27,0x49,0xe1,0x8b,0x95,0xa0,0xaf,0xad,0xb4,0xe4,0xb9, + 0x81,0x81,0xdd,0x58,0x6e,0x9e,0xb2,0x38,0xff,0xdc,0xd2,0xb5,0xb1,0xd7,0xd0,0x23, + 0x6d,0xdc,0xb0,0x5b,0x06,0x77,0x9e,0xbb,0x82,0xa0,0x1f,0x57,0xbe,0x4e,0xdf,0x6c, + 0xbf,0x98,0x49,0x73,0xaf,0x68,0xf2,0x68,0x89,0x73,0x57,0xce,0x91,0x17,0x92,0xbe, + 0xbb,0xf6,0x87,0x27,0xaf,0xc5,0x13,0x1a,0xf4,0x37,0xbb,0xcb,0x37,0x14,0xca,0x8e, + 0x73,0x0b,0x5b,0x16,0xf6,0xec,0x79,0x61,0xcf,0x0b,0x0b,0xaf,0xd1,0x6d,0x0f,0x49, + 0x63,0x72,0x0f,0xfb,0xc4,0xed,0x2e,0x9a,0xfd,0x1a,0x49,0xd3,0x4c,0x5a,0x60,0x61, + 0xcb,0x96,0x2d,0x84,0x50,0x54,0x65,0xed,0xbd,0xf6,0x8d,0x79,0xe3,0xd8,0x65,0xde, + 0xb8,0x4d,0xb7,0x16,0x76,0x7c,0x7d,0xfb,0x75,0xe1,0xf0,0xf6,0x05,0xa4,0xf1,0xf6, + 0x2b,0x57,0x50,0x83,0xa7,0x3f,0x69,0x20,0xf1,0x76,0x49,0xbf,0x2d,0xbe,0xaf,0x08, + 0x65,0xcb,0x1d,0xd7,0x85,0x43,0x77,0x1c,0xba,0x6f,0xfb,0xc2,0x0b,0x5b,0x6e,0xc7, + 0x79,0xbc,0xf5,0xd7,0x9f,0x88,0xbe,0x6c,0x7b,0x97,0x04,0xc9,0x9b,0xdd,0xe1,0x1b, + 0x8d,0x1d,0x7b,0x0e,0x70,0xb4,0xe1,0x76,0x55,0xb4,0x95,0x76,0xda,0x5e,0x7f,0xfd, + 0x75,0x24,0x71,0xfb,0xf6,0x17,0x5e,0xc3,0x59,0xfc,0xcf,0x9f,0xe4,0x9f,0x1c,0x3b, + 0xd2,0x66,0xf7,0x6f,0x9f,0xfe,0x00,0x7e,0x71,0x87,0xf1,0x77,0x8d,0x15,0x08,0x94, + 0x27,0xbf,0x6f,0xac,0x2c,0xb2,0x78,0xc0,0x88,0x34,0xbe,0x8e,0x0c,0x1e,0x7e,0xed, + 0xf6,0x73,0x3b,0x1f,0xdf,0xd8,0x07,0x36,0x74,0x46,0xa3,0xf4,0x4e,0xbb,0x6b,0x83, + 0x3b,0x66,0x71,0xfa,0x7c,0x85,0x7c,0xfc,0xb3,0xcb,0xfc,0x23,0xc6,0xc0,0x62,0x00, + 0x29,0xc3,0xcf,0x45,0xfa,0x69,0x5c,0x34,0x92,0xdd,0x45,0x9e,0x63,0x5c,0xe4,0x7b, + 0xa5,0xcd,0x48,0x8a,0x20,0x83,0x07,0x08,0x83,0x0b,0x5b,0xae,0xbc,0xff,0x95,0x0d, + 0xa3,0xb0,0x2d,0xad,0xff,0xb2,0x59,0x2a,0x13,0x60,0x57,0x76,0x2a,0x11,0x1a,0x0b, + 0x85,0xa6,0x59,0x52,0x9a,0xce,0x76,0x8c,0x8d,0x85,0xc6,0x7c,0xa5,0x25,0x4e,0xd4, + 0xa2,0x0e,0x8c,0x1c,0x6a,0x2a,0x72,0x9f,0xda,0xb5,0x42,0xaa,0xe1,0x8b,0xa1,0x13, + 0xd2,0x59,0x67,0xc2,0x8f,0x55,0xfd,0xc5,0xbc,0x50,0x28,0x52,0xd1,0x4d,0x62,0x1d, + 0xb3,0x55,0xeb,0xf9,0x82,0x81,0x24,0xd9,0x2d,0xab,0x5d,0x05,0x67,0x82,0x55,0x25, + 0x16,0x88,0x19,0xda,0x26,0x73,0x81,0x9a,0x55,0x1b,0x98,0xee,0xa7,0x85,0xc6,0x2c, + 0x15,0x96,0xb7,0x2c,0xb6,0xcc,0x2d,0xb6,0x04,0x16,0xe7,0x8c,0x73,0x8b,0xb8,0x05, + 0x5a,0x02,0x01,0x7c,0x2f,0x06,0xe6,0x16,0x49,0xb2,0x25,0x30,0x47,0x3e,0xf9,0x41, + 0xfc,0xa4,0xc7,0x28,0xd3,0x28,0xc3,0x36,0x46,0xe0,0xb9,0x47,0x37,0xa0,0x6f,0x8c, + 0xdc,0x15,0xfc,0x65,0xb7,0xa4,0x15,0xa0,0x7b,0x17,0xbb,0x5b,0x71,0x8c,0x91,0xaa, + 0x44,0x0a,0x94,0x2d,0x93,0x7a,0x4b,0x93,0x94,0x2b,0xfb,0x57,0x9b,0xb1,0x38,0xcf, + 0x8f,0x45,0x12,0x65,0xc3,0xd5,0x03,0x97,0x76,0xf9,0x56,0xfd,0x03,0x8f,0xbf,0xa2, + 0x97,0xaa,0x75,0xbe,0x06,0x08,0x4f,0xb3,0xc5,0x7f,0x5c,0xdb,0x12,0xcd,0xc9,0x38, + 0x7f,0x34,0x3b,0xc1,0x29,0x0f,0xcd,0xd2,0xa1,0xb4,0x55,0x58,0x96,0xda,0x16,0x91, + 0xa2,0x16,0xca,0x8e,0x71,0xae,0xa5,0x05,0xc9,0x6a,0x09,0xb4,0x50,0xe2,0x8c,0xc8, + 0x26,0x39,0x64,0x2c,0x52,0x48,0x8f,0x52,0x2a,0x17,0x89,0x0e,0x8d,0x28,0xc1,0xfb, + 0x16,0x5e,0xbb,0x72,0x7a,0xe4,0xea,0xfc,0x35,0xb9,0x3a,0xad,0xae,0x74,0xbb,0x94, + 0xd4,0x10,0x28,0x15,0xce,0xd3,0x2e,0xe9,0x58,0x5e,0xb2,0xb7,0x8a,0xde,0xfd,0x37, + 0xdb,0xae,0xea,0x91,0xb3,0x34,0x1b,0x9c,0xa5,0x7b,0x26,0x7e,0xd7,0x5a,0x2a,0x62, + 0x98,0xe5,0x66,0xe9,0x03,0x70,0x39,0xc5,0x9d,0xed,0x2f,0xf6,0x5f,0xe6,0x98,0xa9, + 0xd4,0x5f,0x84,0xde,0x25,0x34,0xcb,0x6f,0xb2,0x72,0x58,0x74,0xd4,0xe8,0x30,0x6b, + 0xc9,0x14,0x17,0xba,0xcc,0x5f,0x7e,0x7a,0x57,0x5b,0x61,0x8a,0xde,0x2a,0xac,0x63, + 0xed,0x71,0xf6,0xb1,0x66,0x5c,0xaa,0xb0,0x0c,0x3b,0xe7,0x5a,0x8c,0x84,0xab,0x16, + 0x26,0xb7,0x45,0xc2,0x18,0x61,0xd0,0x48,0xb8,0x63,0x94,0x19,0x8b,0x6f,0xb6,0x51, + 0x0a,0x71,0xa6,0x07,0x08,0x81,0x87,0x50,0x81,0x27,0xaf,0x4a,0x9f,0xc1,0x35,0x9c, + 0x4a,0x59,0xf7,0x63,0x04,0xd1,0x5c,0x8b,0x4b,0x55,0xbb,0x68,0xab,0x67,0xf8,0x94, + 0xb2,0xb0,0x1e,0xca,0x69,0x7e,0x94,0x91,0x64,0xea,0x4b,0xf8,0x0c,0x63,0x0d,0xf4, + 0xd9,0x19,0x46,0x60,0x67,0x95,0xa1,0x95,0x1d,0x9a,0xd1,0x7d,0x4d,0xa7,0xd3,0xd9, + 0xa0,0x6b,0x2a,0xcb,0xfb,0x6f,0xea,0xd3,0xf9,0xd9,0xe6,0xaf,0xf0,0x98,0x96,0x48, + 0x83,0x5c,0xb2,0x0e,0x79,0xce,0x1f,0xb9,0x27,0x12,0x94,0x02,0xaf,0x2f,0xdb,0x69, + 0x65,0x9d,0x8e,0xdc,0x41,0x5a,0x1c,0xe0,0x06,0x5a,0x23,0xce,0x9e,0x2d,0x94,0x9d, + 0xab,0x5c,0xb1,0xd4,0x46,0xb9,0xe2,0x1c,0x51,0x95,0x2d,0x32,0x32,0x71,0xe3,0x74, + 0xd1,0xcf,0x40,0x0b,0xd7,0x1f,0x27,0x31,0x40,0xdd,0x60,0x1b,0x2a,0x70,0xcb,0xff, + 0x5c,0x35,0x84,0xe4,0xad,0xb1,0xe6,0x58,0xca,0x15,0xc5,0x08,0x5c,0x12,0x60,0x92, + 0x4f,0x29,0x3b,0xe7,0xcf,0x1b,0x61,0x71,0x9c,0x5d,0xa4,0x64,0x98,0xc1,0x7d,0x89, + 0x2a,0x6f,0x26,0xec,0xcd,0xfa,0x09,0x81,0x26,0x72,0x9b,0x25,0xb8,0x0a,0x3e,0xfa, + 0xe4,0x8c,0xac,0xcb,0xf6,0x5a,0x2c,0x96,0xde,0x3c,0x24,0x77,0x59,0xc6,0xf8,0x8d, + 0xcb,0x2b,0x11,0x0b,0x83,0xb3,0xe2,0x4a,0xd1,0xdb,0xcb,0xac,0x73,0x2f,0x90,0xb3, + 0xf8,0x29,0x7f,0x6c,0x48,0xaa,0x76,0xb1,0x1b,0x5f,0xed,0xfd,0xd3,0xac,0xf6,0x14, + 0xe5,0xaf,0x8a,0xd1,0x6a,0xa2,0x8c,0xd5,0x84,0xd8,0x43,0x9d,0x13,0xb0,0x0a,0x5b, + 0x02,0x8c,0x3d,0x42,0x10,0x9b,0xa8,0xb8,0x17,0x50,0x69,0x22,0x07,0x56,0xeb,0x8f, + 0x6d,0xc4,0x0d,0x22,0x81,0xdb,0x17,0x6e,0xff,0xdb,0xab,0xd0,0x67,0x4a,0xa5,0x7a, + 0x9a,0xde,0x4a,0xc5,0xd3,0x65,0x0e,0x50,0x99,0x66,0x13,0x56,0x7d,0x1a,0x10,0x5d, + 0x92,0x5c,0xec,0xa1,0xb5,0x8f,0xca,0xcf,0x94,0x38,0x3f,0x15,0xd9,0x65,0xb1,0x39, + 0x22,0x21,0xc2,0x99,0x9f,0xf8,0xc6,0x74,0x61,0x85,0x91,0xe5,0x8f,0xd4,0x84,0xc3, + 0x61,0xaf,0x03,0xa0,0x90,0xaf,0xf2,0xb3,0xf2,0x63,0x11,0x6f,0x4d,0x8d,0x37,0x5c, + 0xe3,0x75,0x56,0xfc,0xca,0x13,0xe6,0xfc,0x75,0xb2,0x64,0x93,0x85,0xd1,0x41,0x9f, + 0x18,0x83,0x08,0x6b,0x89,0xa7,0xc1,0x59,0x43,0x4c,0x86,0xc3,0xf4,0x52,0x49,0x1d, + 0xe0,0x20,0x21,0x33,0x69,0xe0,0x45,0xd6,0xb8,0x88,0x7a,0xc4,0x48,0xb9,0x33,0x6a, + 0x94,0x85,0x19,0x8c,0xc1,0x16,0x23,0xe1,0x72,0x4e,0xa5,0x93,0xd2,0xd6,0xc2,0x4a, + 0x2d,0x92,0x32,0x18,0x9c,0x0f,0xb4,0x1d,0xda,0xbe,0xe5,0x5b,0x57,0xe1,0xcf,0xd0, + 0xd9,0x3c,0x6a,0xcb,0xf5,0x58,0xd3,0x18,0x81,0x93,0x45,0xf9,0x2b,0x7c,0xc2,0xce, + 0xf2,0x16,0x65,0x78,0x0f,0x53,0xe4,0x98,0x93,0x3e,0x43,0x2b,0xf7,0xf9,0x7a,0x70, + 0xd1,0x9d,0xaa,0x0a,0x3b,0x0a,0xf4,0x20,0xb9,0x53,0x3b,0xca,0xbd,0xbd,0x2e,0xc6, + 0x80,0x7a,0xcd,0x84,0x1d,0xbb,0xc8,0x7c,0x6c,0xa8,0x4e,0x11,0x5c,0x26,0xef,0x8a, + 0x69,0x86,0xd6,0x65,0xd5,0x3a,0xa2,0x7a,0x7a,0x8c,0x26,0xf3,0x34,0xa5,0xba,0x8e, + 0x1c,0x37,0x19,0xa3,0xbf,0x12,0x29,0xdc,0x23,0x93,0xc7,0x27,0x21,0x15,0x62,0x4f, + 0x0a,0x57,0xad,0xa6,0x0f,0x94,0xb6,0x80,0x51,0x9d,0xaa,0x34,0x82,0x90,0x8f,0x40, + 0x31,0x8a,0x68,0xf4,0x47,0x75,0xc9,0xb2,0xb0,0xc8,0x22,0x0d,0x2f,0x24,0x88,0xdc, + 0x77,0x78,0xe1,0x2a,0x13,0x38,0x9c,0x6a,0x7a,0x26,0xf3,0xcc,0x44,0xbd,0xde,0x5c, + 0x36,0x81,0x2d,0x11,0x1a,0x03,0x55,0x97,0xf4,0x4c,0x96,0xf1,0x47,0x5c,0xd2,0x70, + 0x82,0x7a,0xee,0x59,0x1f,0xe3,0x56,0xca,0x84,0x6b,0x0c,0xa4,0xfd,0x33,0xee,0x52, + 0x58,0x0c,0x95,0x3a,0x20,0x4d,0x66,0x1c,0xe7,0x09,0xe3,0xd9,0x75,0x57,0x98,0x36, + 0x6e,0x9d,0x07,0xa1,0xbb,0xb3,0x6c,0xfe,0x86,0xcb,0x5a,0x52,0xf1,0xfb,0x46,0x6f, + 0x84,0x69,0x8e,0x34,0x62,0x9a,0x95,0x9f,0x3d,0xb2,0x96,0xf1,0x3d,0x45,0xfd,0x51, + 0x95,0xb5,0xd0,0x65,0x8c,0xaa,0xbf,0xa2,0x22,0x55,0xfd,0x19,0x79,0x1e,0x9d,0xe3, + 0x64,0x2d,0x73,0x60,0x19,0x67,0xf0,0xe7,0xd7,0xe7,0xef,0xad,0x98,0xad,0x66,0x32, + 0x9c,0xbb,0x3b,0x8e,0x2b,0x18,0xcd,0x0c,0x0e,0x47,0x98,0x24,0xf8,0x6d,0xcb,0x79, + 0xf6,0x2c,0x38,0x7d,0xfc,0xcf,0x6b,0xa0,0x2e,0xce,0xae,0xae,0x59,0x92,0x11,0x47, + 0xd5,0x0c,0xef,0x7e,0x17,0x8f,0x96,0x3a,0x4d,0x07,0xdc,0xd3,0x8e,0xb0,0x93,0x04, + 0x88,0xca,0xc5,0x59,0x89,0x3f,0xfe,0x70,0xfb,0x28,0x4b,0xa6,0x74,0x6c,0xbc,0x59, + 0x79,0xd5,0x75,0x58,0xcb,0xeb,0xa8,0x1e,0x99,0x3c,0xb4,0xc3,0x9f,0x4c,0xd7,0xad, + 0xf9,0x03,0xdc,0x4e,0xad,0x77,0x6b,0x99,0x53,0x43,0x09,0xe5,0x4c,0x13,0x7b,0x35, + 0x25,0xd4,0xa0,0xdc,0x42,0xa3,0x08,0xce,0xe0,0x85,0x3f,0x5a,0x97,0x3e,0x39,0x56, + 0xed,0xb0,0x44,0x2c,0xcf,0x54,0x5b,0xd3,0x18,0x41,0xa4,0xe2,0xef,0xe1,0x99,0x72, + 0x97,0x94,0xe3,0xeb,0x95,0x27,0x50,0x4f,0xd9,0x0e,0x9a,0x28,0x2d,0x82,0xf5,0x85, + 0x49,0x2a,0x80,0x42,0xc9,0xad,0xdb,0xb5,0x33,0xd4,0x5c,0xf5,0x8c,0x77,0xc5,0x2e, + 0xb3,0xa7,0x6a,0xd6,0x42,0x13,0xb7,0xce,0x1f,0xb2,0xb6,0xf2,0x24,0x9b,0x8e,0x61, + 0x4b,0xc9,0x75,0x68,0x50,0x33,0x5d,0x8c,0x39,0x13,0x7c,0x81,0xb4,0xf6,0xf8,0x5c, + 0xd0,0x04,0x57,0x1e,0x39,0x5a,0x68,0x28,0x61,0x81,0x39,0xc0,0xdf,0xc6,0x62,0x58, + 0x69,0x09,0x18,0x35,0x14,0x06,0x02,0x6d,0x7f,0xb9,0xfd,0xc9,0x75,0xf9,0x33,0xa5, + 0x9a,0x6a,0x0a,0xe7,0x23,0xe1,0x89,0x94,0x8b,0x0a,0x50,0x55,0x60,0xbe,0x97,0xcd, + 0x89,0x19,0x1d,0x85,0xea,0x00,0x32,0xe4,0xa1,0x89,0x31,0x1a,0x0e,0x2e,0x17,0x5b, + 0xa8,0x58,0xbc,0x09,0x92,0x85,0x8b,0x45,0x29,0xc2,0xd6,0x3d,0xa6,0xb2,0xb9,0x9a, + 0x2e,0xd8,0xbc,0x06,0xfb,0x1a,0xf1,0xb1,0x33,0x6b,0xf0,0x6b,0xac,0xdb,0xd9,0xc9, + 0xf8,0x2d,0xe3,0xfc,0xc9,0x3a,0x07,0x8f,0xc6,0x0d,0x3a,0x15,0x74,0x4c,0x1d,0x7c, + 0x82,0x78,0x73,0xa3,0x09,0x5e,0xbe,0x42,0xa1,0x1c,0x77,0x2e,0xf2,0x90,0x1b,0x60, + 0x34,0x1a,0xf9,0x64,0xe5,0xe1,0x57,0x15,0x5c,0xf1,0x7b,0xae,0x18,0x80,0x89,0x33, + 0x9c,0x23,0x21,0xe4,0xc7,0xdf,0x5b,0x97,0xbf,0x99,0x54,0xce,0x72,0xfe,0xcc,0x79, + 0x4b,0xee,0x6e,0x8c,0x20,0xee,0x2e,0x45,0x0d,0x21,0x36,0xde,0xea,0x0a,0xd4,0x60, + 0x9f,0x0b,0xd4,0xbb,0xcb,0x9a,0x18,0x3a,0xd1,0x4b,0x25,0x69,0x72,0x93,0x0b,0x15, + 0xe6,0xd6,0xcb,0xa7,0x92,0xb5,0xca,0x36,0x49,0x7c,0xa4,0xa9,0x42,0x44,0xc3,0xa5, + 0xe5,0xf6,0x1a,0xf0,0xad,0xd3,0x12,0xba,0x2e,0xcc,0x5b,0xfc,0x15,0xc5,0xe5,0xe9, + 0x35,0x7f,0xc3,0xac,0x0b,0xb4,0xa8,0xdc,0xb4,0x14,0x99,0x2a,0xb1,0x56,0xcc,0x53, + 0xbf,0xf0,0x13,0x6b,0xb0,0x17,0xa5,0x33,0xb0,0x7c,0xe8,0xe8,0xba,0xd7,0xc0,0xfe, + 0xd4,0x13,0xd3,0xfd,0x06,0x5f,0xc4,0x31,0x31,0xec,0xba,0xd4,0x4e,0x66,0x30,0x53, + 0x4e,0xd3,0x74,0x48,0xf3,0x07,0x2c,0x8a,0x7f,0xa3,0x02,0x2f,0x37,0x8f,0x44,0x7e, + 0x4d,0xd7,0x7b,0x1a,0x85,0x75,0x66,0xa9,0x24,0x65,0xbc,0x7e,0xb0,0xf0,0xb0,0x58, + 0xd1,0x95,0x58,0x24,0xdf,0x9b,0x30,0x69,0x9c,0x26,0x43,0x3c,0xb2,0x62,0x22,0xe6, + 0x4b,0xcd,0xd3,0x9e,0xcc,0x40,0xcb,0x8c,0x5a,0xd4,0x96,0xd0,0xbf,0xea,0x81,0x1f, + 0xe4,0xd9,0x2c,0xc8,0x45,0x8a,0xd9,0xac,0x92,0x87,0xfc,0x10,0xb2,0x06,0x7f,0x3b, + 0xbe,0xaf,0xa5,0x2e,0xc0,0xc3,0xeb,0x9c,0x3a,0xa1,0x99,0x36,0xcb,0x3c,0xa0,0xb1, + 0x85,0xd1,0xca,0x60,0x0c,0x2c,0xbf,0xb4,0x37,0xe8,0x59,0x07,0x7d,0x29,0x5b,0xc4, + 0x37,0x96,0x40,0x01,0xc6,0xd0,0x03,0x9a,0xdd,0xea,0x22,0xa6,0x27,0x32,0xc6,0xff, + 0xd6,0x85,0x0e,0xaf,0x17,0xc8,0x1f,0x27,0xa1,0x49,0x74,0x71,0xa9,0x69,0xdf,0xff, + 0xb7,0x73,0xfe,0x31,0x6d,0x5c,0x77,0x00,0x2f,0x23,0x2c,0xcd,0x0d,0x29,0x6c,0x66, + 0x4d,0xd5,0x45,0xaa,0xa9,0x5b,0x9b,0x90,0x46,0x4a,0x9b,0x55,0x48,0x07,0x9c,0xab, + 0x35,0x5b,0x07,0x0d,0x14,0x95,0x0e,0xea,0x0a,0xe1,0x4c,0xb3,0xbc,0x5a,0x49,0x6b, + 0x05,0x7b,0x5a,0xb4,0x2d,0xd5,0xa4,0xfc,0x31,0x6d,0x19,0x71,0xb4,0x69,0x6b,0x94, + 0x36,0x26,0xaa,0x32,0xc9,0x57,0x8d,0x06,0x31,0x1b,0xbb,0x06,0x2a,0x36,0xa0,0x56, + 0x7a,0xaa,0x2a,0x57,0x1b,0x12,0x95,0xe9,0xb6,0x2e,0x51,0x40,0x5a,0x16,0xab,0x62, + 0x33,0xd1,0xc0,0xdb,0xf7,0xfb,0x7e,0x9c,0xcf,0x10,0x08,0x99,0xba,0xfe,0xf5,0xfd, + 0xbc,0x77,0xef,0xee,0x7d,0xdf,0xf7,0x7d,0xef,0xf9,0xeb,0xf7,0xee,0xde,0x3b,0xff, + 0x60,0xfe,0xb3,0xf4,0xb0,0x6a,0x8d,0xf5,0x05,0xbc,0x59,0x8b,0xd9,0x46,0xdf,0xda, + 0x85,0x94,0xcb,0x09,0xd3,0xc4,0x94,0xf8,0x71,0xb5,0xc9,0x4b,0x95,0x6e,0x1d,0x6c, + 0x07,0x92,0x72,0x89,0x92,0x0c,0xb0,0x93,0xa9,0xec,0x64,0x6c,0xa1,0x76,0xd7,0x25, + 0x27,0xbf,0x5e,0xf4,0xa9,0x58,0x08,0xad,0x51,0x62,0xfc,0x0d,0xd6,0xe5,0x3f,0x9b, + 0xa0,0x38,0xc9,0xaa,0xa8,0xb7,0xf8,0x10,0xa2,0x56,0xdc,0x26,0xe4,0x3c,0x1a,0x73, + 0x3c,0xc3,0xaf,0x6f,0xd3,0x72,0xd0,0x4e,0x97,0x7c,0x86,0xd2,0x69,0x51,0x30,0x7d, + 0xe4,0xed,0xbf,0xff,0xee,0xe6,0x46,0xfe,0x53,0x1f,0x6e,0xa8,0x2c,0x2c,0x06,0xfd, + 0x95,0xcd,0xdd,0x30,0x87,0x1e,0xf4,0xf0,0x6b,0x60,0x7a,0x65,0x28,0xc2,0x2e,0x69, + 0x7d,0xa9,0x40,0x11,0xe7,0xfc,0xa3,0x95,0xfc,0x45,0x68,0x30,0xe6,0x7a,0xf9,0xca, + 0xc9,0xd2,0xd4,0x0e,0x3e,0x7f,0xc5,0xc9,0xa2,0xbc,0x2d,0xf6,0xac,0x7d,0x19,0x0d, + 0xbe,0xe6,0x22,0xce,0xa3,0x75,0xeb,0xdc,0x79,0x30,0x12,0x62,0x4b,0x8a,0x88,0x70, + 0x91,0x62,0xc0,0x1a,0x63,0xd4,0x59,0x69,0xe3,0x93,0x48,0xfe,0x9f,0x15,0xe2,0x91, + 0x44,0x06,0x5a,0xc2,0x56,0x20,0x11,0xf6,0x90,0x60,0x9b,0x78,0x83,0x53,0x41,0x26, + 0x8e,0xf8,0x59,0xa3,0x6c,0xeb,0x9f,0xa5,0xed,0x39,0xb2,0x7f,0xba,0xe4,0x18,0xcb, + 0xe8,0x45,0x2f,0x09,0xef,0x1d,0xd9,0x2f,0x9d,0xc6,0xae,0x79,0xa5,0x0a,0x15,0xd3, + 0xd3,0x9d,0x9d,0x47,0x9e,0x7b,0x63,0x23,0xf7,0xf5,0xa5,0xba,0x1b,0x22,0x05,0x45, + 0xd1,0xef,0x77,0x36,0x0c,0x5d,0xe8,0x81,0x4b,0x20,0x38,0xd0,0xbb,0xb2,0x92,0x9e, + 0x2c,0xda,0x78,0xab,0x83,0x11,0x1f,0x83,0xaf,0x2b,0xe0,0x92,0x54,0x1d,0xe1,0x13, + 0xb2,0x1b,0xa5,0x26,0xc6,0xf8,0x02,0x03,0x7f,0x84,0x2a,0xe7,0x3d,0xeb,0x46,0x92, + 0xd7,0x17,0xba,0x9c,0xc5,0x99,0x88,0xe5,0x19,0xd8,0x5d,0x75,0xc6,0x0e,0xab,0xf5, + 0x8c,0xe2,0xe6,0x59,0xb1,0xb6,0x65,0x9a,0xf2,0x91,0x44,0x4a,0xb6,0x04,0x17,0x35, + 0xcc,0xad,0x5c,0x0c,0xab,0x1a,0xdf,0x8e,0xd0,0x92,0x18,0xe5,0x17,0xd6,0xf9,0xef, + 0xc5,0xe9,0x4d,0xd8,0x5f,0xb1,0x7f,0xbd,0x4c,0x38,0xae,0xa2,0x02,0x52,0x4c,0x3a, + 0xaf,0x6c,0x32,0x7f,0x71,0xdd,0xa8,0xb4,0x2d,0x27,0x95,0x44,0x71,0xc7,0x8d,0xa1, + 0x8e,0x1e,0x1c,0xc2,0x5d,0xe0,0x41,0xb8,0x4b,0xf0,0x56,0x87,0xd9,0xa2,0x61,0xb2, + 0x3b,0xcb,0x9f,0xa2,0xe8,0xb8,0x72,0xf7,0xe1,0x95,0xac,0x2f,0x68,0xfa,0x61,0x25, + 0xce,0x06,0x4f,0xc6,0x96,0x66,0xb7,0x45,0x66,0x77,0x68,0xdd,0xeb,0xf0,0xf6,0x86, + 0x7c,0x1a,0xf6,0xd3,0xa2,0xac,0x08,0x93,0xa5,0x0b,0xcc,0xfa,0xb6,0x38,0x9f,0x75, + 0x27,0x87,0xf8,0xd9,0x0c,0xb1,0xb6,0x65,0x5d,0xb5,0xde,0xcd,0x5b,0xe2,0x9f,0x94, + 0xb0,0x4b,0xc0,0x64,0x65,0x81,0x8f,0x08,0x26,0x72,0xb9,0x7b,0xb9,0xff,0x46,0xd7, + 0x9e,0x76,0xe5,0x6b,0x7f,0x01,0x77,0xbc,0x72,0xe4,0x8b,0x47,0x3a,0x65,0x97,0xea, + 0x14,0xfe,0x61,0x61,0x83,0x23,0xb9,0x03,0x0e,0x9f,0x3a,0xf5,0xc0,0x86,0xfe,0xeb, + 0x6b,0x8e,0xf5,0xda,0x94,0x5c,0x32,0xe8,0x8f,0x5c,0x76,0x4d,0x82,0x03,0xf7,0x41, + 0x17,0x04,0x0f,0x0e,0x67,0xd9,0x55,0x0e,0xe6,0x10,0x6c,0x44,0xc8,0x75,0x85,0x02, + 0xb7,0x17,0x5f,0xc8,0x60,0xc3,0x35,0x06,0xc7,0x2c,0x76,0xf0,0x6b,0x63,0x2a,0x04, + 0xba,0x4b,0x11,0xb9,0xf6,0x4f,0x63,0x19,0x06,0x54,0xc1,0xbb,0x92,0xc7,0x88,0x64, + 0x15,0x34,0xea,0x83,0xec,0x0a,0x93,0xa5,0xb9,0x75,0x8f,0xa1,0xf1,0x87,0x51,0xdc, + 0xb3,0x69,0x39,0x09,0xaa,0x43,0x23,0xd5,0x59,0xfe,0x48,0x42,0xe3,0x73,0xd3,0x15, + 0xfc,0x9c,0x06,0xae,0xd1,0xf2,0x0d,0x76,0xa3,0x30,0x7d,0xd7,0xa4,0xce,0x2f,0xa1, + 0x7e,0x2c,0xe3,0x01,0xcf,0x01,0xbb,0x77,0xc0,0x05,0x4f,0xfe,0xa8,0xd6,0x5b,0xfb, + 0xa5,0xf3,0xe8,0x0d,0xe6,0x92,0x8a,0x0a,0xd1,0xbb,0xa6,0x6f,0x71,0xc4,0x54,0xa6, + 0x57,0x2b,0x2a,0x56,0x51,0x71,0x61,0x61,0xe1,0xb1,0xc7,0x36,0x59,0x7f,0x64,0x2f, + 0xf9,0xfc,0x8a,0xaa,0x2e,0xeb,0x5a,0xef,0x92,0xeb,0x89,0xfa,0xe1,0x29,0xe8,0x82, + 0x57,0x3d,0x9e,0x9e,0x2c,0xbf,0x06,0x69,0xde,0x34,0x06,0x8f,0x11,0x16,0x43,0x2a, + 0xed,0x9d,0x8c,0xc0,0x5c,0x24,0x83,0x93,0x91,0x34,0xfe,0x1f,0x52,0x7a,0x90,0xff, + 0xe2,0x2f,0xa3,0xd6,0x43,0x21,0xdc,0x16,0x59,0x2e,0x06,0x37,0xf2,0x34,0xaf,0x0b, + 0x2a,0x69,0x4c,0xbc,0x53,0x87,0xf8,0x8d,0x21,0xb3,0x04,0x6e,0x49,0xb3,0x72,0xae, + 0xd2,0xe5,0x16,0xd6,0xbb,0x78,0x5e,0x4e,0x82,0xa6,0x40,0x27,0x3d,0xa5,0xf1,0x77, + 0xd2,0xef,0xe5,0xfa,0x60,0x0a,0xab,0x0e,0xbb,0xf9,0x32,0x48,0x43,0x99,0xf9,0x1e, + 0xf6,0x1d,0x82,0x42,0x50,0xe4,0x67,0x66,0xf1,0x7c,0xc5,0xf4,0xb1,0x6b,0x9f,0xfb, + 0xee,0xdb,0xdf,0x3f,0xd6,0xf8,0x68,0x45,0x39,0xab,0xb7,0x38,0x2e,0x97,0xad,0x2e, + 0xb4,0xb6,0x46,0x5f,0x7f,0xed,0xcc,0xc6,0xfe,0x73,0x74,0x87,0xee,0x0f,0xa8,0xe0, + 0xc0,0x44,0xdc,0xb9,0xe4,0x1a,0xea,0x18,0xae,0x9e,0xda,0x07,0x83,0xb8,0x47,0xe3, + 0x8f,0x8d,0x13,0x5e,0xc6,0x55,0xb1,0x2e,0xb3,0x43,0xd7,0xf4,0x14,0x43,0x95,0x8b, + 0xec,0x16,0xdc,0x5c,0xe7,0xf5,0x76,0x4d,0x8a,0x79,0x98,0xaa,0xe1,0xc0,0x8f,0x15, + 0xf9,0x38,0x6a,0xf6,0x76,0xf1,0x9a,0xde,0xae,0x29,0x93,0x6d,0xf2,0x1f,0xc6,0x2e, + 0x79,0xcb,0xf0,0xb8,0xb9,0x75,0x15,0xec,0x5d,0x83,0xd8,0xcb,0xfd,0xd7,0x57,0x8d, + 0x36,0x06,0x45,0x4b,0x82,0xd5,0x60,0xe1,0xa5,0xa9,0x29,0xd8,0x61,0x1d,0xf9,0x06, + 0x1f,0x42,0x41,0x75,0x87,0xf8,0x65,0x59,0x46,0xf3,0xf2,0xbf,0x3e,0x32,0x79,0xab, + 0x73,0xe1,0x9d,0xda,0xf3,0x4f,0x5e,0x59,0x7d,0xe5,0xe5,0x97,0x1b,0x3f,0xbf,0xba, + 0xba,0x5a,0xc1,0x7a,0x16,0xee,0xf9,0xb6,0xb0,0x6a,0x61,0xa1,0x62,0x81,0xc9,0x17, + 0x40,0xbc,0x80,0xb4,0x46,0x67,0x27,0x0e,0x7c,0x65,0x63,0xf7,0xc1,0xa2,0xa9,0xc1, + 0x48,0xe4,0xec,0x76,0x55,0x29,0xc4,0x9d,0xcd,0xb1,0xa1,0xdd,0xf5,0x3d,0xd0,0xa0, + 0x7f,0xf6,0xc4,0x79,0xab,0x03,0x1e,0x06,0x8c,0x5f,0xfe,0xb8,0x08,0x46,0xb7,0x67, + 0x5b,0xd1,0x17,0x67,0x03,0xb1,0x4f,0xf5,0x1b,0x72,0x72,0xab,0x2a,0x93,0x50,0xd4, + 0xe5,0x12,0xfe,0xf3,0x79,0x24,0x3d,0x36,0xdd,0x7e,0x34,0x95,0x4a,0xe1,0x26,0xe7, + 0x79,0x01,0x4f,0x19,0x57,0xc5,0xc3,0xd0,0xa3,0x53,0x2c,0xdb,0x35,0x5a,0xe4,0xff, + 0x92,0x76,0x01,0x73,0x83,0x61,0xf1,0x01,0x40,0x26,0x95,0xc1,0x98,0xc9,0xd8,0x50, + 0x0c,0xc3,0xba,0x24,0x36,0x27,0x90,0xea,0x65,0xcf,0x1a,0x7e,0xb3,0xd0,0x79,0xed, + 0xc9,0x57,0xbc,0xe7,0x17,0x8e,0xed,0x39,0xfc,0xe8,0x8b,0x87,0x17,0xee,0x04,0xe8, + 0x7b,0xd1,0x9d,0x13,0xcf,0x3c,0xf3,0xe0,0x66,0xfe,0x33,0x5c,0x4e,0xff,0xb2,0x6a, + 0xb7,0xe7,0x94,0x82,0xd6,0x7b,0xf9,0x27,0xdd,0x43,0x17,0xea,0xa1,0x0f,0x0e,0x8b, + 0x77,0x3d,0x59,0x77,0xb0,0x0e,0xa3,0xe8,0x7f,0x99,0xea,0x83,0x90,0xc3,0x87,0x98, + 0x4a,0xd9,0xa7,0x12,0x29,0x55,0x77,0xc2,0xb8,0xaf,0xab,0xfb,0xd8,0xe0,0xd3,0x8a, + 0x48,0xdd,0x41,0x11,0x86,0x35,0xdb,0xba,0x0f,0x40,0x1c,0x75,0x75,0xac,0x4c,0x24, + 0x83,0xd2,0xfa,0xf0,0x55,0x26,0x19,0x29,0xf2,0x49,0xe4,0x36,0xcc,0x0c,0x86,0xf3, + 0x6b,0xea,0x2b,0x83,0x50,0x47,0x0e,0x90,0xb2,0x56,0xe4,0x94,0xfa,0x3a,0x8e,0x3c, + 0xfb,0xe0,0x73,0xad,0xef,0xed,0x69,0x3d,0xd5,0x78,0xfe,0x4a,0xe3,0x7b,0xad,0x87, + 0x1b,0xaf,0xb4,0x72,0x06,0x2c,0x29,0xee,0xc4,0x51,0x39,0x03,0xd1,0xd9,0x9d,0x13, + 0x1f,0x8c,0x7f,0xf4,0x78,0xfb,0x66,0xfe,0xb3,0x5f,0x6a,0x36,0x82,0xd0,0x01,0xa1, + 0x07,0x26,0xc2,0x11,0xdf,0x92,0x6b,0xdb,0xe4,0xee,0xfa,0xfa,0xfa,0x70,0x58,0xc5, + 0x37,0xd6,0x21,0x86,0x9e,0x11,0x4f,0xb2,0xf7,0xb9,0x03,0x33,0x3d,0x06,0x38,0x50, + 0x57,0xcd,0xee,0x94,0xb1,0x27,0x0b,0x5a,0x35,0xd3,0xeb,0xce,0x26,0xec,0xa0,0x96, + 0x32,0xcc,0x41,0x3b,0x9c,0xf7,0xab,0x99,0x12,0xcc,0x8a,0xa3,0x7a,0xaa,0x8c,0x62, + 0x96,0x5b,0xff,0x17,0xcf,0x8e,0x18,0x0a,0xcb,0xc6,0x58,0x2e,0xcf,0x5b,0x52,0x22, + 0xd9,0x83,0x6d,0xd0,0x84,0xd9,0x94,0x48,0x52,0x29,0x55,0xd1,0x9d,0x53,0x6b,0xf8, + 0xf9,0x40,0xf4,0x9d,0xef,0x44,0x4f,0x79,0xef,0xde,0x93,0x3e,0x76,0x38,0x5a,0xfb, + 0xa7,0x81,0x81,0xe8,0x40,0x14,0x18,0x60,0x1b,0x0b,0x48,0x94,0x6d,0x66,0xca,0x75, + 0xc0,0x7b,0xc7,0xc7,0x7f,0x3d,0x33,0xf3,0xc9,0x66,0xee,0xeb,0xeb,0x8b,0xdf,0x38, + 0x0d,0x77,0x10,0x7b,0xca,0x9e,0x5b,0x0e,0xfa,0xb3,0xce,0x50,0x43,0xac,0x1b,0xe6, + 0x11,0x79,0x4d,0x5f,0xc4,0x95,0x41,0xfd,0x70,0x0f,0x86,0xa2,0x51,0xc0,0x95,0x41, + 0x72,0x88,0x65,0x77,0x1b,0x95,0xa3,0x86,0x3f,0x00,0x95,0xb0,0xed,0x6a,0x52,0xf7, + 0xe7,0x77,0xb3,0x82,0xe1,0x6e,0x2d,0xaf,0xe3,0xe7,0x14,0x1a,0xcb,0x61,0xbc,0x10, + 0xd6,0xf4,0x00,0x47,0x11,0x5b,0x40,0xe9,0x60,0x85,0x32,0x19,0xae,0x74,0x27,0x98, + 0xf5,0x6e,0x2e,0xf2,0x15,0x6d,0x4c,0xab,0x99,0x15,0x6b,0xf1,0xc4,0x62,0xc0,0x82, + 0x12,0xe8,0x00,0x69,0x7d,0x38,0xab,0x2b,0x8b,0x01,0xfe,0x89,0xca,0x22,0x46,0xdd, + 0xe6,0x8f,0x77,0xf0,0xd6,0x4a,0xcb,0x3d,0xc3,0xf7,0x46,0x67,0xef,0xf9,0x73,0xf4, + 0xb1,0xc6,0x7b,0x7e,0xf0,0x8f,0xda,0x6f,0xce,0xd6,0x3e,0x35,0x3b,0x1b,0xdd,0x39, + 0x1b,0xc5,0x84,0xa5,0x6c,0xdb,0x69,0xee,0x67,0x4b,0xdb,0xce,0x89,0x89,0x13,0x1f, + 0x8c,0x3f,0x32,0xb3,0xeb,0xc3,0x4f,0x36,0xed,0x7e,0xd0,0xeb,0x1b,0x9a,0x0d,0x3d, + 0x69,0x07,0x07,0xaa,0xc9,0xc5,0x42,0xd8,0xed,0xdc,0xb1,0xd4,0xe0,0xfa,0x38,0x9f, + 0x65,0x5f,0x96,0xd5,0xe5,0x94,0xac,0x98,0xcd,0x42,0xd6,0xd6,0xc0,0xb3,0x0f,0xbb, + 0xfd,0x91,0xac,0xe6,0xd7,0x71,0x3d,0x15,0x2c,0xf8,0x6d,0x59,0xa1,0x36,0x19,0x0b, + 0x1b,0xf1,0xac,0x06,0x75,0xcd,0xd9,0xda,0x90,0xdf,0x9d,0x15,0xdf,0xe0,0xcd,0x62, + 0xc4,0xcc,0xa1,0xee,0xc9,0x32,0xdc,0xe5,0xd6,0x9d,0x06,0xcb,0xe6,0x7d,0x2c,0x97, + 0x2f,0xf2,0x4a,0x26,0x36,0x7c,0x92,0xfd,0x84,0x10,0x67,0x35,0xb1,0x8b,0x67,0x4b, + 0xad,0x30,0xf9,0xe3,0xc4,0x89,0x13,0xf7,0x36,0x1e,0x78,0xe8,0xda,0x53,0x07,0x1e, + 0x7a,0xeb,0x9e,0x37,0xae,0xbd,0x36,0x31,0x71,0x1c,0xe2,0x89,0x13,0x13,0x98,0x4e, + 0x40,0x80,0x23,0xcc,0xc0,0xfe,0x38,0x66,0x27,0x58,0x72,0xe2,0x38,0x30,0xfe,0xc3, + 0x47,0x66,0x3e,0xbc,0x7e,0xfd,0x57,0xcf,0x6e,0xee,0x3e,0x58,0xf4,0xb8,0x7c,0xda, + 0x7d,0x0e,0x7b,0x2a,0x05,0x17,0xc1,0x64,0xb0,0xa0,0x19,0x11,0x58,0x2b,0xe8,0x40, + 0x42,0x4f,0x28,0x0d,0x31,0x57,0xcc,0xe5,0x72,0x69,0x98,0x49,0xe8,0x01,0x9f,0x0b, + 0xf3,0xb1,0x58,0xcc,0x59,0x38,0xa4,0x85,0xc3,0x79,0xbf,0x3f,0x9f,0x4f,0xe8,0x4e, + 0xa6,0x84,0xf1,0xd5,0xc5,0x84,0xce,0x02,0xd4,0xe1,0xb2,0x1b,0xac,0x66,0x81,0xc5, + 0x04,0x33,0x92,0x00,0xab,0x52,0x9f,0x19,0x77,0x69,0x4c,0x45,0x0f,0x8e,0xb0,0x6c, + 0x6c,0x14,0xaa,0x80,0xb6,0xee,0x66,0xc5,0x36,0x66,0xa0,0x84,0x1e,0x78,0x15,0xeb, + 0x09,0x53,0x52,0xa8,0x27,0xfc,0x3e,0xb3,0x15,0xfc,0xdc,0xc0,0x33,0xe3,0xe3,0xdb, + 0xb7,0xdf,0xfd,0xd7,0x03,0xb5,0x07,0xf7,0xd4,0x3e,0xfd,0xfc,0x8f,0x7f,0x3f,0xfe, + 0x9f,0xf1,0xed,0x2c,0xa0,0x7c,0x9c,0xb3,0x7d,0x9c,0xe7,0x2d,0x61,0x1c,0x7d,0x07, + 0xce,0x6b,0xaa,0xaa,0xea,0x7f,0xf3,0xec,0xed,0xfc,0xd7,0x17,0x69,0x70,0xe6,0x83, + 0x49,0xfb,0x4d,0xb8,0x43,0xaa,0x0e,0x65,0xb1,0x90,0x0f,0x67,0x23,0x95,0x91,0xd1, + 0xd3,0xbd,0x4e,0xe7,0x88,0x58,0x33,0xf9,0xd8,0x3a,0x75,0xc4,0x29,0x72,0xb8,0xec, + 0x32,0x0a,0x4a,0x00,0x07,0x8e,0xee,0xf6,0xed,0xf0,0xf9,0xca,0xf4,0x2c,0xf5,0x4c, + 0x09,0x70,0x1a,0x2d,0x58,0xcd,0xf8,0x42,0xa6,0x0e,0x2b,0x30,0xab,0x8c,0x58,0xb4, + 0x30,0x33,0xc2,0x2a,0x4b,0x03,0x25,0x1d,0x96,0x9c,0x2e,0x09,0xd7,0xf0,0xc0,0x49, + 0xe4,0xf9,0xda,0x6f,0x7c,0x34,0x33,0x33,0xf3,0xf8,0xb7,0x0e,0x3e,0x3e,0x73,0x52, + 0x30,0x73,0x72,0x17,0x26,0x10,0x67,0xc4,0x9e,0xb1,0x0b,0xf7,0xbb,0x4e,0xee,0xda, + 0xf5,0xe1,0x9b,0xe0,0xbc,0xb1,0xb6,0xb1,0xb1,0x73,0xb7,0x19,0xbd,0x48,0xc6,0xb7, + 0x14,0xf1,0x2f,0x3a,0x60,0x08,0x43,0x1f,0x54,0x61,0x14,0x07,0x0b,0x05,0x7f,0x3e, + 0xac,0x69,0xf1,0xfb,0xb5,0x78,0x3c,0x1b,0x8f,0xe3,0x18,0x89,0x23,0xb0,0x63,0x41, + 0x63,0x49,0x56,0x03,0x25,0x5e,0xc8,0x02,0x26,0x71,0xbe,0x69,0x59,0x8c,0x9c,0x38, + 0xaf,0xcb,0x6a,0x6b,0x62,0xcf,0x07,0x39,0xd3,0x81,0x2d,0xce,0xe5,0x68,0xa2,0x94, + 0xc3,0x53,0xb3,0xb3,0xf0,0x63,0x8d,0xcb,0x85,0xd4,0x34,0x19,0xe7,0xdf,0xf3,0x67, + 0x8a,0xbc,0x09,0xdc,0x24,0x6e,0x5f,0x68,0x42,0xaa,0x9a,0x7e,0xba,0xef,0xe9,0xdf, + 0x7e,0xf9,0x67,0xfb,0xfe,0xf6,0x00,0x1c,0x5b,0xc0,0x4c,0x3f,0xa4,0x18,0x44,0x14, + 0x0a,0x55,0x55,0x63,0x63,0x6d,0x2d,0x40,0x5b,0xff,0xfc,0xed,0xdd,0x87,0x33,0xe1, + 0xa5,0x08,0xf4,0xc0,0x17,0xe0,0x7e,0x80,0xa3,0x18,0x5c,0xb8,0xac,0x2c,0x2e,0xe2, + 0x97,0x4e,0x74,0x19,0xe4,0xce,0x14,0x94,0x95,0x95,0x44,0x96,0x02,0xab,0x8a,0x69, + 0x44,0x96,0x94,0xb2,0x42,0x8d,0x7f,0x69,0x46,0x2f,0xb3,0x2c,0x4f,0x1c,0x2c,0x55, + 0xb4,0x9c,0xbb,0xd4,0x9e,0xf2,0x56,0xc9,0xfd,0x7d,0x2d,0x7b,0x31,0xec,0x6d,0x69, + 0x79,0xf6,0x17,0x0f,0xef,0xfe,0xf8,0xf4,0xb7,0x5b,0x78,0x76,0x2f,0xd0,0x32,0x0f, + 0xc7,0x2c,0xd3,0x22,0xa5,0x98,0xe5,0x85,0x50,0x3a,0x3f,0x7f,0x06,0xb6,0xb6,0xaa, + 0xb6,0xad,0xb8,0x0f,0xff,0x36,0x65,0xa9,0x37,0xac,0x2f,0xab,0x2f,0xe0,0x34,0xf7, + 0x28,0x73,0xa1,0x9a,0x53,0x73,0x39,0x47,0x4e,0xa2,0xb2,0xd4,0xa1,0x62,0x44,0xb1, + 0x03,0x82,0xa9,0xa0,0x8a,0xd4,0x54,0xe7,0x4a,0x0e,0x2e,0xc2,0x52,0x5e,0x43,0x15, + 0xaa,0x2a,0x2b,0x74,0x70,0x3d,0x59,0x0b,0x04,0x0e,0x07,0x2f,0xc9,0x99,0x12,0xeb, + 0x69,0x1d,0xaa,0x45,0xb5,0x74,0x6a,0x69,0xd7,0x61,0x36,0x43,0x18,0x7d,0xbf,0xa6, + 0x7d,0xae,0x66,0xae,0xa6,0xbd,0x46,0x32,0x27,0xe2,0xfb,0xb8,0x13,0x39,0xa4,0x9d, + 0xeb,0xb4,0xf3,0x80,0xc7,0xed,0xed,0xed,0x67,0xce,0xcc,0xb7,0x8d,0xb5,0x6c,0xf5, + 0x2b,0xd0,0x19,0xb8,0x06,0x1a,0xfe,0x20,0x4e,0xa4,0x99,0x07,0x53,0x70,0x3b,0xde, + 0x9c,0xdb,0x95,0xdf,0x46,0xef,0x16,0xe2,0xad,0x5a,0xdc,0x22,0x67,0xcf,0xde,0x84, + 0xc0,0x92,0xa3,0x17,0x59,0x6a,0x4a,0xf8,0xc1,0xcd,0x8b,0x67,0x21,0xf0,0x1c,0x66, + 0x70,0x8f,0xe9,0xc5,0x8b,0x73,0x73,0x73,0x35,0x67,0xf6,0xb6,0x55,0xbd,0xbb,0x45, + 0xef,0x21,0xf9,0x86,0x50,0x24,0x6c,0x0b,0x2e,0x3b,0xd4,0xff,0xcb,0xab,0xf9,0xac, + 0xb9,0x69,0x3a,0x8f,0x7b,0x4c,0x64,0xce,0x96,0x49,0x85,0xd2,0xcd,0xb3,0xd6,0x80, + 0xee,0x43,0xef,0x8d,0x35,0xbd,0x70,0x7b,0xaf,0x59,0xc7,0x70,0x64,0xc9,0x17,0x81, + 0x39,0x5d,0x50,0x59,0x4e,0xb2,0x41,0xe1,0x60,0x83,0x18,0x70,0xb0,0xc1,0x2c,0xf2, + 0xa5,0xc0,0x4a,0x73,0xa6,0xd0,0xc4,0xac,0x67,0x26,0x0e,0xa1,0x9a,0x53,0x73,0x52, + 0xd7,0x61,0x4a,0xf0,0x00,0xab,0x38,0x2c,0xd6,0xb8,0x80,0x1f,0x9a,0x96,0x73,0x66, + 0x2b,0x54,0x8b,0x75,0xa6,0x21,0x54,0x1d,0x66,0x4b,0xde,0xc7,0x2e,0xc4,0x37,0x33, + 0xe2,0x60,0x9e,0x9b,0x2b,0x15,0x48,0x6a,0x4a,0x7b,0x8c,0xed,0x35,0x30,0x72,0xdb, + 0xaa,0x9a,0xe6,0xef,0xf8,0x87,0x5c,0xc9,0xde,0xa5,0x1d,0xce,0xa2,0x96,0xb7,0x15, + 0x12,0x41,0xcb,0x97,0x20,0xb7,0x8c,0xbe,0xbe,0xd2,0x46,0x46,0xee,0xd0,0xf8,0x1d, + 0xa9,0xeb,0xf7,0xbd,0x6b,0xde,0x27,0x24,0x2d,0xb7,0x08,0x82,0x79,0x79,0x34,0xcf, + 0xf4,0xda,0xda,0xda,0xc6,0xaa,0x9a,0xae,0xb7,0x7c,0xf5,0x4e,0xbd,0xc7,0xfa,0x60, + 0x21,0x12,0x0a,0x8d,0x38,0x2b,0x8b,0x45,0xb7,0x81,0x13,0x01,0x43,0xce,0x06,0x3e, + 0x2d,0x8c,0x72,0x63,0x9f,0xa6,0x69,0xc1,0xbf,0xff,0xd0,0xdf,0xcf,0x26,0x21,0xfd, + 0xa5,0xd8,0x6f,0x39,0x6a,0x12,0xbb,0xd2,0x6c,0x45,0x6a,0x0b,0xae,0x7f,0xfd,0xfa, + 0x58,0xfb,0xff,0xfe,0x23,0xc2,0xd4,0x62,0xc2,0xaf,0xb9,0xc1,0x83,0x88,0xbb,0x28, + 0x30,0x64,0x14,0x9b,0x9b,0x97,0xb9,0x65,0x21,0x1e,0x72,0x05,0x77,0x49,0xc0,0x0f, + 0x4c,0x1b,0x5c,0x2c,0x8d,0x18,0x56,0xa9,0xd0,0x75,0x5b,0xaa,0x95,0xb4,0xdc,0xb2, + 0xcc,0xd2,0x02,0xf7,0x9a,0x16,0x71,0xfd,0xef,0xfd,0xf2,0xc1,0x73,0x4d,0xe7,0x9a, + 0xca,0x58,0x93,0x5d,0xc7,0x39,0x8c,0xe7,0xb8,0xde,0xb9,0xa6,0xfe,0xb6,0x96,0x33, + 0x73,0x9f,0xc5,0xdf,0x19,0x13,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04, + 0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41, + 0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10, + 0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04, + 0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41, + 0x10,0x04,0x41,0x10,0x5b,0xe6,0xbf,0x9f,0xe5,0x54,0xe2,0x36,0x30,0x01,0x00, diff --git a/board/esd/hh405/logo_640_480_24bpp.c b/board/esd/hh405/logo_640_480_24bpp.c new file mode 100644 index 0000000..c042b6b --- /dev/null +++ b/board/esd/hh405/logo_640_480_24bpp.c @@ -0,0 +1,4209 @@ + 0x1f,0x8b,0x08,0x08,0xc2,0xbb,0x0b,0x40,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x2d,0x48, + 0x65,0x72,0x5f,0x64,0x74,0x5f,0x33,0x43,0x5f,0x36,0x34,0x30,0x5f,0x34,0x38,0x30, + 0x5f,0x32,0x34,0x62,0x70,0x70,0x2e,0x62,0x6d,0x70,0x32,0x00,0xec,0xdd,0x09,0x58, + 0x56,0x55,0xfe,0xc0,0x71,0x67,0x46,0x4d,0x51,0x01,0xd9,0x71,0x21,0x0b,0x5c,0x73, + 0xdf,0xcd,0xdd,0x4c,0x4d,0x65,0xb1,0x5c,0x13,0x97,0xd2,0x6a,0xfe,0x93,0xa2,0xa9, + 0xa5,0x36,0x35,0x8d,0xe5,0x56,0xa9,0x65,0x8b,0xb2,0xa9,0x28,0x8b,0x0a,0x4e,0x69, + 0x8a,0x1b,0x6e,0xa0,0xa0,0x36,0xb9,0x2f,0x61,0x66,0xa9,0x60,0x08,0x2e,0xec,0x28, + 0x4b,0xff,0xe7,0xff,0x7b,0xa1,0xa1,0xd7,0x7b,0xee,0x7d,0x79,0xe1,0xdf,0xf2,0x3c, + 0xcd,0xd7,0xe7,0x23,0x4f,0xca,0xb9,0xe7,0x9e,0x7b,0xee,0x39,0xf7,0x77,0x7e,0xe7, + 0xbd,0xd8,0x00,0xef,0xae,0xf6,0xb6,0xd5,0x4c,0xbf,0xba,0xca,0xef,0x16,0xf2,0xfb, + 0x9f,0x7f,0xae,0x56,0xed,0xea,0x9f,0xaa,0x55,0xfb,0x53,0x35,0xb7,0xd2,0xbf,0xaf, + 0x26,0xdf,0xf7,0x6c,0x5b,0xad,0xf4,0xf7,0x7f,0x7e,0x95,0xfc,0x6f,0x09,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x54,0x7b,0xf7,0xed,0x5b,0xf9,0xf1,0xc7,0x1a,0x1b,0xa3,0xa3,0x73,0xf3,0xf3,0x8b, + 0x4b,0x7e,0xff,0xe6,0x01,0x00,0xf0,0x87,0x34,0x71,0xe2,0x73,0xd5,0xff,0x5c,0x5d, + 0xa3,0x6b,0xe7,0xae,0xe9,0xb7,0x32,0x7e,0xf7,0xb6,0x01,0x00,0xf0,0x47,0x35,0xc1, + 0x28,0xfe,0x66,0xa4,0xff,0xee,0x6d,0x03,0x00,0xe0,0x8f,0xca,0x7f,0xc2,0x64,0x9d, + 0xf8,0xdb,0xa5,0x5b,0xda,0xcd,0xb4,0xdf,0xbd,0x6d,0x00,0x00,0xfc,0x51,0xe9,0xee, + 0x3f,0x77,0xee,0xd4,0x25,0xfd,0x16,0xf9,0x2f,0x00,0x00,0xbf,0x96,0xf1,0x13,0x26, + 0xe9,0xe6,0xbf,0x19,0x7c,0xfe,0x0b,0x00,0xc0,0xaf,0x86,0xfc,0x17,0x00,0x80,0xdf, + 0x9e,0xfe,0xfb,0xcf,0xe4,0xbf,0x00,0x00,0xfc,0x9a,0x78,0xff,0x0a,0x00,0x80,0xdf, + 0x9e,0x6e,0xfc,0xed,0xd2,0xa9,0x0b,0x3f,0x7f,0x04,0x00,0xc0,0xaf,0x67,0x9c,0xff, + 0x44,0x3e,0xff,0x05,0x00,0xc0,0x82,0xc2,0xe2,0xc2,0xdb,0x77,0xef,0x5c,0xbc,0x94, + 0x7c,0x28,0x3e,0xfe,0xb3,0xad,0x5b,0xd7,0x85,0x85,0x05,0x06,0x05,0x7f,0xf4,0xf1, + 0x27,0xc1,0x21,0xa1,0x11,0x91,0x91,0xb1,0xbb,0x76,0x1e,0xff,0xf2,0xf8,0xf7,0xd7, + 0xaf,0x16,0xdc,0x2f,0xb0,0xbe,0xce,0x0a,0x3f,0xff,0x2d,0xfe,0xb1,0xf8,0x66,0x46, + 0x7a,0xd2,0xb1,0x63,0x31,0x5b,0xb6,0xac,0x0a,0x0a,0xfe,0xf8,0x93,0x4f,0xe5,0xbc, + 0xdb,0x63,0x63,0x4f,0x9d,0x39,0x9d,0x95,0x9d,0x25,0xdf,0xad,0xfa,0xe5,0x14,0x15, + 0xa6,0x65,0xa4,0x7f,0x75,0xea,0xe4,0xee,0xbd,0x7b,0x36,0x84,0x87,0xaf,0x0e,0x0c, + 0xfa,0x78,0xd5,0x27,0x21,0xa1,0xa1,0x91,0x1b,0x37,0xee,0x89,0xdb,0x7b,0xe2,0xd4, + 0x49,0xf9,0xae,0x94,0xb1,0x50,0x43,0x5e,0x41,0x41,0x7e,0x41,0x7e,0x4e,0x5e,0x6e, + 0xd5,0xc8,0xb1,0x79,0xf9,0x79,0xf7,0xee,0xdf,0x53,0xfb,0x59,0xfe,0x5e,0x68,0x0a, + 0x17,0x95,0x14,0x59,0xbe,0xa2,0xfb,0x45,0xf7,0xaf,0xa5,0xa6,0xc4,0x27,0xc4,0x47, + 0x44,0x45,0x7d,0x1a,0xb8,0x3a,0x28,0x38,0xe4,0xf3,0xad,0x9f,0x9f,0x3c,0x7d,0xea, + 0xd6,0x9d,0xdb,0x9a,0x92,0x05,0xf7,0x0a,0x44,0x59,0xb5,0x65,0xf5,0xcb,0x1f,0xd5, + 0x0a,0xe5,0x8c,0xb9,0xf9,0xda,0x0b,0x94,0x43,0x74,0xbb,0x5d,0x0a,0xab,0xbd,0x21, + 0xd5,0x16,0x97,0x18,0xde,0x23,0xa9,0x27,0x4f,0x3a,0xc1,0x74,0x94,0x5c,0x6c,0x5e, + 0xd9,0x55,0xcb,0x1f,0x2d,0x77,0x7b,0xc1,0xbd,0x7b,0xa5,0xe5,0x1f,0x68,0x52,0x85, + 0xa3,0xae,0xa8,0xa4,0x58,0x6e,0xe8,0xb1,0x2f,0x8f,0xcb,0x40,0x92,0xbb,0xfc,0x69, + 0xe0,0xaa,0x4d,0xd1,0xd1,0x49,0x47,0x93,0x6e,0xa4,0xdd,0xd0,0x76,0x63,0xe1,0xfd, + 0xdc,0xd2,0x66,0xe4,0x96,0xdf,0xa6,0x02,0x9d,0xca,0xa5,0xf1,0xf2,0xad,0x6b,0xa9, + 0xd7,0x4e,0x94,0x0e,0xa1,0xc8,0xa8,0xa8,0xa0,0xd0,0x10,0x99,0x0e,0xd2,0xed,0x51, + 0x1b,0x37,0xee,0x3f,0x78,0xe0,0x62,0xf2,0xd7,0xd9,0xb9,0x39,0x55,0x1e,0xa2,0xd2, + 0x80,0x6f,0xbf,0xfb,0xee,0x50,0x42,0xc2,0xe6,0x98,0x98,0xc0,0x10,0xd3,0x44,0x93, + 0xe9,0x16,0xba,0x76,0xcd,0x96,0x7f,0xfd,0x2b,0x6e,0xff,0xbe,0xf3,0x17,0x2f,0xc8, + 0xbc,0x90,0xa1,0xf2,0x8b,0x8c,0x1c,0xe9,0x70,0xf3,0x1b,0x2d,0x17,0x2e,0x67,0x97, + 0x7b,0x57,0x54,0xac,0x73,0xa0,0x14,0x2e,0xaf,0xd9,0xfc,0x46,0xeb,0x16,0x2e,0xbb, + 0xc5,0xe5,0xe5,0xcb,0x6a,0x96,0xee,0xd5,0x2d,0xfc,0xc0,0xfd,0x2a,0x96,0xb1,0x97, + 0x57,0x7e,0x96,0xb2,0xaf,0x79,0x06,0x63,0xcf,0xc8,0xdd,0xac,0xcc,0xe4,0x6f,0x2f, + 0xef,0x3f,0x70,0x60,0x73,0x74,0xf4,0x9a,0xb5,0xeb,0xe4,0xe9,0x21,0xd3,0x5c,0x26, + 0xfb,0xe7,0xdb,0xb6,0x25,0x1e,0x4d,0xfa,0xfe,0xda,0x55,0xa9,0xb0,0xc2,0x4a,0x64, + 0x86,0xfe,0xdc,0x80,0xfc,0xbc,0xb2,0x56,0xa9,0xd3,0x56,0x25,0x87,0x68,0x66,0x84, + 0x74,0xf2,0xbd,0xc2,0xfb,0x55,0x1b,0x0f,0xf8,0xef,0x94,0x7f,0x2f,0xff,0xc4,0xa9, + 0xd3,0x1b,0x22,0x23,0x67,0xcc,0x98,0xf9,0xc4,0xc0,0x81,0x8f,0xb5,0x6a,0xdd,0xb0, + 0x41,0x23,0x87,0xfa,0x8e,0xf5,0xea,0xd6,0xab,0x6b,0x53,0xd7,0xa6,0xb6,0x4d,0x9d, + 0xda,0x75,0x6c,0xeb,0xd9,0x3a,0x39,0x3a,0x37,0xf1,0x68,0xd2,0xb1,0x63,0xc7,0x89, + 0x93,0x26,0x85,0xae,0x5b,0x73,0xf9,0xca,0xb7,0xf7,0x0a,0x2b,0x1e,0xa2,0x16,0xde, + 0x7f,0x96,0x89,0x96,0x72,0x23,0x25,0x30,0x28,0x48,0x4e,0xda,0xe4,0xe1,0x47,0x1c, + 0xec,0x1d,0x6c,0xe4,0x57,0x6d,0x1b,0x39,0xaf,0xb3,0xa3,0xb3,0x97,0x67,0x53,0x1f, + 0x5f,0xdf,0x55,0x41,0x41,0x29,0x37,0x52,0x2b,0x7c,0xbc,0x98,0x93,0x6a,0x33,0xb3, + 0x33,0x63,0x77,0xef,0x9d,0x35,0x67,0x4e,0xaf,0xde,0xbd,0x3d,0x1f,0xf1,0x74,0x75, + 0x71,0xb3,0xab,0x67,0x27,0x57,0x21,0x95,0xcb,0x15,0xd9,0xd9,0xda,0xbb,0xb9,0xb8, + 0x79,0x3e,0xea,0xd5,0xab,0x57,0xef,0xe9,0x01,0x33,0x24,0x84,0xfd,0x70,0x33,0x4d, + 0x42,0x9b,0xa6,0x1e,0x09,0x6a,0x2f,0xbc,0xf8,0x92,0x8f,0x9f,0xb4,0xc2,0x6f,0xb8, + 0x8f,0xb7,0xf9,0x57,0xf9,0x2b,0x6f,0x5f,0x9f,0xb2,0xaf,0xe5,0xff,0x21,0x5f,0x35, + 0xc5,0xfc,0xfc,0x46,0x78,0x7b,0xfb,0xcc,0x98,0xf9,0x4a,0xfe,0x83,0xb1,0x4f,0x9e, + 0xae,0x23,0x47,0x8d,0xf2,0xf1,0xf3,0x35,0x3f,0x76,0xc4,0x88,0xa7,0xaf,0x5c,0xbd, + 0x62,0x74,0x51,0xd2,0xd5,0xc7,0x8e,0x1f,0x7f,0x6d,0xee,0xbc,0x6e,0xdd,0x7b,0xc8, + 0xdd,0xb1,0xb7,0xb3,0x97,0xae,0x92,0x6b,0x71,0xa8,0xef,0xe0,0xe5,0xd5,0x74,0xd8, + 0xb0,0xe1,0xe1,0x91,0x91,0x69,0xe9,0x69,0x65,0xcf,0x2e,0x79,0x02,0x04,0x04,0xcc, + 0x90,0x4a,0x4d,0x35,0xfb,0xfd,0xd4,0xc8,0x79,0xf3,0xe7,0x6b,0x1e,0xe6,0xa6,0x96, + 0xc4,0xc5,0x8d,0x78,0x7a,0xa4,0xe6,0x8a,0x26,0x4e,0x9a,0x7c,0x31,0x39,0x59,0x6d, + 0x43,0xdc,0xbe,0xb8,0x67,0x9e,0xd1,0x2d,0xfc,0xb5,0x51,0xb3,0x2f,0x7f,0x77,0x65, + 0xea,0x8b,0x2f,0x4a,0x1b,0xa4,0xb0,0x89,0x4f,0xe9,0x57,0x3f,0xdf,0x5d,0x71,0xbb, + 0x8d,0x0e,0xb9,0x5f,0x54,0x38,0x77,0xde,0x3c,0xf3,0x53,0x94,0x1e,0xe2,0xf3,0xee, + 0x7b,0xcb,0xf2,0x0a,0xf2,0x74,0x0f,0x91,0xeb,0xfa,0x3a,0x39,0x79,0xd9,0xf2,0xe5, + 0xfd,0xfb,0x0f,0x28,0x1b,0x48,0x75,0x6c,0xea,0x08,0xe9,0x25,0x8f,0xc6,0x1e,0x3d, + 0x7b,0xf5,0x5a,0xf1,0xe1,0x87,0x97,0x2e,0x5f,0x2e,0x1f,0x45,0xcb,0x56,0x7c,0x20, + 0xb7,0xa6,0xac,0x7f,0xca,0xba,0xe8,0xf9,0x29,0x53,0x7e,0xb8,0x79,0xc3,0xac,0x0d, + 0xf7,0x0f,0xc4,0x27,0xbc,0xf5,0xcf,0x05,0xa3,0xc6,0x8c,0xee,0xd4,0xa9,0x93,0x0c, + 0x15,0x17,0x67,0x57,0x7b,0x5b,0xfb,0xba,0x75,0xea,0x96,0x0d,0x21,0xa9,0xd9,0xdd, + 0xad,0x41,0xcb,0x16,0xad,0x7c,0xfd,0xfc,0x3e,0x5c,0xb9,0x32,0xf9,0xf2,0x25,0x6b, + 0xe6,0x42,0x19,0x69,0x46,0x6a,0xda,0x8d,0xe8,0x98,0x98,0x67,0xc7,0xfb,0xb7,0x6f, + 0xdf,0xa1,0x51,0xc3,0xc6,0xf5,0xed,0xea,0x4b,0x6b,0x4d,0x13,0xad,0xb4,0xd9,0xf2, + 0x47,0x37,0x57,0xf7,0xe6,0xcd,0x5a,0xf4,0xed,0xdb,0x4f,0xda,0x90,0x95,0x93,0x55, + 0x7e,0x6c,0x42,0x52,0xe2,0xe8,0x31,0x63,0x34,0x23,0x47,0xae,0xe5,0xdc,0x85,0x0b, + 0x96,0x4f,0x1a,0xbd,0x65,0x8b,0x77,0xe9,0x2d,0x90,0xe2,0x3f,0x75,0xa9,0x8f,0xef, + 0x8b,0x2f,0xfd,0xf5,0xca,0xd5,0xef,0xd5,0xc2,0x07,0x0e,0x25,0x48,0x31,0x53,0x49, + 0x9f,0x9f,0x07,0xbf,0xff,0xa4,0x89,0x67,0xce,0x9d,0x53,0x0b,0x9f,0x3e,0x7b,0x6e, + 0xe4,0x48,0xd3,0xa8,0x30,0x0d,0x0c,0x9f,0x11,0xc3,0x7d,0x4d,0xc3,0x7e,0xec,0xb8, + 0x67,0x65,0xdd,0x6b,0xb9,0x49,0xdb,0x77,0xec,0x90,0xe1,0x54,0x76,0xa2,0xa1,0xde, + 0xc3,0xe4,0x28,0xa9,0xc1,0x7f,0xc2,0xc4,0x6b,0xd7,0xaf,0x57,0xd8,0x87,0x32,0x12, + 0xce,0x9e,0x3f,0x2f,0xb7,0x55,0xe6,0x57,0xeb,0xd6,0x6d,0x1b,0xb8,0x35,0x90,0x4e, + 0xfb,0xe9,0x61,0x65,0x53,0xc7,0xb6,0xae,0xad,0xa3,0x83,0x53,0xe3,0x46,0x1e,0x1d, + 0xda,0x77,0x94,0x53,0x7c,0x1a,0x14,0x24,0x85,0x73,0x0d,0x06,0x8f,0x04,0xe8,0xb7, + 0x17,0x2e,0x32,0x8d,0x04,0x1f,0x9f,0xb2,0x39,0x3b,0xdc,0xdb,0x74,0xbd,0x0b,0xde, + 0x7e,0xc7,0x72,0xec,0x96,0x59,0x36,0x65,0xca,0x54,0x39,0xca,0x7c,0xee,0xfb,0x8c, + 0xf0,0x0b,0x59,0xb3,0x46,0x7d,0x98,0x00,0x46,0x76,0xc7,0xed,0x71,0x71,0x76,0xa9, + 0x59,0xbd,0xa6,0x1a,0x28,0x8d,0x48,0xe1,0x66,0xcd,0x5b,0xbc,0xb5,0x60,0x41,0xf2, + 0x37,0x97,0x2c,0x57,0x6e,0x94,0xff,0xde,0x4c,0xbf,0xf9,0xd5,0x89,0x13,0x7d,0xfa, + 0xf6,0xa9,0xfd,0x50,0x6d,0x0b,0x27,0x7a,0xa8,0x66,0xad,0xde,0xbd,0xfb,0xc4,0xee, + 0xdc,0x69,0xe5,0xaa,0x52,0xb2,0xa4,0xad,0xdb,0xb7,0xc9,0x83,0xa6,0x6e,0xdd,0xba, + 0x56,0x5e,0x4b,0xed,0x5a,0xb5,0xbb,0x77,0xef,0x21,0x73,0xf9,0x6e,0xd6,0x5d,0xf3, + 0xaa,0xae,0xa7,0x5c,0x6f,0xd6,0xac,0xb9,0xf5,0x7d,0x62,0xa4,0x5d,0xfb,0x76,0x99, + 0xd9,0x3f,0x3f,0x42,0x25,0x44,0x06,0x87,0x86,0xca,0xb3,0x42,0x7b,0xa5,0x35,0x1e, + 0x92,0xa7,0x84,0xee,0x45,0xa5,0xdd,0x4c,0x5b,0xb2,0x74,0xa9,0xab,0xab,0x9b,0x85, + 0xb3,0xd8,0xd4,0xb2,0x79,0xf2,0xc9,0x41,0x87,0xe2,0x0f,0x49,0x30,0xba,0x9b,0x95, + 0xd5,0xa8,0x51,0x63,0x4d,0x81,0x41,0x83,0x86,0xdc,0x57,0xfa,0x30,0x30,0x38,0x50, + 0xce,0xab,0x29,0xe9,0xee,0xde,0xf0,0x48,0x52,0x92,0xda,0x8c,0x90,0xd0,0x35,0x6a, + 0x61,0x89,0x14,0x87,0x13,0x13,0x8d,0x6e,0xc7,0x89,0xd3,0x27,0x3d,0x1f,0xf5,0x54, + 0x5b,0xbb,0x2a,0x28,0xd8,0xe8,0x10,0x49,0x40,0x64,0x5d,0xa4,0x1e,0x32,0x66,0xcc, + 0x18,0xf3,0x48,0x54,0x2e,0x37,0x3f,0x77,0x43,0x78,0x44,0x8b,0xe6,0x2d,0x2c,0x0c, + 0x60,0x69,0xb6,0x44,0x3a,0x49,0x60,0x0b,0x4a,0x93,0x1a,0xe9,0x0a,0x4d,0x01,0x2f, + 0x2f,0x2f,0xb9,0xdd,0xe5,0x75,0xde,0xc9,0xbc,0x33,0xf0,0xc9,0x81,0xd6,0xcf,0x05, + 0xaf,0x66,0xcd,0x16,0x2d,0x59,0x9a,0x7a,0x43,0x9b,0x68,0xeb,0xb5,0x36,0x2f,0x62, + 0x63,0x54,0x8f,0xc7,0x7b,0xca,0xa8,0xb3,0xa6,0xf2,0x96,0x2d,0x5b,0xa5,0xde,0x48, + 0x2d,0x3f,0x7c,0x73,0x4c,0xb4,0x6d,0x3d,0x3b,0xb5,0x58,0x42,0xe2,0x61,0xcb,0xe7, + 0x5d,0xbc,0xf4,0x5d,0xf5,0xa8,0xa6,0x9e,0x4d,0x4f,0x9f,0x39,0xa3,0x16,0x0e,0x8f, + 0x8a,0x50,0x0b,0xcb,0x8d,0xde,0x7f,0xf0,0xa0,0x5a,0x78,0xef,0xbe,0x7d,0x12,0xf5, + 0x34,0x85,0x65,0xfd,0xfc,0xc5,0xf6,0x1d,0x96,0x9b,0xf4,0xfe,0xf2,0x15,0x6a,0x27, + 0xc8,0x83,0xe8,0xcc,0x59,0x9d,0x28,0x6f,0x3e,0x7d,0x64,0x51,0xf7,0xf2,0xb4,0x69, + 0xb2,0xd0,0xb2,0xfe,0x06,0x79,0x78,0x34,0x91,0xc5,0xc6,0xa9,0xb3,0xa7,0xd4,0x0a, + 0x65,0x6e,0x0e,0xf3,0x1e,0xae,0x1e,0x35,0xe4,0xa9,0xa7,0xcc,0xa7,0xad,0x2a,0x3b, + 0x37,0xa7,0xc9,0xc3,0x4d,0xd4,0x73,0xcd,0x98,0x39,0xb3,0xc0,0x8a,0xdc,0x19,0x28, + 0x73,0x30,0x21,0xa1,0xc6,0x5f,0x6a,0x58,0x39,0x98,0xcd,0xd5,0x7e,0xc8,0xa6,0x5d, + 0xbb,0xf6,0xb1,0xbb,0x76,0x4a,0x06,0x6d,0x54,0xb9,0x6e,0xfc,0xed,0xd4,0xb1,0x73, + 0x58,0xd8,0xfa,0xf6,0x6d,0x3b,0x58,0x73,0x5e,0x29,0xe3,0xd1,0xf8,0xe1,0x95,0x2b, + 0x3f,0xba,0x57,0x54,0xc1,0xa8,0x4e,0xb9,0x91,0x3a,0x73,0xd6,0x2c,0x99,0xc2,0x55, + 0xb8,0x9c,0x86,0xee,0x0d,0x8f,0x1e,0x3f,0xfe,0x40,0x6d,0xa9,0x29,0x5e,0x9e,0x5e, + 0x55,0xe8,0x16,0x8d,0xb6,0xed,0xdb,0x67,0xe5,0xe4,0x96,0x57,0x5b,0xfc,0x63,0x49, + 0x68,0xe8,0x3a,0x35,0xfe,0x4a,0x9b,0x75,0xe3,0xaf,0x3c,0x7e,0xc7,0x8d,0x7d,0x56, + 0x92,0x77,0x6b,0x3a,0x4a,0x1a,0xbc,0x69,0xf3,0x66,0xc9,0x20,0x1c,0x1c,0x1c,0x34, + 0xdf,0x7d,0x66,0xd4,0x68,0xb5,0xf2,0xa0,0xe0,0x10,0xdd,0x90,0x9a,0x68,0x75,0xfc, + 0x75,0x71,0x71,0x3d,0x62,0x1c,0x7f,0x25,0x09,0x7a,0xf4,0x51,0x9d,0x3e,0x5c,0x15, + 0x18,0x68,0x74,0x88,0xc4,0x5f,0x59,0x71,0xa9,0x87,0x8c,0x19,0x3b,0x56,0x7d,0x1e, + 0x66,0x65,0xe7,0xcc,0x9d,0xff,0xba,0x24,0x3b,0xd6,0x74,0x8e,0xb3,0x93,0xf3,0xd2, + 0x77,0xdf,0xbb,0x9b,0x95,0xd9,0xb9,0x4b,0x57,0xcd,0x77,0xdb,0xb4,0x69,0x9b,0x96, + 0xfe,0xf3,0x0b,0x09,0x99,0x39,0x59,0x3e,0xbe,0x7e,0x95,0xba,0xcb,0x75,0xeb,0xd4, + 0x1b,0x3c,0x68,0xc8,0xe5,0x2b,0x57,0x2c,0x6c,0x9f,0x5e,0xbd,0x76,0x2d,0x20,0x60, + 0x86,0x43,0x7d,0x47,0xeb,0xc7,0xa7,0xe6,0x4d,0x09,0x49,0x63,0xed,0xf4,0xe2,0x6f, + 0x7c,0x62,0xbc,0xe5,0xa9,0xb1,0x64,0xe9,0x7b,0xea,0x51,0x5e,0x9e,0x4d,0x4f,0x9d, + 0x39,0xad,0x16,0x8e,0x88,0x88,0x52,0x0b,0xcb,0xa8,0xd8,0x77,0xf0,0x80,0x5a,0x78, + 0x4f,0xdc,0x3e,0x75,0x09,0xed,0xe4,0xe8,0xbc,0xed,0x8b,0xed,0x96,0x9b,0xb4,0xe2, + 0x83,0x0f,0x6b,0x3d,0x54,0x4b,0x73,0xa0,0xdc,0xa3,0xd3,0x67,0xcf,0x1a,0x1d,0x22, + 0xcf,0x99,0xc8,0xa8,0x8d,0x6d,0xdb,0xb6,0x57,0xc7,0x61,0x85,0xe4,0x90,0x37,0xfe, + 0xf1,0x96,0xfa,0xff,0x5c,0x93,0x41,0x25,0x49,0xb4,0x5a,0x7e,0xc8,0x50,0x6b,0xe2, + 0xaf,0x76,0x0d,0x20,0xf1,0x77,0xa6,0x29,0xfe,0x56,0xe2,0x13,0x3a,0xfc,0x97,0x3b, + 0x77,0xe1,0x82,0x95,0xab,0x71,0x5d,0x8f,0x3c,0xf2,0x48,0xe4,0xa6,0x8d,0x46,0x95, + 0xeb,0xfe,0xfb,0x57,0xee,0xee,0x0d,0x9a,0x78,0x68,0x97,0x8e,0x96,0x99,0x56,0xd4, + 0x3b,0x63,0x0b,0x8d,0x3f,0x54,0xba,0x91,0xf6,0xc3,0xd4,0x17,0x5e,0xb2,0x9c,0x4d, + 0x5b,0xaa,0xdf,0xc9,0x59,0x93,0xf4,0x5d,0x4f,0x4d,0x69,0xfe,0x8b,0xe4,0xbf,0x1d, + 0x3a,0x5a,0x93,0xff,0xca,0xcc,0x55,0xe3,0xaf,0x04,0xa3,0x39,0x73,0x5e,0x93,0xdc, + 0xd6,0xfa,0xd3,0xb5,0x7e,0xac,0xcd,0xfa,0xf0,0x08,0xdb,0x7a,0xb6,0x9a,0xbf,0x9f, + 0xfc,0xdc,0xf3,0x6a,0xa7,0x85,0x84,0xea,0xc7,0xdf,0xa4,0xa3,0x47,0xd5,0xc2,0xa1, + 0x6b,0xd7,0xaa,0xe3,0xc4,0x94,0xff,0x1e,0x39,0x62,0x74,0x53,0x4e,0x1a,0xe6,0xbf, + 0x41,0x46,0x87,0x18,0xe5,0xbf,0xa3,0x47,0x8d,0xd6,0xe4,0xbf,0x92,0xe9,0xaf,0x0d, + 0x0b,0x73,0x74,0x70,0xb4,0xbe,0x73,0xdc,0xdc,0xdc,0x25,0xf4,0x4b,0xb4,0xd5,0xfc, + 0x7d,0xd7,0xae,0xdd,0xee,0x64,0x66,0x96,0xd7,0x9c,0x93,0x97,0x3b,0xde,0x7f,0x62, + 0x15,0x56,0x71,0x23,0x47,0x8f,0x91,0x61,0xa3,0x7b,0x5d,0xd9,0xb9,0xb9,0xfe,0xfe, + 0x13,0xac,0x59,0x47,0x99,0x93,0xae,0xb8,0x75,0xe7,0x56,0x79,0x25,0xd1,0x31,0xfa, + 0xf1,0x57,0x96,0xd0,0x96,0xe7,0xf8,0xe2,0x25,0x95,0x88,0xbf,0xe1,0x7a,0xf1,0xd7, + 0xdd,0xad,0xc1,0xc1,0xf8,0x43,0x6a,0xe1,0xb8,0xfd,0x07,0xeb,0xd8,0x68,0x2f,0xca, + 0xc9,0x94,0xff,0x56,0x10,0x7f,0x75,0xf3,0x5f,0x37,0x57,0x37,0xdd,0x5d,0xee,0x92, + 0xd2,0x0f,0x05,0xd6,0x6f,0xd8,0xd0,0x58,0xd9,0xd8,0xb1,0xde,0xdc,0xf9,0xf3,0xd5, + 0x6a,0xb3,0x72,0x72,0xbc,0xbd,0x7d,0xd5,0xc2,0xd6,0xc4,0x5f,0xb5,0x31,0x35,0xaa, + 0xd7,0x08,0x98,0x1e,0x40,0xfc,0x85,0xf5,0x52,0xd3,0xd2,0x9c,0x9c,0x9c,0xab,0x3c, + 0xaa,0x45,0xe3,0xc6,0x1e,0x71,0xfb,0xf7,0x17,0xe9,0xbd,0x87,0xa3,0x9b,0xff,0x56, + 0x4d,0x9b,0x36,0xed,0x4e,0x9e,0xd2,0xd9,0x41,0x2a,0x29,0xfd,0x10,0x67,0xbc,0xff, + 0x84,0x5a,0x35,0xb5,0xcb,0xe9,0x72,0x32,0xd3,0x1d,0xea,0x3b,0x48,0xb0,0x70,0x71, + 0x76,0xb3,0xb3,0xb5,0x53,0xf7,0x2a,0x9d,0x9d,0x5c,0x8e,0x3c,0x18,0x74,0x24,0x8b, + 0xd4,0x8d,0x1d,0x95,0xd5,0xae,0x43,0xbb,0xec,0x9c,0x9c,0xf2,0x6a,0x25,0xfe,0x4a, + 0x20,0xd3,0xd9,0x7f,0xae,0xa9,0xb3,0xff,0x1c,0xbb,0x6b,0x97,0x1a,0x49,0xcb,0xd4, + 0xac,0x51,0x53,0x2e,0xc4,0xd5,0xc5,0xcd,0xc9,0xd1,0x49,0xf3,0x1c,0x6b,0xf2,0x70, + 0x13,0xa9,0x4d,0x53,0x3e,0x60,0xc6,0x4c,0xb5,0xdf,0x8c,0xf2,0x5f,0xdd,0xf8,0x6b, + 0xb4,0xff,0x5c,0x51,0xfe,0x5b,0xf9,0xf8,0xdb,0xb3,0x97,0x7a,0xc8,0xb8,0x71,0xe3, + 0x34,0xf1,0xf7,0xfc,0xc5,0x8b,0xcd,0x9b,0xea,0x2f,0x90,0x24,0x74,0x4a,0x9c,0x92, + 0xce,0x71,0x71,0x76,0xad,0x5b,0xe7,0x81,0xae,0x36,0x7d,0x92,0x6b,0x57,0x5f,0x53, + 0xbe,0x4f,0x9f,0xbe,0x72,0xde,0xf2,0x9a,0x25,0xcf,0x9a,0x3e,0x3d,0xc0,0x7c,0x90, + 0xc8,0xba,0xce,0xb1,0xbe,0xe3,0x4f,0x15,0x2a,0xf7,0xae,0x9c,0x8c,0xc0,0x39,0xaf, + 0xbe,0xaa,0x7e,0xce,0x9e,0x99,0x9d,0x29,0xfd,0x5f,0x85,0xc1,0x33,0x64,0xc8,0x50, + 0xf3,0x8f,0x45,0x36,0xc7,0xc4,0xe8,0xee,0x3f,0x5b,0xf8,0x08,0xa0,0xcc,0xa2,0xc5, + 0x3a,0xfb,0xcf,0x86,0xf9,0x6f,0x94,0x6e,0xfc,0x75,0x3f,0x70,0x48,0x67,0xff,0x79, + 0x4f,0x5c,0x9c,0x9a,0xc6,0x3a,0x3a,0x38,0xed,0x88,0x8d,0xb5,0xdc,0xa4,0x65,0xcb, + 0x3f,0x50,0x57,0xcb,0x32,0x0d,0x75,0xf3,0xdf,0xa2,0xe2,0xa2,0xa8,0x4d,0x9b,0x2c, + 0xac,0xb5,0x64,0x64,0xda,0xdb,0xd9,0xcb,0x0d,0x92,0x01,0x29,0x33,0x5d,0x77,0x1d, + 0xfe,0xda,0xbc,0x79,0xea,0xee,0x84,0x04,0xd9,0xa1,0xc3,0x87,0xa9,0x85,0x87,0x0d, + 0x1b,0x5e,0x85,0xf8,0x4b,0xfe,0x8b,0xca,0xca,0xce,0xc9,0x36,0xdf,0x48,0x91,0x67, + 0x48,0x7d,0xbb,0xfa,0x1e,0x8d,0x3d,0x1e,0x6b,0xd3,0xba,0xc7,0xe3,0x8f,0xf7,0x7c, + 0xbc,0x67,0xab,0x56,0x6d,0xdc,0x5c,0xdc,0x2d,0x2c,0xdd,0x65,0xd4,0x0d,0x1b,0xe6, + 0x9d,0x71,0xfb,0x96,0x5a,0xf9,0xb3,0x7a,0xf9,0xaf,0xf9,0x73,0x52,0x26,0x4b,0xdf, + 0x7e,0xfd,0x67,0xcd,0x9e,0xbd,0x60,0xe1,0xa2,0x97,0xa7,0x4d,0xef,0xd6,0xad,0x47, + 0xbd,0x3a,0xf5,0x8c,0xa6,0xd8,0x8c,0x59,0xb3,0xd5,0x77,0xb1,0xee,0x17,0x15,0x86, + 0x87,0x47,0xe8,0x3e,0x15,0xe5,0x5a,0x9a,0x7a,0x35,0x9b,0x3c,0xf9,0xf9,0xb0,0x0d, + 0xeb,0xf7,0xc6,0xed,0x93,0xb0,0x72,0xf0,0x50,0xc2,0xd6,0x2f,0x62,0x65,0xed,0xed, + 0x3f,0x61,0x52,0xeb,0xc7,0x5a,0xdb,0xd9,0xda,0x97,0xa5,0x39,0x92,0x5f,0x6b,0x1e, + 0x62,0xd7,0x52,0xae,0x1b,0xed,0x3f,0x97,0x3d,0xde,0xe5,0x51,0xec,0xe2,0xe4,0x6a, + 0xfa,0x6a,0x51,0xff,0xfe,0x03,0x64,0xaa,0x96,0x57,0x6b,0x8a,0xbf,0x6b,0x74,0xe2, + 0xaf,0xba,0xff,0x9c,0x7f,0xaf,0x60,0xea,0xd4,0x17,0x74,0xfb,0x41,0x5a,0xbe,0x68, + 0xf1,0x92,0x6d,0x5f,0x6c,0x3f,0x7c,0x24,0x69,0xdf,0xfe,0x03,0xa1,0x6b,0xc3,0x7c, + 0x7c,0x7c,0x25,0x85,0xb7,0x90,0xb2,0xcd,0x9d,0x3b,0x4f,0xbd,0x3b,0xbf,0x48,0xfc, + 0x8d,0x3f,0x6c,0xf8,0xe1,0xa3,0x61,0xfc,0xb5,0xb8,0xff,0xdc,0xab,0xa7,0xce,0xfe, + 0xb3,0x9a,0xff,0x7e,0xf4,0xc9,0x27,0xea,0x32,0x43,0x86,0xa2,0xac,0x06,0x5f,0x99, + 0x35,0x5b,0x52,0x45,0x49,0xcc,0x0f,0x1e,0x3a,0x1c,0x1d,0x13,0x33,0x65,0xca,0x54, + 0x8f,0xc6,0x0f,0x5b,0xf8,0x80,0x78,0xd0,0xa0,0xc1,0xe6,0xef,0xbb,0xde,0x2b,0xbc, + 0xff,0xf7,0x37,0xde,0x94,0x01,0xef,0x60,0xef,0xd0,0xa3,0xc7,0xe3,0xd3,0xa6,0x4d, + 0x0f,0x0e,0x09,0xdd,0xb5,0x67,0x8f,0x54,0x78,0xe0,0x60,0x42,0xd4,0xe6,0x4d,0x7f, + 0xfd,0xdb,0xff,0xc8,0x04,0xd1,0xad,0xb0,0x79,0xb3,0x16,0x97,0x2e,0x7f,0xa3,0xb9, + 0xa8,0x4d,0xd1,0x31,0x2e,0x2e,0x2e,0x46,0x73,0x47,0x6e,0x5c,0xcf,0x9e,0xbd,0x5e, + 0x7e,0x79,0xfa,0x82,0xb7,0x17,0xbd,0xf9,0xd6,0xdb,0x53,0x5f,0x78,0xa9,0x7f,0xbf, + 0x01,0x8d,0x1a,0x36,0x92,0x89,0xf0,0xf4,0xd3,0x23,0xb3,0x72,0xb2,0xcd,0xeb,0xd1, + 0x8d,0xbf,0xf1,0x89,0x15,0xe4,0xbf,0x0b,0xf5,0x3e,0xff,0xad,0x64,0xfc,0x6d,0x60, + 0x7d,0xfc,0x95,0x35,0xe1,0x8e,0x9d,0x3b,0x2d,0x37,0xc9,0x94,0xff,0xea,0xc4,0x5f, + 0xfd,0xfd,0x67,0x99,0x1a,0xdd,0xba,0x75,0xd7,0x9d,0x89,0xf5,0xed,0x1c,0x64,0xf0, + 0x2f,0x59,0xfa,0xde,0xb6,0xed,0xb1,0xb2,0x14,0x3c,0x92,0x78,0x54,0x4e,0xbd,0x66, + 0xdd,0xba,0xd9,0x73,0x66,0xf7,0xe8,0xde,0xc3,0xd5,0xc5,0xb5,0x7c,0xd0,0x1a,0xc5, + 0x5f,0xfd,0xfd,0xe7,0x61,0x55,0xc9,0x7f,0x89,0xbf,0xa8,0x2c,0x59,0x5b,0x76,0xec, + 0xd8,0x59,0x06,0x8f,0x2c,0x20,0x07,0x0c,0x78,0xe2,0xf5,0xd7,0xff,0xbe,0x63,0x67, + 0xec,0xc5,0x4b,0xc9,0xe9,0xb7,0x6f,0xe7,0xe4,0xe6,0x65,0x66,0xe7,0xdc,0xcc,0x48, + 0xff,0xf7,0x57,0x27,0x96,0x2d,0x5f,0x21,0x53,0xc0,0xe8,0x93,0x17,0xc9,0x32,0x3e, + 0xfb,0x7c,0xab,0x5a,0xb9,0xee,0xbf,0xbf,0x51,0xae,0x5d,0xdb,0x76,0xe1,0x11,0x1b, + 0x33,0xb3,0x7e,0x1e,0xe7,0x69,0xe9,0x19,0x2b,0x56,0x7e,0xd8,0xc0,0xbd,0x81,0x6e, + 0x79,0xc9,0xec,0xce,0x5c,0xd0,0x4e,0xcf,0x6f,0x2e,0x5f,0xee,0xdc,0xb9,0x8b,0x5a, + 0x58,0x32,0xc7,0xbf,0x4d,0x9b,0x26,0x59,0x52,0x61,0xb1,0x4e,0x62,0x5e,0x58,0x54, + 0x2c,0x11,0x36,0x3c,0x72,0xe3,0xa8,0xd1,0x63,0x65,0xbd,0x51,0x9a,0xff,0x3e,0xb0, + 0xff,0x7c,0x37,0x2b,0x6b,0xf0,0x60,0xed,0x8b,0x3a,0xd5,0xff,0x13,0x01,0x9f,0x7e, + 0x66,0x64,0x7c,0xe2,0x91,0x63,0x5f,0xfe,0xfb,0xf8,0x57,0x5f,0x99,0x9c,0x30,0x74, + 0xee,0xc2,0x79,0xf3,0x35,0x43,0xf1,0x8f,0x12,0xc8,0xf4,0xf2,0x5f,0xe5,0xfd,0xab, + 0xab,0xd7,0xaf,0x75,0xec,0xd0,0x49,0x3d,0xfb,0xc0,0x27,0x06,0x9e,0x55,0xf6,0xe8, + 0x72,0xf3,0x73,0x25,0x39,0x6a,0xd6,0xbc,0x99,0x51,0x08,0xfe,0xc7,0x82,0xb7,0xd5, + 0x4e,0x08,0x0a,0xf9,0x05,0xe2,0xaf,0x85,0xe4,0xcb,0x30,0xfe,0xae,0x5e,0x6d,0x74, + 0x88,0xd1,0xfe,0xb3,0x26,0xff,0xcd,0x2b,0xc8,0x1f,0xf7,0xec,0x78,0xb5,0x58,0x8b, + 0xe6,0x2d,0x63,0x77,0xed,0xd2,0xd4,0x29,0xf1,0x34,0xe1,0xc8,0x91,0xde,0x7d,0xfa, + 0xd5,0xac,0xae,0x3f,0x7a,0x65,0xf5,0x68,0xfe,0x72,0x5a,0x61,0x71,0x51,0xc8,0x9a, + 0xb5,0xd3,0xa6,0xcf,0xdc,0x1e,0x1b,0x7b,0x27,0xf3,0xae,0xfa,0xd0,0x2e,0x2c,0x2a, + 0xda,0x1b,0x17,0xd7,0xb6,0x6d,0x3b,0xb5,0x2a,0x09,0x9a,0x61,0x61,0xeb,0xcd,0x0f, + 0xb9,0x75,0x27,0xa3,0x6f,0xdf,0xbe,0xba,0xe7,0x95,0xf5,0xe1,0x53,0x43,0x87,0xee, + 0xdc,0xbd,0xfb,0xce,0x5d,0xb3,0x77,0xff,0x7e,0x2c,0xc9,0xcd,0xcb,0x3f,0x7b,0xfe, + 0x6c,0x60,0x70,0xf0,0xea,0xc0,0x60,0xf3,0x97,0xe7,0x7f,0x9b,0xf7,0xaf,0x8c,0xe2, + 0xaf,0xee,0xfe,0xb3,0x6e,0xfc,0xb5,0xe6,0xfd,0xab,0x65,0x2b,0x3e,0x50,0x5f,0xdc, + 0x32,0x7a,0xff,0x6a,0x5a,0xc0,0x2b,0xba,0xbb,0x5b,0x7d,0xfb,0xf6,0xfb,0x6c,0xeb, + 0x56,0xdd,0x17,0x95,0x8b,0x4b,0x4a,0x32,0xb3,0x32,0x0f,0x27,0x25,0x05,0xcc,0x9c, + 0xd5,0xb2,0x65,0xab,0x9a,0x35,0x6a,0xbe,0x36,0x77,0x9e,0xfa,0xb3,0x72,0x46,0xf1, + 0x77,0x68,0x55,0xf3,0xdf,0x80,0x00,0xf6,0x9f,0x51,0x39,0xcf,0x4d,0x79,0xf1,0xb9, + 0xe7,0xa7,0xc4,0xed,0xdf,0x2f,0x39,0xac,0xd1,0x4f,0x52,0x14,0x16,0x17,0x7e,0x77, + 0xf5,0xea,0xdc,0xb9,0xf3,0x8d,0xf6,0xdf,0xa4,0x06,0x75,0x22,0x58,0xd8,0x7f,0xf6, + 0xf0,0xf0,0x38,0x7a,0xfc,0x98,0xba,0x59,0x27,0x0d,0xf8,0x74,0x75,0x90,0xee,0x5e, + 0x93,0x4d,0xed,0x3a,0x4b,0xdf,0x7b,0x5f,0xf3,0x7a,0xff,0xfb,0xcb,0x96,0xab,0x1f, + 0x24,0xc9,0x5a,0xe2,0x9d,0x77,0x16,0x9a,0xe7,0x0e,0xba,0xe4,0x39,0x29,0x65,0xf6, + 0xc4,0xed,0x9f,0x1e,0x10,0x70,0x52,0x79,0x16,0x1d,0x4e,0x4c,0xea,0xd4,0x49,0x27, + 0xb2,0x0b,0x49,0xdb,0x57,0x07,0x85,0x54,0xe1,0x45,0x47,0xa3,0xcf,0x7f,0x85,0x26, + 0xfe,0x9e,0x3a,0x73,0x46,0x32,0x14,0x4d,0x19,0xc9,0xf8,0xb6,0x7c,0xf6,0x99,0xee, + 0x4b,0x3e,0xd2,0x93,0x3b,0x77,0xed,0x96,0x44,0x4f,0xb7,0xc1,0x0b,0x17,0x2f,0x52, + 0x0f,0x09,0x0a,0x09,0xfe,0xff,0xc7,0xdf,0x04,0x4b,0xf9,0xef,0x09,0x83,0xfd,0x67, + 0x8b,0xef,0x3f,0xeb,0xed,0x3f,0x6b,0xf2,0xdf,0x8c,0x5b,0x19,0xfd,0xfa,0xf5,0x53, + 0x8b,0xbd,0xf1,0xe6,0x5b,0xba,0x3f,0xb9,0x29,0x3d,0x76,0xe6,0xdc,0xf9,0x6e,0xdd, + 0x7b,0xe8,0x76,0x8e,0xac,0xa6,0x34,0x4f,0xe6,0xdc,0x82,0x3c,0x21,0x8b,0x25,0xa3, + 0x76,0x4a,0x08,0x5e,0xb5,0x3a,0x48,0xad,0x4a,0xba,0x68,0xce,0xab,0xaf,0x95,0x4f, + 0x22,0x59,0x7a,0x85,0x47,0x46,0xd8,0xdb,0xda,0xab,0x25,0x25,0xfb,0x9b,0xfc,0xdc, + 0xf3,0xd7,0x53,0x53,0x8c,0x5e,0xd9,0x92,0x63,0x35,0x93,0x71,0x73,0xcc,0x16,0x83, + 0xfd,0x67,0xc3,0x8f,0xe0,0xcb,0x2c,0xd2,0x8d,0xbf,0x5e,0x4d,0x4f,0x9f,0xad,0x44, + 0xfc,0x35,0xca,0x7f,0xd5,0xd9,0x67,0xcd,0xfe,0xf3,0xfb,0xcb,0x97,0x5b,0xb9,0xff, + 0x2c,0x8f,0x1d,0x17,0x57,0xed,0xee,0x81,0x44,0xba,0xc1,0x83,0x86,0x7c,0x9d,0x9c, + 0x5c,0xe1,0xcf,0x0b,0xcb,0x02,0xe6,0x62,0xf2,0xa5,0x05,0xef,0x2c,0x0c,0xd2,0x1b, + 0x75,0x46,0xfb,0xcf,0x4f,0x0d,0x1f,0x5a,0xb5,0xf8,0xfb,0xca,0x2b,0xb3,0x78,0xff, + 0x19,0x95,0x72,0xf5,0x7a,0x4a,0x6e,0x5e,0xae,0x35,0x25,0xb3,0x73,0xb2,0x7d,0x7c, + 0xfd,0x6a,0x54,0xd7,0x49,0xb2,0x3a,0x77,0xea,0x7c,0x2d,0x45,0xfb,0xb3,0x7b,0xba, + 0xef,0x5f,0x55,0x2f,0x7d,0x5f,0x74,0xe1,0xe2,0x25,0x46,0x67,0xc9,0xb8,0x9d,0x31, + 0xde,0xdf,0x5f,0xf7,0x40,0x5f,0x5f,0x3f,0xf3,0x79,0x21,0xb3,0x60,0xd0,0xa0,0xc1, + 0x6a,0xb1,0x71,0xe3,0xfd,0xd3,0xd2,0x6f,0x5a,0xdf,0x03,0xa6,0x7f,0x61,0x40,0x59, + 0xb5,0x4a,0x44,0xdb,0xb3,0x77,0xaf,0x93,0xc1,0xeb,0xb5,0x9e,0x9e,0x9e,0x3b,0x62, + 0x2b,0xd8,0x64,0x53,0x59,0x1f,0x7f,0x75,0x83,0x97,0xb3,0x93,0xf3,0xa9,0xd3,0x3a, + 0x7b,0x86,0xe5,0x0d,0x7e,0x75,0xee,0x5c,0xdd,0x7d,0xd1,0xe5,0x2b,0x3e,0x50,0xcb, + 0xff,0x22,0xf1,0xd7,0xc2,0xfb,0x57,0x86,0xf1,0xd7,0x72,0xfe,0x6b,0x45,0xfc,0xfd, + 0xe1,0x66,0x5a,0x77,0x25,0x98,0x4a,0xf3,0x36,0x44,0x46,0x5a,0xe8,0xfc,0xb0,0xf5, + 0x1b,0xec,0x6c,0x75,0xe2,0xd7,0xe8,0x31,0x63,0x2d,0xfc,0x2b,0x22,0x46,0xe2,0x0f, + 0x1f,0x56,0xab,0xaa,0xf1,0x97,0xff,0x63,0xef,0xba,0x83,0xa2,0x4a,0xb6,0xfe,0x3f, + 0xc6,0x05,0x95,0x8c,0x84,0x25,0x09,0x0a,0x98,0x40,0x17,0x30,0xad,0x88,0x04,0x73, + 0x76,0x15,0x31,0x3e,0x15,0x10,0x94,0xa4,0xae,0x6b,0x40,0x05,0xc3,0xaa,0x80,0xa8, + 0xa0,0xa2,0x6b,0x06,0x23,0x62,0xc2,0x8c,0xa8,0xeb,0x02,0x4a,0x0e,0x2a,0xa0,0x32, + 0x60,0x24,0x07,0x45,0xb2,0xb0,0x55,0xdf,0x19,0x46,0xe7,0x0d,0xb7,0x4f,0xdf,0x49, + 0xb8,0xaf,0xde,0xf7,0xa6,0xea,0x57,0x16,0x33,0xf6,0xed,0xb9,0xb7,0x6f,0x77,0xff, + 0xce,0x39,0x7d,0x42,0x47,0x67,0x17,0x57,0x7e,0x44,0x00,0xcc,0xab,0x05,0x0b,0x17, + 0xa1,0xeb,0x05,0xd4,0xfc,0xdc,0x97,0x42,0xc2,0xf7,0x18,0x38,0x1f,0x19,0x89,0xfa, + 0x03,0x08,0xb5,0x3f,0xef,0xdc,0x15,0x48,0x5e,0x25,0x26,0xff,0xe2,0xe7,0xbf,0x31, + 0xf7,0xee,0x91,0xfe,0x81,0x30,0x4b,0x6f,0x11,0x56,0x08,0x06,0x44,0xe4,0x5f,0x58, + 0x2f,0x87,0xfe,0x38,0x42,0xde,0x0f,0x70,0xdf,0x93,0xc4,0x44,0xd1,0x93,0x75,0x34, + 0x7e,0x69,0xfa,0x84,0xf1,0x29,0x4d,0xff,0x1d,0x37,0x4e,0x42,0xfd,0xd7,0xcb,0xcb, + 0x4b,0xa6,0xff,0xca,0xf0,0xfd,0x70,0x27,0x26,0x16,0x16,0x23,0x39,0x63,0xf5,0xf5, + 0xf4,0x13,0x93,0x13,0x19,0x8d,0x69,0xfa,0xaf,0xa5,0xe5,0x90,0xd7,0xef,0xde,0xb2, + 0xfc,0xca,0xa3,0xb8,0x78,0xd4,0xef,0xd7,0x40,0xdf,0xe0,0x15,0x87,0xc3,0x6f,0x96, + 0x92,0x9e,0xae,0xa9,0xa1,0xc5,0x68,0x03,0xec,0x96,0x4a,0xf1,0xd4,0x92,0x00,0x27, + 0xc3,0xc3,0x35,0x35,0x99,0x3f,0xc1,0x83,0x9e,0xae,0x5e,0x4a,0x5a,0x8a,0x58,0x19, + 0x7b,0x68,0xf1,0x47,0xa4,0xff,0x73,0x76,0x6e,0xae,0x71,0x1f,0x13,0x46,0x33,0xb9, + 0x1f,0xe4,0x59,0xce,0x5b,0x5b,0xb8,0xf9,0x10,0x9e,0x1a,0x19,0xf5,0x26,0x6f,0x35, + 0x78,0xef,0x3e,0xb2,0x71,0xfb,0x9c,0xff,0xd2,0x9d,0x6f,0xa9,0xfe,0xcf,0xac,0xfc, + 0x3b,0xf2,0x67,0xc4,0x5a,0xcb,0x88,0xff,0xad,0xfc,0x58,0x39,0x7e,0x02,0xa2,0xb6, + 0x84,0x86,0x1e,0x60,0x19,0x9c,0xa2,0xe2,0x22,0x7b,0x7b,0x07,0xf2,0x2a,0x27,0xa7, + 0xb9,0x2c,0xae,0xf5,0x28,0x40,0x39,0x85,0x89,0x41,0x76,0x05,0xfc,0xbb,0xd4,0xd9, + 0x85,0x9f,0x2a,0x24,0x2f,0x9f,0x43,0x1a,0x31,0x3a,0xb4,0x5a,0x9e,0xaf,0xdf,0xbc, + 0x29,0x6e,0xee,0xac,0x48,0x8a,0xfe,0x2b,0xd4,0xfe,0x8c,0xea,0xbf,0xe2,0x9e,0xff, + 0xa2,0xf6,0x67,0x94,0x7f,0x45,0xf1,0x7f,0xde,0xb3,0x77,0x1f,0xa9,0x38,0x93,0xfc, + 0x5b,0xf9,0xa9,0x6a,0xe6,0x2f,0xb3,0xc8,0x41,0x5e,0x8b,0x39,0x33,0x4b,0x00,0x69, + 0xce,0x7f,0xc9,0xf8,0x5f,0x99,0xff,0xb3,0x0c,0xdf,0x1b,0xcf,0x73,0xb3,0x8d,0xfb, + 0x18,0x63,0x2b,0x54,0x23,0xf6,0xfe,0x7d,0x46,0x63,0x1a,0xff,0xae,0x59,0xb3,0x96, + 0xb4,0x3c,0x0b,0xa2,0xba,0xa6,0xc6,0xb4,0x6f,0x7f,0xf2,0x42,0x90,0xff,0x1f,0xfc, + 0xf9,0x75,0x1f,0x80,0xed,0x2b,0xe2,0xcc,0x99,0xee,0xf2,0x4c,0x8d,0xc0,0xc2,0xc2, + 0xaa,0x1d,0x4d,0x40,0x9f,0x6b,0x3e,0xef,0xd8,0xb1,0xb3,0x1b,0xf1,0x2b,0x3c,0x38, + 0x38,0x38,0x64,0xe7,0x0a,0xc9,0x3e,0xc4,0xc0,0xb1,0x13,0x22,0xc5,0xff,0x96,0x94, + 0x96,0x8e,0x1c,0x89,0x78,0x22,0xf9,0xfb,0x6f,0x61,0x59,0xe0,0x65,0x95,0x65,0x13, + 0x30,0x7b,0x5a,0xe8,0x7e,0x84,0x98,0xbe,0x37,0xff,0x4a,0x76,0xfe,0x8b,0xc6,0xff, + 0x3a,0x3a,0x3a,0x0a,0xf2,0x6f,0x7d,0x63,0xa3,0xb3,0xcb,0x32,0xb2,0xd9,0xac,0xd9, + 0xb3,0x51,0x3f,0xc0,0x6f,0x57,0x35,0xac,0x5d,0xbb,0x8e,0xbc,0x6a,0xf1,0xe2,0x25, + 0x62,0xbd,0xc1,0xc6,0x2f,0x8d,0x89,0x49,0x49,0x23,0x46,0x20,0xf7,0xd9,0xa9,0x63, + 0xa7,0x95,0xab,0x57,0xf3,0xa7,0xdf,0xfd,0x07,0x0f,0x51,0x8d,0xb5,0x5f,0xbf,0xfe, + 0xa8,0x3a,0xc6,0x8e,0xff,0x20,0xff,0xb6,0xe6,0xdf,0x40,0xe3,0x7f,0x11,0xfb,0xb3, + 0x14,0xfc,0xcb,0xf4,0xbf,0xe2,0x14,0x14,0xf0,0xbc,0x53,0x18,0xfd,0xdf,0xbd,0x7b, + 0x57,0xdc,0xd1,0x43,0x21,0xf3,0xbf,0x92,0xe1,0xbf,0x0b,0xe9,0x59,0x59,0xbd,0x30, + 0x91,0x5e,0x4d,0x45,0x8d,0x3c,0xf4,0x41,0xf9,0xb7,0x4b,0xe7,0x2e,0xd7,0x6f,0x08, + 0x71,0xcf,0x00,0xcc,0x5f,0x88,0xd4,0x6e,0x00,0x84,0x9f,0x3d,0xcb,0x6b,0xd0,0xf8, + 0xa5,0xc9,0x7f,0xcb,0x16,0x86,0x63,0x06,0x10,0x99,0x8b,0x9b,0x7b,0x4b,0xab,0x5f, + 0x19,0xd7,0xf1,0xe9,0x6f,0xee,0x1f,0xcd,0x2d,0xcd,0x00,0xf8,0xc8,0xfd,0x12,0xfd, + 0xf8,0x37,0xf7,0x23,0xef,0x7b,0xf2,0x4e,0x60,0xab,0xf4,0xf4,0xf2,0xee,0x8a,0xe9, + 0xe3,0xb0,0xe2,0x66,0xce,0x9a,0x5d,0x5a,0x21,0x6a,0x39,0x63,0xd1,0xfd,0xaf,0x40, + 0x3e,0xf1,0xf0,0x44,0x82,0x56,0x0c,0xf4,0x0d,0xa2,0x2e,0x5f,0xa6,0xe5,0xd7,0x85, + 0x9d,0x9f,0x0c,0x75,0x81,0xce,0x81,0x6a,0xc9,0xc6,0xed,0xe2,0x7f,0xd5,0xee,0xfc, + 0x2b,0x62,0xfe,0xab,0xe3,0x27,0x4e,0x02,0xd9,0x31,0x9a,0x29,0x29,0x28,0xfd,0xbe, + 0x63,0x07,0x35,0x79,0xef,0xdf,0x2d,0x27,0x4e,0x21,0x4a,0xeb,0x92,0x25,0x4b,0x45, + 0x7c,0x7d,0xb0,0xeb,0xa6,0xa4,0xa7,0x6f,0xdd,0xb6,0x8d,0x16,0x1b,0xde,0x4d,0xae, + 0xdb,0xf1,0xe3,0x27,0xf8,0xb1,0x78,0x61,0x87,0xff,0x20,0xdb,0xc0,0x14,0x5d,0xd6, + 0x3a,0x45,0xc5,0x45,0x64,0x94,0x84,0xfc,0xfb,0xcf,0xfb,0x5f,0xdd,0x14,0xc5,0xff, + 0x59,0x84,0xfc,0x57,0x49,0xc9,0xa9,0x5a,0x9a,0xda,0x8c,0x66,0x03,0xfa,0x0d,0xc8, + 0x7d,0xf1,0x82,0xbf,0xba,0xbf,0xe2,0xdb,0xfa,0x65,0xff,0xc8,0xb8,0x8d,0x76,0xf7, + 0xbf,0x92,0xf1,0xaf,0x0c,0xdf,0x0f,0xc0,0x53,0xc1,0xfb,0x42,0xd0,0x24,0x00,0x9a, + 0x1a,0x5a,0x0f,0xff,0x62,0xe6,0xe1,0x99,0x3f,0x1f,0xe1,0x5f,0x58,0x65,0xa4,0x07, + 0x2f,0x09,0xd8,0x48,0xc9,0xa5,0x0d,0x08,0x08,0x0a,0xe2,0x35,0xa8,0xad,0xaf,0x73, + 0x73,0x5f,0x4e,0x1e,0x77,0x9a,0x9a,0xf6,0x9d,0x35,0xdb,0x11,0xe0,0x38,0xc7,0xe9, + 0x17,0xd0,0x88,0x1c,0xe7,0xc0,0x1f,0x3c,0xc0,0xdf,0xe4,0xc7,0x5f,0xa0,0x71,0xeb, + 0x97,0x8b,0x16,0x2f,0x79,0x9c,0xc8,0x34,0xa1,0xf3,0x50,0x5c,0x5a,0x36,0xc7,0x69, + 0x2e,0x1a,0x57,0x28,0xd7,0x55,0xce,0xc3,0xd3,0xb3,0xb2,0xaa,0x52,0xc4,0x01,0x44, + 0xf9,0x17,0xcd,0xbf,0x11,0x17,0x17,0xaf,0x4a,0x84,0x66,0xc3,0xee,0x0d,0x9b,0xa1, + 0xaf,0xaf,0x6f,0x7c,0x42,0x42,0x71,0x69,0x71,0x6d,0x7d,0x2d,0xa8,0x63,0x5c,0x59, + 0xa2,0x15,0x8d,0x4d,0x8d,0x5b,0xb7,0x6d,0x67,0x5c,0x02,0xbc,0x79,0x08,0x0b,0xb9, + 0x6d,0x97,0xf3,0x5f,0x96,0xf8,0xdf,0xf4,0x8c,0x8c,0x5e,0x68,0xfe,0x2b,0xf1,0xcf, + 0x7f,0x19,0xfa,0x2f,0x20,0xbf,0xe0,0xcd,0x20,0xf3,0x41,0xa4,0xbf,0x77,0x77,0xf9, + 0xee,0xce,0xce,0x2e,0xb7,0xef,0xdc,0x79,0xf7,0xe1,0x3d,0x6c,0x92,0x0d,0x4d,0x0d, + 0xfc,0xc1,0x01,0x80,0xe0,0x47,0x76,0xce,0xce,0xbf,0x20,0x08,0x7d,0x28,0x2a,0xbc, + 0x77,0xff,0xfe,0xf6,0xdf,0x77,0xd8,0xda,0xd9,0x6b,0x6a,0x6a,0xb1,0x64,0x44,0xe9, + 0x6d,0xd4,0xfb,0x79,0x4e,0x36,0xff,0x5d,0xc3,0x6b,0x42,0x26,0xcc,0x0f,0x72,0xfb, + 0x0f,0x1e,0x94,0x60,0xf5,0xd1,0xf3,0x5f,0x09,0xcb,0xbf,0x21,0x56,0xfe,0x2b,0xa9, + 0xf9,0x57,0x14,0xfd,0x77,0xf7,0x9e,0x7d,0xa4,0x40,0x4b,0xda,0x9f,0x6f,0xde,0xba, + 0x4d,0x7a,0xaf,0xa9,0xa9,0xa9,0x4f,0x9c,0x34,0x99,0xbf,0xba,0xd1,0x45,0x4d,0xfb, + 0x78,0xf4,0xc4,0x09,0x41,0x07,0x4e,0x7a,0xfe,0x2b,0x49,0xfc,0xaf,0x64,0xf6,0x67, + 0x19,0xbe,0x2b,0x9e,0x66,0x67,0xf7,0xee,0x83,0x1c,0x2f,0x76,0xe0,0xfa,0x23,0x19, + 0x91,0x2e,0xc4,0x68,0xfc,0x91,0xa1,0xa1,0xd1,0xeb,0xb7,0x6f,0x84,0xfe,0x16,0xa8, + 0x6c,0x68,0x2c,0xb0,0x9f,0x9f,0x3f,0xaf,0xc1,0xe7,0xba,0x56,0xe7,0x16,0x89,0x92, + 0x67,0xa2,0x50,0x56,0x52,0xb9,0x1a,0x1d,0x4d,0xbb,0x9f,0xec,0xdc,0x5c,0x6b,0x1b, + 0x1b,0xf4,0x42,0xd0,0x4a,0xf6,0x86,0x84,0x8a,0xb2,0xee,0xc4,0xe2,0xdf,0xea,0xcf, + 0x9f,0x81,0x4a,0xd0,0x98,0xaf,0xce,0x9d,0x3a,0xeb,0x68,0xeb,0xd8,0xda,0xd9,0x2d, + 0x75,0x71,0x5e,0xb7,0x7e,0x7d,0x40,0x40,0x20,0x0f,0x3b,0x77,0xee,0x1a,0x3f,0x9e, + 0x69,0x7f,0x86,0x1e,0xc2,0x0e,0x23,0x21,0xb7,0x61,0x87,0xda,0x81,0x7f,0x59,0xf5, + 0xdf,0xef,0xe5,0x7f,0xd5,0xd2,0x1a,0x55,0xb4,0x2f,0x24,0x04,0x9d,0x21,0x30,0x25, + 0xd4,0xd5,0x7a,0x0e,0x1b,0x36,0x62,0xfe,0x82,0x85,0x6b,0xd7,0xad,0xfb,0x7d,0xc7, + 0x4e,0xfe,0xf8,0x38,0xbb,0xb8,0x90,0xed,0x59,0xf8,0xf7,0x7d,0x51,0xe1,0xfe,0x03, + 0x07,0x6c,0x6d,0xed,0x7a,0xaa,0xf7,0x24,0xd5,0x6d,0x06,0xba,0x74,0xea,0xf2,0xeb, + 0x9a,0x7f,0xd7,0xb9,0x68,0xfa,0xd2,0x04,0x7a,0x2e,0xd9,0x4c,0x49,0x51,0xf9,0xd2, + 0xe5,0xcb,0x12,0xac,0xbe,0xff,0x22,0xfe,0xbd,0x75,0x5b,0x12,0xfd,0x97,0xe4,0xdf, + 0xa8,0xcb,0x57,0xbb,0xc9,0xe3,0x09,0x01,0x24,0x83,0xb3,0xab,0xab,0x60,0x98,0x86, + 0x34,0xf9,0x27,0x65,0xfa,0xaf,0x0c,0xff,0x18,0xca,0x2b,0x2b,0x0e,0x84,0x85,0xf5, + 0xc1,0x4e,0x7e,0x79,0x18,0x6d,0x33,0xba,0xb4,0x9c,0x69,0x86,0x45,0xfd,0x9f,0x4d, + 0xfb,0xf6,0x2b,0x2c,0x12,0x9e,0xac,0xfe,0xec,0xb9,0x73,0x68,0xe0,0x06,0x3f,0x8f, + 0x5c,0x75,0x4d,0xf5,0xac,0x59,0xb3,0xdb,0x71,0x6d,0xc2,0xf2,0x67,0x37,0x8c,0xbf, + 0xcc,0xcb,0xef,0xdb,0xb7,0x3f,0xca,0xf8,0xaa,0xca,0xaa,0xa8,0x8e,0x49,0x02,0x3d, + 0xff,0x45,0xf3,0x5f,0xb5,0x70,0x1d,0x7d,0x4b,0xa6,0xcf,0x98,0x29,0x71,0x5e,0xcd, + 0xaf,0x9d,0x77,0xec,0x7c,0x30,0x0c,0xe1,0xdf,0x76,0xd1,0x7f,0x25,0xf0,0xbf,0xda, + 0x17,0x1a,0x4a,0xbb,0x44,0xc4,0xf8,0xdf,0xaf,0x8d,0xeb,0xeb,0xd6,0xac,0xdd,0x80, + 0x52,0x92,0x58,0x00,0xfe,0x25,0x43,0x8d,0xa0,0xf3,0xa8,0x4b,0x97,0x40,0x56,0x44, + 0xbd,0x97,0x49,0xc0,0xde,0xbb,0x78,0xe9,0x92,0x92,0xb2,0x7f,0xa7,0x6b,0x06,0xfe, + 0x75,0x71,0x45,0x0e,0xa9,0xd1,0x93,0x1a,0x51,0x40,0x3b,0xff,0x15,0x9e,0xff,0x4a, + 0xea,0xf8,0x23,0x96,0xf3,0x5f,0x2c,0xff,0x95,0xf2,0x95,0x6b,0xd7,0xd8,0x6f,0x09, + 0x8d,0xff,0x55,0x57,0x53,0x67,0xe4,0x9f,0x3c,0x7d,0xfa,0x34,0xd9,0x4c,0x1a,0x78, + 0x7a,0x79,0x89,0xc2,0xbf,0xa2,0xe4,0xbf,0x42,0xeb,0x2f,0xc8,0xf8,0x57,0x86,0x76, + 0x04,0x08,0xf3,0xef,0x0a,0xdf,0x47,0x5d,0xba,0x3c,0x65,0xea,0x54,0x50,0x0f,0x69, + 0xca,0x26,0x7c,0xbf,0x69,0xd3,0x66,0xd2,0x89,0x14,0xe5,0x5f,0x13,0xd3,0xbe,0xa2, + 0x54,0x19,0x3b,0x15,0x1e,0xd1,0x03,0xe3,0xdf,0x75,0xbe,0x1b,0x79,0x0d,0x3e,0xd7, + 0xd6,0x38,0x39,0xcd,0x6f,0xc7,0xb5,0xa9,0xa1,0x81,0x07,0x39,0x0a,0x22,0x3a,0xfa, + 0x16,0xe9,0x96,0xcc,0x1b,0x01,0x5d,0x1d,0xdd,0xbf,0x12,0xfe,0x62,0xaf,0x96,0x48, + 0xf3,0x7f,0xee,0x40,0xc4,0x1f,0xf1,0xf1,0x8a,0xc3,0xf1,0xf0,0xf4,0x06,0x7e,0x17, + 0xab,0x46,0x95,0x20,0xb8,0xe7,0xbf,0x47,0xd0,0xf3,0x5f,0x69,0xf9,0x57,0x4d,0x55, + 0x8d,0x35,0xfe,0x17,0x3f,0xff,0xdd,0x15,0x18,0x44,0xbb,0x84,0xc6,0xbf,0xa4,0xfd, + 0x99,0x87,0x92,0xb2,0xb2,0x80,0xc0,0x60,0x6d,0x2d,0x6d,0x09,0x72,0xf2,0xf3,0xc1, + 0xd5,0x7f,0xdb,0xf2,0x2f,0xbc,0xc4,0xb0,0xc3,0x87,0x75,0x45,0xcb,0x52,0x0e,0xef, + 0xa5,0xa7,0x5a,0x4f,0x67,0x57,0xe7,0xc2,0xe2,0xe2,0x36,0x6b,0x87,0xcb,0xbf,0x6e, + 0x64,0x7b,0xa1,0x62,0x1e,0x0d,0x34,0xfe,0x8d,0x15,0x36,0x69,0xff,0x61,0xfe,0x05, + 0xb1,0xf9,0xdc,0xb9,0xf3,0xec,0xb7,0x14,0xbc,0x27,0x04,0x75,0x9c,0x66,0xe8,0xbf, + 0x17,0x22,0xa3,0x7e,0xf8,0xa1,0x3d,0xf9,0x77,0xfd,0xfa,0x0d,0x82,0x9e,0x9f,0x34, + 0xfe,0xb5,0xb3,0xb3,0xaf,0xfa,0xf4,0x91,0xe5,0xfe,0x65,0xf6,0x67,0x19,0xbe,0x2b, + 0x60,0x16,0xa5,0x65,0x66,0xec,0x0c,0x08,0x18,0x3c,0x78,0x30,0x2d,0x27,0x24,0x1f, + 0x7a,0xba,0xfa,0xa8,0x2d,0x0b,0xb5,0x3f,0xeb,0xfc,0xa8,0xf3,0xe2,0x15,0x33,0x47, + 0x1f,0x89,0x7d,0x21,0x21,0xa8,0xe8,0xbb,0x75,0xeb,0xd7,0x54,0x12,0x75,0x0d,0x75, + 0xee,0xee,0xee,0x12,0xb3,0x12,0x09,0x03,0xfd,0x5e,0xa9,0xe9,0x42,0xea,0x96,0x36, + 0x35,0x37,0x9f,0x3f,0x1f,0x09,0xbc,0x83,0xf6,0x60,0x69,0x69,0x95,0xc6,0x1a,0xfa, + 0x24,0xba,0xff,0x95,0x20,0x1a,0x1a,0x1b,0xae,0x45,0x5f,0x9f,0x3b,0x6f,0x3e,0x2d, + 0xed,0x21,0x3b,0xb8,0xe7,0xbf,0x7f,0xa0,0xfa,0xaf,0xb4,0xfe,0x57,0x0a,0x3d,0x14, + 0xae,0xdf,0xa0,0xaa,0x72,0xb4,0xfa,0x83,0xbe,0xbe,0x1b,0x69,0xf1,0xb6,0xe2,0xd6, + 0x1f,0x6c,0x69,0x75,0xb4,0x4b,0x78,0xf2,0xc4,0xcb,0xdb,0xcb,0xb8,0x8f,0xb1,0x64, + 0x95,0x44,0x98,0xf6,0xe7,0xbf,0x5b,0x92,0x92,0x53,0xd0,0x93,0x6b,0x06,0xe0,0x5d, + 0x68,0xf4,0xd4,0x70,0x74,0x9c,0x73,0xfb,0xf6,0x5d,0x32,0xf9,0x0c,0x3c,0xa3,0xb7, + 0xcf,0x2a,0xf2,0x2a,0x50,0xd8,0x4f,0x45,0x44,0x48,0xb0,0x24,0x69,0xfe,0x57,0x67, + 0xce,0xb1,0x45,0x3d,0xb7,0xfc,0xe3,0xfe,0x57,0xb0,0x6c,0x43,0x42,0xf7,0xb3,0xdf, + 0x92,0x88,0xfe,0x57,0x37,0x6e,0xdd,0x56,0x50,0x40,0x84,0x70,0x89,0xb1,0x7b,0xcf, + 0x1e,0xc1,0xb0,0x2f,0x1a,0xff,0xc2,0x42,0x7e,0x2f,0x50,0xf9,0x91,0x84,0x2c,0xff, + 0x95,0x0c,0xdf,0x09,0xc5,0xa5,0x25,0x57,0xae,0x5d,0x75,0x72,0x9a,0xab,0xa3,0xa3, + 0x2b,0x4a,0xf1,0x1d,0xd8,0x84,0x77,0x05,0x06,0xa2,0xb3,0x0e,0xe5,0x5f,0x79,0x39, + 0xf9,0x98,0xd8,0x7b,0x42,0x6f,0x03,0xf6,0x2e,0x94,0x6b,0x0e,0x7d,0xcb,0x63,0xd3, + 0xf8,0xa5,0x71,0x93,0xbf,0x1f,0x99,0x98,0x6e,0xd8,0xd0,0x61,0xfe,0xfe,0x5b,0x00, + 0x7e,0xfe,0xfe,0x7e,0x7e,0xfe,0x5b,0xb6,0x6e,0x85,0x7f,0xb9,0xf0,0xf7,0xff,0xfa, + 0xbd,0xdf,0x96,0xd5,0xab,0x7f,0x55,0x55,0x65,0xba,0x36,0x0d,0x1c,0x60,0x56,0x80, + 0x55,0x24,0x67,0xa0,0xb6,0xbe,0x76,0xcf,0xde,0x10,0x65,0x45,0x24,0x43,0x17,0xdc, + 0xb0,0xbd,0xc3,0x18,0xce,0x9b,0x7c,0xda,0xb5,0xa2,0xe7,0x7f,0x26,0x2f,0x84,0x25, + 0xff,0x3c,0x27,0xf7,0x64,0x44,0xc4,0xca,0xd5,0xbf,0x4e,0x9e,0x3a,0x75,0xf8,0xf0, + 0xe1,0x03,0x06,0x98,0xf5,0xe9,0x6d,0xdc,0xdb,0xb0,0xb7,0xbe,0x9e,0x01,0x0f,0x20, + 0x08,0x91,0x09,0x43,0x68,0xe7,0xbf,0xd2,0xc7,0x1f,0xc1,0xf4,0x38,0x71,0xf2,0x24, + 0xed,0x9e,0xd3,0x32,0x70,0xfe,0x5d,0xb2,0xd4,0xb9,0x9e,0x92,0x66,0x4d,0xf4,0xf3, + 0xdf,0xb6,0x83,0xc3,0x35,0x17,0x73,0xf2,0x5f,0x5f,0xb9,0x76,0xcd,0x77,0xd3,0xe6, + 0x99,0x33,0x7f,0xb1,0x1e,0x35,0xca,0x6c,0xa0,0xb9,0x71,0x1f,0x13,0x18,0x1c,0x03, + 0x7d,0x03,0xfe,0xf8,0x90,0xd1,0xe2,0xbc,0xfb,0x69,0xfb,0x7e,0xeb,0x3c,0x3c,0xbd, + 0xc9,0xe4,0xd2,0x7c,0xc8,0x75,0x95,0x03,0x76,0x1e,0x3b,0x6e,0x5c,0x70,0xf0,0xde, + 0x94,0xb4,0xd4,0xea,0x9a,0x6a,0x5a,0x24,0x6f,0x60,0x50,0x30,0x79,0x39,0xcc,0xd8, + 0xcd,0x7e,0x7e,0x12,0x2c,0xcc,0x8b,0x94,0xf3,0x5f,0x98,0xe2,0xa0,0x6b,0xb3,0x5c, + 0xe8,0xb7,0x65,0x1b,0x79,0xd5,0xf7,0x3b,0xff,0x85,0xc9,0xec,0xed,0xb3,0x92,0xfd, + 0x59,0x50,0xef,0x4a,0x32,0xfe,0xe8,0x49,0x52,0x12,0x19,0x7d,0xaf,0xa5,0xa5,0xed, + 0xb3,0x72,0x15,0xac,0xe8,0xcd,0x9b,0xfd,0x5a,0x97,0x73,0x9b,0xd5,0x0d,0xeb,0xdd, + 0xdf,0x9f,0xbb,0xe4,0xad,0xac,0x90,0x74,0x67,0x51,0x57,0xae,0x08,0xf6,0x4f,0xe3, + 0x5f,0xc3,0x5e,0x86,0xe9,0x99,0x6c,0x82,0xf4,0xc7,0xea,0x6a,0x6d,0x2d,0xa6,0x63, + 0x36,0xd7,0xfe,0xec,0xe3,0x23,0xcb,0x7f,0x25,0x83,0x64,0x68,0x68,0x6a,0x78,0x14, + 0x17,0x37,0x7e,0xc2,0x44,0x65,0x15,0xe1,0x35,0x55,0xbf,0xed,0xed,0x5d,0xe6,0x2d, + 0x58,0x58,0x5e,0x59,0x81,0x76,0x48,0xcb,0xff,0xbc,0x7d,0x57,0x00,0xbb,0x9d,0x16, + 0x60,0x87,0xa5,0x4a,0x00,0x0a,0xb8,0x16,0xfd,0x35,0xd1,0x74,0x6b,0x2d,0xa1,0x13, + 0xf2,0x84,0x6e,0xbe,0x70,0xe1,0xbf,0xd8,0x7b,0x6e,0x6e,0x69,0x79,0x95,0xc7,0x21, + 0xcb,0x77,0xda,0xda,0xdb,0x55,0x54,0xb1,0x19,0x9d,0xf8,0x00,0x2a,0x5c,0xe1,0xe1, + 0x81,0x46,0x24,0x75,0xe9,0xdc,0x75,0xa9,0x8b,0x6b,0xe5,0xc7,0x2a,0xfc,0xa7,0x29, + 0xf5,0x8f,0x3a,0xd0,0xed,0xcf,0xe8,0xfd,0x7f,0xfa,0x5c,0x5d,0x54,0x52,0x94,0xc7, + 0xc9,0x7f,0x96,0x93,0x9d,0xf5,0xec,0x69,0x72,0x6a,0x2a,0x10,0x01,0x20,0x31,0x39, + 0xd9,0x0b,0x8b,0x3f,0x3a,0x72,0x14,0xb3,0x3f,0x8b,0xc3,0xbf,0x68,0xfd,0x41,0xd8, + 0x69,0x7d,0xbf,0x1d,0x07,0x90,0x78,0x92,0x9c,0xac,0xab,0x83,0xd4,0x49,0x1f,0x33, + 0x66,0x4c,0x45,0x15,0x3e,0x61,0x24,0xe3,0x5f,0xc6,0xe0,0xd4,0xd4,0xd5,0x16,0x97, + 0x95,0xe6,0xbf,0x2e,0xc8,0xce,0xcd,0x81,0xc1,0x49,0xcd,0xe0,0x8e,0x0c,0x6f,0x88, + 0x0e,0x84,0x1d,0x22,0x3b,0x77,0x5b,0xbe,0x42,0xb0,0x87,0xe2,0x92,0x32,0x0b,0x0b, + 0x2b,0x74,0xde,0x02,0x75,0x5a,0x58,0x5a,0x05,0x04,0x05,0x43,0x6f,0x30,0xe7,0xc9, + 0x7a,0xb2,0x0c,0x5c,0xbc,0x74,0x19,0x35,0x8c,0xdb,0x39,0x8c,0x69,0x64,0x65,0x4c, + 0x14,0xb4,0xfc,0x57,0xb3,0x66,0xcd,0x66,0x37,0x96,0xae,0x5c,0x89,0xa8,0xe1,0xed, + 0x93,0x7f,0x23,0x36,0x96,0xac,0x3f,0x08,0xb0,0x19,0x6d,0xcb,0xfe,0x80,0xbf,0xad, + 0xdd,0x80,0x96,0x21,0x63,0xf0,0xef,0x2b,0x0e,0x07,0x84,0x4c,0x46,0x33,0x63,0x63, + 0xd3,0x9c,0x17,0xb9,0x2c,0xd9,0x41,0xe1,0xbd,0xc0,0xff,0x2e,0x58,0xc8,0x0c,0xbe, + 0x00,0x99,0xea,0x71,0x72,0x9b,0x32,0xdf,0x34,0xfe,0x55,0x52,0x54,0x8e,0xbc,0x78, + 0x91,0xe5,0xfe,0x8b,0x4b,0xcb,0xc8,0xb2,0x71,0xb2,0xfc,0x57,0x32,0x48,0x06,0xe0, + 0x85,0x97,0x1c,0x0e,0x28,0x02,0x62,0x79,0x1b,0x2a,0xf6,0x50,0xf4,0xdd,0xbc,0xb1, + 0xbc,0x92,0x1a,0x7a,0x43,0xcb,0xbf,0x31,0xd2,0x7a,0xd4,0x87,0xe2,0x22,0x96,0xfb, + 0x79,0x99,0x97,0xa7,0xa4,0xc8,0x2c,0x22,0xcf,0x5d,0xa1,0xaa,0x6a,0x82,0x46,0xb3, + 0xe4,0xd4,0x34,0xe0,0x0b,0xe6,0xf2,0x34,0x31,0x41,0x53,0xb2,0x0b,0xe2,0x4e,0xcc, + 0x3d,0x39,0x82,0x04,0x3d,0xbd,0x7d,0x84,0x4a,0x05,0x7c,0xc0,0x53,0xbb,0x2e,0x73, + 0x43,0x35,0x74,0xd8,0x72,0x7f,0x5b,0xbb,0x0e,0xcd,0x3e,0x4d,0x3b,0xff,0xa5,0xf9, + 0x5f,0x89,0x8b,0x86,0xa6,0xa6,0x95,0xab,0x57,0x33,0x3a,0x87,0x1d,0xf2,0xfc,0x85, + 0x0b,0x64,0x63,0xe9,0xcf,0x7f,0x01,0xf6,0x63,0x1c,0x68,0xa3,0xfd,0xf0,0xe1,0x43, + 0x54,0xdf,0x04,0xe5,0x31,0x25,0x2d,0x0d,0xbd,0xa4,0xa2,0xaa,0x12,0xad,0xa6,0x31, + 0xc7,0x71,0x4e,0xb5,0xb0,0x6c,0xde,0xa2,0xe0,0x42,0x64,0x24,0xd9,0xf9,0xea,0x35, + 0xbf,0x0a,0xb6,0x79,0x9e,0x93,0x8d,0x66,0x78,0x03,0x65,0x3f,0x78,0xcf,0x5e,0xa1, + 0x49,0xc5,0x05,0xf1,0x2c,0x3b,0x5b,0x1b,0x2b,0x59,0x0b,0xab,0x2c,0x29,0x39,0x45, + 0xdc,0x9b,0xa7,0xf9,0x3f,0x1b,0xc0,0x78,0xa6,0xa7,0xd2,0xae,0xaa,0xad,0xab,0x9f, + 0x39,0x8b,0x99,0x42,0xaa,0x43,0x6b,0xa9,0xa6,0x67,0xd9,0xc8,0x94,0x93,0xfe,0xfc, + 0x97,0xf7,0x80,0x59,0xac,0xf3,0xd9,0x71,0xae,0x13,0x79,0x95,0xa6,0x86,0xe6,0xf3, + 0xec,0x36,0xd9,0x6c,0x40,0x8e,0xfd,0x85,0xc8,0x7f,0xa5,0xd0,0x43,0x21,0xea,0x92, + 0x10,0x07,0xf2,0xaa,0x8f,0x55,0x16,0x16,0x96,0x8c,0x0b,0xb5,0xb4,0xb5,0x2b,0xaa, + 0xda,0x08,0xc6,0x34,0xfe,0xed,0xd8,0xa1,0xe3,0xc2,0x45,0x6c,0x62,0x7c,0xfa,0xd3, + 0x4c,0xf2,0x74,0xac,0x53,0xc7,0x4e,0xab,0x56,0xad,0x92,0xf1,0xaf,0x0c,0x62,0x01, + 0xc8,0x37,0xf3,0x69,0xd6,0x98,0xb1,0xe3,0x45,0x77,0x35,0x94,0xeb,0x2a,0x67,0x65, + 0x35,0x04,0xd4,0x4f,0xf6,0xed,0x88,0x96,0xff,0x59,0x45,0x59,0xf5,0x64,0xc4,0x29, + 0x9a,0xd5,0xae,0xbe,0xb1,0x61,0x57,0x60,0x20,0xea,0xeb,0x65,0x61,0x39,0x44,0x30, + 0xb1,0x33,0x90,0x20,0x99,0x07,0x18,0x36,0x84,0xfb,0x0f,0x1e,0xb2,0x24,0xf7,0x6b, + 0x68,0x6a,0x5c,0x43,0xe4,0x41,0x02,0x26,0x8d,0xf8,0x96,0xd9,0x43,0x44,0x7c,0x28, + 0x2a,0x1c,0x65,0x6d,0x83,0xb2,0x92,0x9a,0xaa,0xda,0x9e,0xbd,0xfb,0xc8,0x1c,0x5f, + 0x34,0xfe,0x65,0xb1,0x3f,0xc3,0x83,0xd4,0x36,0x08,0x11,0x27,0xf8,0x00,0xfe,0x9a, + 0x3a,0x6d,0x1a,0xa3,0x73,0x90,0x64,0xee,0xc5,0xc6,0x92,0x8d,0xdb,0x85,0x7f,0x35, + 0x35,0xb5,0x92,0x52,0xf1,0xcd,0xff,0xf4,0x99,0x33,0xa8,0x07,0x7b,0xb7,0x6e,0xdd, + 0xf6,0x86,0x86,0xa0,0x97,0x80,0xbe,0xa3,0xaf,0x6f,0x40,0x5e,0xe2,0xe2,0xba,0xac, + 0x46,0xa0,0x44,0xaf,0x20,0xea,0x1a,0xea,0x44,0x94,0x9a,0x1a,0x9b,0x1a,0x37,0xfb, + 0xf9,0x93,0x23,0x1f,0x14,0x1c,0x2c,0xd8,0x2c,0x2d,0x23,0x53,0x45,0x19,0xb1,0xff, + 0x0c,0xb2,0xb0,0xac,0xa9,0x13,0x29,0x4d,0xba,0xe0,0xeb,0x80,0x65,0x85,0x2e,0x01, + 0x67,0x17,0xd7,0xf2,0x4a,0x6a,0xaa,0x2e,0x14,0x34,0xfe,0x05,0xad,0x7c,0x93,0xbf, + 0x3f,0x6d,0x10,0x0a,0xde,0xbc,0x1e,0x34,0x08,0x29,0xa4,0xc5,0x3d,0x6d,0xc1,0xc2, + 0x00,0xa5,0xb7,0x3f,0xf3,0x00,0x43,0x5d,0xdf,0x80,0x33,0x51,0x75,0x4d,0x1d,0x9a, + 0xdd,0xae,0xb7,0x51,0xef,0xd7,0x6f,0xda,0xdc,0x52,0x53,0xf3,0x97,0xc0,0xdd,0x4c, + 0x1b,0x3e,0x37,0x81,0xc9,0x32,0x37,0x5a,0xe7,0x3c,0xfc,0x15,0x17,0xa7,0xae,0xd6, + 0x93,0x71,0xe1,0xb8,0xf1,0x13,0x18,0xdb,0x02,0x8d,0x7f,0x01,0xda,0xda,0xda,0x9c, + 0x7c,0x0e,0xda,0x39,0x74,0x72,0xf2,0xd4,0x29,0xf2,0x92,0xae,0x9d,0xbb,0x6e,0xdb, + 0xbe,0x5d,0x02,0xcb,0x86,0x0c,0xff,0xcb,0x28,0x78,0xfd,0x86,0x0c,0x1a,0xa5,0x01, + 0xe6,0x18,0x68,0x28,0x41,0x41,0xbb,0x5f,0xbf,0x7d,0xcb,0x62,0x02,0xe2,0x81,0xa5, + 0xfe,0x60,0xbf,0x7e,0xfd,0x05,0x33,0x39,0x0b,0xe2,0x71,0xe2,0x13,0x13,0xd3,0xbe, + 0xe4,0x25,0x40,0x91,0x6e,0x6e,0xee,0x0c,0x6d,0x6b,0xe3,0x66,0x7f,0x52,0x09,0x9d, + 0x3a,0x75,0xda,0x87,0x42,0x6a,0x88,0x53,0x6a,0x5a,0x9a,0x29,0xd1,0xbf,0x9e,0xbe, + 0x5e,0xae,0x08,0x5e,0x61,0x0c,0xa4,0x65,0x64,0x0c,0x1d,0x3a,0x1c,0x7d,0x40,0x65, + 0x25,0xe5,0x1b,0xb7,0x6e,0x33,0x29,0xf8,0xef,0x96,0x63,0x98,0xfd,0x99,0xc5,0xff, + 0x0a,0xb6,0x08,0xd8,0x82,0x92,0x92,0x93,0x18,0x85,0x9f,0x50,0x3c,0x49,0x4a,0x24, + 0xf9,0x4b,0x5f,0xcf,0x00,0xad,0xda,0x20,0xbd,0xff,0x15,0xf7,0xce,0x3b,0x75,0x59, + 0xbe,0x7c,0x05,0x49,0x8e,0xcd,0x2d,0x2d,0xf0,0xb2,0x68,0xde,0x62,0x66,0x66,0xe6, + 0xa5,0xe5,0xcc,0x02,0x19,0x5f,0x5a,0x9a,0xcf,0x9d,0x3f,0x8f,0x3a,0xbd,0xaf,0xf7, + 0xf5,0x45,0x1f,0x1f,0x86,0xf7,0xf8,0x89,0x93,0x57,0xaf,0x45,0x0b,0x16,0x59,0xa6, + 0x01,0xf6,0x76,0xeb,0x91,0xcc,0xe4,0xd2,0xc0,0x68,0xc0,0x6b,0x82,0xcd,0xd2,0x33, + 0x33,0x51,0xff,0x3a,0x6b,0x1b,0x5b,0x5a,0xda,0x31,0x1a,0x80,0x3e,0xf6,0xec,0x0b, + 0x41,0x6b,0x67,0x83,0x64,0xb2,0x6b,0x77,0x90,0x28,0xef,0x94,0x0f,0x9a,0xff,0x55, + 0x87,0x56,0x07,0xc8,0x84,0xc7,0x8f,0x51,0x99,0x33,0x3c,0x22,0x02,0x35,0x25,0xd9, + 0xdb,0x3b,0xa0,0x56,0x6b,0xba,0xfe,0x8b,0xd6,0x5f,0x88,0xa5,0x09,0xed,0xba,0x3a, + 0xba,0xf7,0xee,0xc7,0x92,0x97,0xc0,0x4d,0xde,0xbc,0x7d,0x1b,0xf5,0x94,0x1b,0x3e, + 0x7c,0x04,0x29,0x93,0x3c,0xcb,0x7d,0x4e,0x5a,0xdd,0x35,0x7a,0x6a,0xdc,0x7f,0x10, + 0x4b,0x93,0xb1,0x3f,0x55,0x7f,0x22,0x03,0xe7,0xe1,0x2d,0x90,0x8e,0xf7,0x2c,0xfc, + 0x0b,0x58,0xe6,0xe6,0x5e,0x5e,0x81,0x1c,0x94,0x94,0x95,0x97,0x4d,0x9f,0x3e,0x83, + 0x6c,0x4f,0x56,0x9f,0x94,0x41,0x06,0x76,0x80,0xd8,0xec,0xbe,0x7c,0x85,0x50,0xcd, + 0x17,0x64,0x6c,0x3d,0x5d,0xbd,0x29,0x53,0xa7,0x9d,0x3b,0x7f,0x01,0xf8,0x5a,0xc4, + 0x7d,0x63,0x3e,0xbd,0xfe,0x20,0x08,0xb1,0x76,0xf6,0x0e,0x8f,0xe2,0xe2,0x04,0xcd, + 0x35,0x0d,0x4d,0x0d,0x4f,0x92,0x9e,0xd8,0x8c,0xb6,0x45,0xf7,0x6d,0x6e,0x5d,0x6f, + 0x22,0x70,0xf2,0x49,0x52,0x92,0x91,0x21,0x33,0x25,0x88,0xdc,0x0f,0xf2,0x40,0x0a, + 0xef,0x0b,0x0b,0x19,0x6b,0x01,0x1e,0xf6,0xcd,0xbb,0xb7,0xe3,0x27,0x4c,0x64,0x78, + 0x6d,0xc1,0xcf,0x2d,0x59,0xb2,0x94,0x51,0x04,0x0a,0x14,0xab,0x92,0xb2,0x52,0x50, + 0xb7,0xf9,0x60,0x7c,0xe4,0x21,0xf2,0x62,0x14,0xe9,0x09,0xc9,0xc3,0x80,0x7e,0x03, + 0x92,0x92,0x93,0x05,0xfb,0xe4,0xe6,0xdf,0xc0,0xfc,0xaf,0x3a,0xd0,0xcf,0x7f,0x4b, + 0xcb,0xcb,0x40,0x6e,0xd7,0xd3,0xd1,0xf3,0xf2,0xf2,0x4e,0x4a,0x4b,0xfa,0xf4,0xf9, + 0x13,0xba,0xc0,0xe1,0xcb,0xfc,0xd7,0x05,0x20,0x78,0x90,0x43,0x37,0xda,0xd6,0xb6, + 0xa8,0x04,0xb1,0xf6,0x4b,0xef,0x7f,0xc5,0x83,0x92,0x82,0x52,0x48,0x68,0xa8,0xe0, + 0x91,0x37,0x0c,0x5d,0xec,0x83,0x58,0x35,0x55,0x75,0xda,0xdb,0x87,0x9b,0x74,0x75, + 0x73,0xe3,0x14,0x14,0xf0,0x9f,0x05,0xa8,0xea,0x79,0x76,0xb6,0xf5,0xc8,0x51,0xa8, + 0xdd,0x23,0x3c,0x1c,0x77,0x18,0x6e,0x68,0x6a,0xf4,0xf6,0xf1,0x51,0x53,0x51,0x9b, + 0x3b,0x77,0xde,0x83,0x87,0x0f,0xca,0x2a,0xca,0x69,0xbb,0x5f,0x69,0x45,0xf9,0x9a, + 0x75,0xbf,0xc9,0xcb,0x31,0x47,0xde,0xd0,0xd0,0x28,0xbd,0xad,0xcb,0x3a,0x08,0x96, + 0x86,0x58,0x0d,0x0b,0x45,0x05,0xc5,0xf8,0xc4,0x44,0xb4,0x52,0x03,0xfc,0x28,0xa8, + 0xc6,0x45,0x25,0xc5,0xe4,0xff,0xbe,0xe2,0xe4,0xa3,0x95,0x82,0xb9,0xf3,0x59,0x45, + 0x75,0xe3,0xa6,0xcd,0xf9,0x05,0xf9,0x0d,0x4d,0x8d,0x8c,0xde,0x40,0x71,0x7e,0x99, + 0xf7,0x8a,0x21,0xbc,0xd1,0xe2,0x8f,0x78,0xab,0x69,0x88,0xd5,0xd0,0xd8,0x07,0x0f, + 0xf8,0xa5,0x1f,0x5a,0x5a,0x1d,0x14,0x33,0x9f,0x65,0x0e,0x1c,0x68,0x86,0x0e,0xa9, + 0x87,0xa7,0x37,0xea,0xb5,0x25,0x76,0xfd,0x41,0x4a,0x70,0x3a,0xfc,0xa8,0xb9,0xd9, + 0xa0,0x3b,0x31,0x31,0x82,0x46,0x83,0xc6,0xe6,0xc6,0x94,0xb4,0x54,0x34,0xc5,0x37, + 0xb7,0x74,0x94,0x40,0xe9,0x0a,0xc1,0x35,0x3b,0x7d,0xc6,0x2c,0xc6,0xac,0x86,0xc6, + 0x56,0x96,0x43,0xe2,0x1f,0x27,0x90,0x1b,0x11,0x2c,0x90,0x7d,0x21,0xa1,0x8a,0x3d, + 0x14,0x19,0xfd,0x9b,0x98,0x98,0x64,0x64,0x31,0x5d,0xaa,0xd8,0xf9,0xb7,0x47,0xf7, + 0x1e,0x9e,0xde,0x3e,0x6f,0xdf,0xbf,0x13,0x9c,0x54,0xd5,0x35,0xd5,0x3b,0x03,0x02, + 0x50,0xc3,0x4e,0x4f,0xf5,0x9e,0x89,0x49,0x78,0x02,0x3d,0x19,0x64,0x40,0xf1,0xe2, + 0xe5,0x4b,0x5a,0x34,0x0d,0x7f,0xab,0x34,0x36,0x36,0x5d,0xb3,0x76,0x43,0x7c,0x42, + 0x02,0xcd,0xad,0x88,0x06,0x9a,0xfd,0x99,0xbf,0x88,0x4c,0xfa,0x98,0xac,0xdb,0xb0, + 0xe1,0x56,0x4c,0x0c,0x28,0x1d,0x77,0x62,0xef,0xfa,0x6d,0xd9,0xd2,0xb7,0x6f,0x5f, + 0x9a,0xd2,0x34,0x72,0xa4,0x35,0xe9,0xe8,0xf5,0xb9,0xb6,0x66,0xe5,0xaa,0x5f,0xc9, + 0xc6,0x20,0xee,0x4e,0x9e,0x32,0x2d,0xfa,0xc6,0xcd,0x0f,0xc5,0xc5,0xf5,0x8d,0x0d, + 0x75,0x0d,0xf5,0xa5,0xe5,0xe5,0x57,0xae,0x5e,0x03,0x2e,0xc3,0x1c,0x3f,0x54,0x6f, + 0xdc,0xba,0xc5,0xd8,0xba,0x63,0xee,0xdd,0x1b,0x3f,0x7e,0xc2,0x68,0x1b,0x5b,0xd0, + 0x14,0x78,0xff,0xda,0xda,0xda,0xf3,0xfe,0xb0,0xb7,0x73,0xb0,0xb3,0xb5,0x07,0xd8, + 0xdb,0x8f,0x19,0x65,0x6d,0x03,0xfb,0x3f,0x7a,0xc3,0xad,0x89,0x1f,0xdb,0x54,0x1d, + 0xa5,0xe5,0xbf,0xea,0x40,0xe7,0x5f,0xa0,0x78,0xf8,0x51,0xde,0x8b,0x30,0xec,0x65, + 0xb8,0x68,0xd1,0xbf,0x80,0x8c,0x5e,0x71,0x38,0xb0,0x75,0xc0,0x73,0xf1,0x00,0x94, + 0x11,0x79,0xf1,0xd2,0x98,0x31,0x63,0xd1,0x32,0xe5,0x6b,0xd7,0xad,0x43,0xcb,0x3a, + 0xb7,0x17,0xff,0x76,0x68,0x3d,0x50,0x98,0x3f,0x7f,0xc1,0xa5,0xe8,0xab,0xa9,0x19, + 0xe9,0x0f,0xe3,0xe2,0xfc,0xb7,0x6e,0x33,0x31,0x31,0x65,0x79,0xf5,0xbc,0x17,0x34, + 0x76,0xec,0x38,0xd0,0x17,0x12,0x93,0x93,0x93,0x52,0x52,0xc2,0x0e,0xff,0x61,0x63, + 0x33,0x1a,0xf5,0x3a,0x06,0xe1,0x90,0x16,0xd5,0x05,0xaf,0x75,0x85,0x87,0x27,0x6f, + 0x2e,0x69,0x69,0x68,0x81,0x56,0xb2,0x3f,0xec,0x50,0xd6,0xb3,0x67,0x30,0x51,0xe1, + 0x91,0x81,0xd7,0x60,0x70,0x3e,0x94,0x7c,0xb8,0xff,0xe0,0xe1,0xbc,0xf9,0x0b,0x15, + 0x7a,0x20,0x7b,0xe6,0xc4,0x89,0x13,0xcb,0xda,0xa6,0xef,0xfe,0x58,0xfd,0x91,0x5b, + 0x64,0x13,0xe3,0xac,0xa1,0x43,0x86,0x9d,0x3e,0x73,0xa6,0xa4,0xb4,0x04,0x7e,0x17, + 0x7a,0xae,0xad,0xaf,0x83,0x09,0xf9,0x2c,0xfb,0xf9,0xb1,0x53,0xa7,0x5c,0x5c,0x5d, + 0x5d,0x97,0x2d,0x2b,0xad,0x28,0x65,0xdc,0x61,0x73,0x4b,0xf3,0xf6,0x1d,0x3b,0x48, + 0x67,0x03,0x1e,0x60,0x26,0x80,0xd2,0xe7,0xbf,0x75,0xeb,0xdd,0x98,0x98,0xcc,0xa7, + 0x4f,0xe1,0x31,0x6f,0xdd,0x8d,0x09,0x3d,0x70,0x70,0xfa,0x8c,0x99,0x13,0x26,0x4e, + 0x2a,0x6d,0x5b,0x4b,0x82,0x85,0x7f,0x79,0x30,0xec,0x65,0xe4,0xe9,0xe5,0x7d,0xfd, + 0xe6,0x4d,0x58,0x4d,0x8f,0x12,0x12,0x02,0x02,0x83,0x2c,0x29,0x8e,0x64,0xa0,0x7e, + 0x5e,0xb8,0x88,0xb8,0x04,0xb4,0x88,0x5b,0x7f,0x90,0xe2,0x7f,0xc5,0x5f,0xe0,0xa0, + 0x05,0xfb,0xac,0x5c,0x75,0xf9,0x6a,0x74,0x7a,0x56,0x56,0xfc,0xe3,0xc7,0x7b,0x43, + 0x43,0x06,0x0f,0xfe,0x09,0xcd,0x24,0x06,0xca,0xe3,0xd1,0x63,0xc7,0xbe,0x60,0x81, + 0x69,0xd1,0x37,0x6f,0x69,0x68,0x68,0x92,0x97,0xf4,0xef,0xdf,0x7f,0xd7,0xee,0xa0, + 0xbc,0xfc,0xfc,0x9a,0xba,0x3a,0x78,0x1d,0xb0,0x15,0xc0,0x18,0xae,0x58,0xe1,0xa1, + 0xae,0x86,0x08,0x7e,0xcb,0x3d,0xbd,0xeb,0xea,0x99,0x26,0x6b,0x76,0xfe,0xe5,0xcd, + 0x52,0x3b,0x3b,0xfb,0xfd,0x07,0x0f,0x3e,0x8a,0x8f,0x87,0x51,0xbd,0x16,0x1d,0xed, + 0xe2,0xe2,0x4a,0xdb,0x30,0xad,0x86,0x0c,0xa9,0x10,0xf3,0x4c,0x41,0x86,0xff,0x65, + 0x80,0x80,0xbd,0x63,0xe7,0x4e,0xda,0xdc,0x6b,0x35,0x35,0x5b,0x46,0x9c,0x39,0x2b, + 0x98,0xd5,0x47,0x2c,0xa0,0xf6,0x67,0xd8,0x4e,0xc9,0xcd,0x8d,0x25,0xdc,0x83,0x07, + 0x98,0xf3,0x17,0x29,0x4e,0x17,0x85,0xc5,0x45,0xe6,0xe6,0x16,0xe8,0x86,0x09,0x94, + 0x01,0x8b,0x71,0xd0,0xa0,0xc1,0x66,0x66,0xe6,0x9a,0x9a,0x5a,0x78,0x9b,0x4e,0x9d, + 0x61,0xcd,0x92,0x0c,0x75,0xfc,0x64,0xb8,0x94,0xb9,0x77,0x80,0x31,0x0f,0x10,0xb9, + 0x16,0x8f,0x1c,0x3d,0x4a,0x6e,0x59,0x68,0xfe,0x49,0x1e,0x40,0x8b,0x1f,0x31,0x9c, + 0x69,0x35,0x95,0x97,0xef,0xa6,0xa3,0xab,0x37,0xd0,0xcc,0x7c,0xf0,0x4f,0x16,0x7d, + 0xfa,0x18,0xc3,0xe0,0xd0,0xd2,0x34,0xa9,0x28,0xab,0x64,0xe7,0xe4,0xa0,0x3d,0x4b, + 0x7f,0xfe,0xdb,0xa5,0x73,0x17,0x86,0x30,0xc3,0xfe,0x1e,0x79,0x99,0x21,0x99,0x25, + 0x33,0x3a,0x74,0x64,0x0f,0x6a,0x1e,0x3e,0xe2,0xe7,0x3a,0xca,0x61,0x1f,0xe8,0x56, + 0x8b,0x9d,0x99,0x29,0x25,0x61,0x78,0xb5,0x34,0xb5,0xfa,0x0f,0x18,0x08,0x5b,0xbd, + 0x89,0x69,0x5f,0x98,0x00,0x34,0xc9,0x01,0xee,0x24,0x32,0xea,0x12,0x69,0x24,0x39, + 0x7d,0xf6,0x1c,0x68,0xbb,0xb4,0x47,0x00,0x35,0x07,0x94,0xca,0x9f,0x2c,0x2c,0x8d, + 0x4d,0x4c,0x35,0x34,0xb5,0xf8,0xa6,0xd4,0x9f,0x2c,0xac,0xd0,0x13,0xd5,0xd2,0xb2, + 0x52,0x47,0xc7,0x39,0x42,0x67,0x0b,0x63,0xe8,0x74,0x7e,0xd4,0xc9,0xcb,0xcf,0x13, + 0xec,0x87,0x76,0xfe,0x4b,0x8e,0x9e,0xd0,0xd5,0x64,0x69,0x39,0xe4,0x43,0x21,0xee, + 0x00,0xd9,0x2e,0xf1,0x47,0x12,0x2c,0xf0,0x01,0x03,0x06,0xbe,0x7d,0xff,0x1e,0xbd, + 0xa5,0xfa,0xc6,0x7a,0xdf,0x4d,0x7e,0xb4,0x1e,0x14,0x15,0x95,0x60,0x09,0x0c,0x1a, + 0xfc,0x93,0x41,0xaf,0x5e,0xb4,0x64,0x1d,0xfd,0xfb,0x0f,0xcc,0x79,0xf1,0x82,0xec, + 0x19,0xf8,0x77,0xc2,0xa4,0x89,0xa2,0x0c,0xa9,0xd0,0x47,0x80,0xdd,0x72,0x57,0x40, + 0x60,0xfb,0xee,0xcf,0x32,0xfc,0xff,0x06,0xa8,0x09,0x33,0x67,0x20,0xbe,0x91,0xbc, + 0xe9,0xe4,0xbc,0xcc,0xed,0x79,0x4e,0x8e,0x34,0xc7,0x19,0x64,0xfd,0x85,0x4e,0x1d, + 0x3b,0xdb,0x3b,0x38,0x18,0x60,0x3e,0x36,0x6c,0x5b,0x53,0xc7,0xce,0x5e,0xde,0x3e, + 0x95,0x55,0x54,0xed,0xfb,0x4a,0x74,0x34,0x08,0xff,0x12,0xe4,0x82,0x86,0x4b,0x46, + 0x8d,0xb2,0x79,0x8e,0x31,0x54,0x78,0x44,0x84,0x28,0xe1,0xcf,0x2c,0x00,0x39,0x9f, + 0x91,0xf8,0x11,0x06,0xf3,0x8f,0xa3,0x47,0x45,0xcc,0xff,0xcc,0xc3,0x9b,0xf7,0xef, + 0xac,0xac,0x86,0x49,0x76,0x03,0x20,0xbd,0xaf,0xf0,0xf0,0xa2,0x79,0xe6,0x48,0xcf, + 0xbf,0xc3,0x46,0x8c,0x30,0x37,0x33,0x17,0x7d,0xd8,0x55,0x95,0x55,0x41,0xb9,0xb3, + 0xb6,0xb6,0x11,0x3d,0x8b,0x48,0x37,0xf9,0xee,0xbb,0x83,0xf7,0xd0,0xde,0x7b,0x75, + 0xcd,0xe7,0x79,0x0b,0x24,0xcc,0x81,0x06,0xf7,0x60,0x67,0x3f,0x06,0x3d,0x03,0x2d, + 0xab,0x28,0x9f,0x32,0x05,0xb1,0xe4,0xb3,0xc3,0xd4,0xd8,0x34,0xf7,0x25,0xb2,0xc9, + 0xc3,0x4b,0x7f,0x9e,0xf3,0x62,0xe0,0x40,0x73,0xb1,0x3a,0x54,0x53,0x51,0x7b,0xd2, + 0xd6,0x98,0x49,0xe3,0xdf,0xb1,0x63,0xc7,0xf5,0xe8,0x2e,0x46,0x12,0x4e,0xe8,0x24, + 0x34,0x74,0x3f,0xed,0x08,0x49,0x7a,0xff,0x67,0x3d,0x3d,0xfd,0x61,0xc3,0x86,0x8b, + 0xb5,0x18,0x41,0x64,0xfa,0x7d,0xe7,0x2e,0x16,0x3f,0xba,0x77,0x1f,0xde,0x4f,0x9e, + 0x32,0x55,0xb2,0x2c,0x67,0xea,0xaa,0xea,0xa7,0xc2,0xc3,0xd1,0xe7,0xe5,0xf2,0xef, + 0x44,0x84,0x7f,0x1d,0xc6,0x8e,0x23,0xdd,0xb7,0xd8,0x31,0x64,0xc8,0xd0,0xec,0x5c, + 0x5c,0xd0,0x95,0x41,0x06,0x14,0x6f,0xde,0xbd,0x45,0xa3,0xd4,0x61,0xa3,0x98,0x34, + 0x69,0x72,0x51,0x49,0xb1,0x94,0xfd,0x93,0xf1,0x47,0x20,0x43,0xae,0x5d,0xbf,0xfe, + 0xc8,0xb1,0xa3,0x5a,0x58,0x64,0x0a,0x0a,0x90,0x04,0x26,0x4c,0x9c,0xc4,0x52,0xd7, + 0xb5,0xa5,0x55,0x91,0xbf,0x7c,0xf9,0x0a,0x37,0x5b,0xaf,0x38,0xab,0x1e,0x1e,0xd3, + 0xdc,0x7c,0x50,0x46,0x66,0x26,0x2a,0x63,0x9c,0x3c,0x19,0x2e,0x4d,0x56,0x43,0x5e, + 0xff,0x61,0x87,0xdb,0xe8,0xbf,0x34,0xfe,0x65,0xf1,0xbf,0xe2,0xbc,0xce,0x37,0x37, + 0x47,0xfc,0x57,0x85,0xff,0x7a,0xc7,0x4e,0x33,0xa6,0xcf,0x78,0xf7,0x9e,0x9a,0xc6, + 0x47,0x7a,0xff,0xab,0xa5,0xae,0xce,0xd1,0x37,0x6e,0x18,0x19,0xf5,0x16,0x65,0xd8, + 0xe1,0x3d,0xba,0x2f,0xf7,0xa8,0xad,0xaf,0x7d,0x14,0x17,0x07,0x64,0x24,0xe2,0x53, + 0x4c,0x9a,0x34,0xe5,0x43,0x11,0x35,0x54,0x0d,0xf6,0x4f,0x51,0x54,0x4b,0x14,0xa0, + 0x03,0x26,0xa5,0x50,0x83,0x80,0xd2,0x33,0xb3,0x46,0xdb,0x8c,0x16,0xab,0x43,0x5d, + 0x5d,0xfd,0x74,0x7a,0xf6,0xb3,0xa4,0xe4,0x34,0x5b,0x3b,0x7b,0xa1,0x45,0x1c,0xf8, + 0x50,0xec,0xa1,0x78,0xfd,0x66,0x9b,0x34,0x95,0x34,0xff,0xab,0xcb,0x57,0xa3,0x57, + 0x78,0x7a,0x88,0x68,0xab,0x81,0x97,0xe8,0xe8,0x34,0xa7,0xea,0x13,0x55,0x94,0x95, + 0x5e,0xff,0x1d,0x3e,0x7c,0xc4,0x9f,0x71,0xf1,0x5c,0x3b,0xb3,0xc8,0xf2,0x86,0xe3, + 0x1c,0x27,0x96,0xb7,0xcc,0x43,0x5e,0x1e,0x07,0x26,0x83,0xb8,0xb9,0xd0,0x35,0x7a, + 0x6a,0x04,0xef,0xd9,0x4b,0x13,0x36,0x60,0xfe,0x8c,0x9f,0x80,0xf0,0xef,0xe1,0xa3, + 0x47,0x82,0x82,0xf7,0xca,0xcb,0xe3,0xa7,0x06,0x24,0x94,0x14,0x94,0xaf,0x5f,0xbf, + 0x2e,0x7a,0xf4,0xa2,0x0c,0x32,0x00,0xf2,0xf2,0x39,0x66,0xd8,0x4e,0xd8,0x5d,0xbe, + 0xfb,0xa9,0x88,0x08,0xf4,0x2c,0x46,0x2c,0x90,0xfa,0x2f,0xf0,0xef,0xfa,0x8d,0xbe, + 0x30,0xed,0x23,0xa3,0x2e,0x19,0x1b,0x9b,0xb0,0x13,0x1c,0xec,0xea,0x6a,0xaa,0x6a, + 0xde,0x2b,0x57,0xa1,0x66,0x3d,0x06,0x60,0x89,0xfd,0x95,0x90,0x30,0x6e,0xfc,0x04, + 0xd4,0x35,0x82,0xec,0x59,0x45,0x59,0x65,0xd1,0xa2,0xc5,0x59,0x59,0xcf,0x68,0x0a, + 0xfe,0xa9,0x70,0x69,0xf5,0x5f,0x6e,0xe2,0xa9,0x43,0xcc,0xc4,0x53,0x47,0x8f,0x9d, + 0x40,0x4f,0x03,0x69,0xfc,0x5b,0x52,0x56,0xba,0xdc,0xc3,0x43,0x5b,0xeb,0x47,0xd1, + 0x77,0x9e,0x56,0x33,0xaf,0xba,0x9b,0xbb,0xfb,0x1b,0xd6,0x71,0x13,0x2f,0xff,0xc6, + 0xb1,0xe3,0xe4,0xe1,0xf2,0xd2,0x65,0xce,0x9f,0x3e,0x57,0x3f,0x78,0xf8,0xa7,0xf5, + 0x28,0x1b,0xd4,0xcb,0x97,0x0f,0x79,0xb9,0x6e,0xae,0xcb,0xdc,0xdf,0xb6,0x0a,0x03, + 0x4d,0xcd,0x5f,0x12,0x53,0x52,0x7e,0x1e,0xf1,0x33,0x7b,0x5e,0x53,0xf8,0x39,0x9b, + 0x51,0xa3,0x69,0xd2,0x11,0x0f,0xc0,0xe6,0xbb,0x02,0x83,0x7a,0x19,0xf4,0x82,0x21, + 0x15,0x5d,0xf4,0x52,0xe8,0xa1,0x38,0x71,0xf2,0x94,0xe4,0xd4,0x74,0x96,0x0d,0x13, + 0x7e,0x34,0x2f,0xbf,0xc0,0xc9,0x69,0x1e,0xe8,0x41,0x22,0xf6,0x0c,0x1a,0xeb,0x43, + 0xcc,0x49,0x58,0xa0,0xc3,0x7c,0x9f,0x95,0xab,0x75,0x7e,0xd4,0x15,0x85,0x85,0x61, + 0xc4,0x8e,0x1d,0x3b,0x2e,0xf8,0xec,0x91,0x51,0x17,0x51,0xfe,0xfd,0x33,0xfe,0x51, + 0x79,0x55,0xf9,0xd6,0xed,0xbf,0xeb,0xea,0xe8,0xb1,0x53,0x1e,0x08,0x7e,0x8b,0x16, + 0x2f,0x79,0xc5,0xa1,0xe6,0x67,0x6b,0x11,0x5f,0xff,0x25,0x3d,0x99,0x87,0x0e,0x1d, + 0x56,0x58,0x5c,0x94,0x9e,0x91,0xe5,0x38,0x67,0xae,0xd0,0xea,0x18,0xdd,0xe4,0xbb, + 0x4f,0x9e,0x32,0xad,0x35,0x98,0x42,0xf8,0x6e,0x03,0x5a,0xb0,0xef,0x26,0x3f,0x0d, + 0x0d,0x4d,0x51,0x98,0x5d,0x5e,0x4e,0x1e,0x64,0x80,0x2b,0x57,0xaf,0xd1,0x22,0xd7, + 0x5a,0xe8,0xe7,0xbf,0xa7,0xcf,0x9e,0xa9,0x6b,0xa8,0xdf,0x17,0xb2,0xdf,0xd4,0xd8, + 0x94,0xfd,0x65,0xc1,0xdc,0x30,0x32,0xea,0x73,0x30,0xec,0x90,0x58,0xae,0xec,0x32, + 0xc8,0xd0,0xd2,0xca,0xbf,0xa8,0x26,0x02,0xe2,0xdc,0x9d,0x98,0x18,0xe9,0xfb,0x77, + 0x71,0x73,0x57,0x52,0x52,0x16,0x84,0xaa,0xaa,0xda,0x96,0x6d,0xdb,0x60,0xae,0x36, + 0xb7,0xb4,0xc4,0x3f,0x7e,0xbc,0x78,0xf1,0x92,0xff,0x63,0xef,0x3c,0xa0,0xa2,0x3a, + 0xba,0x07,0x7e,0xce,0x5f,0x41,0x84,0x28,0x20,0xbb,0x2c,0x65,0x17,0x0b,0x6f,0x05, + 0x2c,0x08,0x28,0x0a,0x24,0x46,0xc5,0x5e,0x40,0x50,0x54,0x96,0x2a,0xbd,0xaa,0x08, + 0x46,0x45,0xfd,0x54,0x94,0x58,0x62,0x12,0x03,0x6a,0xa2,0x11,0x6b,0xc4,0x12,0x5b, + 0x34,0xc6,0x12,0xfb,0x17,0x35,0x08,0x96,0x88,0x62,0x49,0xfc,0x8c,0x05,0x6c,0xa0, + 0x91,0x26,0xb8,0xe8,0x39,0xff,0x3b,0xf3,0x76,0x97,0xc7,0x16,0x14,0x05,0x57,0xc8, + 0xdd,0xf3,0x3b,0x73,0x66,0xee,0xdc,0x99,0xb9,0x33,0xaf,0xdc,0x37,0x6f,0xdf,0x9b, + 0x07,0x12,0xb5,0xe7,0x37,0x63,0x23,0xe3,0x01,0x03,0x07,0x6f,0xdb,0xb6,0xbd,0xf6, + 0x0f,0x91,0x28,0x01,0x47,0xe8,0xca,0x55,0x19,0xbd,0x7a,0xb9,0x68,0x7a,0xe2,0xa5, + 0x39,0x5d,0xc4,0x63,0xb8,0xc7,0xf0,0xad,0xdb,0xb6,0x16,0x69,0xbe,0xa1,0x0d,0x64, + 0x6e,0xd9,0x66,0x66,0x66,0xae,0x64,0x7f,0x9d,0x80,0x86,0xd6,0xac,0x5d,0xa7,0x54, + 0xed,0xc6,0x4d,0x9b,0xe0,0x04,0xa2,0xaa,0x99,0x77,0x4d,0xc3,0x7a,0x05,0xaf,0x5e, + 0x3e,0x2b,0x2e,0x3e,0x7e,0xf2,0x64,0x4a,0x4a,0xaa,0xbb,0x7b,0x7f,0x70,0xac,0xb5, + 0x9c,0x7c,0x74,0x9a,0x93,0x2b,0x16,0x2f,0x6f,0x9f,0x6d,0xdb,0xb7,0xbf,0x76,0xc1, + 0xa8,0x3a,0xf9,0xdf,0x4d,0x99,0x99,0xa6,0xa6,0x02,0x25,0xb3,0x27,0x4d,0x49,0x2c, + 0xab,0x28,0xaf,0x7a,0xf5,0xf2,0xea,0xf5,0x1b,0x33,0x67,0xce,0xb1,0x30,0x17,0xaa, + 0xfd,0x1b,0xda,0xce,0xb6,0xf3,0xfc,0xd4,0x85,0x45,0x35,0x3f,0x91,0xfc,0xe7,0xcd, + 0xbf,0x52,0xe6,0x7d,0xde,0xb1,0xa3,0x8d,0xda,0xee,0xc0,0x80,0x84,0x47,0x44,0x5e, + 0xbd,0x7e,0xed,0xb5,0x17,0x81,0x70,0x9e,0xcc,0xb9,0x70,0x6e,0x69,0x5a,0xba,0x87, + 0xa7,0x57,0xdb,0xb6,0xed,0xd4,0x3e,0x81,0xa6,0x18,0x1c,0xc3,0xd6,0x86,0x9f,0x7e, + 0xda,0x77,0xf9,0x8a,0x95,0xf9,0x0f,0xee,0xbf,0xc9,0x09,0xbf,0xb0,0xa8,0x68,0xeb, + 0x8f,0xdb,0x87,0x0f,0xf7,0x84,0xab,0xb5,0x5a,0x86,0x1d,0x86,0x11,0x14,0xfa,0xf7, + 0x1f,0x90,0x55,0xf3,0x71,0x77,0x55,0x4a,0xcb,0x4b,0x0f,0x1e,0x3a,0x18,0x1a,0x1a, + 0x2e,0x30,0x35,0xaf,0xe5,0xcb,0x4a,0xd0,0x96,0xa5,0xa5,0x70,0xdd,0xba,0xf5,0xdc, + 0x2b,0x04,0xd8,0xa6,0xea,0xfd,0xef,0xe9,0x13,0xec,0x38,0xec,0x3f,0x70,0xc0,0xd7, + 0x57,0xa2,0x69,0x09,0x9d,0x4e,0x9d,0x3a,0xc3,0x80,0x3f,0x7e,0xdd,0x03,0x42,0xd0, + 0x8a,0xea,0x9e,0x6c,0x63,0x63,0xfb,0xdb,0xe9,0x53,0xaa,0xca,0x27,0x4e,0x9e,0x50, + 0x3d,0x46,0x06,0x0e,0x1c,0xf4,0x88,0x3e,0x31,0x72,0xff,0xe1,0xc3,0xf4,0xe5,0xcb, + 0xbb,0xf7,0x70,0x56,0xbb,0x52,0x1c,0xf4,0xd1,0x9a,0x11,0x2f,0x5c,0xbc,0xf0,0xf6, + 0x5d,0xf5,0x7f,0xfb,0x6a,0xda,0xdc,0xfb,0x0e,0xee,0xf7,0x0f,0x08,0x34,0x13,0x68, + 0xbc,0x2e,0xd2,0x6f,0xa9,0xef,0xe8,0xe0,0x98,0xfa,0xf9,0x82,0xbc,0x6b,0xd7,0x6a, + 0xaf,0xad,0xb8,0xb4,0x64,0xec,0xd8,0x71,0xaa,0xfd,0xdd,0x46,0x17,0xbf,0xaa,0x78, + 0x51,0xf9,0xdb,0xe9,0xd3,0xc1,0xc1,0xa1,0x7c,0x53,0xe5,0xa5,0xae,0x58,0x60,0x77, + 0x1a,0x36,0xdc,0xf3,0xc8,0xb1,0x63,0xb8,0xe6,0x06,0xf2,0x16,0xdc,0xbe,0x7b,0xbb, + 0x67,0x4f,0x35,0x4f,0x48,0xc2,0xfc,0x37,0x73,0xf3,0xe6,0x77,0x7f,0x91,0x0d,0x1c, + 0xdc,0xdd,0xfc,0xfc,0x3b,0xf7,0xee,0x01,0x77,0xf3,0xef,0xd3,0x30,0xff,0x59,0x71, + 0x89,0xe2,0x73,0x33,0x70,0x7a,0xb9,0x79,0xeb,0xd6,0x0f,0x99,0x5b,0xa6,0x27,0xcf, + 0x0c,0x0e,0x0d,0x19,0x37,0xce,0x17,0xae,0xcf,0xa7,0x4d,0x9b,0xbe,0x72,0xe5,0xaa, + 0xcb,0x79,0x79,0x6a,0x9f,0xda,0x7d,0x13,0xe0,0x20,0xbd,0x98,0x9b,0x9b,0xb1,0x76, + 0xcd,0xd4,0xa9,0xd3,0x43,0xc3,0xc3,0xe1,0xa4,0x14,0x18,0x14,0x1c,0x1d,0x1b,0x97, + 0x9a,0xba,0x60,0xfb,0xf6,0x1d,0x7f,0xdf,0xb9,0x5b,0x29,0x7d,0xfd,0x9d,0xa2,0x92, + 0xb2,0xb2,0xbb,0xf9,0x05,0xac,0xf1,0x6f,0x07,0x74,0xb9,0xa4,0x4c,0x79,0xc5,0x06, + 0x38,0xe4,0xef,0x15,0x3c,0xe0,0x0c,0x08,0x84,0x64,0x88,0xa4,0x55,0xaf,0xef,0x17, + 0xcc,0x1c,0xc1,0xa4,0xe3,0x27,0x4e,0x7e,0xb7,0x72,0x55,0xf2,0x8c,0x59,0x61,0x11, + 0x11,0x12,0x89,0xbf,0xaf,0x44,0x32,0x3e,0x34,0x74,0x62,0x42,0xc2,0x92,0x2f,0xbf, + 0xda,0xf7,0xcb,0x2f,0x37,0xff,0x7e,0xfd,0x12,0xd6,0x2c,0x75,0xfa,0xff,0x57,0xed, + 0x68,0x3c,0x7d,0x56,0xc3,0xc5,0xdf,0xbb,0x5f,0xb0,0x63,0xe7,0xee,0xe9,0xc9,0xb3, + 0x82,0x43,0x42,0x24,0x7e,0xfe,0x11,0x51,0x51,0x73,0x53,0x52,0x7e,0xd9,0xbf,0x5f, + 0xd3,0xf2,0xa4,0xb0,0x1b,0x14,0x15,0x3d,0xd9,0x7f,0xe0,0xd0,0xfc,0xd4,0xcf,0x23, + 0x22,0xa3,0xfd,0xfd,0xfd,0x83,0x82,0xc7,0x7f,0xf6,0xd9,0x54,0x98,0x6b,0xdf,0xba, + 0xfd,0xb7,0xda,0x37,0x7d,0x6a,0x01,0xc6,0xef,0xe1,0xe3,0xc7,0x59,0xd9,0xe7,0xd7, + 0xae,0xdb,0x30,0x37,0x65,0x7e,0x64,0x4c,0x74,0x60,0x50,0xd0,0xb8,0x71,0xe3,0x82, + 0x43,0x42,0x63,0xe3,0xe2,0xa1,0x89,0x1f,0x77,0xec,0xbc,0x92,0x97,0xf7,0x16,0xcb, + 0x23,0x80,0x25,0x30,0x17,0xde,0xb1,0x6b,0x77,0x4a,0xca,0xbc,0x98,0xd8,0xb8,0x80, + 0xc0,0x40,0xd8,0x51,0xa1,0x8f,0x13,0x26,0x26,0xcc,0x99,0x9b,0xb2,0x6e,0xc3,0xc6, + 0x53,0xbf,0x9f,0xbe,0x9b,0xff,0xa0,0x4e,0x35,0xdf,0xbb,0x9f,0xbf,0xff,0xd0,0xa1, + 0x85,0x8b,0x16,0x47,0xc7,0xc6,0x83,0x9d,0x12,0x89,0x24,0x28,0x98,0xec,0xa2,0x33, + 0x66,0xcc,0x5c,0xbe,0x7c,0xc5,0xb1,0xe3,0xc7,0x61,0x27,0x51,0x1a,0x01,0x4d,0xcf, + 0x3f,0x9f,0xe4,0x7c,0x82,0x0a,0xf6,0xa2,0xab,0xd7,0xaf,0xaf,0xdb,0xb0,0xe9,0xb3, + 0xa9,0xd3,0xc9,0x56,0x90,0x48,0x60,0x2b,0xa4,0xcc,0x9b,0x5f,0xdb,0x56,0x50,0xde, + 0xd0,0xa5,0xec,0x9e,0xa9,0xd8,0x45,0x81,0x82,0x07,0x8f,0xd4,0xba,0x18,0x38,0xd0, + 0x38,0xca,0x05,0xec,0xc1,0xfe,0xa8,0xb0,0x90,0x7b,0xd9,0x50,0x5c,0x5a,0x9c,0x75, + 0x36,0x7b,0xe9,0xd2,0xf4,0xc9,0x89,0x49,0x70,0x18,0xfa,0xf9,0xf9,0x85,0x85,0x87, + 0xcf,0x4d,0x99,0xb7,0xe7,0xe7,0x5f,0x6a,0x79,0x5f,0xac,0x76,0xe0,0xaa,0x0c,0xae, + 0xb4,0x77,0xee,0xde,0x33,0x3f,0x75,0x41,0x74,0x4c,0x8c,0x9f,0x7f,0x80,0x9f,0x9f, + 0x7f,0x68,0x78,0x04,0x9c,0x46,0x56,0x67,0xac,0x3d,0x9b,0x93,0xf3,0xda,0x15,0xf0, + 0x14,0x3c,0x2a,0x2c,0xaa,0xfd,0xb0,0x85,0xfd,0xea,0xf6,0x9d,0xbb,0xbb,0x76,0xef, + 0x9e,0x39,0x6b,0x76,0x58,0x44,0xa4,0x9f,0x3f,0x38,0xff,0xa0,0xb8,0x09,0xf1,0x2b, + 0x57,0xad,0xba,0xf0,0xc7,0xa5,0xb7,0x3e,0x47,0x21,0x48,0xe1,0x93,0xc2,0x11,0x1e, + 0x1e,0x6a,0xaf,0xe7,0xe3,0xe2,0xe3,0xeb,0xba,0xda,0xcf,0xbb,0x00,0x97,0x9a,0xb0, + 0xcf,0x3f,0x2b,0x29,0x86,0x10,0xe2,0xf5,0xf3,0x0e,0xfb,0x2b,0x45,0xb5,0xcf,0xc0, + 0xeb,0xc1,0x21,0x09,0x27,0xb4,0xa6,0xf1,0x76,0x3c,0xf4,0xa2,0x52,0xca,0x76,0xad, + 0x04,0xce,0x6f,0x10,0x81,0x33,0x61,0x5d,0xbb,0x56,0x27,0xff,0xfb,0xe6,0x80,0x61, + 0x30,0xda,0xb0,0x29,0x4b,0xcb,0xcb,0x54,0x57,0x00,0x53,0x0b,0x9c,0xae,0x4b,0xcb, + 0xcb,0xd9,0xad,0xff,0xbc,0xb2,0xe2,0x5d,0xb7,0xd1,0x2b,0xf2,0x51,0x24,0xd8,0xdc, + 0xd4,0x0c,0xd8,0xf4,0x64,0x70,0xde,0xd0,0x92,0xda,0x81,0x4a,0x68,0xb5,0xc5,0x60, + 0x2a,0xdd,0xa3,0xde,0xb5,0x5a,0xe8,0x38,0xc7,0x4e,0xb2,0x8b,0x92,0x5b,0x43,0x1a, + 0xba,0xaf,0xd1,0xff,0x9e,0x52,0x33,0x33,0x85,0x61,0x64,0xab,0xa5,0xbb,0xbd,0xf6, + 0x57,0x64,0x92,0x56,0x55,0xc1,0x56,0x60,0x77,0x0c,0xd8,0xca,0xf5,0x65,0x12,0x1c, + 0xd1,0xdc,0xa3,0x00,0x2e,0x81,0x5e,0xbb,0x28,0xd0,0x5b,0x03,0x95,0xc3,0x2e,0x0d, + 0x0d,0xb1,0x5b,0xaa,0xe1,0x1a,0x42,0xfe,0x25,0xc0,0x41,0x0a,0xd7,0xc9,0x6a,0x6f, + 0xad,0x08,0x2d,0x85,0x47,0x8e,0x1e,0xd5,0xf4,0x9d,0x38,0x05,0x15,0x95,0x15,0xf8, + 0xd4,0x41,0x23,0xa5,0x4e,0xcf,0x5f,0x21,0x5a,0x67,0xfb,0x4e,0xf5,0xcf,0x3f,0xff, + 0xf7,0xb4,0xc6,0x4f,0x30,0x23,0x08,0xf2,0x21,0xf3,0xeb,0xe1,0x23,0x6a,0x57,0x70, + 0xd5,0x69,0xa6,0xe3,0xd0,0xcd,0x71,0x53,0x66,0xe6,0xe3,0xa2,0xc7,0xdc,0x8b,0x55, + 0xb8,0x38,0x87,0xeb,0x58,0x10,0x5e,0xba,0x7c,0x69,0xed,0x86,0xf5,0x01,0x01,0x81, + 0x47,0x8e,0xa9,0x79,0x30,0x03,0xf9,0xf0,0xa9,0xd3,0xff,0xbf,0x88,0xd6,0xd1,0xf4, + 0xfd,0x23,0xb5,0xff,0xcc,0x22,0x08,0xf2,0xe1,0x53,0x5c,0x5a,0xda,0xcd,0x41,0xf9, + 0x0b,0x5f,0x0a,0xda,0x18,0x9b,0x0c,0xf7,0x18,0x31,0x3f,0x35,0x75,0xcb,0x8f,0x5b, + 0x76,0xef,0xd9,0xbd,0x79,0xfb,0xb6,0xa5,0x69,0x69,0x93,0x13,0x93,0x86,0x0d,0x1b, + 0x6e,0xdb,0xd1,0xb6,0x95,0x41,0x2b,0xf0,0xdd,0xab,0x33,0xd6,0x68,0xbd,0x17,0x8d, + 0x8b,0x4a,0xe9,0x0b,0x40,0xb1,0x7a,0x55,0xa5,0xb4,0x52,0x2b,0x6b,0xb6,0xa3,0xff, + 0x6d,0x5c,0x68,0xbc,0xff,0x7c,0xfa,0xbf,0xf5,0xdb,0xd0,0x8b,0x2a,0xe9,0x73,0x7a, + 0x5f,0x8b,0x0d,0x21,0x89,0xdf,0x14,0x40,0x90,0x06,0x62,0xcb,0xb6,0xed,0x02,0x41, + 0xdd,0x5e,0x36,0xe7,0x32,0x37,0x25,0x45,0xeb,0x5d,0x68,0x2c,0x54,0xbd,0x7a,0xf9, + 0xd3,0x4f,0x3f,0xf7,0xe9,0xdb,0xcf,0xd5,0xed,0x63,0x25,0xfe,0xba,0x55,0xdb,0x5b, + 0x21,0x0d,0x41,0x03,0xfd,0xff,0x8b,0x34,0x10,0x9a,0xd6,0xdf,0xf8,0xed,0xf4,0xe9, + 0x7a,0x6c,0x65,0xff,0x81,0x43,0xdc,0xdd,0xd2,0xc5,0xd5,0xad,0x97,0x8b,0xeb,0xb0, + 0xe1,0x1e,0xe7,0x2f,0x5c,0xd0,0xfa,0x08,0x20,0x48,0xd3,0xe3,0x9f,0x92,0x67,0x53, + 0xa7,0x4e,0x7b,0xeb,0x77,0x5d,0xa3,0x62,0x62,0xb5,0xde,0x85,0x46,0x84,0xda,0xf5, + 0x27,0xeb,0xeb,0xfb,0xbf,0x75,0x02,0xfd,0x6f,0xe3,0x42,0xb3,0xff,0xad,0xcf,0xfb, + 0xcf,0x9b,0x36,0xd5,0x61,0xfd,0x0d,0x04,0x41,0xde,0x9d,0x87,0x8f,0x1f,0xc7,0xc7, + 0x4f,0x7c,0x93,0x95,0x2b,0x54,0xf1,0x1c,0xe9,0x85,0x8f,0x60,0xbd,0x21,0x30,0xff, + 0xad,0xeb,0xf7,0x17,0x1a,0x0e,0x7c,0xfe,0xaa,0x71,0xa1,0x69,0xfd,0xab,0xfa,0x7d, + 0xfe,0xaa,0x4e,0xdf,0x1f,0x44,0x10,0xa4,0x5e,0xf8,0xe7,0xd9,0xb3,0xf4,0x65,0xcb, + 0xed,0xbb,0x76,0xab,0x65,0x05,0x03,0xb5,0xb8,0xb9,0xb9,0xa9,0xbe,0xe5,0x8a,0x68, + 0x62,0xcd,0xba,0x75,0x1f,0x8a,0xff,0xc5,0xff,0x7f,0x1b,0x15,0xef,0xe7,0xff,0xdf, + 0x3a,0xad,0x3f,0x89,0x20,0x48,0x7d,0x51,0x29,0xad,0xcc,0xcd,0xcd,0x4b,0x4c,0x4c, + 0xb2,0xb5,0xed,0xf4,0x26,0x4b,0x1f,0xb7,0xd0,0x6d,0xc1,0x30,0xe2,0xc9,0x49,0x89, + 0xb5,0xac,0xf0,0x86,0x70,0xd1,0xb8,0xfe,0xb3,0x6e,0x8b,0x0b,0x97,0x2e,0xbd,0x67, + 0x63,0xd0,0xff,0x36,0x2e,0x34,0xbd,0x7f,0xf4,0x1e,0xfc,0xaf,0xa6,0xf5,0x27,0x11, + 0x04,0xa9,0x77,0x8a,0x9e,0x3e,0x3d,0x7a,0xfc,0xc4,0xe2,0xc5,0x4b,0x42,0x43,0x43, + 0x87,0x0c,0x19,0xf6,0xb1,0x5b,0xef,0x9e,0xce,0xbd,0x5c,0x5c,0xdc,0xfa,0xf5,0x73, + 0x1f,0x31,0xc2,0x23,0x30,0x38,0x38,0x79,0xc6,0xac,0xf5,0x1b,0x36,0x66,0xe5,0xe4, + 0xfc,0x53,0x5c,0xdc,0x34,0x56,0xb4,0x78,0x6f,0xa8,0x9d,0xff,0xd6,0xf2,0xfd,0xa3, + 0x86,0xe3,0xfb,0x8c,0x95,0xaa,0xfe,0xd7,0xdc,0xdc,0xe2,0xf4,0x99,0x33,0x5a,0x1f, + 0x25,0x44,0x95,0x2d,0xdb,0x34,0xbd,0x7f,0x54,0x9f,0xcf,0x5f,0xe1,0xfc,0x17,0x41, + 0x3e,0x04,0xa4,0x55,0x55,0x25,0x65,0x25,0x8f,0x0a,0x0b,0xef,0x15,0xe4,0xdf,0xbe, + 0x73,0xfb,0x0e,0x59,0x98,0xad,0xa0,0xf0,0x49,0x51,0x71,0x69,0x09,0x2e,0x36,0xfe, + 0x76,0xc0,0xb5,0xca,0x9a,0xb5,0xeb,0xda,0x18,0xb5,0xd1,0xd7,0xd3,0xe7,0x02,0x1e, + 0xf9,0x72,0x5e,0xde,0x7b,0x36,0x66,0x75,0x46,0x86,0x7a,0xff,0x8b,0xf3,0xdf,0x0f, + 0x12,0x4d,0xcf,0x5f,0xd5,0xef,0xfc,0x77,0xf3,0xd6,0xad,0x4a,0x3b,0x27,0x60,0x25, + 0xb2,0x42,0xff,0x8b,0x20,0x48,0x63,0x27,0x2f,0xef,0xea,0x8a,0x6f,0x57,0xa6,0xa5, + 0xa7,0xa7,0x2f,0x5b,0xfe,0x4d,0x5a,0x3a,0x8d,0x2c,0x5b,0xb6,0x62,0x45,0xe1,0x93, + 0x27,0x0d,0xdd,0xb4,0x12,0x6b,0xd7,0x6d,0x10,0x98,0x0a,0x8c,0x0c,0x8d,0x8c,0x8c, + 0x8d,0x64,0xa1,0xb1,0x91,0xb8,0xa3,0x4d,0xb6,0xe6,0xaf,0xf2,0x21,0x5a,0xe4,0xa7, + 0xbd,0x7b,0x2d,0x2c,0x2d,0x8d,0x8d,0x4d,0x8c,0xd8,0x9f,0xa1,0x91,0x49,0x1b,0x13, + 0xe0,0x4c,0x56,0x56,0x3d,0xb6,0x72,0xed,0xc6,0x75,0xd8,0x27,0xd3,0xd2,0x97,0x43, + 0xf8,0x4d,0xda,0x32,0xd8,0x39,0x21,0xf2,0x7d,0xc6,0x9a,0x7b,0x05,0x75,0xf8,0x4a, + 0x02,0x82,0x20,0xc8,0x87,0x89,0xf4,0x65,0x95,0xf4,0x25,0x59,0x89,0x9a,0x0d,0x59, + 0xde,0xbf,0x19,0x8f,0x0b,0x8b,0xb2,0xb2,0xb3,0xb3,0xcf,0x9d,0xcb,0xca,0x39,0xc7, + 0x86,0xc0,0xf9,0x8b,0x97,0x4a,0xca,0x4a,0xb4,0x3e,0x44,0x88,0x2a,0x45,0x4f,0xff, + 0xc9,0x39,0x7f,0x3e,0x2b,0x27,0xe7,0x6c,0xce,0xb9,0xb3,0xe7,0xc8,0x26,0xcb,0x3e, + 0x77,0x1e,0x28,0x29,0xad,0xe7,0xa7,0x1f,0xe9,0x9e,0x49,0x76,0x4e,0x08,0xd9,0x9d, + 0xf3,0xdd,0x3f,0x45,0x8a,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08, + 0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82, + 0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20, + 0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08, + 0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82, + 0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20,0x08,0x82,0x20, + 0x08,0x82,0x20,0x08,0x82,0xd4,0x17,0x55,0xaf,0xaa,0xa4,0x2f,0xa5,0x95,0xd2,0xca, + 0xf2,0x8a,0xf2,0xd2,0xe7,0x65,0x25,0xe5,0xa5,0x40,0x29,0x0b,0x4d,0xd6,0x12,0x96, + 0x2a,0x34,0x51,0xb9,0x71,0x2a,0xe3,0xe6,0x6e,0xda,0xca,0x0d,0xbe,0x7d,0x39,0xc9, + 0xb2,0xe7,0x65,0x94,0xf2,0xf2,0x8a,0xe7,0x70,0x32,0x29,0xab,0x78,0xce,0x52,0x2e, + 0x8f,0x68,0xa6,0xe2,0x0d,0x24,0x75,0xe2,0x1d,0x8b,0x37,0x05,0xca,0x2b,0x2b,0x2a, + 0xa4,0xd2,0x17,0x2f,0xa5,0x55,0xaf,0xe0,0x24,0xaf,0x7d,0x47,0x83,0x00,0xe0,0x6a, + 0x4b,0xcb,0x4a,0x1f,0x16,0x3d,0xbe,0x79,0xeb,0x7f,0xe7,0x2e,0x5e,0x38,0x72,0xf4, + 0x48,0xe6,0x96,0x2d,0xcb,0x56,0xac,0x98,0x35,0xe7,0x3f,0xb1,0x71,0xf1,0x21,0x21, + 0xa1,0x41,0xc1,0xe3,0x81,0xf1,0x21,0xa1,0xc1,0xe3,0x43,0x42,0xd8,0x30,0x34,0x0c, + 0x24,0x4a,0xa1,0x22,0x17,0x12,0xa8,0xdc,0x78,0x95,0x71,0x73,0x37,0x6d,0xe5,0x86, + 0xde,0xbe,0xdc,0x64,0x58,0x58,0x78,0x44,0x44,0x64,0x74,0x54,0x7c,0xd4,0x84,0xcf, + 0xa2,0x12,0xe6,0x44,0x25,0x2e,0x88,0x99,0xf6,0x75,0xcc,0xb4,0xf4,0xd8,0xe4,0xb4, + 0x98,0xe9,0xe9,0x31,0xd3,0x97,0xc5,0x24,0x2f,0x83,0x24,0x09,0xd9,0x88,0x9c,0xe8, + 0xe9,0x2b,0xb8,0x49,0xb5,0x12,0x59,0x41,0x45,0xa8,0x9a,0x54,0x5b,0x9c,0xcd,0x85, + 0xa6,0xb9,0xad,0xab,0x2d,0x95,0xbc,0x4c,0xa6,0xc6,0x52,0x4b,0xbb,0x5c,0x61,0xed, + 0x15,0x2a,0x45,0x94,0x92,0x5c,0xab,0x54,0x73,0xd5,0xa2,0xa9,0x15,0x55,0x9b,0xa7, + 0xa5,0x4f,0x98,0xb5,0x62,0xc6,0x57,0x3f,0x7c,0x93,0xb1,0x6b,0xf3,0xce,0xe3,0xfb, + 0x8f,0xe6,0xfc,0xfe,0xc7,0x5f,0x7f,0xdd,0xba,0xfd,0xe0,0xf1,0xd3,0xe2,0xd2,0xd2, + 0xca,0x17,0x2f,0xb4,0xee,0x89,0xfe,0x3d,0x80,0xcf,0x2d,0x7a,0xfa,0xe4,0xe2,0x1f, + 0x17,0x57,0xaf,0x59,0xe3,0x1f,0x14,0xf0,0x49,0xef,0xde,0x5d,0xba,0x74,0xb1,0x12, + 0x59,0x09,0x4c,0xcd,0x4c,0x8c,0x4d,0x0c,0x5b,0x19,0x1a,0xb4,0x34,0xd0,0xd3,0xd5, + 0xd3,0x6d,0xae,0xab,0xd3,0x4c,0x07,0x41,0x10,0xe4,0xad,0x81,0xd3,0x88,0xae,0x8e, + 0x9e,0x8e,0x8e,0xbe,0xae,0xee,0x47,0x2d,0xf5,0xdb,0xb4,0x34,0xee,0x60,0x20,0xb0, + 0x37,0xb4,0xfa,0xc4,0xd8,0x7a,0xb0,0x89,0x8d,0x97,0x89,0x8d,0xb7,0x49,0x47,0x6f, + 0x13,0x9b,0x51,0x26,0x1d,0xbd,0x48,0x84,0xc4,0xbd,0x64,0x72,0x9b,0x91,0x26,0x36, + 0xa3,0x69,0x48,0x23,0x1d,0x3d,0x89,0x1a,0xc1,0x9b,0x67,0x4b,0xe5,0x24,0xf4,0x32, + 0xb1,0xf5,0x92,0xa9,0xd5,0x48,0x7a,0xf1,0xec,0x46,0xb2,0xca,0x10,0xf2,0x6c,0x47, + 0xf2,0x6a,0xe6,0x92,0xd0,0x56,0x11,0x82,0xdc,0xbb,0x5a,0x4e,0x9a,0xf3,0x96,0xd5, + 0x26,0x13,0x12,0x78,0x32,0x1d,0x0f,0x5a,0xa7,0x17,0x55,0x18,0x4d,0xe3,0xde,0x8a, + 0xda,0x78,0xb6,0x9e,0xca,0x56,0xb1,0xc6,0xd8,0x92,0x0a,0xa9,0x19,0xb4,0x20,0xe9, + 0xcb,0x18,0xa2,0xac,0x30,0x40,0xd1,0x90,0xac,0xa0,0xbc,0xac,0x3c,0x97,0xed,0x02, + 0xed,0x94,0x97,0x6a,0x2e,0x3b,0x62,0x3c,0xbb,0x51,0xd0,0x11,0x9e,0x1d,0xb4,0x05, + 0x11,0x68,0xd4,0xc7,0x44,0x3c,0xb2,0x8d,0xd8,0x93,0xb5,0x13,0x6c,0xe0,0xdb,0x79, + 0x99,0x75,0xf2,0xb1,0xb4,0x1f,0xd3,0xce,0xc9,0xd7,0xba,0xe7,0x78,0xbb,0xde,0x11, + 0xf6,0x83,0xe3,0xdc,0x7d,0x12,0xc7,0x44,0xa6,0x2e,0x5c,0xfe,0xe3,0x89,0x33,0xb9, + 0x77,0x0a,0x0a,0x2b,0x5e,0x54,0x6a,0xdd,0x43,0x35,0x55,0x4a,0xca,0x4a,0x2f,0xe6, + 0xe6,0x2e,0x4d,0x4b,0xf3,0xf2,0xf2,0xb6,0x6e,0x6f,0xad,0xaf,0xa7,0xdf,0xfc,0xff, + 0x9a,0x23,0x08,0x82,0xbc,0x57,0x74,0x0c,0x74,0x5b,0x1a,0xb7,0x34,0xea,0xd0,0x5a, + 0xe4,0x66,0x22,0xf6,0xe0,0xd9,0xf8,0x80,0xe7,0xe5,0xd9,0x81,0x63,0x1a,0xc5,0x23, + 0x9e,0x82,0x7a,0x1c,0x3b,0x1f,0x9e,0xdd,0x58,0x93,0x8e,0x24,0x62,0xd2,0xd1,0x87, + 0x47,0x7c,0xb4,0x0f,0xf1,0x29,0x36,0x10,0x1f,0x03,0x9a,0x90,0x64,0xa1,0x6a,0x4a, + 0x49,0xaa,0x66,0xeb,0xa3,0x2c,0x54,0x89,0x2b,0xa1,0x54,0x55,0x8d,0x2c,0xf0,0xe3, + 0x90,0xcb,0x3a,0x47,0x85,0x32,0x27,0xa9,0x30,0x52,0xb5,0x2a,0xae,0xbc,0xba,0x2f, + 0xca,0xca,0x1a,0xcd,0xa8,0x53,0x2e,0xed,0x3b,0xb1,0x8a,0x1a,0x3c,0x86,0x8c,0x1e, + 0xbd,0x42,0x90,0x0f,0xa0,0x17,0xbd,0xd4,0x21,0xd0,0x81,0x85,0x01,0xf7,0x84,0xeb, + 0x01,0x18,0x7c,0xc6,0x35,0x78,0xc0,0xb8,0x99,0xb3,0xbe,0xdc,0x70,0xf0,0xe4,0xb9, + 0xa2,0xe2,0xb2,0xaa,0x57,0x55,0x5a,0x77,0x58,0x4d,0x83,0x82,0x07,0xf7,0xf7,0xed, + 0xdf,0x3f,0x29,0x61,0x72,0xf7,0xee,0x3d,0x0c,0xf4,0x3f,0xd2,0xfe,0xd1,0x87,0x20, + 0x08,0x42,0xd1,0x69,0xd1,0x5a,0x9f,0x67,0x63,0xd4,0xae,0x0f,0xf8,0x02,0x7e,0xe7, + 0x71,0xfc,0x4e,0xe3,0x78,0x14,0x88,0xf3,0x6c,0xc7,0xf2,0x3a,0x4b,0x78,0xb6,0x34, + 0xce,0x0a,0xa9,0x5c,0x0b,0xc9,0x2e,0xbe,0x3c,0xb9,0x61,0x60,0x15,0x9b,0xcb,0xeb, + 0x24,0x51,0x52,0xa6,0xf8,0x72,0xcb,0x42,0x41,0xd2,0x23,0x3b,0x5f,0x7e,0x17,0x49, + 0x75,0xb2,0x93,0xa4,0xe1,0x6c,0x26,0x56,0xd9,0xc9,0x43,0x18,0x40,0x00,0x22,0x76, + 0x74,0x60,0xed,0xc6,0xb2,0xa3,0x4a,0x42,0x92,0x3b,0x86,0xe6,0x12,0x1d,0x7a,0x3d, + 0x00,0x49,0x2f,0x1a,0x8e,0xe9,0xd4,0x37,0x2c,0x64,0xf2,0xd7,0x6b,0xb6,0xfd,0x7a, + 0xfd,0xe6,0x9d,0x4a,0x29,0xde,0x9d,0x7e,0x1b,0xe0,0x02,0xa6,0xe8,0x9f,0x27,0x3b, + 0x76,0xed,0x1a,0x38,0x64,0x90,0xc0,0xd4,0x4c,0xa7,0x99,0x8e,0xd6,0x8f,0x35,0x04, + 0x41,0x10,0x65,0x9a,0xe9,0xe8,0xe8,0x1a,0x18,0xb4,0x69,0x6f,0xd8,0xb6,0x0f,0xaf, + 0x93,0x0f,0x71,0x52,0x5d,0xfd,0x68,0x28,0xe1,0x77,0xf5,0x27,0x61,0x17,0x4a,0x57, + 0x16,0xdf,0x5a,0x43,0x25,0xea,0xa4,0x5c,0x93,0x2e,0x2a,0x55,0x39,0x04,0x91,0xd0, + 0x3e,0x48,0x56,0xdc,0xde,0x5f,0xb9,0xa1,0x2e,0x6a,0x9b,0xa0,0xdd,0x21,0x48,0x6a, + 0x74,0x8a,0xc8,0xdf,0xdd,0x66,0x15,0x05,0xb0,0xaa,0x33,0xc4,0x03,0x64,0x83,0xd6, + 0x2d,0x88,0xf8,0xe8,0xae,0x81,0x7c,0xfb,0x40,0x92,0x05,0x80,0x84,0x98,0x11,0x40, + 0xc2,0xce,0xd4,0x24,0x12,0xa9,0xf6,0xce,0xec,0x9c,0x1a,0xbc,0xb0,0x65,0x37,0x3f, + 0x17,0x8f,0xc9,0x9f,0xa7,0x6f,0xbe,0x75,0xf7,0x01,0x7a,0xe1,0x3a,0x51,0x51,0x59, + 0xf1,0xd3,0xde,0xbd,0xde,0xa3,0x46,0xb5,0x6e,0xd5,0x5a,0xfb,0xc7,0x17,0x82,0x20, + 0xc8,0x6b,0x69,0xa6,0xab,0xd7,0x5a,0x64,0xd4,0xa1,0x3f,0xf1,0x71,0xdd,0xc6,0x13, + 0x9c,0xc2,0xf9,0x0e,0xc1,0x7c,0x87,0x30,0x82,0x53,0x18,0x49,0x3a,0x85,0xf2,0x9d, + 0x22,0xf8,0x4e,0x21,0x2a,0x61,0x28,0xcd,0x0d,0xe3,0x50,0x57,0x65,0x36,0x12,0x41, + 0x09,0x97,0xb7,0x18,0x46,0x94,0x1d,0xd9,0xaa,0x42,0x64,0x38,0x2a,0xaa,0xaa,0xd9, + 0x90,0xc3,0x78,0x12,0x2a,0x72,0xa1,0x94,0x63,0x84,0x80,0x9b,0xe5,0x10,0x42,0x94, + 0x1d,0x69,0x16,0x29,0xfe,0xee,0x36,0xab,0x28,0x43,0x43,0xa4,0x5d,0x0a,0x3b,0x6e, + 0xec,0x48,0x2a,0x13,0x48,0x1c,0x31,0x00,0x7e,0x19,0xfc,0xaf,0x3d,0xeb,0xaf,0x7d, + 0xd9,0x99,0xbe,0x6c,0x4e,0x4d,0x67,0xc7,0xa6,0x76,0x63,0x5d,0x86,0x4d,0xfa,0x6e, + 0xdd,0x4f,0xf7,0xf2,0x1f,0x68,0xdd,0xaf,0x7d,0xf8,0x3c,0x2b,0x79,0x76,0xe8,0xf0, + 0xaf,0xfe,0x81,0x01,0x7c,0x13,0xbe,0x6e,0x73,0x5d,0xed,0x1f,0x53,0x08,0x82,0x20, + 0x6f,0x8c,0xae,0xae,0xbe,0xbe,0xb1,0xb5,0x89,0xad,0x97,0x59,0xf7,0x48,0x81,0x73, + 0xac,0xb9,0x73,0x8c,0xb9,0x73,0x9c,0xa0,0x7b,0x8c,0xa9,0x53,0xb4,0x69,0xf7,0x18, + 0x1a,0x89,0x82,0x88,0x0c,0x10,0x52,0x79,0x7d,0x25,0x05,0xdd,0xd9,0x30,0xc6,0xac, + 0x07,0x10,0x6b,0xda,0x5d,0x16,0x17,0x50,0x1d,0x22,0x71,0x8a,0x86,0xf0,0x4d,0x92, + 0x60,0x27,0x1b,0x17,0xf4,0xa8,0xce,0xa2,0x5d,0x88,0x65,0x93,0xf5,0x6b,0xb9,0x3c, + 0x19,0x6d,0xe6,0x1c,0x6f,0xe6,0x1c,0xcb,0xca,0x89,0xf1,0x64,0x0c,0xe3,0x48,0xbb, + 0xd4,0x18,0xe8,0x0b,0x4d,0xc2,0x18,0x46,0x09,0x9c,0x22,0xf9,0x4e,0x91,0xa6,0x10, + 0x3a,0x84,0xca,0xe8,0x16,0x40,0xe7,0xf5,0x7e,0xb2,0xbb,0x10,0xf4,0x1f,0x01,0x40, + 0xe8,0xe0,0xff,0x89,0x67,0xe2,0xda,0xed,0xc7,0xff,0xbe,0xfb,0x48,0x5a,0x85,0x7f, + 0x0d,0xab,0x41,0xfa,0x52,0x9a,0x7b,0xe5,0x4a,0xdc,0x84,0x09,0x6d,0x45,0x6d,0xf1, + 0x6e,0x33,0x82,0x20,0x8d,0x17,0x3d,0x3d,0xc3,0x56,0x42,0x37,0x0b,0xe7,0x58,0xa1, + 0xdb,0x14,0xa1,0xdb,0x67,0x80,0x85,0xeb,0x14,0x4b,0x57,0x36,0x92,0x08,0x11,0x16, + 0x10,0xb2,0xf2,0xfa,0x4a,0x0a,0xdd,0x92,0x2c,0x5c,0x93,0xa0,0x15,0x4b,0xb7,0x24, + 0x2a,0x4f,0xb2,0x74,0xa3,0x61,0xaf,0x24,0x35,0x45,0x7a,0x25,0x02,0x9a,0x2b,0x4c, + 0x84,0xaa,0x64,0x95,0x34,0x80,0xa9,0x1a,0x92,0x49,0x16,0x6e,0x89,0x96,0x2e,0x93, + 0x59,0x39,0x19,0x2e,0x17,0x08,0xa7,0x58,0xba,0x24,0x09,0x3f,0x9e,0x2a,0x74,0x99, + 0x62,0xee,0x92,0x68,0xd9,0x33,0xc9,0xa2,0x57,0x82,0x45,0xcf,0x04,0x61,0xcf,0xc9, + 0x70,0xbd,0x01,0x83,0x2c,0x20,0x4e,0x19,0xdc,0x74,0x2c,0x99,0x56,0x3b,0xd2,0xf9, + 0x3e,0xb9,0x53,0x1d,0x2c,0xbb,0x49,0x0e,0x93,0x62,0xbb,0x71,0x26,0xb6,0x63,0x84, + 0x8e,0x01,0x23,0x82,0xe7,0xee,0x3d,0x78,0xa6,0xfc,0x39,0x3e,0x26,0x5d,0x83,0x92, + 0xb2,0xd2,0x85,0x8b,0xbf,0xb0,0xb4,0x10,0x6a,0xfd,0xc0,0x41,0x10,0x04,0x79,0x77, + 0x60,0x12,0x61,0x60,0x68,0x69,0xda,0x45,0x22,0xec,0x9d,0x2c,0x72,0x9f,0x2d,0xec, + 0x33,0x5b,0xd4,0x7f,0xb6,0xb0,0xef,0x7f,0x00,0x36,0x52,0x23,0x74,0x9f,0x2d,0xea, + 0x37,0x5b,0x16,0x2a,0x22,0xee,0x2a,0x6a,0xaf,0x53,0x16,0xf6,0x4b,0x61,0x93,0xc2, + 0x7e,0x73,0xa8,0xf2,0x5c,0x61,0x9f,0x39,0x24,0x97,0x2d,0xd8,0x4f,0x56,0x44,0x61, + 0x06,0x01,0x92,0x7d,0x38,0x56,0x55,0xeb,0xbc,0xa6,0x6c,0x03,0x76,0x81,0xd3,0x10, + 0x65,0x26,0x35,0x72,0x96,0xc8,0x7d,0x96,0xf0,0x53,0x4a,0x9f,0x99,0xc2,0x4f,0x92, + 0x85,0x9f,0x26,0x0b,0x7b,0x4f,0x27,0x50,0x07,0x0d,0x13,0x67,0xcb,0x9e,0x93,0x2c, + 0x9c,0xe3,0xc1,0x1d,0x03,0x30,0x95,0x36,0x75,0x0c,0x37,0x05,0x2f,0x4c,0xee,0x54, + 0x07,0xb3,0x93,0x62,0x70,0xc4,0x82,0xae,0x81,0x92,0xb8,0x45,0x17,0xaf,0xe5,0x6b, + 0xdd,0xeb,0x7d,0x20,0xdc,0xcd,0xbf,0x97,0x3c,0x73,0x66,0x1b,0xa3,0x36,0xec,0x4b, + 0xbb,0x5a,0x3f,0x70,0x10,0x04,0x41,0xea,0x85,0x96,0xfa,0x26,0x3c,0x9b,0xc1,0x96, + 0xfd,0xe7,0x8b,0x06,0x7d,0xd1,0x76,0xf0,0x17,0xa2,0x81,0x5f,0x88,0x06,0x2d,0xa9, + 0x66,0x60,0x4d,0x49,0x3d,0x26,0x07,0x7f,0x29,0x93,0x28,0xb5,0xa8,0x16,0x85,0xa6, + 0x42,0xb9,0x96,0x52,0x0d,0x67,0xb3,0x6a,0x52,0x26,0x5c,0xac,0x88,0x58,0x0d,0x5a, + 0x6c,0x35,0x70,0x01,0x44,0x84,0xee,0xa9,0xc2,0xfe,0xa9,0x42,0xf7,0x79,0x42,0x77, + 0xb8,0xe4,0x98,0x23,0xfc,0x74,0xa6,0xf0,0xd3,0xd9,0xc2,0x8f,0xa7,0xc1,0x7c,0x5f, + 0x08,0xb3,0xe9,0x9e,0x09,0xe4,0x8e,0x7a,0x4f,0x7a,0xb7,0xdf,0x29,0xdc,0xd4,0x21, + 0x94,0x3c,0xb2,0x65,0x1f,0x48,0x6f,0x4a,0xfb,0x9a,0x75,0x91,0xf4,0x1d,0x3d,0xed, + 0xd4,0x85,0x1b,0xff,0xf2,0xe7,0xb2,0xaa,0x5e,0x55,0x5d,0xce,0xbb,0x3a,0xd2,0xcb, + 0xbb,0x75,0xab,0xd6,0xe4,0x55,0x77,0xf2,0xb6,0x3b,0xfe,0xe7,0x8b,0x20,0x48,0x93, + 0xc2,0xa8,0x7d,0x6f,0xab,0x01,0x0b,0xac,0x47,0xac,0xec,0x30,0xec,0x3b,0x08,0xad, + 0x47,0x7c,0xcf,0xd2,0x61,0xc4,0x6a,0xa0,0x21,0x92,0xd6,0x9e,0xab,0x3a,0x8c,0xf8, + 0x8e,0x15,0x32,0x9e,0x20,0x5f,0x45,0xda,0xf5,0x58,0x0d,0xd0,0x24,0xab,0xb3,0xda, + 0x9a,0x8d,0x0f,0x5f,0x05,0x30,0x9e,0x19,0x00,0x49,0x7a,0x50,0x09,0x55,0xa6,0x9a, + 0x2b,0x89,0x9a,0x07,0x95,0x37,0xa4,0xcd,0x9c,0xe4,0x2a,0x6a,0xff,0x6a,0x12,0x0e, + 0xff,0x0e,0xb0,0x86,0x70,0xe8,0xb7,0x0a,0xda,0x0d,0x59,0xd6,0x6e,0x68,0x3a,0x60, + 0x35,0xe8,0x1b,0xab,0x41,0x4b,0xad,0x86,0x2c,0x11,0x0e,0x5c,0x24,0x1c,0xb0,0xc8, + 0x6a,0xe0,0x7c,0x98,0xb6,0x8b,0xfa,0xce,0x12,0xf5,0x49,0x16,0xba,0x4d,0xb3,0x74, + 0x99,0x62,0xee,0x3c,0xc9,0xbc,0x47,0xbc,0xb9,0xf3,0x04,0x41,0xf7,0x68,0x72,0x5f, + 0x1a,0x26,0xc2,0xf6,0x01,0xfc,0xae,0xfe,0xbc,0xce,0x7e,0x0e,0x83,0x13,0x36,0x6c, + 0x3f,0x5a,0x51,0xf9,0x2f,0xbd,0x17,0xfd,0xbc,0xf2,0xf9,0x81,0x43,0x87,0x5d,0x5d, + 0xdd,0x3e,0x32,0xf8,0x48,0xb1,0x5c,0x95,0xd6,0x8f,0x14,0x04,0x41,0x90,0x7a,0xa6, + 0x99,0xae,0x81,0xa0,0xb3,0xa8,0xff,0x02,0x66,0xcc,0x66,0xc6,0x67,0x0b,0x33,0x6a, + 0x13,0x25,0x93,0x19,0x9d,0x29,0x8b,0x8c,0xa2,0x91,0xd1,0x14,0x36,0x17,0xb2,0x14, + 0xc9,0xd1,0x0a,0x32,0x95,0xcb,0x2a,0x14,0x46,0x6d,0xaa,0x96,0x90,0xb2,0x3f,0xc8, + 0x93,0xf2,0xca,0x95,0xea,0x1f,0xc5,0x29,0xe2,0x93,0x29,0xb3,0x61,0x74,0x66,0xcd, + 0xe6,0x38,0x35,0xd7,0x68,0x2e,0x93,0xf1,0xfe,0x41,0xd9,0x36,0x25,0x33,0x46,0x71, + 0xfb,0xc2,0xa9,0xa4,0x3a,0x57,0xa5,0x0b,0xd5,0x92,0xcc,0x6a,0x05,0x9f,0x9a,0x66, + 0x7b,0x6f,0x60,0xbc,0x37,0x42,0xeb,0xd6,0x23,0x33,0xac,0xbd,0x33,0xd8,0x8b,0x04, + 0x70,0xd0,0xed,0x87,0xad,0x68,0x3f,0x74,0x85,0xd5,0xd0,0xaf,0x45,0x83,0x60,0xe2, + 0xbf,0x48,0xd8,0xff,0x73,0xd9,0xa4,0xf8,0x13,0xe2,0x88,0xcd,0x5d,0x27,0x9a,0xf5, + 0x88,0x33,0xa3,0x37,0xa5,0xf9,0x8e,0x11,0xe4,0x01,0x75,0x98,0x0b,0x77,0xf6,0x65, + 0x5c,0xc3,0xe6,0x2f,0xdd,0xf2,0xb0,0xf0,0x69,0xd5,0x4b,0xed,0x3b,0xc4,0xf7,0x09, + 0x4c,0xfc,0xd7,0x6f,0xdc,0xd0,0xb5,0x6b,0x57,0x70,0xbe,0x7a,0x2d,0xf4,0xf4,0x74, + 0xf5,0x88,0xff,0x6d,0xae,0xd3,0x42,0xa7,0x85,0xf6,0x0f,0x16,0x04,0x41,0x90,0xfa, + 0xa5,0x99,0xae,0x3e,0xbf,0x53,0xdb,0x61,0x4b,0x98,0x80,0x9f,0x19,0xc9,0x5e,0x16, + 0xb1,0xdf,0x2e,0x12,0xf1,0xfb,0x99,0xc0,0x0a,0xfd,0xe4,0xf8,0xff,0x2c,0x4b,0x42, + 0xe8,0xcf,0x11,0xfa,0xc9,0xca,0x12,0xa1,0xef,0x1e,0x12,0xca,0xd4,0x48,0x5c,0x2c, + 0xd9,0x49,0x75,0x68,0x59,0x88,0xf8,0xee,0x66,0xfc,0xf6,0xc8,0x6b,0xe6,0x94,0x65, + 0x8b,0x40,0x71,0xaa,0x49,0xcc,0x90,0x15,0x91,0xd7,0xe9,0xcf,0xb1,0x84,0xd5,0x07, + 0x39,0xd1,0x97,0x35,0x54,0xdd,0x34,0x5b,0x55,0xb5,0x19,0x9c,0x86,0xb8,0xa6,0x4a, + 0xf6,0xc8,0xd4,0xb8,0x35,0x2b,0x75,0x01,0x0a,0xfa,0x73,0xfa,0x4e,0x3b,0x22,0xf6, + 0xdf,0x45,0xc3,0xdd,0x72,0xcb,0x49,0x8f,0xc4,0xbe,0x3b,0x99,0x71,0xbb,0x08,0x3e, + 0x9b,0x09,0xe0,0x9d,0xbd,0xd7,0x33,0x5e,0xeb,0xad,0x3d,0xc8,0x7c,0xb9,0xfd,0xd0, + 0xe5,0x6d,0x87,0xa6,0x59,0x0d,0xfc,0x4a,0x34,0x68,0x91,0xc8,0x7d,0x9e,0xa8,0xdf, + 0x1c,0xf2,0x1f,0xf1,0xc7,0xd3,0x2c,0x7b,0x4d,0x86,0xe9,0xb0,0xc0,0x39,0x9a,0xdf, + 0x3d,0x8a,0xef,0x14,0xc5,0xb7,0x97,0xf0,0xed,0xfd,0x2c,0x9c,0x42,0x26,0xfe,0x67, + 0xd5,0xed,0x82,0x87,0x5a,0xf7,0x89,0xef,0x8d,0xa2,0x27,0x4f,0x52,0x53,0x17,0xf0, + 0x4d,0x4d,0x5b,0xb5,0x6a,0x05,0xfe,0x17,0x60,0xdd,0x2e,0xbe,0x70,0x84,0x20,0x48, + 0x13,0x46,0xdf,0xa8,0x9d,0xd5,0xe0,0x2f,0x98,0x90,0xe3,0xcc,0xf8,0xe3,0x4c,0xf0, + 0x31,0x66,0xfc,0x49,0x26,0x14,0x22,0x47,0x98,0xe0,0xa3,0x24,0x09,0x84,0x1c,0xa1, + 0x91,0xa3,0x44,0x18,0x74,0x98,0xc6,0xe5,0xb9,0x6c,0x52,0x26,0x54,0xc0,0x29,0x2b, + 0x83,0x96,0xad,0x21,0x91,0xa3,0x5c,0x56,0x53,0x96,0xbc,0x86,0x5a,0xf4,0x55,0x0b, + 0xca,0x22,0x35,0x5b,0xaf,0x51,0x43,0xcd,0x8e,0xbc,0x89,0xcd,0xa0,0x19,0x7a,0xaa, + 0x46,0x32,0xe8,0x08,0xe5,0x10,0x13,0x70,0x50,0xce,0x01,0x71,0xc0,0x3e,0xe2,0xdf, + 0xc1,0x1d,0x8f,0xfd,0x91,0xdc,0x5e,0x20,0x13,0xe4,0x0d,0x1d,0x46,0xac,0x6a,0x3f, + 0xe4,0xdb,0xb6,0x83,0xbf,0xb1,0x1a,0xfc,0xb5,0x70,0xc0,0x22,0x51,0xff,0x14,0xf2, + 0xe0,0x96,0xdb,0x34,0x21,0x7d,0x52,0x4b,0xd0,0x23,0x86,0xb8,0x60,0xf6,0x6d,0x62, + 0x7b,0xbf,0x5e,0x5e,0xd3,0xb3,0x73,0x6f,0x56,0xbd,0x6c,0xfa,0xaf,0x26,0x3d,0xaf, + 0xa8,0x58,0xbc,0xe4,0x4b,0x91,0x48,0x64,0x64,0x68,0xc4,0xfa,0x5f,0x83,0x96,0x06, + 0x30,0xf9,0x6d,0xa1,0xdb,0x02,0x6f,0x41,0x23,0x08,0xd2,0x84,0x81,0xf3,0x5b,0xeb, + 0x36,0xed,0xda,0x8d,0x5e,0x2f,0x8e,0xf8,0xbd,0x63,0x54,0x36,0x13,0x99,0xc3,0x44, + 0x9c,0x95,0x93,0xcd,0x84,0x9f,0x65,0xc2,0xb3,0xe4,0xc9,0x2c,0x1a,0x07,0xe1,0xef, + 0x90,0x24,0xca,0x11,0x10,0xc9,0x16,0x47,0xfe,0x2e,0x8e,0xcc,0xae,0xd6,0xe7,0x16, + 0xaf,0x8e,0x67,0xd1,0xac,0x6c,0x59,0x28,0xcf,0x65,0xcb,0x8a,0x69,0x52,0x1c,0xc1, + 0x51,0xa8,0x6e,0x97,0x53,0x09,0x57,0x18,0xae,0x21,0x8c,0xa0,0x3a,0x34,0xde,0x31, + 0x2a,0x4b,0x1e,0x9e,0x55,0xcd,0xa5,0xa1,0xbc,0x6b,0x35,0x84,0x50,0x84,0x55,0x96, + 0x09,0x89,0x85,0x91,0x20,0xa4,0x61,0x34,0x11,0x42,0x9c,0x76,0xff,0x2c,0x19,0x0a, + 0x52,0x16,0xc2,0x33,0x4c,0xd8,0x29,0xe2,0x9a,0x81,0x10,0x70,0xcd,0x87,0x99,0xc0, + 0x5f,0x99,0xc0,0x43,0x8c,0xff,0x2f,0x8c,0xff,0x3e,0xb1,0xdf,0x0e,0xe2,0x88,0xc9, + 0xa4,0x78,0xa3,0xf5,0xc8,0x8c,0x0e,0x23,0x56,0xb6,0x1d,0x92,0x6e,0x35,0x08,0xbc, + 0xf0,0x02,0x61,0xbf,0x14,0x61,0xef,0x19,0x64,0x2e,0xec,0x9a,0x20,0x20,0x5e,0x38, + 0x56,0xb6,0xe8,0x47,0x57,0x89,0x47,0xc8,0xfc,0xcb,0xd7,0xff,0xd6,0xba,0x7f,0x6c, + 0x50,0x2a,0xa5,0x2f,0xb6,0x6c,0xdd,0xca,0x30,0x62,0x1e,0x8f,0x67,0x6c,0x6c,0x6c, + 0xd8,0xda,0x90,0xf8,0x5f,0x7d,0x03,0xbd,0x16,0x7a,0x30,0x05,0x26,0x1f,0x1c,0xc1, + 0xe7,0xaf,0x10,0x04,0x69,0xd2,0x7c,0x64,0xee,0xd8,0x61,0xec,0x56,0x26,0xee,0x32, + 0x13,0x93,0xcb,0xc4,0x5e,0x66,0xe2,0xaf,0x32,0x71,0x79,0x4c,0xec,0x15,0x26,0xfa, + 0x0f,0x12,0x82,0x04,0x00,0x09,0x57,0x18,0x73,0x89,0xca,0xaf,0x90,0x22,0x71,0xa0, + 0x93,0xcb,0xc4,0xe7,0x11,0x21,0x94,0x05,0x61,0x1c,0x5b,0x84,0x53,0x96,0xa8,0xe5, + 0x11,0x35,0x36,0x64,0xe5,0x20,0x8c,0xb9,0x2c,0x8e,0x23,0x49,0x71,0xdc,0x25,0xaa, + 0xc6,0xd6,0x90,0x2b,0xab,0x99,0x94,0xa5,0xad,0xb0,0x59,0xb2,0xb2,0x57,0xaa,0xeb, + 0xa9,0x51,0xe7,0x15,0x99,0x32,0x6b,0xa1,0xc2,0x4e,0xae,0x0e,0x54,0xce,0x5a,0x22, + 0xb3,0x47,0x6e,0x5e,0xf4,0x25,0x99,0x90,0x2d,0x28,0xeb,0xac,0x5c,0x27,0x26,0x17, + 0x8c,0x14,0x83,0x91,0xf1,0x97,0x69,0xc7,0x69,0xb5,0xa0,0x16,0xfd,0x87,0x38,0x36, + 0x57,0x1c,0x7d,0x11,0x92,0xe2,0xe8,0x0b,0xe2,0xa8,0x1c,0x26,0xf2,0x1c,0x21,0x9c, + 0x5e,0xab,0x10,0x8f,0x7c,0x92,0xdc,0x58,0x60,0x67,0xc7,0x7e,0xfb,0x18,0xdf,0x5d, + 0xcc,0x98,0xad,0xe4,0x4f,0xe4,0x91,0x6b,0xac,0x89,0x17,0x4e,0x13,0x0d,0xfa,0x12, + 0xe6,0xc2,0xc2,0xbe,0x73,0xc0,0x0b,0x5b,0xba,0x4c,0xb1,0x70,0x99,0x24,0x20,0x4b, + 0x94,0x44,0xf1,0x1d,0xc3,0x4d,0xed,0x03,0x7c,0x27,0x7c,0x5d,0xf0,0xf8,0xa9,0xd6, + 0xbd,0x64,0x03,0xf1,0xa2,0x4a,0x7a,0xe4,0xd8,0x71,0x47,0xa7,0xee,0xa6,0xa6,0x02, + 0x3e,0x5f,0x00,0x2e,0xd8,0xd0,0xd0,0x10,0x66,0xc1,0x2d,0x5b,0xb4,0x04,0xe7,0x8b, + 0x37,0x9f,0x11,0x04,0xf9,0x57,0xd0,0x4c,0xb7,0xb5,0xa8,0x87,0xf5,0xf8,0xc3,0xe2, + 0x84,0x9b,0xe2,0x49,0x37,0x28,0x7f,0x42,0x9c,0x99,0xf4,0x27,0x33,0x91,0xc4,0x99, + 0x89,0xd7,0x69,0x78,0x83,0x24,0x27,0xdf,0x94,0xe7,0x92,0xb8,0x4c,0x58,0xad,0xa3, + 0x1c,0xaa,0xcf,0x9a,0x74,0x83,0x2d,0xce,0xd6,0x46,0x1a,0x4a,0xf8,0x4b,0x6d,0x43, + 0xd5,0x95,0xb0,0x45,0xe4,0x91,0x5a,0xda,0xfd,0x7f,0xf6,0xae,0x04,0x28,0xaa,0x63, + 0x6b,0x57,0xfd,0x7f,0xa2,0x68,0x54,0x04,0x15,0x95,0x1d,0x66,0x98,0x61,0x53,0x14, + 0x17,0x10,0x71,0x21,0x8a,0x46,0x5f,0xf4,0x99,0xc4,0xbc,0x3f,0x31,0x9a,0xf8,0x34, + 0x89,0xbe,0x24,0x3e,0x05,0x44,0x86,0x31,0xc6,0x0d,0x17,0x16,0x41,0x56,0x51,0x54, + 0x44,0x11,0x10,0x45,0x40,0x01,0x51,0x41,0x10,0x14,0x35,0x88,0xca,0xa2,0x6c,0x82, + 0x6c,0xb3,0x30,0x0c,0xfb,0x3a,0xa0,0x55,0xff,0xe9,0xee,0x3b,0x97,0x11,0x99,0x71, + 0xa2,0x12,0x2b,0x29,0xca,0x53,0x63,0xdf,0xbe,0xdd,0xa7,0x4f,0x77,0xdf,0xdb,0x5f, + 0x7f,0x7d,0xfa,0x36,0x94,0x55,0xd8,0xc8,0x57,0x12,0x14,0xd3,0xf2,0x92,0x2a,0x52, + 0x65,0x9c,0xd7,0x68,0x33,0x95,0x5e,0x9a,0xb2,0x48,0xd6,0x12,0x1c,0x2f,0xab,0xaa, + 0x88,0x92,0x4d,0x85,0x08,0xdc,0xe1,0x17,0xcf,0x52,0xd8,0x3f,0xe5,0x18,0x6d,0xcc, + 0xc6,0x3c,0x1a,0xa8,0xfd,0x1d,0xc4,0x8b,0xbf,0x4d,0x61,0xae,0x49,0x06,0x46,0x8c, + 0xbc,0xdb,0x88,0x0e,0x47,0x30,0x56,0x84,0x1a,0xfc,0x23,0x58,0x7f,0xa9,0x9f,0xce, + 0x22,0x4f,0xed,0x8f,0xdd,0x74,0xec,0xb6,0x6b,0xdb,0x70,0x80,0x08,0xa3,0x23,0xb6, + 0x80,0x08,0x4f,0x59,0xa7,0x35,0x7d,0xed,0xe6,0x9d,0xa7,0xc4,0x8d,0xcd,0xef,0x1d, + 0x2b,0x07,0x42,0xf2,0x1e,0x17,0x2c,0xfd,0xf4,0xd3,0x09,0x13,0x27,0x82,0x68,0x68, + 0x4c,0x00,0xfc,0x55,0x57,0x53,0x1f,0x35,0x72,0x14,0xf1,0xff,0x0e,0x53,0x19,0x36, + 0x74,0xc8,0xe0,0xe6,0xab,0x41,0x19,0x94,0x41,0xf9,0xfb,0xcb,0x87,0x1f,0x0c,0x1d, + 0x63,0xfe,0xa5,0xd1,0x2f,0x79,0x2c,0xa7,0x4a,0xa3,0x2d,0xc5,0x6c,0xc7,0x32,0x04, + 0x5e,0x0e,0xe5,0x46,0x8e,0xcf,0xd0,0x2f,0x84,0x1d,0xcb,0xc9,0x25,0xcb,0xe1,0xa9, + 0x34,0x06,0x85,0x59,0x90,0x00,0x49,0x39,0x95,0xde,0xa1,0xcc,0xc8,0xb1,0x82,0x84, + 0x11,0xa4,0x42,0xb8,0xcf,0x25,0xd1,0x89,0x05,0x65,0x77,0x78,0x4a,0x15,0x01,0x19, + 0x5f,0x2e,0x48,0x56,0x95,0x6c,0x2e,0x1c,0x53,0x46,0xe5,0x92,0x5b,0xae,0xd4,0xec, + 0x3e,0xe5,0xd2,0x79,0xfb,0x15,0x9c,0x98,0xe5,0x54,0xce,0xda,0x5a,0xc9,0x72,0x2c, + 0x83,0xaa,0x81,0x48,0x6b,0x41,0x8a,0xab,0xc0,0x97,0x95,0xa8,0x5c,0x7c,0x97,0xe5, + 0x50,0x82,0x72,0xfd,0xb7,0x88,0xe5,0x50,0x0a,0xb7,0x5e,0x82,0x63,0x90,0xff,0xe4, + 0x23,0x82,0xbf,0x31,0x07,0xd1,0xe1,0x0d,0x39,0xcc,0x75,0x99,0xc8,0xc3,0x2e,0xcb, + 0x85,0x3f,0x0f,0x63,0xae,0x38,0x61,0xb0,0x34,0x48,0x7f,0xb1,0xaf,0xee,0x22,0xf4, + 0xf9,0xb0,0xce,0xbc,0x5f,0x35,0xad,0x9d,0x26,0xce,0xf8,0x19,0xb9,0x83,0x2d,0xd7, + 0xeb,0xcc,0xfc,0xe1,0x48,0xe8,0xe5,0x8e,0xbf,0xdd,0x47,0x49,0x35,0x3c,0xfe,0xb2, + 0xe5,0x9f,0x4d,0xd4,0xd4,0x99,0xa8,0xa9,0x0d,0xa2,0xa9,0xa5,0x3d,0x76,0xec,0x38, + 0x80,0xe0,0xd1,0xa3,0x47,0x03,0xfe,0x02,0x05,0x7e,0xef,0x6f,0xc4,0xa0,0x0c,0xca, + 0xa0,0x0c,0xca,0x9f,0x29,0x13,0x6c,0x1d,0x11,0x26,0x3a,0xd7,0x80,0xb0,0x01,0x83, + 0xb6,0x56,0x21,0xc1,0x97,0x83,0xf2,0x8a,0x54,0xbf,0xd4,0x38,0x10,0x76,0xc4,0xc0, + 0xed,0x54,0xc1,0x72,0x7a,0x86,0x29,0x73,0xb1,0x11,0x8d,0xc8,0x40,0x8d,0x37,0x3e, + 0x42,0xab,0xd6,0xc4,0xdd,0xbc,0xfe,0x16,0xb5,0x28,0xfd,0x55,0x2c,0xf3,0x5f,0xe7, + 0x18,0x2b,0x4e,0x31,0x96,0x87,0xe8,0x2f,0xf6,0x47,0xc7,0x7a,0x2c,0xdc,0xab,0x3d, + 0x9f,0xab,0x3d,0x87,0xa3,0x69,0xe5,0x30,0x61,0xc6,0x26,0x8d,0x69,0x3f,0x30,0xe6, + 0x6e,0x3a,0x7a,0x36,0xf9,0xef,0xf4,0x45,0x52,0x5d,0x7d,0x9d,0xeb,0xf6,0x1d,0xba, + 0xfa,0xfa,0xda,0xba,0xba,0x7a,0x7a,0xfa,0x9a,0xda,0x3a,0x5a,0xda,0xda,0x63,0xc7, + 0x69,0x00,0x04,0xab,0x8d,0x56,0x23,0x5b,0xa0,0x87,0x7c,0x38,0x64,0xf0,0xfc,0x2b, + 0x65,0x64,0xe8,0x87,0x43,0xd5,0x54,0xd5,0x0c,0x0d,0x19,0x33,0x67,0x5a,0xad,0x58, + 0xf1,0xd9,0x86,0x0d,0xff,0x71,0x74,0x72,0x76,0xe1,0x6c,0x77,0x76,0xde,0xb6,0x61, + 0xc3,0x4f,0x2b,0x57,0x7e,0x69,0x63,0x63,0x6b,0xc4,0x62,0xa9,0xab,0x8d,0x51,0x19, + 0xa2,0xf2,0xde,0xad,0x1d,0x94,0x41,0x19,0x14,0x79,0xa2,0x32,0x4a,0x5b,0x67,0xc5, + 0x09,0xd6,0x36,0x3e,0x6b,0x1b,0x0f,0x84,0xed,0x22,0x40,0x01,0xc0,0x62,0x17,0x01, + 0x0a,0x3b,0xa3,0x30,0x15,0x2f,0x8b,0x44,0x38,0x86,0x4a,0x23,0x9b,0x57,0xe6,0x16, + 0x8e,0xe7,0xf7,0xcd,0x2e,0x93,0xb8,0x6f,0x7a,0xd9,0x94,0x7d,0x02,0xd2,0x4b,0xca, + 0x3c,0x10,0xfa,0x52,0xe6,0xb7,0xf7,0x2e,0x29,0x9a,0xca,0xd5,0x1b,0x23,0x63,0x06, + 0xef,0xa5,0xbb,0x32,0x05,0x51,0x97,0x74,0x59,0xfd,0x56,0xff,0x55,0x5c,0x46,0xd0, + 0x8c,0xd0,0x99,0xed,0x84,0x19,0xf7,0x96,0x12,0x6a,0xa5,0x1a,0xb9,0xb6,0xf3,0x99, + 0x1b,0x1e,0x20,0x2e,0xfc,0x7d,0x16,0xb5,0x83,0x7a,0x75,0x22,0xfa,0x4a,0x6b,0xe5, + 0x59,0xc6,0x8a,0x93,0x06,0x9f,0x06,0xa1,0x7d,0x59,0xf6,0xfb,0xd1,0xd1,0x97,0xb6, + 0x2e,0x9a,0xe8,0x03,0xa5,0x9f,0x34,0x2c,0x37,0x18,0xdb,0x3b,0xdc,0xbd,0x9f,0xdf, + 0xfd,0xb7,0xd8,0x0e,0xdd,0xfd,0xbc,0xdb,0xd7,0x2f,0xc0,0xc8,0x88,0xad,0xc3,0x60, + 0x80,0x18,0x32,0x0c,0x75,0x0c,0x19,0x3a,0xba,0xba,0x13,0x26,0x6a,0x8d,0x1b,0x37, + 0x4e,0x5d,0x5d,0x5d,0x55,0x55,0x95,0x3e,0x82,0x83,0xa0,0xf0,0xa0,0x2f,0xb8,0x5f, + 0x19,0x35,0x72,0xd4,0xac,0x59,0x36,0x9b,0xb7,0x38,0xc4,0xc5,0x5f,0x2e,0x2a,0x29, + 0x6d,0x6a,0x6e,0xea,0x92,0x48,0x7a,0x5e,0xc8,0xb4,0xf6,0x8b,0xe7,0x12,0x49,0x77, + 0x53,0x73,0xf3,0xd3,0xf2,0x8a,0x84,0x2b,0xc9,0xdb,0x7f,0xdd,0x69,0x6f,0xbf,0x08, + 0xc0,0xfa,0xbd,0x5b,0x3e,0x28,0x83,0x32,0x28,0xfd,0xca,0x47,0x1a,0x26,0xac,0x4d, + 0x05,0x08,0x9e,0x38,0x42,0x82,0x62,0xa6,0xae,0x7c,0x63,0x97,0x5e,0x7c,0xa1,0xf1, + 0x51,0x8a,0x89,0x04,0xcb,0xf8,0xb2,0x38,0x0b,0x79,0x09,0x58,0x4b,0x71,0x99,0x2f, + 0x05,0x41,0x2a,0x31,0x05,0x82,0x94,0xc2,0x57,0xee,0xf6,0x29,0x08,0xb4,0x6d,0xe3, + 0xcb,0x96,0x4b,0x03,0x3d,0xc9,0x8b,0x8b,0xab,0x91,0x01,0x53,0xbe,0x34,0x25,0xad, + 0x53,0x40,0x83,0x66,0xef,0x24,0x41,0x9e,0xe6,0xbe,0x20,0x4e,0x9a,0x82,0x4f,0x27, + 0x86,0xaa,0xf5,0xd6,0xd7,0xf9,0xa5,0x96,0x91,0x69,0x16,0x52,0x41,0x84,0xc5,0x6c, + 0x67,0x4c,0x8d,0x1d,0xcb,0x7b,0xb9,0x30,0x46,0x61,0xa3,0x0d,0xf7,0x98,0xeb,0x33, + 0x99,0x6b,0x53,0x99,0xab,0xaf,0xa0,0x4f,0x89,0xbf,0x88,0x64,0x7e,0x7e,0x8a,0xf1, + 0xe9,0x31,0xdd,0x45,0x87,0xb5,0xed,0xdd,0xd1,0x07,0x4a,0xb6,0xae,0xda,0xd6,0x4e, + 0xf8,0xcf,0x3f,0x6d,0x9c,0xbf,0x6a,0x57,0x5e,0x49,0xd5,0x7b,0x47,0xcf,0xb7,0x97, + 0xdc,0xfc,0x7c,0xdb,0x39,0xb6,0x00,0xbb,0x4c,0x26,0x8b,0x09,0xc4,0x8c,0xc5,0xd2, + 0x63,0xb2,0xf5,0x0d,0xf5,0x81,0x02,0x8f,0x1f,0x8f,0x76,0x61,0x11,0x17,0xf0,0xf0, + 0x61,0xc3,0x01,0x76,0xdf,0xd5,0xf9,0x1b,0x13,0xc6,0x4f,0xfc,0x6d,0xf7,0x1e,0xaf, + 0x43,0xde,0x20,0x87,0x0f,0xfb,0xfa,0xfa,0x05,0x06,0x04,0x1d,0x09,0x08,0x44,0x12, + 0x18,0x84,0x24,0xe8,0x48,0xaf,0xf8,0xfa,0xf9,0xcf,0x99,0x33,0x5f,0x49,0xea,0x0d, + 0x76,0xae,0x5b,0xb7,0xfe,0x90,0xb7,0x8f,0xb7,0xcf,0x61,0xc8,0x08,0x9a,0xfd,0x03, + 0x40,0x8e,0xf8,0x05,0xf4,0xd5,0x0c,0x65,0xc1,0xef,0x7f,0x37,0x3b,0x8e,0xfc,0x68, + 0xe4,0xdb,0xd4,0x05,0xda,0x84,0xc9,0x34,0x5a,0xbb,0xee,0xfb,0xc4,0xe4,0x64,0x3e, + 0x5f,0xd8,0xde,0xd9,0xde,0xf3,0x42,0xa9,0x89,0x59,0xa7,0xa4,0xab,0x4e,0x5c,0x9f, + 0x9e,0x91,0xe1,0xbc,0x8d,0x63,0x6e,0x66,0x3e,0x5c,0x65,0xf8,0x9b,0x19,0x00,0x2d, + 0xf3,0xed,0x77,0x6b,0xbd,0x7d,0x7c,0xa1,0xca,0xde,0xf0,0x9f,0x5f,0x40,0x00,0xae, + 0x29,0xa9,0x60,0x1f,0x09,0x08,0xea,0x27,0x52,0x81,0x40,0xeb,0x7d,0xba,0xfc,0x9f, + 0xb2,0xc5,0x99,0x9a,0x98,0x41,0xcb,0x7a,0x7a,0x41,0x0b,0xfb,0xf9,0xf9,0x05,0xf8, + 0xf9,0xfb,0xd3,0x05,0xc9,0x96,0xa8,0xb8,0x20,0x79,0x77,0x89,0x86,0x80,0x57,0xba, + 0xc9,0xcf,0x3f,0x60,0xa1,0xfd,0xe2,0x81,0x1b,0x66,0x57,0xaf,0xf9,0x16,0x3f,0x8d, + 0x87,0x7d,0x0e,0xa3,0x4a,0x05,0x06,0x06,0xf9,0x07,0xca,0x35,0xd2,0xd1,0x69,0xeb, + 0x18,0xf5,0xb1,0x4a,0x6a,0x36,0x33,0x33,0x77,0xdb,0xb7,0xdf,0xc3,0xf3,0x10,0xe8, + 0x87,0x5a,0x80,0x66,0x05,0xcd,0xe2,0xe1,0xe1,0x69,0x6a,0x62,0xaa,0x58,0xe1,0xd8, + 0xb1,0xe3,0x7e,0xdd,0xf1,0x9b,0xd7,0x21,0xea,0x09,0x47,0xd6,0x06,0xf5,0xf3,0x78, + 0xcb,0x6d,0xf9,0x57,0x9e,0x8a,0x7e,0x5f,0x3a,0xdc,0xe6,0x81,0xf3,0xe7,0xdb,0x29, + 0xb0,0x44,0x4f,0x4f,0x7f,0xc7,0xce,0x5d,0x50,0x2f,0x6c,0x48,0x00,0xd8,0x41,0xf4, + 0xf4,0x6b,0x06,0xbc,0xe6,0xb6,0xb3,0x6d,0x95,0x6c,0x34,0x7d,0x3d,0xfd,0x5d,0xbb, + 0xf7,0xc0,0xb8,0x00,0x4f,0x17,0x98,0x41,0x2a,0xd8,0xcf,0xc3,0x09,0xdd,0x14,0x10, + 0x08,0xcf,0xbb,0xfd,0xe2,0x01,0x7b,0x36,0xfe,0xf7,0xc3,0xf1,0x36,0x9b,0x58,0x8e, + 0xcf,0xd8,0x2e,0x42,0x36,0x47,0x04,0xbf,0xc6,0xdc,0x3a,0x63,0xd7,0x3a,0xb6,0x54, + 0x4c,0x5d,0x05,0xc6,0x1c,0x3e,0x04,0x58,0x9c,0x5a,0x12,0x63,0xee,0x0a,0x40,0x56, + 0x6b,0xc2,0xe1,0xa3,0x18,0x8e,0xc8,0xc4,0x55,0x00,0x97,0xe6,0xdc,0x1a,0x3a,0xb1, + 0x09,0x07,0xc5,0x20,0x6d,0xd2,0xc4,0x6c,0x57,0x11,0xb9,0x04,0x31,0xe3,0xf2,0x8d, + 0x5d,0x6b,0x51,0x2e,0x5a,0x15,0x17,0x69,0x06,0x0d,0xa4,0x08,0x08,0x98,0xa0,0x12, + 0x51,0x16,0x9c,0x58,0x84,0x2e,0x51,0x76,0xa2,0xb0,0x9a,0xe4,0x25,0x62,0xe2,0x2a, + 0x84,0x42,0x71,0x7a,0x62,0x5b,0x35,0xa4,0x34,0x46,0x06,0x08,0xe9,0x34,0x28,0x92, + 0xe4,0xe5,0x52,0xc5,0x81,0x4e,0xd0,0x0c,0x91,0x94,0x19,0xd8,0x78,0xfa,0x97,0x24, + 0xa3,0x12,0xbb,0xf6,0xea,0xc1,0x22,0x02,0xf6,0x4d,0x6a,0xc7,0x72,0x11,0x62,0xcc, + 0xed,0x65,0xcd,0xb2,0xa4,0x98,0xbd,0xb5,0x82,0xf8,0x94,0xf1,0xf6,0x2d,0x84,0xc2, + 0xac,0x9f,0x1e,0xa1,0x2d,0xd3,0xdf,0xe3,0xdd,0x59,0x6b,0xae,0xa1,0xf3,0x3d,0xfe, + 0x15,0xcd,0xfc,0x3c,0x8c,0xb1,0xec,0x98,0xfe,0x12,0x5f,0xdd,0xc5,0xee,0xda,0x76, + 0x7b,0xb5,0xe7,0x72,0xb5,0xac,0x1c,0x35,0x67,0xfe,0x32,0x7e,0xfa,0x46,0xae,0x67, + 0x78,0xbb,0xa4,0xfb,0xbd,0x03,0xe8,0xdb,0x08,0x80,0xc5,0xee,0x3d,0x7b,0xd9,0x6c, + 0x13,0x23,0x23,0x13,0x36,0xdb,0xd8,0xcc,0xcc,0xcc,0xc4,0xc4,0x84,0xc5,0x62,0x1b, + 0x30,0x0c,0x35,0x75,0x34,0x09,0xfe,0x8e,0x1c,0x81,0xbe,0x02,0xa6,0xf7,0x5f,0xbd, + 0x93,0x5d,0x58,0xc6,0xc6,0xc6,0x77,0xee,0xde,0x3b,0x77,0xfe,0x42,0x42,0xd2,0xb5, + 0xbc,0x82,0xc7,0x02,0x61,0x6d,0x17,0xb4,0xe4,0x8b,0xfe,0x8d,0x04,0x9c,0xda,0xb5, + 0x7b,0xb7,0x92,0x3e,0xe8,0xd1,0xa3,0x46,0x87,0x47,0x44,0xc6,0xc6,0x5d,0xba,0x10, + 0x7b,0xe9,0xee,0xbd,0xfb,0x95,0x55,0xd5,0xad,0x6d,0x8a,0x00,0x31,0xfb,0xc1,0xfd, + 0xf1,0xe3,0xc6,0xbf,0x71,0x45,0xd4,0xd5,0xd4,0x57,0x7d,0xb3,0x26,0xe3,0xf6,0xad, + 0xe6,0xd6,0xd6,0x37,0xee,0x85,0xce,0xae,0xce,0x47,0x79,0xb9,0x5b,0x9d,0x39,0x5a, + 0x5a,0x6f,0xf2,0x17,0xa6,0x54,0x86,0xaa,0x84,0x9d,0x09,0xbf,0x9c,0x90,0x74,0x31, + 0x2e,0xfe,0xde,0xef,0xd9,0x95,0xd5,0x35,0xed,0x1d,0x9d,0xef,0xcc,0x3f,0xf2,0xe2, + 0xf9,0xf1,0x13,0x27,0x65,0x8b,0xfb,0xe7,0x8a,0xcf,0xa0,0x94,0xa8,0x73,0xe7,0x53, + 0x52,0x33,0x8b,0x8b,0x4b,0x1b,0x1a,0x5b,0xfe,0x84,0x63,0xd2,0x25,0x3d,0xdd,0x1e, + 0x5e,0xde,0x03,0x35,0xc6,0xfe,0xcf,0x07,0x61,0xe1,0x67,0x12,0xaf,0x5c,0xb9,0x10, + 0x1b,0x9f,0x75,0x2f,0xbb,0xb2,0x92,0xd7,0xdc,0xd2,0xa2,0xe0,0x99,0x79,0x98,0x9b, + 0xcb,0x64,0x18,0x29,0xa9,0xf9,0x8b,0x95,0x5f,0xa4,0xa6,0xa5,0x9d,0x8d,0x8c,0x4e, + 0x4d,0xcb,0x7c,0x52,0x54,0x5a,0xdf,0xd0,0x04,0x75,0x91,0xa7,0xb9,0xb9,0xb5,0x65, + 0xe5,0xca,0x95,0xaf,0x79,0x77,0xd8,0xc6,0xb7,0x6e,0x67,0x45,0x46,0xc5,0x24,0x26, + 0x5d,0x7b,0x94,0x57,0x28,0x12,0x89,0xe1,0x05,0x19,0xa0,0x66,0x07,0xa0,0x57,0x60, + 0xc9,0xac,0x59,0x36,0x59,0x77,0xef,0x87,0x9e,0x09,0x4f,0xba,0x7a,0xbd,0xe0,0x71, + 0xa1,0xa8,0x4e,0x2c,0xe9,0x96,0x5b,0xb5,0x4e,0x89,0x84,0xbb,0x7d,0x87,0x92,0x8d, + 0xb6,0xf6,0xdf,0xeb,0x8a,0x4b,0x4a,0x0b,0x1e,0x17,0x09,0x6b,0xc5,0x5d,0xf2,0xc7, + 0xd8,0xee,0x1e,0x74,0x5e,0x01,0x74,0xd6,0xe6,0x2d,0x0e,0x03,0xf7,0x6c,0x0c,0x1f, + 0x39,0xc1,0xe0,0xab,0x28,0x29,0xc2,0x8a,0x64,0xa4,0x8e,0x0e,0x98,0x6d,0x17,0x00, + 0x2e,0x9b,0x6f,0xe7,0x41,0x1a,0x94,0x8c,0x2b,0x36,0xe5,0x0a,0xe1,0x92,0x04,0xe0, + 0x97,0xc2,0x26,0xea,0x56,0x2d,0x44,0x82,0x90,0x4b,0x3a,0x6f,0xaf,0x66,0x3a,0x17, + 0x17,0xe5,0xa2,0x52,0xba,0x8a,0x00,0x97,0x21,0x31,0xc6,0x71,0x3e,0xbe,0x8b,0x04, + 0x6e,0x11,0x6d,0x18,0xa6,0x21,0x6f,0x1d,0xca,0x4b,0x12,0x03,0x7c,0x63,0x85,0x10, + 0x03,0x45,0xa0,0x4b,0x50,0xc8,0x15,0x23,0x84,0xe5,0xa2,0x78,0x0c,0xa9,0xc8,0x2a, + 0xfa,0x2e,0xd2,0xe6,0xca,0x27,0xb9,0x88,0x66,0x52,0x04,0x6d,0x1b,0xb1,0xb9,0xb7, + 0x68,0x57,0x01,0x0b,0x43,0x39,0x41,0x67,0x84,0xb9,0x48,0x04,0x74,0x00,0x01,0x3d, + 0x47,0x68,0xee,0x5a,0x05,0xa0,0xdc,0x97,0x1d,0x13,0x97,0x3a,0xa0,0xb0,0x43,0xa9, + 0x91,0x43,0x19,0xde,0x2c,0x5d,0xc0,0xfc,0xf1,0x3e,0xfa,0xe2,0x98,0x1c,0xeb,0xb1, + 0x3a,0xc9,0xe8,0xff,0xa2,0x99,0x2b,0x23,0x18,0xcb,0x43,0xf4,0x16,0xf9,0xa2,0x3f, + 0xf4,0xb0,0x60,0xa7,0xf6,0x6c,0x8e,0xb6,0x8d,0xf3,0xf8,0x69,0x1b,0xa7,0x2c,0xd9, + 0x76,0x2f,0xf7,0x99,0x3c,0xd4,0xf8,0x4b,0x48,0xc6,0xad,0xdb,0x53,0xa7,0x5a,0x02, + 0xe0,0x02,0xf2,0x4e,0x9e,0x6c,0x61,0x32,0x69,0xaa,0xb9,0xb9,0x39,0x84,0x81,0xd0, + 0x69,0x33,0x58,0x13,0xb5,0xb4,0x34,0x34,0x34,0xc8,0x16,0x2c,0xb2,0x0b,0x1a,0x86, + 0xfa,0x77,0x72,0x0a,0x07,0x83,0xc1,0xb8,0x7a,0x3d,0xe5,0xc0,0x41,0xcf,0xc0,0xa0, + 0x90,0xf4,0x8c,0xdb,0xe5,0x15,0x55,0xed,0x1d,0x1d,0xf2,0x46,0x3c,0x49,0x8f,0x04, + 0x66,0xfb,0x40,0x6c,0x95,0xd1,0x3c,0x72,0xc4,0xa8,0xa0,0xe0,0xa3,0xfe,0x41,0xc7, + 0xdc,0xbd,0x7c,0xe2,0x13,0xae,0x3c,0x2e,0x2c,0x6e,0x6c,0x6a,0x92,0x74,0xcb,0x1d, + 0x4b,0x0b,0x9e,0x3c,0xd1,0xd5,0xd1,0x7d,0x83,0x2a,0xc0,0x7c,0xe0,0x93,0xc5,0x9f, + 0xa4,0x65,0x64,0xbc,0xab,0x13,0xc2,0xbb,0x9f,0xf7,0x14,0x95,0x94,0x7e,0xb3,0xfa, + 0x3b,0x75,0xb5,0x31,0x7f,0xc8,0x12,0xe8,0x97,0x90,0x13,0x27,0x8e,0x1e,0x0f,0x39, + 0xec,0x1d,0x1c,0x13,0x9b,0xf0,0xb8,0xb0,0xb4,0xb1,0xa9,0x45,0xf2,0xee,0x30,0xf1, + 0x6c,0xe4,0x39,0xd9,0xe2,0x16,0x7c,0xbc,0x20,0x25,0xfd,0xc6,0xbe,0x03,0xee,0xa7, + 0x4e,0x47,0x66,0xdd,0xcd,0xae,0xe1,0xf3,0x25,0x92,0xe7,0x03,0xbd,0x1d,0xa2,0xe7, + 0xc5,0xf3,0x90,0x13,0xa1,0x03,0x37,0xc6,0x06,0x04,0x1d,0x0b,0x39,0x7e,0x12,0xf8, + 0xef,0xc5,0xb8,0x24,0x00,0xb5,0xc6,0xc6,0x66,0x05,0x87,0xed,0x14,0x14,0x3e,0x31, + 0x66,0x9b,0x28,0xa9,0x79,0xd9,0xb2,0x65,0x30,0x2f,0xda,0xed,0xe6,0x7e,0x26,0x22, + 0x0a,0x9a,0x4b,0x58,0x2b,0xea,0x90,0xff,0xe7,0x4d,0x3b,0xba,0x24,0xdf,0xfd,0x7b, + 0xbd,0x62,0x85,0x06,0x06,0x8c,0x94,0x1b,0x69,0x7b,0x0f,0xb8,0x1f,0x0d,0x09,0x4d, + 0x4d,0xbb,0x09,0xd3,0xad,0xb6,0xf6,0xf6,0x01,0x6a,0x76,0x20,0xee,0x0a,0x5e,0xf6, + 0x69,0x96,0xd3,0x6e,0x66,0x64,0xfc,0xba,0xcb,0x2d,0xe4,0xc4,0x99,0xf4,0x8c,0x3b, + 0xd5,0x3c,0x7e,0x6b,0x5b,0x9b,0x82,0x1e,0xf4,0x52,0x6e,0x06,0x35,0x5c,0x65,0x78, + 0x5c,0xfc,0xe5,0xcc,0xac,0xbb,0x39,0x0f,0x61,0x66,0x2e,0xea,0xe8,0xec,0x92,0x37, + 0xc6,0x76,0xf7,0xf4,0x00,0xf8,0x3e,0x29,0x2c,0x9e,0x62,0x31,0x75,0xe0,0x9e,0x0d, + 0x10,0x55,0x03,0x3b,0xd6,0xe6,0xc7,0x08,0x41,0x5c,0x10,0xd6,0x00,0x78,0x01,0x0e, + 0x9a,0x72,0x90,0xa7,0x15,0x63,0x2b,0x0d,0xc7,0x04,0x2e,0x05,0x14,0x58,0x13,0xe4, + 0xe2,0x02,0x09,0x45,0x94,0x16,0x2e,0x09,0x48,0xf5,0x42,0x1b,0x86,0x4b,0x1a,0xda, + 0xa4,0x18,0x5a,0x47,0x40,0x1c,0xa8,0x25,0xca,0x45,0x53,0x4b,0xba,0x20,0x29,0x28, + 0x9b,0x70,0x78,0x00,0x7f,0xd2,0x52,0x08,0x10,0x03,0x75,0xa5,0x26,0x00,0x94,0x49, + 0xbd,0xe6,0x91,0xcb,0x3a,0x5c,0x05,0x11,0xad,0x93,0x32,0xa3,0xd7,0x7e,0x12,0xdf, + 0x1b,0xc6,0x6a,0x05,0x32,0x91,0xc0,0xbb,0x85,0x50,0x23,0xc2,0xb8,0xb1,0x91,0x54, + 0x45,0x28,0x86,0x8e,0x27,0x1b,0x04,0xd9,0x81,0xec,0x4b,0xb9,0xb6,0x88,0x64,0x24, + 0xab,0xd6,0xf4,0x62,0x3b,0x85,0xc5,0x5b,0x2b,0xd8,0x4e,0xe5,0xd4,0xee,0x2c,0xbc, + 0x4d,0x9a,0x85,0x88,0xf0,0x5d,0xe6,0xda,0x74,0x74,0x6a,0xc7,0x57,0xb1,0xe8,0x1b, + 0xe1,0x15,0xa7,0x0c,0x96,0x04,0xe9,0x2e,0xf2,0x42,0x7f,0x53,0x69,0x0e,0x47,0xcb, + 0xda,0x51,0xd3,0xea,0xe7,0x1f,0xb8,0xc7,0x1b,0x1a,0x5b,0x7b,0xfe,0x9a,0x10,0xdc, + 0xd8,0xdc,0x08,0xf3,0x46,0x63,0x63,0x13,0x53,0x73,0x0b,0x33,0x8b,0x69,0x96,0x96, + 0xd3,0x2d,0x2c,0x67,0x98,0x4e,0x99,0x31,0xc9,0x62,0x2a,0x70,0x61,0x43,0x86,0x91, + 0x96,0x9e,0x8e,0x86,0xc6,0x04,0x35,0x35,0xb5,0x57,0xf1,0x17,0xb9,0x83,0x3f,0x78, + 0x73,0x14,0xd6,0xd3,0xd5,0x4b,0xb9,0x71,0x63,0xff,0x41,0x0f,0xdf,0x80,0xe0,0x1b, + 0x69,0x99,0xe5,0x15,0x95,0x30,0x86,0xc8,0xc3,0x5f,0x00,0xa6,0xe0,0x63,0x21,0x23, + 0x86,0x8f,0x50,0x46,0xf3,0x47,0xc3,0x47,0x78,0x79,0xfb,0x04,0x05,0x1f,0x3f,0xe8, + 0xe9,0x13,0x1b,0x9f,0x98,0x9b,0xff,0x58,0x31,0xfe,0x3e,0x2d,0x7b,0xc6,0x64,0x30, + 0xff,0xa8,0xfd,0x30,0x2d,0x71,0x70,0x74,0x2a,0x2b,0x2f,0xef,0xea,0xea,0x06,0xdd, + 0xef,0xb0,0x53,0x6a,0x45,0xe2,0xc0,0x23,0xc1,0x86,0x06,0x86,0x7f,0x68,0x92,0xe3, + 0x17,0x14,0x74,0x3c,0x34,0xcc,0xd3,0xdb,0x3f,0x26,0x2e,0x31,0xaf,0xa0,0xa8,0xbe, + 0xb1,0x49,0xc9,0x35,0xf0,0xd7,0x0a,0xd4,0x2e,0x2e,0xfe,0x92,0x6c,0x59,0x36,0x36, + 0xb6,0xe9,0x99,0x19,0x6e,0xfb,0xdc,0x43,0xc3,0xc2,0x33,0x6e,0x67,0xd7,0xf0,0xf8, + 0x30,0x03,0x19,0xe8,0x57,0x00,0xf4,0x47,0x44,0x45,0x0d,0xdc,0x00,0x7b,0xc0,0xc3, + 0xe3,0xe4,0xa9,0x53,0x18,0x7f,0x13,0x1f,0xe6,0x3d,0x01,0xfc,0x85,0xb1,0x5d,0xde, + 0xa4,0xa2,0xb4,0xac,0x4c,0xf9,0x01,0x7f,0xa1,0xfd,0xa2,0xb8,0x4b,0xf1,0xbb,0xf6, + 0x1e,0x0c,0x0d,0x8b,0xcc,0xbc,0x9d,0x2d,0x50,0x88,0xbf,0x5d,0xdd,0x92,0x1f,0x37, + 0x6c,0x54,0xac,0x50,0x5b,0x4b,0x27,0xf9,0x5a,0xca,0x7e,0x77,0xcf,0xc0,0xe0,0x13, + 0xd7,0xae,0xa7,0xc3,0xdc,0x15,0xad,0xf0,0x0c,0xcc,0xfc,0xc7,0x2f,0x20,0x48,0x81, + 0xcb,0xc9,0xdc,0x7c,0x52,0xca,0x8d,0xd4,0x1d,0x3b,0xf7,0x04,0x1d,0x3d,0x71,0x23, + 0xfd,0x16,0x5e,0x78,0x91,0x3b,0x13,0x80,0x1e,0x0c,0x08,0x08,0x52,0xa6,0xc5,0xa6, + 0x4f,0x9b,0xfe,0x28,0x37,0x0f,0x86,0x85,0xa2,0x92,0xf2,0x86,0x26,0x45,0x4f,0x72, + 0x7b,0x47,0x67,0x73,0x73,0xcb,0xd9,0xb3,0x91,0xaa,0x23,0x55,0x07,0xee,0xd9,0x00, + 0x19,0xa2,0xa2,0xaa,0xbb,0xdc,0x17,0x3b,0x3d,0x6b,0x09,0x12,0x01,0x61,0x04,0xac, + 0x34,0x77,0x45,0x88,0x43,0xb0,0x15,0x68,0x20,0x01,0x1d,0x7a,0xb9,0x98,0x60,0x31, + 0x5a,0x70,0xc6,0x64,0xd3,0x18,0xd0,0x87,0x4b,0xc5,0x93,0x95,0x61,0xb6,0x34,0x2f, + 0x0d,0x91,0x88,0xb4,0x72,0xf9,0x38,0xa5,0x98,0x5e,0x25,0xc6,0xb8,0x46,0x2d,0xf3, + 0x22,0xfe,0xcb,0x01,0xc8,0xa3,0xd2,0x93,0xb2,0x30,0x93,0xad,0x46,0x3a,0x09,0xab, + 0xc5,0x34,0x1c,0x2f,0x65,0xf3,0xa4,0x3c,0xb7,0x1a,0x2b,0x47,0xe9,0xb1,0x49,0xa4, + 0x68,0x1a,0x40,0x45,0xc6,0x32,0xf8,0x8b,0xd6,0xab,0x5d,0x85,0x38,0x2f,0x21,0xd4, + 0x62,0x52,0x0a,0x5a,0xca,0x86,0xbc,0xae,0x78,0x46,0xc1,0x15,0x99,0x63,0x72,0x4d, + 0xda,0x01,0x13,0x6d,0x0c,0xd0,0xc8,0xb6,0x3a,0xc2,0xa3,0xe9,0x2a,0x60,0x1b,0x70, + 0x0c,0x2e,0x17,0x4d,0x63,0x38,0x98,0x1a,0xcb,0xfa,0x8b,0xd1,0x06,0xad,0x4a,0xe4, + 0x14,0xde,0x5c,0xdc,0xbb,0x2f,0xeb,0xfb,0xbb,0x46,0xeb,0x6f,0xa2,0xcf,0x84,0x57, + 0x25,0x30,0x3f,0x0f,0x07,0x16,0x6c,0xb0,0x34,0x50,0x77,0x91,0x07,0xda,0x14,0x3d, + 0x0f,0xed,0x88,0x36,0x5b,0xb8,0x35,0xe5,0xd6,0xa3,0xbf,0x28,0xfe,0x5e,0x4e,0x48, + 0xb0,0xb2,0xb2,0x36,0x33,0x33,0xb7,0xb4,0x9c,0x36,0x63,0xa6,0xd5,0x4c,0x2b,0x6b, + 0x90,0x19,0x33,0x66,0x4e,0x9a,0x62,0x69,0x62,0x6e,0xc1,0x60,0x30,0x75,0x0c,0x19, + 0x13,0x26,0x4c,0x20,0xbb,0xb0,0xc8,0x12,0x34,0xc1,0xdf,0xb7,0xf7,0x02,0x6b,0x4e, + 0xd4,0x4c,0x48,0x4a,0x72,0xf7,0xf0,0x0e,0x08,0x3a,0x72,0x35,0x25,0xed,0x69,0x79, + 0x65,0x4b,0x6b,0x9b,0xbc,0x59,0x2e,0xbc,0x80,0x61,0xa7,0x4f,0x03,0xb1,0x55,0x46, + 0xf3,0xf0,0x61,0x1f,0x79,0x78,0x7a,0x1d,0x0b,0x0d,0xdd,0x7f,0xd0,0xfb,0xc2,0xc5, + 0x04,0xe0,0x32,0xf5,0x0d,0x0d,0x0a,0x16,0x48,0x79,0x02,0xbe,0xa9,0xe9,0x6b,0x3c, + 0x6e,0x7d,0x44,0x6b,0xa2,0xd6,0xe9,0x33,0x67,0x1a,0x1a,0x1b,0x3b,0x3b,0x95,0xc2, + 0x1d,0x40,0x7f,0x2c,0xdd,0x5d,0x12,0x09,0x04,0xd0,0xbf,0xe7,0x88,0x30,0x42,0xde, + 0x7e,0xb3,0x4b,0x7a,0xba,0x53,0xd3,0xd2,0xad,0xad,0xac,0x95,0xdf,0xe7,0xb6,0xff, + 0xa0,0x7b,0xd8,0x99,0x70,0x0f,0x2f,0x9f,0xe8,0x0b,0xf1,0x05,0x8f,0x9f,0x88,0xeb, + 0x9b,0x24,0x3d,0x4a,0xe1,0xaf,0x32,0xe3,0x76,0xda,0xcd,0x0c,0xd9,0xb2,0x2c,0xa6, + 0x4c,0xbd,0x73,0xef,0x77,0xb7,0x03,0xee,0xc7,0x43,0xc3,0x33,0x6f,0xdf,0x05,0xfc, + 0xed,0xe8,0xe8,0x1c,0xd0,0x55,0x20,0xd2,0x5c,0x71,0x09,0xf1,0x03,0x37,0xc0,0xee, + 0xda,0xb3,0xf7,0xf4,0x99,0xb3,0x07,0x3d,0xbd,0xcf,0xc7,0xc4,0x3e,0x78,0x94,0x5f, + 0x57,0x5f,0xdf,0xfd,0x5c,0xee,0xb2,0x67,0x35,0xaf,0x66,0xd6,0x2c,0x1b,0x25,0x35, + 0xcf,0xb2,0xb6,0xb9,0x9c,0x90,0xb8,0x7b,0xef,0xfe,0x93,0xa7,0x22,0x32,0x32,0xef, + 0xf0,0x04,0xa2,0x56,0xf9,0x74,0x15,0x7a,0xcd,0x69,0xeb,0x36,0xc5,0x0a,0xc7,0x8e, + 0x1b,0x7b,0x29,0x31,0xc9,0xdd,0xcb,0x27,0x20,0xe8,0x78,0xf2,0xd5,0xd4,0xb2,0x67, + 0x18,0x7f,0x07,0xa6,0xfd,0x4f,0x85,0x85,0x29,0xf0,0xfb,0xb0,0x59,0xc6,0xd7,0x53, + 0x6e,0xfc,0xb6,0x6b,0x5f,0x50,0xf0,0x89,0xeb,0x69,0x19,0xcf,0x2a,0x6b,0x5a,0x5a, + 0x14,0x31,0xf1,0xd3,0x67,0xc2,0x5f,0xdb,0x5c,0x2a,0x43,0x54,0x9c,0xb7,0x71,0x72, + 0x1e,0xe5,0x01,0xa1,0xae,0xaa,0xe1,0xb5,0xb6,0x75,0xc8,0x7d,0x2a,0x5e,0x3c,0x6f, + 0x6b,0xef,0x68,0x6c,0x6a,0x5b,0xb5,0x6a,0xf5,0xc0,0x3d,0x18,0xb4,0xa8,0xea,0x58, + 0x31,0x7f,0xc9,0x23,0x80,0x88,0xf8,0x2f,0x97,0x4f,0x13,0x5e,0xe2,0x2a,0xa5,0xe9, + 0x21,0x75,0x89,0x91,0xab,0xf7,0x17,0xe2,0xb7,0xf3,0xd9,0xb2,0x54,0x54,0x26,0x31, + 0xb5,0x50,0x4c,0xa7,0xe4,0xf2,0x64,0x16,0xb7,0x31,0x68,0xba,0xf2,0x41,0xb0,0x37, + 0x56,0x44,0x80,0x15,0x63,0x9f,0xc8,0x94,0x53,0x43,0xad,0x06,0xcb,0x64,0xa7,0xa9, + 0xae,0x6c,0x41,0x68,0x85,0x59,0x6a,0x33,0xc1,0x65,0x74,0x89,0xb3,0x98,0x62,0xfd, + 0xb2,0x35,0x92,0x2d,0xb7,0x4f,0xa4,0xac,0x6d,0x78,0xc9,0x5a,0xfc,0x92,0x91,0xdc, + 0x5a,0xa9,0x91,0xd2,0x16,0xe0,0x8a,0xf1,0x8c,0x42,0x40,0x99,0x8d,0x17,0xc0,0x49, + 0x5b,0xf5,0xdd,0x2a,0x46,0x3e,0xf2,0x72,0x7a,0xc6,0xda,0x82,0x8f,0xf5,0x40,0x10, + 0x9c,0x63,0xf4,0xe3,0x3d,0x74,0x6a,0xd6,0x9a,0xab,0xe8,0x4f,0x3c,0x7c,0x19,0xce, + 0x04,0x08,0x5e,0x12,0xa0,0x6d,0xef,0xae,0x6d,0xb7,0x0b,0xfd,0xd5,0x06,0x6b,0x87, + 0xaf,0x1d,0x8e,0xd5,0x35,0x34,0x0d,0xdc,0xe0,0x33,0x40,0xd2,0xdc,0xd2,0xfa,0xd5, + 0xd7,0xdf,0x98,0x4e,0xb2,0x98,0x32,0x65,0xea,0xcc,0x99,0x56,0xb3,0x66,0xcf,0xb1, + 0xb1,0x9d,0x63,0x3b,0xc7,0x6e,0xd6,0x6c,0xdb,0x19,0x56,0xd6,0x93,0x26,0x5b,0x18, + 0x1b,0x1b,0x1b,0x18,0x32,0x27,0x6a,0xa2,0x0f,0x81,0x47,0xab,0x52,0x4b,0xd0,0xe8, + 0x20,0xca,0x21,0xd4,0x59,0x58,0x6f,0xb3,0x0a,0x3d,0x6e,0xcc,0xb8,0x8b,0x71,0xf1, + 0x1e,0x9e,0x87,0x3d,0x7c,0x43,0xae,0x5c,0x4f,0x2d,0x2a,0x29,0x6b,0x69,0x6d,0x95, + 0x37,0xd1,0x85,0xf8,0xa8,0xe8,0xf3,0xaa,0xa3,0x94,0x9a,0xe2,0xaa,0x0c,0x1d,0xf6, + 0xdb,0xae,0x3d,0xa1,0x61,0xa7,0xf7,0x1d,0xf0,0x3a,0x1f,0x13,0xf7,0xe0,0x61,0x7e, + 0x9d,0xb8,0x51,0xc1,0x58,0x5a,0x5b,0x27,0x9e,0x62,0x39,0x45,0x79,0xcb,0x27,0x4f, + 0x9a,0x7c,0xfe,0xc2,0xc5,0xe6,0x96,0x66,0x20,0xec,0x8a,0x99,0x2f,0x10,0x28,0xc0, + 0x7d,0x98,0x57,0x34,0x35,0xb7,0x88,0xc4,0xf5,0x42,0x51,0x9d,0xb0,0xb6,0x16,0xe8, + 0x0f,0x04,0x80,0x9f,0x36,0x35,0xb7,0x4a,0x00,0x93,0x69,0xc3,0x5e,0xf4,0xad,0x72, + 0xce,0x83,0x07,0xcb,0x97,0xaf,0x50,0xb2,0x91,0xb7,0xef,0xd8,0x19,0x7e,0x36,0xd2, + 0xdd,0xd3,0xe7,0xdc,0xf9,0xb8,0x07,0xb9,0x05,0xe2,0xfa,0x86,0xee,0xd7,0xe2,0xef, + 0x0b,0xb4,0xb0,0xd0,0x25,0xe9,0xee,0xec,0x92,0x74,0x74,0x75,0xb6,0xb5,0x75,0xc0, + 0x68,0x86,0x02,0x40,0x2a,0x24,0xf8,0x17,0xc7,0x43,0xdc,0xef,0xd9,0xf7,0xa1,0xdf, + 0xe9,0xb2,0x8c,0x8c,0x58,0xb7,0xef,0xdc,0x73,0xdb,0xef,0x19,0x1c,0x12,0x76,0x33, + 0xf3,0x4e,0x65,0x35,0xaf,0xbd,0xb3,0x43,0x99,0xf1,0x1f,0xc3,0x68,0x0f,0xd6,0xd9, + 0x0e,0x59,0xa0,0xc4,0xd6,0xb6,0x36,0xe8,0x77,0x54,0x34,0x15,0x6e,0x03,0x28,0x81, + 0x00,0x5c,0x42,0x18,0x6e,0x81,0xa0,0xdb,0x9d,0xc8,0x8c,0x94,0xd4,0xb4,0x81,0x1b, + 0x5d,0x5d,0x5c,0xb9,0x67,0x23,0xcf,0xb9,0x1d,0xf4,0x8a,0x8a,0x8e,0xcd,0x79,0x98, + 0x0f,0x0d,0xa8,0xc0,0x95,0x29,0xaa,0x13,0xd9,0xd9,0x29,0xda,0x98,0x24,0x2b,0x53, + 0x2d,0x2d,0x2f,0x25,0x24,0xec,0xdc,0xbd,0x2f,0x24,0xf4,0x74,0xda,0xcd,0xdb,0x35, + 0x7c,0x41,0x47,0xa7,0x5c,0x4c,0x01,0xd9,0xb3,0xd7,0xed,0x35,0x40,0xa0,0xaa,0x1a, + 0x1b,0x7f,0xc9,0xf3,0x90,0x8f,0x7f,0x60,0xc8,0x95,0xab,0xa9,0x25,0x4f,0x9f,0x41, + 0x13,0x29,0x5e,0xee,0xc0,0x33,0x3d,0x34,0xf1,0x83,0x0e,0x86,0x49,0x60,0x5b,0x07, + 0xea,0xe2,0x8e,0x2e,0xd4,0xdd,0xd0,0xb6,0xf4,0x25,0xea,0x15,0xd4,0x3b,0x9d,0xd0, + 0xf8,0x10,0xe8,0x94,0x74,0x45,0x45,0x47,0x8f,0x1c,0x21,0x77,0x77,0xa2,0x81,0x81, + 0x61,0xd2,0xd5,0x6b,0x7b,0xdc,0x0e,0x04,0x04,0x87,0x5c,0x4f,0xcd,0x44,0x4c,0xbc, + 0x45,0x51,0xd5,0x2e,0xc6,0x5f,0x7e,0x6d,0x73,0x69,0x8c,0x1b,0x7f,0xe5,0xea,0xb5, + 0x9b,0x99,0xb7,0xb3,0x73,0x72,0x45,0xe2,0x86,0xce,0x2e,0xf9,0x0e,0xe5,0x4e,0x09, + 0xbc,0x46,0xf9,0x05,0x05,0x06,0xfa,0x06,0x03,0xf7,0x60,0xd0,0xf2,0xe1,0x07,0x43, + 0x75,0x97,0x1e,0x46,0xac,0x4d,0xea,0x08,0x36,0xe1,0x0a,0x09,0x3c,0x91,0xdd,0x50, + 0x80,0x68,0x78,0xb9,0x58,0x44,0x31,0x44,0xc4,0x22,0x79,0x98,0xbd,0xf2,0x28,0xd6, + 0x2c,0x75,0x19,0x03,0x0c,0xe1,0x3d,0x4e,0xb5,0xb4,0x2a,0xc8,0x0b,0xa4,0x15,0x40, + 0xaa,0x97,0x0e,0x73,0xc5,0x14,0xe0,0x72,0x29,0x24,0xc5,0x2c,0x55,0x76,0xa7,0x53, + 0x1d,0x1b,0xfb,0x6d,0xa5,0xa4,0x5b,0x88,0xb9,0x27,0x45,0x93,0x91,0xc3,0x17,0xac, + 0xe2,0x52,0x5b,0xb0,0x28,0xbf,0x2d,0x6d,0xa4,0xd4,0x1f,0x8d,0xb3,0xd4,0xd2,0xd4, + 0x5b,0xca,0xcd,0x45,0x24,0x0b,0x11,0xc2,0x9d,0x21,0xa6,0x77,0x83,0x19,0x46,0x7f, + 0xec,0x44,0x46,0xf6,0xa3,0xea,0x03,0xd5,0x75,0xed,0xad,0x3e,0xae,0x20,0x22,0xcb, + 0x64,0xdf,0x17,0x61,0xe5,0xf4,0x92,0xb8,0xb1,0x0b,0x0f,0xc1,0x2e,0x87,0x54,0x5f, + 0xc8,0x76,0x11,0x52,0x1b,0xa4,0x09,0x0b,0x06,0x14,0x76,0x2c,0xc3,0x67,0x76,0x91, + 0xcf,0x84,0x1f,0xe2,0x0f,0x84,0xb3,0xd0,0x8e,0xac,0xaf,0xe3,0x98,0x2b,0x23,0x19, + 0x2b,0x8e,0x1b,0x2c,0x09,0x44,0xbe,0x60,0xbb,0x1d,0xda,0xb6,0x2e,0xac,0x05,0xce, + 0x27,0x2f,0xa4,0xff,0x39,0xa0,0xf9,0xae,0x04,0x5e,0xc6,0xcb,0x89,0x89,0x66,0xa6, + 0x93,0xcc,0x2c,0xa6,0x03,0xf6,0x02,0xf2,0xce,0xb3,0x5b,0x30,0xcf,0xee,0xe3,0xf9, + 0x76,0x0b,0x6d,0xe7,0xce,0xb3,0x9e,0x65,0x33,0x6d,0xda,0x74,0xe2,0x05,0xd6,0xd5, + 0xd5,0xa3,0xf9,0x2f,0x39,0x08,0x1a,0xc0,0x97,0x7c,0xb8,0xfa,0x36,0x5f,0x21,0x8d, + 0x51,0x1b,0x13,0x1d,0x13,0x83,0xb7,0xec,0x06,0x24,0x25,0xa7,0x16,0x16,0x2b,0xc2, + 0x5f,0x90,0xa4,0xa4,0x64,0xf5,0xd1,0xea,0xca,0x68,0x86,0xe9,0x81,0xb3,0xcb,0xb6, + 0xd3,0xe1,0x11,0xfb,0xf7,0x79,0x47,0x5f,0xb8,0x98,0x9d,0x93,0x27,0x12,0x37,0x2a, + 0xf0,0xe5,0xd5,0x37,0x36,0x5a,0x5b,0xcf,0x52,0xd2,0x6c,0x3d,0x5d,0xfd,0x8b,0xb1, + 0x71,0xf5,0x0d,0xf0,0xde,0xb7,0x29,0xfe,0x63,0x1c,0x50,0x97,0x96,0xb6,0x56,0x71, + 0x43,0x43,0x0d,0x4f,0x58,0x58,0xfc,0x34,0x2f,0xff,0xc9,0xef,0x39,0x05,0x77,0xb3, + 0x1f,0xde,0xcb,0xc9,0x7b,0x98,0xfb,0xf8,0x49,0x51,0x49,0x45,0x25,0x8f,0x2f,0x02, + 0x45,0x2d,0x00,0x73,0xfd,0x12,0x61,0xd0,0x50,0x58,0x52,0x62,0x65,0x3d,0x4b,0x99, + 0xd5,0x06,0xa7,0xad,0xce,0xe7,0xce,0xc7,0xb8,0x1d,0xf0,0x8c,0x8c,0x8e,0xbd,0xff, + 0x30,0x4f,0x2c,0xae,0x97,0x48,0x5e,0x83,0xbf,0x30,0xf0,0x36,0x35,0x37,0x8b,0xeb, + 0x1b,0x05,0xc2,0x3a,0x1e,0x5f,0x58,0x2d,0xe0,0x57,0xf3,0x84,0x35,0x7c,0x7e,0x0d, + 0x4f,0x50,0xc3,0xab,0xad,0xaa,0xe6,0x55,0xd7,0x08,0x78,0xfc,0x5a,0x61,0xad,0xe8, + 0xc1,0xc3,0x47,0xc3,0x54,0x86,0xc9,0x34,0x82,0x5e,0x66,0x56,0x16,0xf0,0xdf,0x23, + 0xc1,0x27,0x53,0x6e,0xdc,0x2c,0x2e,0xad,0x80,0xd1,0x5a,0xc1,0x0a,0x3f,0x92,0x17, + 0x08,0x7c,0xdb,0xda,0x3b,0x9b,0x9a,0x5a,0x41,0x21,0x14,0x57,0x55,0x2d,0xa8,0xa8, + 0xac,0xae,0xac,0x16,0x54,0x61,0xa9,0xac,0xe2,0x55,0x55,0xf3,0xb1,0x08,0x64,0xa5, + 0xb2,0xaa,0x06,0x7e,0xab,0xc1,0x2c,0xbe,0xf0,0x76,0xd6,0xbd,0x81,0x3b,0x81,0x6d, + 0xf3,0x96,0x2d,0x91,0x17,0xce,0xb9,0x1d,0xf0,0x8a,0x88,0xba,0xf8,0xfb,0xfd,0x5c, + 0xa1,0x48,0xd1,0x56,0xa2,0xba,0x7a,0xb1,0xfd,0xa2,0x45,0x4a,0x6a,0xb6,0x98,0x3c, + 0x25,0xf1,0x4a,0xf2,0xee,0xbd,0x07,0x8e,0x9e,0x38,0x95,0x7e,0x33,0xb3,0xb2,0x8a, + 0xdf,0xd6,0xd6,0xa9,0xa0,0xad,0x3c,0x0f,0x1d,0x56,0xac,0x10,0xde,0xc4,0xf3,0x17, + 0x63,0x7d,0xfc,0x7d,0xbd,0xfd,0x82,0x13,0x92,0xae,0x16,0x97,0x3e,0x6d,0x6e,0x79, + 0x8d,0xbb,0x1f,0x1a,0xbf,0xb5,0xbd,0x03,0x9e,0xb6,0x3a,0x71,0x3d,0x5f,0x20,0x82, + 0x67,0x12,0xba,0x18,0x3a,0x1a,0x1a,0x16,0xfa,0xa2,0x86,0x07,0x9d,0x5e,0x4b,0xba, + 0x9b,0xfc,0xe2,0xde,0x47,0xf3,0xc4,0x0b,0x31,0xb1,0xaa,0xa3,0x46,0xcb,0x7d,0x1d, + 0x74,0xf4,0x92,0x92,0xaf,0xee,0xd9,0xbb,0xcf,0x3f,0xe8,0x68,0xf2,0xb5,0xf4,0xd2, + 0xb2,0x67,0x8a,0xf9,0xef,0xd5,0x94,0xd4,0xd7,0x36,0x97,0xcd,0x6c,0xdb,0xc2,0xa2, + 0xe2,0xd4,0xf4,0xcc,0xe2,0xd2,0xb2,0x86,0x46,0x45,0x33,0x67,0x98,0x2c,0xc0,0x03, + 0x1c,0x7c,0x34,0x64,0xc4,0xdb,0x7d,0xbf,0xa0,0xbc,0x8c,0x36,0x9c,0xc7,0xda,0x5c, + 0x88,0x36,0x17,0xd1,0xbe,0x5d,0xe2,0xb7,0xc5,0xbb,0xa1,0x00,0xda,0x10,0x6c,0x51, + 0x6c,0xb4,0x8e,0x46,0x1c,0x0a,0xb6,0xb8,0x62,0xe9,0xb2,0xb0,0x88,0x30,0x68,0x82, + 0x68,0xb4,0x2a,0x16,0xd9,0x78,0x4c,0xbb,0x4a,0x65,0xb8,0xb0,0x74,0x71,0x58,0x84, + 0x49,0x2b,0x8f,0xf6,0xb4,0x82,0x90,0xe5,0x68,0x0c,0xd6,0x02,0x44,0x87,0xb9,0xb5, + 0x64,0xa5,0x9a,0xd2,0x2c,0xf5,0xf0,0xa2,0x6f,0xa6,0x08,0x4a,0x72,0x04,0xb2,0xe5, + 0xca,0xd8,0x4c,0x79,0xa5,0x89,0x85,0x64,0x0b,0x16,0xbd,0x3b,0x0b,0x8a,0x00,0xcd, + 0x34,0x3a,0xcb,0xa6,0x91,0x7a,0x87,0x31,0x52,0xbb,0x56,0x4b,0x9b,0x85,0x22,0xc8, + 0xa6,0x1c,0x1e,0xde,0x01,0xce,0x27,0x2e,0x60,0xd2,0x74,0xa6,0x5c,0xaa,0xdd,0x88, + 0x33,0x1d,0x7f,0xcd,0x24,0x24,0xbb,0xb3,0xd8,0x14,0x0a,0xa3,0x73,0x3c,0xd0,0xf1, + 0x59,0x9b,0x4b,0x90,0x3b,0x98,0x82,0xe0,0x4c,0xe6,0x9a,0x64,0xa3,0x55,0xb1,0x64, + 0x21,0x5a,0x7f,0xb1,0x8f,0x8e,0xfd,0x01,0xed,0xb9,0xbf,0x6a,0xd9,0x6e,0x9d,0xbb, + 0xfa,0x50,0x53,0xeb,0x5f,0x89,0x02,0xf3,0x04,0xfc,0x55,0xdf,0xac,0xb6,0xb0,0xb0, + 0x98,0x31,0xd3,0x6a,0xf6,0x9c,0xb9,0x76,0x0b,0x16,0xda,0x2f,0x5e,0xba,0xf8,0x93, + 0x65,0xf6,0x8b,0x97,0x7c,0xbc,0x70,0xf1,0x9c,0xb9,0x1f,0xc3,0xb0,0x6f,0x6e,0x6e, + 0x6e,0x60,0x64,0xa2,0xa3,0xa7,0x2b,0xfb,0x15,0x12,0x40,0x30,0x39,0x0b,0x9a,0x96, + 0x37,0x7b,0x92,0xd5,0x54,0xd5,0xce,0x46,0x44,0x1e,0xf6,0xf5,0xf7,0xf4,0xf6,0xbd, + 0x9c,0x78,0x1d,0xf0,0xa8,0xb9,0xb9,0x95,0x2c,0x33,0xf6,0x6b,0xf0,0xcd,0x8c,0x8c, + 0xb1,0x63,0x94,0xfa,0xe2,0x03,0x4c,0xfa,0xcf,0x4f,0x3f,0x47,0x44,0x47,0xef,0xdb, + 0x77,0x30,0xf2,0x5c,0x4c,0x76,0xce,0x23,0x18,0x4b,0xd1,0x16,0x0e,0x39,0x4d,0x01, + 0x53,0xfd,0x05,0x0b,0x95,0x1a,0x4b,0x75,0x75,0xf4,0xe2,0xe2,0x2f,0xd5,0x01,0xb6, + 0x35,0x34,0xc0,0xd8,0xac,0x80,0xf1,0xc1,0x00,0x0b,0x08,0x5d,0x51,0x55,0x93,0x5f, + 0x50,0x9c,0x96,0x79,0xe7,0xd2,0xe5,0xe4,0xf3,0x31,0x97,0x4e,0x87,0x47,0x11,0x89, + 0x88,0x8a,0x89,0xbb,0x94,0x90,0x7a,0x23,0x33,0xfb,0x7e,0x6e,0x71,0xe9,0x33,0x20, + 0xe0,0x2d,0xad,0x2d,0x80,0xe6,0xfd,0x56,0xff,0x49,0x51,0x91,0xbd,0x12,0xe6,0xfd, + 0xfc,0xcb,0xa6,0x98,0xb8,0xb8,0x7d,0xee,0x87,0x22,0xce,0x5d,0xb8,0x9f,0xf3,0x08, + 0x8c,0x54,0x3c,0x20,0x03,0xbb,0x69,0x6c,0x6c,0xa9,0xac,0xe6,0xe7,0xe6,0x3f,0xc9, + 0xba,0x93,0x9d,0x91,0x79,0x2b,0x3d,0xe3,0x4e,0xea,0xcd,0x5b,0x69,0xe9,0x59,0xff, + 0xcf,0xdc,0x75,0x87,0x45,0x71,0x6e,0xfd,0x3f,0xbe,0x2f,0xc6,0x98,0x28,0x12,0xa3, + 0xb1,0x80,0x1a,0xa5,0x69,0xe2,0x0d,0x26,0x96,0xe4,0xea,0x35,0xd6,0x60,0x01,0xb1, + 0xd7,0xa8,0xd8,0xaf,0x0a,0xb8,0x34,0x69,0xd2,0x61,0xe9,0x4b,0x97,0xde,0x7b,0xef, + 0xbd,0x2e,0x6d,0x01,0xe9,0x45,0xa4,0x08,0x48,0xef,0x4d,0x51,0x24,0xb9,0xdf,0xf3, + 0x9d,0x77,0x66,0x76,0x76,0x21,0xcc,0x40,0x92,0x6b,0x12,0x9e,0xf3,0xf0,0xcc,0xcc, + 0xee,0xbe,0xf3,0x4e,0x7b,0x7f,0xe7,0x77,0xde,0xdf,0x39,0x93,0x93,0x5b,0x90,0xcd, + 0xce,0x63,0xe7,0x72,0xb2,0xd8,0xf9,0x59,0xd9,0x85,0x45,0xc5,0xa5,0x65,0x15,0x95, + 0x4b,0x05,0x78,0x83,0xf0,0xb2,0xe5,0xcb,0xf2,0x0b,0x39,0x4c,0x33,0x4b,0x96,0x8d, + 0x53,0x4c,0x5c,0x52,0x55,0x75,0x3d,0x8c,0xea,0x73,0x4a,0x70,0xdf,0x4e,0x4e,0x8e, + 0x8c,0x8e,0xc1,0x39,0xa9,0xac,0xae,0x2f,0x2c,0x2e,0xcd,0x84,0xbd,0xe4,0x14,0x66, + 0x64,0xe5,0x65,0x66,0xe7,0xc1,0xff,0x2c,0x76,0x5e,0x16,0xac,0x66,0xe7,0xa5,0xc3, + 0x96,0x9c,0x82,0xf4,0x6c,0xd8,0x8e,0xfe,0x03,0xab,0x02,0x83,0x2f,0xe4,0x73,0x4a, + 0x4b,0xcb,0xcb,0xf9,0xdd,0x80,0xff,0xae,0xc9,0xc9,0xdd,0x8c,0x88,0x8a,0x36,0x64, + 0x9a,0x05,0x06,0x87,0x15,0x95,0x94,0x0f,0x0e,0x0d,0xc1,0x29,0xa2,0x3a,0x96,0xd1, + 0xf1,0x31,0xd9,0x13,0x27,0xe7,0xd9,0xb2,0xb8,0xa8,0x78,0x4c,0x6c,0xbc,0x91,0x31, + 0xd3,0xc5,0xd5,0x2b,0x35,0x23,0xef,0x65,0x47,0xd7,0x38,0xad,0x54,0xde,0xc5,0xd5, + 0x8d,0xbe,0x41,0xf0,0x81,0x83,0x42,0x42,0x1c,0x9e,0x38,0xd9,0xd8,0xbb,0xc7,0xc6, + 0x27,0x3f,0x6b,0x6c,0x1d,0x1e,0xa5,0xe5,0xbf,0xff,0x41,0xbe,0x16,0x1c,0x51,0x53, + 0x6b,0x4b,0x59,0x45,0x75,0x5e,0xe1,0xd3,0x2c,0x76,0x01,0x5c,0x65,0x38,0xcf,0x99, + 0xec,0x82,0x2c,0x36,0x27,0x83,0x8d,0xce,0x79,0x4e,0x1e,0xda,0x92,0x93,0x9b,0x9f, + 0x91,0x93,0xcf,0xce,0x2d,0xca,0x61,0x73,0x38,0x4f,0xcb,0x12,0x93,0x52,0x57,0x7c, + 0xb6,0x82,0xaa,0x27,0xab,0x56,0xae,0x8a,0x8d,0x8f,0x37,0x31,0xb5,0xb4,0x77,0x74, + 0x4e,0x4c,0xc9,0x68,0x68,0x7e,0x09,0x80,0x48,0x73,0x68,0x05,0x1c,0x0e,0xfd,0xa1, + 0x81,0x7f,0xc5,0x64,0x9a,0x56,0x54,0xd5,0x72,0x8a,0xcb,0x3a,0xba,0xba,0x81,0xe1, + 0xd2,0xcc,0x6b,0x8c,0x8d,0x4f,0xf4,0xf5,0xf7,0x4b,0x4b,0xcb,0xfc,0x69,0x45,0x81, + 0x3e,0xfc,0x48,0x50,0xf8,0x84,0x2b,0x02,0x29,0x7e,0xd9,0x15,0x2c,0x70,0x21,0x06, + 0x57,0x55,0x11,0xb2,0x28,0x9c,0x54,0x6a,0x74,0x13,0xa0,0x89,0x01,0x10,0x57,0x52, + 0x05,0x24,0xb1,0x17,0xcf,0xdc,0x41,0xc9,0x44,0x00,0x8e,0xfc,0x2a,0x2c,0x20,0xce, + 0x28,0x8a,0xdb,0x45,0x22,0x1d,0x4e,0x42,0x49,0x70,0xe4,0x05,0x84,0xf9,0x65,0xd5, + 0x24,0x5d,0xd5,0xee,0x42,0xa8,0x87,0x08,0x69,0x1f,0x29,0x69,0xe6,0xcf,0x0f,0xc2, + 0x02,0xce,0x98,0x5e,0x5a,0x13,0x65,0x48,0xa1,0x2f,0x13,0x60,0x3a,0x40,0xe8,0xac, + 0xa6,0xeb,0xaf,0xa6,0xfd,0x16,0x03,0x7a,0x22,0x86,0x3c,0x5d,0xb5,0x45,0x3a,0x12, + 0xe4,0x7e,0x71,0x65,0x17,0x37,0x56,0xc0,0x0d,0x65,0x63,0x47,0xba,0x09,0x57,0x80, + 0xa3,0xcc,0xac,0x1e,0xec,0x5c,0x61,0xaa,0x30,0x24,0xcd,0xe2,0xe5,0x41,0x8b,0xa9, + 0xbe,0xc4,0x4b,0x59,0x62,0x10,0x5c,0x89,0x02,0xd1,0x37,0xb1,0x40,0xf4,0x45,0x24, + 0xc7,0xc2,0xde,0x9a,0x64,0x2b,0x74,0x80,0x29,0xb4,0x47,0x67,0xcd,0x2e,0x65,0xaf, + 0x88,0x82,0xff,0x96,0xe2,0xe5,0x4f,0x30,0x4e,0x51,0xd1,0xae,0x5d,0xbb,0xbe,0xf9, + 0xe6,0xdb,0xef,0x77,0xed,0xde,0x77,0xe0,0xc7,0x23,0x47,0x8e,0x1d,0x93,0x39,0x21, + 0x7d,0xfc,0xb4,0xf4,0xf1,0x53,0x52,0x47,0x64,0xf6,0xee,0x3f,0x04,0xa0,0xfc,0xf5, + 0xd7,0x92,0xe2,0xe2,0x9b,0xd7,0xad,0x5f,0xbf,0x6a,0xf5,0x6a,0x54,0x88,0x12,0x7b, + 0x1d,0x21,0xa2,0xc0,0x0b,0x16,0x82,0xfd,0xc1,0xd7,0x11,0x0a,0x2c,0x16,0x70,0xf7, + 0xf4,0xb4,0x77,0x74,0xb2,0x62,0xd9,0xc5,0x25,0xa4,0xd6,0xd4,0x21,0x95,0x32,0x4d, + 0x3d,0x93,0xa2,0xe2,0x92,0x79,0x66,0x09,0x41,0x97,0x6e,0xde,0xba,0x1d,0x19,0x1d, + 0x63,0x60,0x68,0x1a,0x18,0x1c,0x59,0xf4,0xb4,0xb2,0xa7,0xaf,0x7f,0x92,0x26,0x8a, + 0xf5,0x6e,0x52,0x46,0xe6,0xf8,0x9c,0xcd,0x0a,0x0a,0x0a,0x9a,0x5b,0x5a,0x76,0x02, + 0x79,0x18,0x18,0xc0,0xc2,0x7d,0xb3,0xb7,0xf6,0x33,0x1a,0xeb,0x26,0xfb,0x06,0x86, + 0x9a,0x5b,0xda,0x38,0x45,0x65,0x71,0x09,0x29,0x3e,0x7e,0xa1,0x76,0x8e,0x6e,0x96, + 0xd6,0x76,0x4c,0x33,0x6b,0x23,0x63,0x73,0xa6,0xa9,0xa5,0xa9,0x39,0x8b,0x65,0xeb, + 0xe4,0xe2,0xe1,0x13,0x11,0x15,0x97,0x95,0x93,0x57,0x53,0xf7,0xbc,0xbd,0x13,0x25, + 0xbc,0xcc,0xea,0xea,0xc3,0x4d,0x05,0x43,0xe2,0x26,0x89,0xcd,0xf4,0xa7,0xfa,0x9a, + 0x9c,0x5c,0x74,0x5c,0x82,0x89,0xa9,0x45,0x40,0x70,0x68,0x31,0x1c,0x72,0x6f,0xdf, + 0xe4,0x14,0x25,0x20,0x42,0x27,0x27,0x26,0xde,0xc2,0xb1,0x00,0x13,0x4f,0x4a,0xc9, + 0x00,0x7f,0xc0,0xcb,0x27,0xc8,0xc3,0x3b,0xc0,0xcd,0xcb,0xd7,0xc3,0xdb,0xdf,0xdd, + 0xdb,0xcf,0xcd,0xcb,0x07,0x96,0xc1,0xdc,0xbd,0xfc,0x03,0x02,0xc3,0x4a,0x4a,0x2b, + 0x96,0xf1,0x39,0x3f,0x02,0x02,0x02,0xb9,0xf9,0x05,0x86,0xc6,0xa6,0x26,0xa6,0x56, + 0x7e,0x01,0xc1,0xb9,0x79,0x05,0xad,0x2f,0x3b,0x46,0x81,0x82,0xfd,0x8c,0x11,0x79, + 0x0a,0x0f,0x0a,0xf0,0x17,0x3c,0x8d,0xfa,0x86,0x96,0xac,0x9c,0xfc,0xa8,0x98,0x38, + 0x1f,0xff,0x10,0x0f,0x2f,0x7f,0x57,0x0f,0x6f,0x17,0x77,0x6f,0x20,0x86,0xae,0xee, + 0xde,0x2e,0x6e,0x5e,0xae,0xee,0x5e,0x00,0x52,0xae,0x6e,0xde,0xf8,0x7f,0xec,0x53, + 0x2f,0xf4,0xa9,0x9b,0x57,0x50,0x68,0x38,0xb8,0x02,0x70,0x07,0xbe,0xa7,0xa1,0xf5, + 0xd2,0xa5,0x4b,0xd1,0xb1,0x71,0x7a,0xc6,0x66,0xbe,0x01,0xa1,0x9c,0xe2,0xd2,0xce, + 0xde,0xa1,0xb7,0x6f,0x29,0xef,0x99,0x57,0x13,0x13,0x17,0xe7,0x3d,0xe7,0xb8,0x6e, + 0xdd,0x7a,0x40,0x76,0x63,0x13,0x33,0x67,0x57,0xcf,0xd4,0xf4,0xec,0x96,0xb6,0x4e, + 0x70,0xf9,0x68,0xa6,0xdd,0x7d,0x7d,0x03,0xe9,0xaf,0x35,0x3c,0x7d,0x6e,0x1e,0x9e, + 0xce,0xae,0x6e,0x2c,0xd6,0x93,0xe8,0xd8,0xa4,0xfa,0x86,0xc6,0x91,0x51,0xba,0xd8, + 0xd1,0xd4,0xcf,0xe0,0x10,0xbe,0x79,0xd1,0xda,0x5e,0x58,0x54,0x1a,0x1d,0x9b,0x0c, + 0x1e,0xa0,0x97,0x4f,0xa0,0xbb,0xb7,0x2f,0x6e,0xd8,0xb5,0x46,0x97,0x1b,0x5b,0xe6, + 0x37,0x9f,0xc0,0x90,0x88,0xe4,0x94,0xd4,0x95,0x9f,0xaf,0xa2,0xea,0x09,0x40,0x73, + 0x68,0x78,0x84,0x99,0xb9,0xa5,0x8d,0xbd,0x23,0xdc,0x48,0xf5,0x8d,0xad,0xe0,0x62, + 0xd1,0x4c,0xca,0x94,0x56,0x54,0xd0,0xd7,0x7c,0x83,0x73,0x95,0x99,0x95,0x0d,0xee, + 0x1f,0xb8,0x85,0xe0,0x43,0xbe,0x9d,0xa4,0xf4,0x21,0xe1,0xf6,0x86,0x7d,0x15,0x3f, + 0x7d,0xba,0x72,0xe5,0xca,0xf7,0x74,0x4b,0xcc,0x62,0xff,0xf3,0xc1,0xa7,0x9b,0xa5, + 0x51,0x99,0x0b,0x9c,0x3c,0xa2,0xf8,0x2d,0x01,0x58,0x28,0xc4,0x8a,0x89,0x7b,0x31, + 0x38,0x06,0x68,0xc3,0xd3,0x63,0x51,0x30,0x96,0x2f,0xce,0x8c,0x54,0x5b,0x38,0x10, + 0xa3,0x38,0xb0,0x46,0x0f,0x01,0x46,0x58,0xb0,0xf7,0x2b,0x8d,0x76,0xf2,0xb7,0x5c, + 0x3a,0xd9,0xc9,0x1f,0xb5,0x26,0xdb,0x97,0x20,0x76,0x4a,0xce,0x38,0x13,0x79,0x4f, + 0xb8,0xd4,0x0a,0xe3,0xd1,0xfd,0x5c,0xfd,0x15,0xa6,0xbb,0xd6,0x24,0x34,0x63,0xb0, + 0xca,0x8d,0x7b,0x93,0x41,0xe6,0x01,0x9c,0x0e,0x73,0x15,0x56,0x44,0x9e,0x32,0xae, + 0x98,0xc2,0x40,0x93,0xc8,0xff,0xe5,0x6b,0xbc,0x0f,0xeb,0x39,0x26,0x72,0x46,0x84, + 0x97,0xe8,0x09,0x9e,0x44,0x4c,0x92,0x6e,0x6e,0x9b,0xfd,0xbc,0x43,0xc0,0x52,0x86, + 0xc9,0xdf,0x12,0x31,0x73,0xd4,0x0d,0x8c,0xb3,0xe3,0x67,0x06,0x7c,0x0c,0x7e,0x69, + 0xb4,0xca,0x4b,0x94,0x97,0x04,0x2c,0x58,0xfe,0x99,0xf8,0xfd,0x72,0xf4,0xfa,0x86, + 0xeb,0x39,0x22,0x3f,0x25,0x89,0x5c,0x08,0x17,0x39,0xe9,0xbd,0x51,0xda,0x79,0xed, + 0x61,0x0b,0xa1,0x7d,0x86,0x42,0xbb,0x35,0x6f,0x69,0xf9,0x8c,0x8e,0xff,0xfe,0x0c, + 0xd0,0x3f,0xd9,0xec,0xec,0xed,0x25,0x25,0x25,0x81,0xfc,0xee,0xdd,0x7f,0x40,0xea, + 0xf0,0x51,0xe9,0x13,0x67,0x4e,0x9e,0xbd,0x70,0xe6,0xdc,0x85,0x53,0x67,0x2f,0xc8, + 0xc8,0x9e,0xfa,0x51,0xea,0xf0,0xee,0x3d,0x3f,0x00,0x3a,0x03,0x05,0xde,0xb0,0x71, + 0x03,0x56,0x0b,0x7a,0xc5,0xb2,0x65,0xcb,0xf0,0x44,0xe0,0x45,0x1f,0x2d,0xc2,0x69, + 0xc8,0x1f,0x51,0x61,0x7d,0xf2,0xf1,0x62,0x07,0x27,0xc7,0x27,0xae,0xee,0xa6,0x56, + 0xac,0xe8,0xd8,0xc4,0xea,0x9a,0xe7,0x08,0x7f,0xa9,0x63,0x98,0x55,0x35,0xd5,0xc2, + 0x42,0xf3,0xca,0x12,0x82,0xb1,0xeb,0xfc,0xc5,0x0b,0x31,0x71,0x71,0x06,0xc6,0x66, + 0x7e,0x81,0xa1,0x45,0x25,0x65,0xdd,0xbd,0x83,0x93,0xef,0x28,0x1f,0x64,0x40,0xbd, + 0xb3,0xe7,0xce,0xcf,0xd9,0xec,0xdd,0xfb,0x0f,0x5e,0xb4,0xb6,0xb5,0xbd,0xec,0x84, + 0xa7,0x9e,0x4a,0xda,0x04,0x03,0x0f,0xa0,0xcc,0xe0,0xd0,0x48,0x7d,0x43,0x73,0x36, + 0xbb,0x30,0x38,0x2c,0xc2,0xc6,0xd1,0x0d,0x30,0x51,0x43,0x5b,0x47,0x49,0x4d,0x83, + 0xa1,0xac,0xca,0x50,0x52,0x61,0x28,0x3f,0x52,0x56,0xd3,0x50,0xd7,0xd4,0xd1,0xd5, + 0x37,0xb1,0x64,0x39,0xba,0x79,0xfa,0x26,0x26,0xa5,0x15,0x3d,0xad,0x6a,0xef,0x84, + 0x61,0xf9,0x15,0x90,0xd6,0x5f,0x8f,0xcc,0x80,0x6b,0x01,0x81,0x41,0xcb,0xa9,0x69, + 0x08,0xd8,0xb9,0x73,0xe7,0xe3,0x12,0x13,0x0d,0x4d,0x2c,0x7c,0xfc,0x82,0x39,0xc5, + 0xe5,0xbd,0x7d,0x40,0xf9,0xa9,0x83,0x9c,0xff,0x41,0x0c,0xbd,0xa9,0xa5,0x8d,0x9d, + 0xc7,0xf1,0xf1,0x0b,0xb1,0x66,0xd9,0x1b,0x1a,0x33,0x75,0xf4,0x8c,0x90,0xe9,0x1b, + 0x3d,0xd6,0x35,0x84,0xff,0xb0,0xac,0x6b,0x60,0x0c,0x0b,0xa6,0x16,0xd6,0xc0,0x80, + 0xd7,0xac,0x5e,0xc3,0x77,0xed,0x3e,0xc9,0xc8,0xca,0xd1,0x33,0x62,0x6a,0x6a,0xeb, + 0xda,0xda,0x3b,0x85,0x47,0xc6,0x3e,0x2d,0xab,0x6e,0xef,0xe8,0x7e,0x3d,0x41,0xa3, + 0xa0,0x03,0xc4,0x9f,0x04,0xd7,0xa5,0xee,0x79,0x63,0x4a,0x6a,0x96,0x8f,0x5f,0x90, + 0x95,0x8d,0xa3,0x31,0xd3,0x4c,0x47,0xdf,0x10,0x76,0x87,0x4c,0x47,0x9f,0x58,0xe0, + 0xae,0x6a,0xe3,0x5b,0x74,0x0c,0x74,0xf4,0xd0,0x16,0x33,0x0b,0x56,0x5e,0x21,0x67, + 0xd9,0x67,0xbf,0x2d,0x33,0x6b,0xfe,0x76,0xea,0xf4,0xa9,0x84,0xa4,0x24,0x03,0x23, + 0xa6,0xaf,0x7f,0x70,0x7e,0x61,0x71,0x6f,0x5f,0x3f,0x4d,0x5a,0x19,0xf8,0x6c,0x77, + 0xee,0xde,0x9f,0x67,0xcb,0xab,0x56,0xad,0x09,0x8f,0x8c,0x62,0x9a,0x9a,0xb9,0xb8, + 0x7a,0xa4,0xa4,0x67,0xc3,0x5d,0x44,0xcf,0x7f,0x63,0xe3,0x63,0xf9,0x67,0xdb,0x67, + 0x35,0x1b,0x3b,0x7b,0x0f,0x6f,0x1f,0x4b,0x96,0x7d,0x64,0x74,0xc2,0xb3,0x67,0x80, + 0xbf,0x74,0xd9,0x52,0xef,0xde,0x4d,0xc1,0x3d,0x59,0xfb,0xac,0x21,0x21,0x29,0x1d, + 0x9c,0x1c,0xa6,0xb9,0x95,0x1e,0x5c,0x59,0xee,0xe5,0xc6,0x0d,0xce,0xb0,0x2e,0x76, + 0x9e,0xf9,0xb7,0x33,0xcd,0x2d,0x53,0xd2,0xd2,0xd6,0xaf,0xa3,0x9c,0x5d,0x15,0x14, + 0x10,0x0c,0x08,0x0a,0xb2,0xb0,0xb6,0xb5,0xb2,0x73,0x48,0x48,0x4a,0x79,0x86,0x92, + 0xc1,0xe9,0xf8,0x6f,0x43,0x63,0x33,0xdc,0x3c,0x34,0xc7,0x75,0xfa,0xcc,0xe9,0xea, + 0xba,0xba,0xcc,0xec,0xdc,0x17,0x2d,0x2f,0xc7,0xc6,0x29,0x53,0x99,0xc0,0x5e,0x4f, + 0x4c,0xc0,0x69,0x34,0x61,0x9a,0xbe,0xa7,0xfb,0x81,0xca,0x3e,0x5c,0x24,0x20,0x76, + 0xbf,0x14,0xc1,0x87,0x7a,0x37,0x46,0xe2,0x78,0xc4,0x73,0xc6,0x2a,0x4f,0x13,0x85, + 0x2d,0xcc,0x90,0x54,0x71,0x67,0x69,0x31,0xb5,0x12,0x57,0x8f,0x34,0xf3,0xb7,0x38, + 0x68,0x6a,0x63,0xb3,0xba,0xe4,0x74,0x30,0x26,0xd9,0xc2,0xf5,0xc6,0xd0,0x26,0x86, + 0xb0,0x44,0x3e,0x11,0x2e,0xca,0xe2,0xed,0x08,0x6b,0x04,0x7e,0xb2,0x59,0x8b,0x97, + 0x08,0xcc,0xe5,0xa1,0xfd,0xd3,0xf8,0x3b,0x85,0x2a,0x8c,0xb7,0x91,0xaf,0x1b,0xf8, + 0x8e,0x50,0x40,0x5b,0x0b,0xa7,0xd2,0x7c,0x82,0x2b,0x24,0xb5,0xea,0xe2,0xe2,0xfe, + 0xb4,0x5e,0x91,0x34,0x79,0x66,0x27,0x7f,0xad,0x37,0xe3,0xe6,0x28,0x11,0x05,0xb5, + 0x80,0x05,0xab,0xb4,0xa1,0xda,0xd1,0x8a,0x75,0x62,0xf7,0x9e,0x22,0x16,0x7c,0x3d, + 0x47,0xf4,0xa7,0x04,0xd1,0x73,0x21,0x22,0xb2,0xde,0x48,0x8b,0x75,0xd0,0x4c,0x78, + 0x9f,0xce,0xce,0x33,0x16,0xd5,0x0d,0x9d,0x7f,0x2d,0xaa,0xce,0xd3,0xc6,0xc6,0xc7, + 0x2e,0x5d,0xfe,0xe9,0xdb,0x6f,0xb7,0x01,0xc9,0x3d,0x24,0x75,0x44,0xf6,0xc4,0xa9, + 0xb3,0xe7,0x2f,0x5f,0xbc,0x7c,0xfd,0xf2,0x95,0xab,0xe7,0x2f,0x5e,0x3d,0x7d,0xf6, + 0xc2,0xd1,0x63,0xb2,0x7b,0xf7,0x1d,0xdc,0xb1,0xf3,0xbb,0x2d,0x5b,0xb6,0x88,0x88, + 0x88,0xae,0x11,0x12,0x5e,0xbe,0xe2,0xf3,0x4f,0x3f,0xfd,0x74,0xe9,0xd2,0xa5,0x00, + 0xc1,0x78,0x21,0x2c,0xdc,0xd0,0x4b,0x81,0xff,0xf7,0x83,0xdf,0x11,0x85,0x5e,0xb4, + 0x70,0x91,0xb9,0x95,0x85,0x9b,0xbb,0x17,0x8c,0xab,0x51,0x31,0x89,0x55,0x35,0xcf, + 0x87,0x47,0xb0,0x59,0x5a,0x8a,0x01,0xfc,0x79,0x53,0xd3,0xfa,0x79,0xab,0x2c,0xa4, + 0x8f,0xc9,0xc4,0x27,0xc2,0x58,0x6a,0xea,0x1d,0x10,0x58,0x50,0x58,0xda,0xdd,0xdb, + 0x4f,0xa3,0x7f,0x9e,0x9a,0xfa,0x45,0x4e,0xee,0x06,0x4d,0x6b,0x00,0xe8,0x5b,0xb6, + 0x7c,0x5d,0xf3,0xac,0xbe,0xa1,0xe9,0x45,0x77,0x6f,0xdf,0xc4,0x1b,0x4a,0x85,0xc9, + 0xe4,0xe4,0xbb,0x81,0xa1,0xd1,0xc6,0xe6,0xd6,0x8c,0xac,0x3c,0xff,0xc0,0x10,0x96, + 0x9d,0x93,0xb9,0x95,0x8d,0xa5,0x35,0xb0,0x5d,0x7b,0x73,0x6b,0x1b,0x63,0x53,0x33, + 0xed,0xc7,0x3a,0x00,0xc1,0xf2,0xf2,0x0c,0x05,0x05,0x65,0xc5,0x87,0x6a,0x6a,0x8f, + 0x1e,0x03,0xbe,0x39,0xbb,0x78,0x44,0xc5,0x24,0x71,0x4a,0x2a,0x51,0x64,0xf2,0xf5, + 0xeb,0x59,0x83,0x00,0x00,0x6d,0x8a,0x8a,0x0c,0x1a,0x25,0xaa,0xb4,0xb4,0x4c,0x72, + 0x6a,0x1a,0x1c,0xb2,0x8f,0x6f,0x10,0xd0,0x9c,0xae,0x9e,0x01,0x1a,0x97,0x03,0x20, + 0x1e,0x06,0xb7,0x86,0xa6,0x96,0xe4,0xd4,0x4c,0xd8,0xbb,0x8e,0xae,0x91,0x8a,0xaa, + 0x86,0xbc,0x22,0x43,0xe1,0xa1,0x0a,0x32,0x45,0x15,0xee,0x02,0x6c,0x51,0x55,0xd7, + 0xd0,0xc9,0x2b,0xe0,0x6c,0xf8,0x62,0x23,0xb9,0x2f,0xa0,0x30,0x89,0x29,0xc9,0xfa, + 0x86,0x86,0x0c,0xa5,0x47,0x3a,0x7a,0x26,0xf6,0x4e,0x1e,0xf1,0x49,0x29,0x4f,0xcb, + 0xab,0xdb,0xbb,0xfb,0x68,0x84,0x40,0xef,0xa6,0x7e,0x19,0x19,0x1d,0x6f,0x69,0x6b, + 0x07,0xd0,0x0f,0x0e,0x8d,0x66,0xd9,0x38,0x3e,0xd6,0xd5,0x57,0x7a,0xa4,0xae,0xc0, + 0x50,0x55,0x50,0x54,0x85,0x1d,0xc9,0x2b,0x30,0xd0,0xae,0x71,0x7b,0x88,0xb6,0xa0, + 0x05,0x06,0xde,0x13,0x65,0x2d,0x6d,0xbd,0xfc,0x42,0x8e,0xb0,0xb0,0xf0,0x7b,0x1a, + 0x57,0xa5,0xa4,0xa4,0x10,0xfe,0x1a,0x9a,0x7a,0x7a,0x07,0xe6,0xe6,0x17,0x77,0xf5, + 0xf4,0x00,0xc8,0x52,0xb1,0x54,0x70,0x93,0x14,0x14,0x18,0xf3,0x6c,0x19,0x1c,0xa7, + 0x90,0xf0,0x30,0x33,0x4b,0x6b,0x3b,0x27,0x57,0x20,0x89,0x2d,0x6d,0x08,0x7f,0x69, + 0xf8,0x6f,0x6a,0x7a,0xfa,0x9c,0x61,0x76,0x4b,0x6b,0x6b,0x6f,0x7f,0x3f,0x4b,0x6b, + 0x5b,0x70,0x7e,0x6a,0xea,0xea,0x07,0x87,0x87,0x69,0x6a,0x7a,0x80,0x87,0x39,0x34, + 0x3c,0x52,0x5e,0x55,0x1b,0x11,0x9d,0x08,0xbe,0x16,0x78,0x83,0x0f,0x95,0xd4,0xb8, + 0xe7,0x19,0x99,0x22,0x7e,0xaa,0xf9,0x0d,0xdb,0xae,0xa6,0xae,0x0d,0xcf,0x91,0xa8, + 0x08,0x65,0xa5,0x91,0x25,0x8b,0x97,0x78,0x79,0x7b,0xb3,0x6c,0x1d,0x2d,0x6d,0x1c, + 0x62,0x62,0x93,0x9f,0x3d,0x47,0xf8,0x4b,0xc3,0x7f,0xc1,0xc9,0x84,0x61,0x84,0xe6, + 0x41,0xf3,0xf2,0xf2,0x29,0x2a,0x29,0xe5,0x14,0x97,0x75,0xf7,0xf4,0xd2,0x3d,0x68, + 0xef,0xa6,0x80,0xf2,0xb7,0x77,0x76,0xec,0xdf,0x7f,0xe0,0x3d,0xdd,0x0f,0x34,0x26, + 0x24,0x65,0x46,0x50,0x60,0x0c,0x71,0xbe,0xd2,0xea,0xc0,0x15,0x47,0xdc,0x40,0x31, + 0x91,0x89,0xc3,0x9f,0x7f,0x84,0xf2,0x95,0x34,0x89,0x02,0x53,0x78,0x69,0xa9,0x4d, + 0x5c,0x52,0x4c,0x84,0x67,0xb9,0xba,0x29,0xfe,0xa2,0x52,0xb8,0x86,0x0a,0x87,0x39, + 0x7e,0x08,0x43,0xfc,0x54,0x83,0xa8,0xb0,0x81,0x7f,0x4a,0x56,0xde,0x40,0x1f,0x61, + 0xf2,0x2a,0xee,0x84,0x2f,0x11,0x19,0xc6,0x65,0x57,0x5f,0x62,0x7a,0x30,0x42,0x5b, + 0x85,0x61,0x25,0x29,0x03,0xc3,0x25,0x55,0xa4,0x86,0x8a,0xd7,0x25,0x74,0x20,0x1d, + 0xc4,0x16,0xac,0xa2,0x17,0xbe,0x1d,0x7d,0x0d,0x0b,0x02,0x10,0x95,0xb5,0xb8,0x94, + 0x16,0xdf,0x3b,0x4e,0x9f,0x79,0xac,0x9c,0x5b,0xfe,0x8b,0xa4,0xc3,0x78,0x92,0x32, + 0x57,0x24,0x36,0x28,0x81,0x57,0x05,0xd1,0xc4,0xb3,0x93,0xa0,0xfd,0x3e,0x4c,0x1a, + 0xdd,0x47,0x54,0xc5,0x54,0x69,0x15,0xc3,0x21,0x58,0xbe,0x56,0xfc,0x5e,0x09,0xaa, + 0x14,0x2d,0x97,0x29,0x72,0x39,0x4e,0xe4,0x6c,0xd0,0x46,0x59,0xb7,0xb5,0x87,0x59, + 0x42,0x07,0x4d,0xd7,0x1f,0x7a,0xec,0x1b,0x9d,0xff,0x97,0x63,0xeb,0x7c,0xac,0xb2, + 0xa6,0x66,0xef,0xbe,0xfd,0x00,0xaf,0x7b,0xf7,0x1f,0x94,0x3e,0x2e,0x0b,0xb4,0xf7, + 0xc2,0xd5,0x1b,0x97,0xaf,0xdf,0xbd,0x70,0xe3,0xee,0xb5,0xeb,0xb7,0xce,0x5f,0xbc, + 0x22,0x23,0x7b,0xf2,0x90,0xd4,0xd1,0x9d,0xdf,0x7d,0x2f,0x29,0xb9,0x55,0x42,0x42, + 0x42,0x48,0x58,0x98,0x98,0x02,0x86,0xbf,0xc5,0x4b,0x70,0xfe,0xfb,0x07,0xf3,0x7f, + 0xa1,0x05,0x13,0x53,0xa6,0xa7,0x37,0x52,0x29,0x47,0x44,0xc6,0x55,0x54,0xd6,0x0d, + 0x0c,0x8d,0x00,0xf4,0x50,0xc5,0x75,0x3b,0x3a,0x3b,0xc5,0xc5,0xc4,0xe7,0xd9,0xf8, + 0x81,0x83,0x07,0x92,0x52,0x52,0x8d,0x4c,0xcc,0xbd,0x7c,0x02,0x80,0xcb,0x74,0xf5, + 0xf4,0xd3,0xa7,0x25,0xca,0x2b,0x2a,0xd0,0xb4,0x26,0xb8,0x54,0xd0,0xc9,0xf9,0x49, + 0x7d,0xc3,0x8b,0xe7,0x8d,0x2d,0x43,0x23,0x23,0x54,0xba,0x62,0x24,0xb8,0x1a,0x7f, + 0xd5,0xde,0xd1,0xc9,0x29,0x2a,0x0b,0x0e,0x0d,0x0b,0x0c,0x0e,0xcf,0xce,0xcd,0x2f, + 0x29,0x2d,0xcd,0xc8,0xcc,0x0c,0x0c,0x0e,0xf2,0x0f,0x0c,0x8c,0x4f,0x48,0x02,0x04, + 0xc9,0x64,0x67,0x3b,0x38,0x3a,0x30,0x94,0x54,0xef,0xdd,0x93,0x07,0xc4,0x91,0x57, + 0x06,0x9e,0x61,0x02,0x20,0x18,0x1b,0x9f,0x5a,0x5a,0x5e,0x0d,0x5d,0x7d,0xfd,0x66, + 0xf6,0x3c,0xe8,0xaa,0xea,0xda,0xad,0x5b,0xbf,0xa5,0xea,0xe4,0x8f,0x52,0x87,0x53, + 0xd2,0x32,0xf4,0x0c,0x8c,0xbc,0x7d,0x03,0xf3,0x0b,0x4b,0x3a,0xbb,0x7b,0xdf,0x4c, + 0x50,0xcf,0xff,0x62,0x13,0x82,0x00,0xf7,0x45,0x25,0x65,0x11,0x91,0xb1,0xce,0x6e, + 0xee,0x36,0xf6,0x8e,0xd6,0x2c,0x9b,0x59,0x0c,0x15,0xb3,0x74,0x2a,0x2d,0xaf,0x12, + 0x9d,0x7e,0xf2,0x63,0xe2,0x63,0x8d,0x4c,0x98,0x0f,0xe4,0x15,0x95,0x55,0xd5,0xe1, + 0x3c,0xbb,0xb8,0x79,0x26,0xa4,0x64,0x55,0x54,0xd7,0xf7,0x80,0x7f,0x42,0x21,0xee, + 0x85,0xf3,0x0c,0x2e,0xc1,0xe8,0xd8,0xd8,0x8b,0xd6,0xd6,0x92,0xb2,0xf2,0xe4,0x94, + 0xf4,0xc0,0xe0,0x10,0x77,0x6f,0x3f,0xac,0xf8,0xa1,0x9b,0x83,0x93,0x8b,0xa3,0x93, + 0x2b,0x98,0x83,0xa3,0xb3,0xa3,0x93,0x8b,0x03,0x32,0xb4,0x8c,0x0a,0x36,0x3e,0x41, + 0xab,0x1e,0x5e,0xde,0xd5,0xb5,0x35,0x5f,0x7c,0xb1,0xe1,0x3d,0x0d,0xaa,0xff,0xda, + 0xf3,0x43,0x62,0x72,0xb2,0x91,0xb1,0xa9,0xa7,0x4f,0x00,0x3b,0xaf,0x18,0xae,0x23, + 0x4d,0x96,0x2e,0x5c,0x20,0x2d,0xad,0xc7,0xf3,0x6c,0x19,0xee,0x9f,0x80,0xa0,0x60, + 0x4b,0x96,0xad,0xad,0x83,0x4b,0x42,0x62,0x3a,0x78,0x71,0x63,0xe3,0x74,0xf8,0x9b, + 0x93,0x97,0xb7,0x64,0x2e,0xa9,0xbf,0x9e,0xb1,0x91,0x7f,0x50,0xa8,0xb9,0x85,0x55, + 0x68,0x78,0x4c,0x45,0x35,0x26,0x77,0x9f,0xfa,0x85,0x0a,0xf8,0xa0,0xb7,0xe0,0x17, + 0xd5,0x37,0x34,0xe6,0xe4,0xe4,0x05,0x06,0x87,0x3a,0x3a,0xbb,0xb0,0x6c,0x1d,0x66, + 0x5c,0xe5,0x19,0xd7,0x1d,0x2b,0x96,0xc9,0xb2,0x73,0xb0,0xcf,0xce,0x61,0x7f,0xf5, + 0xe5,0x16,0xaa,0x6e,0x2c,0xfe,0x78,0xf1,0x13,0x67,0xb8,0x76,0xce,0x16,0x96,0x36, + 0x51,0x31,0x09,0x40,0xb1,0x91,0x62,0x8a,0x1a,0x7f,0xbb,0x7b,0x7b,0x57,0x2c,0xa7, + 0x0c,0xe3,0xc0,0x47,0x15,0x35,0xd5,0xd9,0xec,0xc2,0xea,0xda,0x06,0x24,0x20,0xa4, + 0xf6,0x28,0x26,0x27,0xa7,0x60,0x47,0xe9,0x99,0x99,0xab,0x56,0xae,0x7e,0x4f,0xf7, + 0x03,0x8d,0x2d,0xdb,0x24,0x2d,0xae,0xdc,0x4c,0xe2,0x2f,0x0f,0x19,0x49,0xe9,0xd1, + 0x74,0x32,0x3b,0x7d,0xfa,0x75,0x96,0x1a,0x1d,0x98,0x44,0xaa,0x87,0xff,0x0b,0xe4, + 0xa7,0xf8,0x6f,0xb9,0xd3,0xc1,0x03,0x3c,0x14,0xe3,0x56,0xa0,0xe2,0xb6,0xd6,0x4b, + 0x4e,0x07,0xe3,0x22,0x28,0xfe,0xd9,0xe1,0x19,0xb3,0xb4,0xf8,0x97,0x31,0xc0,0x1d, + 0xc0,0xe5,0x58,0x64,0x57,0x91,0x00,0x5b,0xa3,0x9b,0x8b,0xbf,0xdd,0xe4,0x4f,0x70, + 0x74,0xc6,0x89,0x33,0x31,0xff,0x8b,0xc1,0x3d,0xde,0x1a,0xb7,0x7c,0xe5,0x8c,0xe3, + 0x25,0x96,0xc9,0x39,0x6b,0xcc,0xb5,0xe8,0xe5,0x86,0xd6,0x09,0xa5,0x16,0x7f,0x55, + 0x2e,0x82,0x98,0xe3,0xc5,0xb2,0xe0,0xb7,0xfc,0xaf,0x81,0x50,0x6d,0x17,0x53,0x6a, + 0x14,0x51,0xac,0x17,0x53,0xa8,0x11,0xfb,0x77,0x89,0xc4,0xad,0x5c,0x54,0x1a,0xeb, + 0x62,0x84,0xc8,0x29,0xbf,0x0d,0xd2,0x2e,0x08,0x82,0xf7,0xe9,0xdd,0x35,0x08,0xfd, + 0xfb,0xbf,0x14,0x09,0xee,0x6a,0x37,0x0f,0x8f,0xed,0x3b,0x76,0x00,0xf9,0x3d,0x72, + 0x54,0x46,0xfa,0xe4,0xc5,0x2b,0x57,0x6f,0xdc,0xbc,0x73,0xef,0xfe,0x7d,0xf9,0x7b, + 0xf7,0x15,0x7f,0xba,0xfd,0xe0,0xda,0xf5,0xdb,0x67,0xce,0x5e,0x3a,0x7c,0xe4,0xe8, + 0x9e,0xbd,0xfb,0xb6,0x6d,0xdb,0x2e,0x26,0xb1,0x19,0x06,0x3d,0xfc,0x75,0x48,0x4b, + 0x05,0x04,0x05,0x96,0x08,0xe0,0x89,0x48,0x78,0x16,0x30,0x1e,0x82,0xfe,0x1d,0xfc, + 0x17,0x38,0x94,0x86,0x86,0xa6,0xaf,0x7f,0xa8,0x89,0xb1,0x55,0x78,0x44,0x6c,0x59, + 0x45,0xf5,0xc0,0xe0,0x30,0x8d,0x64,0xa8,0xa7,0xaf,0xff,0xab,0x2d,0x94,0xe3,0xc0, + 0x0c,0xdb,0xf5,0xcf,0xdd,0xa9,0x19,0xe9,0x46,0xc6,0x4c,0x2f,0x5f,0x18,0x4b,0x8b, + 0x3a,0x3a,0x7b,0x68,0xc6,0x52,0x30,0xad,0xc7,0x74,0x45,0xf6,0xce,0x9c,0x3d,0x5b, + 0xff,0xbc,0x11,0xa0,0xaa,0xbd,0xa3,0x6b,0x62,0x62,0xf6,0x84,0x5f,0xb8,0xee,0xe0, + 0xae,0xf7,0xf6,0x0d,0x94,0x57,0xd4,0xa4,0x67,0x66,0x97,0x95,0x57,0xa5,0xa5,0x67, + 0xfc,0xfb,0xde,0x7d,0x11,0x51,0x31,0x72,0xc2,0x0b,0xce,0xd5,0xca,0x95,0xab,0x8e, + 0x4a,0xcb,0xf8,0xfa,0x83,0x57,0x50,0xe8,0xec,0xe2,0xaa,0xf8,0x50,0x49,0x5e,0xfe, + 0x21,0x43,0x59,0x43,0xcf,0xc0,0xc4,0xc1,0xd9,0x1d,0xc8,0x51,0x55,0xcd,0xf3,0xbe, + 0xc1,0xe1,0x59,0xa9,0x2b,0x5c,0x38,0x00,0x2c,0xaa,0xe9,0xb3,0x5d,0xbb,0x76,0xa5, + 0x67,0x66,0xe9,0x18,0x18,0xbb,0x79,0xfa,0xe7,0xe6,0x17,0x75,0x76,0x53,0xe2,0x20, + 0xd6,0xdb,0x9f,0x39,0xc5,0xc5,0x56,0x58,0x89,0x6c,0x64,0xb6,0x68,0xf8,0xb5,0xb1, + 0xb5,0x03,0x83,0x55,0x7c,0x04,0xb6,0xb5,0xb3,0x27,0x3f,0x35,0x66,0x1a,0x7f,0x36, + 0xbd,0xdc,0xb1,0xa1,0xb1,0x59,0x42,0x62,0xb2,0x92,0x0a,0x90,0x56,0x25,0x25,0x15, + 0x75,0x23,0x53,0x0b,0x00,0xc8,0x94,0xb4,0xac,0xea,0xda,0xfa,0x9e,0xbe,0x81,0x5f, + 0x97,0x32,0x9b,0x9c,0x7a,0x07,0x27,0xc4,0xd8,0xc4,0x4c,0xdf,0xc0,0xd0,0xc8,0xc8, + 0x08,0xfe,0xeb,0xe9,0x1b,0xe8,0xe9,0x19,0xc0,0x7f,0x58,0x26,0x56,0xf5,0x0d,0x75, + 0xf5,0xf4,0xf5,0xf5,0x61,0x19,0x5f,0x45,0x06,0x5b,0x60,0x15,0xbe,0x00,0x0b,0x6a, + 0x8f,0xd4,0x97,0xbe,0xb7,0x77,0x55,0xec,0xd8,0xbe,0x33,0x29,0x35,0xd5,0xc0,0x98, + 0xe9,0xee,0xe9,0x97,0x99,0x5b,0xd0,0xde,0xd9,0x47,0x13,0xc0,0x87,0xcb,0xcd,0x34, + 0xb3,0x98,0x67,0xcb,0x8b,0x3f,0x59,0xec,0xee,0xee,0x6e,0x63,0xe7,0x60,0x63,0xe7, + 0x1c,0x13,0x97,0xd8,0xd0,0xd4,0x06,0x4e,0x08,0x4d,0xb8,0xb8,0xb8,0xa4,0x54,0x50, + 0x70,0x0e,0xa9,0xbf,0x9a,0x9a,0x7a,0x48,0x68,0x98,0xb9,0xa5,0x4d,0x70,0x68,0x54, + 0x69,0x65,0x2d,0xbd,0xdc,0x6e,0xfc,0xf5,0xab,0xc8,0xa8,0x18,0xfc,0x2a,0xdb,0xd9, + 0x3b,0xcc,0x7a,0xb9,0x61,0xbb,0x35,0x76,0xb9,0xc9,0x05,0x1b,0x54,0x95,0xdd,0x41, + 0x45,0x55,0x75,0x05,0xb5,0xee,0x62,0xe1,0x87,0x0b,0xcd,0x2d,0x2c,0x5c,0xdd,0x3d, + 0xcd,0xac,0xec,0xa2,0x63,0x12,0xe0,0xea,0x0f,0x0d,0x8f,0xd2,0x8c,0x81,0x83,0xc3, + 0x23,0x42,0x42,0xeb,0x66,0x6d,0x0a,0xc6,0x90,0xab,0xd7,0xe4,0xea,0x1b,0x9a,0xb2, + 0x73,0x0a,0x5e,0xb6,0x77,0x4e,0x4c,0x50,0x16,0x50,0x85,0x07,0x10,0xe5,0xa6,0xbd, + 0x9e,0x78,0x20,0xaf,0xf0,0x47,0x28,0xc0,0xef,0xb6,0x8f,0x96,0xae,0x5b,0x2f,0x97, + 0x81,0x15,0x91,0x20,0xf0,0x51,0x02,0x43,0x2b,0xa2,0xb6,0x24,0xca,0x81,0xc5,0xca, + 0x43,0x91,0xa0,0x86,0xe9,0x91,0x48,0x49,0x15,0x2e,0x43,0xc2,0x91,0x8e,0x20,0x80, + 0x5c,0x39,0xd6,0xaf,0xeb,0x5b,0x12,0x45,0x1d,0x79,0xf5,0xac,0xfa,0x71,0xc1,0x33, + 0x9f,0x68,0x8a,0xc0,0x38,0x6e,0x53,0x3c,0xe0,0x03,0xd0,0xc4,0xeb,0x6e,0x21,0x1e, + 0xaa,0x4e,0x56,0x69,0xe6,0x17,0x6b,0x71,0x2b,0x71,0x11,0x90,0x3a,0x30,0xcd,0x9d, + 0xd0,0xe4,0x95,0x0a,0xe1,0x09,0xae,0xf0,0x2a,0x5b,0x98,0xbe,0x0b,0x8b,0x6c,0xf7, + 0x92,0x01,0x64,0xb2,0xfc,0x26,0xfc,0xc7,0xf6,0x4b,0xb4,0x43,0xc8,0xcf,0x88,0xca, + 0x1e,0xdd,0x44,0xbc,0x9d,0xcb,0x85,0xb1,0x99,0xdf,0x41,0xd2,0xc1,0xe0,0x75,0x49, + 0xa3,0x0b,0x97,0x63,0xf1,0xde,0x13,0xa1,0xda,0x86,0x0a,0x64,0x29,0xd4,0x8b,0x3e, + 0xa8,0x16,0xbb,0x5b,0x2c,0x7a,0x23,0x57,0xf4,0xa7,0x24,0xf4,0xb2,0xc2,0x93,0x5e, + 0x1b,0xa4,0x6d,0x84,0x0e,0x99,0xed,0xbc,0x68,0xd3,0xd2,0xde,0xf7,0x97,0x23,0x2c, + 0xbd,0x8d,0x8e,0x8f,0x3d,0x90,0x7f,0xb8,0x7d,0xfb,0x8e,0x3d,0x7b,0xf7,0xcb,0x1c, + 0x3f,0x71,0xe1,0xd2,0xb5,0xeb,0x37,0xef,0x3c,0x50,0x50,0x66,0x28,0x3d,0x52,0x64, + 0xa8,0xdd,0x97,0x57,0xba,0x79,0xfb,0xdf,0x17,0x2e,0x5d,0x39,0x2e,0x7b,0xf2,0x87, + 0x7d,0xfb,0xb7,0x6d,0xdf,0xb1,0xf9,0xab,0x2d,0x1b,0x36,0x6c,0xc4,0xf1,0x77,0xd9, + 0xb2,0xcf,0x96,0x2c,0x16,0xf8,0x78,0xd1,0xc7,0x40,0x81,0x3f,0x5c,0x80,0xc0,0x17, + 0x97,0x60,0xfd,0x0e,0x15,0x16,0xfc,0x56,0x91,0xa1,0x18,0x18,0x12,0x66,0x68,0x6a, + 0x15,0x16,0x11,0x55,0x52,0x5a,0xd9,0x0f,0x1e,0x2f,0xf5,0x18,0x32,0x30,0x34,0x04, + 0x7d,0x9e,0x67,0xe3,0x5b,0xbf,0xd9,0x96,0x9a,0x9e,0xc1,0x64,0x5a,0x78,0x7a,0xfb, + 0x67,0xb3,0x0b,0x00,0x7f,0x27,0xde,0xd0,0x65,0x7c,0x00,0xeb,0x59,0xf0,0xc1,0xec, + 0x2e,0x84,0xe0,0xd2,0x4f,0x43,0xc2,0x42,0x4b,0xcb,0x2b,0x2b,0xab,0xeb,0xfa,0xfa, + 0x07,0xa9,0x92,0x7a,0xc0,0xe7,0x1f,0x7f,0xf5,0xaa,0xe9,0x45,0x6b,0x79,0x65,0x75, + 0x4d,0x5d,0x9d,0xd6,0x63,0x6d,0x51,0x51,0x51,0xaa,0x64,0x19,0xc0,0x32,0x59,0xd9, + 0x13,0x71,0x09,0x89,0xc1,0x21,0x61,0xaa,0x6a,0x8f,0x1e,0x28,0x30,0x54,0xd4,0x34, + 0x0d,0x99,0x2c,0x2f,0xbf,0x20,0x76,0x5e,0x7e,0x6b,0x7b,0x27,0xd5,0xfc,0xe0,0xf0, + 0xe8,0xc8,0xce,0x9d,0xdf,0xcd,0x7a,0xb6,0xc1,0x53,0x4a,0xcb,0x4c,0x07,0x1c,0x77, + 0x73,0xf7,0xc9,0x61,0x17,0xb5,0x77,0x74,0xd3,0x14,0x2e,0x98,0xfa,0x79,0xca,0xca, + 0xca,0x1a,0x8f,0x63,0x80,0x91,0x0b,0xfc,0x36,0x63,0xe3,0x8c,0xdd,0x09,0x09,0x09, + 0x39,0xbb,0xba,0x87,0x84,0x85,0x33,0x18,0xca,0x00,0xc1,0xaa,0xea,0x9a,0xa6,0xe6, + 0x56,0x3e,0xbe,0x81,0x59,0xd9,0x05,0x75,0xf5,0x4d,0x03,0x43,0x23,0x33,0xd0,0x1f, + 0xe0,0xb8,0xbc,0xa2,0x6a,0xc7,0x8e,0xef,0x50,0x15,0x71,0xac,0x8a,0x1a,0x76,0xff, + 0xa0,0xff,0xb0,0x4c,0xac,0x2e,0x58,0x88,0x3e,0xe2,0xaa,0xfb,0xf0,0xff,0xc8,0xc7, + 0x5b,0x80,0x7d,0x81,0xeb,0xec,0xbd,0x27,0xdb,0x2a,0xf9,0x4d,0x7a,0x46,0xa6,0x31, + 0xd3,0xdc,0xcd,0xc3,0x37,0x9b,0x9d,0xd7,0xde,0x31,0x47,0x96,0xae,0xe3,0x13,0xa7, + 0x79,0xb6,0x0c,0x67,0x12,0xbd,0x0b,0xe3,0x89,0xab,0x8d,0xc3,0x93,0xd8,0xf8,0xe4, + 0xe7,0x8d,0x2f,0x30,0x91,0x12,0x25,0xfe,0x56,0xd7,0x3e,0x5b,0xbd,0x6a,0x0e,0x5a, + 0x77,0xff,0x81,0x7c,0x64,0x74,0x8c,0x99,0x85,0x55,0x70,0x68,0x64,0x69,0x79,0x55, + 0xff,0xc0,0x20,0x92,0x0a,0x53,0x34,0xd8,0x37,0xd0,0x2f,0x23,0x73,0x9c,0xfe,0x72, + 0x53,0x5d,0x77,0xfa,0x84,0x2f,0xb8,0x22,0xe0,0x30,0xf9,0xf8,0x07,0x98,0x5a,0x58, + 0x47,0x44,0xc6,0x56,0x54,0xd5,0x0d,0x0e,0xcf,0xee,0x3d,0xe2,0xf6,0xfa,0xcd,0x1b, + 0x31,0x8a,0x28,0x16,0x3c,0x68,0xbe,0x7e,0xfe,0x85,0x9c,0xe2,0xa2,0x92,0xf2,0xae, + 0x9e,0x01,0x9a,0x84,0x85,0x29,0x34,0x91,0xf1,0x0a,0xdc,0xbc,0x4d,0x73,0xbd,0xa8, + 0xe2,0x3d,0xd9,0x82,0x05,0x8b,0x84,0x65,0x9d,0xc5,0xb1,0x54,0x1a,0x09,0x0d,0x22, + 0x48,0x8b,0xea,0x41,0x91,0x68,0xa5,0xd1,0x0b,0xab,0x78,0x02,0x2c,0x1f,0x7a,0x12, + 0x88,0x83,0x2b,0x9d,0xd0,0x4b,0x1c,0x90,0x8c,0x8a,0x40,0x67,0x5c,0x8e,0x85,0x89, + 0xb5,0x7a,0x79,0x60,0xad,0xc5,0x95,0x22,0xe3,0xca,0x2b,0x3e,0x32,0xbb,0x49,0xab, + 0x0f,0x4f,0xbc,0x25,0xf3,0x8f,0x88,0xce,0x68,0xf1,0xe4,0x58,0x58,0xd0,0x9b,0xab, + 0x40,0xd6,0xe2,0xbe,0x3d,0x41,0xb3,0x03,0x2f,0xae,0xc5,0x1f,0xac,0x86,0xae,0x4a, + 0x68,0x12,0x99,0x4d,0x78,0x08,0x9d,0xac,0x58,0x85,0xff,0x56,0x9c,0x1b,0x97,0xc6, + 0x8f,0x85,0x54,0x88,0x4d,0xd3,0x63,0x13,0x9d,0xec,0x27,0xdd,0x09,0x7e,0xa6,0xcc, + 0xcf,0xfd,0xc5,0x79,0x51,0x6e,0x0c,0x9d,0x31,0xfe,0x8b,0x52,0x9b,0x35,0xb0,0x97, + 0x43,0x61,0xbc,0x1e,0x8f,0xa8,0x4f,0xab,0x91,0x85,0x2a,0x45,0x37,0x8b,0x32,0x1a, + 0x44,0x15,0x6a,0xc5,0xee,0x96,0x88,0xdf,0xe5,0x88,0x5e,0x4b,0x17,0xbd,0x1c,0x2b, + 0x72,0x3a,0x70,0xa3,0xac,0xdb,0xba,0xc3,0x36,0x62,0xc7,0x2c,0xa2,0x32,0x6b,0xfe, + 0xe6,0xb5,0xb0,0x1a,0x9a,0x9a,0xf6,0x1f,0x38,0xf8,0xdd,0xf7,0xff,0x3c,0x24,0x75, + 0xe4,0xd4,0xd9,0xf3,0x57,0xe4,0x6e,0xde,0x07,0x0a,0xa3,0xa6,0xfe,0x48,0x43,0x4b, + 0x49,0x53,0x17,0x16,0xe4,0x15,0x19,0x57,0xe4,0x6e,0x9d,0x3c,0x75,0xee,0x47,0xa9, + 0xc3,0xdf,0xef,0xda,0x2d,0x29,0x29,0x29,0x26,0x2e,0x2e,0xbc,0x76,0xed,0xe7,0x2b, + 0xd7,0xa0,0x42,0x1c,0xd8,0x14,0x30,0x5e,0x88,0x03,0xe5,0x02,0x7f,0x40,0xbc,0x11, + 0xe9,0xb7,0x8e,0x8d,0xe0,0xee,0xde,0xbe,0x73,0x27,0x22,0x3a,0xd2,0x88,0x69,0x16, + 0x14,0x1c,0x59,0xfc,0xb4,0x1c,0xd0,0x8d,0xe6,0xc9,0x1d,0x7b,0x35,0xbe,0x67,0xcf, + 0x0f,0xf3,0x6c,0x1c,0x1e,0xcc,0xb4,0xac,0x4c,0x96,0x9d,0x93,0x6f,0x40,0x48,0x7e, + 0x61,0x71,0x67,0x57,0xef,0x6b,0xea,0xf8,0x33,0x18,0x30,0x82,0x59,0xfb,0x0f,0x48, + 0x77,0xe4,0xa8,0x74,0x45,0x55,0x4d,0x46,0x56,0xce,0xf3,0xc6,0x96,0xd1,0xb1,0x71, + 0xaa,0x9c,0xd0,0xb7,0x93,0xef,0xfa,0xfa,0x87,0x1a,0x9b,0xdb,0xaa,0x6a,0xea,0xae, + 0xca,0xdd,0x98,0xf3,0x6c,0x40,0xcb,0x1b,0xbe,0xd8,0xe0,0xe2,0xea,0x16,0x9f,0x98, + 0xc8,0x50,0x56,0x91,0x57,0x78,0xa8,0xa9,0xad,0x6b,0x67,0xff,0x24,0x22,0x2a,0xae, + 0xaa,0xf6,0x19,0x8c,0x2d,0x54,0x3b,0x02,0xd4,0xe3,0x4f,0x05,0x22,0xed,0xeb,0x7f, + 0x48,0x66,0xb3,0xd9,0xba,0x86,0x86,0xce,0x6e,0xde,0x59,0xec,0xfc,0xb6,0xf6,0xae, + 0x57,0xd4,0x49,0xa6,0xc0,0x2c,0x1c,0x9d,0x5c,0xfe,0xe0,0x28,0xb4,0x7e,0xdd,0x17, + 0x61,0x91,0x51,0xde,0xbe,0x01,0x8a,0x8a,0x0f,0x15,0x14,0x14,0xd5,0x35,0x1f,0x9b, + 0x99,0xb3,0xfc,0x83,0x42,0xb3,0x72,0x72,0x1b,0x9b,0x5f,0x0e,0x0d,0x8f,0xbc,0xc3, + 0x0a,0x73,0xf2,0xef,0x37,0x2d,0x33,0x6b,0xf3,0x97,0x7f,0xcd,0x98,0x39,0xa7,0x6d, + 0x96,0xd8,0x9c,0x9a,0x96,0xce,0xb2,0x75,0xf4,0xf1,0x0f,0xce,0xcd,0xe3,0xb4,0x77, + 0x75,0xd3,0x09,0xd8,0xfe,0xef,0x17,0x0f,0x9f,0xf9,0x16,0xa3,0x86,0x9b,0x01,0x88, + 0x24,0x34,0xeb,0xe4,0xea,0x99,0x98,0x9c,0xd6,0xd8,0xdc,0x82,0x5e,0xee,0x40,0x4d, + 0x12,0x9b,0x9a,0x9b,0x85,0xe7,0x2a,0x48,0x2e,0x77,0xe3,0x66,0x54,0x5c,0x82,0xb1, + 0xa9,0x05,0x9c,0xf0,0xa7,0x65,0x95,0xd8,0x8b,0x0f,0x28,0x9f,0x9d,0xe1,0xd1,0xe1, + 0x93,0xf3,0xce,0x96,0xfa,0x4d,0x06,0x4f,0xb1,0xba,0xa6,0x46,0x50,0x68,0x38,0x13, + 0xd5,0x2d,0x89,0x2a,0xaf,0x44,0xf8,0x3b,0x45,0x1b,0x37,0x96,0x94,0x9c,0xbd,0x6e, + 0x27,0x38,0x90,0xe0,0xe4,0xa6,0x65,0xb0,0xeb,0xea,0x9b,0x47,0x68,0x6b,0x4e,0xbe, + 0x7d,0x3b,0x09,0x5f,0x48,0x4c,0x4e,0x7e,0xaf,0xfe,0x18,0xbd,0xad,0xd8,0x76,0x0b, + 0xd5,0xa2,0x44,0xd5,0x20,0x67,0x96,0xb4,0x22,0x51,0x8c,0x1f,0x6e,0x28,0x15,0x47, + 0xd3,0xb3,0x78,0x66,0x6a,0xb4,0x90,0xc4,0xba,0x17,0x17,0x2d,0x23,0x0d,0x95,0x16, + 0x2a,0xd0,0xc1,0xab,0x52,0xf5,0xab,0xba,0xd3,0x33,0x45,0x53,0x64,0x95,0x2a,0xed, + 0x69,0x82,0x2b,0xb4,0xaa,0xd1,0x4b,0xaf,0x83,0xe2,0x2f,0xe1,0x85,0x2b,0xac,0xbe, + 0xd4,0xee,0xc5,0x6b,0x70,0x71,0x03,0xec,0x98,0xb2,0x8b,0xaf,0xe0,0x15,0xa1,0xec, + 0xc2,0xaa,0x5d,0x91,0x0d,0x92,0x9f,0x4e,0x2b,0xf0,0x85,0x5e,0x39,0x01,0x9e,0x43, + 0x37,0x56,0xcc,0x84,0xa7,0x0a,0xe3,0x95,0xe1,0xe2,0x2a,0xc7,0x90,0xff,0xc0,0xcf, + 0x82,0x55,0x3b,0xc4,0x95,0x5f,0x88,0xa0,0x89,0xe0,0x6a,0xd1,0xbb,0xc5,0x12,0xb7, + 0xd8,0xe2,0x57,0x53,0x44,0x81,0x02,0x9f,0xf2,0xda,0x70,0xcc,0x61,0xed,0x61,0x0b, + 0x15,0xab,0x98,0xd7,0xd4,0x9e,0xdb,0xdf,0xc1,0xc2,0x23,0xa3,0xb6,0x6d,0xdb,0xb1, + 0x7b,0xcf,0xde,0xa3,0xd2,0x40,0x7e,0xaf,0xde,0xbd,0x27,0xaf,0xa4,0xa2,0xae,0xa2, + 0x65,0xa8,0x6f,0x60,0xf4,0x58,0xd7,0x58,0x4d,0x53,0xe7,0x36,0x43,0xf5,0xe6,0xad, + 0x3b,0x67,0xce,0x5d,0x94,0x3a,0x7c,0x64,0xd7,0xbf,0xf6,0x6c,0xdd,0xba,0x15,0x5c, + 0xd6,0xb5,0xeb,0xd6,0xad,0x5a,0xbd,0x7a,0xf9,0xf2,0xe5,0x82,0x82,0x82,0xf8,0xeb, + 0x80,0x17,0x2d,0x5c,0xf4,0xd1,0x87,0x1f,0x01,0x49,0x21,0x6b,0x61,0xfd,0x26,0x16, + 0x0c,0x5f,0xbe,0x72,0xf5,0x5a,0x54,0xcc,0xff,0x33,0x77,0xdd,0x51,0x51,0x5c,0x5d, + 0xfc,0x9f,0x2f,0x45,0x4d,0x62,0x47,0x9a,0x25,0xd4,0x05,0x14,0xa3,0x31,0x92,0xc4, + 0x44,0x8c,0x1a,0x5b,0x62,0x10,0xe5,0x4b,0xfc,0x10,0x35,0x46,0x63,0x01,0x14,0x69, + 0xd2,0x7b,0xef,0x45,0x7a,0x51,0x90,0xde,0xdb,0xb2,0x2c,0x48,0xef,0x28,0x76,0x50, + 0x94,0x5e,0x64,0x97,0xa5,0x85,0x2a,0x96,0x9c,0xf3,0xbd,0x37,0x6f,0x76,0x18,0x16, + 0x76,0x58,0x8d,0x68,0x38,0xf7,0xec,0x99,0x9d,0x9d,0x79,0xf3,0x66,0x98,0x99,0xdf, + 0xfb,0xdd,0x77,0xef,0xef,0xa6,0xd9,0xd8,0x39,0x47,0xc5,0x24,0x56,0x55,0x03,0xfc, + 0xed,0xa5,0xc8,0x21,0x1d,0x7b,0x36,0xb1,0x77,0xef,0x4f,0x02,0x36,0x2e,0x21,0x21, + 0x55,0x54,0x5a,0x1a,0x15,0x93,0x90,0x49,0xcf,0xa9,0xbd,0xf5,0x80,0xc5,0xe6,0x4c, + 0x50,0x66,0xa7,0x06,0x87,0x84,0xcc,0xe8,0xd7,0x85,0xa5,0x1c,0x02,0x83,0x8a,0xcb, + 0xaa,0xf2,0x0b,0xcb,0xda,0x3a,0x3a,0x29,0x48,0xf4,0xf0,0xc8,0x18,0x8b,0xdd,0xd3, + 0xda,0xd6,0x76,0x44,0x5d,0x83,0x3a,0xc3,0x82,0x6c,0xe2,0xa2,0xe2,0x6e,0xee,0x1e, + 0xa9,0xe9,0xe9,0x7a,0x06,0x86,0x17,0xf5,0x2e,0x81,0x4b,0x11,0x16,0x1e,0x5d,0x5a, + 0x5e,0x0d,0x15,0x05,0xc7,0x66,0x0e,0xfe,0x6c,0x6c,0x6e,0x06,0x14,0x78,0x7a,0x53, + 0x34,0x59,0xb9,0xdc,0x82,0x42,0x2b,0x5b,0xc7,0x80,0xe0,0xf0,0xfc,0xc2,0x92,0xd6, + 0x76,0x58,0xf5,0x89,0xe2,0x94,0x01,0xd7,0xf8,0x87,0xaf,0x20,0xf0,0x1f,0x54,0x90, + 0x57,0x48,0xcd,0x4c,0x0f,0x0d,0xbb,0x72,0x4e,0xf3,0xfc,0x05,0x1d,0x7d,0x63,0x13, + 0x4b,0x37,0x0f,0xef,0x6b,0xd1,0xf1,0x65,0x15,0xd5,0x8d,0xcd,0xad,0x50,0x76,0x7b, + 0xea,0xab,0x18,0xfc,0x7f,0xe9,0x8c,0x1c,0x51,0x11,0xb1,0x77,0x96,0xb0,0x29,0xb8, + 0x7d,0xbe,0x46,0x22,0xf7,0x7a,0x7e,0x64,0x54,0x7c,0x7a,0x66,0x4e,0xcd,0xcd,0xbb, + 0xec,0x9e,0xde,0xd1,0x31,0x2a,0xfe,0x1b,0x9f,0x98,0x2c,0xe0,0x3f,0x1a,0xc0,0x84, + 0xa3,0xb3,0x73,0x16,0x23,0x27,0x2e,0x31,0xa5,0xb8,0xb4,0xaa,0xad,0xbd,0x73,0x78, + 0x64,0x84,0x62,0x92,0xb4,0xb5,0xbd,0x4d,0x4a,0x4a,0x86,0xba,0x4d,0x75,0x75,0x75, + 0x7a,0x4e,0xae,0x8d,0x83,0x4b,0x44,0x54,0xec,0x8d,0xda,0x3b,0xec,0x1e,0x88,0xbf, + 0xfc,0xda,0x04,0x63,0xd7,0x23,0x1a,0x73,0xa5,0xd0,0x78,0x4e,0x13,0x30,0xf1,0x34, + 0x7b,0x27,0xb7,0x98,0xf8,0xe4,0xda,0x3b,0x0f,0x7a,0x7a,0x07,0x28,0xe2,0xc6,0xc1, + 0xa0,0xf2,0xdb,0x6f,0xb7,0xcc,0xd8,0x8e,0xbe,0xbe,0xc1,0xfd,0xba,0xfa,0xaa,0xea, + 0xda,0x8e,0x2e,0xd6,0xd0,0x30,0x5f,0x29,0x78,0xe8,0x7c,0x1e,0x7e,0xd6,0xdb,0xdf, + 0x7f,0xe6,0xec,0xb9,0xf7,0x78,0xb7,0x2c,0x5c,0xbd,0x09,0x96,0x0c,0xe0,0x4e,0xf8, + 0xe2,0x24,0x0e,0x8f,0x2c,0xc2,0x68,0x1d,0x06,0x1c,0x6b,0x4d,0x27,0x25,0xad,0x30, + 0x75,0x29,0xf4,0x95,0x43,0x84,0x63,0xc9,0x4c,0x09,0x4c,0x9a,0x12,0x61,0x45,0x4c, + 0xaa,0x4e,0x8a,0x6f,0xe0,0xed,0x70,0x48,0xde,0x5a,0x54,0x7f,0x10,0x9f,0x9f,0x45, + 0x81,0xc7,0x28,0x25,0x0a,0x6a,0x4f,0xa1,0x6a,0x0e,0xa6,0xbd,0x44,0xea,0x10,0x69, + 0x62,0x1a,0x75,0x80,0x83,0xdc,0xc5,0xdc,0x22,0x11,0x6c,0x1a,0x11,0x76,0x05,0x29, + 0x7c,0x0f,0x6c,0xc1,0x84,0x54,0x95,0x09,0xd3,0x76,0xe6,0x46,0x94,0x71,0x05,0xaf, + 0x48,0x73,0xc1,0x93,0xfd,0xe4,0x4e,0x1c,0x63,0x8c,0x1e,0xe7,0xb9,0x48,0x33,0x04, + 0x75,0x15,0xcd,0xfc,0x62,0xd5,0x91,0x38,0x93,0x9e,0x7c,0x53,0x5c,0x58,0x7b,0x1d, + 0x46,0xc0,0x61,0x30,0x39,0xe8,0x06,0x24,0xc5,0x6c,0xa2,0x82,0x21,0xbc,0xec,0x7a, + 0x8d,0x80,0x05,0xcb,0x6a,0xd5,0x4a,0x9d,0xbe,0x21,0x73,0xa2,0x48,0x5a,0x23,0x4b, + 0xea,0xd7,0x38,0x40,0x81,0xd7,0xec,0x73,0xdf,0x7e,0x2a,0xa4,0x8b,0x3d,0xf8,0xde, + 0x41,0x96,0xef,0xfd,0xff,0xea,0x85,0x93,0x93,0xf3,0x97,0x9b,0x36,0x6f,0xdf,0xf1, + 0xe3,0x01,0x55,0xb5,0x63,0xc7,0x4f,0x6a,0x5d,0xd0,0x35,0x36,0xb1,0xb0,0xb5,0x77, + 0xb0,0x76,0xf4,0x72,0x70,0x74,0xb2,0xb6,0xb1,0x37,0x34,0x32,0x3f,0xa7,0xa5,0xa3, + 0xa6,0xfe,0xc7,0xde,0x7d,0xbf,0x6c,0x55,0xde,0xf9,0xd5,0x26,0x25,0x05,0x05,0x05, + 0x34,0x05,0x2c,0x24,0x24,0x04,0x13,0x81,0xb1,0x72,0x48,0xf3,0xe7,0xcd,0x47,0x5a, + 0x58,0x84,0x73,0xf2,0x75,0x67,0x81,0x55,0x0f,0x1e,0xca,0xc2,0x32,0x3e,0x22,0xa2, + 0x63,0xc1,0x73,0xd7,0xcd,0xa6,0xc2,0x5f,0xf0,0x72,0x51,0x55,0x3d,0x24,0x60,0xcb, + 0x2b,0xc5,0x57,0x55,0x56,0x57,0x17,0x16,0x95,0x55,0xd7,0xdc,0x78,0xfc,0xa4,0x75, + 0x60,0x70,0x84,0xc2,0x3b,0x07,0x2c,0x2e,0x3e,0x7e,0xc6,0xb4,0x08,0x49,0x09,0xc9, + 0xaa,0xea,0x9a,0x8c,0x2c,0x66,0x59,0x45,0xcd,0x53,0x56,0xcf,0x28,0xff,0x80,0xcc, + 0xfe,0x81,0x81,0xde,0xbe,0x3e,0x2f,0x6f,0xcf,0xd7,0xd5,0x81,0x17,0x13,0x15,0x07, + 0x6f,0xe6,0x80,0xd0,0x50,0xed,0x0b,0x17,0x4d,0x4c,0x2d,0xbd,0x7d,0xfc,0x33,0xe9, + 0xcc,0xba,0x87,0xb0,0x4a,0xdd,0x8c,0xaf,0xa0,0x89,0x17,0xcf,0x8d,0x8c,0x4c,0x66, + 0xe8,0xaa,0xa4,0x14,0x3d,0x87,0x69,0x65,0x6b,0xeb,0x1f,0x10,0x72,0x3d,0xbf,0xb8, + 0xa5,0xbd,0x63,0x64,0x64,0x82,0xe2,0x25,0x9f,0x98,0x9c,0xf6,0x56,0x5e,0x44,0xca, + 0xdb,0xb6,0x97,0x96,0x57,0xd8,0x39,0x3a,0x69,0x69,0x9d,0xbf,0x70,0xd1,0xd0,0xd4, + 0xcc,0xc6,0xd3,0x2b,0x20,0x31,0x25,0xbd,0xb2,0xa6,0xb6,0xad,0xfd,0xe9,0xf0,0xc8, + 0x28,0x4f,0x52,0xf3,0xc4,0x8b,0x17,0x80,0x0c,0x2e,0x13,0xb8,0x78,0xee,0x3b,0x33, + 0x71,0xf1,0x95,0x79,0xf9,0xf9,0x80,0xbc,0x57,0x56,0xd6,0x3e,0x69,0x6a,0x1b,0x18, + 0x1c,0xa4,0x1e,0xb3,0xd1,0x19,0xf4,0x59,0xb3,0x84,0x90,0x81,0xc1,0x86,0xa5,0xb5, + 0xcd,0xcd,0x5b,0xb7,0xc1,0x40,0xee,0x7e,0x5d,0x43,0x4f,0x6f,0xdf,0xd8,0x18,0x15, + 0xb3,0xee,0xea,0xea,0x5e,0xb7,0x6e,0x3d,0x75,0x9b,0x2a,0x2a,0x07,0xb2,0x19,0xb9, + 0xd6,0xb6,0x0e,0x11,0xd7,0x60,0xb8,0x7b,0x37,0x8b,0x4d,0x3d,0xff,0x7b,0xe2,0xd4, + 0x2c,0x35,0x95,0xde,0xd8,0x8e,0x1c,0x39,0x9a,0x91,0x9d,0xe5,0xe0,0xec,0x0a,0xf0, + 0xb7,0xfa,0xd6,0x6d,0x4e,0x5f,0xdf,0x04,0xff,0xa4,0x5d,0x60,0x3b,0x66,0x8a,0x58, + 0xfe,0xe4,0x93,0x4f,0xd2,0xb3,0xe8,0x77,0xee,0xd6,0xd5,0xd5,0x37,0x40,0x3f,0xd8, + 0x04,0xff,0x5c,0xaa,0x17,0x2f,0x47,0x46,0x46,0x1f,0xd4,0xd7,0x2b,0x2a,0xce,0x72, + 0x89,0xe6,0xd4,0xe6,0x2f,0x14,0x95,0x3e,0x57,0x83,0x9c,0xb1,0x6b,0x8d,0xdb,0x27, + 0xa7,0x5c,0x21,0x68,0xf6,0xa2,0x82,0x47,0xb2,0x48,0x67,0xc3,0xb8,0x9b,0x90,0xb4, + 0xc2,0x93,0x67,0x51,0xd6,0x2d,0xee,0x9d,0xe6,0xfa,0x93,0x71,0x2e,0x09,0x95,0x37, + 0x88,0xa2,0x09,0x93,0x9c,0x14,0xf3,0x18,0x83,0xc6,0xa7,0x48,0x4b,0x4d,0xce,0xa5, + 0xce,0x98,0x43,0x04,0x21,0x4f,0x9e,0x5b,0x08,0x98,0xd8,0x77,0x12,0xbb,0x49,0x8a, + 0x1f,0x48,0xe1,0x4a,0x0e,0x0f,0xaf,0xea,0xc6,0x05,0xaf,0x60,0x61,0x41,0xf2,0xcc, + 0x32,0x69,0x62,0x1a,0x1d,0xce,0x78,0xf2,0x70,0xa8,0x93,0x5c,0x28,0xef,0xc3,0xa8, + 0x3a,0xa1,0x37,0x42,0x38,0xcf,0x7b,0x91,0x7a,0x27,0x76,0x44,0xcc,0x67,0x6e,0xc4, + 0xc2,0x87,0x19,0xd8,0xfc,0x32,0x9c,0xa4,0xc6,0x16,0x68,0x66,0x7d,0x72,0x66,0x78, + 0x05,0x46,0x4c,0xd8,0x84,0x45,0x92,0x89,0x06,0x14,0xb8,0x49,0x46,0xf7,0x89,0xac, + 0xf6,0x5d,0xd9,0xb3,0x35,0x32,0xa7,0x2a,0x68,0xbf,0x33,0xa4,0xd5,0x93,0x24,0x55, + 0xc3,0x24,0xf6,0x5f,0x96,0x3e,0xe0,0x7b,0xf7,0x51,0xe7,0xfb,0x05,0x59,0x0a,0x1b, + 0x9f,0x98,0x00,0x54,0x4b,0xe9,0xeb,0x6f,0x7f,0xdc,0xf5,0x93,0xda,0x7f,0x7f,0x3b, + 0x71,0x46,0x4b,0xd7,0xd0,0xc4,0xc6,0xd6,0xd1,0xce,0xc5,0xcf,0xdd,0xcb,0xd7,0xd9, + 0xd3,0xdf,0xd6,0xc9,0xc3,0xcc,0xdc,0x46,0xfb,0xa2,0xde,0xef,0x27,0x4e,0xab,0xa8, + 0xaa,0xed,0xd8,0xb9,0x0b,0xcb,0x42,0x52,0x94,0x92,0x92,0x5e,0xb3,0xe6,0x73,0x61, + 0x61,0x61,0x80,0xbf,0x8b,0x17,0x2e,0x41,0x5a,0x58,0x90,0xff,0x62,0x5e,0x68,0x54, + 0x0e,0x09,0xdd,0x99,0x82,0xa3,0xf0,0xae,0x1f,0x77,0x67,0x66,0xe7,0xd8,0xda,0xbb, + 0x00,0xd2,0x51,0x5a,0x05,0xbd,0xc4,0xe3,0xe3,0xcf,0xf8,0x41,0x06,0x60,0x52,0x1a, + 0x1a,0x47,0x05,0x6c,0x79,0x85,0xd0,0x8a,0xf2,0xca,0xaa,0xa6,0x96,0xb6,0xce,0x2e, + 0x16,0x40,0x46,0x18,0xcb,0x41,0x29,0x8d,0x92,0x9a,0x9e,0xb9,0x68,0x26,0x91,0x3d, + 0x70,0x44,0x40,0x2e,0x12,0x93,0x33,0x6a,0x6f,0x3f,0xe0,0xf4,0x0e,0xf2,0xf3,0x09, + 0x4f,0x4c,0xbc,0x18,0x1d,0x1f,0x03,0x88,0xbf,0x7a,0xf5,0x9a,0x37,0x78,0x96,0xb7, + 0x2a,0x6f,0xcb,0x2f,0x2e,0xb2,0xb6,0x73,0xd0,0xd1,0x37,0xb2,0x71,0x70,0x8b,0x8d, + 0x4b,0xae,0xb9,0x09,0x18,0x0d,0xdf,0x29,0xb0,0x92,0xb2,0xf2,0xa5,0xd3,0xa4,0xc0, + 0x56,0xae,0x5c,0x9d,0xc9,0xc8,0xb6,0xb3,0x77,0xbe,0xec,0x17,0x44,0x67,0x16,0x63, + 0x4e,0x4e,0xaa,0x24,0xd3,0x9c,0xdc,0xdc,0xb7,0xf2,0x22,0xfa,0xe0,0x3f,0x1f,0x6c, + 0xd9,0xf2,0x1d,0x38,0x77,0x57,0x37,0x77,0x2d,0x2d,0xed,0xf3,0x3a,0x06,0xa6,0xe6, + 0xd6,0x5e,0x9e,0x41,0x09,0x49,0xa9,0x95,0x35,0xb7,0xdb,0x3a,0xba,0xe1,0x5c,0xe7, + 0x54,0x08,0x1e,0x9f,0x18,0xf7,0xf0,0xf4,0xa6,0x50,0x35,0x7c,0x2f,0xb6,0x42,0x48, + 0x18,0xe0,0x6f,0x4b,0x5b,0x7b,0x7b,0xe7,0x53,0x4e,0xff,0x20,0x45,0xfc,0x0f,0xb2, + 0xb2,0xf2,0x32,0xf0,0x14,0x08,0xd8,0xb8,0xa9,0xb9,0xe5,0x53,0x16,0xab,0xb5,0xbd, + 0x83,0xd3,0xdb,0x37,0x34,0x34,0x4c,0xa1,0x33,0x03,0x8c,0xd3,0xc7,0x51,0xda,0x3c, + 0x83,0x8b,0x83,0x6c,0x3b,0x76,0xee,0x04,0x6c,0xdd,0xda,0xce,0xe5,0x4a,0x64,0x74, + 0x45,0xe5,0xcd,0xce,0xee,0x5e,0x8a,0x70,0xbb,0xf1,0x89,0x67,0x7a,0xfa,0x06,0x73, + 0x74,0xdd,0xf6,0xab,0xfc,0x92,0x9b,0x5f,0x68,0xef,0xe8,0x7a,0x2d,0x3a,0xae,0xaa, + 0xe6,0x0e,0x18,0xa6,0x52,0x17,0x83,0x3e,0x74,0xe8,0xf0,0xf4,0x46,0xb6,0x6e,0x55, + 0x6e,0x6e,0x69,0x7d,0xf4,0xb8,0xb1,0x9b,0xc5,0x19,0x19,0x1d,0xa7,0xb8,0xf2,0x2f, + 0x5e,0xbe,0x1c,0x1b,0x1f,0x0f,0x0a,0x0e,0x99,0xf7,0xb1,0x40,0xd5,0x48,0xe7,0xc8, + 0x3e,0x9a,0xb7,0x78,0xcd,0xe1,0x04,0x98,0x23,0x43,0x84,0x27,0x21,0x87,0x30,0x14, + 0xc7,0x40,0xa9,0xaf,0xbd,0x84,0xb4,0x23,0x2a,0xda,0xcb,0x8d,0x70,0xe6,0x4c,0x91, + 0xa5,0xe2,0x55,0xa9,0x9a,0x04,0x44,0x5c,0x4a,0x0b,0x01,0xe8,0x54,0xa2,0x8d,0xb7, + 0xcc,0xdd,0x18,0xc5,0x15,0x13,0xb9,0x3c,0x48,0x77,0x1a,0x57,0xc9,0x20,0xa2,0x8e, + 0xb9,0xdd,0x20,0xb0,0x1b,0x05,0x6b,0x71,0xd9,0x77,0xef,0xf4,0x29,0xda,0x29,0xe1, + 0x58,0xa6,0x44,0x38,0x56,0x2f,0x79,0x5f,0x80,0x98,0x04,0xc4,0xf3,0xa0,0x3f,0xe1, + 0x8e,0xc6,0x3c,0xde,0xa8,0xe2,0x12,0x1b,0x0d,0x3f,0xc0,0x57,0x39,0xae,0xfc,0x17, + 0x96,0x59,0x0c,0xcb,0x1f,0x43,0x7d,0x4b,0x73,0x0e,0x5a,0x40,0x5a,0x9d,0x28,0x2f, + 0x09,0xa5,0x54,0xc3,0xaf,0xdc,0x74,0x24,0x19,0x83,0x0e,0x40,0x81,0x31,0x08,0xbe, + 0x2d,0x73,0xb6,0x86,0xf6,0x47,0xa1,0xf4,0x91,0x2c,0x58,0x23,0x58,0x25,0x94,0xa6, + 0xe2,0x5d,0x50,0xd5,0xf2,0x7e,0x41,0x96,0xc2,0x06,0x87,0x86,0x4e,0x9d,0x3e,0xb3, + 0xe5,0x3b,0xe5,0xbd,0x3f,0xfd,0x72,0x58,0xfd,0xa8,0xe6,0xf9,0x8b,0xc6,0x66,0xd6, + 0xf6,0x2e,0x5e,0x1e,0xde,0x01,0xbe,0xfe,0x41,0xde,0x7e,0x41,0xae,0x9e,0x7e,0xb6, + 0xf6,0xce,0xfa,0x06,0xc6,0x27,0xff,0xd4,0x54,0xfb,0xf5,0x7f,0x7b,0xf7,0xfd,0xfc, + 0xdd,0xf7,0x5b,0x37,0x6e,0xfc,0x52,0x56,0x96,0x06,0xf0,0x57,0x54,0x4c,0x6c,0xb9, + 0x90,0x30,0x78,0xf9,0x83,0x97,0x27,0xf2,0x42,0x43,0x39,0x4a,0x2c,0x48,0x06,0xa6, + 0x23,0x61,0x4e,0x45,0xc1,0x5d,0x8b,0x5b,0xbf,0xdf,0x86,0xb2,0x84,0xc2,0xaf,0x46, + 0x95,0x94,0xe3,0xf8,0x4b,0xd1,0xf9,0x73,0xe7,0xb4,0x04,0x6c,0x79,0xd1,0xa2,0xc5, + 0xc5,0x25,0xa5,0x7f,0x0d,0x41,0xf5,0xfe,0xf1,0x67,0x33,0x28,0x5a,0xf0,0x18,0x23, + 0x87,0xb9,0x74,0x5a,0xc9,0xdd,0xf9,0x1f,0xcf,0xf7,0xf6,0xf5,0x66,0xe4,0xe6,0x27, + 0xa7,0x65,0xdf,0xbe,0x57,0x8f,0x26,0x34,0x67,0xdc,0x1d,0xe0,0xef,0x5f,0x43,0x43, + 0xfa,0xfa,0x06,0xfc,0x82,0xb8,0xa8,0x0d,0x1c,0xc8,0xdc,0xd2,0x32,0x83,0x4e,0xd7, + 0x33,0x30,0xb6,0xb0,0xb4,0x09,0xbf,0x1a,0x5d,0x5c,0x52,0x09,0x63,0xad,0xf9,0xd0, + 0xed,0x6e,0x16,0x6b,0xf3,0x57,0x4a,0x3c,0x8d,0x88,0x8a,0x88,0xa6,0x65,0x64,0x3a, + 0x3a,0xb9,0xf8,0xfa,0x05,0x32,0x98,0x05,0x4f,0x9a,0x9a,0x87,0x86,0x87,0x29,0x4e, + 0x19,0x20,0xe6,0xdb,0x72,0x02,0x83,0xff,0xfe,0xf1,0xdf,0x4f,0xe4,0xe5,0x17,0x58, + 0x5a,0xd9,0x6a,0x9f,0xbf,0x08,0x58,0x30,0x0c,0xe7,0xf6,0x0f,0x4e,0xcd,0x60,0xdc, + 0xbc,0x73,0xbf,0xa3,0xab,0x7b,0x64,0x0c,0x4f,0x6a,0x26,0x06,0x57,0x7d,0x03,0x03, + 0xfa,0x06,0x86,0x9f,0xbe,0x2b,0xd9,0x5e,0x41,0x6c,0xe9,0x92,0xa5,0x99,0x74,0x3a, + 0xb8,0x68,0xf0,0x9e,0x19,0x9f,0xa0,0x86,0x48,0x74,0x01,0xc1,0x2e,0x02,0x36,0xae, + 0xa7,0x6f,0x38,0x32,0x3a,0x36,0x3c,0x3c,0x3a,0x3a,0x36,0x3e,0x6b,0xcb,0x7d,0x03, + 0xfd,0xdb,0xb6,0xcd,0x92,0xd6,0xaa,0xac,0xac,0x5c,0x54,0x5c,0x6c,0x69,0x63,0x1f, + 0x7e,0xf5,0x5a,0x59,0x45,0x75,0xdb,0x53,0x0e,0x05,0xfe,0x82,0xb1,0xab,0x85,0x95, + 0xf5,0x1c,0x5d,0xb7,0x9d,0x3b,0x77,0x15,0x14,0x17,0xd9,0x3b,0x3a,0x45,0x46,0xc5, + 0x81,0x11,0xd7,0xd3,0x6e,0xd6,0x8b,0x17,0x7c,0xb3,0x08,0x81,0x1d,0x3b,0x76,0x82, + 0xa7,0x05,0x30,0x8c,0xb7,0xb6,0xb1,0x65,0x73,0xfa,0x59,0xec,0xbe,0xe1,0x91,0x51, + 0x0a,0xd9,0xed,0x57,0x58,0xe8,0x02,0x18,0xeb,0xaa,0x1e,0x14,0xd4,0x15,0x36,0x47, + 0xf6,0xc1,0x87,0x0b,0xc4,0xf6,0x7a,0x40,0x38,0x40,0x62,0xcb,0x18,0x71,0x23,0xd2, + 0x5d,0x91,0xd3,0x15,0x5f,0x30,0xc5,0xbd,0xc7,0x08,0x6e,0x48,0x04,0x16,0xa6,0xdc, + 0x92,0xd5,0xa2,0x88,0xf5,0x44,0x84,0x12,0x11,0x5c,0x4d,0x82,0x36,0xdc,0x23,0x4d, + 0xae,0xa1,0x80,0xef,0x6b,0x4c,0x94,0x3f,0x80,0x65,0x1a,0x70,0xa1,0x2d,0xae,0xf3, + 0x19,0x92,0x71,0x44,0xc3,0xf1,0x04,0x5b,0x8c,0x81,0x62,0x75,0x00,0x01,0x4c,0xcb, + 0x18,0x61,0x71,0xd4,0x46,0x88,0xb3,0xf7,0x10,0x6e,0x61,0xe4,0x73,0x96,0xc1,0x0c, + 0x2f,0x1a,0xc8,0x2d,0x20,0x28,0x8b,0x44,0x38,0x4d,0x7a,0xe4,0x8c,0x9e,0x72,0x57, + 0xe2,0x83,0x01,0xe2,0x94,0x51,0xd5,0x09,0x54,0xa6,0x10,0xed,0x02,0xa3,0xce,0xf0, + 0x88,0x2f,0x0e,0x5e,0x39,0x82,0x48,0xfe,0x35,0xc3,0x89,0xbc,0x9c,0x29,0x87,0x7b, + 0x25,0x51,0x91,0x47,0x7c,0x24,0x40,0x33,0xea,0x06,0x64,0x59,0xc1,0xb8,0x83,0x76, + 0xa9,0x53,0x56,0xbf,0x19,0x40,0xb0,0xec,0x85,0x7a,0x05,0x2d,0x40,0x81,0xcb,0xe5, + 0x4f,0x30,0xa5,0x0f,0x27,0x48,0x1e,0x0c,0x97,0xd8,0xef,0x9b,0x94,0x77,0xf7,0xdd, + 0x03,0xab,0x80,0xc6,0x62,0xb3,0xd4,0x8f,0x68,0x7c,0xaf,0xbc,0x6d,0xbf,0x8a,0xda, + 0xd1,0xe3,0x7f,0x5c,0xd4,0xbf,0x64,0x6d,0xe7,0xe8,0xe6,0xed,0x17,0x10,0x1c,0x1e, + 0x72,0xe5,0x6a,0x70,0x68,0x24,0x80,0x60,0x47,0x37,0x1f,0x13,0x33,0xab,0x0b,0x3a, + 0x7a,0x00,0xa0,0x7f,0xfe,0x45,0x15,0x6c,0xbc,0xe9,0x2b,0xa5,0x75,0x6b,0x15,0x25, + 0x24,0x24,0xc5,0x57,0xae,0x14,0x16,0x11,0x5d,0xb6,0x6c,0xf9,0xd2,0x25,0x50,0x0e, + 0x1a,0x69,0x71,0x00,0xf8,0x40,0xb1,0xa9,0xaf,0x1b,0x88,0xb5,0x59,0xe9,0x9b,0xbc, + 0xc2,0x02,0x07,0x27,0xd7,0xd0,0x2b,0xd7,0x0a,0x4b,0xaa,0x3b,0xba,0xa8,0x32,0x2e, + 0x81,0x5d,0x32,0x36,0x11,0x90,0x5c,0x83,0xbe,0x15,0x16,0x15,0x81,0xe7,0x58,0xc0, + 0xcb,0x52,0x54,0x5c,0x3a,0x5d,0x64,0x0f,0x7a,0x86,0xb3,0x19,0x11,0x51,0xb1,0xa9, + 0x19,0x39,0xf7,0xea,0x1e,0x43,0xda,0x32,0x23,0x37,0xff,0xfb,0xd5,0xb3,0x67,0x2f, + 0xee,0xde,0xbb,0xa7,0xa0,0xb0,0xf6,0x8d,0x1f,0x67,0x1a,0x4d,0xae,0xa8,0xac,0xd4, + 0xc6,0xc1,0xd1,0xd8,0xd4,0xc2,0x27,0x10,0x16,0x95,0x6b,0x68,0x6a,0xc3,0x54,0x0a, + 0x67,0xd2,0xe2,0x18,0x1f,0x3b,0x73,0x56,0x93,0xe7,0x52,0x2c,0x5f,0x26,0x94,0x94, + 0x92,0xea,0xe4,0xea,0xee,0xe1,0xe3,0x97,0x9d,0x93,0xf7,0xb8,0xb1,0x99,0x5a,0x89, + 0xb7,0xf6,0xce,0x9d,0xb7,0xa8,0xa5,0x0c,0xee,0x01,0x4d,0x4d,0x2d,0x40,0xcc,0x4d, + 0xcc,0x4c,0xb5,0xb5,0x75,0x74,0x0d,0x8c,0x2c,0x6d,0x1c,0x02,0x83,0x42,0xb3,0x19, + 0xb9,0xb7,0xef,0xd6,0xb3,0x7a,0x7a,0x46,0x47,0x79,0xe9,0x64,0xdf,0x40,0x1f,0x40, + 0x6d,0x0a,0x45,0x91,0xb7,0x6b,0xe4,0x9b,0x73,0xc6,0x5b,0x74,0xe1,0x67,0x0b,0x53, + 0xd2,0xd2,0xa0,0x04,0xb7,0x60,0xd5,0x9c,0x6f,0xdd,0xb9,0x27,0xbc,0x42,0x58,0x90, + 0x1b,0x1e,0x6c,0x70,0xfa,0xac,0xe6,0x8b,0x57,0x30,0x1c,0x4d,0x90,0xe0,0xcc,0x81, + 0xbf,0x06,0xf7,0xec,0xdd,0x37,0xcb,0xb3,0xb3,0x59,0xe9,0x7a,0x61,0x91,0x95,0xad, + 0x43,0x48,0x68,0x64,0x69,0x59,0x25,0x18,0xe4,0x50,0x04,0x27,0xc0,0x59,0x27,0x67, + 0x97,0xd7,0xba,0x5c,0x68,0x38,0x0d,0xc6,0x93,0xb3,0x0e,0xd2,0x94,0xbe,0xdd,0x52, + 0x5a,0x5e,0xee,0xe0,0xe8,0x1c,0x11,0x19,0x53,0x52,0x79,0xab,0xab,0xbb,0x1b,0xd0, + 0x6d,0x8a,0x11,0xaf,0xa6,0x96,0x36,0x4f,0x9b,0x62,0xa2,0x62,0x95,0x55,0xd5,0xa3, + 0xb0,0x26,0x16,0x96,0xdc,0x37,0xdb,0x25,0xaa,0xbd,0x75,0x5b,0x5c,0x6c,0xae,0x64, + 0x58,0x04,0xb4,0x0f,0xfe,0xf3,0x91,0xe8,0x56,0x7d,0xda,0x25,0x7c,0xea,0x56,0x01, + 0x77,0xa2,0x72,0xeb,0xfb,0x90,0xaa,0x13,0x12,0x11,0x4d,0x72,0x28,0x8a,0x69,0x6a, + 0x0c,0x15,0x1e,0xda,0xc4,0x55,0x8b,0x22,0x97,0x05,0x44,0x13,0xca,0xe8,0x2b,0x6a, + 0x84,0x54,0x7f,0xb0,0x87,0x3b,0xdb,0x3b,0x25,0x86,0x0a,0x05,0x3e,0x21,0x57,0x36, + 0xe1,0x61,0x9e,0xb6,0x2f,0x87,0xbc,0x2f,0x26,0x4a,0xf9,0x94,0x90,0xe1,0x22,0x89, + 0x65,0xf5,0x4c,0x6f,0x8a,0xe0,0xb9,0x28,0x2a,0x8c,0x38,0x5f,0xbc,0x1b,0xdc,0x08, + 0xab,0xc9,0x8a,0x8a,0x53,0x7c,0xe3,0xb8,0x8b,0x00,0x46,0x7f,0x71,0x3f,0xe1,0x71, + 0xc1,0x09,0x9a,0xb1,0x61,0x16,0xb0,0xd9,0x64,0xc4,0x17,0x37,0x27,0x1a,0x45,0x9d, + 0x75,0x63,0x64,0x99,0x85,0x76,0x91,0x35,0xea,0x56,0x00,0xec,0x1b,0xcd,0x02,0xeb, + 0x34,0x40,0x0a,0x7c,0xa6,0x4a,0xea,0x44,0x81,0xb4,0x46,0x9a,0x94,0x5a,0x8c,0xa4, + 0x6a,0x88,0x6f,0xc2,0x8d,0xb9,0x86,0xd1,0x37,0xb6,0xa6,0x96,0x66,0x55,0xd5,0x43, + 0xca,0x3f,0xec,0x3c,0xa8,0xf6,0xeb,0xc9,0x3f,0xcf,0x18,0x18,0x9b,0xda,0x39,0x7a, + 0xf8,0x06,0x86,0x00,0x06,0x1a,0x1e,0x95,0x1c,0x19,0x15,0x13,0x14,0x76,0xc5,0xc3, + 0xc7,0xdf,0xc6,0xd6,0x41,0x57,0xdf,0xe8,0xd8,0x89,0x3f,0x0f,0x1c,0xfc,0x6d,0xfb, + 0xce,0x3d,0x5f,0x7f,0xb3,0x45,0x51,0x71,0x3d,0xe6,0x82,0x86,0xb3,0xc0,0xcb,0xb1, + 0xbf,0x45,0x9f,0x2d,0x26,0xbc,0xd0,0xc0,0x20,0x05,0xc6,0x62,0xa1,0x05,0x0f,0xc4, + 0x52,0x5c,0xb7,0x1e,0x90,0x26,0xf0,0xe4,0x86,0x86,0x47,0x16,0x14,0x97,0x77,0x74, + 0x76,0x61,0xd2,0x13,0x7c,0x3b,0x7f,0xaf,0xee,0x41,0x42,0x52,0x52,0x7c,0x22,0xb4, + 0xb8,0x84,0x24,0xb0,0x3c,0xfd,0x13,0xfd,0x9a,0x94,0x92,0xc2,0x62,0xb3,0x05,0xbf, + 0x2c,0x37,0x6e,0xde,0x5c,0xbd,0x8a,0x37,0x2d,0x11,0x70,0x4c,0x80,0xcb,0xfe,0x81, + 0xa1,0x59,0xd9,0x79,0x75,0x0f,0x1b,0x07,0x87,0xf8,0x56,0xd4,0x05,0x38,0xef,0x1f, + 0x10,0x2c,0xb8,0x37,0x72,0xba,0x2d,0x98,0xb7,0xc0,0xc9,0xc5,0x35,0x2a,0x36,0xce, + 0xd0,0xc4,0xd4,0xdb,0x27,0x20,0x3d,0x2b,0xe7,0x61,0xc3,0x93,0x81,0x81,0xe1,0x19, + 0xb3,0x54,0xc0,0xeb,0x34,0x20,0x20,0xe8,0x93,0xf9,0x53,0x26,0xac,0x01,0x7f,0x87, + 0x22,0x0f,0x1e,0x3e,0x6e,0xde,0x97,0x33,0xe9,0xcc,0x47,0x8f,0x9b,0xa1,0x9e,0x27, + 0x7f,0x28,0xa9,0x7b,0xf8,0xf8,0xed,0x6a,0x29,0x2f,0xfc,0x74,0xa1,0xb1,0x89,0x59, + 0x16,0x83,0x69,0x68,0x64,0xa2,0xa5,0xad,0x03,0xb8,0xbc,0xb5,0x9d,0x6b,0x50,0xd8, + 0x55,0x70,0xf5,0xee,0xd7,0x3f,0x62,0xb1,0x39,0xd3,0xc3,0x89,0x9b,0x9a,0x5b,0x0f, + 0x1f,0x56,0x9f,0xd3,0x58,0x2c,0x70,0x43,0xaa,0x1e,0x3c,0x18,0x7e,0x25,0x22,0xec, + 0x4a,0x44,0xc4,0xb5,0xa8,0x6b,0x51,0x31,0x71,0xf1,0x49,0xb1,0xf1,0x09,0xb1,0xf1, + 0xbc,0x37,0x12,0xb8,0x67,0xda,0x3b,0x5f,0x63,0xe6,0xe8,0xaf,0xa1,0xe1,0x8c,0xac, + 0x2c,0xac,0x91,0x64,0xa2,0x11,0xd4,0x26,0x4f,0xcb,0xf1,0x89,0x89,0xd5,0x35,0x35, + 0xaf,0xd1,0xf2,0xf0,0xd0,0x21,0xb5,0xdf,0xa8,0x2f,0xcb,0x17,0x5f,0x6c,0xc8,0x2b, + 0x28,0xb6,0xc6,0xf0,0xb7,0xa8,0xa4,0xb2,0x1d,0x3c,0x3b,0x94,0xd1,0x62,0x8f,0x1e, + 0x37,0x50,0x77,0x92,0xe7,0x33,0x26,0x2e,0x11,0x74,0x1b,0x9c,0x5a,0x54,0x4c,0x8c, + 0x8a,0xea,0x41,0x8a,0x9e,0xac,0x5f,0xff,0x45,0x49,0x79,0xa5,0xbd,0x93,0xeb,0x95, + 0x88,0x98,0xd2,0x8a,0xea,0xce,0xae,0x59,0xe2,0xc6,0x2d,0x2c,0xad,0x84,0x85,0x84, + 0x85,0x96,0x09,0x2d,0x5f,0x0a,0x0d,0x2c,0xa8,0xa8,0x1c,0x18,0x1e,0x85,0xfa,0xd5, + 0x02,0x95,0xd2,0x7e,0xf9,0xdc,0xc3,0xd3,0x6b,0xfe,0xbc,0x05,0x73,0x77,0xcf,0x08, + 0x62,0xe0,0xbf,0x23,0xbc,0xf1,0x98,0x8c,0x41,0x3b,0x21,0x22,0x21,0x3b,0xa9,0x53, + 0xd1,0x4b,0x8e,0x74,0x22,0x18,0x2e,0x16,0xbc,0x44,0x44,0x67,0x71,0x48,0x9b,0x71, + 0xb8,0x14,0xb5,0x97,0xf8,0x95,0x87,0x0e,0x73,0xb3,0x75,0x7a,0x70,0xa1,0x2d,0xae, + 0xba,0x32,0x62,0x9a,0xe8,0x57,0x8c,0x4b,0x4e,0x1e,0x14,0x65,0x39,0x91,0xa9,0x37, + 0x16,0x8b,0xd5,0x87,0x0a,0x1f,0x20,0xfa,0x89,0xb8,0x27,0x0d,0x5b,0xa6,0x99,0x90, + 0x98,0x26,0xc6,0xe5,0xd1,0x36,0x18,0x4b,0x7d,0x8a,0xf6,0xc5,0x17,0xb8,0xdb,0xa0, + 0x35,0xc4,0x32,0xbe,0x06,0xf3,0x1b,0x13,0xed,0x13,0x5e,0x71,0xb4,0x25,0xf1,0x2b, + 0xb1,0x0d,0x8d,0xfb,0x15,0x73,0x35,0xa3,0xa0,0x2f,0x8e,0x2c,0x51,0x2b,0x0a,0xa7, + 0xcc,0x78,0x4f,0x50,0xa5,0xa4,0xb5,0x26,0x2c,0x39,0xc3,0x0e,0x19,0xfd,0x56,0x48, + 0x81,0xcf,0xdf,0x97,0xd5,0xbc,0x21,0x75,0xaa,0x58,0xee,0xf7,0x2c,0xa9,0x5f,0x63, + 0xa5,0x0e,0x85,0x39,0x84,0x96,0x08,0x38,0x84,0x7e,0xf7,0x76,0xef,0xc1,0xfd,0x7d, + 0xfb,0x7e,0xde,0xbe,0x63,0xb7,0x8a,0x9a,0xc6,0xd9,0x73,0x17,0x4c,0xcd,0x2c,0x9d, + 0x3d,0x2f,0x07,0x85,0x46,0x5c,0x8b,0x4e,0x88,0x4f,0x4c,0x8b,0x8e,0x4d,0x0a,0x89, + 0x48,0xf2,0x0b,0x0c,0xb1,0x73,0xf2,0x34,0x32,0x35,0x3f,0x7d,0x4e,0x5b,0xed,0xb7, + 0x23,0x7b,0xf6,0xa9,0x6c,0xf9,0x6e,0xdb,0xc6,0x8d,0x9b,0xe4,0xe4,0xe4,0x24,0x24, + 0xa4,0xc4,0x57,0xae,0x16,0x16,0x11,0x01,0xf8,0xbb,0x74,0xe9,0xd2,0x45,0x0b,0x17, + 0x01,0xd6,0x80,0xf0,0x17,0xcf,0xe2,0xc4,0xe4,0x28,0x67,0x7c,0x75,0x20,0xbd,0x0e, + 0xf2,0x1a,0x69,0x29,0x19,0xe6,0xf5,0x3c,0x7b,0x47,0x37,0xff,0x90,0xf0,0xeb,0x85, + 0x65,0xcd,0x2d,0x1d,0xa3,0x63,0x54,0xba,0xf4,0x73,0x78,0x59,0xee,0xdf,0x93,0x94, + 0x90,0xe2,0xe9,0xf0,0x81,0x03,0xaa,0xf9,0x85,0x45,0x97,0xfd,0x42,0x32,0x19,0xcc, + 0xba,0x47,0x18,0xfe,0x42,0x38,0x9c,0x61,0x77,0xb0,0x52,0xe3,0xd8,0xd1,0x7f,0x88, + 0x23,0xbb,0x76,0xed,0x2e,0x2c,0x2e,0x36,0xb7,0xb2,0x76,0x73,0xf7,0x4a,0x4d,0xcf, + 0x7e,0x50,0xf7,0xa4,0x7f,0x60,0x80,0xdf,0xb4,0x75,0x6e,0x5e,0x01,0x8f,0xc3,0x1c, + 0xd6,0xb3,0x08,0x0b,0xf7,0xf4,0xb9,0xec,0xee,0xe5,0x9b,0x96,0xc1,0x78,0xd8,0xd0, + 0xd4,0x3f,0x40,0x85,0xbf,0x2d,0x6d,0xed,0x0b,0x3f,0x7b,0xcb,0x5a,0x16,0xa0,0x4b, + 0x7e,0x01,0x01,0x19,0xd9,0x0c,0x2d,0x2d,0x6d,0xc0,0x82,0xf5,0x0d,0x4d,0x9d,0x9c, + 0xdd,0x43,0xc3,0xa3,0xf3,0x0b,0x8b,0x1f,0x3e,0x6a,0xec,0xeb,0x1f,0x00,0xcc,0x68, + 0xca,0x5c,0xf0,0xdf,0xaf,0x1a,0x9b,0x9a,0xbf,0xd8,0xb0,0x69,0xee,0x54,0x14,0xc0, + 0x3d,0x69,0x63,0x6b,0x47,0x67,0x30,0x63,0xe2,0x92,0x8b,0x4b,0xcb,0x9e,0x34,0xc2, + 0x24,0x32,0x01,0x5f,0xf5,0xef,0xcb,0x46,0xc6,0x46,0x8e,0x1d,0xff,0x9d,0xfa,0x76, + 0xa2,0xc9,0xca,0xe7,0x15,0x14,0x5a,0x58,0xd9,0xc2,0x70,0xf7,0xa2,0xb2,0xb6,0x0e, + 0x88,0xbf,0xd4,0xd5,0xa8,0xdf,0xcc,0x00,0x65,0x77,0x73,0xf7,0xa4,0xe8,0x09,0x78, + 0x8a,0xcb,0x2a,0xaa,0x9c,0x5c,0xdc,0x42,0xc2,0x23,0xc0,0x42,0x07,0xc2,0x5f,0xfe, + 0x97,0xb7,0xbe,0xfe,0x51,0x36,0x83,0x41,0xcf,0xce,0xce,0xa4,0x67,0xa7,0x67,0x64, + 0x83,0x85,0xbb,0x77,0x1f,0x08,0xde,0x9f,0xfe,0xc1,0x81,0x5d,0xbb,0x67,0x71,0x0e, + 0xbc,0x1b,0x5b,0x4a,0xdb,0x27,0x63,0x88,0x87,0x40,0x4f,0x82,0x2c,0xc6,0xf5,0xd6, + 0xa2,0x60,0x24,0x2c,0x1d,0x18,0xaa,0x53,0x1a,0xb3,0x71,0x89,0x27,0xf2,0xf4,0x28, + 0xb7,0x3a,0xf0,0xd4,0x68,0xe7,0x29,0xc2,0x17,0x44,0xd1,0x40,0x9c,0x87,0x72,0xdd, + 0xd4,0xdc,0x5f,0x67,0x98,0x78,0xc5,0x8a,0x15,0x62,0x32,0x20,0xc6,0x4f,0x09,0xb0, + 0x46,0x81,0x4c,0xe0,0x13,0xcd,0xb4,0xe2,0xb0,0x88,0x4f,0xbc,0x42,0x62,0x8e,0x60, + 0x51,0x1e,0xd5,0x24,0x32,0x65,0x13,0xf4,0x13,0x6d,0x4c,0xb4,0x80,0x16,0x10,0x4a, + 0x12,0x4d,0x11,0xa8,0x8a,0x3e,0x27,0x27,0x6d,0x49,0x6b,0x78,0x0c,0xb5,0xcc,0xd5, + 0xee,0xe8,0x25,0x0e,0x84,0x0b,0x98,0x60,0x61,0xcf,0xe8,0x58,0xe8,0x40,0xeb,0xcc, + 0xf1,0x91,0x83,0xa2,0x39,0x5b,0xc1,0xb8,0x53,0xd6,0x88,0x25,0x67,0xd4,0x0d,0x07, + 0x3f,0xfa,0xcd,0x34,0x9d,0x07,0xb2,0x17,0xee,0xc9,0x9c,0xae,0x94,0x3f,0xc1,0x90, + 0x3e,0x92,0x22,0xa5,0x16,0xa9,0xef,0xc9,0x9c,0x78,0x4e,0x35,0x85,0xf1,0x1e,0xad, + 0xbc,0xa2,0xea,0xc7,0x5d,0x7b,0x76,0xed,0xde,0xa3,0xae,0x71,0xfc,0x9c,0x96,0x8e, + 0x85,0x8d,0xab,0x87,0x4f,0x50,0xc4,0xb5,0xf8,0x84,0xa4,0x94,0xd4,0x8c,0xcc,0x94, + 0x74,0x7a,0x5c,0x42,0x5a,0xd8,0x95,0x48,0x57,0x4f,0x7f,0x2b,0x1b,0x7b,0xed,0xf3, + 0xba,0xc7,0x8e,0x9f,0xdc,0xaf,0x72,0x68,0xdb,0xf6,0x1d,0x4a,0x5f,0x7f,0xa3,0xa8, + 0xa8,0x28,0x2d,0x2d,0xb3,0xfa,0xf3,0x35,0x80,0x02,0x43,0x39,0xca,0xe5,0x42,0x4b, + 0x16,0xe3,0x10,0x0c,0xd3,0x81,0x31,0xf1,0x04,0xa2,0x34,0x30,0xbf,0xb4,0x7d,0xf2, + 0xfa,0xd5,0xab,0xd7,0x64,0xe7,0x31,0x9d,0x5c,0x3d,0x82,0x42,0xae,0x5e,0x2f,0x28, + 0x69,0x69,0x83,0x29,0x33,0xef,0xe5,0xc5,0x58,0x57,0xd7,0x20,0x2f,0xa7,0xc0,0xd3, + 0x55,0x4d,0x2d,0xad,0x0c,0x3a,0xdd,0xe7,0x72,0x20,0x9d,0x71,0xfd,0xe1,0xa3,0x66, + 0x7e,0xde,0x60,0x60,0x63,0xe3,0x63,0xeb,0x15,0x37,0xfe,0xc3,0xc7,0x59,0x78,0x85, + 0x08,0x83,0x79,0xdd,0xdd,0xcb,0xdb,0xd5,0xc3,0x37,0x29,0x2d,0xe3,0xee,0xfd,0x86, + 0xbe,0xfe,0x21,0x7e,0x12,0x7c,0x0f,0x1b,0x1e,0xf1,0x54,0xa3,0x58,0x30,0x7f,0x81, + 0x9f,0x7f,0x80,0x7f,0x60,0xb0,0x93,0x9b,0x6f,0x6a,0x7a,0xd6,0x83,0xfa,0xc7,0x30, + 0x13,0x93,0x7f,0xed,0x54,0x36,0x87,0xb3,0x42,0x44,0xa0,0x7a,0x52,0xaf,0x65,0x2b, + 0x84,0x84,0x43,0x42,0xc3,0x12,0x92,0x92,0x2f,0xea,0xea,0x69,0x9f,0xbf,0x68,0x70, + 0xc9,0xd4,0xde,0xd1,0x25,0x32,0x2a,0x36,0xb7,0xa0,0xac,0xfe,0x51,0x53,0x5f,0x3f, + 0x0c,0x2a,0xe6,0x81,0x89,0x1b,0xb5,0xb7,0x36,0x7f,0x35,0x4b,0xb8,0xd1,0x1b,0x1b, + 0xb8,0x27,0x0d,0x2f,0x19,0x5d,0x8b,0x8e,0x73,0x74,0x70,0x4b,0x4c,0x4a,0xbb,0x75, + 0x17,0x16,0x83,0x9e,0x78,0xfe,0xaf,0xc6,0xdf,0xb1,0x67,0x63,0x9a,0x9a,0x5a,0xd4, + 0x63,0x12,0x49,0x09,0xc9,0xbc,0xfc,0x7c,0x2b,0x1b,0x27,0x30,0x5a,0x66,0xe6,0x17, + 0x37,0xb7,0x76,0x0e,0x53,0x56,0x2b,0x78,0x63,0x03,0xff,0xab,0xc0,0x40,0xaa,0x7a, + 0x88,0xab,0x56,0xae,0xba,0x71,0xeb,0x16,0xe0,0xbf,0x60,0x18,0x5f,0x58,0x5c,0xd1, + 0xde,0xd9,0x39,0x32,0xf2,0x6c,0xee,0x2e,0x2f,0xc0,0x5f,0x13,0x33,0x0b,0x30,0x5a, + 0x7e,0xef,0x29,0x6c,0x8b,0x25,0x95,0x65,0x75,0x1b,0xf0,0x08,0x2b,0x0c,0xcb,0x28, + 0x10,0x87,0x07,0xa7,0xc8,0xd0,0xc6,0xb3,0x2f,0x4f,0x0b,0xc4,0xaf,0xe4,0x16,0x08, + 0x40,0x24,0x35,0x38,0xf9,0x15,0x41,0x2a,0xce,0x8e,0xd1,0xaf,0xe6,0x7d,0x64,0xbf, + 0x2e,0xc2,0x32,0x1a,0xce,0x3a,0x39,0x88,0xdb,0x12,0x08,0x4b,0x6e,0x50,0x6e,0x2a, + 0x22,0x4f,0x3f,0x3b,0x9e,0x35,0x33,0x62,0x37,0x3a,0x05,0xd4,0x14,0x1a,0x18,0x90, + 0x8f,0x8b,0x3a,0xa6,0x68,0x4e,0x56,0xc5,0xe4,0xe0,0x40,0x8f,0x45,0x41,0xc3,0x65, + 0x33,0xac,0x4b,0xdc,0x88,0xe8,0xf5,0xa6,0x9d,0x00,0x7f,0xe5,0x2e,0xb5,0x29,0x1a, + 0x37,0x02,0x0a,0x4c,0xd3,0xae,0xa5,0x69,0xdd,0xa0,0x9d,0x2a,0x92,0x3b,0x9e,0x2a, + 0xfd,0x5b,0xfc,0x1f,0x36,0xcc,0x21,0xfe,0xd2,0x43,0xef,0xd7,0xe8,0x74,0xc6,0xb6, + 0x1f,0xb6,0xef,0xde,0xf3,0xf3,0x91,0xa3,0xc7,0xcf,0xeb,0xe8,0xd9,0xd9,0xbb,0xfa, + 0xf9,0x07,0xc7,0xc4,0x25,0x24,0xa7,0x65,0xa7,0xd1,0x73,0x33,0xb3,0x99,0xc9,0x69, + 0x59,0xd1,0xb1,0xf1,0x7e,0x01,0xc1,0x8e,0xce,0x1e,0x7a,0xfa,0x46,0x27,0x4e,0x9e, + 0x39,0xf4,0xdf,0xff,0xed,0xdc,0xb5,0xef,0xbb,0xef,0x95,0x37,0x6c,0xd8,0x20,0x2f, + 0x2f,0x2f,0x21,0x29,0x29,0xbe,0x6a,0xa5,0xb0,0xb0,0xd8,0xf2,0xe5,0x30,0x17,0x09, + 0x40,0x30,0x51,0x17,0x78,0xc1,0xbc,0x05,0x28,0x16,0x9a,0x78,0x34,0x90,0x3b,0x9a, + 0xdf,0x0d,0x2c,0x22,0x22,0xca,0xc8,0x65,0xba,0xba,0x7b,0xf9,0x07,0x87,0x33,0xf3, + 0x8a,0x9b,0x5a,0xdb,0x28,0xea,0xfa,0xf1,0x7d,0x3f,0xfc,0xcd,0xf7,0xab,0xe0,0x4d, + 0x35,0x36,0x37,0x6f,0xd8,0xc0,0x0b,0xa0,0xc6,0x66,0x66,0xf1,0x49,0xc9,0x1e,0x5e, + 0x97,0xc1,0x65,0xa9,0x7b,0xd8,0xf8,0xd7,0xd0,0x10,0xbf,0x12,0xf3,0x00,0xcb,0x44, + 0x66,0x13,0x2c,0x9a,0xd5,0x3e,0xfc,0xe0,0xc3,0x90,0xf0,0xf0,0xb0,0x88,0xab,0x6e, + 0x9e,0xbe,0x49,0xa9,0x19,0x0f,0xea,0x1a,0xb0,0x88,0xaf,0x99,0x3b,0xdc,0xf9,0xb4, + 0x5b,0x7e,0xea,0x74,0xf3,0xfc,0x8f,0xe7,0xbb,0x7b,0x7a,0x05,0x87,0x86,0xbb,0xba, + 0x79,0xa6,0xa4,0x65,0x23,0x25,0x40,0x8a,0x50,0x9f,0xfe,0xc1,0xa1,0x55,0xb3,0x89, + 0x3c,0xbc,0x81,0x81,0x7f,0xf7,0x9a,0x35,0x6b,0xd2,0x33,0x33,0xaf,0x46,0x44,0x9e, + 0xbf,0xa0,0xa3,0xad,0x63,0x70,0xc9,0xc4,0xcc,0xc5,0xdd,0x07,0x20,0x60,0x71,0x69, + 0xe5,0x93,0xa6,0x56,0x70,0x5c,0x9e,0x2c,0x33,0x30,0xc6,0xc8,0x61,0x5e,0x97,0x94, + 0x94,0x9e,0x8b,0x37,0x2a,0xb8,0xaa,0xba,0xba,0xba,0xb1,0x09,0x49,0xf6,0x8e,0xae, + 0x09,0x89,0x29,0x50,0x66,0xad,0xb7,0x0f,0x0a,0x44,0xfc,0x8b,0xf1,0x77,0x7c,0xe2, + 0x99,0xbe,0xe1,0x25,0xea,0x69,0x65,0x30,0x76,0xa5,0xe7,0xe6,0xd8,0xda,0x3b,0x5d, + 0xf6,0x0b,0x66,0x5e,0x07,0xf8,0xdb,0x41,0x5d,0xf8,0xfe,0x9f,0x3c,0x4a,0x31,0xb1, + 0x71,0x14,0x3d,0x59,0x26,0xb4,0xac,0xa2,0xaa,0x1a,0xf0,0xdf,0x40,0x8c,0x89,0xb7, + 0xb4,0x75,0x8d,0x8d,0xcf,0x21,0xfe,0xbe,0x82,0xfe,0x81,0xd1,0x92,0xd2,0x32,0x0d, + 0x8d,0xe3,0xef,0x37,0x7e,0xef,0x33,0x71,0x25,0xe9,0x8b,0x4f,0x68,0xa6,0xc4,0xb4, + 0x26,0x0b,0x39,0x54,0xc9,0xf4,0x90,0x0c,0xa9,0x44,0x40,0x2f,0xe1,0x80,0x05,0x6b, + 0x90,0x03,0x96,0xfc,0x2b,0x0d,0x6b,0x0a,0xed,0xcb,0xf3,0x2b,0xfa,0x44,0xbf,0x12, + 0x3e,0x5b,0x2e,0x9e,0x72,0xc8,0x8d,0x23,0x6f,0x2d,0xee,0xb3,0xc5,0x42,0x9b,0xd6, + 0xc2,0xa8,0xe9,0x49,0x1c,0x24,0x6f,0x40,0x84,0x39,0xe1,0x94,0xd6,0xa4,0x77,0x7a, + 0x83,0xe4,0xce,0xa3,0x8e,0x11,0xfd,0x21,0x9f,0xaf,0x1c,0x4c,0xda,0x9d,0xe2,0x43, + 0x26,0x63,0x34,0xd9,0xf9,0xcc,0xf5,0x6c,0x73,0x85,0xa3,0xd1,0x57,0xe3,0x0e,0xec, + 0xc4,0xf1,0xa6,0x68,0x66,0x7d,0xeb,0xcc,0x61,0xaf,0xd6,0x9a,0xf7,0x82,0x21,0x84, + 0xbc,0x59,0xaf,0xa2,0x05,0x5c,0x09,0xeb,0x23,0x1b,0xb3,0xd7,0x9b,0x76,0xc9,0x1b, + 0x36,0x29,0x18,0x36,0xd2,0x74,0xea,0xe4,0xb4,0x6e,0xc8,0x9e,0x2a,0x92,0xff,0x23, + 0x5b,0x46,0x3d,0xe6,0xb0,0x69,0x16,0xbb,0xff,0x5f,0x5a,0x88,0x30,0x3a,0x36,0x0e, + 0x20,0xe9,0x9e,0x7d,0x07,0x8e,0x1e,0x3f,0xa9,0xab,0x67,0xe8,0xe2,0xe6,0x1d,0x14, + 0x7a,0x35,0x3e,0x31,0x35,0x8b,0xc1,0xcc,0xcb,0x2f,0xca,0xbd,0x5e,0x98,0x95,0x9d, + 0x97,0x90,0x94,0x1e,0x76,0xf5,0x9a,0x87,0xcf,0x65,0x13,0x73,0x2b,0x40,0x61,0xd4, + 0x8f,0x1c,0xff,0x69,0xff,0xc1,0x1f,0x76,0xec,0xfa,0x6a,0xb3,0x12,0xd4,0xc2,0x92, + 0x91,0x41,0xb9,0xc0,0x22,0x22,0x50,0x0e,0x0b,0xab,0x0b,0x8c,0x4f,0x04,0xa3,0xa4, + 0x60,0x48,0x81,0xb1,0xbc,0xe0,0x59,0x5f,0xa7,0x4b,0x96,0x2e,0xc9,0x62,0x30,0xdc, + 0x3d,0x7d,0x00,0xdc,0x33,0x73,0x8b,0x1e,0x37,0xb6,0x50,0x70,0x4c,0xbe,0x2f,0x8d, + 0x57,0x5c,0xfb,0xfb,0x15,0x2a,0x3e,0x4b,0x54,0xb1,0x17,0xdc,0x95,0x0d,0x06,0xed, + 0xdf,0x7c,0xcd,0x2b,0x0b,0xe0,0xe8,0xe2,0x1a,0x11,0x15,0xed,0xee,0xe1,0x93,0x96, + 0x09,0xe3,0xaf,0xa0,0xb0,0x3c,0x1f,0x3a,0xd9,0xd8,0xdc,0xb2,0x78,0xd1,0x5b,0xf0, + 0xe5,0x9a,0x9a,0x59,0x00,0xe6,0xeb,0xe9,0xed,0x97,0x96,0x99,0x5d,0xf7,0xb0,0x61, + 0x70,0x90,0x6f,0xa1,0x43,0xc0,0x02,0xbe,0x56,0xfa,0x86,0xbc,0xef,0x47,0x1f,0x7e, + 0x64,0x6e,0x61,0x19,0x19,0x1d,0xeb,0xe2,0xe6,0x9e,0x9c,0x9a,0x8e,0x2b,0x01,0xf2, + 0xaf,0x7a,0x3c,0x34,0x32,0x2c,0x2d,0x25,0x68,0x3d,0x8b,0xd7,0xb5,0x0d,0x1b,0xbf, + 0x64,0x30,0x19,0xfe,0xfe,0x01,0xe7,0x2f,0xe8,0x6a,0x5f,0xb8,0x68,0x66,0x61,0xeb, + 0xe6,0xe1,0x1b,0x13,0x97,0x5c,0x51,0x79,0xa3,0xb1,0xb9,0x63,0x68,0x78,0x78,0xe2, + 0xf9,0x14,0x69,0xac,0xe7,0x2f,0x9f,0xc7,0x27,0x26,0x8b,0x89,0x89,0xbf,0xf5,0x9e, + 0x80,0xfb,0xf0,0xcc,0xd9,0xb3,0xc9,0x69,0xa9,0xb6,0x8e,0x6e,0xb1,0xf1,0x29,0x50, + 0x58,0x83,0xc3,0x41,0x89,0x5d,0x2f,0x61,0xb1,0x8f,0x97,0xe4,0x3b,0x87,0x2c,0xdc, + 0xf4,0xba,0xb7,0x10,0xb1,0x31,0x6a,0x84,0xbc,0x3b,0x58,0x43,0x21,0x09,0x35,0xdd, + 0xc0,0xf8,0xc4,0xcc,0xd2,0x92,0x5a,0xdc,0x43,0x4c,0x44,0x2c,0x3d,0x33,0xcb,0x01, + 0x0b,0x77,0x67,0xe6,0x15,0x82,0x3b,0x70,0x68,0x78,0x54,0x90,0xe0,0x25,0x68,0x7f, + 0x73,0x4f,0x19,0x15,0x6b,0xe6,0xf3,0xe0,0x10,0x9f,0x19,0x0c,0x3a,0x45,0x4f,0xc0, + 0x9d,0x5f,0x54,0x5a,0xe6,0xea,0xe1,0x1d,0x18,0x1c,0xc6,0x28,0x28,0x7b,0xdc,0xdc, + 0x3e,0x3a,0xf6,0xda,0x23,0x81,0xc9,0x6e,0x10,0xbd,0x42,0xeb,0xf9,0x9f,0x11,0xb8, + 0x81,0x5d,0x5d,0xdd,0xc8,0x65,0x31,0xdf,0xb1,0x7d,0x2a,0xfa,0x85,0xb4,0x4e,0xbd, + 0x82,0x19,0xcc,0xb2,0x21,0x26,0x34,0x91,0xdf,0x95,0xc2,0x90,0xee,0x13,0xd9,0x13, + 0x8b,0xf6,0x15,0xe4,0x2b,0x4f,0x3b,0x3c,0x9f,0xb2,0xfc,0x43,0x9b,0x66,0xdc,0x1d, + 0x83,0x63,0x36,0x79,0x47,0xfc,0x14,0x4c,0xba,0x79,0x8e,0x32,0xfd,0x2b,0xcf,0xfa, + 0x29,0x46,0x88,0x45,0xff,0x9f,0xb9,0xeb,0x8e,0x8a,0xea,0xd8,0xff,0xff,0xc4,0xbc, + 0xf7,0xce,0xcf,0x34,0x35,0x46,0x23,0x79,0xb1,0x25,0x20,0x6d,0x45,0xd0,0x24,0x26, + 0xcf,0x18,0x93,0x98,0x68,0x62,0x34,0x9a,0x44,0x93,0x97,0x97,0x58,0xd2,0x5e,0x0c, + 0x28,0xbd,0x6c,0x01,0xa4,0x77,0x56,0xfa,0xc2,0xd2,0x11,0x29,0x02,0x22,0xd2,0x61, + 0xc1,0x65,0x97,0x2e,0x20,0x45,0x10,0xa5,0xee,0x2e,0x2c,0x4b,0x57,0x9a,0x9a,0x73, + 0x7e,0xdf,0x99,0xb9,0x7b,0x25,0xab,0xbb,0x26,0xb1,0xe4,0x9d,0xf3,0x3d,0xf7,0xdc, + 0x32,0x77,0x66,0xee,0xdc,0xef,0xcc,0x67,0x3e,0x33,0xdf,0xf9,0xce,0x9d,0xed,0x21, + 0xe6,0x6d,0x18,0xa1,0x7c,0x3a,0x3f,0x93,0xda,0xf4,0xd6,0x8d,0xe8,0x3e,0x12,0x1d, + 0xea,0x04,0xa1,0xad,0x1e,0xeb,0xce,0x77,0x91,0xa7,0xfa,0x4c,0x62,0xdf,0xd5,0xaf, + 0x67,0xdb,0x03,0xf8,0xab,0x6b,0xd9,0xa1,0x67,0x56,0xaf,0xfb,0xd3,0x05,0xdd,0x23, + 0x05,0xaf,0xfc,0x3b,0x6d,0x87,0x65,0x56,0x8f,0x74,0xf8,0x8f,0x6a,0xe0,0xe3,0x91, + 0xa8,0xe8,0xd8,0xb7,0xb6,0xbc,0xb3,0xe3,0xa3,0x4f,0xbe,0x3d,0xf8,0xbd,0x95,0xb5, + 0x9d,0xa7,0x4f,0x60,0x54,0x4c,0x62,0x6a,0xc6,0xf9,0xfc,0xc2,0x92,0xe2,0x52,0x91, + 0xa0,0x5c,0x58,0x50,0x24,0xc8,0x3a,0x97,0x97,0x90,0x94,0x1a,0x14,0xc6,0x3b,0xe1, + 0xea,0x65,0x6e,0x69,0x77,0xe4,0xbb,0x9f,0x3e,0xdd,0xb7,0xff,0xfd,0x0f,0x3e,0x7a, + 0x63,0xf3,0x9b,0xc6,0xc6,0x26,0x7a,0x7a,0x06,0x40,0x55,0x5e,0x5e,0xb9,0x72,0x85, + 0x16,0xb5,0x29,0xd2,0xe2,0x45,0x4b,0x9e,0x79,0x8a,0x5a,0x8e,0x44,0xfc,0x62,0xa1, + 0x7d,0x09,0x9f,0xa4,0x56,0x24,0x69,0x40,0x61,0x78,0x25,0x25,0x3d,0x2d,0x30,0x38, + 0x28,0x30,0x38,0x02,0xf0,0xbf,0xfd,0x0a,0xda,0x17,0x46,0xc3,0xa6,0x27,0x44,0x00, + 0x04,0xa1,0xb9,0x9e,0x9e,0x9d,0xbd,0x31,0x3d,0x35,0x35,0x3d,0x3d,0x3d,0x03,0x32, + 0x03,0xc4,0x19,0x4e,0x66,0x66,0xc9,0xc9,0xcc,0xd4,0xcc,0x34,0x3c,0x25,0x77,0x66, + 0xd5,0xfb,0x05,0xa2,0x45,0x32,0x20,0xdd,0xf6,0xae,0xea,0x8a,0x0f,0xff,0x40,0x6e, + 0x4c,0x6c,0xbc,0xa7,0x6f,0x40,0x7a,0xe6,0xb9,0x86,0xa6,0xe6,0x91,0xd1,0x51,0x75, + 0x2b,0x23,0x5a,0x2f,0x77,0x3c,0x88,0xf1,0x15,0x2d,0x07,0x0f,0x1f,0x86,0x3f,0xc1, + 0x3d,0x19,0x9a,0x9d,0x83,0x4a,0x63,0x6c,0x62,0x42,0xdd,0xfc,0x2f,0x3c,0xda,0xb2, + 0x65,0xab,0x0a,0xd0,0x58,0x58,0x5a,0x25,0xa7,0xa4,0x7a,0x7a,0xf9,0x9c,0x4e,0xcd, + 0xba,0xd8,0xd8,0x2a,0x1f,0x52,0x68,0x18,0x7f,0x86,0x02,0x54,0xe7,0x09,0xf0,0xa1, + 0xa0,0xde,0x96,0x2d,0x6f,0x17,0x95,0x94,0xf8,0xfa,0x05,0x98,0x9a,0x59,0x1c,0x33, + 0xb7,0x06,0x08,0xf6,0xe5,0x86,0xa7,0xa4,0x67,0x8a,0x2a,0x6b,0xba,0x7b,0x7b,0xc7, + 0x27,0xae,0x53,0x83,0x09,0xca,0xd6,0x75,0xe6,0xe6,0x6c,0x70,0x48,0xd8,0xa3,0xd8, + 0xce,0xe6,0xc0,0x81,0x2f,0x33,0xb2,0xce,0x3a,0xbb,0x78,0xc6,0x25,0x9c,0x2e,0x17, + 0x56,0xf6,0xf4,0x49,0x46,0x47,0xc7,0xf0,0xc2,0xb4,0x59,0x40,0x8a,0x69,0xac,0x33, + 0xa0,0x27,0xa0,0x33,0x53,0x48,0x73,0x40,0x69,0x66,0x40,0x09,0xef,0xbb,0x4a,0x88, + 0x06,0x0e,0x08,0x39,0x3b,0x37,0x0b,0xe5,0x09,0xda,0x88,0xb4,0x6e,0x7a,0x0e,0x62, + 0xa3,0x74,0x92,0x52,0x48,0xa4,0xa5,0x28,0xfe,0xe9,0x29,0xd4,0xf1,0xd0,0xb8,0x14, + 0xfd,0x36,0x1e,0x10,0xf0,0xf2,0xf6,0xd5,0x6c,0x19,0xbe,0x74,0xe9,0x0b,0xc8,0xdc, + 0xdd,0xcb,0x87,0x1b,0x14,0x9e,0x79,0xbe,0xe8,0xca,0xd5,0xfb,0x98,0xbb,0xdf,0x56, + 0xc2,0x19,0xa8,0x04,0xaa,0x20,0xa8,0x6e,0xa0,0x1a,0x82,0x6a,0x0a,0x14,0xc2,0xcc, + 0xcc,0x8d,0xa9,0x69,0xba,0x34,0xc8,0x11,0x04,0x4a,0x03,0x3a,0x03,0xc5,0xa5,0x02, + 0x4d,0x30,0xb4,0xf0,0xa9,0x62,0x41,0x89,0x8f,0x7f,0x60,0x48,0x18,0xbf,0xa8,0x44, + 0xd0,0x71,0xb5,0x9b,0x18,0x53,0xdd,0x2f,0x27,0xb7,0xe6,0x6e,0x42,0x41,0xcd,0x92, + 0xf2,0x99,0x42,0x19,0x98,0x82,0xd3,0x69,0x9c,0x1f,0x54,0xaf,0xa1,0x0c,0x71,0x31, + 0x22,0x1d,0x56,0x03,0xc1,0x10,0x2c,0x35,0x2d,0x7d,0xd5,0xaa,0x35,0x7f,0xc9,0x58, + 0x34,0xe0,0xaf,0xae,0xf9,0x65,0x6d,0xe2,0xc9,0x59,0x49,0x4b,0xe7,0x13,0x3d,0xfa, + 0xa8,0x9c,0x69,0x55,0xa8,0xd8,0x29,0xd1,0x4c,0x50,0x85,0x96,0xce,0xe7,0xce,0x77, + 0x8f,0x4e,0xab,0x30,0x53,0x6d,0xa5,0xb9,0x14,0x0d,0xa0,0xf3,0x58,0x2d,0x35,0xd4, + 0x8c,0x3c,0x56,0xd9,0x93,0x7d,0x06,0xd1,0x1e,0x82,0xda,0xd8,0x75,0xd5,0x1d,0xd3, + 0x2c,0x07,0xca,0x19,0x35,0x8e,0x4d,0x41,0x16,0x52,0xad,0x23,0x7b,0x17,0x2a,0xed, + 0xa0,0x88,0x1f,0xad,0x57,0xe9,0x0d,0x07,0x89,0x7f,0x48,0x07,0xe4,0x80,0x9a,0x5e, + 0xe8,0x44,0x76,0x4e,0x54,0x82,0xec,0xfc,0x17,0xb1,0x45,0x34,0xd9,0x67,0xc1,0x4e, + 0x46,0x26,0xaf,0x11,0xc3,0x45,0x8b,0xb3,0x10,0xcf,0x65,0xb0,0x65,0xc4,0xe1,0x06, + 0x83,0x33,0xa8,0xc7,0x42,0x88,0xac,0xcf,0x06,0x92,0x2b,0xd7,0x67,0x2b,0x0c,0xa1, + 0xf4,0x00,0x70,0x59,0x0a,0x74,0x07,0xe8,0x30,0x1b,0xc1,0xb1,0x21,0x1b,0x95,0x95, + 0x9e,0x9d,0x44,0xd7,0x5e,0x6a,0x68,0xdb,0xa9,0x63,0x71,0x45,0xff,0x58,0x83,0xee, + 0x51,0xb1,0xde,0x0f,0x45,0x8c,0x83,0x99,0xdb,0xcd,0xb3,0xdb,0x7a,0x14,0x8f,0x01, + 0x4c,0xff,0x84,0x24,0x25,0x9f,0x7e,0x7b,0xeb,0xbb,0x3b,0x77,0xed,0x39,0x7c,0xf8, + 0x07,0x6b,0x5b,0xa6,0x9f,0x3f,0x97,0x1f,0x97,0x9c,0x79,0xf6,0x7c,0x51,0x49,0x79, + 0x79,0x45,0x75,0x85,0x48,0x2c,0xb8,0x50,0x95,0x57,0x50,0x92,0x9a,0x9e,0x15,0xc5, + 0x4f,0xf0,0xf1,0x3d,0x69,0xe7,0xc0,0xf9,0xef,0xcf,0xc7,0x0e,0x7c,0x85,0x28,0xf0, + 0x96,0xad,0xef,0xe0,0x1d,0x09,0xd7,0xeb,0xe8,0xe8,0xac,0x59,0xb3,0x56,0xeb,0xe5, + 0x7f,0x22,0x8f,0x58,0x04,0x82,0x17,0xe3,0xe5,0x48,0x4f,0x3d,0x45,0x06,0xa2,0x89, + 0x53,0x4a,0x72,0xd4,0xb0,0x62,0x08,0x02,0x27,0xa7,0x24,0x03,0xf9,0xe5,0x06,0x85, + 0x9c,0x3b,0x5f,0x70,0xb9,0xe3,0x2a,0x46,0x1c,0x4d,0xad,0x07,0x34,0x77,0x50,0x61, + 0xc7,0xc6,0xc7,0x07,0xe5,0x23,0x12,0xe9,0x40,0x9f,0x44,0xde,0xdb,0x27,0xe9,0xed, + 0x93,0xf5,0x4b,0x64,0x7d,0xfd,0x70,0x1c,0xe8,0xed,0xeb,0xef,0xeb,0x87,0xa3,0x14, + 0x2e,0x25,0x52,0xb9,0x6c,0x60,0x10,0x78,0x2b,0xd4,0x62,0xcd,0x0d,0xc2,0xe0,0x90, + 0x7c,0xe7,0x8e,0x5d,0x2a,0xd9,0x0b,0xe0,0x72,0xf9,0x31,0x31,0xae,0x9e,0xde,0xa7, + 0x52,0x32,0x6a,0xeb,0x9b,0x06,0xe5,0x43,0xea,0xf0,0xf7,0x5a,0x77,0xf7,0x43,0xe1, + 0xbf,0xfb,0xf7,0x1f,0x28,0x28,0x2a,0x0d,0x8d,0x88,0x2c,0x2c,0xa9,0xc0,0xb3,0xe1, + 0x6a,0xf6,0xd2,0xfd,0x15,0xed,0xde,0xbb,0xed,0xdd,0xf7,0x54,0x20,0xef,0xe8,0x2f, + 0xa6,0x19,0x99,0x19,0xee,0x9e,0x40,0xf4,0x32,0x6a,0x1b,0x9a,0x14,0xc3,0xc8,0xde, + 0x49,0x03,0x70,0xbc,0xf1,0xc6,0x5b,0x8f,0xae,0x75,0x82,0xbf,0xff,0xd9,0xe7,0x5f, + 0x08,0x84,0xe5,0xce,0xae,0xee,0x47,0xd1,0x0e,0x0d,0x36,0x1c,0x27,0xd7,0xe0,0x90, + 0xa8,0xf4,0x8c,0x9c,0xba,0x86,0x86,0x7e,0xa9,0xec,0x6e,0x93,0xd7,0xf1,0x89,0x49, + 0x37,0x57,0x0f,0xcd,0x0e,0xff,0xff,0x84,0xec,0xd9,0xbb,0x37,0xfb,0xfc,0x79,0x47, + 0x67,0x97,0xb0,0xc8,0xe8,0xdc,0xfc,0x92,0xc6,0x4b,0x6d,0xd7,0xba,0xfa,0x40,0x49, + 0x7a,0x7a,0xfb,0xb1,0xce,0x80,0xe6,0x80,0xb6,0x48,0x7b,0x7a,0xfb,0xfa,0x24,0x03, + 0x7d,0x52,0xd9,0xa0,0x5c,0x31,0x82,0x00,0x5a,0xad,0x0b,0xc4,0xf9,0x02,0x38,0x31, + 0x31,0x39,0x25,0x1f,0x1a,0x91,0x0d,0x0c,0x41,0x9c,0x10,0x61,0x2f,0x3a,0xa2,0x08, + 0x89,0x4e,0xa2,0x3b,0x7d,0x24,0x21,0xa9,0x74,0x00,0x02,0x8e,0x01,0xfd,0xbf,0x79, + 0xfb,0xde,0x86,0x7c,0xca,0x5f,0x73,0x2b,0x34,0x2c,0xfc,0xff,0x34,0x9a,0xf8,0x2e, + 0x7a,0x6e,0x71,0x4a,0x5a,0x9a,0x97,0x8f,0x2f,0xae,0x3b,0xc8,0xdc,0x7d,0x72,0xf2, + 0x86,0x66,0xc7,0x17,0x00,0x64,0x00,0xb4,0x63,0xe3,0x93,0xf0,0x81,0x12,0xe9,0x10, + 0x54,0x1c,0xc8,0x21,0xd4,0x14,0x54,0x6b,0x70,0x95,0xc1,0xe7,0x54,0x9e,0xe9,0x4f, + 0x80,0xef,0x12,0x8a,0x44,0x1a,0x72,0xf2,0x8f,0xbf,0xff,0x03,0x3a,0x5a,0x01,0xdc, + 0x20,0x6e,0x30,0x2f,0xbf,0x10,0x8d,0x62,0x8d,0x4d,0x68,0xf2,0xde,0x7c,0x1b,0xfb, + 0xb0,0x02,0xe8,0x84,0x0e,0xed,0x80,0x7c,0xa4,0xaf,0x5f,0xa2,0xac,0xbc,0x32,0x5c, + 0x73,0xa9,0x5c,0x49,0x65,0x03,0xf0,0x2b,0xa0,0xd2,0x69,0xae,0xbf,0xd0,0xf3,0x89, + 0x8d,0x4b,0x58,0x72,0x97,0x3b,0x9a,0xc7,0x20,0x80,0xbf,0xaf,0x9a,0xb5,0xe8,0x52, + 0x83,0xa8,0x77,0xc6,0x63,0xd5,0xc9,0x7c,0x4b,0x27,0x25,0xbd,0x1d,0x54,0x09,0x43, + 0x4f,0xcb,0xaa,0xc8,0x6f,0xdf,0x92,0xd3,0x80,0x3b,0x7f,0xda,0x57,0x5b,0x69,0xf8, + 0x44,0x27,0x44,0x6f,0x6e,0x48,0xb0,0x92,0xc4,0x4c,0x25,0x4a,0xdc,0x80,0x28,0xbd, + 0x82,0x90,0xf9,0x62,0xcc,0x40,0xa9,0x35,0xb9,0x78,0x36,0x56,0x41,0x8c,0x96,0xb5, + 0x95,0xdb,0x23,0xd2,0x89,0xd2,0x27,0x64,0xb4,0x59,0x47,0x69,0x38,0xad,0x6f,0xdf, + 0x4f,0xf9,0x0c,0xc1,0x83,0xde,0xf4,0x8c,0xed,0x7c,0xbb,0x2f,0xfa,0x12,0x9e,0x22, + 0x8b,0x71,0x16,0xd5,0x69,0x61,0xb0,0x31,0x2f,0x66,0x61,0x47,0x1c,0x78,0xb6,0x57, + 0x1b,0xcf,0xfc,0xea,0x61,0xe4,0x25,0x4f,0x19,0x1c,0x85,0x1e,0x0b,0x47,0xcb,0x1c, + 0x36,0x72,0xe8,0x61,0x38,0x48,0x00,0x7f,0x0d,0x6d,0x3a,0x0c,0x2c,0x5a,0xf4,0x8e, + 0x8a,0x8d,0x7e,0x2e,0xd4,0x3f,0x92,0xfb,0x89,0x5d,0x6e,0xa7,0x74,0xfc,0x2f,0x87, + 0xda,0x7b,0x4a,0x51,0x71,0xf1,0x7b,0xef,0x7f,0xb0,0x6b,0xf7,0xbe,0xc3,0x47,0x7e, + 0xb4,0xb1,0x63,0x7a,0x73,0xc3,0xe3,0x12,0x53,0xb2,0x73,0xf2,0x4b,0xca,0x2a,0x2b, + 0xaa,0xeb,0x6a,0x6a,0x2f,0x8a,0xc4,0x55,0x82,0x72,0x71,0x76,0x4e,0x5e,0x42,0x62, + 0xea,0xc9,0xe0,0x70,0x77,0x0f,0x5f,0x73,0x2b,0xdb,0x43,0x87,0x7f,0xdc,0xfb,0xd9, + 0x57,0xef,0x6d,0xff,0xf8,0xcd,0xb7,0xde,0x36,0x31,0xd9,0x64,0x60,0x60,0xb0,0x76, + 0xed,0x2b,0xd8,0x16,0xfa,0x9f,0xcb,0x5f,0xd4,0x7a,0x7e,0xe9,0x8b,0x4b,0x97,0x2e, + 0x5d,0xf4,0x2c,0x82,0x60,0xbc,0x28,0xf8,0x69,0x6a,0x20,0x7a,0xc1,0x93,0xd4,0xb6, + 0x35,0x4f,0xaa,0x2e,0x4a,0x22,0x6d,0x2c,0x3c,0x8d,0x89,0x8b,0xe7,0x45,0xf2,0x03, + 0x82,0x22,0xb2,0x73,0x10,0xfe,0xe2,0x39,0x56,0xf5,0xfc,0x17,0xef,0x5a,0x2b,0x57, + 0x8c,0x76,0x74,0x5e,0x03,0x40,0x14,0x8a,0x6a,0x4a,0x4a,0xcb,0x05,0x65,0xe2,0xd2, + 0x32,0x61,0xa9,0x40,0x58,0x5c,0x2a,0x2c,0x11,0x08,0xe1,0xbc,0x18,0x1f,0xcb,0x2e, + 0x08,0x05,0x17,0x44,0x10,0xac,0xad,0xfd,0x1a,0xf1,0xe5,0xab,0x01,0xd9,0x87,0x47, + 0x47,0x3f,0xff,0x62,0xbf,0x4a,0xfd,0x82,0xc6,0x2d,0x32,0x2a,0xe6,0x84,0xab,0x57, + 0x3c,0xf0,0x26,0xb4,0x21,0xbb,0x7c,0x4a,0xcd,0x12,0x0f,0xb9,0x62,0x78,0xc5,0x8b, + 0x0f,0x61,0xec,0xf4,0xc0,0x97,0x5f,0x15,0x0b,0xca,0x80,0xa6,0x09,0x45,0xd5,0xd0, + 0x0a,0xa9,0xdd,0x33,0xe2,0x57,0x80,0xaa,0xeb,0x5b,0xdf,0xd9,0x36,0xff,0xdd,0x05, + 0x4f,0x2c,0xf8,0xf6,0xe0,0x21,0xf8,0x95,0xae,0x1e,0xbe,0x49,0x29,0xe9,0x35,0x75, + 0x97,0x06,0x06,0xe5,0x1a,0xf8,0x2f,0xc8,0xf6,0xed,0x1f,0x3e,0xd2,0x06,0x0a,0x7e, + 0xfd,0x37,0xdf,0x7c,0x5b,0x21,0x16,0x3b,0xb0,0x1d,0x01,0x81,0x8f,0x5b,0xdb,0x3a, + 0x9e,0x70,0x09,0x0a,0x8b,0xcc,0xc8,0xce,0xab,0xa9,0x6b,0xea,0x97,0x0e,0x5e,0x9f, + 0x9a,0x56,0xf1,0x9a,0x38,0x3d,0x3b,0x67,0x76,0xcc,0xfc,0x99,0xfb,0xed,0x7e,0xfb, + 0x87,0xe4,0xc3,0x1d,0x1f,0xe5,0xe4,0x15,0x30,0xd9,0xce,0x5e,0xfe,0x21,0xb1,0x09, + 0x49,0xd9,0xe7,0x0a,0x0a,0x8a,0x04,0x45,0x02,0x61,0x59,0xb9,0xa8,0xa4,0xb4,0xa2, + 0x14,0x6b,0x8b,0xa0,0x4c,0x58,0x54,0x2a,0x14,0x94,0x57,0x08,0x2b,0x6a,0x6a,0xeb, + 0x1b,0x41,0x67,0xe0,0x9f,0xa2,0xd9,0x10,0x8d,0xc3,0xb9,0x80,0x23,0x00,0x67,0xbd, + 0xfd,0x92,0xfa,0xc6,0x56,0x71,0x55,0x5d,0xc9,0x05,0x51,0x11,0xa8,0x62,0x39,0xd2, + 0x43,0xa4,0x8a,0x44,0x1b,0x4b,0xe1,0x28,0x16,0x20,0x85,0xac,0x14,0x57,0xd5,0x37, + 0x35,0x5f,0xee,0x96,0x0c,0x8e,0xdf,0xa7,0x9f,0x79,0x2b,0x3a,0x26,0x6e,0xe1,0xbd, + 0x26,0x37,0xc9,0xb0,0xd2,0x13,0x78,0xb5,0x32,0x3f,0x36,0x86,0x7b,0x32,0xdc,0x17, + 0x2f,0x37,0x6b,0x6b,0xbf,0x0a,0x38,0xa5,0xb9,0xee,0xdf,0xb8,0x31,0x0b,0x3d,0x8b, + 0xce,0x6b,0xbd,0x75,0xf5,0x97,0x84,0x15,0x55,0x90,0xab,0x62,0x65,0xc5,0x41,0x35, + 0xa8,0x8c,0xce,0x2d,0x16,0x81,0xb8,0xa8,0x04,0xbe,0x42,0x54,0x55,0x53,0x27,0xaa, + 0xaa,0xbd,0xa7,0x77,0x56,0x22,0x80,0xbf,0x99,0xd9,0xd9,0xd0,0x56,0x70,0x83,0x42, + 0x73,0xf3,0x4b,0x5b,0xdb,0xaf,0xdc,0x40,0x0e,0xac,0xd4,0xe2,0x2f,0x7c,0x38,0x54, + 0x46,0xe8,0x88,0x40,0x9f,0xa1,0xb6,0xbe,0x41,0x28,0xac,0x21,0x7f,0x81,0x24,0x0d, + 0x89,0x16,0xe3,0xa2,0x83,0x56,0xe8,0x82,0xa8,0xaa,0xba,0xae,0xa1,0xa5,0xad,0x5d, + 0x3a,0x20,0x1b,0x1d,0x9f,0x54,0xe7,0xd6,0x72,0xee,0xd6,0x4d,0x6f,0x1f,0xdf,0xc7, + 0x39,0x17,0x4c,0x9a,0xaf,0x67,0x57,0x6e,0xd6,0xb6,0xe8,0x24,0x28,0x43,0x4f,0xc8, + 0xce,0x67,0xbe,0x0c,0x36,0x3e,0x32,0x11,0x3a,0xd3,0x00,0xb4,0x0e,0x11,0x3d,0x85, + 0x01,0x53,0x42,0x66,0x8a,0x29,0xac,0xb9,0x0b,0x52,0xe1,0x5d,0xfa,0x29,0x8d,0xdd, + 0x06,0xac,0x41,0x32,0x60,0x3b,0xdf,0xc2,0x8a,0xb6,0x25,0x5e,0xa7,0x5c,0x38,0x4c, + 0x99,0x4e,0xcd,0x4b,0x88,0xc0,0x19,0x4d,0xa5,0x19,0xd8,0x22,0x8b,0x98,0x36,0x21, + 0x6a,0x79,0xc7,0xa6,0x4b,0xae,0xcb,0x44,0x33,0xad,0x24,0x12,0x00,0x3e,0x1d,0x26, + 0x61,0xdc,0xf2,0x75,0xcc,0x21,0xb8,0x54,0xe9,0x33,0xd0,0x66,0xd5,0x10,0x33,0x70, + 0x52,0x1d,0x5c,0x14,0x10,0x21,0xba,0x64,0x21,0x37,0xd7,0xf0,0xc8,0x90,0x4d,0x8d, + 0x72,0xc3,0x7d,0x06,0x1b,0x65,0xd2,0x80,0x35,0xa4,0x8b,0x27,0x76,0x21,0x66,0xb8, + 0xa9,0x07,0x09,0xb1,0xe0,0x29,0xf9,0x3a,0x3c,0x95,0x8c,0x49,0x2e,0x46,0x5b,0x24, + 0x10,0x18,0x22,0x81,0xdc,0x9a,0x70,0x14,0xfa,0xac,0xe1,0xf5,0x9c,0xe1,0xf5,0x6c, + 0x84,0xdd,0x46,0xcc,0x01,0x06,0x53,0x66,0x60,0xd7,0xcd,0xb0,0xbb,0xba,0xde,0xb2, + 0x71,0xbd,0x45,0xbd,0xe1,0x2f,0x15,0xeb,0x7f,0xc8,0x39,0xe0,0x52,0x3c,0x34,0xfe, + 0x48,0x6c,0x11,0x1f,0x5c,0x2a,0xab,0xab,0x77,0xec,0xfc,0xf8,0xe3,0x5d,0x7b,0x8e, + 0x1c,0xf9,0xd1,0xd6,0x9e,0xe3,0xcf,0x0d,0x89,0x4f,0x4a,0x39,0x97,0x9b,0x5f,0x56, + 0x51,0x59,0x55,0x5b,0x5f,0x77,0xb1,0xb9,0xae,0xee,0xa2,0xa8,0xb2,0x1a,0x1a,0xa8, + 0xb4,0x33,0x59,0xbc,0xa8,0x18,0x3f,0x9f,0x93,0x0e,0x4c,0xce,0xd1,0x5f,0x8e,0x7f, + 0xfd,0x9f,0x83,0xbb,0x76,0x7f,0xba,0xed,0xdd,0xf7,0x81,0x02,0x1b,0x1b,0x9b,0x10, + 0x08,0x5e,0xb9,0x7a,0x95,0xd6,0xcb,0x2f,0xbd,0xb0,0x4c,0xeb,0x85,0x17,0x90,0x5f, + 0xca,0x45,0x8b,0x16,0x01,0x0d,0x7c,0x7a,0xe1,0xd3,0x4f,0x2f,0x7c,0x96,0xb0,0x60, + 0x6a,0x69,0xd2,0x93,0x94,0x83,0x4a,0xda,0x1c,0x0b,0x0d,0x4d,0x3f,0xb1,0x00,0xf0, + 0x37,0x24,0x3c,0x22,0x3a,0x36,0x2e,0x90,0x1b,0x92,0x71,0xf6,0x7c,0x6b,0xdb,0x95, + 0xe1,0x51,0x4d,0xf8,0x0b,0x94,0x61,0x62,0xe2,0xfa,0xb5,0xee,0x1e,0x71,0x55,0x4d, + 0xe6,0xd9,0xdc,0xf8,0xc4,0xd3,0x51,0x31,0x89,0x3c,0xb4,0xb4,0x33,0x21,0x32,0x3a, + 0x81,0xc7,0x8f,0x07,0x89,0x8c,0x8a,0x8f,0xe4,0x23,0xe1,0xc7,0x24,0xc5,0xc5,0x9f, + 0x06,0x6a,0x7f,0xa1,0xa2,0xb2,0xf3,0x5a,0x37,0x72,0xe7,0xab,0x3e,0xe6,0x89,0xeb, + 0x93,0xdf,0x1e,0x52,0x75,0xcb,0xc3,0x76,0x72,0x8a,0x49,0x48,0x02,0xd6,0xc6,0x8b, + 0x8c,0x85,0xc6,0x19,0xef,0x68,0x70,0xef,0xdf,0x3a,0x35,0x33,0xbd,0xe9,0x7e,0x0e, + 0x03,0x7f,0x8f,0x7c,0xf7,0xfd,0x0f,0x17,0x84,0x15,0x19,0x59,0x39,0xf5,0x0d,0x4d, + 0xd0,0xfe,0xab,0x1b,0x8a,0xbf,0x79,0x0b,0xb9,0x68,0x78,0xe3,0x8d,0xcd,0x2a,0xaf, + 0xef,0xd9,0xfb,0x69,0x7e,0x61,0x89,0xbb,0x97,0x5f,0xfc,0xa9,0x94,0xea,0xda,0xa6, + 0x81,0x41,0x85,0x06,0xfe,0x0b,0xb2,0x7b,0xf7,0x23,0x77,0x22,0x04,0x30,0x61,0x7a, + 0xdc,0xbc,0xb8,0xb4,0xcc,0xde,0x81,0xfd,0x8b,0x99,0xb9,0xb5,0xad,0x83,0xb3,0xab, + 0x47,0x14,0x3f,0x3e,0x27,0xb7,0x18,0x78,0xa8,0x74,0x00,0x79,0x4d,0x54,0x71,0x97, + 0xd4,0xdb,0xdf,0x7f,0xf0,0xe0,0xe1,0xdf,0xbf,0x87,0xc5,0x7d,0x65,0xeb,0xd6,0x77, + 0x72,0xf3,0x0b,0xad,0xec,0x1c,0x38,0x4e,0x6e,0x5e,0x3e,0xfe,0xc1,0xa1,0xbc,0x70, + 0x5e,0x74,0x04,0x3f,0x36,0x12,0xab,0x0d,0x48,0x54,0x74,0x22,0x1c,0xe1,0x0e,0x9c, + 0xc4,0x25,0x24,0xa7,0x9d,0x39,0x57,0x2e,0xac,0xba,0xd2,0x89,0x16,0x50,0xa3,0x2d, + 0x9c,0xd4,0x01,0xe5,0xaf,0x88,0xfc,0x0e,0x0c,0x0e,0x5d,0x6a,0x6e,0xcf,0xcd,0x2f, + 0x4e,0x4e,0x49,0x8f,0x89,0x4f,0xa6,0x94,0x10,0x09,0x15,0x33,0x2f,0x2a,0x0e,0x29, + 0x67,0x74,0x5c,0x6c,0xfc,0xa9,0xe4,0x94,0x4c,0xf8,0x41,0x97,0x9a,0x3b,0x80,0xd6, + 0x69,0xd8,0xea,0x0b,0xf0,0x37,0x39,0x25,0x55,0x9d,0x23,0x71,0x52,0x83,0x00,0x10, + 0x43,0xc2,0xc2,0x42,0x42,0x23,0x00,0x7f,0xb3,0xb2,0xf3,0x5b,0xda,0xae,0x8c,0x8e, + 0x4d,0x68,0xe0,0xbf,0x10,0x27,0xf0,0xee,0xee,0x1e,0x49,0x65,0x55,0x4d,0x56,0x36, + 0xd4,0x9d,0x54,0x94,0x37,0x7e,0x9c,0xb2,0x04,0x12,0x54,0x72,0x4e,0xca,0x27,0x8a, + 0x9f,0x70,0xea,0x74,0x5a,0x6d,0x6d,0x9d,0x86,0xa5,0xe2,0x90,0x9f,0xd3,0xa9,0x69, + 0x61,0x11,0x91,0xd0,0x19,0xc8,0xce,0x2b,0x68,0x69,0xef,0x9c,0xbc,0x3e,0xa9,0x81, + 0xff,0x82,0xf6,0x4e,0x4c,0x5e,0xbf,0xda,0xd5,0x57,0x21,0xae,0xcd,0x3c,0x9b,0x13, + 0x97,0x98,0xcc,0x87,0x4e,0x38,0x3f,0xee,0x4e,0x2d,0x8e,0x89,0xc7,0xa9,0xc7,0xc5, + 0xc4,0x41,0xe2,0x99,0xf9,0x45,0x25,0xd5,0x75,0x4d,0xdd,0xbd,0x52,0xe8,0xb4,0xdc, + 0x54,0x63,0x00,0x29,0x95,0x49,0xf7,0xee,0xfb,0xfc,0x51,0x2b,0xb3,0x8a,0x3c,0xb7, + 0x76,0xab,0xb6,0xe5,0x35,0x64,0xda,0xc4,0x1c,0xd4,0x65,0x62,0xe4,0xc2,0x74,0x4f, + 0x9f,0x4d,0x0d,0x0e,0xc3,0x1d,0x72,0x84,0x3b,0x78,0x84,0x19,0xd0,0x50,0x0a,0x98, + 0x48,0xc6,0x5a,0x91,0x00,0x7a,0x02,0x0e,0x12,0x5b,0x23,0x78,0x8a,0x29,0x9e,0x21, + 0x7b,0x88,0xbc,0x85,0x9e,0x32,0xd1,0x18,0xb2,0x3e,0x82,0x1b,0xfa,0x52,0x61,0xc0, + 0x1a,0x40,0xc0,0xca,0xa2,0x5e,0xd1,0x65,0x62,0xa3,0x2f,0x26,0x40,0x24,0x9a,0x30, + 0xc5,0x6c,0x51,0x4e,0x27,0x44,0xc5,0x80,0xf1,0x17,0x6e,0x02,0xae,0x19,0xe0,0x73, + 0x3d,0x02,0xee,0xf8,0x92,0x02,0x41,0xa6,0xdc,0x10,0x81,0xa0,0x82,0x04,0x30,0x60, + 0xc9,0x11,0x2c,0x32,0xa5,0x70,0x07,0xa2,0x05,0x7c,0xc4,0xeb,0x80,0x14,0x0c,0x74, + 0x82,0x02,0xc3,0xbb,0x10,0x1e,0x92,0x60,0xe0,0xb7,0x20,0x1b,0xe4,0x45,0x06,0x6b, + 0x00,0x9e,0x1a,0x00,0x4b,0x45,0xb8,0x4f,0x72,0x25,0x27,0xa4,0x95,0x5c,0xae,0x43, + 0x91,0xc3,0xf9,0x10,0xb1,0xaa,0x22,0x93,0xbc,0x80,0xb0,0xc8,0xc2,0x0a,0xf7,0x0a, + 0xa0,0xb8,0xc8,0x38,0x33,0x70,0x5e,0x94,0x0a,0x46,0x61,0x84,0xbc,0x8e,0x28,0x18, + 0x03,0x1d,0x87,0x0d,0x1c,0x06,0x8d,0xd8,0x43,0xd0,0xb7,0x31,0x74,0xe8,0x33,0xb0, + 0xeb,0x32,0xb0,0x6e,0xdf,0x60,0x51,0xc7,0x30,0x15,0x19,0xfd,0x98,0xf3,0x13,0xb7, + 0x72,0x62,0x4a,0xd3,0x40,0xd0,0x5f,0x28,0x97,0x5a,0x5b,0x77,0xef,0xfd,0x6c,0xe7, + 0xae,0x3d,0x87,0x10,0xff,0xe5,0x04,0x06,0x85,0x26,0x26,0xa7,0xe5,0x15,0x14,0x57, + 0x88,0xeb,0xea,0x1a,0x9a,0x1b,0x2f,0x5d,0xbe,0xd8,0xd4,0x52,0x53,0xd7,0x28,0x28, + 0xaf,0x04,0x42,0x9a,0x78,0x2a,0x35,0x24,0x3c,0xd2,0xd5,0xdd,0xdb,0xc2,0xc6,0xee, + 0xc7,0x9f,0x8e,0xee,0xfb,0xe2,0xcb,0x8f,0x76,0xed,0xd9,0xb2,0x75,0xdb,0xa6,0xd7, + 0x5e,0x67,0x30,0x18,0x7a,0x7a,0x7a,0xab,0xd7,0xae,0x59,0xb9,0x6a,0xe5,0x8b,0x5a, + 0x5a,0xcb,0x96,0x6b,0x2d,0x59,0xb2,0x14,0xf9,0xc5,0x7a,0x0e,0x99,0x63,0x11,0x0a, + 0x4c,0x04,0xba,0xc7,0xc4,0x1c,0x8b,0x5a,0x97,0x34,0x6f,0x17,0x57,0x20,0xc8,0x7e, + 0xfe,0x01,0x71,0x09,0x89,0x08,0x7f,0xb3,0x72,0x5a,0x5a,0x01,0x7f,0x47,0x35,0xf4, + 0x9c,0xe7,0xe6,0x6e,0x02,0x8c,0xb6,0xb4,0x75,0xe4,0xe6,0x17,0x85,0x47,0xc6,0xba, + 0x7b,0xfb,0x73,0x5c,0x3c,0x9c,0x9c,0x5c,0x39,0x8e,0xae,0xd0,0xb4,0xb2,0x1d,0x5d, + 0x38,0xce,0xae,0x6c,0x27,0x17,0x47,0x67,0x77,0x16,0xe7,0x84,0xd3,0x09,0x0f,0x77, + 0x4f,0xdf,0x90,0xd0,0xc8,0x8c,0xac,0xdc,0x8b,0x8d,0x2d,0xd0,0xdf,0x9e,0x51,0xef, + 0x16,0xfe,0xfa,0xd4,0x8d,0x9f,0x8f,0xfe,0xa2,0x52,0xbf,0xcc,0x8e,0x1f,0x3b,0x9d, + 0x96,0x0e,0xdd,0x8f,0x93,0xc1,0x40,0xcf,0xd1,0xb6,0xad,0xd0,0xc4,0xa9,0x9b,0x8d, + 0x3a,0x74,0xf8,0xfb,0x07,0x9f,0x84,0x62,0x73,0x1c,0x85,0xa2,0xca,0xe2,0xd2,0xf2, + 0xce,0x6b,0x3d,0xe3,0x13,0x93,0xea,0xfc,0x77,0x41,0x23,0x24,0x91,0x49,0x0c,0x19, + 0xaa,0xfe,0xe7,0xdf,0xdf,0xfe,0x61,0x51,0x89,0xc0,0xc3,0xcb,0x1b,0x18,0xb4,0xb8, + 0xba,0xa1,0x5f,0x36,0xa8,0xc1,0xfe,0x0a,0xe4,0xeb,0xff,0x7c,0xf3,0x18,0x9a,0x29, + 0x50,0x00,0x4f,0x5f,0xef,0x73,0xf9,0xf9,0x56,0x36,0x0e,0xa6,0x66,0x16,0x56,0x36, + 0xf6,0xf0,0x5f,0x22,0xa3,0xe3,0x0b,0x0a,0xcb,0x80,0xda,0x0c,0xca,0x47,0x6e,0x4c, + 0x4d,0xa9,0x0c,0xc6,0x76,0xf5,0xf6,0xec,0xdc,0xf9,0xf1,0xc3,0xda,0x5d,0xce,0x64, + 0xe3,0xa6,0xf3,0x05,0x79,0x96,0x36,0xf6,0x66,0x56,0x36,0xb6,0x0e,0x6c,0x16,0xdb, + 0x09,0x94,0x84,0x08,0x74,0xae,0xe8,0x73,0xd0,0x1f,0xc7,0x13,0x6e,0x6e,0x1e,0xde, + 0x81,0x21,0xbc,0xb4,0x33,0x67,0x2f,0x36,0xb6,0x92,0x19,0x07,0x0d,0x03,0xc5,0xd7, + 0x6f,0x4c,0x77,0xf5,0xf4,0x57,0x88,0xab,0xe3,0x13,0x53,0xfc,0x03,0x43,0x1c,0x5d, + 0x3c,0x41,0x03,0x91,0x40,0xb4,0x8e,0x94,0x2a,0x92,0xc8,0x1d,0x9d,0x3d,0x4e,0xb8, + 0x7a,0xfa,0x05,0x04,0x27,0x9c,0x4a,0x11,0x56,0xd6,0xf4,0xa0,0x2d,0x9e,0x35,0x91, + 0xeb,0xdc,0xbc,0xbc,0x45,0xcf,0x2e,0xd2,0x5c,0xaa,0xde,0xbe,0x68,0xc9,0xad,0x8f, + 0x5f,0x50,0x66,0x56,0x4e,0x73,0x6b,0x3b,0x5a,0x6e,0x76,0x53,0xad,0xb5,0x12,0x68, + 0xc2,0xe8,0xf8,0x38,0xd0,0x64,0xa8,0xec,0xbc,0xa8,0x58,0x2f,0x5f,0xae,0x8b,0xab, + 0x27,0x55,0x71,0x94,0x45,0x81,0xc5,0x0d,0xf2,0x8c,0xb2,0xed,0x88,0x0b,0xc4,0xd9, + 0xc5,0xd7,0xff,0x24,0xf4,0xcd,0x17,0x2f,0xd1,0xe4,0x69,0x33,0x26,0x21,0x3e,0x22, + 0x32,0x8a,0x1b,0x14,0x7e,0x36,0x27,0xbf,0xb5,0xbd,0x73,0x0c,0x55,0x13,0xf5,0xbb, + 0x07,0xce,0xce,0x29,0x86,0x47,0xa0,0xb2,0x43,0x9d,0x0a,0xe5,0x45,0xbb,0x7a,0xfa, + 0x72,0x9c,0xdc,0x1d,0x9d,0xdc,0x9c,0x4e,0x50,0x65,0xc5,0x76,0x76,0x87,0x6c,0x40, + 0x66,0x5c,0xdc,0x3c,0xbd,0x7c,0x03,0x20,0xb7,0xd9,0x39,0xb9,0x17,0x9b,0x5a,0x65, + 0x83,0x43,0x6a,0xfb,0x93,0xbf,0xde,0x2e,0xaf,0x10,0x3d,0x14,0x1b,0x8c,0xdf,0x2f, + 0xcf,0x1b,0x7c,0xa4,0x67,0xd3,0xa3,0x87,0xe0,0x09,0x61,0xa8,0x21,0x6b,0x90,0xd8, + 0x5f,0x11,0x03,0x21,0x6c,0x29,0x84,0xd8,0xa8,0x21,0x53,0xb6,0x0e,0x39,0x40,0xa6, + 0x46,0x4d,0xf1,0x42,0x1b,0x02,0x61,0xc8,0x94,0x48,0x17,0xf1,0x41,0x19,0x86,0x27, + 0xf2,0xae,0x8c,0xb6,0x38,0xc2,0x4f,0xe5,0xd8,0x00,0x78,0x90,0x80,0x3b,0x36,0x9a, + 0xa2,0x2c,0x94,0x68,0x53,0x25,0x94,0x1c,0x6b,0x98,0x8e,0x5f,0x0f,0xd9,0x5c,0x11, + 0x23,0x25,0xe8,0x12,0xa0,0x77,0xf5,0x99,0x0a,0x3a,0x24,0xc4,0xac,0xc3,0x9c,0x17, + 0x98,0xa9,0x1c,0x25,0xc6,0x27,0xb4,0xe1,0x93,0xb6,0xc3,0x6f,0x92,0xa0,0x2f,0xa9, + 0xc0,0xac,0xdf,0x04,0xa6,0xdf,0xa5,0xe2,0x64,0x23,0xdc,0x24,0xb9,0x22,0xa3,0xca, + 0xb4,0x49,0x15,0x15,0x21,0xe6,0xd1,0xd4,0x11,0x07,0x33,0x44,0x53,0xba,0x48,0x7e, + 0x73,0xc9,0xa1,0x6e,0x12,0xd9,0xe0,0x88,0x21,0x98,0x5c,0x72,0x80,0x6e,0x2b,0x36, + 0xb0,0x65,0xc6,0x6c,0xa9,0x11,0xb3,0xd7,0x98,0xd9,0xa9,0x6f,0xdd,0xb9,0xd1,0xa6, + 0x61,0x93,0x45,0xa5,0xf1,0xd1,0x02,0x7b,0xfe,0xc5,0x59,0x35,0xfd,0xb4,0xbf,0x5c, + 0xba,0x7a,0x7a,0xf6,0x7f,0xf9,0x6f,0xc0,0xdf,0x6f,0x0f,0xfd,0x60,0x6d,0xcb,0x0e, + 0xe4,0x06,0x27,0x25,0xa7,0xe6,0xe6,0x97,0x88,0xc4,0x35,0x8d,0x97,0x5a,0x9a,0x5b, + 0x3b,0xa0,0x23,0xdd,0xd0,0xd4,0x5a,0x5d,0x53,0x5f,0x58,0x5c,0x96,0x9e,0x79,0x0e, + 0x58,0x24,0x84,0x61,0x72,0x4e,0x98,0x1e,0xb3,0xf8,0xfa,0x9b,0x23,0x9f,0xee,0xdb, + 0xbf,0xfd,0x83,0x9d,0x6f,0xfe,0x6b,0xcb,0xc6,0x4d,0xaf,0x19,0x19,0x19,0x69,0x6b, + 0xeb,0x20,0x16,0xbc,0x6a,0x95,0xd6,0x4b,0x2f,0x2d,0x7f,0x71,0xc5,0xd2,0xa5,0xcb, + 0x9e,0x5f,0x82,0xa6,0x83,0x9f,0x79,0xe6,0x59,0x7a,0x9b,0x60,0x95,0x6d,0x1a,0x08, + 0x16,0x3f,0xa1,0x74,0xc7,0xe1,0xe2,0xee,0x9e,0x9c,0x02,0x6d,0x57,0x30,0xa4,0x05, + 0x84,0x68,0x78,0x64,0x7c,0xee,0xd6,0x9c,0xba,0x76,0x09,0xf8,0xe0,0xd0,0xf0,0x58, + 0x53,0x73,0x2b,0x90,0x5f,0x68,0xca,0x98,0x6c,0x67,0x4b,0x2b,0x3b,0x53,0x73,0x2b, + 0x53,0x0b,0x6b,0x33,0x0b,0x1b,0x74,0x34,0xb7,0x86,0x4b,0x33,0x73,0x1b,0x38,0x9a, + 0x5b,0xd9,0xd9,0xd8,0xb3,0x3d,0x7d,0x02,0xa0,0xab,0x5f,0x59,0x5d,0x2f,0x95,0x0d, + 0xcd,0xdc,0xb5,0xf2,0x94,0x96,0x1b,0xd3,0x53,0x96,0x56,0xd6,0x2a,0xf5,0xeb,0xf3, + 0x2f,0xf6,0xe7,0xe4,0xe5,0x5b,0xdb,0x31,0xbd,0x7d,0x02,0x4e,0xa7,0xa2,0xa5,0xa3, + 0x68,0x5b,0xde,0xb9,0x7b,0xff,0x59,0x5e,0x14,0xff,0x01,0x47,0x4d,0xff,0xf6,0xe4, + 0xdf,0x62,0x13,0xe2,0x2b,0xab,0xeb,0x6a,0xeb,0x1b,0x24,0x32,0xf9,0xd4,0xf4,0xec, + 0xbd,0xdb,0x52,0x34,0x08,0x3f,0xdb,0xd6,0xde,0x71,0xb7,0xc3,0xae,0xb7,0xfe,0xf5, + 0xb6,0x40,0x58,0xee,0xe1,0xe5,0x17,0x1b,0x9f,0x8c,0x76,0x3d,0x96,0x0d,0xce,0x68, + 0xdc,0x0a,0xd3,0xf4,0xd8,0xf1,0x3f,0xba,0x65,0xd5,0x9f,0x93,0xe5,0xcb,0x96,0xfb, + 0x05,0xf8,0x65,0x64,0x9f,0xb5,0xb4,0xb1,0x43,0x6b,0x82,0xed,0xd8,0x1e,0x1e,0x01, + 0x90,0xc9,0xa2,0x92,0xb2,0xe6,0xd6,0xce,0xe1,0x91,0x91,0xe9,0x99,0x39,0xf8,0x2e, + 0xfa,0xef,0x00,0x7b,0x6a,0x6e,0x6b,0x05,0xde,0xfa,0x50,0xb2,0xa7,0xab,0xa7,0x9f, + 0x57,0x58,0x68,0x65,0x6d,0x07,0x04,0xdc,0xf4,0x98,0x95,0xa9,0x39,0x68,0x0b,0x12, + 0xa4,0x2a,0x16,0xd4,0xb9,0xb9,0xa5,0xed,0x31,0x73,0xeb,0xe3,0x96,0x36,0x36,0x76, + 0x2c,0x77,0x54,0x80,0x49,0x55,0xb5,0x75,0x12,0xa9,0x6c,0x46,0xc3,0x04,0xfa,0xaf, + 0xb7,0xa7,0xa6,0x66,0xbb,0x7a,0xfa,0xca,0xca,0x45,0x11,0x68,0x9e,0xc2,0x03,0xba, + 0x16,0x16,0x56,0xb6,0x28,0x66,0x2c,0x38,0x66,0x1b,0x9c,0x90,0xa5,0x99,0xa5,0x0d, + 0x74,0x3f,0x4e,0xb8,0xb8,0x87,0x85,0x47,0x17,0x96,0x96,0x5d,0xed,0xea,0x55,0x37, + 0x96,0x42,0x44,0x50,0x5e,0xae,0x79,0x8b,0x28,0xa8,0x47,0x6e,0xee,0x6e,0x71,0x09, + 0x49,0xde,0xbe,0xdc,0xd3,0x19,0xe7,0x1b,0x9a,0xdb,0xf0,0x72,0x6f,0xf5,0xac,0xf3, + 0xe6,0xed,0xe1,0x91,0x51,0xa8,0xe0,0xa8,0xee,0x9c,0x0c,0x61,0xb2,0x9d,0xa0,0x82, + 0x98,0x5b,0xda,0x90,0x1c,0xce,0xcb,0x33,0xb9,0x03,0xb5,0xc9,0xca,0xdc,0x12,0xdd, + 0xb7,0xe7,0x38,0x43,0x9f,0x70,0xd9,0x32,0x55,0xef,0xac,0xf3,0x25,0x2c,0x02,0xd4, + 0x3f,0x06,0xaa,0x64,0x56,0x4e,0x5e,0x73,0x5b,0xa7,0x86,0x95,0x02,0xb7,0xf1,0x06, + 0x58,0x80,0xbf,0xd0,0xbd,0x49,0x3d,0x73,0xd6,0x27,0x30,0xcc,0x9e,0xe9,0x08,0xbf, + 0xc6,0xcc,0x9c,0x2e,0x2b,0x2b,0x3a,0x3f,0x90,0x43,0x3b,0x07,0x96,0x9b,0xbb,0x4f, + 0x74,0x6c,0x42,0x69,0x99,0x08,0x28,0x33,0x14,0x9a,0xba,0x6f,0x84,0x76,0xe3,0x93, + 0xdd,0x7b,0x1f,0x9b,0x21,0x16,0x24,0xb4,0xfc,0xf5,0xef,0xd6,0xd9,0x4a,0xf4,0x31, + 0xa2,0x01,0x1c,0xe8,0xd0,0x50,0x88,0x05,0x53,0x48,0x05,0x26,0x86,0x98,0xdc,0xe1, + 0x11,0x57,0x32,0xf4,0x8a,0x2f,0x09,0x17,0x06,0xac,0xc1,0x8f,0x30,0x7d,0x46,0xe4, + 0x14,0xd0,0x16,0x0d,0x02,0xa3,0x77,0xd7,0x29,0x63,0x33,0x60,0x0d,0xd3,0x91,0x60, + 0xeb,0xa3,0xe1,0x75,0xf6,0x98,0x72,0xa2,0x09,0x5c,0x84,0xe0,0x7a,0x4c,0x74,0x4e, + 0x02,0x93,0x08,0x11,0x8a,0x51,0x89,0x52,0x88,0x89,0xd7,0xf2,0x50,0x1c,0x13,0xd9, + 0x32,0x61,0x0c,0x05,0x9a,0x49,0x11,0x52,0x0e,0xc6,0x50,0xcc,0x3a,0xe1,0x11,0x7d, + 0x49,0x07,0x46,0x14,0x1e,0xd3,0x52,0xcc,0xc7,0x29,0x9c,0x55,0xb9,0xd4,0x57,0xc6, + 0x46,0x60,0x9a,0x9e,0xa8,0xd5,0xc5,0x94,0x96,0xe2,0xb3,0xf8,0x84,0xc4,0x6c,0x88, + 0xe9,0x2d,0x61,0xb8,0x78,0x88,0x60,0x18,0xb8,0xed,0x7a,0x84,0xad,0x28,0x03,0x10, + 0x18,0x8e,0x46,0x00,0xbb,0xec,0x31,0xe0,0xbf,0x46,0xf8,0xd2,0xd8,0x11,0x3d,0x35, + 0x72,0x02,0x38,0x56,0x18,0x73,0x06,0x4d,0x38,0x03,0x26,0x9c,0x7e,0x13,0x56,0x97, + 0xb1,0xc3,0x95,0x8d,0xd6,0xf5,0x9b,0x2c,0xab,0x36,0x9a,0x16,0x79,0xa7,0xb7,0xfe, + 0xcf,0xae,0xee,0x97,0x0f,0xc9,0x0f,0x1d,0xf9,0x6e,0xc7,0xc7,0x9f,0x60,0xfc,0x65, + 0xf9,0x07,0x72,0xe3,0x12,0x53,0xf2,0x0a,0x04,0xa2,0x4a,0x80,0x97,0xcb,0xad,0x97, + 0x3b,0x5a,0x2f,0x5f,0x6d,0x69,0xeb,0xac,0x6f,0x68,0xae,0x10,0xd7,0xe4,0xe4,0x16, + 0x24,0x25,0xa7,0x85,0x47,0x44,0xbb,0x78,0xfa,0xd9,0xda,0xb1,0x7e,0xfa,0xaf,0xe9, + 0x57,0x5f,0x7d,0xb3,0xeb,0x93,0x7d,0xdb,0xde,0xfb,0x60,0xf3,0x9b,0x5b,0x8c,0x8d, + 0x4d,0x0c,0x0d,0x0d,0x75,0x74,0x74,0x56,0xaf,0x5e,0xf3,0xf2,0xcb,0x6b,0x56,0x68, + 0x69,0xd1,0xe6,0x58,0x4b,0x16,0xbf,0x40,0xfb,0xe5,0x78,0x7a,0xe1,0x33,0x64,0x3a, + 0x98,0xec,0x57,0x08,0xfd,0x76,0x62,0x1d,0x4d,0x88,0x30,0x30,0xbe,0xb4,0xcc,0x4c, + 0x1f,0xff,0x00,0xa8,0x8c,0x0d,0x80,0xbf,0xc3,0xa3,0x37,0x6f,0xa9,0x35,0x4d,0x81, + 0x66,0xf9,0xfa,0x8d,0x99,0xce,0x6b,0xbd,0xa2,0xca,0x9a,0x33,0x19,0x39,0xd0,0x48, + 0x86,0x46,0x44,0x87,0x84,0xf1,0x82,0xc3,0xa2,0x42,0xc2,0xa3,0x42,0x23,0x90,0x84, + 0x84,0xf3,0x42,0x23,0xf8,0x61,0xe1,0xfc,0x50,0x5e,0x94,0xb7,0x1f,0xf7,0x84,0x9b, + 0x47,0x4c,0x7c,0x92,0xb8,0xaa,0xa6,0x47,0x32,0xa4,0xc1,0x41,0x2e,0x5a,0xf1,0xc1, + 0xe6,0xa8,0x54,0xb1,0x37,0x37,0xbf,0x55,0x54,0x5a,0xec,0xc0,0x74,0x74,0x71,0xf7, + 0xe1,0xc7,0x26,0x56,0x88,0xab,0x7a,0xfa,0xa4,0x78,0x1e,0xf9,0x1e,0x2d,0x40,0x43, + 0x63,0xe3,0x3a,0x9d,0x75,0x0f,0x52,0xa3,0xb5,0x56,0xbc,0x24,0xae,0xac,0xac,0xaa, + 0xa9,0xed,0xb8,0xda,0x35,0x32,0x36,0xa6,0x6e,0x1c,0x00,0x3a,0x21,0x40,0x18,0x4b, + 0xcb,0xcb,0x96,0x2c,0x7e,0x5e,0x25,0x86,0x8d,0xaf,0xbd,0x0e,0x4d,0xa5,0xa7,0x37, + 0x82,0x36,0xa1,0xb8,0xa6,0x5f,0xa6,0xd0,0xec,0x89,0xc8,0xc2,0xca,0xfa,0xf1,0xe0, + 0x2f,0xc8,0xea,0x55,0xab,0x53,0xd3,0xd2,0x13,0x4f,0x25,0x1d,0x43,0x7d,0x24,0x0b, + 0x7b,0x96,0xa3,0x9f,0x7f,0x48,0xe2,0xa9,0xf4,0xb2,0x0b,0x95,0x57,0xbb,0xba,0xef, + 0x69,0x5b,0x5e,0x2a,0x28,0xd7,0x37,0x30,0x7c,0xf0,0xa4,0x5f,0x59,0xfb,0x6a,0x85, + 0x58,0xc4,0x8f,0x89,0x0b,0x45,0xba,0x81,0x54,0x25,0x18,0x24,0x14,0xa9,0x0a,0xd1, + 0x1c,0x24,0x61,0xa0,0x3c,0x3c,0xd0,0x19,0x3f,0xff,0x93,0x6e,0xee,0x9e,0x3c,0x7e, + 0x82,0x50,0x54,0x25,0x91,0xca,0x35,0xb8,0x52,0x24,0xf8,0x2b,0x1f,0x1a,0x6e,0x6a, + 0xbe,0x9c,0x5f,0x58,0x9c,0x78,0x2a,0x25,0x82,0x1f,0x0b,0x31,0x28,0x63,0xbb,0xa3, + 0x93,0xa1,0xe1,0x11,0xa1,0x11,0x91,0xdc,0xe0,0x70,0xa0,0x78,0x41,0x21,0x91,0xb9, + 0x05,0x25,0xd8,0xd4,0x41,0xd3,0x20,0xad,0xb8,0xaa,0x6a,0xe9,0x92,0xa5,0x1a,0x3e, + 0x0a,0xea,0x0e,0x93,0xc5,0x3c,0x75,0x3a,0xd5,0xc7,0xef,0x64,0xda,0x19,0xb4,0xdc, + 0x6c,0x48,0xa1,0x69,0xb9,0xd9,0x6d,0x64,0x33,0x3f,0xd9,0xdd,0x2b,0x11,0x57,0xd5, + 0x9d,0xc9,0x3a,0x17,0x1b,0x77,0x2a,0x34,0xf2,0x4e,0x0e,0xc3,0x79,0x31,0x90,0xe7, + 0x10,0xba,0x34,0xd0,0x27,0xf0,0x50,0x81,0x44,0x44,0xf1,0x63,0xe3,0x1b,0x9a,0x2e, + 0xad,0xd4,0xb8,0xb1,0x57,0x60,0x50,0x70,0x7c,0x42,0xa2,0x5f,0x40,0x50,0xe6,0xd9, + 0xbc,0x4b,0x2d,0xed,0x9a,0xf1,0x17,0x14,0x78,0x7c,0x62,0x02,0x7a,0x20,0x17,0x2a, + 0x2a,0xcf,0x64,0x9e,0xe3,0xf1,0x63,0x22,0xa2,0xa2,0x95,0x95,0x97,0xa4,0x1b,0x75, + 0x32,0x38,0x1c,0x6a,0xdd,0x31,0x40,0x64,0x73,0x0b,0x26,0xc7,0x25,0x30,0x84,0x97, + 0x97,0x5f,0xd2,0x76,0xf9,0xea,0xd8,0x98,0xa6,0x25,0xed,0x91,0x7c,0xfe,0x63,0xdb, + 0x54,0x6b,0xc1,0x82,0xbf,0xaf,0x78,0x97,0xa9,0x6f,0x3f,0xc0,0xe0,0x20,0x50,0xd3, + 0xc7,0x43,0xac,0x04,0x62,0x10,0x70,0x38,0xc8,0x31,0x7d,0x53,0x50,0x63,0xad,0x6c, + 0xc4,0xe9,0x08,0x86,0x1a,0x60,0x3c,0xc5,0x9c,0x4e,0xf1,0x7b,0x2e,0xf5,0x10,0x46, + 0x53,0xd1,0x12,0x3c,0x55,0x09,0xac,0xaf,0x14,0x62,0xa4,0x64,0x88,0x5f,0x31,0xc0, + 0xf0,0x4a,0x20,0x98,0x81,0x87,0x76,0x09,0x2c,0x1a,0x12,0x2b,0x62,0x14,0x1e,0xf5, + 0x0d,0xee,0x50,0x4e,0x14,0x9b,0x62,0x3e,0xd6,0x93,0x4b,0x3c,0x33,0x4b,0xa5,0x8b, + 0x9f,0x2a,0x68,0x58,0x9f,0x7f,0xa9,0x7f,0xa7,0xcb,0x71,0x27,0x5d,0xf8,0x6a,0x54, + 0x38,0x38,0x03,0x7a,0x04,0x52,0x71,0x59,0x19,0x60,0x28,0x07,0xa8,0x85,0x4b,0x7d, + 0x8c,0xda,0x50,0x56,0x00,0xbb,0x0c,0xf6,0x98,0x2e,0x35,0xc8,0x8c,0x06,0x9c,0x37, + 0x38,0xe1,0x4b,0x8e,0x02,0x98,0x2f,0xa0,0xf0,0x06,0xc7,0x31,0x88,0x01,0x42,0xc2, + 0xe5,0x06,0x8c,0xbf,0x0c,0xb6,0xdc,0xc4,0x71,0x08,0xf0,0x77,0xb3,0x63,0x97,0x09, + 0xf3,0xca,0xff,0x33,0x77,0xe5,0x61,0x51,0xde,0x5a,0xff,0x8f,0xab,0x40,0x15,0x14, + 0x10,0x14,0x2b,0x2e,0xe0,0x2e,0x9b,0xc8,0x6a,0x15,0xdc,0xb5,0xa8,0xb5,0x2e,0x55, + 0x5b,0x6d,0xaf,0x5a,0xef,0x75,0x6f,0x2d,0x55,0xac,0x45,0x18,0x66,0x98,0x61,0xdf, + 0x11,0x41,0x45,0x51,0x44,0x10,0x15,0x17,0x44,0x40,0x10,0x64,0x11,0x64,0x17,0x54, + 0x14,0x41,0x16,0xd9,0xb7,0x19,0x86,0x45,0x5c,0xaa,0xf7,0x7b,0xbe,0x93,0xe4,0x9d, + 0xf0,0x3a,0xc3,0x8c,0xbd,0xf7,0x9f,0x76,0x9e,0x3c,0x79,0x92,0x4c,0x72,0x72,0x92, + 0x9c,0xe4,0x97,0x93,0x37,0xcb,0x5c,0xc7,0x47,0x56,0x0e,0x45,0xd6,0xf6,0xe9,0x91, + 0x29,0x35,0x7f,0x5b,0xfc,0xed,0xee,0xed,0x3d,0xf0,0xf3,0xc1,0x15,0x76,0xab,0x7f, + 0xd8,0xf6,0xa3,0xfd,0xaf,0x0e,0x3e,0x81,0xa7,0x00,0x7f,0x93,0xee,0xa4,0xe5,0x17, + 0x96,0x94,0x3e,0x2a,0xaf,0xaa,0x7e,0x59,0x55,0x5d,0xf7,0xbc,0xaa,0xfa,0x71,0x79, + 0x45,0x61,0x51,0x69,0x5a,0xfa,0xfd,0xf8,0x84,0xe4,0xc8,0xa8,0xd8,0xc0,0x90,0x30, + 0xbe,0x9b,0x27,0x28,0x2f,0xbb,0x77,0xef,0xdb,0xf4,0xed,0x96,0x55,0x5f,0xad,0x5b, + 0xb2,0x74,0x99,0xf5,0xdc,0x2f,0x08,0x04,0xcf,0x9a,0x35,0x0b,0xdd,0x8b,0x35,0x49, + 0x5f,0x77,0x22,0x68,0xc1,0x00,0xc1,0xe8,0x5c,0xb0,0xb6,0xf6,0x98,0x51,0x9a,0x5a, + 0x1a,0xea,0xe8,0xa5,0x42,0xf6,0xd1,0x24,0x02,0xc4,0xe4,0x5b,0x30,0xd8,0x07,0x7f, + 0xf9,0xf5,0x7a,0x7c,0x82,0xb7,0x5f,0xf0,0xe5,0xb8,0xf8,0x92,0xb2,0x72,0xf4,0xd1, + 0x53,0xfe,0x37,0xac,0xee,0xde,0x9e,0x88,0xc8,0x08,0x9e,0x2b,0x8f,0xeb,0xca,0xe1, + 0xf2,0xb8,0x2e,0x3c,0x0e,0x8f,0xef,0x42,0x1c,0x60,0x73,0x79,0x3c,0x17,0x9e,0x0b, + 0x71,0x40,0xf8,0xc9,0xf0,0x53,0x79,0x85,0x45,0x02,0x77,0xef,0xb3,0xe7,0xa3,0xb2, + 0x73,0xf2,0x1b,0x9b,0x5b,0x14,0xbc,0xde,0x0b,0xc3,0x85,0x5f,0x40,0xe0,0x40,0xe7, + 0xc2,0xbb,0xc5,0x40,0xc1,0xbc,0x9d,0x94,0xcc,0xf7,0xf0,0x76,0xe2,0xf0,0x83,0x42, + 0xc2,0x92,0x53,0xd2,0xcb,0x9f,0x55,0x02,0x32,0x0e,0xca,0x61,0xff,0x9b,0xd7,0x07, + 0x0f,0xda,0x93,0xe4,0x04,0xd4,0x06,0x85,0x36,0xa9,0x40,0xba,0x3f,0x1c,0xb2,0xfb, + 0x7a,0xed,0x3a,0xa8,0x7c,0xc8,0xa2,0xa3,0x53,0xd4,0x2f,0xff,0xfb,0xc5,0x9b,0xb7, + 0xef,0x7a,0xfb,0xfa,0x4e,0x85,0x87,0xd3,0xfd,0x39,0x94,0xc8,0x8c,0x99,0xb3,0xee, + 0xe7,0x3d,0xf0,0xf6,0xf1,0x3f,0x77,0x3e,0x3a,0x2b,0x3b,0xbf,0xa9,0xa5,0x45,0xf1, + 0x4d,0x08,0x7c,0x81,0x9b,0x8a,0xf2,0x67,0xf2,0xb8,0x25,0x95,0xc0,0xfe,0x57,0x9e, + 0x2d,0x5b,0x3a,0xea,0x20,0x44,0x90,0x19,0x32,0x74,0xca,0xd4,0x69,0x71,0x37,0x6e, + 0x46,0x5f,0x8a,0x85,0x71,0xd5,0xfe,0xf0,0x6f,0x4e,0xce,0xae,0xbe,0x01,0xc7,0x2f, + 0x5e,0x8a,0xbd,0x8f,0x0e,0x05,0xd7,0x75,0x89,0x7b,0xa0,0x62,0xd9,0x53,0x2f,0x80, + 0xa7,0x9c,0xdc,0x7c,0xbd,0x89,0x7a,0x74,0xcf,0xc0,0x27,0x67,0x0b,0x94,0x2b,0xf6, + 0x7e,0x3f,0x8d,0x91,0x1a,0xfb,0xf6,0xef,0x77,0xe1,0x39,0x63,0x51,0x21,0x36,0x07, + 0x1c,0x44,0x90,0x78,0x7c,0x1e,0x97,0xe7,0x02,0x92,0xc3,0x71,0xe1,0x06,0x04,0x05, + 0xe4,0x15,0x16,0x7a,0x78,0xf9,0x9f,0x3e,0x13,0x89,0x1e,0x15,0x6a,0x68,0x62,0x5e, + 0x04,0x90,0x53,0x81,0x45,0x45,0x45,0x6e,0xee,0x7c,0x4a,0x13,0x6c,0x10,0x3c,0xf0, + 0xba,0x60,0x82,0x5c,0x9e,0x2b,0xb1,0x21,0x5c,0xe0,0xce,0xcf,0xcd,0x2f,0x38,0x11, + 0x1a,0xe6,0x17,0x74,0x3c,0xf1,0x4e,0x7a,0x79,0x65,0x9d,0xb8,0x5b,0xd1,0x26,0xe1, + 0xb2,0xc7,0x8f,0xc7,0xeb,0x8e,0x97,0xf7,0xa6,0x27,0xaa,0x8a,0xa1,0x4a,0xfb,0xf6, + 0x1f,0x88,0xbf,0x95,0xe0,0xed,0xeb,0x07,0xf8,0x0b,0xea,0x24,0x7a,0x78,0x57,0xc1, + 0xf7,0xdf,0x0f,0x00,0x4f,0x67,0x48,0xc7,0xc1,0x3d,0xc5,0x19,0x3b,0xb8,0x98,0x73, + 0xc2,0x2d,0x57,0xd2,0x9b,0x24,0xcc,0x73,0x71,0x04,0x57,0x8e,0xfd,0xa1,0x5f,0xa0, + 0x0b,0xb3,0x1b,0x54,0x4a,0x00,0xf8,0x02,0x41,0x74,0xcc,0x65,0x5f,0xbf,0xc0,0xeb, + 0x37,0x13,0x4b,0x1f,0x97,0x8b,0xba,0x7a,0xe4,0x2d,0x13,0xe1,0x5e,0xdc,0x1d,0x7e, + 0xe6,0x2c,0x54,0x3b,0x6a,0x02,0x5c,0x5d,0x1c,0x2e,0x3b,0x5f,0xc8,0x94,0xe3,0x1f, + 0x10,0x98,0x74,0xe7,0x4e,0xe6,0xfd,0x2c,0x81,0x87,0xa7,0x13,0x87,0x7b,0x22,0x34, + 0x3c,0x31,0x39,0xed,0x59,0x45,0x15,0xde,0x3a,0x2e,0x17,0xd9,0x2b,0x2a,0x2b,0x0d, + 0x66,0x19,0x52,0xae,0x64,0x05,0xf8,0xcf,0x98,0x3f,0xd9,0x79,0x95,0x94,0x55,0xf5, + 0xd7,0x05,0x1b,0x3a,0x75,0x18,0x73,0x18,0xfc,0x22,0x20,0x02,0x6e,0x80,0x95,0xd9, + 0xce,0x08,0xbc,0xc0,0x06,0x4d,0x8d,0xfc,0x65,0x8c,0xb5,0x45,0x82,0x20,0x44,0xdd, + 0x03,0x88,0x31,0x92,0x24,0x04,0x83,0xfe,0x75,0x62,0xfe,0x45,0x38,0x8e,0xe3,0x90, + 0x7f,0xa5,0xbc,0x28,0x32,0x8e,0x4f,0xdc,0x78,0x93,0x52,0x27,0x36,0x12,0xe2,0x4e, + 0x42,0x53,0x80,0x2d,0xbc,0x55,0x18,0xa0,0x0a,0x01,0x1f,0x80,0x9d,0x33,0x86,0x36, + 0x92,0x11,0xb3,0xba,0xcb,0x68,0x9a,0x46,0x1c,0x19,0x26,0x49,0x71,0x9c,0x31,0x29, + 0x97,0x4e,0x26,0x89,0x24,0x47,0x23,0x27,0x16,0x05,0xac,0x99,0x12,0x07,0x89,0x86, + 0x72,0xc4,0xb6,0x09,0x0e,0x37,0x71,0x26,0xf5,0x83,0x15,0x58,0x56,0x11,0x88,0xda, + 0x6b,0xc4,0xe9,0x32,0xe2,0x88,0x66,0x23,0xde,0xc4,0x10,0x01,0x40,0x16,0xea,0x70, + 0x36,0x42,0xdb,0x4e,0xc8,0xd7,0x9c,0xdb,0x39,0x9b,0x8b,0xa2,0x99,0x71,0x3b,0xcd, + 0x79,0x42,0x73,0x57,0x21,0xb2,0x19,0x47,0x27,0xd8,0x16,0xdc,0xe6,0x2f,0xf8,0x6d, + 0xd6,0x2e,0x75,0xf3,0x38,0x55,0xb6,0x4e,0xe5,0xf3,0x8e,0x16,0xd8,0x1c,0xcd,0x4e, + 0x2a,0x6c,0xf8,0xcb,0x71,0x56,0x9e,0x79,0xfd,0xf6,0xed,0x31,0x0e,0x6f,0xe9,0xb2, + 0x15,0xdf,0xff,0xb0,0xdd,0xde,0xfe,0xb0,0xa7,0xef,0x71,0xd0,0x95,0x40,0xcf,0x85, + 0x59,0x31,0x60,0x2e,0xe0,0x6f,0x4d,0x5d,0x63,0x4d,0x5d,0x43,0x45,0x65,0xcd,0xa3, + 0x27,0x4f,0x1f,0xe4,0x17,0xa4,0xdc,0x4d,0xbf,0x12,0x77,0x03,0x86,0x23,0x2f,0xff, + 0x10,0x67,0x17,0xee,0xcf,0xbf,0x1c,0xda,0xf1,0xe3,0xae,0x0d,0xdf,0x6c,0x59,0xb5, + 0x6a,0xcd,0x82,0x45,0x8b,0xc9,0x89,0x60,0x43,0x43,0x23,0x72,0x22,0x49,0x4f,0x1f, + 0x41,0x30,0xba,0x9a,0xe3,0xf3,0x71,0xa0,0x08,0x03,0x06,0xa3,0x4d,0x59,0xea,0x5a, + 0xa0,0x02,0x83,0x3a,0x0c,0xf8,0x4b,0x56,0xa4,0xc9,0x72,0x34,0x51,0x84,0xf7,0xec, + 0xdd,0x77,0x2b,0x31,0xd9,0xcf,0x3f,0xe8,0xf2,0x95,0x9b,0xc5,0x78,0xd3,0xd1,0x9b, + 0x37,0x72,0xc7,0x90,0xb6,0x8e,0xb6,0x95,0xab,0x57,0x43,0x42,0x62,0x08,0x11,0xb0, + 0xd1,0x5e,0x2f,0xbc,0xbe,0x4d,0x0c,0xf9,0xd7,0xdc,0xc2,0x3c,0xed,0xde,0x3d,0xfc, + 0xb8,0xc3,0x85,0xcc,0xec,0xfc,0xfa,0xc6,0x96,0x57,0xaf,0xe4,0x2e,0xc6,0xc2,0xe8, + 0x74,0x02,0x5f,0xb2,0x47,0x9f,0x50,0x04,0x03,0x3c,0x87,0x9e,0x0c,0x3d,0x13,0x71, + 0xee,0xe8,0xef,0x4e,0x5e,0x3e,0xfe,0xd1,0xb1,0xd7,0xf2,0x0b,0x4b,0x9b,0x9a,0xe5, + 0x6e,0x4b,0xce,0xbe,0x9f,0xab,0xab,0x3b,0x9e,0x4d,0x64,0x08,0x5e,0x55,0xa6,0x0e, + 0xd9,0x40,0x3a,0x9a,0x8d,0x50,0x1d,0x11,0x76,0xea,0x54,0x3d,0x3e,0x8b,0xd1,0xf7, + 0xaa,0x5f,0xde,0x3a,0xf9,0x7b,0x74,0xf2,0xa8,0x4f,0x28,0x12,0xd9,0x1f,0xb2,0x57, + 0x96,0xec,0x50,0xa2,0x44,0xf4,0xf5,0x26,0xe7,0xe4,0xe5,0xf9,0xfa,0x05,0x9c,0x39, + 0x77,0x11,0x94,0x8b,0xba,0x97,0x8d,0x8a,0x6f,0xc2,0xf7,0x0d,0x08,0x80,0xb9,0x10, + 0xe5,0x84,0x6c,0x8a,0xa3,0x7b,0xe4,0x28,0x74,0x4a,0x95,0x48,0xca,0x96,0x2a,0x8b, + 0x54,0xb9,0x06,0xf0,0x17,0x1b,0x1b,0x5b,0xdb,0xe4,0xd4,0x94,0x90,0xd0,0x93,0x47, + 0x7e,0x3b,0xe6,0x08,0xd3,0x1a,0x0f,0xdf,0x90,0xb0,0xb3,0x09,0x89,0x77,0x8b,0x4b, + 0x1f,0x37,0xb5,0xb6,0xc8,0x7e,0x08,0x86,0xc1,0x16,0x14,0xb0,0x49,0x13,0xf5,0xa4, + 0x68,0xb2,0x99,0xa4,0xb6,0x54,0xf3,0xb1,0xab,0x5d,0x45,0x69,0x40,0x36,0x40,0x5a, + 0xc0,0x86,0x82,0xb3,0x05,0x89,0x48,0x11,0xcc,0x24,0xef,0x65,0xa6,0xfb,0xf8,0x05, + 0x9c,0x0a,0x8f,0x80,0x39,0x5b,0x5d,0x7d,0xa3,0xbc,0xe5,0x0e,0xdc,0x16,0xef,0xcf, + 0x9f,0x8f,0xd4,0xd4,0xd0,0xa4,0x94,0x29,0x7d,0x76,0x08,0x31,0x1a,0xea,0x1a,0x67, + 0x23,0xce,0x85,0x9d,0x3e,0x13,0x10,0x74,0x22,0x31,0x19,0x26,0x72,0x55,0x78,0x73, + 0x97,0x5c,0x90,0xaa,0x7c,0xf1,0x62,0xe2,0x84,0x49,0x52,0xd3,0x18,0xb6,0x14,0xc1, + 0x5f,0xdb,0x77,0xec,0x4c,0x48,0x4a,0xf1,0xf6,0x0d,0xb8,0x74,0xf9,0xfa,0xc3,0xb2, + 0xf2,0xb6,0xf6,0x0e,0x79,0xdb,0x93,0x88,0xe4,0xd8,0xd9,0xad,0xa6,0xec,0x49,0x31, + 0xc9,0x66,0x9e,0xba,0xe9,0x82,0x15,0x04,0x92,0x86,0x96,0x6a,0x05,0x6a,0x3b,0xbb, + 0x70,0x62,0xaf,0xc6,0x01,0xfe,0x5e,0xbb,0x71,0x0b,0x66,0xd1,0xa2,0x2e,0xb1,0x02, + 0xc1,0x6b,0xef,0xec,0x58,0xb2,0x64,0x89,0x54,0xbe,0xec,0xba,0x02,0x03,0x03,0x85, + 0x9e,0x9e,0xfe,0x2f,0xf6,0xbf,0xe6,0x3c,0xc8,0x0b,0x39,0x11,0x76,0xee,0xfc,0xc5, + 0x8c,0xac,0x07,0xa0,0x32,0xe3,0x43,0x61,0x72,0xe5,0x59,0x24,0xee,0x5e,0x61,0x67, + 0x37,0xa8,0x18,0x50,0xf1,0x96,0x5a,0xa0,0x56,0x2c,0xd8,0xec,0xae,0xca,0xc6,0x5f, + 0x08,0x54,0x19,0x3e,0x6a,0xda,0xf6,0x9b,0x00,0x73,0xc6,0x68,0x5b,0x2f,0x82,0x24, + 0x40,0x1c,0xaa,0xcd,0x99,0x72,0x3a,0x0c,0x8e,0x36,0x1b,0x1d,0x46,0x0f,0xd4,0x4e, + 0xdd,0x93,0x3b,0x75,0x6f,0x9e,0xc1,0xc1,0x87,0x06,0x0e,0x35,0x86,0x47,0x9b,0x4c, + 0xf1,0x77,0x4c,0x13,0xb4,0xac,0x8a,0x50,0xc6,0xc0,0x89,0x49,0x42,0x00,0x14,0xdc, + 0xb3,0xb1,0xc3,0x14,0xa9,0x87,0xc8,0x2d,0xeb,0x35,0x72,0x66,0x22,0x1b,0x38,0x31, + 0x91,0x4d,0x58,0x28,0x6c,0x8a,0x41,0xd6,0xd8,0x05,0xb1,0x64,0x22,0x81,0xd4,0xd9, + 0x14,0x07,0x25,0xd1,0x0c,0x25,0x90,0x4a,0xbd,0x86,0xc4,0x4b,0xd4,0x52,0x8c,0xb0, + 0x14,0xd0,0x3f,0x82,0x6c,0x0e,0xc5,0x68,0x26,0x84,0x50,0x66,0x78,0xc0,0x0a,0x38, + 0x49,0x0b,0x30,0x2a,0xc9,0x9a,0x01,0x77,0x02,0xcd,0xe4,0x5f,0xa8,0x3a,0x13,0x52, + 0x28,0x2e,0x8a,0x09,0x6e,0x33,0x2e,0x0a,0x24,0x5e,0x33,0x1e,0x8e,0xc3,0x45,0xff, + 0x42,0xb8,0x39,0x1b,0x7f,0x5d,0x45,0xc8,0xe1,0x2a,0x9c,0x27,0x68,0x03,0x33,0x9f, + 0xdf,0x38,0xdf,0xb5,0xc1,0xd6,0xb5,0x76,0x31,0xf7,0xc9,0xc2,0x63,0x05,0x4b,0x8e, + 0x65,0x17,0x56,0xb4,0xfe,0xe5,0x38,0x2b,0x1f,0x68,0xde,0x07,0x06,0x06,0x2d,0x59, + 0xba,0xfc,0xbb,0xef,0x7e,0xf8,0xe9,0xa0,0xbd,0x87,0x4f,0xc0,0xd9,0xf3,0x17,0x12, + 0x12,0xef,0x64,0xe7,0x16,0x97,0x3d,0xae,0x78,0x51,0xd3,0x50,0xfb,0xb2,0x09,0xcc, + 0x8b,0x9a,0xc6,0xf2,0x0a,0xb4,0x0a,0x9d,0x9d,0x53,0x90,0x94,0x9c,0x16,0x7d,0x29, + 0xee,0x64,0x78,0x84,0x9b,0x87,0xdf,0x11,0x47,0xce,0xbe,0x03,0x07,0xb7,0x6d,0xdf, + 0xb9,0xee,0x9b,0xcd,0xcb,0xbf,0x5c,0x65,0xbb,0x70,0x31,0x68,0xc1,0xa6,0x73,0x24, + 0x0b,0xd1,0x53,0xf4,0x01,0x82,0x27,0x4c,0x44,0x17,0x44,0x7f,0x3e,0x0e,0x7f,0x0e, + 0xd6,0x06,0x1c,0x66,0x14,0x61,0xf4,0x5e,0xd2,0x08,0xf4,0x64,0x21,0xfb,0xb2,0xac, + 0x6d,0x3b,0x7e,0x4c,0xba,0x73,0xd7,0xdb,0x17,0xf0,0xf7,0x46,0x51,0x49,0x59,0x2b, + 0xda,0xf1,0x22,0x17,0x7f,0x3b,0x45,0xc2,0x6f,0x36,0x6e,0x62,0xfa,0xc2,0x50,0x25, + 0xa2,0x10,0xd1,0x0d,0x5d,0xa4,0x8b,0xd1,0x7b,0xb7,0x0c,0x8d,0x8c,0xef,0xa4,0xdf, + 0x73,0xf3,0xf0,0x3a,0x1d,0x7e,0x21,0x23,0x2b,0x07,0x2f,0x1d,0x4b,0x0f,0xef,0x03, + 0xe6,0x3f,0x1f,0x22,0x23,0x2f,0x4a,0x3d,0xa1,0x08,0xa4,0xfe,0xb5,0x7b,0x4f,0x4a, + 0x5a,0xda,0x51,0x47,0x27,0x1e,0x5f,0x10,0x12,0x1e,0x75,0xe7,0x6e,0x46,0x65,0x55, + 0xad,0xb8,0x7b,0xf0,0x6b,0xa9,0xfa,0x5e,0xbf,0x3a,0x7c,0xe4,0x08,0x94,0x6b,0x80, + 0x1f,0xfc,0x1c,0x30,0x7b,0xbf,0x19,0x55,0xe2,0xa4,0x32,0x82,0x6a,0xac,0xa9,0xad, + 0x6d,0x46,0xa7,0x95,0x7b,0x14,0xdc,0x95,0x84,0x76,0xd1,0x88,0xc5,0xcd,0x2d,0xcd, + 0x0b,0x17,0x2e,0x66,0x5f,0xf2,0x49,0x1c,0xa0,0x31,0xe5,0x15,0x14,0xfa,0x07,0x04, + 0x9d,0x39,0x1b,0x95,0x99,0xfd,0x00,0x8a,0xdc,0xff,0x5a,0x2e,0x7c,0x80,0x39,0x75, + 0x3a,0x1c,0xe6,0x18,0x52,0x44,0x68,0x4d,0xca,0x32,0xc9,0x40,0x80,0xc4,0x4b,0xb4, + 0x30,0xa9,0x68,0xf2,0xd2,0x92,0xc8,0x30,0x70,0xd9,0x2e,0x5c,0x58,0x58,0x52,0x12, + 0x7e,0xf6,0xbc,0xc0,0xdd,0xdb,0xcb,0xdb,0x1f,0x54,0x9b,0xcb,0x57,0xe3,0xb3,0x72, + 0x0a,0x5e,0xd4,0x36,0x88,0xbb,0x7b,0xdf,0xc9,0x7c,0x7d,0x78,0xfd,0xf6,0x75,0x68, + 0x58,0x18,0xc0,0x1c,0xe5,0x53,0xea,0x25,0x41,0xfa,0x4c,0x1e,0xcd,0x97,0x2d,0x1b, + 0xe4,0x5f,0xa9,0x22,0x30,0xd1,0x28,0x57,0x92,0xb2,0xeb,0x4d,0xd2,0x4b,0x4d,0x4b, + 0xf3,0xf5,0x0f,0x0a,0x0b,0x8f,0xc8,0xcc,0xce,0xad,0x7d,0xd9,0x80,0x1e,0x15,0x92, + 0x33,0xe0,0x43,0xc5,0x5e,0x8c,0x89,0x19,0x39,0x42,0x5d,0x5e,0x5d,0x11,0xae,0x48, + 0xc8,0xf0,0x61,0xaa,0x21,0xa1,0x30,0x97,0x8b,0xf4,0x0f,0x08,0x49,0x48,0x4c,0x29, + 0x7f,0x56,0xa9,0x58,0xff,0x6d,0x68,0x6c,0x98,0x36,0x6d,0xfa,0xa0,0xcf,0x7a,0x52, + 0xca,0x1b,0x37,0x6f,0xba,0x9b,0x9e,0xe1,0xe9,0x1b,0x04,0xf8,0x5b,0x52,0xf2,0xb8, + 0xbd,0x43,0xd1,0x71,0x6f,0x30,0xeb,0x37,0x7c,0xc3,0xae,0x2b,0x59,0x26,0xd9,0xff, + 0xca,0xcb,0x97,0x56,0x1d,0x5b,0x18,0x0e,0x3b,0x38,0xc4,0xdd,0xb8,0xe5,0xeb,0x17, + 0x74,0xed,0x66,0xc2,0xc3,0x47,0x4f,0x85,0x22,0x31,0xba,0x36,0x43,0x2e,0x4a,0x8a, + 0x57,0xd8,0x7d,0x49,0x5f,0x36,0xa4,0xad,0x20,0xd5,0x82,0xe0,0x85,0xae,0x74,0x31, + 0x3a,0x26,0x33,0x3b,0xe7,0x56,0x62,0x6a,0xd9,0xe3,0xf2,0xd6,0x76,0x21,0x7a,0x1f, + 0x5c,0x3e,0xfe,0x82,0xf0,0xec,0xdd,0x7f,0x80,0xbe,0xc1,0xcd,0xb4,0x85,0x9c,0x02, + 0xca,0x16,0x5f,0x9e,0xb4,0x0f,0xda,0x9d,0xd5,0xc7,0xe8,0x19,0xfe,0x52,0x86,0x17, + 0x42,0x91,0x31,0xc3,0x6b,0xa4,0x04,0xad,0x8c,0x0f,0x57,0xe9,0x6d,0x8a,0x1a,0x6d, + 0xbe,0x73,0xe4,0x04,0xcb,0x61,0x9a,0xfa,0x4a,0xc3,0xb5,0x95,0x55,0xc7,0xa8,0x6a, + 0xcf,0xd2,0x9c,0xba,0x4c,0xc7,0xc6,0x61,0xfa,0xce,0x0c,0x23,0xc7,0x16,0xb4,0xa0, + 0x8a,0xb0,0x12,0xeb,0x8f,0x58,0xc5,0x33,0xa1,0xc9,0xff,0x84,0x01,0x54,0x52,0x1c, + 0x1f,0x58,0x02,0x14,0x9b,0x8d,0x3f,0x95,0x1a,0x62,0xcd,0x17,0x19,0x0e,0x59,0xc8, + 0x65,0xb6,0x33,0xc9,0x3a,0x4c,0xb1,0x9a,0x3c,0x90,0x16,0x27,0x99,0x8d,0x59,0x45, + 0xff,0x72,0x18,0x22,0x24,0x89,0xa9,0x84,0x26,0x56,0x75,0xf1,0xbf,0x1c,0x26,0xfe, + 0x6c,0x56,0x64,0x62,0x93,0x8f,0xb6,0x28,0x17,0x1e,0x2b,0x2d,0x36,0xe6,0x5c,0xc6, + 0x20,0x37,0x0f,0xbb,0x09,0xd4,0xb2,0x0d,0x5f,0xcc,0xb2,0xbb,0xac,0x05,0x22,0x6b, + 0x81,0x10,0xcc,0x5c,0x41,0xe7,0x42,0xf7,0xc6,0x45,0x6e,0xf5,0xcb,0xdd,0x2b,0x97, + 0xf1,0x9f,0x2d,0x72,0x2e,0x5a,0xc5,0xcd,0x7d,0xde,0x20,0xfa,0xcb,0x71,0x56,0x81, + 0x49,0x4e,0x4d,0x5d,0xba,0x74,0xd9,0x86,0x8d,0x9b,0x77,0xed,0xfd,0x19,0xc6,0xc0, + 0x53,0xe1,0xe7,0xc9,0x21,0x9d,0xb2,0xc7,0x4f,0xab,0xaa,0xeb,0xea,0xea,0x9b,0xea, + 0x9b,0xda,0x60,0xe8,0xae,0xae,0x6d,0x7c,0xf2,0xac,0xb2,0xf8,0x61,0x59,0x7a,0x46, + 0xee,0xcd,0x5b,0xb7,0xa3,0x62,0x62,0x83,0x8f,0x9f,0x74,0xf7,0xf4,0xfb,0xed,0xf7, + 0x63,0xfb,0xf6,0xff,0xb4,0xf5,0x87,0xed,0xeb,0xd6,0x6f,0x5a,0xfe,0xe5,0x6a,0x9b, + 0x05,0x8b,0xc9,0x42,0xb4,0x91,0x91,0xd1,0x2c,0x83,0x59,0xd3,0xa7,0xcf,0xd0,0x9b, + 0xac,0x37,0x69,0x12,0x7a,0x29,0xf8,0xf3,0x71,0xba,0x3a,0x63,0xc7,0x8e,0x1e,0x3d, + 0x5a,0x0b,0x2b,0xc2,0x5a,0xa3,0x40,0x17,0x1e,0x45,0x56,0xa4,0x61,0xd8,0x47,0x40, + 0xac,0x3a,0x72,0xcb,0x96,0xad,0x69,0xf7,0x32,0x7d,0x7c,0x83,0x62,0xaf,0xdc,0x28, + 0x2c,0x2e,0x6b,0xef,0xe8,0x54,0xa0,0xff,0x76,0xf7,0x76,0xff,0x73,0xdb,0x76,0xf2, + 0xed,0x18,0x9d,0x69,0x1a,0x32,0x94,0x76,0x25,0xe6,0xc6,0x0f,0xd6,0x16,0xaf,0x99, + 0x33,0x66,0xa6,0xdc,0x4d,0xf3,0xf4,0xf6,0x0f,0x3b,0x7d,0x2e,0x3d,0x33,0x07,0x74, + 0x19,0xd0,0x1c,0x15,0x4c,0x9e,0x6f,0xc6,0x27,0x90,0x65,0x52,0xf2,0x90,0x04,0x9a, + 0xe2,0x2a,0xab,0x18,0x99,0x18,0x65,0xe7,0xe4,0xb8,0x0a,0xdc,0x1d,0x9d,0x5d,0x02, + 0x82,0x42,0x62,0xaf,0x5c,0xcb,0x2f,0x2a,0xad,0x6f,0x6a,0x97,0x77,0x33,0x46,0x75, + 0x4d,0xad,0xed,0x82,0x45,0x04,0x68,0x98,0xd7,0x28,0x24,0x2c,0x91,0x93,0x9b,0x0c, + 0xb7,0x24,0x50,0x89,0xf9,0x6b,0xb4,0xf6,0xe8,0x88,0x73,0x51,0x3d,0x3d,0x7d,0xe8, + 0x62,0x46,0xf9,0xd3,0x8f,0x77,0xef,0xff,0xe8,0xed,0xeb,0x83,0x49,0x48,0x56,0xce, + 0x7d,0x9d,0x31,0x3a,0x74,0x4b,0x1b,0x19,0x22,0x80,0xac,0x96,0x96,0xf6,0xfd,0xbc, + 0xfc,0xc0,0xe0,0xd0,0x93,0xe1,0x91,0x19,0x68,0xbf,0x4a,0x23,0x7e,0xcf,0x51,0xee, + 0x20,0x7f,0x21,0xea,0xa2,0xa6,0xba,0x26,0x99,0xea,0x33,0x5f,0x04,0x86,0xa2,0x9a, + 0x24,0x73,0x7e,0xba,0x6b,0x9d,0xba,0x65,0xbd,0x52,0x75,0xce,0x4e,0x4b,0x63,0xb2, + 0x8b,0x8f,0x8e,0xa4,0xa9,0x7c,0xb6,0x79,0xcb,0xe6,0xfc,0x82,0xfc,0xab,0xd7,0x6f, + 0x44,0x5e,0xbc,0x14,0x7d,0xe9,0xda,0xed,0xe4,0x94,0xfc,0x82,0x62,0xd0,0x6e,0x44, + 0x5d,0x3d,0x6f,0xdf,0x0e,0xb2,0xdf,0xb8,0xbb,0xb7,0xc7,0xd5,0xd5,0x0d,0x6a,0x89, + 0x66,0xca,0xa6,0x4c,0x38,0x67,0xaa,0x42,0x52,0xc9,0x74,0xed,0x91,0xde,0x86,0xca, + 0x2e,0x02,0x89,0x2c,0x45,0x0d,0xd2,0xea,0x8e,0xd3,0xbd,0x9d,0x94,0x1c,0x04,0x82, + 0x7e,0xfa,0x4c,0x5a,0x46,0x4e,0x4d,0x5d,0x7d,0x5f,0x5f,0xbf,0xdc,0x01,0xff,0x3f, + 0x1f,0xe2,0xe3,0x6f,0x6b,0x8d,0xd2,0x1e,0x28,0xe3,0xc7,0x2d,0x4e,0x9b,0x18,0x28, + 0x83,0xcc,0x7b,0xfa,0x78,0x45,0x46,0x45,0x03,0xfe,0xde,0xba,0x9d,0xfa,0xe4,0xe9, + 0xf3,0xae,0xee,0x6e,0x05,0x4b,0xa9,0xad,0xed,0xed,0xc6,0xc6,0x26,0x6c,0xa4,0xa0, + 0xa5,0x60,0x54,0xb9,0x7f,0x0c,0x5d,0xfd,0xd5,0x9a,0xcc,0xec,0xfb,0xa0,0x75,0x46, + 0xc7,0xc6,0xe5,0x17,0x97,0xb5,0xb6,0x89,0x14,0xe3,0xef,0xb6,0x6d,0x3b,0x68,0x25, + 0x0c,0xc1,0x3b,0xb8,0x68,0xc7,0x21,0x02,0xcf,0x4c,0x5a,0x94,0x94,0x89,0x61,0x84, + 0x41,0xd2,0x17,0x48,0xbe,0x6c,0x49,0xa6,0x4d,0xbc,0x6b,0xcf,0x9e,0x9b,0xb7,0x12, + 0xbd,0x7c,0x03,0xaf,0x5e,0xbb,0x51,0xfc,0xf0,0x49,0xa7,0xa8,0xeb,0xf5,0x1b,0xb9, + 0xdf,0x7a,0x7a,0x5f,0xf5,0xad,0x5d,0xb7,0x9e,0x2d,0x2d,0xa4,0xa2,0xc8,0x44,0x68, + 0x40,0x14,0x71,0x84,0xad,0x5b,0xb7,0x56,0x54,0x56,0x15,0x97,0x3e,0xa9,0x6f,0x6c, + 0xee,0xee,0xe9,0x53,0xa0,0xe0,0x7f,0xc0,0xc7,0xb1,0xb9,0x5c,0x1e,0x61,0x52,0x4a, + 0x3c,0x08,0x65,0x3a,0x6e,0x7c,0xd4,0x46,0x1f,0x0b,0x30,0x5b,0xbc,0xe9,0x4c,0x83, + 0xca,0x33,0xbd,0xd6,0x6f,0xd4,0xd4,0x25,0xe6,0xce,0x4d,0x26,0x18,0x32,0x4c,0x88, + 0xbe,0x06,0xb0,0xe2,0x58,0xa7,0xff,0x6d,0x8c,0x86,0xde,0x17,0x2a,0xc3,0x34,0x87, + 0xfc,0x03,0x92,0x7f,0xa6,0xfc,0x99,0xa6,0x8a,0xea,0x68,0x15,0x55,0x6d,0x65,0x95, + 0x91,0x10,0x32,0x74,0x88,0xb2,0xca,0x88,0x09,0x5a,0x73,0x7e,0x98,0xb6,0x2b,0xd3, + 0xd4,0xa5,0xc3,0x9c,0x87,0x16,0xa8,0xe7,0x70,0x19,0xed,0x0f,0x88,0x98,0x62,0x37, + 0xc0,0xab,0x29,0x97,0x71,0x0f,0xea,0x85,0x98,0x00,0xb2,0x00,0x46,0x8a,0x23,0x03, + 0xd8,0x21,0x28,0xe4,0x32,0x90,0x3d,0x47,0xa2,0x5a,0x9a,0xb9,0x30,0xf9,0x9a,0x61, + 0xdb,0x94,0xcb,0xe4,0x3e,0x1b,0xb3,0xc1,0x94,0x08,0xaf,0xfd,0x12,0x3d,0xd4,0x9c, + 0xda,0xac,0xf2,0x22,0x5c,0xe6,0x76,0x92,0x8c,0x80,0x13,0x16,0x29,0xa4,0xd8,0x9a, + 0xb9,0xe2,0xdc,0x25,0xcc,0x80,0x17,0x8c,0x31,0xc9,0x9d,0x87,0xbd,0xd8,0xc1,0x82, + 0x57,0x11,0x1b,0x70,0xcd,0x3e,0x0e,0xb1,0x70,0x15,0x59,0x80,0xcd,0x17,0x59,0x09, + 0x44,0x73,0xdd,0x84,0xf3,0xdd,0x85,0xf3,0x3d,0xb0,0xf1,0x14,0x2e,0xf6,0x6e,0x5f, + 0xe1,0x53,0xbf,0xd4,0xa3,0x76,0x85,0xdb,0xd3,0x15,0xae,0x65,0xfb,0x4e,0x14,0x37, + 0x77,0x29,0xea,0x05,0x7f,0xb9,0xa9,0xa9,0xab,0x5b,0xb7,0x61,0xe3,0xda,0xf5,0x9b, + 0x76,0xed,0xf9,0xf9,0x98,0xb3,0x2b,0x8c,0x35,0x71,0xd7,0x6f,0x65,0x64,0xe5,0x3e, + 0x7c,0xf4,0xe4,0x79,0x55,0x1d,0x20,0x6f,0x43,0x73,0x27,0x48,0x7b,0x7d,0x63,0xeb, + 0xf3,0xea,0xea,0xb2,0x27,0xcf,0x1e,0xe4,0x97,0xa4,0xde,0xcd,0x8c,0xbb,0x7e,0x1b, + 0xb4,0xaa,0x80,0xe0,0x50,0x9e,0xab,0xbb,0xc3,0x91,0xdf,0xf7,0xec,0x3d,0xf0,0xdd, + 0xd6,0x7f,0xae,0x5d,0xbf,0x71,0xf9,0x97,0x5f,0xd9,0x2c,0x58,0x04,0x10,0x3c,0x67, + 0x8e,0x19,0x40,0xb0,0x81,0x81,0xc1,0xf4,0xe9,0xd3,0xf5,0x27,0xeb,0x4f,0xd0,0x9b, + 0x34,0x7e,0xfc,0x04,0xdd,0xf1,0x13,0x91,0x22,0x3c,0x06,0x74,0x61,0xf2,0x43,0xba, + 0xb0,0xa6,0x86,0xd6,0xc8,0x11,0x23,0x41,0x1d,0x06,0xfb,0x9b,0x8d,0x1b,0xd3,0x33, + 0xb2,0x7d,0xfc,0x60,0x0e,0x1f,0x07,0xf8,0xdb,0xd6,0xa1,0x68,0xfd,0x19,0x7a,0xee, + 0x9e,0x3d,0xfb,0xd9,0x23,0x3f,0x5d,0xbc,0xa2,0x5e,0x02,0x22,0xc3,0x54,0x86,0x4d, + 0xd6,0x9f,0x02,0xf8,0xeb,0xed,0xe3,0x7b,0x3a,0xfc,0x3c,0x64,0x01,0xf3,0x8a,0xbe, + 0x3e,0x45,0x9b,0x81,0x53,0xd3,0xef,0x81,0x3e,0x4e,0x46,0x72,0xd2,0x4f,0xc1,0x31, + 0x66,0xf4,0x98,0xe8,0xd8,0xd8,0xf0,0xb3,0x11,0x30,0xeb,0x70,0x75,0xf3,0x08,0x3f, + 0x1b,0x95,0x9c,0x9a,0x01,0xca,0x4b,0xa7,0x50,0x2c,0xef,0xd3,0x2a,0x0c,0xe0,0x33, + 0x66,0xcc,0x04,0x7e,0xc8,0x92,0x1a,0xe9,0xfb,0x74,0x79,0x8d,0x70,0x0b,0x21,0x64, + 0x71,0x8f,0x98,0xbd,0xfb,0xf7,0xb7,0xb4,0xb6,0xf5,0xf7,0xbf,0x51,0x74,0xda,0xf4, + 0xff,0x3e,0x80,0x4e,0xd1,0xd1,0x29,0x6c,0xef,0xec,0x74,0xf7,0xf2,0x84,0x02,0x32, + 0xc9,0x95,0x54,0x08,0xa8,0x01,0x4d,0x7c,0x13,0x6f,0x76,0xf0,0xf1,0xd0,0xd3,0x67, + 0x2f,0x40,0x91,0x5f,0x7c,0x0a,0x7f,0xaf,0xc4,0xc5,0x69,0x6b,0x8d,0x26,0x44,0x08, + 0x05,0x30,0xc3,0x87,0x0d,0x27,0x03,0x2f,0xe2,0x56,0x99,0xb5,0x2a,0x88,0x33,0xa2, + 0x23,0x1b,0x5d,0x33,0xa4,0x05,0x24,0xad,0x80,0x02,0x07,0x4b,0xcb,0xd4,0x00,0x1e, + 0x72,0x41,0x99,0xdd,0x7f,0xe0,0xa7,0xaa,0xea,0x9a,0xdc,0xbc,0xfc,0x9c,0x9c,0xc2, + 0x82,0xe2,0x92,0xa7,0x15,0x2f,0x9a,0x5a,0xda,0x61,0x06,0x02,0x73,0x8c,0x41,0xd7, + 0x28,0x40,0x69,0xfa,0xf7,0xae,0xbd,0xaa,0xaa,0x6a,0x94,0x0d,0x3a,0x2a,0x32,0xc4, + 0xd9,0x0e,0x59,0x9e,0x95,0x98,0xac,0x99,0xb4,0x43,0x86,0x4a,0x95,0x88,0x0c,0xb9, + 0x08,0x7f,0x13,0x93,0x83,0x43,0x4e,0x9c,0x08,0x3b,0x93,0x9a,0x9e,0x05,0xf8,0xdb, + 0xdb,0xa7,0x68,0x01,0xe1,0x6e,0x7a,0x3a,0x48,0x08,0xad,0x0d,0x54,0x0f,0xca,0x1f, + 0xad,0xa3,0x12,0x2f,0x50,0x06,0x55,0x8e,0xc7,0x77,0x8d,0xbe,0x74,0x15,0xf0,0xf7, + 0xe6,0xad,0x64,0x98,0xeb,0x0a,0x45,0xdd,0x6f,0xdf,0xbd,0x93,0xb7,0x20,0xd3,0x29, + 0x12,0x5b,0x59,0x5a,0x4b,0x31,0x49,0xd5,0x61,0xe2,0x5d,0xb2,0x78,0x69,0x66,0x4e, + 0x8e,0xb7,0x5f,0x10,0xe0,0x6f,0x5e,0x71,0x69,0x4b,0xab,0x50,0x31,0xfe,0x82,0x6e, + 0x48,0xd2,0x92,0xb5,0x77,0xa9,0xe2,0x0f,0xb4,0x11,0x6b,0xb2,0x44,0x32,0xa5,0xb2, + 0x41,0x04,0x98,0xa9,0x46,0xfc,0x2f,0x01,0xcd,0x6d,0x3b,0xb7,0xdd,0x4e,0x4a,0x61, + 0xf0,0xb7,0xe4,0x09,0x3a,0x26,0xf0,0x5e,0x6e,0x2f,0x06,0x99,0xdc,0xba,0xf5,0x7b, + 0x22,0x66,0x6c,0xca,0xb4,0x15,0x68,0x3b,0x82,0xbd,0x76,0xdd,0xda,0x86,0x86,0xe6, + 0xc6,0xe6,0x36,0x71,0x77,0x8f,0x82,0xf3,0x83,0x4c,0x07,0x79,0xf7,0xd6,0xdb,0xd7, + 0x57,0x45,0x72,0xf9,0x3c,0x25,0x28,0xc5,0xb3,0xac,0x3c,0x0f,0x2a,0x0c,0x84,0x37, + 0x46,0x72,0x58,0x5d,0x03,0x6c,0x70,0xeb,0xda,0x1c,0xb0,0x12,0x30,0x2b,0xa2,0x00, + 0x34,0x00,0x3a,0xc6,0x8e,0x0d,0x13,0x17,0x1e,0x1e,0xae,0xa6,0x83,0xd4,0x67,0x65, + 0x75,0x75,0x3d,0xdb,0x49,0x4b,0x1c,0xa7,0x6c,0x0c,0x9f,0xb1,0xfd,0xea,0xe4,0xef, + 0xaf,0xe8,0xaf,0x3f,0xa1,0x63,0xb5,0x6b,0xb8,0xce,0x4c,0xac,0x4a,0x2b,0xa9,0xe9, + 0x98,0xe8,0x6f,0xb9,0x82,0x20,0x98,0x82,0x0e,0x06,0x23,0x80,0x2a,0x69,0xd5,0x6f, + 0x50,0xc3,0x1b,0x4c,0x49,0x94,0x31,0x84,0x9a,0x19,0xe6,0x10,0xa7,0x12,0x99,0xf3, + 0x30,0xae,0xf1,0xba,0xe4,0x92,0xfa,0x24,0x65,0x99,0x7f,0xe7,0x0c,0x20,0x29,0x20, + 0x66,0x97,0xa2,0xb4,0x8a,0xb2,0x90,0x4d,0x3b,0xe0,0xb5,0xe0,0x83,0x11,0x5b,0xf2, + 0x41,0xe7,0xed,0x02,0xf0,0xb5,0x76,0x17,0x2f,0xf0,0x16,0xcf,0xf7,0x16,0x2e,0xf4, + 0x11,0x2e,0xf7,0x6d,0x5f,0xe5,0x57,0xf7,0x75,0x40,0x9d,0x9d,0xfb,0xb3,0xaf,0xdd, + 0x8b,0x8e,0xdf,0xaa,0x79,0xfd,0x77,0x3d,0x7c,0x44,0x4c,0x5f,0x7f,0x9f,0xe3,0x31, + 0x97,0xd5,0x5f,0x7d,0xbd,0x63,0xc7,0xbf,0x1c,0x8f,0x71,0x02,0x82,0x42,0x2f,0xc4, + 0xde,0xb8,0x9b,0x9e,0x5d,0x54,0xf2,0xe8,0x79,0x55,0xcd,0xcb,0x86,0xa6,0xe6,0xd6, + 0x8e,0xc6,0xe6,0x76,0x0c,0xc1,0xed,0x80,0xc8,0xa5,0x8f,0x9e,0xe4,0x3e,0x28,0x4c, + 0x4a,0x49,0x03,0x08,0x8e,0x38,0x1f,0xed,0x13,0x14,0xea,0xcc,0xf3,0x3a,0xe4,0x80, + 0x20,0x18,0x69,0xc1,0x1b,0x36,0xad,0xb0,0x5b,0x63,0xbb,0x70,0xf1,0x17,0xf3,0xd0, + 0xa1,0x24,0x13,0x13,0x13,0x43,0x43,0x43,0x00,0x20,0x40,0xe1,0xc9,0x93,0x27,0x03, + 0x0a,0x03,0x04,0xa3,0xe5,0xe8,0xcf,0x3f,0x1f,0x33,0x66,0x0c,0x81,0x60,0x2d,0xad, + 0xd1,0xa3,0x46,0xa1,0x2b,0x2b,0x35,0xd5,0xb5,0x56,0xae,0x5c,0x95,0x91,0x75,0x1f, + 0xe3,0xef,0xb5,0xbc,0x82,0x87,0x90,0xb5,0x82,0x13,0x1f,0xf8,0x94,0xd0,0x91,0x81, + 0x93,0xc5,0xf8,0x72,0x0f,0xe2,0x20,0xf7,0x5e,0xa2,0x81,0x45,0x19,0x7d,0xae,0x02, + 0x78,0x9a,0x38,0x61,0x52,0xc2,0xed,0x24,0xbf,0x80,0x60,0x50,0xf0,0x53,0xd3,0xd1, + 0x03,0x6d,0x48,0xff,0x95,0x7f,0x96,0x33,0x37,0x2f,0x0f,0xe6,0x03,0x90,0x96,0x4d, + 0x1f,0x94,0xf4,0xcd,0x9b,0xbf,0xcd,0xca,0xce,0x71,0xe6,0xba,0x3a,0x71,0xf8,0x3e, + 0xfe,0x41,0x31,0xb1,0x71,0xf7,0x73,0x0b,0xf0,0xa7,0xa8,0x57,0xef,0xc8,0xf8,0xf9, + 0x31,0x62,0x02,0x82,0xa4,0xa5,0x67,0x18,0x1a,0x1a,0xa3,0x9d,0x66,0x2a,0xc3,0x08, + 0x41,0xc2,0x15,0xe9,0xc2,0x94,0x73,0x15,0xfc,0x59,0x10,0xe8,0xb7,0x77,0x08,0x19, + 0xbd,0x4f,0x01,0xf8,0xbe,0x7d,0xdb,0x25,0x16,0x43,0xeb,0x54,0x3c,0x7f,0x61,0x6b, + 0xbb,0x80,0x96,0x9a,0x6e,0x6c,0x03,0xca,0x1a,0x1a,0x1a,0xa9,0x77,0xd3,0x40,0x77, + 0x3b,0x75,0x26,0x32,0x2d,0xfd,0x7e,0x55,0x75,0xad,0xe2,0xfd,0x57,0xc9,0x77,0x52, + 0x60,0x8e,0x44,0xd2,0x02,0x35,0x60,0x98,0x54,0x1d,0x9b,0x67,0xf0,0x7e,0x54,0xc3, + 0xd8,0x8b,0x9e,0x9b,0xc4,0xc3,0x38,0x78,0x69,0x13,0xb0,0x5b,0x81,0x31,0xf8,0x5f, + 0x42,0x59,0xca,0x0b,0x05,0x3f,0xfa,0xbb,0x63,0x13,0xba,0x65,0xb0,0xad,0xa5,0xb5, + 0x43,0xd4,0xd5,0xd5,0xdb,0xdb,0xa7,0xf8,0xb4,0x54,0x6b,0x5b,0xc7,0xee,0x3d,0xfb, + 0x99,0xbd,0xf4,0x2c,0xae,0x10,0x41,0xc9,0xbe,0x3e,0x52,0x04,0x5a,0x2d,0x7f,0xde, + 0x10,0x52,0x00,0xa6,0xd7,0xe3,0xe3,0x43,0xc3,0xc2,0x4f,0x9e,0x8a,0x48,0xbd,0x07, + 0x13,0x98,0xba,0x9e,0x1e,0x45,0xa7,0x74,0x41,0x66,0x74,0x75,0xc7,0x13,0x96,0x68, + 0xa5,0xc9,0x4a,0x26,0xd8,0x23,0xd4,0x46,0xfe,0x76,0xf4,0xd8,0x95,0xb8,0x9b,0x80, + 0xbf,0xf1,0x09,0x89,0x30,0xd5,0xc5,0x1b,0xf9,0xe4,0x0e,0x14,0xbd,0xaf,0x5e,0x2f, + 0x5a,0xbc,0x44,0x96,0x32,0xdb,0x58,0x59,0xcf,0xcd,0xcd,0x2b,0x0a,0x08,0x0c,0xbe, + 0x18,0x13,0xf7,0xa0,0xa0,0xa4,0xa9,0xa5,0x45,0xf1,0xfc,0xed,0xa8,0xa3,0x93,0x9a, + 0x9a,0x9a,0x82,0x46,0x61,0x7b,0x69,0xc5,0xb2,0x73,0x27,0x72,0xc2,0xae,0x31,0x62, + 0x36,0x6d,0xfe,0x36,0x39,0x35,0xdd,0xd3,0x37,0x30,0xe6,0xf2,0x8d,0x82,0xa2,0x87, + 0x1d,0x9d,0x62,0x98,0x09,0xc8,0x3d,0x45,0xf8,0xc7,0xbb,0xbd,0xfb,0xf6,0x93,0x09, + 0xe4,0xa0,0xf9,0x12,0x2f,0x09,0xf7,0xf0,0xf4,0x86,0x59,0x37,0xba,0x53,0xfb,0x53, + 0x83,0x2a,0xba,0xd7,0xfa,0xed,0x1b,0x0f,0x0f,0x4f,0xc2,0xb3,0xbc,0x4a,0xfb,0xdf, + 0x8c,0x14,0x93,0x23,0x35,0xb4,0x0c,0xb6,0x46,0x5a,0x0b,0x28,0x3a,0x88,0xcd,0x7e, + 0xaf,0xd2,0x9e,0xb3,0x6d,0xe8,0x10,0x95,0x21,0x43,0x54,0x34,0x67,0xae,0x34,0xd8, + 0x79,0x6d,0x0e,0xa7,0x05,0x54,0x36,0x1c,0xa7,0xcb,0x9c,0x2f,0x02,0xec,0x40,0x31, + 0x9d,0x6a,0xf5,0xbe,0xf2,0x57,0x1b,0x8b,0x4e,0xee,0xab,0xaa,0x8f,0x99,0xb2,0xd6, + 0x87,0x22,0x11,0x86,0x18,0x69,0xdc,0x91,0x67,0x58,0x91,0xe5,0x1a,0x33,0x7e,0x8f, + 0x95,0x40,0x41,0x84,0x2e,0x04,0x79,0x58,0xcd,0xc4,0xca,0xa6,0x90,0x6d,0xff,0xb7, + 0x86,0x9d,0xca,0x42,0x20,0xc6,0xbc,0x75,0x61,0xc4,0xec,0x92,0x78,0x29,0xe7,0x10, + 0x2e,0xc4,0xb5,0x01,0x75,0xc2,0x60,0x2e,0x8e,0x89,0xaa,0xc8,0x4a,0x80,0x40,0xd6, + 0x52,0x80,0x34,0x62,0x88,0x36,0x17,0xa0,0xd6,0x0d,0x02,0x85,0xf3,0xdc,0x85,0xa0, + 0xf6,0xda,0x7a,0x74,0xcd,0xf7,0x12,0xda,0x7a,0x75,0xd9,0x00,0xf2,0xfa,0x0a,0x97, + 0xf9,0x09,0x97,0x07,0x08,0xed,0x02,0x85,0x1b,0x83,0xeb,0xd7,0xfb,0xd7,0x6c,0xf0, + 0x7b,0xbe,0x25,0xf0,0x51,0xde,0x33,0xe1,0xdf,0xf9,0x69,0x33,0x22,0xa8,0x97,0xaf, + 0xc4,0xad,0x5e,0xb3,0x1e,0x14,0xd8,0xc3,0x0e,0x8e,0xde,0xbe,0xc1,0x51,0xd1,0x97, + 0x93,0xee,0xa4,0xe7,0x15,0xa2,0x6b,0xf7,0x6a,0x5f,0x36,0xb7,0xb4,0x09,0x9b,0x5b, + 0x3b,0x9b,0x5a,0x5a,0x01,0x85,0x41,0x6d,0xac,0xa8,0xac,0x2d,0x2e,0x7e,0x9c,0x9d, + 0xf3,0x20,0xf1,0x4e,0x6a,0xec,0xd5,0x6b,0xe1,0x11,0x17,0xbc,0xfd,0x43,0x5c,0x78, + 0xee,0xf6,0x87,0x7e,0xdb,0xbd,0xf7,0xc0,0x96,0xef,0xb7,0xad,0xdf,0xb0,0x79,0xe5, + 0xca,0xd5,0x0b,0x17,0x2f,0x9d,0x67,0x63,0x6b,0x69,0x65,0x6d,0x6a,0x3a,0xc7,0xd8, + 0xc8,0x84,0x6c,0x8a,0x9e,0x3a,0x6d,0x9a,0xfe,0xe4,0x29,0x13,0xf5,0x26,0xea,0x8e, + 0x1f,0x4f,0x3e,0x0a,0x8f,0x05,0x20,0xd6,0xd1,0xd1,0xc6,0x3f,0x2d,0x2d,0xad,0x2f, + 0xed,0xec,0x32,0xb3,0xb3,0x7d,0x02,0x4e,0xc4,0xc4,0x5e,0xc9,0x2f,0x2c,0xc3,0xf8, + 0x2b,0xf7,0x94,0x2e,0xcc,0x6f,0x5d,0x78,0xae,0x74,0x1f,0x17,0x39,0xd9,0x44,0x6c, + 0x12,0xc2,0xb6,0x01,0x7f,0xaf,0x5e,0xbf,0x1e,0x18,0x72,0x32,0xf4,0x74,0x04,0xe0, + 0x6f,0x75,0x4d,0x5d,0x4f,0x6f,0xaf,0x82,0xd1,0xa9,0xa4,0xb4,0x54,0x5b,0x4b,0x9b, + 0x26,0xa7,0x06,0x66,0x11,0x89,0x49,0x49,0xa7,0xc3,0x41,0x05,0x76,0xe6,0xbb,0x79, + 0x07,0x87,0x46,0xdc,0x44,0xd7,0x27,0x96,0x01,0x70,0xf4,0xf6,0xf5,0x0d,0xca,0x2a, + 0xd4,0x70,0x6a,0x5a,0xfa,0x9a,0x35,0xeb,0x60,0xb6,0xc1,0xa6,0xa6,0x36,0x7c,0xc0, + 0x3d,0x42,0x6d,0xc4,0xb8,0x71,0xba,0x3f,0xfd,0x74,0xf0,0x45,0x75,0xcd,0x1f,0xe8, + 0xac,0x91,0xa2,0x9d,0x33,0x7f,0x7c,0x78,0xdf,0xf7,0xaa,0xbf,0xa1,0xb1,0xb9,0xae, + 0xbe,0x39,0x2a,0xe6,0x22,0x24,0x94,0x62,0x92,0xb0,0x0d,0xf8,0x9b,0x9c,0x92,0x7a, + 0x2a,0xfc,0x1c,0xe0,0x6f,0x6a,0x5a,0x26,0xe0,0x6f,0x5f,0x7f,0xbf,0x82,0xf3,0x1a, + 0xd9,0x59,0xb9,0x93,0xf5,0xa7,0x50,0x52,0xe4,0x06,0x6f,0xd9,0x9a,0x94,0xcd,0x88, + 0x89,0xfc,0xf1,0xbf,0xe0,0x95,0x4d,0x2b,0x65,0xd3,0x38,0x60,0x74,0x75,0x75,0x43, + 0x42,0xc3,0x60,0x52,0xf1,0x0a,0x34,0xff,0x37,0xef,0x60,0x80,0xfd,0xe4,0x63,0x43, + 0x2f,0x1b,0xea,0xed,0xec,0xec,0xc8,0xd1,0x72,0x76,0x65,0xc2,0xc4,0x89,0x4d,0xf9, + 0x7f,0x30,0x24,0xad,0x8e,0xce,0xd8,0x98,0x2b,0x57,0xc3,0xc2,0x23,0x10,0xfe,0xa6, + 0x65,0x31,0x0f,0x72,0xc9,0xd7,0x7f,0x8b,0x4b,0x4a,0xf5,0xf5,0x27,0xcb,0xd6,0x15, + 0xbb,0x26,0xc9,0x5f,0x10,0x72,0xc8,0xe1,0xf0,0x8d,0xf8,0x24,0xc0,0x5f,0xb4,0x49, + 0xf8,0x51,0x39,0x68,0xb8,0x52,0xef,0x30,0x4a,0x89,0xba,0xdd,0xca,0xd5,0x83,0x56, + 0x23,0xa5,0x69,0x66,0x6e,0x51,0x58,0x5c,0x12,0x10,0x14,0x82,0xf0,0x37,0x1f,0xe1, + 0xaf,0xe2,0xed,0x76,0x1e,0x9e,0x5e,0x1a,0xea,0xa3,0x68,0x2b,0x48,0x35,0x87,0x62, + 0x2f,0x2d,0x05,0x3b,0x02,0xfd,0x6b,0xfd,0x86,0x0d,0xf7,0x32,0x73,0x7c,0xfc,0x82, + 0x2f,0x5d,0xbe,0x5e,0x58,0x5c,0x0a,0xfa,0x6f,0xbf,0xfc,0x83,0x6f,0xd0,0xce,0x0e, + 0x47,0x8e,0x2a,0xc8,0x17,0xa0,0x13,0x6c,0x4d,0x8d,0x51,0xf3,0x6d,0x16,0x54,0xd7, + 0xbe,0x44,0xbd,0xe3,0xd3,0xaf,0x39,0x7c,0x78,0xd5,0xff,0xa6,0xaf,0xff,0xd5,0x61, + 0x87,0x23,0xe4,0xd8,0xa3,0xea,0x30,0x55,0x59,0x3e,0xff,0x5b,0x79,0xf8,0x48,0xc0, + 0xd4,0x06,0x44,0x4e,0x5b,0xcf,0x74,0x8e,0x7d,0xbe,0x25,0xc6,0x11,0x84,0x71,0x9c, + 0xc6,0x89,0xcb,0x9c,0x94,0x94,0xd4,0x94,0x3e,0x53,0x1f,0x3b,0x77,0xa7,0x89,0x43, + 0x85,0x99,0x73,0xbd,0xb9,0x73,0x83,0xb9,0x4b,0xab,0xb5,0xfb,0x80,0xee,0x66,0xc1, + 0x6b,0x83,0x40,0x0b,0xa7,0x6a,0x83,0x9d,0x09,0xea,0x93,0x6c,0x86,0xfc,0x43,0x49, + 0x65,0xe4,0x78,0xc3,0xdd,0x77,0x2d,0xf9,0x9d,0x16,0x98,0x0e,0x31,0x08,0x95,0xf8, + 0x62,0x2b,0x01,0xb2,0x01,0xbe,0x2d,0x90,0x1b,0x81,0x1a,0x06,0x26,0xb1,0xa5,0x40, + 0x64,0x85,0x10,0x4d,0x64,0x21,0xe8,0xc2,0x91,0x85,0xd4,0x26,0x9f,0x44,0x2d,0xf8, + 0x04,0xf4,0x21,0x44,0x84,0x09,0xa2,0x05,0x5b,0x4b,0xb4,0x72,0x2b,0x94,0xa4,0x15, + 0x12,0xca,0x00,0x6d,0x24,0x32,0xb5,0x09,0x29,0x4b,0x1c,0x87,0x24,0x81,0x7c,0x11, + 0x27,0x78,0x89,0x18,0x51,0x73,0x13,0x59,0xb9,0x21,0x00,0x25,0x69,0xe1,0xdf,0xb9, + 0x6e,0x22,0x36,0x11,0x88,0x69,0x29,0x10,0x93,0x7c,0x2d,0xb1,0x4d,0x81,0x1e,0x7d, + 0xb4,0x45,0xa9,0x50,0x38,0x72,0x08,0xba,0x21,0xe4,0x0b,0xf7,0x2e,0x4b,0x3e,0x01, + 0x59,0x94,0x0a,0x58,0xb5,0x46,0x7c,0x22,0x07,0x62,0x1b,0x3b,0xe6,0x7b,0x8a,0xe6, + 0xb9,0x8b,0xe6,0x7b,0x0a,0x6d,0x3c,0x45,0x36,0xde,0xff,0xcf,0xdc,0x75,0xc7,0x45, + 0x75,0x7c,0xfb,0x3f,0xde,0x4b,0xf2,0xcb,0xcf,0x42,0xef,0xbd,0x59,0x7e,0x1a,0x63, + 0x07,0x96,0xb6,0x54,0x15,0x51,0xec,0x85,0x98,0xe8,0x4b,0x4c,0xd1,0xa8,0x3f,0x4d, + 0x62,0x30,0x1a,0x4b,0x50,0xea,0x02,0x16,0xea,0xd2,0x51,0xa9,0x22,0x1a,0x0b,0x6a, + 0x54,0x7a,0x13,0x3b,0x88,0x74,0x11,0xa4,0xed,0x72,0xb7,0x01,0x2a,0x3f,0xd0,0xcf, + 0xe7,0x9d,0x33,0xb3,0xbb,0x20,0xca,0xa6,0x99,0xf7,0xb2,0x9f,0xc3,0x30,0x33,0xf7, + 0xdc,0x33,0x67,0xce,0xcc,0x9d,0xef,0x9c,0x7b,0xe7,0xce,0x15,0xb0,0x39,0x02,0x74, + 0x7b,0x43,0x05,0x0b,0x8e,0x31,0x4b,0xc2,0xbb,0x97,0x87,0xf3,0x57,0x47,0xb4,0xaf, + 0x0d,0x6f,0x5e,0x1b,0xfa,0x60,0x5b,0x5c,0x4d,0x97,0x48,0xd1,0x1c,0xfe,0x6f,0x42, + 0x0f,0x6b,0x6b,0x57,0xae,0x5a,0xbd,0x72,0xb5,0xd7,0xbf,0xb7,0x7f,0xeb,0xe3,0x17, + 0x1c,0x97,0x78,0xf2,0xe7,0x0b,0x39,0x45,0x25,0xe5,0x55,0xd5,0x35,0x0d,0x4d,0x2d, + 0x6d,0x1d,0x4c,0x17,0x4f,0x00,0x17,0x51,0x17,0x9f,0x01,0x08,0x6e,0x6a,0x6e,0xad, + 0xae,0x6d,0xa8,0xb8,0x5d,0x59,0x50,0x54,0x72,0x3e,0xe7,0x0a,0x38,0x80,0x31,0xf1, + 0x89,0x9c,0xd0,0xb0,0x7d,0x07,0x0e,0x7d,0xf3,0x9d,0x37,0xf5,0x82,0x41,0x94,0xfb, + 0xc2,0x45,0xce,0xae,0xf3,0x10,0x82,0xad,0xac,0x67,0xcf,0x99,0x4b,0x1d,0xe1,0xc9, + 0x93,0x09,0x0a,0x5b,0x4c,0x30,0x33,0x33,0x37,0x36,0x31,0x31,0x30,0x34,0x24,0xab, + 0xa3,0x75,0x75,0x74,0xf4,0x74,0x74,0x70,0xd7,0x68,0x67,0x57,0xd7,0xe2,0xb2,0xb2, + 0xd0,0xc3,0x47,0x4f,0xa6,0x66,0x96,0x96,0xdf,0x7a,0xd2,0xde,0xf1,0x6c,0xf4,0x57, + 0x6f,0xf0,0x2d,0xa1,0xd0,0x23,0x4a,0xe3,0x94,0x95,0x95,0x94,0xc9,0x2e,0x97,0x4a, + 0x70,0x5d,0xd0,0x4d,0xa7,0x61,0x4c,0x7e,0x25,0x1c,0x3b,0xde,0xd0,0xd0,0x88,0x6c, + 0x8b,0x97,0xc0,0x8d,0x49,0xba,0x72,0x2d,0xbf,0xa1,0xe9,0x11,0x6e,0xba,0x3b,0xfa, + 0x08,0xdf,0xd0,0xd8,0x08,0x5a,0x29,0x29,0xe1,0x52,0x6d,0xf8,0x29,0xa1,0x18,0xfc, + 0xa9,0xaa,0xa8,0x7e,0xb5,0x79,0x4b,0x49,0x59,0xf9,0xee,0x1f,0xf7,0xed,0xde,0x7b, + 0x20,0x20,0xe8,0x48,0x42,0xf2,0x89,0x9c,0xcb,0xb9,0x95,0xd5,0x75,0x5d,0x3c,0xa6, + 0xef,0x69,0xdf,0x68,0xb3,0x85,0xf6,0xce,0x8e,0x23,0x47,0x8e,0x81,0xaf,0xaa,0xa3, + 0xad,0x83,0xd2,0x88,0xce,0x28,0x5c,0x49,0x19,0x8c,0xb0,0xc0,0x7d,0x21,0x4c,0x39, + 0x24,0x3d,0xf8,0xcd,0x1a,0xc5,0xb8,0x33,0x30,0xf0,0xa2,0xa7,0xf7,0x59,0x27,0x8f, + 0x5f,0x5b,0xdf,0xf8,0xa4,0xbd,0x1d,0xec,0xac,0xac,0xa4,0x82,0x0f,0xd0,0x49,0xc5, + 0xc1,0x02,0x68,0x84,0xf1,0x28,0x19,0x86,0xac,0xec,0x73,0xe7,0x13,0x12,0x93,0x62, + 0xe2,0x8e,0x5f,0xfe,0x25,0x1f,0xe0,0x43,0xd2,0xd3,0xa7,0xe0,0x21,0x63,0xc5,0xad, + 0x9b,0x93,0x27,0x4d,0xa1,0x46,0x03,0x0d,0xe5,0x96,0x04,0x23,0x00,0x94,0x4b,0x2d, + 0x49,0x24,0xcb,0x6d,0x4b,0x92,0x2a,0xb4,0x50,0x30,0x97,0x95,0xa5,0x95,0xad,0x8d, + 0xad,0x94,0x6c,0xed,0x90,0x48,0xc4,0x86,0x65,0x63,0x67,0x67,0xc7,0xb2,0x86,0x04, + 0x84,0x2c,0x88,0x43,0x8e,0x94,0x81,0xf2,0x10,0xb6,0x65,0x2b,0x56,0x40,0xeb,0xff, + 0xae,0xae,0x7b,0xf7,0xfe,0x7d,0x37,0xb7,0x79,0x44,0x25,0xd4,0x41,0x69,0x1c,0x74, + 0x00,0xac,0xbe,0x12,0x31,0x2c,0x59,0x57,0x30,0x9e,0x1a,0x87,0xd6,0x08,0x43,0x5c, + 0xf6,0x47,0xac,0x44,0x3b,0xcc,0x58,0x64,0x96,0xb2,0xc9,0x98,0xb1,0xd6,0xe3,0x94, + 0x75,0xb4,0x74,0x13,0x92,0x8f,0xc7,0x25,0x25,0x47,0x45,0xc7,0x42,0x9f,0xa9,0xa9, + 0x6f,0x22,0x6f,0xe9,0x2a,0xba,0x8e,0x26,0x4d,0x9a,0x4c,0xbf,0xbf,0x49,0x3a,0x8d, + 0xb4,0xcf,0xd0,0x72,0xa9,0x25,0xa9,0xad,0x20,0xb9,0x79,0xcb,0xe6,0xf3,0x97,0x2e, + 0x03,0x5c,0x66,0x9f,0xbd,0x70,0xe7,0xfe,0x03,0x3e,0xc3,0x28,0x78,0x9a,0x09,0x9e, + 0xec,0xea,0x35,0x5e,0x64,0xa5,0x84,0x8a,0x12,0xd9,0xce,0x46,0xd6,0xb1,0x87,0xaa, + 0x30,0x75,0xea,0xb4,0x9b,0xb7,0xef,0x1d,0x0e,0x8b,0x4e,0x4e,0x49,0x2f,0x2d,0xbf, + 0x89,0xf8,0xab,0x70,0x79,0x52,0x5a,0x46,0x96,0xab,0xeb,0x3c,0x67,0x17,0x57,0x24, + 0x67,0x29,0x39,0x39,0xbb,0x38,0x39,0x21,0x8d,0x96,0xa4,0xfc,0xe6,0x16,0x13,0xc0, + 0xc6,0xf8,0x52,0xbf,0x92,0xf4,0xa2,0xa3,0x7d,0x83,0xd6,0xce,0x7d,0xa1,0xc7,0xb5, + 0xbc,0xfc,0xa0,0x50,0xa9,0xff,0xdb,0xd9,0x85,0xb3,0x68,0x05,0x8d,0x18,0xc5,0x8d, + 0x53,0x54,0xae,0x8b,0xab,0xc7,0xa2,0x25,0x3e,0x3e,0x07,0xab,0x6b,0x6a,0x7e,0x63, + 0xaf,0xe8,0xeb,0x1f,0x10,0x89,0x7b,0xba,0x19,0xa1,0xd7,0x47,0xeb,0xd0,0x38,0xe3, + 0x95,0xe5,0x44,0x4c,0xf7,0x6a,0xeb,0x8f,0x7b,0xb5,0xf5,0x49,0x8e,0xb4,0xab,0x8c, + 0xc5,0xae,0x82,0xef,0x6b,0x28,0x93,0xeb,0x6b,0xac,0xb4,0x82,0x23,0xba,0x8a,0x91, + 0x95,0x97,0xd5,0xfe,0x16,0x5b,0x3f,0x04,0x2c,0x96,0xaf,0x68,0xf2,0x27,0x99,0x63, + 0x94,0xf5,0xde,0x7d,0xe7,0x5d,0x5d,0xd6,0x57,0x73,0xf7,0x35,0xcd,0xd8,0x59,0xa5, + 0x63,0xf9,0x3f,0xda,0x53,0x16,0x4f,0x58,0x99,0x08,0x68,0xc2,0xf2,0x03,0x42,0xbc, + 0x9b,0xe8,0x75,0x5c,0x73,0xea,0x52,0xf5,0xa9,0x9e,0x13,0xbd,0x12,0x67,0x6c,0x2f, + 0x1b,0x6f,0x30,0x1b,0xd7,0x71,0x59,0xb8,0xce,0xf4,0x7e,0xc8,0x22,0x70,0x63,0x83, + 0xee,0x9e,0x08,0x42,0x16,0x71,0xfa,0x58,0xc4,0xfb,0xa3,0x21,0x02,0x13,0x09,0x31, + 0x49,0xf0,0xcb,0xc6,0x1f,0x99,0x59,0x7e,0x02,0x2b,0x3f,0x00,0x62,0x01,0xcb,0x57, + 0x68,0xe5,0x2b,0x04,0x34,0x04,0x44,0xb3,0xf6,0x43,0xe8,0x24,0x0c,0x00,0x61,0x90, + 0x04,0x06,0x31,0xe4,0xb3,0xfc,0xe1,0x28,0x38,0x95,0xc8,0x03,0x87,0xac,0xfc,0x44, + 0x24,0x29,0xa2,0xa2,0x6c,0xfc,0x01,0x1f,0x85,0x18,0x1e,0x82,0x10,0x94,0x11,0xd1, + 0x52,0xec,0xfc,0x45,0x96,0xbe,0x88,0xbc,0x2c,0x7f,0xa1,0x15,0xde,0xfb,0x85,0x4c, + 0x94,0x09,0x49,0xd9,0x89,0xc8,0xcc,0xf2,0x47,0xb5,0xb1,0x22,0x44,0x7f,0x99,0x28, + 0x54,0x18,0xe7,0x06,0x58,0x10,0x92,0x25,0x32,0x88,0x48,0xe9,0x0c,0x09,0xe5,0xa2, + 0x04,0x20,0xd6,0x06,0x4a,0x24,0x55,0xb0,0xf5,0x47,0xa3,0xe1,0x13,0x5e,0x3f,0x2c, + 0x97,0x15,0x20,0x72,0x08,0xc4,0x1b,0xce,0x8e,0x1c,0x91,0x53,0x08,0x33,0xff,0xa8, + 0x68,0x61,0xb8,0xc8,0x33,0x8a,0x59,0x11,0xdd,0xed,0xc5,0xe5,0x7f,0xc4,0xed,0x5a, + 0x1f,0xdd,0xf8,0x71,0x44,0x5d,0x64,0xce,0xe3,0xdf,0xf5,0xc1,0xd0,0xff,0x2f,0x7a, + 0xd6,0xff,0xfc,0x9b,0x6f,0x77,0x2e,0xf2,0x5c,0xf6,0xe5,0x57,0x5f,0xef,0xd9,0xe7, + 0x13,0x1e,0x15,0x9b,0x95,0x7d,0xfe,0x5a,0x7e,0xc9,0x9d,0xfb,0x0f,0xeb,0x1b,0x1f, + 0x03,0xe6,0xf2,0xba,0x85,0x3c,0xbe,0xb0,0x9b,0x11,0x75,0xf2,0x98,0x96,0x27,0xbc, + 0x86,0xa6,0xd6,0x07,0x0f,0x1b,0x6f,0x54,0xdc,0x2b,0x28,0x2a,0x3d,0x7f,0xf1,0x0a, + 0x5c,0xc8,0x31,0xf1,0xc9,0x30,0xdd,0xdd,0xff,0x93,0xff,0xce,0xef,0xf7,0x6c,0xda, + 0xbc,0x75,0xfd,0x86,0x4f,0x57,0xac,0xf2,0x5a,0xe4,0xb9,0xdc,0xd5,0x6d,0x81,0x83, + 0xa3,0x13,0xcb,0xd6,0x6e,0xce,0x9c,0xb9,0x33,0x67,0xce,0x9a,0x36,0x6d,0x1a,0xb9, + 0x1d,0x8d,0xdb,0x64,0x01,0xd1,0x77,0x94,0x4c,0x4c,0x4d,0xf4,0x0c,0xf5,0xe9,0x7e, + 0x1d,0xf6,0x6c,0xc7,0x82,0xe2,0x92,0xc3,0x61,0x11,0x29,0xa9,0x99,0x65,0x37,0x6e, + 0x3d,0x69,0xeb,0x7c,0x3a,0xfa,0x4d,0x48,0x80,0x92,0x18,0x6e,0x2c,0xae,0xe3,0x52, + 0x51,0x53,0x53,0x81,0x50,0x15,0x08,0x21,0x52,0x59,0x0d,0xf0,0x42,0x4d,0x55,0x8d, + 0x12,0x59,0xe5,0xa5,0x02,0xf8,0x7b,0x22,0x25,0x35,0x36,0x3e,0x99,0x1b,0x93,0x78, + 0xf9,0x97,0x3c,0x70,0x06,0x45,0x62,0x45,0x9b,0xde,0xb7,0xb6,0xb5,0x99,0x9a,0x98, + 0xa9,0x2a,0xe3,0xe7,0x14,0x69,0x08,0x43,0x9f,0x9a,0x1a,0x8a,0xfa,0xd7,0xbf,0xa6, + 0x64,0x9f,0x39,0x9b,0x90,0x9c,0xbc,0x7b,0xef,0xfe,0x03,0x3e,0x01,0xa1,0x47,0xc3, + 0x8f,0xa7,0x64,0x5e,0xcf,0x2f,0x82,0xd9,0x0a,0xaf,0x5b,0xd0,0xd7,0x27,0x7d,0xc6, + 0xfa,0xba,0xf0,0xfe,0x81,0xfe,0xc7,0x2d,0xad,0x17,0x72,0x2e,0xed,0xd9,0xb3,0x6f, + 0xc3,0x86,0x8d,0xab,0x57,0xaf,0xfd,0xf4,0xb3,0xcf,0x0f,0xfc,0x74,0xe8,0xea,0xf5, + 0xfc,0x4e,0x5e,0x97,0xe2,0x8f,0x23,0xc8,0xaa,0x0c,0x9e,0x6f,0x1f,0x8f,0xcf,0x54, + 0x3f,0xac,0xaf,0x6f,0x6c,0x4a,0xcd,0xc8,0xd4,0xd2,0xd2,0xa2,0x15,0xc4,0x9a,0xaa, + 0x60,0x04,0xb4,0x45,0x55,0x55,0xd5,0xd4,0xd5,0xd5,0x53,0xd3,0x33,0x92,0x4f,0xa4, + 0x45,0xc7,0x26,0x40,0x95,0x6b,0xea,0x1e,0xe1,0x26,0x4b,0xa3,0x57,0x19,0xb0,0x6c, + 0xfa,0xf4,0x19,0x70,0x3a,0x08,0x54,0x55,0x51,0x57,0x51,0x52,0x03,0x22,0x49,0xa4, + 0xa1,0x24,0x9a,0x1a,0x19,0x80,0x8d,0x3e,0xbe,0x47,0x66,0x65,0x15,0x0f,0x8f,0x45, + 0xf7,0x2b,0x2b,0x8b,0x4b,0x4b,0xef,0xdc,0xbd,0x57,0x53,0x5b,0xf7,0xb8,0xa5,0xa5, + 0xb3,0x8b,0xd7,0xde,0xd1,0xd9,0xd1,0xc1,0xe3,0xf1,0xf9,0x40,0x5d,0x3c,0x7e,0x57, + 0x17,0x0f,0x68,0x44,0x12,0x03,0x3e,0x84,0x7c,0xe0,0x97,0xf4,0xf6,0xfc,0xae,0xae, + 0x0b,0xa6,0x0e,0x8f,0x88,0x52,0x53,0xd5,0x50,0xc5,0x86,0x7e,0x45,0x67,0x6c,0x7d, + 0xa2,0x2a,0x28,0x49,0x7a,0x82,0xb4,0x9f,0x90,0xa4,0x3a,0xd5,0x5c,0x8d,0x92,0xea, + 0xeb,0xcc,0x50,0x41,0x55,0x5d,0x1d,0xdd,0x98,0xb8,0x78,0x30,0x60,0x64,0x74,0xfc, + 0xa5,0x5f,0xf0,0x2d,0x5d,0xb1,0x58,0xa2,0xe0,0xce,0xe7,0xa3,0xe6,0x96,0x19,0x33, + 0x66,0xbd,0xd1,0x74,0xf2,0x38,0x12,0x51,0x66,0xfd,0x86,0xcf,0xae,0x5c,0xcb,0x3d, + 0x7c,0x24,0x1c,0xbf,0x00,0x75,0xa7,0x0a,0x5f,0xb5,0x1b,0x1d,0xa4,0x00,0x7f,0x37, + 0x6e,0xfc,0x02,0xcd,0xfe,0x6a,0x73,0x60,0xb7,0x1c,0xaf,0xa2,0x46,0xda,0x02,0xa0, + 0xbf,0xfc,0xe6,0xad,0x63,0x51,0x71,0xc7,0x53,0x32,0x0a,0x4b,0x6e,0xb6,0xb4,0xfe, + 0xca,0xeb,0xde,0x4f,0x9f,0x3f,0xed,0x16,0x30,0xfc,0x6e,0x06,0xa0,0x1f,0x42,0x88, + 0xff,0x16,0xe2,0xe1,0x92,0x03,0xc6,0xe7,0xe0,0x41,0x0d,0x0d,0x4d,0x15,0x25,0x55, + 0x54,0x49,0x75,0x64,0x7d,0x5d,0xdc,0xdc,0xf2,0x0a,0x0a,0x43,0x8f,0x84,0xa5,0xa6, + 0x67,0x97,0x94,0xdd,0x84,0xb9,0xe2,0xb3,0x67,0x8a,0xf0,0x17,0x1c,0x55,0x54,0x80, + 0x19,0xb5,0x50,0xa1,0x58,0xa4,0xf8,0x59,0xf6,0xb0,0xfe,0x80,0xc3,0x82,0xb8,0xa7, + 0xb7,0xad,0xa3,0xb3,0xb6,0xbe,0xde,0xc6,0xc6,0x1e,0x86,0x02,0xd2,0x51,0xd5,0xe4, + 0xd7,0xf2,0x70,0x7a,0x43,0xeb,0xab,0xd1,0x4e,0x42,0xe2,0x43,0xbd,0x45,0x4d,0xd6, + 0x85,0xb0,0xab,0x03,0x0b,0xed,0xfc,0x78,0x95,0xa9,0x6a,0x4d,0xfd,0x24,0xde,0xfa, + 0x10,0x63,0x1f,0x80,0x58,0x69,0xf9,0x53,0xa7,0x8a,0x85,0x13,0x38,0xb3,0xaa,0x16, + 0x8e,0x33,0xbc,0x1f,0xda,0x04,0x30,0x33,0xb6,0x17,0x8f,0x51,0x37,0x03,0x6c,0x35, + 0x72,0xdd,0x05,0x5e,0x1b,0x81,0x27,0xc1,0xdc,0x5d,0x55,0xca,0x46,0xb3,0x20,0x53, + 0x49,0x7b,0xea,0xb4,0xad,0xa5,0x90,0x39,0xf1,0xe3,0x8c,0xf7,0x95,0xf5,0xde,0x7b, + 0xef,0x9f,0x26,0x8b,0x83,0x6d,0x08,0x48,0xd9,0x12,0x4e,0x40,0x34,0x3c,0xcb,0x8f, + 0x26,0x65,0x0b,0x8d,0x46,0x10,0xb9,0x1f,0xcb,0x42,0xcc,0x82,0xa4,0x40,0xba,0x1e, + 0x49,0x1a,0x0a,0xe8,0x89,0x04,0x28,0x09,0x0a,0xcb,0x8e,0x02,0xc6,0x59,0xfb,0x8b, + 0xc8,0x51,0x8a,0xb0,0x94,0x13,0x4f,0xa7,0x21,0x3d,0xd7,0x16,0x01,0x54,0xc8,0x22, + 0x71,0x8a,0xcb,0x38,0x25,0x00,0xec,0xf6,0x85,0x1c,0x11,0x99,0x0f,0x88,0x48,0x59, + 0x00,0xfd,0x22,0x02,0x94,0x90,0x2f,0x40,0x1c,0x0f,0x10,0xd0,0x43,0x36,0xa8,0x12, + 0xc0,0x28,0xb8,0xde,0x42,0xc4,0x65,0xbf,0x21,0xb5,0x59,0x44,0x6d,0x79,0x45,0xa4, + 0xba,0xc9,0x72,0xac,0x65,0x55,0x00,0x7d,0x40,0x55,0x74,0x78,0x03,0x05,0x0e,0x41, + 0x22,0x7b,0x8e,0xc0,0x25,0x58,0xc0,0x0e,0x66,0x5c,0x42,0x44,0xee,0x61,0x02,0x8f, + 0x08,0xc1,0x32,0xae,0x78,0x65,0xac,0x60,0x5d,0x3c,0xb3,0x21,0x9e,0xb7,0x31,0xa9, + 0x73,0x63,0x5c,0xeb,0x67,0x31,0x75,0xb9,0x55,0xfc,0xb7,0x8e,0x95,0x7f,0x11,0xc5, + 0x27,0x26,0x2f,0xf4,0x58,0xb4,0x7e,0xc3,0xc6,0xef,0xbd,0xf7,0xc0,0x85,0x93,0x92, + 0x76,0xfa,0xca,0xd5,0xbc,0xf2,0x9b,0xb7,0xc1,0xc9,0x7a,0xd4,0x0a,0xc3,0x23,0xc3, + 0x08,0x44,0x78,0x81,0x30,0x22,0x88,0xb7,0x3c,0x69,0x07,0x08,0xbe,0x57,0x59,0x45, + 0xb6,0x86,0x2e,0x39,0x7b,0xfe,0x22,0x5c,0x68,0xdc,0xb8,0xf8,0x90,0xc3,0xe1,0x07, + 0x0e,0x06,0x7c,0xe7,0xfd,0xc3,0x96,0xad,0x3b,0x00,0x5f,0xd6,0xac,0xfd,0xc8,0x73, + 0xc9,0xca,0x79,0xf3,0xdd,0x1d,0x9d,0xdd,0xc0,0xf5,0xb1,0xb4,0x62,0xcd,0x99,0x6d, + 0x09,0x23,0x3c,0xa0,0xf0,0x94,0x29,0x53,0xc0,0x17,0x36,0x37,0x9f,0x68,0x66,0x86, + 0x28,0x6c,0x6c,0x66,0x62,0x64,0x6c,0x0c,0x10,0x69,0x67,0xcf,0xce,0x2d,0x28,0x09, + 0x8b,0xe4,0x02,0xa2,0x95,0x94,0x57,0xb4,0xb6,0xe1,0x5b,0x42,0xa3,0xbe,0xfd,0xfa, + 0x62,0xf0,0xc4,0x89,0x54,0x5c,0x4a,0x4d,0xf6,0xf7,0xd0,0xc0,0xb7,0x9b,0x74,0xe4, + 0x49,0xf2,0x6f,0x28,0x04,0x5f,0x3b,0x36,0x21,0x3e,0xe9,0xc4,0xc9,0xe8,0x98,0xc4, + 0x4b,0x57,0xae,0xd5,0xa1,0x2f,0xa3,0x68,0x83,0x7a,0xf0,0xf7,0x01,0x67,0xd5,0x65, + 0x3f,0xdc,0x3f,0x44,0x4d,0x2a,0x19,0xfc,0xf4,0xe5,0x2b,0x57,0x55,0xdc,0xbd,0x13, + 0x14,0x12,0xba,0x77,0xbf,0x8f,0x1f,0x7e,0xf4,0x9c,0x9b,0x9a,0x9e,0x95,0x57,0x50, + 0x5a,0x53,0xd7,0x04,0x5e,0x70,0x2f,0xf1,0x82,0x15,0x4c,0xbd,0x06,0x06,0x07,0x7a, + 0xfb,0x7a,0x45,0x12,0x31,0x72,0xfe,0xb6,0x0f,0xcb,0xbe,0xc0,0x6f,0xab,0x0d,0x02, + 0xb8,0x03,0x48,0xd5,0xd4,0x35,0xde,0xbc,0x5d,0x75,0xbf,0xea,0xc1,0x22,0x4f,0xcf, + 0xe1,0xf5,0x55,0x57,0xa3,0x21,0x4d,0x42,0xa8,0x13,0x9b,0x90,0x94,0x96,0x9e,0x15, + 0x13,0x0b,0x53,0x8e,0x5c,0x68,0x4a,0x89,0xa4,0x47,0x41,0x71,0x35,0xb5,0xf5,0x56, + 0x56,0x2c,0x59,0x8d,0x87,0x4c,0x37,0xc2,0x92,0xc3,0x42,0x0d,0x39,0x03,0xfc,0x16, + 0x7b,0x2e,0x29,0x2a,0x29,0x8f,0xe2,0x26,0x9c,0x3e,0x73,0xfe,0xce,0xbd,0xca,0x2e, + 0x3e,0xbf,0x7f,0xf4,0x1b,0xaa,0x6f,0x91,0x32,0x32,0xb3,0xc8,0xf7,0x3e,0xb0,0xbe, + 0xea,0x6f,0xf3,0xa7,0xa9,0xab,0xa7,0x1f,0xcd,0x8d,0x49,0x49,0x4b,0x8f,0x88,0x44, + 0xfc,0x7d,0x58,0x5b,0xaf,0xf8,0x2d,0xa1,0x8e,0xce,0x4e,0x6b,0x6b,0x6b,0x69,0x2b, + 0xfc,0xca,0x4f,0x63,0x8d,0xd7,0xba,0xdc,0xfc,0xc2,0xa3,0xc7,0x22,0x4f,0x9d,0x3e, + 0x77,0xfb,0x2e,0x98,0x8b,0x51,0xb0,0x49,0x05,0xc0,0xca,0xf6,0x1d,0x3b,0x87,0x5b, + 0x5b,0xde,0x10,0x64,0x05,0x05,0xfe,0x2c,0x2c,0x2c,0x4a,0x6f,0x54,0x84,0x45,0xc7, + 0xc3,0xb5,0x53,0x5c,0x5a,0x0e,0xf8,0xab,0x78,0xb9,0xdd,0x9f,0xa1,0xc8,0xa8,0x18, + 0x5d,0x5d,0xfd,0x11,0x0a,0xd0,0x2e,0x01,0x11,0x7b,0x07,0x87,0xbc,0xc2,0xa2,0xc3, + 0x61,0x91,0xc9,0xe9,0x3f,0x97,0x94,0xde,0xec,0xe8,0xe2,0xf7,0xf6,0x8d,0xf2,0xe9, + 0xae,0xb7,0x4d,0x03,0x83,0x38,0x41,0x6d,0xef,0xe0,0x3d,0x7a,0x0c,0x13,0xdd,0x2b, + 0x60,0x13,0xaa,0xd8,0x08,0xd3,0xfd,0x81,0x9f,0x4c,0x82,0x06,0xd9,0xd9,0x7e,0x28, + 0x5b,0xd7,0x78,0xf2,0xdc,0xdd,0xd5,0x00,0x25,0x76,0x80,0x3e,0x7e,0x82,0xe9,0x5f, + 0x5f,0x7f,0xe7,0xdd,0xb1,0xef,0xfe,0x43,0x69,0xe2,0x9a,0x78,0x16,0xde,0x2c,0x15, + 0xce,0xdc,0x5e,0x36,0x46,0xdd,0x02,0xdf,0x07,0x74,0xd9,0x65,0x03,0xf8,0x05,0x60, + 0xea,0xcb,0x33,0xf7,0x0c,0x01,0x36,0xc8,0x34,0x5b,0xb0,0xdf,0xfa,0x50,0xa7,0x4d, + 0x80,0x70,0xce,0xbe,0x56,0x1d,0xcb,0x0d,0xe8,0x02,0x9b,0x3b,0x58,0x1f,0x68,0x61, + 0x91,0x65,0x45,0x80,0xbc,0xb6,0xd4,0x27,0xf5,0x23,0xe8,0x46,0x33,0x87,0x85,0x08, + 0x4c,0x24,0x2e,0xa7,0x37,0x33,0x03,0xb0,0x4a,0xa1,0x1f,0x11,0x0d,0x7c,0x58,0xf9, + 0x51,0x29,0xbc,0x82,0xb3,0xe9,0x37,0x0c,0x34,0x03,0x18,0x69,0xe8,0x2f,0x92,0x42, + 0xb9,0x4c,0x32,0x30,0xd3,0x53,0xe4,0x25,0x42,0x1c,0xcf,0x45,0x57,0x1d,0x51,0x1b, + 0xbd,0x69,0x99,0xe6,0x72,0x06,0xf9,0x51,0xf4,0xeb,0x09,0xee,0xdb,0x20,0x82,0x4b, + 0x28,0xd6,0x43,0x12,0xd7,0x50,0x05,0x92,0xb3,0x02,0x71,0x19,0x33,0xde,0x5e,0xf6, + 0x95,0x25,0x09,0xc1,0x51,0x72,0xb7,0x59,0xec,0x1c,0xcc,0x38,0x71,0x04,0xf3,0x0e, + 0x0b,0xdc,0xc3,0x98,0x85,0xe1,0xe2,0xa5,0x88,0xbc,0x92,0x8f,0x12,0x7b,0x3f,0x49, + 0x60,0x3e,0x3b,0x2e,0xf8,0x3c,0x99,0xb7,0x29,0xf9,0xc9,0x96,0xc4,0x06,0xef,0xd4, + 0xfa,0x66,0xfe,0xdf,0xf4,0xb3,0x47,0xaf,0x13,0x0c,0xe6,0x2b,0x57,0xad,0x5d,0xb9, + 0x66,0xdd,0xe6,0x2d,0x3b,0x7c,0x7c,0x39,0x31,0xf1,0xc7,0xcf,0x9e,0xbb,0x50,0x50, + 0x72,0xeb,0x5e,0x55,0x75,0x53,0xf3,0x93,0xb6,0x8e,0x6e,0x98,0xa0,0x32,0x02,0xb1, + 0x40,0x88,0x28,0xdc,0xd1,0x85,0x2b,0xa2,0xeb,0x1b,0x5b,0xab,0xaa,0xeb,0x6e,0xde, + 0xae,0xcc,0x2f,0x2c,0xbd,0x78,0xe9,0x97,0xf4,0xcc,0xec,0xb8,0xc4,0xe3,0xa1,0x61, + 0xdc,0x43,0x87,0x82,0x7e,0xd8,0xb3,0x7f,0xdb,0xf6,0x6f,0x37,0x7e,0xbe,0x69,0xdd, + 0xc7,0x9f,0x2e,0x5b,0xb1,0x66,0xd1,0xe2,0x65,0xae,0xf3,0x3c,0xd8,0x8e,0x6e,0x2c, + 0x5b,0x7c,0x22,0x3c,0x7b,0xf6,0x9c,0x99,0x33,0x67,0xca,0x96,0x66,0x4d,0x99,0x30, + 0x01,0x51,0xd8,0xc2,0x02,0x42,0x73,0x5b,0x3b,0xfb,0xfc,0x82,0xa2,0x88,0xc8,0x98, + 0x93,0x30,0x86,0xc0,0x1c,0xfe,0x49,0x7b,0x8f,0xc2,0x2b,0xf7,0xec,0xb9,0x8b,0x30, + 0x48,0x6a,0x69,0xe9,0x68,0x69,0xeb,0x6b,0x6a,0x49,0x23,0x30,0x1a,0x6b,0x69,0xeb, + 0x6a,0x69,0xeb,0x01,0x1e,0xd3,0x85,0x5e,0x90,0xd4,0x37,0x30,0x8a,0x88,0x88,0xcc, + 0x38,0x75,0x26,0x0a,0xf1,0xf7,0x3a,0x38,0x83,0xe8,0xff,0xbe,0x78,0x83,0x97,0x4a, + 0x89,0x11,0x8a,0x66,0xcf,0xb1,0x04,0x81,0x20,0x43,0x5b,0x47,0x0f,0x23,0xba,0x06, + 0x54,0x14,0xa0,0x3c,0xb8,0xea,0x21,0xa1,0x87,0x61,0x90,0xd9,0xef,0xe3,0xbb,0xff, + 0x27,0xdf,0x83,0x01,0x87,0x41,0xe7,0xb4,0x8c,0xec,0xdc,0xbc,0xe2,0x87,0x35,0xf5, + 0xed,0x9d,0x5d,0x30,0x08,0x28,0x58,0xf3,0xf9,0xbb,0xe9,0x25,0x82,0xaf,0x58,0xd2, + 0x07,0x43,0xd9,0xfd,0x07,0x75,0x45,0x25,0x37,0x1a,0x9a,0x1e,0xef,0xfa,0x61,0xb7, + 0x81,0x81,0x81,0xbc,0xbe,0xda,0xda,0x3a,0x9a,0xa4,0xbe,0xda,0x3a,0xba,0x58,0x7d, + 0x30,0x85,0x96,0x4e,0x4c,0x6c,0x5c,0xc6,0xa9,0x6c,0x98,0x72,0xe4,0x5c,0xce,0xab, + 0xae,0x69,0x12,0x8b,0x7b,0x15,0x3c,0x59,0x6e,0x6e,0x69,0x65,0x3b,0x39,0xa3,0x28, + 0x1d,0xba,0x3a,0x0e,0x42,0x6d,0x10,0x49,0x42,0xb0,0x83,0x0e,0x4d,0x6a,0x6a,0x62, + 0x08,0xb6,0xd5,0xc4,0x0f,0x4d,0x6a,0x61,0x8e,0x16,0x96,0xb8,0xc0,0x7d,0x61,0x69, + 0x79,0x45,0x78,0x64,0x6c,0x7a,0x56,0x36,0xf4,0x0a,0x98,0x27,0x28,0x7e,0xdd,0xf8, + 0x6d,0xd1,0x85,0x9c,0xcb,0x06,0x06,0x86,0x52,0x35,0x48,0xad,0xb1,0x8d,0x34,0x09, + 0x11,0xb5,0x89,0xce,0x7f,0x20,0x09,0x3d,0x4b,0x3f,0x98,0x6c,0x85,0x0a,0x95,0xca, + 0xb9,0x7c,0xbd,0xaa,0xb6,0x59,0x28,0x12,0x0f,0xbc,0xe9,0x5d,0x6f,0x4a,0x7c,0x46, + 0xe8,0xe4,0xec,0x82,0xa6,0x23,0xca,0x50,0x7d,0x34,0x34,0xa5,0xfa,0x40,0x08,0x71, + 0x20,0x7a,0x68,0xe9,0xf2,0x15,0x85,0xc5,0xa5,0xc7,0xc2,0xa3,0xc1,0xff,0xad,0xb8, + 0x45,0xbf,0x4e,0xa5,0x68,0xba,0xb2,0x6f,0xff,0x4f,0xb4,0x6a,0x52,0x22,0x92,0xc9, + 0xfe,0x72,0xda,0x54,0xb2,0xb1,0x89,0x59,0x59,0xc5,0x6d,0x6e,0x0c,0xe2,0x6f,0x41, + 0x51,0x79,0x6b,0x5b,0x87,0xe2,0x0f,0xff,0xfd,0x19,0x4a,0x3a,0x91,0x6e,0x6c,0x62, + 0xa2,0x89,0x6f,0xf3,0x63,0x57,0xc1,0x3a,0x4a,0x75,0xc3,0x2b,0xc5,0xc6,0x96,0x5d, + 0x54,0x5c,0x02,0x55,0x4b,0x49,0x3b,0x55,0x52,0x7a,0xe3,0x49,0x7b,0x17,0xcc,0xc4, + 0xfe,0x22,0x4d,0xe4,0x04,0x6e,0x6f,0x7f,0xff,0x80,0xa4,0xa7,0xa7,0xad,0x83,0x57, + 0x55,0x5d,0xdb,0xc9,0xe3,0x6d,0xdb,0xf6,0x6f,0x1d,0xb8,0x66,0x65,0xb6,0x92,0xf7, + 0x8d,0xe1,0x06,0x94,0xb7,0x14,0x6d,0x1a,0xe8,0xf9,0x1a,0x9a,0x34,0x07,0x38,0x75, + 0x64,0xf1,0x91,0x7d,0x63,0x98,0x28,0xfd,0xc9,0xae,0x5f,0x82,0x53,0x66,0x1b,0x24, + 0xb0,0x0e,0x00,0xa8,0xea,0x36,0x72,0xf3,0x06,0x0c,0x55,0x33,0x9a,0x6d,0xbd,0xff, + 0x31,0x5d,0x1d,0x34,0x0d,0xf1,0x17,0xfd,0x5f,0x03,0xa7,0xef,0x68,0xce,0xec,0xef, + 0x6f,0x8f,0xd5,0xc6,0x8d,0xb9,0xc6,0x19,0xcc,0xb0,0xf1,0x79,0x6c,0x1f,0x28,0x62, + 0x07,0x8a,0x01,0x5c,0xa6,0x6d,0xce,0x7d,0xef,0x9d,0x7f,0xbc,0x3f,0x46,0x6d,0xe6, + 0xa6,0x1c,0x0a,0x3a,0xc0,0x8c,0x61,0x90,0xd0,0x36,0x88,0x51,0x40,0x70,0x2e,0x70, + 0x02,0x1b,0xf2,0xbf,0x89,0xc1,0x2a,0x00,0x57,0x08,0xe3,0x22,0x61,0x99,0x4c,0x04, + 0xd6,0x00,0x69,0x1c,0x79,0x02,0x87,0x80,0x6f,0x04,0x01,0x27,0x3b,0x48,0x0c,0xbe, + 0xa7,0x7d,0x80,0x90,0xb2,0xa1,0x1f,0x1a,0x20,0x90,0x0a,0x09,0x92,0xaa,0x27,0x15, + 0x05,0x40,0x49,0x96,0x22,0x83,0x35,0xec,0x02,0xb1,0x38,0xeb,0x00,0xac,0x1a,0xf0, + 0x40,0x88,0x00,0x3a,0x5c,0x54,0x00,0x33,0x5c,0x25,0x38,0x0b,0x92,0xac,0x00,0x21, + 0x5a,0x92,0x32,0x73,0x24,0x58,0x29,0x0e,0x28,0x00,0xca,0x0b,0x5d,0x43,0x90,0xdc, + 0x0e,0x8b,0xe6,0x1f,0x11,0x03,0xf2,0x7a,0x46,0xf5,0x2c,0x8f,0x11,0xaf,0x8e,0x13, + 0x6f,0x48,0x12,0x7e,0x99,0x22,0xfc,0x22,0x45,0xb2,0x3d,0x43,0xb8,0x2d,0x5d,0xb8, + 0x35,0xa5,0x63,0x4b,0x52,0x73,0xc2,0xf5,0x8e,0xa7,0xff,0xf9,0x6b,0x47,0x9e,0xb7, + 0x48,0xdd,0x02,0xe6,0x7b,0xef,0x1f,0x96,0x2c,0x5d,0xf1,0xc5,0x57,0x5f,0xff,0xf0, + 0xa3,0xcf,0xd1,0x08,0x2e,0xe0,0xe9,0xf5,0xbc,0xc2,0x9b,0x77,0x2a,0xeb,0x1b,0x9b, + 0x5b,0xdb,0x3a,0x79,0xc4,0x05,0x86,0xf1,0x47,0x28,0x02,0x08,0x16,0xf1,0xf8,0xdd, + 0x8f,0x5b,0xbb,0xea,0x1a,0x9a,0x2b,0x1f,0xd4,0xde,0xa8,0xb8,0x5f,0x50,0x54,0x7a, + 0xee,0xe2,0xe5,0x8c,0x53,0xa7,0x13,0x8f,0x9f,0x3c,0x16,0x16,0x1d,0x18,0x14,0xba, + 0xe7,0x47,0xfc,0x1a,0xc2,0xa6,0xcd,0xdb,0x3e,0x5e,0xbf,0x71,0xd5,0x9a,0x4f,0x16, + 0x2f,0x5d,0xb1,0x60,0xe1,0x62,0x67,0x57,0x77,0x7b,0x07,0x17,0x96,0x8d,0xbd,0xa5, + 0xa5,0x35,0x41,0xe1,0x59,0xd3,0xa6,0x7d,0x38,0xed,0x03,0xfc,0x76,0x12,0x79,0x53, + 0x69,0x92,0x8d,0xad,0xed,0xb5,0xbc,0x3c,0x6e,0x6c,0xd2,0xc9,0xd4,0x4c,0x70,0xa6, + 0x5a,0x5a,0xdb,0x7b,0x7a,0x47,0x9d,0xc3,0x00,0x74,0x02,0x33,0x38,0xce,0xfa,0x06, + 0x06,0x74,0x41,0x97,0x34,0x62,0x20,0x8d,0x00,0xe8,0x42,0x9c,0xe6,0x1b,0x19,0x9b, + 0x84,0x84,0x1e,0x39,0x7d,0xf6,0x3c,0x37,0x36,0x39,0xe7,0xf2,0xd5,0xea,0x9a,0x46, + 0x40,0xd8,0xd1,0xfc,0x5f,0xdc,0x57,0xaa,0xb7,0xd7,0xce,0xde,0x41,0x0f,0x24,0x50, + 0x32,0xd0,0xd7,0x35,0x30,0x92,0x17,0x04,0x49,0x6b,0x6b,0x56,0x56,0xf6,0x99,0xac, + 0xec,0xec,0x9f,0x7c,0xfc,0x7c,0x0e,0x06,0x04,0x06,0x1d,0x8e,0x88,0x8a,0x4d,0x3f, + 0x75,0x26,0x37,0xaf,0xf4,0x5e,0x65,0x4d,0x7b,0x47,0x27,0xd9,0xf6,0xa7,0xff,0xcf, + 0x3c,0x80,0x20,0x37,0xd3,0xf0,0x16,0xeb,0xb3,0xfe,0xe7,0x30,0x5b,0x68,0x6e,0xe3, + 0x81,0xb5,0xf3,0x8b,0xf0,0xd5,0xb0,0xcc,0xac,0xec,0x19,0x33,0x66,0x92,0xaa,0x81, + 0x56,0x86,0x44,0x31,0x43,0xd0,0x93,0xa8,0x67,0x20,0xb7,0x43,0x64,0x64,0xf4,0xe9, + 0x33,0x17,0x62,0xe2,0x70,0xca,0x51,0x5d,0xd3,0x80,0x9b,0x2c,0x8d,0xbe,0x9b,0x47, + 0x7b,0x67,0xa7,0xbb,0xc7,0x22,0x2a,0xc1,0xc0,0xd0,0x58,0x2a,0x47,0x1e,0x0e,0x8f, + 0xc8,0xcc,0x32,0x2c,0xa9,0xef,0x3a,0x6f,0x7e,0xd9,0x8d,0xdb,0x11,0xdc,0xf8,0xf4, + 0x53,0xd9,0xb7,0xee,0x54,0xc2,0x00,0x08,0xd5,0xff,0x3f,0x58,0x7c,0x58,0x50,0x58, + 0x64,0x6e,0x6e,0x8e,0xa6,0xd0,0x1f,0x56,0xf7,0x91,0xea,0xfd,0x91,0x24,0x74,0x2d, + 0xbf,0x80,0xc0,0xb3,0xe7,0x2f,0x44,0xc7,0x24,0x5c,0xc4,0x3e,0x53,0x47,0xf0,0x57, + 0xc1,0x56,0x12,0x12,0x8f,0xc5,0x4b,0x5f,0x31,0x9a,0xac,0x39,0xe4,0xa1,0x9e,0x4c, + 0x49,0x8f,0xc5,0x9e,0x85,0xc5,0x25,0xe1,0x11,0x5c,0xf0,0x7f,0x71,0xfd,0x9e,0x82, + 0xaf,0xf9,0x10,0x0a,0x08,0x0c,0x31,0x34,0x32,0x92,0x57,0x50,0xda,0x4c,0x06,0xb8, + 0xb9,0x8d,0x9e,0x9e,0x01,0x90,0xa9,0xa9,0x59,0x61,0x69,0x09,0xcc,0x81,0xa5,0xf8, + 0xfb,0xa4,0xa3,0xa7,0x0f,0xdf,0x70,0xa7,0x0b,0xe9,0x47,0xbb,0x89,0xf4,0xc7,0xe8, + 0xf4,0x99,0x9f,0x27,0x4e,0x9a,0x0c,0x0a,0xe8,0xe2,0x63,0xa3,0xa1,0x4b,0x8f,0x92, + 0x35,0xcb,0x06,0x1a,0x25,0x22,0x3a,0x36,0x35,0xed,0x54,0x31,0xe0,0x6f,0x5b,0xd7, + 0xd3,0x67,0xfd,0x7f,0xc5,0x4c,0x4c,0x3e,0x7f,0x7e,0xfe,0x9f,0xfe,0xa7,0xcf,0x9f, + 0x09,0x45,0x92,0xc7,0xad,0xed,0xf7,0x2b,0x1f,0xdc,0xb9,0xf7,0xa0,0xb2,0xfa,0xe1, + 0x87,0xd3,0xa7,0x53,0xc5,0xc8,0xb3,0x2d,0x83,0xe1,0x1a,0xca,0x0d,0xf8,0x7a,0xa3, + 0xeb,0xe9,0x8d,0x0c,0x01,0xc4,0x87,0xc6,0x01,0x52,0x59,0x2d,0x7d,0x53,0x64,0x36, + 0x34,0x32,0x98,0xf0,0xe1,0xac,0x4d,0x3f,0x03,0x52,0x38,0x70,0x10,0x65,0xac,0x7d, + 0x5a,0x34,0x3e,0xf0,0x04,0x60,0xd5,0x63,0x7d,0xe9,0x14,0x24,0x06,0xec,0x70,0x08, + 0x12,0xcf,0xf9,0xb6,0x6c,0x8c,0x06,0xfa,0xbf,0x86,0xae,0xbb,0x1d,0x70,0xed,0x10, + 0xdf,0x74,0xa1,0x0f,0xae,0xb6,0xfa,0xa7,0xfa,0x94,0xd5,0xe1,0x36,0x81,0x02,0x47, + 0x0e,0xc0,0x13,0x84,0x42,0xfb,0x83,0xad,0xef,0x2b,0x1b,0xbf,0xf3,0xee,0x18,0x8b, + 0xe5,0x61,0x6c,0x00,0x23,0x8e,0xc8,0x89,0x23,0x76,0xe4,0x88,0x41,0x38,0x20,0x11, + 0x90,0xa3,0x8c,0xd8,0xaf,0x46,0xd8,0x52,0x12,0x03,0x7e,0x0d,0x4b,0x0e,0x1d,0xa5, + 0x21,0xe8,0x43,0x23,0x20,0x19,0x71,0x2d,0x48,0xc8,0xe6,0x08,0xd9,0x44,0x3e,0x89, + 0x43,0x44,0xe4,0x20,0x0d,0x45,0x34,0xc9,0x96,0x1d,0xa2,0x18,0x4a,0x23,0x6c,0xd4, + 0x47,0x7a,0xd4,0x91,0x30,0xd3,0x43,0x32,0x99,0x58,0x10,0x64,0x3a,0x22,0x1b,0x03, + 0x49,0x7a,0x0a,0x41,0x52,0x01,0x95,0x43,0x18,0xc4,0xb8,0x6e,0x59,0x5a,0x3b,0x21, + 0x91,0x29,0xb0,0xe7,0x08,0x01,0xb5,0xd9,0x1c,0xea,0xea,0x0a,0x50,0x32,0x47,0xe0, + 0x12,0x0a,0xa2,0x84,0xf3,0x8e,0x88,0xd0,0xe7,0x3d,0x26,0xf2,0x08,0x17,0x2d,0x8e, + 0x14,0x2f,0x8f,0x96,0xac,0x8c,0x15,0x7e,0x92,0x24,0xfe,0xf4,0x84,0x64,0x63,0x4a, + 0xef,0xd7,0x19,0xbd,0xdb,0x32,0x25,0x3b,0xb2,0x24,0xbb,0x4e,0x75,0x79,0x67,0xb4, + 0x7f,0x77,0xbc,0xa9,0xac,0x86,0xf9,0xdb,0x6e,0xfb,0xfc,0x86,0x9e,0xfc,0x72,0x30, + 0xbf,0xb0,0x18,0x86,0x5f,0xaf,0x8f,0xd7,0x7f,0xb3,0xd3,0xdb,0x8f,0x73,0x34,0x21, + 0x29,0xf5,0xfc,0xc5,0x2b,0x05,0x25,0x15,0x30,0x99,0x6c,0x6e,0x69,0x03,0x17,0x18, + 0x3c,0x5f,0xe8,0xe1,0x30,0x04,0x09,0x84,0x42,0xa0,0x0e,0x1e,0xd3,0xd2,0xd6,0x01, + 0x5e,0x70,0x65,0x75,0x6d,0x05,0x7e,0xc2,0xbb,0x0c,0x70,0x0d,0x26,0xf3,0xc9,0x27, + 0xd2,0xc2,0xa3,0x63,0x83,0x43,0x8e,0x1c,0xf0,0xf1,0xdd,0xb9,0x6b,0xcf,0xd6,0x6d, + 0x3b,0x36,0x7e,0xbe,0xd9,0x6b,0xdd,0x86,0x55,0xab,0xbd,0x00,0xdf,0x17,0xb8,0x2f, + 0x72,0x9b,0xe7,0x6e,0xcf,0x76,0xb6,0xb1,0x63,0xe3,0x1d,0xe9,0xb9,0x96,0xb3,0x66, + 0xcd,0x06,0x20,0x9e,0x3e,0x7d,0x3a,0xb8,0xc3,0x00,0x79,0xbf,0x5c,0xbf,0x9e,0x98, + 0x9c,0x72,0x32,0x2d,0x2b,0xb7,0xa8,0xe2,0x51,0x73,0x9b,0x58,0x22,0xc1,0xb5,0xb0, + 0x2f,0x5f,0x90,0x4f,0xbf,0x81,0xef,0x31,0x88,0x2b,0x63,0x5f,0xe2,0xe2,0x58,0xf8, + 0x2b,0x2d,0x2f,0x27,0xee,0xb3,0x39,0x3e,0x4a,0x36,0x31,0x85,0xd0,0xd4,0xd4,0xdc, + 0xc4,0x0c,0xf7,0xdd,0x82,0x04,0x64,0x60,0x9c,0xe4,0x03,0x05,0x06,0x05,0xe6,0x5c, + 0xba,0xcc,0x8d,0x4b,0xca,0xb9,0x74,0xad,0xea,0x61,0x3d,0xaf,0x5b,0x40,0xa7,0xe5, + 0x03,0x64,0x70,0xa2,0x40,0x49,0x47,0x57,0x88,0xc3,0x60,0xe8,0xe1,0xe1,0x69,0x62, + 0x6a,0x6e,0x6a,0x86,0xa7,0x1b,0x13,0x81,0x44,0x26,0x0a,0x04,0xb1,0x50,0xd0,0x42, + 0x0f,0x8f,0xa2,0xd2,0xe2,0x13,0x29,0x27,0x0f,0xfa,0x06,0xf8,0xfa,0x07,0x07,0x84, + 0x84,0x45,0x44,0xc7,0xa5,0x67,0x9e,0xbe,0x72,0x35,0xff,0xd6,0x9d,0xfb,0x8d,0x8f, + 0x5a,0xf9,0xdd,0x4c,0x4f,0xcf,0xd3,0xe7,0xfd,0xc3,0x50,0xf8,0xe5,0xa8,0x1e,0xf7, + 0xf0,0x51,0x45,0x36,0xb6,0x0c,0x02,0x84,0xf5,0xf4,0xf6,0xc2,0xdc,0xa7,0xf1,0xd1, + 0xe3,0xdb,0x77,0x2b,0xaf,0x5e,0x2b,0x00,0x1f,0xb3,0xb0,0xa8,0xd8,0xcd,0x6d,0x3e, + 0xd5,0x04,0xd4,0x02,0x32,0x91,0xa9,0x47,0x6b,0x4a,0x09,0x74,0x0e,0x0a,0x0e,0x39, + 0x77,0xe1,0x12,0xb8,0x44,0x17,0x2f,0x5f,0xab,0xac,0x06,0xf8,0x10,0xe1,0x0e,0xc6, + 0x2f,0xb0,0x9a,0x40,0x83,0x44,0x19,0x79,0x12,0x4a,0x59,0xb9,0x6a,0x35,0xda,0xf0, + 0x35,0x51,0xbf,0x4a,0xa0,0x89,0xb3,0x8b,0x6b,0xc5,0xad,0x3b,0x91,0xdc,0x04,0x98, + 0xb9,0x95,0x55,0xdc,0x47,0xff,0xeb,0xe9,0x33,0xda,0x64,0x68,0x55,0xf2,0x60,0x8e, + 0x96,0x45,0xed,0x4c,0x92,0xd2,0xa3,0xb2,0x24,0x99,0x72,0x50,0xdd,0xb0,0x45,0x46, + 0x1c,0x1d,0x24,0x34,0xf2,0xdc,0xb2,0xf2,0xf2,0x0f,0x3e,0x98,0x26,0x6f,0xfd,0xdf, + 0xa5,0xf6,0xaf,0x92,0xcf,0xc1,0x43,0xe0,0x5f,0x47,0x71,0x13,0x2f,0x5e,0xb9,0x5e, + 0xf9,0xa0,0xa6,0x5b,0x20,0xc4,0x2f,0x14,0x0f,0xca,0x4a,0x7f,0x31,0x20,0x87,0x63, + 0x88,0xf4,0x3d,0x7b,0xb6,0x7a,0xcd,0xda,0x5f,0x95,0x49,0xcd,0x3b,0xdf,0x7d,0x41, + 0xd9,0x8d,0x8a,0xa8,0x98,0x78,0xc0,0xdf,0x1b,0x15,0xf7,0xda,0x3a,0x3a,0x7a,0xfb, + 0xfa,0x68,0x87,0x94,0x57,0x53,0x6a,0x28,0x12,0x81,0xbe,0x65,0x61,0x31,0x41,0x5e, + 0x41,0x79,0x1b,0x99,0x98,0xd1,0x8a,0x43,0x30,0xe9,0x7a,0x5e,0x7e,0x72,0x4a,0xda, + 0xf1,0x94,0xf4,0x82,0xc2,0xd2,0xfa,0xc6,0x16,0x49,0x4f,0x2f,0xfd,0xac,0x30,0xb9, + 0x5e,0x06,0x87,0xeb,0x3c,0xa2,0x0a,0xc3,0x93,0xb4,0x68,0x4c,0xbe,0x1c,0x1c,0xd1, + 0x28,0xf2,0x0e,0x7c,0xe5,0xea,0xd5,0x0f,0xa7,0xcf,0x84,0xae,0x47,0x4b,0x97,0xea, + 0x60,0x26,0xed,0x84,0x96,0x56,0x56,0xb9,0x79,0xf9,0xdc,0xd8,0xc4,0x94,0xb4,0xec, + 0xdc,0xa2,0xd2,0x96,0x27,0xed,0xa0,0x09,0xfd,0x74,0xe3,0x50,0xb3,0x82,0xc8,0x61, + 0x5a,0xc9,0x0a,0x7d,0xf1,0x7a,0xb9,0xb4,0xe7,0x48,0x2f,0xcc,0x97,0xf8,0xd5,0x51, + 0x68,0x7e,0x0c,0x88,0x92,0x60,0xb1,0xde,0x3e,0x40,0x5e,0x31,0x4c,0x60,0x1a,0x9a, + 0x9a,0x61,0xe2,0x07,0x5e,0x43,0x4d,0x5d,0xc3,0xde,0x7d,0xfb,0x68,0xb7,0x84,0x4b, + 0x03,0x5c,0xf5,0x3f,0xd9,0x0d,0x68,0xbd,0x4c,0x65,0x95,0x35,0x36,0x33,0x31,0xc6, + 0x85,0x2b,0xa6,0x1f,0x38,0xaf,0x77,0x38,0xd4,0x0c,0xf0,0xe1,0x18,0x2c,0x70,0x0b, + 0x15,0xb2,0xf6,0x3e,0x54,0x36,0xb1,0xc6,0xdd,0x7e,0x56,0x84,0xb2,0x43,0x18,0x76, + 0x30,0x80,0x88,0x70,0xf6,0x4e,0x29,0xfe,0x6a,0x4c,0x74,0x9b,0xb8,0x24,0xd0,0x64, + 0x81,0xcf,0x58,0xe2,0x0e,0x8f,0xd3,0x34,0x9d,0xbc,0x36,0xc2,0x72,0x6f,0x8d,0x23, + 0x79,0x71,0xd5,0x9e,0xc3,0x38,0x04,0x33,0x6a,0x13,0xec,0xff,0xfb,0xbf,0xde,0x33, + 0x64,0x7f,0xeb,0x18,0xc8,0x87,0x4c,0xc7,0x10,0xc6,0x31,0x18,0x97,0x18,0xd9,0x23, + 0x90,0x0d,0x11,0xe4,0x3b,0x70,0x90,0x1c,0xe9,0xa1,0x10,0x24,0x27,0x0e,0x80,0x9a, + 0xc0,0x09,0x4f,0x41,0x51,0x4e,0xa1,0x8c,0xa3,0x8c,0x99,0xcd,0xa1,0xfc,0x02,0xa7, + 0x60,0x40,0x3a,0xc6,0x39,0x18,0x40,0x13,0x43,0x36,0x9e,0x82,0x04,0x9c,0x94,0x19, + 0xf2,0x9d,0x48,0xc4,0x29,0x78,0x28,0xe9,0x84,0x0c,0x78,0x2e,0xa0,0x2d,0x9c,0xe5, + 0x44,0xf2,0x51,0x32,0x82,0x2c,0x8a,0x72,0xe4,0x50,0x0d,0x45,0xf4,0x14,0x59,0x12, + 0x5c,0x63,0xcc,0x94,0x9d,0x2b,0x70,0x0e,0x15,0x92,0xa4,0x48,0x06,0xb8,0x42,0x72, + 0x0a,0x26,0xed,0x11,0x70,0x45,0x58,0xdf,0x10,0x91,0x4b,0xa8,0xd0,0x31,0x44,0xe0, + 0x18,0x8a,0x49,0xe7,0x50,0xd1,0xbc,0x23,0x8c,0x7b,0x98,0x08,0xc8,0x23,0x42,0xb8, + 0x94,0xdb,0x0b,0x3e,0xef,0xaa,0x38,0xf1,0xba,0xc4,0x9e,0xcf,0x4e,0xf6,0x6d,0x4c, + 0xe9,0xdb,0x92,0xd9,0xb7,0xe3,0x74,0xef,0x37,0xd9,0x3d,0xbb,0x7f,0x16,0xef,0x3e, + 0xc3,0xec,0x3e,0xd3,0xed,0x9d,0xd9,0xee,0x7f,0xa1,0xad,0xe7,0xf9,0xdf,0xfa,0xb5, + 0xdf,0xd7,0xa9,0x7f,0xa0,0xff,0x7b,0xef,0x5d,0xcb,0x56,0xac,0xfa,0x6a,0xd3,0xd6, + 0xbd,0xfb,0x0f,0x85,0x45,0x72,0x33,0xb3,0xce,0x5d,0xcb,0x2b,0xbc,0x75,0xf7,0x41, + 0x5d,0x43,0x53,0x6b,0x5b,0x17,0xa0,0x89,0x40,0x28,0xf9,0x5f,0xf6,0xbe,0x03,0xba, + 0xad,0xe3,0x4a,0xf4,0x9c,0xbf,0xb6,0x9c,0xea,0x6c,0x36,0xbb,0xc9,0xa6,0x6f,0x49, + 0xbc,0xb1,0x1d,0xa7,0x6c,0x62,0x27,0x9b,0x38,0x2e,0x92,0x2d,0xd9,0x6a,0xee,0x56, + 0xb3,0x64,0x5b,0xb6,0x7a,0xb1,0x2d,0xc9,0xea,0x14,0x29,0x51,0xec,0x9d,0x94,0x28, + 0xf6,0xde,0x2b,0x40,0x90,0x00,0x3b,0x89,0xca,0xde,0x7b,0x27,0xd8,0x2b,0x0a,0x09, + 0x56,0xe0,0x9f,0xf3,0xef,0x9d,0x79,0xef,0xe1,0xa1,0x50,0x96,0x5c,0xe2,0x55,0x7e, + 0x74,0xae,0xc7,0x77,0x66,0xee,0xdc,0x3e,0xb8,0x6f,0xc0,0x87,0xf7,0xe0,0x0c,0x05, + 0x35,0x71,0x66,0x76,0x16,0x60,0x72,0x7a,0x7a,0x68,0x04,0xff,0x16,0x0c,0xc7,0x49, + 0xa8,0x38,0x32,0x65,0x75,0x41,0x91,0x54,0x90,0x93,0x9b,0x98,0x9c,0x1a,0x1a,0x16, + 0xeb,0x17,0x14,0xec,0xe6,0xe1,0x75,0xf9,0x8a,0xf3,0xe9,0xb3,0x17,0x8e,0x9d,0xf8, + 0x68,0xff,0xfb,0x87,0xdf,0xda,0xf7,0xee,0x1b,0x3b,0x76,0xbf,0xf4,0xf2,0xab,0x9b, + 0xb7,0xbe,0xfc,0xdc,0xc6,0xcd,0xeb,0x9f,0xdb,0x44,0xef,0xce,0xfa,0xe3,0xff,0xfc, + 0xe9,0x89,0x27,0xfe,0x07,0x0a,0xf1,0xfa,0xf5,0x1b,0xa0,0x88,0x27,0x24,0xa7,0x42, + 0xfd,0x2d,0x91,0x2a,0xdb,0x3a,0x7b,0xc7,0x27,0xa1,0xe8,0x6b,0xb5,0xfa,0x39,0x1d, + 0xc0,0xdc,0x3c,0xc0,0xdc,0x1c,0x3e,0x18,0x0a,0x76,0x34,0x1c,0x8d,0x1b,0x9a,0x9a, + 0xe0,0xb3,0x97,0xde,0x53,0x4d,0xe1,0x67,0x3f,0xfb,0x39,0xbf,0xfb,0x8b,0x5f,0xfc, + 0x82,0x45,0x1e,0x76,0xba,0x76,0xad,0xa0,0xb8,0x24,0x2c,0x22,0x2e,0x27,0x37,0xbf, + 0xbe,0xb1,0x0d,0x2e,0x2a,0xc0,0x16,0x60,0x05,0xff,0xe9,0xf5,0xf3,0x3a,0x3d,0x32, + 0x07,0xd3,0xe0,0xe4,0x0b,0x83,0xf3,0x86,0x05,0xf8,0x2c,0xe5,0xb3,0xb2,0x05,0xe0, + 0xb9,0x77,0xdf,0xdb,0x32,0xb9,0x3c,0x29,0x39,0xc5,0xc5,0xd5,0xd3,0xd5,0xc3,0xd7, + 0xdb,0xff,0x46,0x70,0x48,0x44,0x5c,0x42,0x7a,0xae,0xb8,0x58,0xa6,0xac,0x6a,0x6d, + 0xef,0x1e,0x1c,0x1a,0x02,0x47,0x69,0xb5,0x3a,0xf8,0xa0,0xa0,0xbf,0xc7,0xfc,0xc4, + 0xfa,0xbb,0x0a,0xd7,0x18,0x2b,0x46,0xa8,0xda,0x50,0x79,0x61,0xed,0xe0,0xd0,0x30, + 0xf0,0x51,0x56,0x54,0xe7,0x8a,0x8b,0x4a,0xcb,0x15,0x95,0xd5,0x55,0x7b,0xf6,0xee, + 0x03,0xd1,0x3f,0xff,0xf9,0x7f,0x3d,0xf4,0x10,0xb5,0x0e,0x90,0x87,0xe1,0x3a,0x84, + 0xed,0x9a,0xc1,0xc5,0xcd,0x03,0x4e,0xbe,0x11,0x91,0x71,0xc2,0x5c,0x09,0x7c,0x34, + 0x8d,0x8c,0x8e,0xc1,0xa9,0x1c,0x8e,0xd2,0x3a,0xb0,0x9a,0xf8,0x90,0x02,0x78,0x00, + 0x3c,0x3c,0x39,0x39,0xb3,0xef,0x9d,0x77,0x6f,0x6f,0xf2,0x6d,0x60,0xfd,0x86,0x0d, + 0x95,0xd5,0xb5,0x21,0x11,0x31,0x49,0xc9,0x99,0x60,0x7b,0x57,0xef,0xc0,0xd4,0xb4, + 0x86,0x08,0x9a,0xc7,0xf0,0x11,0x71,0x24,0x88,0x73,0x8c,0x9f,0x49,0x34,0xe9,0x2c, + 0x13,0x05,0x42,0x40,0x70,0x3d,0x4b,0x8c,0x94,0xcc,0x5a,0x56,0x55,0xd2,0xc5,0x29, + 0x8d,0x16,0xa2,0x84,0x39,0xf0,0xfb,0xc7,0x9f,0x00,0x05,0xc0,0x09,0x9f,0x5a,0x79, + 0xbb,0xf0,0x5f,0xff,0xf5,0x0b,0x27,0xa7,0xab,0x25,0x25,0x65,0x21,0xa1,0x31,0xa2, + 0xbc,0x7c,0xb8,0xc8,0x1c,0x1a,0x19,0xd7,0xd0,0x9c,0x61,0x95,0x67,0x70,0xa2,0x36, + 0x24,0xcd,0x81,0x83,0x87,0xee,0x90,0xf9,0xa6,0x4d,0x2f,0x54,0x56,0x55,0x87,0x86, + 0x47,0xa5,0xa6,0x0b,0x14,0xaa,0xea,0x6e,0x70,0xd7,0xcc,0xac,0x56,0xcf,0x59,0x8a, + 0x11,0xd1,0xea,0x19,0x04,0x8a,0x7e,0x42,0x62,0xd2,0xa3,0xbf,0xfc,0xe5,0x6d,0x18, + 0x3e,0xfc,0xf0,0x23,0xf9,0x45,0xc5,0x49,0x29,0xe9,0xb1,0xf1,0x29,0x25,0x65,0xf2, + 0xd6,0xf6,0xde,0xc9,0xa9,0xa9,0x59,0x8c,0xf5,0x3c,0x4f,0x5b,0x46,0x55,0x9e,0xa0, + 0x79,0x9a,0x0c,0xe6,0xa0,0x70,0x31,0x62,0xac,0x9b,0x83,0x28,0x32,0x09,0x33,0x3f, + 0x3f,0x0b,0x7b,0x66,0x6e,0x5e,0x2e,0x97,0xff,0xe9,0x4f,0x7f,0xb2,0xdd,0x6e,0x14, + 0x9e,0xf8,0xc3,0x1f,0x8b,0x4b,0x4a,0x23,0x63,0x12,0x12,0x93,0x33,0x8a,0x4a,0x65, + 0xf0,0xe9,0x31,0x3e,0x39,0xc5,0x8a,0xe6,0x84,0xb2,0xdb,0xcd,0x1c,0x7a,0x73,0x4a, + 0xe8,0x99,0xfc,0x9c,0xa3,0x1b,0x9f,0x9b,0xd5,0x90,0x1d,0x0b,0x18,0xfc,0x1f,0x3e, + 0x17,0x20,0x97,0x27,0x26,0xa7,0xd4,0xc3,0x63,0x9d,0xdd,0xbd,0x8d,0xcd,0x6d,0xa5, + 0xe5,0xca,0x5c,0x49,0x41,0x5d,0x43,0x53,0x4a,0x5a,0xfa,0xe3,0x4c,0x4a,0x60,0x10, + 0x1f,0x7e,0xf8,0x73,0x4e,0x0c,0xf8,0x87,0xdb,0xff,0x91,0x5f,0xff,0xf1,0x68,0xc6, + 0x46,0xbf,0xd9,0x0d,0x50,0x26,0x7c,0x66,0x9f,0xf7,0xd1,0xfe,0xf9,0x72,0xf3,0xb7, + 0x7e,0xfc,0xbb,0xfb,0xef,0xff,0xda,0x63,0x7b,0x22,0x9e,0xf3,0x9d,0x85,0x3a,0xf8, + 0x9c,0xb7,0xf6,0x8f,0x1f,0x33,0xf7,0x5f,0xad,0xbb,0xef,0x81,0x07,0x1e,0xf8,0xc6, + 0xba,0x75,0x5f,0xbb,0x1f,0xd0,0x7f,0x58,0x77,0xff,0x3f,0xac,0x7b,0xe0,0xab,0xdf, + 0xfa,0xa7,0x7f,0xff,0xfd,0x6f,0x0f,0x64,0xac,0xf7,0xd6,0x3e,0xe7,0x03,0xa5,0x4d, + 0xf3,0xfd,0xdf,0xbc,0x06,0x53,0xff,0xf6,0xd4,0xe1,0x0d,0x1e,0x13,0xb0,0x16,0x78, + 0xc2,0xf8,0x46,0xdf,0xd9,0xe7,0x7d,0x75,0xeb,0x41,0x84,0xbf,0x6e,0x83,0x8f,0xe6, + 0x39,0x5f,0x1d,0x54,0xa8,0xe7,0x7d,0xb5,0x2c,0xe8,0x80,0xec,0x79,0x9f,0xd9,0xe7, + 0x7c,0x74,0xd8,0x7a,0x43,0xab,0xd9,0xe0,0xcd,0xe0,0x38,0x48,0xc8,0x36,0x78,0xcf, + 0x6c,0xf4,0xd3,0x3f,0xe3,0x0d,0x53,0x9a,0x8d,0xc0,0x0d,0x75,0x83,0x25,0xb8,0x70, + 0x83,0x17,0xb3,0x9c,0xea,0x00,0xcb,0x9f,0xf3,0xd6,0xd0,0xd9,0xe7,0x90,0x09,0xb4, + 0x33,0xcf,0xa3,0x81,0xf8,0x1b,0x5b,0x42,0x8c,0x2d,0x21,0x00,0x1b,0xb5,0xd4,0xcc, + 0xf5,0xde,0xb3,0xcf,0xfb,0x41,0xd5,0xd6,0x42,0xbb,0x81,0x5b,0x0b,0x3c,0xfd,0xf0, + 0xc7,0xb9,0x4f,0x33,0xb7,0x4b,0xa1,0x4f,0x80,0x72,0x03,0x0c,0x7a,0x69,0x40,0x87, + 0xe7,0xfd,0x50,0x1f,0xb2,0x56,0x0b,0x3e,0x44,0xdd,0xfc,0x34,0x1b,0xfd,0xb5,0xcf, + 0xf9,0x81,0xb1,0xf4,0x2f,0xbc,0x50,0x76,0x75,0xdb,0x82,0xe1,0xcc,0x3b,0xf7,0x7a, + 0x98,0x66,0x47,0x24,0x54,0x5e,0xfd,0xfe,0xf8,0xf9,0x83,0x49,0x86,0x13,0xe9,0x86, + 0x0f,0x33,0x0d,0xe7,0x84,0x86,0xcb,0x22,0x83,0x63,0x9e,0xc1,0x39,0x4f,0x77,0x55, + 0x34,0xe3,0x24,0x9c,0xb8,0x2a,0x18,0x55,0xf4,0xe8,0xbf,0xf4,0x7a,0xfa,0x29,0x00, + 0x0e,0x56,0x3b,0x77,0xbd,0xb5,0xef,0xed,0x77,0x3f,0x3e,0x7b,0xd1,0xc5,0x33,0x20, + 0x3a,0x2e,0x19,0x3e,0xb7,0xe5,0xaa,0x9a,0xa6,0xd6,0xf6,0x7e,0x28,0x03,0xa3,0xe3, + 0x53,0xd3,0xd3,0xb0,0x05,0x70,0x5f,0xe8,0xf0,0x14,0x0c,0xf9,0x3f,0x3e,0x09,0x25, + 0x78,0xa2,0x6f,0x60,0xa8,0xb5,0xbd,0xa3,0xa1,0xb1,0x59,0x59,0x51,0x07,0x67,0x34, + 0x51,0x5e,0x51,0x52,0x4a,0x56,0x64,0x4c,0xfc,0xcd,0xe0,0x08,0x4f,0x2f,0x7f,0x67, + 0x17,0x8f,0x73,0x17,0x1d,0x3e,0x3a,0x7d,0xee,0xc8,0xb1,0x0f,0xdf,0x79,0xe7,0xc0, + 0xae,0x3d,0xef,0xbe,0xf6,0xfa,0xae,0xed,0x2f,0xbd,0x01,0x55,0x78,0xd3,0x0b,0x9b, + 0xc9,0x3d,0xd2,0x1b,0x9e,0x7c,0xea,0x99,0x3f,0x3f,0xf9,0x97,0xe7,0x37,0x6e,0x12, + 0xe5,0x8a,0x93,0xd3,0x32,0xe3,0x13,0x53,0x24,0x85,0x65,0xd5,0xb5,0x4d,0xed,0x9d, + 0x7d,0xbd,0x7d,0x83,0x3d,0x83,0xe3,0xfd,0x83,0xea,0x81,0xc1,0x61,0x28,0x9a,0xbd, + 0xfd,0x03,0xfd,0x03,0x83,0x03,0xa0,0xcf,0xc8,0x68,0x67,0x77,0x37,0x7c,0xf6,0x3e, + 0xf6,0xd8,0x63,0xbf,0x64,0xff,0x3d,0x46,0xfe,0xfd,0xea,0x57,0xbf,0xa6,0xdd,0x47, + 0x1e,0x79,0x84,0x1b,0xbf,0x70,0xf1,0x12,0x9c,0xf1,0xa1,0xfe,0xa6,0x67,0x66,0xcb, + 0xe4,0xd5,0x4d,0x2d,0x70,0x99,0x0c,0xac,0xd4,0x5d,0xfd,0xf8,0x74,0xcd,0xbe,0xfe, + 0x21,0xb8,0x90,0xe8,0x1e,0x18,0x05,0xce,0x7d,0xfd,0x6a,0x28,0xf9,0xef,0x1f,0x7c, + 0xff,0x97,0xf6,0xfe,0xd1,0xbf,0x5c,0xd3,0x7f,0xbf,0xfa,0xd5,0xaf,0x8e,0x9f,0xfc, + 0xa0,0xae,0xbe,0x2e,0x36,0x29,0xd5,0xc3,0xdb,0xcf,0xcd,0xfb,0x86,0x6f,0xc0,0xcd, + 0xe0,0x5b,0x11,0xd1,0x71,0x89,0x59,0x82,0x3c,0xb8,0x14,0xaf,0xae,0x6b,0xec,0xe8, + 0xea,0x05,0x5d,0x27,0xa7,0xe0,0xa3,0x6b,0x6e,0x61,0x11,0x7f,0xd0,0x0c,0x87,0xeb, + 0x55,0xe6,0x9a,0x9f,0x3d,0xea,0x42,0xcd,0x35,0xae,0xc2,0x69,0x65,0x69,0x79,0xc5, + 0xb0,0xb8,0x00,0x9f,0x36,0x70,0xb1,0x03,0xd7,0x36,0xa0,0x61,0x55,0x4d,0x03,0x7c, + 0x9c,0x66,0x0b,0xf3,0xca,0xa4,0xb2,0xd6,0xb6,0xf6,0xf7,0x0e,0x1c,0xfc,0xed,0x6f, + 0x7f,0xcb,0x37,0x19,0xfe,0x3d,0xfa,0xa8,0x5d,0x4d,0x7f,0x79,0xf5,0x9a,0x73,0xa9, + 0xb4,0x3c,0x34,0x2c,0x1a,0x94,0x29,0x93,0x57,0xb5,0xb4,0xb5,0xf5,0xf4,0x81,0xf3, + 0x86,0x20,0x9a,0x70,0x3c,0x87,0xa8,0xf5,0x0f,0x8e,0x02,0xf4,0x92,0x07,0x7d,0x43, + 0x75,0x3e,0x7a,0xec,0xb8,0x7d,0x46,0x77,0xf0,0x6f,0xc3,0x86,0x0d,0x70,0x36,0x8f, + 0x8c,0x8a,0x87,0x4f,0xdd,0xfc,0xa2,0x92,0x5a,0x34,0xbc,0x8f,0x7a,0xb5,0x6f,0x40, + 0x4d,0x00,0x90,0x61,0x10,0x47,0x9e,0x2b,0x3e,0x4c,0xba,0x2c,0xf4,0x33,0x23,0xd8, + 0x72,0xf8,0x00,0xd3,0x02,0x3d,0xe8,0xdc,0x4b,0xdb,0x7e,0x80,0xe1,0x5e,0x60,0xd2, + 0x8f,0xac,0xc0,0xb1,0x2d,0x6d,0xed,0x7f,0x79,0xea,0xe9,0x4f,0xad,0xf6,0x6d,0xfe, + 0x81,0x93,0xcf,0x5d,0x38,0x5f,0x2a,0x95,0x87,0x86,0xc7,0xa6,0x65,0x64,0x4a,0xe5, + 0xaa,0xa6,0xd6,0x2e,0x88,0x08,0x6b,0x0b,0x75,0x20,0x55,0x69,0x70,0x50,0x3d,0x3c, + 0x3d,0xa3,0xf9,0xe8,0xf4,0xe9,0x3b,0x64,0xfe,0xfc,0xf3,0x1b,0x2b,0xab,0xab,0xa3, + 0xa2,0x13,0x13,0x92,0xd3,0x0a,0x4a,0xca,0x6b,0xeb,0x5b,0x3a,0xbb,0xfb,0xbb,0x7b, + 0xc1,0x5e,0x64,0x08,0x56,0x53,0x04,0xce,0x74,0xdd,0x83,0xe3,0xa3,0xe3,0xe3,0x99, + 0xd9,0x82,0xff,0xfe,0xef,0xdf,0xd9,0x55,0x92,0x66,0xfb,0x63,0x8f,0xfd,0x3a,0x27, + 0x57,0x9c,0x92,0x9a,0x19,0x1d,0x93,0x84,0xaf,0x50,0xa9,0xaa,0x6f,0x6d,0xef,0xea, + 0xee,0x47,0x55,0x49,0xac,0xd1,0xed,0x9c,0x6f,0xa9,0xcf,0x2d,0x42,0xc0,0x73,0xb8, + 0xe5,0x08,0x05,0xec,0xe2,0xd6,0x20,0x39,0x53,0x51,0x55,0xf5,0xec,0xb3,0xcf,0x52, + 0xe9,0xb6,0x2a,0xfd,0xe9,0xcf,0x7f,0x2e,0x2c,0x2e,0x8b,0x8d,0x4f,0x8e,0x8d,0x4b, + 0xcd,0xcb,0x2f,0xaa,0xa9,0x6b,0x80,0x5d,0x4c,0xb8,0x0d,0x0e,0xa8,0x47,0x7b,0xd8, + 0x38,0xb2,0xe1,0x56,0x43,0xee,0xd1,0xd9,0xde,0x7e,0x6b,0xb9,0x64,0x84,0xa7,0x55, + 0xff,0x10,0xc9,0x55,0x35,0xb8,0xa5,0xb7,0x5f,0xdd,0xd6,0xd9,0x0d,0xbb,0xb8,0xba, + 0xb6,0x51,0x2a,0xab,0xcc,0x93,0x94,0xc0,0xbe,0x2e,0x2a,0x93,0x56,0xd5,0xd4,0x6c, + 0x7f,0xf9,0x15,0x4e,0x99,0x47,0xd7,0xda,0x1b,0x9f,0xe1,0x1f,0x7c,0xaa,0x80,0xd7, + 0xff,0xb8,0x71,0xf7,0x26,0xf7,0xfe,0xe7,0x7c,0xf4,0x2f,0x06,0xce,0x6c,0xf2,0xd3, + 0xbe,0x10,0xa0,0x7d,0xd2,0xa1,0xe5,0x5b,0x3f,0x7d,0x62,0xdd,0xfd,0x5f,0x79,0x6c, + 0xf7,0xcd,0x17,0x03,0x34,0x70,0x70,0x83,0x41,0xae,0xfe,0x7e,0xfb,0x27,0xbf,0xf9, + 0xf9,0xd3,0xef,0xff,0xe4,0x2f,0xef,0xff,0xf8,0xc9,0xf7,0x7f,0xf4,0xe4,0xc1,0x7f, + 0x7e,0xe8,0xc9,0x75,0x0f,0xe0,0x2d,0x58,0xdf,0xf9,0xaf,0xf5,0xcf,0x79,0x8e,0xbc, + 0xe0,0xaf,0x7d,0x31,0x40,0xfb,0xbd,0x47,0x5f,0x80,0xba,0xfc,0x1f,0xcf,0x1c,0xdb, + 0xe4,0x3b,0xf1,0x62,0xe0,0x2c,0x14,0xa3,0x17,0x90,0x0f,0x54,0xa5,0xd9,0x17,0xfc, + 0x67,0x01,0x47,0xf0,0xd7,0xc0,0x14,0x74,0x61,0x1c,0x00,0xbb,0x40,0xe3,0xa7,0x23, + 0xf4,0x30,0x0e,0x38,0x8e,0x43,0x77,0x13,0xe9,0xc2,0x12,0xe4,0xe3,0x3f,0x03,0x83, + 0x9b,0x03,0xa1,0xf8,0xce,0xbc,0x18,0xa0,0xc7,0xae,0x1f,0xd1,0x10,0xc7,0xb5,0xb0, + 0x10,0x88,0x37,0x11,0x1c,0x46,0x36,0xfa,0xe2,0x08,0x28,0x8f,0x83,0x84,0x8c,0xc8, + 0x02,0x73,0xa0,0xab,0xdf,0xe4,0x87,0xab,0x88,0xdc,0x59,0x34,0x1c,0xc7,0x75,0xa8, + 0xa4,0xaf,0x6e,0xa3,0xaf,0xfe,0xc5,0x80,0x99,0x17,0x03,0x75,0x30,0x4e,0x96,0x00, + 0x9f,0x19,0x1c,0x87,0x59,0x50,0x38,0x40,0xf7,0x2c,0xfe,0x5c,0x08,0x2b,0x2c,0x0c, + 0x6e,0xf2,0xd7,0x3f,0xef,0x0f,0x45,0x19,0x34,0x47,0xf5,0x36,0x07,0x69,0x36,0x05, + 0x40,0xab,0x63,0x6b,0x2e,0xc0,0x0c,0x9c,0x76,0x01,0x76,0x46,0x68,0xdf,0x8c,0x30, + 0xbc,0x1d,0x83,0x95,0x17,0xce,0xbc,0x87,0x92,0x0d,0x67,0xb2,0xd9,0xca,0x2b,0x36, + 0x38,0xe7,0x1b,0xdc,0x0a,0x0d,0x57,0xf3,0xb5,0xee,0xe2,0x69,0x27,0xe1,0x78,0x94, + 0x7c,0x4a,0xbb,0xf0,0xe5,0x17,0xd3,0x4f,0x01,0x70,0x99,0xed,0xed,0xeb,0xff,0xda, + 0x1b,0x3b,0x8e,0x1e,0x3b,0x71,0xc5,0xf1,0x9a,0x7f,0x70,0x78,0x4a,0x5a,0x76,0x61, + 0x49,0x59,0x75,0x0d,0xd4,0x41,0xd8,0x37,0xe3,0x50,0x6d,0xe9,0x5f,0x81,0xe1,0x68, + 0x06,0x75,0x18,0xea,0x2f,0xb9,0x04,0xd5,0x40,0x69,0x1e,0x1c,0x1a,0x03,0x12,0xd8, + 0x0e,0x35,0xb5,0x0d,0x52,0x99,0xaa,0xa0,0xa8,0x34,0x4b,0x98,0x97,0x90,0x84,0x0f, + 0xe8,0x08,0xba,0x19,0xea,0xe5,0xe3,0x7f,0xcd,0xd9,0xfd,0xfc,0x05,0x87,0xd3,0x67, + 0xce,0x9f,0xf8,0xe0,0xd4,0x81,0x83,0x47,0xdf,0xdd,0x7f,0x70,0xc7,0xce,0xbd,0xaf, + 0xbf,0xb9,0xeb,0xe5,0x57,0xdf,0xd8,0xba,0xed,0xa5,0x17,0x36,0xbf,0xf4,0xfc,0xc6, + 0x2d,0x5b,0xb6,0xbe,0x24,0x96,0xe4,0xe3,0x0b,0x49,0xe3,0x92,0xd3,0x33,0x05,0xe2, + 0x02,0x10,0xae,0x90,0xc9,0x2b,0xa5,0xf2,0x0a,0x99,0xa2,0xaa,0x4c,0x56,0x51,0xae, + 0x50,0xc9,0x15,0xd5,0xe5,0x8a,0x8a,0x52,0xb9,0xaa,0xa2,0xba,0xae,0xbd,0xab,0xe7, + 0xe9,0x67,0x36,0x3c,0xfe,0xc4,0x1f,0x10,0x1e,0xc7,0xf6,0xf7,0xbf,0x7f,0x1c,0xdb, + 0xc7,0x9f,0xe0,0x0f,0xfe,0x0e,0x07,0x9f,0x38,0x73,0xfe,0x2c,0x1c,0x34,0xc2,0x22, + 0x62,0x13,0x92,0xd2,0x85,0x22,0x89,0xa4,0xa8,0xbc,0x54,0xaa,0x2a,0x53,0xa8,0xca, + 0xe4,0x08,0xe5,0x72,0x95,0x54,0x5e,0x55,0x8e,0x48,0x25,0x9c,0x32,0xfb,0xfa,0x07, + 0xcf,0x9c,0x3b,0xcf,0x67,0x85,0x08,0xc1,0xa9,0x08,0xca,0x19,0xda,0x27,0x9e,0xf8, + 0x23,0x5c,0xb1,0x54,0xd6,0xd4,0xe6,0x17,0x95,0x06,0xde,0x08,0xf1,0xf2,0x0f,0xf6, + 0x0f,0xba,0x75,0x2b,0x24,0x12,0x2e,0x3f,0x92,0x52,0x32,0x85,0x39,0x92,0xc2,0xa2, + 0xf2,0xaa,0x9a,0x46,0xb8,0x86,0xe9,0xe9,0x1b,0x04,0x2f,0x8d,0x4d,0x80,0x13,0xb5, + 0x33,0xb3,0x1a,0x3c,0xd9,0x11,0xa0,0x97,0xf7,0xe0,0x4f,0xa8,0xd1,0x30,0x3b,0x34, + 0x32,0xd6,0xd5,0x33,0xd8,0xdc,0xda,0x0d,0x06,0x96,0x96,0xcb,0x05,0x39,0xe2,0xb4, + 0x0c,0x81,0x52,0x55,0xad,0xac,0xa8,0x3c,0x70,0xf8,0x88,0x59,0x19,0xd4,0xe4,0x0f, + 0x8c,0x99,0x7c,0xc3,0x59,0x25,0x01,0x1c,0x9d,0xae,0x96,0x4b,0x55,0xb7,0xc2,0xa0, + 0x28,0xa6,0x65,0x0b,0xc5,0x92,0x42,0x69,0x49,0x39,0xb1,0x57,0xca,0x98,0x2c,0x63, + 0x0c,0x47,0x00,0x93,0x2f,0x3b,0x38,0x70,0x0c,0xed,0x82,0xd9,0xb1,0x56,0xe3,0xbf, + 0x7f,0xfc,0xb9,0x8d,0x9b,0x94,0x95,0xd5,0xd1,0xb1,0x09,0x91,0xd1,0xf1,0x19,0x59, + 0x22,0x71,0x7e,0x71,0x51,0xa9,0x42,0x4a,0xf8,0x43,0xbc,0x10,0x28,0xce,0x03,0x0c, + 0x2b,0x04,0x57,0x51,0x49,0x70,0x6c,0xcb,0x65,0x2a,0x73,0xcb,0x82,0x5c,0x51,0x05, + 0x23,0x72,0x79,0x95,0xed,0xac,0x12,0x5f,0xd4,0xd5,0xba,0x65,0xeb,0x36,0x6b,0x27, + 0xf0,0x42,0xc6,0xd7,0x99,0x89,0xdd,0x9d,0xc0,0xe3,0xb8,0xfc,0xd4,0xc7,0x67,0x41, + 0xb1,0x10,0x74,0x60,0x86,0x50,0x24,0x2e,0x2c,0x2e,0x2f,0x2a,0x53,0x96,0xb1,0xd2, + 0x65,0xf2,0x2a,0x30,0x01,0x35,0x04,0x84,0xdc,0x14,0xe7,0x78,0xe5,0x9a,0x95,0x5b, + 0xec,0xfa,0x0a,0xda,0x8d,0x9b,0x5e,0x50,0x55,0xd6,0x82,0xbb,0xa2,0xa2,0x93,0xd2, + 0xb3,0x20,0xd5,0x4b,0x0b,0x4b,0x31,0x0a,0x32,0x85,0x4a,0xca,0x19,0x2e,0xaf,0x02, + 0xdb,0x41,0x5c,0x5d,0x43,0x2b,0x1c,0xc0,0x9f,0xfc,0xcb,0x53,0xd6,0x06,0x5a,0x76, + 0x05,0x42,0x91,0x40,0x98,0x1b,0x11,0x15,0x97,0x92,0x9e,0x95,0x2b,0x2e,0x2c,0x2a, + 0x95,0xd3,0x70,0x63,0x62,0x2b,0x80,0x73,0x25,0xd5,0x96,0xfa,0x10,0x98,0x97,0x11, + 0x13,0x64,0xe8,0xf9,0x4a,0xb3,0xc3,0x65,0x76,0x5a,0x39,0xc3,0x01,0xec,0xad,0x92, + 0xab,0xaa,0x6a,0xeb,0xeb,0xb6,0x6e,0xdf,0x0e,0x72,0xed,0x1a,0xf8,0xd4,0xd3,0xcf, + 0xe6,0x4a,0xc4,0x29,0x69,0x19,0x11,0x91,0x89,0xc9,0xa9,0xd9,0x79,0x92,0xa2,0xa2, + 0x12,0x69,0x19,0x31,0xc7,0x3a,0x07,0x78,0x52,0x98,0x64,0xe0,0x34,0xe1,0xa2,0xac, + 0x30,0x23,0xe0,0x0d,0x74,0x88,0x4c,0x55,0x2a,0x55,0x16,0x97,0xc9,0x0a,0x0a,0xcb, + 0xc5,0xf9,0x85,0xf0,0x39,0x93,0x9a,0x91,0x9d,0x98,0x94,0x0e,0xbb,0x1b,0xae,0x00, + 0xdf,0xdc,0xb5,0x1b,0x0e,0xe0,0x77,0x1a,0x65,0xdb,0xed,0xb3,0x46,0x32,0x58,0x90, + 0xfd,0xfe,0xf1,0x3f,0xfe,0x65,0xc3,0x86,0x73,0x85,0x5b,0x6e,0x68,0xb6,0x05,0xeb, + 0xa1,0x5e,0x6c,0xb9,0x81,0xf5,0x62,0xa3,0xe7,0xc0,0xbf,0x3e,0xba,0x01,0x4a,0xea, + 0x43,0x2f,0x9c,0xdb,0x7a,0x13,0x8b,0x08,0x4c,0x3d,0x79,0xb9,0xf6,0xeb,0xdf,0xc5, + 0xef,0x9f,0xff,0x73,0xb3,0x03,0xd0,0x6f,0x0f,0xd6,0x6f,0xbb,0x89,0xf4,0x2f,0xf8, + 0xa8,0xff,0xf3,0xcf,0x6f,0xc3,0xf8,0x83,0xdf,0xf9,0xd1,0x7a,0xa7,0xba,0x6d,0x37, + 0xe7,0x37,0xfb,0x4f,0x7d,0xe7,0x47,0x0f,0xad,0x5b,0xf7,0xd5,0x47,0x5f,0x77,0xdb, + 0x12,0xa4,0x83,0xd3,0xdf,0xf6,0x5b,0xf3,0x50,0x95,0xe0,0xe8,0xb7,0xf5,0x26,0x48, + 0x01,0x6e,0x7a,0x52,0x9b,0xe6,0x08,0x0e,0x08,0xce,0x92,0xae,0x86,0xfc,0x0c,0x47, + 0xcf,0x91,0x91,0x2e,0x8c,0xcf,0x82,0x56,0x30,0x02,0x5d,0x32,0xae,0xa1,0x0b,0xc9, + 0x88,0x86,0x22,0xec,0xa0,0x86,0x32,0x27,0xa0,0xe7,0xd1,0xeb,0x59,0x02,0x1d,0xbb, + 0x16,0x24,0xce,0xb3,0x5d,0x0d,0xa1,0xa4,0x42,0x51,0x0a,0xdb,0x65,0x38,0x6f,0xbd, + 0x89,0xc4,0xd0,0x52,0xff,0x80,0x45,0x54,0x67,0xd2,0xe5,0x14,0xc0,0x2f,0x96,0xb7, + 0x07,0xeb,0x00,0xb6,0xdd,0xd4,0xbd,0x1a,0x3a,0xfb,0xf2,0x2d,0xed,0x2b,0xa1,0x73, + 0x6f,0x84,0xeb,0xde,0x0c,0x9f,0xdf,0x19,0xa9,0xdb,0x1d,0x3d,0xb7,0x37,0xc6,0xf0, + 0x5e,0x02,0x96,0x5d,0x38,0xf3,0x7e,0x94,0x65,0xb8,0x24,0x32,0x5c,0x11,0x1b,0xae, + 0x15,0x18,0x5c,0x8a,0x0c,0xde,0xa5,0x8b,0xfe,0xa5,0x0b,0xb7,0xca,0xb5,0x3e,0x45, + 0x06,0xdf,0xfc,0x19,0x5f,0xc9,0x58,0xfb,0xd8,0xe7,0x77,0xe3,0xeb,0x5f,0x1d,0x9a, + 0x5b,0xdb,0xf7,0xee,0x7d,0x1b,0x0a,0xca,0x47,0xa7,0xce,0xba,0x79,0x05,0x44,0xc6, + 0xc4,0xc1,0xe7,0xbf,0x54,0xa1,0xaa,0x6b,0x6c,0xe9,0xe8,0x55,0xf7,0x0f,0x4f,0x4c, + 0x4e,0x41,0xe9,0xd0,0xd2,0xaf,0x7f,0x49,0x15,0x9e,0x83,0x4a,0x32,0x35,0x3d,0x3b, + 0x32,0x36,0x3d,0x88,0x37,0x45,0x0f,0x92,0xd7,0x34,0xb4,0xc0,0x66,0x87,0x4d,0x27, + 0x12,0x17,0xa4,0x65,0x0a,0xe3,0x93,0xd2,0x42,0xc2,0xa2,0x03,0x6f,0xdc,0xf2,0xf4, + 0xf2,0xbb,0x7a,0xcd,0xed,0xc2,0xa5,0x2b,0x50,0x85,0x4f,0x7e,0x70,0xfa,0xf0,0x91, + 0xe3,0xfb,0xf7,0x1f,0xda,0xb3,0x77,0xff,0xce,0xdd,0xfb,0x5e,0x7f,0x63,0xf7,0x2b, + 0xaf,0xbd,0xf1,0xea,0xeb,0x3b,0x73,0x44,0xb9,0xc2,0xdc,0xe2,0x98,0xb8,0xc4,0x84, + 0xa4,0x34,0x28,0xc1,0x99,0xd9,0x79,0x70,0xf4,0xcb,0xcc,0xce,0x81,0x16,0x0e,0x71, + 0x80,0x64,0x09,0x72,0x33,0xb3,0x85,0x80,0x8b,0x25,0x45,0x6d,0x1d,0x9d,0xdb,0x5f, + 0x7e,0xf5,0xa9,0xa7,0xd7,0x43,0x15,0x7e,0xea,0xe9,0x0d,0x4f,0x3d,0xb3,0x01,0x8e, + 0x42,0x4f,0x3d,0xf3,0x2c,0x6d,0x01,0x9e,0x7c,0xea,0x69,0x80,0xbf,0x3c,0xfd,0x0c, + 0xc0,0xe9,0x8f,0xcf,0xd5,0x37,0x34,0x86,0x46,0x46,0x47,0xc7,0x24,0xc2,0xf9,0x3a, + 0x35,0x3d,0x0b,0x2e,0x98,0x33,0xb2,0x84,0x99,0xd9,0x22,0xd2,0xe6,0x00,0x92,0x25, + 0x40,0x1c,0xda,0xc6,0xe6,0xb6,0xeb,0x6e,0xee,0xb0,0xea,0xe9,0x67,0xd7,0x53,0x26, + 0x4f,0x3d,0xb3,0x1e,0x00,0x46,0x9e,0x02,0x40,0x11,0xcf,0x50,0xce,0x4f,0x3f,0xb3, + 0xfe,0x99,0xf5,0x1b,0xc0,0x96,0x82,0xe2,0xe2,0x8a,0xaa,0x1a,0xb8,0x72,0x80,0xeb, + 0x8d,0x5b,0xa1,0xd1,0xa1,0xe1,0x31,0xf8,0x87,0xec,0xc4,0xf4,0xd4,0xf4,0xec,0x5c, + 0xbc,0x92,0x80,0xcf,0x8f,0x9a,0xda,0xba,0x26,0xb8,0x44,0x81,0xe3,0x40,0x4f,0xef, + 0x00,0xbd,0xfe,0x1f,0x1c,0x1a,0x81,0x16,0x0e,0xf5,0x70,0x49,0xdf,0xde,0xd9,0xdb, + 0xdc,0xd6,0x59,0x57,0xd7,0xac,0x54,0x55,0x15,0x97,0xca,0x73,0xc5,0x45,0xe9,0x99, + 0x22,0xa8,0x9b,0xb5,0xf5,0x8d,0xe5,0x52,0xf9,0xc1,0x23,0x47,0x41,0x99,0xbf,0x30, + 0xd2,0x19,0x03,0x29,0xa0,0x81,0x4f,0xa1,0xb1,0x40,0x40,0xbb,0x4f,0x3f,0xf3,0x2c, + 0x00,0xd4,0x53,0x65,0x45,0x75,0x70,0x68,0x44,0x54,0x74,0x02,0xf8,0x33,0x2d,0x23, + 0x0b,0x2a,0x63,0x46,0x16,0x78,0x55,0x44,0x7c,0x2b,0x22,0x00,0x86,0x0b,0x33,0xb2, + 0x72,0x1a,0x9b,0xda,0x5c,0xdd,0x3c,0x28,0x7f,0x86,0x27,0x01,0x4e,0x28,0x95,0xcb, + 0xef,0x82,0xdb,0x09,0xc1,0x06,0x28,0x0d,0xdb,0x5e,0x7a,0x59,0x55,0x59,0x15,0x97, + 0x98,0x1a,0x1a,0x11,0x0b,0xee,0x4d,0x4a,0xcd,0x04,0x9e,0x00,0xc0,0x9f,0xb8,0x97, + 0xf1,0x30,0x01,0x73,0x97,0x28,0x23,0xa4,0x2d,0x0b,0x9c,0x56,0x39,0xdc,0x12,0xaa, + 0x33,0x0f,0xa1,0x3c,0x45,0x39,0x79,0x92,0xc6,0xe6,0x96,0x5d,0x7b,0xde,0xa2,0x61, + 0x7a,0x9a,0xda,0xce,0x86,0x0c,0xbd,0x01,0xb9,0x41,0x7c,0xc2,0x5a,0xf4,0x2c,0xa7, + 0xbc,0x95,0x99,0xd6,0x56,0x43,0xb8,0x9f,0x7e,0xf6,0xd4,0x99,0xb3,0x95,0xd5,0x75, + 0xa1,0x11,0xd1,0x91,0xd1,0x89,0x89,0xc9,0xe9,0x69,0x19,0x98,0x30,0xc4,0x28,0x11, + 0x5f,0x0d,0xd0,0x2a,0x4b,0x90,0xd3,0xd0,0xd4,0xec,0xe3,0xe7,0xff,0x24,0x1b,0x1a, + 0x73,0xaa,0xf0,0xdc,0x48,0x7d,0x05,0x34,0x2f,0x6e,0xd9,0xaa,0xaa,0xac,0x89,0x4f, + 0x48,0x85,0x0b,0xc2,0xb8,0x84,0xe4,0x94,0x34,0xc8,0x46,0x01,0x44,0xc7,0xd2,0x4c, + 0xc6,0xea,0x92,0xd2,0xf2,0xe2,0x92,0xb2,0x17,0x36,0x6f,0x7d,0xfa,0x19,0x26,0xca, + 0xa4,0x65,0x58,0xd1,0x2e,0x30,0x4f,0xcf,0xc8,0x10,0xe5,0x15,0x84,0x86,0xc5,0xc4, + 0xc6,0x27,0x25,0xa5,0x30,0x0c,0x81,0x15,0x41,0x04,0x9c,0xeb,0xf8,0x8e,0xa5,0xe1, + 0xe0,0x5b,0x64,0x39,0x6b,0x1b,0x05,0xdc,0x1d,0xcd,0x2d,0x2d,0x3b,0x76,0xed,0xe2, + 0x25,0x1b,0xbb,0x35,0x48,0x3e,0x3c,0xbf,0xf1,0x05,0xb8,0xbe,0x85,0xab,0xe8,0x30, + 0xf8,0xf8,0x48,0x48,0x4a,0x4c,0xc9,0x82,0x0b,0x48,0x2e,0x82,0x34,0xdf,0x6c,0x22, + 0xcb,0x09,0x12,0xf2,0x68,0xac,0x93,0x01,0x44,0xd3,0x41,0x62,0x51,0x0e,0x6c,0xe1, + 0xa4,0x94,0x8c,0x04,0xf8,0x2f,0x4b,0x00,0xa7,0xec,0xe2,0xd2,0xf2,0xc3,0x64,0x8f, + 0xd0,0x10,0xac,0x15,0x59,0x36,0xf4,0x1b,0xf8,0x5d,0x2e,0x73,0xec,0x12,0x63,0x9e, + 0x3f,0xb5,0x9e,0x1d,0x7c,0x16,0x12,0x63,0xd3,0x9e,0xf3,0x2f,0xdd,0x98,0x7c,0x2d, + 0x54,0xff,0x6a,0xe8,0x1c,0x69,0xb5,0xaf,0x84,0xe8,0x5e,0xb9,0x39,0xf5,0xb3,0xe7, + 0x8e,0x40,0x49,0xfd,0xc1,0x2f,0x37,0xbe,0x1c,0x34,0xf6,0x5a,0x18,0xde,0xa0,0xbb, + 0xc1,0xb1,0xf2,0x41,0x52,0x7f,0x1f,0xda,0x7a,0x9e,0x9c,0xe6,0x90,0x12,0x90,0x57, + 0x6e,0xcd,0x3e,0xbc,0xcd,0x11,0xeb,0xef,0x3f,0xff,0x64,0xd3,0xb5,0x7a,0x60,0xf2, + 0xdc,0xd5,0xda,0xaf,0x7e,0xed,0x9b,0x5f,0xf9,0xda,0xb7,0x9f,0x38,0x9a,0x02,0x0c, + 0x09,0x4f,0x3d,0x50,0xbe,0x4a,0xf8,0xbf,0x86,0xdd,0xb9,0x57,0x42,0x61,0x04,0xbb, + 0x2f,0xdd,0xd2,0xbf,0x16,0x0a,0x53,0xda,0xd7,0xb1,0xab,0x7f,0x39,0x04,0x08,0xe6, + 0x5f,0x0d,0xd5,0x11,0x11,0x73,0x2f,0x07,0x6b,0x51,0x3a,0x10,0x84,0xe8,0x70,0x30, + 0x14,0x2b,0xda,0x2b,0x21,0xda,0x57,0x81,0x5b,0x08,0x10,0x23,0x93,0x97,0x6e,0x51, + 0x62,0x04,0xc0,0x29,0x2b,0x1c,0x04,0xd1,0xc8,0x53,0xf7,0x72,0x08,0xc1,0x43,0x75, + 0x68,0x5a,0x28,0x43,0xf6,0x1a,0x22,0x7a,0xb2,0x4a,0x4f,0x96,0xcc,0xbd,0x8a,0x6a, + 0x00,0x4f,0xdd,0xcb,0xb7,0xf4,0x94,0xe6,0xa5,0x60,0x0d,0x08,0x02,0x71,0xa0,0x24, + 0x99,0x05,0x04,0xb9,0x11,0x1c,0x67,0x5f,0x0b,0x9b,0x67,0x4d,0xd3,0x51,0xfe,0x50, + 0x6d,0x01,0x5e,0x0f,0xd7,0xbe,0x11,0xae,0xdd,0x15,0xa9,0x7f,0x3b,0x66,0x6e,0x5f, + 0xac,0xfe,0x5d,0x72,0xda,0x05,0x38,0x9a,0x6a,0x38,0xce,0x7d,0xdb,0x9c,0x6b,0xb8, + 0x96,0x6f,0x70,0x2f,0x5e,0xf0,0x2b,0x5f,0xf4,0x97,0x2e,0x06,0xca,0x97,0x82,0x64, + 0x8b,0xc1,0xb2,0x45,0xbf,0x62,0xad,0x4f,0xfe,0x8c,0xb0,0x4e,0xb7,0xb8,0xf6,0xef, + 0xf8,0xfe,0xf7,0xc3,0xe2,0xf2,0xd2,0xad,0xb0,0xc8,0x37,0xde,0xdc,0x75,0xf0,0xd0, + 0xd1,0x8b,0x97,0xaf,0xfa,0x06,0xdc,0x84,0xa3,0x53,0x5e,0x7e,0xa1,0x52,0x55,0xdb, + 0xd4,0xda,0x01,0x57,0xf8,0x63,0xe3,0xf8,0x77,0xe0,0x99,0x59,0x3c,0x02,0xcf,0xcd, + 0xd3,0x3f,0xc5,0xce,0xc1,0x29,0x18,0x46,0xc7,0x27,0x67,0x86,0x46,0x26,0x7a,0x07, + 0xd4,0x1d,0x5d,0xfd,0x0d,0x4d,0x6d,0x55,0x35,0x0d,0x50,0x85,0xf3,0x0b,0xcb,0x72, + 0x72,0xf3,0xd3,0x32,0x84,0xb1,0xf1,0x29,0x61,0xe1,0xb1,0x01,0x70,0x42,0xf4,0x0d, + 0x70,0xbc,0xee,0xe9,0xe0,0xe4,0x7c,0xf6,0xbc,0xc3,0xa9,0x33,0xe7,0x3e,0xfc,0xf0, + 0xd4,0xc1,0xc3,0xc7,0x0f,0x1c,0x3c,0xb2,0xff,0xbd,0x43,0xef,0xee,0x3f,0x20,0xc8, + 0xc9,0x2d,0x29,0x95,0xc7,0x25,0xa4,0x81,0x5c,0xb2,0xb9,0x32,0x68,0x9b,0x98,0x0c, + 0x6d,0x1a,0x8c,0xc3,0xc7,0x20,0x00,0xa9,0x26,0x42,0x28,0x58,0x7b,0xdf,0x7e,0x77, + 0xf3,0x96,0x6d,0x5b,0xb6,0x6e,0x7f,0x71,0xf3,0xb6,0x17,0xb7,0xbc,0xbc,0x65,0x1b, + 0x20,0x5b,0x36,0x6f,0xd9,0xba,0x75,0xdb,0x76,0x38,0x4d,0x03,0x0e,0x87,0x23,0xe8, + 0x6e,0xde,0xba,0xed,0xcc,0xb9,0x4b,0xcd,0x2d,0xed,0x91,0x31,0x89,0x51,0x31,0x09, + 0x70,0xee,0x88,0x4b,0x48,0x85,0xcf,0xbd,0xf8,0xc4,0x54,0xd8,0xbf,0x71,0x09,0x29, + 0xa4,0x4d,0x25,0x22,0x52,0x80,0x3f,0x7c,0xea,0xde,0xbc,0x15,0xb2,0x6d,0xfb,0x2b, + 0xc0,0x67,0xf3,0x96,0xed,0x94,0x0f,0x91,0x82,0xac,0x36,0x6f,0xdd,0xbe,0x75,0xfb, + 0x4b,0xf0,0x11,0xba,0x99,0xc0,0x0b,0x38,0xf8,0xf2,0xbe,0xb7,0xdf,0x49,0x49,0x4b, + 0x6f,0xeb,0xe8,0x2a,0x29,0x91,0x46,0x46,0xc7,0x85,0x45,0xc6,0x12,0x41,0xc9,0xc0, + 0x16,0x3e,0x5d,0xe1,0x93,0x10,0xae,0x64,0xc4,0xf9,0x25,0x85,0x25,0x72,0x38,0xe0, + 0x28,0x94,0x55,0x70,0xfc,0x51,0x55,0x37,0x00,0x54,0xd5,0xd4,0x57,0x54,0xd5,0xc1, + 0x79,0x5e,0x2a,0x57,0x16,0x95,0xca,0x24,0x05,0x65,0x42,0x51,0x01,0xf9,0x6c,0x17, + 0x94,0x4b,0x95,0x5d,0xdd,0xbd,0xa9,0x19,0x59,0xc0,0x7c,0x33,0x31,0x04,0x64,0x6d, + 0x41,0x95,0xb6,0xd2,0x2e,0x00,0x98,0xc9,0x74,0xb7,0x6e,0xdf,0x0c,0x26,0x53,0x6f, + 0x6c,0xd9,0x06,0x3a,0x3b,0x5d,0xbd,0x56,0x53,0x5b,0x1f,0x19,0x95,0xc0,0x9a,0x8c, + 0x36,0x82,0x63,0xe3,0x13,0xd3,0x09,0x6e,0x01,0x55,0x35,0x75,0xc1,0xa1,0x21,0x60, + 0x20,0xac,0x05,0x93,0x29,0x5b,0xca,0x6a,0xcb,0xb6,0x97,0x88,0x57,0xb7,0x93,0x91, + 0x6d,0xc4,0xa5,0x8c,0x9f,0x01,0x27,0xf4,0x5b,0xdf,0x78,0x73,0xa7,0x42,0x55,0x09, + 0x1f,0x89,0x70,0xf0,0x27,0xb2,0x92,0x59,0x71,0x76,0x64,0x7d,0x5e,0x00,0x8e,0x85, + 0xfa,0x7b,0xec,0xf8,0xc9,0x17,0x36,0x6f,0x79,0x71,0xeb,0x76,0x6b,0x6f,0xb0,0x01, + 0xe2,0x3b,0x6a,0x0b,0x8e,0x53,0xd7,0xd1,0xb0,0x6e,0x27,0xb0,0xcd,0xaa,0x0b,0xf8, + 0x8b,0x5b,0xb6,0x7f,0x7c,0xfe,0x7c,0x5d,0x43,0x73,0x4c,0x5c,0x52,0x44,0x54,0x42, + 0x6c,0x7c,0x32,0x20,0x60,0x0e,0xb1,0x28,0x99,0x1a,0x08,0xce,0x24,0xc9,0x93,0x06, + 0x50,0x59,0x5d,0x1d,0x16,0x11,0x4d,0xa2,0xb3,0x8d,0xf2,0xa1,0x4e,0xa3,0x72,0x31, + 0x70,0xc4,0x99,0x9b,0xb1,0xdd,0xfe,0xda,0xeb,0x6f,0x56,0x54,0x55,0x67,0x64,0xe6, + 0x44,0x46,0x27,0xc0,0x35,0x1b,0xec,0x0e,0x5b,0x47,0x91,0x9c,0x4c,0x06,0xce,0xb0, + 0x29,0x54,0xaa,0x8a,0x37,0x77,0xbc,0x45,0xd7,0x6e,0xa1,0xa6,0x21,0xdb,0xed,0x4c, + 0x50,0xb6,0x61,0xe8,0x53,0xd3,0xd2,0xe1,0x84,0x0e,0xe7,0x5f,0x08,0x37,0xcf,0xff, + 0x69,0xac,0xce,0xd6,0xde,0xa3,0x99,0x7f,0xe7,0x40,0x58,0x81,0xa5,0x19,0xcd,0x6d, + 0xad,0x87,0x8e,0x1c,0x25,0xe6,0x6c,0xc5,0x8d,0x00,0xbe,0x62,0x93,0x01,0x60,0xeb, + 0xf6,0x57,0x84,0xb9,0x79,0xb9,0x92,0x42,0x30,0x2d,0x3a,0x06,0xac,0x4b,0x61,0x1d, + 0x95,0xfa,0x19,0xc3,0x0d,0xd7,0x75,0xac,0x21,0xc0,0x0d,0x9c,0x96,0x90,0x91,0x95, + 0xad,0x54,0x55,0x76,0x74,0xf5,0xc0,0x66,0xd9,0xb5,0x67,0x1f,0xb8,0x17,0xfc,0x8c, + 0xdf,0xa7,0x81,0x42,0xdb,0x5e,0x62,0x76,0x0a,0x8d,0xac,0x55,0x77,0xab,0x45,0x8c, + 0xcc,0x79,0xc2,0xee,0x23,0xbb,0xc4,0x34,0xcd,0x5e,0xde,0xf1,0xce,0x9b,0xde,0x75, + 0xbb,0xa2,0xe6,0xde,0x8e,0xd1,0xec,0x89,0xd2,0xef,0x8d,0xd6,0xed,0x8c,0x98,0x7b, + 0x2b,0x7a,0x6e,0x4f,0x94,0xf6,0x2f,0x1f,0xa6,0xe0,0xfb,0x25,0xff,0xf1,0x87,0xcf, + 0x3b,0x94,0xed,0x8e,0xd2,0xee,0x89,0xd2,0xbd,0x78,0xad,0xfa,0x1f,0xbf,0xf7,0x33, + 0x18,0xfc,0xc5,0xe6,0x33,0xaf,0x05,0x0d,0xbe,0x41,0xe0,0x25,0xdf,0xbe,0xf5,0xe7, + 0xf3,0x7f,0xf8,0xf0,0x53,0x30,0xfe,0x4f,0x3f,0xfd,0xfd,0xab,0x81,0xc3,0xbb,0xc2, + 0xa6,0xfe,0xfb,0x4d,0x37,0xfc,0x9a,0xfa,0x47,0x8f,0xbc,0xe4,0xdb,0x05,0x0b,0x81, + 0x33,0x30,0xdc,0x19,0xc9,0x70,0xde,0x1b,0xad,0xd9,0x1d,0xa5,0xdf,0x17,0xa3,0x27, + 0x53,0x9a,0xbd,0x31,0x73,0xbb,0xa3,0xe6,0x76,0xe1,0xac,0x6e,0x4f,0x34,0xde,0x8f, + 0xb4,0x37,0x5a,0x0b,0x23,0x7b,0x63,0xb0,0xbb,0x2f,0x46,0x0b,0x2a,0xed,0x8e,0xd4, + 0xed,0x8b,0x86,0x72,0x86,0xcb,0x61,0x2d,0xd4,0x35,0xd0,0x79,0x6f,0x94,0x66,0x27, + 0x8e,0xe8,0x28,0x67,0x50,0x12,0x06,0x41,0xd6,0xce,0x48,0x3d,0x1d,0xdc,0x8d,0x42, + 0xe7,0x61,0xed,0x2e,0xe4,0x4f,0x5b,0x3d,0x2c,0xdf,0x1d,0xa9,0x45,0xfa,0x48,0x2d, + 0x35,0x96,0x2c,0xd7,0x33,0xc4,0x51,0x38,0x45,0xc8,0x70,0x76,0x0f,0x3a,0x44,0xc7, + 0x10,0x47,0xce,0xef,0x88,0x00,0x26,0xc0,0x59,0xb7,0x23,0x12,0x7f,0x2e,0x04,0x83, + 0xd0,0xdd,0xcd,0xca,0x02,0xf5,0xde,0x8e,0xd1,0xbd,0x13,0xab,0x47,0x88,0x9b,0x07, + 0x78,0x3f,0x61,0x0e,0x8e,0xba,0x00,0x47,0x52,0x0c,0x27,0x33,0x0c,0x67,0x05,0x08, + 0x17,0x45,0x06,0xa7,0x7c,0xc3,0xd5,0x02,0x83,0x07,0x1c,0x78,0xcb,0x97,0x82,0xe5, + 0x2b,0xb7,0x14,0x2b,0x51,0x15,0x0b,0x91,0xaa,0xc5,0x70,0xd5,0xd2,0x4d,0xe9,0x42, + 0x40,0xa9,0xe6,0x66,0xf1,0xb4,0x7a,0xf6,0x1e,0x78,0xe0,0xe4,0xed,0x61,0x40,0xad, + 0x86,0xa3,0xd6,0x8e,0x5d,0x6f,0x9d,0x38,0xf9,0xa1,0xd3,0x35,0xf7,0x9b,0x21,0xe1, + 0xe9,0x99,0xc2,0xfc,0xc2,0x72,0xb8,0xc2,0x6c,0x6d,0xef,0xee,0x1f,0x1c,0x19,0x1d, + 0x9f,0x9e,0x9e,0xd1,0xc2,0xc9,0x17,0x4e,0xc1,0xf3,0x06,0x03,0x85,0x59,0x8d,0x06, + 0xea,0x32,0x54,0x61,0x98,0x1d,0x50,0x8f,0xf4,0xf4,0xa9,0xdb,0x3a,0x7a,0x1a,0x9a, + 0x5a,0xab,0x6a,0x6a,0xcb,0xa4,0xaa,0xfc,0xc2,0x52,0x61,0xae,0x24,0x35,0x5d,0x08, + 0x1b,0x07,0x2e,0xf8,0x6f,0x04,0x87,0xf9,0x07,0x04,0xbb,0x7b,0xfa,0x5e,0x73,0x71, + 0xbf,0x7c,0xc5,0xf9,0xfc,0xc5,0xcb,0xa7,0x3e,0x3e,0xff,0xd1,0xa9,0x73,0x27,0x3f, + 0x38,0x05,0x45,0xaa,0xba,0xb6,0x1e,0x5a,0x72,0x1a,0x85,0x2b,0x5e,0xe6,0xd2,0x17, + 0xea,0x17,0x5c,0xf4,0x42,0xcd,0x4d,0xcf,0xcc,0x49,0xcb,0xc8,0x81,0x56,0x90,0x23, + 0xea,0xeb,0xef,0xff,0xe8,0xf4,0x99,0x5d,0xbb,0xf7,0x12,0x78,0xeb,0xf5,0x9d,0xef, + 0xec,0xd8,0xb5,0x77,0xc7,0xce,0xb7,0x76,0x42,0x77,0xcf,0x5e,0xc4,0x77,0xbd,0x05, + 0x2d,0xcc,0xbe,0xb9,0x6b,0xf7,0xb9,0x0b,0x0e,0x9d,0xdd,0x3d,0xc0,0x36,0x2d,0x5d, + 0x98,0x8a,0x90,0x0d,0x97,0xe5,0x04,0x84,0x14,0x81,0x2d,0x0c,0x38,0x5c,0x57,0xc3, + 0xb9,0xb8,0xb2,0xba,0x3e,0x31,0x29,0x69,0xcf,0x9e,0xb7,0xe9,0x72,0xe4,0xb3,0x13, + 0x91,0x9d,0xbb,0x10,0x90,0x21,0x48,0xd9,0xb5,0x77,0x37,0x8e,0xec,0x01,0x71,0x30, + 0xbb,0x73,0xe7,0xde,0x7d,0xef,0x1c,0x70,0xf3,0xf4,0x92,0x2b,0x2b,0xdb,0xda,0x3b, + 0x8b,0x8a,0xcb,0x81,0x27,0x7c,0x78,0x26,0x26,0x67,0x26,0xa7,0x66,0x90,0x03,0x8e, + 0x30,0x23,0x3b,0x37,0x3b,0x27,0x0f,0x4e,0x6d,0x70,0xb6,0xcd,0x93,0x14,0x4b,0x0a, + 0x8b,0x25,0x05,0xa5,0x80,0x50,0xc8,0xc9,0x2b,0x10,0x88,0xf0,0x8c,0x0f,0xc7,0x87, + 0xb2,0x72,0x79,0x67,0x57,0x0f,0xb8,0xc2,0xc5,0xdd,0xe3,0x9d,0xfd,0x07,0x76,0x11, + 0x11,0xd4,0xb4,0x9d,0x68,0xd7,0x5e,0x46,0x28,0x51,0x8c,0xe2,0xbb,0x98,0x11,0x6a, + 0x38,0x12,0x3b,0x5f,0x77,0x6d,0x6a,0xe9,0x64,0x2c,0x4d,0x07,0x33,0xb3,0x08,0x64, + 0x83,0x26,0x9c,0xd5,0xd0,0x25,0x04,0xc2,0x9a,0xba,0xfa,0xc4,0xe4,0x54,0x8e,0x03, + 0x0a,0xda,0xfd,0x16,0xc7,0x16,0xdc,0xbb,0x73,0x27,0x63,0x3e,0x43,0xb0,0x0b,0x95, + 0x21,0x08,0x78,0x63,0xcf,0xbb,0xef,0xbd,0xaf,0xac,0xa8,0x10,0x4b,0x8a,0x88,0x6f, + 0xb3,0xd8,0x48,0x09,0x52,0xd3,0x51,0x04,0x15,0x44,0x25,0x82,0x38,0x0a,0x44,0x07, + 0x0b,0xe0,0x05,0x25,0x9b,0x84,0x43,0xc0,0x52,0x0a,0x2c,0x81,0xae,0x85,0xa3,0x53, + 0x6e,0x47,0x57,0xf7,0x45,0x87,0x2b,0xa0,0xde,0x9b,0x3b,0x31,0x4c,0x3b,0xa9,0xc2, + 0x8c,0x9e,0x6f,0xe1,0xc8,0x2e,0xd6,0x33,0x3c,0x8b,0x30,0x94,0x38,0xc2,0xcc,0xd2, + 0x25,0x94,0x78,0x27,0xd3,0x45,0xfc,0xfc,0x25,0x87,0xe6,0xd6,0x36,0x38,0x73,0x81, + 0x45,0xc4,0x10,0x21,0x5f,0x0d,0x9e,0x6e,0xa8,0x7c,0x45,0x55,0x6d,0x7a,0x66,0xd6, + 0x9e,0xbd,0xfb,0xa8,0x0f,0x49,0xa4,0x18,0x86,0xc0,0x8d,0x26,0x24,0xe3,0x3d,0x48, + 0x95,0xb7,0xf7,0xc3,0x75,0x57,0x41,0x51,0x31,0xe1,0x8c,0x7c,0xc0,0x5d,0x90,0x7b, + 0x10,0x20,0xea,0x3d,0xc2,0x9f,0xb6,0x39,0xb9,0xe2,0xc2,0x86,0xc6,0xa6,0x43,0x87, + 0x8e,0xef,0x60,0xb5,0x7d,0x73,0xe7,0x2e,0xea,0x7c,0x36,0x3a,0xc8,0x36,0x23,0x33, + 0x4b,0x51,0x51,0xc9,0x31,0x64,0x15,0xcb,0xa6,0x4c,0x78,0x51,0xa0,0x99,0xc0,0x84, + 0x89,0x06,0x82,0x5d,0x92,0x6d,0x69,0x1a,0xd7,0x65,0x32,0x87,0x76,0xdb,0x3a,0x3a, + 0xce,0x5f,0x74,0xc0,0x84,0x04,0x7f,0x62,0xfe,0xa3,0x9f,0xd9,0x6d,0x88,0x5e,0xcd, + 0x15,0xe7,0xcb,0x14,0x15,0xa9,0xe9,0x99,0x5c,0x32,0xc0,0x9e,0x65,0x53,0x42,0xc8, + 0x72,0x36,0x8b,0xe6,0x38,0xb3,0x99,0x90,0x6d,0x19,0x77,0x73,0x02,0x40,0xea,0xc2, + 0xd5,0x88,0x28,0xaf,0xb0,0xb4,0x5c,0xd1,0xd4,0xdc,0xd2,0xda,0xd6,0x55,0x58,0x54, + 0xe2,0xe0,0x74,0x6d,0xdf,0x3b,0xfb,0x77,0xd2,0x10,0xef,0x62,0x74,0xa0,0x59,0xca, + 0x86,0xfe,0xad,0x1d,0xdc,0xbe,0xc0,0xc1,0xb7,0x76,0xb0,0x1b,0x99,0x06,0x9a,0x64, + 0xce,0x5b,0x5c,0x6e,0xb3,0xf9,0x4f,0x70,0x20,0x26,0xc8,0x9b,0x64,0xbb,0xbd,0xbe, + 0x7b,0xdf,0x3e,0x67,0xe1,0xfe,0xd8,0x59,0x38,0x97,0x1d,0x48,0x84,0x03,0xda,0xfc, + 0x81,0xa4,0xb9,0xf7,0x12,0xb0,0x6a,0xbc,0x13,0x37,0xf7,0x76,0x98,0xfa,0xdb,0x3f, + 0x7a,0x6c,0xdd,0x7d,0x0f,0x3c,0xb2,0xfe,0xed,0x7d,0x11,0x63,0x40,0xf3,0x8a,0x7b, + 0xd5,0x3f,0x7e,0x1f,0xcf,0xbf,0xdf,0xf8,0xf6,0x0f,0xbe,0xfb,0x6f,0xbf,0xf9,0xce, + 0xbf,0xff,0xee,0x5f,0xfe,0xf3,0x77,0xdf,0xfd,0xd1,0x23,0x5f,0x7f,0xf0,0xbb,0xf7, + 0xdf,0xf7,0xc0,0x37,0x1f,0xfc,0xa7,0x27,0x76,0xbb,0xbc,0x1f,0xaf,0x7b,0xd5,0x4d, + 0xf5,0xcf,0x3f,0xfd,0x0d,0x8c,0xfc,0x7a,0xeb,0xa9,0xf7,0xe3,0xb5,0x07,0x08,0x73, + 0x7a,0x8b,0x2f,0x70,0x7e,0x3f,0x11,0x60,0xde,0x8c,0x80,0x50,0xec,0xea,0x0f,0x24, + 0xe8,0xdf,0x43,0x5c,0x8f,0x78,0xa2,0x0e,0xd4,0x38,0x80,0x5d,0xdd,0xfb,0x09,0x86, + 0xf7,0x12,0x98,0x3b,0x84,0xa1,0x3d,0x40,0x5a,0xa0,0xa1,0x6b,0x09,0x4f,0x3d,0xea, + 0x9c,0x48,0xe9,0x81,0x15,0xe2,0xef,0x31,0xb3,0x88,0x98,0xf1,0x04,0x82,0x27,0x30, + 0x38,0x19,0x24,0x6b,0x51,0x22,0x8f,0x55,0xc2,0xdc,0x7b,0x3c,0x1a,0x22,0xce,0xb0, + 0x9f,0x08,0xdd,0x9f,0x40,0x8f,0xb1,0xcc,0xf8,0xfe,0x78,0xb3,0x56,0x07,0x12,0xe7, + 0x80,0xc9,0xc1,0x24,0x03,0x00,0x1c,0x72,0x01,0xa0,0xe0,0xc2,0x39,0xf7,0x83,0x0c, + 0xe6,0x7b,0x66,0x87,0x3c,0xc3,0x55,0xb1,0xc1,0xa5,0x68,0xc1,0xb5,0x78,0xc1,0xbf, + 0x6c,0x31,0x50,0xb6,0x14,0xa2,0x5c,0x09,0xab,0x58,0x89,0xa9,0x36,0xc6,0xd5,0x1a, + 0x63,0xaa,0x57,0xe3,0x6a,0xa0,0x0a,0x2f,0xdd,0x92,0xcf,0x07,0x14,0x4d,0x49,0x5a, + 0xe7,0x57,0xef,0x9d,0xdf,0x1c,0xad,0x05,0x46,0x93,0x31,0x3d,0x23,0xeb,0xf5,0x37, + 0xf1,0xe9,0x88,0xa7,0xcf,0x5c,0x74,0xf3,0x0a,0x0c,0x8f,0x8e,0xcb,0x12,0xe4,0x96, + 0x4a,0x95,0xe4,0xa6,0x9a,0x9e,0x01,0xf5,0xe8,0xc4,0xd4,0x0c,0x54,0xdb,0x59,0x8d, + 0x9e,0xab,0xbf,0x00,0xf4,0x20,0x4c,0x9f,0x91,0x45,0xbe,0x56,0x1d,0x6a,0xef,0xec, + 0x6b,0x6e,0xed,0xac,0xa9,0x6b,0xae,0xa8,0xac,0x92,0xca,0x54,0x92,0x82,0x12,0xa1, + 0x28,0x3f,0x3d,0x53,0x04,0xd7,0xb1,0x70,0x89,0x1e,0x1a,0x1e,0x1d,0x10,0x1c,0xea, + 0xeb,0x8f,0x85,0xd8,0xc5,0xcd,0xd3,0xe9,0x9a,0xdb,0x15,0x27,0x17,0xa8,0xb3,0xe3, + 0x93,0x93,0x83,0xea,0xa1,0xfe,0x81,0x91,0x01,0x35,0xbd,0x4b,0x64,0xa0,0xb7,0x7f, + 0xa0,0xbb,0x6f,0xa0,0x7f,0xb0,0xbf,0xb7,0x7f,0xb0,0xa7,0xaf,0xaf,0xa7,0x77,0x10, + 0x90,0xbe,0x01,0x38,0x8c,0x4f,0x5e,0x76,0x70,0x3c,0x7c,0xe4,0xd8,0x91,0xa3,0x27, + 0x8f,0x1c,0x3d,0x71,0xe4,0xc8,0xf1,0x43,0x47,0x8e,0x1d,0x3a,0x72,0xf2,0x30,0x81, + 0x83,0x87,0x11,0x28,0x7e,0xe8,0xe8,0xc9,0x0b,0x0e,0xce,0xa3,0x63,0x63,0x7d,0xfd, + 0x7d,0x7d,0xfd,0x83,0xdd,0xbd,0xfd,0x7d,0x84,0x15,0xc3,0x90,0x45,0x7a,0xfb,0x60, + 0x0a,0xf1,0x91,0xb1,0x89,0xd4,0xf4,0x8c,0x23,0x47,0x8f,0xe3,0xf2,0xa3,0xc8,0x07, + 0xd8,0x1e,0x3a,0x7c,0xec,0x30,0xc7,0xfc,0xd0,0x11,0x22,0x14,0x06,0x8f,0x73,0x53, + 0x07,0x0f,0x1d,0x07,0x1d,0xce,0x9c,0xbd,0x9c,0x90,0x94,0xdc,0xdc,0xd2,0x32,0x30, + 0x38,0x52,0x59,0x5d,0x2b,0xce,0x2f,0x86,0x0f,0x0d,0x80,0x4c,0x01,0x16,0x5f,0x38, + 0xdb,0x66,0x09,0x73,0xb3,0x45,0x50,0x85,0xf3,0x73,0xf2,0x0a,0x73,0xc5,0xc5,0x70, + 0x65,0x22,0x10,0x89,0x01,0xb2,0x84,0x79,0x50,0x85,0xab,0x6b,0xeb,0xfa,0x07,0x07, + 0x3b,0x3a,0xbb,0x12,0x93,0xd2,0x2e,0x5c,0x74,0x44,0xe9,0xd4,0x84,0xc3,0x27,0x40, + 0x16,0xb5,0x88,0xd1,0x07,0xc7,0x61,0xe4,0x38,0xea,0xc0,0xce,0x82,0x26,0x9c,0xe1, + 0x2e,0x2e,0x6e,0x3d,0x7d,0xfd,0xc4,0xba,0x7e,0x72,0xef,0xca,0x40,0x5f,0xbf,0x9a, + 0x58,0xda,0x4f,0xad,0x66,0x0d,0xc7,0x2e,0x38,0x27,0x33,0x5b,0x40,0xac,0x3b,0x01, + 0x86,0x50,0xfe,0x87,0x18,0xe6,0xe0,0x87,0xe3,0x38,0x8e,0x6c,0x4f,0x10,0xa1,0x27, + 0x39,0x4d,0x50,0xb7,0x23,0xc7,0x4e,0x7c,0x78,0xa6,0x5c,0xae,0xc4,0x4b,0xaf,0x5e, + 0xc6,0xb1,0x0c,0xe7,0xde,0x41,0x4b,0x59,0xe0,0xe4,0x81,0x5e,0x94,0x68,0xa1,0x86, + 0x99,0x86,0x99,0xed,0xeb,0xe3,0x85,0x06,0xf4,0xe7,0xa9,0x8a,0x69,0x40,0x68,0xfa, + 0x21,0x29,0xd4,0xc3,0x23,0x2e,0xae,0xee,0x54,0x37,0x50,0x1b,0x10,0x9e,0xce,0x5c, + 0x0e,0xa0,0xce,0xac,0xc7,0xd0,0x45,0x00,0x18,0xbb,0x23,0x27,0x69,0x7b,0x88,0xa5, + 0xe4,0xec,0x3a,0x70,0x08,0xdc,0x78,0xe2,0xb2,0xa3,0x53,0x1f,0xba,0x4e,0xdd,0xd3, + 0xdb,0xd3,0xdd,0x63,0x61,0x45,0x0f,0x63,0x02,0xf1,0xed,0x00,0xa8,0xd4,0x3f,0x3c, + 0x32,0x2e,0xc8,0xc9,0x39,0x7a,0xec,0x03,0x2a,0x91,0x1f,0x14,0x0a,0x6c,0x9e,0x80, + 0xf4,0x13,0x90,0xae,0x0a,0x55,0x85,0x7a,0x68,0xb4,0xa7,0xaf,0xb7,0xa7,0x77,0x80, + 0x58,0x04,0x86,0x0f,0xd1,0xf4,0xa6,0x6c,0x41,0x22,0xe4,0x7c,0x77,0x4f,0x7f,0xff, + 0xe0,0x30,0x54,0x9a,0x8f,0xcf,0x5e,0x00,0x3f,0x1f,0x3e,0x42,0x93,0x90,0x4b,0x06, + 0xb3,0x20,0x38,0xcf,0xaa,0x87,0x60,0xcb,0xf4,0xf7,0xf6,0xa9,0xf1,0xae,0xc5,0xde, + 0x1e,0x1a,0x6e,0xf4,0x1e,0x2f,0x0a,0x2c,0x0c,0x90,0xbb,0x98,0xcc,0xbb,0xc0,0xa2, + 0x65,0xa3,0xc0,0xee,0xb8,0x81,0x5e,0x42,0x4c,0xa1,0x7f,0x60,0xe0,0xba,0x8b,0xfb, + 0x61,0x1b,0xa7,0xb1,0x1e,0x3e,0x26,0x10,0x8a,0x46,0xc6,0xc6,0x30,0x52,0x7d,0xe6, + 0x6d,0xc5,0x77,0x1d,0xb7,0xef,0xac,0x92,0xd0,0xaa,0xcb,0x53,0x89,0xa6,0x44,0x2f, + 0x86,0x63,0x60,0x00,0x2e,0xba,0x2a,0xab,0x6a,0x93,0x53,0xd2,0xdc,0x3c,0x7c,0x3e, + 0xf8,0xf0,0xf4,0x21,0x46,0x01,0xd8,0xfb,0xf8,0x21,0x60,0xf6,0x36,0x93,0xc0,0x27, + 0x6c,0xe3,0xcb,0xb9,0x0e,0xa2,0x4c,0xf3,0x99,0xd9,0x56,0x87,0x8f,0x1d,0x80,0x1d, + 0x74,0xe4,0x24,0x03,0x87,0x4f,0x1c,0x3c,0x72,0xfc,0xc0,0xe1,0x23,0x07,0x0e,0x1f, + 0x3d,0x48,0xf2,0xfc,0xd0,0x59,0xf7,0x63,0x49,0x63,0xc7,0xd3,0xf0,0x1b,0xd1,0x13, + 0x14,0x32,0xe6,0x68,0x17,0x6a,0x07,0x20,0xff,0xf3,0x96,0xf3,0xba,0x07,0xbe,0xf1, + 0xb5,0x6f,0x7c,0x7b,0xe3,0x87,0xb1,0xc7,0xd2,0xe7,0x76,0xfb,0xd7,0xfd,0xf0,0xd1, + 0x67,0xbf,0xf9,0xbd,0x9f,0x3f,0xf8,0xbd,0xff,0xfc,0xd6,0xf7,0xfe,0xe3,0xdb,0xdf, + 0xfb,0x31,0x41,0xfe,0xfd,0x1f,0x7f,0xf0,0xd0,0xbf,0x3d,0xfa,0xe4,0x73,0x07,0x7d, + 0xde,0x8b,0x1a,0x3e,0x96,0x30,0xf6,0xcb,0xe7,0xdf,0x5d,0x77,0xff,0x03,0xdf,0xf9, + 0xc1,0xcf,0x5e,0x75,0x55,0x1c,0x4f,0x9f,0x07,0x56,0x94,0x1b,0xb6,0xe9,0x00,0x73, + 0x20,0xe8,0x78,0xda,0x1c,0x42,0xfa,0xfc,0x09,0x02,0x47,0xd3,0xf4,0x30,0x7b,0x8c, + 0x10,0x03,0x25,0xab,0x06,0xd3,0x3d,0x46,0x97,0xa4,0xb3,0x4c,0xd2,0x0c,0x74,0x96, + 0xea,0x4c,0xba,0x66,0x56,0x88,0x67,0xcc,0x1d,0x63,0xbb,0xb0,0xf6,0x78,0x3a,0x99, + 0xcd,0x98,0x3f,0x96,0x36,0x4f,0x38,0xcf,0xb1,0x38,0x76,0x8f,0xf1,0xcc,0x67,0x39, + 0xb3,0xde,0xa0,0x0c,0xd9,0x71,0x18,0x39,0x96,0xca,0x9f,0x65,0xbe,0x4c,0xa6,0x5a, + 0x51,0x38,0x9d,0x8d,0xd5,0xf6,0x9c,0x10,0xef,0xaa,0xba,0x90,0x63,0x70,0xc8,0x35, + 0x38,0x88,0x99,0x1b,0xab,0x3c,0x8a,0x16,0xfc,0x4a,0x17,0x03,0x64,0x4b,0xb7,0x54, + 0x2b,0x00,0x51,0xd5,0xc6,0x98,0x1a,0x53,0x5c,0x9d,0x31,0xbe,0xce,0x98,0xda,0xb8, + 0x94,0xda,0x64,0x8c,0xab,0x5e,0x89,0x54,0xce,0x05,0x95,0xeb,0xa2,0xe4,0x93,0x63, + 0xfa,0x4f,0x7e,0x84,0xef,0x3d,0x01,0xf3,0x0b,0x0b,0x91,0x31,0xb1,0xaf,0xbf,0xb9, + 0xfb,0xc0,0xc1,0xc3,0x50,0x02,0xbc,0x7c,0x82,0xa2,0x62,0x12,0xa1,0x70,0x94,0x41, + 0x09,0xae,0xc7,0xfb,0x86,0xfb,0x06,0xd4,0x93,0x53,0xcc,0x17,0xd1,0xfc,0x53,0x30, + 0x94,0x60,0x28,0xca,0x70,0x16,0x86,0xb9,0xb1,0x89,0xe9,0xa1,0x91,0xf1,0xbe,0x81, + 0x61,0x52,0x85,0xbb,0x1b,0x1a,0x5b,0xaa,0x6b,0x1a,0xa4,0xb2,0x8a,0xe2,0xd2,0x72, + 0x71,0x7e,0x89,0x20,0x47,0x02,0x97,0xb5,0x70,0x36,0x8c,0x89,0x4b,0x0e,0x8b,0x8c, + 0x09,0x09,0x8d,0x0c,0xb8,0x11,0xea,0x17,0x18,0x1c,0x78,0x23,0xe4,0x56,0x48,0x74, + 0x50,0x70,0x58,0x00,0x9c,0x91,0x03,0x6f,0x06,0xdc,0xb8,0xe9,0x1b,0x70,0xd3,0xd7, + 0xff,0xa6,0xaf,0xdf,0x0d,0x1f,0xbf,0x20,0x0f,0xdf,0x00,0x6f,0xdf,0x40,0x77,0x6f, + 0x5f,0x0f,0x1f,0x7f,0x68,0x01,0x2e,0x39,0x38,0x02,0x5c,0xb8,0xe8,0x70,0xf1,0xd2, + 0x95,0x4b,0x97,0x29,0x7e,0xe5,0xe2,0x25,0x47,0x80,0x4b,0x0e,0x57,0xf0,0x2d,0x09, + 0x97,0xb0,0x7b,0xd9,0xc1,0x09,0xba,0x1e,0xee,0xfe,0x74,0xad,0x17,0x01,0xca,0x04, + 0x10,0x6f,0x5f,0x7f,0x8e,0x27,0x76,0x01,0xf1,0xf2,0x85,0xeb,0x01,0xe4,0xe9,0xe0, + 0x04,0xed,0xe5,0x2b,0x0c,0x43,0x22,0x08,0xc5,0x01,0xce,0x75,0x39,0x41,0x97,0x2e, + 0x5f,0x61,0x95,0x71,0x72,0xbc,0xea,0x12,0x19,0x13,0xaf,0xaa,0xac,0xee,0xc5,0x3b, + 0x8e,0x47,0xda,0x3b,0x3a,0x6b,0x1b,0xea,0xe5,0xca,0x6a,0xf0,0x61,0x49,0xa9,0xac, + 0xa8,0x44,0x06,0x6d,0x69,0x99,0xac,0x4c,0xaa,0x50,0x56,0x54,0xd5,0xd4,0xd6,0xb7, + 0x77,0x74,0x41,0xbd,0x1e,0x1a,0x1e,0x52,0x56,0xd4,0xc6,0x26,0x24,0x5e,0xbd,0xe6, + 0x02,0x7c,0xcc,0xe2,0x2e,0xa3,0x0e,0x97,0x2e,0x3b,0x71,0x5d,0x2a,0x17,0x46,0xd0, + 0x6a,0x94,0xcb,0xe8,0x73,0xf9,0xca,0x55,0xaa,0x1e,0xb1,0xfa,0x9a,0x9b,0xa7,0x9f, + 0x97,0x6f,0x80,0x97,0xb7,0xbf,0x97,0xb7,0x9f,0xa7,0x8f,0x9f,0xa7,0xb7,0x9f,0x17, + 0x9a,0xe9,0x07,0xe0,0x0d,0xe3,0xbe,0x01,0x68,0xb8,0x17,0x1a,0xee,0xed,0x13,0xe0, + 0x74,0xcd,0x15,0x59,0x5d,0x76,0x74,0x70,0x44,0x26,0x17,0x2e,0x51,0xb9,0x57,0xa9, + 0xa0,0x8b,0x97,0xaf,0x70,0x82,0x38,0xc7,0x5e,0xbc,0x8c,0x0e,0x47,0xb9,0x0e,0x8e, + 0xce,0x2e,0x1e,0x94,0x2d,0x08,0xf2,0x40,0x60,0xfc,0x89,0xae,0x26,0x08,0x1d,0xa1, + 0xb3,0x5e,0x84,0xcc,0xcb,0x3b,0x00,0xe4,0x7a,0xf9,0x50,0x0d,0x03,0x18,0xf5,0xbc, + 0x7c,0x3d,0xbc,0xfd,0x19,0xad,0x7c,0x03,0x3d,0xc8,0x42,0x0f,0xa2,0x3c,0x8d,0x3e, + 0xb2,0xf2,0xc2,0xe8,0xfb,0x80,0xfe,0x5e,0xbe,0x97,0x1d,0xae,0x5a,0x79,0x83,0xea, + 0x0c,0x8a,0x61,0x7a,0x10,0x8b,0xcc,0xae,0x73,0xa0,0x34,0x8e,0xb4,0x4b,0x5a,0xa4, + 0xa4,0x19,0x42,0x1d,0x4b,0x3c,0xec,0x04,0x0e,0xbf,0x7c,0x05,0x1c,0xe8,0xeb,0xee, + 0xe3,0xe7,0xed,0x83,0x6a,0x80,0xce,0x68,0x82,0x0f,0xda,0x88,0x26,0x60,0xaa,0x04, + 0x82,0x02,0xa0,0x39,0xb5,0xf7,0xda,0x75,0x77,0xe2,0x25,0x3b,0xbe,0x82,0x2e,0xfa, + 0xd3,0x81,0x4b,0x4e,0x70,0x97,0x27,0xba,0xcb,0x27,0x90,0x66,0x32,0xe3,0x2e,0x5f, + 0x74,0x02,0xd8,0xe5,0x41,0x62,0x44,0x42,0x86,0x31,0xba,0xee,0x0a,0x9c,0x9d,0x88, + 0x15,0x4c,0x4e,0x02,0x07,0xe4,0xcc,0x13,0xe4,0x74,0xcd,0xd9,0x0b,0xd4,0xf0,0x06, + 0x0d,0xfd,0xdd,0x30,0xa0,0x16,0xbe,0x02,0xb6,0x8c,0xce,0xbe,0x18,0x11,0xda,0xa5, + 0xbe,0xc5,0xae,0x0f,0x33,0xeb,0x41,0x94,0xf1,0xe2,0xf6,0x08,0x5d,0x4b,0x33,0xc7, + 0x9b,0xd9,0x35,0x1e,0x9e,0xde,0x0e,0x8e,0x4e,0xd4,0x0a,0x7e,0x6e,0x70,0x2e,0xbd, + 0xea,0xec,0xea,0x45,0xf8,0x13,0x5f,0x05,0xb2,0xac,0x30,0xb2,0x14,0xa7,0x22,0x08, + 0x67,0x10,0xcd,0x76,0xbd,0x30,0xa0,0x54,0x2b,0x26,0x0d,0x68,0xe6,0x78,0x33,0xca, + 0xf8,0x40,0x32,0x78,0xfb,0xb9,0xb9,0x7b,0xc0,0xe6,0xe2,0xb6,0x24,0xb7,0x17,0x78, + 0x5d,0x6e,0x1b,0x3a,0x92,0xdc,0xa0,0xf9,0x69,0x19,0x5f,0x07,0x92,0x1b,0xcc,0xee, + 0x76,0xa2,0x39,0x70,0x89,0x8d,0x1d,0x6f,0xb3,0x63,0xf2,0xa0,0x2c,0x74,0xb2,0xd3, + 0x25,0x17,0xff,0xb3,0x49,0x5d,0x58,0x20,0x58,0x80,0xaa,0x61,0xd5,0x1e,0x4f,0x18, + 0xfd,0xf5,0xb3,0xbb,0xf1,0x9b,0xe4,0xef,0xfe,0x78,0xeb,0x47,0xa1,0xe7,0xb2,0x34, + 0x67,0x52,0xc6,0x3f,0x4a,0x1e,0x39,0x95,0x3e,0x7e,0x3a,0x65,0xe4,0x64,0xf2,0xf4, + 0x99,0x94,0x51,0xd2,0x9d,0x3c,0x93,0xa5,0xbb,0x22,0x36,0x9c,0x4a,0x1c,0xf8,0xf5, + 0xb6,0x0f,0xd6,0x3d,0xf0,0xf5,0xaf,0x3c,0xf0,0xb5,0x97,0xcf,0x84,0x5f,0x14,0xe2, + 0xe0,0x85,0x5c,0xc3,0xf9,0x1c,0x3b,0xfc,0x2f,0x8b,0xb0,0x42,0xc1,0xc1,0xf0,0x62, + 0x0e,0xc2,0x25,0xd2,0x85,0x41,0x5b,0x35,0xac,0x00,0xb8,0x5d,0xc9,0x63,0x70,0x47, + 0x91,0x8e,0xd2,0xd0,0xb5,0x80,0x5c,0x14,0x19,0x2e,0x91,0xf6,0x32,0x0c,0x92,0x11, + 0xab,0xf6,0x32,0x99,0xe5,0x46,0x40,0x43,0x4a,0x0c,0x08,0x5f,0x0a,0x9d,0xb5,0x0b, + 0x94,0xff,0x05,0x72,0xeb,0x14,0x42,0x1e,0x01,0x52,0x67,0x1d,0x25,0xf8,0x03,0xa2, + 0xab,0x12,0x83,0x5b,0x11,0x82,0x57,0x09,0xd6,0xdc,0x20,0xd9,0xd2,0x4d,0xc5,0x72, + 0xb0,0x72,0x39,0xa6,0xda,0x14,0x5d,0x6d,0x4c,0xa8,0x5f,0x4d,0x6e,0x30,0xa5,0x34, + 0x9a,0x04,0xad,0xcb,0xc2,0x36,0xa3,0xa0,0x75,0x29,0xad,0x69,0x35,0xa9,0x7e,0x25, + 0xb1,0x66,0x21,0x52,0x31,0x17,0xa6,0xd0,0x8d,0x68,0xbf,0xfc,0xba,0xf9,0x39,0x82, + 0x46,0xab,0x87,0x6d,0xb4,0x67,0xef,0xbe,0x13,0x27,0x3e,0x84,0x63,0xa9,0x5f,0x40, + 0x70,0x62,0x4a,0x9a,0x28,0xaf,0xb0,0x5c,0x56,0x51,0xdf,0xd0,0xdc,0xd6,0xd1,0x3b, + 0x38,0x44,0x1f,0x8a,0x05,0xa7,0x60,0xe6,0x5e,0x2c,0x5a,0x82,0x29,0x0e,0x07,0x61, + 0xf2,0x03,0x61,0xa8,0xc2,0x53,0x03,0x43,0x70,0x25,0x3c,0xd4,0xd5,0xd3,0xdf,0xd2, + 0xd6,0x53,0xdf,0xd8,0x5a,0x5d,0xd3,0x04,0x15,0xa7,0xa4,0x54,0x51,0x50,0x54,0x26, + 0xca,0x2b,0x82,0x73,0x5f,0x5a,0x86,0x20,0x25,0x0d,0xff,0xbc,0x0b,0xb5,0x38,0x32, + 0x2a,0x2e,0x22,0x2a,0x2e,0x38,0x34,0x32,0xe8,0x56,0x78,0x70,0x48,0x44,0xe0,0x8d, + 0x5b,0xfe,0x81,0xc1,0x20,0xdd,0xdb,0xff,0x06,0x82,0xdf,0x0d,0x2f,0xbf,0x20,0x2f, + 0xbf,0x40,0x6f,0xdf,0x20,0x2f,0x9f,0x40,0xfc,0xdc,0xf6,0x0b,0x44,0xf0,0x25,0xe0, + 0xc3,0x82,0xb9,0x4b,0x3e,0xdb,0xe1,0x33,0xc7,0x3b,0xc8,0xcb,0x0b,0x3e,0xea,0x83, + 0xb0,0xeb,0x15,0xe8,0xe5,0xcd,0x92,0x51,0x1a,0x4f,0xd2,0x9a,0x97,0x04,0x7a,0xe2, + 0x47,0x1f,0xe2,0x66,0x41,0xbe,0x41,0x0c,0x37,0x0e,0x21,0x94,0x96,0x82,0x08,0xe2, + 0x0d,0x48,0x10,0x59,0x7b,0xc3,0xdf,0x2f,0x24,0x3c,0x2a,0x36,0x2b,0x27,0x4f,0x8e, + 0x3f,0x07,0xee,0x82,0xf3,0x88,0x7a,0x68,0x44,0x3d,0x34,0x4c,0x61,0x68,0x78,0x58, + 0x3d,0x3c,0x0c,0xa7,0xed,0xf6,0x8e,0x6e,0x55,0x65,0x4d,0xb6,0x40,0x1c,0x1d,0x9b, + 0xe0,0x1f,0x18,0xe2,0xcd,0xd7,0x9f,0x11,0x47,0xba,0xf0,0x41,0xe4,0x17,0xc8,0xca, + 0xb5,0x54,0x83,0xd5,0xdc,0x8c,0xfb,0x06,0xc1,0x47,0x37,0x75,0x85,0xa7,0x05,0x01, + 0x4b,0xe6,0x49,0x5a,0xc6,0x2d,0x3c,0xef,0x79,0x06,0xda,0x61,0xcb,0x57,0x83,0xb3, + 0xd7,0xcc,0x99,0x25,0xf3,0xb4,0x8c,0x82,0x95,0x67,0xbc,0x78,0x0e,0xf7,0xe5,0xac, + 0xe3,0xd3,0xb3,0x94,0xbe,0x6c,0xd7,0x8b,0x20,0x74,0xa1,0xa7,0x45,0x8c,0x2c,0x34, + 0x24,0xf1,0x45,0xf0,0x0e,0xb0,0xb1,0x25,0xd0,0xcc,0x93,0x71,0x8b,0x9f,0x59,0x3d, + 0x36,0x6d,0xbc,0x39,0x03,0x09,0x19,0x26,0x0c,0x97,0x12,0x5c,0x82,0x79,0xb1,0xdc, + 0xbc,0x69,0x0a,0x81,0xc4,0x20,0x36,0x49,0x68,0xd0,0x21,0x73,0x7c,0xbd,0xcd,0x46, + 0x05,0x78,0x59,0xc4,0x28,0x80,0x21,0xb6,0x4a,0x57,0x9e,0x5c,0xb3,0xd5,0x36,0x6e, + 0x21,0xd1,0xa4,0x82,0xfc,0x2d,0x6c,0xe4,0x04,0xa1,0x07,0xfc,0xbc,0xfd,0x83,0xd0, + 0x46,0x9f,0xb5,0x7c,0xc5,0x1f,0x21,0xac,0x2c,0xc8,0x02,0xdd,0xe8,0xd6,0x80,0x6b, + 0x21,0x1f,0xa8,0xfb,0x56,0xcb,0xf9,0x09,0xcf,0x3a,0xc4,0x37,0xc0,0x1c,0x38,0xa2, + 0x9e,0xa7,0xb7,0xbf,0x05,0x99,0x97,0x65,0x0a,0xb1,0x31,0x42,0x41,0x5c,0xb0,0xbc, + 0x38,0x13,0xcc,0x3b,0x11,0xc3,0x64,0x65,0x82,0x77,0xa0,0xa7,0x97,0x1f,0xcd,0x58, + 0x44,0xd8,0x90,0x81,0x4b,0xbd,0x7d,0x03,0xbc,0x7d,0x83,0xac,0xdd,0xc2,0xcb,0x40, + 0x5e,0x7c,0xf9,0x1b,0xc7,0x9f,0x11,0xc4,0x7a,0x86,0x61,0xc2,0x12,0xbb,0x99,0x3d, + 0x10,0xe8,0x15,0x70,0xd3,0x33,0xb9,0xca,0xbd,0x68,0xce,0xb3,0x68,0xc1,0xb5,0xd0, + 0x00,0xad,0x5d,0x70,0x2f,0x34,0x7c,0x18,0x5e,0xf3,0xd0,0x2f,0x9f,0x58,0x77,0xdf, + 0x03,0x0f,0x7e,0xfb,0x7b,0x5b,0x8f,0xf9,0x9e,0x4d,0xee,0xb9,0x56,0xa0,0xf7,0x28, + 0x59,0x70,0x29,0xc6,0x55,0x50,0x5f,0xbc,0x8a,0x17,0xdc,0x8b,0x16,0x1c,0x45,0x9a, + 0x23,0x37,0x15,0xbf,0x7d,0xf1,0xdd,0xaf,0x7c,0xf5,0x9b,0x5f,0xff,0xfa,0xb7,0x9e, + 0xdc,0x7e,0xc8,0x39,0x6f,0xca,0xb3,0x78,0xc1,0x8d,0xd0,0x00,0xb2,0x96,0x88,0x3b, + 0x04,0x37,0x16,0xf1,0x28,0x24,0xdc,0x8a,0x2d,0xa6,0xdc,0x59,0x1c,0x6d,0x29,0x5e, + 0x70,0x2d,0xc2,0x9b,0x9a,0xe0,0xbc,0xe9,0x45,0xc8,0xdc,0x88,0xaa,0x5c,0x0b,0xe3, + 0xee,0x64,0x9c,0x9b,0xf5,0x62,0xbb,0x6e,0x45,0x0c,0xd0,0x71,0xae,0x0b,0x6c,0x01, + 0xcc,0xb3,0x44,0x01,0xba,0xd0,0xab,0x98,0xe9,0x02,0xe2,0x0d,0xd5,0x56,0xba,0xe4, + 0x5b,0xbe,0xe4,0x2f,0x5d,0x0a,0x90,0x2e,0x85,0x28,0x96,0xc2,0x94,0xab,0xe1,0xaa, + 0x55,0xa8,0xb9,0x31,0xd5,0xc6,0xd4,0x86,0x65,0xa8,0xb9,0x19,0xcd,0x50,0x76,0xa1, + 0xe6,0x2e,0x8a,0xdb,0x57,0xc5,0x1d,0xc6,0x9c,0xb6,0x25,0x61,0xbb,0x31,0xb3,0xd9, + 0x90,0x54,0xbf,0x14,0x53,0x31,0x17,0xa9,0x9a,0xab,0x1e,0x5c,0xb8,0x87,0x9e,0x76, + 0x75,0x87,0xa0,0x1e,0x1a,0xba,0x70,0xf9,0xca,0xde,0x7d,0xef,0x9c,0xfc,0xf0,0xb4, + 0xe3,0x35,0x97,0xc0,0xe0,0xf0,0xc4,0xe4,0xb4,0x5c,0x71,0xb1,0x54,0x51,0x55,0xdb, + 0xd0,0xd8,0xd9,0x3d,0xd8,0xaf,0x1e,0x1f,0x9b,0xc4,0x2f,0xa2,0xb5,0x3a,0xfa,0xcc, + 0x0a,0xf3,0x77,0xd1,0xe4,0xd6,0x68,0x1d,0xf9,0xa3,0x30,0xbe,0xd9,0x64,0x74,0x7c, + 0x42,0x3d,0x3c,0x36,0xa0,0x1e,0xe9,0xec,0x1e,0x68,0xeb,0xec,0x6e,0x6e,0xed,0xac, + 0x6f,0x6c,0xae,0xaa,0x6d,0x54,0xaa,0xf0,0xe7,0x0f,0xa5,0xe5,0xf2,0x82,0x22,0xfc, + 0x29,0x81,0x50,0x94,0x9f,0x2d,0x14,0xa7,0x65,0xe6,0xa4,0xa6,0x0b,0x53,0xd2,0xb2, + 0x92,0x52,0xd2,0xc8,0x9d,0x2d,0x29,0x31,0x71,0x29,0xb1,0xf1,0x29,0xd1,0xb1,0xc9, + 0x51,0x00,0x31,0x49,0xd1,0xb1,0x29,0x51,0xb1,0x49,0x80,0x20,0xc4,0x26,0x93,0x71, + 0x32,0x48,0xba,0x91,0x31,0x09,0x14,0x28,0x31,0x19,0x64,0xc6,0x01,0x8f,0x8c,0x66, + 0xa7,0xe8,0x08,0xaf,0xe5,0x77,0xcd,0x23,0xdc,0x20,0xb2,0x4a,0x24,0x48,0x22,0xc3, + 0x16,0x90,0xd8,0x24,0xbc,0xa1,0x8b,0x21,0x48,0x24,0x5a,0x25,0x46,0x46,0xb3,0x23, + 0x64,0x36,0x26,0x9e,0x72,0x4b,0x04,0x13,0xc0,0x9c,0xd4,0x74,0x41,0x96,0x20,0x57, + 0x20,0xca,0x15,0xe4,0xe4,0x66,0x66,0x8b,0x92,0xd3,0xb2,0x12,0x93,0xd3,0xc1,0xc0, + 0xe8,0xb8,0x04,0xc2,0x3f,0xde,0x5a,0x19,0x9e,0x09,0xec,0x14,0x23,0x88,0x55,0x83, + 0x67,0x20,0x75,0x11,0xeb,0x1c,0xce,0x15,0xb6,0x96,0x5a,0x4d,0x31,0xe3,0x51,0x09, + 0x1c,0x2b,0x76,0x9c,0x31,0xd0,0x46,0x8d,0x78,0xea,0x0d,0x4b,0x55,0xad,0x19,0x52, + 0x25,0xad,0x3c,0x6c,0xe5,0x49,0xce,0x22,0x3e,0x2b,0xbb,0x4a,0xda,0x1a,0x62,0x25, + 0x88,0x70,0x8b,0xb7,0xf6,0x55,0x34,0xdf,0x15,0x89,0x56,0x06,0xda,0xb4,0x68,0x2f, + 0xdf,0x96,0xb5,0xc0,0x42,0x2e,0x89,0x2f,0x08,0x8a,0x64,0xbb,0xfc,0x28,0x30,0xa9, + 0x12,0x63,0x11,0x5f,0x86,0x38,0x36,0x39,0x22,0x2a,0x9e,0x6f,0xfe,0x5a,0xde,0xa0, + 0x94,0xb7,0x0f,0x37,0xe3,0x81,0xe8,0x04,0xce,0x5e,0x5b,0x5f,0xd9,0x06,0xd4,0x92, + 0x80,0xaf,0x55,0x82,0x45,0x7a,0xaf,0xed,0x76,0x7b,0x39,0x99,0x68,0xe9,0x2e,0x7b, + 0x19,0x4b,0x76,0x0a,0xab,0xa7,0x79,0x3b,0x5b,0xa7,0x90,0xdd,0x1d,0xca,0xc5,0x9a, + 0xf5,0x46,0x74,0xbc,0x85,0x81,0xfc,0x80,0xb2,0x42,0x13,0x58,0x8b,0xe2,0xa3,0x2c, + 0x37,0x8e,0x65,0x4e,0xf2,0xf5,0x64,0xb6,0x03,0xde,0xbe,0x18,0x97,0x12,0x92,0x5d, + 0x15,0xa2,0x5c,0x8a,0x50,0x1a,0x6e,0x29,0xf0,0xe6,0x9f,0x10,0xd5,0x2a,0x03,0xca, + 0x15,0x04,0xb6,0x1b,0x0a,0x53,0x8a,0xe5,0x4b,0x31,0x35,0x8f,0x3d,0xb1,0xfe,0x81, + 0xfb,0x1e,0x78,0x60,0xdd,0x57,0x1f,0xfa,0xd5,0xe3,0xaf,0x9f,0xf4,0xbe,0x10,0x26, + 0xbf,0x2e,0x18,0xf6,0x2d,0x9c,0xf2,0x92,0x4c,0x5e,0x4b,0xef,0x3d,0xe6,0x23,0x7a, + 0xe1,0xad,0xd3,0xff,0xf2,0xfd,0xff,0xb8,0xef,0x1f,0xd6,0x7d,0xed,0xeb,0x0f,0x6e, + 0xdd,0xfb,0xb1,0xa7,0x64,0x92,0xb2,0xa5,0xfc,0xf9,0x22,0x42,0xed,0x09,0xba,0x4d, + 0x97,0x2e,0x8f,0xa8,0x40,0x84,0x8e,0x73,0x0c,0x43,0x2b,0x56,0xad,0xc8,0xf8,0x88, + 0x15,0x31,0xd7,0xa5,0x34,0x76,0x67,0x81,0x21,0xf2,0xa4,0x04,0x96,0x3c,0xa1,0x0d, + 0x92,0x2f,0x73,0xe6,0xf0,0x81,0xaa,0x01,0x1a,0x46,0x54,0x02,0x18,0xa3,0xab,0x10, + 0xa0,0xe0,0x26,0xd5,0x2d,0xa5,0x36,0x99,0xd2,0x9a,0x56,0x32,0x9a,0x8d,0xa2,0xd6, + 0x15,0x51,0x9b,0x29,0xaf,0x7d,0xb5,0xb0,0xcb,0x98,0xdf,0x6d,0x2a,0xe9,0x31,0x15, + 0xf7,0x98,0xf2,0x3b,0x8d,0x79,0x9d,0xc6,0x9c,0x56,0xa8,0xcb,0xcb,0x09,0xd5,0x0b, + 0xe1,0xca,0x45,0x55,0xef,0xea,0xf2,0xbd,0xf0,0x9e,0xc1,0xbb,0x05,0xe3,0xff,0x35, + 0xb6,0xb6,0x77,0x1c,0x3f,0xfe,0xc1,0xbb,0xfb,0x0f,0x7c,0xf0,0xd1,0x99,0x6b,0x2e, + 0x1e,0x81,0xb7,0xa0,0x04,0xa7,0xe7,0x8a,0x8b,0xe0,0x14,0x5c,0x5b,0xdf,0xd0,0xda, + 0xde,0x83,0xcf,0x6d,0x18,0x9f,0x9a,0x9a,0x86,0x53,0x30,0x79,0x30,0xd0,0xfc,0x3c, + 0xbf,0x0a,0x03,0x40,0x15,0xd6,0x68,0x75,0x70,0x16,0x9e,0x9a,0xd6,0x8e,0x8e,0x4f, + 0x0e,0x8f,0x8e,0x91,0xd7,0x27,0xf5,0x77,0xf7,0xf6,0xc1,0x21,0xba,0xa9,0xa5,0xbd, + 0xae,0xa1,0xad,0xa6,0xb6,0x5e,0x55,0x59,0xaf,0xac,0xa8,0x96,0x29,0x94,0x65,0xe5, + 0xca,0x92,0x72,0x79,0x71,0xa9,0x54,0x52,0x50,0x9a,0x5f,0x50,0x2c,0x96,0x14,0xe7, + 0x8a,0x0b,0xe1,0xdc,0x2d,0xcc,0x15,0x0b,0x73,0x25,0x39,0xb9,0xf9,0x82,0x9c,0xbc, + 0xec,0x1c,0xb1,0x50,0x24,0x16,0xe5,0x61,0xb1,0x86,0x71,0x41,0x0e,0x82,0x30,0x97, + 0x8e,0xe7,0x01,0xb0,0x23,0xe2,0x6c,0x82,0x64,0x0b,0xf3,0x04,0x22,0x32,0x4b,0x68, + 0xb0,0x9b,0x23,0xce,0x12,0x88,0xe9,0x5f,0x5d,0x85,0xa4,0xcd,0xc9,0x2d,0xa0,0x9c, + 0x05,0x84,0x09,0x19,0x97,0x08,0x72,0x24,0xd0,0x66,0x09,0xb0,0x4b,0x56,0x41,0x37, + 0x9f,0xe0,0xb0,0x04,0xbb,0xa0,0x0f,0x8c,0x13,0xad,0x80,0x58,0x9c,0x93,0x57,0x80, + 0x1c,0x44,0xa8,0x6a,0xb6,0x50,0x22,0x60,0xa4,0x8b,0x29,0x67,0x10,0x81,0xd2,0x09, + 0x01,0x0c,0x66,0xe7,0x10,0x0e,0x79,0x05,0xa8,0x09,0x0a,0x45,0x73,0xa8,0x81,0x22, + 0x1c,0xcc,0xa3,0xe3,0x84,0x3e,0x8f,0xf2,0xa1,0xea,0x31,0x20,0xa2,0x7c,0xf2,0xa8, + 0x39,0xb4,0xcb,0x20,0x66,0x1a,0x9c,0x42,0x9e,0x38,0x2b,0x41,0x27,0x10,0x62,0xa1, + 0xa8,0x80,0xf8,0x07,0x34,0xcc,0x47,0x07,0xd2,0x71,0x11,0xd5,0x30,0x8f,0xf5,0x86, + 0x7d,0x41,0xe8,0x55,0x62,0x32,0x75,0x02,0x8d,0x05,0x99,0x25,0x1e,0x13,0x81,0x63, + 0xf3,0x72,0xf2,0xc4,0xac,0x2d,0x12,0xc6,0x52,0xe4,0x99,0x9f,0xcd,0x06,0x85,0xf2, + 0x67,0x14,0xa3,0x6e,0x27,0xac,0xd8,0x08,0xe6,0x53,0xd1,0xd4,0x63,0x8c,0x32,0x18, + 0xf1,0x82,0x6c,0x7b,0x5a,0x51,0x13,0x04,0xf8,0xb7,0xf5,0x7c,0xe2,0x46,0x26,0xbe, + 0x64,0x9c,0xcf,0x59,0x42,0xc3,0xc4,0x31,0xe7,0x3c,0x46,0xe5,0x42,0xc8,0x70,0x39, + 0xe1,0x93,0x2d,0xcc,0x25,0x16,0x15,0xb0,0xa6,0x59,0x68,0xc5,0x86,0x8c,0xf1,0x12, + 0x2c,0x01,0x1a,0x9a,0x90,0x34,0xc1,0xf8,0xbe,0x22,0x6b,0x25,0xd4,0x39,0xd6,0x9e, + 0x44,0x59,0x12,0x22,0x17,0xf9,0xa0,0x81,0x42,0xd6,0x1b,0x42,0x92,0x45,0x9c,0xa5, + 0x39,0xe2,0x5c,0x71,0x01,0xe1,0xc6,0xa4,0x28,0x97,0x57,0x44,0x07,0xde,0x2a,0x91, + 0x84,0x4d,0x15,0x9a,0xf3,0x94,0x83,0x84,0x28,0x99,0xc7,0x0f,0x2b,0x3f,0x46,0xe8, + 0x40,0xd4,0x13,0xe9,0x61,0x90,0xf8,0x2a,0x9f,0xba,0x4e,0xc0,0xd8,0x8e,0xb9,0x4a, + 0x39,0xb3,0xd2,0x99,0x9d,0xc2,0xe8,0x6c,0x56,0x00,0xe9,0x99,0x0c,0x21,0x9e,0xcf, + 0xe6,0xfb,0x1c,0xd3,0x9e,0x31,0x9f,0xda,0x0b,0xba,0x91,0x5d,0x4c,0x93,0x90,0xee, + 0x26,0x76,0xf3,0xd2,0xbd,0xc6,0x25,0x83,0x90,0xb3,0x88,0xc4,0x5d,0x44,0xf3,0x87, + 0x11,0x41,0x73,0x98,0x68,0x45,0xf7,0x29,0x7f,0xc3,0xd2,0x8c,0x35,0xef,0x5f,0x9a, + 0x93,0x6c,0xcb,0x24,0x09,0xbb,0x91,0x25,0xac,0x21,0x6c,0x32,0xe4,0xe4,0xa5,0x17, + 0xd6,0xa6,0xd4,0xce,0x27,0xd6,0x9b,0x92,0xea,0x8d,0xc9,0x8d,0xab,0x49,0x0d,0x46, + 0xc0,0x29,0x24,0x10,0x30,0x77,0xeb,0x8c,0x09,0xa4,0x0d,0x12,0x75,0xec,0x78,0xff, + 0xdc,0x3f,0x7d,0xef,0x87,0x70,0x10,0xfe,0xca,0x57,0xbe,0xfe,0x9d,0xef,0xfc,0xeb, + 0x4f,0x7f,0xf6,0xe8,0x4f,0x1e,0xf9,0xc3,0xcf,0x1f,0xfd,0xdd,0x0f,0x7e,0xf2,0xd0, + 0x37,0x1f,0xfc,0xce,0xba,0x75,0x5f,0xf9,0xca,0x57,0xbf,0xf1,0xd0,0x23,0xbf,0x3f, + 0x7e,0x2d,0x22,0x42,0xaa,0x49,0x6b,0x5a,0x86,0x85,0xc0,0x39,0xbd,0x11,0x11,0xe8, + 0x26,0xf2,0xd8,0xda,0x11,0xb4,0x76,0x97,0xbf,0x9c,0x0e,0x52,0x9d,0x93,0x2c,0x67, + 0x53,0x1b,0x57,0x12,0x89,0x21,0xd8,0x6d,0x30,0xa6,0x36,0xad,0x24,0x70,0xb3,0x6c, + 0x97,0x6a,0x45,0x5b,0x0a,0x9c,0xf9,0x74,0x90,0x53,0x80,0xf2,0xe4,0xd4,0x00,0x9a, + 0x94,0xc6,0xd5,0x54,0x62,0x4b,0x4a,0xfd,0x52,0x7c,0xed,0x2a,0xe7,0x1c,0x90,0x0b, + 0xb3,0x80,0xa4,0x37,0xc1,0x31,0x16,0xab,0xad,0xb0,0xd5,0x28,0x6c,0x35,0x09,0xda, + 0x4c,0xa2,0x76,0x93,0xa4,0xc3,0x24,0xe9,0x36,0x42,0xa9,0x2d,0xeb,0x35,0x96,0xf5, + 0x9a,0x64,0xfd,0x26,0x69,0x9f,0xa9,0xbc,0x0f,0xdb,0xa2,0x1e,0x93,0xa4,0xcb,0x94, + 0xd7,0xb6,0x22,0x68,0x5d,0x49,0xac,0x5d,0x8c,0x52,0xe9,0x4b,0xba,0x16,0x0d,0xf7, + 0xce,0x7b,0x16,0xee,0x16,0x56,0x4d,0xab,0x32,0xb9,0xe2,0x9d,0x77,0x0f,0xec,0x7b, + 0xe7,0xe0,0x99,0xb3,0x17,0x5c,0xdc,0xbc,0x6f,0x86,0x86,0x27,0xa5,0x64,0xc0,0x29, + 0xb8,0x54,0xaa,0xac,0xa9,0x6b,0x69,0xeb,0xec,0xe9,0x85,0x63,0xed,0xd8,0x14,0x7d, + 0x41,0x03,0x3e,0xc5,0x51,0xaf,0xb7,0x2a,0xc1,0x70,0x30,0x26,0x8f,0xac,0xd4,0x92, + 0xbb,0xb3,0x66,0xc9,0x1b,0x0c,0x47,0xa0,0x0a,0x0f,0x0e,0x8d,0xf6,0x0d,0xa8,0xbb, + 0x7a,0xd4,0xed,0x9d,0xdd,0xed,0xf8,0x28,0x9b,0xae,0xc6,0xa6,0xb6,0xba,0x86,0xd6, + 0xea,0xda,0xfa,0xaa,0x9a,0x86,0x4a,0xf2,0x93,0x1c,0xa5,0xaa,0x56,0xa5,0xc2,0x1f, + 0xdd,0x2b,0x54,0x95,0x52,0x7c,0x14,0x43,0xa5,0x4c,0x21,0x97,0xca,0x95,0x00,0xe5, + 0x72,0x39,0xfe,0x5a,0x5f,0x26,0x23,0xc0,0x74,0xcb,0x64,0x52,0x80,0x72,0x99,0x1c, + 0x46,0xa4,0x0a,0x65,0x69,0x39,0x99,0x95,0x2b,0xe4,0x0a,0x45,0x99,0x54,0x8e,0xb3, + 0x52,0x05,0xe9,0x2a,0x71,0x09,0x5d,0x28,0x83,0x71,0x98,0x55,0x92,0x85,0x2a,0x5c, + 0xcb,0xb2,0x82,0x59,0xb9,0x42,0x25,0x95,0xc9,0x41,0x6e,0x69,0x39,0xce,0xc2,0x72, + 0x20,0x96,0xe2,0x23,0x2c,0xa4,0xe4,0xb1,0x00,0x0a,0xa0,0x07,0x02,0x64,0x2b,0xa3, + 0x3c,0x51,0xae,0x14,0x15,0x40,0x3d,0xc9,0x78,0x05,0x61,0x58,0x51,0x8e,0x7c,0x80, + 0x40,0x05,0x5a,0x95,0x49,0x65,0x32,0x5c,0x5b,0x21,0x67,0x95,0x24,0x94,0x0c,0x67, + 0x54,0x15,0x04,0x11,0x55,0xd1,0x52,0x62,0x0e,0x37,0x42,0x65,0x41,0x4b,0x95,0xa4, + 0x04,0x44,0xab,0x4a,0x86,0x46,0x46,0xfc,0x83,0x34,0x52,0xb4,0x8b,0xd1,0xad,0xa2, + 0x0c,0x69,0xa1,0xcb,0x39,0x87,0x5a,0x84,0x5a,0x11,0x1a,0x19,0x27,0x05,0xac,0xb6, + 0x75,0x0e,0x27,0x08,0x57,0xc9,0x2c,0xbc,0x41,0xed,0xa5,0x0b,0x29,0x2b,0x30,0x90, + 0xa8,0x2a,0x27,0x16,0xc1,0x94,0x92,0xf8,0x4a,0xc6,0x2a,0x46,0x65,0xc9,0xcd,0x6e, + 0x67,0xec,0x52,0x41,0x7c,0xa9,0xbd,0x7c,0x7d,0x28,0x31,0xd0,0x80,0xaf,0xa4,0x0a, + 0xbe,0xbd,0x72,0x6a,0x8e,0x4c,0x01,0x5d,0x05,0x55,0xc3,0x2a,0xbe,0x2c,0x07,0xd4, + 0x99,0x58,0x2a,0xe7,0x22,0x45,0x81,0xb8,0x48,0xc9,0x59,0x04,0x1c,0x64,0x0a,0xc6, + 0x22,0x7e,0x5e,0xb1,0x5e,0x85,0xd9,0x0a,0xf3,0x72,0x39,0x89,0x11,0xe6,0x80,0x92, + 0x04,0x8b,0x11,0x64,0xdf,0x57,0x52,0x25,0x13,0x32,0x85,0x92,0xe4,0x30,0x2c,0x64, + 0xb4,0xe2,0xfc,0xcc,0xc5,0x9a,0xa4,0x22,0xa6,0x4a,0xb9,0x9c,0x71,0x9a,0x14,0x95, + 0xc7,0xac,0x23,0xae,0xe0,0xb4,0xe2,0x65,0x2c,0x99,0x95,0x11,0x7d,0x20,0x63,0x09, + 0x67,0x42,0x0c,0x3a,0x93,0x18,0x49,0x15,0x66,0xc7,0xda,0xc4,0x48,0xca,0x85,0x9b, + 0xd3,0x99,0x84,0x4c,0x49,0x93,0x84,0x78,0x89,0xea,0x86,0x3e,0x21,0xaa,0x82,0x4a, + 0x72,0x2e,0x3f,0x69,0x8c,0xa4,0x0a,0xc6,0x57,0x5c,0x14,0x48,0x7a,0xf3,0xc2,0xc1, + 0x73,0x0e,0xc7,0x0a,0x16,0xd2,0x08,0xf2,0xd5,0x20,0x22,0x50,0x49,0xa0,0x67,0x59, + 0x99,0x33,0x56,0x46,0x77,0xb4,0x94,0x91,0x4b,0xd3,0x9b,0xef,0x1c,0xbe,0x27,0x49, + 0xa2,0x32,0x51,0x90,0xe2,0xa6,0xae,0xa4,0x21,0x23,0x79,0x8e,0x41,0x91,0x92,0xdd, + 0x2a,0x63,0xed,0x25,0x5d,0x15,0xb1,0x02,0xa3,0x50,0xac,0x6c,0x14,0xb5,0xe8,0x0b, + 0x3b,0x4d,0x92,0x76,0x63,0x7e,0x97,0x49,0xdc,0x6e,0xcc,0xed,0x34,0x41,0x17,0x5a, + 0x7b,0xdd,0x15,0x20,0x83,0x6e,0x1e,0x40,0xa3,0xe1,0x6a,0x54,0xee,0xb6,0x1d,0x87, + 0xbf,0xff,0xe3,0x9f,0xdd,0x7f,0xdf,0x03,0xf7,0xfd,0x9f,0xfb,0x38,0x78,0xf0,0xc1, + 0x6f,0x3f,0xfc,0xe8,0x6f,0xf6,0x9f,0x72,0x0d,0xcf,0x69,0xcc,0xe9,0x58,0xc9,0xeb, + 0x32,0x15,0x74,0x18,0xf3,0x3a,0x4c,0x00,0x05,0x5d,0xab,0x79,0x04,0x47,0x9e,0x1d, + 0x58,0x71,0x80,0xa1,0xa8,0xf3,0xee,0xba,0xa0,0x15,0x00,0xed,0x52,0x25,0x45,0x54, + 0x25,0xc2,0x16,0xba,0x05,0x30,0x88,0xb2,0x4c,0x56,0x82,0x28,0x31,0x7f,0x56,0xdc, + 0x85,0x00,0xb3,0xf9,0x5d,0x26,0xfe,0x2c,0x15,0x91,0xd3,0x8e,0xab,0xf8,0xb3,0xe8, + 0x87,0x36,0xa3,0x84,0xcc,0x72,0x6b,0xd1,0xb4,0x4e,0x53,0x4e,0xc7,0x2a,0xa8,0x41, + 0x01,0x88,0xf3,0x3a,0x57,0x0b,0xba,0xb0,0xd4,0x96,0xf6,0x18,0x01,0x8a,0x7b,0xb1, + 0xce,0x96,0xb1,0xd5,0x56,0x35,0x88,0xa0,0x18,0x60,0x00,0xab,0x70,0xaf,0xa9,0xa0, + 0xcd,0x98,0xdd,0xb2,0x92,0x54,0xbf,0x12,0xa1,0xd0,0x0b,0x9a,0x97,0x75,0x8b,0x5f, + 0x7e,0x95,0xfc,0xa2,0x41,0x24,0x29,0xdc,0xf7,0xce,0xbb,0xfb,0xdf,0x3b,0xf4,0xe1, + 0x47,0xe7,0xae,0xba,0x78,0xfb,0xdf,0x08,0x8f,0x4f,0x4c,0x11,0xe5,0x15,0x95,0x94, + 0x49,0x2b,0x6a,0xea,0x9a,0x5b,0x3b,0xbb,0x7b,0x07,0xd5,0xc3,0xf8,0x64,0x27,0xf2, + 0x74,0x0e,0x8b,0x3b,0xb2,0x2c,0x6f,0x90,0x36,0xc0,0x2c,0x79,0x76,0x34,0x3e,0x5f, + 0x11,0x88,0xc7,0xc6,0xa7,0x47,0x46,0x27,0xd5,0xc3,0xe3,0xfd,0x83,0x50,0x8b,0x87, + 0x7b,0xf0,0x3e,0xc9,0x81,0x8e,0xae,0x81,0xb6,0x8e,0x6e,0xa8,0xec,0x2d,0x6d,0xdd, + 0xcd,0xad,0x1d,0x4d,0x2d,0x1d,0x8d,0x2d,0x1d,0x80,0x34,0x36,0xb7,0x37,0x35,0xb7, + 0x34,0x34,0x01,0xd2,0xd6,0xd0,0x04,0xd0,0x5e,0xdf,0xd0,0x04,0x2d,0x85,0xfa,0xc6, + 0x36,0x80,0x3b,0xef,0x36,0x34,0xb6,0x7e,0xea,0xb5,0x6b,0x77,0xdb,0xd6,0x98,0x65, + 0x15,0xfe,0xdc,0x04,0xfd,0x2f,0xb1,0xf7,0xce,0xba,0x28,0xba,0xe3,0xcb,0x35,0xff, + 0xf3,0xd1,0xaa,0xb1,0x85,0x09,0xe5,0xe7,0x60,0xd1,0x5a,0xa9,0xc2,0x75,0x5b,0x69, + 0xce,0x7c,0xa9,0xe1,0xb6,0x55,0xf2,0x33,0x69,0xf5,0x85,0x25,0xf0,0x5d,0x69,0xc5, + 0x27,0x26,0x6c,0x79,0x9c,0x89,0xc9,0xf8,0x21,0x03,0xb1,0x6e,0x22,0x9f,0x33,0x8d, + 0xad,0xdd,0xb2,0x01,0x13,0x05,0xa8,0x02,0x70,0x1c,0xe3,0xba,0x77,0x02,0xca,0x41, + 0x58,0xb2,0x5a,0xd0,0x30,0x15,0x2e,0xac,0x70,0x0a,0x4e,0xf9,0xf8,0x7a,0xf0,0x39, + 0xd7,0x10,0xaf,0x88,0x9c,0xc4,0x82,0xb6,0xa2,0x36,0x03,0xad,0x2c,0x77,0xc5,0xf0, + 0xaf,0x03,0xd2,0x7e,0xb3,0xbd,0x14,0x97,0x71,0x6d,0xbf,0x05,0x59,0xd5,0x10,0x8e, + 0x00,0xa5,0xbc,0x1f,0x81,0x9b,0xb5,0xeb,0x2b,0x24,0x63,0x71,0xd5,0x90,0x49,0x0e, + 0x15,0x56,0x6d,0xaa,0x18,0xc2,0xf1,0x9a,0x61,0x64,0x55,0x3b,0x62,0xaa,0x1f,0x65, + 0x00,0xba,0x00,0x95,0x6a,0x6c,0xa1,0xf8,0x96,0xf4,0xe0,0x15,0x8e,0xa0,0x75,0x39, + 0xa9,0xd6,0x10,0xaa,0x5a,0xc9,0x6c,0x34,0x68,0xe6,0xef,0xe1,0x47,0x6d,0xdc,0x39, + 0xe8,0x0d,0x0b,0xd9,0xc2,0xbc,0x77,0xdf,0x3b,0xf0,0xfe,0xfb,0x87,0x4e,0x7f,0x7c, + 0xc1,0xd9,0xd5,0x2b,0x30,0x28,0x38,0x2e,0x21,0x35,0x3b,0x27,0x37,0xbf,0xa8,0x4c, + 0xa6,0xac,0x83,0x2c,0xed,0xec,0x1e,0xe8,0x1f,0x1c,0x1e,0x19,0x9b,0x1c,0x9f,0xa4, + 0x3f,0x4d,0x82,0x2a,0x6c,0xa7,0x04,0xd3,0xbb,0xb3,0xe8,0x2f,0x95,0xc8,0x3d,0x5a, + 0x1a,0x38,0x17,0x4f,0x4e,0xcf,0x4c,0x4e,0x4d,0x4f,0x4c,0x4d,0xc3,0x72,0x38,0x17, + 0x93,0xa3,0xf1,0x48,0xff,0xe0,0x08,0x79,0xfe,0x2d,0x3e,0xfe,0x17,0xea,0x7b,0x4f, + 0xff,0x70,0x37,0xfe,0x3a,0x43,0xdd,0xd5,0x0b,0x35,0x5a,0x8d,0x23,0x7d,0x4c,0x4b, + 0x81,0x0c,0xaa,0xef,0xa6,0xfb,0x59,0xd6,0xda,0xef,0x76,0x33,0xba,0x59,0xcf,0x72, + 0x83,0x9f,0x97,0xa0,0xff,0x25,0xf6,0xde,0x71,0x17,0x22,0x38,0xf0,0x65,0x9b,0xff, + 0xf9,0x68,0xc5,0x8f,0xe9,0x17,0x91,0x2a,0xfc,0x2e,0xb9,0x6b,0x71,0xe0,0x53,0x87, + 0x9b,0x27,0xeb,0x36,0x6a,0xdc,0xb5,0x92,0x54,0xab,0x2f,0x23,0x9f,0x6f,0x97,0xc0, + 0x77,0xa5,0x15,0xeb,0x58,0xf2,0xc1,0x02,0x38,0xf3,0x61,0xd2,0x4f,0x08,0xf0,0x4e, + 0x51,0x6a,0x38,0x20,0x3d,0x83,0x63,0xad,0x23,0x0b,0x50,0x0b,0xea,0x48,0x45,0x68, + 0x00,0x84,0x57,0x20,0xee,0x04,0x1a,0xc6,0x58,0x84,0xb4,0xb0,0xbc,0x7a,0xd8,0xd4, + 0x34,0xba,0x0a,0x2d,0x1d,0xac,0xb9,0x4b,0x86,0x9f,0x1d,0xea,0x58,0x73,0xea,0xd6, + 0x98,0x6d,0x1c,0x47,0x3d,0xeb,0xa8,0xbd,0xa3,0x0c,0x6e,0x4b,0x46,0xcd,0x01,0x1a, + 0x28,0x9a,0xfc,0xba,0x49,0xf9,0xe3,0x38,0x0f,0x1a,0xc6,0xb1,0x45,0x02,0x70,0xc8, + 0x38,0x76,0x1b,0x27,0x10,0x07,0x04,0x5c,0x04,0xd0,0x44,0x90,0x96,0x09,0x53,0x23, + 0xe0,0x13,0x66,0x6e,0x15,0x6a,0x2c,0xeb,0x45,0x3d,0xa6,0x82,0xf6,0x55,0x61,0xeb, + 0x62,0x4a,0xfd,0x42,0x58,0xc5,0x52,0x7a,0xc3,0xfc,0x88,0xe6,0x6f,0xe4,0xd7,0x46, + 0x77,0x02,0x46,0x93,0xa9,0x5c,0x2a,0x3f,0x75,0xfa,0xe3,0xf7,0xdf,0x3b,0x70,0xea, + 0xd4,0xc7,0x8e,0x57,0x5d,0x03,0x02,0x83,0x23,0xa3,0x93,0x32,0xb2,0x72,0x24,0x05, + 0x25,0xe5,0x72,0x25,0x9e,0x83,0xf1,0x21,0xd1,0x83,0x83,0x43,0xe3,0x63,0x13,0xd3, + 0xdc,0xfb,0x82,0xf1,0x30,0x6c,0xef,0x2c,0xcc,0xfe,0x5e,0x58,0x4f,0xde,0xe3,0x00, + 0x87,0x62,0x1d,0xbd,0x53,0x0b,0x60,0x6a,0x1a,0x61,0x62,0x72,0x66,0x7c,0x62,0x0a, + 0xda,0xd1,0xf1,0xa9,0xd1,0xf1,0x99,0x61,0x6c,0x27,0xf1,0x3e,0xae,0xd1,0x89,0x91, + 0x31,0x80,0xa9,0xe1,0xd1,0xc9,0xe1,0xd1,0x89,0x4f,0x0d,0x23,0x63,0xd3,0x9f,0x65, + 0xb9,0x3d,0x98,0x24,0x5a,0xd9,0x9d,0xfa,0xac,0xda,0x7e,0x76,0xf8,0x02,0xec,0xbd, + 0x67,0xa4,0x7f,0xae,0x5a,0x4d,0x0e,0x8d,0x40,0x34,0xa7,0xd4,0xc3,0x9f,0x25,0xa0, + 0x94,0xc9,0x17,0xe8,0x37,0x58,0xa8,0x1e,0xfe,0x64,0xb2,0xa1,0x91,0x4f,0xa7,0xe4, + 0xf4,0x6d,0x17,0x7e,0x59,0xc1,0xba,0x0b,0xad,0x28,0xb7,0x21,0xb2,0x31,0xd5,0xa3, + 0x0c,0x67,0xf8,0x78,0x61,0xdd,0x32,0xae,0x1e,0x9d,0x1a,0x1c,0xd7,0xf4,0x4d,0xad, + 0xf6,0xcf,0x98,0x00,0x7a,0xa6,0x4d,0x14,0xe9,0x9b,0x32,0x52,0xe4,0x0e,0xa1,0x17, + 0x96,0xdc,0x0d,0xfd,0x5f,0x03,0x66,0x79,0x60,0x77,0x96,0xe8,0xdc,0xcb,0xb6,0x76, + 0x4d,0xa0,0x83,0xd4,0x2d,0x9c,0x73,0x38,0x5f,0xd1,0x55,0x5d,0xd3,0x0c,0x74,0x4c, + 0x9b,0x3a,0x09,0x02,0x53,0xdd,0xd3,0xe6,0x71,0x0e,0x3a,0xc9,0x54,0xfb,0x94,0xa9, + 0x75,0xd2,0xd4,0x31,0x89,0x55,0xb8,0x79,0xcc,0x48,0x8f,0xc0,0x70,0xf2,0x2d,0xeb, + 0x35,0xe5,0x77,0x18,0x33,0x5b,0x96,0xd3,0x1a,0xe6,0x43,0x54,0xab,0x65,0x9d,0x8b, + 0x5a,0xc3,0x97,0x5f,0x13,0xff,0xca,0xb0,0x6a,0x5a,0xed,0xea,0xe9,0xb9,0x76,0xfd, + 0xfa,0x81,0x83,0x87,0x8f,0x9f,0xfc,0xd0,0xc1,0xe9,0xba,0xa7,0x4f,0x60,0x68,0x64, + 0x4c,0x72,0x6a,0x86,0x50,0x24,0x29,0x2c,0x91,0x2a,0x2a,0x6b,0xea,0x1a,0x5b,0xda, + 0x3a,0x7a,0xe0,0xd2,0x71,0x60,0x18,0x8b,0xd1,0xe4,0xf4,0x2c,0xd4,0x53,0x38,0x0b, + 0x6b,0x75,0x73,0x5a,0xdd,0x3c,0x77,0x77,0x16,0xf7,0x37,0x62,0xfa,0x10,0x4b,0xf2, + 0x1a,0x82,0x39,0x72,0xa7,0x96,0x16,0xca,0x31,0x7d,0xb9,0x21,0x2c,0x24,0x88,0x0e, + 0x6a,0xf1,0xf4,0x8c,0x66,0x7a,0x56,0xcb,0x8d,0xc3,0xf9,0x9a,0xb4,0xf8,0xac,0x8f, + 0xe9,0x59,0xa8,0xdd,0x1a,0x7c,0xa3,0x81,0x46,0x47,0xde,0x6b,0x00,0x83,0x1a,0xac, + 0xe6,0x58,0xd0,0x67,0x09,0x0d,0xe9,0xce,0xe0,0xe3,0xb9,0xe8,0x20,0xa1,0xc7,0x76, + 0x6a,0x7a,0x96,0x2c,0xe7,0x06,0x81,0x1b,0x6d,0xad,0xd6,0x22,0x5b,0x1e,0x31,0x2a, + 0xc3,0x48,0x27,0x64,0x53,0x48,0x46,0x89,0x11,0x61,0xbb,0x74,0x96,0x12,0xcf,0x52, + 0xce,0x33,0xb3,0x0c,0xab,0x19,0xb6,0x4b,0x89,0x19,0x7a,0xaa,0x36,0xcb,0x8a,0x59, + 0xc8,0x37,0x81,0x4c,0xd1,0x9f,0x5d,0xe3,0x20,0x79,0xf2,0x36,0xa7,0xd5,0x0c,0x23, + 0x88,0xb1,0x88,0xb5,0x02,0x56,0xe9,0xa8,0xc4,0xcf,0x66,0xaf,0x86,0x21,0x63,0xa5, + 0xb0,0x6a,0x50,0xdc,0x8e,0x9f,0xa7,0x67,0x74,0x66,0x1d,0xb0,0x9d,0x9d,0xe6,0xdc, + 0xc2,0xf3,0x06,0x8f,0x9b,0xa5,0xeb,0xb8,0x20,0xb2,0x2d,0x35,0x81,0x68,0x6e,0x61, + 0x02,0x67,0x11,0xb7,0x9c,0x24,0x83,0x8e,0xc7,0xc4,0x22,0x64,0xbc,0xe8,0xcc,0xb2, + 0xb3,0x3a,0x1b,0x89,0x56,0x89,0xa4,0xb1,0xb1,0x45,0x33,0xcd,0xda,0x6b,0x91,0x75, + 0x76,0x58,0xcd,0x12,0x7d,0x2c,0xe5,0x12,0x6f,0xd0,0x71,0x3e,0x0d,0x9b,0xcf,0x8c, + 0x9f,0x69,0x14,0x78,0x72,0x35,0x5c,0x02,0xb3,0xe3,0x34,0x0a,0x1c,0x67,0x2b,0x25, + 0x75,0x34,0x91,0x30,0x55,0xa8,0x73,0x18,0x9d,0x19,0xe7,0x5b,0x27,0x83,0x65,0x9a, + 0x99,0x83,0x02,0xba,0xf1,0xec,0xa5,0xe6,0x53,0x7b,0x51,0x43,0xe2,0x1c,0x73,0x12, + 0xb2,0x26,0x58,0xac,0x9d,0xd1,0xce,0x58,0x45,0x5f,0x63,0x76,0x14,0x2f,0x81,0xb5, + 0xd3,0xfc,0xad,0xa1,0xd1,0xf1,0x13,0x98,0x6f,0x35,0x97,0x24,0x3c,0x13,0xb8,0x2e, + 0x27,0x57,0x6b,0x4e,0x60,0x36,0x63,0xa7,0x78,0x7b,0xdf,0x1c,0x0b,0x70,0xf5,0x0c, + 0xc9,0x79,0xa6,0xab,0x99,0xd2,0x2c,0xa8,0x35,0xc6,0x31,0xbd,0x69,0x58,0x6b,0x1a, + 0xd5,0x99,0xc6,0x74,0xa6,0x71,0xfd,0x5d,0x03,0xac,0x85,0x16,0x98,0x8c,0x10,0x0e, + 0xa3,0xb7,0x65,0x42,0x89,0xbf,0x20,0x00,0xe6,0x54,0x0d,0x40,0x46,0x88,0x45,0x43, + 0x1a,0x6c,0xa1,0x4b,0x0d,0x04,0xe0,0x66,0xd5,0x1a,0xd4,0x16,0x75,0x66,0xd7,0xe2, + 0xb8,0xe5,0x92,0x11,0x1d,0xb3,0x8a,0x33,0xca,0x96,0x95,0x5a,0x63,0xee,0x02,0x0e, + 0x23,0x03,0xb3,0x08,0x74,0x6a,0x48,0x6b,0x2e,0xd9,0xb4,0xbe,0xb7,0x4f,0x1a,0xbb, + 0x26,0x8d,0x2d,0xe4,0x20,0x0c,0x27,0x6b,0xa5,0x1a,0xff,0x10,0x5c,0xdc,0x65,0xcc, + 0x69,0x37,0x66,0xb5,0x2c,0x47,0x57,0x2e,0x47,0x57,0x2f,0xa9,0x06,0x8c,0x0b,0xab, + 0xff,0x5f,0x7c,0xed,0x6c,0x0b,0xc6,0xff,0x6b,0x1a,0x9b,0x98,0xf4,0xf1,0x0b,0x78, + 0x77,0xff,0x81,0xa3,0xc7,0x4f,0x9e,0xbf,0x78,0xc5,0xd5,0xc3,0xf7,0xc6,0xad,0xf0, + 0x98,0xb8,0x94,0xf4,0x4c,0x01,0x1c,0x84,0xa5,0xf2,0x0a,0x28,0xc2,0xe4,0x15,0x03, + 0xdd,0xf8,0x9c,0x1c,0xf5,0xf8,0x08,0x9c,0x5a,0xf1,0x49,0x1d,0x58,0x86,0x49,0x21, + 0xd6,0xeb,0xe7,0x0c,0xe4,0x65,0xa9,0xf3,0xdc,0x1f,0x85,0xc9,0x0b,0x0d,0xa1,0x04, + 0x73,0xb5,0x58,0x4f,0xbf,0xa0,0xa6,0x6f,0x05,0xa2,0x07,0x64,0x52,0x9a,0xe1,0x40, + 0x3d,0x4f,0xab,0x30,0xf9,0xee,0x5a,0x4b,0x66,0xb5,0x74,0x96,0xc2,0x2c,0xd2,0xea, + 0x68,0x8b,0x2f,0x09,0x9d,0x65,0x10,0x42,0xa3,0xa3,0x53,0x50,0xeb,0x09,0x01,0xae, + 0x25,0xef,0xc3,0xd5,0xb1,0x5d,0x0d,0xbd,0x06,0x20,0x0b,0xf1,0x66,0x32,0xab,0x29, + 0x8e,0x33,0x3b,0x4b,0xc7,0xf5,0x3c,0xb9,0x5a,0xfa,0x5a,0x46,0x82,0xeb,0x88,0xbd, + 0x0c,0x31,0xd8,0x42,0xc7,0x29,0x19,0xd5,0x99,0xd5,0x87,0x79,0x93,0x14,0x4b,0xcc, + 0x57,0x92,0x92,0xe9,0x39,0xb9,0x64,0x9c,0xb1,0x88,0x95,0xc8,0x99,0xa0,0xe3,0xf8, + 0x40,0x97,0x1d,0x47,0x59,0xf4,0xb5,0xbf,0x9f,0xc5,0x5e,0x90,0xcb,0xe9,0x46,0xa7, + 0xa8,0x8d,0x40,0xcc,0xad,0x25,0x23,0x7a,0x2a,0x82,0xef,0x7c,0xfe,0x20,0x15,0x67, + 0x13,0x2f,0x1d,0x5f,0x79,0x6a,0x1a,0xe7,0x0d,0x3a,0xc2,0x99,0x40,0x43,0xc9,0x76, + 0xf9,0x7a,0x82,0x1b,0xf5,0x1c,0x67,0xee,0xfd,0x5c,0x94,0x1b,0x2f,0x64,0xe6,0x64, + 0xa0,0x4a,0x72,0xa6,0xf1,0x75,0xa6,0x88,0xa5,0xdb,0x35,0xf4,0xfb,0x1c,0x9e,0xb6, + 0x16,0xd1,0xe1,0xe5,0x86,0x6d,0xee,0xf1,0x89,0xcd,0xa9,0xc8,0x73,0x05,0x43,0xc3, + 0xda,0xc5,0x77,0x3e,0x23,0x97,0x53,0x83,0xd3,0x81,0x17,0x11,0x7e,0x36,0x52,0xff, + 0x58,0x65,0x3b,0xf3,0xc2,0x50,0xd6,0x76,0x3d,0x2f,0x51,0xf9,0xc9,0xa0,0xb3,0x49, + 0x33,0x26,0x4c,0x24,0x4b,0xed,0x98,0x30,0x4b,0xde,0x48,0xca,0xcf,0x0d,0x2e,0x46, + 0x96,0x6b,0xb5,0xac,0x2b,0xf4,0x6c,0xc2,0xeb,0x6c,0xac,0x30,0xfb,0x84,0xd2,0x70, + 0x16,0x59,0xba,0x85,0x1a,0xa8,0xb1,0xf2,0x00,0xcf,0x69,0xfc,0x2d,0x69,0x26,0x63, + 0x89,0x2d,0xf6,0x02,0x1d,0xe7,0x88,0xe9,0x87,0x8c,0x46,0x6f,0x98,0x9c,0x33,0x4e, + 0xcc,0x99,0xfe,0x0e,0x9f,0x08,0x50,0xa3,0x39,0x5c,0x63,0x58,0x73,0x8a,0xe2,0xd0, + 0x0e,0x69,0xd8,0x6a,0xae,0xb5,0x3e,0x53,0xc3,0xf9,0xb7,0x79,0xdc,0xd4,0x34,0x6a, + 0xaa,0x1c,0x36,0x29,0x06,0x4d,0xa5,0xbd,0xf8,0x6b,0xa3,0x8c,0x16,0x7c,0xd4,0x55, + 0x64,0xd5,0x4a,0x64,0xe5,0x42,0xf3,0xe8,0xea,0xca,0xdf,0xe2,0x4f,0x8d,0xee,0x0a, + 0x16,0x16,0x17,0x84,0x79,0x62,0x38,0x05,0x03,0x7c,0x74,0xe6,0xfc,0x15,0x27,0x67, + 0x6f,0xdf,0xc0,0x90,0xf0,0xd8,0xf8,0xc4,0xd4,0x2c,0x41,0x6e,0x41,0x61,0x79,0x99, + 0x4c,0x51,0x59,0xdd,0x54,0xd7,0xd8,0xdc,0xde,0xd9,0x0b,0x67,0xe1,0xfe,0x41,0xb5, + 0x7a,0x78,0x6c,0x64,0x6c,0x72,0x72,0x7a,0x7a,0x6a,0x1a,0xdf,0xd4,0x40,0xee,0xbf, + 0xc2,0xeb,0x67,0x9a,0xff,0x50,0x82,0xe9,0x5b,0xb6,0xe1,0x83,0x9a,0x54,0xde,0x39, + 0xfa,0xf3,0x61,0xba,0x7f,0xe9,0xd1,0x98,0x6e,0x5e,0x42,0x83,0xff,0xa3,0xe3,0xec, + 0x27,0x8f,0x8e,0xfd,0x60,0xd4,0x10,0x02,0xda,0x6a,0x29,0x25,0xf7,0x69,0xc0,0x2b, + 0xe5,0x3a,0x5e,0x2d,0x60,0x76,0x37,0xd9,0x8c,0xf3,0xdc,0xc7,0x17,0xe5,0x43,0xd8, + 0xea,0x59,0x89,0x3a,0x8e,0x33,0xd7,0xa5,0x6c,0x89,0x9e,0x8c,0x20,0x4e,0x2b,0xf6, + 0x23,0x68,0x8e,0xee,0x77,0xae,0x6a,0xb0,0xbb,0x1e,0xd4,0x9e,0x67,0xbb,0x80,0xcf, + 0x91,0xda,0xa1,0x23,0x2f,0x19,0xe7,0xaa,0xc6,0x1c,0x8f,0x8f,0x9e,0x76,0xe9,0x12, + 0xbe,0x15,0xdc,0xd5,0x05,0xcf,0x2e,0x8a,0xd0,0x0f,0xbd,0x39,0x6a,0x26,0xdb,0xfd, + 0x34,0xf6,0xb2,0x4a,0xea,0x78,0x06,0x9a,0xe5,0xd2,0x4f,0x66,0xbe,0x6f,0x6d,0xd6, + 0x7e,0x0a,0x7b,0x39,0x9d,0xf5,0x56,0xa6,0xf1,0x8c,0xe5,0x2c,0xd2,0xf2,0x56,0x99, + 0xed,0xe5,0xae,0xdc,0x38,0x1a,0x2e,0x64,0x9c,0x27,0xb9,0x80,0xf2,0xbb,0x2c,0xa2, + 0x21,0xea,0xe9,0x59,0x9d,0xf5,0x3c,0x0e,0x3a,0x22,0x48,0x67,0x45,0x6c,0xc3,0x8a, + 0xaf,0x80,0x39,0xfa,0x3c,0x8b,0xcc,0x41,0xb1,0xea,0x72,0x51,0xe0,0x2e,0x3f,0xc8, + 0x5a,0xba,0x17,0x68,0xb2,0xcd,0xf1,0x7d,0xc2,0x6a,0x6b,0xf6,0x15,0xe1,0x60,0x91, + 0x03,0x5c,0xe1,0xa3,0x51,0x63,0x4b,0x2a,0xcd,0x2e,0xeb,0x80,0x52,0xcd,0xf9,0xdb, + 0x8a,0xe7,0x3a,0xab,0x7d,0xc4,0x2c,0xe1,0x5d,0x86,0x31,0xd7,0x0c,0x3c,0x6e,0xd6, + 0x51,0xe0,0x4c,0x63,0xcd,0xd4,0xdb,0xc6,0x77,0xed,0x08,0x32,0xa9,0xc2,0xca,0xb5, + 0x93,0x21,0x34,0x10,0xfc,0x0d,0x4b,0xfd,0xc3,0xed,0x1a,0xde,0x27,0x80,0x79,0x83, + 0x68,0x74,0x86,0x49,0xfd,0xea,0x97,0x5e,0xd4,0xfe,0x56,0x81,0x9e,0x94,0xa1,0xf8, + 0x0e,0x6a,0x10,0xfa,0xd9,0x2f,0xb1,0xbb,0x26,0x4d,0xad,0x13,0xa6,0xea,0x11,0x53, + 0xd5,0x08,0xde,0x94,0x05,0xc7,0xde,0x82,0x8e,0x15,0x41,0xcb,0x72,0x46,0xd3,0x4a, + 0x6c,0xd5,0x62,0x88,0x62,0x29,0xad,0x6e,0x79,0x56,0x6f,0xfc,0xdb,0x7b,0xc8,0xc6, + 0xa7,0x83,0xa5,0x95,0xe5,0xa2,0x92,0xd2,0x73,0xe7,0x2f,0x1d,0x38,0x70,0xf8,0xf8, + 0x89,0x0f,0x2f,0x5c,0x72,0x74,0xf3,0xf0,0x09,0xbc,0x11,0x12,0x1e,0x15,0x97,0x9c, + 0x92,0x95,0x9d,0x93,0x97,0x5f,0x88,0x77,0xfb,0xab,0xaa,0xeb,0x6a,0x1b,0x5a,0x9a, + 0x5a,0x3b,0x3b,0xba,0xfa,0xf0,0x91,0xcb,0x03,0x43,0xea,0xe1,0xd1,0xa1,0x91,0xb1, + 0xd1,0xf1,0x69,0x72,0xc3,0xd5,0x2c,0xf9,0x53,0xef,0x2c,0xad,0xc5,0xf4,0x7b,0x24, + 0xfa,0x1e,0x07,0xee,0x5b,0x68,0x7a,0x69,0x4a,0x5a,0xfa,0x0d,0x15,0xfd,0x76,0x48, + 0x07,0x75,0x1c,0x6f,0xdc,0x9a,0x62,0xbe,0x2f,0x9d,0x9c,0x66,0xbe,0x01,0x26,0xdf, + 0xbf,0xe1,0x97,0x4e,0x64,0x4a,0x3b,0x85,0x5d,0x1d,0x61,0xae,0xe1,0xbe,0x70,0xa3, + 0x4c,0x38,0x9a,0x19,0xde,0x17,0x98,0xf8,0xcd,0xd5,0x34,0x25,0xd6,0x4c,0x9b,0xbf, + 0x19,0xe6,0xbe,0xfe,0x62,0x66,0x27,0xa7,0xb4,0x2c,0x43,0x8d,0xf9,0xbb,0x47,0x86, + 0x03,0xa3,0x1b,0x65,0xcb,0x8e,0x33,0xaa,0xb2,0xc0,0x17,0x4a,0x6f,0x08,0xa7,0xf7, + 0xa1,0xd1,0xaf,0xdd,0x38,0x87,0x68,0xd8,0x85,0x16,0x7a,0xf2,0x95,0x9f,0x62,0x74, + 0x63,0x74,0xe6,0xba,0xc0,0x61,0x92,0x51,0x83,0xea,0xc3,0xb7,0xe8,0xae,0xed,0xa5, + 0xab,0xf8,0x7e,0xfe,0xab,0xd8,0x4b,0xbf,0xc6,0x64,0xbc,0xcd,0x19,0x4e,0x97,0x93, + 0xaf,0x1f,0x75,0x9c,0xce,0x66,0xe2,0x69,0x8b,0x2e,0x6f,0x96,0xaf,0xa4,0x86,0x33, + 0x81,0xcb,0x3d,0x2a,0x05,0xec,0x9d,0xb6,0x30,0x41,0xc3,0x7e,0x95,0x6a,0x56,0x9b, + 0xfb,0xfb,0x05,0x97,0x4b,0xf4,0x85,0xce,0xb8,0x76,0xc6,0x92,0xd5,0x8c,0x96,0xfb, + 0x66,0x95,0x67,0xbe,0xc5,0x2c,0x97,0x84,0x96,0x16,0x51,0xc7,0xf2,0xff,0x28,0x30, + 0xcb,0x7e,0x83,0xcd,0xb4,0x2c,0x37,0x9e,0x3f,0x59,0x85,0xd9,0xbf,0x83,0x50,0x7d, + 0xd0,0xcf,0xec,0xd6,0xa0,0x5f,0xed,0x92,0x54,0x99,0xd6,0xb2,0xb8,0x96,0x73,0x02, + 0x31,0x87,0xd2,0x98,0x63,0xc4,0xdb,0x56,0xb3,0x6c,0x1c,0xcd,0x16,0xb1,0x5f,0x7a, + 0xf3,0x36,0xdd,0x34,0x33,0x4b,0xf5,0x59,0x3b,0x0a,0x9c,0x9f,0xf9,0x19,0xc5,0xfd, + 0x09,0x89,0xef,0x3a,0x3b,0x11,0x64,0xf3,0x47,0x43,0x53,0xd4,0x2a,0x3d,0x88,0x74, + 0x6e,0x84,0xa6,0x10,0x9d,0xe2,0xb6,0x3f,0xfd,0x63,0x16,0xdf,0x03,0xda,0x29,0xed, + 0xe2,0xe4,0xdc,0x2a,0x54,0x07,0xae,0x58,0x70,0x25,0xe3,0x1e,0x85,0x51,0xf6,0x3b, + 0x64,0xab,0x0a,0xc8,0xef,0x5a,0xb5,0x76,0x69,0xec,0x76,0xd7,0x12,0x3a,0x3b,0x6f, + 0x4d,0x43,0xbf,0x7f,0x06,0x18,0xd1,0x9a,0x06,0xb9,0xbf,0x2f,0x4f,0x9b,0x3a,0xa7, + 0x4c,0x9d,0x93,0xf8,0x6d,0x73,0xed,0x30,0xb9,0xcf,0x6a,0xd0,0x54,0xd6,0x87,0x3f, + 0x59,0xca,0x6e,0x5d,0x4e,0x6b,0x5a,0x8a,0xaf,0x5d,0x8e,0xac,0x5c,0x09,0x96,0x1b, + 0xc4,0xed,0x10,0x97,0xbf,0x17,0x5f,0x6b,0x18,0x1d,0x9f,0x48,0x49,0xcd,0x3c,0x75, + 0xfa,0xec,0xe1,0xc3,0xc7,0x4f,0x9d,0x3a,0x7b,0xd9,0xd1,0xd9,0xdd,0xd3,0x37,0xe0, + 0x66,0x48,0x44,0x74,0x6c,0x52,0x4a,0x16,0x9c,0x85,0xc5,0xf9,0xa5,0x25,0xe5,0xb2, + 0x72,0x45,0x65,0x55,0x4d,0x63,0x6d,0x63,0x6b,0x4b,0x5b,0x67,0x7b,0x67,0x77,0x67, + 0xf7,0x60,0x4f,0xdf,0x20,0x79,0xf5,0xed,0xd8,0x80,0x7a,0x8c,0xb9,0x65,0x62,0x7c, + 0x1a,0xb8,0x41,0x5d,0x1e,0x9f,0x9c,0x1e,0x1e,0xc7,0x3b,0xaf,0xc6,0x27,0xa7,0xc6, + 0x27,0x26,0xe9,0x5d,0x58,0xb4,0x3b,0x32,0x3e,0x33,0x06,0xdd,0xc9,0xe9,0x89,0x49, + 0x20,0x9b,0xe2,0x6e,0xd0,0x62,0x5a,0x1c,0xe4,0x60,0x8a,0x5d,0xb5,0x46,0x97,0xb2, + 0x35,0x77,0x29,0x62,0x66,0x38,0x8e,0xf7,0x7d,0x31,0xb3,0x13,0xbc,0x59,0xfb,0xc4, + 0x2c,0x2b,0xab,0x2e,0x23,0xd7,0xac,0x9b,0xb5,0x1a,0x63,0x13,0x40,0x3f,0xc3,0xd2, + 0x98,0x6d,0x21,0xe6,0x4c,0x8d,0x5b,0x77,0xc9,0x2a,0x96,0xd8,0xaa,0xcb,0x90,0x59, + 0xb2,0xb2,0x52,0x83,0xb3,0xe8,0xde,0xb0,0xd7,0x92,0x15,0x0c,0x8e,0xdd,0x95,0x5c, + 0xa0,0x1f,0xb7,0x34,0x81,0x4d,0x24,0x72,0x53,0x1f,0x43,0x4c,0x54,0xb2,0xc9,0x9c, + 0xdb,0xcb,0xe5,0xf9,0x99,0x2f,0xc8,0x26,0x21,0x3f,0x21,0xeb,0x26,0xcc,0x42,0xad, + 0x2d,0xb2,0x0d,0x8a,0x55,0x7a,0xf3,0xb5,0xe2,0xbb,0x8e,0x1f,0x23,0x6b,0x7d,0x18, + 0x86,0xbc,0x54,0xb1,0x09,0xe8,0x5a,0x31,0xb2,0xde,0x29,0x3c,0x4f,0xf2,0x77,0xe8, + 0xed,0xf3,0xea,0x36,0x21,0x03,0xa1,0x63,0x96,0x5d,0x1a,0x94,0x91,0x89,0x35,0xf7, + 0x2f,0xdf,0xcf,0x54,0x67,0x0c,0xeb,0x84,0x45,0x22,0x61,0x68,0x70,0xdc,0x42,0x67, + 0xd6,0x04,0x5c,0x42,0x67,0xc7,0x26,0x26,0xc6,0x27,0xb5,0x43,0xd3,0xcb,0x50,0x17, + 0x06,0x66,0xb1,0x40,0xd0,0x62,0x01,0x5d,0xda,0xde,0xbb,0x00,0xfa,0x0f,0xb0,0x08, + 0x85,0x41,0x9e,0x81,0x74,0x96,0x6f,0xa9,0x5d,0x1a,0xdb,0xee,0xc0,0xac,0x79,0xfc, + 0xf6,0xd2,0x29,0x31,0xff,0xd6,0xac,0xee,0x49,0x63,0x37,0xb9,0xc3,0x0a,0xca,0x2e, + 0x9c,0x76,0x2b,0x87,0x4c,0x0a,0xb5,0xa9,0xb8,0xcf,0x54,0xd4,0x67,0xca,0xef,0x5c, + 0x11,0xb6,0x2e,0xa6,0x36,0xad,0x26,0xd6,0x2e,0x86,0x57,0xae,0x86,0xc8,0x0d,0x69, + 0x8d,0xab,0x6d,0xe3,0xa6,0xbf,0x7f,0xe7,0xbc,0x16,0x2c,0xaf,0xae,0x0c,0x0c,0xaa, + 0x93,0x52,0x52,0x4f,0x9f,0x3e,0x0b,0x07,0xe1,0x8f,0x4e,0x9d,0xbd,0xe2,0xe4,0xec, + 0xe6,0xe9,0x17,0x18,0x74,0x2b,0x22,0x2a,0x3e,0x21,0x29,0x2d,0x3d,0x4b,0x28,0x14, + 0x49,0xf2,0x0b,0xa1,0x10,0xcb,0xcb,0xe5,0xd5,0xca,0xca,0x1a,0xa8,0xc5,0xf5,0xcd, + 0x2d,0x8d,0xcd,0xed,0x2d,0x6d,0xdd,0x6d,0x1d,0x3d,0x5d,0x3d,0xfd,0x1d,0x5d,0xfd, + 0xdc,0x3d,0xff,0xf8,0xeb,0x80,0x01,0xfc,0x69,0x40,0xdf,0xc0,0x70,0x6f,0xff,0x50, + 0x6f,0xff,0x30,0x9c,0x9a,0x7b,0xf1,0x2d,0x48,0x88,0x90,0xdf,0x08,0x0f,0x93,0x29, + 0xda,0x0e,0x71,0x2d,0x9d,0x22,0xef,0xb2,0x1f,0x66,0x89,0x87,0x78,0xc4,0x43,0x2c, + 0x31,0x33,0x0b,0x22,0x80,0x98,0x2e,0xa7,0x08,0x8f,0x06,0x46,0xcc,0x6b,0x79,0x64, + 0x8c,0x20,0x4b,0x86,0x43,0x54,0x31,0xbe,0x5c,0x4b,0x0d,0xad,0xbb,0x1c,0x4f,0x8a, + 0xf3,0x75,0xb3,0x94,0x6b,0x26,0x66,0xc9,0xcc,0xfc,0x39,0x35,0x38,0xfe,0x36,0x5d, + 0x86,0x6c,0x2d,0x7b,0x79,0x16,0x59,0x38,0x87,0xb6,0x24,0x04,0x56,0xd2,0xb9,0xa0, + 0x20,0xc2,0x99,0xf0,0x45,0xda,0xcb,0x59,0x3a,0xc4,0x6b,0xed,0x08,0xb2,0x55,0x83, + 0xe5,0x3c,0xc4,0x33,0x6a,0x88,0xeb,0x72,0x89,0xc4,0x85,0x98,0xd7,0xe5,0xb3,0xb2, + 0x23,0x97,0x70,0xe6,0x54,0x1d,0xb2,0xa4,0x19,0xe2,0x99,0x69,0x27,0xeb,0x6c,0xfd, + 0x6c,0xcf,0xc3,0x76,0x12,0x18,0x04,0xf1,0x73,0x80,0x8b,0xaf,0x8d,0x37,0x86,0x2c, + 0xd7,0x0e,0xf1,0xad,0xb8,0x4d,0x02,0xf3,0x77,0x0a,0xd9,0x47,0x7c,0x65,0xac,0xcc, + 0xb7,0xe3,0x7c,0x8e,0x33,0x9d,0x5d,0x8b,0x33,0xd7,0x5d,0x2b,0x55,0xac,0x9d,0xc3, + 0x9b,0xb5,0xb1,0x97,0xa6,0x28,0xa7,0xc0,0xf0,0x5a,0x9b,0x9d,0x6e,0x0d,0x7e,0x76, + 0xd1,0xc1,0x9e,0x81,0xc1,0xde,0x41,0x75,0x8f,0x7a,0xbc,0x6b,0xd4,0xd0,0x31,0xb6, + 0xd2,0x3e,0x61,0x6a,0x9b,0xc0,0xfb,0x6f,0x01,0x9a,0xc7,0x19,0xe4,0x9e,0x80,0x76, + 0x0a,0x13,0x46,0x80,0x8e,0x09,0xbc,0x7f,0xa9,0x75,0x02,0x8f,0x96,0x1d,0x93,0x68, + 0x11,0xd8,0x02,0x78,0xf3,0x98,0xb1,0x6b,0x7c,0x15,0xc7,0x81,0x60,0xc2,0x04,0x64, + 0x6d,0xe3,0xc6,0xe6,0x09,0x3c,0x7e,0xb6,0x4d,0x18,0xbb,0xc8,0x20,0x10,0x77,0x10, + 0x3e,0x2d,0x63,0xc6,0xd6,0x71,0xec,0xb6,0x8f,0x1b,0x81,0xb3,0x55,0xb7,0x71,0x0c, + 0xc5,0x35,0x13,0xce,0xd4,0x51,0xb4,0x6d,0xa3,0x6b,0x27,0x98,0xd9,0x16,0x02,0x30, + 0x05,0xf4,0x8d,0xe3,0xcc,0x8f,0x95,0x00,0xe0,0xa8,0xab,0x52,0xe3,0x9f,0x77,0xcb, + 0xfa,0x4c,0x25,0xbd,0xa6,0xfc,0x6e,0x93,0xa4,0xd3,0x98,0xdd,0xbe,0x9a,0xd1,0xbc, + 0x18,0x57,0x63,0x8c,0xae,0xc6,0x07,0x78,0x06,0xcb,0x17,0x53,0xea,0x57,0x41,0xd5, + 0xbf,0xe1,0x67,0x5b,0x7d,0xae,0x55,0x78,0xb5,0xad,0xa3,0x23,0x2c,0x22,0xf2,0xf8, + 0xf1,0x93,0x50,0x85,0x4f,0x9d,0x3e,0xef,0x70,0xc5,0xd9,0xd5,0xdd,0xc7,0xd7,0x3f, + 0x38,0x34,0x2c,0x3a,0x3a,0x36,0x39,0x29,0x25,0x23,0x23,0x2b,0x27,0x27,0xb7,0x20, + 0x2f,0xbf,0xa8,0xb0,0x44,0x51,0x2a,0x55,0x28,0x94,0x55,0x0a,0x55,0x8d,0xb2,0xaa, + 0xa1,0xaa,0xa6,0xa1,0xae,0xa1,0xb1,0xb6,0xbe,0xb5,0x81,0xf9,0x8d,0x3c,0x3e,0x67, + 0x03,0x00,0x10,0xf2,0xcc,0x0d,0x6c,0x29,0xde,0xd4,0xda,0xd6,0x44,0x1e,0xc4,0xc1, + 0x01,0xd7,0x05,0x32,0x8a,0x43,0x8b,0xc0,0x22,0x1c,0x07,0x8e,0xc0,0xee,0x72,0x8e, + 0x92,0xcf,0xc4,0x8a,0x8c,0xe1,0xcc,0xe2,0x94,0x98,0xbf,0x84,0x23,0xb6,0x56,0xc6, + 0x9e,0x5c,0xfe,0xaa,0x3b,0x91,0x6b,0x6b,0x02,0x15,0xc4,0x67,0x68,0xa5,0xe1,0x5a, + 0x0c,0x6d,0x67,0x39,0x56,0x4d,0xad,0x8c,0xeb,0x6e,0xa3,0x2d,0x9f,0x89,0x5d,0xfd, + 0x3f,0x2f,0x7b,0x9b,0xed,0x69,0x62,0x35,0xc8,0x0f,0x37,0x63,0x82,0x8d,0xd3,0xac, + 0x42,0x6c,0xe1,0x40,0x7b,0x6a,0xd8,0x8a,0xb0,0x6b,0xf5,0x6d,0x54,0xb2,0x52,0x8f, + 0x6f,0x2f,0x5f,0xc9,0xdb,0xbb,0x71,0x2d,0x32,0xbb,0xb1,0xb0,0x82,0x46,0x4a,0xdc, + 0x86,0x48,0x4b,0x9b,0x59,0xa8,0x55,0x86,0xf0,0xb7,0x8f,0xad,0x73,0xd6,0x8a,0x91, + 0xfd,0xe5,0x6d,0x4c,0x97,0x8a,0xb3,0x4e,0x54,0xa2,0x86,0xdd,0xdc,0xe0,0x13,0xdb, + 0xa6,0xae,0x15,0x6e,0xab,0x4c,0x23,0xdb,0xa5,0xfc,0x41,0x0d,0x8e,0xa7,0x99,0x5b, + 0x9b,0x05,0xe7,0xe6,0xd6,0xf6,0xa6,0x96,0xb6,0xa6,0xe6,0xe6,0xe6,0xb6,0x9e,0x9a, + 0xee,0xa9,0xea,0x81,0xc5,0x8a,0x61,0x7c,0x04,0x84,0x52,0xcd,0x3c,0x70,0x09,0x00, + 0xba,0x1c,0x7e,0xaf,0x40,0x85,0x9a,0xc0,0x90,0x59,0xf9,0x4a,0x82,0x57,0x0e,0x23, + 0xa8,0x08,0xa2,0x02,0x4b,0x87,0xd1,0x52,0x6a,0x2f,0x52,0xaa,0x99,0x11,0x95,0xda, + 0xec,0x04,0xca,0x04,0x81,0xc7,0xd3,0x6e,0x97,0x32,0xa7,0x08,0x9d,0xb5,0xf5,0x9e, + 0x9c,0xf7,0xb0,0x8e,0xc2,0x5e,0x53,0x41,0x8f,0x51,0xd2,0xb9,0x22,0xee,0x5c,0x16, + 0x75,0x9a,0x04,0x6d,0x8b,0xe9,0x4d,0xab,0xe9,0xcd,0xcb,0xd1,0x55,0xc6,0xb0,0x8a, + 0xd5,0x9b,0x8a,0xe5,0x80,0xf2,0xa5,0xe8,0xaa,0xe5,0xda,0xe1,0x55,0xed,0xd2,0x97, + 0x5f,0xd7,0xee,0x2d,0x58,0x35,0x19,0x7b,0xfa,0xfa,0x6f,0x86,0x46,0x9d,0x3a,0x73, + 0xf6,0xe8,0xb1,0x13,0x1f,0x7c,0x78,0xfa,0xec,0xf9,0x4b,0x8e,0x57,0x5d,0xdc,0xdc, + 0xbd,0xfc,0xfc,0x6f,0xdc,0x08,0x8e,0x08,0x8f,0x88,0x8f,0x8d,0x4b,0x4d,0x4c,0x4e, + 0x4d,0xcb,0x10,0x66,0x0a,0xa0,0x1c,0xe7,0xe7,0x89,0x0b,0xa1,0x22,0xe7,0x17,0x96, + 0x17,0x95,0x94,0x17,0x15,0x4b,0x8b,0x4b,0x65,0xa5,0xe5,0xf2,0x92,0x72,0x7c,0xe6, + 0x9b,0x54,0x5e,0x09,0x08,0x79,0x36,0x5d,0x45,0xb9,0xac,0x82,0x3c,0x50,0xae,0x82, + 0x3c,0x7e,0xb0,0xb2,0x48,0x56,0x55,0x26,0x83,0x22,0x5e,0x49,0x1f,0xe8,0xc7,0x01, + 0x79,0x92,0x5e,0x15,0x25,0xa6,0x80,0xcf,0x7e,0x54,0x30,0xdd,0x62,0x39,0xae,0x2a, + 0x97,0x57,0x90,0x07,0xf7,0x29,0x99,0x59,0x96,0x98,0x63,0x55,0xce,0x4c,0xa9,0x40, + 0x10,0xed,0xd2,0x67,0xd0,0xf1,0x78,0xaa,0xca,0xe5,0x4a,0x0b,0x11,0x0c,0x30,0x4b, + 0x6c,0x39,0xf3,0xbb,0xbc,0x25,0x4a,0xbe,0x5c,0x46,0x96,0x25,0x13,0xfa,0x90,0x49, + 0xfe,0x2a,0xb0,0xda,0xac,0x24,0x3e,0x3d,0xaf,0x82,0xd1,0x4d,0x51,0xc9,0x29,0x09, + 0xb3,0x68,0x2c,0x4f,0xee,0x27,0xdb,0x2b,0x37,0xaf,0xfd,0x5f,0x63,0x2f,0xfb,0x6c, + 0x40,0x5b,0xb9,0x72,0x3b,0x72,0x19,0x13,0x14,0xf6,0xd6,0x2a,0xac,0x56,0x29,0x2d, + 0xe3,0x6b,0x23,0xd7,0xc6,0x5e,0x4e,0x73,0x1b,0xd3,0x78,0x82,0x14,0xe6,0xb5,0xe8, + 0x70,0x85,0xa5,0x7a,0x76,0xfc,0x4c,0xe4,0x5a,0xfa,0xb0,0xa4,0x9c,0x51,0x95,0x3c, + 0xb6,0x54,0x69,0x35,0x6b,0xdf,0xb1,0x72,0xa5,0xd4,0xc6,0x1b,0x56,0xf1,0xa5,0x4f, + 0x86,0xbc,0x4d,0x5e,0x59,0x38,0xc7,0x5e,0x32,0xd8,0x71,0xbb,0xc2,0x4e,0xb8,0xd7, + 0xda,0x47,0xb6,0x26,0x58,0xf9,0x93,0xcb,0x90,0xb5,0x92,0xd0,0x2a,0x16,0x64,0x84, + 0x6e,0xf6,0x2a,0x62,0x91,0x1c,0xa2,0xcc,0xe7,0x59,0x2a,0xad,0xe2,0xb2,0x85,0x8c, + 0x57,0x91,0xe8,0x80,0x3e,0x55,0xa5,0x95,0xcd,0x65,0x0d,0x23,0x85,0xad,0x1a,0x49, + 0x97,0xb1,0xa0,0xcb,0x28,0xea,0x34,0x72,0x0f,0x45,0xbc,0xa7,0x81,0x7d,0xba,0xa3, + 0xd9,0x22,0x49,0x17,0xf3,0xf4,0x48,0x2b,0xca,0x7c,0x7c,0x26,0xe4,0x2a,0xcc,0xe6, + 0x92,0x55,0xd6,0x4f,0x98,0xbc,0x6d,0x57,0x44,0x9e,0xb4,0x89,0x8f,0x94,0xec,0x34, + 0x8a,0xbb,0x8d,0xf9,0x5d,0xab,0x00,0xb9,0xac,0x08,0x60,0xcb,0x4a,0x41,0x35,0x72, + 0x3a,0x80,0xbf,0x51,0x88,0x4f,0x6c,0x36,0x65,0xb5,0xac,0x66,0x35,0x9b,0x32,0x9b, + 0x4d,0xe9,0xcd,0xa6,0xe4,0x7a,0x7c,0x93,0x6f,0x78,0xe5,0x6a,0xa8,0x72,0x25,0x48, + 0xba,0xe4,0x5f,0xbe,0xe8,0x57,0xb6,0x18,0x5b,0xb9,0x5c,0x39,0x68,0x9c,0xff,0xfb, + 0x99,0xf7,0x33,0xc0,0xdc,0xc2,0x42,0xdf,0x40,0x7f,0x7e,0x41,0x61,0xd0,0x8d,0xe0, + 0xcb,0x0e,0x8e,0xa7,0x3f,0x3e,0xf7,0xf1,0xb9,0x4b,0x17,0xc8,0x2b,0x41,0xdd,0xdc, + 0x7d,0x7c,0x7c,0x03,0xfd,0x82,0x6e,0xdd,0x0a,0x8b,0x0c,0x8f,0x8a,0x8b,0x8c,0x4e, + 0x8c,0x4b,0x48,0x89,0x4f,0x4c,0x4d,0x4c,0xc9,0x4a,0x4d,0xcf,0x4a,0xcb,0xc8,0x86, + 0x33,0x72,0x66,0x36,0x40,0x2e,0x00,0x79,0x01,0x41,0x5e,0xb6,0x40,0x9c,0x95,0x4d, + 0x10,0xa1,0x18,0x71,0x82,0x64,0x64,0xe3,0x3b,0x11,0xe8,0x43,0xef,0xcd,0xef,0x1d, + 0xc0,0x07,0xb0,0xe7,0xe2,0x5b,0x06,0xc8,0xd3,0xdd,0x81,0x98,0x79,0x40,0xbd,0x90, + 0x79,0x79,0x41,0xa6,0x50,0x42,0x97,0x73,0xb3,0x54,0x04,0xf3,0x8a,0x04,0x91,0x65, + 0x9b,0x83,0xa2,0x29,0xe7,0x2c,0x21,0x90,0xe5,0x66,0x33,0x6f,0x52,0xa0,0x2f,0x62, + 0xc8,0xb3,0xec,0x9a,0x75,0x33,0x3f,0xfa,0x5e,0x68,0x7e,0x4d,0x40,0x96,0x9d,0x59, + 0xf3,0x2b,0x15,0xe8,0x38,0xdb,0xcd,0xe5,0xba,0x40,0x46,0xcc,0xb4,0x94,0x2b,0x10, + 0x33,0x80,0xfa,0xe7,0x92,0x87,0xe7,0xb3,0x83,0x64,0x2d,0xd5,0x39,0x43,0x28,0xc9, + 0x66,0x38,0xf0,0xe9,0xad,0xed,0x35,0xc3,0x6d,0xed,0x35,0x2b,0xcf,0x30,0xf9,0x02, + 0xed,0xe5,0x1e,0xb9,0x4f,0x1e,0xb6,0x6f,0x21,0x97,0xfa,0x99,0x89,0xaf,0x90,0x0a, + 0x62,0x63,0x4d,0x25,0x0a,0x2c,0x7d,0xc5,0x99,0x29,0xb0,0x8d,0x6f,0xae,0xb9,0x9b, + 0x23,0xe6,0xe4,0x72,0x06,0x62,0x57,0x40,0xa7,0xc4,0xf6,0xa3,0xc0,0x2d,0x64,0x15, + 0xa0,0x3a,0x98,0x63,0x24,0xb4,0xb5,0x08,0x53,0x94,0x7b,0x1f,0x01,0xe5,0xcc,0x7b, + 0xc5,0x00,0x25,0x96,0x70,0x1c,0x98,0x74,0x15,0x31,0x6b,0xa9,0x62,0x36,0xb1,0x60, + 0x94,0xc9,0xce,0x61,0xa5,0x0b,0x59,0xe5,0xd7,0x90,0x7b,0x1b,0x3f,0x9b,0x83,0xc2, + 0x86,0x29,0xdb,0x9c,0x84,0x16,0x6e,0xe7,0xf2,0xca,0xdc,0x15,0xb2,0xbe,0xe5,0x98, + 0x8b,0xcc,0xf1,0xe5,0xbc,0x61,0xc5,0x0a,0x45,0xe7,0x98,0x23,0x6b,0x2d,0x57,0xc0, + 0x99,0x9f,0xc7,0x4f,0x24,0x22,0x94,0x4d,0x7e,0xa1,0x84,0xe5,0x2f,0xc9,0x84,0x4f, + 0x00,0x58,0x48,0xe8,0x33,0x61,0x4a,0x04,0x78,0x5e,0x16,0xb3,0x17,0x0a,0x04,0xb9, + 0x25,0x59,0xc5,0xb5,0xd9,0xca,0x81,0x94,0x6a,0x5d,0x5a,0xe3,0x62,0x5a,0xe3,0x6a, + 0x42,0xbd,0x31,0xb1,0xde,0x98,0xd6,0xb8,0x9c,0xd2,0xb0,0x9a,0xdc,0xb0,0x9a,0xda, + 0xb8,0x92,0xd6,0xb4,0x0c,0x90,0xdc,0xb8,0x9a,0xdc,0x78,0x8f,0x75,0x53,0x1a,0x4d, + 0xd4,0x84,0x8c,0x66,0x98,0x32,0xe2,0x20,0x79,0xf7,0x41,0x42,0x1d,0xe0,0x46,0x98, + 0x02,0x1b,0x53,0x9b,0x4c,0xa9,0x8d,0x40,0x6c,0x24,0xaf,0x48,0x58,0x4d,0x69,0x5c, + 0x49,0x20,0x2f,0xb2,0xe7,0xde,0xad,0x60,0x17,0xe2,0xe9,0x1b,0x25,0x58,0x84,0xfa, + 0x2a,0x05,0xe5,0x1a,0x13,0xf1,0x35,0x0a,0xe0,0xc6,0xd5,0xc4,0x06,0xee,0x75,0x0c, + 0x46,0xde,0x7b,0x19,0x8c,0x74,0x49,0x5c,0x8d,0x31,0xb6,0xc6,0x18,0x55,0x49,0x5e, + 0xc9,0xa4,0x5c,0x81,0x73,0x6e,0xa0,0x6c,0xe9,0x86,0x6c,0xc9,0xab,0x74,0xe1,0xa6, + 0x6c,0x11,0x0e,0xbc,0xf9,0x9d,0xab,0x9d,0xe3,0x46,0xcd,0xa2,0x69,0xf5,0xef,0x37, + 0x59,0x7d,0x4e,0xb0,0xb2,0x6a,0x1c,0x9f,0x9c,0x50,0x55,0x55,0x25,0x24,0xa5,0x5c, + 0x77,0x71,0xfb,0xe0,0xd4,0xc7,0x1f,0x9d,0xfe,0xf8,0xcc,0xd9,0x0b,0x17,0x2e,0x3b, + 0x39,0x5d,0x75,0x76,0x76,0x71,0x77,0xf3,0xf4,0xf6,0xf2,0x0d,0xf4,0xf5,0x0b,0xf2, + 0x0b,0x0c,0x09,0xb8,0x11,0x7a,0xe3,0x66,0xc4,0xcd,0x5b,0x11,0xb7,0xc2,0x22,0x42, + 0xc2,0xa2,0x00,0xc2,0xc2,0xa3,0x43,0xc3,0xa2,0x42,0x23,0xa2,0x23,0x22,0xe3,0xc2, + 0x23,0x62,0x22,0x22,0x63,0xa1,0x0d,0x8f,0x88,0x85,0x2e,0x81,0xd8,0xd0,0xb0,0x18, + 0x32,0x15,0x4b,0x06,0x63,0x09,0x1e,0xcd,0xcd,0x92,0xc1,0x78,0xfe,0x2c,0x25,0x86, + 0x41,0x7b,0xb3,0xf1,0x7c,0xce,0x1c,0xf1,0x6d,0x66,0xef,0x5c,0x10,0x47,0x60,0xbb, + 0xf6,0xf6,0x82,0xd8,0xf1,0xbb,0x22,0x8e,0xff,0x1b,0xb3,0xf7,0x6e,0x03,0x6a,0xa9, + 0x86,0x7d,0xce,0x6b,0x39,0xf6,0xae,0x7c,0xb5,0x06,0x31,0xdf,0xc0,0xf8,0xbb,0x95, + 0x6b,0x4b,0x1c,0x1e,0x19,0x17,0x46,0x92,0x9f,0xb3,0xee,0x0e,0x1c,0xfb,0x09,0x72, + 0xef,0x2a,0xaf,0xc2,0x22,0xe2,0x42,0x23,0xec,0x08,0xb2,0xab,0x33,0x3b,0x1b,0x7d, + 0x5b,0xb9,0xf1,0x76,0x05,0x59,0x11,0x53,0xb9,0x36,0x8e,0x8d,0x5e,0x83,0x15,0xce, + 0x86,0x46,0xc4,0xdc,0x8a,0x48,0x00,0x1a,0x68,0x43,0xc3,0xa2,0x43,0x22,0x92,0x42, + 0xc3,0x63,0xc3,0x62,0x92,0x42,0x12,0x44,0xe1,0x69,0xc5,0xa1,0x79,0x6d,0x61,0xc5, + 0x63,0x41,0xb2,0xe5,0x60,0x19,0xf3,0x46,0x3c,0x2c,0x01,0xe4,0xed,0x78,0x30,0x12, + 0xac,0x5c,0x09,0xb6,0xf7,0x9a,0xbc,0x7b,0x05,0xa8,0x09,0x37,0x88,0x69,0x60,0xc8, + 0x4d,0x39,0x8b,0xc0,0xa0,0x7c,0x39,0x48,0xbe,0x0c,0x23,0xc1,0x04,0xbf,0xa1,0x40, + 0xb0,0xea,0x32,0x1c,0xe4,0x3c,0x6e,0x0a,0x9c,0xa5,0xbe,0x0a,0xb2,0x44,0x60,0x21, + 0x2c,0xc7,0x59,0xa0,0x84,0xd3,0xab,0x8c,0xe1,0x40,0x17,0x9a,0xb5,0x92,0xaf,0x00, + 0x43,0x7f,0xe9,0x12,0x10,0xf8,0x94,0x2d,0x7a,0x95,0x2d,0x7a,0x96,0x2d,0x7a,0x94, + 0x2e,0xba,0x15,0x2d,0xba,0x15,0x2e,0xf8,0x49,0x17,0x12,0x6a,0x96,0x2a,0xfa,0x57, + 0xfb,0x66,0x4d,0x0b,0xab,0x5f,0x7e,0xb5,0xfa,0x1b,0x86,0xe5,0xd5,0x65,0x8d,0x4e, + 0xd3,0xde,0xd9,0x25,0xcc,0x15,0x87,0x47,0x46,0x07,0xde,0x08,0xf1,0xf1,0x0d,0x70, + 0xf5,0xf4,0x71,0x71,0xf5,0x80,0x43,0xb1,0xa3,0x93,0xb3,0xe3,0x55,0x17,0x07,0x47, + 0x67,0x47,0xa7,0xeb,0x8e,0x57,0xaf,0x3b,0x39,0xbb,0x39,0x5d,0x73,0x83,0xea,0xec, + 0xec,0xe2,0x01,0xed,0x35,0x44,0x3c,0x5d,0x5c,0xbd,0x00,0xdc,0xdc,0xa1,0xf5,0x86, + 0x71,0x82,0x78,0x5d,0x77,0xf3,0xba,0xee,0xea,0x8d,0xad,0x9b,0x97,0x8b,0x9b,0xf7, + 0x75,0xa4,0xf1,0x26,0x94,0x64,0xd0,0x95,0x01,0xda,0x75,0x25,0x70,0xdd,0xd5,0xf3, + 0x3a,0x70,0x73,0x23,0x04,0x2e,0x1e,0x74,0x21,0xb2,0x72,0x71,0xbf,0xee,0xea,0x65, + 0xdd,0x45,0xf0,0x66,0x45,0x7b,0x62,0x97,0x2e,0x21,0x83,0xce,0x48,0xc3,0xcc,0x5e, + 0x77,0xf5,0xc0,0x41,0x10,0xe1,0xce,0xa8,0x01,0x4a,0x12,0x04,0x18,0x52,0x3e,0x9e, + 0xae,0x6e,0x8c,0x5c,0xe7,0xcf,0x26,0xd7,0xc5,0x8d,0xb1,0xc8,0xc5,0xd5,0x9d,0x32, + 0xbf,0x43,0xb9,0xd7,0x19,0xbf,0x51,0xdc,0xdd,0x85,0x95,0x6b,0xee,0xf2,0x5c,0x87, + 0x72,0xc9,0x12,0x32,0x4e,0x99,0xbb,0xbb,0xba,0x71,0x8e,0xfd,0xa2,0xec,0x75,0x71, + 0xfd,0x04,0xb9,0x34,0xe2,0x5c,0xb8,0xa9,0x5c,0x1a,0x5f,0x17,0x92,0x09,0x9c,0x38, + 0x3a,0xce,0x00,0x95,0x62,0x99,0x2a,0x9c,0xbd,0x44,0x84,0xb5,0xaf,0x78,0xde,0x70, + 0x67,0x4c,0xe3,0x19,0x0e,0x59,0x04,0xf4,0x8c,0x14,0xea,0x58,0x1b,0x41,0x98,0x6c, + 0x40,0x63,0x93,0xa2,0x36,0x72,0xcd,0xa9,0x68,0xab,0xa4,0x2b,0x26,0xc0,0x9a,0x4a, + 0x5a,0x07,0xd4,0x95,0xe1,0xe6,0xc2,0x7a,0xcc,0x85,0xe7,0xae,0xdb,0xfb,0xd9,0x6e, + 0x50,0xe8,0x46,0xb3,0x4d,0x42,0xda,0x75,0x75,0x47,0xc4,0x95,0x65,0xee,0xea,0xe6, + 0x41,0x23,0x65,0xb9,0x07,0x3d,0xaf,0xd3,0x9d,0xeb,0xc6,0x68,0x62,0xb3,0x71,0xac, + 0x37,0xac,0xb5,0x5c,0x57,0xf3,0x5a,0x7e,0xd7,0xcd,0xc3,0xcb,0xd9,0x95,0x38,0x07, + 0x63,0x01,0xa9,0xe8,0xe3,0xe2,0xe6,0x79,0xdd,0x3d,0xc0,0xc5,0xeb,0x96,0x8b,0x5f, + 0xe4,0xb5,0xa0,0x44,0xd7,0x30,0x91,0x7b,0xac,0xea,0x6a,0x5a,0x9f,0xa3,0x60,0xfc, + 0x9a,0x58,0xe7,0x24,0x99,0x77,0x2e,0x30,0x38,0x89,0x11,0x1c,0xc5,0x0c,0x82,0x78, + 0x1e,0x82,0x93,0xf8,0xde,0x06,0x6a,0x82,0x5d,0x43,0xae,0x4a,0x10,0xac,0x06,0x9d, + 0xf3,0xe7,0x6c,0x29,0x9d,0x25,0x0b,0x9f,0x88,0xd8,0x8a,0xb8,0x96,0x4f,0x10,0x22, + 0xc2,0x21,0xd7,0xe0,0x5a,0x60,0x1e,0x77,0x29,0x5c,0xf0,0x2a,0x32,0xf8,0x96,0x2c, + 0x04,0x4a,0x17,0x6f,0xc9,0x17,0xa2,0xaa,0x16,0x13,0xaa,0x96,0xb2,0x9b,0x56,0x6a, + 0x87,0x8d,0xd3,0xf3,0x46,0xc3,0xaa,0xe9,0xef,0x3f,0x29,0xfa,0x2b,0xc3,0xca,0xea, + 0x8a,0x61,0x71,0x49,0xa3,0xd3,0x4e,0x4c,0x4d,0x0d,0x0e,0xa9,0xbb,0x7a,0xba,0x9b, + 0x9a,0xdb,0x55,0x15,0x15,0x85,0xc5,0xa5,0xb9,0xe2,0xfc,0x3c,0x09,0x03,0xe2,0xfc, + 0x42,0x84,0x82,0x02,0x49,0x41,0x31,0x74,0x25,0x05,0x85,0x00,0xe2,0x7c,0xe8,0x16, + 0xe5,0x49,0x0a,0xfe,0x5f,0x7b,0x75,0xd0,0xda,0x36,0x0c,0x05,0x00,0xf8,0xff,0xff, + 0x9d,0xb6,0x89,0x65,0x99,0x30,0x56,0x76,0x18,0x8c,0x41,0x21,0xb1,0xc7,0x0e,0xa3, + 0xb0,0xc3,0x60,0x3b,0xb4,0x30,0x36,0x12,0xb7,0x39,0x4c,0xb6,0xec,0xd4,0x49,0x9b, + 0xac,0x2b,0xec,0xb0,0xf1,0xc1,0x87,0x78,0xcf,0x96,0xf4,0x9e,0x8c,0x42,0xe6,0xa1, + 0xea,0xd2,0xb2,0x0b,0xba,0xb1,0x9b,0x56,0xe5,0xb7,0xc3,0xcc,0x9d,0xfe,0xe1,0xbc, + 0x7f,0xd8,0xab,0xc6,0x27,0x0f,0xe3,0x64,0xfe,0x41,0x1a,0xc7,0x85,0xd5,0x64,0x61, + 0x9c,0x96,0x18,0xf6,0xcc,0x0b,0x63,0xdf,0x4f,0xd8,0x6f,0x26,0xe6,0x69,0x0f,0x75, + 0x73,0xcf,0x2f,0xae,0x9b,0xaa,0x4c,0xd2,0x45,0xf7,0xf6,0x79,0x75,0x9f,0x3a,0x42, + 0x5a,0x3b,0x49,0xc3,0x70,0xae,0xa1,0xee,0x7e,0x57,0xbb,0x53,0xe7,0x93,0xfe,0xc5, + 0xf3,0x9e,0xac,0xbb,0xdb,0x6d,0x5a,0x77,0x3e,0xf6,0x3f,0x96,0x1b,0xda,0xc8,0x77, + 0x63,0xd8,0x27,0x2e,0x0e,0xae,0xca,0x6f,0xee,0xc6,0xee,0x6d,0x7c,0x5e,0x1b,0xf1, + 0x78,0xa1,0x93,0x75,0x0f,0x0a,0xbd,0xb0,0xc9,0xa7,0xee,0xe4,0xa3,0x9d,0x4f,0x7d, + 0xe7,0x3f,0xbb,0xfc,0x63,0x9a,0x82,0xd0,0x5f,0xa1,0xfd,0xdf,0xc2,0xfe,0x45,0x0a, + 0xe5,0x5e,0xcf,0x47,0x26,0x1f,0xab,0x7b,0x70,0xde,0xe9,0x27,0x9d,0x85,0xd0,0xf7, + 0x50,0x85,0xf8,0xaa,0x5a,0x5c,0xc6,0xd7,0xef,0xc2,0x65,0x1d,0xdf,0x5e,0x97,0xef, + 0xbf,0xce,0xae,0x6e,0x8b,0xe5,0x8f,0x62,0xb5,0x2e,0x9a,0x76,0x5e,0xb7,0x65,0xbd, + 0x99,0x37,0x6d,0xfc,0xd0,0x05,0x5d,0x5c,0xb7,0x29,0xcd,0xf1,0x2c,0x8d,0xcd,0x26, + 0xc7,0x65,0x8e,0xff,0xcd,0x34,0x9f,0xa8,0x48,0x67,0x4c,0xc1,0xa3,0xf4,0x60,0xf2, + 0xc5,0x6a,0x7d,0xd1,0x7f,0x96,0x21,0xad,0xdb,0x62,0xd5,0x8d,0xf9,0xe1,0xf9,0x18, + 0x9c,0xad,0xfa,0xa0,0xe9,0x82,0x59,0xdd,0x86,0x26,0x8d,0xc3,0xce,0x39,0x0d,0xcb, + 0xf5,0x59,0x5a,0xdb,0xb4,0xe7,0xcb,0x4d,0x1a,0xfb,0x1d,0xd2,0x3e,0x9b,0xf4,0xa9, + 0xdf,0x7c,0x6a,0xaf,0x3e,0xdf,0x7d,0xfc,0x76,0x7f,0x7d,0xb3,0xfd,0xf2,0x7d,0x7b, + 0xfb,0xf3,0x7e,0x7d,0xb7,0x4d,0xb6,0xfe,0x73,0x01,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xfe,0x6b,0xbf,0x00,0xff,0xcf,0xfd,0x4c,0x36,0x10,0x0e, + 0x00, diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds new file mode 100644 index 0000000..f7a20d1 --- /dev/null +++ b/board/esd/hh405/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile new file mode 100644 index 0000000..a60495a --- /dev/null +++ b/board/esd/hub405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/hub405/config.mk b/board/esd/hub405/config.mk new file mode 100644 index 0000000..a6d31aa --- /dev/null +++ b/board/esd/hub405/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd HUB405 boards +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/hub405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i +#include +#include +#include + + +extern void lxt971_no_sleep(void); + + +int board_revision(void) +{ + unsigned long osrl_reg; + unsigned long isr1l_reg; + unsigned long tcr_reg; + unsigned long value; + + /* + * Get version of HUB405 board from GPIO's + */ + + /* + * Setup GPIO pin(s) (IRQ6/GPIO23) + */ + osrl_reg = in32(GPIO0_OSRH); + isr1l_reg = in32(GPIO0_ISR1H); + tcr_reg = in32(GPIO0_TCR); + out32(GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */ + out32(GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */ + out32(GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */ + + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x00000100; /* get config bits */ + + /* + * Restore GPIO settings + */ + out32(GPIO0_OSRH, osrl_reg); /* output select */ + out32(GPIO0_ISR1H, isr1l_reg); /* input select */ + out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ + + if (value & 0x00000100) { + /* Revision 1.1 or 1.2 detected */ + return 1; + } + + /* Revision 1.0 */ + return 0; +} + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + return 0; +} + + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4); + volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4); + volatile unsigned char *led_reg = (unsigned char *)((ulong)DUART0_BA + 0x20); + unsigned long val; + int delay, flashcnt; + char *str; + char hw_rev[4]; + + /* + * Enable interrupts in exar duart mcr[3] + */ + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; + *duart2_mcr = 0x08; + *duart3_mcr = 0x08; + + /* + * Set RS232/RS422 control (RS232 = high on GPIO) + */ + val = in32(GPIO0_OR); + val &= ~(CFG_UART2_RS232 | CFG_UART3_RS232 | CFG_UART4_RS232 | CFG_UART5_RS232); + + str = getenv("phys0"); + if (!str || (str && (str[0] == '0'))) + val |= CFG_UART2_RS232; + + str = getenv("phys1"); + if (!str || (str && (str[0] == '0'))) + val |= CFG_UART3_RS232; + + str = getenv("phys2"); + if (!str || (str && (str[0] == '0'))) + val |= CFG_UART4_RS232; + + str = getenv("phys3"); + if (!str || (str && (str[0] == '0'))) + val |= CFG_UART5_RS232; + + out32(GPIO0_OR, val); + + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + + /* + * check board type and setup AP power + */ + str = getenv("bd_type"); /* this is only set on non prototype hardware */ + if (str != NULL) { + if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) { + unsigned char led_reg_default = 0; + str = getenv("ap_pwr"); + if (!str || (str && (str[0] == '1'))) + led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */ + + /* + * Flash LEDs + */ + for (flashcnt = 0; flashcnt < 3; flashcnt++) { + *led_reg = led_reg_default; /* LED_A..D off */ + for (delay = 0; delay < 100; delay++) + udelay(1000); + *led_reg = led_reg_default | 0xf0; /* LED_A..D on */ + for (delay = 0; delay < 50; delay++) + udelay(1000); + } + *led_reg = led_reg_default; + } + } + + /* + * Reset external DUARTs + */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + udelay(10); /* wait 10us */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + udelay(1000); /* wait 1ms */ + + /* + * Store hardware revision in environment for further processing + */ + sprintf(hw_rev, "1.%ld", gd->board_type); + setenv("hw_rev", hw_rev); + return (0); +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming HUB405"); + } else { + puts(str); + } + + if (getenv_r("bd_type", str, sizeof(str)) != -1) { + printf(" (%s", str); + } else { + puts(" (Missing bd_type!"); + } + + gd->board_type = board_revision(); + printf(", Rev 1.%ld)\n", gd->board_type); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds new file mode 100644 index 0000000..98338e9 --- /dev/null +++ b/board/esd/hub405/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile new file mode 100644 index 0000000..b3039c6 --- /dev/null +++ b/board/esd/ocrtc/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c new file mode 100644 index 0000000..ffbb4ad --- /dev/null +++ b/board/esd/ocrtc/cmd_ocrtc.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include <405gp_pci.h> + + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +/* + * Set device number on pci board + */ +int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int idx = 1; /* start at 1 (skip device 0) */ + pci_dev_t bdf = 0; + u32 addr; + + while (bdf >= 0) { + if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) { + break; + } + printf("Found device nr %d at %x!\n", idx-1, bdf); + pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr); + addr &= ~0xf; + *(u32 *)addr = (bdf & 0x0000f800) >> 11; + printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr); + } + + return 0; +} +U_BOOT_CMD( + setdevice, 1, 1, do_setdevice, + "setdevice - Set device number on pci adapter boards\n", + NULL +); + + +/* + * Get device number on pci board + */ +int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u32 device; + char str[32]; + + device = *(u32 *)0x0; + device = 0x16 - device; /* calculate vxworks bp slot id */ + sprintf(str, "%d", device); + setenv("slot", str); + printf("Variabel slot set to %x\n", device); + + return 0; +} +U_BOOT_CMD( + getdevice, 1, 1, do_getdevice, + "getdevice - Get device number and set slot env variable\n", + NULL +); + +#endif diff --git a/board/esd/ocrtc/config.mk b/board/esd/ocrtc/config.mk new file mode 100644 index 0000000..f123319 --- /dev/null +++ b/board/esd/ocrtc/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFFD0000 diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c new file mode 100644 index 0000000..c3d8bec --- /dev/null +++ b/board/esd/ocrtc/flash.c @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + base_b0 = FLASH_BASE0_PRELIM; + size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + base_b1 = FLASH_BASE1_PRELIM; + size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); + + /* Re-do sizing to get full correct info */ + + if (size_b1) { + mtdcr (ebccfga, pb0cr); + pbcr = mfdcr (ebccfgd); + mtdcr (ebccfga, pb0cr); + base_b1 = -size_b1; + switch (size_b1) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + } + pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17); + mtdcr (ebccfgd, pbcr); + /* printf("pb1cr = %x\n", pbcr); */ + } + + if (size_b0) { + mtdcr (ebccfga, pb1cr); + pbcr = mfdcr (ebccfgd); + mtdcr (ebccfga, pb1cr); + base_b0 = base_b1 - size_b0; + switch (size_b1) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + } + pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); + mtdcr (ebccfgd, pbcr); + /* printf("pb0cr = %x\n", pbcr); */ + } + + size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); + + flash_get_offsets (base_b0, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); + + flash_get_offsets (base_b1, &flash_info[1]); + + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + base_b1 + size_b1 - monitor_flash_len, + base_b1 + size_b1 - 1, &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + flash_protect (FLAG_PROTECT_CLEAR, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c new file mode 100644 index 0000000..261b8a5 --- /dev/null +++ b/board/esd/ocrtc/ocrtc.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "ocrtc.h" +#include +#include +#include + + +extern void lxt971_no_sleep(void); + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: clear EBTC -> high-Z ebc signals between + * transfers, set device-paced timeout to 256 cycles + */ + mtebc (epcr, 0x20400000); + + return 0; +} + + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (i == -1) { +#ifdef CONFIG_OCRTC + puts ("### No HW ID - assuming OCRTC"); +#endif +#ifdef CONFIG_ORSG + puts ("### No HW ID - assuming ORSG"); +#endif + } else { + puts (str); + } + + putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return (0); +} + + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr (memcfga, mem_mb0cf); + val = mfdcr (memcfgd); + +#if 0 + printf ("\nmb0cf=%x\n", val); /* test-only */ + printf ("strap=%x\n", mfdcr (strap)); /* test-only */ +#endif + + return (4 * 1024 * 1024 << ((val & 0x000e0000) >> 17)); +} + + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} diff --git a/board/esd/ocrtc/ocrtc.h b/board/esd/ocrtc/ocrtc.h new file mode 100644 index 0000000..b50d521 --- /dev/null +++ b/board/esd/ocrtc/ocrtc.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds new file mode 100644 index 0000000..476b4a0 --- /dev/null +++ b/board/esd/ocrtc/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile new file mode 100644 index 0000000..6db564f --- /dev/null +++ b/board/esd/pci405/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o cmd_pci405.o +SOBJS = writeibm.o + +$(LIB): $(OBJS) $(SOBJS) +# $(AR) crv $@ $(OBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c new file mode 100644 index 0000000..0315c3d --- /dev/null +++ b/board/esd/pci405/cmd_pci405.c @@ -0,0 +1,985 @@ +/* + * (C) Copyright 2002-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include <405gp_pci.h> +#include + +#include "pci405.h" + + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +extern int do_bootm (cmd_tbl_t *, int, int, char *[]); +extern int do_bootvx (cmd_tbl_t *, int, int, char *[]); +unsigned long get_dcr(unsigned short); + + +/* + * Command loadpci: wait for signal from host and boot image. + */ +int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int *ptr = 0; + int count = 0; + int count2 = 0; + int status; + int i; + char addr[16]; + char str[] = "\\|/-"; + char *local_args[2]; + + /* + * Mark sync address + */ + ptr = 0; + *ptr = 0xffffffff; + puts("\nWaiting for image from pci host -"); + + /* + * Wait for host to write the start address + */ + while (*ptr == 0xffffffff) { + count++; + if (!(count % 100)) { + count2++; + putc(0x08); /* backspace */ + putc(str[count2 % 4]); + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + udelay(1000); + } + + if (*ptr == PCI_RECONFIG_MAGIC) { + /* + * Save own pci configuration in PRAM + */ + memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN); + ptr = (unsigned int *)PCI_REGS_ADDR + 1; + for (i=0; i<0x40; i+=4) { + pci_read_config_dword(PCIDEVID_405GP, i, ptr++); + } + ptr = (unsigned int *)PCI_REGS_ADDR; + *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4); + + printf("\nStoring PCI Configuration Regs...\n"); + } else { + sprintf(addr, "%08x", *ptr); + +#if 0 + /* + * Boot image + */ + if (*ptr & 0x00000001) { + /* + * Boot VxWorks image via bootvx + */ + addr[strlen(addr)-1] = '0'; + printf("\nBooting VxWorks-Image at addr 0x%s ...\n", addr); + setenv("loadaddr", addr); + + local_args[0] = argv[0]; + local_args[1] = NULL; + status = do_bootvx (cmdtp, 0, 1, local_args); + } else { + /* + * Boot image via bootm (normally Linux) + */ + printf("\nBooting Image at addr 0x%s ...\n", addr); + setenv("loadaddr", addr); + + local_args[0] = argv[0]; + local_args[1] = NULL; + status = do_bootm (cmdtp, 0, 1, local_args); + } +#else + /* + * Boot image via bootm + */ + printf("\nBooting Image at addr 0x%s ...\n", addr); + setenv("loadaddr", addr); + + local_args[0] = argv[0]; + local_args[1] = NULL; + status = do_bootm (cmdtp, 0, 1, local_args); +#endif + } + + return 0; +} +U_BOOT_CMD( + loadpci, 1, 1, do_loadpci, + "loadpci - Wait for pci-image and boot it\n", + NULL +); + +#endif + +#if 1 /* test-only */ +int do_getpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int val; + int i; + + printf("\nPCI Configuration Regs for PPC405GP:"); + for (i=0; i<0x64; i+=4) { + pci_read_config_dword(PCIDEVID_405GP, i, &val); + if (!(i % 0x10)) { + printf("\n%02x: ", i); + } + printf("%08x ", val); + } + printf("\n"); + + return 0; +} +U_BOOT_CMD( + getpci, 1, 1, do_getpci, + "getpci - Print own pci configuration registers\n", + NULL +); + +int do_setpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int addr; + unsigned int val; + + addr = simple_strtol (argv[1], NULL, 16); + val = simple_strtol (argv[2], NULL, 16); + + printf("\nWriting %08x to PCI reg %08x.\n", val, addr); + pci_write_config_dword(PCIDEVID_405GP, addr, val); + + return 0; +} +U_BOOT_CMD( + setpci, 3, 1, do_setpci, + "setpci - Set one pci configuration lword\n", + " \n" + " - Write pci configuration lword to .\n" +); + +int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + + printf("\nDevice Configuration Registers (DCR's) for PPC405GP:"); + for (i=0; i<=0x1e0; i++) { + if (!(i % 0x8)) { + printf("\n%04x ", i); + } + printf("%08lx ", get_dcr(i)); + } + printf("\n"); + + return 0; +} +U_BOOT_CMD( + dumpdcr, 1, 1, do_dumpdcr, + "dumpdcr - Dump all DCR registers\n", + NULL +); + + +int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:"); + printf("\n%04x %08x ", 947, mfspr(947)); + printf("\n%04x %08x ", 9, mfspr(9)); + printf("\n%04x %08x ", 1014, mfspr(1014)); + printf("\n%04x %08x ", 1015, mfspr(1015)); + printf("\n%04x %08x ", 1010, mfspr(1010)); + printf("\n%04x %08x ", 957, mfspr(957)); + printf("\n%04x %08x ", 1008, mfspr(1008)); + printf("\n%04x %08x ", 1018, mfspr(1018)); + printf("\n%04x %08x ", 954, mfspr(954)); + printf("\n%04x %08x ", 950, mfspr(950)); + printf("\n%04x %08x ", 951, mfspr(951)); + printf("\n%04x %08x ", 981, mfspr(981)); + printf("\n%04x %08x ", 980, mfspr(980)); + printf("\n%04x %08x ", 982, mfspr(982)); + printf("\n%04x %08x ", 1012, mfspr(1012)); + printf("\n%04x %08x ", 1013, mfspr(1013)); + printf("\n%04x %08x ", 948, mfspr(948)); + printf("\n%04x %08x ", 949, mfspr(949)); + printf("\n%04x %08x ", 1019, mfspr(1019)); + printf("\n%04x %08x ", 979, mfspr(979)); + printf("\n%04x %08x ", 8, mfspr(8)); + printf("\n%04x %08x ", 945, mfspr(945)); + printf("\n%04x %08x ", 987, mfspr(987)); + printf("\n%04x %08x ", 287, mfspr(287)); + printf("\n%04x %08x ", 953, mfspr(953)); + printf("\n%04x %08x ", 955, mfspr(955)); + printf("\n%04x %08x ", 272, mfspr(272)); + printf("\n%04x %08x ", 273, mfspr(273)); + printf("\n%04x %08x ", 274, mfspr(274)); + printf("\n%04x %08x ", 275, mfspr(275)); + printf("\n%04x %08x ", 260, mfspr(260)); + printf("\n%04x %08x ", 276, mfspr(276)); + printf("\n%04x %08x ", 261, mfspr(261)); + printf("\n%04x %08x ", 277, mfspr(277)); + printf("\n%04x %08x ", 262, mfspr(262)); + printf("\n%04x %08x ", 278, mfspr(278)); + printf("\n%04x %08x ", 263, mfspr(263)); + printf("\n%04x %08x ", 279, mfspr(279)); + printf("\n%04x %08x ", 26, mfspr(26)); + printf("\n%04x %08x ", 27, mfspr(27)); + printf("\n%04x %08x ", 990, mfspr(990)); + printf("\n%04x %08x ", 991, mfspr(991)); + printf("\n%04x %08x ", 956, mfspr(956)); + printf("\n%04x %08x ", 284, mfspr(284)); + printf("\n%04x %08x ", 285, mfspr(285)); + printf("\n%04x %08x ", 986, mfspr(986)); + printf("\n%04x %08x ", 984, mfspr(984)); + printf("\n%04x %08x ", 256, mfspr(256)); + printf("\n%04x %08x ", 1, mfspr(1)); + printf("\n%04x %08x ", 944, mfspr(944)); + printf("\n"); + + return 0; +} +U_BOOT_CMD( + dumpspr, 1, 1, do_dumpspr, + "dumpspr - Dump all SPR registers\n", + NULL +); + + +#define PCI0_BRDGOPT1 0x4a +#define plb0_acr 0x87 + +int do_getplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short val; + + printf("PLB0_ACR=%08lx\n", get_dcr(0x87)); + pci_read_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, &val); + printf("PCI0_BRDGOPT1=%04x\n", val); + printf("CCR0=%08x\n", mfspr(ccr0)); + + return 0; +} +U_BOOT_CMD( + getplb, 1, 1, do_getplb, + "getplb - Dump all plb arbiter registers\n", + NULL +); + +int do_setplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int my_acr; + unsigned int my_brdgopt1; + unsigned int my_ccr0; + + my_acr = simple_strtol (argv[1], NULL, 16); + my_brdgopt1 = simple_strtol (argv[2], NULL, 16); + my_ccr0 = simple_strtol (argv[3], NULL, 16); + + mtdcr(plb0_acr, my_acr); + pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, my_brdgopt1); + mtspr(ccr0, my_ccr0); + + return 0; +} +U_BOOT_CMD( + setplb, 4, 1, do_setplb, + "setplb - Set all plb arbiter registers\n", + "PLB0_ACR PCI0_BRDGOPT1 CCR0\n" + " - Set all plb arbiter registers\n" +); + + +/*********************************************************************** + * + * The following code is only for test purposes!!!! + * Please ignore this ugly stuff!!!!!!!!!!!!!!!!!!! + * + ***********************************************************************/ + +#define PCI_ADDR 0xc0000000 + +int do_writepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int addr; + unsigned int size; + unsigned int countmax; + int i; + int max; + volatile unsigned long *ptr; + volatile unsigned long val; + int loopcount = 0; + int test_pci_read = 0; + int test_pci_cfg_write = 0; + int test_sync = 0; + int test_pci_pre_read = 0; + + addr = simple_strtol (argv[1], NULL, 16); + size = simple_strtol (argv[2], NULL, 16); + countmax = simple_strtol (argv[3], NULL, 16); + if (countmax == 0) + countmax = 1000; + + do_getplb(NULL, 0, 0, NULL); + +#if 0 + out32r(PMM0LA, 0); + out32r(PMM0PCILA, 0); + out32r(PMM0PCIHA, 0); + out32r(PMM0MA, 0); + out32r(PMM1LA, PCI_ADDR); + out32r(PMM1PCILA, addr & 0xff000000); + out32r(PMM1PCIHA, 0x00000000); + out32r(PMM1MA, 0xff000001); +#endif + + printf("PMM1LA =%08lx\n", in32r(PMM1LA)); + printf("PMM1MA =%08lx\n", in32r(PMM1MA)); + printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); + printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); + + addr = PCI_ADDR | (addr & 0x00ffffff); + printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); + + max = size >> 2; + + pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ + + val = *(ulong *)0x00000000; + if (val & 0x00000008) { + test_pci_pre_read = 1; + printf("Running test with pre pci-memory-read access!\n"); + } + if (val & 0x00000004) { + test_sync = 1; + printf("Running test with sync instruction!\n"); + } + if (val & 0x00000001) { + test_pci_read = 1; + printf("Running test with pci-memory-read access!\n"); + } + if (val & 0x00000002) { + test_pci_cfg_write = 1; + printf("Running test with pci-config-write access!\n"); + } + + while (1) { + + if (test_pci_pre_read) { + /* + * Read one value back + */ + ptr = (volatile unsigned long *)addr; + val = *ptr; + } + + /* + * Write some values to host via pci busmastering + */ + ptr = (volatile unsigned long *)addr; + for (i=0; i countmax) { + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + putc('.'); + + loopcount = 0; + } + } + + return 0; +} +U_BOOT_CMD( + writepci, 4, 1, do_writepci, + "writepci - Write some data to pcibus\n", + " \n" + " - Write some data to pcibus.\n" +); + +#define PCI_CFGADDR 0xeec00000 +#define PCI_CFGDATA 0xeec00004 + +int ibmPciConfigWrite +( + int offset, /* offset into the configuration space */ + int width, /* data width */ + unsigned int data /* data to be written */ + ) +{ + /* + * Write config register address to the PCI config address register + * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation) + */ + out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC)); + +#if 0 /* test-only */ + ppcSync(); +#endif + + /* + * Write value to be written to the PCI config data register + */ + switch ( width ) { + case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF)); + break; + case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF)); + break; + case 4: out32r(PCI_CFGDATA | (offset & 0x3), data); + break; + } + + return (0); +} + +int do_writepci2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int addr; + unsigned int size; + unsigned int countmax; + int max; + volatile unsigned long *ptr; + volatile unsigned long val; + int loopcount = 0; + + addr = simple_strtol (argv[1], NULL, 16); + size = simple_strtol (argv[2], NULL, 16); + countmax = simple_strtol (argv[3], NULL, 16); + if (countmax == 0) + countmax = 1000; + + do_getplb(NULL, 0, 0, NULL); + +#if 0 + out32r(PMM0LA, 0); + out32r(PMM0PCILA, 0); + out32r(PMM0PCIHA, 0); + out32r(PMM0MA, 0); + out32r(PMM1LA, PCI_ADDR); + out32r(PMM1PCILA, addr & 0xff000000); + out32r(PMM1PCIHA, 0x00000000); + out32r(PMM1MA, 0xff000001); +#endif + + printf("PMM1LA =%08lx\n", in32r(PMM1LA)); + printf("PMM1MA =%08lx\n", in32r(PMM1MA)); + printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); + printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); + + addr = PCI_ADDR | (addr & 0x00ffffff); + printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); + + max = size >> 2; + + pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ + + while (1) { + + /* + * Write one values to host via pci busmastering + */ + ptr = (volatile unsigned long *)addr; + *ptr = 0x01234567; + + /* + * Read one value back + */ + ptr = (volatile unsigned long *)addr; + val = *ptr; + + /* + * One pci config write + */ +/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */ +/* ibmPciConfigWrite(0x44, 1, 0x00); */ + ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */ + + if (loopcount++ > countmax) { + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + putc('.'); + + loopcount = 0; + } + } + + return 0; +} +U_BOOT_CMD( + writepci2, 4, 1, do_writepci2, + "writepci2- Write some data to pcibus\n", + " \n" + " - Write some data to pcibus.\n" +); + +int do_writepci22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int addr; + unsigned int size; + unsigned int countmax = 0; + volatile unsigned long *ptr; + volatile unsigned long val; + + addr = simple_strtol (argv[1], NULL, 16); + size = simple_strtol (argv[2], NULL, 16); + + addr = PCI_ADDR | (addr & 0x00ffffff); + printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); + pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ + + while (1) { + + /* + * Write one values to host via pci busmastering + */ + ptr = (volatile unsigned long *)addr; + *ptr = 0x01234567; + + /* + * Read one value back + */ + ptr = (volatile unsigned long *)addr; + val = *ptr; + + /* + * One pci config write + */ + ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */ + } + + return 0; +} +U_BOOT_CMD( + writepci22, 4, 1, do_writepci22, + "writepci22- Write some data to pcibus\n", + " \n" + " - Write some data to pcibus.\n" +); + +int ibmPciConfigWrite3 +( + int offset, /* offset into the configuration space */ + int width, /* data width */ + unsigned int data /* data to be written */ + ) +{ + /* + * Write config register address to the PCI config address register + * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation) + */ + out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC)); + +#if 1 /* test-only */ + ppcSync(); +#endif + + /* + * Write value to be written to the PCI config data register + */ + switch ( width ) { + case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF)); + break; + case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF)); + break; + case 4: out32r(PCI_CFGDATA | (offset & 0x3), data); + break; + } + + return (0); +} + +int do_writepci3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int addr; + unsigned int size; + unsigned int countmax; + int max; + volatile unsigned long *ptr; + volatile unsigned long val; + int loopcount = 0; + + addr = simple_strtol (argv[1], NULL, 16); + size = simple_strtol (argv[2], NULL, 16); + countmax = simple_strtol (argv[3], NULL, 16); + if (countmax == 0) + countmax = 1000; + + do_getplb(NULL, 0, 0, NULL); + +#if 0 + out32r(PMM0LA, 0); + out32r(PMM0PCILA, 0); + out32r(PMM0PCIHA, 0); + out32r(PMM0MA, 0); + out32r(PMM1LA, PCI_ADDR); + out32r(PMM1PCILA, addr & 0xff000000); + out32r(PMM1PCIHA, 0x00000000); + out32r(PMM1MA, 0xff000001); +#endif + + printf("PMM1LA =%08lx\n", in32r(PMM1LA)); + printf("PMM1MA =%08lx\n", in32r(PMM1MA)); + printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); + printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); + + addr = PCI_ADDR | (addr & 0x00ffffff); + printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); + + max = size >> 2; + + pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ + + while (1) { + + /* + * Write one values to host via pci busmastering + */ + ptr = (volatile unsigned long *)addr; + *ptr = 0x01234567; + + /* + * Read one value back + */ + ptr = (volatile unsigned long *)addr; + val = *ptr; + + /* + * One pci config write + */ +/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */ +/* ibmPciConfigWrite(0x44, 1, 0x00); */ + ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */ + + if (loopcount++ > countmax) { + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + putc('.'); + + loopcount = 0; + } + } + + return 0; +} +U_BOOT_CMD( + writepci3, 4, 1, do_writepci3, + "writepci3- Write some data to pcibus\n", + " \n" + " - Write some data to pcibus.\n" +); + + +#define SECTOR_SIZE 32 /* 32 byte cache line */ +#define SECTOR_MASK 0x1F + +void my_flush_dcache(ulong lcl_addr, ulong count) +{ + unsigned int lcl_target; + + /* promote to nearest cache sector */ + lcl_target = (lcl_addr + count + SECTOR_SIZE - 1) & ~SECTOR_MASK; + lcl_addr &= ~SECTOR_MASK; + while (lcl_addr != lcl_target) + { + /* ppcDcbf((void *)lcl_addr);*/ + __asm__("dcbf 0,%0": :"r" (lcl_addr)); + lcl_addr += SECTOR_SIZE; + } + __asm__("sync"); /* Always flush prefetch queue in any case */ +} + +int do_writepci_cache(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int addr; + unsigned int size; + unsigned int countmax; + int i; + volatile unsigned long *ptr; + volatile unsigned long val; + int loopcount = 0; + + addr = simple_strtol (argv[1], NULL, 16); + size = simple_strtol (argv[2], NULL, 16); + countmax = simple_strtol (argv[3], NULL, 16); + if (countmax == 0) + countmax = 1000; + + do_getplb(NULL, 0, 0, NULL); + +#if 0 + out32r(PMM0LA, 0); + out32r(PMM0PCILA, 0); + out32r(PMM0PCIHA, 0); + out32r(PMM0MA, 0); + out32r(PMM1LA, PCI_ADDR); + out32r(PMM1PCILA, addr & 0xff000000); + out32r(PMM1PCIHA, 0x00000000); + out32r(PMM1MA, 0xff000001); +#endif + + printf("PMM1LA =%08lx\n", in32r(PMM1LA)); + printf("PMM1MA =%08lx\n", in32r(PMM1MA)); + printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); + printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); + + addr = PCI_ADDR | (addr & 0x00ffffff); + printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); + + pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ + + i = 0; + + /* + * Set pci region as cachable + */ + ppcSync(); + __asm__ volatile (" addis 4,0,0x0000 "); + __asm__ volatile (" addi 4,4,0x0080 "); + __asm__ volatile (" mtdccr 4 "); + ppcSync(); + + while (1) { + + /* + * Write one values to host via pci busmastering + */ + ptr = (volatile unsigned long *)addr; + printf("A\n"); /* test-only */ + *ptr++ = i++; + *ptr++ = i++; + *ptr++ = i++; + *ptr++ = i++; + *ptr++ = i++; + *ptr++ = i++; + *ptr++ = i++; + *ptr++ = i++; + printf("B\n"); /* test-only */ + my_flush_dcache(addr, 32); + printf("C\n"); /* test-only */ + + /* + * Read one value back + */ + ptr = (volatile unsigned long *)addr; + val = *ptr; + printf("D\n"); /* test-only */ + + /* + * One pci config write + */ +/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */ +/* ibmPciConfigWrite(0x44, 1, 0x00); */ + ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */ + printf("E\n"); /* test-only */ + + if (loopcount++ > countmax) { + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + putc('.'); + + loopcount = 0; + } + } + + return 0; +} +U_BOOT_CMD( + writepci_cache, 4, 1, do_writepci_cache, + "writepci_cache - Write some data to pcibus\n", + " \n" + " - Write some data to pcibus.\n" +); + +int do_savepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int *ptr; + int i; + + /* + * Save own pci configuration in PRAM + */ + memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN); + ptr = (unsigned int *)PCI_REGS_ADDR + 1; + for (i=0; i<0x40; i+=4) { + pci_read_config_dword(PCIDEVID_405GP, i, ptr++); + } + ptr = (unsigned int *)PCI_REGS_ADDR; + *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4); + + printf("\nStoring PCI Configuration Regs...\n"); + + return 0; +} +U_BOOT_CMD( + savepci, 4, 1, do_savepci, + "savepci - Save all pci regs\n", + " \n" + " - Write some data to pcibus.\n" +); + +int do_restorepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int *ptr; + int i; + + /* + * Rewrite pci config regs (only after soft-reset with magic set) + */ + ptr = (unsigned int *)PCI_REGS_ADDR; + if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { + puts("Restoring PCI Configurations Regs!\n"); + ptr = (unsigned int *)PCI_REGS_ADDR + 1; + for (i=0; i<0x40; i+=4) { + pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); + } + } + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} +U_BOOT_CMD( + restorepci, 4, 1, do_restorepci, + "restorepci - Restore all pci regs\n", + " \n" + " - Write some data to pcibus.\n" +); + + +extern void write_without_sync(void); +extern void write_with_sync(void); +extern void write_with_less_sync(void); +extern void write_with_more_sync(void); + +/* + * code from IBM-PPCSUPP + */ +int do_writeibm1(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ + + write_without_sync(); + + return 0; +} +U_BOOT_CMD( + writeibm1, 4, 1, do_writeibm1, + "writeibm1- Write some data to pcibus (without sync)\n", + " \n" + " - Write some data to pcibus.\n" +); + +int do_writeibm2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ + + write_with_sync(); + + return 0; +} +U_BOOT_CMD( + writeibm2, 4, 1, do_writeibm2, + "writeibm2- Write some data to pcibus (with sync)\n", + " \n" + " - Write some data to pcibus.\n" +); + +int do_writeibm22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ + + write_with_less_sync(); + + return 0; +} +U_BOOT_CMD( + writeibm22, 4, 1, do_writeibm22, + "writeibm22- Write some data to pcibus (with less sync)\n", + " \n" + " - Write some data to pcibus.\n" +); + +int do_writeibm3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ + + write_with_more_sync(); + + return 0; +} +U_BOOT_CMD( + writeibm3, 4, 1, do_writeibm3, + "writeibm3- Write some data to pcibus (with more sync)\n", + " \n" + " - Write some data to pcibus.\n" +); +#endif diff --git a/board/esd/pci405/config.mk b/board/esd/pci405/config.mk new file mode 100644 index 0000000..83f07fe --- /dev/null +++ b/board/esd/pci405/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFFD0000 diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c new file mode 100644 index 0000000..3b21781 --- /dev/null +++ b/board/esd/pci405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i +#include +#include +#include +#include +#include <405gp_pci.h> + +#include "pci405.h" + + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/ +unsigned long fpga_done_state(void); +unsigned long fpga_init_state(void); + +#if 0 +#define FPGA_DEBUG +#endif + +/* predefine these here */ +#define FPGA_DONE_STATE (fpga_done_state()) +#define FPGA_INIT_STATE (fpga_init_state()) + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + +#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE) +#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12) + +#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT) +#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12) + + +int board_revision(void) +{ + unsigned long cntrl0Reg; + unsigned long value; + + /* + * Get version of PCI405 board from GPIO's + */ + + /* + * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x03000000); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200); + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x00100200; /* get config bits */ + + /* + * Restore GPIO settings + */ + mtdcr(cntrl0, cntrl0Reg); + + switch (value) { + case 0x00100200: + /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */ + return 1; + case 0x00000200: + /* CS2==0 && IRQ5==1 -> version 1.2 */ + return 2; + case 0x00000000: + /* CS2==0 && IRQ5==0 -> version 1.3 */ + return 3; +#if 0 /* not yet manufactured ! */ + case 0x00100000: + /* CS2==1 && IRQ5==0 -> version 1.4 */ + return 4; +#endif + default: + /* should not be reached! */ + return 0; + } +} + + +unsigned long fpga_done_state(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->board_type < 2) { + return FPGA_DONE_STATE_V11; + } else { + return FPGA_DONE_STATE_V12; + } +} + + +unsigned long fpga_init_state(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->board_type < 2) { + return FPGA_INIT_STATE_V11; + } else { + return FPGA_INIT_STATE_V12; + } +} + + +int board_early_init_f (void) +{ + unsigned long cntrl0Reg; + + /* + * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) + */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ + out32(GPIO0_OR, 0); /* pull prg low */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive + * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive + * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive + * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive + * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * Setup GPIO pins (IRQ4/GPIO21 as GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00008000); + + /* + * Setup GPIO pins (CS6+CS7 as GPIO) + */ + mtdcr(cntrl0, cntrl0Reg | 0x00300000); + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + unsigned int *ptr; + unsigned int *magic; + + /* + * On PCI-405 the environment is saved in eeprom! + * FPGA can be gzip compressed (malloc) and booted this late. + */ + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + /* + * Reset FPGA via FPGA_DATA pin + */ + SET_FPGA(FPGA_PRG | FPGA_CLK); + udelay(1000); /* wait 1ms */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); + udelay(1000); /* wait 1ms */ + + /* + * Check if magic for pci reconfig is written + */ + magic = (unsigned int *)0x00000004; + if (*magic == PCI_RECONFIG_MAGIC) { + /* + * Rewrite pci config regs (only after soft-reset with magic set) + */ + ptr = (unsigned int *)PCI_REGS_ADDR; + if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { + puts("Restoring PCI Configurations Regs!\n"); + ptr = (unsigned int *)PCI_REGS_ADDR + 1; + for (i=0; i<0x40; i+=4) { + pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); + } + } + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + *magic = 0; /* clear pci reconfig magic again */ + } + +#if 1 /* test-only */ + /* + * Decrease PLB latency timeout and reduce priority of the PCI bridge master + */ +#define PCI0_BRDGOPT1 0x4a + pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); +/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */ + +#define plb0_acr 0x87 + /* + * Enable fairness and high bus utilization + */ + mtdcr(plb0_acr, 0x98000000); + +#if 0 /* test-only */ + printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */ +/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */ + mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000); +#endif +/* printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */ +#endif + + free(dst); + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming PCI405"); + } else { + puts (str); + } + + gd->board_type = board_revision(); + printf(" (Rev 1.%ld", gd->board_type); + + if (gd->board_type >= 2) { + unsigned long cntrl0Reg; + unsigned long value; + + /* + * Setup GPIO pins (Trace/GPIO1 to GPIO) + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg & ~0x08000000); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000); + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x40000000; /* get config bits */ + if (value) { + puts(", 33 MHz PCI"); + } else { + puts(", 66 Mhz PCI"); + } + } + + puts(")\n"); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + +#if 0 /* test-only: all PCI405 version must report 16mb */ + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +#else + return (16*1024*1024); +#endif +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ +int wpeeprom(int wp) +{ + int wp_state = wp; + volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404; + + if (wp == 1) { + *uart1_mcr &= ~0x02; + } else if (wp == 0) { + *uart1_mcr |= 0x02; + } else { + if (*uart1_mcr & 0x02) { + wp_state = 0; + } else { + wp_state = 1; + } + } + return wp_state; +} + +int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int wp = -1; + if (argc >= 2) { + if (argv[1][0] == '1') { + wp = 1; + } else if (argv[1][0] == '0') { + wp = 0; + } + } + + wp = wpeeprom(wp); + printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED"); + return 0; +} + +U_BOOT_CMD( + wpeeprom, 2, 1, do_wpeeprom, + "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n", + "wpeeprom\n" + " - check I2C EEPROM write protection state\n" + "wpeeprom 1\n" + " - enable I2C EEPROM write protection\n" + "wpeeprom 0\n" + " - disable I2C EEPROM write protection\n" + ); diff --git a/board/esd/pci405/pci405.h b/board/esd/pci405/pci405.h new file mode 100644 index 0000000..c11a20f --- /dev/null +++ b/board/esd/pci405/pci405.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PCI405_H_ +#define _PCI405_H_ + +#define PCI_REGS_LEN 0x100 +#define PCI_REGS_ADDR ((unsigned long)0x01000000 - PCI_REGS_LEN) + +#define PCI_RECONFIG_MAGIC 0x07081967 + +#endif /* _PCI405_H_ */ diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds new file mode 100644 index 0000000..f7a20d1 --- /dev/null +++ b/board/esd/pci405/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S new file mode 100644 index 0000000..9f5c35b --- /dev/null +++ b/board/esd/pci405/writeibm.S @@ -0,0 +1,223 @@ +/*------------------------------------------------------------------------------+ */ +/* */ +/* This source code has been made available to you by IBM on an AS-IS */ +/* basis. Anyone receiving this source is licensed under IBM */ +/* copyrights to use it in any way he or she deems fit, including */ +/* copying it, modifying it, compiling it, and redistributing it either */ +/* with or without modifications. No license under IBM patents or */ +/* patent applications is to be implied by the copyright license. */ +/* */ +/* Any user of this software should understand that IBM cannot provide */ +/* technical support for this software and will not be responsible for */ +/* any consequences resulting from the use of this software. */ +/* */ +/* Any person who transfers this source code or any derivative work */ +/* must include the IBM copyright notice, this paragraph, and the */ +/* preceding two paragraphs in the transferred software. */ +/* */ +/* COPYRIGHT I B M CORPORATION 1995 */ +/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ +/*------------------------------------------------------------------------------- */ + +/*----------------------------------------------------------------------------- */ +/* Function: ext_bus_cntlr_init */ +/* Description: Initializes the External Bus Controller for the external */ +/* peripherals. IMPORTANT: For pass1 this code must run from */ +/* cache since you can not reliably change a peripheral banks */ +/* timing register (pbxap) while running code from that bank. */ +/* For ex., since we are running from ROM on bank 0, we can NOT */ +/* execute the code that modifies bank 0 timings from ROM, so */ +/* we run it from cache. */ +/* Bank 0 - Flash and SRAM */ +/* Bank 1 - NVRAM/RTC */ +/* Bank 2 - Keyboard/Mouse controller */ +/* Bank 3 - IR controller */ +/* Bank 4 - not used */ +/* Bank 5 - not used */ +/* Bank 6 - not used */ +/* Bank 7 - FPGA registers */ +/*----------------------------------------------------------------------------- */ +#include + +#include +#include + +#include +#include + + + .globl write_without_sync +write_without_sync: + /* + * Write one values to host via pci busmastering + * ptr = 0xc0000000 -> 0x01000000 (PCI) + * *ptr = 0x01234567; + */ + addi r31,0,0 + lis r31,0xc000 + +start1: + lis r0,0x0123 + ori r0,r0,0x4567 + stw r0,0(r31) + + /* + * Read one value back + * ptr = (volatile unsigned long *)addr; + * val = *ptr; + */ + + lwz r0,0(r31) + + /* + * One pci config write + * ibmPciConfigWrite(0x2e, 2, 0x1234); + */ + /* subsystem id */ + + li r4,0x002C + oris r4,r4,0x8000 + lis r3,0xEEC0 + stwbrx r4,0,r3 + + li r5,0x1234 + ori r3,r3,0x4 + stwbrx r5,0,r3 + + b start1 + + blr /* never reached !!!! */ + + .globl write_with_sync +write_with_sync: + /* + * Write one values to host via pci busmastering + * ptr = 0xc0000000 -> 0x01000000 (PCI) + * *ptr = 0x01234567; + */ + addi r31,0,0 + lis r31,0xc000 + +start2: + lis r0,0x0123 + ori r0,r0,0x4567 + stw r0,0(r31) + + /* + * Read one value back + * ptr = (volatile unsigned long *)addr; + * val = *ptr; + */ + + lwz r0,0(r31) + + /* + * One pci config write + * ibmPciConfigWrite(0x2e, 2, 0x1234); + */ + /* subsystem id */ + + li r4,0x002C + oris r4,r4,0x8000 + lis r3,0xEEC0 + stwbrx r4,0,r3 + sync + + li r5,0x1234 + ori r3,r3,0x4 + stwbrx r5,0,r3 + sync + + b start2 + + blr /* never reached !!!! */ + + .globl write_with_less_sync +write_with_less_sync: + /* + * Write one values to host via pci busmastering + * ptr = 0xc0000000 -> 0x01000000 (PCI) + * *ptr = 0x01234567; + */ + addi r31,0,0 + lis r31,0xc000 + +start2b: + lis r0,0x0123 + ori r0,r0,0x4567 + stw r0,0(r31) + + /* + * Read one value back + * ptr = (volatile unsigned long *)addr; + * val = *ptr; + */ + + lwz r0,0(r31) + + /* + * One pci config write + * ibmPciConfigWrite(0x2e, 2, 0x1234); + */ + /* subsystem id */ + + li r4,0x002C + oris r4,r4,0x8000 + lis r3,0xEEC0 + stwbrx r4,0,r3 + sync + + li r5,0x1234 + ori r3,r3,0x4 + stwbrx r5,0,r3 +/* sync */ + + b start2b + + blr /* never reached !!!! */ + + .globl write_with_more_sync +write_with_more_sync: + /* + * Write one values to host via pci busmastering + * ptr = 0xc0000000 -> 0x01000000 (PCI) + * *ptr = 0x01234567; + */ + addi r31,0,0 + lis r31,0xc000 + +start3: + lis r0,0x0123 + ori r0,r0,0x4567 + stw r0,0(r31) + sync + + /* + * Read one value back + * ptr = (volatile unsigned long *)addr; + * val = *ptr; + */ + + lwz r0,0(r31) + sync + + /* + * One pci config write + * ibmPciConfigWrite(0x2e, 2, 0x1234); + */ + /* subsystem id (PCIC0_SBSYSVID)*/ + + li r4,0x002C + oris r4,r4,0x8000 + lis r3,0xEEC0 + stwbrx r4,0,r3 + sync + + li r5,0x1234 + ori r3,r3,0x4 + stwbrx r5,0,r3 + sync + + b start3 + + blr /* never reached !!!! */ diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile new file mode 100644 index 0000000..603bbe2 --- /dev/null +++ b/board/esd/pf5200/Makefile @@ -0,0 +1,53 @@ + +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +# Objects for Xilinx JTAG programming (CPLD) +# CPLD = ../common/xilinx_jtag/lenval.o \ +# ../common/xilinx_jtag/micro.o \ +# ../common/xilinx_jtag/ports.o + +# OBJS = $(BOARD).o flash.o $(CPLD) +OBJS = $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/esd/pf5200/config.mk b/board/esd/pf5200/config.mk new file mode 100644 index 0000000..07b5de1 --- /dev/null +++ b/board/esd/pf5200/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# IceCube board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFF000000 boot low for 16 MiB boards +# 0xFF800000 boot low for 8 MiB boards +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c new file mode 100644 index 0000000..53afbc0 --- /dev/null +++ b/board/esd/pf5200/flash.c @@ -0,0 +1,461 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define FLASH_ID_MASK 0x00FF + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x0aaa +#define FLASH_ID1 0x00 +#define FLASH_ID2 0x01 +#define FLASH_ID3 0x0E +#define FLASH_ID4 0x0F + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV * addr, flash_info_t * info); +static void flash_reset(flash_info_t * info); +static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init(void) +{ + unsigned long size = 0; + int i = 0; + extern void flash_preinit(void); + extern void flash_afterinit(uint, ulong, ulong); + + ulong flashbase = CFG_FLASH_BASE; + + flash_preinit(); + + /* There is only ONE FLASH device */ + memset(&flash_info[i], 0, sizeof(flash_info_t)); + flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]); + size += flash_info[i].size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + flash_afterinit(i, flash_info[i].start[0], flash_info[i].size); + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t * info) { + FPWV *base = (FPWV *) (info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ + } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { + *base = (FPW) 0x00F000F0; /* AMD Read Mode */ + } +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) { + int i; + flash_info_t *info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + info = &flash_info[i]; + if ((info->size) && (info->start[0] <= base) + && (base <= info->start[0] + info->size - 1)) { + break; + } + } + return (i == CFG_MAX_FLASH_BANKS ? 0 : info); +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info(flash_info_t * info) { + int i; + char *fmt; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMLV256U: + fmt = "29LV256M (256 Mbit)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf(fmt); + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, + info->sector_count); + printf(" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; ++i) { + ulong size; + int erased; + ulong *flash = (unsigned long *)info->start[i]; + + if ((i % 5) == 0) { + printf("\n "); + } + + /* + * Check if whole sector is erased + */ + size = + (i != + (info->sector_count - 1)) ? (info->start[i + 1] - + info->start[i]) >> 2 : (info-> + start + [0] + + info-> + size - + info-> + start + [i]) + >> 2; + + for (flash = (unsigned long *)info->start[i], erased = 1; + (flash != (unsigned long *)info->start[i] + size) + && erased; flash++) { + erased = *flash == ~0x0UL; + } + printf(" %08lX %s %s", info->start[i], erased ? "E" : " ", + info->protect[i] ? "(RO)" : " "); + } + + printf("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info) { + int i; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. */ + /* This works for any bus width and any FLASH device width. */ + udelay(100); + switch (addr[FLASH_ID1] & 0x00ff) { + case (uchar) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) { + switch ((FPW) addr[FLASH_ID2]) { + case (FPW) AMD_ID_MIRROR: + /* MIRROR BIT FLASH, read more ID bytes */ + if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2 + && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) { + /* attention: only the first 16 MB will be used in u-boot */ + info->flash_id += FLASH_AMLV256U; + info->sector_count = 512; + info->size = 0x02000000; + for (i = 0; i < info->sector_count; i++) { + info->start[i] = + (ulong) addr + 0x10000 * i; + } + break; + } + /* fall thru to here ! */ + default: + printf("unknown AMD device=%x %x %x", + (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3], + (FPW) addr[FLASH_ID4]); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0x800000; + break; + } + + /* Put FLASH back in read mode */ + flash_reset(info); + } + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t * info, int s_first, int s_last) { + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMLV256U: + break; + case FLASH_UNKNOWN: + default: + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && rcode == 0; sect++) { + if (info->protect[sect] != 0) { /* protected, skip it */ + continue; + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *) (info->start[sect]); + if (intel) { + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + } else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *) (info->start[0]); + base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ + *addr = (FPW) 0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + start = get_timer(0); + + /* wait at least 50us for AMD, 80us for Intel. */ + /* Let's wait 1 ms. */ + udelay(1000); + + while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + if (intel) { + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + } + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { + /* every second */ + putc('.'); + last = get_timer(0); + } + } + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { + /* every second */ + putc('.'); + last = get_timer(0); + } + flash_reset(info); /* reset to read mode */ + } + printf(" done\n"); + return (rcode); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left) + data += *((uchar *) addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *) addr, data); + break; + default: + /* unknown flash type, error! */ + printf("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) { + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + base = (FPWV *) (info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + start = get_timer(0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW) 0x00F000F0; /* reset bank */ + res = 1; + } + } + return (res); +} diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h new file mode 100644 index 0000000..22d0a55 --- /dev/null +++ b/board/esd/pf5200/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x705f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c new file mode 100644 index 0000000..2b47012 --- /dev/null +++ b/board/esd/pf5200/pf5200.c @@ -0,0 +1,370 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * pf5200.c - main board support/init for the esd pf5200. + */ + +#include +#include +#include +#include + +#include "mt46v16m16-75.h" + +void init_power_switch(void); + +static void sdram_start(int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = + SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = + SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register: extended mode */ + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = + SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = + SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram(int board_type) +{ + ulong dramsize = 0; + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + + /* set tap delay */ + *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = + 0x13 + __builtin_ffs(dramsize >> 20) - 1; + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ + } else { +#if 0 + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ +#else + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = + 0x13 + __builtin_ffs(0x08000000 >> 20) - 1; + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */ +#endif + } + +#if 0 + /* find RAM size using SDRAM CS1 only */ + sdram_start(0); + get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + sdram_start(1); + get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + sdram_start(0); +#endif + /* set SDRAM CS1 size according to the amount of RAM found */ + + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + + init_power_switch(); + return (dramsize); +} + +int checkboard(void) +{ + puts("Board: esd ParaFinder (pf5200)\n"); + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + +void flash_afterinit(ulong size) +{ + if (size == 0x02000000) { + /* adjust mapping */ + *(vu_long *) MPC5XXX_BOOTCS_START = + *(vu_long *) MPC5XXX_CS0_START = + START_REG(CFG_BOOTCS_START | size); + *(vu_long *) MPC5XXX_BOOTCS_STOP = + *(vu_long *) MPC5XXX_CS0_STOP = + STOP_REG(CFG_BOOTCS_START | size, size); + } +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void + ) { + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL + +void init_ide_reset(void) +{ + debug("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; +} + +void ide_set_reset(int idereset) +{ + debug("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + } +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) +#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) +#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010) +#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014) + +#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020) +#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028) +#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C) +#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C) + +#define GPIO_WU6 0x40000000UL +#define GPIO_USB0 0x00010000UL +#define GPIO_USB9 0x08000000UL +#define GPIO_USB9S 0x00080000UL + +void init_power_switch(void) +{ + debug("init_power_switch\n"); + + /* Configure GPIO_WU6 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; + __asm__ volatile ("sync"); + + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0; + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0; + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0; + __asm__ volatile ("sync"); + + *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; + *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9; + __asm__ volatile ("sync"); + + if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; + __asm__ volatile ("sync"); + } + *(vu_char *) CFG_CS1_START = 0x02; /* Red Power LED on */ + __asm__ volatile ("sync"); + + *(vu_char *) (CFG_CS1_START + 1) = 0x02; /* Disable driver for KB11 */ + __asm__ volatile ("sync"); +} + +void power_set_reset(int power) +{ + debug("ide_set_reset(%d)\n", power); + + if (power) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_WU6; + *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; + if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == + 0) { + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= + GPIO_USB0; + } + + } +} + +int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + power_set_reset(1); + return (0); +} + +U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "poweroff- Switch off power\n", NULL); + +int phypower(int flag) +{ + u32 addr; + vu_long *reg; + int status; + pci_dev_t dev; + + dev = PCI_BDF(0, 0x18, 0); + status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr); + if (status == 0) { + reg = (vu_long *) (addr + 0x00000040); + *reg |= 0x40000000; + __asm__ volatile ("sync"); + + reg = (vu_long *) (addr + 0x001000c); + *reg |= 0x20000000; + __asm__ volatile ("sync"); + + reg = (vu_long *) (addr + 0x0010004); + if (flag != 0) { + *reg &= ~0x20000000; + } else { + *reg |= 0x20000000; + } + __asm__ volatile ("sync"); + } + return (status); +} + +int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int status; + + if (argv[1][0] == '0') { + status = phypower(0); + } else { + status = phypower(1); + } + return (0); +} + +U_BOOT_CMD(phypower, 2, 2, do_phypower, + "phypower- Switch power of ethernet phy\n", NULL); + +int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int addr; + unsigned int size; + int i; + volatile unsigned long *ptr; + + addr = simple_strtol(argv[1], NULL, 16); + size = simple_strtol(argv[2], NULL, 16); + + printf("\nWriting at addr %08x, size %08x.\n", addr, size); + + while (1) { + ptr = (volatile unsigned long *)addr; + for (i = 0; i < (size >> 2); i++) { + *ptr++ = i; + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + putc('.'); + } + return 0; +} + +U_BOOT_CMD(writepci, 3, 1, do_writepci, + "writepci- Write some data to pcibus\n", + " \n" " - Write some data to pcibus.\n"); diff --git a/board/esd/pf5200/u-boot.lds b/board/esd/pf5200/u-boot.lds new file mode 100644 index 0000000..f23432e --- /dev/null +++ b/board/esd/pf5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile new file mode 100644 index 0000000..9340a32 --- /dev/null +++ b/board/esd/plu405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk new file mode 100644 index 0000000..25b2105 --- /dev/null +++ b/board/esd/plu405/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd PLU405 boards +# + +TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0x00FC0000 diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/plu405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i +#include +#include +#include + + +#if 0 +#define FPGA_DEBUG +#endif + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); + +/* fpga configuration data - gzip compressed and generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +/* + * include common auto-update code (for esd boards) + */ +#include "../common/auto_update.h" + +au_image_t au_image[] = { + {"plu405/preinst.img", 0, -1, AU_SCRIPT}, + {"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, + {"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND}, + {"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND}, + {"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND}, + {"plu405/postinst.img", 0, 0, AU_SCRIPT}, +}; + +int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); + + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + return 0; +} + + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); + + /* + * Reset FPGA via FPGA_DATA pin + */ + SET_FPGA(FPGA_PRG | FPGA_CLK); + udelay(1000); /* wait 1ms */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); + udelay(1000); /* wait 1ms */ + + /* + * Reset external DUARTs + */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + udelay(10); /* wait 10us */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + udelay(1000); /* wait 1ms */ + + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + + /* + * Enable interrupts in exar duart mcr[3] + */ + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; + + return (0); +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming PLU405"); + } else { + puts(str); + } + + putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + + +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) +{ + volatile unsigned short *fpga_mode = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { /* assert RESET */ + *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + } else { /* release RESET */ + *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + } +} +#endif /* CONFIG_IDE_RESET */ + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif + + +#ifdef CONFIG_AUTO_UPDATE_SHOW +void board_auto_update_show(int au_active) +{ + if (au_active) { + printf("\n Dies ist die board-funktion: Updating!!!\n"); + } else { + printf("\n Dies ist die board-funktion: Updating done!!!\n"); + } +} +#endif diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds new file mode 100644 index 0000000..43f7765 --- /dev/null +++ b/board/esd/plu405/u-boot.lds @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile new file mode 100644 index 0000000..1281be7 --- /dev/null +++ b/board/esd/pmc405/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +# Objects for Xilinx JTAG programming (CPLD) +CPLD = ../common/xilinx_jtag/lenval.o \ + ../common/xilinx_jtag/micro.o \ + ../common/xilinx_jtag/ports.o + +OBJS = $(BOARD).o ../common/misc.o $(CPLD) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/pmc405/config.mk b/board/esd/pmc405/config.mk new file mode 100644 index 0000000..fc2794d --- /dev/null +++ b/board/esd/pmc405/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd PMC405 boards +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/pmc405/fpgadata.c b/board/esd/pmc405/fpgadata.c new file mode 100644 index 0000000..ebdf71d --- /dev/null +++ b/board/esd/pmc405/fpgadata.c @@ -0,0 +1,2472 @@ + 0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08, + 0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00, + 0xf9,0x60,0x20,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00, + 0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08, + 0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01, + 0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02, + 0x08,0xea,0x08,0x00,0x00,0x00,0x22,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x00,0x04,0x38,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x00,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x24,0x38,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x00,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x2c,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x30,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44, + 0x14,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00, + 0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x03,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,0x80,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09, + 0x00,0x00,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x00,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x8c,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x90,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x00,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa4, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00, + 0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc0,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x00,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xcc,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x00,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03, + 0x09,0x00,0x01,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00, + 0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x04,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x08,0x01,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x01,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01, + 0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x20,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x01,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x01,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x2c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x01,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x44,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x01,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x50,0x00,0x03,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x01,0x80,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x01, + 0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x01,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x8c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x01,0xa0,0x10,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xa4,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x01,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xb0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xc0,0x00,0x21,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x01,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xc8, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xcc,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01, + 0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00, + 0x02,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04, + 0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x02,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x10,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x20,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x02,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x28, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x2c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x02,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02, + 0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x44,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x02,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x02,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x02,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x84,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x88, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x8c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x02,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02, + 0xa0,0x00,0x81,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xa4,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x02,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x02,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xb0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x02,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xc8,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0xd0,0x00, + 0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x03,0x00, + 0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, + 0x00,0x00,0x09,0x00,0x03,0x04,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x03,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x03,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0x10,0x01,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x03,0x20,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x03,0x24,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0x28,0x01,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x03,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0x40,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0x44,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x03,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0x4c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x03,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x03,0x09,0x00,0x03,0x80,0x01,0x41,0x00,0x00,0x00,0x00,0x01,0x01,0x00, + 0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x03,0x84,0x02,0x01,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x03,0x88,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0x8c,0x03,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x03,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0xa0,0x03, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0xa4,0x01,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x03,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0xac, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0xb0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x03,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03, + 0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x03,0xc8,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x03,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00, + 0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x03,0xd0,0x00,0x03,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x04,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00, + 0x09,0x00,0x04,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x04,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0x0c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0x10,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x04,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04, + 0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0x28,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x04,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x04,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0x40,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x04,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x04,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0x4c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x04,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x03,0x09,0x00,0x04,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00, + 0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x04,0x84,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x04,0x88,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x04,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x04,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0xa0,0x00,0x41,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x04,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x04,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0xac,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x04,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0xc4,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0xc8,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x04,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e, + 0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x04,0xd0,0x00,0x03,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x05,0x00,0xc0,0x11,0x00,0x00, + 0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00, + 0x05,0x04,0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x05,0x08,0x40,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x0c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x10,0x80,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x05,0x20,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x24,0x00, + 0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x28,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x05,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x30, + 0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x40,0x20,0x19,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x05,0x44,0x20,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05, + 0x48,0x48,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x4c,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x05,0x50,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09, + 0x00,0x05,0x80,0x00,0x21,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00, + 0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x84,0x00,0x11,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x88,0x80,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x05,0x8c,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x90, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xa0,0x04,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x05,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05, + 0xa8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x11,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x05,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x05,0xc0,0xc8,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc4,0x08,0x09,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x05,0xcc,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,0x03,0x02,0x01,0x00,0x00,0x00,0x00, + 0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x07, + 0x42,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06, + 0x0b,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x0f,0x02,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x06,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x06,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x27,0x03,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x2b,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x06,0x2f,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x30,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x06,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x48,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x4c,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x50, + 0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06, + 0x80,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00, + 0x00,0x00,0x00,0x09,0x00,0x06,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x06,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x90,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x06,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xa8,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xac,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x06,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xc0, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xc4,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x06,0xc8,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06, + 0xcc,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x06,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x03,0x09,0x00,0x07,0x02,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01, + 0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x07,0x07,0x02,0x01, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x07,0x0b,0x02, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x0f,0x02,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x07,0x11,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x23, + 0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x27,0x03,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x07,0x2b,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07, + 0x2f,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x30,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x07,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x07,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x48,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04, + 0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x07,0x50,0x00,0x03, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x07,0x82,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00, + 0x00,0x09,0x00,0x07,0x86,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x07,0x89,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07, + 0x8d,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x91,0x02,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x07,0xa0,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x07,0xa5,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0xab,0x02,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x07,0xad,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x07,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0xc0,0x04,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x07,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0xcc,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x07,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x03,0x09,0x00,0x08,0x00,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00, + 0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x08,0x04,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x08,0x08,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x0e,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x08,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x23,0x01,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x26,0x01,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x08,0x28,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x2e,0x01, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x30,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x08,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x44, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x48,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x08,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00, + 0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x08,0x50,0x00,0x03,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x08,0x80,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09, + 0x00,0x08,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x08,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x8c,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x90,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x08,0xa0,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0xa4, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0xa8,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x08,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08, + 0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0xc0,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x08,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x08,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0xcc,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x08,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03, + 0x09,0x00,0x09,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00, + 0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x09,0x04,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x09,0x08,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x09,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09, + 0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0x20,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x09,0x26,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x09,0x28,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0x2e,0x01,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x09,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x09,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0x44,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x09,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x09,0x50,0x00,0x03,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x09,0x80,0x10,0x01,0x00,0x00,0x00, + 0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x09, + 0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x09,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0x8c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x09,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x09,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0xa4,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x09,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0xb0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0xc0,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x09,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0xc8, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x09,0xcc,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x09, + 0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00, + 0x0a,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04, + 0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x0a,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x10,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x20,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x0a,0x26,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x28, + 0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x2c,0x01,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x0a,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a, + 0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x44,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x0a,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x0a,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0a,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0x84,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0x88, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x8c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x0a,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a, + 0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0xa4,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x0a,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x0a,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0xb0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0xc0,0x00,0x41,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x0a,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0xc8,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0xd0,0x00, + 0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0b,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, + 0x00,0x00,0x09,0x00,0x0b,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x0b,0x0a,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x0b,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x10,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x22,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x0b,0x26,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x28,0x01,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x2e,0x01,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x0b,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x40,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x44,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x0b,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x4c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x0b,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x03,0x09,0x00,0x0b,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00, + 0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0b,0x84,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0b,0x88,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x0b,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0xa0,0x20, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0xa4,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x0b,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0xac, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0xb0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x0b,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b, + 0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0xc8,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x0b,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00, + 0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0b,0xd0,0x00,0x03,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0c,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00, + 0x09,0x00,0x0c,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x0c,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0x0c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0x10,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x0c,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c, + 0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0x28,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x0c,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x0c,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0x40,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x0c,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0x4c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x0c,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x03,0x09,0x00,0x0c,0x80,0x00,0x81,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00, + 0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0c,0x84,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0c,0x88,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x0c,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x0c,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0xa0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x0c,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0xac,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x0c,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0xc4,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0xc8,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x0c,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e, + 0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0c,0xd0,0x00,0x03,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0d,0x03,0x02,0x01,0x00,0x00, + 0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00, + 0x0d,0x07,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x0d,0x0b,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x0f,0x02,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x0d,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x27,0x07, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x2b,0x03,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x0d,0x2f,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x30, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x40,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x0d,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d, + 0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x4c,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x0d,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09, + 0x00,0x0d,0x80,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00, + 0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0x88,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x0d,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x90, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0xa0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x0d,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d, + 0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0xac,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x0d,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x0d,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0xc4,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x0d,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0e,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x04, + 0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0e, + 0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x0c,0x80,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x0e,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x0e,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x24,0x00,0x11,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x0e,0x2c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x30,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x40,0x60,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x0e,0x44,0x48,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x48,0xc0, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x4c,0x80,0x11,0x00,0x00,0x00,0x00, + 0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x50, + 0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0e, + 0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00, + 0x00,0x00,0x00,0x09,0x00,0x0e,0x84,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x88,0x40,0x11,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x0e,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x90,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x0e,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa8,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xac,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x0e,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xc0, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xc4,0xa0,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x0e,0xc8,0x08,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e, + 0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x0e,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x03,0x09,0x00,0x0f,0x00,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01, + 0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0f,0x04,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0f,0x0a,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0x0c,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x0f,0x12,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0x20, + 0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0x26,0x01,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x0f,0x28,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f, + 0x2c,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0x30,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x0f,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x0f,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0x48,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04, + 0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0f,0x50,0x00,0x03, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0f,0x80,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00, + 0x00,0x09,0x00,0x0f,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x0f,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f, + 0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0x90,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x0f,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x0f,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0xa8,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x0f,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0xc0,0x10,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x0f,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0f,0xcc,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x0f,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x03,0x09,0x00,0x10,0x01,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00, + 0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x05,0x82,0x01,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x0a,0x82,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x0c,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x10,0x12,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x20,0x03,0x11, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x26,0x03,0x11,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x10,0x2a,0x03,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x2c,0x01, + 0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x30,0x00,0x11,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x10,0x40,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x44, + 0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x48,0x00,0x11,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x10,0x4c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00, + 0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x50,0x00,0x13,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x10,0x80,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09, + 0x00,0x10,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x10,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x8c,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x90,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x10,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0xa4, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0xa8,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x10,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10, + 0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0xc0,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x10,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x10,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0xcc,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x10,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03, + 0x09,0x00,0x11,0x00,0xc0,0x11,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00, + 0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x04,0x00,0x11,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x08,0x80,0x21,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x11,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11, + 0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x20,0x00,0x11,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x11,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x11,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x2c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x11,0x40,0x08,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x44,0x20,0x09, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x48,0xc0,0x11,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x11,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x50,0x00,0x03,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x11,0x80,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x11, + 0x84,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x11,0x88,0x40,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x8c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x90,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x11,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xa4,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x11,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xb0,0x00, + 0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xc0,0x20,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x11,0xc4,0xc0,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xc8, + 0x08,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0xcc,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11, + 0xd0,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00, + 0x12,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04, + 0x00,0x00,0x00,0x00,0x09,0x00,0x12,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x12,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x12,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0x10,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0x20,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x12,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0x28, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0x2c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x12,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12, + 0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0x44,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x12,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x12,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x12,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x12,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x12,0x84,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x12,0x88, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0x8c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x12,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12, + 0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0xa4,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x12,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x12,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0xb0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x12,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x12,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0xc8,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x12,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x12,0xd0,0x00, + 0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x13,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, + 0x00,0x00,0x09,0x00,0x13,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x13,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x13,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0x10,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x13,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x13,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0x28,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x13,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0x40,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0x44,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x13,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0x4c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x13,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x03,0x09,0x00,0x13,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00, + 0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x13,0x84,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x13,0x88,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x13,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xa2,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xa4,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x13,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xac, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xb0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x13,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13, + 0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x13,0xc8,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x13,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00, + 0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x13,0xd0,0x00,0x03,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x14,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00, + 0x09,0x00,0x14,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x14,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x0e, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x10,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x14,0x23,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14, + 0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x28,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x14,0x2e,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x14,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x40,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x14,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0x4c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x14,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x03,0x09,0x00,0x14,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00, + 0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x14,0x84,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x14,0x88,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x14,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x14,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0xa0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x14,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x14,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0xac,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x14,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0xc4,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x14,0xc8,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x14,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e, + 0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x14,0xd0,0x00,0x03,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x15,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00, + 0x15,0x04,0x00,0x11,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x15,0x08,0xc0,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x0c,0x80,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x10,0x80,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x15,0x20,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x24,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x28,0x00,0x11,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x15,0x2c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x30, + 0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x40,0x28,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x15,0x44,0x28,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15, + 0x48,0x48,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x4c,0x00,0x11,0x00,0x00, + 0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x15,0x50,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09, + 0x00,0x15,0x80,0xc0,0x31,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00, + 0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x15,0x84,0xc0,0x21,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x15,0x88,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x15,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0x90, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xa0,0x00,0x11,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x15,0xa4,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15, + 0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xac,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x15,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x15,0xc0,0xc0,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xc4,0x40,0x11,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x15,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x15,0xcc,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x15,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x16,0x02,0x02,0x01,0x00,0x00,0x00,0x00, + 0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x16,0x06, + 0x3a,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x16, + 0x0b,0x42,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x0d,0x02,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x16,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x16,0x20,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x27,0x3b,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x2b,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x16,0x2d,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x30,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x40,0x00,0x09,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x16,0x44,0x14,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x48,0x00, + 0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x4c,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x16,0x50, + 0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x16, + 0x83,0x02,0x11,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00, + 0x00,0x00,0x00,0x09,0x00,0x16,0x87,0x02,0x11,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x16,0x8b,0x02,0x11,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x16,0x8f,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0x93,0x02,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xa3,0x03,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x16,0xa7,0x07,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xab,0x03, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xaf,0x01,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x16,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xc0, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xc4,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x16,0xc8,0x08,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16, + 0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x16,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x03,0x09,0x00,0x17,0x02,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01, + 0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x17,0x07,0x02,0x01, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x17,0x0b,0x02, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x0f,0x02,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x17,0x11,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x23, + 0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x27,0x03,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x17,0x2b,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17, + 0x2f,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x30,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x17,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x17,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x48,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04, + 0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x17,0x50,0x00,0x03, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x17,0x80,0x0a, + 0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00, + 0x00,0x09,0x00,0x17,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x17,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17, + 0x8e,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x90,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x17,0xa3,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x17,0xa6,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xa8,0x01,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xae,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x17,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xc0,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x17,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xcc,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x17,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x03,0x09,0x00,0x18,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00, + 0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x18,0x04,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x18,0x08,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x18,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x20,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x26,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x18,0x28,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x2e,0x01, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x30,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x18,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x44, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x48,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x18,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00, + 0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x18,0x50,0x00,0x03,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x18,0x80,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09, + 0x00,0x18,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x18,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x8c,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x90,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x18,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa6, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa8,0x01,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x18,0xac,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18, + 0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xc0,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x18,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x18,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xcc,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x18,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03, + 0x09,0x00,0x19,0x01,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00, + 0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x19,0x04,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x19,0x08,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x19,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19, + 0x11,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0x20,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x19,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x19,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0x2c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x19,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x19,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0x44,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x19,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x19,0x50,0x00,0x03,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x19,0x80,0x01,0x01,0x00,0x00,0x00, + 0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x19, + 0x85,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x19,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0x8c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x19,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x19,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0xa4,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x19,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0xb0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0xc0,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x19,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0xc8, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x19,0xcc,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x19, + 0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00, + 0x1a,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04, + 0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x1a,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x10,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x20,0x00,0x11,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x1a,0x24,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x28, + 0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x2c,0x00,0x11,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x1a,0x30,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a, + 0x40,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x44,0x00,0x11,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x1a,0x48,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x1a,0x4c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x50,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x1a,0x82,0x81,0x01,0x00,0x00,0x00,0x00,0x01, + 0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x84,0x80, + 0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x88, + 0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x8c,0x80,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x1a,0x90,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a, + 0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0xa4,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x1a,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x1a,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0xb0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x1a,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0xc8,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0xd0,0x00, + 0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x1b,0x00, + 0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, + 0x00,0x00,0x09,0x00,0x1b,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x1b,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x1b,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0x10,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x1b,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0x28,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x1b,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0x40,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0x44,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x1b,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0x4c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x1b,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x03,0x09,0x00,0x1b,0x81,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00, + 0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x1b,0x84,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1b,0x88,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x1b,0x91,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0xa0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0xa4,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x1b,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0xac, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0xb0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x1b,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b, + 0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1b,0xc8,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x1b,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00, + 0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1b,0xd0,0x00,0x03,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x1c,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00, + 0x09,0x00,0x1c,0x07,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x1c,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0x0c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0x10,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x1c,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c, + 0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0x28,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x1c,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x1c,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0x40,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x1c,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0x4c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x1c,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x03,0x09,0x00,0x1c,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00, + 0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x1c,0x85,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1c,0x88,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x1c,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x1c,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0xa0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x1c,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0xac,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x1c,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0xc4,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1c,0xc8,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x1c,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e, + 0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1c,0xd0,0x00,0x03,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x1d,0x01,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00, + 0x1d,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x1d,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0x0c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x1d,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0x24,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0x28,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x1d,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0x30, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0x40,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x1d,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d, + 0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0x4c,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x1d,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09, + 0x00,0x1d,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00, + 0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x1d,0x87,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1d,0x88,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x1d,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0x90, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0xa0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x1d,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d, + 0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0xac,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x1d,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x1d,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0xc4,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x1d,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x1d,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1d,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x1e,0x00,0x01,0x01,0x00,0x00,0x00,0x00, + 0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x1e,0x04, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1e, + 0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0x0c,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x1e,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x1e,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0x24,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x1e,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0x30,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x1e,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0x48,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0x4c,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1e,0x50, + 0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x1e, + 0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00, + 0x00,0x00,0x00,0x09,0x00,0x1e,0x85,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x1e,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x1e,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0x90,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0xa0,0x08,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x1e,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0xa8,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0xac,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x1e,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0xc0, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e,0xc4,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x1e,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1e, + 0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x1e,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x03,0x09,0x00,0x1f,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01, + 0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x1f,0x04,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1f,0x08,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0x0c,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x1f,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0x20, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0x24,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x1f,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f, + 0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0x30,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x1f,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x1f,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0x48,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04, + 0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1f,0x50,0x00,0x03, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x1f,0x83,0x02, + 0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00, + 0x00,0x09,0x00,0x1f,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x1f,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f, + 0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0x90,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x1f,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x1f,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0xa8,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x1f,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0xc0,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x1f,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1f,0xcc,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x1f,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x03,0x09,0x00,0x20,0x03,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00, + 0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x20,0x04,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x20,0x08,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x20,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x20,0x13,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0x20,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x20,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0x2c,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0x30,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x20,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0x44, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0x48,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x20,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00, + 0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x20,0x50,0x00,0x03,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x20,0x80,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09, + 0x00,0x20,0x85,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x20,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0x8c,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0x90,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x20,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0xa4, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0xa8,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x20,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20, + 0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0xc0,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x20,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x20,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x20,0xcc,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x20,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03, + 0x09,0x00,0x21,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00, + 0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x21,0x04,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x21,0x08,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x21,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21, + 0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0x20,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x21,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x21,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0x2c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x21,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x21,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0x44,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x21,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x21,0x50,0x00,0x03,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x21,0x81,0x01,0x01,0x00,0x00,0x00, + 0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x21, + 0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x21,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0x8c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x21,0x91,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x21,0xa0,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0xa4,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x21,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0xb0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0xc0,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x21,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0xc8, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x21,0xcc,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x21, + 0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00, + 0x22,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04, + 0x00,0x00,0x00,0x00,0x09,0x00,0x22,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x22,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x22,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0x10,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0x20,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x22,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0x28, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0x2c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x22,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22, + 0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0x44,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x22,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x22,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x22,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x22,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x22,0x84,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x22,0x88, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0x8c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x22,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22, + 0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0xa4,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x22,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x22,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0xb0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x22,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x22,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0xc8,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x22,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x22,0xd0,0x00, + 0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x23,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, + 0x00,0x00,0x09,0x00,0x23,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x23,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x23,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0x10,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x23,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x23,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0x28,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x23,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0x40,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0x44,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x23,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0x4c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x23,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x03,0x09,0x00,0x23,0x81,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00, + 0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x23,0x84,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x23,0x88,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x23,0x91,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0xa0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0xa4,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x23,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0xac, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0xb0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x23,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23, + 0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x23,0xc8,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x23,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00, + 0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x23,0xd0,0x00,0x03,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x24,0x01,0x01,0x01, + 0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00, + 0x09,0x00,0x24,0x06,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x24,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0x0c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0x10,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x24,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24, + 0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0x28,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x24,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x24,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0x40,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x24,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x24,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0x4c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x24,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x03,0x09,0x00,0x24,0x80,0x22,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00, + 0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x24,0x85,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x24,0x88,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x24,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x24,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0xa0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x24,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x24,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0xac,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x24,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0xc4,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x24,0xc8,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x24,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e, + 0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x24,0xd0,0x00,0x03,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x25,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00, + 0x25,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x25,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0x0c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x25,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0x24,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0x28,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x25,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0x30, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0x40,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x25,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25, + 0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0x4c,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x25,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09, + 0x00,0x25,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00, + 0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x25,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x25,0x88,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x25,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0x90, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0xa0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x25,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25, + 0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0xac,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x25,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x25,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x25,0xc4,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x25,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x25,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x25,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x26,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x26,0x05, + 0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x26, + 0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0x0c,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x26,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x26,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0x24,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x26,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x26,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0x30,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x26,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0x48,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0x4c,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x26,0x50, + 0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x26, + 0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00, + 0x00,0x00,0x00,0x09,0x00,0x26,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x26,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x26,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0x90,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x26,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0xa8,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0xac,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x26,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0xc0, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26,0xc4,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x26,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x26, + 0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x26,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x03,0x09,0x00,0x27,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01, + 0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x27,0x04,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x27,0x08,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0x0c,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x27,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0x20, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0x25,0x01,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x27,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27, + 0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0x30,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x27,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x27,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0x48,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x27,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04, + 0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x27,0x50,0x00,0x03, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x27,0x80,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00, + 0x00,0x09,0x00,0x27,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x27,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27, + 0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0x90,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x27,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x27,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0xa8,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x27,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x27,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0xc0,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x27,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x27,0xcc,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x27,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x03,0x09,0x00,0x28,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00, + 0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x28,0x04,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x28,0x08,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x28,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x20,0x00,0x11, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x24,0x00,0x11,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x28,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x2c,0x00, + 0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x30,0x00,0x11,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x28,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x44, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x48,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x28,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00, + 0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x28,0x50,0x00,0x03,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x28,0x80,0x80,0x01,0x00, + 0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09, + 0x00,0x28,0x84,0x80,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x28,0x88,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x8c,0x80, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x90,0x80,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x28,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xa4, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xa8,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x28,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28, + 0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xc0,0x00,0x11,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x28,0xc4,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x28,0xc8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xcc,0x00,0x11,0x00, + 0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x28,0xd0,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03, + 0x09,0x00,0x29,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00, + 0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x04,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x08,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x29,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29, + 0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x20,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x29,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x2c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x29,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x44,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x29,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x50,0x00,0x03,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x29,0x80,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x29, + 0x84,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x29,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x8c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x29,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xa4,0x80,0xe1, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x29,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xb0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xc0,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x29,0xc4,0x00,0x61,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xc8, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xcc,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29, + 0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00, + 0x2a,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04, + 0x00,0x00,0x00,0x00,0x09,0x00,0x2a,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2a,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x2a,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0x10,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0x20,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x2a,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0x28, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0x2c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x2a,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a, + 0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0x44,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x2a,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x2a,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x2a,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x2a,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x2a,0x84,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2a,0x88, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0x8c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x2a,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a, + 0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0xa4,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x2a,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x2a,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0xb0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x2a,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0xc8,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2a,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2a,0xd0,0x00, + 0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x2b,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, + 0x00,0x00,0x09,0x00,0x2b,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x2b,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x2b,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0x10,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x2b,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0x28,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x2b,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0x40,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0x44,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x2b,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0x4c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x2b,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x03,0x09,0x00,0x2b,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00, + 0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x2b,0x84,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2b,0x88,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x2b,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0xa0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0xa4,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x2b,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0xac, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0xb0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x2b,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b, + 0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2b,0xc8,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x2b,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00, + 0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2b,0xd0,0x00,0x03,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x2c,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00, + 0x09,0x00,0x2c,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x2c,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0x0c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0x10,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x2c,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c, + 0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0x28,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x2c,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x2c,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0x40,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x2c,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0x4c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x2c,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x03,0x09,0x00,0x2c,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00, + 0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x2c,0x84,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2c,0x88,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x2c,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x2c,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0xa0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x2c,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0xac,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x2c,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0xc4,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2c,0xc8,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x2c,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e, + 0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2c,0xd0,0x00,0x03,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x2d,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00, + 0x2d,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x2d,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0x0c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x2d,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0x24,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0x28,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x2d,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0x30, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0x40,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x2d,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d, + 0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0x4c,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x2d,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09, + 0x00,0x2d,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00, + 0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x2d,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2d,0x88,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x2d,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0x90, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0xa0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x2d,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d, + 0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0xac,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x2d,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x2d,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0xc4,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x2d,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x2d,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2d,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x2e,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x2e,0x04, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2e, + 0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0x0c,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x2e,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x2e,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0x24,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x2e,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0x30,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x2e,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0x48,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0x4c,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2e,0x50, + 0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x2e, + 0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00, + 0x00,0x00,0x00,0x09,0x00,0x2e,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x2e,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x2e,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0x90,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x2e,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0xa8,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0xac,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x2e,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0xc0, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e,0xc4,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x2e,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2e, + 0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x2e,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00, + 0x00,0x00,0x00,0x03,0x09,0x00,0x2f,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01, + 0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x2f,0x04,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2f,0x08,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0x0c,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x2f,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0x20, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0x24,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x2f,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f, + 0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0x30,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x2f,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x2f,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0x48,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04, + 0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x2f,0x50,0x00,0x03, + 0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x2f,0x80,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00, + 0x00,0x09,0x00,0x2f,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x2f,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f, + 0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0x90,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x2f,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x2f,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0xa8,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x2f,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0xc0,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x2f,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x2f,0xcc,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x2f,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, + 0x00,0x03,0x09,0x00,0x30,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00, + 0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x30,0x04,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x30,0x08,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x30,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x30,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0x20,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x30,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0x2c,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0x30,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x30,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0x44, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0x48,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x30,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00, + 0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x30,0x50,0x00,0x03,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x30,0x80,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09, + 0x00,0x30,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x30,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0x8c,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0x90,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x30,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0xa4, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0xa8,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x30,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30, + 0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0xc0,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x30,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x30,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x30,0xcc,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x30,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03, + 0x09,0x00,0x31,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00, + 0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x31,0x04,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x31,0x08,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x31,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31, + 0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0x20,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x31,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x31,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0x2c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x31,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x31,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0x44,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x31,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x31,0x50,0x00,0x03,0x00,0x00,0x00,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x31,0x80,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x31, + 0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x31,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0x8c,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x31,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x31,0xa0,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0xa4,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x31,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0xb0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0xc0,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x31,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0xc8, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x31,0xcc,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x31, + 0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00, + 0x32,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04, + 0x00,0x00,0x00,0x00,0x09,0x00,0x32,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x32,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x32,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0x10,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0x20,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x32,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0x28, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0x2c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x32,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32, + 0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0x44,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x32,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x32,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00, + 0x00,0x00,0x00,0x00,0x09,0x00,0x32,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x32,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x32,0x84,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x32,0x88, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0x8c,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x32,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32, + 0xa0,0x00,0x21,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0xa4,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x32,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x32,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0xb0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x32,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x32,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0xc8,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x32,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x32,0xd0,0x00, + 0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x33,0x00, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, + 0x00,0x00,0x09,0x00,0x33,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x00,0x09,0x00,0x33,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x33,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x10,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x33,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x28,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x33,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x40,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x44,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x33,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x4c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00, + 0x00,0x00,0x09,0x00,0x33,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x03,0x09,0x00,0x33,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00, + 0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x33,0x84,0x00,0x01,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x33,0x88,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x33,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xa0,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xa4,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x33,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xac, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xb0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x33,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33, + 0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc8,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x33,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00, + 0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x33,0xd0,0x00,0x03,0x00, + 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x34,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00, + 0x09,0x00,0x34,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x00,0x09,0x00,0x34,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x0c, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x10,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x34,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34, + 0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x28,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x34,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x34,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x40,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x34,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x4c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00, + 0x09,0x00,0x34,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00, + 0x03,0x09,0x00,0x34,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00, + 0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x84,0x00,0x01,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x88,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x34,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x34,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa0,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x34,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xac,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x34,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xc4,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xc8,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x34,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e, + 0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0xd0,0x00,0x03,0x00,0x00,0x00, + 0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0x00,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00, + 0x35,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09, + 0x00,0x35,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x0c,0x00,0x01, + 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01, + 0x09,0x00,0x35,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x24,0x00, + 0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x28,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x35,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x30, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x40,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x35,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35, + 0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x4c,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00, + 0x35,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09, + 0x00,0x35,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00, + 0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x88,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x09,0x00,0x35,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x90, + 0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa0,0x00,0x01,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x35,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35, + 0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x01,0x00,0x00, + 0x00,0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00, + 0x35,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x01,0x00, + 0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09, + 0x00,0x35,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01, + 0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x00,0x01,0x00,0x00,0x00,0x00, + 0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xe8,0x08,0x00,0x00,0x00,0x06,0x01,0x00, + 0x09,0x05,0x00,0x02,0x08,0xee,0x04,0x00,0x00,0x00,0x01,0x08,0x00,0x00,0x00,0x22, + 0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00, + 0x00,0x01,0x03,0xff,0xff,0xff,0xff,0x09,0x00,0x00,0x04,0x38,0x03,0x00,0x00,0x00, + 0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x03,0x00,0x00,0x04,0x38,0x01,0x09,0x00,0x00, + 0x0c,0x00,0x03,0x00,0x00,0x08,0x00,0x01,0x09,0x00,0x00,0x10,0x00,0x03,0x00,0x00, + 0x0c,0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x03,0x00,0x00,0x10,0x00,0x01,0x09,0x00, + 0x00,0x24,0x38,0x03,0x00,0x00,0x20,0x00,0x01,0x09,0x00,0x00,0x28,0x00,0x03,0x00, + 0x00,0x24,0x38,0x01,0x09,0x00,0x00,0x2c,0x00,0x03,0x00,0x00,0x28,0x00,0x01,0x09, + 0x00,0x00,0x30,0x00,0x03,0x00,0x00,0x2c,0x00,0x01,0x09,0x00,0x00,0x40,0x00,0x03, + 0x00,0x00,0x30,0x00,0x01,0x09,0x00,0x00,0x44,0x14,0x03,0x00,0x00,0x40,0x00,0x01, + 0x09,0x00,0x00,0x48,0x00,0x03,0x00,0x00,0x44,0x14,0x01,0x09,0x00,0x00,0x4c,0x00, + 0x03,0x00,0x00,0x48,0x00,0x01,0x09,0x00,0x00,0x50,0x00,0x03,0x00,0x00,0x4c,0x00, + 0x01,0x09,0x00,0x00,0x80,0x00,0x03,0x00,0x00,0x50,0x00,0x01,0x09,0x00,0x00,0x84, + 0x00,0x03,0x00,0x00,0x80,0x00,0x01,0x09,0x00,0x00,0x88,0x00,0x03,0x00,0x00,0x84, + 0x00,0x01,0x09,0x00,0x00,0x8c,0x00,0x03,0x00,0x00,0x88,0x00,0x01,0x09,0x00,0x00, + 0x90,0x00,0x03,0x00,0x00,0x8c,0x00,0x01,0x09,0x00,0x00,0xa0,0x00,0x03,0x00,0x00, + 0x90,0x00,0x01,0x09,0x00,0x00,0xa4,0x00,0x03,0x00,0x00,0xa0,0x00,0x01,0x09,0x00, + 0x00,0xa8,0x00,0x03,0x00,0x00,0xa4,0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x03,0x00, + 0x00,0xa8,0x00,0x01,0x09,0x00,0x00,0xb0,0x00,0x03,0x00,0x00,0xac,0x00,0x01,0x09, + 0x00,0x00,0xc0,0x00,0x03,0x00,0x00,0xb0,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x03, + 0x00,0x00,0xc0,0x00,0x01,0x09,0x00,0x00,0xc8,0x00,0x03,0x00,0x00,0xc4,0x00,0x01, + 0x09,0x00,0x00,0xcc,0x00,0x03,0x00,0x00,0xc8,0x00,0x01,0x09,0x00,0x00,0xd0,0x00, + 0x03,0x00,0x00,0xcc,0x00,0x01,0x09,0x00,0x01,0x00,0x01,0x03,0x00,0x00,0xd0,0x00, + 0x01,0x09,0x00,0x01,0x04,0x00,0x03,0x00,0x01,0x00,0x01,0x01,0x09,0x00,0x01,0x08, + 0x01,0x03,0x00,0x01,0x04,0x00,0x01,0x09,0x00,0x01,0x0c,0x00,0x03,0x00,0x01,0x08, + 0x01,0x01,0x09,0x00,0x01,0x10,0x00,0x03,0x00,0x01,0x0c,0x00,0x01,0x09,0x00,0x01, + 0x20,0x00,0x03,0x00,0x01,0x10,0x00,0x01,0x09,0x00,0x01,0x24,0x00,0x03,0x00,0x01, + 0x20,0x00,0x01,0x09,0x00,0x01,0x28,0x00,0x03,0x00,0x01,0x24,0x00,0x01,0x09,0x00, + 0x01,0x2c,0x00,0x03,0x00,0x01,0x28,0x00,0x01,0x09,0x00,0x01,0x30,0x00,0x03,0x00, + 0x01,0x2c,0x00,0x01,0x09,0x00,0x01,0x40,0x00,0x03,0x00,0x01,0x30,0x00,0x01,0x09, + 0x00,0x01,0x44,0x00,0x03,0x00,0x01,0x40,0x00,0x01,0x09,0x00,0x01,0x48,0x00,0x03, + 0x00,0x01,0x44,0x00,0x01,0x09,0x00,0x01,0x4c,0x00,0x03,0x00,0x01,0x48,0x00,0x01, + 0x09,0x00,0x01,0x50,0x00,0x03,0x00,0x01,0x4c,0x00,0x01,0x09,0x00,0x01,0x80,0x00, + 0x03,0x00,0x01,0x50,0x00,0x01,0x09,0x00,0x01,0x84,0x00,0x03,0x00,0x01,0x80,0x00, + 0x01,0x09,0x00,0x01,0x88,0x00,0x03,0x00,0x01,0x84,0x00,0x01,0x09,0x00,0x01,0x8c, + 0x00,0x03,0x00,0x01,0x88,0x00,0x01,0x09,0x00,0x01,0x90,0x00,0x03,0x00,0x01,0x8c, + 0x00,0x01,0x09,0x00,0x01,0xa0,0x10,0x03,0x00,0x01,0x90,0x00,0x01,0x09,0x00,0x01, + 0xa4,0x00,0x03,0x00,0x01,0xa0,0x10,0x01,0x09,0x00,0x01,0xa8,0x00,0x03,0x00,0x01, + 0xa4,0x00,0x01,0x09,0x00,0x01,0xac,0x00,0x03,0x00,0x01,0xa8,0x00,0x01,0x09,0x00, + 0x01,0xb0,0x00,0x03,0x00,0x01,0xac,0x00,0x01,0x09,0x00,0x01,0xc0,0x00,0x23,0x00, + 0x01,0xb0,0x00,0x01,0x09,0x00,0x01,0xc4,0x00,0x03,0x00,0x01,0xc0,0x00,0x21,0x09, + 0x00,0x01,0xc8,0x00,0x03,0x00,0x01,0xc4,0x00,0x01,0x09,0x00,0x01,0xcc,0x00,0x03, + 0x00,0x01,0xc8,0x00,0x01,0x09,0x00,0x01,0xd0,0x00,0x03,0x00,0x01,0xcc,0x00,0x01, + 0x09,0x00,0x02,0x00,0x00,0x03,0x00,0x01,0xd0,0x00,0x01,0x09,0x00,0x02,0x04,0x00, + 0x03,0x00,0x02,0x00,0x00,0x01,0x09,0x00,0x02,0x08,0x00,0x03,0x00,0x02,0x04,0x00, + 0x01,0x09,0x00,0x02,0x0c,0x00,0x03,0x00,0x02,0x08,0x00,0x01,0x09,0x00,0x02,0x10, + 0x00,0x03,0x00,0x02,0x0c,0x00,0x01,0x09,0x00,0x02,0x20,0x00,0x03,0x00,0x02,0x10, + 0x00,0x01,0x09,0x00,0x02,0x24,0x00,0x03,0x00,0x02,0x20,0x00,0x01,0x09,0x00,0x02, + 0x28,0x00,0x03,0x00,0x02,0x24,0x00,0x01,0x09,0x00,0x02,0x2c,0x00,0x03,0x00,0x02, + 0x28,0x00,0x01,0x09,0x00,0x02,0x30,0x00,0x03,0x00,0x02,0x2c,0x00,0x01,0x09,0x00, + 0x02,0x40,0x00,0x03,0x00,0x02,0x30,0x00,0x01,0x09,0x00,0x02,0x44,0x00,0x03,0x00, + 0x02,0x40,0x00,0x01,0x09,0x00,0x02,0x48,0x00,0x03,0x00,0x02,0x44,0x00,0x01,0x09, + 0x00,0x02,0x4c,0x00,0x03,0x00,0x02,0x48,0x00,0x01,0x09,0x00,0x02,0x50,0x00,0x03, + 0x00,0x02,0x4c,0x00,0x01,0x09,0x00,0x02,0x80,0x00,0x03,0x00,0x02,0x50,0x00,0x01, + 0x09,0x00,0x02,0x84,0x00,0x03,0x00,0x02,0x80,0x00,0x01,0x09,0x00,0x02,0x88,0x00, + 0x03,0x00,0x02,0x84,0x00,0x01,0x09,0x00,0x02,0x8c,0x00,0x03,0x00,0x02,0x88,0x00, + 0x01,0x09,0x00,0x02,0x90,0x00,0x03,0x00,0x02,0x8c,0x00,0x01,0x09,0x00,0x02,0xa0, + 0x00,0x83,0x00,0x02,0x90,0x00,0x01,0x09,0x00,0x02,0xa4,0x00,0x03,0x00,0x02,0xa0, + 0x00,0x81,0x09,0x00,0x02,0xa8,0x00,0x03,0x00,0x02,0xa4,0x00,0x01,0x09,0x00,0x02, + 0xac,0x00,0x03,0x00,0x02,0xa8,0x00,0x01,0x09,0x00,0x02,0xb0,0x00,0x03,0x00,0x02, + 0xac,0x00,0x01,0x09,0x00,0x02,0xc0,0x00,0x03,0x00,0x02,0xb0,0x00,0x01,0x09,0x00, + 0x02,0xc4,0x00,0x03,0x00,0x02,0xc0,0x00,0x01,0x09,0x00,0x02,0xc8,0x00,0x03,0x00, + 0x02,0xc4,0x00,0x01,0x09,0x00,0x02,0xcc,0x00,0x03,0x00,0x02,0xc8,0x00,0x01,0x09, + 0x00,0x02,0xd0,0x00,0x03,0x00,0x02,0xcc,0x00,0x01,0x09,0x00,0x03,0x00,0x01,0x03, + 0x00,0x02,0xd0,0x00,0x01,0x09,0x00,0x03,0x04,0x03,0x03,0x00,0x03,0x00,0x01,0x01, + 0x09,0x00,0x03,0x08,0x00,0x03,0x00,0x03,0x04,0x03,0x01,0x09,0x00,0x03,0x0c,0x00, + 0x03,0x00,0x03,0x08,0x00,0x01,0x09,0x00,0x03,0x10,0x01,0x03,0x00,0x03,0x0c,0x00, + 0x01,0x09,0x00,0x03,0x20,0x02,0x03,0x00,0x03,0x10,0x01,0x01,0x09,0x00,0x03,0x24, + 0x03,0x03,0x00,0x03,0x20,0x02,0x01,0x09,0x00,0x03,0x28,0x01,0x03,0x00,0x03,0x24, + 0x03,0x01,0x09,0x00,0x03,0x2c,0x00,0x03,0x00,0x03,0x28,0x01,0x01,0x09,0x00,0x03, + 0x30,0x00,0x03,0x00,0x03,0x2c,0x00,0x01,0x09,0x00,0x03,0x40,0x00,0x03,0x00,0x03, + 0x30,0x00,0x01,0x09,0x00,0x03,0x44,0x00,0x03,0x00,0x03,0x40,0x00,0x01,0x09,0x00, + 0x03,0x48,0x00,0x03,0x00,0x03,0x44,0x00,0x01,0x09,0x00,0x03,0x4c,0x00,0x03,0x00, + 0x03,0x48,0x00,0x01,0x09,0x00,0x03,0x50,0x00,0x03,0x00,0x03,0x4c,0x00,0x01,0x09, + 0x00,0x03,0x80,0x01,0x43,0x00,0x03,0x50,0x00,0x01,0x09,0x00,0x03,0x84,0x02,0x03, + 0x00,0x03,0x80,0x01,0x41,0x09,0x00,0x03,0x88,0x00,0x03,0x00,0x03,0x84,0x02,0x01, + 0x09,0x00,0x03,0x8c,0x03,0x03,0x00,0x03,0x88,0x00,0x01,0x09,0x00,0x03,0x90,0x00, + 0x03,0x00,0x03,0x8c,0x03,0x01,0x09,0x00,0x03,0xa0,0x03,0x03,0x00,0x03,0x90,0x00, + 0x01,0x09,0x00,0x03,0xa4,0x01,0x03,0x00,0x03,0xa0,0x03,0x01,0x09,0x00,0x03,0xa8, + 0x00,0x03,0x00,0x03,0xa4,0x01,0x01,0x09,0x00,0x03,0xac,0x00,0x03,0x00,0x03,0xa8, + 0x00,0x01,0x09,0x00,0x03,0xb0,0x00,0x03,0x00,0x03,0xac,0x00,0x01,0x09,0x00,0x03, + 0xc0,0x00,0x03,0x00,0x03,0xb0,0x00,0x01,0x09,0x00,0x03,0xc4,0x00,0x03,0x00,0x03, + 0xc0,0x00,0x01,0x09,0x00,0x03,0xc8,0x00,0x03,0x00,0x03,0xc4,0x00,0x01,0x09,0x00, + 0x03,0xcc,0x00,0x03,0x00,0x03,0xc8,0x00,0x01,0x09,0x00,0x03,0xd0,0x00,0x03,0x00, + 0x03,0xcc,0x00,0x01,0x09,0x00,0x04,0x00,0x00,0x03,0x00,0x03,0xd0,0x00,0x01,0x09, + 0x00,0x04,0x04,0x00,0x03,0x00,0x04,0x00,0x00,0x01,0x09,0x00,0x04,0x08,0x00,0x03, + 0x00,0x04,0x04,0x00,0x01,0x09,0x00,0x04,0x0c,0x00,0x03,0x00,0x04,0x08,0x00,0x01, + 0x09,0x00,0x04,0x10,0x00,0x03,0x00,0x04,0x0c,0x00,0x01,0x09,0x00,0x04,0x20,0x00, + 0x03,0x00,0x04,0x10,0x00,0x01,0x09,0x00,0x04,0x24,0x00,0x03,0x00,0x04,0x20,0x00, + 0x01,0x09,0x00,0x04,0x28,0x00,0x03,0x00,0x04,0x24,0x00,0x01,0x09,0x00,0x04,0x2c, + 0x00,0x03,0x00,0x04,0x28,0x00,0x01,0x09,0x00,0x04,0x30,0x00,0x03,0x00,0x04,0x2c, + 0x00,0x01,0x09,0x00,0x04,0x40,0x00,0x03,0x00,0x04,0x30,0x00,0x01,0x09,0x00,0x04, + 0x44,0x00,0x03,0x00,0x04,0x40,0x00,0x01,0x09,0x00,0x04,0x48,0x00,0x03,0x00,0x04, + 0x44,0x00,0x01,0x09,0x00,0x04,0x4c,0x00,0x03,0x00,0x04,0x48,0x00,0x01,0x09,0x00, + 0x04,0x50,0x00,0x03,0x00,0x04,0x4c,0x00,0x01,0x09,0x00,0x04,0x80,0x00,0x03,0x00, + 0x04,0x50,0x00,0x01,0x09,0x00,0x04,0x84,0x00,0x03,0x00,0x04,0x80,0x00,0x01,0x09, + 0x00,0x04,0x88,0x00,0x03,0x00,0x04,0x84,0x00,0x01,0x09,0x00,0x04,0x8c,0x00,0x03, + 0x00,0x04,0x88,0x00,0x01,0x09,0x00,0x04,0x90,0x00,0x03,0x00,0x04,0x8c,0x00,0x01, + 0x09,0x00,0x04,0xa0,0x00,0x43,0x00,0x04,0x90,0x00,0x01,0x09,0x00,0x04,0xa4,0x00, + 0x03,0x00,0x04,0xa0,0x00,0x41,0x09,0x00,0x04,0xa8,0x00,0x03,0x00,0x04,0xa4,0x00, + 0x01,0x09,0x00,0x04,0xac,0x00,0x03,0x00,0x04,0xa8,0x00,0x01,0x09,0x00,0x04,0xb0, + 0x00,0x03,0x00,0x04,0xac,0x00,0x01,0x09,0x00,0x04,0xc0,0x00,0x03,0x00,0x04,0xb0, + 0x00,0x01,0x09,0x00,0x04,0xc4,0x00,0x03,0x00,0x04,0xc0,0x00,0x01,0x09,0x00,0x04, + 0xc8,0x00,0x03,0x00,0x04,0xc4,0x00,0x01,0x09,0x00,0x04,0xcc,0x00,0x03,0x00,0x04, + 0xc8,0x00,0x01,0x09,0x00,0x04,0xd0,0x00,0x03,0x00,0x04,0xcc,0x00,0x01,0x09,0x00, + 0x05,0x00,0xc0,0x13,0x00,0x04,0xd0,0x00,0x01,0x09,0x00,0x05,0x04,0xc0,0x03,0x00, + 0x05,0x00,0xc0,0x11,0x09,0x00,0x05,0x08,0x40,0x33,0x00,0x05,0x04,0xc0,0x01,0x09, + 0x00,0x05,0x0c,0x00,0x03,0x00,0x05,0x08,0x40,0x31,0x09,0x00,0x05,0x10,0x80,0x03, + 0x00,0x05,0x0c,0x00,0x01,0x09,0x00,0x05,0x20,0x00,0x13,0x00,0x05,0x10,0x80,0x01, + 0x09,0x00,0x05,0x24,0x00,0x13,0x00,0x05,0x20,0x00,0x11,0x09,0x00,0x05,0x28,0x00, + 0x03,0x00,0x05,0x24,0x00,0x11,0x09,0x00,0x05,0x2c,0x00,0x03,0x00,0x05,0x28,0x00, + 0x01,0x09,0x00,0x05,0x30,0x00,0x13,0x00,0x05,0x2c,0x00,0x01,0x09,0x00,0x05,0x40, + 0x20,0x1b,0x00,0x05,0x30,0x00,0x11,0x09,0x00,0x05,0x44,0x20,0x13,0x00,0x05,0x40, + 0x20,0x19,0x09,0x00,0x05,0x48,0x48,0x0b,0x00,0x05,0x44,0x20,0x11,0x09,0x00,0x05, + 0x4c,0x00,0x03,0x00,0x05,0x48,0x48,0x09,0x09,0x00,0x05,0x50,0x00,0x13,0x00,0x05, + 0x4c,0x00,0x01,0x09,0x00,0x05,0x80,0x00,0x23,0x00,0x05,0x50,0x00,0x11,0x01,0x03, + 0xff,0xfc,0xfc,0xff,0x09,0x00,0x05,0x84,0x00,0x13,0x00,0x05,0x80,0x00,0x21,0x01, + 0x03,0xff,0xff,0xff,0xff,0x09,0x00,0x05,0x88,0x80,0x03,0x00,0x05,0x84,0x00,0x11, + 0x09,0x00,0x05,0x8c,0x80,0x03,0x00,0x05,0x88,0x80,0x01,0x09,0x00,0x05,0x90,0x00, + 0x03,0x00,0x05,0x8c,0x80,0x01,0x09,0x00,0x05,0xa0,0x04,0x03,0x00,0x05,0x90,0x00, + 0x01,0x09,0x00,0x05,0xa4,0x00,0x03,0x00,0x05,0xa0,0x04,0x01,0x09,0x00,0x05,0xa8, + 0x00,0x13,0x00,0x05,0xa4,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x13,0x00,0x05,0xa8, + 0x00,0x11,0x09,0x00,0x05,0xb0,0x00,0x03,0x00,0x05,0xac,0x00,0x11,0x09,0x00,0x05, + 0xc0,0xc8,0x03,0x00,0x05,0xb0,0x00,0x01,0x09,0x00,0x05,0xc4,0x08,0x0b,0x00,0x05, + 0xc0,0xc8,0x01,0x09,0x00,0x05,0xc8,0x00,0x13,0x00,0x05,0xc4,0x08,0x09,0x09,0x00, + 0x05,0xcc,0x00,0x13,0x00,0x05,0xc8,0x00,0x11,0x09,0x00,0x05,0xd0,0x00,0x03,0x00, + 0x05,0xcc,0x00,0x11,0x09,0x00,0x06,0x03,0x02,0x03,0x00,0x05,0xd0,0x00,0x01,0x09, + 0x00,0x06,0x07,0x42,0x03,0x00,0x06,0x03,0x02,0x01,0x09,0x00,0x06,0x0b,0x02,0x03, + 0x00,0x06,0x07,0x42,0x01,0x09,0x00,0x06,0x0f,0x02,0x03,0x00,0x06,0x0b,0x02,0x01, + 0x09,0x00,0x06,0x13,0x02,0x03,0x00,0x06,0x0f,0x02,0x01,0x09,0x00,0x06,0x23,0x03, + 0x03,0x00,0x06,0x13,0x02,0x01,0x09,0x00,0x06,0x27,0x03,0x03,0x00,0x06,0x23,0x03, + 0x01,0x09,0x00,0x06,0x2b,0x03,0x03,0x00,0x06,0x27,0x03,0x01,0x09,0x00,0x06,0x2f, + 0x01,0x03,0x00,0x06,0x2b,0x03,0x01,0x09,0x00,0x06,0x30,0x00,0x03,0x00,0x06,0x2f, + 0x01,0x01,0x09,0x00,0x06,0x40,0x00,0x03,0x00,0x06,0x30,0x00,0x01,0x09,0x00,0x06, + 0x44,0x00,0x03,0x00,0x06,0x40,0x00,0x01,0x09,0x00,0x06,0x48,0x00,0x03,0x00,0x06, + 0x44,0x00,0x01,0x09,0x00,0x06,0x4c,0x00,0x03,0x00,0x06,0x48,0x00,0x01,0x09,0x00, + 0x06,0x50,0x00,0x03,0x00,0x06,0x4c,0x00,0x01,0x09,0x00,0x06,0x80,0x04,0x03,0x00, + 0x06,0x50,0x00,0x01,0x09,0x00,0x06,0x84,0x00,0x03,0x00,0x06,0x80,0x04,0x01,0x09, + 0x00,0x06,0x88,0x00,0x03,0x00,0x06,0x84,0x00,0x01,0x09,0x00,0x06,0x8c,0x00,0x03, + 0x00,0x06,0x88,0x00,0x01,0x09,0x00,0x06,0x90,0x00,0x03,0x00,0x06,0x8c,0x00,0x01, + 0x09,0x00,0x06,0xa0,0x00,0x03,0x00,0x06,0x90,0x00,0x01,0x09,0x00,0x06,0xa4,0x00, + 0x03,0x00,0x06,0xa0,0x00,0x01,0x09,0x00,0x06,0xa8,0x00,0x03,0x00,0x06,0xa4,0x00, + 0x01,0x09,0x00,0x06,0xac,0x00,0x03,0x00,0x06,0xa8,0x00,0x01,0x09,0x00,0x06,0xb0, + 0x00,0x03,0x00,0x06,0xac,0x00,0x01,0x09,0x00,0x06,0xc0,0x00,0x03,0x00,0x06,0xb0, + 0x00,0x01,0x09,0x00,0x06,0xc4,0x00,0x03,0x00,0x06,0xc0,0x00,0x01,0x09,0x00,0x06, + 0xc8,0x40,0x03,0x00,0x06,0xc4,0x00,0x01,0x09,0x00,0x06,0xcc,0x80,0x03,0x00,0x06, + 0xc8,0x40,0x01,0x09,0x00,0x06,0xd0,0x00,0x03,0x00,0x06,0xcc,0x80,0x01,0x09,0x00, + 0x07,0x02,0x02,0x03,0x00,0x06,0xd0,0x00,0x01,0x09,0x00,0x07,0x07,0x02,0x03,0x00, + 0x07,0x02,0x02,0x01,0x09,0x00,0x07,0x0b,0x02,0x03,0x00,0x07,0x07,0x02,0x01,0x09, + 0x00,0x07,0x0f,0x02,0x03,0x00,0x07,0x0b,0x02,0x01,0x09,0x00,0x07,0x11,0x02,0x03, + 0x00,0x07,0x0f,0x02,0x01,0x09,0x00,0x07,0x23,0x03,0x03,0x00,0x07,0x11,0x02,0x01, + 0x09,0x00,0x07,0x27,0x03,0x03,0x00,0x07,0x23,0x03,0x01,0x09,0x00,0x07,0x2b,0x03, + 0x03,0x00,0x07,0x27,0x03,0x01,0x09,0x00,0x07,0x2f,0x01,0x03,0x00,0x07,0x2b,0x03, + 0x01,0x09,0x00,0x07,0x30,0x00,0x03,0x00,0x07,0x2f,0x01,0x01,0x09,0x00,0x07,0x40, + 0x00,0x03,0x00,0x07,0x30,0x00,0x01,0x09,0x00,0x07,0x44,0x00,0x03,0x00,0x07,0x40, + 0x00,0x01,0x09,0x00,0x07,0x48,0x00,0x03,0x00,0x07,0x44,0x00,0x01,0x09,0x00,0x07, + 0x4c,0x00,0x03,0x00,0x07,0x48,0x00,0x01,0x09,0x00,0x07,0x50,0x00,0x03,0x00,0x07, + 0x4c,0x00,0x01,0x09,0x00,0x07,0x82,0x00,0x03,0x00,0x07,0x50,0x00,0x01,0x09,0x00, + 0x07,0x86,0x02,0x03,0x00,0x07,0x82,0x00,0x01,0x09,0x00,0x07,0x89,0x02,0x03,0x00, + 0x07,0x86,0x02,0x01,0x09,0x00,0x07,0x8d,0x02,0x03,0x00,0x07,0x89,0x02,0x01,0x09, + 0x00,0x07,0x91,0x02,0x03,0x00,0x07,0x8d,0x02,0x01,0x09,0x00,0x07,0xa0,0x02,0x03, + 0x00,0x07,0x91,0x02,0x01,0x09,0x00,0x07,0xa5,0x02,0x03,0x00,0x07,0xa0,0x02,0x01, + 0x09,0x00,0x07,0xab,0x02,0x03,0x00,0x07,0xa5,0x02,0x01,0x09,0x00,0x07,0xad,0x00, + 0x03,0x00,0x07,0xab,0x02,0x01,0x09,0x00,0x07,0xb0,0x00,0x03,0x00,0x07,0xad,0x00, + 0x01,0x09,0x00,0x07,0xc0,0x04,0x03,0x00,0x07,0xb0,0x00,0x01,0x09,0x00,0x07,0xc4, + 0x00,0x03,0x00,0x07,0xc0,0x04,0x01,0x09,0x00,0x07,0xc8,0x00,0x03,0x00,0x07,0xc4, + 0x00,0x01,0x09,0x00,0x07,0xcc,0x00,0x03,0x00,0x07,0xc8,0x00,0x01,0x09,0x00,0x07, + 0xd0,0x00,0x03,0x00,0x07,0xcc,0x00,0x01,0x09,0x00,0x08,0x00,0x02,0x03,0x00,0x07, + 0xd0,0x00,0x01,0x09,0x00,0x08,0x04,0x00,0x03,0x00,0x08,0x00,0x02,0x01,0x09,0x00, + 0x08,0x08,0x00,0x03,0x00,0x08,0x04,0x00,0x01,0x09,0x00,0x08,0x0e,0x00,0x03,0x00, + 0x08,0x08,0x00,0x01,0x09,0x00,0x08,0x10,0x00,0x03,0x00,0x08,0x0e,0x00,0x01,0x09, + 0x00,0x08,0x23,0x01,0x03,0x00,0x08,0x10,0x00,0x01,0x09,0x00,0x08,0x26,0x01,0x03, + 0x00,0x08,0x23,0x01,0x01,0x09,0x00,0x08,0x28,0x01,0x03,0x00,0x08,0x26,0x01,0x01, + 0x09,0x00,0x08,0x2e,0x01,0x03,0x00,0x08,0x28,0x01,0x01,0x09,0x00,0x08,0x30,0x00, + 0x03,0x00,0x08,0x2e,0x01,0x01,0x09,0x00,0x08,0x40,0x00,0x03,0x00,0x08,0x30,0x00, + 0x01,0x09,0x00,0x08,0x44,0x00,0x03,0x00,0x08,0x40,0x00,0x01,0x09,0x00,0x08,0x48, + 0x00,0x03,0x00,0x08,0x44,0x00,0x01,0x09,0x00,0x08,0x4c,0x00,0x03,0x00,0x08,0x48, + 0x00,0x01,0x09,0x00,0x08,0x50,0x00,0x03,0x00,0x08,0x4c,0x00,0x01,0x09,0x00,0x08, + 0x80,0x00,0x03,0x00,0x08,0x50,0x00,0x01,0x09,0x00,0x08,0x84,0x00,0x03,0x00,0x08, + 0x80,0x00,0x01,0x09,0x00,0x08,0x88,0x00,0x03,0x00,0x08,0x84,0x00,0x01,0x09,0x00, + 0x08,0x8c,0x00,0x03,0x00,0x08,0x88,0x00,0x01,0x09,0x00,0x08,0x90,0x00,0x03,0x00, + 0x08,0x8c,0x00,0x01,0x09,0x00,0x08,0xa0,0x80,0x03,0x00,0x08,0x90,0x00,0x01,0x09, + 0x00,0x08,0xa4,0x00,0x03,0x00,0x08,0xa0,0x80,0x01,0x09,0x00,0x08,0xa8,0x00,0x03, + 0x00,0x08,0xa4,0x00,0x01,0x09,0x00,0x08,0xac,0x00,0x03,0x00,0x08,0xa8,0x00,0x01, + 0x09,0x00,0x08,0xb0,0x00,0x03,0x00,0x08,0xac,0x00,0x01,0x09,0x00,0x08,0xc0,0x00, + 0x03,0x00,0x08,0xb0,0x00,0x01,0x09,0x00,0x08,0xc4,0x00,0x03,0x00,0x08,0xc0,0x00, + 0x01,0x09,0x00,0x08,0xc8,0x00,0x03,0x00,0x08,0xc4,0x00,0x01,0x09,0x00,0x08,0xcc, + 0x00,0x03,0x00,0x08,0xc8,0x00,0x01,0x09,0x00,0x08,0xd0,0x00,0x03,0x00,0x08,0xcc, + 0x00,0x01,0x09,0x00,0x09,0x00,0x00,0x03,0x00,0x08,0xd0,0x00,0x01,0x09,0x00,0x09, + 0x04,0x00,0x03,0x00,0x09,0x00,0x00,0x01,0x09,0x00,0x09,0x08,0x00,0x03,0x00,0x09, + 0x04,0x00,0x01,0x09,0x00,0x09,0x0c,0x00,0x03,0x00,0x09,0x08,0x00,0x01,0x09,0x00, + 0x09,0x10,0x00,0x03,0x00,0x09,0x0c,0x00,0x01,0x09,0x00,0x09,0x20,0x00,0x03,0x00, + 0x09,0x10,0x00,0x01,0x09,0x00,0x09,0x26,0x00,0x03,0x00,0x09,0x20,0x00,0x01,0x09, + 0x00,0x09,0x28,0x01,0x03,0x00,0x09,0x26,0x00,0x01,0x09,0x00,0x09,0x2e,0x01,0x03, + 0x00,0x09,0x28,0x01,0x01,0x09,0x00,0x09,0x30,0x00,0x03,0x00,0x09,0x2e,0x01,0x01, + 0x09,0x00,0x09,0x40,0x00,0x03,0x00,0x09,0x30,0x00,0x01,0x09,0x00,0x09,0x44,0x00, + 0x03,0x00,0x09,0x40,0x00,0x01,0x09,0x00,0x09,0x48,0x00,0x03,0x00,0x09,0x44,0x00, + 0x01,0x09,0x00,0x09,0x4c,0x00,0x03,0x00,0x09,0x48,0x00,0x01,0x09,0x00,0x09,0x50, + 0x00,0x03,0x00,0x09,0x4c,0x00,0x01,0x09,0x00,0x09,0x80,0x10,0x03,0x00,0x09,0x50, + 0x00,0x01,0x09,0x00,0x09,0x84,0x00,0x03,0x00,0x09,0x80,0x10,0x01,0x09,0x00,0x09, + 0x88,0x00,0x03,0x00,0x09,0x84,0x00,0x01,0x09,0x00,0x09,0x8c,0x00,0x03,0x00,0x09, + 0x88,0x00,0x01,0x09,0x00,0x09,0x90,0x00,0x03,0x00,0x09,0x8c,0x00,0x01,0x09,0x00, + 0x09,0xa0,0x00,0x03,0x00,0x09,0x90,0x00,0x01,0x09,0x00,0x09,0xa4,0x00,0x03,0x00, + 0x09,0xa0,0x00,0x01,0x09,0x00,0x09,0xa8,0x00,0x03,0x00,0x09,0xa4,0x00,0x01,0x09, + 0x00,0x09,0xac,0x00,0x03,0x00,0x09,0xa8,0x00,0x01,0x09,0x00,0x09,0xb0,0x00,0x03, + 0x00,0x09,0xac,0x00,0x01,0x09,0x00,0x09,0xc0,0x00,0x03,0x00,0x09,0xb0,0x00,0x01, + 0x09,0x00,0x09,0xc4,0x00,0x03,0x00,0x09,0xc0,0x00,0x01,0x09,0x00,0x09,0xc8,0x00, + 0x03,0x00,0x09,0xc4,0x00,0x01,0x09,0x00,0x09,0xcc,0x00,0x03,0x00,0x09,0xc8,0x00, + 0x01,0x09,0x00,0x09,0xd0,0x00,0x03,0x00,0x09,0xcc,0x00,0x01,0x09,0x00,0x0a,0x00, + 0x00,0x03,0x00,0x09,0xd0,0x00,0x01,0x09,0x00,0x0a,0x04,0x00,0x03,0x00,0x0a,0x00, + 0x00,0x01,0x09,0x00,0x0a,0x08,0x00,0x03,0x00,0x0a,0x04,0x00,0x01,0x09,0x00,0x0a, + 0x0c,0x00,0x03,0x00,0x0a,0x08,0x00,0x01,0x09,0x00,0x0a,0x10,0x00,0x03,0x00,0x0a, + 0x0c,0x00,0x01,0x09,0x00,0x0a,0x20,0x00,0x03,0x00,0x0a,0x10,0x00,0x01,0x09,0x00, + 0x0a,0x26,0x00,0x03,0x00,0x0a,0x20,0x00,0x01,0x09,0x00,0x0a,0x28,0x01,0x03,0x00, + 0x0a,0x26,0x00,0x01,0x09,0x00,0x0a,0x2c,0x01,0x03,0x00,0x0a,0x28,0x01,0x01,0x09, + 0x00,0x0a,0x30,0x00,0x03,0x00,0x0a,0x2c,0x01,0x01,0x09,0x00,0x0a,0x40,0x00,0x03, + 0x00,0x0a,0x30,0x00,0x01,0x09,0x00,0x0a,0x44,0x00,0x03,0x00,0x0a,0x40,0x00,0x01, + 0x09,0x00,0x0a,0x48,0x00,0x03,0x00,0x0a,0x44,0x00,0x01,0x09,0x00,0x0a,0x4c,0x00, + 0x03,0x00,0x0a,0x48,0x00,0x01,0x09,0x00,0x0a,0x50,0x00,0x03,0x00,0x0a,0x4c,0x00, + 0x01,0x09,0x00,0x0a,0x80,0x00,0x03,0x00,0x0a,0x50,0x00,0x01,0x09,0x00,0x0a,0x84, + 0x00,0x03,0x00,0x0a,0x80,0x00,0x01,0x09,0x00,0x0a,0x88,0x00,0x03,0x00,0x0a,0x84, + 0x00,0x01,0x09,0x00,0x0a,0x8c,0x00,0x03,0x00,0x0a,0x88,0x00,0x01,0x09,0x00,0x0a, + 0x90,0x00,0x03,0x00,0x0a,0x8c,0x00,0x01,0x09,0x00,0x0a,0xa0,0x00,0x03,0x00,0x0a, + 0x90,0x00,0x01,0x09,0x00,0x0a,0xa4,0x00,0x03,0x00,0x0a,0xa0,0x00,0x01,0x09,0x00, + 0x0a,0xa8,0x00,0x03,0x00,0x0a,0xa4,0x00,0x01,0x09,0x00,0x0a,0xac,0x00,0x03,0x00, + 0x0a,0xa8,0x00,0x01,0x09,0x00,0x0a,0xb0,0x00,0x03,0x00,0x0a,0xac,0x00,0x01,0x09, + 0x00,0x0a,0xc0,0x00,0x43,0x00,0x0a,0xb0,0x00,0x01,0x09,0x00,0x0a,0xc4,0x00,0x03, + 0x00,0x0a,0xc0,0x00,0x41,0x09,0x00,0x0a,0xc8,0x00,0x03,0x00,0x0a,0xc4,0x00,0x01, + 0x09,0x00,0x0a,0xcc,0x00,0x03,0x00,0x0a,0xc8,0x00,0x01,0x09,0x00,0x0a,0xd0,0x00, + 0x03,0x00,0x0a,0xcc,0x00,0x01,0x09,0x00,0x0b,0x00,0x00,0x03,0x00,0x0a,0xd0,0x00, + 0x01,0x09,0x00,0x0b,0x04,0x00,0x03,0x00,0x0b,0x00,0x00,0x01,0x09,0x00,0x0b,0x0a, + 0x00,0x03,0x00,0x0b,0x04,0x00,0x01,0x09,0x00,0x0b,0x0c,0x00,0x03,0x00,0x0b,0x0a, + 0x00,0x01,0x09,0x00,0x0b,0x10,0x00,0x03,0x00,0x0b,0x0c,0x00,0x01,0x09,0x00,0x0b, + 0x22,0x01,0x03,0x00,0x0b,0x10,0x00,0x01,0x09,0x00,0x0b,0x26,0x01,0x03,0x00,0x0b, + 0x22,0x01,0x01,0x09,0x00,0x0b,0x28,0x01,0x03,0x00,0x0b,0x26,0x01,0x01,0x09,0x00, + 0x0b,0x2e,0x01,0x03,0x00,0x0b,0x28,0x01,0x01,0x09,0x00,0x0b,0x30,0x00,0x03,0x00, + 0x0b,0x2e,0x01,0x01,0x09,0x00,0x0b,0x40,0x00,0x03,0x00,0x0b,0x30,0x00,0x01,0x09, + 0x00,0x0b,0x44,0x00,0x03,0x00,0x0b,0x40,0x00,0x01,0x09,0x00,0x0b,0x48,0x00,0x03, + 0x00,0x0b,0x44,0x00,0x01,0x09,0x00,0x0b,0x4c,0x00,0x03,0x00,0x0b,0x48,0x00,0x01, + 0x09,0x00,0x0b,0x50,0x00,0x03,0x00,0x0b,0x4c,0x00,0x01,0x09,0x00,0x0b,0x80,0x00, + 0x03,0x00,0x0b,0x50,0x00,0x01,0x09,0x00,0x0b,0x84,0x00,0x03,0x00,0x0b,0x80,0x00, + 0x01,0x09,0x00,0x0b,0x88,0x00,0x03,0x00,0x0b,0x84,0x00,0x01,0x09,0x00,0x0b,0x8c, + 0x00,0x03,0x00,0x0b,0x88,0x00,0x01,0x09,0x00,0x0b,0x90,0x00,0x03,0x00,0x0b,0x8c, + 0x00,0x01,0x09,0x00,0x0b,0xa0,0x20,0x03,0x00,0x0b,0x90,0x00,0x01,0x09,0x00,0x0b, + 0xa4,0x00,0x03,0x00,0x0b,0xa0,0x20,0x01,0x09,0x00,0x0b,0xa8,0x00,0x03,0x00,0x0b, + 0xa4,0x00,0x01,0x09,0x00,0x0b,0xac,0x00,0x03,0x00,0x0b,0xa8,0x00,0x01,0x09,0x00, + 0x0b,0xb0,0x00,0x03,0x00,0x0b,0xac,0x00,0x01,0x09,0x00,0x0b,0xc0,0x00,0x03,0x00, + 0x0b,0xb0,0x00,0x01,0x09,0x00,0x0b,0xc4,0x00,0x03,0x00,0x0b,0xc0,0x00,0x01,0x09, + 0x00,0x0b,0xc8,0x00,0x03,0x00,0x0b,0xc4,0x00,0x01,0x09,0x00,0x0b,0xcc,0x00,0x03, + 0x00,0x0b,0xc8,0x00,0x01,0x09,0x00,0x0b,0xd0,0x00,0x03,0x00,0x0b,0xcc,0x00,0x01, + 0x09,0x00,0x0c,0x00,0x00,0x03,0x00,0x0b,0xd0,0x00,0x01,0x09,0x00,0x0c,0x04,0x00, + 0x03,0x00,0x0c,0x00,0x00,0x01,0x09,0x00,0x0c,0x08,0x00,0x03,0x00,0x0c,0x04,0x00, + 0x01,0x09,0x00,0x0c,0x0c,0x00,0x03,0x00,0x0c,0x08,0x00,0x01,0x09,0x00,0x0c,0x10, + 0x00,0x03,0x00,0x0c,0x0c,0x00,0x01,0x09,0x00,0x0c,0x20,0x00,0x03,0x00,0x0c,0x10, + 0x00,0x01,0x09,0x00,0x0c,0x24,0x00,0x03,0x00,0x0c,0x20,0x00,0x01,0x09,0x00,0x0c, + 0x28,0x00,0x03,0x00,0x0c,0x24,0x00,0x01,0x09,0x00,0x0c,0x2c,0x00,0x03,0x00,0x0c, + 0x28,0x00,0x01,0x09,0x00,0x0c,0x30,0x00,0x03,0x00,0x0c,0x2c,0x00,0x01,0x09,0x00, + 0x0c,0x40,0x00,0x03,0x00,0x0c,0x30,0x00,0x01,0x09,0x00,0x0c,0x44,0x00,0x03,0x00, + 0x0c,0x40,0x00,0x01,0x09,0x00,0x0c,0x48,0x00,0x03,0x00,0x0c,0x44,0x00,0x01,0x09, + 0x00,0x0c,0x4c,0x00,0x03,0x00,0x0c,0x48,0x00,0x01,0x09,0x00,0x0c,0x50,0x00,0x03, + 0x00,0x0c,0x4c,0x00,0x01,0x09,0x00,0x0c,0x80,0x00,0x83,0x00,0x0c,0x50,0x00,0x01, + 0x09,0x00,0x0c,0x84,0x00,0x03,0x00,0x0c,0x80,0x00,0x81,0x09,0x00,0x0c,0x88,0x00, + 0x03,0x00,0x0c,0x84,0x00,0x01,0x09,0x00,0x0c,0x8c,0x00,0x03,0x00,0x0c,0x88,0x00, + 0x01,0x09,0x00,0x0c,0x90,0x00,0x03,0x00,0x0c,0x8c,0x00,0x01,0x09,0x00,0x0c,0xa0, + 0x00,0x03,0x00,0x0c,0x90,0x00,0x01,0x09,0x00,0x0c,0xa4,0x00,0x03,0x00,0x0c,0xa0, + 0x00,0x01,0x09,0x00,0x0c,0xa8,0x00,0x03,0x00,0x0c,0xa4,0x00,0x01,0x09,0x00,0x0c, + 0xac,0x00,0x03,0x00,0x0c,0xa8,0x00,0x01,0x09,0x00,0x0c,0xb0,0x00,0x03,0x00,0x0c, + 0xac,0x00,0x01,0x09,0x00,0x0c,0xc0,0x00,0x03,0x00,0x0c,0xb0,0x00,0x01,0x09,0x00, + 0x0c,0xc4,0x00,0x03,0x00,0x0c,0xc0,0x00,0x01,0x09,0x00,0x0c,0xc8,0x00,0x03,0x00, + 0x0c,0xc4,0x00,0x01,0x09,0x00,0x0c,0xcc,0x00,0x03,0x00,0x0c,0xc8,0x00,0x01,0x09, + 0x00,0x0c,0xd0,0x00,0x03,0x00,0x0c,0xcc,0x00,0x01,0x09,0x00,0x0d,0x03,0x02,0x03, + 0x00,0x0c,0xd0,0x00,0x01,0x09,0x00,0x0d,0x07,0x02,0x03,0x00,0x0d,0x03,0x02,0x01, + 0x09,0x00,0x0d,0x0b,0x02,0x03,0x00,0x0d,0x07,0x02,0x01,0x09,0x00,0x0d,0x0f,0x02, + 0x03,0x00,0x0d,0x0b,0x02,0x01,0x09,0x00,0x0d,0x13,0x02,0x03,0x00,0x0d,0x0f,0x02, + 0x01,0x09,0x00,0x0d,0x23,0x03,0x03,0x00,0x0d,0x13,0x02,0x01,0x09,0x00,0x0d,0x27, + 0x07,0x03,0x00,0x0d,0x23,0x03,0x01,0x09,0x00,0x0d,0x2b,0x03,0x03,0x00,0x0d,0x27, + 0x07,0x01,0x09,0x00,0x0d,0x2f,0x01,0x03,0x00,0x0d,0x2b,0x03,0x01,0x09,0x00,0x0d, + 0x30,0x00,0x03,0x00,0x0d,0x2f,0x01,0x01,0x09,0x00,0x0d,0x40,0x00,0x03,0x00,0x0d, + 0x30,0x00,0x01,0x09,0x00,0x0d,0x44,0x00,0x03,0x00,0x0d,0x40,0x00,0x01,0x09,0x00, + 0x0d,0x48,0x00,0x03,0x00,0x0d,0x44,0x00,0x01,0x09,0x00,0x0d,0x4c,0x00,0x03,0x00, + 0x0d,0x48,0x00,0x01,0x09,0x00,0x0d,0x50,0x00,0x03,0x00,0x0d,0x4c,0x00,0x01,0x09, + 0x00,0x0d,0x80,0x04,0x03,0x00,0x0d,0x50,0x00,0x01,0x09,0x00,0x0d,0x84,0x00,0x03, + 0x00,0x0d,0x80,0x04,0x01,0x09,0x00,0x0d,0x88,0x00,0x03,0x00,0x0d,0x84,0x00,0x01, + 0x09,0x00,0x0d,0x8c,0x00,0x03,0x00,0x0d,0x88,0x00,0x01,0x09,0x00,0x0d,0x90,0x00, + 0x03,0x00,0x0d,0x8c,0x00,0x01,0x09,0x00,0x0d,0xa0,0x00,0x03,0x00,0x0d,0x90,0x00, + 0x01,0x09,0x00,0x0d,0xa4,0x00,0x03,0x00,0x0d,0xa0,0x00,0x01,0x09,0x00,0x0d,0xa8, + 0x00,0x03,0x00,0x0d,0xa4,0x00,0x01,0x09,0x00,0x0d,0xac,0x00,0x03,0x00,0x0d,0xa8, + 0x00,0x01,0x09,0x00,0x0d,0xb0,0x00,0x03,0x00,0x0d,0xac,0x00,0x01,0x09,0x00,0x0d, + 0xc0,0x00,0x03,0x00,0x0d,0xb0,0x00,0x01,0x09,0x00,0x0d,0xc4,0x00,0x03,0x00,0x0d, + 0xc0,0x00,0x01,0x09,0x00,0x0d,0xc8,0x00,0x03,0x00,0x0d,0xc4,0x00,0x01,0x09,0x00, + 0x0d,0xcc,0x00,0x03,0x00,0x0d,0xc8,0x00,0x01,0x09,0x00,0x0d,0xd0,0x00,0x03,0x00, + 0x0d,0xcc,0x00,0x01,0x09,0x00,0x0e,0x00,0x00,0x03,0x00,0x0d,0xd0,0x00,0x01,0x09, + 0x00,0x0e,0x04,0xc0,0x03,0x00,0x0e,0x00,0x00,0x01,0x09,0x00,0x0e,0x08,0x00,0x03, + 0x00,0x0e,0x04,0xc0,0x01,0x09,0x00,0x0e,0x0c,0x80,0x03,0x00,0x0e,0x08,0x00,0x01, + 0x09,0x00,0x0e,0x10,0x00,0x03,0x00,0x0e,0x0c,0x80,0x01,0x09,0x00,0x0e,0x20,0x00, + 0x03,0x00,0x0e,0x10,0x00,0x01,0x09,0x00,0x0e,0x24,0x00,0x13,0x00,0x0e,0x20,0x00, + 0x01,0x09,0x00,0x0e,0x28,0x00,0x03,0x00,0x0e,0x24,0x00,0x11,0x09,0x00,0x0e,0x2c, + 0x00,0x13,0x00,0x0e,0x28,0x00,0x01,0x09,0x00,0x0e,0x30,0x00,0x03,0x00,0x0e,0x2c, + 0x00,0x11,0x09,0x00,0x0e,0x40,0x60,0x03,0x00,0x0e,0x30,0x00,0x01,0x09,0x00,0x0e, + 0x44,0x48,0x13,0x00,0x0e,0x40,0x60,0x01,0x09,0x00,0x0e,0x48,0xc0,0x03,0x00,0x0e, + 0x44,0x48,0x11,0x09,0x00,0x0e,0x4c,0x80,0x13,0x00,0x0e,0x48,0xc0,0x01,0x09,0x00, + 0x0e,0x50,0x00,0x03,0x00,0x0e,0x4c,0x80,0x11,0x09,0x00,0x0e,0x80,0x00,0x03,0x00, + 0x0e,0x50,0x00,0x01,0x09,0x00,0x0e,0x84,0x00,0x23,0x00,0x0e,0x80,0x00,0x01,0x09, + 0x00,0x0e,0x88,0x40,0x13,0x00,0x0e,0x84,0x00,0x21,0x09,0x00,0x0e,0x8c,0x00,0x03, + 0x00,0x0e,0x88,0x40,0x11,0x09,0x00,0x0e,0x90,0x00,0x03,0x00,0x0e,0x8c,0x00,0x01, + 0x09,0x00,0x0e,0xa0,0x00,0x03,0x00,0x0e,0x90,0x00,0x01,0x09,0x00,0x0e,0xa4,0x00, + 0x03,0x00,0x0e,0xa0,0x00,0x01,0x09,0x00,0x0e,0xa8,0x00,0x03,0x00,0x0e,0xa4,0x00, + 0x01,0x09,0x00,0x0e,0xac,0x00,0x03,0x00,0x0e,0xa8,0x00,0x01,0x09,0x00,0x0e,0xb0, + 0x00,0x03,0x00,0x0e,0xac,0x00,0x01,0x09,0x00,0x0e,0xc0,0x00,0x03,0x00,0x0e,0xb0, + 0x00,0x01,0x09,0x00,0x0e,0xc4,0xa0,0x03,0x00,0x0e,0xc0,0x00,0x01,0x09,0x00,0x0e, + 0xc8,0x08,0x0b,0x00,0x0e,0xc4,0xa0,0x01,0x09,0x00,0x0e,0xcc,0x00,0x03,0x00,0x0e, + 0xc8,0x08,0x09,0x09,0x00,0x0e,0xd0,0x00,0x03,0x00,0x0e,0xcc,0x00,0x01,0x09,0x00, + 0x0f,0x00,0x02,0x03,0x00,0x0e,0xd0,0x00,0x01,0x09,0x00,0x0f,0x04,0x00,0x03,0x00, + 0x0f,0x00,0x02,0x01,0x09,0x00,0x0f,0x0a,0x00,0x03,0x00,0x0f,0x04,0x00,0x01,0x09, + 0x00,0x0f,0x0c,0x00,0x03,0x00,0x0f,0x0a,0x00,0x01,0x09,0x00,0x0f,0x12,0x00,0x03, + 0x00,0x0f,0x0c,0x00,0x01,0x09,0x00,0x0f,0x20,0x01,0x03,0x00,0x0f,0x12,0x00,0x01, + 0x09,0x00,0x0f,0x26,0x01,0x03,0x00,0x0f,0x20,0x01,0x01,0x09,0x00,0x0f,0x28,0x01, + 0x03,0x00,0x0f,0x26,0x01,0x01,0x09,0x00,0x0f,0x2c,0x01,0x03,0x00,0x0f,0x28,0x01, + 0x01,0x09,0x00,0x0f,0x30,0x00,0x03,0x00,0x0f,0x2c,0x01,0x01,0x09,0x00,0x0f,0x40, + 0x00,0x03,0x00,0x0f,0x30,0x00,0x01,0x09,0x00,0x0f,0x44,0x00,0x03,0x00,0x0f,0x40, + 0x00,0x01,0x09,0x00,0x0f,0x48,0x00,0x03,0x00,0x0f,0x44,0x00,0x01,0x09,0x00,0x0f, + 0x4c,0x00,0x03,0x00,0x0f,0x48,0x00,0x01,0x09,0x00,0x0f,0x50,0x00,0x03,0x00,0x0f, + 0x4c,0x00,0x01,0x09,0x00,0x0f,0x80,0x00,0x03,0x00,0x0f,0x50,0x00,0x01,0x09,0x00, + 0x0f,0x84,0x00,0x03,0x00,0x0f,0x80,0x00,0x01,0x09,0x00,0x0f,0x88,0x00,0x03,0x00, + 0x0f,0x84,0x00,0x01,0x09,0x00,0x0f,0x8c,0x00,0x03,0x00,0x0f,0x88,0x00,0x01,0x09, + 0x00,0x0f,0x90,0x00,0x03,0x00,0x0f,0x8c,0x00,0x01,0x09,0x00,0x0f,0xa0,0x00,0x03, + 0x00,0x0f,0x90,0x00,0x01,0x09,0x00,0x0f,0xa4,0x00,0x03,0x00,0x0f,0xa0,0x00,0x01, + 0x09,0x00,0x0f,0xa8,0x00,0x03,0x00,0x0f,0xa4,0x00,0x01,0x09,0x00,0x0f,0xac,0x00, + 0x03,0x00,0x0f,0xa8,0x00,0x01,0x09,0x00,0x0f,0xb0,0x00,0x03,0x00,0x0f,0xac,0x00, + 0x01,0x09,0x00,0x0f,0xc0,0x10,0x03,0x00,0x0f,0xb0,0x00,0x01,0x09,0x00,0x0f,0xc4, + 0x00,0x03,0x00,0x0f,0xc0,0x10,0x01,0x09,0x00,0x0f,0xc8,0x00,0x03,0x00,0x0f,0xc4, + 0x00,0x01,0x09,0x00,0x0f,0xcc,0x00,0x03,0x00,0x0f,0xc8,0x00,0x01,0x09,0x00,0x0f, + 0xd0,0x00,0x03,0x00,0x0f,0xcc,0x00,0x01,0x09,0x00,0x10,0x01,0x82,0x03,0x00,0x0f, + 0xd0,0x00,0x01,0x09,0x00,0x10,0x05,0x82,0x03,0x00,0x10,0x01,0x82,0x01,0x09,0x00, + 0x10,0x0a,0x82,0x03,0x00,0x10,0x05,0x82,0x01,0x09,0x00,0x10,0x0c,0x82,0x03,0x00, + 0x10,0x0a,0x82,0x01,0x09,0x00,0x10,0x12,0x82,0x03,0x00,0x10,0x0c,0x82,0x01,0x09, + 0x00,0x10,0x20,0x03,0x13,0x00,0x10,0x12,0x82,0x01,0x09,0x00,0x10,0x26,0x03,0x13, + 0x00,0x10,0x20,0x03,0x11,0x09,0x00,0x10,0x2a,0x03,0x13,0x00,0x10,0x26,0x03,0x11, + 0x09,0x00,0x10,0x2c,0x01,0x13,0x00,0x10,0x2a,0x03,0x11,0x09,0x00,0x10,0x30,0x00, + 0x13,0x00,0x10,0x2c,0x01,0x11,0x09,0x00,0x10,0x40,0x00,0x13,0x00,0x10,0x30,0x00, + 0x11,0x09,0x00,0x10,0x44,0x00,0x13,0x00,0x10,0x40,0x00,0x11,0x09,0x00,0x10,0x48, + 0x00,0x13,0x00,0x10,0x44,0x00,0x11,0x09,0x00,0x10,0x4c,0x00,0x13,0x00,0x10,0x48, + 0x00,0x11,0x09,0x00,0x10,0x50,0x00,0x13,0x00,0x10,0x4c,0x00,0x11,0x09,0x00,0x10, + 0x80,0x00,0x03,0x00,0x10,0x50,0x00,0x11,0x09,0x00,0x10,0x84,0x00,0x03,0x00,0x10, + 0x80,0x00,0x01,0x09,0x00,0x10,0x88,0x00,0x03,0x00,0x10,0x84,0x00,0x01,0x09,0x00, + 0x10,0x8c,0x00,0x03,0x00,0x10,0x88,0x00,0x01,0x09,0x00,0x10,0x90,0x00,0x03,0x00, + 0x10,0x8c,0x00,0x01,0x09,0x00,0x10,0xa0,0x00,0x03,0x00,0x10,0x90,0x00,0x01,0x09, + 0x00,0x10,0xa4,0x00,0x03,0x00,0x10,0xa0,0x00,0x01,0x09,0x00,0x10,0xa8,0x00,0x03, + 0x00,0x10,0xa4,0x00,0x01,0x09,0x00,0x10,0xac,0x00,0x03,0x00,0x10,0xa8,0x00,0x01, + 0x09,0x00,0x10,0xb0,0x00,0x03,0x00,0x10,0xac,0x00,0x01,0x09,0x00,0x10,0xc0,0x00, + 0x03,0x00,0x10,0xb0,0x00,0x01,0x09,0x00,0x10,0xc4,0x00,0x03,0x00,0x10,0xc0,0x00, + 0x01,0x09,0x00,0x10,0xc8,0x00,0x03,0x00,0x10,0xc4,0x00,0x01,0x09,0x00,0x10,0xcc, + 0x00,0x03,0x00,0x10,0xc8,0x00,0x01,0x09,0x00,0x10,0xd0,0x00,0x03,0x00,0x10,0xcc, + 0x00,0x01,0x09,0x00,0x11,0x00,0xc0,0x13,0x00,0x10,0xd0,0x00,0x01,0x09,0x00,0x11, + 0x04,0x00,0x13,0x00,0x11,0x00,0xc0,0x11,0x09,0x00,0x11,0x08,0x80,0x23,0x00,0x11, + 0x04,0x00,0x11,0x09,0x00,0x11,0x0c,0x00,0x03,0x00,0x11,0x08,0x80,0x21,0x09,0x00, + 0x11,0x10,0x00,0x03,0x00,0x11,0x0c,0x00,0x01,0x09,0x00,0x11,0x20,0x00,0x13,0x00, + 0x11,0x10,0x00,0x01,0x09,0x00,0x11,0x24,0x00,0x03,0x00,0x11,0x20,0x00,0x11,0x09, + 0x00,0x11,0x28,0x00,0x13,0x00,0x11,0x24,0x00,0x01,0x09,0x00,0x11,0x2c,0x00,0x03, + 0x00,0x11,0x28,0x00,0x11,0x09,0x00,0x11,0x30,0x00,0x03,0x00,0x11,0x2c,0x00,0x01, + 0x09,0x00,0x11,0x40,0x08,0x1b,0x00,0x11,0x30,0x00,0x01,0x09,0x00,0x11,0x44,0x20, + 0x0b,0x00,0x11,0x40,0x08,0x19,0x09,0x00,0x11,0x48,0xc0,0x13,0x00,0x11,0x44,0x20, + 0x09,0x09,0x00,0x11,0x4c,0x00,0x03,0x00,0x11,0x48,0xc0,0x11,0x09,0x00,0x11,0x50, + 0x00,0x03,0x00,0x11,0x4c,0x00,0x01,0x09,0x00,0x11,0x80,0x00,0x03,0x00,0x11,0x50, + 0x00,0x01,0x09,0x00,0x11,0x84,0x00,0x23,0x00,0x11,0x80,0x00,0x01,0x09,0x00,0x11, + 0x88,0x40,0x13,0x00,0x11,0x84,0x00,0x21,0x09,0x00,0x11,0x8c,0x00,0x03,0x00,0x11, + 0x88,0x40,0x11,0x09,0x00,0x11,0x90,0x80,0x03,0x00,0x11,0x8c,0x00,0x01,0x09,0x00, + 0x11,0xa0,0x00,0x03,0x00,0x11,0x90,0x80,0x01,0x09,0x00,0x11,0xa4,0x00,0x03,0x00, + 0x11,0xa0,0x00,0x01,0x09,0x00,0x11,0xa8,0x00,0x03,0x00,0x11,0xa4,0x00,0x01,0x09, + 0x00,0x11,0xac,0x00,0x03,0x00,0x11,0xa8,0x00,0x01,0x09,0x00,0x11,0xb0,0x00,0x13, + 0x00,0x11,0xac,0x00,0x01,0x09,0x00,0x11,0xc0,0x20,0x03,0x00,0x11,0xb0,0x00,0x11, + 0x09,0x00,0x11,0xc4,0xc0,0x03,0x00,0x11,0xc0,0x20,0x01,0x09,0x00,0x11,0xc8,0x08, + 0x0b,0x00,0x11,0xc4,0xc0,0x01,0x09,0x00,0x11,0xcc,0x00,0x03,0x00,0x11,0xc8,0x08, + 0x09,0x09,0x00,0x11,0xd0,0x00,0x13,0x00,0x11,0xcc,0x00,0x01,0x09,0x00,0x12,0x00, + 0x00,0x03,0x00,0x11,0xd0,0x00,0x11,0x09,0x00,0x12,0x04,0x00,0x03,0x00,0x12,0x00, + 0x00,0x01,0x09,0x00,0x12,0x08,0x00,0x03,0x00,0x12,0x04,0x00,0x01,0x09,0x00,0x12, + 0x0c,0x00,0x03,0x00,0x12,0x08,0x00,0x01,0x09,0x00,0x12,0x10,0x00,0x03,0x00,0x12, + 0x0c,0x00,0x01,0x09,0x00,0x12,0x20,0x00,0x03,0x00,0x12,0x10,0x00,0x01,0x09,0x00, + 0x12,0x24,0x00,0x03,0x00,0x12,0x20,0x00,0x01,0x09,0x00,0x12,0x28,0x00,0x03,0x00, + 0x12,0x24,0x00,0x01,0x09,0x00,0x12,0x2c,0x00,0x03,0x00,0x12,0x28,0x00,0x01,0x09, + 0x00,0x12,0x30,0x00,0x03,0x00,0x12,0x2c,0x00,0x01,0x09,0x00,0x12,0x40,0x00,0x03, + 0x00,0x12,0x30,0x00,0x01,0x09,0x00,0x12,0x44,0x00,0x03,0x00,0x12,0x40,0x00,0x01, + 0x09,0x00,0x12,0x48,0x00,0x03,0x00,0x12,0x44,0x00,0x01,0x09,0x00,0x12,0x4c,0x00, + 0x03,0x00,0x12,0x48,0x00,0x01,0x09,0x00,0x12,0x50,0x00,0x03,0x00,0x12,0x4c,0x00, + 0x01,0x09,0x00,0x12,0x80,0x00,0x03,0x00,0x12,0x50,0x00,0x01,0x09,0x00,0x12,0x84, + 0x00,0x03,0x00,0x12,0x80,0x00,0x01,0x09,0x00,0x12,0x88,0x00,0x03,0x00,0x12,0x84, + 0x00,0x01,0x09,0x00,0x12,0x8c,0x00,0x03,0x00,0x12,0x88,0x00,0x01,0x09,0x00,0x12, + 0x90,0x00,0x03,0x00,0x12,0x8c,0x00,0x01,0x09,0x00,0x12,0xa0,0x00,0x03,0x00,0x12, + 0x90,0x00,0x01,0x09,0x00,0x12,0xa4,0x00,0x03,0x00,0x12,0xa0,0x00,0x01,0x09,0x00, + 0x12,0xa8,0x00,0x03,0x00,0x12,0xa4,0x00,0x01,0x09,0x00,0x12,0xac,0x00,0x03,0x00, + 0x12,0xa8,0x00,0x01,0x09,0x00,0x12,0xb0,0x00,0x03,0x00,0x12,0xac,0x00,0x01,0x09, + 0x00,0x12,0xc0,0x00,0x03,0x00,0x12,0xb0,0x00,0x01,0x09,0x00,0x12,0xc4,0x00,0x03, + 0x00,0x12,0xc0,0x00,0x01,0x09,0x00,0x12,0xc8,0x00,0x03,0x00,0x12,0xc4,0x00,0x01, + 0x09,0x00,0x12,0xcc,0x00,0x03,0x00,0x12,0xc8,0x00,0x01,0x09,0x00,0x12,0xd0,0x00, + 0x03,0x00,0x12,0xcc,0x00,0x01,0x09,0x00,0x13,0x00,0x00,0x03,0x00,0x12,0xd0,0x00, + 0x01,0x09,0x00,0x13,0x04,0x00,0x03,0x00,0x13,0x00,0x00,0x01,0x09,0x00,0x13,0x08, + 0x00,0x03,0x00,0x13,0x04,0x00,0x01,0x09,0x00,0x13,0x0c,0x00,0x03,0x00,0x13,0x08, + 0x00,0x01,0x09,0x00,0x13,0x10,0x00,0x03,0x00,0x13,0x0c,0x00,0x01,0x09,0x00,0x13, + 0x20,0x00,0x03,0x00,0x13,0x10,0x00,0x01,0x09,0x00,0x13,0x24,0x00,0x03,0x00,0x13, + 0x20,0x00,0x01,0x09,0x00,0x13,0x28,0x00,0x03,0x00,0x13,0x24,0x00,0x01,0x09,0x00, + 0x13,0x2c,0x00,0x03,0x00,0x13,0x28,0x00,0x01,0x09,0x00,0x13,0x30,0x00,0x03,0x00, + 0x13,0x2c,0x00,0x01,0x09,0x00,0x13,0x40,0x00,0x03,0x00,0x13,0x30,0x00,0x01,0x09, + 0x00,0x13,0x44,0x00,0x03,0x00,0x13,0x40,0x00,0x01,0x09,0x00,0x13,0x48,0x00,0x03, + 0x00,0x13,0x44,0x00,0x01,0x09,0x00,0x13,0x4c,0x00,0x03,0x00,0x13,0x48,0x00,0x01, + 0x09,0x00,0x13,0x50,0x00,0x03,0x00,0x13,0x4c,0x00,0x01,0x09,0x00,0x13,0x80,0x00, + 0x03,0x00,0x13,0x50,0x00,0x01,0x09,0x00,0x13,0x84,0x00,0x03,0x00,0x13,0x80,0x00, + 0x01,0x09,0x00,0x13,0x88,0x00,0x03,0x00,0x13,0x84,0x00,0x01,0x09,0x00,0x13,0x8c, + 0x00,0x03,0x00,0x13,0x88,0x00,0x01,0x09,0x00,0x13,0x90,0x00,0x03,0x00,0x13,0x8c, + 0x00,0x01,0x09,0x00,0x13,0xa2,0x00,0x03,0x00,0x13,0x90,0x00,0x01,0x09,0x00,0x13, + 0xa4,0x00,0x03,0x00,0x13,0xa2,0x00,0x01,0x09,0x00,0x13,0xa8,0x00,0x03,0x00,0x13, + 0xa4,0x00,0x01,0x09,0x00,0x13,0xac,0x00,0x03,0x00,0x13,0xa8,0x00,0x01,0x09,0x00, + 0x13,0xb0,0x00,0x03,0x00,0x13,0xac,0x00,0x01,0x09,0x00,0x13,0xc0,0x00,0x03,0x00, + 0x13,0xb0,0x00,0x01,0x09,0x00,0x13,0xc4,0x00,0x03,0x00,0x13,0xc0,0x00,0x01,0x09, + 0x00,0x13,0xc8,0x00,0x03,0x00,0x13,0xc4,0x00,0x01,0x09,0x00,0x13,0xcc,0x00,0x03, + 0x00,0x13,0xc8,0x00,0x01,0x09,0x00,0x13,0xd0,0x00,0x03,0x00,0x13,0xcc,0x00,0x01, + 0x09,0x00,0x14,0x00,0x00,0x03,0x00,0x13,0xd0,0x00,0x01,0x09,0x00,0x14,0x04,0x00, + 0x03,0x00,0x14,0x00,0x00,0x01,0x09,0x00,0x14,0x08,0x00,0x03,0x00,0x14,0x04,0x00, + 0x01,0x09,0x00,0x14,0x0e,0x00,0x03,0x00,0x14,0x08,0x00,0x01,0x09,0x00,0x14,0x10, + 0x00,0x03,0x00,0x14,0x0e,0x00,0x01,0x09,0x00,0x14,0x23,0x00,0x03,0x00,0x14,0x10, + 0x00,0x01,0x09,0x00,0x14,0x24,0x00,0x03,0x00,0x14,0x23,0x00,0x01,0x09,0x00,0x14, + 0x28,0x00,0x03,0x00,0x14,0x24,0x00,0x01,0x09,0x00,0x14,0x2e,0x00,0x03,0x00,0x14, + 0x28,0x00,0x01,0x09,0x00,0x14,0x30,0x00,0x03,0x00,0x14,0x2e,0x00,0x01,0x09,0x00, + 0x14,0x40,0x00,0x03,0x00,0x14,0x30,0x00,0x01,0x09,0x00,0x14,0x44,0x00,0x03,0x00, + 0x14,0x40,0x00,0x01,0x09,0x00,0x14,0x48,0x00,0x03,0x00,0x14,0x44,0x00,0x01,0x09, + 0x00,0x14,0x4c,0x00,0x03,0x00,0x14,0x48,0x00,0x01,0x09,0x00,0x14,0x50,0x00,0x03, + 0x00,0x14,0x4c,0x00,0x01,0x09,0x00,0x14,0x80,0x00,0x03,0x00,0x14,0x50,0x00,0x01, + 0x09,0x00,0x14,0x84,0x00,0x03,0x00,0x14,0x80,0x00,0x01,0x09,0x00,0x14,0x88,0x00, + 0x03,0x00,0x14,0x84,0x00,0x01,0x09,0x00,0x14,0x8c,0x00,0x03,0x00,0x14,0x88,0x00, + 0x01,0x09,0x00,0x14,0x90,0x00,0x03,0x00,0x14,0x8c,0x00,0x01,0x09,0x00,0x14,0xa0, + 0x00,0x03,0x00,0x14,0x90,0x00,0x01,0x09,0x00,0x14,0xa4,0x00,0x03,0x00,0x14,0xa0, + 0x00,0x01,0x09,0x00,0x14,0xa8,0x00,0x03,0x00,0x14,0xa4,0x00,0x01,0x09,0x00,0x14, + 0xac,0x00,0x03,0x00,0x14,0xa8,0x00,0x01,0x09,0x00,0x14,0xb0,0x00,0x03,0x00,0x14, + 0xac,0x00,0x01,0x09,0x00,0x14,0xc0,0x00,0x03,0x00,0x14,0xb0,0x00,0x01,0x09,0x00, + 0x14,0xc4,0x00,0x03,0x00,0x14,0xc0,0x00,0x01,0x09,0x00,0x14,0xc8,0x00,0x03,0x00, + 0x14,0xc4,0x00,0x01,0x09,0x00,0x14,0xcc,0x00,0x03,0x00,0x14,0xc8,0x00,0x01,0x09, + 0x00,0x14,0xd0,0x00,0x03,0x00,0x14,0xcc,0x00,0x01,0x09,0x00,0x15,0x00,0x00,0x03, + 0x00,0x14,0xd0,0x00,0x01,0x09,0x00,0x15,0x04,0x00,0x13,0x00,0x15,0x00,0x00,0x01, + 0x09,0x00,0x15,0x08,0xc0,0x33,0x00,0x15,0x04,0x00,0x11,0x09,0x00,0x15,0x0c,0x80, + 0x03,0x00,0x15,0x08,0xc0,0x31,0x09,0x00,0x15,0x10,0x80,0x03,0x00,0x15,0x0c,0x80, + 0x01,0x09,0x00,0x15,0x20,0x04,0x03,0x00,0x15,0x10,0x80,0x01,0x09,0x00,0x15,0x24, + 0x00,0x03,0x00,0x15,0x20,0x04,0x01,0x09,0x00,0x15,0x28,0x00,0x13,0x00,0x15,0x24, + 0x00,0x01,0x09,0x00,0x15,0x2c,0x00,0x13,0x00,0x15,0x28,0x00,0x11,0x09,0x00,0x15, + 0x30,0x00,0x13,0x00,0x15,0x2c,0x00,0x11,0x09,0x00,0x15,0x40,0x28,0x03,0x00,0x15, + 0x30,0x00,0x11,0x09,0x00,0x15,0x44,0x28,0x0b,0x00,0x15,0x40,0x28,0x01,0x09,0x00, + 0x15,0x48,0x48,0x1b,0x00,0x15,0x44,0x28,0x09,0x09,0x00,0x15,0x4c,0x00,0x13,0x00, + 0x15,0x48,0x48,0x19,0x09,0x00,0x15,0x50,0x00,0x13,0x00,0x15,0x4c,0x00,0x11,0x09, + 0x00,0x15,0x80,0xc0,0x33,0x00,0x15,0x50,0x00,0x11,0x09,0x00,0x15,0x84,0xc0,0x23, + 0x00,0x15,0x80,0xc0,0x31,0x09,0x00,0x15,0x88,0x00,0x03,0x00,0x15,0x84,0xc0,0x21, + 0x09,0x00,0x15,0x8c,0x00,0x03,0x00,0x15,0x88,0x00,0x01,0x09,0x00,0x15,0x90,0x00, + 0x03,0x00,0x15,0x8c,0x00,0x01,0x09,0x00,0x15,0xa0,0x00,0x13,0x00,0x15,0x90,0x00, + 0x01,0x09,0x00,0x15,0xa4,0x00,0x13,0x00,0x15,0xa0,0x00,0x11,0x09,0x00,0x15,0xa8, + 0x00,0x03,0x00,0x15,0xa4,0x00,0x11,0x09,0x00,0x15,0xac,0x00,0x03,0x00,0x15,0xa8, + 0x00,0x01,0x09,0x00,0x15,0xb0,0x00,0x03,0x00,0x15,0xac,0x00,0x01,0x09,0x00,0x15, + 0xc0,0xc0,0x1b,0x00,0x15,0xb0,0x00,0x01,0x09,0x00,0x15,0xc4,0x40,0x13,0x00,0x15, + 0xc0,0xc0,0x19,0x09,0x00,0x15,0xc8,0x00,0x03,0x00,0x15,0xc4,0x40,0x11,0x09,0x00, + 0x15,0xcc,0x80,0x03,0x00,0x15,0xc8,0x00,0x01,0x09,0x00,0x15,0xd0,0x00,0x03,0x00, + 0x15,0xcc,0x80,0x01,0x09,0x00,0x16,0x02,0x02,0x03,0x00,0x15,0xd0,0x00,0x01,0x09, + 0x00,0x16,0x06,0x3a,0x03,0x00,0x16,0x02,0x02,0x01,0x09,0x00,0x16,0x0b,0x42,0x03, + 0x00,0x16,0x06,0x3a,0x01,0x09,0x00,0x16,0x0d,0x02,0x03,0x00,0x16,0x0b,0x42,0x01, + 0x09,0x00,0x16,0x13,0x02,0x03,0x00,0x16,0x0d,0x02,0x01,0x09,0x00,0x16,0x20,0x03, + 0x03,0x00,0x16,0x13,0x02,0x01,0x09,0x00,0x16,0x27,0x3b,0x03,0x00,0x16,0x20,0x03, + 0x01,0x09,0x00,0x16,0x2b,0x03,0x03,0x00,0x16,0x27,0x3b,0x01,0x09,0x00,0x16,0x2d, + 0x01,0x03,0x00,0x16,0x2b,0x03,0x01,0x09,0x00,0x16,0x30,0x00,0x03,0x00,0x16,0x2d, + 0x01,0x01,0x09,0x00,0x16,0x40,0x00,0x0b,0x00,0x16,0x30,0x00,0x01,0x09,0x00,0x16, + 0x44,0x14,0x0b,0x00,0x16,0x40,0x00,0x09,0x09,0x00,0x16,0x48,0x00,0x0b,0x00,0x16, + 0x44,0x14,0x09,0x09,0x00,0x16,0x4c,0x00,0x03,0x00,0x16,0x48,0x00,0x09,0x09,0x00, + 0x16,0x50,0x00,0x03,0x00,0x16,0x4c,0x00,0x01,0x09,0x00,0x16,0x83,0x02,0x13,0x00, + 0x16,0x50,0x00,0x01,0x09,0x00,0x16,0x87,0x02,0x13,0x00,0x16,0x83,0x02,0x11,0x09, + 0x00,0x16,0x8b,0x02,0x13,0x00,0x16,0x87,0x02,0x11,0x09,0x00,0x16,0x8f,0x02,0x03, + 0x00,0x16,0x8b,0x02,0x11,0x09,0x00,0x16,0x93,0x02,0x03,0x00,0x16,0x8f,0x02,0x01, + 0x09,0x00,0x16,0xa3,0x03,0x03,0x00,0x16,0x93,0x02,0x01,0x09,0x00,0x16,0xa7,0x07, + 0x03,0x00,0x16,0xa3,0x03,0x01,0x09,0x00,0x16,0xab,0x03,0x03,0x00,0x16,0xa7,0x07, + 0x01,0x09,0x00,0x16,0xaf,0x01,0x03,0x00,0x16,0xab,0x03,0x01,0x09,0x00,0x16,0xb0, + 0x00,0x03,0x00,0x16,0xaf,0x01,0x01,0x09,0x00,0x16,0xc0,0x00,0x03,0x00,0x16,0xb0, + 0x00,0x01,0x09,0x00,0x16,0xc4,0x00,0x03,0x00,0x16,0xc0,0x00,0x01,0x09,0x00,0x16, + 0xc8,0x08,0x03,0x00,0x16,0xc4,0x00,0x01,0x09,0x00,0x16,0xcc,0x00,0x03,0x00,0x16, + 0xc8,0x08,0x01,0x09,0x00,0x16,0xd0,0x00,0x03,0x00,0x16,0xcc,0x00,0x01,0x09,0x00, + 0x17,0x02,0x02,0x03,0x00,0x16,0xd0,0x00,0x01,0x09,0x00,0x17,0x07,0x02,0x03,0x00, + 0x17,0x02,0x02,0x01,0x09,0x00,0x17,0x0b,0x02,0x03,0x00,0x17,0x07,0x02,0x01,0x09, + 0x00,0x17,0x0f,0x02,0x03,0x00,0x17,0x0b,0x02,0x01,0x09,0x00,0x17,0x11,0x02,0x03, + 0x00,0x17,0x0f,0x02,0x01,0x09,0x00,0x17,0x23,0x03,0x03,0x00,0x17,0x11,0x02,0x01, + 0x09,0x00,0x17,0x27,0x03,0x03,0x00,0x17,0x23,0x03,0x01,0x09,0x00,0x17,0x2b,0x03, + 0x03,0x00,0x17,0x27,0x03,0x01,0x09,0x00,0x17,0x2f,0x01,0x03,0x00,0x17,0x2b,0x03, + 0x01,0x09,0x00,0x17,0x30,0x00,0x03,0x00,0x17,0x2f,0x01,0x01,0x09,0x00,0x17,0x40, + 0x00,0x03,0x00,0x17,0x30,0x00,0x01,0x09,0x00,0x17,0x44,0x00,0x03,0x00,0x17,0x40, + 0x00,0x01,0x09,0x00,0x17,0x48,0x00,0x03,0x00,0x17,0x44,0x00,0x01,0x09,0x00,0x17, + 0x4c,0x00,0x03,0x00,0x17,0x48,0x00,0x01,0x09,0x00,0x17,0x50,0x00,0x03,0x00,0x17, + 0x4c,0x00,0x01,0x09,0x00,0x17,0x80,0x0a,0x03,0x00,0x17,0x50,0x00,0x01,0x09,0x00, + 0x17,0x84,0x00,0x03,0x00,0x17,0x80,0x0a,0x01,0x09,0x00,0x17,0x88,0x00,0x03,0x00, + 0x17,0x84,0x00,0x01,0x09,0x00,0x17,0x8e,0x00,0x03,0x00,0x17,0x88,0x00,0x01,0x09, + 0x00,0x17,0x90,0x00,0x03,0x00,0x17,0x8e,0x00,0x01,0x09,0x00,0x17,0xa3,0x01,0x03, + 0x00,0x17,0x90,0x00,0x01,0x09,0x00,0x17,0xa6,0x01,0x03,0x00,0x17,0xa3,0x01,0x01, + 0x09,0x00,0x17,0xa8,0x01,0x03,0x00,0x17,0xa6,0x01,0x01,0x09,0x00,0x17,0xae,0x01, + 0x03,0x00,0x17,0xa8,0x01,0x01,0x09,0x00,0x17,0xb0,0x00,0x03,0x00,0x17,0xae,0x01, + 0x01,0x09,0x00,0x17,0xc0,0x00,0x03,0x00,0x17,0xb0,0x00,0x01,0x09,0x00,0x17,0xc4, + 0x00,0x03,0x00,0x17,0xc0,0x00,0x01,0x09,0x00,0x17,0xc8,0x00,0x03,0x00,0x17,0xc4, + 0x00,0x01,0x09,0x00,0x17,0xcc,0x00,0x03,0x00,0x17,0xc8,0x00,0x01,0x09,0x00,0x17, + 0xd0,0x00,0x03,0x00,0x17,0xcc,0x00,0x01,0x09,0x00,0x18,0x00,0x00,0x03,0x00,0x17, + 0xd0,0x00,0x01,0x09,0x00,0x18,0x04,0x00,0x03,0x00,0x18,0x00,0x00,0x01,0x09,0x00, + 0x18,0x08,0x00,0x03,0x00,0x18,0x04,0x00,0x01,0x09,0x00,0x18,0x0c,0x00,0x03,0x00, + 0x18,0x08,0x00,0x01,0x09,0x00,0x18,0x10,0x00,0x03,0x00,0x18,0x0c,0x00,0x01,0x09, + 0x00,0x18,0x20,0x00,0x03,0x00,0x18,0x10,0x00,0x01,0x09,0x00,0x18,0x26,0x00,0x03, + 0x00,0x18,0x20,0x00,0x01,0x09,0x00,0x18,0x28,0x01,0x03,0x00,0x18,0x26,0x00,0x01, + 0x09,0x00,0x18,0x2e,0x01,0x03,0x00,0x18,0x28,0x01,0x01,0x09,0x00,0x18,0x30,0x00, + 0x03,0x00,0x18,0x2e,0x01,0x01,0x09,0x00,0x18,0x40,0x00,0x03,0x00,0x18,0x30,0x00, + 0x01,0x09,0x00,0x18,0x44,0x00,0x03,0x00,0x18,0x40,0x00,0x01,0x09,0x00,0x18,0x48, + 0x00,0x03,0x00,0x18,0x44,0x00,0x01,0x09,0x00,0x18,0x4c,0x00,0x03,0x00,0x18,0x48, + 0x00,0x01,0x09,0x00,0x18,0x50,0x00,0x03,0x00,0x18,0x4c,0x00,0x01,0x09,0x00,0x18, + 0x80,0x00,0x03,0x00,0x18,0x50,0x00,0x01,0x09,0x00,0x18,0x84,0x00,0x03,0x00,0x18, + 0x80,0x00,0x01,0x09,0x00,0x18,0x88,0x00,0x03,0x00,0x18,0x84,0x00,0x01,0x09,0x00, + 0x18,0x8c,0x00,0x03,0x00,0x18,0x88,0x00,0x01,0x09,0x00,0x18,0x90,0x00,0x03,0x00, + 0x18,0x8c,0x00,0x01,0x09,0x00,0x18,0xa0,0x00,0x03,0x00,0x18,0x90,0x00,0x01,0x09, + 0x00,0x18,0xa6,0x00,0x03,0x00,0x18,0xa0,0x00,0x01,0x09,0x00,0x18,0xa8,0x01,0x03, + 0x00,0x18,0xa6,0x00,0x01,0x09,0x00,0x18,0xac,0x01,0x03,0x00,0x18,0xa8,0x01,0x01, + 0x09,0x00,0x18,0xb0,0x00,0x03,0x00,0x18,0xac,0x01,0x01,0x09,0x00,0x18,0xc0,0x00, + 0x03,0x00,0x18,0xb0,0x00,0x01,0x09,0x00,0x18,0xc4,0x00,0x03,0x00,0x18,0xc0,0x00, + 0x01,0x09,0x00,0x18,0xc8,0x00,0x03,0x00,0x18,0xc4,0x00,0x01,0x09,0x00,0x18,0xcc, + 0x00,0x03,0x00,0x18,0xc8,0x00,0x01,0x09,0x00,0x18,0xd0,0x00,0x03,0x00,0x18,0xcc, + 0x00,0x01,0x09,0x00,0x19,0x01,0x00,0x03,0x00,0x18,0xd0,0x00,0x01,0x09,0x00,0x19, + 0x04,0x00,0x03,0x00,0x19,0x01,0x00,0x01,0x09,0x00,0x19,0x08,0x00,0x03,0x00,0x19, + 0x04,0x00,0x01,0x09,0x00,0x19,0x0c,0x00,0x03,0x00,0x19,0x08,0x00,0x01,0x09,0x00, + 0x19,0x11,0x00,0x03,0x00,0x19,0x0c,0x00,0x01,0x09,0x00,0x19,0x20,0x00,0x03,0x00, + 0x19,0x11,0x00,0x01,0x09,0x00,0x19,0x24,0x00,0x03,0x00,0x19,0x20,0x00,0x01,0x09, + 0x00,0x19,0x28,0x00,0x03,0x00,0x19,0x24,0x00,0x01,0x09,0x00,0x19,0x2c,0x00,0x03, + 0x00,0x19,0x28,0x00,0x01,0x09,0x00,0x19,0x30,0x00,0x03,0x00,0x19,0x2c,0x00,0x01, + 0x09,0x00,0x19,0x40,0x00,0x03,0x00,0x19,0x30,0x00,0x01,0x09,0x00,0x19,0x44,0x00, + 0x03,0x00,0x19,0x40,0x00,0x01,0x09,0x00,0x19,0x48,0x00,0x03,0x00,0x19,0x44,0x00, + 0x01,0x09,0x00,0x19,0x4c,0x00,0x03,0x00,0x19,0x48,0x00,0x01,0x09,0x00,0x19,0x50, + 0x00,0x03,0x00,0x19,0x4c,0x00,0x01,0x09,0x00,0x19,0x80,0x01,0x03,0x00,0x19,0x50, + 0x00,0x01,0x09,0x00,0x19,0x85,0x00,0x03,0x00,0x19,0x80,0x01,0x01,0x09,0x00,0x19, + 0x88,0x00,0x03,0x00,0x19,0x85,0x00,0x01,0x09,0x00,0x19,0x8c,0x00,0x03,0x00,0x19, + 0x88,0x00,0x01,0x09,0x00,0x19,0x90,0x00,0x03,0x00,0x19,0x8c,0x00,0x01,0x09,0x00, + 0x19,0xa0,0x00,0x03,0x00,0x19,0x90,0x00,0x01,0x09,0x00,0x19,0xa4,0x00,0x03,0x00, + 0x19,0xa0,0x00,0x01,0x09,0x00,0x19,0xa8,0x00,0x03,0x00,0x19,0xa4,0x00,0x01,0x09, + 0x00,0x19,0xac,0x00,0x03,0x00,0x19,0xa8,0x00,0x01,0x09,0x00,0x19,0xb0,0x00,0x03, + 0x00,0x19,0xac,0x00,0x01,0x09,0x00,0x19,0xc0,0x00,0x03,0x00,0x19,0xb0,0x00,0x01, + 0x09,0x00,0x19,0xc4,0x00,0x03,0x00,0x19,0xc0,0x00,0x01,0x09,0x00,0x19,0xc8,0x00, + 0x03,0x00,0x19,0xc4,0x00,0x01,0x09,0x00,0x19,0xcc,0x00,0x03,0x00,0x19,0xc8,0x00, + 0x01,0x09,0x00,0x19,0xd0,0x00,0x03,0x00,0x19,0xcc,0x00,0x01,0x09,0x00,0x1a,0x00, + 0x01,0x03,0x00,0x19,0xd0,0x00,0x01,0x09,0x00,0x1a,0x04,0x00,0x03,0x00,0x1a,0x00, + 0x01,0x01,0x09,0x00,0x1a,0x08,0x00,0x03,0x00,0x1a,0x04,0x00,0x01,0x09,0x00,0x1a, + 0x0c,0x00,0x03,0x00,0x1a,0x08,0x00,0x01,0x09,0x00,0x1a,0x10,0x00,0x03,0x00,0x1a, + 0x0c,0x00,0x01,0x09,0x00,0x1a,0x20,0x00,0x13,0x00,0x1a,0x10,0x00,0x01,0x09,0x00, + 0x1a,0x24,0x00,0x13,0x00,0x1a,0x20,0x00,0x11,0x09,0x00,0x1a,0x28,0x00,0x13,0x00, + 0x1a,0x24,0x00,0x11,0x09,0x00,0x1a,0x2c,0x00,0x13,0x00,0x1a,0x28,0x00,0x11,0x09, + 0x00,0x1a,0x30,0x00,0x13,0x00,0x1a,0x2c,0x00,0x11,0x09,0x00,0x1a,0x40,0x00,0x13, + 0x00,0x1a,0x30,0x00,0x11,0x09,0x00,0x1a,0x44,0x00,0x13,0x00,0x1a,0x40,0x00,0x11, + 0x09,0x00,0x1a,0x48,0x00,0x13,0x00,0x1a,0x44,0x00,0x11,0x09,0x00,0x1a,0x4c,0x00, + 0x13,0x00,0x1a,0x48,0x00,0x11,0x09,0x00,0x1a,0x50,0x00,0x13,0x00,0x1a,0x4c,0x00, + 0x11,0x09,0x00,0x1a,0x82,0x81,0x03,0x00,0x1a,0x50,0x00,0x11,0x09,0x00,0x1a,0x84, + 0x80,0x03,0x00,0x1a,0x82,0x81,0x01,0x09,0x00,0x1a,0x88,0x80,0x03,0x00,0x1a,0x84, + 0x80,0x01,0x09,0x00,0x1a,0x8c,0x80,0x03,0x00,0x1a,0x88,0x80,0x01,0x09,0x00,0x1a, + 0x90,0x80,0x03,0x00,0x1a,0x8c,0x80,0x01,0x09,0x00,0x1a,0xa0,0x00,0x03,0x00,0x1a, + 0x90,0x80,0x01,0x09,0x00,0x1a,0xa4,0x00,0x03,0x00,0x1a,0xa0,0x00,0x01,0x09,0x00, + 0x1a,0xa8,0x00,0x03,0x00,0x1a,0xa4,0x00,0x01,0x09,0x00,0x1a,0xac,0x00,0x03,0x00, + 0x1a,0xa8,0x00,0x01,0x09,0x00,0x1a,0xb0,0x00,0x03,0x00,0x1a,0xac,0x00,0x01,0x09, + 0x00,0x1a,0xc0,0x00,0x03,0x00,0x1a,0xb0,0x00,0x01,0x09,0x00,0x1a,0xc4,0x00,0x03, + 0x00,0x1a,0xc0,0x00,0x01,0x09,0x00,0x1a,0xc8,0x00,0x03,0x00,0x1a,0xc4,0x00,0x01, + 0x09,0x00,0x1a,0xcc,0x00,0x03,0x00,0x1a,0xc8,0x00,0x01,0x09,0x00,0x1a,0xd0,0x00, + 0x03,0x00,0x1a,0xcc,0x00,0x01,0x09,0x00,0x1b,0x00,0x01,0x03,0x00,0x1a,0xd0,0x00, + 0x01,0x09,0x00,0x1b,0x04,0x00,0x03,0x00,0x1b,0x00,0x01,0x01,0x09,0x00,0x1b,0x08, + 0x00,0x03,0x00,0x1b,0x04,0x00,0x01,0x09,0x00,0x1b,0x0c,0x00,0x03,0x00,0x1b,0x08, + 0x00,0x01,0x09,0x00,0x1b,0x10,0x00,0x03,0x00,0x1b,0x0c,0x00,0x01,0x09,0x00,0x1b, + 0x20,0x00,0x03,0x00,0x1b,0x10,0x00,0x01,0x09,0x00,0x1b,0x24,0x00,0x03,0x00,0x1b, + 0x20,0x00,0x01,0x09,0x00,0x1b,0x28,0x00,0x03,0x00,0x1b,0x24,0x00,0x01,0x09,0x00, + 0x1b,0x2c,0x00,0x03,0x00,0x1b,0x28,0x00,0x01,0x09,0x00,0x1b,0x30,0x00,0x03,0x00, + 0x1b,0x2c,0x00,0x01,0x09,0x00,0x1b,0x40,0x00,0x03,0x00,0x1b,0x30,0x00,0x01,0x09, + 0x00,0x1b,0x44,0x00,0x03,0x00,0x1b,0x40,0x00,0x01,0x09,0x00,0x1b,0x48,0x00,0x03, + 0x00,0x1b,0x44,0x00,0x01,0x09,0x00,0x1b,0x4c,0x00,0x03,0x00,0x1b,0x48,0x00,0x01, + 0x09,0x00,0x1b,0x50,0x00,0x03,0x00,0x1b,0x4c,0x00,0x01,0x09,0x00,0x1b,0x81,0x01, + 0x03,0x00,0x1b,0x50,0x00,0x01,0x09,0x00,0x1b,0x84,0x00,0x03,0x00,0x1b,0x81,0x01, + 0x01,0x09,0x00,0x1b,0x88,0x00,0x03,0x00,0x1b,0x84,0x00,0x01,0x09,0x00,0x1b,0x8c, + 0x00,0x03,0x00,0x1b,0x88,0x00,0x01,0x09,0x00,0x1b,0x91,0x01,0x03,0x00,0x1b,0x8c, + 0x00,0x01,0x09,0x00,0x1b,0xa0,0x00,0x03,0x00,0x1b,0x91,0x01,0x01,0x09,0x00,0x1b, + 0xa4,0x00,0x03,0x00,0x1b,0xa0,0x00,0x01,0x09,0x00,0x1b,0xa8,0x00,0x03,0x00,0x1b, + 0xa4,0x00,0x01,0x09,0x00,0x1b,0xac,0x00,0x03,0x00,0x1b,0xa8,0x00,0x01,0x09,0x00, + 0x1b,0xb0,0x00,0x03,0x00,0x1b,0xac,0x00,0x01,0x09,0x00,0x1b,0xc0,0x00,0x03,0x00, + 0x1b,0xb0,0x00,0x01,0x09,0x00,0x1b,0xc4,0x00,0x03,0x00,0x1b,0xc0,0x00,0x01,0x09, + 0x00,0x1b,0xc8,0x00,0x03,0x00,0x1b,0xc4,0x00,0x01,0x09,0x00,0x1b,0xcc,0x00,0x03, + 0x00,0x1b,0xc8,0x00,0x01,0x09,0x00,0x1b,0xd0,0x00,0x03,0x00,0x1b,0xcc,0x00,0x01, + 0x09,0x00,0x1c,0x00,0x00,0x03,0x00,0x1b,0xd0,0x00,0x01,0x09,0x00,0x1c,0x07,0x00, + 0x03,0x00,0x1c,0x00,0x00,0x01,0x09,0x00,0x1c,0x08,0x00,0x03,0x00,0x1c,0x07,0x00, + 0x01,0x09,0x00,0x1c,0x0c,0x00,0x03,0x00,0x1c,0x08,0x00,0x01,0x09,0x00,0x1c,0x10, + 0x00,0x03,0x00,0x1c,0x0c,0x00,0x01,0x09,0x00,0x1c,0x20,0x00,0x03,0x00,0x1c,0x10, + 0x00,0x01,0x09,0x00,0x1c,0x24,0x00,0x03,0x00,0x1c,0x20,0x00,0x01,0x09,0x00,0x1c, + 0x28,0x00,0x03,0x00,0x1c,0x24,0x00,0x01,0x09,0x00,0x1c,0x2c,0x00,0x03,0x00,0x1c, + 0x28,0x00,0x01,0x09,0x00,0x1c,0x30,0x00,0x03,0x00,0x1c,0x2c,0x00,0x01,0x09,0x00, + 0x1c,0x40,0x00,0x03,0x00,0x1c,0x30,0x00,0x01,0x09,0x00,0x1c,0x44,0x00,0x03,0x00, + 0x1c,0x40,0x00,0x01,0x09,0x00,0x1c,0x48,0x00,0x03,0x00,0x1c,0x44,0x00,0x01,0x09, + 0x00,0x1c,0x4c,0x00,0x03,0x00,0x1c,0x48,0x00,0x01,0x09,0x00,0x1c,0x50,0x00,0x03, + 0x00,0x1c,0x4c,0x00,0x01,0x09,0x00,0x1c,0x80,0x00,0x03,0x00,0x1c,0x50,0x00,0x01, + 0x09,0x00,0x1c,0x85,0x00,0x03,0x00,0x1c,0x80,0x00,0x01,0x09,0x00,0x1c,0x88,0x00, + 0x03,0x00,0x1c,0x85,0x00,0x01,0x09,0x00,0x1c,0x8c,0x00,0x03,0x00,0x1c,0x88,0x00, + 0x01,0x09,0x00,0x1c,0x90,0x00,0x03,0x00,0x1c,0x8c,0x00,0x01,0x09,0x00,0x1c,0xa0, + 0x00,0x03,0x00,0x1c,0x90,0x00,0x01,0x09,0x00,0x1c,0xa4,0x00,0x03,0x00,0x1c,0xa0, + 0x00,0x01,0x09,0x00,0x1c,0xa8,0x00,0x03,0x00,0x1c,0xa4,0x00,0x01,0x09,0x00,0x1c, + 0xac,0x00,0x03,0x00,0x1c,0xa8,0x00,0x01,0x09,0x00,0x1c,0xb0,0x00,0x03,0x00,0x1c, + 0xac,0x00,0x01,0x09,0x00,0x1c,0xc0,0x00,0x03,0x00,0x1c,0xb0,0x00,0x01,0x09,0x00, + 0x1c,0xc4,0x00,0x03,0x00,0x1c,0xc0,0x00,0x01,0x09,0x00,0x1c,0xc8,0x00,0x03,0x00, + 0x1c,0xc4,0x00,0x01,0x09,0x00,0x1c,0xcc,0x00,0x03,0x00,0x1c,0xc8,0x00,0x01,0x09, + 0x00,0x1c,0xd0,0x00,0x03,0x00,0x1c,0xcc,0x00,0x01,0x09,0x00,0x1d,0x01,0x00,0x03, + 0x00,0x1c,0xd0,0x00,0x01,0x09,0x00,0x1d,0x04,0x00,0x03,0x00,0x1d,0x01,0x00,0x01, + 0x09,0x00,0x1d,0x08,0x00,0x03,0x00,0x1d,0x04,0x00,0x01,0x09,0x00,0x1d,0x0c,0x00, + 0x03,0x00,0x1d,0x08,0x00,0x01,0x09,0x00,0x1d,0x10,0x00,0x03,0x00,0x1d,0x0c,0x00, + 0x01,0x09,0x00,0x1d,0x20,0x00,0x03,0x00,0x1d,0x10,0x00,0x01,0x09,0x00,0x1d,0x24, + 0x00,0x03,0x00,0x1d,0x20,0x00,0x01,0x09,0x00,0x1d,0x28,0x00,0x03,0x00,0x1d,0x24, + 0x00,0x01,0x09,0x00,0x1d,0x2c,0x00,0x03,0x00,0x1d,0x28,0x00,0x01,0x09,0x00,0x1d, + 0x30,0x00,0x03,0x00,0x1d,0x2c,0x00,0x01,0x09,0x00,0x1d,0x40,0x00,0x03,0x00,0x1d, + 0x30,0x00,0x01,0x09,0x00,0x1d,0x44,0x00,0x03,0x00,0x1d,0x40,0x00,0x01,0x09,0x00, + 0x1d,0x48,0x00,0x03,0x00,0x1d,0x44,0x00,0x01,0x09,0x00,0x1d,0x4c,0x00,0x03,0x00, + 0x1d,0x48,0x00,0x01,0x09,0x00,0x1d,0x50,0x00,0x03,0x00,0x1d,0x4c,0x00,0x01,0x09, + 0x00,0x1d,0x80,0x00,0x03,0x00,0x1d,0x50,0x00,0x01,0x09,0x00,0x1d,0x87,0x00,0x03, + 0x00,0x1d,0x80,0x00,0x01,0x09,0x00,0x1d,0x88,0x00,0x03,0x00,0x1d,0x87,0x00,0x01, + 0x09,0x00,0x1d,0x8c,0x00,0x03,0x00,0x1d,0x88,0x00,0x01,0x09,0x00,0x1d,0x90,0x00, + 0x03,0x00,0x1d,0x8c,0x00,0x01,0x09,0x00,0x1d,0xa0,0x00,0x03,0x00,0x1d,0x90,0x00, + 0x01,0x09,0x00,0x1d,0xa4,0x00,0x03,0x00,0x1d,0xa0,0x00,0x01,0x09,0x00,0x1d,0xa8, + 0x00,0x03,0x00,0x1d,0xa4,0x00,0x01,0x09,0x00,0x1d,0xac,0x00,0x03,0x00,0x1d,0xa8, + 0x00,0x01,0x09,0x00,0x1d,0xb0,0x00,0x03,0x00,0x1d,0xac,0x00,0x01,0x09,0x00,0x1d, + 0xc0,0x00,0x03,0x00,0x1d,0xb0,0x00,0x01,0x09,0x00,0x1d,0xc4,0x00,0x03,0x00,0x1d, + 0xc0,0x00,0x01,0x09,0x00,0x1d,0xc8,0x00,0x03,0x00,0x1d,0xc4,0x00,0x01,0x09,0x00, + 0x1d,0xcc,0x00,0x03,0x00,0x1d,0xc8,0x00,0x01,0x09,0x00,0x1d,0xd0,0x00,0x03,0x00, + 0x1d,0xcc,0x00,0x01,0x09,0x00,0x1e,0x00,0x01,0x03,0x00,0x1d,0xd0,0x00,0x01,0x09, + 0x00,0x1e,0x04,0x00,0x03,0x00,0x1e,0x00,0x01,0x01,0x09,0x00,0x1e,0x08,0x00,0x03, + 0x00,0x1e,0x04,0x00,0x01,0x09,0x00,0x1e,0x0c,0x00,0x03,0x00,0x1e,0x08,0x00,0x01, + 0x09,0x00,0x1e,0x10,0x00,0x03,0x00,0x1e,0x0c,0x00,0x01,0x09,0x00,0x1e,0x20,0x00, + 0x03,0x00,0x1e,0x10,0x00,0x01,0x09,0x00,0x1e,0x24,0x00,0x03,0x00,0x1e,0x20,0x00, + 0x01,0x09,0x00,0x1e,0x28,0x00,0x03,0x00,0x1e,0x24,0x00,0x01,0x09,0x00,0x1e,0x2c, + 0x00,0x03,0x00,0x1e,0x28,0x00,0x01,0x09,0x00,0x1e,0x30,0x00,0x03,0x00,0x1e,0x2c, + 0x00,0x01,0x09,0x00,0x1e,0x40,0x00,0x03,0x00,0x1e,0x30,0x00,0x01,0x09,0x00,0x1e, + 0x44,0x00,0x03,0x00,0x1e,0x40,0x00,0x01,0x09,0x00,0x1e,0x48,0x00,0x03,0x00,0x1e, + 0x44,0x00,0x01,0x09,0x00,0x1e,0x4c,0x00,0x03,0x00,0x1e,0x48,0x00,0x01,0x09,0x00, + 0x1e,0x50,0x00,0x03,0x00,0x1e,0x4c,0x00,0x01,0x09,0x00,0x1e,0x80,0x00,0x03,0x00, + 0x1e,0x50,0x00,0x01,0x09,0x00,0x1e,0x85,0x00,0x03,0x00,0x1e,0x80,0x00,0x01,0x09, + 0x00,0x1e,0x88,0x00,0x03,0x00,0x1e,0x85,0x00,0x01,0x09,0x00,0x1e,0x8c,0x00,0x03, + 0x00,0x1e,0x88,0x00,0x01,0x09,0x00,0x1e,0x90,0x00,0x03,0x00,0x1e,0x8c,0x00,0x01, + 0x09,0x00,0x1e,0xa0,0x08,0x03,0x00,0x1e,0x90,0x00,0x01,0x09,0x00,0x1e,0xa4,0x00, + 0x03,0x00,0x1e,0xa0,0x08,0x01,0x09,0x00,0x1e,0xa8,0x00,0x03,0x00,0x1e,0xa4,0x00, + 0x01,0x09,0x00,0x1e,0xac,0x00,0x03,0x00,0x1e,0xa8,0x00,0x01,0x09,0x00,0x1e,0xb0, + 0x00,0x03,0x00,0x1e,0xac,0x00,0x01,0x09,0x00,0x1e,0xc0,0x00,0x03,0x00,0x1e,0xb0, + 0x00,0x01,0x09,0x00,0x1e,0xc4,0x00,0x03,0x00,0x1e,0xc0,0x00,0x01,0x09,0x00,0x1e, + 0xc8,0x00,0x03,0x00,0x1e,0xc4,0x00,0x01,0x09,0x00,0x1e,0xcc,0x00,0x03,0x00,0x1e, + 0xc8,0x00,0x01,0x09,0x00,0x1e,0xd0,0x00,0x03,0x00,0x1e,0xcc,0x00,0x01,0x09,0x00, + 0x1f,0x00,0x01,0x03,0x00,0x1e,0xd0,0x00,0x01,0x09,0x00,0x1f,0x04,0x00,0x03,0x00, + 0x1f,0x00,0x01,0x01,0x09,0x00,0x1f,0x08,0x00,0x03,0x00,0x1f,0x04,0x00,0x01,0x09, + 0x00,0x1f,0x0c,0x00,0x03,0x00,0x1f,0x08,0x00,0x01,0x09,0x00,0x1f,0x10,0x00,0x03, + 0x00,0x1f,0x0c,0x00,0x01,0x09,0x00,0x1f,0x20,0x00,0x03,0x00,0x1f,0x10,0x00,0x01, + 0x09,0x00,0x1f,0x24,0x00,0x03,0x00,0x1f,0x20,0x00,0x01,0x09,0x00,0x1f,0x28,0x00, + 0x03,0x00,0x1f,0x24,0x00,0x01,0x09,0x00,0x1f,0x2c,0x00,0x03,0x00,0x1f,0x28,0x00, + 0x01,0x09,0x00,0x1f,0x30,0x00,0x03,0x00,0x1f,0x2c,0x00,0x01,0x09,0x00,0x1f,0x40, + 0x00,0x03,0x00,0x1f,0x30,0x00,0x01,0x09,0x00,0x1f,0x44,0x00,0x03,0x00,0x1f,0x40, + 0x00,0x01,0x09,0x00,0x1f,0x48,0x00,0x03,0x00,0x1f,0x44,0x00,0x01,0x09,0x00,0x1f, + 0x4c,0x00,0x03,0x00,0x1f,0x48,0x00,0x01,0x09,0x00,0x1f,0x50,0x00,0x03,0x00,0x1f, + 0x4c,0x00,0x01,0x09,0x00,0x1f,0x83,0x02,0x03,0x00,0x1f,0x50,0x00,0x01,0x09,0x00, + 0x1f,0x84,0x00,0x03,0x00,0x1f,0x83,0x02,0x01,0x09,0x00,0x1f,0x88,0x00,0x03,0x00, + 0x1f,0x84,0x00,0x01,0x09,0x00,0x1f,0x8c,0x00,0x03,0x00,0x1f,0x88,0x00,0x01,0x09, + 0x00,0x1f,0x90,0x00,0x03,0x00,0x1f,0x8c,0x00,0x01,0x09,0x00,0x1f,0xa0,0x00,0x03, + 0x00,0x1f,0x90,0x00,0x01,0x09,0x00,0x1f,0xa4,0x00,0x03,0x00,0x1f,0xa0,0x00,0x01, + 0x09,0x00,0x1f,0xa8,0x00,0x03,0x00,0x1f,0xa4,0x00,0x01,0x09,0x00,0x1f,0xac,0x00, + 0x03,0x00,0x1f,0xa8,0x00,0x01,0x09,0x00,0x1f,0xb0,0x00,0x03,0x00,0x1f,0xac,0x00, + 0x01,0x09,0x00,0x1f,0xc0,0x00,0x03,0x00,0x1f,0xb0,0x00,0x01,0x09,0x00,0x1f,0xc4, + 0x00,0x03,0x00,0x1f,0xc0,0x00,0x01,0x09,0x00,0x1f,0xc8,0x00,0x03,0x00,0x1f,0xc4, + 0x00,0x01,0x09,0x00,0x1f,0xcc,0x00,0x03,0x00,0x1f,0xc8,0x00,0x01,0x09,0x00,0x1f, + 0xd0,0x00,0x03,0x00,0x1f,0xcc,0x00,0x01,0x09,0x00,0x20,0x03,0x03,0x03,0x00,0x1f, + 0xd0,0x00,0x01,0x09,0x00,0x20,0x04,0x00,0x03,0x00,0x20,0x03,0x03,0x01,0x09,0x00, + 0x20,0x08,0x00,0x03,0x00,0x20,0x04,0x00,0x01,0x09,0x00,0x20,0x0c,0x00,0x03,0x00, + 0x20,0x08,0x00,0x01,0x09,0x00,0x20,0x13,0x03,0x03,0x00,0x20,0x0c,0x00,0x01,0x09, + 0x00,0x20,0x20,0x00,0x03,0x00,0x20,0x13,0x03,0x01,0x09,0x00,0x20,0x24,0x00,0x03, + 0x00,0x20,0x20,0x00,0x01,0x09,0x00,0x20,0x28,0x00,0x03,0x00,0x20,0x24,0x00,0x01, + 0x09,0x00,0x20,0x2c,0x00,0x03,0x00,0x20,0x28,0x00,0x01,0x09,0x00,0x20,0x30,0x00, + 0x03,0x00,0x20,0x2c,0x00,0x01,0x09,0x00,0x20,0x40,0x00,0x03,0x00,0x20,0x30,0x00, + 0x01,0x09,0x00,0x20,0x44,0x00,0x03,0x00,0x20,0x40,0x00,0x01,0x09,0x00,0x20,0x48, + 0x00,0x03,0x00,0x20,0x44,0x00,0x01,0x09,0x00,0x20,0x4c,0x00,0x03,0x00,0x20,0x48, + 0x00,0x01,0x09,0x00,0x20,0x50,0x00,0x03,0x00,0x20,0x4c,0x00,0x01,0x09,0x00,0x20, + 0x80,0x00,0x03,0x00,0x20,0x50,0x00,0x01,0x09,0x00,0x20,0x85,0x00,0x03,0x00,0x20, + 0x80,0x00,0x01,0x09,0x00,0x20,0x88,0x00,0x03,0x00,0x20,0x85,0x00,0x01,0x09,0x00, + 0x20,0x8c,0x00,0x03,0x00,0x20,0x88,0x00,0x01,0x09,0x00,0x20,0x90,0x00,0x03,0x00, + 0x20,0x8c,0x00,0x01,0x09,0x00,0x20,0xa0,0x00,0x03,0x00,0x20,0x90,0x00,0x01,0x09, + 0x00,0x20,0xa4,0x00,0x03,0x00,0x20,0xa0,0x00,0x01,0x09,0x00,0x20,0xa8,0x00,0x03, + 0x00,0x20,0xa4,0x00,0x01,0x09,0x00,0x20,0xac,0x00,0x03,0x00,0x20,0xa8,0x00,0x01, + 0x09,0x00,0x20,0xb0,0x00,0x03,0x00,0x20,0xac,0x00,0x01,0x09,0x00,0x20,0xc0,0x00, + 0x03,0x00,0x20,0xb0,0x00,0x01,0x09,0x00,0x20,0xc4,0x00,0x03,0x00,0x20,0xc0,0x00, + 0x01,0x09,0x00,0x20,0xc8,0x00,0x03,0x00,0x20,0xc4,0x00,0x01,0x09,0x00,0x20,0xcc, + 0x00,0x03,0x00,0x20,0xc8,0x00,0x01,0x09,0x00,0x20,0xd0,0x00,0x03,0x00,0x20,0xcc, + 0x00,0x01,0x09,0x00,0x21,0x01,0x01,0x03,0x00,0x20,0xd0,0x00,0x01,0x09,0x00,0x21, + 0x04,0x00,0x03,0x00,0x21,0x01,0x01,0x01,0x09,0x00,0x21,0x08,0x00,0x03,0x00,0x21, + 0x04,0x00,0x01,0x09,0x00,0x21,0x0c,0x00,0x03,0x00,0x21,0x08,0x00,0x01,0x09,0x00, + 0x21,0x10,0x00,0x03,0x00,0x21,0x0c,0x00,0x01,0x09,0x00,0x21,0x20,0x00,0x03,0x00, + 0x21,0x10,0x00,0x01,0x09,0x00,0x21,0x24,0x00,0x03,0x00,0x21,0x20,0x00,0x01,0x09, + 0x00,0x21,0x28,0x00,0x03,0x00,0x21,0x24,0x00,0x01,0x09,0x00,0x21,0x2c,0x00,0x03, + 0x00,0x21,0x28,0x00,0x01,0x09,0x00,0x21,0x30,0x00,0x03,0x00,0x21,0x2c,0x00,0x01, + 0x09,0x00,0x21,0x40,0x00,0x03,0x00,0x21,0x30,0x00,0x01,0x09,0x00,0x21,0x44,0x00, + 0x03,0x00,0x21,0x40,0x00,0x01,0x09,0x00,0x21,0x48,0x00,0x03,0x00,0x21,0x44,0x00, + 0x01,0x09,0x00,0x21,0x4c,0x00,0x03,0x00,0x21,0x48,0x00,0x01,0x09,0x00,0x21,0x50, + 0x00,0x03,0x00,0x21,0x4c,0x00,0x01,0x09,0x00,0x21,0x81,0x01,0x03,0x00,0x21,0x50, + 0x00,0x01,0x09,0x00,0x21,0x84,0x00,0x03,0x00,0x21,0x81,0x01,0x01,0x09,0x00,0x21, + 0x88,0x00,0x03,0x00,0x21,0x84,0x00,0x01,0x09,0x00,0x21,0x8c,0x00,0x03,0x00,0x21, + 0x88,0x00,0x01,0x09,0x00,0x21,0x91,0x01,0x03,0x00,0x21,0x8c,0x00,0x01,0x09,0x00, + 0x21,0xa0,0x40,0x03,0x00,0x21,0x91,0x01,0x01,0x09,0x00,0x21,0xa4,0x00,0x03,0x00, + 0x21,0xa0,0x40,0x01,0x09,0x00,0x21,0xa8,0x00,0x03,0x00,0x21,0xa4,0x00,0x01,0x09, + 0x00,0x21,0xac,0x00,0x03,0x00,0x21,0xa8,0x00,0x01,0x09,0x00,0x21,0xb0,0x00,0x03, + 0x00,0x21,0xac,0x00,0x01,0x09,0x00,0x21,0xc0,0x00,0x03,0x00,0x21,0xb0,0x00,0x01, + 0x09,0x00,0x21,0xc4,0x00,0x03,0x00,0x21,0xc0,0x00,0x01,0x09,0x00,0x21,0xc8,0x00, + 0x03,0x00,0x21,0xc4,0x00,0x01,0x09,0x00,0x21,0xcc,0x00,0x03,0x00,0x21,0xc8,0x00, + 0x01,0x09,0x00,0x21,0xd0,0x00,0x03,0x00,0x21,0xcc,0x00,0x01,0x09,0x00,0x22,0x00, + 0x00,0x03,0x00,0x21,0xd0,0x00,0x01,0x09,0x00,0x22,0x04,0x00,0x03,0x00,0x22,0x00, + 0x00,0x01,0x09,0x00,0x22,0x08,0x00,0x03,0x00,0x22,0x04,0x00,0x01,0x09,0x00,0x22, + 0x0c,0x00,0x03,0x00,0x22,0x08,0x00,0x01,0x09,0x00,0x22,0x10,0x00,0x03,0x00,0x22, + 0x0c,0x00,0x01,0x09,0x00,0x22,0x20,0x00,0x03,0x00,0x22,0x10,0x00,0x01,0x09,0x00, + 0x22,0x24,0x00,0x03,0x00,0x22,0x20,0x00,0x01,0x09,0x00,0x22,0x28,0x00,0x03,0x00, + 0x22,0x24,0x00,0x01,0x09,0x00,0x22,0x2c,0x00,0x03,0x00,0x22,0x28,0x00,0x01,0x09, + 0x00,0x22,0x30,0x00,0x03,0x00,0x22,0x2c,0x00,0x01,0x09,0x00,0x22,0x40,0x00,0x03, + 0x00,0x22,0x30,0x00,0x01,0x09,0x00,0x22,0x44,0x00,0x03,0x00,0x22,0x40,0x00,0x01, + 0x09,0x00,0x22,0x48,0x00,0x03,0x00,0x22,0x44,0x00,0x01,0x09,0x00,0x22,0x4c,0x00, + 0x03,0x00,0x22,0x48,0x00,0x01,0x09,0x00,0x22,0x50,0x00,0x03,0x00,0x22,0x4c,0x00, + 0x01,0x09,0x00,0x22,0x80,0x00,0x03,0x00,0x22,0x50,0x00,0x01,0x09,0x00,0x22,0x84, + 0x00,0x03,0x00,0x22,0x80,0x00,0x01,0x09,0x00,0x22,0x88,0x00,0x03,0x00,0x22,0x84, + 0x00,0x01,0x09,0x00,0x22,0x8c,0x00,0x03,0x00,0x22,0x88,0x00,0x01,0x09,0x00,0x22, + 0x90,0x00,0x03,0x00,0x22,0x8c,0x00,0x01,0x09,0x00,0x22,0xa0,0x00,0x03,0x00,0x22, + 0x90,0x00,0x01,0x09,0x00,0x22,0xa4,0x00,0x03,0x00,0x22,0xa0,0x00,0x01,0x09,0x00, + 0x22,0xa8,0x00,0x03,0x00,0x22,0xa4,0x00,0x01,0x09,0x00,0x22,0xac,0x00,0x03,0x00, + 0x22,0xa8,0x00,0x01,0x09,0x00,0x22,0xb0,0x00,0x03,0x00,0x22,0xac,0x00,0x01,0x09, + 0x00,0x22,0xc0,0x00,0x03,0x00,0x22,0xb0,0x00,0x01,0x09,0x00,0x22,0xc4,0x00,0x03, + 0x00,0x22,0xc0,0x00,0x01,0x09,0x00,0x22,0xc8,0x00,0x03,0x00,0x22,0xc4,0x00,0x01, + 0x09,0x00,0x22,0xcc,0x00,0x03,0x00,0x22,0xc8,0x00,0x01,0x09,0x00,0x22,0xd0,0x00, + 0x03,0x00,0x22,0xcc,0x00,0x01,0x09,0x00,0x23,0x00,0x00,0x03,0x00,0x22,0xd0,0x00, + 0x01,0x09,0x00,0x23,0x04,0x00,0x03,0x00,0x23,0x00,0x00,0x01,0x09,0x00,0x23,0x08, + 0x00,0x03,0x00,0x23,0x04,0x00,0x01,0x09,0x00,0x23,0x0c,0x00,0x03,0x00,0x23,0x08, + 0x00,0x01,0x09,0x00,0x23,0x10,0x00,0x03,0x00,0x23,0x0c,0x00,0x01,0x09,0x00,0x23, + 0x20,0x00,0x03,0x00,0x23,0x10,0x00,0x01,0x09,0x00,0x23,0x24,0x00,0x03,0x00,0x23, + 0x20,0x00,0x01,0x09,0x00,0x23,0x28,0x00,0x03,0x00,0x23,0x24,0x00,0x01,0x09,0x00, + 0x23,0x2c,0x00,0x03,0x00,0x23,0x28,0x00,0x01,0x09,0x00,0x23,0x30,0x00,0x03,0x00, + 0x23,0x2c,0x00,0x01,0x09,0x00,0x23,0x40,0x00,0x03,0x00,0x23,0x30,0x00,0x01,0x09, + 0x00,0x23,0x44,0x00,0x03,0x00,0x23,0x40,0x00,0x01,0x09,0x00,0x23,0x48,0x00,0x03, + 0x00,0x23,0x44,0x00,0x01,0x09,0x00,0x23,0x4c,0x00,0x03,0x00,0x23,0x48,0x00,0x01, + 0x09,0x00,0x23,0x50,0x00,0x03,0x00,0x23,0x4c,0x00,0x01,0x09,0x00,0x23,0x81,0x01, + 0x03,0x00,0x23,0x50,0x00,0x01,0x09,0x00,0x23,0x84,0x00,0x03,0x00,0x23,0x81,0x01, + 0x01,0x09,0x00,0x23,0x88,0x00,0x03,0x00,0x23,0x84,0x00,0x01,0x09,0x00,0x23,0x8c, + 0x00,0x03,0x00,0x23,0x88,0x00,0x01,0x09,0x00,0x23,0x91,0x01,0x03,0x00,0x23,0x8c, + 0x00,0x01,0x09,0x00,0x23,0xa0,0x00,0x03,0x00,0x23,0x91,0x01,0x01,0x09,0x00,0x23, + 0xa4,0x00,0x03,0x00,0x23,0xa0,0x00,0x01,0x09,0x00,0x23,0xa8,0x00,0x03,0x00,0x23, + 0xa4,0x00,0x01,0x09,0x00,0x23,0xac,0x00,0x03,0x00,0x23,0xa8,0x00,0x01,0x09,0x00, + 0x23,0xb0,0x00,0x03,0x00,0x23,0xac,0x00,0x01,0x09,0x00,0x23,0xc0,0x00,0x03,0x00, + 0x23,0xb0,0x00,0x01,0x09,0x00,0x23,0xc4,0x00,0x03,0x00,0x23,0xc0,0x00,0x01,0x09, + 0x00,0x23,0xc8,0x00,0x03,0x00,0x23,0xc4,0x00,0x01,0x09,0x00,0x23,0xcc,0x00,0x03, + 0x00,0x23,0xc8,0x00,0x01,0x09,0x00,0x23,0xd0,0x00,0x03,0x00,0x23,0xcc,0x00,0x01, + 0x09,0x00,0x24,0x01,0x01,0x03,0x00,0x23,0xd0,0x00,0x01,0x09,0x00,0x24,0x06,0x00, + 0x03,0x00,0x24,0x01,0x01,0x01,0x09,0x00,0x24,0x08,0x00,0x03,0x00,0x24,0x06,0x00, + 0x01,0x09,0x00,0x24,0x0c,0x00,0x03,0x00,0x24,0x08,0x00,0x01,0x09,0x00,0x24,0x10, + 0x00,0x03,0x00,0x24,0x0c,0x00,0x01,0x09,0x00,0x24,0x20,0x00,0x03,0x00,0x24,0x10, + 0x00,0x01,0x09,0x00,0x24,0x24,0x00,0x03,0x00,0x24,0x20,0x00,0x01,0x09,0x00,0x24, + 0x28,0x00,0x03,0x00,0x24,0x24,0x00,0x01,0x09,0x00,0x24,0x2c,0x00,0x03,0x00,0x24, + 0x28,0x00,0x01,0x09,0x00,0x24,0x30,0x00,0x03,0x00,0x24,0x2c,0x00,0x01,0x09,0x00, + 0x24,0x40,0x00,0x03,0x00,0x24,0x30,0x00,0x01,0x09,0x00,0x24,0x44,0x00,0x03,0x00, + 0x24,0x40,0x00,0x01,0x09,0x00,0x24,0x48,0x00,0x03,0x00,0x24,0x44,0x00,0x01,0x09, + 0x00,0x24,0x4c,0x00,0x03,0x00,0x24,0x48,0x00,0x01,0x09,0x00,0x24,0x50,0x00,0x03, + 0x00,0x24,0x4c,0x00,0x01,0x09,0x00,0x24,0x80,0x22,0x03,0x00,0x24,0x50,0x00,0x01, + 0x09,0x00,0x24,0x85,0x00,0x03,0x00,0x24,0x80,0x22,0x01,0x09,0x00,0x24,0x88,0x00, + 0x03,0x00,0x24,0x85,0x00,0x01,0x09,0x00,0x24,0x8c,0x00,0x03,0x00,0x24,0x88,0x00, + 0x01,0x09,0x00,0x24,0x90,0x00,0x03,0x00,0x24,0x8c,0x00,0x01,0x09,0x00,0x24,0xa0, + 0x00,0x03,0x00,0x24,0x90,0x00,0x01,0x09,0x00,0x24,0xa4,0x00,0x03,0x00,0x24,0xa0, + 0x00,0x01,0x09,0x00,0x24,0xa8,0x00,0x03,0x00,0x24,0xa4,0x00,0x01,0x09,0x00,0x24, + 0xac,0x00,0x03,0x00,0x24,0xa8,0x00,0x01,0x09,0x00,0x24,0xb0,0x00,0x03,0x00,0x24, + 0xac,0x00,0x01,0x09,0x00,0x24,0xc0,0x00,0x03,0x00,0x24,0xb0,0x00,0x01,0x09,0x00, + 0x24,0xc4,0x00,0x03,0x00,0x24,0xc0,0x00,0x01,0x09,0x00,0x24,0xc8,0x00,0x03,0x00, + 0x24,0xc4,0x00,0x01,0x09,0x00,0x24,0xcc,0x00,0x03,0x00,0x24,0xc8,0x00,0x01,0x09, + 0x00,0x24,0xd0,0x00,0x03,0x00,0x24,0xcc,0x00,0x01,0x09,0x00,0x25,0x00,0x00,0x03, + 0x00,0x24,0xd0,0x00,0x01,0x09,0x00,0x25,0x04,0x00,0x03,0x00,0x25,0x00,0x00,0x01, + 0x09,0x00,0x25,0x08,0x00,0x03,0x00,0x25,0x04,0x00,0x01,0x09,0x00,0x25,0x0c,0x00, + 0x03,0x00,0x25,0x08,0x00,0x01,0x09,0x00,0x25,0x10,0x00,0x03,0x00,0x25,0x0c,0x00, + 0x01,0x09,0x00,0x25,0x20,0x00,0x03,0x00,0x25,0x10,0x00,0x01,0x09,0x00,0x25,0x24, + 0x00,0x03,0x00,0x25,0x20,0x00,0x01,0x09,0x00,0x25,0x28,0x00,0x03,0x00,0x25,0x24, + 0x00,0x01,0x09,0x00,0x25,0x2c,0x00,0x03,0x00,0x25,0x28,0x00,0x01,0x09,0x00,0x25, + 0x30,0x00,0x03,0x00,0x25,0x2c,0x00,0x01,0x09,0x00,0x25,0x40,0x00,0x03,0x00,0x25, + 0x30,0x00,0x01,0x09,0x00,0x25,0x44,0x00,0x03,0x00,0x25,0x40,0x00,0x01,0x09,0x00, + 0x25,0x48,0x00,0x03,0x00,0x25,0x44,0x00,0x01,0x09,0x00,0x25,0x4c,0x00,0x03,0x00, + 0x25,0x48,0x00,0x01,0x09,0x00,0x25,0x50,0x00,0x03,0x00,0x25,0x4c,0x00,0x01,0x09, + 0x00,0x25,0x80,0x00,0x03,0x00,0x25,0x50,0x00,0x01,0x09,0x00,0x25,0x84,0x00,0x03, + 0x00,0x25,0x80,0x00,0x01,0x09,0x00,0x25,0x88,0x00,0x03,0x00,0x25,0x84,0x00,0x01, + 0x09,0x00,0x25,0x8c,0x00,0x03,0x00,0x25,0x88,0x00,0x01,0x09,0x00,0x25,0x90,0x00, + 0x03,0x00,0x25,0x8c,0x00,0x01,0x09,0x00,0x25,0xa0,0x00,0x03,0x00,0x25,0x90,0x00, + 0x01,0x09,0x00,0x25,0xa4,0x00,0x03,0x00,0x25,0xa0,0x00,0x01,0x09,0x00,0x25,0xa8, + 0x00,0x03,0x00,0x25,0xa4,0x00,0x01,0x09,0x00,0x25,0xac,0x00,0x03,0x00,0x25,0xa8, + 0x00,0x01,0x09,0x00,0x25,0xb0,0x00,0x03,0x00,0x25,0xac,0x00,0x01,0x09,0x00,0x25, + 0xc0,0x00,0x03,0x00,0x25,0xb0,0x00,0x01,0x09,0x00,0x25,0xc4,0x00,0x03,0x00,0x25, + 0xc0,0x00,0x01,0x09,0x00,0x25,0xc8,0x00,0x03,0x00,0x25,0xc4,0x00,0x01,0x09,0x00, + 0x25,0xcc,0x00,0x03,0x00,0x25,0xc8,0x00,0x01,0x09,0x00,0x25,0xd0,0x00,0x03,0x00, + 0x25,0xcc,0x00,0x01,0x09,0x00,0x26,0x00,0x00,0x03,0x00,0x25,0xd0,0x00,0x01,0x09, + 0x00,0x26,0x05,0x01,0x03,0x00,0x26,0x00,0x00,0x01,0x09,0x00,0x26,0x08,0x00,0x03, + 0x00,0x26,0x05,0x01,0x01,0x09,0x00,0x26,0x0c,0x00,0x03,0x00,0x26,0x08,0x00,0x01, + 0x09,0x00,0x26,0x10,0x00,0x03,0x00,0x26,0x0c,0x00,0x01,0x09,0x00,0x26,0x20,0x00, + 0x03,0x00,0x26,0x10,0x00,0x01,0x09,0x00,0x26,0x24,0x00,0x03,0x00,0x26,0x20,0x00, + 0x01,0x09,0x00,0x26,0x28,0x00,0x03,0x00,0x26,0x24,0x00,0x01,0x09,0x00,0x26,0x2c, + 0x00,0x03,0x00,0x26,0x28,0x00,0x01,0x09,0x00,0x26,0x30,0x00,0x03,0x00,0x26,0x2c, + 0x00,0x01,0x09,0x00,0x26,0x40,0x00,0x03,0x00,0x26,0x30,0x00,0x01,0x09,0x00,0x26, + 0x44,0x00,0x03,0x00,0x26,0x40,0x00,0x01,0x09,0x00,0x26,0x48,0x00,0x03,0x00,0x26, + 0x44,0x00,0x01,0x09,0x00,0x26,0x4c,0x00,0x03,0x00,0x26,0x48,0x00,0x01,0x09,0x00, + 0x26,0x50,0x00,0x03,0x00,0x26,0x4c,0x00,0x01,0x09,0x00,0x26,0x80,0x00,0x03,0x00, + 0x26,0x50,0x00,0x01,0x09,0x00,0x26,0x84,0x00,0x03,0x00,0x26,0x80,0x00,0x01,0x09, + 0x00,0x26,0x88,0x00,0x03,0x00,0x26,0x84,0x00,0x01,0x09,0x00,0x26,0x8c,0x00,0x03, + 0x00,0x26,0x88,0x00,0x01,0x09,0x00,0x26,0x90,0x00,0x03,0x00,0x26,0x8c,0x00,0x01, + 0x09,0x00,0x26,0xa0,0x00,0x03,0x00,0x26,0x90,0x00,0x01,0x09,0x00,0x26,0xa4,0x00, + 0x03,0x00,0x26,0xa0,0x00,0x01,0x09,0x00,0x26,0xa8,0x00,0x03,0x00,0x26,0xa4,0x00, + 0x01,0x09,0x00,0x26,0xac,0x00,0x03,0x00,0x26,0xa8,0x00,0x01,0x09,0x00,0x26,0xb0, + 0x00,0x03,0x00,0x26,0xac,0x00,0x01,0x09,0x00,0x26,0xc0,0x00,0x03,0x00,0x26,0xb0, + 0x00,0x01,0x09,0x00,0x26,0xc4,0x00,0x03,0x00,0x26,0xc0,0x00,0x01,0x09,0x00,0x26, + 0xc8,0x00,0x03,0x00,0x26,0xc4,0x00,0x01,0x09,0x00,0x26,0xcc,0x00,0x03,0x00,0x26, + 0xc8,0x00,0x01,0x09,0x00,0x26,0xd0,0x00,0x03,0x00,0x26,0xcc,0x00,0x01,0x09,0x00, + 0x27,0x01,0x01,0x03,0x00,0x26,0xd0,0x00,0x01,0x09,0x00,0x27,0x04,0x00,0x03,0x00, + 0x27,0x01,0x01,0x01,0x09,0x00,0x27,0x08,0x00,0x03,0x00,0x27,0x04,0x00,0x01,0x09, + 0x00,0x27,0x0c,0x00,0x03,0x00,0x27,0x08,0x00,0x01,0x09,0x00,0x27,0x10,0x00,0x03, + 0x00,0x27,0x0c,0x00,0x01,0x09,0x00,0x27,0x20,0x00,0x03,0x00,0x27,0x10,0x00,0x01, + 0x09,0x00,0x27,0x25,0x01,0x03,0x00,0x27,0x20,0x00,0x01,0x09,0x00,0x27,0x28,0x00, + 0x03,0x00,0x27,0x25,0x01,0x01,0x09,0x00,0x27,0x2c,0x00,0x03,0x00,0x27,0x28,0x00, + 0x01,0x09,0x00,0x27,0x30,0x00,0x03,0x00,0x27,0x2c,0x00,0x01,0x09,0x00,0x27,0x40, + 0x00,0x03,0x00,0x27,0x30,0x00,0x01,0x09,0x00,0x27,0x44,0x00,0x03,0x00,0x27,0x40, + 0x00,0x01,0x09,0x00,0x27,0x48,0x00,0x03,0x00,0x27,0x44,0x00,0x01,0x09,0x00,0x27, + 0x4c,0x00,0x03,0x00,0x27,0x48,0x00,0x01,0x09,0x00,0x27,0x50,0x00,0x03,0x00,0x27, + 0x4c,0x00,0x01,0x09,0x00,0x27,0x80,0x00,0x03,0x00,0x27,0x50,0x00,0x01,0x09,0x00, + 0x27,0x84,0x00,0x03,0x00,0x27,0x80,0x00,0x01,0x09,0x00,0x27,0x88,0x00,0x03,0x00, + 0x27,0x84,0x00,0x01,0x09,0x00,0x27,0x8c,0x00,0x03,0x00,0x27,0x88,0x00,0x01,0x09, + 0x00,0x27,0x90,0x00,0x03,0x00,0x27,0x8c,0x00,0x01,0x09,0x00,0x27,0xa0,0x00,0x03, + 0x00,0x27,0x90,0x00,0x01,0x09,0x00,0x27,0xa4,0x00,0x03,0x00,0x27,0xa0,0x00,0x01, + 0x09,0x00,0x27,0xa8,0x00,0x03,0x00,0x27,0xa4,0x00,0x01,0x09,0x00,0x27,0xac,0x00, + 0x03,0x00,0x27,0xa8,0x00,0x01,0x09,0x00,0x27,0xb0,0x00,0x03,0x00,0x27,0xac,0x00, + 0x01,0x09,0x00,0x27,0xc0,0x00,0x03,0x00,0x27,0xb0,0x00,0x01,0x09,0x00,0x27,0xc4, + 0x00,0x03,0x00,0x27,0xc0,0x00,0x01,0x09,0x00,0x27,0xc8,0x00,0x03,0x00,0x27,0xc4, + 0x00,0x01,0x09,0x00,0x27,0xcc,0x00,0x03,0x00,0x27,0xc8,0x00,0x01,0x09,0x00,0x27, + 0xd0,0x00,0x03,0x00,0x27,0xcc,0x00,0x01,0x09,0x00,0x28,0x00,0x00,0x03,0x00,0x27, + 0xd0,0x00,0x01,0x09,0x00,0x28,0x04,0x00,0x03,0x00,0x28,0x00,0x00,0x01,0x09,0x00, + 0x28,0x08,0x00,0x03,0x00,0x28,0x04,0x00,0x01,0x09,0x00,0x28,0x0c,0x00,0x03,0x00, + 0x28,0x08,0x00,0x01,0x09,0x00,0x28,0x10,0x00,0x03,0x00,0x28,0x0c,0x00,0x01,0x09, + 0x00,0x28,0x20,0x00,0x13,0x00,0x28,0x10,0x00,0x01,0x09,0x00,0x28,0x24,0x00,0x13, + 0x00,0x28,0x20,0x00,0x11,0x09,0x00,0x28,0x28,0x00,0x13,0x00,0x28,0x24,0x00,0x11, + 0x09,0x00,0x28,0x2c,0x00,0x13,0x00,0x28,0x28,0x00,0x11,0x09,0x00,0x28,0x30,0x00, + 0x13,0x00,0x28,0x2c,0x00,0x11,0x09,0x00,0x28,0x40,0x00,0x03,0x00,0x28,0x30,0x00, + 0x11,0x09,0x00,0x28,0x44,0x00,0x03,0x00,0x28,0x40,0x00,0x01,0x09,0x00,0x28,0x48, + 0x00,0x03,0x00,0x28,0x44,0x00,0x01,0x09,0x00,0x28,0x4c,0x00,0x03,0x00,0x28,0x48, + 0x00,0x01,0x09,0x00,0x28,0x50,0x00,0x03,0x00,0x28,0x4c,0x00,0x01,0x09,0x00,0x28, + 0x80,0x80,0x03,0x00,0x28,0x50,0x00,0x01,0x09,0x00,0x28,0x84,0x80,0x03,0x00,0x28, + 0x80,0x80,0x01,0x09,0x00,0x28,0x88,0x80,0x03,0x00,0x28,0x84,0x80,0x01,0x09,0x00, + 0x28,0x8c,0x80,0x03,0x00,0x28,0x88,0x80,0x01,0x09,0x00,0x28,0x90,0x80,0x03,0x00, + 0x28,0x8c,0x80,0x01,0x09,0x00,0x28,0xa0,0x00,0x03,0x00,0x28,0x90,0x80,0x01,0x09, + 0x00,0x28,0xa4,0x00,0x03,0x00,0x28,0xa0,0x00,0x01,0x09,0x00,0x28,0xa8,0x00,0x03, + 0x00,0x28,0xa4,0x00,0x01,0x09,0x00,0x28,0xac,0x00,0x03,0x00,0x28,0xa8,0x00,0x01, + 0x09,0x00,0x28,0xb0,0x00,0x03,0x00,0x28,0xac,0x00,0x01,0x09,0x00,0x28,0xc0,0x00, + 0x13,0x00,0x28,0xb0,0x00,0x01,0x09,0x00,0x28,0xc4,0x00,0x13,0x00,0x28,0xc0,0x00, + 0x11,0x09,0x00,0x28,0xc8,0x00,0x13,0x00,0x28,0xc4,0x00,0x11,0x09,0x00,0x28,0xcc, + 0x00,0x13,0x00,0x28,0xc8,0x00,0x11,0x09,0x00,0x28,0xd0,0x00,0x13,0x00,0x28,0xcc, + 0x00,0x11,0x09,0x00,0x29,0x00,0x00,0x03,0x00,0x28,0xd0,0x00,0x11,0x09,0x00,0x29, + 0x04,0x00,0x03,0x00,0x29,0x00,0x00,0x01,0x09,0x00,0x29,0x08,0x00,0x03,0x00,0x29, + 0x04,0x00,0x01,0x09,0x00,0x29,0x0c,0x00,0x03,0x00,0x29,0x08,0x00,0x01,0x09,0x00, + 0x29,0x10,0x00,0x03,0x00,0x29,0x0c,0x00,0x01,0x09,0x00,0x29,0x20,0x00,0x03,0x00, + 0x29,0x10,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x03,0x00,0x29,0x20,0x00,0x01,0x09, + 0x00,0x29,0x28,0x00,0x03,0x00,0x29,0x24,0x00,0x01,0x09,0x00,0x29,0x2c,0x00,0x03, + 0x00,0x29,0x28,0x00,0x01,0x09,0x00,0x29,0x30,0x00,0x03,0x00,0x29,0x2c,0x00,0x01, + 0x09,0x00,0x29,0x40,0x00,0x03,0x00,0x29,0x30,0x00,0x01,0x09,0x00,0x29,0x44,0x00, + 0x03,0x00,0x29,0x40,0x00,0x01,0x09,0x00,0x29,0x48,0x00,0x03,0x00,0x29,0x44,0x00, + 0x01,0x09,0x00,0x29,0x4c,0x00,0x03,0x00,0x29,0x48,0x00,0x01,0x09,0x00,0x29,0x50, + 0x00,0x03,0x00,0x29,0x4c,0x00,0x01,0x09,0x00,0x29,0x80,0x00,0x03,0x00,0x29,0x50, + 0x00,0x01,0x09,0x00,0x29,0x84,0x00,0xc3,0x00,0x29,0x80,0x00,0x01,0x09,0x00,0x29, + 0x88,0x00,0x03,0x00,0x29,0x84,0x00,0xc1,0x09,0x00,0x29,0x8c,0x00,0x03,0x00,0x29, + 0x88,0x00,0x01,0x09,0x00,0x29,0x90,0x00,0x03,0x00,0x29,0x8c,0x00,0x01,0x09,0x00, + 0x29,0xa0,0x00,0x03,0x00,0x29,0x90,0x00,0x01,0x09,0x00,0x29,0xa4,0x80,0xe3,0x00, + 0x29,0xa0,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x03,0x00,0x29,0xa4,0x80,0xe1,0x09, + 0x00,0x29,0xac,0x00,0x03,0x00,0x29,0xa8,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,0x03, + 0x00,0x29,0xac,0x00,0x01,0x09,0x00,0x29,0xc0,0x00,0x03,0x00,0x29,0xb0,0x00,0x01, + 0x09,0x00,0x29,0xc4,0x00,0x63,0x00,0x29,0xc0,0x00,0x01,0x09,0x00,0x29,0xc8,0x00, + 0x03,0x00,0x29,0xc4,0x00,0x61,0x09,0x00,0x29,0xcc,0x00,0x03,0x00,0x29,0xc8,0x00, + 0x01,0x09,0x00,0x29,0xd0,0x00,0x03,0x00,0x29,0xcc,0x00,0x01,0x09,0x00,0x2a,0x00, + 0x00,0x03,0x00,0x29,0xd0,0x00,0x01,0x09,0x00,0x2a,0x04,0x00,0x03,0x00,0x2a,0x00, + 0x00,0x01,0x09,0x00,0x2a,0x08,0x00,0x03,0x00,0x2a,0x04,0x00,0x01,0x09,0x00,0x2a, + 0x0c,0x00,0x03,0x00,0x2a,0x08,0x00,0x01,0x09,0x00,0x2a,0x10,0x00,0x03,0x00,0x2a, + 0x0c,0x00,0x01,0x09,0x00,0x2a,0x20,0x00,0x03,0x00,0x2a,0x10,0x00,0x01,0x09,0x00, + 0x2a,0x24,0x00,0x03,0x00,0x2a,0x20,0x00,0x01,0x09,0x00,0x2a,0x28,0x00,0x03,0x00, + 0x2a,0x24,0x00,0x01,0x09,0x00,0x2a,0x2c,0x00,0x03,0x00,0x2a,0x28,0x00,0x01,0x09, + 0x00,0x2a,0x30,0x00,0x03,0x00,0x2a,0x2c,0x00,0x01,0x09,0x00,0x2a,0x40,0x00,0x03, + 0x00,0x2a,0x30,0x00,0x01,0x09,0x00,0x2a,0x44,0x00,0x03,0x00,0x2a,0x40,0x00,0x01, + 0x09,0x00,0x2a,0x48,0x00,0x03,0x00,0x2a,0x44,0x00,0x01,0x09,0x00,0x2a,0x4c,0x00, + 0x03,0x00,0x2a,0x48,0x00,0x01,0x09,0x00,0x2a,0x50,0x00,0x03,0x00,0x2a,0x4c,0x00, + 0x01,0x09,0x00,0x2a,0x80,0x00,0x03,0x00,0x2a,0x50,0x00,0x01,0x09,0x00,0x2a,0x84, + 0x00,0x03,0x00,0x2a,0x80,0x00,0x01,0x09,0x00,0x2a,0x88,0x00,0x03,0x00,0x2a,0x84, + 0x00,0x01,0x09,0x00,0x2a,0x8c,0x00,0x03,0x00,0x2a,0x88,0x00,0x01,0x09,0x00,0x2a, + 0x90,0x00,0x03,0x00,0x2a,0x8c,0x00,0x01,0x09,0x00,0x2a,0xa0,0x00,0x03,0x00,0x2a, + 0x90,0x00,0x01,0x09,0x00,0x2a,0xa4,0x00,0x03,0x00,0x2a,0xa0,0x00,0x01,0x09,0x00, + 0x2a,0xa8,0x00,0x03,0x00,0x2a,0xa4,0x00,0x01,0x09,0x00,0x2a,0xac,0x00,0x03,0x00, + 0x2a,0xa8,0x00,0x01,0x09,0x00,0x2a,0xb0,0x00,0x03,0x00,0x2a,0xac,0x00,0x01,0x09, + 0x00,0x2a,0xc0,0x00,0x03,0x00,0x2a,0xb0,0x00,0x01,0x09,0x00,0x2a,0xc4,0x00,0x03, + 0x00,0x2a,0xc0,0x00,0x01,0x09,0x00,0x2a,0xc8,0x00,0x03,0x00,0x2a,0xc4,0x00,0x01, + 0x09,0x00,0x2a,0xcc,0x00,0x03,0x00,0x2a,0xc8,0x00,0x01,0x09,0x00,0x2a,0xd0,0x00, + 0x03,0x00,0x2a,0xcc,0x00,0x01,0x09,0x00,0x2b,0x00,0x00,0x03,0x00,0x2a,0xd0,0x00, + 0x01,0x09,0x00,0x2b,0x04,0x00,0x03,0x00,0x2b,0x00,0x00,0x01,0x09,0x00,0x2b,0x08, + 0x00,0x03,0x00,0x2b,0x04,0x00,0x01,0x09,0x00,0x2b,0x0c,0x00,0x03,0x00,0x2b,0x08, + 0x00,0x01,0x09,0x00,0x2b,0x10,0x00,0x03,0x00,0x2b,0x0c,0x00,0x01,0x09,0x00,0x2b, + 0x20,0x00,0x03,0x00,0x2b,0x10,0x00,0x01,0x09,0x00,0x2b,0x24,0x00,0x03,0x00,0x2b, + 0x20,0x00,0x01,0x09,0x00,0x2b,0x28,0x00,0x03,0x00,0x2b,0x24,0x00,0x01,0x09,0x00, + 0x2b,0x2c,0x00,0x03,0x00,0x2b,0x28,0x00,0x01,0x09,0x00,0x2b,0x30,0x00,0x03,0x00, + 0x2b,0x2c,0x00,0x01,0x09,0x00,0x2b,0x40,0x00,0x03,0x00,0x2b,0x30,0x00,0x01,0x09, + 0x00,0x2b,0x44,0x00,0x03,0x00,0x2b,0x40,0x00,0x01,0x09,0x00,0x2b,0x48,0x00,0x03, + 0x00,0x2b,0x44,0x00,0x01,0x09,0x00,0x2b,0x4c,0x00,0x03,0x00,0x2b,0x48,0x00,0x01, + 0x09,0x00,0x2b,0x50,0x00,0x03,0x00,0x2b,0x4c,0x00,0x01,0x09,0x00,0x2b,0x80,0x00, + 0x03,0x00,0x2b,0x50,0x00,0x01,0x09,0x00,0x2b,0x84,0x00,0x03,0x00,0x2b,0x80,0x00, + 0x01,0x09,0x00,0x2b,0x88,0x00,0x03,0x00,0x2b,0x84,0x00,0x01,0x09,0x00,0x2b,0x8c, + 0x00,0x03,0x00,0x2b,0x88,0x00,0x01,0x09,0x00,0x2b,0x90,0x00,0x03,0x00,0x2b,0x8c, + 0x00,0x01,0x09,0x00,0x2b,0xa0,0x00,0x03,0x00,0x2b,0x90,0x00,0x01,0x09,0x00,0x2b, + 0xa4,0x00,0x03,0x00,0x2b,0xa0,0x00,0x01,0x09,0x00,0x2b,0xa8,0x00,0x03,0x00,0x2b, + 0xa4,0x00,0x01,0x09,0x00,0x2b,0xac,0x00,0x03,0x00,0x2b,0xa8,0x00,0x01,0x09,0x00, + 0x2b,0xb0,0x00,0x03,0x00,0x2b,0xac,0x00,0x01,0x09,0x00,0x2b,0xc0,0x00,0x03,0x00, + 0x2b,0xb0,0x00,0x01,0x09,0x00,0x2b,0xc4,0x00,0x03,0x00,0x2b,0xc0,0x00,0x01,0x09, + 0x00,0x2b,0xc8,0x00,0x03,0x00,0x2b,0xc4,0x00,0x01,0x09,0x00,0x2b,0xcc,0x00,0x03, + 0x00,0x2b,0xc8,0x00,0x01,0x09,0x00,0x2b,0xd0,0x00,0x03,0x00,0x2b,0xcc,0x00,0x01, + 0x09,0x00,0x2c,0x00,0x00,0x03,0x00,0x2b,0xd0,0x00,0x01,0x09,0x00,0x2c,0x04,0x00, + 0x03,0x00,0x2c,0x00,0x00,0x01,0x09,0x00,0x2c,0x08,0x00,0x03,0x00,0x2c,0x04,0x00, + 0x01,0x09,0x00,0x2c,0x0c,0x00,0x03,0x00,0x2c,0x08,0x00,0x01,0x09,0x00,0x2c,0x10, + 0x00,0x03,0x00,0x2c,0x0c,0x00,0x01,0x09,0x00,0x2c,0x20,0x00,0x03,0x00,0x2c,0x10, + 0x00,0x01,0x09,0x00,0x2c,0x24,0x00,0x03,0x00,0x2c,0x20,0x00,0x01,0x09,0x00,0x2c, + 0x28,0x00,0x03,0x00,0x2c,0x24,0x00,0x01,0x09,0x00,0x2c,0x2c,0x00,0x03,0x00,0x2c, + 0x28,0x00,0x01,0x09,0x00,0x2c,0x30,0x00,0x03,0x00,0x2c,0x2c,0x00,0x01,0x09,0x00, + 0x2c,0x40,0x00,0x03,0x00,0x2c,0x30,0x00,0x01,0x09,0x00,0x2c,0x44,0x00,0x03,0x00, + 0x2c,0x40,0x00,0x01,0x09,0x00,0x2c,0x48,0x00,0x03,0x00,0x2c,0x44,0x00,0x01,0x09, + 0x00,0x2c,0x4c,0x00,0x03,0x00,0x2c,0x48,0x00,0x01,0x09,0x00,0x2c,0x50,0x00,0x03, + 0x00,0x2c,0x4c,0x00,0x01,0x09,0x00,0x2c,0x80,0x00,0x03,0x00,0x2c,0x50,0x00,0x01, + 0x09,0x00,0x2c,0x84,0x00,0x03,0x00,0x2c,0x80,0x00,0x01,0x09,0x00,0x2c,0x88,0x00, + 0x03,0x00,0x2c,0x84,0x00,0x01,0x09,0x00,0x2c,0x8c,0x00,0x03,0x00,0x2c,0x88,0x00, + 0x01,0x09,0x00,0x2c,0x90,0x00,0x03,0x00,0x2c,0x8c,0x00,0x01,0x09,0x00,0x2c,0xa0, + 0x00,0x03,0x00,0x2c,0x90,0x00,0x01,0x09,0x00,0x2c,0xa4,0x00,0x03,0x00,0x2c,0xa0, + 0x00,0x01,0x09,0x00,0x2c,0xa8,0x00,0x03,0x00,0x2c,0xa4,0x00,0x01,0x09,0x00,0x2c, + 0xac,0x00,0x03,0x00,0x2c,0xa8,0x00,0x01,0x09,0x00,0x2c,0xb0,0x00,0x03,0x00,0x2c, + 0xac,0x00,0x01,0x09,0x00,0x2c,0xc0,0x00,0x03,0x00,0x2c,0xb0,0x00,0x01,0x09,0x00, + 0x2c,0xc4,0x00,0x03,0x00,0x2c,0xc0,0x00,0x01,0x09,0x00,0x2c,0xc8,0x00,0x03,0x00, + 0x2c,0xc4,0x00,0x01,0x09,0x00,0x2c,0xcc,0x00,0x03,0x00,0x2c,0xc8,0x00,0x01,0x09, + 0x00,0x2c,0xd0,0x00,0x03,0x00,0x2c,0xcc,0x00,0x01,0x09,0x00,0x2d,0x00,0x00,0x03, + 0x00,0x2c,0xd0,0x00,0x01,0x09,0x00,0x2d,0x04,0x00,0x03,0x00,0x2d,0x00,0x00,0x01, + 0x09,0x00,0x2d,0x08,0x00,0x03,0x00,0x2d,0x04,0x00,0x01,0x09,0x00,0x2d,0x0c,0x00, + 0x03,0x00,0x2d,0x08,0x00,0x01,0x09,0x00,0x2d,0x10,0x00,0x03,0x00,0x2d,0x0c,0x00, + 0x01,0x09,0x00,0x2d,0x20,0x00,0x03,0x00,0x2d,0x10,0x00,0x01,0x09,0x00,0x2d,0x24, + 0x00,0x03,0x00,0x2d,0x20,0x00,0x01,0x09,0x00,0x2d,0x28,0x00,0x03,0x00,0x2d,0x24, + 0x00,0x01,0x09,0x00,0x2d,0x2c,0x00,0x03,0x00,0x2d,0x28,0x00,0x01,0x09,0x00,0x2d, + 0x30,0x00,0x03,0x00,0x2d,0x2c,0x00,0x01,0x09,0x00,0x2d,0x40,0x00,0x03,0x00,0x2d, + 0x30,0x00,0x01,0x09,0x00,0x2d,0x44,0x00,0x03,0x00,0x2d,0x40,0x00,0x01,0x09,0x00, + 0x2d,0x48,0x00,0x03,0x00,0x2d,0x44,0x00,0x01,0x09,0x00,0x2d,0x4c,0x00,0x03,0x00, + 0x2d,0x48,0x00,0x01,0x09,0x00,0x2d,0x50,0x00,0x03,0x00,0x2d,0x4c,0x00,0x01,0x09, + 0x00,0x2d,0x80,0x00,0x03,0x00,0x2d,0x50,0x00,0x01,0x09,0x00,0x2d,0x84,0x00,0x03, + 0x00,0x2d,0x80,0x00,0x01,0x09,0x00,0x2d,0x88,0x00,0x03,0x00,0x2d,0x84,0x00,0x01, + 0x09,0x00,0x2d,0x8c,0x00,0x03,0x00,0x2d,0x88,0x00,0x01,0x09,0x00,0x2d,0x90,0x00, + 0x03,0x00,0x2d,0x8c,0x00,0x01,0x09,0x00,0x2d,0xa0,0x00,0x03,0x00,0x2d,0x90,0x00, + 0x01,0x09,0x00,0x2d,0xa4,0x00,0x03,0x00,0x2d,0xa0,0x00,0x01,0x09,0x00,0x2d,0xa8, + 0x00,0x03,0x00,0x2d,0xa4,0x00,0x01,0x09,0x00,0x2d,0xac,0x00,0x03,0x00,0x2d,0xa8, + 0x00,0x01,0x09,0x00,0x2d,0xb0,0x00,0x03,0x00,0x2d,0xac,0x00,0x01,0x09,0x00,0x2d, + 0xc0,0x00,0x03,0x00,0x2d,0xb0,0x00,0x01,0x09,0x00,0x2d,0xc4,0x00,0x03,0x00,0x2d, + 0xc0,0x00,0x01,0x09,0x00,0x2d,0xc8,0x00,0x03,0x00,0x2d,0xc4,0x00,0x01,0x09,0x00, + 0x2d,0xcc,0x00,0x03,0x00,0x2d,0xc8,0x00,0x01,0x09,0x00,0x2d,0xd0,0x00,0x03,0x00, + 0x2d,0xcc,0x00,0x01,0x09,0x00,0x2e,0x00,0x00,0x03,0x00,0x2d,0xd0,0x00,0x01,0x09, + 0x00,0x2e,0x04,0x00,0x03,0x00,0x2e,0x00,0x00,0x01,0x09,0x00,0x2e,0x08,0x00,0x03, + 0x00,0x2e,0x04,0x00,0x01,0x09,0x00,0x2e,0x0c,0x00,0x03,0x00,0x2e,0x08,0x00,0x01, + 0x09,0x00,0x2e,0x10,0x00,0x03,0x00,0x2e,0x0c,0x00,0x01,0x09,0x00,0x2e,0x20,0x00, + 0x03,0x00,0x2e,0x10,0x00,0x01,0x09,0x00,0x2e,0x24,0x00,0x03,0x00,0x2e,0x20,0x00, + 0x01,0x09,0x00,0x2e,0x28,0x00,0x03,0x00,0x2e,0x24,0x00,0x01,0x09,0x00,0x2e,0x2c, + 0x00,0x03,0x00,0x2e,0x28,0x00,0x01,0x09,0x00,0x2e,0x30,0x00,0x03,0x00,0x2e,0x2c, + 0x00,0x01,0x09,0x00,0x2e,0x40,0x00,0x03,0x00,0x2e,0x30,0x00,0x01,0x09,0x00,0x2e, + 0x44,0x00,0x03,0x00,0x2e,0x40,0x00,0x01,0x09,0x00,0x2e,0x48,0x00,0x03,0x00,0x2e, + 0x44,0x00,0x01,0x09,0x00,0x2e,0x4c,0x00,0x03,0x00,0x2e,0x48,0x00,0x01,0x09,0x00, + 0x2e,0x50,0x00,0x03,0x00,0x2e,0x4c,0x00,0x01,0x09,0x00,0x2e,0x80,0x00,0x03,0x00, + 0x2e,0x50,0x00,0x01,0x09,0x00,0x2e,0x84,0x00,0x03,0x00,0x2e,0x80,0x00,0x01,0x09, + 0x00,0x2e,0x88,0x00,0x03,0x00,0x2e,0x84,0x00,0x01,0x09,0x00,0x2e,0x8c,0x00,0x03, + 0x00,0x2e,0x88,0x00,0x01,0x09,0x00,0x2e,0x90,0x00,0x03,0x00,0x2e,0x8c,0x00,0x01, + 0x09,0x00,0x2e,0xa0,0x00,0x03,0x00,0x2e,0x90,0x00,0x01,0x09,0x00,0x2e,0xa4,0x00, + 0x03,0x00,0x2e,0xa0,0x00,0x01,0x09,0x00,0x2e,0xa8,0x00,0x03,0x00,0x2e,0xa4,0x00, + 0x01,0x09,0x00,0x2e,0xac,0x00,0x03,0x00,0x2e,0xa8,0x00,0x01,0x09,0x00,0x2e,0xb0, + 0x00,0x03,0x00,0x2e,0xac,0x00,0x01,0x09,0x00,0x2e,0xc0,0x00,0x03,0x00,0x2e,0xb0, + 0x00,0x01,0x09,0x00,0x2e,0xc4,0x00,0x03,0x00,0x2e,0xc0,0x00,0x01,0x09,0x00,0x2e, + 0xc8,0x00,0x03,0x00,0x2e,0xc4,0x00,0x01,0x09,0x00,0x2e,0xcc,0x00,0x03,0x00,0x2e, + 0xc8,0x00,0x01,0x09,0x00,0x2e,0xd0,0x00,0x03,0x00,0x2e,0xcc,0x00,0x01,0x09,0x00, + 0x2f,0x00,0x00,0x03,0x00,0x2e,0xd0,0x00,0x01,0x09,0x00,0x2f,0x04,0x00,0x03,0x00, + 0x2f,0x00,0x00,0x01,0x09,0x00,0x2f,0x08,0x00,0x03,0x00,0x2f,0x04,0x00,0x01,0x09, + 0x00,0x2f,0x0c,0x00,0x03,0x00,0x2f,0x08,0x00,0x01,0x09,0x00,0x2f,0x10,0x00,0x03, + 0x00,0x2f,0x0c,0x00,0x01,0x09,0x00,0x2f,0x20,0x00,0x03,0x00,0x2f,0x10,0x00,0x01, + 0x09,0x00,0x2f,0x24,0x00,0x03,0x00,0x2f,0x20,0x00,0x01,0x09,0x00,0x2f,0x28,0x00, + 0x03,0x00,0x2f,0x24,0x00,0x01,0x09,0x00,0x2f,0x2c,0x00,0x03,0x00,0x2f,0x28,0x00, + 0x01,0x09,0x00,0x2f,0x30,0x00,0x03,0x00,0x2f,0x2c,0x00,0x01,0x09,0x00,0x2f,0x40, + 0x00,0x03,0x00,0x2f,0x30,0x00,0x01,0x09,0x00,0x2f,0x44,0x00,0x03,0x00,0x2f,0x40, + 0x00,0x01,0x09,0x00,0x2f,0x48,0x00,0x03,0x00,0x2f,0x44,0x00,0x01,0x09,0x00,0x2f, + 0x4c,0x00,0x03,0x00,0x2f,0x48,0x00,0x01,0x09,0x00,0x2f,0x50,0x00,0x03,0x00,0x2f, + 0x4c,0x00,0x01,0x09,0x00,0x2f,0x80,0x00,0x03,0x00,0x2f,0x50,0x00,0x01,0x09,0x00, + 0x2f,0x84,0x00,0x03,0x00,0x2f,0x80,0x00,0x01,0x09,0x00,0x2f,0x88,0x00,0x03,0x00, + 0x2f,0x84,0x00,0x01,0x09,0x00,0x2f,0x8c,0x00,0x03,0x00,0x2f,0x88,0x00,0x01,0x09, + 0x00,0x2f,0x90,0x00,0x03,0x00,0x2f,0x8c,0x00,0x01,0x09,0x00,0x2f,0xa0,0x00,0x03, + 0x00,0x2f,0x90,0x00,0x01,0x09,0x00,0x2f,0xa4,0x00,0x03,0x00,0x2f,0xa0,0x00,0x01, + 0x09,0x00,0x2f,0xa8,0x00,0x03,0x00,0x2f,0xa4,0x00,0x01,0x09,0x00,0x2f,0xac,0x00, + 0x03,0x00,0x2f,0xa8,0x00,0x01,0x09,0x00,0x2f,0xb0,0x00,0x03,0x00,0x2f,0xac,0x00, + 0x01,0x09,0x00,0x2f,0xc0,0x00,0x03,0x00,0x2f,0xb0,0x00,0x01,0x09,0x00,0x2f,0xc4, + 0x00,0x03,0x00,0x2f,0xc0,0x00,0x01,0x09,0x00,0x2f,0xc8,0x00,0x03,0x00,0x2f,0xc4, + 0x00,0x01,0x09,0x00,0x2f,0xcc,0x00,0x03,0x00,0x2f,0xc8,0x00,0x01,0x09,0x00,0x2f, + 0xd0,0x00,0x03,0x00,0x2f,0xcc,0x00,0x01,0x09,0x00,0x30,0x00,0x00,0x03,0x00,0x2f, + 0xd0,0x00,0x01,0x09,0x00,0x30,0x04,0x00,0x03,0x00,0x30,0x00,0x00,0x01,0x09,0x00, + 0x30,0x08,0x00,0x03,0x00,0x30,0x04,0x00,0x01,0x09,0x00,0x30,0x0c,0x00,0x03,0x00, + 0x30,0x08,0x00,0x01,0x09,0x00,0x30,0x10,0x00,0x03,0x00,0x30,0x0c,0x00,0x01,0x09, + 0x00,0x30,0x20,0x00,0x03,0x00,0x30,0x10,0x00,0x01,0x09,0x00,0x30,0x24,0x00,0x03, + 0x00,0x30,0x20,0x00,0x01,0x09,0x00,0x30,0x28,0x00,0x03,0x00,0x30,0x24,0x00,0x01, + 0x09,0x00,0x30,0x2c,0x00,0x03,0x00,0x30,0x28,0x00,0x01,0x09,0x00,0x30,0x30,0x00, + 0x03,0x00,0x30,0x2c,0x00,0x01,0x09,0x00,0x30,0x40,0x00,0x03,0x00,0x30,0x30,0x00, + 0x01,0x09,0x00,0x30,0x44,0x00,0x03,0x00,0x30,0x40,0x00,0x01,0x09,0x00,0x30,0x48, + 0x00,0x03,0x00,0x30,0x44,0x00,0x01,0x09,0x00,0x30,0x4c,0x00,0x03,0x00,0x30,0x48, + 0x00,0x01,0x09,0x00,0x30,0x50,0x00,0x03,0x00,0x30,0x4c,0x00,0x01,0x09,0x00,0x30, + 0x80,0x00,0x03,0x00,0x30,0x50,0x00,0x01,0x09,0x00,0x30,0x84,0x00,0x03,0x00,0x30, + 0x80,0x00,0x01,0x09,0x00,0x30,0x88,0x00,0x03,0x00,0x30,0x84,0x00,0x01,0x09,0x00, + 0x30,0x8c,0x00,0x03,0x00,0x30,0x88,0x00,0x01,0x09,0x00,0x30,0x90,0x00,0x03,0x00, + 0x30,0x8c,0x00,0x01,0x09,0x00,0x30,0xa0,0x00,0x03,0x00,0x30,0x90,0x00,0x01,0x09, + 0x00,0x30,0xa4,0x00,0x03,0x00,0x30,0xa0,0x00,0x01,0x09,0x00,0x30,0xa8,0x00,0x03, + 0x00,0x30,0xa4,0x00,0x01,0x09,0x00,0x30,0xac,0x00,0x03,0x00,0x30,0xa8,0x00,0x01, + 0x09,0x00,0x30,0xb0,0x00,0x03,0x00,0x30,0xac,0x00,0x01,0x09,0x00,0x30,0xc0,0x00, + 0x03,0x00,0x30,0xb0,0x00,0x01,0x09,0x00,0x30,0xc4,0x00,0x03,0x00,0x30,0xc0,0x00, + 0x01,0x09,0x00,0x30,0xc8,0x00,0x03,0x00,0x30,0xc4,0x00,0x01,0x09,0x00,0x30,0xcc, + 0x00,0x03,0x00,0x30,0xc8,0x00,0x01,0x09,0x00,0x30,0xd0,0x00,0x03,0x00,0x30,0xcc, + 0x00,0x01,0x09,0x00,0x31,0x00,0x00,0x03,0x00,0x30,0xd0,0x00,0x01,0x09,0x00,0x31, + 0x04,0x00,0x03,0x00,0x31,0x00,0x00,0x01,0x09,0x00,0x31,0x08,0x00,0x03,0x00,0x31, + 0x04,0x00,0x01,0x09,0x00,0x31,0x0c,0x00,0x03,0x00,0x31,0x08,0x00,0x01,0x09,0x00, + 0x31,0x10,0x00,0x03,0x00,0x31,0x0c,0x00,0x01,0x09,0x00,0x31,0x20,0x00,0x03,0x00, + 0x31,0x10,0x00,0x01,0x09,0x00,0x31,0x24,0x00,0x03,0x00,0x31,0x20,0x00,0x01,0x09, + 0x00,0x31,0x28,0x00,0x03,0x00,0x31,0x24,0x00,0x01,0x09,0x00,0x31,0x2c,0x00,0x03, + 0x00,0x31,0x28,0x00,0x01,0x09,0x00,0x31,0x30,0x00,0x03,0x00,0x31,0x2c,0x00,0x01, + 0x09,0x00,0x31,0x40,0x00,0x03,0x00,0x31,0x30,0x00,0x01,0x09,0x00,0x31,0x44,0x00, + 0x03,0x00,0x31,0x40,0x00,0x01,0x09,0x00,0x31,0x48,0x00,0x03,0x00,0x31,0x44,0x00, + 0x01,0x09,0x00,0x31,0x4c,0x00,0x03,0x00,0x31,0x48,0x00,0x01,0x09,0x00,0x31,0x50, + 0x00,0x03,0x00,0x31,0x4c,0x00,0x01,0x09,0x00,0x31,0x80,0x00,0x03,0x00,0x31,0x50, + 0x00,0x01,0x09,0x00,0x31,0x84,0x00,0x03,0x00,0x31,0x80,0x00,0x01,0x09,0x00,0x31, + 0x88,0x00,0x03,0x00,0x31,0x84,0x00,0x01,0x09,0x00,0x31,0x8c,0x00,0x03,0x00,0x31, + 0x88,0x00,0x01,0x09,0x00,0x31,0x90,0x00,0x03,0x00,0x31,0x8c,0x00,0x01,0x09,0x00, + 0x31,0xa0,0x40,0x03,0x00,0x31,0x90,0x00,0x01,0x09,0x00,0x31,0xa4,0x00,0x03,0x00, + 0x31,0xa0,0x40,0x01,0x09,0x00,0x31,0xa8,0x00,0x03,0x00,0x31,0xa4,0x00,0x01,0x09, + 0x00,0x31,0xac,0x00,0x03,0x00,0x31,0xa8,0x00,0x01,0x09,0x00,0x31,0xb0,0x00,0x03, + 0x00,0x31,0xac,0x00,0x01,0x09,0x00,0x31,0xc0,0x00,0x03,0x00,0x31,0xb0,0x00,0x01, + 0x09,0x00,0x31,0xc4,0x00,0x03,0x00,0x31,0xc0,0x00,0x01,0x09,0x00,0x31,0xc8,0x00, + 0x03,0x00,0x31,0xc4,0x00,0x01,0x09,0x00,0x31,0xcc,0x00,0x03,0x00,0x31,0xc8,0x00, + 0x01,0x09,0x00,0x31,0xd0,0x00,0x03,0x00,0x31,0xcc,0x00,0x01,0x09,0x00,0x32,0x00, + 0x00,0x03,0x00,0x31,0xd0,0x00,0x01,0x09,0x00,0x32,0x04,0x00,0x03,0x00,0x32,0x00, + 0x00,0x01,0x09,0x00,0x32,0x08,0x00,0x03,0x00,0x32,0x04,0x00,0x01,0x09,0x00,0x32, + 0x0c,0x00,0x03,0x00,0x32,0x08,0x00,0x01,0x09,0x00,0x32,0x10,0x00,0x03,0x00,0x32, + 0x0c,0x00,0x01,0x09,0x00,0x32,0x20,0x00,0x03,0x00,0x32,0x10,0x00,0x01,0x09,0x00, + 0x32,0x24,0x00,0x03,0x00,0x32,0x20,0x00,0x01,0x09,0x00,0x32,0x28,0x00,0x03,0x00, + 0x32,0x24,0x00,0x01,0x09,0x00,0x32,0x2c,0x00,0x03,0x00,0x32,0x28,0x00,0x01,0x09, + 0x00,0x32,0x30,0x00,0x03,0x00,0x32,0x2c,0x00,0x01,0x09,0x00,0x32,0x40,0x00,0x03, + 0x00,0x32,0x30,0x00,0x01,0x09,0x00,0x32,0x44,0x00,0x03,0x00,0x32,0x40,0x00,0x01, + 0x09,0x00,0x32,0x48,0x00,0x03,0x00,0x32,0x44,0x00,0x01,0x09,0x00,0x32,0x4c,0x00, + 0x03,0x00,0x32,0x48,0x00,0x01,0x09,0x00,0x32,0x50,0x00,0x03,0x00,0x32,0x4c,0x00, + 0x01,0x09,0x00,0x32,0x80,0x00,0x03,0x00,0x32,0x50,0x00,0x01,0x09,0x00,0x32,0x84, + 0x00,0x03,0x00,0x32,0x80,0x00,0x01,0x09,0x00,0x32,0x88,0x00,0x03,0x00,0x32,0x84, + 0x00,0x01,0x09,0x00,0x32,0x8c,0x00,0x03,0x00,0x32,0x88,0x00,0x01,0x09,0x00,0x32, + 0x90,0x00,0x03,0x00,0x32,0x8c,0x00,0x01,0x09,0x00,0x32,0xa0,0x00,0x23,0x00,0x32, + 0x90,0x00,0x01,0x09,0x00,0x32,0xa4,0x00,0x03,0x00,0x32,0xa0,0x00,0x21,0x09,0x00, + 0x32,0xa8,0x00,0x03,0x00,0x32,0xa4,0x00,0x01,0x09,0x00,0x32,0xac,0x00,0x03,0x00, + 0x32,0xa8,0x00,0x01,0x09,0x00,0x32,0xb0,0x00,0x03,0x00,0x32,0xac,0x00,0x01,0x09, + 0x00,0x32,0xc0,0x00,0x03,0x00,0x32,0xb0,0x00,0x01,0x09,0x00,0x32,0xc4,0x00,0x03, + 0x00,0x32,0xc0,0x00,0x01,0x09,0x00,0x32,0xc8,0x00,0x03,0x00,0x32,0xc4,0x00,0x01, + 0x09,0x00,0x32,0xcc,0x00,0x03,0x00,0x32,0xc8,0x00,0x01,0x09,0x00,0x32,0xd0,0x00, + 0x03,0x00,0x32,0xcc,0x00,0x01,0x09,0x00,0x33,0x00,0x00,0x03,0x00,0x32,0xd0,0x00, + 0x01,0x09,0x00,0x33,0x04,0x00,0x03,0x00,0x33,0x00,0x00,0x01,0x09,0x00,0x33,0x08, + 0x00,0x03,0x00,0x33,0x04,0x00,0x01,0x09,0x00,0x33,0x0c,0x00,0x03,0x00,0x33,0x08, + 0x00,0x01,0x09,0x00,0x33,0x10,0x00,0x03,0x00,0x33,0x0c,0x00,0x01,0x09,0x00,0x33, + 0x20,0x00,0x03,0x00,0x33,0x10,0x00,0x01,0x09,0x00,0x33,0x24,0x00,0x03,0x00,0x33, + 0x20,0x00,0x01,0x09,0x00,0x33,0x28,0x00,0x03,0x00,0x33,0x24,0x00,0x01,0x09,0x00, + 0x33,0x2c,0x00,0x03,0x00,0x33,0x28,0x00,0x01,0x09,0x00,0x33,0x30,0x00,0x03,0x00, + 0x33,0x2c,0x00,0x01,0x09,0x00,0x33,0x40,0x00,0x03,0x00,0x33,0x30,0x00,0x01,0x09, + 0x00,0x33,0x44,0x00,0x03,0x00,0x33,0x40,0x00,0x01,0x09,0x00,0x33,0x48,0x00,0x03, + 0x00,0x33,0x44,0x00,0x01,0x09,0x00,0x33,0x4c,0x00,0x03,0x00,0x33,0x48,0x00,0x01, + 0x09,0x00,0x33,0x50,0x00,0x03,0x00,0x33,0x4c,0x00,0x01,0x09,0x00,0x33,0x80,0x00, + 0x03,0x00,0x33,0x50,0x00,0x01,0x09,0x00,0x33,0x84,0x00,0x03,0x00,0x33,0x80,0x00, + 0x01,0x09,0x00,0x33,0x88,0x00,0x03,0x00,0x33,0x84,0x00,0x01,0x09,0x00,0x33,0x8c, + 0x00,0x03,0x00,0x33,0x88,0x00,0x01,0x09,0x00,0x33,0x90,0x00,0x03,0x00,0x33,0x8c, + 0x00,0x01,0x09,0x00,0x33,0xa0,0x00,0x03,0x00,0x33,0x90,0x00,0x01,0x09,0x00,0x33, + 0xa4,0x00,0x03,0x00,0x33,0xa0,0x00,0x01,0x09,0x00,0x33,0xa8,0x00,0x03,0x00,0x33, + 0xa4,0x00,0x01,0x09,0x00,0x33,0xac,0x00,0x03,0x00,0x33,0xa8,0x00,0x01,0x09,0x00, + 0x33,0xb0,0x00,0x03,0x00,0x33,0xac,0x00,0x01,0x09,0x00,0x33,0xc0,0x00,0x03,0x00, + 0x33,0xb0,0x00,0x01,0x09,0x00,0x33,0xc4,0x00,0x03,0x00,0x33,0xc0,0x00,0x01,0x09, + 0x00,0x33,0xc8,0x00,0x03,0x00,0x33,0xc4,0x00,0x01,0x09,0x00,0x33,0xcc,0x00,0x03, + 0x00,0x33,0xc8,0x00,0x01,0x09,0x00,0x33,0xd0,0x00,0x03,0x00,0x33,0xcc,0x00,0x01, + 0x09,0x00,0x34,0x00,0x00,0x03,0x00,0x33,0xd0,0x00,0x01,0x09,0x00,0x34,0x04,0x00, + 0x03,0x00,0x34,0x00,0x00,0x01,0x09,0x00,0x34,0x08,0x00,0x03,0x00,0x34,0x04,0x00, + 0x01,0x09,0x00,0x34,0x0c,0x00,0x03,0x00,0x34,0x08,0x00,0x01,0x09,0x00,0x34,0x10, + 0x00,0x03,0x00,0x34,0x0c,0x00,0x01,0x09,0x00,0x34,0x20,0x00,0x03,0x00,0x34,0x10, + 0x00,0x01,0x09,0x00,0x34,0x24,0x00,0x03,0x00,0x34,0x20,0x00,0x01,0x09,0x00,0x34, + 0x28,0x00,0x03,0x00,0x34,0x24,0x00,0x01,0x09,0x00,0x34,0x2c,0x00,0x03,0x00,0x34, + 0x28,0x00,0x01,0x09,0x00,0x34,0x30,0x00,0x03,0x00,0x34,0x2c,0x00,0x01,0x09,0x00, + 0x34,0x40,0x00,0x03,0x00,0x34,0x30,0x00,0x01,0x09,0x00,0x34,0x44,0x00,0x03,0x00, + 0x34,0x40,0x00,0x01,0x09,0x00,0x34,0x48,0x00,0x03,0x00,0x34,0x44,0x00,0x01,0x09, + 0x00,0x34,0x4c,0x00,0x03,0x00,0x34,0x48,0x00,0x01,0x09,0x00,0x34,0x50,0x00,0x03, + 0x00,0x34,0x4c,0x00,0x01,0x09,0x00,0x34,0x80,0x00,0x03,0x00,0x34,0x50,0x00,0x01, + 0x09,0x00,0x34,0x84,0x00,0x03,0x00,0x34,0x80,0x00,0x01,0x09,0x00,0x34,0x88,0x00, + 0x03,0x00,0x34,0x84,0x00,0x01,0x09,0x00,0x34,0x8c,0x00,0x03,0x00,0x34,0x88,0x00, + 0x01,0x09,0x00,0x34,0x90,0x00,0x03,0x00,0x34,0x8c,0x00,0x01,0x09,0x00,0x34,0xa0, + 0x00,0x03,0x00,0x34,0x90,0x00,0x01,0x09,0x00,0x34,0xa4,0x00,0x03,0x00,0x34,0xa0, + 0x00,0x01,0x09,0x00,0x34,0xa8,0x00,0x03,0x00,0x34,0xa4,0x00,0x01,0x09,0x00,0x34, + 0xac,0x00,0x03,0x00,0x34,0xa8,0x00,0x01,0x09,0x00,0x34,0xb0,0x00,0x03,0x00,0x34, + 0xac,0x00,0x01,0x09,0x00,0x34,0xc0,0x00,0x03,0x00,0x34,0xb0,0x00,0x01,0x09,0x00, + 0x34,0xc4,0x00,0x03,0x00,0x34,0xc0,0x00,0x01,0x09,0x00,0x34,0xc8,0x00,0x03,0x00, + 0x34,0xc4,0x00,0x01,0x09,0x00,0x34,0xcc,0x00,0x03,0x00,0x34,0xc8,0x00,0x01,0x09, + 0x00,0x34,0xd0,0x00,0x03,0x00,0x34,0xcc,0x00,0x01,0x09,0x00,0x35,0x00,0x00,0x03, + 0x00,0x34,0xd0,0x00,0x01,0x09,0x00,0x35,0x04,0x00,0x03,0x00,0x35,0x00,0x00,0x01, + 0x09,0x00,0x35,0x08,0x00,0x03,0x00,0x35,0x04,0x00,0x01,0x09,0x00,0x35,0x0c,0x00, + 0x03,0x00,0x35,0x08,0x00,0x01,0x09,0x00,0x35,0x10,0x00,0x03,0x00,0x35,0x0c,0x00, + 0x01,0x09,0x00,0x35,0x20,0x00,0x03,0x00,0x35,0x10,0x00,0x01,0x09,0x00,0x35,0x24, + 0x00,0x03,0x00,0x35,0x20,0x00,0x01,0x09,0x00,0x35,0x28,0x00,0x03,0x00,0x35,0x24, + 0x00,0x01,0x09,0x00,0x35,0x2c,0x00,0x03,0x00,0x35,0x28,0x00,0x01,0x09,0x00,0x35, + 0x30,0x00,0x03,0x00,0x35,0x2c,0x00,0x01,0x09,0x00,0x35,0x40,0x00,0x03,0x00,0x35, + 0x30,0x00,0x01,0x09,0x00,0x35,0x44,0x00,0x03,0x00,0x35,0x40,0x00,0x01,0x09,0x00, + 0x35,0x48,0x00,0x03,0x00,0x35,0x44,0x00,0x01,0x09,0x00,0x35,0x4c,0x00,0x03,0x00, + 0x35,0x48,0x00,0x01,0x09,0x00,0x35,0x50,0x00,0x03,0x00,0x35,0x4c,0x00,0x01,0x09, + 0x00,0x35,0x80,0x00,0x03,0x00,0x35,0x50,0x00,0x01,0x09,0x00,0x35,0x84,0x00,0x03, + 0x00,0x35,0x80,0x00,0x01,0x09,0x00,0x35,0x88,0x00,0x03,0x00,0x35,0x84,0x00,0x01, + 0x09,0x00,0x35,0x8c,0x00,0x03,0x00,0x35,0x88,0x00,0x01,0x09,0x00,0x35,0x90,0x00, + 0x03,0x00,0x35,0x8c,0x00,0x01,0x09,0x00,0x35,0xa0,0x00,0x03,0x00,0x35,0x90,0x00, + 0x01,0x09,0x00,0x35,0xa4,0x00,0x03,0x00,0x35,0xa0,0x00,0x01,0x09,0x00,0x35,0xa8, + 0x00,0x03,0x00,0x35,0xa4,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x03,0x00,0x35,0xa8, + 0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x03,0x00,0x35,0xac,0x00,0x01,0x09,0x00,0x35, + 0xc0,0x00,0x03,0x00,0x35,0xb0,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x03,0x00,0x35, + 0xc0,0x00,0x01,0x09,0x00,0x35,0xc8,0x00,0x03,0x00,0x35,0xc4,0x00,0x01,0x09,0x00, + 0x35,0xcc,0x00,0x03,0x00,0x35,0xc8,0x00,0x01,0x09,0x00,0x35,0xd0,0x00,0x03,0x00, + 0x35,0xcc,0x00,0x01,0x09,0x00,0x35,0xd0,0x00,0x03,0x00,0x35,0xd0,0x00,0x01,0x04, + 0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,0x00,0x64,0x02,0x08,0xf0,0x04, + 0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x07,0x00,0x07,0x20,0x12,0x00,0x12,0x01,0x04, + 0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00, + 0x00,0x00, diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c new file mode 100644 index 0000000..33b5f77 --- /dev/null +++ b/board/esd/pmc405/pmc405.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +extern void lxt971_no_sleep(void); + + +/* fpga configuration data - not compressed, generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; +int filesize = sizeof(fpgadata); + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); + + /* + * Setup GPIO pins (CS6+CS7 as GPIO) + */ + mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000); + + /* + * Configure GPIO pins + */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */ + out32(GPIO0_OR, 0); /* outputs -> low */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming PMC405"); + } else { + puts(str); + } + + putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + volatile uchar *ptr; + volatile uchar val; + int i; + + addr = simple_strtol (argv[1], NULL, 16) + 0x16; + + i = 0; + for (;;) { + ptr = (uchar *)addr; + for (i=0; i<8; i++) { + *ptr = i; + val = *ptr; + + if (val != i) { + printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val); + return 0; + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + ptr++; + } + } + + return 0; +} +U_BOOT_CMD( + cantest, 3, 1, do_cantest, + "cantest - Test CAN controller", + NULL + ); diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds new file mode 100644 index 0000000..e84d69e --- /dev/null +++ b/board/esd/pmc405/u-boot.lds @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/tasreg/Makefile b/board/esd/tasreg/Makefile new file mode 100644 index 0000000..e5d8446 --- /dev/null +++ b/board/esd/tasreg/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/tasreg/config.mk b/board/esd/tasreg/config.mk new file mode 100644 index 0000000..69fd8b6 --- /dev/null +++ b/board/esd/tasreg/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffc00000 diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c new file mode 100644 index 0000000..13c07d2 --- /dev/null +++ b/board/esd/tasreg/flash.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +/*#include */ +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; i +#include +#include +#include + + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); + + +#if 0 +#define FPGA_DEBUG +#endif + +/* predefine these here for FPGA programming (before including fpga.c) */ +#define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data) +#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_DONE) +#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_INIT) +#define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */ +#define out32(a,b) /* nothing to do (gpio already configured) */ + + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +int checkboard (void) { + ulong val; + uchar val8; + + puts ("Board: "); + puts("esd TASREG"); + val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; + printf(" (Switch=%1X)\n", val8); + + /* + * Set LED on + */ + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED; + mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ + + return 0; +}; + + +long int initdram (int board_type) { + unsigned long junk = 0xa5a59696; + + /* + * Note: + * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 + */ + +#ifdef CFG_FAST_CLK + /* + * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 + */ + mbar_writeShort(MCFSIM_DCR, 0x8239); +#elif CFG_PLL_BYPASS + /* + * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 + */ + mbar_writeShort(MCFSIM_DCR, 0x8202); +#else + /* + * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) + */ + mbar_writeShort(MCFSIM_DCR, 0x8222); +#endif + + /* + * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), + * PM=1 (continuous page mode) + */ + + /* RE=0 (keep auto-refresh disabled while setting up registers) */ + mbar_writeLong(MCFSIM_DACR0, 0x00003324); + + /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ + mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); + + /** Precharge sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ + *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ + udelay(0x10); /* Allow several Precharge cycles */ + + /** Refresh Sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ + udelay(0x7d0); /* Allow gobs of refresh cycles */ + + /** Mode Register initialization **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ + *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + + +int testdram (void) { + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} + + +int misc_init_r (void) +{ + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + uchar buf[8]; + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); + + /* + * + */ + buf[0] = 0x00; + buf[1] = 0x32; + buf[2] = 0x3f; + i2c_write(0x38, 0, 0, buf, 3); + + return (0); +} + + +#if 1 /* test-only: board specific test commands */ +int i2c_probe(uchar addr); + +/* + */ +int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + if (argc < 2) { + puts("ERROR!\n"); + return -1; + } + + addr = simple_strtol (argv[1], NULL, 16); + + printf("iprobe looping on addr 0x%lx (cntrl-c aborts)...\n", addr); + + for (;;) { + i2c_probe(addr); + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + udelay(1000); + } + + return 0; +} +U_BOOT_CMD( + iploop, 2, 1, do_iploop, + "iploop - iprobe loop \n", + NULL + ); + +/* + */ +int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar buf[8]; + + *(volatile ushort *)0xe0000000 = 0x4000; + + udelay(5000); /* wait for 5ms */ + + buf[0] = 0x10; + buf[1] = 0x07; + buf[2] = 0x03; + i2c_write(0x10, 0, 0, buf, 3); + + buf[0] = 0x10; + buf[1] = 0x01; + buf[2] = 0x80; + i2c_write(0x10, 0, 0, buf, 3); + + buf[0] = 0x10; + buf[1] = 0x02; + buf[2] = 0x03; + i2c_write(0x10, 0, 0, buf, 3); + + buf[0] = 0x10; + buf[1] = 0x03; + buf[2] = 0x29; + i2c_write(0x10, 0, 0, buf, 3); + + buf[0] = 0x10; + buf[1] = 0x04; + buf[2] = 0x00; + i2c_write(0x10, 0, 0, buf, 3); + + buf[0] = 0x10; + buf[1] = 0x05; + buf[2] = 0x00; + i2c_write(0x10, 0, 0, buf, 3); + + buf[0] = 0x10; + buf[1] = 0x07; + buf[2] = 0x02; + i2c_write(0x10, 0, 0, buf, 3); + + return 0; +} +U_BOOT_CMD( + codec, 1, 1, do_codec, + "codec - Enable codec\n", + NULL + ); + +/* + */ +int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + ulong instr; + ulong cntrl; + ulong data; + uchar buf[8]; + + if (argc < 5) { + puts("ERROR!\n"); + return -1; + } + + addr = simple_strtol (argv[1], NULL, 16); + instr = simple_strtol (argv[2], NULL, 16); + cntrl = simple_strtol (argv[3], NULL, 16); + data = simple_strtol (argv[4], NULL, 16); + + buf[0] = (uchar)instr; + buf[1] = (uchar)cntrl; + buf[2] = (uchar)data; + i2c_write(addr, 0, 0, buf, 3); + + return 0; +} +U_BOOT_CMD( + saa, 5, 1, do_saa, + "saa - Write to SAA1064 \n", + NULL + ); + +/* + */ +int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + ulong data0; + ulong data1; + ulong data2; + ulong data3; + uchar buf[8]; + int cnt; + + if (argc < 3) { + puts("ERROR!\n"); + return -1; + } + + addr = simple_strtol (argv[1], NULL, 16); + cnt = simple_strtol (argv[2], NULL, 16); + data0 = simple_strtol (argv[3], NULL, 16); + data1 = simple_strtol (argv[4], NULL, 16); + data2 = simple_strtol (argv[5], NULL, 16); + data3 = simple_strtol (argv[6], NULL, 16); + + printf("Writing %d bytes to device %lx!\n", cnt, addr); + buf[0] = (uchar)data0; + buf[1] = (uchar)data1; + buf[2] = (uchar)data2; + buf[3] = (uchar)data3; + i2c_write(addr, 0, 0, buf, cnt); + + return 0; +} +U_BOOT_CMD( + iwrite, 6, 1, do_iwrite, + "iwrite - Write n bytes to I2C-device\n", + "addr cnt data0 ... datan\n" + ); + +/* + */ +int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + ulong cnt; + uchar buf[32]; + int i; + + if (argc < 3) { + puts("ERROR!\n"); + return -1; + } + + addr = simple_strtol (argv[1], NULL, 16); + cnt = simple_strtol (argv[2], NULL, 16); + + i2c_read(addr, 0, 0, buf, cnt); + printf("I2C Data:"); + for (i=0; i \n", + NULL + ); + +/* + */ +int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + uchar buf[32]; + int cnt; + + if (argc < 2) { + puts("ERROR!\n"); + return -1; + } + + addr = simple_strtol (argv[1], NULL, 16); + cnt = 1; + + printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr); + + for (;;) { + i2c_read(addr, 0, 0, buf, cnt); + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + udelay(3000); + } + + return 0; +} +U_BOOT_CMD( + ireadl, 2, 1, do_ireadl, + "ireadl - Read-loop from I2C \n", + NULL + ); +#endif diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds new file mode 100644 index 0000000..a803b1c --- /dev/null +++ b/board/esd/tasreg/u-boot.lds @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile new file mode 100644 index 0000000..a60495a --- /dev/null +++ b/board/esd/voh405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/voh405/config.mk b/board/esd/voh405/config.mk new file mode 100644 index 0000000..219a4eb --- /dev/null +++ b/board/esd/voh405/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd VOH405 boards +# + +TEXT_BASE = 0xFFF80000 diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/voh405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c new file mode 100644 index 0000000..eda3fd9 --- /dev/null +++ b/board/esd/voh405/voh405.c @@ -0,0 +1,356 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#if 0 +#define FPGA_DEBUG +#endif + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); + +/* fpga configuration data - gzip compressed and generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); + + +/* logo bitmap data - gzip compressed and generated by bin2c */ +unsigned char logo_bmp_320[] = +{ +#include "logo_320_240_4bpp.c" +}; + +unsigned char logo_bmp_640[] = +{ +#include "logo_640_480_24bpp.c" +}; + + +/* + * include common lcd code (for esd boards) + */ +#include "../common/lcd.c" + +#include "../common/s1d13704_320_240_4bpp.h" +#include "../common/s1d13806_320_240_4bpp.h" +#include "../common/s1d13806_640_480_16bpp.h" + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFFB5); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + return 0; +} + + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + volatile unsigned short *lcd_contrast = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4); + volatile unsigned short *lcd_backlight = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6); + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + char *str; + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); + + /* + * Reset FPGA via FPGA_INIT pin + */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */ + udelay(1000); /* wait 1ms */ + out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */ + udelay(1000); /* wait 1ms */ + + /* + * Reset external DUARTs + */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + udelay(10); /* wait 10us */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + udelay(1000); /* wait 1ms */ + + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + + /* + * Enable interrupts in exar duart mcr[3] + */ + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; + + /* + * Init lcd interface and display logo + */ + str = getenv("bd_type"); + if (strcmp(str, "voh405_bw") == 0) { + lcd_setup(0, 1); + lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + regs_13704_320_240_4bpp, + sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), + logo_bmp_320, sizeof(logo_bmp_320)); + } else if (strcmp(str, "voh405_bwbw") == 0) { + lcd_setup(0, 1); + lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + regs_13704_320_240_4bpp, + sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), + logo_bmp_320, sizeof(logo_bmp_320)); + lcd_setup(1, 1); + lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + regs_13806_320_240_4bpp, + sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]), + logo_bmp_320, sizeof(logo_bmp_320)); + } else if (strcmp(str, "voh405_bwc") == 0) { + lcd_setup(0, 1); + lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + regs_13704_320_240_4bpp, + sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), + logo_bmp_320, sizeof(logo_bmp_320)); + lcd_setup(1, 0); + lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + regs_13806_640_480_16bpp, + sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), + logo_bmp_640, sizeof(logo_bmp_640)); + } else { + printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); + return 0; + } + + /* + * Set invert bit in small lcd controller + */ + *(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01; + + /* + * Set default contrast voltage on epson vga controller + */ + *lcd_contrast = 0x4646; + + /* + * Enable backlight + */ + *lcd_backlight = 0xffff; + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming VOH405"); + } else { + puts(str); + } + + if (getenv_r("bd_type", str, sizeof(str)) != -1) { + printf(" (%s)", str); + } else { + puts(" (Missing bd_type!)"); + } + + putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) +{ + volatile unsigned short *fpga_mode = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { /* assert RESET */ + *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + } else { /* release RESET */ + *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + } +} +#endif /* CONFIG_IDE_RESET */ + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile new file mode 100644 index 0000000..a11ee82 --- /dev/null +++ b/board/esd/vom405/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +# Objects for Xilinx JTAG programming (CPLD) +CPLD = ../common/xilinx_jtag/lenval.o \ + ../common/xilinx_jtag/micro.o \ + ../common/xilinx_jtag/ports.o + +OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/vom405/config.mk b/board/esd/vom405/config.mk new file mode 100644 index 0000000..3041b77 --- /dev/null +++ b/board/esd/vom405/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd VOH405 boards +# + +TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0x00FC0000 diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/vom405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c new file mode 100644 index 0000000..445b8fc --- /dev/null +++ b/board/esd/vom405/vom405.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +extern void lxt971_no_sleep(void); + + +/* fpga configuration data - not compressed, generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; +int filesize = sizeof(fpgadata); + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + /* + * Reset CPLD via GPIO12 (CS3) pin + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 12)); + udelay(1000); /* wait 1ms */ + out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 12)); + udelay(1000); /* wait 1ms */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + unsigned char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + int flashcnt; + int delay; + volatile unsigned char *led_reg = (unsigned char *)((ulong)CAN_BA + 0x1000); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming VOM405"); + } else { + puts(str); + } + + printf(" (PLD-Version=%02d)\n", *led_reg); + + /* + * Flash LEDs + */ + for (flashcnt = 0; flashcnt < 3; flashcnt++) { + *led_reg = 0x40; /* LED_B..D off */ + for (delay = 0; delay < 100; delay++) + udelay(1000); + *led_reg = 0x47; /* LED_B..D on */ + for (delay = 0; delay < 50; delay++) + udelay(1000); + } + *led_reg = 0x40; + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +void reset_phy(void) +{ +#ifdef CONFIG_LXT971_NO_SLEEP + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif +} diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile new file mode 100644 index 0000000..a60495a --- /dev/null +++ b/board/esd/wuh405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../common/misc.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/wuh405/config.mk b/board/esd/wuh405/config.mk new file mode 100644 index 0000000..1d743a9 --- /dev/null +++ b/board/esd/wuh405/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ASH405 boards +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c new file mode 100644 index 0000000..89af119 --- /dev/null +++ b/board/esd/wuh405/flash.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + int size_val = 0; + + /* Init: no FLASHes known */ + for (i=0; i>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c new file mode 100644 index 0000000..db24122 --- /dev/null +++ b/board/esd/wuh405/wuh405.c @@ -0,0 +1,252 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#if 0 +#define FPGA_DEBUG +#endif + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* fpga configuration data - gzip compressed and generated by bin2c */ +const unsigned char fpgadata[] = +{ +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +/* Prototypes */ +int gunzip(void *, int, unsigned char *, unsigned long *); + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4); + volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4); + unsigned char *dst; + ulong len = sizeof(fpgadata); + int status; + int index; + int i; + + dst = malloc(CFG_FPGA_MAX_SIZE); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); + } + + status = fpga_boot(dst, len); + if (status != 0) { + printf("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("FPGA: %s\n", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + /* delayed reboot */ + for (i=20; i>0; i--) { + printf("Rebooting in %2d seconds \r",i); + for (index=0;index<1000;index++) + udelay(1000); + } + putc ('\n'); + do_reset(NULL, 0, 0, NULL); + } + + puts("FPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) { + len = dst[index]; + printf("%s ", &(dst[index+1])); + index += len+3; + } + putc ('\n'); + + free(dst); + + /* + * Reset FPGA via FPGA_DATA pin + */ + SET_FPGA(FPGA_PRG | FPGA_CLK); + udelay(1000); /* wait 1ms */ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); + udelay(1000); /* wait 1ms */ + + /* + * Reset external DUARTs + */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + udelay(10); /* wait 10us */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + udelay(1000); /* wait 1ms */ + + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + + /* + * Enable interrupts in exar duart mcr[3] + */ + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; + *duart2_mcr = 0x08; + *duart3_mcr = 0x08; + + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming WUH405"); + } else { + puts(str); + } + + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif diff --git a/board/esteem192e/Makefile b/board/esteem192e/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/esteem192e/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esteem192e/config.mk b/board/esteem192e/config.mk new file mode 100644 index 0000000..9d6080b --- /dev/null +++ b/board/esteem192e/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8xxL boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c new file mode 100644 index 0000000..3959eea --- /dev/null +++ b/board/esteem192e/esteem192e.c @@ -0,0 +1,243 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * Modified By Conn Clark to work with Esteem 192E 7/31/00 + * + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + * + * active, NOP, read, precharge, NOP */ + 0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00, + 0x11FFCC05, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * NOP, Program + */ + 0x0F0A8C34, 0x1F354C37, /* last */ + + _NOT_USED_, /* Not used */ + + /* + * Burst Read. (Offset 8 in UPMA RAM) + * active, NOP, read, NOP, NOP, NOP, NOP, NOP */ + 0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00, + 0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + * active, NOP, write, NOP, precharge, NOP */ + 0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04, + 0x0FF74C04, 0x1FFFCC05, /* last */ + _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + * active, NOP, write, NOP, NOP, NOP, NOP, NOP */ + 0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00, + 0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + * precharge, NOP, auto_ref, NOP, NOP, NOP */ + 0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, + 0x0FFFCCB4, 0x1FFFCC35, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x0FFB8C00, 0x1FF74C03, /* last */ + _NOT_USED_, _NOT_USED_ +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: Esteem 192E\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0, size_b1; + + /* + * Explain frequency of refresh here + */ + + memctl->memc_mptpr = 0x0200; /* divide by 32 */ + + memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */ + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Map cs 2 and 3 to the SDRAM banks 0 and 1 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + + memctl->memc_or2 = CFG_OR2_PRELIM; /* not defined yet */ + memctl->memc_br2 = CFG_BR2_PRELIM; + + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + + /* perform SDRAM initializsation sequence */ + memctl->memc_mar = 0x00000088; + memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */ + memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ + + memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */ + memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ + + memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */ + +/* printf ("banks 0 and 1 are programed\n"); */ + + /* + * Check Bank 0 Memory Size for re-configuration + * + */ + size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + + printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1); + +/* printf ("bank 1 size %u\n",size_b1); */ + + if (size_b1 == 0) { + /* + * Adjust refresh rate if bank 0 isn't stuffed + */ + memctl->memc_mptpr = 0x0400; /* divide by 64 */ + memctl->memc_br3 &= 0x0FFFFFFFE; + + /* + * Adjust OR2 for size of bank 0 + */ + memctl->memc_or2 |= 7 * size_b0; + } else { + if (size_b0 < size_b1) { + memctl->memc_br2 &= 0x00007FFE; + memctl->memc_br3 &= 0x00007FFF; + + /* + * Adjust OR3 for size of bank 1 + */ + memctl->memc_or3 |= 15 * size_b1; + + /* + * Adjust OR2 for size of bank 0 + */ + memctl->memc_or2 |= 15 * size_b0; + memctl->memc_br2 += (size_b1 + 1); + } else { + memctl->memc_br3 &= 0x00007FFE; + + /* + * Adjust OR2 for size of bank 0 + */ + memctl->memc_or2 |= 15 * size_b0; + + /* + * Adjust OR3 for size of bank 1 + */ + memctl->memc_or3 |= 15 * size_b1; + memctl->memc_br3 += (size_b0 + 1); + } + } + + /* before leaving set all unused i/o pins to outputs */ + + /* + * --*Unused Pin List*-- + * + * group/port bit number + * IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx + * PA 5,7,8,9,14,15 + * PB 22,23,31 + * PC 4,5,6,7,10,11,12,13,14,15 + * PD 5,6,7 + * + */ + + /* + * --*Pin Used for I/O List*-- + * + * port input bit number output bit number either + * PB 18,26,27 + * PD 3,4 8,9,10,11,12,13,14,15 + * + */ + + immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */ + immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */ + immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */ + immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */ + + immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */ + immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */ + immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */ + immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */ + + immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */ + immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */ + immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */ + immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high */ + + immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */ + immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */ + immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */ + immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */ + + return (size_b0 + size_b1); +} diff --git a/board/esteem192e/flash.c b/board/esteem192e/flash.c new file mode 100644 index 0000000..5465dea --- /dev/null +++ b/board/esteem192e/flash.c @@ -0,0 +1,1095 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#ifdef CONFIG_FLASH_16BIT +#define FLASH_WORD_SIZE unsigned short +#define FLASH_ID_MASK 0xFFFF +#else +#define FLASH_WORD_SIZE unsigned long +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); +#ifndef CONFIG_FLASH_16BIT +static int write_word (flash_info_t *info, ulong dest, ulong data); +#else +static int write_short (flash_info_t *info, ulong dest, ushort data); +#endif +/*int flash_write (uchar *, ulong, ulong); */ +/*flash_info_t *addr2info (ulong); */ + +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801; /* (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;*/ + + /* Re-do sizing to get full correct info */ + + size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, + &flash_info[0]); + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + if (size_b1) { + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = (CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK); + /*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V;*/ + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start adress table */ + if (info->flash_id & FLASH_BTYPE) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CONFIG_FLASH_16BIT + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00008000; + info->start[3] = base + 0x0000C000; + info->start[4] = base + 0x00010000; + info->start[5] = base + 0x00014000; + info->start[6] = base + 0x00018000; + info->start[7] = base + 0x0001C000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x000E0000; + } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } +#else + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000A000; + info->start[6] = base + 0x0000C000; + info->start[7] = base + 0x0000E000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00070000; + } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } +#endif + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CONFIG_FLASH_16BIT + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00014000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x0001C000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + + } else { + + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +#else + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000A000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x0000E000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + + } else { + + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } +#endif + } + + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar botboot[]=", bottom boot sect)\n"; + uchar topboot[]=", top boot sector)\n"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + if (info->flash_id & 0x0001 ) { + boottype = botboot; + } else { + boottype = topboot; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype); + break; + case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype); + break; + case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype); + break; + case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype); + break; + case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype); + break; + case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype); + break; + case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype); + break; + +#if 0 /* enable when devices are available */ + + case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype); + break; + case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype); + break; +#endif + + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) +{ + short i; + ulong base = (ulong)addr; + FLASH_WORD_SIZE value; + + /* Write auto select command: read Manufacturer ID */ + + +#ifndef CONFIG_FLASH_16BIT + + /* + * Note: if it is an AMD flash and the word at addr[0000] + * is 0x00890089 this routine will think it is an Intel + * flash device and may(most likely) cause trouble. + */ + + addr[0x0000] = 0x00900090; + if(addr[0x0000] != 0x00890089){ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; +#else + + /* + * Note: if it is an AMD flash and the word at addr[0000] + * is 0x0089 this routine will think it is an Intel + * flash device and may(most likely) cause trouble. + */ + + addr[0x0000] = 0x0090; + + if(addr[0x0000] != 0x0089){ + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0090; +#endif + } + value = addr[0]; + + switch (value) { + case (AMD_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_FUJ; + break; + case (STM_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_STM; + break; + case (SST_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_SST; + break; + case (INTEL_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + + } + + value = addr[1]; /* device ID */ + + switch (value) { + + case (AMD_ID_LV400T & FLASH_ID_MASK): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV400B & FLASH_ID_MASK): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800T & FLASH_ID_MASK): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV800B & FLASH_ID_MASK): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160T & FLASH_ID_MASK): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV160B & FLASH_ID_MASK): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & FLASH_ID_MASK): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (AMD_ID_LV320B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + + case (INTEL_ID_28F800B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL800T; + info->sector_count = 23; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (INTEL_ID_28F800B3B & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (INTEL_ID_28F160B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL160T; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (INTEL_ID_28F160B3B & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (INTEL_ID_28F320B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL320T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (INTEL_ID_28F320B3B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + +#if 0 /* enable when devices are available */ + case (INTEL_ID_28F320B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL320T; + info->sector_count = 135; + info->size = 0x01000000; + break; /* => 16 MB */ + + case (INTEL_ID_28F320B3B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 135; + info->size = 0x01000000; + break; /* => 16 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start adress table */ + if (info->flash_id & FLASH_BTYPE) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CONFIG_FLASH_16BIT + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00008000; + info->start[3] = base + 0x0000C000; + info->start[4] = base + 0x00010000; + info->start[5] = base + 0x00014000; + info->start[6] = base + 0x00018000; + info->start[7] = base + 0x0001C000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x000E0000; + } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } +#else + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000A000; + info->start[6] = base + 0x0000C000; + info->start[7] = base + 0x0000E000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00070000; + } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } +#endif + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CONFIG_FLASH_16BIT + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00014000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x0001C000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + + } else { + + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +#else + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000A000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x0000E000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + + } else { + + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } +#endif + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){ + *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { + *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ + } + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + + volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); + int flag, prot, sect, l_sect, barf; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + ((info->flash_id > FLASH_AMD_COMP) && + ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){ + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + if(info->flash_id < FLASH_AMD_COMP) { +#ifndef CONFIG_FLASH_16BIT + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; +#else + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0080; + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; +#endif + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); + addr[0] = (0x00300030 & FLASH_ID_MASK); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); + while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != + (0x00800080&FLASH_ID_MASK) ) + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + barf = 0; +#ifndef CONFIG_FLASH_16BIT + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00200020; + addr[0] = 0x00D000D0; + while(!(addr[0] & 0x00800080)); /* wait for error or finish */ + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; + } + } +#else + addr = (vu_short*)(info->start[sect]); + addr[0] = 0x0020; + addr[0] = 0x00D0; + while(!(addr[0] & 0x0080)); /* wait for error or finish */ + if( addr[0] & 0x003A) /* check for error */ + barf = addr[0] & 0x003A; +#endif + if(barf) { + printf("\nFlash error in sector at %lx\n",(unsigned long)addr); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if((barf & 0x0030) == 0x0030) + printf("Command Sequence error.\n"); + if((barf & 0x0030) == 0x0020) + printf("Block Erase error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + rcode = 1; + } else printf("."); + l_sect = sect; + } + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ + + } + + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ +#ifndef CONFIG_FLASH_16BIT + ulong cp, wp, data; + int l; +#else + ulong cp, wp; + ushort data; +#endif + int i, rc; + +#ifndef CONFIG_FLASH_16BIT + + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); + +#else + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start byte + */ + if (addr - wp) { + data = 0; + data = (data << 8) | *src++; + --cnt; + if ((rc = write_short(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ +/* l = 0; used for debuging */ + while (cnt >= 2) { + data = 0; + for (i=0; i<2; ++i) { + data = (data << 8) | *src++; + } + +/* if(!l){ + printf("%x",data); + l = 1; + } used for debuging */ + + if ((rc = write_short(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<2; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_short(info, wp, data)); + + +#endif +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifndef CONFIG_FLASH_16BIT +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start,barf; + int flag; + + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if(info->flash_id > FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + } else { + /* intel stuff */ + *addr = 0x00400040; + } + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + + if(info->flash_id > FLASH_AMD_COMP) { + + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + } else { + + while(!(addr[0] & 0x00800080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; + } + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + + + } + + return (0); + +} + +#else + +static int write_short (flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short*)(info->start[0]); + ulong start,barf; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_short *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x00A0; + } else { + /* intel stuff */ + *addr = 0x00D0; + *addr = 0x0040; + } + *((vu_short *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + } else { + /* intel stuff */ + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + + if( addr[0] & 0x003A) { /* check for error */ + barf = addr[0] & 0x003A; + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + *addr = 0x00B0; + *addr = 0x0070; + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + + *addr = 0x00FF; + + } + + return (0); + +} + + +#endif + +/*----------------------------------------------------------------------- + */ diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds new file mode 100644 index 0000000..4c541bf --- /dev/null +++ b/board/esteem192e/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/etin/debris/Makefile b/board/etin/debris/Makefile new file mode 100644 index 0000000..305a1bf --- /dev/null +++ b/board/etin/debris/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o phantom.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/etin/debris/config.mk b/board/etin/debris/config.mk new file mode 100644 index 0000000..64debf5 --- /dev/null +++ b/board/etin/debris/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2000, 2001 +# Sangmoon, Etin Systems, dogoil@etinsys.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Debris boards +# + +#TEXT_BASE = 0x00090000 +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c new file mode 100644 index 0000000..93c502c --- /dev/null +++ b/board/etin/debris/debris.c @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2000 + * Sangmoon Kim, Etin Systems. dogoil@etinsys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +int checkboard (void) +{ + /*TODO: Check processor type */ + + puts ( "Board: Debris " +#ifdef CONFIG_MPC8240 + "8240" +#endif +#ifdef CONFIG_MPC8245 + "8245" +#endif + " ##Test not implemented yet##\n"); + return 0; +} + +#if 0 /* NOT USED */ +int checkflash (void) +{ + /* TODO: XXX XXX XXX */ + printf ("## Test not implemented yet ##\n"); + + return (0); +} +#endif + +long int initdram (int board_type) +{ + int m, row, col, bank, i; + unsigned long start, end; + uint32_t mccr1; + uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; + uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; + uint8_t mber = 0; + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */ + m = i2c_reg_read (0x50, 5); /* # of physical banks */ + row = i2c_reg_read (0x50, 3); /* # of rows */ + col = i2c_reg_read (0x50, 4); /* # of columns */ + bank = i2c_reg_read (0x50, 17); /* # of logical banks */ + + CONFIG_READ_WORD(MCCR1, mccr1); + mccr1 &= 0xffff0000; + + start = CFG_SDRAM_BASE; + end = start + (1 << (col + row + 3) ) * bank - 1; + + for (i = 0; i < m; i++) { + mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; + if (i < 4) { + msar1 |= ((start >> 20) & 0xff) << i * 8; + emsar1 |= ((start >> 28) & 0xff) << i * 8; + mear1 |= ((end >> 20) & 0xff) << i * 8; + emear1 |= ((end >> 28) & 0xff) << i * 8; + } else { + msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; + emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; + mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; + emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; + } + mber |= 1 << i; + start += (1 << (col + row + 3) ) * bank; + end += (1 << (col + row + 3) ) * bank; + } + for (; i < 8; i++) { + if (i < 4) { + msar1 |= 0xff << i * 8; + emsar1 |= 0x30 << i * 8; + mear1 |= 0xff << i * 8; + emear1 |= 0x30 << i * 8; + } else { + msar2 |= 0xff << (i-4) * 8; + emsar2 |= 0x30 << (i-4) * 8; + mear2 |= 0xff << (i-4) * 8; + emear2 |= 0x30 << (i-4) * 8; + } + } + + CONFIG_WRITE_WORD(MCCR1, mccr1); + CONFIG_WRITE_WORD(MSAR1, msar1); + CONFIG_WRITE_WORD(EMSAR1, emsar1); + CONFIG_WRITE_WORD(MEAR1, mear1); + CONFIG_WRITE_WORD(EMEAR1, emear1); + CONFIG_WRITE_WORD(MSAR2, msar2); + CONFIG_WRITE_WORD(EMSAR2, emsar2); + CONFIG_WRITE_WORD(MEAR2, mear2); + CONFIG_WRITE_WORD(EMEAR2, emear2); + CONFIG_WRITE_BYTE(MBER, mber); + + return (1 << (col + row + 3) ) * bank * m; +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_debris_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_debris_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} + +void *nvram_read(void *dest, const long src, size_t count) +{ + volatile uchar *d = (volatile uchar*) dest; + volatile uchar *s = (volatile uchar*) src; + while(count--) { + *d++ = *s++; + asm volatile("sync"); + } + return dest; +} + +void nvram_write(long dest, const void *src, size_t count) +{ + volatile uchar *d = (volatile uchar*)dest; + volatile uchar *s = (volatile uchar*)src; + while(count--) { + *d++ = *s++; + asm volatile("sync"); + } +} + +int misc_init_r(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Write ethernet addr in NVRAM for VxWorks */ + nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS, + (char*)&gd->bd->bi_enetaddr[0], 6); + return 0; +} diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c new file mode 100644 index 0000000..a4100e5 --- /dev/null +++ b/board/etin/debris/flash.c @@ -0,0 +1,720 @@ +/* + * board/eva/flash.c + * + * (C) Copyright 2002 + * Sangmoon Kim, Etin Systems, dogoil@etinsys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t); +int (*write_dword)(flash_info_t*, ulong, uint64_t); + +typedef uint64_t cfi_word; + +#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr)) + +#define cfi_write(flash, val, addr) \ + move64((cfi_word*)&val, \ + (cfi_word*)(flash->start[0] + addr)) + +#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x))) + +static void write32(unsigned long addr, uint32_t value) +{ + *(volatile uint32_t*)(addr) = value; + asm volatile("sync"); +} + +static uint32_t read32(unsigned long addr) +{ + uint32_t value; + value = *(volatile uint32_t*)addr; + asm volatile("sync"); + return value; +} + +static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr) +{ + uint32_t base = flash->start[0]; + uint32_t val=(cmd << 16) | cmd; + addr <<= 3; + write32(base + addr, val); + return addr; +} + +static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr) +{ + uint32_t base = flash->start[0]; + addr <<= 3; + return (uint16_t)read32(base + addr); +} + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static void move64(uint64_t *src, uint64_t *dest) +{ + asm volatile("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : : "fr0" ); /* Clobbers fr0 */ + return; +} + +static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data) +{ + unsigned long start; + cfi_word status = 0; + + status = cfi_read(flash, dest); + data &= status; + + cfi_cmd(flash, 0x40, 0); + cfi_write(flash, data, dest); + + udelay(10); + start = get_timer (0); + for(;;) { + status = cfi_read(flash, dest); + status &= CMD(0x80); + if(status == CMD(0x80)) + break; + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + cfi_cmd(flash, 0xff, 0); + return 1; + } + udelay(1); + } + cfi_cmd(flash, 0xff, 0); + + return 0; +} + +static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data) +{ + ulong start; + cfi_word status = 0; + + status = cfi_read(flash, dest); + if(status != CMD(0xffff)) return 2; + + cfi_cmd(flash, 0xaa, 0x555); + cfi_cmd(flash, 0x55, 0x2aa); + cfi_cmd(flash, 0xa0, 0x555); + + cfi_write(flash, data, dest); + + udelay(10); + start = get_timer (0); + status = ~data; + while(status != data) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return 1; + status = cfi_read(flash, dest); + udelay(1); + } + return 0; +} + +static __inline__ unsigned long get_msr(void) +{ + unsigned long msr; + __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr(unsigned long msr) +{ + __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); +} + +int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + int i, s, l, rc; + cfi_word data; + uint8_t *t = (uint8_t*)&data; + unsigned long base = flash->start[0]; + uint32_t msr; + + if (flash->flash_id == FLASH_UNKNOWN) + return 4; + + if (cnt == 0) + return 0; + + addr -= base; + + msr = get_msr(); + set_msr(msr|MSR_FP); + + wp = (addr & ~7); /* get lower word aligned address */ + + if((addr-wp) != 0) { + data = cfi_read(flash, wp); + s = addr & 7; + l = ( cnt < (8-s) ) ? cnt : (8-s); + for(i = 0; i < l; i++) + t[s+i] = *src++; + if ((rc = write_dword(flash, wp, data)) != 0) + goto DONE; + wp += 8; + cnt -= l; + } + + while (cnt >= 8) { + for (i = 0; i < 8; i++) + t[i] = *src++; + if ((rc = write_dword(flash, wp, data)) != 0) + goto DONE; + wp += 8; + cnt -= 8; + } + + if (cnt == 0) { + rc = 0; + goto DONE; + } + + data = cfi_read(flash, wp); + for(i = 0; i < cnt; i++) + t[i] = *src++; + rc = write_dword(flash, wp, data); +DONE: + set_msr(msr); + return rc; +} + +static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect) +{ + int sa; + int flag; + ulong start, last, now; + cfi_word status; + + flag = disable_interrupts(); + + sa = (flash->start[sect] - flash->start[0]); + write32(flash->start[sect], 0x00200020); + write32(flash->start[sect], 0x00d000d0); + + if (flag) + enable_interrupts(); + + udelay(1000); + start = get_timer (0); + last = start; + + for (;;) { + status = cfi_read(flash, sa); + status &= CMD(0x80); + if (status == CMD(0x80)) + break; + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + cfi_cmd(flash, 0xff, 0); + printf ("Timeout\n"); + return ERR_TIMOUT; + } + + if ((now - last) > 1000) { + serial_putc ('.'); + last = now; + } + udelay(10); + } + cfi_cmd(flash, 0xff, 0); + return ERR_OK; +} + +static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last) +{ + int sect; + int rc = ERR_OK; + + for (sect = s_first; sect <= s_last; sect++) { + if (flash->protect[sect] == 0) { + rc = cfi_erase_oneblock(flash, sect); + if (rc != ERR_OK) break; + } + } + printf (" done\n"); + return rc; +} + +static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last) +{ + int sect; + cfi_word status; + int sa = -1; + int flag; + ulong start, last, now; + + flag = disable_interrupts(); + + cfi_cmd(flash, 0xaa, 0x555); + cfi_cmd(flash, 0x55, 0x2aa); + cfi_cmd(flash, 0x80, 0x555); + cfi_cmd(flash, 0xaa, 0x555); + cfi_cmd(flash, 0x55, 0x2aa); + for ( sect = s_first; sect <= s_last; sect++) { + if (flash->protect[sect] == 0) { + sa = flash->start[sect] - flash->start[0]; + write32(flash->start[sect], 0x00300030); + } + } + if (flag) + enable_interrupts(); + + if (sa < 0) + goto DONE; + + udelay (1000); + start = get_timer (0); + last = start; + for(;;) { + status = cfi_read(flash, sa); + if (status == CMD(0xffff)) + break; + + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return ERR_TIMOUT; + } + + if ((now - last) > 1000) { + serial_putc ('.'); + last = now; + } + udelay(10); + } +DONE: + cfi_cmd(flash, 0xf0, 0); + + printf (" done\n"); + + return ERR_OK; +} + +int flash_erase (flash_info_t *flash, int s_first, int s_last) +{ + int sect; + int prot; + + if ((s_first < 0) || (s_first > s_last)) { + if (flash->flash_id == FLASH_UNKNOWN) + printf ("- missing\n"); + else + printf ("- no sectors to erase\n"); + return ERR_NOT_ERASED; + } + if (flash->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return ERR_NOT_ERASED; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) + if (flash->protect[sect]) prot++; + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf ("\n"); + + return do_flash_erase(flash, s_first, s_last); +} + +struct jedec_flash_info { + const uint16_t mfr_id; + const uint16_t dev_id; + const char *name; + const int DevSize; + const int InterfaceDesc; + const int NumEraseRegions; + const ulong regions[4]; +}; + +#define ERASEINFO(size,blocks) (size<<8)|(blocks-1) + +#define SIZE_1MiB 20 +#define SIZE_2MiB 21 +#define SIZE_4MiB 22 + +static const struct jedec_flash_info jedec_table[] = { + { + mfr_id: (uint16_t)AMD_MANUFACT, + dev_id: (uint16_t)AMD_ID_LV800T, + name: "AMD AM29LV800T", + DevSize: SIZE_1MiB, + NumEraseRegions: 4, + regions: {ERASEINFO(0x10000,15), + ERASEINFO(0x08000,1), + ERASEINFO(0x02000,2), + ERASEINFO(0x04000,1) + } + }, { + mfr_id: (uint16_t)AMD_MANUFACT, + dev_id: (uint16_t)AMD_ID_LV800B, + name: "AMD AM29LV800B", + DevSize: SIZE_1MiB, + NumEraseRegions: 4, + regions: {ERASEINFO(0x10000,15), + ERASEINFO(0x08000,1), + ERASEINFO(0x02000,2), + ERASEINFO(0x04000,1) + } + }, { + mfr_id: (uint16_t)AMD_MANUFACT, + dev_id: (uint16_t)AMD_ID_LV160T, + name: "AMD AM29LV160T", + DevSize: SIZE_2MiB, + NumEraseRegions: 4, + regions: {ERASEINFO(0x10000,31), + ERASEINFO(0x08000,1), + ERASEINFO(0x02000,2), + ERASEINFO(0x04000,1) + } + }, { + mfr_id: (uint16_t)AMD_MANUFACT, + dev_id: (uint16_t)AMD_ID_LV160B, + name: "AMD AM29LV160B", + DevSize: SIZE_2MiB, + NumEraseRegions: 4, + regions: {ERASEINFO(0x04000,1), + ERASEINFO(0x02000,2), + ERASEINFO(0x08000,1), + ERASEINFO(0x10000,31) + } + }, { + mfr_id: (uint16_t)AMD_MANUFACT, + dev_id: (uint16_t)AMD_ID_LV320T, + name: "AMD AM29LV320T", + DevSize: SIZE_4MiB, + NumEraseRegions: 2, + regions: {ERASEINFO(0x10000,63), + ERASEINFO(0x02000,8) + } + + }, { + mfr_id: (uint16_t)AMD_MANUFACT, + dev_id: (uint16_t)AMD_ID_LV320B, + name: "AMD AM29LV320B", + DevSize: SIZE_4MiB, + NumEraseRegions: 2, + regions: {ERASEINFO(0x02000,8), + ERASEINFO(0x10000,63) + } + } +}; + +static ulong cfi_init(uint32_t base, flash_info_t *flash) +{ + int sector; + int block; + int block_count; + int offset = 0; + int reverse = 0; + int primary; + int mfr_id; + int dev_id; + + flash->start[0] = base; + cfi_cmd(flash, 0xF0, 0); + cfi_cmd(flash, 0x98, 0); + if ( !( cfi_read_query(flash, 0x10) == 'Q' && + cfi_read_query(flash, 0x11) == 'R' && + cfi_read_query(flash, 0x12) == 'Y' )) { + cfi_cmd(flash, 0xff, 0); + return 0; + } + + flash->size = 1 << cfi_read_query(flash, 0x27); + flash->size *= 4; + block_count = cfi_read_query(flash, 0x2c); + primary = cfi_read_query(flash, 0x15); + if ( cfi_read_query(flash, primary + 4) == 0x30) + reverse = (cfi_read_query(flash, 0x1) & 0x01); + else + reverse = (cfi_read_query(flash, primary+15) == 3); + + flash->sector_count = 0; + + for ( block = reverse ? block_count - 1 : 0; + reverse ? block >= 0 : block < block_count; + reverse ? block-- : block ++) { + int sector_size = + (cfi_read_query(flash, 0x2d + block*4+2) | + (cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8; + int sector_count = + (cfi_read_query(flash, 0x2d + block*4+0) | + (cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1; + for(sector = 0; sector < sector_count; sector++) { + flash->start[flash->sector_count++] = base + offset; + offset += sector_size * 4; + } + } + mfr_id = cfi_read_query(flash, 0x00); + dev_id = cfi_read_query(flash, 0x01); + + cfi_cmd(flash, 0xff, 0); + + flash->flash_id = (mfr_id << 16) | dev_id; + + for (sector = 0; sector < flash->sector_count; sector++) { + write32(flash->start[sector], 0x00600060); + write32(flash->start[sector], 0x00d000d0); + } + cfi_cmd(flash, 0xff, 0); + + for (sector = 0; sector < flash->sector_count; sector++) + flash->protect[sector] = 0; + + do_flash_erase = cfi_erase; + write_dword = cfi_write_dword; + + return flash->size; +} + +static ulong jedec_init(unsigned long base, flash_info_t *flash) +{ + int i; + int block, block_count; + int sector, offset; + int mfr_id, dev_id; + flash->start[0] = base; + cfi_cmd(flash, 0xF0, 0x000); + cfi_cmd(flash, 0xAA, 0x555); + cfi_cmd(flash, 0x55, 0x2AA); + cfi_cmd(flash, 0x90, 0x555); + mfr_id = cfi_read_query(flash, 0x000); + dev_id = cfi_read_query(flash, 0x0001); + cfi_cmd(flash, 0xf0, 0x000); + + for(i=0; iflash_id = (mfr_id << 16) | dev_id; + flash->size = 1 << jedec_table[0].DevSize; + flash->size *= 4; + block_count = jedec_table[i].NumEraseRegions; + offset = 0; + flash->sector_count = 0; + for (block = 0; block < block_count; block++) { + int sector_size = jedec_table[i].regions[block]; + int sector_count = (sector_size & 0xff) + 1; + sector_size >>= 8; + for (sector=0; sectorstart[flash->sector_count++] = + base + offset; + offset += sector_size * 4; + } + } + break; + } + } + + for (sector = 0; sector < flash->sector_count; sector++) + flash->protect[sector] = 0; + + do_flash_erase = jedec_erase; + write_dword = jedec_write_dword; + + return flash->size; +} + +inline void mtibat1u(unsigned int x) +{ + __asm__ __volatile__ ("mtspr 530, %0" :: "r" (x)); +} + +inline void mtibat1l(unsigned int x) +{ + __asm__ __volatile__ ("mtspr 531, %0" :: "r" (x)); +} + +inline void mtdbat1u(unsigned int x) +{ + __asm__ __volatile__ ("mtspr 538, %0" :: "r" (x)); +} + +inline void mtdbat1l(unsigned int x) +{ + __asm__ __volatile__ ("mtspr 539, %0" :: "r" (x)); +} + +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + unsigned int msr; + + /* BAT1 */ + CONFIG_WRITE_WORD(ERCR3, 0x0C00000C); + CONFIG_WRITE_WORD(ERCR4, 0x0800000C); + msr = get_msr(); + set_msr(msr & ~(MSR_IR | MSR_DR)); + mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); + mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); + mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); + mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); + set_msr(msr); + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + flash_info[i].flash_id = FLASH_UNKNOWN; + size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]); + if (!size) + size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) + printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", + size, size<<20); + + return size; +} + +void flash_print_info (flash_info_t *flash) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *p; + + if (flash->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + flash_init(); + } + + if (flash->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (((flash->flash_id) >> 16) & 0xff) { + case 0x01: + printf ("AMD "); + break; + case 0x04: + printf("FUJITSU "); + break; + case 0x20: + printf("STM "); + break; + case 0xBF: + printf("SST "); + break; + case 0x89: + case 0xB0: + printf("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch ((flash->flash_id) & 0xffff) { + case (uint16_t)AMD_ID_LV800T: + printf ("AM29LV800T\n"); + break; + case (uint16_t)AMD_ID_LV800B: + printf ("AM29LV800B\n"); + break; + case (uint16_t)AMD_ID_LV160T: + printf ("AM29LV160T\n"); + break; + case (uint16_t)AMD_ID_LV160B: + printf ("AM29LV160B\n"); + break; + case (uint16_t)AMD_ID_LV320T: + printf ("AM29LV320T\n"); + break; + case (uint16_t)AMD_ID_LV320B: + printf ("AM29LV320B\n"); + break; + case (uint16_t)INTEL_ID_28F800C3T: + printf ("28F800C3T\n"); + break; + case (uint16_t)INTEL_ID_28F800C3B: + printf ("28F800C3B\n"); + break; + case (uint16_t)INTEL_ID_28F160C3T: + printf ("28F160C3T\n"); + break; + case (uint16_t)INTEL_ID_28F160C3B: + printf ("28F160C3B\n"); + break; + case (uint16_t)INTEL_ID_28F320C3T: + printf ("28F320C3T\n"); + break; + case (uint16_t)INTEL_ID_28F320C3B: + printf ("28F320C3B\n"); + break; + case (uint16_t)INTEL_ID_28F640C3T: + printf ("28F640C3T\n"); + break; + case (uint16_t)INTEL_ID_28F640C3B: + printf ("28F640C3B\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + if (flash->size >= (1 << 20)) { + printf (" Size: %ld MB in %d Sectors\n", + flash->size >> 20, flash->sector_count); + } else { + printf (" Size: %ld kB in %d Sectors\n", + flash->size >> 10, flash->sector_count); + } + + printf (" Sector Start Addresses:"); + for (i = 0; i < flash->sector_count; ++i) { + /* Check if whole sector is erased*/ + if (i != (flash->sector_count-1)) + size = flash->start[i+1] - flash->start[i]; + else + size = flash->start[0] + flash->size - flash->start[i]; + + erased = 1; + p = (volatile unsigned long *)flash->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + flash->protect[i] ? "RO " : " "); + } + printf ("\n"); +} diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c new file mode 100644 index 0000000..0b81fc0 --- /dev/null +++ b/board/etin/debris/phantom.c @@ -0,0 +1,310 @@ +/* + * board/eva/phantom.c + * + * Phantom RTC device driver for EVA + * + * Author: Sangmoon Kim + * dogoil@etinsys.com + * + * Copyright 2002 Etinsys Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + +#define RTC_BASE (CFG_NVRAM_BASE_ADDR + 0x7fff8) + +#define RTC_YEAR ( RTC_BASE + 7 ) +#define RTC_MONTH ( RTC_BASE + 6 ) +#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 ) +#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 ) +#define RTC_HOURS ( RTC_BASE + 3 ) +#define RTC_MINUTES ( RTC_BASE + 2 ) +#define RTC_SECONDS ( RTC_BASE + 1 ) +#define RTC_CENTURY ( RTC_BASE + 0 ) + +#define RTC_CONTROLA RTC_CENTURY +#define RTC_CONTROLB RTC_SECONDS +#define RTC_CONTROLC RTC_DAY_OF_WEEK + +#define RTC_CA_WRITE 0x80 +#define RTC_CA_READ 0x40 + +#define RTC_CB_OSC_DISABLE 0x80 + +#define RTC_CC_BATTERY_FLAG 0x80 +#define RTC_CC_FREQ_TEST 0x40 + + +static int phantom_flag = -1; +static int century_flag = -1; + +static uchar rtc_read(unsigned int addr) +{ + return *(volatile unsigned char *)(addr); +} + +static void rtc_write(unsigned int addr, uchar val) +{ + *(volatile unsigned char *)(addr) = val; +} + +static unsigned char phantom_rtc_sequence[] = { + 0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c +}; + +static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8]) +{ + int i, j; + unsigned char v; + unsigned char save = rtc_read(addr); + + for (j = 0; j < 8; j++) { + v = phantom_rtc_sequence[j]; + for (i = 0; i < 8; i++) { + rtc_write(addr, v & 1); + v >>= 1; + } + } + for (j = 0; j < 8; j++) { + v = 0; + for (i = 0; i < 8; i++) { + if(rtc_read(addr) & 1) + v |= 1 << i; + } + rtc[j] = v; + } + rtc_write(addr, save); + return rtc; +} + +static void phantom_rtc_write(int addr, unsigned char rtc[8]) +{ + int i, j; + unsigned char v; + unsigned char save = rtc_read(addr); + for (j = 0; j < 8; j++) { + v = phantom_rtc_sequence[j]; + for (i = 0; i < 8; i++) { + rtc_write(addr, v & 1); + v >>= 1; + } + } + for (j = 0; j < 8; j++) { + v = rtc[j]; + for (i = 0; i < 8; i++) { + rtc_write(addr, v & 1); + v >>= 1; + } + } + rtc_write(addr, save); +} + +static int get_phantom_flag(void) +{ + int i; + unsigned char rtc[8]; + + phantom_rtc_read(RTC_BASE, rtc); + + for(i = 1; i < 8; i++) { + if (rtc[i] != rtc[0]) + return 1; + } + return 0; +} + +void rtc_reset(void) +{ + if (phantom_flag < 0) + phantom_flag = get_phantom_flag(); + + if (phantom_flag) { + unsigned char rtc[8]; + phantom_rtc_read(RTC_BASE, rtc); + if(rtc[4] & 0x30) { + printf( "real-time-clock was stopped. Now starting...\n" ); + rtc[4] &= 0x07; + phantom_rtc_write(RTC_BASE, rtc); + } + } else { + uchar reg_a, reg_b, reg_c; + reg_a = rtc_read( RTC_CONTROLA ); + reg_b = rtc_read( RTC_CONTROLB ); + + if ( reg_b & RTC_CB_OSC_DISABLE ) + { + printf( "real-time-clock was stopped. Now starting...\n" ); + reg_a |= RTC_CA_WRITE; + reg_b &= ~RTC_CB_OSC_DISABLE; + rtc_write( RTC_CONTROLA, reg_a ); + rtc_write( RTC_CONTROLB, reg_b ); + } + + /* make sure read/write clock register bits are cleared */ + reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); + rtc_write( RTC_CONTROLA, reg_a ); + + reg_c = rtc_read( RTC_CONTROLC ); + if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) + printf( "RTC battery low. Clock setting may not be reliable.\n"); + } +} + +inline unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +inline unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +static int get_century_flag(void) +{ + int flag = 0; + int bcd, century; + bcd = rtc_read( RTC_CENTURY ); + century = bcd2bin( bcd & 0x3F ); + rtc_write( RTC_CENTURY, bin2bcd(century+1)); + if (bcd == rtc_read( RTC_CENTURY )) + flag = 1; + rtc_write( RTC_CENTURY, bcd); + return flag; +} + +void rtc_get( struct rtc_time *tmp) +{ + if (phantom_flag < 0) + phantom_flag = get_phantom_flag(); + + if (phantom_flag) + { + unsigned char rtc[8]; + + phantom_rtc_read(RTC_BASE, rtc); + + tmp->tm_sec = bcd2bin(rtc[1] & 0x7f); + tmp->tm_min = bcd2bin(rtc[2] & 0x7f); + tmp->tm_hour = bcd2bin(rtc[3] & 0x1f); + tmp->tm_wday = bcd2bin(rtc[4] & 0x7); + tmp->tm_mday = bcd2bin(rtc[5] & 0x3f); + tmp->tm_mon = bcd2bin(rtc[6] & 0x1f); + tmp->tm_year = bcd2bin(rtc[7]) + 1900; + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + + if( (rtc[3] & 0x80) && (rtc[3] & 0x40) ) tmp->tm_hour += 12; + if (tmp->tm_year < 1970) tmp->tm_year += 100; + } else { + uchar sec, min, hour; + uchar mday, wday, mon, year; + + int century; + + uchar reg_a; + + if (century_flag < 0) + century_flag = get_century_flag(); + + reg_a = rtc_read( RTC_CONTROLA ); + /* lock clock registers for read */ + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); + + sec = rtc_read( RTC_SECONDS ); + min = rtc_read( RTC_MINUTES ); + hour = rtc_read( RTC_HOURS ); + mday = rtc_read( RTC_DAY_OF_MONTH ); + wday = rtc_read( RTC_DAY_OF_WEEK ); + mon = rtc_read( RTC_MONTH ); + year = rtc_read( RTC_YEAR ); + century = rtc_read( RTC_CENTURY ); + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); + + tmp->tm_sec = bcd2bin( sec & 0x7F ); + tmp->tm_min = bcd2bin( min & 0x7F ); + tmp->tm_hour = bcd2bin( hour & 0x3F ); + tmp->tm_mday = bcd2bin( mday & 0x3F ); + tmp->tm_mon = bcd2bin( mon & 0x1F ); + tmp->tm_wday = bcd2bin( wday & 0x07 ); + + if (century_flag) { + tmp->tm_year = bcd2bin( year ) + + ( bcd2bin( century & 0x3F ) * 100 ); + } else { + tmp->tm_year = bcd2bin( year ) + 1900; + if (tmp->tm_year < 1970) tmp->tm_year += 100; + } + + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + } +} + +void rtc_set( struct rtc_time *tmp ) +{ + if (phantom_flag < 0) + phantom_flag = get_phantom_flag(); + + if (phantom_flag) { + uint year; + unsigned char rtc[8]; + + year = tmp->tm_year; + year -= (year < 2000) ? 1900 : 2000; + + rtc[0] = bin2bcd(0); + rtc[1] = bin2bcd(tmp->tm_sec); + rtc[2] = bin2bcd(tmp->tm_min); + rtc[3] = bin2bcd(tmp->tm_hour); + rtc[4] = bin2bcd(tmp->tm_wday); + rtc[5] = bin2bcd(tmp->tm_mday); + rtc[6] = bin2bcd(tmp->tm_mon); + rtc[7] = bin2bcd(year); + + phantom_rtc_write(RTC_BASE, rtc); + } else { + uchar reg_a; + if (century_flag < 0) + century_flag = get_century_flag(); + + /* lock clock registers for write */ + reg_a = rtc_read( RTC_CONTROLA ); + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); + + rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); + + rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); + rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); + rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); + rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); + rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); + + /* break year up into century and year in century */ + if (century_flag) { + rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); + rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); + reg_a &= 0xc0; + reg_a |= bin2bcd( tmp->tm_year / 100 ); + } else { + rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year - + ((tmp->tm_year < 2000) ? 1900 : 2000))); + } + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); + } +} + +#endif diff --git a/board/etin/debris/speed.h b/board/etin/debris/speed.h new file mode 100644 index 0000000..b66393b --- /dev/null +++ b/board/etin/debris/speed.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*----------------------------------------------------------------------- + * Timer value for timer 2, ICLK = 10 + * + * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) + * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 + * + * SPEED_FCOUNT2 timer 2 counting frequency + * GCLK CPU clock + * SPEED_TMR2_PS prescaler + */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ + +/*----------------------------------------------------------------------- + * Timer value for PIT + * + * PIT_TIME = SPEED_PITC / PITRTCLK + * PITRTCLK = 8192 + */ +#define SPEED_PITC (82 << 16) /* start counting from 82 */ + +/* + * The new value for PTA is calculated from + * + * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) + * + * gclk CPU clock (not bus clock !) + * Trefresh Refresh cycle * 4 (four word bursts used) + * DFBRG For normal mode (no clock reduction) always 0 + * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) + * NCS Number of SDRAM banks (chip selects) on this UPM. + */ diff --git a/board/etin/debris/u-boot.lds b/board/etin/debris/u-boot.lds new file mode 100644 index 0000000..c742bcd --- /dev/null +++ b/board/etin/debris/u-boot.lds @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/etx094/Makefile b/board/etx094/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/etx094/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/etx094/config.mk b/board/etx094/config.mk new file mode 100644 index 0000000..655c2db --- /dev/null +++ b/board/etx094/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# ETX_094 Boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c new file mode 100644 index 0000000..dba3c11 --- /dev/null +++ b/board/etx094/etx094.c @@ -0,0 +1,386 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); +static void read_hw_vers (void); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + + /* single read (offset 0x00 in upm ram) */ + + 0xEECEFC24, 0x100DFC24, 0xE02FBC04, 0x01AA7C04, + 0x1FB5FC00, 0xFFFFFC05, _NOT_USED_, _NOT_USED_, + + /* burst read (offset 0x08 in upm ram) */ + + 0xEECEFC24, 0x100DFC24, 0xE0FFBC04, 0x10FF7C04, + 0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC00, 0xFFFFFC00, + 0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* single write (offset 0x18 in upm ram) */ + + 0xEECEFC24, 0x100DFC24, 0xE02BBC04, 0x01A27C00, + 0xEFAAFC04, 0x1FB5FC05, _NOT_USED_, _NOT_USED_, + + /* burst write (offset 0x20 in upm ram) */ + + 0xEECEFC24, 0x103DFC24, 0xE0FBBC00, 0x10F77C00, + 0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC04, 0xFFFFFC05, + + /* init part1 (offset 0x28 in upm ram) */ + + 0xEFFAFC3C, 0x1FF4FC34, 0xEFFCBC34, 0x1FFC3C34, + 0xFFFC3C35, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* refresh (offset 0x30 in upm ram) */ + + 0xEFFEBC0C, 0x1FFD7C04, 0xFFFFFC04, 0xFFFFFC05, + + /* init part2 (offset 0x34 in upm ram) */ + + 0xFFFEBC04, 0xEFFC3CB4, 0x1FFC3C34, 0xFFFC3C34, + 0xFFFC3C34, 0xEFE83CB4, 0x1FB57C35, _NOT_USED_, + + /* exception (offset 0x3C in upm ram) */ + + 0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_, + +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Test ETX ID string (ETX_xxx...) + * + * Return 1 always. + */ + +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char *s = getenv ("serial#"); + char *e; + + puts ("Board: "); + +#ifdef SB_ETX094 + gd->board_type = 0; /* 0 = 2SDRAM-Device */ +#else + gd->board_type = 1; /* 1 = 1SDRAM-Device */ +#endif + + if (!s || strncmp (s, "ETX_", 4)) { + puts ("### No HW ID - assuming ETX_094\n"); + read_hw_vers (); + return (0); + } + + for (e = s; *e; ++e) { + if (*e == ' ') + break; + } + + for (; s < e; ++s) { + putc (*s); + } + putc ('\n'); + + read_hw_vers (); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0, size_b1, size8, size9; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_1BK_4K; /* MPTPR_PTP_DIV32 0x0200 */ + + /* A3(SDRAM)=0 => Bursttype = Sequential + * A2-A0(SDRAM)=010 => Burst length = 4 + * A4-A6(SDRAM)=010 => CasLat=2 + */ + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + + if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + } + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80004128; /* SDRAM bank 0 (CS2) - Init Part 1 */ + memctl->memc_mcr = 0x80004734; /* SDRAM bank 0 (CS2) - Init Part 2 */ + udelay (1); + + if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ + memctl->memc_mcr = 0x80006128; /* SDRAM bank 1 (CS3) - Init Part 1 */ + memctl->memc_mcr = 0x80006734; /* SDRAM bank 1 (CS3) - Init Part 2 */ + udelay (1); + } + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size_b0 = size9; +/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); +/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ + /* + * Check Bank 1 Memory Size + * use current column settings + * [9 column SDRAM may also be used in 8 column mode, + * but then only half the real size will be used.] + */ + size_b1 = + dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); +/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ + } else { + size_b1 = 0; + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /*DIV16 */ + udelay (1000); + } + + /* + * Final mapping: map bigger bank first + */ + if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ + + memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = + (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b0 > 0) { + /* + * Position Bank 0 immediately above Bank 1 + */ + memctl->memc_or2 = + ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + + size_b1; + } else { + unsigned long reg; + + /* + * No bank 0 + * + * invalidate bank + */ + memctl->memc_br2 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + + } else { /* SDRAM Bank 0 is bigger - map first */ + + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b1 > 0) { + /* + * Position Bank 1 immediately above Bank 0 + */ + memctl->memc_or3 = + ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = + ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + + size_b0; + } else { + unsigned long reg; + + /* + * No bank 1 + * + * invalidate bank + */ + memctl->memc_br3 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + } + + udelay (10000); + + return (size_b0 + size_b1); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +/* HW-ID Table (Bits: 2^9;2^7;2^5) */ +#define HW_ID_0 0x0000 +#define HW_ID_1 0x0020 +#define HW_ID_2 0x0080 +#define HW_ID_3 0x00a0 +#define HW_ID_4 0x0200 +#define HW_ID_5 0x0220 +#define HW_ID_6 0x0280 +#define HW_ID_7 0x02a0 + +void read_hw_vers () +{ + unsigned short rd_msk = 0x02A0; + + /* HW-ID pin-definition */ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + immr->im_ioport.iop_pddir &= ~(rd_msk); + immr->im_ioport.iop_pdpar &= ~(rd_msk); + + /* debug printf("State of PD: %x\n",immr->im_ioport.iop_pddat); */ + + /* Check the HW-ID */ + printf ("HW-Version: "); + switch (immr->im_ioport.iop_pddat & rd_msk) { + case HW_ID_0: + printf ("V0.1 - V0.3 / W97238-Q3162-A1-1-2\n"); + break; + case HW_ID_1: + printf ("V0.9 / W50037-Q1-D6-1\n"); + break; + case HW_ID_2: + printf ("NOT USED - assuming ID#2\n"); + break; + case HW_ID_3: + printf ("NOT USED - assuming ID#3\n"); + break; + case HW_ID_4: + printf ("NOT USED - assuming ID#4\n"); + break; + case HW_ID_5: + printf ("NOT USED - assuming ID#5\n"); + break; + case HW_ID_6: + printf ("NOT USED - assuming ID#6\n"); + break; + case HW_ID_7: + printf ("NOT USED - assuming ID#7\n"); + break; + default: + printf ("###Error###\n"); + break; + } +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/etx094/flash.c b/board/etx094/flash.c new file mode 100644 index 0000000..98a7c0c --- /dev/null +++ b/board/etx094/flash.c @@ -0,0 +1,744 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); +#ifdef CONFIG_FLASH_16BIT + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */ +#else + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; +#endif + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + if (size_b1) { + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); +#ifdef CONFIG_FLASH_16BIT + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V | BR_PS_16; +#else + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V; +#endif + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00002000); + } + return; + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ +#ifdef CONFIG_FLASH_16BIT + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; +#else + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; +#endif + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n"); + break; + case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n"); + break; + case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n"); + break; + case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ +#ifdef CONFIG_FLASH_16BIT + vu_short *s_addr = (vu_short*)addr; + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x0090; + value = s_addr[0]; + value = value|(value<<16); +#else + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + addr[0x5555] = 0x00900090; + value = addr[0]; +#endif + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } +#ifdef CONFIG_FLASH_16BIT + value = s_addr[1]; + value = value|(value<<16); +#else + value = addr[1]; /* device ID */ +#endif + + switch (value) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; +#ifdef CONFIG_FLASH_16BIT + info->sector_count = 19; + info->size = 0x00100000; /* => 1 MB */ +#else + info->sector_count = 19; + info->size = 0x00200000; /* => 2 MB */ +#endif + break; + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; +#ifdef CONFIG_FLASH_16BIT + info->sector_count = 35; + info->size = 0x00200000; /* => 2 MB */ +#else + info->sector_count = 35; + info->size = 0x00400000; /* => 4 MB */ +#endif + + break; +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + case SST_ID_xF200A: + info->flash_id += FLASH_SST200A; + info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */ + info->size = 0x00080000; + break; + case SST_ID_xF400A: + info->flash_id += FLASH_SST400A; + info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */ + info->size = 0x00100000; + break; + case SST_ID_xF800A: + info->flash_id += FLASH_SST800A; + info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */ + info->size = 0x00200000; + break; /* => 2 MB */ + case STM_ID_x800AB: + info->flash_id += FLASH_STM800AB; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00002000); + } + } else { /* AMD and Fujitsu types */ + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ +#ifdef CONFIG_FLASH_16BIT + + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; +#else + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; +#endif + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address: + * (A7 .. A0) = 0x02 + * D0 = 1 if protected + */ +#ifdef CONFIG_FLASH_16BIT + s_addr = (volatile unsigned short *)(info->start[i]); + info->protect[i] = s_addr[2] & 1; +#else + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; +#endif + } + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { +#ifdef CONFIG_FLASH_16BIT + s_addr = (volatile unsigned short *)(info->start[0]); + *s_addr = 0x00F0; /* reset bank */ +#else + addr = (volatile unsigned long *)info->start[0]; + *addr = 0x00F000F0; /* reset bank */ +#endif + + } + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect; + ulong start, now, last; +#ifdef CONFIG_FLASH_16BIT + vu_short *s_addr = (vu_short*)addr; +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } +/*#ifndef CONFIG_FLASH_16BIT + ulong type; + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return; + } +#endif*/ + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ +#ifdef CONFIG_FLASH_16BIT + vu_short *s_sect_addr = (vu_short*)(info->start[sect]); +#else + vu_long *sect_addr = (vu_long*)(info->start[sect]); +#endif + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + +#ifdef CONFIG_FLASH_16BIT + + /*printf("\ns_sect_addr=%x",s_sect_addr);*/ + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x0080; + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_sect_addr[0] = 0x0030; +#else + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + addr[0x5555] = 0x00800080; + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + sect_addr[0] = 0x00300030; +#endif + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#ifdef CONFIG_FLASH_16BIT + while ((s_sect_addr[0] & 0x0080) != 0x0080) { +#else + while ((sect_addr[0] & 0x00800080) != 0x00800080) { +#endif + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + } + } + + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; +#ifdef CONFIG_FLASH_16BIT + s_addr[0] = 0x00F0; /* reset bank */ +#else + addr[0] = 0x00F000F0; /* reset bank */ +#endif + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + +#ifdef CONFIG_FLASH_16BIT + vu_short high_data; + vu_short low_data; + vu_short *s_addr = (vu_short*)addr; +#endif + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + +#ifdef CONFIG_FLASH_16BIT + /* Write the 16 higher-bits */ + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + high_data = ((data>>16) & 0x0000ffff); + + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x00A0; + + *((vu_short *)dest) = high_data; + + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + + /* Write the 16 lower-bits */ +#endif + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); +#ifdef CONFIG_FLASH_16BIT + dest += 0x2; + low_data = (data & 0x0000ffff); + + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x00A0; + *((vu_short *)dest) = low_data; + +#else + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + addr[0x5555] = 0x00A000A0; + *((vu_long *)dest) = data; +#endif + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + +#ifdef CONFIG_FLASH_16BIT + while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { +#else + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { +#endif + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds new file mode 100644 index 0000000..c50db8f --- /dev/null +++ b/board/etx094/u-boot.lds @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + cpu/mpc8xx/interrupts.o (.text) + cpu/mpc8xx/serial.o (.text) + cpu/mpc8xx/cpu_init.o (.text) + cpu/mpc8xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/etx094/u-boot.lds.debug b/board/etx094/u-boot.lds.debug new file mode 100644 index 0000000..e4d8b10 --- /dev/null +++ b/board/etx094/u-boot.lds.debug @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + cpu/mpc8xx/interrupts.o (.text) + cpu/mpc8xx/cpu.o (.text) + cpu/mpc8xx/cpu_init.o (.text) + cpu/mpc8xx/speed.o (.text) + cpu/mpc8xx/serial.o (.text) + lib_ppc/extable.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/string.o (.text) + lib_generic/crc32.o (.text) + common/dlmalloc.o (.text) + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/evb4510/Makefile b/board/evb4510/Makefile new file mode 100644 index 0000000..10850a9 --- /dev/null +++ b/board/evb4510/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := evb4510.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/evb4510/config.mk b/board/evb4510/config.mk new file mode 100644 index 0000000..4d1a019 --- /dev/null +++ b/board/evb4510/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (c) 2004 Cucy Systems (http://www.cucy.com) +# Curt Brune +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x007d0000 diff --git a/board/evb4510/evb4510.c b/board/evb4510/evb4510.c new file mode 100644 index 0000000..0008e5a --- /dev/null +++ b/board/evb4510/evb4510.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_EVB4510 + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + icache_enable(); + + /* address for the kernel command line */ + gd->bd->bi_boot_params = 0x800; + + /* enable board LEDs for output */ + PUT_REG( REG_IOPDATA, 0x0); + PUT_REG( REG_IOPMODE, 0xFFFF); + PUT_REG( REG_IOPDATA, 0xFF); + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +#if CONFIG_NR_DRAM_BANKS == 2 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif + return 0; +} + +#endif diff --git a/board/evb4510/flash.c b/board/evb4510/flash.c new file mode 100644 index 0000000..aff92f9 --- /dev/null +++ b/board/evb4510/flash.c @@ -0,0 +1,539 @@ +/* + * + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +typedef enum { + FLASH_DEV_U9_512KB = 0, + FLASH_DEV_U7_2MB = 1 +} FLASH_DEV; + +#define FLASH_DQ7 (0x80) +#define FLASH_DQ5 (0x20) + +#define PROG_ADDR (0xAAA) +#define SETUP_ADDR (0xAAA) +#define ID_ADDR (0xAAA) +#define UNLOCK_ADDR1 (0xAAA) +#define UNLOCK_ADDR2 (0x555) + +#define UNLOCK_CMD1 (0xAA) +#define UNLOCK_CMD2 (0x55) +#define ERASE_SUSPEND_CMD (0xB0) +#define ERASE_RESUME_CMD (0x30) +#define RESET_CMD (0xF0) +#define ID_CMD (0x90) +#define SELECT_CMD (0x90) +#define CHIPERASE_CMD (0x10) +#define BYPASS_CMD (0x20) +#define SECERASE_CMD (0x30) +#define PROG_CMD (0xa0) +#define SETUP_CMD (0x80) + +#if 0 +#define WRITE_UNLOCK(addr) { \ + PUT__U8( addr + UNLOCK_ADDR1, UNLOCK_CMD1); \ + PUT__U8( addr + UNLOCK_ADDR2, UNLOCK_CMD2); \ +} + +/* auto select command */ +#define CMD_ID(addr) WRITE_UNLOCK(addr); { \ + PUT__U8( addr + ID_ADDR, ID_CMD); \ +} + +#define CMD_RESET(addr) WRITE_UNLOCK(addr); { \ + PUT__U8( addr + ID_ADDR, RESET_CMD); \ +} + +#define CMD_ERASE_SEC(base, addr) WRITE_UNLOCK(base); \ + PUT__U8( base + SETUP_ADDR, SETUP_CMD); \ + WRITE_UNLOCK(base); \ + PUT__U8( addr, SECERASE_CMD); + +#define CMD_ERASE_CHIP(base) WRITE_UNLOCK(base); \ + PUT__U8( base + SETUP_ADDR, SETUP_CMD); \ + WRITE_UNLOCK(base); \ + PUT__U8( base + SETUP_ADDR, CHIPERASE_CMD); + +/* prepare for bypass programming */ +#define CMD_UNLOCK_BYPASS(addr) WRITE_UNLOCK(addr); { \ + PUT__U8( addr + ID_ADDR, 0x20); \ +} + +/* terminate bypass programming */ +#define CMD_BYPASS_RESET(addr) { \ + PUT__U8(addr, 0x90); \ + PUT__U8(addr, 0x00); \ +} +#endif + +inline static void FLASH_CMD_UNLOCK (FLASH_DEV dev, u32 base) +{ + switch (dev) { + case FLASH_DEV_U7_2MB: + PUT__U8 (base + 0xAAA, 0xAA); + PUT__U8 (base + 0x555, 0x55); + break; + case FLASH_DEV_U9_512KB: + PUT__U8 (base + 0x555, 0xAA); + PUT__U8 (base + 0x2AA, 0x55); + break; + } +} + +inline static void FLASH_CMD_SELECT (FLASH_DEV dev, u32 base) +{ + switch (dev) { + case FLASH_DEV_U7_2MB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0xAAA, SELECT_CMD); + break; + case FLASH_DEV_U9_512KB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0x555, SELECT_CMD); + break; + } +} + +inline static void FLASH_CMD_RESET (FLASH_DEV dev, u32 base) +{ + switch (dev) { + case FLASH_DEV_U7_2MB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0xAAA, RESET_CMD); + break; + case FLASH_DEV_U9_512KB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0x555, RESET_CMD); + break; + } +} + +inline static void FLASH_CMD_ERASE_SEC (FLASH_DEV dev, u32 base, u32 addr) +{ + switch (dev) { + case FLASH_DEV_U7_2MB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0xAAA, SETUP_CMD); + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (addr, SECERASE_CMD); + break; + case FLASH_DEV_U9_512KB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0x555, SETUP_CMD); + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (addr, SECERASE_CMD); + break; + } +} + +inline static void FLASH_CMD_ERASE_CHIP (FLASH_DEV dev, u32 base) +{ + switch (dev) { + case FLASH_DEV_U7_2MB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0xAAA, SETUP_CMD); + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base, CHIPERASE_CMD); + break; + case FLASH_DEV_U9_512KB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0x555, SETUP_CMD); + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base, CHIPERASE_CMD); + break; + } +} + +inline static void FLASH_CMD_UNLOCK_BYPASS (FLASH_DEV dev, u32 base) +{ + switch (dev) { + case FLASH_DEV_U7_2MB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0xAAA, BYPASS_CMD); + break; + case FLASH_DEV_U9_512KB: + FLASH_CMD_UNLOCK (dev, base); + PUT__U8 (base + 0x555, BYPASS_CMD); + break; + } +} + +inline static void FLASH_CMD_BYPASS_RESET (FLASH_DEV dev, u32 base) +{ + PUT__U8 (base, SELECT_CMD); + PUT__U8 (base, 0x0); +} + +/* poll for flash command completion */ +static u16 _flash_poll (FLASH_DEV dev, u32 addr, u16 data, ulong timeOut) +{ + u32 done = 0; + ulong t0; + + u16 error = 0; + volatile u16 flashData; + + data = data & 0xFF; + t0 = get_timer (0); + while (get_timer (t0) < timeOut) { + /* for( i = 0; i < POLL_LOOPS; i++) { */ + /* Read the Data */ + flashData = GET__U8 (addr); + + /* FLASH_DQ7 = Data? */ + if ((flashData & FLASH_DQ7) == (data & FLASH_DQ7)) { + done = 1; + break; + } + + /* Check Timeout (FLASH_DQ5==1) */ + if (flashData & FLASH_DQ5) { + /* Read the Data */ + flashData = GET__U8 (addr); + + /* FLASH_DQ7 = Data? */ + if (!((flashData & FLASH_DQ7) == (data & FLASH_DQ7))) { + printf ("_flash_poll(): FLASH_DQ7 & flashData not equal to write value\n"); + error = ERR_PROG_ERROR; + } + FLASH_CMD_RESET (dev, addr); + done = 1; + break; + } + /* spin delay */ + udelay (10); + } + + + /* error update */ + if (!done) { + printf ("_flash_poll(): Timeout\n"); + error = ERR_TIMOUT; + } + + /* Check the data */ + if (!error) { + /* Read the Data */ + flashData = GET__U8 (addr); + if (flashData != data) { + error = ERR_PROG_ERROR; + printf ("_flash_poll(): flashData(0x%04x) not equal to data(0x%04x)\n", + flashData, data); + } + } + + return error; +} + +/*----------------------------------------------------------------------- + */ +static int _flash_check_protection (flash_info_t * info, int s_first, int s_last) +{ + int sect, prot = 0; + + for (sect = s_first; sect <= s_last; sect++) + if (info->protect[sect]) { + printf (" Flash sector %d protected.\n", sect); + prot++; + } + return prot; +} + +static int _detectFlash (FLASH_DEV dev, u32 base, u8 venId, u8 devId) +{ + + u32 baseAddr = base | CACHE_DISABLE_MASK; + u8 vendorId, deviceId; + + /* printf(__FUNCTION__"(): detecting flash @ 0x%08x\n", base); */ + + /* Send auto select command and read manufacturer info */ + FLASH_CMD_SELECT (dev, baseAddr); + vendorId = GET__U8 (baseAddr); + FLASH_CMD_RESET (dev, baseAddr); + + /* Send auto select command and read device info */ + FLASH_CMD_SELECT (dev, baseAddr); + + if (dev == FLASH_DEV_U7_2MB) { + deviceId = GET__U8 (baseAddr + 2); + } else if (dev == FLASH_DEV_U9_512KB) { + deviceId = GET__U8 (baseAddr + 1); + } else { + return 0; + } + + FLASH_CMD_RESET (dev, baseAddr); + + /* printf (__FUNCTION__"(): found vendorId 0x%04x, deviceId 0x%04x\n", + vendorId, deviceId); + */ + + return (vendorId == venId) && (deviceId == devId); + +} + +/****************************************************************************** + * + * Public u-boot interface functions below + * + *****************************************************************************/ + +/*************************************************************************** + * + * Flash initialization + * + * This board has two banks of flash, but the base addresses depend on + * how the board is jumpered. + * + * The two flash types are: + * + * AMD Am29LV160DB (2MB) sectors layout 16KB, 2x8KB, 32KB, 31x64KB + * + * AMD Am29LV040B (512KB) sectors: 8x64KB + *****************************************************************************/ + +unsigned long flash_init (void) +{ + flash_info_t *info; + u16 i; + u32 flashtest; + s16 amd160 = -1; + u32 amd160base = 0; + +#if CFG_MAX_FLASH_BANKS == 2 + s16 amd040 = -1; + u32 amd040base = 0; +#endif + + /* configure PHYS_FLASH_1 */ + if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_1, 0x1, 0x49)) { + amd160 = 0; + amd160base = PHYS_FLASH_1; +#if CFG_MAX_FLASH_BANKS == 1 + } +#else + if (_detectFlash + (FLASH_DEV_U9_512KB, PHYS_FLASH_2, 0x1, 0x4F)) { + amd040 = 1; + amd040base = PHYS_FLASH_2; + } else { + printf (__FUNCTION__ + "(): Unable to detect PHYS_FLASH_2: 0x%08x\n", + PHYS_FLASH_2); + } + } else if (_detectFlash (FLASH_DEV_U9_512KB, PHYS_FLASH_1, 0x1, 0x4F)) { + amd040 = 0; + amd040base = PHYS_FLASH_1; + if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_2, 0x1, 0x49)) { + amd160 = 1; + amd160base = PHYS_FLASH_2; + } else { + printf (__FUNCTION__ + "(): Unable to detect PHYS_FLASH_2: 0x%08x\n", + PHYS_FLASH_2); + } + } +#endif + else { + printf ("flash_init(): Unable to detect PHYS_FLASH_1: 0x%08x\n", + PHYS_FLASH_1); + } + + /* Configure AMD Am29LV160DB (2MB) */ + info = &flash_info[amd160]; + info->flash_id = FLASH_DEV_U7_2MB; + info->sector_count = 35; + info->size = 2 * 1024 * 1024; /* 2MB */ + /* 1*16K Boot Block + 2*8K Parameter Block + 1*32K Small Main Block */ + info->start[0] = amd160base; + info->start[1] = amd160base + 0x4000; + info->start[2] = amd160base + 0x6000; + info->start[3] = amd160base + 0x8000; + for (i = 1; i < info->sector_count; i++) + info->start[3 + i] = amd160base + i * (64 * 1024); + + for (i = 0; i < info->sector_count; i++) { + /* Write auto select command sequence and query sector protection */ + FLASH_CMD_SELECT (info->flash_id, + info->start[i] | CACHE_DISABLE_MASK); + flashtest = + GET__U8 (((info->start[i] + 4) | CACHE_DISABLE_MASK)); + FLASH_CMD_RESET (info->flash_id, + amd160base | CACHE_DISABLE_MASK); + info->protect[i] = (flashtest & 0x0001); + } + + /* + * protect monitor and environment sectors in 2MB flash + */ + flash_protect (FLAG_PROTECT_SET, + amd160base, amd160base + monitor_flash_len - 1, info); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, info); + +#if CFG_MAX_FLASH_BANKS == 2 + /* Configure AMD Am29LV040B (512KB) */ + info = &flash_info[amd040]; + info->flash_id = FLASH_DEV_U9_512KB; + info->sector_count = 8; + info->size = 512 * 1024; /* 512KB, 8 x 64KB */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = amd040base + i * (64 * 1024); + /* Write auto select command sequence and query sector protection */ + FLASH_CMD_SELECT (info->flash_id, + info->start[i] | CACHE_DISABLE_MASK); + flashtest = + GET__U8 (((info->start[i] + 2) | CACHE_DISABLE_MASK)); + FLASH_CMD_RESET (info->flash_id, + amd040base | CACHE_DISABLE_MASK); + info->protect[i] = (flashtest & 0x0001); + } +#endif + + return flash_info[0].size +#if CFG_MAX_FLASH_BANKS == 2 + + flash_info[1].size +#endif + ; +} + +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_DEV_U7_2MB) { + printf ("AMD Am29LV160DB (2MB) 16KB,2x8KB,32KB,31x64KB\n"); + } else if (info->flash_id == FLASH_DEV_U9_512KB) { + printf ("AMD Am29LV040B (512KB) 8x64KB\n"); + } else { + printf ("Unknown flash_id ...\n"); + return; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 4) == 0) + printf ("\n "); + printf (" S%02d @ 0x%08lX%s", i, + info->start[i], info->protect[i] ? " !" : " "); + } + printf ("\n"); +} + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + u16 i, error = 0; + + printf ("\n"); + + /* check flash protection bits */ + if (_flash_check_protection (info, s_first, s_last)) { + printf (" Flash erase aborted due to protected sectors\n"); + return ERR_PROTECTED; + } + + if ((s_first < info->sector_count) && (s_first <= s_last)) { + for (i = s_first; i <= s_last && !error; i++) { + printf (" Erasing Sector %d @ 0x%08lx ... ", i, + info->start[i]); + /* bypass the cache to access the flash memory */ + FLASH_CMD_ERASE_SEC (info->flash_id, + (info-> + start[0] | CACHE_DISABLE_MASK), + (info-> + start[i] | CACHE_DISABLE_MASK)); + /* look for sector to become 0xFF after erase */ + error = _flash_poll (info->flash_id, + info-> + start[i] | CACHE_DISABLE_MASK, + 0xFF, CFG_FLASH_ERASE_TOUT); + FLASH_CMD_RESET (info->flash_id, + (info-> + start[0] | CACHE_DISABLE_MASK)); + printf ("done\n"); + if (error) { + break; + } + } + } else + error = ERR_INVAL; + + return error; +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + u16 error = 0, i; + u32 n; + u8 *bp, *bps; + + /* Write Setup */ + /* bypass the cache to access the flash memory */ + FLASH_CMD_UNLOCK_BYPASS (info->flash_id, + (info->start[0] | CACHE_DISABLE_MASK)); + + /* Write the Data to Flash */ + + bp = (u8 *) (addr | CACHE_DISABLE_MASK); + bps = (u8 *) src; + + for (n = 0; n < cnt && !error; n++, bp++, bps++) { + + if (!(n % (cnt / 15))) { + printf ("."); + } + + /* write the flash command for flash memory */ + *bp = 0xA0; + + /* Write the data */ + *bp = *bps; + + /* Check if the write is done */ + for (i = 0; i < 0xff; i++); + error = _flash_poll (info->flash_id, (u32) bp, *bps, + CFG_FLASH_WRITE_TOUT); + if (error) { + return error; + } + } + + /* Reset the Flash Mode to read */ + FLASH_CMD_BYPASS_RESET (info->flash_id, info->start[0]); + + printf (" "); + + return error; +} diff --git a/board/evb4510/lowlevel_init.S b/board/evb4510/lowlevel_init.S new file mode 100644 index 0000000..7184d72 --- /dev/null +++ b/board/evb4510/lowlevel_init.S @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include + +/*********************************************************************** + * Configure Memory Map + * + * This memory map allows us to relocate from FLASH to SRAM. After + * power-on reset the CPU only knows about the FLASH memory at address + * 0x00000000. After lowlevel_init completes the memory map will be: + * + * Memory Addr + * 0x00000000 + * to 8MB SRAM (U5) -- 8MB Map + * 0x00800000 + * + * 0x01000000 + * to 2MB Flash @ 0x00000000 (U7) -- 2MB Map + * 0x01200000 + * + * 0x02000000 + * to 512KB Flash @ 0x02000000 (U9) -- 2MB Map + * 0x02080000 + * + * Load all 12 memory registers with the STMIA instruction since + * memory access is disabled once these registers are written. The + * last register written re-enables memory access. For more info see + * the user's manual for the S3C4510B, available from Samsung's web + * site. Search for part number "S3C4510B". + * + ***********************************************************************/ + +.globl lowlevel_init +lowlevel_init: + + /* preserve the temp register (r12 AKA ip) and remap it. */ + ldr r1, =SRAM_BASE+0xC + add r0, r12, #0x01000000 + str r0, [r1] + + /* remap the link register for when we return */ + add lr, lr, #0x01000000 + + /* store a short program in the on chip SRAM, which is + * unaffected when remapping memory. Note the cache must be + * disabled for the on chip SRAM to be available. + */ + ldr r1, =SRAM_BASE + ldr r0, =0xe8801ffe /* stmia r0, {r1-r12} */ + str r0, [r1] + add r1, r1, #4 + ldr r0, =0xe59fc000 /* ldr r12, [pc, #0] */ + str r0, [r1] + add r1, r1, #4 + ldr r0, =0xe1a0f00e /* mov pc, lr */ + str r0, [r1] + + adr r0, memory_map_data + ldmia r0, {r1-r12} + ldr r0, =REG_EXTDBWTH + + ldr pc, =SRAM_BASE + +.globl reset_cpu +reset_cpu: + /* + * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to + * address 0x0. We accomplish this by storing a few + * instructions into the on chip SRAM (8KB) and run from + * there. Note the cache must be disabled for the on chip + * SRAM to be available. + * + * load r2 with REG_ROMCON0 + * load r3 with 0x12040060 configure FLASH bank 0 @ 0x00000000 + * load r4 with REG_DRAMCON0 + * load r5 with 0x08000380 configure RAM bank 0 @ 0x01000000 + * load r6 with REG_REFEXTCON + * load r7 with 0x9c218360 + * load r8 with 0x0 + * store str r3,[r2] @ SRAM_BASE + * store str r5,[r4] @ SRAM_BASE + 0x4 + * store str r7,[r6] @ SRAM_BASE + 0x8 + * store mov pc,r8 @ SRAM_BASE + 0xC + * mov pc, SRAM_BASE + * + */ + + /* disable cache */ + ldr r0, =REG_SYSCFG + ldr r1, =0x83ffffa0 /* cache-disabled */ + str r1, [r0] + + ldr r2, =REG_ROMCON0 + ldr r3, =0x02000060 /* Bank0 2MB FLASH @ 0x00000000 */ + ldr r4, =REG_DRAMCON0 + ldr r5, =0x18040380 /* DRAM0 8MB SRAM @ 0x01000000 */ + ldr r6, =REG_REFEXTCON + ldr r7, =0xce278360 + ldr r8, =0x00000000 + ldr r1, =SRAM_BASE + ldr r0, =0xe5823000 /* str r3, [r2] */ + str r0, [r1] + ldr r1, =SRAM_BASE+4 + ldr r0, =0xe5845000 /* str r5, [r4] */ + str r0, [r1] + ldr r1, =SRAM_BASE+8 + ldr r0, =0xe5867000 /* str r7, [r6] */ + str r0, [r1] + ldr r1, =SRAM_BASE+0xC + ldr r0, =0xe1a0f008 /* mov pc, r8 */ + str r0, [r1] + ldr r1, =SRAM_BASE + mov pc, r1 + + /* never return */ + +/************************************************************************ + * Below are twelve 32-bit values for the twelve memory registers of + * the system manager, starting with register REG_EXTDBWTH. + ***********************************************************************/ +memory_map_data: + .long 0x00f03005 /* memory widths */ + .long 0x12040060 /* Bank0 2MB FLASH @ 0x01000000 */ + .long 0x22080060 /* Bank1 512KB FLASH @ 0x02000000 */ + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + .long 0x08000380 /* DRAM0 8MB SRAM @ 0x00000000 */ + .long 0x00000000 + .long 0x00000000 + .long 0x00000000 + .long 0x9c218360 /* enable memory */ diff --git a/board/evb4510/u-boot.lds b/board/evb4510/u-boot.lds new file mode 100644 index 0000000..5b70a40 --- /dev/null +++ b/board/evb4510/u-boot.lds @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/board/evb64260/64260.h b/board/evb64260/64260.h new file mode 100644 index 0000000..d106ced --- /dev/null +++ b/board/evb64260/64260.h @@ -0,0 +1,31 @@ +#ifndef __64260_H__ +#define __64260_H__ + +/* CPU Configuration bits */ +#define CPU_CONF_ADDR_MISS_EN (1 << 8) +#define CPU_CONF_AACK_DELAY (1 << 11) +#define CPU_CONF_ENDIANESS (1 << 12) +#define CPU_CONF_PIPELINE (1 << 13) +#define CPU_CONF_TA_DELAY (1 << 15) +#define CPU_CONF_RD_OOO (1 << 16) +#define CPU_CONF_STOP_RETRY (1 << 17) +#define CPU_CONF_MULTI_DECODE (1 << 18) +#define CPU_CONF_DP_VALID (1 << 19) +#define CPU_CONF_PERR_PROP (1 << 22) +#define CPU_CONF_FAST_CLK (1 << 23) +#define CPU_CONF_AACK_DELAY_2 (1 << 25) +#define CPU_CONF_AP_VALID (1 << 26) +#define CPU_CONF_REMAP_WR_DIS (1 << 27) +#define CPU_CONF_CONF_SB_DIS (1 << 28) +#define CPU_CONF_IO_SB_DIS (1 << 29) +#define CPU_CONF_CLK_SYNC (1 << 30) + +/* CPU Master Control bits */ +#define CPU_MAST_CTL_ARB_EN (1 << 8) +#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) +#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) +#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) +#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) +#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) + +#endif /* __64260_H__ */ diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile new file mode 100644 index 0000000..c493d6c --- /dev/null +++ b/board/evb64260/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001 +# Josh Huber , Mission Critical Linux, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +SOBJS = misc.o +OBJS = $(BOARD).o flash.o serial.o memory.o pci.o \ + eth.o eth_addrtbl.o mpsc.o i2c.o \ + sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o + + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt new file mode 100644 index 0000000..391d49a --- /dev/null +++ b/board/evb64260/bootseq.txt @@ -0,0 +1,94 @@ +(cpu/mpc7xxx/start.S) + +start: + b boot_cold + +start_warm: + b boot_warm + + +boot_cold: +boot_warm: + clear bats + init l2 (if enabled) + init altivec (if enabled) + invalidate l2 (if enabled) + setup bats (from defines in config_EVB) + enable_addr_trans: (if MMU enabled) + enable MSR_IR and MSR_DR + jump to in_flash + +in_flash: + enable l1 dcache + gal_low_init: (board/evb64260/sdram_init.S) + config SDRAM (CFG, TIMING, DECODE) + init scratch regs (810 + 814) + + detect DIMM0 (bank 0 only) + config SDRAM_PARA0 to 256/512Mbit + bl sdram_op_mode + detect bank0 width + write scratch reg 810 + config SDRAM_PARA0 with results + config SDRAM_PARA1 with results + + detect DIMM1 (bank 2 only) + config SDRAM_PARA2 to 256/512Mbit + detect bank2 width + write scratch reg 814 + config SDRAM_PARA2 with results + config SDRAM_PARA3 with results + + setup device bus timings/width + setup boot device timings/width + + setup CPU_CONF (0x0) + setup cpu master control register 0x160 + setup PCI0 TIMEOUT + setup PCI1 TIMEOUT + setup PCI0 BAR + setup PCI1 BAR + + setup MPP control 0-3 + setup GPP level control + setup Serial ports multiplex + + setup stack pointer (r1) + setup GOT + call cpu_init_f + debug leds + board_init_f: (common/board.c) + board_early_init_f: + remap gt regs? + map PCI mem/io + map device space + clear out interupts + init_timebase + env_init + serial_init + console_init_f + display_options + initdram: (board/evb64260/evb64260.c) + detect memory + for each bank: + dram_size() + setup PCI slave memory mappings + setup SCS + setup monitor + alloc board info struct + init bd struct + relocate_code: (cpu/mpc7xxx/start.S) + copy,got,clearbss + board_init_r(bd, dest_addr) (common/board.c) + setup bd function pointers + trap_init + flash_init: (board/evb64260/flash.c) + setup bd flash info + cpu_init_r: (cpu/mpc7xxx/cpu_init.c) + nothing + mem_malloc_init + malloc_bin_reloc + spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + env_relocated + misc_init_r(bd): (board/evb64260/evb64260.c) + mpsc_init2 diff --git a/board/evb64260/config.mk b/board/evb64260/config.mk new file mode 100644 index 0000000..0646a3e --- /dev/null +++ b/board/evb64260/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Josh Huber , Mission Critical Linux, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EVB64260 boards +# + +TEXT_BASE = 0xfff00000 diff --git a/board/evb64260/ecctest.c b/board/evb64260/ecctest.c new file mode 100644 index 0000000..5d3679a --- /dev/null +++ b/board/evb64260/ecctest.c @@ -0,0 +1,111 @@ +indent: Standard input:27: Warning:old style assignment ambiguity in "=*". Assuming "= *" + +#ifdef ECC_TEST +static inline void ecc_off (void) +{ + *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000; +} + +static inline void ecc_on (void) +{ + *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000; +} + +static int putshex (const char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) { + printf ("%02x", buf[i]); + } + return 0; +} + +static int char_memcpy (void *d, const void *s, int len) +{ + int i; + char *cd = d; + const char *cs = s; + + for (i = 0; i < len; i++) { + *(cd++) = *(cs++); + } + return 0; +} + +static int memory_test (char *buf) +{ + const char src[][16] = { + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}, + {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}, + {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}, + {0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, + 0x08, 0x08, 0x08, 0x08, 0x08, 0x08}, + {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, + {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20}, + {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}, + {0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}, + {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55}, + {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}, + {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} + }; + const int foo[] = { 0 }; + int i, j, a; + + printf ("\ntest @ %d %p\n", foo[0], buf); + for (i = 0; i < 12; i++) { + for (a = 0; a < 8; a++) { + const char *s = src[i] + a; + int align = (unsigned) (s) & 0x7; + + /* ecc_off(); */ + memcpy (buf, s, 8); + /* ecc_on(); */ + putshex (s, 8); + if (memcmp (buf, s, 8)) { + putc ('\n'); + putshex (buf, 8); + printf (" [FAIL] (%p) align=%d\n", s, align); + for (j = 0; j < 8; j++) { + s[j] == buf[j] ? puts (" ") : + printf ("%02x", + (s[j]) ^ (buf[j])); + } + putc ('\n'); + } else { + printf (" [PASS] (%p) align=%d\n", s, align); + } + /* ecc_off(); */ + char_memcpy (buf, s, 8); + /* ecc_on(); */ + putshex (s, 8); + if (memcmp (buf, s, 8)) { + putc ('\n'); + putshex (buf, 8); + printf (" [FAIL] (%p) align=%d\n", s, align); + for (j = 0; j < 8; j++) { + s[j] == buf[j] ? puts (" ") : + printf ("%02x", + (s[j]) ^ (buf[j])); + } + putc ('\n'); + } else { + printf (" [PASS] (%p) align=%d\n", s, align); + } + } + } + + return 0; +} +#endif diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c new file mode 100644 index 0000000..eafa48b --- /dev/null +++ b/board/evb64260/eth.c @@ -0,0 +1,807 @@ +/************************************************************************** +Etherboot - BOOTP/TFTP Bootstrap Program +Skeleton NIC driver for Etherboot +***************************************************************************/ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +/* + * This file is a modified version from the Galileo polled mode + * network driver for the ethernet contained within the GT64260 + * chip. It has been modified to fit into the U-Boot framework, from + * the original (etherboot) setup. Also, additional cleanup and features + * were added. + * + * - Josh Huber + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "eth.h" +#include "eth_addrtbl.h" + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) + +#define GT6426x_ETH_BUF_SIZE 1536 + +/* if you like verbose output, turn this on! */ +#undef DEBUG + +/* Restart autoneg if we detect link is up on phy init. */ + +/* + * The GT doc's say that after Rst is deasserted, and the PHY + * reports autoneg complete, it runs through its autoneg + * procedures. This doesn't seem to be the case for MII + * PHY's. To work around this check for link up && autoneg + * complete when initilizing the port. If they are both set, + * then restart PHY autoneg. Of course, it may be something + * completly different. + */ +#ifdef CONFIG_ETHER_PORT_MII +# define RESTART_AUTONEG +#endif + +/* do this if you dont want to use snooping */ +#define USE_SOFTWARE_CACHE_MANAGEMENT + +#ifdef USE_SOFTWARE_CACHE_MANAGEMENT +#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} +#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} +#else +/* bummer - w/o flush, nothing works, even with snooping - FIXME */ +/* #define FLUSH_DCACHE(a,b) */ +#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) +#define INVALIDATE_DCACHE(a,b) +#endif +struct eth_dev_s { + eth0_tx_desc_single *eth_tx_desc; + eth0_rx_desc_single *eth_rx_desc; + char *eth_tx_buffer; + char *eth_rx_buffer[NR]; + int tdn, rdn; + int dev; + unsigned int reg_base; +}; + + +#ifdef CONFIG_INTEL_LXT97X +/* for intel LXT972 */ +static const char ether_port_phy_addr[3]={0,1,2}; +#else +static const char ether_port_phy_addr[3]={4,5,6}; +#endif + +/* MII PHY access routines are common for all i/f, use gal_ent0 */ +#define GT6426x_MII_DEVNAME "gal_enet0" + +int gt6426x_miiphy_read(char *devname, unsigned char phy, + unsigned char reg, unsigned short *val); + +static inline unsigned short +miiphy_read_ret(unsigned short phy, unsigned short reg) +{ + unsigned short val; + gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val); + return val; +} + + +/************************************************************************** +RESET - Reset adapter +***************************************************************************/ +void +gt6426x_eth_reset(void *v) +{ + /* we should do something here... + struct eth_device *wp = (struct eth_device *)v; + struct eth_dev_s *p = wp->priv; + */ + + printf ("RESET\n"); + /* put the card in its initial state */ +} + +static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr) +{ +#ifdef DEBUG + printf("SMI interrupt: "); + + if(icr&0x20000000) { + printf("SMI done\n"); + } +#endif + + if(icr&0x10000000) { + unsigned int psr; + psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); +#ifdef DEBUG + printf("PHY state change:\n" + " GT:%s:%s:%s:%s\n", + psr&1?"100":" 10", + psr&8?" Link":"nLink", + psr&2?"FD":"HD", + psr&4?" FC":"nFC"); + +#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */ + { + unsigned short mii_11; + mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11); + + printf(" mii:%s:%s:%s:%s %s:%s %s\n", + mii_11&(1<<14)?"100":" 10", + mii_11&(1<<10)?" Link":"nLink", + mii_11&(1<<9)?"FD":"HD", + mii_11&(1<<4)?" FC":"nFC", + + mii_11&(1<<7)?"ANc":"ANnc", + mii_11&(1<<8)?"AN":"Manual", + "" + ); + } +#endif /* CONFIG_INTEL_LXT97X */ +#endif /* DEBUG */ + } +} + +static int +gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr) +{ + int eth_len=0; + char *eth_data; + + eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)]; + + INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); + + if (rx->command_status & 0x80000000) { + return 0; /* No packet received */ + } + + eth_len = (unsigned int) + (rx->buff_size_byte_count) & 0x0000ffff; + eth_data = (char *) p->eth_rx_buffer[p->rdn]; + +#ifdef DEBUG + if (eth_len) { + printf ("%s: Recived %d byte Packet @ 0x%p\n", + __FUNCTION__, eth_len, eth_data); + } +#endif + /* + * packet is now in: + * eth0_rx_buffer[RDN_ETH0]; + */ + + /* let the upper layer handle the packet */ + NetReceive ((uchar *)eth_data, eth_len); + + rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; + + + /* GT96100 Owner */ + rx->command_status = 0x80000000; + + FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); + + p->rdn ++; + if (p->rdn == NR) {p->rdn = 0;} + + sync(); + + /* Start Rx*/ + GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080); + +#ifdef DEBUG + { + int i; + for (i=0;i<12;i++) { + printf(" %02x", eth_data[i]); + } + } + printf(": %d bytes\n", eth_len); +#endif + INVALIDATE_DCACHE((unsigned int)eth_data, + (unsigned int)eth_data+eth_len); + return eth_len; +} + +/************************************************************************** +POLL - look for an rx frame, handle other conditions +***************************************************************************/ +int +gt6426x_eth_poll(void *v) +{ + struct eth_device *wp = (struct eth_device *)v; + struct eth_dev_s *p = wp->priv; + unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base); + + if(icr) { + GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0); +#ifdef DEBUG + printf("poll got ICR %08x\n", icr); +#endif + /* SMI done or PHY state change*/ + if(icr&0x30000000) gt6426x_handle_SMI(p, icr); + } + /* always process. We aren't using RX interrupts */ + return gt6426x_eth_receive(p, icr); +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +int +gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s) +{ + struct eth_device *wp = (struct eth_device *)v; + struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv; +#ifdef DEBUG + unsigned int old_command_stat,old_psr; +#endif + eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn]; + + /* wait for tx to be ready */ + INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); + while (tx->command_status & 0x80000000) { + int i; + for(i=0;i<1000;i++); + INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); + } + + GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base, + (unsigned int)tx); + +#ifdef DEBUG + printf("copying to tx_buffer [%p], length %x, desc = %p\n", + dev->eth_tx_buffer, s, dev->eth_tx_desc); +#endif + memcpy(dev->eth_tx_buffer, (char *) p, s); + + tx->buff_pointer = (uchar *)dev->eth_tx_buffer; + tx->bytecount_reserved = ((__u16)s) << 16; + + /* 31 - own + * 22 - gencrc + * 18:16 - pad, last, first */ + tx->command_status = (1<<31) | (1<<22) | (7<<16); +#if 0 + /* FEr #18 */ + tx->next_desc = NULL; +#else + tx->next_desc = + (struct eth0_tx_desc_struct *) + &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved; + + /* cpu owned */ + dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */ +#endif + +#ifdef DEBUG + old_command_stat=tx->command_status, + old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); +#endif + + FLUSH_DCACHE((unsigned int)tx, + (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]); + + FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s); + + GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000); + +#ifdef DEBUG + { + unsigned int command_stat=0; + printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr); + /* wait for tx to be ready */ + do { + unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); + command_stat=tx->command_status; + if(command_stat!=old_command_stat || psr !=old_psr) { + printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr); + old_command_stat = command_stat; + old_psr = psr; + } + /* gt6426x_eth0_poll(); */ + } while (command_stat & 0x80000000); + + printf("sent %d byte frame\n", s); + + if((command_stat & (3<<15)) == 3) { + printf("frame had error (stat=%08x)\n", command_stat); + } + } +#endif + return 0; +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +void +gt6426x_eth_disable(void *v) +{ + struct eth_device *wp = (struct eth_device *)v; + struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; + + GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000); +} + +/************************************************************************** +MII utilities - write: write to an MII register via SMI +***************************************************************************/ +int +gt6426x_miiphy_write(char *devname, unsigned char phy, + unsigned char reg, unsigned short data) +{ + unsigned int temp= (reg<<21) | (phy<<16) | data; + + while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ + + GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); + return 0; +} + +/************************************************************************** +MII utilities - read: read from an MII register via SMI +***************************************************************************/ +int +gt6426x_miiphy_read(char *devname, unsigned char phy, + unsigned char reg, unsigned short *val) +{ + unsigned int temp= (reg<<21) | (phy<<16) | 1<<26; + + while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ + + GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); + + while(1) { + temp=GTREGREAD(ETHERNET_SMI_REGISTER); + if(temp & (1<<27)) break; /* wait for ReadValid */ + } + *val = temp & 0xffff; + + return 0; +} + +#ifdef DEBUG +/************************************************************************** +MII utilities - dump mii registers +***************************************************************************/ +static void +gt6426x_dump_mii(bd_t *bis, unsigned short phy) +{ + printf("mii reg 0 - 3: %04x %04x %04x %04x\n", + miiphy_read_ret(phy, 0x0), + miiphy_read_ret(phy, 0x1), + miiphy_read_ret(phy, 0x2), + miiphy_read_ret(phy, 0x3) + ); + printf(" 4 - 7: %04x %04x %04x %04x\n", + miiphy_read_ret(phy, 0x4), + miiphy_read_ret(phy, 0x5), + miiphy_read_ret(phy, 0x6), + miiphy_read_ret(phy, 0x7) + ); + printf(" 8: %04x\n", + miiphy_read_ret(phy, 0x8) + ); + printf(" 16-19: %04x %04x %04x %04x\n", + miiphy_read_ret(phy, 0x10), + miiphy_read_ret(phy, 0x11), + miiphy_read_ret(phy, 0x12), + miiphy_read_ret(phy, 0x13) + ); + printf(" 20,30: %04x %04x\n", + miiphy_read_ret(phy, 20), + miiphy_read_ret(phy, 30) + ); +} +#endif + +#ifdef RESTART_AUTONEG + +/* If link is up && autoneg compleate, and if + * GT and PHY disagree about link capabilitys, + * restart autoneg - something screwy with FD/HD + * unless we do this. */ +static void +check_phy_state(struct eth_dev_s *p) +{ + int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR); + int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); + + if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) { + int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) & + miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR); + int want; + + if (nego & PHY_ANLPAR_TXFD) { + want = 0x3; + printf("MII: 100Base-TX, Full Duplex\n"); + } else if (nego & PHY_ANLPAR_TX) { + want = 0x1; + printf("MII: 100Base-TX, Half Duplex\n"); + } else if (nego & PHY_ANLPAR_10FD) { + want = 0x2; + printf("MII: 10Base-T, Full Duplex\n"); + } else if (nego & PHY_ANLPAR_10) { + want = 0x0; + printf("MII: 10Base-T, Half Duplex\n"); + } else { + printf("MII: Unknown link-foo! %x\n", nego); + return; + } + + if ((psr & 0x3) != want) { + printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n", + psr & 0x3, want); + miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0, + miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9)); + udelay(10000); /* the EVB's GT takes a while to notice phy + went down and up */ + } + } +} +#endif + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +***************************************************************************/ +int +gt6426x_eth_probe(void *v, bd_t *bis) +{ + struct eth_device *wp = (struct eth_device *)v; + struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; + int dev = p->dev; + unsigned int reg_base = p->reg_base; + unsigned long temp; + int i; + + if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS )) + { /* This should never happen */ + printf("%s: Invalid device %d\n", __FUNCTION__, dev ); + return 0; + } + +#ifdef DEBUG + printf ("%s: initializing %s\n", __FUNCTION__, wp->name ); + printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n", + GTREGREAD(COMM_UNIT_ARBITER_CONTROL), + GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER)); +#endif + + /* clear MIB counters */ + for(i=0;i<255; i++) + temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i); + +#ifdef CONFIG_INTEL_LXT97X + /* for intel LXT972 */ + + /* led 1: 0x1=txact + led 2: 0xc=link/rxact + led 3: 0x2=rxact (N/C) + strch: 0,2=30 ms, enable */ + miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22); + + /* 2.7ns port rise time */ + /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */ +#else + /* already set up in mpsc.c */ + /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */ + + /* already set up in sdram_init.S... */ + /* MPSC0, MPSC1, RMII */ + /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */ +#endif + GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER, + ether_port_phy_addr[0] | + (ether_port_phy_addr[1]<<5) | + (ether_port_phy_addr[2]<<10)); /* 2000 */ + + /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes) + * 9 - 1: RIFB - interrupt on frame boundaries only + * 6:7 - 00: big endian rx and tx + * 5:2 - 1111: 15 retries */ + GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base, + (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */ + +#ifndef USE_SOFTWARE_CACHE_MANAGEMENT + /* enable rx/tx desc/buffer cache snoop */ + GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, + &temp); /* f200 */ + temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30); + GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, + temp); +#endif + + /* 31 28 27 24 23 20 19 16 + * 0000 0000 0000 0000 [0004] + * 15 12 11 8 7 4 3 0 + * 1000 1101 0000 0000 [4d00] + * 20 - 0=MII 1=RMII + * 19 - 0=speed autoneg + * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE) + * 11 - no force link pass + * 10 - 1=disable fctl autoneg + * 8 - override prio ?? */ + temp = 0x00004d00; +#ifndef CONFIG_ETHER_PORT_MII + temp |= (1<<20); /* RMII */ +#endif + /* set En */ + GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base, + temp); /* 2408 */ + + /* hardcode E1 also? */ + /* -- according to dox, this is safer due to extra pulldowns? */ + if (dev<2) { + GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400, + temp); /* 2408 */ + } + + /* wake up MAC */ /* 2400 */ + GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp); + temp |= (1<<7); /* enable port */ +#ifdef CONFIG_GT_USE_MAC_HASH_TABLE + temp |= (1<<12); /* hash size 1/2k */ +#else + temp |= 1; /* promisc */ +#endif + GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp); + /* 2400 */ + +#ifdef RESTART_AUTONEG + check_phy_state(p); +#endif + + printf("%s: Waiting for link up..\n", wp->name); + temp = 10 * 1000; + /* wait for link back up */ + while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8) + && (--temp > 0)){ + udelay(1000); /* wait 1 ms */ + } + if ( temp == 0) { + printf("%s: Failed!\n", wp->name); + return (0); + } + + printf("%s: OK!\n", wp->name); + + p->tdn = 0; + p->rdn = 0; + p->eth_tx_desc[p->tdn].command_status = 0; + + /* Initialize Rx Side */ + for (temp = 0; temp < NR; temp++) { + p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp]; + p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; + + /* GT96100 Owner */ + p->eth_rx_desc[temp].command_status = 0x80000000; + p->eth_rx_desc[temp].next_desc = + (struct eth0_rx_desc_struct *) + &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count; + } + + FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0], + (unsigned int)&p->eth_tx_desc[NR]); + FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0], + (unsigned int)&p->eth_rx_desc[NR]); + + GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base, + (unsigned int) p->eth_tx_desc); + GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base, + (unsigned int) p->eth_rx_desc); + GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base, + (unsigned int) p->eth_rx_desc); + +#ifdef DEBUG + printf ("\nRx descriptor pointer is %08x %08x\n", + GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base), + GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base)); + printf ("\n\n%08x %08x\n", + (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status); + + printf ("Descriptor dump:\n"); + printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status); + printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count); + printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer); + printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc); + printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0)); + printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4)); + printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8)); + printf ("%08x\n\n", + *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc)); +#endif + +#ifdef DEBUG + gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]); +#endif + +#ifdef CONFIG_GT_USE_MAC_HASH_TABLE + { + unsigned int hashtable_base; + u8 *b = (u8 *)(wp->enetaddr); + u32 macH, macL; + + /* twist the MAC up into the way the discovery wants it */ + macH= (b[0]<<8) | b[1]; + macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5]; + + /* mode 0, size 0x800 */ + hashtable_base =initAddressTable(dev,0,1); + + if(!hashtable_base) { + printf("initAddressTable failed\n"); + return 0; + } + + addAddressTableEntry(dev, macH, macL, 1, 0); + GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base, + hashtable_base); + } +#endif + + /* Start Rx*/ + GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080); + printf("%s: gt6426x eth device %d init success \n", wp->name, dev ); + return 1; +} + +/* enter all the galileo ethernet devs into MULTI-BOOT */ +void +gt6426x_eth_initialize(bd_t *bis) +{ + struct eth_device *dev; + struct eth_dev_s *p; + int devnum, x, temp; + char *s, *e, buf[64]; + +#ifdef DEBUG + printf( "\n%s\n", __FUNCTION ); +#endif + + for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) { + dev = calloc(sizeof(*dev), 1); + if (!dev) { + printf( "%s: gal_enet%d allocation failure, %s\n", + __FUNCTION__, devnum, "eth_device structure"); + return; + } + + /* must be less than NAMESIZE (16) */ + sprintf(dev->name, "gal_enet%d", devnum); + +#ifdef DEBUG + printf( "Initializing %s\n", dev->name ); +#endif + + /* Extract the MAC address from the environment */ + switch (devnum) + { + case 0: s = "ethaddr"; break; +#if (GAL_ETH_DEVS > 1) + case 1: s = "eth1addr"; break; +#endif +#if (GAL_ETH_DEVS > 2) + case 2: s = "eth2addr"; break; +#endif + default: /* this should never happen */ + printf( "%s: Invalid device number %d\n", + __FUNCTION__, devnum ); + return; + } + + temp = getenv_r (s, buf, sizeof(buf)); + s = (temp > 0) ? buf : NULL; + +#ifdef DEBUG + printf ("Setting MAC %d to %s\n", devnum, s ); +#endif + for (x = 0; x < 6; ++x) { + dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e+1 : e; + } + + dev->init = (void*)gt6426x_eth_probe; + dev->halt = (void*)gt6426x_eth_reset; + dev->send = (void*)gt6426x_eth_transmit; + dev->recv = (void*)gt6426x_eth_poll; + + p = calloc( sizeof(*p), 1 ); + dev->priv = (void*)p; + if (!p) + { + printf( "%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, "Private Device Structure"); + free(dev); + return; + } + + p->dev = devnum; + p->tdn=0; + p->rdn=0; + p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS; + + p->eth_tx_desc = + (eth0_tx_desc_single *) + (((unsigned int) malloc(sizeof (eth0_tx_desc_single) * + (NT+1)) & 0xfffffff0) + 0x10); + if (!p) + { + printf( "%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, "Tx Descriptor"); + free(dev); + return; + } + + p->eth_rx_desc = + (eth0_rx_desc_single *) + (((unsigned int) malloc(sizeof (eth0_rx_desc_single) * + (NR+1)) & 0xfffffff0) + 0x10); + if (!p->eth_rx_desc) + { + printf( "%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, "Rx Descriptor"); + free(dev); + free(p); + return; + } + + p->eth_tx_buffer = + (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); + if (!p->eth_tx_buffer) + { + printf( "%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, "Tx Bufffer"); + free(dev); + free(p); + free(p->eth_rx_desc); + return; + } + + for (temp = 0 ; temp < NR ; temp ++) { + p->eth_rx_buffer[temp] = + (char *) + (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); + if (!p->eth_rx_buffer[temp]) + { + printf( "%s: %s allocation failure, %s\n", + __FUNCTION__, dev->name, "Rx Buffers"); + free(dev); + free(p); + free(p->eth_tx_buffer); + free(p->eth_rx_desc); + free(p->eth_tx_desc); + while (temp >= 0) + free(p->eth_rx_buffer[--temp]); + return; + } + } + + + eth_register(dev); +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register(dev->name, + gt6426x_miiphy_read, gt6426x_miiphy_write); +#endif + } + +} +#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */ diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h new file mode 100644 index 0000000..beb6db1 --- /dev/null +++ b/board/evb64260/eth.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * eth.h - header file for the polled mode GT ethernet driver + */ + +#ifndef __GT6426x_ETH_H__ +#define __GT6426x_ETH_H__ + +#include +#include +#include +#include + +typedef struct eth0_tx_desc_struct { + volatile __u32 bytecount_reserved; + volatile __u32 command_status; + volatile struct eth0_tx_desc_struct * next_desc; + /* Note - the following will not work for 64 bit addressing */ + volatile unsigned char * buff_pointer; +} __attribute__ ((packed)) eth0_tx_desc_single; + +typedef struct eth0_rx_desc_struct { + volatile __u32 buff_size_byte_count; + volatile __u32 command_status; + volatile struct eth0_rx_desc_struct * next_desc; + volatile unsigned char * buff_pointer; +} __attribute__ ((packed)) eth0_rx_desc_single; + +#define NT 20 /* Number of Transmit buffers */ +#define NR 20 /* Number of Receive buffers */ +#define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) /* 1600 */ +#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400 + +unsigned long TDN_ETH0 , RDN_ETH0; /* Rx/Tx current Descriptor Number*/ +unsigned int EVB64260_ETH0_irq; + +#define CLOSED 0 +#define OPENED 1 + +#define PORT_ETH0 0 + +extern eth0_tx_desc_single *eth0_tx_desc; +extern eth0_rx_desc_single *eth0_rx_desc; +extern char *eth0_tx_buffer; +extern char *eth0_rx_buffer[NR]; +extern char *eth_data; + +extern int gt6426x_eth_poll(void *v); +extern int gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s); +extern void gt6426x_eth_disable(void *v); +extern int gt6426x_eth_probe(void *v, bd_t *bis); + +#endif /* __GT64260x_ETH_H__ */ diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c new file mode 100644 index 0000000..e8ef0e3 --- /dev/null +++ b/board/evb64260/eth_addrtbl.c @@ -0,0 +1,221 @@ +#include +#include +#include +#include +#include +#include "eth.h" +#include "eth_addrtbl.h" + +#define TRUE 1 +#define FALSE 0 + +#define PRINTF printf + +#ifdef CONFIG_GT_USE_MAC_HASH_TABLE + +static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, }; +static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, }; +static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, }; +static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, }; + +static const u32 hashLength[2] = { + (0x8000), /* 8K * 4 entries */ + (0x8000 / 16), /* 512 * 4 entries */ +}; + +/* Initialize the address table for a port, if needed */ +unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector) +{ + unsigned int tableBase; + + if (port < 0 || port >= GAL_ETH_DEVS) { + printf ("%s: Invalid port number %d\n", __FUNCTION__, port); + return 0; + } + + if (hashMode > 1) { + printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port); + return 0; + } + + if (realAddrTableBase[port] && + (addressTableHashSize[port] != hashSizeSelector)) { + /* we have been here before, + * but now we want a different sized table + */ + free (realAddrTableBase[port]); + realAddrTableBase[port] = 0; + addressTableBase[port] = 0; + + } + + tableBase = (unsigned int) addressTableBase[port]; + /* we get called for every probe, so only do this once */ + if (!tableBase) { + int bytes = + hashLength[hashSizeSelector] * sizeof (addrTblEntry); + + realAddrTableBase[port] = + malloc (bytes + 64); + tableBase = (unsigned int)realAddrTableBase; + + if (!tableBase) { + printf ("%s: alloc memory failed \n", __FUNCTION__); + return 0; + } + + /* align to octal byte */ + if (tableBase & 63) + tableBase = (tableBase + 63) & ~63; + + addressTableHashMode[port] = hashMode; + addressTableHashSize[port] = hashSizeSelector; + addressTableBase[port] = (addrTblEntry *) tableBase; + + memset ((void *) tableBase, 0, bytes); + } + + return tableBase; +} + +/* + * ---------------------------------------------------------------------------- + * This function will calculate the hash function of the address. + * depends on the hash mode and hash size. + * Inputs + * macH - the 2 most significant bytes of the MAC address. + * macL - the 4 least significant bytes of the MAC address. + * hashMode - hash mode 0 or hash mode 1. + * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800) + * Outputs + * return the calculated entry. + */ +u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode) +{ + u32 hashResult; + u32 addrH; + u32 addrL; + u32 addr0; + u32 addr1; + u32 addr2; + u32 addr3; + u32 addrHSwapped; + u32 addrLSwapped; + + + addrH = NIBBLE_SWAPPING_16_BIT (macH); + addrL = NIBBLE_SWAPPING_32_BIT (macL); + + addrHSwapped = FLIP_4_BITS (addrH & 0xf) + + ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4) + + ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8) + + ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12); + + addrLSwapped = FLIP_4_BITS (addrL & 0xf) + + ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4) + + ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8) + + ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12) + + ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16) + + ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20) + + ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24) + + ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28); + + addrH = addrHSwapped; + addrL = addrLSwapped; + + if (hash_mode == 0) { + addr0 = (addrL >> 2) & 0x03f; + addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2; + addr2 = (addrL >> 15) & 0x1ff; + addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8); + } else { + addr0 = FLIP_6_BITS (addrL & 0x03f); + addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff)); + addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff); + addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) | + ((addrH & 0x1) << 8))); + } + + hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); + + if (HashSize == _8K_TABLE) { + hashResult = hashResult & 0xffff; + } else { + hashResult = hashResult & 0x07ff; + } + + return (hashResult); +} + + +/* + * ---------------------------------------------------------------------------- + * This function will add an entry to the address table. + * depends on the hash mode and hash size that was initialized. + * Inputs + * port - ETHERNET port number. + * macH - the 2 most significant bytes of the MAC address. + * macL - the 4 least significant bytes of the MAC address. + * skip - if 1, skip this address. + * rd - the RD field in the address table. + * Outputs + * address table entry is added. + * TRUE if success. + * FALSE if table full + */ +int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip) +{ + addrTblEntry *entry; + u32 newHi; + u32 newLo; + u32 i; + + newLo = (((macH >> 4) & 0xf) << 15) + | (((macH >> 0) & 0xf) << 11) + | (((macH >> 12) & 0xf) << 7) + | (((macH >> 8) & 0xf) << 3) + | (((macL >> 20) & 0x1) << 31) + | (((macL >> 16) & 0xf) << 27) + | (((macL >> 28) & 0xf) << 23) + | (((macL >> 24) & 0xf) << 19) + | (skip << SKIP_BIT) | (rd << 2) | VALID; + + newHi = (((macL >> 4) & 0xf) << 15) + | (((macL >> 0) & 0xf) << 11) + | (((macL >> 12) & 0xf) << 7) + | (((macL >> 8) & 0xf) << 3) + | (((macL >> 21) & 0x7) << 0); + + /* + * Pick the appropriate table, start scanning for free/reusable + * entries at the index obtained by hashing the specified MAC address + */ + entry = addressTableBase[port]; + entry += hashTableFunction (macH, macL, addressTableHashSize[port], + addressTableHashMode[port]); + for (i = 0; i < HOP_NUMBER; i++, entry++) { + if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) { + break; + } else { /* if same address put in same position */ + if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8)) + && (entry->hi == newHi)) { + break; + } + } + } + + if (i == HOP_NUMBER) { + PRINTF ("addGT64260addressTableEntry: table section is full\n"); + return (FALSE); + } + + /* + * Update the selected entry + */ + entry->hi = newHi; + entry->lo = newLo; + DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE); + return (TRUE); +} + +#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */ diff --git a/board/evb64260/eth_addrtbl.h b/board/evb64260/eth_addrtbl.h new file mode 100644 index 0000000..5a62c67 --- /dev/null +++ b/board/evb64260/eth_addrtbl.h @@ -0,0 +1,83 @@ +#ifndef _ADDRESS_TABLE_H +#define _ADDRESS_TABLE_H 1 + +/* + * ---------------------------------------------------------------------------- + * addressTable.h - this file has all the declarations of the address table + */ + +#define _8K_TABLE 0 +#define ADDRESS_TABLE_ALIGNMENT 8 +#define HASH_DEFAULT_MODE 14 +#define HASH_MODE 13 +#define HASH_SIZE 12 +#define HOP_NUMBER 12 +#define MAC_ADDRESS_STRING_SIZE 12 +#define MAC_ENTRY_SIZE sizeof(addrTblEntry) +#define MAX_NUMBER_OF_ADDRESSES_TO_STORE 1000 +#define PROMISCUOUS_MODE 0 +#define SKIP 1<<1 +#define SKIP_BIT 1 +#define VALID 1 + +/* + * ---------------------------------------------------------------------------- + * XXX_MIKE - potential sign-extension bugs lurk here... + */ +#define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \ + | (((X) & 0x0f0f0f0f) << 4) ) + +#define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \ + | (((X) & 0x00000f0f) << 4) ) + +#define FLIP_4_BITS(X) ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \ + | (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) ) + +#define FLIP_6_BITS(X) ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \ + | (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \ + | (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) ) + +#define FLIP_9_BITS(X) ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \ + | (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \ + | (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \ + | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) ) + +/* + * V: value we're operating on + * O: offset of rightmost bit in field + * W: width of field to shift + * S: distance to shift left + */ +#define MASK( fieldWidth ) ((1 << (fieldWidth)) - 1) +#define leftShiftedBitfield( V,O,W,S) (((V) & (MASK(W) << (O))) << (S)) +#define rightShiftedBitfield(V,O,W,S) (((u32)((V) & (MASK(W) << (O)))) >> (S)) + + +/* + * Push to main memory all cache lines associated with + * the specified range of virtual memory addresses + * + * A: Address of first byte in range to flush + * N: Number of bytes to flush + * Note - flush_dcache_range() does a "sync", does NOT invalidate + */ +#define DCACHE_FLUSH_N_SYNC( A, N ) flush_dcache_range( (A), ((A)+(N)) ) + + +typedef struct addressTableEntryStruct { + u32 hi; + u32 lo; +} addrTblEntry; + +u32 +uncachedPages( u32 pages ); +u32 +hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode ); + +unsigned int +initAddressTable( u32 port, u32 hashMode, u32 hashSize ); + +int +addAddressTableEntry( u32 port, u32 macH, u32 macL, u32 rd, u32 skip ); + +#endif /* #ifndef _ADDRESS_TABLE_H */ diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c new file mode 100644 index 0000000..6a9d164 --- /dev/null +++ b/board/evb64260/evb64260.c @@ -0,0 +1,444 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * evb64260.c - main board support/init for the Galileo Eval board. + */ + +#include +#include <74xx_7xx.h> +#include +#include +#include +#include + +#include +#include "eth.h" +#include "mpsc.h" +#include "i2c.h" +#include "64260.h" +#ifdef CONFIG_ZUMA_V2 +extern void zuma_mbox_init(void); +#endif + +#undef DEBUG +#define MAP_PCI + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +/* ------------------------------------------------------------------------- */ + +/* this is the current GT register space location */ +/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ + +/* Unfortunately, we cant change it while we are in flash, so we initialize it + * to the "final" value. This means that any debug_led calls before + * board_early_init_f wont work right (like in cpu_init_f). + * See also my_remap_gt_regs below. (NTL) + */ + +unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; + +/* ------------------------------------------------------------------------- */ + +/* + * This is a version of the GT register space remapping function that + * doesn't touch globals (meaning, it's ok to run from flash.) + * + * Unfortunately, this has the side effect that a writable + * INTERNAL_REG_BASE_ADDR is impossible. Oh well. + */ + +void +my_remap_gt_regs(u32 cur_loc, u32 new_loc) +{ + u32 temp; + + /* check and see if it's already moved */ + temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); + if ((temp & 0xffff) == new_loc >> 20) + return; + + temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & + 0xffff0000) | (new_loc >> 20); + + out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); + + while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); +} + +static void +gt_pci_config(void) +{ + /* move PCI stuff out of the way - NTL */ + /* map PCI Host 0 */ + pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE); + + pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0); + pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0); + pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0); + + pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI, + CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE); + + /* map PCI Host 1 */ + pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE); + + pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0); + pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0); + pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0); + + pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI, + CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE); + + /* PCI interface settings */ + GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff); + GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff); + GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); + GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); + + +} + +/* Setup CPU interface paramaters */ +static void +gt_cpu_config(void) +{ + cpu_t cpu = get_cpu_type(); + ulong tmp; + + /* cpu configuration register */ + tmp = GTREGREAD(CPU_CONFIGURATION); + + /* set the AACK delay bit + * see Res#14 */ + tmp |= CPU_CONF_AACK_DELAY; + tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */ + + /* Galileo claims this is necessary for all busses >= 100 MHz */ + tmp |= CPU_CONF_FAST_CLK; + + if (cpu == CPU_750CX) { + tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */ + tmp &= ~CPU_CONF_AP_VALID; + } else { + tmp |= CPU_CONF_DP_VALID; + tmp |= CPU_CONF_AP_VALID; + } + + /* this only works with the MPX bus */ + tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */ + tmp |= CPU_CONF_PIPELINE; + tmp |= CPU_CONF_TA_DELAY; + + GT_REG_WRITE(CPU_CONFIGURATION, tmp); + + /* CPU master control register */ + tmp = GTREGREAD(CPU_MASTER_CONTROL); + + tmp |= CPU_MAST_CTL_ARB_EN; + + if ((cpu == CPU_7400) || + (cpu == CPU_7410) || + (cpu == CPU_7450)) { + + tmp |= CPU_MAST_CTL_CLEAN_BLK; + tmp |= CPU_MAST_CTL_FLUSH_BLK; + + } else { + /* cleanblock must be cleared for CPUs + * that do not support this command + * see Res#1 */ + tmp &= ~CPU_MAST_CTL_CLEAN_BLK; + tmp &= ~CPU_MAST_CTL_FLUSH_BLK; + } + GT_REG_WRITE(CPU_MASTER_CONTROL, tmp); +} + +/* + * board_early_init_f. + * + * set up gal. device mappings, etc. + */ +int board_early_init_f (void) +{ + uchar sram_boot = 0; + + /* + * set up the GT the way the kernel wants it + * the call to move the GT register space will obviously + * fail if it has already been done, but we're going to assume + * that if it's not at the power-on location, it's where we put + * it last time. (huber) + */ + my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS); + + gt_pci_config(); + + /* mask all external interrupt sources */ + GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0); + GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); + GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); + GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); + GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); + GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); + GT_REG_WRITE(CPU_INT_0_MASK, 0); + GT_REG_WRITE(CPU_INT_1_MASK, 0); + GT_REG_WRITE(CPU_INT_2_MASK, 0); + GT_REG_WRITE(CPU_INT_3_MASK, 0); + + /* now, onto the configuration */ + GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG); + + /* ----- DEVICE BUS SETTINGS ------ */ + + /* + * EVB + * 0 - SRAM + * 1 - RTC + * 2 - UART + * 3 - Flash + * boot - BootCS + * + * Zuma + * 0 - Flash + * boot - BootCS + */ + + /* + * the dual 7450 module requires burst access to the boot + * device, so the serial rom copies the boot device to the + * on-board sram on the eval board, and updates the correct + * registers to boot from the sram. (device0) + */ +#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) + /* Zuma has no SRAM */ + sram_boot = 0; +#else + if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CFG_MONITOR_BASE) + sram_boot = 1; +#endif + + if (!sram_boot) + memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + + memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); + memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); + memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + + /* configure device timing */ +#ifdef CFG_DEV0_PAR + if (!sram_boot) + GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); +#endif + +#ifdef CFG_DEV1_PAR + GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#endif +#ifdef CFG_DEV2_PAR + GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#endif + +#ifdef CONFIG_EVB64260 +#ifdef CFG_32BIT_BOOT_PAR + /* detect if we are booting from the 32 bit flash */ + if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { + /* 32 bit boot flash */ + GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR); + } else { + /* 8 bit boot flash */ + GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + } +#else + /* 8 bit boot flash only */ + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); +#endif +#else /* CONFIG_EVB64260 not defined */ + /* We are booting from 16-bit flash. + */ + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_16BIT_BOOT_PAR); +#endif + + gt_cpu_config(); + + /* MPP setup */ + GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0); + GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1); + GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2); + GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3); + + GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX); + + return 0; +} + +/* various things to do after relocation */ + +int misc_init_r (void) +{ + icache_enable(); +#ifdef CFG_L2 + l2cache_enable(); +#endif + +#ifdef CONFIG_MPSC + mpsc_init2(); +#endif + +#ifdef CONFIG_ZUMA_V2 + zuma_mbox_init(); +#endif + return (0); +} + +void +after_reloc(ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* check to see if we booted from the sram. If so, move things + * back to the way they should be. (we're running from main + * memory at this point now */ + + if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) { + memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M); + } + + /* now, jump to the main U-Boot board init code */ + board_init_r ((gd_t *)gd, dest_addr); + + /* NOTREACHED */ +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int +checkboard (void) +{ + puts ("Board: " CFG_BOARD_NAME "\n"); + return (0); +} + +/* utility functions */ +void +debug_led(int led, int mode) +{ +#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4) + volatile int *addr = NULL; + int dummy; + + if (mode == 1) { + switch (led) { + case 0: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000); + break; + + case 1: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000); + break; + + case 2: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000); + break; + } + } else if (mode == 0) { + switch (led) { + case 0: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000); + break; + + case 1: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000); + break; + + case 2: + addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000); + break; + } + } + WRITE_CHAR(addr, 0); + dummy = *addr; +#endif /* CONFIG_ZUMA_V2 */ +} + +void +display_mem_map(void) +{ + int i,j; + unsigned int base,size,width; + /* SDRAM */ + printf("SDRAM\n"); + for(i=0;i<=BANK3;i++) { + base = memoryGetBankBaseAddress(i); + size = memoryGetBankSize(i); + if(size !=0) + { + printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20); + } + } + + /* CPU's PCI windows */ + for(i=0;i<=PCI_HOST1;i++) { + printf("\nCPU's PCI %d windows\n", i); + base=pciGetSpaceBase(i,PCI_IO); + size=pciGetSpaceSize(i,PCI_IO); + printf(" IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20); + for(j=0;j<=PCI_REGION3;j++) { + base = pciGetSpaceBase(i,j); + size = pciGetSpaceSize(i,j); + printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base, + size>>20); + } + } + + /* Devices */ + printf("\nDEVICES\n"); + for(i=0;i<=DEVICE3;i++) { + base = memoryGetDeviceBaseAddress(i); + size = memoryGetDeviceSize(i); + width= memoryGetDeviceWidth(i) * 8; + printf("DEV %d: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", + i, base, size>>20, width); + } + + /* Bootrom */ + base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */ + size = memoryGetDeviceSize(BOOT_DEVICE); + width= memoryGetDeviceWidth(BOOT_DEVICE) * 8; + printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", + base, size>>20, width); +} diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c new file mode 100644 index 0000000..6ab23dc --- /dev/null +++ b/board/evb64260/flash.c @@ -0,0 +1,854 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * flash.c - flash support for the 512k, 8bit boot flash on the GEVB + * most of this file was based on the existing U-Boot + * flash drivers. + */ + +#include +#include +#include +#include +#include "intel_flash.h" + +#define FLASH_ROM 0xFFFD /* unknown flash type */ +#define FLASH_RAM 0xFFFE /* unknown flash type */ +#define FLASH_MAN_UNKNOWN 0xFFFF0000 + +/* #define DEBUG */ +/* #define FLASH_ID_OVERRIDE */ /* Hack to set type to 040B if ROM emulator is installed. + * Can be used to program a ROM in circuit if a programmer + * is not available by swapping the rom out. */ + +/* Intel flash commands */ +int flash_erase_intel(flash_info_t *info, int s_first, int s_last); +int write_word_intel(bank_addr_t addr, bank_word_t value); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + */ + +unsigned long +flash_init (void) +{ + unsigned int i; + unsigned long size_b0 = 0, size_b1 = 0; + unsigned long base, flash_size; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + flash_size = size_b0 + size_b1; + return flash_size; +} + +/*----------------------------------------------------------------------- + */ +static void +flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + int sector_size; + + if(!info->sector_count) return; + + /* set up sector start address table */ + switch(info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + case FLASH_28F128J3A: + case FLASH_28F640J3A: + case FLASH_RAM: + /* this chip has uniformly spaced sectors */ + sector_size=info->size/info->sector_count; + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * sector_size); + break; + default: + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + } +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->start[0] <= base && base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ +void +flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf ("AM29LV040B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400B: + printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_28F640J3A: + printf ("28F640J3A (64 Mbit)\n"); + break; + case FLASH_28F128J3A: + printf ("28F128J3A (128 Mbit)\n"); + break; + case FLASH_ROM: + printf ("ROM\n"); + break; + case FLASH_RAM: + printf ("RAM\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + puts (" Size: "); + print_size (info->size, ""); + printf (" in %d Sectors\n", info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static inline void flash_cmd(int width, volatile unsigned char *addr, int offset, unsigned char cmd) +{ + /* supports 1x8, 1x16, and 2x16 */ + /* 2x8 and 4x8 are not supported */ + if(width==4) { + /* assuming chips are in 16 bit mode */ + /* 2x16 */ + unsigned long cmd32=(cmd<<16)|cmd; + *(volatile unsigned long *)(addr+offset*2)=cmd32; + } else if (width == 2) { + /* 1x16 */ + *(volatile unsigned short *)((unsigned short*)addr+offset)=cmd; + } else { + /* 1x8 */ + *(volatile unsigned char *)(addr+offset)=cmd; + } +} + +static ulong +flash_get_size (int portwidth, vu_long *addr, flash_info_t *info) +{ + short i; + volatile unsigned char *caddr = (unsigned char *)addr; + volatile unsigned short *saddr = (unsigned short *)addr; + volatile unsigned long *laddr = (unsigned long *)addr; + char old[2], save; + ulong id, manu, base = (ulong)addr; + + info->portwidth=portwidth; + + save = *caddr; + + flash_cmd(portwidth,caddr,0,0xf0); + flash_cmd(portwidth,caddr,0,0xf0); + + udelay(10); + + old[0] = caddr[0]; + old[1] = caddr[1]; + + + if(old[0]!=0xf0) { + flash_cmd(portwidth,caddr,0,0xf0); + flash_cmd(portwidth,caddr,0,0xf0); + + udelay(10); + + if(*caddr==0xf0) { + /* this area is ROM */ + *caddr=save; +#ifndef FLASH_ID_OVERRIDE + info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; + info->sector_count = 8; + info->size = 0x80000; +#else + info->flash_id = FLASH_MAN_AMD + FLASH_AM040; + info->sector_count = 8; + info->size = 0x80000; + info->chipwidth=1; +#endif + flash_get_offsets(base, info); + return info->size; + } + } else { + *caddr=0; + + udelay(10); + + if(*caddr==0) { + /* this area is RAM */ + *caddr=save; + info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN; + info->sector_count = 8; + info->size = 0x80000; + flash_get_offsets(base, info); + return info->size; + } + flash_cmd(portwidth,caddr,0,0xf0); + + udelay(10); + } + + /* Write auto select command: read Manufacturer ID */ + flash_cmd(portwidth,caddr,0x555,0xAA); + flash_cmd(portwidth,caddr,0x2AA,0x55); + flash_cmd(portwidth,caddr,0x555,0x90); + + udelay(10); + + if ((caddr[0] == old[0]) && + (caddr[1] == old[1])) { + + /* this area is ROM */ +#ifndef FLASH_ID_OVERRIDE + info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; + info->sector_count = 8; + info->size = 0x80000; +#else + info->flash_id = FLASH_MAN_AMD + FLASH_AM040; + info->sector_count = 8; + info->size = 0x80000; + info->chipwidth=1; +#endif + flash_get_offsets(base, info); + return info->size; +#ifdef DEBUG + } else { + printf("%px%d: %02x:%02x -> %02x:%02x\n", + caddr, portwidth, old[0], old[1], + caddr[0], caddr[1]); +#endif + } + + switch(portwidth) { + case 1: + manu = caddr[0]; + manu |= manu<<16; + id = caddr[1]; + break; + case 2: + manu = saddr[0]; + manu |= manu<<16; + id = saddr[1]; + id |= id<<16; + break; + case 4: + manu = laddr[0]; + id = laddr[1]; + break; + default: + id = manu = -1; + break; + } + +#ifdef DEBUG + printf("\n%08lx:%08lx:%08lx\n", base, manu, id); + printf("%08lx %08lx %08lx %08lx\n", + laddr[0],laddr[1],laddr[2],laddr[3]); +#endif + + switch (manu) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + printf("Unknown Mfr [%08lx]:%08lx\n", manu, id); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + switch (id) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + info->chipwidth=1; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + info->chipwidth=1; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + info->chipwidth=1; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + info->chipwidth=1; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + info->chipwidth=1; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + info->chipwidth=1; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + case AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x80000; + info->chipwidth=1; + break; + + case INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */ + info->chipwidth=2; + if(portwidth==4) info->size*=2; /* 2x16 */ + break; + + case INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */ + info->chipwidth=2; + if(portwidth==4) info->size*=2; /* 2x16 */ + break; + + default: + printf("Unknown id %lx:[%lx]\n", manu, id); + info->flash_id = FLASH_UNKNOWN; + info->chipwidth=1; + return (0); /* => no or unknown flash */ + + } + + flash_get_offsets(base, info); + +#if 0 + /* set up sector start address table */ + if (info->flash_id & FLASH_AM040) { + /* this chip has uniformly spaced sectors */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +#endif + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0)=0x02 */ + /* D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + saddr = (volatile unsigned short *)(info->start[i]); + laddr = (volatile unsigned long *)(info->start[i]); + if(portwidth==1) + info->protect[i] = caddr[2] & 1; + else if(portwidth==2) + info->protect[i] = saddr[2] & 1; + else + info->protect[i] = laddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (volatile unsigned char *)info->start[0]; + + flash_cmd(portwidth,caddr,0,0xF0); /* reset bank */ + } + + return (info->size); +} + +/* TODO: 2x16 unsupported */ +int +flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile unsigned char *addr = (uchar *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + /* TODO: 2x16 unsupported */ + if(info->portwidth==4) return 1; + + if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; + if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { + for (sect = s_first; sect<=s_last; sect++) { + int sector_size=info->size/info->sector_count; + addr = (uchar *)(info->start[sect]); + memset((void *)addr, 0, sector_size); + } + return 0; + } + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL) { + return flash_erase_intel(info, + (unsigned short)s_first, + (unsigned short)s_last); + } + +#if 0 + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } +#endif + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_cmd(info->portwidth,addr,0x555,0xAA); + flash_cmd(info->portwidth,addr,0x2AA,0x55); + flash_cmd(info->portwidth,addr,0x555,0x80); + flash_cmd(info->portwidth,addr,0x555,0xAA); + flash_cmd(info->portwidth,addr,0x2AA,0x55); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (uchar *)(info->start[sect]); + flash_cmd(info->portwidth,addr,0,0x30); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile unsigned char *)(info->start[l_sect]); + /* broken for 2x16: TODO */ + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned char *)info->start[0]; + flash_cmd(info->portwidth,addr,0,0xf0); + flash_cmd(info->portwidth,addr,0,0xf0); + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +/* broken for 2x16: TODO */ +int +write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + if(info->portwidth==4) return 1; + + if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0; + if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { + memcpy((void *)addr, src, cnt); + return 0; + } + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +/* broken for 2x16: TODO */ +static int +write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile unsigned char *addr = (uchar *)(info->start[0]); + ulong start; + int flag, i; + + if(info->portwidth==4) return 1; + + if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; + if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { + *(unsigned long *)dest=data; + return 0; + } + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + unsigned short low = data & 0xffff; + unsigned short hi = (data >> 16) & 0xffff; + int ret = write_word_intel((bank_addr_t)dest, hi); + + if (!ret) ret = write_word_intel((bank_addr_t)(dest+2), low); + + return ret; + } + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* first, perform an unlock bypass command to speed up flash writes */ + addr[0x555] = 0xAA; + addr[0x2AA] = 0x55; + addr[0x555] = 0x20; + + /* write each byte out */ + for (i = 0; i < 4; i++) { + char *data_ch = (char *)&data; + addr[0] = 0xA0; + *(((char *)dest)+i) = data_ch[i]; + udelay(10); /* XXX */ + } + + /* we're done, now do an unlock bypass reset */ + addr[0] = 0x90; + addr[0] = 0x00; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c new file mode 100644 index 0000000..c62b647 --- /dev/null +++ b/board/evb64260/i2c.c @@ -0,0 +1,315 @@ +#include +#include +#include +#include +#include + +#define MAX_I2C_RETRYS 10 +#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */ +#undef DEBUG_I2C + +#ifdef DEBUG_I2C +#define DP(x) x +#else +#define DP(x) +#endif + +/* Assuming that there is only one master on the bus (us) */ + +static void +i2c_init(int speed, int slaveaddr) +{ + unsigned int n, m, freq, margin, power; + unsigned int actualFreq, actualN=0, actualM=0; + unsigned int control, status; + unsigned int minMargin = 0xffffffff; + unsigned int tclk = 125000000; + + DP(puts("i2c_init\n")); + + for(n = 0 ; n < 8 ; n++) + { + for(m = 0 ; m < 16 ; m++) + { + power = 2< freq) + margin = speed - freq; + else + margin = freq - speed; + if(margin < minMargin) + { + minMargin = margin; + actualFreq = freq; + actualN = n; + actualM = m; + } + } + } + + DP(puts("setup i2c bus\n")); + + /* Setup bus */ + + GT_REG_WRITE(I2C_SOFT_RESET, 0); + + DP(puts("udelay...\n")); + + udelay(I2C_DELAY); + + DP(puts("set baudrate\n")); + + GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); + GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); + + udelay(I2C_DELAY * 10); + + DP(puts("read control, baudrate\n")); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + GT_REG_READ(I2C_CONTROL, &control); +} + +static uchar +i2c_start(void) +{ + unsigned int control, status; + int count = 0; + + DP(puts("i2c_start\n")); + + /* Set the start bit */ + + GT_REG_READ(I2C_CONTROL, &control); + control |= (0x1 << 5); + GT_REG_WRITE(I2C_CONTROL, control); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + + count = 0; + while ((status & 0xff) != 0x08) { + udelay(I2C_DELAY); + if (count > 20) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return (status); + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + + return (0); +} + +static uchar +i2c_select_device(uchar dev_addr, uchar read, int ten_bit) +{ + unsigned int status, data, bits = 7; + int count = 0; + + DP(puts("i2c_select_device\n")); + + /* Output slave address */ + + if (ten_bit) { + bits = 10; + } + + data = (dev_addr << 1); + /* set the read bit */ + data |= read; + GT_REG_WRITE(I2C_DATA, data); + /* assert the address */ + RESET_REG_BITS(I2C_CONTROL, BIT3); + + udelay(I2C_DELAY); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count = 0; + while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { + udelay(I2C_DELAY); + if (count > 20) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return(status); + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + + if (bits == 10) { + printf("10 bit I2C addressing not yet implemented\n"); + return (0xff); + } + + return (0); +} + +static uchar +i2c_get_data(uchar* return_data, int len) { + + unsigned int data, status = 0; + int count = 0; + + DP(puts("i2c_get_data\n")); + + while (len) { + + /* Get and return the data */ + + RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); + + udelay(I2C_DELAY * 5); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x50) { + udelay(I2C_DELAY); + if(count > 2) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return 0; + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + GT_REG_READ(I2C_DATA, &data); + len--; + *return_data = (uchar)data; + return_data++; + } + RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3); + while ((status & 0xff) != 0x58) { + udelay(I2C_DELAY); + if(count > 200) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return (status); + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */ + + return (0); +} + +static uchar +i2c_write_data(unsigned int data, int len) +{ + unsigned int status; + int count = 0; + + DP(puts("i2c_write_data\n")); + + if (len > 4) + return -1; + + while (len) { + /* Set and assert the data */ + + GT_REG_WRITE(I2C_DATA, (unsigned int)data); + RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); + + udelay(I2C_DELAY); + + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + while ((status & 0xff) != 0x28) { + udelay(I2C_DELAY); + if(count > 20) { + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ + return (status); + } + GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); + count++; + } + len--; + } + GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4)); + GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); + + udelay(I2C_DELAY * 10); + + return (0); +} + +static uchar +i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit) +{ + uchar status; + + DP(puts("i2c_set_dev_offset\n")); + + status = i2c_select_device(dev_addr, 0, ten_bit); + if (status) { +#ifdef DEBUG_I2C + printf("Failed to select device setting offset: 0x%02x\n", + status); +#endif + return status; + } + + status = i2c_write_data(offset, 1); + if (status) { +#ifdef DEBUG_I2C + printf("Failed to write data: 0x%02x\n", status); +#endif + return status; + } + + return (0); +} + +uchar +i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data, + int ten_bit) +{ + uchar status = 0; + unsigned int i2cFreq = 400000; + + DP(puts("i2c_read\n")); + + i2c_init(i2cFreq,0); + + status = i2c_start(); + + if (status) { +#ifdef DEBUG_I2C + printf("Transaction start failed: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_set_dev_offset(dev_addr, 0, 0); + if (status) { +#ifdef DEBUG_I2C + printf("Failed to set offset: 0x%02x\n", status); +#endif + return status; + } + + i2c_init(i2cFreq,0); + + status = i2c_start(); + if (status) { +#ifdef DEBUG_I2C + printf("Transaction restart failed: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_select_device(dev_addr, 1, ten_bit); + if (status) { +#ifdef DEBUG_I2C + printf("Address not acknowledged: 0x%02x\n", status); +#endif + return status; + } + + status = i2c_get_data(data, len); + if (status) { +#ifdef DEBUG_I2C + printf("Data not recieved: 0x%02x\n", status); +#endif + return status; + } + + return 0; +} diff --git a/board/evb64260/i2c.h b/board/evb64260/i2c.h new file mode 100644 index 0000000..9c21992 --- /dev/null +++ b/board/evb64260/i2c.h @@ -0,0 +1,7 @@ +#ifndef __I2C_H__ +#define __I2C_H__ + +/* function declarations */ +uchar i2c_read(uchar, unsigned int, int, uchar*, int); + +#endif diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c new file mode 100644 index 0000000..ed6a2a0 --- /dev/null +++ b/board/evb64260/intel_flash.c @@ -0,0 +1,277 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00 + */ + +#include +#include +#include +#include +#include "intel_flash.h" + + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +static void +bank_reset(flash_info_t *info, int sect) +{ + bank_addr_t addrw, eaddrw; + + addrw = (bank_addr_t)info->start[sect]; + eaddrw = BANK_ADDR_NEXT_WORD(addrw); + + while (addrw < eaddrw) { +#ifdef FLASH_DEBUG + printf(" writing reset cmd to addr 0x%08lx\n", + (unsigned long)addrw); +#endif + *addrw = BANK_CMD_RST; + addrw++; + } +} + +static void +bank_erase_init(flash_info_t *info, int sect) +{ + bank_addr_t addrw, saddrw, eaddrw; + int flag; + +#ifdef FLASH_DEBUG + printf("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG); + printf("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1); + printf("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2); + printf("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT); + printf("0x%08x BANK_CMD_RST\n", BANK_CMD_RST); + printf("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY); + printf("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR); +#endif + + saddrw = (bank_addr_t)info->start[sect]; + eaddrw = BANK_ADDR_NEXT_WORD(saddrw); + +#ifdef FLASH_DEBUG + printf("erasing sector %d, start addr = 0x%08lx " + "(bank next word addr = 0x%08lx)\n", sect, + (unsigned long)saddrw, (unsigned long)eaddrw); +#endif + + /* Disable intrs which might cause a timeout here */ + flag = disable_interrupts(); + + for (addrw = saddrw; addrw < eaddrw; addrw++) { +#ifdef FLASH_DEBUG + printf(" writing erase cmd to addr 0x%08lx\n", + (unsigned long)addrw); +#endif + *addrw = BANK_CMD_ERASE1; + *addrw = BANK_CMD_ERASE2; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); +} + +static int +bank_erase_poll(flash_info_t *info, int sect) +{ + bank_addr_t addrw, saddrw, eaddrw; + int sectdone, haderr; + + saddrw = (bank_addr_t)info->start[sect]; + eaddrw = BANK_ADDR_NEXT_WORD(saddrw); + + sectdone = 1; + haderr = 0; + + for (addrw = saddrw; addrw < eaddrw; addrw++) { + bank_word_t stat = *addrw; + +#ifdef FLASH_DEBUG + printf(" checking status at addr " + "0x%08x [0x%08x]\n", + (unsigned long)addrw, stat); +#endif + if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY) + sectdone = 0; + else if ((stat & BANK_STAT_ERR) != 0) { + printf(" failed on sector %d " + "(stat = 0x%08x) at " + "address 0x%p\n", + sect, stat, addrw); + *addrw = BANK_CMD_CLR_STAT; + haderr = 1; + } + } + + if (haderr) + return (-1); + else + return (sectdone); +} + +int +write_word_intel(bank_addr_t addr, bank_word_t value) +{ + bank_word_t stat; + ulong start; + int flag, retval; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = BANK_CMD_PROG; + + *addr = value; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + retval = 0; + + /* data polling for D7 */ + start = get_timer (0); + do { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + retval = 1; + goto done; + } + stat = *addr; + } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); + + if ((stat & BANK_STAT_ERR) != 0) { + printf("flash program failed (stat = 0x%08lx) " + "at address 0x%08lx\n", (ulong)stat, (ulong)addr); + *addr = BANK_CMD_CLR_STAT; + retval = 3; + } + +done: + /* reset to read mode */ + *addr = BANK_CMD_RST; + + return (retval); +} + +/*----------------------------------------------------------------------- + */ + +int +flash_erase_intel(flash_info_t *info, int s_first, int s_last) +{ + int prot, sect, haderr; + ulong start, now, last; + +#ifdef FLASH_DEBUG + printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" + " Bank # %d: ", s_last - s_first + 1, s_first, s_last, + (info - flash_info) + 1); + flash_print_info(info); +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sector%s will not be erased!\n", + prot, (prot > 1 ? "s" : "")); + } + + start = get_timer (0); + last = 0; + haderr = 0; + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + ulong estart; + int sectdone; + + bank_erase_init(info, sect); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + estart = get_timer(start); + + do { + now = get_timer(start); + + if (now - estart > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout (sect %d)\n", sect); + haderr = 1; + break; + } + +#ifndef FLASH_DEBUG + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } +#endif + + sectdone = bank_erase_poll(info, sect); + + if (sectdone < 0) { + haderr = 1; + break; + } + + } while (!sectdone); + + if (haderr) + break; + } + } + + if (haderr > 0) + printf (" failed\n"); + else + printf (" done\n"); + + /* reset to read mode */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + bank_reset(info, sect); + } + } + return haderr; +} diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h new file mode 100644 index 0000000..dc2aa00 --- /dev/null +++ b/board/evb64260/intel_flash.h @@ -0,0 +1,160 @@ +/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ + +/* + * acceptable chips types are: + * + * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A + */ + +/* register addresses, valid only following an CHIP_CMD_RD_ID command */ +#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */ +#define CHIP_ADDR_REG_DEV 0x000001 /* device id */ +#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */ +#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */ + +/* Commands */ +#define CHIP_CMD_RST 0xFF /* reset flash */ +#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ +#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ +#define CHIP_CMD_RD_STAT 0x70 /* read the status register */ +#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ +#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */ +#define CHIP_CMD_PROG 0x40 /* program word command */ +#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ +#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ +#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ +#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ +#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ +#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ +#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ + +/* status register bits */ +#define CHIP_STAT_DPS 0x02 /* Device Protect Status */ +#define CHIP_STAT_VPPS 0x08 /* VPP Status */ +#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ +#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ +#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ +#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ + +#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \ + CHIP_STAT_ECLBS | CHIP_STAT_PSLBS) + +/* ID and Lock Configuration */ +#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ +#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ +#define CHIP_RD_ID_DEV CFG_FLASH_ID + +/* dimensions */ +#define CHIP_WIDTH 2 /* chips are in 16 bit mode */ +#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */ +#define CHIP_NBLOCKS 128 +#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */ +#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS) + +/********************** DEFINES for Hymod Flash ******************************/ + +/* + * The hymod board has 2 x 28F320J5 chips running in + * 16 bit mode, for a 32 bit wide bank. + */ + +typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */ +typedef volatile bank_word_t *bank_addr_t; +typedef unsigned long bank_size_t; /* want this big - >= 32 bit */ + +#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */ +#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */ + +#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH) +#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT) +#define BANK_NBLOCKS CHIP_NBLOCKS +#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH) +#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH) + +#define MAX_BANKS 1 /* only one bank possible */ + +/* align bank addresses and sizes to bank word boundaries */ +#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(BANK_WIDTH - 1))) +#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \ + (bank_size_t)(s) + (BANK_WIDTH - 1))) + +/* align bank addresses and sizes to bank block boundaries */ +#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(BANK_BLKSZ - 1))) +#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \ + (bank_size_t)(s) + (BANK_BLKSZ - 1))) + +/* align bank addresses and sizes to bank boundaries */ +#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(BANK_SIZE - 1))) +#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \ + (bank_size_t)(s) + (BANK_SIZE - 1))) + +/* add an offset to a bank address */ +#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \ + (bank_size_t)(o)) + +/* get base address of bank b, given flash base address a */ +#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ + (bank_size_t)(b) * BANK_SIZE) + +/* adjust a bank address to start of next word, block or bank */ +#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ + BANK_WIDTH) +#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ + BANK_BLKSZ) +#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ + BANK_SIZE) + +/* get bank address of chip register r given a bank base address a */ +#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ + ((bank_size_t)(r) << BANK_WSHIFT)) + +/* make a bank address for each chip register address */ + +#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN) +#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV) +#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM) +#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b)) + +/* + * replicate a chip cmd/stat/rd value into each byte position within a word + * so that multiple chips are accessed in a single word i/o operation + * + * this must be as wide as the bank_word_t type, and take into account the + * chip width and bank layout + */ + +#define BANK_FILL_WORD(o) ((bank_word_t)(o)) + +/* make a bank word value for each chip cmd/stat/rd value */ + +/* Commands */ +#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST) +#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID) +#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT) +#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT) +#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1) +#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2) +#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG) +#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK) +#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK) +#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR) +#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK) + +/* status register bits */ +#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS) +#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS) +#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS) +#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS) +#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS) +#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS) +#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY) + +#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR) + +/* ID and Lock Configuration */ +#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK) +#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN) +#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV) diff --git a/board/evb64260/local.h b/board/evb64260/local.h new file mode 100644 index 0000000..3d9b443 --- /dev/null +++ b/board/evb64260/local.h @@ -0,0 +1,62 @@ +/* + * include/local.h - local configuration options, board specific + */ + +#ifndef __LOCAL_H +#define __LOCAL_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +/* This tells U-Boot that the config options are compiled in */ +/* #undef ENV_IS_EMBEDDED */ +/* Don't touch this! U-Boot figures this out based on other + * magic. */ + +/* Uncomment and define any of the below options */ + +/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ + /* Note: If you defined CONFIG_EVB64260_750CX this */ + /* gets defined automatically. */ + +/* These want string arguments */ +/* #define CONFIG_BOOTARGS */ +/* #define CONFIG_BOOTCOMMAND */ +/* #define CONFIG_RAMBOOTCOMMAND */ +/* #define CONFIG_NFSBOOTCOMMAND */ +/* #define CFG_AUTOLOAD */ +/* #define CONFIG_PREBOOT */ + +/* These don't */ + +/* #define CONFIG_BOOTDELAY */ +/* #define CONFIG_BAUDRATE */ +/* #define CONFIG_LOADS_ECHO */ +/* #define CONFIG_ETHADDR */ +/* #define CONFIG_ETH2ADDR */ +/* #define CONFIG_ETH3ADDR */ +/* #define CONFIG_IPADDR */ +/* #define CONFIG_SERVERIP */ +/* #define CONFIG_ROOTPATH */ +/* #define CONFIG_GATEWAYIP */ +/* #define CONFIG_NETMASK */ +/* #define CONFIG_HOSTNAME */ +/* #define CONFIG_BOOTFILE */ +/* #define CONFIG_LOADADDR */ + +/* these hardware addresses are pretty bogus, please change them to + suit your needs */ + +/* first ethernet */ +#define CONFIG_ETHADDR 00:11:22:33:44:55 + +/* next two ethernet hwaddrs */ +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:11:22:33:44:66 +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:11:22:33:44:77 + +#define CONFIG_ENV_OVERWRITE +#endif /* __CONFIG_H */ diff --git a/board/evb64260/memory.c b/board/evb64260/memory.c new file mode 100644 index 0000000..e339854 --- /dev/null +++ b/board/evb64260/memory.c @@ -0,0 +1,457 @@ +/* Memory.c - Memory mappings and remapping functions */ + +/* Copyright - Galileo technology. */ + +/* modified by Josh Huber to clean some things up, and + * fit it into the U-Boot framework */ + +#include +#include + +/******************************************************************** +* memoryGetBankBaseAddress - Gets the base address of a memory bank +* - If the memory bank size is 0 then this base address has no meaning!!! +* +* +* INPUTS: MEMORY_BANK bank - The bank we ask for its base Address. +* OUTPUT: N/A +* RETURNS: Memory bank base address. +*********************************************************************/ +static unsigned long memoryGetBankRegOffset(MEMORY_BANK bank) +{ + switch (bank) + { + case BANK0: + return SCS_0_LOW_DECODE_ADDRESS; + case BANK1: + return SCS_1_LOW_DECODE_ADDRESS; + case BANK2: + return SCS_2_LOW_DECODE_ADDRESS; + case BANK3: + return SCS_3_LOW_DECODE_ADDRESS; + } + return SCS_0_LOW_DECODE_ADDRESS; /* default value */ +} + +unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank) +{ + unsigned int base; + unsigned int regOffset=memoryGetBankRegOffset(bank); + + GT_REG_READ(regOffset,&base); + base = base << 20; + return base; +} + +/******************************************************************** +* memoryGetDeviceBaseAddress - Gets the base address of a device. +* - If the device size is 0 then this base address has no meaning!!! +* +* +* INPUT: DEVICE device - The device we ask for its base address. +* OUTPUT: N/A +* RETURNS: Device base address. +*********************************************************************/ +static unsigned int memoryGetDeviceRegOffset(DEVICE device) +{ + switch (device) + { + case DEVICE0: + return CS_0_LOW_DECODE_ADDRESS; + case DEVICE1: + return CS_1_LOW_DECODE_ADDRESS; + case DEVICE2: + return CS_2_LOW_DECODE_ADDRESS; + case DEVICE3: + return CS_3_LOW_DECODE_ADDRESS; + case BOOT_DEVICE: + return BOOTCS_LOW_DECODE_ADDRESS; + } + return CS_0_LOW_DECODE_ADDRESS; /* default value */ +} + +unsigned int memoryGetDeviceBaseAddress(DEVICE device) +{ + unsigned int regBase; + unsigned int regEnd; + unsigned int regOffset=memoryGetDeviceRegOffset(device); + + GT_REG_READ(regOffset, ®Base); + GT_REG_READ(regOffset+8, ®End); + + if(regEnd<=regBase) return 0xffffffff; /* ERROR !!! */ + + regBase = regBase << 20; + return regBase; +} + +/******************************************************************** +* memoryGetBankSize - Returns the size of a memory bank. +* +* +* INPUT: MEMORY_BANK bank - The bank we ask for its size. +* OUTPUT: N/A +* RETURNS: Memory bank size. +*********************************************************************/ +unsigned int memoryGetBankSize(MEMORY_BANK bank) +{ + unsigned int size,base; + unsigned int highValue; + unsigned int highAddress=memoryGetBankRegOffset(bank)+8; + + base = memoryGetBankBaseAddress(bank); + GT_REG_READ(highAddress,&highValue); + highValue = (highValue + 1) << 20; + if(base > highValue) + size=0; + else + size = highValue - base; + return size; +} + +/******************************************************************** +* memoryGetDeviceSize - Returns the size of a device memory space +* +* +* INPUT: DEVICE device - The device we ask for its base address. +* OUTPUT: N/A +* RETURNS: Size of a device memory space. +*********************************************************************/ +unsigned int memoryGetDeviceSize(DEVICE device) +{ + unsigned int size,base; + unsigned int highValue; + unsigned int highAddress=memoryGetDeviceRegOffset(device)+8; + + base = memoryGetDeviceBaseAddress(device); + GT_REG_READ(highAddress,&highValue); + if (highValue == 0xfff) + { + size = (~base) + 1; /* what the heck is this? */ + return size; + } + else + highValue = (highValue + 1) << 20; + + if(base > highValue) + size=0; + else + size = highValue - base; + return size; +} + +/******************************************************************** +* memoryGetDeviceWidth - A device can be with: 1,2,4 or 8 Bytes data width. +* The width is determine in registers: 'Device Parameters' +* registers (0x45c, 0x460, 0x464, 0x468, 0x46c - for each device. +* at bits: [21:20]. +* +* INPUT: DEVICE device - Device number +* OUTPUT: N/A +* RETURNS: Device width in Bytes (1,2,4 or 8), 0 if error had occurred. +*********************************************************************/ +unsigned int memoryGetDeviceWidth(DEVICE device) +{ + unsigned int width; + unsigned int regValue; + + GT_REG_READ(DEVICE_BANK0PARAMETERS + device*4,®Value); + width = (regValue & 0x00300000) >> 20; + switch (width) + { + case 0: + return 1; + case 1: + return 2; + case 2: + return 4; + case 3: + return 8; + default: + return 0; + } +} + +bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength) +{ + unsigned int low=0xfff; + unsigned int high=0x0; + unsigned int regOffset=memoryGetBankRegOffset(bank); + + if(bankLength!=0) { + low = (bankBase >> 20) & 0xffff; + high=((bankBase+bankLength)>>20)-1; + } + +#ifdef DEBUG + { + unsigned int oldLow, oldHigh; + GT_REG_READ(regOffset,&oldLow); + GT_REG_READ(regOffset+8,&oldHigh); + + printf("b%d %x-%x->%x-%x\n", bank, oldLow, oldHigh, low, high); + } +#endif + + GT_REG_WRITE(regOffset,low); + GT_REG_WRITE(regOffset+8,high); + + return true; +} +bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength) +{ + /* TODO: what are appropriate "unmapped" values? */ + unsigned int low=0xfff; + unsigned int high=0x0; + unsigned int regOffset=memoryGetDeviceRegOffset(device); + + if(deviceLength != 0) { + low=deviceBase>>20; + high=((deviceBase+deviceLength)>>20)-1; + } else { + /* big problems in here... */ + /* this will HANG */ + } + + GT_REG_WRITE(regOffset,low); + GT_REG_WRITE(regOffset+8,high); + + return true; +} + + +/******************************************************************** +* memoryMapInternalRegistersSpace - Sets new base address for the internals +* registers. +* +* INPUTS: unsigned int internalRegBase - The new base address. +* RETURNS: true on success, false on failure +*********************************************************************/ +bool memoryMapInternalRegistersSpace(unsigned int internalRegBase) +{ + unsigned int currentValue; + unsigned int internalValue = internalRegBase; + + internalRegBase = (internalRegBase >> 20); + GT_REG_READ(INTERNAL_SPACE_DECODE,¤tValue); + internalRegBase = (currentValue & 0xffff0000) | internalRegBase; + GT_REG_WRITE(INTERNAL_SPACE_DECODE,internalRegBase); + INTERNAL_REG_BASE_ADDR = internalValue; + return true; +} + +/******************************************************************** +* memoryGetInternalRegistersSpace - Gets internal registers Base Address. +* +* INPUTS: unsigned int internalRegBase - The new base address. +* RETURNS: true on success, false on failure +*********************************************************************/ +unsigned int memoryGetInternalRegistersSpace(void) +{ + return INTERNAL_REG_BASE_ADDR; +} + +/******************************************************************** +* memorySetProtectRegion - This function modifys one of the 8 regions with +* one of the three protection mode. +* - Be advised to check the spec before modifying them. +* +* +* Inputs: CPU_PROTECT_REGION - one of the eight regions. +* CPU_ACCESS - general access. +* CPU_WRITE - read only access. +* CPU_CACHE_PROTECT - chache access. +* we defining CPU because there is another protect from the pci SIDE. +* Returns: false if one of the parameters is wrong and true else +*********************************************************************/ +bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, + MEMORY_ACCESS memAccess, + MEMORY_ACCESS_WRITE memWrite, + MEMORY_CACHE_PROTECT cacheProtection, + unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int protectHigh = baseAddress + regionLength; + + if(regionLength == 0) /* closing the region */ + { + GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,0x0000ffff); + GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,0); + return true; + } + baseAddress = (baseAddress & 0xfff00000) >> 20; + baseAddress = baseAddress | memAccess << 16 | memWrite << 17 + | cacheProtection << 18; + GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,baseAddress); + protectHigh = (protectHigh & 0xfff00000) >> 20; + GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,protectHigh - 1); + return true; +} + +/******************************************************************** +* memorySetRegionSnoopMode - This function modifys one of the 4 regions which +* supports Cache Coherency. +* +* +* Inputs: SNOOP_REGION region - One of the four regions. +* SNOOP_TYPE snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* unsigned int baseAddress - Base Address of this region. +* unsigned int topAddress - Top Address of this region. +* Returns: false if one of the parameters is wrong and true else +*********************************************************************/ +bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, + MEMORY_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int snoopXbaseAddress; + unsigned int snoopXtopAddress; + unsigned int data; + unsigned int snoopHigh = baseAddress + regionLength; + + if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) ) + return false; + snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region; + snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region; + if(regionLength == 0) /* closing the region */ + { + GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); + GT_REG_WRITE(snoopXtopAddress,0); + return true; + } + baseAddress = baseAddress & 0xffff0000; + data = (baseAddress >> 16) | snoopType << 16; + GT_REG_WRITE(snoopXbaseAddress,data); + snoopHigh = (snoopHigh & 0xfff00000) >> 20; + GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1); + return true; +} + +/******************************************************************** +* memoryRemapAddress - This fubction used for address remapping. +* +* +* Inputs: regOffset: remap register +* remapValue : +* Returns: false if one of the parameters is erroneous,true otherwise. +*********************************************************************/ +bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue) +{ + unsigned int valueForReg; + valueForReg = (remapValue & 0xfff00000) >> 20; + GT_REG_WRITE(remapReg, valueForReg); + return true; +} + +/******************************************************************** +* memoryGetDeviceParam - This function used for getting device parameters from +* DEVICE BANK PARAMETERS REGISTER +* +* +* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK +* PARAMETERS REGISTER +* - deviceNum : number of device +* Returns: false if one of the parameters is erroneous,true otherwise. +*********************************************************************/ +bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum) +{ + unsigned int valueOfReg; + unsigned int calcData; + + GT_REG_READ(DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg); + calcData = (0x7 & valueOfReg) + ((0x400000 & valueOfReg) >> 19); + deviceParam -> turnOff = calcData; /* Turn Off */ + + calcData = ((0x78 & valueOfReg) >> 3) + ((0x800000 & valueOfReg) >> 19); + deviceParam -> acc2First = calcData; /* Access To First */ + + calcData = ((0x780 & valueOfReg) >> 7) + ((0x1000000 & valueOfReg) >> 20); + deviceParam -> acc2Next = calcData; /* Access To Next */ + + calcData = ((0x3800 & valueOfReg) >> 11) + ((0x2000000 & valueOfReg) >> 22); + deviceParam -> ale2Wr = calcData; /* Ale To Write */ + + calcData = ((0x1c000 & valueOfReg) >> 14) + ((0x4000000 & valueOfReg) >> 23); + deviceParam -> wrLow = calcData; /* Write Active */ + + calcData = ((0xe0000 & valueOfReg) >> 17) + ((0x8000000 & valueOfReg) >> 24); + deviceParam -> wrHigh = calcData; /* Write High */ + + calcData = ((0x300000 & valueOfReg) >> 20); + switch (calcData) + { + case 0: + deviceParam -> deviceWidth = 1; /* one Byte - 8-bit */ + break; + case 1: + deviceParam -> deviceWidth = 2; /* two Bytes - 16-bit */ + break; + case 2: + deviceParam -> deviceWidth = 4; /* four Bytes - 32-bit */ + break; + case 3: + deviceParam -> deviceWidth = 8; /* eight Bytes - 64-bit */ + break; + default: + deviceParam -> deviceWidth = 1; + break; + } + return true; +} + +/******************************************************************** +* memorySetDeviceParam - This function used for setting device parameters to +* DEVICE BANK PARAMETERS REGISTER +* +* +* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK +* PARAMETERS REGISTER +* - deviceNum : number of device +* Returns: false if one of the parameters is erroneous,true otherwise. +*********************************************************************/ +bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum) +{ + unsigned int valueForReg; + + if((deviceParam -> turnOff >= 0xf) || (deviceParam -> acc2First >= 0x1f) || + (deviceParam -> acc2Next >= 0x1f) || (deviceParam -> ale2Wr >= 0xf) || + (deviceParam -> wrLow >= 0xf) || (deviceParam -> wrHigh >= 0xf)) + return false; + valueForReg = (((deviceParam -> turnOff) & 0x7) | + (((deviceParam -> turnOff) & 0x8) << 19) | + (((deviceParam -> acc2First) & 0xf) << 3) | + (((deviceParam -> acc2First) & 0x10) << 19) | + (((deviceParam -> acc2Next) & 0xf) << 7) | + (((deviceParam -> acc2Next) & 0x10) << 20) | + (((deviceParam -> ale2Wr) & 0x7) << 11) | + (((deviceParam -> ale2Wr) & 0xf) << 22) | + (((deviceParam -> wrLow) & 0x7) << 14) | + (((deviceParam -> wrLow) & 0xf) << 23) | + (((deviceParam -> wrHigh) & 0x7) << 17) | + (((deviceParam -> wrHigh) & 0xf) << 24)); + /* insert the device width: */ + switch(deviceParam->deviceWidth) + { + case 1: + valueForReg = valueForReg | _8BIT; + break; + case 2: + valueForReg = valueForReg | _16BIT; + break; + case 4: + valueForReg = valueForReg | _32BIT; + break; + case 8: + valueForReg = valueForReg | _64BIT; + break; + default: + valueForReg = valueForReg | _8BIT; + break; + } + GT_REG_WRITE(DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg); + return true; +} diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S new file mode 100644 index 0000000..438dea6 --- /dev/null +++ b/board/evb64260/misc.S @@ -0,0 +1,182 @@ +#include +#include <74xx_7xx.h> +#include + +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_ECC + /* Galileo specific asm code for initializing ECC */ + .globl board_relocate_rom +board_relocate_rom: + mflr r7 + /* update the location of the GT registers */ + lis r11, CFG_GT_REGS@h + /* if we're using ECC, we must use the DMA engine to copy ourselves */ + bl start_idma_transfer_0 + bl wait_for_idma_0 + bl stop_idma_engine_0 + + mtlr r7 + blr + + .globl board_init_ecc +board_init_ecc: + mflr r7 + /* NOTE: r10 still contains the location we've been relocated to + * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + + /* now that we're running from ram, init the rest of main memory + * for ECC use */ + lis r8, CFG_MONITOR_LEN@h + ori r8, r8, CFG_MONITOR_LEN@l + + divw r3, r10, r8 + + /* set up the counter, and init the starting address */ + mtctr r3 + li r12, 0 + + /* bytes per transfer */ + mr r5, r8 +about_to_init_ecc: +1: mr r3, r12 + mr r4, r12 + bl start_idma_transfer_0 + bl wait_for_idma_0 + bl stop_idma_engine_0 + add r12, r12, r8 + bdnz 1b + + mtlr r7 + blr + + /* r3: dest addr + * r4: source addr + * r5: byte count + * r11: gt regbase + * trashes: r6, r5 + */ +start_idma_transfer_0: + /* set the byte count, including the OWN bit */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_BYTE_COUNT + stwbrx r5, 0, (r6) + + /* set the source address */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS + stwbrx r4, 0, (r6) + + /* set the dest address */ + mr r6, r11 + ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS + stwbrx r3, 0, (r6) + + /* set the next record pointer */ + li r5, 0 + mr r6, r11 + ori r6, r6, CHANNEL0NEXT_RECORD_POINTER + stwbrx r5, 0, (r6) + + /* set the low control register */ + /* bit 9 is NON chained mode, bit 31 is new style descriptors. + bit 12 is channel enable */ + ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) + /* 15 shifted by 16 (oris) == bit 31 */ + oris r5, r5, (1 << 15) + mr r6, r11 + ori r6, r6, CHANNEL0CONTROL + stwbrx r5, 0, (r6) + + blr + + /* this waits for the bytecount to return to zero, indicating + * that the trasfer is complete */ +wait_for_idma_0: + mr r5, r11 + lis r6, 0xff + ori r6, r6, 0xffff + ori r5, r5, CHANNEL0_DMA_BYTE_COUNT +1: lwbrx r4, 0, (r5) + and. r4, r4, r6 + bne 1b + + blr + + /* this turns off channel 0 of the idma engine */ +stop_idma_engine_0: + /* shut off the DMA engine */ + li r5, 0 + mr r6, r11 + ori r6, r6, CHANNEL0CONTROL + stwbrx r5, 0, (r6) + + blr +#endif + +#ifdef CFG_BOARD_ASM_INIT + /* NOTE: trashes r3-r7 */ + .globl board_asm_init +board_asm_init: + /* just move the GT registers to where they belong */ + lis r3, CFG_DFL_GT_REGS@h + ori r3, r3, CFG_DFL_GT_REGS@l + lis r4, CFG_GT_REGS@h + ori r4, r4, CFG_GT_REGS@l + li r5, INTERNAL_SPACE_DECODE + + /* test to see if we've already moved */ + lwbrx r6, r5, r4 + andi. r6, r6, 0xffff + rlwinm r7, r4, 12, 16, 31 + cmp cr0, r7, r6 + beqlr + + /* nope, have to move the registers */ + lwbrx r6, r5, r3 + andis. r6, r6, 0xffff + or r6, r6, r7 + stwbrx r6, r5, r3 + + /* now, poll for the change */ +1: lwbrx r7, r5, r4 + cmp cr0, r7, r6 + bne 1b + + /* done! */ + blr +#endif + +/* For use of the debug LEDs */ + .global led_on0 +led_on0: + xor r18, r18, r18 + lis r18, 0x1c80 + ori r18, r18, 0x8000 + stw r18, 0x0(r18) + sync + blr + + .global led_on1 +led_on1: + xor r18, r18, r18 + lis r18, 0x1c80 + ori r18, r18, 0xc000 + stw r18, 0x0(r18) + sync + blr + + .global led_on2 +led_on2: + xor r18, r18, r18 + lis r18, 0x1c81 + ori r18, r18, 0x0000 + stw r18, 0x0(r18) + sync + blr diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c new file mode 100644 index 0000000..ee623ca --- /dev/null +++ b/board/evb64260/mpsc.c @@ -0,0 +1,868 @@ +/* + * (C) Copyright 2001 + * John Clemens , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpsc.c - driver for console over the MPSC. + */ + +#include +#include +#include + +#include +#include "mpsc.h" + +int (*mpsc_putchar)(char ch) = mpsc_putchar_early; + +static volatile unsigned int *rx_desc_base=NULL; +static unsigned int rx_desc_index=0; +static volatile unsigned int *tx_desc_base=NULL; +static unsigned int tx_desc_index=0; + +/* local function declarations */ +static int galmpsc_connect(int channel, int connect); +static int galmpsc_route_serial(int channel, int connect); +static int galmpsc_route_rx_clock(int channel, int brg); +static int galmpsc_route_tx_clock(int channel, int brg); +static int galmpsc_write_config_regs(int mpsc, int mode); +static int galmpsc_config_channel_regs(int mpsc); +static int galmpsc_set_char_length(int mpsc, int value); +static int galmpsc_set_stop_bit_length(int mpsc, int value); +static int galmpsc_set_parity(int mpsc, int value); +static int galmpsc_enter_hunt(int mpsc); +static int galmpsc_set_brkcnt(int mpsc, int value); +static int galmpsc_set_tcschar(int mpsc, int value); +static int galmpsc_set_snoop(int mpsc, int value); +static int galmpsc_shutdown(int mpsc); + +static int galsdma_set_RFT(int channel); +static int galsdma_set_SFM(int channel); +static int galsdma_set_rxle(int channel); +static int galsdma_set_txle(int channel); +static int galsdma_set_burstsize(int channel, unsigned int value); +static int galsdma_set_RC(int channel, unsigned int value); + +static int galbrg_set_CDV(int channel, int value); +static int galbrg_enable(int channel); +static int galbrg_disable(int channel); +static int galbrg_set_clksrc(int channel, int value); +static int galbrg_set_CUV(int channel, int value); + +static void galsdma_enable_rx(void); + +/* static int galbrg_reset(int channel); */ + +#define SOFTWARE_CACHE_MANAGEMENT + +#ifdef SOFTWARE_CACHE_MANAGEMENT +#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} +#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} +#else +#define FLUSH_DCACHE(a,b) +#define FLUSH_AND_INVALIDATE_DCACHE(a,b) +#define INVALIDATE_DCACHE(a,b) +#endif + + +/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */ +#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack)) + +#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);} +#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M) + +#define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);} +#define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i]) + +/* make sure this isn't bigger than 16 long words (u-boot.h) */ +struct _tag_mirror_hack { + unsigned GALMPSC_PROTOCONF_REG_M[2]; /* 8008 */ + unsigned GALMPSC_CHANNELREG_1_M[2]; /* 800c */ + unsigned GALMPSC_CHANNELREG_2_M[2]; /* 8010 */ + unsigned GALBRG_0_CONFREG_M[2]; /* b200 */ + + unsigned GALMPSC_ROUTING_REGISTER_M; /* b400 */ + unsigned GALMPSC_RxC_ROUTE_M; /* b404 */ + unsigned GALMPSC_TxC_ROUTE_M; /* b408 */ + + unsigned int baudrate; /* current baudrate, for tsc delay calc */ +}; + +/* static struct _tag_mirror_hack *mh = NULL; */ + +/* special function for running out of flash. doesn't modify any + * global variables [josh] */ +int +mpsc_putchar_early(char ch) +{ + DECLARE_GLOBAL_DATA_PTR; + int mpsc=CHANNEL; + int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); + galmpsc_set_tcschar(mpsc,ch); + GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp|0x200); + +#define MAGIC_FACTOR (10*1000000) + + udelay(MAGIC_FACTOR / MIRROR_HACK->baudrate); + return 0; +} + +/* This is used after relocation, see serial.c and mpsc_init2 */ +static int +mpsc_putchar_sdma(char ch) +{ + volatile unsigned int *p; + unsigned int temp; + + + /* align the descriptor */ + p = tx_desc_base; + memset((void *)p, 0, 8 * sizeof(unsigned int)); + + /* fill one 64 bit buffer */ + /* word swap, pad with 0 */ + p[4] = 0; /* x */ + p[5] = (unsigned int)ch; /* x */ + + /* CHANGED completely according to GT64260A dox - NTL */ + p[0] = 0x00010001; /* 0 */ + p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* 4 */ + p[2] = 0; /* 8 */ + p[3] = (unsigned int)&p[4]; /* c */ + +#if 0 + p[9] = DESC_FIRST | DESC_LAST; + p[10] = (unsigned int)&p[0]; + p[11] = (unsigned int)&p[12]; +#endif + + FLUSH_DCACHE(&p[0], &p[8]); + + GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), + (unsigned int)&p[0]); + GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), + (unsigned int)&p[0]); + + temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); + temp |= (TX_DEMAND | TX_STOP); + GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); + + INVALIDATE_DCACHE(&p[1], &p[2]); + + while(p[1] & DESC_OWNER) { + udelay(100); + INVALIDATE_DCACHE(&p[1], &p[2]); + } + + return 0; +} + +char +mpsc_getchar(void) +{ + DECLARE_GLOBAL_DATA_PTR; + static unsigned int done = 0; + volatile char ch; + unsigned int len=0, idx=0, temp; + + volatile unsigned int *p; + + + do { + p=&rx_desc_base[rx_desc_index*8]; + + INVALIDATE_DCACHE(&p[0], &p[1]); + /* Wait for character */ + while (p[1] & DESC_OWNER){ + udelay(100); + INVALIDATE_DCACHE(&p[0], &p[1]); + } + + /* Handle error case */ + if (p[1] & (1<<15)) { + printf("oops, error: %08x\n", p[1]); + + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,CHANNEL,GALMPSC_REG_GAP); + temp |= (1 << 23); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2, CHANNEL,GALMPSC_REG_GAP, temp); + + /* Can't poll on abort bit, so we just wait. */ + udelay(100); + + galsdma_enable_rx(); + } + + /* Number of bytes left in this descriptor */ + len = p[0] & 0xffff; + + if (len) { + /* Where to look */ + idx = 5; + if (done > 3) idx = 4; + if (done > 7) idx = 7; + if (done > 11) idx = 6; + + INVALIDATE_DCACHE(&p[idx], &p[idx+1]); + ch = p[idx] & 0xff; + done++; + } + + if (done < len) { + /* this descriptor has more bytes still + * shift down the char we just read, and leave the + * buffer in place for the next time around + */ + p[idx] = p[idx] >> 8; + FLUSH_DCACHE(&p[idx], &p[idx+1]); + } + + if (done == len) { + /* nothing left in this descriptor. + * go to next one + */ + p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; + p[0] = 0x00100000; + FLUSH_DCACHE(&p[0], &p[1]); + /* Next descriptor */ + rx_desc_index = (rx_desc_index + 1) % RX_DESC; + done = 0; + } + } while (len==0); /* galileo bug.. len might be zero */ + + return ch; +} + +int +mpsc_test_char(void) +{ + volatile unsigned int *p=&rx_desc_base[rx_desc_index*8]; + + INVALIDATE_DCACHE(&p[1], &p[2]); + + if (p[1] & DESC_OWNER) return 0; + else return 1; +} + +int +mpsc_init(int baud) +{ + DECLARE_GLOBAL_DATA_PTR; + + memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack)); + MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff; + + /* BRG CONFIG */ + galbrg_set_baudrate(CHANNEL, baud); +#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) + galbrg_set_clksrc(CHANNEL,0x8); /* connect TCLK -> BRG */ +#else + galbrg_set_clksrc(CHANNEL,0); +#endif + galbrg_set_CUV(CHANNEL, 0); + galbrg_enable(CHANNEL); + + /* Set up clock routing */ + galmpsc_connect(CHANNEL, GALMPSC_CONNECT); + galmpsc_route_serial(CHANNEL, GALMPSC_CONNECT); + galmpsc_route_rx_clock(CHANNEL, CHANNEL); + galmpsc_route_tx_clock(CHANNEL, CHANNEL); + + /* reset MPSC state */ + galmpsc_shutdown(CHANNEL); + + /* SDMA CONFIG */ + galsdma_set_burstsize(CHANNEL, L1_CACHE_BYTES/8); /* in 64 bit words (8 bytes) */ + galsdma_set_txle(CHANNEL); + galsdma_set_rxle(CHANNEL); + galsdma_set_RC(CHANNEL, 0xf); + galsdma_set_SFM(CHANNEL); + galsdma_set_RFT(CHANNEL); + + /* MPSC CONFIG */ + galmpsc_write_config_regs(CHANNEL, GALMPSC_UART); + galmpsc_config_channel_regs(CHANNEL); + galmpsc_set_char_length(CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ + galmpsc_set_parity(CHANNEL, GALMPSC_PARITY_NONE); /* N */ + galmpsc_set_stop_bit_length(CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ + + /* COMM_MPSC CONFIG */ +#ifdef SOFTWARE_CACHE_MANAGEMENT + galmpsc_set_snoop(CHANNEL, 0); /* disable snoop */ +#else + galmpsc_set_snoop(CHANNEL, 1); /* enable snoop */ +#endif + + return 0; +} + +void +mpsc_init2(void) +{ + int i; + + mpsc_putchar = mpsc_putchar_sdma; + + /* RX descriptors */ + rx_desc_base = (unsigned int *)malloc(((RX_DESC+1)*8) * + sizeof(unsigned int)); + + /* align descriptors */ + rx_desc_base = (unsigned int *) + (((unsigned int)rx_desc_base+32) & 0xFFFFFFF0); + + rx_desc_index = 0; + + memset((void *)rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int)); + + for (i = 0; i < RX_DESC; i++) { + rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; /* Buffer */ + rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[(i+1)*8]; /* Next descriptor */ + rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* Command & control */ + rx_desc_base[i*8] = 0x00100000; + } + rx_desc_base[(i-1)*8 + 2] = (unsigned int)&rx_desc_base[0]; + + FLUSH_DCACHE(&rx_desc_base[0], &rx_desc_base[RX_DESC*8]); + GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF), + (unsigned int)&rx_desc_base[0]); + + /* TX descriptors */ + tx_desc_base = (unsigned int *)malloc(((TX_DESC+1)*8) * + sizeof(unsigned int)); + + /* align descriptors */ + tx_desc_base = (unsigned int *) + (((unsigned int)tx_desc_base+32) & 0xFFFFFFF0); + + tx_desc_index = -1; + + memset((void *)tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int)); + + for (i = 0; i < TX_DESC; i++) { + tx_desc_base[i*8 + 5] = (unsigned int)0x23232323; + tx_desc_base[i*8 + 4] = (unsigned int)0x23232323; + tx_desc_base[i*8 + 3] = (unsigned int)&tx_desc_base[i*8 + 4]; + tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[(i+1)*8]; + tx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; + + /* set sbytecnt and shadow byte cnt to 1 */ + tx_desc_base[i*8] = 0x00010001; + } + tx_desc_base[(i-1)*8 + 2] = (unsigned int)&tx_desc_base[0]; + + FLUSH_DCACHE(&tx_desc_base[0], &tx_desc_base[TX_DESC*8]); + + udelay(100); + + galsdma_enable_rx(); + + return; +} + +int +galbrg_set_baudrate(int channel, int rate) +{ + DECLARE_GLOBAL_DATA_PTR; + int clock; + + galbrg_disable(channel); + +#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) + /* from tclk */ + clock = (CFG_BUS_HZ/(16*rate)) - 1; +#else + clock = (3686400/(16*rate)) - 1; +#endif + + galbrg_set_CDV(channel, clock); + + galbrg_enable(channel); + + MIRROR_HACK->baudrate = rate; + + return 0; +} + +/* ------------------------------------------------------------------ */ + +/* Below are all the private functions that no one else needs */ + +static int +galbrg_set_CDV(int channel, int value) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); + temp &= 0xFFFF0000; + temp |= (value & 0x0000FFFF); + GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel,GALBRG_REG_GAP, temp); + + return 0; +} + +static int +galbrg_enable(int channel) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); + temp |= 0x00010000; + GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); + + return 0; +} + +static int +galbrg_disable(int channel) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); + temp &= 0xFFFEFFFF; + GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); + + return 0; +} + +static int +galbrg_set_clksrc(int channel, int value) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP); + temp &= 0xFF83FFFF; + temp |= (value << 18); + GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp); + + return 0; +} + +static int +galbrg_set_CUV(int channel, int value) +{ + GT_REG_WRITE(GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); + + return 0; +} + +#if 0 +static int +galbrg_reset(int channel) +{ + unsigned int temp; + + temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); + temp |= 0x20000; + GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); + + return 0; +} +#endif + +static int +galsdma_set_RFT(int channel) +{ + unsigned int temp; + + temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); + temp |= 0x00000001; + GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); + + return 0; +} + +static int +galsdma_set_SFM(int channel) +{ + unsigned int temp; + + temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); + temp |= 0x00000002; + GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); + + return 0; +} + +static int +galsdma_set_rxle(int channel) +{ + unsigned int temp; + + temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); + temp |= 0x00000040; + GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); + + return 0; +} + +static int +galsdma_set_txle(int channel) +{ + unsigned int temp; + + temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); + temp |= 0x00000080; + GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); + + return 0; +} + +static int +galsdma_set_RC(int channel, unsigned int value) +{ + unsigned int temp; + + temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); + temp &= ~0x0000003c; + temp |= (value << 2); + GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); + + return 0; +} + +static int +galsdma_set_burstsize(int channel, unsigned int value) +{ + unsigned int temp; + + temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); + temp &= 0xFFFFCFFF; + switch (value) { + case 8: + GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), + (temp | (0x3 << 12))); + break; + + case 4: + GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), + (temp | (0x2 << 12))); + break; + + case 2: + GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), + (temp | (0x1 << 12))); + break; + + case 1: + GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), + (temp | (0x0 << 12))); + break; + + default: + return -1; + break; + } + + return 0; +} + +static int +galmpsc_connect(int channel, int connect) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER); + + if ((channel == 0) && connect) + temp &= ~0x00000007; + else if ((channel == 1) && connect) + temp &= ~(0x00000007 << 6); + else if ((channel == 0) && !connect) + temp |= 0x00000007; + else + temp |= (0x00000007 << 6); + + /* Just in case... */ + temp &= 0x3fffffff; + + GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp); + + return 0; +} + +static int +galmpsc_route_serial(int channel, int connect) +{ + unsigned int temp; + + temp = GTREGREAD(GALMPSC_SERIAL_MULTIPLEX); + + if ((channel == 0) && connect) + temp |= 0x00000100; + else if ((channel == 1) && connect) + temp |= 0x00001000; + else if ((channel == 0) && !connect) + temp &= ~0x00000100; + else + temp &= ~0x00001000; + + GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX,temp); + + return 0; +} + +static int +galmpsc_route_rx_clock(int channel, int brg) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE); + + if (channel == 0) + temp |= brg; + else + temp |= (brg << 8); + + GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp); + + return 0; +} + +static int +galmpsc_route_tx_clock(int channel, int brg) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE); + + if (channel == 0) + temp |= brg; + else + temp |= (brg << 8); + + GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp); + + return 0; +} + +static int +galmpsc_write_config_regs(int mpsc, int mode) +{ + if (mode == GALMPSC_UART) { + /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ + GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP), + 0x000004c4); + + /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ + GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP), + 0x024003f8); + /* 22 2222 1111 */ + /* 54 3210 9876 */ + /* 0000 0010 0000 0000 */ + /* 1 */ + /* 098 7654 3210 */ + /* 0000 0011 1111 1000 */ + } else + return -1; + + return 0; +} + +static int +galmpsc_config_channel_regs(int mpsc) +{ + DECLARE_GLOBAL_DATA_PTR; + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0); + GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1); + GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0); + GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0); + GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0); + GT_REG_WRITE(GALMPSC_CHANNELREG_7+(mpsc*GALMPSC_REG_GAP), 0); + GT_REG_WRITE(GALMPSC_CHANNELREG_8+(mpsc*GALMPSC_REG_GAP), 0); + GT_REG_WRITE(GALMPSC_CHANNELREG_9+(mpsc*GALMPSC_REG_GAP), 0); + GT_REG_WRITE(GALMPSC_CHANNELREG_10+(mpsc*GALMPSC_REG_GAP), 0); + + galmpsc_set_brkcnt(mpsc, 0x3); + galmpsc_set_tcschar(mpsc, 0xab); + + return 0; +} + +static int +galmpsc_set_brkcnt(int mpsc, int value) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); + temp &= 0x0000FFFF; + temp |= (value << 16); + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); + + return 0; +} + +static int +galmpsc_set_tcschar(int mpsc, int value) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); + temp &= 0xFFFF0000; + temp |= value; + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); + + return 0; +} + +static int +galmpsc_set_char_length(int mpsc, int value) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); + temp &= 0xFFFFCFFF; + temp |= (value << 12); + GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp); + + return 0; +} + +static int +galmpsc_set_stop_bit_length(int mpsc, int value) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); + temp |= (value << 14); + GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp); + + return 0; +} + +static int +galmpsc_set_parity(int mpsc, int value) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int temp; + + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); + if (value != -1) { + temp &= 0xFFF3FFF3; + temp |= ((value << 18) | (value << 2)); + temp |= ((value << 17) | (value << 1)); + } else { + temp &= 0xFFF1FFF1; + } + + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); + + return 0; +} + +static int +galmpsc_enter_hunt(int mpsc) +{ + DECLARE_GLOBAL_DATA_PTR; + int temp; + + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); + temp |= 0x80000000; + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); + + /* Should Poll on Enter Hunt bit, but the register is write-only */ + /* errata suggests pausing 100 system cycles */ + udelay(100); + + return 0; +} + + +static int +galmpsc_shutdown(int mpsc) +{ + DECLARE_GLOBAL_DATA_PTR; +#if 0 + unsigned int temp; + + /* cause RX abort (clears RX) */ + temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); + temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; + temp &= ~MPSC_ENTER_HUNT; + GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp); +#endif + + GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0); + GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, + SDMA_TX_ABORT | SDMA_RX_ABORT); + + /* shut down the MPSC */ + GT_REG_WRITE(GALMPSC_MCONF_LOW, 0); + GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0); + GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0); + + udelay(100); + + /* shut down the sdma engines. */ + /* reset config to default */ + GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF, + 0x000000fc); + + udelay(100); + + /* clear the SDMA current and first TX and RX pointers */ + GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); + GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); + GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); + + udelay(100); + + return 0; +} + +static void +galsdma_enable_rx(void) +{ + int temp; + + /* Enable RX processing */ + temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); + temp |= RX_ENABLE; + GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); + + galmpsc_enter_hunt(CHANNEL); +} + +static int +galmpsc_set_snoop(int mpsc, int value) +{ + int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW; + int temp=GTREGREAD(reg); + if(value) + temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30); + else + temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30)); + GT_REG_WRITE(reg, temp); + return 0; +} diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h new file mode 100644 index 0000000..54b642a --- /dev/null +++ b/board/evb64260/mpsc.h @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2001 + * John Clemens , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpsc.h - header file for MPSC in uart mode (console driver) + */ + +#ifndef __MPSC_H__ +#define __MPSC_H__ + +/* include actual Galileo defines */ +#include + +/* driver related defines */ + +int mpsc_init(int baud); +void mpsc_init2(void); +char mpsc_getchar(void); +int mpsc_test_char(void); +int galbrg_set_baudrate(int channel, int rate); + +int mpsc_putchar_early(char ch); +extern int (*mpsc_putchar)(char ch); + +#define CHANNEL CONFIG_MPSC_PORT + +#define TX_DESC 5 +#define RX_DESC 20 + +#define DESC_FIRST 0x00010000 +#define DESC_LAST 0x00020000 +#define DESC_OWNER 0x80000000 + +#define TX_DEMAND 0x00800000 +#define TX_STOP 0x00010000 +#define RX_ENABLE 0x00000080 + +#define SDMA_RX_ABORT (1 << 15) +#define SDMA_TX_ABORT (1 << 31) +#define MPSC_TX_ABORT (1 << 7) +#define MPSC_RX_ABORT (1 << 23) +#define MPSC_ENTER_HUNT (1 << 31) + +/* MPSC defines */ + +#define GALMPSC_CONNECT 0x1 +#define GALMPSC_DISCONNECT 0x0 + +#define GALMPSC_UART 0x1 + +#define GALMPSC_STOP_BITS_1 0x0 +#define GALMPSC_STOP_BITS_2 0x1 +#define GALMPSC_CHAR_LENGTH_8 0x3 +#define GALMPSC_CHAR_LENGTH_7 0x2 + +#define GALMPSC_PARITY_ODD 0x0 +#define GALMPSC_PARITY_EVEN 0x2 +#define GALMPSC_PARITY_MARK 0x3 +#define GALMPSC_PARITY_SPACE 0x1 +#define GALMPSC_PARITY_NONE -1 + +#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ +#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ +#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ +#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ +#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ +#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ +#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ + +#define GALMPSC_REG_GAP 0x1000 + +#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ +#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ +#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ +#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ +#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ +#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ +#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ +#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ +#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ +#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ +#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ +#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ + +#define GALSDMA_COMMAND_FIRST (1 << 16) +#define GALSDMA_COMMAND_LAST (1 << 17) +#define GALSDMA_COMMAND_ENABLEINT (1 << 23) +#define GALSDMA_COMMAND_AUTO (1 << 30) +#define GALSDMA_COMMAND_OWNER (1 << 31) + +#define GALSDMA_RX 0 +#define GALSDMA_TX 1 + +/* CHANNEL2 should be CHANNEL1, according to documentation, + * but to work with the current GTREGS file... + */ +#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ +#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ +#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ +#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ +#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ +#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ +#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ +#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ +#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ +#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ +#define GALSDMA_REG_DIFF 0x2000 + +/* WRONG in gt64260R.h */ +#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ +#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ + +#define GALSDMA_MODE_UART 0 +#define GALSDMA_MODE_BISYNC 1 +#define GALSDMA_MODE_HDLC 2 +#define GALSDMA_MODE_TRANSPARENT 3 + +#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ +#define GALBRG_REG_GAP 0x0008 +#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ + +#endif /* __MPSC_H__ */ diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c new file mode 100644 index 0000000..59b9acb --- /dev/null +++ b/board/evb64260/pci.c @@ -0,0 +1,760 @@ +/* PCI.c - PCI functions */ + +/* Copyright - Galileo technology. */ + +#include +#include + +#include + +static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { +#ifdef CONFIG_ZUMA_V2 + {0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0}, + {0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0} +#else /* EVB??? This is a guess */ + {0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0}, + {0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0} +#endif +}; + +static const unsigned int pci_p2p_configuration_reg[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION +}; + +static const unsigned int pci_configuration_address[] = { + PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS +}; + +static const unsigned int pci_configuration_data[] = { + PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, + PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER +}; + +static const unsigned int pci_error_cause_reg[] = { + PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE +}; + +static const unsigned int pci_arbiter_control[] = { + PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL +}; + +static const unsigned int pci_snoop_control_base_0_low[] = { + PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW +}; +static const unsigned int pci_snoop_control_top_0[] = { + PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 +}; + +static const unsigned int pci_access_control_base_0_low[] = { + PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW +}; +static const unsigned int pci_access_control_top_0[] = { + PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 +}; + +static const unsigned int pci_scs_bank_size[2][4] = { + {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, + PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, + {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, + PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} +}; + +static const unsigned int pci_p2p_configuration[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION +}; + +static unsigned int local_buses[] = { 0, 0 }; + +/******************************************************************** +* pciWriteConfigReg - Write to a PCI configuration register +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* +* +* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum, unsigned int data) +{ + volatile unsigned int DataForAddrReg; + unsigned int functionNum; + unsigned int busNum = PCI_BUS (pciDevNum); + unsigned int addr; + + if (pciDevNum > 32) /* illegal device Number */ + return; + if (pciDevNum == SELF) { /* configure our configuration space. */ + pciDevNum = + (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & + 0x1f; + busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & + 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = + (regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); + GT_REG_READ (pci_configuration_address[host], &addr); + if (addr != DataForAddrReg) + return; + GT_REG_WRITE (pci_configuration_data[host], data); +} + +/******************************************************************** +* pciReadConfigReg - Read from a PCI0 configuration register +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec) +* pciDevNum: The device number needs to be addressed. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum) +{ + volatile unsigned int DataForAddrReg; + unsigned int data; + unsigned int functionNum; + unsigned int busNum = PCI_BUS (pciDevNum); + + if (pciDevNum > 32) /* illegal device Number */ + return 0xffffffff; + if (pciDevNum == SELF) { /* configure our configuration space. */ + pciDevNum = + (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & + 0x1f; + busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & + 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = + (regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); + GT_REG_READ (pci_configuration_address[host], &data); + if (data != DataForAddrReg) + return 0xffffffff; + GT_REG_READ (pci_configuration_data[host], &data); + return data; +} + +/******************************************************************** +* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. +* +* Inputs: unsigned int regOffset - The register offset as it apears in the +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +* The configuration Address is configure as type-I (bits[1:0] = '01') due to +* PCI spec referring to P2P. +* +*********************************************************************/ +void pciOverBridgeWriteConfigReg (PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum, unsigned int data) +{ + unsigned int DataForReg; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if (pciDevNum == SELF) { /* This board */ + DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; + } else { + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | + BIT31 | BIT0; + } + GT_REG_WRITE (pci_configuration_address[host], DataForReg); + if (pciDevNum == SELF) { /* This board */ + GT_REG_WRITE (pci_configuration_data[host], data); + } else { /* configuration Transaction over the pci. */ + + /* The PCI is working in LE Mode So it swap the Data. */ + GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data)); + } +} + + +/******************************************************************** +* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum) +{ + unsigned int DataForReg; + unsigned int data; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if (pciDevNum == SELF) { /* This board */ + DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; + } else { /* agent on another bus */ + + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | + BIT0 | BIT31; + } + GT_REG_WRITE (pci_configuration_address[host], DataForReg); + if (pciDevNum == SELF) { /* This board */ + GT_REG_READ (pci_configuration_data[host], &data); + return data; + } else { /* The PCI is working in LE Mode So it swap the Data. */ + + GT_REG_READ (pci_configuration_data[host], &data); + return WORD_SWAP (data); + } +} + +/******************************************************************** +* pciGetRegOffset - Gets the register offset for this region config. +* +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI register base address +*********************************************************************/ +static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) +{ + switch (host) { + case PCI_HOST0: + switch (region) { + case PCI_IO: + return PCI_0I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: + return PCI_0MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: + return PCI_0MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: + return PCI_0MEMORY3_LOW_DECODE_ADDRESS; + } + case PCI_HOST1: + switch (region) { + case PCI_IO: + return PCI_1I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: + return PCI_1MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: + return PCI_1MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: + return PCI_1MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: + return PCI_1MEMORY3_LOW_DECODE_ADDRESS; + } + } + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; +} + +static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) +{ + switch (host) { + case PCI_HOST0: + switch (region) { + case PCI_IO: + return PCI_0I_O_ADDRESS_REMAP; + case PCI_REGION0: + return PCI_0MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: + return PCI_0MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: + return PCI_0MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: + return PCI_0MEMORY3_ADDRESS_REMAP; + } + case PCI_HOST1: + switch (region) { + case PCI_IO: + return PCI_1I_O_ADDRESS_REMAP; + case PCI_REGION0: + return PCI_1MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: + return PCI_1MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: + return PCI_1MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: + return PCI_1MEMORY3_ADDRESS_REMAP; + } + } + return PCI_0MEMORY0_ADDRESS_REMAP; +} + +bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, + unsigned int bankBase, unsigned int bankLength) +{ + unsigned int low = 0xfff; + unsigned int high = 0x0; + unsigned int regOffset = pciGetRegOffset (host, region); + unsigned int remapOffset = pciGetRemapOffset (host, region); + + if (bankLength != 0) { + low = (bankBase >> 20) & 0xfff; + high = ((bankBase + bankLength) >> 20) - 1; + } + + GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ + GT_REG_WRITE (regOffset + 8, high); + + if (bankLength != 0) { /* must do AFTER writing maps */ + GT_REG_WRITE (remapOffset, remapBase >> 20); /* sorry, 32 bits only. + dont support upper 32 + in this driver */ + } + return true; +} + +unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) +{ + unsigned int low; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, &low); + return (low & 0xfff) << 20; +} + +unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) +{ + unsigned int low, high; + unsigned int regOffset = pciGetRegOffset (host, region); + + GT_REG_READ (regOffset, &low); + GT_REG_READ (regOffset + 8, &high); + high &= 0xfff; + low &= 0xfff; + if (high <= low) + return 0; + return (high + 1 - low) << 20; +} + +/******************************************************************** +* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. +* +* Inputs: base and size of PCI SCS +*********************************************************************/ +void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, + unsigned int pciDramBase, unsigned int pciDramSize) +{ + pciDramBase = pciDramBase & 0xfffff000; + pciDramBase = pciDramBase | (pciReadConfigReg (host, + PCI_SCS_0_BASE_ADDRESS + + 4 * bank, + SELF) & 0x00000fff); + pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF, + pciDramBase); + if (pciDramSize == 0) + pciDramSize++; + GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); +} + + +/******************************************************************** +* pciSetRegionFeatures - This function modifys one of the 8 regions with +* feature bits given as an input. +* - Be advised to check the spec before modifying them. +* Inputs: PCI_PROTECT_REGION region - one of the eight regions. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. +* Returns: false if one of the parameters is erroneous true otherwise. +*********************************************************************/ +bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, + unsigned int features, unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int accessLow; + unsigned int accessHigh; + unsigned int accessTop = baseAddress + regionLength; + + if (regionLength == 0) { /* close the region. */ + pciDisableAccessRegion (host, region); + return true; + } + /* base Address is store is bits [11:0] */ + accessLow = (baseAddress & 0xfff00000) >> 20; + /* All the features are update according to the defines in pci.h (to be on + the safe side we disable bits: [11:0] */ + accessLow = accessLow | (features & 0xfffff000); + /* write to the Low Access Region register */ + GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, + accessLow); + + accessHigh = (accessTop & 0xfff00000) >> 20; + + /* write to the High Access Region register */ + GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, + accessHigh - 1); + return true; +} + +/******************************************************************** +* pciDisableAccessRegion - Disable The given Region by writing MAX size +* to its low Address and MIN size to its high Address. +* +* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. +* Returns: N/A. +*********************************************************************/ +void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) +{ + /* writing back the registers default values. */ + GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, + 0x01001fff); + GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); +} + +/******************************************************************** +* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true. +*********************************************************************/ +bool pciArbiterEnable (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); + return true; +} + +/******************************************************************** +* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true +*********************************************************************/ +bool pciArbiterDisable (PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); + return true; +} + +/******************************************************************** +* pciParkingDisable - Park on last option disable, with this function you can +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. +* +* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* Returns: true +*********************************************************************/ +bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, + PCI_AGENT_PARK externalAgent0, + PCI_AGENT_PARK externalAgent1, + PCI_AGENT_PARK externalAgent2, + PCI_AGENT_PARK externalAgent3, + PCI_AGENT_PARK externalAgent4, + PCI_AGENT_PARK externalAgent5) +{ + unsigned int regData; + unsigned int writeData; + + GT_REG_READ (pci_arbiter_control[host], ®Data); + writeData = (internalAgent << 14) + (externalAgent0 << 15) + + (externalAgent1 << 16) + (externalAgent2 << 17) + + (externalAgent3 << 18) + (externalAgent4 << 19) + + (externalAgent5 << 20); + regData = (regData & ~(0x7f << 14)) | writeData; + GT_REG_WRITE (pci_arbiter_control[host], regData); + return true; +} + +/******************************************************************** +* pciSetRegionSnoopMode - This function modifys one of the 4 regions which +* supports Cache Coherency in the PCI_n interface. +* Inputs: region - One of the four regions. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. +* Returns: false if one of the parameters is wrong otherwise return true. +*********************************************************************/ +bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, + PCI_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int snoopXbaseAddress; + unsigned int snoopXtopAddress; + unsigned int data; + unsigned int snoopHigh = baseAddress + regionLength; + + if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) + return false; + snoopXbaseAddress = + pci_snoop_control_base_0_low[host] + 0x10 * region; + snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; + if (regionLength == 0) { /* closing the region */ + GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); + GT_REG_WRITE (snoopXtopAddress, 0); + return true; + } + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + data = (baseAddress >> 20) | snoopType << 12; + GT_REG_WRITE (snoopXbaseAddress, data); + snoopHigh = (snoopHigh & 0xfff00000) >> 20; + GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); + return true; +} + +/* + * + */ + +static int gt_read_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 * value) +{ + int bus = PCI_BUS (dev); + + if ((bus == local_buses[0]) || (bus == local_buses[1])) { + *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, + PCI_DEV (dev)); + } else { + *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> + cfg_addr, offset, + PCI_DEV (dev), bus); + } + return 0; +} + +static int gt_write_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + int bus = PCI_BUS (dev); + + if ((bus == local_buses[0]) || (bus == local_buses[1])) { + pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, + PCI_DEV (dev), value); + } else { + pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, + offset, PCI_DEV (dev), value, + bus); + } + return 0; +} + +/* + * + */ + +static void gt_setup_ide (struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; + u32 bar_response, bar_value; + int bar; + + for (bar = 0; bar < 6; bar++) { + pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, + 0x0); + pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, + &bar_response); + + pciauto_region_allocate (bar_response & + PCI_BASE_ADDRESS_SPACE_IO ? hose-> + pci_io : hose->pci_mem, ide_bar[bar], + &bar_value); + + pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, + bar_value); + } +} + +#ifndef CONFIG_P3G4 +static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char pin, irq; + + pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); + + if (pin == 1) { /* only allow INT A */ + irq = pci_irq_swizzle[(PCI_HOST) hose-> + cfg_addr][PCI_DEV (dev)]; + if (irq) + pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); + } +} +#endif + +struct pci_config_table gt_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, + + {} +}; + +struct pci_controller pci0_hose = { +#ifndef CONFIG_P3G4 + fixup_irq:gt_fixup_irq, +#endif + config_table:gt_config_table, +}; + +struct pci_controller pci1_hose = { +#ifndef CONFIG_P3G4 + fixup_irq:gt_fixup_irq, +#endif + config_table:gt_config_table, +}; + +void pci_init_board (void) +{ + unsigned int command; + + pci0_hose.first_busno = 0; + pci0_hose.last_busno = 0xff; + local_buses[0] = pci0_hose.first_busno; + /* PCI memory space */ + pci_set_region (pci0_hose.regions + 0, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (pci0_hose.regions + 1, + CFG_PCI0_IO_SPACE_PCI, + CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + + pci_set_ops (&pci0_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + + pci0_hose.region_count = 2; + + pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; + + pci_register_hose (&pci0_hose); + +#ifndef CONFIG_P3G4 + pciArbiterEnable (PCI_HOST0); + pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); +#endif + + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + + pci0_hose.last_busno = pci_hose_scan (&pci0_hose); + + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + + pci1_hose.first_busno = pci0_hose.last_busno + 1; + pci1_hose.last_busno = 0xff; + pci1_hose.current_busno = pci0_hose.current_busno; + local_buses[1] = pci1_hose.first_busno; + + /* PCI memory space */ + pci_set_region (pci1_hose.regions + 0, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (pci1_hose.regions + 1, + CFG_PCI1_IO_SPACE_PCI, + CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + + pci_set_ops (&pci1_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + + pci1_hose.region_count = 2; + + pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; + + pci_register_hose (&pci1_hose); + +#ifndef CONFIG_P3G4 + pciArbiterEnable (PCI_HOST1); + pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); +#endif + + command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); + + pci1_hose.last_busno = pci_hose_scan (&pci1_hose); + + command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); +} diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c new file mode 100644 index 0000000..8d63c6f --- /dev/null +++ b/board/evb64260/sdram_init.c @@ -0,0 +1,662 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* sdram_init.c - automatic memory sizing */ + +#include +#include <74xx_7xx.h> +#include +#include +#include +#include + +#include "eth.h" +#include "mpsc.h" +#include "i2c.h" +#include "64260.h" + +/* #define DEBUG */ +#define MAP_PCI + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +#define GB (1 << 30) + +/* structure to store the relevant information about an sdram bank */ +typedef struct sdram_info { + uchar drb_size; + uchar registered, ecc; + uchar tpar; + uchar tras_clocks; + uchar burst_len; + uchar banks, slot; + int size; /* detected size, not from I2C but from dram_size() */ +} sdram_info_t; + +#ifdef DEBUG +void dump_dimm_info (struct sdram_info *d) +{ + static const char *ecc_legend[] = { "", " Parity", " ECC" }; + + printf ("dimm%s %sDRAM: %dMibytes:\n", + ecc_legend[d->ecc], + d->registered ? "R" : "", (d->size >> 20)); + printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n", + d->drb_size, d->tpar, d->tras_clocks, d->burst_len, + d->banks, d->slot); +} +#endif + +static int +memory_map_bank (unsigned int bankNo, + unsigned int bankBase, unsigned int bankLength) +{ +#ifdef DEBUG + if (bankLength > 0) { + printf ("mapping bank %d at %08x - %08x\n", + bankNo, bankBase, bankBase + bankLength - 1); + } else { + printf ("unmapping bank %d\n", bankNo); + } +#endif + + memoryMapBank (bankNo, bankBase, bankLength); + + return 0; +} + +#ifdef MAP_PCI +static int +memory_map_bank_pci (unsigned int bankNo, + unsigned int bankBase, unsigned int bankLength) +{ + PCI_HOST host; + + for (host = PCI_HOST0; host <= PCI_HOST1; host++) { + const int features = + PREFETCH_ENABLE | + DELAYED_READ_ENABLE | + AGGRESSIVE_PREFETCH | + READ_LINE_AGGRESSIVE_PREFETCH | + READ_MULTI_AGGRESSIVE_PREFETCH | + MAX_BURST_4 | PCI_NO_SWAP; + + pciMapMemoryBank (host, bankNo, bankBase, bankLength); + + pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, + bankLength); + + pciSetRegionFeatures (host, bankNo, features, bankBase, + bankLength); + } + return 0; +} +#endif + +/* ------------------------------------------------------------------------- */ + +/* much of this code is based on (or is) the code in the pip405 port */ +/* thanks go to the authors of said port - Josh */ + + +/* + * translate ns.ns/10 coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short NS10to10PS (unsigned char spd_byte) +{ + unsigned short ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + return (ns * 100 + ns10 * 10); +} + +/* + * translate ns coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short NSto10PS (unsigned char spd_byte) +{ + return (spd_byte * 100); +} + +#ifdef CONFIG_ZUMA_V2 +static int check_dimm (uchar slot, sdram_info_t * info) +{ + /* assume 2 dimms, 2 banks each 256M - we dont have an + * dimm i2c so rely on the detection routines later */ + + memset (info, 0, sizeof (*info)); + + info->slot = slot; + info->banks = 2; /* Detect later */ + info->registered = 0; + info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit + but doesn't matter, both do same + thing in setup_sdram() */ + info->tpar = 3; + info->tras_clocks = 5; + info->burst_len = 4; +#ifdef CONFIG_ECC + info->ecc = 0; /* Detect later */ +#endif /* CONFIG_ECC */ + return 0; +} + +#elif defined(CONFIG_P3G4) + +static int check_dimm (uchar slot, sdram_info_t * info) +{ + memset (info, 0, sizeof (*info)); + + if (slot) + return 0; + + info->slot = slot; + info->banks = 1; + info->registered = 0; + info->drb_size = 4; + info->tpar = 3; + info->tras_clocks = 6; + info->burst_len = 4; +#ifdef CONFIG_ECC + info->ecc = 2; +#endif + return 0; +} + +#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */ + +/* This code reads the SPD chip on the sdram and populates + * the array which is passed in with the relevant information */ +static int check_dimm (uchar slot, sdram_info_t * info) +{ + DECLARE_GLOBAL_DATA_PTR; + uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; + int ret; + uchar rows, cols, sdram_banks, supp_cal, width, cal_val; + ulong tmemclk; + uchar trp_clocks, trcd_clocks; + uchar data[128]; + + get_clocks (); + + tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */ + +#ifdef CONFIG_EVB64260_750CX + if (0 != slot) { + printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,"); + printf (" called with slot=%d insetad!\n", slot); + return 0; + } +#endif + DP (puts ("before i2c read\n")); + + ret = i2c_read (addr, 0, 128, data, 0); + + DP (puts ("after i2c read\n")); + + /* zero all the values */ + memset (info, 0, sizeof (*info)); + + if (ret) { + DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + return 0; + } + + /* first, do some sanity checks */ + if (data[2] != 0x4) { + printf ("Not SDRAM in slot %d\n", slot); + return 0; + } + + /* get various information */ + rows = data[3]; + cols = data[4]; + info->banks = data[5]; + sdram_banks = data[17]; + width = data[13] & 0x7f; + + DP (printf + ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks)); + + /* check if the memory is registered */ + if (data[21] & (BIT1 | BIT4)) + info->registered = 1; + +#ifdef CONFIG_ECC + /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ + info->ecc = (data[11] & 2) >> 1; +#endif + + /* bit 1 is CL2, bit 2 is CL3 */ + supp_cal = (data[18] & 0x6) >> 1; + + /* compute the relevant clock values */ + trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk; + trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk; + info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk; + + DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n", + trp_clocks, trcd_clocks, info->tras_clocks)); + + /* try a CAS latency of 3 first... */ + cal_val = 0; + if (supp_cal & 3) { + if (NS10to10PS (data[9]) <= tmemclk) + cal_val = 3; + } + + /* then 2... */ + if (supp_cal & 2) { + if (NS10to10PS (data[23]) <= tmemclk) + cal_val = 2; + } + + DP (printf ("cal_val = %d\n", cal_val)); + + /* bummer, did't work... */ + if (cal_val == 0) { + DP (printf ("Couldn't find a good CAS latency\n")); + return 0; + } + + /* get the largest delay -- these values need to all be the same + * see Res#6 */ + info->tpar = cal_val; + if (trp_clocks > info->tpar) + info->tpar = trp_clocks; + if (trcd_clocks > info->tpar) + info->tpar = trcd_clocks; + + DP (printf ("tpar set to: %d\n", info->tpar)); + +#ifdef CFG_BROKEN_CL2 + if (info->tpar == 2) { + info->tpar = 3; + DP (printf ("tpar fixed-up to: %d\n", info->tpar)); + } +#endif + /* compute the module DRB size */ + info->drb_size = + (((1 << (rows + cols)) * sdram_banks) * width) / _16M; + + DP (printf ("drb_size set to: %d\n", info->drb_size)); + + /* find the burst len */ + info->burst_len = data[16] & 0xf; + if ((info->burst_len & 8) == 8) { + info->burst_len = 1; + } else if ((info->burst_len & 4) == 4) { + info->burst_len = 0; + } else { + return 0; + } + + info->slot = slot; + return 0; +} +#endif /* ! CONFIG_ZUMA_V2 */ + +static int setup_sdram_common (sdram_info_t info[2]) +{ + ulong tmp; + int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2; + + if (!info[0].banks && !info[1].banks) + return 0; + + if (info[0].banks) { + if (info[0].tpar > tpar) + tpar = info[0].tpar; + if (info[0].tras_clocks > tras_clocks) + tras_clocks = info[0].tras_clocks; + if (!info[0].registered) + registered = 0; + if (info[0].ecc != 2) + ecc = 0; + } + + if (info[1].banks) { + if (info[1].tpar > tpar) + tpar = info[1].tpar; + if (info[1].tras_clocks > tras_clocks) + tras_clocks = info[1].tras_clocks; + if (!info[1].registered) + registered = 0; + if (info[1].ecc != 2) + ecc = 0; + } + + /* SDRAM configuration */ + tmp = GTREGREAD (SDRAM_CONFIGURATION); + + /* Turn on physical interleave if both DIMMs + * have even numbers of banks. */ + if ((info[0].banks == 0 || info[0].banks == 2) && + (info[1].banks == 0 || info[1].banks == 2)) { + /* physical interleave on */ + tmp &= ~(1 << 15); + } else { + /* physical interleave off */ + tmp |= (1 << 15); + } + + tmp |= (registered << 17); + + /* Use buffer 1 to return read data to the CPU + * See Res #12 */ + tmp |= (1 << 26); + + GT_REG_WRITE (SDRAM_CONFIGURATION, tmp); + DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION))); + + /* SDRAM timing */ + tmp = (((tpar == 3) ? 2 : 1) | + (((tpar == 3) ? 2 : 1) << 2) | + (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8)); + +#ifdef CONFIG_ECC + /* Setup ECC */ + if (ecc == 2) + tmp |= 1 << 13; +#endif /* CONFIG_ECC */ + + GT_REG_WRITE (SDRAM_TIMING, tmp); + DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n", + GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks)); + + /* SDRAM address decode register */ + /* program this with the default value */ + GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2); + DP (printf ("SDRAM decode: %08x\n", + GTREGREAD (SDRAM_ADDRESS_DECODE))); + + return 0; +} + +/* sets up the GT properly with information passed in */ +static int setup_sdram (sdram_info_t * info) +{ + ulong tmp, check; + ulong *addr = 0; + int i; + + /* sanity checking */ + if (!info->banks) + return 0; + + /* ---------------------------- */ + /* Program the GT with the discovered data */ + + /* bank parameters */ + tmp = (0xf << 16); /* leave all virt bank pages open */ + + DP (printf ("drb_size: %d\n", info->drb_size)); + switch (info->drb_size) { + case 1: + tmp |= (1 << 14); + break; + case 4: + case 8: + tmp |= (2 << 14); + break; + case 16: + case 32: + tmp |= (3 << 14); + break; + default: + printf ("Error in dram size calculation\n"); + return 1; + } + + /* SDRAM bank parameters */ + /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ + GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp); + GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp); + DP (printf + ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, + info->slot * 2, (info->slot * 2) + 1, tmp)); + + /* set the SDRAM configuration for each bank */ + for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) { + DP (printf ("*** Running a MRS cycle for bank %d ***\n", i)); + + /* map the bank */ + memory_map_bank (i, 0, GB / 4); + + /* set SDRAM mode */ + GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3); + check = GTREGREAD (SDRAM_OPERATION_MODE); + + /* dummy write */ + *addr = 0; + + /* wait for the command to complete */ + while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0); + + /* switch back to normal operation mode */ + GT_REG_WRITE (SDRAM_OPERATION_MODE, 0); + check = GTREGREAD (SDRAM_OPERATION_MODE); + + /* unmap the bank */ + memory_map_bank (i, 0, 0); + DP (printf ("*** MRS cycle for bank %d done ***\n", i)); + } + + return 0; +} + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +static long int dram_size (long int *base, long int maxsize) +{ + volatile long int *addr, *b = base; + long int cnt, val, save1, save2; + +#define STARTVAL (1<<20) /* start test at 1M */ + for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); + cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + save1 = *addr; /* save contents of addr */ + save2 = *b; /* save contents of base */ + + *addr = cnt; /* write cnt to addr */ + *b = 0; /* put null at base */ + + /* check at base address */ + if ((*b) != 0) { + *addr = save1; /* restore *addr */ + *b = save2; /* restore *b */ + return (0); + } + val = *addr; /* read *addr */ + + *addr = save1; + *b = save2; + + if (val != cnt) { + /* fix boundary condition.. STARTVAL means zero */ + if (cnt == STARTVAL / sizeof (long)) + cnt = 0; + return (cnt * sizeof (long)); + } + } + return maxsize; +} + +/* ------------------------------------------------------------------------- */ + +/* U-Boot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int initdram (int board_type) +{ + ulong checkbank[4] = {[0 ... 3] = 0 }; + int bank_no; + ulong total; + int nhr; + sdram_info_t dimm_info[2]; + + + /* first, use the SPD to get info about the SDRAM */ + + /* check the NHR bit and skip mem init if it's already done */ + nhr = get_hid0 () & (1 << 16); + + if (nhr) { + printf ("Skipping SDRAM setup due to NHR bit being set\n"); + } else { + /* DIMM0 */ + check_dimm (0, &dimm_info[0]); + + /* DIMM1 */ +#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */ + check_dimm (1, &dimm_info[1]); +#else /* CONFIG_EVB64260_750CX */ + memset (&dimm_info[1], 0, sizeof (sdram_info_t)); +#endif + + /* unmap all banks */ + memory_map_bank (0, 0, 0); + memory_map_bank (1, 0, 0); + memory_map_bank (2, 0, 0); + memory_map_bank (3, 0, 0); + + /* Now, program the GT with the correct values */ + if (setup_sdram_common (dimm_info)) { + printf ("Setup common failed.\n"); + } + + if (setup_sdram (&dimm_info[0])) { + printf ("Setup for DIMM1 failed.\n"); + } + + if (setup_sdram (&dimm_info[1])) { + printf ("Setup for DIMM2 failed.\n"); + } + + /* set the NHR bit */ + set_hid0 (get_hid0 () | (1 << 16)); + } + /* next, size the SDRAM banks */ + + total = 0; + if (dimm_info[0].banks > 0) + checkbank[0] = 1; + if (dimm_info[0].banks > 1) + checkbank[1] = 1; + if (dimm_info[0].banks > 2) + printf ("Error, SPD claims DIMM1 has >2 banks\n"); + + if (dimm_info[1].banks > 0) + checkbank[2] = 1; + if (dimm_info[1].banks > 1) + checkbank[3] = 1; + if (dimm_info[1].banks > 2) + printf ("Error, SPD claims DIMM2 has >2 banks\n"); + + /* Generic dram sizer: works even if we don't have i2c DIMMs, + * as long as the timing settings are more or less correct */ + + /* + * pass 1: size all the banks, using first bat (0-256M) + * limitation: we only support 256M per bank due to + * us only having 1 BAT for all DRAM + */ + for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + /* skip over banks that are not populated */ + if (!checkbank[bank_no]) + continue; + + DP (printf ("checking bank %d\n", bank_no)); + + memory_map_bank (bank_no, 0, GB / 4); + checkbank[bank_no] = dram_size (NULL, GB / 4); + memory_map_bank (bank_no, 0, 0); + + DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no])); + } + + /* + * pass 2: contiguously map each bank into physical address + * space. + */ + dimm_info[0].banks = dimm_info[1].banks = 0; + for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + if (!checkbank[bank_no]) + continue; + + dimm_info[bank_no / 2].banks++; + dimm_info[bank_no / 2].size += checkbank[bank_no]; + + memory_map_bank (bank_no, total, checkbank[bank_no]); +#ifdef MAP_PCI + memory_map_bank_pci (bank_no, total, checkbank[bank_no]); +#endif + total += checkbank[bank_no]; + } + +#ifdef CONFIG_ECC +#ifdef CONFIG_ZUMA_V2 + /* + * We always enable ECC when bank 2 and 3 are unpopulated + * If we 2 or 3 are populated, we CAN'T support ECC. + * (Zuma boards only support ECC in banks 0 and 1; assume that + * in that configuration, ECC chips are mounted, even for stacked + * chips) + */ + if (checkbank[2] == 0 && checkbank[3] == 0) { + dimm_info[0].ecc = 2; + GT_REG_WRITE (SDRAM_TIMING, + GTREGREAD (SDRAM_TIMING) | (1 << 13)); + /* TODO: do we have to run MRS cycles again? */ + } +#endif /* CONFIG_ZUMA_V2 */ + + if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) { + puts ("[ECC] "); + } +#endif /* CONFIG_ECC */ + +#ifdef DEBUG + dump_dimm_info (&dimm_info[0]); + dump_dimm_info (&dimm_info[1]); +#endif + /* TODO: return at MOST 256M? */ + /* return total > GB/4 ? GB/4 : total; */ + return total; +} diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c new file mode 100644 index 0000000..d9c7a15 --- /dev/null +++ b/board/evb64260/serial.c @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * serial.c - serial support for the gal ev board + */ + +/* supports both the 16650 duart and the MPSC */ + +#include +#include +#include + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +#include +#endif + +#include "serial.h" + +#include "mpsc.h" + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, + (NS16550_t) CFG_NS16550_COM2 }; +#endif + +#ifdef CONFIG_MPSC + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; +#endif + + mpsc_init(gd->baudrate); + + /* init the DUART chans so that KGDB in the kernel can use them */ +#ifdef CFG_INIT_CHAN1 + NS16550_reinit(COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + NS16550_reinit(COM_PORTS[1], clock_divisor); +#endif + return (0); +} + +void +serial_putc(const char c) +{ + if (c == '\n') + mpsc_putchar('\r'); + + mpsc_putchar(c); +} + +int +serial_getc(void) +{ + return mpsc_getchar(); +} + +int +serial_tstc(void) +{ + return mpsc_test_char(); +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate); +} + +#else /* ! CONFIG_MPSC */ + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + (void)NS16550_init(COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + (void)NS16550_init(COM_PORTS[1], clock_divisor); +#endif + + return (0); +} + +void +serial_putc(const char c) +{ + if (c == '\n') + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); + + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); +} + +int +serial_getc(void) +{ + return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); +} + +int +serial_tstc(void) +{ + return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + NS16550_reinit(COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + NS16550_reinit(COM_PORTS[1], clock_divisor); +#endif +} + +#endif /* CONFIG_MPSC */ + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +void +kgdb_serial_init(void) +{ +} + +void +putDebugChar (int c) +{ + serial_putc (c); +} + +void +putDebugStr (const char *str) +{ + serial_puts (str); +} + +int +getDebugChar (void) +{ + return serial_getc(); +} + +void +kgdb_interruptible (int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ diff --git a/board/evb64260/serial.h b/board/evb64260/serial.h new file mode 100644 index 0000000..bac9253 --- /dev/null +++ b/board/evb64260/serial.h @@ -0,0 +1,63 @@ +/* serial.h - mostly useful for DUART serial_init in serial.c */ + +#ifndef __SERIAL_H__ +#define __SERIAL_H__ + +#if 0 + +#define B230400 1 +#define B115200 2 +#define B57600 4 +#define B38400 82 +#define B19200 163 +#define B9600 24 +#define B4800 651 +#define B2400 1302 +#define B1200 2604 +#define B600 5208 +#define B300 10417 +#define B150 20833 +#define B110 28409 +#define BDEFAULT B115200 + + /* this stuff is important to initialize + the DUART channels */ + +#define Scale 0x01L /* distance between port addresses */ +#define COM1 0x000003f8 /* Keyboard */ +#define COM2 0x000002f8 /* Host */ + + +/* Port Definitions relative to base COM port addresses */ +#define DataIn (0x00*Scale) /* data input port */ +#define DataOut (0x00*Scale) /* data output port */ +#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ +#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ +#define Ier (0x01*Scale) /* interrupt enable register */ +#define Iir (0x02*Scale) /* interrupt identification register */ +#define Lcr (0x03*Scale) /* line control register */ +#define Mcr (0x04*Scale) /* modem control register */ +#define Lsr (0x05*Scale) /* line status register */ +#define Msr (0x06*Scale) /* modem status register */ + +/* Bit Definitions for above ports */ +#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ +#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ + +#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ +#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ +#define McrDflt (McrRts|McrDtr) + +#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ + /* b6: transmitter empty */ +#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ + +#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ +#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ +#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ + +#define IerRda 0xf /* b0: Enable received data available interrupt */ + +#endif + +#endif /* __SERIAL_H__ */ diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds new file mode 100644 index 0000000..d89eb6c --- /dev/null +++ b/board/evb64260/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c new file mode 100644 index 0000000..d64025a --- /dev/null +++ b/board/evb64260/zuma_pbb.c @@ -0,0 +1,220 @@ +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +#include +#endif + +#include +#include +#include "zuma_pbb.h" + +#undef DEBUG + +#define PAT_LO 0x00010203 +#define PAT_HI 0x04050607 + +static PBB_DMA_REG_MAP *zuma_pbb_reg = NULL; +static char test_buf1[2048]; +static char test_buf2[2048]; +void zuma_init_pbb(void); +int zuma_mbox_init(void); +int zuma_test_dma(int cmd, int size); + +int zuma_test_dma (int cmd, int size) +{ + static const char *const test_legend[] = { + "write", "verify", + "copy", "compare", + "write inc", "verify inc" + }; + register int i, j; + unsigned int p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff); + unsigned int p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff); + volatile unsigned int *ps = (unsigned int *) p1; + volatile unsigned int *pd = (unsigned int *) p2; + unsigned int funct, pat_lo = PAT_LO, pat_hi = PAT_HI; + DMA_INT_STATUS stat; + int ret = 0; + + if (!zuma_pbb_reg) { + printf ("not initted\n"); + return -1; + } + + if (cmd < 0 || cmd > 5) { + printf ("inv cmd %d\n", cmd); + return -1; + } + + if (cmd == 2 || cmd == 3) { + /* not implemented */ + return 0; + } + + if (size <= 0 || size > 1024) + size = 1024; + + size &= (~7); /* throw away bottom 3 bits */ + + p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff); + p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff); + + memset ((void *) p1, 0, size); + memset ((void *) p2, 0, size); + + for (i = 0; i < size / 4; i += 2) { + ps[i] = pat_lo; + ps[i + 1] = pat_hi; + if (cmd == 4 || cmd == 5) { + unsigned char *pl = (unsigned char *) &pat_lo; + unsigned char *ph = (unsigned char *) &pat_hi; + + for (j = 0; j < 4; j++) { + pl[j] += 8; + ph[j] += 8; + } + } + } + + funct = (1 << 31) | (cmd << 24) | (size); + + zuma_pbb_reg->int_mask.pci_bits.chan0 = + EOF_RX_FLAG | EOF_TX_FLAG | EOB_TX_FLAG; + + zuma_pbb_reg->debug_57 = PAT_LO; /* patl */ + zuma_pbb_reg->debug_58 = PAT_HI; /* path */ + + zuma_pbb_reg->debug_54 = cpu_to_le32 (p1); /* src 0x01b0 */ + zuma_pbb_reg->debug_55 = cpu_to_le32 (p2); /* dst 0x01b8 */ + zuma_pbb_reg->debug_56 = cpu_to_le32 (funct); /* func, 0x01c0 */ + + /* give DMA time to chew on things.. dont use DRAM or PCI */ + /* if you can avoid it. */ + do { + for (i = 0; i < 1000 * 10; i++); + } while (le32_to_cpu (zuma_pbb_reg->debug_56) & (1 << 31)); + + stat.word = zuma_pbb_reg->status.word; + zuma_pbb_reg->int_mask.word = 0; + + printf ("stat: %08x (%x)\n", stat.word, stat.pci_bits.chan0); + + printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56)); + printf ("src @%08x: %08x %08x %08x %08x\n", p1, ps[0], ps[1], ps[2], + ps[3]); + printf ("dst @%08x: %08x %08x %08x %08x\n", p2, pd[0], pd[1], pd[2], + pd[3]); + printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56)); + + + if (cmd == 0 || cmd == 4) { + /* this is a write */ + if (!(stat.pci_bits.chan0 & EOF_RX_FLAG) || /* not done */ + (memcmp ((void *) ps, (void *) pd, size) != 0)) { /* cmp error */ + for (i = 0; i < size / 4; i += 2) { + if ((ps[i] != pd[i]) || (ps[i + 1] != pd[i + 1])) { + printf ("s @%p:%08x %08x\n", &ps[i], ps[i], ps[i + 1]); + printf ("d @%p:%08x %08x\n", &pd[i], pd[i], pd[i + 1]); + } + } + ret = -1; + } + } else { + /* this is a verify */ + if (!(stat.pci_bits.chan0 & EOF_TX_FLAG) || /* not done */ + (stat.pci_bits.chan0 & EOB_TX_FLAG)) { /* cmp error */ + printf ("%08x: %08x %08x\n", + le32_to_cpu (zuma_pbb_reg->debug_63), + zuma_pbb_reg->debug_61, zuma_pbb_reg->debug_62); + ret = -1; + } + } + + printf ("%s cmd %d, %d bytes: %s!\n", test_legend[cmd], cmd, size, + (ret == 0) ? "PASSED" : "FAILED"); + return 0; +} + +void zuma_init_pbb (void) +{ + unsigned int iobase; + pci_dev_t dev = + pci_find_device (VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); + + if (dev == -1) { + printf ("no zuma pbb\n"); + return; + } + + pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase); + + zuma_pbb_reg = + (PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK); + + if (!zuma_pbb_reg) { + printf ("zuma pbb bar none! (hah hah, get it?)\n"); + return; + } + + zuma_pbb_reg->int_mask.word = 0; + + printf ("pbb @ %p v%d.%d, timestamp %08x\n", zuma_pbb_reg, + zuma_pbb_reg->version.pci_bits.rev_major, + zuma_pbb_reg->version.pci_bits.rev_minor, + zuma_pbb_reg->timestamp); + +} + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +static int last_cmd = 4; /* write increment */ +static int last_size = 64; + +int +do_zuma_init_pbb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + zuma_init_pbb (); + return 0; +} + +int +do_zuma_test_dma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc > 1) { + last_cmd = simple_strtoul (argv[1], NULL, 10); + } + if (argc > 2) { + last_size = simple_strtoul (argv[2], NULL, 10); + } + zuma_test_dma (last_cmd, last_size); + return 0; +} + +int +do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + zuma_mbox_init (); + return 0; +} + +U_BOOT_CMD( + zinit, 1, 0, do_zuma_init_pbb, + "zinit - init zuma pbb\n", + "\n" + " - init zuma pbb\n" +); +U_BOOT_CMD( + zdtest, 3, 1, do_zuma_test_dma, + "zdtest - run dma test\n", + "[cmd [count]]\n" + " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n" +); +U_BOOT_CMD( + zminit, 1, 0, do_zuma_init_mbox, + "zminit - init zuma mbox\n", + "\n" + " - init zuma mbox\n" +); + +#endif /* CFG_CMD_BSP */ diff --git a/board/evb64260/zuma_pbb.h b/board/evb64260/zuma_pbb.h new file mode 100644 index 0000000..300b2fe --- /dev/null +++ b/board/evb64260/zuma_pbb.h @@ -0,0 +1,346 @@ +#ifndef ZUMA_PBB_H +#define ZUMA_PBB_H + +#define MAX_NUM_BUFFER_PER_RING 32 + +#ifdef __BIG_ENDIAN +#define cpu_bits _be_s_bits /* use with le32_to_cpu only */ +#define pci_bits _be_bits /* may contain swapped bytes, + but dont need le32_to_cpu */ +#endif + +#ifdef __LITTLE_ENDIAN +#define cpu_bits _le_bits +#define pci_bits _le_bits +#endif + +#define VENDOR_ID_ZUMA 0x1172 +#define DEVICE_ID_ZUMA_PBB 0x0004 + +#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch*8 */ +#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch*8 + 4 */ +#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch*8 + 64 */ +#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch*8 + 68 */ + +#define PBB_DMA_OWN_BIT 0x80000000 +#define PBB_DMA_LAST_BIT 0x40000000 + +#define EOF_RX_FLAG 1 /* bit 0 */ +#define EOB_RX_FLAG 2 /* bit 1 */ +#define EOF_TX_FLAG 4 /* bit 2 */ +#define EOB_TX_FLAG 8 /* bit 3 */ + +#define TX_MODE(m) (((m)&7) << 16) + +#define RX_DESC(i) (cs->rx_desc[i]) +#define TX_DESC(i) (cs->tx_desc[i]) + +#define RX_CONTROL(i) (RX_DESC(i).control.word) +#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size) +#define TX_CONTROL(i) (TX_DESC(i).control.word) + +#define RX_DATA_P(i) (&RX_DESC(i).ptr) +#define TX_DATA_P(i) (&TX_DESC(i).ptr) + +typedef volatile unsigned char V8; +typedef volatile unsigned short V16; +typedef volatile unsigned int V32; + +/* RAM descriptor layout */ +typedef struct _tag_dma_descriptor { + V32 ptr; + union { + struct { + V32 owner:1; + V32 last:1; + V32 reserved0: 10; + V32 tx_mode: 4; + + V32 reserved1: 5; + V32 size: 11; + } tx; + struct { + V32 owner:1; + V32 last:1; + V32 reserved0: 14; + + V32 reserved1: 5; + V32 size: 11; + } rx; + V32 word; + } control; +} DMA_DESCRIPTOR; + +/* + * NOTE: DO NOT USE structure to write non-word values... all registers + * MUST be written 4 bytes at a time in SI version 0. + * Non-word writes will result in "unaccessed" bytes written as zero. + * + * Byte reads are allowed. + * + * V32 pads are because the registers are spaced every 8 bytes (64 bits) + * + */ + +/* NOTE!!! 4 dwords */ +typedef struct _tag_dma_descriptor_ring { + DMA_DESCRIPTOR *base; + V32 pad1; /* skip high dword */ + volatile DMA_DESCRIPTOR *current; + V32 pad3; /* skip high dword */ +} DMA_DESCRIPTOR_RING; + +/* 1 dword */ +typedef union _tag_dma_generic { + struct { /* byte 3 2 1 0 */ + V32 chan7:4; /* bits 31-28 */ + V32 chan6:4; /* bits 27-24 */ + V32 chan5:4; /* bits 23-20 */ + V32 chan4:4; /* bits 19-16 */ + V32 chan3:4; /* bits 15-12 */ + V32 chan2:4; /* bits 11-8 */ + V32 chan1:4; /* bits 7-4 */ + V32 chan0:4; /* bits 3-0 */ + } _be_s_bits; + struct { /* byte 0 1 2 3 */ + V32 chan1:4; /* bits 7-4 */ + V32 chan0:4; /* bits 3-0 */ + V32 chan3:4; /* bits 15-12 */ + V32 chan2:4; /* bits 11-8 */ + V32 chan5:4; /* bits 23-20 */ + V32 chan4:4; /* bits 19-16 */ + V32 chan7:4; /* bits 31-28 */ + V32 chan6:4; /* bits 27-24 */ + } _be_bits; + struct { /* byte 0 1 2 3 */ + V32 chan0:4; /* bits 0-3 */ + V32 chan1:4; /* bits 4-7 */ + V32 chan2:4; /* bits 8-11 */ + V32 chan3:4; /* bits 12-15 */ + V32 chan4:4; /* bits 16-19 */ + V32 chan5:4; /* bits 20-23 */ + V32 chan6:4; /* bits 24-27 */ + V32 chan7:4; /* bits 28-31 */ + } _le_bits; + V8 byte[4]; + V32 word; +} DMA_RXTX_ENABLE, DMA_RX_DELETE, + DMA_INT_STATUS, DMA_INT_MASK, + DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK; + +/* 1 dword */ +typedef union _tag_dma_rx_timer{ + struct { + V32 res0:8; /* bits 32-24 */ + V32 res1:7; /* bits 23-17 */ + V32 enable:1; /* bit 16 */ + V32 value:16; /* bits 15-0 */ + } _be_s_bits; + struct { + /* crosses byte boundary. must use swap. */ + V32 s_value:16; /* bits 7-0,15-8 */ + V32 enable:1; /* bit 16 */ + V32 res1:7; /* bits 23-17 */ + V32 res0:8; /* bits 32-24 */ + } _be_bits; + struct { + V32 value:16; /* bits 0-15 */ + V32 enable:1; /* bit 16 */ + V32 res1:7; /* bits 17-23 */ + V32 res0:8; /* bits 24-32 */ + } _le_bits; + V8 byte[4]; + V32 word; +} DMA_RX_TIMER; + +/* NOTE!!!: 2 dwords */ +typedef struct _tag_dma_desc_level{ + union { + struct { + V32 res1:8; /* bits 31-24 */ + V32 res0:7; /* bits 23-17 */ + V32 write:1; /* bit 16 */ + V32 thresh:8; /* bits 15-8 */ + V32 level:8; /* bits 7-0 */ + } _be_s_bits; + struct { + V32 level:8; /* bits 7-0 */ + V32 thresh:8; /* bits 15-8 */ + V32 res0:7; /* bits 30-17 */ + V32 write:1; /* bit 16 */ + V32 res1:8; /* bits 31-24 */ + } _be_bits; + struct { + V32 level:8; /* bits 0-7 */ + V32 thresh:8; /* bits 8-15 */ + V32 write:1; /* bit 16 */ + V32 res0:7; /* bit 17-30 */ + V32 res1:8; /* bits 24-31 */ + } _le_bits; + V8 byte[4]; + V32 word; + } desc; + V32 pad1; +} DMA_DESC_LEVEL; + +typedef struct _tag_pbb_dma_reg_map { + /* 0-15 (0x000-0x078) */ + DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */ + + /* 16-31 (0x080-0x0f8) */ + DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */ + + /* 32/33 (0x100/0x108) */ + V32 reserved_32; + V32 pad_32; + V32 reserved_33; + V32 pad_33; + + /* 34 (0x110) */ + DMA_RXTX_ENABLE rxtx_enable; + V32 pad_34; + + /* 35 (0x118) */ + DMA_RX_DELETE rx_delete; + V32 pad_35; + + /* 36-38 (0x120-0x130) */ + DMA_INT_STATUS status; + V32 pad_36; + DMA_INT_STATUS last_status; + V32 pad_37; + DMA_INT_MASK int_mask; + V32 pad_38; + + /* 39/40 (0x138/0x140) */ + union { + /* NOTE!! 4 dwords */ + struct { + V32 channel_3:8; + V32 channel_2:8; + V32 channel_1:8; + V32 channel_0:8; + V32 pad1; + V32 channel_7:8; + V32 channel_6:8; + V32 channel_5:8; + V32 channel_4:8; + V32 pad3; + } _be_s_bits; + struct { + V32 channel_0:8; + V32 channel_1:8; + V32 channel_2:8; + V32 channel_3:8; + V32 pad1; + V32 channel_4:8; + V32 channel_5:8; + V32 channel_6:8; + V32 channel_7:8; + V32 pad3; + } _be_bits, _le_bits; + V8 byte[16]; + V32 word[4]; + } rx_size; + + /* 41/42 (0x148/0x150) */ + V32 reserved_41; + V32 pad_41; + V32 reserved_42; + V32 pad_42; + + /* 43/44 (0x158/0x160) */ + DMA_RX_LEVEL_STATUS rx_level_status; + V32 pad_43; + DMA_RX_LEVEL_INT_MASK rx_level_int_mask; + V32 pad_44; + + /* 45 (0x168) */ + DMA_RX_TIMER rx_timer; + V32 pad_45; + + /* 46 (0x170) */ + V32 reserved_46; + V32 pad_46; + + /* 47 (0x178) */ + V32 mbox_status; + V32 pad_47; + + /* 48/49 (0x180/0x188) */ + V32 mbox_out; + V32 pad_48; + V32 mbox_in; + V32 pad_49; + + /* 50 (0x190) */ + V32 config; + V32 pad_50; + + /* 51/52 (0x198/0x1a0) */ + V32 c2a_ctr; + V32 pad_51; + V32 a2c_ctr; + V32 pad_52; + + /* 53 (0x1a8) */ + union { + struct { + V32 rev_major:8; /* bits 31-24 */ + V32 rev_minor:8; /* bits 23-16 */ + V32 reserved:16; /* bits 15-0 */ + } _be_s_bits; + struct { + V32 s_reserved:16; /* bits 7-0, 15-8 */ + V32 rev_minor:8; /* bits 23-16 */ + V32 rev_major:8; /* bits 31-24 */ + } _be_bits; + struct { + V32 reserved:16; /* bits 0-15 */ + V32 rev_minor:8; /* bits 16-23 */ + V32 rev_major:8; /* bits 24-31 */ + } _le_bits; + V8 byte[4]; + V32 word; + } version; + V32 pad_53; + + /* 54-59 (0x1b0-0x1d8) */ + V32 debug_54; + V32 pad_54; + V32 debug_55; + V32 pad_55; + V32 debug_56; + V32 pad_56; + V32 debug_57; + V32 pad_57; + V32 debug_58; + V32 pad_58; + V32 debug_59; + V32 pad_59; + + /* 60 (0x1e0) */ + V32 timestamp; + V32 pad_60; + + /* 61-63 (0x1e8-0x1f8) */ + V32 debug_61; + V32 pad_61; + V32 debug_62; + V32 pad_62; + V32 debug_63; + V32 pad_63; + + /* 64-71 (0x200 - 0x238) */ + DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */ + + /* 72-98 (0x240 - 0x2f8) */ + /* reserved */ + + /* 96-127 (0x300 - 0x3f8) */ + /* mirrors (0x100 - 0x1f8) */ + +} PBB_DMA_REG_MAP; + + +#endif /* ZUMA_PBB_H */ diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c new file mode 100644 index 0000000..2b9a469 --- /dev/null +++ b/board/evb64260/zuma_pbb_mbox.c @@ -0,0 +1,187 @@ +#include +#include +#include +#include + +#include "zuma_pbb.h" +#include "zuma_pbb_mbox.h" + + +struct _zuma_mbox_dev zuma_mbox_dev; + + +static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data) +{ + unsigned int status, count = 0, i; + + status = (volatile int)le32_to_cpu(dev->sip->mbox_status); + + while((status & OUT_PENDING) && count < 1000) { + count++; + for(i=0;i<1000;i++); + status = (volatile int)le32_to_cpu(dev->sip->mbox_status); + } + if(count < 1000) { + /* if SET it means msg pending */ + /* printf("mbox real write %08x\n",data); */ + dev->sip->mbox_out = cpu_to_le32(data); + return 4; + } + + printf("mbox tx timeout\n"); + return 0; +} + +static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data) +{ + unsigned int status, count = 0, i; + + status = (volatile int)le32_to_cpu(dev->sip->mbox_status); + + while(!(status & IN_VALID) && count < 1000) { + count++; + for(i=0;i<1000;i++); + status = (volatile int)le32_to_cpu(dev->sip->mbox_status); + } + if(count < 1000) { + /* if SET it means msg pending */ + *data=le32_to_cpu(dev->sip->mbox_in); + /*printf("mbox real read %08x\n", *data); */ + return 4; + } + printf("mbox rx timeout\n"); + return 0; +} + +static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in) +{ + int ret; + ret=zuma_mbox_write(&zuma_mbox_dev,out); + /*printf("write 0x%08x (%d bytes)\n", out, ret); */ + if(ret!=4) return -1; + ret=zuma_mbox_read(&zuma_mbox_dev,in); + /*printf("read 0x%08x (%d bytes)\n", *in, ret); */ + if(ret!=4) return -1; + return 0; +} + + +#define RET_IF_FAILED(x) if ((x) == -1) return -1 + +static int zuma_mbox_do_all_mailbox(void) +{ + unsigned int data_in; + unsigned short sdata_in; + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in)); + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in)); + memcpy(zuma_acc_mac+2,&data_in,4); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in)); + sdata_in=data_in&0xffff; + memcpy(zuma_acc_mac,&sdata_in,2); + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in)); + zuma_ip=data_in; + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in)); + zuma_slot_bac=data_in>>3; + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in)); + zuma_console_baud = data_in & 0xffff; + zuma_debug_baud = data_in >> 16; + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in)); + memcpy(zuma_prv_mac+2,&data_in,4); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in)); + sdata_in=data_in&0xffff; + memcpy(zuma_prv_mac,&sdata_in,2); + + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in)); + + return 0; +} + + +static void +zuma_mbox_dump(void) +{ + printf("ACC MAC=%04x%08x\n",*(unsigned short *)(&zuma_acc_mac),*(unsigned int *)((char *)&zuma_acc_mac+2)); + printf("PRV MAC=%04x%08x\n",*(unsigned short *)(&zuma_prv_mac),*(unsigned int *)((char *)&zuma_prv_mac+2)); + printf("slot:bac=%d:%d\n",(zuma_slot_bac>>2)&0xf, zuma_slot_bac & 0x3); + printf("BAUD1=%d BAUD2=%d\n",zuma_console_baud,zuma_debug_baud); +} + + +static void +zuma_mbox_setenv(void) +{ + char *data, buf[32]; + unsigned char save = 0; + + data = getenv("baudrate"); + + if(!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) { + sprintf(buf, "%6d", zuma_console_baud); + setenv("baudrate", buf); + save=1; + printf("baudrate doesn't match from mbox\n"); + } + + ip_to_string(zuma_ip, buf); + setenv("ipaddr", buf); + + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x", + zuma_prv_mac[0], + zuma_prv_mac[1], + zuma_prv_mac[2], + zuma_prv_mac[3], + zuma_prv_mac[4], + zuma_prv_mac[5]); + setenv("ethaddr", buf); + + sprintf(buf,"%02x",zuma_slot_bac); + setenv("bacslot", buf); + + if(save) + saveenv(); +} + +/** + * zuma_mbox_init: + */ + +int zuma_mbox_init(void) +{ + unsigned int iobase; + memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev)); + + zuma_mbox_dev.dev = pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); + + if(zuma_mbox_dev.dev == -1) { + printf("no zuma pbb\n"); + return -1; + } + + pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase); + + zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK); + + zuma_mbox_dev.sip->int_mask.word=0; + + printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip, + zuma_mbox_dev.sip->version.pci_bits.rev_major, + zuma_mbox_dev.sip->version.pci_bits.rev_minor, + zuma_mbox_dev.sip->timestamp); + + if (zuma_mbox_do_all_mailbox() == -1) { + printf("mailbox failed.. no ACC?\n"); + return -1; + } + + zuma_mbox_dump(); + + zuma_mbox_setenv(); + + return 0; +} diff --git a/board/evb64260/zuma_pbb_mbox.h b/board/evb64260/zuma_pbb_mbox.h new file mode 100644 index 0000000..b4a4c0c --- /dev/null +++ b/board/evb64260/zuma_pbb_mbox.h @@ -0,0 +1,43 @@ +#define IN_VALID 1 +#define OUT_PENDING 2 + +enum { + ZUMA_MBOXMSG_DONE, + ZUMA_MBOXMSG_MACL, + ZUMA_MBOXMSG_MACH, + ZUMA_MBOXMSG_IP, + ZUMA_MBOXMSG_SLOT, + ZUMA_MBOXMSG_RESET, + ZUMA_MBOXMSG_BAUD, + ZUMA_MBOXMSG_START, + ZUMA_MBOXMSG_ENG_PRV_MACL, + ZUMA_MBOXMSG_ENG_PRV_MACH, + + MBOXMSG_LAST +}; + +struct zuma_mailbox_info { + unsigned char acc_mac[6]; + unsigned char prv_mac[6]; + unsigned int ip; + unsigned int slot_bac; + unsigned int console_baud; + unsigned int debug_baud; +}; + +struct _zuma_mbox_dev { + pci_dev_t dev; + PBB_DMA_REG_MAP *sip; + struct zuma_mailbox_info mailbox; +}; + +#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac +#define zuma_acc_mac zuma_mbox_dev.mailbox.acc_mac +#define zuma_ip zuma_mbox_dev.mailbox.ip +#define zuma_slot_bac zuma_mbox_dev.mailbox.slot_bac +#define zuma_console_baud zuma_mbox_dev.mailbox.console_baud +#define zuma_debug_baud zuma_mbox_dev.mailbox.debug_baud + + +extern struct _zuma_mbox_dev zuma_mbox_dev; +extern int zuma_mbox_init (void); diff --git a/board/exbitgen/Makefile b/board/exbitgen/Makefile new file mode 100644 index 0000000..34bd4b2 --- /dev/null +++ b/board/exbitgen/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +SOBJS = init.o + + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/exbitgen/config.mk b/board/exbitgen/config.mk new file mode 100644 index 0000000..42ea0c6 --- /dev/null +++ b/board/exbitgen/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# ExbitGen board +# + +LDFLAGS += $(LINKER_UNDEFS) + +TEXT_BASE := 0xFFF80000 +#TEXT_BASE := 0x00100000 + +PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS) diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c new file mode 100644 index 0000000..39a9722 --- /dev/null +++ b/board/exbitgen/exbitgen.c @@ -0,0 +1,117 @@ +#include +#include +#include +#include "exbitgen.h" + +/* ************************************************************************ */ +int board_early_init_f (void) +/* ------------------------------------------------------------------------ -- + * Purpose : + * Remarks : + * Restrictions: + * See also : + * Example : + * ************************************************************************ */ +{ + unsigned long i; + + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the Walnut board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive + | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive + | IRQ 27 (EXT IRQ 2) Not Used + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive + | Note for Walnut board: + | An interrupt taken for the FPGA (IRQ 25) indicates that either + | the Mouse, Keyboard, IRDA, or External Expansion caused the + | interrupt. The FPGA must be read to determine which device + | caused the interrupt. The default setting of the FPGA clears + | + +-------------------------------------------------------------------------*/ + + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* Perform reset of PHY connected to PPC via register in CPLD */ + out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */ + for (i = 0; i < 10000000; i++) { + ; + } + out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */ + + return 0; +} + + +/* ************************************************************************ */ +int checkboard (void) +/* ------------------------------------------------------------------------ -- + * Purpose : + * Remarks : + * Restrictions: + * See also : + * Example : + * ************************************************************************ */ +{ + printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR)); + return (0); +} + +/* ************************************************************************ */ +long int initdram (int board_type) +/* ------------------------------------------------------------------------ -- + * Purpose : Determines size of mounted DRAM. + * Remarks : Size is determined by reading SDRAM configuration registers as + * set up by sdram_init. + * Restrictions: + * See also : + * Example : + * ************************************************************************ */ +{ + ulong tot_size; + ulong bank_size; + ulong tmp; + + tot_size = 0; + + mtdcr (memcfga, mem_mb0cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + mtdcr (memcfga, mem_mb1cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + mtdcr (memcfga, mem_mb2cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + mtdcr (memcfga, mem_mb3cf); + tmp = mfdcr (memcfgd); + if (tmp & 0x00000001) { + bank_size = 0x00400000 << ((tmp >> 17) & 0x7); + tot_size += bank_size; + } + + return tot_size; +} diff --git a/board/exbitgen/exbitgen.h b/board/exbitgen/exbitgen.h new file mode 100644 index 0000000..058ad48 --- /dev/null +++ b/board/exbitgen/exbitgen.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define GPIO_CPU_LED GPIO_3 + + +#define CPLD_BASE 0x10000000 /* t.b.m. */ +#define DEBUG_LEDS_ADDR CPLD_BASE + 0x01 +#define HW_ID_ADDR CPLD_BASE + 0x02 +#define DIP_SWITCH_ADDR CPLD_BASE + 0x04 +#define PHY_CTRL_ADDR CPLD_BASE + 0x05 +#define SPI_OUT_ADDR CPLD_BASE + 0x07 +#define SPI_IN_ADDR CPLD_BASE + 0x08 +#define MDIO_OUT_ADDR CPLD_BASE + 0x09 +#define MDIO_IN_ADDR CPLD_BASE + 0x0A +#define MISC_OUT_ADDR CPLD_BASE + 0x0B + +/* Addresses used on I2C bus */ +#define LM75_CHIP_ADDR 0x9C +#define LM75_CPU_ADDR 0x9E +#define SDRAM_SPD_ADDR 0xA0 + +#define SDRAM_SPD_WRITE_ADDRESS (SDRAM_SPD_ADDR) +#define SDRAM_SPD_READ_ADDRESS (SDRAM_SPD_ADDR+1) + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c new file mode 100644 index 0000000..ae88994 --- /dev/null +++ b/board/exbitgen/flash.c @@ -0,0 +1,597 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +#ifdef MEIGSBOARD_ONBOARD_FLASH /* onboard = 2MB */ +# ifdef CONFIG_EXBITGEN +# define FLASH_WORD_SIZE unsigned long +# endif +#else /* Meigsboard socket flash = 512KB */ +# ifdef CONFIG_EXBITGEN +# define FLASH_WORD_SIZE unsigned char +# endif +#endif + +#ifdef CONFIG_EXBITGEN +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char +#endif + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long bank_size; + unsigned long tot_size; + unsigned long bank_addr; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = 0; + } + + tot_size = 0; + + /* Detect Boot Flash */ + bank_addr = CFG_FLASH0_BASE; + bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[0]); + if (bank_size > 0) { + (void)flash_protect(FLAG_PROTECT_CLEAR, + bank_addr, + bank_addr + bank_size - 1, + &flash_info[0]); + } + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Boot Flash Bank\n"); + } + flash_info[0].size = bank_size; + tot_size += bank_size; + + /* Detect Application Flash */ + bank_addr = CFG_FLASH1_BASE; + for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) { + bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[i]); + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + break; + } + if (bank_size > 0) { + (void)flash_protect(FLAG_PROTECT_CLEAR, + bank_addr, + bank_addr + bank_size - 1, + &flash_info[i]); + } + flash_info[i].size = bank_size; + tot_size += bank_size; + bank_addr += bank_size; + } + if (flash_info[1].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Application Flash Bank\n"); + } + + /* Protect monitor and environment sectors */ +#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#if 0xfffffffc >= CFG_FLASH0_BASE +#if 0xfffffffc <= CFG_FLASH0_BASE + CFG_FLASH0_SIZE - 1 + flash_protect(FLAG_PROTECT_SET, + 0xfffffffc, 0xffffffff, + &flash_info[0]); +#endif +#endif +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return tot_size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AMDLV033C: printf ("AM29LV033C (32 Mbit, uniform sector size)\n"); + break; + case FLASH_AMDLV065D: printf ("AM29LV065D (64 Mbit, uniform sector size)\n"); + break; + case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; + + value = addr2[0]; + + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE)FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE)SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE)AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV033C: + info->flash_id += FLASH_AMDLV033C; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV065D: + info->flash_id += FLASH_AMDLV065D; + info->sector_count = 128; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (FLASH_WORD_SIZE)SST_ID_xF800A: + info->flash_id += FLASH_SST800A; + info->sector_count = 16; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE)SST_ID_xF160A: + info->flash_id += FLASH_SST160A; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + case (FLASH_WORD_SIZE)SST_ID_xF040: + info->flash_id += FLASH_SST040; + info->sector_count = 128; + info->size = 0x00080000; + break; /* => 512KB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040) || + (info->flash_id == FLASH_AMDLV033C) || + (info->flash_id == FLASH_AMDLV065D)) { + ulong sectsize = info->size / info->sector_count; + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * sectsize); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* switch to the read mode */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while ((addr2[0] & 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now=get_timer(start)) > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; + } + } + + printf (" done\n"); + + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile ulong *)dest) & data) != data) { + printf("dest = %08lx, *dest = %08lx, data = %08lx\n", + dest, *(volatile ulong *)dest, data); + return 2; + } + + for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & 0x00800080) != (data2[i] & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + addr2[0] = (FLASH_WORD_SIZE)0x00F000F0; + return (1); + } + } + } + + addr2[0] = (FLASH_WORD_SIZE)0x00F000F0; + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S new file mode 100644 index 0000000..0e6cd04 --- /dev/null +++ b/board/exbitgen/init.S @@ -0,0 +1,1009 @@ +/*----------------------------------------------------------------------+ + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *----------------------------------------------------------------------- + */ + +#include +#include +#include "config.h" + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ +#define FPGA_BRDC 0xF0300004 + +#include +#include + +#include +#include + +#include "exbitgen.h" + +/* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */ +/* c-code declarations and consequently can't be included here). */ +/* (Possibly to be solved somehow else). */ +/*--------------------------------------------------------------------- */ +#define I2C_REGISTERS_BASE_ADDRESS 0xEF600500 +#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) +#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) +#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) +#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) +#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) +#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) +#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) +#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) +#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) +#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) +#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) +#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) +#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) +#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) +#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) + +/* MDCNTL Register Bit definition */ +#define IIC_MDCNTL_HSCL 0x01 +#define IIC_MDCNTL_EUBS 0x02 +#define IIC_MDCNTL_FMDB 0x40 +#define IIC_MDCNTL_FSDB 0x80 + +/* CNTL Register Bit definition */ +#define IIC_CNTL_PT 0x01 +#define IIC_CNTL_READ 0x02 +#define IIC_CNTL_CHT 0x04 + +/* STS Register Bit definition */ +#define IIC_STS_PT 0X01 +#define IIC_STS_ERR 0X04 +#define IIC_STS_MDBS 0X20 + +/* EXTSTS Register Bit definition */ +#define IIC_EXTSTS_XFRA 0X01 +#define IIC_EXTSTS_ICT 0X02 +#define IIC_EXTSTS_LA 0X04 + +/* LED codes used for inditing progress and errors during read of DIMM SPD. */ +/*--------------------------------------------------------------------- */ +#define LED_SDRAM_CODE_1 0xef +#define LED_SDRAM_CODE_2 0xee +#define LED_SDRAM_CODE_3 0xed +#define LED_SDRAM_CODE_4 0xec +#define LED_SDRAM_CODE_5 0xeb +#define LED_SDRAM_CODE_6 0xea +#define LED_SDRAM_CODE_7 0xe9 +#define LED_SDRAM_CODE_8 0xe8 +#define LED_SDRAM_CODE_9 0xe7 +#define LED_SDRAM_CODE_10 0xe6 +#define LED_SDRAM_CODE_11 0xe5 +#define LED_SDRAM_CODE_12 0xe4 +#define LED_SDRAM_CODE_13 0xe3 +#define LED_SDRAM_CODE_14 0xe2 +#define LED_SDRAM_CODE_15 0xe1 +#define LED_SDRAM_CODE_16 0xe0 + + +#define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100 + +#define FLASH_8bit_AP 0x9B015480 +#define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */ + +#define FLASH_32bit_AP 0x9B015480 +#define FLASH_32bit_CR 0xFFE3C000 /* 2MB, 32bit, R/W */ + + +#define WDCR_EBC(reg,val) addi r4,0,reg;\ + mtdcr ebccfga,r4;\ + addis r4,0,val@h;\ + ori r4,r4,val@l;\ + mtdcr ebccfgd,r4 + +/*--------------------------------------------------------------------- + * Function: ext_bus_cntlr_init + * Description: Initializes the External Bus Controller for the external + * peripherals. IMPORTANT: For pass1 this code must run from + * cache since you can not reliably change a peripheral banks + * timing register (pbxap) while running code from that bank. + * For ex., since we are running from ROM on bank 0, we can NOT + * execute the code that modifies bank 0 timings from ROM, so + * we run it from cache. + * Bank 0 - Boot flash + * Bank 1-4 - application flash + * Bank 5 - CPLD + * Bank 6 - not used + * Bank 7 - Heathrow chip + *--------------------------------------------------------------------- + */ + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + mflr r4 /* save link register */ + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 10; used to prefetch */ + mtctr r4 /* 10 cache lines to fit this function */ + /* in cache (gives us 8x10=80 instrctns) */ +..ebcloop: + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 10 cache lines */ + + mflr r31 /* save link register */ + + /*----------------------------------------------------------- + * Delay to ensure all accesses to ROM are complete before changing + * bank 0 timings. 200usec should be enough. + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + *----------------------------------------------------------- + */ + + addis r3,0,0x0 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + /*--------------------------------------------------------------- + * Memory Bank 0 (Boot Flash) initialization + *--------------------------------------------------------------- + */ + WDCR_EBC(pb0ap, FLASH_32bit_AP) + WDCR_EBC(pb0cr, 0xffe38000) +/*pnc WDCR_EBC(pb0cr, FLASH_32bit_CR) */ + + /*--------------------------------------------------------------- + * Memory Bank 5 (CPLD) initialization + *--------------------------------------------------------------- + */ + WDCR_EBC(pb5ap, 0x01010040) +/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ + WDCR_EBC(pb5cr, 0x10038000) + + /*--------------------------------------------------------------- */ + /* Memory Bank 6 (not used) initialization */ + /*--------------------------------------------------------------- */ + WDCR_EBC(pb6cr, 0x00000000) + + /* Read HW ID to determine whether old H2 board or new generic CPU board */ + addis r3, 0, HW_ID_ADDR@h + ori r3, r3, HW_ID_ADDR@l + lbz r3,0x0000(r3) + cmpi 0, r3, 1 /* if (HW_ID==1) */ + beq setup_h2evalboard /* then jump */ + cmpi 0, r3, 2 /* if (HW_ID==2) */ + beq setup_genieboard /* then jump */ + cmpi 0, r3, 3 /* if (HW_ID==3) */ + beq setup_genieboard /* then jump */ + +setup_genieboard: + /*--------------------------------------------------------------- */ + /* Memory Bank 1 (Application Flash) initialization for generic CPU board */ + /*--------------------------------------------------------------- */ +/* WDCR_EBC(pb1ap, 0x7b015480) /###* T.B.M. */ +/* WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(pb1ap, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */ + +/* WDCR_EBC(pb1cr, 0x20098000) /###* 16 MB */ + WDCR_EBC(pb1cr, 0x200B8000) /* 32 MB */ + + /*--------------------------------------------------------------- */ + /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */ + /*--------------------------------------------------------------- */ + WDCR_EBC(pb4ap, 0x01010000) /* */ + WDCR_EBC(pb4cr, 0x1021c000) /* */ + + /*--------------------------------------------------------------- */ + /* Memory Bank 7 (Heathrow chip on Reference board) initialization */ + /*--------------------------------------------------------------- */ + WDCR_EBC(pb7ap, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */ + WDCR_EBC(pb7cr, 0X4001A000) + + bl setup_continue + + +setup_h2evalboard: + /*--------------------------------------------------------------- */ + /* Memory Bank 1 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ + WDCR_EBC(pb1ap, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(pb1cr, 0x20058000) + + /*--------------------------------------------------------------- */ + /* Memory Bank 2 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ + WDCR_EBC(pb2ap, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(pb2ap, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(pb2cr, 0x20458000) + + /*--------------------------------------------------------------- */ + /* Memory Bank 3 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ + WDCR_EBC(pb3ap, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(pb3ap, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(pb3cr, 0x20858000) + + /*--------------------------------------------------------------- */ + /* Memory Bank 4 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ + WDCR_EBC(pb4ap, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(pb4ap, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(pb4cr, 0x20C58000) + + /*--------------------------------------------------------------- */ + /* Memory Bank 7 (Heathrow chip) initialization */ + /*--------------------------------------------------------------- */ + WDCR_EBC(pb7ap, 0x02000280) /* No Ready, 4 wait states */ + WDCR_EBC(pb7cr, 0X4001A000) + +setup_continue: + + + mtlr r31 /* restore lr */ + nop /* pass2 DCR errata #8 */ + blr + +/*--------------------------------------------------------------------- */ +/* Function: sdram_init */ +/* Description: Configures SDRAM memory banks. */ +/*--------------------------------------------------------------------- */ + .globl sdram_init + +sdram_init: +#if CFG_MONITOR_BASE < CFG_FLASH_BASE + blr +#else + mflr r31 + + /* output SDRAM code on LEDs */ + addi r4, 0, LED_SDRAM_CODE_1 + addis r5, 0, 0x1000 + ori r5, r5, 0x0001 + stb r4,0(r5) + eieio + + /* Read contents of spd */ + /*--------------------- */ + bl read_spd + + /*----------------------------------------------------------- */ + /* */ + /* */ + /* Update SDRAM timing register */ + /* */ + /* */ + /*----------------------------------------------------------- */ + + /* Read PLL feedback divider and calculate clock period of local bus in */ + /* granularity of 10 ps. Save clock period in r30 */ + /*-------------------------------------------------------------- */ + mfdcr r4, pllmd + addi r9, 0, 25 + srw r4, r4, r9 + andi. r4, r4, 0x07 + addis r5, 0, TIMEBASE_10PS@h + ori r5, r5, TIMEBASE_10PS@l + divwu r30, r5, r4 + + /* Determine CASL */ + /*--------------- */ + bl find_casl /* Returns CASL in r3 */ + + /* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */ + /* (trp read from byte 27 in granularity of 1 ns) */ + /*------------------------------------------------ */ + mulli r16, r16, 100 + add r16, r16, r30 + addi r6, 0, 1 + subf r16, r6, r16 + divwu r16, r16, r30 + + /* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */ + /* (trcd read from byte 29 in granularity of 1 ns) */ + /*--------------------------------------------------- */ + mulli r17, r17, 100 + add r17, r17, r30 + addi r6, 0, 1 + subf r17, r6, r17 + divwu r17, r17, r30 + + /* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */ + /* (tras read from byte 30 in granularity of 1 ns) */ + /*--------------------------------------------------- */ + mulli r18, r18, 100 + add r18, r18, r30 + addi r6, 0, 1 + subf r18, r6, r18 + divwu r18, r18, r30 + + /* Calc trc_clocks = trp_clocks + tras_clocks */ + /*------------------------------------------- */ + add r18, r18, r16 + + /* CASL value */ + /*----------- */ + addi r9, 0, 23 + slw r4, r3, r9 + + /* PTA = trp_clocks - 1 */ + /*--------------------- */ + addi r6, 0, 1 + subf r5, r6, r16 + addi r9, 0, 18 + slw r5, r5, r9 + or r4, r4, r5 + + /* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */ + /*------------------------------------------------ */ + addi r5, r18, 0 + subf r5, r16, r5 + subf r5, r17, r5 + addi r6, 0, 1 + subf r5, r6, r5 + addi r9, 0, 16 + slw r5, r5, r9 + or r4, r4, r5 + + /* LDF = 1 */ + /*-------- */ + ori r4, r4, 0x4000 + + /* RFTA = trc_clocks - 4 */ + /*---------------------- */ + addi r6, 0, 4 + subf r5, r6, r18 + addi r9, 0, 2 + slw r5, r5, r9 + or r4, r4, r5 + + /* RCD = trcd_clocks - 1 */ + /*---------------------- */ + addi r6, 0, 1 + subf r5, r6, r17 + or r4, r4, r5 + + /*----------------------------------------------------------- */ + /* Set SDTR1 */ + /*----------------------------------------------------------- */ + addi r5,0,mem_sdtr1 + mtdcr memcfga,r5 + mtdcr memcfgd,r4 + + /*----------------------------------------------------------- */ + /* */ + /* */ + /* Update memory bank 0-3 configuration registers */ + /* */ + /* */ + /*----------------------------------------------------------- */ + + /* Build contents of configuration register for bank 0 into r6 */ + /*------------------------------------------------------------ */ + bl find_mode /* returns addressing mode in r3 */ + addi r29, r3, 0 /* save mode temporarily in r29 */ + bl find_size_code /* returns size code in r3 */ + addi r9, 0, 17 /* bit offset of size code in configuration register */ + slw r3, r3, r9 /* */ + addi r9, 0, 13 /* bit offset of addressing mode in configuration register */ + slw r29, r29, r9 /* */ + or r3, r29, r3 /* merge size code and addressing mode */ + ori r6, r3, CFG_SDRAM_BASE + 1 /* insert base address and enable bank */ + + /* Calculate banksize r15 = (density << 22) / 2 */ + /*--------------------------------------------- */ + addi r9, 0, 21 + slw r15, r15, r9 + + /* Set SDRAM bank 0 register and adjust r6 for next bank */ + /*------------------------------------------------------ */ + addi r7,0,mem_mb0cf + mtdcr memcfga,r7 + mtdcr memcfgd,r6 + + add r6, r6, r15 /* add bank size to base address for next bank */ + + /* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */ + /*---------------------------------------------------------------------------- */ + cmpi 0, r12, 2 + bne b1skip + + addi r7,0,mem_mb1cf + mtdcr memcfga,r7 + mtdcr memcfgd,r6 + + add r6, r6, r15 /* add bank size to base address for next bank */ + + /* Set SDRAM bank 2 register and adjust r6 for next bank */ + /*------------------------------------------------------ */ +b1skip: addi r7,0,mem_mb2cf + mtdcr memcfga,r7 + mtdcr memcfgd,r6 + + add r6, r6, r15 /* add bank size to base address for next bank */ + + /* If two rows/banks then set SDRAM bank 3 register */ + /*------------------------------------------------ */ + cmpi 0, r12, 2 + bne b3skip + + addi r7,0,mem_mb3cf + mtdcr memcfga,r7 + mtdcr memcfgd,r6 +b3skip: + + /*----------------------------------------------------------- */ + /* Set RTR */ + /*----------------------------------------------------------- */ + cmpi 0, r30, 1600 + bge rtr_1 + addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ + bl rtr_2 +rtr_1: addis r7, 0, 0x03F8 +rtr_2: addi r4,0,mem_rtr + mtdcr memcfga,r4 + mtdcr memcfgd,r7 + + /*----------------------------------------------------------- */ + /* Delay to ensure 200usec have elapsed since reset. Assume worst */ + /* case that the core is running 200Mhz: */ + /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ + /*----------------------------------------------------------- */ + addis r3,0,0x0000 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 +..spinlp2: + bdnz ..spinlp2 /* spin loop */ + + /*----------------------------------------------------------- */ + /* Set memory controller options reg, MCOPT1. */ + /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ + /* read/prefetch. */ + /*----------------------------------------------------------- */ + addi r4,0,mem_mcopt1 + mtdcr memcfga,r4 + addis r4,0,0x80C0 /* set DC_EN=1 */ + ori r4,r4,0x0000 + mtdcr memcfgd,r4 + + + /*----------------------------------------------------------- */ + /* Delay to ensure 10msec have elapsed since reset. This is */ + /* required for the MPC952 to stabalize. Assume worst */ + /* case that the core is running 200Mhz: */ + /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */ + /* This delay should occur before accessing SDRAM. */ + /*----------------------------------------------------------- */ + addis r3,0,0x001E + ori r3,r3,0x8480 /* ensure 10msec have passed since reset */ + mtctr r3 +..spinlp3: + bdnz ..spinlp3 /* spin loop */ + + /* output SDRAM code on LEDs */ + addi r4, 0, LED_SDRAM_CODE_16 + addis r5, 0, 0x1000 + ori r5, r5, 0x0001 + stb r4,0(r5) + eieio + + mtlr r31 /* restore lr */ + blr + +/*--------------------------------------------------------------------- */ +/* Function: read_spd */ +/* Description: Reads contents of SPD and saves parameters to be used for */ +/* configuration in dedicated registers (see code below). */ +/*--------------------------------------------------------------------- */ + +#define WRITE_I2C(reg,val) \ + addi r3,0,val;\ + addis r4, 0, 0xef60;\ + ori r4, r4, 0x0500 + reg;\ + stb r3, 0(r4);\ + eieio + +#define READ_I2C(reg) \ + addis r3, 0, 0xef60;\ + ori r3, r3, 0x0500 + reg;\ + lbz r3, 0x0000(r3);\ + eieio + +read_spd: + + mflr r5 + + /* Initialize i2c */ + /*--------------- */ + WRITE_I2C(IICLMADR, 0x00) /* clear lo master address */ + WRITE_I2C(IICHMADR, 0x00) /* clear hi master address */ + WRITE_I2C(IICLSADR, 0x00) /* clear lo slave address */ + WRITE_I2C(IICHSADR, 0x00) /* clear hi slave address */ + WRITE_I2C(IICSTS, 0x08) /* update status register */ + WRITE_I2C(IICEXTSTS, 0x8f) + WRITE_I2C(IICCLKDIV, 0x05) + WRITE_I2C(IICINTRMSK, 0x00) /* no interrupts */ + WRITE_I2C(IICXFRCNT, 0x00) /* clear transfer count */ + WRITE_I2C(IICXTCNTLSS, 0xf0) /* clear extended control & stat */ + WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB) /* mode control */ + READ_I2C(IICMDCNTL) + ori r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL + WRITE_I2C(IICMDCNTL, r3) /* mode control */ + WRITE_I2C(IICCNTL, 0x00) /* clear control reg */ + + /* Wait until initialization completed */ + /*------------------------------------ */ + bl wait_i2c_transfer_done + + WRITE_I2C(IICHMADR, 0x00) /* 7-bit addressing */ + WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS) + + /* Write 0 into buffer(start address) */ + /*----------------------------------- */ + WRITE_I2C(IICMDBUF, 0x00); + + /* Wait a little */ + /*-------------- */ + addis r3,0,0x0000 + ori r3,r3,0xA000 + mtctr r3 +in02: bdnz in02 + + /* Issue write command */ + /*-------------------- */ + WRITE_I2C(IICCNTL, IIC_CNTL_PT) + bl wait_i2c_transfer_done + + /* Read 128 bytes */ + /*--------------- */ + addi r7, 0, 0 /* byte counter in r7 */ + addi r8, 0, 0 /* checksum in r8 */ +rdlp: + /* issue read command */ + /*------------------- */ + cmpi 0, r7, 127 + blt rd01 + WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT) + bl rd02 +rd01: WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT) +rd02: bl wait_i2c_transfer_done + + /* Fetch byte from buffer */ + /*----------------------- */ + READ_I2C(IICMDBUF) + + /* Retrieve parameters that are going to be used during configuration. */ + /* Save them in dedicated registers. */ + /*------------------------------------------------------------ */ + cmpi 0, r7, 3 /* Save byte 3 in r10 */ + bne rd10 + addi r10, r3, 0 +rd10: cmpi 0, r7, 4 /* Save byte 4 in r11 */ + bne rd11 + addi r11, r3, 0 +rd11: cmpi 0, r7, 5 /* Save byte 5 in r12 */ + bne rd12 + addi r12, r3, 0 +rd12: cmpi 0, r7, 17 /* Save byte 17 in r13 */ + bne rd13 + addi r13, r3, 0 +rd13: cmpi 0, r7, 18 /* Save byte 18 in r14 */ + bne rd14 + addi r14, r3, 0 +rd14: cmpi 0, r7, 31 /* Save byte 31 in r15 */ + bne rd15 + addi r15, r3, 0 +rd15: cmpi 0, r7, 27 /* Save byte 27 in r16 */ + bne rd16 + addi r16, r3, 0 +rd16: cmpi 0, r7, 29 /* Save byte 29 in r17 */ + bne rd17 + addi r17, r3, 0 +rd17: cmpi 0, r7, 30 /* Save byte 30 in r18 */ + bne rd18 + addi r18, r3, 0 +rd18: cmpi 0, r7, 9 /* Save byte 9 in r19 */ + bne rd19 + addi r19, r3, 0 +rd19: cmpi 0, r7, 23 /* Save byte 23 in r20 */ + bne rd20 + addi r20, r3, 0 +rd20: cmpi 0, r7, 25 /* Save byte 25 in r21 */ + bne rd21 + addi r21, r3, 0 +rd21: + + /* Calculate checksum of the first 63 bytes */ + /*----------------------------------------- */ + cmpi 0, r7, 63 + bgt rd31 + beq rd30 + add r8, r8, r3 + bl rd31 + + /* Verify checksum at byte 63 */ + /*--------------------------- */ +rd30: andi. r8, r8, 0xff /* use only 8 bits */ + cmp 0, r8, r3 + beq rd31 + addi r4, 0, LED_SDRAM_CODE_8 + addis r5, 0, 0x1000 + ori r5, r5, 0x0001 + stb r4,0(r5) + eieio +rderr: bl rderr + +rd31: + + /* Increment byte counter and check whether all bytes have been read. */ + /*------------------------------------------------------------------- */ + addi r7, r7, 1 + cmpi 0, r7, 127 + bgt rd05 + bl rdlp +rd05: + mtlr r5 /* restore lr */ + blr + +wait_i2c_transfer_done: + mflr r6 +wt01: READ_I2C(IICSTS) + andi. r4, r3, IIC_STS_PT + cmpi 0, r4, IIC_STS_PT + beq wt01 + mtlr r6 /* restore lr */ + blr + +/*--------------------------------------------------------------------- */ +/* Function: find_mode */ +/* Description: Determines addressing mode to be used dependent on */ +/* number of rows (r10 = byte 3 from SPD), number of columns (r11 = */ +/* byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */ +/* mode is returned in r3. */ +/* (It would be nicer having a table, pnc). */ +/*--------------------------------------------------------------------- */ +find_mode: + + mflr r5 + + cmpi 0, r10, 11 + bne fm01 + cmpi 0, r11, 9 + bne fm01 + cmpi 0, r13, 2 + bne fm01 + addi r3, 0, 1 + bl fmfound + +fm01: cmpi 0, r10, 11 + bne fm02 + cmpi 0, r11, 10 + bne fm02 + cmpi 0, r13, 2 + bne fm02 + addi r3, 0, 1 + bl fmfound + +fm02: cmpi 0, r10, 12 + bne fm03 + cmpi 0, r11, 9 + bne fm03 + cmpi 0, r13, 4 + bne fm03 + addi r3, 0, 2 + bl fmfound + +fm03: cmpi 0, r10, 12 + bne fm04 + cmpi 0, r11, 10 + bne fm04 + cmpi 0, r13, 4 + bne fm04 + addi r3, 0, 2 + bl fmfound + +fm04: cmpi 0, r10, 13 + bne fm05 + cmpi 0, r11, 9 + bne fm05 + cmpi 0, r13, 4 + bne fm05 + addi r3, 0, 3 + bl fmfound + +fm05: cmpi 0, r10, 13 + bne fm06 + cmpi 0, r11, 10 + bne fm06 + cmpi 0, r13, 4 + bne fm06 + addi r3, 0, 3 + bl fmfound + +fm06: cmpi 0, r10, 13 + bne fm07 + cmpi 0, r11, 11 + bne fm07 + cmpi 0, r13, 4 + bne fm07 + addi r3, 0, 3 + bl fmfound + +fm07: cmpi 0, r10, 12 + bne fm08 + cmpi 0, r11, 8 + bne fm08 + cmpi 0, r13, 2 + bne fm08 + addi r3, 0, 4 + bl fmfound + +fm08: cmpi 0, r10, 12 + bne fm09 + cmpi 0, r11, 8 + bne fm09 + cmpi 0, r13, 4 + bne fm09 + addi r3, 0, 4 + bl fmfound + +fm09: cmpi 0, r10, 11 + bne fm10 + cmpi 0, r11, 8 + bne fm10 + cmpi 0, r13, 2 + bne fm10 + addi r3, 0, 5 + bl fmfound + +fm10: cmpi 0, r10, 11 + bne fm11 + cmpi 0, r11, 8 + bne fm11 + cmpi 0, r13, 4 + bne fm11 + addi r3, 0, 5 + bl fmfound + +fm11: cmpi 0, r10, 13 + bne fm12 + cmpi 0, r11, 8 + bne fm12 + cmpi 0, r13, 2 + bne fm12 + addi r3, 0, 6 + bl fmfound + +fm12: cmpi 0, r10, 13 + bne fm13 + cmpi 0, r11, 8 + bne fm13 + cmpi 0, r13, 4 + bne fm13 + addi r3, 0, 6 + bl fmfound + +fm13: cmpi 0, r10, 13 + bne fm14 + cmpi 0, r11, 9 + bne fm14 + cmpi 0, r13, 2 + bne fm14 + addi r3, 0, 7 + bl fmfound + +fm14: cmpi 0, r10, 13 + bne fm15 + cmpi 0, r11, 10 + bne fm15 + cmpi 0, r13, 2 + bne fm15 + addi r3, 0, 7 + bl fmfound + +fm15: + /* not found, error code to be issued on LEDs */ + addi r7, 0, LED_SDRAM_CODE_2 + addis r6, 0, 0x1000 + ori r6, r6, 0x0001 + stb r7,0(r6) + eieio +fmerr: bl fmerr + +fmfound:addi r6, 0, 1 + subf r3, r6, r3 + + mtlr r5 /* restore lr */ + blr + +/*--------------------------------------------------------------------- */ +/* Function: find_size_code */ +/* Description: Determines size code to be used in configuring SDRAM controller */ +/* dependent on density (r15 = byte 31 from SPD) */ +/*--------------------------------------------------------------------- */ +find_size_code: + + mflr r5 + + addi r3, r15, 0 /* density */ + addi r7, 0, 0 +fs01: andi. r6, r3, 0x01 + cmpi 0, r6, 1 + beq fs04 + + addi r7, r7, 1 + cmpi 0, r7, 7 + bge fs02 + addi r9, 0, 1 + srw r3, r3, r9 + bl fs01 + + /* not found, error code to be issued on LEDs */ +fs02: addi r4, 0, LED_SDRAM_CODE_3 + addis r8, 0, 0x1000 + ori r8, r8, 0x0001 + stb r4,0(r8) + eieio +fs03: bl fs03 + +fs04: addi r3, r7, 0 + cmpi 0, r3, 0 + beq fs05 + addi r6, 0, 1 + subf r3, r6, r3 +fs05: + mtlr r5 /* restore lr */ + blr + +/*--------------------------------------------------------------------- */ +/* Function: find_casl */ +/* Description: Determines CAS latency */ +/*--------------------------------------------------------------------- */ +find_casl: + + mflr r5 + + andi. r14, r14, 0x7f /* r14 holds supported CAS latencies */ + addi r3, 0, 0xff /* preset determined CASL */ + addi r4, 0, 6 /* Start at bit 6 of supported CAS latencies */ + addi r2, 0, 0 /* Start finding highest CAS latency */ + +fc01: srw r6, r14, r4 /* */ + andi. r6, r6, 0x01 /* */ + cmpi 0, r6, 1 /* Check bit for current latency */ + bne fc06 /* If not supported, go to next */ + + cmpi 0, r2, 2 /* Check if third-highest latency */ + bge fc04 /* If so, go calculate with another format */ + + cmpi 0, r2, 0 /* Check if highest latency */ + bgt fc02 /* */ + addi r7, r19, 0 /* SDRAM cycle time for highest CAS latenty */ + + bl fc03 +fc02: + addi r7, r20, 0 /* SDRAM cycle time for next-highest CAS latenty */ +fc03: + addi r8, r7, 0 + addi r9, 0, 4 + srw r7, r7, r9 + andi. r7, r7, 0x0f + mulli r7, r7, 100 + andi. r8, r8, 0x0f + mulli r8, r8, 10 + add r7, r7, r8 + cmp 0, r7, r30 + bgt fc05 + addi r3, r2, 0 + bl fc05 +fc04: + addi r7, r21, 0 /* SDRAM cycle time for third-highest CAS latenty */ + addi r8, r7, 0 + addi r9, 0, 2 + srw r7, r7, r9 + andi. r7, r7, 0x3f + mulli r7, r7, 100 + andi. r8, r8, 0x03 + mulli r8, r8, 25 + add r7, r7, r8 + + cmp 0, r7, r30 + bgt fc05 + addi r3, r2, 0 + +fc05: addi r2, r2, 1 /* next latency */ + cmpi 0, r2, 3 + bge fc07 +fc06: addi r6, 0, 1 + subf r4, r6, r4 + cmpi 0, r4, 0 + bne fc01 + +fc07: + + mtlr r5 /* restore lr */ + blr +#endif + + +/* Peripheral Bank 1 Access Parameters */ +/* 0 BME = 1 ; burstmode enabled */ +/* " 1:8" TWT=00110110 ;Transfer wait (details below) */ +/* 1:5 FWT=00110 ; first wait = 6 cycles */ +/* 6:8 BWT=110 ; burst wait = 6 cycles */ +/* 9:11 000 ; reserved */ +/* 12:13 CSN=00 ; chip select on timing = 0 */ +/* 14:15 OEN=01 ; output enable */ +/* 16:17 WBN=01 ; write byte enable on timing 1 cycle */ +/* 18:19 WBF=01 ; write byte enable off timing 1 cycle */ +/* 20:22 TH=010 ; transfer hold = 2 cycles */ +/* 23 RE=0 ; ready enable = disabled */ +/* 24 SOR=1 ; sample on ready = same PerClk */ +/* 25 BEM=0 ; byte enable mode = only for write cycles */ +/* 26 PEN=0 ; parity enable = disable */ +/* 27:31 00000 ;reserved */ +/* */ +/* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */ +/* */ +/* */ +/* Code for BDI probe: */ +/* */ +/* WDCR 18 0x00000011 ;Select PB1AP */ +/* WDCR 19 0x1b015480 ;PB1AP: Flash */ +/* */ +/* Peripheral Bank 0 Access Parameters */ +/* 0:11 BAS=0x200 ; base address select = 0x200 * 0x100000 (1MB) = */ +/* 12:14 BS=100 ; bank size = 16MB (100) / 32MB (101) */ +/* 15:16 BU=11 ; bank usage = read/write */ +/* 17:18 BW=00 ; bus width = 8-bit */ +/* 19:31 ; reserved */ +/* */ +/* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */ +/* WDCR 18 0x00000001 ;Select PB1CR */ +/* WDCR 19 0x20098000 ;PB1CR: 1MB at 0x00100000, r/w, 8bit */ + +/* For CPLD */ +/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */ +/* WDCR_EBC(pb5ap, 0x01010040) */ +/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ +/* WDCR_EBC(pb5cr, 0X10018000) */ +/* Access parms */ +/* 100 3 8 0 0 0 */ +/* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */ +/* Address : 0x10000000 */ +/* Size: 2 MB */ +/* Usage: read/write */ +/* Width: 32 bit */ + +/* For Genie onboard fpga 32 bit interface */ +/* 0 1 0 1 0 0 0 0 */ +/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */ +/* 0x01010000 */ +/* Access parms */ +/* 102 1 c 0 0 0 */ +/* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */ +/* Address : 0x10200000 */ +/* Size: 2 MB */ +/* Usage: read/write */ +/* Width: 32 bit */ + +/* Walnut fpga pb7ap */ +/* 0 1 8 1 5 2 8 0 */ +/* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */ +/* Walnut fpga pb7cr */ +/* 0xF0318000 */ +/* */ diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds new file mode 100644 index 0000000..d5dea82 --- /dev/null +++ b/board/exbitgen/u-boot.lds @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/exbitgen/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + . = ALIGN(4); + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/fads/Makefile b/board/fads/Makefile new file mode 100644 index 0000000..baa6c2e --- /dev/null +++ b/board/fads/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o lamp.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/fads/config.mk b/board/fads/config.mk new file mode 100644 index 0000000..621b9a2 --- /dev/null +++ b/board/fads/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and +# MPC885ADS boards +# + +TEXT_BASE = 0xFE000000 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/fads +HOST_CFLAGS += -I$(TOPDIR)/board/fads +HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/fads diff --git a/board/fads/fads.c b/board/fads/fads.c new file mode 100644 index 0000000..013b3cb --- /dev/null +++ b/board/fads/fads.c @@ -0,0 +1,953 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define _NOT_USED_ 0xFFFFFFFF + +/* ========================================================================= */ + +#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ + +#if defined(CONFIG_DRAM_50MHZ) +/* 50MHz tables */ +static const uint dram_60ns[] = +{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04, + 0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_, + 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c, + 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44, + 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00, + 0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, + 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; + +static const uint dram_70ns[] = +{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, + 0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_, + 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, + 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00, + 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04, + 0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_, + 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, + 0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; + +static const uint edo_60ns[] = +{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04, + 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_, + 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c, + 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c, + 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, + 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; + +static const uint edo_70ns[] = +{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04, + 0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_, + 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c, + 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00, + 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00, + 0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, + 0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; + +#elif defined(CONFIG_DRAM_25MHZ) + +/* 25MHz tables */ + +static const uint dram_60ns[] = +{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, + 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, + 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, + 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, + 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; + +static const uint dram_70ns[] = +{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, + 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, + 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, + 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, + 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; + +static const uint edo_60ns[] = +{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c, + 0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48, + 0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; + +static const uint edo_70ns[] = +{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00, + 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00, + 0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00, + 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00, + 0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; +#else +#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ +#endif + +/* ------------------------------------------------------------------------- */ +static int _draminit (uint base, uint noMbytes, uint edo, uint delay) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* init upm */ + + switch (delay) { + case 70: + if (edo) { + upmconfig (UPMA, (uint *) edo_70ns, + sizeof (edo_70ns) / sizeof (uint)); + } else { + upmconfig (UPMA, (uint *) dram_70ns, + sizeof (dram_70ns) / sizeof (uint)); + } + + break; + + case 60: + if (edo) { + upmconfig (UPMA, (uint *) edo_60ns, + sizeof (edo_60ns) / sizeof (uint)); + } else { + upmconfig (UPMA, (uint *) dram_60ns, + sizeof (dram_60ns) / sizeof (uint)); + } + + break; + + default: + return -1; + } + + memctl->memc_mptpr = 0x0400; /* divide by 16 */ + + switch (noMbytes) { + case 4: /* 4 Mbyte uses only CS2 */ +#ifdef CONFIG_ADS + memctl->memc_mamr = 0xc0a21114; +#else + memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ +#endif + memctl->memc_or2 = 0xffc00800; /* 4M */ + break; + + case 8: /* 8 Mbyte uses both CS3 and CS2 */ + memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ + memctl->memc_or3 = 0xffc00800; /* 4M */ + memctl->memc_br3 = 0x00400081 + base; + memctl->memc_or2 = 0xffc00800; /* 4M */ + break; + + case 16: /* 16 Mbyte uses only CS2 */ +#ifdef CONFIG_ADS /* XXX: why PTA=0x60 only in 16M case? - NTL */ + memctl->memc_mamr = 0x60b21114; /* PTA 0x60 AMA 011 */ +#else + memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ +#endif + memctl->memc_or2 = 0xff000800; /* 16M */ + break; + + case 32: /* 32 Mbyte uses both CS3 and CS2 */ + memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ + memctl->memc_or3 = 0xff000800; /* 16M */ + memctl->memc_br3 = 0x01000081 + base; + memctl->memc_or2 = 0xff000800; /* 16M */ + break; + + default: + return -1; + } + + memctl->memc_br2 = 0x81 + base; /* use upma */ + + *((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */ + + /* if no dimm is inserted, noMbytes is still detected as 8m, so + * sanity check top and bottom of memory */ + + /* check bytes / 2 because get_ram_size tests at base+bytes, which + * is not mapped */ + if (noMbytes == 8) + if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) { + *((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */ + return -1; + } + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +static void _dramdisable(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_br2 = 0x00000000; + memctl->memc_br3 = 0x00000000; + + /* maybe we should turn off upma here or something */ +} +#endif /* !CONFIG_MPC885ADS */ + +/* ========================================================================= */ + +#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */ + +#if defined(CONFIG_SDRAM_100MHZ) + +/* ------------------------------------------------------------------------- */ +/* sdram table by Dan Malek */ + +/* This has the stretched early timing so the 50 MHz + * processor can make the 100 MHz timing. This will + * work at all processor speeds. + */ + +#ifdef SDRAM_ALT_INIT_SEQENCE +# define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ +#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0 +# define SDRAM_MCRVALUE0 0x80808111 /* run upmb cs4 loop 1 addr 0x11 MRS */ +# define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 /* ??? why not 0x80808130? */ +#else +# define SDRAM_MxMR_PTx 195 +# define UPM_MRS_ADDR 0x11 +# define UPM_REFRESH_ADDR 0x30 /* or 0x11 if we want to be like above? */ +#endif /* !SDRAM_ALT_INIT_SEQUENCE */ + +static const uint sdram_table[] = +{ + /* single read. (offset 0 in upm RAM) */ + 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04, + 0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_, + + /* burst read. (offset 8 in upm RAM) */ + 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04, + 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00, + 0x1ff77c45, + + /* precharge + MRS. (offset 11 in upm RAM) */ + 0xeffbbc04, 0x1ff77c34, 0xefeabc34, + 0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* single write. (offset 18 in upm RAM) */ + 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04, + 0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* burst write. (offset 20 in upm RAM) */ + 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, + 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* refresh. (offset 30 in upm RAM) */ + 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* exception. (offset 3c in upm RAM) */ + 0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ }; + +#elif defined(CONFIG_SDRAM_50MHZ) + +/* ------------------------------------------------------------------------- */ +/* sdram table stolen from the fads manual */ +/* for chip MB811171622A-100 */ + +/* this table is for 32-50MHz operation */ +#ifdef SDRAM_ALT_INIT_SEQENCE +# define SDRAM_MBMRVALUE0 0x80802114 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ +# define SDRAM_MBMRVALUE1 0x80802118 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */ +# define SDRAM_MCRVALUE0 0x80808105 /* run upmb cs4 loop 1 addr 0x5 MRS */ +# define SDRAM_MCRVALUE1 0x80808130 /* run upmb cs4 loop 1 addr 0x30 REFRESH */ +# define SDRAM_MPTRVALUE 0x400 +#define SDRAM_MARVALUE 0x88 +#else +# define SDRAM_MxMR_PTx 128 +# define UPM_MRS_ADDR 0x5 +# define UPM_REFRESH_ADDR 0x30 +#endif /* !SDRAM_ALT_INIT_SEQUENCE */ + +static const uint sdram_table[] = +{ + /* single read. (offset 0 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, + 0x1ff77c47, + + /* precharge + MRS. (offset 5 in upm RAM) */ + 0x1ff77c34, 0xefeabc34, 0x1fb57c35, + + /* burst read. (offset 8 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* single write. (offset 18 in upm RAM) */ + 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* burst write. (offset 20 in upm RAM) */ + 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, + 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* refresh. (offset 30 in upm RAM) */ + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* exception. (offset 3c in upm RAM) */ + 0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; + +/* ------------------------------------------------------------------------- */ +#else +#error SDRAM not correctly configured +#endif +/* ------------------------------------------------------------------------- */ + +/* + * Memory Periodic Timer Prescaler + */ + +#define SDRAM_OR4VALUE 0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */ +#define SDRAM_BR4VALUE 0x000000c1 /* UPMB,base addr or'ed on later */ + +/* ------------------------------------------------------------------------- */ +#ifdef SDRAM_ALT_INIT_SEQENCE +/* ------------------------------------------------------------------------- */ + +static int _initsdram(uint base, uint noMbytes) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); + + memctl->memc_mptpr = SDRAM_MPTPRVALUE; + + /* Configure the refresh (mostly). This needs to be + * based upon processor clock speed and optimized to provide + * the highest level of performance. For multiple banks, + * this time has to be divided by the number of banks. + * Although it is not clear anywhere, it appears the + * refresh steps through the chip selects for this UPM + * on each refresh cycle. + * We have to be careful changing + * UPM registers after we ask it to run these commands. + */ + + memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ + memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */ + + udelay(200); + + /* Now run the precharge/nop/mrs commands. + */ + + memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50Mhz) */ + /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100Mhz) */ + udelay(200); + + /* Run 8 refresh cycles */ + + memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 Mhz)*/ + /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */ + + udelay(200); + + memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 Mhz) or TLF 8 (50MHz) */ + memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 Mhz) */ + /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */ + + udelay(200); + + memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ + + memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); + memctl->memc_br4 = SDRAM_BR4VALUE | base; + + return 0; +} + +/* ------------------------------------------------------------------------- */ +#else /* !SDRAM_ALT_INIT_SEQUENCE */ +/* ------------------------------------------------------------------------- */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +# define MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +# define MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +# define MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +# define MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MxMR settings for SDRAM + */ + +/* 8 column SDRAM */ +# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTBE | \ + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) +/* 9 column SDRAM */ +# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTAE | \ + MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) + +static int _initsdram(uint base, uint noMbytes) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); + + memctl->memc_mptpr = MPTPR_2BK_4K; + memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */ + + /* map CS 4 */ + memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); + memctl->memc_br4 = SDRAM_BR4VALUE | base; + + /* Perform SDRAM initilization */ +# ifdef UPM_NOP_ADDR /* not currently in UPM table */ + /* step 1: nop */ + memctl->memc_mar = 0x00000000; + memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | + MCR_MLCF(0) | UPM_NOP_ADDR; +# endif + + /* step 2: delay */ + udelay(200); + +# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */ + /* step 3: precharge */ + memctl->memc_mar = 0x00000000; + memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | + MCR_MLCF(4) | UPM_PRECHARGE_ADDR; +# endif + + /* step 4: refresh */ + memctl->memc_mar = 0x00000000; + memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | + MCR_MLCF(2) | UPM_REFRESH_ADDR; + + /* + * note: for some reason, the UPM values we are using include + * precharge with MRS + */ + + /* step 5: mrs */ + memctl->memc_mar = 0x00000088; + memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | + MCR_MLCF(1) | UPM_MRS_ADDR; + +# ifdef UPM_NOP_ADDR + memctl->memc_mar = 0x00000000; + memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | + MCR_MLCF(0) | UPM_NOP_ADDR; +# endif + /* + * Enable refresh + */ + + memctl->memc_mbmr |= MBMR_PTBE; + return 0; +} +#endif /* !SDRAM_ALT_INIT_SEQUENCE */ + +/* ------------------------------------------------------------------------- */ + +static void _sdramdisable(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_br4 = 0x00000000; + + /* maybe we should turn off upmb here or something */ +} + +/* ------------------------------------------------------------------------- */ + +static int initsdram(uint base, uint *noMbytes) +{ + uint m = CFG_SDRAM_SIZE>>20; + + /* _initsdram needs access to sdram */ + *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */ + + if(!_initsdram(base, m)) + { + *noMbytes += m; + return 0; + } + else + { + *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */ + + _sdramdisable(); + + return -1; + } +} + +#endif /* CONFIG_FADS */ + +/* ========================================================================= */ + +long int initdram (int board_type) +{ + uint sdramsz = 0; /* size of sdram in Mbytes */ + uint base = 0; /* base of dram in bytes */ + uint m = 0; /* size of dram in Mbytes */ +#ifndef CONFIG_MPC885ADS + uint k, s; +#endif + +#ifdef CONFIG_FADS + if (!initsdram (0x00000000, &sdramsz)) { + base = sdramsz << 20; + printf ("(%u MB SDRAM) ", sdramsz); + } +#endif +#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ + k = (*((uint *) BCSR2) >> 23) & 0x0f; + + switch (k & 0x3) { + /* "MCM36100 / MT8D132X" */ + case 0x00: + m = 4; + break; + + /* "MCM36800 / MT16D832X" */ + case 0x01: + m = 32; + break; + /* "MCM36400 / MT8D432X" */ + case 0x02: + m = 16; + break; + /* "MCM36200 / MT16D832X ?" */ + case 0x03: + m = 8; + break; + + } + + switch (k >> 2) { + case 0x02: + k = 70; + break; + + case 0x03: + k = 60; + break; + + default: + printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k); + k = 70; + } + +#ifdef CONFIG_FADS + /* the FADS is missing this bit, all rams treated as non-edo */ + s = 0; +#else + s = (*((uint *) BCSR2) >> 27) & 0x01; +#endif + + if (!_draminit (base, m, s, k)) { + printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : ""); + } else { + _dramdisable (); + m = 0; + } +#endif /* !CONFIG_MPC885ADS */ + m += sdramsz; /* add sdram size to total */ + + return (m << 20); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ========================================================================= */ + +/* + * Check Board Identity: + */ + +#if defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) +static void checkdboard(void) +{ + /* get db type from BCSR 3 */ + uint k = (*((uint *)BCSR3) >> 24) & 0x3f; + + puts (" with db "); + + switch(k) { + case 0x03 : + puts ("MPC823"); + break; + case 0x20 : + puts ("MPC801"); + break; + case 0x21 : + puts ("MPC850"); + break; + case 0x22 : + puts ("MPC821, MPC860 / MPC860SAR / MPC860T"); + break; + case 0x23 : + puts ("MPC860SAR"); + break; + case 0x24 : + case 0x2A : + puts ("MPC860T"); + break; + case 0x3F : + puts ("MPC850SAR"); + break; + default : printf("0x%x", k); + } +} +#endif /* defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) */ + +int checkboard (void) +{ + /* get revision from BCSR 3 */ + uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) + | (((*((uint *) BCSR3) >> 19) & 1) << 2) + | (((*((uint *) BCSR3) >> 16) & 3)); + + puts ("Board: "); + +#if defined(CONFIG_MPC86xADS) + puts ("MPC86xADS"); +#elif defined(CONFIG_MPC885ADS) + puts ("MPC885ADS"); + r = 0; /* I've got NR (No Revision) board */ +#elif defined(CONFIG_FADS) + puts ("FADS"); + checkdboard (); +#else + puts ("ADS"); +#endif + puts (" rev "); + + switch (r) { +#if defined(CONFIG_ADS) + case 0x00: + puts ("ENG - this board sucks, check the errata, not supported\n"); + return -1; + case 0x01: + puts ("PILOT - warning, read errata \n"); + break; + case 0x02: + puts ("A - warning, read errata \n"); + break; + case 0x03: + puts ("B \n"); + break; +#elif defined(CONFIG_MPC885ADS) + case 0x00: + puts ("NR\n"); + break; +#else /* FADS and newer */ + case 0x00: + puts ("ENG\n"); + break; + case 0x01: + puts ("PILOT\n"); + break; +#endif /* CONFIG_ADS */ + default: + printf ("unknown (0x%x)\n", r); + return -1; + } + + return 0; +} + +/* ========================================================================= */ + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) + +#ifdef CFG_PCMCIA_MEM_ADDR +volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; +#endif + +int pcmcia_init(void) +{ + volatile pcmconf8xx_t *pcmp; + uint v, slota = 0, slotb = 0; + + /* + ** Enable the PCMCIA for a Flash card. + */ + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + +#if 0 + pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR; + pcmp->pcmc_por0 = 0xc00ff05d; +#endif + + /* Set all slots to zero by default. */ + pcmp->pcmc_pgcra = 0; + pcmp->pcmc_pgcrb = 0; +#ifdef CONFIG_PCMCIA_SLOT_A + pcmp->pcmc_pgcra = 0x40; +#endif +#ifdef CONFIG_PCMCIA_SLOT_B + pcmp->pcmc_pgcrb = 0x40; +#endif + + /* enable PCMCIA buffers */ + *((uint *)BCSR1) &= ~BCSR1_PCCEN; + + /* Check if any PCMCIA card is plugged in. */ + +#ifdef CONFIG_PCMCIA_SLOT_A + slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ; +#endif +#ifdef CONFIG_PCMCIA_SLOT_B + slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ; +#endif + + if (!(slota || slotb)) { + printf("No card present\n"); + pcmp->pcmc_pgcra = 0; + pcmp->pcmc_pgcrb = 0; + return -1; + } + else + printf("Card present ("); + + v = 0; + + /* both the ADS and the FADS have a 5V keyed pcmcia connector (?) + ** + ** Paolo - Yes, but i have to insert some 3.3V card in that slot on + ** my FADS... :-) + */ + +#if defined(CONFIG_MPC86x) + switch ((pcmp->pcmc_pipr >> 30) & 3) +#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850) + switch ((pcmp->pcmc_pipr >> 14) & 3) +#endif + { + case 0x00 : + printf("5V"); + v = 5; + break; + case 0x01 : + printf("5V and 3V"); +#ifdef CONFIG_FADS + v = 3; /* User lower voltage if supported! */ +#else + v = 5; +#endif + break; + case 0x03 : + printf("5V, 3V and x.xV"); +#ifdef CONFIG_FADS + v = 3; /* User lower voltage if supported! */ +#else + v = 5; +#endif + break; + } + + switch (v) { +#ifdef CONFIG_FADS + case 3: + printf("; using 3V"); + /* + ** Enable 3 volt Vcc. + */ + *((uint *)BCSR1) &= ~BCSR1_PCCVCC1; + *((uint *)BCSR1) |= BCSR1_PCCVCC0; + break; +#endif + case 5: + printf("; using 5V"); +#ifdef CONFIG_ADS + /* + ** Enable 5 volt Vcc. + */ + *((uint *)BCSR1) &= ~BCSR1_PCCVCCON; +#endif +#ifdef CONFIG_FADS + /* + ** Enable 5 volt Vcc. + */ + *((uint *)BCSR1) &= ~BCSR1_PCCVCC0; + *((uint *)BCSR1) |= BCSR1_PCCVCC1; +#endif + break; + + default: + *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */ + + printf("; unknown voltage"); + return -1; + } + printf(")\n"); + /* disable pcmcia reset after a while */ + + udelay(20); + +#ifdef CONFIG_PCMCIA_SLOT_A + pcmp->pcmc_pgcra = 0; +#endif +#ifdef CONFIG_PCMCIA_SLOT_B + pcmp->pcmc_pgcrb = 0; +#endif + + /* If you using a real hd you should give a short + * spin-up time. */ +#ifdef CONFIG_DISK_SPINUP_TIME + udelay(CONFIG_DISK_SPINUP_TIME); +#endif + + return 0; +} + +#endif /* CFG_CMD_PCMCIA */ + +/* ========================================================================= */ + +#ifdef CFG_PC_IDE_RESET + +void ide_set_reset(int on) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + + /* + * Configure PC for IDE Reset Pin + */ + if (on) { /* assert RESET */ + immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); + } else { /* release RESET */ + immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; + } + + /* program port pin as GPIO output */ + immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; +} + +#endif /* CFG_PC_IDE_RESET */ diff --git a/board/fads/fads.h b/board/fads/fads.h new file mode 100644 index 0000000..1127c7f --- /dev/null +++ b/board/fads/fads.h @@ -0,0 +1,514 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum, + * and Dan Malek + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * This header file contains values common to all FADS family boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * Flash Memory Map as used by U-Boot: + * + * Start Address Length + * +-----------------------+ 0xFE00_0000 Start of Flash ----------------- + * | | 0xFE00_0100 Reset Vector + * + + 0xFE0?_???? + * | U-Boot code | + * | | + * +-----------------------+ 0xFE04_0000 (sector border) + * | | + * | | + * | U-Boot environment | + * | | ^ + * | | | U-Boot + * +=======================+ 0xFE08_0000 (sector border) ----------------- + * | Available | | Applications + * | ... | v + * + *****************************************************************************/ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "dhcp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ + +/* + * New MPC86xADS and Duet provide two Ethernet connectivity options: + * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on + * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have + * got FEC so FEC is the default. + */ +#ifndef CONFIG_ADS +#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */ +#define CONFIG_FEC_ENET /* Use FEC ethernet */ +#else /* Old ADS has not got FEC option */ +#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */ +#undef CONFIG_FEC_ENET /* No FEC ethernet */ +#endif /* !CONFIG_ADS */ + +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#ifdef CONFIG_FEC_ENET +#define CFG_DISCOVER_PHY +#endif + +#ifndef CONFIG_COMMANDS +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_MII \ + | CFG_CMD_PCMCIA \ + | CFG_CMD_PING \ + ) +#endif /* !CONFIG_COMMANDS */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ +#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ +#elif defined(CONFIG_FADS) /* Old/new FADS */ +#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ +#else /* Old ADS */ +#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */ +#endif + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#if (CFG_SDRAM_SIZE) +#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ +#else +#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ +#endif /* CFG_SDRAM_SIZE */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ + +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ +#else +#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ +#endif /* CONFIG_BZIP2 */ + +/*----------------------------------------------------------------------- + * Flash organization + */ +#define CFG_FLASH_BASE CFG_MONITOR_BASE +#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ + +#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ +#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ + +#define CFG_DIRECT_FLASH_TFTP + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3" +#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)" +*/ + +#define CFG_JFFS2_SORT_FRAGMENTS +#endif /* CFG_CMD_JFFS2 */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * I2C configuration + */ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ +#define CFG_I2C_SLAVE 0x7F +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control + */ +#ifndef CFG_PLPRCR +#define CFG_PLPRCR PLPRCR_TEXPS +#endif + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the +* entire address space, we have to set the memory controller +* differently. Normally, you write the option register +* first, and then enable the chip select by writing the +* base register. For CS0, you must write the base register +* first, followed by the option register. +*/ + +/* + * Init Memory Controller: + * + * BR0/OR0 (Flash) + * BR1/OR1 (BCSR) + */ +/* the other CS:s are determined by looking at parameters in BCSRx */ + +#define BCSR_ADDR ((uint) 0xFF080000) + +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) + +/* BCSRx - Board Control and Status Registers */ +#define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* values according to the manual */ + +#define PCMCIA_MEM_ADDR ((uint)0xFF020000) +#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) + +#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) +#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) +#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) +#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) +#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) + +/* + * (F)ADS bitvalues by Helmut Buchsbaum + * + * See User's Manual for a proper + * description of the following structures + */ + +#define BCSR0_ERB ((uint)0x80000000) +#define BCSR0_IP ((uint)0x40000000) +#define BCSR0_BDIS ((uint)0x10000000) +#define BCSR0_BPS_MASK ((uint)0x0C000000) +#define BCSR0_ISB_MASK ((uint)0x01800000) +#define BCSR0_DBGC_MASK ((uint)0x00600000) +#define BCSR0_DBPC_MASK ((uint)0x00180000) +#define BCSR0_EBDF_MASK ((uint)0x00060000) + +#define BCSR1_FLASH_EN ((uint)0x80000000) +#define BCSR1_DRAM_EN ((uint)0x40000000) +#define BCSR1_ETHEN ((uint)0x20000000) +#define BCSR1_IRDEN ((uint)0x10000000) +#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) +#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) +#define BCSR1_BCSR_EN ((uint)0x02000000) +#define BCSR1_RS232EN_1 ((uint)0x01000000) +#define BCSR1_PCCEN ((uint)0x00800000) +#define BCSR1_PCCVCC0 ((uint)0x00400000) +#define BCSR1_PCCVPP_MASK ((uint)0x00300000) +#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) +#define BCSR1_RS232EN_2 ((uint)0x00040000) +#define BCSR1_SDRAM_EN ((uint)0x00020000) +#define BCSR1_PCCVCC1 ((uint)0x00010000) + +#define BCSR1_PCCVCCON BCSR1_PCCVCC0 + +#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) +#define BCSR2_FLASH_PD_SHIFT 28 +#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) +#define BCSR2_DRAM_PD_SHIFT 23 +#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) +#define BCSR2_DBREVNR_MASK ((uint)0x00030000) + +#define BCSR3_DBID_MASK ((ushort)0x3800) +#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) +#define BCSR3_BREVNR0 ((ushort)0x0080) +#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) +#define BCSR3_BREVN1 ((ushort)0x0008) +#define BCSR3_BREVN2_MASK ((ushort)0x0003) + +#define BCSR4_ETHLOOP ((uint)0x80000000) +#define BCSR4_TFPLDL ((uint)0x40000000) +#define BCSR4_TPSQEL ((uint)0x20000000) +#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) +#define BCSR4_FETH_EN ((uint)0x08000000) +#define BCSR4_FETHCFG0 ((uint)0x04000000) +#define BCSR4_FETHFDE ((uint)0x02000000) +#define BCSR4_FETHCFG1 ((uint)0x00400000) +#define BCSR4_FETHRST ((uint)0x00200000) + +#ifdef CONFIG_MPC823 +#define BCSR4_USB_EN ((uint)0x08000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860SAR +#define BCSR4_UTOPIA_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860SAR */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETH_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_USB_SPEED ((uint)0x04000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHCFG0 ((uint)0x04000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VCCO ((uint)0x02000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHFDE ((uint)0x02000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VIDEO_ON ((uint)0x00800000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC823 +#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHCFG1 ((uint)0x00400000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VIDEO_RST ((uint)0x00200000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHRST ((uint)0x00200000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_MODEM_EN ((uint)0x00100000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC823 +#define BCSR4_DATA_VOICE ((uint)0x00080000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC850 +#define BCSR4_DATA_VOICE ((uint)0x00080000) +#endif /* CONFIG_MPC850 */ + +/* BSCR5 exists on MPC86xADS and Duet ADS only */ + +#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) + +#define BCSR5 (CFG_PHYDEV_ADDR + 0x300) + +#define BCSR5_MII2_EN 0x40 +#define BCSR5_MII2_RST 0x20 +#define BCSR5_T1_RST 0x10 +#define BCSR5_ATM155_RST 0x08 +#define BCSR5_ATM25_RST 0x04 +#define BCSR5_MII1_EN 0x02 +#define BCSR5_MII1_RST 0x01 + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_ISO_PARTITION 1 + +#undef CONFIG_ATAPI +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR +#define CFG_ATA_IDE0_OFFSET 0x0000 + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0000 + +#define CONFIG_DISK_SPINUP_TIME 1000000 +#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */ diff --git a/board/fads/flash.c b/board/fads/flash.c new file mode 100644 index 0000000..f0fb621 --- /dev/null +++ b/board/fads/flash.c @@ -0,0 +1,560 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#define QUAD_ID(id) ((((ulong)(id) & 0xFF) << 24) | \ + (((ulong)(id) & 0xFF) << 16) | \ + (((ulong)(id) & 0xFF) << 8) | \ + (((ulong)(id) & 0xFF) << 0) \ + ) + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static int write_word (flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + vu_long *bcsr = (vu_long *)BCSR_ADDR; + unsigned long pd_size, total_size, bsize, or_am; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = 0; + flash_info[i].sector_count = 0; + flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */ + } + + switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) { + case 2: + case 4: + case 6: + pd_size = 0x800000; + or_am = 0xFF800000; + break; + + case 5: + case 7: + pd_size = 0x400000; + or_am = 0xFFC00000; + break; + + case 8: + pd_size = 0x200000; + or_am = 0xFFE00000; + break; + + default: + pd_size = 0; + or_am = 0xFFE00000; + printf("## Unsupported flash detected by BCSR: 0x%08X\n", bcsr[2]); + } + + total_size = 0; + for (i = 0; i < CFG_MAX_FLASH_BANKS && total_size < pd_size; ++i) { + bsize = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), + &flash_info[i]); + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, bsize, bsize >> 20); + } + + total_size += bsize; + } + + if (total_size != pd_size) { + printf("## Detected flash size %lu conflicts with PD data %lu\n", + total_size, pd_size); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = or_am | CFG_OR_TIMING_FLASH; + + for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) { +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + if (CFG_MONITOR_BASE >= flash_info[i].start[0]) + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[i]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + if (CFG_ENV_ADDR >= flash_info[i].start[0]) + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[i]); +#endif + } + + return total_size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_BM: + printf ("BRIGHT MICRO "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM080: + printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: + printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + * The following code can not run from flash! + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + short i; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x90909090; + + switch (addr[0]) { + case QUAD_ID(AMD_MANUFACT): + info->flash_id = FLASH_MAN_AMD; + break; + + case QUAD_ID(FUJ_MANUFACT): + info->flash_id = FLASH_MAN_FUJ; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + switch (addr[1]) { /* device ID */ + case QUAD_ID(AMD_ID_F040B): + case QUAD_ID(AMD_ID_LV040B): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00200000; + break; /* => 2 MB */ + + case QUAD_ID(AMD_ID_F080B): + info->flash_id += FLASH_AM080; + info->sector_count = 16; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif /* 0 */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + +#if 0 + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +#else + /* set sector offsets for uniform sector type */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = (ulong)addr + (i * 0x00040000); +#endif + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *) (info->start[i]); + info->protect[i] = addr[2] & 1; + } + + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *) info->start[0]; + *addr = 0xF0F0F0F0; /* reset bank */ + } + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + vu_long *addr = (vu_long *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return ERR_INVAL; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type - aborted\n"); + return ERR_UNKNOWN_FLASH_TYPE; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x80808080; + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long *) (info->start[sect]); + addr[0] = 0x30303030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long *) (info->start[l_sect]); + while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) + { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return ERR_TIMOUT; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned long *) info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *) (info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *) dest) & data) != data) { + return ERR_NOT_ERASED; + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0xA0A0A0A0; + + *((vu_long *) dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080)) + { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return ERR_TIMOUT; + } + } + return (0); +} diff --git a/board/fads/lamp.c b/board/fads/lamp.c new file mode 100644 index 0000000..4e58291 --- /dev/null +++ b/board/fads/lamp.c @@ -0,0 +1,47 @@ +#include + +#ifndef CONFIG_ADS /* Old ADS has not got any user-controllable LED */ + +#include + +void +signal_delay(unsigned int n) +{ + while (n--); +} + +void +signal_on(void) +{ + *((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */ +} + +void +signal_off(void) +{ + *((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */ +} + +void +slow_blink(unsigned int n) +{ + while (n--) { + signal_on(); + signal_delay(0x00400000); + signal_off(); + signal_delay(0x00400000); + } +} + +void +fast_blink(unsigned int n) +{ + while (n--) { + signal_on(); + signal_delay(0x00100000); + signal_off(); + signal_delay(0x00100000); + } +} + +#endif /* !CONFIG_ADS */ diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds new file mode 100644 index 0000000..21a2d9e --- /dev/null +++ b/board/fads/u-boot.lds @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + + /*. = DEFINED(env_offset) ? env_offset : .;*/ + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/fads/u-boot.lds.debug b/board/fads/u-boot.lds.debug new file mode 100644 index 0000000..650572d --- /dev/null +++ b/board/fads/u-boot.lds.debug @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/flagadm/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/flagadm/config.mk b/board/flagadm/config.mk new file mode 100644 index 0000000..9c72c79 --- /dev/null +++ b/board/flagadm/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8xxL boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c new file mode 100644 index 0000000..9c55367 --- /dev/null +++ b/board/flagadm/flagadm.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define _NOT_USED_ 0xFFFFFFFF + +/*Orginal table, GPL4 disabled*/ +const uint sdram_table[] = +{ + /* single read (offset 0x00 in upm ram) */ + 0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00, + 0x1ff74c47, + /* Precharge */ + 0x1FF74C05, + _NOT_USED_, + _NOT_USED_, + /* burst read (offset 0x08 in upm ram) */ + 0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00, + 0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* single write (offset 0x18 in upm ram) */ + 0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47, + /* Load moderegister */ + 0x1FF74C34, /*Precharge*/ + 0xEFEA8C34, /*NOP*/ + 0x1FB54C35, /*Load moderegister*/ + _NOT_USED_, + + /* burst write (offset 0x20 in upm ram) */ + 0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00, + 0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* refresh (offset 0x30 in upm ram) */ + 0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04, + 0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* exception (offset 0x3C in upm ram) */ + 0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* GPL5 driven every cycle */ +/* the display and the DSP */ +const uint dsp_disp_table[] = +{ + /* single read (offset 0x00 in upm ram) */ + 0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004, + 0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05, + /* burst read (offset 0x08 in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* single write (offset 0x18 in upm ram) */ + 0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004, + 0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05, + /* burst write (offset 0x20 in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* refresh (offset 0x30 in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* exception (offset 0x3C in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +int checkboard (void) +{ + puts ("Board: FlagaDM V3.0\n"); + return 0; +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0; + + memctl->memc_or2 = CFG_OR2; + memctl->memc_br2 = CFG_BR2; + + udelay(100); + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + memctl->memc_mptpr = MPTPR_PTP_DIV16; + memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_1X; + + /*Do the initialization of the SDRAM*/ + /*Start with the precharge cycle*/ + memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ + MCR_MLCF(1) | MCR_MAD(0x5)); + + /*Then we need two refresh cycles*/ + memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_2X; + memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ + MCR_MLCF(2) | MCR_MAD(0x30)); + + /*Mode register programming*/ + memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/ + memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ + MCR_MLCF(1) | MCR_MAD(0x1C)); + + /* That should do it, just enable the periodic refresh in burst of 4*/ + memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X; + memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS); + + size_b0 = 16*1024*1024; + + /* + * No bank 1 or 3 + * invalidate bank + */ + memctl->memc_br1 = 0; + memctl->memc_br3 = 0; + + upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint)); + + memctl->memc_mbmr = MBMR_GPL_B4DIS; + + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; + + return (size_b0); +} diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c new file mode 100644 index 0000000..fd0082c --- /dev/null +++ b/board/flagadm/flash.c @@ -0,0 +1,697 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +ulong flash_recognize (vu_long *base); +int write_word (flash_info_t *info, ulong dest, ulong data); +void flash_get_geometry (vu_long *base, flash_info_t *info); +void flash_unprotect(flash_info_t *info); +int _flash_real_protect(flash_info_t *info, long idx, int on); + + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + int i; + int rec; + + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | + (memctl->memc_br0 & ~(BR_BA_MSK)); + + rec = flash_recognize((vu_long*)CFG_FLASH_BASE); + + if (rec == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + flash_info[0].size, flash_info[0].size<<20); + } + +#if CFG_FLASH_PROTECTION + /*Unprotect all the flash memory*/ + flash_unprotect(&flash_info[0]); +#endif + + *((vu_short*)CFG_FLASH_BASE) = 0xffff; + + return (flash_info[0].size); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_OFFSET, + CFG_ENV_OFFSET+CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + return (flash_info[0].size); +} + + +int flash_get_protect_status(flash_info_t * info, long idx) +{ + vu_short * base; + ushort res; + +#ifdef DEBUG + printf("\n Attempting to set protection info with %d sectors\n", info->sector_count); +#endif + + + base = (vu_short*)info->start[idx]; + + *(base) = 0xffff; + + *(base + 0x55) = 0x0098; + res = base[0x2]; + + *(base) = 0xffff; + + if(res != 0) + res = 1; + else + res = 0; + + return res; +} + +void flash_get_geometry (vu_long *base, flash_info_t *info) +{ + int i,j; + ulong ner = 0; + vu_short * sb = (vu_short*)base; + ulong offset = (ulong)base; + + /* Read Device geometry */ + + *sb = 0xffff; + + *sb = 0x0090; + + info->flash_id = ((ulong)base[0x0]); +#ifdef DEBUG + printf("Id is %x\n", (uint)(ulong)info->flash_id); +#endif + + *sb = 0xffff; + + *(sb+0x55) = 0x0098; + + info->size = 1 << (sb[0x27]); /* Read flash size */ + +#ifdef DEBUG + printf("Size is %x\n", (uint)(ulong)info->size); +#endif + + *sb = 0xffff; + + *(sb + 0x55) = 0x0098; + ner = sb[0x2c] ; /*Number of erase regions*/ + +#ifdef DEBUG + printf("Number of erase regions %x\n", (uint)ner); +#endif + + info->sector_count = 0; + + for(i = 0; i < ner; i++) + { + uint s; + uint count; + uint t1,t2,t3,t4; + + *sb = 0xffff; + + *(sb + 0x55) = 0x0098; + + t1 = sb[0x2d + i*4]; + t2 = sb[0x2e + i*4]; + t3 = sb[0x2f + i*4]; + t4 = sb[0x30 + i*4]; + + count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/ + s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/ + +#ifdef DEBUG + printf("count and size %x, %x\n", count, s); + printf("sector count for erase region %d is %d\n", i, count); +#endif + for(j = 0; j < count; j++) + { +#ifdef DEBUG + printf("%x, ", (uint)offset); +#endif + info->start[ info->sector_count + j] = offset; + offset += s; + } + info->sector_count += count; + } + + if ((offset - (ulong)base) != info->size) + printf("WARNING reported size %x does not match to calculted size %x.\n" + , (uint)info->size, (uint)(offset - (ulong)base) ); + + /* Next check if there are any sectors protected.*/ + + for(i = 0; i < info->sector_count; i++) + info->protect[i] = flash_get_protect_status(info, i); + + *sb = 0xffff; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return ; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case INTEL_MANUFACT & FLASH_VENDMASK: + printf ("Intel "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case INTEL_ID_28F320C3B & FLASH_TYPEMASK: + printf ("28F320RC3(4 MB)\n"); + break; + case INTEL_ID_28F320J3A: + printf("28F320J3A (4 MB)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 4) == 0) + printf ("\n "); + printf (" %02d %08lX%s", + i, info->start[i], + info->protect[i]!=0 ? " (RO)" : " " + ); + } + printf ("\n"); + return ; +} + +ulong flash_recognize (vu_long *base) +{ + ulong id; + ulong res = FLASH_UNKNOWN; + vu_short * sb = (vu_short*)base; + + *sb = 0xffff; + + *sb = 0x0090; + id = base[0]; + + switch (id & 0x00FF0000) + { + case (MT_MANUFACT & 0x00FF0000): /* MT or => Intel */ + case (INTEL_ALT_MANU & 0x00FF0000): + res = FLASH_MAN_INTEL; + break; + default: + res = FLASH_UNKNOWN; + } + + *sb = 0xffff; + + return res; +} + +/*-----------------------------------------------------------------------*/ +#define INTEL_FLASH_STATUS_BLS 0x02 +#define INTEL_FLASH_STATUS_PSS 0x04 +#define INTEL_FLASH_STATUS_VPPS 0x08 +#define INTEL_FLASH_STATUS_PS 0x10 +#define INTEL_FLASH_STATUS_ES 0x20 +#define INTEL_FLASH_STATUS_ESS 0x40 +#define INTEL_FLASH_STATUS_WSMS 0x80 + +int flash_decode_status_bits(char status) +{ + int err = 0; + + if(!(status & INTEL_FLASH_STATUS_WSMS)) { + printf("Busy\n"); + err = -1; + } + + if(status & INTEL_FLASH_STATUS_ESS) { + printf("Erase suspended\n"); + err = -1; + } + + if(status & INTEL_FLASH_STATUS_ES) { + printf("Error in block erase\n"); + err = -1; + } + + if(status & INTEL_FLASH_STATUS_PS) { + printf("Error in programming\n"); + err = -1; + } + + if(status & INTEL_FLASH_STATUS_VPPS) { + printf("Vpp low, operation aborted\n"); + err = -1; + } + + if(status & INTEL_FLASH_STATUS_PSS) { + printf("Program is suspended\n"); + err = -1; + } + + if(status & INTEL_FLASH_STATUS_BLS) { + printf("Attempting to program/erase a locked sector\n"); + err = -1; + } + + if((status & INTEL_FLASH_STATUS_PS) && + (status & INTEL_FLASH_STATUS_ES) && + (status & INTEL_FLASH_STATUS_ESS)) { + printf("A command sequence error\n"); + return -1; + } + + return err; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_short *addr; + int flag, prot, sect; + ulong start, now; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + char tmp; + + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_short *)(info->start[sect]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Single Block Erase Command */ + *addr = 0x0020; + /* Confirm */ + *addr = 0x00D0; + /* Resume Command, as per errata update */ + *addr = 0x00D0; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + *addr = 0x70; /*Read status register command*/ + tmp = (short)*addr & 0x00FF; /* Read the status */ + while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + *addr = 0x0050; /* Reset the status register */ + *addr = 0xffff; + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - start) > 1000) { /* every second */ + putc ('.'); + } + udelay(100000); /* 100 ms */ + *addr = 0x0070; /*Read status register command*/ + tmp = (short)*addr & 0x00FF; /* Read status */ + start = get_timer(0); + } + if( tmp & INTEL_FLASH_STATUS_ES ) + flash_decode_status_bits(tmp); + + *addr = 0x0050; /* Reset the status register */ + *addr = 0xffff; /* Reset to read mode */ + } + } + + + printf (" done\n"); + return rcode; +} + +void flash_unprotect (flash_info_t *info) +{ + /*We can only unprotect the whole flash at once*/ + /*Therefore we must prevent the _flash_real_protect()*/ + /*from re-protecting sectors, that ware protected before */ + /*we called flash_real_protect();*/ + + int i; + + for(i = 0; i < info->sector_count; i++) + info->protect[i] = 0; + +#ifdef CFG_FLASH_PROTECTION + _flash_real_protect(info, 0, 0); +#endif +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_word (flash_info_t *info, ulong dest, ulong da) +{ + vu_short *addr = (vu_short *)dest; + ulong start; + char csr; + int flag; + ushort * d = (ushort*)&da; + int i; + + /* Check if Flash is (sufficiently) erased */ + if (((*addr & d[0]) != d[0]) || ((*(addr+1) & d[1]) != d[1])) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for(i = 0; i < 2; i++) + { + /* Write Command */ + *addr = 0x0010; + + /* Write Data */ + *addr = d[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + flag = 0; + *addr = 0x0070; /*Read statusregister command */ + while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + *addr = 0x0070; /*Read statusregister command */ + } + if (csr & INTEL_FLASH_STATUS_PSS) { + printf ("CSR indicates write error (%0x) at %08lx\n", + csr, (ulong)addr); + flag = 1; + } + + /* Clear Status Registers Command */ + *addr = 0x0050; + /* Reset to read array mode */ + *addr = 0xffff; + addr++; + } + + return (flag); +} + +int flash_real_protect(flash_info_t *info, long offset, int prot) +{ + int i, idx; + + for(idx = 0; idx < info->sector_count; idx++) + if(info->start[idx] == offset) + break; + + if(idx==info->sector_count) + return -1; + + if(prot == 0) { + /* Unprotect one sector, which means unprotect all flash + * and reprotect the other protected sectors. + */ + _flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/ + info->protect[idx] = 0; + + for(i = 0; i < info->sector_count; i++) + if(info->protect[i]) + _flash_real_protect(info, i, 1); + } + else { + /* We can protect individual sectors */ + _flash_real_protect(info, idx, 1); + } + + for( i = 0; i < info->sector_count; i++) + info->protect[i] = flash_get_protect_status(info, i); + + return 0; +} + +int _flash_real_protect(flash_info_t *info, long idx, int prot) +{ + vu_short *addr; + int flag; + ushort cmd; + ushort tmp; + ulong now, start; + + if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { + printf ("Can't change protection for unknown flash type %08lx - aborted\n", + info->flash_id); + return -1; + } + + if(prot == 0) { + /*Unlock the sector*/ + cmd = 0x00D0; + } + else { + /*Lock the sector*/ + cmd = 0x0001; + } + + addr = (vu_short *)(info->start[idx]); + + /* If chip is busy, wait for it */ + start = get_timer(0); + *addr = 0x0070; /*Read status register command*/ + tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ + while(!(tmp & INTEL_FLASH_STATUS_WSMS)) { + /*Write State Machine Busy*/ + /*Wait untill done or timeout.*/ + if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + *addr = 0x0050; /* Reset the status register */ + *addr = 0xffff; /* Reset the chip */ + printf ("TTimeout\n"); + return 1; + } + *addr = 0x0070; + tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ + start = get_timer(0); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Unlock block*/ + *addr = 0x0060; + + *addr = cmd; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + *addr = 0x0070; /*Read status register command*/ + tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */ + while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { + /* Write State Machine Busy */ + if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + *addr = 0x0050; /* Reset the status register */ + *addr = 0xffff; + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - start) > 1000) { /* every second */ + putc ('.'); + } + udelay(100000); /* 100 ms */ + *addr = 0x70; /*Read status register command*/ + tmp = (short)*addr & 0x00FF; /* Read status */ + start = get_timer(0); + } + if( tmp & INTEL_FLASH_STATUS_PS ) + flash_decode_status_bits(tmp); + + *addr =0x0050; /*Clear status register*/ + + /* reset to read mode */ + *addr = 0xffff; + + return 0; +} diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds new file mode 100644 index 0000000..04995ea --- /dev/null +++ b/board/flagadm/u-boot.lds @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug new file mode 100644 index 0000000..3165d56 --- /dev/null +++ b/board/flagadm/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/funkwerk/vovpn-gw/Makefile b/board/funkwerk/vovpn-gw/Makefile new file mode 100644 index 0000000..f77cc60 --- /dev/null +++ b/board/funkwerk/vovpn-gw/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o m88e6060.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/funkwerk/vovpn-gw/config.mk b/board/funkwerk/vovpn-gw/config.mk new file mode 100644 index 0000000..e59b483 --- /dev/null +++ b/board/funkwerk/vovpn-gw/config.mk @@ -0,0 +1,21 @@ +# (C) Copyright 2004 +# Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) +# +# Support for the Elmeg VoVPN Gateway Module +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +TEXT_BASE = 0xfff00000 diff --git a/board/funkwerk/vovpn-gw/flash.c b/board/funkwerk/vovpn-gw/flash.c new file mode 100644 index 0000000..7dd0d3f --- /dev/null +++ b/board/funkwerk/vovpn-gw/flash.c @@ -0,0 +1,449 @@ +/* + * (C) Copyright 2004 + * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) + * + * Support for the Elmeg VoVPN Gateway Module + * ------------------------------------------ + * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3 + * and 28F128J3A flashs working in 8 Bit mode. + * + * Most of this code is taken from existing u-boot source code. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_READ_STATUS 0x70 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xd0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_SUSPEND_ERASE 0xb0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_WRITE_BUFF 0xe8 +#define FLASH_CMD_PROG_RESUME 0xd0 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xd0 +#define FLASH_STATUS_DONE 0x80 + +#define FLASH_WRITE_BUFFER_SIZE 32 + +#ifdef CFG_FLASH_16BIT +#define FLASH_WORD_SIZE unsigned short +#define FLASH_ID_MASK 0xffff +#define FLASH_CMD_ADDR_SHIFT 0 +#else +#define FLASH_WORD_SIZE unsigned char +#define FLASH_ID_MASK 0xff +/* A0 is not used in either 8x or 16x for READ ID */ +#define FLASH_CMD_ADDR_SHIFT 1 +#endif + + +static unsigned long +flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info) +{ + volatile FLASH_WORD_SIZE *p; + FLASH_WORD_SIZE value; + int i; + + addr[0] = FLASH_CMD_READ_ID; + + /* manufactor */ + value = addr[0 << FLASH_CMD_ADDR_SHIFT]; + switch (value) { + case (INTEL_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + *addr = FLASH_CMD_RESET; + return (0); + + } + + /* device */ + value = addr[1 << FLASH_CMD_ADDR_SHIFT]; + switch (value) { + case (INTEL_ID_28F320J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; + case (INTEL_ID_28F640J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; + case (INTEL_ID_28F128J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + *addr = FLASH_CMD_RESET; + return (0); + } + + /* setup sectors */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count); + } + + /* check protected sectors */ + for (i = 0; i < info->sector_count; i++) { + p = (volatile FLASH_WORD_SIZE *)(info->start[i]); + info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1; + } + + /* reset bank */ + *addr = FLASH_CMD_RESET; + return (info->size); +} + +unsigned long +flash_init(void) +{ + unsigned long size; + int i; + + for (i=0; i= CFG_FLASH_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_FLASH, + CFG_MONITOR_FLASH+CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif +#ifdef CFG_ENV_IS_IN_FLASH + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + return (size); +} + +void +flash_print_info(flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: printf ("28F320JA3 (32 Mbit)\n"); + break; + case FLASH_28F640J3A: printf ("28F640JA3 (64 Mbit)\n"); + break; + case FLASH_28F128J3A: printf ("28F128JA3 (128 Mbit)\n"); + break; + default: printf ("Unknown Chip Type"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +int +flash_erase(flash_info_t *info, int s_first, int s_last) +{ + unsigned long start, now, last; + int flag, prot, sect; + volatile FLASH_WORD_SIZE *addr; + FLASH_WORD_SIZE status; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return (1); + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Cannot erase unknown flash - aborted\n"); + return (1); + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect]) { + continue; + } + + addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + +#ifdef DEBUG + printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]); +#endif + + *addr = FLASH_CMD_CLEAR_STATUS; + *addr = FLASH_CMD_BLOCK_ERASE; + *addr = FLASH_CMD_ERASE_CONFIRM; + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Flash erase timeout at address %lx\n", info->start[sect]); + *addr = FLASH_CMD_SUSPEND_ERASE; + *addr = FLASH_CMD_RESET; + return (1); + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + *addr = FLASH_CMD_RESET; + } + printf (" done\n"); + return (0); +} + +static int +write_buff2( volatile FLASH_WORD_SIZE *dst, + volatile FLASH_WORD_SIZE *src, + unsigned long cnt ) +{ + unsigned long start; + FLASH_WORD_SIZE status; + int flag, i; + + start = get_timer (0); + while (1) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + dst[0] = FLASH_CMD_WRITE_BUFF; + if ((status = *dst) & FLASH_STATUS_DONE) { + break; + } + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (-1); + } + } + dst[0] = (FLASH_WORD_SIZE)(cnt - 1); + for (i=0; i CFG_FLASH_WRITE_TOUT) { + *addr = FLASH_CMD_RESET; + return (-1); + } + } + *addr = FLASH_CMD_RESET; + return (0); +} + +/* + * write_buff return values: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ +int +write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt) +{ + volatile FLASH_WORD_SIZE *addr, *dst; + unsigned long bcnt; + int flag, i; + + if (info->flash_id == FLASH_UNKNOWN) { + return (4); + } + + addr = (volatile FLASH_WORD_SIZE *)(info->start[0]); + dst = (volatile FLASH_WORD_SIZE *) udst; + +#ifdef CFG_FLASH_16BIT +#error NYI +#else + while (cnt > 0) { + /* Check if buffer write is possible */ + if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) { + bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt; + /* Check if Flash is (sufficiently) erased */ + for (i=0; istart[sector]); + *addr = FLASH_CMD_CLEAR_STATUS; + *addr = FLASH_CMD_PROTECT; + + if(prot) { + *addr = FLASH_CMD_PROTECT_SET; + } else { + *addr = FLASH_CMD_PROTECT_CLEAR; + } + + /* wait for error or finish */ + start = get_timer (0); + while(!(addr[0] & FLASH_STATUS_DONE)){ + if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + printf("Flash protect timeout at address %lx\n", info->start[sector]); + addr[0] = FLASH_CMD_RESET; + return (1); + } + } + + /* Set software protect flag */ + info->protect[sector] = prot; + *addr = FLASH_CMD_RESET; + return (0); +} diff --git a/board/funkwerk/vovpn-gw/m88e6060.c b/board/funkwerk/vovpn-gw/m88e6060.c new file mode 100644 index 0000000..03a03d0 --- /dev/null +++ b/board/funkwerk/vovpn-gw/m88e6060.c @@ -0,0 +1,262 @@ +/* + * (C) Copyright 2004 + * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) + * + * Support for the Elmeg VoVPN Gateway Module + * ------------------------------------------ + * Initialize Marvell M88E6060 Switch + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "m88e6060.h" + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +static int prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 }; +static int phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 }; + +static m88x_regCfg_t prtCfg0[] = { + { 4, 0x3e7c, 0x8000 }, + { 4, 0x3e7c, 0x8003 }, + { 6, 0x0fc0, 0x001e }, + { -1, 0xffff, 0x0000 } +}; + +static m88x_regCfg_t prtCfg1[] = { + { 4, 0x3e7c, 0x8000 }, + { 4, 0x3e7c, 0x8003 }, + { 6, 0x0fc0, 0x001d }, + { -1, 0xffff, 0x0000 } +}; + +static m88x_regCfg_t prtCfg2[] = { + { 4, 0x3e7c, 0x8000 }, + { 4, 0x3e7c, 0x8003 }, + { 6, 0x0fc0, 0x001b }, + { -1, 0xffff, 0x0000 } +}; + +static m88x_regCfg_t prtCfg3[] = { + { 4, 0x3e7c, 0x8000 }, + { 4, 0x3e7c, 0x8003 }, + { 6, 0x0fc0, 0x0017 }, + { -1, 0xffff, 0x0000 } +}; + +static m88x_regCfg_t prtCfg4[] = { + { 4, 0x3e7c, 0x8000 }, + { 4, 0x3e7c, 0x8003 }, + { 6, 0x0fc0, 0x000f }, + { -1, 0xffff, 0x0000 } +}; + +static m88x_regCfg_t *prtCfg[M88X_PRT_CNT] = { + prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL +}; + +static m88x_regCfg_t phyCfgX[] = { + { 4, 0xfa1f, 0x01e0 }, + { 0, 0x213f, 0x1200 }, + { 24, 0x81ff, 0x1200 }, + { -1, 0xffff, 0x0000 } +}; + +static m88x_regCfg_t *phyCfg[M88X_PHY_CNT] = { + phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL +}; + +#if 0 +static void +m88e6060_dump( int devAddr ) +{ + int i, j; + unsigned short val[6]; + + printf( "M88E6060 Register Dump\n" ); + printf( "====================================\n" ); + printf( "PortNo 0 1 2 3 4 5\n" ); + for (i=0; i<6; i++) + miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] ); + printf( "STAT %04hx %04hx %04hx %04hx %04hx %04hx\n", + val[0],val[1],val[2],val[3],val[4],val[5] ); + + for (i=0; i<6; i++) + miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] ); + printf( "ID %04hx %04hx %04hx %04hx %04hx %04hx\n", + val[0],val[1],val[2],val[3],val[4],val[5] ); + + for (i=0; i<6; i++) + miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] ); + printf( "CNTL %04hx %04hx %04hx %04hx %04hx %04hx\n", + val[0],val[1],val[2],val[3],val[4],val[5] ); + + for (i=0; i<6; i++) + miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] ); + printf( "VLAN %04hx %04hx %04hx %04hx %04hx %04hx\n", + val[0],val[1],val[2],val[3],val[4],val[5] ); + + for (i=0; i<6; i++) + miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] ); + printf( "PAV %04hx %04hx %04hx %04hx %04hx %04hx\n", + val[0],val[1],val[2],val[3],val[4],val[5] ); + + for (i=0; i<6; i++) + miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] ); + printf( "RX %04hx %04hx %04hx %04hx %04hx %04hx\n", + val[0],val[1],val[2],val[3],val[4],val[5] ); + + for (i=0; i<6; i++) + miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] ); + printf( "TX %04hx %04hx %04hx %04hx %04hx %04hx\n", + val[0],val[1],val[2],val[3],val[4],val[5] ); + + printf( "------------------------------------\n" ); + printf( "PhyNo 0 1 2 3 4\n" ); + for (i=0; i<9; i++) { + for (j=0; j<5; j++) { + miiphy_read( devAddr+phyTab[j],i,&val[j] ); + } + printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n", + i,val[0],val[1],val[2],val[3],val[4] ); + } + for (i=0x10; i<0x1d; i++) { + for (j=0; j<5; j++) { + miiphy_read( devAddr+phyTab[j],i,&val[j] ); + } + printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n", + i,val[0],val[1],val[2],val[3],val[4] ); + } +} +#endif + +int +m88e6060_initialize( int devAddr ) +{ + static char *_f = "m88e6060_initialize:"; + m88x_regCfg_t *p; + int err; + int i; + unsigned short val; + + /*** reset all phys into powerdown ************************************/ + for (i=0, err=0; ienetaddr + val = (ea[4] << 8) | ea[5]; + err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val ); + val = (ea[2] << 8) | ea[3]; + err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val ); + val = (ea[0] << 8) | ea[1]; +#undef ea + val &= 0xfeff; /* clear DiffAddr */ + err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val ); + if (err) { + printf( "%s [ERR] switch mac address register\n",_f ); + return( -1 ); + } + + /* !DiscardExcessive, MaxFrameSize, CtrMode */ + err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val ); + val &= 0xd870; + val |= 0x0500; + err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val ); + if (err) { + printf( "%s [ERR] switch global control register\n",_f ); + return( -1 ); + } + + /* LernDis off, ATUSize 1024, AgeTime 5min */ + err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val ); + val &= 0x000f; + val |= 0x2130; + err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val ); + if (err) { + printf( "%s [ERR] atu control register\n",_f ); + return( -1 ); + } + + /*** initialize ports *************************************************/ + for (i=0; ireg != -1) { + err = 0; + err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val ); + val &= p->msk; + val |= p->val; + err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val ); + if (err) { + printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg ); + /* XXX what todo */ + } + p++; + } + } + + /*** initialize phys **************************************************/ + for (i=0; ireg != -1) { + err = 0; + err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val ); + val &= p->msk; + val |= p->val; + err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val ); + if (err) { + printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg ); + /* XXX what todo */ + } + p++; + } + } + udelay(100000); + return( 0 ); +} +#endif diff --git a/board/funkwerk/vovpn-gw/m88e6060.h b/board/funkwerk/vovpn-gw/m88e6060.h new file mode 100644 index 0000000..15d4583 --- /dev/null +++ b/board/funkwerk/vovpn-gw/m88e6060.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2004 + * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) + * + * Support for the Elmeg VoVPN Gateway Module + * ------------------------------------------ + * Initialize Marvell M88E6060 Switch + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _INC_m88e6060_h_ +#define _INC_m88e6060_h_ + +/* ************************************************************************** */ +/* *** DEFINES ************************************************************** */ + +/* switch hw */ +#define M88X_PRT_CNT 6 +#define M88X_PHY_CNT 5 + +/* phy register offsets */ +#define M88X_PHY_CNTL 0x00 +#define M88X_PHY_STAT 0x00 +#define M88X_PHY_ID0 0x02 +#define M88X_PHY_ID1 0x03 +#define M88X_PHY_ANEG_ADV 0x04 +#define M88X_PHY_LPA 0x05 +#define M88X_PHY_ANEG_EXP 0x06 +#define M88X_PHY_NPT 0x07 +#define M88X_PHY_LPNP 0x08 + +/* port register offsets */ +#define M88X_PRT_STAT 0x00 +#define M88X_PRT_ID 0x03 +#define M88X_PRT_CNTL 0x04 +#define M88X_PRT_VLAN 0x06 +#define M88X_PRT_PAV 0x0b +#define M88X_PRT_RX 0x10 +#define M88X_PRT_TX 0x11 + +/* global/atu register offsets */ +#define M88X_GLB_STAT 0x00 +#define M88X_GLB_MAC01 0x01 +#define M88X_GLB_MAC23 0x02 +#define M88X_GLB_MAC45 0x03 +#define M88X_GLB_CNTL 0x04 +#define M88X_ATU_CNTL 0x0a +#define M88X_ATU_OP 0x0b + +/* id0 register - 0x02 */ +#define M88X_PHY_ID0_VALUE 0x0141 + +/* id1 register - 0x03 */ +#define M88X_PHY_ID1_VALUE 0x0c80 /* without revision ! */ + + +/* misc */ +#define M88E6060_ID ((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE) + +/* ************************************************************************** */ +/* *** TYPEDEFS ************************************************************* */ + +typedef struct { + int reg; + unsigned short msk; + unsigned short val; +} m88x_regCfg_t; + +/* ************************************************************************** */ +/* *** PROTOTYPES *********************************************************** */ + +extern int m88e6060_initialize( int ); + +#endif /* _INC_m88e6060_h_ */ diff --git a/board/funkwerk/vovpn-gw/u-boot.lds b/board/funkwerk/vovpn-gw/u-boot.lds new file mode 100644 index 0000000..bf8048d --- /dev/null +++ b/board/funkwerk/vovpn-gw/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c new file mode 100644 index 0000000..97f81ee --- /dev/null +++ b/board/funkwerk/vovpn-gw/vovpn-gw.c @@ -0,0 +1,375 @@ +/* + * (C) Copyright 2004 + * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) + * + * Support for the Elmeg VoVPN Gateway Module + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "m88e6060.h" + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */ + /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */ + /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */ + /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ + /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ + /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ + /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ + /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ + /* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */ + /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */ + /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */ + /* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */ + /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */ + /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */ + /* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */ + /* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */ + /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */ + /* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */ + /* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */ + /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */ + /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */ + /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */ + /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */ + /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */ + /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */ + /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */ + /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */ + /* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */ + /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */ + /* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */ + /* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */ + /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */ + /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */ + /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */ + /* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */ + /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */ + /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */ + /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */ + /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */ + /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */ + /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */ + /* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */ + /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */ + /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */ + /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */ + /* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */ + /* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */ + /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ + /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */ + /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */ + /* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */ + /* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */ + /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */ + /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ + } +}; + +void reset_phy (void) +{ + volatile ioport_t *iop; +#if (CONFIG_COMMANDS & CFG_CMD_NET) + int i; + unsigned short val; +#endif + + iop = ioport_addr((immap_t *)CFG_IMMR, 0); + + /* Reset the PHY */ + iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */ +#if (CONFIG_COMMANDS & CFG_CMD_NET) + udelay(20000); + iop->pdat |= 0x00080000; + for (i=0; i<100; i++) { + udelay(20000); + if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) { + break; + } + } + /* initialize switch */ + m88e6060_initialize( CFG_PHY_ADDR ); +#endif +} + +static unsigned long UPMATable[] = { + 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ + 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */ + 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ + 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ + 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ + 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ + 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */ +}; + +int board_early_init_f (void) +{ + volatile immap_t *immap; + volatile memctl8260_t *memctl; + volatile unsigned char *dummy; + int i; + + immap = (immap_t *) CFG_IMMR; + memctl = &immap->im_memctl; + +#if 0 + /* CS2-5 - DSP via UPMA */ + dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK); + memctl->memc_mar = 0; + memctl->memc_mamr = MxMR_OP_WARR; + for (i = 0; i < 64; i++) { + memctl->memc_mdr = UPMATable[i]; + *dummy = 0; + } + memctl->memc_mamr = 0x00044440; +#else + /* CS7 - DPRAM via UPMA */ + dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); + memctl->memc_mar = 0; + memctl->memc_mamr = MxMR_OP_WARR; + for (i = 0; i < 64; i++) { + memctl->memc_mdr = UPMATable[i]; + *dummy = 0; + } + memctl->memc_mamr = 0x00044440; +#endif + return 0; +} + +int misc_init_r (void) +{ + volatile ioport_t *iop; + unsigned char temp; +#if 0 + /* DUMP UPMA RAM */ + volatile immap_t *immap; + volatile memctl8260_t *memctl; + volatile unsigned char *dummy; + unsigned char c; + int i; + + immap = (immap_t *) CFG_IMMR; + memctl = &immap->im_memctl; + + + dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); + memctl->memc_mar = 0; + memctl->memc_mamr = MxMR_OP_RARR; + for (i = 0; i < 64; i++) { + c = *dummy; + printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i, + memctl->memc_mamr, + memctl->memc_mar, + memctl->memc_mdr ); + } + memctl->memc_mamr = 0x00044440; +#endif + /* enable buffers (DSP, DPRAM) */ + iop = ioport_addr((immap_t *)CFG_IMMR, 0); + iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */ + + /* destroy DPRAM magic */ + *(volatile unsigned char *)0xf0500000 = 0x00; + + /* clear any pending DPRAM irq */ + temp = *(volatile unsigned char *)0xf05003ff; + + /* write module-id into DPRAM */ + *(volatile unsigned char *)0xf0500201 = 0x50; + + return 0; +} + +#if defined(CONFIG_HAVE_OWN_RESET) +int +do_reset (void *cmdtp, int flag, int argc, char *argv[]) +{ + volatile ioport_t *iop; + + iop = ioport_addr((immap_t *)CFG_IMMR, 2); + iop->pdat |= 0x00002000; /* PC18 = HW_RESET */ + return 1; +} +#endif /* CONFIG_HAVE_OWN_RESET */ + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) + +long int initdram (int board_type) +{ +#ifndef CFG_RAMBOOT + volatile immap_t *immap; + volatile memctl8260_t *memctl; + volatile uchar *ramaddr; + int i; + uchar c; + + immap = (immap_t *) CFG_IMMR; + memctl = &immap->im_memctl; + ramaddr = (uchar *) CFG_SDRAM_BASE; + c = 0xff; + + immap->im_siu_conf.sc_ppc_acr = 0x02; + immap->im_siu_conf.sc_ppc_alrh = 0x01267893; + immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef; + immap->im_siu_conf.sc_tescr1 = 0x00000000; + immap->im_siu_conf.sc_tescr2 = 0x00000000; + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CFG_PSRT; + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM; + + /* Precharge all banks */ + memctl->memc_psdmr = CFG_PSDMR | 0x28000000; + *ramaddr = c; + + /* CBR refresh */ + memctl->memc_psdmr = CFG_PSDMR | 0x08000000; + for (i = 0; i < 8; i++) + *ramaddr = c; + + /* Mode Register write */ + memctl->memc_psdmr = CFG_PSDMR | 0x18000000; + *ramaddr = c; + + /* Refresh enable */ + memctl->memc_psdmr = CFG_PSDMR | 0x40000000; + *ramaddr = c; +#endif /* CFG_RAMBOOT */ + + return (CFG_SDRAM_SIZE); +} + +int checkboard (void) +{ +#ifdef CONFIG_CLKIN_66MHz + puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n"); +#else + puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n"); +#endif + return 0; +} diff --git a/board/g2000/Makefile b/board/g2000/Makefile new file mode 100644 index 0000000..5471d13 --- /dev/null +++ b/board/g2000/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o strataflash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/g2000/config.mk b/board/g2000/config.mk new file mode 100644 index 0000000..25b2105 --- /dev/null +++ b/board/g2000/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd PLU405 boards +# + +TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0x00FC0000 diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c new file mode 100644 index 0000000..3f78753 --- /dev/null +++ b/board/g2000/g2000.c @@ -0,0 +1,312 @@ +/* + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define MEM_MCOPT1_INIT_VAL 0x00800000 +#define MEM_RTR_INIT_VAL 0x04070000 +#define MEM_PMIT_INIT_VAL 0x07c00000 +#define MEM_MB0CF_INIT_VAL 0x00082001 +#define MEM_MB1CF_INIT_VAL 0x04082000 +#define MEM_SDTR1_INIT_VAL 0x00854005 +#define SDRAM0_CFG_ENABLE 0x80000000 + +#define CFG_SDRAM_SIZE 0x04000000 /* 64 MB */ + +int board_early_init_f (void) +{ +#if 0 /* test-only */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000010); + mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */ + mtdcr (uictr, 0x00000010); /* set int trigger levels */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ +#else + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ +#endif + +#if 1 /* test-only */ + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ +#endif + + return 0; +} + + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); +#endif + + return (0); +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming G2000"); + } else { + puts(str); + } + + putc ('\n'); + + return 0; +} + + +/* ------------------------------------------------------------------------- + G2000 rev B is an embeded design. we don't read for spd of this version. + Doing static SDRAM controller configuration in the following section. + ------------------------------------------------------------------------- */ + +long int init_sdram_static_settings(void) +{ +#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) + /* disable memcontroller so updates work */ + mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL ); + mtsdram0( mem_rtr , MEM_RTR_INIT_VAL ); + mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL ); + mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL ); + mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL ); + mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL ); + + /* SDRAM have a power on delay, 500 micro should do */ + udelay(500); + mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); + + return (CFG_SDRAM_SIZE); /* CFG_SDRAM_SIZE is in G2000.h */ + } + + +long int initdram (int board_type) +{ + long int ret; + +/* flzt, we can still turn this on in the future */ +/* #ifdef CONFIG_SPD_EEPROM + ret = spd_sdram (); +#else + ret = init_sdram_static_settings(); +#endif +*/ + + ret = init_sdram_static_settings(); + + return ret; +} + + +#if 1 /* test-only */ +void sdram_init(void) +{ + init_sdram_static_settings(); +} +#endif + + +#if 0 /* test-only */ +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} +#endif + + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif + + +#if 0 /* test-only !!! */ +int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong ap, cr; + + printf("\nEBC registers for PPC405GP:\n"); + mfebc(pb0ap, ap); mfebc(pb0cr, cr); + printf("0: AP=%08lx CP=%08lx\n", ap, cr); + mfebc(pb1ap, ap); mfebc(pb1cr, cr); + printf("1: AP=%08lx CP=%08lx\n", ap, cr); + mfebc(pb2ap, ap); mfebc(pb2cr, cr); + printf("2: AP=%08lx CP=%08lx\n", ap, cr); + mfebc(pb3ap, ap); mfebc(pb3cr, cr); + printf("3: AP=%08lx CP=%08lx\n", ap, cr); + mfebc(pb4ap, ap); mfebc(pb4cr, cr); + printf("4: AP=%08lx CP=%08lx\n", ap, cr); + printf("\n"); + + return 0; +} +U_BOOT_CMD( + dumpebc, 1, 1, do_dumpebc, + "dumpebc - Dump all EBC registers\n", + NULL +); + + +int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + + printf("\nDevice Configuration Registers (DCR's) for PPC405GP:"); + for (i=0; i<=0x1e0; i++) { + if (!(i % 0x8)) { + printf("\n%04x ", i); + } + printf("%08lx ", get_dcr(i)); + } + printf("\n"); + + return 0; +} +U_BOOT_CMD( + dumpdcr, 1, 1, do_dumpdcr, + "dumpdcr - Dump all DCR registers\n", + NULL +); + + +int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:"); + printf("\n%04x %08x ", 947, mfspr(947)); + printf("\n%04x %08x ", 9, mfspr(9)); + printf("\n%04x %08x ", 1014, mfspr(1014)); + printf("\n%04x %08x ", 1015, mfspr(1015)); + printf("\n%04x %08x ", 1010, mfspr(1010)); + printf("\n%04x %08x ", 957, mfspr(957)); + printf("\n%04x %08x ", 1008, mfspr(1008)); + printf("\n%04x %08x ", 1018, mfspr(1018)); + printf("\n%04x %08x ", 954, mfspr(954)); + printf("\n%04x %08x ", 950, mfspr(950)); + printf("\n%04x %08x ", 951, mfspr(951)); + printf("\n%04x %08x ", 981, mfspr(981)); + printf("\n%04x %08x ", 980, mfspr(980)); + printf("\n%04x %08x ", 982, mfspr(982)); + printf("\n%04x %08x ", 1012, mfspr(1012)); + printf("\n%04x %08x ", 1013, mfspr(1013)); + printf("\n%04x %08x ", 948, mfspr(948)); + printf("\n%04x %08x ", 949, mfspr(949)); + printf("\n%04x %08x ", 1019, mfspr(1019)); + printf("\n%04x %08x ", 979, mfspr(979)); + printf("\n%04x %08x ", 8, mfspr(8)); + printf("\n%04x %08x ", 945, mfspr(945)); + printf("\n%04x %08x ", 987, mfspr(987)); + printf("\n%04x %08x ", 287, mfspr(287)); + printf("\n%04x %08x ", 953, mfspr(953)); + printf("\n%04x %08x ", 955, mfspr(955)); + printf("\n%04x %08x ", 272, mfspr(272)); + printf("\n%04x %08x ", 273, mfspr(273)); + printf("\n%04x %08x ", 274, mfspr(274)); + printf("\n%04x %08x ", 275, mfspr(275)); + printf("\n%04x %08x ", 260, mfspr(260)); + printf("\n%04x %08x ", 276, mfspr(276)); + printf("\n%04x %08x ", 261, mfspr(261)); + printf("\n%04x %08x ", 277, mfspr(277)); + printf("\n%04x %08x ", 262, mfspr(262)); + printf("\n%04x %08x ", 278, mfspr(278)); + printf("\n%04x %08x ", 263, mfspr(263)); + printf("\n%04x %08x ", 279, mfspr(279)); + printf("\n%04x %08x ", 26, mfspr(26)); + printf("\n%04x %08x ", 27, mfspr(27)); + printf("\n%04x %08x ", 990, mfspr(990)); + printf("\n%04x %08x ", 991, mfspr(991)); + printf("\n%04x %08x ", 956, mfspr(956)); + printf("\n%04x %08x ", 284, mfspr(284)); + printf("\n%04x %08x ", 285, mfspr(285)); + printf("\n%04x %08x ", 986, mfspr(986)); + printf("\n%04x %08x ", 984, mfspr(984)); + printf("\n%04x %08x ", 256, mfspr(256)); + printf("\n%04x %08x ", 1, mfspr(1)); + printf("\n%04x %08x ", 944, mfspr(944)); + printf("\n"); + + return 0; +} +U_BOOT_CMD( + dumpspr, 1, 1, do_dumpspr, + "dumpspr - Dump all SPR registers\n", + NULL +); +#endif diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c new file mode 100644 index 0000000..8446e02 --- /dev/null +++ b/board/g2000/strataflash.c @@ -0,0 +1,793 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for ppcboot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + +#define FLASH_MAN_CFI 0x01000000 + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char * cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *)(info->start[sect] + (offset * info->portwidth))); +} +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | + (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + unsigned long address; + + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif +#else + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + - CFG_MONITOR_LEN, + - 1, &flash_info[1]); +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if( info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3 ), (info->chipwidth << 3 )); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + int k; + int size; + int erased; + volatile unsigned long *flash; + + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); +#endif + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for(i=0;iportwidth) && (cnt > 0) ; i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *)cp)); + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while(cnt >= info->portwidth) { + i = info->buffer_size > cnt? cnt: info->buffer_size; + if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + /* handle the aligned part */ + while(cnt >= info->portwidth) { + cword.l = 0; + for(i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; iportwidth; ++i, ++cp) { + flash_add_byte(info, & cword, (*(uchar *)cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if(prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, + prot?"protect":"unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if(prot == 0) { + int i; + for(i = 0 ; isector_count; i++) { + if(info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt,info->start[sector]); + if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ + printf("Command Sequence Error.\n"); + } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) +{ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) +{ + int i; + uchar *cp = (uchar *)cmdbuf; + for(i=0; i< info->portwidth; i++) + *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi(flash_info_t * info) +{ + + for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; + info->portwidth <<= 1) { + for(info->chipwidth =FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } + return 0; +} +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t * info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if(flash_detect_cfi(info)){ +#ifdef DEBUG_FLASH + printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif + sect_cnt = 0; + sector = base; + for(i = 0 ; i < num_erase_regions; i++) { + if(i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) +1; + for(j = 0; j< erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *)dest; + + + /* Check if Flash is (sufficiently) erased */ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if(!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if(flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t *info, ulong addr) +{ + int sector; + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *)dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + if (len & 0x1) { /* test-only: unaligned size */ + puts("\nUnalgined size!!!\n"); /* test-only */ + cnt++; + } + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar)cnt-1); + while(cnt-- > 0) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check(info, sector, info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/g2000/u-boot.lds b/board/g2000/u-boot.lds new file mode 100644 index 0000000..43f7765 --- /dev/null +++ b/board/g2000/u-boot.lds @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/gcplus/Makefile b/board/gcplus/Makefile new file mode 100644 index 0000000..1954d66 --- /dev/null +++ b/board/gcplus/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# 2003 (c) MontaVista Software, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := gcplus.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/gcplus/config.mk b/board/gcplus/config.mk new file mode 100644 index 0000000..57326b8 --- /dev/null +++ b/board/gcplus/config.mk @@ -0,0 +1,13 @@ +# +# ADS GCPlus board with SA1110 cpu +# +# The ADS GCPlus has 2 banks of 16 MiB SDRAM +# +# We use the ADS GCPlus Linux boot ROM to load U-Boot into SDRAM +# at c020'0000 and then move ourself to c8f0'0000. Basically, just +# install the U-Boot binary as you would the Linux zImage and then +# reap the benfits of more convenient Linux development cycles, i.e. +# bootp;tftp;bootm, repeat, etc.,. +# + +TEXT_BASE = 0xc8f00000 diff --git a/board/gcplus/flash.c b/board/gcplus/flash.c new file mode 100644 index 0000000..36d7363 --- /dev/null +++ b/board/gcplus/flash.c @@ -0,0 +1,440 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * 2003 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPW * addr, flash_info_t * info); +static int write_data(flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets(ulong base, flash_info_t * info); +void inline spin_wheel(void); + +/*----------------------------------------------------------------------- + */ + +unsigned long +flash_init(void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets(PHYS_FLASH_1, &flash_info[i]); + break; + default: + panic("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void +flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void +flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf("INTEL "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf("28F128J3A\n"); + break; + case FLASH_28F640J5: + printf("28F640J5\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong +flash_get_size(FPW * addr, flash_info_t * info) +{ + volatile FPW value; + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb(); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb(); + value = addr[1]; /* device ID */ + switch (value) { + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 16 MB */ + case (FPW) INTEL_ID_28F640J5: + info->flash_id += FLASH_28F640J5; + info->sector_count = 64; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int +flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + start = get_timer(0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = (FPW) 0x00500050; /* clear status register cmd. */ + *addr = (FPW) 0x00FF00FF; /* resest to read mode */ + + printf(" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int +write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data(info, wp, SWAP(data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data(info, wp, SWAP(data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data(info, wp, SWAP(data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int +write_data(flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("not erased at %08lX (%lX)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline +spin_wheel(void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/gcplus/gcplus.c b/board/gcplus/gcplus.c new file mode 100644 index 0000000..261e894 --- /dev/null +++ b/board/gcplus/gcplus.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * 2003-2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +int +board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = MACH_TYPE_GRAPHICSCLIENT; + + gd->bd->bi_boot_params = 0xc000003c; /* Weird address? */ + + /* Most of the ADS GCPlus I/O is connected to Static nCS2. + * So I'm brute forcing nCS2 timiming here for worst case. + */ + MSC1 &= ~0xFFFF; + MSC1 |= 0x8649; + + /* Nothing is connected to Static nCS4 or nCS5. But I'm using + * nCS4 as a paranoia safe guard to force nCS2, nOE; nWE high + * after accessing I/O via (non-VLIO) nCS2. What can I say, I'm + * paranoid and lack decent tools to alleviate my fear. I sure + * do wish I had a logic analyzer. : ( + */ + + MSC2 = 0xfff9fff9; + + return 0; +} + +int +dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + + return (0); +} diff --git a/board/gcplus/lowlevel_init.S b/board/gcplus/lowlevel_init.S new file mode 100644 index 0000000..f292c4d --- /dev/null +++ b/board/gcplus/lowlevel_init.S @@ -0,0 +1,77 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * 2003-2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "config.h" +#include "version.h" + + + .globl lowlevel_init +lowlevel_init: + /* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us. + * However the darn thing leaves the MMU enabled before handing control + * over to us. So we need to disable the MMU and we use lowlevel_init + * to do it. + */ + +@ The following code segment was borrowed with gratitude from: +@ linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S + + @ Data cache might be active. + @ Be sure to flush kernel binary out of the cache, + @ whatever state it is, before it is turned off. + @ This is done by fetching through currently executed + @ memory to be sure we hit the same cache. + bic r2, pc, #0x1f + add r3, r2, #0x4000 @ 16 kb is quite enough... +1: ldr r0, [r2], #32 + teq r2, r3 + bne 1b + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches + + @ disabling MMU and caches + mrc p15, 0, r0, c1, c0, 0 @ read control reg + bic r0, r0, #0x0d @ clear WB, DC, MMU + bic r0, r0, #0x1000 @ clear Icache + mcr p15, 0, r0, c1, c0, 0 + + nop + nop + nop + nop + nop + + b 2f +2: + nop + nop + nop + nop + nop + + + mov pc, lr diff --git a/board/gcplus/u-boot.lds b/board/gcplus/u-boot.lds new file mode 100644 index 0000000..9900a57 --- /dev/null +++ b/board/gcplus/u-boot.lds @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * 2003 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile new file mode 100644 index 0000000..dd7ecf1 --- /dev/null +++ b/board/gen860t/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o beeper.o fpga.o ioport.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/gen860t/README b/board/gen860t/README new file mode 100644 index 0000000..7205afb --- /dev/null +++ b/board/gen860t/README @@ -0,0 +1,146 @@ +This directory contains board specific code for a generic MPC860T based +embedded computer, called 'GEN860T'. The design is generic in the sense that +common, readily available components are used and that the architecture of the +system is relatively straightforward: + + One eight bit wide boot (FLASH) memory + 32 bit main memory using SDRAM + DOC 2000+ + Ethernet PHY + Some I2C peripheral devices: Atmel AT24C256 EEPROM, Maxim DS1337 RTC. + Some other miscellaneous peripherals + +NOTE: There are references to a XIlinx FPGA and Mil-Std 1553 databus in this +port. I guess the computer is not as generic as I first said 8) However, +these extras can be safely ignored. + +Given the GEN860T files, it should be pretty easy to reverse engineer the +hardware configuration, if that's useful to you. Hopefully, this code will +be useful to someone as a basis for a port to a new system or as a head start +on a custom design. If you end up using any of this, I would appreciate +hearing from you, especially if you discover bugs or find ways to improve the +quality of this U-Boot port. + +Here are the salient features of the system: +Clock : 33.3 Mhz oscillator +Processor core frequency : 66.6 Mhz if in 1:2:1 mode; can also run 1:1 +Bus frequency : 33.3 Mhz + +Main memory: + Type : SDRAM + Width : 32 bits + Size : 64 mibibytes + Chip : Two Micron MT48LC16M16A2TG-7E + CS : MPC860T CS1*/UPMA + UPMA CONNECTIONS: + SDRAM A10 : GPLA0* + SDRAM CAS* : GPLA2* + SDRAM WE* : GPLA3* + SDRAM RAS* : GPLA4* + +Boot memory: + Type : FLASH + Width : 8 bits + Size : 16 mibibytes + Chip : One Intel 28F128J3A (StrataFlash) + CS : MPC860T CS0*/GPCM (this is the "boot" chip select) + +EEPROM memory: + Type : Serial I2C EEPROM + Width : 8 bits + Size : 32 kibibytes + Chip : One Atmel AT25C256 + CS : 0x50 (external I2C address pins on device are tied to GND) + +Filesystem memory: + Type : NAND FLASH (Toshiba) + Width : 8 bits (i.e. interface to DOC is 8 bits) + Size : 32 mibibytes + Chip : One DiskOnCHip Millenium Plus (DOC 2000+) + CS : MPC860T CS2*/GPCM + +Network support: + MAC : MPC86OT FEC (Fast Ethernet Controller) + PHY : Intel LXT971A + MII Addr: 0x0 (hardwired on the board) + MII IRQ : + +Console: + RS-232 on SMC1 (Maxim MAX3232 LVCMOS-RS232 level shifter) + +Real Time Clock: + Type : Low power, I2C interface + Chip : Maxim DS1337 + CS : Address 0x68 on I2C bus + + The MPC860T's internal RTC has a defect in Mask rev D that increases + the current drain on the KAPWR line to 10 mA. Since this is an + unreasonable amount of current draw for a RTC, and Motorola does not + plan to fix this in future mask revisions, a serial (I2C) RTC that + works has been included instead. NOTE that the DS1337 can be + configured to output a 32768 Hz clock while the main power is on. + This clock output has been routed to the MPC860T's EXTAL pin to allow + the internal RTC to be used. NOTE also that due to yet another + defect in the rev D mask, the RTC does not operate reliably when the + internal RTC divisor is set to use a 32768 Hz reference. So just use + the I2C RTC. + +Miscellaneous: + Xilinx Virtex FPGA on CS3*/GPCM. + Virtex FPGA slave SelectMap interface on cs4*/UPMB. + Mil-Std 1553 databus interface on CS5*/GPCM. + Audio sounder (beeper) with digital volume control connected to SPKROUT. + +SC variant: + A reduced-feature version of the GEN860T port is also supported: GEN860T_SC. + The 'SC' variant only provides support for the Virtex FPGA, SDRAM main + memory, EEPROM and flash memory. The system clock frequency is reduced + to 24 MHz. + +Issues: + The DOC 2000+ returns 0x40 as its device ID when probed using the method + desxribed in the DOC datasheet. Unfortunately, the U-Boot DOC driver + does not recognize this device. As of this writing, it seems that MTD + does not support the DOC 2000+ either. + +Status: + Everything appears to work except DOC support. As of this writing, + David Woodhouse has stated on the MTD mailing list that he has no + knowledge of the DOC Millineum Plus and therfore there is no support + in MTD for this device. I wish I had known this sooner :( + +The GEN860T board specific files and configuration is based on the work +of others who have contributed to U-Boot. The copyright and license notices +of these authors have been retained wherever their code has been reused. +All new code to support the GEN860T board is: + + (C) Copyright 2001-2003 + Keith Outwater (keith_outwater@mvis.com) + +and the following license applies: + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of +the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place, Suite 330, Boston, +MA 02111-1307 USA + +Thanks to Wolfgang Denk for a great software package and to everyone +who contributed to its development. + +Keith Outwater +Sr. Staff Engineer +Microvision, Inc. + + + +vim: set ts=4 sw=4 tw=78: diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c new file mode 100644 index 0000000..46fe66b --- /dev/null +++ b/board/gen860t/beeper.c @@ -0,0 +1,213 @@ +/* + * (C) Copyright 2002 + * Keith Outwater, keith_outwater@mvis.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * Basic beeper support for the GEN860T board. The GEN860T includes + * an audio sounder driven by a Phillips TDA8551 amplifier. The + * TDA8551 features a digital volume control which uses a "trinary" + * input (high/high-Z/low) to set volume. The 860's SPKROUT pin + * drives the amplifier input. + */ + + +/* + * Initialize beeper-related hardware. Initialize timer 1 for use with + * the beeper. Use 66 Mhz internal clock with prescale of 33 to get + * 1 uS period per count. + * FIXME: we should really compute the prescale based on the reported + * core clock frequency. + */ +void +init_beeper(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1; + immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK) + | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN; + immap->im_cpmtimer.cpmt_tcn1 = 0; + immap->im_cpmtimer.cpmt_ter1 = 0xffff; + immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1; +} + + +/* + * Set beeper frequency. Max allowed frequency is 2.5 KHz. This limit + * is mostly arbitrary, but the beeper isn't really much good beyond this + * frequency. + */ +void +set_beeper_frequency(uint frequency) +{ +#define FREQ_LIMIT 2500 + + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + /* + * Compute timer ticks given desired frequency. The timer is set up + * to count 0.5 uS per tick and it takes two ticks per cycle (Hz). + */ + if (frequency > FREQ_LIMIT) frequency = FREQ_LIMIT; + frequency = 1000000/frequency; + immap->im_cpmtimer.cpmt_trr1 = (ushort)frequency; +} + + +/* + * Turn the beeper on + */ +void +beeper_on(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1; +} + + +/* + * Turn the beeper off + */ +void +beeper_off(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1; +} + + +/* + * Increase or decrease the beeper volume. Volume can be set + * from off to full in 64 steps. To increase volume, the output + * pin is actively driven high, then returned to tristate. + * To decrease volume, output a low on the port pin (no need to + * change pin mode to tristate) then output a high to go back to + * tristate. + */ +void +set_beeper_volume(int steps) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + int i; + + if (steps >= 0) { + for (i = 0; i < (steps >= 64 ? 64 : steps); i++) { + immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19); + udelay(1); + immap->im_cpm.cp_pbodr |= (0x80000000 >> 19); + udelay(1); + } + } + else { + for (i = 0; i > (steps <= -64 ? -64 : steps); i--) { + immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19); + udelay(1); + immap->im_cpm.cp_pbdat |= (0x80000000 >> 19); + udelay(1); + } + } +} + + +/* + * Check the environment to see if the beeper needs beeping. + * Controlled by a sequence of the form: + * freq/delta volume/on time/off time;... where: + * freq = frequency in Hz (0 - 2500) + * delta volume = volume steps up or down (-64 <= vol <= 64) + * on time = time in mS + * off time = time in mS + * + * Return 1 on success, 0 on failure + */ +int +do_beeper(char *sequence) +{ +#define DELIMITER ';' + +int args[4]; +int i; +int val; +char *p = sequence; +char *tp; + + /* + * Parse the control sequence. This is a really simple parser + * without any real error checking. You can probably blow it + * up really easily. + */ + if (*p == '\0' || !isdigit(*p)) { + printf("%s:%d: null or invalid string (%s)\n", + __FILE__, __LINE__, p); + return 0; + } + + i = 0; + while (*p != '\0') { + while (*p != DELIMITER) { + if (i > 3) i = 0; + val = (int) simple_strtol(p, &tp, 0); + if (tp == p) { + printf("%s:%d: no digits or bad format\n", + __FILE__,__LINE__); + return 0; + } + else { + args[i] = val; + } + + i++; + if (*tp == DELIMITER) + p = tp; + else + p = ++tp; + } + p++; + + /* + * Well, we got something that has a chance of being correct + */ +#if 0 + for (i = 0; i < 4; i++) { + printf("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, args[i]); + } + printf("\n"); +#endif + + set_beeper_frequency(args[0]); + set_beeper_volume(args[1]); + beeper_on(); + udelay(1000 * args[2]); + beeper_off(); + udelay(1000 * args[3]); + } + return 1; +} + +/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/beeper.h b/board/gen860t/beeper.h new file mode 100644 index 0000000..535ee6c --- /dev/null +++ b/board/gen860t/beeper.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2002 + * Keith Outwater, keith_outwater@mvis.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +void init_beeper(void); +void set_beeper_frequency(uint frequency); +void beeper_on(void); +void beeper_off(void); +void set_beeper_volume(int steps); +int do_beeper(char *sequence); + +/* vim: set ts=4 tw=78 sw=4: */ diff --git a/board/gen860t/config.mk b/board/gen860t/config.mk new file mode 100644 index 0000000..7acd904 --- /dev/null +++ b/board/gen860t/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# FLASH base address for GEN860T board +# + +TEXT_BASE = 0x40000000 diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c new file mode 100644 index 0000000..ec32d07 --- /dev/null +++ b/board/gen860t/flash.c @@ -0,0 +1,644 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Keith Outwater, keith_outwater@mvsi.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/* + * Use buffered writes to flash by default - they are about 32x faster than + * single byte writes. + */ +#ifndef CFG_GEN860T_FLASH_USE_WRITE_BUFFER +#define CFG_GEN860T_FLASH_USE_WRITE_BUFFER +#endif + +/* + * Max time to wait (in mS) for flash device to allocate a write buffer. + */ +#ifndef CFG_FLASH_ALLOC_BUFFER_TOUT +#define CFG_FLASH_ALLOC_BUFFER_TOUT 100 +#endif + +/* + * These functions support a single Intel StrataFlash device (28F128J3A) + * in byte mode only!. The flash routines are very basic and simple + * since there isn't really any remapping necessary. + */ + +/* + * Intel SCS (Scalable Command Set) command definitions + * (taken from 28F128J3A datasheet) + */ +#define SCS_READ_CMD 0xff +#define SCS_READ_ID_CMD 0x90 +#define SCS_QUERY_CMD 0x98 +#define SCS_READ_STATUS_CMD 0x70 +#define SCS_CLEAR_STATUS_CMD 0x50 +#define SCS_WRITE_BUF_CMD 0xe8 +#define SCS_PROGRAM_CMD 0x40 +#define SCS_BLOCK_ERASE_CMD 0x20 +#define SCS_BLOCK_ERASE_RESUME_CMD 0xd0 +#define SCS_PROGRAM_RESUME_CMD 0xd0 +#define SCS_BLOCK_ERASE_SUSPEND_CMD 0xb0 +#define SCS_SET_BLOCK_LOCK_CMD 0x60 +#define SCS_CLR_BLOCK_LOCK_CMD 0x60 + +/* + * SCS status/extended status register bit definitions + */ +#define SCS_SR7 0x80 +#define SCS_XSR7 0x80 + +/*---------------------------------------------------------------------*/ +#if 0 +#define DEBUG_FLASH +#endif + +#ifdef DEBUG_FLASH +#define PRINTF(fmt,args...) printf(fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_char *addr, flash_info_t *info); +static int write_data8 (flash_info_t *info, ulong dest, uchar data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + * Initialize the flash memory. + */ +unsigned long +flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + for (i= 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* + * The gen860t board only has one FLASH memory device, so the + * FLASH Bank configuration is done statically. + */ + PRINTF("\n## Get flash bank 1 size @ 0x%08x\n", FLASH_BASE0_PRELIM); + size_b0 = flash_get_size((vu_char *)FLASH_BASE0_PRELIM, &flash_info[0]); + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0: " + "ID 0x%lx, Size = 0x%08lx = %ld MB\n", + flash_info[0].flash_id,size_b0, size_b0 << 20); + } + + PRINTF("## Before remap:\n" + " BR0: 0x%08x OR0: 0x%08x\n BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0, + memctl->memc_br1, memctl->memc_or1); + + /* + * Remap FLASH according to real size + */ + memctl->memc_or0 |= (-size_b0 & 0xFFFF8000); + memctl->memc_br0 |= (CFG_FLASH_BASE & BR_BA_MSK); + + PRINTF("## After remap:\n" + " BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); + + /* + * Re-do sizing to get full correct info + */ + size_b0 = flash_get_size ((vu_char *)CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_info[0].size = size_b0; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* + * Monitor protection is ON by default + */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* + * Environment protection ON by default + */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0); + return (size_b0); +} + + +/*----------------------------------------------------------------------- + * Fill in the FLASH offset table + */ +static void +flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 1024 * 128; + } + return; + + default: + printf ("Don't know sector offsets for FLASH" + " type 0x%lx\n", info->flash_id); + return; + } +} + + +/*----------------------------------------------------------------------- + * Display FLASH device info + */ +void +flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("Intel "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A (128Mbit = 128K x 128)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >= (1024 * 1024)) { + i = 20; + } else { + i = 10; + } + printf (" Size: %ld %cB in %d Sectors\n", + info->size >> i, + (i == 20) ? 'M' : 'k', + info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + + +/*----------------------------------------------------------------------- + * Get size and other information for a FLASH device. + * NOTE: The following code cannot be run from FLASH! + */ +static +ulong flash_get_size (vu_char *addr, flash_info_t *info) +{ +#define NO_FLASH 0 + + vu_char value[2]; + + /* + * Try to read the manufacturer ID + */ + addr[0] = SCS_READ_CMD; + addr[0] = SCS_READ_ID_CMD; + value[0] = addr[0]; + value[1] = addr[2]; + addr[0] = SCS_READ_CMD; + + PRINTF("Manuf. ID @ 0x%08lx: 0x%02x\n", (ulong)addr, value[0]); + switch (value[0]) { + case (INTEL_MANUFACT & 0xff): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (NO_FLASH); + } + + /* + * Read the device ID + */ + PRINTF("Device ID @ 0x%08lx: 0x%02x\n", (ulong)(&addr[2]), value[1]); + switch (value[1]) { + case (INTEL_ID_28F128J3A & 0xff): + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 16 * 1024 * 1024; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (NO_FLASH); + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + return (info->size); +} + + +/*----------------------------------------------------------------------- + * Erase the specified sectors in the specified FLASH device + */ +int +flash_erase(flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* + * Start erase on unprotected sectors + */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_char *addr = (uchar *)(info->start[sect]); + vu_char status; + + /* + * Disable interrupts which might cause a timeout + */ + flag = disable_interrupts(); + + *addr = SCS_CLEAR_STATUS_CMD; + *addr = SCS_BLOCK_ERASE_CMD; + *addr = SCS_BLOCK_ERASE_RESUME_CMD; + + /* + * Re-enable interrupts if necessary + */ + if (flag) + enable_interrupts(); + + /* + * Wait at least 80us - let's wait 1 ms + */ + udelay (1000); + + while (((status = *addr) & SCS_SR7) != SCS_SR7) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = SCS_BLOCK_ERASE_SUSPEND_CMD; + *addr = SCS_READ_CMD; + return 1; + } + + /* + * Show that we're waiting + */ + if ((now - last) > 1000) { /* 1 second */ + putc ('.'); + last = now; + } + } + *addr = SCS_READ_CMD; + } + } + printf (" done\n"); + return 0; +} + + +#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER +/* + * Allocate a flash buffer, fill it with data and write it to the flash. + * 0 - OK + * 1 - Timeout on buffer request + * + * NOTE: After the last call to this function, WSM status needs to be checked! + */ +static int +write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p, + uint count) +{ + vu_char *block_addr_p = NULL; + vu_char *start_addr_p = NULL; + ulong blocksize = info_p->size / (ulong)info_p->sector_count; + + int i; + uint time = get_timer(0); + + PRINTF("%s:%d: src: 0x%p dest: 0x%p count: %d\n", + __FUNCTION__, __LINE__, src_p, dest_p, count); + + /* + * What block are we in? We already know that the source address is + * in the flash address range, but we also can't cross a block boundary. + * We assume that the block does not cross a boundary (we'll check before + * calling this function). + */ + for (i = 0; i < info_p->sector_count; ++i) { + if ( ((ulong)dest_p >= info_p->start[i]) && + ((ulong)dest_p < (info_p->start[i] + blocksize)) ) { + PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n", + __FUNCTION__, __LINE__, dest_p, i, info_p->start[i]); + block_addr_p = (vu_char *)info_p->start[i]; + break; + } + } + + /* + * Request a buffer + */ + *block_addr_p = SCS_WRITE_BUF_CMD; + while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) { + if (get_timer(time) > CFG_FLASH_ALLOC_BUFFER_TOUT) { + PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n", + __FUNCTION__, __LINE__, block_addr_p, + CFG_FLASH_ALLOC_BUFFER_TOUT); + return 1; + } + *block_addr_p = SCS_WRITE_BUF_CMD; + } + + /* + * Fill the buffer with data + */ + start_addr_p = dest_p; + *block_addr_p = count - 1; /* flash device wants count - 1 */ + PRINTF("%s:%d: Fill buffer at block addr 0x%p\n", + __FUNCTION__, __LINE__, block_addr_p); + for (i = 0; i < count; i++) { + *start_addr_p++ = *src_p++; + } + + /* + * Flush buffer to flash + */ + *block_addr_p = SCS_PROGRAM_RESUME_CMD; +#if 1 + time = get_timer(0); + while ((*block_addr_p & SCS_SR7) != SCS_SR7) { + if (get_timer(time) > CFG_FLASH_WRITE_TOUT) { + PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n", + __FUNCTION__, __LINE__, block_addr_p, CFG_FLASH_WRITE_TOUT); + return 1; + } + } + +#endif + return 0; +} +#endif + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ +int +write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count) +{ + int rc = 0; +#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER +#define FLASH_WRITE_BUF_SIZE 0x00000020 /* 32 bytes */ + int i; + uint bufs; + ulong buf_count; + vu_char *sp; + vu_char *dp; +#else + ulong wp; +#endif + + PRINTF("\n%s:%d: src: 0x%.8lx dest: 0x%.8lx size: %d (0x%.8lx)\n", + __FUNCTION__, __LINE__, (ulong)src_p, addr, (uint)count, count); + + if (info_p->flash_id == FLASH_UNKNOWN) { + return 4; + } + +#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER + sp = src_p; + dp = (uchar *)addr; + + /* + * For maximum performance, we want to align the start address to + * the beginning of a write buffer boundary (i.e. A4-A0 of the + * start address = 0). See how many bytes are required to get to a + * write-buffer-aligned address. If that number is non-zero, do + * non buffered writes of the non-aligned data. By doing non-buffered + * writes, we avoid the problem of crossing a block (sector) boundary + * with buffered writes. + */ + buf_count = FLASH_WRITE_BUF_SIZE - (addr & (FLASH_WRITE_BUF_SIZE - 1)); + if (buf_count == FLASH_WRITE_BUF_SIZE) { /* already on a boundary */ + buf_count = 0; + } + if (buf_count > count) { /* not a full buffers worth of data to write */ + buf_count = count; + } + count -= buf_count; + + PRINTF("%s:%d: Write buffer alignment count = %ld\n", + __FUNCTION__, __LINE__, buf_count); + while (buf_count-- >= 1) { + if ((rc = write_data8(info_p, (ulong)dp++, *sp++)) != 0) { + return (rc); + } + } + + PRINTF("%s:%d: count = %ld\n", __FUNCTION__, __LINE__, count); + if (count == 0) { /* all done */ + PRINTF("%s:%d: Less than 1 buffer (%d) worth of bytes\n", + __FUNCTION__, __LINE__, FLASH_WRITE_BUF_SIZE); + return (rc); + } + + /* + * Now that we are write buffer aligned, write full or partial buffers. + * The fact that we are write buffer aligned automatically avoids + * crossing a block address during a write buffer operation. + */ + bufs = count / FLASH_WRITE_BUF_SIZE; + PRINTF("%s:%d: %d (0x%x) buffers to write\n", __FUNCTION__, __LINE__, + bufs, bufs); + while (bufs >= 1) { + rc = write_flash_buffer8(info_p, sp, dp, FLASH_WRITE_BUF_SIZE); + if (rc != 0) { + PRINTF("%s:%d: ** Error writing buf %d\n", + __FUNCTION__, __LINE__, bufs); + return (rc); + } + bufs--; + sp += FLASH_WRITE_BUF_SIZE; + dp += FLASH_WRITE_BUF_SIZE; + } + + /* + * Do the leftovers + */ + i = count % FLASH_WRITE_BUF_SIZE; + PRINTF("%s:%d: %d (0x%x) leftover bytes\n", __FUNCTION__, __LINE__, i, i); + if (i > 0) { + rc = write_flash_buffer8(info_p, sp, dp, i); + } + + sp = (vu_char*)info_p->start[0]; + *sp = SCS_READ_CMD; + return (rc); + +#else + wp = addr; + while (count-- >= 1) { + if((rc = write_data8(info_p, wp++, *src_p++)) != 0) + return (rc); + } + return 0; +#endif +} + + +/*----------------------------------------------------------------------- + * Write a byte to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int +write_data8 (flash_info_t *info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *)dest; + vu_char status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = SCS_PROGRAM_CMD; + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (((status = *addr) & SCS_SR7) != SCS_SR7) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = SCS_READ_CMD; + return (1); + } + } + *addr = SCS_READ_CMD; + return (0); +} + +/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c new file mode 100644 index 0000000..37788d5 --- /dev/null +++ b/board/gen860t/fpga.c @@ -0,0 +1,380 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Virtex2 FPGA configuration support for the GEN860T computer + */ + +#include +#include +#include +#include "fpga.h" + +#if (CONFIG_FPGA) + +#if 0 +#define GEN860T_FPGA_DEBUG +#endif + +#ifdef GEN860T_FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* + * Port bit numbers for the Selectmap controls + */ +#define FPGA_INIT_BIT_NUM 22 /* PB22 */ +#define FPGA_RESET_BIT_NUM 11 /* PC11 */ +#define FPGA_DONE_BIT_NUM 16 /* PB16 */ +#define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */ + +/* Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + */ +Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_init_fn, + fpga_err_fn, + fpga_done_fn, + fpga_clk_fn, + fpga_cs_fn, + fpga_wr_fn, + fpga_read_data_fn, + fpga_write_data_fn, + fpga_busy_fn, + fpga_abort_fn, + fpga_post_config_fn +}; + +Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + {Xilinx_Virtex2, + slave_selectmap, + XILINX_XC2V3000_SIZE, + (void *) &fpga_fns, + 0} +}; + +/* + * Display FPGA revision information + */ +void print_fpga_revision (void) +{ + vu_long *rev_p = (vu_long *) 0x60000008; + + printf ("FPGA Revision 0x%.8lx" + " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n", + *rev_p, + ((*rev_p >> 28) & 0xf), + ((*rev_p >> 20) & 0xff), + ((*rev_p >> 12) & 0xff), + ((*rev_p >> 8) & 0xf), (*rev_p & 0xff)); +} + + +/* + * Perform a simple test of the FPGA to processor interface using the FPGA's + * inverting bus test register. The great thing about doing a read/write + * test on a register that inverts it's contents is that you avoid any + * problems with bus charging. + * Return 0 on failure, 1 on success. + */ +int test_fpga_ibtr (void) +{ + vu_long *ibtr_p = (vu_long *) 0x60000010; + vu_long readback; + vu_long compare; + int i; + int j; + int k; + int pass = 1; + + static const ulong bitpattern[] = { + 0xdeadbeef, /* magic ID pattern for debug */ + 0x00000001, /* single bit */ + 0x00000003, /* two adjacent bits */ + 0x00000007, /* three adjacent bits */ + 0x0000000F, /* four adjacent bits */ + 0x00000005, /* two non-adjacent bits */ + 0x00000015, /* three non-adjacent bits */ + 0x00000055, /* four non-adjacent bits */ + 0xaaaaaaaa, /* alternating 1/0 */ + }; + + for (i = 0; i < 1024; i++) { + for (j = 0; j < 31; j++) { + for (k = 0; + k < sizeof (bitpattern) / sizeof (bitpattern[0]); + k++) { + *ibtr_p = compare = (bitpattern[k] << j); + readback = *ibtr_p; + if (readback != ~compare) { + printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback); + pass = 0; + break; + } + } + if (!pass) + break; + } + if (!pass) + break; + } + if (pass) { + printf ("FPGA inverting bus test passed\n"); + print_fpga_revision (); + } else { + printf ("** FPGA inverting bus test failed\n"); + } + return pass; +} + + +/* + * Set the active-low FPGA reset signal. + */ +void fpga_reset (int assert) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__); + if (assert) { + immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM); + PRINTF ("asserted\n"); + } else { + immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM); + PRINTF ("deasserted\n"); + } +} + + +/* + * Initialize the SelectMap interface. We assume that the mode and the + * initial state of all of the port pins have already been set! + */ +void fpga_selectmap_init (void) +{ + PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, + __LINE__); + fpga_pgm_fn (FALSE, FALSE, 0); /* make sure program pin is inactive */ +} + + +/* + * Initialize the fpga. Return 1 on success, 0 on failure. + */ +int gen860t_init_fpga (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + + PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); + fpga_init (gd->reloc_off); + fpga_selectmap_init (); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); + fpga_add (fpga_xilinx, &fpga[i]); + } + return 1; +} + + +/* + * Set the FPGA's active-low SelectMap program line to the specified level + */ +int fpga_pgm_fn (int assert, int flush, int cookie) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); + + if (assert) { + immap->im_ioport.iop_padat &= + ~(0x8000 >> FPGA_PROGRAM_BIT_NUM); + PRINTF ("asserted\n"); + } else { + immap->im_ioport.iop_padat |= + (0x8000 >> FPGA_PROGRAM_BIT_NUM); + PRINTF ("deasserted\n"); + } + return assert; +} + + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int fpga_init_fn (int cookie) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__); + if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) { + PRINTF ("high\n"); + return 0; + } else { + PRINTF ("low\n"); + return 1; + } +} + + +/* + * Test the state of the active-high FPGA DONE pin + */ +int fpga_done_fn (int cookie) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__); + if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) { + PRINTF ("high\n"); + return FPGA_SUCCESS; + } else { + PRINTF ("low\n"); + return FPGA_FAIL; + } +} + + +/* + * Read FPGA SelectMap data. + */ +int fpga_read_data_fn (unsigned char *data, int cookie) +{ + vu_char *p = (vu_char *) SELECTMAP_BASE; + + *data = *p; +#if 0 + PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data); +#endif + return (int) data; +} + + +/* + * Write data to the FPGA SelectMap port + */ +int fpga_write_data_fn (unsigned char data, int flush, int cookie) +{ + vu_char *p = (vu_char *) SELECTMAP_BASE; + +#if 0 + PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data); +#endif + *p = data; + return (int) data; +} + + +/* + * Abort and FPGA operation + */ +int fpga_abort_fn (int cookie) +{ + PRINTF ("%s:%d: FPGA program sequence aborted\n", + __FUNCTION__, __LINE__); + return FPGA_FAIL; +} + + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +int fpga_pre_config_fn (int cookie) +{ + PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); + fpga_reset (TRUE); + return 0; +} + + +/* + * FPGA post configuration function. Blip the FPGA reset line and then see if + * the FPGA appears to be running. + */ +int fpga_post_config_fn (int cookie) +{ + int rc; + + PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); + fpga_reset (TRUE); + udelay (1000); + fpga_reset (FALSE); + udelay (1000); + + /* + * Use the FPGA,s inverting bus test register to do a simple test of the + * processor interface. + */ + rc = test_fpga_ibtr (); + return rc; +} + + +/* + * Clock, chip select and write signal assert functions and error check + * and busy functions. These are only stubs because the GEN860T selectmap + * interface handles sequencing of control signals automatically (it uses + * a memory-mapped interface to the FPGA SelectMap port). The design of + * the interface guarantees that the SelectMap port cannot be overrun so + * no busy check is needed. A configuration error is signalled by INIT + * going low during configuration, so there is no need for a separate error + * function. + */ +int fpga_clk_fn (int assert_clk, int flush, int cookie) +{ + return assert_clk; +} + +int fpga_cs_fn (int assert_cs, int flush, int cookie) +{ + return assert_cs; +} + +int fpga_wr_fn (int assert_write, int flush, int cookie) +{ + return assert_write; +} + +int fpga_err_fn (int cookie) +{ + return 0; +} + +int fpga_busy_fn (int cookie) +{ + return 0; +} +#endif + +/* vim: set ts=4 tw=78 sw=4: */ diff --git a/board/gen860t/fpga.h b/board/gen860t/fpga.h new file mode 100644 index 0000000..01967a4 --- /dev/null +++ b/board/gen860t/fpga.h @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Virtex2 FPGA configuration support for the GEN860T computer + */ + +extern int gen860t_init_fpga(void); +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_init_fn(int cookie); +extern int fpga_err_fn(int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_cs_fn(int assert_cs, int flush, int cookie); +extern int fpga_wr_fn(int assert_write, int flush, int cookie); +extern int fpga_read_data_fn(unsigned char *data, int cookie); +extern int fpga_write_data_fn(unsigned char data, int flush, int cookie); +extern int fpga_busy_fn(int cookie); +extern int fpga_abort_fn(int cookie ); +extern int fpga_pre_config_fn(int cookie ); +extern int fpga_post_config_fn(int cookie ); + +/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c new file mode 100644 index 0000000..b7a1b56 --- /dev/null +++ b/board/gen860t/gen860t.c @@ -0,0 +1,309 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Keith Outwater, keith_outwater@mvis.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "beeper.h" +#include "fpga.h" +#include "ioport.h" + +#ifdef CONFIG_STATUS_LED +#include +#endif + +#if defined(CFG_CMD_MII) && defined(CONFIG_MII) +#include +#endif + +#if 0 +#define GEN860T_DEBUG +#endif + +#ifdef GEN860T_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* + * The following UPM init tables were generated automatically by + * Motorola's MCUINIT program. See the README file for UPM to + * SDRAM pin assignments if you want to type this data into + * MCUINIT in order to reverse engineer the waveforms. + */ + +/* + * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices + * (UPMA) and Virtex FPGA SelectMap interface (UPMB). + * NOTE that unused areas of the table are used to hold NOP, precharge + * and mode register set sequences. + * + */ +#define UPMA_NOP_ADDR 0x5 +#define UPMA_PRECHARGE_ADDR 0x6 +#define UPMA_MRS_ADDR 0x12 + +#define UPM_SINGLE_READ_ADDR 0x00 +#define UPM_BURST_READ_ADDR 0x08 +#define UPM_SINGLE_WRITE_ADDR 0x18 +#define UPM_BURST_WRITE_ADDR 0x20 +#define UPM_REFRESH_ADDR 0x30 + +const uint sdram_upm_table[] = { + /* single read (offset 0x00 in upm ram) */ + 0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05, + 0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff, + /* burst read (offset 0x08 in upm ram) */ + 0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00, + 0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff, + 0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4, + 0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff, + /* single write (offset 0x18 in upm ram) */ + 0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + /* burst write (offset 0x20 in upm ram) */ + 0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00, + 0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + /* refresh (offset 0x30 in upm ram) */ + 0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84, + 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + /* exception (offset 0x3C in upm ram) */ +}; + +const uint selectmap_upm_table[] = { + /* single read (offset 0x00 in upm ram) */ + 0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00, + 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, + /* burst read (offset 0x08 in upm ram) */ + 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + /* single write (offset 0x18 in upm ram) */ + 0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + /* burst write (offset 0x20 in upm ram) */ + 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + /* refresh (offset 0x30 in upm ram) */ + 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + /* exception (offset 0x3C in upm ram) */ + 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff +}; + +/* + * Check board identity. Always successful (gives information only) + */ +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char *s; + char buf[64]; + int i; + + i = getenv_r ("board_id", buf, sizeof (buf)); + s = (i > 0) ? buf : NULL; + + if (s) { + printf ("%s ", s); + } else { + printf (" "); + } + + i = getenv_r ("serial#", buf, sizeof (buf)); + s = (i > 0) ? buf : NULL; + + if (s) { + printf ("S/N %s\n", s); + } else { + printf ("S/N \n"); + } + + printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk)); + printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk)); + return (0); +} + +/* + * Initialize SDRAM + */ +long int initdram (int board_type) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + + upmconfig (UPMA, + (uint *) sdram_upm_table, + sizeof (sdram_upm_table) / sizeof (uint) + ); + + /* + * Setup MAMR register + */ + memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + /* + * Map CS1* to SDRAM bank + */ + memctl->memc_or1 = CFG_OR1; + memctl->memc_br1 = CFG_BR1; + + /* + * Perform SDRAM initialization sequence: + * 1. Apply at least one NOP command + * 2. 100 uS delay (JEDEC standard says 200 uS) + * 3. Issue 4 precharge commands + * 4. Perform two refresh cycles + * 5. Program mode register + * + * Program SDRAM for standard operation, sequential burst, burst length + * of 4, CAS latency of 2. + */ + memctl->memc_mar = 0x00000000; + memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | + MCR_MLCF (0) | UPMA_NOP_ADDR; + udelay (200); + memctl->memc_mar = 0x00000000; + memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | + MCR_MLCF (4) | UPMA_PRECHARGE_ADDR; + + memctl->memc_mar = 0x00000000; + memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | + MCR_MLCF (2) | UPM_REFRESH_ADDR; + + memctl->memc_mar = 0x00000088; + memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | + MCR_MLCF (1) | UPMA_MRS_ADDR; + + memctl->memc_mar = 0x00000000; + memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | + MCR_MLCF (0) | UPMA_NOP_ADDR; + /* + * Enable refresh + */ + memctl->memc_mamr |= MAMR_PTAE; + + return (SDRAM_SIZE); +} + +/* + * Disk On Chip (DOC) Millenium initialization. + * The DOC lives in the CS2* space + */ +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); + +void doc_init (void) +{ + printf ("Probing at 0x%.8x: ", DOC_BASE); + doc_probe (DOC_BASE); +} +#endif + +/* + * Miscellaneous intialization + */ +int misc_init_r (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + + /* + * Set up UPMB to handle the Virtex FPGA SelectMap interface + */ + upmconfig (UPMB, (uint *) selectmap_upm_table, + sizeof (selectmap_upm_table) / sizeof (uint)); + + memctl->memc_mbmr = 0x0; + + config_mpc8xx_ioports (immr); + +#if (CONFIG_COMMANDS & CFG_CMD_MII) + mii_init (); +#endif + +#if (CONFIG_FPGA) + gen860t_init_fpga (); +#endif + return 0; +} + +/* + * Final init hook before entering command loop. + */ +int last_stage_init (void) +{ +#if !defined(CONFIG_SC) + char buf[256]; + int i; + + /* + * Turn the beeper volume all the way down in case this is a warm boot. + */ + set_beeper_volume (-64); + init_beeper (); + + /* + * Read the environment to see what to do with the beeper + */ + i = getenv_r ("beeper", buf, sizeof (buf)); + if (i > 0) { + do_beeper (buf); + } +#endif + return 0; +} + +/* + * Stub to make POST code happy. Can't self-poweroff, so just hang. + */ +void board_poweroff (void) +{ + puts ("### Please power off the board ###\n"); + while (1); +} + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed (void) +{ + return 0; /* No hotkeys supported */ +} +#endif + +/* vim: set ts=4 sw=4 tw=78 : */ diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c new file mode 100644 index 0000000..1fc9545 --- /dev/null +++ b/board/gen860t/ioport.c @@ -0,0 +1,347 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "ioport.h" + +#if 0 +#define IOPORT_DEBUG +#endif + +#ifdef IOPORT_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* + * The ioport configuration table. + */ +const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { + /* + * Port A configuration + * Pin Signal Type Active Initial state + * PA7 fpgaProgramLowOut Out Low High + * PA1 fpgaCoreVoltageFailLow In Low N/A + */ + { /* conf ppar psor pdir podr pdat pint function */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ + /* PA15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PA14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PA13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PA12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PA11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PA10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PA9 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 1*/ + /* PA8 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 1*/ + /* PA7 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaProgramLow */ + /* PA6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PA5 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 0*/ + /* PA4 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 0*/ + /* PA3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PA2 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) + /* PA1 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaCoreVoltageFail*/ +#else + /* PA1 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#endif + /* PA0 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ + }, + + /* + * Port B configuration + * Pin Signal Type Active Initial state + * PB14 docBusyLowIn In Low X + * PB15 gpio1Sig Out High Low + * PB16 fpgaDoneBi In High X + * PB17 swBitOkLowOut Out Low High + * PB19 speakerVolSig Out/Hi-Z High/Low High (Hi-Z) + * PB22 fpgaInitLowBi In Low X + * PB23 batteryOkSig In High X + * PB31 pulseCatcherClr Out High 0 + */ + { /* conf ppar psor pdir podr pdat pint function */ +#if !defined(CONFIG_SC) + /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#else + /* PB31 */ { 1, 0, 0, 1, 0, 0, 0 }, /* pulseCatcherClr */ +#endif + /* PB30 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PB29 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PB28 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PB27 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PB26 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PB25 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PB24 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) + /* PB23 */ { 1, 0, 0, 0, 0, 0, 0 }, /* batteryOk */ +#else + /* PB23 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#endif + /* PB22 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaInitLowBi */ + /* PB21 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PB20 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) + /* PB19 */ { 1, 0, 0, 1, 1, 1, 0 }, /* speakerVol */ +#else + /* PB19 */ { 0, 0, 0, 1, 1, 1, 0 }, /* */ +#endif + /* PB18 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PB17 */ { 1, 0, 0, 1, 0, 1, 0 }, /* swBitOkLow */ + /* PB16 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaDone */ + /* PB15 */ { 1, 0, 0, 1, 0, 0, 0 }, /* gpio1 */ +#if !defined(CONFIG_SC) + /* PB14 */ { 1, 0, 0, 0, 0, 0, 0 } /* docBusyLow */ +#else + /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ +#endif + }, + + /* + * Port C configuration + * Pin Signal Type Active Initial state + * PC4 i2cBus1EnSig Out High High + * PC5 i2cBus2EnSig Out High High + * PC6 gpio0Sig Out High Low + * PC8 i2cBus3EnSig Out High High + * PC10 i2cBus4EnSig Out High High + * PC11 fpgaResetLowOut Out Low High + * PC12 systemBitOkIn In High X + * PC15 selfDreqLow In Low X + */ + { /* conf ppar psor pdir podr pdat pint function */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PC15 */ { 1, 0, 0, 0, 0, 0, 0 }, /* selfDreqLowIn */ + /* PC14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PC13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) + /* PC12 */ { 1, 0, 0, 0, 0, 0, 0 }, /* systemBitOkIn */ +#else + /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#endif + /* PC11 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaResetLowOut */ +#if !defined(CONFIG_SC) + /* PC10 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus4EnSig */ +#else + /* PC10 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ +#endif + /* PC9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ +#if !defined(CONFIG_SC) + /* PC8 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus3EnSig */ +#else + /* PC8 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ +#endif + /* PC7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PC6 */ { 1, 0, 0, 1, 0, 1, 0 }, /* gpio0 */ +#if !defined(CONFIG_SC) + /* PC5 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus2EnSig */ + /* PC4 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus1EnSig */ +#else + /* PC5 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ + /* PC4 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ +#endif + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ + }, + + /* + * Port D configuration + */ + { /* conf ppar psor pdir podr pdat pint function */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD8 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD5 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD4 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PD3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ + } +}; + +/* + * Configure the MPC8XX I/O ports per the ioport configuration table + * (taken from ./cpu/mpc8260/cpu_init.c) + */ +void config_mpc8xx_ioports (volatile immap_t * immr) +{ + int portnum; + + for (portnum = 0; portnum < NUM_PORTS; portnum++) { + uint pmsk = 0, ppar = 0, psor = 0, pdir = 0; + uint podr = 0, pdat = 0, pint = 0; + uint msk = 1; + mpc8xx_iop_conf_t *iopc = + (mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0]; + mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS; + + /* + * For all ports except port B, ignore the two don't care entries + * in the configuration tables. + */ + if (portnum != 1) { + iopc = (mpc8xx_iop_conf_t *) & + iop_conf_tab[portnum][2]; + } + + /* + * NOTE: index 0 refers to pin 17, index 17 refers to pin 0 + */ + while (iopc < eiopc) { + if (iopc->conf) { + pmsk |= msk; + if (iopc->ppar) + ppar |= msk; + if (iopc->psor) + psor |= msk; + if (iopc->pdir) + pdir |= msk; + if (iopc->podr) + podr |= msk; + if (iopc->pdat) + pdat |= msk; + if (iopc->pint) + pint |= msk; + } + msk <<= 1; + iopc++; + } + + PRINTF ("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__, + portnum); +#ifdef IOPORT_DEBUG + switch (portnum) { + case 0: + printf ("(A)\n"); + break; + case 1: + printf ("(B)\n"); + break; + case 2: + printf ("(C)\n"); + break; + case 3: + printf ("(D)\n"); + break; + default: + printf ("(?)\n"); + break; + } +#endif + PRINTF (" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n" + " pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n", + ppar, pdir, podr, pdat, psor, pint, pmsk); + + /* + * Have to handle the ioports on a port-by-port basis since there + * are three different flavors. + */ + if (pmsk != 0) { + uint tpmsk = ~pmsk; + + if (0 == portnum) { /* port A */ + immr->im_ioport.iop_papar &= tpmsk; + immr->im_ioport.iop_padat = + (immr->im_ioport. + iop_padat & tpmsk) | pdat; + immr->im_ioport.iop_padir = + (immr->im_ioport. + iop_padir & tpmsk) | pdir; + immr->im_ioport.iop_paodr = + (immr->im_ioport. + iop_paodr & tpmsk) | podr; + immr->im_ioport.iop_papar |= ppar; + } else if (1 == portnum) { /* port B */ + immr->im_cpm.cp_pbpar &= tpmsk; + immr->im_cpm.cp_pbdat = + (immr->im_cpm. + cp_pbdat & tpmsk) | pdat; + immr->im_cpm.cp_pbdir = + (immr->im_cpm. + cp_pbdir & tpmsk) | pdir; + immr->im_cpm.cp_pbodr = + (immr->im_cpm. + cp_pbodr & tpmsk) | podr; + immr->im_cpm.cp_pbpar |= ppar; + } else if (2 == portnum) { /* port C */ + immr->im_ioport.iop_pcpar &= tpmsk; + immr->im_ioport.iop_pcdat = + (immr->im_ioport. + iop_pcdat & tpmsk) | pdat; + immr->im_ioport.iop_pcdir = + (immr->im_ioport. + iop_pcdir & tpmsk) | pdir; + immr->im_ioport.iop_pcint = + (immr->im_ioport. + iop_pcint & tpmsk) | pint; + immr->im_ioport.iop_pcso = + (immr->im_ioport. + iop_pcso & tpmsk) | psor; + immr->im_ioport.iop_pcpar |= ppar; + } else if (3 == portnum) { /* port D */ + immr->im_ioport.iop_pdpar &= tpmsk; + immr->im_ioport.iop_pddat = + (immr->im_ioport. + iop_pddat & tpmsk) | pdat; + immr->im_ioport.iop_pddir = + (immr->im_ioport. + iop_pddir & tpmsk) | pdir; + immr->im_ioport.iop_pdpar |= ppar; + } + } + } + + PRINTF ("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x" + " paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__, + immr->im_ioport.iop_papar, immr->im_ioport.iop_padir, + immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat); + PRINTF ("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x" + " pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__, + immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir, + immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat); + PRINTF ("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x" + " pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ", + __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar, + immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat, + immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint); + PRINTF ("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x" + " pddat=0x%.4x\n", __FUNCTION__, __LINE__, + immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir, + immr->im_ioport.iop_pddat); +} diff --git a/board/gen860t/ioport.h b/board/gen860t/ioport.h new file mode 100644 index 0000000..34a2d7b --- /dev/null +++ b/board/gen860t/ioport.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Keith Outwater, keith_outwater@mvis.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define NUM_PORTS 4 +#define PORT_BITS 18 + +/* + * This structure provides configuration information for one port pin. + * We include all fields needed to initialize any of the ioports. + */ +typedef struct { + unsigned char conf:1; /* If 1, configure this port */ + unsigned char ppar:1; /* Port Pin Assignment Register */ + unsigned char psor:1; /* Port Special Options Register */ + unsigned char pdir:1; /* Port Data Direction Register */ + unsigned char podr:1; /* Port Open Drain Register */ + unsigned char pdat:1; /* Port Data Register */ + unsigned char pint:1; /* Port Interrupt Register */ +} mpc8xx_iop_conf_t; + +extern void config_mpc8xx_ioports(volatile immap_t *immr); + +/* vim: set ts=4 tw=78 sw=4: */ diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds new file mode 100644 index 0000000..7926a2e --- /dev/null +++ b/board/gen860t/u-boot-flashenv.lds @@ -0,0 +1,139 @@ +/* + * Linker command file for the GEN860T board when the environment is + * stored in flash memory. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* + * Read-only sections, merged into text segment: + */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* + * Read-write section, merged into data segment: + */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data: + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); + + .ppcenv: + { + . = env_offset; + common/environment.o + } +} diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds new file mode 100644 index 0000000..1df4817 --- /dev/null +++ b/board/gen860t/u-boot.lds @@ -0,0 +1,133 @@ +/* + * Linker command file for the GEN860T board. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* + * Read-only sections, merged into text segment: + */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* + * Read-write section, merged into data segment: + */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/genietv/Makefile b/board/genietv/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/genietv/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/genietv/config.mk b/board/genietv/config.mk new file mode 100644 index 0000000..69ab21f --- /dev/null +++ b/board/genietv/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x00000000 +OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data diff --git a/board/genietv/flash.c b/board/genietv/flash.c new file mode 100644 index 0000000..1c1728b --- /dev/null +++ b/board/genietv/flash.c @@ -0,0 +1,469 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + /* Detect size */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + /* Setup offsets */ + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + size_b1 = 0 ; + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + * Fix this to support variable sector sizes +*/ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + /* set sector offsets for bottom boot block type */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) + { + puts ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) + { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) + { + case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >> 20) { + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + } else { + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, + info->sector_count); + } + + puts (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) + { + if ((i % 5) == 0) + { + puts ("\n "); + } + + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + putc ('\n'); + return; +} +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + volatile unsigned char *caddr; + char value; + + caddr = (volatile unsigned char *)addr ; + + /* Write auto select command: read Manufacturer ID */ + +#if 0 + printf("Base address is: %08x\n", caddr); +#endif + + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0x90; + + value = caddr[0]; + +#if 0 + printf("Manufact ID: %02x\n", value); +#endif + switch (value) + { + case 0x1: /* AMD_MANUFACT */ + info->flash_id = FLASH_MAN_AMD; + break; + + case 0x4: /* FUJ_MANUFACT */ + info->flash_id = FLASH_MAN_FUJ; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + value = caddr[1]; /* device ID */ +#if 0 + printf("Device ID: %02x\n", value); +#endif + switch (value) + { + case AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512Kb */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + flash_get_offsets ((ulong)addr, &flash_info[0]); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) + { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) + { + caddr = (volatile unsigned char *)info->start[0]; + *caddr = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (volatile unsigned char *)(info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile unsigned char *)(info->start[l_sect]); + + while ((addr[0] & 0xFF) != 0xFF) + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned char *)info->start[0]; + + addr[0] = 0xF0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]), + *cdest,*cdata; + ulong start; + int flag, count = 4 ; + + cdest = (volatile unsigned char *)dest ; + cdata = (volatile unsigned char *)&data ; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + while(count--) + { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *cdest = *cdata; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*cdest ^ *cdata) & 0x80) + { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + cdata++ ; + cdest++ ; + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c new file mode 100644 index 0000000..5f8c899 --- /dev/null +++ b/board/genietv/genietv.c @@ -0,0 +1,360 @@ +/* + * genietv/genietv.c + * + * The GENIETV is using the following physical memorymap (copied from + * the FADS configuration): + * + * ff020000 -> ff02ffff : pcmcia + * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM + * ff000000 -> ff00ffff : IMAP internal in the cpu + * 02800000 -> 0287ffff : flash connected to CS0 + * 00000000 -> nnnnnnnn : sdram setup by U-Boot + * + * CS pins are connected as follows: + * + * CS0 -512Kb boot flash + * CS1 - SDRAM #1 + * CS2 - SDRAM #2 + * CS3 - Flash #1 + * CS4 - Flash #2 + * CS5 - LON (if present) + * CS6 - PCMCIA #1 + * CS7 - PCMCIA #2 + * + * Ports are configured as follows: + * + * PA7 - SDRAM banks enable + */ + +#include +#include + +#define CFG_PA7 0x0100 + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMB RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00, + 0x1FFDDC47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMB RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */ + /* + * Burst Read. (Offset 8 in UPMB RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMB RAM) + */ + 0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMB RAM) + */ + 0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMB RAM) + */ + 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMB RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity + */ + +int checkboard (void) +{ + puts ("Board: GenieTV\n"); + return 0; +} + +#if 0 +static void PrintState (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &im->im_memctl; + + printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, + memctl->memc_or0); + printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1, + memctl->memc_or1); + printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2, + memctl->memc_or2); +} +#endif + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &im->im_memctl; + long int size_b0, size_b1, size8; + + /* Enable SDRAM */ + + /* Configuring PA7 for general purpouse output pin */ + im->im_ioport.iop_papar &= ~CFG_PA7; /* 0 = general purpouse */ + im->im_ioport.iop_padir |= CFG_PA7; /* 1 = output */ + + /* Enable SDRAM - PA7 = 1 */ + im->im_ioport.iop_padat |= CFG_PA7; /* value of PA7 */ + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + + memctl->memc_mbmr = CFG_MBMR_8COL; + + upmconfig (UPMB, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + + memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM; + memctl->memc_br1 = + ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); + + memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); + + /* perform SDRAM initialization sequence */ + memctl->memc_mar = 0x00000088; + + memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */ + + memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */ + + /* Execute refresh 8 times */ + memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X; + + memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */ + + memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */ + + /* Execute refresh 4 times */ + memctl->memc_mbmr = CFG_MBMR_8COL; + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + +#if 0 + PrintState (); +#endif +/* printf ("\nChecking bank1..."); */ + size8 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM, + SDRAM_MAX_SIZE); + + size_b0 = size8; + +/* printf ("\nChecking bank2..."); */ + size_b1 = + dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + /* + * Final mapping: map bigger bank first + */ + + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; + + if (size_b1 > 0) { + /* + * Position Bank 1 immediately above Bank 0 + */ + memctl->memc_or2 = + ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + + (size_b0 & BR_BA_MSK); + } else { + /* + * No bank 1 + * + * invalidate bank + */ + memctl->memc_br2 = 0; + /* adjust refresh rate depending on SDRAM type, one bank */ + memctl->memc_mptpr = CFG_MPTPR_1BK_4K; + } + + /* If no memory detected, disable SDRAM */ + if ((size_b0 + size_b1) == 0) { + printf ("disabling SDRAM!\n"); + /* Disable SDRAM - PA7 = 1 */ + im->im_ioport.iop_padat &= ~CFG_PA7; /* value of PA7 */ + } +/* else */ +/* printf("done! (%08lx)\n", size_b0 + size_b1); */ + +#if 0 + PrintState (); +#endif + return (size_b0 + size_b1); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mbmr_value, long int *base, + long int maxsize) +{ + long size; + + /*memctl->memc_mbmr = mbmr_value; */ + + size = get_ram_size (base, maxsize); + + if (size) { +/* printf("(%08lx)", size); */ + } else { + printf ("(0)"); + } + + return (size); +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) + +#ifdef CFG_PCMCIA_MEM_ADDR +volatile unsigned char *pcmcia_mem = (unsigned char *) CFG_PCMCIA_MEM_ADDR; +#endif + +int pcmcia_init (void) +{ + volatile pcmconf8xx_t *pcmp; + uint v, slota, slotb; + + /* + ** Enable the PCMCIA for a Flash card. + */ + pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); + +#if 0 + pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR; + pcmp->pcmc_por0 = 0xc00ff05d; +#endif + + /* Set all slots to zero by default. */ + pcmp->pcmc_pgcra = 0; + pcmp->pcmc_pgcrb = 0; +#ifdef PCMCIA_SLOT_A + pcmp->pcmc_pgcra = 0x40; +#endif +#ifdef PCMCIA_SLOT_B + pcmp->pcmc_pgcrb = 0x40; +#endif + + /* Check if any PCMCIA card is luged in. */ + slota = (pcmp->pcmc_pipr & 0x18000000) == 0; + slotb = (pcmp->pcmc_pipr & 0x00001800) == 0; + + if (!(slota || slotb)) { + printf ("No card present\n"); +#ifdef PCMCIA_SLOT_A + pcmp->pcmc_pgcra = 0; +#endif +#ifdef PCMCIA_SLOT_B + pcmp->pcmc_pgcrb = 0; +#endif + return -1; + } else + printf ("Unknown card ("); + + v = 0; + + switch ((pcmp->pcmc_pipr >> 14) & 3) { + case 0x00: + printf ("5V"); + v = 5; + break; + case 0x01: + printf ("5V and 3V"); + v = 3; + break; + case 0x03: + printf ("5V, 3V and x.xV"); + v = 3; + break; + } + + switch (v) { + case 3: + printf ("; using 3V"); + /* Enable 3 volt Vcc. */ + + break; + + default: + printf ("; unknown voltage"); + return -1; + } + printf (")\n"); + /* disable pcmcia reset after a while */ + + udelay (20); + + pcmp->pcmc_pgcrb = 0; + + /* If you using a real hd you should give a short + * spin-up time. */ +#ifdef CONFIG_DISK_SPINUP_TIME + udelay (CONFIG_DISK_SPINUP_TIME); +#endif + + return 0; +} +#endif /* CFG_CMD_PCMCIA */ diff --git a/board/genietv/genietv.h b/board/genietv/genietv.h new file mode 100644 index 0000000..7c95b56 --- /dev/null +++ b/board/genietv/genietv.h @@ -0,0 +1,25 @@ +/* + * The GENIETV is using the following physical memorymap (copied from + * the FADS configuration): + * + * ff020000 -> ff02ffff : pcmcia + * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM + * ff000000 -> ff00ffff : IMAP internal in the cpu + * 02800000 -> 0287ffff : flash connected to CS0 + * 00000000 -> nnnnnnnn : sdram setup by U-Boot + * + * CS pins are connected as follows: + * + * CS0 -512Kb boot flash + * CS1 - SDRAM #1 + * CS2 - SDRAM #2 + * CS3 - Flash #1 + * CS4 - Flash #2 + * CS5 - LON (if present) + * CS6 - PCMCIA #1 + * CS7 - PCMCIA #2 + * + * Ports are configured as follows: + * + * PA7 - SDRAM banks enable + */ diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds new file mode 100644 index 0000000..f48b9ad --- /dev/null +++ b/board/genietv/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + . = ALIGN(256 * 1024); + .ppcenv : + { + common/environment.o (.ppcenv) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug new file mode 100644 index 0000000..e843df6 --- /dev/null +++ b/board/genietv/u-boot.lds.debug @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + . = ALIGN(256 * 1024); + .ppcenv : + { + common/environment.o (.ppcenv) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/gth/Makefile b/board/gth/Makefile new file mode 100644 index 0000000..e14c12e --- /dev/null +++ b/board/gth/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ee_access.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/gth/README b/board/gth/README new file mode 100644 index 0000000..241c70b --- /dev/null +++ b/board/gth/README @@ -0,0 +1,18 @@ +Written by Thomas.Lange@corelatus.com 010805 + +To make a system for gth that actually works ;-) +the variable TBASE needs to be set to 0,1 or 2 +depending on location where image is supposed to +be started from. +E.g. make TBASE=1 + +0: Start from RAM, base 0 + +1: Start from flash_base + 0x10070 + +2: Start from flash_base + 0x30070 + +When using 1 or 2, the image is supposed to be launched +from miniboot that boots the first U-Boot image found in +flash. +For miniboot code, description, see www.opensource.se diff --git a/board/gth/config.mk b/board/gth/config.mk new file mode 100644 index 0000000..3c80156 --- /dev/null +++ b/board/gth/config.mk @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +ifeq ($(TBASE),0) +TEXT_BASE = 0 +else +ifeq ($(TBASE),1) +TEXT_BASE = 0x80010070 +else +ifeq ($(TBASE),2) +TEXT_BASE = 0x80030070 +else +## Only to make ordinary make work +TEXT_BASE = 0x90000000 +endif +endif +endif + +OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data diff --git a/board/gth/ee_access.c b/board/gth/ee_access.c new file mode 100644 index 0000000..716c90e --- /dev/null +++ b/board/gth/ee_access.c @@ -0,0 +1,335 @@ +/* Module for handling DALLAS DS2438, smart battery monitor + Chip can store up to 40 bytes of user data in EEPROM, + perform temp, voltage and current measurements. + Chip also contains a unique serial number. + + Always read/write LSb first + + For documentaion, see data sheet for DS2438, 2438.pdf + + By Thomas.Lange@corelatus.com 001025 */ + +#include +#include +#include + +#include <../board/gth/ee_dev.h> + +/* We dont have kernel functions */ +#define printk printf +#define KERN_DEBUG +#define KERN_ERR +#define EIO 1 + +static int Debug = 0; + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +/* + * lookup table ripped from DS app note 17, understanding and using + * cyclic redundancy checks... + */ + +static u8 crc_lookup[256] = { + 0, 94, 188, 226, 97, 63, 221, 131, + 194, 156, 126, 32, 163, 253, 31, 65, + 157, 195, 33, 127, 252, 162, 64, 30, + 95, 1, 227, 189, 62, 96, 130, 220, + 35, 125, 159, 193, 66, 28, 254, 160, + 225, 191, 93, 3, 128, 222, 60, 98, + 190, 224, 2, 92, 223, 129, 99, 61, + 124, 34, 192, 158, 29, 67, 161, 255, + 70, 24, 250, 164, 39, 121, 155, 197, + 132, 218, 56, 102, 229, 187, 89, 7, + 219, 133, 103, 57, 186, 228, 6, 88, + 25, 71, 165, 251, 120, 38, 196, 154, + 101, 59, 217, 135, 4, 90, 184, 230, + 167, 249, 27, 69, 198, 152, 122, 36, + 248, 166, 68, 26, 153, 199, 37, 123, + 58, 100, 134, 216, 91, 5, 231, 185, + 140, 210, 48, 110, 237, 179, 81, 15, + 78, 16, 242, 172, 47, 113, 147, 205, + 17, 79, 173, 243, 112, 46, 204, 146, + 211, 141, 111, 49, 178, 236, 14, 80, + 175, 241, 19, 77, 206, 144, 114, 44, + 109, 51, 209, 143, 12, 82, 176, 238, + 50, 108, 142, 208, 83, 13, 239, 177, + 240, 174, 76, 18, 145, 207, 45, 115, + 202, 148, 118, 40, 171, 245, 23, 73, + 8, 86, 180, 234, 105, 55, 213, 139, + 87, 9, 235, 181, 54, 104, 138, 212, + 149, 203, 41, 119, 244, 170, 72, 22, + 233, 183, 85, 11, 136, 214, 52, 106, + 43, 117, 151, 201, 74, 20, 246, 168, + 116, 42, 200, 150, 21, 75, 169, 247, + 182, 232, 10, 84, 215, 137, 107, 53 +}; + +static u8 make_new_crc( u8 Old_crc, u8 New_value ){ + /* Compute a new checksum with new byte, using previous checksum as input + See DS app note 17, understanding and using cyclic redundancy checks... + Also see DS2438, page 11 */ + return( crc_lookup[Old_crc ^ New_value ]); +} + +int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){ + /* Check if the checksum for this buffer is correct */ + u8 Curr_crc=0; + int i; + u8 *Curr_byte = Buffer; + + for(i=0;i>=1; + } +} + +int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){ + /* Execute this command string, including + giving reset and setting to idle after command + if Rx_len is set, we read out data from EEPROM */ + int i; + + E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len ); + + if(do_reset()){ + /* Failed! */ + return(-EIO); + } + + if(Send_skip) + /* Always send SKIP_ROM first to tell chip we are sending a command, + except when we read out rom data for chip */ + write_byte(SKIP_ROM); + + /* Always have Tx data */ + for(i=0;iim_ioport.iop_padat &= ~PA_FRONT_LED; + else + immap->im_ioport.iop_padat |= PA_FRONT_LED; + udelay(1); + } + + /* Set port to open drain to be able to read data from + port without setting it to input */ + PORT_B_PAR &= ~PB_EEPROM; + PORT_B_ODR |= PB_EEPROM; + SET_PORT_B_OUTPUT(PB_EEPROM); + + /* Set idle mode */ + set_idle(); + + /* Copy all User EEPROM data to scratchpad */ + for(i=0;iim_cpm.cp_pbpar +#define PORT_B_ODR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbodr +#define PORT_B_DIR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdir +#define PORT_B_DAT ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat + +#define SET_PORT_B_INPUT(Mask) PORT_B_DIR &= ~(Mask) +#define SET_PORT_B_OUTPUT(Mask) PORT_B_DIR |= Mask + +#define WRITE_PORT_B(Mask,Value) { \ + if (Value) PORT_B_DAT |= Mask; \ + else PORT_B_DAT &= ~(Mask); \ + } +#define WRITE_PORT(Value) WRITE_PORT_B(PB_EEPROM,Value) + +#define READ_PORT (PORT_B_DAT&PB_EEPROM) + +/* 64 bytes chip */ +#define EE_CHIP_SIZE 64 + +/* We use this resistor for measuring the current drain on 3.3V */ +#define CURRENT_RESISTOR 0.022 + +/* microsecs + Pull line down at least this long for reset pulse */ +#define RESET_LOW_TIME 490 + +/* Read presence pulse after we release reset pulse */ +#define PRESENCE_TIMEOUT 100 +#define PRESENCE_LOW_TIME 200 + +#define WRITE_0_LOW 80 +#define WRITE_1_LOW 2 +#define TOTAL_WRITE_LOW 80 + +#define READ_LOW 2 +#define READ_TIMEOUT 10 +#define TOTAL_READ_LOW 80 + +/*** Rom function commands ***/ +#define READ_ROM 0x33 +#define MATCH_ROM 0x55 +#define SKIP_ROM 0xCC +#define SEARCH_ROM 0xF0 + + +/*** Memory_command_function ***/ +#define WRITE_SCRATCHPAD 0x4E +#define READ_SCRATCHPAD 0xBE +#define COPY_SCRATCHPAD 0x48 +#define RECALL_MEMORY 0xB8 +#define CONVERT_TEMP 0x44 +#define CONVERT_VOLTAGE 0xB4 + +/* Chip is divided in 8 pages, 8 bytes each */ + +#define EE_PAGE_SIZE 8 + +/* All chip data we want are in page 0 */ + +/* Bytes in page 0 */ +#define EE_P0_STATUS 0 +#define EE_P0_TEMP_LSB 1 +#define EE_P0_TEMP_MSB 2 +#define EE_P0_VOLT_LSB 3 +#define EE_P0_VOLT_MSB 4 +#define EE_P0_CURRENT_LSB 5 +#define EE_P0_CURRENT_MSB 6 + + +/* 40 byte user data is located at page 3-7 */ +#define EE_USER_PAGE_0 3 +#define USER_PAGES 5 + +#endif /* INCeedevh */ diff --git a/board/gth/flash.c b/board/gth/flash.c new file mode 100644 index 0000000..41a5c50 --- /dev/null +++ b/board/gth/flash.c @@ -0,0 +1,649 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /*printf("faking");*/ + + return(0x1fffff); + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) + { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) + { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0<<20); + } + +#if 0 + if (FLASH_BASE1_PRELIM != 0x0) { + size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); + + if (size_b1 > size_b0) { + printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20,size_b0, size_b0<<20); + + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + } else { +#endif + size_b1 = 0; + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR0_PRELIM; + memctl->memc_br0 = CFG_BR0_PRELIM; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + if (size_b1) + { + /* memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; */ + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + } + else + { +/* memctl->memc_or1 = CFG_OR1_PRELIM; + FIXME memctl->memc_br1 = CFG_BR1_PRELIM; */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + + +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start adress table */ + if (info->flash_id & FLASH_BTYPE) + { + /* set sector offsets for bottom boot block type */ + for (i = 0; i < info->sector_count; i++) + { + info->start[i] = base + (i * 0x00040000); + } + } + else + { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + for (; i >= 0; i--) + { + info->start[i] = base + i * 0x00040000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + +#if 0 + case FLASH_AM040B: + printf ("AM29F040B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM040T: + printf ("AM29F040T (4 Mbit, top boot sect)\n"); + break; +#endif + case FLASH_AM400B: + printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) + { + if ((i % 5) == 0) + { + printf ("\n "); + } + + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; +#if 0 + ulong base = (ulong)addr; +#endif + ulong value; + + /* Write auto select command: read Manufacturer ID */ +#if 0 + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; +#else + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x90909090; +#endif + + value = addr[0]; + + switch (value) + { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + value = addr[1]; /* device ID */ + + switch (value) + { +#if 0 + case AMD_ID_F040B: + info->flash_id += FLASH_AM040B; + info->sector_count = 8; + info->size = 0x00200000; + break; /* => 2 MB */ +#endif + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + +#if 0 + /* set up sector start adress table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +#else + flash_get_offsets ((ulong)addr, &flash_info[0]); +#endif + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) + { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) + { + addr = (volatile unsigned long *)info->start[0]; +#if 0 + *addr = 0x00F000F0; /* reset bank */ +#else + *addr = 0xF0F0F0F0; /* reset bank */ +#endif + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + +#if 0 + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; +#else + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x80808080; + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; +#endif + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); +#if 0 + addr[0] = 0x00300030; +#else + addr[0] = 0x30303030; +#endif + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); +#if 0 + while ((addr[0] & 0x00800080) != 0x00800080) +#else + while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) +#endif + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; +#if 0 + addr[0] = 0x00F000F0; /* reset bank */ +#else + addr[0] = 0xF0F0F0F0; /* reset bank */ +#endif + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + +#if 0 + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; +#else + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0xA0A0A0A0; +#endif + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); +#if 0 + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) +#else + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) +#endif + { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/gth/gth.c b/board/gth/gth.c new file mode 100644 index 0000000..b1fcbf5 --- /dev/null +++ b/board/gth/gth.c @@ -0,0 +1,595 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Adapted from FADS and other board config files to GTH by thomas@corelatus.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "ee_access.h" +#include "ee_dev.h" + +#ifdef CONFIG_BDM +#undef printf +#define printf(a,...) /* nothing */ +#endif + + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + int Id = 0; + int Rev = 0; + u32 Pbdat; + + puts ("Board: "); + + /* Turn on leds and setup for reading rev and id */ + +#define PB_OUTS (PB_BLUE_LED|PB_ID_GND) +#define PB_INS (PB_ID_0|PB_ID_1|PB_ID_2|PB_ID_3|PB_REV_1|PB_REV_0) + + immap->im_cpm.cp_pbpar &= ~(PB_OUTS | PB_INS); + + immap->im_cpm.cp_pbdir &= ~PB_INS; + + immap->im_cpm.cp_pbdir |= PB_OUTS; + immap->im_cpm.cp_pbodr |= PB_OUTS; + immap->im_cpm.cp_pbdat &= ~PB_OUTS; + + /* Hold 100 Mbit in reset until fpga is loaded */ + immap->im_ioport.iop_pcpar &= ~PC_ENET100_RESET; + immap->im_ioport.iop_pcdir |= PC_ENET100_RESET; + immap->im_ioport.iop_pcso &= ~PC_ENET100_RESET; + immap->im_ioport.iop_pcdat &= ~PC_ENET100_RESET; + + /* Turn on front led to show that we are alive */ + immap->im_ioport.iop_papar &= ~PA_FRONT_LED; + immap->im_ioport.iop_padir |= PA_FRONT_LED; + immap->im_ioport.iop_paodr |= PA_FRONT_LED; + immap->im_ioport.iop_padat &= ~PA_FRONT_LED; + + Pbdat = immap->im_cpm.cp_pbdat; + + if (!(Pbdat & PB_ID_0)) + Id += 1; + if (!(Pbdat & PB_ID_1)) + Id += 2; + if (!(Pbdat & PB_ID_2)) + Id += 4; + if (!(Pbdat & PB_ID_3)) + Id += 8; + + if (Pbdat & PB_REV_0) + Rev += 1; + if (Pbdat & PB_REV_1) + Rev += 2; + + /* Turn ID off since we dont need it anymore */ + immap->im_cpm.cp_pbdat |= PB_ID_GND; + + printf ("GTH board, rev %d, id=0x%01x\n", Rev, Id); + return 0; +} + +#define _NOT_USED_ 0xffffffff +const uint sdram_table[] = { + /* Single read, offset 0 */ + 0x0f3dfc04, 0x0eefbc04, 0x01bf7c04, 0x0feafc00, + 0x1fb5fc45, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* Burst read, Offset 0x8, 4 reads */ + 0x0f3dfc04, 0x0eefbc04, 0x00bf7c04, 0x00ffec00, + 0x00fffc00, 0x01eafc00, 0x1fb5fc00, 0xfffffc45, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* Not used part of burst read is used for MRS, Offset 0x14 */ + 0xefeabc34, 0x1fb57c34, 0xfffffc05, _NOT_USED_, + /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */ + + /* Single write, Offset 0x18 */ + 0x0f3dfc04, 0x0eebbc00, 0x01a27c04, 0x1fb5fc45, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* Burst write, Offset 0x20. 4 writes */ + 0x0f3dfc04, 0x0eebbc00, 0x00b77c00, 0x00fffc00, + 0x00fffc00, 0x01eafc04, 0x1fb5fc45, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* Not used part of burst write is used for precharge, Offset 0x2C */ + 0x0ff5fc04, 0xfffffc05, _NOT_USED_, _NOT_USED_, + /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */ + + /* Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command */ + 0x1ffd7c04, 0xfffffc04, 0xfffffc04, 0xfffffc05, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* Exception, Offset 0x3C */ + 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ +}; + +const uint fpga_table[] = { + /* Single read, offset 0 */ + 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04, + 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05, + + /* Burst read, Offset 0x8 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* Single write, Offset 0x18 */ + 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04, + 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05, + + /* Burst write, Offset 0x20. */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* Period timer service. Offset 0x30. */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* Exception, Offset 0x3C */ + 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ +}; + +int _initsdram (uint base, uint * noMbytes) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *mc = &immap->im_memctl; + volatile u32 *memptr; + + mc->memc_mptpr = MPTPR_PTP_DIV16; /* (16-17) */ + + /* SDRAM in UPMA + + GPL_0 is connected instead of A19 to SDRAM. + According to table 16-17, AMx should be 001, i.e. type 1 + and GPL_0 should hold address A10 when multiplexing */ + + mc->memc_mamr = (0x2E << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_AMA_TYPE_1 | MAMR_G0CLA_A10 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X; /* (16-13) */ + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* Perform init of sdram ( Datasheet Page 9 ) + Precharge */ + mc->memc_mcr = 0x8000212C; /* run upm a at 0x2C (16-15) */ + + /* Run 2 refresh cycles */ + mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */ + mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */ + + /* Set Mode register */ + mc->memc_mar = 0x00000088; /* set mode register (address) to 0x022 (16-17) */ + /* Lower 2 bits are not connected to chip */ + mc->memc_mcr = 0x80002114; /* run upm a at 0x14 (16-15) */ + + /* CS1, base 0x0000000 - 64 Mbyte, use UPM A */ + mc->memc_or1 = 0xfc000000 | OR_CSNT_SAM; + mc->memc_br1 = BR_MS_UPMA | BR_V; /* SDRAM base always 0 */ + + /* Test if we really have 64 MB SDRAM */ + memptr = (u32 *) 0; + *memptr = 0; + + memptr = (u32 *) 0x2000000; /* First u32 in upper 32 MB */ + *memptr = 0x12345678; + + memptr = (u32 *) 0; + if (*memptr == 0x12345678) { + /* Wrapped, only have 32 MB */ + mc->memc_or1 = 0xfe000000 | OR_CSNT_SAM; + *noMbytes = 32; + } else { + /* 64 MB */ + *noMbytes = 64; + } + + /* Setup FPGA in UPMB */ + upmconfig (UPMB, (uint *) fpga_table, + sizeof (fpga_table) / sizeof (uint)); + + /* Enable UPWAITB */ + mc->memc_mbmr = MBMR_GPL_B4DIS; /* (16-13) */ + + /* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */ + mc->memc_or2 = 0xffc00000 | OR_BI; + mc->memc_br2 = FPGA_2_BASE | BR_MS_UPMB | BR_V; + + /* CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit */ + mc->memc_or3 = 0xffc00000 | OR_BI; + mc->memc_br3 = FPGA_3_BASE | BR_MS_UPMB | BR_V | BR_PS_16; + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +void _sdramdisable (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_br1 = 0x00000000; + + /* maybe we should turn off upmb here or something */ +} + +/* ------------------------------------------------------------------------- */ + +int initsdram (uint base, uint * noMbytes) +{ + *noMbytes = 32; + +#ifdef CONFIG_START_IN_RAM + /* SDRAM is already setup. Dont touch it */ + return 0; +#else + + if (!_initsdram (base, noMbytes)) { + + return 0; + } else { + _sdramdisable (); + + return -1; + } +#endif +} + +long int initdram (int board_type) +{ + u32 *i; + u32 j; + u32 k; + + /* GTH only have SDRAM */ + uint sdramsz; + + if (!initsdram (0x00000000, &sdramsz)) { + printf ("(%u MB SDRAM) ", sdramsz); + } else { + /******************************** + *SDRAM ERROR, HALT PROCESSOR + *********************************/ + printf ("SDRAM ERROR\n"); + while (1); + } + +#ifndef CONFIG_START_IN_RAM + +#define U32_S ((sdramsz<<18)-1) + +#if 1 + /* Do a simple memory test */ + for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) { + *i = j + (j << 17); + *(i + 1) = ~(j + (j << 18)); + } + + WATCHDOG_RESET (); + + printf ("."); + + for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) { + k = *i; + if (k != (j + (j << 17))) { + printf ("Mem test error, i=0x%x, 0x%x\n, 0x%x", (u32) i, j, k); + while (1); + } + k = *(i + 1); + if (k != ~(j + (j << 18))) { + printf ("Mem test error(+1), i=0x%x, 0x%x\n, 0x%x", + (u32) i + 1, j, k); + while (1); + } + } +#endif + + WATCHDOG_RESET (); + + /* Clear memory */ + for (i = (u32 *) 0; (u32) i < U32_S; i++) { + *i = 0; + } +#endif /* !start in ram */ + + WATCHDOG_RESET (); + + return (sdramsz << 20); +} + +#define POWER_OFFSET 0xF0000 +#define SW_WATCHDOG_REASON 13 + +#define BOOTDATA_OFFSET 0xF8000 +#define MAX_ATTEMPTS 5 + +#define FAILSAFE_BOOT 1 +#define SYSTEM_BOOT 2 + +#define WRITE_FLASH16(a, d) \ +do \ +{ \ + *((volatile u16 *) (a)) = (d);\ + } while(0) + +static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) +{ + u16 data; + volatile u16 *flash = (u16 *) (CFG_FLASH_BASE); + + if ((System != FAILSAFE_BOOT) & (System != SYSTEM_BOOT)) { + printf ("Invalid system data %u, setting failsafe\n", System); + System = FAILSAFE_BOOT; + } + + if ((Count < 1) | (Count > MAX_ATTEMPTS)) { + printf ("Invalid boot count %u, setting 1\n", Count); + Count = 1; + } + + if (System == FAILSAFE_BOOT) { + printf ("Setting failsafe boot in flash\n"); + } else { + printf ("Setting system boot in flash\n"); + } + printf ("Boot attempt %d\n", Count); + + data = (System << 8) | Count; + /* AMD 16 bit */ + WRITE_FLASH16 (&flash[0x555], 0xAAAA); + WRITE_FLASH16 (&flash[0x2AA], 0x5555); + WRITE_FLASH16 (&flash[0x555], 0xA0A0); + + WRITE_FLASH16 (addr, data); +} + +static void maybe_update_restart_reason (volatile u32 * addr32) +{ + /* Update addr if sw wd restart */ + volatile u16 *flash = (u16 *) (CFG_FLASH_BASE); + volatile u16 *addr_16 = (u16 *) addr32; + u32 rsr; + + /* Dont reset register now */ + rsr = ((volatile immap_t *) CFG_IMMR)->im_clkrst.car_rsr; + + rsr >>= 24; + + if (rsr & 0x10) { + /* Was really a sw wd restart, update reason */ + + printf ("Last restart by software watchdog\n"); + + /* AMD 16 bit */ + WRITE_FLASH16 (&flash[0x555], 0xAAAA); + WRITE_FLASH16 (&flash[0x2AA], 0x5555); + WRITE_FLASH16 (&flash[0x555], 0xA0A0); + + WRITE_FLASH16 (addr_16, 0); + + udelay (1000); + + WATCHDOG_RESET (); + + /* AMD 16 bit */ + WRITE_FLASH16 (&flash[0x555], 0xAAAA); + WRITE_FLASH16 (&flash[0x2AA], 0x5555); + WRITE_FLASH16 (&flash[0x555], 0xA0A0); + + WRITE_FLASH16 (addr_16 + 1, SW_WATCHDOG_REASON); + + } +} + +static void check_restart_reason (void) +{ + /* Update restart reason if sw watchdog was + triggered */ + + int i; + volatile u32 *raddr; + + raddr = (u32 *) (CFG_FLASH_BASE + POWER_OFFSET); + + if (*raddr == 0xFFFFFFFF) { + /* Nothing written */ + maybe_update_restart_reason (raddr); + } else { + /* Search for latest written reason */ + i = 0; + while ((*(raddr + 2) != 0xFFFFFFFF) & (i < 2000)) { + raddr += 2; + i++; + } + if (i >= 2000) { + /* Whoa, dont write any more */ + printf ("*** No free restart reason found ***\n"); + } else { + /* Check if written */ + if (*raddr == 0) { + /* Erased by kernel, no new reason written */ + maybe_update_restart_reason (raddr + 2); + } + } + } +} + +static void check_boot_tries (void) +{ + /* Count the number of boot attemps + switch system if too many */ + + int i; + volatile u16 *addr; + volatile u16 data; + int failsafe = 1; + u8 system; + u8 count; + + addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET); + + if (*addr == 0xFFFF) { + printf ("*** No bootdata exists. ***\n"); + write_bootdata (addr, FAILSAFE_BOOT, 1); + } else { + /* Search for latest written bootdata */ + i = 0; + while ((*(addr + 1) != 0xFFFF) & (i < 8000)) { + addr++; + i++; + } + if (i >= 8000) { + /* Whoa, dont write any more */ + printf ("*** No bootdata found. Not updating flash***\n"); + } else { + /* See how many times we have tried to boot real system */ + data = *addr; + system = data >> 8; + count = data & 0xFF; + if ((system != SYSTEM_BOOT) & (system != FAILSAFE_BOOT)) { + printf ("*** Wrong system %d\n", system); + system = FAILSAFE_BOOT; + count = 1; + } else { + switch (count) { + case 0: + case 1: + case 2: + case 3: + case 4: + /* Try same system again if needed */ + count++; + break; + + case 5: + /* Switch system and reset tries */ + count = 1; + system = 3 - system; + printf ("***Too many boot attempts, switching system***\n"); + break; + default: + /* Switch system, start over and hope it works */ + printf ("***Unexpected data on addr 0x%x, %u***\n", + (u32) addr, data); + count = 1; + system = 3 - system; + } + } + write_bootdata (addr + 1, system, count); + if (system == SYSTEM_BOOT) { + failsafe = 0; + } + } + } + if (failsafe) { + printf ("Booting failsafe system\n"); + setenv ("bootargs", "panic=1 root=/dev/hda7"); + setenv ("bootcmd", "disk 100000 0:5;bootm 100000"); + } else { + printf ("Using normal system\n"); + setenv ("bootargs", "panic=1 root=/dev/hda4"); + setenv ("bootcmd", "disk 100000 0:2;bootm 100000"); + } +} + +int misc_init_r (void) +{ + u8 Rx[80]; + u8 Tx[5]; + int page; + int read = 0; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* Kill fpga */ + immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG | PA_FL_CE); + immap->im_ioport.iop_padir |= (PA_FL_CONFIG | PA_FL_CE); + immap->im_ioport.iop_paodr &= ~(PA_FL_CONFIG | PA_FL_CE); + + /* Enable fpga, active low */ + immap->im_ioport.iop_padat &= ~PA_FL_CE; + + /* Start configuration */ + immap->im_ioport.iop_padat &= ~PA_FL_CONFIG; + udelay (2); + + immap->im_ioport.iop_padat |= (PA_FL_CONFIG | PA_FL_CE); + + /* Check if we need to boot failsafe system */ + check_boot_tries (); + + /* Check if we need to update restart reason */ + check_restart_reason (); + + if (ee_init_data ()) { + printf ("EEPROM init failed\n"); + return (0); + } + + /* Read the pages where ethernet address is stored */ + + for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) { + /* Copy from nvram to scratchpad */ + Tx[0] = RECALL_MEMORY; + Tx[1] = page; + if (ee_do_command (Tx, 2, NULL, 0, TRUE)) { + printf ("EE user page %d recall failed\n", page); + return (0); + } + + Tx[0] = READ_SCRATCHPAD; + if (ee_do_command (Tx, 2, Rx + read, 9, TRUE)) { + printf ("EE user page %d read failed\n", page); + return (0); + } + /* Crc in 9:th byte */ + if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) { + printf ("EE read failed, page %d. CRC error\n", page); + return (0); + } + read += 8; + } + + /* Add eos after eth addr */ + Rx[17] = 0; + + printf ("Ethernet addr read from eeprom: %s\n\n", Rx); + + if ((Rx[2] != ':') | + (Rx[5] != ':') | + (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) { + printf ("*** ethernet addr invalid, using default ***\n"); + } else { + setenv ("ethaddr", (char *)Rx); + } + return (0); +} diff --git a/board/gth/u-boot.lds b/board/gth/u-boot.lds new file mode 100644 index 0000000..8ac4bda --- /dev/null +++ b/board/gth/u-boot.lds @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o(.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/gw8260/Makefile b/board/gw8260/Makefile new file mode 100644 index 0000000..827a6ac --- /dev/null +++ b/board/gw8260/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := gw8260.o flash.o +SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/gw8260/config.mk b/board/gw8260/config.mk new file mode 100644 index 0000000..ca0540d --- /dev/null +++ b/board/gw8260/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MBX8xx boards +# + +TEXT_BASE = 0x40000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c new file mode 100644 index 0000000..5620a1d --- /dev/null +++ b/board/gw8260/flash.c @@ -0,0 +1,523 @@ +/* + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Oliver Brown + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*********************************************************************/ +/* DESCRIPTION: + * This file contains the flash routines for the GW8260 board. + * + * + * + * MODULE DEPENDENCY: + * None + * + * + * RESTRICTIONS/LIMITATIONS: + * + * Only supports the following flash devices: + * AMD 29F080B + * AMD 29F016D + * + * Copyright (c) 2001, Advent Networks, Inc. + * + */ +/*********************************************************************/ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*********************************************************************/ +/* functions */ +/*********************************************************************/ + +/*********************************************************************/ +/* NAME: flash_init() - initializes flash banks */ +/* */ +/* DESCRIPTION: */ +/* This function initializes the flash bank(s). */ +/* */ +/* RETURNS: */ +/* The size in bytes of the flash */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH0_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return (CFG_FLASH0_SIZE * 1024 * 1024); /*size*/ +} + +/*********************************************************************/ +/* NAME: flash_print_info() - prints flash imformation */ +/* */ +/* DESCRIPTION: */ +/* This function prints the flash information. */ +/* */ +/* INPUTS: */ +/* flash_info_t *info - flash information structure */ +/* */ +/* OUTPUTS: */ +/* Displays flash information to console */ +/* */ +/* RETURNS: */ +/* None */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case 0x1: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + case AMD_ID_F080B: + printf ("AM29F080B (8 Mbit)\n"); + break; + case AMD_ID_F016D: + printf ("AM29F016D (16 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*********************************************************************/ +/* The following code cannot be run from FLASH! */ +/*********************************************************************/ + +/*********************************************************************/ +/* NAME: flash_get_size() - detects the flash size */ +/* */ +/* DESCRIPTION: */ +/* 1) Reads vendor ID and devices ID from the flash devices. */ +/* 2) Initializes flash info struct. */ +/* 3) Return the flash size */ +/* */ +/* INPUTS: */ +/* vu_long *addr - pointer to start of flash */ +/* flash_info_t *info - flash information structure */ +/* */ +/* OUTPUTS: */ +/* None */ +/* */ +/* RETURNS: */ +/* Size of the flash in bytes, or 0 if device id is unknown. */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* Only supports the following devices: */ +/* AM29F080D */ +/* AM29F016D */ +/* */ +/*********************************************************************/ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + vu_long vendor, devid; + ulong base = (ulong)addr; + + /*printf("addr = %08lx\n", (unsigned long)addr); */ + + /* Reset and Write auto select command: read Manufacturer ID */ + addr[0x0000] = 0xf0f0f0f0; + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x90909090; + udelay (1000); + + vendor = addr[0]; + /*printf("vendor = %08lx\n", vendor); */ + if (vendor != 0x01010101) { + info->size = 0; + goto out; + } + + devid = addr[1]; + /*printf("devid = %08lx\n", devid); */ + + if ((devid & 0xff) == AMD_ID_F080B) { + info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B; + /* we have 16 sectors with 64KB each x 4 */ + info->sector_count = 16; + info->size = 4 * info->sector_count * 64*1024; + } else if ((devid & 0xff) == AMD_ID_F016D){ + info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F016D; + /* we have 32 sectors with 64KB each x 4 */ + info->sector_count = 32; + info->size = 4 * info->sector_count * 64*1024; + } else { + info->size = 0; + goto out; + } + /*printf("sector count = %08x\n", info->sector_count); */ + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* sector base address */ + info->start[i] = base + i * (info->size / info->sector_count); + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* reset command */ + addr = (vu_long *)info->start[0]; + + out: + addr[0] = 0xf0f0f0f0; + + /*printf("size = %08x\n", info->size); */ + return info->size; +} + +/*********************************************************************/ +/* NAME: flash_erase() - erases flash by sector */ +/* */ +/* DESCRIPTION: */ +/* This function erases flash sectors starting for s_first to */ +/* s_last. */ +/* */ +/* INPUTS: */ +/* flash_info_t *info - flash information structure */ +/* int s_first - first sector to erase */ +/* int s_last - last sector to erase */ +/* */ +/* OUTPUTS: */ +/* None */ +/* */ +/* RETURNS: */ +/* Returns 0 for success, 1 for failure. */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/*********************************************************************/ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x80808080; + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + udelay (100); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x30303030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*********************************************************************/ +/* NAME: write_buff() - writes a buffer to flash */ +/* */ +/* DESCRIPTION: */ +/* This function copies a buffer, *src, to flash. */ +/* */ +/* INPUTS: */ +/* flash_info_t *info - flash information structure */ +/* uchar *src - pointer to buffer to write to flash */ +/* ulong addr - address to start write at */ +/* ulong cnt - number of bytes to write to flash */ +/* */ +/* OUTPUTS: */ +/* None */ +/* */ +/* RETURNS: */ +/* 0 - OK */ +/* 1 - write timeout */ +/* 2 - Flash not erased */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/*********************************************************************/ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + for (; (i < 4) && (cnt > 0); ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; (cnt == 0) && (i < 4); ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; (i < 4) && (cnt > 0); ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; (i < 4); ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*********************************************************************/ +/* NAME: write_word() - writes a word to flash */ +/* */ +/* DESCRIPTION: */ +/* This writes a single word to flash. */ +/* */ +/* INPUTS: */ +/* flash_info_t *info - flash information structure */ +/* ulong dest - address to write */ +/* ulong data - data to write */ +/* */ +/* OUTPUTS: */ +/* None */ +/* */ +/* RETURNS: */ +/* 0 - OK */ +/* 1 - write timeout */ +/* 2 - Flash not erased */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/*********************************************************************/ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0xA0A0A0A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} +/*********************************************************************/ +/* End of flash.c */ +/*********************************************************************/ diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c new file mode 100644 index 0000000..2719a95 --- /dev/null +++ b/board/gw8260/gw8260.c @@ -0,0 +1,659 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Oliver Brown + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*********************************************************************/ +/* DESCRIPTION: + * This file contains the board routines for the GW8260 board. + * + * MODULE DEPENDENCY: + * None + * + * RESTRICTIONS/LIMITATIONS: + * None + * + * Copyright (c) 2001, Advent Networks, Inc. + */ +/*********************************************************************/ + +#include +#include +#include + +/* + * I/O Port configuration table + * + */ +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* TP14 */ + /* PA30 */ { 1, 1, 1, 1, 0, 0 }, /* US_RTS */ + /* PA29 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_DATA */ + /* PA28 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_CLK */ + /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* TP12 */ + /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* IO_STATUS */ + /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CLOCK */ + /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CONFIG */ + /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DONE */ + /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DATA */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD3 */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD2 */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD1 */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD0 */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD0 */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD1 */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD2 */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD3 */ + /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE7 */ + /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE6 */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE5 */ + /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE4 */ + /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE3 */ + /* PA8 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE2 */ + /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* LSSI_IN */ + /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE0 */ + /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* DEMOD_RESET_ */ + /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* MOD_RESET_ */ + /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* IO_RESET */ + /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* TX_ENABLE */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* RX_LOCK */ + /* PA0 */ { 1, 0, 0, 1, 0, 1 } /* MPC_RESET_ */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FETH0_TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD3 */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD2 */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD1 */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD0 */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD0 */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD1 */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD2 */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD3 */ + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_DV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_ER */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_ER */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD3 */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD2 */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD1 */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD0 */ + /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD0 */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD1 */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD2 */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD3 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_RESET_ */ + /* PC30 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_PAUSE_ */ + /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW1 */ + /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW0 */ + /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* TP13 */ + /* PC26 */ { 1, 0, 0, 0, 0, 0 }, /* RXDECDFLG */ + /* PC25 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFAIL */ + /* PC24 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFLG */ + /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* WD_TCL */ + /* PC22 */ { 1, 0, 0, 1, 0, 0 }, /* WD_EN */ + /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* US_TXCLK */ + /* PC20 */ { 1, 0, 0, 0, 0, 0 }, /* DS_RXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_TX_CLK */ + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_CLK */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_TX_CLK */ + /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* TX_SHUTDOWN_ */ + /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* RS_232_DTR_ */ + /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* TXERR */ + /* PC12 */ { 1, 0, 0, 1, 0, 1 }, /* FETH1_MDDIS */ + /* PC11 */ { 1, 0, 0, 1, 0, 1 }, /* FETH0_MDDIS */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */ + /* PC9 */ { 1, 0, 0, 1, 1, 1 }, /* MDIO */ + /* PC8 */ { 1, 0, 0, 1, 1, 1 }, /* SER_NUM */ + /* PC7 */ { 1, 1, 0, 0, 0, 0 }, /* US_CTS */ + /* PC6 */ { 1, 1, 0, 0, 0, 0 }, /* DS_CD_ */ + /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* FETH1_PWRDWN */ + /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* FETH0_PWRDWN */ + /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED3 */ + /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED2 */ + /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED1 */ + /* PC0 */ { 1, 0, 0, 1, 0, 1 }, /* MPULED0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ + /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ + /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ + /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ + /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SCL */ + /* PD13 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED7 */ + /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED6 */ + /* PD11 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED5 */ + /* PD10 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED4 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* RS232_TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* RD232_RXD */ + /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/*********************************************************************/ +/* NAME: checkboard() - Displays the board type and serial number */ +/* */ +/* OUTPUTS: */ +/* Displays the board type and serial number */ +/* */ +/* RETURNS: */ +/* Always returns 1 */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int checkboard (void) +{ + char *str; + + puts ("Board: Advent Networks gw8260\n"); + + str = getenv ("serial#"); + if (str != NULL) { + printf ("SN: %s\n", str); + } + return 0; +} + + +#if defined (CFG_DRAM_TEST) +/*********************************************************************/ +/* NAME: move64() - moves a double word (64-bit) */ +/* */ +/* DESCRIPTION: */ +/* this function performs a double word move from the data at */ +/* the source pointer to the location at the destination pointer. */ +/* */ +/* INPUTS: */ +/* unsigned long long *src - pointer to data to move */ +/* */ +/* OUTPUTS: */ +/* unsigned long long *dest - pointer to locate to move data */ +/* */ +/* RETURNS: */ +/* None */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* May cloober fr0. */ +/* */ +/*********************************************************************/ +static void move64 (unsigned long long *src, unsigned long long *dest) +{ + asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : : "fr0"); /* Clobbers fr0 */ + return; +} + + +#if defined (CFG_DRAM_TEST_DATA) + +unsigned long long pattern[] = { + 0xaaaaaaaaaaaaaaaaULL, + 0xccccccccccccccccULL, + 0xf0f0f0f0f0f0f0f0ULL, + 0xff00ff00ff00ff00ULL, + 0xffff0000ffff0000ULL, + 0xffffffff00000000ULL, + 0x00000000ffffffffULL, + 0x0000ffff0000ffffULL, + 0x00ff00ff00ff00ffULL, + 0x0f0f0f0f0f0f0f0fULL, + 0x3333333333333333ULL, + 0x5555555555555555ULL, +}; + +/*********************************************************************/ +/* NAME: mem_test_data() - test data lines for shorts and opens */ +/* */ +/* DESCRIPTION: */ +/* Tests data lines for shorts and opens by forcing adjacent data */ +/* to opposite states. Because the data lines could be routed in */ +/* an arbitrary manner the must ensure test patterns ensure that */ +/* every case is tested. By using the following series of binary */ +/* patterns every combination of adjacent bits is test regardless */ +/* of routing. */ +/* */ +/* ...101010101010101010101010 */ +/* ...110011001100110011001100 */ +/* ...111100001111000011110000 */ +/* ...111111110000000011111111 */ +/* */ +/* Carrying this out, gives us six hex patterns as follows: */ +/* */ +/* 0xaaaaaaaaaaaaaaaa */ +/* 0xcccccccccccccccc */ +/* 0xf0f0f0f0f0f0f0f0 */ +/* 0xff00ff00ff00ff00 */ +/* 0xffff0000ffff0000 */ +/* 0xffffffff00000000 */ +/* */ +/* The number test patterns will always be given by: */ +/* */ +/* log(base 2)(number data bits) = log2 (64) = 6 */ +/* */ +/* To test for short and opens to other signals on our boards. we */ +/* simply */ +/* test with the 1's complemnt of the paterns as well. */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* Assumes only one one SDRAM bank */ +/* */ +/*********************************************************************/ +int mem_test_data (void) +{ + unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE; + unsigned long long temp64 = 0; + int num_patterns = sizeof (pattern) / sizeof (pattern[0]); + int i; + unsigned int hi, lo; + + for (i = 0; i < num_patterns; i++) { + move64 (&(pattern[i]), pmem); + move64 (pmem, &temp64); + + /* hi = (temp64>>32) & 0xffffffff; */ + /* lo = temp64 & 0xffffffff; */ + /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ + + hi = (pattern[i] >> 32) & 0xffffffff; + lo = pattern[i] & 0xffffffff; + /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ + + if (temp64 != pattern[i]) { + printf ("\n Data Test Failed, pattern 0x%08x%08x", + hi, lo); + return 1; + } + } + + return 0; +} +#endif /* CFG_DRAM_TEST_DATA */ + +#if defined (CFG_DRAM_TEST_ADDRESS) +/*********************************************************************/ +/* NAME: mem_test_address() - test address lines */ +/* */ +/* DESCRIPTION: */ +/* This function performs a test to verify that each word im */ +/* memory is uniquly addressable. The test sequence is as follows: */ +/* */ +/* 1) write the address of each word to each word. */ +/* 2) verify that each location equals its address */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_address (void) +{ + volatile unsigned int *pmem = + (volatile unsigned int *) CFG_SDRAM_BASE; + const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024) / 4; + unsigned int i; + + /* write address to each location */ + for (i = 0; i < size; i++) { + pmem[i] = i; + } + + /* verify each loaction */ + for (i = 0; i < size; i++) { + if (pmem[i] != i) { + printf ("\n Address Test Failed at 0x%x", i); + return 1; + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_ADDRESS */ + +#if defined (CFG_DRAM_TEST_WALK) +/*********************************************************************/ +/* NAME: mem_march() - memory march */ +/* */ +/* DESCRIPTION: */ +/* Marches up through memory. At each location verifies rmask if */ +/* read = 1. At each location write wmask if write = 1. Displays */ +/* failing address and pattern. */ +/* */ +/* INPUTS: */ +/* volatile unsigned long long * base - start address of test */ +/* unsigned int size - number of dwords(64-bit) to test */ +/* unsigned long long rmask - read verify mask */ +/* unsigned long long wmask - wrtie verify mask */ +/* short read - verifies rmask if read = 1 */ +/* short write - writes wmask if write = 1 */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_march (volatile unsigned long long *base, + unsigned int size, + unsigned long long rmask, + unsigned long long wmask, short read, short write) +{ + unsigned int i; + unsigned long long temp = 0; + unsigned int hitemp, lotemp, himask, lomask; + + for (i = 0; i < size; i++) { + if (read != 0) { + /* temp = base[i]; */ + move64 ((unsigned long long *) &(base[i]), &temp); + if (rmask != temp) { + hitemp = (temp >> 32) & 0xffffffff; + lotemp = temp & 0xffffffff; + himask = (rmask >> 32) & 0xffffffff; + lomask = rmask & 0xffffffff; + + printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); + return 1; + } + } + if (write != 0) { + /* base[i] = wmask; */ + move64 (&wmask, (unsigned long long *) &(base[i])); + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_WALK */ + +/*********************************************************************/ +/* NAME: mem_test_walk() - a simple walking ones test */ +/* */ +/* DESCRIPTION: */ +/* Performs a walking ones through entire physical memory. The */ +/* test uses as series of memory marches, mem_march(), to verify */ +/* and write the test patterns to memory. The test sequence is as */ +/* follows: */ +/* 1) march writing 0000...0001 */ +/* 2) march verifying 0000...0001 , writing 0000...0010 */ +/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ +/* the write mask equals 1000...0000 */ +/* 4) march verifying 1000...0000 */ +/* The test fails if any of the memory marches return a failure. */ +/* */ +/* OUTPUTS: */ +/* Displays which pass on the memory test is executing */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_walk (void) +{ + unsigned long long mask; + volatile unsigned long long *pmem = + (volatile unsigned long long *) CFG_SDRAM_BASE; + const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024) / 8; + + unsigned int i; + + mask = 0x01; + + printf ("Initial Pass"); + mem_march (pmem, size, 0x0, 0x1, 0, 1); + + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + + for (i = 0; i < 63; i++) { + printf ("Pass %2d", i + 2); + if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { + /*printf("mask: 0x%x, pass: %d, ", mask, i); */ + return 1; + } + mask = mask << 1; + printf ("\b\b\b\b\b\b\b"); + } + + printf ("Last Pass"); + if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { + /* printf("mask: 0x%x", mask); */ + return 1; + } + printf ("\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b"); + + return 0; +} + +/*********************************************************************/ +/* NAME: testdram() - calls any enabled memory tests */ +/* */ +/* DESCRIPTION: */ +/* Runs memory tests if the environment test variables are set to */ +/* 'y'. */ +/* */ +/* INPUTS: */ +/* testdramdata - If set to 'y', data test is run. */ +/* testdramaddress - If set to 'y', address test is run. */ +/* testdramwalk - If set to 'y', walking ones test is run */ +/* */ +/* OUTPUTS: */ +/* None */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int testdram (void) +{ + char *s; + int rundata, runaddress, runwalk; + + s = getenv ("testdramdata"); + rundata = (s && (*s == 'y')) ? 1 : 0; + s = getenv ("testdramaddress"); + runaddress = (s && (*s == 'y')) ? 1 : 0; + s = getenv ("testdramwalk"); + runwalk = (s && (*s == 'y')) ? 1 : 0; + + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf ("Testing RAM ... "); + } +#ifdef CFG_DRAM_TEST_DATA + if (rundata == 1) { + if (mem_test_data () == 1) { + return 1; + } + } +#endif +#ifdef CFG_DRAM_TEST_ADDRESS + if (runaddress == 1) { + if (mem_test_address () == 1) { + return 1; + } + } +#endif +#ifdef CFG_DRAM_TEST_WALK + if (runwalk == 1) { + if (mem_test_walk () == 1) { + return 1; + } + } +#endif + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf ("passed"); + } + return 0; + +} +#endif /* CFG_DRAM_TEST */ + +/*********************************************************************/ +/* NAME: initdram() - initializes SDRAM controller */ +/* */ +/* DESCRIPTION: */ +/* Initializes the MPC8260's SDRAM controller. */ +/* */ +/* INPUTS: */ +/* CFG_IMMR - MPC8260 Internal memory map */ +/* CFG_SDRAM_BASE - Physical start address of SDRAM */ +/* CFG_PSDMR - SDRAM mode register */ +/* CFG_MPTPR - Memory refresh timer prescaler register */ +/* CFG_SDRAM0_SIZE - SDRAM size */ +/* */ +/* RETURNS: */ +/* SDRAM size in bytes */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); + ulong psdmr = CFG_PSDMR; + int i; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) { + *ramaddr = c; + } + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + + /* return total ram size */ + return (CFG_SDRAM0_SIZE * 1024 * 1024); +} + +/*********************************************************************/ +/* End of gw8260.c */ +/*********************************************************************/ diff --git a/board/gw8260/u-boot.lds b/board/gw8260/u-boot.lds new file mode 100644 index 0000000..ab65cb1 --- /dev/null +++ b/board/gw8260/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hermes/Makefile b/board/hermes/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/hermes/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/hermes/config.mk b/board/hermes/config.mk new file mode 100644 index 0000000..008165f --- /dev/null +++ b/board/hermes/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Multidata HERMES-PRO ISDN Routers +# + +TEXT_BASE = 0xFE000000 diff --git a/board/hermes/flash.c b/board/hermes/flash.c new file mode 100644 index 0000000..799fe83 --- /dev/null +++ b/board/hermes/flash.c @@ -0,0 +1,460 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_byte (flash_info_t *info, ulong dest, uchar data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | + (memctl->memc_br0 & ~(BR_BA_MSK)); + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + flash_info[0].size = size; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + uchar value; + vu_char *caddr = (vu_char *)addr; + ulong base = (ulong)addr; + + + /* Write auto select command: read Manufacturer ID */ + caddr[0x0AAA] = 0xAA; + caddr[0x0555] = 0x55; + caddr[0x0AAA] = 0x90; + + value = caddr[0]; + switch (value) { + case (AMD_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = caddr[2]; /* device ID */ + + switch (value) { + case (AMD_ID_LV400T & 0xFF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV400B & 0xFF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV800T & 0xFF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800B & 0xFF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV160T & 0xFF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160B & 0xFF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & 0xFF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV320B & 0xFF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection: D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[4] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (vu_char *)info->start[0]; + + *caddr = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_char *addr = (vu_char*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0AAA] = 0xAA; + addr[0x0555] = 0x55; + addr[0x0AAA] = 0x80; + addr[0x0AAA] = 0xAA; + addr[0x0555] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char*)(info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_char*)(info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + int rc; + + while (cnt > 0) { + if ((rc = write_byte(info, addr++, *src++)) != 0) { + return (rc); + } + --cnt; + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte (flash_info_t *info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0AAA] = 0xAA; + addr[0x0555] = 0x55; + addr[0x0AAA] = 0xA0; + + *((vu_char *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c new file mode 100644 index 0000000..e95d9ee --- /dev/null +++ b/board/hermes/hermes.c @@ -0,0 +1,605 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); +static ulong board_init (void); +static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd, + uchar * msg); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, + 0x1ff77c47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00, + 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7ffffc07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Test ID string (HERMES...) + * + * Return code for board revision and network speed + */ + +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char *s = getenv ("serial#"); + char *e; + + puts ("Board: "); + + if (!s || strncmp (s, "HERMES", 6)) { + puts ("### No HW ID - assuming HERMES-PRO"); + } else { + for (e = s; *e; ++e) { + if (*e == ' ') + break; + } + + for (; s < e; ++s) { + putc (*s); + } + } + + gd->board_type = board_init (); + + printf (" Rev. %ld.x\n", (gd->board_type >> 16)); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size, size8, size9; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = 0x0400; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 1 to the SDRAM banks at preliminary address + */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + /* HERMES-PRO boards have only one bank SDRAM */ + + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mamr = 0xD0802114; + memctl->memc_mcr = 0x80002105; + udelay (1); + memctl->memc_mamr = 0xD0802118; + memctl->memc_mcr = 0x80002130; + udelay (1); + memctl->memc_mamr = 0xD0802114; + memctl->memc_mcr = 0x80002106; + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, + SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size = size9; +/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + size = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); +/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + udelay (1000); + + memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; + memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + udelay (10000); + + return (size); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +#define PB_LED_3 0x00020000 /* Status LED's */ +#define PB_LED_2 0x00010000 +#define PB_LED_1 0x00008000 +#define PB_LED_0 0x00004000 + +#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3) + +#define PC_REP_SPD1 0x00000800 +#define PC_REP_SPD0 0x00000400 + +#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */ + +#define PB_MAI_4 0x00000010 /* Configuration */ +#define PB_MAI_3 0x00000008 +#define PB_MAI_2 0x00000004 +#define PB_MAI_1 0x00000002 +#define PB_MAI_0 0x00000001 + +#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4) + + +#define PC_REP_MGRPRS 0x0200 +#define PC_REP_SPD 0x0040 /* Select 100 Mbps */ +#define PC_REP_RES 0x0004 +#define PC_BIT14 0x0002 /* ??? */ +#define PC_BIT15 0x0001 /* ??? ENDSL ?? */ + +/* ------------------------------------------------------------------------- */ + +static ulong board_init (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + ulong reg, revision, speed = 100; + int ethspeed; + char *s; + + if ((s = getenv ("ethspeed")) != NULL) { + if (strcmp (s, "100") == 0) { + ethspeed = 100; + } else if (strcmp (s, "10") == 0) { + ethspeed = 10; + } else { + ethspeed = 0; + } + } else { + ethspeed = 0; + } + + /* Configure Port B Output Pins => 0x0003cc3F */ + reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 | + PB_MAI_ALL; + immr->im_cpm.cp_pbpar &= ~reg; + immr->im_cpm.cp_pbodr &= ~reg; + immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */ + immr->im_cpm.cp_pbdir |= reg; + + /* Check hardware revision */ + if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) { + /* + * Revision 3.x hardware + */ + revision = 3; + + immr->im_ioport.iop_pcdat = 0x0240; + immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */ + immr->im_ioport.iop_pcdat |= PC_REP_RES; + } else { + immr->im_ioport.iop_pcdat = 0x0002; + immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */ + + if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) { + /* + * Revision 2.x hardware: PC9 connected to PB21 + */ + revision = 2; + + if (ethspeed == 0) { + /* both 10 and 100 Mbps allowed: + * select 10 Mbps and autonegotiation + */ + puts (" [10+100]"); + immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */ + speed = 10; + } else if (ethspeed == 10) { + /* we are asked for 10 Mbps, + * so select 10 Mbps + */ + puts (" [10]"); + immr->im_cpm.cp_pbdat = 0; /* ??? */ + speed = 10; + } else { + /* anything else: + * select 100 Mbps + */ + puts (" [100]"); + immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1; + /* SPD1:SPD0 = 1:1 - 100 Mbps */ + speed = 100; + } + immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14); + + /* must be run from RAM */ + /* start_lxt980 (speed); */ + /*************************/ + } else { + /* + * Revision 1.x hardware + */ + revision = 1; + + immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */ + immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */ + + if (ethspeed == 0) { + /* both 10 and 100 Mbps allowed: + * select 100 Mbps and autonegotiation + */ + puts (" [10+100]"); + immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */ + immr->im_ioport.iop_pcdat |= PC_REP_SPD; + } else if (ethspeed == 10) { + /* we are asked for 10 Mbps, + * so select 10 Mbps + */ + puts (" [10]"); + immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */ + } else { + /* anything else: + * select 100 Mbps + */ + puts (" [100]"); + immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1; + /* SPD1:SPD0 = 1:1 - 100 Mbps */ + immr->im_ioport.iop_pcdat |= PC_REP_SPD; + } + + immr->im_ioport.iop_pcdat |= PC_REP_RES; + } + } + SHOW_BOOT_PROGRESS (0x00); + + return ((revision << 16) | (speed & 0xFFFF)); +} + +/* ------------------------------------------------------------------------- */ + +#define SCC_SM 1 /* Index => SCC2 */ +#define PROFF PROFF_SCC2 + +#define SMI_MSGLEN 8 /* Length of SMI Messages */ + +#define PHYGPCR_ADDR 0x109 /* Port Enable */ +#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */ +#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */ +#define RPRESET_ADDR 0x144 /* Repeater Reset */ + +#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */ +#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */ +#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */ +#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */ +#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */ + +/* ------------------------------------------------------------------------- */ + +/* + * Must run from RAM: + * uses parameter RAM area which is used for stack while running from ROM + */ +void hermes_start_lxt980 (int speed) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm); + volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]); + volatile cbd_t *bd; + volatile hdlc_pram_t *hp; + uchar smimsg[SMI_MSGLEN]; + ushort phypcrval; + uint bd_off; + int pnr; + + printf ("LXT9880: %3d Mbps\n", speed); + + immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */ + immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */ + immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */ + immr->im_ioport.iop_padir |= 0x4000; + + /* get temporary BD; no need for permanent alloc */ + bd_off = dpram_base_align (8); + + bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off); + + bd->cbd_bufaddr = 0; + bd->cbd_datlen = 0; + bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC; + + /* init. baudrate generator BRG4 */ + cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */ + + cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */ + cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */ + + /* init SCC_SM register */ + sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */ + sp->scc_todr = 0x0000; + sp->scc_dsr = 0x7e7e; + + /* init. SCC_SM parameter area */ + hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF]; + + hp->tbase = bd_off; /* offset from beginning of DPRAM */ + + hp->rfcr = 0x18; + hp->tfcr = 0x18; + hp->mrblr = 10; + + hp->c_mask = 0x0000f0b8; + hp->c_pres = 0x0000ffff; + + hp->disfc = 0; + hp->crcec = 0; + hp->abtsc = 0; + hp->nmarc = 0; + hp->retrc = 0; + + hp->mflr = 10; + + hp->rfthr = 1; + + hp->hmask = 0; + hp->haddr1 = 0; + hp->haddr2 = 0; + hp->haddr3 = 0; + hp->haddr4 = 0; + + cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */ + while (cp->cp_cpcr & CPM_CR_FLG); + + /* clear all outstanding SCC events */ + sp->scc_scce = ~0; + + /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */ + sp->scc_gsmrh = 0; + sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 | + SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC; + +#if 0 + smimsg[0] = 0x00; /* CHIP/HUB ID */ + smimsg[1] = 0x38; /* WRITE CMD */ + smimsg[2] = (RPRESET_ADDR << 4) & 0xf0; + smimsg[3] = RPRESET_ADDR >> 4; + smimsg[4] = 0x01; + smimsg[5] = 0x00; + smimsg[6] = 0x00; + smimsg[7] = 0x00; + + send_smi_frame (sp, bd, smimsg); +#endif + + smimsg[0] = 0x7f; /* BROADCAST */ + smimsg[1] = 0x34; /* ASSIGN HUB ID */ + smimsg[2] = 0x00; + smimsg[3] = 0x00; + smimsg[4] = 0x00; /* HUB ID = 0 */ + smimsg[5] = 0x00; + smimsg[6] = 0x00; + smimsg[7] = 0x00; + + send_smi_frame (sp, bd, smimsg); + + smimsg[0] = 0x7f; /* BROADCAST */ + smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */ + smimsg[2] = 0x00; /* ADDRESS = 0 */ + smimsg[3] = 0x00; + smimsg[4] = 0x00; /* DATA = 0 */ + smimsg[5] = 0x00; + smimsg[6] = 0x00; + smimsg[7] = 0x00; + + send_smi_frame (sp, bd, smimsg); + + if (speed == 100) { + phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */ + } else { + phypcrval = 0; /* 10 MBIT, disable autoneg. */ + } + + /* send MSGs */ + for (pnr = 0; pnr < 8; pnr++) { + smimsg[0] = 0x00; /* CHIP/HUB ID */ + smimsg[1] = 0x38; /* WRITE CMD */ + smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0; + smimsg[3] = (PHYPCR_ADDR + pnr) >> 4; + smimsg[4] = (unsigned char) (phypcrval & 0xff); + smimsg[5] = (unsigned char) (phypcrval >> 8); + smimsg[6] = 0x00; + smimsg[7] = 0x00; + + send_smi_frame (sp, bd, smimsg); + } + + smimsg[0] = 0x00; /* CHIP/HUB ID */ + smimsg[1] = 0x38; /* WRITE CMD */ + smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0; + smimsg[3] = PHYGPCR_ADDR >> 4; + smimsg[4] = 0xff; /* enable port 1-8 */ + smimsg[5] = 0x01; /* enable MII1 (0x01) */ + smimsg[6] = 0x00; + smimsg[7] = 0x00; + + send_smi_frame (sp, bd, smimsg); + + smimsg[0] = 0x00; /* CHIP/HUB ID */ + smimsg[1] = 0x38; /* WRITE CMD */ + smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0; + smimsg[3] = LEDPCR_ADDR >> 4; + smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */ + smimsg[5] = 0xaa; + smimsg[6] = 0x00; + smimsg[7] = 0x00; + + send_smi_frame (sp, bd, smimsg); + + /* + * Disable Transmitter (so that we can free the BD, too) + */ + sp->scc_gsmrl &= ~SCC_GSMRL_ENT; +} + +/* ------------------------------------------------------------------------- */ + +static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd, + uchar * msg) +{ +#ifdef DEBUG + unsigned hub, chip, cmd, length, addr; + + hub = msg[0] & 0x1F; + chip = msg[0] >> 5; + cmd = msg[1] & 0x1F; + length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3); + addr = (msg[2] >> 4) | (msg[3] << 4); + + printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: " + "%02x %02x %02x %02x\n", + hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]); +#endif /* DEBUG */ + + bd->cbd_bufaddr = (uint) msg; + bd->cbd_datlen = SMI_MSGLEN; + bd->cbd_sc |= BD_SC_READY; + + /* wait for msg transmitted */ + while ((sp->scc_scce & 0x0002) == 0); + /* clear all events */ + sp->scc_scce = ~0; +} + +/* ------------------------------------------------------------------------- */ + +void show_boot_progress (int status) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + status ^= 0x0F; + status = (status & 0x0F) << 14; + immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status; +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds new file mode 100644 index 0000000..ef53ab7 --- /dev/null +++ b/board/hermes/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + cpu/mpc8xx/interrupts.o (.text) + lib_ppc/time.o (.text) + lib_ppc/ticks.o (.text) + lib_ppc/cache.o (.text) + lib_generic/crc32.o (.text) + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug new file mode 100644 index 0000000..a961fa4 --- /dev/null +++ b/board/hermes/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + lib_ppc/ppcstring.o (.text) + cpu/mpc8xx/interrupts.o (.text) + lib_ppc/time.o (.text) + lib_ppc/ticks.o (.text) + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hidden_dragon/Makefile b/board/hidden_dragon/Makefile new file mode 100644 index 0000000..b9f1df6 --- /dev/null +++ b/board/hidden_dragon/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/hidden_dragon/README b/board/hidden_dragon/README new file mode 100644 index 0000000..529fe2b --- /dev/null +++ b/board/hidden_dragon/README @@ -0,0 +1,60 @@ +U-Boot for Hidden Dragon board +------------------------------ + +Hidden Dragon is a MPC824x-based board by Motorola. For the most +part it is similar to Sandpoint8245 board. So unless otherwise +mentioned, the codes in this directory are adapted from ../sandpoint +directory. + +Apparently there are very few of this board out there. Even Motorola +website does not have any info on it. + +RAM: + start = 0x0000 0000 + size = 0x0200 0000 (32 MB) + +Flash: + BANK ONE: + start = 0xFFE0 0000 + size = 0x0020 0000 (2 MB) + flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits) + flash sectors = 16K, 2x8K, 32K, 31x64K + + BANK TWO: + NONE + +The processor interrupt vectors reside on the first 256 bytes +starting from address 0xFFF00000. The "reset vector" (first +instruction executed after reset) is located on 0xFFF0 0100. + +U-Boot is configured to reside in flash starting at the address of +0xFFF00000. The environment space is located in flash separately from +U-Boot, at the second sector of the first flash bank, starting from +0xFFE04000 until 0xFFE06000 (8KB). + +Network: + - RTL8139 chip on the base board (SUPPORTED) + - RTL8129 chip on the processor board (NOT SUPPORTED) + +Serial: + - Two NS16550 compatible UART on the processor board (SUPPORTED) + - One NS16550 compatible UART on the base board (UNTESTED) + +Misc: + VIA686A PCI SuperIO peripheral controller + - 2 USB ports (UNTESTED) + - 2 PS2 ports (UNTESTED) + - Parallel port (UNTESTED) + - IDE & floppy interface (UNTESTED) + + S3 Savage4 video card (UNTESTED) + +TODO: +----- +- Support for the VIA686A based peripherals +- The RTL8139 driver frequently gives rx error. +- Support for RTL8129 network controller. (Why is the support removed from + rtl8139.c driver?) + +(C) Copyright 2004 +Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com diff --git a/board/hidden_dragon/config.mk b/board/hidden_dragon/config.mk new file mode 100644 index 0000000..5c36d05 --- /dev/null +++ b/board/hidden_dragon/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Hidden Dragon boards +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/hidden_dragon/early_init.S b/board/hidden_dragon/early_init.S new file mode 100644 index 0000000..07dafb7 --- /dev/null +++ b/board/hidden_dragon/early_init.S @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2001 + * Thomas Koeller, tkoeller@gmx.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ 1 +#endif + +#include +#include +#include +#include + +#if defined(USE_DINK32) + /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ + #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) +#else + #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) +#endif + + .text + + /* Values to program into memory controller registers */ +tbl: .long MCCR1, MCCR1VAL + .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT + .long MCCR3 + .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ + (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ + (CFG_RDLAT << MCCR3_RDLAT_SHIFT) + .long MCCR4 + .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ + (CFG_REGISTERD_TYPE_BUFFER << 20) | \ + (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ + ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ + (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ + (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ + ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) + .long MSAR1 + .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMSAR1 + .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MSAR2 + .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMSAR2 + .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MEAR1 + .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMEAR1 + .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MEAR2 + .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMEAR2 + .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long 0 + + + /* + * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This + * must be done in assembly, since we have no stack at this point. + */ + .global early_init_f +early_init_f: + mflr r10 + + /* basic memory controller configuration */ + lis r3, CONFIG_ADDR_HIGH + lis r4, CONFIG_DATA_HIGH + bl lab +lab: mflr r5 + lwzu r0, tbl - lab(r5) +loop: lwz r1, 4(r5) + stwbrx r0, 0, r3 + eieio + stwbrx r1, 0, r4 + eieio + lwzu r0, 8(r5) + cmpli cr0, 0, r0, 0 + bne cr0, loop + + /* set bank enable bits */ + lis r0, MBER@h + ori r0, 0, MBER@l + li r1, CFG_BANK_ENABLE + stwbrx r0, 0, r3 + eieio + stb r1, 0(r4) + eieio + + /* delay loop */ + lis r0, 0x0003 + mtctr r0 +delay: bdnz delay + + /* enable memory controller */ + lis r0, MCCR1@h + ori r0, 0, MCCR1@l + stwbrx r0, 0, r3 + eieio + lwbrx r0, 0, r4 + oris r0, 0, MCCR1_MEMGO@h + stwbrx r0, 0, r4 + eieio + + /* set up stack pointer */ + lis r1, CFG_INIT_SP_OFFSET@h + ori r1, r1, CFG_INIT_SP_OFFSET@l + + mtlr r10 + blr diff --git a/board/hidden_dragon/flash.c b/board/hidden_dragon/flash.c new file mode 100644 index 0000000..21c5a01 --- /dev/null +++ b/board/hidden_dragon/flash.c @@ -0,0 +1,575 @@ +/* + * (C) Copyright 2004 + * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com + * + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define ROM_CS0_START 0xFF800000 +#define ROM_CS1_START 0xFF000000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*flash command address offsets*/ + +#define ADDR0 (0xAAA) +#define ADDR1 (0x555) +#define ADDR3 (0x001) + +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------- + */ + +static unsigned long flash_id (unsigned char mfct, unsigned char chip) + __attribute__ ((const)); + +typedef struct { + FLASH_WORD_SIZE extval; + unsigned short intval; +} map_entry; + +static unsigned long flash_id (unsigned char mfct, unsigned char chip) +{ + static const map_entry mfct_map[] = { + {(FLASH_WORD_SIZE) AMD_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, + {(FLASH_WORD_SIZE) FUJ_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, + {(FLASH_WORD_SIZE) STM_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, + {(FLASH_WORD_SIZE) MT_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, + {(FLASH_WORD_SIZE) INTEL_MANUFACT, + (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, + {(FLASH_WORD_SIZE) INTEL_ALT_MANU, + (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} + }; + + static const map_entry chip_map[] = { + {AMD_ID_F040B, FLASH_AM040}, + {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} + }; + + const map_entry *p; + unsigned long result = FLASH_UNKNOWN; + + /* find chip id */ + for (p = &chip_map[0]; + p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) + if (p->extval == chip) { + result = FLASH_VENDMASK | p->intval; + break; + } + + /* find vendor id */ + for (p = &mfct_map[0]; + p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) + if (p->extval == mfct) { + result &= ~FLASH_VENDMASK; + result |= (unsigned long) p->intval << 16; + break; + } + + return result; +} + +unsigned long flash_init (void) +{ + unsigned long i; + unsigned char j; + static const ulong flash_banks[] = CFG_FLASH_BANKS; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info_t *const pflinfo = &flash_info[i]; + + pflinfo->flash_id = FLASH_UNKNOWN; + pflinfo->size = 0; + pflinfo->sector_count = 0; + } + + /* Enable writes to Hidden Dragon flash */ + { + register unsigned char temp; + + CONFIG_READ_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, + temp); + temp &= ~0x20; /* clear BIOSWP bit */ + CONFIG_WRITE_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, + temp); + } + + for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) { + flash_info_t *const pflinfo = &flash_info[i]; + const unsigned long base_address = flash_banks[i]; + volatile FLASH_WORD_SIZE *const flash = + (FLASH_WORD_SIZE *) base_address; + + flash[0xAAA << (3 * i)] = 0xaa; + flash[0x555 << (3 * i)] = 0x55; + flash[0xAAA << (3 * i)] = 0x90; + __asm__ __volatile__ ("sync"); + + pflinfo->flash_id = + flash_id (flash[0x0], flash[0x2 + 14 * i]); + + switch (pflinfo->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + pflinfo->size = 0x00080000; + pflinfo->sector_count = 8; + for (j = 0; j < 8; j++) { + pflinfo->start[j] = + base_address + 0x00010000 * j; + pflinfo->protect[j] = flash[(j << 16) | 0x2]; + } + break; + case FLASH_STM800AB: + pflinfo->size = 0x00100000; + pflinfo->sector_count = 19; + pflinfo->start[0] = base_address; + pflinfo->start[1] = base_address + 0x4000; + pflinfo->start[2] = base_address + 0x6000; + pflinfo->start[3] = base_address + 0x8000; + for (j = 1; j < 16; j++) { + pflinfo->start[j + 3] = + base_address + 0x00010000 * j; + } + break; + default: + /* The chip used is not listed in flash_id + TODO: Change this to explicitly detect the flash type + */ + { + int sector_addr = base_address; + + pflinfo->size = 0x00200000; + pflinfo->sector_count = 35; + pflinfo->start[0] = sector_addr; + sector_addr += 0x4000; /* 16K */ + pflinfo->start[1] = sector_addr; + sector_addr += 0x2000; /* 8K */ + pflinfo->start[2] = sector_addr; + sector_addr += 0x2000; /* 8K */ + pflinfo->start[3] = sector_addr; + sector_addr += 0x8000; /* 32K */ + + for (j = 4; j < 35; j++) { + pflinfo->start[j] = sector_addr; + sector_addr += 0x10000; /* 64K */ + } + } + break; + } + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + /* reset device to read mode */ + flash[0x0000] = 0xf0; + __asm__ __volatile__ ("sync"); + } + + /* only have 1 bank */ + return flash_info[0].size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + static const char unk[] = "Unknown"; + const char *mfct = unk, *type = unk; + unsigned int i; + + if (info->flash_id != FLASH_UNKNOWN) { + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + mfct = "AMD"; + break; + case FLASH_MAN_FUJ: + mfct = "FUJITSU"; + break; + case FLASH_MAN_STM: + mfct = "STM"; + break; + case FLASH_MAN_SST: + mfct = "SST"; + break; + case FLASH_MAN_BM: + mfct = "Bright Microelectonics"; + break; + case FLASH_MAN_INTEL: + mfct = "Intel"; + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + type = "AM29F040B (512K * 8, uniform sector size)"; + break; + case FLASH_AM400B: + type = "AM29LV400B (4 Mbit, bottom boot sect)"; + break; + case FLASH_AM400T: + type = "AM29LV400T (4 Mbit, top boot sector)"; + break; + case FLASH_AM800B: + type = "AM29LV800B (8 Mbit, bottom boot sect)"; + break; + case FLASH_AM800T: + type = "AM29LV800T (8 Mbit, top boot sector)"; + break; + case FLASH_AM160T: + type = "AM29LV160T (16 Mbit, top boot sector)"; + break; + case FLASH_AM320B: + type = "AM29LV320B (32 Mbit, bottom boot sect)"; + break; + case FLASH_AM320T: + type = "AM29LV320T (32 Mbit, top boot sector)"; + break; + case FLASH_STM800AB: + type = "M29W800AB (8 Mbit, bottom boot sect)"; + break; + case FLASH_SST800A: + type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; + break; + case FLASH_SST160A: + type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; + break; + } + } + + printf ("\n Brand: %s Type: %s\n" + " Size: %lu KB in %d Sectors\n", + mfct, type, info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; i++) { + unsigned long size; + unsigned int erased; + unsigned long *flash = (unsigned long *) info->start[i]; + + /* + * Check if whole sector is erased + */ + size = (i != (info->sector_count - 1)) ? + (info->start[i + 1] - info->start[i]) >> 2 : + (info->start[0] + info->size - info->start[i]) >> 2; + + for (flash = (unsigned long *) info->start[i], erased = 1; + (flash != (unsigned long *) info->start[i] + size) + && erased; flash++) + erased = *flash == ~0x0UL; + + printf ("%s %08lX %s %s", + (i % 5) ? "" : "\n ", + info->start[i], + erased ? "E" : " ", info->protect[i] ? "RO" : " "); + } + + puts ("\n"); + return; +} + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + unsigned char sh8b; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) + && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FLASH_WORD_SIZE *) (info->start[0] + + ((info->start[sect] - + info->start[0]) << sh8b)); + if (info->flash_id & FLASH_MAN_SST) { + addr[ADDR0 << sh8b] = + (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = + (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0 << sh8b] = + (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0 << sh8b] = + (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = + (FLASH_WORD_SIZE) 0x00550055; + addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ + udelay (30000); /* wait 30 ms */ + } else + addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - + info-> + start[0]) << sh8b)); + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; + volatile FLASH_WORD_SIZE *dest2; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int flag; + int i; + unsigned char sh8b; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) + && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; + + dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + + info->start[0]); + + /* Check if Flash is (sufficiently) erased */ + if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i << sh8b] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c new file mode 100644 index 0000000..daab833 --- /dev/null +++ b/board/hidden_dragon/hidden_dragon.c @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2004 + * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com + * + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int checkboard (void) +{ + /*TODO: Check processor type */ + + puts ( "Board: Hidden Dragon " +#ifdef CONFIG_MPC8240 + "8240" +#endif +#ifdef CONFIG_MPC8245 + "8245" +#endif + " ##Test not implemented yet##\n"); + /* TODO: Implement board test */ + return 0; +} + +long int initdram (int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_hidden_dragon_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_hidden_dragon_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} diff --git a/board/hidden_dragon/speed.h b/board/hidden_dragon/speed.h new file mode 100644 index 0000000..b66393b --- /dev/null +++ b/board/hidden_dragon/speed.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*----------------------------------------------------------------------- + * Timer value for timer 2, ICLK = 10 + * + * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) + * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 + * + * SPEED_FCOUNT2 timer 2 counting frequency + * GCLK CPU clock + * SPEED_TMR2_PS prescaler + */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ + +/*----------------------------------------------------------------------- + * Timer value for PIT + * + * PIT_TIME = SPEED_PITC / PITRTCLK + * PITRTCLK = 8192 + */ +#define SPEED_PITC (82 << 16) /* start counting from 82 */ + +/* + * The new value for PTA is calculated from + * + * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) + * + * gclk CPU clock (not bus clock !) + * Trefresh Refresh cycle * 4 (four word bursts used) + * DFBRG For normal mode (no clock reduction) always 0 + * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) + * NCS Number of SDRAM banks (chip selects) on this UPM. + */ diff --git a/board/hidden_dragon/u-boot.lds b/board/hidden_dragon/u-boot.lds new file mode 100644 index 0000000..2a5cd2e --- /dev/null +++ b/board/hidden_dragon/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hmi1001/Makefile b/board/hmi1001/Makefile new file mode 100644 index 0000000..ed36ea7 --- /dev/null +++ b/board/hmi1001/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/hmi1001/config.mk b/board/hmi1001/config.mk new file mode 100644 index 0000000..51e8e84c --- /dev/null +++ b/board/hmi1001/config.mk @@ -0,0 +1,41 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# INKA 4X0 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFE00000 boot high +# +# 0x00100000 boot from RAM (for testing only) +# + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +#TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c new file mode 100644 index 0000000..237e863 --- /dev/null +++ b/board/hmi1001/hmi1001.c @@ -0,0 +1,297 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + +/* return dramsize + dramsize2; */ + return dramsize; +} + +int checkboard (void) +{ + puts ("Board: HMI1001\n"); + return 0; +} + +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +#define S1_ROT 0xf0 +#define S2_Q 0x40 +#define S2_M 0x20 + +struct kbd_data_t { + char s1; + char s2; +}; + +struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) +{ + kbd_data->s1 = *((volatile uchar*)(CFG_STATUS1_BASE)); + kbd_data->s2 = *((volatile uchar*)(CFG_STATUS2_BASE)); + + return kbd_data; +} + +static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str) +{ + char s1 = str[0]; + char s2; + + if (s1 >= '0' && s1 <= '9') + s1 -= '0'; + else if (s1 >= 'a' && s1 <= 'f') + s1 = s1 - 'a' + 10; + else if (s1 >= 'A' && s1 <= 'F') + s1 = s1 - 'A' + 10; + else + return -1; + + if (((S1_ROT & kbd_data->s1) >> 4) != s1) + return -1; + + s2 = (S2_Q | S2_M) & kbd_data->s2; + + switch (str[1]) { + case 'q': + case 'Q': + if (s2 == S2_Q) + return -1; + break; + case 'm': + case 'M': + if (s2 == S2_M) + return -1; + break; + case '\0': + if (s2 == (S2_Q | S2_M)) + return 0; + default: + return -1; + } + + if (str[2]) + return -1; + + return 0; +} + +static uchar *key_match (const struct kbd_data_t *kbd_data) +{ + uchar magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + uchar *kbd_magic_keys; + + /* + * The following string defines the characters that can be appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix = kbd_magic_keys; *suffix || + suffix == kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); + + if (compare_magic(kbd_data, getenv(magic)) == 0) { + uchar cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv (cmd_name); + + return (cmd); + } + } + + return (NULL); +} + +#endif /* CONFIG_PREBOOT */ + +int misc_init_r (void) +{ +#ifdef CONFIG_PREBOOT + struct kbd_data_t kbd_data; + /* Decode keys */ + uchar *str = strdup (key_match (get_keys (&kbd_data))); + /* Set or delete definition */ + setenv ("preboot", str); + free (str); +#endif /* CONFIG_PREBOOT */ + + return 0; +} + +int board_early_init_r (void) +{ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + *(vu_long *)MPC5XXX_BOOTCS_START = + *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); + *(vu_long *)MPC5XXX_BOOTCS_STOP = + *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); + return 0; +} +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif diff --git a/board/hmi1001/u-boot.lds b/board/hmi1001/u-boot.lds new file mode 100644 index 0000000..123a14c --- /dev/null +++ b/board/hmi1001/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xxx/start.o (.text) + cpu/mpc5xxx/traps.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hymod/Makefile b/board/hymod/Makefile new file mode 100644 index 0000000..b52af9a --- /dev/null +++ b/board/hymod/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c new file mode 100644 index 0000000..0596fa4 --- /dev/null +++ b/board/hymod/bsp.c @@ -0,0 +1,407 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01 + */ + +#include +#include +#include +#include + +/*----------------------------------------------------------------------- + * Board Special Commands: FPGA load/store, EEPROM erase + */ + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +#define LOAD_SUCCESS 0 +#define LOAD_FAIL_NOCONF 1 +#define LOAD_FAIL_NOINIT 2 +#define LOAD_FAIL_NODONE 3 + +#define STORE_SUCCESS 0 + +/* + * Programming the Hymod FPGAs + * + * The 8260 io port config table is set up so that the INIT pin is + * held Low (Open Drain output 0) - this will delay the automatic + * Power-On config until INIT is released (by making it an input). + * + * If the FPGA has been programmed before, then the assertion of PROGRAM + * will initiate configuration (i.e. it begins clearing the RAM). + * + * When the FPGA is ready to receive configuration data (either after + * releasing INIT after Power-On, or after asserting PROGRAM), it will + * pull INIT high. + * + * Notes from Paul Dunn: + * + * 1. program pin should be forced low for >= 300ns + * (about 20 bus clock cycles minimum). + * + * 2. then wait for init to go high, which signals + * that the FPGA has cleared its internal memory + * and is ready to load + * + * 3. perform load writes of entire config file + * + * 4. wait for done to go high, which should be + * within a few bus clock cycles. If done has not + * gone high after reasonable period, then load + * has not worked (wait several ms?) + */ + +int +fpga_load (int mezz, uchar *addr, ulong size) +{ + DECLARE_GLOBAL_DATA_PTR; + + hymod_conf_t *cp = &gd->bd->bi_hymod_conf; + xlx_info_t *fp; + xlx_iopins_t *fpgaio; + volatile uchar *fpgabase; + volatile uint cnt; + uchar *eaddr = addr + size; + int result; + + if (mezz) + fp = &cp->mezz.xlx[0]; + else + fp = &cp->main.xlx[0]; + + if (!fp->mmap.prog.exists) + return (LOAD_FAIL_NOCONF); + + fpgabase = (uchar *)fp->mmap.prog.base; + fpgaio = &fp->iopins; + + /* set enable HIGH if required */ + if (fpgaio->enable_pin.flag) + iopin_set_high (&fpgaio->enable_pin); + + /* ensure INIT is released (set it to be an input) */ + iopin_set_in (&fpgaio->init_pin); + + /* toggle PROG Low then High (will already be Low after Power-On) */ + iopin_set_low (&fpgaio->prog_pin); + udelay (1); /* minimum 300ns - 1usec should do it */ + iopin_set_high (&fpgaio->prog_pin); + + /* wait for INIT High */ + cnt = 0; + while (!iopin_is_high (&fpgaio->init_pin)) + if (++cnt == 10000000) { + result = LOAD_FAIL_NOINIT; + goto done; + } + + /* write configuration data */ + while (addr < eaddr) + *fpgabase = *addr++; + + /* wait for DONE High */ + cnt = 0; + while (!iopin_is_high (&fpgaio->done_pin)) + if (++cnt == 100000000) { + result = LOAD_FAIL_NODONE; + goto done; + } + + /* success */ + result = LOAD_SUCCESS; + + done: + + if (fpgaio->enable_pin.flag) + iopin_set_low (&fpgaio->enable_pin); + + return (result); +} + +/* ------------------------------------------------------------------------- */ +int +do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + uchar *addr, *save_addr; + ulong size; + int mezz, arg, result; + + switch (argc) { + + case 0: + case 1: + break; + + case 2: + if (strcmp (argv[1], "info") == 0) { + printf ("\nHymod FPGA Info...\n"); + printf ("\t\t\t\tAddress\t\tSize\n"); + printf ("\tMain Configuration:\t0x%08x\t%d\n", + FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE); + printf ("\tMain Register:\t\t0x%08x\t%d\n", + FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE); + printf ("\tMain Port:\t\t0x%08x\t%d\n", + FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE); + printf ("\tMezz Configuration:\t0x%08x\t%d\n", + FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE); + return 0; + } + break; + + case 3: + if (strcmp (argv[1], "store") == 0) { + addr = (uchar *) simple_strtoul (argv[2], NULL, 16); + + save_addr = addr; +#if 0 + /* fpga readback unimplemented */ + while (more readback data) + *addr++ = *fpga; + result = error ? STORE_FAIL_XXX : STORE_SUCCESS; +#else + result = STORE_SUCCESS; +#endif + + if (result == STORE_SUCCESS) { + printf ("SUCCEEDED (%d bytes)\n", + addr - save_addr); + return 0; + } else + printf ("FAILED (%d bytes)\n", + addr - save_addr); + return 1; + } + break; + + case 4: + if (strcmp (argv[1], "tftp") == 0) { + copy_filename (BootFile, argv[2], sizeof (BootFile)); + load_addr = simple_strtoul (argv[3], NULL, 16); + NetBootFileXferSize = 0; + + if (NetLoop (TFTP) <= 0) { + printf ("tftp transfer failed - aborting " + "fgpa load\n"); + return 1; + } + + if (NetBootFileXferSize == 0) { + printf ("can't determine file size - " + "aborting fpga load\n"); + return 1; + } + + printf ("File transfer succeeded - " + "beginning fpga load..."); + + result = fpga_load (0, (uchar *) load_addr, + NetBootFileXferSize); + + if (result == LOAD_SUCCESS) { + printf ("SUCCEEDED\n"); + return 0; + } else if (result == LOAD_FAIL_NOCONF) + printf ("FAILED (no CONF)\n"); + else if (result == LOAD_FAIL_NOINIT) + printf ("FAILED (no INIT)\n"); + else + printf ("FAILED (no DONE)\n"); + return 1; + + } + /* fall through ... */ + + case 5: + if (strcmp (argv[1], "load") == 0) { + if (argc == 5) { + if (strcmp (argv[2], "main") == 0) + mezz = 0; + else if (strcmp (argv[2], "mezz") == 0) + mezz = 1; + else { + printf ("FPGA type must be either " + "`main' or `mezz'\n"); + return 1; + } + arg = 3; + } else { + mezz = 0; + arg = 2; + } + + addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16); + size = (ulong) simple_strtoul (argv[arg], NULL, 16); + + result = fpga_load (mezz, addr, size); + + if (result == LOAD_SUCCESS) { + printf ("SUCCEEDED\n"); + return 0; + } else if (result == LOAD_FAIL_NOCONF) + printf ("FAILED (no CONF)\n"); + else if (result == LOAD_FAIL_NOINIT) + printf ("FAILED (no INIT)\n"); + else + printf ("FAILED (no DONE)\n"); + return 1; + } + break; + + default: + break; + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} +U_BOOT_CMD( + fpga, 6, 1, do_fpga, + "fpga - FPGA sub-system\n", + "load [type] addr size\n" + " - write the configuration data at memory address `addr',\n" + " size `size' bytes, into the FPGA of type `type' (either\n" + " `main' or `mezz', default `main'). e.g.\n" + " `fpga load 100000 7d8f'\n" + " loads the main FPGA with config data at address 100000\n" + " HEX, size 7d8f HEX (32143 DEC) bytes\n" + "fpga tftp file addr\n" + " - transfers `file' from the tftp server into memory at\n" + " address `addr', then writes the entire file contents\n" + " into the main FPGA\n" + "fpga store addr\n" + " - read configuration data from the main FPGA (the mezz\n" + " FPGA is write-only), into address `addr'. There must be\n" + " enough memory available at `addr' to hold all the config\n" + " data - the size of which is determined by VC:???\n" + "fpga info\n" + " - print information about the Hymod FPGA, namely the\n" + " memory addresses at which the four FPGA local bus\n" + " address spaces appear in the physical address space\n" +); +/* ------------------------------------------------------------------------- */ +int +do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + uchar data[HYMOD_EEPROM_SIZE]; + uint addr = CFG_I2C_EEPROM_ADDR; + + switch (argc) { + + case 1: + addr |= HYMOD_EEOFF_MAIN; + break; + + case 2: + if (strcmp (argv[1], "main") == 0) { + addr |= HYMOD_EEOFF_MAIN; + break; + } + if (strcmp (argv[1], "mezz") == 0) { + addr |= HYMOD_EEOFF_MEZZ; + break; + } + /* fall through ... */ + + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + memset (data, 0, HYMOD_EEPROM_SIZE); + + eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE); + + return 0; +} +U_BOOT_CMD( + eeclear, 1, 0, do_eecl, + "eeclear - Clear the eeprom on a Hymod board \n", + "[type]\n" + " - write zeroes into the EEPROM on the board of type `type'\n" + " (`type' is either `main' or `mezz' - default `main')\n" + " Note: the EEPROM write enable jumper must be installed\n" +); + +/* ------------------------------------------------------------------------- */ + +int +do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if 0 + int rc; +#endif +#ifdef CONFIG_ETHER_LOOPBACK_TEST + extern void eth_loopback_test (void); +#endif /* CONFIG_ETHER_LOOPBACK_TEST */ + + printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n"); + +#if 0 + /* Load FPGA with test program */ + + printf ("Loading test FPGA program ..."); + + rc = fpga_load (0, test_bitfile, sizeof (test_bitfile)); + + switch (rc) { + + case LOAD_SUCCESS: + printf (" SUCCEEDED\n"); + break; + + case LOAD_FAIL_NOCONF: + printf (" FAILED (no configuration space defined)\n"); + return 1; + + case LOAD_FAIL_NOINIT: + printf (" FAILED (timeout - no INIT signal seen)\n"); + return 1; + + case LOAD_FAIL_NODONE: + printf (" FAILED (timeout - no DONE signal seen)\n"); + return 1; + + default: + printf (" FAILED (unknown return code from fpga_load\n"); + return 1; + } + + /* run Local Bus <=> Xilinx tests */ + + /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */ + + /* run SDRAM test */ +#endif + +#ifdef CONFIG_ETHER_LOOPBACK_TEST + /* run Ethernet test */ + eth_loopback_test (); +#endif /* CONFIG_ETHER_LOOPBACK_TEST */ + + return 0; +} + +#endif /* CFG_CMD_BSP */ + +/* ------------------------------------------------------------------------- */ diff --git a/board/hymod/config.mk b/board/hymod/config.mk new file mode 100644 index 0000000..0a9985f --- /dev/null +++ b/board/hymod/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# HYMOD boards +# + +TEXT_BASE = 0x40000000 + +PLATFORM_CPPFLAGS += -I$(TOPDIR) + +OBJCFLAGS = --remove-section=.ppcenv diff --git a/board/hymod/eeprom.c b/board/hymod/eeprom.c new file mode 100644 index 0000000..c9b9b18 --- /dev/null +++ b/board/hymod/eeprom.c @@ -0,0 +1,694 @@ +/* + * (C) Copyright 2001 + * Murray Jensen, CSIRO-MIT, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* imports from fetch.c */ +extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); + +/* imports from input.c */ +extern int hymod_get_serno (const char *); + +/* this is relative to the root of the server's tftp directory */ +static char *def_bddb_cfgdir = "/hymod/bddb"; + +static int +hymod_eeprom_load (int which, hymod_eeprom_t *ep) +{ + unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \ + (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); + unsigned offset = 0; + uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp; + hymod_eehdr_t hdr; + ulong len, crc; + + memset (ep, 0, sizeof *ep); + + eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr)); + offset += sizeof (hdr); + + if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER || + (len = hdr.len) > HYMOD_EEPROM_MAXLEN) + return (0); + + eeprom_read (dev_addr, offset, data, len); + offset += len; + + eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong)); + offset += sizeof (ulong); + + if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc) + return (0); + + ep->ver = hdr.ver; + dp = data; edp = dp + len; + + for (;;) { + ulong rtyp; + uchar rlen, *rdat; + + rtyp = *dp++; + if ((rtyp & 0x80) == 0) + rlen = *dp++; + else { + uchar islarge = rtyp & 0x40; + + rtyp = ((rtyp & 0x3f) << 8) | *dp++; + if (islarge) { + rtyp = (rtyp << 8) | *dp++; + rtyp = (rtyp << 8) | *dp++; + } + + rlen = *dp++; + rlen = (rlen << 8) | *dp++; + if (islarge) { + rlen = (rlen << 8) | *dp++; + rlen = (rlen << 8) | *dp++; + } + } + + if (rtyp == 0) + break; + + rdat = dp; + dp += rlen; + + if (dp > edp) /* error? */ + break; + + switch (rtyp) { + + case HYMOD_EEREC_SERNO: /* serial number */ + if (rlen == sizeof (ulong)) + ep->serno = \ + ((ulong)rdat[0] << 24) | \ + ((ulong)rdat[1] << 16) | \ + ((ulong)rdat[2] << 8) | \ + (ulong)rdat[3]; + break; + + case HYMOD_EEREC_DATE: /* date */ + if (rlen == sizeof (hymod_date_t)) { + ep->date.year = ((ushort)rdat[0] << 8) | \ + (ushort)rdat[1]; + ep->date.month = rdat[2]; + ep->date.day = rdat[3]; + } + break; + + case HYMOD_EEREC_BATCH: /* batch */ + if (rlen <= HYMOD_MAX_BATCH) + memcpy (ep->batch, rdat, ep->batchlen = rlen); + break; + + case HYMOD_EEREC_TYPE: /* board type */ + if (rlen == 1) + ep->bdtype = *rdat; + break; + + case HYMOD_EEREC_REV: /* board revision */ + if (rlen == 1) + ep->bdrev = *rdat; + break; + + case HYMOD_EEREC_SDRAM: /* sdram size(s) */ + if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) { + int i; + + for (i = 0; i < rlen; i++) + ep->sdramsz[i] = rdat[i]; + ep->nsdram = rlen; + } + break; + + case HYMOD_EEREC_FLASH: /* flash size(s) */ + if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) { + int i; + + for (i = 0; i < rlen; i++) + ep->flashsz[i] = rdat[i]; + ep->nflash = rlen; + } + break; + + case HYMOD_EEREC_ZBT: /* zbt ram size(s) */ + if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) { + int i; + + for (i = 0; i < rlen; i++) + ep->zbtsz[i] = rdat[i]; + ep->nzbt = rlen; + } + break; + + case HYMOD_EEREC_XLXTYP: /* xilinx fpga type(s) */ + if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { + int i; + + for (i = 0; i < rlen; i++) + ep->xlx[i].type = rdat[i]; + ep->nxlx = rlen; + } + break; + + case HYMOD_EEREC_XLXSPD: /* xilinx fpga speed(s) */ + if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { + int i; + + for (i = 0; i < rlen; i++) + ep->xlx[i].speed = rdat[i]; + } + break; + + case HYMOD_EEREC_XLXTMP: /* xilinx fpga temperature(s) */ + if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { + int i; + + for (i = 0; i < rlen; i++) + ep->xlx[i].temp = rdat[i]; + } + break; + + case HYMOD_EEREC_XLXGRD: /* xilinx fpga grade(s) */ + if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { + int i; + + for (i = 0; i < rlen; i++) + ep->xlx[i].grade = rdat[i]; + } + break; + + case HYMOD_EEREC_CPUTYP: /* CPU type */ + if (rlen == 1) + ep->mpc.type = *rdat; + break; + + case HYMOD_EEREC_CPUSPD: /* CPU speed */ + if (rlen == 1) + ep->mpc.cpuspd = *rdat; + break; + + case HYMOD_EEREC_CPMSPD: /* CPM speed */ + if (rlen == 1) + ep->mpc.cpmspd = *rdat; + break; + + case HYMOD_EEREC_BUSSPD: /* bus speed */ + if (rlen == 1) + ep->mpc.busspd = *rdat; + break; + + case HYMOD_EEREC_HSTYPE: /* hs-serial chip type */ + if (rlen == 1) + ep->hss.type = *rdat; + break; + + case HYMOD_EEREC_HSCHIN: /* num hs-serial input chans */ + if (rlen == 1) + ep->hss.nchin = *rdat; + break; + + case HYMOD_EEREC_HSCHOUT: /* num hs-serial output chans */ + if (rlen == 1) + ep->hss.nchout = *rdat; + break; + + default: /* ignore */ + break; + } + } + + return (1); +} + +/* maps an ascii "name=value" into a binary eeprom data record */ +typedef + struct _eerec_map { + char *name; + uint type; + uchar *(*handler) \ + (struct _eerec_map *, uchar *, uchar *, uchar *); + uint length; + uint maxlen; + } +eerec_map_t; + +static uchar * +uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) +{ + char *eval; + ulong lval; + + lval = simple_strtol ((char *)val, &eval, 10); + + if ((uchar *)eval == val || *eval != '\0') { + printf ("%s rec (%s) is not a valid uint\n", rp->name, val); + return (NULL); + } + + if (dp + 2 + rp->length > edp) { + printf ("can't fit %s rec into eeprom\n", rp->name); + return (NULL); + } + + *dp++ = rp->type; + *dp++ = rp->length; + + switch (rp->length) { + + case 1: + if (lval >= 256) { + printf ("%s rec value (%lu) out of range (0-255)\n", + rp->name, lval); + return (NULL); + } + *dp++ = lval; + break; + + case 2: + if (lval >= 65536) { + printf ("%s rec value (%lu) out of range (0-65535)\n", + rp->name, lval); + return (NULL); + } + *dp++ = lval >> 8; + *dp++ = lval; + break; + + case 4: + *dp++ = lval >> 24; + *dp++ = lval >> 16; + *dp++ = lval >> 8; + *dp++ = lval; + break; + + default: + printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length); + return (NULL); + } + + return (dp); +} + +static uchar * +date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) +{ + hymod_date_t date; + char *p = (char *)val; + char *ep; + ulong lval; + + lval = simple_strtol (p, &ep, 10); + if (ep == p || *ep++ != '-') { +bad_date: + printf ("%s rec (%s) is not a valid date\n", rp->name, val); + return (NULL); + } + if (lval >= 65536) + goto bad_date; + date.year = lval; + + lval = simple_strtol (p = ep, &ep, 10); + if (ep == p || *ep++ != '-' || lval == 0 || lval > 12) + goto bad_date; + date.month = lval; + + lval = simple_strtol (p = ep, &ep, 10); + if (ep == p || *ep != '\0' || lval == 0 || lval > 31) + goto bad_date; + date.day = lval; + + if (dp + 2 + rp->length > edp) { + printf ("can't fit %s rec into eeprom\n", rp->name); + return (NULL); + } + + *dp++ = rp->type; + *dp++ = rp->length; + *dp++ = date.year >> 8; + *dp++ = date.year; + *dp++ = date.month; + *dp++ = date.day; + + return (dp); +} + +static uchar * +string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) +{ + uint len; + + if ((len = strlen ((char *)val)) > rp->maxlen) { + printf ("%s rec (%s) string is too long (%d>%d)\n", + rp->name, val, len, rp->maxlen); + return (NULL); + } + + if (dp + 2 + len > edp) { + printf ("can't fit %s rec into eeprom\n", rp->name); + return (NULL); + } + + *dp++ = rp->type; + *dp++ = len; + memcpy (dp, val, len); + dp += len; + + return (dp); +} + +static uchar * +bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) +{ + uchar bytes[HYMOD_MAX_BYTES], nbytes, *p; + char *ep; + + for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) { + ulong lval; + + lval = simple_strtol ((char *)p, &ep, 10); + if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \ + lval >= 256) { + printf ("%s rec (%s) byte array has invalid uint\n", + rp->name, val); + return (NULL); + } + if (nbytes >= HYMOD_MAX_BYTES) { + printf ("%s rec (%s) byte array too long\n", + rp->name, val); + return (NULL); + } + bytes[nbytes++] = lval; + + if (*ep != '\0') + ep++; + } + + if (dp + 2 + nbytes > edp) { + printf ("can't fit %s rec into eeprom\n", rp->name); + return (NULL); + } + + *dp++ = rp->type; + *dp++ = nbytes; + memcpy (dp, bytes, nbytes); + dp += nbytes; + + return (dp); +} + +static eerec_map_t eerec_map[] = { + /* name type handler len max */ + { "serno", HYMOD_EEREC_SERNO, uint_handler, 4, 0 }, + { "date", HYMOD_EEREC_DATE, date_handler, 4, 0 }, + { "batch", HYMOD_EEREC_BATCH, string_handler, 0, HYMOD_MAX_BATCH }, + { "type", HYMOD_EEREC_TYPE, uint_handler, 1, 0 }, + { "rev", HYMOD_EEREC_REV, uint_handler, 1, 0 }, + { "sdram", HYMOD_EEREC_SDRAM, bytes_handler, 0, HYMOD_MAX_SDRAM }, + { "flash", HYMOD_EEREC_FLASH, bytes_handler, 0, HYMOD_MAX_FLASH }, + { "zbt", HYMOD_EEREC_ZBT, bytes_handler, 0, HYMOD_MAX_ZBT }, + { "xlxtyp", HYMOD_EEREC_XLXTYP, bytes_handler, 0, HYMOD_MAX_XLX }, + { "xlxspd", HYMOD_EEREC_XLXSPD, bytes_handler, 0, HYMOD_MAX_XLX }, + { "xlxtmp", HYMOD_EEREC_XLXTMP, bytes_handler, 0, HYMOD_MAX_XLX }, + { "xlxgrd", HYMOD_EEREC_XLXGRD, bytes_handler, 0, HYMOD_MAX_XLX }, + { "cputyp", HYMOD_EEREC_CPUTYP, uint_handler, 1, 0 }, + { "cpuspd", HYMOD_EEREC_CPUSPD, uint_handler, 1, 0 }, + { "cpmspd", HYMOD_EEREC_CPMSPD, uint_handler, 1, 0 }, + { "busspd", HYMOD_EEREC_BUSSPD, uint_handler, 1, 0 }, + { "hstype", HYMOD_EEREC_HSTYPE, uint_handler, 1, 0 }, + { "hschin", HYMOD_EEREC_HSCHIN, uint_handler, 1, 0 }, + { "hschout", HYMOD_EEREC_HSCHOUT, uint_handler, 1, 0 }, +}; + +static int neerecs = sizeof eerec_map / sizeof eerec_map[0]; + +static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp; + +static int +eerec_callback (uchar *name, uchar *val) +{ + eerec_map_t *rp; + + for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++) + if (strcmp ((char *)name, rp->name) == 0) + break; + + if (rp >= &eerec_map[neerecs]) + return (0); + + if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL) + return (0); + + return (1); +} + +static int +hymod_eeprom_fetch(int which, char *filename, ulong addr) +{ + unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \ + (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); + hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0]; + ulong crc; + + memset (hp, 0, sizeof *hp); + hp->id = HYMOD_EEPROM_ID; + hp->ver = HYMOD_EEPROM_VER; + + dp = sdp = (uchar *)(hp + 1); + edp = dp + HYMOD_EEPROM_MAXLEN; + + if (fetch_and_parse (filename, addr, eerec_callback) == 0) + return (0); + + hp->len = dp - sdp; + + crc = crc32 (0, data, dp - data); + memcpy (dp, &crc, sizeof (ulong)); + dp += sizeof (ulong); + + eeprom_write (dev_addr, 0, data, dp - data); + + return (1); +} + +static char *type_vals[] = { + "NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY" +}; + +static char *xlxtyp_vals[] = { + "NONE", "XCV300E", "XCV400E", "XCV600E" +}; + +static char *xlxspd_vals[] = { + "NONE", "6", "7", "8" +}; + +static char *xlxtmp_vals[] = { + "NONE", "COM", "IND" +}; + +static char *xlxgrd_vals[] = { + "NONE", "NORMAL", "ENGSAMP" +}; + +static char *cputyp_vals[] = { + "NONE", "MPC8260" +}; + +static char *clk_vals[] = { + "NONE", "33", "66", "100", "133", "166", "200" +}; + +static char *hstype_vals[] = { + "NONE", "AMCC-S2064A" +}; + +static void +print_mem (char *l, char *s, uchar n, uchar a[]) +{ + if (n > 0) { + if (n == 1) + printf ("%s%dMB %s", s, 1 << (a[0] - 20), l); + else { + ulong t = 0; + int i; + + for (i = 0; i < n; i++) + t += 1 << (a[i] - 20); + + printf ("%s%luMB %s (%d banks:", s, t, l, n); + + for (i = 0; i < n; i++) + printf ("%dMB%s", + 1 << (a[i] - 20), + (i == n - 1) ? ")" : ","); + } + } + else + printf ("%sNO %s", s, l); +} + +void +hymod_eeprom_print (hymod_eeprom_t *ep) +{ + int i; + + printf (" Hymod %s board, rev %03d\n", + type_vals[ep->bdtype], ep->bdrev); + + printf (" serial #: %010lu, date %04d-%02d-%02d", + ep->serno, ep->date.year, ep->date.month, ep->date.day); + if (ep->batchlen > 0) + printf (", batch \"%.*s\"", ep->batchlen, ep->batch); + puts ("\n"); + + switch (ep->bdtype) { + + case HYMOD_BDTYPE_IO: + case HYMOD_BDTYPE_CLP: + case HYMOD_BDTYPE_DSP: + printf (" Motorola %s CPU, speeds: %s/%s/%s", + cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd], + clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]); + + print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz); + + print_mem ("FLASH", ", ", ep->nflash, ep->flashsz); + + puts ("\n"); + + print_mem ("ZBT", " ", ep->nzbt, ep->zbtsz); + + if (ep->nxlx > 0) { + hymod_xlx_t *xp; + + if (ep->nxlx == 1) { + xp = &ep->xlx[0]; + printf (", Xilinx %s FPGA (%s/%s/%s)", + xlxtyp_vals[xp->type], + xlxspd_vals[xp->speed], + xlxtmp_vals[xp->temp], + xlxgrd_vals[xp->grade]); + } + else { + printf (", %d Xilinx FPGAs (", ep->nxlx); + for (i = 0; i < ep->nxlx; i++) { + xp = &ep->xlx[i]; + printf ("%s[%s/%s/%s]%s", + xlxtyp_vals[xp->type], + xlxspd_vals[xp->speed], + xlxtmp_vals[xp->temp], + xlxgrd_vals[xp->grade], + (i == ep->nxlx - 1) ? ")" : ", "); + } + } + } + else + puts(", NO FPGAs"); + + puts ("\n"); + + if (ep->hss.type > 0) + printf (" High Speed Serial: " + "%s, %d input%s, %d output%s\n", + hstype_vals[ep->hss.type], + ep->hss.nchin, + (ep->hss.nchin == 1 ? "" : "s"), + ep->hss.nchout, + (ep->hss.nchout == 1 ? "" : "s")); + break; + + case HYMOD_BDTYPE_INPUT: + case HYMOD_BDTYPE_ALTINPUT: + case HYMOD_BDTYPE_DISPLAY: + break; + + default: + /* crap! */ + printf (" UNKNOWN BOARD TYPE: %d\n", ep->bdtype); + break; + } +} + +int +hymod_eeprom_read (int which, hymod_eeprom_t *ep) +{ + char *label = which ? "mezzanine" : "main"; + unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \ + (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); + char filename[50], prompt[50], *dir; + int serno, count = 0, rc; + + rc = eeprom_probe (dev_addr, 0); + + if (rc > 0) { + printf ("*** probe for eeprom failed with code %d\n", rc); + return (0); + } + + if (rc < 0) + return (rc); + + sprintf (prompt, "Enter %s board serial number: ", label); + + if ((dir = getenv ("bddb_cfgdir")) == NULL) + dir = def_bddb_cfgdir; + + for (;;) { + int rc; + + if (hymod_eeprom_load (which, ep)) + return (1); + + printf ("*** %s board EEPROM contents are %sinvalid\n", + label, count == 0 ? "" : "STILL "); + + puts ("*** will fetch from server (Ctrl-C to abort)\n"); + + serno = hymod_get_serno (prompt); + + if (serno < 0) { + if (serno == -1) + puts ("\n*** interrupted!"); + else + puts ("\n*** timeout!"); + puts (" - ignoring eeprom contents\n"); + return (0); + } + + sprintf (filename, "%s/%010d.cfg", dir, serno); + + printf ("*** fetching %s board EEPROM contents from server\n", + label); + + rc = hymod_eeprom_fetch (which, filename, CFG_LOAD_ADDR); + + if (rc == 0) { + puts ("*** fetch failed - ignoring eeprom contents\n"); + return (0); + } + + count++; + } +} diff --git a/board/hymod/env.c b/board/hymod/env.c new file mode 100644 index 0000000..f9e1421 --- /dev/null +++ b/board/hymod/env.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2003 + * Murray Jensen, CSIRO-MIT, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* imports from fetch.c */ +extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); + +/* this is relative to the root of the server's tftp directory */ +static char *def_global_env_path = "/hymod/global_env"; + +static int +env_callback (uchar *name, uchar *value) +{ + DECLARE_GLOBAL_DATA_PTR; + + hymod_conf_t *cp = &gd->bd->bi_hymod_conf; + char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver; + int override = 1, append = 0, remove = 0, nnl, ovl, nvl; + + nn = (char *)name; + + if (*nn == '-') { + override = 0; + nn++; + } + + while (*nn == ' ' || *nn == '\t') + nn++; + + if ((nnl = strlen (nn)) == 0) { + printf ("Empty name in global env file\n"); + return (0); + } + + if ((c = nn[nnl - 1]) == '+' || c == '-') { + if (c == '+') + append = 1; + else + remove = 1; + nn[--nnl] = '\0'; + } + + while (nnl > 0 && ((c = nn[nnl - 1]) == ' ' || c == '\t')) + nn[--nnl] = '\0'; + if (nnl == 0) { + printf ("Empty name in global env file\n"); + return (0); + } + + p = (char *)value; + q = nv; + + while ((c = *p) == ' ' || c == '\t') + p++; + + nvl = strlen (p); + while (nvl > 0 && ((c = p[nvl - 1]) == ' ' || c == '\t')) + p[--nvl] = '\0'; + + while ((*q = *p++) != '\0') { + if (*q == '%') { + switch (*p++) { + + case '\0': /* whoops - back up */ + p--; + break; + + case '%': /* a single percent character */ + q++; + break; + + case 's': /* main board serial number as string */ + q += sprintf (q, "%010lu", + cp->main.eeprom.serno); + break; + + case 'S': /* main board serial number as number */ + q += sprintf (q, "%lu", cp->main.eeprom.serno); + break; + + default: /* ignore any others */ + break; + } + } + else + q++; + } + + if ((nvl = q - nv) == 0) { + setenv (nn, NULL); + return (1); + } + + if ((curver = getenv ("global_env_version")) == NULL) + curver = "unknown"; + + if ((newver = getenv ("new_genv_version")) == NULL || \ + strcmp (curver, newver) == 0) { + if (strcmp (nn, "version") == 0) + setenv ("new_genv_version", nv); + return (1); + } + + if ((p = getenv (nn)) != NULL) { + + strcpy (ov, p); + ovl = strlen (ov); + + if (append) { + + if (strstr (ov, nv) == NULL) { + + printf ("Appending '%s' to env var '%s'\n", + nv, nn); + + while (nvl >= 0) { + nv[ovl + 1 + nvl] = nv[nvl]; + nvl--; + } + + nv[ovl] = ' '; + + while (--ovl >= 0) + nv[ovl] = ov[ovl]; + + setenv (nn, nv); + } + + return (1); + } + + if (remove) { + + if (strstr (ov, nv) != NULL) { + + printf ("Removing '%s' from env var '%s'\n", + nv, nn); + + while ((p = strstr (ov, nv)) != NULL) { + q = p + nvl; + if (*q == ' ') + q++; + strcpy(p, q); + } + + setenv (nn, ov); + } + + return (1); + } + + if (!override || strcmp (ov, nv) == 0) + return (1); + + printf ("Re-setting env cmd '%s' from '%s' to '%s'\n", + nn, ov, nv); + } + else + printf ("Setting env cmd '%s' to '%s'\n", nn, nv); + + setenv (nn, nv); + return (1); +} + +void +hymod_check_env (void) +{ + char *p, *path, *curver, *newver; + int firsttime = 0, needsave = 0; + + if (getenv ("global_env_loaded") == NULL) { + puts ("*** global environment has never been loaded\n"); + puts ("*** fetching from server"); + firsttime = 1; + } + else if ((p = getenv ("always_check_env")) != NULL && + strcmp (p, "yes") == 0) + puts ("*** checking for updated global environment"); + else + return; + + puts (" (Control-C to Abort)\n"); + + if ((path = getenv ("global_env_path")) == NULL || *path == '\0') + path = def_global_env_path; + + if (fetch_and_parse (path, CFG_LOAD_ADDR, env_callback) == 0) { + puts ("*** Fetch of global environment failed!\n"); + return; + } + + if ((newver = getenv ("new_genv_version")) == NULL) { + puts ("*** Version number not set - contents ignored!\n"); + return; + } + + if ((curver = getenv ("global_env_version")) == NULL || \ + strcmp (curver, newver) != 0) { + setenv ("global_env_version", newver); + needsave = 1; + } + else + printf ("*** Global environment up-to-date (ver %s)\n", curver); + + setenv ("new_genv_version", NULL); + + if (firsttime) { + setenv ("global_env_loaded", "yes"); + needsave = 1; + } + + if (needsave) + puts ("\n*** Remember to run the 'saveenv' " + "command to save the changes\n\n"); +} diff --git a/board/hymod/fetch.c b/board/hymod/fetch.c new file mode 100644 index 0000000..e121d55 --- /dev/null +++ b/board/hymod/fetch.c @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2001 + * Murray Jensen, CSIRO-MIT, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* imports from input.c */ +extern int hymod_get_ethaddr (void); + +int +fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *)) +{ + char *ethaddr; + uchar *fp, *efp; + int rc, count = 0; + + while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') { + + printf ("*** Ethernet address is%s not set\n", + count == 0 ? "" : " STILL"); + + if ((rc = hymod_get_ethaddr ()) < 0) { + if (rc == -1) + puts ("\n*** interrupted!"); + else + puts ("\n*** timeout!"); + printf (" - fetch of '%s' aborted\n", fn); + return (0); + } + + count++; + } + + copy_filename (BootFile, fn, sizeof (BootFile)); + load_addr = addr; + NetBootFileXferSize = 0; + + if (NetLoop (TFTP) == 0) { + printf ("tftp transfer of file '%s' failed\n", fn); + return (0); + } + + if (NetBootFileXferSize == 0) { + printf ("can't determine size of file '%s'\n", fn); + return (0); + } + + fp = (uchar *)load_addr; + efp = fp + NetBootFileXferSize; + + do { + uchar *name, *value; + + if (*fp == '#' || *fp == '\n') { + /* skip this line */ + while (fp < efp && *fp++ != '\n') + ; + continue; + } + + name = fp; + + while (fp < efp && *fp != '=' && *fp != '\n') + fp++; + if (fp >= efp) + break; + if (*fp == '\n') { + fp++; + continue; + } + *fp++ = '\0'; + + value = fp; + + while (fp < efp && *fp != '\n') + fp++; + if (fp[-1] == '\r') + fp[-1] = '\0'; + *fp++ = '\0'; /* ok if we go off the end here */ + + if ((*cback)(name, value) == 0) + return (0); + + } while (fp < efp); + + return (1); +} diff --git a/board/hymod/flash.c b/board/hymod/flash.c new file mode 100644 index 0000000..ad0a229 --- /dev/null +++ b/board/hymod/flash.c @@ -0,0 +1,506 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +/*----------------------------------------------------------------------- + */ + +/* + * probe for flash bank at address "base" and store info about it + * in the flash_info entry "fip". Fatal error if nothing there. + */ +static void +bank_probe (flash_info_t *fip, volatile bank_addr_t base) +{ + volatile bank_addr_t addr; + bank_word_t word; + int i; + + /* reset the flash */ + *base = BANK_CMD_RST; + + /* put flash into read id mode */ + *base = BANK_CMD_RD_ID; + + /* check the manufacturer id - must be intel */ + word = *BANK_REG_MAN_CODE (base); + if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff)) + panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx", + (unsigned long)word, (unsigned long)base); + + /* check the device id */ + word = *BANK_REG_DEV_CODE (base); + switch (word) { + + case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff): + fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5; + fip->sector_count = 32; + break; + + case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff): + fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5; + fip->sector_count = 64; + break; + + case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff): + fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A; + fip->sector_count = 32; + break; + + case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff): + fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A; + fip->sector_count = 64; + break; + + case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff): + fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A; + fip->sector_count = 128; + break; + + default: + panic ("\nbad device code (0x%08lx) at addr 0x%08lx", + (unsigned long)word, (unsigned long)base); + } + + if (fip->sector_count >= CFG_MAX_FLASH_SECT) + panic ("\ntoo many sectors (%d) in flash at address 0x%08lx", + fip->sector_count, (unsigned long)base); + + addr = base; + for (i = 0; i < fip->sector_count; i++) { + fip->start[i] = (unsigned long)addr; + fip->protect[i] = 0; + addr = BANK_ADDR_NEXT_BLK (addr); + } + + fip->size = (bank_size_t)addr - (bank_size_t)base; + + /* reset the flash */ + *base = BANK_CMD_RST; +} + +static void +bank_reset (flash_info_t *info, int sect) +{ + volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; + +#ifdef FLASH_DEBUG + printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr); +#endif + + *addr = BANK_CMD_RST; +} + +static void +bank_erase_init (flash_info_t *info, int sect) +{ + volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; + int flag; + +#ifdef FLASH_DEBUG + printf ("erasing sector %d, addr = 0x%08lx\n", + sect, (unsigned long)addr); +#endif + + /* Disable intrs which might cause a timeout here */ + flag = disable_interrupts (); + +#ifdef FLASH_DEBUG + printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr); +#endif + *addr = BANK_CMD_ERASE1; + *addr = BANK_CMD_ERASE2; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); +} + +static int +bank_erase_poll (flash_info_t *info, int sect) +{ + volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; + bank_word_t stat = *addr; + +#ifdef FLASH_DEBUG + printf ("checking status at addr 0x%08lx [0x%08lx]\n", + (unsigned long)addr, (unsigned long)stat); +#endif + + if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) { + if ((stat & BANK_STAT_ERR) != 0) { + printf ("failed on sector %d [0x%08lx] at " + "address 0x%08lx\n", sect, + (unsigned long)stat, (unsigned long)addr); + *addr = BANK_CMD_CLR_STAT; + return (-1); + } + else + return (1); + } + else + return (0); +} + +static int +bank_write_word (volatile bank_addr_t addr, bank_word_t value) +{ + bank_word_t stat; + ulong start; + int flag, retval; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = BANK_CMD_PROG; + + *addr = value; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + retval = 0; + + /* data polling for D7 */ + start = get_timer (0); + do { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + retval = 1; + goto done; + } + stat = *addr; + } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); + + if ((stat & BANK_STAT_ERR) != 0) { + printf ("flash program failed [0x%08lx] at address 0x%08lx\n", + (unsigned long)stat, (unsigned long)addr); + *addr = BANK_CMD_CLR_STAT; + retval = 3; + } + +done: + /* reset to read mode */ + *addr = BANK_CMD_RST; + + return (retval); +} + +/*----------------------------------------------------------------------- + */ + +unsigned long +flash_init (void) +{ + int i; + + /* Init: no FLASHes known */ + for (i=0; iflash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J5: printf ("28F320J5 (32 Mbit, 2 x 16bit)\n"); + break; + case FLASH_28F640J5: printf ("28F640J5 (64 Mbit, 2 x 16bit)\n"); + break; + case FLASH_28F320J3A: printf ("28F320J3A (32 Mbit, 2 x 16bit)\n"); + break; + case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 2 x 16bit)\n"); + break; + case FLASH_28F128J3A: printf ("28F320J3A (128 Mbit, 2 x 16bit)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ + +/*----------------------------------------------------------------------- + */ + +int +flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int prot, sect, haderr; + ulong start, now, last; + int rcode = 0; + +#ifdef FLASH_DEBUG + printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" + " Bank # %d: ", s_last - s_first + 1, s_first, s_last, + (info - flash_info) + 1); + flash_print_info (info); +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sector%s will not be erased\n", + prot, (prot > 1 ? "s" : "")); + } + + start = get_timer (0); + last = 0; + haderr = 0; + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + ulong estart; + int sectdone; + + bank_erase_init (info, sect); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + estart = get_timer (start); + + do { + now = get_timer (start); + + if (now - estart > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout (sect %d)\n", sect); + haderr = 1; + rcode = 1; + break; + } + +#ifndef FLASH_DEBUG + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } +#endif + + sectdone = bank_erase_poll (info, sect); + + if (sectdone < 0) { + haderr = 1; + rcode = 1; + break; + } + + } while (!sectdone); + + if (haderr) + break; + } + } + + if (haderr > 0) + printf (" failed\n"); + else + printf (" done\n"); + + /* reset to read mode */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + bank_reset (info, sect); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 3 - Program failed + */ +static int +write_word (flash_info_t *info, ulong dest, ulong data) +{ + /* Check if Flash is (sufficiently) erased */ + if ((*(ulong *)dest & data) != data) + return (2); + + return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data)); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 3 - Program failed + */ + +int +write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/hymod/flash.h b/board/hymod/flash.h new file mode 100644 index 0000000..ee047fe --- /dev/null +++ b/board/hymod/flash.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2000 + * Murray Jensen, CSIRO-MIT, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ + +/* Commands */ +#define ISF_CMD_RST 0xFF /* reset flash */ +#define ISF_CMD_RD_ID 0x90 /* read the id and lock bits */ +#define ISF_CMD_RD_QUERY 0x98 /* read device capabilities */ +#define ISF_CMD_RD_STAT 0x70 /* read the status register */ +#define ISF_CMD_CLR_STAT 0x50 /* clear the staus register */ +#define ISF_CMD_WR_BUF 0xE8 /* clear the staus register */ +#define ISF_CMD_PROG 0x40 /* program word command */ +#define ISF_CMD_ERASE1 0x20 /* 1st word for block erase */ +#define ISF_CMD_ERASE2 0xD0 /* 2nd word for block erase */ +#define ISF_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ +#define ISF_CMD_LOCK 0x60 /* 1st word for all lock cmds */ +#define ISF_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ +#define ISF_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ +#define ISF_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ + +/* status register bits */ +#define ISF_STAT_DPS 0x02 /* Device Protect Status */ +#define ISF_STAT_VPPS 0x08 /* VPP Status */ +#define ISF_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ +#define ISF_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ +#define ISF_STAT_ESS 0x40 /* Erase Suspend Status */ +#define ISF_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ + +#define ISF_STAT_ERR (ISF_STAT_VPPS | ISF_STAT_DPS | \ + ISF_STAT_ECLBS | ISF_STAT_PSLBS) + +/* register addresses, valid only following an ISF_CMD_RD_ID command */ +#define ISF_REG_MAN_CODE 0x00 /* manufacturer code */ +#define ISF_REG_DEV_CODE 0x01 /* device code */ +#define ISF_REG_BLK_LCK 0x02 /* block lock configuration */ +#define ISF_REG_MST_LCK 0x03 /* master lock configuration */ + +/********************** DEFINES for Hymod Flash ******************************/ + +/* + * this code requires that the flash on any Hymod board appear as a bank + * of two (identical) 16bit Intel StrataFlash chips with 64Kword erase + * sectors (or blocks), running in x16 bit mode and connected side-by-side + * to make a 32-bit wide bus. + */ + +typedef unsigned long bank_word_t; +typedef bank_word_t bank_blk_t[64 * 1024]; + +#define BANK_FILL_WORD(b) (((bank_word_t)(b) << 16) | (bank_word_t)(b)) + +#ifdef EXAMPLE + +/* theoretically the following examples should also work */ + +/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */ +typedef unsigned char bank_word_t; +typedef bank_word_t bank_blk_t[128 * 1024]; +#define BANK_FILL_WORD(b) ((bank_word_t)(b)) + +/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */ +typedef unsigned long long bank_word_t; +typedef bank_word_t bank_blk_t[32 * 1024]; +#define BANK_FILL_WORD(b) ( \ + ((bank_word_t)(b) << 48) \ + ((bank_word_t)(b) << 32) \ + ((bank_word_t)(b) << 16) \ + ((bank_word_t)(b) << 0) \ + ) + +#endif /* EXAMPLE */ + +/* the sizes of these two types should probably be the same */ +typedef bank_word_t *bank_addr_t; +typedef unsigned long bank_size_t; + +/* align bank addresses and sizes to bank word boundaries */ +#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(sizeof (bank_word_t) - 1))) +#define BANK_SIZE_WORD_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_word_t) - 1) \ + & ~(sizeof (bank_word_t) - 1)) + +/* align bank addresses and sizes to bank block boundaries */ +#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ + & ~(sizeof (bank_blk_t) - 1))) +#define BANK_SIZE_BLK_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \ + & ~(sizeof (bank_blk_t) - 1)) + +/* add an offset to a bank address */ +#define BANK_ADDR_OFFSET(a, o) ((bank_addr_t)((bank_size_t)(a) + \ + (bank_size_t)(o))) + +/* adjust a bank address to start of next word, block or bank */ +#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ + sizeof (bank_word_t)) +#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ + sizeof (bank_blk_t)) + +/* get bank address of register r given a bank base address a and block num b */ +#define BANK_ADDR_REG(a, b, r) BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \ + (bank_size_t)(b) * sizeof (bank_blk_t)), \ + (bank_size_t)(r) * sizeof (bank_word_t)) + +/* make a bank word value for each StrataFlash value */ + +/* Commands */ +#define BANK_CMD_RST BANK_FILL_WORD(ISF_CMD_RST) +#define BANK_CMD_RD_ID BANK_FILL_WORD(ISF_CMD_RD_ID) +#define BANK_CMD_RD_STAT BANK_FILL_WORD(ISF_CMD_RD_STAT) +#define BANK_CMD_CLR_STAT BANK_FILL_WORD(ISF_CMD_CLR_STAT) +#define BANK_CMD_ERASE1 BANK_FILL_WORD(ISF_CMD_ERASE1) +#define BANK_CMD_ERASE2 BANK_FILL_WORD(ISF_CMD_ERASE2) +#define BANK_CMD_PROG BANK_FILL_WORD(ISF_CMD_PROG) +#define BANK_CMD_LOCK BANK_FILL_WORD(ISF_CMD_LOCK) +#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK) +#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR) +#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK) + +/* status register bits */ +#define BANK_STAT_DPS BANK_FILL_WORD(ISF_STAT_DPS) +#define BANK_STAT_PSS BANK_FILL_WORD(ISF_STAT_PSS) +#define BANK_STAT_VPPS BANK_FILL_WORD(ISF_STAT_VPPS) +#define BANK_STAT_PSLBS BANK_FILL_WORD(ISF_STAT_PSLBS) +#define BANK_STAT_ECLBS BANK_FILL_WORD(ISF_STAT_ECLBS) +#define BANK_STAT_ESS BANK_FILL_WORD(ISF_STAT_ESS) +#define BANK_STAT_RDY BANK_FILL_WORD(ISF_STAT_RDY) + +#define BANK_STAT_ERR BANK_FILL_WORD(ISF_STAT_ERR) + +/* make a bank register address for each StrataFlash register address */ + +#define BANK_REG_MAN_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE) +#define BANK_REG_DEV_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE) +#define BANK_REG_BLK_LCK(a, b) BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK) +#define BANK_REG_MST_LCK(a) BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK) diff --git a/board/hymod/global_env b/board/hymod/global_env new file mode 100644 index 0000000..f61d080 --- /dev/null +++ b/board/hymod/global_env @@ -0,0 +1,161 @@ +# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE + +# (C) Copyright 2001 +# Murray Jensen, CSIRO-MIT, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# global_env +# +# file used by Hymod boards to initialise the u-boot non-volatile +# environment when u-boot is first run (it determines this by the +# absence of the environment variable "global_env_loaded") +# +# format of this file is: +# +# 1. blank lines and lines beginning with '#' are ignored +# 2. all other lines must have the form = +# 3. if a percent appears anywhere, it is replaced like so: +# +# %s serial number of the main board (10 digit zero filled) +# %S serial number of the main board (plain number) +# %% a percentage character +# ... otherwise the %x is discarded +# +# if first character in is a dash ('-'), then an existing env var +# will not be overwritten (the dash is removed). i.e. it is only set if +# it does not exist +# +# if last character in is a plus ('+'), then will be appended +# to any existing env var (the plus is ignored). Duplicates of are +# removed. +# +# similarly, if the last character in is a minus ('-'), then any +# occurences of in the current value of will removed (the +# minus is ignored). +# +# leading and trailing whitespace is removed in both and +# (after processing any initial or final plus/minus in ). +# + +# MISCELLANEOUS PARAMETERS + +# version must always come first +version=4 + +# set the ip address based on the main board serial number +ipaddr=192.168.1.%S +serverip=192.168.1.254 + +# stop auto execute after tftp (not a very good name really) +autostart=no + +# setting this to "yes" forces the global_env file to be loaded and processed +# if the current version is different to the version in the file +always_check_env=no + +# BOOTING COMMANDS AND PARAMETERS + +# command to run when "auto-booting" +bootcmd=bootm 40080000 + +# how long the "countdown" to automatically running "bootcmd" is +bootdelay=2 + +# how long before it "times out" console input and attempts to run "bootcmd" +bootretry=5 + +# arguments passed to the boot program (i.e. linux kernel) via register 6 +# the linux kernel (v2.4) uses the following registers: +# r3 - address of board information structure +# r4 - address of initial ramdisk image (0 means no initrd) +# r5 - size of initial ramdisk image +# r6 - address of command line string +-bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro + +# these four are for hymod linux integrated into our Sun network +bootargs+=serialno=%S +bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4 +bootargs+=nfsclient +bootargs+=automount + +# start a web server by default +bootargs+=webserver + +# give negotiation time to finish +bootargs+=netsleep=5 + +# then our ciscos don't pass packets for 25-30 secs after that, so +# pinging the server until it responds prevents network connections +# from failing... +bootargs+=netping + +# these are old bootargs - we don't need them anymore +bootargs-=preload=unix,i2c-cpm,i2c-dev +bootargs-=ramdisk_size=32768 +bootargs-=ramdisk_size=24576 + +# FLASH MANIPULATION COMMANDS + +# +# 16M flash, 64 x 256K sectors, mapped at address 0x40000000 +# +# Sector(s) Address Size Description +# +# 0 - 0 0x40000000 256K boot code +# 1 - 1 0x40040000 256K non volatile environment +# 2 - 4 0x40080000 768K linux kernel image +# 5 - 7 0x40140000 768K alternate linux kernel image +# 8 - 47 0x40200000 10M linux initial ramdisk image +# 48 - 63 0x40c00000 4M ramdisk image for applications +# + +fetchboot=tftp 100000 /hymod/u-boot.bin +eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0 +copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0 +cmpboot=cmp.b 100000 40000000 40000 +newboot=run fetchboot eraseboot copyboot cmpboot + +fetchlinux=tftp 100000 /hymod/linux.bin +eraselinux=erase 1:2-4 +copylinux=cp.b 100000 40080000 ${filesize} +cmplinux=cmp.b 100000 40080000 ${filesize} +newlinux=run fetchlinux eraselinux copylinux cmplinux + +fetchaltlinux=tftp 100000 /hymod/altlinux.bin +erasealtlinux=erase 1:5-7 +copyaltlinux=cp.b 100000 40140000 ${filesize} +cmpaltlinux=cmp.b 100000 40140000 ${filesize} +newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux + +fetchroot=tftp 100000 /hymod/root.bin +eraseroot=erase 1:8-47 +copyroot=cp.b 100000 40200000 ${filesize} +cmproot=cmp.b 100000 40200000 ${filesize} +newroot=run fetchroot eraseroot copyroot cmproot + +fetchard=tftp 100000 /hymod/apprd.bin +eraseard=erase 1:48-63 +copyard=cp.b 100000 40c00000 ${filesize} +cmpard=cmp.b 100000 40c00000 ${filesize} +newapprd=run fetchard eraseard copyard cmpard + +# pass above map to linux mtd driver +bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod) diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c new file mode 100644 index 0000000..dea0a70 --- /dev/null +++ b/board/hymod/hymod.c @@ -0,0 +1,537 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 + */ + +#include +#include +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +/* imports from eeprom.c */ +extern int hymod_eeprom_read (int, hymod_eeprom_t *); +extern void hymod_eeprom_print (hymod_eeprom_t *); + +/* imports from env.c */ +extern void hymod_check_env (void); + +/* ------------------------------------------------------------------------- */ + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { + /* cnf par sor dir odr dat */ + { 1, 1, 1, 0, 0, 0 }, /* PA31: FCC1 MII COL */ + { 1, 1, 1, 0, 0, 0 }, /* PA30: FCC1 MII CRS */ + { 1, 1, 1, 1, 0, 0 }, /* PA29: FCC1 MII TX_ER */ + { 1, 1, 1, 1, 0, 0 }, /* PA28: FCC1 MII TX_EN */ + { 1, 1, 1, 0, 0, 0 }, /* PA27: FCC1 MII RX_DV */ + { 1, 1, 1, 0, 0, 0 }, /* PA26: FCC1 MII RX_ER */ + { 1, 0, 0, 1, 0, 0 }, /* PA25: FCC2 MII MDIO */ + { 1, 0, 0, 1, 0, 0 }, /* PA24: FCC2 MII MDC */ + { 1, 0, 0, 1, 0, 0 }, /* PA23: FCC3 MII MDIO */ + { 1, 0, 0, 1, 0, 0 }, /* PA22: FCC3 MII MDC */ + { 1, 1, 0, 1, 0, 0 }, /* PA21: FCC1 MII TxD[3] */ + { 1, 1, 0, 1, 0, 0 }, /* PA20: FCC1 MII TxD[2] */ + { 1, 1, 0, 1, 0, 0 }, /* PA19: FCC1 MII TxD[1] */ + { 1, 1, 0, 1, 0, 0 }, /* PA18: FCC1 MII TxD[0] */ + { 1, 1, 0, 0, 0, 0 }, /* PA17: FCC1 MII RxD[3] */ + { 1, 1, 0, 0, 0, 0 }, /* PA16: FCC1 MII RxD[2] */ + { 1, 1, 0, 0, 0, 0 }, /* PA15: FCC1 MII RxD[1] */ + { 1, 1, 0, 0, 0, 0 }, /* PA14: FCC1 MII RxD[0] */ + { 1, 0, 0, 1, 0, 0 }, /* PA13: FCC1 MII MDIO */ + { 1, 0, 0, 1, 0, 0 }, /* PA12: FCC1 MII MDC */ + { 1, 0, 0, 1, 0, 0 }, /* PA11: SEL_CD */ + { 1, 0, 0, 0, 0, 0 }, /* PA10: FLASH STS1 */ + { 1, 0, 0, 0, 0, 0 }, /* PA09: FLASH STS0 */ + { 1, 0, 0, 0, 0, 0 }, /* PA08: FLASH ~PE */ + { 1, 0, 0, 0, 0, 0 }, /* PA07: WATCH ~HRESET */ + { 1, 0, 0, 0, 1, 0 }, /* PA06: VC DONE */ + { 1, 0, 0, 1, 1, 0 }, /* PA05: VC INIT */ + { 1, 0, 0, 1, 0, 0 }, /* PA04: VC ~PROG */ + { 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */ + { 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */ + { 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */ + { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */ + }, + + /* Port B configuration */ + { + /* cnf par sor dir odr dat */ + { 1, 1, 0, 1, 0, 0 }, /* PB31: FCC2 MII TX_ER */ + { 1, 1, 0, 0, 0, 0 }, /* PB30: FCC2 MII RX_DV */ + { 1, 1, 1, 1, 0, 0 }, /* PB29: FCC2 MII TX_EN */ + { 1, 1, 0, 0, 0, 0 }, /* PB28: FCC2 MII RX_ER */ + { 1, 1, 0, 0, 0, 0 }, /* PB27: FCC2 MII COL */ + { 1, 1, 0, 0, 0, 0 }, /* PB26: FCC2 MII CRS */ + { 1, 1, 0, 1, 0, 0 }, /* PB25: FCC2 MII TxD[3] */ + { 1, 1, 0, 1, 0, 0 }, /* PB24: FCC2 MII TxD[2] */ + { 1, 1, 0, 1, 0, 0 }, /* PB23: FCC2 MII TxD[1] */ + { 1, 1, 0, 1, 0, 0 }, /* PB22: FCC2 MII TxD[0] */ + { 1, 1, 0, 0, 0, 0 }, /* PB21: FCC2 MII RxD[0] */ + { 1, 1, 0, 0, 0, 0 }, /* PB20: FCC2 MII RxD[1] */ + { 1, 1, 0, 0, 0, 0 }, /* PB19: FCC2 MII RxD[2] */ + { 1, 1, 0, 0, 0, 0 }, /* PB18: FCC2 MII RxD[3] */ + { 1, 1, 0, 0, 0, 0 }, /* PB17: FCC3 MII RX_DV */ + { 1, 1, 0, 0, 0, 0 }, /* PB16: FCC3 MII RX_ER */ + { 1, 1, 0, 1, 0, 0 }, /* PB15: FCC3 MII TX_ER */ + { 1, 1, 0, 1, 0, 0 }, /* PB14: FCC3 MII TX_EN */ + { 1, 1, 0, 0, 0, 0 }, /* PB13: FCC3 MII COL */ + { 1, 1, 0, 0, 0, 0 }, /* PB12: FCC3 MII CRS */ + { 1, 1, 0, 0, 0, 0 }, /* PB11: FCC3 MII RxD[3] */ + { 1, 1, 0, 0, 0, 0 }, /* PB10: FCC3 MII RxD[2] */ + { 1, 1, 0, 0, 0, 0 }, /* PB09: FCC3 MII RxD[1] */ + { 1, 1, 0, 0, 0, 0 }, /* PB08: FCC3 MII RxD[0] */ + { 1, 1, 0, 1, 0, 0 }, /* PB07: FCC3 MII TxD[3] */ + { 1, 1, 0, 1, 0, 0 }, /* PB06: FCC3 MII TxD[2] */ + { 1, 1, 0, 1, 0, 0 }, /* PB05: FCC3 MII TxD[1] */ + { 1, 1, 0, 1, 0, 0 }, /* PB04: FCC3 MII TxD[0] */ + { 0, 0, 0, 0, 0, 0 }, /* PB03: pin doesn't exist */ + { 0, 0, 0, 0, 0, 0 }, /* PB02: pin doesn't exist */ + { 0, 0, 0, 0, 0, 0 }, /* PB01: pin doesn't exist */ + { 0, 0, 0, 0, 0, 0 } /* PB00: pin doesn't exist */ + }, + + /* Port C configuration */ + { + /* cnf par sor dir odr dat */ + { 1, 0, 0, 0, 0, 0 }, /* PC31: MEZ ~IACK */ + { 0, 0, 0, 0, 0, 0 }, /* PC30: ? */ + { 1, 1, 0, 0, 0, 0 }, /* PC29: CLK SCCx */ + { 1, 1, 0, 0, 0, 0 }, /* PC28: CLK4 */ + { 1, 1, 0, 0, 0, 0 }, /* PC27: CLK SCCF */ + { 1, 1, 0, 0, 0, 0 }, /* PC26: CLK 32K */ + { 1, 1, 0, 0, 0, 0 }, /* PC25: BRG4/CLK7 */ + { 0, 0, 0, 0, 0, 0 }, /* PC24: ? */ + { 1, 1, 0, 0, 0, 0 }, /* PC23: CLK SCCx */ + { 1, 1, 0, 0, 0, 0 }, /* PC22: FCC1 MII RX_CLK */ + { 1, 1, 0, 0, 0, 0 }, /* PC21: FCC1 MII TX_CLK */ + { 1, 1, 0, 0, 0, 0 }, /* PC20: CLK SCCF */ + { 1, 1, 0, 0, 0, 0 }, /* PC19: FCC2 MII RX_CLK */ + { 1, 1, 0, 0, 0, 0 }, /* PC18: FCC2 MII TX_CLK */ + { 1, 1, 0, 0, 0, 0 }, /* PC17: FCC3 MII RX_CLK */ + { 1, 1, 0, 0, 0, 0 }, /* PC16: FCC3 MII TX_CLK */ + { 1, 0, 0, 0, 0, 0 }, /* PC15: SCC1 UART ~CTS */ + { 1, 0, 0, 0, 0, 0 }, /* PC14: SCC1 UART ~CD */ + { 1, 0, 0, 0, 0, 0 }, /* PC13: SCC2 UART ~CTS */ + { 1, 0, 0, 0, 0, 0 }, /* PC12: SCC2 UART ~CD */ + { 1, 0, 0, 1, 0, 0 }, /* PC11: SCC1 UART ~DTR */ + { 1, 0, 0, 1, 0, 0 }, /* PC10: SCC1 UART ~DSR */ + { 1, 0, 0, 1, 0, 0 }, /* PC09: SCC2 UART ~DTR */ + { 1, 0, 0, 1, 0, 0 }, /* PC08: SCC2 UART ~DSR */ + { 1, 0, 0, 0, 0, 0 }, /* PC07: TEMP ~ALERT */ + { 1, 0, 0, 0, 0, 0 }, /* PC06: FCC3 INT */ + { 1, 0, 0, 0, 0, 0 }, /* PC05: FCC2 INT */ + { 1, 0, 0, 0, 0, 0 }, /* PC04: FCC1 INT */ + { 0, 1, 1, 1, 0, 0 }, /* PC03: SDMA IDMA2 ~DACK */ + { 0, 1, 1, 0, 0, 0 }, /* PC02: SDMA IDMA2 ~DONE */ + { 0, 1, 0, 0, 0, 0 }, /* PC01: SDMA IDMA2 ~DREQ */ + { 1, 1, 0, 1, 0, 0 } /* PC00: BRG7 */ + }, + + /* Port D configuration */ + { + /* cnf par sor dir odr dat */ + { 1, 1, 0, 0, 0, 0 }, /* PD31: SCC1 UART RxD */ + { 1, 1, 1, 1, 0, 0 }, /* PD30: SCC1 UART TxD */ + { 1, 0, 0, 1, 0, 0 }, /* PD29: SCC1 UART ~RTS */ + { 1, 1, 0, 0, 0, 0 }, /* PD28: SCC2 UART RxD */ + { 1, 1, 0, 1, 0, 0 }, /* PD27: SCC2 UART TxD */ + { 1, 0, 0, 1, 0, 0 }, /* PD26: SCC2 UART ~RTS */ + { 1, 0, 0, 0, 0, 0 }, /* PD25: SCC1 UART ~RI */ + { 1, 0, 0, 0, 0, 0 }, /* PD24: SCC2 UART ~RI */ + { 1, 0, 0, 1, 0, 0 }, /* PD23: CLKGEN PD */ + { 1, 0, 0, 0, 0, 0 }, /* PD22: USER3 */ + { 1, 0, 0, 0, 0, 0 }, /* PD21: USER2 */ + { 1, 0, 0, 0, 0, 0 }, /* PD20: USER1 */ + { 1, 1, 1, 0, 0, 0 }, /* PD19: SPI ~SEL */ + { 1, 1, 1, 0, 0, 0 }, /* PD18: SPI CLK */ + { 1, 1, 1, 0, 0, 0 }, /* PD17: SPI MOSI */ + { 1, 1, 1, 0, 0, 0 }, /* PD16: SPI MISO */ + { 1, 1, 1, 0, 1, 0 }, /* PD15: I2C SDA */ + { 1, 1, 1, 0, 1, 0 }, /* PD14: I2C SCL */ + { 1, 0, 0, 1, 0, 1 }, /* PD13: TEMP ~STDBY */ + { 1, 0, 0, 1, 0, 1 }, /* PD12: FCC3 ~RESET */ + { 1, 0, 0, 1, 0, 1 }, /* PD11: FCC2 ~RESET */ + { 1, 0, 0, 1, 0, 1 }, /* PD10: FCC1 ~RESET */ + { 1, 0, 0, 0, 0, 0 }, /* PD09: PD9 */ + { 1, 0, 0, 0, 0, 0 }, /* PD08: PD8 */ + { 1, 0, 0, 1, 0, 1 }, /* PD07: PD7 */ + { 1, 0, 0, 1, 0, 1 }, /* PD06: PD6 */ + { 1, 0, 0, 1, 0, 1 }, /* PD05: PD5 */ + { 1, 0, 0, 1, 0, 1 }, /* PD04: PD4 */ + { 0, 0, 0, 0, 0, 0 }, /* PD03: pin doesn't exist */ + { 0, 0, 0, 0, 0, 0 }, /* PD02: pin doesn't exist */ + { 0, 0, 0, 0, 0, 0 }, /* PD01: pin doesn't exist */ + { 0, 0, 0, 0, 0, 0 } /* PD00: pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* + * AMI FS6377 Clock Generator configuration table + * + * the "fs6377_regs[]" table entries correspond to FS6377 registers + * 0 - 15 (total of 16 bytes). + * + * the data is written to the FS6377 via the i2c bus using address in + * "fs6377_addr" (address is 7 bits - R/W bit not included). + * + * The fs6377 has four clock outputs: A, B, C and D. + * + * Outputs C and D can each provide two different clock outputs C1/D1 or + * C2/D2 depending on the state of the SEL_CD input which is connected to + * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0) + * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2. + * + * PA11 defaults to output low (or 0) in the i/o port config table above. + * + * Output A provides a 100MHz for the High Speed Serial chips. Output B + * provides a 3.6864MHz clock for more accurate asynchronous serial bit + * rates. Output C is routed to the mezzanine connector but is currently + * unused - both C1 and C2 are set to 16MHz. Output D is used by both the + * alt-input and display mezzanine boards for their video chips. The + * alt-input board requires a clock of 24.576MHz and this is available on + * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this + * is available on D2 (PA11=SEL_CD=1). + * + * So the default is a clock suitable for the alt-input board. PA11 is toggled + * later in misc_init_r(), if a display board is detected. + */ + +uchar fs6377_addr = 0x5c; + +uchar fs6377_regs[16] = { + 12, 75, 64, 25, 144, 128, 25, 192, + 0, 16, 135, 192, 224, 64, 64, 192 +}; + +/* ------------------------------------------------------------------------- */ + +/* + * special board initialisation, after clocks and timebase have been + * set up but before environment and serial are initialised. + * + * added so that very early initialisations can be done using the i2c + * driver (which requires the clocks, to calculate the dividers, and + * the timebase, for udelay()) + */ + +int +board_postclk_init (void) +{ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* + * Initialise the FS6377 clock chip + * + * the secondary address is the register number from where to + * start the write - I want to write all the registers + * + * don't bother checking return status - we have no console yet + * to print it on, nor any RAM to store it in - it will be obvious + * if this doesn't work + */ + (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs, + sizeof (fs6377_regs)); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: Hardwired to HYMOD + */ + +int +checkboard (void) +{ + puts ("Board: HYMOD\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * miscellaneous (early - while running in flash) initialisations. + */ + +#define _NOT_USED_ 0xFFFFFFFF + +uint upmb_table[] = { + /* Read Single Beat (RSS) - offset 0x00 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Read Burst (RBS) - offset 0x08 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Write Single Beat (WSS) - offset 0x18 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Write Burst (WSS) - offset 0x20 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Refresh Timer (PTS) - offset 0x30 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Exception Condition (EXS) - offset 0x3c */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ +}; + +uint upmc_table[] = { + /* Read Single Beat (RSS) - offset 0x00 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Read Burst (RBS) - offset 0x08 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Write Single Beat (WSS) - offset 0x18 */ + 0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000, + 0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Write Burst (WSS) - offset 0x20 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Refresh Timer (PTS) - offset 0x30 */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* Exception Condition (EXS) - offset 0x3c */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ +}; + +int +misc_init_f (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + + printf ("UPMs: "); + + upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]); + memctl->memc_mbmr = CFG_MBMR; + + upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]); + memctl->memc_mcmr = CFG_MCMR; + + printf ("configured\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long +initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); + ulong psdmr = CFG_PSDMR; + int i; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are conŜgured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + + return (CFG_SDRAM_SIZE << 20); +} + +/* ------------------------------------------------------------------------- */ +/* miscellaneous initialisations after relocation into ram (misc_init_r) */ +/* */ +/* loads the data in the main board and mezzanine board eeproms into */ +/* the hymod configuration struct stored in the board information area. */ +/* */ +/* if the contents of either eeprom is invalid, prompts for a serial */ +/* number (and an ethernet address if required) then fetches a file */ +/* containing information to be stored in the eeprom from the tftp server */ +/* (the file name is based on the serial number and a built-in path) */ + +int +last_stage_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + hymod_conf_t *cp = &gd->bd->bi_hymod_conf; + int rc; + +#ifdef CONFIG_BOOT_RETRY_TIME + /* + * we use the readline () function, but we also want + * command timeout enabled + */ + init_cmd_timeout (); +#endif + + memset ((void *) cp, 0, sizeof (*cp)); + + /* set up main board config info */ + + rc = hymod_eeprom_read (0, &cp->main.eeprom); + + puts ("EEPROM:main..."); + if (rc < 0) + puts ("NOT PRESENT\n"); + else if (rc == 0) + puts ("INVALID\n"); + else { + cp->main.eeprom.valid = 1; + + printf ("OK (ver %u)\n", cp->main.eeprom.ver); + hymod_eeprom_print (&cp->main.eeprom); + + /* + * hard-wired assumption here: all hymod main boards will have + * one xilinx fpga, with the interrupt line connected to IRQ2 + * + * One day, this might be based on the board type + */ + + cp->main.xlx[0].mmap.prog.exists = 1; + cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE; + cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE; + + cp->main.xlx[0].mmap.reg.exists = 1; + cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE; + cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE; + + cp->main.xlx[0].mmap.port.exists = 1; + cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE; + cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE; + + cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT; + cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN; + cp->main.xlx[0].iopins.prog_pin.flag = 1; + cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT; + cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN; + cp->main.xlx[0].iopins.init_pin.flag = 1; + cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT; + cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN; + cp->main.xlx[0].iopins.done_pin.flag = 1; +#ifdef FPGA_MAIN_ENABLE_PORT + cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT; + cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN; + cp->main.xlx[0].iopins.enable_pin.flag = 1; +#endif + + cp->main.xlx[0].irq = FPGA_MAIN_IRQ; + } + + /* set up mezzanine board config info */ + + rc = hymod_eeprom_read (1, &cp->mezz.eeprom); + + puts ("EEPROM:mezz..."); + if (rc < 0) + puts ("NOT PRESENT\n"); + else if (rc == 0) + puts ("INVALID\n"); + else { + cp->main.eeprom.valid = 1; + + printf ("OK (ver %u)\n", cp->mezz.eeprom.ver); + hymod_eeprom_print (&cp->mezz.eeprom); + } + + cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc)); + + hymod_check_env (); + + return (0); +} + +#ifdef CONFIG_SHOW_ACTIVITY +void board_show_activity (ulong timebase) +{ +#ifdef CFG_HYMOD_DBLEDS + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile iop8260_t *iop = &immr->im_ioport; + static int shift = 0; + + if ((timestamp % CFG_HZ) == 0) { + if (++shift > 3) + shift = 0; + iop->iop_pdatd = + (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift)); + } +#endif /* CFG_HYMOD_DBLEDS */ +} + +void show_activity(int arg) +{ +} +#endif /* CONFIG_SHOW_ACTIVITY */ diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h new file mode 100644 index 0000000..9d8d662 --- /dev/null +++ b/board/hymod/hymod.h @@ -0,0 +1,322 @@ +/* + * (C) Copyright 2001 + * Murray Jensen, CSIRO-MIT, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _HYMOD_H_ +#define _HYMOD_H_ + +#include +#ifdef CONFIG_8260 +#include +#endif + +/* + * hymod configuration data - passed by boot code via the board information + * structure (only U-Boot has support for this at the moment) + * + * there are three types of data passed up from the boot monitor. the first + * (type hymod_eeprom_t) is the eeprom data that was read off both the main + * (or mother) board and the mezzanine board (if any). this data defines how + * many Xilinx fpgas are on each board, and their types (among other things). + * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where + * in the physical address space the various Xilinx fpga access regions have + * been mapped by the boot rom. the third type of data (type xlx_iopins_t, + * one per Xilinx fpga) defines which io port pins are connected to the various + * signals required to program a Xilinx fpga. + * + * A ram/flash "bank" refers to memory controlled by the same chip select. + * + * the eeprom contents are defined as in technical note #2 - basically, + * a header, zero or more records in no particular order, and a 32 bit crc + * a record is 1 or more type bytes, a length byte and "length" bytes. + */ + +#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */ +#define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */ +#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */ + +/* eeprom header */ +typedef + struct { + unsigned char id; /* eeprom id byte */ + unsigned char :1; + unsigned char ver:7; /* eeprom contents version number */ + unsigned long len; /* total # of bytes btw hdr and crc */ + } +hymod_eehdr_t; + +/* maximum number of bytes available for eeprom data records */ +#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \ + - sizeof (hymod_eehdr_t) \ + - sizeof (unsigned long)) + +/* eeprom data record */ +typedef + union { + struct { + unsigned char topbit:1; + unsigned char type:7; + unsigned char len; + unsigned char data[1]; /* variable length */ + } small; + struct { + unsigned short topbit:1; + unsigned short nxtbit:1; + unsigned short type:14; + unsigned short len; + unsigned char data[1]; /* variable length */ + } medium; + struct { + unsigned long topbit:1; + unsigned long nxtbit:1; + unsigned long type:30; + unsigned long len; + unsigned char data[1]; /* variable length */ + } large; + } +hymod_eerec_t; + +#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */ +#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */ + +/* eeprom record types */ +#define HYMOD_EEREC_SERNO 1 /* serial number */ +#define HYMOD_EEREC_DATE 2 /* date */ +#define HYMOD_EEREC_BATCH 3 /* batch id */ +#define HYMOD_EEREC_TYPE 4 /* board type */ +#define HYMOD_EEREC_REV 5 /* revision number */ +#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */ +#define HYMOD_EEREC_FLASH 7 /* flash sizes */ +#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */ +#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */ +#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */ +#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */ +#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */ +#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */ +#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */ +#define HYMOD_EEREC_BUSSPD 15 /* bus speed */ +#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */ +#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */ +#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */ +#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */ + +/* some dimensions */ +#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */ +#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */ +#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */ +#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */ +#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */ + +#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */ + +/* board types */ +#define HYMOD_BDTYPE_NONE 0 /* information not present */ +#define HYMOD_BDTYPE_IO 1 /* I/O main board */ +#define HYMOD_BDTYPE_CLP 2 /* CLP main board */ +#define HYMOD_BDTYPE_DSP 3 /* DSP main board */ +#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */ +#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */ +#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */ +#define HYMOD_BDTYPE_MAX 7 /* first invalid value */ + +/* Xilinx fpga types */ +#define HYMOD_XTYP_NONE 0 /* information not present */ +#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */ +#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */ +#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */ +#define HYMOD_XTYP_MAX 4 /* first invalid value */ + +/* Xilinx fpga speeds */ +#define HYMOD_XSPD_NONE 0 /* information not present */ +#define HYMOD_XSPD_SIX 1 +#define HYMOD_XSPD_SEVEN 2 +#define HYMOD_XSPD_EIGHT 3 +#define HYMOD_XSPD_MAX 4 /* first invalid value */ + +/* Xilinx fpga temperatures */ +#define HYMOD_XTMP_NONE 0 /* information not present */ +#define HYMOD_XTMP_COM 1 +#define HYMOD_XTMP_IND 2 +#define HYMOD_XTMP_MAX 3 /* first invalid value */ + +/* Xilinx fpga grades */ +#define HYMOD_XTMP_NONE 0 /* information not present */ +#define HYMOD_XTMP_NORMAL 1 +#define HYMOD_XTMP_ENGSAMP 2 +#define HYMOD_XTMP_MAX 3 /* first invalid value */ + +/* CPU types */ +#define HYMOD_CPUTYPE_NONE 0 /* information not present */ +#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */ +#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */ + +/* CPU/BUS/CPM clock speeds */ +#define HYMOD_CLKSPD_NONE 0 /* information not present */ +#define HYMOD_CLKSPD_33MHZ 1 +#define HYMOD_CLKSPD_66MHZ 2 +#define HYMOD_CLKSPD_100MHZ 3 +#define HYMOD_CLKSPD_133MHZ 4 +#define HYMOD_CLKSPD_166MHZ 5 +#define HYMOD_CLKSPD_200MHZ 6 +#define HYMOD_CLKSPD_MAX 7 /* first invalid value */ + +/* high speed serial chip types */ +#define HYMOD_HSSTYPE_NONE 0 /* information not present */ +#define HYMOD_HSSTYPE_AMCC52064 1 +#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */ + +/* a date (yyyy-mm-dd) */ +typedef + struct { + unsigned short year; + unsigned char month; + unsigned char day; + } +hymod_date_t; + +/* describes a Xilinx fpga */ +typedef + struct { + unsigned char type; /* chip type */ + unsigned char speed; /* chip speed rating */ + unsigned char temp; /* chip temperature rating */ + unsigned char grade; /* chip grade */ + } +hymod_xlx_t; + +/* describes a Motorola embedded processor */ +typedef + struct { + unsigned char type; /* CPU type */ + unsigned char cpuspd; /* speed of the PowerPC core */ + unsigned char busspd; /* speed of the system and 60x bus */ + unsigned char cpmspd; /* speed of the CPM co-processor */ + } +hymod_mpc_t; + +/* info about high-speed (1Gbit) serial interface */ +typedef + struct { + unsigned char type; /* high-speed serial chip type */ + unsigned char nchin; /* number of input channels mounted */ + unsigned char nchout; /* number of output channels mounted */ + } +hymod_hss_t; + +/* + * this defines the contents of the serial eeprom that exists on every + * hymod board, including mezzanine boards (the serial eeprom will be + * faked for early development boards that don't have one) + */ + +typedef + struct { + unsigned char valid:1; /* contents of this struct is valid */ + unsigned char ver:7; /* eeprom contents version */ + unsigned char bdtype; /* board type */ + unsigned char bdrev; /* board revision */ + unsigned char batchlen; /* length of batch string below */ + unsigned long serno; /* serial number */ + hymod_date_t date; /* manufacture date */ + unsigned char batch[32]; /* manufacturer specific batch id */ + unsigned char nsdram; /* # of ram "banks" */ + unsigned char nflash; /* # of flash "banks" */ + unsigned char nzbt; /* # of ZBT rams */ + unsigned char nxlx; /* # of Xilinx fpgas */ + unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */ + unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */ + unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */ + hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */ + hymod_mpc_t mpc; /* Motorola MPC CPU info */ + hymod_hss_t hss; /* high-speed serial info */ + } +hymod_eeprom_t; + +/* + * this defines a region in the processor's physical address space + */ +typedef + struct { + unsigned long exists:1; /* 1 if the region exists, 0 if not */ + unsigned long size:31; /* size in bytes */ + unsigned long base; /* base address */ + } +xlx_prgn_t; + +/* + * this defines where the various Xilinx fpga access regions are mapped + * into the physical address space of the processor + */ +typedef + struct { + xlx_prgn_t prog; /* program access region */ + xlx_prgn_t reg; /* register access region */ + xlx_prgn_t port; /* port access region */ + } +xlx_mmap_t; + +/* + * this defines which 8260 i/o port pins are connected to the various + * signals required for programming a Xilinx fpga + */ +typedef + struct { + iopin_t prog_pin; /* assert for >= 300ns to program */ + iopin_t init_pin; /* goes high when fpga is cleared */ + iopin_t done_pin; /* goes high when program is done */ + iopin_t enable_pin; /* some fpgas need enabling */ + } +xlx_iopins_t; + +/* all info about one Xilinx chip */ +typedef + struct { + xlx_mmap_t mmap; + xlx_iopins_t iopins; + unsigned long irq:8; /* h/w intr req number for this fpga */ + } +xlx_info_t; + +/* all info about one hymod board */ +typedef + struct { + hymod_eeprom_t eeprom; + xlx_info_t xlx[HYMOD_MAX_XLX]; + } +hymod_board_t; + +/* + * this defines the configuration information of a hymod board-set + * (main board + possible mezzanine board). In future, there may be + * more than one mezzanine board (stackable?) - if so, add a "mezz2" + * field, and so on... or make mezz an array? + */ +typedef + struct { + unsigned long ver:8; /* version control */ + hymod_board_t main; /* main board info */ + hymod_board_t mezz; /* mezzanine board info */ + unsigned long crc; /* ensures kernel and boot prom agree */ + } +hymod_conf_t; + +#endif /* _HYMOD_H_ */ diff --git a/board/hymod/input.c b/board/hymod/input.c new file mode 100644 index 0000000..63aa13c --- /dev/null +++ b/board/hymod/input.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2003 + * Murray Jensen, CSIRO-MIT, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* imports from common/main.c */ +extern char console_buffer[CFG_CBSIZE]; + +int +hymod_get_serno (const char *prompt) +{ + for (;;) { + int n, serno; + char *p; + +#ifdef CONFIG_BOOT_RETRY_TIME + reset_cmd_timeout (); +#endif + + n = readline (prompt); + + if (n < 0) + return (n); + + if (n == 0) + continue; + + serno = (int) simple_strtol (console_buffer, &p, 10); + + if (p > console_buffer && *p == '\0' && serno > 0) + return (serno); + + printf ("Invalid number (%s) - please re-enter\n", + console_buffer); + } +} + +int +hymod_get_ethaddr (void) +{ + for (;;) { + int n; + +#ifdef CONFIG_BOOT_RETRY_TIME + reset_cmd_timeout (); +#endif + + n = readline ("Enter board ethernet address: "); + + if (n < 0) + return (n); + + if (n == 0) + continue; + + if (n == 17) { + int i; + char *p, *q; + uchar ea[6]; + + /* see if it looks like an ethernet address */ + + p = console_buffer; + + for (i = 0; i < 6; i++) { + char term = (i == 5 ? '\0' : ':'); + + ea[i] = simple_strtol (p, &q, 16); + + if ((q - p) != 2 || *q++ != term) + break; + + p = q; + } + + if (i == 6) { + /* it looks ok - set it */ + printf ("Setting ethernet addr to %s\n", + console_buffer); + + setenv ("ethaddr", console_buffer); + + puts ("Remember to do a 'saveenv' to " + "make it permanent\n"); + + return (0); + } + } + + printf ("Invalid ethernet addr (%s) - please re-enter\n", + console_buffer); + } +} diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds new file mode 100644 index 0000000..337a395 --- /dev/null +++ b/board/hymod/u-boot.lds @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8260/start.o (.text) +/* + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; +*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + . = ALIGN(256 * 1024); + .ppcenv : + { + common/environment.o (.ppcenv) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug new file mode 100644 index 0000000..ddd4678 --- /dev/null +++ b/board/hymod/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/icecube/Makefile b/board/icecube/Makefile new file mode 100644 index 0000000..eb5ed59 --- /dev/null +++ b/board/icecube/Makefile @@ -0,0 +1,47 @@ + +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/icecube/config.mk b/board/icecube/config.mk new file mode 100644 index 0000000..07b5de1 --- /dev/null +++ b/board/icecube/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# IceCube board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFF000000 boot low for 16 MiB boards +# 0xFF800000 boot low for 8 MiB boards +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/icecube/flash.c b/board/icecube/flash.c new file mode 100644 index 0000000..713011c --- /dev/null +++ b/board/icecube/flash.c @@ -0,0 +1,491 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + extern void flash_preinit(void); + extern void flash_afterinit(ulong); + ulong flashbase = CFG_FLASH_BASE; + + flash_preinit(); + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + flash_info[i].size = + flash_get_size((FPW *)flashbase, &flash_info[i]); + + size += flash_info[i].size; + flashbase += 0x800000; + } +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + + flash_afterinit(size); + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && + info->start[0] <= base && base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + char *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDLV065D: + fmt = "29LV065 (64 Mbit, uniform sectors)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + int i; + FPWV* addr2; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(100); + switch (addr[0] & 0xff) { + + case (uchar)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { + + case (FPW)AMD_ID_LV065D: + info->flash_id += FLASH_AMDLV065D; + info->sector_count = 128; + info->size = 0x00800000; + for( i = 0; i < info->sector_count; i++ ) + info->start[i] = (ulong)addr + (i * 0x10000); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + /* test for real flash at bank 1 */ + addr2 = (FPW *)((ulong)addr | 0x800000); + if (addr2 != addr && + ((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) { + /* Seems 2 banks are the same space (8Mb chip is installed, + * J24 in default position (CS0)). Disable this (first) bank. + */ + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + } + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDLV065D: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + if (intel) { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW)0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) {/* every second */ + putc ('.'); + last = get_timer(0); + } + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { /* every second */ + putc ('.'); + last = get_timer(0); + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c new file mode 100644 index 0000000..1f1a74c --- /dev/null +++ b/board/icecube/icecube.c @@ -0,0 +1,310 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m16a2-75.h" +#endif + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +#if defined(CONFIG_MPC5200) +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize + dramsize2; +} + +#elif defined(CONFIG_MGT5100) + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup and enable SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; + __asm__ volatile ("sync"); + + /* find RAM size */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* set SDRAM end address according to size */ + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); + +#else /* CFG_RAMBOOT */ + + /* Retrieve amount of SDRAM available */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif + +int checkboard (void) +{ +#if defined(CONFIG_MPC5200) + puts ("Board: Motorola MPC5200 (IceCube)\n"); +#elif defined(CONFIG_MGT5100) + puts ("Board: Motorola MGT5100 (IceCube)\n"); +#endif + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ +#if defined(CONFIG_MGT5100) + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ +#endif + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + +void flash_afterinit(ulong size) +{ + if (size == 0x800000) { /* adjust mapping */ + *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = + START_REG(CFG_BOOTCS_START | size); + *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = + STOP_REG(CFG_BOOTCS_START | size, size); + } +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + /* Deassert reset */ + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(500000); + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + } +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h new file mode 100644 index 0000000..4c0f9a7 --- /dev/null +++ b/board/icecube/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x705f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h new file mode 100644 index 0000000..ffdf039 --- /dev/null +++ b/board/icecube/mt48lc16m16a2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/icecube/u-boot.lds b/board/icecube/u-boot.lds new file mode 100644 index 0000000..f23432e --- /dev/null +++ b/board/icecube/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/icu862/Makefile b/board/icu862/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/icu862/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/icu862/config.mk b/board/icu862/config.mk new file mode 100644 index 0000000..315e70d --- /dev/null +++ b/board/icu862/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# ICU862 boards +# + +TEXT_BASE = 0x40F00000 +OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data diff --git a/board/icu862/flash.c b/board/icu862/flash.c new file mode 100644 index 0000000..ca5bcf3 --- /dev/null +++ b/board/icu862/flash.c @@ -0,0 +1,617 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, + size_b0 >> 20); + } + + if (FLASH_BASE1_PRELIM != 0x0) { + size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); + + if (size_b1 > size_b0) { + printf ("## ERROR: Bank 1 (0x%08lx = %ld MB)" + " > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1 >> 20, + size_b0, size_b0 >> 20); + + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + } else { + size_b1 = 0; + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + + /* ICU862 Board has only one Flash Bank */ + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); + +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM033C)) { + /* set sector offsets for uniform sector type */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00040000); + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + puts ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: puts ("AMD "); break; + case FLASH_MAN_FUJ: puts ("FUJITSU "); break; + case FLASH_MAN_BM: puts ("BRIGHT MICRO "); break; + default: puts ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: puts ("29F040/29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AM033C: puts ("AM29LV033C (32 Mbit)\n"); + break; + default: puts ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + puts (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + puts ("\n "); + } + + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + + puts ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; +#if 0 + ulong base = (ulong)addr; +#endif + uchar value; + + /* Write auto select command: read Manufacturer ID */ +#if 0 + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; +#else + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x90909090; +#endif + + value = addr[0]; + + switch (value + (value << 16)) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + value = addr[1]; /* device ID */ + + switch ((unsigned long)value) { + case AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + case AMD_ID_LV033C: + info->flash_id += FLASH_AM033C; + info->sector_count = 64; + info->size = 0x01000000; + break; /* => 16Mb */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + +#if 0 + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +#else + flash_get_offsets ((ulong)addr, &flash_info[0]); +#endif + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); +#if 1 + /* We don't know why it happens, but on ICU Board * + * for AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if ( i == 32 ) { + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x90909090; + } +#endif + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; +#if 0 + *addr = 0x00F000F0; /* reset bank */ +#else + *addr = 0xF0F0F0F0; /* reset bank */ +#endif + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + puts ("- missing\n"); + } else { + puts ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + puts ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + puts ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + +#if 0 + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; +#else + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x80808080; + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; +#endif + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); +#if 0 + addr[0] = 0x00300030; +#else + addr[0] = 0x30303030; +#endif + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); +#if 0 + while ((addr[0] & 0x00800080) != 0x00800080) +#else + while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) +#endif + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + puts ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; +#if 0 + addr[0] = 0x00F000F0; /* reset bank */ +#else + addr[0] = 0xF0F0F0F0; /* reset bank */ +#endif + + puts (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + +#if 0 + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; +#else + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0xA0A0A0A0; +#endif + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); +#if 0 + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) +#else + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) +#endif + { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c new file mode 100644 index 0000000..8da9d1c --- /dev/null +++ b/board/icu862/icu862.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Memory Controller Using + * + * CS0 - Flash memory (0x40000000) + * CS1 - SDRAM (0x00000000} + * CS2 - S/UNI Ultra ATM155 + * CS3 - IDT 77106 ATM25 + * CS4 - DSP HPI + * CS5 - E1/T1 Interface device + * CS6 - PCMCIA device + * CS7 - PCMCIA device + */ + +/* ------------------------------------------------------------------------- */ + +#define _not_used_ 0xffffffff + +const uint sdram_table[] = { + /* single read. (offset 0 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, + 0x1ff77c47, + + /* MRS initialization (offset 5) */ + + 0x1ff77c34, 0xefeabc34, 0x1fb57c35, + + /* burst read. (offset 8 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* single write. (offset 18 in upm RAM) */ + 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* burst write. (offset 20 in upm RAM) */ + 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, + 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* refresh. (offset 30 in upm RAM) */ + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* exception. (offset 3c in upm RAM) */ + 0x7ffffc07, _not_used_, _not_used_, _not_used_ +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: ICU862 Board\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size8, size9; + long int size_b0 = 0; + unsigned long reg; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 1 to the SDRAM bank at + * preliminary address - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay (200); + memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ + udelay (200); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE1_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE1_PRELIM, + SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size_b0 = size9; +/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); +/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if ((size_b0 < 0x02000000)) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping + */ + + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + + udelay (10000); + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds new file mode 100644 index 0000000..4bc50c5 --- /dev/null +++ b/board/icu862/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) +/* + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) +*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug new file mode 100644 index 0000000..87f228b --- /dev/null +++ b/board/icu862/u-boot.lds.debug @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ids8247/Makefile b/board/ids8247/Makefile new file mode 100644 index 0000000..cfef750 --- /dev/null +++ b/board/ids8247/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2005 +# Heiko Schocher, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/ids8247/config.mk b/board/ids8247/config.mk new file mode 100644 index 0000000..136cdb8 --- /dev/null +++ b/board/ids8247/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2005 +# Heiko Schocher, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# IDS 8247 Board +# + +# This should be equal to the CFG_FLASH_BASE define in config_IDS8247.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# +TEXT_BASE = 0xfff00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/ids8247/flash.c b/board/ids8247/flash.c new file mode 100644 index 0000000..4eba4b9 --- /dev/null +++ b/board/ids8247/flash.c @@ -0,0 +1,484 @@ +/* + * (C) Copyright 2005 + * Heiko Schocher, DENX Software Engineering, + * + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#undef DEBUG + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH8 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#elif FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#else /* FLASH_PORT_WIDTH8 */ +#define FLASH_PORT_WIDTH uchar +#define FLASH_PORT_WIDTHV vu_char +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPWV * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immr->im_memctl; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + size_b0 = flash_get_size ((FPW *) CFG_FLASH0_BASE, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + memctl->memc_or0 = 0xff800060; + memctl->memc_br0 = 0xff800801; + + flash_get_offsets (0xff800000, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000); + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: + printf ("28F320J3A\n"); + break; + case FLASH_28F640J3A: + printf ("28F640J3A\n"); + break; + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (FPWV * addr, flash_info_t * info) +{ + FPW value; + + addr[0] = (FPW) 0x00900090; + + value = addr[0]; + + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value) { + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + +#ifdef FLASH_PORT_WIDTH8 + value = addr[2]; /* device ID */ +#else + value = addr[1]; /* device ID */ +#endif + + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value) { + case (FPW) INTEL_ID_28F320J3A: + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (FPW) INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + + int i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#elif defined(FLASH_PORT_WIDTH32) + wp = (addr & ~3); + port_width = 4; +#else + wp = addr; + port_width = 1; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c new file mode 100644 index 0000000..081ef65 --- /dev/null +++ b/board/ids8247/ids8247.c @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2005 + * Heiko Schocher, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */ + /* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ + /* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ + /* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ + /* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ + /* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ + /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ +#if defined(CONFIG_SOFT_I2C) + /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ + /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */ +#else /* normal I/O port pins */ + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ +#endif + /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ + /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ + /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ + /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ + /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */ + /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */ + /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */ + /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */ + /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */ + /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */ + /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */ + /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */ + /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */ + /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */ +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */ +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + puts ("Board: IDS 8247\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + + long psize, lsize; + + psize = 16 * 1024 * 1024; + lsize = 0; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + psize = try_init (memctl, CFG_PSDMR, CFG_OR2, + (uchar *) CFG_SDRAM_BASE); +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_flashstart = 0xff800000; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +extern ulong +nand_probe (ulong physadr); + +void +nand_init (void) +{ + ulong totlen = 0; + + debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); + totlen += nand_probe (CFG_NAND0_BASE); + + printf ("%4lu MB\n", totlen >>20); +} + +#endif /* CFG_CMD_NAND */ diff --git a/board/ids8247/u-boot.lds b/board/ids8247/u-boot.lds new file mode 100644 index 0000000..788aed3 --- /dev/null +++ b/board/ids8247/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Heiko Schocher, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/impa7/Makefile b/board/impa7/Makefile new file mode 100644 index 0000000..08543f9 --- /dev/null +++ b/board/impa7/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := impa7.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/impa7/config.mk b/board/impa7/config.mk new file mode 100644 index 0000000..417d6a8 --- /dev/null +++ b/board/impa7/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xc1780000 diff --git a/board/impa7/flash.c b/board/impa7/flash.c new file mode 100644 index 0000000..ca76fe8 --- /dev/null +++ b/board/impa7/flash.c @@ -0,0 +1,357 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define FLASH_BANK_SIZE 0x800000 +#define MAIN_SECT_SIZE 0x20000 +#define PARAM_SECT_SIZE 0x4000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F320B3T & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else if (i == 1) + flashbase = PHYS_FLASH_2; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j <= 7) { + flash_info[i].start[j] = + flashbase + j * PARAM_SECT_SIZE; + } else { + flash_info[i].start[j] = + flashbase + (j - 7) * MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F320B3T & FLASH_TYPEMASK): + printf ("28F320F3B (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done:; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + int rc = ERR_OK; + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (INTEL_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *) (info->start[sect]); + + *addr = 0x00200020; /* erase setup */ + *addr = 0x00D000D0; /* erase confirm */ + + while ((*addr & 0x00800080) != 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + *addr = 0x00B000B0; /* suspend erase */ + *addr = 0x00FF00FF; /* reset to read mode */ + rc = ERR_TIMOUT; + goto outahere; + } + } + + *addr = 0x00FF00FF; /* reset to read mode */ + } + printf ("ok.\n"); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (flag) + enable_interrupts (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *) dest; + ulong barf; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased + */ + if ((*addr & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* clear status register command */ + *addr = 0x00500050; + + /* program set-up command */ + *addr = 0x00400040; + + /* latch address/data */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* read status register command */ + *addr = 0x00700070; + + /* wait while polling the status register */ + while ((*addr & 0x00800080) != 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + rc = ERR_TIMOUT; + /* suspend program command */ + *addr = 0x00B000B0; + goto outahere; + } + + if (*addr & 0x003A003A) { /* check for error */ + barf = *addr; + if (barf & 0x003A0000) { + barf >>= 16; + } else { + barf &= 0x0000003A; + } + printf ("\nFlash write error %02lx at address %08lx\n", barf, (unsigned long) dest); + if (barf & 0x0002) { + printf ("Block locked, not erased.\n"); + rc = ERR_NOT_ERASED; + goto outahere; + } + if (barf & 0x0010) { + printf ("Programming error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + if (barf & 0x0008) { + printf ("Vpp Low error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + rc = ERR_PROG_ERROR; + goto outahere; + } + } + + + outahere: + /* read array command */ + *addr = 0x00FF00FF; + + if (flag) + enable_interrupts (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = *((vu_long *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 4; + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + + return write_word (info, wp, data); +} diff --git a/board/impa7/impa7.c b/board/impa7/impa7.c new file mode 100644 index 0000000..e496923 --- /dev/null +++ b/board/impa7/impa7.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Activate LED flasher */ + IO_LEDFLSH = 0x40; + + /* arch number of EP7111 */ + gd->bd->bi_arch_number = MACH_TYPE_EDB7211; + + /* location of boot parameters for EP7111 */ + gd->bd->bi_boot_params = 0xc0020100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + + return (0); +} diff --git a/board/impa7/lowlevel_init.S b/board/impa7/lowlevel_init.S new file mode 100644 index 0000000..7ce10a2 --- /dev/null +++ b/board/impa7/lowlevel_init.S @@ -0,0 +1,85 @@ +/* + * Memory Setup stuff - taken from ??? + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +SYSCON2: .long 0x80001100 +MEMCFG1: .long 0x80000180 +MEMCFG2: .long 0x800001C0 +DRFPR: .long 0x80000200 + +syscon2_mask: .long 0x00000004 +memcfg1_val: .long 0x160c1414 +memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits +memcfg2_val: .long 0x00000000 @ upper 16 bits are reserved for CS7 + CS6 +drfpr_val: .long 0x00000081 +/* setting up the memory */ + +.globl lowlevel_init +lowlevel_init: + /* + * DRFPR + * 64kHz DRAM refresh + */ + ldr r0, DRFPR + ldr r1, drfpr_val + str r1, [r0] + + /* + * SYSCON2: clear bit 2, DRAM is 32 bits wide + */ + ldr r0, SYSCON2 + ldr r2, [r0] + ldr r1, syscon2_mask + bic r2, r2, r1 + str r2, [r0] + + /* + * MEMCFG1 + * Setting up Keyboard at CS3, 8 Bit, 3 Waitstates + * Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates + * Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates + */ + ldr r0, MEMCFG1 + ldr r1, memcfg1_val + str r1, [r0] + + /* + * MEMCFG2 + * Setting up ? with 0 + * + */ + ldr r0, MEMCFG2 + ldr r2, [r0] + ldr r1, memcfg2_mask + bic r2, r2, r1 + ldr r1, memcfg2_val + orr r2, r2, r1 + str r2, [r0] + + /* everything is fine now */ + mov pc, lr diff --git a/board/impa7/u-boot.lds b/board/impa7/u-boot.lds new file mode 100644 index 0000000..1122d75 --- /dev/null +++ b/board/impa7/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/incaip/Makefile b/board/incaip/Makefile new file mode 100644 index 0000000..d9b0e2d --- /dev/null +++ b/board/incaip/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = lowlevel_init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/incaip/config.mk b/board/incaip/config.mk new file mode 100644 index 0000000..0cecc01 --- /dev/null +++ b/board/incaip/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# INCA-IP board with MIPS 4Kc CPU core +# + +# ROM version +TEXT_BASE = 0xB0000000 + +# RAM version +#TEXT_BASE = 0x80100000 diff --git a/board/incaip/flash.c b/board/incaip/flash.c new file mode 100644 index 0000000..520514d --- /dev/null +++ b/board/incaip/flash.c @@ -0,0 +1,671 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +#if 0 +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa +#else +#define FLASH_CYCLE1 0x0554 +#define FLASH_CYCLE2 0x02ab +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static void flash_get_offsets(ulong base, flash_info_t *info); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; + ulong * buscon = (ulong *) + ((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2); + + /* Disable write protection */ + *buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS; + +#if 1 + memset(&flash_info[i], 0, sizeof(flash_info_t)); +#endif + + flash_info[i].size = + flash_get_size((FPW *)flashbase, &flash_info[i]); + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", + i, flash_info[i].size); + } + + size += flash_info[i].size; + } + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL + && (info->flash_id & FLASH_BTYPE)) { + int bootsect_size; /* number of bytes/boot sector */ + int sect_size; /* number of bytes/regular sector */ + + bootsect_size = 0x00002000 * (sizeof(FPW)/2); + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < 8; ++i) { + info->start[i] = base + (i * bootsect_size); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i - 7) * sect_size); + } + } + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set up sector start address table (uniform sector type) */ + for( i = 0; i < info->sector_count; i++ ) + info->start[i] = base + (i * sect_size); + } +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->start[0] <= base && base < info->start[0] + info->size) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + char *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM640U: + fmt = "29LV641D (64 Mbit, uniform sectors)\n"; + break; + case FLASH_28F800C3B: + case FLASH_28F800C3T: + fmt = "28F800C3%s (8 Mbit, %s)\n"; + break; + case FLASH_INTEL800B: + case FLASH_INTEL800T: + fmt = "28F800B3%s (8 Mbit, %s)\n"; + break; + case FLASH_28F160C3B: + case FLASH_28F160C3T: + fmt = "28F160C3%s (16 Mbit, %s)\n"; + break; + case FLASH_INTEL160B: + case FLASH_INTEL160T: + fmt = "28F160B3%s (16 Mbit, %s)\n"; + break; + case FLASH_28F320C3B: + case FLASH_28F320C3T: + fmt = "28F320C3%s (32 Mbit, %s)\n"; + break; + case FLASH_INTEL320B: + case FLASH_INTEL320T: + fmt = "28F320B3%s (32 Mbit, %s)\n"; + break; + case FLASH_28F640C3B: + case FLASH_28F640C3T: + fmt = "28F640C3%s (64 Mbit, %s)\n"; + break; + case FLASH_INTEL640B: + case FLASH_INTEL640T: + fmt = "28F640B3%s (64 Mbit, %s)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + /* Write auto select command: read Manufacturer ID */ + + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + switch (addr[1] & 0xff) { + + case (uchar)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { + + case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F800C3B: + info->flash_id += FLASH_28F800C3B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F800B3B: + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F160B3B: + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F320B3B: + info->flash_id += FLASH_INTEL320B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F640B3B: + info->flash_id += FLASH_INTEL640B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets((ulong)addr, info); + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_INTEL800B: + case FLASH_INTEL160B: + case FLASH_INTEL320B: + case FLASH_INTEL640B: + case FLASH_28F800C3B: + case FLASH_28F160C3B: + case FLASH_28F320C3B: + case FLASH_28F640C3B: + case FLASH_AM640U: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + if (intel) { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW)0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) {/* every second */ + putc ('.'); + last = get_timer(0); + } + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { /* every second */ + putc ('.'); + last = get_timer(0); + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + case FLASH_MAN_INTEL: + res = write_word_intel(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for Intel FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + *dest = (FPW)0x00400040; /* program setup */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00B000B0; /* Suspend program */ + res = 1; + } + } + + if (res == 0 && (*dest & (FPW)0x00100010)) + res = 1; /* write failed, time out error is close enough */ + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + + return (res); +} diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c new file mode 100644 index 0000000..b5d9e00 --- /dev/null +++ b/board/incaip/incaip.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +extern uint incaip_get_cpuclk(void); + +static ulong max_sdram_size(void) +{ + /* The only supported SDRAM data width is 16bit. + */ +#define CFG_DW 2 + + /* The only supported number of SDRAM banks is 4. + */ +#define CFG_NB 4 + + ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; + int cols = cfgpb0 & 0xF; + int rows = (cfgpb0 & 0xF0) >> 4; + ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; + + return size; +} + +long int initdram(int board_type) +{ + int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0; + ulong size, max_size = 0; + ulong our_address; + + asm volatile ("move %0, $25" : "=r" (our_address) :); + + /* Can't probe for RAM size unless we are running from Flash. + */ + if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) + { + return max_sdram_size(); + } + + for (cols = 0x8; cols <= 0xC; cols++) + { + for (rows = 0xB; rows <= 0xD; rows++) + { + *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) | + (rows << 4) | cols; + size = get_ram_size((long *)CFG_SDRAM_BASE, + max_sdram_size()); + + if (size > max_size) + { + best_val = *INCA_IP_SDRAM_MC_CFGPB0; + max_size = size; + } + } + } + + *INCA_IP_SDRAM_MC_CFGPB0 = best_val; + return max_size; +} + +int checkboard (void) +{ + + unsigned long chipid = *INCA_IP_WDT_CHIPID; + int part_num; + + puts ("Board: INCA-IP "); + part_num = (chipid >> 12) & 0xffff; + switch (part_num) { + case 0xc0: + printf ("Standard Version, "); + break; + case 0xc1: + printf ("Basic Version, "); + break; + default: + printf ("Unknown Part Number 0x%x ", part_num); + break; + } + + printf ("Chip V1.%ld, ", (chipid >> 28)); + + printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000); + + return 0; +} diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S new file mode 100644 index 0000000..14d738a --- /dev/null +++ b/board/incaip/lowlevel_init.S @@ -0,0 +1,298 @@ +/* + * Memory sub-system initialization code for INCA-IP development board. + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + + +#define EBU_MODUL_BASE 0xB8000200 +#define EBU_CLC(value) 0x0000(value) +#define EBU_CON(value) 0x0010(value) +#define EBU_ADDSEL0(value) 0x0020(value) +#define EBU_ADDSEL1(value) 0x0024(value) +#define EBU_ADDSEL2(value) 0x0028(value) +#define EBU_BUSCON0(value) 0x0060(value) +#define EBU_BUSCON1(value) 0x0064(value) +#define EBU_BUSCON2(value) 0x0068(value) + +#define MC_MODUL_BASE 0xBF800000 +#define MC_ERRCAUSE(value) 0x0100(value) +#define MC_ERRADDR(value) 0x0108(value) +#define MC_IOGP(value) 0x0800(value) +#define MC_SELFRFSH(value) 0x0A00(value) +#define MC_CTRLENA(value) 0x1000(value) +#define MC_MRSCODE(value) 0x1008(value) +#define MC_CFGDW(value) 0x1010(value) +#define MC_CFGPB0(value) 0x1018(value) +#define MC_LATENCY(value) 0x1038(value) +#define MC_TREFRESH(value) 0x1040(value) + +#define CGU_MODUL_BASE 0xBF107000 +#define CGU_PLL1CR(value) 0x0008(value) +#define CGU_DIVCR(value) 0x0010(value) +#define CGU_MUXCR(value) 0x0014(value) +#define CGU_PLL1SR(value) 0x000C(value) + + .set noreorder + + +/* + * void ebu_init(long) + * + * a0 has the clock value we are going to run at + */ + .globl ebu_init + .ent ebu_init +ebu_init: +__ebu_init: + + li t1, EBU_MODUL_BASE + li t2, 0xA0000041 + sw t2, EBU_ADDSEL0(t1) + li t2, 0xA0800041 + sw t2, EBU_ADDSEL2(t1) + li t2, 0xBE0000F1 + sw t2, EBU_ADDSEL1(t1) + + li t3, 100000000 + beq a0, t3, 1f + nop + li t3, 133000000 + beq a0, t3, 2f + nop + li t3, 150000000 + beq a0, t3, 2f + nop + b 3f + nop + + /* 100 MHz */ +1: + li t2, 0x8841417D + sw t2, EBU_BUSCON0(t1) + sw t2, EBU_BUSCON2(t1) + li t2, 0x684142BD + b 3f + sw t2, EBU_BUSCON1(t1) /* delay slot */ + + /* 133 or 150 MHz */ +2: + li t2, 0x8841417E + sw t2, EBU_BUSCON0(t1) + sw t2, EBU_BUSCON2(t1) + li t2, 0x684143FD + sw t2, EBU_BUSCON1(t1) +3: + j ra + nop + + .end ebu_init + + +/* + * void cgu_init(long) + * + * a0 has the clock value + */ + .globl cgu_init + .ent cgu_init +cgu_init: +__cgu_init: + + li t1, CGU_MODUL_BASE + + li t3, 100000000 + beq a0, t3, 1f + nop + li t3, 133000000 + beq a0, t3, 2f + nop + li t3, 150000000 + beq a0, t3, 3f + nop + b 5f + nop + + /* 100 MHz clock */ +1: + li t2, 0x80000014 + sw t2, CGU_DIVCR(t1) + li t2, 0x80000000 + sw t2, CGU_MUXCR(t1) + li t2, 0x800B0001 + b 5f + sw t2, CGU_PLL1CR(t1) /* delay slot */ + + /* 133 MHz clock */ +2: + li t2, 0x80000054 + sw t2, CGU_DIVCR(t1) + li t2, 0x80000000 + sw t2, CGU_MUXCR(t1) + li t2, 0x800B0001 + b 5f + sw t2, CGU_PLL1CR(t1) /* delay slot */ + + /* 150 MHz clock */ +3: + li t2, 0x80000017 + sw t2, CGU_DIVCR(t1) + li t2, 0xC00B0001 + sw t2, CGU_PLL1CR(t1) + li t3, 0x80000000 +4: + lw t2, CGU_PLL1SR(t1) + and t2, t2, t3 + beq t2, zero, 4b + nop + li t2, 0x80000001 + sw t2, CGU_MUXCR(t1) +5: + j ra + nop + + .end cgu_init + + +/* + * void sdram_init(long) + * + * a0 has the clock value + */ + .globl sdram_init + .ent sdram_init +sdram_init: +__sdram_init: + + li t1, MC_MODUL_BASE + +#if 0 + /* Disable memory controller before changing any of its registers */ + sw zero, MC_CTRLENA(t1) +#endif + + li t2, 100000000 + beq a0, t2, 1f + nop + li t2, 133000000 + beq a0, t2, 2f + nop + li t2, 150000000 + beq a0, t2, 3f + nop + b 5f + nop + + /* 100 MHz clock */ +1: + /* Set clock ratio (clkrat=1:1, rddel=3) */ + li t2, 0x00000003 + sw t2, MC_IOGP(t1) + + /* Set sdram refresh rate (4K/64ms @ 100MHz) */ + li t2, 0x0000061A + b 4f + sw t2, MC_TREFRESH(t1) + + /* 133 MHz clock */ +2: + /* Set clock ratio (clkrat=1:1, rddel=3) */ + li t2, 0x00000003 + sw t2, MC_IOGP(t1) + + /* Set sdram refresh rate (4K/64ms @ 133MHz) */ + li t2, 0x00000822 + b 4f + sw t2, MC_TREFRESH(t1) + + /* 150 MHz clock */ +3: + /* Set clock ratio (clkrat=3:2, rddel=4) */ + li t2, 0x00000014 + sw t2, MC_IOGP(t1) + + /* Set sdram refresh rate (4K/64ms @ 150MHz) */ + li t2, 0x00000927 + sw t2, MC_TREFRESH(t1) + +4: + /* Clear Error log registers */ + sw zero, MC_ERRCAUSE(t1) + sw zero, MC_ERRADDR(t1) + + /* Clear Power-down registers */ + sw zero, MC_SELFRFSH(t1) + + /* Set CAS Latency */ + li t2, 0x00000020 /* CL = 2 */ + sw t2, MC_MRSCODE(t1) + + /* Set word width to 16 bit */ + li t2, 0x2 + sw t2, MC_CFGDW(t1) + + /* Set CS0 to SDRAM parameters */ + li t2, 0x000014C9 + sw t2, MC_CFGPB0(t1) + + /* Set SDRAM latency parameters */ + li t2, 0x00026325 /* BC PC100 */ + sw t2, MC_LATENCY(t1) + +5: + /* Finally enable the controller */ + li t2, 0x00000001 + sw t2, MC_CTRLENA(t1) + + j ra + nop + + .end sdram_init + + + .globl lowlevel_init + .ent lowlevel_init +lowlevel_init: + + /* EBU, CGU and SDRAM Initialization. + */ + li a0, CPU_CLOCK_RATE + move t0, ra + + /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init() + * modify t0 and a0. + */ + bal __cgu_init + nop + bal __ebu_init + nop + bal __sdram_init + nop + move ra, t0 + + j ra + nop + + .end lowlevel_init diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds new file mode 100644 index 0000000..10c9917 --- /dev/null +++ b/board/incaip/u-boot.lds @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile new file mode 100644 index 0000000..bf83292 --- /dev/null +++ b/board/inka4x0/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/inka4x0/config.mk b/board/inka4x0/config.mk new file mode 100644 index 0000000..cb19a7d --- /dev/null +++ b/board/inka4x0/config.mk @@ -0,0 +1,41 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# INKA 4X0 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFE00000 boot low +# +# 0x00100000 boot from RAM (for testing only) +# + +ifndef TEXT_BASE +## Standard: boot low +TEXT_BASE = 0xFFE00000 +## For testing: boot from RAM +#TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/inka4x0/flash.c b/board/inka4x0/flash.c new file mode 100644 index 0000000..b138655 --- /dev/null +++ b/board/inka4x0/flash.c @@ -0,0 +1,432 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * CPU to flash interface is 8-bit, so make declaration accordingly + */ +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + extern void flash_preinit(void); + ulong flashbase = CFG_FLASH_BASE; + + flash_preinit(); + + /* Init: no FLASHes known */ + memset(&flash_info[0], 0, sizeof(flash_info_t)); + + flash_info[0].size = + flash_get_size((FPW *)flashbase, &flash_info[0]); + + size = flash_info[0].size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM116DB: + printf ("AM29LV116DB (16Mbit, bottom boot sect)\n"); + break; + case FLASH_AMLV128U: + printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + int i; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(100); + switch (addr[0] & 0xff) { + + case (uchar)AMD_MANUFACT: + debug ("Manufacturer: AMD (Spansion)\n"); + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + debug ("Manufacturer: Intel (not supported yet)\n"); + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { + + case (uchar)AMD_ID_LV116DB: + debug ("Chip: AM29LV116DB\n"); + info->flash_id += FLASH_AM116DB; + info->sector_count = 35; + info->size = 0x00200000; + /* + * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all + * the other ones are 64 kB + */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for( i = 4; i < info->sector_count; i++ ) + info->start[i] = + base + (i * (64 << 10)) - 0x00030000; + break; /* => 2 MB */ + + case (FPW)AMD_ID_LV160B: + debug ("Chip: AM29LV160MB\n"); + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + /* + * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all + * the other ones are 64 kB + */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for( i = 4; i < info->sector_count; i++ ) + info->start[i] = + base + (i * 2 * (64 << 10)) - 0x00060000; + break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + } + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr = (FPWV*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = (FPW)0x00AA00AA; + addr[0x02AA] = (FPW)0x00550055; + addr[0x0555] = (FPW)0x00800080; + addr[0x0555] = (FPW)0x00AA00AA; + addr[0x02AA] = (FPW)0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FPWV*)(info->start[sect]); + addr[0] = (FPW)0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FPWV*)(info->start[l_sect]); + while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (FPWV*)info->start[0]; + addr[0] = (FPW)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + int i, rc = 0; + + for (i = 0; i < cnt; i++) + if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) { + return (rc); + } + + return rc; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + return (1); + } + } + return (0); +} diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c new file mode 100644 index 0000000..29878f9 --- /dev/null +++ b/board/inka4x0/inka4x0.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m16a2-75.h" +#endif + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + +/* return dramsize + dramsize2; */ + return dramsize; +} + +int checkboard (void) +{ + puts ("Board: INKA 4X0\n"); + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + +#define GPIO_WKUP_7 0x80000000UL +#define GPIO_PSC3_9 0x04000000UL + +int misc_init_f (void) +{ + uchar tmp[10]; + int i, br; + + i = getenv_r("brightness", tmp, sizeof(tmp)); + br = (i > 0) + ? (int) simple_strtoul (tmp, NULL, 10) + : CFG_BRIGHTNESS; + if (br > 255) + br = 255; + + /* Initialize GPIO output pins. + */ + /* Configure GPT as GPIO output (and set them as they control low-active LEDs */ + *(vu_long *)MPC5XXX_GPT0_ENABLE = + *(vu_long *)MPC5XXX_GPT1_ENABLE = + *(vu_long *)MPC5XXX_GPT2_ENABLE = + *(vu_long *)MPC5XXX_GPT3_ENABLE = + *(vu_long *)MPC5XXX_GPT4_ENABLE = + *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34; + + /* Configure GPT7 as PWM timer, 1kHz, no ints. */ + *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */ + *(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe; + *(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16); + *(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */ + + /* Configure PSC3_6,7 as GPIO output */ + *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000; + *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000; + + /* Configure PSC3_8 as GPIO output, no interrupt */ + *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000; + *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000; + *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000; + + /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */ + *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000; + *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000; + + /* Set LR mirror bit because it is low-active */ + *(vu_long *)MPC5XXX_WU_GPIO_DATA |= GPIO_WKUP_7; + /* + * Reset Coral-P graphics controller + */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9; + return 0; +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + /* Deassert reset */ + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(500000); + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + } +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h new file mode 100644 index 0000000..f650faa --- /dev/null +++ b/board/inka4x0/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h new file mode 100644 index 0000000..13a97ac --- /dev/null +++ b/board/inka4x0/mt48lc16m16a2-75.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ +/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ +#define SDRAM_CONFIG2 0x8AD70000 +/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/inka4x0/u-boot.lds b/board/inka4x0/u-boot.lds new file mode 100644 index 0000000..123a14c --- /dev/null +++ b/board/inka4x0/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xxx/start.o (.text) + cpu/mpc5xxx/traps.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/innokom/Makefile b/board/innokom/Makefile new file mode 100644 index 0000000..73f6a74 --- /dev/null +++ b/board/innokom/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := innokom.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/innokom/config.mk b/board/innokom/config.mk new file mode 100644 index 0000000..2354392 --- /dev/null +++ b/board/innokom/config.mk @@ -0,0 +1,15 @@ +# +# Linux-Kernel is expected to be at c000'8000, entry c000'8000 +# +# we load ourself to c170'0000, the upper 1 MB of second bank +# +# download areas is c800'0000 +# + +# This is the address where U-Boot lives in flash: +#TEXT_BASE = 0 + +# FIXME: armboot does only work correctly when being compiled +# for the addresses _after_ relocation to RAM!! Otherwhise the +# .bss segment is assumed in flash... +TEXT_BASE = 0xa1fe0000 diff --git a/board/innokom/flash.c b/board/innokom/flash.c new file mode 100644 index 0000000..298acc8 --- /dev/null +++ b/board/innokom/flash.c @@ -0,0 +1,419 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Robert Schwebel, Pengutronix, + * + * (C) Copyright 2002 + * Auerswald GmbH & Co KG, Germany + * Kai-Uwe Bloem + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Debugging macros ------------------------------------------------------ */ + +#undef FLASH_DEBUG + +/* Some debug macros */ +#if (FLASH_DEBUG > 2 ) +#define PRINTK3(args...) printf(args) +#else +#define PRINTK3(args...) +#endif + +#if FLASH_DEBUG > 1 +#define PRINTK2(args...) printf(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef FLASH_DEBUG +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + +/* ------------------------------------------------------------------------ */ + +/* Development system: we have only 16 MB Flash */ +#ifdef CONFIG_MTD_INNOKOM_16MB +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB (during development) */ +#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */ +#endif + +/* Production system: we have 64 MB Flash */ +#ifdef CONFIG_MTD_INNOKOM_64MB +#define FLASH_BANK_SIZE 0x04000000 /* 64 MB */ +#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */ +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/** + * flash_init: - initialize data structures for flash chips + * + * @return: size of the flash + */ + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F128J3 & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + + switch (i) { + case 0: + flashbase = PHYS_FLASH_1; + break; + default: + panic("configured too many flash banks!\n"); + break; + } + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; + } + size += flash_info[i].size; + } + + /* Protect u-boot sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + (256*1024) - 1, + &flash_info[0]); + +#ifdef CFG_ENV_IS_IN_FLASH + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return size; +} + + +/** + * flash_print_info: - print information about the flash situation + * + * @param info: + */ + +void flash_print_info (flash_info_t *info) +{ + int i, j; + + for (j=0; jflash_id & FLASH_VENDMASK) { + + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf("Intel: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + + case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): + printf("28F128J3 (128Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) printf ("\n "); + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + info++; + } +} + + +/** + * flash_erase: - erase flash sectors + * + */ + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + int rc = ERR_OK; + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) prot++; + } + + if (prot) return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { + + printf("Erasing sector %2d ... ", sect); + + PRINTK("\n"); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + if (info->protect[sect] == 0) { /* not protected */ + u16 * volatile addr = (u16 * volatile)(info->start[sect]); + + PRINTK("unlocking sector\n"); + *addr = 0x0060; + *addr = 0x00d0; + *addr = 0x00ff; + + PRINTK("erasing sector\n"); + *addr = 0x0020; + PRINTK("confirming erase\n"); + *addr = 0x00D0; + + while ((*addr & 0x0080) != 0x0080) { + PRINTK("."); + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + *addr = 0x00B0; /* suspend erase*/ + *addr = 0x00FF; /* read mode */ + rc = ERR_TIMOUT; + goto outahere; + } + } + + PRINTK("clearing status register\n"); + *addr = 0x0050; + PRINTK("resetting to read mode"); + *addr = 0x00FF; + } + + printf("ok.\n"); + } + + if (ctrlc()) printf("User Interrupt!\n"); + + outahere: + + /* allow flash to settle - wait 10 ms */ + udelay_masked(10000); + + if (flag) enable_interrupts(); + + return rc; +} + + +/** + * write_word: - copy memory to flash + * + * @param info: + * @param dest: + * @param data: + * @return: + */ + +static int write_word (flash_info_t *info, ulong dest, ushort data) +{ + volatile u16 *addr = (u16 *)dest, val; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts(); + + /* clear status register command */ + *addr = 0x50; + + /* program set-up command */ + *addr = 0x40; + + /* latch address/data */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + /* wait while polling the status register */ + while(((val = *addr) & 0x80) != 0x80) { + if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { + rc = ERR_TIMOUT; + *addr = 0xB0; /* suspend program command */ + goto outahere; + } + } + + if(val & 0x1A) { /* check for error */ + printf("\nFlash write error %02x at address %08lx\n", + (int)val, (unsigned long)dest); + if(val & (1<<3)) { + printf("Voltage range error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + if(val & (1<<1)) { + printf("Device protect error.\n"); + rc = ERR_PROTECTED; + goto outahere; + } + if(val & (1<<4)) { + printf("Programming error.\n"); + rc = ERR_PROG_ERROR; + goto outahere; + } + rc = ERR_PROG_ERROR; + goto outahere; + } + + outahere: + + *addr = 0xFF; /* read array command */ + if (flag) enable_interrupts(); + + return rc; +} + + +/** + * write_buf: - Copy memory to flash. + * + * @param info: + * @param src: source of copy transaction + * @param addr: where to copy to + * @param cnt: number of bytes to copy + * + * @return error code + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + ushort data; + int l; + int i, rc; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 8); + } + for (; i<2 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt==0 && i<2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 8); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + /* data = *((vushort*)src); */ + data = *((ushort*)src); + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i<2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 8); + } + + return write_word(info, wp, data); +} diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c new file mode 100644 index 0000000..ae5402e --- /dev/null +++ b/board/innokom/innokom.c @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2002 + * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de + * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net + * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +/** + * i2c_init_board - reset i2c bus. When the board is powercycled during a + * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. + * The Innokom board has GPIO70 connected to SCLK which can be toggled + * until all chips think that their current cycles are finished. + */ +int i2c_init_board(void) +{ + int i, icr; + + /* disable I2C controller first, otherwhise it thinks we want to */ + /* talk to the slave port... */ + icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE); + + /* set gpio pin low _before_ we change direction to output */ + GPCR(70) = GPIO_bit(70); + + /* now toggle between output=low and high-impedance */ + for (i = 0; i < 20; i++) { + GPDR(70) |= GPIO_bit(70); /* output */ + udelay(10); + GPDR(70) &= ~GPIO_bit(70); /* input */ + udelay(10); + } + + ICR = icr; + + return 0; +} + + +/** + * misc_init_r: - misc initialisation routines + */ + +int misc_init_r(void) +{ + uchar *str; + + /* determine if the software update key is pressed during startup */ + if (GPLR0 & 0x00000800) { + printf("using bootcmd_normal (sw-update button not pressed)\n"); + str = getenv("bootcmd_normal"); + } else { + printf("using bootcmd_update (sw-update button pressed)\n"); + str = getenv("bootcmd_update"); + } + + setenv("bootcmd",str); + + return 0; +} + + +/** + * board_init: - setup some data structures + * + * @return: 0 in case of success + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + gd->bd->bi_arch_number = MACH_TYPE_INNOKOM; + gd->bd->bi_boot_params = 0xa0000100; + gd->bd->bi_baudrate = CONFIG_BAUDRATE; + + return 0; +} + + +/** + * dram_init: - setup dynamic RAM + * + * @return: 0 in case of success + */ + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + + +/** + * innokom_set_led: - switch LEDs on or off + * + * @param led: LED to switch (0,1,2) + * @param state: switch on (1) or off (0) + */ + +void innokom_set_led(int led, int state) +{ + switch(led) { +/* + case 0: if (state==1) { + GPCR0 |= CSB226_USER_LED0; + } else if (state==0) { + GPSR0 |= CSB226_USER_LED0; + } + break; + + case 1: if (state==1) { + GPCR0 |= CSB226_USER_LED1; + } else if (state==0) { + GPSR0 |= CSB226_USER_LED1; + } + break; + + case 2: if (state==1) { + GPCR0 |= CSB226_USER_LED2; + } else if (state==0) { + GPSR0 |= CSB226_USER_LED2; + } + break; +*/ + } + + return; +} + + +/** + * show_boot_progress: - indicate state of the boot process + * + * @param status: Status number - see README for details. + * + * The CSB226 does only have 3 LEDs, so we switch them on at the most + * important states (1, 5, 15). + */ + +void show_boot_progress (int status) +{ + switch(status) { +/* + case 1: csb226_set_led(0,1); break; + case 5: csb226_set_led(1,1); break; + case 15: csb226_set_led(2,1); break; +*/ + } + + return; +} diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S new file mode 100644 index 0000000..aa9dcba --- /dev/null +++ b/board/innokom/lowlevel_init.S @@ -0,0 +1,437 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + +_TEXT_BASE: + .word TEXT_BASE + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + +/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ +/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ +/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ +/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ +/* */ +/* ldr r1, =LED_BLANK */ +/* mov r0, #0xFF */ +/* str r0, [r1] / turn on hex leds */ +/* */ +/*loop: */ +/* */ +/* ldr r0, =0xB0070001 */ +/* ldr r1, =_LED */ +/* str r0, [r1] / hex display */ + + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ + adr r3, mem_init /* r0 <- current position of code */ + ldr r2, =mem_init + cmp r3, r2 /* skip init if in place */ + beq initirqs + + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + /* Step 4a: assert MDREFR:K?RUN and configure */ + /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ + + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4b: de-assert MDREFR:SLFRSH. */ + + bic r4, r4, #(MDREFR_SLFRSH) + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4c: assert MDREFR:E1PIN and E0PIO */ + + orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + /* There should 9 writes, since the first write doesn't */ + /* trigger a refresh cycle on PXA250. See Intel PXA250 and */ + /* PXA210 Processors Specification Update, */ + /* Jan 2003, Errata #116, page 30. */ + + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + + /* We are finished with Intel's memory controller initialisation */ + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + /* (hard-coding at 398.12MHz for now). */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + + /* default value in case no valid rotary switch setting is found */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + + /* enable the 32Khz oscillator for RTC and PowerManager */ +/* + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] +*/ + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size */ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + + /* FIXME */ + +#ifndef DEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/innokom/u-boot.lds b/board/innokom/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/innokom/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/integratorap/Makefile b/board/integratorap/Makefile new file mode 100644 index 0000000..358df62 --- /dev/null +++ b/board/integratorap/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2004 +# ARM Ltd. +# Philippe Robin, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := integratorap.o flash.o +SOBJS := lowlevel_init.o memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/integratorap/config.mk b/board/integratorap/config.mk new file mode 100644 index 0000000..25b79b3 --- /dev/null +++ b/board/integratorap/config.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x01000000 +# + +TEXT_BASE = 0x01000000 diff --git a/board/integratorap/flash.c b/board/integratorap/flash.c new file mode 100644 index 0000000..b120d63 --- /dev/null +++ b/board/integratorap/flash.c @@ -0,0 +1,473 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, 32 * 1024}, /* 4 * 32kBytes sectors */ + {255, 128 * 1024}, /* 255 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + OrgDef *pOrgDef; + + pOrgDef = OrgIntel_28F256L18T; + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 255) { + info->start[i] = base + (i * 0x8000); + info->protect[i] = 0; + } else { + info->start[i] = base + + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; + info->size = 0x02000000; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + flash_unprotect_sectors (addr); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c new file mode 100644 index 0000000..d4f61d6 --- /dev/null +++ b/board/integratorap/integratorap.c @@ -0,0 +1,651 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_PCI +#include +#endif + +void flash__init (void); +void ether__init (void); +void peripheral_power_enable (void); + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of Integrator Board */ + gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + gd->flags = 0; + +#ifdef CONFIG_CM_REMAP +extern void cm_remap(void); + cm_remap(); /* remaps writeable memory to 0x00000000 */ +#endif + + icache_enable (); + + flash__init (); + return 0; +} + + +int misc_init_r (void) +{ +#ifdef CONFIG_PCI + pci_init(); +#endif + setenv("verify", "n"); + return (0); +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifdef CONFIG_PCI + +#ifndef CONFIG_PCI_PNP + +static struct pci_config_table pci_integrator_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { } +}; +#endif + +/* V3 access routines */ +#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v)) +#define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o))) + +#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v)) +#define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o))) + +/* Compute address necessary to access PCI config space for the given */ +/* bus and device. */ +#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \ + unsigned int __address, __devicebit; \ + unsigned short __mapaddress; \ + unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \ + \ + if (__bus == 0) { \ + /* local bus segment so need a type 0 config cycle */ \ + /* build the PCI configuration "address" with one-hot in A31-A11 */ \ + __address = PCI_CONFIG_BASE; \ + __address |= ((__devfn & 0x07) << 8); \ + __address |= __offset & 0xFF; \ + __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \ + __devicebit = (1 << (__dev + 11)); \ + \ + if ((__devicebit & 0xFF000000) != 0) { \ + /* high order bits are handled by the MAP register */ \ + __mapaddress |= (__devicebit >> 16); \ + } else { \ + /* low order bits handled directly in the address */ \ + __address |= __devicebit; \ + } \ + } else { /* bus !=0 */ \ + /* not the local bus segment so need a type 1 config cycle */ \ + /* A31-A24 are don't care (so clear to 0) */ \ + __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \ + __address = PCI_CONFIG_BASE; \ + __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \ + __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \ + __address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \ + __address |= __offset & 0xFF; /* bits 7..0 = register number */ \ + } \ + _V3Write16 (V3_LB_MAP1, __mapaddress); \ + __address; \ +}) + +/* _V3OpenConfigWindow - open V3 configuration window */ +#define _V3OpenConfigWindow() { \ + /* Set up base0 to see all 512Mbytes of memory space (not */ \ + /* prefetchable), this frees up base1 for re-use by configuration*/ \ + /* memory */ \ + \ + _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ + 0x90 | V3_LB_BASE_M_ENABLE)); \ + /* Set up base1 to point into configuration space, note that MAP1 */ \ + /* register is set up by pciMakeConfigAddress(). */ \ + \ + _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \ + 0x40 | V3_LB_BASE_M_ENABLE)); \ +} + +/* _V3CloseConfigWindow - close V3 configuration window */ +#define _V3CloseConfigWindow() { \ + /* Reassign base1 for use by prefetchable PCI memory */ \ + _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \ + | 0x84 | V3_LB_BASE_M_ENABLE)); \ + _V3Write16 (V3_LB_MAP1, \ + (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \ + \ + /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \ + \ + _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ + 0x80 | V3_LB_BASE_M_ENABLE)); \ +} + +static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev, + int offset, unsigned char *val) +{ + _V3OpenConfigWindow (); + *val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), + PCI_FUNC (dev), + offset); + _V3CloseConfigWindow (); + + return 0; +} + +static int pci_integrator_read__word (struct pci_controller *hose, + pci_dev_t dev, int offset, + unsigned short *val) +{ + _V3OpenConfigWindow (); + *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), + PCI_FUNC (dev), + offset); + _V3CloseConfigWindow (); + + return 0; +} + +static int pci_integrator_read_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, + unsigned int *val) +{ + _V3OpenConfigWindow (); + *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), + PCI_FUNC (dev), + offset); + *val |= (*(volatile unsigned int *) + PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev), + (offset + 2))) << 16; + _V3CloseConfigWindow (); + + return 0; +} + +static int pci_integrator_write_byte (struct pci_controller *hose, + pci_dev_t dev, int offset, + unsigned char val) +{ + _V3OpenConfigWindow (); + *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), + PCI_FUNC (dev), + offset) = val; + _V3CloseConfigWindow (); + + return 0; +} + +static int pci_integrator_write_word (struct pci_controller *hose, + pci_dev_t dev, int offset, + unsigned short val) +{ + _V3OpenConfigWindow (); + *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), + PCI_FUNC (dev), + offset) = val; + _V3CloseConfigWindow (); + + return 0; +} + +static int pci_integrator_write_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, + unsigned int val) +{ + _V3OpenConfigWindow (); + *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), + PCI_FUNC (dev), + offset) = (val & 0xFFFF); + *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), + PCI_FUNC (dev), + (offset + 2)) = ((val >> 16) & 0xFFFF); + _V3CloseConfigWindow (); + + return 0; +} +/****************************** + * PCI initialisation + ******************************/ + +struct pci_controller integrator_hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_integrator_config_table, +#endif +}; + +void pci_init_board (void) +{ + volatile int i, j; + struct pci_controller *hose = &integrator_hose; + + /* setting this register will take the V3 out of reset */ + + *(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1; + + /* wait a few usecs to settle the device and the PCI bus */ + + for (i = 0; i < 100; i++) + j = i + 1; + + /* Now write the Base I/O Address Word to V3_BASE + 0x6C */ + + *(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) = + (unsigned short) (V3_BASE >> 16); + + do { + *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA; + *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) = + 0x55; + } while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA + || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + + 4) != 0x55); + + /* Make sure that V3 register access is not locked, if it is, unlock it */ + + if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) & + V3_SYSTEM_M_LOCK) + == V3_SYSTEM_M_LOCK) + *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F; + + /* Ensure that the slave accesses from PCI are disabled while we */ + /* setup windows */ + + *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &= + ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); + + /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ + + *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &= + ~V3_SYSTEM_M_RST_OUT; + + /* Make all accesses from PCI space retry until we're ready for them */ + + *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |= + V3_PCI_CFG_M_RETRY_EN; + + /* Set up any V3 PCI Configuration Registers that we absolutely have to */ + /* LB_CFG controls Local Bus protocol. */ + /* Enable LocalBus byte strobes for READ accesses too. */ + /* set bit 7 BE_IMODE and bit 6 BE_OMODE */ + + *(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0; + + /* PCI_CMD controls overall PCI operation. */ + /* Enable PCI bus master. */ + + *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04; + + /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */ + + *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) = + (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M | + V3_PCI_MAP_M_REG_EN | + V3_PCI_MAP_M_ENABLE); + + /* PCI_BASE0 is the PCI address of the start of the window */ + + *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) = + INTEGRATOR_BOOT_ROM_BASE; + + /* PCI_MAP1 is LOCAL address of the start of the window */ + + *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) = + (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M | + V3_PCI_MAP_M_REG_EN | + V3_PCI_MAP_M_ENABLE); + + /* PCI_BASE1 is the PCI address of the start of the window */ + + *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) = + INTEGRATOR_HDR0_SDRAM_BASE; + + /* Set up the windows from local bus memory into PCI configuration, */ + /* I/O and Memory. */ + /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */ + + *(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) = + ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE; + *(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0; + + /* PCI Configuration, use LB_BASE1/LB_MAP1. */ + + /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */ + /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */ + /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */ + + *(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) = + INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE); + + *(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) = + ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006; + + /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ + + *(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) = + INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE); + + *(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) = + (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006; + + /* Allow accesses to PCI Configuration space */ + /* and set up A1, A0 for type 1 config cycles */ + + *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) = + ((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) & + ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) | + V3_PCI_CFG_M_AD_LOW0; + + /* now we can allow in PCI MEMORY accesses */ + + *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) = + (*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) | + V3_COMMAND_M_MEM_EN; + + /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */ + /* initialise and lock the V3 system register so that no one else */ + /* can play with it */ + + *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = + (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | + V3_SYSTEM_M_RST_OUT; + + *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = + (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | + V3_SYSTEM_M_LOCK; + + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region (hose->regions + 0, + 0x00000000, 0x40000000, 0x01000000, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI Memory - config space */ + pci_set_region (hose->regions + 1, + 0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM); + + /* PCI V3 regs */ + pci_set_region (hose->regions + 2, + 0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (hose->regions + 3, + 0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO); + + pci_set_ops (hose, + pci_integrator_read_byte, + pci_integrator_read__word, + pci_integrator_read_dword, + pci_integrator_write_byte, + pci_integrator_write_word, pci_integrator_write_dword); + + hose->region_count = 4; + + pci_register_hose (hose); + + pciauto_config_init (hose); + pciauto_config_device (hose, 0); + + hose->last_busno = pci_hose_scan (hose); +} +#endif + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ +} +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + +#ifdef CONFIG_CM_SPD_DETECT + { +extern void dram_query(void); + unsigned long cm_reg_sdram; + unsigned long sdram_shift; + + dram_query(); /* Assembler accesses to CM registers */ + /* Queries the SPD values */ + + /* Obtain the SDRAM size from the CM SDRAM register */ + + cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM); + /* Register SDRAM size + * + * 0xXXXXXXbbb000bb 16 MB + * 0xXXXXXXbbb001bb 32 MB + * 0xXXXXXXbbb010bb 64 MB + * 0xXXXXXXbbb011bb 128 MB + * 0xXXXXXXbbb100bb 256 MB + * + */ + sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; + gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; + + } +#endif /* CM_SPD_DETECT */ + + return 0; +} + +/* The Integrator/AP timer1 is clocked at 24MHz + * can be divided by 16 or 256 + * and is a 16-bit counter + */ +/* U-Boot expects a 32 bit timer running at CFG_HZ*/ +static ulong timestamp; /* U-Boot ticks since startup */ +static ulong total_count = 0; /* Total timer count */ +static ulong lastdec; /* Timer reading at last call */ +static ulong div_clock = 256; /* Divisor applied to the timer clock */ +static ulong div_timer = 1; /* Divisor to convert timer reading + * change to U-Boot ticks + */ +/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */ + +#define TIMER_LOAD_VAL 0x0000FFFFL +#define READ_TIMER ((*(volatile ulong *)(CFG_TIMERBASE+4)) & 0x0000FFFFL) + +/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec + * - unless otherwise stated + */ + +/* starts a counter + * - the Integrator/AP timer issues an interrupt + * each time it reaches zero + */ +int interrupt_init (void) +{ + /* Load timer with initial value */ + *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL; + /* Set timer to be + * enabled 1 + * free-running 0 + * XX 00 + * divider 256 10 + * XX 00 + */ + *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x00000088; + total_count = 0; + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + div_timer = CFG_HZ_CLOCK / CFG_HZ; + div_timer /= div_clock; + + return (0); +} + +/* + * timer without interrupts + */ +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base_ticks) +{ + return get_timer_masked () - base_ticks; +} + +void set_timer (ulong ticks) +{ + timestamp = ticks; + total_count = ticks * div_timer; + reset_timer_masked(); +} + +/* delay x useconds */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + /* Convert to U-Boot ticks */ + tmo = usec * CFG_HZ; + tmo /= (1000000L); + + tmp = get_timer_masked(); /* get current timestamp */ + tmo += tmp; /* wake up timestamp */ + + while (get_timer_masked () < tmo) { /* loop till event */ + /*NOP*/; + } +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capture current decrementer value */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +/* converts the timer reading to U-Boot ticks */ +/* the timestamp is the number of ticks since reset */ +/* This routine does not detect wraps unless called regularly + ASSUMES a call at least every 16 seconds to detect every reload */ +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current count */ + + if (now > lastdec) { + /* Must have wrapped */ + total_count += lastdec + TIMER_LOAD_VAL + 1 - now; + } else { + total_count += lastdec - now; + } + lastdec = now; + timestamp = total_count/div_timer; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * Return the timebase clock frequency + * i.e. how often the timer decrements + */ +ulong get_tbclk (void) +{ + return CFG_HZ_CLOCK/div_clock; +} diff --git a/board/integratorap/lowlevel_init.S b/board/integratorap/lowlevel_init.S new file mode 100644 index 0000000..ab9589c --- /dev/null +++ b/board/integratorap/lowlevel_init.S @@ -0,0 +1,213 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004, ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + /* Reset using CM control register */ +.global reset_cpu +reset_cpu: + mov r0, #CM_BASE + ldr r1,[r0,#OS_CTRL] + orr r1,r1,#CMMASK_RESET + str r1,[r0,#OS_CTRL] + +reset_failed: + b reset_failed + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + /* If U-Boot has been run after the ARM boot monitor + * then all the necessary actions have been done + * otherwise we are running from user flash mapped to 0x00000000 + * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED -- + * Changes to the (possibly soft) reset defaults of the processor + * itself should be performed in cpu/arm<>/start.S + * This function affects only the core module or board settings + */ + +#ifdef CONFIG_CM_INIT + /* CM has an initialization register + * - bits in it are wired into test-chip pins to force + * reset defaults + * - may need to change its contents for U-Boot + */ + + /* set the desired CM specific value */ + mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */ + +#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) + orr r2,r2,#CMMASK_INIT_102 +#else + +#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ + !defined (CONFIG_CM940T) + +#ifdef CONFIG_CM_MULTIPLE_SSRAM + /* set simple mapping */ + and r2,r2,#CMMASK_MAP_SIMPLE +#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ + +#ifdef CONFIG_CM_TCRAM + /* disable TCRAM */ + and r2,r2,#CMMASK_TCRAM_DISABLE +#endif /* #ifdef CONFIG_CM_TCRAM */ + +#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ + defined (CONFIG_CM1136JF_S) + + and r2,r2,#CMMASK_LE + +#endif /* cpu with little endian initialization */ + + orr r2,r2,#CMMASK_CMxx6_COMMON + +#endif /* CMxx6 code */ + +#endif /* ARM102xxE value */ + + /* read CM_INIT */ + mov r0, #CM_BASE + ldr r1, [r0, #OS_INIT] + /* check against desired bit setting */ + and r3,r1,r2 + cmp r3,r2 + beq init_reg_OK + + /* lock for change */ + mov r3, #CMVAL_LOCK1 + add r3,r3,#CMVAL_LOCK2 + str r3, [r0, #OS_LOCK] + /* set desired value */ + orr r1,r1,r2 + /* write & relock CM_INIT */ + str r1, [r0, #OS_INIT] + mov r1, #CMVAL_UNLOCK + str r1, [r0, #OS_LOCK] + + /* soft reset so new values used */ + b reset_cpu + +init_reg_OK: + +#endif /* CONFIG_CM_INIT */ + + mov pc, lr + +#ifdef CONFIG_CM_SPD_DETECT + /* Fast memory is available for the DRAM data + * - ensure it has been transferred, then summarize the data + * into a CM register + */ +.globl dram_query +dram_query: + stmfd r13!,{r4-r6,lr} + /* set up SDRAM info */ + /* - based on example code from the CM User Guide */ + mov r0, #CM_BASE + +readspdbit: + ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ + and r1, r1, #0x20 /* mask SPD bit (5) */ + cmp r1, #0x20 /* test if set */ + bne readspdbit + +setupsdram: + add r0, r0, #OS_SPD /* address the copy of the SDP data */ + ldrb r1, [r0, #3] /* number of row address lines */ + ldrb r2, [r0, #4] /* number of column address lines */ + ldrb r3, [r0, #5] /* number of banks */ + ldrb r4, [r0, #31] /* module bank density */ + mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ + mov r5, r5, ASL#2 /* size in MB */ + mov r0, #CM_BASE /* reload for later code */ + cmp r5, #0x10 /* is it 16MB? */ + bne not16 + mov r6, #0x2 /* store size and CAS latency of 2 */ + b writesize + +not16: + cmp r5, #0x20 /* is it 32MB? */ + bne not32 + mov r6, #0x6 + b writesize + +not32: + cmp r5, #0x40 /* is it 64MB? */ + bne not64 + mov r6, #0xa + b writesize + +not64: + cmp r5, #0x80 /* is it 128MB? */ + bne not128 + mov r6, #0xe + b writesize + +not128: + /* if it is none of these sizes then it is either 256MB, or + * there is no SDRAM fitted so default to 256MB + */ + mov r6, #0x12 + +writesize: + mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */ + orr r2, r1, r2, ASL#12 /* OR in column address lines */ + orr r3, r2, r3, ASL#16 /* OR in number of banks */ + orr r6, r6, r3 /* OR in size and CAS latency */ + str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */ + +#endif /* #ifdef CONFIG_CM_SPD_DETECT */ + + ldmfd r13!,{r4-r6,pc} /* back to caller */ + +#ifdef CONFIG_CM_REMAP + /* CM remap bit is operational + * - use it to map writeable memory at 0x00000000, in place of flash + */ +.globl cm_remap +cm_remap: + stmfd r13!,{r4-r10,lr} + + mov r0, #CM_BASE + ldr r1, [r0, #OS_CTRL] + orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ + str r1, [r0, #OS_CTRL] + + /* Now 0x00000000 is writeable, replace the vectors */ + ldr r0, =_start /* r0 <- start of vectors */ + ldr r2, =_armboot_start /* r2 <- past vectors */ + sub r1,r1,r1 /* destination 0x00000000 */ + +copy_vec: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + ble copy_vec + + ldmfd r13!,{r4-r10,pc} /* back to caller */ + +#endif /* #ifdef CONFIG_CM_REMAP */ diff --git a/board/integratorap/memsetup.S b/board/integratorap/memsetup.S new file mode 100644 index 0000000..dfdc784 --- /dev/null +++ b/board/integratorap/memsetup.S @@ -0,0 +1,29 @@ +/* + * Memory setup for integratorAP + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Memory setup + * - the reset defaults are assumed sufficient + */ + +.globl memsetup +memsetup: + mov pc,lr diff --git a/board/integratorap/split_by_variant.sh b/board/integratorap/split_by_variant.sh new file mode 100755 index 0000000..9f71bab --- /dev/null +++ b/board/integratorap/split_by_variant.sh @@ -0,0 +1,116 @@ +#!/bin/sh +# --------------------------------------------------------- +# Set the platform defines +# --------------------------------------------------------- +echo -n "/* Integrator configuration implied " > tmp.fil +echo " by Makefile target */" >> tmp.fil +echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil +echo " /* Integrator board */" >> tmp.fil +echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil +echo " 1 /* Integrator/AP */" >> tmp.fil +# --------------------------------------------------------- +# Set the core module defines according to Core Module +# --------------------------------------------------------- +cpu="arm_intcm" +variant="unknown core module" + +if [ "$1" == "" ] +then + echo "$0:: No parameters - using arm_intcm" +else + case "$1" in + ap7_config) + cpu="arm_intcm" + variant="unported core module CM7TDMI" + ;; + + ap966) + cpu="arm_intcm" + variant="unported core module CM966E-S" + ;; + + ap922_config) + cpu="arm_intcm" + variant="unported core module CM922T" + ;; + + integratorap_config | \ + ap_config) + cpu="arm_intcm" + variant="unspecified core module" + ;; + + ap720t_config) + cpu="arm720t" + echo -n "#define CONFIG_CM720T" >> tmp.fil + echo " 1 /* CPU core is ARM720T */ " >> tmp.fil + variant="Core module CM720T" + ;; + + ap922_XA10_config) + cpu="arm_intcm" + variant="unported core module CM922T_XA10" + echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil + echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil + ;; + + ap920t_config) + cpu="arm920t" + variant="Core module CM920T" + echo -n "#define CONFIG_CM920T" >> tmp.fil + echo " 1 /* CPU core is ARM920T */" >> tmp.fil + ;; + + ap926ejs_config) + cpu="arm926ejs" + variant="Core module CM926EJ-S" + echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil + echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil + ;; + + ap946es_config) + cpu="arm946es" + variant="Core module CM946E-S" + echo -n "#define CONFIG_CM946E_S" >> tmp.fil + echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil + ;; + + *) + echo "$0:: Unknown core module" + variant="unknown core module" + cpu="arm_intcm" + ;; + + esac +fi + +if [ "$cpu" == "arm_intcm" ] +then + echo "/* Core module undefined/not ported */" >> tmp.fil + echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil + echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "multiple SSRAM mapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil + echo -n " /* CM may not support SPD " >> tmp.fil + echo "query */" >> tmp.fil + echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil + echo -n " /* CM may not support " >> tmp.fil + echo "remapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_INIT " >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "initialization reg */" >> tmp.fil + echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil + echo " /* CM may not have TCRAM */" >> tmp.fil +fi +mv tmp.fil ./include/config.h +# --------------------------------------------------------- +# Ensure correct core object loaded first in U-Boot image +# --------------------------------------------------------- +sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorap/u-boot.lds.template > board/integratorap/u-boot.lds +# --------------------------------------------------------- +# Complete the configuration +# --------------------------------------------------------- +./mkconfig -a integratorap arm $cpu integratorap; +echo "Variant:: $variant with core $cpu" + diff --git a/board/integratorap/u-boot.lds.template b/board/integratorap/u-boot.lds.template new file mode 100644 index 0000000..0ec8087 --- /dev/null +++ b/board/integratorap/u-boot.lds.template @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +# Template used during configuration to emsure the core module processor code, +# from CPU_FILE, is placed at the start of the image */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + CPU_FILE (.text) + *(.text) + } + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/integratorcp/Makefile b/board/integratorcp/Makefile new file mode 100644 index 0000000..3d589fc --- /dev/null +++ b/board/integratorcp/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := integratorcp.o flash.o +SOBJS := lowlevel_init.o memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/integratorcp/config.mk b/board/integratorcp/config.mk new file mode 100644 index 0000000..25b79b3 --- /dev/null +++ b/board/integratorcp/config.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x01000000 +# + +TEXT_BASE = 0x01000000 diff --git a/board/integratorcp/flash.c b/board/integratorcp/flash.c new file mode 100644 index 0000000..4d6eff0 --- /dev/null +++ b/board/integratorcp/flash.c @@ -0,0 +1,564 @@ +/* + * (C) Copyright 2004 + * Xiaogeng (Shawn) Jin, Agilent Technologies, xiaogeng_jin@agilent.com + * + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define DEBUG + +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, 32 * 1024}, /* 4 * 32kBytes sectors */ + {255, 128 * 1024}, /* 255 * 128kBytes sectors */ +}; + +/* CP control register base address */ +#define CPCR_BASE 0xCB000000 +#define CPCR_EXTRABANK 0x8 +#define CPCR_FLASHSIZE 0x4 +#define CPCR_FLWREN 0x2 +#define CPCR_FLVPPEN 0x1 + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + int i, nbanks; + ulong size = 0; + vu_long *cpcr = (vu_long *)CPCR_BASE; + + /* Check if there is an extra bank of flash */ + if (cpcr[1] & CPCR_EXTRABANK) + nbanks = 2; + else + nbanks = 1; + + if (nbanks > CFG_MAX_FLASH_BANKS) + nbanks = CFG_MAX_FLASH_BANKS; + + /* Enable flash write */ + cpcr[1] |= 3; + + for (i = 0; i < nbanks; i++) { + flash_get_size ((FPW *)(CFG_FLASH_BASE + size), &flash_info[i]); + flash_get_offsets (CFG_FLASH_BASE + size, &flash_info[i]); + size += flash_info[i].size; + } + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + /* Protect SIB (0x24800000) and bootMonitor (0x24c00000) */ + flash_protect (FLAG_PROTECT_SET, + flash_info[0].start[62], + flash_info[0].start[63] + PHYS_FLASH_SECT_SIZE - 1, + &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + /* Integrator CP board uses 28F640J3C or 28F128J3C parts, + * which have the same device id numbers as 28F640J3A or + * 28F128J3A + */ + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + case FLASH_28F640J3A: + printf ("FLASH 28F640J3C\n"); + break; + case FLASH_28F128J3A: + printf ("FLASH 28F128J3C\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + vu_long *cpcr = (vu_long *)CPCR_BASE; + int nsects; + + /* Check the flash size */ + if (cpcr[1] & CPCR_FLASHSIZE) + nsects = 128; + else + nsects = 64; + + if (nsects > CFG_MAX_FLASH_SECT) + nsects = CFG_MAX_FLASH_SECT; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; + info->size = 0x02000000; + break; /* => 32 MB */ + + case (FPW) (INTEL_ID_28F640J3A): + info->flash_id += FLASH_28F640J3A; + info->sector_count = nsects; + info->size = nsects * PHYS_FLASH_SECT_SIZE; + break; + + case (FPW) (INTEL_ID_28F128J3A): + info->flash_id += FLASH_28F128J3A; + info->sector_count = nsects; + info->size = nsects * PHYS_FLASH_SECT_SIZE; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ + FPW status; + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; + + reset_timer_masked(); + while (((status = *addr) & (FPW)0x00800080) != 0x00800080) { + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + printf("Timeout"); + break; + } + } + + *addr = (FPW) 0x00FF00FF; +} + + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* flash_unprotect_sectors (addr); */ + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + mb(); + + udelay(1000); /* Let's wait 1 ms */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + *addr = (FPW)0x00700070; + status = *addr; + if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) { + /* erase suspended? Resume it */ + reset_timer_masked(); + *addr = (FPW) 0x00D000D0; + } else { +#ifdef DEBUG + printf ("Timeout,0x%08x\n", status); +#else + printf("Timeout\n"); +#endif + + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + } + + *addr = (FPW) 0x00FF00FF; /* resest to read mode */ + printf (" done\n"); + } + } + + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* flash_unprotect_sectors (addr); */ + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + mb(); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { +#ifdef DEBUG + *addr = (FPW) 0x00700070; + status = *addr; + printf("## status=0x%08x, addr=0x%08x\n", status, addr); +#endif + *addr = (FPW) 0x00500050; /* clear status register cmd */ + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/integratorcp/integratorcp.c b/board/integratorcp/integratorcp.c new file mode 100644 index 0000000..216876b --- /dev/null +++ b/board/integratorcp/integratorcp.c @@ -0,0 +1,276 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +void flash__init (void); +void ether__init (void); +void peripheral_power_enable (void); + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of Integrator Board */ + gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + gd->flags = 0; + +#ifdef CONFIG_CM_REMAP +extern void cm_remap(void); + cm_remap(); /* remaps writeable memory to 0x00000000 */ +#endif + + icache_enable (); + + flash__init (); + ether__init (); + return 0; +} + + +int misc_init_r (void) +{ + setenv("verify", "n"); + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ +} +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + +#ifdef CONFIG_CM_SPD_DETECT + { +extern void dram_query(void); + unsigned long cm_reg_sdram; + unsigned long sdram_shift; + + dram_query(); /* Assembler accesses to CM registers */ + /* Queries the SPD values */ + + /* Obtain the SDRAM size from the CM SDRAM register */ + + cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM); + /* Register SDRAM size + * + * 0xXXXXXXbbb000bb 16 MB + * 0xXXXXXXbbb001bb 32 MB + * 0xXXXXXXbbb010bb 64 MB + * 0xXXXXXXbbb011bb 128 MB + * 0xXXXXXXbbb100bb 256 MB + * + */ + sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; + gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; + + } +#endif /* CM_SPD_DETECT */ + + return 0; +} + +/* The Integrator/CP timer1 is clocked at 1MHz + * can be divided by 16 or 256 + * and can be set up as a 32-bit timer + */ +/* U-Boot expects a 32 bit timer, running at CFG_HZ */ +/* Keep total timer count to avoid losing decrements < div_timer */ +static unsigned long long total_count = 0; +static unsigned long long lastdec; /* Timer reading at last call */ +static unsigned long long div_clock = 1; /* Divisor applied to timer clock */ +static unsigned long long div_timer = 1; /* Divisor to convert timer reading + * change to U-Boot ticks + */ +/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */ +static ulong timestamp; /* U-Boot ticks since startup */ + +#define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF) +#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4)) + +/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec + * - unless otherwise stated + */ + +/* starts up a counter + * - the Integrator/CP timer can be set up to issue an interrupt */ +int interrupt_init (void) +{ + /* Load timer with initial value */ + *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL; + /* Set timer to be + * enabled 1 + * periodic 1 + * no interrupts 0 + * X 0 + * divider 1 00 == less rounding error + * 32 bit 1 + * wrapping 0 + */ + *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x000000C2; + /* init the timestamp */ + total_count = 0ULL; + reset_timer_masked(); + + div_timer = (unsigned long long)(CFG_HZ_CLOCK / CFG_HZ); + div_timer /= div_clock; + + return (0); +} + +/* + * timer without interrupts + */ +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base_ticks) +{ + return get_timer_masked () - base_ticks; +} + +void set_timer (ulong ticks) +{ + timestamp = ticks; + total_count = (unsigned long long)ticks * div_timer; +} + +/* delay usec useconds */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + /* Convert to U-Boot ticks */ + tmo = usec * CFG_HZ; + tmo /= (1000000L); + + tmp = get_timer_masked(); /* get current timestamp */ + tmo += tmp; /* form target timestamp */ + + while (get_timer_masked () < tmo) {/* loop till event */ + /*NOP*/; + } +} + +void reset_timer_masked (void) +{ + /* capure current decrementer value */ + lastdec = (unsigned long long)READ_TIMER; + /* start "advancing" time stamp from 0 */ + timestamp = 0L; +} + +/* converts the timer reading to U-Boot ticks */ +/* the timestamp is the number of ticks since reset */ +ulong get_timer_masked (void) +{ + /* get current count */ + unsigned long long now = (unsigned long long)READ_TIMER; + + if(now > lastdec) { + /* Must have wrapped */ + total_count += lastdec + TIMER_LOAD_VAL + 1 - now; + } else { + total_count += lastdec - now; + } + lastdec = now; + timestamp = (ulong)(total_count/div_timer); + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return (unsigned long long)get_timer(0); +} + +/* + * Return the timebase clock frequency + * i.e. how often the timer decrements + */ +ulong get_tbclk (void) +{ + return (ulong)(((unsigned long long)CFG_HZ_CLOCK)/div_clock); +} diff --git a/board/integratorcp/lowlevel_init.S b/board/integratorcp/lowlevel_init.S new file mode 100644 index 0000000..18f7d2e --- /dev/null +++ b/board/integratorcp/lowlevel_init.S @@ -0,0 +1,214 @@ +/* + * Board specific setup info + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Reset using CM control register */ +.global reset_cpu +reset_cpu: + mov r0, #CM_BASE + ldr r1,[r0,#OS_CTRL] + orr r1,r1,#CMMASK_RESET + str r1,[r0,#OS_CTRL] + +reset_failed: + b reset_failed + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + /* If U-Boot has been run after the ARM boot monitor + * then all the necessary actions have been done + * otherwise we are running from user flash mapped to 0x00000000 + * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED -- + * Changes to the (possibly soft) reset defaults of the processor + * itself should be performed in cpu/arm<>/start.S + * This function affects only the core module or board settings + */ + +#ifdef CONFIG_CM_INIT + /* CM has an initialization register + * - bits in it are wired into test-chip pins to force + * reset defaults + * - may need to change its contents for U-Boot + */ + + /* set the desired CM specific value */ + mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */ + +#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) + orr r2,r2,#CMMASK_INIT_102 +#else + +#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ + !defined (CONFIG_CM940T) + /* CMxx6 code */ + +#ifdef CONFIG_CM_MULTIPLE_SSRAM + /* set simple mapping */ + and r2,r2,#CMMASK_MAP_SIMPLE +#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ + +#ifdef CONFIG_CM_TCRAM + /* disable TCRAM */ + and r2,r2,#CMMASK_TCRAM_DISABLE +#endif /* #ifdef CONFIG_CM_TCRAM */ + +#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ + defined (CONFIG_CM1136JF_S) + + and r2,r2,#CMMASK_LE + +#endif /* cpu with little endian initialization */ + + orr r2,r2,#CMMASK_CMxx6_COMMON + +#endif /* CMxx6 code */ + +#endif /* ARM102xxE value */ + + /* read CM_INIT */ + mov r0, #CM_BASE + ldr r1, [r0, #OS_INIT] + /* check against desired bit setting */ + and r3,r1,r2 + cmp r3,r2 + beq init_reg_OK + + /* lock for change */ + mov r3, #CMVAL_LOCK1 + and r3, r3, #CMVAL_LOCK2 + str r3, [r0, #OS_LOCK] + /* set desired value */ + orr r1,r1,r2 + /* write & relock CM_INIT */ + str r1, [r0, #OS_INIT] + mov r1, #CMVAL_UNLOCK + str r1, [r0, #OS_LOCK] + + /* soft reset so new values used */ + b reset_cpu + +init_reg_OK: + +#endif /* CONFIG_CM_INIT */ + + mov pc, lr + +#ifdef CONFIG_CM_SPD_DETECT + /* Fast memory is available for the DRAM data + * - ensure it has been transferred, then summarize the data + * into a CM register + */ +.globl dram_query +dram_query: + stmfd r13!,{r4-r6,lr} + /* set up SDRAM info */ + /* - based on example code from the CM User Guide */ + mov r0, #CM_BASE + +readspdbit: + ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ + and r1, r1, #0x20 /* mask SPD bit (5) */ + cmp r1, #0x20 /* test if set */ + bne readspdbit + +setupsdram: + add r0, r0, #OS_SPD /* address the copy of the SDP data */ + ldrb r1, [r0, #3] /* number of row address lines */ + ldrb r2, [r0, #4] /* number of column address lines */ + ldrb r3, [r0, #5] /* number of banks */ + ldrb r4, [r0, #31] /* module bank density */ + mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ + mov r5, r5, ASL#2 /* size in MB */ + mov r0, #CM_BASE /* reload for later code */ + cmp r5, #0x10 /* is it 16MB? */ + bne not16 + mov r6, #0x2 /* store size and CAS latency of 2 */ + b writesize + +not16: + cmp r5, #0x20 /* is it 32MB? */ + bne not32 + mov r6, #0x6 + b writesize + +not32: + cmp r5, #0x40 /* is it 64MB? */ + bne not64 + mov r6, #0xa + b writesize + +not64: + cmp r5, #0x80 /* is it 128MB? */ + bne not128 + mov r6, #0xe + b writesize + +not128: + /* if it is none of these sizes then it is either 256MB, or + * there is no SDRAM fitted so default to 256MB + */ + mov r6, #0x12 + +writesize: + mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */ + orr r2, r1, r2, ASL#12 /* OR in column address lines */ + orr r3, r2, r3, ASL#16 /* OR in number of banks */ + orr r6, r6, r3 /* OR in size and CAS latency */ + str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */ + +#endif /* #ifdef CONFIG_CM_SPD_DETECT */ + + ldmfd r13!,{r4-r6,pc} /* back to caller */ + +#ifdef CONFIG_CM_REMAP + /* CM remap bit is operational + * - use it to map writeable memory at 0x00000000, in place of flash + */ +.globl cm_remap +cm_remap: + stmfd r13!,{r4-r10,lr} + + mov r0, #CM_BASE + ldr r1, [r0, #OS_CTRL] + orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ + str r1, [r0, #OS_CTRL] + + /* Now 0x00000000 is writeable, replace the vectors */ + ldr r0, =_start /* r0 <- start of vectors */ + ldr r2, =_armboot_start /* r2 <- past vectors */ + sub r1,r1,r1 /* destination 0x00000000 */ + +copy_vec: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + ble copy_vec + + ldmfd r13!,{r4-r10,pc} /* back to caller */ + +#endif /* #ifdef CONFIG_CM_REMAP */ diff --git a/board/integratorcp/memsetup.S b/board/integratorcp/memsetup.S new file mode 100644 index 0000000..dfdc784 --- /dev/null +++ b/board/integratorcp/memsetup.S @@ -0,0 +1,29 @@ +/* + * Memory setup for integratorAP + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Memory setup + * - the reset defaults are assumed sufficient + */ + +.globl memsetup +memsetup: + mov pc,lr diff --git a/board/integratorcp/split_by_variant.sh b/board/integratorcp/split_by_variant.sh new file mode 100755 index 0000000..3a35433 --- /dev/null +++ b/board/integratorcp/split_by_variant.sh @@ -0,0 +1,111 @@ +#!/bin/sh +# --------------------------------------------------------- +# Set the platform defines +# --------------------------------------------------------- +echo -n "/* Integrator configuration implied " > tmp.fil +echo " by Makefile target */" >> tmp.fil +echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil +echo " /* Integrator board */" >> tmp.fil +echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil +echo " 1 /* Integrator/CP */" >> tmp.fil + +cpu="arm_intcm" +variant="unknown core module" + +if [ "$1" == "" ] +then + echo "$0:: No parameters - using arm_intcm" +else + case "$1" in + ap966) + cpu="arm_intcm" + variant="unported core module CM966E-S" + ;; + + ap922_config) + cpu="arm_intcm" + variant="unported core module CM922T" + ;; + + integratorcp_config | \ + cp_config) + cpu="arm_intcm" + variant="unspecified core module" + ;; + + cp922_XA10_config) + cpu="arm_intcm" + variant="unported core module CM922T_XA10" + echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil + echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil + ;; + + cp920t_config) + cpu="arm920t" + variant="Core module CM920T" + echo -n "#define CONFIG_CM920T" >> tmp.fil + echo " 1 /* CPU core is ARM920T */" >> tmp.fil + ;; + + cp926ejs_config) + cpu="arm926ejs" + variant="Core module CM926EJ-S" + echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil + echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil + ;; + + + cp946es_config) + cpu="arm946es" + variant="Core module CM946E-S" + echo -n "#define CONFIG_CM946E_S" >> tmp.fil + echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil + ;; + + cp1136_config) + cpu="arm1136" + variant="Core module CM1136EJF-S" + echo -n "#define CONFIG_CM1136EJF_S" >> tmp.fil + echo " 1 /* CPU core is ARM1136JF-S */ " >> tmp.fil + ;; + + *) + echo "$0:: Unknown core module" + variant="unknown core module" + cpu="arm_intcm" + ;; + + esac + +fi + +if [ "$cpu" == "arm_intcm" ] +then + echo "/* Core module undefined/not ported */" >> tmp.fil + echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil + echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "multiple SSRAM mapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil + echo -n " /* CM may not support SPD " >> tmp.fil + echo "query */" >> tmp.fil + echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil + echo -n " /* CM may not support " >> tmp.fil + echo "remapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_INIT " >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "initialization reg */" >> tmp.fil + echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil + echo " /* CM may not have TCRAM */" >> tmp.fil +fi +mv tmp.fil ./include/config.h +# --------------------------------------------------------- +# Ensure correct core object loaded first in U-Boot image +# --------------------------------------------------------- +sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorcp/u-boot.lds.template > board/integratorcp/u-boot.lds +# --------------------------------------------------------- +# Complete the configuration +# --------------------------------------------------------- +./mkconfig -a integratorcp arm $cpu integratorcp; +echo "Variant:: $variant with core $cpu" + diff --git a/board/integratorcp/u-boot.lds.template b/board/integratorcp/u-boot.lds.template new file mode 100644 index 0000000..0ec8087 --- /dev/null +++ b/board/integratorcp/u-boot.lds.template @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +# Template used during configuration to emsure the core module processor code, +# from CPU_FILE, is placed at the start of the image */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + CPU_FILE (.text) + *(.text) + } + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/ip860/Makefile b/board/ip860/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/ip860/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/ip860/config.mk b/board/ip860/config.mk new file mode 100644 index 0000000..ea3b873 --- /dev/null +++ b/board/ip860/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MicroSys IP860 VMEBus Systems +# + +TEXT_BASE = 0x10000000 diff --git a/board/ip860/flash.c b/board/ip860/flash.c new file mode 100644 index 0000000..2cf23b3 --- /dev/null +++ b/board/ip860/flash.c @@ -0,0 +1,456 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; + unsigned long size; + int i; + + /* Init: enable write, + * or we cannot even write flash commands + */ + bcsr->bd_ctrl |= BD_CTRL_FLWE; + + for (i=0; imemc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | + (memctl->memc_br1 & ~(BR_BA_MSK)); + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* all possible flash types + * (28F016SV, 28F160S3, 28F320S3) + * have the same erase block size: 64 kB per chip, + * of 128 kB per bank + */ + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x00020000; + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); + break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write "Intelligent Identifier" command: read Manufacturer ID */ + *addr = 0x90909090; + + value = addr[0]; + switch (value) { + case (MT_MANUFACT & 0x00FF00FF): /* MT or => Intel */ + case (INTEL_ALT_MANU & 0x00FF00FF): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case (INTEL_ID_28F016S): + info->flash_id += FLASH_28F016SV; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F160S3): + info->flash_id += FLASH_28F160S3; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F320S3): + info->flash_id += FLASH_28F320S3; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 2x4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000); + /* don't know how to check sector protection */ + info->protect[i] = 0; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_long *)info->start[0]; + + *addr = 0xFFFFFF; /* reset bank to read array mode */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Single Block Erase Command */ + *addr = 0x20202020; + /* Confirm */ + *addr = 0xD0D0D0D0; + /* Resume Command, as per errata update */ + *addr = 0xD0D0D0D0; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while ((*addr & 0x00800080) != 0x00800080) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + /* reset to read mode */ + *addr = 0xFFFFFFFF; + } + } + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong start, csr; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = 0x10101010; + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + flag = 0; + while (((csr = *addr) & 0x00800080) != 0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x00400040) { +printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + + /* Clear Status Registers Command */ + *addr = 0x50505050; + /* Reset to read array mode */ + *addr = 0xFFFFFFFF; + + return (flag); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c new file mode 100644 index 0000000..9dd809b --- /dev/null +++ b/board/ip860/ip860.c @@ -0,0 +1,356 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); +unsigned long ip860_get_dram_size(void); +unsigned long ip860_get_clk_freq (void); +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, + 0x1ff77c47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1ff77c34, 0xefeabc34, 0x1fb57c35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, + 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7ffffc07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + + +/* ------------------------------------------------------------------------- */ +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + +/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */ + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + * + * Test ID string (IP860...) + */ + +int checkboard (void) +{ + unsigned char *s, *e; + unsigned char buf[64]; + int i; + + puts ("Board: "); + + i = getenv_r ("serial#", (char *)buf, sizeof (buf)); + s = (i > 0) ? buf : NULL; + + if (!s || strncmp ((char *)s, "IP860", 5)) { + puts ("### No HW ID - assuming IP860"); + } else { + for (e = s; *e; ++e) { + if (*e == ' ') + break; + } + + for (; s < e; ++s) { + putc (*s); + } + } + + putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + ulong refresh_val; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh + */ + if (ip860_get_clk_freq() == 50000000) + { + memctl->memc_mptpr = 0x0400; + refresh_val = 0xC3000000; + } + else + { + memctl->memc_mptpr = 0x0200; + refresh_val = 0x9C000000; + } + + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 to the SDRAM address + */ + memctl->memc_or2 = CFG_OR2; + memctl->memc_br2 = CFG_BR2; + + /* IP860 boards have only one bank SDRAM */ + + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mamr = 0x00804114 | refresh_val; + memctl->memc_mcr = 0x80004105; /* run precharge pattern from loc 5 */ + udelay(1); + memctl->memc_mamr = 0x00804118 | refresh_val; + memctl->memc_mcr = 0x80004130; /* run refresh pattern 8 times */ + + + udelay (1000); + + /* + * Check SDRAM Memory Size + */ + if (ip860_get_dram_size() == 16) + size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE); + else + size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE); + + udelay (1000); + + memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; + memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + udelay (10000); + + /* + * Also, map other memory to correct position + */ + +#if (defined(CFG_OR1) && defined(CFG_BR1_PRELIM)) + memctl->memc_or1 = CFG_OR1; + memctl->memc_br1 = CFG_BR1; +#endif + +#if defined(CFG_OR3) && defined(CFG_BR3) + memctl->memc_or3 = CFG_OR3; + memctl->memc_br3 = CFG_BR3; +#endif + +#if defined(CFG_OR4) && defined(CFG_BR4) + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; +#endif + +#if defined(CFG_OR5) && defined(CFG_BR5) + memctl->memc_or5 = CFG_OR5; + memctl->memc_br5 = CFG_BR5; +#endif + +#if defined(CFG_OR6) && defined(CFG_BR6) + memctl->memc_or6 = CFG_OR6; + memctl->memc_br6 = CFG_BR6; +#endif + +#if defined(CFG_OR7) && defined(CFG_BR7) + memctl->memc_or7 = CFG_OR7; + memctl->memc_br7 = CFG_BR7; +#endif + + return (size); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +void reset_phy (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + ulong mask = PB_ENET_RESET | PB_ENET_JABD; + ulong reg; + + /* Make sure PHY is not in low-power mode */ + immr->im_cpm.cp_pbpar &= ~(mask); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(mask); /* active output */ + + /* Set JABD low (no JABber Disable), + * and RESET high (Reset PHY) + */ + reg = immr->im_cpm.cp_pbdat; + reg = (reg & ~PB_ENET_JABD) | PB_ENET_RESET; + immr->im_cpm.cp_pbdat = reg; + + /* now drive outputs */ + immr->im_cpm.cp_pbdir |= mask; /* output */ + udelay (1000); + /* + * Release RESET signal + */ + immr->im_cpm.cp_pbdat &= ~(PB_ENET_RESET); + udelay (1000); +} + +/* ------------------------------------------------------------------------- */ + +unsigned long ip860_get_clk_freq(void) +{ + volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; + ulong temp; + uchar sysclk; + + if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */ + sysclk = (bcsr->bd_rev & 0x18) >> 3; + else + sysclk = 0x00; + + switch (sysclk) + { + case 0x00: + temp = 50000000; + break; + + case 0x01: + temp = 80000000; + break; + + default: + temp = 50000000; + break; + } + + return (temp); + +} + + +/* ------------------------------------------------------------------------- */ + +unsigned long ip860_get_dram_size(void) +{ + volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; + ulong temp; + uchar dram_size; + + if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */ + dram_size = (bcsr->bd_rev & 0xE0) >> 5; + else + dram_size = 0x00; /* default is 16 MB */ + + switch (dram_size) + { + case 0x00: + temp = 16; + break; + + case 0x01: + temp = 32; + break; + + default: + temp = 16; + break; + } + + return (temp); + +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds new file mode 100644 index 0000000..8cb2504 --- /dev/null +++ b/board/ip860/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + cpu/mpc8xx/interrupts.o (.text) + lib_ppc/time.o (.text) + lib_ppc/ticks.o (.text) +/** + . = env_offset; + common/environment.o(.text) +**/ + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug new file mode 100644 index 0000000..43d2b3b --- /dev/null +++ b/board/ip860/u-boot.lds.debug @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + lib_ppc/ppcstring.o (.text) + cpu/mpc8xx/interrupts.o (.text) + lib_ppc/time.o (.text) + lib_ppc/ticks.o (.text) +/** + . = env_offset; + common/environment.o(.text) +**/ + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/iphase4539/Makefile b/board/iphase4539/Makefile new file mode 100644 index 0000000..19da5d0 --- /dev/null +++ b/board/iphase4539/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2002 Wolfgang Grandegger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/iphase4539/config.mk b/board/iphase4539/config.mk new file mode 100644 index 0000000..632c1d2 --- /dev/null +++ b/board/iphase4539/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2002 Wolfgang Grandegger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# iphase4539 board +# + +TEXT_BASE = 0xffb00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/iphase4539/flash.c b/board/iphase4539/flash.c new file mode 100644 index 0000000..4eca467 --- /dev/null +++ b/board/iphase4539/flash.c @@ -0,0 +1,490 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Adapted for Interphase 4539 by Wolfgang Grandegger . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +extern int hwc_flash_size(void); +static ulong flash_get_size (u32 addr, flash_info_t *info); +static int flash_get_offsets (u32 base, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_reset (u32 addr); + +#define out8(a,v) *(volatile unsigned char*)(a) = v +#define in8(a) *(volatile unsigned char*)(a) +#define in32(a) *(volatile unsigned long*)(a) +#define iobarrier_rw() eieio() + +unsigned long flash_init (void) +{ + unsigned int i; + unsigned long flash_size = 0; + unsigned long bank_size; + unsigned int bank = 0; + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = 0; + flash_info[i].size = 0; + } + + /* Initialise the BOOT Flash */ + if (bank == CFG_MAX_FLASH_BANKS) { + puts ("Warning: not all Flashes are initialised !"); + return flash_size; + } + + bank_size = flash_get_size (CFG_FLASH_BASE, flash_info + bank); + if (bank_size) { +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \ + CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_MAX_FLASH_SIZE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + flash_info + bank); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + flash_info + bank); +#endif + + /* HWC protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + 0x10000 - 1, + flash_info + bank); + + flash_size += bank_size; + bank++; + } else { + puts ("Warning: the BOOT Flash is not initialised !"); + } + + return flash_size; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (u32 addr, flash_info_t *info) +{ + volatile uchar value; +#if 0 + int i; +#endif + + /* Write auto select command: read Manufacturer ID */ + out8(addr + 0x0555, 0xAA); + iobarrier_rw(); + udelay(10); + out8(addr + 0x02AA, 0x55); + iobarrier_rw(); + udelay(10); + out8(addr + 0x0555, 0x90); + iobarrier_rw(); + udelay(10); + + value = in8(addr); + iobarrier_rw(); + udelay(10); + switch (value | (value << 16)) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + flash_reset (addr); + return 0; + } + + value = in8(addr + 1); /* device ID */ + iobarrier_rw(); + + switch (value) { + case AMD_ID_LV033C: + info->flash_id += FLASH_AM033C; + info->size = hwc_flash_size(); + if (info->size > CFG_MAX_FLASH_SIZE) { + printf("U-Boot supports only %d MB\n", + CFG_MAX_FLASH_SIZE); + info->size = CFG_MAX_FLASH_SIZE; + } + info->sector_count = info->size / 0x10000; + break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + flash_reset (addr); + return (0); /* => no or unknown flash */ + + } + + if (!flash_get_offsets (addr, info)) { + flash_reset (addr); + return 0; + } + +#if 0 + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + value = in8(info->start[i] + 2); + iobarrier_rw(); + info->protect[i] = (value & 1) != 0; + } +#endif + + /* + * Reset bank to read mode + */ + flash_reset (addr); + + return (info->size); +} + +static int flash_get_offsets (u32 base, flash_info_t *info) +{ + unsigned int i, size; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM033C: + /* set sector offsets for uniform sector type */ + size = info->size / info->sector_count; + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + i * size; + } + break; + default: + return 0; + } + + return 1; +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile u32 addr = info->start[0]; + int flag, prot, sect, l_sect; + ulong start, now, last; + + if (s_first < 0 || s_first > s_last) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN || + info->flash_id > FLASH_AMD_COMP) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + out8(addr + 0x555, 0x80); + iobarrier_rw(); + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = info->start[sect]; + out8(addr, 0x30); + iobarrier_rw(); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = info->start[l_sect]; + while ((in8(addr) & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + iobarrier_rw(); + } + +DONE: + /* reset to read mode */ + flash_reset (info->start[0]); + + printf (" done\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/* + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile u32 addr = info->start[0]; + ulong start; + int flag, i; + + /* Check if Flash is (sufficiently) erased */ + if ((in32(dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* first, perform an unlock bypass command to speed up flash writes */ + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + out8(addr + 0x555, 0x20); + iobarrier_rw(); + + /* write each byte out */ + for (i = 0; i < 4; i++) { + char *data_ch = (char *)&data; + out8(addr, 0xA0); + iobarrier_rw(); + out8(dest+i, data_ch[i]); + iobarrier_rw(); + udelay(10); /* XXX */ + } + + /* we're done, now do an unlock bypass reset */ + out8(addr, 0x90); + iobarrier_rw(); + out8(addr, 0x00); + iobarrier_rw(); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((in32(dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + iobarrier_rw(); + } + + flash_reset (addr); + + return (0); +} + +/* + * Reset bank to read mode + */ +static void flash_reset (u32 addr) +{ + out8(addr, 0xF0); /* reset bank */ + iobarrier_rw(); +} + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM033C: printf ("AM29LV033C (32 Mbit, uniform sectors)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size % 0x100000 == 0) { + printf (" Size: %ld MB in %d Sectors\n", + info->size / 0x100000, info->sector_count); + } + else if (info->size % 0x400 == 0) { + printf (" Size: %ld KB in %d Sectors\n", + info->size / 0x400, info->sector_count); + } + else { + printf (" Size: %ld B in %d Sectors\n", + info->size, info->sector_count); + } + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} diff --git a/board/iphase4539/iphase4539.c b/board/iphase4539/iphase4539.c new file mode 100644 index 0000000..0ca9cf5 --- /dev/null +++ b/board/iphase4539/iphase4539.c @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2002 Wolfgang Grandegger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +int hwc_flash_size (void); +int hwc_local_sdram_size (void); +int hwc_main_sdram_size (void); +int hwc_serial_number (void); +int hwc_mac_address (char *str); +int hwc_manufact_date (char *str); +int seeprom_read (int addr, uchar * data, int size); + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + * + * The port definitions are taken from the old firmware (see + * also SYS/H/4539.H): + * + * ppar psor pdir podr pdat + * PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0 + * PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290 + * PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d + * PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9 + */ +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + {0, 1, 0, 0, 0, 0}, /* PA31 FCC1_TXENB SLAVE */ + {0, 1, 0, 1, 0, 0}, /* PA30 FCC1_TXCLAV SLAVE */ + {0, 1, 0, 1, 0, 0}, /* PA29 FCC1_TXSOC */ + {0, 1, 0, 0, 0, 0}, /* PA28 FCC1_RXENB SLAVE */ + {0, 1, 0, 0, 0, 0}, /* PA27 FCC1_RXSOC */ + {0, 1, 0, 1, 0, 0}, /* PA26 FCC1_RXCLAV SLAVE */ + {0, 1, 0, 1, 0, 1}, /* PA25 FCC1_TXD0 */ + {0, 1, 0, 1, 0, 1}, /* PA24 FCC1_TXD1 */ + {0, 1, 0, 1, 0, 1}, /* PA23 FCC1_TXD2 */ + {0, 1, 0, 1, 0, 1}, /* PA22 FCC1_TXD3 */ + {0, 1, 0, 1, 0, 1}, /* PA21 FCC1_TXD4 */ + {0, 1, 0, 1, 0, 1}, /* PA20 FCC1_TXD5 */ + {0, 1, 0, 1, 0, 1}, /* PA19 FCC1_TXD6 */ + {0, 1, 0, 1, 0, 1}, /* PA18 FCC1_TXD7 */ + {0, 1, 0, 0, 0, 0}, /* PA17 FCC1_RXD7 */ + {0, 1, 0, 0, 0, 0}, /* PA16 FCC1_RXD6 */ + {0, 1, 0, 0, 0, 0}, /* PA15 FCC1_RXD5 */ + {0, 1, 0, 0, 0, 0}, /* PA14 FCC1_RXD4 */ + {0, 1, 0, 0, 0, 0}, /* PA13 FCC1_RXD3 */ + {0, 1, 0, 0, 0, 0}, /* PA12 FCC1_RXD2 */ + {0, 1, 0, 0, 0, 0}, /* PA11 FCC1_RXD1 */ + {0, 1, 0, 0, 0, 0}, /* PA10 FCC1_RXD0 */ + {0, 1, 1, 1, 0, 1}, /* PA9 TDMA1_L1TXD */ + {0, 1, 1, 0, 0, 0}, /* PA8 TDMA1_L1RXD */ + {0, 0, 0, 0, 0, 0}, /* PA7 CONFIG0 */ + {0, 1, 1, 0, 0, 1}, /* PA6 TDMA1_L1RSYNC */ + {0, 0, 0, 1, 0, 0}, /* PA5 FCC2:RxAddr[2] */ + {0, 0, 0, 1, 0, 0}, /* PA4 FCC2:RxAddr[1] */ + {0, 0, 0, 1, 0, 0}, /* PA3 FCC2:RxAddr[0] */ + {0, 0, 0, 1, 0, 0}, /* PA2 FCC2:TxAddr[0] */ + {0, 0, 0, 1, 0, 0}, /* PA1 FCC2:TxAddr[1] */ + {0, 0, 0, 1, 0, 0} /* PA0 FCC2:TxAddr[2] */ + }, + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + {0, 0, 0, 1, 0, 0}, /* PB31 FCC2_RXSOC */ + {0, 0, 0, 1, 0, 0}, /* PB30 FCC2_TXSOC */ + {0, 0, 0, 1, 0, 0}, /* PB29 FCC2_RXCLAV */ + {0, 0, 0, 0, 0, 0}, /* PB28 CONFIG2 */ + {0, 1, 1, 0, 0, 1}, /* PB27 FCC2_TXD0 */ + {0, 1, 1, 0, 0, 0}, /* PB26 FCC2_TXD1 */ + {0, 0, 0, 1, 0, 0}, /* PB25 FCC2_TXD4 */ + {0, 1, 1, 0, 0, 1}, /* PB24 FCC2_TXD5 */ + {0, 0, 0, 1, 0, 0}, /* PB23 FCC2_TXD6 */ + {0, 1, 0, 1, 0, 1}, /* PB22 FCC2_TXD7 */ + {0, 1, 0, 0, 0, 0}, /* PB21 FCC2_RXD7 */ + {0, 1, 0, 0, 0, 0}, /* PB20 FCC2_RXD6 */ + {0, 1, 0, 0, 0, 0}, /* PB19 FCC2_RXD5 */ + {0, 0, 0, 1, 0, 0}, /* PB18 FCC2_RXD4 */ + {1, 1, 0, 0, 0, 0}, /* PB17 FCC3_RX_DV */ + {1, 1, 0, 0, 0, 0}, /* PB16 FCC3_RX_ER */ + {1, 1, 0, 1, 0, 0}, /* PB15 FCC3_TX_ER */ + {1, 1, 0, 1, 0, 0}, /* PB14 FCC3_TX_EN */ + {1, 1, 0, 0, 0, 0}, /* PB13 FCC3_COL */ + {1, 1, 0, 0, 0, 0}, /* PB12 FCC3_CRS */ + {1, 1, 0, 0, 0, 0}, /* PB11 FCC3_RXD3 */ + {1, 1, 0, 0, 0, 0}, /* PB10 FCC3_RXD2 */ + {1, 1, 0, 0, 0, 0}, /* PB9 FCC3_RXD1 */ + {1, 1, 0, 0, 0, 0}, /* PB8 FCC3_RXD0 */ + {1, 1, 0, 1, 0, 1}, /* PB7 FCC3_TXD0 */ + {1, 1, 0, 1, 0, 1}, /* PB6 FCC3_TXD1 */ + {1, 1, 0, 1, 0, 1}, /* PB5 FCC3_TXD2 */ + {1, 1, 0, 1, 0, 1}, /* PB4 FCC3_TXD3 */ + {0, 0, 0, 0, 0, 0}, /* PB3 */ + {0, 0, 0, 0, 0, 0}, /* PB2 */ + {0, 0, 0, 0, 0, 0}, /* PB1 */ + {0, 0, 0, 0, 0, 0}, /* PB0 */ + }, + /* Port C configuration */ + { /* conf ppar psor pdir podr pdat */ + {0, 1, 0, 0, 0, 1}, /* PC31 CLK1 */ + {0, 0, 0, 1, 0, 0}, /* PC30 U1MASTER_N */ + {0, 1, 0, 0, 0, 1}, /* PC29 CLK3 */ + {0, 0, 0, 1, 0, 1}, /* PC28 -MT90220_RST */ + {0, 1, 0, 0, 0, 1}, /* PC27 CLK5 */ + {0, 0, 0, 1, 0, 1}, /* PC26 -QUADFALC_RST */ + {0, 1, 1, 1, 0, 1}, /* PC25 BRG4 */ + {1, 0, 0, 1, 0, 0}, /* PC24 MDIO */ + {1, 0, 0, 1, 0, 0}, /* PC23 MDC */ + {0, 1, 0, 0, 0, 1}, /* PC22 CLK10 */ + {0, 0, 0, 1, 0, 0}, /* PC21 */ + {0, 1, 0, 0, 0, 1}, /* PC20 CLK12 */ + {0, 1, 0, 0, 0, 1}, /* PC19 CLK13 */ + {1, 1, 0, 0, 0, 1}, /* PC18 CLK14 */ + {0, 1, 0, 0, 0, 0}, /* PC17 CLK15 */ + {1, 1, 0, 0, 0, 1}, /* PC16 CLK16 */ + {0, 1, 1, 0, 0, 0}, /* PC15 FCC1_TXADDR0 SLAVE */ + {0, 1, 1, 0, 0, 0}, /* PC14 FCC1_RXADDR0 SLAVE */ + {0, 1, 1, 0, 0, 0}, /* PC13 FCC1_TXADDR1 SLAVE */ + {0, 1, 1, 0, 0, 0}, /* PC12 FCC1_RXADDR1 SLAVE */ + {0, 0, 0, 1, 0, 0}, /* PC11 FCC2_RXD2 */ + {0, 0, 0, 1, 0, 0}, /* PC10 FCC2_RXD3 */ + {0, 0, 0, 1, 0, 1}, /* PC9 LTMODE */ + {0, 0, 0, 1, 0, 1}, /* PC8 SELSYNC */ + {0, 1, 1, 0, 0, 0}, /* PC7 FCC1_TXADDR2 SLAVE */ + {0, 1, 1, 0, 0, 0}, /* PC6 FCC1_RXADDR2 SLAVE */ + {0, 0, 0, 1, 0, 0}, /* PC5 FCC2_TXCLAV MASTER */ + {0, 0, 0, 1, 0, 0}, /* PC4 FCC2_RXENB MASTER */ + {0, 0, 0, 1, 0, 0}, /* PC3 FCC2_TXD2 */ + {0, 0, 0, 1, 0, 0}, /* PC2 FCC2_TXD3 */ + {0, 0, 0, 0, 0, 1}, /* PC1 PTMC -PTEENB */ + {0, 0, 0, 1, 0, 1}, /* PC0 COMCLK_N */ + }, + /* Port D configuration */ + { /* conf ppar psor pdir podr pdat */ + {0, 0, 0, 1, 0, 1}, /* PD31 -CAM_RST */ + {0, 0, 0, 1, 0, 0}, /* PD30 FCC2_TXENB */ + {0, 1, 1, 0, 0, 0}, /* PD29 FCC1_RXADDR3 SLAVE */ + {0, 1, 1, 0, 0, 1}, /* PD28 TDMC1_L1TXD */ + {0, 1, 1, 0, 0, 0}, /* PD27 TDMC1_L1RXD */ + {0, 1, 1, 0, 0, 1}, /* PD26 TDMC1_L1RSYNC */ + {0, 0, 0, 1, 0, 1}, /* PD25 LED0 -OFF */ + {0, 0, 0, 1, 0, 1}, /* PD24 LED5 -OFF */ + {1, 0, 0, 1, 0, 1}, /* PD23 -LXT971_RST */ + {0, 1, 1, 0, 0, 1}, /* PD22 TDMA2_L1TXD */ + {0, 1, 1, 0, 0, 0}, /* PD21 TDMA2_L1RXD */ + {0, 1, 1, 0, 0, 1}, /* PD20 TDMA2_L1RSYNC */ + {0, 0, 0, 1, 0, 0}, /* PD19 FCC2_TXADDR3 */ + {0, 0, 0, 1, 0, 0}, /* PD18 FCC2_RXADDR3 */ + {0, 1, 0, 1, 0, 0}, /* PD17 BRG2 */ + {0, 0, 0, 1, 0, 0}, /* PD16 */ + {0, 0, 0, 1, 0, 0}, /* PD15 PT2TO1 */ + {0, 0, 0, 1, 0, 1}, /* PD14 PT4TO3 */ + {0, 0, 0, 1, 0, 1}, /* PD13 -SWMODE */ + {0, 0, 0, 1, 0, 1}, /* PD12 -PTMODE */ + {0, 0, 0, 1, 0, 0}, /* PD11 FCC2_RXD0 */ + {0, 0, 0, 1, 0, 0}, /* PD10 FCC2_RXD1 */ + {1, 1, 0, 1, 0, 1}, /* PD9 SMC1_SMTXD */ + {1, 1, 0, 0, 0, 1}, /* PD8 SMC1_SMRXD */ + {0, 1, 1, 0, 0, 0}, /* PD7 FCC1_TXADDR3 SLAVE */ + {0, 0, 0, 1, 0, 0}, /* PD6 IMAMODE */ + {0, 0, 0, 0, 0, 0}, /* PD5 CONFIG2 */ + {0, 1, 0, 1, 0, 0}, /* PD4 BRG8 */ + {0, 0, 0, 0, 0, 0}, /* PD3 */ + {0, 0, 0, 0, 0, 0}, /* PD2 */ + {0, 0, 0, 0, 0, 0}, /* PD1 */ + {0, 0, 0, 0, 0, 0}, /* PD0 */ + } +}; + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar *base; + ulong maxsize; + int i; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#ifndef CFG_RAMBOOT + immap->im_siu_conf.sc_ppc_acr = 0x00000026; + immap->im_siu_conf.sc_ppc_alrh = 0x01276345; + immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; + immap->im_siu_conf.sc_lcl_acr = 0x00000000; + immap->im_siu_conf.sc_lcl_alrh = 0x01234567; + immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; + immap->im_siu_conf.sc_tescr1 = 0x00004000; + immap->im_siu_conf.sc_ltescr1 = 0x00004000; + + /* Init Main SDRAM */ +#define OP_VALUE 0x404A241A +#define OP_VALUE_M (OP_VALUE & 0x87FFFFFF); + base = (uchar *) CFG_SDRAM_BASE; + memctl->memc_psdmr = 0x28000000 | OP_VALUE_M; + *base = 0xFF; + memctl->memc_psdmr = 0x08000000 | OP_VALUE_M; + for (i = 0; i < 8; i++) + *base = 0xFF; + memctl->memc_psdmr = 0x18000000 | OP_VALUE_M; + *(base + 0x110) = 0xFF; + memctl->memc_psdmr = OP_VALUE; + memctl->memc_lsdmr = 0x4086A522; + *base = 0xFF; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2; + + maxsize = get_ram_size((long *)base, maxsize); + + memctl->memc_or1 |= ~(maxsize - 1); + + if (maxsize != hwc_main_sdram_size ()) + printf ("Oops: memory test has not found all memory!\n"); +#endif + + icache_enable (); + /* return total ram size of SDRAM */ + return (maxsize); +} + +int checkboard (void) +{ + char string[32]; + + hwc_manufact_date (string); + + printf ("Board: Interphase 4539 (#%d %s)\n", + hwc_serial_number (), + string); + +#ifdef DEBUG + printf ("Manufacturing date: %s\n", string); + printf ("Serial number : %d\n", hwc_serial_number ()); + printf ("FLASH size : %d MB\n", hwc_flash_size () >> 20); + printf ("Main SDRAM size : %d MB\n", hwc_main_sdram_size () >> 20); + printf ("Local SDRAM size : %d MB\n", hwc_local_sdram_size () >> 20); + hwc_mac_address (string); + printf ("MAC address : %s\n", string); +#endif + + return 0; +} + +int misc_init_r (void) +{ + char *s, str[32]; + int num; + + if ((s = getenv ("serial#")) == NULL && + (num = hwc_serial_number ()) != -1) { + sprintf (str, "%06d", num); + setenv ("serial#", str); + } + if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) { + setenv ("ethaddr", str); + } + return (0); +} + +/*************************************************************** + * We take some basic Hardware Configuration Parameter from the + * Serial EEPROM conected to the PSpan bridge. We keep it as + * simple as possible. + */ +int hwc_flash_size (void) +{ + uchar byte; + + if (!seeprom_read (0x40, &byte, sizeof (byte))) { + switch ((byte >> 2) & 0x3) { + case 0x1: + return 0x0400000; + break; + case 0x2: + return 0x0800000; + break; + case 0x3: + return 0x1000000; + default: + return 0x0100000; + } + } + return -1; +} +int hwc_local_sdram_size (void) +{ + uchar byte; + + if (!seeprom_read (0x40, &byte, sizeof (byte))) { + switch ((byte & 0x03)) { + case 0x1: + return 0x0800000; + case 0x2: + return 0x1000000; + default: + return 0; /* not present */ + } + } + return -1; +} +int hwc_main_sdram_size (void) +{ + uchar byte; + + if (!seeprom_read (0x41, &byte, sizeof (byte))) { + return 0x1000000 << ((byte >> 5) & 0x7); + } + return -1; +} +int hwc_serial_number (void) +{ + int sn = -1; + + if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) { + sn = cpu_to_le32 (sn); + } + return sn; +} +int hwc_mac_address (char *str) +{ + char mac[6]; + + if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) { + sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } else { + strcpy (str, "ERROR"); + return -1; + } + return 0; +} +int hwc_manufact_date (char *str) +{ + uchar byte; + int value; + + if (seeprom_read (0x92, &byte, sizeof (byte))) + goto out; + value = byte; + if (seeprom_read (0x93, &byte, sizeof (byte))) + goto out; + value += byte << 8; + sprintf (str, "%02d/%02d/%04d", + value & 0x1F, (value >> 5) & 0xF, + 1980 + ((value >> 9) & 0x1FF)); + return 0; + + out: + strcpy (str, "ERROR"); + return -1; +} + +#define PSPAN_ADDR 0xF0020000 +#define EEPROM_REG 0x408 +#define EEPROM_READ_CMD 0xA000 +#define PSPAN_WRITE(a,v) \ + *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio() +#define PSPAN_READ(a) \ + *((volatile unsigned long *)(PSPAN_ADDR+(a))) + +int seeprom_read (int addr, uchar * data, int size) +{ + ulong val, cmd; + int i; + + for (i = 0; i < size; i++) { + + cmd = EEPROM_READ_CMD; + cmd |= ((addr + i) << 24) & 0xff000000; + + /* Wait for ACT to authorize write */ + while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) + eieio (); + + /* Write command */ + PSPAN_WRITE (EEPROM_REG, cmd); + + /* Wait for data to be valid */ + while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) + eieio (); + /* Do it twice, first read might be erratic */ + while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) + eieio (); + + /* Read error */ + if (val & 0x00000040) { + return -1; + } else { + data[i] = (val >> 16) & 0xff; + } + } + return 0; +} diff --git a/board/iphase4539/u-boot.lds b/board/iphase4539/u-boot.lds new file mode 100644 index 0000000..4ea01ea --- /dev/null +++ b/board/iphase4539/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ispan/Makefile b/board/ispan/Makefile new file mode 100644 index 0000000..9123a80 --- /dev/null +++ b/board/ispan/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2004 Arabella Software Ltd. +# Yuli Barcohen +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ispan/config.mk b/board/ispan/config.mk new file mode 100644 index 0000000..4600dbb --- /dev/null +++ b/board/ispan/config.mk @@ -0,0 +1,29 @@ +# +# Copyright (C) 2004 Arabella Software Ltd. +# Yuli Barcohen +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Interphase iSPAN Communications Controllers +# +#TEXT_BASE = 0xFF800000 +#TEXT_BASE = 0xFFBA0000 +TEXT_BASE = 0xFE7A0000 diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c new file mode 100644 index 0000000..d39b8cd --- /dev/null +++ b/board/ispan/ispan.c @@ -0,0 +1,464 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen + * + * Support for Interphase iSPAN Communications Controllers + * (453x and others). Tested on 4532. + * + * Derived from iSPAN 4539 port (iphase4539) by + * Wolfgang Grandegger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * I/O Ports configuration table + * + * If conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3) + +const iop_conf_t iop_conf_tab[4][32] = { + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ + /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ + /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ + /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ + /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ + /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ + /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ + /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ + /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ + /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ + /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ + /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ + /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ + /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ + /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ + /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ + /* PC18 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ + /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */ + /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */ + /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */ + /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { CFG_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */ + /* PD5 */ { CFG_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +#define PSPAN_ADDR 0xF0020000 +#define EEPROM_REG 0x408 +#define EEPROM_READ_CMD 0xA000 +#define PSPAN_WRITE(a,v) \ + *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio() +#define PSPAN_READ(a) \ + *((volatile unsigned long *)(PSPAN_ADDR+(a))) + +static int seeprom_read (int addr, uchar * data, int size) +{ + ulong val, cmd; + int i; + + for (i = 0; i < size; i++) { + + cmd = EEPROM_READ_CMD; + cmd |= ((addr + i) << 24) & 0xff000000; + + /* Wait for ACT to authorize write */ + while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) + eieio (); + + /* Write command */ + PSPAN_WRITE (EEPROM_REG, cmd); + + /* Wait for data to be valid */ + while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) + eieio (); + /* Do it twice, first read might be erratic */ + while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) + eieio (); + + /* Read error */ + if (val & 0x00000040) { + return -1; + } else { + data[i] = (val >> 16) & 0xff; + } + } + return 0; +} + +/*************************************************************** + * We take some basic Hardware Configuration Parameter from the + * Serial EEPROM conected to the PSpan bridge. We keep it as + * simple as possible. + */ +#ifdef DEBUG +static int hwc_flash_size (void) +{ + uchar byte; + + if (!seeprom_read (0x40, &byte, sizeof (byte))) { + switch ((byte >> 2) & 0x3) { + case 0x1: + return 0x0400000; + break; + case 0x2: + return 0x0800000; + break; + case 0x3: + return 0x1000000; + default: + return 0x0100000; + } + } + return -1; +} + +static int hwc_local_sdram_size (void) +{ + uchar byte; + + if (!seeprom_read (0x40, &byte, sizeof (byte))) { + switch ((byte & 0x03)) { + case 0x1: + return 0x0800000; + case 0x2: + return 0x1000000; + default: + return 0; /* not present */ + } + } + return -1; +} +#endif /* DEBUG */ + +static int hwc_main_sdram_size (void) +{ + uchar byte; + + if (!seeprom_read (0x41, &byte, sizeof (byte))) { + return 0x1000000 << ((byte >> 5) & 0x7); + } + return -1; +} + +static int hwc_serial_number (void) +{ + int sn = -1; + + if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) { + sn = cpu_to_le32 (sn); + } + return sn; +} + +static int hwc_mac_address (char *str) +{ + char mac[6]; + + if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) { + sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + } else { + strcpy (str, "ERROR"); + return -1; + } + return 0; +} + +static int hwc_manufact_date (char *str) +{ + uchar byte; + int value; + + if (seeprom_read (0x92, &byte, sizeof (byte))) + goto out; + value = byte; + if (seeprom_read (0x93, &byte, sizeof (byte))) + goto out; + value += byte << 8; + sprintf (str, "%02d/%02d/%04d", + value & 0x1F, (value >> 5) & 0xF, + 1980 + ((value >> 9) & 0x1FF)); + return 0; + +out: + strcpy (str, "ERROR"); + return -1; +} + +static int hwc_board_type (char **str) +{ + ushort id = 0; + + if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) { + switch (id) { + case 0x9080: + *str = "4532-002"; + break; + case 0x9081: + *str = "4532-001"; + break; + case 0x9082: + *str = "4532-000"; + break; + default: + *str = "Unknown"; + } + } else { + *str = "Unknown"; + } + + return id; +} + +long int initdram (int board_type) +{ + long maxsize = hwc_main_sdram_size(); + +#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE) + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar *base; + int i; + + immap->im_siu_conf.sc_ppc_acr = 0x00000026; + immap->im_siu_conf.sc_ppc_alrh = 0x01276345; + immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; + immap->im_siu_conf.sc_lcl_acr = 0x00000000; + immap->im_siu_conf.sc_lcl_alrh = 0x01234567; + immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; + immap->im_siu_conf.sc_tescr1 = 0x00004000; + immap->im_siu_conf.sc_ltescr1 = 0x00004000; + + memctl->memc_mptpr = CFG_MPTPR; + + /* Initialise 60x bus SDRAM */ + base = (uchar *)(CFG_SDRAM_BASE | 0x110); + memctl->memc_psrt = CFG_PSRT; + memctl->memc_or1 = CFG_60x_OR; + memctl->memc_br1 = CFG_SDRAM_BASE | CFG_60x_BR; + + memctl->memc_psdmr = CFG_PSDMR | 0x28000000; + *base = 0xFF; + memctl->memc_psdmr = CFG_PSDMR | 0x08000000; + for (i = 0; i < 8; i++) + *base = 0xFF; + memctl->memc_psdmr = CFG_PSDMR | 0x18000000; + *base = 0xFF; + memctl->memc_psdmr = CFG_PSDMR | 0x40000000; + + /* Initialise local bus SDRAM */ + base = (uchar *)CFG_LSDRAM_BASE; + memctl->memc_lsrt = CFG_LSRT; + memctl->memc_or2 = CFG_LOC_OR; + memctl->memc_br2 = CFG_LSDRAM_BASE | CFG_LOC_BR; + + memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; + *base = 0xFF; + memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; + for (i = 0; i < 8; i++) + *base = 0xFF; + memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; + *base = 0xFF; + memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2; + + maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize); + + memctl->memc_or1 |= ~(maxsize - 1); + + if (maxsize != hwc_main_sdram_size()) + puts("Oops: memory test has not found all memory!\n"); +#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */ + + /* Return total RAM size (size of 60x SDRAM) */ + return maxsize; +} + +int checkboard(void) +{ + char string[32], *id; + + hwc_manufact_date(string); + hwc_board_type(&id); + printf("Board: Interphase iSPAN %s (#%d %s)\n", + id, hwc_serial_number(), string); +#ifdef DEBUG + printf("Manufacturing date: %s\n", string); + printf("Serial number : %d\n", hwc_serial_number()); + printf("FLASH size : %d MB\n", hwc_flash_size() >> 20); + printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20); + printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20); + hwc_mac_address(string); + printf("MAC address : %s\n", string); +#endif + return 0; +} + +int misc_init_r(void) +{ + char *s, str[32]; + int num; + + if ((s = getenv("serial#")) == NULL && + (num = hwc_serial_number()) != -1) { + sprintf(str, "%06d", num); + setenv("serial#", str); + } + if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) { + setenv("ethaddr", str); + } + + return 0; +} diff --git a/board/ispan/u-boot.lds b/board/ispan/u-boot.lds new file mode 100644 index 0000000..bf8048d --- /dev/null +++ b/board/ispan/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/ivm/Makefile b/board/ivm/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/ivm/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/ivm/config.mk b/board/ivm/config.mk new file mode 100644 index 0000000..37e7185 --- /dev/null +++ b/board/ivm/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# IVM boards +# + +TEXT_BASE = 0xFF000000 diff --git a/board/ivm/flash.c b/board/ivm/flash.c new file mode 100644 index 0000000..140ba2d --- /dev/null +++ b/board/ivm/flash.c @@ -0,0 +1,598 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \ + BR_MS_GPCM | BR_PS_16 | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size_b0; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_MT: + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + ((i-3) * 0x00020000); + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + return; + + case FLASH_MAN_SST: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00002000); + } + return; + + case FLASH_MAN_AMD: + case FLASH_MAN_FUJ: + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + return; + default: + printf ("Don't know sector ofsets for flash type 0x%lx\n", + info->flash_id); + return; + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("Fujitsu "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_MT: printf ("MT "); break; + case FLASH_MAN_INTEL: printf ("Intel "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n"); + break; + case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n"); + break; + case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n"); + break; + case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n"); + break; + case FLASH_28F008S5: printf ("28F008S5 (1M = 64K x 16)\n"); + break; + case FLASH_28F400_T: printf ("28F400B3 (4Mbit, top boot sector)\n"); + break; + case FLASH_28F400_B: printf ("28F400B3 (4Mbit, bottom boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >= (1 << 20)) { + i = 20; + } else { + i = 10; + } + printf (" Size: %ld %cB in %d Sectors\n", + info->size >> i, + (i == 20) ? 'M' : 'k', + info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + ushort value; + vu_short *saddr = (vu_short *)addr; + + /* Read Manufacturer ID */ + saddr[0] = 0x0090; + value = saddr[0]; + + switch (value) { + case (AMD_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_FUJ; + break; + case (SST_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_SST; + break; + case (STM_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_STM; + break; + case (MT_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_MT; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + saddr[0] = 0x00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + value = saddr[1]; /* device ID */ + + switch (value) { + case (AMD_ID_LV400T & 0xFFFF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV400B & 0xFFFF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800T & 0xFFFF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV800B & 0xFFFF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160T & 0xFFFF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV160B & 0xFFFF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & 0xFFFF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (AMD_ID_LV320B & 0xFFFF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + case (SST_ID_xF200A & 0xFFFF): + info->flash_id += FLASH_SST200A; + info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */ + info->size = 0x00080000; + break; + case (SST_ID_xF400A & 0xFFFF): + info->flash_id += FLASH_SST400A; + info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */ + info->size = 0x00100000; + break; + case (SST_ID_xF800A & 0xFFFF): + info->flash_id += FLASH_SST800A; + info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */ + info->size = 0x00200000; + break; /* => 2 MB */ + case (STM_ID_x800AB & 0xFFFF): + info->flash_id += FLASH_STM800AB; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + case (MT_ID_28F400_T & 0xFFFF): + info->flash_id += FLASH_28F400_T; + info->sector_count = 7; + info->size = 0x00080000; + break; /* => 512 kB */ + case (MT_ID_28F400_B & 0xFFFF): + info->flash_id += FLASH_28F400_B; + info->sector_count = 7; + info->size = 0x00080000; + break; /* => 512 kB */ + default: + info->flash_id = FLASH_UNKNOWN; + saddr[0] = 0x00FF; /* restore read mode */ + return (0); /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + saddr[0] = 0x00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MT) { + printf ("Can erase only MT flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *)(info->start[sect]); + unsigned short status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = 0x0050; /* clear status register */ + *addr = 0x0020; /* erase setup */ + *addr = 0x00D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & 0x0080) != 0x0080) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0x00FF; /* reset to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = 0x00FF; /* reset to read mode */ + } + } + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 2 /* flash bus width in bytes */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= FLASH_WIDTH) { + data = 0; + for (i=0; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i CFG_FLASH_WRITE_TOUT) { + *addr = 0x00FF; /* restore read mode */ + return (1); + } + } + + *addr = 0x00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c new file mode 100644 index 0000000..7927ea9 --- /dev/null +++ b/board/ivm/ivm.c @@ -0,0 +1,352 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_STATUS_LED +# include +#endif + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +/* + * 50 MHz SHARC access using UPM A + */ +const uint sharc_table[] = { + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04, + 0xFFFFEC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04, + 0xFFFFEC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + + +/* + * 50 MHz SDRAM access using UPM B + */ +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */ + _NOT_USED_, + /* + * SDRAM Initialization (offset 5 in UPM RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00, + 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00, + 0xE1BBBC04, 0x1FF77C45, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84, + 0xFFFFFC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + */ + +int checkboard (void) +{ +#ifdef CONFIG_IVMS8 + puts ("Board: IVMS8\n"); +#endif +#ifdef CONFIG_IVML24 + puts ("Board: IVM-L8/24\n"); +#endif + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + long int size_b0; + + /* enable SDRAM clock ("switch on" SDRAM) */ + immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */ + immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE; /* output */ + immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE; /* assert SDRAM CLKE */ + udelay (1); + + /* + * Map controller bank 1 for ELIC SACCO + */ + memctl->memc_or1 = CFG_OR1; + memctl->memc_br1 = CFG_BR1; + + /* + * Map controller bank 2 for ELIC EPIC + */ + memctl->memc_or2 = CFG_OR2; + memctl->memc_br2 = CFG_BR2; + + /* + * Configure UPMA for SHARC + */ + upmconfig (UPMA, (uint *) sharc_table, + sizeof (sharc_table) / sizeof (uint)); + +#if defined(CONFIG_IVML24) + /* + * Map controller bank 4 for HDLC Address space + */ + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; +#endif + + /* + * Map controller bank 5 for SHARC + */ + memctl->memc_or5 = CFG_OR5; + memctl->memc_br5 = CFG_BR5; + + memctl->memc_mamr = 0x00001000; + + /* + * Configure UPMB for SDRAM + */ + upmconfig (UPMB, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ + + udelay (200); + memctl->memc_mcr = 0x80806105; /* precharge */ + udelay (1); + memctl->memc_mcr = 0x80806106; /* load mode register */ + udelay (1); + memctl->memc_mcr = 0x80806130; /* autorefresh */ + udelay (1); + memctl->memc_mcr = 0x80806130; /* autorefresh */ + udelay (1); + memctl->memc_mcr = 0x80806130; /* autorefresh */ + udelay (1); + memctl->memc_mcr = 0x80806130; /* autorefresh */ + udelay (1); + memctl->memc_mcr = 0x80806130; /* autorefresh */ + udelay (1); + memctl->memc_mcr = 0x80806130; /* autorefresh */ + udelay (1); + memctl->memc_mcr = 0x80806130; /* autorefresh */ + udelay (1); + memctl->memc_mcr = 0x80806130; /* autorefresh */ + + memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ + + /* + * Check Bank 0 Memory Size for re-configuration + */ + size_b0 = + dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); + + memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + + memctl->memc_mbmr = mamr_value; + + return (get_ram_size (base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +void reset_phy (void) +{ + immap_t *immr = (immap_t *) CFG_IMMR; + + /* De-assert Ethernet Powerdown */ + immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */ + immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN; /* output */ + immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + udelay (1000); + + /* + * RESET is implemented by a positive pulse of at least 1 us + * at the reset pin. + * + * Configure RESET pins for NS DP83843 PHY, and RESET chip. + * + * Note: The RESET pin is high active, but there is an + * inverter on the SPD823TS board... + */ + immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET); + immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET; + /* assert RESET signal of PHY */ + immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET); + udelay (10); + /* de-assert RESET signal of PHY */ + immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET; + udelay (10); +} + +/* ------------------------------------------------------------------------- */ + +void show_boot_progress (int status) +{ +#if defined(CONFIG_STATUS_LED) +# if defined(STATUS_LED_YELLOW) + status_led_set (STATUS_LED_YELLOW, + (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF); +# endif /* STATUS_LED_YELLOW */ +# if defined(STATUS_LED_BOOT) + if (status == 6) + status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF); +# endif /* STATUS_LED_BOOT */ +#endif /* CONFIG_STATUS_LED */ +} + +/* ------------------------------------------------------------------------- */ + +void ide_set_reset (int on) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* + * Configure PC for IDE Reset Pin + */ + if (on) { /* assert RESET */ + immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); + } else { /* release RESET */ + immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; + } + + /* program port pin as GPIO output */ + immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds new file mode 100644 index 0000000..fdeabc5 --- /dev/null +++ b/board/ivm/u-boot.lds @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug new file mode 100644 index 0000000..3214f3f --- /dev/null +++ b/board/ivm/u-boot.lds.debug @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ixdp425/Makefile b/board/ixdp425/Makefile new file mode 100644 index 0000000..e4282c4 --- /dev/null +++ b/board/ixdp425/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := ixdp425.o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ixdp425/config.mk b/board/ixdp425/config.mk new file mode 100644 index 0000000..9f616f3 --- /dev/null +++ b/board/ixdp425/config.mk @@ -0,0 +1,2 @@ +#TEXT_BASE = 0x00100000 +TEXT_BASE = 0x00f80000 diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c new file mode 100644 index 0000000..1d958c8 --- /dev/null +++ b/board/ixdp425/flash.c @@ -0,0 +1,427 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) x +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + _bss_start - _armboot_start, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = (FPW) 0x00500050; /* clear status register cmd. */ + *addr = (FPW) 0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c new file mode 100644 index 0000000..c04626a --- /dev/null +++ b/board/ixdp425/ixdp425.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + + +/* local prototypes */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +/**********************************************************/ + +int board_post_init (void) +{ + return (0); +} + +/**********************************************************/ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of IXDP */ + gd->bd->bi_arch_number = MACH_TYPE_IXDP425; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + return 0; +} + +/**********************************************************/ + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +/**********************************************************/ + +extern struct pci_controller hose; +extern void pci_ixp_init(struct pci_controller * hose); + +void pci_init_board(void) +{ + extern void pci_ixp_init (struct pci_controller *hose); + + pci_ixp_init(&hose); +} diff --git a/board/ixdp425/u-boot.lds b/board/ixdp425/u-boot.lds new file mode 100644 index 0000000..e2ceac7 --- /dev/null +++ b/board/ixdp425/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/ixp/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/jse/Makefile b/board/jse/Makefile new file mode 100644 index 0000000..0da27b6 --- /dev/null +++ b/board/jse/Makefile @@ -0,0 +1,44 @@ +# +# Copyright 2004 Picture Elements, Inc. +# Stephen Williams +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o sdram.o flash.o host_bridge.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/jse/README.txt b/board/jse/README.txt new file mode 100644 index 0000000..84497db --- /dev/null +++ b/board/jse/README.txt @@ -0,0 +1,48 @@ +JSE Configuration Details + +Memory Bank 0 -- Flash chip +--------------------------- + +0xfff00000 - 0xffffffff + +The flash chip is really only 512Kbytes, but the high address bit of +the 1Meg region is ignored, so the flash is replicated through the +region. Thus, this is consistent with a flash base address 0xfff80000. + +The placement at the end is to be consistent with reset behavior, +where the processor itself initially uses this bus to load the branch +vector and start running. + +On-Chip Memory +-------------- + +0xf4000000 - 0xf4000fff + +The 405GPr includes a 4K on-chip memory that can be placed however +software chooses. I choose to place the memory at this address, to +keep it out of the cachable areas. + + +Memory Bank 1 -- SystemACE Controller +------------------------------------- + +0xf0000000 - 0xf00fffff + +The SystemACE chip is along on peripheral bank CS#1. We don't need +much space, but 1Meg is the smallest we can configure the chip to +allocate. We need it far away from the flash region, because this +region is set to be non-cached. + + +Internal Peripherals +-------------------- + +0xef600300 - 0xef6008ff + +These are scattered various peripherals internal to the PPC405GPr +chip. + +SDRAM +----- + +0x00000000 - 0x07ffffff (128 MBytes) diff --git a/board/jse/config.mk b/board/jse/config.mk new file mode 100644 index 0000000..03ec085 --- /dev/null +++ b/board/jse/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2003 Picture Elements, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Picture Elements, Inc. JSE boards +# + +TEXT_BASE = 0xFFF80000 diff --git a/board/jse/flash.c b/board/jse/flash.c new file mode 100644 index 0000000..c462fe0 --- /dev/null +++ b/board/jse/flash.c @@ -0,0 +1,520 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +#if CFG_MAX_FLASH_BANKS != 1 +#error "CFG_MAX_FLASH_BANKS must be 1" +#endif +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static int write_word (flash_info_t * info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + + /* Init: no FLASHes known */ + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + /* Setup offsets */ + flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM, + FLASH_BASE0_PRELIM + monitor_flash_len - 1, + &flash_info[0]); + flash_info[0].size = size_b0; + + return size_b0; +} + + +/*----------------------------------------------------------------------- + */ +/* + * This implementation assumes that the flash chips are uniform sector + * devices. This is true for all likely JSE devices. + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + unsigned idx; + unsigned long sector_size = info->size / info->sector_count; + + for (idx = 0; idx < info->sector_count; idx += 1) { + info->start[idx] = base + (idx * sector_size); + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_SST: + printf ("SST "); + break; + case FLASH_MAN_STM: + printf ("ST Micro "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + /* (Reduced table of only parts expected in JSE boards.) */ + switch (info->flash_id) { + case FLASH_MAN_AMD | FLASH_AM040: + printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_MAN_STM | FLASH_AM040: + printf ("MM29W040W (512 Kbit, uniform sector size)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *) info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; + + value = addr2[0]; + + switch (value) { + case (FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + printf("Unknown flash manufacturer code: 0x%x\n", value); + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */ + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* Calculate the sector offsets (Use JSE Optimized code). */ + flash_get_offsets(base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *) info->start[0]; + *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7 (flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = + (FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); + printf ("Erasing sector %p\n", addr2); /* CLH */ + + if ((info->flash_id & FLASH_VENDMASK) == + FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay (1000); /* wait 1 ms */ + } else { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7 (info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#if 0 + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + wait_for_DQ7 (info, l_sect); + +DONE: +#endif + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = + (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/jse/host_bridge.c b/board/jse/host_bridge.c new file mode 100644 index 0000000..363be97 --- /dev/null +++ b/board/jse/host_bridge.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2004 Picture Elements, Inc. + * Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +#ident "$Id:$" + +# include +# include +# include "jse_priv.h" + +/* + * The JSE board has an Intel 21555 non-transparent bridge for + * communication with the host. We need to render it harmless on the + * JSE side, but leave it alone on the host (primary) side. Normally, + * this will all be done before the host BIOS can gain access to the + * board, due to the Primary Access Lockout bit. + * + * The host_bridge_init function is called as a late initialization + * function, after most of the board is set up, including a PCI scan. + */ + +void host_bridge_init (void) +{ + /* The bridge chip is at a fixed location. */ + pci_dev_t dev = PCI_BDF (0, 10, 0); + + /* Set PCI Class code -- + The primary side sees this class code at 0x08 in the + primary config space. This must be something other then a + bridge, or MS Windows starts doing weird stuff to me. */ + pci_write_config_dword (dev, 0x48, 0x04800000); + + /* Set subsystem ID -- + The primary side sees this value at 0x2c. We set it here so + that the host can tell what sort of device this is: + We are a Picture Elements [0x12c5] JSE [0x008a]. */ + pci_write_config_dword (dev, 0x6c, 0x008a12c5); + + /* Downstream (Primary-to-Secondary) BARs are set up mostly + off. We need only the Memory-0 Bar so that the host can get + at the CSR region to set up tables and the lot. */ + + /* Downstream Memory 0 setup (4K for CSR) */ + pci_write_config_dword (dev, 0xac, 0xfffff000); + /* Downstream Memory 1 setup (off) */ + pci_write_config_dword (dev, 0xb0, 0x00000000); + /* Downstream Memory 2 setup (off) */ + pci_write_config_dword (dev, 0xb4, 0x00000000); + /* Downstream Memory 3 setup (off) */ + pci_write_config_dword (dev, 0xb8, 0x00000000); + + /* Upstream (Secondary-to-Primary) BARs are used to get at + host memory from the JSE card. Create two regions: a small + one to manage individual word reads/writes, and a larger + one for doing bulk frame moves. */ + + /* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */ + pci_write_config_dword (dev, 0xc4, 0xfffff000); + /* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */ + pci_write_config_dword (dev, 0xc8, 0xfffff000); + + /* Upstream Memory 2 (BAR4) uses page translation, and is set + up in CCR1. Configure for 4K pages. */ + + /* Set CCR1,0 reigsters. This clears the Primary PCI Lockout + bit as well, so we are done configuring after this + point. Therefore, this must be the last step. + + CC1[15:12]= 0 (disable I2O message unit) + CC1[11:8] = 0x5 (4K page size) + CC0[11] = 1 (Secondary Clock Disable: disable clock) + CC0[10] = 0 (Primary Access Lockout: allow primary access) + */ + pci_write_config_dword (dev, 0xcc, 0x05000800); +} diff --git a/board/jse/init.S b/board/jse/init.S new file mode 100644 index 0000000..231cd1c --- /dev/null +++ b/board/jse/init.S @@ -0,0 +1,105 @@ +/*------------------------------------------------------------------------+ */ +/* */ +/* This source code has been made available to you by IBM on an AS-IS */ +/* basis. Anyone receiving this source is licensed under IBM */ +/* copyrights to use it in any way he or she deems fit, including */ +/* copying it, modifying it, compiling it, and redistributing it either */ +/* with or without modifications. No license under IBM patents or */ +/* patent applications is to be implied by the copyright license. */ +/* */ +/* Any user of this software should understand that IBM cannot provide */ +/* technical support for this software and will not be responsible for */ +/* any consequences resulting from the use of this software. */ +/* */ +/* Any person who transfers this source code or any derivative work */ +/* must include the IBM copyright notice, this paragraph, and the */ +/* preceding two paragraphs in the transferred software. */ +/* */ +/* COPYRIGHT I B M CORPORATION 1995 */ +/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ +/*------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------- */ +/* Function: ext_bus_cntlr_init */ +/* Description: Initializes the External Bus Controller for the external */ +/* peripherals. IMPORTANT: For pass1 this code must run from */ +/* cache since you can not reliably change a peripheral banks */ +/* timing register (pbxap) while running code from that bank. */ +/* For ex., since we are running from ROM on bank 0, we can NOT */ +/* execute the code that modifies bank 0 timings from ROM, so */ +/* we run it from cache. */ +/* */ +/* */ +/* The layout for the PEI JSE board: */ +/* Bank 0 - Flash and SRAM */ +/* Bank 1 - SystemACE */ +/* Bank 2 - not used */ +/* Bank 3 - not used */ +/* Bank 4 - not used */ +/* Bank 5 - not used */ +/* Bank 6 - not used */ +/* Bank 7 - not used */ +/*------------------------------------------------------------------------- */ +#include + +#include +#include + +#include +#include + +#define cpc0_cr0 0xB1 + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + mflr r4 /* save link register */ + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 10; used to prefetch */ + mtctr r4 /* 10 cache lines to fit this function */ + /* in cache (gives us 8x10=80 instrctns) */ +..ebcloop: + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 10 cache lines */ + + /*----------------------------------------------------------------- */ + /* Delay to ensure all accesses to ROM are complete before changing */ + /* bank 0 timings. 200usec should be enough. */ + /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ + /*----------------------------------------------------------------- */ + addis r3,0,0x0 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + /*----------------------------------------------------------------- */ + /* Memory Bank 0 (Flash) initialization */ + /*----------------------------------------------------------------- */ + + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,0x9B01 + ori r4,r4,0x5480 + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ + ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ + mtdcr ebccfgd,r4 + + blr + + +/*----------------------------------------------------------------------- */ +/* Function: sdram_init */ +/* Description: This function is called by cpu/ppc4xx/start.S code */ +/* to get the SDRAM initialized. */ +/*----------------------------------------------------------------------- */ + .globl sdram_init +sdram_init: + blr diff --git a/board/jse/jse.c b/board/jse/jse.c new file mode 100644 index 0000000..9290814 --- /dev/null +++ b/board/jse/jse.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2004 Picture Elements, Inc. + * Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +# include +# include +# include +# include +# include "jse_priv.h" + +/* + * This function is run very early, out of flash, and before devices are + * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * of being in the init_sequence array. + * + * The SDRAM has been initialized already -- start.S:start called + * init.S:init_sdram early on -- but it is not yet being used for + * anything, not even stack. So be careful. + */ +int board_early_init_f (void) +{ + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the JSE board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED/UNUSED + | IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive + | IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive + | IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive + | IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive + | IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high + | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused) + | IRQ 31 (EXT IRQ 6) (unused) + +-------------------------------------------------------------------------*/ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* Configure the interface to the SystemACE MCU port. + The SystemACE is fast, but there is no reason to have + excessivly tight timings. So the settings are slightly + generous. */ + + /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1, + WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */ + mtdcr (ebccfga, pb1ap); + mtdcr (ebccfgd, 0x01011000); + + /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */ + mtdcr (ebccfga, pb1cr); + mtdcr (ebccfgd, CFG_SYSTEMACE_BASE | 0x00018000); + + /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */ + /* CPC0_CR1 |= PCIPW */ + mtdcr (0xb2, mfdcr (0xb2) | 0x00004000); + + return 0; +} + +#ifdef CONFIG_BOARD_PRE_INIT +int board_pre_init (void) +{ + return board_early_init_f (); +} + +#endif + +/* + * This function is also called by lib_ppc/board.c:board_init_f (it is + * also in the init_sequence array) but later. Many more things are + * configured, but we are still running from flash. + */ +int checkboard (void) +{ + unsigned vers, status; + + /* check that the SystemACE chip is alive. */ + printf ("ACE: "); + vers = readw (CFG_SYSTEMACE_BASE + 0x16); + printf ("SystemACE %u.%u (build %u)", + (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff); + + status = readl (CFG_SYSTEMACE_BASE + 0x04); +#ifdef DEBUG + printf (" STATUS=0x%08x", status); +#endif + /* If the flash card is present and there is an initial error, + then force a restart of the program. */ + if (status & 0x00000010) { + printf (" CFDETECT"); + + if (status & 0x04) { + /* CONTROLREG = CFGPROG */ + writew (0x1000, CFG_SYSTEMACE_BASE + 0x18); + udelay (500); + /* CONTROLREG = CFGRESET */ + writew (0x0080, CFG_SYSTEMACE_BASE + 0x18); + udelay (500); + writew (0x0000, CFG_SYSTEMACE_BASE + 0x18); + /* CONTROLREG = CFGSTART */ + writew (0x0020, CFG_SYSTEMACE_BASE + 0x18); + + status = readl (CFG_SYSTEMACE_BASE + 0x04); + } + } + + /* Wait for the SystemACE to program its chain of devices. */ + while ((status & 0x84) == 0x00) { + udelay (500); + status = readl (CFG_SYSTEMACE_BASE + 0x04); + } + + if (status & 0x04) + printf (" CFG-ERROR"); + if (status & 0x80) + printf (" CFGDONE"); + + printf ("\n"); + + /* Force /RTS to active. The board it not wired quite + correctly to use cts/rtc flow control, so just force the + /RST active and forget about it. */ + writeb (readb (0xef600404) | 0x03, 0xef600404); + + printf ("JSE: ready\n"); + + return 0; +} + +/* **** No more functions called by board_init_f. **** */ + +/* + * This function is called by lib_ppc/board.c:board_init_r. At this + * point, basic setup is done, U-Boot has been moved into SDRAM and + * PCI has been set up. From here we done late setup. + */ +int misc_init_r (void) +{ + host_bridge_init (); + return 0; +} diff --git a/board/jse/jse_priv.h b/board/jse/jse_priv.h new file mode 100644 index 0000000..ed4894b --- /dev/null +++ b/board/jse/jse_priv.h @@ -0,0 +1,25 @@ +#ifndef __jse_priv_H +#define __jse_prov_H +/* + * Copyright (c) 2004 Picture Elements, Inc. + * Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +extern void host_bridge_init(void); + +#endif diff --git a/board/jse/sdram.c b/board/jse/sdram.c new file mode 100644 index 0000000..9060d97 --- /dev/null +++ b/board/jse/sdram.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2004 Picture Elements, Inc. + * Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include +#include + +# define SDRAM_LEN 0x08000000 + +/* + * this is even after checkboard. It returns the size of the SDRAM + * that we have installed. This function is called by board_init_f + * in lib_ppc/board.c to initialize the memory and return what I + * found. + */ +long int initdram (int board_type) +{ + /* Configure the SDRAMS */ + + /* disable memory controller */ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x00000000); + + udelay (500); + + /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ + mtdcr (memcfga, mem_besra); + mtdcr (memcfgd, 0xffffffff); + + /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ + mtdcr (memcfga, mem_besrb); + mtdcr (memcfgd, 0xffffffff); + + /* Clear SDRAM0_ECCCFG (disable ECC) */ + mtdcr (memcfga, mem_ecccf); + mtdcr (memcfgd, 0x00000000); + + /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ + mtdcr (memcfga, mem_eccerr); + mtdcr (memcfgd, 0xffffffff); + + /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ + mtdcr (memcfga, mem_sdtr1); + mtdcr (memcfgd, 0x010a4016); + + /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ + mtdcr (memcfga, mem_mb0cf); + mtdcr (memcfgd, 0x00084001); + + /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ + mtdcr (memcfga, mem_mb1cf); + mtdcr (memcfgd, 0x04084001); + + /* Memory Bank 2 Config == BE=0 */ + mtdcr (memcfga, mem_mb2cf); + mtdcr (memcfgd, 0x00000000); + + /* Memory Bank 3 Config == BE=0 */ + mtdcr (memcfga, mem_mb3cf); + mtdcr (memcfgd, 0x00000000); + + /* refresh timer = 0x400 */ + mtdcr (memcfga, mem_rtr); + mtdcr (memcfgd, 0x04000000); + + /* Power management idle timer set to the default. */ + mtdcr (memcfga, mem_pmit); + mtdcr (memcfgd, 0x07c00000); + + udelay (500); + + /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x80e00000); + + return SDRAM_LEN; +} + +/* + * The U-Boot core, as part of the initialization to prepare for + * loading the monitor into SDRAM, requests of this function that the + * memory be tested. Return 0 if the memory tests OK. + */ +int testdram (void) +{ + unsigned long idx; + unsigned val; + unsigned errors; + volatile unsigned long *sdram; + +#ifdef DEBUG + printf ("SDRAM Controller Registers --\n"); + + mtdcr (memcfga, mem_mcopt1); + val = mfdcr (memcfgd); + printf (" SDRAM0_CFG : 0x%08x\n", val); + + mtdcr (memcfga, 0x24); + val = mfdcr (memcfgd); + printf (" SDRAM0_STATUS: 0x%08x\n", val); + + mtdcr (memcfga, mem_mb0cf); + val = mfdcr (memcfgd); + printf (" SDRAM0_B0CR : 0x%08x\n", val); + + mtdcr (memcfga, mem_mb1cf); + val = mfdcr (memcfgd); + printf (" SDRAM0_B1CR : 0x%08x\n", val); + + mtdcr (memcfga, mem_sdtr1); + val = mfdcr (memcfgd); + printf (" SDRAM0_TR : 0x%08x\n", val); + + mtdcr (memcfga, mem_rtr); + val = mfdcr (memcfgd); + printf (" SDRAM0_RTR : 0x%08x\n", val); +#endif + + /* Wait for memory to be ready by testing MRSCMPbit + bit. Really, there should already have been plenty of time, + given it was started long ago. But, best to check. */ + for (idx = 0; idx < 1000000; idx += 1) { + mtdcr (memcfga, 0x24); + val = mfdcr (memcfgd); + if (val & 0x80000000) + break; + } + + if (!(val & 0x80000000)) { + printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n"); + return 1; + } + + /* Start memory test. */ + printf ("test: %u MB - ", SDRAM_LEN / 1048576); + + sdram = (unsigned long *) CFG_SDRAM_BASE; + + printf ("write - "); + for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) { + sdram[idx + 0] = idx; + sdram[idx + 1] = ~idx; + } + + printf ("read - "); + errors = 0; + for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) { + if (sdram[idx + 0] != idx) + errors += 1; + if (sdram[idx + 1] != ~idx) + errors += 1; + if (errors > 0) + break; + } + + if (errors > 0) { + printf ("NOT OK\n"); + printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n", + sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx); + return 1; + } + + printf ("ok\n"); + return 0; +} diff --git a/board/jse/u-boot.lds b/board/jse/u-boot.lds new file mode 100644 index 0000000..60c1115 --- /dev/null +++ b/board/jse/u-boot.lds @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : { + /* The start.o file includes the initial jump vector that + must be located in the beginning. It is the basic run- + time function that calls all other functions. */ + cpu/ppc4xx/start.o (.text) + + board/jse/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/kb9202/Makefile b/board/kb9202/Makefile new file mode 100644 index 0000000..f36d88d --- /dev/null +++ b/board/kb9202/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Adapted for KwikByte KB920x boards - APR2005 +# +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := kb9202.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/kb9202/config.mk b/board/kb9202/config.mk new file mode 100644 index 0000000..9ce161e --- /dev/null +++ b/board/kb9202/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x21f00000 diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c new file mode 100644 index 0000000..4a7cf77 --- /dev/null +++ b/board/kb9202/kb9202.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Adapted for KwikByte KB920x board from at91rm9200dk.c: 22APR2005 + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +void lowlevel_init(void) { + /* Required by assembly functions - do nothing */ +} + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Enable Ctrlc */ + console_init_f (); + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + gd->bd->bi_arch_number = MACH_TYPE_KB9200; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_DRIVER_ETHER +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac); +UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac); +UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac); +UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status); + +/* + * Name: + * at91rm9200_GetPhyInterface + * Description: + * Initialise the interface functions to the PHY + * Arguments: + * None + * Return value: + * None + */ +void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) +{ + p_phyops->Init = lxt972_InitPhy; + p_phyops->IsPhyConnected = lxt972_IsPhyConnected; + p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed; + p_phyops->AutoNegotiate = lxt972_AutoNegotiate; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/kb9202/u-boot.lds b/board/kb9202/u-boot.lds new file mode 100644 index 0000000..76df6b2 --- /dev/null +++ b/board/kb9202/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/kup/Makefile b/board/kup/Makefile new file mode 100644 index 0000000..071f0d2 --- /dev/null +++ b/board/kup/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o kup.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/kup/common/flash.c b/board/kup/common/flash.c new file mode 100644 index 0000000..903c88f --- /dev/null +++ b/board/kup/common/flash.c @@ -0,0 +1,515 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifndef CFG_ENV_ADDR +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +#define CONFIG_FLASH_16BIT + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + vu_short *s_addr=(vu_short*)addr; + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x0090; + + value = s_addr[0]; + value = value|(value<<16); + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = s_addr[1]; + value = value|(value<<16); + + switch (value) { + case FUJI_ID_29F800BA: + info->flash_id += FLASH_AM400T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + s_addr = (volatile unsigned short *)(info->start[i]); + info->protect[i] = s_addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + s_addr = (volatile unsigned short *)info->start[0]; + *s_addr = 0x00F0; /* reset bank */ + } + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect; + ulong start, now, last; +#ifdef CONFIG_FLASH_16BIT + vu_short *s_addr = (vu_short*)addr; +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } +/*#ifndef CONFIG_FLASH_16BIT + ulong type; + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return; + } +#endif*/ + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ +#ifdef CONFIG_FLASH_16BIT + vu_short *s_sect_addr = (vu_short*)(info->start[sect]); +#else + vu_long *sect_addr = (vu_long*)(info->start[sect]); +#endif + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + +#ifdef CONFIG_FLASH_16BIT + + /*printf("\ns_sect_addr=%x",s_sect_addr);*/ + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x0080; + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_sect_addr[0] = 0x0030; +#else + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + addr[0x5555] = 0x00800080; + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + sect_addr[0] = 0x00300030; +#endif + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#ifdef CONFIG_FLASH_16BIT + while ((s_sect_addr[0] & 0x0080) != 0x0080) { +#else + while ((sect_addr[0] & 0x00800080) != 0x00800080) { +#endif + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + } + } + + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; +#ifdef CONFIG_FLASH_16BIT + s_addr[0] = 0x00F0; /* reset bank */ +#else + addr[0] = 0x00F000F0; /* reset bank */ +#endif + + printf (" done\n"); + return 0; +} + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + +#ifdef CONFIG_FLASH_16BIT + vu_short high_data; + vu_short low_data; + vu_short *s_addr = (vu_short*)addr; +#endif + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + +#ifdef CONFIG_FLASH_16BIT + /* Write the 16 higher-bits */ + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + high_data = ((data>>16) & 0x0000ffff); + + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x00A0; + + *((vu_short *)dest) = high_data; + + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + + /* Write the 16 lower-bits */ +#endif + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); +#ifdef CONFIG_FLASH_16BIT + dest += 0x2; + low_data = (data & 0x0000ffff); + + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x00A0; + *((vu_short *)dest) = low_data; + +#else + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + addr[0x5555] = 0x00A000A0; + *((vu_long *)dest) = data; +#endif + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + +#ifdef CONFIG_FLASH_16BIT + while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { +#else + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { +#endif + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c new file mode 100644 index 0000000..d018e3c --- /dev/null +++ b/board/kup/common/kup.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2004 + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "kup.h" + +int misc_init_f (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile sysconf8xx_t *siu = &immap->im_siu_conf; + + while (siu->sc_sipend & 0x20000000) { + /* printf("waiting for 5V VCC\n"); */ + ; + } + + /* RS232 / RS485 default is RS232 */ + immap->im_ioport.iop_padat &= ~(PA_RS485); + immap->im_ioport.iop_papar &= ~(PA_RS485); + immap->im_ioport.iop_paodr &= ~(PA_RS485); + immap->im_ioport.iop_padir |= (PA_RS485); + return (0); +} + + +#ifdef CONFIG_IDE_LED +void ide_led (uchar led, uchar status) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* We have one led for both pcmcia slots */ + if (status) { /* led on */ + immap->im_ioport.iop_padat &= ~(PA_LED_YELLOW); + } else { + immap->im_ioport.iop_padat |= (PA_LED_YELLOW); + } +} +#endif + +void poweron_key (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1); + immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1); + + if (immap->im_ioport.iop_pcdat & (PC_SWITCH1)) + setenv ("key1", "off"); + else + setenv ("key1", "on"); +} + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed (void) +{ + return (0); +} +#endif diff --git a/board/kup/common/kup.h b/board/kup/common/kup.h new file mode 100644 index 0000000..70d7f01 --- /dev/null +++ b/board/kup/common/kup.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2004 + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __KUP_H +#define __KUP_H + +#define PA_8 0x0080 +#define PA_11 0x0010 +#define PA_12 0x0008 + +#define PB_14 0x00020000 +#define PB_17 0x00004000 + +#define PC_9 0x0040 + +#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ +#define PA_LED_YELLOW PA_8 +#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off*/ +#define PB_LCD_PWM PB_17 /* PB 17 */ +#define PC_SWITCH1 PC_9 /* Reboot switch */ + +extern void poweron_key (void); + +#endif /* __KUP_H */ diff --git a/board/kup/common/load_sernum_ethaddr.c b/board/kup/common/load_sernum_ethaddr.c new file mode 100644 index 0000000..b7b7499 --- /dev/null +++ b/board/kup/common/load_sernum_ethaddr.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/*----------------------------------------------------------------------- + * Process Hardware Information Block: + * + * If we boot on a system fresh from factory, check if the Hardware + * Information Block exists and save the information it contains. + * + * The KUP Hardware Information Block is defined as + * follows: + * - located in first flash bank + * - starts at offset CFG_HWINFO_OFFSET + * - size CFG_HWINFO_SIZE + * + * Internal structure: + * - sequence of ASCII character lines + * - fields separated by + * - last field terminated by NUL character (0x00) + * + * Fields in Hardware Information Block: + * 1) Module Type + * 2) MAC Address + * 3) .... + */ + + +#define ETHADDR_TOKEN "ethaddr=" +#define LCD_TOKEN "lcd=" + +void load_sernum_ethaddr (void) +{ + unsigned char *hwi; + char *var; + unsigned char hwi_stack[CFG_HWINFO_SIZE]; + char *p; + + hwi = (unsigned char *) (CFG_FLASH_BASE + CFG_HWINFO_OFFSET); + if (*((unsigned long *) hwi) != (unsigned long) CFG_HWINFO_MAGIC) { + printf ("HardwareInfo not found!\n"); + return; + } + memcpy (hwi_stack, hwi, CFG_HWINFO_SIZE); + + /* + ** ethaddr + */ + var = strstr ((char *)hwi_stack, ETHADDR_TOKEN); + if (var) { + var += sizeof (ETHADDR_TOKEN) - 1; + p = strchr (var, '\r'); + if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) { + *p = '\0'; + setenv ("ethaddr", var); + *p = '\r'; + } + } + /* + ** lcd + */ + var = strstr ((char *)hwi_stack, LCD_TOKEN); + if (var) { + var += sizeof (LCD_TOKEN) - 1; + p = strchr (var, '\r'); + if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) { + *p = '\0'; + setenv ("lcd", var); + *p = '\r'; + } + } +} diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile new file mode 100644 index 0000000..62d289b --- /dev/null +++ b/board/kup/kup4k/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/kup/kup4k/config.mk b/board/kup/kup4k/config.mk new file mode 100644 index 0000000..22e30b2 --- /dev/null +++ b/board/kup/kup4k/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# KUP4K board +# + +TEXT_BASE = 0x40000000 diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c new file mode 100644 index 0000000..e621c43 --- /dev/null +++ b/board/kup/kup4k/kup4k.c @@ -0,0 +1,459 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "../common/kup.h" +#ifdef CONFIG_KUP4K_LOGO + #include "s1d13706.h" +#endif + +#undef DEBUG +#ifdef DEBUG +# define debugk(fmt,args...) printf(fmt ,##args) +#else +# define debugk(fmt,args...) +#endif + +typedef struct { + volatile unsigned char *VmemAddr; + volatile unsigned char *RegAddr; +} FB_INFO_S1D13xxx; + + +/* ------------------------------------------------------------------------- */ + +#if 0 +static long int dram_size (long int, long int *, long int); +#endif + +#ifdef CONFIG_KUP4K_LOGO +void lcd_logo(bd_t *bd); +#endif + + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + uchar *latch,rev,mod; + + /* + * Init ChipSelect #4 (CAN + HW-Latch) + */ + immap->im_memctl.memc_or4 = 0xFFFF8926; + immap->im_memctl.memc_br4 = 0x90000401; + __asm__ ("eieio"); + latch=(uchar *)0x90000200; + rev = (*latch & 0xF8) >> 3; + mod=(*latch & 0x03); + printf ("Board: KUP4K Rev %d.%d\n",rev,mod); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0 = 0; + long int size_b1 = 0; + long int size_b2 = 0; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ +/* memctl->memc_or1 = CFG_OR1_PRELIM; */ +/* memctl->memc_br1 = CFG_BR1_PRELIM; */ + +/* memctl->memc_or2 = CFG_OR2_PRELIM; */ +/* memctl->memc_br2 = CFG_BR2_PRELIM; */ + + + memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ + udelay (1); + memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ + udelay (1); + memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + udelay (1000); + +#if 0 /* 3 x 8MB */ + size_b0 = 0x00800000; + size_b1 = 0x00800000; + size_b2 = 0x00800000; + memctl->memc_mptpr = CFG_MPTPR; + udelay (1000); + memctl->memc_or1 = 0xFF800A00; + memctl->memc_br1 = 0x00000081; + memctl->memc_or2 = 0xFF000A00; + memctl->memc_br2 = 0x00800081; + memctl->memc_or3 = 0xFE000A00; + memctl->memc_br3 = 0x01000081; +#else /* 3 x 16 MB */ + size_b0 = 0x01000000; + size_b1 = 0x01000000; + size_b2 = 0x01000000; + memctl->memc_mptpr = CFG_MPTPR; + udelay (1000); + memctl->memc_or1 = 0xFF000A00; + memctl->memc_br1 = 0x00000081; + memctl->memc_or2 = 0xFE000A00; + memctl->memc_br2 = 0x01000081; + memctl->memc_or3 = 0xFC000A00; + memctl->memc_br3 = 0x02000081; +#endif + + udelay (10000); + + return (size_b0 + size_b1 + size_b2); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +#if 0 +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile long int *addr; + ulong cnt, val; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if (val != (~cnt)) { + return (cnt * sizeof (long)); + } + } + return (maxsize); +} +#endif + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_STATUS_LED + volatile immap_t *immap = (immap_t *) CFG_IMMR; +#endif +#ifdef CONFIG_KUP4K_LOGO + bd_t *bd = gd->bd; + + lcd_logo (bd); +#endif /* CONFIG_KUP4K_LOGO */ +#ifdef CONFIG_IDE_LED + /* Configure PA8 as output port */ + immap->im_ioport.iop_padir |= 0x80; + immap->im_ioport.iop_paodr |= 0x80; + immap->im_ioport.iop_papar &= ~0x80; + immap->im_ioport.iop_padat |= 0x80; /* turn it off */ +#endif + setenv("hw","4k"); + poweron_key(); + return (0); +} + +#ifdef CONFIG_KUP4K_LOGO + + +void lcd_logo (bd_t * bd) +{ + FB_INFO_S1D13xxx fb_info; + S1D_INDEX s1dReg; + S1D_VALUE s1dValue; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl; + ushort i; + uchar *fb; + int rs, gs, bs; + int r = 8, g = 8, b = 4; + int r1, g1, b1; + int n; + char tmp[64]; /* long enough for environment variables */ + int tft = 0; + + immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ + immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); + +/*----------------------------------------------------------------------------- */ +/* Initialize the chip and the frame buffer driver. */ +/*----------------------------------------------------------------------------- */ + memctl = &immr->im_memctl; + + + /* + * Init ChipSelect #5 (S1D13768) + */ + memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */ + memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ + __asm__ ("eieio"); + + fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); + fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); + + if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) + || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { + printf ("Warning:LCD Controller S1D13706 not found\n"); + setenv ("lcd", "none"); + return; + } + + + for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) { + s1dReg = aS1DRegs_prelimn[i].Index; + s1dValue = aS1DRegs_prelimn[i].Value; + debugk ("s13768 reg: %02x value: %02x\n", + aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value); + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = + s1dValue; + } + + + n = getenv_r ("lcd", tmp, sizeof (tmp)); + if (n > 0) { + if (!strcmp ("tft", tmp)) + tft = 1; + else + tft = 0; + } +#if 0 + if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04) + tft = 0; + else + tft = 1; +#endif + + debugk ("Port=0x%02x -> TFT=%d\n", tft, + ((S1D_VALUE *) fb_info.RegAddr)[0xAC]); + + /* init controller */ + if (!tft) { + for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) { + s1dReg = aS1DRegs_stn[i].Index; + s1dValue = aS1DRegs_stn[i].Value; + debugk ("s13768 reg: %02x value: %02x\n", + aS1DRegs_stn[i].Index, + aS1DRegs_stn[i].Value); + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] = + s1dValue; + } + n = getenv_r ("contrast", tmp, sizeof (tmp)); + ((S1D_VALUE *) fb_info.RegAddr)[0xB3] = + (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0; + switch (bd->bi_busfreq) { + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; + break; + case 48000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; + break; + default: + printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 64000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; + break; + } + /* setenv("lcd","stn"); */ + } else { + for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) { + s1dReg = aS1DRegs_tft[i].Index; + s1dValue = aS1DRegs_tft[i].Value; + debugk ("s13768 reg: %02x value: %02x\n", + aS1DRegs_tft[i].Index, + aS1DRegs_tft[i].Value); + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = + s1dValue; + } + + switch (bd->bi_busfreq) { + default: + printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; + break; + } + /* setenv("lcd","tft"); */ + } + + /* create and set colormap */ + rs = 256 / (r - 1); + gs = 256 / (g - 1); + bs = 256 / (b - 1); + for (i = 0; i < 256; i++) { + r1 = (rs * ((i / (g * b)) % r)) * 255; + g1 = (gs * ((i / b) % g)) * 255; + b1 = (bs * ((i) % b)) * 255; + debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); + S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), + (b1 >> 4)); + } + + /* copy bitmap */ + fb = (uchar *) (fb_info.VmemAddr); + memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240); +} +#endif /* CONFIG_KUP4K_LOGO */ diff --git a/board/kup/kup4k/s1d13706.h b/board/kup/kup4k/s1d13706.h new file mode 100644 index 0000000..cd5eccc --- /dev/null +++ b/board/kup/kup4k/s1d13706.h @@ -0,0 +1,174 @@ +/*---------------------------------------------------------------------------- */ +/* */ +/* File generated by S1D13706CFG.EXE */ +/* */ +/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ +/* All rights reserved. */ +/* */ +/*---------------------------------------------------------------------------- */ + +/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ + +#define S1D_DISPLAY_WIDTH 320 +#define S1D_DISPLAY_HEIGHT 240 +#define S1D_DISPLAY_BPP 8 +#define S1D_DISPLAY_SCANLINE_BYTES 320 +#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L +#define S1D_PHYSICAL_VMEM_SIZE 0x14000L +#define S1D_PHYSICAL_REG_ADDR 0x80080000L +#define S1D_PHYSICAL_REG_SIZE 0x100 +#define S1D_DISPLAY_PCLK 6250 +#define S1D_PALETTE_SIZE 256 +#define S1D_REGDELAYOFF 0xFFFE +#define S1D_REGDELAYON 0xFFFF + +#define S1D_WRITE_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ + ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ + ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ + ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ +} + +#define S1D_READ_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ + r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ + g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ + b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ +} + +typedef unsigned short S1D_INDEX; +typedef unsigned char S1D_VALUE; + + +typedef struct +{ + S1D_INDEX Index; + S1D_VALUE Value; +} S1D_REGS; + + +static S1D_REGS aS1DRegs_prelimn[] = +{ + {0x10,0x00}, /* PANEL Type Register */ + {0xA8,0x00}, /* GPIO Config Register 0 */ + {0xA9,0x80}, /* GPIO Config Register 1 */ + +}; + +static S1D_REGS aS1DRegs_stn[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x10,0xD0}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xF0}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x80}, /* Vertical Sync Pulse Width Register */ + {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x83}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xA8,0x01}, /* GPIO Config Register 0 */ + {0xA9,0x80}, /* GPIO Config Register 1 */ + {0xAC,0x01}, /* GPIO Status Control Register 0 */ + {0xAD,0x00}, /* GPIO Status Control Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; + +static S1D_REGS aS1DRegs_tft[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x05,0x42}, /* PCLK Config Register */ + {0x10,0x61}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x12,0x30}, /* Horizontal Total Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xFA}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x00}, /* Vertical Sync Pulse Width Register */ + {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x03}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xA8,0x01}, /* GPIO Config Register 0 */ + {0xA9,0x80}, /* GPIO Config Register 1 */ + {0xAC,0x01}, /* GPIO Status Control Register 0 */ + {0xAD,0x00}, /* GPIO Status Control Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds new file mode 100644 index 0000000..8625999 --- /dev/null +++ b/board/kup/kup4k/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) +/* + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) +*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug new file mode 100644 index 0000000..c0cf1cb --- /dev/null +++ b/board/kup/kup4k/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile new file mode 100644 index 0000000..62d289b --- /dev/null +++ b/board/kup/kup4x/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/kup/kup4x/config.mk b/board/kup/kup4x/config.mk new file mode 100644 index 0000000..61d4e09 --- /dev/null +++ b/board/kup/kup4x/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# KUP4X board +# + +TEXT_BASE = 0x40000000 diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c new file mode 100644 index 0000000..cd9ed13 --- /dev/null +++ b/board/kup/kup4x/kup4x.c @@ -0,0 +1,312 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "../common/kup.h" +#ifdef CONFIG_KUP4K_LOGO +/* #include "s1d13706.h" */ +#endif + +#define KUP4X_USB + + +typedef struct { + volatile unsigned char *VmemAddr; + volatile unsigned char *RegAddr; +} FB_INFO_S1D13xxx; + +/* ------------------------------------------------------------------------- */ + +int usb_init_kup4x (void); + + +#ifdef CONFIG_KUP4K_LOGO +void lcd_logo (bd_t * bd); +#endif + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile uchar *latch; + uchar rev, mod; + + /* + * Init ChipSelect #4 (CAN + HW-Latch) + */ + memctl->memc_or4 = 0xFFFF8926; + memctl->memc_br4 = 0x90000401; + __asm__ ("eieio"); + latch = (volatile uchar *) 0x90000200; + rev = (*latch & 0xF8) >> 3; + mod = (*latch & 0x03); + printf ("Board: KUP4X Rev %d.%d\n",rev,mod); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0 = 0; + long int size_b1 = 0; + long int size_b2 = 0; + long int size_b3 = 0; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ +/* memctl->memc_or1 = CFG_OR1_PRELIM; */ +/* memctl->memc_br1 = CFG_BR1_PRELIM; */ + +/* memctl->memc_or2 = CFG_OR2_PRELIM; */ +/* memctl->memc_br2 = CFG_BR2_PRELIM; */ + + memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ + udelay (1); + memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ + udelay (1); + memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x8000C105; /* SDRAM bank 2 */ + udelay (1); + memctl->memc_mcr = 0x8000C830; /* SDRAM bank 2 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x8000C106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + udelay (1000); +#if 0 /* 4 x 8MB */ + size_b0 = 0x00800000; + size_b1 = 0x00800000; + size_b2 = 0x00800000; + size_b3 = 0x00800000; + memctl->memc_mptpr = CFG_MPTPR; + udelay (1000); + memctl->memc_or1 = 0xFF800A00; + memctl->memc_br1 = 0x00000081; + memctl->memc_or2 = 0xFF000A00; + memctl->memc_br2 = 0x00800081; + memctl->memc_or3 = 0xFE000A00; + memctl->memc_br3 = 0x01000081; + memctl->memc_or6 = 0xFE000A00; + memctl->memc_br6 = 0x01800081; +#else /* 4 x 16 MB */ + size_b0 = 0x01000000; + size_b1 = 0x01000000; + size_b2 = 0x01000000; + size_b3 = 0x01000000; + memctl->memc_mptpr = CFG_MPTPR; + udelay (1000); + memctl->memc_or1 = 0xFF000A00; + memctl->memc_br1 = 0x00000081; + memctl->memc_or2 = 0xFE000A00; + memctl->memc_br2 = 0x01000081; + memctl->memc_or3 = 0xFD000A00; + memctl->memc_br3 = 0x02000081; + memctl->memc_or6 = 0xFC000A00; + memctl->memc_br6 = 0x03000081; +#endif + udelay (10000); + + return (size_b0 + size_b1 + size_b2 + size_b3); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +#if 0 +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile long int *addr; + ulong cnt, val; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if (val != (~cnt)) { + return (cnt * sizeof (long)); + } + } + return (maxsize); +} +#endif + +int misc_init_r (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + +#ifdef CONFIG_IDE_LED + /* Configure PA8 as output port */ + immap->im_ioport.iop_padir |= 0x80; + immap->im_ioport.iop_paodr |= 0x80; + immap->im_ioport.iop_papar &= ~0x80; + immap->im_ioport.iop_padat |= 0x80; /* turn it off */ +#endif +#ifdef KUP4X_USB + usb_init_kup4x (); +#endif + setenv ("hw", "4x"); + poweron_key (); + return (0); +} diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds new file mode 100644 index 0000000..8625999 --- /dev/null +++ b/board/kup/kup4x/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) +/* + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) +*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug new file mode 100644 index 0000000..c0cf1cb --- /dev/null +++ b/board/kup/kup4x/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/lantec/Makefile b/board/lantec/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/lantec/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/lantec/config.mk b/board/lantec/config.mk new file mode 100644 index 0000000..05ea3b9 --- /dev/null +++ b/board/lantec/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Lantec board (based on TQM8xxL config). +# + +TEXT_BASE = 0x40000000 diff --git a/board/lantec/flash.c b/board/lantec/flash.c new file mode 100644 index 0000000..0faa82c --- /dev/null +++ b/board/lantec/flash.c @@ -0,0 +1,625 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Derived from ../tqm8xx/flash.c + * [Torsten Stevens, FHG IMS; Bruno Achauer, Exet AG] + */ + +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + DEBUGF ("## Before remap: " + "BR0: 0x%08x OR0: 0x%08x " + "BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0, + memctl->memc_br1, memctl->memc_or1); + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \ + BR_MS_GPCM | BR_PS_32 | BR_V; + + DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size_b0; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + + if (size_b1) { + memctl->memc_or5 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br5 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_PS_32 | BR_V; + + DEBUGF("## BR5: 0x%08x OR5: 0x%08x\n", + memctl->memc_br5, memctl->memc_or5); + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_info[1].size = size_b1; + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[1]); +#endif + } else { + memctl->memc_br5 = 0; /* invalidate bank */ + memctl->memc_or5 = 0; /* invalidate bank */ + + DEBUGF("## DISABLE BR5: 0x%08x OR5: 0x%08x\n", + memctl->memc_br5, memctl->memc_or5); + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + flash_info[1].size = 0; + } + + DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c new file mode 100644 index 0000000..417dbbb --- /dev/null +++ b/board/lantec/lantec.c @@ -0,0 +1,208 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2001 + * Torsten Stevens, FHG IMS, stevens@ims.fhg.de + * Bruno Achauer, Exet AG, bruno@exet-ag.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Derived from ../tqm8xx/tqm8xx.c + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, + 0x1ff77c47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, + 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7ffffc07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Test TQ ID string (TQM8xx...) + * If present, check for "L" type (no second DRAM bank), + * otherwise "L" type is assumed as default. + * + * Return 1 for "L" type, 0 else. + */ + +int checkboard (void) +{ + printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0; + int i; + + /* + * Configure UPMA for SDRAM + */ + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ; + + /* burst length=4, burst type=sequential, CAS latency=2 */ + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + /* initialize memory address register */ + memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */ + + /* mode initialization (offset 5) */ + udelay (200); /* 0x80006105 */ + memctl->memc_mcr = + MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05); + + /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ + udelay (1); /* 0x80006130 */ + memctl->memc_mcr = + MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); + udelay (1); /* 0x80006130 */ + memctl->memc_mcr = + MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); + + udelay (1); /* 0x80006106 */ + memctl->memc_mcr = + MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06); + + memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */ + + udelay (200); + + /* Need at least 10 DRAM accesses to stabilize */ + for (i = 0; i < 10; ++i) { + volatile unsigned long *addr = + (volatile unsigned long *) SDRAM_BASE3_PRELIM; + unsigned long val; + + val = *(addr + i); + *(addr + i) = val; + } + + /* + * Check Bank 0 Memory Size for re-configuration + */ + size_b0 = dram_size (CFG_MAMR_8COL, + (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + + memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE; + + /* + * Final mapping: + */ + + memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + udelay (1000); + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size (base, maxsize)); +} diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds new file mode 100644 index 0000000..29ecabd --- /dev/null +++ b/board/lantec/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug new file mode 100644 index 0000000..65b25b9 --- /dev/null +++ b/board/lantec/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/lart/Makefile b/board/lart/Makefile new file mode 100644 index 0000000..550aa1d --- /dev/null +++ b/board/lart/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := lart.o flash.o +SOBJS := flashasm.o lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/lart/config.mk b/board/lart/config.mk new file mode 100644 index 0000000..3033c4f --- /dev/null +++ b/board/lart/config.mk @@ -0,0 +1,23 @@ +# +# LART board with SA1100 cpu +# +# see http://www.lart.tudelft.nl/ for more information on LART +# + +# +# LART has 4 banks of 8 MB DRAM +# +# c000'0000 +# c100'0000 +# c800'0000 +# c900'0000 +# +# Linux-Kernel is expected to be at c000'8000, entry c000'8000 +# +# we load ourself to c178'0000, the upper 1 MB of second bank +# +# download areas is c800'0000 +# + + +TEXT_BASE = 0xc1780000 diff --git a/board/lart/flash.c b/board/lart/flash.c new file mode 100644 index 0000000..5232ed2 --- /dev/null +++ b/board/lart/flash.c @@ -0,0 +1,474 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +ulong myflush(void); + + +#define FLASH_BANK_SIZE 0x800000 +#define MAIN_SECT_SIZE 0x20000 +#define PARAM_SECT_SIZE 0x4000 + +/* puzzle magic for lart + * data_*_flash are def'd in flashasm.S + */ + +extern u32 data_from_flash(u32); +extern u32 data_to_flash(u32); + +#define PUZZLE_FROM_FLASH(x) data_from_flash((x)) +#define PUZZLE_TO_FLASH(x) data_to_flash((x)) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +#define CMD_READ_ARRAY 0x00FF00FF +#define CMD_IDENTIFY 0x00900090 +#define CMD_ERASE_SETUP 0x00200020 +#define CMD_ERASE_CONFIRM 0x00D000D0 +#define CMD_PROGRAM 0x00400040 +#define CMD_RESUME 0x00D000D0 +#define CMD_SUSPEND 0x00B000B0 +#define CMD_STATUS_READ 0x00700070 +#define CMD_STATUS_RESET 0x00500050 + +#define BIT_BUSY 0x00800080 +#define BIT_ERASE_SUSPEND 0x00400040 +#define BIT_ERASE_ERROR 0x00200020 +#define BIT_PROGRAM_ERROR 0x00100010 +#define BIT_VPP_RANGE_ERROR 0x00080008 +#define BIT_PROGRAM_SUSPEND 0x00040004 +#define BIT_PROTECT_ERROR 0x00020002 +#define BIT_UNDEFINED 0x00010001 + +#define BIT_SEQUENCE_ERROR 0x00300030 +#define BIT_TIMEOUT 0x80000000 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + ulong flashbase = 0; + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F160F3B & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) + { + if (j <= 7) + { + flash_info[i].start[j] = flashbase + j * PARAM_SECT_SIZE; + } + else + { + flash_info[i].start[j] = flashbase + (j - 7)*MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) + { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf("Intel: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) + { + case (INTEL_ID_28F160F3B & FLASH_TYPEMASK): + printf("2x 28F160F3B (16Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto Done; + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) + { + if ((i % 5) == 0) + { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: + ; +} + +/*----------------------------------------------------------------------- + */ + +int flash_error (ulong code) +{ + /* Check bit patterns */ + /* SR.7=0 is busy, SR.7=1 is ready */ + /* all other flags indicate error on 1 */ + /* SR.0 is undefined */ + /* Timeout is our faked flag */ + + /* sequence is described in Intel 290644-005 document */ + + /* check Timeout */ + if (code & BIT_TIMEOUT) + { + printf ("Timeout\n"); + return ERR_TIMOUT; + } + + /* check Busy, SR.7 */ + if (~code & BIT_BUSY) + { + printf ("Busy\n"); + return ERR_PROG_ERROR; + } + + /* check Vpp low, SR.3 */ + if (code & BIT_VPP_RANGE_ERROR) + { + printf ("Vpp range error\n"); + return ERR_PROG_ERROR; + } + + /* check Device Protect Error, SR.1 */ + if (code & BIT_PROTECT_ERROR) + { + printf ("Device protect error\n"); + return ERR_PROG_ERROR; + } + + /* check Command Seq Error, SR.4 & SR.5 */ + if (code & BIT_SEQUENCE_ERROR) + { + printf ("Command seqence error\n"); + return ERR_PROG_ERROR; + } + + /* check Block Erase Error, SR.5 */ + if (code & BIT_ERASE_ERROR) + { + printf ("Block erase error\n"); + return ERR_PROG_ERROR; + } + + /* check Program Error, SR.4 */ + if (code & BIT_PROGRAM_ERROR) + { + printf ("Program error\n"); + return ERR_PROG_ERROR; + } + + /* check Block Erase Suspended, SR.6 */ + if (code & BIT_ERASE_SUSPEND) + { + printf ("Block erase suspended\n"); + return ERR_PROG_ERROR; + } + + /* check Program Suspended, SR.2 */ + if (code & BIT_PROGRAM_SUSPEND) + { + printf ("Program suspended\n"); + return ERR_PROG_ERROR; + } + + /* OK, no error */ + return ERR_OK; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (INTEL_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status(); + icache_disable(); + iflag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) + { + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + if (info->protect[sect] == 0) + { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + + *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET); + *addr = PUZZLE_TO_FLASH(CMD_ERASE_SETUP); + *addr = PUZZLE_TO_FLASH(CMD_ERASE_CONFIRM); + + /* wait until flash is ready */ + do + { + /* check timeout */ + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + { + *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); + result = BIT_TIMEOUT; + break; + } + + result = PUZZLE_FROM_FLASH(*addr); + } while (~result & BIT_BUSY); + + *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY); + + if ((rc = flash_error(result)) != ERR_OK) + goto outahere; + + printf("ok.\n"); + } + else /* it was protected */ + { + printf("protected!\n"); + } + } + + if (ctrlc()) + printf("User Interrupt!\n"); + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked(10000); + + if (iflag) + enable_interrupts(); + + if (cflag) + icache_enable(); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + + /* Check if Flash is (sufficiently) erased + */ + result = PUZZLE_FROM_FLASH(*addr); + if ((result & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status(); + icache_disable(); + iflag = disable_interrupts(); + + *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET); + *addr = PUZZLE_TO_FLASH(CMD_PROGRAM); + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + /* wait until flash is ready */ + do + { + /* check timeout */ + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + { + *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); + result = BIT_TIMEOUT; + break; + } + + result = PUZZLE_FROM_FLASH(*addr); + } while (~result & BIT_BUSY); + + *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY); + + rc = flash_error(result); + + if (iflag) + enable_interrupts(); + + if (cflag) + icache_enable(); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 24); + } + for (; i<4 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = *((vu_long*)src); + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + src += 4; + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + return write_word(info, wp, data); +} diff --git a/board/lart/flashasm.S b/board/lart/flashasm.S new file mode 100644 index 0000000..9021972 --- /dev/null +++ b/board/lart/flashasm.S @@ -0,0 +1,177 @@ +/* + * flashasm.S: flash magic for LART + * + * Copyright (C) 1999 2000 2001 Jan-Derk bakker (J.D.Bakker@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +.text + + +.globl data_to_flash +.globl data_from_flash + /* Subroutine that takes data in r0 and formats it so it will be in */ + /* the correct order for the internal flash */ + /* used for LART only */ +data_to_flash: + mov r1, #0x0 + + tst r0, #0x00000001 + orrne r1, r1, #0x00001000 + tst r0, #0x00000002 + orrne r1, r1, #0x00004000 + tst r0, #0x00000004 + orrne r1, r1, #0x00000800 + tst r0, #0x00000008 + orrne r1, r1, #0x00000200 + tst r0, #0x00000010 + orrne r1, r1, #0x00000001 + tst r0, #0x00000020 + orrne r1, r1, #0x00000004 + tst r0, #0x00000040 + orrne r1, r1, #0x00000080 + tst r0, #0x00000080 + orrne r1, r1, #0x00000020 + + tst r0, #0x00000100 + orrne r1, r1, #0x00002000 + tst r0, #0x00000200 + orrne r1, r1, #0x00008000 + tst r0, #0x00000400 + orrne r1, r1, #0x00000400 + tst r0, #0x00000800 + orrne r1, r1, #0x00000100 + tst r0, #0x00001000 + orrne r1, r1, #0x00000002 + tst r0, #0x00002000 + orrne r1, r1, #0x00000008 + tst r0, #0x00004000 + orrne r1, r1, #0x00000040 + tst r0, #0x00008000 + orrne r1, r1, #0x00000010 + + tst r0, #0x00010000 + orrne r1, r1, #0x00100000 + tst r0, #0x00020000 + orrne r1, r1, #0x00400000 + tst r0, #0x00040000 + orrne r1, r1, #0x00080000 + tst r0, #0x00080000 + orrne r1, r1, #0x00020000 + tst r0, #0x00100000 + orrne r1, r1, #0x01000000 + tst r0, #0x00200000 + orrne r1, r1, #0x04000000 + tst r0, #0x00400000 + orrne r1, r1, #0x80000000 + tst r0, #0x00800000 + orrne r1, r1, #0x20000000 + + tst r0, #0x01000000 + orrne r1, r1, #0x00200000 + tst r0, #0x02000000 + orrne r1, r1, #0x00800000 + tst r0, #0x04000000 + orrne r1, r1, #0x00040000 + tst r0, #0x08000000 + orrne r1, r1, #0x00010000 + tst r0, #0x10000000 + orrne r1, r1, #0x02000000 + tst r0, #0x20000000 + orrne r1, r1, #0x08000000 + tst r0, #0x40000000 + orrne r1, r1, #0x40000000 + tst r0, #0x80000000 + orrne r1, r1, #0x10000000 + + mov r0, r1 + mov pc, lr + + /* Takes data received from the flash, and unshuffles it. */ +data_from_flash: + mov r1, #0x00 + + tst r0, #0x00000001 + orrne r1, r1, #0x00000010 + tst r0, #0x00000002 + orrne r1, r1, #0x00001000 + tst r0, #0x00000004 + orrne r1, r1, #0x00000020 + tst r0, #0x00000008 + orrne r1, r1, #0x00002000 + tst r0, #0x00000010 + orrne r1, r1, #0x00008000 + tst r0, #0x00000020 + orrne r1, r1, #0x00000080 + tst r0, #0x00000040 + orrne r1, r1, #0x00004000 + tst r0, #0x00000080 + orrne r1, r1, #0x00000040 + + tst r0, #0x00000100 + orrne r1, r1, #0x00000800 + tst r0, #0x00000200 + orrne r1, r1, #0x00000008 + tst r0, #0x00000400 + orrne r1, r1, #0x00000400 + tst r0, #0x00000800 + orrne r1, r1, #0x00000004 + tst r0, #0x00001000 + orrne r1, r1, #0x00000001 + tst r0, #0x00002000 + orrne r1, r1, #0x00000100 + tst r0, #0x00004000 + orrne r1, r1, #0x00000002 + tst r0, #0x00008000 + orrne r1, r1, #0x00000200 + + tst r0, #0x00010000 + orrne r1, r1, #0x08000000 + tst r0, #0x00020000 + orrne r1, r1, #0x00080000 + tst r0, #0x00040000 + orrne r1, r1, #0x04000000 + tst r0, #0x00080000 + orrne r1, r1, #0x00040000 + tst r0, #0x00100000 + orrne r1, r1, #0x00010000 + tst r0, #0x00200000 + orrne r1, r1, #0x01000000 + tst r0, #0x00400000 + orrne r1, r1, #0x00020000 + tst r0, #0x00800000 + orrne r1, r1, #0x02000000 + + tst r0, #0x01000000 + orrne r1, r1, #0x00100000 + tst r0, #0x02000000 + orrne r1, r1, #0x10000000 + tst r0, #0x04000000 + orrne r1, r1, #0x00200000 + tst r0, #0x08000000 + orrne r1, r1, #0x20000000 + tst r0, #0x10000000 + orrne r1, r1, #0x80000000 + tst r0, #0x20000000 + orrne r1, r1, #0x00800000 + tst r0, #0x40000000 + orrne r1, r1, #0x40000000 + tst r0, #0x80000000 + orrne r1, r1, #0x00400000 + + mov r0, r1 + mov pc, lr diff --git a/board/lart/lart.c b/board/lart/lart.c new file mode 100644 index 0000000..66b730d --- /dev/null +++ b/board/lart/lart.c @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of LART-Board */ + gd->bd->bi_arch_number = MACH_TYPE_LART; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xc0000100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; + + bd->bi_dram[0].start = PHYS_SDRAM_1; + bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + bd->bi_dram[1].start = PHYS_SDRAM_2; + bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + bd->bi_dram[2].start = PHYS_SDRAM_3; + bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + bd->bi_dram[3].start = PHYS_SDRAM_4; + bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return (0); +} diff --git a/board/lart/lowlevel_init.S b/board/lart/lowlevel_init.S new file mode 100644 index 0000000..db9fd63 --- /dev/null +++ b/board/lart/lowlevel_init.S @@ -0,0 +1,94 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +MEM_BASE: .long 0xa0000000 +MEM_START: .long 0xc0000000 + +#define MDCNFG 0x00 +#define MDCAS0 0x04 +#define MDCAS1 0x08 +#define MDCAS2 0x0c +#define MSC0 0x10 +#define MSC1 0x14 +#define MECR 0x18 + +mdcas0: .long 0xc71c703f +mdcas1: .long 0xffc71c71 +mdcas2: .long 0xffffffff +/* mdcnfg: .long 0x0bb2bcbf */ +mdcnfg: .long 0x0334b22f @ alt +/* mcs0: .long 0xfff8fff8 */ +msc0: .long 0xad8c4888 @ alt +mecr: .long 0x00060006 +/* mecr: .long 0x994a994a @ alt */ + +/* setting up the memory */ + +.globl lowlevel_init +lowlevel_init: + ldr r0, MEM_BASE + + /* Setup the flash memory */ + ldr r1, msc0 + str r1, [r0, #MSC0] + + /* Set up the DRAM */ + + /* MDCAS0 */ + ldr r1, mdcas0 + str r1, [r0, #MDCAS0] + + /* MDCAS1 */ + ldr r1, mdcas1 + str r1, [r0, #MDCAS1] + + /* MDCAS2 */ + ldr r1, mdcas2 + str r1, [r0, #MDCAS2] + + /* MDCNFG */ + ldr r1, mdcnfg + str r1, [r0, #MDCNFG] + + /* Set up PCMCIA space */ + ldr r1, mecr + str r1, [r0, #MECR] + + /* Load something to activate bank */ + ldr r1, MEM_START + +.rept 8 + ldr r0, [r1] +.endr + + /* everything is fine now */ + mov pc, lr diff --git a/board/lart/u-boot.lds b/board/lart/u-boot.lds new file mode 100644 index 0000000..258bece --- /dev/null +++ b/board/lart/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/logodl/Makefile b/board/logodl/Makefile new file mode 100644 index 0000000..c7cde7d --- /dev/null +++ b/board/logodl/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := logodl.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/logodl/config.mk b/board/logodl/config.mk new file mode 100644 index 0000000..76c382d --- /dev/null +++ b/board/logodl/config.mk @@ -0,0 +1,15 @@ +# +# Linux-Kernel is expected to be at c000'8000, entry c000'8000 +# +# we load ourself to c170'0000, the upper 1 MB of second bank +# +# download areas is c800'0000 +# + +#TEXT_BASE = 0 + +# FIXME: armboot does only work correctly when being compiled +# # for the addresses _after_ relocation to RAM!! Otherwhise the +# # .bss segment is assumed in flash... +# +TEXT_BASE = 0x083E0000 diff --git a/board/logodl/flash.c b/board/logodl/flash.c new file mode 100644 index 0000000..a947731 --- /dev/null +++ b/board/logodl/flash.c @@ -0,0 +1,829 @@ +/* + * (C) 2000 Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) 2003 August Hoeraendl, Logotronic GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#undef CONFIG_FLASH_16BIT + +#include + +#define FLASH_BANK_SIZE 0x1000000 +#define MAIN_SECT_SIZE 0x20000 /* 2x64k = 128k per sector */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; + +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +#define write_word(in, de, da) write_word_amd(in, de, da) +static void flash_get_offsets(ulong base, flash_info_t *info); +#ifdef CFG_FLASH_PROTECTION +static void flash_sync_real_protect(flash_info_t *info); +#endif + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + ulong flashbase = 0; + flash_info[i].flash_id = + (FLASH_MAN_AMD & FLASH_VENDMASK) | + (FLASH_AM640U & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) + { + case 0: + flashbase = PHYS_FLASH_1; + break; + case 1: + flashbase = PHYS_FLASH_2; + break; + default: + panic("configured too many flash banks!\n"); + break; + } + for (j = 0; j < flash_info[i].sector_count; j++) + { + flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + _bss_start - _armboot_start, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL + && (info->flash_id & FLASH_BTYPE)) { + int bootsect_size; /* number of bytes/boot sector */ + int sect_size; /* number of bytes/regular sector */ + + bootsect_size = 0x00002000 * (sizeof(FPW)/2); + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < 8; ++i) { + info->start[i] = base + (i * bootsect_size); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i - 7) * sect_size); + } + } + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set up sector start address table (uniform sector type) */ + for( i = 0; i < info->sector_count; i++ ) + info->start[i] = base + (i * sect_size); + } +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + uchar *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM640U: + fmt = "29LV641D (64 Mbit, uniform sectors)\n"; + break; + case FLASH_28F800C3B: + case FLASH_28F800C3T: + fmt = "28F800C3%s (8 Mbit, %s)\n"; + break; + case FLASH_INTEL800B: + case FLASH_INTEL800T: + fmt = "28F800B3%s (8 Mbit, %s)\n"; + break; + case FLASH_28F160C3B: + case FLASH_28F160C3T: + fmt = "28F160C3%s (16 Mbit, %s)\n"; + break; + case FLASH_INTEL160B: + case FLASH_INTEL160T: + fmt = "28F160B3%s (16 Mbit, %s)\n"; + break; + case FLASH_28F320C3B: + case FLASH_28F320C3T: + fmt = "28F320C3%s (32 Mbit, %s)\n"; + break; + case FLASH_INTEL320B: + case FLASH_INTEL320T: + fmt = "28F320B3%s (32 Mbit, %s)\n"; + break; + case FLASH_28F640C3B: + case FLASH_28F640C3T: + fmt = "28F640C3%s (64 Mbit, %s)\n"; + break; + case FLASH_INTEL640B: + case FLASH_INTEL640T: + fmt = "28F640B3%s (64 Mbit, %s)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + /* Write auto select command: read Manufacturer ID */ + + /* Write auto select command sequence and test FLASH answer */ + addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + switch (addr[0] & 0xff) { + + case (uchar)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { + + case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F800C3B: + info->flash_id += FLASH_28F800C3B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F800B3B: + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F160B3B: + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F320B3B: + info->flash_id += FLASH_INTEL320B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F640B3B: + info->flash_id += FLASH_INTEL640B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets((ulong)addr, info); + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ + +static void flash_sync_real_protect(flash_info_t *info) +{ + FPWV *addr = (FPWV *)(info->start[0]); + FPWV *sect; + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F800C3B: + case FLASH_28F800C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + /* check for protected sectors */ + *addr = (FPW)0x00900090; + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but mixed protected and unprotected devices + * within a sector should never happen. + */ + sect = (FPWV *)(info->start[i]); + info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0; + } + + /* Put FLASH back in read mode */ + flash_reset(info); + break; + + case FLASH_AM640U: + default: + /* no hardware protect that we support */ + break; + } +} +#endif + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_INTEL800B: + case FLASH_INTEL160B: + case FLASH_INTEL320B: + case FLASH_INTEL640B: + case FLASH_28F800C3B: + case FLASH_28F160C3B: + case FLASH_28F320C3B: + case FLASH_28F640C3B: + case FLASH_AM640U: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer(0); + last = start; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + if (intel) { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[0x0555] = (FPW)0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW)0x00550055; /* unlock */ + base[0x0555] = (FPW)0x00800080; /* erase mode */ + base[0x0555] = (FPW)0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW)0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + case FLASH_MAN_INTEL: + res = write_word_intel(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/** + * write_buf: - Copy memory to flash. + * + * @param info: + * @param src: source of copy transaction + * @param addr: where to copy to + * @param cnt: number of bytes to copy + * + * @return error code + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int l; + int i, rc; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 8); + } + for (; i<2 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt==0 && i<2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 8); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + /* data = *((vushort*)src); */ + data = *((FPW*)src); + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + src += sizeof(FPW); + wp += sizeof(FPW); + cnt -= sizeof(FPW); + } + + if (cnt == 0) return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i<2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 8); + } + + return write_word(info, wp, data); +} + + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *)(info->start[0]); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[0x0555] = (FPW)0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW)0x00550055; /* unlock */ + base[0x0555] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for Intel FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + *dest = (FPW)0x00400040; /* program setup */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00B000B0; /* Suspend program */ + res = 1; + } + } + + if (res == 0 && (*dest & (FPW)0x00100010)) + res = 1; /* write failed, time out error is close enough */ + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + + return (res); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F800C3B: + case FLASH_28F800C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + flash_reset (info); /* make sure in read mode */ + *addr = (FPW) 0x00600060L; /* lock command setup */ + if (prot) + *addr = (FPW) 0x00010001L; /* lock sector */ + else + *addr = (FPW) 0x00D000D0L; /* unlock sector */ + flash_reset (info); /* reset to read mode */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) 0x00900090; + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) 0x00010001; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) 0x00010001) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect (info); + break; + + case FLASH_AM640U: + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c new file mode 100644 index 0000000..95634ac --- /dev/null +++ b/board/logodl/logodl.c @@ -0,0 +1,123 @@ +/* + * (C) 2002 Kyle Harris , Nexus Technologies, Inc. + * (C) 2002 Marius Groeger , Sysgo GmbH + * (C) 2003 Robert Schwebel , Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/** + * board_init: - setup some data structures + * + * @return: 0 in case of success + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + gd->bd->bi_arch_number = MACH_TYPE_LOGODL; + gd->bd->bi_boot_params = 0x08000100; + gd->bd->bi_baudrate = CONFIG_BAUDRATE; + + (*((volatile short*)0x14800000)) = 0xff; /* power on eth0 */ + (*((volatile short*)0x14000000)) = 0xff; /* power on uart */ + + return 0; +} + + +/** + * dram_init: - setup dynamic RAM + * + * @return: 0 in case of success + */ + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + + +/** + * logodl_set_led: - switch LEDs on or off + * + * @param led: LED to switch (0,1) + * @param state: switch on (1) or off (0) + */ + +void logodl_set_led(int led, int state) +{ + switch(led) { + + case 0: + if (state==1) { + CFG_LED_A_CR = CFG_LED_A_BIT; + } else if (state==0) { + CFG_LED_A_SR = CFG_LED_A_BIT; + } + break; + + case 1: + if (state==1) { + CFG_LED_B_CR = CFG_LED_B_BIT; + } else if (state==0) { + CFG_LED_B_SR = CFG_LED_B_BIT; + } + break; + } + + return; +} + + +/** + * show_boot_progress: - indicate state of the boot process + * + * @param status: Status number - see README for details. + * + * The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most + * important states (1, 5, 15). + */ + +void show_boot_progress (int status) +{ + /* + switch(status) { + case 1: logodl_set_led(0,1); break; + case 5: logodl_set_led(1,1); break; + case 15: logodl_set_led(2,1); break; + } + */ + logodl_set_led(0, (status & 1)==1); + logodl_set_led(1, (status & 2)==2); + + return; +} diff --git a/board/logodl/lowlevel_init.S b/board/logodl/lowlevel_init.S new file mode 100644 index 0000000..aa9dcba --- /dev/null +++ b/board/logodl/lowlevel_init.S @@ -0,0 +1,437 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + +_TEXT_BASE: + .word TEXT_BASE + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + +/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ +/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ +/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ +/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ +/* */ +/* ldr r1, =LED_BLANK */ +/* mov r0, #0xFF */ +/* str r0, [r1] / turn on hex leds */ +/* */ +/*loop: */ +/* */ +/* ldr r0, =0xB0070001 */ +/* ldr r1, =_LED */ +/* str r0, [r1] / hex display */ + + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ + adr r3, mem_init /* r0 <- current position of code */ + ldr r2, =mem_init + cmp r3, r2 /* skip init if in place */ + beq initirqs + + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + /* Step 4a: assert MDREFR:K?RUN and configure */ + /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ + + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4b: de-assert MDREFR:SLFRSH. */ + + bic r4, r4, #(MDREFR_SLFRSH) + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4c: assert MDREFR:E1PIN and E0PIO */ + + orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + /* There should 9 writes, since the first write doesn't */ + /* trigger a refresh cycle on PXA250. See Intel PXA250 and */ + /* PXA210 Processors Specification Update, */ + /* Jan 2003, Errata #116, page 30. */ + + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + + /* We are finished with Intel's memory controller initialisation */ + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + /* (hard-coding at 398.12MHz for now). */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + + /* default value in case no valid rotary switch setting is found */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + + /* enable the 32Khz oscillator for RTC and PowerManager */ +/* + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] +*/ + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size */ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + + /* FIXME */ + +#ifndef DEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/logodl/u-boot.lds b/board/logodl/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/logodl/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/lpd7a40x/Makefile b/board/lpd7a40x/Makefile new file mode 100644 index 0000000..ebe14df --- /dev/null +++ b/board/lpd7a40x/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := lpd7a40x.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/lpd7a40x/config.mk b/board/lpd7a40x/config.mk new file mode 100644 index 0000000..bc03874 --- /dev/null +++ b/board/lpd7a40x/config.mk @@ -0,0 +1,38 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Logic ZOOM LH7A400 SDK board w/Logic LH7A400-10 card engine +# w/Sharp LH7A400 SoC (ARM920T) cpu +# + +# +# 32 or 64 MB SDRAM on SDCSC0 @ 0xc0000000 +# +# Linux-Kernel is @ 0xC0008000, entry 0xc0008000 +# params @ 0xc0000100 +# optionally with a ramdisk at 0xc0300000 +# +# we load ourself to 0xc1fc0000 (32M - 256K) +# +# download area is 0xc0f00000 +# + +TEXT_BASE = 0xc1fc0000 +#TEXT_BASE = 0x00000000 diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c new file mode 100644 index 0000000..2dfe376 --- /dev/null +++ b/board/lpd7a40x/flash.c @@ -0,0 +1,489 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include + +#define FLASH_BANK_SIZE 0x1000000 /* 16MB (2 x 8 MB) */ +#define MAIN_SECT_SIZE 0x40000 /* 256KB (2 x 128kB) */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +#define CMD_READ_ARRAY 0x00FF00FF +#define CMD_IDENTIFY 0x00900090 +#define CMD_ERASE_SETUP 0x00200020 +#define CMD_ERASE_CONFIRM 0x00D000D0 +#define CMD_PROGRAM 0x00400040 +#define CMD_RESUME 0x00D000D0 +#define CMD_SUSPEND 0x00B000B0 +#define CMD_STATUS_READ 0x00700070 +#define CMD_STATUS_RESET 0x00500050 + +#define BIT_BUSY 0x00800080 +#define BIT_ERASE_SUSPEND 0x00400040 +#define BIT_ERASE_ERROR 0x00200020 +#define BIT_PROGRAM_ERROR 0x00100010 +#define BIT_VPP_RANGE_ERROR 0x00080008 +#define BIT_PROGRAM_SUSPEND 0x00040004 +#define BIT_PROTECT_ERROR 0x00020002 +#define BIT_UNDEFINED 0x00010001 + +#define BIT_SEQUENCE_ERROR 0x00300030 +#define BIT_TIMEOUT 0x80000000 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F640J3A & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = CFG_FLASH_BASE; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase; + + /* uniform sector size */ + flashbase += MAIN_SECT_SIZE; + } + size += flash_info[i].size; + } + + /* + * Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): + printf ("2x 28F640J3A (64Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + return; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +int flash_error (ulong code) +{ + /* Check bit patterns */ + /* SR.7=0 is busy, SR.7=1 is ready */ + /* all other flags indicate error on 1 */ + /* SR.0 is undefined */ + /* Timeout is our faked flag */ + + /* sequence is described in Intel 290644-005 document */ + + /* check Timeout */ + if (code & BIT_TIMEOUT) { + puts ("Timeout\n"); + return ERR_TIMOUT; + } + + /* check Busy, SR.7 */ + if (~code & BIT_BUSY) { + puts ("Busy\n"); + return ERR_PROG_ERROR; + } + + /* check Vpp low, SR.3 */ + if (code & BIT_VPP_RANGE_ERROR) { + puts ("Vpp range error\n"); + return ERR_PROG_ERROR; + } + + /* check Device Protect Error, SR.1 */ + if (code & BIT_PROTECT_ERROR) { + puts ("Device protect error\n"); + return ERR_PROG_ERROR; + } + + /* check Command Seq Error, SR.4 & SR.5 */ + if (code & BIT_SEQUENCE_ERROR) { + puts ("Command seqence error\n"); + return ERR_PROG_ERROR; + } + + /* check Block Erase Error, SR.5 */ + if (code & BIT_ERASE_ERROR) { + puts ("Block erase error\n"); + return ERR_PROG_ERROR; + } + + /* check Program Error, SR.4 */ + if (code & BIT_PROGRAM_ERROR) { + puts ("Program error\n"); + return ERR_PROG_ERROR; + } + + /* check Block Erase Suspended, SR.6 */ + if (code & BIT_ERASE_SUSPEND) { + puts ("Block erase suspended\n"); + return ERR_PROG_ERROR; + } + + /* check Program Suspended, SR.2 */ + if (code & BIT_PROGRAM_SUSPEND) { + puts ("Program suspended\n"); + return ERR_PROG_ERROR; + } + + /* OK, no error */ + return ERR_OK; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result, result1; + int iflag, prot, sect; + int rc = ERR_OK; + +#ifdef USE_920T_MMU + int cflag; +#endif + + debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (INTEL_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ +#ifdef USE_920T_MMU + cflag = dcache_status (); + dcache_disable (); +#endif + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + + debug ("Erasing sector %2d @ %08lX... ", + sect, info->start[sect]); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *) (info->start[sect]); + ulong bsR7, bsR7_2, bsR5, bsR5_2; + + /* *addr = CMD_STATUS_RESET; */ + *addr = CMD_ERASE_SETUP; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + do { + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + *addr = CMD_STATUS_RESET; + result = BIT_TIMEOUT; + break; + } + + *addr = CMD_STATUS_READ; + result = *addr; + bsR7 = result & (1 << 7); + bsR7_2 = result & (1 << 23); + } while (!bsR7 | !bsR7_2); + + *addr = CMD_STATUS_READ; + result1 = *addr; + bsR5 = result1 & (1 << 5); + bsR5_2 = result1 & (1 << 21); +#ifdef SAMSUNG_FLASH_DEBUG + printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); + if (bsR5 != 0 && bsR5_2 != 0) + printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); +#endif + + *addr = CMD_READ_ARRAY; + *addr = CMD_RESUME; + + if ((rc = flash_error (result)) != ERR_OK) + goto outahere; +#if 0 + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); +#endif + } + } + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + +#ifdef USE_920T_MMU + if (cflag) + dcache_enable (); +#endif + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_word (flash_info_t * info, ulong dest, + ulong data) +{ + vu_long *addr = (vu_long *) dest; + ulong result; + int rc = ERR_OK; + int iflag; + +#ifdef USE_920T_MMU + int cflag; +#endif + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ +#ifdef USE_920T_MMU + cflag = dcache_status (); + dcache_disable (); +#endif + iflag = disable_interrupts (); + + /* *addr = CMD_STATUS_RESET; */ + *addr = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + do { + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + *addr = CMD_SUSPEND; + result = BIT_TIMEOUT; + break; + } + + *addr = CMD_STATUS_READ; + result = *addr; + } while (~result & BIT_BUSY); + + /* *addr = CMD_READ_ARRAY; */ + *addr = CMD_STATUS_READ; + result = *addr; + + rc = flash_error (result); + + if (iflag) + enable_interrupts (); + +#ifdef USE_920T_MMU + if (cflag) + dcache_enable (); +#endif + *addr = CMD_READ_ARRAY; + *addr = CMD_RESUME; + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = *((vu_long *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 4; + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + + return write_word (info, wp, data); +} diff --git a/board/lpd7a40x/lowlevel_init.S b/board/lpd7a40x/lowlevel_init.S new file mode 100644 index 0000000..b3ed55c --- /dev/null +++ b/board/lpd7a40x/lowlevel_init.S @@ -0,0 +1,212 @@ +/* + * Memory Setup - initialize memory controller(s) for devices required + * to boot and relocate + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* memory controller */ +#define BCRX_DEFAULT (0x0000fbe0) +#define BCRX_MW_8 (0x00000000) +#define BCRX_MW_16 (0x10000000) +#define BCRX_MW_32 (0x20000000) +#define BCRX_PME (0x08000000) +#define BCRX_WP (0x04000000) +#define BCRX_WST2_SHIFT (11) +#define BCRX_WST1_SHIFT (5) +#define BCRX_IDCY_SHIFT (0) + +/* Bank0 Async Flash */ +#define BCR0 (0x80002000) +#define BCR0_FLASH (BCRX_MW_32 | (0x08< + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_LH7A400) +#include +#elif defined(CONFIG_LH7A404) +#include +#else +#error "No CPU defined!" +#endif +#include + +#include + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* set up the I/O ports */ + + /* enable flash programming */ + *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_FLASH_REG)) |= FLASH_FPEN; + + /* Auto wakeup, LCD disable, WLAN enable */ + *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_CECTL_REG)) &= + ~(CECTL_AWKP|CECTL_LCDV|CECTL_WLPE); + + /* Status LED 2 on (leds are active low) */ + *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_EXTGPIO_REG)) = + (EXTGPIO_STATUS1|EXTGPIO_GPIO1) & ~(EXTGPIO_STATUS2); + +#if defined(CONFIG_LH7A400) + /* arch number of Logic-Board - MACH_TYPE_LPD7A400 */ + gd->bd->bi_arch_number = MACH_TYPE_LPD7A400; +#elif defined(CONFIG_LH7A404) + /* arch number of Logic-Board - MACH_TYPE_LPD7A400 */ + gd->bd->bi_arch_number = MACH_TYPE_LPD7A404; +#endif + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xc0000100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/board/lpd7a40x/u-boot.lds b/board/lpd7a40x/u-boot.lds new file mode 100644 index 0000000..156b871 --- /dev/null +++ b/board/lpd7a40x/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/lh7a40x/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile new file mode 100644 index 0000000..106622c --- /dev/null +++ b/board/lubbock/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := lubbock.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/lubbock/config.mk b/board/lubbock/config.mk new file mode 100644 index 0000000..55c8b27 --- /dev/null +++ b/board/lubbock/config.mk @@ -0,0 +1,3 @@ +#TEXT_BASE = 0xa1700000 +TEXT_BASE = 0xa3080000 +#TEXT_BASE = 0 diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c new file mode 100644 index 0000000..ba82892 --- /dev/null +++ b/board/lubbock/flash.c @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0] ); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S new file mode 100644 index 0000000..15276e8 --- /dev/null +++ b/board/lubbock/lowlevel_init.S @@ -0,0 +1,411 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + /* set MDREFR according to user define with exception of a few bits */ + + ldr r4, =CFG_MDREFR_VAL + orr r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4b: de-assert MDREFR:SLFRSH. */ + + bic r4, r4, #(MDREFR_SLFRSH) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ + + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + + /* We are finished with Intel's memory controller initialisation */ + + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + /* (hard-coding at 398.12MHz for now). */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + + /* default value in case no valid rotary switch setting is found */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size */ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + + /* FIXME */ + +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c new file mode 100644 index 0000000..e618ab9 --- /dev/null +++ b/board/lubbock/lubbock.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board */ + gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/lubbock/u-boot.lds b/board/lubbock/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/lubbock/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/lwmon/Makefile b/board/lwmon/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/lwmon/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/lwmon/README.keybd b/board/lwmon/README.keybd new file mode 100644 index 0000000..54f0aeb --- /dev/null +++ b/board/lwmon/README.keybd @@ -0,0 +1,126 @@ + +Tastaturabfrage: + +Die Implementierung / Decodierung beruht auf den Angaben aus dem Do- +kument "PIC LWE-Tastatur" in der Fassung vom 9. 3. 2001, insbesonde- +re Tabelle 3 im Kapitel 4.3 Tastencodes. In U-Boot werden die vom +Keyboard-Controller gelesenen Daten hexadezimal codiert in der auto- +matisch angelegten Environment-Variablen "keybd" übergeben. Ist kei- +ne Taste gedrückt worden, steht dort: + + keybd=000000000000000000 + +Der decodierte Tastencode ("keybd") kann mit den "bootargs" an den +Linux-Kernel übergeben und dort z. B. in einem Device-Treiber oder +einer Applikation ausgewertet werden. + + +Sonderfunktionen beim Booten: + +Es lassen sich eine oder mehrere (beliebig viele) Tasten oder Tasten- +kombinationen definieren, die Sonderfunktionen auslösen, wenn diese +Tasten beim Booten (Reset) gedrückt sind. + +Wird eine eingestellte Taste bzw. Tastenkombination erkannt, so wird +in U-Boot noch vor dem Start des "Countdown" und somit vor jedem an- +deren Kommando der Inhalt einer dieser Taste bzw. Tastenkombination +zugeordneten Environment-Variablen ausführen. + + +Die Environment-Variable "magic_keys" wird als Liste von Zeichen ver- +standen, die als Suffix an den Namen "key_magic" angefügt werden und +so die Namen der Environment-Variablen definieren, mit denen die +Tasten (-kombinationen) festgelegt werden: + +Ist "magic_keys" NICHT definiert, so wird nur die in der Environment- +Variablen "key_magic" codierte Tasten (-kombination) geprüft, und +ggf. der Inhalt der Environment-Variablen "key_cmd" ausgeführt (ge- +nauer: der Inhalt von "key_cmd" wird der Variablen "preboot" zugewie- +sen, die ausgeführt wird, unmittelbar bevor die interaktive Kommando- +interpretation beginnt). + +Enthält "magic_keys" z. B. die Zeichenkette "0123CB*", so werden +nacheinander folgende Aktionen ausgeführt: + + prüfe Tastencode ggf. führe aus Kommando + in Variable in Variable + ----------------------------------- + key_magic0 ==> key_cmd0 + key_magic1 ==> key_cmd1 + key_magic2 ==> key_cmd2 + key_magic3 ==> key_cmd3 + key_magicC ==> key_cmdC + key_magicB ==> key_cmdB + key_magicA ==> key_cmdA + key_magic* ==> key_cmd* + +Hinweis: sobald ein aktivierter Tastencode erkannt wurde, wird die +Bearbeitung abgebrochen; es wird daher höchstens eines der definier- +ten Kommandos ausgeführt, wobei die Priorität durch die Suchreihen- +folge festgelegt wird, also durch die Reihenfolge der Zeichen in der +Varuiablen "magic_keys". + + +Die Codierung der Tasten, die beim Booten gedrückt werden müssen, um +eine Funktion auszulösen, erfolgt nach der Tastaturtabelle. + +Die Definitionen + + => setenv key_magic0 3a+3b + => setenv key_cmd0 setenv bootdelay 30 + +bedeuten dementsprechend, daß die Tasten mit den Codes 0x3A (Taste +"F1") und 0x3B (Taste "F2") gleichzeitig gedrückt werden müssen. Sie +können dort eine beliebige Tastenkombination eintragen (jeweils 2 +Zeichen für die Hex-Codes der Tasten, und '+' als Trennzeichen). + +Wird die eingestellte Tastenkombination erkannt, so wird in U-Boot +noch vor dem Start des "Countdown" und somit vor jedem anderen Kom- +mando das angebene Kommando ausgeführt und somit ein langes Boot- +Delay eingetragen. + +Praktisch könnten Sie also in U-Boot "bootdelay" auf 0 setzen und +somit stets ohne jede User-Interaktion automatisch booten, außer, +wenn die beiden Tasten "F1" und "F2" beim Booten gedrückt werden: +dann würde ein Boot-Delay von 30 Sekunden eingefügt. + + +Hinweis: dem Zeichen '#' kommt innerhalb von "magic_keys" eine beson- +dere Bedeutung zu: die dadurch definierte Key-Sequenz schaltet den +Monitor in den "Debug-Modus" - das bedeutet zunächst, daß alle weite- +ren Meldungen von U-Boot über das LCD-Display ausgegeben werden; +außerdem kann man durch das mit dieser Tastenkombination verknüpfte +Kommando z. B. die Linux-Bootmeldungen ebenfalls auf das LCD-Display +legen, so daß der Boot-Vorgang direkt und ohne weitere Hilfsmittel +analysiert werden kann. + +Beispiel: + +In U-Boot werden folgende Environment-Variablen gesetzt und abgespei- +chert: + +(1) => setenv magic_keys 01234#X +(2) => setenv key_cmd# setenv addfb setenv bootargs \\${bootargs} console=tty0 console=ttyS1,\\${baudrate} +(3) => setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\${serverip}:\${rootpath} +(4) => setenv addip setenv bootargs \${bootargs} ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off panic=1 +(5) => setenv addfb setenv bootargs \${bootargs} console=ttyS1,\${baudrate} +(6) => setenv bootcmd bootp\;run nfsargs\;run addip\;run addfb\;bootm + +Hierbei wird die Linux Commandline (in der Variablen "bootargs") im +Boot-Kommando "bootcmd" (6) schrittweise zusammengesetzt: zunächst +werden die für Root-Filesystem über NFS erforderlichen Optionen ge- +setzt ("run nfsargs", vgl. (3)), dann die Netzwerkkonfiguration an- +gefügt ("run addip", vgl. (4)), und schließlich die Systemconsole +definiert ("run addfb"). + +Dabei wird im Normalfall die Definition (5) verwendt; wurde aller- +dings beim Reset die entsprechende Taste gedrückt gehalten, so wird +diese Definition bei der Ausführung des in (2) definierten Kommandos +überschrieben, so daß Linux die Bootmeldungen auch über das Frame- +buffer-Device (=LCD-Display) ausgibt. + +Beachten Sie die Verdoppelung der '\'-Escapes in der Definition von +"key_cmd#" - diese ist erforderlich, weil der String _zweimal_ inter- +pretiert wird: das erste Mal bei der Eingabe von "key_cmd#", das +zweite Mal, wenn der String (als Inhalt von "preboot") ausgeführt +wird. diff --git a/board/lwmon/config.mk b/board/lwmon/config.mk new file mode 100644 index 0000000..dfa952a --- /dev/null +++ b/board/lwmon/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# LWE Monitorcontroller Litronic LCD IV boards +# + +TEXT_BASE = 0x40000000 +#TEXT_BASE = 0x41000000 diff --git a/board/lwmon/flash.c b/board/lwmon/flash.c new file mode 100644 index 0000000..b894887 --- /dev/null +++ b/board/lwmon/flash.c @@ -0,0 +1,648 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*---------------------------------------------------------------------*/ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, ulong data); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + debug ("## Before remap: " + "BR0: 0x%08x OR0: 0x%08x " + "BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0, + memctl->memc_br1, memctl->memc_or1); + + /* Remap FLASH according to real size */ + memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CFG_OR_TIMING_FLASH | + OR_CSNT_SAM | OR_ACS_DIV1; + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V; + + debug ("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size_b0; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + + if (size_b1) { + memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CFG_OR_TIMING_FLASH | + OR_CSNT_SAM | OR_ACS_DIV1; + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_PS_32 | BR_V; + + debug ("## BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_info[1].size = size_b1; + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[1]); +#endif + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + memctl->memc_or1 = 0; /* invalidate bank */ + + debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + flash_info[1].size = 0; + } + + debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x00020000 * 2; /* 128k * 2 chips per bank */ + } + return; + + default: + printf ("Don't know sector ofsets for flash type 0x%lx\n", + info->flash_id); + return; + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("Fujitsu "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_MT: printf ("MT "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n"); + break; + case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n"); + break; + case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >= (1 << 20)) { + i = 20; + } else { + i = 10; + } + printf (" Size: %ld %cB in %d Sectors\n", + info->size >> i, + (i == 20) ? 'M' : 'k', + info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + ulong value; + + /* Read Manufacturer ID */ + addr[0] = 0x00900090; + value = addr[0]; + + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + case INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value) { + case INTEL_ID_28F320J3A: + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000 * 2; + break; /* => 8 MB */ + + case INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000 * 2; + break; /* => 16 MB */ + + case INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000 * 2; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + addr[0] = 0x00FF00FF; /* restore read mode */ + return (0); /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + unsigned long status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = 0x00600060; /* clear lock bit setup */ + *addr = 0x00D000D0; /* clear lock bit confirm */ + + udelay (1000); + /* This takes awfully long - up to 50 ms and more */ + while (((status = *addr) & 0x00800080) != 0x00800080) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0x00FF00FF; /* reset to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + udelay (1000); /* to trigger the watchdog */ + } + + *addr = 0x00500050; /* clear status register */ + *addr = 0x00200020; /* erase setup */ + *addr = 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & 0x00800080) != 0x00800080) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0x00B000B0; /* suspend erase */ + *addr = 0x00FF00FF; /* reset to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + udelay (1000); /* to trigger the watchdog */ + } + + *addr = 0x00FF00FF; /* reset to read mode */ + } + } + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 4 /* flash bus width in bytes */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= FLASH_WIDTH) { + i = CFG_FLASH_BUFFER_SIZE > cnt ? + (cnt & ~(FLASH_WIDTH - 1)) : CFG_FLASH_BUFFER_SIZE; + if((rc = write_data_buf(info, wp, src,i)) != 0) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + while (cnt >= FLASH_WIDTH) { + data = 0; + for (i=0; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i tout) { + printf("Flash %s timeout at address %p\n", prompt, addr); + *addr = 0x00FF00FF; /* restore read mode */ + return (1); + } + } + return 0; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = 0x00400040; /* write setup */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + if (flash_status_check(addr, CFG_FLASH_WRITE_TOUT, "write") != 0) { + return (1); + } + + *addr = 0x00FF00FF; /* restore read mode */ + + return (0); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE +/*----------------------------------------------------------------------- + * Write a buffer to Flash, returns: + * 0 - OK + * 1 - write timeout + */ +static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + vu_long *addr = (vu_long *)dest; + int sector; + int cnt; + int retcode; + vu_long * src = (vu_long *)cp; + vu_long * dst = (vu_long *)dest; + + /* find sector */ + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(dest >= info->start[sector]) + break; + } + + *addr = 0x00500050; /* clear status */ + *addr = 0x00e800e8; /* write buffer */ + + if((retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT, + "write to buffer")) == 0) { + cnt = len / FLASH_WIDTH; + *addr = (cnt-1) | ((cnt-1) << 16); + while(cnt-- > 0) { + *dst++ = *src++; + } + *addr = 0x00d000d0; /* write buffer confirm */ + retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT, + "buffer write"); + } + *addr = 0x00FF00FF; /* restore read mode */ + *addr = 0x00500050; /* clear status */ + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ + +/*----------------------------------------------------------------------- + */ diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c new file mode 100644 index 0000000..a174b57 --- /dev/null +++ b/board/lwmon/lwmon.c @@ -0,0 +1,1068 @@ +/*********************************************************************** + * +M* Modul: lwmon.c +M* +M* Content: LWMON specific U-Boot commands. + * + * (C) Copyright 2001, 2002 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * All rights reserved. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + ***********************************************************************/ + +/*---------------------------- Headerfiles ----------------------------*/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include /* for strdup */ + +/*------------------------ Local prototypes ---------------------------*/ +static long int dram_size (long int, long int *, long int); +static void kbd_init (void); +static int compare_magic (uchar *kbd_data, uchar *str); + + +/*--------------------- Local macros and constants --------------------*/ +#define _NOT_USED_ 0xFFFFFFFF + +#ifdef CONFIG_MODEM_SUPPORT +static int key_pressed(void); +extern void disable_putc(void); +#endif /* CONFIG_MODEM_SUPPORT */ + +/* + * 66 MHz SDRAM access using UPM A + */ +const uint sdram_table[] = +{ +#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E) + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, + 0x1FF5FC47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPM RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7FFFFC07, /* last */ + 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF, +#endif +#ifdef CFG_MEMORY_7E + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */ + _NOT_USED_, + /* + * SDRAM Initialization (offset 5 in UPM RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + 0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00, + 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + 0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00, + 0xE1BAFC04, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7FFFFC07, /* last */ + 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF, +#endif +}; + +/* + * Check Board Identity: + * + */ + +/*********************************************************************** +F* Function: int checkboard (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int - 0 is always returned + * +Z* Intention: This function is the checkboard() method implementation +Z* for the lwmon board. Only a standard message is printed. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int checkboard (void) +{ + puts ("Board: LICCON Konsole LCD3\n"); + return (0); +} + +/*********************************************************************** +F* Function: long int initdram (int board_type) P*A*Z* + * +P* Parameters: int board_type +P* - Usually type of the board - ignored here. +P* +P* Returnvalue: long int +P* - Size of initialized memory + * +Z* Intention: This function is the initdram() method implementation +Z* for the lwmon board. +Z* The memory controller is initialized to access the +Z* DRAM. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +long int initdram (int board_type) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + long int size_b0; + long int size8, size9; + int i; + + /* + * Configure UPMA for SDRAM + */ + upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + memctl->memc_mptpr = CFG_MPTPR; + + /* burst length=4, burst type=sequential, CAS latency=2 */ + memctl->memc_mar = CFG_MAR; + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + /* initialize memory address register */ + memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */ + + /* mode initialization (offset 5) */ + udelay (200); /* 0x80006105 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05); + + /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ + udelay (1); /* 0x80006130 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); + udelay (1); /* 0x80006130 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); + + udelay (1); /* 0x80006106 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06); + + memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */ + + udelay (200); + + /* Need at least 10 DRAM accesses to stabilize */ + for (i = 0; i < 10; ++i) { + volatile unsigned long *addr = + (volatile unsigned long *) SDRAM_BASE3_PRELIM; + unsigned long val; + + val = *(addr + i); + *(addr + i) = val; + } + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size_b0 = size9; + memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE; + udelay (500); + } else { /* back to 8 columns */ + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE; + udelay (500); + } + + /* + * Final mapping: + */ + + memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | + OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; + memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + udelay (1000); + + return (size_b0); +} + +/*********************************************************************** +F* Function: static long int dram_size (long int mamr_value, +F* long int *base, +F* long int maxsize) P*A*Z* + * +P* Parameters: long int mamr_value +P* - Value for MAMR for the test +P* long int *base +P* - Base address for the test +P* long int maxsize +P* - Maximum size to test for +P* +P* Returnvalue: long int +P* - Size of probed memory + * +Z* Intention: Check memory range for valid RAM. A simple memory test +Z* determines the actually available RAM size between +Z* addresses `base' and `base + maxsize'. Some (not all) +Z* hardware errors are detected: +Z* - short between address lines +Z* - short between data lines + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +#ifndef PB_ENET_TENA +# define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ +#endif + +/*********************************************************************** +F* Function: int board_early_init_f (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: This function is the board_early_init_f() method implementation +Z* for the lwmon board. +Z* Disable Ethernet TENA on Port B. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int board_early_init_f (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* Disable Ethernet TENA on Port B + * Necessary because of pull up in COM3 port. + * + * This is just a preliminary fix, intended to turn off TENA + * as soon as possible to avoid noise on the network. Once + * I²C is running we will make sure the interface is + * correctly initialized. + */ + immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA; + immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA; + immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA; /* set to 0 = disabled */ + immr->im_cpm.cp_pbdir |= PB_ENET_TENA; + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +/*********************************************************************** +F* Function: void reset_phy (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: none + * +Z* Intention: Reset the PHY. In the lwmon case we do this by the +Z* signaling the PIC I/O expander. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +void reset_phy (void) +{ + uchar c; + +#ifdef DEBUG + printf ("### Switch on Ethernet for SCC2 ###\n"); +#endif + c = pic_read (0x61); +#ifdef DEBUG + printf ("Old PIC read: reg_61 = 0x%02x\n", c); +#endif + c |= 0x40; /* disable COM3 */ + c &= ~0x80; /* enable Ethernet */ + pic_write (0x61, c); +#ifdef DEBUG + c = pic_read (0x61); + printf ("New PIC read: reg_61 = 0x%02x\n", c); +#endif + udelay (1000); +} + + +/*------------------------- Keyboard controller -----------------------*/ +/* command codes */ +#define KEYBD_CMD_READ_KEYS 0x01 +#define KEYBD_CMD_READ_VERSION 0x02 +#define KEYBD_CMD_READ_STATUS 0x03 +#define KEYBD_CMD_RESET_ERRORS 0x10 + +/* status codes */ +#define KEYBD_STATUS_MASK 0x3F +#define KEYBD_STATUS_H_RESET 0x20 +#define KEYBD_STATUS_BROWNOUT 0x10 +#define KEYBD_STATUS_WD_RESET 0x08 +#define KEYBD_STATUS_OVERLOAD 0x04 +#define KEYBD_STATUS_ILLEGAL_WR 0x02 +#define KEYBD_STATUS_ILLEGAL_RD 0x01 + +/* Number of bytes returned from Keyboard Controller */ +#define KEYBD_VERSIONLEN 2 /* version information */ +#define KEYBD_DATALEN 9 /* normal key scan data */ + +/* maximum number of "magic" key codes that can be assigned */ + +static uchar kbd_addr = CFG_I2C_KEYBD_ADDR; + +static uchar *key_match (uchar *); + +#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ + +/*********************************************************************** +F* Function: int board_postclk_init (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: This function is the board_postclk_init() method implementation +Z* for the lwmon board. + * + ***********************************************************************/ +int board_postclk_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + kbd_init(); + +#ifdef CONFIG_MODEM_SUPPORT + if (key_pressed()) { + disable_putc(); /* modem doesn't understand banner etc */ + gd->do_mdm_init = 1; + } +#endif + + return (0); +} + +struct serial_device * default_serial_console (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device; +} + +static void kbd_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uchar kbd_data[KEYBD_DATALEN]; + uchar tmp_data[KEYBD_DATALEN]; + uchar val, errcd; + int i; + + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + gd->kbd_status = 0; + + /* Forced by PIC. Delays <= 175us loose */ + udelay(1000); + + /* Read initial keyboard error code */ + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &errcd, 1); + /* clear unused bits */ + errcd &= KEYBD_STATUS_MASK; + /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ + errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); + if (errcd) { + gd->kbd_status |= errcd << 8; + } + /* Reset error code and verify */ + val = KEYBD_CMD_RESET_ERRORS; + i2c_write (kbd_addr, 0, 0, &val, 1); + udelay(1000); /* delay NEEDED by keyboard PIC !!! */ + + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &val, 1); + + val &= KEYBD_STATUS_MASK; /* clear unused bits */ + if (val) { /* permanent error, report it */ + gd->kbd_status |= val; + return; + } + + /* + * Read current keyboard state. + * + * After the error reset it may take some time before the + * keyboard PIC picks up a valid keyboard scan - the total + * scan time is approx. 1.6 ms (information by Martin Rajek, + * 28 Sep 2002). We read a couple of times for the keyboard + * to stabilize, using a big enough delay. + * 10 times should be enough. If the data is still changing, + * we use what we get :-( + */ + + memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ + for (i=0; i<10; ++i) { + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { + /* consistent state, done */ + break; + } + /* remeber last state, delay, and retry */ + memcpy (tmp_data, kbd_data, KEYBD_DATALEN); + udelay (5000); + } +} + +/*********************************************************************** +F* Function: int misc_init_r (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned, even in the case of a keyboard +P* error. + * +Z* Intention: This function is the misc_init_r() method implementation +Z* for the lwmon board. +Z* The keyboard controller is initialized and the result +Z* of a read copied to the environment variable "keybd". +Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for +Z* this key, and if found display to the LCD will be enabled. +Z* The keys in "keybd" are checked against the magic +Z* keycommands defined in the environment. +Z* See also key_match(). + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar kbd_init_status = gd->kbd_status >> 8; + uchar kbd_status = gd->kbd_status; + uchar val; + char *str; + int i; + + if (kbd_init_status) { + printf ("KEYBD: Error %02X\n", kbd_init_status); + } + if (kbd_status) { /* permanent error, report it */ + printf ("*** Keyboard error code %02X ***\n", kbd_status); + sprintf (keybd_env, "%02X", kbd_status); + setenv ("keybd", keybd_env); + return 0; + } + + /* + * Now we know that we have a working keyboard, so disable + * all output to the LCD except when a key press is detected. + */ + + if ((console_assign (stdout, "serial") < 0) || + (console_assign (stderr, "serial") < 0)) { + printf ("Can't assign serial port as output device\n"); + } + + /* Read Version */ + val = KEYBD_CMD_READ_VERSION; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); + printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); + + /* Read current keyboard state */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + } + setenv ("keybd", keybd_env); + + str = strdup ((char *)key_match (kbd_data)); /* decode keys */ +#ifdef KEYBD_SET_DEBUGMODE + if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ + if ((console_assign (stdout, "lcd") < 0) || + (console_assign (stderr, "lcd") < 0)) { + printf ("Can't assign LCD display as output device\n"); + } + } +#endif /* KEYBD_SET_DEBUGMODE */ +#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ + setenv ("preboot", str); /* set or delete definition */ +#endif /* CONFIG_PREBOOT */ + if (str != NULL) { + free (str); + } + return (0); +} + +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +static int compare_magic (uchar *kbd_data, uchar *str) +{ + uchar compare[KEYBD_DATALEN-1]; + char *nxt; + int i; + + /* Don't include modifier byte */ + memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); + + for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { + uchar c; + int k; + + c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); + + if (str == (uchar *)nxt) { /* invalid character */ + break; + } + + /* + * Check if this key matches the input. + * Set matches to zero, so they match only once + * and we can find duplicates or extra keys + */ + for (k = 0; k < sizeof(compare); ++k) { + if (compare[k] == '\0') /* only non-zero entries */ + continue; + if (c == compare[k]) { /* found matching key */ + compare[k] = '\0'; + break; + } + } + if (k == sizeof(compare)) { + return -1; /* unmatched key */ + } + } + + /* + * A full match leaves no keys in the `compare' array, + */ + for (i = 0; i < sizeof(compare); ++i) { + if (compare[i]) + { + return -1; + } + } + + return 0; +} + +/*********************************************************************** +F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* + * +P* Parameters: uchar *kbd_data +P* - The keys to match against our magic definitions +P* +P* Returnvalue: uchar * +P* - != NULL: Pointer to the corresponding command(s) +P* NULL: No magic is about to happen + * +Z* Intention: Check if pressed key(s) match magic sequence, +Z* and return the command string associated with that key(s). +Z* +Z* If no key press was decoded, NULL is returned. +Z* +Z* Note: the first character of the argument will be +Z* overwritten with the "magic charcter code" of the +Z* decoded key(s), or '\0'. +Z* +Z* Note: the string points to static environment data +Z* and must be saved before you call any function that +Z* modifies the environment. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +static uchar *key_match (uchar *kbd_data) +{ + char magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can pe appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); +#if 0 + printf ("### Check magic \"%s\"\n", magic); +#endif + if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { + char cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + + cmd = getenv (cmd_name); +#if 0 + printf ("### Set PREBOOT to $(%s): \"%s\"\n", + cmd_name, cmd ? cmd : "<>"); +#endif + *kbd_data = *suffix; + return ((uchar *)cmd); + } + } +#if 0 + printf ("### Delete PREBOOT\n"); +#endif + *kbd_data = '\0'; + return (NULL); +} +#endif /* CONFIG_PREBOOT */ + +/*---------------Board Special Commands: PIC read/write ---------------*/ + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +/*********************************************************************** +F* Function: int do_pic (cmd_tbl_t *cmdtp, int flag, +F* int argc, char *argv[]) P*A*Z* + * +P* Parameters: cmd_tbl_t *cmdtp +P* - Pointer to our command table entry +P* int flag +P* - If the CMD_FLAG_REPEAT bit is set, then this call is +P* a repetition +P* int argc +P* - Argument count +P* char *argv[] +P* - Array of the actual arguments +P* +P* Returnvalue: int +P* - 0 The command was handled successfully +P* 1 An error occurred + * +Z* Intention: Implement the "pic [read|write]" commands. +Z* The read subcommand takes one argument, the register, +Z* whereas the write command takes two, the register and +Z* the new value. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar reg, val; + + switch (argc) { + case 3: /* PIC read reg */ + if (strcmp (argv[1], "read") != 0) + break; + + reg = simple_strtoul (argv[2], NULL, 16); + + printf ("PIC read: reg %02x: %02x\n\n", reg, pic_read (reg)); + + return 0; + case 4: /* PIC write reg val */ + if (strcmp (argv[1], "write") != 0) + break; + + reg = simple_strtoul (argv[2], NULL, 16); + val = simple_strtoul (argv[3], NULL, 16); + + printf ("PIC write: reg %02x val 0x%02x: %02x => ", + reg, val, pic_read (reg)); + pic_write (reg, val); + printf ("%02x\n\n", pic_read (reg)); + return 0; + default: + break; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} +U_BOOT_CMD( + pic, 4, 1, do_pic, + "pic - read and write PIC registers\n", + "read reg - read PIC register `reg'\n" + "pic write reg val - write value `val' to PIC register `reg'\n" +); + +/*********************************************************************** +F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, +F* int argc, char *argv[]) P*A*Z* + * +P* Parameters: cmd_tbl_t *cmdtp +P* - Pointer to our command table entry +P* int flag +P* - If the CMD_FLAG_REPEAT bit is set, then this call is +P* a repetition +P* int argc +P* - Argument count +P* char *argv[] +P* - Array of the actual arguments +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: Implement the "kbd" command. +Z* The keyboard status is read. The result is printed on +Z* the console and written into the "keybd" environment +Z* variable. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar val; + int i; + +#if 0 /* Done in kbd_init */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); +#endif + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + puts ("Keys:"); + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + printf (" %02x", kbd_data[i]); + } + putc ('\n'); + setenv ("keybd", keybd_env); + return 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "kbd - read keyboard status\n", + NULL +); + +/* Read and set LSB switch */ +#define CFG_PC_TXD1_ENA 0x0008 /* PC.12 */ + +/*********************************************************************** +F* Function: int do_lsb (cmd_tbl_t *cmdtp, int flag, +F* int argc, char *argv[]) P*A*Z* + * +P* Parameters: cmd_tbl_t *cmdtp +P* - Pointer to our command table entry +P* int flag +P* - If the CMD_FLAG_REPEAT bit is set, then this call is +P* a repetition +P* int argc +P* - Argument count +P* char *argv[] +P* - Array of the actual arguments +P* +P* Returnvalue: int +P* - 0 The command was handled successfully +P* 1 An error occurred + * +Z* Intention: Implement the "lsb [on|off]" commands. +Z* The lsb is switched according to the first parameter by +Z* by signaling the PIC I/O expander. +Z* Called with no arguments, the current setting is +Z* printed. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar val; + immap_t *immr = (immap_t *) CFG_IMMR; + + switch (argc) { + case 1: /* lsb - print setting */ + val = pic_read (0x60); + printf ("LSB is o%s\n", (val & 0x20) ? "n" : "ff"); + return 0; + case 2: /* lsb on or lsb off - set switch */ + val = pic_read (0x60); + + if (strcmp (argv[1], "on") == 0) { + val |= 0x20; + immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA); + immr->im_ioport.iop_pcdat |= CFG_PC_TXD1_ENA; + immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA; + } else if (strcmp (argv[1], "off") == 0) { + val &= ~0x20; + immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA); + immr->im_ioport.iop_pcdat &= ~(CFG_PC_TXD1_ENA); + immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA; + } else { + break; + } + pic_write (0x60, val); + return 0; + default: + break; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + lsb, 2, 1, do_lsb, + "lsb - check and set LSB switch\n", + "on - switch LSB on\n" + "lsb off - switch LSB off\n" + "lsb - print current setting\n" +); + +#endif /* CFG_CMD_BSP */ + +/*----------------------------- Utilities -----------------------------*/ +/*********************************************************************** +F* Function: uchar pic_read (uchar reg) P*A*Z* + * +P* Parameters: uchar reg +P* - Register to read +P* +P* Returnvalue: uchar +P* - Value read from register + * +Z* Intention: Read a register from the PIC I/O expander. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +uchar pic_read (uchar reg) +{ + return (i2c_reg_read (CFG_I2C_PICIO_ADDR, reg)); +} + +/*********************************************************************** +F* Function: void pic_write (uchar reg, uchar val) P*A*Z* + * +P* Parameters: uchar reg +P* - Register to read +P* uchar val +P* - Value to write +P* +P* Returnvalue: none + * +Z* Intention: Write to a register on the PIC I/O expander. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +void pic_write (uchar reg, uchar val) +{ + i2c_reg_write (CFG_I2C_PICIO_ADDR, reg, val); +} + +/*---------------------- Board Control Functions ----------------------*/ +/*********************************************************************** +F* Function: void board_poweroff (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: none + * +Z* Intention: Turn off the battery power and loop endless, so this +Z* should better be the last function you call... + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +void board_poweroff (void) +{ + /* Turn battery off */ + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13)); + + while (1); +} + +#ifdef CONFIG_MODEM_SUPPORT +static int key_pressed(void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar val; + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + return (compare_magic(kbd_data, (uchar *)CONFIG_MODEM_KEY_MAGIC) == 0); +} +#endif /* CONFIG_MODEM_SUPPORT */ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar val; + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0); +} +#endif diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds new file mode 100644 index 0000000..6505d45 --- /dev/null +++ b/board/lwmon/u-boot.lds @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug new file mode 100644 index 0000000..828afbb --- /dev/null +++ b/board/lwmon/u-boot.lds.debug @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/m5272c3/Makefile b/board/m5272c3/Makefile new file mode 100644 index 0000000..e5d8446 --- /dev/null +++ b/board/m5272c3/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/m5272c3/config.mk b/board/m5272c3/config.mk new file mode 100644 index 0000000..ccb2cf7 --- /dev/null +++ b/board/m5272c3/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c new file mode 100644 index 0000000..fb91843 --- /dev/null +++ b/board/m5272c3/flash.c @@ -0,0 +1,378 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x200000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_PL160CB & FLASH_TYPEMASK): + printf ("AM29PL160CB (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done: +} + + +unsigned long flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_PL160CB & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured to many flash banks!\n"); + + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j == 0) { + /* 1st is 16 KiB */ + flash_info[i].start[j] = flashbase; + } + if ((j >= 1) && (j <= 2)) { + /* 2nd and 3rd are 8 KiB */ + flash_info[i].start[j] = + flashbase + 0x4000 + 0x2000 * (j - 1); + } + if (j == 3) { + /* 4th is 224 KiB */ + flash_info[i].start[j] = flashbase + 0x8000; + } + if ((j >= 4) && (j <= 10)) { + /* rest is 256 KiB */ + flash_info[i].start[j] = + flashbase + 0x40000 + 0x40000 * (j - + 4); + } + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + 0x3ffff, &flash_info[0]); + + return size; +} + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + printf ("\n"); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = + (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + udelay (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + + +volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + } + +#if 0 + if (cnt & 1) { + printf ("odd transfer sizes not supported\n"); + return ERR_ALIGN; + } +#endif + + wp = addr; + + if (addr & 1) { + data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) + src); + if ((rc = write_word (info, wp - 1, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src) << 8) | + *((volatile u8 *) (wp + 1)); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + return ERR_OK; +} diff --git a/board/m5272c3/m5272c3.c b/board/m5272c3/m5272c3.c new file mode 100644 index 0000000..0dfeaf2 --- /dev/null +++ b/board/m5272c3/m5272c3.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + + +int checkboard (void) { + puts ("Board: "); + puts("MOTOROLA MCF5272C3 EVB\n"); + return 0; + }; + +long int initdram (int board_type) { + volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR); + + sdp->sdram_sdtr = 0xf539; + sdp->sdram_sdcr = 0x4211; + + /* Dummy write to start SDRAM */ + *((volatile unsigned long *)0) = 0; + + return CFG_SDRAM_SIZE * 1024 * 1024; + }; + +int testdram (void) { + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/m5272c3/u-boot.lds b/board/m5272c3/u-boot.lds new file mode 100644 index 0000000..f7dc070 --- /dev/null +++ b/board/m5272c3/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/m5282evb/Makefile b/board/m5282evb/Makefile new file mode 100644 index 0000000..e5d8446 --- /dev/null +++ b/board/m5282evb/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/m5282evb/config.mk b/board/m5282evb/config.mk new file mode 100644 index 0000000..8484307 --- /dev/null +++ b/board/m5282evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x20000 diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c new file mode 100644 index 0000000..ff70783 --- /dev/null +++ b/board/m5282evb/flash.c @@ -0,0 +1,378 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x200000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_PL160CB & FLASH_TYPEMASK): + printf ("AM29PL160CB (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done: +} + + +unsigned long flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_PL160CB & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured to many flash banks!\n"); + + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j == 0) { + /* 1st is 16 KiB */ + flash_info[i].start[j] = flashbase; + } + if ((j >= 1) && (j <= 2)) { + /* 2nd and 3rd are 8 KiB */ + flash_info[i].start[j] = + flashbase + 0x4000 + 0x2000 * (j - 1); + } + if (j == 3) { + /* 4th is 32 KiB */ + flash_info[i].start[j] = flashbase + 0x8000; + } + if ((j >= 4) && (j <= 34)) { + /* rest is 256 KiB */ + flash_info[i].start[j] = + flashbase + 0x10000 + 0x10000 * (j - + 4); + } + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + 0xffff, &flash_info[0]); + + return size; +} + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + printf ("\n"); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = + (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + udelay (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + + +volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + } + +#if 0 + if (cnt & 1) { + printf ("odd transfer sizes not supported\n"); + return ERR_ALIGN; + } +#endif + + wp = addr; + + if (addr & 1) { + data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) + src); + if ((rc = write_word (info, wp - 1, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src) << 8) | + *((volatile u8 *) (wp + 1)); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + return ERR_OK; +} diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c new file mode 100644 index 0000000..a08af68 --- /dev/null +++ b/board/m5282evb/m5282evb.c @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +int checkboard (void) +{ + puts ("MOTOROLA M5272EVB Evaluation Board\n"); + return 0; +} + +long int initdram (int board_type) +{ + return 0x1000000; +} diff --git a/board/m5282evb/u-boot.lds b/board/m5282evb/u-boot.lds new file mode 100644 index 0000000..c461d20 --- /dev/null +++ b/board/m5282evb/u-boot.lds @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/string.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset; */ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile new file mode 100644 index 0000000..3e8376c --- /dev/null +++ b/board/mbx8xx/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o vpd.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/mbx8xx/config.mk b/board/mbx8xx/config.mk new file mode 100644 index 0000000..d5e8ed2 --- /dev/null +++ b/board/mbx8xx/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MBX8xx boards +# + +TEXT_BASE = 0xfe000000 +/*TEXT_BASE = 0x00200000 */ diff --git a/board/mbx8xx/csr.h b/board/mbx8xx/csr.h new file mode 100644 index 0000000..832e924 --- /dev/null +++ b/board/mbx8xx/csr.h @@ -0,0 +1,60 @@ +#ifndef __csr_h +#define __csr_h + +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Control and Status Register definitions for the MBX + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* bits for control register #1 / status register #1 */ +#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */ +#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */ +#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */ +#define CSR1_TPEN 0x10 /* TP manually selected */ +#define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */ +#define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */ +#define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */ +#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */ + +/* bits for control register #2 */ +#define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ +#define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ +#define CR2_BRDFAIL 0x08 /* Board fail */ +#define CR2_SWS1 0x04 /* Software Status #2 LED */ +#define CR2_SWS2 0x02 /* Software Status #2 LED */ +#define CR2_QSPANRST 0x01 /* Reset QSPAN */ + +/* bits for status register #2 */ +#define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ +#define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ +#define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */ +#define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */ +#define SR2_RDY 0x02 /* Flash programming status bit */ +#define SR2_FT 0x01 /* Reserved for Factory test purposes */ + +#define MBX_CSR1 (*((uchar *)CFG_CSR_BASE)) +#define MBX_CSR2 (*((uchar *)CFG_CSR_BASE + 1)) + +#endif /* __csr_h */ diff --git a/board/mbx8xx/dimm.h b/board/mbx8xx/dimm.h new file mode 100644 index 0000000..b40f112 --- /dev/null +++ b/board/mbx8xx/dimm.h @@ -0,0 +1,98 @@ +#ifndef __dimm_h +#define __dimm_h + +/* + * Module name: %M% + * Description: + * Serial Presence Detect Definitions Module + * SCCS identification: %I% + * Branch: %B% + * Sequence: %S% + * Date newest applied delta was created (MM/DD/YY): %G% + * Time newest applied delta was created (HH:MM:SS): %U% + * SCCS file name %F% + * Fully qualified SCCS file name: + * %P% + * Copyright: + * (C) COPYRIGHT MOTOROLA, INC. 1996 + * ALL RIGHTS RESERVED + * Notes: + * 1. All data was taken from an IBM application note titled + * "Serial Presence Detect Definitions". + * History: + * Date Who + * + * 10/24/96 Rob Baxter + * Initial release. + * + */ + +/* + * serial PD byte assignment address map (256 byte EEPROM) + */ +typedef struct dimm +{ + uchar n_bytes; /* 00 number of bytes written/used */ + uchar t_bytes; /* 01 total number of bytes in serial PD device */ + uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */ + uchar n_row; /* 03 number of rows */ + uchar n_col; /* 04 number of columns */ + uchar n_banks; /* 05 number of banks */ + uchar data_w_lo; /* 06 data width */ + uchar data_w_hi; /* 07 data width */ + uchar ifl; /* 08 interface levels */ + uchar a_ras; /* 09 RAS access */ + uchar a_cas; /* 0A CAS access */ + uchar ct; /* 0B configuration type (non-parity/parity/ECC) */ + uchar refresh_rt; /* 0C refresh rate/type */ + uchar p_dram_o; /* 0D primary DRAM organization */ + uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */ + uchar reserved[17]; /* 0F reserved fields for future offerings */ + uchar ss_info[32]; /* 20 superset information (may be used in the future) */ + uchar m_info[64]; /* 40 manufacturer information (optional) */ + uchar unused[128]; /* 80 unused storage locations */ +} dimm_t; + +/* + * memory type definitions + */ +#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */ +#define DIMM_MT_EDO 2 /* EDO (extended data out) */ +#define DIMM_MT_PN 3 /* pipelined nibble */ +#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */ + +/* + * row addresses definitions + */ +#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */ +#define DIMM_RA_MASK 0x7f /* number of row addresses mask */ + +/* + * module interface levels definitions + */ +#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */ +#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */ +#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */ +#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */ +#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */ + +/* + * DIMM configuration type definitions + */ +#define DIMM_CT_NONE 0 /* none */ +#define DIMM_CT_PARITY 1 /* parity */ +#define DIMM_CT_ECC 2 /* ECC */ + +/* + * row addresses definitions + */ +#define DIMM_RRT_SR (1<<7) /* self refresh flag */ +#define DIMM_RRT_MASK 0x7f /* refresh rate mask */ +#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */ +#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */ +#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */ +#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */ +#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */ +#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */ + +#endif /* __dimm_h */ diff --git a/board/mbx8xx/flash.c b/board/mbx8xx/flash.c new file mode 100644 index 0000000..a491f7b --- /dev/null +++ b/board/mbx8xx/flash.c @@ -0,0 +1,408 @@ +/* + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AM290[48]0B devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "vpd.h" + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size, totsize; + int i; + ulong addr; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + return (totsize); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id >> 16) { + case 0x1: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + case AMD_ID_F080B: + printf ("AM29F080B (8 Mbit)\n"); + break; + case AMD_ID_F016D: + printf ("AM29F016D (16 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong vendor, devid; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x90909090; + + vendor = addr[0]; + devid = addr[1] & 0xff; + + /* only support AMD */ + if (vendor != 0x01010101) { + return 0; + } + + vendor &= 0xf; + devid &= 0xff; + + if (devid == AMD_ID_F040B) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 8; + info->size = info->sector_count * 0x10000; + } + else if (devid == AMD_ID_F080B) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 16; + info->size = 4 * info->sector_count * 0x10000; + } + else if (devid == AMD_ID_F016D) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 32; + info->size = 4 * info->sector_count * 0x10000; + } + else { + printf ("## Unknown Flash Type: %08lx\n", devid); + return 0; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* sector base address */ + info->start[i] = base + i * (info->size / info->sector_count); + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_long *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0XAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x80808080; + addr[0x0555] = 0XAAAAAAAA; + addr[0x02AA] = 0x55555555; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x30303030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0xA0A0A0A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c new file mode 100644 index 0000000..9a9bf80 --- /dev/null +++ b/board/mbx8xx/mbx8xx.c @@ -0,0 +1,379 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Board specific routines for the MBX + * + * - initialisation + * - interface to VPD data (mac address, clock speeds) + * - memory controller + * - serial io initialisation + * - ethernet io initialisation + * + * ----------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "dimm.h" +#include "vpd.h" +#include "csr.h" + +/* ------------------------------------------------------------------------- */ + +static const uint sdram_table_40[] = { + /* DRAM - single read. (offset 0 in upm RAM) + */ + 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, + 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, + + /* DRAM - burst read. (offset 8 in upm RAM) + */ + 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08, + 0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08, + 0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005, + 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, + + /* DRAM - single write. (offset 18 in upm RAM) + */ + 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804, + 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, + + /* DRAM - burst write. (offset 20 in upm RAM) + */ + 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, + 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, + 0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005, + 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, + + /* refresh (offset 30 in upm RAM) + */ + 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, + 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, + 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, + + /* exception. (offset 3c in upm RAM) + */ + 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, +}; + +static const uint sdram_table_50[] = { + /* DRAM - single read. (offset 0 in upm RAM) + */ + 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, + 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, + + /* DRAM - burst read. (offset 8 in upm RAM) + */ + 0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04, + /* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */ + 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, + 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04, + /* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */ + 0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005, + + /* DRAM - single write. (offset 18 in upm RAM) + */ + 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804, + 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, + + /* DRAM - burst write. (offset 20 in upm RAM) + */ + 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, + 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, + 0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005, + 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, + + /* refresh (offset 30 in upm RAM) + */ + 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, + 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, + 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, + + /* exception. (offset 3c in upm RAM) + */ + 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, +}; + +/* ------------------------------------------------------------------------- */ + +static unsigned int get_reffreq(void); +static unsigned int board_get_cpufreq(void); + +void mbx_init (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + ulong speed, refclock, plprcr, sccr; + ulong br0_32 = memctl->memc_br0 & 0x400; + + /* real-time clock status and control register */ + immr->im_sitk.sitk_rtcsck = KAPWR_KEY; + immr->im_sit.sit_rtcsc = 0x00C3; + + /* SIEL and SIMASK Registers (see MBX PRG 2-3) */ + immr->im_siu_conf.sc_simask = 0x00000000; + immr->im_siu_conf.sc_siel = 0xAAAA0000; + immr->im_siu_conf.sc_tesr = 0xFFFFFFFF; + + /* + * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus: + * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h) + * 2. RAM Specs (see dimm.h) + * 2. DIMM Specs (see dimm.h) + */ + vpd_init (); + + /* system clock and reset control register */ + immr->im_clkrstk.cark_sccrk = KAPWR_KEY; + sccr = immr->im_clkrst.car_sccr; + sccr &= SCCR_MASK; + sccr |= CFG_SCCR; + immr->im_clkrst.car_sccr = sccr; + + speed = board_get_cpufreq (); + refclock = get_reffreq (); + +#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0) + plprcr = CFG_PLPRCR; +#else + plprcr = immr->im_clkrst.car_plprcr; + plprcr &= PLPRCR_MF_MSK; /* isolate MF field */ + plprcr |= CFG_PLPRCR; /* reset control bits */ +#endif + +#ifdef CFG_USE_OSCCLK /* See doc/README.MBX ! */ + plprcr |= ((speed + refclock / 2) / refclock - 1) << 20; +#endif + + immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; + immr->im_clkrst.car_plprcr = plprcr; + + /* + * preliminary setup of memory controller: + * - map Flash, otherwise configuration/status + * registers won't be accessible when read + * by board_init_f. + * - map NVRAM and configuation/status registers. + * - map pci registers. + * - DON'T map ram yet, this is done in initdram(). + */ + switch (speed / 1000000) { + case 40: + memctl->memc_br0 = 0xFE000000 | br0_32 | 1; + memctl->memc_or0 = 0xFF800930; + memctl->memc_or4 = CFG_NVRAM_OR | 0x920; + memctl->memc_br4 = CFG_NVRAM_BASE | 0x401; + break; + case 50: + memctl->memc_br0 = 0xFE000000 | br0_32 | 1; + memctl->memc_or0 = 0xFF800940; + memctl->memc_or4 = CFG_NVRAM_OR | 0x930; + memctl->memc_br4 = CFG_NVRAM_BASE | 0x401; + break; + default: + hang (); + break; + } +#ifdef CONFIG_USE_PCI + memctl->memc_or5 = CFG_PCIMEM_OR; + memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001; + memctl->memc_or6 = CFG_PCIBRIDGE_OR; + memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001; +#endif + /* + * FIXME: I do not understand why I have to call this to + * initialise the control register here before booting from + * the PCMCIA card but if I do not the Linux kernel falls + * over in a big heap. If you can answer this question I + * would like to know about it. + */ + board_ether_init(); +} + +void board_serial_init (void) +{ + MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS); +} + +void board_ether_init (void) +{ + MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN); + MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS; +} + +static unsigned int board_get_cpufreq (void) +{ +#ifndef CONFIG_8xx_GCLK_FREQ + vpd_packet_t *packet; + + packet = vpd_find_packet (VPD_PID_ICS); + return *((ulong *) packet->data); +#else + return((unsigned int)CONFIG_8xx_GCLK_FREQ ); +#endif /* CONFIG_8xx_GCLK_FREQ */ +} + +static unsigned int get_reffreq (void) +{ + vpd_packet_t *packet; + + packet = vpd_find_packet (VPD_PID_RCS); + return *((ulong *) packet->data); +} + +void board_get_enetaddr (uchar * addr) +{ + int i; + vpd_packet_t *packet; + + packet = vpd_find_packet (VPD_PID_EA); + for (i = 0; i < 6; i++) + addr[i] = packet->data[i]; +} + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + vpd_packet_t *packet; + int i; + const char *const fmt = + "\n *** Warning: Low Battery Status - %s Battery ***"; + + puts ("Board: "); + + packet = vpd_find_packet (VPD_PID_PID); + for (i = 0; i < packet->size; i++) { + serial_putc (packet->data[i]); + } + packet = vpd_find_packet (VPD_PID_MT); + for (i = 0; i < packet->size; i++) { + serial_putc (packet->data[i]); + } + serial_putc ('('); + packet = vpd_find_packet (VPD_PID_FAN); + for (i = 0; i < packet->size; i++) { + serial_putc (packet->data[i]); + } + serial_putc (')'); + + if (!(MBX_CSR2 & SR2_BATGD)) + printf (fmt, "On-Board"); + if (!(MBX_CSR2 & SR2_NVBATGD)) + printf (fmt, "NVRAM"); + + serial_putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +static ulong get_ramsize (dimm_t * dimm) +{ + ulong size = 0; + + if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3 + || dimm->fmt == 4) { + size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks * + ((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8); + } + + return size; +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long ram_sz = 0; + unsigned long dimm_sz = 0; + dimm_t vpd_dimm, vpd_dram; + unsigned int speed = board_get_cpufreq () / 1000000; + + if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) { + dimm_sz = get_ramsize (&vpd_dimm); + } + if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) { + ram_sz = get_ramsize (&vpd_dram); + } + + /* + * Only initialize memory controller when running from FLASH. + * When running from RAM, don't touch it. + */ + if ((ulong) initdram & 0xff000000) { + ulong dimm_bank; + ulong br0_32 = memctl->memc_br0 & 0x400; + + switch (speed) { + case 40: + upmconfig (UPMA, (uint *) sdram_table_40, + sizeof (sdram_table_40) / sizeof (uint)); + memctl->memc_mptpr = 0x0200; + memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000; + memctl->memc_or7 = 0xff800930; + memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; + break; + case 50: + upmconfig (UPMA, (uint *) sdram_table_50, + sizeof (sdram_table_50) / sizeof (uint)); + memctl->memc_mptpr = 0x0200; + memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100; + memctl->memc_or7 = 0xff800940; + memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; + break; + default: + hang (); + break; + } + + /* now map ram and dimm, largest one first */ + dimm_bank = dimm_sz / 2; + if (!dimm_sz) { + memctl->memc_or1 = ~(ram_sz - 1) | 0x400; + memctl->memc_br1 = CFG_SDRAM_BASE | 0x81; + memctl->memc_br2 = 0; + memctl->memc_br3 = 0; + } else if (ram_sz > dimm_bank) { + memctl->memc_or1 = ~(ram_sz - 1) | 0x400; + memctl->memc_br1 = CFG_SDRAM_BASE | 0x81; + memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; + memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81; + memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; + memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) \ + | 0x81; + } else { + memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; + memctl->memc_br2 = CFG_SDRAM_BASE | 0x81; + memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; + memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81; + memctl->memc_or1 = ~(ram_sz - 1) | 0x400; + memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81; + } + } + + return ram_sz + dimm_sz; +} diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds new file mode 100644 index 0000000..1400cea --- /dev/null +++ b/board/mbx8xx/u-boot.lds @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug new file mode 100644 index 0000000..650572d --- /dev/null +++ b/board/mbx8xx/u-boot.lds.debug @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mbx8xx/vpd.c b/board/mbx8xx/vpd.c new file mode 100644 index 0000000..6f88352 --- /dev/null +++ b/board/mbx8xx/vpd.c @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Code in faintly related to linux/arch/ppc/8xx_io: + * MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net). + * + * This file implements functions to read the MBX's Vital Product Data + * (VPD). I can't use the more general i2c code in mpc8xx/... since I need + * the VPD at a time where there is no RAM available yet. Hence the VPD is + * read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD). + * + * ----------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#ifdef CONFIG_8xx +#include +#endif +#include "vpd.h" + +/* Location of receive/transmit buffer descriptors + * Allocate one transmit bd and one receive bd. + * IIC_BD_FREE points to free bd space which we'll use as tx buffer. + */ +#define IIC_BD_TX1 (BD_IIC_START + 0*sizeof(cbd_t)) +#define IIC_BD_TX2 (BD_IIC_START + 1*sizeof(cbd_t)) +#define IIC_BD_RX (BD_IIC_START + 2*sizeof(cbd_t)) +#define IIC_BD_FREE (BD_IIC_START + 3*sizeof(cbd_t)) + +/* FIXME -- replace 0x2000 with offsetof */ +#define VPD_P ((vpd_t *)(CFG_IMMR + 0x2000 + CFG_DPRAMVPD)) + +/* transmit/receive buffers */ +#define IIC_RX_LENGTH 128 + +#define WITH_MICROCODE_PATCH + +vpd_packet_t * vpd_find_packet(u_char ident) +{ + vpd_packet_t *packet; + vpd_t *vpd = VPD_P; + + packet = (vpd_packet_t *)&vpd->packets; + while ((packet->identifier != ident) && packet->identifier != 0xFF) + { + packet = (vpd_packet_t *)((char *)packet + packet->size + 2); + } + return packet; +} + +void vpd_init(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); + volatile iic_t *iip; +#ifdef WITH_MICROCODE_PATCH + ulong reloc = 0; +#endif + + iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; + + /* + * kludge: when running from flash, no microcode patch can be + * installed. However, the DPMEM usually contains non-zero + * garbage at the relocatable patch base location, so lets clear + * it now. This way the rest of the code can support the microcode + * patch dynamically. + */ + if ((ulong)vpd_init & 0xff000000) + iip->iic_rpbase = 0; + +#ifdef WITH_MICROCODE_PATCH + /* Check for and use a microcode relocation patch. */ + if ((reloc = iip->iic_rpbase)) + iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; +#endif + /* Initialize Port B IIC pins */ + cp->cp_pbpar |= 0x00000030; + cp->cp_pbdir |= 0x00000030; + cp->cp_pbodr |= 0x00000030; + + i2c->i2c_i2mod = 0x04; /* filter clock */ + i2c->i2c_i2add = 0x34; /* select an arbitrary (unique) address */ + i2c->i2c_i2brg = 0x07; /* make clock run maximum slow */ + i2c->i2c_i2cmr = 0x00; /* disable interrupts */ + i2c->i2c_i2cer = 0x1f; /* clear events */ + i2c->i2c_i2com = 0x01; /* configure i2c to work as master */ + + if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE) + { + hang(); + } +} + + +/* Read from I2C. + * This is a two step process. First, we send the "dummy" write + * to set the device offset for the read. Second, we perform + * the read operation. + */ +int vpd_read(uint iic_device, uchar *buf, int count, int offset) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); + volatile iic_t *iip; + volatile cbd_t *tbdf1, *tbdf2, *rbdf; + uchar *tb; + uchar event; +#ifdef WITH_MICROCODE_PATCH + ulong reloc = 0; +#endif + + iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; +#ifdef WITH_MICROCODE_PATCH + /* Check for and use a microcode relocation patch. */ + if ((reloc = iip->iic_rpbase)) + iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; +#endif + tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1]; + tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2]; + rbdf = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX]; + + /* Send a "dummy write" operation. This is a write request with + * only the offset sent, followed by another start condition. + * This will ensure we start reading from the first location + * of the EEPROM. + */ + tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE]; + tb[0] = iic_device & 0xfe; /* device address */ + tb[1] = offset; /* offset */ + tbdf1->cbd_bufaddr = (uint)tb; + tbdf1->cbd_datlen = 2; + tbdf1->cbd_sc = 0x8400; + + tb += 2; + tb[0] = iic_device | 1; /* device address */ + tbdf2->cbd_bufaddr = (uint)tb; + tbdf2->cbd_datlen = count+1; + tbdf2->cbd_sc = 0xbc00; + + rbdf->cbd_bufaddr = (uint)buf; + rbdf->cbd_datlen = 0; + rbdf->cbd_sc = 0xb000; + + iip->iic_tbase = IIC_BD_TX1; + iip->iic_tbptr = IIC_BD_TX1; + iip->iic_rbase = IIC_BD_RX; + iip->iic_rbptr = IIC_BD_RX; + iip->iic_rfcr = 0x15; + iip->iic_tfcr = 0x15; + iip->iic_mrblr = count; + iip->iic_rstate = 0; + iip->iic_tstate = 0; + + i2c->i2c_i2cer = 0x1f; /* clear event mask */ + i2c->i2c_i2mod |= 1; /* enable iic operation */ + i2c->i2c_i2com |= 0x80; /* start master */ + + /* wait for IIC transfer */ + do { + __asm__ volatile ("eieio"); + event = i2c->i2c_i2cer; + } while (event == 0); + + if ((event & 0x10) || (event & 0x04)) { + count = -1; + goto bailout; + } + +bailout: + i2c->i2c_i2mod &= ~1; /* turn off iic operation */ + i2c->i2c_i2cer = 0x1f; /* clear event mask */ + + return count; +} diff --git a/board/mbx8xx/vpd.h b/board/mbx8xx/vpd.h new file mode 100644 index 0000000..1d9eb7f --- /dev/null +++ b/board/mbx8xx/vpd.h @@ -0,0 +1,119 @@ +#ifndef __vpd_h +#define __vpd_h + +/* + * Module name: %M% + * Description: + * Vital Product Data (VPD) Header Module + * SCCS identification: %I% + * Branch: %B% + * Sequence: %S% + * Date newest applied delta was created (MM/DD/YY): %G% + * Time newest applied delta was created (HH:MM:SS): %U% + * SCCS file name %F% + * Fully qualified SCCS file name: + * %P% + * Copyright: + * (C) COPYRIGHT MOTOROLA, INC. 1996 + * ALL RIGHTS RESERVED + * Notes: + * History: + * Date Who + * + * 10/24/96 Rob Baxter + * Initial release. + * + */ + +#define VPD_EEPROM_SIZE 256 /* EEPROM size in bytes */ + +/* + * packet tuple identifiers + * + * 0x0D - 0xBF reserved + * 0xC0 - 0xFE user defined + */ +#define VPD_PID_GI 0x00 /* guaranteed illegal */ +#define VPD_PID_PID 0x01 /* product identifier (ASCII) */ +#define VPD_PID_FAN 0x02 /* factory assembly-number (ASCII) */ +#define VPD_PID_SN 0x03 /* serial-number (ASCII) */ +#define VPD_PID_PCO 0x04 /* product configuration options(binary) */ +#define VPD_PID_ICS 0x05 /* internal clock speed in HZ (integer) */ +#define VPD_PID_ECS 0x06 /* external clock speed in HZ (integer) */ +#define VPD_PID_RCS 0x07 /* reference clock speed in HZ(integer) */ +#define VPD_PID_EA 0x08 /* ethernet address (binary) */ +#define VPD_PID_MT 0x09 /* microprocessor type (ASCII) */ +#define VPD_PID_CRC 0x0A /* EEPROM CRC (integer) */ +#define VPD_PID_FMC 0x0B /* FLASH memory configuration (binary) */ +#define VPD_PID_VLSI 0x0C /* VLSI revisions/versions (binary) */ +#define VPD_PID_TERM 0xFF /* termination */ + +/* + * VPD structure (format) + */ +#define VPD_EYE_SIZE 8 /* eyecatcher size */ +typedef struct vpd_header +{ + uchar eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "MOTOROLA" */ + ushort size; /* size of EEPROM */ +} vpd_header_t; + +#define VPD_DATA_SIZE (VPD_EEPROM_SIZE-sizeof(vpd_header_t)) +typedef struct vpd +{ + vpd_header_t header; /* header */ + uchar packets[VPD_DATA_SIZE]; /* data */ +} vpd_t; + +/* + * packet tuple structure (format) + */ +typedef struct vpd_packet +{ + uchar identifier; /* identifier (PIDs above) */ + uchar size; /* size of the following data area */ + uchar data[1]; /* data (size is dependent upon PID) */ +} vpd_packet_t; + +/* + * MBX product configuration options bit definitions + * + * Notes: + * 1. The bit numbering is reversed in perspective with the C compiler. + */ +#define PCO_BBRAM (1<<0) /* battery-backed RAM (BBRAM) and socket */ +#define PCO_BOOTROM (1<<1) /* boot ROM and socket (i.e., socketed FLASH) */ +#define PCO_KAPWR (1<<2) /* keep alive power source (lithium battey) and control circuit */ +#define PCO_ENET_TP (1<<3) /* ethernet twisted pair (TP) connector (RJ45) */ +#define PCO_ENET_AUI (1<<4) /* ethernet attachment unit interface (AUI) header */ +#define PCO_PCMCIA (1<<5) /* PCMCIA socket */ +#define PCO_DIMM (1<<6) /* DIMM module socket */ +#define PCO_DTT (1<<7) /* digital thermometer and thermostat (DTT) device */ +#define PCO_LCD (1<<8) /* liquid crystal display (LCD) device */ +#define PCO_PCI (1<<9) /* PCI-Bus bridge device (QSpan) and ISA-Bus bridge device (Winbond) */ +#define PCO_PCIO (1<<10) /* PC I/O (COM1, COM2, FDC, LPT, Keyboard/Mouse) */ +#define PCO_EIDE (1<<11) /* enhanced IDE (EIDE) header */ +#define PCO_FDC (1<<12) /* floppy disk controller (FDC) header */ +#define PCO_LPT_8XX (1<<13) /* parallel port header via MPC8xx */ +#define PCO_LPT_PCIO (1<<14) /* parallel port header via PC I/O */ + +/* + * FLASH memory configuration packet data + */ +typedef struct vpd_fmc +{ + ushort mid; /* manufacturer's idenitfier */ + ushort did; /* manufacturer's device idenitfier */ + uchar ddw; /* device data width (e.g., 8-bits, 16-bits) */ + uchar nod; /* number of devices present */ + uchar noc; /* number of columns */ + uchar cw; /* column width in bits */ + uchar wedw; /* write/erase data width */ +} vpd_fmc_t; + +/* function prototypes */ +extern void vpd_init(void); +extern int vpd_read(uint iic_device, uchar *buf, int count, int offset); +extern vpd_packet_t *vpd_find_packet(u_char ident); + +#endif /* __vpd_h */ diff --git a/board/ml2/Makefile b/board/ml2/Makefile new file mode 100644 index 0000000..40c60b1 --- /dev/null +++ b/board/ml2/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o serial.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/ml2/config.mk b/board/ml2/config.mk new file mode 100644 index 0000000..41118d5 --- /dev/null +++ b/board/ml2/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0x18000000 diff --git a/board/ml2/flash.c b/board/ml2/flash.c new file mode 100644 index 0000000..87cb1ff --- /dev/null +++ b/board/ml2/flash.c @@ -0,0 +1,300 @@ +/* + * flash.c: Support code for the flash chips on the Xilinx ML2 board + * + * Copyright 2002 Mind NV + * + * http://www.mind.be/ + * + * Author : Peter De Schrijver (p2@mind.be) + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire program + * is licensed under the GPL. + * + */ + +#include +#include +#include + +#define FLASH_BANK_SIZE (64*1024*1024) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define SECT_SIZE (512*1024) + +#define CMD_READ_ARRAY 0x00FF00FF00FF00FULL +#define CMD_IDENTIFY 0x0090009000900090ULL +#define CMD_ERASE_SETUP 0x0020002000200020ULL +#define CMD_ERASE_CONFIRM 0x00D000D000D000D0ULL +#define CMD_PROGRAM 0x0040004000400040ULL +#define CMD_RESUME 0x00D000D000D000D0ULL +#define CMD_SUSPEND 0x00B000B000B000B0ULL +#define CMD_STATUS_READ 0x0070007000700070ULL +#define CMD_STATUS_RESET 0x0050005000500050ULL + +#define BIT_BUSY 0x0080008000800080ULL +#define BIT_ERASE_SUSPEND 0x004000400400040ULL +#define BIT_ERASE_ERROR 0x0020002000200020ULL +#define BIT_PROGRAM_ERROR 0x0010001000100010ULL +#define BIT_VPP_RANGE_ERROR 0x0008000800080008ULL +#define BIT_PROGRAM_SUSPEND 0x0004000400040004ULL +#define BIT_PROTECT_ERROR 0x0002000200020002ULL +#define BIT_UNDEFINED 0x0001000100010001ULL + +#define BIT_SEQUENCE_ERROR 0x0030003000300030ULL + +#define BIT_TIMEOUT 0x80000000 + + +inline void eieio(void) { + + __asm__ __volatile__ ("eieio" : : : "memory"); + +} + +ulong flash_init(void) { + + int i, j; + ulong size = 0; + + for(i=0;iflash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf("Intel: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F128J3A & FLASH_TYPEMASK): + printf("4x 28F128J3A (128Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) + printf("\n "); + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + +int flash_error (unsigned long long code) { + + if (code & BIT_TIMEOUT) { + printf ("Timeout\n"); + return ERR_TIMOUT; + } + + if (~code & BIT_BUSY) { + printf ("Busy\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_VPP_RANGE_ERROR) { + printf ("Vpp range error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_PROTECT_ERROR) { + printf ("Device protect error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_SEQUENCE_ERROR) { + printf ("Command seqence error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_ERASE_ERROR) { + printf ("Block erase error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_PROGRAM_ERROR) { + printf ("Program error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_ERASE_SUSPEND) { + printf ("Block erase suspended\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_PROGRAM_SUSPEND) { + printf ("Program suspended\n"); + return ERR_PROG_ERROR; + } + + return ERR_OK; + +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) { + + int rc = ERR_OK; + int sect; + unsigned long long result; + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) + return ERR_INVAL; + + if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + + for (sect=s_first; sect<=s_last; ++sect) + if (info->protect[sect]) + return ERR_PROTECTED; + + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { + volatile unsigned long long *addr= + (unsigned long long *)(info->start[sect]); + + printf("Erasing sector %2d ... ", sect); + + *addr=CMD_STATUS_RESET; + eieio(); + *addr=CMD_ERASE_SETUP; + eieio(); + *addr=CMD_ERASE_CONFIRM; + eieio(); + + do { + result = *addr; + } while(~result & BIT_BUSY); + + *addr=CMD_READ_ARRAY; + + if ((rc = flash_error(result)) == ERR_OK) + printf("ok.\n"); + else + break; + } + + if (ctrlc()) + printf("User Interrupt!\n"); + + return rc; +} + +static int write_word (flash_info_t *info, ulong dest, unsigned long long data) { + + volatile unsigned long long *addr=(unsigned long long *)dest; + unsigned long long result; + int rc = ERR_OK; + + result=*addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + *addr=CMD_STATUS_RESET; + eieio(); + *addr=CMD_PROGRAM; + eieio(); + *addr=data; + eieio(); + + do { + result=*addr; + } while(~result & BIT_BUSY); + + *addr=CMD_READ_ARRAY; + + rc = flash_error(result); + + return rc; + +} + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { + + ulong cp, wp; + unsigned long long data; + int l; + int i,rc; + + wp=(addr & ~7); + + if((l=addr-wp) != 0) { + data=0; + for(i=0,cp=wp;i> 8) | (*(uchar *)cp << 24); + + for (; i<8 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + + for (; i<8; ++i, ++cp) + data = (data >> 8) | (*(uchar *)cp << 24); + + if ((rc = write_word(info, wp, data)) != 0) + return rc; + + wp+=8; + } + + while(cnt>=8) { + data=*((unsigned long long *)src); + if ((rc = write_word(info, wp, data)) != 0) + return rc; + src+=8; + wp+=8; + cnt-=8; + } + + if(cnt == 0) + return ERR_OK; + + data = 0; + for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i<8; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + return write_word(info, wp, data); + +} diff --git a/board/ml2/init.S b/board/ml2/init.S new file mode 100644 index 0000000..80f98c5 --- /dev/null +++ b/board/ml2/init.S @@ -0,0 +1,34 @@ +/* + * init.S: Stubs for U-Boot initialization + * + * Copyright 2002 Mind NV + * + * http://www.mind.be/ + * + * Author : Peter De Schrijver (p2@mind.be) + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#include + +#include +#include + +#include +#include + + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + blr + + .globl sdram_init +sdram_init: + blr diff --git a/board/ml2/ml2.c b/board/ml2/ml2.c new file mode 100644 index 0000000..f32e512 --- /dev/null +++ b/board/ml2/ml2.c @@ -0,0 +1,66 @@ +/* + * ml2.c: U-Boot platform support for Xilinx ML2 board + * + * Copyright 2002 Mind NV + * + * http://www.mind.be/ + * + * Author : Peter De Schrijver (p2@mind.be) + * + * Derived from : Other platform support files in this tree + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#include +#include + + +int board_early_init_f (void) +{ + return 0; +} + + +int checkboard (void) +{ + char *s = getenv ("serial#"); + char *e; + + if (!s || strncmp (s, "ML2", 9)) { + printf ("### No HW ID - assuming ML2"); + } else { + for (e = s; *e; ++e) { + if (*e == ' ') + break; + } + + for (; s < e; ++s) { + putc (*s); + } + } + + + putc ('\n'); + + return (0); +} + + +long int initdram (int board_type) +{ + return 32 * 1024 * 1024; +} + +int testdram (void) +{ + printf ("test: xxx MB - ok\n"); + + return (0); +} diff --git a/board/ml2/serial.c b/board/ml2/serial.c new file mode 100644 index 0000000..92baba9 --- /dev/null +++ b/board/ml2/serial.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2002 + * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +#include +#endif + +#if 0 +#include "serial.h" +#endif + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, + (NS16550_t) CFG_NS16550_COM2 }; +#endif + +int +serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + (void)NS16550_init(COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + (void)NS16550_init(COM_PORTS[1], clock_divisor); +#endif + return 0; + +} + +void +serial_putc(const char c) +{ + if (c == '\n') + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); + + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); +} + +int +serial_getc(void) +{ + return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); +} + +int +serial_tstc(void) +{ + return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + NS16550_reinit(COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + NS16550_reinit(COM_PORTS[1], clock_divisor); +#endif +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +void +kgdb_serial_init(void) +{ +} + +void +putDebugChar (int c) +{ + serial_putc (c); +} + +void +putDebugStr (const char *str) +{ + serial_puts (str); +} + +int +getDebugChar (void) +{ + return serial_getc(); +} + +void +kgdb_interruptible (int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds new file mode 100644 index 0000000..f8e9e33 --- /dev/null +++ b/board/ml2/u-boot.lds @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/ml2/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ml2/u-boot.lds.debug b/board/ml2/u-boot.lds.debug new file mode 100644 index 0000000..1608f8c --- /dev/null +++ b/board/ml2/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/modnet50/Makefile b/board/modnet50/Makefile new file mode 100644 index 0000000..ab2c376 --- /dev/null +++ b/board/modnet50/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := modnet50.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/modnet50/config.mk b/board/modnet50/config.mk new file mode 100644 index 0000000..49d4836 --- /dev/null +++ b/board/modnet50/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x00f00000 +#CROSS_COMPILE = arm-elf- diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c new file mode 100644 index 0000000..a50639e --- /dev/null +++ b/board/modnet50/flash.c @@ -0,0 +1,536 @@ +/* + * (C) Copyright 2002 + * MAZeT GmbH + * Stephan Linz , + * + * The most stuff comes from PPCBoot and Linux. + * + * IMMS gGmbH + * Thomas Elste + * + * Modifications for ModNET50 Board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define SCR (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_SYSTEM_CONTROL)) + +#define ALIGN_ABORT_OFF SCR = SCR & ~NETARM_GEN_SYS_CFG_ALIGN_ABORT +#define ALIGN_ABORT_ON SCR = SCR | NETARM_GEN_SYS_CFG_ALIGN_ABORT + +#define PROG_ADDR (0x555*2) +#define SETUP_ADDR (0x555*2) +#define ID_ADDR (0x555*2) +#define UNLOCK_ADDR1 (0x555*2) +#define UNLOCK_ADDR2 (0x2AA*2) + +#define UNLOCK_CMD1 (0xAA) +#define UNLOCK_CMD2 (0x55) +#define ERASE_SUSPEND_CMD (0xB0) +#define ERASE_RESUME_CMD (0x30) +#define RESET_CMD (0xF0) +#define ID_CMD (0x90) +#define SECERASE_CMD (0x30) +#define CHIPERASE_CMD (0x10) +#define PROG_CMD (0xa0) +#define SETUP_CMD (0x80) + +#define DQ2 (0x04) +#define DQ3 (DQ2*2) +#define DQ5 (DQ3*4) +#define DQ6 (DQ5*2) + +#define WRITE_UNLOCK(addr) { \ + *(volatile __u16*)(addr + UNLOCK_ADDR1) = (__u16)UNLOCK_CMD1; \ + *(volatile __u16*)(addr + UNLOCK_ADDR2) = (__u16)UNLOCK_CMD2; \ +} + +#define CONFIG_AM29_RESERVED (0) +#define K (1024) +#define MB (4) + +#define CELL_SIZE (64*K) +#define DEVICE_SIZE (MB*K*K) +#define CELLS_PER_DEVICE (DEVICE_SIZE/CELL_SIZE) +#define RESERVED_CELLS (CONFIG_AM29_RESERVED*K)/CELL_SIZE +#define MAX_FLASH_DEVICES (1) +#define AVAIL_SIZE (DEVICE_SIZE*MAX_FLASH_DEVICES - RESERVED_CELLS*CELL_SIZE) + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +static __u16 toggling_bits; + + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size (ulong baseaddr, flash_info_t * info) +{ + short i; + __u16 flashtest; + + /* Write auto select command sequence and test FLASH answer */ + WRITE_UNLOCK (baseaddr); + *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD; + flashtest /* manufacturer ID */ = *(volatile __u16 *) (baseaddr); + *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD; + + switch ((__u32) ((flashtest << 16) + flashtest)) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD & FLASH_VENDMASK; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ & FLASH_VENDMASK; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + /* Write auto select command sequence and test FLASH answer */ + WRITE_UNLOCK (baseaddr); + *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD; + flashtest /* device ID */ = *(volatile __u16 *) (baseaddr + 2); + *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD; + + /* toggling_bits = (flashtest == TOSHIBA)?(DQ6):(DQ2|DQ6); */ + toggling_bits = (DQ2 | DQ6); + + switch ((__u32) ((flashtest << 16) + flashtest)) { + case AMD_ID_LV160B: + info->flash_id += + (FLASH_AM160LV | FLASH_AM160B) & FLASH_TYPEMASK; + info->sector_count = CFG_MAX_FLASH_SECT; + info->size = CFG_FLASH_SIZE; + /* 1*16K Boot Block + 2*8K Parameter Block + 1*32K Small Main Block */ + info->start[0] = baseaddr; + info->start[1] = baseaddr + 0x4000; + info->start[2] = baseaddr + 0x6000; + info->start[3] = baseaddr + 0x8000; + for (i = 1; i < info->sector_count; i++) + info->start[3 + i] = baseaddr + i * CFG_MAIN_SECT_SIZE; + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* no or unknown flash */ + } + + for (i = 0; i < info->sector_count; i++) { + /* Write auto select command sequence and test FLASH answer */ + WRITE_UNLOCK (info->start[i]); + *(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) ID_CMD; + flashtest /* protected verify */ = *(volatile __u16 *) (info->start[i] + 4); + *(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) RESET_CMD; + if (flashtest & 0x0001) { + info->protect[i] = 1; /* D0 = 1 if protected */ + } else { + info->protect[i] = 0; + } + } + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +ulong flash_init (void) +{ + ulong size = 0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here (only one bank) */ + size = flash_get_size (CFG_FLASH_BASE, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN || size == 0) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size, size >> 20); + } + + /* + * protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("Fujitsu "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDL323B: + printf ("29DL323B (32 M, bottom sector)\n"); + break; + case (FLASH_AM160LV | FLASH_AM160B): + printf ("29LV160BE (1M x 16, bottom sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 4) == 0) + printf ("\n "); + printf (" S%02d @ 0x%08lX%s", i, + info->start[i], info->protect[i] ? " !" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ +int flash_check_protection (flash_info_t * info, int s_first, int s_last) +{ + int sect, prot = 0; + + for (sect = s_first; sect <= s_last; sect++) + if (info->protect[sect]) + prot++; + if (prot) + printf ("- can't erase %d protected sectors\n", prot); + return prot; +} + +/*----------------------------------------------------------------------- + */ +int flash_check_erase_amd (ulong start) +{ + __u16 v1, v2; + + v1 = *(volatile __u16 *) (start); + v2 = *(volatile __u16 *) (start); + + if (((v1 ^ v2) & toggling_bits) == toggling_bits) { + if (((v1 | v2) & DQ5) == DQ5) { + printf ("[DQ5] "); + /* OOPS: exceeded timing limits */ + + v1 = *(volatile __u16 *) (start); + v2 = *(volatile __u16 *) (start); + + if (((v1 ^ v2) & toggling_bits) == toggling_bits) { + + printf ("[%s] ", + ((toggling_bits & (DQ2 | DQ6)) == + (DQ2 | DQ6)) ? "DQ2,DQ6" : "DQ6"); + + /* OOPS: there is an erasure in progress, + * try to reset chip */ + *(volatile __u16 *) (start) = + (__u16) RESET_CMD; + + return 1; /* still busy */ + } + } + return 1; /* still busy */ + } + return 0; /* be free */ +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, sect, setup_offset = 0; + int rc = ERR_OK; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + return ERR_UNKNOWN_FLASH_TYPE; + } + + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return ERR_INVAL; + } + + if (flash_check_protection (info, s_first, s_last)) + return ERR_PROTECTED; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_FUJ: + case FLASH_MAN_AMD: + switch (info->flash_id & FLASH_TYPEMASK) { + case (FLASH_AM160LV | FLASH_AM160B): + setup_offset = UNLOCK_ADDR1; /* just the adress for setup_cmd differs */ + case FLASH_AMDL323B: + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); + sect++) { + printf ("Erasing sector %2d ... ", sect); + + if (info->protect[sect] == 0) { + /* not protected */ + /* Write sector erase command sequence */ + WRITE_UNLOCK (info->start[0]); + *(volatile __u16 *) (info->start[0] + + setup_offset) = + (__u16) SETUP_CMD; + WRITE_UNLOCK (info->start[0]); + *(volatile __u16 *) (info-> + start[sect]) = + (__u16) SECERASE_CMD; + + /* wait some time */ + reset_timer_masked (); + while (get_timer_masked () < 1000) { + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + while (flash_check_erase_amd (info->start[sect])) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("timeout!\n"); + /* OOPS: reach timeout, + * try to reset chip + */ + *(volatile __u16 *) (info-> start[sect]) = (__u16) RESET_CMD; + rc = ERR_TIMOUT; + goto outahere_323B; + } + } + printf ("ok.\n"); + } else { + printf ("protected!\n"); + } + } + if (ctrlc ()) + printf ("User Interrupt!\n"); +outahere_323B: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + if (flag) + enable_interrupts (); + return rc; + default: + printf ("- unknown chip type\n"); + return ERR_UNKNOWN_FLASH_TYPE; + } + break; + default: + printf ("- unknown vendor "); + return ERR_UNKNOWN_FLASH_VENDOR; + } +} + +/*----------------------------------------------------------------------- + */ +int flash_check_write_amd (ulong dest) +{ + __u16 v1, v2; + + v1 = *(volatile __u16 *) (dest); + v2 = *(volatile __u16 *) (dest); + + /* DQ6 toggles during write */ + if (((v1 ^ v2) & DQ6) == DQ6) { + if (((v1 | v2) & DQ5) == DQ5) { + printf ("[DQ5] @ %08lX\n", dest); + + /* OOPS: exceeded timing limits, + * try to reset chip */ + *(volatile __u16 *) (dest) = (__u16) RESET_CMD; + return 0; /* be free */ + } + return 1; /* still busy */ + } + + return 0; /* be free */ +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ +static int write_word (flash_info_t * info, ulong dest, ushort data) +{ + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*(__u16 *) (dest) & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* Write program command sequence */ + WRITE_UNLOCK (info->start[0]); + + /* Flash dependend program seqence */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_FUJ: + case FLASH_MAN_AMD: + switch (info->flash_id & FLASH_TYPEMASK) { + case (FLASH_AM160LV | FLASH_AM160B): + *(volatile __u16 *) (info->start[0] + UNLOCK_ADDR1) = + (__u16) PROG_CMD; + *(volatile __u16 *) (dest) = (__u16) data; + break; + case FLASH_AMDL323B: + *(volatile __u16 *) (dest) = (__u16) PROG_CMD; + *(volatile __u16 *) (dest) = (__u16) data; + break; + } + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + while (flash_check_write_amd (dest)) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + printf ("timeout! @ %08lX\n", dest); + /* OOPS: reach timeout, + * try to reset chip */ + *(volatile __u16 *) (dest) = (__u16) RESET_CMD; + + rc = ERR_TIMOUT; + goto outahere_323B; + } + } + + /* Check if Flash was (accurately) written */ + if (*(__u16 *) (dest) != data) + rc = ERR_PROG_ERROR; + +outahere_323B: + if (flag) + enable_interrupts (); + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + ushort data; + int l; + int i, rc; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((ushort *) src); + if ((rc = write_word (info, wp, data)) != 0) + return (rc); + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_word (info, wp, data); +} diff --git a/board/modnet50/lowlevel_init.S b/board/modnet50/lowlevel_init.S new file mode 100644 index 0000000..c98c155 --- /dev/null +++ b/board/modnet50/lowlevel_init.S @@ -0,0 +1,204 @@ +/* + * Memory Setup stuff - taken from Linux + * + * Copyright (c) 2002 Stephan Linz , + * (c) 2004 IMMS gGmbH , Thomas Elste + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include + + +/* some parameters for the board */ +#define FLASH_90ns_WAIT_STATES ((NETARM_PLL_COUNT_VAL + 2) / 3) +#define FLASH_70ns_WAIT_STATES 4 + +#define NETARM_MMAP_CS0_BASE (PHYS_FLASH_1) +#if 1 +#define NETARM_MMAP_CS0_MASK (~(PHYS_FLASH_1_SIZE - 1)) +#else +#define NETARM_MMAP_CS0_MASK (~(1000000 - 1)) +#endif +#define NETARM_MMAP_CS1_BASE (PHYS_SDRAM_1) +#define NETARM_MMAP_CS1_MASK (~(PHYS_SDRAM_1_SIZE - 1)) +#define NETARM_MMAP_CS2_BASE (PHYS_SDRAM_2) +#define NETARM_MMAP_CS2_MASK (~(PHYS_SDRAM_2_SIZE - 1)) +#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE) +#define NETARM_MMAP_CS3_BASE (PHYS_NVRAM_1) +#define NETARM_MMAP_CS3_MASK (~(PHYS_NVRAM_SIZE - 1)) +#endif +#define NETARM_MMAP_CS4_BASE (PHYS_EXT_1) +#define NETARM_MMAP_CS4_MASK (~(PHYS_EXT_SIZE - 1)) + +/* setting up the memory */ +.globl lowlevel_init +lowlevel_init: + +#if defined(CONFIG_MODNET50) + ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE) + +_jump_to_high: + /* + * MEM Config Reg + * --------------------------------------------------- + */ + ldr r0, =NETARM_MEM_MODULE_BASE + ldr r1, =( NETARM_MEM_REFR_PERIOD_USEC(16) | \ + NETARM_MEM_CFG_REFRESH_EN | \ + NETARM_MEM_CFG_REFR_CYCLE_5CLKS ) + str r1, [r0, #+NETARM_MEM_MODULE_CONFIG] + + +memsetup_cs0: + /* + * Base Addr / Option Reg 0 (Flash) + * --------------------------------------------------- + */ + ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \ + NETARM_MEM_BAR_DRAM_FP | \ + NETARM_MEM_BAR_DRAM_MUX_INT | \ + NETARM_MEM_BAR_DRAM_MUX_BAL | \ + NETARM_MEM_BAR_VALID ) + str r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR] + + /* trust that the bus size for flash was strapped correctly */ + /* this saves the bus width in r2 and then ORs it back in */ + /* it's pretty safe assumption, otherwise it wouldn't boot */ + ldr r2, [r0, #+NETARM_MEM_CS0_OPTIONS] + and r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK + +/* just a test: assume 32 bit flash mem */ +/* mov r2, #NETARM_MEM_OPT_32BIT */ + + ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \ + NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \ + NETARM_MEM_OPT_BCYC_4 | \ + NETARM_MEM_OPT_BSIZE_16 | \ + NETARM_MEM_OPT_16BIT | \ + NETARM_MEM_OPT_READ_ASYNC | \ + NETARM_MEM_OPT_WRITE_ASYNC ) + + orr r1, r1, r2 + str r1, [r0, #+NETARM_MEM_CS0_OPTIONS] + + +memsetup_cs1: + /* + * Base Addr / Option Reg 1 (DRAM #1) + * --------------------------------------------------- + */ +#ifdef CONFIG_NETARM_NET40_REV2 + /* we have to config SDRAM in burst mode */ + ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \ + NETARM_MEM_OPT_BCYC_2 | \ + NETARM_MEM_OPT_BSIZE_16 | \ + NETARM_MEM_OPT_WAIT_STATES(0) | \ + NETARM_MEM_OPT_32BIT | \ + NETARM_MEM_OPT_READ_ASYNC | \ + NETARM_MEM_OPT_WRITE_ASYNC ) + str r1, [r0, #+NETARM_MEM_CS1_OPTIONS] + + ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \ + NETARM_MEM_BAR_DRAM_SYNC | \ + NETARM_MEM_BAR_DRAM_MUX_INT | \ + NETARM_MEM_BAR_DRAM_MUX_UNBAL | \ + NETARM_MEM_BAR_DRAM_SEL | \ + NETARM_MEM_BAR_BURST_EN | \ + NETARM_MEM_BAR_VALID ) + str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR] +#else + /* we have to config FPDRAM in burst mode with smaller burst access size */ + ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \ + NETARM_MEM_OPT_BCYC_2 | \ + NETARM_MEM_OPT_BSIZE_16 | \ + NETARM_MEM_OPT_WAIT_STATES(0) | \ + NETARM_MEM_OPT_32BIT | \ + NETARM_MEM_OPT_READ_ASYNC | \ + NETARM_MEM_OPT_WRITE_ASYNC ) + str r1, [r0, #+NETARM_MEM_CS1_OPTIONS] + + ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \ + NETARM_MEM_BAR_DRAM_SYNC | \ + NETARM_MEM_BAR_DRAM_MUX_INT | \ + NETARM_MEM_BAR_DRAM_MUX_UNBAL | \ + NETARM_MEM_BAR_DRAM_SEL | \ + NETARM_MEM_BAR_BURST_EN | \ + NETARM_MEM_BAR_VALID ) + str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR] + +#endif /* CONFIG_NETARM_NET40_REV2 */ + + +memsetup_cs3: + /* + * Base Addr / Option Reg 3 (EEPROM, NVRAM) + * --------------------------------------------------- + */ +#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE) + ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \ + NETARM_MEM_OPT_BCYC_3 | \ + NETARM_MEM_OPT_BSIZE_2 | \ + NETARM_MEM_OPT_WAIT_STATES(10) | \ + NETARM_MEM_OPT_8BIT | \ + NETARM_MEM_OPT_READ_ASYNC | \ + NETARM_MEM_OPT_WRITE_ASYNC ) + str r1, [r0, #+NETARM_MEM_CS3_OPTIONS] + + ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \ + NETARM_MEM_BAR_DRAM_FP | \ + NETARM_MEM_BAR_DRAM_MUX_INT | \ + NETARM_MEM_BAR_DRAM_MUX_BAL | \ + NETARM_MEM_BAR_VALID ) + str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR] +#else + /* we don't need EEPROM --> no config */ + ldr r1, =( 0 ) + str r1, [r0, #+NETARM_MEM_CS3_OPTIONS] + + ldr r1, =( 0 ) + str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR] +#endif + + +#else +/* +#error "missing CONFIG_MODNET50 (see your config.h)" +*/ +#endif /* CONFIG_MODNET50 */ + + +lowlevel_init_end: + /* + * manipulate address in lr and ip to match new + * address space + */ + ldr r3, =(NETARM_MMAP_CS0_BASE) + mov r0, lr + add r0, r3, r0 + mov lr, r0 + mov r0, ip + add r0, r3, r0 + mov ip, r0 + + /* everything is fine now */ + mov pc, lr diff --git a/board/modnet50/modnet50.c b/board/modnet50/modnet50.c new file mode 100644 index 0000000..448c623 --- /dev/null +++ b/board/modnet50/modnet50.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* address for the kernel command line */ + gd->bd->bi_boot_params = 0x800; + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + if (CONFIG_NR_DRAM_BANKS == 2) { + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + } + return (0); +} diff --git a/board/modnet50/u-boot.lds b/board/modnet50/u-boot.lds new file mode 100644 index 0000000..5b70a40 --- /dev/null +++ b/board/modnet50/u-boot.lds @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/board/mousse/Makefile b/board/mousse/Makefile new file mode 100644 index 0000000..ddc5546 --- /dev/null +++ b/board/mousse/Makefile @@ -0,0 +1,41 @@ + +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o m48t59y.o pci.o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/mousse/README b/board/mousse/README new file mode 100644 index 0000000..d5dda7a --- /dev/null +++ b/board/mousse/README @@ -0,0 +1,346 @@ + +U-Boot for MOUSSE/MPC8240 (KAHLUA) +---------------------------------- +James Dougherty (jfd@broadcom.com), 09/10/01 + +The Broadcom/Vooha Mousse board is a 3U Compact PCI system board +which uses the MPC8240, a 64MB SDRAM SIMM, and has onboard +DEC 21143, NS16550 UART, an SGS M48T59Y TOD, and 4MB FLASH. +See also: http://www.vooha.com/ + +* NVRAM setenv/printenv/savenv supported. +* Date Command +* Serial Console support +* Network support +* FLASH of kernel images is supported. +* FLASH of U-Boot to onboard and PLCC boot region. +* Kernel command line options from NVRAM is supported. +* IP PNP options supported. + +U-Boot Loading... + + +U-Boot 1.0.5 (Sep 10 2001 - 00:22:25) + +CPU: MPC8240 Revision 1.1 at 198 MHz: 16 kB I-Cache 16 kB D-Cache +Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B) +Built: Sep 10 2001 at 01:01:50 +MPLD: Revision 127 +Local Bus: 33 MHz +RTC: M48T589 TOD/NVRAM (8176) bytes + Current date/time: 9/10/2001 0:18:52 +DRAM: 64 MB +FLASH: 1.960 MB +PCI: scanning bus0 ... + bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE + 00 00 00 1057 0003 060000 11 00000008 00000000 01 00 + 00 0d 00 1011 0019 020000 41 80000001 80000000 01 01 + 00 0e 00 105a 4d38 018000 01 a0000001 a0001001 01 03 +In: serial +Out: serial +Err: serial + +Hit any key to stop autoboot: 0 +=> + +I. Root FileSystem/IP Configuration + +bootcmd=tftp 100000 vmlinux.img;bootm +bootdelay=3 +baudrate=9600 +ipaddr= +netmask= +hostname= +serverip= +ethaddr=00:00:10:20:30:44 +nfsroot=:/boot/root-fs +gateway= +root=/dev/nfs +stdin=serial +stdout=serial +stderr=serial + +NVRAM environment variables. + +use the command: + +setenv + +type "saveenv" to write to NVRAM. + + +II. To boot from a hard drive: + +setenv root /dev/hda1 + + +III. IP options which configure the network: + +ipaddr= +netmask= +hostname=mousse +ethaddr=00:00:10:20:30:44 +gateway= + + +IV. IP Options which configure NFS Root/Boot Support + +root=/dev/nfs +serverip= +nfsroot=:/boot/root-fs + +V. U-Boot Image Support + +The U-Boot boot loader assumes that after you build +your kernel (vmlinux), you will create a U-Boot image +using the following commands or script: + +#!/bin/csh +/bin/touch vmlinux.img +/bin/rm vmlinux.img +set path=($TOOLBASE/bin $path) +set path=($U_BOOT/tools $path) +powerpc-linux-objcopy -S -O binary vmlinux vmlinux.bin +gzip -vf vmlinux.bin +mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 -n vmlinux.bin.gz -d vmlinux.bin.gz vmlinux.img +ls -l vmlinux.img + + +VI. ONBOARD FLASH Support + +FLASH support is provided for the onboard FLASH chip Bootrom area. +U-Boot is loaded into either the ROM boot region of the FLASH chip, +after first being boot-strapped from a pre-progammed AMD29F040 PLCC +bootrom. The PLCC needs to be programmed with a ROM burner using +AMD 29F040 ROM parts and the u-boot.bin or u-boot.hex (S-Record) +images. + +The PLCC overlays this same region of flash as the onboard FLASH, +the jumper J100 is a chip-select for which flash chip you want to +progam. When jumper J100 is connected to pins 2-3, you boot from +PLCC FLASH. + +To bringup a system, simply flash a flash an AMD29F040 PLCC +bootrom, and put this in the PLCC socket. Move jumper J100 to +pins 2-3 and boot from the PLCC. + + +Now, while the system is running, move Jumper J100 to +pins 1-2 and follow the procedure below to FLASH a bootrom +(u-boot.bin) image into the onboard bootrom region (AMD29LV160DB): + +tftp 100000 u-boot.bin +protect off FFF00000 FFF7FFFF +erase FFF00000 FFF7FFFF +cp.b 100000 FFF00000 \${filesize}\ + + +Here is an example: + +=>tftp 100000 u-boot.bin +eth_halt +eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) +DEC Ethernet iobase=0x80000000 +ARP broadcast 1 +Filename 'u-boot.bin'. +Load address: 0x100000 +Loading: ######################### +done +Bytes transferred = 123220 (1e154 hex) +eth_halt +=>protect off FFF00000 FFF7FFFF +Un-Protected 8 sectors +=>erase FFF00000 FFF7FFFF +Erase Flash from 0xfff00000 to 0xfff7ffff +Erase FLASH[PLCC_BOOT] -8 sectors:........ done +Erased 8 sectors +=>cp.b 100000 FFF00000 1e154 +Copy to Flash... FLASH[PLCC_BOOT]:..done +=> + + +B. FLASH RAMDISK REGION + +FLASH support is provided for an Onboard 512K RAMDISK region. + +TThe following commands will FLASH a bootrom (u-boot.bin) image +into the onboard FLASH region (AMD29LV160DB 2MB FLASH): + +tftp 100000 u-boot.bin +protect off FFF80000 FFFFFFFF +erase FFF80000 FFFFFFFF +cp.b 100000 FFF80000 \${filesize}\ + + +C. FLASH KERNEL REGION (960KB) + +FLASH support is provided for the 960KB onboard FLASH1 segment. +This allows flashing of kernel images which U-Boot can load +and run (standalone) from the onboard FLASH chip. It also assumes + +The following commands will FLASH a kernel image to 0xffe10000 + +tftp 100000 vmlinux.img +protect off FFE10000 FFEFFFFF +erase FFE10000 FFEFFFFF +cp.b 100000 FFE10000 \${filesize}\ +reset + +Here is an example: + + +=>tftp 100000 vmlinux.img +eth_halt +eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) +DEC Ethernet iobase=0x80000000 +ARP broadcast 1 +TFTP from server 209.128.93.133; our IP address is 209.128.93.138 +Filename 'vmlinux.img'. +Load address: 0x100000 +Loading: ##################################################################################################################################################### +done +Bytes transferred = 760231 (b99a7 hex) +eth_halt +=>protect off FFE10000 FFEFFFFF +Un-Protected 15 sectors +=>erase FFE10000 FFEFFFFF +Erase Flash from 0xffe10000 to 0xffefffff +Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done +Erased 15 sectors +=>cp.b 100000 FFE10000 b99a7 +Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done +=> + + +When finished, use the command: + +bootm ffe10000 + +to start the kernel. + +Finally, to make this the default boot command, use +the following commands: + +setenv bootcmd bootm ffe10000 +savenv + +to make it automatically boot the kernel from FLASH. + + +To go back to development mode (NFS boot) + +setenv bootcmd tftp 100000 vmlinux.img\;bootm +savenv + + +=>tftp 100000 vmlinux.img +eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) +DEC Ethernet iobase=0x80000000 +ARP broadcast 1 +Filename 'vmlinux.img'. +Load address: 0x100000 +Loading: #################################################################################################################################################### +done +Bytes transferred = 752717 (b7c4d hex) +eth_halt +=>protect off FFE10000 FFEFFFFF +Un-Protected 15 sectors +=>erase FFE10000 FFEFFFFF +Erase Flash from 0xffe10000 to 0xffefffff +Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done +Erased 15 sectors +=>cp.b 100000 FFE10000 b7c4d +Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done +=>bootm ffe10000 +## Booting image at ffe10000 ... + Image Name: vmlinux.bin.gz + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 752653 Bytes = 735 kB = 0 MB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK +Total memory = 64MB; using 0kB for hash table (at 00000000) +Linux version 2.4.2_hhl20 (jfd@atlantis) (gcc version 2.95.2 19991024 (release)) #597 Wed Sep 5 23:23:23 PDT 2001 +cpu0: MPC8240/KAHLUA : MOUSSE Platform : 64MB RAM: MPLD Rev. 7f +Sandpoint port (C) 2000, 2001 MontaVista Software, Inc. (source@mvista.com) +IP PNP: 802.3 Ethernet Address=<0:0:10:20:30:44> +NOTICE: mounting root file system via NFS +On node 0 totalpages: 16384 +zone(0): 16384 pages. +zone(1): 0 pages. +zone(2): 0 pages. +time_init: decrementer frequency = 16.665914 MHz +time_init: MPC8240 PCI Bus frequency = 33.331828 MHz +Calibrating delay loop... 133.12 BogoMIPS +Memory: 62436k available (1336k kernel code, 500k data, 88k init, 0k highmem) +Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes) +Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) +Page-cache hash table entries: 16384 (order: 4, 65536 bytes) +Inode-cache hash table entries: 4096 (order: 3, 32768 bytes) +POSIX conformance testing by UNIFIX +PCI: Probing PCI hardware +Linux NET4.0 for Linux 2.4 +Based upon Swansea University Computer Society NET3.039 +Initializing RT netlink socket +Starting kswapd v1.8 +pty: 256 Unix98 ptys configured +block: queued sectors max/low 41394kB/13798kB, 128 slots per queue +Uniform Multi-Platform E-IDE driver Revision: 6.31 +ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx +PDC20262: IDE controller on PCI bus 00 dev 70 +PDC20262: chipset revision 1 +PDC20262: not 100% native mode: will probe irqs later +PDC20262: ROM enabled at 0x000d0000 +PDC20262: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode. +PDC20262: FORCING BURST BIT 0x00 -> 0x01 ACTIVE +PDC20262: irq=3 dev->irq=3 + ide0: BM-DMA at 0xbfff00-0xbfff07, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0xbfff08-0xbfff0f, BIOS settings: hdc:pio, hdd:pio +hda: WDC WD300AB-00BVA0, ATA DISK drive +hdc: SONY CD-RW CRX160E, ATAPI CD/DVD-ROM drive +ide0 at 0xbfff78-0xbfff7f,0xbfff76 on irq 3 +ide1 at 0xbfff68-0xbfff6f,0xbfff66 on irq 3 +hda: 58633344 sectors (30020 MB) w/2048KiB Cache, CHS=58168/16/63, UDMA(66) +hdc: ATAPI 32X CD-ROM CD-R/RW drive, 4096kB Cache +Uniform CD-ROM driver Revision: 3.12 +Partition check: + /dev/ide/host0/bus0/target0/lun0: p1 p2 +hd: unable to get major 3 for hard disk +udf: registering filesystem +loop: loaded (max 8 devices) +Serial driver version 5.02 (2000-08-09) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled +ttyS00 at 0xffe08080 (irq = 4) is a ST16650 +Linux Tulip driver version 0.9.13a (January 20, 2001) +eth0: Digital DS21143 Tulip rev 65 at 0xbfff80, EEPROM not present, 00:00:10:20:30:44, IRQ 1. +eth0: MII transceiver #0 config 3000 status 7829 advertising 01e1. +NET4: Linux TCP/IP 1.0 for NET4.0 +IP Protocols: ICMP, UDP, TCP +IP: routing cache hash table of 512 buckets, 4Kbytes +TCP: Hash tables configured (established 4096 bind 4096) +NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. +devfs: v0.102 (20000622) Richard Gooch (rgooch@atnf.csiro.au) +devfs: boot_options: 0x0 +VFS: Mounted root (nfs filesystem). +Mounted devfs on /dev +Freeing unused kernel memory: 88k init 4k openfirmware +eth0: Setting full-duplex based on MII#0 link partner capability of 45e1. +INIT: version 2.78 booting +INIT: Entering runlevel: 2 + + +Welcome to Linux/PPC +MPC8240/MOUSSE + + +mousse login: root +Password: +PAM_unix[13]: (login) session opened for user root by LOGIN(uid=0) +Last login: Thu Sep 6 00:16:51 2001 on console + + +Welcome to Linux/PPC +MPC8240/MOUSSE + + +mousse# diff --git a/board/mousse/config.mk b/board/mousse/config.mk new file mode 100644 index 0000000..64cffa4 --- /dev/null +++ b/board/mousse/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MOUSSE boards +# +TEXT_BASE = 0xFFF00000 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/mousse/flash.c b/board/mousse/flash.c new file mode 100644 index 0000000..2c32b8f --- /dev/null +++ b/board/mousse/flash.c @@ -0,0 +1,939 @@ +/* + * MOUSSE/MPC8240 Board definitions. + * Flash Routines for MOUSSE onboard AMD29LV106DB devices + * + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. + * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "mousse.h" +#include "flash.h" + +int flashLibDebug = 0; +int flashLibInited = 0; + +#define OK 0 +#define ERROR -1 +#define STATUS int +#define PRINTF if (flashLibDebug) printf +#if 0 +#define PRIVATE static +#else +#define PRIVATE +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define SLEEP_DELAY 166 +#define FLASH_SECTOR_SIZE (64*1024) +/*********************************************************************** + * + * Virtual Flash Devices on Mousse board + * + * These must be kept in sync with the definitions in flashLib.h. + * + ***********************************************************************/ + +PRIVATE flash_dev_t flashDev[] = { + /* Bank 0 sector SA0 (16 kB) */ + { "SA0",FLASH0_BANK, FLASH0_SEG0_START, 1, 14, + FLASH0_VENDOR_ID, FLASH0_DEVICE_ID + }, + /* Bank 0 sector SA1 (8 kB) */ + { "SA1", FLASH0_BANK, FLASH0_SEG0_START + 0x4000, 1, 13, + FLASH0_VENDOR_ID, FLASH0_DEVICE_ID + }, + /* Bank 0 sector SA2 (8 kB) */ + { "SA2", FLASH0_BANK, FLASH0_SEG0_START + 0x6000, 1, 13, + FLASH0_VENDOR_ID, FLASH0_DEVICE_ID + }, + /* Bank 0 sector SA3 is occluded by Mousse I/O devices */ + /* Bank 0 sectors SA4-SA18, after Mousse devices up to PLCC (960 kB) */ + { "KERNEL", FLASH0_BANK, FLASH0_SEG1_START, 15, 16, + FLASH0_VENDOR_ID, FLASH0_DEVICE_ID + }, + /* Bank 0 sectors SA19-SA26, jumper can occlude this by PLCC (512 kB) */ + /* This is where the Kahlua boot vector and boot ROM code resides. */ + { "BOOT",FLASH0_BANK, FLASH0_SEG2_START, 8, 16, + FLASH0_VENDOR_ID, FLASH0_DEVICE_ID + }, + /* Bank 0 sectors SA27-SA34 (512 kB) */ + { "RAMDISK",FLASH0_BANK, FLASH0_SEG3_START, 8, 16, + FLASH0_VENDOR_ID, FLASH0_DEVICE_ID + }, +}; + +int flashDevCount = (sizeof (flashDev) / sizeof (flashDev[0])); + +#define DEV(no) (&flashDev[no]) +#define DEV_NO(dev) ((dev) - flashDev) + +/*********************************************************************** + * + * Private Flash Routines + * + ***********************************************************************/ + +/* + * The convention is: + * + * "addr" is always the PROM raw address, which is the address of an + * 8-bit quantity for flash 0 and 16-bit quantity for flash 1. + * + * "pos" is always a logical byte position from the PROM beginning. + */ + +#define FLASH0_ADDR(dev, addr) \ + ((unsigned char *) ((dev)->base + (addr))) + +#define FLASH0_WRITE(dev, addr, value) \ + (*FLASH0_ADDR(dev, addr) = (value)) + +#define FLASH0_READ(dev, addr) \ + (*FLASH0_ADDR(dev, addr)) + +PRIVATE int flashCheck (flash_dev_t * dev) +{ + if (!flashLibInited) { + printf ("flashCheck: flashLib not initialized\n"); + return ERROR; + } + + if (dev < &flashDev[0] || dev >= &flashDev[flashDevCount]) { + printf ("flashCheck: Bad dev parameter\n"); + return ERROR; + } + + if (!dev->found) { + printf ("flashCheck: Device %d not available\n", DEV_NO (dev)); + return ERROR; + } + + return OK; +} + +PRIVATE void flashReset (flash_dev_t * dev) +{ + PRINTF ("flashReset: dev=%d\n", DEV_NO (dev)); + + if (dev->bank == FLASH0_BANK) { + FLASH0_WRITE (dev, 0x555, 0xaa); + FLASH0_WRITE (dev, 0xaaa, 0x55); + FLASH0_WRITE (dev, 0x555, 0xf0); + } + + udelay (SLEEP_DELAY); + + PRINTF ("flashReset: done\n"); +} + +PRIVATE int flashProbe (flash_dev_t * dev) +{ + int rv, deviceID, vendorID; + + PRINTF ("flashProbe: dev=%d\n", DEV_NO (dev)); + + if (dev->bank != FLASH0_BANK) { + rv = ERROR; + goto DONE; + } + + FLASH0_WRITE (dev, 0xaaa, 0xaa); + FLASH0_WRITE (dev, 0x555, 0x55); + FLASH0_WRITE (dev, 0xaaa, 0x90); + + udelay (SLEEP_DELAY); + + vendorID = FLASH0_READ (dev, 0); + deviceID = FLASH0_READ (dev, 2); + + FLASH0_WRITE (dev, 0, 0xf0); + + PRINTF ("flashProbe: vendor=0x%x device=0x%x\n", vendorID, deviceID); + + if (vendorID == dev->vendorID && deviceID == dev->deviceID) + rv = OK; + else + rv = ERROR; + + DONE: + PRINTF ("flashProbe: rv=%d\n", rv); + + return rv; +} + +PRIVATE int flashWait (flash_dev_t * dev, int addr, int expect, int erase) +{ + int rv = ERROR; + int i, data; + int polls; + +#if 0 + PRINTF ("flashWait: dev=%d addr=0x%x expect=0x%x erase=%d\n", + DEV_NO (dev), addr, expect, erase); +#endif + + if (dev->bank != FLASH0_BANK) { + rv = ERROR; + goto done; + } + + if (erase) + polls = FLASH_ERASE_SECTOR_TIMEOUT; /* Ticks */ + else + polls = FLASH_PROGRAM_POLLS; /* Loops */ + + for (i = 0; i < polls; i++) { + if (erase) + udelay (SLEEP_DELAY); + + data = FLASH0_READ (dev, addr); + + if (((data ^ expect) & 0x80) == 0) { + rv = OK; + goto done; + } + + if (data & 0x20) { + /* + * If the 0x20 bit has come on, it could actually be because + * the operation succeeded, so check the done bit again. + */ + + data = FLASH0_READ (dev, addr); + + if (((data ^ expect) & 0x80) == 0) { + rv = OK; + goto done; + } + + printf ("flashWait: Program error (dev: %d, addr: 0x%x)\n", + DEV_NO (dev), addr); + + flashReset (dev); + rv = ERROR; + goto done; + } + } + + printf ("flashWait: Timeout %s (dev: %d, addr: 0x%x)\n", + erase ? "erasing sector" : "programming byte", + DEV_NO (dev), addr); + + done: + +#if 0 + PRINTF ("flashWait: rv=%d\n", rv); +#endif + + return rv; +} + +/*********************************************************************** + * + * Public Flash Routines + * + ***********************************************************************/ + +STATUS flashLibInit (void) +{ + int i; + + PRINTF ("flashLibInit: devices=%d\n", flashDevCount); + + for (i = 0; i < flashDevCount; i++) { + flash_dev_t *dev = &flashDev[i]; + + /* + * For bank 1, probe both without and with byte swappage, + * so that this module works on both old and new Mousse boards. + */ + + flashReset (dev); + + if (flashProbe (dev) != ERROR) + dev->found = 1; + + flashReset (dev); + + if (flashProbe (dev) != ERROR) + dev->found = 1; + + dev->swap = 0; + + if (dev->found) { + PRINTF ("\n FLASH %s[%d]: iobase=0x%x - %d sectors %d KB", + flashDev[i].name, i, flashDev[i].base, + flashDev[i].sectors, + (flashDev[i].sectors * FLASH_SECTOR_SIZE) / 1024); + + } + } + + flashLibInited = 1; + + PRINTF ("flashLibInit: done\n"); + + return OK; +} + +STATUS flashEraseSector (flash_dev_t * dev, int sector) +{ + int pos, addr; + + PRINTF ("flashErasesector: dev=%d sector=%d\n", DEV_NO (dev), sector); + + if (flashCheck (dev) == ERROR) + return ERROR; + + if (sector < 0 || sector >= dev->sectors) { + printf ("flashEraseSector: Sector out of range (dev: %d, sector: %d)\n", DEV_NO (dev), sector); + return ERROR; + } + + pos = FLASH_SECTOR_POS (dev, sector); + + if (dev->bank != FLASH0_BANK) { + return ERROR; + } + + addr = pos; + + FLASH0_WRITE (dev, 0xaaa, 0xaa); + FLASH0_WRITE (dev, 0x555, 0x55); + FLASH0_WRITE (dev, 0xaaa, 0x80); + FLASH0_WRITE (dev, 0xaaa, 0xaa); + FLASH0_WRITE (dev, 0x555, 0x55); + FLASH0_WRITE (dev, addr, 0x30); + + return flashWait (dev, addr, 0xff, 1); +} + +/* + * Note: it takes about as long to flash all sectors together with Chip + * Erase as it does to flash them one at a time (about 30 seconds for 2 + * MB). Also since we want to be able to treat subsets of sectors as if + * they were complete devices, we don't use Chip Erase. + */ + +STATUS flashErase (flash_dev_t * dev) +{ + int sector; + + PRINTF ("flashErase: dev=%d sectors=%d\n", DEV_NO (dev), dev->sectors); + + if (flashCheck (dev) == ERROR) + return ERROR; + + for (sector = 0; sector < dev->sectors; sector++) { + if (flashEraseSector (dev, sector) == ERROR) + return ERROR; + } + return OK; +} + +/* + * Read and write bytes + */ + +STATUS flashRead (flash_dev_t * dev, int pos, char *buf, int len) +{ + int addr, words; + + PRINTF ("flashRead: dev=%d pos=0x%x buf=0x%x len=0x%x\n", + DEV_NO (dev), pos, (int) buf, len); + + if (flashCheck (dev) == ERROR) + return ERROR; + + if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { + printf ("flashRead: Position out of range " + "(dev: %d, pos: 0x%x, len: 0x%x)\n", + DEV_NO (dev), pos, len); + return ERROR; + } + + if (len == 0) + return OK; + + if (dev->bank == FLASH0_BANK) { + addr = pos; + words = len; + + PRINTF ("flashRead: memcpy(0x%x, 0x%x, 0x%x)\n", + (int) buf, (int) FLASH0_ADDR (dev, pos), len); + + memcpy (buf, FLASH0_ADDR (dev, addr), words); + + } + PRINTF ("flashRead: rv=OK\n"); + + return OK; +} + +STATUS flashWrite (flash_dev_t * dev, int pos, char *buf, int len) +{ + int addr, words; + + PRINTF ("flashWrite: dev=%d pos=0x%x buf=0x%x len=0x%x\n", + DEV_NO (dev), pos, (int) buf, len); + + if (flashCheck (dev) == ERROR) + return ERROR; + + if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { + printf ("flashWrite: Position out of range " + "(dev: %d, pos: 0x%x, len: 0x%x)\n", + DEV_NO (dev), pos, len); + return ERROR; + } + + if (len == 0) + return OK; + + if (dev->bank == FLASH0_BANK) { + unsigned char tmp; + + addr = pos; + words = len; + + while (words--) { + tmp = *buf; + if (~FLASH0_READ (dev, addr) & tmp) { + printf ("flashWrite: Attempt to program 0 to 1 " + "(dev: %d, addr: 0x%x, data: 0x%x)\n", + DEV_NO (dev), addr, tmp); + return ERROR; + } + FLASH0_WRITE (dev, 0xaaa, 0xaa); + FLASH0_WRITE (dev, 0x555, 0x55); + FLASH0_WRITE (dev, 0xaaa, 0xa0); + FLASH0_WRITE (dev, addr, tmp); + if (flashWait (dev, addr, tmp, 0) < 0) + return ERROR; + buf++; + addr++; + } + } + + PRINTF ("flashWrite: rv=OK\n"); + + return OK; +} + +/* + * flashWritable returns TRUE if a range contains all F's. + */ + +STATUS flashWritable (flash_dev_t * dev, int pos, int len) +{ + int addr, words; + int rv = ERROR; + + PRINTF ("flashWritable: dev=%d pos=0x%x len=0x%x\n", + DEV_NO (dev), pos, len); + + if (flashCheck (dev) == ERROR) + goto done; + + if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { + printf ("flashWritable: Position out of range " + "(dev: %d, pos: 0x%x, len: 0x%x)\n", + DEV_NO (dev), pos, len); + goto done; + } + + if (len == 0) { + rv = 1; + goto done; + } + + if (dev->bank == FLASH0_BANK) { + addr = pos; + words = len; + + while (words--) { + if (FLASH0_READ (dev, addr) != 0xff) { + rv = 0; + goto done; + } + addr++; + } + } + + rv = 1; + + done: + PRINTF ("flashWrite: rv=%d\n", rv); + return rv; +} + + +/* + * NOTE: the below code cannot run from FLASH!!! + */ +/*********************************************************************** + * + * Flash Diagnostics + * + ***********************************************************************/ + +STATUS flashDiag (flash_dev_t * dev) +{ + unsigned int *buf = 0; + int i, len, sector; + int rv = ERROR; + + if (flashCheck (dev) == ERROR) + return ERROR; + + printf ("flashDiag: Testing device %d, " + "base: 0x%x, %d sectors @ %d kB = %d kB\n", + DEV_NO (dev), dev->base, + dev->sectors, + 1 << (dev->lgSectorSize - 10), + dev->sectors << (dev->lgSectorSize - 10)); + + len = 1 << dev->lgSectorSize; + + printf ("flashDiag: Erasing\n"); + + if (flashErase (dev) == ERROR) { + printf ("flashDiag: Erase failed\n"); + goto done; + } + printf ("%d bytes requested ...\n", len); + buf = malloc (len); + printf ("allocated %d bytes ...\n", len); + if (buf == 0) { + printf ("flashDiag: Out of memory\n"); + goto done; + } + + /* + * Write unique counting pattern to each sector + */ + + for (sector = 0; sector < dev->sectors; sector++) { + printf ("flashDiag: Write sector %d\n", sector); + + for (i = 0; i < len / 4; i++) + buf[i] = sector << 24 | i; + + if (flashWrite (dev, + sector << dev->lgSectorSize, + (char *) buf, len) == ERROR) { + printf ("flashDiag: Write failed (dev: %d, sector: %d)\n", + DEV_NO (dev), sector); + goto done; + } + } + + /* + * Verify + */ + + for (sector = 0; sector < dev->sectors; sector++) { + printf ("flashDiag: Verify sector %d\n", sector); + + if (flashRead (dev, + sector << dev->lgSectorSize, + (char *) buf, len) == ERROR) { + printf ("flashDiag: Read failed (dev: %d, sector: %d)\n", + DEV_NO (dev), sector); + goto done; + } + + for (i = 0; i < len / 4; i++) { + if (buf[i] != (sector << 24 | i)) { + printf ("flashDiag: Verify error " + "(dev: %d, sector: %d, offset: 0x%x)\n", + DEV_NO (dev), sector, i); + printf ("flashDiag: Expected 0x%08x, got 0x%08x\n", + sector << 24 | i, buf[i]); + + goto done; + } + } + } + + printf ("flashDiag: Erasing\n"); + + if (flashErase (dev) == ERROR) { + printf ("flashDiag: Final erase failed\n"); + goto done; + } + + rv = OK; + + done: + if (buf) + free (buf); + + if (rv == OK) + printf ("flashDiag: Device %d passed\n", DEV_NO (dev)); + else + printf ("flashDiag: Device %d failed\n", DEV_NO (dev)); + + return rv; +} + +STATUS flashDiagAll (void) +{ + int i; + int rv = OK; + + PRINTF ("flashDiagAll: devices=%d\n", flashDevCount); + + for (i = 0; i < flashDevCount; i++) { + flash_dev_t *dev = &flashDev[i]; + + if (dev->found && flashDiag (dev) == ERROR) + rv = ERROR; + } + + if (rv == OK) + printf ("flashDiagAll: Passed\n"); + else + printf ("flashDiagAll: Failed because of earlier errors\n"); + + return OK; +} + + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + flash_dev_t *dev = NULL; + + flashLibInit (); + + /* + * Provide info for FLASH (up to 960K) of Kernel Image data. + */ + dev = FLASH_DEV_BANK0_LOW; + flash_info[FLASH_BANK_KERNEL].flash_id = + (dev->vendorID << 16) | dev->deviceID; + flash_info[FLASH_BANK_KERNEL].sector_count = dev->sectors; + flash_info[FLASH_BANK_KERNEL].size = + flash_info[FLASH_BANK_KERNEL].sector_count * FLASH_SECTOR_SIZE; + flash_info[FLASH_BANK_KERNEL].start[FIRST_SECTOR] = dev->base; + size += flash_info[FLASH_BANK_KERNEL].size; + + /* + * Provide info for 512K PLCC FLASH ROM (U-Boot) + */ + dev = FLASH_DEV_BANK0_BOOT; + flash_info[FLASH_BANK_BOOT].flash_id = + (dev->vendorID << 16) | dev->deviceID; + flash_info[FLASH_BANK_BOOT].sector_count = dev->sectors; + flash_info[FLASH_BANK_BOOT].size = + flash_info[FLASH_BANK_BOOT].sector_count * FLASH_SECTOR_SIZE; + flash_info[FLASH_BANK_BOOT].start[FIRST_SECTOR] = dev->base; + size += flash_info[FLASH_BANK_BOOT].size; + + + /* + * Provide info for 512K FLASH0 segment (U-Boot) + */ + dev = FLASH_DEV_BANK0_HIGH; + flash_info[FLASH_BANK_AUX].flash_id = + (dev->vendorID << 16) | dev->deviceID; + flash_info[FLASH_BANK_AUX].sector_count = dev->sectors; + flash_info[FLASH_BANK_AUX].size = + flash_info[FLASH_BANK_AUX].sector_count * FLASH_SECTOR_SIZE; + flash_info[FLASH_BANK_AUX].start[FIRST_SECTOR] = dev->base; + size += flash_info[FLASH_BANK_AUX].size; + + + return size; +} + +/* + * Get flash device from U-Boot flash info. + */ +flash_dev_t *getFlashDevFromInfo (flash_info_t * info) +{ + int i; + + if (!info) + return NULL; + + for (i = 0; i < flashDevCount; i++) { + flash_dev_t *dev = &flashDev[i]; + + if (dev->found && (dev->base == info->start[0])) + return dev; + } + printf ("ERROR: notice, no FLASH mapped at address 0x%x\n", + (unsigned int) info->start[0]); + return NULL; +} + +ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + int i; + + for (i = 0; i < flashDevCount; i++) { + flash_dev_t *dev = &flashDev[i]; + + if (dev->found) { + if (dev->base == (unsigned int) addr) { + info->flash_id = (dev->vendorID << 16) | dev->deviceID; + info->sector_count = dev->sectors; + info->size = info->sector_count * FLASH_SECTOR_SIZE; + return dev->sectors * FLASH_SECTOR_SIZE; + } + } + } + return 0; +} + +void flash_print_info (flash_info_t * info) +{ + int i; + unsigned int chip; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case 0x1: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + chip = (unsigned int) info->flash_id & 0x000000ff; + + switch (chip) { + + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + + case AMD_ID_LV160B: + case FLASH_AM160LV: + case 0x49: + printf ("AM29LV160B (16 Mbit / 2M x 8bit)\n"); + break; + + default: + printf ("Unknown Chip Type:0x%x\n", chip); + break; + } + + printf (" Size: %ld bytes in %d Sectors\n", + info->size, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[FIRST_SECTOR] + i * FLASH_SECTOR_SIZE, + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + + +/* + * Erase a range of flash sectors. + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + vu_long *addr = (vu_long *) (info->start[0]); + int prot, sect, l_sect; + flash_dev_t *dev = NULL; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Start erase on unprotected sectors */ + dev = getFlashDevFromInfo (info); + if (dev) { + printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors); + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long *) (dev->base); + /* printf("erase_sector: sector=%d, addr=0x%x\n", + sect, addr); */ + printf ("."); + if (ERROR == flashEraseSector (dev, sect)) { + printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name); + return 1; + } + } + } + } + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + + flash_dev_t *dev = getFlashDevFromInfo (info); + int addr = dest - info->start[0]; + + if (!dev) + return 1; + + if (OK != flashWrite (dev, addr, (char *) &data, sizeof (ulong))) { + printf ("ERROR: could not write to addr=0x%x, data=0x%x\n", + (unsigned int) addr, (unsigned) data); + return 1; + } + + if ((addr % FLASH_SECTOR_SIZE) == 0) + printf ("."); + + + PRINTF ("write_word:0x%x, base=0x%x, addr=0x%x, data=0x%x\n", + (unsigned) info->start[0], + (unsigned) dest, + (unsigned) (dest - info->start[0]), (unsigned) data); + + return (0); +} + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + flash_dev_t *dev = getFlashDevFromInfo (info); + + if (dev) { + printf ("FLASH[%s]:", dev->name); + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); + } + return 1; +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/mousse/flash.h b/board/mousse/flash.h new file mode 100644 index 0000000..b7e4619 --- /dev/null +++ b/board/mousse/flash.h @@ -0,0 +1,78 @@ +#ifndef FLASH_LIB_H +#define FLASH_LIB_H + +#include + +/* PIO operations max */ +#define FLASH_PROGRAM_POLLS 100000 + +/* 10 Seconds default */ +#define FLASH_ERASE_SECTOR_TIMEOUT (10*1000 /*SEC*/ ) + +/* Flash device info structure */ +typedef struct flash_dev_s { + char name[24]; /* Bank Name */ + int bank; /* Bank 0 or 1 */ + unsigned int base; /* Base address */ + int sectors; /* Sector count */ + int lgSectorSize; /* Log2(usable bytes/sector) */ + int vendorID; /* Expected vendor ID */ + int deviceID; /* Expected device ID */ + int found; /* Set if found by flashLibInit */ + int swap; /* Set for bank 1 if byte swap req'd */ +} flash_dev_t; + +#define FLASH_MAX_POS(dev) \ + ((dev)->sectors << (dev)->lgSectorSize) + +#define FLASH_SECTOR_POS(dev, sector) \ + ((sector) << (dev)->lgSectorSize) + +/* AMD 29F040 */ +#define FLASH0_BANK 0 +#define FLASH0_VENDOR_ID 0x01 +#define FLASH0_DEVICE_ID 0x49 + +/* AMD29LV160DB */ +#define FLASH1_BANK 1 +#define FLASH1_VENDOR_ID 0x0001 +#define FLASH1_DEVICE_ID 0x2249 + +extern flash_dev_t flashDev[]; +extern int flashDevCount; + +/* + * Device pointers + * + * These must be kept in sync with the table in flashLib.c. + */ +#define FLASH_DEV_BANK0_SA0 (&flashDev[0]) +#define FLASH_DEV_BANK0_SA1 (&flashDev[1]) +#define FLASH_DEV_BANK0_SA2 (&flashDev[2]) +#define FLASH_DEV_BANK0_LOW (&flashDev[3]) /* 960K */ +#define FLASH_DEV_BANK0_BOOT (&flashDev[4]) /* PLCC */ +#define FLASH_DEV_BANK0_HIGH (&flashDev[5]) /* 512K PLCC shadow */ + +unsigned long flash_init(void); +int flashEraseSector(flash_dev_t *dev, int sector); +int flashErase(flash_dev_t *dev); +int flashRead(flash_dev_t *dev, int pos, char *buf, int len); +int flashWrite(flash_dev_t *dev, int pos, char *buf, int len); +int flashWritable(flash_dev_t *dev, int pos, int len); +int flashDiag(flash_dev_t *dev); +int flashDiagAll(void); + +ulong flash_get_size (vu_long *addr, flash_info_t *info); +void flash_print_info (flash_info_t *info); +int flash_erase (flash_info_t *info, int s_first, int s_last); +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); + +/* + * Flash info indices. + */ +#define FLASH_BANK_KERNEL 0 +#define FLASH_BANK_BOOT 1 +#define FLASH_BANK_AUX 2 +#define FIRST_SECTOR 0 + +#endif /* !FLASH_LIB_H */ diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c new file mode 100644 index 0000000..37a6244 --- /dev/null +++ b/board/mousse/m48t59y.c @@ -0,0 +1,322 @@ +/* + * SGS M48-T59Y TOD/NVRAM Driver + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. + * + * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * SGS M48-T59Y TOD/NVRAM Driver + * + * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and + * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD) + * registers which are used to set/get the internal date/time functions. + * + * This module implements Y2K compliance by taking full year numbers + * and translating back and forth from the TOD 2-digit year. + * + * NOTE: for proper interaction with an operating system, the TOD should + * be used to store Universal Coordinated Time (GMT) and timezone + * conversions should be used. + * + * Here is a diagram of the memory layout: + * + * +---------------------------------------------+ 0xffe0a000 + * | Non-volatile memory | . + * | | . + * | (8176 bytes of Non-volatile memory) | . + * | | . + * +---------------------------------------------+ 0xffe0bff0 + * | Flags | + * +---------------------------------------------+ 0xffe0bff1 + * | Unused | + * +---------------------------------------------+ 0xffe0bff2 + * | Alarm Seconds | + * +---------------------------------------------+ 0xffe0bff3 + * | Alarm Minutes | + * +---------------------------------------------+ 0xffe0bff4 + * | Alarm Date | + * +---------------------------------------------+ 0xffe0bff5 + * | Interrupts | + * +---------------------------------------------+ 0xffe0bff6 + * | WatchDog | + * +---------------------------------------------+ 0xffe0bff7 + * | Calibration | + * +---------------------------------------------+ 0xffe0bff8 + * | Seconds | + * +---------------------------------------------+ 0xffe0bff9 + * | Minutes | + * +---------------------------------------------+ 0xffe0bffa + * | Hours | + * +---------------------------------------------+ 0xffe0bffb + * | Day | + * +---------------------------------------------+ 0xffe0bffc + * | Date | + * +---------------------------------------------+ 0xffe0bffd + * | Month | + * +---------------------------------------------+ 0xffe0bffe + * | Year (2 digits only) | + * +---------------------------------------------+ 0xffe0bfff + */ +#include +#include +#include "mousse.h" + +/* + * Imported from mousse.h: + * + * TOD_REG_BASE Base of m48t59y TOD registers + * SYS_TOD_UNPROTECT() Disable NVRAM write protect + * SYS_TOD_PROTECT() Re-enable NVRAM write protect + */ + +#define YEAR 0xf +#define MONTH 0xe +#define DAY 0xd +#define DAY_OF_WEEK 0xc +#define HOUR 0xb +#define MINUTE 0xa +#define SECOND 0x9 +#define CONTROL 0x8 +#define WATCH 0x7 +#define INTCTL 0x6 +#define WD_DATE 0x5 +#define WD_HOUR 0x4 +#define WD_MIN 0x3 +#define WD_SEC 0x2 +#define _UNUSED 0x1 +#define FLAGS 0x0 + +#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE) + +int m48_tod_init(void) +{ + SYS_TOD_UNPROTECT(); + + M48_ADDR[CONTROL] = 0; + M48_ADDR[WATCH] = 0; + M48_ADDR[INTCTL] = 0; + + /* + * If the oscillator is currently stopped (as on a new part shipped + * from the factory), start it running. + * + * Here is an example of the TOD bytes on a brand new M48T59Y part: + * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01 + */ + + if (M48_ADDR[SECOND] & 0x80) + M48_ADDR[SECOND] = 0; + + /* Is battery low */ + if ( M48_ADDR[FLAGS] & 0x10) { + printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n"); + } + + SYS_TOD_PROTECT(); + + return 0; +} + +/* + * m48_tod_set + */ + +static int to_bcd(int value) +{ + return value / 10 * 16 + value % 10; +} + +static int from_bcd(int value) +{ + return value / 16 * 10 + value % 16; +} + +static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */ +{ + static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; + y -= m < 3; + return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7; +} + +/* + * Note: the TOD should store the current GMT + */ + +int m48_tod_set(int year, /* 1980-2079 */ + int month, /* 01-12 */ + int day, /* 01-31 */ + int hour, /* 00-23 */ + int minute, /* 00-59 */ + int second) /* 00-59 */ + +{ + SYS_TOD_UNPROTECT(); + + M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */ + + M48_ADDR[YEAR] = to_bcd(year % 100); + M48_ADDR[MONTH] = to_bcd(month); + M48_ADDR[DAY] = to_bcd(day); + M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1; + M48_ADDR[HOUR] = to_bcd(hour); + M48_ADDR[MINUTE] = to_bcd(minute); + M48_ADDR[SECOND] = to_bcd(second); + + M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */ + + SYS_TOD_PROTECT(); + + return 0; +} + +/* + * Note: the TOD should store the current GMT + */ + +int m48_tod_get(int *year, /* 1980-2079 */ + int *month, /* 01-12 */ + int *day, /* 01-31 */ + int *hour, /* 00-23 */ + int *minute, /* 00-59 */ + int *second) /* 00-59 */ +{ + int y; + + SYS_TOD_UNPROTECT(); + + M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */ + + y = from_bcd(M48_ADDR[YEAR]); + *year = y < 80 ? 2000 + y : 1900 + y; + *month = from_bcd(M48_ADDR[MONTH]); + *day = from_bcd(M48_ADDR[DAY]); + /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */ + *hour = from_bcd(M48_ADDR[HOUR]); + *minute = from_bcd(M48_ADDR[MINUTE]); + *second = from_bcd(M48_ADDR[SECOND] & 0x7f); + + M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */ + + SYS_TOD_PROTECT(); + + return 0; +} + +int m48_tod_get_second(void) +{ + return from_bcd(M48_ADDR[SECOND] & 0x7f); +} + +/* + * Watchdog function + * + * If usec is 0, the watchdog timer is disarmed. + * + * If usec is non-zero, the watchdog timer is armed (or re-armed) for + * approximately usec microseconds (if the exact requested usec is + * not supported by the chip, the next higher available value is used). + * + * Minimum watchdog timeout = 62500 usec + * Maximum watchdog timeout = 124 sec (124000000 usec) + */ + +void m48_watchdog_arm(int usec) +{ + int mpy, res; + + SYS_TOD_UNPROTECT(); + + if (usec == 0) { + res = 0; + mpy = 0; + } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */ + res = 0; + mpy = (usec + 62499) / 62500; + } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */ + res = 1; + mpy = (usec + 249999) / 250000; + } else if (usec < 32000000) { /* Resolution: 1s if below 32s */ + res = 2; + mpy = (usec + 999999) / 1000000; + } else { /* Resolution: 4s up to 124s */ + res = 3; + mpy = (usec + 3999999) / 4000000; + if (mpy > 31) + mpy = 31; + } + + M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */ + mpy << 2 | + res); + + SYS_TOD_PROTECT(); +} + +/* + * U-Boot RTC support. + */ +void +rtc_get( struct rtc_time *tmp ) +{ + m48_tod_get(&tmp->tm_year, + &tmp->tm_mon, + &tmp->tm_mday, + &tmp->tm_hour, + &tmp->tm_min, + &tmp->tm_sec); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + +#ifdef RTC_DEBUG + printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); +#endif +} + +void +rtc_set( struct rtc_time *tmp ) +{ + m48_tod_set(tmp->tm_year, /* 1980-2079 */ + tmp->tm_mon, /* 01-12 */ + tmp->tm_mday, /* 01-31 */ + tmp->tm_hour, /* 00-23 */ + tmp->tm_min, /* 00-59 */ + tmp->tm_sec); /* 00-59 */ + +#ifdef RTC_DEBUG + printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + +} + +void +rtc_reset (void) +{ + m48_tod_init(); +} diff --git a/board/mousse/m48t59y.h b/board/mousse/m48t59y.h new file mode 100644 index 0000000..717300d --- /dev/null +++ b/board/mousse/m48t59y.h @@ -0,0 +1,57 @@ +/* + * SGS M48-T59Y TOD/NVRAM Driver + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. + * + * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __M48_T59_Y_H +#define __M48_T59_Y_H + +/* + * M48 T59Y -Timekeeping Battery backed SRAM. + */ + +int m48_tod_init(void); + +int m48_tod_set(int year, + int month, + int day, + int hour, + int minute, + int second); + +int m48_tod_get(int *year, + int *month, + int *day, + int *hour, + int *minute, + int *second); + +int m48_tod_get_second(void); + +void m48_watchdog_arm(int usec); + +#endif /*!__M48_T59_Y_H */ diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c new file mode 100644 index 0000000..7208a17 --- /dev/null +++ b/board/mousse/mousse.c @@ -0,0 +1,86 @@ +/* + * MOUSSE Board Support + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * James Dougherty, jfd@cs.stanford.edu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "mousse.h" +#include "m48t59y.h" +#include + + +int checkboard (void) +{ + ulong busfreq = get_bus_freq (0); + char buf[32]; + + puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n"); + printf ("Built: %s at %s\n", __DATE__, __TIME__); + printf ("MPLD: Revision %d\n", SYS_REVID_GET ()); + printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); + + return 0; +} + +int checkflash (void) +{ + printf ("checkflash\n"); + flash_init (); + return 0; +} + +long int initdram (int board_type) +{ + return CFG_RAM_SIZE; +} + + +void get_tod (void) +{ + int year, month, day, hour, minute, second; + + m48_tod_get (&year, &month, &day, &hour, &minute, &second); + + printf (" Current date/time: %d/%d/%d %d:%d:%d \n", + month, day, year, hour, minute, second); + +} + +/* + * EPIC, PCI, and I/O devices. + * Initialize Mousse Platform, probe for PCI devices, + * Query configuration parameters if not set. + */ +int misc_init_f (void) +{ + m48_tod_init (); /* Init SGS M48T59Y TOD/NVRAM */ + printf ("RTC: M48T589 TOD/NVRAM (%d) bytes\n", TOD_NVRAM_SIZE); + get_tod (); + return 0; +} diff --git a/board/mousse/mousse.h b/board/mousse/mousse.h new file mode 100644 index 0000000..5468314 --- /dev/null +++ b/board/mousse/mousse.h @@ -0,0 +1,259 @@ +/* + * MOUSSE/MPC8240 Board definitions. + * For more info, see http://www.vooha.com/ + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * James Dougherty (jfd@cs.stanford.edu) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MOUSSE_H +#define __MOUSSE_H + +/* System addresses */ + +#define PCI_SPECIAL_BASE 0xfe000000 +#define PCI_SPECIAL_SIZE 0x01000000 + +/* PORTX Device Addresses for Mousse */ + +#define PORTX_DEV_BASE 0xff000000 +#define PORTX_DEV_SIZE 0x01000000 + +#define ENET_DEV_BASE 0x80000000 + +#define PLD_REG_BASE (PORTX_DEV_BASE | 0xe09000) +#define PLD_REG(off) (*(volatile unsigned char *) \ + (PLD_REG_BASE + (off))) + +#define PLD_REVID_B1 0x7f +#define PLD_REVID_B2 0x01 + +/* MPLD */ +#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */ +#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f) +#define SYS_LED_OFF() (PLD_REG(1) |= 0x80) +#define SYS_LED_ON() (PLD_REG(1) &= ~0x80) +#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80) +#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80) +#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80) +#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80) + +/* SGS M48T59Y */ +#define TOD_BASE (PORTX_DEV_BASE | 0xe0a000) +#define TOD_REG_BASE (TOD_BASE | 0x1ff0) +#define TOD_NVRAM_BASE TOD_BASE +#define TOD_NVRAM_SIZE 0x1ff0 +#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE) + +/* NS16552 SIO */ +#define SERIAL_BASE(_x) (PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80)) +#define N_SIO_CHANNELS 2 +#define N_COM_PORTS N_SIO_CHANNELS + +/* + * On-board Dec21143 PCI Ethernet + * Note: The PCI MBAR chosen here was used from MPC8240UM which states + * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS] + * is set, then PCI memory maps 1-1 with this address range in the + * correct byte order. + */ +#define PCI_ENET_IOADDR 0x80000000 +#define PCI_ENET_MEMADDR 0x80000000 + +/* + * Flash Memory Layout + * + * 2 MB Flash Bank 0 runs in 8-bit mode. In Flash Bank 0, the 32 kB + * sector SA3 is obscured by the 32 kB serial/TOD access space, and + * the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC + * containing the fixed boot ROM. (If the 512 kB PLCC is + * deconfigured by jumper, this window to Flash Bank 0 becomes + * visible, but it still contains the fixed boot code and should be + * considered read-only). Flash Bank 0 sectors SA0 (16 kB), SA1 (8 + * kB), and SA2 (8 kB) are currently unused. + * + * 2 MB Flash Bank 1 runs in 16-bit mode. Flash Bank 1 is fully + * usable, but it's a 16-bit wide device on a 64-bit bus. Therefore + * 16-bit words only exist at addresses that are multiples of 8. All + * PROM data and control addresses must be multiplied by 8. + * + * See flashMap.c for description of flash filesystem layout. + */ + +/* + * FLASH memory address space: 8-bit wide FLASH memory spaces. + */ +#define FLASH0_SEG0_START 0xffe00000 /* Baby 32Kb segment */ +#define FLASH0_SEG0_END 0xffe07fff /* 16 kB + 8 kB + 8 kB */ +#define FLASH0_SEG0_SIZE 0x00008000 /* (sectors SA0-SA2) */ + +#define FLASH0_SEG1_START 0xffe10000 /* 1MB - 64Kb FLASH0 seg */ +#define FLASH0_SEG1_END 0xffefffff /* 960 kB */ +#define FLASH0_SEG1_SIZE 0x000f0000 + +#define FLASH0_SEG2_START 0xfff00000 /* Boot Loader stored here */ +#define FLASH0_SEG2_END 0xfff7ffff /* 512 kB FLASH0/PLCC seg */ +#define FLASH0_SEG2_SIZE 0x00080000 + +#define FLASH0_SEG3_START 0xfff80000 /* 512 kB FLASH0 seg */ +#define FLASH0_SEG3_END 0xffffffff +#define FLASH0_SEG3_SIZE 0x00080000 + +/* Where Kahlua starts */ +#define FLASH_RESET_VECT 0xfff00100 + +/* + * CHRP / PREP (MAP A/B) definitions. + */ + +#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ +#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ +/* MPC107 (MPC8240 internal EUMBBAR mapped) */ +#define CHRP_REG_ADDR 0xfec00000 /* MPC106 Config, Map B */ +#define CHRP_REG_DATA 0xfee00000 /* MPC106 Config, Map B */ + +/* + * Mousse PCI IDSEL Assignments (Device Number) + */ +#define MOUSSE_IDSEL_ENET 13 /* On-board 21143 Ethernet */ +#define MOUSSE_IDSEL_LPCI 14 /* On-board PCI slot */ +#define MOUSSE_IDSEL_82371 15 /* That other thing */ +#define MOUSSE_IDSEL_CPCI2 31 /* CPCI slot 2 */ +#define MOUSSE_IDSEL_CPCI3 30 /* CPCI slot 3 */ +#define MOUSSE_IDSEL_CPCI4 29 /* CPCI slot 4 */ +#define MOUSSE_IDSEL_CPCI5 28 /* CPCI slot 5 */ +#define MOUSSE_IDSEL_CPCI6 27 /* CPCI slot 6 */ + +/* + * Mousse Interrupt Mapping: + * + * IRQ1 Enet (intA|intB|intC|intD) + * IRQ2 CPCI intA (See below) + * IRQ3 Local PCI slot intA|intB|intC|intD + * IRQ4 COM1 Serial port (Actually higher addressed port on duart) + * + * PCI Interrupt Mapping in CPCI chassis: + * + * | CPCI Slot + * | 1 (CPU) 2 3 4 5 6 + * -----------+--------+-------+-------+-------+-------+-------+ + * intA | X X X + * intB | X X X + * intC | X X X + * intD | X X X + */ + + +#define EPIC_VECTOR_EXT0 0 +#define EPIC_VECTOR_EXT1 1 +#define EPIC_VECTOR_EXT2 2 +#define EPIC_VECTOR_EXT3 3 +#define EPIC_VECTOR_EXT4 4 +#define EPIC_VECTOR_TM0 16 +#define EPIC_VECTOR_TM1 17 +#define EPIC_VECTOR_TM2 18 +#define EPIC_VECTOR_TM3 19 +#define EPIC_VECTOR_I2C 20 +#define EPIC_VECTOR_DMA0 21 +#define EPIC_VECTOR_DMA1 22 +#define EPIC_VECTOR_I2O 23 + + +#define INT_VEC_IRQ0 0 +#define INT_NUM_IRQ0 INT_VEC_IRQ0 +#define MOUSSE_IRQ_ENET EPIC_VECTOR_EXT1 /* Hardwired */ +#define MOUSSE_IRQ_CPCI EPIC_VECTOR_EXT2 /* Hardwired */ +#define MOUSSE_IRQ_LPCI EPIC_VECTOR_EXT3 /* Hardwired */ +#define MOUSSE_IRQ_DUART EPIC_VECTOR_EXT4 /* Hardwired */ + +/* Onboard DEC 21143 Ethernet */ +#define PCI_ENET_MEMADDR 0x80000000 +#define PCI_ENET_IOADDR 0x80000000 + +/* Some other PCI device */ +#define PCI_SLOT_MEMADDR 0x81000000 +#define PCI_SLOT_IOADDR 0x81000000 + +/* Promise ATA66 PCI Device (ATA controller) */ +#define PROMISE_MBAR0 0xa0000000 +#define PROMISE_MBAR1 (PROMISE_MBAR0 + 0x1000) +#define PROMISE_MBAR2 (PROMISE_MBAR0 + 0x2000) +#define PROMISE_MBAR3 (PROMISE_MBAR0 + 0x3000) +#define PROMISE_MBAR4 (PROMISE_MBAR0 + 0x4000) +#define PROMISE_MBAR5 (PROMISE_MBAR0 + 0x5000) + +/* ATA/66 Controller offsets */ +#define CFG_ATA_BASE_ADDR PROMISE_MBAR0 +#define CFG_IDE_MAXBUS 2 /* ide0/ide1 */ +#define CFG_IDE_MAXDEVICE 2 /* 2 drives per controller */ +#define CFG_ATA_IDE0_OFFSET 0 +#define CFG_ATA_IDE1_OFFSET 0x3000 +/* + * Definitions for accessing IDE controller registers + */ +#define CFG_ATA_DATA_OFFSET 0 +#define CFG_ATA_REG_OFFSET 0 +#define CFG_ATA_ALT_OFFSET (0x1000) + +/* + * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS + * are defined in config.h and Makefile. + * All definitions for these constants must be identical. + */ +#define ROM_BASE_ADRS 0xfff00000 /* base address of ROM */ +#define ROM_TEXT_ADRS (ROM_BASE_ADRS+0x0100) /* with PC & SP */ +#define ROM_WARM_ADRS (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */ +#define ROM_SIZE 0x00080000 /* 512KB ROM space */ +#define RAM_LOW_ADRS 0x00010000 /* RAM address for vxWorks */ +#define RAM_HIGH_ADRS 0x00c00000 /* RAM address for bootrom */ + +/* + * NVRAM configuration + * NVRAM is implemented via the SGS Thomson M48T59Y + * 64Kbit (8Kbx8) Timekeeper SRAM. + * This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information. + */ + +#define NV_RAM_ADRS TOD_NVRAM_BASE +#define NV_RAM_INTRVL 1 +#define NV_RAM_WR_ENBL SYS_TOD_UNPROTECT() +#define NV_RAM_WR_DSBL SYS_TOD_PROTECT() + +#define NV_OFF_BOOT0 0x0000 /* Boot string 0 (256b) */ +#define NV_OFF_BOOT1 0x0100 /* Boot string 1 (256b) */ +#define NV_OFF_BOOT2 0x0200 /* Boot string 2 (256b)*/ +#define NV_OFF_MACADDR 0x0400 /* 21143 MAC address (6b) */ +#define NV_OFF_ACTIVEBOOT 0x0406 /* Active boot string, 0 to 2 (1b) */ +#define NV_OFF_UNUSED1 0x0407 /* Unused (1b) */ +#define NV_OFF_BINDFIX 0x0408 /* See sysLib.c:sysBindFix() (1b) */ +#define NV_OFF_UNUSED2 0x0409 /* Unused (7b) */ +#define NV_OFF_TIMEZONE 0x0410 /* TIMEZONE env var (64b) */ +#define NV_OFF_VXWORKS_END 0x07FF /* 2047 VxWorks Total */ +#define NV_OFF_U_BOOT 0x0800 /* 2048 U-Boot boot-loader */ +#define NV_OFF_U_BOOT_ADDR (TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/ +#define NV_U_BOOT_ENV_SIZE 2048 /* 2K - U-Boot Total */ +#define NV_OFF__next_free (NV_U_BOOT_ENVSIZE +1) +#define NV_RAM_SIZE 8176 /* NVRAM End */ + +#endif /* __MOUSSE_H */ diff --git a/board/mousse/pci.c b/board/mousse/pci.c new file mode 100644 index 0000000..4f39398 --- /dev/null +++ b/board/mousse/pci.c @@ -0,0 +1,283 @@ +/* + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * James Dougherty (jfd@cs.stanford.edu) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge + */ +#include +#include +#include + +#include "mousse.h" + +/* + * Promise ATA/66 support. + */ +#define XFER_PIO_4 0x0C /* 0000|1100 */ +#define XFER_PIO_3 0x0B /* 0000|1011 */ +#define XFER_PIO_2 0x0A /* 0000|1010 */ +#define XFER_PIO_1 0x09 /* 0000|1001 */ +#define XFER_PIO_0 0x08 /* 0000|1000 */ +#define XFER_PIO_SLOW 0x00 /* 0000|0000 */ + +/* Promise Regs */ +#define REG_A 0x01 +#define REG_B 0x02 +#define REG_C 0x04 +#define REG_D 0x08 + +void +pdc202xx_decode_registers (unsigned char registers, unsigned char value) +{ + unsigned char bit = 0, bit1 = 0, bit2 = 0; + switch(registers) { + case REG_A: + bit2 = 0; + printf(" A Register "); + if (value & 0x80) printf("SYNC_IN "); + if (value & 0x40) printf("ERRDY_EN "); + if (value & 0x20) printf("IORDY_EN "); + if (value & 0x10) printf("PREFETCH_EN "); + if (value & 0x08) { printf("PA3 ");bit2 |= 0x08; } + if (value & 0x04) { printf("PA2 ");bit2 |= 0x04; } + if (value & 0x02) { printf("PA1 ");bit2 |= 0x02; } + if (value & 0x01) { printf("PA0 ");bit2 |= 0x01; } + printf("PIO(A) = %d ", bit2); + break; + case REG_B: + bit1 = 0;bit2 = 0; + printf(" B Register "); + if (value & 0x80) { printf("MB2 ");bit1 |= 0x80; } + if (value & 0x40) { printf("MB1 ");bit1 |= 0x40; } + if (value & 0x20) { printf("MB0 ");bit1 |= 0x20; } + printf("DMA(B) = %d ", bit1 >> 5); + if (value & 0x10) printf("PIO_FORCED/PB4 "); + if (value & 0x08) { printf("PB3 ");bit2 |= 0x08; } + if (value & 0x04) { printf("PB2 ");bit2 |= 0x04; } + if (value & 0x02) { printf("PB1 ");bit2 |= 0x02; } + if (value & 0x01) { printf("PB0 ");bit2 |= 0x01; } + printf("PIO(B) = %d ", bit2); + break; + case REG_C: + bit2 = 0; + printf(" C Register "); + if (value & 0x80) printf("DMARQp "); + if (value & 0x40) printf("IORDYp "); + if (value & 0x20) printf("DMAR_EN "); + if (value & 0x10) printf("DMAW_EN "); + + if (value & 0x08) { printf("MC3 ");bit2 |= 0x08; } + if (value & 0x04) { printf("MC2 ");bit2 |= 0x04; } + if (value & 0x02) { printf("MC1 ");bit2 |= 0x02; } + if (value & 0x01) { printf("MC0 ");bit2 |= 0x01; } + printf("DMA(C) = %d ", bit2); + break; + case REG_D: + printf(" D Register "); + break; + default: + return; + } + printf("\n %s ", (registers & REG_D) ? "DP" : + (registers & REG_C) ? "CP" : + (registers & REG_B) ? "BP" : + (registers & REG_A) ? "AP" : "ERROR"); + for (bit=128;bit>0;bit/=2) + printf("%s", (value & bit) ? "1" : "0"); + printf("\n"); +} + +/* + * Promise ATA/66 Support: configure Promise ATA66 card in specified mode. + */ +int +pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed) +{ + unsigned short drive_conf; + int err = 0; + unsigned char drive_pci, AP, BP, CP, DP; + unsigned char TA = 0, TB = 0; + + switch (drive) { + case 0: drive_pci = 0x60; break; + case 1: drive_pci = 0x64; break; + case 2: drive_pci = 0x68; break; + case 3: drive_pci = 0x6c; break; + default: return -1; + } + + pci_read_config_word(dev, drive_pci, &drive_conf); + pci_read_config_byte(dev, (drive_pci), &AP); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); + pci_read_config_byte(dev, (drive_pci)|0x02, &CP); + pci_read_config_byte(dev, (drive_pci)|0x03, &DP); + + if ((AP & 0x0F) || (BP & 0x07)) { + /* clear PIO modes of lower 8421 bits of A Register */ + pci_write_config_byte(dev, (drive_pci), AP & ~0x0F); + pci_read_config_byte(dev, (drive_pci), &AP); + + /* clear PIO modes of lower 421 bits of B Register */ + pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); + + pci_read_config_byte(dev, (drive_pci), &AP); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); + } + + pci_read_config_byte(dev, (drive_pci), &AP); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); + pci_read_config_byte(dev, (drive_pci)|0x02, &CP); + + switch(speed) { + case XFER_PIO_4: TA = 0x01; TB = 0x04; break; + case XFER_PIO_3: TA = 0x02; TB = 0x06; break; + case XFER_PIO_2: TA = 0x03; TB = 0x08; break; + case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; + case XFER_PIO_0: + default: TA = 0x09; TB = 0x13; break; + } + + pci_write_config_byte(dev, (drive_pci), AP|TA); + pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB); + + pci_read_config_byte(dev, (drive_pci), &AP); + pci_read_config_byte(dev, (drive_pci)|0x01, &BP); + pci_read_config_byte(dev, (drive_pci)|0x02, &CP); + pci_read_config_byte(dev, (drive_pci)|0x03, &DP); + + +#ifdef PDC202XX_DEBUG + pdc202xx_decode_registers(REG_A, AP); + pdc202xx_decode_registers(REG_B, BP); + pdc202xx_decode_registers(REG_C, CP); + pdc202xx_decode_registers(REG_D, DP); +#endif + return err; +} +/* + * Show/Init PCI devices on the specified bus number. + */ + +void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned int line; + + switch(PCI_DEV(dev)) { + case 0x0d: + line = 0x00000101; + break; + + case 0x0e: + default: + line = 0x00000303; + break; + } + + pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line); +} + +void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *_) +{ + unsigned short vendorId; + unsigned int mbar0, cmd; + int bar, a; + + pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId); + + if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){ + /* PDC 202xx card is handled differently, it is a bootable + * device and needs all 5 MBAR's configured + */ + for(bar = 0; bar < 5; bar++){ + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); +#ifdef DEBUG + printf(" ATA_bar[%d] = %dbytes\n", bar, + ~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1); +#endif + } + + /* Program all BAR's */ + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, PROMISE_MBAR2); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, PROMISE_MBAR3); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, PROMISE_MBAR4); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, PROMISE_MBAR5); + + for(bar = 0; bar < 5; bar++){ + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); +#ifdef DEBUG + printf(" ATA_bar[%d]@0x%x\n", bar, mbar0); +#endif + } + + /* Enable ROM Expansion base */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1); + + /* Io enable, Memory enable, master enable */ + pci_read_config_dword(dev, PCI_COMMAND, &cmd); + cmd &= ~0xffff0000; + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config_dword(dev, PCI_COMMAND, cmd); + + /* Breath some life into the controller */ + for( a = 0; a < 4; a++) + pdc202xx_tune_chipset(dev, a, XFER_PIO_0); + } +} + +static struct pci_config_table pci_sandpoint_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00, + pci_mousse_setup_pdc202xx }, +#ifndef CONFIG_PCI_PNP + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00, + pci_cfgfunc_config_device, {PCI_ENET_IOADDR, + PCI_ENET_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_SLOT_IOADDR, + PCI_SLOT_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, +#endif + { } +}; + +struct pci_controller hose = { + config_table: pci_sandpoint_config_table, + fixup_irq: pci_mousse_fixup_irq, +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds new file mode 100644 index 0000000..57358b8 --- /dev/null +++ b/board/mousse/u-boot.lds @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram new file mode 100644 index 0000000..eb47ae6 --- /dev/null +++ b/board/mousse/u-boot.lds.ram @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems Ltd. robt@flyingpig.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); + +MEMORY { + ram (!rx) : org = 0x00000000 , LENGTH = 8M + code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000) + rom (rx) : org = 0xfff00000 , LENGTH = 512K +} + +SECTIONS +{ + _f_init = .; + PROVIDE(_f_init = .); + _f_init_rom = .; + PROVIDE(_f_init_rom = .); + + .init : { + cpu/mpc824x/start.o (.text) + *(.init) + } > ram + _init_size = SIZEOF(.init); + PROVIDE(_init_size = SIZEOF(.init)); + + ENTRY(_start) + +/* _ftext = .; + _ftext_rom = .; + _text_size = SIZEOF(.text); + */ + .text : { + *(.text) + *(.got1) + } > ram + .rodata : { *(.rodata) } > ram + .dtors : { *(.dtors) } > ram + .data : { *(.data) } > ram + .sdata : { *(.sdata) } > ram + .sdata2 : { *(.sdata2) + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } > ram + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .sbss : { *(.sbss) } > ram + .sbss2 : { *(.sbss2) } > ram + .bss : { *(.bss) } > ram + .debug : { *(.debug) } > ram + .line : { *(.line) } > ram + .symtab : { *(.symtab) } > ram + .shrstrtab : { *(.shstrtab) } > ram + .strtab : { *(.strtab) } > ram + /* .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } > ram + */ + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } > ram + __stop___ex_table = .; + + + .ppcenv : + { + common/environment.o (.ppcenv) + } > ram + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom new file mode 100644 index 0000000..5a5722e --- /dev/null +++ b/board/mousse/u-boot.lds.rom @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + common/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mp2usb/Makefile b/board/mp2usb/Makefile new file mode 100644 index 0000000..b6ea3cf --- /dev/null +++ b/board/mp2usb/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := mp2usb.o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mp2usb/config.mk b/board/mp2usb/config.mk new file mode 100644 index 0000000..e299bfd --- /dev/null +++ b/board/mp2usb/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x27F00000 +## For testing: load at 0x20100000 and "go" at 0x201000A4 +#TEXT_BASE = 0x20100000 diff --git a/board/mp2usb/flash.c b/board/mp2usb/flash.c new file mode 100644 index 0000000..89ced16 --- /dev/null +++ b/board/mp2usb/flash.c @@ -0,0 +1,552 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified for the MP2USB by (C) Copyright 2005 Eric Benard + * ebenard@eukrea.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define CFG_MAX_FLASH_BANKS 1 +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_PROG 0x00400040 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_SUSPEND 0x00B000B0 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_RESET 0xFFFFFFFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0] ); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F640J3A: + printf ("28F640J3A\n"); + break; + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) INTEL_RESET; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) INTEL_RESET; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int prot, sect; + ulong type, start, last; + int rcode = 0; + int cflag, iflag; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + /* Disable interrupts which might cause a timeout here */ + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) INTEL_SUSPEND; /* suspend erase */ + *addr = (FPW) INTEL_RESET; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = (FPWV)INTEL_CLEAR; /* clear status register cmd. */ + *addr = (FPWV)INTEL_RESET; /* resest to read mode */ + + printf (" done\n"); + } + } + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + /* get lower word aligned address */ + wp = (addr & ~1); + port_width = 2; + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int cflag, iflag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + /* Disable interrupts which might cause a timeout here */ + iflag = disable_interrupts (); + + *addr = (FPW) INTEL_PROG; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +/*----------------------------------------------------------------------- + * Set/Clear sector's lock bit, returns: + * 0 - OK + * 1 - Error (timeout, voltage problems, etc.) + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int i; + int rc = 0; + FPWV *addr = (FPWV *)(info->start[sector]); + int flag = disable_interrupts(); + + *addr = (FPW) INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */ + *addr = (FPW) INTEL_PROTECT; /* set */ + } + else { /* Clear sector lock bit */ + *addr = (FPW) INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = (FPW) INTEL_CONFIRM; /* clear */ + } + + reset_timer_masked (); + + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + + if (*addr != (FPW) INTEL_OK) { + printf("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + rc = 1; + } + + if (!rc) + info->protect[sector] = prot; + + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + */ + if (!prot) + { + for (i = 0; i < info->sector_count; i++) + { + if (info->protect[i]) + { + reset_timer_masked (); + addr = (FPWV *) (info->start[i]); + *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */ + *addr = (FPW) INTEL_PROTECT; /* set */ + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) + { + if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) + { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + } + } + } + + if (flag) + enable_interrupts(); + + *addr = (FPW) INTEL_RESET; /* Reset to read array mode */ + + return rc; +} diff --git a/board/mp2usb/mp2usb.c b/board/mp2usb/mp2usb.c new file mode 100644 index 0000000..e75be1e --- /dev/null +++ b/board/mp2usb/mp2usb.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Modified for the MP2USB by (C) Copyright 2005 Eric Benard + * ebenard@eukrea.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Enable Ctrlc */ + console_init_f (); + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of MP2USB-Board. */ + gd->bd->bi_arch_number = MACH_TYPE_MP2USB; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_DRIVER_ETHER +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * at91rm9200_GetPhyInterface + * Description: + * Initialise the interface functions to the PHY + * Arguments: + * None + * Return value: + * None + */ +void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) +{ + p_phyops->Init = dm9161_InitPhy; + p_phyops->IsPhyConnected = dm9161_IsPhyConnected; + p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; + p_phyops->AutoNegotiate = dm9161_AutoNegotiate; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/mp2usb/u-boot.lds b/board/mp2usb/u-boot.lds new file mode 100644 index 0000000..76df6b2 --- /dev/null +++ b/board/mp2usb/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mpc8260ads/Makefile b/board/mpc8260ads/Makefile new file mode 100644 index 0000000..cc519d1 --- /dev/null +++ b/board/mpc8260ads/Makefile @@ -0,0 +1,47 @@ + +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8260ads/config.mk b/board/mpc8260ads/config.mk new file mode 100644 index 0000000..eb6f7c9 --- /dev/null +++ b/board/mpc8260ads/config.mk @@ -0,0 +1,37 @@ +# +# (C) Copyright 2001-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com +# +# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +endif diff --git a/board/mpc8260ads/flash.c b/board/mpc8260ads/flash.c new file mode 100644 index 0000000..59997aa --- /dev/null +++ b/board/mpc8260ads/flash.c @@ -0,0 +1,492 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Add support the Sharp chips on the mpc8260ads. + * I started with board/ip860/flash.c and made changes I found in + * the MTD project by David Schleef. + * + * (C) Copyright 2003 Arabella Software Ltd. + * Yuli Barcohen + * Re-written to support multi-bank flash SIMMs. + * Added support for real protection and JFFS2. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* Intel-compatible flash ID */ +#define INTEL_COMPAT 0x89898989 +#define INTEL_ALT 0xB0B0B0B0 + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x10101010 +#define INTEL_ERASE 0x20202020 +#define INTEL_CLEAR 0x50505050 +#define INTEL_LOCKBIT 0x60606060 +#define INTEL_PROTECT 0x01010101 +#define INTEL_STATUS 0x70707070 +#define INTEL_READID 0x90909090 +#define INTEL_CONFIRM 0xD0D0D0D0 +#define INTEL_RESET 0xFFFFFFFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x80808080 +#define INTEL_OK 0x80808080 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.) + * Up to 32MB of flash supported (up to 4 banks.) + * BCSR is used for flash presence detect (page 4-65 of the User's Manual) + * + * The following code can not run from flash! + */ +unsigned long flash_init (void) +{ + ulong size = 0, sect_start, sect_size = 0, bank_size; + ushort sect_count = 0; + int i, j, nbanks; + vu_long *addr = (vu_long *)CFG_FLASH_BASE; + vu_long *bcsr = (vu_long *)CFG_BCSR; + + switch (bcsr[2] & 0xF) { + case 0: + nbanks = 4; + break; + case 1: + nbanks = 2; + break; + case 2: + nbanks = 1; + break; + default: /* Unsupported configurations */ + nbanks = CFG_MAX_FLASH_BANKS; + } + + if (nbanks > CFG_MAX_FLASH_BANKS) + nbanks = CFG_MAX_FLASH_BANKS; + + for (i = 0; i < nbanks; i++) { + *addr = INTEL_READID; /* Read Intelligent Identifier */ + if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) { + switch (addr[1]) { + case SHARP_ID_28F016SCL: + case SHARP_ID_28F016SCZ: + flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + sect_count = 32; + sect_size = 0x40000; + break; + default: + flash_info[i].flash_id = FLASH_UNKNOWN; + sect_count = CFG_MAX_FLASH_SECT; + sect_size = + CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT; + } + } + else + flash_info[i].flash_id = FLASH_UNKNOWN; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n", + addr[0], addr[1], (ulong)addr); + size = 0; + *addr = INTEL_RESET; /* Reset bank to Read Array mode */ + break; + } + flash_info[i].sector_count = sect_count; + flash_info[i].size = bank_size = sect_size * sect_count; + size += bank_size; + sect_start = (ulong)addr; + for (j = 0; j < sect_count; j++) { + addr = (vu_long *)sect_start; + flash_info[i].start[j] = sect_start; + flash_info[i].protect[j] = (addr[2] == 0x01010101); + sect_start += sect_size; + } + *addr = INTEL_RESET; /* Reset bank to Read Array mode */ + addr = (vu_long *)sect_start; + } + + if (size == 0) { /* Unknown flash, fill with hard-coded values */ + sect_start = CFG_FLASH_BASE; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS; + flash_info[i].sector_count = sect_count; + for (j = 0; j < sect_count; j++) { + flash_info[i].start[j] = sect_start; + flash_info[i].protect[j] = 0; + sect_start += sect_size; + } + } + size = CFG_FLASH_SIZE; + } + else + for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = 0; + flash_info[i].sector_count = 0; + } + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_SHARP: printf ("Sharp "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); + break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; + case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) + && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + + last = start = get_timer (0); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Clear Status Register */ + *addr = INTEL_CLEAR; + /* Single Block Erase Command */ + *addr = INTEL_ERASE; + /* Confirm */ + *addr = INTEL_CONFIRM; + + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr = INTEL_CONFIRM; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = INTEL_RESET; /* reset bank */ + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + if (*addr != INTEL_OK) { + printf("Block erase failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + *addr = INTEL_RESET; /* reset bank */ + return 1; + } + + /* reset to read mode */ + *addr = INTEL_RESET; + } + } + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + ulong start; + int rc = 0; + int flag; + vu_long *addr = (vu_long *)dest; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + + *addr = INTEL_CLEAR; /* Clear status register */ + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = INTEL_PROGRAM; + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + printf("Write timed out\n"); + rc = 1; + break; + } + } + if (*addr != INTEL_OK) { + printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr); + rc = 1; + } + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + rc = write_word(info, wp, data); + + return rc; +} + +/*----------------------------------------------------------------------- + * Set/Clear sector's lock bit, returns: + * 0 - OK + * 1 - Error (timeout, voltage problems, etc.) + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + ulong start; + int i; + int rc = 0; + vu_long *addr = (vu_long *)(info->start[sector]); + int flag = disable_interrupts(); + + *addr = INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + } + else { /* Clear sector lock bit */ + *addr = INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = INTEL_CONFIRM; /* clear */ + } + + start = get_timer(0); + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + + if (*addr != INTEL_OK) { + printf("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + rc = 1; + } + + if (!rc) + info->protect[sector] = prot; + + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + */ + if (!prot) + for (i = 0; i < info->sector_count; i++) + if (info->protect[i]) { + addr = (vu_long *)(info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + udelay(CFG_FLASH_LOCK_TOUT * 1000); + } + + if (flag) + enable_interrupts(); + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c new file mode 100644 index 0000000..93550e2 --- /dev/null +++ b/board/mpc8260ads/mpc8260ads.c @@ -0,0 +1,546 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified during 2001 by + * Advanced Communications Technologies (Australia) Pty. Ltd. + * Howard Walker, Tuong Vu-Dinh + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Added support for the 16M dram simm on the 8260ads boards + * + * (C) Copyright 2003-2004 Arabella Software Ltd. + * Yuli Barcohen + * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init. + * + * Copyright (c) 2005 MontaVista Software, Inc. + * Vitaly Bordug + * Added support for PCI. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_PCI +#include +#endif + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3) + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */ + /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */ + /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ +#if CONFIG_ADSTYPE == CFG_8272ADS + /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */ + /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */ +#else + /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ +#if CONFIG_ADSTYPE == CFG_8272ADS + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ +#else + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +void reset_phy (void) +{ + vu_long *bcsr = (vu_long *)CFG_BCSR; + + /* Reset the PHY */ +#if CFG_PHY_ADDR == 0 + bcsr[1] &= ~(FETHIEN1 | FETH1_RST); + udelay(2); + bcsr[1] |= FETH1_RST; +#else + bcsr[3] &= ~(FETHIEN2 | FETH2_RST); + udelay(2); + bcsr[3] |= FETH2_RST; +#endif /* CFG_PHY_ADDR == 0 */ + udelay(1000); +#ifdef CONFIG_MII +#if CONFIG_ADSTYPE >= CFG_PQ2FADS + /* + * Do not bypass Rx/Tx (de)scrambler (fix configuration error) + * Enable autonegotiation. + */ + bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610); + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#else + /* + * Ethernet PHY is configured (by means of configuration pins) + * to work at 10Mb/s only. We reconfigure it using MII + * to advertise all capabilities, including 100Mb/s, and + * restart autonegotiation. + */ + + /* Advertise all capabilities */ + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1); + + /* Do not bypass Rx/Tx (de)scrambler */ + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000); + + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ +#endif /* CONFIG_MII */ +} + +#ifdef CONFIG_PCI +typedef struct pci_ic_s { + unsigned long pci_int_stat; + unsigned long pci_int_mask; +}pci_ic_t; +#endif + +int board_early_init_f (void) +{ + vu_long *bcsr = (vu_long *)CFG_BCSR; + +#ifdef CONFIG_PCI + volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT; + + /* mask alll the PCI interrupts */ + pci_ic->pci_int_mask |= 0xfff00000; +#endif +#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1) + bcsr[1] &= ~RS232EN_1; +#endif +#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1) + bcsr[1] &= ~RS232EN_2; +#endif + +#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */ +#if CONFIG_ADSTYPE == CFG_PQ2FADS + if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */ +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + { + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; + immap->im_siu_conf.sc_siumcr = + (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) + | SIUMCR_LBPC01; + } +#endif /* CONFIG_ADSTYPE != CFG_8260ADS */ + + return 0; +} + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) + +long int initdram (int board_type) +{ +#if CONFIG_ADSTYPE == CFG_PQ2FADS + long int msize = 32; +#elif CONFIG_ADSTYPE == CFG_8272ADS + long int msize = 64; +#else + long int msize = 16; +#endif + +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar *ramaddr, c = 0xff; + uint or; + uint psdmr; + uint psrt; + + int i; + + immap->im_siu_conf.sc_ppc_acr = 0x00000002; + immap->im_siu_conf.sc_ppc_alrh = 0x01267893; + immap->im_siu_conf.sc_tescr1 = 0x00004000; + + memctl->memc_mptpr = CFG_MPTPR; +#ifdef CFG_LSDRAM_BASE + /* + Initialise local bus SDRAM only if the pins + are configured as local bus pins and not as PCI. + The configuration is determined by the HRCW. + */ + if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { + memctl->memc_lsrt = CFG_LSRT; +#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */ + memctl->memc_or3 = 0xFF803280; + memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861; +#else /* CS4 */ + memctl->memc_or4 = 0xFFC01480; + memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; + ramaddr = (uchar *) CFG_LSDRAM_BASE; + *ramaddr = c; + memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; + for (i = 0; i < 8; i++) + *ramaddr = c; + memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; + *ramaddr = c; + memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; + } +#endif /* CFG_LSDRAM_BASE */ + + /* Init 60x bus SDRAM */ +#ifdef CONFIG_SPD_EEPROM + { + spd_eeprom_t spd; + uint pbi, bsel, rowst, lsb, tmp; + + i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd)); + + /* Bank-based interleaving is not supported for physical bank + sizes greater than 128MB which is encoded as 0x20 in SPD + */ + pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI; + msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */ + or = ~(msize - 1) << 20; /* SDAM */ + switch (spd.nbanks) { /* BPD */ + case 2: + bsel = 1; + break; + case 4: + bsel = 2; + or |= 0x00002000; + break; + case 8: + bsel = 3; + or |= 0x00004000; + break; + } + lsb = 3; /* For 64-bit port, lsb is 3 bits */ + + if (pbi) { /* Bus partition depends on interleaving */ + rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb); + or |= (rowst << 9); /* ROWST */ + } else { + rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb); + or |= ((rowst * 2 - 12) << 9); /* ROWST */ + } + or |= ((spd.nrow_addr - 9) << 6); /* NUMR */ + + psdmr = (pbi << 31); /* PBI */ + /* Bus multiplexing parameters */ + tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */ + psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */ + psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */ + + tmp = (31 - lsb - 10) - tmp; + /* Pin connected to SDA10 is (31 - lsb - 10). + rowst is multiplexed over (32 - (lsb + spd.nrow_addr)), + so (rowst + tmp) alternates with AP. + */ + if (pbi) /* Table 10-7 */ + psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */ + else + psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */ + + /* SDRAM device-specific parameters */ + tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */ + switch (tmp) { /* RFRC */ + case 1: + case 2: + psdmr |= (1 << 15); + break; + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + psdmr |= ((tmp - 2) << 15); + break; + default: + psdmr |= (7 << 15); + } + psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */ + psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */ + /* BL=0 because for 64-bit SDRAM burst length must be 4 */ + /* LDOTOPRE ??? */ + for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++) + tmp >>= 1; + switch (i) { /* WRC */ + case 0: + case 1: + psdmr |= (1 << 4); + break; + case 2: + case 3: + psdmr |= (i << 4); + break; + } + /* EAMUX=0 - no external address multiplexing */ + /* BUFCMD=0 - no external buffers */ + for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++) + tmp >>= 1; + psdmr |= i; /* CL */ + + switch (spd.refresh & 0x7F) { + case 1: + tmp = 3900; + break; + case 2: + tmp = 7800; + break; + case 3: + tmp = 31300; + break; + case 4: + tmp = 62500; + break; + case 5: + tmp = 125000; + break; + default: + tmp = 15625; + } + psrt = tmp / (1000000000 / CONFIG_8260_CLKIN * + ((memctl->memc_mptpr >> 8) + 1)) - 1; +#ifdef SPD_DEBUG + printf ("\nDIMM type: %-18.18s\n", spd.mpart); + printf ("SPD size: %d\n", spd.info_size); + printf ("EEPROM size: %d\n", 1 << spd.chip_size); + printf ("Memory type: %d\n", spd.mem_type); + printf ("Row addr: %d\n", spd.nrow_addr); + printf ("Column addr: %d\n", spd.ncol_addr); + printf ("# of rows: %d\n", spd.nrows); + printf ("Row density: %d\n", spd.row_dens); + printf ("# of banks: %d\n", spd.nbanks); + printf ("Data width: %d\n", + 256 * spd.dataw_msb + spd.dataw_lsb); + printf ("Chip width: %d\n", spd.primw); + printf ("Refresh rate: %02X\n", spd.refresh); + printf ("CAS latencies: %02X\n", spd.cas_lat); + printf ("Write latencies: %02X\n", spd.write_lat); + printf ("tRP: %d\n", spd.trp); + printf ("tRCD: %d\n", spd.trcd); + + printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt); +#endif /* SPD_DEBUG */ + } +#else /* !CONFIG_SPD_EEPROM */ + or = CFG_OR2; + psdmr = CFG_PSDMR; + psrt = CFG_PSRT; +#endif /* CONFIG_SPD_EEPROM */ + memctl->memc_psrt = psrt; + memctl->memc_or2 = or; + memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; + ramaddr = (uchar *) CFG_SDRAM_BASE; + memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */ + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */ + *ramaddr = c; +#endif /* CFG_RAMBOOT */ + + /* return total 60x bus SDRAM size */ + return (msize * 1024 * 1024); +} + +int checkboard (void) +{ +#if CONFIG_ADSTYPE == CFG_8260ADS + puts ("Board: Motorola MPC8260ADS\n"); +#elif CONFIG_ADSTYPE == CFG_8266ADS + puts ("Board: Motorola MPC8266ADS\n"); +#elif CONFIG_ADSTYPE == CFG_PQ2FADS + puts ("Board: Motorola PQ2FADS-ZU\n"); +#elif CONFIG_ADSTYPE == CFG_8272ADS + puts ("Board: Motorola MPC8272ADS\n"); +#else + puts ("Board: unknown\n"); +#endif + return 0; +} + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/mpc8260ads/u-boot.lds b/board/mpc8260ads/u-boot.lds new file mode 100644 index 0000000..bf8048d --- /dev/null +++ b/board/mpc8260ads/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/mpc8266ads/Makefile b/board/mpc8266ads/Makefile new file mode 100644 index 0000000..cd0f40b --- /dev/null +++ b/board/mpc8266ads/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8266ads/config.mk b/board/mpc8266ads/config.mk new file mode 100644 index 0000000..ecc2a7d --- /dev/null +++ b/board/mpc8266ads/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8260ads board +# + +TEXT_BASE = 0xfe000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/mpc8266ads/flash.c b/board/mpc8266ads/flash.c new file mode 100644 index 0000000..9512c72 --- /dev/null +++ b/board/mpc8266ads/flash.c @@ -0,0 +1,509 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Add support the Sharp chips on the mpc8260ads. + * I started with board/ip860/flash.c and made changes I found in + * the MTD project by David Schleef. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static int clear_block_lock_bit(vu_long * addr); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ +#ifndef CONFIG_MPC8266ADS + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; +#endif + unsigned long size; + int i; + + /* Init: enable write, + * or we cannot even write flash commands + */ +#ifndef CONFIG_MPC8266ADS + bcsr->bd_ctrl |= BD_CTRL_FLWE; +#endif + + + for (i=0; imemc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | + (memctl->memc_br1 & ~(BR_BA_MSK)); +#endif + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_SHARP: printf ("Sharp "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); + break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; + case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + ulong sector_offset; + + /* Write "Intelligent Identifier" command: read Manufacturer ID */ + *addr = 0x90909090; + + value = addr[0] & 0x00FF00FF; + switch (value) { + case MT_MANUFACT: /* SHARP, MT or => Intel */ + case INTEL_ALT_MANU: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + printf("unknown manufacturer: %x\n", (unsigned int)value); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case (INTEL_ID_28F016S): + info->flash_id += FLASH_28F016SV; + info->sector_count = 32; + info->size = 0x00400000; + sector_offset = 0x20000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F160S3): + info->flash_id += FLASH_28F160S3; + info->sector_count = 32; + info->size = 0x00400000; + sector_offset = 0x20000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F320S3): + info->flash_id += FLASH_28F320S3; + info->sector_count = 64; + info->size = 0x00800000; + sector_offset = 0x20000; + break; /* => 2x4 MB */ + + case SHARP_ID_28F016SCL: + case SHARP_ID_28F016SCZ: + info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + info->sector_count = 32; + info->size = 0x00800000; + sector_offset = 0x40000; + break; /* => 4x2 MB */ + + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += sector_offset; + /* don't know how to check sector protection */ + info->protect[i] = 0; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_long *)info->start[0]; + + *addr = 0xFFFFFF; /* reset bank to read array mode */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) + && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Make Sure Block Lock Bit is not set. */ + if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ + return 1; + } + + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + + last = start = get_timer (0); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Reset Array */ + *addr = 0xffffffff; + /* Clear Status Register */ + *addr = 0x50505050; + /* Single Block Erase Command */ + *addr = 0x20202020; + /* Confirm */ + *addr = 0xD0D0D0D0; + + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr = 0xD0D0D0D0; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + while ((*addr & 0x80808080) != 0x80808080) { + if(*addr & 0x20202020){ + printf("Error in Block Erase - Lock Bit may be set!\n"); + printf("Status Register = 0x%X\n", (uint)*addr); + *addr = 0xFFFFFFFF; /* reset bank */ + return 1; + } + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + /* reset to read mode */ + *addr = 0xFFFFFFFF; + } + } + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong start, csr; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = 0x10101010; + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + flag = 0; + while (((csr = *addr) & 0x80808080) != 0x80808080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x40404040) { + printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + + /* Clear Status Registers Command */ + *addr = 0x50505050; + /* Reset to read array mode */ + *addr = 0xFFFFFFFF; + + return (flag); +} + +/*----------------------------------------------------------------------- + * Clear Block Lock Bit, returns: + * 0 - OK + * 1 - Timeout + */ + +static int clear_block_lock_bit(vu_long * addr) +{ + ulong start, now; + + /* Reset Array */ + *addr = 0xffffffff; + /* Clear Status Register */ + *addr = 0x50505050; + + *addr = 0x60606060; + *addr = 0xd0d0d0d0; + + start = get_timer (0); + while(*addr != 0x80808080){ + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout on clearing Block Lock Bit\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + return 1; + } + } + return 0; +} diff --git a/board/mpc8266ads/mpc8266ads.c b/board/mpc8266ads/mpc8266ads.c new file mode 100644 index 0000000..8f7273c --- /dev/null +++ b/board/mpc8266ads/mpc8266ads.c @@ -0,0 +1,586 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified during 2001 by + * Advanced Communications Technologies (Australia) Pty. Ltd. + * Howard Walker, Tuong Vu-Dinh + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Added support for the 16M dram simm on the 8260ads boards + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* + * PBI Page Based Interleaving + * PSDMR_PBI page based interleaving + * 0 bank based interleaving + * External Address Multiplexing (EAMUX) adds a clock to address cycles + * (this can help with marginal board layouts) + * PSDMR_EAMUX adds a clock + * 0 no extra clock + * Buffer Command (BUFCMD) adds a clock to command cycles. + * PSDMR_BUFCMD adds a clock + * 0 no extra clock + */ +#define CONFIG_PBI 0 +#define PESSIMISTIC_SDRAM 0 +#define EAMUX 0 /* EST requires EAMUX */ +#define BUFCMD 0 + + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +typedef struct bscr_ { + unsigned long bcsr0; + unsigned long bcsr1; + unsigned long bcsr2; + unsigned long bcsr3; + unsigned long bcsr4; + unsigned long bcsr5; + unsigned long bcsr6; + unsigned long bcsr7; +} bcsr_t; + +typedef struct pci_ic_s { + unsigned long pci_int_stat; + unsigned long pci_int_mask; +} pci_ic_t; + +void reset_phy(void) +{ + volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; + + /* reset the FEC port */ + bcsr->bcsr1 &= ~FETH_RST; + bcsr->bcsr1 |= FETH_RST; +} + + +int board_early_init_f (void) +{ + volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; + volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT; + + bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; + + /* mask all PCI interrupts */ + pci_ic->pci_int_mask |= 0xfff00000; + + return 0; +} + +int checkboard(void) +{ + puts ("Board: Motorola MPC8266ADS\n"); + return 0; +} + +long int initdram(int board_type) +{ + /* Autoinit part stolen from board/sacsng/sacsng.c */ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0xff; + volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8); + uint psdmr = CFG_PSDMR; + int i; + + uint psrt = 0x21; /* for no SPD */ + uint chipselects = 1; /* for no SPD */ + uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CFG_OR2_PRELIM; /* for no SPD */ + uint data_width; + uint rows; + uint banks; + uint cols; + uint caslatency; + uint width; + uint rowst; + uint sdam; + uint bsma; + uint sda10; + u_char spd_size; + u_char data; + u_char cksum; + int j; + + /* Keep the compiler from complaining about potentially uninitialized vars */ + data_width = rows = banks = cols = caslatency = 0; + + /* + * Read the SDRAM SPD EEPROM via I2C. + */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); + spd_size = data; + cksum = data; + for(j = 1; j < 64; j++) + { /* read only the checksummed bytes */ + /* note: the I2C address autoincrements when alen == 0 */ + i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); + /*printf("addr %d = 0x%02x\n", j, data);*/ + if(j == 5) chipselects = data & 0x0F; + else if(j == 6) data_width = data; + else if(j == 7) data_width |= data << 8; + else if(j == 3) rows = data & 0x0F; + else if(j == 4) cols = data & 0x0F; + else if(j == 12) + { + /* + * Refresh rate: this assumes the prescaler is set to + * approximately 0.39uSec per tick and the target refresh period + * is about 85% of maximum. + */ + switch(data & 0x7F) + { + default: + case 0: psrt = 0x21; /* 15.625uS */ break; + case 1: psrt = 0x07; /* 3.9uS */ break; + case 2: psrt = 0x0F; /* 7.8uS */ break; + case 3: psrt = 0x43; /* 31.3uS */ break; + case 4: psrt = 0x87; /* 62.5uS */ break; + case 5: psrt = 0xFF; /* 125uS */ break; + } + } + else if(j == 17) banks = data; + else if(j == 18) + { + caslatency = 3; /* default CL */ +# if(PESSIMISTIC_SDRAM) + if((data & 0x04) != 0) caslatency = 3; + else if((data & 0x02) != 0) caslatency = 2; + else if((data & 0x01) != 0) caslatency = 1; +# else + if((data & 0x01) != 0) caslatency = 1; + else if((data & 0x02) != 0) caslatency = 2; + else if((data & 0x04) != 0) caslatency = 3; +# endif + else + { + printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", + data); + } + } + else if(j == 63) + { + if(data != cksum) + { + printf ("WARNING: Configuration data checksum failure:" + " is 0x%02x, calculated 0x%02x\n", + data, cksum); + } + } + cksum += data; + } + + /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ + if(caslatency < 2) { + printf("CL was %d, forcing to 2\n", caslatency); + caslatency = 2; + } + if(rows > 14) { + printf("This doesn't look good, rows = %d, should be <= 14\n", rows); + rows = 14; + } + if(cols > 11) { + printf("This doesn't look good, columns = %d, should be <= 11\n", cols); + cols = 11; + } + + if((data_width != 64) && (data_width != 72)) + { + printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", + data_width); + } + width = 3; /* 2^3 = 8 bytes = 64 bits wide */ + /* + * Convert banks into log2(banks) + */ + if (banks == 2) banks = 1; + else if(banks == 4) banks = 2; + else if(banks == 8) banks = 3; + + + sdram_size = 1 << (rows + cols + banks + width); + /* hack for high density memory (512MB per CS) */ + /* !!!!! Will ONLY work with Page Based Interleave !!!!! + ( PSDMR[PBI] = 1 ) + */ + /* mamory actually has 11 column addresses, but the memory controller + doesn't really care. + the calculations that follow will however move the rows so that + they are muxed one bit off if you use 11 bit columns. + The solution is to tell the memory controller the correct size of the memory + but change the number of columns to 10 afterwards. + The 11th column addre will still be mucxed correctly onto the bus. + + Also be aware that the MPC8266ADS board Rev B has not connected + Row addres 13 to anything. + + The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) + */ + if (cols > 10) + cols = 10; + +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + rowst = ((32 - 6) - (rows + cols + width)) * 2; +#else + rowst = 32 - (rows + banks + cols + width); +#endif + + or = ~(sdram_size - 1) | /* SDAM address mask */ + ((banks-1) << 13) | /* banks per device */ + (rowst << 9) | /* rowst */ + ((rows - 9) << 6); /* numr */ + + + /*printf("memctl->memc_or2 = 0x%08x\n", or);*/ + + /* + * SDAM specifies the number of columns that are multiplexed + * (reference AN2165/D), defined to be (columns - 6) for page + * interleave, (columns - 8) for bank interleave. + * + * BSMA is 14 - max(rows, cols). The bank select lines come + * into play above the highest "address" line going into the + * the SDRAM. + */ +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + sdam = cols - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam + 2; +#else + sdam = cols + banks - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam; +#endif +#if(PESSIMISTIC_SDRAM) + psdmr = (CONFIG_PBI |\ + PSDMR_RFEN |\ + PSDMR_RFRC_16_CLK |\ + PSDMR_PRETOACT_8W |\ + PSDMR_ACTTORW_8W |\ + PSDMR_WRC_4C |\ + PSDMR_EAMUX |\ + PSDMR_BUFCMD) |\ + caslatency |\ + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ + (sdam << 24) |\ + (bsma << 21) |\ + (sda10 << 18); +#else + psdmr = (CONFIG_PBI |\ + PSDMR_RFEN |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \ + PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \ + PSDMR_WRC_1C | /* 1 clock + 7nSec */ + EAMUX |\ + BUFCMD) |\ + caslatency |\ + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ + (sdam << 24) |\ + (bsma << 21) |\ + (sda10 << 18); +#endif + /*printf("psdmr = 0x%08x\n", psdmr);*/ + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * Quote from Micron MT48LC8M16A2 data sheet: + * + * "...the SDRAM requires a 100uS delay prior to issuing any + * command other than a COMMAND INHIBIT or NOP. Starting at some + * point during this 100uS period and continuing at least through + * the end of this period, COMMAND INHIBIT or NOP commands should + * be applied." + * + * "Once the 100uS delay has been satisfied with at least one COMMAND + * INHIBIT or NOP command having been applied, a /PRECHARGE command/ + * should be applied. All banks must then be precharged, thereby + * placing the device in the all banks idle state." + * + * "Once in the idle state, /two/ AUTO REFRESH cycles must be + * performed. After the AUTO REFRESH cycles are complete, the + * SDRAM is ready for mode register programming." + * + * (/emphasis/ mine, gvb) + * + * The way I interpret this, Micron start up sequence is: + * 1. Issue a PRECHARGE-BANK command (initial precharge) + * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") + * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands + * 4. Issue a MODE-SET command to initialize the mode register + * + * -------- + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = psrt; + + memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = or; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + + /* + * Do it a second time for the second set of chips if the DIMM has + * two chip selects (double sided). + */ + if(chipselects > 1) + { + ramaddr += sdram_size; + + memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size; + memctl->memc_or3 = or; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + } + + /* print info */ + printf("SDRAM configuration read from SPD\n"); + printf("\tSize per side = %dMB\n", sdram_size >> 20); + printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width); + printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency); +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + printf(", Using Bank Based Interleave\n"); +#else + printf(", Using Page Based Interleave\n"); +#endif + printf("\tTotal size: "); + + /* this delay only needed for original 16MB DIMM... + * Not needed for any other memory configuration */ + if ((sdram_size * chipselects) == (16 *1024 *1024)) + udelay (250000); + return (sdram_size * chipselects); + /*return (16 * 1024 * 1024);*/ +} + + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/mpc8266ads/u-boot.lds b/board/mpc8266ads/u-boot.lds new file mode 100644 index 0000000..2220758 --- /dev/null +++ b/board/mpc8266ads/u-boot.lds @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpc8349ads/Makefile b/board/mpc8349ads/Makefile new file mode 100644 index 0000000..4327b0d --- /dev/null +++ b/board/mpc8349ads/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8349ads/config.mk b/board/mpc8349ads/config.mk new file mode 100644 index 0000000..4602169 --- /dev/null +++ b/board/mpc8349ads/config.mk @@ -0,0 +1,27 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC83xxADS +# + +TEXT_BASE = 0xFE700000 diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c new file mode 100644 index 0000000..da8d3d7 --- /dev/null +++ b/board/mpc8349ads/mpc8349ads.c @@ -0,0 +1,276 @@ +/* + * Copyright Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PCI) +#include +#endif +#if defined(CONFIG_SPD_EEPROM) +#include +#endif +int fixed_sdram(void); +void sdram_init(void); + +int board_early_init_f (void) +{ + volatile u8* bcsr = (volatile u8*)CFG_BCSR; + + /* Enable flash write */ + bcsr[1] &= ~0x01; + + return 0; +} + + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) + +long int initdram (int board_type) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(NULL); +#else + msize = fixed_sdram(); +#endif + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size>>1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); +#if (CFG_DDR_SIZE != 256) +#warning Currenly any ddr size other than 256 is not supported +#endif + + im->ddr.csbnds[0].csbnds = 0x00100017; + im->ddr.csbnds[1].csbnds = 0x0018001f; + im->ddr.csbnds[2].csbnds = 0x00000007; + im->ddr.csbnds[3].csbnds = 0x0008000f; + im->ddr.cs_config[0] = CFG_DDR_CONFIG; + im->ddr.cs_config[1] = CFG_DDR_CONFIG; + im->ddr.cs_config[2] = CFG_DDR_CONFIG; + im->ddr.cs_config[3] = CFG_DDR_CONFIG; + im->ddr.timing_cfg_1 = + 3 << TIMING_CFG1_PRETOACT_SHIFT | + 7 << TIMING_CFG1_ACTTOPRE_SHIFT | + 3 << TIMING_CFG1_ACTTORW_SHIFT | + 4 << TIMING_CFG1_CASLAT_SHIFT | + 3 << TIMING_CFG1_REFREC_SHIFT | + 3 << TIMING_CFG1_WRREC_SHIFT | + 2 << TIMING_CFG1_ACTTOACT_SHIFT | + 1 << TIMING_CFG1_WRTORD_SHIFT; + im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT; + im->ddr.sdram_cfg = + SDRAM_CFG_SREN +#if defined(CONFIG_DDR_2T_TIMING) + | SDRAM_CFG_2T_EN +#endif + | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; + im->ddr.sdram_mode = + 0x2000 << SDRAM_MODE_ESD_SHIFT | + 0x0162 << SDRAM_MODE_SD_SHIFT; + + im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT | + 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT; + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} +#endif/*!CFG_SPD_EEPROM*/ + + +int checkboard (void) +{ + puts("Board: Freescale MPC8349ADS\n"); + return 0; +} + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxads_config_table[] = { + {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMON_MEMORY | PCI_COMMAND_MASTER + } }, + {} +} +#endif + + +volatile static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxads_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxads_config_table, +#endif + } +}; +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc83xx_init(volatile struct pci_controller *hose); + + pci_mpc83xx_init(hose); +#endif /* CONFIG_PCI */ +} + +/* + * if MPC8349ADS is soldered with SDRAM + */ +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void +sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile lbus8349_t *lbc= &immap->lbus; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts("\n SDRAM on Local Bus: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + + /*setup mtrpt, lsrt and lbcr for LB bus*/ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode Register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/ + + lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/ + asm("sync"); + /*1 times*/ + *sdram_addr = 0xff; + udelay(100); + /*2 times*/ + *sdram_addr = 0xff; + udelay(100); + /*3 times*/ + *sdram_addr = 0xff; + udelay(100); + /*4 times*/ + *sdram_addr = 0xff; + udelay(100); + /*5 times*/ + *sdram_addr = 0xff; + udelay(100); + /*6 times*/ + *sdram_addr = 0xff; + udelay(100); + /*7 times*/ + *sdram_addr = 0xff; + udelay(100); + /*8 times*/ + *sdram_addr = 0xff; + udelay(100); + + /* 0x58636733;mode register write operation */ + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); +} +#else +void +sdram_init(void) +{ + put("SDRAM on Local Bus is NOT available!\n"); +} +#endif diff --git a/board/mpc8349ads/u-boot.lds b/board/mpc8349ads/u-boot.lds new file mode 100644 index 0000000..020cfa6 --- /dev/null +++ b/board/mpc8349ads/u-boot.lds @@ -0,0 +1,122 @@ +/* + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/mpc8540ads/Makefile b/board/mpc8540ads/Makefile new file mode 100644 index 0000000..5d8ea34 --- /dev/null +++ b/board/mpc8540ads/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8540ads/config.mk b/board/mpc8540ads/config.mk new file mode 100644 index 0000000..92f8931 --- /dev/null +++ b/board/mpc8540ads/config.mk @@ -0,0 +1,33 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8540ads board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8540ads/init.S b/board/mpc8540ads/init.S new file mode 100644 index 0000000..242cb9f --- /dev/null +++ b/board/mpc8540ads/init.S @@ -0,0 +1,280 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xf8000000 16K BCSR registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) + .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + .long TLB1_MAS0(1, 8, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1, 9, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c new file mode 100644 index 0000000..d0eb690 --- /dev/null +++ b/board/mpc8540ads/mpc8540ads.c @@ -0,0 +1,344 @@ + /* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram(void); + + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts("Board: ADS\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + uint temp_ddrdll = 0; + + /* + * Work around to stabilize DDR DLL + */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); + } +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr(); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + + +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void +sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts(" SDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + lbc->br2 = CFG_BR2_PRELIM; + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("sync"); + + /* + * Configure the SDRAM controller. + */ + lbc->lsdmr = CFG_LBC_LSDMR_1; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_3; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ + #ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; + #if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + ddr->err_sbe = 0x00ff0000; + #endif + asm("sync;isync;msync"); + udelay(500); + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + asm("sync; isync; msync"); + udelay(500); + #endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/mpc8540ads/u-boot.lds b/board/mpc8540ads/u-boot.lds new file mode 100644 index 0000000..e7a88cf --- /dev/null +++ b/board/mpc8540ads/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2002,2003, Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/mpc8540ads/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/mpc8540ads/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile new file mode 100644 index 0000000..6f1995e --- /dev/null +++ b/board/mpc8540eval/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o +#OBJS := $(BOARD).o flash.o $(BOARD)_slave.o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8540eval/config.mk b/board/mpc8540eval/config.mk new file mode 100644 index 0000000..68271bd --- /dev/null +++ b/board/mpc8540eval/config.mk @@ -0,0 +1,34 @@ +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# gda8540 board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +#TEXT_BASE = 0x1000000 +TEXT_BASE = 0xfff80000 + + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c new file mode 100644 index 0000000..7300a04 --- /dev/null +++ b/board/mpc8540eval/flash.c @@ -0,0 +1,892 @@ +/* + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao,(X.Xiao@motorola.com) + * + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Add support the Sharp chips on the mpc8260ads. + * I started with board/ip860/flash.c and made changes I found in + * the MTD project by David Schleef. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if !defined(CFG_NO_FLASH) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/* + * The variable should be in the flash info structure. Since it + * is only used in this board specific file it is declared here. + * In the future I think an endian flag should be part of the + * flash_info_t structure. (Ron Alder) + */ +static ulong big_endian = 0; + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_block (flash_info_t *info, uchar * src, ulong dest, ulong cnt); +static int write_short (flash_info_t *info, ulong dest, ushort data); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static int clear_block_lock_bit(flash_info_t *info, vu_long * addr); +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: enable write, + * or we cannot even write flash commands + */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_SHARP: printf ("Sharp "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); + break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; + case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); + break; + case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + + /* only deal with 16 bit and 32 bit port width, 16bit chip */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value,va,vb,vc,vd; + ulong base = (ulong)addr; + ulong sector_offset; + +#ifdef DEBUG + printf("Check flash at 0x%08x\n",(uint)addr); +#endif + /* Write "Intelligent Identifier" command: read Manufacturer ID */ + *addr = 0x90909090; + udelay(20); + asm("sync"); + +#ifndef CFG_FLASH_CFI + printf("Not define CFG_FLASH_CFI\n"); + return (0); +#else + value = addr[0]; + va=(value & 0xFF000000)>>24; + vb=(value & 0x00FF0000)>>16; + vc=(value & 0x0000FF00)>>8; + vd=(value & 0x000000FF); + if ((va==0) && (vb==0)) { + printf("cannot identify Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + else if ((va==0) && (vb!=0)) { + big_endian = 1; + info->chipwidth = FLASH_CFI_BY16; + if(vb == vd) info->portwidth = FLASH_CFI_32BIT; + else info->portwidth = FLASH_CFI_16BIT; + } + else if ((va!=0) && (vb==0)) { + big_endian = 0; + info->chipwidth = FLASH_CFI_BY16; + if(va == vc) info->portwidth = FLASH_CFI_32BIT; + else info->portwidth = FLASH_CFI_16BIT; + } + else if ((va!=0) && (vb!=0)) { + big_endian = 1; /* no meaning for 8bit chip */ + info->chipwidth = FLASH_CFI_BY8; + if(va == vb) info->portwidth = FLASH_CFI_16BIT; + else info->portwidth = FLASH_CFI_8BIT; + } +#ifdef DEBUG + switch (info->portwidth) { + case FLASH_CFI_8BIT: + printf("port width is 8 bit.\n"); + break; + case FLASH_CFI_16BIT: + printf("port width is 16 bit, "); + break; + case FLASH_CFI_32BIT: + printf("port width is 32 bit, "); + break; + } + switch (info->chipwidth) { + case FLASH_CFI_BY16: + printf("chip width is 16 bit, "); + switch (big_endian) { + case 0: + printf("Little Endian.\n"); + break; + case 1: + printf("Big Endian.\n"); + break; + } + break; + } +#endif +#endif /*#ifdef CFG_FLASH_CFI*/ + + if (big_endian==0) value = (addr[0] & 0xFF000000) >>8; + else value = (addr[0] & 0x00FF0000); +#ifdef DEBUG + printf("manufacturer=0x%x\n",(uint)(value>>16)); +#endif + switch (value) { + case MT_MANUFACT & 0xFFFF0000: /* SHARP, MT or => Intel */ + case INTEL_ALT_MANU & 0xFFFF0000: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + printf("unknown manufacturer: %x\n", (unsigned int)value); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + if (info->portwidth==FLASH_CFI_16BIT) { + switch (big_endian) { + case 0: + value = (addr[0] & 0x0000FF00)>>8; + break; + case 1: + value = (addr[0] & 0x000000FF); + break; + } + } + else if (info->portwidth == FLASH_CFI_32BIT) { + switch (big_endian) { + case 0: + value = (addr[1] & 0x0000FF00)>>8; + break; + case 1: + value = (addr[1] & 0x000000FF); + break; + } + } + +#ifdef DEBUG + printf("deviceID=0x%x\n",(uint)value); +#endif + switch (value) { + case (INTEL_ID_28F016S & 0x0000FFFF): + info->flash_id += FLASH_28F016SV; + info->sector_count = 32; + sector_offset = 0x10000; + break; /* => 2 MB */ + + case (INTEL_ID_28F160S3 & 0x0000FFFF): + info->flash_id += FLASH_28F160S3; + info->sector_count = 32; + sector_offset = 0x10000; + break; /* => 2 MB */ + + case (INTEL_ID_28F320S3 & 0x0000FFFF): + info->flash_id += FLASH_28F320S3; + info->sector_count = 64; + sector_offset = 0x10000; + break; /* => 4 MB */ + + case (INTEL_ID_28F640J3A & 0x0000FFFF): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + sector_offset = 0x20000; + break; /* => 8 MB */ + + case SHARP_ID_28F016SCL & 0x0000FFFF: + case SHARP_ID_28F016SCZ & 0x0000FFFF: + info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + info->sector_count = 32; + sector_offset = 0x10000; + break; /* => 2 MB */ + + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + sector_offset = sector_offset * (info->portwidth / info->chipwidth); + info->size = info->sector_count * sector_offset; + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += sector_offset; + /* don't know how to check sector protection */ + info->protect[i] = 0; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_long *)info->start[0]; + *addr = 0xFFFFFF; /* reset bank to read array mode */ + asm("sync"); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last, ready, erase_err_status; + + if (big_endian == 1) { + ready = 0x0080; + erase_err_status = 0x00a0; + } + else { + ready = 0x8000; + erase_err_status = 0xa000; + } + if ((info->portwidth / info->chipwidth)==2) { + ready += (ready <<16); + erase_err_status += (erase_err_status <<16); + } + +#ifdef DEBUG + printf ("\nReady flag is 0x%lx\nErase error flag is 0x%lx", ready, erase_err_status); +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) + && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + +#ifdef DEBUG + printf("\nFlash Erase:\n"); +#endif + /* Make Sure Block Lock Bit is not set. */ + if(clear_block_lock_bit(info, (vu_long *)(info->start[s_first]))){ + return 1; + } + + /* Start erase on unprotected sectors */ +#if defined(DEBUG) + printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); +#endif + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr16 = (vu_short *)(info->start[sect]); + vu_long *addr = (vu_long *)(info->start[sect]); + printf("."); + switch (info->portwidth) { + case FLASH_CFI_16BIT: + asm("sync"); + last = start = get_timer (0); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + /* Reset Array */ + *addr16 = 0xffff; + asm("sync"); + /* Clear Status Register */ + *addr16 = 0x5050; + asm("sync"); + /* Single Block Erase Command */ + *addr16 = 0x2020; + asm("sync"); + /* Confirm */ + *addr16 = 0xD0D0; + asm("sync"); + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr16 = 0xD0D0; + asm("sync"); + } + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + /* wait at least 80us - let's wait 1 ms */ + *addr16 = 0x7070; + udelay (1000); + while ((*addr16 & ready) != ready) { + if((*addr16 & erase_err_status)== erase_err_status){ + printf("Error in Block Erase - Lock Bit may be set!\n"); + printf("Status Register = 0x%X\n", (uint)*addr16); + *addr16 = 0xFFFF; /* reset bank */ + asm("sync"); + return 1; + } + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr16 = 0xFFFF; /* reset bank */ + asm("sync"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + /* reset to read mode */ + *addr16 = 0xFFFF; + asm("sync"); + break; + case FLASH_CFI_32BIT: + asm("sync"); + last = start = get_timer (0); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + /* Single Block Erase Command */ + *addr = 0x20202020; + asm("sync"); + /* Confirm */ + *addr = 0xD0D0D0D0; + asm("sync"); + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr = 0xD0D0D0D0; + asm("sync"); + } + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + /* wait at least 80us - let's wait 1 ms */ + *addr = 0x70707070; + udelay (1000); + while ((*addr & ready) != ready) { + if((*addr & erase_err_status)==erase_err_status){ + printf("Error in Block Erase - Lock Bit may be set!\n"); + printf("Status Register = 0x%X\n", (uint)*addr); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + /* reset to read mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + break; + } /* end switch */ + } /* end if */ + } /* end for */ + + printf ("flash erase done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +#define FLASH_BLOCK_SIZE 32 + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data, count, temp; +/* ulong temp[FLASH_BLOCK_SIZE/4];*/ + int i, l, rc; + + count = cnt; + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + cp = wp; + /* handle unaligned block bytes , flash block size = 16bytes */ + wp = (cp+FLASH_BLOCK_SIZE-1) & ~(FLASH_BLOCK_SIZE-1); + if ((wp-cp)>=cnt) { + if ((rc = write_block(info,src,cp,wp-cp)) !=0) + return (rc); + src += wp-cp; + cnt -= wp-cp; + } + /* handle aligned block bytes */ + temp = 0; + printf("\n"); + while ( cnt >= FLASH_BLOCK_SIZE) { + if ((rc = write_block(info,src,cp,FLASH_BLOCK_SIZE)) !=0) { + return (rc); + } + src += FLASH_BLOCK_SIZE; + cp += FLASH_BLOCK_SIZE; + cnt -= FLASH_BLOCK_SIZE; + if (((count-cnt)>>10)>temp) { + temp=(count-cnt)>>10; + printf("\r%d KB",temp); + } + } + printf("\n"); + wp = cp; + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} +#undef FLASH_BLOCK_SIZE + +/*----------------------------------------------------------------------- + * Write block to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * -1 Error + */ +static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt) +{ + vu_short *baddr, *addr = (vu_short *)dest; + ushort data; + ulong start, now, xsr,csr, ready; + int flag; + + if (cnt==0) return 0; + else if(cnt != (cnt& ~1)) return -1; + + /* Check if Flash is (sufficiently) erased */ + data = * src; + data = (data<<8) | *(src+1); + if ((*addr & data) != data) { + return (2); + } + if (big_endian == 1) { + ready = 0x0080; + } + else { + ready = 0x8000; + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + do { + /* Write Command */ + *addr = 0xe8e8; + asm("sync"); + xsr = *addr; + asm("sync"); + } while (!(xsr & ready)); /*wait until read */ + /*write count=BLOCK SIZE -1 */ + data=(cnt>>1)-1; + data=(data<<8)|data; + *addr = data; /* word mode, cnt/2 */ + asm("sync"); + baddr = addr; + while(cnt) { + data = * src++; + data = (data<<8) | *src++; + asm("sync"); + *baddr = data; + asm("sync"); + ++baddr; + cnt = cnt -2; + } + *addr = 0xd0d0; /* confirm write */ + start = get_timer(0); + asm("sync"); + if (flag) + enable_interrupts(); + /* data polling for D7 */ + flag = 0; + while (((csr = *addr) & ready) != ready) { + if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x4040) { + printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + /* Clear Status Registers Command */ + *addr = 0x5050; + asm("sync"); + /* Reset to read array mode */ + *addr = 0xFFFF; + asm("sync"); + return (flag); +} + + +/*----------------------------------------------------------------------- + * Write a short word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_short (flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *)dest; + ulong start, now, csr, ready; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = 0x1010; + start = get_timer (0); + asm("sync"); + /* Write Data */ + *addr = data; + asm("sync"); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + if (big_endian == 1) { + ready = 0x0080; + } + else { + ready = 0x8000; + } + /* data polling for D7 */ + flag = 0; + while (((csr = *addr) & ready) != ready) { + if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x4040) { + printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + /* Clear Status Registers Command */ + *addr = 0x5050; + asm("sync"); + /* Reset to read array mode */ + *addr = 0xFFFF; + asm("sync"); + return (flag); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong start, csr, ready; + int flag=0; + + switch (info->portwidth) { + case FLASH_CFI_32BIT: + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if (big_endian == 1) { + ready = 0x0080; + } + else { + ready = 0x8000; + } + if ((info->portwidth / info->chipwidth)==2) { + ready += (ready <<16); + } + else { + ready = ready << 16; + } + /* Write Command */ + *addr = 0x10101010; + asm("sync"); + /* Write Data */ + *addr = data; + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + /* data polling for D7 */ + start = get_timer (0); + flag = 0; + while (((csr = *addr) & ready) != ready) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x40404040) { + printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + /* Clear Status Registers Command */ + *addr = 0x50505050; + asm("sync"); + /* Reset to read array mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + break; + case FLASH_CFI_16BIT: + flag = write_short (info, dest, (unsigned short) (data>>16)); + if (flag == 0) + flag = write_short (info, dest+2, (unsigned short) (data)); + break; + } + return (flag); +} + +/*----------------------------------------------------------------------- + * Clear Block Lock Bit, returns: + * 0 - OK + * 1 - Timeout + */ + +static int clear_block_lock_bit(flash_info_t * info, vu_long * addr) +{ + ulong start, now, ready; + + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + + *addr = 0x60606060; + asm("sync"); + *addr = 0xd0d0d0d0; + asm("sync"); + + + if (big_endian == 1) { + ready = 0x0080; + } + else { + ready = 0x8000; + } + if ((info->portwidth / info->chipwidth)==2) { + ready += (ready <<16); + } + else { + ready = ready << 16; + } +#ifdef DEBUG + printf ("%s: Ready flag is 0x%8lx\n", __FUNCTION__, ready); +#endif + *addr = 0x70707070; /* read status */ + start = get_timer (0); + while((*addr & ready) != ready){ + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout on clearing Block Lock Bit\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + } + return 0; +} + +#endif /* !CFG_NO_FLASH */ diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S new file mode 100644 index 0000000..8c2ca65 --- /dev/null +++ b/board/mpc8540eval/init.S @@ -0,0 +1,178 @@ +/* +* Copyright (C) 2002,2003, Motorola Inc. +* Xianghua Xiao +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +/* TLB1 entries configuration: */ + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + .long 0x0a /* the following data table uses a few of 16 TLB entries */ + + .long TLB1_MAS0(1,1,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + #if defined(CFG_FLASH_PORT_WIDTH_16) + .long TLB1_MAS0(1,2,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) + .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,3,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) + .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) + #else + .long TLB1_MAS0(1,2,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) + .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,3,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + #endif + + #if !defined(CONFIG_SPD_EEPROM) + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) + .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) + .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + #else + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + #endif + + .long TLB1_MAS0(1,6,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) + #if defined(CONFIG_RAM_AS_FLASH) + .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + #else + .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) + #endif + .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,7,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) + #ifdef CONFIG_L2_INIT_RAM + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) + #else + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) + #endif + .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,8,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,9,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) + .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + #else + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + #endif + entry_end + +/* LAW(Local Access Window) configuration: + * 0000_0000-0800_0000: DDR(128M) -or- larger + * f000_0000-f3ff_ffff: PCI(256M) + * f400_0000-f7ff_ffff: RapidIO(128M) + * f800_0000-ffff_ffff: localbus(128M) + * f800_0000-fbff_ffff: LBC SDRAM(64M) + * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) + * fdf0_0000-fdff_ffff: CCSRBAR(1M) + * fe00_0000-ffff_ffff: Flash(32M) + * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access + * Window. + * Note: If flash is 8M at default position(last 8M),no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#if !defined(CONFIG_RAM_AS_FLASH) +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR2 0 +#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x03 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 + entry_end diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c new file mode 100644 index 0000000..3b3c8ed --- /dev/null +++ b/board/mpc8540eval/mpc8540eval.c @@ -0,0 +1,251 @@ +/* + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +extern long int spd_sdram (void); + +long int fixed_sdram (void); + +int board_pre_init (void) +{ +#if defined(CONFIG_PCI) + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; + + pci->peer &= 0xffffffdf; /* disable master abort */ +#endif + return 0; +} + +int checkboard (void) +{ + sys_info_t sysinfo; + + get_sys_info (&sysinfo); + + printf ("Board: Freescale MPC8540EVAL Board\n"); + printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); + printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); + if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ + || (CFG_LBC_LCRR & 0x0f) == 8) { + printf ("\tLBC: %lu MHz\n", + sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f)); + } else { + printf("\tLBC: unknown\n"); + } + printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); + return (0); +} + +long int initdram (int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; +#if !defined(CONFIG_RAM_AS_FLASH) + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + sys_info_t sysinfo; + uint temp_lbcdll = 0; +#endif +#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) + volatile ccsr_gur_t *gur= &immap->im_gur; +#endif + +#if defined(CONFIG_DDR_DLL) + uint temp_ddrdll = 0; + + /* Work around to stabilize DDR DLL */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CFG_RAMBOOT) + return dram_size; +#endif + +#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ + get_sys_info(&sysinfo); + /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ + if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { + lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; + } else { + lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; + udelay(200); + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; + asm("sync;isync;msync"); + } + lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ + lbc->br2 = CFG_BR2_PRELIM; + lbc->lbcr = CFG_LBC_LBCR; + lbc->lsdmr = CFG_LBC_LSDMR_1; + asm("sync"); + * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_2; + asm("sync"); + * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_3; + asm("sync"); + * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm("sync"); + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + lbc->mrtpr = CFG_LBC_MRTPR; + asm("sync"); +#endif + +#if defined(CONFIG_DDR_ECC) + { + /* Initialize all of memory for ECC, then + * enable errors */ + uint *p = 0; + uint i = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + dma_init(); + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } + *p = (unsigned int)0xdeadbeef; + if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } + } + + /* 8K */ + dma_xfer((uint *)0x2000,0x2000,(uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000,0x4000,(uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000,0x8000,(uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000,0x10000,(uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000,0x20000,(uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000,0x40000,(uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000,0x80000,(uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000,0x100000,(uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000,0x200000,(uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000,0x400000,(uint *)0); + + for (i = 1; i < dram_size / 0x800000; i++) { + dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); + } + + /* Enable errors for ECC */ + ddr->err_disable = 0x00000000; + asm("sync;isync;msync"); + } +#endif + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; +#if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + ddr->err_sbe = 0x00ff0000; +#endif + asm("sync;isync;msync"); + udelay(500); +#if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); +#else + ddr->sdram_cfg = CFG_DDR_CONTROL; +#endif + asm("sync; isync; msync"); + udelay(500); +#endif + return (CFG_SDRAM_SIZE * 1024 * 1024); +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds new file mode 100644 index 0000000..0755d01 --- /dev/null +++ b/board/mpc8540eval/u-boot.lds @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2002,2003, Motorola,Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Assumes that the size of u-boot is less than 512K and the + * start address is aligned on a 512K block. + * Boot page and reset vector is put at that end of the 512K block. */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/mpc8540eval/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); + + . = (. & 0xFFF80000) + 0x0007F000; + .bootpg : + { + cpu/mpc85xx/start.o (.bootpg) + board/mpc8540eval/init.o (.bootpg) + } = 0xffff + + . = (. & 0xFFF80000) + 0x0007FFFC; + .resetvec : + { + *(.resetvec) + } = 0xffff + +} diff --git a/board/mpc8560ads/Makefile b/board/mpc8560ads/Makefile new file mode 100644 index 0000000..5d8ea34 --- /dev/null +++ b/board/mpc8560ads/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8560ads/config.mk b/board/mpc8560ads/config.mk new file mode 100644 index 0000000..9aef2bb --- /dev/null +++ b/board/mpc8560ads/config.mk @@ -0,0 +1,32 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,2003 Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8560ads board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8560ads/init.S b/board/mpc8560ads/init.S new file mode 100644 index 0000000..242cb9f --- /dev/null +++ b/board/mpc8560ads/init.S @@ -0,0 +1,280 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xf8000000 16K BCSR registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) + .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + .long TLB1_MAS0(1, 8, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1, 9, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c new file mode 100644 index 0000000..25f69a0 --- /dev/null +++ b/board/mpc8560ads/mpc8560ads.c @@ -0,0 +1,546 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram(void); + + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + + +/* + * MPC8560ADS Board Status & Control Registers + */ +typedef struct bcsr_ { + volatile unsigned char bcsr0; + volatile unsigned char bcsr1; + volatile unsigned char bcsr2; + volatile unsigned char bcsr3; + volatile unsigned char bcsr4; + volatile unsigned char bcsr5; +} bcsr_t; + + +int board_early_init_f (void) +{ + return 0; +} + +void reset_phy (void) +{ +#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ + volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR; +#endif + /* reset Giga bit Ethernet port if needed here */ + + /* reset the CPM FEC port */ +#if (CONFIG_ETHER_INDEX == 2) + bcsr->bcsr2 &= ~FETH2_RST; + udelay(2); + bcsr->bcsr2 |= FETH2_RST; + udelay(1000); +#elif (CONFIG_ETHER_INDEX == 3) + bcsr->bcsr3 &= ~FETH3_RST; + udelay(2); + bcsr->bcsr3 |= FETH3_RST; + udelay(1000); +#endif +#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) + /* reset PHY */ + miiphy_reset("FCC1 ETHERNET", 0x0); + + /* change PHY address to 0x02 */ + bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + + bb_miiphy_write(NULL, 0x02, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#endif /* CONFIG_MII */ +} + + +int checkboard (void) +{ + puts("Board: ADS\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + uint temp_ddrdll = 0; + + /* + * Work around to stabilize DDR DLL + */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); + } +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr(); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + + +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void +sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts(" SDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + lbc->br2 = CFG_BR2_PRELIM; + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("sync"); + + /* + * Configure the SDRAM controller. + */ + lbc->lsdmr = CFG_LBC_LSDMR_1; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_3; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ + #ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; + #if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + ddr->err_sbe = 0x00ff0000; + #endif + asm("sync;isync;msync"); + udelay(500); + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + asm("sync; isync; msync"); + udelay(500); + #endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/mpc8560ads/u-boot.lds b/board/mpc8560ads/u-boot.lds new file mode 100644 index 0000000..8dcee1f --- /dev/null +++ b/board/mpc8560ads/u-boot.lds @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2002,2003,Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/mpc8560ads/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/mpc8560ads/init.o (.text) + cpu/mpc85xx/commproc.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/serial_scc.o (.text) + cpu/mpc85xx/ether_fcc.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/i2c.o (.text) + cpu/mpc85xx/spd_sdram.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c new file mode 100644 index 0000000..b331d6e --- /dev/null +++ b/board/mpl/common/common_util.c @@ -0,0 +1,674 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include "common_util.h" +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PIP405 +#include "../pip405/pip405.h" +#include <405gp_pci.h> +#endif +#ifdef CONFIG_MIP405 +#include "../mip405/mip405.h" +#include <405gp_pci.h> +#endif +#if defined(CONFIG_PATI) +#define FIRM_START 0xFFF00000 +#endif + +extern int gunzip(void *, int, uchar *, unsigned long *); +extern int mem_test(ulong start, ulong ramsize, int quiet); + +#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ +#define IMAGE_SIZE CFG_MONITOR_LEN /* ugly, but it works for now */ + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +static image_header_t header; + + +static int +mpl_prg(uchar *src, ulong size) +{ + ulong start; + flash_info_t *info; + int i, rc; +#if defined(CONFIG_PATI) + int start_sect; +#endif +#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI) + char *copystr = (char *)src; + ulong *magic = (ulong *)src; +#endif + + info = &flash_info[0]; + +#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI) + if (ntohl(magic[0]) != IH_MAGIC) { + puts("Bad Magic number\n"); + return -1; + } + /* some more checks before we delete the Flash... */ + /* Checking the ISO_STRING prevents to program a + * wrong Firmware Image into the flash. + */ + i = 4; /* skip Magic number */ + while (1) { + if (strncmp(©str[i], "MEV-", 4) == 0) + break; + if (i++ >= 0x100) { + puts("Firmware Image for unknown Target\n"); + return -1; + } + } + /* we have the ISO STRING, check */ + if (strncmp(©str[i], CONFIG_ISO_STRING, sizeof(CONFIG_ISO_STRING)-1) != 0) { + printf("Wrong Firmware Image: %s\n", ©str[i]); + return -1; + } +#if !defined(CONFIG_PATI) + start = 0 - size; + for (i = info->sector_count-1; i > 0; i--) { + info->protect[i] = 0; /* unprotect this sector */ + if (start >= info->start[i]) + break; + } + /* set-up flash location */ + /* now erase flash */ + printf("Erasing at %lx (sector %d) (start %lx)\n", + start,i,info->start[i]); + if ((rc = flash_erase (info, i, info->sector_count-1)) != 0) { + puts("ERROR "); + flash_perror(rc); + return (1); + } + +#else /* #if !defined(CONFIG_PATI */ + start = FIRM_START; + start_sect = -1; + for (i = 0; i < info->sector_count; i++) { + if (start < info->start[i]) { + start_sect = i - 1; + break; + } + } + + info->protect[i - 1] = 0; /* unprotect this sector */ + for (; i < info->sector_count; i++) { + if ((start + size) < info->start[i]) + break; + info->protect[i] = 0; /* unprotect this sector */ + } + + i--; + /* set-up flash location */ + /* now erase flash */ + printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n", + start, start + size, start_sect, i, + info->start[start_sect], info->start[i]); + if ((rc = flash_erase (info, start_sect, i)) != 0) { + puts ("ERROR "); + flash_perror (rc); + return (1); + } +#endif /* defined(CONFIG_PATI) */ + +#elif defined(CONFIG_VCMA9) + start = 0; + for (i = 0; i sector_count; i++) { + info->protect[i] = 0; /* unprotect this sector */ + if (size < info->start[i]) + break; + } + /* set-up flash location */ + /* now erase flash */ + printf("Erasing at %lx (sector %d) (start %lx)\n", + start,0,info->start[0]); + if ((rc = flash_erase (info, 0, i)) != 0) { + puts("ERROR "); + flash_perror(rc); + return (1); + } + +#endif + printf("flash erased, programming from 0x%lx 0x%lx Bytes\n", + (ulong)src, size); + if ((rc = flash_write ((char *)src, start, size)) != 0) { + puts("ERROR "); + flash_perror(rc); + return (1); + } + puts("OK programming done\n"); + return 0; +} + + +static int +mpl_prg_image(uchar *ld_addr) +{ + unsigned long len, checksum; + uchar *data; + image_header_t *hdr = &header; + int rc; + + /* Copy header so we can blank CRC field for re-calculation */ + memcpy (&header, (char *)ld_addr, sizeof(image_header_t)); + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts("Bad Magic Number\n"); + return 1; + } + print_image_hdr(hdr); + if (hdr->ih_os != IH_OS_U_BOOT) { + puts("No U-Boot Image\n"); + return 1; + } + if (hdr->ih_type != IH_TYPE_FIRMWARE) { + puts("No Firmware Image\n"); + return 1; + } + data = (uchar *)&header; + len = sizeof(image_header_t); + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + if (crc32 (0, (uchar *)data, len) != checksum) { + puts("Bad Header Checksum\n"); + return 1; + } + data = ld_addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + puts("Verifying Checksum ... "); + if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { + puts("Bad Data CRC\n"); + return 1; + } + puts("OK\n"); + + if (hdr->ih_comp != IH_COMP_NONE) { + uchar *buf; + /* reserve space for uncompressed image */ + if ((buf = malloc(IMAGE_SIZE)) == NULL) { + puts("Insufficient space for decompression\n"); + return 1; + } + + switch (hdr->ih_comp) { + case IH_COMP_GZIP: + puts("Uncompressing (GZIP) ... "); + rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len); + if (rc != 0) { + puts("GUNZIP ERROR\n"); + free(buf); + return 1; + } + puts("OK\n"); + break; +#ifdef CONFIG_BZIP2 + case IH_COMP_BZIP2: + puts("Uncompressing (BZIP2) ... "); + { + uint retlen = IMAGE_SIZE; + rc = BZ2_bzBuffToBuffDecompress ((char *)(buf), &retlen, + (char *)data, len, 0, 0); + len = retlen; + } + if (rc != BZ_OK) { + printf ("BUNZIP2 ERROR: %d\n", rc); + free(buf); + return 1; + } + puts("OK\n"); + break; +#endif + default: + printf ("Unimplemented compression type %d\n", hdr->ih_comp); + free(buf); + return 1; + } + + rc = mpl_prg(buf, len); + free(buf); + } else { + rc = mpl_prg(data, len); + } + + return(rc); +} + +#if !defined(CONFIG_PATI) +void get_backup_values(backup_t *buf) +{ + i2c_read(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t)); +} + +void set_backup_values(int overwrite) +{ + backup_t back; + int i; + + get_backup_values(&back); + if(!overwrite) { + if(strncmp(back.signature,"MPL\0",4)==0) { + puts("Not possible to write Backup\n"); + return; + } + } + memcpy(back.signature,"MPL\0",4); + i = getenv_r("serial#",back.serial_name,16); + if(i < 0) { + puts("Not possible to write Backup\n"); + return; + } + back.serial_name[16]=0; + i = getenv_r("ethaddr",back.eth_addr,20); + if(i < 0) { + puts("Not possible to write Backup\n"); + return; + } + back.eth_addr[20]=0; + i2c_write(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); +} + +void clear_env_values(void) +{ + backup_t back; + unsigned char env_crc[4]; + + memset(&back,0xff,sizeof(backup_t)); + memset(env_crc,0x00,4); + i2c_write(CFG_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); + i2c_write(CFG_DEF_EEPROM_ADDR,CFG_ENV_OFFSET,2,(void *)env_crc,4); +} + +/* + * check crc of "older" environment + */ +int check_env_old_size(ulong oldsize) +{ + ulong crc, len, new; + unsigned off; + uchar buf[64]; + + /* read old CRC */ + eeprom_read (CFG_DEF_EEPROM_ADDR, + CFG_ENV_OFFSET, + (uchar *)&crc, sizeof(ulong)); + + new = 0; + len = oldsize; + off = sizeof(long); + len = oldsize-off; + while (len > 0) { + int n = (len > sizeof(buf)) ? sizeof(buf) : len; + + eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, buf, n); + new = crc32 (new, buf, n); + len -= n; + off += n; + } + + return (crc == new); +} + +static ulong oldsizes[] = { + 0x200, + 0x800, + 0 +}; + +void copy_old_env(ulong size) +{ + uchar name_buf[64]; + uchar value_buf[0x800]; + uchar c; + ulong len; + unsigned off; + uchar *name, *value; + + name=&name_buf[0]; + value=&value_buf[0]; + len=size; + off = sizeof(long); + while (len > off) { + eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, &c, 1); + if(c != '=') { + *name++=c; + off++; + } + else { + *name++='\0'; + off++; + do { + eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, &c, 1); + *value++=c; + off++; + if(c == '\0') + break; + } while(len > off); + name=&name_buf[0]; + value=&value_buf[0]; + if(strncmp((char *)name,"baudrate",8)!=0) { + setenv((char *)name,(char *)value); + } + + } + } +} + + +void check_env(void) +{ + char *s; + int i=0; + char buf[32]; + backup_t back; + + s=getenv("serial#"); + if(!s) { + while(oldsizes[i]) { + if(check_env_old_size(oldsizes[i])) + break; + i++; + } + if(!oldsizes[i]) { + /* no old environment has been found */ + get_backup_values (&back); + if (strncmp (back.signature, "MPL\0", 4) == 0) { + sprintf (buf, "%s", back.serial_name); + setenv ("serial#", buf); + sprintf (buf, "%s", back.eth_addr); + setenv ("ethaddr", buf); + printf ("INFO: serial# and ethaddr recovered, use saveenv\n"); + return; + } + } + else { + copy_old_env(oldsizes[i]); + puts("INFO: old environment ajusted, use saveenv\n"); + } + } + else { + /* check if back up is set */ + get_backup_values(&back); + if(strncmp(back.signature,"MPL\0",4)!=0) { + set_backup_values(0); + } + } +} + + +extern device_t *stdio_devices[]; +extern char *stdio_names[]; + +void show_stdio_dev(void) +{ + /* Print information */ + puts("In: "); + if (stdio_devices[stdin] == NULL) { + puts("No input devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stdin]->name); + } + + puts("Out: "); + if (stdio_devices[stdout] == NULL) { + puts("No output devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stdout]->name); + } + + puts("Err: "); + if (stdio_devices[stderr] == NULL) { + puts("No error devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stderr]->name); + } +} + +#endif /* #if !defined(CONFIG_PATI) */ + +int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong size,src,ld_addr; + int result; +#if !defined(CONFIG_PATI) + backup_t back; + src = MULTI_PURPOSE_SOCKET_ADDR; + size = IMAGE_SIZE; +#endif + + if (strcmp(argv[1], "flash") == 0) + { +#if (CONFIG_COMMANDS & CFG_CMD_FDC) + if (strcmp(argv[2], "floppy") == 0) { + char *local_args[3]; + extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]); + puts("\nupdating bootloader image from floppy\n"); + local_args[0] = argv[0]; + if(argc==4) { + local_args[1] = argv[3]; + local_args[2] = NULL; + ld_addr=simple_strtoul(argv[3], NULL, 16); + result=do_fdcboot(cmdtp, 0, 2, local_args); + } + else { + local_args[1] = NULL; + ld_addr=CFG_LOAD_ADDR; + result=do_fdcboot(cmdtp, 0, 1, local_args); + } + result=mpl_prg_image((uchar *)ld_addr); + return result; + } +#endif /* (CONFIG_COMMANDS & CFG_CMD_FDC) */ + if (strcmp(argv[2], "mem") == 0) { + if(argc==4) { + ld_addr=simple_strtoul(argv[3], NULL, 16); + } + else { + ld_addr=load_addr; + } + printf ("\nupdating bootloader image from memory at %lX\n",ld_addr); + result=mpl_prg_image((uchar *)ld_addr); + return result; + } +#if !defined(CONFIG_PATI) + if (strcmp(argv[2], "mps") == 0) { + puts("\nupdating bootloader image from MPS\n"); + result=mpl_prg((uchar *)src,size); + return result; + } +#endif /* #if !defined(CONFIG_PATI) */ + } + if (strcmp(argv[1], "mem") == 0) + { + result=0; + if(argc==3) + { + result = (int)simple_strtol(argv[2], NULL, 16); + } + src=(unsigned long)&result; + src-=CFG_MEMTEST_START; + src-=(100*1024); /* - 100k */ + src&=0xfff00000; + size=0; + do { + size++; + printf("\n\nPass %ld\n",size); + mem_test(CFG_MEMTEST_START,src,1); + if(ctrlc()) + break; + if(result>0) + result--; + + }while(result); + return 0; + } +#if !defined(CONFIG_PATI) + if (strcmp(argv[1], "clearenvvalues") == 0) + { + if (strcmp(argv[2], "yes") == 0) + { + clear_env_values(); + return 0; + } + } + if (strcmp(argv[1], "getback") == 0) { + get_backup_values(&back); + back.signature[3]=0; + back.serial_name[16]=0; + back.eth_addr[20]=0; + printf("GetBackUp: signature: %s\n",back.signature); + printf(" serial#: %s\n",back.serial_name); + printf(" ethaddr: %s\n",back.eth_addr); + return 0; + } + if (strcmp(argv[1], "setback") == 0) { + set_backup_values(1); + return 0; + } +#endif + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +} + + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe(ulong physadr); +void doc_init (void) +{ + doc_probe(MULTI_PURPOSE_SOCKET_ADDR); +} +#endif + + +#ifdef CONFIG_VIDEO +/****************************************************** + * Routines to display the Board information + * to the screen (since the VGA will be initialized as last, + * we must resend the infos) + */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +extern GraphicDevice ctfb; +extern int get_boot_mode(void); + +void video_get_info_str (int line_number, char *info) +{ + /* init video info strings for graphic console */ + DECLARE_GLOBAL_DATA_PTR; + PPC405_SYS_INFO sys_info; + char rev; + int i,boot; + unsigned long pvr; + char buf[64]; + char tmp[16]; + char cpustr[16]; + char *s, *e, bc; + switch (line_number) + { + case 2: + /* CPU and board infos */ + pvr=get_pvr(); + get_sys_info (&sys_info); + switch (pvr) { + case PVR_405GP_RB: rev='B'; break; + case PVR_405GP_RC: rev='C'; break; + case PVR_405GP_RD: rev='D'; break; + case PVR_405GP_RE: rev='E'; break; + case PVR_405GPR_RB: rev='B'; break; + default: rev='?'; break; + } + if(pvr==PVR_405GPR_RB) + sprintf(cpustr,"PPC405GPr %c",rev); + else + sprintf(cpustr,"PPC405GP %c",rev); + /* Board info */ + i=0; + s=getenv ("serial#"); +#ifdef CONFIG_PIP405 + if (!s || strncmp (s, "PIP405", 6)) { + sprintf(buf,"### No HW ID - assuming PIP405"); + } +#endif +#ifdef CONFIG_MIP405 + if (!s || strncmp (s, "MIP405", 6)) { + sprintf(buf,"### No HW ID - assuming MIP405"); + } +#endif + else { + for (e = s; *e; ++e) { + if (*e == ' ') + break; + } + for (; s < e; ++s) { + if (*s == '_') { + ++s; + break; + } + buf[i++]=*s; + } + sprintf(&buf[i]," SN "); + i+=4; + for (; s < e; ++s) { + buf[i++]=*s; + } + buf[i++]=0; + } + sprintf (info," %s %s %s MHz (%lu/%lu/%lu MHz)", + buf, cpustr, + strmhz (tmp, gd->cpu_clk), sys_info.freqPLB / 1000000, + sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, + sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000); + return; + case 3: + /* Memory Info */ + boot = get_boot_mode(); + bc = in8 (CONFIG_PORT_ADDR); + sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s", + gd->bd->bi_memsize / 0x100000, + gd->bd->bi_flashsize / 0x100000, + bc, + (boot & BOOT_MPS) ? "MPS boot" : "Flash boot", + ctfb.modeIdent); + return; + case 1: + sprintf (buf, "%s",CONFIG_IDENT_STRING); + sprintf (info, " %s", &buf[1]); + return; + } + /* no more info lines */ + *info = 0; + return; +} +#endif /* CONFIG_CONSOLE_EXTRA_INFO */ + +#endif /* CONFIG_VIDEO */ diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h new file mode 100644 index 0000000..8f2ec03 --- /dev/null +++ b/board/mpl/common/common_util.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _COMMON_UTIL_H_ +#define _COMMON_UTIL_H_ + +typedef struct { + char signature[4]; + char serial_name[17]; /* "MIP405_1000xxxxx" */ + char eth_addr[21]; /* "00:60:C2:0a:00:00" */ +} backup_t; + +void get_backup_values(backup_t *buf); + +#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) +#define BOOT_MPS 0x01 +#define BOOT_PCI 0x02 +#endif + +void show_stdio_dev(void); +void check_env(void); +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +void doc_init (void); +#endif + +#endif /* _COMMON_UTIL_H_ */ diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c new file mode 100644 index 0000000..fd43008 --- /dev/null +++ b/board/mpl/common/flash.c @@ -0,0 +1,882 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +/* + * Modified 3/7/2001 + * - adapted for pip405, Denis Peter, MPL AG Switzerland + * TODO: + * clean-up + */ + +#include + +#if !defined(CONFIG_PATI) +#include +#include +#include "common_util.h" +#if defined(CONFIG_MIP405) +#include "../mip405/mip405.h" +#endif +#if defined(CONFIG_PIP405) +#include "../pip405/pip405.h" +#endif +#include <405gp_pci.h> +#else /* defined(CONFIG_PATI) */ +#include +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned short + +#define FALSE 0 +#define TRUE 1 + +#if !defined(CONFIG_PATI) + +/*----------------------------------------------------------------------- + * Some CS switching routines: + * + * On PIP/MIP405 we have 3 (4) possible boot mode + * + * - Boot from Flash (Flash CS = CS0, MPS CS = CS1) + * - Boot from MPS (Flash CS = CS1, MPS CS = CS0) + * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1) + * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0) + * The flash init is the first board specific routine which is called + * after code relocation (running from SDRAM) + * The first thing we do is to map the Flash CS to the Flash area and + * the MPS CS to the MPS area. Since the flash size is unknown at this + * point, we use the max flash size and the lowest flash address as base. + * + * After flash detection we adjust the size of the CS area accordingly. + * The board_init_r will fill in wrong values in the board init structure, + * but this will be fixed in the misc_init_r routine: + * bd->bi_flashstart=0-flash_info[0].size + * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN + * bd->bi_flashoffset=0 + * + */ +int get_boot_mode(void) +{ + unsigned long pbcr; + int res = 0; + pbcr = mfdcr (strap); + if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) + /* boot via MPS or MPS mapping */ + res = BOOT_MPS; + if(pbcr & PSR_ROM_LOC) + /* boot via PCI.. */ + res |= BOOT_PCI; + return res; +} + +/* Map the flash high (in boot area) + This code can only be executed from SDRAM (after relocation). +*/ +void setup_cs_reloc(void) +{ + int mode; + /* Since we are relocated, we can set-up the CS finaly + * but first of all, switch off PCI mapping (in case it was a PCI boot) */ + out32r(PMM0MA,0L); + icache_enable (); /* we are relocated */ + /* get boot mode */ + mode=get_boot_mode(); + /* we map the flash high in every case */ + /* first findout on which cs the flash is */ + if(mode & BOOT_MPS) { + /* map flash high on CS1 and MPS on CS0 */ + mtdcr (ebccfga, pb0ap); + mtdcr (ebccfgd, MPS_AP); + mtdcr (ebccfga, pb0cr); + mtdcr (ebccfgd, MPS_CR); + /* we use the default values (max values) for the flash + * because its real size is not yet known */ + mtdcr (ebccfga, pb1ap); + mtdcr (ebccfgd, FLASH_AP); + mtdcr (ebccfga, pb1cr); + mtdcr (ebccfgd, FLASH_CR_B); + } + else { + /* map flash high on CS0 and MPS on CS1 */ + mtdcr (ebccfga, pb1ap); + mtdcr (ebccfgd, MPS_AP); + mtdcr (ebccfga, pb1cr); + mtdcr (ebccfgd, MPS_CR); + /* we use the default values (max values) for the flash + * because its real size is not yet known */ + mtdcr (ebccfga, pb0ap); + mtdcr (ebccfgd, FLASH_AP); + mtdcr (ebccfga, pb0cr); + mtdcr (ebccfgd, FLASH_CR_B); + } +} + +#endif /* #if !defined(CONFIG_PATI) */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + +#if !defined(CONFIG_PATI) + unsigned long size_b1,flashcr,size_reg; + int mode; + extern char version_string; + char *p=&version_string; + + /* Since we are relocated, we can set-up the CS finally */ + setup_cs_reloc(); + /* get and display boot mode */ + mode=get_boot_mode(); + if(mode & BOOT_PCI) + printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ? + "MPS" : "Flash"); + else + printf("(%s Boot) ",(mode & BOOT_MPS) ? + "MPS" : "Flash"); +#endif /* #if !defined(CONFIG_PATI) */ + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif +#if !defined(CONFIG_PATI) + /* protect reset vector */ + flash_info[0].protect[flash_info[0].sector_count-1] = 1; + size_b1 = 0 ; + flash_info[0].size = size_b0; + /* set up flash cs according to the size */ + size_reg=(flash_info[0].size >>20); + switch (size_reg) { + case 0: + case 1: i=0; break; /* <= 1MB */ + case 2: i=1; break; /* = 2MB */ + case 4: i=2; break; /* = 4MB */ + case 8: i=3; break; /* = 8MB */ + case 16: i=4; break; /* = 16MB */ + case 32: i=5; break; /* = 32MB */ + case 64: i=6; break; /* = 64MB */ + case 128: i=7; break; /*= 128MB */ + default: + printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg); + while(1); + } + if(mode & BOOT_MPS) { + /* flash is on CS1 */ + mtdcr(ebccfga, pb1cr); + flashcr = mfdcr (ebccfgd); + /* we map the flash high in every case */ + flashcr&=0x0001FFFF; /* mask out address bits */ + flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ + flashcr|= (i << 17); /* size addr */ + mtdcr(ebccfga, pb1cr); + mtdcr(ebccfgd, flashcr); + } + else { + /* flash is on CS0 */ + mtdcr(ebccfga, pb0cr); + flashcr = mfdcr (ebccfgd); + /* we map the flash high in every case */ + flashcr&=0x0001FFFF; /* mask out address bits */ + flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ + flashcr|= (i << 17); /* size addr */ + mtdcr(ebccfga, pb0cr); + mtdcr(ebccfgd, flashcr); + } +#if 0 + /* enable this (PIP405/MIP405 only) if you want to test if + the relocation has be done ok. + This will disable both Chipselects */ + mtdcr (ebccfga, pb0cr); + mtdcr (ebccfgd, 0L); + mtdcr (ebccfga, pb1cr); + mtdcr (ebccfgd, 0L); + printf("CS0 & CS1 switched off for test\n"); +#endif + /* patch version_string */ + for(i=0;i<0x100;i++) { + if(*p=='\n') { + *p=0; + break; + } + p++; + } +#else /* #if !defined(CONFIG_PATI) */ +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif +#endif /* #if !defined(CONFIG_PATI) */ + return (size_b0); +} + + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_INTEL: printf ("Intel "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_INTEL320T: printf ("TE28F320C3 (32 Mbit, top sector size)\n"); + break; + case FLASH_AM640U: printf ("AM29LV640U (64 Mbit, uniform sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + +*/ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; + + value = addr2[0]; + /* printf("flash_get_size value: %x\n",value); */ + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE)FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + case (FLASH_WORD_SIZE)SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + value = addr2[1]; /* device ID */ + /* printf("Device value %x\n",value); */ + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE)AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + case (FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + case (FLASH_WORD_SIZE)AMD_ID_LV640U: + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000; + break; /* => 8 MB */ +#if 0 /* enable when device IDs are available */ + + case (FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ +#endif + case (FLASH_WORD_SIZE)SST_ID_xF800A: + info->flash_id += FLASH_SST800A; + info->sector_count = 16; + info->size = 0x00100000; + break; /* => 1 MB */ + case (FLASH_WORD_SIZE)INTEL_ID_28F320C3T: + info->flash_id += FLASH_INTEL320T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + + + case (FLASH_WORD_SIZE)SST_ID_xF160A: + info->flash_id += FLASH_SST160A; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + /* base address calculation */ + base=0-info->size; + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040) || + (info->flash_id == FLASH_AM640U)){ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } + else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + if(info->sector_count==71) { + + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000A000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x0000E000; + for (; i >= 0; i--) + info->start[i] = base + i * 0x000010000; + } + else { + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + return (info->size); +} + + +int wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return ERR_TIMOUT; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return ERR_OK; +} + +int intel_wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last, status; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return ERR_TIMOUT; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + status = addr[0] & (FLASH_WORD_SIZE)0x00280028; + /* clear status register */ + addr[0] = (FLASH_WORD_SIZE)0x00500050; + /* check status for block erase fail and VPP low */ + return (status == 0 ? ERR_OK : ERR_NOT_ERASED); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i, rcode = 0; + + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + /* printf("Erasing sector %p\n", addr2); */ /* CLH */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + for (i=0; i<50; i++) + udelay(1000); /* wait 1 ms */ + rcode |= wait_for_DQ7(info, sect); + } + else { + if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ + addr2[0] = (FLASH_WORD_SIZE)0x00600060; /* unlock sector */ + addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */ + intel_wait_for_DQ7(info, sect); + addr2[0] = (FLASH_WORD_SIZE)0x00200020; /* sector erase */ + addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */ + rcode |= intel_wait_for_DQ7(info, sect); + } + else { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + rcode |= wait_for_DQ7(info, sect); + } + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + /* wait_for_DQ7(info, sect); */ + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#if 0 + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + wait_for_DQ7(info, l_sect); + +DONE: +#endif + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + if (!rcode) + printf (" done\n"); + + return rcode; +} + + +void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt) +{ + int i; + volatile FLASH_WORD_SIZE *addr2; + long c; + c= (long)cnt; + for(i=info->sector_count-1;i>0;i--) + { + if(addr>=info->start[i]) + break; + } + do { + addr2 = (FLASH_WORD_SIZE *)(info->start[i]); + addr2[0] = (FLASH_WORD_SIZE)0x00600060; /* unlock sector setup */ + addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* unlock sector */ + intel_wait_for_DQ7(info, i); + i++; + c-=(info->start[i]-info->start[i-1]); + }while(c>0); +} + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ + unlock_intel_sectors(info,addr,cnt); + } + wp = (addr & ~3); /* get lower word aligned address */ + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + if((wp % 0x10000)==0) + printf("."); /* show Progress */ + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + rc=write_word(info, wp, data); + return rc; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static FLASH_WORD_SIZE *read_val = (FLASH_WORD_SIZE *)0x200000; + +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *)dest) & + (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) + { + if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ + /* intel style writting */ + dest2[i] = (FLASH_WORD_SIZE)0x00500050; + dest2[i] = (FLASH_WORD_SIZE)0x00400040; + *read_val++ = data2[i]; + dest2[i] = data2[i]; + if (flag) + enable_interrupts(); + /* data polling for D7 */ + start = get_timer (0); + udelay(10); + while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) + { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */ + udelay(10); + dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */ + if(dest2[i]!=data2[i]) + printf("Error at %p 0x%04X != 0x%04X\n",&dest2[i],dest2[i],data2[i]); + } + else { + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; + dest2[i] = data2[i]; + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c new file mode 100644 index 0000000..51b2773 --- /dev/null +++ b/board/mpl/common/isa.c @@ -0,0 +1,494 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * TODO: clean-up + */ + +#include +#include +#include +#include "isa.h" +#include "piix4_pci.h" +#include "kbd.h" +#include "video.h" + + +#undef ISA_DEBUG + +#ifdef ISA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#if defined(CONFIG_PIP405) + +extern int drv_isa_kbd_init (void); + +/* fdc (logical device 0) */ +const SIO_LOGDEV_TABLE sio_fdc[] = { + {0x60, 3}, /* set IO to FDPort (3F0) */ + {0x61, 0xF0}, /* set IO to FDPort (3F0) */ + {0x70, 06}, /* set IRQ 6 for FDPort */ + {0x74, 02}, /* set DMA 2 for FDPort */ + {0xF0, 0x05}, /* set to PS2 type */ + {0xF1, 0x00}, /* default value */ + {0x30, 1}, /* and activate the device */ + {0xFF, 0} /* end of device table */ +}; +/* paralell port (logical device 3) */ +const SIO_LOGDEV_TABLE sio_pport[] = { + {0x60, 3}, /* set IO to PPort (378) */ + {0x61, 0x78}, /* set IO to PPort (378) */ + {0x70, 07}, /* set IRQ 7 for PPort */ + {0xF1, 00}, /* set PPort to normal */ + {0x30, 1}, /* and activate the device */ + {0xFF, 0} /* end of device table */ +}; +/* paralell port (logical device 3) Floppy assigned to lpt */ +const SIO_LOGDEV_TABLE sio_pport_fdc[] = { + {0x60, 3}, /* set IO to PPort (378) */ + {0x61, 0x78}, /* set IO to PPort (378) */ + {0x70, 07}, /* set IRQ 7 for PPort */ + {0xF1, 02}, /* set PPort to Floppy */ + {0x30, 1}, /* and activate the device */ + {0xFF, 0} /* end of device table */ +}; +/* uart 1 (logical device 4) */ +const SIO_LOGDEV_TABLE sio_com1[] = { + {0x60, 3}, /* set IO to COM1 (3F8) */ + {0x61, 0xF8}, /* set IO to COM1 (3F8) */ + {0x70, 04}, /* set IRQ 4 for COM1 */ + {0x30, 1}, /* and activate the device */ + {0xFF, 0} /* end of device table */ +}; +/* uart 2 (logical device 5) */ +const SIO_LOGDEV_TABLE sio_com2[] = { + {0x60, 2}, /* set IO to COM2 (2F8) */ + {0x61, 0xF8}, /* set IO to COM2 (2F8) */ + {0x70, 03}, /* set IRQ 3 for COM2 */ + {0x30, 1}, /* and activate the device */ + {0xFF, 0} /* end of device table */ +}; + +/* keyboard controller (logical device 7) */ +const SIO_LOGDEV_TABLE sio_keyboard[] = { + {0x70, 1}, /* set IRQ 1 for keyboard */ + {0x72, 12}, /* set IRQ 12 for mouse */ + {0xF0, 0}, /* disable Port92 (this is a PowerPC!!) */ + {0x30, 1}, /* and activate the device */ + {0xFF, 0} /* end of device table */ +}; + + +/******************************************************************************* +* Config SuperIO FDC37C672 +********************************************************************************/ +unsigned char open_cfg_super_IO(int address) +{ + out8(CFG_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */ + out8(CFG_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */ + if(in8(CFG_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */ + return TRUE; + else + return FALSE; +} + +void close_cfg_super_IO(int address) +{ + out8(CFG_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */ +} + + +unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr) +{ + /* assuming config reg is open */ + out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ + out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ + out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ + return in8(CFG_ISA_IO_BASE_ADDRESS | address | 1); +} + +void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data) +{ + /* assuming config reg is open */ + out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ + out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ + out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ + out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */ +} + +void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev) +{ + while (ldt->index != 0xFF) { + write_cfg_super_IO(SIO_CFG_PORT, ldev, ldt->index, ldt->val); + ldt++; + } /* endwhile */ +} + +void isa_sio_loadtable(void) +{ + char *s = getenv("floppy"); + /* setup Floppy device 0*/ + isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0); + /* setup parallel port device 3 */ + if(s && !strncmp(s, "lpt", 3)) { + printf("SIO: Floppy assigned to LPT\n"); + /* floppy is assigned to the LPT */ + isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport_fdc,3); + } + else { + /*printf("Floppy assigned to internal port\n");*/ + isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport,3); + } + /* setup Com1 port device 4 */ + isa_write_table((SIO_LOGDEV_TABLE *)&sio_com1,4); + /* setup Com2 port device 5 */ + isa_write_table((SIO_LOGDEV_TABLE *)&sio_com2,5); + /* setup keyboards device 7 */ + isa_write_table((SIO_LOGDEV_TABLE *)&sio_keyboard,7); +} + + +void isa_sio_setup(void) +{ + if(open_cfg_super_IO(SIO_CFG_PORT)==TRUE) + { + isa_sio_loadtable(); + close_cfg_super_IO(0x3F0); + } +} +#endif + +/****************************************************************************** + * IRQ Controller + * we use the Vector mode + */ + +struct isa_irq_action { + interrupt_handler_t *handler; + void *arg; + int count; +}; + +static struct isa_irq_action isa_irqs[16]; + + +/* + * This contains the irq mask for both 8259A irq controllers, + */ +static unsigned int cached_irq_mask = 0xfff9; + +#define cached_imr1 (unsigned char)cached_irq_mask +#define cached_imr2 (unsigned char)(cached_irq_mask>>8) +#define IMR_1 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1 +#define IMR_2 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1 +#define ICW1_1 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1 +#define ICW1_2 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1 +#define ICW2_1 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2 +#define ICW2_2 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2 +#define ICW3_1 ICW2_1 +#define ICW3_2 ICW2_2 +#define ICW4_1 ICW2_1 +#define ICW4_2 ICW2_2 +#define ISR_1 ICW1_1 +#define ISR_2 ICW1_2 + + +void disable_8259A_irq(unsigned int irq) +{ + unsigned int mask = 1 << irq; + + cached_irq_mask |= mask; + if (irq & 8) + out8(IMR_2,cached_imr2); + else + out8(IMR_1,cached_imr1); +} + +void enable_8259A_irq(unsigned int irq) +{ + unsigned int mask = ~(1 << irq); + + cached_irq_mask &= mask; + if (irq & 8) + out8(IMR_2,cached_imr2); + else + out8(IMR_1,cached_imr1); +} +/* +int i8259A_irq_pending(unsigned int irq) +{ + unsigned int mask = 1<> 8); + spin_unlock_irqrestore(&i8259A_lock, flags); + + return ret; +} +*/ + +/* + * This function assumes to be called rarely. Switching between + * 8259A registers is slow. + */ +int i8259A_irq_real(unsigned int irq) +{ + int value; + int irqmask = 1<> 8); + out8(ISR_2,0x0A); /* back to the IRR register */ + return value; +} + +/* + * Careful! The 8259A is a fragile beast, it pretty + * much _has_ to be done exactly like this (mask it + * first, _then_ send the EOI, and the order of EOI + * to the two 8259s is important! + */ +void mask_and_ack_8259A(unsigned int irq) +{ + unsigned int irqmask = 1 << irq; + unsigned int temp_irqmask = cached_irq_mask; + /* + * Lightweight spurious IRQ detection. We do not want + * to overdo spurious IRQ handling - it's usually a sign + * of hardware problems, so we only do the checks we can + * do without slowing down good hardware unnecesserily. + * + * Note that IRQ7 and IRQ15 (the two spurious IRQs + * usually resulting from the 8259A-1|2 PICs) occur + * even if the IRQ is masked in the 8259A. Thus we + * can check spurious 8259A IRQs without doing the + * quite slow i8259A_irq_real() call for every IRQ. + * This does not cover 100% of spurious interrupts, + * but should be enough to warn the user that there + * is something bad going on ... + */ + if (temp_irqmask & irqmask) + goto spurious_8259A_irq; + temp_irqmask |= irqmask; + +handle_real_irq: + if (irq & 8) { + in8(IMR_2); /* DUMMY - (do we need this?) */ + out8(IMR_2,(unsigned char)(temp_irqmask>>8)); + out8(ISR_2,0x60+(irq&7));/* 'Specific EOI' to slave */ + out8(ISR_1,0x62); /* 'Specific EOI' to master-IRQ2 */ + out8(IMR_2,cached_imr2); /* turn it on again */ + } else { + in8(IMR_1); /* DUMMY - (do we need this?) */ + out8(IMR_1,(unsigned char)temp_irqmask); + out8(ISR_1,0x60+irq); /* 'Specific EOI' to master */ + out8(IMR_1,cached_imr1); /* turn it on again */ + } + + return; + +spurious_8259A_irq: + /* + * this is the slow path - should happen rarely. + */ + if (i8259A_irq_real(irq)) + /* + * oops, the IRQ _is_ in service according to the + * 8259A - not spurious, go handle it. + */ + goto handle_real_irq; + + { + static int spurious_irq_mask; + /* + * At this point we can be sure the IRQ is spurious, + * lets ACK and report it. [once per IRQ] + */ + if (!(spurious_irq_mask & irqmask)) { + PRINTF("spurious 8259A interrupt: IRQ%d.\n", irq); + spurious_irq_mask |= irqmask; + } + /* irq_err_count++; */ + /* + * Theoretically we do not have to handle this IRQ, + * but in Linux this does not cause problems and is + * simpler for us. + */ + goto handle_real_irq; + } +} + +void init_8259A(void) +{ + out8(IMR_1,0xff); /* mask all of 8259A-1 */ + out8(IMR_2,0xff); /* mask all of 8259A-2 */ + + out8(ICW1_1,0x11); /* ICW1: select 8259A-1 init */ + out8(ICW2_1,0x20 + 0); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ + out8(ICW3_1,0x04); /* 8259A-1 (the master) has a slave on IR2 */ + out8(ICW4_1,0x01); /* master expects normal EOI */ + out8(ICW1_2,0x11); /* ICW2: select 8259A-2 init */ + out8(ICW2_2,0x20 + 8); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */ + out8(ICW3_2,0x02); /* 8259A-2 is a slave on master's IR2 */ + out8(ICW4_2,0x01); /* (slave's support for AEOI in flat mode + is to be investigated) */ + udelay(10000); /* wait for 8259A to initialize */ + out8(IMR_1,cached_imr1); /* restore master IRQ mask */ + udelay(10000); /* wait for 8259A to initialize */ + out8(IMR_2,cached_imr2); /* restore slave IRQ mask */ +} + + +#define PCI_INT_ACK_ADDR 0xEED00000 + +int handle_isa_int(void) +{ + unsigned long irqack; + unsigned char isr1,isr2,irq; + /* first we acknokledge the int via the PCI bus */ + irqack=in32(PCI_INT_ACK_ADDR); + /* now we get the ISRs */ + isr2=in8(ISR_2); + isr1=in8(ISR_1); + irq=(unsigned char)irqack; + irq-=32; +/* if((irq==7)&&((isr1&0x80)==0)) { + PRINTF("IRQ7 detected but not in ISR\n"); + } + else { +*/ /* we should handle cascaded interrupts here also */ + { +/* printf("ISA Irq %d\n",irq); */ + isa_irqs[irq].count++; + if(irq!=2) { /* just swallow the cascade irq 2 */ + if (isa_irqs[irq].handler != NULL) + (*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */ + else { + PRINTF ("bogus interrupt vector 0x%x\n", irq); + } + } + } + /* issue EOI instruction to clear the IRQ */ + mask_and_ack_8259A(irq); + return 0; +} + + +/****************************************************************** + * Install and free an ISA interrupt handler. + */ + +void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +{ + if (isa_irqs[vec].handler != NULL) { + printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n", + vec, (uint)handler, (uint)isa_irqs[vec].handler); + } + isa_irqs[vec].handler = handler; + isa_irqs[vec].arg = arg; + enable_8259A_irq(vec); + PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask); + +} + +void isa_irq_free_handler(int vec) +{ + disable_8259A_irq(vec); + isa_irqs[vec].handler = NULL; + isa_irqs[vec].arg = NULL; + PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask); + +} + +/****************************************************************************/ +void isa_init_irq_contr(void) +{ + int i; + /* disable all Interrupts */ + /* first write icws controller 1 */ + for(i=0;i<16;i++) + { + isa_irqs[i].handler=NULL; + isa_irqs[i].arg=NULL; + isa_irqs[i].count=0; + } + init_8259A(); + out8(IMR_2,0xFF); +} +/*************************************************************************/ + +void isa_show_irq(void) +{ + int vec; + + printf ("\nISA Interrupt-Information:\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<16; vec++) { + if (isa_irqs[vec].handler != NULL) { + printf ("%02d %08lx %08lx %d\n", + vec, + (ulong)isa_irqs[vec].handler, + (ulong)isa_irqs[vec].arg, + isa_irqs[vec].count); + } + } +} + +int isa_irq_get_count(int vec) +{ + return(isa_irqs[vec].count); +} + +/****************************************************************** + * Init the ISA bus and devices. + */ + +#if defined(CONFIG_PIP405) + +int isa_init(void) +{ + isa_sio_setup(); + isa_init_irq_contr(); + drv_isa_kbd_init(); + return 0; +} +#endif diff --git a/board/mpl/common/isa.h b/board/mpl/common/isa.h new file mode 100644 index 0000000..28ed219 --- /dev/null +++ b/board/mpl/common/isa.h @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ISA_H_ +#define _ISA_H_ +/* Super IO */ +#define SIO_CFG_PORT 0x3F0 /* Config Port Address */ + +#if defined(CONFIG_PIP405) +/* table fore SIO initialization */ +typedef struct { + const uchar index; + const uchar val; +} SIO_LOGDEV_TABLE; + +typedef struct { + const uchar ldev; + const SIO_LOGDEV_TABLE *ldev_table; +} SIO_TABLE; + + +unsigned char open_cfg_super_IO(int address); +unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr); +void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data); +void close_cfg_super_IO(int address); +void isa_sio_setup(void); +#endif + +void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg); +void isa_irq_free_handler(int vec); +int handle_isa_int(void); +void isa_init_irq_contr(void); +void isa_show_irq(void); +int isa_irq_get_count(int vec); + + +#endif diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c new file mode 100644 index 0000000..7724e24 --- /dev/null +++ b/board/mpl/common/kbd.c @@ -0,0 +1,647 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * Source partly derived from: + * linux/drivers/char/pc_keyb.c + * + * + */ +#include +#include +#include +#include "isa.h" +#include "kbd.h" + + +unsigned char kbd_read_status(void); +unsigned char kbd_read_input(void); +void kbd_send_data(unsigned char data); +void disable_8259A_irq(unsigned int irq); +void enable_8259A_irq(unsigned int irq); + +/* used only by send_data - set by keyboard_interrupt */ + + +#undef KBG_DEBUG + +#ifdef KBG_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#define KBD_STAT_KOBF 0x01 +#define KBD_STAT_IBF 0x02 +#define KBD_STAT_SYS 0x04 +#define KBD_STAT_CD 0x08 +#define KBD_STAT_LOCK 0x10 +#define KBD_STAT_MOBF 0x20 +#define KBD_STAT_TI_OUT 0x40 +#define KBD_STAT_PARERR 0x80 + +#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */ +#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */ +#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */ +/* + * Keyboard Controller Commands + */ + +#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ +#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ +#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ +#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ +#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ +#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ +#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ +#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ +#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ +#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ +#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if + initiated by the auxiliary device */ +#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ + +/* + * Keyboard Commands + */ + +#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ +#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ +#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ +#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ +#define KBD_CMD_RESET 0xFF /* Reset */ + +/* + * Keyboard Replies + */ + +#define KBD_REPLY_POR 0xAA /* Power on reset */ +#define KBD_REPLY_ACK 0xFA /* Command ACK */ +#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ + +/* + * Status Register Bits + */ + +#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ +#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ +#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ +#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ +#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ +#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ +#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ +#define KBD_STAT_PERR 0x80 /* Parity error */ + +#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF) + +/* + * Controller Mode Register Bits + */ + +#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ +#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ +#define KBD_MODE_SYS 0x04 /* The system flag (?) */ +#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ +#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ +#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ +#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ +#define KBD_MODE_RFU 0x80 + + +#define KDB_DATA_PORT 0x60 +#define KDB_COMMAND_PORT 0x64 + +#define LED_SCR 0x01 /* scroll lock led */ +#define LED_CAP 0x04 /* caps lock led */ +#define LED_NUM 0x02 /* num lock led */ + +#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ + + +static volatile char kbd_buffer[KBD_BUFFER_LEN]; +static volatile int in_pointer = 0; +static volatile int out_pointer = 0; + + +static unsigned char num_lock = 0; +static unsigned char caps_lock = 0; +static unsigned char scroll_lock = 0; +static unsigned char shift = 0; +static unsigned char ctrl = 0; +static unsigned char alt = 0; +static unsigned char e0 = 0; +static unsigned char leds = 0; + +#define DEVNAME "kbd" + +/* Simple translation table for the keys */ + +static unsigned char kbd_plain_xlate[] = { + 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ + 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +static unsigned char kbd_shift_xlate[] = { + 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */ + 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +static unsigned char kbd_ctrl_xlate[] = { + 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */ + 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */ + 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */ + 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +/****************************************************************** + * Init + ******************************************************************/ +int isa_kbd_init(void) +{ + char* result; + result=kbd_initialize(); + if(result==NULL) { + PRINTF("AT Keyboard initialized\n"); + irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL); + isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL); + return (1); + } + else { + printf("%s\n",result); + return (-1); + } +} + +#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console (void); +#else +int overwrite_console (void) +{ + return (0); +} +#endif + +int drv_isa_kbd_init (void) +{ + int error; + device_t kbddev ; + char *stdinname = getenv ("stdin"); + + if(isa_kbd_init()==-1) + return -1; + memset (&kbddev, 0, sizeof(kbddev)); + strcpy(kbddev.name, DEVNAME); + kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbddev.putc = NULL ; + kbddev.puts = NULL ; + kbddev.getc = kbd_getc ; + kbddev.tstc = kbd_testc ; + + error = device_register (&kbddev); + if(error==0) { + /* check if this is the standard input device */ + if(strcmp(stdinname,DEVNAME)==0) { + /* reassign the console */ + if(overwrite_console()) { + return 1; + } + error=console_assign(stdin,DEVNAME); + if(error==0) + return 1; + else + return error; + } + return 1; + } + return error; +} + +/****************************************************************** + * Queue handling + ******************************************************************/ +/* puts character in the queue and sets up the in and out pointer */ +void kbd_put_queue(char data) +{ + if((in_pointer+1)==KBD_BUFFER_LEN) { + if(out_pointer==0) { + return; /* buffer full */ + } else{ + in_pointer=0; + } + } else { + if((in_pointer+1)==out_pointer) + return; /* buffer full */ + in_pointer++; + } + kbd_buffer[in_pointer]=data; + return; +} + +/* test if a character is in the queue */ +int kbd_testc(void) +{ + if(in_pointer==out_pointer) + return(0); /* no data */ + else + return(1); +} +/* gets the character from the queue */ +int kbd_getc(void) +{ + char c; + while(in_pointer==out_pointer); + if((out_pointer+1)==KBD_BUFFER_LEN) + out_pointer=0; + else + out_pointer++; + c=kbd_buffer[out_pointer]; + return (int)c; + +} + + +/* set LEDs */ + +void kbd_set_leds(void) +{ + if(caps_lock==0) + leds&=~LED_CAP; /* switch caps_lock off */ + else + leds|=LED_CAP; /* switch on LED */ + if(num_lock==0) + leds&=~LED_NUM; /* switch LED off */ + else + leds|=LED_NUM; /* switch on LED */ + if(scroll_lock==0) + leds&=~LED_SCR; /* switch LED off */ + else + leds|=LED_SCR; /* switch on LED */ + kbd_send_data(KBD_CMD_SET_LEDS); + kbd_send_data(leds); +} + + +void handle_keyboard_event(unsigned char scancode) +{ + unsigned char keycode; + + /* Convert scancode to keycode */ + PRINTF("scancode %x\n",scancode); + if(scancode==0xe0) { + e0=1; /* special charakters */ + return; + } + if(e0==1) { + e0=0; /* delete flag */ + if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */ + ((scancode&0x7F)==0x1D)|| /* the right alt key */ + ((scancode&0x7F)==0x35)|| /* the right '/' key */ + ((scancode&0x7F)==0x1C) )) /* the right enter key */ + /* we swallow unknown e0 codes */ + return; + } + /* special cntrl keys */ + switch(scancode) + { + case 0x2A: + case 0x36: /* shift pressed */ + shift=1; + return; /* do nothing else */ + case 0xAA: + case 0xB6: /* shift released */ + shift=0; + return; /* do nothing else */ + case 0x38: /* alt pressed */ + alt=1; + return; /* do nothing else */ + case 0xB8: /* alt released */ + alt=0; + return; /* do nothing else */ + case 0x1d: /* ctrl pressed */ + ctrl=1; + return; /* do nothing else */ + case 0x9d: /* ctrl released */ + ctrl=0; + return; /* do nothing else */ + case 0x46: /* scrollock pressed */ + scroll_lock=~scroll_lock; + kbd_set_leds(); + return; /* do nothing else */ + case 0x3A: /* capslock pressed */ + caps_lock=~caps_lock; + kbd_set_leds(); + return; + case 0x45: /* numlock pressed */ + num_lock=~num_lock; + kbd_set_leds(); + return; + case 0xC6: /* scroll lock released */ + case 0xC5: /* num lock released */ + case 0xBA: /* caps lock released */ + return; /* just swallow */ + } + if((scancode&0x80)==0x80) /* key released */ + return; + /* now, decide which table we need */ + if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow it */ + } + /* setup plain code first */ + keycode=kbd_plain_xlate[scancode]; + if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown caps-locked scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_shift_xlate[scancode]; + if(keycode<'A') { /* we only want the alphas capital */ + keycode=kbd_plain_xlate[scancode]; + } + } + if(shift==1) { /* shift overwrites caps_lock */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown shifted scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_shift_xlate[scancode]; + } + if(ctrl==1) { /* ctrl overwrites caps_lock and shift */ + if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown ctrl scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_ctrl_xlate[scancode]; + } + /* check if valid keycode */ + if(keycode==0xff) { + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow unknown codes */ + } + + kbd_put_queue(keycode); + PRINTF("%x\n",keycode); +} + +/* + * This reads the keyboard status port, and does the + * appropriate action. + * + */ +unsigned char handle_kbd_event(void) +{ + unsigned char status = kbd_read_status(); + unsigned int work = 10000; + + while ((--work > 0) && (status & KBD_STAT_OBF)) { + unsigned char scancode; + + scancode = kbd_read_input(); + + /* Error bytes must be ignored to make the + Synaptics touchpads compaq use work */ + /* Ignore error bytes */ + if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) + { + if (status & KBD_STAT_MOUSE_OBF) + ; /* not supported: handle_mouse_event(scancode); */ + else + handle_keyboard_event(scancode); + } + status = kbd_read_status(); + } + if (!work) + PRINTF("pc_keyb: controller jammed (0x%02X).\n", status); + return status; +} + + +/****************************************************************************** + * Lowlevel Part of keyboard section + */ +unsigned char kbd_read_status(void) +{ + return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); +} + +unsigned char kbd_read_input(void) +{ + return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); +} + +void kbd_write_command(unsigned char cmd) +{ + out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); +} + +void kbd_write_output(unsigned char data) +{ + out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); +} + +int kbd_read_data(void) +{ + int val; + unsigned char status; + + val=-1; + status = kbd_read_status(); + if (status & KBD_STAT_OBF) { + val = kbd_read_input(); + if (status & (KBD_STAT_GTO | KBD_STAT_PERR)) + val = -2; + } + return val; +} + +int kbd_wait_for_input(void) +{ + unsigned long timeout; + int val; + + timeout = KBD_TIMEOUT; + val=kbd_read_data(); + while(val < 0) + { + if(timeout--==0) + return -1; + udelay(1000); + val=kbd_read_data(); + } + return val; +} + + +int kb_wait(void) +{ + unsigned long timeout = KBC_TIMEOUT * 10; + + do { + unsigned char status = handle_kbd_event(); + if (!(status & KBD_STAT_IBF)) + return 0; /* ok */ + udelay(1000); + timeout--; + } while (timeout); + return 1; +} + +void kbd_write_command_w(int data) +{ + if(kb_wait()) + PRINTF("timeout in kbd_write_command_w\n"); + kbd_write_command(data); +} + +void kbd_write_output_w(int data) +{ + if(kb_wait()) + PRINTF("timeout in kbd_write_output_w\n"); + kbd_write_output(data); +} + +void kbd_send_data(unsigned char data) +{ + unsigned char status; + disable_8259A_irq(1); /* disable interrupt */ + kbd_write_output_w(data); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + enable_8259A_irq(1); /* enable interrupt */ +} + + +char * kbd_initialize(void) +{ + int status; + + in_pointer = 0; /* delete in Buffer */ + out_pointer = 0; + /* + * Test the keyboard interface. + * This seems to be the only way to get it going. + * If the test is successful a x55 is placed in the input buffer. + */ + kbd_write_command_w(KBD_CCMD_SELF_TEST); + if (kbd_wait_for_input() != 0x55) + return "Kbd: failed self test"; + /* + * Perform a keyboard interface test. This causes the controller + * to test the keyboard clock and data lines. The results of the + * test are placed in the input buffer. + */ + kbd_write_command_w(KBD_CCMD_KBD_TEST); + if (kbd_wait_for_input() != 0x00) + return "Kbd: interface failed self test"; + /* + * Enable the keyboard by allowing the keyboard clock to run. + */ + kbd_write_command_w(KBD_CCMD_KBD_ENABLE); + status = kbd_wait_for_input(); + /* + * Reset keyboard. If the read times out + * then the assumption is that no keyboard is + * plugged into the machine. + * This defaults the keyboard to scan-code set 2. + * + * Set up to try again if the keyboard asks for RESEND. + */ + do { + kbd_write_output_w(KBD_CMD_RESET); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + break; + if (status != KBD_REPLY_RESEND) + { + PRINTF("status: %X\n",status); + return "Kbd: reset failed, no ACK"; + } + } while (1); + if (kbd_wait_for_input() != KBD_REPLY_POR) + return "Kbd: reset failed, no POR"; + + /* + * Set keyboard controller mode. During this, the keyboard should be + * in the disabled state. + * + * Set up to try again if the keyboard asks for RESEND. + */ + do { + kbd_write_output_w(KBD_CMD_DISABLE); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + break; + if (status != KBD_REPLY_RESEND) + return "Kbd: disable keyboard: no ACK"; + } while (1); + + kbd_write_command_w(KBD_CCMD_WRITE_MODE); + kbd_write_output_w(KBD_MODE_KBD_INT + | KBD_MODE_SYS + | KBD_MODE_DISABLE_MOUSE + | KBD_MODE_KCC); + + /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */ + kbd_write_command_w(KBD_CCMD_READ_MODE); + if (!(kbd_wait_for_input() & KBD_MODE_KCC)) { + /* + * If the controller does not support conversion, + * Set the keyboard to scan-code set 1. + */ + kbd_write_output_w(0xF0); + kbd_wait_for_input(); + kbd_write_output_w(0x01); + kbd_wait_for_input(); + } + kbd_write_output_w(KBD_CMD_ENABLE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: enable keyboard: no ACK"; + + /* + * Finally, set the typematic rate to maximum. + */ + kbd_write_output_w(KBD_CMD_SET_RATE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: Set rate: no ACK"; + kbd_write_output_w(0x00); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: Set rate: no ACK"; + return NULL; +} + +void kbd_interrupt(void) +{ + handle_kbd_event(); +} diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h new file mode 100644 index 0000000..229ba61 --- /dev/null +++ b/board/mpl/common/kbd.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _KBD_H_ +#define _KBD_H_ + +extern int kbd_testc(void); +extern int kbd_getc(void); +extern void kbd_interrupt(void); +extern char *kbd_initialize(void); + +unsigned char kbd_is_init(void); +#define KBD_INTERRUPT 1 +#endif diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c new file mode 100644 index 0000000..2c77d37 --- /dev/null +++ b/board/mpl/common/memtst.c @@ -0,0 +1,590 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* NOT Used yet... + add following code to PIP405.c : +int testdram (void) +{ + unsigned char s[32]; + int i; + + i = getenv_r ("testmem", s, 32); + if (i != 0) { + i = (int) simple_strtoul (s, NULL, 10); + if ((i > 0) && (i < 0xf)) { + printf ("testing "); + i = mem_test (0, ramsize, i); + if (i > 0) + printf ("ERROR "); + else + printf ("Ok "); + } + } + return (1); +} +*/ + + +#include +#include +#include <405gp_i2c.h> + +#define FALSE 0 +#define TRUE 1 + +#define TEST_QUIET 8 +#define TEST_SHOW_PROG 4 +#define TEST_SHOW_ERR 2 +#define TEST_SHOW_ALL 1 + +#define TESTPAT1 0xAA55AA55 +#define TESTPAT2 0x55AA55AA +#define TEST_PASSED 0 +#define TEST_FAILED 1 +#define MEGABYTE (1024*1024) + + +typedef struct { + volatile unsigned long pat1; + volatile unsigned long pat2; +} RAM_MEMTEST_PATTERN2; + +typedef struct { + volatile unsigned long addr; +} RAM_MEMTEST_ADDRLINE; + +static __inline unsigned long Swap_32 (unsigned long val) +{ + return (((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF)); +} + +void testm_puts (int quiet, char *buf) +{ + if ((quiet & TEST_SHOW_ALL) == TEST_SHOW_ALL) + puts (buf); +} + + +void Write_Error (int mode, unsigned long addr, unsigned long expected, + unsigned long actual) +{ + + char dispbuf[64]; + + sprintf (dispbuf, "\n ERROR @ 0x%08lX: (exp: 0x%08lX act: 0x%08lX) ", + addr, expected, actual); + testm_puts (((mode & TEST_SHOW_ERR) == + TEST_SHOW_ERR) ? TEST_SHOW_ALL : mode, dispbuf); +} + + +/* + * fills the memblock of bytes from with pat1 and pat2 + */ + + +void RAM_MemTest_WritePattern2 (unsigned long startaddr, + unsigned long size, unsigned long pat1, + unsigned long pat2) +{ + RAM_MEMTEST_PATTERN2 *p, *pe; + + p = (RAM_MEMTEST_PATTERN2 *) startaddr; + pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); + + while (p < pe) { + p->pat1 = pat1; + p->pat2 = pat2; + p++; + } /* endwhile */ +} + +/* + * checks the memblock of bytes from with pat1 and pat2 + * returns the address of the first error or NULL if all is well + */ + +void *RAM_MemTest_CheckPattern2 (int mode, unsigned long startaddr, + unsigned long size, unsigned long pat1, + unsigned long pat2) +{ + RAM_MEMTEST_PATTERN2 *p, *pe; + unsigned long actual1, actual2; + + p = (RAM_MEMTEST_PATTERN2 *) startaddr; + pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); + + while (p < pe) { + actual1 = p->pat1; + actual2 = p->pat2; + + if (actual1 != pat1) { + Write_Error (mode, (unsigned long) &(p->pat1), pat1, actual1); + return ((void *) &(p->pat1)); + } + /* endif */ + if (actual2 != pat2) { + Write_Error (mode, (unsigned long) &(p->pat2), pat2, actual2); + return ((void *) &(p->pat2)); + } + /* endif */ + p++; + } /* endwhile */ + + return (NULL); +} + +/* + * fills the memblock of bytes from with the address + */ + +void RAM_MemTest_WriteAddrLine (unsigned long startaddr, + unsigned long size, int swapped) +{ + RAM_MEMTEST_ADDRLINE *p, *pe; + + p = (RAM_MEMTEST_ADDRLINE *) startaddr; + pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); + + if (!swapped) { + while (p < pe) { + p->addr = (unsigned long) p; + p++; + } /* endwhile */ + } else { + while (p < pe) { + p->addr = Swap_32 ((unsigned long) p); + p++; + } /* endwhile */ + } /* endif */ +} + +/* + * checks the memblock of bytes from + * returns the address of the error or NULL if all is well + */ + +void *RAM_MemTest_CheckAddrLine (int mode, unsigned long startaddr, + unsigned long size, int swapped) +{ + RAM_MEMTEST_ADDRLINE *p, *pe; + unsigned long actual, expected; + + p = (RAM_MEMTEST_ADDRLINE *) startaddr; + pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); + + if (!swapped) { + while (p < pe) { + actual = p->addr; + expected = (unsigned long) p; + if (actual != expected) { + Write_Error (mode, (unsigned long) &(p->addr), expected, + actual); + return ((void *) &(p->addr)); + } /* endif */ + p++; + } /* endwhile */ + } else { + while (p < pe) { + actual = p->addr; + expected = Swap_32 ((unsigned long) p); + if (actual != expected) { + Write_Error (mode, (unsigned long) &(p->addr), expected, + actual); + return ((void *) &(p->addr)); + } /* endif */ + p++; + } /* endwhile */ + } /* endif */ + + return (NULL); +} + +/* + * checks the memblock of bytes from + * returns the address of the error or NULL if all is well + */ + +void *RAM_MemTest_CheckAddrLineReverse (int mode, unsigned long startaddr, + unsigned long size, int swapped) +{ + RAM_MEMTEST_ADDRLINE *p, *pe; + unsigned long actual, expected; + + p = (RAM_MEMTEST_ADDRLINE *) (startaddr + size - sizeof (p->addr)); + pe = (RAM_MEMTEST_ADDRLINE *) startaddr; + + if (!swapped) { + while (p > pe) { + actual = p->addr; + expected = (unsigned long) p; + if (actual != expected) { + Write_Error (mode, (unsigned long) &(p->addr), expected, + actual); + return ((void *) &(p->addr)); + } /* endif */ + p--; + } /* endwhile */ + } else { + while (p > pe) { + actual = p->addr; + expected = Swap_32 ((unsigned long) p); + if (actual != expected) { + Write_Error (mode, (unsigned long) &(p->addr), expected, + actual); + return ((void *) &(p->addr)); + } /* endif */ + p--; + } /* endwhile */ + } /* endif */ + + return (NULL); +} + +/* + * fills the memblock of bytes from with walking bit pattern + */ + +void RAM_MemTest_WriteWalkBit (unsigned long startaddr, unsigned long size) +{ + volatile unsigned long *p, *pe; + unsigned long i; + + p = (unsigned long *) startaddr; + pe = (unsigned long *) (startaddr + size); + i = 0; + + while (p < pe) { + *p = 1UL << i; + i = (i + 1 + (((unsigned long) p) >> 7)) % 32; + p++; + } /* endwhile */ +} + +/* + * checks the memblock of bytes from + * returns the address of the error or NULL if all is well + */ + +void *RAM_MemTest_CheckWalkBit (int mode, unsigned long startaddr, + unsigned long size) +{ + volatile unsigned long *p, *pe; + unsigned long actual, expected; + unsigned long i; + + p = (unsigned long *) startaddr; + pe = (unsigned long *) (startaddr + size); + i = 0; + + while (p < pe) { + actual = *p; + expected = (1UL << i); + if (actual != expected) { + Write_Error (mode, (unsigned long) p, expected, actual); + return ((void *) p); + } /* endif */ + i = (i + 1 + (((unsigned long) p) >> 7)) % 32; + p++; + } /* endwhile */ + + return (NULL); +} + +/* + * fills the memblock of bytes from with "random" pattern + */ + +void RAM_MemTest_WriteRandomPattern (unsigned long startaddr, + unsigned long size, + unsigned long *pat) +{ + unsigned long i, p; + + p = *pat; + + for (i = 0; i < (size / 4); i++) { + *(unsigned long *) (startaddr + i * 4) = p; + if ((p % 2) > 0) { + p ^= i; + p >>= 1; + p |= 0x80000000; + } else { + p ^= ~i; + p >>= 1; + } /* endif */ + } /* endfor */ + *pat = p; +} + +/* + * checks the memblock of bytes from + * returns the address of the error or NULL if all is well + */ + +void *RAM_MemTest_CheckRandomPattern (int mode, unsigned long startaddr, + unsigned long size, + unsigned long *pat) +{ + void *perr = NULL; + unsigned long i, p, p1; + + p = *pat; + + for (i = 0; i < (size / 4); i++) { + p1 = *(unsigned long *) (startaddr + i * 4); + if (p1 != p) { + if (perr == NULL) { + Write_Error (mode, startaddr + i * 4, p, p1); + perr = (void *) (startaddr + i * 4); + } /* endif */ + } + /* endif */ + if ((p % 2) > 0) { + p ^= i; + p >>= 1; + p |= 0x80000000; + } else { + p ^= ~i; + p >>= 1; + } /* endif */ + } /* endfor */ + + *pat = p; + return (perr); +} + + +void RAM_MemTest_WriteData1 (unsigned long startaddr, unsigned long size, + unsigned long *pat) +{ + RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT1, TESTPAT2); +} + +void *RAM_MemTest_CheckData1 (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat) +{ + return (RAM_MemTest_CheckPattern2 + (mode, startaddr, size, TESTPAT1, TESTPAT2)); +} + +void RAM_MemTest_WriteData2 (unsigned long startaddr, unsigned long size, + unsigned long *pat) +{ + RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT2, TESTPAT1); +} + +void *RAM_MemTest_CheckData2 (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat) +{ + return (RAM_MemTest_CheckPattern2 + (mode, startaddr, size, TESTPAT2, TESTPAT1)); +} + +void RAM_MemTest_WriteAddr1 (unsigned long startaddr, unsigned long size, + unsigned long *pat) +{ + RAM_MemTest_WriteAddrLine (startaddr, size, FALSE); +} + +void *RAM_MemTest_Check1Addr1 (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat) +{ + return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, FALSE)); +} + +void *RAM_MemTest_Check2Addr1 (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat) +{ + return (RAM_MemTest_CheckAddrLineReverse + (mode, startaddr, size, FALSE)); +} + +void RAM_MemTest_WriteAddr2 (unsigned long startaddr, unsigned long size, + unsigned long *pat) +{ + RAM_MemTest_WriteAddrLine (startaddr, size, TRUE); +} + +void *RAM_MemTest_Check1Addr2 (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat) +{ + return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, TRUE)); +} + +void *RAM_MemTest_Check2Addr2 (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat) +{ + return (RAM_MemTest_CheckAddrLineReverse + (mode, startaddr, size, TRUE)); +} + + +typedef struct { + void (*test_write) (unsigned long startaddr, unsigned long size, + unsigned long *pat); + char *test_write_desc; + void *(*test_check1) (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat); + void *(*test_check2) (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat); +} RAM_MEMTEST_FUNC; + + +#define TEST_STAGES 5 +static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = { + {RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1, + NULL}, + {RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2, + NULL}, + {RAM_MemTest_WriteAddr1, "address line test...\n", + RAM_MemTest_Check1Addr1, RAM_MemTest_Check2Addr1}, + {RAM_MemTest_WriteAddr2, "address line test (swapped)...\n", + RAM_MemTest_Check1Addr2, RAM_MemTest_Check2Addr2}, + {RAM_MemTest_WriteRandomPattern, "random data test...\n", + RAM_MemTest_CheckRandomPattern, NULL} +}; + +void mem_test_reloc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long addr; + int i; + for (i=0; i< TEST_STAGES; i++) { + addr = (ulong) (test_stage[i].test_write) + gd->reloc_off; + test_stage[i].test_write= + (void (*) (unsigned long startaddr, unsigned long size, + unsigned long *pat))addr; + addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off; + test_stage[i].test_write_desc=(char *)addr; + if(test_stage[i].test_check1) { + addr = (ulong) (test_stage[i].test_check1) + gd->reloc_off; + test_stage[i].test_check1= + (void *(*) (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat))addr; + } + if(test_stage[i].test_check2) { + addr = (ulong) (test_stage[i].test_check2) + gd->reloc_off; + test_stage[i].test_check2= + (void *(*) (int mode, unsigned long startaddr, + unsigned long size, unsigned long *pat))addr; + } + } +} + + +int mem_test (unsigned long start, unsigned long ramsize, int quiet) +{ + unsigned long errors, stage; + unsigned long startaddr, size, i; + const unsigned long blocksize = 0x80000; /* check in 512KB blocks */ + unsigned long *perr; + unsigned long rdatapat; + char dispbuf[80]; + int status = TEST_PASSED; + int prog = 0; + + errors = 0; + startaddr = start; + size = ramsize; + if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { + prog++; + printf ("."); + } + sprintf (dispbuf, "\nMemory Test: addr = 0x%lx size = 0x%lx\n", + startaddr, size); + testm_puts (quiet, dispbuf); + for (stage = 0; stage < TEST_STAGES; stage++) { + sprintf (dispbuf, test_stage[stage].test_write_desc); + testm_puts (quiet, dispbuf); + /* fill SDRAM */ + rdatapat = 0x12345678; + sprintf (dispbuf, "writing block: "); + testm_puts (quiet, dispbuf); + for (i = 0; i < size; i += blocksize) { + sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); + testm_puts (quiet, dispbuf); + test_stage[stage].test_write (startaddr + i, blocksize, + &rdatapat); + } /* endfor */ + sprintf (dispbuf, "\n"); + testm_puts (quiet, dispbuf); + if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { + prog++; + printf ("."); + } + /* check SDRAM */ + rdatapat = 0x12345678; + sprintf (dispbuf, "checking block: "); + testm_puts (quiet, dispbuf); + for (i = 0; i < size; i += blocksize) { + sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); + testm_puts (quiet, dispbuf); + if ((perr = + test_stage[stage].test_check1 (quiet, startaddr + i, + blocksize, + &rdatapat)) != NULL) { + status = TEST_FAILED; + } /* endif */ + } /* endfor */ + sprintf (dispbuf, "\n"); + testm_puts (quiet, dispbuf); + if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { + prog++; + printf ("."); + } + if (test_stage[stage].test_check2 != NULL) { + /* check2 SDRAM */ + sprintf (dispbuf, "2nd checking block: "); + rdatapat = 0x12345678; + testm_puts (quiet, dispbuf); + for (i = 0; i < size; i += blocksize) { + sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); + testm_puts (quiet, dispbuf); + if ((perr = + test_stage[stage].test_check2 (quiet, startaddr + i, + blocksize, + &rdatapat)) != NULL) { + status = TEST_FAILED; + } /* endif */ + } /* endfor */ + sprintf (dispbuf, "\n"); + testm_puts (quiet, dispbuf); + if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { + prog++; + printf ("."); + } + } + + } /* next stage */ + if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { + while (prog-- > 0) + printf ("\b \b"); + } + + if (status == TEST_FAILED) + errors++; + + return (errors); +} diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c new file mode 100644 index 0000000..692930b --- /dev/null +++ b/board/mpl/common/pci.c @@ -0,0 +1,126 @@ +/*-----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1995 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++-----------------------------------------------------------------------------*/ +/* + * Adapted for PIP405 03.07.01 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * TODO: Clean-up + */ + +#include +#include +#include "isa.h" + +#ifdef CONFIG_405GP +#ifdef CONFIG_PCI + +#undef DEBUG + +#include "piix4_pci.h" +#include "pci_parts.h" + +void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) +{ + struct pci_pip405_config_entry *table; + int i; + + table = (struct pci_pip405_config_entry*) entry->priv[0]; + + for (i=0; table[i].width; i++) + { +#ifdef DEBUG + printf("Reg 0x%02X Value 0x%08lX Width %02d written\n", + table[i].index, table[i].val, table[i].width); +#endif + + switch(table[i].width) + { + case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break; + case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break; + case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break; + } + } +} + + +static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line = 0xff; + unsigned char pin; + /* + * Write pci interrupt line register + */ + if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */ + return; + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); + if ((pin == 0) || (pin > 4)) + return; + + int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); +#ifdef DEBUG + printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", + PCI_DEV(dev),dev,int_line,int_line); +#endif +} + +extern void pci_405gp_init(struct pci_controller *hose); + + +static struct pci_controller hose = { + config_table: pci_pip405_config_table, + fixup_irq: pci_pip405_fixup_irq, +}; + + +static void reloc_pci_cfg_table(struct pci_config_table *table) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long addr; + + for (; table && table->vendor; table++) { + addr = (ulong) (table->config_device) + gd->reloc_off; +#ifdef DEBUG + printf ("device \"%d\": 0x%08lx => 0x%08lx\n", + table->device, (ulong) (table->config_device), addr); +#endif + table->config_device = + (void (*)(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *))addr; + table->priv[0]+=gd->reloc_off; + } +} + +void pci_init_board(void) +{ + /*we want the ptrs to RAM not flash (ie don't use init list)*/ + hose.fixup_irq = pci_pip405_fixup_irq; + hose.config_table = pci_pip405_config_table; + reloc_pci_cfg_table(hose.config_table); +#ifdef DEBUG + printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); +#endif + pci_405gp_init(&hose); +} + +#endif /* CONFIG_PCI */ +#endif /* CONFIG_405GP */ diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h new file mode 100644 index 0000000..60008e2 --- /dev/null +++ b/board/mpl/common/pci_parts.h @@ -0,0 +1,193 @@ + /* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _PCI_PARTS_H_ +#define _PCI_PARTS_H_ + + +/* Board specific file containing: + * - PCI Memory Mapping + * - PCI IO Mapping + * - PCI Interrupt Mapping + */ + +/* PIP405 PCI INT Routing: + * IRQ0 VECTOR + * PIXX4 IDSEL = AD16 INTA# 28 (Function 2 USB is INTD# = 31) + * VGA IDSEL = AD17 INTB# 29 + * SCSI IDSEL = AD18 INTC# 30 + * PC104 IDSEL0 = AD20 INTA# 28 + * PC104 IDSEL1 = AD21 INTB# 29 + * PC104 IDSEL2 = AD22 INTC# 30 + * PC104 IDSEL3 = AD23 INTD# 31 + * + * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00 + * ^ ^ ^ ^ ^ + * 31 23 15 10 7 + * E = Enabled + * B = Bussnumber + * D = Devicenumber (Device0 = AD10) + * F = Functionnumber + * R = Registernumber + * + * Device = (busdevfunc>>11) + 10 + * Vector = devicenumber % 4 + 28 + * + */ +#define PCI_HIGHEST_ON_BOARD_ID 19 +/*#define PCI_DEV_NUMBER(x) (((x>>11) & 0x1f) + 10) */ +#define PCI_IRQ_VECTOR(x) ((PCI_DEV(x) + 10) % 4) + 28 + + +/* PCI Device List for PIP405 */ + +/* Mapping: + * +-------------+------------+------------+--------------------------------+ + * Ĥ PCI MemAddr | PCI IOAddr | Local Addr | Device / Function | + * +-------------+------------+------------+--------------------------------+ + * | 0x00000000 | | 0xA0000000 | ISA Memory (hard wired) | + * | 0x00FFFFFF | | 0xA0FFFFFF | | + * +-------------+------------+------------+--------------------------------+ + * | | 0x00000000 | 0xE8000000 | ISA IO (hard wired) | + * | | 0x0000FFFF | 0xE800FFFF | | + * +-------------+------------+------------+--------------------------------+ + * | 0x80000000 | | 0x80000000 | VGA Controller Memory | + * | 0x80FFFFFF | | 0x80FFFFFF | | + * +-------------+------------+------------+--------------------------------+ + * | 0x81000000 | | 0x81000000 | SCSI Controller Memory | + * | 0x81FFFFFF | | 0x81FFFFFF | | + * +-------------+------------+------------+--------------------------------+ + */ + +struct pci_pip405_config_entry { + int index; /* address */ + unsigned long val; /* value */ + int width; /* data size */ +}; + +extern void pci_pip405_write_regs(struct pci_controller *, + pci_dev_t, + struct pci_config_table *); + +/* PIIX4 ISA Bridge Function 0 */ +static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = { + {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */ + {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */ + {PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */ + {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */ + {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */ +#if defined(CONFIG_PIP405) + {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */ + {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */ +#endif + {PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */ + { } /* end of device table */ +}; + +/* PIIX4 IDE Controller Function 1 */ +static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = { + {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */ + {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ +#if !defined(CONFIG_MIP405T) + {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */ +#else + {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */ +#endif + { } /* end of device table */ +}; + +/* PIIX4 USB Controller Function 2 */ +static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = { +#if !defined(CONFIG_MIP405T) + {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */ + {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */ + {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */ + {0xC0, 0x2000, 2}, /* Legacy support */ + {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */ +#endif + { } /* end of device table */ +}; + +/* PIIX4 Power Management Function 3 */ +static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = { + {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */ + {PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */ + {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */ + {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ + { } /* end of device table */ +}; +/* PPC405 Dummy only used to prevent autosetup on this host bridge */ +static struct pci_pip405_config_entry ppc405_dummy[] = { + { } /* end of device table */ +}; + +void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry); + + +static struct pci_config_table pci_pip405_config_table[]={ + {PCI_VENDOR_ID_IBM, /* 405 dummy */ + PCI_DEVICE_ID_IBM_405GP, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 0, + pci_pip405_write_regs, {(unsigned long) ppc405_dummy}}, + + {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */ + PCI_DEVICE_ID_INTEL_82371AB_0, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 0, + pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}}, + + {PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */ + PCI_DEVICE_ID_INTEL_82371AB, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 1, + pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}}, + + {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */ + PCI_DEVICE_ID_INTEL_82371AB_2, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 2, + pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}}, + + {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 3 */ + PCI_DEVICE_ID_INTEL_82371AB_3, + PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, 3, + pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}}, + + {PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_405gp_setup_vga}, + + {PCI_ANY_ID, + PCI_ANY_ID, + PCI_CLASS_NOT_DEFINED_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_405gp_setup_vga}, + + { } +}; +#endif /* _PCI_PARTS_H_ */ diff --git a/board/mpl/common/piix4_pci.h b/board/mpl/common/piix4_pci.h new file mode 100644 index 0000000..0ff802e --- /dev/null +++ b/board/mpl/common/piix4_pci.h @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef _PIIX4_PCI_H +#define _PIIX4_PCI_H + +/*************************************************************************** +* Defines PIIX4 Config Registers +****************************************************************************/ + +/* Function 0 ISA Bridge */ +#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ +#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ +#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ +#define PCI_CFG_PIIX4_SERIRQ 0x64 +#define PCI_CFG_PIIX4_TOM 0x69 +#define PCI_CFG_PIIX4_MSTAT 0x6A +#define PCI_CFG_PIIX4_MBDMA 0x76 +#define PCI_CFG_PIIX4_APICBS 0x80 +#define PCI_CFG_PIIX4_DLC 0x82 +#define PCI_CFG_PIIX4_PDMACFG 0x90 +#define PCI_CFG_PIIX4_DDMABS 0x92 +#define PCI_CFG_PIIX4_GENCFG 0xB0 +#define PCI_CFG_PIIX4_RTCCFG 0xCB + +/* IO Addresses */ +#define PIIX4_ISA_DMA1_CH0BA 0x00 +#define PIIX4_ISA_DMA1_CH0CA 0x01 +#define PIIX4_ISA_DMA1_CH1BA 0x02 +#define PIIX4_ISA_DMA1_CH1CA 0x03 +#define PIIX4_ISA_DMA1_CH2BA 0x04 +#define PIIX4_ISA_DMA1_CH2CA 0x05 +#define PIIX4_ISA_DMA1_CH3BA 0x06 +#define PIIX4_ISA_DMA1_CH3CA 0x07 +#define PIIX4_ISA_DMA1_CMDST 0x08 +#define PIIX4_ISA_DMA1_REQ 0x09 +#define PIIX4_ISA_DMA1_WSBM 0x0A +#define PIIX4_ISA_DMA1_CH_MOD 0x0B +#define PIIX4_ISA_DMA1_CLR_PT 0x0C +#define PIIX4_ISA_DMA1_M_CLR 0x0D +#define PIIX4_ISA_DMA1_CLR_M 0x0E +#define PIIX4_ISA_DMA1_RWAMB 0x0F + +#define PIIX4_ISA_DMA2_CH0BA 0xC0 +#define PIIX4_ISA_DMA2_CH0CA 0xC1 +#define PIIX4_ISA_DMA2_CH1BA 0xC2 +#define PIIX4_ISA_DMA2_CH1CA 0xC3 +#define PIIX4_ISA_DMA2_CH2BA 0xC4 +#define PIIX4_ISA_DMA2_CH2CA 0xC5 +#define PIIX4_ISA_DMA2_CH3BA 0xC6 +#define PIIX4_ISA_DMA2_CH3CA 0xC7 +#define PIIX4_ISA_DMA2_CMDST 0xD0 +#define PIIX4_ISA_DMA2_REQ 0xD2 +#define PIIX4_ISA_DMA2_WSBM 0xD4 +#define PIIX4_ISA_DMA2_CH_MOD 0xD6 +#define PIIX4_ISA_DMA2_CLR_PT 0xD8 +#define PIIX4_ISA_DMA2_M_CLR 0xDA +#define PIIX4_ISA_DMA2_CLR_M 0xDC +#define PIIX4_ISA_DMA2_RWAMB 0xDE + +#define PIIX4_ISA_INT1_ICW1 0x20 +#define PIIX4_ISA_INT1_OCW2 0x20 +#define PIIX4_ISA_INT1_OCW3 0x20 +#define PIIX4_ISA_INT1_ICW2 0x21 +#define PIIX4_ISA_INT1_ICW3 0x21 +#define PIIX4_ISA_INT1_ICW4 0x21 +#define PIIX4_ISA_INT1_OCW1 0x21 + +#define PIIX4_ISA_INT1_ELCR 0x4D0 + +#define PIIX4_ISA_INT2_ICW1 0xA0 +#define PIIX4_ISA_INT2_OCW2 0xA0 +#define PIIX4_ISA_INT2_OCW3 0xA0 +#define PIIX4_ISA_INT2_ICW2 0xA1 +#define PIIX4_ISA_INT2_ICW3 0xA1 +#define PIIX4_ISA_INT2_ICW4 0xA1 +#define PIIX4_ISA_INT2_OCW1 0xA1 +#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ + +#define PIIX4_ISA_INT2_ELCR 0x4D1 + +#define PIIX4_ISA_TMR0_CNT_ST 0x40 +#define PIIX4_ISA_TMR1_CNT_ST 0x41 +#define PIIX4_ISA_TMR2_CNT_ST 0x42 +#define PIIX4_ISA_TMR_TCW 0x43 + +#define PIIX4_ISA_RST_XBUS 0x60 + +#define PIIX4_ISA_NMI_CNT_ST 0x61 +#define PIIX4_ISA_NMI_ENABLE 0x70 + +#define PIIX4_ISA_RTC_INDEX 0x70 +#define PIIX4_ISA_RTC_DATA 0x71 +#define PIIX4_ISA_RTCEXT_IND 0x70 +#define PIIX4_ISA_RTCEXT_DATA 0x71 + +#define PIIX4_ISA_DMA1_CH2LPG 0x81 +#define PIIX4_ISA_DMA1_CH3LPG 0x82 +#define PIIX4_ISA_DMA1_CH1LPG 0x83 +#define PIIX4_ISA_DMA1_CH0LPG 0x87 +#define PIIX4_ISA_DMA2_CH2LPG 0x89 +#define PIIX4_ISA_DMA2_CH3LPG 0x8A +#define PIIX4_ISA_DMA2_CH1LPG 0x8B +#define PIIX4_ISA_DMA2_LPGRFR 0x8F + +#define PIIX4_ISA_PORT_92 0x92 + +#define PIIX4_ISA_APM_CONTRL 0xB2 +#define PIIX4_ISA_APM_STATUS 0xB3 + +#define PIIX4_ISA_COCPU_ERROR 0xF0 + +/* Function 1 IDE Controller */ +#define PCI_CFG_PIIX4_BMIBA 0x20 +#define PCI_CFG_PIIX4_IDETIM 0x40 +#define PCI_CFG_PIIX4_SIDETIM 0x44 +#define PCI_CFG_PIIX4_UDMACTL 0x48 +#define PCI_CFG_PIIX4_UDMATIM 0x4A + +/* Function 2 USB Controller */ +#define PCI_CFG_PIIX4_SBRNUM 0x60 +#define PCI_CFG_PIIX4_LEGSUP 0xC0 + +/* Function 3 Power Management */ +#define PCI_CFG_PIIX4_PMBA 0x40 +#define PCI_CFG_PIIX4_CNTA 0x44 +#define PCI_CFG_PIIX4_CNTB 0x48 +#define PCI_CFG_PIIX4_GPICTL 0x4C +#define PCI_CFG_PIIX4_DEVRESD 0x50 +#define PCI_CFG_PIIX4_DEVACTA 0x54 +#define PCI_CFG_PIIX4_DEVACTB 0x58 +#define PCI_CFG_PIIX4_DEVRESA 0x5C +#define PCI_CFG_PIIX4_DEVRESB 0x60 +#define PCI_CFG_PIIX4_DEVRESC 0x64 +#define PCI_CFG_PIIX4_DEVRESE 0x68 +#define PCI_CFG_PIIX4_DEVRESF 0x6C +#define PCI_CFG_PIIX4_DEVRESG 0x70 +#define PCI_CFG_PIIX4_DEVRESH 0x74 +#define PCI_CFG_PIIX4_DEVRESI 0x78 +#define PCI_CFG_PIIX4_PMMISC 0x80 +#define PCI_CFG_PIIX4_SMBBA 0x90 + + +#endif diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c new file mode 100644 index 0000000..84c91c4 --- /dev/null +++ b/board/mpl/common/usb_uhci.c @@ -0,0 +1,1169 @@ +/* + * Part of this code has been derived from linux: + * Universal Host Controller Interface driver for USB (take II). + * + * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar) + * Deti Fliegl, deti@fliegl.de (executive slave) (lead voice) + * Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader) + * Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter) + * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support + * from usb-ohci.c by Adam Richter, adam@yggdrasil.com). + * (C) 2000 David Brownell, david-b@pacbell.net (usb-ohci.c) + * + * HW-initalization based on material of + * + * (C) Copyright 1999 Linus Torvalds + * (C) Copyright 1999 Johannes Erdfelt + * (C) Copyright 1999 Randy Dunlap + * (C) Copyright 1999 Gregory P. Smith + * + * + * Adapted for U-Boot: + * (C) Copyright 2001 Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + */ + +/********************************************************************** + * How it works: + * ------------- + * The framelist / Transfer descriptor / Queue Heads are similar like + * in the linux usb_uhci.c. + * + * During initialization, the following skeleton is allocated in init_skel: + * + * framespecific | common chain + * + * framelist[] + * [ 0 ]-----> TD ---------\ + * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL + * ... TD ---------/ + * [1023]-----> TD --------/ + * + * ^^ ^^ ^^ ^^ ^^ + * 7 TDs for 1 TD for Start of Start of End Chain + * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain + * + * + * Since this is a bootloader, the isochronous transfer descriptor have been removed. + * + * Interrupt Transfers. + * -------------------- + * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They + * will be inserted after the appropriate (depending the interval setting) skeleton TD. + * If an interrupt has been detected the dev->irqhandler is called. The status and number + * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the + * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned, + * the interrupt TD will be reactivated. + * + * Control Transfers + * ----------------- + * Control Transfers are issued by filling the tmp_td with the appropriate data and connect + * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued, + * the programm has to wait for completion. This does not allows asynchronous data transfer. + * + * Bulk Transfers + * -------------- + * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect + * them to the qh_bulk queue header. Before other control/bulk transfers can be issued, + * the programm has to wait for completion. This does not allows asynchronous data transfer. + * + * + */ + +#include +#include + +#ifdef CONFIG_USB_UHCI + +#include +#include "usb_uhci.h" + +#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */ +#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */ + + +#undef USB_UHCI_DEBUG + +#ifdef USB_UHCI_DEBUG +#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define USB_UHCI_PRINTF(fmt,args...) +#endif + + +static int irqvec = -1; /* irq vector, if -1 uhci is stopped / reseted */ +unsigned int usb_base_addr; /* base address */ + +static uhci_td_t td_int[8]; /* Interrupt Transfer descriptors */ +static uhci_qh_t qh_cntrl; /* control Queue Head */ +static uhci_qh_t qh_bulk; /* bulk Queue Head */ +static uhci_qh_t qh_end; /* end Queue Head */ +static uhci_td_t td_last; /* last TD (linked with end chain) */ + +/* temporary tds */ +static uhci_td_t tmp_td[USB_MAX_TEMP_TD]; /* temporary bulk/control td's */ +static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD]; /* temporary interrupt td's */ + +static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */ + +static struct virt_root_hub rh; /* struct for root hub */ + +/********************************************************************** + * some forward decleration + */ +int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len,struct devrequest *setup); + +/* fill a td with the approproiate data. Link, status, info and buffer + * are used by the USB controller itselfes, dev is used to identify the + * "connected" device + */ +void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status, + unsigned long info, unsigned long buffer, unsigned long dev) +{ + td->link=swap_32(link); + td->status=swap_32(status); + td->info=swap_32(info); + td->buffer=swap_32(buffer); + td->dev_ptr=dev; +} + +/* fill a qh with the approproiate data. Head and element are used by the USB controller + * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh. + * Please note, that after completion of the td chain, the entry element is removed / + * marked invalid by the USB controller. + */ +void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element) +{ + qh->head=swap_32(head); + qh->element=swap_32(element); + qh->dev_ptr=0L; +} + +/* get the status of a td->status + */ +unsigned long usb_uhci_td_stat(unsigned long status) +{ + unsigned long result=0; + result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0; + result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0; + result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0; + result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0; + result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0; + result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0; + result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0; + return result; +} + +/* get the status and the transfered len of a td chain. + * called from the completion handler + */ +int usb_get_td_status(uhci_td_t *td,struct usb_device *dev) +{ + unsigned long temp,info; + unsigned long stat; + uhci_td_t *mytd=td; + + if(dev->devnum==rh.devnum) + return 0; + dev->act_len=0; + stat=0; + do { + temp=swap_32((unsigned long)mytd->status); + stat=usb_uhci_td_stat(temp); + info=swap_32((unsigned long)mytd->info); + if(((info & 0xff)!= USB_PID_SETUP) && + (((info >> 21) & 0x7ff)!= 0x7ff) && + (temp & 0x7FF)!=0x7ff) + { /* if not setup and not null data pack */ + dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */ + } + if(stat) { /* status no ok */ + dev->status=stat; + return -1; + } + temp=swap_32((unsigned long)mytd->link); + mytd=(uhci_td_t *)(temp & 0xfffffff0); + }while((temp & 0x1)==0); /* process all TDs */ + dev->status=stat; + return 0; /* Ok */ +} + + +/*------------------------------------------------------------------- + * LOW LEVEL STUFF + * assembles QHs und TDs for control, bulk and iso + *-------------------------------------------------------------------*/ + +/* Submits a control message. That is a Setup, Data and Status transfer. + * Routine does not wait for completion. + */ +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len,struct devrequest *setup) +{ + unsigned long destination, status; + int maxsze = usb_maxpacket(dev, pipe); + unsigned long dataptr; + int len; + int pktsze; + int i=0; + + if (!maxsze) { + USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe); + return -1; + } + if(((pipe>>8)&0x7f)==rh.devnum) { + /* this is the root hub -> redirect it */ + return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup); + } + USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze); + /* The "pipe" thing contains the destination in bits 8--18 */ + destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */ + /* 3 errors */ + status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); + /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */ + /* Build the TD for the control request, try forever, 8 bytes of data */ + usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev); +#if 0 + { + char *sp=(char *)setup; + printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe, + sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]); + } +#endif + dataptr = (unsigned long)buffer; + len=transfer_len; + + /* If direction is "send", change the frame from SETUP (0x2D) + to OUT (0xE1). Else change it from SETUP to IN (0x69). */ + destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN); + while (len > 0) { + /* data stage */ + pktsze = len; + i++; + if (pktsze > maxsze) + pktsze = maxsze; + destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */ + usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ + tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); + + dataptr += pktsze; + len -= pktsze; + } + + /* Build the final TD for control status */ + /* It's only IN if the pipe is out AND we aren't expecting data */ + + destination &= ~UHCI_PID; + if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0)) + destination |= USB_PID_IN; + else + destination |= USB_PID_OUT; + destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */ + i++; + status &=~TD_CTRL_SPD; + /* no limit on errors on final packet , 0 bytes of data */ + usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev); + tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); /* queue status td */ + /* usb_show_td(i+1);*/ + USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i); + /* first mark the control QH element terminated */ + qh_cntrl.element=0xffffffffL; + /* set qh active */ + qh_cntrl.dev_ptr=(unsigned long)dev; + /* fill in tmp_td_chain */ + qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]); + return 0; +} + +/*------------------------------------------------------------------- + * Prepare TDs for bulk transfers. + */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len) +{ + unsigned long destination, status,info; + unsigned long dataptr; + int maxsze = usb_maxpacket(dev, pipe); + int len; + int i=0; + + if(transfer_len < 0) { + printf("Negative transfer length in submit_bulk\n"); + return -1; + } + if (!maxsze) + return -1; + /* The "pipe" thing contains the destination in bits 8--18. */ + destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe); + /* 3 errors */ + status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); + /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */ + /* Build the TDs for the bulk request */ + len = transfer_len; + dataptr = (unsigned long)buffer; + do { + int pktsze = len; + if (pktsze > maxsze) + pktsze = maxsze; + /* pktsze bytes of data */ + info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) | + (usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE); + + if((len-pktsze)==0) + status |= TD_CTRL_IOC; /* last one generates INT */ + + usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ + if(i>0) + tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); + i++; + dataptr += pktsze; + len -= pktsze; + usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); + } while (len > 0); + /* first mark the bulk QH element terminated */ + qh_bulk.element=0xffffffffL; + /* set qh active */ + qh_bulk.dev_ptr=(unsigned long)dev; + /* fill in tmp_td_chain */ + qh_bulk.element=swap_32((unsigned long)&tmp_td[0]); + return 0; +} + + +/* search a free interrupt td + */ +uhci_td_t *uhci_alloc_int_td(void) +{ + int i; + for(i=0;i free TD */ + return &tmp_int_td[i]; + } + return NULL; +} + +#if 0 +void uhci_show_temp_int_td(void) +{ + int i; + for(i=0;i free TD */ + printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr); + } + printf("all others temp_tds are free\n"); +} +#endif +/*------------------------------------------------------------------- + * submits USB interrupt (ie. polling ;-) + */ +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval) +{ + int nint, n; + unsigned long status, destination; + unsigned long info,tmp; + uhci_td_t *mytd; + if (interval < 0 || interval >= 256) + return -1; + + if (interval == 0) + nint = 0; + else { + for (nint = 0, n = 1; nint <= 8; nint++, n += n) /* round interval down to 2^n */ + { + if(interval < n) { + interval = n / 2; + break; + } + } + nint--; + } + + USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint); + mytd=uhci_alloc_int_td(); + if(mytd==NULL) { + printf("No free INT TDs found\n"); + return -1; + } + status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27); +/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27); +*/ + + destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21); + + info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE); + tmp = swap_32(td_int[nint].link); + usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev); + /* Link it */ + tmp = swap_32((unsigned long)mytd); + td_int[nint].link=tmp; + + usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); + + return 0; +} + +/********************************************************************** + * Low Level functions + */ + + +void reset_hc(void) +{ + + /* Global reset for 100ms */ + out16r( usb_base_addr + USBPORTSC1,0x0204); + out16r( usb_base_addr + USBPORTSC2,0x0204); + out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS); + /* Turn off all interrupts */ + out16r(usb_base_addr + USBINTR,0); + wait_ms(50); + out16r( usb_base_addr + USBCMD,0); + wait_ms(10); +} + +void start_hc(void) +{ + int timeout = 1000; + + while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) { + if (!--timeout) { + printf("USBCMD_HCRESET timed out!\n"); + break; + } + } + /* Turn on all interrupts */ + out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP); + /* Start at frame 0 */ + out16r(usb_base_addr + USBFRNUM,0); + /* set Framebuffer base address */ + out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist); + /* Run and mark it configured with a 64-byte max packet */ + out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP); +} + +/* Initialize the skeleton + */ +void usb_init_skel(void) +{ + unsigned long temp; + int n; + + for(n=0;nstatus & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ + qh_cntrl.dev_ptr=0; + } + } + /* now process the bulk */ + if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */ + { + dev=(struct usb_device *)qh_bulk.dev_ptr; + usb_get_td_status(&tmp_td[0],dev); /* update status */ + if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ + qh_bulk.dev_ptr=0; + } + } +} + +/* check the interrupt chain, ubdate the status of the appropriate device, + * call the appropriate irqhandler and reactivate the TD if the irqhandler + * returns with 1 + */ +void usb_check_int_chain(void) +{ + int i,res; + unsigned long link,status; + struct usb_device *dev; + uhci_td_t *td,*prevtd; + + for(i=0;i<8;i++) { + prevtd=&td_int[i]; /* the first previous td is the skeleton td */ + link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */ + td=(uhci_td_t *)link; /* assign it */ + /* all interrupt TDs are finally linked to the td_int[0]. + * so we process all until we find the td_int[0]. + * if int0 chain points to a QH, we're also done + */ + while(((i>0) && (link != (unsigned long)&td_int[0])) || + ((i==0) && !(swap_32(td->link) & UHCI_PTR_QH))) + { + /* check if a device is assigned with this td */ + status=swap_32(td->status); + if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) { + /* td is not active and a device is assigned -> call irqhandler */ + dev=(struct usb_device *)td->dev_ptr; + dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */ + dev->irq_status=usb_uhci_td_stat(status); /* get status */ + res=dev->irq_handle(dev); /* call irqhandler */ + if(res==1) { + /* reactivate */ + status|=TD_CTRL_ACTIVE; + td->status=swap_32(status); + prevtd=td; /* previous td = this td */ + } + else { + prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */ + /* remove device pointer */ + td->dev_ptr=0L; + } + } /* if we call the irq handler */ + link=swap_32(td->link) & 0xfffffff0; /* next in chain */ + td=(uhci_td_t *)link; /* assign it */ + } /* process all td in this int chain */ + } /* next interrupt chain */ +} + + +/* usb interrupt service routine. + */ +void handle_usb_interrupt(void) +{ + unsigned short status; + + /* + * Read the interrupt status, and write it back to clear the + * interrupt cause + */ + + status = in16r(usb_base_addr + USBSTS); + + if (!status) /* shared interrupt, not mine */ + return; + if (status != 1) { + /* remove host controller halted state */ + if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) { + out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD)); + } + } + usb_check_int_chain(); /* call interrupt handlers for int tds */ + usb_check_skel(); /* call completion handler for common transfer routines */ + out16r(usb_base_addr+USBSTS,status); +} + + +/* init uhci + */ +int usb_lowlevel_init(void) +{ + unsigned char temp; + int busdevfunc; + + busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */ + if(busdevfunc==-1) { + printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID); + return -1; + } + pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp); + irqvec = temp; + irq_free_handler(irqvec); + USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec); + pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp); + USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp); + pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr); + USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr); + usb_base_addr&=0xFFFFFFF0; + usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS; + rh.devnum = 0; + usb_init_skel(); + reset_hc(); + start_hc(); + irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL); + return 0; +} + +/* stop uhci + */ +int usb_lowlevel_stop(void) +{ + if(irqvec==-1) + return 1; + irq_free_handler(irqvec); + reset_hc(); + irqvec=-1; + return 0; +} + +/******************************************************************************************* + * Virtual Root Hub + * Since the uhci does not have a real HUB, we simulate one ;-) + */ +#undef USB_RH_DEBUG + +#ifdef USB_RH_DEBUG +#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args) +static void usb_display_wValue(unsigned short wValue,unsigned short wIndex); +static void usb_display_Req(unsigned short req); +#else +#define USB_RH_PRINTF(fmt,args...) +static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {} +static void usb_display_Req(unsigned short req) {} +#endif + +static unsigned char root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x00, /* __u16 bcdUSB; v1.0 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x01, /* __u8 iManufacturer; */ + 0x00, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + + +/* Configuration descriptor */ +static unsigned char root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + + +static unsigned char root_hub_hub_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x29, /* __u8 bDescriptorType; Hub-descriptor */ + 0x02, /* __u8 bNbrPorts; */ + 0x00, /* __u16 wHubCharacteristics; */ + 0x00, + 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ + 0x00, /* __u8 bHubContrCurrent; 0 mA */ + 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ + 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'U', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + + +/* + * Root Hub Control Pipe (interrupt Pipes are not supported) + */ + + +int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd) +{ + void *data = buffer; + int leni = transfer_len; + int len = 0; + int status = 0; + int stat = 0; + int i; + + unsigned short cstatus; + + unsigned short bmRType_bReq; + unsigned short wValue; + unsigned short wIndex; + unsigned short wLength; + + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + printf("Root-Hub submit IRQ: NOT implemented\n"); +#if 0 + uhci->rh.urb = urb; + uhci->rh.send = 1; + uhci->rh.interval = urb->interval; + rh_init_int_timer (urb); +#endif + return 0; + } + bmRType_bReq = cmd->requesttype | cmd->request << 8; + wValue = swap_16(cmd->value); + wIndex = swap_16(cmd->index); + wLength = swap_16(cmd->length); + usb_display_Req(bmRType_bReq); + for (i = 0; i < 8; i++) + rh.c_p_r[i] = 0; + USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n", + dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(unsigned short *) data = swap_16(1); + len=2; + break; + case RH_GET_STATUS | RH_INTERFACE: + *(unsigned short *) data = swap_16(0); + len=2; + break; + case RH_GET_STATUS | RH_ENDPOINT: + *(unsigned short *) data = swap_16(0); + len=2; + break; + case RH_GET_STATUS | RH_CLASS: + *(unsigned long *) data = swap_32(0); + len=4; + break; /* hub power ** */ + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + + status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1)); + cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) | + ((status & USBPORTSC_PEC) >> (3 - 1)) | + (rh.c_p_r[wIndex - 1] << (0 + 4)); + status = (status & USBPORTSC_CCS) | + ((status & USBPORTSC_PE) >> (2 - 1)) | + ((status & USBPORTSC_SUSP) >> (12 - 2)) | + ((status & USBPORTSC_PR) >> (9 - 4)) | + (1 << 8) | /* power on ** */ + ((status & USBPORTSC_LSDA) << (-8 + 9)); + + *(unsigned short *) data = swap_16(status); + *(unsigned short *) (data + 2) = swap_16(cstatus); + len=4; + break; + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): + len=0; + break; + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case (RH_C_HUB_OVER_CURRENT): + len=0; /* hub power over current ** */ + break; + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + usb_display_wValue(wValue,wIndex); + switch (wValue) { + case (RH_PORT_ENABLE): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) & ~USBPORTSC_PE; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_PORT_SUSPEND): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) & ~USBPORTSC_SUSP; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_PORT_POWER): + len=0; /* port power ** */ + break; + case (RH_C_PORT_CONNECTION): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_CSC; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_C_PORT_ENABLE): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_PEC; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_C_PORT_SUSPEND): +/*** WR_RH_PORTSTAT(RH_PS_PSSC); */ + len=0; + break; + case (RH_C_PORT_OVER_CURRENT): + len=0; + break; + case (RH_C_PORT_RESET): + rh.c_p_r[wIndex - 1] = 0; + len=0; + break; + } + break; + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + usb_display_wValue(wValue,wIndex); + switch (wValue) { + case (RH_PORT_SUSPEND): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_SUSP; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_PORT_RESET): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_PR; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + wait_ms(10); + status = (status & 0xfff5) & ~USBPORTSC_PR; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + udelay(10); + status = (status & 0xfff5) | USBPORTSC_PE; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + wait_ms(10); + status = (status & 0xfff5) | 0xa; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + case (RH_PORT_POWER): + len=0; /* port power ** */ + break; + case (RH_PORT_ENABLE): + status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); + status = (status & 0xfff5) | USBPORTSC_PE; + out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); + len=0; + break; + } + break; + + case RH_SET_ADDRESS: + rh.devnum = wValue; + len=0; + break; + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + i=sizeof(root_hub_config_des); + status=i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_dev_des, len); + break; + case (0x02): /* configuration descriptor */ + i=sizeof(root_hub_config_des); + status=i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_config_des, len); + break; + case (0x03): /*string descriptors */ + if(wValue==0x0300) { + i=sizeof(root_hub_str_index0); + status = i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_str_index0, len); + break; + } + if(wValue==0x0301) { + i=sizeof(root_hub_str_index1); + status = i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_str_index1, len); + break; + } + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + root_hub_hub_des[2] = 2; + i=sizeof(root_hub_hub_des); + status= i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy (data, root_hub_hub_des, len); + break; + case RH_GET_CONFIGURATION: + *(unsigned char *) data = 0x01; + len = 1; + break; + case RH_SET_CONFIGURATION: + len=0; + break; + default: + stat = USB_ST_STALLED; + } + USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat, + in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2)); + dev->act_len=len; + dev->status=stat; + return stat; + +} + +/******************************************************************************** + * Some Debug Routines + */ + +#ifdef USB_RH_DEBUG + +static void usb_display_Req(unsigned short req) +{ + USB_RH_PRINTF("- Root-Hub Request: "); + switch (req) { + case RH_GET_STATUS: + USB_RH_PRINTF("Get Status "); + break; + case RH_GET_STATUS | RH_INTERFACE: + USB_RH_PRINTF("Get Status Interface "); + break; + case RH_GET_STATUS | RH_ENDPOINT: + USB_RH_PRINTF("Get Status Endpoint "); + break; + case RH_GET_STATUS | RH_CLASS: + USB_RH_PRINTF("Get Status Class"); + break; /* hub power ** */ + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + USB_RH_PRINTF("Get Status Class Others"); + break; + case RH_CLEAR_FEATURE | RH_ENDPOINT: + USB_RH_PRINTF("Clear Feature Endpoint "); + break; + case RH_CLEAR_FEATURE | RH_CLASS: + USB_RH_PRINTF("Clear Feature Class "); + break; + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + USB_RH_PRINTF("Clear Feature Other Class "); + break; + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + USB_RH_PRINTF("Set Feature Other Class "); + break; + case RH_SET_ADDRESS: + USB_RH_PRINTF("Set Address "); + break; + case RH_GET_DESCRIPTOR: + USB_RH_PRINTF("Get Descriptor "); + break; + case RH_GET_DESCRIPTOR | RH_CLASS: + USB_RH_PRINTF("Get Descriptor Class "); + break; + case RH_GET_CONFIGURATION: + USB_RH_PRINTF("Get Configuration "); + break; + case RH_SET_CONFIGURATION: + USB_RH_PRINTF("Get Configuration "); + break; + default: + USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req); + } + USB_RH_PRINTF("\n"); + +} + +static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) +{ + switch (wValue) { + case (RH_PORT_ENABLE): + USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex); + break; + case (RH_PORT_SUSPEND): + USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex); + break; + case (RH_PORT_POWER): + USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex); + break; + case (RH_C_PORT_CONNECTION): + USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex); + break; + case (RH_C_PORT_ENABLE): + USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex); + break; + case (RH_C_PORT_SUSPEND): + USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex); + break; + case (RH_C_PORT_OVER_CURRENT): + USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex); + break; + case (RH_C_PORT_RESET): + USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex); + break; + default: + USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex); + break; + } +} + +#endif + + +#ifdef USB_UHCI_DEBUG + +static int usb_display_td(uhci_td_t *td) +{ + unsigned long tmp; + int valid; + + printf("TD at %p:\n",td); + + tmp=swap_32(td->link); + printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0, + ((tmp & 0x4)==0x4) ? "Depth" : "Breath", + ((tmp & 0x2)==0x2) ? "QH" : "TD", + ((tmp & 0x1)==0x1) ? "invalid" : "valid"); + valid=((tmp & 0x1)==0x0); + tmp=swap_32(td->status); + printf(" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n", + (((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable", + ((tmp>>28)&0x3), + (((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed", + (((tmp>>25)&0x1)==0x1) ? "ISO " : "", + (((tmp>>24)&0x1)==0x1) ? "IOC " : "", + (((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ", + (((tmp>>22)&0x1)==0x1) ? "Stalled" : "", + (((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "", + (((tmp>>20)&0x1)==0x1) ? "Babble" : "", + (((tmp>>19)&0x1)==0x1) ? "NAK" : "", + (((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "", + (tmp&0x7ff)); + tmp=swap_32(td->info); + printf(" MaxLen 0x%lX\n",((tmp>>21)&0x7FF)); + printf(" %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "", + ((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF); + tmp=swap_32(td->buffer); + printf(" Buffer 0x%08lX\n",tmp); + printf(" DEV %08lX\n",td->dev_ptr); + return valid; +} + + +void usb_show_td(int max) +{ + int i; + if(max>0) { + for(i=0;i: */ +#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ +#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ +#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ +#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ +#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ +#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ +#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ +#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ +#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ +#define TD_CTRL_NAK (1 << 19) /* NAK Received */ +#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ +#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ +#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ + +#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ + TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) + +#define TD_TOKEN_TOGGLE 19 + +/* ------------------------------------------------------------------------------------ + Virtual Root HUB + ------------------------------------------------------------------------------------ */ +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +/* Our Vendor Specific feature */ +#define RH_REMOVE_EP 0x00 + + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* Transfer descriptor structure */ +typedef struct { + unsigned long link; /* next td/qh (LE)*/ + unsigned long status; /* status of the td */ + unsigned long info; /* Max Lenght / Endpoint / device address and PID */ + unsigned long buffer; /* pointer to data buffer (LE) */ + unsigned long dev_ptr; /* pointer to the assigned device (BE) */ + unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */ +} uhci_td_t, *puhci_td_t; + +/* Queue Header structure */ +typedef struct { + unsigned long head; /* Next QH (LE)*/ + unsigned long element; /* Queue element pointer (LE) */ + unsigned long res[5]; /* reserved */ + unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */ +} uhci_qh_t, *puhci_qh_t; + +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + int numports; /* number of ports */ + int c_p_r[8]; /* C_PORT_RESET */ +}; + + +#endif /* _USB_UHCI_H_ */ diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile new file mode 100644 index 0000000..9276f64 --- /dev/null +++ b/board/mpl/mip405/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \ + ../common/usb_uhci.o ../common/memtst.o ../common/common_util.o + +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c new file mode 100644 index 0000000..6fbc585 --- /dev/null +++ b/board/mpl/mip405/cmd_mip405.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * hacked for MIP405 + */ + +#include +#include +#include "mip405.h" +#include "../common/common_util.h" + + +extern void print_mip405_info(void); +extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + + +/* ------------------------------------------------------------------------- */ + +int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + ulong led_on; + + if (strcmp(argv[1], "info") == 0) + { + print_mip405_info(); + return 0; + } + if (strcmp(argv[1], "led") == 0) + { + led_on = (ulong)simple_strtoul(argv[2], NULL, 10); + user_led0(led_on); + return 0; + } + return (do_mplcommon(cmdtp, flag, argc, argv)); +} +U_BOOT_CMD( + mip405, 8, 1, do_mip405, + "mip405 - MIP405 specific Cmds\n", + "flash mem [SrcAddr] - updates U-Boot with image in memory\n" + "mip405 flash mps - updates U-Boot with image from MPS\n" + "mip405 info - displays board information\n" + "mip405 led - switches LED on (on=1) or off (on=0)\n" + "mip405 mem [cnt] - Memory Test -times, = -1 loop forever\n" +); + +/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/mip405/config.mk b/board/mpl/mip405/config.mk new file mode 100644 index 0000000..0f8d153 --- /dev/null +++ b/board/mpl/mip405/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFF80000 diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S new file mode 100644 index 0000000..3351b5b --- /dev/null +++ b/board/mpl/mip405/init.S @@ -0,0 +1,233 @@ +/*------------------------------------------------------------------------------+ + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *-------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- + * Function: ext_bus_cntlr_init + * Description: Initializes the External Bus Controller for the external + * peripherals. IMPORTANT: For pass1 this code must run from + * cache since you can not reliably change a peripheral banks + * timing register (pbxap) while running code from that bank. + * For ex., since we are running from ROM on bank 0, we can NOT + * execute the code that modifies bank 0 timings from ROM, so + * we run it from cache. + * Bank 0 - Flash or Multi Purpose Socket + * Bank 1 - Multi Purpose Socket or Flash (set in C-Code) + * Bank 2 - UART 1 (set in C-Code) + * Bank 3 - UART 2 (set in C-Code) + * Bank 4 - not used + * Bank 5 - not used + * Bank 6 - not used + * Bank 7 - PLD Register + *-----------------------------------------------------------------------------*/ +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include +#include + +#include +#include +#include "mip405.h" + + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + mflr r4 /* save link register */ + mfdcr r3,strap /* get strapping reg */ + andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ + bnelr /* jump back if PCI boot */ + + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 14; used to prefetch */ + mtctr r4 /* 14 cache lines to fit this function */ + /* in cache (gives us 8x14=112 instrctns) */ +..ebcloop: + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 14 cache lines */ + + /*------------------------------------------------------------------- + * Delay to ensure all accesses to ROM are complete before changing + * bank 0 timings. + *------------------------------------------------------------------- */ + addis r3,0,0x0 + ori r3,r3,0xA000 + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + /*----------------------------------------------------------------------- + * decide boot up mode + *----------------------------------------------------------------------- */ + addi r4,0,pb0cr + mtdcr ebccfga,r4 + mfdcr r4,ebccfgd + + andi. r0, r4, 0x2000 /* mask out irrelevant bits */ + beq 0f /* jump if 8 bit bus width */ + + /* setup 16 bit things + *----------------------------------------------------------------------- + * Memory Bank 0 (16 Bit Flash) initialization + *---------------------------------------------------------------------- */ + + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,(FLASH_AP_B)@h + ori r4,r4,(FLASH_AP_B)@l + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + /* BS=0x010(4MB),BU=0x3(R/W), */ + addis r4,0,(FLASH_CR_B)@h + ori r4,r4,(FLASH_CR_B)@l + mtdcr ebccfgd,r4 + b 1f + +0: + + /* 8Bit boot mode: */ + /*----------------------------------------------------------------------- + * Memory Bank 0 Multi Purpose Socket initialization + *----------------------------------------------------------------------- */ + /* 0x7F8FFE80 slowest boot */ + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,(MPS_AP_B)@h + ori r4,r4,(MPS_AP_B)@l + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + /* BS=0x010(4MB),BU=0x3(R/W), */ + addis r4,0,(MPS_CR_B)@h + ori r4,r4,(MPS_CR_B)@l + + mtdcr ebccfgd,r4 + + +1: + /*----------------------------------------------------------------------- + * Memory Bank 2-3-4-5-6 (not used) initialization + *-----------------------------------------------------------------------*/ + addi r4,0,pb1cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb2cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb3cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb4cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb5cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb6cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb7cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + nop /* pass2 DCR errata #8 */ + blr + +/*----------------------------------------------------------------------------- + * Function: sdram_init + * Description: Configures the internal SRAM memory. and setup the + * Stackpointer in it. + *----------------------------------------------------------------------------- */ + .globl sdram_init + +sdram_init: + + + blr + + +#if defined(CONFIG_BOOT_PCI) + .section .bootpg,"ax" + .globl _start_pci +/******************************************* + */ + +_start_pci: + /* first handle errata #68 / PCI_18 */ + iccci r0, r0 /* invalidate I-cache */ + lis r31, 0 + mticcr r31 /* ICCR = 0 (all uncachable) */ + isync + + mfccr0 r28 /* set CCR0[24] = 1 */ + ori r28, r28, 0x0080 + mtccr0 r28 + + /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ + lis r28, 0xEF40 + addi r28, r28, 0x0004 + stw r31, 0x0C(r28) /* clear PMM0PCIHA */ + lis r29, 0xFFF8 /* open 512 kByte */ + addi r29, r29, 0x0001/* and enable this region */ + stwbrx r29, r0, r28 /* write PMM0MA */ + + lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ + addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ + + lis r31, 0x8000 /* set en bit bus 0 */ + ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ + stwbrx r31, r0, r28 /* write it */ + + lwbrx r31, r0, r29 /* load XBCS register */ + oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ + stwbrx r31, r0, r29 /* write back XBCS register */ + + nop + nop + b _start /* normal start */ +#endif diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c new file mode 100644 index 0000000..9c469b0 --- /dev/null +++ b/board/mpl/mip405/mip405.c @@ -0,0 +1,820 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * TODO: clean-up + */ + +/* + * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM? + * + * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being + * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum + * parameters from the datasheet are: + * Tclk = 7.5ns (CL = 2) + * Trp = 15ns + * Trc = 60ns + * Trcd = 15ns + * Trfc = 66ns + * + * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock + * period is 10ns and the parameters needed for the Timing Register are: + * CASL = CL = 2 clock cycles + * PTA = Trp = 15ns / 10ns = 2 clock cycles + * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles + * LDF = 2 clock cycles (but can be extended to meet board-level timing) + * RFTA = Trfc = 66ns / 10ns= 7 clock cycles + * RCD = Trcd = 15ns / 10ns= 2 clock cycles + * + * The actual bit settings in the register would be: + * + * CASL = 0b01 + * PTA = 0b01 + * CTP = 0b10 + * LDF = 0b01 + * RFTA = 0b011 + * RCD = 0b01 + * + * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc + * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay + * defined as Trc rather than Trfc. + * When using DIMM modules, most but not all of the required timing parameters can be read + * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc + * are not available from the EEPROM + */ + +#include +#include "mip405.h" +#include +#include <405gp_i2c.h> +#include +#include "../common/common_util.h" +#include +#include +extern block_dev_desc_t * scsi_get_dev(int dev); +extern block_dev_desc_t * ide_get_dev(int dev); + +#undef SDRAM_DEBUG +#define ENABLE_ECC /* for ecc boards */ +#define FALSE 0 +#define TRUE 1 + +/* stdlib.h causes some compatibility problems; should fixe these! -- wd */ +#ifndef __ldiv_t_defined +typedef struct { + long int quot; /* Quotient */ + long int rem; /* Remainder */ +} ldiv_t; +extern ldiv_t ldiv (long int __numer, long int __denom); +# define __ldiv_t_defined 1 +#endif + + +#define PLD_PART_REG PER_PLD_ADDR + 0 +#define PLD_VERS_REG PER_PLD_ADDR + 1 +#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 +#define PLD_IRQ_REG PER_PLD_ADDR + 3 +#define PLD_COM_MODE_REG PER_PLD_ADDR + 4 +#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 + +#define MEGA_BYTE (1024*1024) + +typedef struct { + unsigned char boardtype; /* Board revision and Population Options */ + unsigned char cal; /* cas Latency (will be programmend as cal-1) */ + unsigned char trp; /* datain27 in clocks */ + unsigned char trcd; /* datain29 in clocks */ + unsigned char tras; /* datain30 in clocks */ + unsigned char tctp; /* tras - trcd in clocks */ + unsigned char am; /* Address Mod (will be programmed as am-1) */ + unsigned char sz; /* log binary => Size = (4MByte<baudrate = 9600; + serial_init (); +#endif + serial_puts ("\n"); + serial_puts (s); + serial_puts ("\n enable SDRAM_DEBUG for more info\n"); + for (;;); +} + + +unsigned char get_board_revcfg (void) +{ + out8 (PER_BOARD_ADDR, 0); + return (in8 (PER_BOARD_ADDR)); +} + + +#ifdef SDRAM_DEBUG + +void write_hex (unsigned char i) +{ + char cc; + + cc = i >> 4; + cc &= 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); + cc = i & 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); +} + +void write_4hex (unsigned long val) +{ + write_hex ((unsigned char) (val >> 24)); + write_hex ((unsigned char) (val >> 16)); + write_hex ((unsigned char) (val >> 8)); + write_hex ((unsigned char) val); +} + +#endif + + +int init_sdram (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long tmp, baseaddr; + unsigned short i; + unsigned char trp_clocks, + trcd_clocks, + tras_clocks, + trc_clocks, + tctp_clocks; + unsigned char cal_val; + unsigned char bc; + unsigned long sdram_tim, sdram_bank; + + /*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/ + (void) get_clocks (); + gd->baudrate = 9600; + serial_init (); + /* set up the pld */ + mtdcr (ebccfga, pb7ap); + mtdcr (ebccfgd, PLD_AP); + mtdcr (ebccfga, pb7cr); + mtdcr (ebccfgd, PLD_CR); + /* THIS IS OBSOLETE */ + /* set up the board rev reg*/ + mtdcr (ebccfga, pb5ap); + mtdcr (ebccfgd, BOARD_AP); + mtdcr (ebccfga, pb5cr); + mtdcr (ebccfgd, BOARD_CR); +#ifdef SDRAM_DEBUG + /* get all informations from PLD */ + serial_puts ("\nPLD Part 0x"); + bc = in8 (PLD_PART_REG); + write_hex (bc); + serial_puts ("\nPLD Vers 0x"); + bc = in8 (PLD_VERS_REG); + write_hex (bc); + serial_puts ("\nBoard Rev 0x"); + bc = in8 (PLD_BOARD_CFG_REG); + write_hex (bc); + serial_puts ("\n"); +#endif + /* check board */ + bc = in8 (PLD_PART_REG); +#if defined(CONFIG_MIP405T) + if((bc & 0x80)==0) + SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n"); +#else + if((bc & 0x80)==0x80) + SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); +#endif + /* set-up the chipselect machine */ + mtdcr (ebccfga, pb0cr); /* get cs0 config reg */ + tmp = mfdcr (ebccfgd); + if ((tmp & 0x00002000) == 0) { + /* MPS Boot, set up the flash */ + mtdcr (ebccfga, pb1ap); + mtdcr (ebccfgd, FLASH_AP); + mtdcr (ebccfga, pb1cr); + mtdcr (ebccfgd, FLASH_CR); + } else { + /* Flash boot, set up the MPS */ + mtdcr (ebccfga, pb1ap); + mtdcr (ebccfgd, MPS_AP); + mtdcr (ebccfga, pb1cr); + mtdcr (ebccfgd, MPS_CR); + } + /* set up UART0 (CS2) and UART1 (CS3) */ + mtdcr (ebccfga, pb2ap); + mtdcr (ebccfgd, UART0_AP); + mtdcr (ebccfga, pb2cr); + mtdcr (ebccfgd, UART0_CR); + mtdcr (ebccfga, pb3ap); + mtdcr (ebccfgd, UART1_AP); + mtdcr (ebccfga, pb3cr); + mtdcr (ebccfgd, UART1_CR); + bc = in8 (PLD_BOARD_CFG_REG); +#ifdef SDRAM_DEBUG + serial_puts ("\nstart SDRAM Setup\n"); + serial_puts ("\nBoard Rev: "); + write_hex (bc); + serial_puts ("\n"); +#endif + i = 0; + baseaddr = CFG_SDRAM_BASE; + while (sdram_table[i].sz != 0xff) { + if (sdram_table[i].boardtype == bc) + break; + i++; + } + if (sdram_table[i].boardtype != bc) + SDRAM_err ("No SDRAM table found for this board!!!\n"); +#ifdef SDRAM_DEBUG + serial_puts (" found table "); + write_hex (i); + serial_puts (" \n"); +#endif + /* since the ECC initialisation needs some time, + * we show that we're alive + */ + if (sdram_table[i].ecc) + serial_puts ("\nInitializing SDRAM, Please stand by"); + cal_val = sdram_table[i].cal - 1; /* Cas Latency */ + trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */ + trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ + tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ + /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ + tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */ + /* trc_clocks is sum of trp_clocks + tras_clocks */ + trc_clocks = trp_clocks + tras_clocks; + /* get SDRAM timing register */ + mtdcr (memcfga, mem_sdtr1); + sdram_tim = mfdcr (memcfgd) & ~0x018FC01F; + /* insert CASL value */ + sdram_tim |= ((unsigned long) (cal_val)) << 23; + /* insert PTA value */ + sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18; + /* insert CTP value */ + sdram_tim |= + ((unsigned long) (trc_clocks - trp_clocks - + trcd_clocks)) << 16; + /* insert LDF (always 01) */ + sdram_tim |= ((unsigned long) 0x01) << 14; + /* insert RFTA value */ + sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2; + /* insert RCD value */ + sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0; + + tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */ + /* insert SZ value; */ + tmp |= ((unsigned long) sdram_table[i].sz << 17); + /* get SDRAM bank 0 register */ + mtdcr (memcfga, mem_mb0cf); + sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001; + sdram_bank |= (baseaddr | tmp | 0x01); + +#ifdef SDRAM_DEBUG + serial_puts ("sdtr: "); + write_4hex (sdram_tim); + serial_puts ("\n"); +#endif + + /* write SDRAM timing register */ + mtdcr (memcfga, mem_sdtr1); + mtdcr (memcfgd, sdram_tim); + +#ifdef SDRAM_DEBUG + serial_puts ("mb0cf: "); + write_4hex (sdram_bank); + serial_puts ("\n"); +#endif + + /* write SDRAM bank 0 register */ + mtdcr (memcfga, mem_mb0cf); + mtdcr (memcfgd, sdram_bank); + + if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ + /* get SDRAM refresh interval register */ + mtdcr (memcfga, mem_rtr); + tmp = mfdcr (memcfgd) & ~0x3FF80000; + tmp |= 0x07F00000; + } else { + /* get SDRAM refresh interval register */ + mtdcr (memcfga, mem_rtr); + tmp = mfdcr (memcfgd) & ~0x3FF80000; + tmp |= 0x05F00000; + } + /* write SDRAM refresh interval register */ + mtdcr (memcfga, mem_rtr); + mtdcr (memcfgd, tmp); + /* enable ECC if used */ +#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) + if (sdram_table[i].ecc) { + /* disable checking for all banks */ + unsigned long *p; +#ifdef SDRAM_DEBUG + serial_puts ("disable ECC.. "); +#endif + mtdcr (memcfga, mem_ecccf); + tmp = mfdcr (memcfgd); + tmp &= 0xff0fffff; /* disable all banks */ + mtdcr (memcfga, mem_ecccf); + /* set up SDRAM Controller with ECC enabled */ +#ifdef SDRAM_DEBUG + serial_puts ("setup SDRAM Controller.. "); +#endif + mtdcr (memcfgd, tmp); + mtdcr (memcfga, mem_mcopt1); + tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, tmp); + udelay (600); +#ifdef SDRAM_DEBUG + serial_puts ("fill the memory..\n"); +#endif + serial_puts ("."); + /* now, fill all the memory */ + tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz); + p = (unsigned long) 0; + while ((unsigned long) p < tmp) { + *p++ = 0L; + if (!((unsigned long) p % 0x00800000)) /* every 8MByte */ + serial_puts ("."); + } + /* enable bank 0 */ + serial_puts ("."); +#ifdef SDRAM_DEBUG + serial_puts ("enable ECC\n"); +#endif + udelay (400); + mtdcr (memcfga, mem_ecccf); + tmp = mfdcr (memcfgd); + tmp |= 0x00800000; /* enable bank 0 */ + mtdcr (memcfgd, tmp); + udelay (400); + } else +#endif + { + /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ + mtdcr (memcfga, mem_mcopt1); + tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000; + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, tmp); + udelay (400); + } + serial_puts ("\n"); + return (0); +} + +int board_early_init_f (void) +{ + init_sdram (); + + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the PIP405 board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive + | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive + | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive + | Note for MIP405 board: + | An interrupt taken for the SouthBridge (IRQ 25) indicates that + | the Interrupt Controller in the South Bridge has caused the + | interrupt. The IC must be read to determine which device + | caused the interrupt. + | + +-------------------------------------------------------------------------*/ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ + mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + return 0; +} + + +/* + * Get some PLD Registers + */ + +unsigned short get_pld_parvers (void) +{ + unsigned short result; + unsigned char rc; + + rc = in8 (PLD_PART_REG); + result = (unsigned short) rc << 8; + rc = in8 (PLD_VERS_REG); + result |= rc; + return result; +} + + +void user_led0 (unsigned char on) +{ + if (on) + out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4)); + else + out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb)); +} + + +void ide_set_reset (int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + if (idereset) + out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1)); + else { + udelay (10000); + out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe)); + } +} + + +/* ------------------------------------------------------------------------- */ + +void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var) +{ +#if !defined(CONFIG_MIP405T) + unsigned char bc,rc,tmp; + int i; + + bc = in8 (PLD_BOARD_CFG_REG); + tmp = ~bc; + tmp &= 0xf; + rc = 0; + for (i = 0; i < 4; i++) { + rc <<= 1; + rc += (tmp & 0x1); + tmp >>= 1; + } + rc++; + if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */ + || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */ + && (rc==0x1)) /* Population Option 1 is a -3 */ + rc=3; + *pcbrev=(bc >> 4) & 0xf; + *var=rc; +#else + unsigned char bc; + bc = in8 (PLD_BOARD_CFG_REG); + *pcbrev=(bc >> 4) & 0xf; + *var=16-(bc & 0xf); +#endif +} + +/* + * Check Board Identity: + */ +/* serial String: "MIP405_1000" OR "MIP405T_1000" */ +#if !defined(CONFIG_MIP405T) +#define BOARD_NAME "MIP405" +#else +#define BOARD_NAME "MIP405T" +#endif + +int checkboard (void) +{ + char s[50]; + unsigned char bc, var; + int i; + backup_t *b = (backup_t *) s; + + puts ("Board: "); + get_pcbrev_var(&bc,&var); + i = getenv_r ("serial#", (char *)s, 32); + if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) { + get_backup_values (b); + if (strncmp (b->signature, "MPL\0", 4) != 0) { + puts ("### No HW ID - assuming " BOARD_NAME); + printf ("-%d Rev %c", var, 'A' + bc); + } else { + b->serial_name[sizeof(BOARD_NAME)-1] = 0; + printf ("%s-%d Rev %c SN: %s", b->serial_name, var, + 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]); + } + } else { + s[sizeof(BOARD_NAME)-1] = 0; + printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc, + &s[sizeof(BOARD_NAME)]); + } + bc = in8 (PLD_EXT_CONF_REG); + printf (" Boot Config: 0x%x\n", bc); + return (0); +} + + +/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- */ +/* + initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of + the necessary info for SDRAM controller configuration +*/ +/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- */ +static int test_dram (unsigned long ramsize); + +long int initdram (int board_type) +{ + + unsigned long bank_reg[4], tmp, bank_size; + int i, ds; + unsigned long TotalSize; + + ds = 0; + /* since the DRAM controller is allready set up, calculate the size with the + bank registers */ + mtdcr (memcfga, mem_mb0cf); + bank_reg[0] = mfdcr (memcfgd); + mtdcr (memcfga, mem_mb1cf); + bank_reg[1] = mfdcr (memcfgd); + mtdcr (memcfga, mem_mb2cf); + bank_reg[2] = mfdcr (memcfgd); + mtdcr (memcfga, mem_mb3cf); + bank_reg[3] = mfdcr (memcfgd); + TotalSize = 0; + for (i = 0; i < 4; i++) { + if ((bank_reg[i] & 0x1) == 0x1) { + tmp = (bank_reg[i] >> 17) & 0x7; + bank_size = 4 << tmp; + TotalSize += bank_size; + } else + ds = 1; + } + mtdcr (memcfga, mem_ecccf); + tmp = mfdcr (memcfgd); + + if (!tmp) + printf ("No "); + printf ("ECC "); + + test_dram (TotalSize * MEGA_BYTE); + return (TotalSize * MEGA_BYTE); +} + +/* ------------------------------------------------------------------------- */ + + +static int test_dram (unsigned long ramsize) +{ +#ifdef SDRAM_DEBUG + mem_test (0L, ramsize, 1); +#endif + /* not yet implemented */ + return (1); +} + +/* used to check if the time in RTC is valid */ +static unsigned long start; +static struct rtc_time tm; +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* adjust flash start and size as well as the offset */ + gd->bd->bi_flashstart=0-flash_info[0].size; + gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; + gd->bd->bi_flashoffset=0; + + /* check, if RTC is running */ + rtc_get (&tm); + start=get_timer(0); + /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ + if (mfdcr(strap) & PSR_ROM_LOC) + mtspr(ccr0, (mfspr(ccr0) & ~0x80)); + + return (0); +} + + +void print_mip405_rev (void) +{ + unsigned char part, vers, pcbrev, var; + + get_pcbrev_var(&pcbrev,&var); + part = in8 (PLD_PART_REG); + vers = in8 (PLD_VERS_REG); + printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n", + var, pcbrev + 'A', part & 0x7F, vers); +} + + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif + +extern void mem_test_reloc(void); +extern int mk_date (char *, struct rtc_time *); + +int last_stage_init (void) +{ + unsigned long stop; + struct rtc_time newtm; + char *s; + mem_test_reloc(); + /* write correct LED configuration */ + if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) { + printf ("Error writing to the PHY\n"); + } + /* since LED/CFG2 is not connected on the -2, + * write to correct capability information */ + if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) { + printf ("Error writing to the PHY\n"); + } + print_mip405_rev (); + show_stdio_dev (); + check_env (); + /* check if RTC time is valid */ + stop=get_timer(start); + while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */ + udelay(1000); + stop=get_timer(start); + } + rtc_get (&newtm); + if(tm.tm_sec==newtm.tm_sec) { + s=getenv("defaultdate"); + if(!s) + mk_date ("010112001970", &newtm); + else + if(mk_date (s, &newtm)!=0) { + printf("RTC: Bad date format in defaultdate\n"); + return 0; + } + rtc_reset (); + rtc_set(&newtm); + } + return 0; +} + +/*************************************************************************** + * some helping routines + */ + +int overwrite_console (void) +{ + return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */ +} + + +/************************************************************************ +* Print MIP405 Info +************************************************************************/ +void print_mip405_info (void) +{ + unsigned char part, vers, cfg, irq_reg, com_mode, ext; + + part = in8 (PLD_PART_REG); + vers = in8 (PLD_VERS_REG); + cfg = in8 (PLD_BOARD_CFG_REG); + irq_reg = in8 (PLD_IRQ_REG); + com_mode = in8 (PLD_COM_MODE_REG); + ext = in8 (PLD_EXT_CONF_REG); + + printf ("PLD Part %d version %d\n", part & 0x7F, vers); + printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A'); + printf ("Population Options %d %d %d %d\n", (cfg) & 0x1, + (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1); + printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off"); + printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3); +#if !defined(CONFIG_MIP405T) + printf ("User Config Switch %d %d %d %d %d %d %d %d\n", + (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, + (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, + (ext >> 6) & 0x1, (ext >> 7) & 0x1); + printf ("SER1 uses handshakes %s\n", + (ext & 0x80) ? "DTR/DSR" : "RTS/CTS"); +#else + printf ("User Config Switch %d %d %d %d %d %d %d %d\n", + (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, + (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, + (ext >> 6) & 0x1,(ext >> 7) & 0x1); +#endif + printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted"); + printf ("IRQs:\n"); + printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active"); +#if !defined(CONFIG_MIP405T) + printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active"); + printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active"); +#endif + printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active"); + printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active"); + printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active"); +} diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h new file mode 100644 index 0000000..b1d91de --- /dev/null +++ b/board/mpl/mip405/mip405.h @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + /**************************************************************************** + * Global routines used for MIP405 + *****************************************************************************/ +#ifndef __ASSEMBLY__ +/*int switch_cs(unsigned char boot);*/ + +extern int mem_test(unsigned long start, unsigned long ramsize,int mode); + +void user_led0(unsigned char on); + + +#endif +/* timings */ +/* PLD (CS7) */ +#define PLD_BME 0 /* Burst disable */ +#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */ +#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define PLD_OEN 1 /* Cycles from CS low to OE low */ +#define PLD_WBN 1 /* Cycles from CS low to WE low */ +#define PLD_WBF 1 /* Cycles from WE high to CS high */ +#define PLD_TH 2 /* Number of hold cycles after transfer */ +#define PLD_RE 0 /* Ready disabled */ +#define PLD_SOR 1 /* Sample on Ready disabled */ +#define PLD_BEM 0 /* Byte Write only active on Write cycles */ +#define PLD_PEN 0 /* Parity disable */ +#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \ + (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define PLD_BS 0 /* 1 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define PLD_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define PLD_BW 0 /* 16Bit */ +#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13)) + + +/* timings */ + +#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024)) +/* Dummy CS to get the board revision */ +#define BOARD_BME 0 /* Burst disable */ +#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ +#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define BOARD_OEN 1 /* Cycles from CS low to OE low */ +#define BOARD_WBN 1 /* Cycles from CS low to WE low */ +#define BOARD_WBF 1 /* Cycles from WE high to CS high */ +#define BOARD_TH 2 /* Number of hold cycles after transfer */ +#define BOARD_RE 0 /* Ready disabled */ +#define BOARD_SOR 1 /* Sample on Ready disabled */ +#define BOARD_BEM 0 /* Byte Write only active on Write cycles */ +#define BOARD_PEN 0 /* Parity disable */ +#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \ + (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define BOARD_BS 0 /* 1 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define BOARD_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define BOARD_BW 0 /* 16Bit */ +#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13)) + + +/* UART0 CS2 */ +#define UART0_BME 0 /* Burst disable */ +#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */ +#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define UART0_OEN 1 /* Cycles from CS low to OE low */ +#define UART0_WBN 1 /* Cycles from CS low to WE low */ +#define UART0_WBF 1 /* Cycles from WE high to CS high */ +#define UART0_TH 2 /* Number of hold cycles after transfer */ +#define UART0_RE 0 /* Ready disabled */ +#define UART0_SOR 1 /* Sample on Ready disabled */ +#define UART0_BEM 0 /* Byte Write only active on Write cycles */ +#define UART0_PEN 0 /* Parity disable */ +#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \ + (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define UART0_BS 0 /* 1 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define UART0_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define UART0_BW 0 /* 8Bit */ +#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) + +/* UART1 CS3 */ +#define UART1_AP UART0_AP /* same timing as UART0 */ +#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) + + +/* Flash CS0 or CS 1 */ +/* 0x7F8FFE80 slowest timing at all... */ +#define FLASH_BME_B 1 /* Burst enable */ +#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ +#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ +#define FLASH_BME 0 /* Burst disable */ +#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ +#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define FLASH_OEN 1 /* Cycles from CS low to OE low */ +#define FLASH_WBN 1 /* Cycles from CS low to WE low */ +#define FLASH_WBF 1 /* Cycles from WE high to CS high */ +#define FLASH_TH 2 /* Number of hold cycles after transfer */ +#define FLASH_RE 0 /* Ready disabled */ +#define FLASH_SOR 1 /* Sample on Ready disabled */ +#define FLASH_BEM 0 /* Byte Write only active on Write cycles */ +#define FLASH_PEN 0 /* Parity disable */ +/* Access Parameter Register for non Boot */ +#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ + (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) +/* Access Parameter Register for Boot */ +#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ + (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define FLASH_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define FLASH_BW 1 /* 16Bit */ +/* CR register for Boot */ +#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) +/* CR register for non Boot */ +#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) + +/* MPS CS1 or CS0 */ +/* Boot CS: */ +#define MPS_BME_B 1 /* Burst enable */ +#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ +#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ +#define MPS_BME 0 /* Burst disable */ +#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ +#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define MPS_OEN 1 /* Cycles from CS low to OE low */ +#define MPS_WBN 1 /* Cycles from CS low to WE low */ +#define MPS_WBF 1 /* Cycles from WE high to CS high */ +#define MPS_TH 2 /* Number of hold cycles after transfer */ +#define MPS_RE 0 /* Ready disabled */ +#define MPS_SOR 1 /* Sample on Ready disabled */ +#define MPS_BEM 0 /* Byte Write only active on Write cycles */ +#define MPS_PEN 0 /* Parity disable */ +/* Access Parameter Register for non Boot */ +#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ + (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) +/* Access Parameter Register for Boot */ +#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ + (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define MPS_BS 2 /* 4 MByte */ +#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define MPS_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define MPS_BW 0 /* 8Bit */ +/* CR register for Boot */ +#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13)) +/* CR register for non Boot */ +#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds new file mode 100644 index 0000000..ad5f273 --- /dev/null +++ b/board/mpl/mip405/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + .bootpg 0xFFFFF000 : + { + board/mpl/mip405/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/mpl/mip405/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile new file mode 100644 index 0000000..1a9ce12 --- /dev/null +++ b/board/mpl/pati/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o +#### cmd_pati.o +SOBJS := + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c new file mode 100644 index 0000000..98429c0 --- /dev/null +++ b/board/mpl/pati/cmd_pati.c @@ -0,0 +1,449 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Adapted for PATI + */ + +#include +#include +#define PLX9056_LOC +#include "plx9056.h" +#include "pati.h" +#include "pci_eeprom.h" + +extern void show_pld_regs(void); +extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +extern void user_led0(int led_on); +extern void user_led1(int led_on); + +/* ------------------------------------------------------------------------- */ +#if defined(CFG_PCI_CON_DEVICE) +extern void pci_con_disc(void); +extern void pci_con_connect(void); +#endif + +/****************************************************************************** + * Eeprom Support + ******************************************************************************/ +unsigned long get32(unsigned long addr) +{ + unsigned long *p=(unsigned long *)addr; + return *p; +} + +void set32(unsigned long addr,unsigned long data) +{ + unsigned long *p=(unsigned long *)addr; + *p=data; +} + +#define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE)) +#define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y))) + + +/****************************************************************************** + * reload_pci_eeprom + ******************************************************************************/ + +static void reload_pci_eeprom(void) +{ + unsigned long reg; + /* Set Bit 29 and clear it again */ + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + udelay(1); + /* set it*/ + reg|=(1<<29); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + /* EECLK @ 33MHz = 125kHz + * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec + * use 20msec + */ + udelay(20000); /* wait 20ms */ + reg &= ~(1<<29); /* set it low */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + udelay(1); /* wait some time */ +} + +/****************************************************************************** + * clock_pci_eeprom + ******************************************************************************/ + +static void clock_pci_eeprom(void) +{ + unsigned long reg; + /* clock is low, data is valid */ + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + udelay(1); + /* set clck high */ + reg|=(1<<24); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + udelay(1); /* wait some time */ + reg &= ~(1<<24); /* set clock low */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + udelay(1); /* wait some time */ +} + +/****************************************************************************** + * send_pci_eeprom_cmd + ******************************************************************************/ +static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len) +{ + unsigned long reg; + int i; + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + /* Clear all EEPROM bits */ + reg &= ~(0xF << 24); + /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + udelay(1); /* wait some time */ + /* Enable EEPROM Chip Select */ + reg |= (1 << 25); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + /* Send EEPROM command - one bit at a time */ + for (i = (int)(len-1); i >= 0; i--) { + /* Check if current bit is 0 or 1 */ + if (cmd & (1 << i)) + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); + else + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); + clock_pci_eeprom(); + } +} + +/****************************************************************************** + * write_pci_eeprom_offs + ******************************************************************************/ +static void write_pci_eeprom_offs(unsigned short offset, unsigned short value) +{ + unsigned long reg; + int bitpos, cmdshft, cmdlen, timeout; + /* we're using the Eeprom 93CS66 */ + cmdshft = 2; + cmdlen = EE66_CMD_LEN; + /* Send Write_Enable command to EEPROM */ + send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen); + /* Send EEPROM Write command and offset to EEPROM */ + send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen); + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + /* Clear all EEPROM bits */ + reg &= ~(0xF << 24); + /* Make sure EEDO Input is disabled for some PLX chips */ + reg &= ~(1 << 31); + /* Enable EEPROM Chip Select */ + reg |= (1 << 25); + /* Write 16-bit value to EEPROM - one bit at a time */ + for (bitpos = 15; bitpos >= 0; bitpos--) { + /* Get bit value and shift into result */ + if (value & (1 << bitpos)) + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); + else + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg ); + clock_pci_eeprom(); + } /* for */ + /* Deselect Chip */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25)); + /* Re-select Chip */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25)); + /* A small delay is needed to let EEPROM complete */ + timeout = 0; + do { + udelay(10); + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + timeout++; + } while (((reg & (1 << 27)) == 0) && timeout < 20000); + /* Send Write_Disable command to EEPROM */ + send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen); + /* Clear Chip Select and all other EEPROM bits */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); +} + + +/****************************************************************************** + * read_pci_eeprom_offs + ******************************************************************************/ +static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue) +{ + unsigned long reg; + int bitpos, cmdshft, cmdlen; + /* we're using the Eeprom 93CS66 */ + cmdshft = 2; + cmdlen = EE66_CMD_LEN; + /* Send EEPROM read command and offset to EEPROM */ + send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen); + /* Set EEPROM write output bit */ + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + /* Set EEDO Input enable */ + reg |= (1 << 31); + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26)); + /* Get 16-bit value from EEPROM - one bit at a time */ + for (bitpos = 0; bitpos < 16; bitpos++) { + clock_pci_eeprom(); + udelay(10); + reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); + /* Get bit value and shift into result */ + if (reg & (1 << 27)) + *pvalue = (unsigned short)((*pvalue << 1) | 1); + else + *pvalue = (unsigned short)(*pvalue << 1); + } + /* Clear EEDO Input enable */ + reg &= ~(1 << 31); + /* Clear Chip Select and all other EEPROM bits */ + PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); +} + + +/****************************************************************************** + * EEPROM read/writes +******************************************************************************/ + +#undef EEPROM_DBG +static int pati_pci_eeprom_erase(void) +{ + int i; + printf("Erasing EEPROM "); + for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) { + write_pci_eeprom_offs(i,0xffff); + if((i%0x10)) + printf("."); + } + printf("\nDone\n"); + return 0; +} + +static int pati_pci_eeprom_prg(void) +{ + int i; + i=0; + printf("Programming EEPROM "); + while(pati_eeprom[i].offset<0xffff) { + write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value); + #ifdef EEPROM_DBG + printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value); + #else + if((i%0x10)) + printf("."); + #endif + i++; + } + printf("\nDone\n"); + return 0; +} + +static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size) +{ + int i; + unsigned short value; + unsigned short *buffer =(unsigned short *)addr; + if((offset + size) > PATI_EEPROM_LAST_OFFSET) { + size = PATI_EEPROM_LAST_OFFSET - offset; + } + printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2); + for( i = offset; i< (offset + size); i+=2) { + value = *buffer++; + write_pci_eeprom_offs(i,value); + #ifdef EEPROM_DBG + printf("0x%04X: 0x%04X\n",i, value); + #else + if((i%0x10)) + printf("."); + #endif + } + printf("\nDone\n"); + return 0; +} + +static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size) +{ + int i; + unsigned short value; + unsigned short *buffer =(unsigned short *)addr; + if((offset + size) > PATI_EEPROM_LAST_OFFSET) { + size = PATI_EEPROM_LAST_OFFSET - offset; + } + printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2); + for( i = offset; i< (offset + size); i+=2) { + read_pci_eeprom_offs(i,&value); + *buffer++=value; + #ifdef EEPROM_DBG + printf("0x%04X: 0x%04X\n",i, value); + #else + if((i%0x10)) + printf("."); + #endif + } + printf("\nDone\n"); + return 0; +} + +/****************************************************************************** + * PCI Bridge Registers Dump +*******************************************************************************/ +static void display_pci_regs(void) +{ + printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE)); + printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP)); + printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT)); + printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC)); + printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE)); + printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP)); + printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC)); + printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE)); + printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE)); + printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE)); + printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP)); + printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG)); + printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE)); + printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP)); + printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC)); + printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC)); + printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0)); + printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1)); + printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2)); + printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3)); + printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4)); + printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5)); + printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6)); + printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7)); + printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL)); + printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL)); + printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT)); + printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT)); + printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID)); + printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID)); + printf(" \n"); + printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID)); + printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND)); + printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION)); + printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE)); + printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE)); + printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE)); + printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0)); + printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1)); + printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1)); + printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2)); + printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR)); + printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID)); + printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE)); + printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR)); + printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE)); + printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID)); + printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR)); + printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID)); + printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID)); + printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA)); +} + + +int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (strcmp(argv[1], "info") == 0) + { + show_pld_regs(); + return 0; + } + if (strcmp(argv[1], "pci") == 0) + { + display_pci_regs(); + return 0; + } + if (strcmp(argv[1], "led") == 0) + { + int led_nr,led_on; + led_nr = (int)simple_strtoul(argv[2], NULL, 10); + led_on = (int)simple_strtoul(argv[3], NULL, 10); + if(!led_nr) + user_led0(led_on); + else + user_led1(led_on); + return 0; + } +#if defined(CFG_PCI_CON_DEVICE) + if (strcmp(argv[1], "con") == 0) { + pci_con_connect(); + return 0; + } + if (strcmp(argv[1], "disc") == 0) { + pci_con_disc(); + return 0; + } +#endif + if (strcmp(argv[1], "eeprom") == 0) { + unsigned long addr; + int size, offset; + offset = 0; + size = PATI_EEPROM_LAST_OFFSET; + if(argc>2) { + if(argc>3) { + addr = simple_strtoul(argv[3], NULL, 16); + if(argc>4) + offset = (int) simple_strtoul(argv[4], NULL, 16); + if(argc>5) + size = (int) simple_strtoul(argv[5], NULL, 16); + if (strcmp(argv[2], "read") == 0) { + return (pati_pci_eeprom_read(offset, addr, size)); + } + if (strcmp(argv[2], "write") == 0) { + return (pati_pci_eeprom_write(offset, addr, size)); + } + } + if (strcmp(argv[2], "prg") == 0) { + return (pati_pci_eeprom_prg()); + } + if (strcmp(argv[2], "era") == 0) { + return (pati_pci_eeprom_erase()); + } + if (strcmp(argv[2], "reload") == 0) { + reload_pci_eeprom(); + return 0; + } + + + } + } + + return (do_mplcommon(cmdtp, flag, argc, argv)); +} + +U_BOOT_CMD( + pati, 8, 1, do_pati, + "pati - PATI specific Cmds\n", + "info - displays board information\n" + "pati pci - displays PCI registers\n" + "pati led \n" + " - switch LED \n" + "pati flash mem [SrcAddr]\n" + " - updates U-Boot with image in memory\n" + "pati eeprom - PCI EEPROM sub-system\n" + " read \n" + " - read PCI EEPROM to from words\n" + " write \n" + " - write PCI EEPROM from to words\n" + " prg - programm PCI EEPROM with default values\n" + " era - erase PCI EEPROM (write all word to 0xffff)\n" + " reload- Reload PCI Bridge with EEPROM Values\n" + " NOTE: must start on word boundary\n" + " and must be even byte values\n" +); + +/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pati/config.mk b/board/mpl/pati/config.mk new file mode 100644 index 0000000..b8a0985 --- /dev/null +++ b/board/mpl/pati/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003 +# Martin Winistoerfer, martinwinistoerfer@gmx.ch. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EPQ Board Configuration +# + +# Boot from flash at location 0x00000000 +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c new file mode 100644 index 0000000..0355b65 --- /dev/null +++ b/board/mpl/pati/pati.c @@ -0,0 +1,618 @@ +/* + * (C) Copyright 2003 + * Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * Atapted for PATI + * Denis Peter, d.peter@mpl.ch + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*********************************************************************************** + * Bits for the SDRAM controller + * ----------------------------- + * + * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on + * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM + * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3). + * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default) + * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns. + * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns. + * If set to 1 tWR must be equal or less 50ns. + * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less + * 25ns. If set to 1 tRP must be equal or less 50ns. + * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal + * or less 75ns. If set to 1 tRC must be equal or less 100ns. + * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM + * is the Load Mode Register Command. + * IIP: Init in progress. Set to 1 for starting the init sequence + * (Precharge All). As long this bit is set, the Precharge All is still in progress. + * After command has completed, wait at least for 8 refresh (200usec) before proceed. + **********************************************************************************/ + +#include +#include +#include +#include +#define PLX9056_LOC +#include "plx9056.h" +#include "pati.h" + +#if defined(__APPLE__) +/* Leading underscore on symbols */ +# define SYM_CHAR "_" +#else /* No leading character on symbols */ +# define SYM_CHAR +#endif + +#undef SDRAM_DEBUG +/* + * Macros to generate global absolutes. + */ +#define GEN_SYMNAME(str) SYM_CHAR #str +#define GEN_VALUE(str) #str +#define GEN_ABS(name, value) \ + asm (".globl " GEN_SYMNAME(name)); \ + asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) + + +/************************************************************************ + * Early debug routines + */ +void write_hex (unsigned char i) +{ + char cc; + + cc = i >> 4; + cc &= 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); + cc = i & 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); +} + +#if defined(SDRAM_DEBUG) + +void write_4hex (unsigned long val) +{ + write_hex ((unsigned char) (val >> 24)); + write_hex ((unsigned char) (val >> 16)); + write_hex ((unsigned char) (val >> 8)); + write_hex ((unsigned char) val); +} + +#endif + +unsigned long in32(unsigned long addr) +{ + unsigned long *p=(unsigned long *)addr; + return *p; +} + +void out32(unsigned long addr,unsigned long data) +{ + unsigned long *p=(unsigned long *)addr; + *p=data; +} + +typedef struct { + unsigned short boardtype; /* Board revision and Population Options */ + unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */ + unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/ + unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */ + unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */ + unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */ + unsigned char sz; /* log binary => Size = (4MByte< Size 2 = 16MByte, 1=8 */ + }, + { 0xffff, /* terminator */ + 0xff, + 0xff, + 0xff, + 0xff, + 0xff, + 0xff } +}; + + +extern int mem_test (unsigned long start, unsigned long ramsize, int quiet); +extern void mem_test_reloc(void); + +/* + * Get RAM size. + */ +long int initdram(int board_type) +{ + unsigned char board_rev; + unsigned long reg; + unsigned long lmr; + int i,timeout; + +#if defined(SDRAM_DEBUG) + reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); + puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg)); + puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg)); + puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg)); + puts(" Vers 0x"); write_4hex(SDRAM_ID(reg)); + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg)); + putc('\n'); +#endif + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + board_rev=(unsigned char)(SYSCNTR_BREV(reg)); + i=0; + while(1) { + if(sdram_table[i].boardtype==0xffff) { + puts("ERROR, found no table for Board 0x"); + write_hex(board_rev); + while(1); + } + if(sdram_table[i].boardtype==(unsigned char)board_rev) + break; + i++; + } + /* Set CAL, RCD, WREQ, PR and RC Bits */ +#if defined(SDRAM_DEBUG) + puts("Set CAL, RCD, WREQ, PR and RC Bits\n"); +#endif + /* mask bits */ + reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) | + SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) | + SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0)); + /* set bits */ + reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) | + SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) | + SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) | + SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) | + SET_REG_BIT(sdram_table[i].rc,SDRAM_RC)); + + out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); + /* step 2 set IIP */ +#if defined(SDRAM_DEBUG) + puts("step 2 set IIP\n"); +#endif + /* step 2 set IIP */ + reg |= SET_REG_BIT(1,SDRAM_IIP); + timeout=0; + while (timeout!=0xffff) { + __asm__ volatile("eieio"); + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + if((reg & SET_REG_BIT(1,SDRAM_IIP))==0) + break; + timeout++; + udelay(1); + } + /* wait for at least 8 refresh */ + udelay(1000); + /* set LMR */ + reg |= SET_REG_BIT(1,SDRAM_LMR); + out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); + __asm__ volatile("eieio"); + lmr=0x00000002; /* sequential burst 4 data */ + if(sdram_table[i].cal==1) + lmr|=0x00000030; /* cal = 3 */ + else + lmr|=0000000020; /* cal = 2 */ + /* rest standard operation programmed write burst length */ + /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */ + lmr<<=2; + in32(CFG_SDRAM_BASE + lmr); + /* ok, we're done, return SDRAM size */ + return ((0x400000 << sdram_table[i].sz)); /* log2 value of 4MByte */ +} + + +void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp) +{ + unsigned long reg; + reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE); + reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) | + SET_REG_BIT(1,SYSCNTR_FL_VPP) | + SET_REG_BIT(1,SYSCNTR_FL_WP)); + + reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) | + SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) | + SET_REG_BIT(ext_wp,SYSCNTR_FL_WP)); + out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg); + udelay(100); +} + + +void show_pld_regs(void) +{ + unsigned long reg,reg1; + reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); + printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg)); + printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg)); + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A')); + printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg)); + printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n", + GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD), + GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR), + GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR), + GET_REG_BIT(reg,SDRAM_IIP)); + reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1); + reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2); + printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n", + GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP), + GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM), + GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg), + GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM)); + printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg), + GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN), + GET_SYSCNTR_CFG(reg1)); + printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n", + GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP), + GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP)); +} + + +/**************************************************************** + * Setting IOs + * ----------- + * GPIO6 is User LED1 + * GPIO7 is Interrupt PLX (Output) + * GPIO5 is User LED0 + * GPIO2 is PLX USERi (Output) + * GPIO1 is PLX Interrupt (Input) + ****************************************************************/ + void init_ios(void) + { + volatile immap_t * immr = (immap_t *) CFG_IMMR; + volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; + unsigned long reg; + reg=sysconf->sc_sgpiocr; /* Data direction register */ + reg &= ~0x67000000; + reg |= 0x27000000; /* set outpupts */ + sysconf->sc_sgpiocr=reg; /* Data direction register */ + reg=sysconf->sc_sgpiodt2; /* Data register */ + /* set output to 0 */ + reg &= ~0x27000000; + /* set IRQ and USERi to 1 */ + reg |= 0x28000000; + sysconf->sc_sgpiodt2=reg; /* Data register */ +} + +void user_led0(int led_on) +{ + volatile immap_t * immr = (immap_t *) CFG_IMMR; + volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; + unsigned long reg; + reg=sysconf->sc_sgpiodt2; /* Data register */ + if(led_on) /* set output to 1 */ + reg |= 0x04000000; + else + reg &= ~0x04000000; + sysconf->sc_sgpiodt2=reg; /* Data register */ +} + +void user_led1(int led_on) +{ + volatile immap_t * immr = (immap_t *) CFG_IMMR; + volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; + unsigned long reg; + reg=sysconf->sc_sgpiodt2; /* Data register */ + if(led_on) /* set output to 1 */ + reg |= 0x02000000; + else + reg &= ~0x02000000; + sysconf->sc_sgpiodt2=reg; /* Data register */ +} + + +/**************************************************************** + * Last Stage Init + ****************************************************************/ +int last_stage_init (void) +{ + mem_test_reloc(); + init_ios(); + return 0; +} + +/**************************************************************** + * Check the board + ****************************************************************/ + +#define BOARD_NAME "PATI" + +int checkboard (void) +{ + unsigned char s[50]; + unsigned long reg; + char rev; + int i; + + puts ("\nBoard: "); + reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); + rev=(char)(SYSCNTR_BREV(reg)+'A'); + i = getenv_r ("serial#", s, 32); + if ((i == -1)) { + puts ("### No HW ID - assuming " BOARD_NAME); + printf(" Rev. %c\n",rev); + } + else { + s[sizeof(BOARD_NAME)-1] = 0; + printf ("%s-1 Rev %c SN: %s\n", s,rev, + &s[sizeof(BOARD_NAME)]); + } + set_flash_vpp(1,0,0); /* set Flash VPP */ + return 0; +} + + +#ifdef CFG_PCI_CON_DEVICE +/************************************************************************ + * PCI Communication + * + * Alive (Pinging): + * ---------------- + * PCI Host sends message ALIVE, Local acknowledges with ALIVE + * + * PCI_CON console over PCI: + * ------------------------- + * Local side: + * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that + * data is avaible (PCIMSG_CONN) + * - uses PCI9056_MAILBOX1 to send data + * - uses PCI9056_MAILBOX0 to receive data + * PCI side: + * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that + * data is avaible (PCIMSG_CONN) + * - uses PCI9056_MAILBOX0 to send data + * - uses PCI9056_MAILBOX1 to receive data + * + * How it works: + * Send: + * - check if PCICON_TRANSMIT_REG is empty + * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG + * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data + * is waiting + * Receive: + * - get an interrupt via the PCICON_ACK_REG register message + * PCIMSG_CONN + * - write the data from the PCICON_RECEIVE_REG into the receive + * buffer and if the receive buffer is not full, clear the + * PCICON_RECEIVE_REG (this allows the counterpart to write more data) + * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG + * + * The PCICON_RECEIVE_REG must be cleared by the routine which reads + * the receive buffer if the buffer is not full any more + * + */ + +#undef PCI_CON_DEBUG + +#ifdef PCI_CON_DEBUG +#define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args) +#else +#define PCI_CON_PRINTF(fmt,args...) +#endif + + +/********************************************************* + * we work only with a receive buffer on eiter side. + * Transmit buffer is free, if mailbox is cleared. + * Transmit character is or'ed with 0x80000000 + * PATI receive register MAILBOX0 + * PATI transmit register MAILBOX1 + *********************************************************/ +#define PCICON_RECEIVE_REG PCI9056_MAILBOX0 +#define PCICON_TRANSMIT_REG PCI9056_MAILBOX1 +#define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL +#define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL + + +#define PCIMSG_ALIVE 0x1 +#define PCIMSG_CONN 0x2 +#define PCIMSG_DISC 0x3 +#define PCIMSG_CON_DATA 0x5 + + +#define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE)) +#define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y)) +#define PCICON_TX_FLAG 0x80000000 + + +#define REC_BUFFER_SIZE 0x100 +int recbuf[REC_BUFFER_SIZE]; +static int r_ptr = 0; +int w_ptr; +device_t pci_con_dev; +int conn=0; +int buff_full=0; + +void pci_con_put_it(const char c) +{ + /* Test for completition */ + unsigned long reg; + do { + reg=PCICON_GET_REG(PCICON_TRANSMIT_REG); + }while(reg); + reg=PCICON_TX_FLAG + c; + PCICON_SET_REG(PCICON_TRANSMIT_REG,reg); + PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA); +} + +void pci_con_putc(const char c) +{ + pci_con_put_it(c); + if(c == '\n') + pci_con_put_it('\r'); +} + + +int pci_con_getc(void) +{ + int res; + int diff; + while(r_ptr==(volatile int)w_ptr); + res=recbuf[r_ptr++]; + if(r_ptr==REC_BUFFER_SIZE) + r_ptr=0; + if(w_ptr(REC_BUFFER_SIZE-4)) + buff_full=1; + else + /* clear Mail box */ + PCICON_SET_REG(PCICON_RECEIVE_REG,0L); + break; + default: + serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg); + } + /* clear IRQ */ + PCICON_SET_REG(PCICON_ACK_REG,~0L); + } + return 0; +} + +void pci_con_connect(void) +{ + unsigned long reg; + conn=0; + reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT); + /* default 0x0f010180 */ + reg &= 0xff000000; + reg |= 0x00030000; /* enable local dorbell */ + reg |= 0x00000300; /* enable PCI dorbell */ + PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg); + irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL); + memset (&pci_con_dev, 0, sizeof (pci_con_dev)); + strcpy (pci_con_dev.name, "pci_con"); + pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + pci_con_dev.putc = pci_con_putc; + pci_con_dev.puts = pci_con_puts; + pci_con_dev.getc = pci_con_getc; + pci_con_dev.tstc = pci_con_tstc; + device_register (&pci_con_dev); + printf("PATI ready for PCI connection, type ctrl-c for exit\n"); + do { + udelay(10); + if((volatile int)conn) + break; + if(ctrlc()) { + irq_free_handler(0x2); + return; + } + }while(1); + console_assign(stdin,"pci_con"); + console_assign(stderr,"pci_con"); + console_assign(stdout,"pci_con"); +} + +void pci_con_disc(void) +{ + console_assign(stdin,"serial"); + console_assign(stderr,"serial"); + console_assign(stdout,"serial"); + PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC); + /* reconnection */ + irq_free_handler(0x02); + pci_con_connect(); +} +#endif /* #ifdef CFG_PCI_CON_DEVICE */ + +/* + * Absolute environment address for linker file. + */ +GEN_ABS(env_start, CFG_ENV_OFFSET + CFG_FLASH_BASE); diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h new file mode 100644 index 0000000..d521772 --- /dev/null +++ b/board/mpl/pati/pati.h @@ -0,0 +1,440 @@ +/* + * (C) Copyright 2003 + * Denis Peter, d.peter@mpl.ch + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/************************************************************************ + * MACROS and register definitions for PATI Registers + ************************************************************************/ +#ifndef __PATI_H_ +#define __PATI_H_ 1 + +#define PLD_PART_ID 0x0 +#define PLD_BOARD_TIMING 0x4 +#define PLD_CONF_REG1 0x8 +#define PLD_CONF_REG2 0xC +#define PLD_CONF_RES 0x10 + +#define SET_REG_BIT(y,x) (y<<(31-x)) +#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L) + +/* SDRAM Controller PLD_PART_ID */ +/* 9 10 11 12 13 14 19 31 */ +#define SDRAM_PART3 9 +#define SDRAM_PART2 10 +#define SDRAM_PART1 11 +#define SDRAM_PART0 12 +#define SDRAM_ID3 13 +#define SDRAM_ID2 14 +#define SDRAM_ID1 19 +#define SDRAM_ID0 31 + +#define SDRAM_PART(x) ( \ + (GET_REG_BIT(x,SDRAM_PART3)<<3) |\ + (GET_REG_BIT(x,SDRAM_PART2)<<2) |\ + (GET_REG_BIT(x,SDRAM_PART1)<<1) |\ + (GET_REG_BIT(x,SDRAM_PART0))) + +#define SDRAM_ID(x) ( \ + (GET_REG_BIT(x,SDRAM_ID3)<<3) |\ + (GET_REG_BIT(x,SDRAM_ID2)<<2) |\ + (GET_REG_BIT(x,SDRAM_ID1)<<1) |\ + (GET_REG_BIT(x,SDRAM_ID0))) + +/* System Controller */ +/* 0 1 3 4 5 16 20 28 29 30 */ +#define SYSCNTR_PART4 0 +#define SYSCNTR_PART3 1 +#define SYSCNTR_PART2 3 +#define SYSCNTR_PART1 4 +#define SYSCNTR_PART0 5 +#define SYSCNTR_ID4 16 +#define SYSCNTR_ID3 20 +#define SYSCNTR_ID2 28 +#define SYSCNTR_ID1 29 +#define SYSCNTR_ID0 30 + +#define SYSCNTR_PART(x) ( \ + (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\ + (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\ + (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_PART0))) + +#define SYSCNTR_ID(x) ( \ + (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\ + (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\ + (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_ID0))) + +/* SDRAM Controller PLD_BOARD_TIMING */ +/* 9 10 11 12 13 14 19 31 */ +#define SDRAM_CAL 9 +#define SDRAM_RCD 10 +#define SDRAM_WREQ 11 +#define SDRAM_PR 12 +#define SDRAM_RC 13 +#define SDRAM_LMR 14 +#define SDRAM_IIP 19 +#define SDRAM_RES0 31 +/* System Controller */ +/* 0 1 3 4 5 16 20 28 29 30 */ +#define SYSCNTR_BREV0 0 +#define SYSCNTR_BREV1 1 +#define SYSCNTR_BREV2 3 +#define SYSCNTR_BREV3 4 +#define SYSCNTR_RES0 5 +#define SYSCNTR_RES1 16 +#define SYSCNTR_RES2 20 +#define SYSCNTR_FLWAIT2 28 +#define SYSCNTR_FLWAIT1 29 +#define SYSCNTR_FLWAIT0 30 + +#define SYSCNTR_BREV(x) ( \ + (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\ + (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_BREV0))) + +#define GET_SYSCNTR_FLWAIT(x) ( \ + (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_FLWAIT0))) + +#define SET_SYSCNTR_FLWAIT(x) ( \ + (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\ + (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\ + (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0))) + +/* SDRAM Controller REG 2*/ +/* 9 10 11 12 13 14 19 31 */ +#define SDRAM_MUX0 9 +#define SDRAM_MUX1 10 +#define SDRAM_PDIS 11 +#define SDRAM_RES1 12 +#define SDRAM_RES2 13 +#define SDRAM_RES3 14 +#define SDRAM_RES4 19 +#define SDRAM_RIP 31 + +#define GET_SDRAM_MUX(x) ( \ + (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \ + (GET_REG_BIT(x,SDRAM_MUX0))) + + +/* System Controller */ +/* 0 1 3 4 5 16 20 28 29 30 */ +#define SYSCNTR_FLAG 0 +#define SYSCNTR_IP 1 +#define SYSCNTR_BIND2 3 +#define SYSCNTR_BIND1 4 +#define SYSCNTR_BIND0 5 +#define SYSCNTR_PRM 16 +#define SYSCNTR_ICW 20 +#define SYSCNTR_ISB2 28 +#define SYSCNTR_ISB1 29 +#define SYSCNTR_ISB0 30 + +#define GET_SYSCNTR_BOOTIND(x) ( \ + (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\ + (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\ + (GET_REG_BIT(x,SYSCNTR_BIND0))) + +#define SET_SYSCNTR_BOOTIND(x) ( \ + (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\ + (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \ + (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0))) + +#define GET_SYSCNTR_ISB(x) ( \ + (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \ + (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \ + (GET_REG_BIT(x,SYSCNTR_ISB0))) + +#define SET_SYSCNTR_ISB(x) ( \ + (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \ + (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \ + (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0))) + +/* SDRAM Controller REG 3*/ +/* 9 10 11 12 13 14 19 31 */ +#define SDRAM_RES5 9 +#define SDRAM_CFG1 10 +#define SDRAM_CFG2 11 +#define SDRAM_CFG3 12 +#define SDRAM_RES6 13 +#define SDRAM_CFG5 14 +#define SDRAM_CFG6 19 +#define SDRAM_RES7 31 + +#define GET_SDRAM_CFG(x) ( \ + (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\ + (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\ + (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\ + (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\ + (GET_REG_BIT(x,SDRAM_CFG1))) + +/* System Controller */ +/* 0 1 3 4 5 16 20 28 29 30 */ +#define SYSCNTR_BDIS 0 +#define SYSCNTR_PCIM 1 +#define SYSCNTR_CFG0 3 +#define SYSCNTR_CFG1 4 +#define SYSCNTR_CFG2 5 +#define SYSCNTR_CFG3 16 +#define SYSCNTR_BOOTEN 20 +#define SYSCNTR_CPU_VPP 28 +#define SYSCNTR_FL_VPP 29 +#define SYSCNTR_FL_WP 30 + +#define GET_SYSCNTR_CFG(x) ( \ + (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \ + (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \ + (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \ + (GET_REG_BIT(x,SYSCNTR_CFG0))) + + +/*************************************************************** + * MISC Defines + ***************************************************************/ + +#define PCI_VENDOR_ID_MPL 0x18E6 +#define PCI_DEVICE_ID_PATI 0x00DA + +#if defined(CONFIG_MIP405) +#define PATI_FIRMWARE_START_OFFSET 0x00300000 +#define PATI_ISO_STRING "MEV-10084-001" +#endif + +#define PATI_ENDIAN_MODE 0x3E + +/******************************************* + * PATI Mapping: + * ------------- + * PCI Map: + * ------- + * All addreses are mapped into the memory area + * (IO Area on some areas may also be possible) + * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes + * - pci_space0_addr: configurable + * - pci_space1_addr configurable + * + * Local Map: + * ---------- + * Local addresses (Remap) + * - SDRAM 0x06000000 Size 16MByte mask 0xff000000 + * - EPLD CFG 0x07000000 Size 512Bytes + * - FLASH 0x03000000 Size up to 8MByte + * - CPU 0x01000000 Size 4MByte (only accessable if special configured) + * + * Implemention: + * ------------- + * To prevent using large resources reservation on the host following + * PCI mapping is choosed: + * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes + * - pci_space0_addr: configured to the EPLD Config Area size 256Bytes + * - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this + * space is used to switch between SDRAM, Flash and CPU + * + */ + +/* Attribute definitions */ +#define PATI_BUS_SIZE_8 0 +#define PATI_BUS_SIZE_16 1 +#define PATI_BUS_SIZE_32 3 + +#define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */ +#define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */ + +#define PATI_EXTRA_LONG_EEPROM 1 + +#define SPACE0_TA_ENABLE (1<<6) +#define SPACE1_TA_ENABLE (1<<6) + +/* Config Area */ +#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */ +#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */ +/* Attributes */ +#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ +#define PATI_LOC_CFG_BURST 0 /* No Burst */ +#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */ +#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */ + +#define PATI_LOC_CFG_SPACE0_ATTR ( \ + PATI_LOC_CFG_BUS_SIZE | \ + (PATI_LOC_CFG_TA_ENABLE << 6) | \ + (PATI_LOC_CFG_NO_PREFETCH << 8) | \ + (PATI_LOC_CFG_BURST << 24) | \ + (PATI_EXTRA_LONG_EEPROM << 25)) + +/* should never be used */ +#define PATI_LOC_CFG_SPACE1_ATTR ( \ + PATI_LOC_CFG_BUS_SIZE | \ + (PATI_LOC_CFG_TA_ENABLE << 6) | \ + (PATI_LOC_CFG_NO_PREFETCH << 9) | \ + (PATI_LOC_CFG_BURST << 8)) + + +/* SDRAM Area */ +#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */ +#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */ +/* Attributes */ +#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ +#define PATI_LOC_SDRAM_BURST 0 /* No Burst */ +#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */ +#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */ + +/* should never be used */ +#define PATI_LOC_SDRAM_SPACE0_ATTR ( \ + PATI_LOC_SDRAM_BUS_SIZE | \ + (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ + (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \ + (PATI_LOC_SDRAM_BURST << 24) | \ + (PATI_EXTRA_LONG_EEPROM << 25)) + +#define PATI_LOC_SDRAM_SPACE1_ATTR ( \ + PATI_LOC_SDRAM_BUS_SIZE | \ + (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ + (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \ + (PATI_LOC_SDRAM_BURST << 8)) + + +/* Flash Area */ +#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */ +#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */ +/* Attributes */ +#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */ +#define PATI_LOC_FLASH_BURST 0 /* No Burst */ +#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */ +#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */ + +/* should never be used */ +#define PATI_LOC_FLASH_SPACE0_ATTR ( \ + PATI_LOC_FLASH_BUS_SIZE | \ + (PATI_LOC_FLASH_TA_ENABLE << 6) | \ + (PATI_LOC_FLASH_NO_PREFETCH << 8) | \ + (PATI_LOC_FLASH_BURST << 24) | \ + (PATI_EXTRA_LONG_EEPROM << 25)) + +#define PATI_LOC_FLASH_SPACE1_ATTR ( \ + PATI_LOC_FLASH_BUS_SIZE | \ + (PATI_LOC_FLASH_TA_ENABLE << 6) | \ + (PATI_LOC_FLASH_NO_PREFETCH << 9) | \ + (PATI_LOC_FLASH_BURST << 8)) + + +/* CPU Area */ +#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */ +#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */ +/* Attributes */ +#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ +#define PATI_LOC_CPU_BURST 0 /* No Burst */ +#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */ +#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */ + +/* should never be used */ +#define PATI_LOC_CPU_SPACE0_ATTR ( \ + PATI_LOC_CPU_BUS_SIZE | \ + (PATI_LOC_CPU_TA_ENABLE << 6) | \ + (PATI_LOC_CPU_NO_PREFETCH << 8) | \ + (PATI_LOC_CPU_BURST << 24) | \ + (PATI_EXTRA_CPU_EEPROM << 25)) + +#define PATI_LOC_CPU_SPACE1_ATTR ( \ + PATI_LOC_CPU_BUS_SIZE | \ + (PATI_LOC_CPU_TA_ENABLE << 6) | \ + (PATI_LOC_CPU_NO_PREFETCH << 9) | \ + (PATI_LOC_CPU_BURST << 8)) + +/*************************************************** + * Hardware Config word definition + ***************************************************/ +#define BOOT_EXT_FLASH 0x00000000 +#define BOOT_INT_FLASH 0x00000004 +#define BOOT_FROM_PCI 0x00000006 +#define BOOT_FROM_SDRAM 0x00000005 + +#define ENABLE_INT_ARB 0x00000008 + +#define INITIAL_IRQ_PREF 0x00000010 + +#define INITIAL_MEM_0M 0x00000000 +#define INITIAL_MEM_4M 0x00000080 +#define INITIAL_MEM_8M 0x00000040 +#define INITIAL_MEM_12M 0x000000C0 +#define INITIAL_MEM_16M 0x00000020 +#define INITIAL_MEM_20M 0x000000A0 +#define INITIAL_MEM_24M 0x00000060 +#define INITIAL_MEM_28M 0x000000E0 +/* CONF */ +#define INTERNAL_HWCONF 0x00000100 +/* PRPM */ +#define LOCAL_CPU_SLAVE 0x00000200 +/* BDIS */ +#define DISABLE_MEM_CNTR 0x00000400 +/* PCIM */ +#define PCI_MASTER_ONLY 0x00000800 + + +#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF)) +#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) +#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) +#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE)) + +/*************************************************** + * Direct Master Config + ***************************************************/ +#define PATI_DMASTER_PCI_ADDR 0x01000000 +#define PATI_BUS_MASTER 1 + + +#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */ +#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */ + +#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */ +#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */ +#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */ +#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000 +#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008 +#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000 +#define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008 +#define PATI_DMASTER_REL_PCI 0x00000000 +#define PATI_DMASTER_NOT_REL_PCI 0x00000010 +#define PATI_DMASTER_WR_INVAL 0x00000200 +#define PATI_DMASTER_NOT_WR_INVAL 0x00000000 +#define PATI_DMASTER_PRE_LIMIT 0x00000800 +#define PATI_DMASTER_PRE_CONT 0x00000000 +#define PATI_DMASTER_DELAY_WR_0 0x00000000 +#define PATI_DMASTER_DELAY_WR_4 0x00004000 +#define PATI_DMASTER_DELAY_WR_8 0x00008000 +#define PATI_DMASTER_DELAY_WR_16 0x0000C000 + +#define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000 + +#define PATI_DMASTER_ATTR \ + PATI_DMASTER_MEMORY_EN | \ + PATI_DMASTER_READ_AHEAD | \ + PATI_DMASTER_PRE_SIZE_CNTRL_4 | \ + PATI_DMASTER_REL_PCI | \ + PATI_DMASTER_NOT_WR_INVAL | \ + PATI_DMASTER_PRE_LIMIT | \ + PATI_DMASTER_DELAY_WR_0 + + +#endif /* #ifndef __PATI_H_ */ diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h new file mode 100644 index 0000000..9658808 --- /dev/null +++ b/board/mpl/pati/pci_eeprom.h @@ -0,0 +1,91 @@ + +#ifndef __PCI_EEPROM_H_ +#define __PCI_EEPROM_H_ 1 + +#include "pati.h" +/****************************************************************************** + * Eeprom Support + ******************************************************************************/ +/********************************************** +* Definitions +**********************************************/ +#define EE46_CMD_LEN 9 /* Bits in instructions */ +#define EE56_CMD_LEN 11 /* Bits in instructions */ +#define EE66_CMD_LEN 11 /* Bits in instructions */ +#define EE_READ 0x0180 /* 01 1000 0000 read instruction */ +#define EE_WRITE 0x0140 /* 01 0100 0000 write instruction */ +#define EE_WREN 0x0130 /* 01 0011 0000 write enable instruction */ +#define EE_WRALL 0x0110 /* 01 0001 0000 write all registers */ +#define EE_PRREAD 0x0180 /* 01 1000 0000 read address stored in Protect Register */ +#define EE_PRWRITE 0x0140 /* 01 0100 0000 write the address into PR */ +#define EE_WDS 0x0100 /* 01 0000 0000 write disable instruction */ +#define EE_PREN 0x0130 /* 01 0011 0000 protect enable instruction */ +#define EE_PRCLEAR 0x01FF /* 01 1111 1111 clear protect register instr */ +#define EE_PRDS 0x0100 /* 01 0000 0000 ONE TIME ONLY, permenant */ + +/*************************************************** + * EEPROM + ***************************************************/ +#define LOW_WORD(x) (((x) & 0xFFFF)) +#define HIGH_WORD(x) (((x) >> 16) & 0xFFFF) + +typedef struct pci_eeprom_t { + unsigned short offset; + unsigned short value; +} pci_eeprom; + +static pci_eeprom pati_eeprom[] = { + { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */ + { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */ + { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */ + { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */ + { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */ + { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */ + { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */ + { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */ + { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */ + { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */ + { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */ + { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */ + { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */ + { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */ + { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */ + { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */ + { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */ + { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */ + { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */ + { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */ + { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */ + { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */ + { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */ + { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */ + { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */ + { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */ + { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */ + { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */ + { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */ + { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */ + { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */ + { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */ + { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/ + { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */ + { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */ + { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */ + { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */ + { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */ + { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */ + { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */ + { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */ + { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */ + { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */ + { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */ + { 0x58,0x0000 }, /* Reserved Reserved */ + { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */ + { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */ + { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/ + { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */ + { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */ + { 0xFFFF,0xFFFF} /* terminaror */ +}; +#define PATI_EEPROM_LAST_OFFSET 0x64 +#endif /* #ifndef __PCI_EEPROM_H_ */ diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h new file mode 100644 index 0000000..cd4df18 --- /dev/null +++ b/board/mpl/pati/plx9056.h @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2003 + * Denis Peter, d.peter@mpl.ch + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* PLX9096 register definitions +*/ +#ifndef __PLX9056_H_ +#define __PLX9056_H_ 1 + +#include + +#ifdef PLX9056_LOC +#define LOCAL_OFFSET 0x080 +/* PCI Config regs */ +#else +#define LOCAL_OFFSET 0x000 +#endif + +#define PCI9056_VENDOR_ID PCI_VENDOR_ID +/*#define PCI9656_DEVICE_ID PCI_DEVICE_ID */ +#define PCI9056_COMMAND PCI_COMMAND +/*#define PCI9656_STATUS PCI_STATUS */ +#define PCI9056_REVISION PCI_REVISION_ID + +#define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE +#define PCI9056_RTR_BASE PCI_BASE_ADDRESS_0 +#define PCI9056_RTR_IO_BASE PCI_BASE_ADDRESS_1 +#define PCI9056_LOCAL_BASE0 PCI_BASE_ADDRESS_2 +#define PCI9056_LOCAL_BASE1 PCI_BASE_ADDRESS_3 +#define PCI9056_UNUSED_BASE1 PCI_BASE_ADDRESS_4 +#define PCI9056_UNUSED_BASE2 PCI_BASE_ADDRESS_5 +#define PCI9056_CIS_PTR PCI_CARDBUS_CIS +#define PCI9056_SUB_ID PCI_SUBSYSTEM_VENDOR_ID +#define PCI9056_EXP_ROM_BASE PCI_ROM_ADDRESS +#define PCI9056_CAP_PTR PCI_CAPABILITY_LIST +#define PCI9056_INT_LINE PCI_INTERRUPT_LINE + +#if defined(PLX9056_LOC) + #define PCI9056_PM_CAP_ID 0x180 + #define PCI9056_PM_CSR 0x184 + #define PCI9056_HS_CAP_ID 0x188 + #define PCI9056_VPD_CAP_ID 0x18C + #define PCI9056_VPD_DATA 0x190 +#endif + + +#define PCI_DEVICE_ID_PLX9056 0x9056 + +/* Local Configuration Registers Accessible via the PCI Base address + Variable */ +#define PCI9056_SPACE0_RANGE (0x000 + LOCAL_OFFSET) +#define PCI9056_SPACE0_REMAP (0x004 + LOCAL_OFFSET) +#define PCI9056_LOCAL_DMA_ARBIT (0x008 + LOCAL_OFFSET) +#define PCI9056_ENDIAN_DESC (0x00c + LOCAL_OFFSET) +#define PCI9056_EXP_ROM_RANGE (0x010 + LOCAL_OFFSET) +#define PCI9056_EXP_ROM_REMAP (0x014 + LOCAL_OFFSET) +#define PCI9056_SPACE0_ROM_DESC (0x018 + LOCAL_OFFSET) +#define PCI9056_DM_RANGE (0x01c + LOCAL_OFFSET) +#define PCI9056_DM_MEM_BASE (0x020 + LOCAL_OFFSET) +#define PCI9056_DM_IO_BASE (0x024 + LOCAL_OFFSET) +#define PCI9056_DM_PCI_MEM_REMAP (0x028 + LOCAL_OFFSET) +#define PCI9056_DM_PCI_IO_CONFIG (0x02c + LOCAL_OFFSET) +#define PCI9056_SPACE1_RANGE (0x0f0 + LOCAL_OFFSET) +#define PCI9056_SPACE1_REMAP (0x0f4 + LOCAL_OFFSET) +#define PCI9056_SPACE1_DESC (0x0f8 + LOCAL_OFFSET) +#define PCI9056_DM_DAC (0x0fc + LOCAL_OFFSET) + +#ifdef PLX9056_LOC +#define PCI9056_ARBITER_CTRL 0x1A0 +#define PCI9056_ABORT_ADDRESS 0x1A4 +#endif + +/* Runtime registers PCI Address + LOCAL_OFFSET */ +#ifdef PLX9056_LOC +#define PCI9056_MAILBOX0 0x0C0 +#define PCI9056_MAILBOX1 0x0C4 +#else +#define PCI9056_MAILBOX0 0x078 +#define PCI9056_MAILBOX1 0x07c +#endif + +#define PCI9056_MAILBOX2 (0x048 + LOCAL_OFFSET) +#define PCI9056_MAILBOX3 (0x04c + LOCAL_OFFSET) +#define PCI9056_MAILBOX4 (0x050 + LOCAL_OFFSET) +#define PCI9056_MAILBOX5 (0x054 + LOCAL_OFFSET) +#define PCI9056_MAILBOX6 (0x058 + LOCAL_OFFSET) +#define PCI9056_MAILBOX7 (0x05c + LOCAL_OFFSET) +#define PCI9056_PCI_TO_LOC_DBELL (0x060 + LOCAL_OFFSET) +#define PCI9056_LOC_TO_PCI_DBELL (0x064 + LOCAL_OFFSET) +#define PCI9056_INT_CTRL_STAT (0x068 + LOCAL_OFFSET) +#define PCI9056_EEPROM_CTRL_STAT (0x06c + LOCAL_OFFSET) +#define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET) +#define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET) + +#endif /* #ifndef __PLX9056_H_ */ diff --git a/board/mpl/pati/u-boot.lds b/board/mpl/pati/u-boot.lds new file mode 100644 index 0000000..5b03fef --- /dev/null +++ b/board/mpl/pati/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de + * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +/* . = env_start; + .ppcenv : + { + common/environment.o (.ppcenv) + } +*/ +} diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile new file mode 100644 index 0000000..a818d08 --- /dev/null +++ b/board/mpl/pip405/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o \ + ../common/flash.o cmd_pip405.o ../common/pci.o \ + ../common/isa.o ../common/kbd.o \ + ../common/usb_uhci.o \ + ../common/memtst.o ../common/common_util.o + +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c new file mode 100644 index 0000000..1bf4d7b --- /dev/null +++ b/board/mpl/pip405/cmd_pip405.c @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * hacked for PIP405 + */ + +#include +#include +#include "pip405.h" +#include "../common/common_util.h" + + +extern void print_pip405_info(void); +extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + + +/* ------------------------------------------------------------------------- */ + +int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + ulong led_on,led_nr; + + if (strcmp(argv[1], "info") == 0) + { + print_pip405_info(); + return 0; + } + if (strcmp(argv[1], "led") == 0) + { + led_nr = (ulong)simple_strtoul(argv[2], NULL, 10); + led_on = (ulong)simple_strtoul(argv[3], NULL, 10); + if(!led_nr) + user_led0(led_on); + else + user_led1(led_on); + return 0; + } + + return (do_mplcommon(cmdtp, flag, argc, argv)); +} +U_BOOT_CMD( + pip405, 6, 1, do_pip405, + "pip405 - PIP405 specific Cmds\n", + "flash mem [SrcAddr] - updates U-Boot with image in memory\n" + "pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n" + "pip405 flash mps - updates U-Boot with image from MPS\n" +); + +/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pip405/config.mk b/board/mpl/pip405/config.mk new file mode 100644 index 0000000..0f8d153 --- /dev/null +++ b/board/mpl/pip405/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0xFFF80000 diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S new file mode 100644 index 0000000..39f2ea5 --- /dev/null +++ b/board/mpl/pip405/init.S @@ -0,0 +1,230 @@ +/*------------------------------------------------------------------------------+ + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *-------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- + * Function: ext_bus_cntlr_init + * Description: Initializes the External Bus Controller for the external + * peripherals. IMPORTANT: For pass1 this code must run from + * cache since you can not reliably change a peripheral banks + * timing register (pbxap) while running code from that bank. + * For ex., since we are running from ROM on bank 0, we can NOT + * execute the code that modifies bank 0 timings from ROM, so + * we run it from cache. + * Bank 0 - Flash or Multi Purpose Socket + * Bank 1 - Multi Purpose Socket or Flash + * Bank 2 - not used + * Bank 3 - not used + * Bank 4 - not used + * Bank 5 - not used + * Bank 6 - used to switch on the 12V for the Multipurpose socket + * Bank 7 - Config Register + *-----------------------------------------------------------------------------*/ +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include +#include + +#include +#include +#include "pip405.h" + + .globl ext_bus_cntlr_init + ext_bus_cntlr_init: + mflr r4 /* save link register */ + mfdcr r3,strap /* get strapping reg */ + andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ + bnelr /* jump back if PCI boot */ + + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 14; used to prefetch */ + mtctr r4 /* 14 cache lines to fit this function */ + /* in cache (gives us 8x14=112 instrctns) */ +..ebcloop: + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 14 cache lines */ + + /*------------------------------------------------------------------- + * Delay to ensure all accesses to ROM are complete before changing + * bank 0 timings. + *------------------------------------------------------------------- */ + addis r3,0,0x0 + ori r3,r3,0xA000 + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + /*----------------------------------------------------------------------- + * decide boot up mode + *----------------------------------------------------------------------- */ + addi r4,0,pb0cr + mtdcr ebccfga,r4 + mfdcr r4,ebccfgd + + andi. r0, r4, 0x2000 /* mask out irrelevant bits */ + beq 0f /* jump if 8 bit bus width */ + + /* setup 16 bit things + *----------------------------------------------------------------------- + * Memory Bank 0 (16 Bit Flash) initialization + *---------------------------------------------------------------------- */ + + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,(FLASH_AP_B)@h + ori r4,r4,(FLASH_AP_B)@l + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + /* BS=0x010(4MB),BU=0x3(R/W), */ + addis r4,0,(FLASH_CR_B)@h + ori r4,r4,(FLASH_CR_B)@l + mtdcr ebccfgd,r4 + b 1f + +0: + /* 8Bit boot mode: */ + /*----------------------------------------------------------------------- + * Memory Bank 0 Multi Purpose Socket initialization + *----------------------------------------------------------------------- */ + /* 0x7F8FFE80 slowest boot */ + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,(MPS_AP_B)@h + ori r4,r4,(MPS_AP_B)@l + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + /* BS=0x010(4MB),BU=0x3(R/W), */ + addis r4,0,(MPS_CR_B)@h + ori r4,r4,(MPS_CR_B)@l + mtdcr ebccfgd,r4 + + +1: + /*----------------------------------------------------------------------- + * Memory Bank 2-3-4-5-6 (not used) initialization + *-----------------------------------------------------------------------*/ + addi r4,0,pb1cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb2cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb3cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb4cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb5cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb6cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + + addi r4,0,pb7cr + mtdcr ebccfga,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr ebccfgd,r4 + nop /* pass2 DCR errata #8 */ + blr + +/*----------------------------------------------------------------------------- + * Function: sdram_init + * Description: Configures the internal SRAM memory. and setup the + * Stackpointer in it. + *----------------------------------------------------------------------------- */ + .globl sdram_init + +sdram_init: + + + blr + + +#if defined(CONFIG_BOOT_PCI) + .section .bootpg,"ax" + .globl _start_pci +/******************************************* + */ + +_start_pci: + /* first handle errata #68 / PCI_18 */ + iccci r0, r0 /* invalidate I-cache */ + lis r31, 0 + mticcr r31 /* ICCR = 0 (all uncachable) */ + isync + + mfccr0 r28 /* set CCR0[24] = 1 */ + ori r28, r28, 0x0080 + mtccr0 r28 + + /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ + lis r28, 0xEF40 + addi r28, r28, 0x0004 + stw r31, 0x0C(r28) /* clear PMM0PCIHA */ + lis r29, 0xFFF8 /* open 512 kByte */ + addi r29, r29, 0x0001/* and enable this region */ + stwbrx r29, r0, r28 /* write PMM0MA */ + + lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ + addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ + + lis r31, 0x8000 /* set en bit bus 0 */ + ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ + stwbrx r31, r0, r28 /* write it */ + + lwbrx r31, r0, r29 /* load XBCS register */ + oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ + stwbrx r31, r0, r29 /* write back XBCS register */ + + nop + nop + b _start /* normal start */ +#endif diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c new file mode 100644 index 0000000..a398362 --- /dev/null +++ b/board/mpl/pip405/pip405.c @@ -0,0 +1,960 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * TODO: clean-up + */ + +#include +#include "pip405.h" +#include +#include +#include "../common/isa.h" +#include "../common/common_util.h" + +#undef SDRAM_DEBUG + +#define FALSE 0 +#define TRUE 1 + +/* stdlib.h causes some compatibility problems; should fixe these! -- wd */ +#ifndef __ldiv_t_defined +typedef struct { + long int quot; /* Quotient */ + long int rem; /* Remainder */ +} ldiv_t; +extern ldiv_t ldiv (long int __numer, long int __denom); + +# define __ldiv_t_defined 1 +#endif + + +typedef enum { + SDRAM_NO_ERR, + SDRAM_SPD_COMM_ERR, + SDRAM_SPD_CHKSUM_ERR, + SDRAM_UNSUPPORTED_ERR, + SDRAM_UNKNOWN_ERR +} SDRAM_ERR; + +typedef struct { + const unsigned char mode; + const unsigned char row; + const unsigned char col; + const unsigned char bank; +} SDRAM_SETUP; + +static const SDRAM_SETUP sdram_setup_table[] = { + {1, 11, 9, 2}, + {1, 11, 10, 2}, + {2, 12, 9, 4}, + {2, 12, 10, 4}, + {3, 13, 9, 4}, + {3, 13, 10, 4}, + {3, 13, 11, 4}, + {4, 12, 8, 2}, + {4, 12, 8, 4}, + {5, 11, 8, 2}, + {5, 11, 8, 4}, + {6, 13, 8, 2}, + {6, 13, 8, 4}, + {7, 13, 9, 2}, + {7, 13, 10, 2}, + {0, 0, 0, 0} +}; + +static const unsigned char cal_indextable[] = { + 9, 23, 25 +}; + + +/* + * translate ns.ns/10 coding of SPD timing values + * into 10 ps unit values + */ + +unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version) +{ + unsigned short ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + return (ns * 100 + ns10 * 10); +} + +/* + * translate ns.ns/4 coding of SPD timing values + * into 10 ps unit values + */ + +unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version) +{ + unsigned short ns, ns4; + + /* isolate upper 6 bits */ + ns = (spd_byte >> 2) & 0x3F; + /* isloate lower 2 bits */ + ns4 = (spd_byte & 0x03); + + return (ns * 100 + ns4 * 25); +} + +/* + * translate ns coding of SPD timing values + * into 10 ps unit values + */ + +unsigned short NSto10PS (unsigned char spd_byte) +{ + return (spd_byte * 100); +} + +void SDRAM_err (const char *s) +{ +#ifndef SDRAM_DEBUG + DECLARE_GLOBAL_DATA_PTR; + + (void) get_clocks (); + gd->baudrate = 9600; + serial_init (); +#endif + serial_puts ("\n"); + serial_puts (s); + serial_puts ("\n enable SDRAM_DEBUG for more info\n"); + for (;;); +} + + +#ifdef SDRAM_DEBUG + +void write_hex (unsigned char i) +{ + char cc; + + cc = i >> 4; + cc &= 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); + cc = i & 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); +} + +void write_4hex (unsigned long val) +{ + write_hex ((unsigned char) (val >> 24)); + write_hex ((unsigned char) (val >> 16)); + write_hex ((unsigned char) (val >> 8)); + write_hex ((unsigned char) val); +} + +#endif + +int board_early_init_f (void) +{ + unsigned char dataout[1]; + unsigned char datain[128]; + unsigned long sdram_size = 0; + SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; + unsigned long memclk; + unsigned long tmemclk = 0; + unsigned long tmp, bank, baseaddr, bank_size; + unsigned short i; + unsigned char rows, cols, banks, sdram_banks, density; + unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, + trc_clocks, tctp_clocks; + unsigned char cal_index, cal_val, spd_version, spd_chksum; + unsigned char buf[8]; +#ifdef SDRAM_DEBUG + DECLARE_GLOBAL_DATA_PTR; +#endif + /* set up the config port */ + mtdcr (ebccfga, pb7ap); + mtdcr (ebccfgd, CONFIG_PORT_AP); + mtdcr (ebccfga, pb7cr); + mtdcr (ebccfgd, CONFIG_PORT_CR); + + memclk = get_bus_freq (tmemclk); + tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ + +#ifdef SDRAM_DEBUG + (void) get_clocks (); + gd->baudrate = 9600; + serial_init (); + serial_puts ("\nstart SDRAM Setup\n"); +#endif + + /* Read Serial Presence Detect Information */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + dataout[0] = 0; + for (i = 0; i < 128; i++) + datain[i] = 127; + i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); +#ifdef SDRAM_DEBUG + serial_puts ("\ni2c_read returns "); + write_hex (i); + serial_puts ("\n"); +#endif + +#ifdef SDRAM_DEBUG + for (i = 0; i < 128; i++) { + write_hex (datain[i]); + serial_puts (" "); + if (((i + 1) % 16) == 0) + serial_puts ("\n"); + } + serial_puts ("\n"); +#endif + spd_chksum = 0; + for (i = 0; i < 63; i++) { + spd_chksum += datain[i]; + } /* endfor */ + if (datain[63] != spd_chksum) { +#ifdef SDRAM_DEBUG + serial_puts ("SPD chksum: 0x"); + write_hex (datain[63]); + serial_puts (" != calc. chksum: 0x"); + write_hex (spd_chksum); + serial_puts ("\n"); +#endif + SDRAM_err ("SPD checksum Error"); + } + /* SPD seems to be ok, use it */ + + /* get SPD version */ + spd_version = datain[62]; + + /* do some sanity checks on the kind of RAM */ + if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */ + (datain[2] != 0x04) || /* if not SDRAM */ + (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ + (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ + (datain[126] == 0x66)) /* or a 66Mhz modules */ + SDRAM_err ("unsupported SDRAM"); +#ifdef SDRAM_DEBUG + serial_puts ("SDRAM sanity ok\n"); +#endif + + /* get number of rows/cols/banks out of byte 3+4+5 */ + rows = datain[3]; + cols = datain[4]; + banks = datain[5]; + + /* get number of SDRAM banks out of byte 17 and + supported CAS latencies out of byte 18 */ + sdram_banks = datain[17]; + supported_cal = datain[18] & ~0x81; + + while (t->mode != 0) { + if ((t->row == rows) && (t->col == cols) + && (t->bank == sdram_banks)) + break; + t++; + } /* endwhile */ + +#ifdef SDRAM_DEBUG + serial_puts ("rows: "); + write_hex (rows); + serial_puts (" cols: "); + write_hex (cols); + serial_puts (" banks: "); + write_hex (banks); + serial_puts (" mode: "); + write_hex (t->mode); + serial_puts ("\n"); +#endif + if (t->mode == 0) + SDRAM_err ("unsupported SDRAM"); + /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */ +#ifdef SDRAM_DEBUG + serial_puts ("tRP: "); + write_hex (datain[27]); + serial_puts ("\ntRCD: "); + write_hex (datain[29]); + serial_puts ("\ntRAS: "); + write_hex (datain[30]); + serial_puts ("\n"); +#endif + + trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk; + trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk; + tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk; + density = datain[31]; + + /* trc_clocks is sum of trp_clocks + tras_clocks */ + trc_clocks = trp_clocks + tras_clocks; + /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ + tctp_clocks = + ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + + (tmemclk - 1)) / tmemclk; + +#ifdef SDRAM_DEBUG + serial_puts ("c_RP: "); + write_hex (trp_clocks); + serial_puts ("\nc_RCD: "); + write_hex (trcd_clocks); + serial_puts ("\nc_RAS: "); + write_hex (tras_clocks); + serial_puts ("\nc_RC: (RP+RAS): "); + write_hex (trc_clocks); + serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): "); + write_hex (tctp_clocks); + serial_puts ("\nt_CTP: RAS - RCD: "); + write_hex ((unsigned + char) ((NSto10PS (datain[30]) - + NSto10PS (datain[29])) >> 8)); + write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29]))); + serial_puts ("\ntmemclk: "); + write_hex ((unsigned char) (tmemclk >> 8)); + write_hex ((unsigned char) (tmemclk)); + serial_puts ("\n"); +#endif + + + cal_val = 255; + for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) { + /* is this CAS latency supported ? */ + if ((supported_cal >> i) & 0x01) { + buf[0] = datain[cal_indextable[cal_index]]; + if (cal_index < 2) { + if (NS10to10PS (buf[0], spd_version) <= tmemclk) + cal_val = i; + } else { + /* SPD bytes 25+26 have another format */ + if (NS4to10PS (buf[0], spd_version) <= tmemclk) + cal_val = i; + } /* endif */ + cal_index++; + } /* endif */ + } /* endfor */ +#ifdef SDRAM_DEBUG + serial_puts ("CAL: "); + write_hex (cal_val + 1); + serial_puts ("\n"); +#endif + + if (cal_val == 255) + SDRAM_err ("unsupported SDRAM"); + + /* get SDRAM timing register */ + mtdcr (memcfga, mem_sdtr1); + tmp = mfdcr (memcfgd) & ~0x018FC01F; + /* insert CASL value */ +/* tmp |= ((unsigned long)cal_val) << 23; */ + tmp |= ((unsigned long) cal_val) << 23; + /* insert PTA value */ + tmp |= ((unsigned long) (trp_clocks - 1)) << 18; + /* insert CTP value */ +/* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */ + tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16; + /* insert LDF (always 01) */ + tmp |= ((unsigned long) 0x01) << 14; + /* insert RFTA value */ + tmp |= ((unsigned long) (trc_clocks - 4)) << 2; + /* insert RCD value */ + tmp |= ((unsigned long) (trcd_clocks - 1)) << 0; + +#ifdef SDRAM_DEBUG + serial_puts ("sdtr: "); + write_4hex (tmp); + serial_puts ("\n"); +#endif + + /* write SDRAM timing register */ + mtdcr (memcfga, mem_sdtr1); + mtdcr (memcfgd, tmp); + baseaddr = CFG_SDRAM_BASE; + bank_size = (((unsigned long) density) << 22) / 2; + /* insert AM value */ + tmp = ((unsigned long) t->mode - 1) << 13; + /* insert SZ value; */ + switch (bank_size) { + case 0x00400000: + tmp |= ((unsigned long) 0x00) << 17; + break; + case 0x00800000: + tmp |= ((unsigned long) 0x01) << 17; + break; + case 0x01000000: + tmp |= ((unsigned long) 0x02) << 17; + break; + case 0x02000000: + tmp |= ((unsigned long) 0x03) << 17; + break; + case 0x04000000: + tmp |= ((unsigned long) 0x04) << 17; + break; + case 0x08000000: + tmp |= ((unsigned long) 0x05) << 17; + break; + case 0x10000000: + tmp |= ((unsigned long) 0x06) << 17; + break; + default: + SDRAM_err ("unsupported SDRAM"); + } /* endswitch */ + /* get SDRAM bank 0 register */ + mtdcr (memcfga, mem_mb0cf); + bank = mfdcr (memcfgd) & ~0xFFCEE001; + bank |= (baseaddr | tmp | 0x01); +#ifdef SDRAM_DEBUG + serial_puts ("bank0: baseaddr: "); + write_4hex (baseaddr); + serial_puts (" banksize: "); + write_4hex (bank_size); + serial_puts (" mb0cf: "); + write_4hex (bank); + serial_puts ("\n"); +#endif + baseaddr += bank_size; + sdram_size += bank_size; + + /* write SDRAM bank 0 register */ + mtdcr (memcfga, mem_mb0cf); + mtdcr (memcfgd, bank); + + /* get SDRAM bank 1 register */ + mtdcr (memcfga, mem_mb1cf); + bank = mfdcr (memcfgd) & ~0xFFCEE001; + sdram_size = 0; + +#ifdef SDRAM_DEBUG + serial_puts ("bank1: baseaddr: "); + write_4hex (baseaddr); + serial_puts (" banksize: "); + write_4hex (bank_size); +#endif + if (banks == 2) { + bank |= (baseaddr | tmp | 0x01); + baseaddr += bank_size; + sdram_size += bank_size; + } /* endif */ +#ifdef SDRAM_DEBUG + serial_puts (" mb1cf: "); + write_4hex (bank); + serial_puts ("\n"); +#endif + /* write SDRAM bank 1 register */ + mtdcr (memcfga, mem_mb1cf); + mtdcr (memcfgd, bank); + + /* get SDRAM bank 2 register */ + mtdcr (memcfga, mem_mb2cf); + bank = mfdcr (memcfgd) & ~0xFFCEE001; + + bank |= (baseaddr | tmp | 0x01); + +#ifdef SDRAM_DEBUG + serial_puts ("bank2: baseaddr: "); + write_4hex (baseaddr); + serial_puts (" banksize: "); + write_4hex (bank_size); + serial_puts (" mb2cf: "); + write_4hex (bank); + serial_puts ("\n"); +#endif + + baseaddr += bank_size; + sdram_size += bank_size; + + /* write SDRAM bank 2 register */ + mtdcr (memcfga, mem_mb2cf); + mtdcr (memcfgd, bank); + + /* get SDRAM bank 3 register */ + mtdcr (memcfga, mem_mb3cf); + bank = mfdcr (memcfgd) & ~0xFFCEE001; + +#ifdef SDRAM_DEBUG + serial_puts ("bank3: baseaddr: "); + write_4hex (baseaddr); + serial_puts (" banksize: "); + write_4hex (bank_size); +#endif + + if (banks == 2) { + bank |= (baseaddr | tmp | 0x01); + baseaddr += bank_size; + sdram_size += bank_size; + } + /* endif */ +#ifdef SDRAM_DEBUG + serial_puts (" mb3cf: "); + write_4hex (bank); + serial_puts ("\n"); +#endif + + /* write SDRAM bank 3 register */ + mtdcr (memcfga, mem_mb3cf); + mtdcr (memcfgd, bank); + + + /* get SDRAM refresh interval register */ + mtdcr (memcfga, mem_rtr); + tmp = mfdcr (memcfgd) & ~0x3FF80000; + + if (tmemclk < NSto10PS (16)) + tmp |= 0x05F00000; + else + tmp |= 0x03F80000; + + /* write SDRAM refresh interval register */ + mtdcr (memcfga, mem_rtr); + mtdcr (memcfgd, tmp); + + /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ + mtdcr (memcfga, mem_mcopt1); + tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000; + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, tmp); + + + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the PIP405 board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive + | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive + | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive + | Note for PIP405 board: + | An interrupt taken for the SouthBridge (IRQ 25) indicates that + | the Interrupt Controller in the South Bridge has caused the + | interrupt. The IC must be read to determine which device + | caused the interrupt. + | + +-------------------------------------------------------------------------*/ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ + mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char s[50]; + unsigned char bc; + int i; + backup_t *b = (backup_t *) s; + + puts ("Board: "); + + i = getenv_r ("serial#", (char *)s, 32); + if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) { + get_backup_values (b); + if (strncmp (b->signature, "MPL\0", 4) != 0) { + puts ("### No HW ID - assuming PIP405"); + } else { + b->serial_name[6] = 0; + printf ("%s SN: %s", b->serial_name, + &b->serial_name[7]); + } + } else { + s[6] = 0; + printf ("%s SN: %s", s, &s[7]); + } + bc = in8 (CONFIG_PORT_ADDR); + printf (" Boot Config: 0x%x\n", bc); + return (0); +} + + +/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- */ +/* + initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of + the necessary info for SDRAM controller configuration +*/ +/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- */ +static int test_dram (unsigned long ramsize); + +long int initdram (int board_type) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long bank_reg[4], tmp, bank_size; + int i, ds; + unsigned long TotalSize; + + ds = 0; + /* since the DRAM controller is allready set up, + * calculate the size with the bank registers + */ + mtdcr (memcfga, mem_mb0cf); + bank_reg[0] = mfdcr (memcfgd); + mtdcr (memcfga, mem_mb1cf); + bank_reg[1] = mfdcr (memcfgd); + mtdcr (memcfga, mem_mb2cf); + bank_reg[2] = mfdcr (memcfgd); + mtdcr (memcfga, mem_mb3cf); + bank_reg[3] = mfdcr (memcfgd); + TotalSize = 0; + for (i = 0; i < 4; i++) { + if ((bank_reg[i] & 0x1) == 0x1) { + tmp = (bank_reg[i] >> 17) & 0x7; + bank_size = 4 << tmp; + TotalSize += bank_size; + } else + ds = 1; + } + if (ds == 1) + printf ("single-sided DIMM "); + else + printf ("double-sided DIMM "); + test_dram (TotalSize * 1024 * 1024); + /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */ + (void) get_clocks(); + if (gd->cpu_clk > 220000000) + TotalSize /= 2; + return (TotalSize * 1024 * 1024); +} + +/* ------------------------------------------------------------------------- */ + + +static int test_dram (unsigned long ramsize) +{ + /* not yet implemented */ + return (1); +} + + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* adjust flash start and size as well as the offset */ + gd->bd->bi_flashstart=0-flash_info[0].size; + gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; + gd->bd->bi_flashoffset=0; + + /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ + if (mfdcr(strap) & PSR_ROM_LOC) + mtspr(ccr0, (mfspr(ccr0) & ~0x80)); + + return (0); +} + +/*************************************************************************** + * some helping routines + */ + +int overwrite_console (void) +{ + return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */ +} + + +extern int isa_init (void); + + +void print_pip405_rev (void) +{ + unsigned char part, vers, cfg; + + part = in8 (PLD_PART_REG); + vers = in8 (PLD_VERS_REG); + cfg = in8 (PLD_BOARD_CFG_REG); + printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n", + 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf, + vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf); +} + +extern void check_env(void); + + +int last_stage_init (void) +{ + print_pip405_rev (); + isa_init (); + show_stdio_dev (); + check_env(); + return 0; +} + +/************************************************************************ +* Print PIP405 Info +************************************************************************/ +void print_pip405_info (void) +{ + unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr, + compwr, nicvga, scsirst; + + part = in8 (PLD_PART_REG); + vers = in8 (PLD_VERS_REG); + cfg = in8 (PLD_BOARD_CFG_REG); + ledu = in8 (PLD_LED_USER_REG); + sysman = in8 (PLD_SYS_MAN_REG); + flashcom = in8 (PLD_FLASH_COM_REG); + can = in8 (PLD_CAN_REG); + serpwr = in8 (PLD_SER_PWR_REG); + compwr = in8 (PLD_COM_PWR_REG); + nicvga = in8 (PLD_NIC_VGA_REG); + scsirst = in8 (PLD_SCSI_RST_REG); + printf ("PLD Part %d version %d\n", + part & 0xf, vers & 0xf); + printf ("PLD Part %d version %d\n", + (part >> 4) & 0xf, (vers >> 4) & 0xf); + printf ("Board Revision %c\n", (cfg & 0xf) + 'A'); + printf ("Population Options %d %d %d %d\n", + (cfg >> 4) & 0x1, (cfg >> 5) & 0x1, + (cfg >> 6) & 0x1, (cfg >> 7) & 0x1); + printf ("User LED0 %s User LED1 %s\n", + ((ledu & 0x1) == 0x1) ? "on" : "off", + ((ledu & 0x2) == 0x2) ? "on" : "off"); + printf ("Additionally Options %d %d\n", + (ledu >> 2) & 0x1, (ledu >> 3) & 0x1); + printf ("User Config Switch %d %d %d %d\n", + (ledu >> 4) & 0x1, (ledu >> 5) & 0x1, + (ledu >> 6) & 0x1, (ledu >> 7) & 0x1); + switch (sysman & 0x3) { + case 0: + printf ("PCI Clocks are running\n"); + break; + case 1: + printf ("PCI Clocks are stopped in POS State\n"); + break; + case 2: + printf ("PCI Clocks are stopped when PCI_STP# is asserted\n"); + break; + case 3: + printf ("PCI Clocks are stopped\n"); + break; + } + switch ((sysman >> 2) & 0x3) { + case 0: + printf ("Main Clocks are running\n"); + break; + case 1: + printf ("Main Clocks are stopped in POS State\n"); + break; + case 2: + case 3: + printf ("PCI Clocks are stopped\n"); + break; + } + printf ("INIT asserts %sINT2# (SMI)\n", + ((sysman & 0x10) == 0x10) ? "" : "not "); + printf ("INIT asserts %sINT1# (NMI)\n", + ((sysman & 0x20) == 0x20) ? "" : "not "); + printf ("INIT occured %d\n", (sysman >> 6) & 0x1); + printf ("SER1 is routed to %s\n", + ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232"); + printf ("COM2 is routed to %s\n", + ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232"); + printf ("RS485 is configured as %s duplex\n", + ((flashcom & 0x4) == 0x4) ? "full" : "half"); + printf ("RS485 is connected to %s\n", + ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2"); + printf ("SER1 uses handshakes %s\n", + ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS"); + printf ("Bootflash is %swriteprotected\n", + ((flashcom & 0x20) == 0x20) ? "not " : ""); + printf ("Bootflash VPP is %s\n", + ((flashcom & 0x40) == 0x40) ? "on" : "off"); + printf ("Bootsector is %swriteprotected\n", + ((flashcom & 0x80) == 0x80) ? "not " : ""); + switch ((can) & 0x3) { + case 0: + printf ("CAN Controller is on address 0x1000..0x10FF\n"); + break; + case 1: + printf ("CAN Controller is on address 0x8000..0x80FF\n"); + break; + case 2: + printf ("CAN Controller is on address 0xE000..0xE0FF\n"); + break; + case 3: + printf ("CAN Controller is disabled\n"); + break; + } + switch ((can >> 2) & 0x3) { + case 0: + printf ("CAN Controller Reset is ISA Reset\n"); + break; + case 1: + printf ("CAN Controller Reset is ISA Reset and POS State\n"); + break; + case 2: + case 3: + printf ("CAN Controller is in reset\n"); + break; + } + if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13)) + printf ("CAN Interrupt is disabled\n"); + else + printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf); + switch (serpwr & 0x3) { + case 0: + printf ("SER0 Drivers are enabled\n"); + break; + case 1: + printf ("SER0 Drivers are disabled in the POS state\n"); + break; + case 2: + case 3: + printf ("SER0 Drivers are disabled\n"); + break; + } + switch ((serpwr >> 2) & 0x3) { + case 0: + printf ("SER1 Drivers are enabled\n"); + break; + case 1: + printf ("SER1 Drivers are disabled in the POS state\n"); + break; + case 2: + case 3: + printf ("SER1 Drivers are disabled\n"); + break; + } + switch (compwr & 0x3) { + case 0: + printf ("COM1 Drivers are enabled\n"); + break; + case 1: + printf ("COM1 Drivers are disabled in the POS state\n"); + break; + case 2: + case 3: + printf ("COM1 Drivers are disabled\n"); + break; + } + switch ((compwr >> 2) & 0x3) { + case 0: + printf ("COM2 Drivers are enabled\n"); + break; + case 1: + printf ("COM2 Drivers are disabled in the POS state\n"); + break; + case 2: + case 3: + printf ("COM2 Drivers are disabled\n"); + break; + } + switch ((nicvga) & 0x3) { + case 0: + printf ("PHY is running\n"); + break; + case 1: + printf ("PHY is in Power save mode in POS state\n"); + break; + case 2: + case 3: + printf ("PHY is in Power save mode\n"); + break; + } + switch ((nicvga >> 2) & 0x3) { + case 0: + printf ("VGA is running\n"); + break; + case 1: + printf ("VGA is in Power save mode in POS state\n"); + break; + case 2: + case 3: + printf ("VGA is in Power save mode\n"); + break; + } + printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not "); + printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not "); + printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1, + (nicvga >> 7) & 0x1); + switch ((scsirst) & 0x3) { + case 0: + printf ("SCSI Controller is running\n"); + break; + case 1: + printf ("SCSI Controller is in Power save mode in POS state\n"); + break; + case 2: + case 3: + printf ("SCSI Controller is in Power save mode\n"); + break; + } + printf ("SCSI termination is %s\n", + ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled"); + printf ("SCSI Controller is %sreseted\n", + ((scsirst & 0x10) == 0x10) ? "" : "not "); + printf ("IDE disks are %sreseted\n", + ((scsirst & 0x20) == 0x20) ? "" : "not "); + printf ("ISA Bus is %sreseted\n", + ((scsirst & 0x40) == 0x40) ? "" : "not "); + printf ("Super IO is %sreseted\n", + ((scsirst & 0x80) == 0x80) ? "" : "not "); +} + +void user_led0 (unsigned char on) +{ + if (on == TRUE) + out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1)); + else + out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe)); +} + +void user_led1 (unsigned char on) +{ + if (on == TRUE) + out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2)); + else + out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd)); +} + +void ide_set_reset (int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + unsigned char resreg; + + resreg = in8 (PLD_SCSI_RST_REG); + if (idereset == 1) + resreg |= 0x20; + else { + udelay(10000); + resreg &= 0xdf; + } + out8 (PLD_SCSI_RST_REG, resreg); +} diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h new file mode 100644 index 0000000..b41c5bb --- /dev/null +++ b/board/mpl/pip405/pip405.h @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + /**************************************************************************** + * Global routines used for PIP405 + *****************************************************************************/ + +#ifndef __ASSEMBLY__ + +extern int mem_test(unsigned long start, unsigned long ramsize,int mode); + +void print_pip405_info(void); + +void user_led0(unsigned char on); +void user_led1(unsigned char on); + + +#define PLD_BASE_ADDRESS CFG_ISA_IO_BASE_ADDRESS + 0x800 +#define PLD_PART_REG PLD_BASE_ADDRESS + 0 +#define PLD_VERS_REG PLD_BASE_ADDRESS + 1 +#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2 +#define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3 +#define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4 +#define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5 +#define PLD_CAN_REG PLD_BASE_ADDRESS + 6 +#define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7 +#define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8 +#define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9 +#define PLD_SCSI_RST_REG PLD_BASE_ADDRESS + 0xA + +#define PIIX4_VENDOR_ID 0x8086 +#define PIIX4_IDE_DEV_ID 0x7111 + +#endif + +/* timings */ + +/* CS Config register (CS7) */ +#define CONFIG_PORT_BME 0 /* Burst disable */ +#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ +#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */ +#define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */ +#define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */ +#define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */ +#define CONFIG_PORT_RE 0 /* Ready disabled */ +#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */ +#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */ +#define CONFIG_PORT_PEN 0 /* Parity disable */ +#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \ + (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define CONFIG_PORT_BS 0 /* 1 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define CONFIG_PORT_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define CONFIG_PORT_BW 0 /* 16Bit */ +#define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13)) + +/* Flash CS0 or CS 1 */ +/* 0x7F8FFE80 slowest timing at all... */ +#define FLASH_BME_B 1 /* Burst enable */ +#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ +#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ +#define FLASH_BME 0 /* Burst disable */ +#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ +#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define FLASH_OEN 1 /* Cycles from CS low to OE low */ +#define FLASH_WBN 1 /* Cycles from CS low to WE low */ +#define FLASH_WBF 1 /* Cycles from WE high to CS high */ +#define FLASH_TH 2 /* Number of hold cycles after transfer */ +#define FLASH_RE 0 /* Ready disabled */ +#define FLASH_SOR 1 /* Sample on Ready disabled */ +#define FLASH_BEM 0 /* Byte Write only active on Write cycles */ +#define FLASH_PEN 0 /* Parity disable */ +/* Access Parameter Register for non Boot */ +#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ + (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) +/* Access Parameter Register for Boot */ +#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ + (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define FLASH_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define FLASH_BW 1 /* 16Bit */ +/* CR register for Boot */ +#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) +/* CR register for non Boot */ +#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) + +/* MPS CS1 or CS0 */ +/* Boot CS: */ +#define MPS_BME_B 1 /* Burst enable */ +#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ +#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ +#define MPS_BME 0 /* Burst disable */ +#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ +#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define MPS_OEN 1 /* Cycles from CS low to OE low */ +#define MPS_WBN 1 /* Cycles from CS low to WE low */ +#define MPS_WBF 1 /* Cycles from WE high to CS high */ +#define MPS_TH 2 /* Number of hold cycles after transfer */ +#define MPS_RE 0 /* Ready disabled */ +#define MPS_SOR 1 /* Sample on Ready disabled */ +#define MPS_BEM 0 /* Byte Write only active on Write cycles */ +#define MPS_PEN 0 /* Parity disable */ +/* Access Parameter Register for non Boot */ +#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ + (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) +/* Access Parameter Register for Boot */ +#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ + (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define MPS_BS 2 /* 4 MByte */ +#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define MPS_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define MPS_BW 0 /* 8Bit */ +/* CR register for Boot */ +#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) +/* CR register for non Boot */ +#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds new file mode 100644 index 0000000..11819a4 --- /dev/null +++ b/board/mpl/pip405/u-boot.lds @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/mpl/pip405/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug new file mode 100644 index 0000000..1608f8c --- /dev/null +++ b/board/mpl/pip405/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile new file mode 100644 index 0000000..304c965 --- /dev/null +++ b/board/mpl/vcma9/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := vcma9.o flash.o cmd_vcma9.o +OBJS += ../common/common_util.o ../common/memtst.o + +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c new file mode 100644 index 0000000..44b4112 --- /dev/null +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2002 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * adapted for VCMA9 + * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include "vcma9.h" +#include "../common/common_util.h" + +#if defined(CONFIG_DRIVER_CS8900) +#include <../drivers/cs8900.h> + +static uchar cs8900_chksum(ushort data) +{ + return((data >> 8) & 0x00FF) + (data & 0x00FF); +} + +#endif + +extern void print_vcma9_info(void); +extern int vcma9_cantest(int); +extern int vcma9_nandtest(void); +extern int vcma9_nanderase(void); +extern int vcma9_nandread(ulong); +extern int vcma9_nandwrite(ulong); +extern int vcma9_dactest(int); +extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* ------------------------------------------------------------------------- */ + +int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (strcmp(argv[1], "info") == 0) + { + print_vcma9_info(); + return 0; + } +#if defined(CONFIG_DRIVER_CS8900) + if (strcmp(argv[1], "cs8900") == 0) { + if (strcmp(argv[2], "read") == 0) { + uchar addr; ushort data; + + addr = simple_strtoul(argv[3], NULL, 16); + cs8900_e2prom_read(addr, &data); + printf("0x%2.2X: 0x%4.4X\n", addr, data); + } else if (strcmp(argv[2], "write") == 0) { + uchar addr; ushort data; + + addr = simple_strtoul(argv[3], NULL, 16); + data = simple_strtoul(argv[4], NULL, 16); + cs8900_e2prom_write(addr, data); + } else if (strcmp(argv[2], "setaddr") == 0) { + uchar addr, i, csum; ushort data; + + /* check for valid ethaddr */ + for (i = 0; i < 6; i++) + if (gd->bd->bi_enetaddr[i] != 0) + break; + + if (i < 6) { + addr = 1; + data = 0x2158; + cs8900_e2prom_write(addr, data); + csum = cs8900_chksum(data); + addr++; + for (i = 0; i < 6; i+=2) { + data = gd->bd->bi_enetaddr[i+1] << 8 | + gd->bd->bi_enetaddr[i]; + cs8900_e2prom_write(addr, data); + csum += cs8900_chksum(data); + addr++; + } + /* calculate header link byte */ + data = 0xA100 | (addr * 2); + cs8900_e2prom_write(0, data); + csum += cs8900_chksum(data); + /* write checksum word */ + cs8900_e2prom_write(addr, (0 - csum) << 8); + } else { + puts("\nplease defined 'ethaddr'\n"); + } + } else if (strcmp(argv[2], "dump") == 0) { + uchar addr = 0, endaddr, csum; ushort data; + + puts("Dump of CS8900 config device: "); + cs8900_e2prom_read(addr, &data); + if ((data & 0xE000) == 0xA000) { + endaddr = (data & 0x00FF) / 2; + csum = cs8900_chksum(data); + for (addr = 1; addr <= endaddr; addr++) { + cs8900_e2prom_read(addr, &data); + printf("\n0x%2.2X: 0x%4.4X", addr, data); + csum += cs8900_chksum(data); + } + printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong"); + } else { + puts("no valid config found"); + } + puts("\n"); + } + + return 0; + } +#endif +#if 0 + if (strcmp(argv[1], "cantest") == 0) { + if (argc >= 3) + vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1); + else + vcma9_cantest(0); + return 0; + } + if (strcmp(argv[1], "nandtest") == 0) { + vcma9_nandtest(); + return 0; + } + if (strcmp(argv[1], "nanderase") == 0) { + vcma9_nanderase(); + return 0; + } + if (strcmp(argv[1], "nandread") == 0) { + ulong offset = 0; + + if (argc >= 3) + offset = simple_strtoul(argv[2], NULL, 16); + + vcma9_nandread(offset); + return 0; + } + if (strcmp(argv[1], "nandwrite") == 0) { + ulong offset = 0; + + if (argc >= 3) + offset = simple_strtoul(argv[2], NULL, 16); + + vcma9_nandwrite(offset); + return 0; + } + if (strcmp(argv[1], "dactest") == 0) { + if (argc >= 3) + vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1); + else + vcma9_dactest(0); + return 0; + } +#endif + + return (do_mplcommon(cmdtp, flag, argc, argv)); +} + +U_BOOT_CMD( + vcma9, 6, 1, do_vcma9, + "vcma9 - VCMA9 specific commands\n", + "flash mem [SrcAddr]\n - updates U-Boot with image in memory\n" +); diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk new file mode 100644 index 0000000..1fa09c9 --- /dev/null +++ b/board/mpl/vcma9/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2002, 2003 +# David Mueller, ELSOFT AG, +# +# MPL VCMA9 board with S3C2410X (ARM920T) cpu +# +# see http://www.mpl.ch/ for more information about the MPL VCMA9 +# + +# +# MPL VCMA9 has 1 bank of minimal 16 MB DRAM +# from 0x30000000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3040'0000 +# +# we load ourself to 33F8'0000 +# +# download area is 3080'0000 +# + + +#TEXT_BASE = 0x30F80000 +TEXT_BASE = 0x33F80000 diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c new file mode 100644 index 0000000..ccfe176 --- /dev/null +++ b/board/mpl/vcma9/flash.c @@ -0,0 +1,432 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +ulong myflush (void); + + +#define FLASH_BANK_SIZE PHYS_FLASH_SIZE +#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +#define CMD_READ_ARRAY 0x000000F0 +#define CMD_UNLOCK1 0x000000AA +#define CMD_UNLOCK2 0x00000055 +#define CMD_ERASE_SETUP 0x00000080 +#define CMD_ERASE_CONFIRM 0x00000030 +#define CMD_PROGRAM 0x000000A0 +#define CMD_UNLOCK_BYPASS 0x00000020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) + +#define BIT_ERASE_DONE 0x00000080 +#define BIT_RDY_MASK 0x00000080 +#define BIT_PROGRAM_ERROR 0x00000020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = +#if defined(CONFIG_AMD_LV400) + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV400B & FLASH_TYPEMASK); +#elif defined(CONFIG_AMD_LV800) + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV800B & FLASH_TYPEMASK); +#else +#error "Unknown flash configured" +#endif + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j <= 3) { + /* 1st one is 16 KB */ + if (j == 0) { + flash_info[i].start[j] = + flashbase + 0; + } + + /* 2nd and 3rd are both 8 KB */ + if ((j == 1) || (j == 2)) { + flash_info[i].start[j] = + flashbase + 0x4000 + (j - + 1) * + 0x2000; + } + + /* 4th 32 KB */ + if (j == 3) { + flash_info[i].start[j] = + flashbase + 0x8000; + } + } else { + flash_info[i].start[j] = + flashbase + (j - 3) * MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + puts ("AMD: "); + break; + default: + puts ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV400B & FLASH_TYPEMASK): + puts ("1x Amd29LV400BB (4Mbit)\n"); + break; + case (AMD_ID_LV800B & FLASH_TYPEMASK): + puts ("1x Amd29LV800BB (8Mbit)\n"); + break; + default: + puts ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + puts (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + puts ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + puts ("\n"); + +Done: ; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ushort result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip = TMO; + break; + } + + if (!chip + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip = READY; + + if (!chip + && (result & 0xFFFF) & BIT_PROGRAM_ERROR) + chip = ERR; + + } while (!chip); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + puts ("ok.\n"); + } else { /* it was protected */ + + puts ("protected!\n"); + } + } + + if (ctrlc ()) + puts ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest; + ushort result; + int rc = ERR_OK; + int cflag, iflag; + int chip; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + chip = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + chip = ERR | TMO; + break; + } + if (!chip && ((result & 0x80) == (data & 0x80))) + chip = READY; + + if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { + result = *addr; + + if ((result & 0x80) == (data & 0x80)) + chip = READY; + else + chip = ERR; + } + + } while (!chip); + + *addr = CMD_READ_ARRAY; + + if (chip == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + int l; + int i, rc; + ushort data; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_hword (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_hword (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_hword (info, wp, data); +} diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S new file mode 100644 index 0000000..a023353 --- /dev/null +++ b/board/mpl/vcma9/lowlevel_init.S @@ -0,0 +1,212 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +#define BWSCON 0x48000000 +#define PLD_BASE 0x2C000000 +#define SDRAM_REG 0x2C000106 + +/* BWSCON */ +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +/* BANKSIZE */ +#define BURST_EN (0x1<<7) + +#define B1_BWSCON (DW16) +#define B2_BWSCON (DW32) +#define B3_BWSCON (DW32) +#define B4_BWSCON (DW16 + WAIT + UBLB) +#define B5_BWSCON (DW8 + UBLB) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) + +/* BANK0CON */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x1 /* 1clk */ +/*#define B0_Tcos 0x0 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +/*#define B0_Tacc 0x5 8clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 /* page mode is not used */ +#define B0_PMC 0x0 /* page mode disabled */ + +/* BANK1CON */ +#define B1_Tacs 0x0 /* 0clk */ +#define B1_Tcos 0x1 /* 1clk */ +/*#define B1_Tcos 0x0 0clk */ +#define B1_Tacc 0x7 /* 14clk */ +/*#define B1_Tacc 0x5 8clk */ +#define B1_Tcoh 0x0 /* 0clk */ +#define B1_Tah 0x0 /* 0clk */ +#define B1_Tacp 0x0 /* page mode is not used */ +#define B1_PMC 0x0 /* page mode disabled */ + +#define B2_Tacs 0x3 /* 4clk */ +#define B2_Tcos 0x3 /* 4clk */ +#define B2_Tacc 0x7 /* 14clk */ +#define B2_Tcoh 0x3 /* 4clk */ +#define B2_Tah 0x3 /* 4clk */ +#define B2_Tacp 0x0 /* page mode is not used */ +#define B2_PMC 0x0 /* page mode disabled */ + +#define B3_Tacs 0x3 /* 4clk */ +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 /* 14clk */ +#define B3_Tcoh 0x3 /* 4clk */ +#define B3_Tah 0x3 /* 4clk */ +#define B3_Tacp 0x0 /* page mode is not used */ +#define B3_PMC 0x0 /* page mode disabled */ + +#define B4_Tacs 0x3 /* 4clk */ +#define B4_Tcos 0x1 /* 1clk */ +#define B4_Tacc 0x7 /* 14clk */ +#define B4_Tcoh 0x1 /* 1clk */ +#define B4_Tah 0x0 /* 0clk */ +#define B4_Tacp 0x0 /* page mode is not used */ +#define B4_PMC 0x0 /* page mode disabled */ + +#define B5_Tacs 0x0 /* 0clk */ +#define B5_Tcos 0x3 /* 4clk */ +#define B5_Tacc 0x5 /* 8clk */ +#define B5_Tcoh 0x2 /* 2clk */ +#define B5_Tah 0x1 /* 1clk */ +#define B5_Tacp 0x0 /* page mode is not used */ +#define B5_PMC 0x0 /* page mode disabled */ + +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 /* 3clk */ +#define B6_SCAN 0x2 /* 10bit */ + +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x2 /* 10bit */ + +/* REFRESH parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x0 /* 2clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x2 /* 3clk */ +#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +/**************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =CSDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #CSDATA_END-CSDATA +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* PLD access is now possible */ + /* r0 == SDRAMDATA */ + /* r1 == SDRAM controller regs */ + ldr r2, =PLD_BASE + ldrb r3, [r2, #SDRAM_REG-PLD_BASE] + mov r4, #SDRAMDATA1_END-SDRAMDATA + /* calculate start and end point */ + mla r0, r3, r4, r0 + add r2, r0, r4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +CSDATA: + .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) +CSDATA_END: + +SDRAMDATA: +/* 4Mx8x4 */ + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 +SDRAMDATA1_END: + +/* 8Mx8x4 (not implemented yet) */ + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + +/* 2Mx8x4 (not implemented yet) */ + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + +/* 4Mx8x2 (not implemented yet) */ + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 diff --git a/board/mpl/vcma9/u-boot.lds b/board/mpl/vcma9/u-boot.lds new file mode 100644 index 0000000..f4fbf96 --- /dev/null +++ b/board/mpl/vcma9/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c new file mode 100644 index 0000000..ffdba5d --- /dev/null +++ b/board/mpl/vcma9/vcma9.c @@ -0,0 +1,353 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "vcma9.h" +#include "../common/common_util.h" + +/* ------------------------------------------------------------------------- */ + +#define FCLK_SPEED 1 + +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ +#define M_MDIV 0xC3 +#define M_PDIV 0x4 +#define M_SDIV 0x1 +#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ +#define M_MDIV 0xA1 +#define M_PDIV 0x3 +#define M_SDIV 0x1 +#endif + +#define USB_CLOCK 1 + +#if USB_CLOCK==0 +#define U_M_MDIV 0xA1 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x1 +#elif USB_CLOCK==1 +#define U_M_MDIV 0x48 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x2 +#endif + +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->LOCKTIME = 0xFFFFFF; + + /* configure MPLL */ + clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (4000); + + /* configure UPLL */ + clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (8000); + + /* set up the I/O ports */ + gpio->GPACON = 0x007FFFFF; + gpio->GPBCON = 0x002AAAAA; + gpio->GPBUP = 0x000002BF; + gpio->GPCCON = 0xAAAAAAAA; + gpio->GPCUP = 0x0000FFFF; + gpio->GPDCON = 0xAAAAAAAA; + gpio->GPDUP = 0x0000FFFF; + gpio->GPECON = 0xAAAAAAAA; + gpio->GPEUP = 0x000037F7; + gpio->GPFCON = 0x00000000; + gpio->GPFUP = 0x00000000; + gpio->GPGCON = 0xFFEAFF5A; + gpio->GPGUP = 0x0000F0DC; + gpio->GPHCON = 0x0028AAAA; + gpio->GPHUP = 0x00000656; + + /* setup correct IRQ modes for NIC */ + gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */ + + /* select USB port 2 to be host or device (fix to host for now) */ + gpio->MISCCR |= 0x08; + + /* init serial */ + gd->baudrate = CONFIG_BAUDRATE; + gd->have_console = 1; + serial_init(); + + /* arch number of VCMA9-Board */ + gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + icache_enable(); + dcache_enable(); + + return 0; +} + +/* + * NAND flash initialization. + */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +extern ulong +nand_probe(ulong physadr); + + +static inline void NF_Reset(void) +{ + int i; + + NF_SetCE(NFCE_LOW); + NF_Cmd(0xFF); /* reset command */ + for(i = 0; i < 10; i++); /* tWB = 100ns. */ + NF_WaitRB(); /* wait 200~500us; */ + NF_SetCE(NFCE_HIGH); +} + + +static inline void NF_Init(void) +{ +#if 0 /* a little bit too optimistic */ +#define TACLS 0 +#define TWRPH0 3 +#define TWRPH1 0 +#else +#define TACLS 0 +#define TWRPH0 4 +#define TWRPH1 2 +#endif + + NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); + /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ + /* 1 1 1 1, 1 xxx, r xxx, r xxx */ + /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ + + NF_Reset(); +} + +void +nand_init(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + NF_Init(); +#ifdef DEBUG + printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); +#endif + printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); +} +#endif + +/* + * Get some Board/PLD Info + */ + +static u8 Get_PLD_ID(void) +{ + VCMA9_PLD * const pld = VCMA9_GetBase_PLD(); + + return(pld->ID); +} + +static u8 Get_PLD_BOARD(void) +{ + VCMA9_PLD * const pld = VCMA9_GetBase_PLD(); + + return(pld->BOARD); +} + +static u8 Get_PLD_SDRAM(void) +{ + VCMA9_PLD * const pld = VCMA9_GetBase_PLD(); + + return(pld->SDRAM); +} + +static u8 Get_PLD_Version(void) +{ + return((Get_PLD_ID() >> 4) & 0x0F); +} + +static u8 Get_PLD_Revision(void) +{ + return(Get_PLD_ID() & 0x0F); +} + +#if 0 /* not used */ +static int Get_Board_Config(void) +{ + u8 config = Get_PLD_BOARD() & 0x03; + + if (config == 3) + return 1; + else + return 0; +} +#endif + +static uchar Get_Board_PCB(void) +{ + return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); +} + +static u8 Get_SDRAM_ChipNr(void) +{ + switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { + case 0: return 4; + case 1: return 1; + case 2: return 2; + default: return 0; + } +} + +static ulong Get_SDRAM_ChipSize(void) +{ + switch (Get_PLD_SDRAM() & 0x0F) { + case 0: return 16 * (1024*1024); + case 1: return 32 * (1024*1024); + case 2: return 8 * (1024*1024); + case 3: return 8 * (1024*1024); + default: return 0; + } +} +static const char * Get_SDRAM_ChipGeom(void) +{ + switch (Get_PLD_SDRAM() & 0x0F) { + case 0: return "4Mx8x4"; + case 1: return "8Mx8x4"; + case 2: return "2Mx8x4"; + case 3: return "4Mx8x2"; + default: return "unknown"; + } +} + +static void Show_VCMA9_Info(char *board_name, char *serial) +{ + printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", + board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); + printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard(void) +{ + unsigned char s[50]; + int i; + backup_t *b = (backup_t *) s; + + i = getenv_r("serial#", s, 32); + if ((i < 0) || strncmp (s, "VCMA9", 5)) { + get_backup_values (b); + if (strncmp (b->signature, "MPL\0", 4) != 0) { + puts ("### No HW ID - assuming VCMA9"); + } else { + b->serial_name[5] = 0; + Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); + } + } else { + s[5] = 0; + Show_VCMA9_Info(s, &s[6]); + } + /*printf("\n");*/ + return(0); +} + + +extern void mem_test_reloc(void); + +int last_stage_init(void) +{ + mem_test_reloc(); + checkboard(); + show_stdio_dev(); + check_env(); + return 0; +} + +/*************************************************************************** + * some helping routines + */ +#if !CONFIG_USB_KEYBOARD +int overwrite_console(void) +{ + /* return TRUE if console should be overwritten */ + return 0; +} +#endif + +/************************************************************************ +* Print VCMA9 Info +************************************************************************/ +void print_vcma9_info(void) +{ + unsigned char s[50]; + int i; + + if ((i = getenv_r("serial#", s, 32)) < 0) { + puts ("### No HW ID - assuming VCMA9"); + printf("i %d", i*24); + } else { + s[5] = 0; + Show_VCMA9_Info(s, &s[6]); + } +} diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h new file mode 100644 index 0000000..c0167d5 --- /dev/null +++ b/board/mpl/vcma9/vcma9.h @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2002, 2003 + * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + /**************************************************************************** + * Global routines used for VCMA9 + *****************************************************************************/ + +#include + +extern int mem_test(unsigned long start, unsigned long ramsize,int mode); + +void print_vcma9_info(void); + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +typedef enum { + NFCE_LOW, + NFCE_HIGH +} NFCE_STATE; + +static inline void NF_Conf(u16 conf) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFCONF = conf; +} + +static inline void NF_Cmd(u8 cmd) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFCMD = cmd; +} + +static inline void NF_CmdW(u8 cmd) +{ + NF_Cmd(cmd); + udelay(1); +} + +static inline void NF_Addr(u8 addr) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFADDR = addr; +} + +static inline void NF_SetCE(NFCE_STATE s) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + switch (s) { + case NFCE_LOW: + nand->NFCONF &= ~(1<<11); + break; + + case NFCE_HIGH: + nand->NFCONF |= (1<<11); + break; + } +} + +static inline void NF_WaitRB(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + while (!(nand->NFSTAT & (1<<0))); +} + +static inline void NF_Write(u8 data) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFDATA = data; +} + +static inline u8 NF_Read(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + return(nand->NFDATA); +} + +static inline void NF_Init_ECC(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + nand->NFCONF |= (1<<12); +} + +static inline u32 NF_Read_ECC(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + return(nand->NFECC); +} + +#endif + +/* VCMA9 PLD regsiters */ +typedef struct { + S3C24X0_REG8 ID; + S3C24X0_REG8 NIC; + S3C24X0_REG8 CAN; + S3C24X0_REG8 MISC; + S3C24X0_REG8 GPCD; + S3C24X0_REG8 BOARD; + S3C24X0_REG8 SDRAM; +} /*__attribute__((__packed__))*/ VCMA9_PLD; + +#define VCMA9_PLD_BASE 0x2C000100 +static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void) +{ + return (VCMA9_PLD * const)VCMA9_PLD_BASE; +} diff --git a/board/musenki/Makefile b/board/musenki/Makefile new file mode 100644 index 0000000..24dc026 --- /dev/null +++ b/board/musenki/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/musenki/README b/board/musenki/README new file mode 100644 index 0000000..135a01a --- /dev/null +++ b/board/musenki/README @@ -0,0 +1,298 @@ +U-Boot for a Musenki M-3/M-1 board +--------------------------- + +Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each. + +In board's notation, bank 0 is the one at the address of 0xFF800000 +and bank 1 is the one at the address of 0xFF000000. + +On power-up the processor jumps to the address of 0xFFF00100, the last +megabyte of the bank 0 of flash. + +Thus, U-Boot is configured to reside in flash starting at the address of +0xFFF00000. The environment space is located in flash separately from +U-Boot, at the address of 0xFF800000. + +There is a Davicom 9102A on-board, but I don't have it working yet. + +U-Boot test results +-------------------- + +x.x Operation on all available serial consoles + +x.x.x CONFIG_CONS_INDEX 1 + + +U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) + +CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache +Board: MUSENKI Local Bus at 100 MHz +DRAM: 32 MB +FLASH: 4 MB +In: serial +Out: serial +Err: serial +Hit any key to stop autoboot: 0 +=> help +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootd - boot default, i.e., run 'bootcmd' +cmp - memory compare +coninfo - print console devices and informations +cp - memory copy +crc32 - checksum calculation +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +iminfo - print header information for application image +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loop - infinite loop on address range +md - memory display +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nm - memory modify (constant address) +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +tftpboot- boot image via network using TFTP protocol + and env variables ipaddr and serverip +version - print monitor version +? - alias for 'help' + + +x.x.x CONFIG_CONS_INDEX 2 + +**** NOT TESTED **** + +x.x Flash Driver Operation + + +Boot 1.1.1 (Nov 20 2001 - 15:55:32) + +CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache +Board: MUSENKI Local Bus at 100 MHz +DRAM: 32 MB +FLASH: 4 MB +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Hit any key to stop autoboot: 0 +=> +=> md ff800000 +ff800000: 46989bf8 626f6f74 636d643d 626f6f74 F...bootcmd=boot +ff800010: 6d204646 38323030 30300062 6f6f7464 m FF820000.bootd +ff800020: 656c6179 3d350062 61756472 6174653d elay=5.baudrate= +ff800030: 39363030 00636c6f 636b735f 696e5f6d 9600.clocks_in_m +ff800040: 687a3d31 00737464 696e3d73 65726961 hz=1.stdin=seria +ff800050: 6c007374 646f7574 3d736572 69616c00 l.stdout=serial. +ff800060: 73746465 72723d73 65726961 6c006970 stderr=serial.ip +ff800070: 61646472 3d313932 2e313638 2e302e34 addr=192.168.0.4 +ff800080: 32007365 72766572 69703d31 39322e31 2.serverip=192.1 +ff800090: 36382e30 2e380000 00000000 00000000 68.0.8.......... +ff8000a0: 00000000 00000000 00000000 00000000 ................ +ff8000b0: 00000000 00000000 00000000 00000000 ................ +ff8000c0: 00000000 00000000 00000000 00000000 ................ +ff8000d0: 00000000 00000000 00000000 00000000 ................ +ff8000e0: 00000000 00000000 00000000 00000000 ................ +ff8000f0: 00000000 00000000 00000000 00000000 ................ +=> protect off ff800000 ff81ffff +Un-Protected 1 sectors +=> erase ff800000 ff81ffff +Erase Flash from 0xff800000 to 0xff81ffff + done +Erased 1 sectors +=> md ff800000 +ff800000: ffffffff ffffffff ffffffff ffffffff ................ +ff800010: ffffffff ffffffff ffffffff ffffffff ................ +ff800020: ffffffff ffffffff ffffffff ffffffff ................ +ff800030: ffffffff ffffffff ffffffff ffffffff ................ +ff800040: ffffffff ffffffff ffffffff ffffffff ................ +ff800050: ffffffff ffffffff ffffffff ffffffff ................ +ff800060: ffffffff ffffffff ffffffff ffffffff ................ +ff800070: ffffffff ffffffff ffffffff ffffffff ................ +ff800080: ffffffff ffffffff ffffffff ffffffff ................ +ff800090: ffffffff ffffffff ffffffff ffffffff ................ +ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ + +x.x.x Information + + +U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) + +CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache +Board: MUSENKI Local Bus at 100 MHz +DRAM: 32 MB +FLASH: 4 MB +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Hit any key to stop autoboot: 0 +=> flinfo + +Bank # 1: Intel 28F320J3A (32Mbit = 128K x 32) + Size: 4 MB in 32 Sectors + Sector Start Addresses: + FF800000 (RO) FF820000 FF840000 FF860000 FF880000 + FF8A0000 FF8C0000 FF8E0000 FF900000 FF920000 + FF940000 FF960000 FF980000 FF9A0000 FF9C0000 + FF9E0000 FFA00000 FFA20000 FFA40000 FFA60000 + FFA80000 FFAA0000 FFAC0000 FFAE0000 FFB00000 + FFB20000 FFB40000 FFB60000 FFB80000 FFBA0000 + FFBC0000 FFBE0000 + +Bank # 2: missing or unknown FLASH type +=> + + +x.x.x Flash Programming + + +U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) + +CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache +Board: MUSENKI Local Bus at 100 MHz +DRAM: 32 MB +FLASH: 4 MB + +In: serial +Out: serial +Err: serial +Hit any key to stop autoboot: 0 +=> +=> +=> +=> protect off ff800000 ff81ffff +Un-Protected 1 sectors +=> cp 0 ff800000 20 +Copy to Flash... done +=> md ff800000 +ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc 7.3.3.3L3.1.3.5. +ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc 3...0.....3.1.6. +ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec 3.;.1.3.....3.3. +ff800030: 234c33ec 32cc22cc 33883bdc 534433cc #L3.2.".3.;.SD3. +ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc 3.0.1.2.3.3.3.3. +ff800050: 33cc13dc 334c534c b1c433d8 128c13cc 3...3LSL..3..... +ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc 7.6.3.3.......w. +ff800070: 314c0adc 139c30ed 33cc334c 33c833ec 1L....0.3.3L3.3. +ff800080: ffffffff ffffffff ffffffff ffffffff ................ +ff800090: ffffffff ffffffff ffffffff ffffffff ................ +ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ +ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ + + +x.x.x Storage of environment variables in flash + + +U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) + +CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache +Board: MUSENKI Local Bus at 100 MHz +DRAM: 32 MB +FLASH: 4 MB +In: serial +Out: serial +Err: serial +Hit any key to stop autoboot: 0 +=> printenv +bootcmd=bootm FF820000 +bootdelay=5 +baudrate=9600 +clocks_in_mhz=1 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 106/16380 bytes +=> setenv myvar 1234 +=> saveenv +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Saving Environment to Flash... +Protected 1 sectors +=> reset + + +U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) + +CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache +Board: MUSENKI Local Bus at 100 MHz +DRAM: 32 MB +FLASH: 4 MB +In: serial +Out: serial +Err: serial +Hit any key to stop autoboot: 0 +=> printenv +bootcmd=bootm FF820000 +bootdelay=5 +baudrate=9600 +clocks_in_mhz=1 +myvar=1234 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 117/16380 bytes + +x.x Image Download and run over serial port + + +U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) + +CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache +Board: MUSENKI Local Bus at 100 MHz +DRAM: 32 MB +FLASH: 4 MB +In: serial +Out: serial +Err: serial +Hit any key to stop autoboot: 0 +=> loads +## Ready for S-Record download ... + +## First Load Addr = 0x00040000 +## Last Load Addr = 0x00050177 +## Total Size = 0x00010178 = 65912 Bytes +## Start Addr = 0x00040004 +=> go 40004 +## Starting application at 0x00040004 ... +Hello World +argc = 1 +argv[0] = "40004" +argv[1] = "" +Hit any key to exit ... + +## Application terminated, rc = 0x0 + + +x.x Image download and run over ethernet interface + +untested (not working yet, actually) diff --git a/board/musenki/config.mk b/board/musenki/config.mk new file mode 100644 index 0000000..18673e1 --- /dev/null +++ b/board/musenki/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# CU824 board +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/musenki/flash.c b/board/musenki/flash.c new file mode 100644 index 0000000..cd33d8e --- /dev/null +++ b/board/musenki/flash.c @@ -0,0 +1,512 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_char *addr, flash_info_t *info); +static int write_data (flash_info_t *info, uchar *dest, uchar data); +static void flash_get_offsets (ulong base, flash_info_t *info); + + +/* + * don't ask. its stupid, but more than one soul has had to live with this mistake + * "swaptab[i]" is the value of "i" with the bits reversed. + */ + +#define MUSENKI_BROKEN_FLASH 1 + +#ifdef MUSENKI_BROKEN_FLASH +unsigned char swaptab[256] = { + 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, + 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, + 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, + 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, + 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, + 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, + 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, + 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, + 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, + 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, + 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, + 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, + 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, + 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, + 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, + 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, + 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, + 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, + 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, + 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, + 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, + 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, + 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, + 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, + 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, + 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, + 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, + 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, + 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, + 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, + 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, + 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff, +}; + +#define BS(b) (swaptab[b]) + +#else + +#define BS(b) (b) + +#endif + +#define BYTEME(x) ((x) & 0xFF) + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, monitor_flash_len); + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE); + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + + if (size_b1) { + flash_info[1].size = size_b1; + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[1]); +#endif + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + flash_info[1].size = 0; + } + + DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x00020000; /* 128k per bank */ + } + return; + + default: + printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id); + return; + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("Fujitsu "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_MT: printf ("MT "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n"); + break; + case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n"); + break; + case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >= (1 << 20)) { + i = 20; + } else { + i = 10; + } + printf (" Size: %ld %cB in %d Sectors\n", + info->size >> i, + (i == 20) ? 'M' : 'k', + info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_char *addr, flash_info_t *info) +{ + vu_char manuf, device; + + addr[0] = BS(0x90); + manuf = BS(addr[0]); + DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (vu_char *)addr, manuf); + + switch (manuf) { + case BYTEME(AMD_MANUFACT): + info->flash_id = FLASH_MAN_AMD; + break; + case BYTEME(FUJ_MANUFACT): + info->flash_id = FLASH_MAN_FUJ; + break; + case BYTEME(SST_MANUFACT): + info->flash_id = FLASH_MAN_SST; + break; + case BYTEME(STM_MANUFACT): + info->flash_id = FLASH_MAN_STM; + break; + case BYTEME(INTEL_MANUFACT): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */ + return 0; /* no or unknown flash */ + } + + device = BS(addr[2]); /* device ID */ + + DEBUGF("Device ID @ 0x%08x: 0x%08x\n", (&addr[1]), device); + + switch (device) { + case BYTEME(INTEL_ID_28F320J3A): + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 4 MB */ + + case BYTEME(INTEL_ID_28F640J3A): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + case BYTEME(INTEL_ID_28F128J3A): + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */ + return 0; /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = BS(0xFF); /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_char *addr = (vu_char *)(info->start[sect]); + unsigned long status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = BS(0x50); /* clear status register */ + *addr = BS(0x20); /* erase setup */ + *addr = BS(0xD0); /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = BS(0xB0); /* suspend erase */ + *addr = BS(0xFF); /* reset to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = BS(0xFF); /* reset to read mode */ + } + } + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 1 /* flash bus width in bytes */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + uchar *wp = (uchar *)addr; + int rc; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + while (cnt > 0) { + if ((rc = write_data(info, wp, *src)) != 0) { + return rc; + } + wp++; + src++; + cnt--; + } + + return cnt; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, uchar *dest, uchar data) +{ + vu_char *addr = (vu_char *)dest; + ulong status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((BS(*addr) & data) != data) { + return 2; + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = BS(0x40); /* write setup */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + start = get_timer (0); + + while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = BS(0xFF); /* restore read mode */ + return 1; + } + } + + *addr = BS(0xFF); /* restore read mode */ + + return 0; +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c new file mode 100644 index 0000000..88ef83a --- /dev/null +++ b/board/musenki/musenki.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int checkboard (void) +{ + ulong busfreq = get_bus_freq(0); + char buf[32]; + + printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq)); + return 0; + +} + +#if 0 /* NOT USED */ +int checkflash (void) +{ + /* TODO: XXX XXX XXX */ + printf ("## Test not implemented yet ##\n"); + + return (0); +} +#endif + +long int initdram (int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +} + +/* + * Initialize PCI Devices + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_sandpoint_config_table[] = { +#if 0 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + 0x0, 0x0, 0x0, /* unknown eth0 divice */ + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + 0x0, 0x0, 0x0, /* unknown eth1 device */ + pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER }}, +#endif + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_sandpoint_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} diff --git a/board/musenki/u-boot.lds b/board/musenki/u-boot.lds new file mode 100644 index 0000000..7c05109 --- /dev/null +++ b/board/musenki/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mvblue/Makefile b/board/mvblue/Makefile new file mode 100644 index 0000000..24dc026 --- /dev/null +++ b/board/mvblue/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/mvblue/config.mk b/board/mvblue/config.mk new file mode 100644 index 0000000..6e0ce4e --- /dev/null +++ b/board/mvblue/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2001-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c new file mode 100644 index 0000000..8df573a --- /dev/null +++ b/board/mvblue/flash.c @@ -0,0 +1,583 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2001-2003 + * + * Changes for MATRIX Vision mvBLUE devices + * MATRIX Vision GmbH / hg,as info@matrix-vision.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if 0 + #define mvdebug(p) printf ##p +#else + #define mvdebug(p) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define FLASH_BUS_WIDTH 8 + +#if (FLASH_BUS_WIDTH==32) + #define FLASH_DATA_MASK 0xffffffff + #define FLASH_SHIFT 1 + #define FDT vu_long +#elif (FLASH_BUS_WIDTH==16) + #define FLASH_DATA_MASK 0xff + #define FLASH_SHIFT 0 + #define FDT vu_short +#elif (FLASH_BUS_WIDTH==8) + #define FLASH_DATA_MASK 0xff + #define FLASH_SHIFT 0 + #define FDT vu_char +#else + #error FLASH_BUS_WIDTH undefined +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *address, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + + for (i=0; iflash_id & FLASH_BTYPE) + { /* bottom boot sector types - these are the useful ones! */ + /* set sector offsets for bottom boot block type */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) + { /* AMDLV320B has 8 x 8k bottom boot sectors */ + for (i = 0; i < 8; i++) /* +8k */ + info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); + for (; i < info->sector_count; i++) /* +64k */ + info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT); + } + else + { /* other types have 4 bottom boot sectors (16,8,8,32) */ + i = 0; + info->start[i++] = base + 0x00000000; /* - */ + info->start[i++] = base + (0x00004000 << FLASH_SHIFT); /* +16k */ + info->start[i++] = base + (0x00006000 << FLASH_SHIFT); /* +8k */ + info->start[i++] = base + (0x00008000 << FLASH_SHIFT); /* +8k */ + info->start[i++] = base + (0x00010000 << FLASH_SHIFT); /* +32k */ + for (; i < info->sector_count; i++) /* +64k */ + info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT); + } + } + else + { /* top boot sector types - not so useful */ + /* set sector offsets for top boot block type */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) + { /* AMDLV320T has 8 x 8k top boot sectors */ + for (i = 0; i < info->sector_count - 8; i++) /* +64k */ + info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); + for (; i < info->sector_count; i++) /* +8k */ + info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); + } + else + { /* other types have 4 top boot sectors (32,8,8,16) */ + for (i = 0; i < info->sector_count - 4; i++) /* +64k */ + info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); + + info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT); /* -32k */ + info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT); /* -8k */ + info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT); /* -8k */ + info->start[i] = base + info->size - (0x00004000 << FLASH_SHIFT); /* -16k */ + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_STM: printf ("ST "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_STMW320DB: printf ("M29W320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_STMW320DT: printf ("M29W320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ + +#define AMD_ID_LV160T_MVS (AMD_ID_LV160T & FLASH_DATA_MASK) +#define AMD_ID_LV160B_MVS (AMD_ID_LV160B & FLASH_DATA_MASK) +#define AMD_ID_LV320T_MVS (AMD_ID_LV320T & FLASH_DATA_MASK) +#define AMD_ID_LV320B_MVS (AMD_ID_LV320B & FLASH_DATA_MASK) +#define STM_ID_W320DT_MVS (STM_ID_29W320DT & FLASH_DATA_MASK) +#define STM_ID_W320DB_MVS (STM_ID_29W320DB & FLASH_DATA_MASK) +#define AMD_MANUFACT_MVS (AMD_MANUFACT & FLASH_DATA_MASK) +#define FUJ_MANUFACT_MVS (FUJ_MANUFACT & FLASH_DATA_MASK) +#define STM_MANUFACT_MVS (STM_MANUFACT & FLASH_DATA_MASK) + +#if (FLASH_BUS_WIDTH >= 16) + #define AUTOSELECT_ADDR1 0x0555 + #define AUTOSELECT_ADDR2 0x02AA + #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 +#else + #define AUTOSELECT_ADDR1 0x0AAA + #define AUTOSELECT_ADDR2 0x0555 + #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 +#endif + +#define AUTOSELECT_DATA1 (0x00AA00AA & FLASH_DATA_MASK) +#define AUTOSELECT_DATA2 (0x00550055 & FLASH_DATA_MASK) +#define AUTOSELECT_DATA3 (0x00900090 & FLASH_DATA_MASK) + +#define RESET_BANK_DATA (0x00F000F0 & FLASH_DATA_MASK) + + +static ulong flash_get_size (vu_long *address, flash_info_t *info) +{ + short i; + FDT value; + FDT *addr = (FDT *)address; + + ulong base = (ulong)address; + addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1; + addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2; + addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3; + __asm__ __volatile__("sync"); + + udelay(180); + + value = addr[0]; /* manufacturer ID */ + switch (value) { + case AMD_MANUFACT_MVS: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT_MVS: + info->flash_id = FLASH_MAN_FUJ; + break; + case STM_MANUFACT_MVS: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } +#if (FLASH_BUS_WIDTH >= 16) + value = addr[1]; /* device ID */ +#else + value = addr[2]; /* device ID */ +#endif + + switch (value) { + case AMD_ID_LV160T_MVS: + info->flash_id += FLASH_AM160T; + info->sector_count = 37; + info->size = (0x00200000 << FLASH_SHIFT); + break; /* => 2 or 4 MB */ + + case AMD_ID_LV160B_MVS: + info->flash_id += FLASH_AM160B; + info->sector_count = 37; + info->size = (0x00200000 << FLASH_SHIFT); + break; /* => 2 or 4 MB */ + + case AMD_ID_LV320T_MVS: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = (0x00400000 << FLASH_SHIFT); + break; /* => 4 or 8 MB */ + + case AMD_ID_LV320B_MVS: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = (0x00400000 << FLASH_SHIFT); + break; /* => 4 or 8MB */ + + case STM_ID_W320DT_MVS: + info->flash_id += FLASH_STMW320DT; + info->sector_count = 67; + info->size = (0x00400000 << FLASH_SHIFT); + break; /* => 4 or 8 MB */ + + case STM_ID_W320DB_MVS: + info->flash_id += FLASH_STMW320DB; + info->sector_count = 67; + info->size = (0x00400000 << FLASH_SHIFT); + break; /* => 4 or 8MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + flash_get_offsets (base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (FDT *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (FDT *)info->start[0]; + *addr = RESET_BANK_DATA; /* reset bank */ + } + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +#if (FLASH_BUS_WIDTH >= 16) + #define ERASE_ADDR1 0x0555 + #define ERASE_ADDR2 0x02AA +#else + #define ERASE_ADDR1 0x0AAA + #define ERASE_ADDR2 0x0555 +#endif + +#define ERASE_ADDR3 ERASE_ADDR1 +#define ERASE_ADDR4 ERASE_ADDR1 +#define ERASE_ADDR5 ERASE_ADDR2 + +#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) +#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK) +#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK) +#define ERASE_DATA4 ERASE_DATA1 +#define ERASE_DATA5 ERASE_DATA2 + +#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK) +#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK) +#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK) + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FDT *addr = (FDT *)(info->start[0]); + + int prot, sect, l_sect, flag; + ulong start, now, last; + + __asm__ __volatile__ ("sync"); + addr[0] = 0xf0; + udelay(1000); + + printf("\nflash_erase: first = %d @ 0x%08lx\n", s_first, info->start[s_first] ); + printf(" last = %d @ 0x%08lx\n", s_last , info->start[s_last ] ); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[ERASE_ADDR1] = ERASE_DATA1; + addr[ERASE_ADDR2] = ERASE_DATA2; + addr[ERASE_ADDR3] = ERASE_DATA3; + addr[ERASE_ADDR4] = ERASE_DATA4; + addr[ERASE_ADDR5] = ERASE_DATA5; + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { + addr = (FDT *)(info->start[sect]); + addr[0] = ERASE_SECTOR_DATA; + l_sect = sect; + } + } + + if (flag) + enable_interrupts(); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FDT *)(info->start[l_sect]); + + while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ +#define BUFF_INC 4 + ulong cp, wp, data; + int i, l, rc; + + mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt)); + + wp = (addr & ~3); /* get lower word aligned address */ + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + mvdebug ((" handle unaligned start bytes (cnt = 0x%08lx)\n", cnt)); + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= BUFF_INC) { + data = 0; + for (i=0; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i= 16) + #define WRITE_ADDR1 0x0555 + #define WRITE_ADDR2 0x02AA +#else + #define WRITE_ADDR1 0x0AAA + #define WRITE_ADDR2 0x0555 + #define WRITE_ADDR3 WRITE_ADDR1 +#endif + +#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) +#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK) +#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK) + +#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA + +/*----------------------------------------------------------------------- + * Write a byte to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_char (flash_info_t *info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *)dest) & data) != data) { + printf(" *** ERROR: Flash not erased !\n"); + return (2); + } + flag = disable_interrupts(); + + addr[WRITE_ADDR1] = WRITE_DATA1; + addr[WRITE_ADDR2] = WRITE_DATA2; + addr[WRITE_ADDR3] = WRITE_DATA3; + *((vu_char *)dest) = data; + + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + addr = (vu_char *)dest; + while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + printf(" *** ERROR: Flash write timeout !"); + return (1); + } + } + mvdebug (("-write_byte\n")); + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + int i, + result = 0; + + mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest)); + for ( i=0; (i < 4) && (result == 0); i++, dest+=1 ) + result = write_char (info, dest, (data >> (8*(3-i))) & 0xff ); + mvdebug (("-write_word\n")); + return result; +} +/*---------------------------------------------------------------- */ diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c new file mode 100644 index 0000000..20a551d --- /dev/null +++ b/board/mvblue/mvblue.c @@ -0,0 +1,247 @@ +/* + * GNU General Public License for more details. + * + * MATRIX Vision GmbH / June 2002-Nov 2003 + * Andre Schwarz + */ + +#include +#include +#include +#include + +#ifdef CONFIG_PCI +#include +#endif + +u32 get_BoardType (void); + +#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \ + | ((d&0x1f)<<11) \ + | ((f&0x7)<<7) \ + | (r&0xfc) ) + +int mv_pci_read (int bus, int dev, int func, int reg) +{ + *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg); + asm ("sync"); + return cpu_to_le32 (*(u32 *) (0xfee00cfc)); +} + +u32 get_BoardType () +{ + return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1); +} + +void init_2nd_DUART (void) +{ + NS16550_t console = (NS16550_t) CFG_NS16550_COM2; + int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE; + + *(u8 *) (0xfc004511) = 0x1; + NS16550_init (console, clock_divisor); +} +void hw_watchdog_reset (void) +{ + if (get_BoardType () == 0) { + *(u32 *) (0xff000005) = 0; + asm ("sync"); + } +} +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong busfreq = get_bus_freq (0); + char buf[32]; + u32 BoardType = get_BoardType (); + char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" }; + char *p; + bd_t *bd = gd->bd; + + hw_watchdog_reset (); + + printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION); + printf (" Found %s running at %s MHz memory clock.\n", + BoardName[BoardType], strmhz (buf, busfreq)); + + init_2nd_DUART (); + + if ((p = getenv ("console_nr")) != NULL) { + unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; + + bd->bi_baudrate &= ~3; + bd->bi_baudrate |= con_nr & 3; + } + return 0; +} + +long int initdram (int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +} + +/* ------------------------------------------------------------------------- */ +u8 *dhcp_vendorex_prep (u8 * e) +{ + char *ptr; + + /* DHCP vendor-class-identifier = 60 */ + if ((ptr = getenv ("dhcp_vendor-class-identifier"))) { + *e++ = 60; + *e++ = strlen (ptr); + while (*ptr) + *e++ = *ptr++; + } + /* my DHCP_CLIENT_IDENTIFIER = 61 */ + if ((ptr = getenv ("dhcp_client_id"))) { + *e++ = 61; + *e++ = strlen (ptr); + while (*ptr) + *e++ = *ptr++; + } + return e; +} + +u8 *dhcp_vendorex_proc (u8 * popt) +{ + return NULL; +} + +/* ------------------------------------------------------------------------- */ + +/* + * Initialize PCI Devices + */ +#ifdef CONFIG_PCI +void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev) +{ + u32 cnt; + + printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev), + PCI_FUNC (dev)); + for (cnt = 0; cnt < 6; cnt++) + pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt), + 0x0); + printf ("done\n"); +} + +void duart_setup (u32 base, u16 divisor) +{ + printf ("duart setup ..."); + out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80); + out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff); + out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8); + out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03); + out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03); + out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07); + printf ("done\n"); +} + +void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose, + pci_dev_t bridge, unsigned char irq) +{ + pci_dev_t d; + unsigned char bus; + unsigned short vendor, class; + + pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus); + for (d = PCI_BDF (bus, 0, 0); + d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1, + PCI_MAX_PCI_FUNCTIONS - 1); + d += PCI_BDF (0, 0, 1)) { + pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor); + if (vendor != 0xffff && vendor != 0x0000) { + pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE, + &class); + if (class == PCI_CLASS_BRIDGE_PCI) + pci_mvblue_fixup_irq_behind_bridge (hose, d, + irq); + else + pci_hose_write_config_byte (hose, d, + PCI_INTERRUPT_LINE, + irq); + } + } +} + +#define MV_MAX_PCI_BUSSES 3 +#define SLOT0_IRQ 3 +#define SLOT1_IRQ 4 +void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char line = 0xff; + unsigned short class; + + if (PCI_BUS (dev) == 0) { + switch (PCI_DEV (dev)) { + case 0xd: + if (get_BoardType () == 0) { + line = 1; + } else + /* mvBL */ + line = 2; + break; + case 0xe: + /* mvBB: IDE */ + line = 2; + pci_hose_write_config_byte (hose, dev, 0x8a, 0x20); + break; + case 0xf: + /* mvBB: Slot0 (Grabber) */ + pci_hose_read_config_word (hose, dev, + PCI_CLASS_DEVICE, &class); + if (class == PCI_CLASS_BRIDGE_PCI) { + pci_mvblue_fixup_irq_behind_bridge (hose, dev, + SLOT0_IRQ); + line = 0xff; + } else + line = SLOT0_IRQ; + break; + case 0x10: + /* mvBB: Slot1 */ + pci_hose_read_config_word (hose, dev, + PCI_CLASS_DEVICE, &class); + if (class == PCI_CLASS_BRIDGE_PCI) { + pci_mvblue_fixup_irq_behind_bridge (hose, dev, + SLOT1_IRQ); + line = 0xff; + } else + line = SLOT1_IRQ; + break; + default: + printf ("***pci_scan: illegal dev = 0x%08x\n", + PCI_DEV (dev)); + line = 0xff; + break; + } + pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, + line); + } +} + +struct pci_controller hose = { + fixup_irq:pci_mvblue_fixup_irq +}; + +void pci_init_board (void) +{ + pci_mpc824x_init (&hose); +} +#endif diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds new file mode 100644 index 0000000..7c05109 --- /dev/null +++ b/board/mvblue/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mvs1/Makefile b/board/mvs1/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/mvs1/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/mvs1/README b/board/mvs1/README new file mode 100644 index 0000000..69520bd --- /dev/null +++ b/board/mvs1/README @@ -0,0 +1,14 @@ +This port is for the MATRIX Vision mvSensor. +It is an mpc823-based universal image processing board +with CMOS or CCD sensor, 4MB FLASH and 16-64MB RAM. + +See http://www.matrix-vision.de for more details or mail... + +mvsensor@matrix-vision.de + +Howard Gray +MATRIX Vision GmbH +Talstr. 16 +D-71570 +Oppenweiler +Germany diff --git a/board/mvs1/config.mk b/board/mvs1/config.mk new file mode 100644 index 0000000..9d6080b --- /dev/null +++ b/board/mvs1/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8xxL boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/mvs1/flash.c b/board/mvs1/flash.c new file mode 100644 index 0000000..0845943 --- /dev/null +++ b/board/mvs1/flash.c @@ -0,0 +1,719 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Changes for MATRIX Vision MVsensor (C) Copyright 2001 + * MATRIX Vision GmbH / hg, info@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#undef MVDEBUG +#ifdef MVDEBUG +#define mvdebug debug +#else +#define mvdebug(p) do {} while (0) +#endif + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +#ifdef CONFIG_MVS_16BIT_FLASH + #define FLASH_DATA_MASK 0xffff + #define FLASH_SHIFT 0 +#else + #define FLASH_DATA_MASK 0xffffffff + #define FLASH_SHIFT 1 +#endif + + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *address, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } +#else + size_b1 = 0; +#endif + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); +#ifdef CONFIG_MVS_16BIT_FLASH + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; +#else + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_GPCM | BR_V; +#endif + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE+monitor_flash_len-1, + &flash_info[0]); + + if (size_b1) { + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); +#ifdef CONFIG_MVS_16BIT_FLASH + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_PS_16 | BR_MS_GPCM | BR_V; +#else + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_PS_32 | BR_MS_GPCM | BR_V; +#endif + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE+monitor_flash_len-1, + &flash_info[1]); + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) + { /* bottom boot sector types - these are the useful ones! */ + /* set sector offsets for bottom boot block type */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) + { /* AMDLV320B has 8 x 8k bottom boot sectors */ + for (i = 0; i < 8; i++) /* +8k */ + info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); + for (; i < info->sector_count; i++) /* +64k */ + info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT); + } + else + { /* other types have 4 bottom boot sectors (16,8,8,32) */ + i = 0; + info->start[i++] = base + 0x00000000; /* - */ + info->start[i++] = base + (0x00004000 << FLASH_SHIFT); /* +16k */ + info->start[i++] = base + (0x00006000 << FLASH_SHIFT); /* +8k */ + info->start[i++] = base + (0x00008000 << FLASH_SHIFT); /* +8k */ + info->start[i++] = base + (0x00010000 << FLASH_SHIFT); /* +32k */ + for (; i < info->sector_count; i++) /* +64k */ + info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT); + } + } + else + { /* top boot sector types - not so useful */ + /* set sector offsets for top boot block type */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) + { /* AMDLV320T has 8 x 8k top boot sectors */ + for (i = 0; i < info->sector_count - 8; i++) /* +64k */ + info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); + for (; i < info->sector_count; i++) /* +8k */ + info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); + } + else + { /* other types have 4 top boot sectors (32,8,8,16) */ + for (i = 0; i < info->sector_count - 4; i++) /* +64k */ + info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); + + info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT); /* -32k */ + info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT); /* -8k */ + info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT); /* -8k */ + info->start[i] = base + info->size - (0x00004000 << FLASH_SHIFT); /* -16k */ + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_STM: printf ("ST "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_STMW320DB: printf ("M29W320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_STMW320DT: printf ("M29W320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +#define AMD_ID_LV160T_MVS (AMD_ID_LV160T & FLASH_DATA_MASK) +#define AMD_ID_LV160B_MVS (AMD_ID_LV160B & FLASH_DATA_MASK) +#define AMD_ID_LV320T_MVS (AMD_ID_LV320T & FLASH_DATA_MASK) +#define AMD_ID_LV320B_MVS (AMD_ID_LV320B & FLASH_DATA_MASK) +#define STM_ID_W320DT_MVS (STM_ID_29W320DT & FLASH_DATA_MASK) +#define STM_ID_W320DB_MVS (STM_ID_29W320DB & FLASH_DATA_MASK) +#define AMD_MANUFACT_MVS (AMD_MANUFACT & FLASH_DATA_MASK) +#define FUJ_MANUFACT_MVS (FUJ_MANUFACT & FLASH_DATA_MASK) +#define STM_MANUFACT_MVS (STM_MANUFACT & FLASH_DATA_MASK) + +#define AUTOSELECT_ADDR1 0x0555 +#define AUTOSELECT_ADDR2 0x02AA +#define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 + +#define AUTOSELECT_DATA1 (0x00AA00AA & FLASH_DATA_MASK) +#define AUTOSELECT_DATA2 (0x00550055 & FLASH_DATA_MASK) +#define AUTOSELECT_DATA3 (0x00900090 & FLASH_DATA_MASK) + +#define RESET_BANK_DATA (0x00F000F0 & FLASH_DATA_MASK) + +static ulong flash_get_size (vu_long *address, flash_info_t *info) +{ + short i; +#ifdef CONFIG_MVS_16BIT_FLASH + ushort value; + vu_short *addr = (vu_short *)address; +#else + ulong value; + vu_long *addr = (vu_long *)address; +#endif + ulong base = (ulong)address; + + /* Write auto select command: read Manufacturer ID */ + addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1; + addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2; + addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3; + + value = addr[0]; /* manufacturer ID */ + switch (value) { + case AMD_MANUFACT_MVS: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT_MVS: + info->flash_id = FLASH_MAN_FUJ; + break; + case STM_MANUFACT_MVS: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + switch (value) { + case AMD_ID_LV160T_MVS: + info->flash_id += FLASH_AM160T; + info->sector_count = 37; + info->size = (0x00200000 << FLASH_SHIFT); + break; /* => 2 or 4 MB */ + + case AMD_ID_LV160B_MVS: + info->flash_id += FLASH_AM160B; + info->sector_count = 37; + info->size = (0x00200000 << FLASH_SHIFT); + break; /* => 2 or 4 MB */ + + case AMD_ID_LV320T_MVS: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = (0x00400000 << FLASH_SHIFT); + break; /* => 4 or 8 MB */ + + case AMD_ID_LV320B_MVS: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = (0x00400000 << FLASH_SHIFT); + break; /* => 4 or 8MB */ + + case STM_ID_W320DT_MVS: + info->flash_id += FLASH_STMW320DT; + info->sector_count = 67; + info->size = (0x00400000 << FLASH_SHIFT); + break; /* => 4 or 8 MB */ + + case STM_ID_W320DB_MVS: + info->flash_id += FLASH_STMW320DB; + info->sector_count = 67; + info->size = (0x00400000 << FLASH_SHIFT); + break; /* => 4 or 8MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + flash_get_offsets (base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ +#ifdef CONFIG_MVS_16BIT_FLASH + addr = (vu_short *)(info->start[i]); +#else + addr = (vu_long *)(info->start[i]); +#endif + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { +#ifdef CONFIG_MVS_16BIT_FLASH + addr = (vu_short *)info->start[0]; +#else + addr = (vu_long *)info->start[0]; +#endif + *addr = RESET_BANK_DATA; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +#define ERASE_ADDR1 0x0555 +#define ERASE_ADDR2 0x02AA +#define ERASE_ADDR3 ERASE_ADDR1 +#define ERASE_ADDR4 ERASE_ADDR1 +#define ERASE_ADDR5 ERASE_ADDR2 + +#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) +#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK) +#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK) +#define ERASE_DATA4 ERASE_DATA1 +#define ERASE_DATA5 ERASE_DATA2 + +#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK) +#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK) +#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK) + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ +#ifdef CONFIG_MVS_16BIT_FLASH + vu_short *addr = (vu_short *)(info->start[0]); +#else + vu_long *addr = (vu_long *)(info->start[0]); +#endif + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[ERASE_ADDR1] = ERASE_DATA1; + addr[ERASE_ADDR2] = ERASE_DATA2; + addr[ERASE_ADDR3] = ERASE_DATA3; + addr[ERASE_ADDR4] = ERASE_DATA4; + addr[ERASE_ADDR5] = ERASE_DATA5; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ +#ifdef CONFIG_MVS_16BIT_FLASH + addr = (vu_short *)(info->start[sect]); +#else + addr = (vu_long *)(info->start[sect]); +#endif + addr[0] = ERASE_SECTOR_DATA; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; +#ifdef CONFIG_MVS_16BIT_FLASH + addr = (vu_short *)(info->start[l_sect]); +#else + addr = (vu_long *)(info->start[l_sect]); +#endif + while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ +#ifdef CONFIG_MVS_16BIT_FLASH + addr = (vu_short *)info->start[0]; +#else + addr = (vu_long *)info->start[0]; +#endif + addr[0] = RESET_BANK_DATA; /* reset bank */ + + printf (" done\n"); + return 0; +} + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ +#define BUFF_INC 4 + ulong cp, wp, data; + int i, l, rc; + + mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt)); + + wp = (addr & ~3); /* get lower word aligned address */ + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + mvdebug ((" handle unaligned start bytes (cnt = 0x%08%lx)\n", cnt)); + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= BUFF_INC) { + data = 0; + for (i=0; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; istart[0]); + ulong start; + int flag; + + mvdebug (("+write_word (to 0x%08lx)\n", dest)); + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[WRITE_ADDR1] = WRITE_DATA1; + addr[WRITE_ADDR2] = WRITE_DATA2; + addr[WRITE_ADDR3] = WRITE_DATA3; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + addr = (vu_long *)dest; + while ((*addr & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + mvdebug (("-write_word\n")); + return (0); +} +#else /* CONFIG_MVS_16BIT_FLASH */ +/*----------------------------------------------------------------------- + * Write a halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_halfword (flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *)(info->start[0]); + ulong start; + int flag; + + mvdebug (("+write_halfword (to 0x%08lx)\n", dest)); + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_short *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[WRITE_ADDR1] = WRITE_DATA1; + addr[WRITE_ADDR2] = WRITE_DATA2; + addr[WRITE_ADDR3] = WRITE_DATA3; + + *((vu_short *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + addr = (vu_short *)dest; + while ((*addr & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + mvdebug (("-write_halfword\n")); + return (0); +} + + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + int result = 0; + + if (write_halfword (info, dest, (data & ~FLASH_DATA_MASK) >> 16) == 0) + { + dest += 2; + data = data & FLASH_DATA_MASK; + result = write_halfword (info, dest, data); + } + return result; +} +#endif +/*----------------------------------------------------------------------- + */ diff --git a/board/mvs1/mvs1.c b/board/mvs1/mvs1.c new file mode 100644 index 0000000..f8a8cb7 --- /dev/null +++ b/board/mvs1/mvs1.c @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Changes for MATRIX Vision MVsensor (C) Copyright 2001 + * MATRIX Vision GmbH / hg, info@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, + 0x1FF5FC47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F0DFC04 /*0x1F2DFC04??*/, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: MATRIX Vision MVsensor\n"); + return 0; +} + + +#ifdef DO_RAM_TEST +/* ------------------------------------------------------------------------- */ + +/* + * Test SDRAM by writing its address to itself and reading several times +*/ +#define READ_RUNS 4 +static void test_dram (unsigned long *start, unsigned long *end) +{ + unsigned long *addr; + unsigned long value; + int read_runs, errors, addr_errors; + + printf ("\nChecking SDRAM from %p to %p\n", start, end); + udelay (1000000); + for (addr = start; addr < end; addr++) + *addr = (unsigned long) addr; + + for (addr = start, addr_errors = 0; addr < end; addr++) { + for (read_runs = READ_RUNS, errors = 0; read_runs > 0; read_runs--) { + if ((value = *addr) != (unsigned long) addr) + errors++; + } + if (errors > 0) { + addr_errors++; + printf ("SDRAM errors (%d) at %p, last read = %ld\n", + errors, addr, value); + udelay (10000); + } + } + printf ("SDRAM check finished, total errors = %d\n", addr_errors); +} +#endif /* DO_RAM_TEST */ + + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0, size_b1, size8, size9; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + +#if defined (CFG_OR3_PRELIM) && defined (CFG_BR3_PRELIM) + if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + } +#endif + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ + udelay (1); + + if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ + memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ + udelay (1); + memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ + udelay (1); + } + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size_b0 = size9; + } else { /* back to 8 columns */ + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); + } + + if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ + /* + * Check Bank 1 Memory Size + * use current column settings + * [9 column SDRAM may also be used in 8 column mode, + * but then only half the real size will be used.] + */ +#if defined (SDRAM_BASE3_PRELIM) + size_b1 = + dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); +#else + size_b1 = 0; +#endif + } else { + size_b1 = 0; + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping: map bigger bank first + */ + if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ + + memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = + (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b0 > 0) { + /* + * Position Bank 0 immediately above Bank 1 + */ + memctl->memc_or2 = + ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + + size_b1; + } else { + unsigned long reg; + + /* + * No bank 0 + * + * invalidate bank + */ + memctl->memc_br2 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + + } else { /* SDRAM Bank 0 is bigger - map first */ + + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b1 > 0) { + /* + * Position Bank 1 immediately above Bank 0 + */ + memctl->memc_or3 = + ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = + ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + + size_b0; + } else { + unsigned long reg; + + /* + * No bank 1 + * + * invalidate bank + */ + memctl->memc_br3 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + } + + udelay (10000); + +#ifdef DO_RAM_TEST + if (size_b0 > 0) + test_dram ((unsigned long *) CFG_SDRAM_BASE, + (unsigned long *) (CFG_SDRAM_BASE + size_b0)); +#endif + + return (size_b0 + size_b1); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + + +/* ------------------------------------------------------------------------- */ + +u8 *dhcp_vendorex_prep (u8 * e) +{ + char *ptr; + +/* DHCP vendor-class-identifier = 60 */ + if ((ptr = getenv ("dhcp_vendor-class-identifier"))) { + *e++ = 60; + *e++ = strlen (ptr); + while (*ptr) + *e++ = *ptr++; + } +/* my DHCP_CLIENT_IDENTIFIER = 61 */ + if ((ptr = getenv ("dhcp_client_id"))) { + *e++ = 61; + *e++ = strlen (ptr); + while (*ptr) + *e++ = *ptr++; + } + + return e; +} + + +/* ------------------------------------------------------------------------- */ +u8 *dhcp_vendorex_proc (u8 * popt) +{ + return NULL; +} diff --git a/board/mvs1/u-boot.lds b/board/mvs1/u-boot.lds new file mode 100644 index 0000000..a04de3d --- /dev/null +++ b/board/mvs1/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_generic/ctype.o (.text) + lib_generic/string.o (.text) + lib_ppc/extable.o (.text) + lib_ppc/kgdb.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mvs1/u-boot.lds.debug b/board/mvs1/u-boot.lds.debug new file mode 100644 index 0000000..ddd4678 --- /dev/null +++ b/board/mvs1/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile new file mode 100644 index 0000000..3e805fe --- /dev/null +++ b/board/mx1ads/Makefile @@ -0,0 +1,48 @@ +# +# board/mx1ads/Makefile +# +# (c) Copyright 2004 +# Techware Information Technology, Inc. +# http://www.techware.com.tw/ +# +# Ming-Len Wu +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := mx1ads.o syncflash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mx1ads/config.mk b/board/mx1ads/config.mk new file mode 100644 index 0000000..f6ac40d --- /dev/null +++ b/board/mx1ads/config.mk @@ -0,0 +1,25 @@ +# +# board/mx1ads/config.mk +# +# (c) Copyright 2004 +# Techware Information Technology, Inc. +# http://www.techware.com.tw/ +# +# Ming-Len Wu +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +TEXT_BASE = 0x08400000 diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S new file mode 100644 index 0000000..09c260d --- /dev/null +++ b/board/mx1ads/lowlevel_init.S @@ -0,0 +1,81 @@ +/* + * board/mx1ads/lowlevel_init.S + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define SDCTL0 0x221000 +#define SDCTL1 0x221004 + + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: +/* memory controller init */ + + ldr r1, =SDCTL0 + +/* Set Precharge Command */ + + ldr r3, =0x92120200 +/* ldr r3, =0x92120251 +*/ + str r3, [r1] + +/* Issue Precharge All Commad */ + ldr r3, =0x8200000 + ldr r2, [r3] + +/* Set AutoRefresh Command */ + ldr r3, =0xA2120200 + str r3, [r1] + +/* Issue AutoRefresh Command */ + ldr r3, =0x8000000 + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + +/* Set Mode Register */ + ldr r3, =0xB2120200 + str r3, [r1] + +/* Issue Mode Register Command */ + ldr r3, =0x08111800 /* Mode Register Value */ + ldr r2, [r3] + +/* Set Normal Mode */ + ldr r3, =0x82124200 + str r3, [r1] + +/* everything is fine now */ + mov pc, lr diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c new file mode 100644 index 0000000..5c33ba3 --- /dev/null +++ b/board/mx1ads/mx1ads.c @@ -0,0 +1,168 @@ +/* + * board/mx1ads/mx1ads.c + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +/*#include */ +#include + +/* ------------------------------------------------------------------------- */ + +#define FCLK_SPEED 1 + +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ +#define M_MDIV 0xC3 +#define M_PDIV 0x4 +#define M_SDIV 0x1 +#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ +#define M_MDIV 0xA1 +#define M_PDIV 0x3 +#define M_SDIV 0x1 +#endif + +#define USB_CLOCK 1 + +#if USB_CLOCK==0 +#define U_M_MDIV 0xA1 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x1 +#elif USB_CLOCK==1 +#define U_M_MDIV 0x48 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x2 +#endif + +#if 0 + +static inline void delay (unsigned long loops) { + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +#endif + +/* + * Miscellaneous platform dependent initialisations + */ + +void SetAsynchMode(void) { + __asm__ ( + "mrc p15,0,r0,c1,c0,0 \n" + "mov r2, #0xC0000000 \n" + "orr r0,r2,r0 \n" + "mcr p15,0,r0,c1,c0,0 \n" + ); +} + +static u32 mc9328sid; + +int board_init (void) { + + DECLARE_GLOBAL_DATA_PTR; + + volatile unsigned int tmp; + + mc9328sid = SIDR; + + GPCR = 0x000003AB; /* I/O pad driving strength */ + +/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ +/* MX1_CS1L = 0x11110601; */ + + MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ + +/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and + * BCLK divider to 2 (i.e. BCLK to 48 MHz) + */ + CSCR = 0xAF000403; + + CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ + CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ + +/* setup cs4 for cs8900 ethernet */ + + CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ + CS4L = 0x00001501; + + GIUS(0) &= 0xFF3FFFFF; + GPR(0) &= 0xFF3FFFFF; + + tmp = *(unsigned int *)(0x1500000C); + tmp = *(unsigned int *)(0x1500000C); + + SetAsynchMode(); + + gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; + + gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ + + icache_enable(); + dcache_enable(); + +/* set PERCLKs */ + PCDR = 0x00000055; /* set PERCLKS */ + +/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes + * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place + * all sources selected as normal interrupt + */ + +/* MX1_INTTYPEH = 0; + MX1_INTTYPEL = 0; +*/ + return 0; +} + +int board_late_init(void) { + + setenv("stdout", "serial"); + setenv("stderr", "serial"); + + switch (mc9328sid) { + case 0x0005901d : + printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid); + break; + case 0x04d4c01d : + printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid); + break; + case 0x00d4c01d : + printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid); + break; + + default : + printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid); + break; + } + return 0; +} + +int dram_init (void) { + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c new file mode 100644 index 0000000..eb7fde5 --- /dev/null +++ b/board/mx1ads/syncflash.c @@ -0,0 +1,322 @@ +/* + * board/mx1ads/syncflash.c + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +/*#include */ +#include + +typedef unsigned long * p_u32; + +/* 4Mx16x2 IAM=0 CSD1 */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Following Setting is for CSD1 */ +#define SFCTL 0x00221004 +#define reg_SFCTL __REG(SFCTL) + +#define SYNCFLASH_A10 (0x00100000) + +#define CMD_NORMAL (0x81020300) /* Normal Mode */ +#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ +#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ +#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ +#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ +#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) + +#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ + +/* LCR Command */ +#define LCR_READSTATUS (0x0001C000) /* 0x70 */ +#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ +#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ +#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ +#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ + +/* Get Status register */ +u32 SF_SR(void) { + u32 tmp,tmp1; + + reg_SFCTL = CMD_PROGRAM; + tmp = __REG(CFG_FLASH_BASE); + + reg_SFCTL = CMD_NORMAL; + + reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ + tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR); + + return tmp; +} + +/* check if SyncFlash is ready */ +u8 SF_Ready(void) { + u32 tmp; + + tmp = SF_SR(); + + if ((tmp & 0x00800000) && (tmp & 0x001C0000)) { + printf ("SyncFlash Error code %08x\n",tmp); + }; + + if ((tmp & 0x00000080) && (tmp & 0x0000001C)) { + printf ("SyncFlash Error code %08x\n",tmp); + }; + + if (tmp == 0x00800080) /* Test Bit 7 of SR */ + return 1; + else + return 0; +} + +/* Issue the precharge all command */ +void SF_PrechargeAll(void) { + + u32 tmp; + + reg_SFCTL = CMD_PREC; /* Set Precharge Command */ + tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ +} + +/* set SyncFlash to normal mode */ +void SF_Normal(void) { + + SF_PrechargeAll(); + + reg_SFCTL = CMD_NORMAL; +} + +/* Erase SyncFlash */ +void SF_Erase(u32 RowAddress) { + u32 tmp; + + reg_SFCTL = CMD_NORMAL; + tmp = __REG(RowAddress); + + reg_SFCTL = CMD_PREC; + tmp = __REG(RowAddress); + + reg_SFCTL = CMD_LCR; /* Set LCR mode */ + __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ + + reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ + __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ + + while(!SF_Ready()); +} + +void SF_NvmodeErase(void) { + SF_PrechargeAll(); + + reg_SFCTL = CMD_LCR; /* Set to LCR mode */ + __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ + + reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ + __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ + + while(!SF_Ready()); +} + +void SF_NvmodeWrite(void) { + SF_PrechargeAll(); + + reg_SFCTL = CMD_LCR; /* Set to LCR mode */ + __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ + + reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ + __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ +} + +/****************************************************************************************/ + +ulong flash_init(void) { + int i, j; + u32 tmp; + +/* Turn on CSD1 for negating RESETSF of SyncFLash */ + + reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ + udelay(200); + + reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ + tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ + + SF_Normal(); + + i = 0; + + flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; + + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000; + } + + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + + return FLASH_BANK_SIZE; +} + +void flash_print_info (flash_info_t *info) { + + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (FLASH_MAN_MT & FLASH_VENDMASK): + printf("Micron: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (FLASH_MT28S4M16LC & FLASH_TYPEMASK): + printf("2x FLASH_MT28S4M16LC (16MB Total)\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses: "); + + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) + printf ("\n "); + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*-----------------------------------------------------------------------*/ + +int flash_erase (flash_info_t *info, int s_first, int s_last) { + int iflag, cflag, prot, sect; + int rc = ERR_OK; + +/* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) + return ERR_INVAL; + + if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + + prot = 0; + + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf("protected!\n"); + return ERR_PROTECTED; + } +/* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status(); + icache_disable(); + iflag = disable_interrupts(); + +/* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc(); sect++) { + + printf("Erasing sector %2d ... ", sect); + +/* arm simple, non interrupt dependent timer */ + + reset_timer_masked(); + + SF_NvmodeErase(); + SF_NvmodeWrite(); + + SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect)); + SF_Normal(); + + printf("ok.\n"); + } + + if (ctrlc()) + printf("User Interrupt!\n"); + + if (iflag) + enable_interrupts(); + + if (cflag) + icache_enable(); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { + int i; + + for(i = 0; i < cnt; i += 4) { + + SF_PrechargeAll(); + + reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ + __REG(addr + i) = __REG((u32)src + i); + + while(!SF_Ready()); + } + + SF_Normal(); + + return ERR_OK; +} diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds new file mode 100644 index 0000000..8438f99 --- /dev/null +++ b/board/mx1ads/u-boot.lds @@ -0,0 +1,58 @@ +/* + * board/mx1ads/u-boot.lds + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mx1fs2/Makefile b/board/mx1fs2/Makefile new file mode 100644 index 0000000..9e3bca1 --- /dev/null +++ b/board/mx1fs2/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := mx1fs2.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mx1fs2/config.mk b/board/mx1fs2/config.mk new file mode 100644 index 0000000..59ab542 --- /dev/null +++ b/board/mx1fs2/config.mk @@ -0,0 +1,10 @@ +# +# This config file is used for compilation of IMX sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +# + +TEXT_BASE = 0x08f00000 diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c new file mode 100644 index 0000000..3806310 --- /dev/null +++ b/board/mx1fs2/flash.c @@ -0,0 +1,849 @@ +/* + * (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) 2003 August Hoeraendl, Logotronic GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#undef CONFIG_FLASH_16BIT + +#include + +#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE +#define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; + +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +/*----------------------------------------------------------------------- + * Functions + */ +#if 0 +static ulong flash_get_size(FPWV * addr, flash_info_t * info); +static void flash_get_offsets(ulong base, flash_info_t * info); +#endif +static void flash_reset(flash_info_t * info); +static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data); +static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); +#define write_word(in, de, da) write_word_amd(in, de, da) +#ifdef CFG_FLASH_PROTECTION +static void flash_sync_real_protect(flash_info_t * info); +#endif + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +ulong +flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + flash_info[i].flash_id = + (FLASH_MAN_AMD & FLASH_VENDMASK) | + (FLASH_AM640U & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) { + case 0: + flashbase = MX1FS2_FLASH_BASE; + break; + default: + panic("configured too many flash banks!\n"); + break; + } + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + _bss_start - _armboot_start, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void +flash_reset(flash_info_t * info) +{ + FPWV *base = (FPWV *) (info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW) 0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ +#if 0 +static void +flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL + && (info->flash_id & FLASH_BTYPE)) { + int bootsect_size; /* number of bytes/boot sector */ + int sect_size; /* number of bytes/regular sector */ + + bootsect_size = 0x00002000 * (sizeof (FPW) / 2); + sect_size = 0x00010000 * (sizeof (FPW) / 2); + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < 8; ++i) { + info->start[i] = base + (i * bootsect_size); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i - 7) * sect_size); + } + } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof (FPW) / 2); + + /* set up sector start address table (uniform sector type) */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * sect_size); + } +} +#endif /* 0 */ + +/*----------------------------------------------------------------------- + */ + +void +flash_print_info(flash_info_t * info) +{ + int i; + uchar *boottype; + uchar *bootletter; + uchar *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_BM: + printf("BRIGHT MICRO "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_SST: + printf("SST "); + break; + case FLASH_MAN_STM: + printf("STM "); + break; + case FLASH_MAN_INTEL: + printf("INTEL "); + break; + default: + printf("Unknown Vendor "); + break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM640U: + fmt = "29LV641D (64 Mbit, uniform sectors)\n"; + break; + case FLASH_28F800C3B: + case FLASH_28F800C3T: + fmt = "28F800C3%s (8 Mbit, %s)\n"; + break; + case FLASH_INTEL800B: + case FLASH_INTEL800T: + fmt = "28F800B3%s (8 Mbit, %s)\n"; + break; + case FLASH_28F160C3B: + case FLASH_28F160C3T: + fmt = "28F160C3%s (16 Mbit, %s)\n"; + break; + case FLASH_INTEL160B: + case FLASH_INTEL160T: + fmt = "28F160B3%s (16 Mbit, %s)\n"; + break; + case FLASH_28F320C3B: + case FLASH_28F320C3T: + fmt = "28F320C3%s (32 Mbit, %s)\n"; + break; + case FLASH_INTEL320B: + case FLASH_INTEL320T: + fmt = "28F320B3%s (32 Mbit, %s)\n"; + break; + case FLASH_28F640C3B: + case FLASH_28F640C3T: + fmt = "28F640C3%s (64 Mbit, %s)\n"; + break; + case FLASH_INTEL640B: + case FLASH_INTEL640T: + fmt = "28F640B3%s (64 Mbit, %s)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf(fmt, bootletter, boottype); + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) { + printf("\n "); + } + + printf(" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +#if 0 +ulong +flash_get_size(FPWV * addr, flash_info_t * info) +{ + /* Write auto select command: read Manufacturer ID */ + + /* Write auto select command sequence and test FLASH answer */ + addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ + addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ + addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + switch (addr[0] & 0xff) { + + case (uchar) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) + switch (addr[1]) { + + case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000 * (sizeof (FPW) / 2); + break; /* => 8 or 16 MB */ + + case (FPW) INTEL_ID_28F800C3B: + info->flash_id += FLASH_28F800C3B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof (FPW) / 2); + break; /* => 1 or 2 MB */ + + case (FPW) INTEL_ID_28F800B3B: + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof (FPW) / 2); + break; /* => 1 or 2 MB */ + + case (FPW) INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof (FPW) / 2); + break; /* => 2 or 4 MB */ + + case (FPW) INTEL_ID_28F160B3B: + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof (FPW) / 2); + break; /* => 2 or 4 MB */ + + case (FPW) INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof (FPW) / 2); + break; /* => 4 or 8 MB */ + + case (FPW) INTEL_ID_28F320B3B: + info->flash_id += FLASH_INTEL320B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof (FPW) / 2); + break; /* => 4 or 8 MB */ + + case (FPW) INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof (FPW) / 2); + break; /* => 8 or 16 MB */ + + case (FPW) INTEL_ID_28F640B3B: + info->flash_id += FLASH_INTEL640B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof (FPW) / 2); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets((ulong) addr, info); + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} +#endif /* 0 */ + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ + +static void +flash_sync_real_protect(flash_info_t * info) +{ + FPWV *addr = (FPWV *) (info->start[0]); + FPWV *sect; + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F800C3B: + case FLASH_28F800C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + /* check for protected sectors */ + *addr = (FPW) 0x00900090; + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but mixed protected and unprotected devices + * within a sector should never happen. + */ + sect = (FPWV *) (info->start[i]); + info->protect[i] = + (sect[2] & (FPW) (0x00010001)) ? 1 : 0; + } + + /* Put FLASH back in read mode */ + flash_reset(info); + break; + + case FLASH_AM640U: + default: + /* no hardware protect that we support */ + break; + } +} +#endif + +/*----------------------------------------------------------------------- + */ + +int +flash_erase(flash_info_t * info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_INTEL800B: + case FLASH_INTEL160B: + case FLASH_INTEL320B: + case FLASH_INTEL640B: + case FLASH_28F800C3B: + case FLASH_28F160C3B: + case FLASH_28F320C3B: + case FLASH_28F640C3B: + case FLASH_AM640U: + break; + case FLASH_UNKNOWN: + default: + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + start = get_timer(0); + last = start; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *) (info->start[sect]); + if (intel) { + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + } else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *) (info->start[0]); + base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW) 0x00550055; /* unlock */ + base[0x0555] = (FPW) 0x00800080; /* erase mode */ + base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW) 0x00550055; /* unlock */ + *addr = (FPW) 0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay(1000); + + while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { + if ((now = get_timer(0)) - start > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + + flash_reset(info); /* reset to read mode */ + } + + printf(" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int +bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof (data), left -= sizeof (data) - bytes) { + + bytes = addr & (sizeof (data) - 1); + addr &= ~(sizeof (data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof (data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left) + data += *((uchar *) addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *) addr, data); + break; + case FLASH_MAN_INTEL: + res = write_word_intel(info, (FPWV *) addr, data); + break; + default: + /* unknown flash type, error! */ + printf("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/** + * write_buf: - Copy memory to flash. + * + * @param info: + * @param src: source of copy transaction + * @param addr: where to copy to + * @param cnt: number of bytes to copy + * + * @return error code + */ + +int +write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int l; + int i, rc; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* handle unaligned start bytes */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_word(info, (FPWV *)wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* handle word aligned part */ + while (cnt >= 2) { + /* data = *((vushort*)src); */ + data = *((FPW *) src); + if ((rc = write_word(info, (FPWV *)wp, data)) != 0) { + return (rc); + } + src += sizeof (FPW); + wp += sizeof (FPW); + cnt -= sizeof (FPW); + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_word(info, (FPWV *)wp, data); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int +write_word_amd(flash_info_t * info, FPWV * dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + base = (FPWV *) (info->start[0]); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW) 0x00550055; /* unlock */ + base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { + if (get_timer(0) - start > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW) 0x00F000F0; /* reset bank */ + printf("SHA timeout\n"); + res = 1; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for Intel FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int +write_word_intel(flash_info_t * info, FPWV * dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dest = (FPW) 0x00500050; /* clear status register */ + *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ + *dest = (FPW) 0x00400040; /* program setup */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW) 0x00B000B0; /* Suspend program */ + res = 1; + } + } + + if (res == 0 && (*dest & (FPW) 0x00100010)) + res = 1; /* write failed, time out error is close enough */ + + *dest = (FPW) 0x00500050; /* clear status register */ + *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ + + return (res); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int +flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F800C3B: + case FLASH_28F800C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + flash_reset(info); /* make sure in read mode */ + *addr = (FPW) 0x00600060L; /* lock command setup */ + if (prot) + *addr = (FPW) 0x00010001L; /* lock sector */ + else + *addr = (FPW) 0x00D000D0L; /* unlock sector */ + flash_reset(info); /* reset to read mode */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) 0x00900090; + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) 0x00010001; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) 0x00010001) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect(info); + break; + + case FLASH_AM640U: + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif diff --git a/board/mx1fs2/intel.h b/board/mx1fs2/intel.h new file mode 100644 index 0000000..8db5dd4 --- /dev/null +++ b/board/mx1fs2/intel.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2002 ETC s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Marcel Telka , 2002. + * + * Documentation: + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + */ + +#ifndef FLASH_INTEL_H +#define FLASH_INTEL_H + +#include + +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ + +#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ + +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ + +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ + +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ + +#define CFI_CHIP_INTEL_28F320J3A 0x0016 +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" +#define CFI_CHIP_INTEL_28F640J3A 0x0017 +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" +#define CFI_CHIP_INTEL_28F128J3A 0x0018 +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" + +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ + +#define CFI_CHIP_INTEL_28F640K3 0x8801 +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" +#define CFI_CHIP_INTEL_28F128K3 0x8802 +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" +#define CFI_CHIP_INTEL_28F256K3 0x8803 +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" +#define CFI_CHIP_INTEL_28F640K18 0x8805 +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" +#define CFI_CHIP_INTEL_28F128K18 0x8806 +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" +#define CFI_CHIP_INTEL_28F256K18 0x8807 +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" + +#endif /* FLASH_INTEL_H */ diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S new file mode 100644 index 0000000..8211beb --- /dev/null +++ b/board/mx1fs2/lowlevel_init.S @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2004 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + * 02111-1307, USA. + * + */ + +#include +#include +#include + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + +/* Change PERCLK1DIV to 14 ie 14+1 */ + ldr r0, =PCDR + ldr r1, =CFG_PCDR_VAL + str r1, [r0] + +/* set MCU PLL Control Register 0 */ + + ldr r0, =MPCTL0 + ldr r1, =CFG_MPCTL0_VAL + str r1, [r0] + +/* set MCU PLL Control Register 1 */ + + ldr r0, =MPCTL1 + ldr r1, =CFG_MPCTL1_VAL + str r1, [r0] + +/* set mpll restart bit */ + ldr r0, =CSCR + ldr r1, [r0] + orr r1,r1,#(1<<21) + str r1, [r0] + + mov r2,#0x10 +1: + mov r3,#0x2000 +2: + subs r3,r3,#1 + bne 2b + + subs r2,r2,#1 + bne 1b + +/* set System PLL Control Register 0 */ + + ldr r0, =SPCTL0 + ldr r1, =CFG_SPCTL0_VAL + str r1, [r0] + +/* set System PLL Control Register 1 */ + + ldr r0, =SPCTL1 + ldr r1, =CFG_SPCTL1_VAL + str r1, [r0] + +/* set spll restart bit */ + ldr r0, =CSCR + ldr r1, [r0] + orr r1,r1,#(1<<22) + str r1, [r0] + + mov r2,#0x10 +1: + mov r3,#0x2000 +2: + subs r3,r3,#1 + bne 2b + + subs r2,r2,#1 + bne 1b + + ldr r0, =CSCR + ldr r1, =CFG_CSCR_VAL + str r1, [r0] + + ldr r0, =GPCR + ldr r1, =CFG_GPCR_VAL + str r1, [r0] + +/* + * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon + * this..... + * + * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 + * register 1, this stops it using the output of the PLL and thus runs at the + * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never + * use the value set in the CM_OSC registers...regardless of what you set it + * too! Thus, although i thought i was running at 140MHz, i'm actually running + * at 40!.. + * + * Slapping this into my bootloader does the trick... + * + * MRC p15,0,r0,c1,c0,0 ; read core configuration register + * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode + * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration + * register + * + */ + MRC p15,0,r0,c1,c0,0 +/* ORR r0,r0,#0xC0000000 async mode */ +/* ORR r0,r0,#0x40000000 sync mode */ + ORR r0,r0,#0xC0000000 + MCR p15,0,r0,c1,c0,0 + + ldr r0, =GIUS(0) + ldr r1, =CFG_GIUS_A_VAL + str r1, [r0] + + ldr r0, =FMCR + ldr r1, =CFG_FMCR_VAL + str r1, [r0] + + ldr r0, =CS0U + ldr r1, =CFG_CS0U_VAL + str r1, [r0] + + ldr r0, =CS0L + ldr r1, =CFG_CS0L_VAL + str r1, [r0] + + ldr r0, =CS1U + ldr r1, =CFG_CS1U_VAL + str r1, [r0] + + ldr r0, =CS1L + ldr r1, =CFG_CS1L_VAL + str r1, [r0] + + ldr r0, =CS4U + ldr r1, =CFG_CS4U_VAL + str r1, [r0] + + ldr r0, =CS4L + ldr r1, =CFG_CS4L_VAL + str r1, [r0] + + ldr r0, =CS5U + ldr r1, =CFG_CS5U_VAL + str r1, [r0] + + ldr r0, =CS5L + ldr r1, =CFG_CS5L_VAL + str r1, [r0] + +/* SDRAM Setup */ + + ldr r1,=0x00221000 /* adr of SDCTRL0 */ + ldr r0,=0x92120200 + str r0,[r1,#0] /* put in precharge command mode */ + ldr r2,=0x08200000 /* adr for precharge cmd */ + ldr r0,[r2,#0] /* precharge */ + ldr r0,=0xA2120200 + ldr r2,=0x08000000 /* start of SDRAM */ + str r0,[r1,#0] /* put in auto-refresh mode */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,=0xB2120200 + ldr r2,=0x08111800 + str r0,[r1,#0] /* setup for mode register of SDRAM */ + ldr r0,[r2,#0] /* program mode register */ + ldr r0,=0x82124267 + str r0,[r1,#0] /* back to normal operation */ + + mov pc,r10 diff --git a/board/mx1fs2/mx1fs2.c b/board/mx1fs2/mx1fs2.c new file mode 100644 index 0000000..9e7a06c --- /dev/null +++ b/board/mx1fs2/mx1fs2.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2004 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include + +#include + +#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) + +extern void imx_gpio_mode(int gpio_mode); + +static void logo_init(void) +{ + imx_gpio_mode(PD15_PF_LD0); + imx_gpio_mode(PD16_PF_LD1); + imx_gpio_mode(PD17_PF_LD2); + imx_gpio_mode(PD18_PF_LD3); + imx_gpio_mode(PD19_PF_LD4); + imx_gpio_mode(PD20_PF_LD5); + imx_gpio_mode(PD21_PF_LD6); + imx_gpio_mode(PD22_PF_LD7); + imx_gpio_mode(PD23_PF_LD8); + imx_gpio_mode(PD24_PF_LD9); + imx_gpio_mode(PD25_PF_LD10); + imx_gpio_mode(PD26_PF_LD11); + imx_gpio_mode(PD27_PF_LD12); + imx_gpio_mode(PD28_PF_LD13); + imx_gpio_mode(PD29_PF_LD14); + imx_gpio_mode(PD30_PF_LD15); + imx_gpio_mode(PD14_PF_FLM_VSYNC); + imx_gpio_mode(PD13_PF_LP_HSYNC); + imx_gpio_mode(PD6_PF_LSCLK); + imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO); + imx_gpio_mode(PD11_PF_CONTRAST); + imx_gpio_mode(PD10_PF_SPL_SPR); + + LCDC_RMCR = 0x00000000; + LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5); + LCDC_HCR = HCR_H_WIDTH(2); + LCDC_VCR = VCR_V_WIDTH(2); + + LCDC_PWMR = 0x00000380; /* contrast to 0x80 middle (is best !!!) */ + LCDC_SSA = 0x10040000; /* image in flash */ + + LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240); /* screen size */ + + LCDC_VPW = 0x000000A0; /* Virtual Page Width Register */ + LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */ + + /* disable Cursor */ + LCDC_CPOS = 0x00000000; + + /* fixed burst length */ + LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2); + + /* enable LCD */ + DR(3) |= 0x00001000; + LCDC_RMCR = RMCR_LCDC_EN; + +} + +int +board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = MACH_TYPE_MX1FS2; + gd->bd->bi_boot_params = 0x08000100; +serial_init(); + logo_init(); + return 0; +} + +int +dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#if ( CONFIG_NR_DRAM_BANKS > 0 ) + gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1; + gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE; +#endif + return 0; +} + +/** + * show_boot_progress: - indicate state of the boot process + * + * @param status: Status number - see README for details. + * + */ + +void +show_boot_progress(int status) +{ + /* We use this as a hook to disable serial ports just before booting + * This way we suppress the "uncompressing linux..." message + */ +#ifdef CONFIG_SILENT_CONSOLE + if( status == 8) { + if( getenv("silent") != NULL ) { + *(volatile unsigned long *)0x206080 &= ~1; + *(volatile unsigned long *)0x207080 &= ~1; + } + } +#endif + return; +} diff --git a/board/mx1fs2/u-boot.lds b/board/mx1fs2/u-boot.lds new file mode 100644 index 0000000..1d1669c --- /dev/null +++ b/board/mx1fs2/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/nc650/Makefile b/board/nc650/Makefile new file mode 100644 index 0000000..a4dd85f --- /dev/null +++ b/board/nc650/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/nc650/config.mk b/board/nc650/config.mk new file mode 100644 index 0000000..fa8ba31 --- /dev/null +++ b/board/nc650/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# NC650 board +# + +TEXT_BASE = 0x40700000 diff --git a/board/nc650/flash.c b/board/nc650/flash.c new file mode 100644 index 0000000..ce2f83b --- /dev/null +++ b/board/nc650/flash.c @@ -0,0 +1,542 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#undef DEBUG + +#include +#include + +#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ +#define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH8 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#elif FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#else /* FLASH_PORT_WIDTH8 */ +#define FLASH_PORT_WIDTH uchar +#define FLASH_PORT_WIDTHV vu_char +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPWV * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; +#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ + int scy, trlx, flash_or_timing, clk_diff; + + DECLARE_GLOBAL_DATA_PTR; + + scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; + if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { + trlx = OR_TRLX; + scy *= 2; + } else + trlx = 0; + + /* We assume that each 10MHz of bus clock require 1-clk SCY + * adjustment. + */ + clk_diff = (gd->bus_clk / 1000000) - 50; + + /* We need proper rounding here. This is what the "+5" and "-5" + * are here for. + */ + if (clk_diff >= 0) + scy += (clk_diff + 5) / 10; + else + scy += (clk_diff - 5) / 10; + + /* For bus frequencies above 50MHz, we want to use relaxed + * timing (OR_TRLX). + */ + if (gd->bus_clk >= 50000000) + trlx = OR_TRLX; + else + trlx = 0; + + if (trlx) + scy /= 2; + + if (scy > 0xf) + scy = 0xf; + if (scy < 1) + scy = 1; + + flash_or_timing = (scy << 4) | trlx | + (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); +#endif + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + /* Remap FLASH according to real size */ +#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); +#else + memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK); +#endif + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000); + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: + printf ("28F320J3A\n"); + break; + case FLASH_28F640J3A: + printf ("28F640J3A\n"); + break; + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (FPWV * addr, flash_info_t * info) +{ + FPW value; + + addr[0] = (FPW) 0x00900090; + + value = addr[0]; + + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value) { + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + +#ifdef FLASH_PORT_WIDTH8 + value = addr[2]; /* device ID */ +#else + value = addr[1]; /* device ID */ +#endif + + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value) { + case (FPW) INTEL_ID_28F320J3A: + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (FPW) INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + + int i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#elif defined(FLASH_PORT_WIDTH32) + wp = (addr & ~3); + port_width = 4; +#else + wp = addr; + port_width = 1; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c new file mode 100644 index 0000000..fe96b93 --- /dev/null +++ b/board/nc650/nc650.c @@ -0,0 +1,253 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Memory Controller Using + * + * CS0 - Flash memory (0x40000000) + * CS3 - SDRAM (0x00000000} + */ + +/* ------------------------------------------------------------------------- */ + +#define _not_used_ 0xffffffff + +const uint sdram_table[] = { + /* single read. (offset 0 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, + 0x1ff77c47, + + /* MRS initialization (offset 5) */ + + 0x1ff77c34, 0xefeabc34, 0x1fb57c35, + + /* burst read. (offset 8 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* single write. (offset 18 in upm RAM) */ + 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* burst write. (offset 20 in upm RAM) */ + 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, + 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* refresh. (offset 30 in upm RAM) */ + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* exception. (offset 3c in upm RAM) */ + 0x7ffffc07, _not_used_, _not_used_, _not_used_ +}; + +const uint nand_flash_table[] = { + /* single read. (offset 0 in upm RAM) */ + 0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04, + 0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05, + + /* burst read. (offset 8 in upm RAM) */ + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + + /* single write. (offset 18 in upm RAM) */ + 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04, + 0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05, + + /* burst write. (offset 20 in upm RAM) */ + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + + /* refresh. (offset 30 in upm RAM) */ + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + + /* exception. (offset 3c in upm RAM) */ + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05 +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: NC650\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size8, size9; + long int size_b0 = 0; + unsigned long reg; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 1 to the SDRAM bank at + * preliminary address - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80006105; /* SDRAM bank 0 */ + udelay (200); + memctl->memc_mcr = 0x80006230; /* SDRAM bank 0 - execute twice */ + udelay (200); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + if (size8 < size9) { + size_b0 = size9; + } else { + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); + } + + /* + * Adjust refresh rate depending on SDRAM type, both banks. + * For types > 128 MBit leave it at the current (fast) rate + */ + if ((size_b0 < 0x02000000)) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping + */ + + memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + + udelay (10000); + + /* Configure UPMB for NAND flash access */ + upmconfig (UPMB, (uint *) nand_flash_table, + sizeof (nand_flash_table) / sizeof (uint)); + + memctl->memc_mbmr = CFG_MBMR_NAND; + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +void nand_init(void) +{ + extern unsigned long nand_probe(unsigned long physadr); + + unsigned long totlen = nand_probe(CFG_NAND_BASE); + + printf ("%4lu MB\n", totlen >> 20); +} +#endif diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds new file mode 100644 index 0000000..ca44918 --- /dev/null +++ b/board/nc650/u-boot.lds @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/nc650/u-boot.lds.debug b/board/nc650/u-boot.lds.debug new file mode 100644 index 0000000..2228a20 --- /dev/null +++ b/board/nc650/u-boot.lds.debug @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netphone/Makefile b/board/netphone/Makefile new file mode 100644 index 0000000..b3c1797 --- /dev/null +++ b/board/netphone/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o phone_console.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/netphone/config.mk b/board/netphone/config.mk new file mode 100644 index 0000000..8497ebc --- /dev/null +++ b/board/netphone/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# netVia Boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/netphone/flash.c b/board/netphone/flash.c new file mode 100644 index 0000000..0c81140 --- /dev/null +++ b/board/netphone/flash.c @@ -0,0 +1,529 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_byte(flash_info_t * info, ulong dest, uchar data); +static void flash_get_offsets(ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size; +#if CONFIG_NETPHONE_VERSION == 2 + unsigned long size1; +#endif + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size, size << 20); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + flash_info[0].size = size; + +#if CONFIG_NETPHONE_VERSION == 2 + size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]); + if (size1 > 0) { + if (flash_info[1].flash_id == FLASH_UNKNOWN) + printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20); + + /* Remap FLASH according to real size */ + memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000); + memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK)); + + /* Re-do sizing to get full correct info */ + size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]); + + flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]); + + size += size1; + } else + memctl->memc_br4 &= ~BR_V; +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_MX: + printf("MXIC "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + short i; + uchar mid; + uchar pid; + vu_char *caddr = (vu_char *) addr; + ulong base = (ulong) addr; + + /* Write auto select command: read Manufacturer ID */ + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0x90; + + mid = caddr[0]; + switch (mid) { + case (AMD_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_FUJ; + break; + case (MX_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_MX; + break; + case (STM_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + pid = caddr[1]; /* device ID */ + switch (pid) { + case (AMD_ID_LV400T & 0xFF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV400B & 0xFF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV800T & 0xFF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800B & 0xFF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV160T & 0xFF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160B & 0xFF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + + case (STM_ID_M29W040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & 0xFF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV320B & 0xFF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + printf(" "); + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection: D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (vu_char *) info->start[0]; + + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0xF0; + + udelay(20000); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *) (info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer(0); + last = start; + addr = (vu_char *) (info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_char *) info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + + while (cnt > 0) { + if ((rc = write_byte(info, addr++, *src++)) != 0) { + return (rc); + } + --cnt; + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte(flash_info_t * info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *) (info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *) dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((vu_char *) dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c new file mode 100644 index 0000000..dd03e4b --- /dev/null +++ b/board/netphone/netphone.c @@ -0,0 +1,722 @@ +/* + * (C) Copyright 2000-2004 + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#include +#include +#include +#include + +#include "mpc8xx.h" + +#ifdef CONFIG_HW_WATCHDOG +#include +#endif + +int fec8xx_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +int fec8xx_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); + +/****************************************************************/ + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +/****************************************************************/ + +/* + * Check Board Identity: + * + * Return 1 always. + */ + +int checkboard(void) +{ + printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION); + return (0); +} + +/****************************************************************/ + +#define _NOT_USED_ 0xFFFFFFFF + +/****************************************************************/ + +#define CS_0000 0x00000000 +#define CS_0001 0x10000000 +#define CS_0010 0x20000000 +#define CS_0011 0x30000000 +#define CS_0100 0x40000000 +#define CS_0101 0x50000000 +#define CS_0110 0x60000000 +#define CS_0111 0x70000000 +#define CS_1000 0x80000000 +#define CS_1001 0x90000000 +#define CS_1010 0xA0000000 +#define CS_1011 0xB0000000 +#define CS_1100 0xC0000000 +#define CS_1101 0xD0000000 +#define CS_1110 0xE0000000 +#define CS_1111 0xF0000000 + +#define BS_0000 0x00000000 +#define BS_0001 0x01000000 +#define BS_0010 0x02000000 +#define BS_0011 0x03000000 +#define BS_0100 0x04000000 +#define BS_0101 0x05000000 +#define BS_0110 0x06000000 +#define BS_0111 0x07000000 +#define BS_1000 0x08000000 +#define BS_1001 0x09000000 +#define BS_1010 0x0A000000 +#define BS_1011 0x0B000000 +#define BS_1100 0x0C000000 +#define BS_1101 0x0D000000 +#define BS_1110 0x0E000000 +#define BS_1111 0x0F000000 + +#define GPL0_AAAA 0x00000000 +#define GPL0_AAA0 0x00200000 +#define GPL0_AAA1 0x00300000 +#define GPL0_000A 0x00800000 +#define GPL0_0000 0x00A00000 +#define GPL0_0001 0x00B00000 +#define GPL0_111A 0x00C00000 +#define GPL0_1110 0x00E00000 +#define GPL0_1111 0x00F00000 + +#define GPL1_0000 0x00000000 +#define GPL1_0001 0x00040000 +#define GPL1_1110 0x00080000 +#define GPL1_1111 0x000C0000 + +#define GPL2_0000 0x00000000 +#define GPL2_0001 0x00010000 +#define GPL2_1110 0x00020000 +#define GPL2_1111 0x00030000 + +#define GPL3_0000 0x00000000 +#define GPL3_0001 0x00004000 +#define GPL3_1110 0x00008000 +#define GPL3_1111 0x0000C000 + +#define GPL4_0000 0x00000000 +#define GPL4_0001 0x00001000 +#define GPL4_1110 0x00002000 +#define GPL4_1111 0x00003000 + +#define GPL5_0000 0x00000000 +#define GPL5_0001 0x00000400 +#define GPL5_1110 0x00000800 +#define GPL5_1111 0x00000C00 +#define LOOP 0x00000080 + +#define EXEN 0x00000040 + +#define AMX_COL 0x00000000 +#define AMX_ROW 0x00000020 +#define AMX_MAR 0x00000030 + +#define NA 0x00000008 + +#define UTA 0x00000004 + +#define TODT 0x00000002 + +#define LAST 0x00000001 + +#define A10_AAAA GPL0_AAAA +#define A10_AAA0 GPL0_AAA0 +#define A10_AAA1 GPL0_AAA1 +#define A10_000A GPL0_000A +#define A10_0000 GPL0_0000 +#define A10_0001 GPL0_0001 +#define A10_111A GPL0_111A +#define A10_1110 GPL0_1110 +#define A10_1111 GPL0_1111 + +#define RAS_0000 GPL1_0000 +#define RAS_0001 GPL1_0001 +#define RAS_1110 GPL1_1110 +#define RAS_1111 GPL1_1111 + +#define CAS_0000 GPL2_0000 +#define CAS_0001 GPL2_0001 +#define CAS_1110 GPL2_1110 +#define CAS_1111 GPL2_1111 + +#define WE_0000 GPL3_0000 +#define WE_0001 GPL3_0001 +#define WE_1110 GPL3_1110 +#define WE_1111 GPL3_1111 + +/* #define CAS_LATENCY 3 */ +#define CAS_LATENCY 2 + +const uint sdram_table[0x40] = { + +#if CAS_LATENCY == 3 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, +#endif + +#if CAS_LATENCY == 2 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + +#endif + + /* UPT */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, +}; + +#if CONFIG_NETPHONE_VERSION == 2 +static const uint nandcs_table[0x40] = { + /* RSS */ + CS_1000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1110 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111, + CS_0000 | GPL4_0001 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ + + /* RBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_1000 | GPL4_1111 | GPL5_1110 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0001 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, + + /* WBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* UPT */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 , + CS_0001 | LAST, +}; +#endif + +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ +/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ +#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) + +/* 8 */ +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +void check_ram(unsigned int addr, unsigned int size) +{ + unsigned int i, j, v, vv; + volatile unsigned int *p; + unsigned int pv; + + p = (unsigned int *)addr; + pv = (unsigned int)p; + for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) + *p++ = pv; + + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + v = (unsigned int)p; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + p++; + } + + for (j = 0; j < 5; j++) { + switch (j) { + case 0: v = 0x00000000; break; + case 1: v = 0xffffffff; break; + case 2: v = 0x55555555; break; + case 3: v = 0xaaaaaaaa; break; + default:v = 0xdeadbeef; break; + } + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + *p = v; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + *p = ~v; + p++; + } + } +} + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + + upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = MPTPR_PTP_DIV8; + + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initialisation sequence */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ + udelay(1); + + memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ + + udelay(10000); + + { + u32 d1, d2; + + d1 = 0xAA55AA55; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + + d1 = 0x55AA55AA; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + } + + size = get_ram_size((long *)0, SDRAM_MAX_SIZE); + + if (size == 0) { + printf("SIZE is zero: LOOP on 0\n"); + for (;;) { + *(volatile u32 *)0 = 0; + (void)*(volatile u32 *)0; + } + } + + return size; +} + +/* ------------------------------------------------------------------------- */ + +void reset_phys(void) +{ + int phyno; + unsigned short v; + + udelay(10000); + /* reset the damn phys */ + mii_init(); + + for (phyno = 0; phyno < 32; ++phyno) { + fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); + if (v == 0xFFFF) + continue; + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); + udelay(10000); + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, + PHY_BMCR_RESET | PHY_BMCR_AUTON); + udelay(10000); + } +} + +/* ------------------------------------------------------------------------- */ + +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + +/* bits that can have a special purpose or can be configured as inputs/outputs */ +#define PA_GP_INMASK 0 +#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) +#define PA_SP_MASK 0 +#define PA_ODR_VAL 0 +#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) +#define PA_SP_DIRVAL 0 + +#define PB_GP_INMASK _B(28) +#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) +#define PB_SP_MASK (_BR(22, 25)) +#define PB_ODR_VAL 0 +#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) +#define PB_SP_DIRVAL 0 + +#if CONFIG_NETPHONE_VERSION == 1 +#define PC_GP_INMASK _BW(12) +#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) +#elif CONFIG_NETPHONE_VERSION == 2 +#define PC_GP_INMASK (_BW(13) | _BW(15)) +#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) +#endif +#define PC_SP_MASK 0 +#define PC_SOVAL 0 +#define PC_INTVAL 0 +#define PC_GP_OUTVAL (_BW(10) | _BW(11)) +#define PC_SP_DIRVAL 0 + +#if CONFIG_NETPHONE_VERSION == 1 +#define PE_GP_INMASK _B(31) +#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) +#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) +#elif CONFIG_NETPHONE_VERSION == 2 +#define PE_GP_INMASK _BR(28, 31) +#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) +#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) +#endif +#define PE_SP_MASK 0 +#define PE_ODR_VAL 0 +#define PE_SP_DIRVAL 0 + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* NAND chip select */ +#if CONFIG_NETPHONE_VERSION == 1 + memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); + memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); +#elif CONFIG_NETPHONE_VERSION == 2 + upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); + memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); + memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); + memctl->memc_mamr = 0; /* all clear */ +#endif + + /* DSP chip select */ + memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); + memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); + +#if CONFIG_NETPHONE_VERSION == 1 + memctl->memc_br4 &= ~BR_V; +#endif + memctl->memc_br5 &= ~BR_V; + memctl->memc_br6 &= ~BR_V; + memctl->memc_br7 &= ~BR_V; + + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + cpm->cp_pedat = PE_GP_OUTVAL; + cpm->cp_peodr = PE_ODR_VAL; + cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; + cpm->cp_pepar = PE_SP_MASK; + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include + +extern ulong nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + unsigned long totlen; + + totlen = nand_probe(CFG_NAND_BASE); + printf ("%4lu MB\n", totlen >> 20); +} +#endif + +#ifdef CONFIG_HW_WATCHDOG + +void hw_watchdog_reset(void) +{ + /* XXX add here the really funky stuff */ +} + +#endif + +#ifdef CONFIG_SHOW_ACTIVITY + +static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */ + +/* called from timer interrupt every 1/CFG_HZ sec */ +void board_show_activity(ulong timestamp) +{ + if (left_to_poll > -PHONE_CONSOLE_POLL_HZ) + --left_to_poll; +} + +extern void phone_console_do_poll(void); + +static void do_poll(void) +{ + unsigned int base; + + while (left_to_poll <= 0) { + phone_console_do_poll(); + base = left_to_poll + PHONE_CONSOLE_POLL_HZ; + do { + left_to_poll = base; + } while (base != left_to_poll); + } +} + +/* called when looping */ +void show_activity(int arg) +{ + do_poll(); +} + +#endif + +#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + /* printf("overwrite_console called\n"); */ + return 0; +} +#endif + +extern int drv_phone_init(void); +extern int drv_phone_use_me(void); +extern int drv_phone_is_idle(void); + +int misc_init_r(void) +{ + return drv_phone_init(); +} + +int last_stage_init(void) +{ + int i; + +#if CONFIG_NETPHONE_VERSION == 2 + /* assert peripheral reset */ + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); + for (i = 0; i < 10; i++) + udelay(1000); + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12); +#endif + reset_phys(); + + /* check in order to enable the local console */ + left_to_poll = PHONE_CONSOLE_POLL_HZ; + i = CFG_HZ * 2; + while (i > 0) { + + if (tstc()) { + getc(); + break; + } + + do_poll(); + + if (drv_phone_use_me()) { + status_led_set(0, STATUS_LED_ON); + while (!drv_phone_is_idle()) { + do_poll(); + udelay(1000000 / CFG_HZ); + } + + console_assign(stdin, "phone"); + console_assign(stdout, "phone"); + console_assign(stderr, "phone"); + setenv("bootdelay", "-1"); + break; + } + + udelay(1000000 / CFG_HZ); + i--; + left_to_poll--; + } + left_to_poll = PHONE_CONSOLE_POLL_HZ; + + return 0; +} diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c new file mode 100644 index 0000000..408ada0 --- /dev/null +++ b/board/netphone/phone_console.c @@ -0,0 +1,1144 @@ +/* + * (C) Copyright 2004 Intracom S.A. + * Pantelis Antoniou + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * phone_console.c + * + * A phone based console + * + * Virtual display of 80x24 characters. + * The actual display is much smaller and panned to show the virtual one. + * Input is made by a numeric keypad utilizing the input method of + * mobile phones. Sorry no T9 lexicons... + * + */ + +#include + +#include +#include +#include + +#include + +/*************************************************************************************************/ + +#define ROWS 24 +#define COLS 80 + +#define REFRESH_HZ (CFG_HZ/50) /* refresh every 20ms */ +#define BLINK_HZ (CFG_HZ/2) /* cursor blink every 500ms */ + +/*************************************************************************************************/ + +#define DISPLAY_BACKLIT_PORT ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat +#define DISPLAY_BACKLIT_MASK 0x0010 + +/*************************************************************************************************/ + +#define KP_STABLE_HZ (CFG_HZ/100) /* stable for 10ms */ +#define KP_REPEAT_DELAY_HZ (CFG_HZ/4) /* delay before repeat 250ms */ +#define KP_REPEAT_HZ (CFG_HZ/20) /* repeat every 50ms */ +#define KP_FORCE_DELAY_HZ (CFG_HZ/2) /* key was force pressed */ +#define KP_IDLE_DELAY_HZ (CFG_HZ/2) /* key was released and idle */ + +#if CONFIG_NETPHONE_VERSION == 1 +#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define KP_SPI_RXD_MASK 0x0008 + +#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define KP_SPI_TXD_MASK 0x0004 + +#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define KP_SPI_CLK_MASK 0x0001 +#elif CONFIG_NETPHONE_VERSION == 2 +#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define KP_SPI_RXD_MASK 0x00000008 + +#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define KP_SPI_TXD_MASK 0x00000004 + +#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define KP_SPI_CLK_MASK 0x00000002 +#endif + +#define KP_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) +#define KP_CS_MASK 0x00000010 + +#define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK) + +#define KP_SPI_TXD(x) \ + do { \ + if (x) \ + KP_SPI_TXD_PORT |= KP_SPI_TXD_MASK; \ + else \ + KP_SPI_TXD_PORT &= ~KP_SPI_TXD_MASK; \ + } while(0) + +#define KP_SPI_CLK(x) \ + do { \ + if (x) \ + KP_SPI_CLK_PORT |= KP_SPI_CLK_MASK; \ + else \ + KP_SPI_CLK_PORT &= ~KP_SPI_CLK_MASK; \ + } while(0) + +#define KP_SPI_CLK_TOGGLE() (KP_SPI_CLK_PORT ^= KP_SPI_CLK_MASK) + +#define KP_SPI_BIT_DELAY() /* no delay */ + +#define KP_CS(x) \ + do { \ + if (x) \ + KP_CS_PORT |= KP_CS_MASK; \ + else \ + KP_CS_PORT &= ~KP_CS_MASK; \ + } while(0) + +#define KP_ROWS 7 +#define KP_COLS 4 + +#define KP_ROWS_MASK ((1 << KP_ROWS) - 1) +#define KP_COLS_MASK ((1 << KP_COLS) - 1) + +#define SCAN 0 +#define SCAN_FILTER 1 +#define SCAN_COL 2 +#define SCAN_COL_FILTER 3 +#define PRESSED 4 + +#define KP_F1 0 /* leftmost dot (tab) */ +#define KP_F2 1 /* middle left dot */ +#define KP_F3 2 /* up */ +#define KP_F4 3 /* middle right dot */ +#define KP_F5 4 /* rightmost dot */ +#define KP_F6 5 /* C */ +#define KP_F7 6 /* left */ +#define KP_F8 7 /* down */ +#define KP_F9 8 /* right */ +#define KP_F10 9 /* enter */ +#define KP_F11 10 /* R */ +#define KP_F12 11 /* save */ +#define KP_F13 12 /* redial */ +#define KP_F14 13 /* speaker */ +#define KP_F15 14 /* unused */ +#define KP_F16 15 /* unused */ + +#define KP_RELEASE -1 /* key depressed */ +#define KP_FORCE -2 /* key was pressed for more than force hz */ +#define KP_IDLE -3 /* key was released and idle */ + +#define KP_1 '1' +#define KP_2 '2' +#define KP_3 '3' +#define KP_4 '4' +#define KP_5 '5' +#define KP_6 '6' +#define KP_7 '7' +#define KP_8 '8' +#define KP_9 '9' +#define KP_0 '0' +#define KP_STAR '*' +#define KP_HASH '#' + +/*************************************************************************************************/ + +static int curs_disabled; +static int curs_col, curs_row; +static int disp_col, disp_row; + +static int width, height; + +/* the simulated vty buffer */ +static char vty_buf[ROWS * COLS]; +static char last_visible_buf[ROWS * COLS]; /* worst case */ +static char *last_visible_curs_ptr; +static int last_visible_curs_rev; +static int blinked_state; +static int last_input_mode; +static int refresh_time; +static int blink_time; +static char last_fast_punct; + +/*************************************************************************************************/ + +#define IM_SMALL 0 +#define IM_CAPITAL 1 +#define IM_NUMBER 2 + +static int input_mode; +static char fast_punct; +static int tab_indicator; +static const char *fast_punct_list = ",.:;*"; + +static const char *input_mode_txt[] = { "abc", "ABC", "123" }; + +static const char *punct = ".,!;?'\"-()@/:_+&%*=<>$[]{}\\~^#|"; +static const char *whspace = " 0\n"; +/* per mode character select (for 2-9) */ +static const char *digits_sel[2][8] = { + { /* small */ + "abc2", /* 2 */ + "def3", /* 3 */ + "ghi4", /* 4 */ + "jkl5", /* 5 */ + "mno6", /* 6 */ + "pqrs7", /* 7 */ + "tuv8", /* 8 */ + "wxyz9", /* 9 */ + }, { /* capital */ + "ABC2", /* 2 */ + "DEF3", /* 3 */ + "GHI4", /* 4 */ + "JKL5", /* 5 */ + "MNO6", /* 6 */ + "PQRS7", /* 7 */ + "TUV8", /* 8 */ + "WXYZ9", /* 9 */ + } +}; + +/*****************************************************************************/ + +static void update(void); +static void ensure_visible(int col, int row, int dx, int dy); + +static void console_init(void) +{ + curs_disabled = 0; + curs_col = 0; + curs_row = 0; + + disp_col = 0; + disp_row = 0; + + input_mode = IM_SMALL; + fast_punct = ','; + last_fast_punct = '\0'; + refresh_time = REFRESH_HZ; + blink_time = BLINK_HZ; + + memset(vty_buf, ' ', sizeof(vty_buf)); + + memset(last_visible_buf, ' ', sizeof(last_visible_buf)); + last_visible_curs_ptr = NULL; + last_input_mode = -1; + last_visible_curs_rev = 0; + + blinked_state = 0; + + sed156x_init(); + width = sed156x_text_width; + height = sed156x_text_height - 1; + + tab_indicator = 0; +} + +/*****************************************************************************/ + +void phone_putc(const char c); + +/*****************************************************************************/ + +static int queued_char = -1; +static int enabled = 0; + +/*****************************************************************************/ + +/* flush buffers */ +int phone_start(void) +{ + console_init(); + + update(); + sed156x_sync(); + + enabled = 1; + queued_char = 'U' - '@'; + + /* backlit on */ + DISPLAY_BACKLIT_PORT &= ~DISPLAY_BACKLIT_MASK; + + return 0; +} + +int phone_stop(void) +{ + enabled = 0; + + sed156x_clear(); + sed156x_sync(); + + /* backlit off */ + DISPLAY_BACKLIT_PORT |= DISPLAY_BACKLIT_MASK; + + return 0; +} + +void phone_puts(const char *s) +{ + int count = strlen(s); + + while (count--) + phone_putc(*s++); +} + +int phone_tstc(void) +{ + return queued_char >= 0 ? 1 : 0; +} + +int phone_getc(void) +{ + int r; + + if (queued_char < 0) + return -1; + + r = queued_char; + queued_char = -1; + + return r; +} + +/*****************************************************************************/ + +int drv_phone_init(void) +{ + device_t console_dev; + + console_init(); + + memset(&console_dev, 0, sizeof(console_dev)); + strcpy(console_dev.name, "phone"); + console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ + console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + console_dev.start = phone_start; + console_dev.stop = phone_stop; + console_dev.putc = phone_putc; /* 'putc' function */ + console_dev.puts = phone_puts; /* 'puts' function */ + console_dev.tstc = phone_tstc; /* 'tstc' function */ + console_dev.getc = phone_getc; /* 'getc' function */ + + if (device_register(&console_dev) == 0) + return 1; + + return 0; +} + +static int use_me; + +int drv_phone_use_me(void) +{ + return use_me; +} + +static void kp_do_poll(void); + +void phone_console_do_poll(void) +{ + int i, x, y; + + kp_do_poll(); + + if (enabled) { + /* do the blink */ + blink_time -= PHONE_CONSOLE_POLL_HZ; + if (blink_time <= 0) { + blink_time += BLINK_HZ; + if (last_visible_curs_ptr) { + i = last_visible_curs_ptr - last_visible_buf; + x = i % width; y = i / width; + sed156x_reverse_at(x, y, 1); + last_visible_curs_rev ^= 1; + } + } + + /* do the refresh */ + refresh_time -= PHONE_CONSOLE_POLL_HZ; + if (refresh_time <= 0) { + refresh_time += REFRESH_HZ; + sed156x_sync(); + } + } + +} + +static int last_scancode = -1; +static int forced_scancode = 0; +static int input_state = -1; +static int input_scancode = -1; +static int input_selected_char = -1; +static char input_covered_char; + +static void putchar_at_cursor(char c) +{ + vty_buf[curs_row * COLS + curs_col] = c; + ensure_visible(curs_col, curs_row, 1, 1); +} + +static char getchar_at_cursor(void) +{ + return vty_buf[curs_row * COLS + curs_col]; +} + +static void queue_input_char(char c) +{ + if (c <= 0) + return; + + queued_char = c; +} + +static void terminate_input(void) +{ + if (input_state < 0) + return; + + if (input_selected_char >= 0) + queue_input_char(input_selected_char); + + input_state = -1; + input_selected_char = -1; + putchar_at_cursor(input_covered_char); + + curs_disabled = 0; + blink_time = BLINK_HZ; + update(); +} + +static void handle_enabled_scancode(int scancode) +{ + char c; + int new_disp_col, new_disp_row; + const char *sel; + + + switch (scancode) { + + /* key was released */ + case KP_RELEASE: + forced_scancode = 0; + break; + + /* key was forced */ + case KP_FORCE: + + switch (last_scancode) { + case '#': + if (input_mode == IM_NUMBER) { + input_mode = IM_CAPITAL; + /* queue backspace to erase # */ + queue_input_char('\b'); + } else { + input_mode = IM_NUMBER; + fast_punct = '*'; + } + update(); + break; + + case '0': case '1': + case '2': case '3': case '4': case '5': + case '6': case '7': case '8': case '9': + + if (input_state < 0) + break; + + input_selected_char = last_scancode; + putchar_at_cursor((char)input_selected_char); + terminate_input(); + + break; + + default: + break; + } + + break; + + /* release and idle */ + case KP_IDLE: + input_scancode = -1; + if (input_state < 0) + break; + terminate_input(); + break; + + /* change input mode */ + case '#': + if (last_scancode == '#') /* no repeat */ + break; + + if (input_mode == IM_NUMBER) { + input_scancode = scancode; + input_state = 0; + input_selected_char = scancode; + input_covered_char = getchar_at_cursor(); + putchar_at_cursor((char)input_selected_char); + terminate_input(); + break; + } + + if (input_mode == IM_SMALL) + input_mode = IM_CAPITAL; + else + input_mode = IM_SMALL; + + update(); + break; + + case '*': + /* no repeat */ + if (last_scancode == scancode) + break; + + if (input_state >= 0) + terminate_input(); + + input_scancode = fast_punct; + input_state = 0; + input_selected_char = input_scancode; + input_covered_char = getchar_at_cursor(); + putchar_at_cursor((char)input_selected_char); + terminate_input(); + + break; + + case '0': case '1': + case '2': case '3': case '4': case '5': + case '6': case '7': case '8': case '9': + + /* no repeat */ + if (last_scancode == scancode) + break; + + if (input_mode == IM_NUMBER) { + input_scancode = scancode; + input_state = 0; + input_selected_char = scancode; + input_covered_char = getchar_at_cursor(); + putchar_at_cursor((char)input_selected_char); + terminate_input(); + break; + } + + if (input_state >= 0 && input_scancode != scancode) + terminate_input(); + + if (input_state < 0) { + curs_disabled = 1; + input_scancode = scancode; + input_state = 0; + input_covered_char = getchar_at_cursor(); + } else + input_state++; + + if (scancode == '0') + sel = whspace; + else if (scancode == '1') + sel = punct; + else + sel = digits_sel[input_mode][scancode - '2']; + c = *(sel + input_state); + if (c == '\0') { + input_state = 0; + c = *sel; + } + + input_selected_char = (int)c; + putchar_at_cursor((char)input_selected_char); + update(); + + break; + + /* move visible display */ + case KP_F3: case KP_F8: case KP_F7: case KP_F9: + + new_disp_col = disp_col; + new_disp_row = disp_row; + + switch (scancode) { + /* up */ + case KP_F3: + if (new_disp_row <= 0) + break; + new_disp_row--; + break; + + /* down */ + case KP_F8: + if (new_disp_row >= ROWS - height) + break; + new_disp_row++; + break; + + /* left */ + case KP_F7: + if (new_disp_col <= 0) + break; + new_disp_col--; + break; + + /* right */ + case KP_F9: + if (new_disp_col >= COLS - width) + break; + new_disp_col++; + break; + } + + /* no change? */ + if (disp_col == new_disp_col && disp_row == new_disp_row) + break; + + disp_col = new_disp_col; + disp_row = new_disp_row; + update(); + + break; + + case KP_F6: /* backspace */ + /* inputing something; no backspace sent, just cancel input */ + if (input_state >= 0) { + input_selected_char = -1; /* cancel */ + terminate_input(); + break; + } + queue_input_char('\b'); + break; + + case KP_F10: /* enter */ + /* inputing something; first cancel input */ + if (input_state >= 0) + terminate_input(); + queue_input_char('\r'); + break; + + case KP_F11: /* R -> Ctrl-C (abort) */ + if (input_state >= 0) + terminate_input(); + queue_input_char('C' - 'Q'); /* ctrl-c */ + break; + + case KP_F5: /* F% -> Ctrl-U (clear line) */ + if (input_state >= 0) + terminate_input(); + queue_input_char('U' - 'Q'); /* ctrl-c */ + break; + + + case KP_F1: /* tab */ + /* inputing something; first cancel input */ + if (input_state >= 0) + terminate_input(); + queue_input_char('\t'); + break; + + case KP_F2: /* change fast punct */ + sel = strchr(fast_punct_list, fast_punct); + if (sel == NULL) + sel = &fast_punct_list[0]; + sel++; + if (*sel == '\0') + sel = &fast_punct_list[0]; + fast_punct = *sel; + update(); + break; + + + } + + if (scancode != KP_FORCE && scancode != KP_IDLE) /* don't record forced or idle scancode */ + last_scancode = scancode; +} + +static void scancode_action(int scancode) +{ +#if 0 + if (scancode == KP_RELEASE) + printf(" RELEASE\n"); + else if (scancode == KP_FORCE) + printf(" FORCE\n"); + else if (scancode == KP_IDLE) + printf(" IDLE\n"); + else if (scancode < 32) + printf(" F%d", scancode + 1); + else + printf(" %c", (char)scancode); + printf("\n"); +#endif + + if (enabled) { + handle_enabled_scancode(scancode); + return; + } + + if (scancode == KP_FORCE && last_scancode == '*') + use_me = 1; + + last_scancode = scancode; +} + +/**************************************************************************************/ + +/* update the display; make sure to update only the differences */ +static void update(void) +{ + int i; + char *s, *e, *t, *r, *b, *cp; + + if (input_mode != last_input_mode) + sed156x_output_at(sed156x_text_width - 3, sed156x_text_height - 1, input_mode_txt[input_mode], 3); + + if (tab_indicator == 0) { + sed156x_output_at(0, sed156x_text_height - 1, "\\t", 2); + tab_indicator = 1; + } + + if (fast_punct != last_fast_punct) + sed156x_output_at(4, sed156x_text_height - 1, &fast_punct, 1); + + if (curs_disabled || + curs_col < disp_col || curs_col >= (disp_col + width) || + curs_row < disp_row || curs_row >= (disp_row + height)) { + cp = NULL; + } else + cp = last_visible_buf + (curs_row - disp_row) * width + (curs_col - disp_col); + + + /* printf("(%d,%d) (%d,%d) %s\n", curs_col, curs_row, disp_col, disp_row, cp ? "YES" : "no"); */ + + /* clear previous cursor */ + if (last_visible_curs_ptr && last_visible_curs_rev == 0) { + i = last_visible_curs_ptr - last_visible_buf; + sed156x_reverse_at(i % width, i / width, 1); + } + + b = vty_buf + disp_row * COLS + disp_col; + t = last_visible_buf; + for (i = 0; i < height; i++) { + s = b; + e = b + width; + /* update only the differences */ + do { + while (s < e && *s == *t) { + s++; + t++; + } + if (s == e) /* no more */ + break; + + /* find run */ + r = s; + while (s < e && *s != *t) + *t++ = *s++; + + /* and update */ + sed156x_output_at(r - b, i, r, s - r); + + } while (s < e); + + b += COLS; + } + + /* set cursor */ + if (cp) { + last_visible_curs_ptr = cp; + i = last_visible_curs_ptr - last_visible_buf; + sed156x_reverse_at(i % width, i / width, 1); + last_visible_curs_rev = 0; + } else { + last_visible_curs_ptr = NULL; + } + + last_input_mode = input_mode; + last_fast_punct = fast_punct; +} + +/* ensure visibility; the trick is to minimize the screen movement */ +static void ensure_visible(int col, int row, int dx, int dy) +{ + int x1, y1, x2, y2, a1, b1, a2, b2; + + /* clamp visible region */ + if (col < 0) { + dx -= col; + col = 0; + if (dx <= 0) + dx = 1; + } + + if (row < 0) { + dy -= row; + row = 0; + if (dy <= 0) + dy = 1; + } + + if (col + dx > COLS) + dx = COLS - col; + + if (row + dy > ROWS) + dy = ROWS - row; + + + /* move to easier to use vars */ + x1 = disp_col; y1 = disp_row; + x2 = x1 + width; y2 = y1 + height; + a1 = col; b1 = row; + a2 = a1 + dx; b2 = b1 + dy; + + /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ + + if (a2 > x2) { + /* move to the right */ + x2 = a2; + x1 = x2 - width; + if (x1 < 0) { + x1 = 0; + x2 = width; + } + } else if (a1 < x1) { + /* move to the left */ + x1 = a1; + x2 = x1 + width; + if (x2 > COLS) { + x2 = COLS; + x1 = x2 - width; + } + } + + if (b2 > y2) { + /* move down */ + y2 = b2; + y1 = y2 - height; + if (y1 < 0) { + y1 = 0; + y2 = height; + } + } else if (b1 < y1) { + /* move up */ + y1 = b1; + y2 = y1 + width; + if (y2 > ROWS) { + y2 = ROWS; + y1 = y2 - height; + } + } + + /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ + + /* no movement? */ + if (disp_col == x1 && disp_row == y1) + return; + + disp_col = x1; + disp_row = y1; +} + +/**************************************************************************************/ + +static void newline(void) +{ + curs_col = 0; + if (curs_row + 1 < ROWS) + curs_row++; + else { + memmove(vty_buf, vty_buf + COLS, COLS * (ROWS - 1)); + memset(vty_buf + (ROWS - 1) * COLS, ' ', COLS); + } +} + +void phone_putc(const char c) +{ + int i; + + if (input_mode != -1) { + input_selected_char = -1; + terminate_input(); + } + + curs_disabled = 1; + update(); + + blink_time = BLINK_HZ; + + switch (c) { + case '\a': /* ignore bell */ + case '\r': /* ignore carriage return */ + break; + + case '\n': /* next line */ + newline(); + ensure_visible(curs_col, curs_row, 1, 1); + break; + + case 9: /* tab 8 */ + /* move to tab */ + i = curs_col; + i |= 0x0008; + i &= ~0x0007; + + if (i < COLS) + curs_col = i; + else + newline(); + + ensure_visible(curs_col, curs_row, 1, 1); + break; + + case 8: /* backspace */ + if (curs_col <= 0) + break; + curs_col--; + + /* make sure that we see a couple of characters before */ + if (curs_col > 4) + ensure_visible(curs_col - 4, curs_row, 4, 1); + else + ensure_visible(curs_col, curs_row, 1, 1); + + break; + + default: /* draw the char */ + putchar_at_cursor(c); + + /* + * check for newline + */ + if (curs_col + 1 < COLS) + curs_col++; + else + newline(); + + ensure_visible(curs_col, curs_row, 1, 1); + + break; + } + + curs_disabled = 0; + blink_time = BLINK_HZ; + update(); +} + +/**************************************************************************************/ + +static inline unsigned int kp_transfer(unsigned int val) +{ + unsigned int rx; + int b; + + rx = 0; b = 8; + while (--b >= 0) { + KP_SPI_TXD(val & 0x80); + val <<= 1; + KP_SPI_CLK_TOGGLE(); + KP_SPI_BIT_DELAY(); + rx <<= 1; + if (KP_SPI_RXD()) + rx |= 1; + KP_SPI_CLK_TOGGLE(); + KP_SPI_BIT_DELAY(); + } + + return rx; +} + +unsigned int kp_data_transfer(unsigned int val) +{ + KP_SPI_CLK(1); + KP_CS(0); + val = kp_transfer(val); + KP_CS(1); + + return val; +} + +unsigned int kp_get_col_mask(unsigned int row_mask) +{ + unsigned int val, col_mask; + + val = 0x80 | (row_mask & 0x7F); + (void)kp_data_transfer(val); +#if CONFIG_NETPHONE_VERSION == 1 + col_mask = kp_data_transfer(val) & 0x0F; +#elif CONFIG_NETPHONE_VERSION == 2 + col_mask = ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & 0x0f; + /* XXX FUCK FUCK FUCK FUCK FUCK!!!! */ + col_mask = ((col_mask & 0x08) >> 3) | /* BKBR1 */ + ((col_mask & 0x04) << 1) | /* BKBR2 */ + (col_mask & 0x02) | /* BKBR3 */ + ((col_mask & 0x01) << 2); /* BKBR4 */ + +#endif + /* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */ + + return col_mask; +} + +/**************************************************************************************/ + +static const int kp_scancodes[KP_ROWS * KP_COLS] = { + KP_F1, KP_F3, KP_F4, KP_F2, + KP_F6, KP_F8, KP_F9, KP_F7, + KP_1, KP_3, KP_F11, KP_2, + KP_4, KP_6, KP_F12, KP_5, + KP_7, KP_9, KP_F13, KP_8, + KP_STAR, KP_HASH, KP_F14, KP_0, + KP_F5, KP_F15, KP_F16, KP_F10, +}; + +static const int kp_repeats[KP_ROWS * KP_COLS] = { + 0, 1, 0, 0, + 0, 1, 1, 1, + 1, 1, 0, 1, + 1, 1, 0, 1, + 1, 1, 0, 1, + 1, 1, 0, 1, + 0, 0, 0, 1, +}; + +static int kp_state = SCAN; +static int kp_last_col_mask; +static int kp_cur_row, kp_cur_col; +static int kp_scancode; +static int kp_stable; +static int kp_repeat; +static int kp_repeat_time; +static int kp_force_time; +static int kp_idle_time; + +static void kp_do_poll(void) +{ + unsigned int col_mask; + int col; + + switch (kp_state) { + case SCAN: + if (kp_idle_time > 0) { + kp_idle_time -= PHONE_CONSOLE_POLL_HZ; + if (kp_idle_time <= 0) + scancode_action(KP_IDLE); + } + + col_mask = kp_get_col_mask(KP_ROWS_MASK); + if (col_mask == KP_COLS_MASK) + break; /* nothing */ + kp_last_col_mask = col_mask; + kp_stable = 0; + kp_state = SCAN_FILTER; + break; + + case SCAN_FILTER: + col_mask = kp_get_col_mask(KP_ROWS_MASK); + if (col_mask != kp_last_col_mask) { + kp_state = SCAN; + break; + } + + kp_stable += PHONE_CONSOLE_POLL_HZ; + if (kp_stable < KP_STABLE_HZ) + break; + + kp_cur_row = 0; + kp_stable = 0; + kp_state = SCAN_COL; + + (void)kp_get_col_mask(1 << kp_cur_row); + break; + + case SCAN_COL: + col_mask = kp_get_col_mask(1 << kp_cur_row); + if (col_mask == KP_COLS_MASK) { + if (++kp_cur_row >= KP_ROWS) { + kp_state = SCAN; + break; + } + kp_get_col_mask(1 << kp_cur_row); + break; + } + kp_last_col_mask = col_mask; + kp_stable = 0; + kp_state = SCAN_COL_FILTER; + break; + + case SCAN_COL_FILTER: + col_mask = kp_get_col_mask(1 << kp_cur_row); + if (col_mask != kp_last_col_mask || col_mask == KP_COLS_MASK) { + kp_state = SCAN; + break; + } + + kp_stable += PHONE_CONSOLE_POLL_HZ; + if (kp_stable < KP_STABLE_HZ) + break; + + for (col = 0; col < KP_COLS; col++) + if ((col_mask & (1 << col)) == 0) + break; + kp_cur_col = col; + kp_state = PRESSED; + kp_scancode = kp_scancodes[kp_cur_row * KP_COLS + kp_cur_col]; + kp_repeat = kp_repeats[kp_cur_row * KP_COLS + kp_cur_col]; + + if (kp_repeat) + kp_repeat_time = KP_REPEAT_DELAY_HZ; + kp_force_time = KP_FORCE_DELAY_HZ; + + scancode_action(kp_scancode); + + break; + + case PRESSED: + col_mask = kp_get_col_mask(1 << kp_cur_row); + if (col_mask != kp_last_col_mask) { + kp_state = SCAN; + scancode_action(KP_RELEASE); + kp_idle_time = KP_IDLE_DELAY_HZ; + break; + } + + if (kp_repeat) { + kp_repeat_time -= PHONE_CONSOLE_POLL_HZ; + if (kp_repeat_time <= 0) { + kp_repeat_time += KP_REPEAT_HZ; + scancode_action(kp_scancode); + } + } + + if (kp_force_time > 0) { + kp_force_time -= PHONE_CONSOLE_POLL_HZ; + if (kp_force_time <= 0) + scancode_action(KP_FORCE); + } + + break; + } +} + +/**************************************************************************************/ + +int drv_phone_is_idle(void) +{ + return kp_state == SCAN; +} diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds new file mode 100644 index 0000000..9f2901c --- /dev/null +++ b/board/netphone/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug new file mode 100644 index 0000000..004e7fd --- /dev/null +++ b/board/netphone/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netta/Makefile b/board/netta/Makefile new file mode 100644 index 0000000..68e2402 --- /dev/null +++ b/board/netta/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o dsp.o codec.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/netta/codec.c b/board/netta/codec.c new file mode 100644 index 0000000..01ab14b --- /dev/null +++ b/board/netta/codec.c @@ -0,0 +1,1484 @@ +/* + * CODEC + */ + +#include +#include + +#include "mpc8xx.h" + +/***********************************************/ + +#define MAX_DUSLIC 4 + +#define NUM_CHANNELS 2 +#define MAX_SLICS (MAX_DUSLIC * NUM_CHANNELS) + +/***********************************************/ + +#define SOP_READ_CH_0 0xC4 /* Read SOP Register for Channel A */ +#define SOP_READ_CH_1 0xCC /* Read SOP Register for Channel B */ +#define SOP_WRITE_CH_0 0x44 /* Write SOP Register for Channel A */ +#define SOP_WRITE_CH_1 0x4C /* Write SOP Register for Channel B */ + +#define COP_READ_CH_0 0xC5 +#define COP_READ_CH_1 0xCD +#define COP_WRITE_CH_0 0x45 +#define COP_WRITE_CH_1 0x4D + +#define POP_READ_CH_0 0xC6 +#define POP_READ_CH_1 0xCE +#define POP_WRITE_CH_0 0x46 +#define POP_WRITE_CH_1 0x4E + +#define RST_CMD_DUSLIC_CHIP 0x40 /* OR 0x48 */ +#define RST_CMD_DUSLIC_CH_A 0x41 +#define RST_CMD_DUSLIC_CH_B 0x49 + +#define PCM_RESYNC_CMD_CH_A 0x42 +#define PCM_RESYNC_CMD_CH_B 0x4A + +#define ACTIVE_HOOK_LEV_4 0 +#define ACTIVE_HOOK_LEV_12 1 + +#define SLIC_P_NORMAL 0x01 + +/************************************************/ + +#define CODSP_WR 0x00 +#define CODSP_RD 0x80 +#define CODSP_OP 0x40 +#define CODSP_ADR(x) (((unsigned char)(x) & 7) << 3) +#define CODSP_M(x) ((unsigned char)(x) & 7) +#define CODSP_CMD(x) ((unsigned char)(x) & 7) + +/************************************************/ + +/* command indication ops */ +#define CODSP_M_SLEEP_PWRDN 7 +#define CODSP_M_PWRDN_HIZ 0 +#define CODSP_M_ANY_ACT 2 +#define CODSP_M_RING 5 +#define CODSP_M_ACT_MET 6 +#define CODSP_M_GND_START 4 +#define CODSP_M_RING_PAUSE 1 + +/* single byte commands */ +#define CODSP_CMD_SOFT_RESET CODSP_CMD(0) +#define CODSP_CMD_RESET_CH CODSP_CMD(1) +#define CODSP_CMD_RESYNC CODSP_CMD(2) + +/* two byte commands */ +#define CODSP_CMD_SOP CODSP_CMD(4) +#define CODSP_CMD_COP CODSP_CMD(5) +#define CODSP_CMD_POP CODSP_CMD(6) + +/************************************************/ + +/* read as 4-bytes */ +#define CODSP_INTREG_INT_CH 0x80000000 +#define CODSP_INTREG_HOOK 0x40000000 +#define CODSP_INTREG_GNDK 0x20000000 +#define CODSP_INTREG_GNDP 0x10000000 +#define CODSP_INTREG_ICON 0x08000000 +#define CODSP_INTREG_VRTLIM 0x04000000 +#define CODSP_INTREG_OTEMP 0x02000000 +#define CODSP_INTREG_SYNC_FAIL 0x01000000 +#define CODSP_INTREG_LM_THRES 0x00800000 +#define CODSP_INTREG_READY 0x00400000 +#define CODSP_INTREG_RSTAT 0x00200000 +#define CODSP_INTREG_LM_OK 0x00100000 +#define CODSP_INTREG_IO4_DU 0x00080000 +#define CODSP_INTREG_IO3_DU 0x00040000 +#define CODSP_INTREG_IO2_DU 0x00020000 +#define CODSP_INTREG_IO1_DU 0x00010000 +#define CODSP_INTREG_DTMF_OK 0x00008000 +#define CODSP_INTREG_DTMF_KEY4 0x00004000 +#define CODSP_INTREG_DTMF_KEY3 0x00002000 +#define CODSP_INTREG_DTMF_KEY2 0x00001000 +#define CODSP_INTREG_DTMF_KEY1 0x00000800 +#define CODSP_INTREG_DTMF_KEY0 0x00000400 +#define CODSP_INTREG_UTDR_OK 0x00000200 +#define CODSP_INTREG_UTDX_OK 0x00000100 +#define CODSP_INTREG_EDSP_FAIL 0x00000080 +#define CODSP_INTREG_CIS_BOF 0x00000008 +#define CODSP_INTREG_CIS_BUF 0x00000004 +#define CODSP_INTREG_CIS_REQ 0x00000002 +#define CODSP_INTREG_CIS_ACT 0x00000001 + +/************************************************/ + +/* ======== SOP REG ADDRESSES =======*/ + +#define REVISION_ADDR 0x00 +#define PCMC1_ADDR 0x05 +#define XCR_ADDR 0x06 +#define INTREG1_ADDR 0x07 +#define INTREG2_ADDR 0x08 +#define INTREG3_ADDR 0x09 +#define INTREG4_ADDR 0x0A +#define LMRES1_ADDR 0x0D +#define MASK_ADDR 0x11 +#define IOCTL3_ADDR 0x14 +#define BCR1_ADDR 0x15 +#define BCR2_ADDR 0x16 +#define BCR3_ADDR 0x17 +#define BCR4_ADDR 0x18 +#define BCR5_ADDR 0x19 +#define DSCR_ADDR 0x1A +#define LMCR1_ADDR 0x1C +#define LMCR2_ADDR 0x1D +#define LMCR3_ADDR 0x1E +#define OFR1_ADDR 0x1F +#define PCMR1_ADDR 0x21 +#define PCMX1_ADDR 0x25 +#define TSTR3_ADDR 0x2B +#define TSTR4_ADDR 0x2C +#define TSTR5_ADDR 0x2D + +/* ========= POP REG ADDRESSES ========*/ + +#define CIS_DAT_ADDR 0x00 + +#define LEC_LEN_ADDR 0x3A +#define LEC_POWR_ADDR 0x3B +#define LEC_DELP_ADDR 0x3C +#define LEC_DELQ_ADDR 0x3D +#define LEC_GAIN_XI_ADDR 0x3E +#define LEC_GAIN_RI_ADDR 0x3F +#define LEC_GAIN_XO_ADDR 0x40 +#define LEC_RES_1_ADDR 0x41 +#define LEC_RES_2_ADDR 0x42 + +#define NLP_POW_LPF_ADDR 0x30 +#define NLP_POW_LPS_ADDR 0x31 +#define NLP_BN_LEV_X_ADDR 0x32 +#define NLP_BN_LEV_R_ADDR 0x33 +#define NLP_BN_INC_ADDR 0x34 +#define NLP_BN_DEC_ADDR 0x35 +#define NLP_BN_MAX_ADDR 0x36 +#define NLP_BN_ADJ_ADDR 0x37 +#define NLP_RE_MIN_ERLL_ADDR 0x38 +#define NLP_RE_EST_ERLL_ADDR 0x39 +#define NLP_SD_LEV_X_ADDR 0x3A +#define NLP_SD_LEV_R_ADDR 0x3B +#define NLP_SD_LEV_BN_ADDR 0x3C +#define NLP_SD_LEV_RE_ADDR 0x3D +#define NLP_SD_OT_DT_ADDR 0x3E +#define NLP_ERL_LIN_LP_ADDR 0x3F +#define NLP_ERL_LEC_LP_ADDR 0x40 +#define NLP_CT_LEV_RE_ADDR 0x41 +#define NLP_CTRL_ADDR 0x42 + +#define UTD_CF_H_ADDR 0x4B +#define UTD_CF_L_ADDR 0x4C +#define UTD_BW_H_ADDR 0x4D +#define UTD_BW_L_ADDR 0x4E +#define UTD_NLEV_ADDR 0x4F +#define UTD_SLEV_H_ADDR 0x50 +#define UTD_SLEV_L_ADDR 0x51 +#define UTD_DELT_ADDR 0x52 +#define UTD_RBRK_ADDR 0x53 +#define UTD_RTIME_ADDR 0x54 +#define UTD_EBRK_ADDR 0x55 +#define UTD_ETIME_ADDR 0x56 + +#define DTMF_LEV_ADDR 0x30 +#define DTMF_TWI_ADDR 0x31 +#define DTMF_NCF_H_ADDR 0x32 +#define DTMF_NCF_L_ADDR 0x33 +#define DTMF_NBW_H_ADDR 0x34 +#define DTMF_NBW_L_ADDR 0x35 +#define DTMF_GAIN_ADDR 0x36 +#define DTMF_RES1_ADDR 0x37 +#define DTMF_RES2_ADDR 0x38 +#define DTMF_RES3_ADDR 0x39 + +#define CIS_LEV_H_ADDR 0x43 +#define CIS_LEV_L_ADDR 0x44 +#define CIS_BRS_ADDR 0x45 +#define CIS_SEIZ_H_ADDR 0x46 +#define CIS_SEIZ_L_ADDR 0x47 +#define CIS_MARK_H_ADDR 0x48 +#define CIS_MARK_L_ADDR 0x49 +#define CIS_LEC_MODE_ADDR 0x4A + +/*=====================================*/ + +#define HOOK_LEV_ACT_START_ADDR 0x89 +#define RO1_START_ADDR 0x70 +#define RO2_START_ADDR 0x95 +#define RO3_START_ADDR 0x96 + +#define TG1_FREQ_START_ADDR 0x38 +#define TG1_GAIN_START_ADDR 0x39 +#define TG1_BANDPASS_START_ADDR 0x3B +#define TG1_BANDPASS_END_ADDR 0x3D + +#define TG2_FREQ_START_ADDR 0x40 +#define TG2_GAIN_START_ADDR 0x41 +#define TG2_BANDPASS_START_ADDR 0x43 +#define TG2_BANDPASS_END_ADDR 0x45 + +/*====================================*/ + +#define PCM_HW_B 0x80 +#define PCM_HW_A 0x00 +#define PCM_TIME_SLOT_0 0x00 /* Byte 0 of PCM Frame (by default is assigned to channel A ) */ +#define PCM_TIME_SLOT_1 0x01 /* Byte 1 of PCM Frame (by default is assigned to channel B ) */ +#define PCM_TIME_SLOT_4 0x04 /* Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */ + +#define RX_LEV_ADDR 0x28 +#define TX_LEV_ADDR 0x30 +#define Ik1_ADDR 0x83 + +#define AR_ROW 3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */ +#define AX_ROW 6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */ +#define DCF_ROW 0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */ + +/* Mark the start byte of Duslic parameters that we use with configurator */ +#define Ik1_START_BYTE 3 +#define RX_LEV_START_BYTE 0 +#define TX_LEV_START_BYTE 0 + +/************************************************/ + +#define INTREG4_CIS_ACT (1 << 0) + +#define BCR1_SLEEP 0x20 +#define BCR1_REVPOL 0x10 +#define BCR1_ACTR 0x08 +#define BCR1_ACTL 0x04 +#define BCR1_SLIC_MASK 0x03 + +#define BCR2_HARD_POL_REV 0x40 +#define BCR2_TTX 0x20 +#define BCR2_TTX_12K 0x10 +#define BCR2_HIMAN 0x08 +#define BCR2_PDOT 0x01 + +#define BCR3_PCMX_EN (1 << 4) + +#define BCR5_DTMF_EN (1 << 0) +#define BCR5_DTMF_SRC (1 << 1) +#define BCR5_LEC_EN (1 << 2) +#define BCR5_LEC_OUT (1 << 3) +#define BCR5_CIS_EN (1 << 4) +#define BCR5_CIS_AUTO (1 << 5) +#define BCR5_UTDX_EN (1 << 6) +#define BCR5_UTDR_EN (1 << 7) + +#define DSCR_TG1_EN (1 << 0) +#define DSCR_TG2_EN (1 << 1) +#define DSCR_PTG (1 << 2) +#define DSCR_COR8 (1 << 3) +#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4) + +#define CIS_LEC_MODE_CIS_V23 (1 << 0) +#define CIS_LEC_MODE_CIS_FRM (1 << 1) +#define CIS_LEC_MODE_NLP_EN (1 << 2) +#define CIS_LEC_MODE_UTDR_SUM (1 << 4) +#define CIS_LEC_MODE_UTDX_SUM (1 << 5) +#define CIS_LEC_MODE_LEC_FREEZE (1 << 6) +#define CIS_LEC_MODE_LEC_ADAPT (1 << 7) + +#define TSTR4_COR_64 (1 << 5) + +#define TSTR3_AC_DLB_8K (1 << 2) +#define TSTR3_AC_DLB_32K (1 << 3) +#define TSTR3_AC_DLB_4M (1 << 5) + + +#define LMCR1_TEST_EN (1 << 7) +#define LMCR1_LM_EN (1 << 6) +#define LMCR1_LM_THM (1 << 5) +#define LMCR1_LM_ONCE (1 << 2) +#define LMCR1_LM_MASK (1 << 1) + +#define LMCR2_LM_RECT (1 << 5) +#define LMCR2_LM_SEL_VDD 0x0D +#define LMCR2_LM_SEL_IO3 0x0A +#define LMCR2_LM_SEL_IO4 0x0B +#define LMCR2_LM_SEL_IO4_MINUS_IO3 0x0F + +#define LMCR3_RTR_SEL (1 << 6) + +#define LMCR3_RNG_OFFSET_NONE 0x00 +#define LMCR3_RNG_OFFSET_1 0x01 +#define LMCR3_RNG_OFFSET_2 0x02 +#define LMCR3_RNG_OFFSET_3 0x03 + +#define TSTR5_DC_HOLD (1 << 3) + +/************************************************/ + +#define TARGET_ONHOOK_BATH_x100 4600 /* 46.0 Volt */ +#define TARGET_ONHOOK_BATL_x100 2500 /* 25.0 Volt */ +#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */ +#define DIVIDER_RATIO_ACCURx100 (22 * 100) +#define V_AD_x10000 10834L /* VAD = 1.0834 */ +#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */ +#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2*100 */ + +#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/ +#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */ +#define K_INTDC_RECT_OFF 2 /* 2^2 */ +#define RNG_FREQ 25 +#define SAMPLING_FREQ (2000L) +#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */ +#define HOOK_THRESH_RING_START_ADDR 0x8B +#define RING_PARAMS_START_ADDR 0x70 + +#define V_OUT_BATH_MAX_DIFFx100 300 /* 3.0 x100 */ +#define V_OUT_BATL_MAX_DIFFx100 400 /* 4.0 x100 */ +#define MAX_V_RING_MEANx100 50 +#define TARGET_V_RING_RMSx100 2720 +#define V_RMS_RING_MAX_DIFFx100 250 + +#define LM_OK_SRC_IRG_2 (1 << 4) + +/************************************************/ + +#define PORTB (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define PORTC (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define PORTD (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) + +#define _PORTD_SET(mask, state) \ + do { \ + if (state) \ + PORTD |= mask; \ + else \ + PORTD &= ~mask; \ + } while (0) + +#define _PORTB_SET(mask, state) \ + do { \ + if (state) \ + PORTB |= mask; \ + else \ + PORTB &= ~mask; \ + } while (0) + +#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0) +#define _PORTB_GET(mask) (!!(PORTB & mask)) + +#define _PORTC_GET(mask) (!!(PORTC & mask)) + +/* port B */ +#define SPI_RXD (1 << (31 - 28)) +#define SPI_TXD (1 << (31 - 29)) +#define SPI_CLK (1 << (31 - 30)) + +/* port C */ +#define COM_HOOK1 (1 << (15 - 9)) +#define COM_HOOK2 (1 << (15 - 10)) + +#ifndef CONFIG_NETTA_SWAPHOOK + +#define COM_HOOK3 (1 << (15 - 11)) +#define COM_HOOK4 (1 << (15 - 12)) + +#else + +#define COM_HOOK3 (1 << (15 - 12)) +#define COM_HOOK4 (1 << (15 - 11)) + +#endif + +/* port D */ +#define SPIENC1 (1 << (15 - 9)) +#define SPIENC2 (1 << (15 - 10)) +#define SPIENC3 (1 << (15 - 11)) +#define SPIENC4 (1 << (15 - 14)) + +#define SPI_DELAY() udelay(1) + +static inline unsigned int __SPI_Transfer(unsigned int tx) +{ + unsigned int rx; + int b; + + rx = 0; b = 8; + while (--b >= 0) { + _PORTB_SET(SPI_TXD, tx & 0x80); + tx <<= 1; + _PORTB_TGL(SPI_CLK); + SPI_DELAY(); + rx <<= 1; + rx |= _PORTB_GET(SPI_RXD); + _PORTB_TGL(SPI_CLK); + SPI_DELAY(); + } + + return rx; +} + +static const char *codsp_dtmf_map = "D1234567890*#ABC"; + +static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 }; +static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 }; + +static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen) +{ + unsigned int rx; + int i; + + /* just some sanity checks */ + if (cmd == 0 || cmdlen < 0) + return -1; + + _PORTD_SET(spienc_mask_tab[duslic_id], 0); + + /* first 2 bytes are without response */ + i = 2; + while (i-- > 0 && cmdlen-- > 0) + __SPI_Transfer(*cmd++); + + while (cmdlen-- > 0) { + rx = __SPI_Transfer(*cmd++); + if (res != 0 && reslen-- > 0) + *res++ = (unsigned char)rx; + } + if (res != 0) { + while (reslen-- > 0) + *res++ = __SPI_Transfer(0xFF); + } + + _PORTD_SET(spienc_mask_tab[duslic_id], 1); + + return 0; +} + +/****************************************************************************/ + +void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m) +{ + unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m); + codsp_send(duslic_id, &cmd, 1, 0, 0); +} + +void codsp_reset_chip(int duslic_id) +{ + static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET; + codsp_send(duslic_id, &cmd, 1, 0, 0); +} + +void codsp_reset_channel(int duslic_id, int channel) +{ + unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH; + codsp_send(duslic_id, &cmd, 1, 0, 0); +} + +void codsp_resync_channel(int duslic_id, int channel) +{ + unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC; + codsp_send(duslic_id, &cmd, 1, 0, 0); +} + +/****************************************************************************/ + +void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val) +{ + unsigned char cmd[3]; + + cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; + cmd[1] = regno; + cmd[2] = val; + + codsp_send(duslic_id, cmd, 3, 0, 0); +} + +void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val) +{ + unsigned char cmd[4]; + + cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; + cmd[1] = regno; + cmd[2] = (unsigned char)(val >> 8); + cmd[3] = (unsigned char)val; + + codsp_send(duslic_id, cmd, 4, 0, 0); +} + +void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val) +{ + unsigned char cmd[5]; + + cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP; + cmd[1] = regno; + cmd[2] = (unsigned char)(val >> 24); + cmd[3] = (unsigned char)(val >> 16); + cmd[4] = (unsigned char)(val >> 8); + cmd[5] = (unsigned char)val; + + codsp_send(duslic_id, cmd, 6, 0, 0); +} + +unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno) +{ + unsigned char cmd[3]; + unsigned char res[2]; + + cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; + cmd[1] = regno; + + codsp_send(duslic_id, cmd, 2, res, 2); + + return res[1]; +} + +unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno) +{ + unsigned char cmd[2]; + unsigned char res[3]; + + cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; + cmd[1] = regno; + + codsp_send(duslic_id, cmd, 2, res, 3); + + return ((unsigned short)res[1] << 8) | res[2]; +} + +unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno) +{ + unsigned char cmd[2]; + unsigned char res[5]; + + cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; + cmd[1] = regno; + + codsp_send(duslic_id, cmd, 2, res, 5); + + return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4]; +} + +/****************************************************************************/ + +void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block) +{ + unsigned char cmd[10]; + + cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; + cmd[1] = addr; + memcpy(cmd + 2, block, 8); + codsp_send(duslic_id, cmd, 10, 0, 0); +} + +void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val) +{ + unsigned char cmd[3]; + + cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; + cmd[1] = addr; + cmd[2] = val; + codsp_send(duslic_id, cmd, 3, 0, 0); +} + +void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val) +{ + unsigned char cmd[3]; + + cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; + cmd[1] = addr; + cmd[2] = (unsigned char)(val >> 8); + cmd[3] = (unsigned char)val; + + codsp_send(duslic_id, cmd, 4, 0, 0); +} + +void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block) +{ + unsigned char cmd[2]; + unsigned char res[9]; + + cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; + cmd[1] = addr; + codsp_send(duslic_id, cmd, 2, res, 9); + memcpy(block, res + 1, 8); +} + +unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr) +{ + unsigned char cmd[2]; + unsigned char res[2]; + + cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; + cmd[1] = addr; + codsp_send(duslic_id, cmd, 2, res, 2); + return res[1]; +} + +unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr) +{ + unsigned char cmd[2]; + unsigned char res[3]; + + cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; + cmd[1] = addr; + + codsp_send(duslic_id, cmd, 2, res, 3); + + return ((unsigned short)res[1] << 8) | res[2]; +} + +/****************************************************************************/ + +#define MAX_POP_BLOCK 50 + +void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr, + const unsigned char *block, int len) +{ + unsigned char cmd[2 + MAX_POP_BLOCK]; + + if (len > MAX_POP_BLOCK) /* truncate */ + len = MAX_POP_BLOCK; + + cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; + cmd[1] = addr; + memcpy (cmd + 2, block, len); + codsp_send (duslic_id, cmd, 2 + len, 0, 0); +} + +void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno, + unsigned char val) +{ + unsigned char cmd[3]; + + cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; + cmd[1] = regno; + cmd[2] = val; + + codsp_send (duslic_id, cmd, 3, 0, 0); +} + +void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno, + unsigned short val) +{ + unsigned char cmd[4]; + + cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; + cmd[1] = regno; + cmd[2] = (unsigned char) (val >> 8); + cmd[3] = (unsigned char) val; + + codsp_send (duslic_id, cmd, 4, 0, 0); +} + +void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno, + unsigned int val) +{ + unsigned char cmd[5]; + + cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP; + cmd[1] = regno; + cmd[2] = (unsigned char) (val >> 24); + cmd[3] = (unsigned char) (val >> 16); + cmd[4] = (unsigned char) (val >> 8); + cmd[5] = (unsigned char) val; + + codsp_send (duslic_id, cmd, 6, 0, 0); +} + +unsigned char codsp_read_pop_char (int duslic_id, int channel, + unsigned char regno) +{ + unsigned char cmd[3]; + unsigned char res[2]; + + cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; + cmd[1] = regno; + + codsp_send (duslic_id, cmd, 2, res, 2); + + return res[1]; +} + +unsigned short codsp_read_pop_short (int duslic_id, int channel, + unsigned char regno) +{ + unsigned char cmd[2]; + unsigned char res[3]; + + cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; + cmd[1] = regno; + + codsp_send (duslic_id, cmd, 2, res, 3); + + return ((unsigned short) res[1] << 8) | res[2]; +} + +unsigned int codsp_read_pop_int (int duslic_id, int channel, + unsigned char regno) +{ + unsigned char cmd[2]; + unsigned char res[5]; + + cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; + cmd[1] = regno; + + codsp_send (duslic_id, cmd, 2, res, 5); + + return (((unsigned int) res[1] << 24) | + ((unsigned int) res[2] << 16) | + ((unsigned int) res[3] << 8) | + res[4] ); +} +/****************************************************************************/ + +struct _coeffs { + unsigned char addr; + unsigned char values[8]; +}; + +struct _coeffs ac_coeffs[11] = { + { 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */ + { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */ + { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */ + { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */ + { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */ + { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */ + { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */ + { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */ + { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */ + { 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */ + { 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */ +}; + +struct _coeffs ac_coeffs_0dB[11] = { + { 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} }, + { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} }, + { 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} }, + { 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} }, + { 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} }, + { 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} }, + { 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} }, + { 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} }, + { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, + { 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} }, + { 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} } +}; + +struct _coeffs dc_coeffs[9] = { + { 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */ + { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */ + { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */ + { 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */ + { 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */ + { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */ + { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */ + { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */ + { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */ +}; + +void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size) +{ + int i; + + for (i = 0; i < tab_size; i++) + codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values); +} + +#define SS_OPEN_CIRCUIT 0 +#define SS_RING_PAUSE 1 +#define SS_ACTIVE 2 +#define SS_ACTIVE_HIGH 3 +#define SS_ACTIVE_RING 4 +#define SS_RINGING 5 +#define SS_ACTIVE_WITH_METERING 6 +#define SS_ONHOOKTRNSM 7 +#define SS_STANDBY 8 +#define SS_MAX 8 + +static void codsp_set_slic(int duslic_id, int channel, int state) +{ + unsigned char v; + + v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR); + + switch (state) { + + case SS_ACTIVE: + codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL); + codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); + break; + + case SS_ACTIVE_HIGH: + codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL)); + codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); + break; + + case SS_ACTIVE_RING: + case SS_ONHOOKTRNSM: + codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR); + codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); + break; + + case SS_STANDBY: + codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR)); + codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN); + break; + + case SS_OPEN_CIRCUIT: + codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ); + break; + + case SS_RINGING: + codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING); + break; + + case SS_RING_PAUSE: + codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE); + break; + } +} + +const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 }; +const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 }; + +void retrieve_slic_state(int slic_id) +{ + int duslic_id = slic_id >> 1; + int channel = slic_id & 1; + + /* Retrieve the state of the SLICs */ + codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); + + /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ + udelay(10000); + + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); + codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); + codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); + + /* Program Default Hook Ring thresholds */ + codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values); + + /* Now program Hook Threshold while Ring and ac RingTrip to max values */ + codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values); + + codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); + + udelay(40000); +} + +int wait_level_metering_finish(int duslic_id, int channel) +{ + int cnt; + + for (cnt = 0; cnt < 1000 && + (codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { } + + return cnt != 1000; +} + +int measure_on_hook_voltages(int slic_id, long *vdd, + long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v) +{ + short LM_Result, Offset_Compensation; /* Signed 16 bit */ + long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ; + unsigned char err_mask = 0; + int duslic_id = slic_id >> 1; + int channel = slic_id & 1; + int i; + + /* measure VDD */ + /* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */ + codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD); + + /* Activate Test Mode ==> To Enable DC Hold !!! */ + /* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */ + /* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/ + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK); + + udelay(40000); + + /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */ + codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD); + + /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ + udelay(10000); + + /* Now Read the LM Result Registers */ + LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); + VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ; /* VDDx100 */ + + *vdd = VDD; + + VDD_diff = VDD - TARGET_VDDx100; + + if (VDD_diff < 0) + VDD_diff = -VDD_diff; + + if (VDD_diff > VDD_MAX_DIFFx100) + err_mask |= 1; + + Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100; + + codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); + + codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */ + + udelay(40000); + + codsp_write_sop_char(duslic_id, channel, + LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK); + + udelay(40000); + + /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */ + codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3); + + /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ + udelay(10000); + + /* Now Read the LM Result Registers */ + LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); + V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/ + + V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ + + *v_oh_H = V_out; + + Vout_diff = V_out - TARGET_ONHOOK_BATH_x100; + + if (Vout_diff < 0) + Vout_diff = -Vout_diff; + + if (Vout_diff > V_OUT_BATH_MAX_DIFFx100) + err_mask |= 2; + + codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */ + + udelay(40000); + + /* Now Read the LM Result Registers */ + LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); + + V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/ + + V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ + + *v_oh_L = V_out; + + Vout_diff = V_out - TARGET_ONHOOK_BATL_x100; + + if (Vout_diff < 0) + Vout_diff = -Vout_diff; + + if (Vout_diff > V_OUT_BATL_MAX_DIFFx100) + err_mask |= 4; + + /* perform ring tests */ + + codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); + + udelay(40000); + + codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE); + + /* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/ + codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz); + + /* By Default RO1 is selected when ringing RNG-OFFSET = 00 */ + + /* Now program Hook Threshold while Ring and ac RingTrip to max values */ + for(i = 0; i < sizeof(Max_HookRingTh); i++) + codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]); + + codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); + + codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */ + + /* select source for the levelmeter to be IO4-IO3 */ + codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3); + + udelay(40000); + + /* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */ + codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF); + + udelay(10000); + + /* Enable LevelMeter to Integrate only once (Rectifier Disabled) */ + codsp_write_sop_char(duslic_id, channel, + LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); + + udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */ + + if (wait_level_metering_finish(duslic_id, channel)) { + + udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */ + + /* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */ + Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); + Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES); + + /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); + + /* Now programm Integrator Offset Registers !!! */ + codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation); + + codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */ + + udelay(40000); + + /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ + codsp_write_sop_char(duslic_id, channel, + LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); + + udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */ + + /* Poll the LM_OK bit to see when Integration Result is Ready */ + if (wait_level_metering_finish(duslic_id, channel)) { + + udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */ + + /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ + /* ==>After that Result Regs will be updated every 500us !!!) */ + LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); + V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ; /* Vin x 10000*/ + + V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ + + if (V_out < 0) + V_out= -V_out; + + if (V_out > MAX_V_RING_MEANx100) + err_mask |= 8; + + *ring_mean_v = V_out; + } else { + err_mask |= 8; + *ring_mean_v = 0; + } + } else { + err_mask |= 8; + *ring_mean_v = 0; + } + + /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, + LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); + codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); + + codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */ + + /* Now Enable Rectifier */ + /* select source for the levelmeter to be IO4-IO3 */ + codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, + LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT); + + /* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */ + codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON); + + udelay(40000); + + /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, + LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); + + udelay(40000); + + /* Poll the LM_OK bit to see when Integration Result is Ready */ + if (wait_level_metering_finish(duslic_id, channel)) { + + udelay(10000); + + /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ + /* ==>After that Result Regs will be updated every 500us !!!) */ + Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); + Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES); + + /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); + + /* Now programm Integrator Offset Registers !!! */ + codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation); + + /* Be sure that a Ring is generated !!!! */ + codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */ + + udelay(40000); + + /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, + LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); + + udelay(40000); + + /* Poll the LM_OK bit to see when Integration Result is Ready */ + if (wait_level_metering_finish(duslic_id, channel)) { + + udelay(10000); + + /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ + /* ==>After that Result Regs will be updated every 500us !!!) */ + LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); + V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ; /* Vin x 10000*/ + + V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ; /* Vout_RMS x100 */ + if (V_out < 0) + V_out = -V_out; + + Vout_diff = (V_out - TARGET_V_RING_RMSx100); + + if (Vout_diff < 0) + Vout_diff = -Vout_diff; + + if (Vout_diff > V_RMS_RING_MAX_DIFFx100) + err_mask |= 16; + + *ring_rms_v = V_out; + } else { + err_mask |= 16; + *ring_rms_v = 0; + } + } else { + err_mask |= 16; + *ring_rms_v = 0; + } + /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ + codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); + + retrieve_slic_state(slic_id); + + return(err_mask); +} + +int test_dtmf(int slic_id) +{ + unsigned char code; + unsigned char b; + unsigned int intreg; + int duslic_id = slic_id >> 1; + int channel = slic_id & 1; + + for (code = 0; code < 16; code++) { + b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); + codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, + (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN); + udelay(80000); + + intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); + if ((intreg & CODSP_INTREG_INT_CH) == 0) + break; + + if ((intreg & CODSP_INTREG_DTMF_OK) == 0 || + codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code]) + break; + + b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); + codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, + b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN)); + + udelay(80000); + + intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */ + } + + if (code != 16) { + b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */ + codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, + b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN)); + return(1); + } + + return(0); +} + +void data_up_persist_time(int duslic_id, int channel, int time_ms) +{ + unsigned char b; + + b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR); + b = (b & 0x0F) | ((time_ms & 0x0F) << 4); + codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b); +} + +static void program_dtmf_params(int duslic_id, int channel) +{ + unsigned char b; + + codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10); + codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C); + codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79); + codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10); + codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02); + codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB); + codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91); + codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00); + codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00); + codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00); + + b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR); + codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN); +} + +static void codsp_channel_full_reset(int duslic_id, int channel) +{ + + program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs)); + program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs)); + + /* program basic configuration registers */ + codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01); + codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41); + codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43); + codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00); + codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00); + + codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04); /* PG */ + + program_dtmf_params(duslic_id, channel); + + codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); /* RingTRip_SEL */ + + data_up_persist_time(duslic_id, channel, 4); + + codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF); /* All interrupts masked */ + + codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); +} + +static int codsp_chip_full_reset(int duslic_id) +{ + int i, cnt; + int intreg[NUM_CHANNELS]; + unsigned char pcm_resync; + unsigned char revision; + + codsp_reset_chip(duslic_id); + + udelay(2000); + + for (i = 0; i < NUM_CHANNELS; i++) + intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR); + + udelay(1500); + + if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) { + printf("_HOOK(%d) stayed low\n", duslic_id); + return -1; + } + + for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) { + if (intreg[i] & CODSP_INTREG_SYNC_FAIL) + pcm_resync |= 1 << i; + } + + for (cnt = 0; cnt < 5 && pcm_resync; cnt++) { + for (i = 0; i < NUM_CHANNELS; i++) + codsp_resync_channel(duslic_id, i); + + udelay(2000); + + pcm_resync = 0; + + for (i = 0; i < NUM_CHANNELS; i++) { + if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL) + pcm_resync |= 1 << i; + } + } + + if (cnt == 5) { + printf("PCM_Resync(%u) not completed\n", duslic_id); + return -2; + } + + revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR); + printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F); + + codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80); /* EDSP_EN */ + + for (i = 0; i < NUM_CHANNELS; i++) { + codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01); + codsp_channel_full_reset(duslic_id, i); + } + + return 0; +} + +int slic_self_test(int duslic_mask) +{ + int slic; + int i; + int r; + long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v; + const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" }; + int error = 0; + + for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */ + if (duslic_mask & (1 << (slic >> 1))) { + r = measure_on_hook_voltages(slic, &vdd, + &v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v); + + printf("SLIC %u measured voltages (x100):\n\t" + "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n", + slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v); + + if (r != 0) + error |= 1 << slic; + + for (i = 0; i < 5; i++) + if (r & (1 << i)) + printf("\t%s out of range\n", err_txt[i]); + } + } + + for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */ + if (duslic_mask & (1 << (slic >> 1))) { + printf("SLIC %u VOICE PATH...CHECKING", slic); + printf("\rSLIC %u VOICE PATH...%s\n", slic, + (r = test_dtmf(slic)) != 0 ? "FAILED " : "PASSED "); + + if (r != 0) + error |= 1 << slic; + } + } + + return(error); +} + +#if defined(CONFIG_NETTA_ISDN) + +#define SPIENS1 (1 << (31 - 15)) +#define SPIENS2 (1 << (31 - 19)) + +static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 }; +int s_initialized = 0; + +static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value) +{ + unsigned int rx, v; + + _PORTB_SET(spiens_mask_tab[s_id], 0); + + rx = __SPI_Transfer(address); + + switch (address & 0xF0) { + case 0x60: /* write byte register */ + case 0x70: + rx = __SPI_Transfer(value); + break; + + case 0xE0: /* read R6 register */ + v = __SPI_Transfer(0); + + rx = (rx << 8) | v; + + break; + + case 0xF0: /* read byte register */ + rx = __SPI_Transfer(0); + + break; + } + + _PORTB_SET(spiens_mask_tab[s_id], 1); + + return rx; +} + +static void s_write_BR(int s_id, unsigned int regno, unsigned int val) +{ + unsigned int address; + unsigned int v; + + address = 0x70 | (regno & 15); + val &= 0xff; + + v = s_transfer_internal(s_id, address, val); +} + +static void s_write_OR(int s_id, unsigned int regno, unsigned int val) +{ + unsigned int address; + unsigned int v; + + address = 0x70 | (regno & 15); + val &= 0xff; + + v = s_transfer_internal(s_id, address, val); +} + +static void s_write_NR(int s_id, unsigned int regno, unsigned int val) +{ + unsigned int address; + unsigned int v; + + address = (regno & 7) << 4; + val &= 0xf; + + v = s_transfer_internal(s_id, address | val, 0x00); +} + +#define BR7_IFR 0x08 /* IDL2 free run */ +#define BR7_ICSLSB 0x04 /* IDL2 clock speed LSB */ + +#define BR15_OVRL_REG_EN 0x80 +#define OR7_D3VR 0x80 /* disable 3V regulator */ + +#define OR8_TEME 0x10 /* TE mode enable */ +#define OR8_MME 0x08 /* master mode enable */ + +void s_initialize(void) +{ + int s_id; + + for (s_id = 0; s_id < 2; s_id++) { + s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB); + s_write_BR(s_id, 15, BR15_OVRL_REG_EN); + s_write_OR(s_id, 8, OR8_TEME | OR8_MME); + s_write_OR(s_id, 7, OR7_D3VR); + s_write_OR(s_id, 6, 0); + s_write_BR(s_id, 15, 0); + s_write_NR(s_id, 3, 0); + } +} + +#endif + +int board_post_codec(int flags) +{ + int j; + int r; + int duslic_mask; + + printf("board_post_dsp\n"); + +#if defined(CONFIG_NETTA_ISDN) + if (s_initialized == 0) { + s_initialize(); + s_initialized = 1; + + printf("s_initialized\n"); + + udelay(20000); + } +#endif + duslic_mask = 0; + + for (j = 0; j < MAX_DUSLIC; j++) { + if (codsp_chip_full_reset(j) < 0) + printf("Error initializing DuSLIC#%d\n", j); + else + duslic_mask |= 1 << j; + } + + if (duslic_mask != 0) { + printf("Testing SLICs...\n"); + + r = slic_self_test(duslic_mask); + for (j = 0; j < MAX_SLICS; j++) { + if (duslic_mask & (1 << (j >> 1))) + printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK"); + } + } + printf("DuSLIC self test finished\n"); + + return 0; /* return -1 on error */ +} diff --git a/board/netta/config.mk b/board/netta/config.mk new file mode 100644 index 0000000..8497ebc --- /dev/null +++ b/board/netta/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# netVia Boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/netta/dsp.c b/board/netta/dsp.c new file mode 100644 index 0000000..66e0b85 --- /dev/null +++ b/board/netta/dsp.c @@ -0,0 +1,1208 @@ +/* + * Intracom TI6711/TI6412 DSP + */ + +#include +#include + +#include "mpc8xx.h" + +struct ram_range { + u32 start; + u32 size; +}; + +#if defined(CONFIG_NETTA_6412) + +static const struct ram_range int_ram[] = { + { 0x00000000U, 0x00040000U }, +}; + +static const struct ram_range ext_ram[] = { + { 0x80000000U, 0x00100000U }, +}; + +static const struct ram_range ranges[] = { + { 0x00000000U, 0x00040000U }, + { 0x80000000U, 0x00100000U }, +}; + +static inline u16 bit_invert(u16 d) +{ + register u8 i; + register u16 r; + register u16 bit; + + r = 0; + for (i = 0; i < 16; i++) { + bit = d & (1 << i); + if (bit != 0) + r |= 1 << (15 - i); + } + return r; +} + +#else + +static const struct ram_range int_ram[] = { + { 0x00000000U, 0x00010000U }, +}; + +static const struct ram_range ext_ram[] = { + { 0x80000000U, 0x00100000U }, +}; + +static const struct ram_range ranges[] = { + { 0x00000000U, 0x00010000U }, + { 0x80000000U, 0x00100000U }, +}; + +#endif + +/*******************************************************************************************************/ + +static inline int addr_in_int_ram(u32 addr) +{ + int i; + + for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++) + if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size) + return 1; + + return 0; +} + +static inline int addr_in_ext_ram(u32 addr) +{ + int i; + + for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++) + if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size) + return 1; + + return 0; +} + +/*******************************************************************************************************/ + +#define DSP_HPIC 0x0 +#define DSP_HPIA 0x4 +#define DSP_HPID1 0x8 +#define DSP_HPID2 0xC + +static u32 dummy_delay; +static volatile u32 *ti6711_delay = &dummy_delay; + +static inline void dsp_go_slow(void) +{ + volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl; +#if defined(CONFIG_NETTA_6412) + memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX; +#else + memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX; +#endif + memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX; + + ti6711_delay = (u32 *)DUMMY_BASE; +} + +static inline void dsp_go_fast(void) +{ + volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl; +#if defined(CONFIG_NETTA_6412) + memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; +#else + memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK; +#endif + memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; + + ti6711_delay = &dummy_delay; +} + +/*******************************************************************************************************/ + +static inline void dsp_delay(void) +{ + /* perform ti6711_delay chip select read to have a small delay */ + (void) *(volatile u32 *)ti6711_delay; +} + +static inline u16 dsp_read_hpic(void) +{ +#if defined(CONFIG_NETTA_6412) + return bit_invert(*((volatile u16 *)DSP_BASE)); +#else + return *((volatile u16 *)DSP_BASE); +#endif +} + +static inline void dsp_write_hpic(u16 val) +{ +#if defined(CONFIG_NETTA_6412) + *((volatile u16 *)DSP_BASE) = bit_invert(val); +#else + *((volatile u16 *)DSP_BASE) = val; +#endif +} + +static inline void dsp_reset(void) +{ +#if defined(CONFIG_NETTA_6412) + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15)); + udelay(500); + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 15)); + udelay(500); +#else + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7)); + udelay(250); + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7)); + udelay(250); +#endif +} + +static inline u32 dsp_read_hpic_word(u32 addr) +{ + u32 val; + volatile u16 *p; +#if defined(CONFIG_NETTA_6412) + p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); + + val = ((u32) bit_invert(p[0]) << 16); + /* dsp_delay(); */ + + val |= bit_invert(p[1]); + /* dsp_delay(); */ +#else + p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); + + val = ((u32) p[0] << 16); + dsp_delay(); + + val |= p[1]; + dsp_delay(); +#endif + return val; +} + +static inline u16 dsp_read_hpic_hi_hword(u32 addr) +{ +#if defined(CONFIG_NETTA_6412) + return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr)); +#else + return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr); +#endif +} + +static inline u16 dsp_read_hpic_lo_hword(u32 addr) +{ +#if defined(CONFIG_NETTA_6412) + return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2)); +#else + return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2); +#endif +} + +static inline void dsp_wait_hrdy(void) +{ + int i; + + i = 0; +#if defined(CONFIG_NETTA_6412) + while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) { +#else + while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { +#endif + dsp_delay(); + i++; + } +} + +static inline void dsp_write_hpic_word(u32 addr, u32 val) +{ + volatile u16 *p; +#if defined(CONFIG_NETTA_6412) + p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); + p[0] = bit_invert((u16)(val >> 16)); + /* dsp_delay(); */ + + p[1] = bit_invert((u16)val); + /* dsp_delay(); */ +#else + p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); + p[0] = (u16)(val >> 16); + dsp_delay(); + + p[1] = (u16)val; + dsp_delay(); +#endif +} + +static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h) +{ +#if defined(CONFIG_NETTA_6412) + *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h); +#else + + *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h; +#endif +} + +static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l) +{ +#if defined(CONFIG_NETTA_6412) + *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l); +#else + *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l; +#endif +} + +/********************************************************************/ + +static inline void c62_write_word(u32 addr, u32 val) +{ + dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); +#endif + dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); +#endif + + dsp_wait_hrdy(); +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); +#endif + dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16)); +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); + + /* dsp_wait_hrdy(); + dsp_delay(); */ +#endif + dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val); +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); +#endif +} + +static u32 c62_read_word(u32 addr) +{ + u32 val; + + dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); +#endif + dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); +#endif + + /* FETCH */ +#if defined(CONFIG_NETTA_6412) + dsp_write_hpic_word(DSP_HPIC, 0x00100010); +#else + dsp_write_hpic(0x10); + dsp_delay(); +#endif + dsp_wait_hrdy(); +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); +#endif + val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16; +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); + + /* dsp_wait_hrdy(); + dsp_delay(); */ +#endif + val |= dsp_read_hpic_lo_hword(DSP_HPID2); +#if !defined(CONFIG_NETTA_6412) + dsp_delay(); +#endif + return val; +} + +static inline void c62_read(u32 addr, u32 *buffer, int numdata) +{ + int i; + + if (numdata <= 0) + return; + + for (i = 0; i < numdata; i++) { + *buffer++ = c62_read_word(addr); + addr += 4; + } +} + +static inline u32 c62_checksum(u32 addr, int numdata) +{ + int i; + u32 chksum; + + chksum = 0; + for (i = 0; i < numdata; i++) { + chksum += c62_read_word(addr); + addr += 4; + } + + return chksum; +} + +static inline void c62_write(u32 addr, const u32 *buffer, int numdata) +{ + int i; + + if (numdata <= 0) + return; + + for (i = 0; i < numdata; i++) { + c62_write_word(addr, *buffer++); + addr += 4; + } +} + +static inline int c62_write_word_validated(u32 addr, u32 val) +{ + c62_write_word(addr, val); + return c62_read_word(addr) == val ? 0 : -1; +} + +static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata) +{ + int i, r; + + if (numdata <= 0) + return 0; + + for (i = 0; i < numdata; i++) { + r = c62_write_word_validated(addr, *buffer++); + if (r < 0) + return r; + addr += 4; + } + return 0; +} + +#if defined(CONFIG_NETTA_6412) + +#define DRAM_REGS_BASE 0x1800000 + +#define GBLCTL DRAM_REGS_BASE +#define CECTL1 (DRAM_REGS_BASE + 0x4) +#define CECTL0 (DRAM_REGS_BASE + 0x8) +#define CECTL2 (DRAM_REGS_BASE + 0x10) +#define CECTL3 (DRAM_REGS_BASE + 0x14) +#define SDCTL (DRAM_REGS_BASE + 0x18) +#define SDTIM (DRAM_REGS_BASE + 0x1C) +#define SDEXT (DRAM_REGS_BASE + 0x20) +#define SESEC1 (DRAM_REGS_BASE + 0x44) +#define SESEC0 (DRAM_REGS_BASE + 0x48) +#define SESEC2 (DRAM_REGS_BASE + 0x50) +#define SESEC3 (DRAM_REGS_BASE + 0x54) + +#define MAR128 0x1848200 +#define MAR129 0x1848204 + +void dsp_dram_initialize(void) +{ + c62_write_word(GBLCTL, 0x120E4); + c62_write_word(CECTL1, 0x18); + c62_write_word(CECTL0, 0xD0); + c62_write_word(CECTL2, 0x18); + c62_write_word(CECTL3, 0x18); + c62_write_word(SDCTL, 0x47115000); + c62_write_word(SDTIM, 1536); + c62_write_word(SDEXT, 0x534A9); +#if 0 + c62_write_word(SESEC1, 0); + c62_write_word(SESEC0, 0); + c62_write_word(SESEC2, 0); + c62_write_word(SESEC3, 0); +#endif + c62_write_word(MAR128, 1); + c62_write_word(MAR129, 0); +} + +#endif + +static inline void dsp_init_hpic(void) +{ + int i; + volatile u16 *p; +#if defined(CONFIG_NETTA_6412) + dsp_go_fast(); +#else + dsp_go_slow(); +#endif + i = 0; +#if defined(CONFIG_NETTA_6412) + while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) { +#else + while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { +#endif + dsp_delay(); + i++; + } + + if (i == 1000) + printf("HRDY stuck\n"); + + dsp_delay(); + + /* write control register */ + p = (volatile u16 *)DSP_BASE; + p[0] = 0x0000; + dsp_delay(); + p[1] = 0x0000; + dsp_delay(); + +#if !defined(CONFIG_NETTA_6412) + dsp_go_fast(); +#endif +} + +/***********************************************************************************************************/ + +#if !defined(CONFIG_NETTA_6412) + +static const u8 bootstrap_rbin[5084] = { + 0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, + 0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, + 0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x03, 0x62, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x10, 0x5a, + 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, + 0x02, 0x00, 0x00, 0xaa, 0x02, 0x10, 0xac, 0xe2, 0x00, 0x00, 0x20, 0x00, + 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x9f, 0x7a, + 0x30, 0x00, 0x08, 0x10, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x04, 0x28, + 0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a, + 0x00, 0x10, 0x02, 0xe4, 0x00, 0x00, 0x60, 0x00, 0x00, 0x02, 0xd6, 0xc8, + 0x00, 0x10, 0x02, 0xf4, 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, + 0x03, 0x1a, 0xf7, 0xca, 0x03, 0x10, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28, + 0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a, + 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x97, 0xcf, 0x5a, + 0x02, 0x90, 0x02, 0xf6, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, + 0x02, 0x96, 0x10, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x0c, 0x03, 0x62, + 0x00, 0x00, 0x80, 0x00, 0x02, 0x90, 0x10, 0x5a, 0x00, 0x00, 0x04, 0x28, + 0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a, + 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x03, 0x18, 0x2f, 0xda, + 0x03, 0x10, 0x02, 0xf6, 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, + 0x03, 0x1a, 0x10, 0x8a, 0x03, 0x10, 0x02, 0xf6, 0x00, 0x19, 0x2e, 0x28, + 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x03, 0x00, 0x00, 0xaa, + 0x02, 0x98, 0xac, 0xe2, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x64, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0xbf, 0x7a, 0x22, 0x90, 0x02, 0xe6, + 0x00, 0x00, 0x60, 0x00, 0x22, 0x96, 0xd6, 0x8a, 0x22, 0x90, 0x02, 0xf6, + 0x22, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x22, 0x96, 0xf7, 0x8a, + 0x22, 0x90, 0x02, 0xf6, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, + 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, + 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, + 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x02, 0x64, + 0x00, 0x00, 0x60, 0x00, 0x00, 0x80, 0x4f, 0x58, 0x02, 0x00, 0x12, 0x2a, + 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, + 0x02, 0x95, 0x8c, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x12, 0x28, + 0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, + 0x02, 0x11, 0xad, 0xca, 0x02, 0x00, 0x02, 0x76, 0x92, 0x00, 0x12, 0x2a, + 0x92, 0x00, 0xc8, 0x6a, 0x92, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, + 0x92, 0x95, 0x6b, 0xca, 0x92, 0x90, 0x02, 0xf6, 0x80, 0x00, 0x12, 0x28, + 0x80, 0x00, 0xc8, 0x68, 0x82, 0x00, 0x02, 0x66, 0x80, 0x00, 0x12, 0x28, + 0x80, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, 0x82, 0x11, 0x6b, 0x8a, + 0x82, 0x00, 0x02, 0x76, 0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x95, 0x4a, 0xca, + 0x02, 0x90, 0x02, 0xf6, 0x90, 0x00, 0x12, 0x28, 0x90, 0x00, 0xc8, 0x68, + 0x92, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, 0x92, 0x11, 0x29, 0xca, + 0x92, 0x00, 0x02, 0x76, 0x82, 0x00, 0x12, 0x2a, 0x82, 0x00, 0xc8, 0x6a, + 0x82, 0x10, 0x02, 0xe6, 0x80, 0x00, 0x12, 0x28, 0x80, 0x00, 0xc8, 0x68, + 0x00, 0x00, 0x20, 0x00, 0x82, 0x11, 0x29, 0x8a, 0x82, 0x00, 0x02, 0x76, + 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66, + 0x00, 0x00, 0x60, 0x00, 0x02, 0x11, 0x08, 0xca, 0x02, 0x00, 0x02, 0x76, + 0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6, + 0x00, 0x00, 0x60, 0x00, 0x02, 0x97, 0x6f, 0x5a, 0x02, 0x90, 0x02, 0xf6, + 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x64, + 0x00, 0x00, 0x60, 0x00, 0x02, 0x0e, 0xff, 0x5a, 0x02, 0x00, 0x02, 0x76, + 0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x00, 0x10, 0x02, 0xe4, + 0x00, 0x00, 0x60, 0x00, 0x02, 0x83, 0xbf, 0x5a, 0x02, 0x90, 0x02, 0xf6, + 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x64, + 0x00, 0x00, 0x60, 0x00, 0x02, 0x0f, 0xdf, 0x5a, 0x02, 0x00, 0x02, 0x76, + 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66, + 0x00, 0x00, 0x60, 0x00, 0x02, 0x12, 0xf7, 0xca, 0x02, 0x00, 0x02, 0x76, + 0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6, + 0x00, 0x00, 0x60, 0x00, 0x02, 0x96, 0xd6, 0xca, 0x02, 0x90, 0x02, 0xf6, + 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66, + 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x10, 0x85, 0xca, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x04, 0x28, + 0x00, 0x00, 0xc8, 0x68, 0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x04, 0x2a, + 0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x95, 0xca, + 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68, + 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x02, 0x0f, 0xdf, 0x5a, + 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x96, 0x10, 0xca, + 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68, + 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, 0x02, 0x11, 0xef, 0xca, + 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc8, 0x68, + 0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x95, 0xae, 0xca, 0x02, 0x90, 0x02, 0xf6, + 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x10, 0x02, 0xe6, + 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x10, 0x21, 0x0a, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x06, 0x28, + 0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x06, 0x28, + 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, 0x01, 0x8d, 0xae, 0xc8, + 0x01, 0x8d, 0x0c, 0x88, 0x01, 0x80, 0x02, 0x74, 0x00, 0x00, 0x06, 0x28, + 0x00, 0x00, 0xc8, 0x68, 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x06, 0x28, + 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0xa7, 0xca, + 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc8, 0x68, + 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x00, 0x00, 0x20, 0x00, 0x00, 0x02, 0x31, 0xc8, 0x00, 0x02, 0x10, 0x88, + 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc8, 0x68, + 0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x74, 0xca, 0x02, 0x90, 0x02, 0xf6, + 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x02, 0x80, 0x02, 0x66, + 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x96, 0x52, 0x8a, 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x08, 0x2a, + 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28, + 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x21, 0x0a, + 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc8, 0x68, + 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0xae, 0xc8, 0x00, 0x01, 0x0c, 0x88, + 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc8, 0x68, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0xa7, 0xca, 0x02, 0x00, 0x02, 0x76, + 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6, + 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x96, 0x31, 0xca, 0x02, 0x96, 0x10, 0x8a, 0x02, 0x90, 0x02, 0xf6, + 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x10, 0x02, 0xe6, + 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x12, 0x74, 0xca, 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x08, 0x2a, + 0x02, 0x00, 0xc8, 0x6a, 0x02, 0x90, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a, + 0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x52, 0x8a, + 0x02, 0x90, 0x02, 0xf6, 0x90, 0x00, 0x1b, 0x10, 0x90, 0x19, 0x2e, 0x28, + 0x90, 0x00, 0x00, 0x68, 0x90, 0x00, 0x02, 0x64, 0x00, 0x00, 0x20, 0x00, + 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x64, + 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x0a, 0x28, 0x01, 0x8f, 0xbd, 0x88, + 0x00, 0x00, 0xc8, 0x68, 0x01, 0x80, 0x02, 0x74, 0x00, 0x00, 0x0a, 0x28, + 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x0a, 0x2a, + 0x02, 0x00, 0xc8, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x03, 0x9c, 0x88, + 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x0a, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x00, 0x10, 0x02, 0xe4, 0x02, 0x00, 0x0a, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x00, 0x00, 0x20, 0x00, 0x00, 0x03, 0x1b, 0xc8, 0x00, 0x02, 0x17, 0x88, + 0x00, 0x10, 0x02, 0xf4, 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, + 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x0a, 0x2a, 0x02, 0x00, 0xc8, 0x6a, + 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x00, 0x00, 0x01, 0x82, 0x42, 0x64, + 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x10, 0x07, 0xca, 0x02, 0x0c, 0x9f, 0xfa, 0x02, 0x00, 0x02, 0x76, + 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, + 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x80, 0x58, 0x03, 0x00, 0x10, 0x2a, + 0x02, 0x04, 0x03, 0xe2, 0x02, 0x18, 0x56, 0x15, 0x02, 0x93, 0xcf, 0x5a, + 0x00, 0x94, 0x03, 0xa2, 0x02, 0x18, 0x56, 0x14, 0x00, 0x00, 0x20, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x98, 0x56, 0x15, 0x00, 0x90, 0x4a, 0x58, + 0x81, 0x98, 0xa0, 0x14, 0x04, 0x04, 0x00, 0x59, 0x00, 0x00, 0x06, 0x12, + 0x00, 0x90, 0x4a, 0x59, 0x02, 0x98, 0x56, 0x15, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x1b, 0x40, 0x5b, 0x03, 0x80, 0x00, 0xf9, 0x02, 0x00, 0x00, 0xa9, + 0x81, 0x98, 0xa0, 0x14, 0x01, 0x20, 0x00, 0x59, 0x04, 0x04, 0x01, 0xa1, + 0x20, 0x00, 0x02, 0x13, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x10, 0x6c, 0xe1, + 0x00, 0x94, 0x4a, 0x59, 0x02, 0x98, 0x56, 0x14, 0xa3, 0x9c, 0x0f, 0xf9, + 0x20, 0x03, 0xe0, 0x5b, 0x81, 0x98, 0xa0, 0x14, 0x04, 0x04, 0x00, 0x59, + 0x01, 0x20, 0x01, 0xa0, 0x00, 0x94, 0x4a, 0x59, 0xa0, 0x10, 0x6c, 0xe0, + 0xa3, 0x9c, 0x0f, 0xf9, 0x81, 0x98, 0x60, 0x14, 0x04, 0x04, 0x00, 0x59, + 0x01, 0x20, 0x01, 0xa0, 0x00, 0x94, 0x4a, 0x59, 0xa0, 0x10, 0x6c, 0xe0, + 0xa3, 0x9c, 0x0f, 0xf9, 0x81, 0x98, 0x20, 0x14, 0x02, 0x84, 0x00, 0x59, + 0x01, 0x20, 0x01, 0xa0, 0xa0, 0x10, 0x6c, 0xe0, 0x01, 0x14, 0x01, 0xa1, + 0xa3, 0x9c, 0x0f, 0xf8, 0x00, 0x90, 0x03, 0xa2, 0xa0, 0x10, 0x6c, 0xe0, + 0xa3, 0x9c, 0x0f, 0xf8, 0x02, 0x00, 0x0c, 0x2b, 0x00, 0x00, 0x00, 0xa8, + 0x02, 0x00, 0xc8, 0x6b, 0x00, 0x00, 0x01, 0xe8, 0x00, 0x10, 0x02, 0xf4, + 0x02, 0x00, 0x0e, 0x2a, 0x02, 0x00, 0xc8, 0x6a, 0x03, 0x90, 0x02, 0xf4, + 0x00, 0x00, 0x10, 0x28, 0x00, 0x00, 0xc8, 0x68, 0x03, 0x80, 0x02, 0x74, + 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x2e, 0x28, + 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x00, 0x80, 0x2f, 0x58, + 0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x90, 0x02, 0xe6, + 0x00, 0x00, 0x60, 0x00, 0x02, 0x95, 0x8c, 0xca, 0x02, 0x90, 0x02, 0xf6, + 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x02, 0x00, 0x02, 0x66, + 0x00, 0x00, 0x60, 0x00, 0x02, 0x11, 0xad, 0xca, 0x02, 0x00, 0x02, 0x76, + 0x92, 0x00, 0x12, 0x2a, 0x92, 0x00, 0xc6, 0x6a, 0x92, 0x90, 0x02, 0xe6, + 0x00, 0x00, 0x60, 0x00, 0x92, 0x95, 0x6b, 0xca, 0x92, 0x90, 0x02, 0xf6, + 0x80, 0x00, 0x12, 0x28, 0x80, 0x00, 0xc6, 0x68, 0x82, 0x00, 0x02, 0x66, + 0x80, 0x00, 0x12, 0x28, 0x80, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00, + 0x82, 0x11, 0x6b, 0x8a, 0x82, 0x00, 0x02, 0x76, 0x02, 0x00, 0x12, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, + 0x02, 0x95, 0x4a, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x90, 0x00, 0x12, 0x28, + 0x90, 0x00, 0xc6, 0x68, 0x92, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, + 0x92, 0x11, 0x29, 0xca, 0x92, 0x00, 0x02, 0x76, 0x82, 0x00, 0x12, 0x2a, + 0x82, 0x00, 0xc6, 0x6a, 0x82, 0x10, 0x02, 0xe6, 0x80, 0x00, 0x12, 0x28, + 0x80, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00, 0x82, 0x11, 0x29, 0x8a, + 0x82, 0x00, 0x02, 0x76, 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, 0x02, 0x11, 0x08, 0xca, + 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc6, 0x6a, + 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x97, 0x6f, 0x5a, + 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x02, 0x0e, 0xff, 0x5a, + 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x12, 0x2a, 0x02, 0x00, 0xc6, 0x6a, + 0x00, 0x10, 0x02, 0xe4, 0x00, 0x00, 0x60, 0x00, 0x02, 0x83, 0xbf, 0x5a, + 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x12, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x02, 0x0f, 0xdf, 0x5a, + 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, 0x02, 0x12, 0xf7, 0xca, + 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc6, 0x6a, + 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x96, 0xd6, 0xca, + 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x85, 0xca, 0x02, 0x00, 0x02, 0x76, + 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x02, 0x80, 0x02, 0x66, + 0x02, 0x00, 0x04, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x96, 0x95, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28, + 0x00, 0x00, 0xc6, 0x68, 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, + 0x02, 0x0f, 0xdf, 0x5a, 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x04, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, + 0x02, 0x96, 0x10, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28, + 0x00, 0x00, 0xc6, 0x68, 0x02, 0x00, 0x02, 0x66, 0x00, 0x00, 0x60, 0x00, + 0x02, 0x11, 0xef, 0xca, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x04, 0x28, + 0x00, 0x00, 0xc6, 0x68, 0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x04, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x02, 0x95, 0xae, 0xca, + 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc6, 0x6a, + 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x21, 0x0a, 0x02, 0x00, 0x02, 0x76, + 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x01, 0x80, 0x02, 0x64, + 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00, + 0x01, 0x8d, 0xae, 0xc8, 0x01, 0x8d, 0x0c, 0x88, 0x01, 0x80, 0x02, 0x74, + 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x02, 0x00, 0x02, 0x66, + 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x10, 0xa7, 0xca, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x06, 0x28, + 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x06, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x02, 0x31, 0xc8, + 0x00, 0x02, 0x10, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x06, 0x28, + 0x00, 0x00, 0xc6, 0x68, 0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x06, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x74, 0xca, + 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x06, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x02, 0x80, 0x02, 0x66, 0x02, 0x00, 0x06, 0x2a, 0x02, 0x00, 0xc6, 0x6a, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x52, 0x8a, 0x02, 0x90, 0x02, 0xf6, + 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x10, 0x02, 0xe6, + 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x10, 0x21, 0x0a, 0x02, 0x00, 0x02, 0x76, 0x00, 0x00, 0x08, 0x28, + 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x08, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0xae, 0xc8, + 0x00, 0x01, 0x0c, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x08, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28, + 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0xa7, 0xca, + 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, + 0x02, 0x90, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x31, 0xca, 0x02, 0x96, 0x10, 0x8a, + 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, + 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x12, 0x74, 0xca, 0x02, 0x00, 0x02, 0x76, + 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x90, 0x02, 0xe6, + 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x96, 0x52, 0x8a, 0x02, 0x90, 0x02, 0xf6, 0x90, 0x00, 0x19, 0x90, + 0x90, 0x19, 0x2e, 0x28, 0x90, 0x00, 0x00, 0x68, 0x90, 0x00, 0x02, 0x64, + 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x0a, 0x28, + 0x01, 0x8f, 0xbd, 0x88, 0x00, 0x00, 0xc6, 0x68, 0x01, 0x80, 0x02, 0x74, + 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x02, 0x64, + 0x02, 0x00, 0x0a, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, + 0x00, 0x03, 0x9c, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x0a, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x10, 0x02, 0xe4, 0x02, 0x00, 0x0a, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x03, 0x1b, 0xc8, + 0x00, 0x02, 0x17, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x19, 0x2e, 0x28, + 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x0a, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x82, 0x22, 0x64, 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x10, 0x07, 0xca, 0x02, 0x0c, 0x9f, 0xfa, + 0x02, 0x00, 0x02, 0x76, 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, + 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x80, 0x58, + 0x03, 0x00, 0x10, 0x2a, 0x02, 0x04, 0x03, 0xe3, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x18, 0x56, 0x15, 0x02, 0x93, 0xcf, 0x5a, 0x00, 0x94, 0x03, 0xa2, + 0x02, 0x18, 0x56, 0x14, 0x00, 0x00, 0x20, 0x00, 0x02, 0x98, 0x56, 0x15, + 0x00, 0x90, 0x2a, 0x58, 0x81, 0x98, 0xa0, 0x14, 0x04, 0x04, 0x00, 0x59, + 0x00, 0x00, 0x04, 0x12, 0x00, 0x90, 0x2a, 0x59, 0x02, 0x98, 0x56, 0x14, + 0x00, 0x1b, 0x40, 0x5b, 0x03, 0x80, 0x00, 0xf9, 0x02, 0x00, 0x00, 0xa9, + 0x81, 0x98, 0xa0, 0x14, 0x01, 0x20, 0x00, 0x59, 0x04, 0x04, 0x01, 0xa1, + 0x20, 0x00, 0x00, 0x12, 0xa0, 0x10, 0x6c, 0xe1, 0x00, 0x94, 0x2a, 0x59, + 0x02, 0x98, 0x56, 0x15, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0xa3, 0x9c, 0x0f, 0xf9, 0x20, 0x03, 0xe0, 0x5b, 0x81, 0x98, 0xa0, 0x14, + 0x04, 0x04, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0, 0x00, 0x94, 0x2a, 0x59, + 0xa0, 0x10, 0x6c, 0xe1, 0x00, 0x00, 0x00, 0x00, 0xa3, 0x9c, 0x0f, 0xf9, + 0x81, 0x98, 0x60, 0x14, 0x04, 0x04, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0, + 0x00, 0x94, 0x2a, 0x59, 0xa0, 0x10, 0x6c, 0xe0, 0xa3, 0x9c, 0x0f, 0xf9, + 0x81, 0x98, 0x20, 0x14, 0x02, 0x84, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0, + 0xa0, 0x10, 0x6c, 0xe0, 0x01, 0x14, 0x01, 0xa1, 0xa3, 0x9c, 0x0f, 0xf8, + 0x00, 0x90, 0x03, 0xa2, 0xa0, 0x10, 0x6c, 0xe0, 0xa3, 0x9c, 0x0f, 0xf8, + 0x02, 0x00, 0x0c, 0x2b, 0x00, 0x00, 0x00, 0xa8, 0x02, 0x00, 0xc6, 0x6b, + 0x00, 0x00, 0x01, 0xe8, 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x0e, 0x2a, + 0x02, 0x00, 0xc6, 0x6a, 0x03, 0x90, 0x02, 0xf4, 0x00, 0x00, 0x10, 0x28, + 0x00, 0x00, 0xc6, 0x68, 0x03, 0x80, 0x02, 0x74, 0x00, 0x0c, 0x03, 0x62, + 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc0, 0x69, + 0x02, 0x00, 0x10, 0x2a, 0x02, 0x00, 0x02, 0x76, 0x00, 0x0c, 0x03, 0x62, + 0x00, 0x00, 0x80, 0x00, 0x01, 0xbc, 0x54, 0xf6, 0x02, 0x04, 0x03, 0xe2, + 0x02, 0x13, 0xcf, 0x5a, 0x00, 0x90, 0x03, 0xa2, 0x02, 0x18, 0x50, 0x2a, + 0x02, 0x00, 0x00, 0x6a, 0x00, 0x10, 0x03, 0x62, 0x01, 0x97, 0x30, 0x2a, + 0x01, 0x80, 0x00, 0x6a, 0x00, 0x00, 0x40, 0x00, 0x00, 0x17, 0xb4, 0x28, + 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x3c, 0x2a, + 0x01, 0x80, 0x00, 0x6a, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x04, 0x29, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x69, 0x02, 0x00, 0x10, 0x2a, + 0x02, 0x00, 0x02, 0x76, 0x00, 0x14, 0x4e, 0x28, 0x00, 0x00, 0x00, 0x68, + 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x52, 0x2a, 0x01, 0x80, 0x00, 0x6a, + 0x00, 0x00, 0x40, 0x00, 0x00, 0x11, 0x94, 0x28, 0x00, 0x00, 0x00, 0x68, + 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x5e, 0x2a, 0x01, 0x80, 0x00, 0x6a, + 0x00, 0x00, 0x40, 0x00, 0x02, 0x11, 0x4c, 0x2a, 0x02, 0x00, 0x00, 0x6a, + 0x00, 0x10, 0x03, 0x62, 0x01, 0x97, 0x6c, 0x2a, 0x01, 0x80, 0x00, 0x6a, + 0x02, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x20, 0x00, 0x00, 0x11, 0x4c, 0x28, + 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x7a, 0x2a, + 0x01, 0x80, 0x00, 0x6a, 0x02, 0x00, 0x00, 0xa8, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x04, 0x03, 0xe2, 0x00, 0x12, 0x00, 0x28, 0x02, 0x00, 0x9f, 0xfa, + 0x00, 0x90, 0x03, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, + 0x01, 0xbc, 0x52, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x00, 0x0c, 0x03, 0x62, + 0x00, 0x00, 0x80, 0x00, 0x07, 0xae, 0xfe, 0x2a, 0x07, 0x80, 0x00, 0x6a, + 0x00, 0x10, 0x00, 0x28, 0x02, 0x80, 0x13, 0xa2, 0x0f, 0xff, 0xe3, 0x12, + 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x30, 0x28, + 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, + 0x00, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x90, 0x00, 0x20, 0x90, + 0x01, 0x04, 0x2a, 0x58, 0x00, 0x00, 0x60, 0x00, 0xa0, 0x00, 0x0a, 0x10, + 0x00, 0x00, 0x80, 0x00, 0x02, 0x00, 0x00, 0xfa, 0x02, 0x00, 0xc0, 0x6a, + 0x02, 0x90, 0x02, 0xe6, 0x03, 0x00, 0x08, 0x2a, 0x00, 0x00, 0x40, 0x00, + 0x02, 0x94, 0xcd, 0xfa, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x00, 0xf8, + 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, + 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74, 0x0f, 0xff, 0xfa, 0x90, + 0x00, 0x00, 0x80, 0x00, 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb, + 0x01, 0x80, 0x00, 0xf8, 0x01, 0x90, 0x02, 0xf4, 0x02, 0x60, 0x80, 0x2a, + 0x02, 0x00, 0xdb, 0xeb, 0x02, 0x00, 0x04, 0x28, 0x02, 0x10, 0x02, 0xf4, + 0x02, 0x00, 0x22, 0x66, 0x02, 0x60, 0x88, 0x28, 0x02, 0x00, 0xdb, 0xe8, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76, 0x02, 0x80, 0x42, 0x66, + 0x02, 0x60, 0x8a, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0xc2, 0x66, 0x02, 0x60, 0x92, 0x28, + 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76, + 0x02, 0x80, 0x62, 0x66, 0x02, 0x60, 0x8c, 0x2a, 0x02, 0x00, 0xdb, 0xea, + 0x00, 0x00, 0x20, 0x00, 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x82, 0x66, + 0x02, 0x60, 0x8e, 0x28, 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00, + 0x02, 0x10, 0x02, 0x76, 0x00, 0x00, 0xa2, 0x64, 0x02, 0x60, 0x90, 0x2a, + 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00, 0x00, 0x10, 0x02, 0xf4, + 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x01, 0x90, 0x02, 0xf4, + 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb, 0x00, 0x00, 0x00, 0xa8, + 0x00, 0x10, 0x02, 0xf4, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x19, 0x2a, 0x2a, + 0x02, 0x84, 0x20, 0xfb, 0x02, 0x00, 0x00, 0x6a, 0x02, 0x90, 0x02, 0xf6, + 0x02, 0x98, 0xe0, 0x2a, 0x02, 0x19, 0x2c, 0x2a, 0x02, 0x00, 0x00, 0x6b, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x29, 0x02, 0x80, 0x00, 0x6a, + 0x03, 0x94, 0x10, 0x59, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x12, 0xaa, + 0x00, 0x80, 0x00, 0xa8, 0x04, 0x08, 0x00, 0x28, 0x04, 0x00, 0x00, 0x68, + 0x20, 0x03, 0xe0, 0x5b, 0x90, 0x14, 0x02, 0x64, 0x20, 0x00, 0x00, 0x12, + 0x93, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x00, 0x00, 0x03, 0x20, 0x02, 0x65, + 0x02, 0x19, 0x2a, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x79, + 0x01, 0xa0, 0x36, 0x65, 0x02, 0x00, 0x00, 0x68, 0x80, 0x87, 0xe0, 0x59, + 0x90, 0x14, 0x02, 0x75, 0x02, 0x90, 0x01, 0xa0, 0x00, 0x14, 0x02, 0x64, + 0x00, 0x00, 0x40, 0x00, 0x03, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x60, 0x78, + 0x00, 0x14, 0x02, 0x74, 0x00, 0x19, 0x2a, 0x28, 0x00, 0x00, 0x00, 0x68, + 0x00, 0x18, 0xe0, 0x29, 0x00, 0x00, 0x02, 0x66, 0x00, 0x00, 0x00, 0x68, + 0x00, 0x00, 0x40, 0x00, 0x31, 0x80, 0x80, 0x59, 0x32, 0x19, 0x2e, 0x2a, + 0x32, 0x00, 0x00, 0x6a, 0x31, 0x90, 0x02, 0xf4, 0x30, 0x02, 0x9d, 0x41, + 0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4, + 0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa, + 0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a, + 0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6, + 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64, + 0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74, + 0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, + 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static int load_bootstrap(void) +{ + const u8 *s = bootstrap_rbin; + u32 l = sizeof(bootstrap_rbin); + const u8 *data, *hdr, *h; + u32 chksum, chksum2; + int i, j, rangenr; + u32 start, length; + + if (l < 12) { + printf("bootstrap image corrupted. (too short header)\n"); + return -1; + } + + chksum = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] << 8) | (u32)s[ 7]; + rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] << 8) | (u32)s[11]; + s += 12; l -= 12; + + hdr = s; + s += 8 * rangenr; l -= 8 * rangenr; + data = s; + + /* validate bootstrap image */ + h = hdr; s = data; chksum2 = 0; + for (i = 0; i < rangenr; i++) { + start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; + length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; + h += 8; + + /* too short */ + if (l < length) { + printf("bootstrap image corrupted. (too short data)\n"); + return -1; + } + l -= length; + + j = (int)length / 4; + while (j-- > 0) { + chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] << 8) | (u32)s[3]; + s += 4; + } + } + + /* checksum must match */ + if (chksum != chksum2) { + printf("bootstrap image corrupted. (checksum error)\n"); + return -1; + } + + /* nothing must be left */ + if (l != 0) { + printf("bootstrap image corrupted. (garbage at the end)\n"); + return -1; + } + + /* write the image */ + h = hdr; + s = data; + for (i = 0; i < rangenr; i++) { + start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; + length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; + h += 8; + c62_write(start, (u32 *)s, length / 4); + s += length; + } + + /* and now validate checksum */ + h = hdr; + s = data; + chksum2 = 0; + for (i = 0; i < rangenr; i++) { + start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; + length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; + h += 8; + chksum2 += c62_checksum(start, length / 4); + s += length; + } + + /* checksum must match */ + if (chksum != chksum2) { + printf("bootstrap in DSP memory is corrupted\n"); + return -1; + } + + return 0; +} + +struct host_init { + u32 master_mode; + struct { + u8 port_id; + u8 slot_id; + } ch_serial_map[32]; + u32 clk_divider[2]; + /* pll */ + u32 initmode; + u32 pllm; + u32 div[4]; + u32 oscdiv1; + u32 unused[10]; +}; + +const struct host_init hi_default = { + .master_mode = +#if !defined(CONFIG_NETTA_ISDN) + -1, +#else + 0, +#endif + + .ch_serial_map = { + [ 0] = { .port_id = 2, .slot_id = 16 }, + [ 1] = { .port_id = 2, .slot_id = 17 }, + [ 2] = { .port_id = 2, .slot_id = 18 }, + [ 3] = { .port_id = 2, .slot_id = 19 }, + [ 4] = { .port_id = 2, .slot_id = 20 }, + [ 5] = { .port_id = 2, .slot_id = 21 }, + [ 6] = { .port_id = 2, .slot_id = 22 }, + [ 7] = { .port_id = 2, .slot_id = 23 }, + [ 8] = { .port_id = 2, .slot_id = 24 }, + [ 9] = { .port_id = 2, .slot_id = 25 }, + [10] = { .port_id = 2, .slot_id = 26 }, + [11] = { .port_id = 2, .slot_id = 27 }, + [12] = { .port_id = 2, .slot_id = 28 }, + [13] = { .port_id = 2, .slot_id = 29 }, + [14] = { .port_id = 2, .slot_id = 30 }, + [15] = { .port_id = 2, .slot_id = 31 }, + }, + + /* + dsp_clk(xin, pllm) = xin * pllm + serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1) + */ + + .clk_divider = { + [0] = 47, /* must be 2048Hz */ + [1] = 47, + }, + + .initmode = 1, + .pllm = +#if !defined(CONFIG_NETTA_ISDN) + 8, /* for =~ 25MHz 8 */ +#else + 4, +#endif + .div = { + [0] = 0x8000, + [1] = 0x8000, /* for =~ 25MHz 0x8000 */ + [2] = 0x8001, /* for =~ 25MHz 0x8001 */ + [3] = 0x8001, /* for =~ 25MHz 0x8001 */ + }, + + .oscdiv1 = 0, +}; + +static void hi_write(const struct host_init *hi) +{ + u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)]; + u32 *s; + u32 chksum; + int i; + + memset(hi_buf, 0, sizeof(hi_buf)); + + s = hi_buf; + s++; + *s++ = hi->master_mode; + for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++) + *s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) | + ((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id; + + for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++) + *s++ = hi->clk_divider[i]; + + *s++ = hi->initmode; + *s++ = hi->pllm; + for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++) + *s++ = hi->div[i]; + *s++ = hi->oscdiv1; + + chksum = 0; + for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++) + chksum += hi_buf[i]; + hi_buf[0] = -chksum; + + c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0])); +} + +static void run_bootstrap(void) +{ + dsp_go_slow(); + + hi_write(&hi_default); + + /* signal interrupt */ + dsp_write_hpic(0x0002); + dsp_delay(); + + dsp_go_fast(); +} + +#endif + +/***********************************************************************************************************/ + +int board_post_dsp(int flags) +{ + u32 ramS, ramE; + u32 data, data2; + int i, j, k; +#if !defined(CONFIG_NETTA_6412) + int r; +#endif + dsp_reset(); + dsp_init_hpic(); +#if !defined(CONFIG_NETTA_6412) + dsp_go_slow(); +#endif + data = 0x11223344; + dsp_write_hpic_word(DSP_HPIA, data); + data2 = dsp_read_hpic_word(DSP_HPIA); + if (data2 != 0x11223344) { + printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); + goto err; + } + + data = 0xFFEEDDCC; + dsp_write_hpic_word(DSP_HPIA, data); + data2 = dsp_read_hpic_word(DSP_HPIA); + if (data2 != 0xFFEEDDCC) { + printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); + goto err; + } +#if defined(CONFIG_NETTA_6412) + dsp_dram_initialize(); +#else + r = load_bootstrap(); + if (r < 0) { + printf("BOOTSTRAP: ** ERROR ** failed to load\n"); + goto err; + } + + run_bootstrap(); + + dsp_go_fast(); +#endif + printf(" "); + + /* test RAMs */ + for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) { + + ramS = ranges[k].start; + ramE = ranges[k].start + ranges[k].size; + + for (j = 0; j < 3; j++) { + + printf("\b\b\b\bR%d.%d", k, j); + + for (i = ramS; i < ramE; i += 4) { + + data = 0; + switch (j) { + case 0: data = 0xAA55AA55; break; + case 1: data = 0x55AA55AA; break; + case 2: data = (u32)i; break; + } + + c62_write_word(i, data); + data2 = c62_read_word(i); + if (data != data2) { + printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2); + goto err; + } + } + } + } + + printf("\b\b\b\b \b\b\b\bOK\n"); +#if !defined(CONFIG_NETTA_6412) + /* XXX assume that this works */ + load_bootstrap(); + run_bootstrap(); + dsp_go_fast(); +#endif + return 0; + +err: + return -1; +} + +int board_dsp_reset(void) +{ +#if !defined(CONFIG_NETTA_6412) + int r; +#endif + dsp_reset(); + dsp_init_hpic(); +#if defined(CONFIG_NETTA_6412) + dsp_dram_initialize(); +#else + dsp_go_slow(); + r = load_bootstrap(); + if (r < 0) + return r; + + run_bootstrap(); + dsp_go_fast(); +#endif + return 0; +} diff --git a/board/netta/flash.c b/board/netta/flash.c new file mode 100644 index 0000000..ca3e061 --- /dev/null +++ b/board/netta/flash.c @@ -0,0 +1,508 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_byte(flash_info_t * info, ulong dest, uchar data); +static void flash_get_offsets(ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + + flash_info[0].size = size; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_MX: + printf("MXIC "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + short i; + uchar mid; + uchar pid; + vu_char *caddr = (vu_char *) addr; + ulong base = (ulong) addr; + + + /* Write auto select command: read Manufacturer ID */ + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0x90; + + mid = caddr[0]; + switch (mid) { + case (AMD_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_FUJ; + break; + case (MX_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_MX; + break; + case (STM_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + pid = caddr[1]; /* device ID */ + switch (pid) { + case (AMD_ID_LV400T & 0xFF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV400B & 0xFF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV800T & 0xFF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800B & 0xFF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV160T & 0xFF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160B & 0xFF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + + case (STM_ID_M29W040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & 0xFF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV320B & 0xFF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + printf(" "); + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection: D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (vu_char *) info->start[0]; + + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0xF0; + + udelay(20000); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *) (info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer(0); + last = start; + addr = (vu_char *) (info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (vu_char *) info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + + while (cnt > 0) { + if ((rc = write_byte(info, addr++, *src++)) != 0) { + return (rc); + } + --cnt; + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte(flash_info_t * info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *) (info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *) dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((vu_char *) dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/netta/netta.c b/board/netta/netta.c new file mode 100644 index 0000000..9194bfb --- /dev/null +++ b/board/netta/netta.c @@ -0,0 +1,600 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#include +#include + +#include "mpc8xx.h" + +#ifdef CONFIG_HW_WATCHDOG +#include +#endif + +int fec8xx_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +int fec8xx_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); + +/****************************************************************/ + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +/****************************************************************/ + +/* + * Check Board Identity: + * + * Return 1 always. + */ + +int checkboard(void) +{ + printf ("Intracom NETTA" +#if defined(CONFIG_NETTA_ISDN) + " with ISDN support" +#endif +#if defined(CONFIG_NETTA_6412) + " (DSP:TI6412)" +#else + " (DSP:TI6711)" +#endif + "\n" + ); + return (0); +} + +/****************************************************************/ + +#define _NOT_USED_ 0xFFFFFFFF + +/****************************************************************/ + +#define CS_0000 0x00000000 +#define CS_0001 0x10000000 +#define CS_0010 0x20000000 +#define CS_0011 0x30000000 +#define CS_0100 0x40000000 +#define CS_0101 0x50000000 +#define CS_0110 0x60000000 +#define CS_0111 0x70000000 +#define CS_1000 0x80000000 +#define CS_1001 0x90000000 +#define CS_1010 0xA0000000 +#define CS_1011 0xB0000000 +#define CS_1100 0xC0000000 +#define CS_1101 0xD0000000 +#define CS_1110 0xE0000000 +#define CS_1111 0xF0000000 + +#define BS_0000 0x00000000 +#define BS_0001 0x01000000 +#define BS_0010 0x02000000 +#define BS_0011 0x03000000 +#define BS_0100 0x04000000 +#define BS_0101 0x05000000 +#define BS_0110 0x06000000 +#define BS_0111 0x07000000 +#define BS_1000 0x08000000 +#define BS_1001 0x09000000 +#define BS_1010 0x0A000000 +#define BS_1011 0x0B000000 +#define BS_1100 0x0C000000 +#define BS_1101 0x0D000000 +#define BS_1110 0x0E000000 +#define BS_1111 0x0F000000 + +#define A10_AAAA 0x00000000 +#define A10_AAA0 0x00200000 +#define A10_AAA1 0x00300000 +#define A10_000A 0x00800000 +#define A10_0000 0x00A00000 +#define A10_0001 0x00B00000 +#define A10_111A 0x00C00000 +#define A10_1110 0x00E00000 +#define A10_1111 0x00F00000 + +#define RAS_0000 0x00000000 +#define RAS_0001 0x00040000 +#define RAS_1110 0x00080000 +#define RAS_1111 0x000C0000 + +#define CAS_0000 0x00000000 +#define CAS_0001 0x00010000 +#define CAS_1110 0x00020000 +#define CAS_1111 0x00030000 + +#define WE_0000 0x00000000 +#define WE_0001 0x00004000 +#define WE_1110 0x00008000 +#define WE_1111 0x0000C000 + +#define GPL4_0000 0x00000000 +#define GPL4_0001 0x00001000 +#define GPL4_1110 0x00002000 +#define GPL4_1111 0x00003000 + +#define GPL5_0000 0x00000000 +#define GPL5_0001 0x00000400 +#define GPL5_1110 0x00000800 +#define GPL5_1111 0x00000C00 +#define LOOP 0x00000080 + +#define EXEN 0x00000040 + +#define AMX_COL 0x00000000 +#define AMX_ROW 0x00000020 +#define AMX_MAR 0x00000030 + +#define NA 0x00000008 + +#define UTA 0x00000004 + +#define TODT 0x00000002 + +#define LAST 0x00000001 + +/* #define CAS_LATENCY 3 */ +#define CAS_LATENCY 2 + +const uint sdram_table[0x40] = { + +#if CAS_LATENCY == 3 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, +#endif + +#if CAS_LATENCY == 2 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + +#endif + + /* UPT */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, +}; + +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ +/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ +#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) + +/* 8 */ +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +void check_ram(unsigned int addr, unsigned int size) +{ + unsigned int i, j, v, vv; + volatile unsigned int *p; + unsigned int pv; + + p = (unsigned int *)addr; + pv = (unsigned int)p; + for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) + *p++ = pv; + + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + v = (unsigned int)p; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + p++; + } + + for (j = 0; j < 5; j++) { + switch (j) { + case 0: v = 0x00000000; break; + case 1: v = 0xffffffff; break; + case 2: v = 0x55555555; break; + case 3: v = 0xaaaaaaaa; break; + default:v = 0xdeadbeef; break; + } + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + *p = v; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + *p = ~v; + p++; + } + } +} + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + + upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = MPTPR_PTP_DIV8; + + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initialisation sequence */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ + udelay(1); + + memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ + + udelay(10000); + + { + u32 d1, d2; + + d1 = 0xAA55AA55; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + + d1 = 0x55AA55AA; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + } + + size = get_ram_size((long *)0, SDRAM_MAX_SIZE); + +#if 0 + printf("check 0\n"); + check_ram(( 0 << 20), (2 << 20)); + printf("check 16\n"); + check_ram((16 << 20), (2 << 20)); + printf("check 32\n"); + check_ram((32 << 20), (2 << 20)); + printf("check 48\n"); + check_ram((48 << 20), (2 << 20)); +#endif + + if (size == 0) { + printf("SIZE is zero: LOOP on 0\n"); + for (;;) { + *(volatile u32 *)0 = 0; + (void)*(volatile u32 *)0; + } + } + + return size; +} + +/* ------------------------------------------------------------------------- */ + +int misc_init_r(void) +{ + return(0); +} + +void reset_phys(void) +{ + int phyno; + unsigned short v; + + /* reset the damn phys */ + mii_init(); + + for (phyno = 0; phyno < 32; ++phyno) { + fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); + if (v == 0xFFFF) + continue; + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); + udelay(10000); + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, + PHY_BMCR_RESET | PHY_BMCR_AUTON); + udelay(10000); + } +} + +extern int board_dsp_reset(void); + +int last_stage_init(void) +{ + int r; + + reset_phys(); + r = board_dsp_reset(); + if (r < 0) + printf("*** WARNING *** DSP reset failed (run diagnostics)\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + +/* bits that can have a special purpose or can be configured as inputs/outputs */ +#define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11)) +#define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15)) +#define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5)) +#define PA_ODR_VAL 0 +#define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15)) +#define PA_SP_DIRVAL 0 + +#define PB_GP_INMASK (_B(28) | _B(31)) +#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30)) +#define PB_SP_MASK (_BR(22, 25)) +#define PB_ODR_VAL 0 +#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31)) +#define PB_SP_DIRVAL 0 + +#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15)) +#define PC_GP_OUTMASK (_BW(6) | _BW(12)) +#define PC_SP_MASK (_BW(4) | _BW(8)) +#define PC_SOVAL 0 +#define PC_INTVAL _BW(7) +#define PC_GP_OUTVAL (_BW(6) | _BW(12)) +#define PC_SP_DIRVAL 0 + +#define PD_GP_INMASK 0 +#define PD_GP_OUTMASK _BWR(3, 15) +#define PD_SP_MASK 0 + +#if defined(CONFIG_NETTA_6412) + +#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15)) + +#else + +#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11)) + +#endif + +#define PD_SP_DIRVAL 0 + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* CS1: NAND chip select */ + memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ; + memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); +#if !defined(CONFIG_NETTA_6412) + /* CS2: DSP */ + memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); + memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); +#else + /* CS6: DSP */ + memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); + memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); +#endif + /* CS4: External register chip select */ + memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); + memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); + + /* CS5: dummy for accurate delay */ + memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2); + memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); + + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + ioport->iop_pddat = PD_GP_OUTVAL; + ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; + ioport->iop_pdpar = PD_SP_MASK; + + /* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */ + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include + +extern ulong nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + unsigned long totlen = nand_probe(CFG_NAND_BASE); + + printf ("%4lu MB\n", totlen >> 20); +} +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) + +int pcmcia_init(void) +{ + return 0; +} + +#endif + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif + +#ifdef CONFIG_HW_WATCHDOG + +void hw_watchdog_reset(void) +{ + /* XXX add here the really funky stuff */ +} + +#endif diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds new file mode 100644 index 0000000..9f2901c --- /dev/null +++ b/board/netta/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug new file mode 100644 index 0000000..004e7fd --- /dev/null +++ b/board/netta/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netta2/Makefile b/board/netta2/Makefile new file mode 100644 index 0000000..d457020 --- /dev/null +++ b/board/netta2/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/netta2/config.mk b/board/netta2/config.mk new file mode 100644 index 0000000..8497ebc --- /dev/null +++ b/board/netta2/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# netVia Boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/netta2/flash.c b/board/netta2/flash.c new file mode 100644 index 0000000..a1c87f5 --- /dev/null +++ b/board/netta2/flash.c @@ -0,0 +1,506 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_byte(flash_info_t * info, ulong dest, uchar data); +static void flash_get_offsets(ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size, size << 20); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + flash_info[0].size = size; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_MX: + printf("MXIC "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + short i; + uchar mid; + uchar pid; + vu_char *caddr = (vu_char *) addr; + ulong base = (ulong) addr; + + /* Write auto select command: read Manufacturer ID */ + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0x90; + + mid = caddr[0]; + switch (mid) { + case (AMD_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_FUJ; + break; + case (MX_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_MX; + break; + case (STM_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + pid = caddr[1]; /* device ID */ + switch (pid) { + case (AMD_ID_LV400T & 0xFF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV400B & 0xFF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV800T & 0xFF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800B & 0xFF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV160T & 0xFF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160B & 0xFF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + + case (STM_ID_M29W040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & 0xFF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV320B & 0xFF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + printf(" "); + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection: D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (vu_char *) info->start[0]; + + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0xF0; + + udelay(20000); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *) (info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer(0); + last = start; + addr = (vu_char *) (info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_char *) info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + + while (cnt > 0) { + if ((rc = write_byte(info, addr++, *src++)) != 0) { + return (rc); + } + --cnt; + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte(flash_info_t * info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *) (info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *) dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((vu_char *) dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c new file mode 100644 index 0000000..c9b4051 --- /dev/null +++ b/board/netta2/netta2.c @@ -0,0 +1,670 @@ +/* + * (C) Copyright 2000-2004 + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#include +#include + +#include "mpc8xx.h" + +#ifdef CONFIG_HW_WATCHDOG +#include +#endif + +int fec8xx_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +int fec8xx_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); + +/****************************************************************/ + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +/****************************************************************/ + +/* + * Check Board Identity: + * + * Return 1 always. + */ + +int checkboard(void) +{ + printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION); + return (0); +} + +/****************************************************************/ + +#define _NOT_USED_ 0xFFFFFFFF + +/****************************************************************/ + +#define CS_0000 0x00000000 +#define CS_0001 0x10000000 +#define CS_0010 0x20000000 +#define CS_0011 0x30000000 +#define CS_0100 0x40000000 +#define CS_0101 0x50000000 +#define CS_0110 0x60000000 +#define CS_0111 0x70000000 +#define CS_1000 0x80000000 +#define CS_1001 0x90000000 +#define CS_1010 0xA0000000 +#define CS_1011 0xB0000000 +#define CS_1100 0xC0000000 +#define CS_1101 0xD0000000 +#define CS_1110 0xE0000000 +#define CS_1111 0xF0000000 + +#define BS_0000 0x00000000 +#define BS_0001 0x01000000 +#define BS_0010 0x02000000 +#define BS_0011 0x03000000 +#define BS_0100 0x04000000 +#define BS_0101 0x05000000 +#define BS_0110 0x06000000 +#define BS_0111 0x07000000 +#define BS_1000 0x08000000 +#define BS_1001 0x09000000 +#define BS_1010 0x0A000000 +#define BS_1011 0x0B000000 +#define BS_1100 0x0C000000 +#define BS_1101 0x0D000000 +#define BS_1110 0x0E000000 +#define BS_1111 0x0F000000 + +#define GPL0_AAAA 0x00000000 +#define GPL0_AAA0 0x00200000 +#define GPL0_AAA1 0x00300000 +#define GPL0_000A 0x00800000 +#define GPL0_0000 0x00A00000 +#define GPL0_0001 0x00B00000 +#define GPL0_111A 0x00C00000 +#define GPL0_1110 0x00E00000 +#define GPL0_1111 0x00F00000 + +#define GPL1_0000 0x00000000 +#define GPL1_0001 0x00040000 +#define GPL1_1110 0x00080000 +#define GPL1_1111 0x000C0000 + +#define GPL2_0000 0x00000000 +#define GPL2_0001 0x00010000 +#define GPL2_1110 0x00020000 +#define GPL2_1111 0x00030000 + +#define GPL3_0000 0x00000000 +#define GPL3_0001 0x00004000 +#define GPL3_1110 0x00008000 +#define GPL3_1111 0x0000C000 + +#define GPL4_0000 0x00000000 +#define GPL4_0001 0x00001000 +#define GPL4_1110 0x00002000 +#define GPL4_1111 0x00003000 + +#define GPL5_0000 0x00000000 +#define GPL5_0001 0x00000400 +#define GPL5_1110 0x00000800 +#define GPL5_1111 0x00000C00 +#define LOOP 0x00000080 + +#define EXEN 0x00000040 + +#define AMX_COL 0x00000000 +#define AMX_ROW 0x00000020 +#define AMX_MAR 0x00000030 + +#define NA 0x00000008 + +#define UTA 0x00000004 + +#define TODT 0x00000002 + +#define LAST 0x00000001 + +#define A10_AAAA GPL0_AAAA +#define A10_AAA0 GPL0_AAA0 +#define A10_AAA1 GPL0_AAA1 +#define A10_000A GPL0_000A +#define A10_0000 GPL0_0000 +#define A10_0001 GPL0_0001 +#define A10_111A GPL0_111A +#define A10_1110 GPL0_1110 +#define A10_1111 GPL0_1111 + +#define RAS_0000 GPL1_0000 +#define RAS_0001 GPL1_0001 +#define RAS_1110 GPL1_1110 +#define RAS_1111 GPL1_1111 + +#define CAS_0000 GPL2_0000 +#define CAS_0001 GPL2_0001 +#define CAS_1110 GPL2_1110 +#define CAS_1111 GPL2_1111 + +#define WE_0000 GPL3_0000 +#define WE_0001 GPL3_0001 +#define WE_1110 GPL3_1110 +#define WE_1111 GPL3_1111 + +/* #define CAS_LATENCY 3 */ +#define CAS_LATENCY 2 + +const uint sdram_table[0x40] = { + +#if CAS_LATENCY == 3 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, +#endif + +#if CAS_LATENCY == 2 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + +#endif + + /* UPT */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, +}; + +#if CONFIG_NETTA2_VERSION == 2 +static const uint nandcs_table[0x40] = { + /* RSS */ + CS_1000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1110 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111, + CS_0000 | GPL4_0001 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ + + /* RBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_1000 | GPL4_1111 | GPL5_1110 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0001 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, + + /* WBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* UPT */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 , + CS_0001 | LAST, +}; +#endif + +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ +/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ +#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) + +/* 8 */ +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +void check_ram(unsigned int addr, unsigned int size) +{ + unsigned int i, j, v, vv; + volatile unsigned int *p; + unsigned int pv; + + p = (unsigned int *)addr; + pv = (unsigned int)p; + for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) + *p++ = pv; + + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + v = (unsigned int)p; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + p++; + } + + for (j = 0; j < 5; j++) { + switch (j) { + case 0: v = 0x00000000; break; + case 1: v = 0xffffffff; break; + case 2: v = 0x55555555; break; + case 3: v = 0xaaaaaaaa; break; + default:v = 0xdeadbeef; break; + } + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + *p = v; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + *p = ~v; + p++; + } + } +} + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + + upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = MPTPR_PTP_DIV8; + + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initialisation sequence */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ + udelay(1); + + memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ + + udelay(10000); + + { + u32 d1, d2; + + d1 = 0xAA55AA55; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + + d1 = 0x55AA55AA; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + hang(); + } + } + + size = get_ram_size((long *)0, SDRAM_MAX_SIZE); + + if (size == 0) { + printf("SIZE is zero: LOOP on 0\n"); + for (;;) { + *(volatile u32 *)0 = 0; + (void)*(volatile u32 *)0; + } + } + + return size; +} + +/* ------------------------------------------------------------------------- */ + +void reset_phys(void) +{ + int phyno; + unsigned short v; + + udelay(10000); + /* reset the damn phys */ + mii_init(); + + for (phyno = 0; phyno < 32; ++phyno) { + fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); + if (v == 0xFFFF) + continue; + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); + udelay(10000); + fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, + PHY_BMCR_RESET | PHY_BMCR_AUTON); + udelay(10000); + } +} + +/* ------------------------------------------------------------------------- */ + +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + +/* bits that can have a special purpose or can be configured as inputs/outputs */ +#define PA_GP_INMASK 0 +#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) +#define PA_SP_MASK 0 +#define PA_ODR_VAL 0 +#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) +#define PA_SP_DIRVAL 0 + +#define PB_GP_INMASK _B(28) +#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) +#define PB_SP_MASK (_BR(22, 25)) +#define PB_ODR_VAL 0 +#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) +#define PB_SP_DIRVAL 0 + +#if CONFIG_NETTA2_VERSION == 1 +#define PC_GP_INMASK _BW(12) +#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) +#elif CONFIG_NETTA2_VERSION == 2 +#define PC_GP_INMASK (_BW(13) | _BW(15)) +#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) +#endif +#define PC_SP_MASK 0 +#define PC_SOVAL 0 +#define PC_INTVAL 0 +#define PC_GP_OUTVAL (_BW(10) | _BW(11)) +#define PC_SP_DIRVAL 0 + +#if CONFIG_NETTA2_VERSION == 1 +#define PE_GP_INMASK _B(31) +#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) +#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) +#elif CONFIG_NETTA2_VERSION == 2 +#define PE_GP_INMASK _BR(28, 31) +#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) +#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) +#endif +#define PE_SP_MASK 0 +#define PE_ODR_VAL 0 +#define PE_SP_DIRVAL 0 + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* NAND chip select */ +#if CONFIG_NETTA2_VERSION == 1 + memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); + memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); +#elif CONFIG_NETTA2_VERSION == 2 + upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); + memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); + memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); + memctl->memc_mamr = 0; /* all clear */ +#endif + + /* DSP chip select */ + memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); + memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); + +#if CONFIG_NETTA2_VERSION == 1 + memctl->memc_br4 &= ~BR_V; +#endif + memctl->memc_br5 &= ~BR_V; + memctl->memc_br6 &= ~BR_V; + memctl->memc_br7 &= ~BR_V; + + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + cpm->cp_pedat = PE_GP_OUTVAL; + cpm->cp_peodr = PE_ODR_VAL; + cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; + cpm->cp_pepar = PE_SP_MASK; + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include + +extern ulong nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + unsigned long totlen; + + totlen = nand_probe(CFG_NAND_BASE); + printf ("%4lu MB\n", totlen >> 20); +} +#endif + +#ifdef CONFIG_HW_WATCHDOG + +void hw_watchdog_reset(void) +{ + /* XXX add here the really funky stuff */ +} + +#endif + +#ifdef CONFIG_SHOW_ACTIVITY + +/* called from timer interrupt every 1/CFG_HZ sec */ +void board_show_activity(ulong timestamp) +{ +} + +/* called when looping */ +void show_activity(int arg) +{ +} + +#endif + +#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + /* printf("overwrite_console called\n"); */ + return 0; +} +#endif + +extern int drv_phone_init(void); +extern int drv_phone_use_me(void); +extern int drv_phone_is_idle(void); + +int misc_init_r(void) +{ + return 0; +} + +int last_stage_init(void) +{ +#if CONFIG_NETTA2_VERSION == 2 + int i; +#endif + +#if CONFIG_NETTA2_VERSION == 2 + /* assert peripheral reset */ + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); + for (i = 0; i < 10; i++) + udelay(1000); + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12); +#endif + reset_phys(); + + return 0; +} diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds new file mode 100644 index 0000000..9f2901c --- /dev/null +++ b/board/netta2/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug new file mode 100644 index 0000000..004e7fd --- /dev/null +++ b/board/netta2/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netvia/Makefile b/board/netvia/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/netvia/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/netvia/config.mk b/board/netvia/config.mk new file mode 100644 index 0000000..9dddaad --- /dev/null +++ b/board/netvia/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# netVia Boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/netvia/flash.c b/board/netvia/flash.c new file mode 100644 index 0000000..d31f770 --- /dev/null +++ b/board/netvia/flash.c @@ -0,0 +1,511 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_byte(flash_info_t * info, ulong dest, uchar data); +static void flash_get_offsets(ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + + flash_info[0].size = size; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_MX: + printf("MXIC "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + short i; + uchar mid; + uchar pid; + vu_char *caddr = (vu_char *) addr; + ulong base = (ulong) addr; + + + /* Write auto select command: read Manufacturer ID */ + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0x90; + + mid = caddr[0]; + switch (mid) { + case (AMD_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_FUJ; + break; + case (MX_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_MX; + break; + case (STM_MANUFACT & 0xFF): + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + pid = caddr[1]; /* device ID */ + switch (pid) { + case (AMD_ID_LV400T & 0xFF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV400B & 0xFF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 512 kB */ + + case (AMD_ID_LV800T & 0xFF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800B & 0xFF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV160T & 0xFF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160B & 0xFF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + + case (STM_ID_M29W040B & 0xFF): + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; + +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & 0xFF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV320B & 0xFF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + printf(" "); + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection: D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + caddr = (vu_char *) info->start[0]; + + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0xF0; + + udelay(20000); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *) (info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer(0); + last = start; + addr = (vu_char *) (info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (vu_char *) info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int rc; + + while (cnt > 0) { + if ((rc = write_byte(info, addr++, *src++)) != 0) { + return (rc); + } + --cnt; + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte(flash_info_t * info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *) (info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *) dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((vu_char *) dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c new file mode 100644 index 0000000..fb7f770 --- /dev/null +++ b/board/netvia/netvia.c @@ -0,0 +1,432 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetVia board + */ + +#include +#include "mpc8xx.h" + +/****************************************************************/ + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 +/* last value written to the external register; we cannot read back */ +unsigned int last_er_val; +#endif + +/****************************************************************/ + +/****************************************************************/ + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +/****************************************************************/ + +#define _NOT_USED_ 0xFFFFFFFF + +/****************************************************************/ + +#define CS_0000 0x00000000 +#define CS_0001 0x10000000 +#define CS_0010 0x20000000 +#define CS_0011 0x30000000 +#define CS_0100 0x40000000 +#define CS_0101 0x50000000 +#define CS_0110 0x60000000 +#define CS_0111 0x70000000 +#define CS_1000 0x80000000 +#define CS_1001 0x90000000 +#define CS_1010 0xA0000000 +#define CS_1011 0xB0000000 +#define CS_1100 0xC0000000 +#define CS_1101 0xD0000000 +#define CS_1110 0xE0000000 +#define CS_1111 0xF0000000 + +#define BS_0000 0x00000000 +#define BS_0001 0x01000000 +#define BS_0010 0x02000000 +#define BS_0011 0x03000000 +#define BS_0100 0x04000000 +#define BS_0101 0x05000000 +#define BS_0110 0x06000000 +#define BS_0111 0x07000000 +#define BS_1000 0x08000000 +#define BS_1001 0x09000000 +#define BS_1010 0x0A000000 +#define BS_1011 0x0B000000 +#define BS_1100 0x0C000000 +#define BS_1101 0x0D000000 +#define BS_1110 0x0E000000 +#define BS_1111 0x0F000000 + +#define A10_AAAA 0x00000000 +#define A10_AAA0 0x00200000 +#define A10_AAA1 0x00300000 +#define A10_000A 0x00800000 +#define A10_0000 0x00A00000 +#define A10_0001 0x00B00000 +#define A10_111A 0x00C00000 +#define A10_1110 0x00E00000 +#define A10_1111 0x00F00000 + +#define RAS_0000 0x00000000 +#define RAS_0001 0x00040000 +#define RAS_1110 0x00080000 +#define RAS_1111 0x000C0000 + +#define CAS_0000 0x00000000 +#define CAS_0001 0x00010000 +#define CAS_1110 0x00020000 +#define CAS_1111 0x00030000 + +#define WE_0000 0x00000000 +#define WE_0001 0x00004000 +#define WE_1110 0x00008000 +#define WE_1111 0x0000C000 + +#define GPL4_0000 0x00000000 +#define GPL4_0001 0x00001000 +#define GPL4_1110 0x00002000 +#define GPL4_1111 0x00003000 + +#define GPL5_0000 0x00000000 +#define GPL5_0001 0x00000400 +#define GPL5_1110 0x00000800 +#define GPL5_1111 0x00000C00 +#define LOOP 0x00000080 + +#define EXEN 0x00000040 + +#define AMX_COL 0x00000000 +#define AMX_ROW 0x00000020 +#define AMX_MAR 0x00000030 + +#define NA 0x00000008 + +#define UTA 0x00000004 + +#define TODT 0x00000002 + +#define LAST 0x00000001 + +const uint sdram_table[0x40] = { + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* UPT */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP, + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP, + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, + + /* REG */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR, + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Test ETX ID string (ETX_xxx...) + * + * Return 1 always. + */ + +int checkboard(void) +{ +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 + printf ("NETVIA v1\n"); +#else + printf ("NETVIA v2+\n"); +#endif + return (0); +} + +/* ------------------------------------------------------------------------- */ + +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ +#define MAR_SDRAM_INIT 0x000000C8LU + +#define MCR_OP(x) ((unsigned long)((x) & 3) << (31-1)) +#define MCR_OP_MASK MCR_OP(3) + +#define MCR_UM(x) ((unsigned long)((x) & 1) << (31 - 8)) +#define MCR_UM_MASK MCR_UM(1) +#define MCR_UM_UPMA MCR_UM(0) +#define MCR_UM_UPMB MCR_UM(1) + +#define MCR_MB(x) ((unsigned long)((x) & 7) << (31 - 18)) +#define MCR_MB_MASK MCR_MB(7) +#define MCR_MB_CS(x) MCR_MB(x) + +#define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23)) +#define MCR_MCLF_MASK MCR_MCLF(15) + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + + upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mamr = CFG_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initialisation sequence */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C); /* precharge all */ + udelay(1); + memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0) */ + udelay(1); + memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E); /* exception program (write mar) */ + udelay(1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay(1000); + + memctl->memc_mamr = CFG_MAMR_9COL; + + size = SDRAM_MAX_SIZE; + + udelay(10000); + + return (size); +} + +/* ------------------------------------------------------------------------- */ + +int misc_init_r(void) +{ +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + last_er_val = 0xffffffff; +#endif + return(0); +} + +/* ------------------------------------------------------------------------- */ + +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + +/* bits that can have a special purpose or can be configured as inputs/outputs */ +#define PA_GP_INMASK 0 +#define PA_GP_OUTMASK (_BW(5) | _BWR(14, 15)) +#define PA_SP_MASK (_BW(4) | _BWR(6, 13)) +#define PA_ODR_VAL 0 +#define PA_GP_OUTVAL _BW(5) +#define PA_SP_DIRVAL 0 + +#define PB_GP_INMASK _B(28) +#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) +#define PB_SP_MASK _BR(22, 25) +#define PB_ODR_VAL 0 +#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) +#define PB_SP_DIRVAL 0 + +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 + +#define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13)) +#define PC_GP_OUTMASK _BW(12) +#define PC_SP_MASK (_BW(4) | _BW(8)) +#define PC_SOVAL 0 +#define PC_INTVAL 0 +#define PC_GP_OUTVAL 0 +#define PC_SP_DIRVAL 0 + +#define PD_GP_INMASK 0 +#define PD_GP_OUTMASK _BWR(3, 15) +#define PD_SP_MASK 0 +#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15)) +#define PD_SP_DIRVAL 0 + +#elif CONFIG_NETVIA_VERSION >= 2 + +#define PC_GP_INMASK (_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15)) +#define PC_GP_OUTMASK (_BW(6) | _BW(12)) +#define PC_SP_MASK (_BW(4) | _BW(8)) +#define PC_SOVAL 0 +#define PC_INTVAL _BW(7) +#define PC_GP_OUTVAL (_BW(6) | _BW(12)) +#define PC_SP_DIRVAL 0 + +#define PD_GP_INMASK 0 +#define PD_GP_OUTMASK _BWR(3, 15) +#define PD_SP_MASK 0 +#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(9) | _BW(11)) +#define PD_SP_DIRVAL 0 + +#else +#error Unknown NETVIA board version. +#endif + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* DSP0 chip select */ + memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); + memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); + + /* DSP1 chip select */ + memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); + memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); + + /* FPGA chip select */ + memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK); + memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + /* NAND chip select */ + memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); + memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); + + /* kill this chip select */ + memctl->memc_br2 &= ~BR_V; /* invalid */ + + /* external reg chip select */ + memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); + memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); +#endif + + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + ioport->iop_pddat = PD_GP_OUTVAL; + ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; + ioport->iop_pdpar = PD_SP_MASK; + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + /* external register init */ + *(volatile uint *)ER_BASE = 0xFFFFFFFF; +#endif + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include + +extern ulong nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + unsigned long totlen = nand_probe(CFG_NAND_BASE); + + printf ("%4lu MB\n", totlen >> 20); +} +#endif diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds new file mode 100644 index 0000000..dc69db6 --- /dev/null +++ b/board/netvia/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug new file mode 100644 index 0000000..96569bf --- /dev/null +++ b/board/netvia/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile new file mode 100644 index 0000000..fb4333c --- /dev/null +++ b/board/ns9750dev/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := ns9750dev.o flash.o led.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ns9750dev/config.mk b/board/ns9750dev/config.mk new file mode 100644 index 0000000..6a22cee --- /dev/null +++ b/board/ns9750dev/config.mk @@ -0,0 +1,16 @@ +####################################################################### +# +# Copyright (C) 2004 by FS Forth-Systeme GmbH. +# Markus Pietrek +# +# @TODO +# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000 +# optionally with a ramdisk at 0080'0000 +# +# we load ourself to 0078'0000 +# +# download area is 0060'0000 +# + + +TEXT_BASE = 0x00780000 diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c new file mode 100644 index 0000000..e7d6515 --- /dev/null +++ b/board/ns9750dev/flash.c @@ -0,0 +1,477 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, 32 * 1024}, /* 4 * 32kBytes sectors */ + {255, 128 * 1024}, /* 255 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + OrgDef *pOrgDef; + + pOrgDef = OrgIntel_28F256L18T; + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 255) { + info->start[i] = base + (i * 0x8000); + info->protect[i] = 0; + } else { + info->start[i] = base + + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; + info->size = 0x02000000; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + flash_unprotect_sectors (addr); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/ns9750dev/led.c b/board/ns9750dev/led.c new file mode 100644 index 0000000..b85c869 --- /dev/null +++ b/board/ns9750dev/led.c @@ -0,0 +1,46 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Defines helper functions for toggeling LEDs + * @Usage: + * @References: [1] + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifdef CONFIG_STATUS_LED + +#include + +static inline void __led_init( led_id_t mask, int state ) +{ + XXXX; +} + +static inline void __led_toggle( led_id_t mask ) +{ +} + +static inline void __led_set( led_id_t mask, int state ) +{ +} + +#endif /* CONFIG_STATUS_LED */ diff --git a/board/ns9750dev/lowlevel_init.S b/board/ns9750dev/lowlevel_init.S new file mode 100644 index 0000000..3a09786 --- /dev/null +++ b/board/ns9750dev/lowlevel_init.S @@ -0,0 +1,298 @@ +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * Modified for the NS9750 DevBoard by + * (C) Copyright 2004 by FS Forth-Systeme GmbH. + * Markus Pietrek + * @References: [1] NS9750 Hardware Reference/December 2003 + * [2] ns9750_a.cmd from MAJIC configuration + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_NS9750DEV) +# ifndef CONFIG_SKIP_LOWLEVEL_INIT +# include <./ns9750_sys.h> +# include <./ns9750_mem.h> +# endif +#endif + +/*********************************************************************** + * @Function: write_register_block + * @Return: nothing + * @Descr: Copies the register block of register_offset:register value to + * the registers at base r0. The block is assumed to start in RAM at r1 + * and end at r2. The linked RAM base address of U-Boot is assumed to be + * in r5 while the ROM base address we are running from is r6 + * Uses r3 and r4 as tempory registers + ***********************************************************************/ + +.macro write_register_block + @@ map the addresses to high memory + sub r1, r1, r5 + add r1, r1, r6 + sub r2, r2, r5 + add r2, r2, r6 + + @@ copy all +1: + @@ Write register/value pair starting at [r1] to register base r0 + ldr r3, [r1], #4 + ldr r4, [r1], #4 + str r4, [r0,r3] + cmp r1, r2 + blt 1b +.endm + +_TEXT_BASE: + .word TEXT_BASE @ sdram load addr from config.mk +_PHYS_FLASH: + .word PHYS_FLASH_1 @ real flash address (without mirroring) +_CAS_LATENCY: + .word 0x00022000 @ for CAS2 latency + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +.globl lowlevel_init +lowlevel_init: + + /* U-Boot may be linked to RAM at 0x780000. But this code will run in + flash from 0x0. But in order to enable RAM we have to disable the + mirror bit, therefore we have to jump to our real flash address + beginning at PHYS_FLASH_1 (CS4 Base). Therefore, + _run_at_real_flash_address may be 0x500003b0 while be linked to + 0x7803b0. So we must modify our linked addresses */ + + @@ branch to high memory address, away from 0x0 + ldr r5, _TEXT_BASE + ldr r6, _PHYS_FLASH + ldr r0, =_run_at_real_flash_address + sub r0, r0, r5 + add r0, r0, r6 + mov pc, r0 + nop @ for pipelining + +_run_at_real_flash_address: + @@ now we are running > PHYS_FLASH_1, safe to enable memory controller + + @@ Write Memory Configuration Registers + + ldr r0, _NS9750_MEM_MODULE_BASE + ldr r1, =_MEM_CONFIG_START + ldr r2, =_MEM_CONFIG_END + + write_register_block + + @@ Give SDRAM some time to settle + @@ @TODO. According to [2] it should be 2 AHB cycles. Check + + ldr r1, =0x50 +_sdram_settle: + subs r1, r1, #1 + bne _sdram_settle + +_enable_mappings: + @@ Enable SDRAM Mode + + ldr r1, =_MEM_MODE_START + ldr r2, =_MEM_MODE_END + + write_register_block + + ldr r3, _CAS_LATENCY @ perform one read from SDRAM + ldr r3, [r3] + + @@ Enable SDRAM and memory mappings + + ldr r1, =_MEM_ENABLE_START + ldr r2, =_MEM_ENABLE_END + + write_register_block + + @@ Activate AHB monitor + + ldr r0, =NS9750_SYS_MODULE_BASE + ldr r1, =_AHB_MONITOR_START + ldr r2, =_AHB_MONITOR_END + + write_register_block +_relocate_lr: + /* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to + PHYS_FLASH. */ + mov r1, ip + add r1, r1, r6 + mov ip, r1 + + mov r1, lr + add r1, r1, r6 + mov lr, r1 + + @@ back to arch calling code + mov pc, lr + + .ltorg + +_NS9750_MEM_MODULE_BASE: + .word NS9750_MEM_MODULE_BASE + +_MEM_CONFIG_START: + /* Table of 2 32bit entries. First word is register address offset + relative to NS9750_MEM_MODULE_BASE, second one is value. They are + written in order of appearance */ + + @@ Register values taken from [2] + .word NS9750_MEM_CTRL + .word NS9750_MEM_CTRL_E + + .word NS9750_MEM_DYN_REFRESH + .word (0x6 & NS9750_MEM_DYN_REFRESH_MA) + + .word NS9750_MEM_DYN_READ_CFG + .word (0x1 & NS9750_MEM_DYN_READ_CFG_MA) + + .word NS9750_MEM_DYN_TRP + .word (0x1 & NS9750_MEM_DYN_TRP_MA) + + .word NS9750_MEM_DYN_TRAS + .word (0x4 & NS9750_MEM_DYN_TRAS_MA) + + .word NS9750_MEM_DYN_TAPR + .word (0x1 & NS9750_MEM_DYN_TRAS_MA) + + .word NS9750_MEM_DYN_TDAL + .word (0x5 & NS9750_MEM_DYN_TDAL_MA) + + .word NS9750_MEM_DYN_TWR + .word (0x1 & NS9750_MEM_DYN_TWR_MA) + + .word NS9750_MEM_DYN_TRC + .word (0x6 & NS9750_MEM_DYN_TRC_MA) + + .word NS9750_MEM_DYN_TRFC + .word (0x6 & NS9750_MEM_DYN_TRFC_MA) + + .word NS9750_MEM_DYN_TRRD + .word (0x1 & NS9750_MEM_DYN_TRRD_MA) + + .word NS9750_MEM_DYN_TMRD + .word (0x1 & NS9750_MEM_DYN_TMRD_MA) + + @@ CS 4 + .word NS9750_MEM_DYN_CFG(0) + .word (NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + .word NS9750_MEM_DYN_RAS_CAS(0) + .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ + (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) + + @@ CS 5 + .word NS9750_MEM_DYN_CFG(1) + .word (NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + .word NS9750_MEM_DYN_RAS_CAS(1) + .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ + (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) + + @@ CS 6 + .word NS9750_MEM_DYN_CFG(2) + .word (NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + .word NS9750_MEM_DYN_RAS_CAS(2) + .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ + (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) + + @@ CS 7 + .word NS9750_MEM_DYN_CFG(3) + .word (NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + .word NS9750_MEM_DYN_RAS_CAS(3) + .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ + (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) + + .word NS9750_MEM_DYN_CTRL + .word (NS9750_MEM_DYN_CTRL_I_PALL | \ + NS9750_MEM_DYN_CTRL_SR | \ + NS9750_MEM_DYN_CTRL_CE ) + + .word NS9750_MEM_DYN_REFRESH + .word (0x1 & NS9750_MEM_DYN_REFRESH_MA) + @@ No further register settings after refresh +_MEM_CONFIG_END: + +_MEM_MODE_START: + .word NS9750_MEM_DYN_REFRESH + .word (0x30 & NS9750_MEM_DYN_REFRESH_MA) + + .word NS9750_MEM_DYN_CTRL + .word (NS9750_MEM_DYN_CTRL_I_MODE | \ + NS9750_MEM_DYN_CTRL_SR | \ + NS9750_MEM_DYN_CTRL_CE ) +_MEM_MODE_END: + +_MEM_ENABLE_START: + .word NS9750_MEM_DYN_CTRL + .word (NS9750_MEM_DYN_CTRL_I_NORMAL | \ + NS9750_MEM_DYN_CTRL_SR | \ + NS9750_MEM_DYN_CTRL_CE ) + + @@ CS 4 + .word NS9750_MEM_DYN_CFG(0) + .word (NS9750_MEM_DYN_CFG_BDMC | \ + NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + @@ CS 5 + .word NS9750_MEM_DYN_CFG(1) + .word (NS9750_MEM_DYN_CFG_BDMC | \ + NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + @@ CS 6 + .word NS9750_MEM_DYN_CFG(2) + .word (NS9750_MEM_DYN_CFG_BDMC | \ + NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) + + @@ CS 7 + .word NS9750_MEM_DYN_CFG(3) + .word (NS9750_MEM_DYN_CFG_BDMC | \ + NS9750_MEM_DYN_CFG_AM | \ + (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) +_MEM_ENABLE_END: + +_AHB_MONITOR_START: + .word NS9750_SYS_AHB_TIMEOUT + .word 0x01000100 @ @TODO not calculated yet + + .word NS9750_SYS_AHB_MON + .word (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \ + NS9750_SYS_AHB_MON_BATC_GEN_IRQ) +_AHB_MONITOR_END: + +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c new file mode 100644 index 0000000..ea00d5a --- /dev/null +++ b/board/ns9750dev/ns9750dev.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * Markus Pietrek + * derived from omap1610innovator.c + * @References: [1] NS9750 Hardware Reference/December 2003 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_NS9750DEV) +# include <./configs/ns9750dev.h> +# include <./ns9750_bbus.h> +#endif + +void flash__init( void ); +void ether__init( void ); + +static inline void delay( unsigned long loops ) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + + +/*********************************************************************** + * @Function: board_init + * @Return: 0 + * @Descr: Enables BBUS modules and other devices + ***********************************************************************/ + +int board_init( void ) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Active BBUS modules */ + *get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0; + +#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new + /* arch number of OMAP 1510-Board */ + /* to be changed for OMAP 1610 Board */ + gd->bd->bi_arch_number = 234; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + +/* this speeds up your boot a quite a bit. However to make it + * work, you need make sure your kernel startup flush bug is fixed. + * ... rkw ... + */ + icache_enable(); + + flash__init(); + ether__init(); + return 0; +} + + +int misc_init_r (void) +{ + /* currently empty */ + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ +} +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif + return 0; +} diff --git a/board/ns9750dev/u-boot.lds b/board/ns9750dev/u-boot.lds new file mode 100644 index 0000000..8ebb651 --- /dev/null +++ b/board/ns9750dev/u-boot.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = . ; + +} diff --git a/board/nx823/Makefile b/board/nx823/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/nx823/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/nx823/config.mk b/board/nx823/config.mk new file mode 100644 index 0000000..3b3ea1e --- /dev/null +++ b/board/nx823/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Nexus boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/nx823/flash.c b/board/nx823/flash.c new file mode 100644 index 0000000..581925e --- /dev/null +++ b/board/nx823/flash.c @@ -0,0 +1,464 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern u_long *my_sernum; /* from nx823.c */ + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE+monitor_flash_len-1, + &flash_info[0]); + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000); + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: + printf ("28F320J3A\n"); break; + case FLASH_28F640J3A: + printf ("28F640J3A\n"); break; + case FLASH_28F128J3A: + printf ("28F128J3A\n"); break; + default: printf ("Unknown Chip Type\n"); break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW)0x00AA00AA; + addr[0x2AAA] = (FPW)0x00550055; + addr[0x5555] = (FPW)0x00900090; + + value = addr[0]; + + switch (value) { + case (FPW)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW)0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case (FPW)INTEL_ID_28F320J3A: + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (FPW)INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (FPW)INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW)0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *)(info->start[sect]); + FPW status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW)0x00B000B0; /* suspend erase */ + *addr = (FPW)0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = (FPW)0x00FF00FF; /* reset to read mode */ + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* save sernum if needed */ + if (addr >= CFG_FLASH_SN_SECTOR && addr < CFG_FLASH_SN_BASE) + { + u_long dest = CFG_FLASH_SN_BASE; + u_short *sn = (u_short *)my_sernum; + + printf("(saving sernum)"); + for (i=0; i<4; i++) + { + if ((rc = write_data(info, dest, sn[i])) != 0) { + return (rc); + } + dest += port_width; + } + } + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= port_width) { + data = 0; + for (i=0; i 0x800) + { + putc('.'); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i CFG_FLASH_WRITE_TOUT) { + *addr = (FPW)0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW)0x00FF00FF; /* restore read mode */ + + return (0); +} diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c new file mode 100644 index 0000000..65d45c1 --- /dev/null +++ b/board/nx823/nx823.c @@ -0,0 +1,404 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { +#if (MPC8XX_SPEED <= 50000000L) + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07, + 0xFFFFFFFF, + + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FE7F434, 0xEFABE834, 0x1FA7D435, + + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00, + 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00, + 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF +#else + + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800, + 0x1FF7F447, + + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF7F434, 0xEFEBE834, 0x1FB7D435, + + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +#endif +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + */ + +int checkboard (void) +{ + printf ("Board: Nexus NX823"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0, size_b1, size8, size9; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Up to 2 Banks of 64Mbit x 2 devices + * Initial builds only have 1 + */ + memctl->memc_mptpr = CFG_MPTPR_1BK_4K; + memctl->memc_mar = 0x00000088; + + /* + * Map controller SDRAM bank 0 + */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + udelay (200); + + /* + * Map controller SDRAM bank 1 + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + + /* + * Perform SDRAM initializsation sequence + */ + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ + udelay (1); + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ + udelay (1); + memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + udelay (1000); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + memctl->memc_mar = 0x00000088; + + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, + SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size_b0 = size9; +/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); +/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + /* + * Check Bank 1 Memory Size + * use current column settings + * [9 column SDRAM may also be used in 8 column mode, + * but then only half the real size will be used.] + */ + size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); +/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping: map bigger bank first + */ + if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ + + memctl->memc_or2 = + ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b0 > 0) { + /* + * Position Bank 0 immediately above Bank 1 + */ + memctl->memc_or1 = + ((-size_b0) & 0xFFFF0000) | + CFG_OR_TIMING_SDRAM; + memctl->memc_br1 = + ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | + BR_V) + + size_b1; + } else { + unsigned long reg; + + /* + * No bank 0 + * + * invalidate bank + */ + memctl->memc_br1 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + + } else { /* SDRAM Bank 0 is bigger - map first */ + + memctl->memc_or1 = + ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br1 = + (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b1 > 0) { + /* + * Position Bank 1 immediately above Bank 0 + */ + memctl->memc_or2 = + ((-size_b1) & 0xFFFF0000) | + CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | + BR_V) + + size_b0; + } else { + unsigned long reg; + + /* + * No bank 1 + * + * invalidate bank + */ + memctl->memc_br2 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + } + + udelay (10000); + + return (size_b0 + size_b1); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size (base, maxsize)); +} + +u_long *my_sernum; + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char tmp[50]; + u_char *e = gd->bd->bi_enetaddr; + + /* save serial numbre from flash (uniquely programmed) */ + my_sernum = malloc (8); + memcpy (my_sernum, gd->bd->bi_sernum, 8); + + /* save env variables according to sernum */ + sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]); + setenv ("serial#", tmp); + + sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3], + e[4], e[5]); + setenv ("ethaddr", tmp); + return (0); +} + +void load_sernum_ethaddr (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + bd_t *bd = gd->bd; + + for (i = 0; i < 8; i++) { + bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i); + } + bd->bi_enetaddr[0] = 0x10; + bd->bi_enetaddr[1] = 0x20; + bd->bi_enetaddr[2] = 0x30; + bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2]; + bd->bi_enetaddr[4] = bd->bi_sernum[5]; + bd->bi_enetaddr[5] = bd->bi_sernum[6]; +} diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds new file mode 100644 index 0000000..7099fc4 --- /dev/null +++ b/board/nx823/u-boot.lds @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug new file mode 100644 index 0000000..3165d56 --- /dev/null +++ b/board/nx823/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/o2dnt/Makefile b/board/o2dnt/Makefile new file mode 100644 index 0000000..2eb4366 --- /dev/null +++ b/board/o2dnt/Makefile @@ -0,0 +1,47 @@ + +# +# (C) Copyright 2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/o2dnt/config.mk b/board/o2dnt/config.mk new file mode 100644 index 0000000..b873376 --- /dev/null +++ b/board/o2dnt/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# boot low for 16 MiB boards +TEXT_BASE = 0xFF000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/o2dnt/flash.c b/board/o2dnt/flash.c new file mode 100644 index 0000000..037d287 --- /dev/null +++ b/board/o2dnt/flash.c @@ -0,0 +1,587 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * flash_real_protect() routine based on boards/alaska/flash.c + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* Intel-compatible flash commands */ +#define INTEL_ERASE 0x20 +#define INTEL_PROGRAM 0x40 +#define INTEL_CLEAR 0x50 +#define INTEL_LOCKBIT 0x60 +#define INTEL_PROTECT 0x01 +#define INTEL_STATUS 0x70 +#define INTEL_READID 0x90 +#define INTEL_READID 0x90 +#define INTEL_SUSPEND 0xB0 +#define INTEL_CONFIRM 0xD0 +#define INTEL_RESET 0xFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x80 +#define INTEL_OK 0x80 + +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV +#define FLASH_ID_MASK 0xFF + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static flash_info_t *flash_get_info(ulong base); +static int write_data (flash_info_t *info, FPWV *dest, FPW data); /* O2D */ +static void flash_sync_real_protect (flash_info_t * info); +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + extern void flash_preinit(void); + extern void flash_afterinit(ulong); + + flash_preinit(); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + memset(&flash_info[i], 0, sizeof(flash_info_t)); + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Query flash chip */ + flash_info[0].size = + flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); + size += flash_info[0].size; + + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + + flash_afterinit(size); + return (size ? size : 1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW) INTEL_RESET; /* Intel Read Mode */ +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && + info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } + + return (i == CFG_MAX_FLASH_BANKS ? 0 : info); +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + char *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + fmt = "28F128J3 (128 Mbit, uniform sectors)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + int i; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW) INTEL_READID; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(100); + switch (addr[0] & 0xff) { + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Strataflash is configurable to 8/16bit Bus, + * but the Query-Structure is Word-orientated */ + if (info->flash_id != FLASH_UNKNOWN) { + switch ((FPW)addr[2]) { + case (FPW)INTEL_ID_28F128J3: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + for( i = 0; i < info->sector_count; i++ ) + info->start[i] = (ulong)addr + (i * 0x20000); + break; /* => Intel Strataflash 16MB */ + default: + printf("Flash_id != %xd\n", (FPW)addr[2]); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + } + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) + if (info->protect[sect]) + prot++; + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!", + prot); + + printf ("\n"); + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* wait at least 80us for Intel - let's wait 1 ms */ + udelay (1000); + + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) INTEL_SUSPEND;/* suspend erase */ + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) { /* every second */ + putc ('.'); + last = get_timer(0); + } + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + res = write_data(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, FPWV *dest, FPW data) +{ + FPWV *addr = dest; + ulong status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) INTEL_PROGRAM; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) INTEL_RESET; /* restore read mode */ + if (flag) + enable_interrupts(); + + return (0); +} + + +/*----------------------------------------------------------------------- + * Set/Clear sector's lock bit, returns: + * 0 - OK + * 1 - Error (timeout, voltage problems, etc.) + */ +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + ulong start; + int i; + int rc = 0; + FPWV *addr = (FPWV *) (info->start[sector]); + int flag = disable_interrupts (); + + *addr = INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + } else { /* Clear sector lock bit */ + *addr = INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = INTEL_CONFIRM; /* clear */ + } + + start = get_timer (0); + + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) { + printf ("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + + if (*addr != INTEL_OK) { + printf ("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint) addr, (uint) * addr); + rc = 1; + } + + if (!rc) + info->protect[sector] = prot; + + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + */ + if (!prot) { + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) { + start = get_timer (0); + addr = (FPWV *) (info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + while ((*addr & INTEL_FINISHED) != + INTEL_FINISHED) { + if (get_timer (start) > + CFG_FLASH_UNLOCK_TOUT) { + printf ("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + } + } + } + + if (flag) + enable_interrupts (); + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} + + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +static void flash_sync_real_protect (flash_info_t * info) +{ + int i; + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + udelay(1); + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer (0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* wait at least 35ns (W12) before reading */ + udelay(1); + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector] + 4; + ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} diff --git a/board/o2dnt/o2dnt.c b/board/o2dnt/o2dnt.c new file mode 100644 index 0000000..81a2700 --- /dev/null +++ b/board/o2dnt/o2dnt.c @@ -0,0 +1,182 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + else + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) + dramsize2 = 0; + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + + return dramsize + dramsize2; +} + +int checkboard (void) +{ + puts ("Board: O2DNT\n"); + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + +void flash_afterinit(ulong size) +{ + if (size == 0x800000) { /* adjust mapping */ + *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = + START_REG(CFG_BOOTCS_START | size); + + *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = + STOP_REG(CFG_BOOTCS_START | size, size); + } +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif diff --git a/board/o2dnt/u-boot.lds b/board/o2dnt/u-boot.lds new file mode 100644 index 0000000..88dc118 --- /dev/null +++ b/board/o2dnt/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/omap1510inn/Makefile b/board/omap1510inn/Makefile new file mode 100644 index 0000000..902b24e --- /dev/null +++ b/board/omap1510inn/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap1510innovator.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap1510inn/config.mk b/board/omap1510inn/config.mk new file mode 100644 index 0000000..7b24780 --- /dev/null +++ b/board/omap1510inn/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Kshitij Gupta +# +# TI Innovator board with OMAP1510 (ARM925T) cpu +# see http://www.ti.com/ for more information on Texas Insturments +# +# Innovator has 1 bank of 256 MB SDRAM +# Physical Address: +# 1000'0000 to 2000'0000 +# +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved) +# +# we load ourself to 1108'0000 +# +# + + +TEXT_BASE = 0x11080000 diff --git a/board/omap1510inn/lowlevel_init.S b/board/omap1510inn/lowlevel_init.S new file mode 100644 index 0000000..1c68e5b --- /dev/null +++ b/board/omap1510inn/lowlevel_init.S @@ -0,0 +1,396 @@ +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, + * + * -- Some bits of code used from rrload's head_OMAP1510.s -- + * Copyright (C) 2002 RidgeRun, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_OMAP1510) +#include <./configs/omap1510.h> +#endif + +#define OMAP1510_CLKS ((1< + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +static void flash__init (void); +static void ether__init (void); + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of OMAP 1510-Board */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + +/* kk - this speeds up your boot a quite a bit. However to make it + * work, you need make sure your kernel startup flush bug is fixed. + * ... rkw ... + */ + icache_enable (); + + flash__init (); + ether__init (); + return 0; +} + + +int misc_init_r (void) +{ + /* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ + /* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ + + /* setup gpio direction to match board (no floats!) */ + /**gdir = 0xCFF9; */ + /**mdir = 0x103F; */ + + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +static void flash__init (void) +{ +#define CS0_CHIP_SELECT_REG 0xfffecc10 +#define CS3_CHIP_SELECT_REG 0xfffecc1c +#define EMIFS_GlB_Config_REG 0xfffecc0c + + { + unsigned int regval; + + regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); + regval = regval | 0x0001; /* Turn off write protection for flash devices. */ + if (regval & 0x0002) { + regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ + /* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ + /* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ + /* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ + } + *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; + } +} + + +/****************************** + Routine: + Description: +******************************/ +static void ether__init (void) +{ +#define ETH_CONTROL_REG 0x0800000b + /* take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + */ + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; + udelay (3); +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/board/omap1510inn/u-boot.lds b/board/omap1510inn/u-boot.lds new file mode 100644 index 0000000..b6d1619 --- /dev/null +++ b/board/omap1510inn/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm925t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap1610inn/Makefile b/board/omap1610inn/Makefile new file mode 100644 index 0000000..4560102 --- /dev/null +++ b/board/omap1610inn/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap1610innovator.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap1610inn/config.mk b/board/omap1610inn/config.mk new file mode 100644 index 0000000..80976ef --- /dev/null +++ b/board/omap1610inn/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Kshitij Gupta +# +# TI Innovator board with OMAP1610 (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Innovator has 1 bank of 256 MB SDRAM +# Physical Address: +# 1000'0000 to 2000'0000 +# +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# (mem base + reserved) +# +# we load ourself to 1108'0000 +# +# + + +TEXT_BASE = 0x11080000 diff --git a/board/omap1610inn/flash.c b/board/omap1610inn/flash.c new file mode 100644 index 0000000..c8e4c9e --- /dev/null +++ b/board/omap1610inn/flash.c @@ -0,0 +1,493 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, 32 * 1024}, /* 4 * 32kBytes sectors */ + {255, 128 * 1024}, /* 255 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); +void flash_unlock(flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]); + flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]); + /* to reset the lock bit */ + flash_unlock(&flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_unlock(flash_info_t * info) +{ + int j; + for (j=2;jstart[j]); + flash_unprotect_sectors (addr); + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + } +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + OrgDef *pOrgDef; + + pOrgDef = OrgIntel_28F256L18T; + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 255) { + info->start[i] = base + (i * 0x8000); + info->protect[i] = 0; + } else { + info->start[i] = base + + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; + info->size = 0x02000000; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/omap1610inn/lowlevel_init.S b/board/omap1610inn/lowlevel_init.S new file mode 100644 index 0000000..eaf1742 --- /dev/null +++ b/board/omap1610inn/lowlevel_init.S @@ -0,0 +1,452 @@ +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_OMAP1610) +#include <./configs/omap1510.h> +#endif + + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl lowlevel_init +lowlevel_init: + + + /*------------------------------------------------------* + *mask all IRQs by setting all bits in the INTMR default* + *------------------------------------------------------*/ + mov r1, #0xffffffff + ldr r0, =REG_IHL1_MIR + str r1, [r0] + ldr r0, =REG_IHL2_MIR + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT1) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT1 + ldr r1, VAL_ARM_IDLECT1 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT2) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT2 + ldr r1, VAL_ARM_IDLECT2 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT3) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT3 + ldr r1, VAL_ARM_IDLECT3 + str r1, [r0] + +#ifdef CONFIG_CS_AUTOBOOT /* do the setup depending on boot mode */ + ldr r0, CONF_STATUS + ldr r1, [r0] + tst r1, #0x02 + beq disable_wd /* booting from RAM, skip setup */ +#endif + + mov r1, #0x01 /* PER_EN bit */ + ldr r0, REG_ARM_RSTCT2 + strh r1, [r0] /* CLKM; Peripheral reset. */ + + /* Set CLKM to Sync-Scalable */ + /* I supposedly need to enable the dsp clock before switching */ + mov r1, #0x0000 + ldr r0, REG_ARM_SYSST + strh r1, [r0] + mov r0, #0x400 +1: + subs r0, r0, #0x1 /* wait for any bubbles to finish */ + bne 1b + ldr r1, VAL_ARM_CKCTL + ldr r0, REG_ARM_CKCTL + strh r1, [r0] + + /* a few nops to let settle */ + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* setup DPLL 1 */ + /* Ramp up the clock to 96Mhz */ + ldr r1, VAL_DPLL1_CTL + ldr r0, REG_DPLL1_CTL + strh r1, [r0] + ands r1, r1, #0x10 /* Check if PLL is enabled. */ + beq lock_end /* Do not look for lock if BYPASS selected */ +2: + ldrh r1, [r0] + ands r1, r1, #0x01 /* Check the LOCK bit.*/ + beq 2b /* loop until bit goes hi. */ +lock_end: + + + /*------------------------------------------------------* + * Turn off the watchdog during init... * + *------------------------------------------------------*/ +disable_wd: + ldr r0, REG_WATCHDOG + ldr r1, WATCHDOG_VAL1 + str r1, [r0] + ldr r1, WATCHDOG_VAL2 + str r1, [r0] + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL1 + str r1, [r0] + ldr r0, REG_WWPSDOG + +watch1Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch1Wait + + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL2 + str r1, [r0] + ldr r0, REG_WWPSDOG +watch2Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch2Wait + + + /* Set memory timings corresponding to the new clock speed */ + + /* Check execution location to determine current execution location + * and branch to appropriate initialization code. + */ + /* Load physical SDRAM base. */ + mov r0, #0x10000000 + /* Get current execution location. */ + mov r1, pc + /* Compare. */ + cmp r1, r0 + /* Skip over EMIF-fast initialization if running from SDRAM. */ + bge skip_sdram + + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 /* value should be checked */ +3: + subs r3, r3, #0x1 /* Decrement count */ + bne 3b + + + /* + * Set SDRAM control values. Disable refresh before MRS command. + */ + + /* mobile ddr operation */ + ldr r0, REG_SDRAM_OPERATION + mov r2, #07 + str r2, [r0] + + /* config register */ + ldr r0, REG_SDRAM_CONFIG + ldr r1, SDRAM_CONFIG_VAL + str r1, [r0] + + /* manual command register */ + ldr r0, REG_SDRAM_MANUAL_CMD + /* issue set cke high */ + mov r1, #CMD_SDRAM_CKE_SET_HIGH + str r1, [r0] + /* issue nop */ + mov r1, #CMD_SDRAM_NOP + str r1, [r0] + + mov r2, #0x0100 +waitMDDR1: + subs r2, r2, #1 + bne waitMDDR1 /* delay loop */ + + /* issue precharge */ + mov r1, #CMD_SDRAM_PRECHARGE + str r1, [r0] + + /* issue autorefresh x 2 */ + mov r1, #CMD_SDRAM_AUTOREFRESH + str r1, [r0] + str r1, [r0] + + /* mrs register ddr mobile */ + ldr r0, REG_SDRAM_MRS + mov r1, #0x33 + str r1, [r0] + + /* emrs1 low-power register */ + ldr r0, REG_SDRAM_EMRS1 + /* self refresh on all banks */ + mov r1, #0 + str r1, [r0] + + ldr r0, REG_DLL_URD_CONTROL + ldr r1, DLL_URD_CONTROL_VAL + str r1, [r0] + + ldr r0, REG_DLL_LRD_CONTROL + ldr r1, DLL_LRD_CONTROL_VAL + str r1, [r0] + + ldr r0, REG_DLL_WRT_CONTROL + ldr r1, DLL_WRT_CONTROL_VAL + str r1, [r0] + + /* delay loop */ + mov r2, #0x0100 +waitMDDR2: + subs r2, r2, #1 + bne waitMDDR2 + + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 +4: + subs r3, r3, #1 /* Decrement count. */ + bne 4b + b common_tc + +skip_sdram: + + ldr r0, REG_SDRAM_CONFIG + ldr r1, SDRAM_CONFIG_VAL + str r1, [r0] + +common_tc: + /* slow interface */ + ldr r1, VAL_TC_EMIFS_CS0_CONFIG + ldr r0, REG_TC_EMIFS_CS0_CONFIG + str r1, [r0] /* Chip Select 0 */ + + ldr r1, VAL_TC_EMIFS_CS1_CONFIG + ldr r0, REG_TC_EMIFS_CS1_CONFIG + str r1, [r0] /* Chip Select 1 */ + ldr r1, VAL_TC_EMIFS_CS3_CONFIG + ldr r0, REG_TC_EMIFS_CS3_CONFIG + str r1, [r0] /* Chip Select 3 */ + +#ifdef CONFIG_H2_OMAP1610 + /* inserting additional 2 clock cycle hold time for LAN */ + ldr r0, REG_TC_EMIFS_CS1_ADVANCED + ldr r1, VAL_TC_EMIFS_CS1_ADVANCED + str r1, [r0] +#endif + /* Start MPU Timer 1 */ + ldr r0, REG_MPU_LOAD_TIMER + ldr r1, VAL_MPU_LOAD_TIMER + str r1, [r0] + + ldr r0, REG_MPU_CNTL_TIMER + ldr r1, VAL_MPU_CNTL_TIMER + str r1, [r0] + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +#ifdef CONFIG_CS_AUTOBOOT +CONF_STATUS: + .word 0xfffe1130 /* 32 bits */ +#endif + +REG_TC_EMIFS_CONFIG: /* 32 bits */ + .word 0xfffecc0c +REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ + .word 0xfffecc10 +REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ + .word 0xfffecc14 +REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ + .word 0xfffecc18 +REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ + .word 0xfffecc1c + +#ifdef CONFIG_H2_OMAP1610 +REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ + .word 0xfffecc54 +#endif + +/* MPU clock/reset/power mode control registers */ +REG_ARM_CKCTL: /* 16 bits */ + .word 0xfffece00 + +REG_ARM_IDLECT3: /* 16 bits */ + .word 0xfffece24 +REG_ARM_IDLECT2: /* 16 bits */ + .word 0xfffece08 +REG_ARM_IDLECT1: /* 16 bits */ + .word 0xfffece04 + +REG_ARM_RSTCT2: /* 16 bits */ + .word 0xfffece14 +REG_ARM_SYSST: /* 16 bits */ + .word 0xfffece18 +/* DPLL control registers */ +REG_DPLL1_CTL: /* 16 bits */ + .word 0xfffecf00 + +/* Watch Dog register */ +/* secure watchdog stop */ +REG_WSPRDOG: + .word 0xfffeb048 +/* watchdog write pending */ +REG_WWPSDOG: + .word 0xfffeb034 + +WSPRDOG_VAL1: + .word 0x0000aaaa +WSPRDOG_VAL2: + .word 0x00005555 + +/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, + counter @8192 rows, 10 ns, 8 burst */ +REG_SDRAM_CONFIG: + .word 0xfffecc20 + +/* Operation register */ +REG_SDRAM_OPERATION: + .word 0xfffecc80 + +/* Manual command register */ +REG_SDRAM_MANUAL_CMD: + .word 0xfffecc84 + +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ +REG_SDRAM_MRS: + .word 0xfffecc70 + +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ +REG_SDRAM_EMRS1: + .word 0xfffecc78 + +/* WRT DLL register */ +REG_DLL_WRT_CONTROL: + .word 0xfffecc68 +DLL_WRT_CONTROL_VAL: + .word 0x03f00002 + +/* URD DLL register */ +REG_DLL_URD_CONTROL: + .word 0xfffeccc0 +DLL_URD_CONTROL_VAL: + .word 0x00800002 + +/* LRD DLL register */ +REG_DLL_LRD_CONTROL: + .word 0xfffecccc + +REG_WATCHDOG: + .word 0xfffec808 + +REG_MPU_LOAD_TIMER: + .word 0xfffec600 +REG_MPU_CNTL_TIMER: + .word 0xfffec500 + +/* 96 MHz Samsung Mobile DDR */ +SDRAM_CONFIG_VAL: + .word 0x001200f4 + +DLL_LRD_CONTROL_VAL: + .word 0x00800002 + +VAL_ARM_CKCTL: + .word 0x3000 +VAL_DPLL1_CTL: + .word 0x2830 + +#ifdef CONFIG_INNOVATOROMAP1610 +VAL_TC_EMIFS_CS0_CONFIG: + .word 0x002130b0 +VAL_TC_EMIFS_CS1_CONFIG: + .word 0x00001131 +VAL_TC_EMIFS_CS2_CONFIG: + .word 0x000055f0 +VAL_TC_EMIFS_CS3_CONFIG: + .word 0x88011131 +#endif + +#ifdef CONFIG_H2_OMAP1610 +VAL_TC_EMIFS_CS0_CONFIG: + .word 0x00203331 +VAL_TC_EMIFS_CS1_CONFIG: + .word 0x8180fff3 +VAL_TC_EMIFS_CS2_CONFIG: + .word 0xf800f22a +VAL_TC_EMIFS_CS3_CONFIG: + .word 0x88011131 +VAL_TC_EMIFS_CS1_ADVANCED: + .word 0x00000022 +#endif + +VAL_TC_EMIFF_SDRAM_CONFIG: + .word 0x010290fc +VAL_TC_EMIFF_MRS: + .word 0x00000027 + +VAL_ARM_IDLECT1: + .word 0x00000400 + +VAL_ARM_IDLECT2: + .word 0x00000886 +VAL_ARM_IDLECT3: + .word 0x00000015 + +WATCHDOG_VAL1: + .word 0x000000f5 +WATCHDOG_VAL2: + .word 0x000000a0 + +VAL_MPU_LOAD_TIMER: + .word 0xffffffff +VAL_MPU_CNTL_TIMER: + .word 0xffffffa1 + +/* command values */ +.equ CMD_SDRAM_NOP, 0x00000000 +.equ CMD_SDRAM_PRECHARGE, 0x00000001 +.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 +.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/omap1610inn/omap1610innovator.c b/board/omap1610inn/omap1610innovator.c new file mode 100644 index 0000000..7842518 --- /dev/null +++ b/board/omap1610inn/omap1610innovator.c @@ -0,0 +1,306 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_OMAP1610) +#include <./configs/omap1510.h> +#endif + +#ifdef CONFIG_CS_AUTOBOOT +unsigned long omap_flash_base; +#endif + +void flash__init (void); +void ether__init (void); +void set_muxconf_regs (void); +void peripheral_power_enable (void); + +#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (machine_is_omap_h2()) + gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2; + else if (machine_is_omap_innovator()) + gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; + else + gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + /* Configure MUX settings */ + set_muxconf_regs (); + peripheral_power_enable (); + +/* this speeds up your boot a quite a bit. However to make it + * work, you need make sure your kernel startup flush bug is fixed. + * ... rkw ... + */ + icache_enable (); + + flash__init (); + ether__init (); + return 0; +} + + +int misc_init_r (void) +{ + /* currently empty */ + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ +#define EMIFS_GlB_Config_REG 0xfffecc0c + unsigned int regval; + +#ifdef CONFIG_CS_AUTOBOOT + /* Check swapping of CS0 and CS3, set flash base accordingly */ + omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ? + PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1; +#endif + regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); + /* Turn off write protection for flash devices. */ + regval = regval | 0x0001; + *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; +} +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ +#define ETH_CONTROL_REG 0x0400030b + +#ifdef CONFIG_H2_OMAP1610 + #define LAN_RESET_REGISTER 0x0400001c + + /* The debug board on which the lan chip resides may not be powered + * ON at the same time as the OMAP chip. So wait in a loop until the + * lan reset register (on the debug board) is available (powered on) + * and reset the lan chip. + */ + + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; + do { + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; + udelay (3); + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); + + do { + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; + udelay (3); + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); +#endif + + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; + udelay (3); +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +/****************************************************** + Routine: set_muxconf_regs + Description: Setting up the configuration Mux registers + specific to the hardware +*******************************************************/ +void set_muxconf_regs (void) +{ + volatile unsigned int *MuxConfReg; + /* set each registers to its reset value; */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); + /* setup for UART1 */ + *MuxConfReg &= ~(0x02000000); /* bit 25 */ + /* setup for UART2 */ + *MuxConfReg &= ~(0x01000000); /* bit 24 */ + /* Disable Uwire CS Hi-Z */ + *MuxConfReg |= 0x08000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); + /*setup mux for UART3 */ + *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ + *MuxConfReg &= ~0x0000003e; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); + /* Disable Uwire CS Hi-Z */ + *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); + /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ + /* hardware will actually use TX and RTS based on bit 25 in */ + /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ + *MuxConfReg |= 0x00201000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); + /* setup for UART2 */ + /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ + /* hardware will actually use TX and RTS based on bit 24 in */ + /* FUNC_MUX_CTRL_0. */ + *MuxConfReg |= 0x09000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); + *MuxConfReg = 0x00000000; + /* mux setup for SD/MMC driver */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); + *MuxConfReg &= 0xFFFE0FFF; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); + /* bit 13 for MMC2 XOR_CLK */ + *MuxConfReg &= ~(0x00002000); + /* bit 29 for UART 1 */ + *MuxConfReg &= ~(0x00002000); + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); + /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ + *MuxConfReg |= 0x000C0000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); + *MuxConfReg &= ~(0x00000070); + *MuxConfReg &= ~(0x00000008); + *MuxConfReg |= 0x00000003; + *MuxConfReg |= 0x00000180; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); + /* bit 17, software controls VBUS */ + *MuxConfReg &= ~(0x00020000); + /* Enable USB 48 and 12M clocks */ + *MuxConfReg |= 0x00000200; + *MuxConfReg &= ~(0x00000180); + /*2.75V for MMCSDIO1 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); + *MuxConfReg = 0x00001FE7; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); + *MuxConfReg = 0x00000000; + /* Turn on UART2 48 MHZ clock */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); + *MuxConfReg |= 0x40000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); + /* setup for USB VBus detection OMAP161x */ + *MuxConfReg |= 0x00040000; /* bit 18 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); + /* PullUps for SD/MMC driver */ + *MuxConfReg |= ~(0xFFFE0FFF); + MuxConfReg = + (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); + *MuxConfReg = COMP_MODE_ENABLE; +} + +/****************************************************** + Routine: peripheral_power_enable + Description: Enable the power for UART1 +*******************************************************/ +void peripheral_power_enable (void) +{ +#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) +#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) + + *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; +} diff --git a/board/omap1610inn/u-boot.lds b/board/omap1610inn/u-boot.lds new file mode 100644 index 0000000..710b2a2 --- /dev/null +++ b/board/omap1610inn/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile new file mode 100644 index 0000000..ed47868 --- /dev/null +++ b/board/omap2420h4/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap2420h4.o mem.o sys_info.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk new file mode 100644 index 0000000..3edcde0 --- /dev/null +++ b/board/omap2420h4/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2004 +# Texas Instruments, +# +# TI H4 board with OMAP2420 (ARM1136) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) ES2 will be configurable +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + +# Used with full SRAM boot. +# This is either with a GP system or a signed boot image. +# easiest, and safest way to go if you can. +#TEXT_BASE = 0x40270000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap2420h4/flash.c b/board/omap2420h4/flash.c new file mode 100644 index 0000000..d5e106a --- /dev/null +++ b/board/omap2420h4/flash.c @@ -0,0 +1,537 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define PHYS_FLASH_SECT_SIZE SZ_128K +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +# define FLASH_PORT_WIDTH ushort +# define FLASH_PORT_WIDTHV vu_short +# define SWAP(x) __swab16(x) +#else +# define FLASH_PORT_WIDTH ulong +# define FLASH_PORT_WIDTHV vu_long +# define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, SZ_32K}, /* 4 * 32kBytes sectors */ + {255, SZ_128K}, /* 255 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); +void flash_unlock(flash_info_t * info, int bank); +int flash_probe(void); + +/*----------------------------------------------------------------------- + */ + +/* see if flash is ok */ +int flash_probe(void) +{ + return(flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[0])); +} + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + /* to reset the lock bit */ + flash_unlock(&flash_info[i],i); + break; + case 1: + flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + /* to reset the lock bit */ + flash_unlock(&flash_info[i],i); + break; + + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + +#ifdef CFG_ENV_IS_IN_FLASH + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_unlock(flash_info_t * info, int bank) +{ + int j; + if (!bank) + j=2; /* leave 0,1 locked for boot bank */ + else + j=0; /* get the whole bank for #2 */ + + for (;jstart[j]); + if (addr == NULL) { + printf("Warning Flash probe failed\n"); + break; + } + flash_unprotect_sectors (addr); + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + } +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + volatile int r; /* gcc 3.4.0-1 strangeness, need to follow up.*/ + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 254) { /* 255,256,257,258 */ + r=i; + info->start[i] = base + (((r-(int)255) * SZ_32K) + (255*PHYS_FLASH_SECT_SIZE)); + info->protect[i] = 0; + } else { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + /* mb(); this one makes ARM11 err go away, but I want it :) as a guide to problems */ + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0] & 0xFF; /* just looking for 89 (8989 is hw pat)*/ + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return(0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): /* 880D */ + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; /*0-258*/ + info->size = SZ_32M; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return(info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int prot, sect; + ulong type, start, last; + int rcode = 0; +#ifdef CONFIG_USE_IRQ + int iflag; +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + start = get_timer (0); + last = start; + +#ifdef CONFIG_USE_IRQ + /* Disable interrupts which might cause a timeout here */ + iflag = disable_interrupts (); +#endif + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } +#ifdef CONFIG_USE_IRQ + if (iflag) + enable_interrupts(); +#endif + + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return(rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return(rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return(0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return(write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; +#ifdef CONFIG_USE_IRQ + int iflag; +#endif + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return(2); + } + /* Disable interrupts which might cause a timeout here */ +#ifdef CONFIG_USE_IRQ + iflag = disable_interrupts (); +#endif + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return(1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + +#ifdef CONFIG_USE_IRQ + if (iflag) + enable_interrupts(); +#endif + + return(0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/omap2420h4/lowlevel_init.S b/board/omap2420h4/lowlevel_init.S new file mode 100644 index 0000000..9752fc4 --- /dev/null +++ b/board/omap2420h4/lowlevel_init.S @@ -0,0 +1,185 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = PRCM_CLKCFG_CTRL - addr of valid reg + * R1 = CM_CLKEN_PLL - addr dpll ctlr reg + * R2 = dpll value + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + ******************************************************************************/ +.global go_to_speed + go_to_speed: + sub sp, sp, #0x4 /* get some stack space */ + str r4, [sp] /* save r4's value */ + + /* move into fast relock bypass */ + ldr r8, pll_ctl_add + mov r4, #0x2 + str r4, [r8] + ldr r4, pll_stat +block: + ldr r8, [r4] /* wait for bypass to take effect */ + and r8, r8, #0x3 + cmp r8, #0x1 + bne block + + /* set new dpll dividers _after_ in bypass */ + ldr r4, pll_div_add + ldr r8, pll_div_val + str r8, [r4] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r4, cfg3_0_addr + ldr r8, cfg3_0_val + str r8, [r4] + ldr r4, cfg4_0_addr + ldr r8, cfg4_0_val + str r8, [r4] + ldr r4, cfg1_0_addr + ldr r8, [r4] + orr r8, r8, #0x3 /* up gpmc divider */ + str r8, [r4] + + /* setup to 2x loop though code. The first loop pre-loads the + * icache, the 2nd commits the prcm config, and locks the dpll + */ + mov r4, #0x1000 /* spin spin spin */ + mov r8, #0x4 /* first pass condition & set registers */ + cmp r8, #0x4 +2: + ldrne r8, [r3] /* DPLL lock check */ + and r8, r8, #0x7 + cmp r8, #0x2 + beq 4f +3: + subeq r8, r8, #0x1 + streq r8, [r0] /* commit dividers (2nd time) */ + nop +lloop1: + sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop1 + mov r4, #0x40000 + cmp r8, #0x1 + nop + streq r2, [r1] /* lock dpll (2nd time) */ + nop +lloop2: + sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop2 + mov r4, #0x40000 + cmp r8, #0x1 + nop + ldreq r8, [r3] /* get lock condition for dpll */ + cmp r8, #0x4 /* first time though? */ + bne 2b + moveq r8, #0x2 /* set to dpll check condition. */ + beq 3b /* if condition not true branch */ +4: + ldr r4, [sp] + add sp, sp, #0x4 /* return stack space */ + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +cfg3_0_addr: + .word GPMC_CONFIG3_0 +cfg3_0_val: + .word H4_24XX_GPMC_CONFIG3_0 +cfg4_0_addr: + .word GPMC_CONFIG4_0 +cfg4_0_val: + .word H4_24XX_GPMC_CONFIG4_0 +cfg1_0_addr: + .word GPMC_CONFIG1_0 +pll_ctl_add: + .word CM_CLKEN_PLL +pll_stat: + .word CM_IDLEST_CKGEN +pll_div_add: + .word CM_CLKSEL1_PLL +pll_div_val: + .word DPLL_VAL /* DPLL setting (300MHz default) */ + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* map interrupt controller */ + ldr r0, VAL_INTH_SETUP + mcr p15, 0, r0, c15, c2, 4 + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +VAL_INTH_SETUP: + .word PERIFERAL_PORT_BASE +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c new file mode 100644 index 0000000..62eb6e3 --- /dev/null +++ b/board/omap2420h4/mem.c @@ -0,0 +1,375 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in 12MHz bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay (unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/********************************************************************************* + * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default). + * -- called from SRAM, or Flash (using temp SRAM stack). + *********************************************************************************/ +void prcm_init(void) +{ + u32 div; + void (*f_lock_pll) (u32, u32, u32, u32); + extern void *_end_vect, *_start; + + f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE); + + __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ + __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ + __raw_writel(0, CM_ICLKEN1_CORE); + __raw_writel(0, CM_ICLKEN2_CORE); + + __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */ + __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */ + __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */ + __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */ + + div = BUS_DIV; + __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */ + sdelay(1000); + + if(running_in_sram()){ + /* If running fully from SRAM this is OK. The Flash bus drops out for just a little. + * but then comes back. If running from Flash this sequence kills you, thus you need + * to run it using CONFIG_PARTIAL_SRAM. + */ + __raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */ + wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */ + sdelay(1000); + /* set clock selection and dpll dividers. */ + __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */ + __raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */ + sdelay(10000); + __raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */ + sdelay(10000); + wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */ + }else if(running_in_flash()){ + /* if running from flash, need to jump to small relocated code area in SRAM. + * This is the only safe spot to do configurations from. + */ + (*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN); + } + + __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */ + wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */ + sdelay(1000); +} + +/************************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow + * command line mem=xyz use all memory with out discontigious support + * compiled in. Could do it at the ATAG, but there really is two banks... + * Called as part of 2nd phase DDR init. + **************************************************************************/ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(SDRC_CS0_OSET); + size /= SZ_32M; /* find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + __raw_writel((a_add_high|a_add_low),SDRC_CS_CFG); + +} + +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in gussing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(void) +{ + u32 val1, val2; + u32 pattern = 0x12345678; + + __raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */ + __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */ + __raw_writel(0x0,OMAP2420_SDRC_CS0+4); /* remove pattern off the bus */ + val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */ + val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed*/ + return(0); + else + return(1); +} + + +/******************************************************** + * sdrc_init() - init the sdrc chip selects CS0 and CS1 + * - early init routines, called from flash or + * SRAM. + *******************************************************/ +void sdrc_init(void) +{ + #define EARLY_INIT 1 + do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */ +} + +/************************************************************************* + * do_sdrc_init(): initialize the SDRAM for use. + * -called from low level code with stack only. + * -code sets up SDRAM timing and muxing for 2422 or 2420. + * -optimal settings can be placed here, or redone after i2c + * inspection of board info + * + * This is a bit ugly, but should handle all memory moduels + * used with the H4. The first time though this code from s_init() + * we configure the first chip select. Later on we come back and + * will configure the 2nd chip select if it exists. + * + **************************************************************************/ +void do_sdrc_init(u32 offset, u32 early) +{ + u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype; + sdrc_data_t *sdata; /* do not change type */ + u32 a, b, r; + + static const sdrc_data_t sdrc_2422 = + { + H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0, + H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR, + 0, H4_2422_SDRC_DLLAB_CTRL + }; + static const sdrc_data_t sdrc_2420 = + { + H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR, + H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0, + H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR, + H4_2420_SDRC_DLLAB_CTRL + }; + + if (offset == SDRC_CS0_OSET) + cs0 = common = 1; /* int regs shared between both chip select */ + + cpu = get_cpu_type(); + rev = get_cpu_rev(); + + /* warning generated, though code generation is correct. this may bite later, + * but is ok for now. there is only so much C code you can do on stack only + * operation. + */ + if (cpu == CPU_2422){ + sdata = (sdrc_data_t *)&sdrc_2422; + pass_type = STACKED; + } else{ + sdata = (sdrc_data_t *)&sdrc_2420; + pass_type = IP_DDR; + } + + __asm__ __volatile__("": : :"memory"); /* limit compiler scope */ + + /* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx. + * If we are running in flash prior to relocation and we use data + * here which is not pc relative we need to get the address correct. + * We need to find the current flash mapping to dress up the initial + * pointer load. As long as this is const data we should be ok. + */ + if((early) && running_in_flash()){ + sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base()); + /* NOR internal boot offset is 0x4000 from xloader signature */ + if(running_from_internal_boot()) + sdata = (sdrc_data_t *)((u32)sdata + 0x4000); + } + + if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) { + if(mtype == DDR_COMBO){ + pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */ + pass_type = COMBO_DDR; /* CS1 config */ + __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER); + } + if(rev != CPU_2420_2422_ES1) /* for es2 and above smooth things out */ + make_cs1_contiguous(); + } + +next_mem_type: + if (common) { /* do a SDRC reset between types to clear regs*/ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */ + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */ + __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */ + __raw_writel(sdata->sdrc_sharing, SDRC_SHARING); +#ifdef POWER_SAVE + __raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG); + __raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING); + __raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER); +#endif + } + + if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */ + __raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset); + else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */ + __raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset); + } else if (pass_type == IP_SDR){ /* ip sdr-CS0 */ + __raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset); + } + + a = sdata->sdrc_actim_ctrla_0; + b = sdata->sdrc_actim_ctrlb_0; + r = sdata->sdrc_dllab_ctrl; + + /* work around ES1 DDR issues */ + if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){ + a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1; + b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1; + r = H4_242x_SDRC_RFR_CTRL_ES1; + } + + if (cs0) { + __raw_writel(a, SDRC_ACTIM_CTRLA_0); + __raw_writel(b, SDRC_ACTIM_CTRLB_0); + } else { + __raw_writel(a, SDRC_ACTIM_CTRLA_1); + __raw_writel(b, SDRC_ACTIM_CTRLB_1); + } + __raw_writel(r, SDRC_RFR_CTRL+offset); + + /* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0+offset); + sdelay(5000); /* susposed to be 100us per design spec for mddr/msdr */ + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset); + + /* + * CSx SDRC Mode Register + * Burst length = (4 - DDR) (2-SDR) + * Serial mode + * CAS latency = x + */ + if(pass_type == IP_SDR) + __raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset); + else + __raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset); + + /* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/ + if (rev == CPU_2420_2422_ES1){ + dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */ + __raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7) + ,SMS_CLASS_ARB0);/* enable bust complete for lcd */ + } + else + dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */ + + /* enable & load up DLL with good value for 75MHz, and set phase to 90 + * ES1 recommends 90 phase, ES2 recommends 72 phase. + */ + if (common && (pass_type != IP_SDR)) { + __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL); + } + sdelay(90000); + + if(mem_ok()) + return; /* STACKED, other configued type */ + ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */ + goto next_mem_type; +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + u32 mux=0, mtype, mwidth, rev, tval; + + rev = get_cpu_rev(); + if (rev == CPU_2420_2422_ES1) + tval = 1; + else + tval = 0; /* disable bit switched meaning */ + + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */ +#ifdef CFG_NAND_BOOT + __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ +#else + __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */ +#endif + + /* discover bus connection from sysboot */ + if (is_gpmc_muxed() == GPMC_MUXED) + mux = BIT9; + mtype = get_gpmc0_type(); + mwidth = get_gpmc0_width(); + + /* setup cs0 */ + __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ + sdelay(1000); + +#ifdef CFG_NAND_BOOT + __raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0); +#else + __raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0); +#endif + +#ifdef PRCM_CONFIG_III + __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); +#endif + __raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0); + __raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0); +#ifdef PRCM_CONFIG_III + __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); + __raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0); +#endif + __raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */ + sdelay(2000); + + /* setup cs1 */ + __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */ + sdelay(1000); + __raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1); + __raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1); + __raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1); + __raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1); + __raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1); + __raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1); + __raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */ + sdelay(2000); +} diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c new file mode 100644 index 0000000..6ae1a49 --- /dev/null +++ b/board/omap2420h4/omap2420h4.c @@ -0,0 +1,868 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +#endif + + void wait_for_command_complete(unsigned int wd_base); + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRM, finish GPMC */ + + gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */ + gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */ + + return 0; +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_sram(void) +{ + /* if GP device unlock device SRAM for general use */ + if (get_device_type() == GP_DEVICE) { + __raw_writel(0xFF, A_REQINFOPERM0); + __raw_writel(0xCFDE, A_READPERM0); + __raw_writel(0xCFDE, A_WRITEPERM0); + } +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with sram stack. + **********************************************************/ +void s_init(void) +{ + int in_sdram = running_in_sdram(); + + watchdog_init(); + set_muxconf_regs(); + delay(100); + try_unlock_sram(); + + if(!in_sdram) + prcm_init(); + + peripheral_enable(); + icache_enable(); + if (!in_sdram) + sdrc_init(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r (void) +{ + ether_init(); /* better done here so timers are init'ed */ + return(0); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 4 watch dogs. 1 secure, and 3 general purpose. + * The ROM takes care of the secure one. Of the 3 GP ones, + * 1 can reset us directly, the other 2 only generate MPU interrupts. + */ + __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); + +#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/ + __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR); + wait_for_command_complete(WD3_BASE); + __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR); + + __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR); + wait_for_command_complete(WD4_BASE); + __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR); +#endif +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base+WWPS); + } while (pending); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init (void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */ + + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay (100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay (100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay (1000); + + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; + udelay (1000); + + h4reset_err_out: + return; +#endif +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0=0,size1=0; + u32 mtype, btype, rev, cpu; + u8 chg_on = 0x5; /* enable charge of back up battery */ + u8 vmode_on = 0x8C; + #define NOT_EARLY 0 + + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */ + + btype = get_board_type(); + mtype = get_mem_type(); + rev = get_cpu_rev(); + cpu = get_cpu_type(); + + display_board_info(btype); + if (btype == BOARD_H4_MENELAUS){ + update_mux(btype,mtype); /* combo part on menelaus */ + i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */ + i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */ + } + + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */ + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */ + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + else /* ES2 and above can remap at 32MB granularity */ + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware + *********************************************************/ +void set_muxconf_regs (void) +{ + muxSetupSDRC(); + muxSetupGPMC(); + muxSetupUsb0(); + muxSetupUart3(); + muxSetupI2C1(); + muxSetupUART1(); + muxSetupLCD(); + muxSetupCamera(); + muxSetupMMCSD(); + muxSetupTouchScreen(); + muxSetupHDQ(); +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void peripheral_enable(void) +{ + unsigned int v, if_clks=0, func_clks=0; + + /* Enable GP2 timer.*/ + if_clks |= BIT4; + func_clks |= BIT4; + v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */ + __raw_writel(v, CM_CLKSEL2_CORE); + __raw_writel(0x1, CM_CLKSEL_WKUP); + +#ifdef CFG_NS16550 + /* Enable UART1 clock */ + func_clks |= BIT21; + if_clks |= BIT21; +#endif + v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ + __raw_writel(v,CM_ICLKEN1_CORE ); + v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN1_CORE); + delay(1000); + +#ifndef KERNEL_UPDATED + { +#define V1 0xffffffff +#define V2 0x00000007 + + __raw_writel(V1, CM_FCLKEN1_CORE); + __raw_writel(V2, CM_FCLKEN2_CORE); + __raw_writel(V1, CM_ICLKEN1_CORE); + __raw_writel(V1, CM_ICLKEN2_CORE); + } +#endif +} + +/**************************************** + * Routine: muxSetupUsb0 (ostboot) + * Description: Setup usb muxing + *****************************************/ +void muxSetupUsb0(void) +{ + volatile uint8 *MuxConfigReg; + volatile uint32 *otgCtrlReg; + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN; + *MuxConfigReg &= (uint8)(~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP; + *MuxConfigReg &= (uint8)(~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM; + *MuxConfigReg &= (uint8)(~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV; + *MuxConfigReg &= (uint8)(~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN; + *MuxConfigReg &= (uint8)(~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0; + *MuxConfigReg &= (uint8)(~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT; + *MuxConfigReg &= (uint8)(~0x1F); + + /* setup for USB VBus detection */ + otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL; + *otgCtrlReg |= 0x00040000; /* bit 18 */ +} + +/**************************************** + * Routine: muxSetupUart3 (ostboot) + * Description: Setup uart3 muxing + *****************************************/ +void muxSetupUart3(void) +{ + volatile uint8 *MuxConfigReg; + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX; + *MuxConfigReg &= (uint8)(~0x1F); + + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX; + *MuxConfigReg &= (uint8)(~0x1F); +} + +/**************************************** + * Routine: muxSetupI2C1 (ostboot) + * Description: Setup i2c muxing + *****************************************/ +void muxSetupI2C1(void) +{ + volatile unsigned char *MuxConfigReg; + + /* I2C1 Clock pin configuration, PIN = M19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* I2C1 Data pin configuration, PIN = L15 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* Pull-up required on data line */ + /* external pull-up already present. */ + /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */ +} + +/**************************************** + * Routine: muxSetupUART1 (ostboot) + * Description: Set up uart1 muxing + *****************************************/ +void muxSetupUART1(void) +{ + volatile unsigned char *MuxConfigReg; + + /* UART1_CTS pin configuration, PIN = D21 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* UART1_RTS pin configuration, PIN = H21 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* UART1_TX pin configuration, PIN = L20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* UART1_RX pin configuration, PIN = T21 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ +} + +/**************************************** + * Routine: muxSetupLCD (ostboot) + * Description: Setup lcd muxing + *****************************************/ +void muxSetupLCD(void) +{ + volatile unsigned char *MuxConfigReg; + + /* LCD_D0 pin configuration, PIN = Y7 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D1 pin configuration, PIN = P10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D2 pin configuration, PIN = V8 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D3 pin configuration, PIN = Y8 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D4 pin configuration, PIN = W8 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D5 pin configuration, PIN = R10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D6 pin configuration, PIN = Y9 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D7 pin configuration, PIN = V9 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D8 pin configuration, PIN = W9 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D9 pin configuration, PIN = P11 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D10 pin configuration, PIN = V10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D11 pin configuration, PIN = Y10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D12 pin configuration, PIN = W10 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D13 pin configuration, PIN = R11 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D14 pin configuration, PIN = V11 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D15 pin configuration, PIN = W11 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D16 pin configuration, PIN = P12 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_D17 pin configuration, PIN = R12 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_PCLK pin configuration, PIN = W6 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_VSYNC pin configuration, PIN = V7 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_HSYNC pin configuration, PIN = Y6 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* LCD_ACBIAS pin configuration, PIN = W7 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ +} + +/**************************************** + * Routine: muxSetupCamera (ostboot) + * Description: Setup camera muxing + *****************************************/ +void muxSetupCamera(void) +{ + volatile unsigned char *MuxConfigReg; + + /* CAMERA_RSTZ pin configuration, PIN = Y16 */ + /* CAM_RST is connected through the I2C IO expander.*/ + /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/ + /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */ + + /* CAMERA_XCLK pin configuration, PIN = U3 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_LCLK pin configuration, PIN = V5 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_VSYNC pin configuration, PIN = U2 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_HSYNC pin configuration, PIN = T3 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT0 pin configuration, PIN = T4 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT1 pin configuration, PIN = V2 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT2 pin configuration, PIN = V3 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT3 pin configuration, PIN = U4 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT4 pin configuration, PIN = W2 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT5 pin configuration, PIN = V4 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT6 pin configuration, PIN = W3 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT7 pin configuration, PIN = Y2 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT8 pin configuration, PIN = Y4 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* CAMERA_DAT9 pin configuration, PIN = V6 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ +} + +/**************************************** + * Routine: muxSetupMMCSD (ostboot) + * Description: set up MMC muxing + *****************************************/ +void muxSetupMMCSD(void) +{ + volatile unsigned char *MuxConfigReg; + + /* SDMMC_CLKI pin configuration, PIN = H15 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_CLKO pin configuration, PIN = G19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_CMD pin configuration, PIN = H18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DAT0 pin configuration, PIN = F20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DAT1 pin configuration, PIN = H14 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DAT2 pin configuration, PIN = E19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DAT3 pin configuration, PIN = D19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + /* External pull-ups are present. */ + /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ + + /* SDMMC_DDIR0 pin configuration, PIN = F19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_DDIR1 pin configuration, PIN = E20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_DDIR2 pin configuration, PIN = F18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_DDIR3 pin configuration, PIN = E18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* SDMMC_CDIR pin configuration, PIN = G18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/ + /* MMC_CD for 2422IP=K1 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14, + *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ + + /* MMC_WP pin configuration, PIN = B4 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13, + *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ +} + +/****************************************** + * Routine: muxSetupTouchScreen (ostboot) + * Description: Set up touch screen muxing + *******************************************/ +void muxSetupTouchScreen(void) +{ + volatile unsigned char *MuxConfigReg; + + /* SPI1_CLK pin configuration, PIN = U18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* SPI1_MOSI pin configuration, PIN = V20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* SPI1_MISO pin configuration, PIN = T18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* SPI1_nCS0 pin configuration, PIN = U19 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* PEN_IRQ pin configuration, PIN = P20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR, + *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ +} + +/**************************************** + * Routine: muxSetupHDQ (ostboot) + * Description: setup 1wire mux + *****************************************/ +void muxSetupHDQ(void) +{ + volatile unsigned char *MuxConfigReg; + + /* HDQ_SIO pin configuration, PIN = N18 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO, + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ +} + +/*************************************************************** + * Routine: muxSetupGPMC (ostboot) + * Description: Configures balls which cam up in protected mode + ***************************************************************/ +void muxSetupGPMC(void) +{ + volatile uint8 *MuxConfigReg; + volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C; + + /* gpmc_io_dir */ + *MCR = 0x19000000; + + /* NOR FLASH CS0 */ + /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3, + *MuxConfigReg = 0x00 ; + + /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3, + *MuxConfigReg = 0x01 ; + + /* MPDB(Multi Port Debug Port) CS1 */ + /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1, + *MuxConfigReg = 0x00 ; + + /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2, + *MuxConfigReg = 0x00 ; +} + +/**************************************************************** + * Routine: muxSetupSDRC (ostboot) + * Description: Configures balls which come up in protected mode + ****************************************************************/ +void muxSetupSDRC(void) +{ + volatile uint8 *MuxConfigReg; + + /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1, + *MuxConfigReg = 0x00 ; + + /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2, + *MuxConfigReg = 0x00 ; + + /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3 Pull/up - N/A */ + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3, + *MuxConfigReg = 0x00; + + if (get_cpu_type() == CPU_2422) { + MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0, + *MuxConfigReg = 0x1b; + } +} + +/***************************************************************************** + * Routine: update_mux() + * Description: Update balls which are different beween boards. All should be + * updated to match functionaly. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype,u32 mtype) +{ + u32 cpu, base = OMAP2420_CTRL_BASE; + cpu = get_cpu_type(); + + if (btype == BOARD_H4_MENELAUS) { + if (cpu == CPU_2420) { + /* PIN = B3, GPIO.0->KBR5, mode 3, (pun?),-DO-*/ + __raw_writeb(0x3, base+0x30); + /* PIN = B13, GPIO.38->KBC6, mode 3, (pun?)-DO-*/ + __raw_writeb(0x3, base+0xa3); + /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/ + /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/ + /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/ + /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/ + /* PIN = M1 (HSUSBOTG) */ + /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/ + __raw_writeb(0x3, base+0x9d); + /* PIN = U32, (WLAN_CLKREQ) */ + /* PIN = Y11, WLAN */ + /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */ + __raw_writeb(0x3, base+0xe7); + /* PIN = AA8, mDOC */ + /* PIN = AA10, BT */ + /* PIN = AA13, WLAN */ + /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */ + __raw_writeb(0x3, base+0x10e); + /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */ + __raw_writeb(0x3, base+0x110); + /* PIN = J15 HHUSB */ + /* PIN = H19 HSUSB */ + /* PIN = W13, P13, R13, W16 ... */ + /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */ + __raw_writeb(0x3, base+0xde); + /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */ + __raw_writeb(0x0, base+0x12c); + /* PIN = AA17->sys_clkreq mode 0 -DO- */ + __raw_writeb(0x0, base+0x136); + } else if (cpu == CPU_2422) { + /* PIN = B3, GPIO.0->nc, mode 3, set above (pun?)*/ + /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/ + /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/ + /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/ + /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/ + __raw_writeb(0x0, base+0x92); + /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/ + /* PIN = M1 (HSUSBOTG) */ + /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/ + __raw_writeb(0x3, base+0x10c); + /* PIN = U32, (WLAN_CLKREQ) */ + /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */ + __raw_writeb(0x3, base+0x30); + /* PIN = AA8, mDOC */ + /* PIN = AA10, BT */ + /* PIN = AA12, WLAN */ + /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */ + __raw_writeb(0x3, base+0x10e); + /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */ + __raw_writeb(0x3, base+0x110); + /* PIN = J15 HHUSB */ + /* PIN = H19 HSUSB */ + /* PIN = W13, P13, R13, W16 ... */ + /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */ + __raw_writeb(0x3, base+0xde); + /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */ + __raw_writeb(0x0, base+0x12c); + /* PIN = AA17->sys_clkreq mode 0 -DO- */ + __raw_writeb(0x0, base+0x136); + } + + } else if (btype == BOARD_H4_SDP) { + if (cpu == CPU_2420) { + /* PIN = B3, GPIO.0->nc mode 3, set above (pun?)*/ + /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/ + /* Pin = Y11 VLNQ */ + /* Pin = AA4 VLNQ */ + /* Pin = AA6 VLNQ */ + /* Pin = AA8 VLNQ */ + /* Pin = AA10 VLNQ */ + /* Pin = AA12 VLNQ */ + /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */ + __raw_writeb(0x3, base+0x10e); + /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */ + __raw_writeb(0x3, base+0x110); + /* PIN = J15 MDOC_nDMAREQ */ + /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */ + __raw_writeb(0x3, base+0x114); + /* PIN = W13, V12, P13, R13, W19, W16 ... */ + /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */ + } else if (cpu == CPU_2422) { + /* PIN = B3, GPIO.0->MMC_CD, mode 3, set above */ + /* PIN = B13, GPIO.38->wlan_int, mode 3, (pun?)*/ + /* Pin = Y11 VLNQ */ + /* Pin = AA4 VLNQ */ + /* Pin = AA6 VLNQ */ + /* Pin = AA8 VLNQ */ + /* Pin = AA10 VLNQ */ + /* Pin = AA12 VLNQ */ + /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */ + __raw_writeb(0x3, base+0x10e); + /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */ + __raw_writeb(0x3, base+0x110); + /* PIN = J15 MDOC_nDMAREQ */ + /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */ + __raw_writeb(0x3, base+0x114); + /* PIN = W13, V12, P13, R13, W19, W16 ... */ + /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */ + } + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +void nand_init(void) +{ + extern flash_info_t flash_info[]; + + nand_probe(CFG_NAND_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } + +#ifdef CFG_JFFS2_MEM_NAND + flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; + flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */ + flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ + flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ +#endif +} +#endif diff --git a/board/omap2420h4/sys_info.c b/board/omap2420h4/sys_info.c new file mode 100644 index 0000000..a9f7241 --- /dev/null +++ b/board/omap2420h4/sys_info.c @@ -0,0 +1,387 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include + +/************************************************************************** + * get_prod_id() - get id info from chips + ***************************************************************************/ +static u32 get_prod_id(void) +{ + u32 p; + p = __raw_readl(PRODUCTION_ID); /* get production ID */ + return((p & CPU_242X_PID_MASK) >> 16); +} + +/************************************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + * - just looking to say if this is a 2422 or 2420 or ... + * - to start with we will look at switch settings.. + * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics + * (mux for 2420, non-mux for 2422). + ***************************************************************************/ +u32 get_cpu_type(void) +{ + u32 v; + + switch(get_prod_id()){ + case 1:;/* 2420 */ + case 2: return(CPU_2420); break; /* 2420 pop */ + case 4: return(CPU_2422); break; + case 8: return(CPU_2423); break; + default: break; /* early 2420/2422's unmarked */ + } + + v = __raw_readl(TAP_IDCODE_REG); + v &= CPU_24XX_ID_MASK; + if (v == CPU_2420_CHIPID) { /* currently 2420 and 2422 have same id */ + if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */ + return(CPU_2420); + else + return(CPU_2422); + } else + return(CPU_2420); /* don't know, say 2420 */ +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v = v >> 28; + return(v+1); /* currently 2422 and 2420 match up */ +} +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET); + if(*burst == H4_2420_SDRC_MR_0_SDR) + return(1); + return(0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + * 2422 uses stacked DDR, 2 parts CS0/CS1. + * 2420 may have 1 or 2, no good way to know...only init 1... + * when eeprom data is up we can select 1 more. + *************************************************************/ +u32 get_mem_type(void) +{ + u32 cpu, sdr = is_mem_sdr(); + + cpu = get_cpu_type(); + if (cpu == CPU_2422 || cpu == CPU_2423) + return(DDR_STACKED); + + if(get_prod_id() == 0x2) + return(XDR_POP); + + if (get_board_type() == BOARD_H4_MENELAUS) + if(sdr) + return(SDR_DISCRETE); + else + return(DDR_COMBO); + else + if(sdr) /* SDP + SDR kit */ + return(SDR_DISCRETE); + else + return(DDR_DISCRETE); /* origional SDP */ +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */ + size &= 0x2FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return(size); +} + +/*********************************************************************** + * get_board_type() - get board type based on current production stats. + * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + ************************************************************************/ +u32 get_board_type(void) +{ + if (i2c_probe(I2C_MENELAUS) == 0) + return(BOARD_H4_MENELAUS); + else + return(BOARD_H4_SDP); +} + +/****************************************************************** + * get_sysboot_value() - get init word settings (dip switch on h4) + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return(0x00000FFF & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG7_0); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return(b); +} + +/***************************************************************** + * is_gpmc_muxed() - tells if address/data lines are multiplexed + *****************************************************************/ +u32 is_gpmc_muxed(void) +{ + u32 mux; + mux = get_sysboot_value(); + if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3)) + return(GPMC_MUXED); /* NAND Boot mode */ + if (mux & BIT1) /* if mux'ed */ + return(GPMC_MUXED); + else + return(GPMC_NONMUXED); +} + +/************************************************************************ + * get_gpmc0_type() - read sysboot lines to see type of memory attached + ************************************************************************/ +u32 get_gpmc0_type(void) +{ + u32 type; + type = get_sysboot_value(); + if ((type & (BIT3|BIT2)) == (BIT3|BIT2)) + return(TYPE_NAND); + else + return(TYPE_NOR); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + u32 width; + width = get_sysboot_value(); + if ((width & 0xF) == (BIT3|BIT2)) + return(WIDTH_8BIT); + else + return(WIDTH_16BIT); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return(1); + if (i==bound) + return(0); + } while (1); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char cpu_2420[] = "2420"; /* cpu type */ + char cpu_2422[] = "2422"; + char cpu_2423[] = "2423"; + char db_men[] = "Menelaus"; /* board type */ + char db_ip[] = "IP"; + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; + + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if(is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + if(cpu == CPU_2423) + cpu_s = cpu_2423; + else if (cpu == CPU_2422) + cpu_s = cpu_2422; + else + cpu_s = cpu_2420; + + if(btype == BOARD_H4_MENELAUS) + db_s = db_men; + else + db_s = db_ip; + + switch(sec){ + case TST_DEVICE: sec_s = t_tst; break; + case EMU_DEVICE: sec_s = t_emu; break; + case HS_DEVICE: sec_s = t_hs; break; + case GP_DEVICE: sec_s = t_gp; break; + default: sec_s = unk; + } + + printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1); + printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = 242x IP platform (first 2xx boards) + * 1 = 242x Menelaus platfrom. + *************************************************************************/ +u32 get_board_rev(void) +{ + u32 rev = 0; + u32 btype = get_board_type(); + + if (btype == BOARD_H4_MENELAUS){ + rev = 1; + } + return(rev); +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); + val &= 0xF0000000; + val >>= 28; + return(val); +} + +/******************************************************** + * get_base2(); get 2upper addr of current execution + *******************************************************/ +u32 get_base2(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); + val &= 0xFF000000; + val >>= 24; + return(val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return(1); /* in flash */ + return(0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return(1); /* in SRAM */ + return(0); /* running in FLASH or SDRAM */ +} +/******************************************************** + * running_in_sdram() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return(1); /* in sdram */ + return(0); /* running in SRAM or FLASH */ +} + +/************************************************************* + * running_from_internal_boot() - am I a signed NOR image. + *************************************************************/ +u32 running_from_internal_boot(void) +{ + u32 v, base; + + v = get_sysboot_value() & BIT3; + base = get_base2(); + /* if running at mask rom flash address and + * sysboot3 says this was an internal boot + */ + if ((base == 0x08) && v) + return(1); + else + return(0); +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8); + return(mode >>= 8); +} diff --git a/board/omap2420h4/u-boot.lds b/board/omap2420h4/u-boot.lds new file mode 100644 index 0000000..1460adc --- /dev/null +++ b/board/omap2420h4/u-boot.lds @@ -0,0 +1,59 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap5912osk/Makefile b/board/omap5912osk/Makefile new file mode 100644 index 0000000..4b56421 --- /dev/null +++ b/board/omap5912osk/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap5912osk.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap5912osk/config.mk b/board/omap5912osk/config.mk new file mode 100644 index 0000000..0375796 --- /dev/null +++ b/board/omap5912osk/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2002-2004 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Kshitij Gupta +# +# (C) Copyright 2004 +# Texas Instruments, +# Rishi Bhattacharya +# +# TI OSK board with OMAP5912 (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# OSK has 1 bank of 256 MB SDRAM +# Physical Address: +# 1000'0000 to 2000'0000 +# +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# (mem base + reserved) +# +# we load ourself to 1108'0000 +# +# + + +TEXT_BASE = 0x11080000 diff --git a/board/omap5912osk/lowlevel_init.S b/board/omap5912osk/lowlevel_init.S new file mode 100644 index 0000000..3b9633a --- /dev/null +++ b/board/omap5912osk/lowlevel_init.S @@ -0,0 +1,442 @@ +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 + * + * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_OMAP1610) +#include <./configs/omap1510.h> +#endif + + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl lowlevel_init +lowlevel_init: + + + /*------------------------------------------------------* + *mask all IRQs by setting all bits in the INTMR default* + *------------------------------------------------------*/ + mov r1, #0xffffffff + ldr r0, =REG_IHL1_MIR + str r1, [r0] + ldr r0, =REG_IHL2_MIR + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT1) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT1 + ldr r1, VAL_ARM_IDLECT1 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT2) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT2 + ldr r1, VAL_ARM_IDLECT2 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT3) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT3 + ldr r1, VAL_ARM_IDLECT3 + str r1, [r0] + + + mov r1, #0x01 /* PER_EN bit */ + ldr r0, REG_ARM_RSTCT2 + strh r1, [r0] /* CLKM; Peripheral reset. */ + + /* Set CLKM to Sync-Scalable */ + /* I supposedly need to enable the dsp clock before switching */ + mov r1, #0x0000 + ldr r0, REG_ARM_SYSST + strh r1, [r0] + mov r0, #0x400 +1: + subs r0, r0, #0x1 /* wait for any bubbles to finish */ + bne 1b + ldr r1, VAL_ARM_CKCTL + ldr r0, REG_ARM_CKCTL + strh r1, [r0] + + /* a few nops to let settle */ + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* setup DPLL 1 */ + /* Ramp up the clock to 96Mhz */ + ldr r1, VAL_DPLL1_CTL + ldr r0, REG_DPLL1_CTL + strh r1, [r0] + ands r1, r1, #0x10 /* Check if PLL is enabled. */ + beq lock_end /* Do not look for lock if BYPASS selected */ +2: + ldrh r1, [r0] + ands r1, r1, #0x01 /* Check the LOCK bit.*/ + beq 2b /* loop until bit goes hi. */ +lock_end: + + + /*------------------------------------------------------* + * Turn off the watchdog during init... * + *------------------------------------------------------*/ + ldr r0, REG_WATCHDOG + ldr r1, WATCHDOG_VAL1 + str r1, [r0] + ldr r1, WATCHDOG_VAL2 + str r1, [r0] + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL1 + str r1, [r0] + ldr r0, REG_WWPSDOG + +watch1Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch1Wait + + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL2 + str r1, [r0] + ldr r0, REG_WWPSDOG +watch2Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch2Wait + + + /* Set memory timings corresponding to the new clock speed */ + + /* Check execution location to determine current execution location + * and branch to appropriate initialization code. + */ + /* Load physical SDRAM base. */ + mov r0, #0x10000000 + /* Get current execution location. */ + mov r1, pc + /* Compare. */ + cmp r1, r0 + /* Skip over EMIF-fast initialization if running from SDRAM. */ + bge skip_sdram + + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 /* value should be checked */ +3: + subs r3, r3, #0x1 /* Decrement count */ + bne 3b + + + /* + * Set SDRAM control values. Disable refresh before MRS command. + */ + + /* mobile ddr operation */ + ldr r0, REG_SDRAM_OPERATION + mov r2, #07 + str r2, [r0] + + /* config register */ + ldr r0, REG_SDRAM_CONFIG + ldr r1, SDRAM_CONFIG_VAL + str r1, [r0] + + /* manual command register */ + ldr r0, REG_SDRAM_MANUAL_CMD + /* issue set cke high */ + mov r1, #CMD_SDRAM_CKE_SET_HIGH + str r1, [r0] + /* issue nop */ + mov r1, #CMD_SDRAM_NOP + str r1, [r0] + + mov r2, #0x0100 +waitMDDR1: + subs r2, r2, #1 + bne waitMDDR1 /* delay loop */ + + /* issue precharge */ + mov r1, #CMD_SDRAM_PRECHARGE + str r1, [r0] + + /* issue autorefresh x 2 */ + mov r1, #CMD_SDRAM_AUTOREFRESH + str r1, [r0] + str r1, [r0] + + /* mrs register ddr mobile */ + ldr r0, REG_SDRAM_MRS + mov r1, #0x33 + str r1, [r0] + + /* emrs1 low-power register */ + ldr r0, REG_SDRAM_EMRS1 + /* self refresh on all banks */ + mov r1, #0 + str r1, [r0] + + ldr r0, REG_DLL_URD_CONTROL + ldr r1, DLL_URD_CONTROL_VAL + str r1, [r0] + + ldr r0, REG_DLL_LRD_CONTROL + ldr r1, DLL_LRD_CONTROL_VAL + str r1, [r0] + + ldr r0, REG_DLL_WRT_CONTROL + ldr r1, DLL_WRT_CONTROL_VAL + str r1, [r0] + + /* delay loop */ + mov r2, #0x0100 +waitMDDR2: + subs r2, r2, #1 + bne waitMDDR2 + + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 +4: + subs r3, r3, #1 /* Decrement count. */ + bne 4b + b common_tc + +skip_sdram: + + ldr r0, REG_SDRAM_CONFIG + ldr r1, SDRAM_CONFIG_VAL + str r1, [r0] + +common_tc: + /* slow interface */ + ldr r1, VAL_TC_EMIFS_CS0_CONFIG + ldr r0, REG_TC_EMIFS_CS0_CONFIG + str r1, [r0] /* Chip Select 0 */ + + ldr r1, VAL_TC_EMIFS_CS1_CONFIG + ldr r0, REG_TC_EMIFS_CS1_CONFIG + str r1, [r0] /* Chip Select 1 */ + ldr r1, VAL_TC_EMIFS_CS3_CONFIG + ldr r0, REG_TC_EMIFS_CS3_CONFIG + str r1, [r0] /* Chip Select 3 */ + +#ifdef CONFIG_H2_OMAP1610 + /* inserting additional 2 clock cycle hold time for LAN */ + ldr r0, REG_TC_EMIFS_CS1_ADVANCED + ldr r1, VAL_TC_EMIFS_CS1_ADVANCED + str r1, [r0] +#endif + /* Start MPU Timer 1 */ + ldr r0, REG_MPU_LOAD_TIMER + ldr r1, VAL_MPU_LOAD_TIMER + str r1, [r0] + + ldr r0, REG_MPU_CNTL_TIMER + ldr r1, VAL_MPU_CNTL_TIMER + str r1, [r0] + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + + +REG_TC_EMIFS_CONFIG: /* 32 bits */ + .word 0xfffecc0c +REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ + .word 0xfffecc10 +REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ + .word 0xfffecc14 +REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ + .word 0xfffecc18 +REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ + .word 0xfffecc1c + +#ifdef CONFIG_H2_OMAP1610 +REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ + .word 0xfffecc54 +#endif + +/* MPU clock/reset/power mode control registers */ +REG_ARM_CKCTL: /* 16 bits */ + .word 0xfffece00 + +REG_ARM_IDLECT3: /* 16 bits */ + .word 0xfffece24 +REG_ARM_IDLECT2: /* 16 bits */ + .word 0xfffece08 +REG_ARM_IDLECT1: /* 16 bits */ + .word 0xfffece04 + +REG_ARM_RSTCT2: /* 16 bits */ + .word 0xfffece14 +REG_ARM_SYSST: /* 16 bits */ + .word 0xfffece18 +/* DPLL control registers */ +REG_DPLL1_CTL: /* 16 bits */ + .word 0xfffecf00 + +/* Watch Dog register */ +/* secure watchdog stop */ +REG_WSPRDOG: + .word 0xfffeb048 +/* watchdog write pending */ +REG_WWPSDOG: + .word 0xfffeb034 + +WSPRDOG_VAL1: + .word 0x0000aaaa +WSPRDOG_VAL2: + .word 0x00005555 + +/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, + counter @8192 rows, 10 ns, 8 burst */ +REG_SDRAM_CONFIG: + .word 0xfffecc20 + +/* Operation register */ +REG_SDRAM_OPERATION: + .word 0xfffecc80 + +/* Manual command register */ +REG_SDRAM_MANUAL_CMD: + .word 0xfffecc84 + +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ +REG_SDRAM_MRS: + .word 0xfffecc70 + +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ +REG_SDRAM_EMRS1: + .word 0xfffecc78 + +/* WRT DLL register */ +REG_DLL_WRT_CONTROL: + .word 0xfffecc68 +DLL_WRT_CONTROL_VAL: + .word 0x03f00002 + +/* URD DLL register */ +REG_DLL_URD_CONTROL: + .word 0xfffeccc0 +DLL_URD_CONTROL_VAL: + .word 0x00800002 + +/* LRD DLL register */ +REG_DLL_LRD_CONTROL: + .word 0xfffecccc + +REG_WATCHDOG: + .word 0xfffec808 + +REG_MPU_LOAD_TIMER: + .word 0xfffec600 +REG_MPU_CNTL_TIMER: + .word 0xfffec500 + +/* 96 MHz Samsung Mobile DDR */ +SDRAM_CONFIG_VAL: + .word 0x001200f4 + +DLL_LRD_CONTROL_VAL: + .word 0x00800002 + +VAL_ARM_CKCTL: + .word 0x3000 +VAL_DPLL1_CTL: + .word 0x2830 + +#ifdef CONFIG_OSK_OMAP5912 +VAL_TC_EMIFS_CS0_CONFIG: + .word 0x002130b0 +VAL_TC_EMIFS_CS1_CONFIG: + .word 0x00001131 +VAL_TC_EMIFS_CS2_CONFIG: + .word 0x000055f0 +VAL_TC_EMIFS_CS3_CONFIG: + .word 0x88011131 +#endif + +#ifdef CONFIG_H2_OMAP1610 +VAL_TC_EMIFS_CS0_CONFIG: + .word 0x00203331 +VAL_TC_EMIFS_CS1_CONFIG: + .word 0x8180fff3 +VAL_TC_EMIFS_CS2_CONFIG: + .word 0xf800f22a +VAL_TC_EMIFS_CS3_CONFIG: + .word 0x88011131 +VAL_TC_EMIFS_CS1_ADVANCED: + .word 0x00000022 +#endif + +VAL_TC_EMIFF_SDRAM_CONFIG: + .word 0x010290fc +VAL_TC_EMIFF_MRS: + .word 0x00000027 + +VAL_ARM_IDLECT1: + .word 0x00000400 + +VAL_ARM_IDLECT2: + .word 0x00000886 +VAL_ARM_IDLECT3: + .word 0x00000015 + +WATCHDOG_VAL1: + .word 0x000000f5 +WATCHDOG_VAL2: + .word 0x000000a0 + +VAL_MPU_LOAD_TIMER: + .word 0xffffffff +VAL_MPU_CNTL_TIMER: + .word 0xffffffa1 + +/* command values */ +.equ CMD_SDRAM_NOP, 0x00000000 +.equ CMD_SDRAM_PRECHARGE, 0x00000001 +.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 +.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/omap5912osk/omap5912osk.c b/board/omap5912osk/omap5912osk.c new file mode 100644 index 0000000..1faa084 --- /dev/null +++ b/board/omap5912osk/omap5912osk.c @@ -0,0 +1,292 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * (C) Copyright 2004 + * Texas Instruments, + * Rishi Bhattacharya + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_OMAP1610) +#include <./configs/omap1510.h> +#endif + +void flash__init (void); +void ether__init (void); +void set_muxconf_regs (void); +void peripheral_power_enable (void); + +#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + /* Configure MUX settings */ + set_muxconf_regs (); + peripheral_power_enable (); + +/* this speeds up your boot a quite a bit. However to make it + * work, you need make sure your kernel startup flush bug is fixed. + * ... rkw ... + */ + icache_enable (); + + flash__init (); + ether__init (); + return 0; +} + + +int misc_init_r (void) +{ + /* currently empty */ + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ +#define EMIFS_GlB_Config_REG 0xfffecc0c + unsigned int regval; + regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); + /* Turn off write protection for flash devices. */ + regval = regval | 0x0001; + *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; +} +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ +#define ETH_CONTROL_REG 0x0480000b + int i; + + *((volatile unsigned short *) 0xfffece08) = 0x03FF; + *((volatile unsigned short *) 0xfffb3824) = 0x8000; + *((volatile unsigned short *) 0xfffb3830) = 0x0000; + *((volatile unsigned short *) 0xfffb3834) = 0x0009; + *((volatile unsigned short *) 0xfffb3838) = 0x0009; + *((volatile unsigned short *) 0xfffb3818) = 0x0002; + *((volatile unsigned short *) 0xfffb382C) = 0x0048; + *((volatile unsigned short *) 0xfffb3824) = 0x8603; + udelay (3); + for (i=0;i<2000;i++); + *((volatile unsigned short *) 0xfffb381C) = 0x6610; + udelay (30); + for (i=0;i<10000;i++); + + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; + udelay (3); + + +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +/****************************************************** + Routine: set_muxconf_regs + Description: Setting up the configuration Mux registers + specific to the hardware +*******************************************************/ +void set_muxconf_regs (void) +{ + volatile unsigned int *MuxConfReg; + /* set each registers to its reset value; */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); + /* setup for UART1 */ + *MuxConfReg &= ~(0x02000000); /* bit 25 */ + /* setup for UART2 */ + *MuxConfReg &= ~(0x01000000); /* bit 24 */ + /* Disable Uwire CS Hi-Z */ + *MuxConfReg |= 0x08000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); + /*setup mux for UART3 */ + *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ + *MuxConfReg &= ~0x0000003e; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); + /* Disable Uwire CS Hi-Z */ + *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); + /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ + /* hardware will actually use TX and RTS based on bit 25 in */ + /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ + *MuxConfReg |= 0x00201000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); + /* setup for UART2 */ + /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ + /* hardware will actually use TX and RTS based on bit 24 in */ + /* FUNC_MUX_CTRL_0. */ + *MuxConfReg |= 0x09000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D); + *MuxConfReg |= 0x00000020; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); + *MuxConfReg = 0x00000000; + /* mux setup for SD/MMC driver */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); + *MuxConfReg &= 0xFFFE0FFF; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); + /* bit 13 for MMC2 XOR_CLK */ + *MuxConfReg &= ~(0x00002000); + /* bit 29 for UART 1 */ + *MuxConfReg &= ~(0x00002000); + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); + /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ + *MuxConfReg |= 0x000C0000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); + *MuxConfReg &= ~(0x00000070); + *MuxConfReg &= ~(0x00000008); + *MuxConfReg |= 0x00000003; + *MuxConfReg |= 0x00000180; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); + /* bit 17, software controls VBUS */ + *MuxConfReg &= ~(0x00020000); + /* Enable USB 48 and 12M clocks */ + *MuxConfReg |= 0x00000200; + *MuxConfReg &= ~(0x00000180); + /*2.75V for MMCSDIO1 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); + *MuxConfReg = 0x00001FE7; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); + *MuxConfReg = 0x00000000; + /* Turn on UART2 48 MHZ clock */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); + *MuxConfReg |= 0x40000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); + /* setup for USB VBus detection OMAP161x */ + *MuxConfReg |= 0x00040000; /* bit 18 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); + /* PullUps for SD/MMC driver */ + *MuxConfReg |= ~(0xFFFE0FFF); + MuxConfReg = + (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); + *MuxConfReg = COMP_MODE_ENABLE; +} + +/****************************************************** + Routine: peripheral_power_enable + Description: Enable the power for UART1 +*******************************************************/ +void peripheral_power_enable (void) +{ +#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) +#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) + + *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; +} diff --git a/board/omap5912osk/u-boot.lds b/board/omap5912osk/u-boot.lds new file mode 100644 index 0000000..142450c --- /dev/null +++ b/board/omap5912osk/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap730p2/Makefile b/board/omap730p2/Makefile new file mode 100644 index 0000000..29467ac --- /dev/null +++ b/board/omap730p2/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap730p2.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap730p2/config.mk b/board/omap730p2/config.mk new file mode 100644 index 0000000..16bff6f --- /dev/null +++ b/board/omap730p2/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Kshitij Gupta +# +# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Innovator has 1 bank of 256 MB SDRAM +# Physical Address: +# 1000'0000 to 2000'0000 +# +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# (mem base + reserved) +# +# we load ourself to 1108'0000 +# +# + +TEXT_BASE = 0x11080000 diff --git a/board/omap730p2/flash.c b/board/omap730p2/flash.c new file mode 100644 index 0000000..e7d6515 --- /dev/null +++ b/board/omap730p2/flash.c @@ -0,0 +1,477 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, 32 * 1024}, /* 4 * 32kBytes sectors */ + {255, 128 * 1024}, /* 255 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + OrgDef *pOrgDef; + + pOrgDef = OrgIntel_28F256L18T; + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 255) { + info->start[i] = base + (i * 0x8000); + info->protect[i] = 0; + } else { + info->start[i] = base + + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; + info->size = 0x02000000; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + flash_unprotect_sectors (addr); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/omap730p2/lowlevel_init.S b/board/omap730p2/lowlevel_init.S new file mode 100644 index 0000000..6c6f482 --- /dev/null +++ b/board/omap730p2/lowlevel_init.S @@ -0,0 +1,395 @@ +/* + * Board specific setup info + * + * (C) Copyright 2003-2004 + * + * Texas Instruments, + * Kshitij Gupta + * + * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 + * + * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited + * (http://www.mpc-data.co.uk) + * + * TODO : Tidy up and change to use system register defines + * from omap730.h where possible. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_OMAP730) +#include <./configs/omap730.h> +#endif + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl lowlevel_init +lowlevel_init: + /* Save callers address in r11 - r11 must never be modified */ + mov r11, lr + + /*------------------------------------------------------* + *mask all IRQs by setting all bits in the INTMR default* + *------------------------------------------------------*/ + mov r1, #0xffffffff + ldr r0, =REG_IHL1_MIR + str r1, [r0] + ldr r0, =REG_IHL2_MIR + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT1) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT1 + ldr r1, VAL_ARM_IDLECT1 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT2) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT2 + ldr r1, VAL_ARM_IDLECT2 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT3) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT3 + ldr r1, VAL_ARM_IDLECT3 + str r1, [r0] + + + mov r1, #0x01 /* PER_EN bit */ + ldr r0, REG_ARM_RSTCT2 + strh r1, [r0] /* CLKM; Peripheral reset. */ + + /* Set CLKM to Sync-Scalable */ + /* I supposedly need to enable the dsp clock before switching */ + mov r1, #0x1000 + ldr r0, REG_ARM_SYSST + strh r1, [r0] + mov r0, #0x400 +1: + subs r0, r0, #0x1 /* wait for any bubbles to finish */ + bne 1b + ldr r1, VAL_ARM_CKCTL + ldr r0, REG_ARM_CKCTL + strh r1, [r0] + + /* a few nops to let settle */ + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* setup DPLL 1 */ + /* Ramp up the clock to 96Mhz */ + ldr r1, VAL_DPLL1_CTL + ldr r0, REG_DPLL1_CTL + strh r1, [r0] + ands r1, r1, #0x10 /* Check if PLL is enabled. */ + beq lock_end /* Do not look for lock if BYPASS selected */ +2: + ldrh r1, [r0] + ands r1, r1, #0x01 /* Check the LOCK bit.*/ + beq 2b /* loop until bit goes hi. */ +lock_end: + + /*------------------------------------------------------* + * Turn off the watchdog during init... * + *------------------------------------------------------*/ + ldr r0, REG_WATCHDOG + ldr r1, WATCHDOG_VAL1 + str r1, [r0] + ldr r1, WATCHDOG_VAL2 + str r1, [r0] + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL1 + str r1, [r0] + ldr r0, REG_WWPSDOG + +watch1Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch1Wait + + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL2 + str r1, [r0] + ldr r0, REG_WWPSDOG +watch2Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch2Wait + + /* Set memory timings corresponding to the new clock speed */ + + /* Check execution location to determine current execution location + * and branch to appropriate initialization code. + */ + /* Compare physical SDRAM base & current execution location. */ + and r0, pc, #0xF0000000 + /* Compare. */ + cmp r0, #0 + /* Skip over EMIF-fast initialization if running from SDRAM. */ + bne skip_sdram + + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 /* value should be checked */ +3: + subs r3, r3, #0x1 /* Decrement count */ + bne 3b + + ldr r0, REG_SDRAM_CONFIG + ldr r1, SDRAM_CONFIG_VAL + str r1, [r0] + + ldr r0, REG_SDRAM_MRS_LEGACY + ldr r1, SDRAM_MRS_VAL + str r1, [r0] + +skip_sdram: + +common_tc: + /* slow interface */ + ldr r1, VAL_TC_EMIFS_CS0_CONFIG + ldr r0, REG_TC_EMIFS_CS0_CONFIG + str r1, [r0] /* Chip Select 0 */ + + ldr r1, VAL_TC_EMIFS_CS1_CONFIG + ldr r0, REG_TC_EMIFS_CS1_CONFIG + str r1, [r0] /* Chip Select 1 */ + ldr r1, VAL_TC_EMIFS_CS2_CONFIG + ldr r0, REG_TC_EMIFS_CS2_CONFIG + str r1, [r0] /* Chip Select 2 */ + ldr r1, VAL_TC_EMIFS_CS3_CONFIG + ldr r0, REG_TC_EMIFS_CS3_CONFIG + str r1, [r0] /* Chip Select 3 */ + + /* 48MHz clock request for UART1 */ + ldr r1, PERSEUS2_CONFIG_BASE + ldrh r0, [r1, #CONFIG_PCC_CONF] + orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R + strh r0, [r1, #CONFIG_PCC_CONF] + + /* Initialize public and private rheas + * - set access factor 2 on both rhea / strobe + * - disable write buffer on strb0, enable write buffer on strb1 + */ + + ldr R0, REG_RHEA_PUB_CTL + ldr R1, REG_RHEA_PRIV_CTL + ldr R2, VAL_RHEA_CTL + strh R2, [R0] + strh R2, [R1] + mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */ + strh R3, [R0, #0x08] /* arm rhea control reg */ + strh R3, [R1, #0x08] + + /* enable IRQ and FIQ */ + + mrs r4, CPSR + bic r4, r4, #IRQ_MASK + bic r4, r4, #FIQ_MASK + msr CPSR, r4 + + /* set TAP CONF to TRI EMULATION */ + + ldr r1, [r0, #CONFIG_MODE2] + bic r1, r1, #0x18 + orr r1, r1, #0x10 + str r1, [r0, #CONFIG_MODE2] + + /* set tdbgen to 1 */ + + ldr r0, PERSEUS2_CONFIG_BASE + ldr r1, [r0, #CONFIG_MODE1] + mov r2, #0x10000 + orr r1, r1, r2 + str r1, [r0, #CONFIG_MODE1] + +#ifdef CONFIG_P2_OMAP1610 + /* inserting additional 2 clock cycle hold time for LAN */ + ldr r0, REG_TC_EMIFS_CS1_ADVANCED + ldr r1, VAL_TC_EMIFS_CS1_ADVANCED + str r1, [r0] +#endif + /* Start MPU Timer 1 */ + ldr r0, REG_MPU_LOAD_TIMER + ldr r1, VAL_MPU_LOAD_TIMER + str r1, [r0] + + ldr r0, REG_MPU_CNTL_TIMER + ldr r1, VAL_MPU_CNTL_TIMER + str r1, [r0] + + /* back to arch calling code */ + mov pc, r11 + + /* the literal pools origin */ + .ltorg + +REG_TC_EMIFS_CONFIG: /* 32 bits */ + .word 0xfffecc0c +REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ + .word 0xfffecc10 +REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ + .word 0xfffecc14 +REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ + .word 0xfffecc18 +REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ + .word 0xfffecc1c + +#ifdef CONFIG_P2_OMAP730 +REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ + .word 0xfffecc54 +#endif + +/* MPU clock/reset/power mode control registers */ +REG_ARM_CKCTL: /* 16 bits */ + .word 0xfffece00 + +REG_ARM_IDLECT3: /* 16 bits */ + .word 0xfffece24 +REG_ARM_IDLECT2: /* 16 bits */ + .word 0xfffece08 +REG_ARM_IDLECT1: /* 16 bits */ + .word 0xfffece04 + +REG_ARM_RSTCT2: /* 16 bits */ + .word 0xfffece14 +REG_ARM_SYSST: /* 16 bits */ + .word 0xfffece18 +/* DPLL control registers */ +REG_DPLL1_CTL: /* 16 bits */ + .word 0xfffecf00 + +/* Watch Dog register */ +/* secure watchdog stop */ +REG_WSPRDOG: + .word 0xfffeb048 +/* watchdog write pending */ +REG_WWPSDOG: + .word 0xfffeb034 + +WSPRDOG_VAL1: + .word 0x0000aaaa +WSPRDOG_VAL2: + .word 0x00005555 + +/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, + counter @8192 rows, 10 ns, 8 burst */ +REG_SDRAM_CONFIG: + .word 0xfffecc20 + +REG_SDRAM_MRS_LEGACY: + .word 0xfffecc24 + +REG_WATCHDOG: + .word 0xfffec808 + +REG_MPU_LOAD_TIMER: + .word 0xfffec600 +REG_MPU_CNTL_TIMER: + .word 0xfffec500 + +/* Public and private rhea bridge registers definition */ + +REG_RHEA_PUB_CTL: + .word 0xFFFECA00 + +REG_RHEA_PRIV_CTL: + .word 0xFFFED300 + +/* EMIFF SDRAM Configuration register + - self refresh disable + - auto refresh enabled + - SDRAM type 64 Mb, 16 bits bus 4 banks + - power down enabled + - SDRAM clock disabled + */ +SDRAM_CONFIG_VAL: + .word 0x0C017DF4 + +/* Burst full page length ; cas latency = 3 */ +SDRAM_MRS_VAL: + .word 0x00000037 + +VAL_ARM_CKCTL: + .word 0x6505 +VAL_DPLL1_CTL: + .word 0x3412 + +#ifdef CONFIG_P2_OMAP730 +VAL_TC_EMIFS_CS0_CONFIG: + .word 0x0000FFF3 +VAL_TC_EMIFS_CS1_CONFIG: + .word 0x00004278 +VAL_TC_EMIFS_CS2_CONFIG: + .word 0x00004278 +VAL_TC_EMIFS_CS3_CONFIG: + .word 0x00004278 +VAL_TC_EMIFS_CS1_ADVANCED: + .word 0x00000022 +#endif + +VAL_ARM_IDLECT1: + .word 0x00000400 +VAL_ARM_IDLECT2: + .word 0x00000886 +VAL_ARM_IDLECT3: + .word 0x00000015 + +WATCHDOG_VAL1: + .word 0x000000f5 +WATCHDOG_VAL2: + .word 0x000000a0 + +VAL_MPU_LOAD_TIMER: + .word 0xffffffff +VAL_MPU_CNTL_TIMER: + .word 0xffffffa1 + +VAL_RHEA_CTL: + .word 0xFF22 + +/* Config Register vals */ +PERSEUS2_CONFIG_BASE: + .word 0xFFFE1000 + +.equ CONFIG_PCC_CONF, 0xB4 +.equ CONFIG_MODE1, 0x10 +.equ CONFIG_MODE2, 0x14 +.equ CONF_MOD_UART1_CLK_MODE_R, 0x0A + +/* misc values */ +.equ IRQ_MASK, 0x80 /* IRQ mask value */ +.equ FIQ_MASK, 0x40 /* FIQ mask value */ diff --git a/board/omap730p2/omap730p2.c b/board/omap730p2/omap730p2.c new file mode 100644 index 0000000..256c6a6 --- /dev/null +++ b/board/omap730p2/omap730p2.c @@ -0,0 +1,267 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_OMAP730) +#include <./configs/omap730.h> +#endif + +int test_boot_mode(void); +void spin_up_leds(void); +void flash__init (void); +void ether__init (void); +void set_muxconf_regs (void); +void peripheral_power_enable (void); + +#define FLASH_ON_CS0 1 +#define FLASH_ON_CS3 0 + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +int test_boot_mode(void) +{ + /* Check for CS0 and CS3 address decode swapping */ + if (*((volatile int *)EMIFS_CONFIG) & 0x00000002) + return(FLASH_ON_CS3); + else + return(FLASH_ON_CS0); +} + +/* Toggle backup LED indication */ +void toggle_backup_led(void) +{ + static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */ + volatile unsigned int *IOConfReg; + + + IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT); + + if (backupLEDState != 0) { + *IOConfReg &= (0xFFFFEFFF); + backupLEDState = 0; + } else { + *IOConfReg |= (0x00001000); + backupLEDState = 1; + } +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of OMAP 730 P2 Board - Same as the Innovator! */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + /* Configure MUX settings */ + set_muxconf_regs (); + + peripheral_power_enable (); + + /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */ + toggle_backup_led(); + + /* Hold GSM in reset until needed */ + *((volatile unsigned short *)M_CTL) &= ~1; + + /* + * CSx timings, GPIO Mux ... setup + */ + + /* Flash: CS0 timings setup */ + *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3; + *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088; + + /* Ethernet support trough the debug board */ + /* CS1 timings setup */ + *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3; + *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000; + + /* this speeds up your boot a quite a bit. However to make it + * work, you need make sure your kernel startup flush bug is fixed. + * ... rkw ... + */ + icache_enable (); + + flash__init (); + ether__init (); + + return 0; +} + +int misc_init_r (void) +{ + /* currently empty */ + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ + unsigned int regval; + + regval = *((volatile unsigned int *) EMIFS_CONFIG); + /* Turn off write protection for flash devices. */ + regval = regval | 0x0001; + *((volatile unsigned int *) EMIFS_CONFIG) = regval; +} + +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ +#define LAN_RESET_REGISTER 0x0400001c + + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; + do { + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; + udelay (100); + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); + + do { + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; + udelay (100); + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); + +#define ETH_CONTROL_REG 0x0400030b + + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; + udelay (100); +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +/****************************************************** + Routine: set_muxconf_regs + Description: Setting up the configuration Mux registers + specific to the hardware +*******************************************************/ +void set_muxconf_regs (void) +{ + volatile unsigned int *MuxConfReg; + /* set each registers to its reset value; */ + + /* + * Backup LED Indication + */ + + /* Configure MUXed pin. Mode 6: GPIO_140 */ + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10); + *MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */ + *MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */ + + /* Configure GPIO_140 as output */ + MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL); + *MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */ + + /* + * Configure GPIOs for battery charge & feedback + */ + + /* Configure MUXed pin. Mode 6: GPIO_35 */ + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); + *MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */ + *MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */ + + /* Configure MUXed pin. Mode 6: GPIO_72,73,74 */ + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5); + *MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */ + *MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */ + + MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL); + *MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */ + *MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */ + + /* + * Allow battery charge + */ + + MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT); + *MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */ + + /* + * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, + * It is used as the Ethernet controller interrupt + */ + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9); + *MuxConfReg &= 0x1FFFFFFF; +} + +/****************************************************** + Routine: peripheral_power_enable + Description: Enable the power for UART1 +*******************************************************/ +void peripheral_power_enable (void) +{ + volatile unsigned int *MuxConfReg; + + + /* Set up pins used by UART */ + + /* Start UART clock (48MHz) */ + MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG); + *MuxConfReg &= (0xFFFFFFF7); + *MuxConfReg |= (0x00000008); + + /* Get the UART pin in mode0 */ + MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); + *MuxConfReg &= (0xFF1FFFFF); + *MuxConfReg &= (0xF1FFFFFF); +} diff --git a/board/omap730p2/u-boot.lds b/board/omap730p2/u-boot.lds new file mode 100644 index 0000000..710b2a2 --- /dev/null +++ b/board/omap730p2/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/oxc/Makefile b/board/oxc/Makefile new file mode 100644 index 0000000..ae7a932 --- /dev/null +++ b/board/oxc/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/oxc/config.mk b/board/oxc/config.mk new file mode 100644 index 0000000..7a5bcfc --- /dev/null +++ b/board/oxc/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# OXC boards +# + +#TEXT_BASE = 0x00090000 +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/oxc/flash.c b/board/oxc/flash.c new file mode 100644 index 0000000..795b7cc --- /dev/null +++ b/board/oxc/flash.c @@ -0,0 +1,372 @@ +/* + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for STM29W320DB/STM29W800D flash chips + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +static ulong flash_get_size (vu_char *addr, flash_info_t *info); +static int write_byte (flash_info_t *info, ulong dest, uchar data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_PRELIMBASE) + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_STM: + printf ("ST "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_STM320DB: + printf ("M29W320DB (32 Mbit)\n"); + break; + case FLASH_STM800DB: + printf ("M29W800DB (8 Mbit, bottom boot block)\n"); + break; + case FLASH_STM800DT: + printf ("M29W800DT (8 Mbit, top boot block)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_char *addr, flash_info_t *info) +{ + short i; + uchar vendor, devid; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0AAA] = 0xAA; + addr[0x0555] = 0x55; + addr[0x0AAA] = 0x90; + + udelay(1000); + + vendor = addr[0]; + devid = addr[2]; + + /* only support STM */ + if ((vendor << 16) != FLASH_MAN_STM) { + return 0; + } + + if (devid == FLASH_STM320DB) { + /* MPC8240 can address maximum 2Mb of flash, that is why the MSB + * lead is grounded and we can access only 2 first Mb */ + info->flash_id = vendor << 16 | devid; + info->sector_count = 32; + info->size = info->sector_count * 0x10000; + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + i * 0x10000; + } + } + else if (devid == FLASH_STM800DB) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 19; + info->size = 0x100000; + info->start[0] = 0x0000; + info->start[1] = 0x4000; + info->start[2] = 0x6000; + info->start[3] = 0x8000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i-3) * 0x10000; + } + } + else if (devid == FLASH_STM800DT) { + info->flash_id = vendor << 16 | devid; + info->sector_count = 19; + info->size = 0x100000; + for (i = 0; i < info->sector_count-4; i++) { + info->start[i] = base + i * 0x10000; + } + info->start[i] = base + i * 0x10000; + info->start[i+1] = base + i * 0x10000 + 0x8000; + info->start[i+2] = base + i * 0x10000 + 0xa000; + info->start[i+3] = base + i * 0x10000 + 0xc000; + } + else { + return 0; + } + + /* mark all sectors as unprotected */ + for (i = 0; i < info->sector_count; i++) { + info->protect[i] = 0; + } + + /* Issue the reset command */ + if (info->flash_id != FLASH_UNKNOWN) { + addr[0] = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_char *addr = (vu_char *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0AAA] = 0xAA; + addr[0x0555] = 0x55; + addr[0x0AAA] = 0x80; + addr[0x0AAA] = 0xAA; + addr[0x0555] = 0x55; + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_char *)(info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_char *)(info->start[l_sect]); + while ((addr[0] & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + int rc; + + while (cnt > 0) { + if ((rc = write_byte(info, addr, *src)) != 0) { + return (rc); + } + addr++; + src++; + cnt--; + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a byte to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_byte (flash_info_t *info, ulong dest, uchar data) +{ + vu_char *addr = (vu_char *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_char *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0AAA] = 0xAA; + addr[0x0555] = 0x55; + addr[0x0AAA] = 0xA0; + + *((vu_char *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c new file mode 100644 index 0000000..fa7ff02 --- /dev/null +++ b/board/oxc/oxc.c @@ -0,0 +1,217 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +int checkboard (void) +{ + puts ( "Board: OXC8240\n" ); + return 0; +} + +long int initdram (int board_type) +{ +#ifndef CFG_RAMBOOT + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +#else + /* if U-Boot starts from RAM, then suppose we have 16Mb of RAM */ + return (16 << 20); +#endif +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_oxc_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x14, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x15, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { } +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_oxc_config_table, +#endif +}; + +void pci_init_board (void) +{ + pci_mpc824x_init(&hose); +} + +int board_early_init_f (void) +{ + *(volatile unsigned char *)(CFG_CPLD_RESET) = 0x89; + return 0; +} + +#ifdef CONFIG_WATCHDOG +void oxc_wdt_reset(void) +{ + *(volatile unsigned char *)(CFG_CPLD_WATCHDOG) = 0xff; +} + +void watchdog_reset(void) +{ + int re_enable = disable_interrupts(); + + oxc_wdt_reset(); + if (re_enable) + enable_interrupts(); +} +#endif + +static int oxc_get_expander(unsigned char addr, unsigned char * val) +{ + return i2c_read(addr, 0, 0, val, 1); +} + +static int oxc_set_expander(unsigned char addr, unsigned char val) +{ + return i2c_write(addr, 0, 0, &val, 1); +} + +static int expander0alive = 0; + +#ifdef CONFIG_SHOW_ACTIVITY +static int ledtoggle = 0; +static int ledstatus = 1; + +void oxc_toggle_activeled(void) +{ + ledtoggle++; +} + +void board_show_activity (ulong timestamp) +{ + if ((timestamp % (CFG_HZ / 10)) == 0) + oxc_toggle_activeled (); +} + +void show_activity(int arg) +{ + static unsigned char led = 0; + unsigned char val; + + if (!expander0alive) return; + + if ((ledtoggle > (2 * arg)) && ledstatus) { + led ^= 0x80; + oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val); + udelay(200); + oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, (val & 0x7F) | led); + ledtoggle = 0; + } +} +#endif + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int arg) +{ + unsigned char val; + + if (!expander0alive) return; + + if (arg > 0 && ledstatus) { + ledstatus = 0; + oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val); + udelay(200); + oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val | 0x80); + } else if (arg < 0) { + oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val); + udelay(200); + oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val & 0x7F); + ledstatus = 1; + } +} +#endif + +int misc_init_r (void) +{ + /* check whether the i2c expander #0 is accessible */ + if (!oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, 0x7F)) { + udelay(200); + expander0alive = 1; + } + +#ifdef CFG_OXC_GENERATE_IP + { + DECLARE_GLOBAL_DATA_PTR; + + char str[32]; + unsigned long ip = CFG_OXC_IPMASK; + bd_t *bd = gd->bd; + + if (expander0alive) { + unsigned char val; + + if (!oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val)) { + ip = (ip & 0xffffff00) | ((val & 0x7c) >> 2); + } + } + + if ((ip & 0xff) < 3) { + /* if fail, set x.x.x.254 */ + ip = (ip & 0xffffff00) | 0xfe; + } + + bd->bi_ip_addr = ip; + sprintf(str, "%ld.%ld.%ld.%ld", + (bd->bi_ip_addr & 0xff000000) >> 24, + (bd->bi_ip_addr & 0x00ff0000) >> 16, + (bd->bi_ip_addr & 0x0000ff00) >> 8, + (bd->bi_ip_addr & 0x000000ff)); + setenv("ipaddr", str); + printf("ip: %s\n", str); + } +#endif + return (0); +} diff --git a/board/oxc/u-boot.lds b/board/oxc/u-boot.lds new file mode 100644 index 0000000..2a5cd2e --- /dev/null +++ b/board/oxc/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile new file mode 100644 index 0000000..d1cdc6b --- /dev/null +++ b/board/pb1x00/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o +SOBJS = memsetup.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/pb1x00/README b/board/pb1x00/README new file mode 100644 index 0000000..b37ff36 --- /dev/null +++ b/board/pb1x00/README @@ -0,0 +1,63 @@ +By Thomas.Lange@corelatus.se 2004-Oct-05 +---------------------------------------- +DbAu1xx0 are development boards from AMD containing +an Alchemy AU1xx0 series cpu with mips32 core. +Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 + +Limitations & comments +---------------------- +Support was originally big endian only. +I have not tested, but several u-boot users report working +configurations in little endian mode. + +I named the board dbau1x00, to allow +support for all three development boards +( dbau1000, dbau1100 and dbau1500 ). +Now there is a new board called dbau1550 also, which +should be supported RSN. + +I only have a dbau1000, so my testing is limited +to this board. + +The board has two different flash banks, that can +be selected via dip switch. This makes it possible +to test new bootloaders without thrashing the YAMON +boot loader delivered with board. + +NOTE! When you switch between the two boot flashes, the +base addresses will be swapped. +Have this in mind when you compile u-boot. TEXT_BASE has +to match the address where u-boot is located when you +actually launch. + +Ethernet only supported for mac0. + +PCMCIA only supported for slot 0, only 3.3V. + +PCMCIA IDE tested with Sandisk Compact Flash and +IBM microdrive. + +################################### +######## NOTE!!!!!! ######### +################################### +If you partition a disk on another system (e.g. laptop), +all bytes will be swapped on 16bit level when using +PCMCIA and running cpu in big endian mode!!!! + +This is probably due to an error in Au1000 chip. + +Solution: + +a) Boot via network and partition disk directly from +dbau1x00. The endian will then be correct. + +b) Partition disk on "laptop" and fill it with all files +you need. Then write a simple program that endian swaps +whole disk, + +Example: +Original "laptop" byte order: +B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... + +Dbau1000 byte order will then be: +B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... diff --git a/board/pb1x00/config.mk b/board/pb1x00/config.mk new file mode 100644 index 0000000..396a045 --- /dev/null +++ b/board/pb1x00/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AMD development board AMD Alchemy Pb1x00, MIPS32 core +# + +# ROM version +#TEXT_BASE = 0xbfc00000 + +# SDRAM version +TEXT_BASE = 0x83800000 diff --git a/board/pb1x00/flash.c b/board/pb1x00/flash.c new file mode 100644 index 0000000..3cf29e8 --- /dev/null +++ b/board/pb1x00/flash.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + printf ("Skipping flash_init\n"); + return (0); +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + printf ("write_buff not implemented\n"); + return (-1); +} diff --git a/board/pb1x00/memsetup.S b/board/pb1x00/memsetup.S new file mode 100644 index 0000000..44f02b9 --- /dev/null +++ b/board/pb1x00/memsetup.S @@ -0,0 +1,392 @@ +/* Memory sub-system initialization code */ + +#include +#include +#include +#include +#include + +#define AU1500_SYS_ADDR 0xB1900000 +#define sys_endian 0x0038 +#define CP0_Config0 $16 +#define MEM_1MS ((396000000/1000000) * 1000) + + .text + .set noreorder + .set mips32 + + .globl memsetup +memsetup: + /* + * Step 1) Establish CPU endian mode. + * NOTE: A fair amount of code is necessary on the Pb1000 to + * obtain the value of Switch S8.1 which is used to determine + * endian at run-time. + */ + + /* RCE1 */ + li t0, MEM_STCFG1 + li t1, 0x00000083 + sw t1, 0(t0) + + li t0, MEM_STTIME1 + li t1, 0x33030A10 + sw t1, 0(t0) + + li t0, MEM_STADDR1 + li t1, 0x11803E40 + sw t1, 0(t0) + + /* Set DSTRB bits so switch will read correctly */ + li t1, 0xBE00000C + lw t2, 0(t1) + or t2, t2, 0x00000300 + sw t2, 0(t1) + + /* Check switch setting */ + li t1, 0xBE000014 + lw t2, 0(t1) + and t2, t2, 0x00000100 + bne t2, zero, big_endian + nop + +little_endian: + + /* Change Au1 core to little endian */ + li t0, AU1500_SYS_ADDR + li t1, 1 + sw t1, sys_endian(t0) + mfc0 t2, CP0_CONFIG + mtc0 t2, CP0_CONFIG + nop + nop + + /* Big Endian is default so nothing to do but fall through */ + +big_endian: + + /* + * Step 2) Establish Status Register + * (set BEV, clear ERL, clear EXL, clear IE) + */ + li t1, 0x00400000 + mtc0 t1, CP0_STATUS + + /* + * Step 3) Establish CP0 Config0 + * (set OD, set K0=3) + */ + li t1, 0x00080003 + mtc0 t1, CP0_CONFIG + + /* + * Step 4) Disable Watchpoint facilities + */ + li t1, 0x00000000 + mtc0 t1, CP0_WATCHLO + mtc0 t1, CP0_IWATCHLO + /* + * Step 5) Disable the performance counters + */ + mtc0 zero, CP0_PERFORMANCE + nop + + /* + * Step 6) Establish EJTAG Debug register + */ + mtc0 zero, CP0_DEBUG + nop + + /* + * Step 7) Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + /* First setup pll:s to make serial work ok */ + /* We have a 12 MHz crystal */ + li t0, SYS_CPUPLL + li t1, 0x21 /* 396 MHz */ + sw t1, 0(t0) + sync + nop + nop + + /* wait 1mS for clocks to settle */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + /* Setup AUX PLL */ + li t0, SYS_AUXPLL + li t1, 8 /* 96 MHz */ + sw t1, 0(t0) /* aux pll */ + sync + + /* Static memory controller */ + + /* RCE0 8MB AMD29D323 Flash */ + li t0, MEM_STCFG0 + li t1, 0x00001403 + sw t1, 0(t0) + + li t0, MEM_STTIME0 + li t1, 0xFFFFFFDD + sw t1, 0(t0) + + li t0, MEM_STADDR0 + li t1, 0x11F83FE0 + sw t1, 0(t0) + + /* RCE1 CPLD Board Logic */ + li t0, MEM_STCFG1 + li t1, 0x00000083 + sw t1, 0(t0) + + li t0, MEM_STTIME1 + li t1, 0x33030A10 + sw t1, 0(t0) + + li t0, MEM_STADDR1 + li t1, 0x11803E40 + sw t1, 0(t0) + + /* RCE2 CPLD Board Logic */ + li t0, MEM_STCFG2 + li t1, 0x00000004 + sw t1, 0(t0) + + li t0, MEM_STTIME2 + li t1, 0x08061908 + sw t1, 0(t0) + + li t0, MEM_STADDR2 + li t1, 0x12A03FC0 + sw t1, 0(t0) + + /* RCE3 PCMCIA 250ns */ + li t0, MEM_STCFG3 + li t1, 0x00000002 + sw t1, 0(t0) + + li t0, MEM_STTIME3 + li t1, 0x280E3E07 + sw t1, 0(t0) + + li t0, MEM_STADDR3 + li t1, 0x10000000 + sw t1, 0(t0) + + sync + + /* Set peripherals to a known state */ + li t0, IC0_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC0_CFG0CLR + sw t1, 0(t0) + + li t0, IC0_CFG1CLR + sw t1, 0(t0) + + li t0, IC0_CFG2CLR + sw t1, 0(t0) + + li t0, IC0_SRCSET + sw t1, 0(t0) + + li t0, IC0_ASSIGNSET + sw t1, 0(t0) + + li t0, IC0_WAKECLR + sw t1, 0(t0) + + li t0, IC0_RISINGCLR + sw t1, 0(t0) + + li t0, IC0_FALLINGCLR + sw t1, 0(t0) + + li t0, IC0_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, IC1_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC1_CFG0CLR + sw t1, 0(t0) + + li t0, IC1_CFG1CLR + sw t1, 0(t0) + + li t0, IC1_CFG2CLR + sw t1, 0(t0) + + li t0, IC1_SRCSET + sw t1, 0(t0) + + li t0, IC1_ASSIGNSET + sw t1, 0(t0) + + li t0, IC1_WAKECLR + sw t1, 0(t0) + + li t0, IC1_RISINGCLR + sw t1, 0(t0) + + li t0, IC1_FALLINGCLR + sw t1, 0(t0) + + li t0, IC1_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, SYS_FREQCTRL0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_FREQCTRL1 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_CLKSRC + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_PININPUTEN + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, 0xB1100100 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, 0xB1400100 + li t1, 0x00000000 + sw t1, 0(t0) + + + li t0, SYS_WAKEMSK + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_WAKESRC + li t1, 0x00000000 + sw t1, 0(t0) + + /* wait 1mS before setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + + /* + * Skip memory setup if we are running from memory + */ + li t0, 0x90000000 + sub t0, ra, t0 + bltz t0, skip_memsetup + nop + + /* + * SDCS0 - Not used, for SMROM + * SDCS1 - 32MB Micron 48LCBM16A2 + * SDCS2 - 32MB Micron 48LCBM16A2 + */ + li t0, MEM_SDMODE0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_SDMODE1 + li t1, 0x00552229 + sw t1, 0(t0) + + li t0, MEM_SDMODE2 + li t1, 0x00552229 + sw t1, 0(t0) + + li t0, MEM_SDADDR0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_SDADDR1 + li t1, 0x001003F8 + sw t1, 0(t0) + + li t0, MEM_SDADDR2 + li t1, 0x001023F8 + sw t1, 0(t0) + + sync + + li t0, MEM_SDREFCFG + li t1, 0x74000c30 /* Disable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDPRECMD + sw zero, 0(t0) + sync + + li t0, MEM_SDAUTOREF + sw zero, 0(t0) + sync + sw zero, 0(t0) + sync + + li t0, MEM_SDREFCFG + li t1, 0x76000c30 /* Enable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD0 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD1 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD2 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + /* wait 1mS after setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + +skip_memsetup: + + li t0, SYS_PINFUNC + li t1, 0/*0x00008080*/ + sw t1, 0(t0) + + /* + li t0, SYS_TRIOUTCLR + li t1, 0x00001FFF + sw t1, 0(t0) + + li t0, SYS_OUTPUTCLR + li t1, 0x00008000 + sw t1, 0(t0) + */ + sync + + j ra + nop diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c new file mode 100644 index 0000000..40ac2a4 --- /dev/null +++ b/board/pb1x00/pb1x00.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2003 + * Thomas.Lange@corelatus.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +long int initdram(int board_type) +{ + /* Sdram is setup by assembler code */ + /* If memory could be changed, we should return the true value here */ + return 64*1024*1024; +} + +#define BCSR_PCMCIA_PC0DRVEN 0x0010 +#define BCSR_PCMCIA_PC0RST 0x0080 + +/* In cpu/mips/cpu.c */ +void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); + +int checkboard (void) +{ + u16 status; + /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */ + volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; + u32 proc_id; + + *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ + + proc_id = read_32bit_cp0_register(CP0_PRID); + + switch (proc_id >> 24) { + case 0: + puts ("Board: Pb1000\n"); + printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", + (proc_id >> 8) & 0xFF, proc_id & 0xFF); + break; + case 1: + puts ("Board: Pb1500\n"); + printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", + (proc_id >> 8) & 0xFF, proc_id & 0xFF); + break; + case 2: + puts ("Board: Pb1100\n"); + printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", + (proc_id >> 8) & 0xFF, proc_id & 0xFF); + break; + default: + printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); + } +#if defined(CONFIG_IDE_PCMCIA) && 0 + /* Enable 3.3 V on slot 0 ( VCC ) + No 5V */ + status = 4; + *pcmcia_bcsr = status; + + status |= BCSR_PCMCIA_PC0DRVEN; + *pcmcia_bcsr = status; + au_sync(); + + udelay(300*1000); + + status |= BCSR_PCMCIA_PC0RST; + *pcmcia_bcsr = status; + au_sync(); + + udelay(100*1000); + + /* PCMCIA is on a 36 bit physical address. + We need to map it into a 32 bit addresses */ + +#if 0 + /* We dont need theese unless we run whole pcmcia package */ + write_one_tlb(20, /* index */ + 0x01ffe000, /* Pagemask, 16 MB pages */ + CFG_PCMCIA_IO_BASE, /* Hi */ + 0x3C000017, /* Lo0 */ + 0x3C200017); /* Lo1 */ + + write_one_tlb(21, /* index */ + 0x01ffe000, /* Pagemask, 16 MB pages */ + CFG_PCMCIA_ATTR_BASE, /* Hi */ + 0x3D000017, /* Lo0 */ + 0x3D200017); /* Lo1 */ +#endif /* 0 */ + write_one_tlb(22, /* index */ + 0x01ffe000, /* Pagemask, 16 MB pages */ + CFG_PCMCIA_MEM_ADDR, /* Hi */ + 0x3E000017, /* Lo0 */ + 0x3E200017); /* Lo1 */ +#endif /* CONFIG_IDE_PCMCIA */ + + return 0; +} diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds new file mode 100644 index 0000000..a2d19a8 --- /dev/null +++ b/board/pb1x00/u-boot.lds @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/board/pcippc2/Makefile b/board/pcippc2/Makefile new file mode 100644 index 0000000..2998f23 --- /dev/null +++ b/board/pcippc2/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \ + fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o + +AOBJS = + +OBJS = $(COBJS) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/pcippc2/config.mk b/board/pcippc2/config.mk new file mode 100644 index 0000000..92d37c9 --- /dev/null +++ b/board/pcippc2/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# PCIPPC-2 boards +# + +TEXT_BASE = 0xfff00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/pcippc2/cpc710.h b/board/pcippc2/cpc710.h new file mode 100644 index 0000000..8167270 --- /dev/null +++ b/board/pcippc2/cpc710.h @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CPC710_H_ +#define _CPC710_H_ + +/* Revision */ +#define CPC710_TYPE_100 0x80 +#define CPC710_TYPE_100P 0x90 + +/* System control area */ +#define HW_PHYS_SCA 0xff000000 + +#define HW_SCA_CPC0 0x000000 +#define HW_SCA_SDRAM0 0x000000 +#define HW_SCA_DMA0 0x1C0000 + +#define HW_PHYS_CPC0 (HW_PHYS_SCA + HW_SCA_CPC0) +#define HW_PHYS_SDRAM0 (HW_PHYS_SCA + HW_SCA_SDRAM0) + +#define HW_CPC0_PCICNFR 0x000c +#define HW_CPC0_RSTR 0x0010 +#define HW_CPC0_SPOR 0x00e8 +#define HW_CPC0_UCTL 0x1000 +#define HW_CPC0_SIOC0 0x1020 +#define HW_CPC0_ABCNTL 0x1030 +#define HW_CPC0_SESR 0x1060 +#define HW_CPC0_SEAR 0x1070 +#define HW_CPC0_PGCHP 0x1100 +#define HW_CPC0_RGBAN0 0x1110 +#define HW_CPC0_RGBAN1 0x1120 + +#define HW_CPC0_GPDIR 0x1130 +#define HW_CPC0_GPIN 0x1140 +#define HW_CPC0_GPOUT 0x1150 + +#define HW_CPC0_ATAS 0x1160 + +#define HW_CPC0_PCIBAR 0x200018 +#define HW_CPC0_PCIENB 0x201000 + +#define HW_SDRAM0_MCCR 0x1200 +#define HW_SDRAM0_MESR 0x1220 +#define HW_SDRAM0_MEAR 0x1230 + +#define HW_SDRAM0_MCER0 0x1300 +#define HW_SDRAM0_MCER1 0x1310 +#define HW_SDRAM0_MCER2 0x1320 +#define HW_SDRAM0_MCER3 0x1330 +#define HW_SDRAM0_MCER4 0x1340 +#define HW_SDRAM0_MCER5 0x1350 +#define HW_SDRAM0_MCER6 0x1360 +#define HW_SDRAM0_MCER7 0x1370 + +#define HW_BRIDGE_PCIDG 0xf6120 +#define HW_BRIDGE_INTACK 0xf7700 +#define HW_BRIDGE_PIBAR 0xf7800 +#define HW_BRIDGE_PMBAR 0xf7810 +#define HW_BRIDGE_CRR 0xf7ef0 +#define HW_BRIDGE_PR 0xf7f20 +#define HW_BRIDGE_ACR 0xf7f30 +#define HW_BRIDGE_MSIZE 0xf7f40 +#define HW_BRIDGE_IOSIZE 0xf7f60 +#define HW_BRIDGE_SMBAR 0xf7f80 +#define HW_BRIDGE_SIBAR 0xf7fc0 +#define HW_BRIDGE_CFGADDR 0xf8000 +#define HW_BRIDGE_CFGDATA 0xf8010 +#define HW_BRIDGE_PSSIZE 0xf8100 +#define HW_BRIDGE_BARPS 0xf8120 +#define HW_BRIDGE_PSBAR 0xf8140 + +/* Configuration space registers */ +#define CPC710_BUS_NUMBER 0x40 +#define CPC710_SUB_BUS_NUMBER 0x41 + +#endif diff --git a/board/pcippc2/cpc710_init_ram.c b/board/pcippc2/cpc710_init_ram.c new file mode 100644 index 0000000..57ed8f0 --- /dev/null +++ b/board/pcippc2/cpc710_init_ram.c @@ -0,0 +1,254 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "pcippc2.h" +#include "i2c.h" + +typedef struct cpc710_mem_org_s +{ + u8 rows; + u8 cols; + u8 banks2; + u8 org; +} cpc710_mem_org_t; + +static int cpc710_compute_mcer (u32 * mcer, + unsigned long * + size, + unsigned int sdram); +static int cpc710_eeprom_checksum (unsigned int sdram); +static u8 cpc710_eeprom_read (unsigned int sdram, + unsigned int offset); + +static u32 cpc710_mcer_mem [] = +{ + 0x000003f3, /* 18 lines, 4 Mb */ + 0x000003e3, /* 19 lines, 8 Mb */ + 0x000003c3, /* 20 lines, 16 Mb */ + 0x00000383, /* 21 lines, 32 Mb */ + 0x00000303, /* 22 lines, 64 Mb */ + 0x00000203, /* 23 lines, 128 Mb */ + 0x00000003, /* 24 lines, 256 Mb */ + 0x00000002, /* 25 lines, 512 Mb */ + 0x00000001 /* 26 lines, 1024 Mb */ +}; +static cpc710_mem_org_t cpc710_mem_org [] = +{ + { 0x0c, 0x09, 0x02, 0x00 }, /* 0000: 12/ 9/2 */ + { 0x0d, 0x09, 0x02, 0x00 }, /* 0000: 13/ 9/2 */ + { 0x0d, 0x0a, 0x02, 0x00 }, /* 0000: 13/10/2 */ + { 0x0d, 0x0b, 0x02, 0x00 }, /* 0000: 13/11/2 */ + { 0x0d, 0x0c, 0x02, 0x00 }, /* 0000: 13/12/2 */ + { 0x0e, 0x0c, 0x02, 0x00 }, /* 0000: 14/12/2 */ + { 0x0b, 0x08, 0x02, 0x01 }, /* 0001: 11/ 8/2 */ + { 0x0b, 0x09, 0x01, 0x02 }, /* 0010: 11/ 9/1 */ + { 0x0b, 0x0a, 0x01, 0x03 }, /* 0011: 11/10/1 */ + { 0x0c, 0x08, 0x02, 0x04 }, /* 0100: 12/ 8/2 */ + { 0x0c, 0x0a, 0x02, 0x05 }, /* 0101: 12/10/2 */ + { 0x0d, 0x08, 0x01, 0x06 }, /* 0110: 13/ 8/1 */ + { 0x0d, 0x08, 0x02, 0x07 }, /* 0111: 13/ 8/2 */ + { 0x0d, 0x09, 0x01, 0x08 }, /* 1000: 13/ 9/1 */ + { 0x0d, 0x0a, 0x01, 0x09 }, /* 1001: 13/10/1 */ + { 0x0b, 0x08, 0x01, 0x0a }, /* 1010: 11/ 8/1 */ + { 0x0c, 0x08, 0x01, 0x0b }, /* 1011: 12/ 8/1 */ + { 0x0c, 0x09, 0x01, 0x0c }, /* 1100: 12/ 9/1 */ + { 0x0e, 0x09, 0x02, 0x0d }, /* 1101: 14/ 9/2 */ + { 0x0e, 0x0a, 0x02, 0x0e }, /* 1110: 14/10/2 */ + { 0x0e, 0x0b, 0x02, 0x0f } /* 1111: 14/11/2 */ +}; + +unsigned long cpc710_ram_init (void) +{ + unsigned long memsize = 0; + unsigned long bank_size; + u32 mcer; + +#ifndef CFG_RAMBOOT + /* Clear memory banks + */ + out32(REG(SDRAM0, MCER0), 0); + out32(REG(SDRAM0, MCER1), 0); + out32(REG(SDRAM0, MCER2), 0); + out32(REG(SDRAM0, MCER3), 0); + out32(REG(SDRAM0, MCER4), 0); + out32(REG(SDRAM0, MCER5), 0); + out32(REG(SDRAM0, MCER6), 0); + out32(REG(SDRAM0, MCER7), 0); + iobarrier_rw(); + + /* Disable memory + */ + out32(REG(SDRAM0,MCCR), 0x13b06000); + iobarrier_rw(); +#endif + + /* Only the first memory bank is initialised now + */ + if (! cpc710_compute_mcer(& mcer, & bank_size, 0)) + { + puts("Unsupported SDRAM type !\n"); + hang(); + } + memsize += bank_size; +#ifndef CFG_RAMBOOT + /* Enable bank, zero start + */ + out32(REG(SDRAM0, MCER0), mcer | 0x80000000); + iobarrier_rw(); +#endif + +#ifndef CFG_RAMBOOT + /* Enable memory + */ + out32(REG(SDRAM0, MCCR), in32(REG(SDRAM0, MCCR)) | 0x80000000); + + /* Wait until initialisation finished + */ + while (! (in32 (REG(SDRAM0, MCCR)) & 0x20000000)) + { + iobarrier_rw(); + } + + /* Clear Memory Error Status and Address registers + */ + out32(REG(SDRAM0, MESR), 0); + out32(REG(SDRAM0, MEAR), 0); + iobarrier_rw(); + + /* ECC is not configured now + */ +#endif + + /* Memory size counter + */ + out32(REG(CPC0, RGBAN1), memsize); + + return memsize; +} + +static int cpc710_compute_mcer ( + u32 * mcer, + unsigned long * size, + unsigned int sdram) +{ + u8 rows; + u8 cols; + u8 banks2; + unsigned int lines; + u32 mc = 0; + unsigned int i; + cpc710_mem_org_t * org = 0; + + + if (! i2c_reset()) + { + puts("Can't reset I2C!\n"); + hang(); + } + + if (! cpc710_eeprom_checksum(sdram)) + { + puts("Invalid EEPROM checksum !\n"); + hang(); + } + + rows = cpc710_eeprom_read(sdram, 3); + cols = cpc710_eeprom_read(sdram, 4); + /* Can be 2 or 4 banks; divide by 2 + */ + banks2 = cpc710_eeprom_read(sdram, 17) / 2; + + lines = rows + cols + banks2; + + if (lines < 18 || lines > 26) + { + /* Unsupported configuration + */ + return 0; + } + + + mc |= cpc710_mcer_mem [lines - 18] << 6; + + for (i = 0; i < sizeof(cpc710_mem_org) / sizeof(cpc710_mem_org_t); i++) + { + cpc710_mem_org_t * corg = cpc710_mem_org + i; + + if (corg->rows == rows && corg->cols == cols && corg->banks2 == banks2) + { + org = corg; + + break; + } + } + + if (! org) + { + /* Unsupported configuration + */ + return 0; + } + + mc |= (u32) org->org << 2; + + /* Supported configuration + */ + *mcer = mc; + *size = 1l << (lines + 4); + + return 1; +} + +static int cpc710_eeprom_checksum ( + unsigned int sdram) +{ + u8 sum = 0; + unsigned int i; + + for (i = 0; i < 63; i++) + { + sum += cpc710_eeprom_read(sdram, i); + } + + return sum == cpc710_eeprom_read(sdram, 63); +} + +static u8 cpc710_eeprom_read ( + unsigned int sdram, + unsigned int offset) +{ + u8 dev = (sdram << 1) | 0xa0; + u8 data; + + if (! i2c_read_byte(& data, dev,offset)) + { + puts("I2C error !\n"); + hang(); + } + + return data; +} diff --git a/board/pcippc2/cpc710_pci.c b/board/pcippc2/cpc710_pci.c new file mode 100644 index 0000000..bed8aea --- /dev/null +++ b/board/pcippc2/cpc710_pci.c @@ -0,0 +1,309 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include "hardware.h" +#include "pcippc2.h" + +struct pci_controller local_hose, cpci_hose; + +static u32 cpc710_mapped_ram; + + /* Enable PCI retry timeouts + */ +void cpc710_pci_enable_timeout (void) +{ + out32(BRIDGE(LOCAL, CFGADDR), 0x50000080); + iobarrier_rw(); + out32(BRIDGE(LOCAL, CFGDATA), 0x32000000); + iobarrier_rw(); + + out32(BRIDGE(CPCI, CFGADDR), 0x50000180); + iobarrier_rw(); + out32(BRIDGE(CPCI, CFGDATA), 0x32000000); + iobarrier_rw(); +} + +void cpc710_pci_init (void) +{ + u32 sdram_size = pcippc2_sdram_size(); + + cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ? + sdram_size : PCI_MEMORY_MAXSIZE; + + /* Select the local PCI + */ + out32(REG(CPC0, PCICNFR), 0x80000002); + iobarrier_rw(); + + out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS); + iobarrier_rw(); + + /* Enable PCI bridge address decoding + */ + out32(REG(CPC0, PCIENB), 0x80000000); + iobarrier_rw(); + + /* Select the CPCI bridge + */ + out32(REG(CPC0, PCICNFR), 0x80000003); + iobarrier_rw(); + + out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS); + iobarrier_rw(); + + /* Enable PCI bridge address decoding + */ + out32(REG(CPC0, PCIENB), 0x80000000); + iobarrier_rw(); + + /* Disable configuration accesses + */ + out32(REG(CPC0, PCICNFR), 0x80000000); + iobarrier_rw(); + + /* Initialise the local PCI + */ + out32(BRIDGE(LOCAL, CRR), 0x7c000000); + iobarrier_rw(); + out32(BRIDGE(LOCAL, PCIDG), 0x40000000); + iobarrier_rw(); + out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS); + out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS); + out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE); + iobarrier_rw(); + out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS); + out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS); + out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE); + iobarrier_rw(); + out32(BRIDGE(LOCAL, PR), 0x00ffe000); + iobarrier_rw(); + out32(BRIDGE(LOCAL, ACR), 0xfe000000); + iobarrier_rw(); + out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24); + out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24); + out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24)); + iobarrier_rw(); + + /* Initialise the CPCI bridge + */ + out32(BRIDGE(CPCI, CRR), 0x7c000000); + iobarrier_rw(); + out32(BRIDGE(CPCI, PCIDG), 0xC0000000); + iobarrier_rw(); + out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS); + out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS); + out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE); + iobarrier_rw(); + out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS); + out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS); + out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE); + iobarrier_rw(); + out32(BRIDGE(CPCI, PR), 0x80ffe000); + iobarrier_rw(); + out32(BRIDGE(CPCI, ACR), 0xdf000000); + iobarrier_rw(); + out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24); + out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24); + out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24)); + iobarrier_rw(); + + /* Local PCI + */ + + out32(BRIDGE(LOCAL, CFGADDR), 0x04000080); + iobarrier_rw(); + out32(BRIDGE(LOCAL, CFGDATA), 0x56010000); + iobarrier_rw(); + + out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080); + iobarrier_rw(); + out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); + iobarrier_rw(); + + /* Set bus and subbus numbers + */ + out32(BRIDGE(LOCAL, CFGADDR), 0x40000080); + iobarrier_rw(); + out32(BRIDGE(LOCAL, CFGDATA), 0x00000000); + iobarrier_rw(); + + out32(BRIDGE(LOCAL, CFGADDR), 0x50000080); + iobarrier_rw(); + /* PCI retry timeouts will be enabled later + */ + out32(BRIDGE(LOCAL, CFGDATA), 0x00000000); + iobarrier_rw(); + + /* CPCI + */ + + /* Set bus and subbus numbers + */ + out32(BRIDGE(CPCI, CFGADDR), 0x40000080); + iobarrier_rw(); + out32(BRIDGE(CPCI, CFGDATA), 0x01010000); + iobarrier_rw(); + + out32(BRIDGE(CPCI, CFGADDR), 0x04000180); + iobarrier_rw(); + out32(BRIDGE(CPCI, CFGDATA), 0x56010000); + iobarrier_rw(); + + out32(BRIDGE(CPCI, CFGADDR), 0x0c000180); + iobarrier_rw(); + out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); + iobarrier_rw(); + + /* Write to the PSBAR */ + out32(BRIDGE(CPCI, CFGADDR), 0x10000180); + iobarrier_rw(); + out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS)); + iobarrier_rw(); + + /* Set bus and subbus numbers + */ + out32(BRIDGE(CPCI, CFGADDR), 0x40000180); + iobarrier_rw(); + out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000); + iobarrier_rw(); + + out32(BRIDGE(CPCI, CFGADDR), 0x50000180); + iobarrier_rw(); + out32(BRIDGE(CPCI, CFGDATA), 0x32000000); + /* PCI retry timeouts will be enabled later + */ + out32(BRIDGE(CPCI, CFGDATA), 0x00000000); + iobarrier_rw(); + + /* Remove reset on the PCI buses + */ + out32(BRIDGE(LOCAL, CRR), 0xfc000000); + iobarrier_rw(); + out32(BRIDGE(CPCI, CRR), 0xfc000000); + iobarrier_rw(); + + local_hose.first_busno = 0; + local_hose.last_busno = 0xff; + + /* System memory space */ + pci_set_region(local_hose.regions + 0, + PCI_MEMORY_BUS, + PCI_MEMORY_PHYS, + PCI_MEMORY_MAXSIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(local_hose.regions + 1, + BRIDGE_LOCAL_MEM_BUS, + BRIDGE_LOCAL_MEM_PHYS, + BRIDGE_LOCAL_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(local_hose.regions + 2, + BRIDGE_LOCAL_IO_BUS, + BRIDGE_LOCAL_IO_PHYS, + BRIDGE_LOCAL_IO_SIZE, + PCI_REGION_IO); + + local_hose.region_count = 3; + + pci_setup_indirect(&local_hose, + BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR, + BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA); + + pci_register_hose(&local_hose); + + /* Initialize PCI32 bus registers */ + pci_hose_write_config_byte(&local_hose, + PCI_BDF(local_hose.first_busno,0,0), + CPC710_BUS_NUMBER, + local_hose.first_busno); + pci_hose_write_config_byte(&local_hose, + PCI_BDF(local_hose.first_busno,0,0), + CPC710_SUB_BUS_NUMBER, + local_hose.last_busno); + + local_hose.last_busno = pci_hose_scan(&local_hose); + + /* Write out correct max subordinate bus number for local hose */ + pci_hose_write_config_byte(&local_hose, + PCI_BDF(local_hose.first_busno,0,0), + CPC710_SUB_BUS_NUMBER, + local_hose.last_busno); + + cpci_hose.first_busno = local_hose.last_busno + 1; + cpci_hose.last_busno = 0xff; + + /* System memory space */ + pci_set_region(cpci_hose.regions + 0, + PCI_MEMORY_BUS, + PCI_MEMORY_PHYS, + PCI_MEMORY_MAXSIZE, + PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(cpci_hose.regions + 1, + BRIDGE_CPCI_MEM_BUS, + BRIDGE_CPCI_MEM_PHYS, + BRIDGE_CPCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(cpci_hose.regions + 2, + BRIDGE_CPCI_IO_BUS, + BRIDGE_CPCI_IO_PHYS, + BRIDGE_CPCI_IO_SIZE, + PCI_REGION_IO); + + cpci_hose.region_count = 3; + + pci_setup_indirect(&cpci_hose, + BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR, + BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA); + + pci_register_hose(&cpci_hose); + + /* Initialize PCI64 bus registers */ + pci_hose_write_config_byte(&cpci_hose, + PCI_BDF(cpci_hose.first_busno,0,0), + CPC710_BUS_NUMBER, + cpci_hose.first_busno); + pci_hose_write_config_byte(&cpci_hose, + PCI_BDF(cpci_hose.first_busno,0,0), + CPC710_SUB_BUS_NUMBER, + cpci_hose.last_busno); + + cpci_hose.last_busno = pci_hose_scan(&cpci_hose); + + /* Write out correct max subordinate bus number for cpci hose */ + pci_hose_write_config_byte(&cpci_hose, + PCI_BDF(cpci_hose.first_busno,0,0), + CPC710_SUB_BUS_NUMBER, + cpci_hose.last_busno); +} diff --git a/board/pcippc2/cpc710_pci.h b/board/pcippc2/cpc710_pci.h new file mode 100644 index 0000000..24d0db6 --- /dev/null +++ b/board/pcippc2/cpc710_pci.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CPC710_PCI_H_ +#define _CPC710_PCI_H_ + +#define PCI_MEMORY_PHYS 0x00000000 +#define PCI_MEMORY_BUS 0x80000000 +#define PCI_MEMORY_MAXSIZE 0x20000000 + +#define BRIDGE_CPCI_PHYS 0xff500000 +#define BRIDGE_CPCI_MEM_SIZE 0x08000000 +#define BRIDGE_CPCI_MEM_PHYS 0xf0000000 +#define BRIDGE_CPCI_MEM_BUS 0x00000000 +#define BRIDGE_CPCI_IO_SIZE 0x02000000 +#define BRIDGE_CPCI_IO_PHYS 0xfc000000 +#define BRIDGE_CPCI_IO_BUS 0x00000000 + +#define BRIDGE_LOCAL_PHYS 0xff400000 +#define BRIDGE_LOCAL_MEM_SIZE 0x04000000 +#define BRIDGE_LOCAL_MEM_PHYS 0xf8000000 +#define BRIDGE_LOCAL_MEM_BUS 0x40000000 +#define BRIDGE_LOCAL_IO_SIZE 0x01000000 +#define BRIDGE_LOCAL_IO_PHYS 0xfe000000 +#define BRIDGE_LOCAL_IO_BUS 0x04000000 + +#define BRIDGE(r, x) (BRIDGE_##r##_PHYS + HW_BRIDGE_##x) + +#define PCI_LATENCY_TIMER_VAL 0xff + +#endif diff --git a/board/pcippc2/flash.c b/board/pcippc2/flash.c new file mode 100644 index 0000000..8c01415 --- /dev/null +++ b/board/pcippc2/flash.c @@ -0,0 +1,573 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static ulong flash_get_size (ulong addr, flash_info_t *info); +static int flash_get_offsets (ulong base, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_reset (ulong addr); + +unsigned long flash_init (void) +{ + unsigned int i; + unsigned long flash_size = 0; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE && \ + CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + } else { + puts ("Warning: the BOOT Flash is not initialised !"); + } + + return flash_size; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (ulong addr, flash_info_t *info) +{ + short i; + uchar value; + + /* Write auto select command: read Manufacturer ID */ + out8(addr + 0x0555, 0xAA); + iobarrier_rw(); + out8(addr + 0x02AA, 0x55); + iobarrier_rw(); + out8(addr + 0x0555, 0x90); + iobarrier_rw(); + + value = in8(addr); + iobarrier_rw(); + + DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); + + switch (value | (value << 16)) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + + case STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + flash_reset (addr); + return 0; + } + + value = in8(addr + 1); /* device ID */ + iobarrier_rw(); + + DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value); + + switch ((ulong)value) { + case AMD_ID_F040B: + DEBUGF("Am29F040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + + case AMD_ID_LV040B: + DEBUGF("Am29LV040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + + case AMD_ID_LV400T: + DEBUGF("Am29LV400T\n"); + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + DEBUGF("Am29LV400B\n"); + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + DEBUGF("Am29LV800T\n"); + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + DEBUGF("Am29LV400B\n"); + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + DEBUGF("Am29LV160T\n"); + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + DEBUGF("Am29LV160B\n"); + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV320T: + DEBUGF("Am29LV320T\n"); + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + +#if 0 + /* Has the same ID as AMD_ID_LV320T, to be fixed */ + case AMD_ID_LV320B: + DEBUGF("Am29LV320B\n"); + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + + case AMD_ID_LV033C: + DEBUGF("Am29LV033C\n"); + info->flash_id += FLASH_AM033C; + info->sector_count = 64; + info->size = 0x01000000; + break; /* => 16Mb */ + + case STM_ID_F040B: + DEBUGF("M29F040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + + default: + info->flash_id = FLASH_UNKNOWN; + flash_reset (addr); + return (0); /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + if (! flash_get_offsets (addr, info)) { + flash_reset (addr); + return 0; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + value = in8(info->start[i] + 2); + iobarrier_rw(); + info->protect[i] = (value & 1) != 0; + } + + /* + * Reset bank to read mode + */ + flash_reset (addr); + + return (info->size); +} + +static int flash_get_offsets (ulong base, flash_info_t *info) +{ + unsigned int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + /* set sector offsets for uniform sector type */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + i * info->size / + info->sector_count; + } + break; + default: + return 0; + } + + return 1; +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile ulong addr = info->start[0]; + int flag, prot, sect, l_sect; + ulong start, now, last; + + if (s_first < 0 || s_first > s_last) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + out8(addr + 0x555, 0x80); + iobarrier_rw(); + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = info->start[sect]; + out8(addr, 0x30); + iobarrier_rw(); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = info->start[l_sect]; + + DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT); + + while ((in8(addr) & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + flash_reset (info->start[0]); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + iobarrier_rw(); + } + +DONE: + /* reset to read mode */ + flash_reset (info->start[0]); + + printf (" done\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/* + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile ulong addr = info->start[0]; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((in32(dest) & data) != data) { + return (2); + } + + /* write each byte out */ + for (i = 0; i < 4; i++) { + char *data_ch = (char *)&data; + int flag = disable_interrupts(); + + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + out8(addr + 0x555, 0xA0); + iobarrier_rw(); + out8(dest+i, data_ch[i]); + iobarrier_rw(); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flash_reset (addr); + return (1); + } + iobarrier_rw(); + } + } + + flash_reset (addr); + return (0); +} + +/* + * Reset bank to read mode + */ +static void flash_reset (ulong addr) +{ + out8(addr, 0xF0); /* reset bank */ + iobarrier_rw(); +} + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_STM: printf ("SGS THOMSON "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size % 0x100000 == 0) { + printf (" Size: %ld MB in %d Sectors\n", + info->size / 0x100000, info->sector_count); + } else if (info->size % 0x400 == 0) { + printf (" Size: %ld KB in %d Sectors\n", + info->size / 0x400, info->sector_count); + } else { + printf (" Size: %ld B in %d Sectors\n", + info->size, info->sector_count); + } + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} diff --git a/board/pcippc2/fpga_serial.c b/board/pcippc2/fpga_serial.c new file mode 100644 index 0000000..579bfc7 --- /dev/null +++ b/board/pcippc2/fpga_serial.c @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "fpga_serial.h" +#include "hardware.h" +#include "pcippc2.h" + + /* 8 data, 1 stop, no parity + */ +#define LCRVAL 0x03 + /* RTS/DTR + */ +#define MCRVAL 0x03 + /* Clear & enable FIFOs + */ +#define FCRVAL 0x07 + +static void fpga_serial_wait (void); +static void fpga_serial_print (char c); + +void fpga_serial_init (int baudrate) +{ + int clock_divisor = 115200 / baudrate; + + out8 (FPGA (INT, SERIAL_CONFIG), 0x24); + iobarrier_rw (); + + fpga_serial_wait (); + + out8 (UART (IER), 0); + out8 (UART (LCR), LCRVAL | 0x80); + iobarrier_rw (); + out8 (UART (DLL), clock_divisor & 0xff); + out8 (UART (DLM), clock_divisor >> 8); + iobarrier_rw (); + out8 (UART (LCR), LCRVAL); + iobarrier_rw (); + out8 (UART (MCR), MCRVAL); + out8 (UART (FCR), FCRVAL); + iobarrier_rw (); +} + +void fpga_serial_putc (char c) +{ + if (c) { + fpga_serial_print (c); + } +} + +void fpga_serial_puts (const char *s) +{ + while (*s) { + fpga_serial_print (*s++); + } +} + +int fpga_serial_getc (void) +{ + while ((in8 (UART (LSR)) & 0x01) == 0); + + return in8 (UART (RBR)); +} + +int fpga_serial_tstc (void) +{ + return (in8 (UART (LSR)) & 0x01) != 0; +} + +void fpga_serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = 115200 / gd->baudrate; + + fpga_serial_wait (); + + out8 (UART (LCR), LCRVAL | 0x80); + iobarrier_rw (); + out8 (UART (DLL), clock_divisor & 0xff); + out8 (UART (DLM), clock_divisor >> 8); + iobarrier_rw (); + out8 (UART (LCR), LCRVAL); + iobarrier_rw (); +} + +static void fpga_serial_wait (void) +{ + while ((in8 (UART (LSR)) & 0x40) == 0); +} + +static void fpga_serial_print (char c) +{ + if (c == '\n') { + while ((in8 (UART (LSR)) & 0x20) == 0); + + out8 (UART (THR), '\r'); + iobarrier_rw (); + } + + while ((in8 (UART (LSR)) & 0x20) == 0); + + out8 (UART (THR), c); + iobarrier_rw (); + + if (c == '\n') { + fpga_serial_wait (); + } +} diff --git a/board/pcippc2/fpga_serial.h b/board/pcippc2/fpga_serial.h new file mode 100644 index 0000000..92c9cdd --- /dev/null +++ b/board/pcippc2/fpga_serial.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FPGA_SERIAL_H_ +#define _FPGA_SERIAL_H_ + +extern void fpga_serial_init (int); +extern void fpga_serial_putc (char); +extern void fpga_serial_puts (const char *); +extern int fpga_serial_getc (void); +extern int fpga_serial_tstc (void); +extern void fpga_serial_setbrg (void); + +#endif diff --git a/board/pcippc2/hardware.h b/board/pcippc2/hardware.h new file mode 100644 index 0000000..489929d --- /dev/null +++ b/board/pcippc2/hardware.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _HARDWARE_H_ +#define _HARDWARE_H_ + +#include "cpc710.h" +#include "cpc710_pci.h" +#include "pcippc2_fpga.h" +#include "ns16550.h" + +#define REG(r, x) (HW_PHYS_##r + HW_##r##_##x) + + /* Address map: + * + * 0x00000000-0x20000000 SDRAM + * 0x40000000-0x00008000 Init RAM in the CPU DCache + * 0xf0000000-0xf8000000 CPCI MEM + * 0xf8000000-0xfc000000 Local PCI MEM + * 0xfc000000-0xfe000000 CPCI I/O + * 0xfe000000-0xff000000 Local PCI I/O + * 0xff000000-0xff201000 System configuration space + * 0xff400000-0xff500000 Local PCI bridge space + * 0xff500000-0xff600000 CPCI bridge space + * 0xfff00000-0xfff80000 Boot Flash + */ + +#endif diff --git a/board/pcippc2/i2c.c b/board/pcippc2/i2c.c new file mode 100644 index 0000000..36b1d0f --- /dev/null +++ b/board/pcippc2/i2c.c @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "hardware.h" +#include "i2c.h" + +static void i2c_start (void); +static void i2c_stop (void); +static int i2c_write (u8 data); +static void i2c_read (u8 * data); + +static inline void i2c_port_start (void); +static inline void i2c_clock (unsigned int val); +static inline void i2c_data (unsigned int val); +static inline unsigned int + i2c_in (void); +static inline void i2c_write_bit (unsigned int val); +static inline unsigned int + i2c_read_bit (void); + +static inline void i2c_udelay (unsigned int time); + +int i2c_read_byte ( + u8 * data, + u8 dev, + u8 offset) +{ + int err = 0; + + i2c_start(); + + err = ! i2c_write(dev); + + if (! err) + { + err = ! i2c_write(offset); + } + + if (! err) + { + i2c_start(); + } + + if (! err) + { + err = ! i2c_write(dev | 0x01); + } + + if (! err) + { + i2c_read(data); + } + + i2c_stop(); + + return ! err; +} + +static inline void i2c_udelay ( + unsigned int time) +{ + int v; + + asm volatile("mtdec %0" : : "r" (time * ((CFG_BUS_CLK / 4) / 1000000))); + + do + { + asm volatile("isync; mfdec %0" : "=r" (v)); + } while (v >= 0); +} + + /* Low-level hardware access + */ + +#define BIT_GPDATA 0x80000000 +#define BIT_GPCLK 0x40000000 + +static inline void i2c_port_start (void) +{ + out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~(BIT_GPCLK | BIT_GPDATA)); + out32(REG(CPC0, GPOUT), in32(REG(CPC0, GPOUT)) & ~(BIT_GPCLK | BIT_GPDATA)); + iobarrier_rw(); + + i2c_udelay(1); +} + +static inline void i2c_clock ( + unsigned int val) +{ + if (val) + { + out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPCLK); + } + else + { + out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPCLK); + } + + iobarrier_rw(); + + i2c_udelay(1); +} + +static inline void i2c_data ( + unsigned int val) +{ + if (val) + { + out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPDATA); + } + else + { + out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPDATA); + } + + iobarrier_rw(); + + i2c_udelay(1); +} + +static inline unsigned int i2c_in (void) +{ + unsigned int val = ((in32(REG(CPC0, GPIN)) & BIT_GPDATA) != 0)?1:0; + + iobarrier_rw(); + + return val; +} + + + /* Protocol implementation + */ + +static inline void i2c_write_bit ( + unsigned int val) +{ + i2c_data(val); + i2c_udelay(10); + i2c_clock(1); + i2c_udelay(10); + i2c_clock(0); + i2c_udelay(10); +} + +static inline unsigned int i2c_read_bit (void) +{ + unsigned int val; + + i2c_data(1); + i2c_udelay(10); + + i2c_clock(1); + i2c_udelay(10); + + val = i2c_in(); + + i2c_clock(0); + i2c_udelay(10); + + return val; +} + +unsigned int i2c_reset (void) +{ + unsigned int val; + int i; + + i2c_port_start(); + + i=0; + do { + i2c_udelay(10); + i2c_clock(0); + i2c_udelay(10); + i2c_clock(1); + i2c_udelay(10); + val = i2c_in(); + i++; + } while ((i<9)&&(val==0)); + return (val); +} + + +static void i2c_start (void) +{ + i2c_data(1); + i2c_clock(1); + i2c_udelay(10); + i2c_data(0); + i2c_udelay(10); + i2c_clock(0); + i2c_udelay(10); +} + +static void i2c_stop (void) +{ + i2c_data(0); + i2c_udelay(10); + i2c_clock(1); + i2c_udelay(10); + i2c_data(1); + i2c_udelay(10); +} + +static int i2c_write ( + u8 data) +{ + unsigned int i; + + for (i = 0; i < 8; i++) + { + i2c_write_bit(data >> 7); + data <<= 1; + } + + return i2c_read_bit() == 0; +} + +static void i2c_read ( + u8 * data) +{ + unsigned int i; + u8 val = 0; + + for (i = 0; i < 8; i++) + { + val <<= 1; + val |= i2c_read_bit(); + } + + *data = val; + i2c_write_bit(1); /* NoAck */ +} diff --git a/board/pcippc2/i2c.h b/board/pcippc2/i2c.h new file mode 100644 index 0000000..1224b42 --- /dev/null +++ b/board/pcippc2/i2c.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +#include + +extern int i2c_read_byte (u8 * data, + u8 dev, + u8 offset); + +extern unsigned int i2c_reset (void); + + +#endif diff --git a/board/pcippc2/ns16550.h b/board/pcippc2/ns16550.h new file mode 100644 index 0000000..7023f13 --- /dev/null +++ b/board/pcippc2/ns16550.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _NS16550_H_ +#define _NS16550_H_ + +#define NS16550_RBR 0x00 +#define NS16550_IER 0x01 +#define NS16550_FCR 0x02 +#define NS16550_LCR 0x03 +#define NS16550_MCR 0x04 +#define NS16550_LSR 0x05 +#define NS16550_MSR 0x06 +#define NS16550_SCR 0x07 + +#define NS16550_THR NS16550_RBR +#define NS16550_IIR NS16550_FCR +#define NS16550_DLL NS16550_RBR +#define NS16550_DLM NS16550_IER + +#endif diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c new file mode 100644 index 0000000..231b505 --- /dev/null +++ b/board/pcippc2/pcippc2.c @@ -0,0 +1,245 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "hardware.h" +#include "pcippc2.h" +#include "sconsole.h" +#include "fpga_serial.h" + +#if defined(CONFIG_WATCHDOG) + +static int pcippc2_wdt_init_done = 0; + +void pcippc2_wdt_init (void); + +#endif + + /* Check board identity + */ +int checkboard (void) +{ +#ifdef CONFIG_PCIPPC2 + puts ("Board: Gespac PCIPPC-2\n"); +#else + puts ("Board: Gespac PCIPPC-6\n"); +#endif + return 0; +} + + /* RAM size is stored in CPC0_RGBAN1 + */ +u32 pcippc2_sdram_size (void) +{ + return in32 (REG (CPC0, RGBAN1)); +} + +long initdram (int board_type) +{ + return cpc710_ram_init (); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + out32 (REG (CPC0, SPOR), 0); + iobarrier_rw (); + while (1); + /* notreached */ + return (-1); +} + +int board_early_init_f (void) +{ + out32 (REG (CPC0, RSTR), 0xC0000000); + iobarrier_rw (); + + out32 (REG (CPC0, RSTR), 0xF0000000); + iobarrier_rw (); + + out32 (REG (CPC0, UCTL), 0x00F80000); + + out32 (REG (CPC0, SIOC0), 0x30000000); + + out32 (REG (CPC0, ABCNTL), 0x00000000); + + out32 (REG (CPC0, SESR), 0x00000000); + out32 (REG (CPC0, SEAR), 0x00000000); + + /* Detect IBM Avignon CPC710 Revision */ + if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P) + out32 (REG (CPC0, PGCHP), 0xA0000040); + else + out32 (REG (CPC0, PGCHP), 0x80800040); + + + out32 (REG (CPC0, ATAS), 0x709C2508); + + iobarrier_rw (); + + return 0; +} + +void after_reloc (ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Jump to the main U-Boot board init code + */ + board_init_r ((gd_t *)gd, dest_addr); +} + +int misc_init_r (void) +{ + pcippc2_fpga_init (); + + pcippc2_cpci3264_init (); + +#if defined(CONFIG_WATCHDOG) + pcippc2_wdt_init (); +#endif + + fpga_serial_init (sconsole_get_baudrate ()); + + sconsole_putc = fpga_serial_putc; + sconsole_puts = fpga_serial_puts; + sconsole_getc = fpga_serial_getc; + sconsole_tstc = fpga_serial_tstc; + sconsole_setbrg = fpga_serial_setbrg; + + sconsole_flush (); + return (0); +} + +void pci_init_board (void) +{ + cpc710_pci_init (); + + /* FPGA requires no retry timeouts to be enabled + */ + cpc710_pci_enable_timeout (); +} + +void doc_init (void) +{ + doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC); +} + +void pcippc2_cpci3264_init (void) +{ + pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0); + + if (bdf == -1) + { + puts("Unable to find FPGA !\n"); + hang(); + } + + if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000) + /* 32-bits Compact PCI bus - LSB bit */ + { + iobarrier_rw(); + out32(BRIDGE(CPCI, PCIDG), 0x40000000); /* 32-bits bridge, Pipeline */ + iobarrier_rw(); + } +} + +#if defined(CONFIG_WATCHDOG) + +void pcippc2_wdt_init (void) +{ + out16r (FPGA (WDT, PROG), 0xffff); + out8 (FPGA (WDT, CTRL), 0x1); + + pcippc2_wdt_init_done = 1; +} + +void pcippc2_wdt_done (void) +{ + out8 (FPGA (WDT, CTRL), 0x0); + + pcippc2_wdt_init_done = 0; +} + +void pcippc2_wdt_reset (void) +{ + if (pcippc2_wdt_init_done == 1) + out8 (FPGA (WDT, REFRESH), 0x56); +} + +void watchdog_reset (void) +{ + int re_enable = disable_interrupts (); + + pcippc2_wdt_reset (); + if (re_enable) + enable_interrupts (); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + switch (argc) { + case 1: + printf ("Watchdog timer status is %s\n", + pcippc2_wdt_init_done == 1 ? "on" : "off"); + + return 0; + case 2: + if (!strcmp(argv[1],"on")) { + pcippc2_wdt_init(); + printf("Watchdog timer now is on\n"); + + return 0; + + } else if (!strcmp(argv[1],"off")) { + pcippc2_wdt_done(); + printf("Watchdog timer now is off\n"); + + return 0; + + } else + break; + default: + break; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + wd, 2, 1, do_wd, + "wd - check and set watchdog\n", + "on - switch watchDog on\n" + "wd off - switch watchdog off\n" + "wd - print current status\n" +); + +#endif /* CFG_CMD_BSP */ +#endif /* CONFIG_WATCHDOG */ diff --git a/board/pcippc2/pcippc2.h b/board/pcippc2/pcippc2.h new file mode 100644 index 0000000..3820bbe --- /dev/null +++ b/board/pcippc2/pcippc2.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PCIPPC2_H_ +#define _PCIPPC2_H_ + +#include +#include + +#include "hardware.h" + +#define FPGA(r, p) (pcippc2_fpga0_phys + HW_FPGA0_##r##_##p) +#define UART(r) (pcippc2_fpga0_phys + HW_FPGA0_UART1 + NS16550_##r * 4) +#define RTC(r) (pcippc2_fpga1_phys + HW_FPGA1_RTC + r) + +extern u32 pcippc2_fpga0_phys; +extern u32 pcippc2_fpga1_phys; + +extern u32 pcippc2_sdram_size (void); + +extern void pcippc2_fpga_init (void); + +extern void pcippc2_cpci3264_init (void); + +extern void cpc710_pci_init (void); +extern void cpc710_pci_enable_timeout (void); + +extern unsigned long + cpc710_ram_init (void); + +#endif diff --git a/board/pcippc2/pcippc2_fpga.c b/board/pcippc2/pcippc2_fpga.c new file mode 100644 index 0000000..7f6739d --- /dev/null +++ b/board/pcippc2/pcippc2_fpga.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "pci.h" + +#include "hardware.h" +#include "pcippc2.h" + +u32 pcippc2_fpga0_phys; +u32 pcippc2_fpga1_phys; + +void pcippc2_fpga_init (void) +{ + pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0); + unsigned int addr; + u16 cmd; + + if (bdf == -1) + { + puts("Unable to find FPGA !\n"); + hang(); + } + + pci_read_config_word(bdf, PCI_COMMAND, &cmd); + if ((cmd & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) != (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) + { + puts("FPGA is not configured !\n"); + hang(); + } + + pci_read_config_dword(bdf, PCI_BASE_ADDRESS_0, &addr); + if (addr & 0x1) + { + /* IO space + */ + pcippc2_fpga0_phys = pci_io_to_phys(bdf, addr & 0xfffffffc); + } + else + { + /* Memory space + */ + pcippc2_fpga0_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0); + } + + pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr); + if (addr & 0x1) + { + /* IO space + */ + pcippc2_fpga1_phys = pci_io_to_phys(bdf, addr & 0xfffffffc); + } + else + { + /* Memory space + */ + pcippc2_fpga1_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0); + } + + /* Interrupts are not used + */ + out32(FPGA(INT, INTR_MASK), 0xffffffff); + iobarrier_rw(); +} diff --git a/board/pcippc2/pcippc2_fpga.h b/board/pcippc2/pcippc2_fpga.h new file mode 100644 index 0000000..850c331 --- /dev/null +++ b/board/pcippc2/pcippc2_fpga.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PCIPPC2_FPGA_H_ +#define _PCIPPC2_FPGA_H_ + +#define FPGA_VENDOR_ID 0x1310 +#define FPGA_DEVICE_ID 0x000d + +#define HW_FPGA0_INT 0x0000 +#define HW_FPGA0_BOARD 0x0060 +#define HW_FPGA0_UART1 0x0080 +#define HW_FPGA0_UART2 0x0100 +#define HW_FPGA0_RTC 0x2000 +#define HW_FPGA0_DOC 0x4000 +#define HW_FPGA1_RTC 0x0000 +#define HW_FPGA1_DOC 0x4000 + +#define HW_FPGA0_INT_INTR_MASK 0x30 +#define HW_FPGA0_INT_INTR_STATUS 0x34 +#define HW_FPGA0_INT_INTR_EOI 0x40 +#define HW_FPGA0_INT_SERIAL_CONFIG 0x5c + +#define HW_FPGA0_WDT_CTRL 0x44 +#define HW_FPGA0_WDT_PROG 0x48 +#define HW_FPGA0_WDT_VAL 0x4c +#define HW_FPGA0_WDT_REFRESH 0x50 + +#endif diff --git a/board/pcippc2/sconsole.c b/board/pcippc2/sconsole.c new file mode 100644 index 0000000..a9f2b29 --- /dev/null +++ b/board/pcippc2/sconsole.c @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include "sconsole.h" + +void (*sconsole_putc) (char) = 0; +void (*sconsole_puts) (const char *) = 0; +int (*sconsole_getc) (void) = 0; +int (*sconsole_tstc) (void) = 0; +void (*sconsole_setbrg) (void) = 0; + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + + sb->pos = 0; + sb->size = 0; + sb->baud = gd->baudrate; + sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t); + + return (0); +} + +void serial_putc (char c) +{ + if (sconsole_putc) { + (*sconsole_putc) (c); + } else { + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + + if (c) { + sb->data[sb->pos++] = c; + if (sb->pos == sb->max_size) { + sb->pos = 0; + } + if (sb->size < sb->max_size) { + sb->size++; + } + } + } +} + +void serial_puts (const char *s) +{ + if (sconsole_puts) { + (*sconsole_puts) (s); + } else { + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + + while (*s) { + sb->data[sb->pos++] = *s++; + if (sb->pos == sb->max_size) { + sb->pos = 0; + } + if (sb->size < sb->max_size) { + sb->size++; + } + } + } +} + +int serial_getc (void) +{ + if (sconsole_getc) { + return (*sconsole_getc) (); + } else { + return 0; + } +} + +int serial_tstc (void) +{ + if (sconsole_tstc) { + return (*sconsole_tstc) (); + } else { + return 0; + } +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (sconsole_setbrg) { + (*sconsole_setbrg) (); + } else { + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + + sb->baud = gd->baudrate; + } +} + +int sconsole_get_baudrate (void) +{ + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + + return sb->baud; +} + +void sconsole_flush (void) +{ + if (sconsole_putc) { + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + unsigned int end = sb->pos < sb->size + ? sb->pos + sb->max_size - sb->size + : sb->pos - sb->size; + + while (sb->size) { + (*sconsole_putc) (sb->data[end++]); + if (end == sb->max_size) { + end = 0; + } + sb->size--; + } + } +} diff --git a/board/pcippc2/sconsole.h b/board/pcippc2/sconsole.h new file mode 100644 index 0000000..40fd75b --- /dev/null +++ b/board/pcippc2/sconsole.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SCONSOLE_H_ +#define _SCONSOLE_H_ + +#include + +typedef struct sconsole_buffer_s +{ + unsigned long size; + unsigned long max_size; + unsigned long pos; + unsigned long baud; + char data [1]; +} sconsole_buffer_t; + +#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR) + +extern void (* sconsole_putc) (char); +extern void (* sconsole_puts) (const char *); +extern int (* sconsole_getc) (void); +extern int (* sconsole_tstc) (void); +extern void (* sconsole_setbrg) (void); + +extern void sconsole_flush (void); +extern int sconsole_get_baudrate (void); + +#endif diff --git a/board/pcippc2/u-boot.lds b/board/pcippc2/u-boot.lds new file mode 100644 index 0000000..5c8cd5a --- /dev/null +++ b/board/pcippc2/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pleb2/Makefile b/board/pleb2/Makefile new file mode 100644 index 0000000..95d9170 --- /dev/null +++ b/board/pleb2/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := pleb2.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/pleb2/config.mk b/board/pleb2/config.mk new file mode 100644 index 0000000..6958a63 --- /dev/null +++ b/board/pleb2/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0xa1F80000 +#TEXT_BASE = 0xa3080000 +#TEXT_BASE = 0 diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c new file mode 100644 index 0000000..97271d9 --- /dev/null +++ b/board/pleb2/flash.c @@ -0,0 +1,814 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +/* environment.h defines the various CFG_ENV_... values in terms + * of whichever ones are given in the configuration file. + */ +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; + +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPWV * addr, flash_info_t * info); +static void flash_reset (flash_info_t * info); +static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data); +static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +#ifdef CFG_FLASH_PROTECTION +static void flash_sync_real_protect (flash_info_t * info); +#endif + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size_b; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + size_b = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size_b; + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n", + size_b); + } + + /* Do this again (was done already in flast_get_size), just + * in case we move it when remap the FLASH. + */ + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#ifdef CFG_FLASH_PROTECTION + /* read the hardware protection status (if any) into the + * protection array in flash_info. + */ + flash_sync_real_protect (&flash_info[0]); +#endif + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_ADDR + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + return (size_b); +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset (flash_info_t * info) +{ + FPWV *base = (FPWV *) (info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW) 0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL + && (info->flash_id & FLASH_BTYPE)) { + int bootsect_size; /* number of bytes/boot sector */ + int sect_size; /* number of bytes/regular sector */ + + bootsect_size = 0x00002000 * (sizeof (FPW) / 2); + sect_size = 0x00010000 * (sizeof (FPW) / 2); + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < 8; ++i) { + info->start[i] = base + (i * bootsect_size); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i - 7) * sect_size); + } + } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof (FPW) / 2); + + /* set up sector start address table (uniform sector type) */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * sect_size); + } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof (FPW) / 2); + + /* set up sector start address table (top boot sector type) */ + for (i = 0; i < info->sector_count - 3; i++) + info->start[i] = base + (i * sect_size); + i = info->sector_count - 1; + info->start[i--] = + base + (info->size - 0x00004000) * (sizeof (FPW) / 2); + info->start[i--] = + base + (info->size - 0x00006000) * (sizeof (FPW) / 2); + info->start[i--] = + base + (info->size - 0x00008000) * (sizeof (FPW) / 2); + } +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t * info) +{ + int i; + uchar *boottype; + uchar *bootletter; + uchar *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_BM: + printf ("BRIGHT MICRO "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_SST: + printf ("SST "); + break; + case FLASH_MAN_STM: + printf ("STM "); + break; + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM800T: + fmt = "29LV800B%s (8 Mbit, %s)\n"; + break; + case FLASH_AM640U: + fmt = "29LV641D (64 Mbit, uniform sectors)\n"; + break; + case FLASH_28F800C3B: + case FLASH_28F800C3T: + fmt = "28F800C3%s (8 Mbit, %s)\n"; + break; + case FLASH_INTEL800B: + case FLASH_INTEL800T: + fmt = "28F800B3%s (8 Mbit, %s)\n"; + break; + case FLASH_28F160C3B: + case FLASH_28F160C3T: + fmt = "28F160C3%s (16 Mbit, %s)\n"; + break; + case FLASH_INTEL160B: + case FLASH_INTEL160T: + fmt = "28F160B3%s (16 Mbit, %s)\n"; + break; + case FLASH_28F320C3B: + case FLASH_28F320C3T: + fmt = "28F320C3%s (32 Mbit, %s)\n"; + break; + case FLASH_INTEL320B: + case FLASH_INTEL320T: + fmt = "28F320B3%s (32 Mbit, %s)\n"; + break; + case FLASH_28F640C3B: + case FLASH_28F640C3T: + fmt = "28F640C3%s (64 Mbit, %s)\n"; + break; + case FLASH_INTEL640B: + case FLASH_INTEL640T: + fmt = "28F640B3%s (64 Mbit, %s)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV * addr, flash_info_t * info) +{ + /* Write auto select command: read Manufacturer ID */ + + /* Write auto select command sequence and test FLASH answer */ + addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ + addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ + addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + switch (addr[0] & 0xff) { + + case (uchar) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) + switch (addr[1]) { + + case (FPW) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000 * (sizeof (FPW) / 2); + break; /* => 1 or 2 MiB */ + + case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000 * (sizeof (FPW) / 2); + break; /* => 8 or 16 MB */ + + case (FPW) INTEL_ID_28F800C3B: + info->flash_id += FLASH_28F800C3B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof (FPW) / 2); + break; /* => 1 or 2 MB */ + + case (FPW) INTEL_ID_28F800B3B: + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof (FPW) / 2); + break; /* => 1 or 2 MB */ + + case (FPW) INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof (FPW) / 2); + break; /* => 2 or 4 MB */ + + case (FPW) INTEL_ID_28F160B3B: + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof (FPW) / 2); + break; /* => 2 or 4 MB */ + + case (FPW) INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof (FPW) / 2); + break; /* => 4 or 8 MB */ + + case (FPW) INTEL_ID_28F320B3B: + info->flash_id += FLASH_INTEL320B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof (FPW) / 2); + break; /* => 4 or 8 MB */ + + case (FPW) INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof (FPW) / 2); + break; /* => 8 or 16 MB */ + + case (FPW) INTEL_ID_28F640B3B: + info->flash_id += FLASH_INTEL640B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof (FPW) / 2); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets ((ulong) addr, info); + + /* Put FLASH back in read mode */ + flash_reset (info); + + return (info->size); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ + +static void flash_sync_real_protect (flash_info_t * info) +{ + FPWV *addr = (FPWV *) (info->start[0]); + FPWV *sect; + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F800C3B: + case FLASH_28F800C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + /* check for protected sectors */ + *addr = (FPW) 0x00900090; + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but mixed protected and unprotected devices + * within a sector should never happen. + */ + sect = (FPWV *) (info->start[i]); + info->protect[i] = + (sect[2] & (FPW) (0x00010001)) ? 1 : 0; + } + + /* Put FLASH back in read mode */ + flash_reset (info); + break; + + case FLASH_AM640U: + case FLASH_AM800T: + default: + /* no hardware protect that we support */ + break; + } +} +#endif + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_INTEL800B: + case FLASH_INTEL160B: + case FLASH_INTEL320B: + case FLASH_INTEL640B: + case FLASH_28F800C3B: + case FLASH_28F160C3B: + case FLASH_28F320C3B: + case FLASH_28F640C3B: + case FLASH_AM640U: + case FLASH_AM800T: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + reset_timer_masked (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + reset_timer_masked (); + last = 0; + + addr = (FPWV *) (info->start[sect]); + if (intel) { + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + } else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *) (info->start[0]); + base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW) 0x00550055; /* unlock */ + base[0x0555] = (FPW) 0x00800080; /* erase mode */ + base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW) 0x00550055; /* unlock */ + *addr = (FPW) 0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { + if ((now = + get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + } + + flash_reset (info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((now - last) > 1 * CFG_HZ) { /* every second */ + putc ('.'); + last = now; + } + } + + flash_reset (info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof (data), left -= sizeof (data) - bytes) { + + bytes = addr & (sizeof (data) - 1); + addr &= ~(sizeof (data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ +#ifdef CFG_LITTLE_ENDIAN + for (i = 0; i < sizeof (data); i++) { + data >>= 8; + if (i < bytes || i - bytes >= left) + data += (*((uchar *) addr + i)) << 24; + else + data += (*src++) << 24; + } +#else + for (i = 0; i < sizeof (data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left) + data += *((uchar *) addr + i); + else + data += *src++; + } +#endif + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd (info, (FPWV *) addr, data); + break; + case FLASH_MAN_INTEL: + res = write_word_intel (info, (FPWV *) addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) +{ + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *) (info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW) 0x00550055; /* unlock */ + base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + reset_timer_masked (); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW) 0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for Intel FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) +{ + int flag; + int res = 0; /* result, assume success */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *dest = (FPW) 0x00500050; /* clear status register */ + *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ + *dest = (FPW) 0x00400040; /* program setup */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + reset_timer_masked (); + + while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW) 0x00B000B0; /* Suspend program */ + res = 1; + } + } + + if (res == 0 && (*dest & (FPW) 0x00100010)) + res = 1; /* write failed, time out error is close enough */ + + *dest = (FPW) 0x00500050; /* clear status register */ + *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ + + return (res); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F800C3B: + case FLASH_28F800C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + flash_reset (info); /* make sure in read mode */ + *addr = (FPW) 0x00600060L; /* lock command setup */ + if (prot) + *addr = (FPW) 0x00010001L; /* lock sector */ + else + *addr = (FPW) 0x00D000D0L; /* unlock sector */ + flash_reset (info); /* reset to read mode */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) 0x00900090; + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) 0x00010001; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) 0x00010001) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect (info); + break; + + case FLASH_AM640U: + case FLASH_AM800T: + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif diff --git a/board/pleb2/lowlevel_init.S b/board/pleb2/lowlevel_init.S new file mode 100644 index 0000000..add2c53 --- /dev/null +++ b/board/pleb2/lowlevel_init.S @@ -0,0 +1,488 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + + /* Set up GPIO pins first */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + /* enable GPIO pins */ + ldr r0, =PSSR + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + +/********************************************************************* + Initlialize Memory Controller + + See PXA250 Operating System Developer's Guide + + pause for 200 uSecs- allow internal clocks to settle + *Note: only need this if hard reset... doing it anyway for now +*/ + + @ Step 1 + @ ---- Wait 200 usec + ldr r3, =OSCR @ reset the OS Timer Count to zero + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + @ get memory controller base address + ldr r1, =MEMC_BASE + +@**************************************************************************** +@ Step 2 +@ + + @ Step 2a + @ write msc0, read back to ensure data latches + @ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] + + @ write msc1 + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + @ write msc2 + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + +@ Step 2b + @ write mecr + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + + @ write mcmem0 + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + + @ write mcmem1 + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + + @ write mcatt0 + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + + @ write mcatt1 + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + + @ write mcio0 + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + + @ write mcio1 + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + +@ Step 2c + @ fly-by-dma is defeatured on this part + @ write flycnfg + @ldr r2, =CFG_FLYCNFG_VAL + @str r2, [r1, #FLYCNFG_OFFSET] + +/* FIXME Does this sequence really make sense */ +#ifdef REDBOOT_WAY + @ Step 2d + @ get the mdrefr settings + ldr r3, =CFG_MDREFR_VAL + + @ extract DRI field (we need a valid DRI field) + @ + ldr r2, =0xFFF + + @ valid DRI field in r3 + @ + and r3, r3, r2 + + @ get the reset state of MDREFR + @ + ldr r4, [r1, #MDREFR_OFFSET] + + @ clear the DRI field + @ + bic r4, r4, r2 + + @ insert the valid DRI field loaded above + @ + orr r4, r4, r3 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ *Note: preserve the mdrefr value in r4 * + +@**************************************************************************** +@ Step 3 +@ +@ NO SRAM + + mov pc, r10 + + +@**************************************************************************** +@ Step 4 +@ + + @ Assumes previous mdrefr value in r4, if not then read current mdrefr + + @ clear the free-running clock bits + @ (clear K0Free, K1Free, K2Free + @ + bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000) + + @ set K0RUN for CPLD clock + @ + orr r4, r4, #0x00002000 + + @ set K1RUN if bank 0 installed + @ + orr r4, r4, #0x00010000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + @ deassert SLFRSH + @ + bic r4, r4, #0x00400000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ assert E1PIN + @ + orr r4, r4, #0x00008000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + nop + nop +#else + @ Step 2d + @ get the mdrefr settings + ldr r3, =CFG_MDREFR_VAL + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ Step 4 + + @ set K0RUN for CPLD clock + @ + orr r4, r4, #0x00002000 + + @ set K1RUN for bank 0 + @ + orr r4, r4, #0x00010000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + @ deassert SLFRSH + @ + bic r4, r4, #0x00400000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ assert E1PIN + @ + orr r4, r4, #0x00008000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + nop + nop +#endif + + @ Step 4d + @ fetch platform value of mdcnfg + @ + ldr r2, =CFG_MDCNFG_VAL + + @ disable all sdram banks + @ + bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) + bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) + + @ program banks 0/1 for bus width + @ + bic r2, r2, #MDCNFG_DWID0 @0=32-bit + + @ write initial value of mdcnfg, w/o enabling sdram banks + @ + str r2, [r1, #MDCNFG_OFFSET] + + @ Step 4e + @ pause for 200 uSecs + @ + ldr r3, =OSCR @ reset the OS Timer Count to zero + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty + 1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + /* Why is this here??? */ + mov r0, #0x78 @turn everything off + mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.) + + @ Step 4f + @ Access memory *not yet enabled* for CBR refresh cycles (8) + @ - CBR is generated for all banks + + ldr r2, =CFG_DRAM_BASE + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + + @ Step 4g + @get memory controller base address + @ + ldr r1, =MEMC_BASE + + @fetch current mdcnfg value + @ + ldr r3, [r1, #MDCNFG_OFFSET] + + @enable sdram bank 0 if installed (must do for any populated bank) + @ + orr r3, r3, #MDCNFG_DE0 + + @write back mdcnfg, enabling the sdram bank(s) + @ + str r3, [r1, #MDCNFG_OFFSET] + + @ Step 4h + @ write mdmrs + @ + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + @ Done Memory Init + + /*SET_LED 6 */ + + @******************************************************************** + @ Disable (mask) all interrupts at the interrupt controller + @ + + @ clear the interrupt level register (use IRQ, not FIQ) + @ + mov r1, #0 + ldr r2, =ICLR + str r1, [r2] + + @ Set interrupt mask register + @ + ldr r1, =CFG_ICMR_VAL + ldr r2, =ICMR + str r1, [r2] + + @ ******************************************************************** + @ Disable the peripheral clocks, and set the core clock + @ + + @ Turn Off ALL on-chip peripheral clocks for re-configuration + @ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + @ set core clocks + @ + ldr r2, =CFG_CCCR_VAL + ldr r1, =CCCR + str r2, [r1] + + #ifdef ENABLE32KHZ + @ enable the 32Khz oscillator for RTC and PowerManager + @ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + @ NOTE: spin here until OSCC.OOK get set, + @ meaning the PLL has settled. + @ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + @ Turn on needed clocks + @ + ldr r1, =CKEN + ldr r2, =CFG_CKEN_VAL + str r2, [r1] + + /*SET_LED 7 */ + +/* Is this needed???? */ +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + +#endif + + mov pc, r10 + +@ End lowlevel_init diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c new file mode 100644 index 0000000..ce9245c --- /dev/null +++ b/board/pleb2/pleb2.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board */ + gd->bd->bi_arch_number = MACH_TYPE_PLEB2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/pleb2/u-boot.lds b/board/pleb2/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/pleb2/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/pm520/Makefile b/board/pm520/Makefile new file mode 100644 index 0000000..8cf0d7d --- /dev/null +++ b/board/pm520/Makefile @@ -0,0 +1,47 @@ + +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/pm520/config.mk b/board/pm520/config.mk new file mode 100644 index 0000000..ad689f3 --- /dev/null +++ b/board/pm520/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# PM520 board +# + +TEXT_BASE = 0xfff00000 +# TEXT_BASE = 0x00100000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/pm520/flash.c b/board/pm520/flash.c new file mode 100644 index 0000000..3868221 --- /dev/null +++ b/board/pm520/flash.c @@ -0,0 +1,655 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) (x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) (x) +#endif + +/* Intel-compatible flash ID */ +#define INTEL_COMPAT 0x00890089 +#define INTEL_ALT 0x00B000B0 + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_RESET 0xFFFFFFFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); +static void flash_sync_real_protect (flash_info_t * info); +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + extern void flash_preinit(void); + extern void flash_afterinit(ulong, ulong); + ulong flashbase = CFG_FLASH_BASE; + + flash_preinit(); + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + memset(&flash_info[i], 0, sizeof(flash_info_t)); + flash_get_size ((FPW *) flashbase, &flash_info[i]); + flash_get_offsets (flash_info[i].start[0], &flash_info[i]); + break; + default: + panic ("configured to many flash banks!\n"); + break; + } + size += flash_info[i].size; + + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); + } + + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#ifndef CONFIG_BOOT_ROM + flash_protect ( FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0] ); +#endif +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); +#endif + + flash_afterinit(flash_info[0].start[0], flash_info[0].size); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + + case FLASH_28F640J3A: + printf ("28F640J3A\n"); + break; + + case FLASH_28F320J3A: + printf ("28F320J3A\n"); + break; + + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + udelay(100); + + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + info->start[0] = CFG_FLASH_BASE; + break; /* => 32 MB */ + + case (FPW) INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x01000000; + info->start[0] = CFG_FLASH_BASE + 0x01000000; + break; /* => 16 MB */ + + case (FPW) INTEL_ID_28F320J3A: + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x800000; + info->start[0] = CFG_FLASH_BASE + 0x01800000; + break; /* => 8 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +static void flash_sync_real_protect (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + + case FLASH_28F128J3A: + case FLASH_28F640J3A: + case FLASH_28F320J3A: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + udelay(1); + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer (0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* wait at least 35ns (W12) before reading */ + udelay(1); + + /* Intel example code uses offset of 2 for 16 bit flash */ + lock_conf_addr = (FPWV *) info->start[sector] + 2; + ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +/*----------------------------------------------------------------------- + * Set/Clear sector's lock bit, returns: + * 0 - OK + * 1 - Error (timeout, voltage problems, etc.) + */ +int flash_real_protect (flash_info_t *info, long sector, int prot) +{ + ulong start; + int i; + int rc = 0; + vu_long *addr = (vu_long *)(info->start[sector]); + int flag = disable_interrupts(); + + *addr = INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + } + else { /* Clear sector lock bit */ + *addr = INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = INTEL_CONFIRM; /* clear */ + } + + start = get_timer(0); + + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + + if (*addr != INTEL_OK) { + printf("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + rc = 1; + } + + if (!rc) + info->protect[sector] = prot; + + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + * WARNING: code below re-locks sectors only for one bank (info). + * This causes problems on boards where several banks share + * the same chip, as sectors in othere banks will be unlocked + * but not re-locked. It works fine on pm520 though, as there + * is only one chip and one bank. + */ + if (!prot) + { + for (i = 0; i < info->sector_count; i++) + { + if (info->protect[i]) + { + start = get_timer(0); + addr = (vu_long *)(info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) + { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) + { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + } + } + /* + * get the s/w sector protection status in sync with the h/w, + * in case something went wrong during the re-locking. + */ + flash_sync_real_protect(info); /* resets flash to read mode */ + } + + if (flag) + enable_interrupts(); + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h new file mode 100644 index 0000000..f650faa --- /dev/null +++ b/board/pm520/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h new file mode 100644 index 0000000..ffdf039 --- /dev/null +++ b/board/pm520/mt48lc16m16a2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c new file mode 100644 index 0000000..d4cc5cb --- /dev/null +++ b/board/pm520/pm520.c @@ -0,0 +1,322 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m16a2-75.h" +#endif + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +#if defined(CONFIG_MPC5200) +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize + dramsize2; +} + +#elif defined(CONFIG_MGT5100) + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup and enable SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; + __asm__ volatile ("sync"); + + /* find RAM size */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* set SDRAM end address according to size */ + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); + +#else /* CFG_RAMBOOT */ + + /* Retrieve amount of SDRAM available */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif + +int checkboard (void) +{ +#if defined(CONFIG_MPC5200) + puts ("Board: MicroSys PM520 \n"); +#elif defined(CONFIG_MGT5100) + puts ("Board: MicroSys PM510 \n"); +#endif + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ +#if defined(CONFIG_MGT5100) + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ +#endif + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + +void flash_afterinit(ulong start, ulong size) +{ +#if defined(CONFIG_BOOT_ROM) + /* adjust mapping */ + *(vu_long *)MPC5XXX_CS1_START = + START_REG(start); + *(vu_long *)MPC5XXX_CS1_STOP = + STOP_REG(start, size); +#else + /* adjust mapping */ + *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = + START_REG(start); + *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = + STOP_REG(start, size); +#endif +} + + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* adjust flash start */ + gd->bd->bi_flashstart = flash_info[0].start[0]; + return (0); +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif diff --git a/board/pm520/u-boot.lds b/board/pm520/u-boot.lds new file mode 100644 index 0000000..3cc2968 --- /dev/null +++ b/board/pm520/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pm826/Makefile b/board/pm826/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/pm826/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/pm826/config.mk b/board/pm826/config.mk new file mode 100644 index 0000000..c93bad9 --- /dev/null +++ b/board/pm826/config.mk @@ -0,0 +1,37 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MicroSys PM826 board: +# + + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot 64-bit flash +TEXT_BASE = 0xFF000000 + +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/pm826/flash.c b/board/pm826/flash.c new file mode 100644 index 0000000..fee07cf --- /dev/null +++ b/board/pm826/flash.c @@ -0,0 +1,386 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for Intel devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size (volatile unsigned long *baseaddr, + flash_info_t * info) +{ + short i; + unsigned long flashtest_h, flashtest_l; + + info->sector_count = info->size = 0; + info->flash_id = FLASH_UNKNOWN; + + /* Write query command sequence and test FLASH answer + */ + baseaddr[0] = 0x00980098; + baseaddr[1] = 0x00980098; + + flashtest_h = baseaddr[0]; /* manufacturer ID */ + flashtest_l = baseaddr[1]; + + if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) + return (0); /* no or unknown flash */ + + flashtest_h = baseaddr[2]; /* device ID */ + flashtest_l = baseaddr[3]; + + if (flashtest_h != flashtest_l) + return (0); + + switch (flashtest_h) { + case INTEL_ID_28F160C3B: + info->flash_id = FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + case INTEL_ID_28F160F3B: + info->flash_id = FLASH_28F160F3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + case INTEL_ID_28F640C3B: + info->flash_id = FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ + break; + default: + return (0); /* no or unknown flash */ + } + + info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ + + if (info->flash_id & FLASH_BTYPE) { + volatile unsigned long *tmp = baseaddr; + + /* set up sector start adress table (bottom sector type) + * AND unlock the sectors (if our chip is 160C3 or 640C3) + */ + for (i = 0; i < info->sector_count; i++) { + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { + tmp[0] = 0x00600060; + tmp[1] = 0x00600060; + tmp[0] = 0x00D000D0; + tmp[1] = 0x00D000D0; + } + info->start[i] = (uint) tmp; + tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ + } + } + + memset (info->protect, 0, info->sector_count); + + baseaddr[0] = 0x00FF00FF; + baseaddr[1] = 0x00FF00FF; + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + int i; + + /* Init: no FLASHes known + */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here (only one bank) */ + + size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]); + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + /* protect monitor and environment sectors + */ + +#ifndef CONFIG_BOOT_ROM + /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE + * but we shouldn't protect it. + */ + +# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] + ); +# endif +#endif /* CONFIG_BOOT_ROM */ + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case 0x89: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + printf ("28F160C3B (16 M, bottom sector)\n"); + break; + case FLASH_28F160F3B: + printf ("28F160F3B (16 M, bottom sector)\n"); + break; + case FLASH_28F640C3B: + printf ("28F640C3B (64 M, bottom sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Start erase on unprotected sectors + */ + for (sect = s_first; sect <= s_last; sect++) { + volatile ulong *addr = + (volatile unsigned long *) info->start[sect]; + + start = get_timer (0); + last = start; + if (info->protect[sect] == 0) { + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + /* Erase the block + */ + addr[0] = 0x00200020; + addr[1] = 0x00200020; + addr[0] = 0x00D000D0; + addr[1] = 0x00D000D0; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms + */ + udelay (1000); + + last = start; + while ((addr[0] & 0x00800080) != 0x00800080 || + (addr[1] & 0x00800080) != 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout (erase suspended!)\n"); + /* Suspend erase + */ + addr[0] = 0x00B000B0; + addr[1] = 0x00B000B0; + goto DONE; + } + /* show that we're waiting + */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { + printf ("*** ERROR: erase failed!\n"); + goto DONE; + } + } + /* Clear status register and reset to read mode + */ + addr[0] = 0x00500050; + addr[1] = 0x00500050; + addr[0] = 0x00FF00FF; + addr[1] = 0x00FF00FF; + } + + printf (" done\n"); + +DONE: + return 0; +} + +static int write_word (flash_info_t *, volatile unsigned long *, ulong); + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong v; + int i, l, cc = cnt, res = 0; + + + for (v=0; cc > 0; addr += 4, cc -= 4 - l) { + l = (addr & 3); + addr &= ~3; + + for (i = 0; i < 4; i++) { + v = (v << 8) + (i < l || i - l >= cc ? + *((unsigned char *) addr + i) : *src++); + } + + if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) + break; + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, volatile unsigned long *addr, + ulong data) +{ + int flag, res = 0; + ulong start; + + /* Check if Flash is (sufficiently) erased + */ + if ((*addr & data) != data) + return (2); + + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + *addr = 0x00400040; + *addr = data; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + while ((*addr & 0x00800080) != 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + /* Suspend program + */ + *addr = 0x00B000B0; + res = 1; + goto OUT; + } + } + + if (*addr & 0x00220022) { + printf ("*** ERROR: program failed!\n"); + res = 1; + } + +OUT: + /* Clear status register and reset to read mode + */ + *addr = 0x00500050; + *addr = 0x00FF00FF; + + return (res); +} diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c new file mode 100644 index 0000000..7514cd7 --- /dev/null +++ b/board/pm826/pm826.c @@ -0,0 +1,330 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */ +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) +#ifdef CONFIG_ETHER_ON_FCC2 +#error "SCC1 conflicts with FCC2" +#endif + /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ +#else + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */ +#endif + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ + /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */ + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */ + /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */ + /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */ + /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + puts ("Board: PM826\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + + *orx_ptr = orx | ~(size - 1); + + return (size); +} + + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + ulong size8, size9; +#endif + ulong psize = 32 * 1024 * 1024; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#ifndef CFG_RAMBOOT + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL) "); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL) "); + } +#endif + return (psize); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/pm826/u-boot.lds b/board/pm826/u-boot.lds new file mode 100644 index 0000000..05f29c6 --- /dev/null +++ b/board/pm826/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pm828/Makefile b/board/pm828/Makefile new file mode 100644 index 0000000..b9ef0c0 --- /dev/null +++ b/board/pm828/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/pm828/config.mk b/board/pm828/config.mk new file mode 100644 index 0000000..e894af7 --- /dev/null +++ b/board/pm828/config.mk @@ -0,0 +1,37 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MicroSys PM828 board: +# + + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot 64-bit flash +TEXT_BASE = 0x40000000 + +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/pm828/flash.c b/board/pm828/flash.c new file mode 100644 index 0000000..1f21b3e --- /dev/null +++ b/board/pm828/flash.c @@ -0,0 +1,386 @@ +/* + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for Intel devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size (volatile unsigned long *baseaddr, + flash_info_t * info) +{ + short i; + unsigned long flashtest_h, flashtest_l; + + info->sector_count = info->size = 0; + info->flash_id = FLASH_UNKNOWN; + + /* Write query command sequence and test FLASH answer + */ + baseaddr[0] = 0x00980098; + baseaddr[1] = 0x00980098; + + flashtest_h = baseaddr[0]; /* manufacturer ID */ + flashtest_l = baseaddr[1]; + + if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) + return (0); /* no or unknown flash */ + + flashtest_h = baseaddr[2]; /* device ID */ + flashtest_l = baseaddr[3]; + + if (flashtest_h != flashtest_l) + return (0); + + switch (flashtest_h) { + case INTEL_ID_28F160C3B: + info->flash_id = FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + case INTEL_ID_28F160F3B: + info->flash_id = FLASH_28F160F3B; + info->sector_count = 39; + info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ + break; + case INTEL_ID_28F640C3B: + info->flash_id = FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ + break; + default: + return (0); /* no or unknown flash */ + } + + info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ + + if (info->flash_id & FLASH_BTYPE) { + volatile unsigned long *tmp = baseaddr; + + /* set up sector start adress table (bottom sector type) + * AND unlock the sectors (if our chip is 160C3 or 640c3) + */ + for (i = 0; i < info->sector_count; i++) { + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { + tmp[0] = 0x00600060; + tmp[1] = 0x00600060; + tmp[0] = 0x00D000D0; + tmp[1] = 0x00D000D0; + } + info->start[i] = (uint) tmp; + tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ + } + } + + memset (info->protect, 0, info->sector_count); + + baseaddr[0] = 0x00FF00FF; + baseaddr[1] = 0x00FF00FF; + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + int i; + + /* Init: no FLASHes known + */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here (only one bank) */ + + size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]); + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + /* protect monitor and environment sectors + */ + +#ifndef CONFIG_BOOT_ROM + /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE + * but we shouldn't protect it. + */ + +# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] + ); +# endif +#endif /* CONFIG_BOOT_ROM */ + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case 0x89: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + printf ("28F160C3B (16 M, bottom sector)\n"); + break; + case FLASH_28F160F3B: + printf ("28F160F3B (16 M, bottom sector)\n"); + break; + case FLASH_28F640C3B: + printf ("28F640C3B (64 M, bottom sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Start erase on unprotected sectors + */ + for (sect = s_first; sect <= s_last; sect++) { + volatile ulong *addr = + (volatile unsigned long *) info->start[sect]; + + start = get_timer (0); + last = start; + if (info->protect[sect] == 0) { + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + /* Erase the block + */ + addr[0] = 0x00200020; + addr[1] = 0x00200020; + addr[0] = 0x00D000D0; + addr[1] = 0x00D000D0; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms + */ + udelay (1000); + + last = start; + while ((addr[0] & 0x00800080) != 0x00800080 || + (addr[1] & 0x00800080) != 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout (erase suspended!)\n"); + /* Suspend erase + */ + addr[0] = 0x00B000B0; + addr[1] = 0x00B000B0; + goto DONE; + } + /* show that we're waiting + */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { + printf ("*** ERROR: erase failed!\n"); + goto DONE; + } + } + /* Clear status register and reset to read mode + */ + addr[0] = 0x00500050; + addr[1] = 0x00500050; + addr[0] = 0x00FF00FF; + addr[1] = 0x00FF00FF; + } + + printf (" done\n"); + +DONE: + return 0; +} + +static int write_word (flash_info_t *, volatile unsigned long *, ulong); + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong v; + int i, l, cc = cnt, res = 0; + + + for (v=0; cc > 0; addr += 4, cc -= 4 - l) { + l = (addr & 3); + addr &= ~3; + + for (i = 0; i < 4; i++) { + v = (v << 8) + (i < l || i - l >= cc ? + *((unsigned char *) addr + i) : *src++); + } + + if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) + break; + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, volatile unsigned long *addr, + ulong data) +{ + int flag, res = 0; + ulong start; + + /* Check if Flash is (sufficiently) erased + */ + if ((*addr & data) != data) + return (2); + + /* Disable interrupts which might cause a timeout here + */ + flag = disable_interrupts (); + + *addr = 0x00400040; + *addr = data; + + /* re-enable interrupts if necessary + */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + while ((*addr & 0x00800080) != 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + /* Suspend program + */ + *addr = 0x00B000B0; + res = 1; + goto OUT; + } + } + + if (*addr & 0x00220022) { + printf ("*** ERROR: program failed!\n"); + res = 1; + } + +OUT: + /* Clear status register and reset to read mode + */ + *addr = 0x00500050; + *addr = 0x00FF00FF; + + return (res); +} diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c new file mode 100644 index 0000000..3193274 --- /dev/null +++ b/board/pm828/pm828.c @@ -0,0 +1,363 @@ +/* + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */ +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) +#ifdef CONFIG_ETHER_ON_FCC2 +#error "SCC1 conflicts with FCC2" +#endif + /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ +#else + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */ +#endif + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ + /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ + /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */ + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ + /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */ + /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */ + /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */ + /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + puts ("Board: PM828\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile ulong cnt, val; + volatile ulong *addr; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + int i; + ulong save[32]; /* to make test non-destructive */ + ulong maxsize; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or2; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + /* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + i = 0; + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = (volatile ulong *) base + cnt; /* pointer arith! */ + save[i++] = *addr; + *addr = ~cnt; + } + + addr = (volatile ulong *) base; + save[i] = *addr; + *addr = 0; + + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = (volatile ulong *) base + cnt; /* pointer arith! */ + val = *addr; + *addr = save[--i]; + if (val != ~cnt) { + /* Write the actual size to ORx + */ + *orx_ptr = orx | ~(cnt * sizeof (long) - 1); + return (cnt * sizeof (long)); + } + } + return (maxsize); +} + + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + ulong size8, size9; +#endif + ulong psize = 32 * 1024 * 1024; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#ifndef CFG_RAMBOOT + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL) "); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL) "); + } +#endif + return (psize); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/pm828/u-boot.lds b/board/pm828/u-boot.lds new file mode 100644 index 0000000..928c1cf --- /dev/null +++ b/board/pm828/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pm854/Makefile b/board/pm854/Makefile new file mode 100644 index 0000000..7828166 --- /dev/null +++ b/board/pm854/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/pm854/config.mk b/board/pm854/config.mk new file mode 100644 index 0000000..7d58d6e --- /dev/null +++ b/board/pm854/config.mk @@ -0,0 +1,33 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# pm854 board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/pm854/init.S b/board/pm854/init.S new file mode 100644 index 0000000..ade5d6e --- /dev/null +++ b/board/pm854/init.S @@ -0,0 +1,263 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH (8,16,32 or 64 MB) + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7: 256M DDR + * 0x00000000 256M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c new file mode 100644 index 0000000..94c492f --- /dev/null +++ b/board/pm854/pm854.c @@ -0,0 +1,296 @@ + /* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram(void); + + +int board_early_init_f (void) +{ +#if defined(CONFIG_PCI) + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; + + pci->peer &= 0xffffffdf; /* disable master abort */ +#endif + + return 0; +} + +int checkboard (void) +{ + puts("Board: MicroSys PM854\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + int i,x; + + x = 10; + + /* + * Work around to stabilize DDR DLL + */ + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay (200); + while (gur->ddrdllcr != 0x81000100) + { + gur->devdisr = gur->devdisr | 0x00010000; + asm("sync;isync;msync"); + for (i=0; idevdisr = gur->devdisr & 0xfff7ffff; + asm("sync;isync;msync"); + x++; + } + } +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CONFIG_DDR_ECC) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr(); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ + #ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; + #if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + ddr->err_sbe = 0x00ff0000; + #endif + asm("sync;isync;msync"); + udelay(500); + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + asm("sync; isync; msync"); + udelay(500); + #endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_pm854_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_pm854_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds new file mode 100644 index 0000000..fbfc65a --- /dev/null +++ b/board/pm854/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2002,2003, Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/pm854/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/pm854/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pm856/Makefile b/board/pm856/Makefile new file mode 100644 index 0000000..5d8ea34 --- /dev/null +++ b/board/pm856/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/pm856/config.mk b/board/pm856/config.mk new file mode 100644 index 0000000..1f98b33 --- /dev/null +++ b/board/pm856/config.mk @@ -0,0 +1,33 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,2003 Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# PM856 board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/pm856/init.S b/board/pm856/init.S new file mode 100644 index 0000000..ade5d6e --- /dev/null +++ b/board/pm856/init.S @@ -0,0 +1,263 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH (8,16,32 or 64 MB) + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7: 256M DDR + * 0x00000000 256M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c new file mode 100644 index 0000000..5044708 --- /dev/null +++ b/board/pm856/pm856.c @@ -0,0 +1,449 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +long int fixed_sdram(void); + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + + +int board_early_init_f (void) +{ + return 0; +} + +void reset_phy (void) +{ +} + + +int checkboard (void) +{ + puts("Board: MicroSys PM856\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + int i,x; + + x = 10; + + /* + * Work around to stabilize DDR DLL + */ + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay (200); + while (gur->ddrdllcr != 0x81000100) + { + gur->devdisr = gur->devdisr | 0x00010000; + asm("sync;isync;msync"); + for (i=0; idevdisr = gur->devdisr & 0xfff7ffff; + asm("sync;isync;msync"); + x++; + } + } +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CONFIG_DDR_ECC) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr(); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ + #ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; + #if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + ddr->err_sbe = 0x00ff0000; + #endif + asm("sync;isync;msync"); + udelay(500); + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + asm("sync; isync; msync"); + udelay(500); + #endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/pm856/u-boot.lds b/board/pm856/u-boot.lds new file mode 100644 index 0000000..e946a8e --- /dev/null +++ b/board/pm856/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2005 Wolfgang Denk + * (C) Copyright 2002,2003, Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/pm856/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/pm856/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pn62/Makefile b/board/pn62/Makefile new file mode 100644 index 0000000..e85d4fd --- /dev/null +++ b/board/pn62/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o cmd_pn62.o misc.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c new file mode 100644 index 0000000..3ea068d --- /dev/null +++ b/board/pn62/cmd_pn62.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2002 + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include "pn62.h" + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + +/* + * Command led: controls the various LEDs 0..11 on the PN62 card. + */ +int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int number, function; + + if (argc != 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + number = simple_strtoul(argv[1], NULL, 10); + if (number > PN62_LED_MAX) + return 1; + function = simple_strtoul(argv[2], NULL, 16); + set_led (number, function); + return 0; +} +U_BOOT_CMD( + led , 3, 1, do_led, + "led - set LED 0..11 on the PN62 board\n", + "i fun\n" + " - set 'i'th LED to function 'fun'\n" +); + +/* + * Command loadpci: loads a image over PCI. + */ +#define CMD_MOVE_WINDOW 0x1 +#define CMD_BOOT_IMAGE 0x2 + +int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *s; + ulong addr = 0, count = 0; + u32 off; + int cmd, rcode = 0; + + /* pre-set load_addr */ + if ((s = getenv("loadaddr")) != NULL) { + addr = simple_strtoul(s, NULL, 16); + } + + switch (argc) { + case 1: + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + printf ("## Ready for image download ...\n"); + + show_startup_phase(12); + + while (1) { + /* Alive indicator */ + i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY); + + /* Toggle status LEDs */ + cmd = (count / 200) % 4; /* downscale */ + set_led(4, cmd == 0 ? LED_1 : LED_0); + set_led(5, cmd == 1 ? LED_1 : LED_0); + set_led(6, cmd == 2 ? LED_1 : LED_0); + set_led(7, cmd == 3 ? LED_1 : LED_0); + udelay(1000); + count++; + + cmd = i2155x_read_scrapad(BOOT_CMD); + + if (cmd == BOOT_CMD_MOVE) { + off = i2155x_read_scrapad(BOOT_DATA); + off += addr; + i2155x_set_bar_base(3, off); + printf ("## BAR3 Addr moved = 0x%08x\n", off); + i2155x_write_scrapad(BOOT_CMD, ~cmd); + show_startup_phase(13); + } + else if (cmd == BOOT_CMD_BOOT) { + set_led(4, LED_1); + set_led(5, LED_1); + set_led(6, LED_1); + set_led(7, LED_1); + + i2155x_write_scrapad(BOOT_CMD, ~cmd); + show_startup_phase(14); + break; + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + printf("\nAbort\n"); + return 0; + } + + } + + /* Repoint to the default shared memory */ + i2155x_set_bar_base(3, PN62_SMEM_DEFAULT); + + load_addr = addr; + printf ("## Start Addr = 0x%08lx\n", addr); + + show_startup_phase(15); + + /* Loading ok, check if we should attempt an auto-start */ + if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) { + char *local_args[2]; + local_args[0] = argv[0]; + local_args[1] = NULL; + + printf ("Automatic boot of image at addr 0x%08lX ...\n", + load_addr); + rcode = do_bootm (cmdtp, 0, 1, local_args); + } + +#ifdef CONFIG_AUTOSCRIPT + if (load_addr) { + char *s; + + if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { + printf("Running autoscript at addr 0x%08lX ...\n", load_addr); + rcode = autoscript (bd, load_addr); + } + } +#endif + return rcode; +} + +U_BOOT_CMD( + loadpci, 2, 1, do_loadpci, + "loadpci - load binary file over PCI\n", + "[addr]\n" + " - load binary file over PCI to address 'addr'\n" +); + +#endif diff --git a/board/pn62/config.mk b/board/pn62/config.mk new file mode 100644 index 0000000..a2b6f05 --- /dev/null +++ b/board/pn62/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# PN62 boards +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/pn62/misc.c b/board/pn62/misc.c new file mode 100644 index 0000000..dcb2db5 --- /dev/null +++ b/board/pn62/misc.c @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2002 Wolfgang Grandegger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include "pn62.h" + +typedef struct { + pci_dev_t devno; + volatile u32 *csr; + +} i2155x_t; + +static i2155x_t i2155x = { 0, NULL }; + +static struct pci_device_id i2155x_ids[] = { + { 0x1011, 0x0046 }, /* i21554 */ + { 0x8086, 0xb555 } /* i21555 */ +}; + +int i2155x_init(void) +{ + pci_dev_t devno; + u32 val; + int i; + + /* + * Find the Intel bridge. + */ + if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) { + printf("Error: Intel bridge 2155x not found!\n"); + return -1; + } + i2155x.devno = devno; + + /* + * Get auto-configured base address for CSR access. + */ + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val); + if (val & PCI_BASE_ADDRESS_SPACE_IO) { + val &= PCI_BASE_ADDRESS_IO_MASK; + i2155x.csr = (volatile u32 *)(_IO_BASE + val); + } else { + val &= PCI_BASE_ADDRESS_MEM_MASK; + i2155x.csr = (volatile u32 *)val; + } + + /* + * Translate downstream memory 2 (bar3) to base of shared memory. + */ + i2155x_set_bar_base(3, PN62_SMEM_DEFAULT); + + /* + * Enable memory space, I/O space and bus master bits + * in both Primary and Secondary command registers. + */ + val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO; + pci_write_config_word(devno, 0x44, val); + pci_write_config_word(devno, 0x04, val); + + /* + * Clear scratchpad registers. + */ + for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) { + i2155x_write_scrapad(i, 0x0); + } + + /* + * Set interrupt line for Linux. + */ + pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3); + + return 0; +} + +/* + * Access the Scratchpad registers 0..7 of the Intel bridge. + */ +void i2155x_write_scrapad(int idx, u32 val) +{ + if (idx >= 0 && idx < I2155X_SCRAPAD_MAX) + out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val); + else + printf("i2155x_write_scrapad: invalid index\n"); +} + +u32 i2155x_read_scrapad(int idx) +{ + if (idx >= 0 && idx < I2155X_SCRAPAD_MAX) + return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx); + else + printf("i2155x_read_scrapad: invalid index\n"); + return -1; +} + +void i2155x_set_bar_base(int bar, u32 base) +{ + if (bar >= 2 && bar <= 4) { + pci_write_config_dword(i2155x.devno, + I2155X_BAR2_BASE + (bar - 2) * 4, + base); + } +} + +/* + * Read Vital Product Data (VPD) from the Serial EPROM attached + * to the Intel bridge. + */ +int i2155x_read_vpd(int offset, int size, unsigned char *data) +{ + int i, n; + u16 val16; + + for (i = 0; i < size; i++) { + pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR, + offset + i - I2155X_VPD_START); + for (n = 10000; n > 0; n--) { + pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16); + if ((val16 & 0x8000) != 0) /* wait for completion */ + break; + udelay(100); + } + if (n == 0) { + printf("i2155x_read_vpd: TIMEOUT\n"); + return -1; + } + + pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]); + } + + return i; +} + +static struct pci_device_id am79c95x_ids [] = { + { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE }, + { } +}; + + +/* + * Initialize the AMD ethernet controllers. + */ +int am79c95x_init(void) +{ + pci_dev_t devno; + int i; + + /* + * Set interrupt line for Linux. + */ + for (i = 0; i < 2; i++) { + if ((devno = pci_find_devices(am79c95x_ids, i)) < 0) + break; + pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i); + } + if (i < 2) + printf("Error: Only %d AMD Ethernet Controller found!\n", i); + + return 0; +} + + +void set_led(unsigned int number, unsigned int function) +{ + volatile u8 *addr; + + if ((number >= 0) && (number < PN62_LED_MAX) && + (function >= 0) && (function <= LED_LAST_FUNCTION)) { + addr = (volatile u8 *)(PN62_LED_BASE + number * 8); + out_8(addr, function&0xff); + } +} + +/* + * Show fatal error indicated by Kinght Rider(tm) effect + * in LEDS 0-7. LEDS 8-11 contain 4 bit error code. + * Note: this function will not terminate. + */ +void fatal_error(unsigned int error_code) +{ + int i, d; + + for (i = 0; i < 12; i++) { + set_led(i, LED_0); + } + + /* + * Write error code. + */ + set_led(8, (error_code & 0x01) ? LED_1 : LED_0); + set_led(9, (error_code & 0x02) ? LED_1 : LED_0); + set_led(10, (error_code & 0x04) ? LED_1 : LED_0); + set_led(11, (error_code & 0x08) ? LED_1 : LED_0); + + /* + * Yay - Knight Rider effect! + */ + while(1) { + unsigned int delay = 2000; + + for (i = 0; i < 8; i++) { + set_led(i, LED_1); + for (d = 0; d < delay; d++); + set_led(i, LED_0); + } + + for (i = 7; i > 0; i--) { + set_led(i, LED_1); + for (d = 0; d < delay; d++); + set_led(i, LED_0); + } + } +} diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c new file mode 100644 index 0000000..377aaa8 --- /dev/null +++ b/board/pn62/pn62.c @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2002 Wolfgang Grandegger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "pn62.h" + + +static int get_serial_number (char *string, int size); +static int get_mac_address (int id, u8 * mac, char *string, int size); + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress (int phase) +{ + /* + * Show phases of the bootm command on the front panel + * LEDs and the scratchpad register #3 as well. We use + * blinking LEDs for logical "1". + */ + if (phase > 0) { + set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0); + set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0); + set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0); + set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0); + } + i2155x_write_scrapad (BOOT_STATUS, phase); + if (phase < 0) + i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR); +} +#endif + +void show_startup_phase (int phase) +{ + /* + * Show the phase of U-Boot startup on the front panel + * LEDs and the scratchpad register #3 as well. + */ + if (phase > 0) { + set_led (8, (phase & 0x1) ? LED_1 : LED_0); + set_led (9, (phase & 0x2) ? LED_1 : LED_0); + set_led (10, (phase & 0x4) ? LED_1 : LED_0); + set_led (11, (phase & 0x8) ? LED_1 : LED_0); + } + i2155x_write_scrapad (BOOT_STATUS, phase); + if (phase < 0) + i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR); +} + +int checkboard (void) +{ + show_startup_phase (1); + puts ("Board: PN62\n"); + return 0; +} + +long int initdram (int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + show_startup_phase (2); + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg (MEAR1); + emear1 = mpc824x_mpc107_getreg (EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg (MEAR1, mear1); + mpc824x_mpc107_setreg (EMEAR1, emear1); + + return (size); +} + +/* + * Initialize PCI Devices. We rely on auto-configuration. + */ +#ifndef CONFIG_PCI_PNP +#error "CONFIG_PCI_PNP is not defined, please correct!" +#endif + +struct pci_controller hose = { +}; + +void pci_init_board (void) +{ + show_startup_phase (4); + pci_mpc824x_init (&hose); + + show_startup_phase (5); + i2155x_init (); + show_startup_phase (6); + am79c95x_init (); + show_startup_phase (7); +} + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char str[20]; + u8 mac[6]; + + show_startup_phase (8); + /* + * Get serial number and ethernet addresses if not already defined + * and update the board info structure and the environment. + */ + if (getenv ("serial#") == NULL && + get_serial_number (str, strlen (str)) > 0) { + setenv ("serial#", str); + } + show_startup_phase (9); + + if (getenv ("ethaddr") == NULL && + get_mac_address (0, mac, str, sizeof (str)) > 0) { + setenv ("ethaddr", str); + memcpy (gd->bd->bi_enetaddr, mac, 6); + } + show_startup_phase (10); + +#ifdef CONFIG_HAS_ETH1 + if (getenv ("eth1addr") == NULL && + get_mac_address (1, mac, str, sizeof (str)) > 0) { + setenv ("eth1addr", str); + memcpy (gd->bd->bi_enet1addr, mac, 6); + } +#endif /* CONFIG_HAS_ETH1 */ + show_startup_phase (11); + + /* Tell everybody that U-Boot is up and runnig */ + i2155x_write_scrapad (0, 0x12345678); + return (0); +} + +static int get_serial_number (char *string, int size) +{ + int i; + char c; + + if (size < I2155X_VPD_SN_SIZE) + size = I2155X_VPD_SN_SIZE; + for (i = 0; i < (size - 1); i++) { + i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c); + if (c == '\0') + break; + string[i] = c; + } + string[i] = '\0'; /* make sure it's terminated */ + + return i; +} + +static int get_mac_address (int id, u8 * mac, char *string, int size) +{ + if (size < 6 * 3) + return -1; + + i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac); + return sprintf (string, "%02x:%02x:%02x:%02x:%02x:%02x", + mac[0], mac[1], mac[2], + mac[3], mac[4], mac[5]); +} diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h new file mode 100644 index 0000000..7bda0ad --- /dev/null +++ b/board/pn62/pn62.h @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2002 Wolfgang Grandegger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PN62_H_ +#define _PN62_H_ + +/* + * Definitions for the Intel Bridge 21554 or 21555. + */ +#define I2155X_VPD_ADDR 0xe6 +#define I2155X_VPD_DATA 0xe8 + +#define I2155X_VPD_START 0x80 +#define I2155X_VPD_SN_START 0x80 +#define I2155X_VPD_SN_SIZE 0x10 +#define I2155X_VPD_MAC0_START 0x90 +#define I2155X_VPD_MAC1_START 0x96 + +#define I2155X_SCRAPAD_ADDR 0xa8 +#define I2155X_SCRAPAD_MAX 8 + +#define I2155X_BAR2_BASE 0x98 +#define I2155X_BAR3_BASE 0x9c +#define I2155X_BAR4_BASE 0xa0 + +#define I2155X_BAR2_SETUP 0xb0 +#define I2155X_BAR3_SETUP 0xb4 +#define I2155X_BAR4_SETUP 0xb8 + +/* + * Interrupt request numbers + */ +#define PN62_IRQ_HOST 0x0 +#define PN62_IRQ_PLX9054 0x1 +#define PN62_IRQ_ETH0 0x2 +#define PN62_IRQ_ETH1 0x3 +#define PN62_IRQ_COM1 0x4 +#define PN62_IRQ_COM2 0x4 + +/* + * Miscellaneous definitons. + */ +#define PN62_SMEM_DEFAULT 0x1f00000 + +/* + * Definitions for boot protocol using Scratchpad registers. + */ +#define BOOT_DONE 0 +#define BOOT_DONE_CLEAR 0x00dead00 +#define BOOT_DONE_ERROR 0xbad0dead +#define BOOT_DONE_U_BOOT 0x12345678 +#define BOOT_DONE_LINUX 0x87654321 +#define BOOT_CMD 1 +#define BOOT_CMD_MOVE 0x1 +#define BOOT_CMD_BOOT 0x2 +#define BOOT_DATA 2 +#define BOOT_PROTO 3 +#define BOOT_PROTO_READY 0x23456789 +#define BOOT_PROTO_CLEAR 0x00000000 +#define BOOT_STATUS 4 + +/* + * LED Definitions: + */ +#define PN62_LED_BASE 0xff800300 +#define PN62_LED_MAX 12 + +/* + * LED0 - 7 mounted on top of board, D1 - D8 + * LED8 - 11 upper four LEDs on the front panel of the board. + */ +#define LED_0 0x00 /* OFF */ +#define LED_1 0x01 /* ON */ +#define LED_SLOW_CLOCK 0x02 /* SLOW 1Hz ish */ +#define LED_nSLOW_CLOCK 0x03 /* inverse of above */ +#define LED_WATCHDOG_OUT 0x06 /* Reset Watchdog level */ +#define LED_WATCHDOG_CLOCK 0x07 /* clock to watchdog */ + +/* + * LED's currently setup in AMD79C973 device as the following: + * LED0 100Mbit + * LED1 LNKSE + * LED2 TX Activity + * LED3 RX Activity + */ +#define LED_E0_LED0 0x08 /* Ethernet Port 0 LED 0 */ +#define LED_E0_LED1 0x09 /* Ethernet Port 0 LED 1 */ +#define LED_E0_LED2 0x0A /* Ethernet Port 0 LED 2 */ +#define LED_E0_LED3 0x0B /* Ethernet Port 0 LED 3 */ +#define LED_E1_LED0 0x0C /* Ethernet Port 1 LED 0 */ +#define LED_E1_LED1 0x0D /* Ethernet Port 1 LED 1 */ +#define LED_E1_LED2 0x0E /* Ethernet Port 1 LED 2 */ +#define LED_E1_LED3 0x0F /* Ethernet Port 1 LED 3 */ +#define LED_STROBE0 0x10 /* Processor Strobe 0 */ +#define LED_STROBE1 0x11 /* Processor Strobe 1 */ +#define LED_STROBE2 0x12 /* Processor Strobe 2 */ +#define LED_STROBE3 0x13 /* Processor Strobe 3 */ +#define LED_STROBE4 0x14 /* Processor Strobe 4 */ +#define LED_STROBE5 0x15 /* Processor Strobe 5 */ +#define LED_STROBE6 0x16 /* Processor Strobe 6 */ +#define LED_STROBE7 0x17 /* Processor Strobe 7 */ +#define LED_HOST_STROBE0 0x18 /* Host strobe 0 */ +#define LED_HOST_STROBE1 0x19 /* Host strobe 1 */ +#define LED_HOST_STROBE2 0x1A /* Host strobe 2 */ +#define LED_HOST_STROBE3 0x1B /* Host strobe 3 */ +#define LED_HOST_STROBE4 0x1C /* Host strobe 4 */ +#define LED_HOST_STROBE5 0x1D /* Host strobe 5 */ +#define LED_HOST_STROBE6 0x1E /* Host strobe 6 */ +#define LED_HOST_STROBE7 0x1F /* Host strobe 7 */ +#define LED_MPC_INT0 0x20 /* MPC8240 INT 0 */ +#define LED_MPC_INT1 0x21 /* MPC8240 INT 1 */ +#define LED_MPC_INT2 0x22 /* MPC8240 INT 2 */ +#define LED_MPC_INT3 0x23 /* MPC8240 INT 3 */ +#define LED_MPC_INT4 0x24 /* MPC8240 INT 4 */ +#define LED_UART0_CS 0x25 /* UART 0 Chip Select */ +#define LED_UART1_CS 0x26 /* UART 1 Chip Select */ +#define LED_SRAM_CS 0x27 /* SRAM Chip Select */ +#define LED_SRAM_WR 0x28 /* SRAM WR Signal */ +#define LED_SRAM_RD 0x29 /* SRAM RD Signal */ +#define LED_MPC_RCS0 0x2A /* MPC8240 RCS0 Signal */ +#define LED_S_PCI_FRAME 0x2B /* Secondary PCI Frame Signal */ +#define LED_MPC_CS0 0x2C /* MPC8240 CS0 Signal */ +#define LED_HOST_INT 0x2D /* MPC8240 to Host Interrupt signal */ +#define LED_LAST_FUNCTION LED_HOST_INT /* last function */ + +/* + * Forward declarations + */ +int i2155x_init (void); +void i2155x_write_scrapad(int idx, u32 val); +u32 i2155x_read_scrapad (int idx); +void i2155x_set_bar_base (int bar, u32 addr); +int i2155x_read_vpd (int offset, int size, unsigned char *data); + +int am79c95x_init (void); + +void set_led (unsigned int number, unsigned int function); +void fatal_error (unsigned int error_code); +void show_startup_phase (int phase); + + +#endif /* _PN62_H_ */ diff --git a/board/pn62/u-boot.lds b/board/pn62/u-boot.lds new file mode 100644 index 0000000..eaee3fd --- /dev/null +++ b/board/pn62/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile new file mode 100644 index 0000000..351f4ee --- /dev/null +++ b/board/ppmc8260/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := ppmc8260.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ppmc8260/config.mk b/board/ppmc8260/config.mk new file mode 100644 index 0000000..d06fcea --- /dev/null +++ b/board/ppmc8260/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MBX8xx boards +# + +TEXT_BASE = 0xfe000000 +TEXT_END = 0xfe080000 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c new file mode 100644 index 0000000..2b20c26 --- /dev/null +++ b/board/ppmc8260/ppmc8260.c @@ -0,0 +1,307 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ + /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ + /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ + /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ + /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ + /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_A1:L1TSYNC */ + /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* TDN_A1:L1RSYNC */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_A1:L1CLK0 */ + /* PB15 */ { 1, 0, 0, 1, 0, 1 }, /* /FETHRST */ + /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* FETHDIS */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_B1:L1CLK0 */ + /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TXD */ + /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RXD */ + /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TSYNC */ + /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RSYNC */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* CLK4 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* CLK7 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ + /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[0] */ + /* PC14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[0] */ + /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[1] */ + /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[1] */ + /* PC11 */ { 1, 1, 0, 1, 0, 0 }, /* TDM_D1:L1CLK0 */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ + /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[2]*/ + /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[2] */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DACK */ + /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DONE */ + /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DREQ */ + /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DREQ */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ + /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ + /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[3] */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_C1:L1RSYNC */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TXD */ + /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RXD */ + /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TSYNC */ + /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RSYNC*/ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1:TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:RXD */ + /* PD7 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:SMSYN */ + /* PD6 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DACK */ + /* PD5 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DONE */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: Wind River PPMC8260\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0xff; + volatile uchar *ramaddr0 = (uchar *) (CFG_SDRAM0_BASE); + volatile uchar *ramaddr1 = (uchar *) (CFG_SDRAM1_BASE); + ulong psdmr = CFG_PSDMR; + volatile uchar *ramaddr2 = (uchar *) (CFG_SDRAM2_BASE); + ulong lsdmr = CFG_LSDMR; + int i; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#ifndef CFG_RAMBOOT + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr0++ = c; + *ramaddr1++ = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) { + *ramaddr0++ = c; + *ramaddr1++ = c; + } + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + ramaddr0 = (uchar *) (CFG_SDRAM0_BASE + 0x110); + ramaddr1 = (uchar *) (CFG_SDRAM1_BASE + 0x110); + *ramaddr0 = c; + *ramaddr1 = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr0 = c; + *ramaddr1 = c; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; + *ramaddr2++ = c; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) { + *ramaddr2++ = c; + } + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; + *ramaddr2++ = c; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr2 = c; +#endif + + /* return total ram size */ + return ((CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE) * 1024 * 1024); +} + +#ifdef CONFIG_MISC_INIT_R +/* ------------------------------------------------------------------------- */ +int misc_init_r (void) +{ +#ifdef CFG_LED_BASE + uchar ds = *(unsigned char *) (CFG_LED_BASE + 1); + uchar ss; + uchar tmp[64]; + int res; + + if ((ds != 0) && (ds != 0xff)) { + res = getenv_r ("ethaddr", (char *)tmp, sizeof (tmp)); + if (res > 0) { + ss = ((ds >> 4) & 0x0f); + ss += ss < 0x0a ? '0' : ('a' - 10); + tmp[15] = ss; + + ss = (ds & 0x0f); + ss += ss < 0x0a ? '0' : ('a' - 10); + tmp[16] = ss; + + tmp[17] = '\0'; + setenv ("ethaddr", (char *)tmp); + /* set the led to show the address */ + *((unsigned char *) (CFG_LED_BASE + 1)) = ds; + } + } +#endif /* CFG_LED_BASE */ + return (0); +} +#endif /* CONFIG_MISC_INIT_R */ diff --git a/board/ppmc8260/strataflash.c b/board/ppmc8260/strataflash.c new file mode 100644 index 0000000..f9abfac --- /dev/null +++ b/board/ppmc8260/strataflash.c @@ -0,0 +1,752 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + + +#define FLASH_MAN_CFI 0x01000000 + + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char * cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +/*----------------------------------------------------------------------- + * Functions + */ + + +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *)(info->start[sect] + (offset * info->portwidth))); +} +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | + (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + unsigned long address; + + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if( info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3 ), (info->chipwidth << 3 )); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n"); + printf (" %08lX%5s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for(i=0;iportwidth) && (cnt > 0) ; i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *)cp)); + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while(cnt >= info->portwidth) { + i = info->buffer_size > cnt? cnt: info->buffer_size; + if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + /* handle the aligned part */ + while(cnt >= info->portwidth) { + cword.l = 0; + for(i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; iportwidth; ++i, ++cp) { + flash_add_byte(info, & cword, (*(uchar *)cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if(prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, + prot?"protect":"unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if(prot == 0) { + int i; + for(i = 0 ; isector_count; i++) { + if(info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt,info->start[sector]); + if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ + printf("Command Sequence Error.\n"); + } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) +{ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) +{ + int i; + uchar *cp = (uchar *)cmdbuf; + for(i=0; i< info->portwidth; i++) + *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi(flash_info_t * info) +{ + + for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; + info->portwidth <<= 1) { + for(info->chipwidth =FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } + return 0; +} +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t * info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if(flash_detect_cfi(info)){ + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif + sect_cnt = 0; + sector = base; + for(i = 0 ; i < num_erase_regions; i++) { + if(i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) +1; + for(j = 0; j< erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *)dest; + + + /* Check if Flash is (sufficiently) erased */ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if(!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if(flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t *info, ulong addr) +{ + int sector; + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *)dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar)cnt-1); + while(cnt-- > 0) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check(info, sector, info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/ppmc8260/u-boot.lds b/board/ppmc8260/u-boot.lds new file mode 100644 index 0000000..84d4b78 --- /dev/null +++ b/board/ppmc8260/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile new file mode 100644 index 0000000..47116d3 --- /dev/null +++ b/board/prodrive/p3p440/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk new file mode 100644 index 0000000..e5722dd --- /dev/null +++ b/board/prodrive/p3p440/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFFC0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S new file mode 100644 index 0000000..ee6b706 --- /dev/null +++ b/board/prodrive/p3p440/init.S @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright (C) 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c new file mode 100644 index 0000000..d42a643 --- /dev/null +++ b/board/prodrive/p3p440/p3p440.c @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright (C) 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "p3p440.h" + +void set_led(int color) +{ + switch (color) { + case LED_OFF: + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED); + break; + + case LED_GREEN: + out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED); + break; + + case LED_RED: + out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN); + break; + + case LED_ORANGE: + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED); + break; + } +} + +static int is_monarch(void) +{ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_GPIO_RDY); + udelay(1000); + + if (in32(GPIO0_IR) & CFG_MONARCH_IO) + return 0; + else + return 1; +} + +static void wait_for_pci_ready(void) +{ + /* + * Configure EREADY_IO as input + */ + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO); + udelay(1000); + + for (;;) { + if (in32(GPIO0_IR) & CFG_EREADY_IO) + return; + } + +} + +int board_early_init_f(void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + + /*-------------------------------------------------------------------- + * Setup pin multiplexing (GPIO/IRQ...) + *-------------------------------------------------------------------*/ + mtdcr(cpc0_gpio, 0x03F01F80); + + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN); + out32(GPIO0_OR, CFG_GPIO_RDY); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: P3P440"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + if (is_monarch()) { + puts(", Monarch"); + } else { + puts(", None-Monarch"); + } + + putc('\n'); + + return (0); +} + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if only one FLASH bank is available + */ + if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { + mtebc(pb1cr, 0); /* disable cs */ + mtebc(pb1ap, 0); + mtebc(pb2cr, 0); /* disable cs */ + mtebc(pb2ap, 0); + mtebc(pb3cr, 0); /* disable cs */ + mtebc(pb3ap, 0); + } + + return 0; +} + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The P3P440 board is always configured as the host & requires the + * PCI arbiter to be disabled because it's an PMC module. + *--------------------------------------------------------------------------*/ + strap = mfdcr(cpc0_strp1); + if (strap & 0x00100000) { + printf("PCI: CPC0_STRP1[PAE] set.\n"); + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r(PCIX0_PIM0SA, 0); /* disable */ + out32r(PCIX0_PIM1SA, 0); /* disable */ + out32r(PCIX0_PIM2SA, 0); /* disable */ + out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE); + out32r(PCIX0_PIM0LAH, 0); + out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); + + out32r(PCIX0_BAR0, 0); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); + out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); + + out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + if (is_monarch()) { + wait_for_pci_ready(); + return 1; /* return 1 for host controller */ + } else { + return 0; /* return 0 for adapter controller */ + } +} +#endif /* defined(CONFIG_PCI) */ diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h new file mode 100644 index 0000000..e4e87d1 --- /dev/null +++ b/board/prodrive/p3p440/p3p440.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __P3P440_H__ +#define __P3P440_H__ + +#define CFG_GPIO_RDY (0x80000000 >> 11) +#define CFG_MONARCH_IO (0x80000000 >> 18) +#define CFG_EREADY_IO (0x80000000 >> 20) +#define CFG_LED_GREEN (0x80000000 >> 21) +#define CFG_LED_RED (0x80000000 >> 22) + +#define LED_OFF 1 +#define LED_GREEN 2 +#define LED_RED 3 +#define LED_ORANGE 4 + +long int fixed_sdram(void); + +#endif /* __P3P440_H__ */ diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds new file mode 100644 index 0000000..92bb740 --- /dev/null +++ b/board/prodrive/p3p440/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/prodrive/p3p440/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c new file mode 100644 index 0000000..4965743 --- /dev/null +++ b/board/psyent/common/AMDLV065D.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#if defined(CONFIG_NIOS) +#include +#else +#include +#endif + +#define SECTSZ (64 * 1024) +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------*/ +unsigned long flash_init (void) +{ + int i; + unsigned long addr; + flash_info_t *fli = &flash_info[0]; + + fli->size = CFG_FLASH_SIZE; + fli->sector_count = CFG_MAX_FLASH_SECT; + fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; + + addr = CFG_FLASH_BASE; + for (i = 0; i < fli->sector_count; ++i) { + fli->start[i] = addr; + addr += SECTSZ; + fli->protect[i] = 1; + } + + return (CFG_FLASH_SIZE); +} +/*--------------------------------------------------------------------*/ +void flash_print_info (flash_info_t * info) +{ + int i, k; + unsigned long size; + int erased; + volatile unsigned char *flash; + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + + /* Check if whole sector is erased */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]); + for (k = 0; k < size; k++) { + if (*flash++ != 0xff) { + erased = 0; + break; + } + } + + /* Print the info */ + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + CACHE_NO_BYPASS(info->start[i]), + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf ("\n"); +} + +/*-------------------------------------------------------------------*/ + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) + CACHE_BYPASS(info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int prot, sect; + ulong start; + + /* Some sanity checking */ + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* It's ok to erase multiple sectors provided we don't delay more + * than 50 usec between cmds ... at which point the erase time-out + * occurs. So don't go and put printf() calls in the loop ... it + * won't be very helpful ;-) + */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) + CACHE_BYPASS((info->start[sect])); + *addr = 0xaa; + *addr = 0x55; + *addr = 0x80; + *addr = 0xaa; + *addr = 0x55; + *addr2 = 0x30; + /* Now just wait for 0xff & provide some user + * feedback while we wait. + */ + start = get_timer (0); + while (*addr2 != 0xff) { + udelay (1000 * 1000); + putc ('.'); + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + printf ("timeout\n"); + return 1; + } + } + } + } + printf ("\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + + vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]); + vu_char *dst = (vu_char *) CACHE_BYPASS(addr); + unsigned char b; + ulong start; + + while (cnt) { + /* Check for sufficient erase */ + b = *src; + if ((*dst & b) != b) { + printf ("%02x : %02x\n", *dst, b); + return (2); + } + + *cmd = 0xaa; + *cmd = 0x55; + *cmd = 0xa0; + *dst = b; + + /* Verify write */ + start = get_timer (0); + while (*dst != b) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return 1; + } + } + dst++; + src++; + cnt--; + } + + return (0); +} diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile new file mode 100644 index 0000000..8e55c9b --- /dev/null +++ b/board/psyent/pci5441/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COMOBJS := ../common/AMDLV065D.o + +OBJS := $(BOARD).o $(COMOBJS) + +SOBJS = + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk new file mode 100644 index 0000000..d72bcee --- /dev/null +++ b/board/psyent/pci5441/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2004, Psyent Corporation +# Scott McNutt +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x018e0000 + +PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/psyent/pci5441/pci5441.c b/board/psyent/pci5441/pci5441.c new file mode 100644 index 0000000..ea80dd1 --- /dev/null +++ b/board/psyent/pci5441/pci5441.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts ("BOARD : Psyent PCI-5441\n"); + return 0; +} + +long int initdram (int board_type) +{ + return (0); +} diff --git a/board/psyent/pci5441/u-boot.lds b/board/psyent/pci5441/u-boot.lds new file mode 100644 index 0000000..8f9cd8f --- /dev/null +++ b/board/psyent/pci5441/u-boot.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-littlenios2") +OUTPUT_ARCH(nios2) +ENTRY(_start) + +SECTIONS +{ + .text : + { + cpu/nios2/start.o (.text) + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + } + . = ALIGN (4); + _etext = .; + PROVIDE (etext = .); + + /* CMD TABLE - sandwich this in between text and data so + * the initialization code relocates the command table as + * well -- admittedly, this is just pure laziness ;-) + */ + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + /* INIT DATA sections - "Small" data (see the gcc -G option) + * is always gp-relative. Here we make all init data sections + * adjacent to simplify the startup code -- and provide + * the global pointer for gp-relative access. + */ + _data = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + } + + . = ALIGN(16); + _gp = .; /* Global pointer addr */ + PROVIDE (gp = .); + + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* UNINIT DATA - Small uninitialized data is first so it's + * adjacent to sdata and can be referenced via gp. The normal + * bss follows. We keep it adjacent to simplify init code. + */ + __bss_start = .; + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + . = ALIGN(4); + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + *(.scommon) + } + . = ALIGN(4); + _end = .; + PROVIDE (end = .); + + /* DEBUG -- symbol table, string table, etc. etc. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile new file mode 100644 index 0000000..5c1db03 --- /dev/null +++ b/board/psyent/pk1c20/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COMOBJS := ../common/AMDLV065D.o + +OBJS := $(BOARD).o led.o $(COMOBJS) + +SOBJS = + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk new file mode 100644 index 0000000..d72bcee --- /dev/null +++ b/board/psyent/pk1c20/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2004, Psyent Corporation +# Scott McNutt +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x018e0000 + +PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c new file mode 100644 index 0000000..c175c9b --- /dev/null +++ b/board/psyent/pk1c20/led.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* The LED port is configured as output only, so we + * must track the state manually. + */ +static led_id_t val = 0; + +void __led_init (led_id_t mask, int state) +{ + nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); + + if (state == STATUS_LED_ON) + val &= ~mask; + else + val |= mask; + pio->data = val; +} + +void __led_set (led_id_t mask, int state) +{ + nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); + + if (state == STATUS_LED_ON) + val &= ~mask; + else + val |= mask; + pio->data = val; +} + +void __led_toggle (led_id_t mask) +{ + nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); + + val ^= mask; + pio->data = val; +} diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c new file mode 100644 index 0000000..1924ae3 --- /dev/null +++ b/board/psyent/pk1c20/pk1c20.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts ("BOARD : Psyent PK-1C20\n"); + return 0; +} + +long int initdram (int board_type) +{ + return (0); +} diff --git a/board/psyent/pk1c20/u-boot.lds b/board/psyent/pk1c20/u-boot.lds new file mode 100644 index 0000000..8f9cd8f --- /dev/null +++ b/board/psyent/pk1c20/u-boot.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-littlenios2") +OUTPUT_ARCH(nios2) +ENTRY(_start) + +SECTIONS +{ + .text : + { + cpu/nios2/start.o (.text) + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + } + . = ALIGN (4); + _etext = .; + PROVIDE (etext = .); + + /* CMD TABLE - sandwich this in between text and data so + * the initialization code relocates the command table as + * well -- admittedly, this is just pure laziness ;-) + */ + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + /* INIT DATA sections - "Small" data (see the gcc -G option) + * is always gp-relative. Here we make all init data sections + * adjacent to simplify the startup code -- and provide + * the global pointer for gp-relative access. + */ + _data = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + } + + . = ALIGN(16); + _gp = .; /* Global pointer addr */ + PROVIDE (gp = .); + + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* UNINIT DATA - Small uninitialized data is first so it's + * adjacent to sdata and can be referenced via gp. The normal + * bss follows. We keep it adjacent to simplify init code. + */ + __bss_start = .; + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + . = ALIGN(4); + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + *(.scommon) + } + . = ALIGN(4); + _end = .; + PROVIDE (end = .); + + /* DEBUG -- symbol table, string table, etc. etc. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/board/purple/Makefile b/board/purple/Makefile new file mode 100644 index 0000000..b2f2fc0 --- /dev/null +++ b/board/purple/Makefile @@ -0,0 +1,42 @@ + +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o sconsole.o +SOBJS = lowlevel_init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/purple/config.mk b/board/purple/config.mk new file mode 100644 index 0000000..ea478ed --- /dev/null +++ b/board/purple/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Purple board with MIPS 5Kc CPU core +# + +# ROM version +TEXT_BASE = 0xB0000000 + +# RAM version +#TEXT_BASE = 0x80100000 diff --git a/board/purple/flash.c b/board/purple/flash.c new file mode 100644 index 0000000..7522580 --- /dev/null +++ b/board/purple/flash.c @@ -0,0 +1,596 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; + +#define FLASH_ID_MASK 0xFFFFFFFF + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +#define FLASH29_REG_ADRS(reg) ((FPWV *)PHYS_FLASH_1 + (reg)) + +/* FLASH29 command register addresses */ + +#define FLASH29_REG_FIRST_CYCLE FLASH29_REG_ADRS (0x1555) +#define FLASH29_REG_SECOND_CYCLE FLASH29_REG_ADRS (0x2aaa) +#define FLASH29_REG_THIRD_CYCLE FLASH29_REG_ADRS (0x3555) +#define FLASH29_REG_FOURTH_CYCLE FLASH29_REG_ADRS (0x4555) +#define FLASH29_REG_FIFTH_CYCLE FLASH29_REG_ADRS (0x5aaa) +#define FLASH29_REG_SIXTH_CYCLE FLASH29_REG_ADRS (0x6555) + +/* FLASH29 command definitions */ + +#define FLASH29_CMD_FIRST 0xaaaaaaaa +#define FLASH29_CMD_SECOND 0x55555555 +#define FLASH29_CMD_FOURTH 0xaaaaaaaa +#define FLASH29_CMD_FIFTH 0x55555555 +#define FLASH29_CMD_SIXTH 0x10101010 + +#define FLASH29_CMD_SECTOR 0x30303030 +#define FLASH29_CMD_PROGRAM 0xa0a0a0a0 +#define FLASH29_CMD_CHIP_ERASE 0x80808080 +#define FLASH29_CMD_READ_RESET 0xf0f0f0f0 +#define FLASH29_CMD_AUTOSELECT 0x90909090 +#define FLASH29_CMD_READ 0x70707070 + +#define IN_RAM_CMD_READ 0x1 +#define IN_RAM_CMD_WRITE 0x2 + +#define FLASH_WRITE_CMD ((ulong)(flash_write_cmd) & 0x7)+0xbf008000 +#define FLASH_READ_CMD ((ulong)(flash_read_cmd) & 0x7)+0xbf008000 + +typedef void (*FUNCPTR_CP)(ulong *source, ulong *destination, ulong nlongs); +typedef void (*FUNCPTR_RD)(int cmd, FPWV * pFA, char * string, int strLen); +typedef void (*FUNCPTR_WR)(int cmd, FPWV * pFA, FPW value); + +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static int write_word(flash_info_t *info, FPWV *dest, FPW data); +static void flash_get_offsets(ulong base, flash_info_t *info); +static flash_info_t *flash_get_info(ulong base); + +static void load_cmd(ulong cmd); +static ulong in_ram_cmd = 0; + + +/****************************************************************************** +* +* Don't change the program architecture +* This architecture assure the program +* can be relocated to scratch ram +*/ +static void flash_read_cmd(int cmd, FPWV * pFA, char * string, int strLen) +{ + int i,j; + FPW temp,temp1; + FPWV *str; + + str = (FPWV *)string; + + j= strLen/4; + + if(cmd == FLASH29_CMD_AUTOSELECT) + { + *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST; + *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND; + *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_AUTOSELECT; + } + + if(cmd == FLASH29_CMD_READ) + { + i = 0; + while(i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM160B) { + + int bootsect_size[4]; /* number of bytes/boot sector */ + int sect_size; /* number of bytes/regular sector */ + + bootsect_size[0] = 0x00008000; + bootsect_size[1] = 0x00004000; + bootsect_size[2] = 0x00004000; + bootsect_size[3] = 0x00010000; + sect_size = 0x00020000; + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += i < 4 ? bootsect_size[i] : sect_size; + } + } +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->start[0] <= base && base < info->start[0] + info->size) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + uchar *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM160B: + fmt = "29LV160B%s (16 Mbit, %s)\n"; + break; + case FLASH_28F800C3B: + case FLASH_28F800C3T: + fmt = "28F800C3%s (8 Mbit, %s)\n"; + break; + case FLASH_INTEL800B: + case FLASH_INTEL800T: + fmt = "28F800B3%s (8 Mbit, %s)\n"; + break; + case FLASH_28F160C3B: + case FLASH_28F160C3T: + fmt = "28F160C3%s (16 Mbit, %s)\n"; + break; + case FLASH_INTEL160B: + case FLASH_INTEL160T: + fmt = "28F160B3%s (16 Mbit, %s)\n"; + break; + case FLASH_28F320C3B: + case FLASH_28F320C3T: + fmt = "28F320C3%s (32 Mbit, %s)\n"; + break; + case FLASH_INTEL320B: + case FLASH_INTEL320T: + fmt = "28F320B3%s (32 Mbit, %s)\n"; + break; + case FLASH_28F640C3B: + case FLASH_28F640C3T: + fmt = "28F640C3%s (64 Mbit, %s)\n"; + break; + case FLASH_INTEL640B: + case FLASH_INTEL640T: + fmt = "28F640B3%s (64 Mbit, %s)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + FUNCPTR_RD absEntry; + FPW retValue; + int flag; + + load_cmd(IN_RAM_CMD_READ); + absEntry = (FUNCPTR_RD)FLASH_READ_CMD; + + flag = disable_interrupts(); + absEntry(FLASH29_CMD_AUTOSELECT,0,0,0); + if (flag) enable_interrupts(); + + udelay(100); + + flag = disable_interrupts(); + absEntry(FLASH29_CMD_READ, addr + 1, (char *)&retValue, sizeof(retValue)); + absEntry(FLASH29_CMD_READ_RESET,0,0,0); + if (flag) enable_interrupts(); + + udelay(100); + + switch (retValue) { + + case (FPW)AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets((ulong)addr, info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + ulong start, now, last; + int rcode = 0; + FUNCPTR_WR absEntry; + + load_cmd(IN_RAM_CMD_WRITE); + absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM160B: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + last = get_timer(0); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + absEntry(FLASH29_CMD_SECTOR, addr, 0); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + while ((now = get_timer(start)) <= CFG_FLASH_ERASE_TOUT) { + + /* show that we're waiting */ + if ((get_timer(last)) > CFG_HZ) {/* every second */ + putc ('.'); + last = get_timer(0); + } + } + + flag = disable_interrupts(); + absEntry(FLASH29_CMD_READ_RESET,0,0); + if (flag) + enable_interrupts(); + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + res = write_word(info, (FPWV *)addr, data); + } + + return (res); +} + +static int write_word (flash_info_t *info, FPWV *dest, FPW data) +{ + int res = 0; /* result, assume success */ + FUNCPTR_WR absEntry; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + if (info->start[0] != PHYS_FLASH_1) + { + return (3); + } + + load_cmd(IN_RAM_CMD_WRITE); + absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD; + + flag = disable_interrupts(); + absEntry(FLASH29_CMD_PROGRAM,dest,data); + if (flag) enable_interrupts(); + + udelay(100); + + flag = disable_interrupts(); + absEntry(FLASH29_CMD_READ_RESET,0,0); + if (flag) enable_interrupts(); + + return (res); +} diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S new file mode 100644 index 0000000..668124a --- /dev/null +++ b/board/purple/lowlevel_init.S @@ -0,0 +1,37 @@ +/* + * Memory sub-system initialization code for PURPLE development board. + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define MC_IOGP 0xBF800800 + + .globl lowlevel_init +lowlevel_init: + li t0, MC_IOGP + li t1, 0xf24 + sw t1, 0(t0) + j ra + nop diff --git a/board/purple/purple.c b/board/purple/purple.c new file mode 100644 index 0000000..4c3e5b4 --- /dev/null +++ b/board/purple/purple.c @@ -0,0 +1,266 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "sconsole.h" + +#define cache_unroll(base,op) \ + __asm__ __volatile__(" \ + .set noreorder; \ + .set mips3; \ + cache %1, (%0); \ + .set mips0; \ + .set reorder" \ + : \ + : "r" (base), \ + "i" (op)); + +typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs); + +extern void asc_serial_init (void); +extern void asc_serial_putc (char); +extern void asc_serial_puts (const char *); +extern int asc_serial_getc (void); +extern int asc_serial_tstc (void); +extern void asc_serial_setbrg (void); + +static void sdram_timing_init (ulong size) +{ + register uint pass; + register uint done; + register uint count; + register uint p0, p1, p2, p3, p4; + register uint addr; + +#define WRITE_MC_IOGP_1 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+(p4<<8)+(p0<<4)+p3; +#define WRITE_MC_IOGP_2 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+((p4-16)<<8)+(p0<<4)+p3; + + done = 0; + p0 = 2; + while (p0 < 4 && done == 0) { + p1 = 0; + while (p1 < 2 && done == 0) { + p2 = 0; + while (p2 < 2 && done == 0) { + p3 = 0; + while (p3 < 16 && done == 0) { + count = 0; + p4 = 0; + while (p4 < 32 && done == 0) { + WRITE_MC_IOGP_1; + + for (addr = KSEG1 + 0x4000; + addr < KSEG1ADDR (size); + addr = addr + 4) { + *(uint *) addr = 0xaa55aa55; + } + + pass = 1; + + for (addr = KSEG1 + 0x4000; + addr < KSEG1ADDR (size) && pass == 1; + addr = addr + 4) { + if (*(uint *) addr != 0xaa55aa55) + pass = 0; + } + + if (pass == 1) { + count++; + } else { + count = 0; + } + + if (count == 32) { + WRITE_MC_IOGP_2; + done = 1; + } + p4++; + } + p3++; + } + p2++; + } + p1++; + } + p0++; + if (p0 == 1) + p0++; + } +} + +long int initdram(int board_type) +{ + /* The only supported number of SDRAM banks is 4. + */ +#define CFG_NB 4 + + ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; + ulong cfgdw = *INCA_IP_SDRAM_MC_CFGDW; + int cols = cfgpb0 & 0xF; + int rows = (cfgpb0 & 0xF0) >> 4; + int dw = cfgdw & 0xF; + ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; + void (* sdram_init) (ulong); + + sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init); + + sdram_init(0x10000); + + return size; +} + +int checkboard (void) +{ + + unsigned long chipid = *(unsigned long *)0xB800C800; + + printf ("Board: Purple PLB 2800 chip version %ld, ", chipid & 0xF); + + printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000); + + return 0; +} + +int misc_init_r (void) +{ + asc_serial_init (); + + sconsole_putc = asc_serial_putc; + sconsole_puts = asc_serial_puts; + sconsole_getc = asc_serial_getc; + sconsole_tstc = asc_serial_tstc; + sconsole_setbrg = asc_serial_setbrg; + + sconsole_flush (); + return (0); +} + +/******************************************************************************* +* +* copydwords - copy one buffer to another a long at a time +* +* This routine copies the first longs from to . +*/ +static void copydwords (ulong *source, ulong *destination, ulong nlongs) +{ + ulong temp,temp1; + ulong *dstend = destination + nlongs; + + while (destination < dstend) + { + temp = *source++; + /* dummy read from sdram */ + temp1 = *(ulong *)0xa0000000; + /* avoid optimization from compliler */ + *(ulong *)0xbf0081f8 = temp1 + temp; + *destination++ = temp; + + } +} + +/******************************************************************************* +* +* copyLongs - copy one buffer to another a long at a time +* +* This routine copies the first longs from to . +*/ +static void copyLongs (ulong *source, ulong *destination, ulong nlongs) +{ + FUNCPTR absEntry; + + absEntry = (FUNCPTR)(0xbf008000+((ulong)copydwords & 0x7)); + absEntry(source, destination, nlongs); +} + +/******************************************************************************* +* +* programLoad - load program into ram +* +* This routine load copydwords into ram +* +*/ +static void programLoad(void) +{ + FUNCPTR absEntry; + ulong *src,*dst; + + src = (ulong *)(TEXT_BASE + 0x428); + dst = (ulong *)0xbf0081d0; + + absEntry = (FUNCPTR)(TEXT_BASE + 0x400); + absEntry(src,dst,0x6); + + src = (ulong *)((ulong)copydwords & 0xfffffff8); + dst = (ulong *)0xbf008000; + + absEntry(src,dst,0x38); +} + +/******************************************************************************* +* +* copy_code - copy u-boot image from flash to RAM +* +* This routine is needed to solve flash problems on this board +* +*/ +void copy_code (ulong dest_addr) +{ + extern long uboot_end_data; + unsigned long start; + unsigned long end; + + /* load copydwords into ram + */ + programLoad(); + + /* copy u-boot code + */ + copyLongs((ulong *)CFG_MONITOR_BASE, + (ulong *)dest_addr, + ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4); + + + /* flush caches + */ + + start = KSEG0; + end = start + CFG_DCACHE_SIZE; + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_D); + start += CFG_CACHELINE_SIZE; + } + + start = KSEG0; + end = start + CFG_ICACHE_SIZE; + while(start < end) { + cache_unroll(start,Index_Invalidate_I); + start += CFG_CACHELINE_SIZE; + } +} diff --git a/board/purple/sconsole.c b/board/purple/sconsole.c new file mode 100644 index 0000000..f52d50d --- /dev/null +++ b/board/purple/sconsole.c @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include "sconsole.h" + +void (*sconsole_putc) (char) = 0; +void (*sconsole_puts) (const char *) = 0; +int (*sconsole_getc) (void) = 0; +int (*sconsole_tstc) (void) = 0; +void (*sconsole_setbrg) (void) = 0; + +int serial_init (void) +{ + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + + sb->pos = 0; + sb->size = 0; + sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t); + + return (0); +} + +void serial_putc (char c) +{ + if (sconsole_putc) { + (*sconsole_putc) (c); + } else { + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + + if (c) { + sb->data[sb->pos++] = c; + if (sb->pos == sb->max_size) { + sb->pos = 0; + } + if (sb->size < sb->max_size) { + sb->size++; + } + } + } +} + +void serial_puts (const char *s) +{ + if (sconsole_puts) { + (*sconsole_puts) (s); + } else { + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + + while (*s) { + sb->data[sb->pos++] = *s++; + if (sb->pos == sb->max_size) { + sb->pos = 0; + } + if (sb->size < sb->max_size) { + sb->size++; + } + } + } +} + +int serial_getc (void) +{ + if (sconsole_getc) { + return (*sconsole_getc) (); + } else { + return 0; + } +} + +int serial_tstc (void) +{ + if (sconsole_tstc) { + return (*sconsole_tstc) (); + } else { + return 0; + } +} + +void serial_setbrg (void) +{ + if (sconsole_setbrg) { + (*sconsole_setbrg) (); + } +} + +void sconsole_flush (void) +{ + if (sconsole_putc) { + sconsole_buffer_t *sb = SCONSOLE_BUFFER; + unsigned int end = sb->pos < sb->size + ? sb->pos + sb->max_size - sb->size + : sb->pos - sb->size; + + while (sb->size) { + (*sconsole_putc) (sb->data[end++]); + if (end == sb->max_size) { + end = 0; + } + sb->size--; + } + } +} diff --git a/board/purple/sconsole.h b/board/purple/sconsole.h new file mode 100644 index 0000000..d441f37 --- /dev/null +++ b/board/purple/sconsole.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SCONSOLE_H_ +#define _SCONSOLE_H_ + +#include + +typedef struct sconsole_buffer_s +{ + unsigned long size; + unsigned long max_size; + unsigned long pos; + char data [1]; +} sconsole_buffer_t; + +#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR) + +extern void (* sconsole_putc) (char); +extern void (* sconsole_puts) (const char *); +extern int (* sconsole_getc) (void); +extern int (* sconsole_tstc) (void); +extern void (* sconsole_setbrg) (void); + +extern void sconsole_flush (void); + +#endif diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds new file mode 100644 index 0000000..1bdac1f --- /dev/null +++ b/board/purple/u-boot.lds @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/mips/start.o (.text) + board/purple/lowlevel_init.o (.text) + cpu/mips/cache.o (.text) + common/main.o (.text) + common/dlmalloc.o (.text) + common/cmd_boot.o (.text) + lib_generic/zlib.o (.text) + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile new file mode 100644 index 0000000..b5f352a --- /dev/null +++ b/board/pxa255_idp/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := pxa_idp.o +SOBJS := memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/pxa255_idp/README b/board/pxa255_idp/README new file mode 100644 index 0000000..0cc2f2a --- /dev/null +++ b/board/pxa255_idp/README @@ -0,0 +1,11 @@ +Tested: + +- MMC +- Ethernet +- BL console (on serial port connector J5) +- flash support + +Todo: + +- display support +- PCMCIA support diff --git a/board/pxa255_idp/config.mk b/board/pxa255_idp/config.mk new file mode 100644 index 0000000..d2a2040 --- /dev/null +++ b/board/pxa255_idp/config.mk @@ -0,0 +1,3 @@ +#TEXT_BASE = 0xa1700000 +TEXT_BASE = 0xa3000000 +#TEXT_BASE = 0 diff --git a/board/pxa255_idp/idp_notes.txt b/board/pxa255_idp/idp_notes.txt new file mode 100644 index 0000000..4746748 --- /dev/null +++ b/board/pxa255_idp/idp_notes.txt @@ -0,0 +1,46 @@ +Notes on the Vibren PXA255 IDP. + +Chip select usage: + +CS0 - flash +CS1 - alt flash (Mdoc or main flash) +CS2 - high speed expansion bus +CS3 - Media Q, low speed exp bus +CS4 - low speed exp bus +CS5 - low speed exp bus + - IDE: offset 0x03000000 (abs: 0x17000000) + - Eth: offset 0x03400000 (abs: 0x17400000) + - core voltage latch: offset 0x03800000 (abs: 0x17800000) + - CPLD: offset 0x03C00000 (abs: 0x17C00000) + +PCMCIA Power control + +MAX1602EE w/ code pulled high (Cirrus code) +vx = 5v +vy = 3v + + Bit pattern + PWR 3,2,1,0 +vcc vpp A1VCC A0VCC A1VPP A0VPP +===================================================== +0 0 0 0 0 0 0x0 +3 (vy) 0 1 0 1 1 0xB +3 (vy) 3 (vy) 1 0 0 1 0x9 +3 (vy) 12(12in) 1 0 1 0 0xA +5 (vx) 0 0 1 1 1 0x7 +5 (vx) 5 (vx) 0 1 0 1 0x5 +5 (vx 12(12in) 0 1 1 0 0x6 + +Display power sequencing: + +- VDD applied +- within 1sec, activate scanning signals +- wait at least 50mS - scanning signals must be active before activating DISP + +Signal mapping: +Schematic LV8V31 signal name +========================================= +LCD_ENAVLCD DISP +LCD_PWR Applies VDD to board + +Both of the above signals are controlled by the CPLD diff --git a/board/pxa255_idp/memsetup.S b/board/pxa255_idp/memsetup.S new file mode 100644 index 0000000..7e485a2 --- /dev/null +++ b/board/pxa255_idp/memsetup.S @@ -0,0 +1,496 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/memsetup.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + +/* + * Memory setup + */ +.globl memsetup +memsetup: + + mov r10, lr + +#ifdef DEBUG_BLINK_ENABLE + /* 3rd blink */ + bl blink +#endif + + /* Set up GPIO pins first ----------------------------------------- */ + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + +#ifdef DEBUG_BLINK_ENABLE + /* 4th debug blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + +#ifdef DEBUG_BLINK_ENABLE + /* 5th blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + /* set MDREFR according to user define with exception of a few bits */ + + ldr r4, =CFG_MDREFR_VAL + orr r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4b: de-assert MDREFR:SLFRSH. */ + + bic r4, r4, #(MDREFR_SLFRSH) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ + + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ +#if 0 + /* FIXME turn on serial ports */ + /* look into moving this to board_init() */ + ldr r2, =(PXA_CS5_PHYS + 0x03C0002c) + mov r3, #0x13 + str r3, [r2] +#endif + +#ifdef DEBUG_BLINK_ENABLE + /* 6th blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + /* (hard-coding at 398.12MHz for now). */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ +#if 0 + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + /* default value in case no valid rotary switch setting is found */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + +#endif + +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size */ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + + /* FIXME */ + +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End memsetup */ + /* ---------------------------------------------------------------- */ + +#ifdef DEBUG_BLINK_ENABLE + /* 7th blink */ + bl blink +#endif + +endmemsetup: + + mov pc, r10 + + +#ifdef DEBUG_BLINK_ENABLE + +/* debug LED code */ + +/* delay about 200ms */ +delay: + + /* reset OSCR to 0 */ + ldr r8, =OSCR + mov r9, #0 + str r9, [r8] + + /* make sure new value has stuck */ +1: + ldr r8, =OSCR + ldr r9, [r8] + mov r8, #0x10000 + cmp r9, r8 + bgt 1b + + /* now, wait for delay to expire */ +1: + ldr r8, =OSCR + ldr r9, [r8] + mov r8, #0xd4000 + cmp r8, r9 + bgt 1b + + mov pc, lr + +/* blink code -- trashes r7, r8, r9 */ + +.globl blink +blink: + + mov r7, lr + + /* set GPIO10 as outout */ + ldr r8, =GPDR0 + ldr r9, [r8] + orr r9, r9, #(1<<10) + str r9, [r8] + + /* turn LED off */ + mov r9, #(1<<10) + ldr r8, =GPCR0 + str r9, [r8] + bl delay + + /* turn LED on */ + mov r9, #(1<<10) + ldr r8, =GPSR0 + str r9, [r8] + bl delay + + /* turn LED off */ + mov r9, #(1<<10) + ldr r8, =GPCR0 + str r9, [r8] + + mov pc, r7 + +#endif diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c new file mode 100644 index 0000000..d5b993a --- /dev/null +++ b/board/pxa255_idp/pxa_idp.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2004 + * BEC Systems + * Cliff Brake + * Support for Accelent/Vibren PXA255 IDP + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board */ + gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + /* turn on serial ports */ + *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13; + + /* set PWM for LCD */ + /* a value that works is 60Hz, 77% duty cycle */ + CKEN |= CKEN0_PWM0; + PWM_CTRL0 = 0x3f; + PWM_PERVAL0 = 0x3ff; + PWM_PWDUTY0 = 792; + + /* clear reset to AC97 codec */ + CKEN |= CKEN2_AC97; + GCR = GCR_COLD_RST; + + /* enable LCD backlight */ + /* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */ + + /* test display */ + /* lcd_puts("This is a test\nTest #2\n"); */ + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} + + +#ifdef DEBUG_BLINKC_ENABLE + +void delay_c(void) +{ + /* reset OSCR to 0 */ + OSCR = 0; + while(OSCR > 0x10000) + ; + + while(OSCR < 0xd4000) + ; +} + +void blink_c(void) +{ + int led_bit = (1<<10); + + GPDR0 = led_bit; + GPCR0 = led_bit; + delay_c(); + GPSR0 = led_bit; + delay_c(); + GPCR0 = led_bit; +} + +int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("IDPCMD started\n"); + return 0; +} + +U_BOOT_CMD(idpcmd, CFG_MAXARGS, 0, do_idpcmd, + "idpcmd - custom IDP command\n", + "no args at this time\n" +); + +#endif diff --git a/board/pxa255_idp/pxa_reg_calcs.out b/board/pxa255_idp/pxa_reg_calcs.out new file mode 100644 index 0000000..bda9946 --- /dev/null +++ b/board/pxa255_idp/pxa_reg_calcs.out @@ -0,0 +1,119 @@ +gafr0_l: 0x80001005 +gafr0_u: 0xa5128012 +gafr1_l: 0x699a9558 +gafr1_u: 0xaaa5aa6a +gafr2_l: 0xaaaaaaaa +gafr2_u: 0x2 +gpcr0: 0x1800400 +gpcr1: 0x0 +gpcr2: 0x0 +gpdr0: 0xc1818440 +gpdr1: 0xfcffab82 +gpdr2: 0x1ffff +gpsr0: 0x8000 +gpsr1: 0x3f0002 +gpsr2: 0x1c000 + + +#define CFG_GAFR0_L_VAL 0x80001005 +#define CFG_GAFR0_U_VAL 0xa5128012 +#define CFG_GAFR1_L_VAL 0x699a9558 +#define CFG_GAFR1_U_VAL 0xaaa5aa6a +#define CFG_GAFR2_L_VAL 0xaaaaaaaa +#define CFG_GAFR2_U_VAL 0x2 +#define CFG_GPCR0_VAL 0x1800400 +#define CFG_GPCR1_VAL 0x0 +#define CFG_GPCR2_VAL 0x0 +#define CFG_GPDR0_VAL 0xc1818440 +#define CFG_GPDR1_VAL 0xfcffab82 +#define CFG_GPDR2_VAL 0x1ffff +#define CFG_GPSR0_VAL 0x8000 +#define CFG_GPSR1_VAL 0x3f0002 +#define CFG_GPSR2_VAL 0x1c000 + + +GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET# +GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET# +GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA +GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ# +GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH +GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH# +GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK +GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD# +GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD# +GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD# +GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED +GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK +GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK +GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT +GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ +GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1# +GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0 +GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB +GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY +GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O# +GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0 +GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI +GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O# +GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK +GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM +GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD +GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD +GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK +GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK +GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0 +GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT +GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC +GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1 +GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5# +GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD +GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS +GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD +GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR +GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI +GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD +GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR +GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS +GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD +GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD +GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS +GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS +GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD +GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD +GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE# +GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE# +GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR# +GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW# +GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1# +GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2# +GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL +GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG# +GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT# +GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16# +GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0 +GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1 +GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2 +GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3 +GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4 +GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5 +GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6 +GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7 +GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8 +GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9 +GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10 +GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11 +GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12 +GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13 +GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14 +GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15 +GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK +GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK +GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK +GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS +GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2# +GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3# +GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4# +GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc= +GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc= +GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc= +GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc= diff --git a/board/pxa255_idp/pxa_reg_calcs.py b/board/pxa255_idp/pxa_reg_calcs.py new file mode 100644 index 0000000..c4bcb4b --- /dev/null +++ b/board/pxa255_idp/pxa_reg_calcs.py @@ -0,0 +1,311 @@ +#!/usr/bin/python + +# (C) Copyright 2004 +# BEC Systems +# Cliff Brake + +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# calculations for PXA255 registers + +class gpio: + dir = '0' + set = '0' + clr = '0' + alt = '0' + desc = '' + + def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''): + self.dir = dir + self.set = set + self.clr = clr + self.alt = alt + self.desc = desc + + +# the following is a dictionary of all GPIOs in the system +# the key is the GPIO number + + +pxa255_alt_func = { + 0: ['gpio', 'none', 'none', 'none'], + 1: ['gpio', 'gpio reset', 'none', 'none'], + 2: ['gpio', 'none', 'none', 'none'], + 3: ['gpio', 'none', 'none', 'none'], + 4: ['gpio', 'none', 'none', 'none'], + 5: ['gpio', 'none', 'none', 'none'], + 6: ['gpio', 'MMC clk', 'none', 'none'], + 7: ['gpio', '48MHz clock', 'none', 'none'], + 8: ['gpio', 'MMC CS0', 'none', 'none'], + 9: ['gpio', 'MMC CS1', 'none', 'none'], + 10: ['gpio', 'RTC Clock', 'none', 'none'], + 11: ['gpio', '3.6MHz', 'none', 'none'], + 12: ['gpio', '32KHz', 'none', 'none'], + 13: ['gpio', 'none', 'MBGNT', 'none'], + 14: ['gpio', 'MBREQ', 'none', 'none'], + 15: ['gpio', 'none', 'nCS_1', 'none'], + 16: ['gpio', 'none', 'PWM0', 'none'], + 17: ['gpio', 'none', 'PWM1', 'none'], + 18: ['gpio', 'RDY', 'none', 'none'], + 19: ['gpio', 'DREQ[1]', 'none', 'none'], + 20: ['gpio', 'DREQ[0]', 'none', 'none'], + 21: ['gpio', 'none', 'none', 'none'], + 22: ['gpio', 'none', 'none', 'none'], + 23: ['gpio', 'none', 'SSP SCLK', 'none'], + 24: ['gpio', 'none', 'SSP SFRM', 'none'], + 25: ['gpio', 'none', 'SSP TXD', 'none'], + 26: ['gpio', 'SSP RXD', 'none', 'none'], + 27: ['gpio', 'SSP EXTCLK', 'none', 'none'], + 28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'], + 29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'], + 30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'], + 31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'], + 32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'], + 33: ['gpio', 'none', 'nCS_5', 'none'], + 34: ['gpio', 'FF RXD', 'MMC CS0', 'none'], + 35: ['gpio', 'FF CTS', 'none', 'none'], + 36: ['gpio', 'FF DCD', 'none', 'none'], + 37: ['gpio', 'FF DSR', 'none', 'none'], + 38: ['gpio', 'FF RI', 'none', 'none'], + 39: ['gpio', 'MMC CS1', 'FF TXD', 'none'], + 40: ['gpio', 'none', 'FF DTR', 'none'], + 41: ['gpio', 'none', 'FF RTS', 'none'], + 42: ['gpio', 'BT RXD', 'none', 'HW RXD'], + 43: ['gpio', 'none', 'BT TXD', 'HW TXD'], + 44: ['gpio', 'BT CTS', 'none', 'HW CTS'], + 45: ['gpio', 'none', 'BT RTS', 'HW RTS'], + 46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'], + 47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'], + 48: ['gpio', 'HW TXD', 'nPOE', 'none'], + 49: ['gpio', 'HW RXD', 'nPWE', 'none'], + 50: ['gpio', 'HW CTS', 'nPIOR', 'none'], + 51: ['gpio', 'nPIOW', 'HW RTS', 'none'], + 52: ['gpio', 'none', 'nPCE[1]', 'none'], + 53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'], + 54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'], + 55: ['gpio', 'none', 'nPREG', 'none'], + 56: ['gpio', 'nPWAIT', 'none', 'none'], + 57: ['gpio', 'nIOIS16', 'none', 'none'], + 58: ['gpio', 'none', 'LDD[0]', 'none'], + 59: ['gpio', 'none', 'LDD[1]', 'none'], + 60: ['gpio', 'none', 'LDD[2]', 'none'], + 61: ['gpio', 'none', 'LDD[3]', 'none'], + 62: ['gpio', 'none', 'LDD[4]', 'none'], + 63: ['gpio', 'none', 'LDD[5]', 'none'], + 64: ['gpio', 'none', 'LDD[6]', 'none'], + 65: ['gpio', 'none', 'LDD[7]', 'none'], + 66: ['gpio', 'MBREQ', 'LDD[8]', 'none'], + 67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'], + 68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'], + 69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'], + 70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'], + 71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'], + 72: ['gpio', '32 KHz', 'LDD[14]', 'none'], + 73: ['gpio', 'MBGNT', 'LDD[15]', 'none'], + 74: ['gpio', 'none', 'LCD_FCLK', 'none'], + 75: ['gpio', 'none', 'LCD_LCLK', 'none'], + 76: ['gpio', 'none', 'LCD_PCLK', 'none'], + 77: ['gpio', 'none', 'LCD_ACBIAS', 'none'], + 78: ['gpio', 'none', 'nCS_2', 'none'], + 79: ['gpio', 'none', 'nCS_3', 'none'], + 80: ['gpio', 'none', 'nCS_4', 'none'], + 81: ['gpio', 'NSSPSCLK', 'none', 'none'], + 82: ['gpio', 'NSSPSFRM', 'none', 'none'], + 83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'], + 84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'], +} + + +#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''): + +gpio_list = [] + +for i in range(0,85): + gpio_list.append(gpio()) + +#chip select GPIOs +gpio_list[18] = gpio(0, 0, 0, 1, 'RDY') +gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#') +gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#') +gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#') +gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#') +gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#') +gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#') +gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI') +gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#') +gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0') +gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0') +gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB') +gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0') + +# PCMCIA stuff +gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#') +gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#') +gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#') +gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL') +gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#') +gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#') +gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#') +gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#') +gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#') +gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#') + +# SSP port +gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD') +gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD') +gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM') +gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK') +gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK') + +# audio codec +gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1') +gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC') +gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT') +gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0') +gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK') + +# serial ports +gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD') +gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD') +gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS') +gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS') +gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR') +gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR') +gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI') +gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD') + +gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD') +gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD') +gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS') +gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS') + +gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD') +gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD') + +# misc GPIO signals +gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ') +gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT') +gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK') +gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK') +gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED') +gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#') +gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#') +gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#') +gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK') +gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#') +gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH') +gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#') +gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA') +gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#') +gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#') + +# LCD GPIOs +gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0') +gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1') +gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2') +gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3') +gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4') +gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5') +gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6') +gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7') +gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8') +gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9') +gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10') +gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11') +gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12') +gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13') +gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14') +gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15') +gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK') +gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK') +gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK') +gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS') + +# calculate registers +pxa_regs = { + 'gpdr0':0, 'gpdr1':0, 'gpdr2':0, + 'gpsr0':0, 'gpsr1':0, 'gpsr2':0, + 'gpcr0':0, 'gpcr1':0, 'gpcr2':0, + 'gafr0_l':0, 'gafr0_u':0, + 'gafr1_l':0, 'gafr1_u':0, + 'gafr2_l':0, 'gafr2_u':0, +} + +# U-boot define names +uboot_reg_names = { + 'gpdr0':'CFG_GPDR0_VAL', 'gpdr1':'CFG_GPDR1_VAL', 'gpdr2':'CFG_GPDR2_VAL', + 'gpsr0':'CFG_GPSR0_VAL', 'gpsr1':'CFG_GPSR1_VAL', 'gpsr2':'CFG_GPSR2_VAL', + 'gpcr0':'CFG_GPCR0_VAL', 'gpcr1':'CFG_GPCR1_VAL', 'gpcr2':'CFG_GPCR2_VAL', + 'gafr0_l':'CFG_GAFR0_L_VAL', 'gafr0_u':'CFG_GAFR0_U_VAL', + 'gafr1_l':'CFG_GAFR1_L_VAL', 'gafr1_u':'CFG_GAFR1_U_VAL', + 'gafr2_l':'CFG_GAFR2_L_VAL', 'gafr2_u':'CFG_GAFR2_U_VAL', +} + +# bit mappings + +bit_mappings = [ + +{ 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} }, +{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} }, +{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} }, +{ 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} }, +{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} }, +{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} }, +{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} }, +{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} }, +{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} }, + +] + +def stuff_bits(bit_mapping, gpio_list): + gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1]) + + for gpio in gpios: + for reg in bit_mapping['regs'].keys(): + value = eval( 'gpio_list[gpio].%s' % (reg) ) + if ( value ): + # we have a high bit + bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift'] + bit = value << (bit_shift) + pxa_regs[bit_mapping['regs'][reg]] |= bit + +for i in bit_mappings: + stuff_bits(i, gpio_list) + +# now print out all regs +registers = pxa_regs.keys() +registers.sort() +for reg in registers: + print '%s: 0x%x' % (reg, pxa_regs[reg]) + +# print define to past right into U-Boot source code + +print +print + +for reg in registers: + print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg]) + +# print all GPIOS +print +print + +for i in range(len(gpio_list)): + gpio_i = gpio_list[i] + alt_func_desc = pxa255_alt_func[i][gpio_i.alt] + print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc) + + diff --git a/board/pxa255_idp/u-boot.lds b/board/pxa255_idp/u-boot.lds new file mode 100644 index 0000000..20ce108 --- /dev/null +++ b/board/pxa255_idp/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/quantum/Makefile b/board/quantum/Makefile new file mode 100644 index 0000000..e50f5ff --- /dev/null +++ b/board/quantum/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o fpga.o + + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/quantum/config.mk b/board/quantum/config.mk new file mode 100644 index 0000000..7cb374e --- /dev/null +++ b/board/quantum/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# RMU boards +# + +TEXT_BASE = 0xfff00000 diff --git a/board/quantum/fpga.c b/board/quantum/fpga.c new file mode 100644 index 0000000..75c2658 --- /dev/null +++ b/board/quantum/fpga.c @@ -0,0 +1,263 @@ +/* + * (C) Copyright 2001-2003 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* The DEBUG define must be before common to enable debugging */ +#undef DEBUG +#include +#include +#include +#include "fpga.h" +/* ------------------------------------------------------------------------- */ + +#define MAX_ONES 226 + +/* MPC850 port D */ +#define PD(bit) (1 << (15 - (bit))) +# define FPGA_INIT PD(11) /* FPGA init pin (ppc input) */ +# define FPGA_PRG PD(12) /* FPGA program pin (ppc output) */ +# define FPGA_CLK PD(13) /* FPGA clk pin (ppc output) */ +# define FPGA_DATA PD(14) /* FPGA data pin (ppc output) */ +# define FPGA_DONE PD(15) /* FPGA done pin (ppc input) */ + + +/* DDR 0 - input, 1 - output */ +#define FPGA_INIT_PDDIR FPGA_PRG | FPGA_CLK | FPGA_DATA /* just set outputs */ + + +#define SET_FPGA(data) immr->im_ioport.iop_pddat = (data) +#define GET_FPGA immr->im_ioport.iop_pddat + +#define FPGA_WRITE_1 { \ + SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ + SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ + +#define FPGA_WRITE_0 { \ + SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ + SET_FPGA(FPGA_PRG); /* set data to 0 */ \ + SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \ + SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ + + +int fpga_boot (unsigned char *fpgadata, int size) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + int i, index, len; + int count; + +#ifdef CFG_FPGA_SPARTAN2 + int j; + unsigned char data; +#else + unsigned char b; + int bit; +#endif + + debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size); + + /* display infos on fpgaimage */ + printf ("FPGA:"); + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf (" %s", &(fpgadata[index + 1])); + index += len + 3; + } + printf ("\n"); + + + index = 0; + +#ifdef CFG_FPGA_SPARTAN2 + /* search for preamble 0xFFFFFFFF */ + while (1) { + if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) + && (fpgadata[index + 2] == 0xff) + && (fpgadata[index + 3] == 0xff)) + break; /* preamble found */ + else + index++; + } +#else + /* search for preamble 0xFF2X */ + for (index = 0; index < size - 1; index++) { + if ((fpgadata[index] == 0xff) + && ((fpgadata[index + 1] & 0xf0) == 0x30)) + break; + } + index += 2; +#endif + + debug ("FPGA: configdata starts at position 0x%x\n", index); + debug ("FPGA: length of fpga-data %d\n", size - index); + + /* + * Setup port pins for fpga programming + */ + immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR; + + debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); + debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); + + /* + * Init fpga by asserting and deasserting PROGRAM* + */ + SET_FPGA (FPGA_CLK | FPGA_DATA); + + /* Wait for FPGA init line low */ + count = 0; + while (GET_FPGA & FPGA_INIT) { + udelay (1000); /* wait 1ms */ + /* Check for timeout - 100us max, so use 3ms */ + if (count++ > 3) { + debug ("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_LOW; + } + } + + debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); + debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); + + /* deassert PROGRAM* */ + SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); + + /* Wait for FPGA end of init period . */ + count = 0; + while (!(GET_FPGA & FPGA_INIT)) { + udelay (1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) { + debug ("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_HIGH; + } + } + + debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); + debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); + + debug ("write configuration data into fpga\n"); + /* write configuration-data into fpga... */ + +#ifdef CFG_FPGA_SPARTAN2 + /* + * Load uncompressed image into fpga + */ + for (i = index; i < size; i++) { +#ifdef CFG_FPGA_PROG_FEEDBACK + if ((i % 1024) == 0) + printf ("%6d out of %6d\r", i, size); /* let them know we are alive */ +#endif + + data = fpgadata[i]; + for (j = 0; j < 8; j++) { + if ((data & 0x80) == 0x80) { + FPGA_WRITE_1; + } else { + FPGA_WRITE_0; + } + data <<= 1; + } + } + /* add some 0xff to the end of the file */ + for (i = 0; i < 8; i++) { + data = 0xff; + for (j = 0; j < 8; j++) { + if ((data & 0x80) == 0x80) { + FPGA_WRITE_1; + } else { + FPGA_WRITE_0; + } + data <<= 1; + } + } +#else + /* send 0xff 0x20 */ + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_1; + FPGA_WRITE_0; + FPGA_WRITE_0; + FPGA_WRITE_1; + FPGA_WRITE_0; + FPGA_WRITE_0; + FPGA_WRITE_0; + FPGA_WRITE_0; + FPGA_WRITE_0; + + /* + ** Bit_DeCompression + ** Code 1 .. maxOnes : n '1's followed by '0' + ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' + ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' + ** 255 : '1' + */ + + for (i = index; i < size; i++) { + b = fpgadata[i]; + if ((b >= 1) && (b <= MAX_ONES)) { + for (bit = 0; bit < b; bit++) { + FPGA_WRITE_1; + } + FPGA_WRITE_0; + } else if (b == (MAX_ONES + 1)) { + for (bit = 1; bit < b; bit++) { + FPGA_WRITE_1; + } + } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { + for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { + FPGA_WRITE_0; + } + FPGA_WRITE_1; + } else if (b == 255) { + FPGA_WRITE_1; + } + } +#endif + debug ("\n\n"); + debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); + debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); + + /* + * Check if fpga's DONE signal - correctly booted ? + */ + + /* Wait for FPGA end of programming period . */ + count = 0; + while (!(GET_FPGA & FPGA_DONE)) { + udelay (1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) { + debug ("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_DONE; + } + } + + debug ("FPGA: Booting successful!\n"); + return 0; +} diff --git a/board/quantum/fpga.h b/board/quantum/fpga.h new file mode 100644 index 0000000..2ef45e5 --- /dev/null +++ b/board/quantum/fpga.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Virtex2 FPGA configuration support for the QUANTUM computer + */ +int fpga_boot(unsigned char *fpgadata, int size); + +#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ +#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ +#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ +/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c new file mode 100644 index 0000000..2861bc3 --- /dev/null +++ b/board/quantum/quantum.c @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include "fpga.h" + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); +unsigned long flash_init (void); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFCC25 + +const uint sdram_table[] = { + /* + * Single Read. (Offset 00h in UPMA RAM) + */ + 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Read. (Offset 08h in UPMA RAM) + */ + 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, + 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18h in UPMA RAM) + */ + 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20h in UPMA RAM) + */ + 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, + 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Refresh. (Offset 30h in UPMA RAM) + * (Initialization code at 0x36) + */ + 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, + 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4, + + /* + * Exception. (Offset 3Ch in UPMA RAM) + */ + 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + puts ("Board QUANTUM, Serial No: "); + + for (; s && *s; ++s) { + if (*s == ' ') + break; + putc (*s); + } + putc ('\n'); + return (0); /* success */ +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size9; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* Refresh clock prescalar */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000088; + + /* Map controller banks 1 to the SDRAM bank */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* Check Bank 0 Memory Size, + * 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, + SDRAM_MAX_SIZE); + /* + * Final mapping: + */ + memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + udelay (1000); + + return (size9); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile ulong *addr; + ulong cnt, val, size; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + /* Restore the original data before leaving the function. + */ + *addr = save[i]; + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = (volatile ulong *) base + cnt; + *addr = save[--i]; + } + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if (val != (~cnt)) { + size = cnt * sizeof (long); + /* Restore the original data before returning + */ + for (cnt <<= 1; cnt <= maxsize / sizeof (long); + cnt <<= 1) { + addr = (volatile ulong *) base + cnt; + *addr = save[--i]; + } + return (size); + } + } + return (maxsize); +} + +/* + * Miscellaneous intialization + */ +int misc_init_r (void) +{ + char *fpga_data_str = getenv ("fpgadata"); + char *fpga_size_str = getenv ("fpgasize"); + void *fpga_data; + int fpga_size; + int status; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + int flash_size; + + /* Remap FLASH according to real size */ + flash_size = flash_init (); + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + if (fpga_data_str && fpga_size_str) { + fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16); + fpga_size = simple_strtoul (fpga_size_str, NULL, 10); + + status = fpga_boot (fpga_data, fpga_size); + if (status != 0) { + printf ("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf ("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + } + } + return 0; +} diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds new file mode 100644 index 0000000..049f990 --- /dev/null +++ b/board/quantum/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) +/* XXX ? + . = env_offset; +*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug new file mode 100644 index 0000000..894b9bd --- /dev/null +++ b/board/quantum/u-boot.lds.debug @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/r360mpi/Makefile b/board/r360mpi/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/r360mpi/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/r360mpi/config.mk b/board/r360mpi/config.mk new file mode 100644 index 0000000..9d6080b --- /dev/null +++ b/board/r360mpi/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8xxL boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/r360mpi/flash.c b/board/r360mpi/flash.c new file mode 100644 index 0000000..9b42960 --- /dev/null +++ b/board/r360mpi/flash.c @@ -0,0 +1,484 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Protection Flags: + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000); + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: + printf ("28F320J3A\n"); + break; + case FLASH_28F640J3A: + printf ("28F640J3A\n"); + break; + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + FPW value; + + /* Make sure Block Lock Bits get cleared */ + addr[0] = (FPW) 0x00FF00FF; + addr[0] = (FPW) 0x00600060; + addr[0] = (FPW) 0x00D000D0; + addr[0] = (FPW) 0x00FF00FF; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + value = addr[0]; + + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value) { + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value) { + case (FPW) INTEL_ID_28F320J3A: + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (FPW) INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + + int i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, data)) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c new file mode 100644 index 0000000..ffb4c0e --- /dev/null +++ b/board/r360mpi/r360mpi.c @@ -0,0 +1,419 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include /* for strdup */ + + +/* + * Memory Controller Using + * + * CS0 - Flash memory (0x40000000) + * CS1 - FLASH memory (0x????????) + * CS2 - SDRAM (0x00000000) + * CS3 - + * CS4 - + * CS5 - + * CS6 - PCMCIA device + * CS7 - PCMCIA device + */ + +/* ------------------------------------------------------------------------- */ + +#define _not_used_ 0xffffffff + +const uint sdram_table[]= +{ + /* single read. (offset 0 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, + 0x1ff77c47, + + /* MRS initialization (offset 5) */ + + 0x1ff77c34, 0xefeabc34, 0x1fb57c35, + + /* burst read. (offset 8 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* single write. (offset 18 in upm RAM) */ + 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* burst write. (offset 20 in upm RAM) */ + 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, + 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* refresh. (offset 30 in upm RAM) */ + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* exception. (offset 3c in upm RAM) */ + 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: R360 MPI Board\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size8, size9; + long int size_b0 = 0; + unsigned long reg; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 2 to the SDRAM bank at + * preliminary address - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ + udelay (200); + memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ + udelay (200); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 2 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size_b0 = size9; +/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); +/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if ((size_b0 < 0x02000000)) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping + */ + + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + + udelay (10000); + +#ifdef CONFIG_CAN_DRIVER + /* Initialize OR3 / BR3 */ + memctl->memc_or3 = CFG_OR3_CAN; /* switch GPLB_5 to GPLA_5 */ + memctl->memc_br3 = CFG_BR3_CAN; + + /* Initialize MBMR */ + memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */ + + /* Initialize UPMB for CAN: single read */ + memctl->memc_mdr = 0xFFFFC004; + memctl->memc_mcr = 0x0100 | UPMB; + + memctl->memc_mdr = 0x0FFFD004; + memctl->memc_mcr = 0x0101 | UPMB; + + memctl->memc_mdr = 0x0FFFC000; + memctl->memc_mcr = 0x0102 | UPMB; + + memctl->memc_mdr = 0x3FFFC004; + memctl->memc_mcr = 0x0103 | UPMB; + + memctl->memc_mdr = 0xFFFFDC05; + memctl->memc_mcr = 0x0104 | UPMB; + + /* Initialize UPMB for CAN: single write */ + memctl->memc_mdr = 0xFFFCC004; + memctl->memc_mcr = 0x0118 | UPMB; + + memctl->memc_mdr = 0xCFFCD004; + memctl->memc_mcr = 0x0119 | UPMB; + + memctl->memc_mdr = 0x0FFCC000; + memctl->memc_mcr = 0x011A | UPMB; + + memctl->memc_mdr = 0x7FFCC004; + memctl->memc_mcr = 0x011B | UPMB; + + memctl->memc_mdr = 0xFFFDCC05; + memctl->memc_mcr = 0x011C | UPMB; +#endif + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, + long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +void r360_i2c_lcd_write (uchar data0, uchar data1) +{ + if (i2c_write (CFG_I2C_LCD_ADDR, data0, 1, &data1, 1)) { + printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1); + } +} + +/* ------------------------------------------------------------------------- */ + +/*----------------------------------------------------------------------- + * Keyboard Controller + */ + +/* Number of bytes returned from Keyboard Controller */ +#define KEYBD_KEY_MAX 16 /* maximum key number */ +#define KEYBD_DATALEN ((KEYBD_KEY_MAX + 7) / 8) /* normal key scan data */ + +static uchar *key_match (uchar *); + +int misc_init_r (void) +{ + char kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + char *str; + int i; + + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + i2c_read (CFG_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN); + + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + } + setenv ("keybd", keybd_env); + + str = strdup ((char *)key_match ((uchar *)keybd_env)); /* decode keys */ + +#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ + setenv ("preboot", str); /* set or delete definition */ +#endif /* CONFIG_PREBOOT */ + if (str != NULL) { + free (str); + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Check if pressed key(s) match magic sequence, + * and return the command string associated with that key(s). + * + * If no key press was decoded, NULL is returned. + * + * Note: the first character of the argument will be overwritten with + * the "magic charcter code" of the decoded key(s), or '\0'. + * + * + * Note: the string points to static environment data and must be + * saved before you call any function that modifies the environment. + */ +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +static uchar *key_match (uchar * kbd_str) +{ + uchar magic[sizeof (kbd_magic_prefix) + 1]; + uchar cmd_name[sizeof (kbd_command_prefix) + 1]; + uchar *str, *suffix; + uchar *kbd_magic_keys; + char *cmd; + + /* + * The following string defines the characters that can pe appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) { + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix = kbd_magic_keys; + *suffix || suffix == kbd_magic_keys; + ++suffix) { + sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix); + +#if 0 + printf ("### Check magic \"%s\"\n", magic); +#endif + + if ((str = (uchar *)getenv ((char *)magic)) != 0) { + +#if 0 + printf ("### Compare \"%s\" \"%s\"\n", + kbd_str, str); +#endif + if (strcmp ((char *)kbd_str, (char *)str) == 0) { + sprintf ((char *)cmd_name, "%s%c", + kbd_command_prefix, + *suffix); + + if ((cmd = getenv ((char *)cmd_name)) != 0) { +#if 0 + printf ("### Set PREBOOT to $(%s): \"%s\"\n", + cmd_name, cmd); +#endif + return ((uchar *)cmd); + } + } + } + } + } +#if 0 + printf ("### Delete PREBOOT\n"); +#endif + *kbd_str = '\0'; + return (NULL); +} +#endif /* CONFIG_PREBOOT */ + +/* Read Keyboard status */ +int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar keybd_env[2 * KEYBD_DATALEN + 1]; + int i; + + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read keys */ + i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN); + + puts ("Keys:"); + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]); + printf (" %02x", kbd_data[i]); + } + putc ('\n'); + setenv ("keybd", (char *)keybd_env); + return 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "kbd - read keyboard status\n", + NULL +); diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds new file mode 100644 index 0000000..8b06af7 --- /dev/null +++ b/board/r360mpi/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/cpu_init.o (.text) + cpu/mpc8xx/interrupts.o (.text) + cpu/mpc8xx/traps.o (.text) +/*** + . = env_offset; + common/environment.o (.text) +***/ + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); + . = ALIGN(128 * 1024); + .ppcenv : + { + common/environment.o (.ppcenv) + } +} diff --git a/board/rattler/Makefile b/board/rattler/Makefile new file mode 100644 index 0000000..52f0fd6 --- /dev/null +++ b/board/rattler/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2001-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/rattler/config.mk b/board/rattler/config.mk new file mode 100644 index 0000000..5fca8c7 --- /dev/null +++ b/board/rattler/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Yuli Barcohen, Arabella Software Ltd. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Rattler series boards by Analogue & Micro +# + +TEXT_BASE = 0xFE000000 diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c new file mode 100644 index 0000000..be7977d --- /dev/null +++ b/board/rattler/rattler.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen + * + * Support for Analogue&Micro Rattler boards family. + * Tested on Rattler8248. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */ + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */ + /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ + /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ + /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ + /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ + /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ + /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */ + /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + } +}; + +long int initdram(int board_type) +{ + long int msize = CFG_SDRAM_SIZE; + +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; + uchar c = 0xFF; + uint psdmr = CFG_PSDMR; + int i; + + immap->im_siu_conf.sc_ppc_acr = 0x02; + immap->im_siu_conf.sc_ppc_alrh = 0x30126745; + immap->im_siu_conf.sc_tescr1 = 0x00004000; + + memctl->memc_mptpr = CFG_MPTPR; + + /* Initialise 60x bus SDRAM */ + memctl->memc_psrt = CFG_PSRT; + memctl->memc_or1 = CFG_SDRAM_OR; + memctl->memc_br1 = CFG_SDRAM_BR; + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + for (i = 0; i < 8; i++) + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ + *ramaddr = c; +#endif /* !CFG_RAMBOOT */ + + /* Return total 60x bus SDRAM size */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40); + return 0; +} diff --git a/board/rattler/u-boot.lds b/board/rattler/u-boot.lds new file mode 100644 index 0000000..522e6da --- /dev/null +++ b/board/rattler/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/rbc823/Makefile b/board/rbc823/Makefile new file mode 100644 index 0000000..0121ddc --- /dev/null +++ b/board/rbc823/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o kbd.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/rbc823/config.mk b/board/rbc823/config.mk new file mode 100644 index 0000000..199ea3c --- /dev/null +++ b/board/rbc823/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# RBC823 boards +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c new file mode 100644 index 0000000..84ae5c1 --- /dev/null +++ b/board/rbc823/flash.c @@ -0,0 +1,469 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + /* Detect size */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + /* Setup offsets */ + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + size_b1 = 0 ; + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + * Fix this to support variable sector sizes +*/ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + /* set sector offsets for bottom boot block type */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) + { + puts ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) + { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) + { + case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size >> 20) { + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + } else { + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, + info->sector_count); + } + + puts (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) + { + if ((i % 5) == 0) + { + puts ("\n "); + } + + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + putc ('\n'); + return; +} +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + volatile unsigned char *caddr; + char value; + + caddr = (volatile unsigned char *)addr ; + + /* Write auto select command: read Manufacturer ID */ + +#if 0 + printf("Base address is: %08x\n", caddr); +#endif + + caddr[0x0555] = 0xAA; + caddr[0x02AA] = 0x55; + caddr[0x0555] = 0x90; + + value = caddr[0]; + +#if 0 + printf("Manufact ID: %02x\n", value); +#endif + switch (value) + { + case 0x01: /*AMD_MANUFACT*/ + info->flash_id = FLASH_MAN_AMD; + break; + + case 0x04: /*FUJ_MANUFACT*/ + info->flash_id = FLASH_MAN_FUJ; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + value = caddr[1]; /* device ID */ +#if 0 + printf("Device ID: %02x\n", value); +#endif + switch (value) + { + case AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512Kb */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + flash_get_offsets ((ulong)addr, &flash_info[0]); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) + { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + caddr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = caddr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) + { + caddr = (volatile unsigned char *)info->start[0]; + *caddr = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (volatile unsigned char *)(info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile unsigned char *)(info->start[l_sect]); + + while ((addr[0] & 0xFF) != 0xFF) + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned char *)info->start[0]; + + addr[0] = 0xF0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]), + *cdest,*cdata; + ulong start; + int flag, count = 4 ; + + cdest = (volatile unsigned char *)dest ; + cdata = (volatile unsigned char *)&data ; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + while(count--) + { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *cdest = *cdata; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*cdest ^ *cdata) & 0x80) + { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + cdata++ ; + cdest++ ; + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c new file mode 100644 index 0000000..c27929d --- /dev/null +++ b/board/rbc823/kbd.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Modified by Udi Finkelstein + * + * This file includes communication routines for SMC1 that can run even if + * SMC2 have already been initialized. + */ + +#include +#include +#include +#include +#include + +#define SMC_INDEX 0 +#define PROFF_SMC PROFF_SMC1 +#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 + +#define RBC823_KBD_BAUDRATE 38400 +#define CPM_KEYBOARD_BASE 0x1000 +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +void smc1_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + + /* Set up the baud rate generator. + * See 8xx_io/commproc.c for details. + * + * Wire BRG2 to SMC1, BRG1 to SMC2 + */ + + cp->cp_simode = 0x00001000; + + cp->cp_brgc2 = + (((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN; +} + +int smc1_init (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile smc_t *sp; + volatile smc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile cpm8xx_t *cp = &(im->im_cpm); + uint dpaddr; + + /* initialize pointers to SMC */ + + sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); + up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; + + /* Disable transmitter/receiver. + */ + sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); + + /* Enable SDMA. + */ + im->im_siu_conf.sc_sdcr = 1; + + /* clear error conditions */ +#ifdef CFG_SDSR + im->im_sdma.sdma_sdsr = CFG_SDSR; +#else + im->im_sdma.sdma_sdsr = 0x83; +#endif + + /* clear SDMA interrupt mask */ +#ifdef CFG_SDMR + im->im_sdma.sdma_sdmr = CFG_SDMR; +#else + im->im_sdma.sdma_sdmr = 0x00; +#endif + + /* Use Port B for SMC1 instead of other functions. + */ + cp->cp_pbpar |= 0x000000c0; + cp->cp_pbdir &= ~0x000000c0; + cp->cp_pbodr &= ~0x000000c0; + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + +#ifdef CFG_ALLOC_DPRAM + dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; +#else + dpaddr = CPM_KEYBOARD_BASE ; +#endif + + /* Allocate space for two buffer descriptors in the DP ram. + * For now, this address seems OK, but it may have to + * change with newer versions of the firmware. + * damm: allocating space after the two buffers for rx/tx data + */ + + rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; + rbdf->cbd_bufaddr = (uint) (rbdf+2); + rbdf->cbd_sc = 0; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; + tbdf->cbd_sc = 0; + + /* Set up the uart parameters in the parameter ram. + */ + up->smc_rbase = dpaddr; + up->smc_tbase = dpaddr+sizeof(cbd_t); + up->smc_rfcr = SMC_EB; + up->smc_tfcr = SMC_EB; + + /* Set UART mode, 8 bit, no parity, one stop. + * Enable receive and transmit. + */ + sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; + + /* Mask all interrupts and remove anything pending. + */ + sp->smc_smcm = 0; + sp->smc_smce = 0xff; + + /* Set up the baud rate generator. + */ + smc1_setbrg (); + + /* Make the first buffer the only buffer. + */ + tbdf->cbd_sc |= BD_SC_WRAP; + rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + + /* Single character receive. + */ + up->smc_mrblr = 1; + up->smc_maxidl = 0; + + /* Initialize Tx/Rx parameters. + */ + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. + */ + sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; + + return (0); +} + +void smc1_putc(const char c) +{ + volatile cbd_t *tbdf; + volatile char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + + up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; + + tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; + + /* Wait for last character to go. + */ + + buf = (char *)tbdf->cbd_bufaddr; + + *buf = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; + __asm__("eieio"); + + while (tbdf->cbd_sc & BD_SC_READY) { + WATCHDOG_RESET (); + __asm__("eieio"); + } +} + +int smc1_getc(void) +{ + volatile cbd_t *rbdf; + volatile unsigned char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + unsigned char c; + + up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; + + rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; + + /* Wait for character to show up. + */ + buf = (unsigned char *)rbdf->cbd_bufaddr; + + while (rbdf->cbd_sc & BD_SC_EMPTY) + WATCHDOG_RESET (); + + c = *buf; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return(c); +} + +int smc1_tstc(void) +{ + volatile cbd_t *rbdf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + + up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; + + rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; + + return(!(rbdf->cbd_sc & BD_SC_EMPTY)); +} + +/* search for keyboard and register it if found */ +int drv_keyboard_init(void) +{ + int error = 0; + device_t kbd_dev; + + if (0) { + /* register the keyboard */ + memset (&kbd_dev, 0, sizeof(device_t)); + strcpy(kbd_dev.name, "kbd"); + kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbd_dev.putc = NULL; + kbd_dev.puts = NULL; + kbd_dev.getc = smc1_getc; + kbd_dev.tstc = smc1_tstc; + error = device_register (&kbd_dev); + } else { + lcd_is_enabled = 0; + lcd_disable(); + } + return error; +} diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c new file mode 100644 index 0000000..9e60c2b --- /dev/null +++ b/board/rbc823/rbc823.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "mpc8xx.h" +#include + +extern int kbd_init(void); +extern int drv_kbd_init(void); + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x1FF7FC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +const uint static_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04, + 0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04, + 0xFFFFFC04, 0xFFFFFC05, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04, + 0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + * + * Test TQ ID string (TQM8xx...) + * If present, check for "L" type (no second DRAM bank), + * otherwise "L" type is assumed as default. + * + * Return 1 for "L" type, 0 else. + */ + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + if (!s || strncmp (s, "TQM8", 4)) { + printf ("### No HW ID - assuming RBC823\n"); + return (0); + } + + puts (s); + putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0, size8, size9; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * 1 Bank of 64Mbit x 2 devices + */ + memctl->memc_mptpr = CFG_MPTPR_1BK_4K; + memctl->memc_mar = 0x00000088; + + /* + * Map controller SDRAM bank 0 + */ + memctl->memc_or4 = CFG_OR4_PRELIM; + memctl->memc_br4 = CFG_BR4_PRELIM; + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + udelay (200); + + /* + * Perform SDRAM initializsation sequence + */ + memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X; + udelay (200); + memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */ + udelay (1); + memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; + udelay (200); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + udelay (1000); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /* 16: but should be: CFG_MPTPR_1BK_4K */ + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM, + SDRAM_MAX_SIZE); + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM, + SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size_b0 = size9; +/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); +/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if ((size_b0 < 0x02000000)) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* SDRAM Bank 0 is bigger - map first */ + + memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + udelay (10000); + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size (base, maxsize)); +} + +void doc_init (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + upmconfig (UPMB, (uint *) static_table, + sizeof (static_table) / sizeof (uint)); + memctl->memc_mbmr = MAMR_DSA_1_CYCL; + + doc_probe (FLASH_BASE1_PRELIM); +} diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds new file mode 100644 index 0000000..68ca856 --- /dev/null +++ b/board/rbc823/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/rmu/Makefile b/board/rmu/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/rmu/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/rmu/config.mk b/board/rmu/config.mk new file mode 100644 index 0000000..7cb374e --- /dev/null +++ b/board/rmu/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# RMU boards +# + +TEXT_BASE = 0xfff00000 diff --git a/board/rmu/flash.c b/board/rmu/flash.c new file mode 100644 index 0000000..0f2c327 --- /dev/null +++ b/board/rmu/flash.c @@ -0,0 +1,540 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0 ; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_br0, memctl->memc_or0); + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + debug ("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); + + /* Re-do sizing to get full correct info */ + + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + +#if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND) + debug ("Protect redundand environment: %08lx ... %08lx\n", + (ulong)CFG_ENV_ADDR_REDUND, + (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE - 1); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + debug ("## Final Flash bank size: %08lx\n", size_b0); + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00010000; + info->start[2] = base + 0x00018000; + info->start[3] = base + 0x00020000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + ((i-3) * 0x00040000) ; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00040000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0xAAA] = 0xAAAAAAAA ; + addr[0x555] = 0x55555555 ; + addr[0xAAA] = 0x90909090 ; + + value = addr[0] ; + + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value & 0x00FF00FF) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[2] ; /* device ID */ + + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value & 0x00FF00FF) { + case (AMD_ID_LV400T & 0x00FF00FF): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV400B & 0x00FF00FF): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800T & 0x00FF00FF): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV800B & 0x00FF00FF): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00400000; /*%%% Size doubled by yooth */ + break; /* => 4 MB */ + + case (AMD_ID_LV160T & 0x00FF00FF): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV160B & 0x00FF00FF): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00800000; + break; /* => 8 MB */ + case (AMD_ID_LV320T & 0x00FF00FF): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (AMD_ID_LV320B & 0x00FF00FF): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x01000000; + break; /* => 16 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00010000; + info->start[2] = base + 0x00018000; + info->start[3] = base + 0x00020000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + ((i-3) * 0x00040000) ; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00040000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[4] & 1 ; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0xF0F0F0F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0x80808080; + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long *)(info->start[sect]) ; + addr[0] = 0x30303030 ; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long *)(info->start[l_sect]); + while ((addr[0] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0xAAA] = 0xAAAAAAAA; + addr[0x555] = 0x55555555; + addr[0xAAA] = 0xA0A0A0A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c new file mode 100644 index 0000000..8cb03c7 --- /dev/null +++ b/board/rmu/rmu.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFCC25 + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 00h in UPMA RAM) + */ + 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Read. (Offset 08h in UPMA RAM) + */ + 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, + 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18h in UPMA RAM) + */ + 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20h in UPMA RAM) + */ + 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, + 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Refresh. (Offset 30h in UPMA RAM) + * (Initialization code at 0x36) + */ + 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, + 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4, + + /* + * Exception. (Offset 3Ch in UPMA RAM) + */ + 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: RMU\n") ; + return (0) ; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size9; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* Refresh clock prescalar */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000088; + + /* Map controller banks 1 to the SDRAM bank */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* Check Bank 0 Memory Size, + * 9 column mode + */ + + size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, + SDRAM_MAX_SIZE); + + /* + * Final mapping: + */ + + memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + udelay (1000); + + return (size9); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} diff --git a/board/rmu/u-boot.lds b/board/rmu/u-boot.lds new file mode 100644 index 0000000..049f990 --- /dev/null +++ b/board/rmu/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) +/* XXX ? + . = env_offset; +*/ + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/rmu/u-boot.lds.debug b/board/rmu/u-boot.lds.debug new file mode 100644 index 0000000..894b9bd --- /dev/null +++ b/board/rmu/u-boot.lds.debug @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile new file mode 100644 index 0000000..4535106 --- /dev/null +++ b/board/rpxsuper/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := rpxsuper.o flash.o mii_phy.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/rpxsuper/config.mk b/board/rpxsuper/config.mk new file mode 100644 index 0000000..4b8c5d3 --- /dev/null +++ b/board/rpxsuper/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MBX8xx boards +# + +TEXT_BASE = 0x80F00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c new file mode 100644 index 0000000..d80e778 --- /dev/null +++ b/board/rpxsuper/flash.c @@ -0,0 +1,434 @@ +/* + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AMD 29F080B devices + * Added support for 64bit and AMD 29DL323B + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define RD_SWP32(x) in_le32((volatile u32*)x) + +/*----------------------------------------------------------------------- + * Functions + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH0_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD "); + break; + case (FUJ_MANUFACT & FLASH_VENDMASK): + printf ("FUJITSU "); + break; + case (SST_MANUFACT & FLASH_VENDMASK): + printf ("SST "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_DL323B & FLASH_TYPEMASK): + printf("AM29DL323B (32 MBit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + vu_long vendor[2], devid[2]; + ulong base = (ulong)addr; + + /* Reset and Write auto select command: read Manufacturer ID */ + addr[0] = 0xf0f0f0f0; + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555] = 0x90909090; + addr[1] = 0xf0f0f0f0; + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + addr[2 * 0x0555 + 1] = 0x90909090; + udelay (1000); + + vendor[0] = RD_SWP32(&addr[0]); + vendor[1] = RD_SWP32(&addr[1]); + if (vendor[0] != vendor[1] || vendor[0] != AMD_MANUFACT) { + info->size = 0; + goto out; + } + + devid[0] = RD_SWP32(&addr[2]); + devid[1] = RD_SWP32(&addr[3]); + + if (devid[0] == AMD_ID_DL323B) { + /* + * we have 2 Banks + * Bank 1 (23 Sectors): 0-7=8kbyte, 8-22=64kbyte + * Bank 2 (48 Sectors): 23-70=64kbyte + */ + info->flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_DL323B & FLASH_TYPEMASK); + info->sector_count = 71; + info->size = 4 * (8 * 8 + 63 * 64) * 1024; + } + else { + info->size = 0; + goto out; + } + + /* set up sector start address table */ + for (i = 0; i < 8; i++) { + info->start[i] = base + (i * 0x8000); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x40000) + 8 * 0x8000 - 8 * 0x40000; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address */ + addr = (volatile unsigned long *)(info->start[i]); + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555] = 0x90909090; + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + addr[2 * 0x0555 + 1] = 0x90909090; + udelay (1000); + base = RD_SWP32(&addr[4]); + base |= RD_SWP32(&addr[5]); + info->protect[i] = base & 0x00010001 ? 1 : 0; + } + addr = (vu_long*)info->start[0]; + +out: + /* reset command */ + addr[0] = 0xf0f0f0f0; + addr[1] = 0xf0f0f0f0; + + return info->size; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555] = 0x80808080; + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + addr[2 * 0x0555 + 1] = 0x80808080; + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + udelay (100); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x30303030; + addr[1] = 0x30303030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ( (addr[0] & 0x80808080) != 0x80808080 || + (addr[1] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + addr[1] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if ((dest & 0x00000004) == 0) { + addr[2 * 0x0555] = 0xAAAAAAAA; + addr[2 * 0x02AA] = 0x55555555; + addr[2 * 0x0555] = 0xA0A0A0A0; + } + else { + addr[2 * 0x0555 + 1] = 0xAAAAAAAA; + addr[2 * 0x02AA + 1] = 0x55555555; + addr[2 * 0x0555 + 1] = 0xA0A0A0A0; + } + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c new file mode 100644 index 0000000..ef99aff --- /dev/null +++ b/board/rpxsuper/mii_phy.c @@ -0,0 +1,107 @@ +#include +#include +#include "rpxsuper.h" + +#define MII_MDIO 0x01 +#define MII_MDCK 0x02 +#define MII_MDIR 0x04 + +void +mii_discover_phy(void) +{ + int known; + unsigned short phy_reg; + unsigned long phy_id; + + known = 0; + printf("Discovering phy @ 0: "); + phy_id = mii_phy_read(2) << 16; + phy_id |= mii_phy_read(3); + if ((phy_id & 0xFFFFFC00) == 0x00137800) { + printf("Level One "); + if ((phy_id & 0x000003F0) == 0xE0) { + printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); + known = 1; + } + else printf("unknown type\n"); + } + else printf("unknown OUI = 0x%08lX\n", phy_id); + + phy_reg = mii_phy_read(1); + if (!(phy_reg & 0x0004)) printf("Link is down\n"); + if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); + if (phy_reg & 0x0002) printf("Jabber condition detected\n"); + if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); + + if (known) { + phy_reg = mii_phy_read(17); + if (phy_reg & 0x0400) + printf("Phy operating at %d MBit/s in %s-duplex mode\n", + phy_reg & 0x4000 ? 100 : 10, + phy_reg & 0x0200 ? "full" : "half"); + else + printf("bad link!!\n"); +/* +left off: no link, green 100MBit, yellow 10MBit +right off: no activity, green full-duplex, yellow half-duplex +*/ + mii_phy_write(20, 0x0452); + } +} + +unsigned short +mii_phy_read(unsigned short reg) +{ + int i; + unsigned short tmp, val = 0, adr = 0; + t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + + tmp = 0x6002 | (adr << 7) | (reg << 2); + regs->bcsr4 = 0xC3; + for (i = 0; i < 64; i++) { + regs->bcsr4 ^= MII_MDCK; + } + for (i = 0; i < 16; i++) { + regs->bcsr4 &= ~MII_MDCK; + if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; + else regs->bcsr4 &= ~MII_MDIO; + regs->bcsr4 |= MII_MDCK; + tmp <<= 1; + } + regs->bcsr4 |= MII_MDIR; + for (i = 0; i < 16; i++) { + val <<= 1; + regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); + if (regs->bcsr4 & MII_MDIO) val |= 1; + regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); + } + return val; +} + +void +mii_phy_write(unsigned short reg, unsigned short val) +{ + int i; + unsigned short tmp, adr = 0; + t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + + tmp = 0x5002 | (adr << 7) | (reg << 2); + regs->bcsr4 = 0xC3; + for (i = 0; i < 64; i++) { + regs->bcsr4 ^= MII_MDCK; + } + for (i = 0; i < 16; i++) { + regs->bcsr4 &= ~MII_MDCK; + if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; + else regs->bcsr4 &= ~MII_MDIO; + regs->bcsr4 |= MII_MDCK; + tmp <<= 1; + } + for (i = 0; i < 16; i++) { + regs->bcsr4 &= ~MII_MDCK; + if (val & 0x8000) regs->bcsr4 |= MII_MDIO; + else regs->bcsr4 &= ~MII_MDIO; + regs->bcsr4 |= MII_MDCK; + val <<= 1; + } +} diff --git a/board/rpxsuper/readme b/board/rpxsuper/readme new file mode 100644 index 0000000..21267bd --- /dev/null +++ b/board/rpxsuper/readme @@ -0,0 +1,30 @@ +Hi, + +so this is the port to the Embedded Planet RPX Super Board. + +ATTENTION +This code is only tested on the AY-Version, which is an early release with some +hardware bugs. The main problem is that this board uses the default Hard Reset +Configuration Word and not the 4 bytes located at start of FLASH because at +0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be +carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low +byte. + +The icache can only manually be enabled after reset. +The FLASH and main SDRAM is working with icache enabled. +The local SDRAM can only be used as data memory when icache is enabled. +If U-Boot runs in local SDRAM, TFTP does not work. +The functions in mii_phy.c are all working. Call mii_phy_discover() out of +eth_init() and solve the linker error. +I2C, RTC/NVRAM and PCMCIA are not working yet. + +TODO +The 32MB local SDRAM is working but not shown in the startup messages of +U-Boot. If you locate U-Boot or any other program to this area it won't run. +Turning the ichache off does not solve this problem. + +As I won't buy another RPX Super there might be some little work to do for you +getting this U-Boot port running on the final board. + + +frank.morauf@salzbrenner.com diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c new file mode 100644 index 0000000..b4331f1 --- /dev/null +++ b/board/rpxsuper/rpxsuper.c @@ -0,0 +1,305 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "rpxsuper.h" + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ + /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ + /* PA29 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ + /* PA28 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ + /* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ + /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ + /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ + /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ + /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ + /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ + /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Setup CS4 to enable the Board Control/Status registers. + * Otherwise the smcs won't work. +*/ +int board_early_init_f (void) +{ + volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + memctl->memc_br4 = CFG_BR4_PRELIM; + memctl->memc_or4 = CFG_OR4_PRELIM; + regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */ + regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */ + return 0; +} + +void +reset_phy(void) +{ + volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + regs->bcsr4 = 0xC3; +} + +/* + * Check Board Identity: + */ + +int checkboard(void) +{ + volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + printf ("Board: Embedded Planet RPX Super, Revision %d\n", + regs->bcsr0 >> 4); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0, *ramaddr; + ulong psdmr, lsdmr, bcr; + long size = 0; + int i; + + psdmr = CFG_PSDMR; + lsdmr = CFG_LSDMR; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + size = CFG_SDRAM0_SIZE; + bcr = immap->im_siu_conf.sc_bcr; + immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM); + + memctl->memc_mptpr = CFG_MPTPR; + + ramaddr = (uchar *)(CFG_SDRAM0_BASE); + memctl->memc_psrt = CFG_PSRT; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + + immap->im_siu_conf.sc_bcr = bcr; + +#ifndef CFG_RAMBOOT +/* size += CFG_SDRAM1_SIZE; */ + ramaddr = (uchar *)(CFG_SDRAM1_BASE); + memctl->memc_lsrt = CFG_LSRT; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; +#endif + + /* return total ram size */ + return (size * 1024 * 1024); +} diff --git a/board/rpxsuper/rpxsuper.h b/board/rpxsuper/rpxsuper.h new file mode 100644 index 0000000..af31060 --- /dev/null +++ b/board/rpxsuper/rpxsuper.h @@ -0,0 +1,25 @@ +#ifndef __RPX8260_H__ +#define __RPX8260_H__ + +typedef struct tt_rpx_regs +{ + volatile unsigned char bcsr0; + volatile unsigned char bcsr1; + volatile unsigned char bcsr2; + volatile unsigned char bcsr3; + volatile unsigned char bcsr4; + volatile unsigned char bcsr5; + volatile unsigned char bcsr6; + volatile unsigned char bcsr7; + volatile unsigned char bcsr8; + volatile unsigned char bcsr9; + volatile unsigned char bcsr10; + volatile unsigned char bcsr11; + volatile unsigned char bcsr12; + volatile unsigned char bcsr13; + volatile unsigned char bcsr14; + volatile unsigned char bcsr15; +} t_rpx_regs; +typedef t_rpx_regs* tp_rpx_regs; + +#endif diff --git a/board/rpxsuper/u-boot.lds b/board/rpxsuper/u-boot.lds new file mode 100644 index 0000000..9e623d0 --- /dev/null +++ b/board/rpxsuper/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile new file mode 100644 index 0000000..9934787 --- /dev/null +++ b/board/rsdproto/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := rsdproto.o flash.o +SOBJS := flash_asm.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/rsdproto/config.mk b/board/rsdproto/config.mk new file mode 100644 index 0000000..5844ec1 --- /dev/null +++ b/board/rsdproto/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MBX8xx boards +# + +TEXT_BASE = 0xff000000 +/*TEXT_BASE = 0x00200000 */ diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c new file mode 100644 index 0000000..5ad3218 --- /dev/null +++ b/board/rsdproto/flash.c @@ -0,0 +1,402 @@ +/* + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AM290[48]0B devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* flash hardware ids */ +#define VENDOR_AMD 0x0001 +#define AMD_29DL323C_B 0x2253 + +/* Define this to include autoselect sequence in flash_init(). Does NOT + * work when executing from flash itself, so this should be turned + * on only when debugging the RAM version. + */ +#undef WITH_AUTOSELECT + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if 1 +#define D(x) +#else +#define D(x) printf x +#endif + +/*----------------------------------------------------------------------- + * Functions + */ + +static unsigned char write_ull(flash_info_t *info, + unsigned long address, + volatile unsigned long long data); + +/* from flash_asm.S */ +extern void ull_write(unsigned long long volatile *address, + unsigned long long volatile *data); +extern void ull_read(unsigned long long volatile *address, + unsigned long long volatile *data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong addr; + +#ifdef WITH_AUTOSELECT + { + unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH; + unsigned long long f_command, vendor, device; + /* Perform Autoselect */ + f_command = 0x00AA00AA00AA00AAULL; + ull_write(&f_addr[0x555], &f_command); + f_command = 0x0055005500550055ULL; + ull_write(&f_addr[0x2AA], &f_command); + f_command = 0x0090009000900090ULL; + ull_write(&f_addr[0x555], &f_command); + ull_read(&f_addr[0], &vendor); + vendor &= 0xffff; + ull_read(&f_addr[1], &device); + device &= 0xffff; + f_command = 0x00F000F000F000F0ULL; + ull_write(&f_addr[0x555], &f_command); + if (vendor != VENDOR_AMD || device != AMD_29DL323C_B) + return 0; + } +#endif + + /* Init: no FLASHes known */ + for (i=0; i= PHYS_FLASH + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[1]); +#endif + + return flash_info[0].size + flash_info[1].size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id >> 16) { + case VENDOR_AMD: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case AMD_29DL323C_B: + printf ("AM29DL323CB (32 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect, l_sect; + ulong start; + unsigned long long volatile *f_addr; + unsigned long long volatile f_command; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + f_addr = (unsigned long long *)info->start[0]; + f_command = 0x00AA00AA00AA00AAULL; + ull_write(&f_addr[0x555], &f_command); + f_command = 0x0055005500550055ULL; + ull_write(&f_addr[0x2AA], &f_command); + f_command = 0x0080008000800080ULL; + ull_write(&f_addr[0x555], &f_command); + f_command = 0x00AA00AA00AA00AAULL; + ull_write(&f_addr[0x555], &f_command); + f_command = 0x0055005500550055ULL; + ull_write(&f_addr[0x2AA], &f_command); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (l_sect = -1, sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + f_addr = + (unsigned long long *)(info->start[sect]); + f_command = 0x0030003000300030ULL; + ull_write(f_addr, &f_command); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + do + { + if (get_timer(start) > CFG_FLASH_ERASE_TOUT) + { /* write reset command, command address is unimportant */ + /* this command turns the flash back to read mode */ + f_addr = + (unsigned long long *)(info->start[l_sect]); + f_command = 0x00F000F000F000F0ULL; + ull_write(f_addr, &f_command); + printf (" timeout\n"); + return 1; + } + } while(*f_addr != 0xFFFFFFFFFFFFFFFFULL); + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + unsigned long cp, wp; + unsigned long long data; + int i, l, rc; + + wp = (addr & ~7); /* get lower long long aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<8; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_ull(info, wp, data)) != 0) { + return rc; + } + wp += 4; + } + + /* + * handle long long aligned part + */ + while (cnt >= 8) { + data = 0; + for (i=0; i<8; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_ull(info, wp, data)) != 0) { + return rc; + } + wp += 8; + cnt -= 8; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<8; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return write_ull(info, wp, data); +} + +/*--------------------------------------------------------------------------- +* +* FUNCTION NAME: write_ull +* +* DESCRIPTION: writes 8 bytes to flash +* +* EXTERNAL EFFECT: nothing +* +* PARAMETERS: 32 bit long pointer to address, 64 bit long pointer to data +* +* RETURNS: 0 if OK, 1 if timeout, 4 if parameter error +*--------------------------------------------------------------------------*/ + +static unsigned char write_ull(flash_info_t *info, + unsigned long address, + volatile unsigned long long data) +{ + static unsigned long long f_command; + static unsigned long long *f_addr; + ulong start; + + /* address muss be 8-aligned! */ + if (address & 0x7) + return ERR_ALIGN; + + f_addr = (unsigned long long *)info->start[0]; + f_command = 0x00AA00AA00AA00AAULL; + ull_write(&f_addr[0x555], &f_command); + f_command = 0x0055005500550055ULL; + ull_write(&f_addr[0x2AA], &f_command); + f_command = 0x00A000A000A000A0ULL; + ull_write(&f_addr[0x555], &f_command); + + f_addr = (unsigned long long *)address; + f_command = data; + ull_write(f_addr, &f_command); + + start = get_timer (0); + do + { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + { + /* write reset command, command address is unimportant */ + /* this command turns the flash back to read mode */ + f_addr = (unsigned long long *)info->start[0]; + f_command = 0x00F000F000F000F0ULL; + ull_write(f_addr, &f_command); + return ERR_TIMOUT; + } + } while(*((unsigned long long *)address) != data); + + return 0; +} diff --git a/board/rsdproto/flash_asm.S b/board/rsdproto/flash_asm.S new file mode 100644 index 0000000..557cac0 --- /dev/null +++ b/board/rsdproto/flash_asm.S @@ -0,0 +1,39 @@ +/* + * -*- mode:c -*- + * + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * void ull_write(unsigned long long volatile *address, + * unsigned long long volatile *data) + * r3 = address + * r4 = data + * + * void ull_read(unsigned long long volatile *address, + * unsigned long long volatile *data) + * r3 = address + * r4 = data + * + * Uses the floating point unit to read and write 64 bit wide + * data (unsigned long long) on the 60x bus. This is necessary + * because all 4 flash chips use the /WE line from byte lane 0 + * + * IMPORTANT: data should always be 8-aligned, otherwise an exception will + * occur. + */ + +#include +#include + + .globl ull_write +ull_write: + lfd 0,0(r4) + stfd 0,0(r3) + blr + + .globl ull_read +ull_read: + lfd 0, 0(r3) + stfd 0, 0(r4) + blr diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c new file mode 100644 index 0000000..bf4fd53 --- /dev/null +++ b/board/rsdproto/rsdproto.c @@ -0,0 +1,378 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* define to initialise the SDRAM on the local bus */ +#undef INIT_LOCAL_BUS_SDRAM + +/* I2C Bus adresses for PPC & Protocol board */ +#define PPC8260_I2C_ADR 0x30 /*(0)011.0000 */ +#define LM84_PPC_I2C_ADR 0x2A /*(0)010.1010 */ +#define LM84_SHARC_I2C_ADR 0x29 /*(0)010.1001 */ +#define VIRTEX_I2C_ADR 0x25 /*(0)010.0101 */ +#define X24645_PPC_I2C_ADR 0x00 /*(0)00X.XXXX -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */ +#define RS5C372_PPC_I2C_ADR 0x32 /*(0)011.0010 -> this adress is programmed by the manufacturer and cannot be changed !!! */ + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 0, 0, 0 }, + /* PA30 */ { 0, 0, 0, 0, 0, 0 }, + /* PA29 */ { 0, 0, 0, 0, 0, 0 }, + /* PA28 */ { 0, 0, 0, 0, 0, 0 }, + /* PA27 */ { 0, 0, 0, 0, 0, 0 }, + /* PA26 */ { 0, 0, 0, 0, 0, 0 }, + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, + /* PA21 */ { 0, 0, 0, 0, 0, 0 }, + /* PA20 */ { 0, 0, 0, 0, 0, 0 }, + /* PA19 */ { 0, 0, 0, 0, 0, 0 }, + /* PA18 */ { 0, 0, 0, 0, 0, 0 }, + /* PA17 */ { 0, 0, 0, 0, 0, 0 }, + /* PA16 */ { 0, 0, 0, 0, 0, 0 }, + /* PA15 */ { 0, 0, 0, 0, 0, 0 }, + /* PA14 */ { 0, 0, 0, 0, 0, 0 }, + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, + /* PA9 */ { 0, 0, 0, 0, 0, 0 }, + /* PA8 */ { 0, 0, 0, 0, 0, 0 }, + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, + /* PA0 */ { 0, 0, 0, 0, 0, 0 } + }, + + + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, + /* PC21 */ { 0, 0, 0, 0, 0, 0 }, + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* ETHRXCLK: CLK14 */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* ETHTXCLK: CLK15 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART CD/ */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDC: GP */ + /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDIO: GP */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, + /* PC0 */ { 0, 0, 0, 0, 0, 0 } + }, + + + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +struct tm { + unsigned int tm_sec; + unsigned int tm_min; + unsigned int tm_hour; + unsigned int tm_wday; + unsigned int tm_mday; + unsigned int tm_mon; + unsigned int tm_year; +}; + +void read_RS5C372_time (struct tm *timedate) +{ + unsigned char buffer[8]; + +#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) + + if (i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) { + timedate->tm_sec = BCD_TO_BIN (buffer[0]); + timedate->tm_min = BCD_TO_BIN (buffer[1]); + timedate->tm_hour = BCD_TO_BIN (buffer[2]); + timedate->tm_wday = BCD_TO_BIN (buffer[3]); + timedate->tm_mday = BCD_TO_BIN (buffer[4]); + timedate->tm_mon = BCD_TO_BIN (buffer[5]); + timedate->tm_year = BCD_TO_BIN (buffer[6]) + 2000; + } else { + /*printf("i2c error %02x\n", rc); */ + memset (timedate, 0, sizeof (struct tm)); + } +} + +/* ------------------------------------------------------------------------- */ + +int read_LM84_temp (int address) +{ + unsigned char buffer[8]; + /*int rc;*/ + + if (i2c_read (address, 0, 1, buffer, 1)) { + return (int) buffer[0]; + } else { + /*printf("i2c error %02x\n", rc); */ + return -42; + } +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + struct tm timedate; + unsigned int ppctemp, prottemp; + + puts ("Board: Rohde & Schwarz 8260 Protocol Board\n"); + + /* initialise i2c */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + read_RS5C372_time (&timedate); + printf (" Time: %02d:%02d:%02d\n", + timedate.tm_hour, timedate.tm_min, timedate.tm_sec); + printf (" Date: %02d-%02d-%04d\n", + timedate.tm_mday, timedate.tm_mon, timedate.tm_year); + ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR); + prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR); + printf (" Temp: PPC %d C, Protocol Board %d C\n", + ppctemp, prottemp); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations while still + * running in flash + */ + +int misc_init_f (void) +{ + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifdef INIT_LOCAL_BUS_SDRAM + volatile uchar *ramaddr8; +#endif + volatile ulong *ramaddr32; + ulong sdmr; + int i; + + /* + * Only initialize SDRAM when running from FLASH. + * When running from RAM, don't touch it. + */ + if ((ulong) initdram & 0xff000000) { + immap->im_siu_conf.sc_ppc_acr = 0x02; + immap->im_siu_conf.sc_ppc_alrh = 0x01267893; + immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; + immap->im_siu_conf.sc_lcl_acr = 0x02; + immap->im_siu_conf.sc_lcl_alrh = 0x01234567; + immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; + /* + * Program local/60x bus Transfer Error Status and Control Regs: + * Disable parity errors + */ + immap->im_siu_conf.sc_tescr1 = 0x00040000; + immap->im_siu_conf.sc_ltescr1 = 0x00040000; + + /* + * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2) + * + * The appropriate BRx/ORx registers have already + * been set when we get here (see cpu_init_f). The + * SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + memctl->memc_mptpr = 0x2000; + memctl->memc_mar = 0x0200; +#ifdef INIT_LOCAL_BUS_SDRAM + /* initialise local bus ram + * + * (using the PSRMR_ definitions is NOT an error here + * - the LSDMR has the same fields as the PSDMR!) + */ + memctl->memc_lsrt = 0x0b; + memctl->memc_lurt = 0x00; + ramaddr = (uchar *) PHYS_SDRAM_LOCAL; + sdmr = CFG_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); + memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA; + *ramaddr = 0xff; + for (i = 0; i < 8; i++) { + memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR; + *ramaddr = 0xff; + } + memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW; + *ramaddr = 0xff; + memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_NORM; +#endif + /* initialise 60x bus ram */ + memctl->memc_psrt = 0x0b; + memctl->memc_purt = 0x08; + ramaddr32 = (ulong *) PHYS_SDRAM_60X; + sdmr = CFG_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); + memctl->memc_psdmr = sdmr | PSDMR_OP_PREA; + ramaddr32[0] = 0x00ff00ff; + ramaddr32[1] = 0x00ff00ff; + memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) { + ramaddr32[0] = 0x00ff00ff; + ramaddr32[1] = 0x00ff00ff; + } + memctl->memc_psdmr = sdmr | PSDMR_OP_MRW; + ramaddr32[0] = 0x00ff00ff; + ramaddr32[1] = 0x00ff00ff; + memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + } + + /* return the size of the 60x bus ram */ + return PHYS_SDRAM_60X_SIZE; +} + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations after monitor + * has been relocated into ram + */ + +int misc_init_r (void) +{ + printf ("misc_init_r\n"); + return (0); +} diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds new file mode 100644 index 0000000..70fc3a5 --- /dev/null +++ b/board/rsdproto/u-boot.lds @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + /*. = env_offset; */ + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile new file mode 100644 index 0000000..baefa4a --- /dev/null +++ b/board/sacsng/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := sacsng.o flash.o clkinit.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c new file mode 100644 index 0000000..ea4c65d --- /dev/null +++ b/board/sacsng/clkinit.c @@ -0,0 +1,1025 @@ +/* + * (C) Copyright 2002 + * Custom IDEAS, Inc. + * Jon Diekema + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "clkinit.h" + +int Daq64xSampling = 0; + + +void Daq_BRG_Reset(uint brg) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uint *brg_ptr; + + brg_ptr = (uint *)&immr->im_brgc1; + + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg -= 4; + } + brg_ptr += brg; + *brg_ptr |= CPM_BRG_RST; + *brg_ptr &= ~CPM_BRG_RST; +} + +void Daq_BRG_Disable(uint brg) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uint *brg_ptr; + + brg_ptr = (uint *)&immr->im_brgc1; + + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg -= 4; + } + brg_ptr += brg; + *brg_ptr &= ~CPM_BRG_EN; +} + +void Daq_BRG_Enable(uint brg) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uint *brg_ptr; + + brg_ptr = (uint *)&immr->im_brgc1; + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg -= 4; + } + brg_ptr += brg; + *brg_ptr |= CPM_BRG_EN; +} + +uint Daq_BRG_Get_Div16(uint brg) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint *brg_ptr; + + brg_ptr = (uint *)&immr->im_brgc1; + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg -= 4; + } + brg_ptr += brg; + + if (*brg_ptr & CPM_BRG_DIV16) { + /* DIV16 active */ + return (TRUE); + } + else { + /* DIV16 inactive */ + return (FALSE); + } +} + +void Daq_BRG_Set_Div16(uint brg, uint div16) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint *brg_ptr; + + brg_ptr = (uint *)&immr->im_brgc1; + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg -= 4; + } + brg_ptr += brg; + + if (div16) { + /* DIV16 active */ + *brg_ptr |= CPM_BRG_DIV16; + } + else { + /* DIV16 inactive */ + *brg_ptr &= ~CPM_BRG_DIV16; + } +} + +uint Daq_BRG_Get_Count(uint brg) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint *brg_ptr; + uint brg_cnt; + + brg_ptr = (uint *)&immr->im_brgc1; + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg -= 4; + } + brg_ptr += brg; + + /* Get the clock divider + * + * Note: A clock divider of 0 means divide by 1, + * therefore we need to add 1 to the count. + */ + brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT; + brg_cnt++; + if (*brg_ptr & CPM_BRG_DIV16) { + brg_cnt *= 16; + } + + return (brg_cnt); +} + +void Daq_BRG_Set_Count(uint brg, uint brg_cnt) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint *brg_ptr; + + brg_ptr = (uint *)&immr->im_brgc1; + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg -= 4; + } + brg_ptr += brg; + + /* + * Note: A clock divider of 0 means divide by 1, + * therefore we need to subtract 1 from the count. + */ + if (brg_cnt > 4096) { + /* Prescale = Divide by 16 */ + *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) | + (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT); + *brg_ptr |= CPM_BRG_DIV16; + } + else { + /* Prescale = Divide by 1 */ + *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) | + ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT); + *brg_ptr &= ~CPM_BRG_DIV16; + } +} + +uint Daq_BRG_Get_ExtClk(uint brg) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint *brg_ptr; + + brg_ptr = (uint *)&immr->im_brgc1; + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg -= 4; + } + brg_ptr += brg; + + return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT); +} + +char* Daq_BRG_Get_ExtClk_Description(uint brg) +{ + uint extc; + + extc = Daq_BRG_Get_ExtClk(brg); + + switch (brg + 1) { + case 1: + case 2: + case 5: + case 6: { + switch (extc) { + case 0: { + return ("BRG_INT"); + } + case 1: { + return ("CLK3"); + } + case 2: { + return ("CLK5"); + } + } + return ("??1245??"); + } + case 3: + case 4: + case 7: + case 8: { + switch (extc) { + case 0: { + return ("BRG_INT"); + } + case 1: { + return ("CLK9"); + } + case 2: { + return ("CLK15"); + } + } + return ("??3478??"); + } + } + return ("??9876??"); +} + +void Daq_BRG_Set_ExtClk(uint brg, uint extc) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint *brg_ptr; + + brg_ptr = (uint *)&immr->im_brgc1; + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg -= 4; + } + brg_ptr += brg; + + *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) | + ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK); +} + +uint Daq_BRG_Rate(uint brg) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint *brg_ptr; + uint brg_cnt; + uint brg_freq = 0; + + brg_ptr = (uint *)&immr->im_brgc1; + brg_ptr += brg; + if (brg >= 5) { + brg_ptr = (uint *)&immr->im_brgc5; + brg_ptr += (brg - 4); + } + + brg_cnt = Daq_BRG_Get_Count(brg); + + switch (Daq_BRG_Get_ExtClk(brg)) { + case CPM_BRG_EXTC_CLK3: + case CPM_BRG_EXTC_CLK5: { + brg_freq = brg_cnt; + break; + } + default: { + brg_freq = (uint)BRG_INT_CLK / brg_cnt; + } + } + return (brg_freq); +} + +uint Daq_Get_SampleRate(void) +{ + /* + * Read the BRG's to return the actual sample rate. + */ + return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR)); +} + +void Daq_Init_Clocks(int sample_rate, int sample_64x) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */); + uint mclk_divisor; /* MCLK divisor */ + int flag; /* Interrupt state */ + + /* Save off the clocking data */ + Daq64xSampling = sample_64x; + + /* + * Limit the sample rate to some sensible values. + */ + if (sample_rate > MAX_64x_SAMPLE_RATE) { + sample_rate = MAX_64x_SAMPLE_RATE; + } + if (sample_rate < MIN_SAMPLE_RATE) { + sample_rate = MIN_SAMPLE_RATE; + } + + /* + * Initialize the MCLK/SCLK/LRCLK baud rate generators. + */ + + /* Setup MCLK */ + Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK); + + /* Setup SCLK */ +# ifdef RUN_SCLK_ON_BRG_INT + Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK); +# else + Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9); +# endif + + /* Setup LRCLK */ +# ifdef RUN_LRCLK_ON_BRG_INT + Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK); +# else + Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5); +# endif + + /* + * Dynamically adjust MCLK based on the new sample rate. + */ + + /* Compute the divisors */ + mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR); + + /* + * Disable interrupt and save the current state + */ + flag = disable_interrupts(); + + /* Setup MCLK */ + Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor); + + /* Setup SCLK */ +# ifdef RUN_SCLK_ON_BRG_INT + Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR); +# else + Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR); +# endif + +# ifdef RUN_LRCLK_ON_BRG_INT + Daq_BRG_Set_Count(LRCLK_BRG, + mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR); +# else + Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR); +# endif + + /* + * Restore the Interrupt state + */ + if (flag) { + enable_interrupts(); + } + + /* Enable the clock drivers */ + iopa->pdat &= ~SLRCLK_EN_MASK; +} + +void Daq_Stop_Clocks(void) + +{ +#ifdef TIGHTEN_UP_BRG_TIMING + volatile immap_t *immr = (immap_t *)CFG_IMMR; + register uint mclk_brg; /* MCLK BRG value */ + register uint sclk_brg; /* SCLK BRG value */ + register uint lrclk_brg; /* LRCLK BRG value */ + unsigned long flag; /* Interrupt flags */ +#endif + +# ifdef TIGHTEN_UP_BRG_TIMING + /* + * Obtain MCLK BRG reset/disabled value + */ +# if (MCLK_BRG == 0) + mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (MCLK_BRG == 1) + mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (MCLK_BRG == 2) + mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (MCLK_BRG == 3) + mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (MCLK_BRG == 4) + mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (MCLK_BRG == 5) + mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (MCLK_BRG == 6) + mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (MCLK_BRG == 7) + mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif + + /* + * Obtain SCLK BRG reset/disabled value + */ +# if (SCLK_BRG == 0) + sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (SCLK_BRG == 1) + sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (SCLK_BRG == 2) + sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (SCLK_BRG == 3) + sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (SCLK_BRG == 4) + sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (SCLK_BRG == 5) + sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (SCLK_BRG == 6) + sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (SCLK_BRG == 7) + sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif + + /* + * Obtain LRCLK BRG reset/disabled value + */ +# if (LRCLK_BRG == 0) + lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 1) + lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 2) + lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 3) + lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 4) + lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 5) + lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 6) + lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 7) + lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; +# endif + + /* + * Disable interrupt and save the current state + */ + flag = disable_interrupts(); + + /* + * Set reset on MCLK BRG + */ +# if (MCLK_BRG == 0) + *IM_BRGC1 = mclk_brg; +# endif +# if (MCLK_BRG == 1) + *IM_BRGC2 = mclk_brg; +# endif +# if (MCLK_BRG == 2) + *IM_BRGC3 = mclk_brg; +# endif +# if (MCLK_BRG == 3) + *IM_BRGC4 = mclk_brg; +# endif +# if (MCLK_BRG == 4) + *IM_BRGC5 = mclk_brg; +# endif +# if (MCLK_BRG == 5) + *IM_BRGC6 = mclk_brg; +# endif +# if (MCLK_BRG == 6) + *IM_BRGC7 = mclk_brg; +# endif +# if (MCLK_BRG == 7) + *IM_BRGC8 = mclk_brg; +# endif + + /* + * Set reset on SCLK BRG + */ +# if (SCLK_BRG == 0) + *IM_BRGC1 = sclk_brg; +# endif +# if (SCLK_BRG == 1) + *IM_BRGC2 = sclk_brg; +# endif +# if (SCLK_BRG == 2) + *IM_BRGC3 = sclk_brg; +# endif +# if (SCLK_BRG == 3) + *IM_BRGC4 = sclk_brg; +# endif +# if (SCLK_BRG == 4) + *IM_BRGC5 = sclk_brg; +# endif +# if (SCLK_BRG == 5) + *IM_BRGC6 = sclk_brg; +# endif +# if (SCLK_BRG == 6) + *IM_BRGC7 = sclk_brg; +# endif +# if (SCLK_BRG == 7) + *IM_BRGC8 = sclk_brg; +# endif + + /* + * Set reset on LRCLK BRG + */ +# if (LRCLK_BRG == 0) + *IM_BRGC1 = lrclk_brg; +# endif +# if (LRCLK_BRG == 1) + *IM_BRGC2 = lrclk_brg; +# endif +# if (LRCLK_BRG == 2) + *IM_BRGC3 = lrclk_brg; +# endif +# if (LRCLK_BRG == 3) + *IM_BRGC4 = lrclk_brg; +# endif +# if (LRCLK_BRG == 4) + *IM_BRGC5 = lrclk_brg; +# endif +# if (LRCLK_BRG == 5) + *IM_BRGC6 = lrclk_brg; +# endif +# if (LRCLK_BRG == 6) + *IM_BRGC7 = lrclk_brg; +# endif +# if (LRCLK_BRG == 7) + *IM_BRGC8 = lrclk_brg; +# endif + + /* + * Clear reset on MCLK BRG + */ +# if (MCLK_BRG == 0) + *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST; +# endif +# if (MCLK_BRG == 1) + *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST; +# endif +# if (MCLK_BRG == 2) + *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST; +# endif +# if (MCLK_BRG == 3) + *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST; +# endif +# if (MCLK_BRG == 4) + *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST; +# endif +# if (MCLK_BRG == 5) + *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST; +# endif +# if (MCLK_BRG == 6) + *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST; +# endif +# if (MCLK_BRG == 7) + *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST; +# endif + + /* + * Clear reset on SCLK BRG + */ +# if (SCLK_BRG == 0) + *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST; +# endif +# if (SCLK_BRG == 1) + *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST; +# endif +# if (SCLK_BRG == 2) + *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST; +# endif +# if (SCLK_BRG == 3) + *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST; +# endif +# if (SCLK_BRG == 4) + *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST; +# endif +# if (SCLK_BRG == 5) + *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST; +# endif +# if (SCLK_BRG == 6) + *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST; +# endif +# if (SCLK_BRG == 7) + *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST; +# endif + + /* + * Clear reset on LRCLK BRG + */ +# if (LRCLK_BRG == 0) + *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST; +# endif +# if (LRCLK_BRG == 1) + *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST; +# endif +# if (LRCLK_BRG == 2) + *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST; +# endif +# if (LRCLK_BRG == 3) + *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST; +# endif +# if (LRCLK_BRG == 4) + *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST; +# endif +# if (LRCLK_BRG == 5) + *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST; +# endif +# if (LRCLK_BRG == 6) + *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST; +# endif +# if (LRCLK_BRG == 7) + *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST; +# endif + + /* + * Restore the Interrupt state + */ + if (flag) { + enable_interrupts(); + } +# else + /* + * Reset the clocks + */ + Daq_BRG_Reset(MCLK_BRG); + Daq_BRG_Reset(SCLK_BRG); + Daq_BRG_Reset(LRCLK_BRG); +# endif +} + +void Daq_Start_Clocks(int sample_rate) + +{ +#ifdef TIGHTEN_UP_BRG_TIMING + volatile immap_t *immr = (immap_t *)CFG_IMMR; + + register uint mclk_brg; /* MCLK BRG value */ + register uint sclk_brg; /* SCLK BRG value */ + register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */ + register uint real_lrclk_brg; /* Permanent LRCLK BRG value */ + uint lrclk_brg; /* LRCLK BRG value */ + unsigned long flags; /* Interrupt flags */ + uint sclk_cnt; /* SCLK count */ + uint delay_cnt; /* Delay count */ +#endif + +# ifdef TIGHTEN_UP_BRG_TIMING + /* + * Obtain the enabled MCLK BRG value + */ +# if (MCLK_BRG == 0) + mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (MCLK_BRG == 1) + mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (MCLK_BRG == 2) + mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (MCLK_BRG == 3) + mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (MCLK_BRG == 4) + mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (MCLK_BRG == 5) + mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (MCLK_BRG == 6) + mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (MCLK_BRG == 7) + mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif + + /* + * Obtain the enabled SCLK BRG value + */ +# if (SCLK_BRG == 0) + sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (SCLK_BRG == 1) + sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (SCLK_BRG == 2) + sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (SCLK_BRG == 3) + sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (SCLK_BRG == 4) + sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (SCLK_BRG == 5) + sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (SCLK_BRG == 6) + sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (SCLK_BRG == 7) + sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif + + /* + * Obtain the enabled LRCLK BRG value + */ +# if (LRCLK_BRG == 0) + lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 1) + lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 2) + lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 3) + lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 4) + lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 5) + lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 6) + lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif +# if (LRCLK_BRG == 7) + lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; +# endif + + /* Save off the real LRCLK value */ + real_lrclk_brg = lrclk_brg; + + /* Obtain the current SCLK count */ + sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1; + + /* Compute the delay as a function of SCLK count */ + delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6; + if (DaqSampleRate == 43402) { + delay_cnt++; + } + + /* Clear out the count */ + temp_lrclk_brg = sclk_brg & ~0x00001FFE; + + /* Insert the count */ + temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE; + + /* + * Disable interrupt and save the current state + */ + flag = disable_interrupts(); + + /* + * Enable MCLK BRG + */ +# if (MCLK_BRG == 0) + *IM_BRGC1 = mclk_brg; +# endif +# if (MCLK_BRG == 1) + *IM_BRGC2 = mclk_brg; +# endif +# if (MCLK_BRG == 2) + *IM_BRGC3 = mclk_brg; +# endif +# if (MCLK_BRG == 3) + *IM_BRGC4 = mclk_brg; +# endif +# if (MCLK_BRG == 4) + *IM_BRGC5 = mclk_brg; +# endif +# if (MCLK_BRG == 5) + *IM_BRGC6 = mclk_brg; +# endif +# if (MCLK_BRG == 6) + *IM_BRGC7 = mclk_brg; +# endif +# if (MCLK_BRG == 7) + *IM_BRGC8 = mclk_brg; +# endif + + /* + * Enable SCLK BRG + */ +# if (SCLK_BRG == 0) + *IM_BRGC1 = sclk_brg; +# endif +# if (SCLK_BRG == 1) + *IM_BRGC2 = sclk_brg; +# endif +# if (SCLK_BRG == 2) + *IM_BRGC3 = sclk_brg; +# endif +# if (SCLK_BRG == 3) + *IM_BRGC4 = sclk_brg; +# endif +# if (SCLK_BRG == 4) + *IM_BRGC5 = sclk_brg; +# endif +# if (SCLK_BRG == 5) + *IM_BRGC6 = sclk_brg; +# endif +# if (SCLK_BRG == 6) + *IM_BRGC7 = sclk_brg; +# endif +# if (SCLK_BRG == 7) + *IM_BRGC8 = sclk_brg; +# endif + + /* + * Enable LRCLK BRG (1st time - temporary) + */ +# if (LRCLK_BRG == 0) + *IM_BRGC1 = temp_lrclk_brg; +# endif +# if (LRCLK_BRG == 1) + *IM_BRGC2 = temp_lrclk_brg; +# endif +# if (LRCLK_BRG == 2) + *IM_BRGC3 = temp_lrclk_brg; +# endif +# if (LRCLK_BRG == 3) + *IM_BRGC4 = temp_lrclk_brg; +# endif +# if (LRCLK_BRG == 4) + *IM_BRGC5 = temp_lrclk_brg; +# endif +# if (LRCLK_BRG == 5) + *IM_BRGC6 = temp_lrclk_brg; +# endif +# if (LRCLK_BRG == 6) + *IM_BRGC7 = temp_lrclk_brg; +# endif +# if (LRCLK_BRG == 7) + *IM_BRGC8 = temp_lrclk_brg; +# endif + + /* + * Enable LRCLK BRG (2nd time - permanent) + */ +# if (LRCLK_BRG == 0) + *IM_BRGC1 = real_lrclk_brg; +# endif +# if (LRCLK_BRG == 1) + *IM_BRGC2 = real_lrclk_brg; +# endif +# if (LRCLK_BRG == 2) + *IM_BRGC3 = real_lrclk_brg; +# endif +# if (LRCLK_BRG == 3) + *IM_BRGC4 = real_lrclk_brg; +# endif +# if (LRCLK_BRG == 4) + *IM_BRGC5 = real_lrclk_brg; +# endif +# if (LRCLK_BRG == 5) + *IM_BRGC6 = real_lrclk_brg; +# endif +# if (LRCLK_BRG == 6) + *IM_BRGC7 = real_lrclk_brg; +# endif +# if (LRCLK_BRG == 7) + *IM_BRGC8 = real_lrclk_brg; +# endif + + /* + * Restore the Interrupt state + */ + if (flag) { + enable_interrupts(); + } +# else + /* + * Enable the clocks + */ + Daq_BRG_Enable(LRCLK_BRG); + Daq_BRG_Enable(SCLK_BRG); + Daq_BRG_Enable(MCLK_BRG); +# endif +} + +void Daq_Display_Clocks(void) + +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint mclk_divisor; /* Detected MCLK divisor */ + uint sclk_divisor; /* Detected SCLK divisor */ + + printf("\nBRG:\n"); + if (immr->im_brgc4 != 0) { + printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n", + immr->im_brgc4, + (uint)&(immr->im_brgc4), + Daq_BRG_Get_Count(3), + Daq_BRG_Get_ExtClk(3), + Daq_BRG_Get_ExtClk_Description(3)); + } + if (immr->im_brgc8 != 0) { + printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n", + immr->im_brgc8, + (uint)&(immr->im_brgc8), + Daq_BRG_Get_Count(7), + Daq_BRG_Get_ExtClk(7), + Daq_BRG_Get_ExtClk_Description(7)); + } + if (immr->im_brgc6 != 0) { + printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n", + immr->im_brgc6, + (uint)&(immr->im_brgc6), + Daq_BRG_Get_Count(5), + Daq_BRG_Get_ExtClk(5), + Daq_BRG_Get_ExtClk_Description(5)); + } + if (immr->im_brgc1 != 0) { + printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n", + immr->im_brgc1, + (uint)&(immr->im_brgc1), + Daq_BRG_Get_Count(0), + Daq_BRG_Get_ExtClk(0), + Daq_BRG_Get_ExtClk_Description(0)); + } + if (immr->im_brgc2 != 0) { + printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n", + immr->im_brgc2, + (uint)&(immr->im_brgc2), + Daq_BRG_Get_Count(1), + Daq_BRG_Get_ExtClk(1), + Daq_BRG_Get_ExtClk_Description(1)); + } + if (immr->im_brgc3 != 0) { + printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n", + immr->im_brgc3, + (uint)&(immr->im_brgc3), + Daq_BRG_Get_Count(2), + Daq_BRG_Get_ExtClk(2), + Daq_BRG_Get_ExtClk_Description(2)); + } + if (immr->im_brgc5 != 0) { + printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n", + immr->im_brgc5, + (uint)&(immr->im_brgc5), + Daq_BRG_Get_Count(4), + Daq_BRG_Get_ExtClk(4), + Daq_BRG_Get_ExtClk_Description(4)); + } + if (immr->im_brgc7 != 0) { + printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n", + immr->im_brgc7, + (uint)&(immr->im_brgc7), + Daq_BRG_Get_Count(6), + Daq_BRG_Get_ExtClk(6), + Daq_BRG_Get_ExtClk_Description(6)); + } + +# ifdef RUN_SCLK_ON_BRG_INT + mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG); +# else + mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG); +# endif +# ifdef RUN_LRCLK_ON_BRG_INT + sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG); +# else + sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG); +# endif + + printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor); + printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n", + Daq_BRG_Rate(MCLK_BRG), + mclk_divisor, + mclk_divisor * sclk_divisor); +# ifdef RUN_SCLK_ON_BRG_INT + printf("\tSCLK %8d Hz, or %3dx LRCLK\n", + Daq_BRG_Rate(SCLK_BRG), + sclk_divisor); +# else + printf("\tSCLK %8d Hz, or %3dx LRCLK\n", + Daq_BRG_Rate(MCLK_BRG) / mclk_divisor, + sclk_divisor); +# endif +# ifdef RUN_LRCLK_ON_BRG_INT + printf("\tLRCLK %8d Hz\n", + Daq_BRG_Rate(LRCLK_BRG)); +# else +# ifdef RUN_SCLK_ON_BRG_INT + printf("\tLRCLK %8d Hz\n", + Daq_BRG_Rate(SCLK_BRG) / sclk_divisor); +# else + printf("\tLRCLK %8d Hz\n", + Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor)); +# endif +# endif + printf("\n"); +} diff --git a/board/sacsng/clkinit.h b/board/sacsng/clkinit.h new file mode 100644 index 0000000..011638f --- /dev/null +++ b/board/sacsng/clkinit.h @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2002 + * Custom IDEAS, Inc. + * Jon Diekema + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef FALSE +#define FALSE 0 +#define TRUE (!FALSE) +#endif + +#define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */ + +#define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */ +#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */ +#define MAX_64x_SAMPLE_RATE 86805 /* Maximum 64x sample rate */ + +#define KHZ ((uint)1000) +#define MHZ ((uint)(1000 * KHZ)) + +#define MCLK_BRG 3 /* MCLK, Master CLocK for the A/D & D/A */ +#define SCLK_BRG 7 /* SCLK, Sample CLocK for the A/D & D/A */ +#define LRCLK_BRG 5 /* LRCLK, L/R CLocK for the A/D & D/A */ + /* 0 == BRG1 (used for SMC1) */ + /* 1 == BRG2 (used for SMC2) */ + /* 2 == BRG3 (used for SCC1) */ + /* 3 == BRG4 (MCLK) */ + /* 4 == BRG5 */ + /* 5 == BRG6 (LRCLK) */ + /* 6 == BRG7 */ + /* 7 == BRG8 (SCLK) */ + +#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */ +#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128) + /* LRCLK = SCLK / SCLK_DIVISOR */ + +#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */ +#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */ + /* The 8260 (Mask B.3) seems to have */ + /* problems generating SCLK from MCLK */ + /* via CLK9. */ +#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */ + /* The 8260 (Mask B.3) seems to have */ + /* problems generating LRCLK from SCLK */ + +#define NUM_LRCLKS_TO_STABILIZE 1 /* Number of LRCLK period (sample) */ + /* to wait for the clock to stabilize */ + +#define CPM_CLK (gd->bd->bi_cpmfreq) +#define DFBRG 4 +#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG) + /* BRG = CPM * 2 / DFBRG (Sect 9.8) */ + /* BRG = CPM * 2 / 4 */ + /* BRG = CPM / 2 */ + +#define CPM_BRG_EXTC_MASK ((uint)0x0000C000) +#define CPM_BRG_EXTC_SHIFT 14 + +#define CPM_BRG_DIV16_MASK ((uint)0x00000001) +#define CPM_BRG_DIV16_SHIFT 1 + +#define CPM_BRG_EXTC_BRGCLK 0 +#define CPM_BRG_EXTC_CLK3 1 +#define CPM_BRG_EXTC_CLK9 CPM_BRG_EXTC_CLK3 +#define CPM_BRG_EXTC_CLK5 2 +#define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5 + +#define IM_BRGC1 ((uint *)0xf00119f0) +#define IM_BRGC2 ((uint *)0xf00119f4) +#define IM_BRGC3 ((uint *)0xf00119f8) +#define IM_BRGC4 ((uint *)0xf00119fc) +#define IM_BRGC5 ((uint *)0xf00115f0) +#define IM_BRGC6 ((uint *)0xf00115f4) +#define IM_BRGC7 ((uint *)0xf00115f8) +#define IM_BRGC8 ((uint *)0xf00115fc) + +/* + * External declarations + */ + +extern int Daq64xSampling; + +extern void Daq_BRG_Reset(uint brg); +extern void Daq_BRG_Run(uint brg); + +extern void Daq_BRG_Disable(uint brg); +extern void Daq_BRG_Enable(uint brg); + +extern uint Daq_BRG_Get_Div16(uint brg); +extern void Daq_BRG_Set_Div16(uint brg, uint div16); + +extern uint Daq_BRG_Get_Count(uint brg); +extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt); + +extern uint Daq_BRG_Get_ExtClk(uint brg); +extern char* Daq_BRG_Get_ExtClk_Description(uint brg); +extern void Daq_BRG_Set_ExtClk(uint brg, uint extc); + +extern uint Daq_BRG_Rate(uint brg); + +extern uint Daq_Get_SampleRate(void); + +extern void Daq_Init_Clocks(int sample_rate, int sample_64x); +extern void Daq_Stop_Clocks(void); +extern void Daq_Start_Clocks(int sample_rate); +extern void Daq_Display_Clocks(void); diff --git a/board/sacsng/config.mk b/board/sacsng/config.mk new file mode 100644 index 0000000..220b218 --- /dev/null +++ b/board/sacsng/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# 82xx boards +# + +TEXT_BASE = 0x40000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/sacsng/flash.c b/board/sacsng/flash.c new file mode 100644 index 0000000..52e01de --- /dev/null +++ b/board/sacsng/flash.c @@ -0,0 +1,523 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +#undef DEBUG + +#ifndef CFG_ENV_ADDR +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif +#ifndef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#endif + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_short *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + + if (size_b1) { +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[1]); +#endif + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + /* + * We only report the primary flash for U-Boot's use. + */ + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_short *addr, flash_info_t *info) +{ + short i; + ushort value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0xAAAA; + addr[0x02AA] = 0x5555; + addr[0x0555] = 0x9090; + __asm__ __volatile__(" sync\n "); + + value = addr[0]; +#ifdef DEBUG + printf("Flash manufacturer 0x%04X\n", value); +#endif + + if(value == (ushort)AMD_MANUFACT) { + info->flash_id = FLASH_MAN_AMD; + } else if (value == (ushort)FUJ_MANUFACT) { + info->flash_id = FLASH_MAN_FUJ; + } else { +#ifdef DEBUG + printf("Unknown flash manufacturer 0x%04X\n", value); +#endif + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ +#ifdef DEBUG + printf("Flash type 0x%04X\n", value); +#endif + + if(value == (ushort)AMD_ID_LV400T) { + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; /* => 0.5 MB */ + } else if(value == (ushort)AMD_ID_LV400B) { + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; /* => 0.5 MB */ + } else if(value == (ushort)AMD_ID_LV800T) { + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; /* => 1 MB */ + } else if(value == (ushort)AMD_ID_LV800B) { + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; /* => 1 MB */ + } else if(value == (ushort)AMD_ID_LV160T) { + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; /* => 2 MB */ + } else if(value == (ushort)AMD_ID_LV160B) { + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; /* => 2 MB */ + } else if(value == (ushort)AMD_ID_LV320T) { + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; /* => 4 MB */ + } else if(value == (ushort)AMD_ID_LV320B) { + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; /* => 4 MB */ + } else { +#ifdef DEBUG + printf("Unknown flash type 0x%04X\n", value); + info->size = CFG_FLASH_SIZE; +#else + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ +#endif + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + ((i - 3) * 0x00010000); + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + (i * 0x00010000); + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned short *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned short *)info->start[0]; + + } + + addr[0] = 0xF0F0; /* reset bank */ + __asm__ __volatile__(" sync\n "); + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_short *addr = (vu_short*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAAAA; + addr[0x02AA] = 0x5555; + addr[0x0555] = 0x8080; + addr[0x0555] = 0xAAAA; + addr[0x02AA] = 0x5555; + __asm__ __volatile__(" sync\n "); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_short*)(info->start[sect]); + addr[0] = 0x3030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_short*)(info->start[l_sect]); + while ((addr[0] & 0x0080) != 0x0080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + addr[0] = 0xF0F0; /* reset bank */ + __asm__ __volatile__(" sync\n "); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_short*)info->start[0]; + addr[0] = 0xF0F0; /* reset bank */ + __asm__ __volatile__(" sync\n "); + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_short *addr = (vu_short*)(info->start[0]); + ulong start; + int flag; + int j; + + /* Check if Flash is (sufficiently) erased */ + if (((*(vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* The original routine was designed to write 32 bit words to + * 32 bit wide memory. We have 16 bit wide memory so we do + * two writes. We write the LSB first at dest+2 and then the + * MSB at dest (lousy big endian). + */ + dest += 2; + for(j = 0; j < 2; j++) { + addr[0x0555] = 0xAAAA; + addr[0x02AA] = 0x5555; + addr[0x0555] = 0xA0A0; + __asm__ __volatile__(" sync\n "); + + *((vu_short *)dest) = (ushort)data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while (*(vu_short *)dest != (ushort)data) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + dest -= 2; + data >>= 16; + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/sacsng/ioconfig.h b/board/sacsng/ioconfig.h new file mode 100644 index 0000000..be1ce7c --- /dev/null +++ b/board/sacsng/ioconfig.h @@ -0,0 +1,217 @@ +/* + * I/O Port configuration table + * + * If conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +#ifdef SKIP +#undef SKIP +#endif + +#ifdef CONF +#undef CONF +#endif + +#ifdef DIN +#undef DIN +#endif + +#ifdef DOUT +#undef DOUT +#endif + +#ifdef GPIO +#undef GPIO +#endif + +#ifdef SPEC +#undef SPEC +#endif + +#ifdef ACTV +#undef ACTV +#endif + +#ifdef OPEN +#undef OPEN +#endif + +#define SKIP 0 /* SKIP over this port */ +#define CONF 1 /* CONFiguration the port */ + +#define DIN 0 /* PDIRx 0: Direction IN */ +#define DOUT 1 /* PDIRx 1: Direction OUT */ + +#define GPIO 0 /* PPARx 0: General Purpose I/O */ +#define SPEC 1 /* PPARx 1: dedicated to a peripheral function, */ + /* i.e. the port has a SPECial use. */ + +#define ACTV 0 /* PODRx 0: ACTiVely driven as an output */ +#define OPEN 1 /* PODRx 1: OPEN-drain driver */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS8* */ + /* PA30 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS7* */ + /* PA29 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS6* */ + /* PA28 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS5* */ + /* PA27 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS4* */ + /* PA26 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS3* */ + /* PA25 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS2* */ + /* PA24 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS1* */ + /* PA23 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* ODIS_EN* */ + /* PA22 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED2_EN* */ + /* PA21 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED1_EN* */ + /* PA20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED3_EN* */ + /* PA19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED2_EN* */ + /* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */ + /* PA17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PA16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* DAC_RST* */ + /* PA15 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH34SDATA_PU */ + /* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */ + /* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */ + /* PA12 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4ACDC* */ + /* PA11 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4TEDS* */ + /* PA10 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4XTDS* */ + /* PA9 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3ACDC* */ + /* PA8 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3TEDS* */ + /* PA7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3XTDS* */ + /* PA6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2ACDC* */ + /* PA5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2TEDS* */ + /* PA4 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2XTDS* */ + /* PA3 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PA2 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1ACDC* */ + /* PA1 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1TEDS* */ + /* PA0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 } /* MTRX_1XTDS* */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TX_ER */ + /* PB30 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_DV */ + /* PB29 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* FCC2 MII_TX_EN */ + /* PB28 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_ER */ + /* PB27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_COL */ + /* PB26 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_CRS */ + /* PB25 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD3 */ + /* PB24 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD2 */ + /* PB23 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD1 */ + /* PB22 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD0 */ + /* PB21 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD0 */ + /* PB20 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD1 */ + /* PB19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD2 */ + /* PB18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD3 */ + /* PB17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PB16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PB15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PB14 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDC1, BSDATA_ADC12 */ + /* PB13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PB12 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCC1, LRCLK */ + /* PB11 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1TXDD1, RSDATA_DAC12 */ + /* PB10 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDD1, BSDATA_ADC34 */ + /* PB9 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PB8 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCD1, LRCLK */ + /* PB7 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PB6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* XCITE_SHDN */ + /* PB5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* TRIGGER */ + /* PB4 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* ARM */ + /* PB3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ + /* PB2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ + /* PB1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ + /* PB0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC30 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC29 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK3, MCLK */ + /* PC28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* TOUT2* */ +#ifdef QQQ + /* PC28 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TOUT2* */ +#endif + /* PC27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK5, SCLK */ + /* PC26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC25 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK7, SCLK */ + /* PC24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC23 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK9, MCLK */ + /* PC22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC21 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO6 (LRCLK) */ + /* PC20 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK13, MII_RXCLK */ + /* PC18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK14, MII_TXCLK */ + /* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */ + /* PC16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC15 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC2_TX */ + /* PC14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB3 */ + /* PC11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* TDM_STRB4 */ + /* PC9 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN3 */ + /* PC8 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN2 */ + /* PC7 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN1 */ + /* PC6 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PC5 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN2* */ + /* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */ + /* PC3 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* MUSH_STAT */ + /* PC2 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* OUTDRV_STAT */ + /* PC1 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* PHY_MDIO */ + /* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SCC1_RX */ + /* PD30 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SCC1_TX */ + /* PD29 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD27 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD25 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD23 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD21 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_ADC_CS* */ + /* PD19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_DAC_CS* */ +#if defined(CONFIG_SOFT_SPI) + /* PD18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_CLK */ + /* PD17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_MOSI */ + /* PD16 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* SPI_MISO */ +#else + /* PD18 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_CLK */ + /* PD17 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_MOSI */ + /* PD16 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* SPI_MISO */ +#endif +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* I2C_SDA */ + /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* I2C_SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SDA */ + /* PD14 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SDA */ + /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SCL */ +#endif +#endif + /* PD13 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB1 */ + /* PD12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB2 */ + /* PD11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ + /* PD10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* BRGO4 (MCLK) */ + /* PD9 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC1_TX */ + /* PD8 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SMC1_RX */ + /* PD7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ + /* PD6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ + /* PD5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ + /* PD4 */ { CONF, SPEC, 1, DOUT, ACTV, 1 }, /* SMC2_RX */ + /* PD3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ + /* PD2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ + /* PD1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ + /* PD0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */ + } +}; diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c new file mode 100644 index 0000000..e50b747 --- /dev/null +++ b/board/sacsng/sacsng.c @@ -0,0 +1,890 @@ +/* + * (C) Copyright 2002 + * Custom IDEAS, Inc. + * Gerald Van Baren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +#include +#endif + +#ifdef CONFIG_ETHER_LOOPBACK_TEST +extern void eth_loopback_test(void); +#endif /* CONFIG_ETHER_LOOPBACK_TEST */ + +extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +#include "clkinit.h" +#include "ioconfig.h" /* I/O configuration table */ + +/* + * PBI Page Based Interleaving + * PSDMR_PBI page based interleaving + * 0 bank based interleaving + * External Address Multiplexing (EAMUX) adds a clock to address cycles + * (this can help with marginal board layouts) + * PSDMR_EAMUX adds a clock + * 0 no extra clock + * Buffer Command (BUFCMD) adds a clock to command cycles. + * PSDMR_BUFCMD adds a clock + * 0 no extra clock + */ +#define CONFIG_PBI PSDMR_PBI +#define PESSIMISTIC_SDRAM 0 +#define EAMUX 0 /* EST requires EAMUX */ +#define BUFCMD 0 + +/* + * ADC/DAC Defines: + */ +#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */ +#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */ +#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */ +#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */ +#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */ + +/* + * ADC Defines: + */ +#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */ +#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */ + +#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */ +#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */ + +#define ADC_VREF_CAP 100 /* VREF capacitor in uF */ +#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */ +#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */ +#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500) + /* Wait at least 4100 LRCLK's */ + +#define ADC_REG1_FRAME_START 0x80 /* Frame start */ +#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */ +#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */ +#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */ + +#define ADC_REG2_128x 0x80 /* Oversample at 128x */ +#define ADC_REG2_CAL 0x40 /* System calibration enable */ +#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */ +#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */ +#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */ +#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */ +#define ADC_REG2_DFS 0x02 /* Digital format select */ +#define ADC_REG2_MUTE 0x01 /* Mute */ + +#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */ +#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */ +#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */ +#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */ +#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */ +#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */ +#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */ + +/* + * DAC Defines: + */ + +#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */ + +#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */ +#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */ +#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */ + +#define DAC_REG1_AMUTE 0x80 /* Auto-mute */ + +#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */ +#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */ +#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */ +#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */ +#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */ +#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */ + +#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */ +#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */ +#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */ +#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */ + +#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */ +#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */ +#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */ +#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */ + +#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */ +#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */ +#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */ +#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */ +#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */ +#define DAC_REG5_FREEZE 0x04 /* Freeze */ +#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */ +#define DAC_REG5_RESERVED 0x01 /* Reserved */ + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard(void) +{ + printf ("SACSng\n"); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0; + volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8); + uint psdmr = CFG_PSDMR; + int i; + uint psrt = 14; /* for no SPD */ + uint chipselects = 1; /* for no SPD */ + uint sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CFG_OR2_PRELIM; /* for no SPD */ +#ifdef SDRAM_SPD_ADDR + uint data_width; + uint rows; + uint banks; + uint cols; + uint caslatency; + uint width; + uint rowst; + uint sdam; + uint bsma; + uint sda10; + u_char spd_size; + u_char data; + u_char cksum; + int j; +#endif + +#ifdef SDRAM_SPD_ADDR + /* Keep the compiler from complaining about potentially uninitialized vars */ + data_width = chipselects = rows = banks = cols = caslatency = psrt = 0; + + /* + * Read the SDRAM SPD EEPROM via I2C. + */ + i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); + spd_size = data; + cksum = data; + for(j = 1; j < 64; j++) { /* read only the checksummed bytes */ + /* note: the I2C address autoincrements when alen == 0 */ + i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); + if(j == 5) chipselects = data & 0x0F; + else if(j == 6) data_width = data; + else if(j == 7) data_width |= data << 8; + else if(j == 3) rows = data & 0x0F; + else if(j == 4) cols = data & 0x0F; + else if(j == 12) { + /* + * Refresh rate: this assumes the prescaler is set to + * approximately 1uSec per tick. + */ + switch(data & 0x7F) { + default: + case 0: psrt = 14 ; /* 15.625uS */ break; + case 1: psrt = 2; /* 3.9uS */ break; + case 2: psrt = 6; /* 7.8uS */ break; + case 3: psrt = 29; /* 31.3uS */ break; + case 4: psrt = 60; /* 62.5uS */ break; + case 5: psrt = 120; /* 125uS */ break; + } + } + else if(j == 17) banks = data; + else if(j == 18) { + caslatency = 3; /* default CL */ +#if(PESSIMISTIC_SDRAM) + if((data & 0x04) != 0) caslatency = 3; + else if((data & 0x02) != 0) caslatency = 2; + else if((data & 0x01) != 0) caslatency = 1; +#else + if((data & 0x01) != 0) caslatency = 1; + else if((data & 0x02) != 0) caslatency = 2; + else if((data & 0x04) != 0) caslatency = 3; +#endif + else { + printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", + data); + } + } + else if(j == 63) { + if(data != cksum) { + printf ("WARNING: Configuration data checksum failure:" + " is 0x%02x, calculated 0x%02x\n", + data, cksum); + } + } + cksum += data; + } + + /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ + if(caslatency < 2) { + printf("WARNING: CL was %d, forcing to 2\n", caslatency); + caslatency = 2; + } + if(rows > 14) { + printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows); + rows = 14; + } + if(cols > 11) { + printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols); + cols = 11; + } + + if((data_width != 64) && (data_width != 72)) + { + printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", + data_width); + } + width = 3; /* 2^3 = 8 bytes = 64 bits wide */ + /* + * Convert banks into log2(banks) + */ + if (banks == 2) banks = 1; + else if(banks == 4) banks = 2; + else if(banks == 8) banks = 3; + + sdram_size = 1 << (rows + cols + banks + width); + +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + rowst = ((32 - 6) - (rows + cols + width)) * 2; +#else + rowst = 32 - (rows + banks + cols + width); +#endif + + or = ~(sdram_size - 1) | /* SDAM address mask */ + ((banks-1) << 13) | /* banks per device */ + (rowst << 9) | /* rowst */ + ((rows - 9) << 6); /* numr */ + + memctl->memc_or2 = or; + + /* + * SDAM specifies the number of columns that are multiplexed + * (reference AN2165/D), defined to be (columns - 6) for page + * interleave, (columns - 8) for bank interleave. + * + * BSMA is 14 - max(rows, cols). The bank select lines come + * into play above the highest "address" line going into the + * the SDRAM. + */ +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + sdam = cols - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam + 2; +#else + sdam = cols - 6; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam; +#endif +#if(PESSIMISTIC_SDRAM) + psdmr = (CONFIG_PBI |\ + PSDMR_RFEN |\ + PSDMR_RFRC_16_CLK |\ + PSDMR_PRETOACT_8W |\ + PSDMR_ACTTORW_8W |\ + PSDMR_WRC_4C |\ + PSDMR_EAMUX |\ + PSDMR_BUFCMD) |\ + caslatency |\ + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ + (sdam << 24) |\ + (bsma << 21) |\ + (sda10 << 18); +#else + psdmr = (CONFIG_PBI |\ + PSDMR_RFEN |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \ + PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \ + PSDMR_WRC_1C | /* 1 clock + 7nSec */ + EAMUX |\ + BUFCMD) |\ + caslatency |\ + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ + (sdam << 24) |\ + (bsma << 21) |\ + (sda10 << 18); +#endif +#endif + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * Quote from Micron MT48LC8M16A2 data sheet: + * + * "...the SDRAM requires a 100uS delay prior to issuing any + * command other than a COMMAND INHIBIT or NOP. Starting at some + * point during this 100uS period and continuing at least through + * the end of this period, COMMAND INHIBIT or NOP commands should + * be applied." + * + * "Once the 100uS delay has been satisfied with at least one COMMAND + * INHIBIT or NOP command having been applied, a /PRECHARGE command/ + * should be applied. All banks must then be precharged, thereby + * placing the device in the all banks idle state." + * + * "Once in the idle state, /two/ AUTO REFRESH cycles must be + * performed. After the AUTO REFRESH cycles are complete, the + * SDRAM is ready for mode register programming." + * + * (/emphasis/ mine, gvb) + * + * The way I interpret this, Micron start up sequence is: + * 1. Issue a PRECHARGE-BANK command (initial precharge) + * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") + * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands + * 4. Issue a MODE-SET command to initialize the mode register + * + * -------- + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = psrt; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + + /* + * Do it a second time for the second set of chips if the DIMM has + * two chip selects (double sided). + */ + if(chipselects > 1) { + ramaddr += sdram_size; + + memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size; + memctl->memc_or3 = or; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + } + + /* return total ram size */ + return (sdram_size * chipselects); +} + +/*----------------------------------------------------------------------- + * Board Control Functions + */ +void board_poweroff (void) +{ + while (1); /* hang forever */ +} + + +#ifdef CONFIG_MISC_INIT_R +/* ------------------------------------------------------------------------- */ +int misc_init_r(void) +{ + /* + * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. + */ + volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */); + volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); + + int reg; /* I2C register value */ + char *ep; /* Environment pointer */ + char str_buf[12] ; /* sprintf output buffer */ + int sample_rate; /* ADC/DAC sample rate */ + int sample_64x; /* Use 64/4 clocking for the ADC/DAC */ + int sample_128x; /* Use 128/4 clocking for the ADC/DAC */ + int right_just; /* Is the data to the DAC right justified? */ + int mclk_divide; /* MCLK Divide */ + int quiet; /* Quiet or minimal output mode */ + + quiet = 0; + if ((ep = getenv("quiet")) != NULL) { + quiet = simple_strtol(ep, NULL, 10); + } + else { + setenv("quiet", "0"); + } + + /* + * SACSng custom initialization: + * Start the ADC and DAC clocks, since the Crystal parts do not + * work on the I2C bus until the clocks are running. + */ + + sample_rate = INITIAL_SAMPLE_RATE; + if ((ep = getenv("DaqSampleRate")) != NULL) { + sample_rate = simple_strtol(ep, NULL, 10); + } + + sample_64x = INITIAL_SAMPLE_64X; + sample_128x = INITIAL_SAMPLE_128X; + if ((ep = getenv("Daq64xSampling")) != NULL) { + sample_64x = simple_strtol(ep, NULL, 10); + if (sample_64x) { + sample_128x = 0; + } + else { + sample_128x = 1; + } + } + else { + if ((ep = getenv("Daq128xSampling")) != NULL) { + sample_128x = simple_strtol(ep, NULL, 10); + if (sample_128x) { + sample_64x = 0; + } + else { + sample_64x = 1; + } + } + } + + /* + * Stop the clocks and wait for at least 1 LRCLK period + * to make sure the clocking has really stopped. + */ + Daq_Stop_Clocks(); + udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); + + /* + * Initialize the clocks with the new rates + */ + Daq_Init_Clocks(sample_rate, sample_64x); + sample_rate = Daq_Get_SampleRate(); + + /* + * Start the clocks and wait for at least 1 LRCLK period + * to make sure the clocking has become stable. + */ + Daq_Start_Clocks(sample_rate); + udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); + + sprintf(str_buf, "%d", sample_rate); + setenv("DaqSampleRate", str_buf); + + if (sample_64x) { + setenv("Daq64xSampling", "1"); + setenv("Daq128xSampling", NULL); + } + else { + setenv("Daq64xSampling", NULL); + setenv("Daq128xSampling", "1"); + } + + /* + * Display the ADC/DAC clocking information + */ + if (!quiet) { + Daq_Display_Clocks(); + } + + /* + * Determine the DAC data justification + */ + + right_just = INITIAL_RIGHT_JUST; + if ((ep = getenv("DaqDACRightJustified")) != NULL) { + right_just = simple_strtol(ep, NULL, 10); + } + + sprintf(str_buf, "%d", right_just); + setenv("DaqDACRightJustified", str_buf); + + /* + * Determine the DAC MCLK Divide + */ + + mclk_divide = INITIAL_MCLK_DIVIDE; + if ((ep = getenv("DaqDACMClockDivide")) != NULL) { + mclk_divide = simple_strtol(ep, NULL, 10); + } + + sprintf(str_buf, "%d", mclk_divide); + setenv("DaqDACMClockDivide", str_buf); + + /* + * Initializing the I2C address in the Crystal A/Ds: + * + * 1) Wait for VREF cap to settle (10uSec per uF) + * 2) Release pullup on SDATA + * 3) Write the I2C address to register 6 + * 4) Enable address matching by setting the MSB in register 7 + */ + + if (!quiet) { + printf("Initializing the ADC...\n"); + } + udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */ + + iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */ + udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ + + i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */ + i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */ + ADC_REG7_ADDR_ENABLE); + + i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */ + (sample_64x ? 0 : ADC_REG2_128x) | + ADC_REG2_HIGH_PASS_DIS | + ADC_REG2_SLAVE_MODE); + + reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F; + if(reg != I2C_ADC_1_ADDR) + printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n", + reg, I2C_ADC_1_ADDR); + + iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */ + udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ + + i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */ + + i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */ + (sample_64x ? 0 : ADC_REG2_128x) | + ADC_REG2_HIGH_PASS_DIS | + ADC_REG2_SLAVE_MODE); + + reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F; + if(reg != I2C_ADC_2_ADDR) + printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n", + reg, I2C_ADC_2_ADDR); + + i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */ + ADC_REG1_FRAME_START | + ADC_REG1_GROUND_CAL); + + i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */ + (sample_64x ? 0 : ADC_REG2_128x) | + ADC_REG2_CAL | + ADC_REG2_HIGH_PASS_DIS | + ADC_REG2_SLAVE_MODE); + + udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */ + i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */ + + /* + * Now that we have synchronized the ADC's, enable address + * selection on the second ADC as well as the first. + */ + i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE); + + /* + * Initialize the Crystal DAC + * + * Two of the config lines are used for I2C so we have to set them + * to the proper initialization state without inadvertantly + * sending an I2C "start" sequence. When we bring the I2C back to + * the normal state, we send an I2C "stop" sequence. + */ + if (!quiet) { + printf("Initializing the DAC...\n"); + } + + /* + * Bring the I2C clock and data lines low for initialization + */ + I2C_SCL(0); + I2C_DELAY; + I2C_SDA(0); + I2C_ACTIVE; + I2C_DELAY; + + /* Reset the DAC */ + iopa->pdat &= ~DAC_RST_MASK; + udelay(DAC_RESET_DELAY); + + /* Release the DAC reset */ + iopa->pdat |= DAC_RST_MASK; + udelay(DAC_INITIAL_DELAY); + + /* + * Cause the DAC to: + * Enable control port (I2C mode) + * Going into power down + */ + i2c_reg_write(I2C_DAC_ADDR, 0x05, + DAC_REG5_I2C_MODE | + DAC_REG5_POWER_DOWN); + + /* + * Cause the DAC to: + * Enable control port (I2C mode) + * Going into power down + * . MCLK divide by 1 + * . MCLK divide by 2 + */ + i2c_reg_write(I2C_DAC_ADDR, 0x05, + DAC_REG5_I2C_MODE | + DAC_REG5_POWER_DOWN | + (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); + + /* + * Cause the DAC to: + * Auto-mute disabled + * . Format 0, left justified 24 bits + * . Format 3, right justified 24 bits + * No de-emphasis + * . Single speed mode + * . Double speed mode + */ + i2c_reg_write(I2C_DAC_ADDR, 0x01, + (right_just ? DAC_REG1_RIGHT_JUST_24BIT : + DAC_REG1_LEFT_JUST_24_BIT) | + DAC_REG1_DEM_NO | + (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE)); + + sprintf(str_buf, "%d", + sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE); + setenv("DaqDACFunctionalMode", str_buf); + + /* + * Cause the DAC to: + * Enable control port (I2C mode) + * Remove power down + * . MCLK divide by 1 + * . MCLK divide by 2 + */ + i2c_reg_write(I2C_DAC_ADDR, 0x05, + DAC_REG5_I2C_MODE | + (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); + + /* + * Create a I2C stop condition: + * low->high on data while clock is high. + */ + I2C_SCL(1); + I2C_DELAY; + I2C_SDA(1); + I2C_DELAY; + I2C_TRISTATE; + + if (!quiet) { + printf("\n"); + } + +#ifdef CONFIG_ETHER_LOOPBACK_TEST + /* + * Run the Ethernet loopback test + */ + eth_loopback_test (); +#endif /* CONFIG_ETHER_LOOPBACK_TEST */ + +#ifdef CONFIG_SHOW_BOOT_PROGRESS + /* + * Turn off the RED fail LED now that we are up and running. + */ + status_led_set(STATUS_LED_RED, STATUS_LED_OFF); +#endif + + return 0; +} + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +/* + * Show boot status: flash the LED if something goes wrong, indicating + * that last thing that worked and thus, by implication, what is broken. + * + * This stores the last OK value in RAM so this will not work properly + * before RAM is initialized. Since it is being used for indicating + * boot status (i.e. after RAM is initialized), that is OK. + */ +static void flash_code(uchar number, uchar modulo, uchar digits) +{ + int j; + + /* + * Recursively do upper digits. + */ + if(digits > 1) { + flash_code(number / modulo, modulo, digits - 1); + } + + number = number % modulo; + + /* + * Zero is indicated by one long flash (dash). + */ + if(number == 0) { + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); + udelay(1000000); + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); + udelay(200000); + } else { + /* + * Non-zero is indicated by short flashes, one per count. + */ + for(j = 0; j < number; j++) { + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); + udelay(100000); + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); + udelay(200000); + } + } + /* + * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total + */ + udelay(700000); +} + +static int last_boot_progress; + +void show_boot_progress (int status) +{ + int i,j; + if(status > 0) { + last_boot_progress = status; + } else { + /* + * If a specific failure code is given, flash this code + * else just use the last success code we've seen + */ + if(status < -1) + last_boot_progress = -status; + + /* + * Flash this code 5 times + */ + for(j=0; j<5; j++) { + /* + * Houston, we have a problem. + * Blink the last OK status which indicates where things failed. + */ + status_led_set(STATUS_LED_RED, STATUS_LED_ON); + flash_code(last_boot_progress, 5, 3); + + /* + * Delay 5 seconds between repetitions, + * with the fault LED blinking + */ + for(i=0; i<5; i++) { + status_led_set(STATUS_LED_RED, STATUS_LED_OFF); + udelay(500000); + status_led_set(STATUS_LED_RED, STATUS_LED_ON); + udelay(500000); + } + } + + /* + * Reset the board to retry initialization. + */ + do_reset (NULL, 0, 0, NULL); + } +} +#endif /* CONFIG_SHOW_BOOT_PROGRESS */ + + +/* + * The following are used to control the SPI chip selects for the SPI command. + */ +#if (CONFIG_COMMANDS & CFG_CMD_SPI) + +#define SPI_ADC_CS_MASK 0x00000800 +#define SPI_DAC_CS_MASK 0x00001000 + +void spi_adc_chipsel(int cs) +{ + volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); + + if(cs) + iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */ + else + iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */ +} + +void spi_dac_chipsel(int cs) +{ + volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); + + if(cs) + iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */ + else + iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */ +} + +/* + * The SPI command uses this table of functions for controlling the SPI + * chip selects: it calls the appropriate function to control the SPI + * chip selects. + */ +spi_chipsel_type spi_chipsel[] = { + spi_adc_chipsel, + spi_dac_chipsel +}; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +#endif /* CFG_CMD_SPI */ + +#endif /* CONFIG_MISC_INIT_R */ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} + +#endif diff --git a/board/sacsng/u-boot.lds b/board/sacsng/u-boot.lds new file mode 100644 index 0000000..9e623d0 --- /dev/null +++ b/board/sacsng/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c new file mode 100644 index 0000000..762fb73 --- /dev/null +++ b/board/sandburst/common/flash.c @@ -0,0 +1,512 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Ported from Ebony flash support + * Travis B. Sawyer + * Sandburst Corporation + */ +#include +#include +#include + + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { + {0xfff80000} /* Boot Flash */ +}; + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i=0; iflash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; + } + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); + + /* Write auto select command: read Manufacturer ID */ + udelay(10000); + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + udelay(1000); + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + udelay(1000); + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; + udelay(1000); + + value = addr2[0]; + + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; /* => 512 kb */ + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (info->flash_id == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* reset to return to reading data */ + addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + DEBUGF("Erasing sector %p\n", addr2); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + for (i=0; i<50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c new file mode 100644 index 0000000..859dd7a --- /dev/null +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -0,0 +1,512 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by + * Travis B. Sawyer + * Sandburst Corporation. + */ +#include +#include +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif +#include +#include <440_i2c.h> +#include +#include "ppc440gx_i2c.h" + +#ifdef CONFIG_I2C_BUS1 + +#define IIC_OK 0 +#define IIC_NOK 1 +#define IIC_NOK_LA 2 /* Lost arbitration */ +#define IIC_NOK_ICT 3 /* Incomplete transfer */ +#define IIC_NOK_XFRA 4 /* Transfer aborted */ +#define IIC_NOK_DATA 5 /* No data in buffer */ +#define IIC_NOK_TOUT 6 /* Transfer timeout */ + +#define IIC_TIMEOUT 1 /* 1 second */ +#if defined(CFG_I2C_NOPROBES) +static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; +#endif + +static void _i2c_bus1_reset (void) +{ + int i, status; + + /* Reset status register */ + /* write 1 in SCMP and IRQA to clear these fields */ + out8 (IIC_STS1, 0x0A); + + /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ + out8 (IIC_EXTSTS1, 0x8F); + __asm__ volatile ("eieio"); + + /* + * Get current state, reset bus + * only if no transfers are pending. + */ + i = 10; + do { + /* Get status */ + status = in8 (IIC_STS1); + udelay (500); /* 500us */ + i--; + } while ((status & IIC_STS_PT) && (i > 0)); + /* Soft reset controller */ + status = in8 (IIC_XTCNTLSS1); + out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST)); + __asm__ volatile ("eieio"); + + /* make sure where in initial state, data hi, clock hi */ + out8 (IIC_DIRECTCNTL1, 0xC); + for (i = 0; i < 10; i++) { + if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) { + /* clock until we get to known state */ + out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */ + udelay (100); /* 100us */ + out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */ + udelay (100); /* 100us */ + } else { + break; + } + } + /* send start condition */ + out8 (IIC_DIRECTCNTL1, 0x4); + udelay (1000); /* 1ms */ + /* send stop condition */ + out8 (IIC_DIRECTCNTL1, 0xC); + udelay (1000); /* 1ms */ + /* Unreset controller */ + out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST)); + udelay (1000); /* 1ms */ +} + +void i2c1_init (int speed, int slaveadd) +{ + sys_info_t sysInfo; + unsigned long freqOPB; + int val, divisor; + +#ifdef CFG_I2C_INIT_BOARD + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#endif + + /* Handle possible failed I2C state */ + /* FIXME: put this into i2c_init_board()? */ + _i2c_bus1_reset (); + + /* clear lo master address */ + out8 (IIC_LMADR1, 0); + + /* clear hi master address */ + out8 (IIC_HMADR1, 0); + + /* clear lo slave address */ + out8 (IIC_LSADR1, 0); + + /* clear hi slave address */ + out8 (IIC_HSADR1, 0); + + /* Clock divide Register */ + /* get OPB frequency */ + get_sys_info (&sysInfo); + freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; + /* set divisor according to freqOPB */ + divisor = (freqOPB - 1) / 10000000; + if (divisor == 0) + divisor = 1; + out8 (IIC_CLKDIV1, divisor); + + /* no interrupts */ + out8 (IIC_INTRMSK1, 0); + + /* clear transfer count */ + out8 (IIC_XFRCNT1, 0); + + /* clear extended control & stat */ + /* write 1 in SRC SRS SWC SWS to clear these fields */ + out8 (IIC_XTCNTLSS1, 0xF0); + + /* Mode Control Register + Flush Slave/Master data buffer */ + out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); + __asm__ volatile ("eieio"); + + + val = in8(IIC_MDCNTL1); + __asm__ volatile ("eieio"); + + /* Ignore General Call, slave transfers are ignored, + disable interrupts, exit unknown bus state, enable hold + SCL + 100kHz normaly or FastMode for 400kHz and above + */ + + val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL; + if( speed >= 400000 ){ + val |= IIC_MDCNTL_FSM; + } + out8 (IIC_MDCNTL1, val); + + /* clear control reg */ + out8 (IIC_CNTL1, 0x00); + __asm__ volatile ("eieio"); + +} + +/* + This code tries to use the features of the 405GP i2c + controller. It will transfer up to 4 bytes in one pass + on the loop. It only does out8(lbz) to the buffer when it + is possible to do out16(lhz) transfers. + + cmd_type is 0 for write 1 for read. + + addr_len can take any value from 0-255, it is only limited + by the char, we could make it larger if needed. If it is + 0 we skip the address write cycle. + + Typical case is a Write of an addr followd by a Read. The + IBM FAQ does not cover this. On the last byte of the write + we don't set the creg CHT bit, and on the first bytes of the + read we set the RPST bit. + + It does not support address only transfers, there must be + a data part. If you want to write the address yourself, put + it in the data pointer. + + It does not support transfer to/from address 0. + + It does not check XFRCNT. +*/ +static +int i2c_transfer1(unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], + unsigned short data_len ) +{ + unsigned char* ptr; + int reading; + int tran,cnt; + int result; + int status; + int i; + uchar creg; + + if( data == 0 || data_len == 0 ){ + /*Don't support data transfer of no length or to address 0*/ + printf( "i2c_transfer: bad call\n" ); + return IIC_NOK; + } + if( addr && addr_len ){ + ptr = addr; + cnt = addr_len; + reading = 0; + }else{ + ptr = data; + cnt = data_len; + reading = cmd_type; + } + + /*Clear Stop Complete Bit*/ + out8(IIC_STS1,IIC_STS_SCMP); + /* Check init */ + i=10; + do { + /* Get status */ + status = in8(IIC_STS1); + __asm__ volatile("eieio"); + i--; + } while ((status & IIC_STS_PT) && (i>0)); + + if (status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + return(result); + } + /*flush the Master/Slave Databuffers*/ + out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); + /*need to wait 4 OPB clocks? code below should take that long*/ + + /* 7-bit adressing */ + out8(IIC_HMADR1,0); + out8(IIC_LMADR1, chip); + __asm__ volatile("eieio"); + + tran = 0; + result = IIC_OK; + creg = 0; + + while ( tran != cnt && (result == IIC_OK)) { + int bc,j; + + /* Control register = + Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start, + Transfer is a sequence of transfers + */ + creg |= IIC_CNTL_PT; + + bc = (cnt - tran) > 4 ? 4 : + cnt - tran; + creg |= (bc-1)<<4; + /* if the real cmd type is write continue trans*/ + if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) ) + creg |= IIC_CNTL_CHT; + + if (reading) + creg |= IIC_CNTL_READ; + else { + for(j=0; j0)); + + if (status & IIC_STS_ERR) { + result = IIC_NOK; + status = in8 (IIC_EXTSTS1); + /* Lost arbitration? */ + if (status & IIC_EXTSTS_LA) + result = IIC_NOK_LA; + /* Incomplete transfer? */ + if (status & IIC_EXTSTS_ICT) + result = IIC_NOK_ICT; + /* Transfer aborted? */ + if (status & IIC_EXTSTS_XFRA) + result = IIC_NOK_XFRA; + } else if ( status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + } + /* Command is reading => get buffer */ + if ((reading) && (result == IIC_OK)) { + /* Are there data in buffer */ + if (status & IIC_STS_MDBS) { + /* + even if we have data we have to wait 4OPB clocks + for it to hit the front of the FIFO, after that + we can just read. We should check XFCNT here and + if the FIFO is full there is no need to wait. + */ + udelay (1); + for(j=0;jed (i.e. there was a chip at that address which + * drove the data line low). + */ + return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0); +} + + +int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + int ret; + + if ( alen > 4 ) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if ( alen > 0 ) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if( alen > 0 ) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { + printf( "I2c read: failed %d\n", ret); + return 1; + } + return 0; +} + +int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + + if ( alen > 4 ) { + printf ("I2C write: addr len %d not supported\n", alen); + return 1; + + } + if ( alen > 0 ) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if( alen > 0 ) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + + return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); +} + +/*----------------------------------------------------------------------- + * Read a register + */ +uchar i2c_reg_read1(uchar i2c_addr, uchar reg) +{ + uchar buf; + + i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1); + + return(buf); +} + +/*----------------------------------------------------------------------- + * Write a register + */ +void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write1(i2c_addr, reg, 1, &val, 1); +} + + +int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int j; +#if defined(CFG_I2C_NOPROBES) + int k, skip; +#endif + + puts ("Valid chip addresses:"); + for(j = 0; j < 128; j++) { +#if defined(CFG_I2C_NOPROBES) + skip = 0; + for (k = 0; k < sizeof(i2c_no_probes); k++){ + if (j == i2c_no_probes[k]){ + skip = 1; + break; + } + } + if (skip) + continue; +#endif + if(i2c_probe1(j) == 0) { + printf(" %02X", j); + } + } + putc ('\n'); + +#if defined(CFG_I2C_NOPROBES) + puts ("Excluded chip addresses:"); + for( k = 0; k < sizeof(i2c_no_probes); k++ ) + printf(" %02X", i2c_no_probes[k] ); + putc ('\n'); +#endif + + return 0; +} + +U_BOOT_CMD( + iprobe1, 1, 1, do_i2c1_probe, + "iprobe1 - probe to discover valid I2C chip addresses\n", + "\n -discover valid I2C chip addresses\n" +); + +#endif /* CONFIG_I2C_BUS1 */ diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h new file mode 100644 index 0000000..cd4fc86 --- /dev/null +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ported from i2c driver for ppc4xx by AS HARNOIS by + * Travis B. Sawyer + * Sandburst Corporation + */ +#include +#include +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif +#include + +#ifdef CONFIG_HARD_I2C + +#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500) +#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR +#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF) +#define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF) +#define IIC_LMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR) +#define IIC_HMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR) +#define IIC_CNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL) +#define IIC_MDCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL) +#define IIC_STS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS) +#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS) +#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR) +#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR) +#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV) +#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK) +#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT) +#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS) +#define IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL) + +void i2c1_init (int speed, int slaveadd); +int i2c_probe1 (uchar chip); +int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len); +int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len); +uchar i2c_reg_read1(uchar i2c_addr, uchar reg); +void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val); + +#endif /* CONFIG_HARD_I2C */ diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c new file mode 100644 index 0000000..3530416 --- /dev/null +++ b/board/sandburst/common/sb_common.c @@ -0,0 +1,451 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include "ppc440gx_i2c.h" +#include "sb_common.h" + +long int fixed_sdram (void); + +/************************************************************************* + * metrobox_get_master + * + * PRI_N - active low signal. If the GPIO pin is low we are the master + * + ************************************************************************/ +int sbcommon_get_master(void) +{ + ppc440_gpio_regs_t *gpio_regs; + + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + + if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { + return 0; + } + else { + return 1; + } +} + +/************************************************************************* + * metrobox_secondary_present + * + * Figure out if secondary/slave board is present + * + ************************************************************************/ +int sbcommon_secondary_present(void) +{ + ppc440_gpio_regs_t *gpio_regs; + + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + + if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) + return 0; + else + return 1; +} + +/************************************************************************* + * sbcommon_get_serial_number + * + * Retrieve the board serial number via the mac address in eeprom + * + ************************************************************************/ +unsigned short sbcommon_get_serial_number(void) +{ + unsigned char buff[0x100]; + unsigned short sernum; + + /* Get the board serial number from eeprom */ + /* Initialize I2C */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read 256 bytes in EEPROM */ + i2c_read (0x50, 0, 1, buff, 0x100); + + memcpy(&sernum, &buff[0xF4], 2); + sernum /= 32; + + return (sernum); +} + +/************************************************************************* + * sbcommon_fans + * + * Spin up fans 2 & 3 to get some air moving. OS will take care + * of the rest. This is mostly a precaution... + * + * Assumes i2c bus 1 is ready. + * + ************************************************************************/ +void sbcommon_fans(void) +{ + /* + * Attempt to turn on 2 of the fans... + * Need to go through the bridge + */ + puts ("FANS: "); + + /* select fan4 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x08); /* val = bus 4 */ + + /* Turn on FAN 4 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 4 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + /* select fan3 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x04); /* val = bus 3 */ + + /* Turn on FAN 3 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 3 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + /* select fan2 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x02); /* val = bus 4 */ + + /* Turn on FAN 2 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 2 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + /* select fan1 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x01); /* val = bus 0 */ + + /* Turn on FAN 1 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 1 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + puts ("on\n"); + + return; + +} + +/************************************************************************* + * initdram + * + * Initialize sdram + * + ************************************************************************/ +long int initdram (int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (0); +#else + dram_size = fixed_sdram (); +#endif + return dram_size; +} + + +/************************************************************************* + * testdram + * + * + ************************************************************************/ +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing SDRAM: "); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("OK\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + * + * Assumes: 128 MB, non-ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +long int fixed_sdram (void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + /* RA=10 RD=3 */ + mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + udelay (400); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + for (;;) { + mfsdram (mem_mcsts, reg); + if (reg & 0x80000000) + break; + } + + return (128 * 1024 * 1024); /* 128 MB */ +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The metrobox is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + + +/************************************************************************* + * is_pci_host + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* The metrobox is always configured as host. */ + return(1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * board_get_enetaddr + * + * Get the ethernet MAC address for the management ethernet from the + * strap EEPROM. Note that is the BASE address for the range of + * external ethernet MACs on the board. The base + 31 is the actual + * mgmt mac address. + * + ************************************************************************/ +static int macaddr_idx = 0; + +void board_get_enetaddr (uchar * enet) +{ + int i; + unsigned short tmp; + unsigned char buff[0x100], *cp; + + if (0 == macaddr_idx) { + + /* Initialize I2C */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read 256 bytes in EEPROM */ + i2c_read (0x50, 0, 1, buff, 0x100); + + cp = &buff[0xF0]; + + for (i = 0; i < 6; i++,cp++) + enet[i] = *cp; + + memcpy(&tmp, &enet[4], 2); + tmp += 31; + memcpy(&enet[4], &tmp, 2); + + macaddr_idx++; + } else { + enet[0] = 0x02; + enet[1] = 0x00; + enet[2] = 0x00; + enet[3] = 0x00; + enet[4] = 0x00; + if (1 == sbcommon_get_master() ) { + /* Master/Primary card */ + enet[5] = 0x01; + } else { + /* Slave/Secondary card */ + enet [5] = 0x02; + } + } + + return; +} + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + + return (ctrlc()); +} +#endif diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h new file mode 100644 index 0000000..888e4f0 --- /dev/null +++ b/board/sandburst/common/sb_common.h @@ -0,0 +1,76 @@ +#ifndef __SBCOMMON_H__ +#define __SBCOMMON_H__ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include "ppc440gx_i2c.h" + +/* + * GPIO Settings + */ +/* Chassis settings */ +#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */ +#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */ + +/* Debug LEDs */ +#define SBCOMMON_GPIO_DBGLED_0 0x00000400 +#define SBCOMMON_GPIO_DBGLED_1 0x00000200 +#define SBCOMMON_GPIO_DBGLED_2 0x00100000 +#define SBCOMMON_GPIO_DBGLED_3 0x00000100 + +#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \ + SBCOMMON_GPIO_DBGLED_1 | \ + SBCOMMON_GPIO_DBGLED_2 | \ + SBCOMMON_GPIO_DBGLED_3) + +#define SBCOMMON_GPIO_SYS_FAULT 0x00000080 +#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040 +#define SBCOMMON_GPIO_SYS_STATUS 0x00000020 + +#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS) + +#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \ + SBCOMMON_GPIO_DBGLED_1 | \ + SBCOMMON_GPIO_DBGLED_2 | \ + SBCOMMON_GPIO_DBGLED_3 | \ + SBCOMMON_GPIO_SYS_STATUS) + +typedef struct ppc440_gpio_regs { + volatile unsigned long out; + volatile unsigned long tri_state; + volatile unsigned long dummy[4]; + volatile unsigned long open_drain; + volatile unsigned long in; +} __attribute__((packed)) ppc440_gpio_regs_t; + +int sbcommon_get_master(void); +int sbcommon_secondary_present(void); +unsigned short sbcommon_get_serial_number(void); +void sbcommon_fans(void); + +#endif /* __SBCOMMON_H__ */ diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile new file mode 100644 index 0000000..8b3173c --- /dev/null +++ b/board/sandburst/karef/Makefile @@ -0,0 +1,59 @@ +# +# (C) Copyright 2005 +# Sandburst Corporation +# Travis B. Sawyer +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# TBS: add for debugging purposes +BUILDUSER := $(shell whoami) +FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) + +CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' +# TBS: end debugging + + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ + ../common/sb_common.o + +SOBJS = init.o + + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk new file mode 100644 index 0000000..65c1e48 --- /dev/null +++ b/board/sandburst/karef/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2005 +# Sandburst Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Sandburst Corporation Metrobox Reference Design +# Travis B. Sawyer +# + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h new file mode 100644 index 0000000..cc501c9 --- /dev/null +++ b/board/sandburst/karef/hal_ka_of_auto.h @@ -0,0 +1,324 @@ +/* **************************************************************** + * Common defs for reg spec for chip ka_of + * Auto-generated by trex2: DO NOT HAND-EDIT!! + * **************************************************************** + */ + +#ifndef HAL_KA_OF_AUTO_H +#define HAL_KA_OF_AUTO_H + + +/* ---------------------------------------------------------------- + * For block: 'ofem' + */ + +/* ---- Block instance addressing (for block-select) */ +#define OFEM_BLOCK_ADDR_BIT_L 6 +#define OFEM_BLOCK_ADDR_BIT_H 9 +#define OFEM_BLOCK_ADDR_WIDTH 4 + +#define OFEM_ADDR 0x0 + +/* ---- Reg addressing (within block) */ +#define OFEM_REG_ADDR_BIT_L 2 +#define OFEM_REG_ADDR_BIT_H 5 +#define OFEM_REG_ADDR_WIDTH 4 + + +/* ================================================================ + * ---- Register KA_OF_OFEM_REVISION */ +#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000 +#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31 +#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_RESET */ +#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004 +#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31 +#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_CNTL */ +#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018 +#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31 +#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */ +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c +#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_INTERRUPT */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008 +#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_INTERRUPT_MASK */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c +#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_SCRATCH */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010 +#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_SCRATCH_MASK */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014 +#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0 + +/* ================================================================ + * Field info for register KA_OF_OFEM_REVISION */ +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_RESET */ +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_CNTL */ +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */ +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_INTERRUPT */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_INTERRUPT_MASK */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register KA_OF_OFEM_SCRATCH */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_SCRATCH_MASK */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff + +#endif /* matches #ifndef HAL_KA_OF_AUTO_H */ diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h new file mode 100644 index 0000000..db1cec2 --- /dev/null +++ b/board/sandburst/karef/hal_ka_sc_auto.h @@ -0,0 +1,836 @@ +/* **************************************************************** + * Common defs for reg spec for chip ka_sc + * Auto-generated by trex2: DO NOT HAND-EDIT!! + * **************************************************************** + */ + +#ifndef HAL_KA_SC_AUTO_H +#define HAL_KA_SC_AUTO_H + + +/* ---------------------------------------------------------------- + * For block: 'scan' + */ + +/* ---- Block instance addressing (for block-select) */ +#define SCAN_BLOCK_ADDR_BIT_L 7 +#define SCAN_BLOCK_ADDR_BIT_H 9 +#define SCAN_BLOCK_ADDR_WIDTH 3 + +#define SCAN_ADDR 0x0 + +/* ---- Reg addressing (within block) */ +#define SCAN_REG_ADDR_BIT_L 2 +#define SCAN_REG_ADDR_BIT_H 6 +#define SCAN_REG_ADDR_WIDTH 5 + + +/* ================================================================ + * ---- Register KA_SC_SCAN_REVISION */ +#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000 +#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31 +#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_RESET */ +#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004 +#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31 +#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_STATUS */ +#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008 +#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31 +#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_CNTL */ +#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c +#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31 +#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_INFO */ +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020 +#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_FROM_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_FROM_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_TO_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_TO_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_CTRL */ +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_PLL_CTRL */ +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038 +#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c +#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_DR_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040 +#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044 +#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048 +#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c +#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_BRD_IN */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050 +#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_MISC */ +#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054 +#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31 +#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_INTERRUPT */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c +#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_INTERRUPT_MASK */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010 +#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCRATCH */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014 +#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCRATCH_MASK */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018 +#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0 + +/* ================================================================ + * Field info for register KA_SC_SCAN_REVISION */ +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_RESET */ +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_STATUS */ +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_CNTL */ +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_INFO */ +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_FROM_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_FROM_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_TO_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_TO_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_CTRL */ +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_PLL_CTRL */ +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_DR_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_BRD_IN */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_MISC */ +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_INTERRUPT */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_INTERRUPT_MASK */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCRATCH */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCRATCH_MASK */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff + +#endif /* matches #ifndef HAL_KA_SC_AUTO_H */ diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S new file mode 100644 index 0000000..b1d47a4 --- /dev/null +++ b/board/sandburst/karef/init.S @@ -0,0 +1,101 @@ +/* +* Copyright (C) 2005 Sandburst Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ +/* + * Ported from Ebony init.S by Travis B. Sawyer + */ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c new file mode 100644 index 0000000..2d71d3b --- /dev/null +++ b/board/sandburst/karef/karef.c @@ -0,0 +1,570 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "karef.h" +#include "karef_version.h" +#include +#include +#include +#include +#include "../common/sb_common.h" +#include "../common/ppc440gx_i2c.h" + +void fpga_init (void); + +KAREF_BOARD_ID_ST board_id_as[] = +{ + {"Undefined"}, /* Not specified */ + {"Kamino Reference Design"}, + {"Reserved"}, /* Reserved for future use */ + {"Reserved"}, /* Reserved for future use */ +}; + +KAREF_BOARD_ID_ST ofem_board_id_as[] = +{ + {"Undefined"}, + {"1x10 + 10x2"}, + {"Reserved"}, + {"Reserved"}, +}; + +/************************************************************************* + * board_early_init_f + * + * Setup chip selects, initialize the Opto-FPGA, initialize + * interrupt polarity and triggers. + ************************************************************************/ +int board_early_init_f (void) +{ + ppc440_gpio_regs_t *gpio_regs; + + /* Enable GPIO interrupts */ + mtsdr(sdr_pfc0, 0x00103E00); + + /* Setup access for LEDs, and system topology info */ + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; + gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; + + /* Turn on all the leds for now */ + gpio_regs->out = SBCOMMON_GPIO_LEDS; + + /*--------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------*/ + mtebc(xbcfg, + EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | + EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | + EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | + EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | + EBC_CFG_PR_32); + + /*--------------------------------------------------------------------+ + | 1/2 MB FLASH. Initialize bank 0 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb0ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + /*--------------------------------------------------------------------+ + | 8KB NVRAM/RTC. Initialize bank 1 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb1ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb2ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | KaRef Scan FPGA. Initialize bank 3 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb5ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | MAC A & B for Kamino. OFEM FPGA decodes the addresses + | Initialize bank 4 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb4ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | OFEM FPGA Initialize bank 5 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb3ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + + mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb6ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | BME-32. Initialize bank 7 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb7ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + * Setup the interrupt controller polarities, triggers, etc. + +-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non- critical */ + mtdcr (uic0pr, 0xfffffe03); /* polarity */ + mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffc8ff); /* polarity */ + mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffff83ff); /* polarity */ + mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); + mtdcr (uicb0tr, 0x00000000); + mtdcr (uicb0vr, 0x00000001); + + fpga_init(); + + return 0; +} + + +/************************************************************************* + * checkboard + * + * Dump pertinent info to the console + ************************************************************************/ +int checkboard (void) +{ + sys_info_t sysinfo; + unsigned char brd_rev, brd_id; + unsigned short sernum; + unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0; + unsigned char ofem_brd_rev, ofem_brd_id; + KAREF_FPGA_REGS_ST *karef_ps; + OFEM_FPGA_REGS_ST *ofem_ps; + + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + + scan_id = (unsigned char)((karef_ps->revision_ul & + SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) + >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT); + + scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK) + >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT); + + brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT); + + brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT); + + ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); + + ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT); + + if (0xF != ofem_brd_id) { + ofem_id = (unsigned char)((ofem_ps->revision_ul & + SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK) + >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT); + + ofem_rev = (unsigned char)((ofem_ps->revision_ul & + SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK) + >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT); + } + + get_sys_info (&sysinfo); + + sernum = sbcommon_get_serial_number(); + + printf ("Board: Sandburst Corporation Kamino Reference Design " + "Serial Number: %d\n", sernum); + printf ("%s\n", KAREF_U_BOOT_REL_STR); + + printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); + if (sbcommon_get_master()) { + printf("Slot 0 - Master\nSlave board"); + if (sbcommon_secondary_present()) + printf(" present\n"); + else + printf(" not detected\n"); + } else { + printf("Slot 1 - Slave\n\n"); + } + + printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev); + printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id); + if(0xF != ofem_brd_id) { + printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev); + printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev); + } + + /* Fix the ack in the bme 32 */ + udelay(5000); + out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + asm("eieio"); + + + return (0); +} + +/************************************************************************* + * misc_init_f + * + * Initialize I2C bus one to gain access to the fans + ************************************************************************/ +int misc_init_f (void) +{ + /* Turn on i2c bus 1 */ + puts ("I2C1: "); + i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + puts ("ready\n"); + + /* Turn on fans 3 & 4 */ + sbcommon_fans(); + + return (0); +} + +/************************************************************************* + * misc_init_r + * + * Do nothing. + ************************************************************************/ +int misc_init_r (void) +{ + unsigned short sernum; + char envstr[255]; + KAREF_FPGA_REGS_ST *karef_ps; + OFEM_FPGA_REGS_ST *ofem_ps; + + if(NULL != getenv("secondserial")) { + puts("secondserial is set, switching to second serial port\n"); + setenv("stderr", "serial1"); + setenv("stdout", "serial1"); + setenv("stdin", "serial1"); + } + + setenv("ubrelver", KAREF_U_BOOT_REL_STR); + + memset(envstr, 0, 255); + sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); + setenv("bldstr", envstr); + saveenv(); + + if( getenv("autorecover")) { + setenv("autorecover", NULL); + saveenv(); + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for automatic filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", + sernum, sernum); + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type allow the system to continue to boot\n"); + } + + if( getenv("fakeled")) { + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; + karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; + setenv("bootdelay", "-1"); + saveenv(); + printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); + } + + return (0); +} + +/************************************************************************* + * ide_set_reset + ************************************************************************/ +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) +{ + KAREF_FPGA_REGS_ST *karef_ps; + /* TODO: ide reset */ + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + + if (on) { + karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; + } else { + karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; + } +} +#endif /* CONFIG_IDE_RESET */ + +/************************************************************************* + * fpga_init + ************************************************************************/ +void fpga_init(void) +{ + KAREF_FPGA_REGS_ST *karef_ps; + OFEM_FPGA_REGS_ST *ofem_ps; + unsigned char ofem_id; + unsigned long tmp; + + /* Ensure we have power all around */ + udelay(500); + + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + tmp = + SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK; + + karef_ps->reset_ul = tmp; + + /* + * Wait a bit to allow the ofem fpga to get its brains + */ + udelay(5000); + + /* + * Check to see if the ofem is there + */ + ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); + if(0xF != ofem_id) { + tmp = + SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK | + SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | + SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; + + ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + ofem_ps->reset_ul = tmp; + + ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; + } + + karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT; + + asm("eieio"); + + return; +} + +int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + memset(envstr, 0, 255); + /* + * Setup our ip address + */ + sprintf(envstr, "10.100.70.%d", sernum); + + setenv("ipaddr", envstr); + /* + * Setup the host ip address + */ + setenv("serverip", "10.100.17.10"); + + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " + "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d " + "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:" + "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33", + sernum, sernum, sernum); + + setenv("bootargs_nfs", envstr); + setenv("bootargs", envstr); + + /* + * Setup CF bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " + "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", + sernum, sernum); + + setenv("bootargs_cf", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000"); + setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000"); + + /* + * Setup compact flash boot command + */ + setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000"); + + saveenv(); + + return(1); +} + +int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none", + sernum, sernum); + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + + setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type boot.\nWhen the kernel has booted" + " please type fsrecover.sh\n"); + + return(1); +} + +U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, + "kasetup - Set environment to factory defaults\n", NULL); + +U_BOOT_CMD(karecover, 1, 1, karefRecover, + "karecover - Set environment to allow for fs recovery\n", NULL); diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h new file mode 100644 index 0000000..5de7cb5 --- /dev/null +++ b/board/sandburst/karef/karef.h @@ -0,0 +1,76 @@ +#ifndef __KAREF_H__ +#define __KAREF_H__ +/* + * (C) Copyright 2005 + * Sandburst Corporation + * Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Ka Reference Design OFEM FPGA Registers & definitions */ +#include "hal_ka_sc_auto.h" +#include "hal_ka_of_auto.h" + +typedef struct karef_board_id_s { + const char name[40]; +} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST; + +/* SCAN FPGA */ +typedef struct karef_fpga_regs_s +{ + volatile unsigned long revision_ul; /* Read Only */ + volatile unsigned long reset_ul; /* Read/Write */ + volatile unsigned long interrupt_ul; /* Read Only */ + volatile unsigned long mask_ul; /* Read/Write */ + volatile unsigned long scratch_ul; /* Read/Write */ + volatile unsigned long scrmask_ul; /* Read/Write */ + volatile unsigned long status_ul; /* Read Only */ + volatile unsigned long control_ul; /* Read/Write */ + volatile unsigned long boardinfo_ul; /* Read Only */ + volatile unsigned long scan_from0_ul; /* Read Only */ + volatile unsigned long scan_from1_ul; /* Read Only */ + volatile unsigned long scan_to0_ul; /* Read/Write */ + volatile unsigned long scan_to1_ul; /* Read/Write */ + volatile unsigned long scan_control_ul; /* Read/Write */ + volatile unsigned long pll_control_ul; /* Read/Write */ + volatile unsigned long core_clock_cnt_ul; /* Read/Write */ + volatile unsigned long dr_clock_cnt_ul; /* Read/Write */ + volatile unsigned long spi_clock_cnt_ul; /* Read/Write */ + volatile unsigned long brdout_data_ul; /* Read/Write */ + volatile unsigned long brdout_enable_ul; /* Read/Write */ + volatile unsigned long brdin_data_ul; /* Read Only */ + volatile unsigned long misc_ul; /* Read/Write */ +} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST; + +/* OFEM FPGA */ +typedef struct ofem_fpga_regs_s +{ + volatile unsigned long revision_ul; /* Read Only */ + volatile unsigned long reset_ul; /* Read/Write */ + volatile unsigned long interrupt_ul; /* Read Only */ + volatile unsigned long mask_ul; /* Read/Write */ + volatile unsigned long scratch_ul; /* Read/Write */ + volatile unsigned long scrmask_ul; /* Read/Write */ + volatile unsigned long control_ul; /* Read/Write */ + volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */ +} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST; + + +#endif /* __KAREF_H__ */ diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h new file mode 100644 index 0000000..9960b9a --- /dev/null +++ b/board/sandburst/karef/karef_version.h @@ -0,0 +1,26 @@ +#ifndef _KAREF_VERSION_H_ +#define _KAREF_VERSION_H_ +/* + * Copyright (C) 2005 Sandburst Corporation + * Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define KAREF_U_BOOT_REL_STR "Release 0.0.7" +#endif diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds new file mode 100644 index 0000000..9e9e990 --- /dev/null +++ b/board/sandburst/karef/u-boot.lds @@ -0,0 +1,159 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/karef/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug new file mode 100644 index 0000000..47d80fa --- /dev/null +++ b/board/sandburst/karef/u-boot.lds.debug @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/karef/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile new file mode 100644 index 0000000..06a9a22 --- /dev/null +++ b/board/sandburst/metrobox/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2005 +# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# TBS: add for debugging purposes +BUILDUSER := $(shell whoami) +FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) + +CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' +# TBS: end debugging + + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ + ../common/sb_common.o +SOBJS = init.o + + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk new file mode 100644 index 0000000..91aee2f --- /dev/null +++ b/board/sandburst/metrobox/config.mk @@ -0,0 +1,38 @@ +# +# (C) Copyright 2005 +# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h new file mode 100644 index 0000000..c99b38c --- /dev/null +++ b/board/sandburst/metrobox/hal_xc_auto.h @@ -0,0 +1,553 @@ +/* **************************************************************** + * Common defs for reg spec for chip xc + * Auto-generated by trex2: DO NOT HAND-EDIT!! + * **************************************************************** + */ + +#ifndef HAL_XC_AUTO_H +#define HAL_XC_AUTO_H + +/* ---------------------------------------------------------------- + * For block: 'xcvr_cntl' + */ + +/* ---- Block instance addressing (for block-select) */ +#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6 +#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9 +#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4 + +#define XCVR_CNTL_ADDR 0x0 + +/* ---- Reg addressing (within block) */ +#define XCVR_CNTL_REG_ADDR_BIT_L 2 +#define XCVR_CNTL_REG_ADDR_BIT_H 5 +#define XCVR_CNTL_REG_ADDR_WIDTH 4 + + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_REVISION */ +#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000 +#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_RESET */ +#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004 +#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_STATUS */ +#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008 +#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_CNTL */ +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c +#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_BRD_INFO */ +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020 +#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */ +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024 +#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_INTERRUPT */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c +#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010 +#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_SCRATCH */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014 +#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018 +#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_REVISION */ +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_RESET */ +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_STATUS */ +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_CNTL */ +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_BRD_INFO */ +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */ +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_INTERRUPT */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_SCRATCH */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff + +#endif /* matches #ifndef HAL_XC_AUTO_H */ diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S new file mode 100644 index 0000000..e398f00 --- /dev/null +++ b/board/sandburst/metrobox/init.S @@ -0,0 +1,99 @@ +/* +* Copyright (C) 2005 +* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c new file mode 100644 index 0000000..86d259f --- /dev/null +++ b/board/sandburst/metrobox/metrobox.c @@ -0,0 +1,536 @@ +/* + * Copyright (c) 2005 + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include "metrobox.h" +#include "metrobox_version.h" +#include +#include +#include +#include +#include "../common/ppc440gx_i2c.h" +#include "../common/sb_common.h" + +void fpga_init (void); + +METROBOX_BOARD_ID_ST board_id_as[] = +{ {"Undefined"}, /* Not specified */ + {"2x10Gb"}, /* 2 ports, 10 GbE */ + {"20x1Gb"}, /* 20 ports, 1 GbE */ + {"Reserved"}, /* Reserved for future use */ +}; + +/************************************************************************* + * board_early_init_f + * + * Setup chip selects, initialize the Opto-FPGA, initialize + * interrupt polarity and triggers. + ************************************************************************/ +int board_early_init_f (void) +{ + ppc440_gpio_regs_t *gpio_regs; + + /* Enable GPIO interrupts */ + mtsdr(sdr_pfc0, 0x00103E00); + + /* Setup access for LEDs, and system topology info */ + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; + gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; + + /* Turn on all the leds for now */ + gpio_regs->out = SBCOMMON_GPIO_LEDS; + + /*--------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------*/ + mtebc(xbcfg, + EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | + EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | + EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | + EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | + EBC_CFG_PR_32); + + /*--------------------------------------------------------------------+ + | 1/2 MB FLASH. Initialize bank 0 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb0ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + /*--------------------------------------------------------------------+ + | 8KB NVRAM/RTC. Initialize bank 1 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb1ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb2ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | OPTO & OFEM FPGA. Initialize bank 3 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb3ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | MAC A for metrobox + | MAC A & B for Kamino. OFEM FPGA decodes the addresses + | Initialize bank 4 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb4ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | Metrobox MAC B Initialize bank 5 with default values. + | KA REF FPGA Initialize bank 5 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb5ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb6ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | BME-32. Initialize bank 7 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb7ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + * Setup the interrupt controller polarities, triggers, etc. + +-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non- critical */ + mtdcr (uic0pr, 0xfffffe03); /* polarity */ + mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffc8ff); /* polarity */ + mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffff83ff); /* polarity */ + mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); + mtdcr (uicb0tr, 0x00000000); + mtdcr (uicb0vr, 0x00000001); + + fpga_init(); + + return 0; +} + +/************************************************************************* + * checkboard + * + * Dump pertinent info to the console + ************************************************************************/ +int checkboard (void) +{ + sys_info_t sysinfo; + unsigned char brd_rev, brd_id; + unsigned short sernum; + unsigned char opto_rev, opto_id; + OPTO_FPGA_REGS_ST *opto_ps; + + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + opto_rev = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); + + opto_id = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT); + + brd_rev = (unsigned char)((opto_ps->boardinfo_ul & + SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK) + >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT); + + brd_id = (unsigned char)((opto_ps->boardinfo_ul & + SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK) + >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT); + + get_sys_info (&sysinfo); + + sernum = sbcommon_get_serial_number(); + printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum); + printf ("%s\n", METROBOX_U_BOOT_REL_STR); + + printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); + if (sbcommon_get_master()) { + printf("Slot 0 - Master\nSlave board"); + if (sbcommon_secondary_present()) + printf(" present\n"); + else + printf(" not detected\n"); + } else { + printf("Slot 1 - Slave\n\n"); + } + + printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev); + printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]); + + /* Fix the ack in the bme 32 */ + udelay(5000); + out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + asm("eieio"); + + + return (0); +} + +/************************************************************************* + * misc_init_f + * + * Initialize I2C bus one to gain access to the fans + ************************************************************************/ +int misc_init_f (void) +{ + /* Turn on i2c bus 1 */ + puts ("I2C1: "); + i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + puts ("ready\n"); + + /* Turn on fans */ + sbcommon_fans(); + + return (0); +} + +/************************************************************************* + * misc_init_r + * + * Do nothing. + ************************************************************************/ +int misc_init_r (void) +{ + unsigned short sernum; + char envstr[255]; + unsigned char opto_rev; + OPTO_FPGA_REGS_ST *opto_ps; + + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + if(NULL != getenv("secondserial")) { + puts("secondserial is set, switching to second serial port\n"); + setenv("stderr", "serial1"); + setenv("stdout", "serial1"); + setenv("stdin", "serial1"); + } + + setenv("ubrelver", METROBOX_U_BOOT_REL_STR); + + memset(envstr, 0, 255); + sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); + setenv("bldstr", envstr); + saveenv(); + + if( getenv("autorecover")) { + setenv("autorecover", NULL); + saveenv(); + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for automatic filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", + sernum, sernum); + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type allow the system to continue to boot\n"); + } + + if( getenv("fakeled")) { + setenv("bootdelay", "-1"); + saveenv(); + printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); + opto_rev = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); + + if(0x12 <= opto_rev) { + opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK; + } + } + + return (0); +} + +/************************************************************************* + * ide_set_reset + ************************************************************************/ +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) +{ + OPTO_FPGA_REGS_ST *opto_ps; + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + if (on) { /* assert RESET */ + opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; + } else { /* release RESET */ + opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; + } +} +#endif /* CONFIG_IDE_RESET */ + +/************************************************************************* + * fpga_init + ************************************************************************/ +void fpga_init(void) +{ + OPTO_FPGA_REGS_ST *opto_ps; + unsigned char opto_rev; + unsigned long tmp; + + /* Ensure we have power all around */ + udelay(500); + + /* + * Take appropriate hw bits out of reset + */ + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + tmp = + SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK; + opto_ps->reset_ul = tmp; + /* + * Turn on the 'Slow Blink' for the System Error Led. + * Ensure FPGA rev is up to at least rev 0x12 + */ + opto_rev = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); + if(0x12 <= opto_rev) { + opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT; + } + + asm("eieio"); + + return; +} + +int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + memset(envstr, 0, 255); + /* + * Setup our ip address + */ + sprintf(envstr, "10.100.60.%d", sernum); + + setenv("ipaddr", envstr); + /* + * Setup the host ip address + */ + setenv("serverip", "10.100.17.10"); + + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " + "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d " + "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1" + ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33", + sernum, sernum, sernum); + + setenv("bootargs_nfs", envstr); + setenv("bootargs", envstr); + + /* + * Setup CF bootargs + */ + memset(envstr, 0, 255); + sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " + "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", + sernum, sernum); + + setenv("bootargs_cf", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000"); + setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000"); + + /* + * Setup compact flash boot command + */ + setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000"); + + saveenv(); + + + return(1); +} + +int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none", + sernum, sernum); + + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type boot.\nWhen the kernel has booted" + " please type fsrecover.sh\n"); + + return(1); +} + +U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars, + "mbsetup - Set environment to factory defaults\n", NULL); + +U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover, + "mbrecover - Set environment to allow for fs recovery\n", NULL); diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h new file mode 100644 index 0000000..3f28f00 --- /dev/null +++ b/board/sandburst/metrobox/metrobox.h @@ -0,0 +1,45 @@ +#ifndef __METROBOX_H__ +#define __METROBOX_H__ +/* + * (C) Copyright 2005 + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +typedef struct metrobox_board_id_s { + const char name[40]; +} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST; + + +/* Metrobox Opto-FPGA registers and definitions */ +#include "hal_xc_auto.h" +typedef struct opto_fpga_regs_s { + volatile unsigned long revision_ul; /* Read Only */ + volatile unsigned long reset_ul; /* Read/Write */ + volatile unsigned long status_ul; /* Read Only */ + volatile unsigned long interrupt_ul; /* Read Only */ + volatile unsigned long mask_ul; /* Read/Write */ + volatile unsigned long scratch_ul; /* Read/Write */ + volatile unsigned long scrmask_ul; /* Read/Write */ + volatile unsigned long control_ul; /* Read/Write */ + volatile unsigned long boardinfo_ul; /* Read Only */ +} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST; + +#endif /* __METROBOX_H__ */ diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h new file mode 100644 index 0000000..1b6fee5 --- /dev/null +++ b/board/sandburst/metrobox/metrobox_version.h @@ -0,0 +1,27 @@ +#ifndef _METROBOX_VERSION_H_ +#define _METROBOX_VERSION_H_ +/* + * (C) Copyright 2005 + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define METROBOX_U_BOOT_REL_STR "Release 2.0.3" + +#endif diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds new file mode 100644 index 0000000..a17401a --- /dev/null +++ b/board/sandburst/metrobox/u-boot.lds @@ -0,0 +1,159 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/metrobox/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug new file mode 100644 index 0000000..fef4c42 --- /dev/null +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/metrobox/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile new file mode 100644 index 0000000..d6bbf2f --- /dev/null +++ b/board/sandpoint/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sandpoint/README b/board/sandpoint/README new file mode 100644 index 0000000..9e48168 --- /dev/null +++ b/board/sandpoint/README @@ -0,0 +1,15 @@ +This port of U-Boot will run on a Motorola Sandpoint 3 development +system equipped with a Unity X4 PPMC card (MPC8240 CPU) only. It is a +snapshot of work in progress and far from being completed. In order +to run it on the target system, it has to be downloaded using the +DINK32 monitor program that came with your Sandpoint system. Please +note that DINK32 does not accept the S-Record file created by the +U-Boot build process unmodified, because it contains CR/LF line +terminators. You have to strip the CR characters first. There is a +tiny script named 'dinkdl' I created for this purpose. + +The Sandpoint port is based on the work of Rob Taylor, who does not +seem to maintain it any more. I can be reached by mail as +tkoeller@gmx.net. + +Thomas Koeller diff --git a/board/sandpoint/config.mk b/board/sandpoint/config.mk new file mode 100644 index 0000000..b3f65eb --- /dev/null +++ b/board/sandpoint/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Sandpoint boards +# + +#TEXT_BASE = 0x00090000 +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/sandpoint/dinkdl b/board/sandpoint/dinkdl new file mode 100644 index 0000000..f281452 --- /dev/null +++ b/board/sandpoint/dinkdl @@ -0,0 +1,2 @@ +#! /bin/bash +tr -d "\r" <$1 >/dev/tts/1 diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S new file mode 100644 index 0000000..07dafb7 --- /dev/null +++ b/board/sandpoint/early_init.S @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2001 + * Thomas Koeller, tkoeller@gmx.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ 1 +#endif + +#include +#include +#include +#include + +#if defined(USE_DINK32) + /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ + #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) +#else + #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) +#endif + + .text + + /* Values to program into memory controller registers */ +tbl: .long MCCR1, MCCR1VAL + .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT + .long MCCR3 + .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ + (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ + (CFG_RDLAT << MCCR3_RDLAT_SHIFT) + .long MCCR4 + .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ + (CFG_REGISTERD_TYPE_BUFFER << 20) | \ + (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ + ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ + (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ + (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ + ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) + .long MSAR1 + .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMSAR1 + .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MSAR2 + .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMSAR2 + .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MEAR1 + .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMEAR1 + .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long MEAR2 + .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long EMEAR2 + .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long 0 + + + /* + * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This + * must be done in assembly, since we have no stack at this point. + */ + .global early_init_f +early_init_f: + mflr r10 + + /* basic memory controller configuration */ + lis r3, CONFIG_ADDR_HIGH + lis r4, CONFIG_DATA_HIGH + bl lab +lab: mflr r5 + lwzu r0, tbl - lab(r5) +loop: lwz r1, 4(r5) + stwbrx r0, 0, r3 + eieio + stwbrx r1, 0, r4 + eieio + lwzu r0, 8(r5) + cmpli cr0, 0, r0, 0 + bne cr0, loop + + /* set bank enable bits */ + lis r0, MBER@h + ori r0, 0, MBER@l + li r1, CFG_BANK_ENABLE + stwbrx r0, 0, r3 + eieio + stb r1, 0(r4) + eieio + + /* delay loop */ + lis r0, 0x0003 + mtctr r0 +delay: bdnz delay + + /* enable memory controller */ + lis r0, MCCR1@h + ori r0, 0, MCCR1@l + stwbrx r0, 0, r3 + eieio + lwbrx r0, 0, r4 + oris r0, 0, MCCR1_MEMGO@h + stwbrx r0, 0, r4 + eieio + + /* set up stack pointer */ + lis r1, CFG_INIT_SP_OFFSET@h + ori r1, r1, CFG_INIT_SP_OFFSET@l + + mtlr r10 + blr diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c new file mode 100644 index 0000000..a9f73ff --- /dev/null +++ b/board/sandpoint/flash.c @@ -0,0 +1,764 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define ROM_CS0_START 0xFF800000 +#define ROM_CS1_START 0xFF000000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word (flash_info_t *info, ulong dest, ulong data); +#if 0 +static void flash_get_offsets (ulong base, flash_info_t *info); +#endif /* 0 */ + +/*flash command address offsets*/ + +#if 0 +#define ADDR0 (0x555) +#define ADDR1 (0x2AA) +#define ADDR3 (0x001) +#else +#define ADDR0 (0xAAA) +#define ADDR1 (0x555) +#define ADDR3 (0x001) +#endif + +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------- + */ + +#if 0 +static int byte_parity_odd(unsigned char x) __attribute__ ((const)); +#endif /* 0 */ +static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const)); + +typedef struct +{ + FLASH_WORD_SIZE extval; + unsigned short intval; +} map_entry; + +#if 0 +static int +byte_parity_odd(unsigned char x) +{ + x ^= x >> 4; + x ^= x >> 2; + x ^= x >> 1; + return (x & 0x1) != 0; +} +#endif /* 0 */ + + +static unsigned long +flash_id(unsigned char mfct, unsigned char chip) +{ + static const map_entry mfct_map[] = + { + {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, + {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, + {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, + {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, + {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, + {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} + }; + + static const map_entry chip_map[] = + { + {AMD_ID_F040B, FLASH_AM040}, + {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} + }; + + const map_entry *p; + unsigned long result = FLASH_UNKNOWN; + + /* find chip id */ + for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) + if(p->extval == chip) + { + result = FLASH_VENDMASK | p->intval; + break; + } + + /* find vendor id */ + for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) + if(p->extval == mfct) + { + result &= ~FLASH_VENDMASK; + result |= (unsigned long) p->intval << 16; + break; + } + + return result; +} + + +unsigned long +flash_init(void) +{ + unsigned long i; + unsigned char j; + static const ulong flash_banks[] = CFG_FLASH_BANKS; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + flash_info_t * const pflinfo = &flash_info[i]; + pflinfo->flash_id = FLASH_UNKNOWN; + pflinfo->size = 0; + pflinfo->sector_count = 0; + } + + /* Enable writes to Sandpoint flash */ + { + register unsigned char temp; + CONFIG_READ_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); + temp &= ~0x20; /* clear BIOSWP bit */ + CONFIG_WRITE_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); + } + + for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) + { + flash_info_t * const pflinfo = &flash_info[i]; + const unsigned long base_address = flash_banks[i]; + volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address; +#if 0 + volatile FLASH_WORD_SIZE * addr2; +#endif +#if 0 + /* write autoselect sequence */ + flash[0x5555] = 0xaa; + flash[0x2aaa] = 0x55; + flash[0x5555] = 0x90; +#else + flash[0xAAA << (3 * i)] = 0xaa; + flash[0x555 << (3 * i)] = 0x55; + flash[0xAAA << (3 * i)] = 0x90; +#endif + __asm__ __volatile__("sync"); + +#if 0 + pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]); +#else + pflinfo->flash_id = flash_id(flash[0x0], flash[0x2 + 14 * i]); +#endif + + switch(pflinfo->flash_id & FLASH_TYPEMASK) + { + case FLASH_AM040: + pflinfo->size = 0x00080000; + pflinfo->sector_count = 8; + for(j = 0; j < 8; j++) + { + pflinfo->start[j] = base_address + 0x00010000 * j; + pflinfo->protect[j] = flash[(j << 16) | 0x2]; + } + break; + case FLASH_STM800AB: + pflinfo->size = 0x00100000; + pflinfo->sector_count = 19; + pflinfo->start[0] = base_address; + pflinfo->start[1] = base_address + 0x4000; + pflinfo->start[2] = base_address + 0x6000; + pflinfo->start[3] = base_address + 0x8000; + for(j = 1; j < 16; j++) + { + pflinfo->start[j+3] = base_address + 0x00010000 * j; + } +#if 0 + /* check for protected sectors */ + for (j = 0; j < pflinfo->sector_count; j++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[j]); + if (pflinfo->flash_id & FLASH_MAN_SST) + pflinfo->protect[j] = 0; + else + pflinfo->protect[j] = addr2[2] & 1; + } +#endif + break; + } + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + /* reset device to read mode */ + flash[0x0000] = 0xf0; + __asm__ __volatile__("sync"); + } + + return flash_info[0].size + flash_info[1].size; +} + +#if 0 +static void +flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_MAN_SST) + { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } + else + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + +} +#endif /* 0 */ + +/*----------------------------------------------------------------------- + */ +void +flash_print_info(flash_info_t *info) +{ + static const char unk[] = "Unknown"; + const char *mfct = unk, *type = unk; + unsigned int i; + + if(info->flash_id != FLASH_UNKNOWN) + { + switch(info->flash_id & FLASH_VENDMASK) + { + case FLASH_MAN_AMD: mfct = "AMD"; break; + case FLASH_MAN_FUJ: mfct = "FUJITSU"; break; + case FLASH_MAN_STM: mfct = "STM"; break; + case FLASH_MAN_SST: mfct = "SST"; break; + case FLASH_MAN_BM: mfct = "Bright Microelectonics"; break; + case FLASH_MAN_INTEL: mfct = "Intel"; break; + } + + switch(info->flash_id & FLASH_TYPEMASK) + { + case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break; + case FLASH_AM400B: type = "AM29LV400B (4 Mbit, bottom boot sect)"; break; + case FLASH_AM400T: type = "AM29LV400T (4 Mbit, top boot sector)"; break; + case FLASH_AM800B: type = "AM29LV800B (8 Mbit, bottom boot sect)"; break; + case FLASH_AM800T: type = "AM29LV800T (8 Mbit, top boot sector)"; break; + case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break; + case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break; + case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break; + case FLASH_STM800AB: type = "M29W800AB (8 Mbit, bottom boot sect)"; break; + case FLASH_SST800A: type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; break; + case FLASH_SST160A: type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; break; + } + } + + printf( + "\n Brand: %s Type: %s\n" + " Size: %lu KB in %d Sectors\n", + mfct, + type, + info->size >> 10, + info->sector_count + ); + + printf (" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; i++) + { + unsigned long size; + unsigned int erased; + unsigned long * flash = (unsigned long *) info->start[i]; + + /* + * Check if whole sector is erased + */ + size = + (i != (info->sector_count - 1)) ? + (info->start[i + 1] - info->start[i]) >> 2 : + (info->start[0] + info->size - info->start[i]) >> 2; + + for( + flash = (unsigned long *) info->start[i], erased = 1; + (flash != (unsigned long *) info->start[i] + size) && erased; + flash++ + ) + erased = *flash == ~0x0UL; + + printf( + "%s %08lX %s %s", + (i % 5) ? "" : "\n ", + info->start[i], + erased ? "E" : " ", + info->protect[i] ? "RO" : " " + ); + } + + puts("\n"); + return; +} + +#if 0 + +/* + * The following code cannot be run from FLASH! + */ +ulong +flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + printf("flash_get_size: \n"); + /* Write auto select command: read Manufacturer ID */ + eieio(); + addr2[ADDR0] = (FLASH_WORD_SIZE)0xAA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x55; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x90; + value = addr2[0]; + + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE)FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE)SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + printf("recognised manufacturer"); + + value = addr2[ADDR3]; /* device ID */ + debug ("\ndev_code=%x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE)SST_ID_xF800A: + info->flash_id += FLASH_SST800A; + info->sector_count = 16; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE)SST_ID_xF160A: + info->flash_id += FLASH_SST160A; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE)AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + printf("flash id %lx; sector count %x, size %lx\n", info->flash_id,info->sector_count,info->size); + /* set up sector start address table */ + if (info->flash_id & FLASH_MAN_SST) + { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } + else + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + if (info->flash_id & FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +#endif + + +int +flash_erase(flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + unsigned char sh8b; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FLASH_WORD_SIZE *)(info->start[0] + ( + (info->start[sect] - info->start[0]) << sh8b)); + if (info->flash_id & FLASH_MAN_SST) + { + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + udelay(30000); /* wait 30 ms */ + } + else + addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FLASH_WORD_SIZE *)(info->start[0] + ( + (info->start[l_sect] - info->start[0]) << sh8b)); + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0]; + volatile FLASH_WORD_SIZE *dest2; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + unsigned char sh8b; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; + + dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) + + info->start[0]); + + /* Check if Flash is (sufficiently) erased */ + if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) + { + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0; + + dest2[i << sh8b] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c new file mode 100644 index 0000000..d3445bd --- /dev/null +++ b/board/sandpoint/sandpoint.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int checkboard (void) +{ + /*TODO: Check processor type */ + + puts ( "Board: Sandpoint " +#ifdef CONFIG_MPC8240 + "8240" +#endif +#ifdef CONFIG_MPC8245 + "8245" +#endif + " Unity ##Test not implemented yet##\n"); + return 0; +} + +#if 0 /* NOT USED */ +int checkflash (void) +{ + /* TODO: XXX XXX XXX */ + printf ("## Test not implemented yet ##\n"); + + return (0); +} +#endif + +long int initdram (int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_sandpoint_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, + PCI_ENET1_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_sandpoint_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h new file mode 100644 index 0000000..b66393b --- /dev/null +++ b/board/sandpoint/speed.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*----------------------------------------------------------------------- + * Timer value for timer 2, ICLK = 10 + * + * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) + * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 + * + * SPEED_FCOUNT2 timer 2 counting frequency + * GCLK CPU clock + * SPEED_TMR2_PS prescaler + */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ + +/*----------------------------------------------------------------------- + * Timer value for PIT + * + * PIT_TIME = SPEED_PITC / PITRTCLK + * PITRTCLK = 8192 + */ +#define SPEED_PITC (82 << 16) /* start counting from 82 */ + +/* + * The new value for PTA is calculated from + * + * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) + * + * gclk CPU clock (not bus clock !) + * Trefresh Refresh cycle * 4 (four word bursts used) + * DFBRG For normal mode (no clock reduction) always 0 + * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) + * NCS Number of SDRAM banks (chip selects) on this UPM. + */ diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds new file mode 100644 index 0000000..2a5cd2e --- /dev/null +++ b/board/sandpoint/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile new file mode 100644 index 0000000..c4198c4 --- /dev/null +++ b/board/sbc405/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o strataflash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sbc405/config.mk b/board/sbc405/config.mk new file mode 100644 index 0000000..bd57217 --- /dev/null +++ b/board/sbc405/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Wind River sbc405 boards +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c new file mode 100644 index 0000000..cad5873 --- /dev/null +++ b/board/sbc405/sbc405.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2001 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + + +int board_early_init_f (void) +{ + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive + * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive + * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive + * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + */ + mtebc (epcr, 0xa8400000); + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ +} + + +int misc_init_r (void) +{ + return (0); +} + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming sbc405"); + } else { + puts(str); + } + + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + return spd_sdram (0); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 64 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c new file mode 100644 index 0000000..d21d885 --- /dev/null +++ b/board/sbc405/strataflash.c @@ -0,0 +1,793 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for ppcboot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + + +#define FLASH_MAN_CFI 0x01000000 + + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char * cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +/*----------------------------------------------------------------------- + * Functions + */ + + +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *)(info->start[sect] + (offset * info->portwidth))); +} +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | + (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + unsigned long address; + + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif +#else + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + - CFG_MONITOR_LEN, + - 1, &flash_info[1]); +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if( info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3 ), (info->chipwidth << 3 )); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + int k; + int size; + int erased; + volatile unsigned long *flash; + + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); +#endif + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for(i=0;iportwidth) && (cnt > 0) ; i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *)cp)); + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while(cnt >= info->portwidth) { + i = info->buffer_size > cnt? cnt: info->buffer_size; + if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + /* handle the aligned part */ + while(cnt >= info->portwidth) { + cword.l = 0; + for(i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; iportwidth; ++i, ++cp) { + flash_add_byte(info, & cword, (*(uchar *)cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if(prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, + prot?"protect":"unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if(prot == 0) { + int i; + for(i = 0 ; isector_count; i++) { + if(info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt,info->start[sector]); + if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ + printf("Command Sequence Error.\n"); + } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) +{ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) +{ + int i; + uchar *cp = (uchar *)cmdbuf; + for(i=0; i< info->portwidth; i++) + *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi(flash_info_t * info) +{ + + for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; + info->portwidth <<= 1) { + for(info->chipwidth =FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } + return 0; +} +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t * info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if(flash_detect_cfi(info)){ +#ifdef DEBUG_FLASH + printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif + sect_cnt = 0; + sector = base; + for(i = 0 ; i < num_erase_regions; i++) { + if(i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) +1; + for(j = 0; j< erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *)dest; + + + /* Check if Flash is (sufficiently) erased */ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if(!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if(flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t *info, ulong addr) +{ + int sector; + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *)dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar)cnt-1); + while(cnt-- > 0) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check(info, sector, info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/sbc405/u-boot.lds b/board/sbc405/u-boot.lds new file mode 100644 index 0000000..39fba61 --- /dev/null +++ b/board/sbc405/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sbc8240/Makefile b/board/sbc8240/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/sbc8240/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sbc8240/README b/board/sbc8240/README new file mode 100644 index 0000000..71595b4 --- /dev/null +++ b/board/sbc8240/README @@ -0,0 +1,140 @@ +The supported features of the SBC8240/8245 board are: + 8240 or 8245 processor + 66MHz & 100MHz bus speed + Decrementer timer + 1 UART channel (Console channel) + 8240 Interrupt Controller + 8240 PCI bridge + 8240 Memory Controller + SDRAM (16, 64 MB Memory DIMM) + FLASH 512K On board + FLASH 4MB On board + + +Memory Map from CPU point of view: + + Start Size Access to + ----------------------------------------------------- + 0x00000000 64MB SDRAM DIMM + 0xFF000000 4MB On Board FLASH + 0xFFF00000 512K On Board FLASH or SRAM (Configured by jumper) + 0xFFE00000 8K EEPROM + 0xFFE80000 8Bit LED + 0xFFF80000 8Bit UART + + +Setting the board Jumpers & Switches: + + In order to get the board running with the default configuration the + jumpers need to be set as follows: + + General Jumpers: + ____________________________________________ + | Jumpers | Jumpers | Jumpers | + |-------------|--------------|---------------| + |JP1 1-2 | JP14 1-2 | JP27 1-2 | + |JP5 Open | JP15 1-2 | JP28 2-3 | + |JP8 1-2 | JP16 1-2 | JP33 Open | + |JP9 1-2 | JP17 1-2 | JP37 Close | + |JP10 1-2 | JP18 1-2 | | + |JP11 2-3 | JP19 1-2 | | + |JP12 1-2 | JP20 1-2 | | + |JP13 1-2 | JP25 Open | | + |_____________|______________|_______________| + + Bus speed Jumpers: + _________________________ + | 100MHz Bus | 66 MHz Bus | + |------------|------------| + | JP2 1-2 | JP2 1-2 | + | JP3 1-2 | JP3 2-3 | + | JP4 1-2 | JP4 2-3 | + | JP6 1-2 | JP6 2-3 | + | JP7 1-2 | JP7 1-2 | + |____________|____________| + + +U-Boot 1.1.2 (Jun 24 2004 - 17:01:04) + +CPU: MPC8240 Revision 1.1 at 247.500 MHz: 16 kB I-Cache 16 kB D-Cache +Board: sbc8240 Revision 255 Local Bus at 99 MHz +DRAM: 64 MB +FLASH: 512 kB + 00 11 8086 1229 0200 00 +In: serial +Out: serial +Err: serial +Net: i82559#0 + +Welcome to U-Boot for the sbc8240 + +Type ? or help to get on-line help + +Hit any key to stop autoboot: 0 +=> printenv +bootcmd=version;echo;tftpboot $loadaddr $loadfile;bootvx +bootdelay=5 +baudrate=9600 +ethaddr=DE:AD:BE:EF:01:01 +ipaddr=192.168.193.102 +preboot=echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type "? or help" to get on-line help;echo +netmask=255.255.255.248 +clocks_in_mhz=1 +bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei +ipaddr=192.168.193.102 +loadfile=vxWorks.st +loadaddr=0x01000000 +net_load=tftpboot $loadaddr $loadfile +serverip=192.168.193.99 +ethact=i82559#0 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 631/16380 bytes +=> boot + +U-Boot 1.1.2 (Jun 24 2004 - 17:01:04) + +Using i82559#0 device +TFTP from server 192.168.193.99; our IP address is 192.168.193.102 +Filename 'vxWorks.st'. +Load address: 0x1000000 +Loading: ################################################################# + ################################################################# + ############################################################## +done +Bytes transferred = 979927 (ef3d7 hex) +## Ethernet MAC address not copied to NV RAM +Loading .text @ 0x00100000 (758848 bytes) +Loading .data @ 0x001b9440 (79904 bytes) +Clearing .bss @ 0x001ccc60 (20288 bytes) +## Using bootline (@ 0x4200): $fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei +## Starting vxWorks at 0x00100000 ... + +Adding 2845 symbols for standalone. + + + ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] + ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] + ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] + ]]]]]]]]]]] ]]]] ]]]]]]]]]] ]] ]]]] (R) + ] ]]]]]]]]] ]]]]]] ]]]]]]]] ]] ]]]] + ]] ]]]]]]] ]]]]]]]] ]]]]]] ] ]] ]]]] + ]]] ]]]]] ] ]]] ] ]]]] ]]] ]]]]]]]]] ]]]] ]] ]]]] ]] ]]]]] + ]]]] ]]] ]] ] ]]] ]] ]]]]] ]]]]]] ]] ]]]]]]] ]]]] ]] ]]]] + ]]]]] ] ]]]] ]]]]] ]]]]]]]] ]]]] ]] ]]]] ]]]]]]] ]]]] + ]]]]]] ]]]]] ]]]]]] ] ]]]]] ]]]] ]] ]]]] ]]]]]]]] ]]]] + ]]]]]]] ]]]]] ] ]]]]]] ] ]]] ]]]] ]] ]]]] ]]]] ]]]] ]]]] + ]]]]]]]] ]]]]] ]]] ]]]]]]] ] ]]]]]]] ]]]] ]]]] ]]]] ]]]]] + ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] + ]]]]]]]]]]]]]]]]]]]]]]]]]]]]] Development System + ]]]]]]]]]]]]]]]]]]]]]]]]]]]] + ]]]]]]]]]]]]]]]]]]]]]]]]]]] VxWorks version 5.5.1 + ]]]]]]]]]]]]]]]]]]]]]]]]]] KERNEL: WIND version 2.6 + ]]]]]]]]]]]]]]]]]]]]]]]]] Copyright Wind River Systems, Inc., 1984-2003 + + CPU: MPC8240 -- Wind River BSP. SBC8240 Board. Processor #0. + Memory Size: 0x2000000. BSP version 1.2/28. + +-> diff --git a/board/sbc8240/config.mk b/board/sbc8240/config.mk new file mode 100644 index 0000000..1e97960 --- /dev/null +++ b/board/sbc8240/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# sbc8240 board +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/sbc8240/flash.c b/board/sbc8240/flash.c new file mode 100644 index 0000000..dec6156 --- /dev/null +++ b/board/sbc8240/flash.c @@ -0,0 +1,638 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +#if CFG_MAX_FLASH_BANKS != 1 +#error "CFG_MAX_FLASH_BANKS must be 1" +#endif +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static int write_word (flash_info_t * info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + + /* Init: no FLASHes known */ + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + /* Setup offsets */ + flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM, + FLASH_BASE0_PRELIM + monitor_flash_len - 1, + &flash_info[0]); + flash_info[0].size = size_b0; + + return size_b0; +} + + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_SST: + printf ("SST "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: + printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST800A: + printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: + printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *) info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; + + value = addr2[0]; + + switch (value) { + case (FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ +#if 0 /* enable when device IDs are available */ + case (FLASH_WORD_SIZE) AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (FLASH_WORD_SIZE) AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ +#endif + case (FLASH_WORD_SIZE) SST_ID_xF800A: + info->flash_id += FLASH_SST800A; + info->sector_count = 16; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (FLASH_WORD_SIZE) SST_ID_xF160A: + info->flash_id += FLASH_SST160A; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *) info->start[0]; + *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7 (flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = + (FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); + printf ("Erasing sector %p\n", addr2); /* CLH */ + + if ((info->flash_id & FLASH_VENDMASK) == + FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay (1000); /* wait 1 ms */ + } else { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7 (info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#if 0 + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + wait_for_DQ7 (info, l_sect); + + DONE: +#endif + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = + (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c new file mode 100644 index 0000000..a6d3bab --- /dev/null +++ b/board/sbc8240/sbc8240.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define BOARD_REV_REG 0xFE80002B + +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char revision = *(volatile char *)(BOARD_REV_REG); + char buf[32]; + + puts ("Board: sbc8240 "); + printf("Revision %d ", revision); + printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk)); + + return 0; +} + +long int initdram(int board_type) +{ + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_sandpoint_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_sandpoint_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} + +#ifdef CONFIG_MISC_INIT_R +/* ------------------------------------------------------------------------- */ +int misc_init_r (void) +{ +#ifdef CFG_LED_BASE + *((unsigned char *) (CFG_LED_BASE)) = 0xFF; +#endif /* CFG_LED_BASE */ + + return (0); +} +#endif /* CONFIG_MISC_INIT_R */ diff --git a/board/sbc8240/u-boot.lds b/board/sbc8240/u-boot.lds new file mode 100644 index 0000000..7be85e4 --- /dev/null +++ b/board/sbc8240/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sbc8260/Makefile b/board/sbc8260/Makefile new file mode 100644 index 0000000..14ed457 --- /dev/null +++ b/board/sbc8260/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := sbc8260.o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sbc8260/config.mk b/board/sbc8260/config.mk new file mode 100644 index 0000000..1f18260 --- /dev/null +++ b/board/sbc8260/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MBX8xx boards +# + +TEXT_BASE = 0x40000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/sbc8260/flash.c b/board/sbc8260/flash.c new file mode 100644 index 0000000..9a8b952 --- /dev/null +++ b/board/sbc8260/flash.c @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2000 + * Marius Groeger + * Sysgo Real-Time Solutions, GmbH + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AMD 29F080B devices + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + * Functions + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH0_BASE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + + return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ((info->flash_id >> 16) & 0xff) { + case 0x1: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case AMD_ID_F040B: + printf ("AM29F040B (4 Mbit)\n"); + break; + case AMD_ID_F080B: + printf ("AM29F080B (8 Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + vu_long vendor, devid; + ulong base = (ulong)addr; + +/* printf("addr = %08lx\n", (unsigned long)addr); */ + + /* Reset and Write auto select command: read Manufacturer ID */ + addr[0] = 0xf0f0f0f0; + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x90909090; + udelay (1000); + + vendor = addr[0]; +/* printf("vendor = %08lx\n", vendor); */ + if (vendor != 0x01010101) { + info->size = 0; + goto out; + } + + devid = addr[1]; +/* printf("devid = %08lx\n", devid); */ + + if ((devid & 0xff) == AMD_ID_F080B) { + info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B; + /* we have 16 sectors with 64KB each x 4 */ + info->sector_count = 16; + info->size = 4 * info->sector_count * 64*1024; + } + else { + info->size = 0; + goto out; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* sector base address */ + info->start[i] = base + i * (info->size / info->sector_count); + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* reset command */ + addr = (vu_long *)info->start[0]; + +out: + addr[0] = 0xf0f0f0f0; + + return info->size; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0x80808080; + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + udelay (100); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x30303030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x80808080) != 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAAAAAAAA; + addr[0x02AA] = 0x55555555; + addr[0x0555] = 0xA0A0A0A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c new file mode 100644 index 0000000..48aefa0 --- /dev/null +++ b/board/sbc8260/sbc8260.c @@ -0,0 +1,289 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ + /* PA30 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ + /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ + /* PA28 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ + /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ + /* PA26 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 1, 0, 0, 1, 0, 0 }, /* PB17 */ + /* PB16 */ { 1, 0, 0, 1, 0, 0 }, /* PB16 */ + /* PB15 */ { 1, 0, 0, 1, 0, 0 }, /* PB15 */ + /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* PB14 */ + /* PB13 */ { 1, 0, 0, 1, 0, 0 }, /* PB13 */ + /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* PB12 */ + /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* PB11 */ + /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* PB10 */ + /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* PB9 */ + /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* PB8 */ + /* PB7 */ { 1, 0, 0, 1, 0, 0 }, /* PB7 */ + /* PB6 */ { 1, 0, 0, 1, 0, 0 }, /* PB6 */ + /* PB5 */ { 1, 0, 0, 1, 0, 0 }, /* PB5 */ + /* PB4 */ { 1, 0, 0, 1, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 1, 0, 0, 1, 0, 0 }, /* PC16 */ + /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ + /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ + /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 1, 0, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 1, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 1, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 1, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 1, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 1, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 1, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: EST SBC8260\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); + ulong psdmr = CFG_PSDMR; + int i; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + + /* return total ram size */ + return (CFG_SDRAM0_SIZE * 1024 * 1024); +} + +#ifdef CONFIG_MISC_INIT_R +/* ------------------------------------------------------------------------- */ +int misc_init_r (void) +{ +#ifdef CFG_LED_BASE + uchar ds = *(unsigned char *) (CFG_LED_BASE + 1); + uchar ss; + uchar tmp[64]; + int res; + + if ((ds != 0) && (ds != 0xff)) { + res = getenv_r ("ethaddr", tmp, sizeof (tmp)); + if (res > 0) { + ss = ((ds >> 4) & 0x0f); + ss += ss < 0x0a ? '0' : ('a' - 10); + tmp[15] = ss; + + ss = (ds & 0x0f); + ss += ss < 0x0a ? '0' : ('a' - 10); + tmp[16] = ss; + + tmp[17] = '\0'; + setenv ("ethaddr", tmp); + /* set the led to show the address */ + *((unsigned char *) (CFG_LED_BASE + 1)) = ds; + } + } +#endif /* CFG_LED_BASE */ + return (0); +} +#endif /* CONFIG_MISC_INIT_R */ diff --git a/board/sbc8260/u-boot.lds b/board/sbc8260/u-boot.lds new file mode 100644 index 0000000..9e623d0 --- /dev/null +++ b/board/sbc8260/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile new file mode 100644 index 0000000..da295fb --- /dev/null +++ b/board/sbc8560/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2004 Wind River Systems Inc . +# Added support for Wind River SBC8560 board +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sbc8560/config.mk b/board/sbc8560/config.mk new file mode 100644 index 0000000..6d9ae45 --- /dev/null +++ b/board/sbc8560/config.mk @@ -0,0 +1,33 @@ +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,2003 Motorola Inc. +# +# (C) Copyright 2004 Wind River Systems Inc . +# Added support for Wind River SBC8560 board +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# based on mpc8560ads board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 256K +# +TEXT_BASE = 0xfffc0000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S new file mode 100644 index 0000000..3d8d180 --- /dev/null +++ b/board/sbc8560/init.S @@ -0,0 +1,165 @@ +/* +* Copyright (C) 2002,2003, Motorola Inc. +* Xianghua Xiao +* +* (C) Copyright 2004 Wind River Systems Inc . +* Added support for Wind River SBC8560 board +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + +/* LAW(Local Access Window) configuration: + * 0000_0000-0800_0000: DDR(512M) -or- larger + * c000_0000-cfff_ffff: PCI(256M) + * d000_0000-dfff_ffff: RapidIO(256M) + * e000_0000-ffff_ffff: localbus(512M) + * e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6 + * e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1 + * e800_0000-efff_ffff: LBC 128M, nothing here + * f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3 + * f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4 + * f800_0000-fdff_ffff: LBC 64M, nothing here + * fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5 + * fd00_0000-fdff_ffff: LBC 16M, nothing here + * fe00_0000-feff_ffff: LBC 16M, nothing here + * ff00_0000-ff6f_ffff: LBC 7M, nothing here + * ff70_0000-ff7f_ffff: CCSRBAR 1M + * ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0 + * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access + * Window. + * Note: If flash is 8M at default position(last 8M),no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) + #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) + #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#else + #define LAWBAR0 0 + #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR2 ((0xe0000000>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x03 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 + entry_end + +/* TLB1 entries configuration: */ + + .section .bootpg, "ax" + .globl tlb1_entry + +tlb1_entry: + entry_start + + .long 0x08 /* the following data table uses a few of 16 TLB entries */ + +/* TLB for CCSRBAR (IMMR) */ + + .long TLB1_MAS0(1,1,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + +/* TLB for Local Bus stuff, just map the whole 512M */ +/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ + + .long TLB1_MAS0(1,2,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,3,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) +#else + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) +#endif + + .long TLB1_MAS0(1,6,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) +#ifdef CONFIG_L2_INIT_RAM + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) +#else + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) +#endif + .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,7,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) +#else + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) +#endif + entry_end diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c new file mode 100644 index 0000000..e8b9929 --- /dev/null +++ b/board/sbc8560/sbc8560.c @@ -0,0 +1,460 @@ +/* + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * (C) Copyright 2004 Wind River Systems Inc . + * Added support for Wind River SBC8560 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +extern long int spd_sdram (void); + +#include +#include +#include +#include +#include +#include + +long int fixed_sdram (void); + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ + /* PD27 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */ + /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +int board_early_init_f (void) +{ +#if defined(CONFIG_PCI) + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; + + pci->peer &= 0xfffffffdf; /* disable master abort */ +#endif + return 0; +} + +void reset_phy (void) +{ +#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ + volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR; +#endif + /* reset Giga bit Ethernet port if needed here */ + + /* reset the CPM FEC port */ +#if (CONFIG_ETHER_INDEX == 2) + bcsr[0] &= ~0x20; + udelay(2); + bcsr[0] |= 0x20; + udelay(1000); +#elif (CONFIG_ETHER_INDEX == 3) + bcsr[0] &= ~0x10; + udelay(2); + bcsr[0] |= 0x10; + udelay(1000); +#endif +#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) + /* reset PHY */ + miiphy_reset("FCC1 ETHERNET", 0x0); + + /* change PHY address to 0x02 */ + bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + + bb_miiphy_write(NULL, 0x02, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#endif /* CONFIG_MII */ +} + +int checkboard (void) +{ + sys_info_t sysinfo; + + get_sys_info (&sysinfo); + +#ifdef CONFIG_SBC8560 + printf ("Board: Wind River SBC8560 Board\n"); +#else + printf ("Board: Wind River SBC8540 Board\n"); +#endif + printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); + printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); + if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ + || (CFG_LBC_LCRR & 0x0f) == 8) { + printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f)); + } else { + printf("\tLBC: unknown\n"); + } + printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); + printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); + return (0); +} + + +long int initdram (int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; +#if 0 +#if !defined(CONFIG_RAM_AS_FLASH) + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + sys_info_t sysinfo; + uint temp_lbcdll = 0; +#endif +#endif /* 0 */ +#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) + volatile ccsr_gur_t *gur= &immap->im_gur; +#endif +#if defined(CONFIG_DDR_DLL) + uint temp_ddrdll = 0; + + /* Work around to stabilize DDR DLL */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if 0 +#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ + get_sys_info(&sysinfo); + /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ + if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { + lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; + } else { +#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */ + lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */ +#endif + lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; + udelay(200); + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; + asm("sync;isync;msync"); + } + lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ + lbc->br2 = CFG_BR2_PRELIM; + lbc->lbcr = CFG_LBC_LBCR; + lbc->lsdmr = CFG_LBC_LSDMR_1; + asm("sync"); + (unsigned int) * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_2; + asm("sync"); + (unsigned int) * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_3; + asm("sync"); + (unsigned int) * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + (unsigned int) * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm("sync"); + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + lbc->mrtpr = CFG_LBC_MRTPR; + asm("sync"); +#endif +#endif + +#if defined(CONFIG_DDR_ECC) + { + /* Initialize all of memory for ECC, then + * enable errors */ + uint *p = 0; + uint i = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + dma_init(); + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } + *p = (unsigned int)0xdeadbeef; + if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } + } + + /* 8K */ + dma_xfer((uint *)0x2000,0x2000,(uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000,0x4000,(uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000,0x8000,(uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000,0x10000,(uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000,0x20000,(uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000,0x40000,(uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000,0x80000,(uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000,0x100000,(uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000,0x200000,(uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000,0x400000,(uint *)0); + + for (i = 1; i < dram_size / 0x800000; i++) { + dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); + } + + /* Enable errors for ECC */ + ddr->err_disable = 0x00000000; + asm("sync;isync;msync"); + } +#endif + + return dram_size; +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ + +#define CFG_DDR_CONTROL 0xc2000000 + + #ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = 0x00000007; + ddr->cs1_bnds = 0x0010001f; + ddr->cs2_bnds = 0x00000000; + ddr->cs3_bnds = 0x00000000; + ddr->cs0_config = 0x80000102; + ddr->cs1_config = 0x80000102; + ddr->cs2_config = 0x00000000; + ddr->cs3_config = 0x00000000; + ddr->timing_cfg_1 = 0x37334321; + ddr->timing_cfg_2 = 0x00000800; + ddr->sdram_cfg = 0x42000000; + ddr->sdram_mode = 0x00000022; + ddr->sdram_interval = 0x05200100; + ddr->err_sbe = 0x00ff0000; + #if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + #endif + asm("sync;isync;msync"); + udelay(500); + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + asm("sync; isync; msync"); + udelay(500); + #endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds new file mode 100644 index 0000000..48e19fe --- /dev/null +++ b/board/sbc8560/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2002,2003,Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * (C) Copyright 2004 Wind River Systems Inc . + * Added support for Wind River SBC8560 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/sbc8560/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/sbc8560/init.o (.text) + cpu/mpc85xx/commproc.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/serial_scc.o (.text) + cpu/mpc85xx/ether_fcc.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/i2c.o (.text) + cpu/mpc85xx/spd_sdram.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile new file mode 100644 index 0000000..ab06ebc --- /dev/null +++ b/board/sc520_cdp/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := sc520_cdp.o flash.o +SOBJS := sc520_cdp_asm.o sc520_cdp_asm16.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sc520_cdp/config.mk b/board/sc520_cdp/config.mk new file mode 100644 index 0000000..2253815 --- /dev/null +++ b/board/sc520_cdp/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +TEXT_BASE = 0x387c0000 diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c new file mode 100644 index 0000000..d52a847 --- /dev/null +++ b/board/sc520_cdp/flash.c @@ -0,0 +1,637 @@ +/* + * (C) Copyright 2002, 2003 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define PROBE_BUFFER_SIZE 1024 +static unsigned char buffer[PROBE_BUFFER_SIZE]; + +#define SC520_MAX_FLASH_BANKS 3 +#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ +#define SC520_FLASH_BANK1_BASE 0x30000000 /* ROMCS0 */ +#define SC520_FLASH_BANK2_BASE 0x28000000 /* ROMCS1 */ +#define SC520_FLASH_BANKSIZE 0x8000000 + +#define AMD29LV016B_SIZE 0x200000 +#define AMD29LV016B_SECTORS 32 + +flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + + +static u32 _probe_flash(u32 addr, u32 bw, int il) +{ + u32 result=0; + + /* First do an unlock cycle for the benefit of + * devices that need it */ + + switch (bw) { + + case 1: + *(volatile u8*)(addr+0x5555) = 0xaa; + *(volatile u8*)(addr+0x2aaa) = 0x55; + *(volatile u8*)(addr+0x5555) = 0x90; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5555), 0xf0; + break; + + case 2: + *(volatile u16*)(addr+0xaaaa) = 0xaaaa; + *(volatile u16*)(addr+0x5554) = 0x5555; + + /* Issue identification command */ + if (il == 2) { + *(volatile u16*)(addr+0xaaaa) = 0x9090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u16*)addr = 0xffff; + *(volatile u16*)(addr+0xaaaa), 0xf0f0; + + } else { + *(volatile u8*)(addr+0xaaaa) = 0x90; + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0xaaaa), 0xf0; + } + + break; + + case 4: + *(volatile u32*)(addr+0x5554) = 0xaaaaaaaa; + *(volatile u32*)(addr+0xaaa8) = 0x55555555; + + switch (il) { + case 1: + /* Issue identification command */ + *(volatile u8*)(addr+0x5554) = 0x90; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5554), 0xf0; + break; + + case 2: + /* Issue identification command */ + *(volatile u32*)(addr + 0x5554) = 0x00900090; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0x00ff00ff; + *(volatile u32*)(addr+0x5554), 0x00f000f0; + break; + + case 4: + /* Issue identification command */ + *(volatile u32*)(addr+0x5554) = 0x90909090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0xffffffff; + *(volatile u32*)(addr+0x5554), 0xf0f0f0f0; + break; + } + break; + } + + + return result; +} + +extern int _probe_flash_end; +asm ("_probe_flash_end:\n" + ".long 0\n"); + +static int identify_flash(unsigned address, int width) +{ + int is; + int device; + int vendor; + int size; + unsigned res; + + u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il); + + size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_probe_flash() routine too large (%d) %p - %p\n", + size, &_probe_flash_end, _probe_flash); + return 0; + } + + memcpy(buffer, _probe_flash, size); + _probe_flash_ptr = (void*)buffer; + + is = disable_interrupts(); + res = _probe_flash_ptr(address, width, 1); + if (is) { + enable_interrupts(); + } + + + vendor = res >> 16; + device = res & 0xffff; + + + return res; +} + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { + unsigned id; + ulong flashbase = 0; + int sectsize = 0; + + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) { + case 0: + flashbase = SC520_FLASH_BANK0_BASE; + break; + case 1: + flashbase = SC520_FLASH_BANK1_BASE; + break; + case 2: + flashbase = SC520_FLASH_BANK2_BASE; + break; + default: + panic("configured too many flash banks!\n"); + } + + id = identify_flash(flashbase, 4); + switch (id & 0x00ff00ff) { + case 0x000100c8: + /* 29LV016B/29LV017B */ + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV016B & FLASH_TYPEMASK); + + flash_info[i].size = AMD29LV016B_SIZE*4; + flash_info[i].sector_count = AMD29LV016B_SECTORS; + sectsize = (AMD29LV016B_SIZE*4)/AMD29LV016B_SECTORS; + printf("Bank %d: 4 x AMD 29LV017B\n", i); + break; + + + default: + printf("Bank %d have unknown flash %08x\n", i, id); + flash_info[i].flash_id = FLASH_UNKNOWN; + continue; + } + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j * sectsize; + } + size += flash_info[i].size; + + flash_protect(FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + flash_info[i].size - 1, + &flash_info[i]); + } + + /* + * Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + i386boot_start, + i386boot_end, + &flash_info[0]); +#ifdef CFG_ENV_ADDR + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + + case (AMD_MANUFACT & FLASH_VENDMASK): + printf("AMD: "); + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV016B & FLASH_TYPEMASK): + printf("4x AMD29LV017B (4x16Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto done; + break; + } + + break; + default: + printf("Unknown Vendor "); + break; + } + + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +done: ; +} + +/*----------------------------------------------------------------------- + */ + +/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */ +#define __udelay(delay) \ +{ \ + unsigned micro; \ + unsigned milli=0; \ + \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + \ + for (;;) { \ + \ + milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \ + \ + if ((delay) <= (micro + (milli * 1000))) { \ + break; \ + } \ + } \ +} while (0) + +static u32 _amd_erase_flash(u32 addr, u32 sector) +{ + unsigned elapsed; + + /* Issue erase */ + *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA; + *(volatile u32*)(addr + 0xaaa8) = 0x55555555; + *(volatile u32*)(addr + 0x5554) = 0x80808080; + /* And one unlock */ + *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA; + *(volatile u32*)(addr + 0xaaa8) = 0x55555555; + /* Sector erase command comes last */ + *(volatile u32*)(addr + sector) = 0x30303030; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + __udelay(50); + while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) { + + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + *(volatile u32*)(addr) = 0xf0f0f0f0; + return 1; + } + } + + *(volatile u32*)(addr) = 0xf0f0f0f0; + + return 0; +} + +extern int _amd_erase_flash_end; +asm ("_amd_erase_flash_end:\n" + ".long 0\n"); + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + u32 (*_erase_flash_ptr)(u32 a, u32 so); + int prot; + int sect; + unsigned size; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_erase_flash() routine too large (%d) %p - %p\n", + size, &_amd_erase_flash_end, _amd_erase_flash); + return 0; + } + + memcpy(buffer, _amd_erase_flash, size); + _erase_flash_ptr = (void*)buffer; + + } else { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + + if (info->protect[sect] == 0) { /* not protected */ + int res; + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + + if (res) { + printf("Erase timed out, sector %d\n", sect); + return res; + } + + putc('.'); + } + } + + + return 0; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int _amd_write_word(unsigned start, unsigned dest, unsigned data) +{ + volatile u32 *addr2 = (u32*)start; + volatile u32 *dest2 = (u32*)dest; + volatile u32 *data2 = (u32*)&data; + unsigned elapsed; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u32*)dest) & (u32)data) != (u32)data) { + return 2; + } + + addr2[0x5554] = 0xAAAAAAAA; + addr2[0xaaa8] = 0x55555555; + addr2[0x5554] = 0xA0A0A0A0; + + dest2[0] = data; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + + /* data polling for D7 */ + while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) { + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + addr2[0] = 0xf0f0f0f0; + return 1; + } + } + + + addr2[0] = 0xf0f0f0f0; + + return 0; +} + +extern int _amd_write_word_end; +asm ("_amd_write_word_end:\n" + ".long 0\n"); + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 3 - Unsupported flash type + */ + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + int flag; + u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data); + unsigned size; + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_write_word() routine too large (%d) %p - %p\n", + size, &_amd_write_word_end, _amd_write_word); + return 0; + } + + memcpy(buffer, _amd_write_word, size); + _write_word_ptr = (void*)buffer; + + } else { + printf ("Can't program unknown flash type - aborted\n"); + return 3; + } + + + wp = (addr & ~3); /* get lower word aligned address */ + + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data |= *src++ << (8*i); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + + for (i=0; i<4; ++i) { + data |= *src++ << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return 0; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data |= *src++ << (8*i); + --cnt; + } + + for (; i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + return rc; + +} diff --git a/board/sc520_cdp/flash_old.c b/board/sc520_cdp/flash_old.c new file mode 100644 index 0000000..3c0f6d6 --- /dev/null +++ b/board/sc520_cdp/flash_old.c @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +ulong myflush(void); + + +#define SC520_MAX_FLASH_BANKS 3 +#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ +#define SC520_FLASH_BANK1_BASE 0x30000000 /* ROMCS0 */ +#define SC520_FLASH_BANK2_BASE 0x28000000 /* ROMCS1 */ +#define SC520_FLASH_BANKSIZE 0x8000000 + +#define AMD29LV016_SIZE 0x200000 +#define AMD29LV016_SECTORS 32 + +flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; + +#define CMD_READ_ARRAY 0x00F000F0 +#define CMD_UNLOCK1 0x00AA00AA +#define CMD_UNLOCK2 0x00550055 +#define CMD_ERASE_SETUP 0x00800080 +#define CMD_ERASE_CONFIRM 0x00300030 +#define CMD_PROGRAM 0x00A000A0 +#define CMD_UNLOCK_BYPASS 0x00200020 + + +#define BIT_ERASE_DONE 0x00800080 +#define BIT_RDY_MASK 0x00800080 +#define BIT_PROGRAM_ERROR 0x00200020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + int sectsize = 0; + if (i==0 || i==2) { + /* FixMe: this assumes that bank 0 and 2 + * are mapped to the two 8Mb banks */ + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV016B & FLASH_TYPEMASK); + + flash_info[i].size = AMD29LV016_SIZE*4; + flash_info[i].sector_count = AMD29LV016_SECTORS; + sectsize = (AMD29LV016_SIZE*4)/AMD29LV016_SECTORS; + } else { + /* FixMe: this assumes that bank1 is unmapped + * (or mapped to the same flash bank as BOOTCS) */ + flash_info[i].flash_id = 0; + flash_info[i].size = 0; + flash_info[i].sector_count = 0; + sectsize=0; + } + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) { + case 0: + flashbase = SC520_FLASH_BANK0_BASE; + break; + case 1: + flashbase = SC520_FLASH_BANK1_BASE; + break; + case 2: + flashbase = SC520_FLASH_BANK0_BASE; + break; + default: + panic("configured too many flash banks!\n"); + } + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = sectsize; + flash_info[i].start[j] = flashbase + j * sectsize; + } + size += flash_info[i].size; + } + + /* + * Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + i386boot_start-SC520_FLASH_BANK0_BASE, + i386boot_end-SC520_FLASH_BANK0_BASE, + &flash_info[0]); + +#ifdef CFG_ENV_ADDR + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf("AMD: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV016B & FLASH_TYPEMASK): + printf("4x Amd29LV016B (16Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto done; + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + done: +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + ulong result; + int iflag, prot, sect; + int rc = ERR_OK; + int chip1, chip2; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) { + return ERR_UNKNOWN_FLASH_TYPE; + } + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + return ERR_PROTECTED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + iflag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer(); + + if (info->protect[sect] == 0) { + /* not protected */ + ulong addr = info->start[sect]; + + writel(CMD_UNLOCK1, addr + 1); + writel(CMD_UNLOCK2, addr + 2); + writel(CMD_ERASE_SETUP, addr + 1); + + writel(CMD_UNLOCK1, addr + 1); + writel(CMD_UNLOCK2, addr + 2); + writel(CMD_ERASE_CONFIRM, addr); + + + /* wait until flash is ready */ + chip1 = chip2 = 0; + + do { + result = readl(addr); + + /* check timeout */ + if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { + writel(CMD_READ_ARRAY, addr + 1); + chip1 = TMO; + break; + } + + if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) { + chip1 = READY; + } + + if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) { + chip1 = ERR; + } + + if (!chip2 && (result >> 16) & BIT_ERASE_DONE) { + chip2 = READY; + } + + if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) { + chip2 = ERR; + } + + } while (!chip1 || !chip2); + + writel(CMD_READ_ARRAY, addr + 1); + + if (chip1 == ERR || chip2 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf("ok.\n"); + } else { /* it was protected */ + + printf("protected!\n"); + } + } + + if (ctrlc()) { + printf("User Interrupt!\n"); + } + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay(10000); + + if (iflag) { + enable_interrupts(); + } + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_word(flash_info_t *info, ulong dest, ulong data) +{ + ulong addr = dest; + ulong result; + int rc = ERR_OK; + int iflag; + int chip1, chip2; + + /* + * Check if Flash is (sufficiently) erased + */ + result = readl(addr); + if ((result & data) != data) { + return ERR_NOT_ERASED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + iflag = disable_interrupts(); + + writel(CMD_UNLOCK1, addr + 1); + writel(CMD_UNLOCK2, addr + 2); + writel(CMD_UNLOCK_BYPASS, addr + 1); + writel(addr, CMD_PROGRAM); + writel(addr, data); + + /* arm simple, non interrupt dependent timer */ + reset_timer(); + + /* wait until flash is ready */ + chip1 = chip2 = 0; + do { + result = readl(addr); + + /* check timeout */ + if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + + if (!chip1 && ((result & 0x80) == (data & 0x80))) { + chip1 = READY; + } + + if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { + result = readl(addr); + + if ((result & 0x80) == (data & 0x80)) { + chip1 = READY; + } else { + chip1 = ERR; + } + } + + if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) { + chip2 = READY; + } + + if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) { + result = readl(addr); + + if ((result & (0x80 << 16)) == (data & (0x80 << 16))) { + chip2 = READY; + } else { + chip2 = ERR; + } + } + + } while (!chip1 || !chip2); + + writel(CMD_READ_ARRAY, addr); + + if (chip1 == ERR || chip2 == ERR || readl(addr) != data) { + rc = ERR_PROG_ERROR; + } + + if (iflag) { + enable_interrupts(); + } + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 24); + } + for (; i<4 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return rc; + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = *((vu_long*)src); + if ((rc = write_word(info, wp, data)) != 0) { + return rc; + } + src += 4; + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + return write_word(info, wp, data); +} diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c new file mode 100644 index 0000000..cd52324 --- /dev/null +++ b/board/sc520_cdp/sc520_cdp.c @@ -0,0 +1,630 @@ +/* + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#undef SC520_CDP_DEBUG + +#ifdef SC520_CDP_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* ------------------------------------------------------------------------- */ + + +/* + * Theory: + * We first set up all IRQs to be non-pci, edge triggered, + * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets + * called we reallocate irqs to the pci bus with sc520_pci_set_irq() + * as needed. Whe choose the irqs to gram from a configurable list + * inside pci_sc520_fixup_irq() (If this list contains stupid irq's + * such as 0 thngas will not work) + */ + +static void irq_init(void) +{ + /* disable global interrupt mode */ + write_mmcr_byte(SC520_PICICR, 0x40); + + /* set all irqs to edge */ + write_mmcr_byte(SC520_MPICMODE, 0x00); + write_mmcr_byte(SC520_SL1PICMODE, 0x00); + write_mmcr_byte(SC520_SL2PICMODE, 0x00); + + /* active low polarity on PIC interrupt pins, + * active high polarity on all other irq pins */ + write_mmcr_word(SC520_INTPINPOL, 0x0000); + + /* set irq number mapping */ + write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ + write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ + write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ + write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ + write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ + write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ + write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ + write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ + write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ + write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ + write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ + write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */ + write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ + write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ + write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ + write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ + write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ + + if (CFG_USE_SIO_UART) { + write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */ + write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */ + write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ + write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */ + } else { + write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ + write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ + write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */ + write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */ + } + + write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */ + write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */ + write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */ + write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */ + write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */ + write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */ + write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */ + write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */ + write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */ + + write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ + write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ + +} + + +/* PCI stuff */ +static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + /* a configurable lists of irqs to steal + * when we need one (a board with more pci interrupt pins + * would use a larger table */ + static int irq_list[] = { + CFG_FIRST_PCI_IRQ, + CFG_SECOND_PCI_IRQ, + CFG_THIRD_PCI_IRQ, + CFG_FORTH_PCI_IRQ + }; + static int next_irq_index=0; + + char tmp_pin; + int pin; + + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); + pin = tmp_pin; + + pin-=1; /* pci config space use 1-based numbering */ + if (-1 == pin) { + return; /* device use no irq */ + } + + + /* map device number + pin to a pin on the sc520 */ + switch (PCI_DEV(dev)) { + case 20: + pin+=SC520_PCI_INTA; + break; + + case 19: + pin+=SC520_PCI_INTB; + break; + + case 18: + pin+=SC520_PCI_INTC; + break; + + case 17: + pin+=SC520_PCI_INTD; + break; + + default: + return; + } + + pin&=3; /* wrap around */ + + if (sc520_pci_ints[pin] == -1) { + /* re-route one interrupt for us */ + if (next_irq_index > 3) { + return; + } + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + return; + } + next_irq_index++; + } + + + if (-1 != sc520_pci_ints[pin]) { + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + sc520_pci_ints[pin]); + } + PRINTF("fixup_irq: device %d pin %c irq %d\n", + PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); +} + +static struct pci_controller sc520_cdp_hose = { + fixup_irq: pci_sc520_cdp_fixup_irq, +}; + +void pci_init_board(void) +{ + pci_sc520_init(&sc520_cdp_hose); +} + + +static void silence_uart(int port) +{ + outb(0, port+1); +} + +void setup_ali_sio(int uart_primary) +{ + ali512x_init(); + + ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0); + ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3); + ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4); + ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3); + ali512x_set_rtc(ALI_DISABLED, 0, 0); + ali512x_set_kbc(ALI_ENABLED, 1, 12); + ali512x_set_cio(ALI_ENABLED); + + /* IrDa pins */ + ali512x_cio_function(12, 1, 0, 0); + ali512x_cio_function(13, 1, 0, 0); + + /* SSI chip select pins */ + ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */ + ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */ + ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */ + + /* Board REV pins */ + ali512x_cio_function(20, 0, 0, 1); + ali512x_cio_function(21, 0, 0, 1); + ali512x_cio_function(22, 0, 0, 1); + ali512x_cio_function(23, 0, 0, 1); +} + + +/* set up the ISA bus timing and system address mappings */ +static void bus_init(void) +{ + + /* set up the GP IO pins */ + write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */ + write_mmcr_byte(SC520_CLKSEL, 0x70); + + + write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ + write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ + write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ + write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ + write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ + write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ + write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ + + write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */ + write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */ + write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */ + + /* adjust the memory map: + * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM + * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio + * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ + + + /* SRAM = GPCS3 128k @ d0000-effff*/ + write_mmcr_long(SC520_PAR2, 0x4e00400d); + + /* IDE0 = GPCS6 1f0-1f7 */ + write_mmcr_long(SC520_PAR3, 0x380801f0); + + /* IDE1 = GPCS7 3f6 */ + write_mmcr_long(SC520_PAR4, 0x3c0003f6); + /* bootcs */ + write_mmcr_long(SC520_PAR12, 0x8bffe800); + /* romcs2 */ + write_mmcr_long(SC520_PAR13, 0xcbfff000); + /* romcs1 */ + write_mmcr_long(SC520_PAR14, 0xabfff800); + /* 680 LEDS */ + write_mmcr_long(SC520_PAR15, 0x30000640); + + write_mmcr_byte(SC520_ADDDECCTL, 0); + + asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ + + if (CFG_USE_SIO_UART) { + write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS); + setup_ali_sio(1); + } else { + write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); + setup_ali_sio(0); + silence_uart(0x3e8); + silence_uart(0x2e8); + } + +} + +/* GPCS usage + * GPCS0 PIO27 (NMI) + * GPCS1 ROMCS1 + * GPCS2 ROMCS2 + * GPCS3 SRAMCS PAR2 + * GPCS4 unused PAR3 + * GPCS5 unused PAR4 + * GPCS6 IDE + * GPCS7 IDE + */ + + +/* par usage: + * PAR0 legacy_video + * PAR1 PCI ROM mapping + * PAR2 SRAM + * PAR3 IDE + * PAR4 IDE + * PAR5 legacy_video + * PAR6 legacy_video + * PAR7 legacy_video + * PAR8 legacy_video + * PAR9 legacy_video + * PAR10 legacy_video + * PAR11 ISAROM + * PAR12 BOOTCS + * PAR13 ROMCS1 + * PAR14 ROMCS2 + * PAR15 Port 0x680 LED display + */ + +/* + * This function should map a chunk of size bytes + * of the system address space to the ISA bus + * + * The function will return the memory address + * as seen by the host (which may very will be the + * same as the bus address) + */ +u32 isa_map_rom(u32 bus_addr, int size) +{ + u32 par; + + PRINTF("isa_map_rom asked to map %d bytes at %x\n", + size, bus_addr); + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 12; + par--; + par&=0x7f; + par <<= 18; + par |= (bus_addr>>12); + par |= 0x50000000; + + PRINTF ("setting PAR11 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR11, par); + + return bus_addr; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void isa_unmap_rom(u32 addr) +{ + PRINTF("isa_unmap_rom asked to unmap %x", addr); + if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { + write_mmcr_long(SC520_PAR11, 0); + PRINTF(" done\n"); + return; + } + PRINTF(" not ours\n"); +} + +#ifdef CONFIG_PCI +#define PCI_ROM_TEMP_SPACE 0x10000 +/* + * This function should map a chunk of size bytes + * of the system address space to the PCI bus, + * suitable to map PCI ROMS (bus address < 16M) + * the function will return the host memory address + * which should be converted into a bus address + * before used to configure the PCI rom address + * decoder + */ +u32 pci_get_rom_window(struct pci_controller *hose, int size) +{ + u32 par; + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 16; + par--; + par&=0x7ff; + par <<= 14; + par |= (PCI_ROM_TEMP_SPACE>>16); + par |= 0x72000000; + + PRINTF ("setting PAR1 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR1, par); + + return PCI_ROM_TEMP_SPACE; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void pci_remove_rom_window(struct pci_controller *hose, u32 addr) +{ + PRINTF("pci_remove_rom_window: %x", addr); + if (addr == PCI_ROM_TEMP_SPACE) { + write_mmcr_long(SC520_PAR1, 0); + PRINTF(" done\n"); + return; + } + PRINTF(" not ours\n"); + +} + +/* + * This function is called in order to provide acces to the + * legacy video I/O ports on the PCI bus. + * After this function accesses to I/O ports 0x3b0-0x3bb and + * 0x3c0-0x3df shuld result in transactions on the PCI bus. + * + */ +int pci_enable_legacy_video_ports(struct pci_controller *hose) +{ + /* Map video memory to 0xa0000*/ + write_mmcr_long(SC520_PAR0, 0x7200400a); + + /* forward all I/O accesses to PCI */ + write_mmcr_byte(SC520_ADDDECCTL, + read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); + + + /* so we map away all io ports to pci (only way to access pci io + * below 0x400. But then we have to map back the portions that we dont + * use so that the generate cycles on the GPIO bus where the sio and + * ISA slots are connected, this requre the use of several PAR registers + */ + + /* bring 0x100 - 0x1ef back to ISA using PAR5 */ + write_mmcr_long(SC520_PAR5, 0x30ef0100); + + /* IDE use 1f0-1f7 */ + + /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */ + write_mmcr_long(SC520_PAR6, 0x30ff01f8); + + /* com2 use 2f8-2ff */ + + /* bring 0x300 - 0x3af back to ISA using PAR7 */ + write_mmcr_long(SC520_PAR7, 0x30af0300); + + /* vga use 3b0-3bb */ + + /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ + write_mmcr_long(SC520_PAR8, 0x300303bc); + + /* vga use 3c0-3df */ + + /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */ + write_mmcr_long(SC520_PAR9, 0x301503e0); + + /* ide use 3f6 */ + + /* bring 0x3f7 back to ISA using PAR10 */ + write_mmcr_long(SC520_PAR10, 0x300003f7); + + /* com1 use 3f8-3ff */ + + return 0; +} +#endif + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + init_sc520(); + bus_init(); + irq_init(); + + /* max drive current on SDRAM */ + write_mmcr_word(SC520_DSCTL, 0x0100); + + /* enter debug mode after next reset (only if jumper is also set) */ + write_mmcr_byte(SC520_RESCFG, 0x08); + /* configure the software timer to 33.333MHz */ + write_mmcr_byte(SC520_SWTMRCFG, 0); + gd->bus_clk = 33333000; + + return 0; +} + +int dram_init(void) +{ + init_sc520_dram(); + return 0; +} + +void show_boot_progress(int val) +{ + outb(val&0xff, 0x80); + outb((val&0xff00)>>8, 0x680); +} + + +int last_stage_init(void) +{ + int minor; + int major; + + major = minor = 0; + major |= ali512x_cio_in(23)?2:0; + major |= ali512x_cio_in(22)?1:0; + minor |= ali512x_cio_in(21)?2:0; + minor |= ali512x_cio_in(20)?1:0; + + printf("AMD SC520 CDP revision %d.%d\n", major, minor); + + return 0; +} + + +void ssi_chip_select(int dev) +{ + + /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */ + switch (dev) { + case 1: /* SPI EEPROM */ + ali512x_cio_out(16, 0); + break; + + case 2: /* MW EEPROM */ + ali512x_cio_out(15, 1); + break; + + case 3: /* AUX */ + ali512x_cio_out(14, 1); + break; + + case 0: + ali512x_cio_out(16, 1); + ali512x_cio_out(15, 0); + ali512x_cio_out(14, 0); + break; + + default: + printf("Illegal SSI device requested: %d\n", dev); + } +} + +void spi_eeprom_probe(int x) +{ +} + +int spi_eeprom_read(int x, int offset, char *buffer, int len) +{ + return 0; +} + +int spi_eeprom_write(int x, int offset, char *buffer, int len) +{ + return 0; +} + +void spi_init_f(void) +{ +#ifdef CONFIG_SC520_CDP_USE_SPI + spi_eeprom_probe(1); +#endif +#ifdef CONFIG_SC520_CDP_USE_MW + mw_eeprom_probe(2); +#endif +} + +ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) +{ + int offset; + int i; + ssize_t res; + + offset = 0; + for (i=0;i. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* now setup the General purpose bus to give us access to the LEDs. + * We can then use the leds to display status information. + */ + +sc520_cdp_registers: +/* size offset value */ +.word 1 ; .word 0x040 ; .long 0x00 /* SDRAM buffer control */ +.word 2 ; .word 0xc08 ; .long 0x0001 /* GP CS offset */ +.word 2 ; .word 0xc09 ; .long 0x0003 /* GP CS width */ +.word 2 ; .word 0xc0a ; .long 0x0001 /* GP CS width */ +.word 2 ; .word 0xc0b ; .long 0x0003 /* GP RD pulse width */ +.word 2 ; .word 0xc0c ; .long 0x0001 /* GP RD offse */ +.word 2 ; .word 0xc0d ; .long 0x0003 /* GP WR pulse width */ +.word 2 ; .word 0xc0e ; .long 0x0001 /* GP WR offset */ +.word 2 ; .word 0xc2c ; .long 0x0000 /* GPIO directionreg */ +.word 2 ; .word 0xc2a ; .long 0x0000 /* GPIO directionreg */ +.word 2 ; .word 0xc22 ; .long 0xffff /* GPIO pin function 31-16 reg */ +.word 2 ; .word 0xc20 ; .long 0xffff /* GPIO pin function 15-0 reg */ +.word 2 ; .word 0x0c4 ; .long 0x28000680 /* PAR 15 for access to led 680 */ +.word 0 ; .word 0x000 ; .long 0x00 + +/* board early intialization */ +.globl early_board_init +early_board_init: + movl $sc520_cdp_registers,%esi +init_loop: + movl $0xfffef000,%edi /* MMCR base to edi */ + movw (%esi), %bx /* load sizer to bx */ + cmpw $0, %bx /* if sie is 0 we're done */ + je done + xorl %edx,%edx + movw 2(%esi), %dx /* load MMCR offset to dx */ + addl %edx, %edi /* add offset to base in edi */ + movl 4(%esi), %eax /* load value in eax */ + cmpw $1, %bx + je byte /* byte op? */ + cmpw $2, %bx + je word /* word op? */ + movl %eax, (%edi) /* must be long, then */ + jmp next +byte: movb %al,(%edi) + jmp next +word: movw %ax,(%edi) +next: addl $8, %esi /* advance esi */ + jmp init_loop + + /* the leds ad 0x80 and 0x680 should now work */ +done: movb $0x88, %al + out %al, $0x80 + movw $0x680, %dx + out %al, %dx + + jmp *%ebp /* return to caller */ + + +.globl __show_boot_progress +__show_boot_progress: + out %al, $0x80 + xchg %al, %ah + movw $0x680, %dx + out %al, %dx + jmp *%ebp diff --git a/board/sc520_cdp/sc520_cdp_asm16.S b/board/sc520_cdp/sc520_cdp_asm16.S new file mode 100644 index 0000000..a3e700a --- /dev/null +++ b/board/sc520_cdp/sc520_cdp_asm16.S @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 16bit initialization code. + * This code have to map the area of the boot flash + * that is used by U-boot to its final destination. + */ + +.text +.section .start16, "ax" +.code16 +.globl board_init16 +board_init16: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* Map the entire flash at 0x38000000 + * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */ + movl $0xc0, %edi + movl $0x8bfff800, %eax + movl %eax, (%di) + + /* Disable SDRAM write buffer */ + movw $0x40,%di + xorw %ax,%ax + movb %al, (%di) + + /* Disabe MMCR alias */ + movw $0xfffc, %dx + movl $0x000000cb, %eax + outl %eax, %dx + + /* the return address is tored in bp */ + jmp *%bp + + +.section .bios, "ax" +.code16 +.globl realmode_reset +realmode_reset: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* issue software reset thorugh MMCR */ + movl $0xd72, %edi + movb $0x01, %al + movb %al, (%di) + +1: hlt + jmp 1 diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds new file mode 100644 index 0000000..72164a1 --- /dev/null +++ b/board/sc520_cdp/u-boot.lds @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ + . = 0x387c0000; /* Where bootcode in the flash is mapped */ + .text : { *(.text); } + + . = ALIGN(4); + .rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) } + + . = 0x400000; /* Ram data segment to use */ + _i386boot_romdata_dest = ABSOLUTE(.); + .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } + _i386boot_romdata_start = LOADADDR(.data); + + . = ALIGN(4); + .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } + _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); + + + . = ALIGN(4); + _i386boot_bss_start = ABSOLUTE(.); + .bss : { *(.bss) } + _i386boot_bss_size = SIZEOF(.bss); + + + /* 16bit realmode trampoline code */ + .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) } + + _i386boot_realmode = LOADADDR(.realmode); + _i386boot_realmode_size = SIZEOF(.realmode); + + /* 16bit BIOS emulation code (just enough to boot Linux) */ + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } + + _i386boot_bios = LOADADDR(.bios); + _i386boot_bios_size = SIZEOF(.bios); + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + /* The load addresses below assumes that the flash + * will be mapped so that 0x387f0000 == 0xffff0000 + * at reset time + * + * The fe00 and ff00 offsets of the start32 and start16 + * segments are arbitrary, the just have to be mapped + * at reset and the code have to fit. + * The fff0 offset of reset is important, however. + */ + + + . = 0xfffffe00; + .start32 : AT (0x387ffe00) { *(.start32); } + + . = 0xff00; + .start16 : AT (0x387fff00) { *(.start16); } + + . = 0xfff0; + .reset : AT (0x387ffff0) { *(.reset); } + _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); +} diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile new file mode 100644 index 0000000..242d53c --- /dev/null +++ b/board/sc520_spunk/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := sc520_spunk.o flash.o +SOBJS := sc520_spunk_asm.o sc520_spunk_asm16.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sc520_spunk/config.mk b/board/sc520_spunk/config.mk new file mode 100644 index 0000000..2253815 --- /dev/null +++ b/board/sc520_spunk/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +TEXT_BASE = 0x387c0000 diff --git a/board/sc520_spunk/flash.c b/board/sc520_spunk/flash.c new file mode 100644 index 0000000..4942e59 --- /dev/null +++ b/board/sc520_spunk/flash.c @@ -0,0 +1,809 @@ +/* + * (C) Copyright 2002, 2003 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define PROBE_BUFFER_SIZE 1024 +static unsigned char buffer[PROBE_BUFFER_SIZE]; + + +#define SC520_MAX_FLASH_BANKS 1 +#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ +#define SC520_FLASH_BANKSIZE 0x8000000 + +#define A29LV641DH_SIZE 0x800000 +#define A29LV641DH_SECTORS 128 + +#define A29LV641MH_SIZE 0x800000 +#define A29LV641MH_SECTORS 128 + +#define I28F320J3A_SIZE 0x400000 +#define I28F320J3A_SECTORS 32 + +#define I28F640J3A_SIZE 0x800000 +#define I28F640J3A_SECTORS 64 + +#define I28F128J3A_SIZE 0x1000000 +#define I28F128J3A_SECTORS 128 + +flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + + +static u32 _probe_flash(u32 addr, u32 bw, int il) +{ + u32 result=0; + + /* First do an unlock cycle for the benefit of + * devices that need it */ + + switch (bw) { + + case 1: + *(volatile u8*)(addr+0x5555) = 0xaa; + *(volatile u8*)(addr+0x2aaa) = 0x55; + *(volatile u8*)(addr+0x5555) = 0x90; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5555), 0xf0; + break; + + case 2: + *(volatile u16*)(addr+0xaaaa) = 0xaaaa; + *(volatile u16*)(addr+0x5554) = 0x5555; + + /* Issue identification command */ + if (il == 2) { + *(volatile u16*)(addr+0xaaaa) = 0x9090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u16*)addr = 0xffff; + *(volatile u16*)(addr+0xaaaa), 0xf0f0; + + } else { + *(volatile u8*)(addr+0xaaaa) = 0x90; + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0xaaaa), 0xf0; + } + + break; + + case 4: + *(volatile u32*)(addr+0x5554) = 0xaaaaaaaa; + *(volatile u32*)(addr+0xaaa8) = 0x55555555; + + switch (il) { + case 1: + /* Issue identification command */ + *(volatile u8*)(addr+0x5554) = 0x90; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5554), 0xf0; + break; + + case 2: + /* Issue identification command */ + *(volatile u32*)(addr + 0x5554) = 0x00900090; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0x00ff00ff; + *(volatile u32*)(addr+0x5554), 0x00f000f0; + break; + + case 4: + /* Issue identification command */ + *(volatile u32*)(addr+0x5554) = 0x90909090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0xffffffff; + *(volatile u32*)(addr+0x5554), 0xf0f0f0f0; + break; + } + break; + } + + + return result; +} + +extern int _probe_flash_end; +asm ("_probe_flash_end:\n" + ".long 0\n"); + +static int identify_flash(unsigned address, int width) +{ + int is; + int device; + int vendor; + int size; + unsigned res; + + u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il); + + size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_probe_flash() routine too large (%d) %p - %p\n", + size, &_probe_flash_end, _probe_flash); + return 0; + } + + memcpy(buffer, _probe_flash, size); + _probe_flash_ptr = (void*)buffer; + + is = disable_interrupts(); + res = _probe_flash_ptr(address, width, 1); + if (is) { + enable_interrupts(); + } + + + vendor = res >> 16; + device = res & 0xffff; + + + return res; +} + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { + unsigned id; + ulong flashbase = 0; + int sectsize = 0; + + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) { + case 0: + flashbase = SC520_FLASH_BANK0_BASE; + break; + default: + panic("configured too many flash banks!\n"); + } + + id = identify_flash(flashbase, 2); + switch (id) { + case 0x000122d7: + /* 29LV641DH */ + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV640U & FLASH_TYPEMASK); + + flash_info[i].size = A29LV641DH_SIZE; + flash_info[i].sector_count = A29LV641DH_SECTORS; + sectsize = A29LV641DH_SIZE/A29LV641DH_SECTORS; + printf("Bank %d: AMD 29LV641DH\n", i); + break; + + case 0x0001227E: + /* 29LV641MH */ + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_DL640 & FLASH_TYPEMASK); + + flash_info[i].size = A29LV641MH_SIZE; + flash_info[i].sector_count = A29LV641MH_SECTORS; + sectsize = A29LV641MH_SIZE/A29LV641MH_SECTORS; + printf("Bank %d: AMD 29LV641MH\n", i); + break; + + case 0x00890016: + /* 28F320J3A */ + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F320J3A & FLASH_TYPEMASK); + + flash_info[i].size = I28F320J3A_SIZE; + flash_info[i].sector_count = I28F320J3A_SECTORS; + sectsize = I28F320J3A_SIZE/I28F320J3A_SECTORS; + printf("Bank %d: Intel 28F320J3A\n", i); + break; + + case 0x00890017: + /* 28F640J3A */ + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F640J3A & FLASH_TYPEMASK); + + flash_info[i].size = I28F640J3A_SIZE; + flash_info[i].sector_count = I28F640J3A_SECTORS; + sectsize = I28F640J3A_SIZE/I28F640J3A_SECTORS; + printf("Bank %d: Intel 28F640J3A\n", i); + break; + + case 0x00890018: + /* 28F128J3A */ + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F128J3A & FLASH_TYPEMASK); + + flash_info[i].size = I28F128J3A_SIZE; + flash_info[i].sector_count = I28F128J3A_SECTORS; + sectsize = I28F128J3A_SIZE/I28F128J3A_SECTORS; + printf("Bank %d: Intel 28F128J3A\n", i); + break; + + default: + printf("Bank %d have unknown flash %08x\n", i, id); + flash_info[i].flash_id = FLASH_UNKNOWN; + continue; + } + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j * sectsize; + } + size += flash_info[i].size; + + flash_protect(FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + flash_info[i].size - 1, + &flash_info[i]); + } + + /* + * Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + i386boot_start, + i386boot_end, + &flash_info[0]); +#ifdef CFG_ENV_ADDR + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf("INTEL: "); + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F320J3A & FLASH_TYPEMASK): + printf("1x I28F320J3A (32Mbit)\n"); + break; + case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): + printf("1x I28F640J3A (64Mbit)\n"); + break; + case (INTEL_ID_28F128J3A & FLASH_TYPEMASK): + printf("1x I28F128J3A (128Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto done; + break; + } + + break; + + case (AMD_MANUFACT & FLASH_VENDMASK): + printf("AMD: "); + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV640U & FLASH_TYPEMASK): + printf("1x AMD29LV641DH (64Mbit)\n"); + break; + case (AMD_ID_DL640 & FLASH_TYPEMASK): + printf("1x AMD29LV641MH (64Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto done; + break; + } + + break; + default: + printf("Unknown Vendor "); + break; + } + + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + done: +} + +/*----------------------------------------------------------------------- + */ + + +static u32 _amd_erase_flash(u32 addr, u32 sector) +{ + unsigned elapsed; + + /* Issue erase */ + *(volatile u16*)(addr + 0xaaaa) = 0x00AA; + *(volatile u16*)(addr + 0x5554) = 0x0055; + *(volatile u16*)(addr + 0xaaaa) = 0x0080; + /* And one unlock */ + *(volatile u16*)(addr + 0xaaaa) = 0x00AA; + *(volatile u16*)(addr + 0x5554) = 0x0055; + /* Sector erase command comes last */ + *(volatile u16*)(addr + sector) = 0x0030; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) { + + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + *(volatile u16*)(addr) = 0x00f0; + return 1; + } + } + + *(volatile u16*)(addr) = 0x00f0; + + return 0; +} + +extern int _amd_erase_flash_end; +asm ("_amd_erase_flash_end:\n" + ".long 0\n"); + +/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */ +#define __udelay(delay) \ +{ \ + unsigned micro; \ + unsigned milli=0; \ + \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + \ + for (;;) { \ + \ + milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \ + \ + if ((delay) <= (micro + (milli * 1000))) { \ + break; \ + } \ + } \ +} while (0) + +static u32 _intel_erase_flash(u32 addr, u32 sector) +{ + unsigned elapsed; + + *(volatile u16*)(addr + sector) = 0x0050; /* clear status register */ + *(volatile u16*)(addr + sector) = 0x0020; /* erase setup */ + *(volatile u16*)(addr + sector) = 0x00D0; /* erase confirm */ + + + /* Wait at least 80us - let's wait 1 ms */ + __udelay(1000); + + elapsed = 0; + while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) { + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + *(volatile u16*)(addr + sector) = 0x00B0; /* suspend erase */ + *(volatile u16*)(addr + sector) = 0x00FF; /* reset to read mode */ + return 1; + } + } + + *(volatile u16*)(addr + sector) = 0x00FF; /* reset to read mode */ + + return 0; +} + + +extern int _intel_erase_flash_end; +asm ("_intel_erase_flash_end:\n" + ".long 0\n"); + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + u32 (*_erase_flash_ptr)(u32 a, u32 so); + int prot; + int sect; + unsigned size; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_erase_flash() routine too large (%d) %p - %p\n", + size, &_amd_erase_flash_end, _amd_erase_flash); + return 0; + } + + memcpy(buffer, _amd_erase_flash, size); + _erase_flash_ptr = (void*)buffer; + + } else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_intel_erase_flash_end - (unsigned)_intel_erase_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_intel_erase_flash() routine too large (%d) %p - %p\n", + size, &_intel_erase_flash_end, _intel_erase_flash); + return 0; + } + + memcpy(buffer, _intel_erase_flash, size); + _erase_flash_ptr = (void*)buffer; + } else { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + + if (info->protect[sect] == 0) { /* not protected */ + int res; + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + + if (res) { + printf("Erase timed out, sector %d\n", sect); + return res; + } + + putc('.'); + } + } + + + return 0; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int _amd_write_word(unsigned start, unsigned dest, unsigned data) +{ + volatile u16 *addr2 = (u16*)start; + volatile u16 *dest2 = (u16*)dest; + volatile u16 *data2 = (u16*)&data; + int i; + unsigned elapsed; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u16*)dest) & (u16)data) != (u16)data) { + return 2; + } + + for (i = 0; i < 2; i++) { + + + addr2[0x5555] = 0x00AA; + addr2[0x2aaa] = 0x0055; + addr2[0x5555] = 0x00A0; + + dest2[i] = (data >> (i*16)) & 0xffff; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + + /* data polling for D7 */ + while ((dest2[i] & 0x0080) != (data2[i] & 0x0080)) { + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + addr2[i] = 0x00f0; + return 1; + } + } + } + + addr2[i] = 0x00f0; + + return 0; +} + +extern int _amd_write_word_end; +asm ("_amd_write_word_end:\n" + ".long 0\n"); + + +static int _intel_write_word(unsigned start, unsigned dest, unsigned data) +{ + int i; + unsigned elapsed; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u16*)dest) & (u16)data) != (u16)data) { + return 2; + } + + for (i = 0; i < 2; i++) { + + *(volatile u16*)(dest+2*i) = 0x0040; /* write setup */ + *(volatile u16*)(dest+2*i) = (data >> (i*16)) & 0xffff; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + + /* data polling for D7 */ + while ((*(volatile u16*)dest & 0x0080) != 0x0080) { + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + *(volatile u16*)dest = 0x00ff; + return 1; + } + } + } + + *(volatile u16*)dest = 0x00ff; + + + return 0; + +} + +extern int _intel_write_word_end; +asm ("_intel_write_word_end:\n" + ".long 0\n"); + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 3 - Unsupported flash type + */ + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + int flag; + u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data); + unsigned size; + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_write_word() routine too large (%d) %p - %p\n", + size, &_amd_write_word_end, _amd_write_word); + return 0; + } + + memcpy(buffer, _amd_write_word, size); + _write_word_ptr = (void*)buffer; + + } else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_intel_write_word_end - (unsigned)_intel_write_word; + + if (size > PROBE_BUFFER_SIZE) { + printf("_intel_write_word() routine too large (%d) %p - %p\n", + size, &_intel_write_word_end, _intel_write_word); + return 0; + } + + memcpy(buffer, _intel_write_word, size); + _write_word_ptr = (void*)buffer; + } else { + printf ("Can't program unknown flash type - aborted\n"); + return 3; + } + + + wp = (addr & ~3); /* get lower word aligned address */ + + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data |= *src++ << (8*i); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + + for (i=0; i<4; ++i) { + data |= *src++ << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return 0; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data |= *src++ << (8*i); + --cnt; + } + + for (; i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + return rc; + +} diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c new file mode 100644 index 0000000..e7a7d51 --- /dev/null +++ b/board/sc520_spunk/sc520_spunk.c @@ -0,0 +1,681 @@ +/* + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* ------------------------------------------------------------------------- */ + + +/* + * Theory: + * We first set up all IRQs to be non-pci, edge triggered, + * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets + * called we reallocate irqs to the pci bus with sc520_pci_set_irq() + * as needed. Whe choose the irqs to gram from a configurable list + * inside pci_sc520_fixup_irq() (If this list contains stupid irq's + * such as 0 thngas will not work) + */ + +static void irq_init(void) +{ + /* disable global interrupt mode */ + write_mmcr_byte(SC520_PICICR, 0x40); + + /* set all irqs to edge */ + write_mmcr_byte(SC520_MPICMODE, 0x00); + write_mmcr_byte(SC520_SL1PICMODE, 0x00); + write_mmcr_byte(SC520_SL2PICMODE, 0x00); + + /* active low polarity on PIC interrupt pins, + * active high polarity on all other irq pins */ + write_mmcr_word(SC520_INTPINPOL, 0x0000); + + /* set irq number mapping */ + write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ + write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ + write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ + write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ + write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ + write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ + write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ + write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ + write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ + write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ + write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ + write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6); /* Set Synchronius serial INT to IRQ6*/ + write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ + write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ + write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ + write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ + write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ + + write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ + write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ + + write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7); /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */ + write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14); /* Set GPIRQ1 (CF IRQ) to IRQ14 */ + write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5); /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */ + write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disbale GIRQ4 ( IRR IRQ ) */ + write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ5 */ + write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ6 */ + write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ7 */ + write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ8 */ + write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ9 */ + write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ2 */ + write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED); /* disable GPIRQ10 */ + + write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ + write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ + +} + + +/* PCI stuff */ +static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + int version = read_mmcr_byte(SC520_SYSINFO); + + /* a configurable lists of irqs to steal + * when we need one (a board with more pci interrupt pins + * would use a larger table */ + static int irq_list[] = { + CFG_FIRST_PCI_IRQ, + CFG_SECOND_PCI_IRQ, + CFG_THIRD_PCI_IRQ, + CFG_FORTH_PCI_IRQ + }; + static int next_irq_index=0; + + char tmp_pin; + int pin; + + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); + pin = tmp_pin; + + pin-=1; /* pci config space use 1-based numbering */ + if (-1 == pin) { + return; /* device use no irq */ + } + + + /* map device number + pin to a pin on the sc520 */ + switch (PCI_DEV(dev)) { + case 6: /* ETH0 */ + pin+=SC520_PCI_INTA; + break; + + case 7: /* ETH1 */ + pin+=SC520_PCI_INTB; + break; + + case 8: /* Crypto */ + pin+=SC520_PCI_INTC; + break; + + case 9: /* PMC slot */ + pin+=SC520_PCI_INTD; + break; + + case 10: /* PC-Card */ + + if (version < 10) { + pin+=SC520_PCI_INTD; + } else { + pin+=SC520_PCI_INTC; + } + break; + + default: + return; + } + + pin&=3; /* wrap around */ + + if (sc520_pci_ints[pin] == -1) { + /* re-route one interrupt for us */ + if (next_irq_index > 3) { + return; + } + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + return; + } + next_irq_index++; + } + + + if (-1 != sc520_pci_ints[pin]) { + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + sc520_pci_ints[pin]); + } +#if 0 + printf("fixup_irq: device %d pin %c irq %d\n", + PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); +#endif +} + + +static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *te) +{ + u32 io_base; + u32 temp; + + pciauto_config_device(hose, dev); + + pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */ + pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */ + pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */ + pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */ + pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */ + pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */ + pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */ + + pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */ + pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */ + /* route MF0 to ~INT and MF3 to IRQ7 + * reserve all others */ + pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); + pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */ + pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */ + + if (te->device != 0xac56) { + pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */ + pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */ + pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */ + pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */ + pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */ + } else { + pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */ + } + pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */ + + + pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base); + io_base &= ~0xfL; + + writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */ + writel(0, io_base+0x10); /* CLKRUN default */ + writel(0, io_base+0x20); /* CLKRUN default */ + +} + + +static struct pci_config_table pci_sc520_spunk_config_table[] = { + { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, + { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, + { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}} +}; + +static struct pci_controller sc520_spunk_hose = { + fixup_irq: pci_sc520_spunk_fixup_irq, + config_table: pci_sc520_spunk_config_table, + first_busno: 0x00, + last_busno: 0xff, +}; + +void pci_init_board(void) +{ + pci_sc520_init(&sc520_spunk_hose); +} + + +/* set up the ISA bus timing and system address mappings */ +static void bus_init(void) +{ + /* versions + * 0 Hyglo versions 0.95 and 0.96 (large baords) + * ?? Hyglo version 0.97 (small board) + * 10 Spunk board + */ + int version = read_mmcr_byte(SC520_SYSINFO); + + if (version) { + /* set up the GP IO pins (for the Spunk board) */ + write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */ + write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */ + write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */ + write_mmcr_byte(SC520_CLKSEL, 0x70); + + write_mmcr_word(SC520_PIOCLR31_16, 0x0003); /* reset SSI chip-selects */ + write_mmcr_word(SC520_PIOSET31_16, 0x000c); + + } else { + /* set up the GP IO pins (for the Hyglo board) */ + write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */ + write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */ + write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */ + write_mmcr_byte(SC520_CLKSEL, 0x70); + + write_mmcr_word(SC520_PIOCLR15_0, 0x0180); /* reset SSI chip-selects */ + } + + write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ + write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ + write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ + write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ + write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ + write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ + write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ + + write_mmcr_word(SC520_BOOTCSCTL, 0x0407); /* set up timing of BOOTCS */ + + /* adjust the memory map: + * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM + * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio + * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ + + + /* bootcs */ + write_mmcr_long(SC520_PAR12, 0x8bffe800); + + /* IDE0 = GPCS6 1f0-1f7 */ + write_mmcr_long(SC520_PAR3, 0x380801f0); + + /* IDE1 = GPCS7 3f6 */ + write_mmcr_long(SC520_PAR4, 0x3c0003f6); + + asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ + + write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); + +} + + +/* par usage: + * PAR0 (legacy_video) + * PAR1 (PCI ROM mapping) + * PAR2 + * PAR3 IDE + * PAR4 IDE + * PAR5 (legacy_video) + * PAR6 + * PAR7 (legacy_video) + * PAR8 (legacy_video) + * PAR9 (legacy_video) + * PAR10 + * PAR11 (ISAROM) + * PAR12 BOOTCS + * PAR13 + * PAR14 + * PAR15 + */ + +/* + * This function should map a chunk of size bytes + * of the system address space to the ISA bus + * + * The function will return the memory address + * as seen by the host (which may very will be the + * same as the bus address) + */ +u32 isa_map_rom(u32 bus_addr, int size) +{ + u32 par; + + printf("isa_map_rom asked to map %d bytes at %x\n", + size, bus_addr); + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 12; + par--; + par&=0x7f; + par <<= 18; + par |= (bus_addr>>12); + par |= 0x50000000; + + printf ("setting PAR11 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR11, par); + + return bus_addr; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void isa_unmap_rom(u32 addr) +{ + printf("isa_unmap_rom asked to unmap %x", addr); + if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { + write_mmcr_long(SC520_PAR11, 0); + printf(" done\n"); + return; + } + printf(" not ours\n"); +} + +#ifdef CONFIG_PCI +#define PCI_ROM_TEMP_SPACE 0x10000 +/* + * This function should map a chunk of size bytes + * of the system address space to the PCI bus, + * suitable to map PCI ROMS (bus address < 16M) + * the function will return the host memory address + * which should be converted into a bus address + * before used to configure the PCI rom address + * decoder + */ +u32 pci_get_rom_window(struct pci_controller *hose, int size) +{ + u32 par; + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 16; + par--; + par&=0x7ff; + par <<= 14; + par |= (PCI_ROM_TEMP_SPACE>>16); + par |= 0x72000000; + + printf ("setting PAR1 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR1, par); + + return PCI_ROM_TEMP_SPACE; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void pci_remove_rom_window(struct pci_controller *hose, u32 addr) +{ + printf("pci_remove_rom_window: %x", addr); + if (addr == PCI_ROM_TEMP_SPACE) { + write_mmcr_long(SC520_PAR1, 0); + printf(" done\n"); + return; + } + printf(" not ours\n"); + +} + +/* + * This function is called in order to provide acces to the + * legacy video I/O ports on the PCI bus. + * After this function accesses to I/O ports 0x3b0-0x3bb and + * 0x3c0-0x3df shuld result in transactions on the PCI bus. + * + */ +int pci_enable_legacy_video_ports(struct pci_controller *hose) +{ + /* Map video memory to 0xa0000*/ + write_mmcr_long(SC520_PAR0, 0x7200400a); + + /* forward all I/O accesses to PCI */ + write_mmcr_byte(SC520_ADDDECCTL, + read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); + + + /* so we map away all io ports to pci (only way to access pci io + * below 0x400. But then we have to map back the portions that we dont + * use so that the generate cycles on the GPIO bus where the sio and + * ISA slots are connected, this requre the use of several PAR registers + */ + + /* bring 0x100 - 0x2f7 back to ISA using PAR5 */ + write_mmcr_long(SC520_PAR5, 0x31f70100); + + /* com2 use 2f8-2ff */ + + /* bring 0x300 - 0x3af back to ISA using PAR7 */ + write_mmcr_long(SC520_PAR7, 0x30af0300); + + /* vga use 3b0-3bb */ + + /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ + write_mmcr_long(SC520_PAR8, 0x300303bc); + + /* vga use 3c0-3df */ + + /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */ + write_mmcr_long(SC520_PAR9, 0x301703e0); + + /* com1 use 3f8-3ff */ + + return 0; +} +#endif + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + init_sc520(); + bus_init(); + irq_init(); + + /* max drive current on SDRAM */ + write_mmcr_word(SC520_DSCTL, 0x0100); + + /* enter debug mode after next reset (only if jumper is also set) */ + write_mmcr_byte(SC520_RESCFG, 0x08); + /* configure the software timer to 33.000MHz */ + write_mmcr_byte(SC520_SWTMRCFG, 1); + gd->bus_clk = 33000000; + + return 0; +} + +int dram_init(void) +{ + init_sc520_dram(); + return 0; +} + +void show_boot_progress(int val) +{ + int version = read_mmcr_byte(SC520_SYSINFO); + + if (version == 0) { + /* PIO31-PIO16 Data */ + write_mmcr_word(SC520_PIODATA31_16, + (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */ + + /* PIO0-PIO15 Data */ + write_mmcr_word(SC520_PIODATA15_0, + (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13)); + } else { + /* newer boards use PIO4-PIO12 */ + /* PIO0-PIO15 Data */ +#if 0 + val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3); +#else + val = (val & 0x007) | ((val & 0x07e) << 2); +#endif + write_mmcr_word(SC520_PIODATA15_0, + (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4)); + } +} + + +int last_stage_init(void) +{ + + int version = read_mmcr_byte(SC520_SYSINFO); + + printf("Omicron Ceti SC520 Spunk revision %x\n", version); + +#if 0 + if (version) { + int x, y; + + printf("eeprom probe %d\n", spi_eeprom_probe(1)); + + spi_eeprom_read(1, 0, (u8*)&x, 2); + spi_eeprom_read(1, 1, (u8*)&y, 2); + printf("eeprom bytes %04x%04x\n", x, y); + x ^= 0xffff; + y ^= 0xffff; + spi_eeprom_write(1, 0, (u8*)&x, 2); + spi_eeprom_write(1, 1, (u8*)&y, 2); + + spi_eeprom_read(1, 0, (u8*)&x, 2); + spi_eeprom_read(1, 1, (u8*)&y, 2); + printf("eeprom bytes %04x%04x\n", x, y); + + } else { + int x, y; + + printf("eeprom probe %d\n", mw_eeprom_probe(1)); + + mw_eeprom_read(1, 0, (u8*)&x, 2); + mw_eeprom_read(1, 1, (u8*)&y, 2); + printf("eeprom bytes %04x%04x\n", x, y); + + x ^= 0xffff; + y ^= 0xffff; + mw_eeprom_write(1, 0, (u8*)&x, 2); + mw_eeprom_write(1, 1, (u8*)&y, 2); + + mw_eeprom_read(1, 0, (u8*)&x, 2); + mw_eeprom_read(1, 1, (u8*)&y, 2); + printf("eeprom bytes %04x%04x\n", x, y); + + + } +#endif + + ds1722_probe(2); + + return 0; +} + +void ssi_chip_select(int dev) +{ + int version = read_mmcr_byte(SC520_SYSINFO); + + if (version) { + /* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */ + switch (dev) { + case 1: /* EEPROM */ + write_mmcr_word(SC520_PIOCLR31_16, 0x0004); + break; + + case 2: /* Temp Probe */ + write_mmcr_word(SC520_PIOSET31_16, 0x0002); + break; + + case 3: /* CAN */ + write_mmcr_word(SC520_PIOCLR31_16, 0x0008); + break; + + case 4: /* AUX */ + write_mmcr_word(SC520_PIOSET31_16, 0x0001); + break; + + case 0: + write_mmcr_word(SC520_PIOCLR31_16, 0x0003); + write_mmcr_word(SC520_PIOSET31_16, 0x000c); + break; + + default: + printf("Illegal SSI device requested: %d\n", dev); + } + } else { + + /* Globox board: Both EEPROM and TEMP are active-high */ + + switch (dev) { + case 1: /* EEPROM */ + write_mmcr_word(SC520_PIOSET15_0, 0x0100); + break; + + case 2: /* Temp Probe */ + write_mmcr_word(SC520_PIOSET15_0, 0x0080); + break; + + case 0: + write_mmcr_word(SC520_PIOCLR15_0, 0x0180); + break; + + default: + printf("Illegal SSI device requested: %d\n", dev); + } + } +} + + +void spi_init_f(void) +{ + read_mmcr_byte(SC520_SYSINFO) ? + spi_eeprom_probe(1) : + mw_eeprom_probe(1); + +} + +ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) +{ + int offset; + int i; + + offset = 0; + for (i=0;i. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* now setup the General purpose bus to give us access to the LEDs. + * We can then use the leds to display status information. + */ + +sc520_cdp_registers: +/* size offset value */ +.word 1 ; .word 0x040 ; .long 0x00 /* SDRAM buffer control */ +.word 2 ; .word 0xc08 ; .long 0x0001 /* GP CS offset */ +.word 2 ; .word 0xc09 ; .long 0x0003 /* GP CS width */ +.word 2 ; .word 0xc0a ; .long 0x0001 /* GP CS width */ +.word 2 ; .word 0xc0b ; .long 0x0003 /* GP RD pulse width */ +.word 2 ; .word 0xc0c ; .long 0x0001 /* GP RD offse */ +.word 2 ; .word 0xc0d ; .long 0x0003 /* GP WR pulse width */ +.word 2 ; .word 0xc0e ; .long 0x0001 /* GP WR offset */ +.word 2 ; .word 0xc2c ; .long 0x003f /* GPIO directionreg 31-16 */ +.word 2 ; .word 0xc2a ; .long 0xe000 /* GPIO directionreg 15-0 */ +.word 2 ; .word 0xc22 ; .long 0xffc0 /* GPIO pin function 31-16 reg */ +.word 2 ; .word 0xc20 ; .long 0x1fff /* GPIO pin function 15-0 reg */ +.word 0 ; .word 0x000 ; .long 0x00 + +/* board early intialization */ +.globl early_board_init +early_board_init: + movl $sc520_cdp_registers,%esi +init_loop: + movl $0xfffef000,%edi /* MMCR base to edi */ + movw (%esi), %bx /* load size to bx */ + cmpw $0, %bx /* if size is 0 we're done */ + je done + xorl %edx,%edx + movw 2(%esi), %dx /* load MMCR offset to dx */ + addl %edx, %edi /* add offset to base in edi */ + movl 4(%esi), %eax /* load value in eax */ + cmpw $1, %bx + je byte /* byte op? */ + cmpw $2, %bx + je word /* word op? */ + movl %eax, (%edi) /* must be long, then */ + jmp next +byte: movb %al,(%edi) + jmp next +word: movw %ax,(%edi) +next: addl $8, %esi /* advance esi */ + jmp init_loop + + /* light all leds */ +done: movl $0xfffefc32,%edx + movw $0000,(%edx) + + jmp *%ebp /* return to caller */ + + +.globl __show_boot_progress +__show_boot_progress: + movl $0xfffefc32,%edx + xorw $0xffff, %ax + movw %ax,(%edx) + jmp *%ebp diff --git a/board/sc520_spunk/sc520_spunk_asm16.S b/board/sc520_spunk/sc520_spunk_asm16.S new file mode 100644 index 0000000..8bb1766 --- /dev/null +++ b/board/sc520_spunk/sc520_spunk_asm16.S @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 16bit initialization code. + * This code have to map the area of the boot flash + * that is used by U-boot to its final destination. + */ + +.text +.section .start16, "ax" +.code16 +.globl board_init16 +board_init16: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* Map the entire flash at 0x38000000 + * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */ + movl $0xc0, %edi + movl $0x8bfff800, %eax + movl %eax, (%di) + + /* Disable SDRAM write buffer */ + movw $0x40,%di + xorw %ax,%ax + movb %al, (%di) + + /* Disabe MMCR alias */ + movw $0xfffc, %dx + movl $0x000000cb, %eax + outl %eax, %dx + + /* the return address is stored in bp */ + jmp *%bp + + +.section .bios, "ax" +.code16 +.globl realmode_reset +realmode_reset: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* issue software reset thorugh MMCR */ + movl $0xd72, %edi + movb $0x01, %al + movb %al, (%di) + +1: hlt + jmp 1 diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds new file mode 100644 index 0000000..127d707 --- /dev/null +++ b/board/sc520_spunk/u-boot.lds @@ -0,0 +1,92 @@ + +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ + . = 0x387c0000; /* Where bootcode in the flash is mapped */ + .text : { *(.text); } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = 0x400000; /* Ram data segment to use */ + _i386boot_romdata_dest = ABSOLUTE(.); + .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } + _i386boot_romdata_start = LOADADDR(.data); + + . = ALIGN(4); + .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } + _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); + + + . = ALIGN(4); + _i386boot_bss_start = ABSOLUTE(.); + .bss : { *(.bss) } + _i386boot_bss_size = SIZEOF(.bss); + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + /* 16bit realmode trampoline code */ + .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) } + + _i386boot_realmode = LOADADDR(.realmode); + _i386boot_realmode_size = SIZEOF(.realmode); + + /* 16bit BIOS emulation code (just enough to boot Linux) */ + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } + + _i386boot_bios = LOADADDR(.bios); + _i386boot_bios_size = SIZEOF(.bios); + + + /* The load addresses below assumes that the flash + * will be mapped so that 0x387f0000 == 0xffff0000 + * at reset time + * + * The fe00 and ff00 offsets of the start32 and start16 + * segments are arbitrary, the just have to be mapped + * at reset and the code have to fit. + * The fff0 offset of reset is important, however. + */ + + + . = 0xfffffe00; + .start32 : AT (0x387ffe00) { *(.start32); } + + . = 0xff00; + .start16 : AT (0x387fff00) { *(.start16); } + + . = 0xfff0; + .reset : AT (0x387ffff0) { *(.reset); } + _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); +} diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile new file mode 100644 index 0000000..5dc3fd4 --- /dev/null +++ b/board/scb9328/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := scb9328.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/scb9328/config.mk b/board/scb9328/config.mk new file mode 100644 index 0000000..8d1d79a --- /dev/null +++ b/board/scb9328/config.mk @@ -0,0 +1,10 @@ +# +# This config file is used for compilation of scb93328 sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +# + +TEXT_BASE = 0x08f00000 diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c new file mode 100644 index 0000000..1b56f8c --- /dev/null +++ b/board/scb9328/flash.c @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This code was inspired by Marius Groeger and Kyle Harris code + * available in other board ports for U-Boot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#include +#include "intel.h" + + +/* + * This code should handle CFI FLASH memory device. This code is very + * minimalistic approach without many essential error handling code as well. + * Because U-Boot actually is missing smart handling of FLASH device, + * we just set flash_id to anything else to FLASH_UNKNOW, so common code + * can call us without any restrictions. + * TODO: Add CFI Query, to be able to determine FLASH device. + * TODO: Add error handling code + * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but + * hopefully may work with other configurations. + */ + +#if ( SCB9328_FLASH_BUS_WIDTH == 1 ) +# define FLASH_BUS vu_char +# if ( SCB9328_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# else +# error "With 8bit bus only one chip is allowed" +# endif + + +#elif ( SCB9328_FLASH_BUS_WIDTH == 2 ) +# define FLASH_BUS vu_short +# if ( SCB9328_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( SCB9328_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 8 )| x ) +# else +# error "With 16bit bus only 1 or 2 chip(s) are allowed" +# endif + + +#elif ( SCB9328_FLASH_BUS_WIDTH == 4 ) +# define FLASH_BUS vu_long +# if ( SCB9328_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( SCB9328_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 16 )| x ) +# elif ( SCB9328_FLASH_INTERLEAVE == 4 ) +# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) +# else +# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" +# endif + +#else +# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" +#endif + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static FLASH_BUS flash_status_reg (void) +{ + + FLASH_BUS *addr = (FLASH_BUS *) 0; + + *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); + + return *addr; +} + +static int flash_ready (ulong timeout) +{ + int ok = 1; + + reset_timer_masked (); + while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != + FLASH_CMD (CFI_INTEL_SR_READY)) { + if (get_timer_masked () > timeout && timeout != 0) { + ok = 0; + break; + } + } + return ok; +} + +#if ( CFG_MAX_FLASH_BANKS != 1 ) +# error "SCB9328 platform has only one flash bank!" +#endif + + +ulong flash_init (void) +{ + int i; + unsigned long address = SCB9328_FLASH_BASE; + + flash_info[0].size = SCB9328_FLASH_BANK_SIZE; + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + flash_info[0].flash_id = INTEL_MANUFACT; + memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + + for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { + flash_info[0].start[i] = address; +#ifdef SCB9328_FLASH_UNLOCK + /* Some devices are hw locked after start. */ + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); + flash_ready (0); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); +#endif + address += SCB9328_FLASH_SECT_SIZE; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return SCB9328_FLASH_BANK_SIZE; +} + +void flash_print_info (flash_info_t * info) +{ + int i; + + printf (" Intel vendor\n"); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if (!(i % 5)) { + printf ("\n"); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, non_protected = 0, sector; + int rc = ERR_OK; + + FLASH_BUS *address; + + for (sector = s_first; sector <= s_last; sector++) { + if (!info->protect[sector]) { + non_protected++; + } + } + + if (!non_protected) { + return ERR_PROTECTED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + + /* Start erase on unprotected sectors */ + for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { + if (info->protect[sector]) { + printf ("Protected sector %2d skipping...\n", sector); + continue; + } else { + printf ("Erasing sector %2d ... ", sector); + } + + address = (FLASH_BUS *) (info->start[sector]); + + *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); + *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); + if (flash_ready (CFG_FLASH_ERASE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + printf ("ok.\n"); + } else { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + break; + } + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) +{ + FLASH_BUS *address = (FLASH_BUS *) dest; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*address & data) != data) { + return ERR_NOT_ERASED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + flag = disable_interrupts (); + + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); + *address = data; + + if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + } + + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong read_addr, write_addr; + FLASH_BUS data; + int i, result = ERR_OK; + + + read_addr = addr & ~(sizeof (FLASH_BUS) - 1); + write_addr = read_addr; + if (read_addr != addr) { + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (read_addr < addr || cnt == 0) { + data |= *((uchar *) read_addr) << i * 8; + } else { + data |= (*src++) << i * 8; + cnt--; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + } + for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { + if ((result = write_data (info, write_addr, + *((FLASH_BUS *) src))) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + src += sizeof (FLASH_BUS); + } + if (cnt > 0) { + read_addr = write_addr; + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (cnt > 0) { + data |= (*src++) << i * 8; + cnt--; + } else { + data |= *((uchar *) read_addr) << i * 8; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != 0) { + return result; + } + } + return ERR_OK; +} diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h new file mode 100644 index 0000000..77498b6 --- /dev/null +++ b/board/scb9328/intel.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2002 ETC s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Marcel Telka , 2002. + * + * Documentation: + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + */ + +#ifndef FLASH_INTEL_H +#define FLASH_INTEL_H + +#include + +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ + +#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ + +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ + +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ + +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ + +#define CFI_CHIP_INTEL_28F320J3A 0x0016 +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" +#define CFI_CHIP_INTEL_28F640J3A 0x0017 +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" +#define CFI_CHIP_INTEL_28F128J3A 0x0018 +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" + +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ + +#define CFI_CHIP_INTEL_28F640K3 0x8801 +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" +#define CFI_CHIP_INTEL_28F128K3 0x8802 +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" +#define CFI_CHIP_INTEL_28F256K3 0x8803 +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" +#define CFI_CHIP_INTEL_28F640K18 0x8805 +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" +#define CFI_CHIP_INTEL_28F128K18 0x8806 +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" +#define CFI_CHIP_INTEL_28F256K18 0x8807 +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" + +#endif /* FLASH_INTEL_H */ diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S new file mode 100644 index 0000000..ba3b6d2 --- /dev/null +++ b/board/scb9328/lowlevel_init.S @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + * 02111-1307, USA. + * + */ + +#include +#include +#include + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + +/* Change PERCLK1DIV to 14 ie 14+1 */ + ldr r0, =PCDR + ldr r1, =CFG_PCDR_VAL + str r1, [r0] + +/* set MCU PLL Control Register 0 */ + + ldr r0, =MPCTL0 + ldr r1, =CFG_MPCTL0_VAL + str r1, [r0] + +/* set mpll restart bit */ + ldr r0, =CSCR + ldr r1, [r0] + orr r1,r1,#(1<<21) + str r1, [r0] + + mov r2,#0x10 +1: + mov r3,#0x2000 +2: + subs r3,r3,#1 + bne 2b + + subs r2,r2,#1 + bne 1b + +/* set System PLL Control Register 0 */ + + ldr r0, =SPCTL0 + ldr r1, =CFG_SPCTL0_VAL + str r1, [r0] + +/* set spll restart bit */ + ldr r0, =CSCR + ldr r1, [r0] + orr r1,r1,#(1<<22) + str r1, [r0] + + mov r2,#0x10 +1: + mov r3,#0x2000 +2: + subs r3,r3,#1 + bne 2b + + subs r2,r2,#1 + bne 1b + + ldr r0, =CSCR + ldr r1, =CFG_CSCR_VAL + str r1, [r0] + +/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon + *this..... + * + * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 + * register 1, this stops it using the output of the PLL and thus runs at the + * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never + * use the value set in the CM_OSC registers...regardless of what you set it + * too! Thus, although i thought i was running at 140MHz, i'm actually running + * at 40!.. + + * Slapping this into my bootloader does the trick... + + * MRC p15,0,r0,c1,c0,0 ; read core configuration register + * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode + * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration + * register + */ + MRC p15,0,r0,c1,c0,0 + ORR r0,r0,#0xC0000000 + MCR p15,0,r0,c1,c0,0 + + ldr r0, =GPR(0) + ldr r1, =CFG_GPR_A_VAL + str r1, [r0] + + ldr r0, =GIUS(0) + ldr r1, =CFG_GIUS_A_VAL + str r1, [r0] + +/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ + + ldr r0, =FMCR + ldr r1, =CFG_FMCR_VAL + str r1, [r0] + + ldr r0, =CS0U + ldr r1, =CFG_CS0U_VAL + str r1, [r0] + + ldr r0, =CS0L + ldr r1, =CFG_CS0L_VAL + str r1, [r0] + + ldr r0, =CS1U + ldr r1, =CFG_CS1U_VAL + str r1, [r0] + + ldr r0, =CS1L + ldr r1, =CFG_CS1L_VAL + str r1, [r0] + + ldr r0, =CS2U + ldr r1, =CFG_CS2U_VAL + str r1, [r0] + + ldr r0, =CS2L + ldr r1, =CFG_CS2L_VAL + str r1, [r0] + + ldr r0, =CS3U + ldr r1, =CFG_CS3U_VAL + str r1, [r0] + + ldr r0, =CS3L + ldr r1, =CFG_CS3L_VAL + str r1, [r0] + + ldr r0, =CS4U + ldr r1, =CFG_CS4U_VAL + str r1, [r0] + + ldr r0, =CS4L + ldr r1, =CFG_CS4L_VAL + str r1, [r0] + + ldr r0, =CS5U + ldr r1, =CFG_CS5U_VAL + str r1, [r0] + + ldr r0, =CS5L + ldr r1, =CFG_CS5L_VAL + str r1, [r0] + +/* SDRAM Setup */ + + ldr r0, =SDCTL0 + ldr r1, =PRECHARGE_CMD + str r1, [r0] + + ldr r0, =0x08200000 + ldr r1, =0x0 /* Issue Precharge all Command */ + str r1, [r0] + + ldr r0, =SDCTL0 + ldr r1, =AUTOREFRESH_CMD + str r1, [r0] + + ldr r0, =0x08000000 + ldr r1, =0x0 /* Issue AutoRefresh Command */ + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + + ldr r0, =SDCTL0 + ldr r1, =0xb10a8300 + str r1, [r0] + + ldr r0, =0x08223000 /* CAS Latency 2 */ + ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */ + str r1, [r0] + + ldr r0, =SDCTL0 + ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */ + str r1, [r0] + + mov pc,r10 diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c new file mode 100644 index 0000000..3ed8753 --- /dev/null +++ b/board/scb9328/scb9328.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +int board_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = MACH_TYPE_SCB9328; + gd->bd->bi_boot_params = 0x08000100; + + return 0; +} + +int dram_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + +#if ( CONFIG_NR_DRAM_BANKS > 0 ) + gd->bd->bi_dram[0].start = SCB9328_SDRAM_1; + gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 1 ) + gd->bd->bi_dram[1].start = SCB9328_SDRAM_2; + gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 2 ) + gd->bd->bi_dram[2].start = SCB9328_SDRAM_3; + gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 3 ) + gd->bd->bi_dram[3].start = SCB9328_SDRAM_4; + gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE; +#endif + + return 0; +} + +/** + * show_boot_progress: - indicate state of the boot process + * + * @param status: Status number - see README for details. + * + * The CSB226 does only have 3 LEDs, so we switch them on at the most + * important states (1, 5, 15). + */ + +void show_boot_progress (int status) +{ + return; +} diff --git a/board/scb9328/u-boot.lds b/board/scb9328/u-boot.lds new file mode 100644 index 0000000..1d1669c --- /dev/null +++ b/board/scb9328/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/shannon/Makefile b/board/shannon/Makefile new file mode 100644 index 0000000..f66b096 --- /dev/null +++ b/board/shannon/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := shannon.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/shannon/config.mk b/board/shannon/config.mk new file mode 100644 index 0000000..ca45733 --- /dev/null +++ b/board/shannon/config.mk @@ -0,0 +1,23 @@ +# +# LART board with SA1100 cpu +# +# see http://www.lart.tudelft.nl/ for more information on LART +# + +# +# Tuxscreen has 4 banks of 4 MB DRAM each +# +# c000'0000 +# c800'0000 +# d000'0000 +# d800'0000 +# +# Linux-Kernel is expected to be at c000'8000, entry c000'8000 +# +# we load ourself to d838'0000, the upper 1 MB of the last (4th) bank +# +# download areas is c800'0000 +# + + +TEXT_BASE = 0xd8380000 diff --git a/board/shannon/flash.c b/board/shannon/flash.c new file mode 100644 index 0000000..13c01d8 --- /dev/null +++ b/board/shannon/flash.c @@ -0,0 +1,473 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +ulong myflush(void); + + +#define FLASH_BANK_SIZE 0x400000 /* 4 MB */ +#define MAIN_SECT_SIZE 0x20000 /* 128 KB */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +#define CMD_READ_ARRAY 0x00F000F0 +#define CMD_UNLOCK1 0x00AA00AA +#define CMD_UNLOCK2 0x00550055 +#define CMD_ERASE_SETUP 0x00800080 +#define CMD_ERASE_CONFIRM 0x00300030 +#define CMD_PROGRAM 0x00A000A0 +#define CMD_UNLOCK_BYPASS 0x00200020 + +#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2))) +#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2))) + +#define BIT_ERASE_DONE 0x00800080 +#define BIT_RDY_MASK 0x00800080 +#define BIT_PROGRAM_ERROR 0x00200020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + ulong flashbase = 0; + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV160B & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) + { + + if (j <= 3) + { + /* 1st one is 32 KB */ + if (j == 0) + { + flash_info[i].start[j] = flashbase + 0; + } + + /* 2nd and 3rd are both 16 KB */ + if ((j == 1) || (j == 2)) + { + flash_info[i].start[j] = flashbase + 0x8000 + (j-1)*0x4000; + } + + /* 4th 64 KB */ + if (j == 3) + { + flash_info[i].start[j] = flashbase + 0x10000; + } + } + else + { + flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + /* + * Protect monitor and environment sectors + * Inferno is complicated, it's hardware locked + */ +#ifdef CONFIG_INFERNO + /* first one, 0x00000 to 0x07fff */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE + 0x00000, + CFG_FLASH_BASE + 0x08000 - 1, + &flash_info[0]); + + /* third to 10th, 0x0c000 - 0xdffff */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE + 0x0c000, + CFG_FLASH_BASE + 0xe0000 - 1, + &flash_info[0]); +#else + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) + { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf("AMD: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) + { + case (AMD_ID_LV160B & FLASH_TYPEMASK): + printf("2x Amd29F160BB (16Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto Done; + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) + { + if ((i % 5) == 0) + { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: + ; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1, chip2; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status(); + icache_disable(); + iflag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) + { + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + if (info->protect[sect] == 0) + { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = chip2 = 0; + + do + { + result = *addr; + + /* check timeout */ + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) + chip1 = ERR; + + if (!chip2 && (result >> 16) & BIT_ERASE_DONE) + chip2 = READY; + + if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) + chip2 = ERR; + + } while (!chip1 || !chip2); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR || chip2 == ERR) + { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) + { + rc = ERR_TIMOUT; + goto outahere; + } + + printf("ok.\n"); + } + else /* it was protected */ + { + printf("protected!\n"); + } + } + + if (ctrlc()) + printf("User Interrupt!\n"); + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked(10000); + + if (iflag) + enable_interrupts(); + + if (cflag) + icache_enable(); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1, chip2; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status(); + icache_disable(); + iflag = disable_interrupts(); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; + *addr = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + /* wait until flash is ready */ + chip1 = chip2 = 0; + do + { + result = *addr; + + /* check timeout */ + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) + { + result = *addr; + + if ((result & 0x80) == (data & 0x80)) + chip1 = READY; + else + chip1 = ERR; + } + + if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) + chip2 = READY; + + if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) + { + result = *addr; + + if ((result & (0x80 << 16)) == (data & (0x80 << 16))) + chip2 = READY; + else + chip2 = ERR; + } + + } while (!chip1 || !chip2); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || chip2 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts(); + + if (cflag) + icache_enable(); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 24); + } + for (; i<4 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = *((vu_long*)src); + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + src += 4; + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + return write_word(info, wp, data); +} diff --git a/board/shannon/inferno.header b/board/shannon/inferno.header new file mode 100644 index 0000000..28ee85a Binary files /dev/null and b/board/shannon/inferno.header differ diff --git a/board/shannon/lowlevel_init.S b/board/shannon/lowlevel_init.S new file mode 100644 index 0000000..0655c42 --- /dev/null +++ b/board/shannon/lowlevel_init.S @@ -0,0 +1,92 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +MEM_BASE: .long 0xa0000000 +MEM_START: .long 0xc0000000 + +#define MDCNFG 0x00 +#define MDCAS0 0x04 +#define MDCAS1 0x08 +#define MDCAS2 0x0c +#define MSC0 0x10 +#define MSC1 0x14 +#define MECR 0x18 + +mdcas0: .long 0xc71c703f @ cccccccf +mdcas1: .long 0xffc71c71 @ fffffffc +mdcas2: .long 0xffffffff @ ffffffff +mdcnfg: .long 0x0334b21f @ 9326991f +msc0: .long 0xfff84458 @ 42304230 +msc1: .long 0xffffffff @ 20182018 +mecr: .long 0x7fff7fff @ 01000000 + +/* setting up the memory */ + +.globl lowlevel_init +lowlevel_init: + ldr r0, MEM_BASE + + /* Setup the flash memory */ + ldr r1, msc0 + str r1, [r0, #MSC0] + + /* Set up the DRAM */ + + /* MDCAS0 */ + ldr r1, mdcas0 + str r1, [r0, #MDCAS0] + + /* MDCAS1 */ + ldr r1, mdcas1 + str r1, [r0, #MDCAS1] + + /* MDCAS2 */ + ldr r1, mdcas2 + str r1, [r0, #MDCAS2] + + /* MDCNFG */ + ldr r1, mdcnfg + str r1, [r0, #MDCNFG] + + /* Set up PCMCIA space */ + ldr r1, mecr + str r1, [r0, #MECR] + + /* Load something to activate bank */ + ldr r1, MEM_START + +.rept 8 + ldr r0, [r1] +.endr + + /* everything is fine now */ + mov pc, lr diff --git a/board/shannon/shannon.c b/board/shannon/shannon.c new file mode 100644 index 0000000..0d9f146 --- /dev/null +++ b/board/shannon/shannon.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* but if we use InfernoLoader, we must do some inits here */ + +#ifdef CONFIG_INFERNO + { + unsigned long temp; + __asm__ __volatile__(/* disable MMU, enable icache */ + "mrc p15, 0, %0, c1, c0\n" + "bic %0, %0, #0x00002000\n" + "bic %0, %0, #0x0000000f\n" + "orr %0, %0, #0x00001000\n" + "orr %0, %0, #0x00000002\n" + "mcr p15, 0, %0, c1, c0\n" + /* flush caches */ + "mov %0, #0\n" + "mcr p15, 0, %0, c7, c7, 0\n" + "mcr p15, 0, %0, c8, c7, 0\n" + : "=r" (temp) + : + : "memory"); + /* setup PCMCIA timing */ + temp = 0xa0000018; + *(unsigned long *)temp = 0x00060006; + + } +#endif /* CONFIG_INFERNO */ + + /* arch number for shannon */ + gd->bd->bi_arch_number = MACH_TYPE_SHANNON; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xc0000100; + + return 0; +} + +int dram_init (void) +{ +#if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \ + defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4) + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; +#endif + +#ifdef PHYS_SDRAM_1 + bd->bi_dram[0].start = PHYS_SDRAM_1; + bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +#endif + +#ifdef PHYS_SDRAM_2 + bd->bi_dram[1].start = PHYS_SDRAM_2; + bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif + +#ifdef PHYS_SDRAM_3 + bd->bi_dram[2].start = PHYS_SDRAM_3; + bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; +#endif + +#ifdef PHYS_SDRAM_4 + bd->bi_dram[3].start = PHYS_SDRAM_4; + bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; +#endif + + return (0); +} diff --git a/board/shannon/u-boot.lds b/board/shannon/u-boot.lds new file mode 100644 index 0000000..258bece --- /dev/null +++ b/board/shannon/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/siemens/CCM/Makefile b/board/siemens/CCM/Makefile new file mode 100644 index 0000000..ee2fc53 --- /dev/null +++ b/board/siemens/CCM/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \ + ../../tqm8xx/load_sernum_ethaddr.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c new file mode 100644 index 0000000..5a32e45 --- /dev/null +++ b/board/siemens/CCM/ccm.c @@ -0,0 +1,408 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); +void can_driver_enable (void); +void can_driver_disable (void); + +int fpga_init(void); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, + 0x1FF5FC47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Always return 1 (no second DRAM bank since based on TQM8xxL module) + */ + +int checkboard (void) +{ + unsigned char *s; + unsigned char buf[64]; + + s = (getenv_r ("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL; + + puts ("Board: Siemens CCM"); + + if (s) { + puts (" ("); + + for (; *s; ++s) { + if (*s == ' ') + break; + putc (*s); + } + putc (')'); + } + + putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * If Power-On-Reset switch off the Red and Green LED: At reset, the + * data direction registers are cleared and must therefore be restored. + */ +#define RSR_CSRS 0x08000000 + +int power_on_reset(void) +{ + /* Test Reset Status Register */ + return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; +} + +#define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */ +#define PB_LED_RED 0x20000 /* red LED is on PB.14 */ +#define PB_LEDS (PB_LED_GREEN | PB_LED_RED); + +static void init_leds (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + immap->im_cpm.cp_pbpar &= ~PB_LEDS; + immap->im_cpm.cp_pbodr &= ~PB_LEDS; + immap->im_cpm.cp_pbdir |= PB_LEDS; + /* Check stop reset status */ + if (power_on_reset()) { + immap->im_cpm.cp_pbdat &= ~PB_LEDS; + } +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size8, size9; + long int size = 0; + unsigned long reg; + + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ + udelay(1); + memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ + udelay(1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size = size9; +/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */ + } else { /* back to 8 columns */ + size = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay(500); +/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */ + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type + * For types > 128 MBit leave it at the current (fast) rate + */ + if (size < 0x02000000) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay(1000); + } + + /* + * Final mapping + */ + + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + + can_driver_enable (); + init_leds (); + + udelay(10000); + + return (size); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Warning - both the PUMA load mode and the CAN driver use UPM B, + * so make sure only one of both is active. + */ +void can_driver_enable (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* Initialize MBMR */ + memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ + + /* Initialize UPMB for CAN: single read */ + memctl->memc_mdr = 0xFFFFC004; + memctl->memc_mcr = 0x0100 | UPMB; + + memctl->memc_mdr = 0x0FFFD004; + memctl->memc_mcr = 0x0101 | UPMB; + + memctl->memc_mdr = 0x0FFFC000; + memctl->memc_mcr = 0x0102 | UPMB; + + memctl->memc_mdr = 0x3FFFC004; + memctl->memc_mcr = 0x0103 | UPMB; + + memctl->memc_mdr = 0xFFFFDC05; + memctl->memc_mcr = 0x0104 | UPMB; + + /* Initialize UPMB for CAN: single write */ + memctl->memc_mdr = 0xFFFCC004; + memctl->memc_mcr = 0x0118 | UPMB; + + memctl->memc_mdr = 0xCFFCD004; + memctl->memc_mcr = 0x0119 | UPMB; + + memctl->memc_mdr = 0x0FFCC000; + memctl->memc_mcr = 0x011A | UPMB; + + memctl->memc_mdr = 0x7FFCC004; + memctl->memc_mcr = 0x011B | UPMB; + + memctl->memc_mdr = 0xFFFDCC05; + memctl->memc_mcr = 0x011C | UPMB; + + /* Initialize OR3 / BR3 for CAN Bus Controller */ + memctl->memc_or3 = CFG_OR3_CAN; + memctl->memc_br3 = CFG_BR3_CAN; +} + +void can_driver_disable (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* Reset OR3 / BR3 to disable CAN Bus Controller */ + memctl->memc_br3 = 0; + memctl->memc_or3 = 0; + + memctl->memc_mbmr = 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) + +#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN) + +void reset_phy(void) +{ + immap_t *immr = (immap_t *)CFG_IMMR; + ulong value; + + /* Configure all needed port pins for GPIO */ +#ifdef CFG_ETH_MDDIS_VALUE + immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; +#else + immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* Set low */ +#endif + immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* GPIO */ + immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* active output */ + immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET; /* output */ + + immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ + + value = immr->im_cpm.cp_pbdat; + + /* Assert Powerdown and Reset signals */ + value |= CFG_PB_ETH_POWERDOWN; + + /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ +#ifdef CFG_ETH_CFG1_VALUE + value |= CFG_PB_ETH_CFG1; +#else + value &= ~(CFG_PB_ETH_CFG1); +#endif +#ifdef CFG_ETH_CFG2_VALUE + value |= CFG_PB_ETH_CFG2; +#else + value &= ~(CFG_PB_ETH_CFG2); +#endif +#ifdef CFG_ETH_CFG3_VALUE + value |= CFG_PB_ETH_CFG3; +#else + value &= ~(CFG_PB_ETH_CFG3); +#endif + + /* Drive output signals to initial state */ + immr->im_cpm.cp_pbdat = value; + immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; + udelay (10000); + + /* De-assert Ethernet Powerdown */ + immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + udelay (10000); + + /* de-assert RESET signal of PHY */ + immr->im_ioport.iop_padat |= CFG_PA_ETH_RESET; + udelay (1000); +} + + +int misc_init_r (void) +{ + fpga_init(); + return (0); +} +/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/CCM/config.mk b/board/siemens/CCM/config.mk new file mode 100644 index 0000000..9c72c79 --- /dev/null +++ b/board/siemens/CCM/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8xxL boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c new file mode 100644 index 0000000..9c32785 --- /dev/null +++ b/board/siemens/CCM/flash.c @@ -0,0 +1,553 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + if (size_b1) { + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c new file mode 100644 index 0000000..11b97bc --- /dev/null +++ b/board/siemens/CCM/fpga_ccm.c @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2002 + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include + +#include "../common/fpga.h" + +fpga_t fpga_list[] = { + { "PUMA" , PUMA_CONF_BASE , + CFG_PC_PUMA_INIT , CFG_PC_PUMA_PROG , CFG_PC_PUMA_DONE } +}; +int fpga_count = sizeof(fpga_list) / sizeof(fpga_t); + +void can_driver_enable (void); +void can_driver_disable (void); + +#define _NOT_USED_ 0xFFFFFFFF + +/* + * PUMA access using UPM B + */ +const uint puma_table[] = +{ + /* + * Single Read. (Offset 0 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, + /* + * Precharge and MRS + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + + +ulong fpga_control (fpga_t* fpga, int cmd) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + + switch (cmd) { + case FPGA_INIT_IS_HIGH: + immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */ + return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0; + + case FPGA_INIT_SET_LOW: + immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ + immr->im_ioport.iop_pcdat &= ~fpga->init_mask; + break; + + case FPGA_INIT_SET_HIGH: + immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ + immr->im_ioport.iop_pcdat |= fpga->init_mask; + break; + + case FPGA_PROG_SET_LOW: + immr->im_ioport.iop_pcdat &= ~fpga->prog_mask; + break; + + case FPGA_PROG_SET_HIGH: + immr->im_ioport.iop_pcdat |= fpga->prog_mask; + break; + + case FPGA_DONE_IS_HIGH: + return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0; + + case FPGA_READ_MODE: + /* disable FPGA in memory controller */ + memctl->memc_br4 = 0; + memctl->memc_or4 = PUMA_CONF_OR_READ; + memctl->memc_br4 = PUMA_CONF_BR_READ; + + /* (re-) enable CAN drivers */ + can_driver_enable (); + + break; + + case FPGA_LOAD_MODE: + /* disable FPGA in memory controller */ + memctl->memc_br4 = 0; + /* + * We must disable the CAN drivers first because + * they use UPM B, too. + */ + can_driver_disable (); + /* + * Configure UPMB for FPGA + */ + upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint)); + memctl->memc_or4 = PUMA_CONF_OR_LOAD; + memctl->memc_br4 = PUMA_CONF_BR_LOAD; + break; + + case FPGA_GET_ID: + return *(volatile ulong *)fpga->conf_base; + + case FPGA_INIT_PORTS: + immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */ + immr->im_ioport.iop_pcso &= ~fpga->init_mask; + immr->im_ioport.iop_pcdir &= ~fpga->init_mask; + + immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */ + immr->im_ioport.iop_pcso &= ~fpga->prog_mask; + immr->im_ioport.iop_pcdir |= fpga->prog_mask; + + immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */ + immr->im_ioport.iop_pcso &= ~fpga->done_mask; + immr->im_ioport.iop_pcdir &= ~fpga->done_mask; + + break; + + } + return 0; +} diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds new file mode 100644 index 0000000..cdf550f --- /dev/null +++ b/board/siemens/CCM/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug new file mode 100644 index 0000000..3b50272 --- /dev/null +++ b/board/siemens/CCM/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) +/* + . = env_offset; + common/environment.o(.text) +*/ + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c new file mode 100644 index 0000000..e498937 --- /dev/null +++ b/board/siemens/IAD210/IAD210.c @@ -0,0 +1,286 @@ +/* + * (C) Copyright 2001 + * Paul Geerinckx + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "atm.h" +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +/* used PLD registers */ +# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0) +# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10) +# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11) +# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12) +# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13) + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */ + _NOT_USED_, + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0xFFFAF834, 0xFFE5B435, /* last */ + _NOT_USED_, + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00, + 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, + 0xF1AAF804, 0xFFA5F447, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84, + 0xFFAFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * MRS sequence (Offset 38 in UPMA RAM) + */ + 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */ + _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0xFFAFFC04, 0xFFAFFC05, /* last */ + _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile iop8xx_t *iop = &immap->im_ioport; + volatile fec_t *fecp = &immap->im_cpm.cp_fec; + long int size; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + + memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ + udelay (1); + + memctl->memc_mcr = 0x80004105; /* SDRAM precharge */ + udelay (1); + memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */ + udelay (1); + memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + */ + size = dram_size (CFG_MAMR, (long *) SDRAM_BASE_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + + memctl->memc_mamr = CFG_MAMR; + udelay (1000); + + /* + * Final mapping + */ + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM; + memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V); + + udelay (10000); + + /* prepare pin multiplexing for fast ethernet */ + + atmLoad (); + fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */ + iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */ + + + return (size); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size (base, maxsize)); +} + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + return (0); +} + +void board_serial_init (void) +{ + ; /* nothing to do here */ +} + +void board_ether_init (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *iop = &immap->im_ioport; + volatile fec_t *fecp = &immap->im_cpm.cp_fec; + + atmLoad (); + fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */ + iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */ +} + +int board_early_init_f (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile iop8xx_t *iop = &immap->im_ioport; + + /* configure the LED timing output pins - port A pin 4 */ + iop->iop_papar = 0x0800; + iop->iop_padir = 0x0800; + + /* start timer 2 for the 4hz LED blink rate */ + timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */ + timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */ + timers->cpmt_tgcr = 0x00000810; /* run timer 2 */ + + /* chip select for PLD access */ + memctl->memc_br6 = 0x10000401; + memctl->memc_or6 = 0xFC000908; + + /* PLD initial values ( set LEDs, remove reset on LXT) */ + + *PLD_GCR1_REG = 0x06; + *PLD_EXT_RES = 0xC0; + *PLD_EXT_FETH = 0x40; + *PLD_EXT_LED = 0xFF; + *PLD_EXT_X21 = 0x04; + return 0; +} + +void board_get_enetaddr (uchar * addr) +{ + int i; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cpm = &immap->im_cpm; + unsigned int rccrtmp; + + char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 }; + + for (i = 0; i < 6; i++) + addr[i] = default_mac_addr[i]; + + printf ("There is an error in the i2c driver .. /n"); + printf ("You need to fix it first....../n"); + + rccrtmp = cpm->cp_rccr; + cpm->cp_rccr |= 0x0020; + + i2c_reg_read (0xa0, 0); + printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n", + i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0), + i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0), + i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0)); + + cpm->cp_rccr = rccrtmp; +} diff --git a/board/siemens/IAD210/Makefile b/board/siemens/IAD210/Makefile new file mode 100644 index 0000000..87a6893 --- /dev/null +++ b/board/siemens/IAD210/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o atm.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c new file mode 100644 index 0000000..c77e359 --- /dev/null +++ b/board/siemens/IAD210/atm.c @@ -0,0 +1,653 @@ + +#include +#include +#include + +#include "atm.h" +#include + +#define SYNC __asm__("sync") +#define ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1))) + +#define FALSE 1 +#define TRUE 0 +#define OK 0 +#define ERROR -1 + +struct atm_connection_t g_conn[NUM_CONNECTIONS] = +{ + { NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */ +}; + +struct atm_driver_t g_atm = +{ + FALSE, /* loaded */ + FALSE, /* started */ + NULL, /* csram */ + 0, /* csram_size */ + NULL, /* am_top */ + NULL, /* ap_top */ + NULL, /* int_reload_ptr */ + NULL, /* int_serv_ptr */ + NULL, /* rbd_base_ptr */ + NULL, /* tbd_base_ptr */ + 0 /* linerate */ +}; + +char csram[1024]; /* more than enough for doing nothing*/ + +int atmLoad(void); +void atmUnload(void); +int atmMemInit(void); +void atmIntInit(void); +void atmApcInit(void); +void atmAmtInit(void); +void atmCpmInit(void); +void atmUtpInit(void); + +/***************************************************************************** + * + * FUNCTION NAME: atmLoad + * + * DESCRIPTION: Basic ATM initialization. + * + * PARAMETERS: none + * + * RETURNS: OK or ERROR + * + ****************************************************************************/ +int atmLoad() +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; + volatile iop8xx_t *iop = &immap->im_ioport; + + timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */ + immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */ + iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */ + + if ( atmMemInit() != OK ) return ERROR; + + atmIntInit(); + atmApcInit(); + atmAmtInit(); + atmCpmInit(); + atmUtpInit(); + + g_atm.loaded = TRUE; + + return OK; +} + +/***************************************************************************** + * + * FUNCTION NAME: atmUnload + * + * DESCRIPTION: Disables ATM and UTOPIA. + * + * PARAMETERS: none + * + * RETURNS: void + * + ****************************************************************************/ +void atmUnload() +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; + volatile iop8xx_t *iop = &immap->im_ioport; + + timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */ + immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */ + iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */ + g_atm.loaded = FALSE; +} + +/***************************************************************************** + * + * FUNCTION NAME: atmMemInit + * + * DESCRIPTION: + * + * The ATM driver uses the following resources: + * + * A. Memory in DPRAM to hold + * + * 1/ CT = Connection Table ( RCT & TCT ) + * 2/ TCTE = Transmit Connection Table Extension + * 3/ MPHYPT = Multi-PHY Pointing Table + * 4/ APCP = APC Parameter Table + * 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 ) + * 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR ) + * 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR ) + * 8/ TQ = Transmit Queue + * 9/ AM = Address Matching Table + * 10/ AP = Address Pointing Table + * + * B. Memory in cache safe RAM to hold + * + * 1/ INT = Interrupt Queue + * 2/ RBD = Receive Buffer Descriptors + * 3/ TBD = Transmit Buffer Descriptors + * + * This function + * 1. clears the ATM DPRAM area, + * 2. Allocates and clears cache safe memory, + * 3. Initializes 'g_conn'. + * + * PARAMETERS: none + * + * RETURNS: OK or ERROR + * + ****************************************************************************/ +int atmMemInit() +{ + int i; + unsigned immr = CFG_IMMR; + int total_num_rbd = 0; + int total_num_tbd = 0; + + memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE); + + g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY; + + for ( i = 0; i < NUM_CONNECTIONS; ++i ) { + total_num_rbd += g_conn[i].num_rbd; + total_num_tbd += g_conn[i].num_tbd; + } + + g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4; + + g_atm.csram = &csram[0]; + memset(&(g_atm.csram), 0x00, g_atm.csram_size); + + g_atm.int_reload_ptr = (uint32 *)ALIGN(g_atm.csram, 4); + g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES); + g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd); + + g_conn[0].rbd_ptr = g_atm.rbd_base_ptr; + g_conn[0].tbd_ptr = g_atm.tbd_base_ptr; + g_conn[0].ct_ptr = CT_PTR(immr); + g_conn[0].tcte_ptr = TCTE_PTR(immr); + + return OK; +} + +/***************************************************************************** + * + * FUNCTION NAME: atmIntInit + * + * DESCRIPTION: + * + * Initialization of the MPC860 ESAR Interrupt Queue. + * This function + * - clears all entries in the INT, + * - sets the WRAP bit of the last INT entry, + * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure + * to the first INT entry. + * + * PARAMETERS: none + * + * RETURNS: void + * + * REMARKS: + * + * - The INT resides in external cache safe memory. + * - The base address of the INT is stored in g_atm.int_reload_ptr. + * - The number of entries in the INT is given by NUM_INT_ENTRIES. + * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit(). + * + ****************************************************************************/ +void atmIntInit() +{ + int i; + for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0; + g_atm.int_reload_ptr[i] = INT_WRAP; + g_atm.int_serv_ptr = g_atm.int_reload_ptr; +} + +/***************************************************************************** + * + * FUNCTION NAME: atmApcInit + * + * DESCRIPTION: + * + * This function initializes the following ATM Pace Controller related + * data structures: + * + * - 1 MPHY Pointing Table (contains only one entry) + * - 3 APC Parameter Tables (one PHY with 3 priorities) + * - 3 APC Tables (one table for each priority) + * - 1 Transmit Queue (one transmit queue per PHY) + * + * PARAMETERS: none + * + * RETURNS: void + * + ****************************************************************************/ +void atmApcInit() +{ + int i; + /* unsigned immr = CFG_IMMR; */ + uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR); + struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR); + uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR); + uint16 * tq_ptr = TQ_PTR(CFG_IMMR); + /***************************************************/ + /* Initialize MPHY Pointing Table (only one entry) */ + /***************************************************/ + *mphypt_ptr = APCP_BASE; + + /********************************************/ + /* Initialize APC parameters for priority 1 */ + /********************************************/ + apcp_ptr->apct_base1 = APCT_PRIO_1_BASE; + apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2; + apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE; + apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE; + apcp_ptr->etqbase = TQ_BASE; + apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2; + apcp_ptr->etqaptr = TQ_BASE; + apcp_ptr->etqtptr = TQ_BASE; + apcp_ptr->apc_mi = 8; + apcp_ptr->ncits = 0x0100; /* NCITS = 1 */ + apcp_ptr->apcnt = 0; + apcp_ptr->reserved1 = 0; + apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */ + apcp_ptr->ptp_counter = 0; + apcp_ptr->ptp_txch = 0; + apcp_ptr->reserved2 = 0; + + + /***************************************************/ + /* Initialize APC Tables with empty slots (0xFFFF) */ + /***************************************************/ + for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF; + + /************************/ + /* Clear Transmit Queue */ + /************************/ + for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0; +} + +/***************************************************************************** + * + * FUNCTION NAME: atmAmtInit + * + * DESCRIPTION: + * + * This function clears the first entry in the Address Matching Table and + * lets the first entry in the Address Pointing table point to the first + * entry in the TCT table (i.e. the raw cell channel). + * + * PARAMETERS: none + * + * RETURNS: void + * + * REMARKS: + * + * The values for the AMBASE, AMEND and APBASE registers in SAR parameter + * RAM are initialized by atmCpmInit(). + * + ****************************************************************************/ +void atmAmtInit() +{ + unsigned immr = CFG_IMMR; + + g_atm.am_top = AM_PTR(immr); + g_atm.ap_top = AP_PTR(immr); + + *(g_atm.ap_top--) = CT_BASE; + *(g_atm.am_top--) = 0; +} + +/***************************************************************************** + * + * FUNCTION NAME: atmCpmInit + * + * DESCRIPTION: + * + * This function initializes the Utopia Interface Parameter RAM Map + * (SCC4, ATM Protocol) of the Communication Processor Modudule. + * + * PARAMETERS: none + * + * RETURNS: void + * + ****************************************************************************/ +void atmCpmInit() +{ + unsigned immr = CFG_IMMR; + + memset((char *)immr + 0x3F00, 0x00, 0xC0); + + /*-----------------------------------------------------------------*/ + /* RBDBASE - Receive buffer descriptors base address */ + /* The RBDs reside in cache safe external memory. */ + /*-----------------------------------------------------------------*/ + *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr; + + /*-----------------------------------------------------------------*/ + /* SRFCR - SAR receive function code */ + /* 0-2 rsvd = 000 */ + /* 3-4 BO = 11 Byte ordering (big endian). */ + /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ + /* when the SDMA channel accesses memory. */ + /*-----------------------------------------------------------------*/ + *SRFCR(immr) = 0x18; + + /*-----------------------------------------------------------------*/ + /* SRSTATE - SAR receive status */ + /* 0 EXT = 0 Extended mode off. */ + /* 1 ACP = 0 Valid only if EXT = 1. */ + /* 2 EC = 0 Standard 53-byte ATM cell. */ + /* 3 SNC = 0 In sync. Must be set to 0 during initialization. */ + /* 4 ESAR = 1 Enhanced SAR functionality enabled. */ + /* 5 MCF = 1 Management Cell Filter active. */ + /* 6 SER = 0 UTOPIA mode. */ + /* 7 MPY = 1 Multiple PHY mode. */ + /*-----------------------------------------------------------------*/ + *SRSTATE(immr) = 0x0D; + + /*-----------------------------------------------------------------*/ + /* MRBLR - Maximum receive buffer length register. */ + /* Must be cleared for ATM operation (see also SMRBLR). */ + /*-----------------------------------------------------------------*/ + *MRBLR(immr) = 0; + + /*-----------------------------------------------------------------*/ + /* RSTATE - SCC internal receive state parameters */ + /* The first byte must be initialized with the value of SRFCR. */ + /*-----------------------------------------------------------------*/ + *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24; + + /*-----------------------------------------------------------------*/ + /* STFCR - SAR transmit function code */ + /* 0-2 rsvd = 000 */ + /* 3-4 BO = 11 Byte ordering (big endian). */ + /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ + /* when the SDMA channel accesses memory. */ + /*-----------------------------------------------------------------*/ + *STFCR(immr) = 0x18; + + /*-----------------------------------------------------------------*/ + /* SRSTATE - SAR transmit status */ + /* 0 EXT = 0 : Extended mode off */ + /* 1 rsvd = 0 : */ + /* 2 EC = 0 : Standard 53-byte ATM cell */ + /* 3 rsvd = 0 : */ + /* 4 ESAR = 1 : Enhanced SAR functionality enabled */ + /* 5 rsvd = 0 : */ + /* 6 SER = 0 : UTOPIA mode */ + /* 7 MPY = 1 : Multiple PHY mode */ + /*-----------------------------------------------------------------*/ + *STSTATE(immr) = 0x09; + + /*-----------------------------------------------------------------*/ + /* TBDBASE - Transmit buffer descriptors base address */ + /* The TBDs reside in cache safe external memory. */ + /*-----------------------------------------------------------------*/ + *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr; + + /*-----------------------------------------------------------------*/ + /* TSTATE - SCC internal transmit state parameters */ + /* The first byte must be initialized with the value of STFCR. */ + /*-----------------------------------------------------------------*/ + *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24; + + /*-----------------------------------------------------------------*/ + /* CTBASE - Connection table base address */ + /* Offset from the beginning of DPRAM (64-byte aligned). */ + /*-----------------------------------------------------------------*/ + *CTBASE(immr) = CT_BASE; + + /*-----------------------------------------------------------------*/ + /* INTBASE - Interrupt queue base pointer. */ + /* The interrupt queue resides in cache safe external memory. */ + /*-----------------------------------------------------------------*/ + *INTBASE(immr) = (uint32)g_atm.int_reload_ptr; + + /*-----------------------------------------------------------------*/ + /* INTPTR - Pointer into interrupt queue. */ + /* Initialize to INTBASE. */ + /*-----------------------------------------------------------------*/ + *INTPTR(immr) = *INTBASE(immr); + + /*-----------------------------------------------------------------*/ + /* C_MASK - Constant mask for CRC32 */ + /* Must be initialized to 0xDEBB20E3. */ + /*-----------------------------------------------------------------*/ + *C_MASK(immr) = 0xDEBB20E3; + + /*-----------------------------------------------------------------*/ + /* INT_ICNT - Interrupt threshold value */ + /*-----------------------------------------------------------------*/ + *INT_ICNT(immr) = 1; + + /*-----------------------------------------------------------------*/ + /* INT_CNT - Interrupt counter */ + /* Initalize to INT_ICNT. Decremented for each interrupt entry */ + /* reported in the interrupt queue. On zero an interrupt is */ + /* signaled to the host by setting the GINT bit in the event */ + /* register. The counter is reinitialized with INT_ICNT. */ + /*-----------------------------------------------------------------*/ + *INT_CNT(immr) = *INT_ICNT(immr); + + /*-----------------------------------------------------------------*/ + /* SMRBLR - SAR maximum receive buffer length register. */ + /* Must be a multiple of 48 bytes. Common for all ATM connections. */ + /*-----------------------------------------------------------------*/ + *SMRBLR(immr) = SAR_RXB_SIZE; + + /*-----------------------------------------------------------------*/ + /* APCST - APC status register. */ + /* 0 rsvd 0 */ + /* 1-2 CSER 11 Initialize with the same value as NSER. */ + /* 3-4 NSER 11 Next serial or UTOPIA channel. */ + /* 5-7 rsvd 000 */ + /* 8-10 rsvd 000 */ + /* 11 rsvd 0 */ + /* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */ + /* 13 DIS 0 APC disable. Must be initiazed to 0. */ + /* 14 PL2 0 Not used. */ + /* 15 MPY 1 Multiple PHY mode on. */ + /*-----------------------------------------------------------------*/ + *APCST(immr) = 0x7809; + + /*-----------------------------------------------------------------*/ + /* APCPTR - Pointer to the APC parameter table */ + /* In MPHY master mode this parameter points to the MPHY pointing */ + /* table. 2-byte aligned. */ + /*-----------------------------------------------------------------*/ + *APCPTR(immr) = MPHYPT_BASE; + + /*-----------------------------------------------------------------*/ + /* HMASK - Header mask */ + /* Each incoming cell is masked with HMASK before being compared */ + /* to the entries in the address matching table. */ + /*-----------------------------------------------------------------*/ + *HMASK(immr) = AM_HMASK; + + /*-----------------------------------------------------------------*/ + /* AMBASE - Address matching table base address */ + /*-----------------------------------------------------------------*/ + *AMBASE(immr) = AM_BASE; + + /*-----------------------------------------------------------------*/ + /* AMEND - Address matching table end address */ + /*-----------------------------------------------------------------*/ + *AMEND(immr) = AM_BASE; + + /*-----------------------------------------------------------------*/ + /* APBASE - Address pointing table base address */ + /*-----------------------------------------------------------------*/ + *APBASE(immr) = AP_BASE; + + /*-----------------------------------------------------------------*/ + /* MPHYST - MPHY status register */ + /* 0-1 rsvd 00 */ + /* 2-6 NMPHY 00000 1 PHY */ + /* 7-9 rsvd 000 */ + /* 10-14 CMPHY 00000 Initialize with same value as NMPHY */ + /*-----------------------------------------------------------------*/ + *MPHYST(immr) = 0x0000; + + /*-----------------------------------------------------------------*/ + /* TCTEBASE - Transmit connection table extension base address */ + /* Offset from the beginning of DPRAM (32-byte aligned). */ + /*-----------------------------------------------------------------*/ + *TCTEBASE(immr) = TCTE_BASE; + + /*-----------------------------------------------------------------*/ + /* Clear not used registers. */ + /*-----------------------------------------------------------------*/ +} + +/***************************************************************************** + * + * FUNCTION NAME: atmUtpInit + * + * DESCRIPTION: + * + * This function initializes the ATM interface for + * + * - UTOPIA mode + * - muxed bus + * - master operation + * - multi PHY (because of a bug in the MPC860P rev. E.0) + * - internal clock = SYSCLK / 2 + * + * EXTERNAL EFFECTS: + * + * After calling this function, the MPC860ESAR UTOPIA bus is + * active and uses the following ports/pins: + * + * Port Pin Signal Description + * ------ --- ------- ------------------------------------------- + * PB[15] R17 TxClav Transmit cell available input/output signal + * PC[15] D16 RxClav Receive cell available input/output signal + * PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal + * PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal + * PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal + * PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal + * PD[11] T16 RXENB Receive enable input/output signal + * PD[10] W18 TXENB Transmit enable input/output signal + * PD[9] V17 UTPCLK UTOPIA clock input/output signal + * PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal + * PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal + * PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal + * PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal + * PD[3] W16 SOC Start of cell input/output signal + * + * PARAMETERS: none + * + * RETURNS: void + * + * REMARK: + * + * The ATM parameters and data structures must be configured before + * initializing the UTOPIA port. The UTOPIA port activates immediately + * upon initialization, and if its associated data structures are not + * initialized, the CPM will lock up. + * + ****************************************************************************/ +void atmUtpInit() +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile iop8xx_t *iop = &immap->im_ioport; + volatile car8xx_t *car = &immap->im_clkrst; + volatile cpm8xx_t *cpm = &immap->im_cpm; + int flag; + + flag = disable_interrupts(); + + /*-----------------------------------------------------------------*/ + /* SCCR - System Clock Control Register */ + /* */ + /* The UTOPIA clock can be selected to be internal clock or */ + /* external clock (selected by the UTOPIA mode register). */ + /* In case of internal clock, the UTOPIA clock is derived from */ + /* the system frequency divided by two dividers. */ + /* Bits 27-31 of the SCCR register are defined to control the */ + /* UTOPIA clock. */ + /* */ + /* SCCR[27:29] DFUTP Division factor. Divide the system clock */ + /* by 2^DFUTP. */ + /* SCCR[30:31] DFAUTP Additional division factor. Divide the */ + /* system clock by the following value: */ + /* 00 = divide by 1 */ + /* 00 = divide by 3 */ + /* 10 = divide by 5 */ + /* 11 = divide by 7 */ + /* */ + /* Note that the UTOPIA clock must be programmed as to operate */ + /* within the range SYSCLK/10 .. 50Mhz. */ + /*-----------------------------------------------------------------*/ + car->car_sccr &= 0xFFFFFFE0; + car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */ + + /*-----------------------------------------------------------------*/ + /* RCCR - RISC Controller Configuration Register */ + /* */ + /* RCCR[8] DR1M IDMA Request 0 Mode */ + /* 0 = edge sensitive */ + /* 1 = level sensitive */ + /* RCCR[9] DR0M IDMA Request 0 Mode */ + /* 0 = edge sensitive */ + /* 1 = level sensitive */ + /* RCCR[10:11] DRQP IDMA Request Priority */ + /* 00 = IDMA req. have more prio. than SCCs */ + /* 01 = IDMA req. have less prio. then SCCs */ + /* 10 = IDMA requests have the lowest prio. */ + /* 11 = reserved */ + /* */ + /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */ + /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */ + /* higher priority. */ + /*-----------------------------------------------------------------*/ + cpm->cp_rccr &= 0xFF0F; + cpm->cp_rccr |= 0x00D0; + + /*-----------------------------------------------------------------*/ + /* Port B - TxClav Signal */ + /*-----------------------------------------------------------------*/ + cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */ + cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */ + + /*-----------------------------------------------------------------*/ + /* UTOPIA Mode Register */ + /* */ + /* - muxed bus (master operation only) */ + /* - multi PHY (because of a bug in the MPC860P rev.E.0) */ + /* - internal clock */ + /* - no loopback */ + /* - do no activate statistical counters */ + /*-----------------------------------------------------------------*/ + iop->utmode = 0x00000004; SYNC; + + /*-----------------------------------------------------------------*/ + /* Port D - UTOPIA Data and Control Signals */ + /* */ + /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */ + /* 11 RXENB UTOPIA receive enable input/output signal */ + /* 10 TXENB UTOPIA transmit enable input/output signal */ + /* 9 TUPCLK UTOPIA clock input/output signal */ + /* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */ + /* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */ + /* 3 SOC UTOPIA Start of cell input/output signal */ + /* 2 Reserved */ + /* 1 Enable UTOPIA mode */ + /* 0 Enable SAR */ + /*-----------------------------------------------------------------*/ + iop->iop_pdpar |= 0xDF7F; SYNC; + iop->iop_pddir &= 0x2080; SYNC; + + /*-----------------------------------------------------------------*/ + /* Port C - RxClav Signal */ + /*-----------------------------------------------------------------*/ + iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */ + iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */ + iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */ + + if (flag) + enable_interrupts(); +} diff --git a/board/siemens/IAD210/atm.h b/board/siemens/IAD210/atm.h new file mode 100644 index 0000000..71b0497 --- /dev/null +++ b/board/siemens/IAD210/atm.h @@ -0,0 +1,287 @@ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; +typedef volatile unsigned char vuint8; +typedef volatile unsigned short vuint16; +typedef volatile unsigned int vuint32; + + +#define DPRAM_ATM CFG_IMMR + 0x3000 + +#define ATM_DPRAM_BEGIN (DPRAM_ATM - CFG_IMMR - 0x2000) +#define NUM_CONNECTIONS 1 +#define SAR_RXB_SIZE 1584 +#define AM_HMASK 0x0FFFFFF0 + +#define NUM_CT_ENTRIES (NUM_CONNECTIONS) +#define NUM_TCTE_ENTRIES (NUM_CONNECTIONS) +#define NUM_AM_ENTRIES (NUM_CONNECTIONS+1) +#define NUM_AP_ENTRIES (NUM_CONNECTIONS+1) +#define NUM_MPHYPT_ENTRIES 1 +#define NUM_APCP_ENTRIES 1 +#define NUM_APCT_PRIO_1_ENTRIES 146 /* Determines minimum rate */ +#define NUM_TQ_ENTRIES 12 + +#define SIZE_OF_CT_ENTRY 64 +#define SIZE_OF_TCTE_ENTRY 32 +#define SIZE_OF_AM_ENTRY 4 +#define SIZE_OF_AP_ENTRY 2 +#define SIZE_OF_MPHYPT_ENTRY 2 +#define SIZE_OF_APCP_ENTRY 32 +#define SIZE_OF_APCT_ENTRY 2 +#define SIZE_OF_TQ_ENTRY 2 + +#define CT_BASE ((ATM_DPRAM_BEGIN + 63) & 0xFFC0) /*64 */ +#define TCTE_BASE (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32 */ +#define APCP_BASE (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY) /*32 */ +#define AM_BEGIN (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY) /*4 */ +#define AM_BASE (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY) +#define AP_BEGIN (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY) /*2 */ +#define AP_BASE (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY) +#define MPHYPT_BASE (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY) /*2 */ +#define APCT_PRIO_1_BASE (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY) /*2 */ +#define TQ_BASE (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY) /*2 */ +#define ATM_DPRAM_SIZE ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN) + +#define CT_PTR(base) ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE)) +#define TCTE_PTR(base) ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE)) +#define AM_PTR(base) ((uint32 *)((char *)(base) + 0x2000 + AM_BASE)) +#define AP_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + AP_BASE)) +#define MPHYPT_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE)) +#define APCP_PTR(base) ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE)) +#define APCT1_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE)) +#define APCT2_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE)) +#define APCT3_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE)) +#define TQ_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE)) + +/* SAR registers */ +#define RBDBASE(base) ((vuint32 *)(base + 0x3F00)) /* Base address of RxBD-List */ +#define SRFCR(base) ((vuint8 *)(base + 0x3F04)) /* DMA Receive function code */ +#define SRSTATE(base) ((vuint8 *)(base + 0x3F05)) /* DMA Receive status */ +#define MRBLR(base) ((vuint16 *)(base + 0x3F06)) /* Init to 0 for ATM */ +#define RSTATE(base) ((vuint32 *)(base + 0x3F08)) /* Do not write to */ +#define R_CNT(base) ((vuint16 *)(base + 0x3F10)) /* Do not write to */ +#define STFCR(base) ((vuint8 *)(base + 0x3F12)) /* DMA Transmit function code */ +#define STSTATE(base) ((vuint8 *)(base + 0x3F13)) /* DMA Transmit status */ +#define TBDBASE(base) ((vuint32 *)(base + 0x3F14)) /* Base address of TxBD-List */ +#define TSTATE(base) ((vuint32 *)(base + 0x3F18)) /* Do not write to */ +#define COMM_CH(base) ((vuint16 *)(base + 0x3F1C)) /* Command channel */ +#define STCHNUM(base) ((vuint16 *)(base + 0x3F1E)) /* Do not write to */ +#define T_CNT(base) ((vuint16 *)(base + 0x3F20)) /* Do not write to */ +#define CTBASE(base) ((vuint16 *)(base + 0x3F22)) /* Base address of Connection-table */ +#define ECTBASE(base) ((vuint32 *)(base + 0x3F24)) /* Valid only for external Conn.-table */ +#define INTBASE(base) ((vuint32 *)(base + 0x3F28)) /* Base address of Interrupt-table */ +#define INTPTR(base) ((vuint32 *)(base + 0x3F2C)) /* Pointer to Interrupt-queue */ +#define C_MASK(base) ((vuint32 *)(base + 0x3F30)) /* CRC-mask */ +#define SRCHNUM(base) ((vuint16 *)(base + 0x3F34)) /* Do not write to */ +#define INT_CNT(base) ((vuint16 *)(base + 0x3F36)) /* Interrupt-Counter */ +#define INT_ICNT(base) ((vuint16 *)(base + 0x3F38)) /* Interrupt threshold */ +#define TSTA(base) ((vuint16 *)(base + 0x3F3A)) /* Time-stamp-address */ +#define OLDLEN(base) ((vuint16 *)(base + 0x3F3C)) /* Do not write to */ +#define SMRBLR(base) ((vuint16 *)(base + 0x3F3E)) /* SAR max RXBuffer length */ +#define EHEAD(base) ((vuint32 *)(base + 0x3F40)) /* Valid for serial mode */ +#define EPAYLOAD(base) ((vuint32 *)(base + 0x3F44)) /* Valid for serial mode */ +#define TQBASE(base) ((vuint16 *)(base + 0x3F48)) /* Base address of Tx queue */ +#define TQEND(base) ((vuint16 *)(base + 0x3F4A)) /* End address of Tx queue */ +#define TQAPTR(base) ((vuint16 *)(base + 0x3F4C)) /* TQ APC pointer */ +#define TQTPTR(base) ((vuint16 *)(base + 0x3F4E)) /* TQ Tx pointer */ +#define APCST(base) ((vuint16 *)(base + 0x3F50)) /* APC status */ +#define APCPTR(base) ((vuint16 *)(base + 0x3F52)) /* APC parameter pointer */ +#define HMASK(base) ((vuint32 *)(base + 0x3F54)) /* Header mask */ +#define AMBASE(base) ((vuint16 *)(base + 0x3F58)) /* Address match table base */ +#define AMEND(base) ((vuint16 *)(base + 0x3F5A)) /* Address match table end */ +#define APBASE(base) ((vuint16 *)(base + 0x3F5C)) /* Address match parameter */ +#define FLBASE(base) ((vuint32 *)(base + 0x3F54)) /* First-level table base */ +#define SLBASE(base) ((vuint32 *)(base + 0x3F58)) /* Second-level table base */ +#define FLMASK(base) ((vuint16 *)(base + 0x3F5C)) /* First-level mask */ +#define ECSIZE(base) ((vuint16 *)(base + 0x3F5E)) /* Valid for extended mode */ +#define APCT_REAL(base) ((vuint32 *)(base + 0x3F60)) /* APC 32 bit counter */ +#define R_PTR(base) ((vuint32 *)(base + 0x3F64)) /* Do not write to */ +#define RTEMP(base) ((vuint32 *)(base + 0x3F68)) /* Do not write to */ +#define T_PTR(base) ((vuint32 *)(base + 0x3F6C)) /* Do not write to */ +#define TTEMP(base) ((vuint32 *)(base + 0x3F70)) /* Do not write to */ + +/* ESAR registers */ +#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80)) /* Perf.Mon.Timestamp */ +#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84)) /* Perf.Mon.Template */ +#define PMPTR(base) ((vuint16 *)(base + 0x3F88)) /* Perf.Mon.Table */ +#define PMCHANNEL(base) ((vuint16 *)(base + 0x3F8A)) /* Perf.Mon.Channel */ +#define MPHYST(base) ((vuint16 *)(base + 0x3F90)) /* Multi-PHY Status */ +#define TCTEBASE(base) ((vuint16 *)(base + 0x3F92)) /* Internal TCT Extension Base */ +#define ETCTEBASE(base) ((vuint32 *)(base + 0x3F94)) /* External TCT Extension Base */ +#define COMM_CH2(base) ((vuint32 *)(base + 0x3F98)) /* 2nd command channel word */ +#define STATBASE(base) ((vuint16 *)(base + 0x3F9C)) /* Statistics table pointer */ + +/* UTOPIA Mode Register */ +#define UTMODE(base) (CAST(vuint32 *)(base + 0x0978)) + +/* SAR commands */ +#define TRANSMIT_CHANNEL_ACTIVATE_CMD 0x0FC1 +#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1 +#define STOP_TRANSMIT_CMD 0x2FC1 +#define RESTART_TRANSMIT_CMD 0x3FC1 +#define STOP_RECEIVE_CMD 0x4FC1 +#define RESTART_RECEIVE_CMD 0x5FC1 +#define APC_BYPASS_CMD 0x6FC1 +#define MEM_WRITE_CMD 0x7FC1 +#define CPCR_FLG 0x0001 + +/* INT flags */ +#define INT_VALID 0x80000000 +#define INT_WRAP 0x40000000 +#define INT_APCO 0x00800000 +#define INT_TQF 0x00200000 +#define INT_RXF 0x00080000 +#define INT_BSY 0x00040000 +#define INT_TXB 0x00020000 +#define INT_RXB 0x00010000 + +#define NUM_INT_ENTRIES 80 +#define SIZE_OF_INT_ENTRY 4 + +struct apc_params_t { + vuint16 apct_base1; /* APC Table - First Priority Base pointer */ + vuint16 apct_end1; /* First APC Table - Length */ + vuint16 apct_ptr1; /* First APC Table Pointer */ + vuint16 apct_sptr1; /* APC Table First Priority Service pointer */ + vuint16 etqbase; /* Enhanced Transmit Queue Base pointer */ + vuint16 etqend; /* Enhanced Transmit Queue End pointer */ + vuint16 etqaptr; /* Enhanced Transmit Queue APC pointer */ + vuint16 etqtptr; /* Enhanced Transmit Queue Transmitter pointer */ + vuint16 apc_mi; /* APC - Max Iteration */ + vuint16 ncits; /* Number of Cells In TimeSlot */ + vuint16 apcnt; /* APC - N Timer */ + vuint16 reserved1; /* reserved */ + vuint16 eapcst; /* APC status */ + vuint16 ptp_counter; /* PTP queue length */ + vuint16 ptp_txch; /* PTP channel */ + vuint16 reserved2; /* reserved */ +}; + +struct ct_entry_t { + /* RCT */ + unsigned fhnt:1; + unsigned pm_rct:1; + unsigned reserved0:6; + unsigned hec:1; + unsigned clp:1; + unsigned cng_ncrc:1; + unsigned inf_rct:1; + unsigned cngi_ptp:1; + unsigned cdis_rct:1; + unsigned aal_rct:2; + uint16 rbalen; + uint32 rcrc; + uint32 rb_ptr; + uint16 rtmlen; + uint16 rbd_ptr; + uint16 rbase; + uint16 tstamp; + uint16 imask; + unsigned ft:2; + unsigned nim:1; + unsigned reserved1:2; + unsigned rpmt:6; + unsigned reserved2:5; + uint8 reserved3[8]; + /* TCT */ + unsigned reserved4:1; + unsigned pm_tct:1; + unsigned reserved5:6; + unsigned pc:1; + unsigned reserved6:2; + unsigned inf_tct:1; + unsigned cr10:1; + unsigned cdis_tct:1; + unsigned aal_tct:2; + uint16 tbalen; + uint32 tcrc; + uint32 tb_ptr; + uint16 ttmlen; + uint16 tbd_ptr; + uint16 tbase; + unsigned reserved7:5; + unsigned tpmt:6; + unsigned reserved8:3; + unsigned avcf:1; + unsigned act:1; + uint32 chead; + uint16 apcl; + uint16 apcpr; + unsigned out:1; + unsigned bnr:1; + unsigned tservice:2; + unsigned apcp:12; + uint16 apcpf; +}; + +struct tcte_entry_t { + unsigned res1:4; + unsigned scr:12; + uint16 scrf; + uint16 bt; + uint16 buptrh; + uint32 buptrl; + unsigned vbr2:1; + unsigned res2:15; + uint16 oobr; + uint16 res3[8]; +}; + +#define SIZE_OF_RBD 12 +#define SIZE_OF_TBD 12 + +struct atm_bd_t { + vuint16 flags; + vuint16 length; + unsigned char *buffer_ptr; + vuint16 cpcs_uu_cpi; + vuint16 reserved; +}; + +/* BD flags */ +#define EMPTY 0x8000 +#define READY 0x8000 +#define WRAP 0x2000 +#define INTERRUPT 0x1000 +#define LAST 0x0800 +#define FIRST 0x0400 +#define OAM 0x0400 +#define CONTINUOUS 0x0200 +#define HEC_ERROR 0x0080 +#define CELL_LOSS 0x0040 +#define CONGESTION 0x0020 +#define ABORT 0x0010 +#define LEN_ERROR 0x0002 +#define CRC_ERROR 0x0001 + +struct atm_connection_t { + struct atm_bd_t *rbd_ptr; + int num_rbd; + struct atm_bd_t *tbd_ptr; + int num_tbd; + struct ct_entry_t *ct_ptr; + struct tcte_entry_t *tcte_ptr; + void *drv; + void (*notify) (void *drv, int event); +}; + +struct atm_driver_t { + int loaded; + int started; + char *csram; + int csram_size; + uint32 *am_top; + uint16 *ap_top; + uint32 *int_reload_ptr; + uint32 *int_serv_ptr; + struct atm_bd_t *rbd_base_ptr; + struct atm_bd_t *tbd_base_ptr; + unsigned linerate_in_bps; +}; + +extern struct atm_connection_t g_conn[NUM_CONNECTIONS]; +extern struct atm_driver_t g_atm; + +extern int atmLoad (void); +extern void atmUnload (void); diff --git a/board/siemens/IAD210/config.mk b/board/siemens/IAD210/config.mk new file mode 100644 index 0000000..c30abcb --- /dev/null +++ b/board/siemens/IAD210/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# iad210 boards +# + +TEXT_BASE = 0x08000000 +/*TEXT_BASE = 0x00200000 */ diff --git a/board/siemens/IAD210/flash.c b/board/siemens/IAD210/flash.c new file mode 100644 index 0000000..110858d --- /dev/null +++ b/board/siemens/IAD210/flash.c @@ -0,0 +1,502 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size; + + return (size); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds new file mode 100644 index 0000000..42e1b83 --- /dev/null +++ b/board/siemens/IAD210/u-boot.lds @@ -0,0 +1,139 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + cpu/mpc8xx/interrupts.o (.text) + lib_ppc/time.o (.text) + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile new file mode 100644 index 0000000..af646e4 --- /dev/null +++ b/board/siemens/SCM/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \ + ../../tqm8xx/load_sernum_ethaddr.o + + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/siemens/SCM/config.mk b/board/siemens/SCM/config.mk new file mode 100644 index 0000000..855ae38 --- /dev/null +++ b/board/siemens/SCM/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Siemens SCM boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_SCM.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# +TEXT_BASE = 0x40000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c new file mode 100644 index 0000000..056fe81 --- /dev/null +++ b/board/siemens/SCM/flash.c @@ -0,0 +1,488 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AMD devices on the TQM8260 board + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define V_ULONG(a) (*(volatile unsigned long *)( a )) +#define V_BYTE(a) (*(volatile unsigned char *)( a )) + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +/*----------------------------------------------------------------------- + */ +void flash_reset (void) +{ + if (flash_info[0].flash_id != FLASH_UNKNOWN) { + V_ULONG (flash_info[0].start[0]) = 0x00F000F0; + V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0; + } +} + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size (ulong baseaddr, flash_info_t * info) +{ + short i; + unsigned long flashtest_h, flashtest_l; + + /* Write auto select command sequence and test FLASH answer */ + V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA; + V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055; + V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090; + V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA; + V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055; + V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090; + + flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */ + flashtest_l = V_ULONG (baseaddr + 4); + + switch ((int) flashtest_h) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + flashtest_h = V_ULONG (baseaddr + 8); /* device ID */ + flashtest_l = V_ULONG (baseaddr + 12); + if (flashtest_h != flashtest_l) { + info->flash_id = FLASH_UNKNOWN; + } else { + switch (flashtest_h) { + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00400000; + break; /* 4 * 1 MB = 4 MB */ + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00400000; + break; /* 4 * 1 MB = 4 MB */ + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00800000; + break; /* 4 * 2 MB = 8 MB */ + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00800000; + break; /* 4 * 2 MB = 8 MB */ + case AMD_ID_DL322T: + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_DL322B: + info->flash_id += FLASH_AMDL322B; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_DL323T: + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_DL323B: + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_LV640U: + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x02000000; + break; /* 4 * 8 MB = 32 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* no or unknown flash */ + } + } + + if (flashtest_h == AMD_ID_LV640U) { + + /* set up sector start adress table (uniform sector type) */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = baseaddr + (i * 0x00040000); + + } else if (info->flash_id & FLASH_BTYPE) { + + /* set up sector start adress table (bottom sector type) */ + info->start[0] = baseaddr + 0x00000000; + info->start[1] = baseaddr + 0x00010000; + info->start[2] = baseaddr + 0x00018000; + info->start[3] = baseaddr + 0x00020000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; + } + + } else { + + /* set up sector start adress table (top sector type) */ + i = info->sector_count - 1; + info->start[i--] = baseaddr + info->size - 0x00010000; + info->start[i--] = baseaddr + info->size - 0x00018000; + info->start[i--] = baseaddr + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = baseaddr + i * 0x00040000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + if ((V_ULONG (info->start[i] + 16) & 0x00010001) || + (V_ULONG (info->start[i] + 20) & 0x00010001)) { + info->protect[i] = 1; /* D0 = 1 if protected */ + } else { + info->protect[i] = 0; + } + } + + flash_reset (); + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here (only one bank) */ + + size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]); + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + /* + * protect monitor and environment sectors + */ + +#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM800T: + printf ("29LV800T (8 M, top sector)\n"); + break; + case FLASH_AM800B: + printf ("29LV800T (8 M, bottom sector)\n"); + break; + case FLASH_AM160T: + printf ("29LV160T (16 M, top sector)\n"); + break; + case FLASH_AM160B: + printf ("29LV160B (16 M, bottom sector)\n"); + break; + case FLASH_AMDL322T: + printf ("29DL322T (32 M, top sector)\n"); + break; + case FLASH_AMDL322B: + printf ("29DL322B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL323T: + printf ("29DL323T (32 M, top sector)\n"); + break; + case FLASH_AMDL323B: + printf ("29DL323B (32 M, bottom sector)\n"); + break; + case FLASH_AM640U: + printf ("29LV640D (64 M, uniform sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080; + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; + udelay (1000); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + V_ULONG (info->start[sect]) = 0x00300030; + V_ULONG (info->start[sect] + 4) = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || + (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) + { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + flash_reset (); + + printf (" done\n"); + return 0; +} + +static int write_dword (flash_info_t *, ulong, unsigned char *); + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong dp; + static unsigned char bb[8]; + int i, l, rc, cc = cnt; + + dp = (addr & ~7); /* get lower dword aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - dp) != 0) { + for (i = 0; i < 8; i++) + bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++; + if ((rc = write_dword (info, dp, bb)) != 0) { + return (rc); + } + dp += 8; + cc -= 8 - l; + } + + /* + * handle word aligned part + */ + while (cc >= 8) { + if ((rc = write_dword (info, dp, src)) != 0) { + return (rc); + } + dp += 8; + src += 8; + cc -= 8; + } + + if (cc <= 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + for (i = 0; i < 8; i++) { + bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i); + } + return (write_dword (info, dp, bb)); +} + +/*----------------------------------------------------------------------- + * Write a dword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) +{ + ulong start, cl, ch; + int flag, i; + + for (ch = 0, i = 0; i < 4; i++) + ch = (ch << 8) + *pdata++; /* high word */ + for (cl = 0, i = 0; i < 4; i++) + cl = (cl << 8) + *pdata++; /* low word */ + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *) dest) & ch) != ch + || (*((vu_long *) (dest + 4)) & cl) != cl) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0; + V_ULONG (dest) = ch; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0; + V_ULONG (dest + 4) = cl; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || + ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c new file mode 100644 index 0000000..661bf66 --- /dev/null +++ b/board/siemens/SCM/fpga_scm.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2002 + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include "../common/fpga.h" + +fpga_t fpga_list[] = { + {"FIOX", CFG_FIOX_BASE, + CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE} + , + {"FDOHM", CFG_FDOHM_BASE, + CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE} +}; +int fpga_count = sizeof (fpga_list) / sizeof (fpga_t); + + +ulong fpga_control (fpga_t * fpga, int cmd) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + switch (cmd) { + case FPGA_INIT_IS_HIGH: + immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */ + return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0; + + case FPGA_INIT_SET_LOW: + immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */ + immr->im_ioport.iop_pdatd &= ~fpga->init_mask; + break; + + case FPGA_INIT_SET_HIGH: + immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */ + immr->im_ioport.iop_pdatd |= fpga->init_mask; + break; + + case FPGA_PROG_SET_LOW: + immr->im_ioport.iop_pdatd &= ~fpga->prog_mask; + break; + + case FPGA_PROG_SET_HIGH: + immr->im_ioport.iop_pdatd |= fpga->prog_mask; + break; + + case FPGA_DONE_IS_HIGH: + return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0; + + case FPGA_READ_MODE: + break; + + case FPGA_LOAD_MODE: + break; + + case FPGA_GET_ID: + if (fpga->conf_base == CFG_FIOX_BASE) { + ulong ver = + *(volatile ulong *) (fpga->conf_base + 0x10); + return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0); + } else if (fpga->conf_base == CFG_FDOHM_BASE) { + return (*(volatile ushort *) fpga->conf_base) & 0xff; + } else { + return *(volatile ulong *) fpga->conf_base; + } + + case FPGA_INIT_PORTS: + immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */ + immr->im_ioport.iop_psord &= ~fpga->init_mask; + immr->im_ioport.iop_pdird &= ~fpga->init_mask; + + immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */ + immr->im_ioport.iop_psord &= ~fpga->prog_mask; + immr->im_ioport.iop_pdird |= fpga->prog_mask; + + immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */ + immr->im_ioport.iop_psord &= ~fpga->done_mask; + immr->im_ioport.iop_pdird &= ~fpga->done_mask; + + break; + + } + return 0; +} diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c new file mode 100644 index 0000000..d20688d --- /dev/null +++ b/board/siemens/SCM/scm.c @@ -0,0 +1,540 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "scm.h" + +static void config_scoh_cs(void); +extern int fpga_init(void); + +#if 0 +#define DEBUGF(fmt,args...) printf (fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, + /* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */ + /* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */ + /* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */ + /* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */ + /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */ + /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */ + /* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */ + /* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, + /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */ + /* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */ + /* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */ + /* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */ + /* PB27 */ { 0, 1, 0, 0, 0, 0 }, + /* PB26 */ { 0, 1, 0, 0, 0, 0 }, + /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */ + /* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */ + /* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */ + /* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */ + /* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */ + /* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */ + /* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */ + /* PB18 */ { 0, 1, 0, 0, 0, 0 }, + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ + /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */ + /* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */ + /* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */ + /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */ + /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */ + /* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ + /* PC19 */ { 0, 1, 0, 0, 0, 0 }, + /* PC18 */ { 0, 1, 0, 0, 0, 0 }, + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, + /* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */ + /* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */ + }, + + /* Port D configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, + /* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */ + /* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */ + /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ + /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */ + /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */ + /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */ + /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */ + /* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */ + /* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */ + /* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, + /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */ + /* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (!i || strncmp (str, "TQM8260", 7)) { + puts ("### No HW ID - assuming TQM8260\n"); + return (0); + } + + puts (str); + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; + orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +/* + * Test Power-On-Reset. + */ +int power_on_reset (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Test Reset Status Register */ + return gd->reset_status & RSR_CSRS ? 0 : 1; +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + long size8, size9; +#endif + long psize, lsize; + + psize = 16 * 1024 * 1024; + lsize = 0; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#if 0 /* Just for debugging */ +#define prt_br_or(brX,orX) do { \ + ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ + ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ + printf ("\n" \ + #brX " 0x%08x " #orX " 0x%08x " \ + "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ + memctl->memc_ ## brX, memctl->memc_ ## orX, \ + start, start+sizem, (sizem+1)>>20); \ + } while (0) + prt_br_or (br0, or0); + prt_br_or (br1, or1); + prt_br_or (br2, or2); + prt_br_or (br3, or3); +#endif + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL - %ld MB, ", psize >> 20); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL - %ld MB, ", psize >> 20); + } + + /* Local SDRAM setup: + */ +#ifdef CFG_INIT_LOCAL_SDRAM + memctl->memc_lsrt = CFG_LSRT; + size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, + (uchar *) SDRAM_BASE2_PRELIM); + + if (size8 < size9) { + lsize = size9; + printf ("Local:9COL - %ld MB) using ", lsize >> 20); + } else { + lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + printf ("Local:8COL - %ld MB) using ", lsize >> 20); + } + +#if 0 + /* Set up BR2 so that the local SDRAM goes + * right after the 60x SDRAM + */ + memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | + (CFG_SDRAM_BASE + psize); +#endif +#endif /* CFG_INIT_LOCAL_SDRAM */ +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + config_scoh_cs (); + + return (psize); +} + +/* ------------------------------------------------------------------------- */ + +static void config_scoh_cs (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immr->im_memctl; + volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE; + volatile uint tmp, i; + + /* Initialize OR3 / BR3 for CAN Bus Controller 0 */ + memctl->memc_or3 = CFG_CAN0_OR3; + memctl->memc_br3 = CFG_CAN0_BR3; + /* Initialize OR4 / BR4 for CAN Bus Controller 1 */ + memctl->memc_or4 = CFG_CAN1_OR4; + memctl->memc_br4 = CFG_CAN1_BR4; + + /* Initialize MAMR to write in the array at address 0x0 */ + memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS; + + /* Initialize UPMA for CAN: single read */ + memctl->memc_mdr = 0xcffeec00; + udelay (1); /* Necessary to have the data correct in the UPM array!!!! */ + /* The read on the CAN controller write the data of mdr in UPMA array. */ + /* The index to the array will be incremented automatically + through this read */ + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcfc00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x0ffcfc00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0xfffdec07; + udelay (1); + tmp = can->cpu_interface; + + + /* Initialize MAMR to write in the array at address 0x18 */ + memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS; + + /* Initialize UPMA for CAN: single write */ + memctl->memc_mdr = 0xfcffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00ffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00ffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00ffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00ffec00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00fffc00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x00fffc00; + udelay (1); + tmp = can->cpu_interface; + + memctl->memc_mdr = 0x30ffec07; + udelay (1); + tmp = can->cpu_interface; + + /* Initialize MAMR */ + memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */ + + + /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */ + memctl->memc_or5 = CFG_EXTPROM_OR5; + memctl->memc_br5 = CFG_EXTPROM_BR5; + /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */ + memctl->memc_or6 = CFG_EXTPROM_OR6; + memctl->memc_br6 = CFG_EXTPROM_BR6; + + /* Initialize OR7 / BR7 for the Glue Logic */ + memctl->memc_or7 = CFG_FIOX_OR7; + memctl->memc_br7 = CFG_FIOX_BR7; + + /* Initialize OR8 / BR8 for the DOH Logic */ + memctl->memc_or8 = CFG_FDOHM_OR8; + memctl->memc_br8 = CFG_FDOHM_BR8; + + DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0); + DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1); + DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2); + DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3); + DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4); + DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5); + DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6); + DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7); + DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8); + + DEBUGF ("UPMA addr 0x0\n"); + memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS; + for (i = 0; i < 0x8; i++) { + tmp = can->cpu_interface; + udelay (1); + DEBUGF (" %08x ", memctl->memc_mdr); + } + DEBUGF ("\nUPMA addr 0x18\n"); + memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS; + for (i = 0; i < 0x8; i++) { + tmp = can->cpu_interface; + udelay (1); + DEBUGF (" %08x ", memctl->memc_mdr); + } + DEBUGF ("\n"); + memctl->memc_mamr = MxMR_GPL_x4DIS; +} + +/* ------------------------------------------------------------------------- */ + +int misc_init_r (void) +{ + fpga_init (); + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/SCM/scm.h b/board/siemens/SCM/scm.h new file mode 100644 index 0000000..70c12e6 --- /dev/null +++ b/board/siemens/SCM/scm.h @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SCM_H +#define __SCM_H + +/*----------------*/ +/* CAN Structures */ +/*----------------*/ + +/* Message */ +typedef struct can_msg { + uchar ctrl_0; + uchar ctrl_1; + uchar arbit_0; + uchar arbit_1; + uchar arbit_2; + uchar arbit_3; + uchar config; + uchar data[8]; +} can_msg_t; + +/* CAN Register */ +typedef struct can_reg { + uchar ctrl; + uchar status; + uchar cpu_interface; + uchar resv0; + ushort high_speed_rd; + ushort gbl_mask_std; + uint gbl_mask_extd; + uint msg15_mask; + can_msg_t msg1 __attribute__ ((packed)); + uchar clkout; + can_msg_t msg2 __attribute__ ((packed)); + uchar bus_config; + can_msg_t msg3 __attribute__ ((packed)); + uchar bit_timing_0; + can_msg_t msg4 __attribute__ ((packed)); + uchar bit_timing_1; + can_msg_t msg5 __attribute__ ((packed)); + uchar interrupt; + can_msg_t msg6 __attribute__ ((packed)); + uchar resv1; + can_msg_t msg7 __attribute__ ((packed)); + uchar resv2; + can_msg_t msg8 __attribute__ ((packed)); + uchar resv3; + can_msg_t msg9 __attribute__ ((packed)); + uchar p1conf; + can_msg_t msg10 __attribute__ ((packed)); + uchar p2conf; + can_msg_t msg11 __attribute__ ((packed)); + uchar p1in; + can_msg_t msg12 __attribute__ ((packed)); + uchar p2in; + can_msg_t msg13 __attribute__ ((packed)); + uchar p1out; + can_msg_t msg14 __attribute__ ((packed)); + uchar p2out; + can_msg_t msg15 __attribute__ ((packed)); + uchar ser_res_addr; + uchar resv_cs[0x8000-0x100]; /* 0x8000 is the min size for CS */ +} can_reg_t; + + +#endif /* __SCM_H */ diff --git a/board/siemens/SCM/u-boot.lds b/board/siemens/SCM/u-boot.lds new file mode 100644 index 0000000..05f29c6 --- /dev/null +++ b/board/siemens/SCM/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/siemens/common/README b/board/siemens/common/README new file mode 100644 index 0000000..7f1c8cd --- /dev/null +++ b/board/siemens/common/README @@ -0,0 +1,27 @@ +CCM/SCM-Ergaenzungen fuer U-Boot und Linux: +------------------------------------------- + +Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs: + + => help fpga + fpga fpga status [name] - print FPGA status + fpga reset [name] - reset FPGA + fpga load [name] addr - load FPGA configuration data + +Der Name kann beim CCM-Module auch weggelassen werden. +Die Laengenangabe und damit "puma_len" ist nicht mehr +noetig: + + => fpga load puma 40600000 + FPGA load PUMA: addr 40600000: (00000005)... done + +Die MTD-Partitionierung kann nun mittels "bootargs" ueber- +geben werden: + + => printenv addmtd + addmtd=setenv bootargs ${bootargs} + mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2) + +Die Portierung auf SMC ist natuerlich noch nicht getestet. + +Wolfgang Grandegger (04.06.2002) diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c new file mode 100644 index 0000000..e9941cd --- /dev/null +++ b/board/siemens/common/fpga.c @@ -0,0 +1,364 @@ +/* + * (C) Copyright 2002 + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include + +#include "fpga.h" + +int power_on_reset(void); + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + + +static int fpga_get_version(fpga_t* fpga, char* name) +{ + char vname[12]; + /* + * Net-list string format: + * "vvvvvvvvddddddddn...". + * Version Date Name + * "0000000322042002PUMA" = PUMA version 3 from 22.04.2002. + */ + if (strlen(name) < (16 + strlen(fpga->name))) + goto failure; + /* Check FPGA name */ + if (strcmp(&name[16], fpga->name) != 0) + goto failure; + /* Get version number */ + memcpy(vname, name, 8); + vname[8] = '\0'; + return simple_strtoul(vname, NULL, 16); + + failure: + printf("Image name %s is invalid\n", name); + return -1; +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +static fpga_t* fpga_get(char* fpga_name) +{ + char name[FPGA_NAME_LEN]; + int i; + + if (strlen(fpga_name) >= FPGA_NAME_LEN) + goto failure; + for (i = 0; i < strlen(fpga_name); i++) + name[i] = toupper(fpga_name[i]); + name[i] = '\0'; + for (i = 0; i < fpga_count; i++) { + if (strcmp(name, fpga_list[i].name) == 0) + return &fpga_list[i]; + } + failure: + printf("FPGA: name %s is invalid\n", fpga_name); + return NULL; +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +static void fpga_status (fpga_t* fpga) +{ + /* Check state */ + if (fpga_control(fpga, FPGA_DONE_IS_HIGH)) + printf ("%s is loaded (%08lx)\n", + fpga->name, fpga_control(fpga, FPGA_GET_ID)); + else + printf ("%s is NOT loaded\n", fpga->name); +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */ + +static int fpga_reset (fpga_t* fpga) +{ + int i; + + /* Set PROG to low and wait til INIT goes low */ + fpga_control(fpga, FPGA_PROG_SET_LOW); + for (i = 0; i < FPGA_RESET_TIMEOUT; i++) { + udelay (100); + if (!fpga_control(fpga, FPGA_INIT_IS_HIGH)) + break; + } + if (i == FPGA_RESET_TIMEOUT) + goto failure; + + /* Set PROG to high and wait til INIT goes high */ + fpga_control(fpga, FPGA_PROG_SET_HIGH); + for (i = 0; i < FPGA_RESET_TIMEOUT; i++) { + udelay (100); + if (fpga_control(fpga, FPGA_INIT_IS_HIGH)) + break; + } + if (i == FPGA_RESET_TIMEOUT) + goto failure; + + return 0; + failure: + return 1; +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */ + +static int fpga_load (fpga_t* fpga, ulong addr, int checkall) +{ + volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base; + image_header_t hdr; + ulong len, checksum; + uchar *data = (uchar *)&hdr; + char *s, msg[32]; + int verify, i; + + /* + * Check the image header and data of the net-list + */ + memcpy (&hdr, (char *)addr, sizeof(image_header_t)); + + if (hdr.ih_magic != IH_MAGIC) { + strcpy (msg, "Bad Image Magic Number"); + goto failure; + } + + len = sizeof(image_header_t); + + checksum = hdr.ih_hcrc; + hdr.ih_hcrc = 0; + + if (crc32 (0, data, len) != checksum) { + strcpy (msg, "Bad Image Header CRC"); + goto failure; + } + + data = (uchar*)(addr + sizeof(image_header_t)); + len = hdr.ih_size; + + s = getenv ("verify"); + verify = (s && (*s == 'n')) ? 0 : 1; + if (verify) { + if (crc32 (0, data, len) != hdr.ih_dcrc) { + strcpy (msg, "Bad Image Data CRC"); + goto failure; + } + } + + if (checkall && fpga_get_version(fpga, (char *)(hdr.ih_name)) < 0) + return 1; + + /* align length */ + if (len & 1) + ++len; + + /* + * Reset FPGA and wait for completion + */ + if (fpga_reset(fpga)) { + strcpy (msg, "Reset Timeout"); + goto failure; + } + + printf ("(%s)... ", hdr.ih_name); + /* + * Copy data to FPGA + */ + fpga_control (fpga, FPGA_LOAD_MODE); + while (len--) { + *fpga_addr = *data++; + } + fpga_control (fpga, FPGA_READ_MODE); + + /* + * Wait for completion and check error status if timeout + */ + for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) { + udelay (100); + if (fpga_control (fpga, FPGA_DONE_IS_HIGH)) + break; + } + if (i == FPGA_LOAD_TIMEOUT) { + if (fpga_control(fpga, FPGA_INIT_IS_HIGH)) + strcpy(msg, "Invalid Size"); + else + strcpy(msg, "CRC Error"); + goto failure; + } + + printf("done\n"); + return 0; + + failure: + + printf("ERROR: %s\n", msg); + return 1; +} + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr = 0; + int i; + fpga_t* fpga; + + if (argc < 2) + goto failure; + + if (strncmp(argv[1], "stat", 4) == 0) { /* status */ + if (argc == 2) { + for (i = 0; i < fpga_count; i++) { + fpga_status (&fpga_list[i]); + } + } + else if (argc == 3) { + if ((fpga = fpga_get(argv[2])) == 0) + goto failure; + fpga_status (fpga); + } + else + goto failure; + } + else if (strcmp(argv[1],"load") == 0) { /* load */ + if (argc == 3 && fpga_count == 1) { + fpga = &fpga_list[0]; + } + else if (argc == 4) { + if ((fpga = fpga_get(argv[2])) == 0) + goto failure; + } + else + goto failure; + + addr = simple_strtoul(argv[argc-1], NULL, 16); + + printf ("FPGA load %s: addr %08lx: ", + fpga->name, addr); + fpga_load (fpga, addr, 1); + + } + else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */ + if (argc == 2 && fpga_count == 1) { + fpga = &fpga_list[0]; + } + else if (argc == 3) { + if ((fpga = fpga_get(argv[2])) == 0) + goto failure; + } + else + goto failure; + + printf ("FPGA reset %s: ", fpga->name); + if (fpga_reset(fpga)) + printf ("ERROR: Timeout\n"); + else + printf ("done\n"); + } + else + goto failure; + + return 0; + + failure: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + fpga, 4, 1, do_fpga, + "fpga - access FPGA(s)\n", + "fpga status [name] - print FPGA status\n" + "fpga reset [name] - reset FPGA\n" + "fpga load [name] addr - load FPGA configuration data\n" +); + +#endif /* CONFIG_COMMANDS & CFG_CMD_BSP */ + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +int fpga_init (void) +{ + ulong addr; + ulong new_id, old_id = 0; + image_header_t *hdr; + fpga_t* fpga; + int do_load, i, j; + char name[16], *s; + + /* + * Port setup for FPGA control + */ + for (i = 0; i < fpga_count; i++) { + fpga_control(&fpga_list[i], FPGA_INIT_PORTS); + } + + /* + * Load FPGA(s): a new net-list is loaded if the FPGA is + * empty, Power-on-Reset or the old one is not up-to-date + */ + for (i = 0; i < fpga_count; i++) { + fpga = &fpga_list[i]; + printf ("%s: ", fpga->name); + + for (j = 0; j < strlen(fpga->name); j++) + name[j] = tolower(fpga->name[j]); + name[j] = '\0'; + sprintf(name, "%s_addr", name); + addr = 0; + if ((s = getenv(name)) != NULL) + addr = simple_strtoul(s, NULL, 16); + + if (!addr) { + printf ("env. variable %s undefined\n", name); + return 1; + } + + hdr = (image_header_t *)addr; + if ((new_id = fpga_get_version(fpga, (char *)(hdr->ih_name))) == -1) + return 1; + + do_load = 1; + + if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) { + old_id = fpga_control(fpga, FPGA_GET_ID); + if (new_id == old_id) + do_load = 0; + } + + if (do_load) { + printf ("loading "); + fpga_load (fpga, addr, 0); + } else { + printf ("loaded (%08lx)\n", old_id); + } + } + + return 0; +} diff --git a/board/siemens/common/fpga.h b/board/siemens/common/fpga.h new file mode 100644 index 0000000..2de25b0 --- /dev/null +++ b/board/siemens/common/fpga.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2002 + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef _FPGA_H_ +#define _FPGA_H_ + +#define FPGA_INIT_IS_HIGH 0 +#define FPGA_INIT_SET_HIGH 1 +#define FPGA_INIT_SET_LOW 2 +#define FPGA_PROG_SET_HIGH 3 +#define FPGA_PROG_SET_LOW 4 +#define FPGA_DONE_IS_HIGH 5 +#define FPGA_READ_MODE 6 +#define FPGA_LOAD_MODE 7 +#define FPGA_GET_ID 8 +#define FPGA_INIT_PORTS 9 + +#define FPGA_NAME_LEN 8 +typedef struct { + char name[FPGA_NAME_LEN]; + ulong conf_base; + uint init_mask; + uint prog_mask; + uint done_mask; +} fpga_t; + +extern fpga_t fpga_list[]; +extern int fpga_count; + +ulong fpga_control (fpga_t* fpga, int cmd); + +#endif /* _FPGA_H_ */ diff --git a/board/siemens/pcu_e/Makefile b/board/siemens/pcu_e/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/siemens/pcu_e/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/siemens/pcu_e/config.mk b/board/siemens/pcu_e/config.mk new file mode 100644 index 0000000..10f3773 --- /dev/null +++ b/board/siemens/pcu_e/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Siemens PCU E Boards +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c new file mode 100644 index 0000000..05c364b --- /dev/null +++ b/board/siemens/pcu_e/flash.c @@ -0,0 +1,700 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + * + * The PCU E uses an address map where flash banks are aligned top + * down, so that the "first" flash bank ends at top of memory, and + * the monitor entry point is at address (0xFFF00100). The second + * flash bank is mapped immediately below bank 0. + * + * This is NOT in conformance to the "official" memory map! + * + */ + +#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \ + - (0xFFFFFFFF - CFG_MONITOR_BASE) ) + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long base, size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + DEBUGF ("## Before remap: " + "BR0: 0x%08x OR0: 0x%08x " + "BR6: 0x%08x OR6: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0, + memctl->memc_br6, memctl->memc_or6); + + /* Remap FLASH according to real size */ + base = 0 - size_b0; + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; + + DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)base, &flash_info[0]); + base = 0 - size_b0; + + flash_info[0].size = size_b0; + + flash_get_offsets (base, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + PCU_MONITOR_BASE, + PCU_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + + if (size_b1) { + flash_info_t tmp_info; + + memctl->memc_or6 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) | + BR_PS_16 | BR_MS_GPCM | BR_V; + + DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n", + memctl->memc_br6, memctl->memc_or6); + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(base - size_b1), + &flash_info[1]); + base -= size_b1; + + flash_get_offsets (base, &flash_info[1]); + + flash_info[1].size = size_b1; + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[1]); +#endif + /* + * Swap bank numbers so that addresses are in ascending order + */ + tmp_info = flash_info[0]; + flash_info[0] = flash_info[1]; + flash_info[1] = tmp_info; + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + + DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + short n; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) { + return; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDL322T: + case FLASH_AMDL323T: + case FLASH_AMDL324T: + /* set sector offsets for top boot block type */ + + base += info->size; + i = info->sector_count; + for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ + base -= 8 << 10; + --i; + info->start[i] = base; + } + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + return; + case FLASH_AMDL322B: + case FLASH_AMDL323B: + case FLASH_AMDL324B: + /* set sector offsets for bottom boot block type */ + for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ + info->start[i] = base; + base += 8 << 10; + } + while (base < info->size) { /* 64k regular sectors */ + info->start[i] = base; + base += 64 << 10; + ++i; + } + return; + case FLASH_AMDL640: + /* set sector offsets for dual boot block type */ + for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ + info->start[i] = base; + base += 8 << 10; + } + n = info->sector_count - 8; + while (i < n) { /* 64k regular sectors */ + info->start[i] = base; + base += 64 << 10; + ++i; + } + while (i < info->sector_count) { /* 8 x 8k boot sectors */ + info->start[i] = base; + base += 8 << 10; + ++i; + } + return; + default: + return; + } + /* NOTREACHED */ +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n"); + break; + default: printf ("Unknown Chip Type 0x%lX\n", + info->flash_id); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ushort value; + vu_short *saddr = (vu_short *)addr; + + /* Write auto select command: read Manufacturer ID */ + saddr[0x0555] = 0x00AA; + saddr[0x02AA] = 0x0055; + saddr[0x0555] = 0x0090; + + value = saddr[0]; + + DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value); + + switch (value) { + case (AMD_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & 0xFFFF): + info->flash_id = FLASH_MAN_FUJ; + break; + default: + DEBUGF("Unknown Manufacturer ID\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = saddr[1]; /* device ID */ + + DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value); + + switch (value) { + + case (AMD_ID_DL322T & 0xFFFF): + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 8 MB */ + + case (AMD_ID_DL322B & 0xFFFF): + info->flash_id += FLASH_AMDL322B; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 8 MB */ + + case (AMD_ID_DL323T & 0xFFFF): + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 8 MB */ + + case (AMD_ID_DL323B & 0xFFFF): + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 8 MB */ + + case (AMD_ID_DL324T & 0xFFFF): + info->flash_id += FLASH_AMDL324T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 8 MB */ + + case (AMD_ID_DL324B & 0xFFFF): + info->flash_id += FLASH_AMDL324B; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 8 MB */ + case (AMD_ID_DL640 & 0xFFFF): + info->flash_id += FLASH_AMDL640; + info->sector_count = 142; + info->size = 0x00800000; + break; + default: + DEBUGF("Unknown Device ID\n"); + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + flash_get_offsets ((ulong)addr, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { +#if 0 + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + saddr = (vu_short *)(info->start[i]); + info->protect[i] = saddr[2] & 1; +#else + info->protect[i] =0; +#endif + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + saddr = (vu_short *)info->start[0]; + *saddr = 0x00F0; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_short *addr = (vu_short*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0080; + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_short*)(info->start[sect]); + addr[0] = 0x0030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_short*)(info->start[l_sect]); + while ((addr[0] & 0x0080) != 0x0080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_short *)info->start[0]; + addr[0] = 0x00F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +#define FLASH_WIDTH 2 /* flash bus width in bytes */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= FLASH_WIDTH) { + data = 0; + for (i=0; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; istart[0]); + vu_short *sdest = (vu_short *)dest; + ushort sdata = (ushort)data; + ushort sval; + ulong start, passed; + int flag, rc; + + /* Check if Flash is (sufficiently) erased */ + if ((*sdest & sdata) != sdata) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x00A0; + +#ifdef WORKAROUND_FOR_BROKEN_HARDWARE + /* work around the timeout bugs */ + udelay(20); +#endif + + *sdest = sdata; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + rc = 0; + /* data polling for D7 */ + start = get_timer (0); + + for (passed=0; passed < CFG_FLASH_WRITE_TOUT; passed=get_timer(start)) { + + sval = *sdest; + + if ((sval & 0x0080) == (sdata & 0x0080)) + break; + + if ((sval & 0x0020) == 0) /* DQ5: Timeout? */ + continue; + + sval = *sdest; + + if ((sval & 0x0080) != (sdata & 0x0080)) + rc = 1; + + break; + } + + if (rc) { + DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n", + dest, sval, sdata); + } + + if (passed >= CFG_FLASH_WRITE_TOUT) { + DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n", + dest, sval, sdata); + rc = 1; + } + + /* reset to read mode */ + addr = (vu_short *)info->start[0]; + addr[0] = 0x00F0; /* reset bank */ + + return (rc); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c new file mode 100644 index 0000000..3f05e4a --- /dev/null +++ b/board/siemens/pcu_e/pcu_e.c @@ -0,0 +1,563 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); +static void puma_status (void); +static void puma_set_mode (int mode); +static int puma_init_done (void); +static void puma_load (ulong addr, ulong len); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +/* + * 50 MHz SDRAM access using UPM A + */ +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00, + 0x1ffddc47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPM RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */ + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00, + 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7ffffc07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + +/* + * PUMA access using UPM B + */ +const uint puma_table[] = { + /* + * Single Read. (Offset 0 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, + /* + * Precharge and MRS + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7ffffc07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + */ + +int checkboard (void) +{ + puts ("Board: Siemens PCU E\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + long int size_b0, reg; + int i; + + /* + * Configure UPMA for SDRAM + */ + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + memctl->memc_mptpr = CFG_MPTPR; + + /* burst length=4, burst type=sequential, CAS latency=2 */ + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 2 to the SDRAM bank at preliminary address. + */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_or5 = CFG_OR5_PRELIM; + memctl->memc_br5 = CFG_BR5_PRELIM; +#else /* XXX */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; +#endif /* XXX */ + + /* initialize memory address register */ + memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */ + + /* mode initialization (offset 5) */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + udelay (200); /* 0x8000A105 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05); +#else /* XXX */ + udelay (200); /* 0x80004105 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05); +#endif /* XXX */ + + /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + udelay (1); /* 0x8000A830 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30); +#else /* XXX */ + udelay (1); /* 0x80004830 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30); +#endif /* XXX */ + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + udelay (1); /* 0x8000A106 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06); +#else /* XXX */ + udelay (1); /* 0x80004106 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06); +#endif /* XXX */ + + reg = memctl->memc_mamr; + reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */ + reg |= MAMR_TLFA_4X; /* ... to 4x */ + reg |= MAMR_PTAE; /* enable refresh */ + memctl->memc_mamr = reg; + + udelay (200); + + /* Need at least 10 DRAM accesses to stabilize */ + for (i = 0; i < 10; ++i) { +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + volatile unsigned long *addr = + (volatile unsigned long *) SDRAM_BASE5_PRELIM; +#else /* XXX */ + volatile unsigned long *addr = + (volatile unsigned long *) SDRAM_BASE2_PRELIM; +#endif /* XXX */ + unsigned long val; + + val = *(addr + i); + *(addr + i) = val; + } + + /* + * Check Bank 0 Memory Size for re-configuration + */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); +#else /* XXX */ + size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); +#endif /* XXX */ + + memctl->memc_mamr = CFG_MAMR | MAMR_PTAE; + + /* + * Final mapping: + */ + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; + memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; +#else /* XXX */ + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; + memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; +#endif /* XXX */ + udelay (1000); + + /* + * Configure UPMB for PUMA + */ + upmconfig (UPMB, (uint *) puma_table, + sizeof (puma_table) / sizeof (uint)); + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size (base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#else /* XXX */ +#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \ + CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#endif /* XXX */ + +#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET) + +void reset_phy (void) +{ + immap_t *immr = (immap_t *) CFG_IMMR; + ulong value; + + /* Configure all needed port pins for GPIO */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +# ifdef CFG_ETH_MDDIS_VALUE + immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; +# else + immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */ +# endif + immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */ + immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */ + immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */ +#endif /* XXX */ + immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ + + value = immr->im_cpm.cp_pbdat; + + /* Assert Powerdown and Reset signals */ + value |= CFG_PB_ETH_POWERDOWN; + value &= ~(CFG_PB_ETH_RESET); + + /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ +#if !PCU_E_WITH_SWAPPED_CS +# ifdef CFG_ETH_MDDIS_VALUE + value |= CFG_PB_ETH_MDDIS; +# else + value &= ~(CFG_PB_ETH_MDDIS); +# endif +#endif +#ifdef CFG_ETH_CFG1_VALUE + value |= CFG_PB_ETH_CFG1; +#else + value &= ~(CFG_PB_ETH_CFG1); +#endif +#ifdef CFG_ETH_CFG2_VALUE + value |= CFG_PB_ETH_CFG2; +#else + value &= ~(CFG_PB_ETH_CFG2); +#endif +#ifdef CFG_ETH_CFG3_VALUE + value |= CFG_PB_ETH_CFG3; +#else + value &= ~(CFG_PB_ETH_CFG3); +#endif + + /* Drive output signals to initial state */ + immr->im_cpm.cp_pbdat = value; + immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; + udelay (10000); + + /* De-assert Ethernet Powerdown */ + immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + udelay (10000); + + /* de-assert RESET signal of PHY */ + immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET; + udelay (1000); +} + +/*----------------------------------------------------------------------- + * Board Special Commands: access functions for "PUMA" FPGA + */ +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +#define PUMA_READ_MODE 0 +#define PUMA_LOAD_MODE 1 + +int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, len; + + switch (argc) { + case 2: /* PUMA reset */ + if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */ + puma_status (); + return 0; + } + break; + case 4: /* PUMA load addr len */ + if (strcmp (argv[1], "load") != 0) + break; + + addr = simple_strtoul (argv[2], NULL, 16); + len = simple_strtoul (argv[3], NULL, 16); + + printf ("PUMA load: addr %08lX len %ld (0x%lX): ", + addr, len, len); + puma_load (addr, len); + + return 0; + default: + break; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD (puma, 4, 1, do_puma, + "puma - access PUMA FPGA\n", + "status - print PUMA status\n" + "puma load addr len - load PUMA configuration data\n"); + +#endif /* CFG_CMD_BSP */ + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +static void puma_set_mode (int mode) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + + /* disable PUMA in memory controller */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_br3 = 0; +#else /* XXX */ + memctl->memc_br4 = 0; +#endif /* XXX */ + + switch (mode) { + case PUMA_READ_MODE: +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_or3 = PUMA_CONF_OR_READ; + memctl->memc_br3 = PUMA_CONF_BR_READ; +#else /* XXX */ + memctl->memc_or4 = PUMA_CONF_OR_READ; + memctl->memc_br4 = PUMA_CONF_BR_READ; +#endif /* XXX */ + break; + case PUMA_LOAD_MODE: +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + memctl->memc_or3 = PUMA_CONF_OR_LOAD; + memctl->memc_br3 = PUMA_CONF_BR_LOAD; +#else /* XXX */ + memctl->memc_or4 = PUMA_CONF_OR_READ; + memctl->memc_br4 = PUMA_CONF_BR_READ; +#endif /* XXX */ + break; + } +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */ + +static void puma_load (ulong addr, ulong len) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */ + uchar *data = (uchar *) addr; + int i; + + /* align length */ + if (len & 1) + ++len; + + /* Reset FPGA */ + immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */ + immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT); + immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT); + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */ + immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */ + immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */ +#else + immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */ + immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */ + immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */ + immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */ +#endif /* XXX */ + udelay (100); + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ + immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */ +#else + immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */ +#endif /* XXX */ + + /* wait until INIT indicates completion of reset */ + for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) { + udelay (1000); + if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT) + break; + } + if (i == PUMA_INIT_TIMEOUT) { + printf ("*** PUMA init timeout ***\n"); + return; + } + + puma_set_mode (PUMA_LOAD_MODE); + + while (len--) + *fpga_addr = *data++; + + puma_set_mode (PUMA_READ_MODE); + + puma_status (); +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +static void puma_status (void) +{ + /* Check state */ + printf ("PUMA initialization is %scomplete\n", + puma_init_done ()? "" : "NOT "); +} + +/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ + +static int puma_init_done (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* make sure pin is GPIO input */ + immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE); + immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE); + immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE); + + return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0; +} + +/* ------------------------------------------------------------------------- */ + +int misc_init_r (void) +{ + ulong addr = 0; + ulong len = 0; + char *s; + + printf ("PUMA: "); + if (puma_init_done ()) { + printf ("initialized\n"); + return 0; + } + + if ((s = getenv ("puma_addr")) != NULL) + addr = simple_strtoul (s, NULL, 16); + + if ((s = getenv ("puma_len")) != NULL) + len = simple_strtoul (s, NULL, 16); + + if ((!addr) || (!len)) { + printf ("net list undefined\n"); + return 0; + } + + printf ("loading... "); + + puma_load (addr, len); + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds new file mode 100644 index 0000000..6505d45 --- /dev/null +++ b/board/siemens/pcu_e/u-boot.lds @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug new file mode 100644 index 0000000..828afbb --- /dev/null +++ b/board/siemens/pcu_e/u-boot.lds.debug @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sixnet/Makefile b/board/sixnet/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/sixnet/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sixnet/config.mk b/board/sixnet/config.mk new file mode 100644 index 0000000..0cd8f44 --- /dev/null +++ b/board/sixnet/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# SIXNET boards +# + +TEXT_BASE = 0xF8000000 diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c new file mode 100644 index 0000000..61d7580 --- /dev/null +++ b/board/sixnet/flash.c @@ -0,0 +1,790 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +/* environment.h defines the various CFG_ENV_... values in terms + * of whichever ones are given in the configuration file. + */ +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it + * has nothing to do with the flash chip being 8-bit or 16-bit. + */ +#ifdef CONFIG_FLASH_16BIT +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFF +#else +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static void flash_get_offsets(ulong base, flash_info_t *info); +#ifdef CFG_FLASH_PROTECTION +static void flash_sync_real_protect(flash_info_t *info); +#endif + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b; + int i; + + /* Init: no FLASHes known */ + for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + size_b = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size_b; + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b); + } + + /* Remap FLASH according to real size, so only at proper address */ + memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b); + + /* Do this again (was done already in flast_get_size), just + * in case we move it when remap the FLASH. + */ + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#ifdef CFG_FLASH_PROTECTION + /* read the hardware protection status (if any) into the + * protection array in flash_info. + */ + flash_sync_real_protect(&flash_info[0]); +#endif + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_ADDR + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + return (size_b); +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL + && (info->flash_id & FLASH_BTYPE)) { + int bootsect_size; /* number of bytes/boot sector */ + int sect_size; /* number of bytes/regular sector */ + + bootsect_size = 0x00002000 * (sizeof(FPW)/2); + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < 8; ++i) { + info->start[i] = base + (i * bootsect_size); + } + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i - 7) * sect_size); + } + } + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set up sector start address table (uniform sector type) */ + for( i = 0; i < info->sector_count; i++ ) + info->start[i] = base + (i * sect_size); + } + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { + + int sect_size; /* number of bytes/sector */ + + sect_size = 0x00010000 * (sizeof(FPW)/2); + + /* set up sector start address table (top boot sector type) */ + for (i = 0; i < info->sector_count - 3; i++) + info->start[i] = base + (i * sect_size); + i = info->sector_count - 1; + info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2); + info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2); + info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2); + } +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar *bootletter; + char *fmt; + uchar botbootletter[] = "B"; + uchar topbootletter[] = "T"; + uchar botboottype[] = "bottom boot sector"; + uchar topboottype[] = "top boot sector"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + /* check for top or bottom boot, if it applies */ + if (info->flash_id & FLASH_BTYPE) { + boottype = botboottype; + bootletter = botbootletter; + } + else { + boottype = topboottype; + bootletter = topbootletter; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM800T: + fmt = "29LV800B%s (8 Mbit, %s)\n"; + break; + case FLASH_AM640U: + fmt = "29LV641D (64 Mbit, uniform sectors)\n"; + break; + case FLASH_28F800C3B: + case FLASH_28F800C3T: + fmt = "28F800C3%s (8 Mbit, %s)\n"; + break; + case FLASH_INTEL800B: + case FLASH_INTEL800T: + fmt = "28F800B3%s (8 Mbit, %s)\n"; + break; + case FLASH_28F160C3B: + case FLASH_28F160C3T: + fmt = "28F160C3%s (16 Mbit, %s)\n"; + break; + case FLASH_INTEL160B: + case FLASH_INTEL160T: + fmt = "28F160B3%s (16 Mbit, %s)\n"; + break; + case FLASH_28F320C3B: + case FLASH_28F320C3T: + fmt = "28F320C3%s (32 Mbit, %s)\n"; + break; + case FLASH_INTEL320B: + case FLASH_INTEL320T: + fmt = "28F320B3%s (32 Mbit, %s)\n"; + break; + case FLASH_28F640C3B: + case FLASH_28F640C3T: + fmt = "28F640C3%s (64 Mbit, %s)\n"; + break; + case FLASH_INTEL640B: + case FLASH_INTEL640T: + fmt = "28F640B3%s (64 Mbit, %s)\n"; + break; + default: + fmt = "Unknown Chip Type\n"; + break; + } + + printf (fmt, bootletter, boottype); + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + /* Write auto select command: read Manufacturer ID */ + + /* Write auto select command sequence and test FLASH answer */ + addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + switch (addr[0] & 0xff) { + + case (uchar)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { + + case (FPW)AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MiB */ + + case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F800C3B: + info->flash_id += FLASH_28F800C3B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F800B3B: + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F160B3B: + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F320B3B: + info->flash_id += FLASH_INTEL320B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F640B3B: + info->flash_id += FLASH_INTEL640B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets((ulong)addr, info); + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ + +static void flash_sync_real_protect(flash_info_t *info) +{ + FPWV *addr = (FPWV *)(info->start[0]); + FPWV *sect; + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F800C3B: + case FLASH_28F800C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + /* check for protected sectors */ + *addr = (FPW)0x00900090; + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but mixed protected and unprotected devices + * within a sector should never happen. + */ + sect = (FPWV *)(info->start[i]); + info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0; + } + + /* Put FLASH back in read mode */ + flash_reset(info); + break; + + case FLASH_AM640U: + case FLASH_AM800T: + default: + /* no hardware protect that we support */ + break; + } +} +#endif + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect; + int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_INTEL800B: + case FLASH_INTEL160B: + case FLASH_INTEL320B: + case FLASH_INTEL640B: + case FLASH_28F800C3B: + case FLASH_28F160C3B: + case FLASH_28F320C3B: + case FLASH_28F640C3B: + case FLASH_AM640U: + case FLASH_AM800T: + break; + case FLASH_UNKNOWN: + default: + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer(0); + last = start; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + + if (info->protect[sect] != 0) /* protected, skip it */ + continue; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr = (FPWV *)(info->start[sect]); + if (intel) { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { + /* must be AMD style if not Intel */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[0x0555] = (FPW)0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW)0x00550055; /* unlock */ + base[0x0555] = (FPW)0x00800080; /* erase mode */ + base[0x0555] = (FPW)0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 50us for AMD, 80us for Intel. + * Let's wait 1 ms. + */ + udelay (1000); + + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + + if (intel) { + /* suspend erase */ + *addr = (FPW)0x00B000B0; + } + + flash_reset(info); /* reset to read mode */ + rcode = 1; /* failed */ + break; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + flash_reset(info); /* reset to read mode */ + } + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } + + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + case FLASH_MAN_INTEL: + res = write_word_intel(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[0x0555] = (FPW)0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW)0x00550055; /* unlock */ + base[0x0555] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for Intel FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + *dest = (FPW)0x00400040; /* program setup */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00B000B0; /* Suspend program */ + res = 1; + } + } + + if (res == 0 && (*dest & (FPW)0x00100010)) + res = 1; /* write failed, time out error is close enough */ + + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + + return (res); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F800C3B: + case FLASH_28F800C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + flash_reset (info); /* make sure in read mode */ + *addr = (FPW) 0x00600060L; /* lock command setup */ + if (prot) + *addr = (FPW) 0x00010001L; /* lock sector */ + else + *addr = (FPW) 0x00D000D0L; /* unlock sector */ + flash_reset (info); /* reset to read mode */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) 0x00900090; + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) 0x00010001; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) 0x00010001) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect (info); + break; + + case FLASH_AM640U: + case FLASH_AM800T: + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif diff --git a/board/sixnet/fpgadata.c b/board/sixnet/fpgadata.c new file mode 100644 index 0000000..2d3a7b3 --- /dev/null +++ b/board/sixnet/fpgadata.c @@ -0,0 +1,1719 @@ + 0xff, 0x87, 0xff, 0x88, 0x7f, 0xff, 0xf9, 0xff, + 0xff, 0xf5, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0xf9, + 0xff, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xcf, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, + 0x7f, 0x7b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x77, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x86, 0xf6, 0xf0, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x0f, 0x7f, + 0xc1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xff, 0xff, 0xf6, 0xf0, 0xff, 0xff, + 0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x0f, 0x7f, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xff, 0xf8, 0xf7, 0x8f, 0xcf, 0xf0, 0xf6, 0xff, + 0xff, 0xef, 0xff, 0xfb, 0x7f, 0x2f, 0x1f, 0x71, + 0xf5, 0xff, 0xff, 0xef, 0x7f, + 0xff, 0x7f, 0xff, 0xf7, 0xf6, 0xfe, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0x7f, 0x77, 0xf7, 0xff, 0xfb, + 0x0f, 0xff, 0xf0, 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xfe, 0xff, 0x8f, 0x7f, 0xf1, + 0xff, 0xff, 0xfa, 0xce, 0xff, 0xfd, 0xff, 0xff, + 0x9f, 0xff, 0x8e, 0xff, 0xf0, 0xbf, 0x7f, 0xf5, + 0xff, 0xef, 0x9f, 0xfd, 0x81, + 0xff, 0xf9, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, + 0xff, 0xef, 0x9f, 0xfb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x7f, + 0xff, 0x77, 0xfa, 0xb6, 0xff, 0x78, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xbf, 0xfd, 0x0f, 0x7f, 0xf1, + 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0xf6, 0xf7, 0xf6, 0x7f, 0xbf, 0xff, 0xff, + 0xff, 0xff, 0xef, 0xbf, 0xf2, 0x7f, 0xef, 0xff, + 0xfe, 0xfb, 0xff, 0xef, 0xff, + 0xff, 0xf7, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xbf, + 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xf7, 0xff, 0xf7, 0xcf, 0x8f, 0xff, 0xf0, + 0xef, 0xf9, 0xfb, 0xff, 0xff, 0xff, 0x9f, 0x0f, + 0x65, 0xe1, 0xfb, 0x7b, 0xf3, + 0xff, 0xf7, 0xf6, 0xfe, 0xff, 0x8f, 0xf6, 0xe8, + 0xf6, 0xf1, 0xff, 0xff, 0xff, 0xf9, 0xff, 0xff, + 0x6f, 0x61, 0xf1, 0xfb, 0xff, + 0xff, 0xde, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff, + 0xf7, 0xbf, 0xff, 0xd4, 0x8f, 0x0f, 0x71, 0xc1, + 0x6f, 0xd1, 0xeb, 0x5f, 0xfd, + 0xff, 0x9f, 0xff, 0xfb, 0xff, 0x8f, 0x9f, 0xf7, + 0x9f, 0xff, 0xf4, 0xb7, 0xfd, 0xff, 0xfe, 0x8f, + 0xbf, 0x71, 0x1f, 0xff, 0x7f, + 0xff, 0xfd, 0x87, 0x87, 0xf0, 0x70, 0x1f, 0xf7, + 0xbf, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0x81, + 0xbf, 0x3e, 0x7f, 0x7f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0x7f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0xff, 0x07, 0xff, 0xf0, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xf7, 0x8d, 0x7f, 0xf1, 0xff, + 0xff, 0x9f, 0x6f, 0xf1, 0xff, + 0xbf, 0x71, 0x87, 0xfe, 0xf0, 0x8f, 0x8f, 0xf0, + 0xfb, 0xcb, 0xff, 0xf0, 0x8f, 0x7f, 0xf1, 0x8f, + 0x1e, 0xe1, 0x7e, 0x91, 0x7f, + 0xbf, 0x1a, 0xff, 0x71, 0xff, 0x9f, 0x8f, 0xf6, + 0xf8, 0xdf, 0xf7, 0xf4, 0xff, 0xff, 0xff, 0x8f, + 0x1f, 0xf0, 0x7f, 0x97, 0xff, + 0xbf, 0x97, 0xff, 0xfb, 0xbf, 0xdf, 0xff, 0xf7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0xdf, + 0xf9, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xdf, 0xff, 0xf1, 0xff, + 0xff, 0x9f, 0xfc, 0xfb, 0xff, 0xf0, 0xfe, 0xff, + 0xff, 0xff, 0x9d, 0xff, 0xf4, 0xcf, 0xff, 0x7f, + 0xf7, 0xff, 0xff, 0xff, 0xcf, + 0xff, 0x97, 0xff, 0xfa, 0xff, 0x8f, 0xf8, 0xf0, + 0xff, 0xff, 0xff, 0xdf, 0xff, 0xfd, 0xff, 0x0f, + 0x7f, 0xe1, 0xff, 0xf1, 0xff, + 0xff, 0x83, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x6f, 0x7f, 0x77, 0x7d, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0x6f, 0xf1, + 0xff, 0xd7, 0xff, 0xfe, 0xff, 0xff, 0x9f, 0xfd, + 0x78, 0xef, 0xff, 0xbf, 0xff, 0xf5, 0xff, 0xff, + 0xbf, 0x0f, 0x79, 0xd1, 0xff, + 0xff, 0xd2, 0xff, 0x72, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xfe, 0x70, 0x9d, 0xff, 0xf4, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xbf, 0x7f, + 0xff, 0x07, 0xff, 0x78, 0xff, 0x9f, 0xff, 0xfe, + 0xff, 0x77, 0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x8f, + 0x7f, 0xe1, 0x0f, 0x71, 0xf1, + 0xff, 0xfe, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0xfd, 0xff, 0xba, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0xef, 0x7f, 0xa1, 0x7f, + 0xff, 0xbd, 0x7f, 0xf7, 0xf9, 0xfd, 0xfb, 0xff, + 0xff, 0x8f, 0xbf, 0xb7, 0x8f, 0xaf, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0x5f, 0xeb, + 0xbf, 0xfd, 0xf8, 0xff, 0xff, 0xfb, 0xff, 0xfb, + 0xff, 0xf7, 0xcf, 0xfb, 0xf0, 0xff, 0xff, 0xdf, + 0xff, 0xff, 0xef, 0x7f, 0xab, + 0xff, 0xfd, 0xfa, 0xbf, 0x8f, 0xbf, 0xca, 0xfe, + 0xff, 0xff, 0xdf, 0x6f, 0xd4, 0xf6, 0x0f, 0x3f, + 0x11, 0xf9, 0xff, 0x7f, 0x8b, + 0xbf, 0xff, 0x8f, 0xff, 0xc0, 0xfb, 0xf5, 0xef, + 0xf7, 0x7f, 0xff, 0xff, 0xfb, 0x7f, 0xff, 0x7f, + 0xff, 0x6f, 0xff, 0xff, 0xff, + 0xbf, 0x87, 0xbb, 0xf8, 0xfb, 0xcf, 0xfe, 0xfe, + 0xff, 0xef, 0xff, 0xfb, 0x7f, 0xff, 0xff, 0x8f, + 0xff, 0xe1, 0x7f, 0x7b, 0xff, + 0xbf, 0x80, 0x89, 0x88, 0xb0, 0xf5, 0xf0, 0xff, + 0xf7, 0xdf, 0xfe, 0x7c, 0x8f, 0x0f, 0x71, 0xe1, + 0xff, 0xf1, 0xe5, 0x0e, 0x2b, + 0xff, 0xff, 0xff, 0xbf, 0xff, 0xcf, 0xf5, 0x9f, + 0xff, 0xff, 0xfe, 0xff, 0x8f, 0x7f, 0x71, 0x8f, + 0xff, 0x91, 0x7f, 0xfb, 0xff, + 0xff, 0x7f, 0x7f, 0xcf, 0x8a, 0xff, 0xf0, 0xff, + 0x57, 0xfe, 0xfb, 0x8f, 0xff, 0xf0, 0xff, 0x7e, + 0xff, 0xff, 0x9a, 0xff, 0xf1, + 0xff, 0xff, 0xcf, 0xb7, 0xce, 0xff, 0xf4, 0xff, + 0xff, 0x7f, 0xf7, 0xfb, 0xff, 0xfe, 0xff, 0x7f, + 0xff, 0xfd, 0xfe, 0x75, 0xfd, + 0xff, 0xef, 0xcf, 0xff, 0xf5, 0xff, 0xf5, 0xff, + 0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff, + 0xcf, 0x7f, 0x31, 0x7f, 0xff, + 0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0f, 0x0f, 0xf1, 0xf1, 0xdf, 0xff, 0xff, + 0xff, 0x9f, 0xff, 0x84, 0x0e, + 0xff, 0xf8, 0x7f, 0xf7, 0x7f, 0xff, 0xff, 0x8f, + 0x8f, 0x80, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0x9f, 0x8e, 0x05, 0x71, + 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0x8f, 0x0f, + 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8e, 0x0f, 0x71, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xf7, 0xff, 0xff, 0x8f, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x7f, 0xf0, 0xff, 0xff, + 0x7f, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x9f, 0xff, 0x8f, 0x7e, + 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0xff, 0x8f, + 0xff, 0x87, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0x8e, 0x7f, 0xf1, + 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x8f, + 0xff, 0xf0, 0x0f, 0xff, 0x70, 0xff, 0x8f, 0x7e, + 0xf1, 0xdf, 0xff, 0xfb, 0x8e, + 0xff, 0x80, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xaf, 0x7f, 0x84, 0xff, 0xf1, 0xff, 0xfe, + 0xff, 0xff, 0xfe, 0x8f, 0x7f, + 0xff, 0x80, 0xff, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x7f, 0xf0, 0xdf, 0xdf, 0xff, 0xdf, 0xff, + 0xff, 0xff, 0x8f, 0x7f, 0xf1, + 0xff, 0xfd, 0xff, 0xff, 0xff, 0x0f, 0xff, 0x80, + 0xff, 0xf0, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0x8e, + 0x0f, 0x01, 0x71, 0xf1, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0xff, 0x8f, 0x8f, 0xd0, 0xf0, 0xdf, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xfe, + 0xff, 0xdf, 0xff, 0xfb, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xaf, 0xfe, 0xf5, 0xff, 0xff, + 0xff, 0xff, 0x0f, 0x8f, 0xf0, 0x80, 0xff, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0x1f, 0xaf, 0x71, 0xa7, + 0x6f, 0xf5, 0xfe, 0xff, 0xff, + 0xff, 0x77, 0x79, 0x8f, 0xff, 0xf0, 0x8f, 0xff, + 0x00, 0xff, 0xd0, 0x4f, 0x3d, 0xf0, 0xf7, 0xfd, + 0x8f, 0x7f, 0x81, 0x7f, 0xd1, + 0xff, 0xcd, 0xff, 0xff, 0x8f, 0x0f, 0x70, 0xf0, + 0xff, 0x7f, 0x7f, 0xff, 0xff, 0xdb, 0x8d, 0x4b, + 0x73, 0xf9, 0xff, 0xdf, 0xff, + 0x3f, 0xfc, 0xff, 0x8f, 0xff, 0xf2, 0x8f, 0x8f, + 0x70, 0x7a, 0x3f, 0xbc, 0xf7, 0xdb, 0xff, 0xf9, + 0xff, 0xff, 0xff, 0xff, 0xee, + 0xff, 0xe8, 0xf7, 0x8f, 0xfd, 0x80, 0xff, 0xf0, + 0x9f, 0xa5, 0x7a, 0xf4, 0x6f, 0x3f, 0xcf, 0x07, + 0x6a, 0xe1, 0xff, 0x8f, 0x7f, + 0xff, 0xff, 0x77, 0xf1, 0x8f, 0x8f, 0xf0, 0xf0, + 0xbf, 0xff, 0xe7, 0x7f, 0x8f, 0x24, 0x03, 0x77, + 0xf3, 0xff, 0xfe, 0xff, 0xff, + 0xbf, 0x9f, 0x77, 0x8b, 0xff, 0xf0, 0xff, 0xef, + 0x7d, 0x7f, 0xff, 0x9f, 0xeb, 0x3d, 0xff, 0xf7, + 0xff, 0xfb, 0xfe, 0xff, 0xdf, + 0xff, 0xff, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbb, 0x5d, + 0xf5, 0xbb, 0xef, 0xff, 0xff, + 0xff, 0x7f, 0x8f, 0x8f, 0xf0, 0xf8, 0xff, 0xff, + 0xf7, 0x7f, 0xff, 0xff, 0xaf, 0xbf, 0x75, 0xb7, + 0xff, 0xf7, 0xff, 0xff, 0xff, + 0xff, 0x7f, 0x87, 0x7f, 0xf8, 0xff, 0xf7, 0xf7, + 0x8f, 0xff, 0xf0, 0x7f, 0xf7, 0xff, 0xad, 0xff, + 0xf7, 0xee, 0x9f, 0xff, 0xf5, + 0xff, 0xf8, 0x07, 0xff, 0x80, 0x8f, 0x80, 0x80, + 0xf0, 0x8f, 0x7f, 0x70, 0x4f, 0x0f, 0x79, 0xf1, + 0xfd, 0xff, 0xef, 0x8f, 0x7f, + 0xbf, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xd0, 0xbf, 0xdb, 0xe5, + 0x3b, 0xfe, 0xf7, 0xff, 0x8f, + 0xff, 0xff, 0x8f, 0x77, 0x80, 0xff, 0xf0, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xbd, 0xef, 0x07, 0x7f, + 0xf1, 0xfe, 0xff, 0xfe, 0xff, + 0x7f, 0x7f, 0xff, 0xf7, 0xf7, 0xff, 0xf7, 0x8f, + 0xbf, 0x70, 0xf5, 0x7f, 0xff, 0xef, 0x3f, 0x7d, + 0xf7, 0xff, 0xff, 0xfe, 0xfe, + 0xff, 0x97, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, + 0x7e, 0xff, 0xff, 0x9f, 0xdf, 0xf7, 0x3b, 0xff, + 0xf7, 0xff, 0x7f, 0xfe, 0xff, + 0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x1f, 0x1f, 0xf1, 0xf1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x80, 0x0e, + 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f, + 0x9f, 0x80, 0xe1, 0xf1, 0xff, 0xff, 0xef, 0xff, + 0xfe, 0x9f, 0x0e, 0x01, 0x71, + 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xef, + 0xfe, 0xef, 0xff, 0x8f, 0x0f, + 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x9f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8e, 0x0f, 0x71, + 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xef, 0xff, 0xff, 0xef, 0xfe, 0xef, + 0xef, 0xff, 0xff, 0xef, 0xff, + 0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x7f, 0xe0, 0xff, 0xff, + 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7e, + 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xef, 0xff, 0xff, + 0xff, 0xff, 0xee, 0xef, 0x9f, + 0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xe0, 0xff, 0xff, + 0xff, 0xef, 0x8e, 0x7f, 0xf1, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xef, 0xff, 0xfe, 0x8f, 0x7f, + 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xdf, + 0xff, 0xf0, 0x0f, 0xff, 0x70, 0xff, 0x8f, 0x7e, + 0xe1, 0xdf, 0xff, 0xf7, 0x8e, + 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xff, + 0xff, 0xef, 0xfe, 0x8f, 0x7f, + 0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xff, 0x7f, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0x7e, 0xf1, + 0xff, 0xff, 0xff, 0xf7, 0xff, 0x0f, 0x8f, 0x80, + 0xf7, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9e, + 0x6f, 0x91, 0x71, 0xf1, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xef, 0xff, 0xff, + 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xdf, 0x8f, + 0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe, + 0xff, 0xef, 0xff, 0xd7, 0xff, + 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0x8f, 0xff, + 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, + 0xff, 0xfe, 0xf9, 0xdf, 0xff, + 0xff, 0xff, 0x8f, 0xbf, 0xf7, 0x9f, 0xf8, 0xf0, + 0xff, 0xff, 0x77, 0xff, 0x0e, 0x1f, 0x61, 0x81, + 0x7f, 0xf1, 0xfe, 0xff, 0xff, + 0xff, 0x7f, 0xb9, 0xcf, 0xff, 0xff, 0x0f, 0xff, + 0x00, 0xff, 0xd0, 0x7f, 0x75, 0x8b, 0x7f, 0xf1, + 0x8f, 0x7f, 0x80, 0x7e, 0x91, + 0xff, 0xbf, 0xdf, 0xff, 0xa7, 0x47, 0x70, 0xf7, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0x0f, + 0x61, 0xf1, 0xef, 0xff, 0xff, + 0x7f, 0xfe, 0xef, 0x5f, 0xf7, 0xff, 0xff, 0xff, + 0xff, 0xe7, 0xb7, 0xfc, 0xeb, 0x9f, 0x7f, 0xf1, + 0x9f, 0x0f, 0x71, 0xf1, 0xee, + 0xff, 0xf0, 0xf7, 0x3f, 0xef, 0x97, 0xf8, 0xe8, + 0xff, 0x9f, 0x7f, 0xf0, 0x7f, 0x9f, 0x6f, 0x91, + 0x7e, 0xf1, 0x9f, 0x8f, 0x57, + 0xff, 0xff, 0x26, 0xb9, 0xb8, 0xff, 0xf0, 0xff, + 0xff, 0xff, 0xf7, 0x7f, 0x6f, 0xf4, 0x9f, 0x1f, + 0x71, 0xe1, 0xfe, 0x7f, 0xff, + 0xbf, 0xff, 0x71, 0xbb, 0xe8, 0xff, 0xff, 0xf8, + 0xbf, 0xff, 0xaf, 0xff, 0xf8, 0x9d, 0x6f, 0xf1, + 0xbf, 0xff, 0xb7, 0xff, 0xbd, + 0xbf, 0xff, 0xff, 0xdf, 0x97, 0xc7, 0xf7, 0xf0, + 0xff, 0xff, 0x93, 0xff, 0xff, 0xef, 0xcf, 0x5f, + 0xf1, 0xf7, 0xdf, 0xf5, 0x9f, + 0xff, 0xff, 0x87, 0xbf, 0xe0, 0xbf, 0xf7, 0xff, + 0xf7, 0x7f, 0xff, 0xff, 0x8f, 0x5f, 0x21, 0xb1, + 0xff, 0x6d, 0xff, 0xef, 0xff, + 0xff, 0xff, 0xd7, 0xff, 0xb8, 0xff, 0xff, 0xff, + 0x3f, 0xef, 0xf0, 0x7f, 0xd7, 0x7f, 0xf1, 0xff, + 0xef, 0xee, 0xbf, 0x7f, 0xf1, + 0xff, 0xf8, 0x47, 0x0f, 0xc7, 0xf0, 0x7f, 0xf0, + 0xf0, 0x90, 0x7f, 0x70, 0x8f, 0x2f, 0xc1, 0x0f, + 0x11, 0x1f, 0xef, 0xaf, 0x7f, + 0xbf, 0x7f, 0xf0, 0x9f, 0xe7, 0xf7, 0x38, 0xff, + 0xff, 0xff, 0x8f, 0x7f, 0xf0, 0xaf, 0xff, 0xff, + 0xbf, 0xfe, 0xfd, 0xdf, 0x8f, + 0xff, 0xff, 0xbf, 0xf7, 0x8f, 0xff, 0xf7, 0xff, + 0xeb, 0xff, 0xff, 0xff, 0x8d, 0x3f, 0x81, 0x7f, + 0xd1, 0xfe, 0xdf, 0xfe, 0xff, + 0x7f, 0xff, 0xff, 0xdf, 0xa8, 0xff, 0xf0, 0xff, + 0xff, 0xf0, 0xf7, 0xff, 0xff, 0xff, 0xef, 0xef, + 0xef, 0x9f, 0x7f, 0x7e, 0xfe, + 0xff, 0xff, 0xef, 0xff, 0xa7, 0x77, 0xff, 0xff, + 0xef, 0xff, 0xff, 0xdf, 0xff, 0xe7, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0xff, + 0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xbf, + 0xff, 0x0f, 0x0f, 0xf1, 0xe1, 0xff, 0xff, 0xef, + 0xef, 0xff, 0xff, 0x8e, 0x0e, + 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f, + 0x8f, 0x80, 0xf1, 0xf1, 0xef, 0xaf, 0xaf, 0xff, + 0xee, 0xdf, 0x0e, 0x01, 0x71, + 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff, + 0xef, 0x8f, 0x9f, 0xf1, 0xe1, 0xff, 0xaf, 0xef, + 0xfe, 0xff, 0xff, 0x8f, 0x0f, + 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x9f, 0x9f, 0xf1, 0xf1, 0xef, 0xff, 0xaf, 0xff, + 0xff, 0xff, 0x8e, 0x0f, 0x71, + 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xef, 0xbf, 0xef, 0xff, + 0xef, 0xbf, 0xff, 0xef, 0xff, + 0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xfe, + 0xcf, 0x3f, 0xf0, 0xff, 0xff, + 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, + 0xff, 0x88, 0xff, 0xf0, 0xff, 0xff, 0xef, 0xfe, + 0xff, 0xff, 0xff, 0x8f, 0x6e, + 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xe0, 0xff, 0xef, 0xff, + 0xff, 0xff, 0xee, 0xef, 0x9f, + 0xff, 0x8f, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xa0, 0xff, 0xfe, + 0xff, 0xbf, 0x8e, 0x6f, 0xf1, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x6f, + 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xcf, + 0xff, 0xb0, 0x0f, 0xaf, 0x70, 0xff, 0x8f, 0x7e, + 0xf1, 0xff, 0xff, 0xf1, 0x9e, + 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xef, 0x8f, 0x7f, 0x90, 0xff, 0xf1, 0xff, 0xff, + 0xff, 0xaf, 0xfe, 0x8f, 0x7f, + 0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x3f, 0xdf, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x9f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xbf, 0x7e, 0xf1, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0x0f, 0xaf, 0x80, + 0xf0, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xde, + 0x0f, 0x91, 0x7f, 0xf1, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xfe, + 0xff, 0xff, 0xbf, 0xff, 0xfb, + 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xdf, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0xff, 0xff, 0xdf, 0xbf, 0xff, 0xef, 0xff, + 0xff, 0xaf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xdf, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xaf, 0xff, + 0xf0, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, + 0xdf, 0xfe, 0xfe, 0xff, 0xff, + 0xff, 0xff, 0x0f, 0x8f, 0xf0, 0x8f, 0xff, 0xf0, + 0xf9, 0xff, 0xf7, 0xff, 0x0f, 0x5f, 0x29, 0x89, + 0x77, 0xf1, 0xfa, 0xff, 0xde, + 0xff, 0xc3, 0x3f, 0x4b, 0x7f, 0xe9, 0x0f, 0xff, + 0x00, 0xff, 0x90, 0x0f, 0xd7, 0xff, 0x7f, 0xf9, + 0x8f, 0x7f, 0x81, 0x7f, 0x81, + 0xff, 0xff, 0xfb, 0x7d, 0x80, 0x46, 0x76, 0xf0, + 0xff, 0xff, 0x6f, 0xff, 0xff, 0xad, 0xcf, 0x3f, + 0x71, 0xf9, 0xff, 0xff, 0xff, + 0x3f, 0xba, 0xff, 0xc7, 0xf7, 0xb9, 0xcf, 0xde, + 0x77, 0xb7, 0x77, 0xfe, 0xff, 0xbf, 0x6f, 0xf9, + 0xff, 0x7e, 0x79, 0xb9, 0xfe, + 0xff, 0xe4, 0xf7, 0x8f, 0xfe, 0x07, 0xfe, 0xf8, + 0xff, 0x89, 0x7f, 0xe8, 0x7f, 0xd7, 0x7f, 0x99, + 0x76, 0xf1, 0xff, 0x0f, 0x7b, + 0xbf, 0xff, 0xb6, 0xb9, 0x8f, 0xdf, 0xf6, 0xff, + 0xff, 0xf7, 0xff, 0xff, 0x8f, 0xdd, 0x87, 0x7f, + 0x71, 0xf1, 0xfe, 0xff, 0xff, + 0xff, 0x7f, 0xf1, 0x8a, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0xff, 0xcf, 0xfb, 0xe8, 0x9d, 0x77, 0xa9, + 0xff, 0x77, 0xda, 0x7f, 0xff, + 0xbf, 0xff, 0xf7, 0xf7, 0x86, 0xe5, 0xf0, 0xe0, + 0xff, 0xff, 0xbf, 0xff, 0xff, 0xef, 0x8f, 0x7f, + 0xbd, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0xef, 0x86, 0x8f, 0xf0, 0xff, 0xf6, 0x9f, + 0xff, 0x7f, 0xff, 0xff, 0xcf, 0x1f, 0x71, 0xdd, + 0x7f, 0xe1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xc7, 0xf7, 0xb9, 0xff, 0xff, 0xfa, + 0x3f, 0xef, 0xf0, 0xff, 0xef, 0x7f, 0xd5, 0xff, + 0xfb, 0xff, 0xf7, 0x6e, 0xf1, + 0xff, 0xfc, 0xc7, 0xbf, 0xc8, 0xc0, 0x59, 0xff, + 0xdf, 0xff, 0x7b, 0xf0, 0xa7, 0x1f, 0xa9, 0x77, + 0x79, 0x71, 0x11, 0xff, 0x79, + 0xbf, 0xfb, 0x70, 0xbf, 0xff, 0xf9, 0x37, 0xbe, + 0xff, 0xff, 0x8f, 0x7f, 0xf4, 0x9f, 0xff, 0xff, + 0xd7, 0x7f, 0xff, 0xff, 0xaf, + 0xff, 0xff, 0x9e, 0xf7, 0x9f, 0xfe, 0xe4, 0xff, + 0xcf, 0xcf, 0xff, 0xff, 0xdf, 0x7f, 0x8d, 0x7f, + 0xf9, 0xfa, 0xdf, 0x9f, 0xef, + 0x7f, 0xef, 0xff, 0xff, 0xbe, 0xfd, 0xd2, 0xdf, + 0xff, 0x7e, 0xf7, 0xff, 0xff, 0xab, 0x97, 0xef, + 0xf3, 0xfe, 0x7f, 0x71, 0xfe, + 0xff, 0x9f, 0xff, 0xff, 0xb6, 0xfb, 0xf7, 0xff, + 0xff, 0xf7, 0xff, 0xbf, 0xff, 0xb7, 0xdb, 0xff, + 0xbb, 0xef, 0xff, 0xff, 0xff, + 0x3f, 0x68, 0xfe, 0xfd, 0xfb, 0xff, 0xff, 0xef, + 0xf1, 0x1e, 0x1b, 0xf1, 0xf5, 0xff, 0xff, 0xff, + 0xff, 0x9f, 0xfb, 0x9a, 0x36, + 0xff, 0xfc, 0x7d, 0xff, 0x73, 0xf7, 0xff, 0xaf, + 0x9f, 0x94, 0xfd, 0xf5, 0xff, 0xf7, 0xff, 0xfb, + 0xfe, 0xef, 0x3e, 0x07, 0x4d, + 0xbf, 0xe8, 0xf8, 0xff, 0x7f, 0xff, 0xf7, 0xf7, + 0xf1, 0x8f, 0xaf, 0xd1, 0xf7, 0xf9, 0xfd, 0xff, + 0xf8, 0xdf, 0xfb, 0x8f, 0x2f, + 0xff, 0xf8, 0x7f, 0xff, 0xf7, 0xf7, 0xff, 0xff, + 0xa7, 0xaf, 0xf7, 0xf3, 0xdf, 0xff, 0xfd, 0xff, + 0xfd, 0xff, 0xae, 0x0f, 0x71, + 0xff, 0xff, 0xff, 0xf9, 0xff, 0xff, 0xf3, 0xf3, + 0xff, 0xf3, 0xff, 0xf7, 0xfb, 0xf3, 0xff, 0xff, + 0xff, 0xeb, 0xff, 0xf3, 0xdb, + 0xff, 0xeb, 0x7b, 0xfb, 0xf7, 0xff, 0x8b, 0xf7, + 0xfc, 0xf7, 0xfb, 0xff, 0xfb, 0xf3, 0xff, 0xff, + 0x8b, 0x7f, 0xd4, 0xfb, 0xff, + 0x7f, 0xec, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xf7, + 0xff, 0x8e, 0xff, 0xf8, 0xf7, 0xfb, 0xfd, 0xff, + 0xfd, 0x9f, 0xf7, 0x9f, 0x7e, + 0xbf, 0xfb, 0x7c, 0xff, 0xf7, 0xff, 0xff, 0xfb, + 0xfb, 0xf1, 0x8f, 0xf3, 0xdc, 0xf7, 0xfd, 0xff, + 0xe9, 0xeb, 0xef, 0xc3, 0xb7, + 0xff, 0x07, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xf7, + 0x8f, 0xff, 0xf4, 0x8f, 0xfb, 0xfc, 0xff, 0xef, + 0xff, 0xf7, 0x8f, 0x7f, 0xd1, + 0xff, 0xfa, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, + 0xf3, 0x89, 0xef, 0xf8, 0xff, 0xf7, 0xff, 0xef, + 0xef, 0xf7, 0xf3, 0xab, 0x7f, + 0x3f, 0xf9, 0x7e, 0xf9, 0x8f, 0x7f, 0xf0, 0xef, + 0xff, 0xfc, 0x1b, 0xff, 0x7c, 0xff, 0x8f, 0x6e, + 0xf1, 0xf7, 0x73, 0xff, 0xa6, + 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xf9, 0x8f, 0x7f, 0x84, 0xff, 0xf1, 0xff, 0xff, + 0xff, 0xff, 0xfa, 0x8f, 0x7f, + 0xff, 0x96, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, + 0x57, 0xaf, 0xfb, 0x85, 0x7f, 0xf4, 0xff, 0xfe, + 0xef, 0xff, 0xef, 0xbf, 0x53, + 0xff, 0x7d, 0xff, 0xff, 0xe3, 0xff, 0xff, 0xff, + 0x97, 0x71, 0xf8, 0xff, 0xff, 0xff, 0xdb, 0xef, + 0xef, 0xe7, 0x97, 0x72, 0xfd, + 0xff, 0xff, 0xff, 0xff, 0xf3, 0x0f, 0xe3, 0x86, + 0xf0, 0xf4, 0xfb, 0xff, 0xdf, 0xff, 0xfb, 0x8e, + 0x0b, 0xa5, 0x72, 0xf9, 0xff, + 0xff, 0xfb, 0xff, 0xff, 0xf7, 0xff, 0xf3, 0xff, + 0xf7, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xfb, 0xee, + 0xfb, 0xff, 0xef, 0xff, 0xff, + 0xbf, 0x82, 0xf8, 0xf8, 0xf7, 0x7f, 0xf7, 0xff, + 0xff, 0xef, 0x87, 0x87, 0xf0, 0xf0, 0xfb, 0xff, + 0xfb, 0xf7, 0xef, 0xef, 0x87, + 0xff, 0xf6, 0xff, 0xfa, 0xf1, 0xef, 0xf3, 0xf7, + 0x7f, 0xff, 0xff, 0xef, 0xff, 0xf7, 0xff, 0xff, + 0xfb, 0xf7, 0xff, 0xfe, 0xff, + 0xff, 0xf7, 0xfb, 0xf2, 0xf3, 0xff, 0xf1, 0xf7, + 0xff, 0xef, 0xf7, 0xef, 0xf7, 0xf7, 0xff, 0xfe, + 0xff, 0xff, 0xef, 0xff, 0xe7, + 0xff, 0xfb, 0xfb, 0xff, 0xf5, 0xef, 0xf7, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0x77, 0xff, 0xff, 0xfe, + 0xff, 0xf7, 0xff, 0xef, 0xef, + 0xff, 0xff, 0xff, 0xff, 0xf7, 0xef, 0xe5, 0xff, + 0xfe, 0x61, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x9f, 0xef, 0xef, 0xf3, 0xf7, + 0xff, 0xff, 0x0f, 0x9f, 0xfa, 0x87, 0xff, 0xf6, + 0xeb, 0xff, 0xff, 0xef, 0x0f, 0x6f, 0xfd, 0x0d, + 0x53, 0xf1, 0xf3, 0xff, 0xff, + 0xbf, 0x1b, 0x7f, 0x96, 0xfe, 0xff, 0x8f, 0xfb, + 0x00, 0xff, 0xb0, 0x17, 0x7c, 0x8f, 0xff, 0xfd, + 0x8f, 0x7f, 0x81, 0x7e, 0xf1, + 0xff, 0xfd, 0xed, 0xee, 0x9e, 0x0b, 0x79, 0xff, + 0xfb, 0x77, 0x5b, 0xff, 0x9f, 0xff, 0x4f, 0x0f, + 0x71, 0xf0, 0xdb, 0xff, 0xf7, + 0x7f, 0xe7, 0xef, 0x18, 0xff, 0xff, 0x9d, 0x8e, + 0x67, 0xbf, 0x4f, 0xff, 0xff, 0xae, 0xff, 0xf1, + 0xeb, 0xef, 0xfd, 0xad, 0xf6, + 0xff, 0xfc, 0xf7, 0x1f, 0xff, 0x9f, 0xfb, 0xfc, + 0xff, 0x8f, 0x77, 0xec, 0x5f, 0x6f, 0xdf, 0x25, + 0x7e, 0xd9, 0xe6, 0x97, 0x3f, + 0xff, 0xf7, 0x67, 0xec, 0x92, 0xbe, 0xf1, 0xfb, + 0xff, 0x7f, 0xdf, 0x7b, 0x5e, 0x7d, 0xe7, 0x5f, + 0xf1, 0xf1, 0xfb, 0xff, 0xf7, + 0xbf, 0xf7, 0x71, 0x9a, 0xfd, 0xff, 0xf7, 0xfb, + 0x5f, 0x7f, 0xaf, 0xdf, 0xf9, 0xe7, 0x77, 0xdd, + 0x6f, 0xf7, 0xbb, 0xff, 0x8b, + 0xbf, 0xff, 0x77, 0xff, 0x93, 0xfe, 0xf8, 0xfe, + 0xbf, 0xfe, 0xbf, 0xff, 0xff, 0xbf, 0xab, 0x7f, + 0xfd, 0xff, 0xcf, 0x67, 0xff, + 0xff, 0x7f, 0x07, 0x9f, 0xe4, 0xdb, 0xff, 0xf1, + 0xf7, 0x7f, 0xff, 0xff, 0x8f, 0x6f, 0xd1, 0x6d, + 0x73, 0xff, 0xff, 0xfb, 0xff, + 0xff, 0x6f, 0x9f, 0x7b, 0xfd, 0xff, 0xf6, 0xfd, + 0x27, 0xff, 0xfc, 0xff, 0xaf, 0xff, 0xfd, 0xfe, + 0x7f, 0xdf, 0xff, 0x7f, 0xef, + 0xff, 0xfe, 0x81, 0xe7, 0x93, 0x91, 0x83, 0x85, + 0xef, 0x8f, 0x7f, 0x74, 0x8d, 0x1b, 0x2d, 0xe2, + 0xcd, 0xe5, 0xb5, 0x9f, 0x77, + 0xbf, 0x7f, 0xe4, 0xef, 0xff, 0xf7, 0xdb, 0xfd, + 0x7f, 0xfe, 0xab, 0x7f, 0xfc, 0xbf, 0xff, 0xde, + 0x77, 0xfb, 0xdf, 0xef, 0xbf, + 0xff, 0xff, 0x1e, 0x7f, 0x8f, 0xff, 0x92, 0xf3, + 0xdf, 0x7b, 0xff, 0x7b, 0xff, 0xdb, 0x3d, 0x5f, + 0xf9, 0xf6, 0xff, 0xf2, 0xf7, + 0x7f, 0x7f, 0xff, 0xff, 0xef, 0xd2, 0xf0, 0xb7, + 0xfb, 0x7f, 0xfc, 0x77, 0xd7, 0x3f, 0xc7, 0x7f, + 0xf3, 0xe7, 0xff, 0xfd, 0xfe, + 0xff, 0xff, 0xef, 0x7b, 0xef, 0xf5, 0xda, 0xff, + 0x7c, 0xff, 0xff, 0xff, 0xff, 0x7b, 0xeb, 0xfb, + 0xef, 0xff, 0xef, 0xff, 0xff, + 0x3f, 0x60, 0xfc, 0xfb, 0xf7, 0xff, 0xff, 0xff, + 0xfb, 0x00, 0x0f, 0xf1, 0xf5, 0xfb, 0xff, 0xff, + 0xff, 0xff, 0xf3, 0x86, 0x3e, + 0xff, 0xf8, 0x7f, 0xfb, 0x73, 0xff, 0xff, 0x9f, + 0xab, 0x8c, 0xf5, 0xd1, 0xff, 0xfb, 0xff, 0xff, + 0xfe, 0xeb, 0x36, 0x0d, 0x49, + 0xbf, 0xf0, 0xfc, 0xfb, 0x73, 0xff, 0xf3, 0xff, + 0xff, 0xab, 0xa7, 0xf1, 0xf9, 0xff, 0xf7, 0xdf, + 0xfa, 0xfb, 0xff, 0xa7, 0x3f, + 0xff, 0xf8, 0x7f, 0xff, 0xfb, 0xfb, 0xfb, 0xff, + 0xaf, 0x8f, 0xf9, 0xf9, 0xdf, 0xdf, 0xf7, 0xdb, + 0xff, 0xff, 0xba, 0x2f, 0x69, + 0xff, 0xe7, 0xfb, 0xfb, 0xff, 0xff, 0xff, 0xfb, + 0xff, 0xfb, 0xd7, 0xff, 0xdf, 0xf7, 0xd7, 0xdf, + 0xf3, 0xdb, 0xff, 0xdb, 0xff, + 0xff, 0xe3, 0x7b, 0xf9, 0xfb, 0xff, 0x8f, 0xfb, + 0xf8, 0xff, 0xff, 0xef, 0xdf, 0xf3, 0xd7, 0xdf, + 0xa3, 0x5b, 0xc4, 0xfb, 0xef, + 0x7f, 0xe0, 0xfd, 0xfb, 0xfb, 0xff, 0xfb, 0xeb, + 0xff, 0x8c, 0xeb, 0xf0, 0xd3, 0xff, 0xd7, 0xff, + 0xf7, 0xbb, 0x7f, 0x8f, 0x7e, + 0xbf, 0xfb, 0x6c, 0xfb, 0xfb, 0xff, 0xfb, 0xff, + 0xfb, 0xf3, 0x8b, 0xf3, 0xf4, 0xf7, 0xd7, 0xff, + 0xf3, 0xff, 0xfe, 0xc2, 0xbf, + 0xff, 0x87, 0x7f, 0xfa, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf4, 0xff, 0xdf, + 0xff, 0xfb, 0x8f, 0x7f, 0xc5, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0xf3, 0x87, 0xef, 0xfc, 0xfd, 0xfb, 0xff, 0xff, + 0xdf, 0xff, 0xfb, 0xab, 0x7f, + 0x3f, 0xf3, 0xfa, 0xf9, 0x8f, 0x7f, 0xf0, 0xeb, + 0xfb, 0xec, 0x1f, 0xcf, 0x7e, 0xff, 0x8f, 0x5e, + 0xd1, 0xbf, 0xff, 0xfe, 0xaa, + 0xff, 0x80, 0x7d, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xf7, 0x8f, 0x5f, 0x8c, 0xff, 0xf1, 0xff, 0xff, + 0xff, 0xff, 0xfa, 0x9f, 0x6f, + 0xff, 0x9a, 0xfd, 0xfc, 0xff, 0xff, 0xff, 0xff, + 0x6f, 0xbf, 0xd7, 0x89, 0x7f, 0xf4, 0xff, 0xfe, + 0xff, 0xff, 0xdf, 0xbf, 0x6f, + 0xff, 0xfd, 0xff, 0xff, 0xef, 0xff, 0xfb, 0xff, + 0x2b, 0x73, 0xf0, 0xf3, 0xff, 0xff, 0xc3, 0xff, + 0xff, 0xff, 0x8b, 0x62, 0xfd, + 0xff, 0xef, 0xff, 0xff, 0xfb, 0x0f, 0x8b, 0x8e, + 0xf0, 0xdc, 0xf7, 0xff, 0xff, 0xff, 0xfb, 0xae, + 0x43, 0xa9, 0x73, 0xf9, 0xfb, + 0x7f, 0xf9, 0xff, 0xff, 0xfd, 0xff, 0xf9, 0xff, + 0xfb, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xf3, 0xfe, + 0xf3, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0x87, 0xf8, 0xf8, 0xf9, 0x7f, 0xf9, 0xff, + 0xff, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, 0xf3, 0xff, + 0xf3, 0xfb, 0xff, 0xff, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, + 0xfb, 0xef, 0xff, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xf7, 0xf9, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xfe, + 0xf3, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xf1, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xfe, + 0xfb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xf1, 0xff, 0x85, 0xff, + 0xfe, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, + 0xf3, 0xde, 0xff, 0xf3, 0xff, + 0xbf, 0xff, 0x0f, 0x9f, 0xfa, 0x9f, 0xeb, 0xf2, + 0xe7, 0xff, 0x7b, 0xff, 0x4f, 0x73, 0x31, 0x81, + 0x5f, 0xf1, 0xfe, 0xff, 0xbf, + 0xff, 0xaf, 0x7f, 0x94, 0xfb, 0xfe, 0x8f, 0xff, + 0x00, 0xff, 0xf0, 0xef, 0xef, 0x5f, 0xfb, 0xf5, + 0x8f, 0x7f, 0x81, 0x5e, 0xf1, + 0xff, 0xf9, 0xff, 0xef, 0x86, 0x0f, 0x71, 0xf6, + 0xff, 0x7f, 0x7f, 0x97, 0xcf, 0xfd, 0xbf, 0x5f, + 0xf9, 0xf1, 0xf3, 0xff, 0xff, + 0x3f, 0xdb, 0xed, 0x1e, 0xff, 0xf6, 0x95, 0x9a, + 0x6f, 0x3d, 0xff, 0xf8, 0xfb, 0xdf, 0xf7, 0xfd, + 0xfb, 0xf7, 0xfd, 0xed, 0xde, + 0x7f, 0xf0, 0xf7, 0x87, 0x7f, 0x9b, 0xff, 0xec, + 0x9f, 0xbf, 0x7f, 0xcd, 0x7f, 0xf7, 0x3b, 0xad, + 0x7e, 0xf8, 0xff, 0xbb, 0x79, + 0xff, 0xff, 0xe3, 0x7c, 0x01, 0x8d, 0xf5, 0xfb, + 0xe7, 0xf7, 0xff, 0xff, 0x9e, 0x7d, 0x0f, 0x7f, + 0xf1, 0xcd, 0xfe, 0xf7, 0xff, + 0x3f, 0xd7, 0xf4, 0x9a, 0xf7, 0xed, 0xff, 0xf3, + 0xb7, 0xff, 0xef, 0xff, 0xbd, 0xe7, 0x5f, 0xbd, + 0xff, 0xef, 0xfe, 0x7f, 0xf1, + 0x3f, 0xff, 0xe7, 0xff, 0xcf, 0xfa, 0xf8, 0xff, + 0xff, 0xdf, 0xbf, 0xfe, 0xdf, 0xff, 0xd3, 0x1f, + 0xfd, 0xef, 0x7f, 0xff, 0xcf, + 0x7f, 0xff, 0x93, 0xdf, 0xf0, 0xef, 0xf3, 0xd4, + 0x77, 0x6f, 0xff, 0xff, 0xbf, 0x7f, 0x7d, 0xfd, + 0x7f, 0x7d, 0xff, 0xff, 0xf7, + 0xff, 0xf7, 0xdf, 0xfb, 0xbc, 0xef, 0xff, 0xfd, + 0xff, 0xff, 0xfc, 0x7f, 0xb7, 0xff, 0xfd, 0x5f, + 0xcf, 0xff, 0xef, 0x7f, 0xfd, + 0xff, 0xee, 0x87, 0xef, 0x92, 0xf0, 0x7e, 0xe5, + 0xbf, 0x8f, 0x7f, 0x60, 0xd9, 0xdb, 0x71, 0xb3, + 0x2d, 0x49, 0x6c, 0x29, 0x7f, + 0xbf, 0xff, 0xe4, 0x6f, 0xf3, 0xfa, 0x57, 0xfd, + 0xff, 0xfe, 0xb7, 0x7f, 0xfc, 0xff, 0x73, 0xdf, + 0xf3, 0x7f, 0xfd, 0xff, 0xbf, + 0xff, 0xef, 0x8b, 0x7f, 0x8f, 0xff, 0xf2, 0xff, + 0xff, 0xf7, 0xfb, 0xff, 0xff, 0xdf, 0xed, 0xef, + 0xf1, 0xf7, 0xfd, 0xdf, 0xf7, + 0xff, 0xff, 0xff, 0xf7, 0xe7, 0xe6, 0xf1, 0xff, + 0xdf, 0xfb, 0xe9, 0xfe, 0xbf, 0xff, 0xbf, 0x5f, + 0xff, 0xbf, 0x0e, 0x75, 0xfa, + 0xff, 0xff, 0xff, 0x6f, 0xfb, 0xf9, 0xff, 0xff, + 0xf3, 0xff, 0xfb, 0xbf, 0xef, 0xff, 0xf3, 0x7f, + 0xff, 0xff, 0xff, 0xfb, 0xff, + 0xff, 0x38, 0xf8, 0xf7, 0xff, 0xff, 0xdf, 0x9f, + 0xf7, 0x0b, 0x0f, 0xf5, 0xf5, 0xff, 0xff, 0xff, + 0xbf, 0xf7, 0xf3, 0x8e, 0x0e, + 0xbf, 0xe8, 0x6f, 0xef, 0x7f, 0xff, 0xdf, 0xdf, + 0xef, 0x88, 0xf5, 0x91, 0xfb, 0xff, 0xff, 0xbf, + 0xfe, 0xbf, 0xa6, 0x81, 0x71, + 0xff, 0xf0, 0xf8, 0xff, 0x67, 0xef, 0xff, 0xb7, + 0xf7, 0x8f, 0x2f, 0xd1, 0x41, 0xff, 0xcf, 0x5f, + 0xfe, 0xff, 0x7b, 0x8f, 0x9f, + 0xff, 0xf8, 0x6f, 0xef, 0xf7, 0xe7, 0xff, 0xff, + 0xbf, 0x8f, 0xd1, 0xf1, 0xcf, 0xdf, 0xcf, 0xdf, + 0xff, 0xff, 0x9f, 0x8f, 0xe1, + 0xff, 0xe7, 0xff, 0xf7, 0xe7, 0x6f, 0xf7, 0xe7, + 0xe7, 0x77, 0xef, 0xef, 0x6f, 0xff, 0xff, 0xdf, + 0xff, 0xdf, 0xdf, 0xff, 0xff, + 0xff, 0xa7, 0x6f, 0xff, 0xf7, 0xef, 0x97, 0xe7, + 0xf0, 0xef, 0x7f, 0xaf, 0x4f, 0xff, 0xff, 0xdf, + 0xbf, 0x5f, 0xe0, 0x7f, 0xef, + 0x7f, 0xa0, 0xef, 0xff, 0xe7, 0xff, 0xf7, 0xf7, + 0xff, 0x8b, 0xbf, 0xf8, 0xdf, 0xff, 0xcf, 0x7e, + 0xff, 0xdf, 0x7f, 0x8e, 0x5f, + 0xff, 0xff, 0x38, 0xff, 0xf7, 0xff, 0xf7, 0xf7, + 0xf7, 0xf7, 0x8f, 0xf7, 0xf8, 0xf7, 0xcf, 0xff, + 0xff, 0xff, 0xfe, 0xcb, 0x3f, + 0x3f, 0x9f, 0x7f, 0xf8, 0xff, 0xef, 0xff, 0xff, + 0x8f, 0xff, 0xf0, 0xaf, 0xff, 0xf0, 0xff, 0xdf, + 0xff, 0xff, 0xae, 0x7f, 0xc1, + 0x7f, 0xf0, 0x7f, 0xff, 0xff, 0xff, 0xef, 0xff, + 0xf7, 0xbf, 0xbf, 0xd0, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xff, 0x9b, 0xff, + 0x7f, 0xcf, 0xf8, 0xff, 0x8f, 0x6f, 0xe0, 0xd7, + 0xf7, 0xf7, 0xff, 0xfe, 0xf0, 0xfe, 0x8f, 0x5e, + 0xd1, 0xff, 0xdf, 0xdf, 0xbe, + 0xff, 0x84, 0x7f, 0xf8, 0xff, 0x7f, 0xdf, 0xff, + 0xff, 0xaf, 0x7f, 0x81, 0x7f, 0xf5, 0xff, 0xff, + 0xff, 0xff, 0xfa, 0x9f, 0x3f, + 0xff, 0xd8, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x0f, 0xff, 0x85, 0x7f, 0xf0, 0xff, 0xfe, + 0xbf, 0xff, 0xdf, 0x6f, 0xbf, + 0xff, 0xff, 0xff, 0xff, 0xaf, 0xff, 0xf7, 0xdf, + 0xf7, 0x47, 0xf4, 0xff, 0xef, 0xff, 0xdf, 0x7f, + 0xff, 0xbf, 0xcf, 0x5a, 0xf1, + 0xff, 0xbf, 0xbf, 0xff, 0xff, 0x3f, 0x8f, 0xc0, + 0xf3, 0xd1, 0xff, 0xfb, 0xef, 0xff, 0xdf, 0xbe, + 0x0f, 0x25, 0xe9, 0xd1, 0xff, + 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xf7, 0xf7, + 0x2f, 0xaf, 0xf3, 0xfb, 0xef, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xcf, 0xbf, 0xfb, + 0xbf, 0x87, 0xf8, 0xf8, 0xdf, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xeb, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe, + 0xfb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xdf, 0xf7, 0xff, 0xff, 0xcf, 0xff, + 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xfe, + 0xcf, 0xff, 0x7b, 0xfd, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0xdf, 0xff, 0xbf, 0xff, + 0xfb, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xef, 0xff, + 0xfb, 0xbe, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xd4, 0xbf, 0xf0, + 0xbf, 0xff, 0xff, 0xff, 0x93, 0x2f, 0xfd, 0xad, + 0xf7, 0x75, 0xff, 0xff, 0xfe, + 0xbf, 0x7f, 0xff, 0x9a, 0xff, 0xf4, 0x0f, 0xff, + 0x00, 0xde, 0xf0, 0xf3, 0xf9, 0xbf, 0x7d, 0xff, + 0x8f, 0x7f, 0x81, 0x0f, 0xd1, + 0xff, 0xfb, 0xdf, 0xee, 0x8b, 0x0b, 0x78, 0xf0, + 0xff, 0xfa, 0x7f, 0xbf, 0xff, 0xd5, 0x8f, 0x8f, + 0xe1, 0xf7, 0xfb, 0xfb, 0xff, + 0x7f, 0xb7, 0x99, 0xef, 0xdf, 0xf4, 0xff, 0xff, + 0xe4, 0xf4, 0x5d, 0xf6, 0xef, 0x9f, 0xef, 0xf7, + 0x3b, 0x3f, 0xdf, 0xbf, 0xec, + 0xff, 0xec, 0xf7, 0xb9, 0x6b, 0xbc, 0xfb, 0xf7, + 0xef, 0xff, 0x7e, 0xfd, 0x7e, 0xbb, 0xdf, 0x85, + 0xfe, 0xf7, 0xff, 0x7b, 0x7f, + 0xff, 0xff, 0xa7, 0xee, 0xe7, 0x5f, 0xe0, 0xf0, + 0xff, 0xff, 0xff, 0x5f, 0xe6, 0x6f, 0x81, 0x8d, + 0xd5, 0xf7, 0xbf, 0xef, 0xb6, + 0xff, 0xd7, 0xf4, 0xee, 0xb7, 0x7c, 0xff, 0xd7, + 0xaf, 0x7f, 0xed, 0x9f, 0xe5, 0xbf, 0xf7, 0x7d, + 0xfb, 0xb7, 0xad, 0xd7, 0xfd, + 0xbf, 0xff, 0xff, 0xc7, 0x8b, 0xff, 0xf0, 0xf6, + 0xff, 0xfd, 0xfb, 0xff, 0xdf, 0xbe, 0x0f, 0x7f, + 0xd5, 0xf7, 0xff, 0xf2, 0xfe, + 0xff, 0xff, 0xc5, 0xff, 0xf0, 0x7c, 0xff, 0xad, + 0x7f, 0x7f, 0xef, 0xff, 0xcf, 0x4f, 0xf1, 0xf5, + 0x7b, 0xdd, 0xff, 0xdf, 0xff, + 0xff, 0x77, 0xef, 0xff, 0xd8, 0xbf, 0xf7, 0xf3, + 0x5f, 0xfb, 0xf9, 0x7f, 0xe7, 0xff, 0xd7, 0x7f, + 0xad, 0xff, 0xfb, 0xfb, 0xf3, + 0xff, 0xcc, 0x95, 0x8f, 0xd8, 0xf3, 0xfc, 0xbc, + 0xdc, 0xdf, 0xbb, 0x44, 0x8b, 0xcb, 0x87, 0xb1, + 0xb7, 0xa7, 0x97, 0xee, 0xf3, + 0xff, 0x7f, 0xb4, 0xbf, 0xff, 0xc7, 0x7f, 0xcb, + 0xfd, 0xbf, 0x7f, 0x7f, 0x74, 0xe7, 0xdf, 0xf5, + 0xbb, 0xcf, 0xed, 0xfe, 0xfd, + 0xff, 0x3f, 0xfb, 0x77, 0xcc, 0xbb, 0xf0, 0xfb, + 0xff, 0xef, 0xbe, 0xff, 0xcf, 0xff, 0x85, 0x3f, + 0xb5, 0xff, 0xf7, 0x37, 0x7f, + 0x3f, 0xf7, 0xbf, 0xcf, 0x9f, 0xd7, 0xf7, 0xef, + 0xff, 0x78, 0xe7, 0xff, 0xff, 0xff, 0x1f, 0x7f, + 0x65, 0xbf, 0xbf, 0xff, 0xe7, + 0xff, 0xff, 0xff, 0xff, 0xdb, 0xf7, 0xdf, 0xff, + 0x77, 0x7f, 0xff, 0xff, 0xbf, 0xbf, 0xde, 0x77, + 0xdd, 0xff, 0xff, 0xfe, 0xff, + 0xbf, 0x68, 0xf8, 0xff, 0xf7, 0xff, 0xcf, 0xcf, + 0xf3, 0x17, 0x3f, 0xd5, 0xdd, 0xf7, 0xff, 0xff, + 0xcf, 0xdf, 0x73, 0x95, 0x3f, + 0xff, 0xac, 0x6f, 0xef, 0x77, 0xdf, 0xff, 0xf7, + 0xbb, 0x85, 0xdd, 0xe1, 0xf7, 0xfb, 0x7b, 0xdf, + 0xfe, 0xff, 0xb7, 0x9f, 0x79, + 0xff, 0xd8, 0xac, 0xfb, 0x47, 0xaf, 0xeb, 0xf7, + 0xff, 0xaf, 0x2e, 0x70, 0xd9, 0xf7, 0xfb, 0xdf, + 0xea, 0xfb, 0xfb, 0x1b, 0x5f, + 0xff, 0xf8, 0x6f, 0xaf, 0xd7, 0xb7, 0xeb, 0xff, + 0xe7, 0xaf, 0x7c, 0x70, 0xfb, 0xdf, 0xff, 0x7b, + 0xfb, 0xff, 0xda, 0x9f, 0xf9, + 0xff, 0x95, 0xbb, 0xfd, 0xc7, 0xcf, 0xfb, 0x83, + 0xef, 0xf3, 0xbf, 0xcf, 0x47, 0xf7, 0xe7, 0x1f, + 0xd7, 0x8b, 0x6f, 0x33, 0xbe, + 0xff, 0xc7, 0x6f, 0xfd, 0x97, 0x2f, 0xeb, 0xb7, + 0xdc, 0x77, 0xd7, 0x1f, 0x67, 0xf7, 0xe7, 0x9e, + 0xe7, 0xdb, 0x34, 0xdb, 0xfb, + 0x7f, 0xa8, 0xef, 0xff, 0xe7, 0xef, 0xff, 0xf7, + 0xff, 0x8b, 0xbf, 0xd8, 0xef, 0xff, 0xe7, 0xdf, + 0xf7, 0xfb, 0xf7, 0x9f, 0x66, + 0xff, 0xfb, 0x6c, 0xff, 0xb7, 0x9f, 0xcf, 0xcb, + 0xbb, 0x93, 0xaf, 0xff, 0xa8, 0xff, 0xc7, 0x3f, + 0xa7, 0xcf, 0xfe, 0xe3, 0x3f, + 0x3f, 0xdf, 0x7b, 0xfa, 0xff, 0xff, 0xff, 0xf7, + 0x8f, 0x3f, 0xd0, 0xd3, 0x7f, 0xfc, 0xff, 0x8e, + 0xff, 0xf3, 0x8f, 0x4e, 0xe4, + 0x7f, 0xb8, 0xff, 0xff, 0xff, 0xef, 0x8f, 0xdf, + 0xf3, 0xbb, 0x3f, 0xe0, 0xf3, 0xff, 0xff, 0xef, + 0x8f, 0xd7, 0xf3, 0xab, 0xef, + 0x7f, 0x8f, 0xf8, 0xfb, 0x8f, 0x6f, 0xa0, 0xff, + 0xff, 0xdc, 0xff, 0x5f, 0xfc, 0xf3, 0x8f, 0x6e, + 0xb1, 0xf7, 0xf7, 0xf7, 0x3e, + 0xff, 0x90, 0x7b, 0xf8, 0xff, 0x7f, 0xdf, 0xff, + 0xfb, 0x9f, 0x7f, 0xa0, 0xf3, 0xf1, 0xff, 0xff, + 0xdf, 0xff, 0xdb, 0xbf, 0x3f, + 0xff, 0xdc, 0xfb, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x77, 0xaf, 0xff, 0xad, 0xf3, 0xf8, 0xff, 0xfe, + 0xef, 0xff, 0xff, 0x6f, 0xbf, + 0xff, 0xff, 0xcf, 0xff, 0xa3, 0xff, 0xaf, 0xcf, + 0x93, 0xc3, 0x74, 0xef, 0xdf, 0xff, 0xab, 0x2f, + 0xe7, 0xc7, 0xf3, 0x73, 0x79, + 0xff, 0xff, 0xcf, 0xff, 0xc3, 0x7f, 0x83, 0xe4, + 0xd3, 0xbc, 0x7b, 0xdb, 0xdf, 0x7f, 0x8b, 0x8e, + 0x83, 0x01, 0x51, 0xd5, 0x7b, + 0xff, 0xfb, 0xdf, 0xff, 0xc3, 0xef, 0xb3, 0xff, + 0xb7, 0xff, 0xfe, 0xbf, 0xdf, 0xff, 0x8b, 0x6e, + 0xf3, 0xfb, 0xb7, 0x1f, 0xfe, + 0xbf, 0x82, 0xc8, 0xf8, 0xd3, 0x7f, 0xf3, 0xfb, + 0xff, 0xef, 0x87, 0x87, 0xd0, 0x70, 0x8b, 0xff, + 0xf3, 0xff, 0xef, 0xef, 0x87, + 0xff, 0xff, 0xff, 0xff, 0x47, 0xff, 0xf3, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xdf, 0x7f, 0xcb, 0xef, + 0xf2, 0xf7, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0xef, 0xf2, 0xf7, 0xff, 0xf7, 0xff, + 0xff, 0xff, 0xf7, 0xef, 0xdf, 0xf7, 0xca, 0x7f, + 0xf3, 0xf7, 0xef, 0xff, 0xf6, + 0xff, 0xfa, 0xfb, 0xff, 0xe7, 0xff, 0xf7, 0xff, + 0xff, 0xef, 0xff, 0xf7, 0x57, 0x7f, 0xca, 0xef, + 0xf3, 0xff, 0xff, 0xef, 0xef, + 0xff, 0xf6, 0xeb, 0xfa, 0xf7, 0xff, 0xf7, 0x8f, + 0xff, 0xe3, 0xf7, 0xef, 0xd7, 0xf7, 0xcb, 0x7f, + 0xf3, 0x8f, 0x6c, 0xf2, 0xe7, + 0xff, 0xff, 0x2f, 0xff, 0xf1, 0x9d, 0x9e, 0xf4, + 0xff, 0xff, 0xff, 0xef, 0x0f, 0xff, 0xf1, 0x09, + 0x3f, 0xf9, 0xbf, 0xf7, 0xfb, + 0xff, 0xef, 0x7f, 0xf6, 0xfb, 0xf5, 0x0f, 0xdf, + 0x00, 0xff, 0xd0, 0xbf, 0xc0, 0xbf, 0xf9, 0xff, + 0x8f, 0x7f, 0x81, 0x6f, 0xe1, + 0xff, 0xff, 0x9e, 0xaf, 0xf7, 0x0f, 0x18, 0xd9, + 0xbf, 0x6f, 0x37, 0xef, 0x8f, 0xff, 0x9e, 0x06, + 0x75, 0xf7, 0xf6, 0xff, 0xef, + 0x7f, 0xf7, 0xcf, 0xbb, 0xfb, 0x6d, 0xfb, 0xef, + 0x7d, 0xe9, 0xff, 0xff, 0xbf, 0xc2, 0xf7, 0x6f, + 0xff, 0xdc, 0xff, 0xf3, 0xfa, + 0x7f, 0x6f, 0xf7, 0xf9, 0xff, 0x6d, 0xfe, 0x9c, + 0xbf, 0xbf, 0x7d, 0xe2, 0x7f, 0x77, 0x9f, 0xcd, + 0xb7, 0xb5, 0xff, 0xff, 0x7f, + 0x7f, 0xff, 0x87, 0xae, 0x86, 0xdf, 0xc0, 0xfd, + 0xfb, 0xfa, 0xff, 0xff, 0x8e, 0x6d, 0xd5, 0x3d, + 0xf1, 0xff, 0xfe, 0xef, 0xff, + 0xff, 0x3f, 0xd2, 0xa4, 0xfe, 0xd9, 0xf7, 0xfe, + 0xdf, 0xff, 0xcb, 0xff, 0xdd, 0x7e, 0xbb, 0xdd, + 0x5f, 0xf7, 0xbf, 0xff, 0xed, + 0xff, 0xfe, 0xf5, 0xff, 0xb7, 0xf6, 0xb4, 0xae, + 0xfe, 0xef, 0xf7, 0xff, 0xff, 0x8f, 0x07, 0x7b, + 0xfb, 0xff, 0x7f, 0xff, 0xf7, + 0xff, 0x7b, 0xa3, 0xbf, 0xe3, 0xff, 0xff, 0xf7, + 0xf7, 0xfd, 0xdf, 0xff, 0x8f, 0x7f, 0x9b, 0xdf, + 0xfb, 0xef, 0xfe, 0xff, 0x3f, + 0xff, 0x6f, 0xff, 0x7f, 0xb3, 0x7f, 0xdf, 0xbd, + 0x78, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xef, 0xff, + 0xdf, 0xee, 0x9d, 0xfd, 0xef, + 0xff, 0xf8, 0x05, 0x8e, 0xb0, 0x58, 0xf7, 0xfc, + 0xa4, 0x85, 0xdd, 0xbc, 0x0b, 0x05, 0x61, 0xf8, + 0xb7, 0xff, 0xeb, 0xef, 0x7f, + 0xbf, 0xff, 0xc7, 0xbb, 0xd8, 0x6f, 0x79, 0xde, + 0xff, 0xff, 0xcf, 0xff, 0xba, 0xaf, 0xd9, 0x7b, + 0xfd, 0xff, 0xf5, 0xdf, 0xbf, + 0xff, 0xff, 0xaf, 0x7f, 0x88, 0x7f, 0xf0, 0xea, + 0xfe, 0x7f, 0xf2, 0xff, 0xdf, 0xd7, 0x4f, 0x7f, + 0xe3, 0xde, 0xff, 0xff, 0xf7, + 0xff, 0x7d, 0x6f, 0x5f, 0xab, 0xff, 0x7a, 0xb6, + 0xbf, 0x78, 0xdd, 0x7f, 0xde, 0xef, 0x4b, 0x9b, + 0xeb, 0x7f, 0x76, 0x9f, 0xac, + 0xff, 0xcf, 0xff, 0xff, 0xb7, 0x7f, 0xae, 0xef, + 0xdb, 0xef, 0xff, 0xf7, 0xff, 0xfb, 0xe7, 0xfe, + 0xbf, 0x7e, 0xfb, 0xf7, 0xfb, + 0xff, 0xff, 0xff, 0xff, 0xcf, 0xbf, 0xff, 0xff, + 0xf3, 0xff, 0xff, 0xff, 0xff, 0xef, 0xd7, 0xff, + 0xe9, 0xef, 0xf2, 0xfe, 0xff, + 0xff, 0xff, 0xff, 0xef, 0xff, 0x8d, 0xaf, 0xf2, + 0x71, 0xff, 0xfe, 0xff, 0xff, 0x7f, 0xff, 0xcf, + 0x0f, 0x75, 0xf1, 0xff, 0xff, + 0x3f, 0x78, 0xbc, 0xfb, 0xfe, 0xff, 0xff, 0xbf, + 0xf3, 0x0f, 0x3f, 0xc9, 0xe9, 0x7f, 0xf7, 0xdf, + 0xff, 0xff, 0x57, 0x82, 0x2e, + 0xff, 0xf8, 0x7f, 0xfb, 0x7a, 0xfb, 0xff, 0xff, + 0xeb, 0x87, 0x9b, 0xf1, 0xe5, 0x7f, 0x75, 0x7f, + 0xfe, 0xff, 0xbe, 0x39, 0x79, + 0xff, 0xcd, 0xbf, 0xfd, 0x7e, 0xff, 0xfb, 0xf4, + 0xf7, 0xed, 0x6f, 0xf3, 0x6b, 0xf7, 0xd7, 0xbf, + 0xfe, 0xfd, 0xf7, 0x8f, 0xef, + 0xff, 0xf8, 0x7a, 0xff, 0xfa, 0xf0, 0xff, 0xff, + 0xe6, 0x8f, 0x9b, 0xf1, 0xad, 0xbf, 0xf7, 0xfd, + 0xbf, 0xfd, 0xef, 0x8f, 0x3f, + 0xbf, 0xff, 0xad, 0xfb, 0xf4, 0xbf, 0xf3, 0x90, + 0xdd, 0xf0, 0xfa, 0xcf, 0xe7, 0xf2, 0xf7, 0x7f, + 0xff, 0xad, 0xff, 0xf5, 0xdf, + 0xff, 0xcb, 0x7b, 0xfa, 0xd2, 0x7f, 0xc7, 0xf3, + 0xa9, 0xf7, 0xe7, 0x8b, 0xe7, 0xf1, 0xf7, 0x3f, + 0x8f, 0x7f, 0xb0, 0xdf, 0xfd, + 0x7f, 0xf8, 0xff, 0xfb, 0xf2, 0xff, 0xd2, 0xe3, + 0xdf, 0x87, 0xd3, 0xf0, 0xed, 0xff, 0xf7, 0x7f, + 0xff, 0xef, 0x77, 0xaa, 0x7f, + 0xbf, 0xea, 0xfc, 0xfb, 0xb3, 0xbf, 0xb3, 0xff, + 0xd8, 0x93, 0xab, 0xf1, 0xac, 0xff, 0xf7, 0x3f, + 0xaf, 0xef, 0xed, 0xc7, 0xad, + 0xff, 0xd6, 0xff, 0xfd, 0xff, 0xdf, 0xff, 0xf4, + 0x8f, 0xbf, 0xb1, 0xed, 0xf5, 0xfb, 0xff, 0xef, + 0xff, 0xf5, 0x8f, 0xdf, 0xf1, + 0xff, 0xf8, 0xfe, 0xfb, 0xff, 0xdf, 0x9f, 0xf8, + 0xf0, 0xef, 0xff, 0xd0, 0xfd, 0xf7, 0xff, 0xef, + 0xaf, 0xf5, 0xf7, 0xce, 0x7f, + 0x7f, 0x83, 0x7d, 0xfa, 0x8f, 0x5f, 0xd0, 0xcb, + 0xe9, 0xbb, 0x76, 0x9f, 0x7b, 0xf7, 0x8f, 0x6e, + 0xb1, 0xd5, 0xf7, 0x5f, 0xc6, + 0xff, 0xa3, 0x7f, 0xfc, 0xff, 0x7f, 0xff, 0xff, + 0xdf, 0x9f, 0x7f, 0xa8, 0x77, 0xf5, 0xff, 0xfe, + 0xff, 0xff, 0xfe, 0x7f, 0x2d, + 0xff, 0x96, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, + 0x37, 0x6f, 0xfd, 0xaf, 0x77, 0xf8, 0xff, 0xff, + 0xef, 0xff, 0xff, 0xff, 0x4b, + 0xff, 0x72, 0xaf, 0xff, 0xe5, 0xdf, 0x99, 0xfc, + 0x10, 0x63, 0xf0, 0xef, 0xef, 0x7f, 0x8b, 0xef, + 0xaf, 0xe7, 0xf5, 0xf7, 0x7d, + 0xff, 0xef, 0x8f, 0xff, 0xa1, 0x4f, 0x81, 0xe7, + 0xb0, 0xfa, 0xfe, 0xd7, 0xcf, 0xff, 0xca, 0xcf, + 0x0b, 0x85, 0x71, 0xfa, 0xff, + 0xff, 0xdd, 0xef, 0xff, 0xa4, 0xdf, 0xb1, 0xdc, + 0xd3, 0xff, 0xf8, 0xff, 0xcf, 0x7f, 0xcb, 0x7f, + 0xff, 0xf5, 0xff, 0xbf, 0xfd, + 0xbf, 0x82, 0xc8, 0xf8, 0xe1, 0x7f, 0xf0, 0xdf, + 0xff, 0xef, 0x87, 0x87, 0xc0, 0xf0, 0xca, 0x2f, + 0xfb, 0xff, 0xef, 0xee, 0x97, + 0xff, 0xff, 0x8f, 0xfa, 0xa5, 0xdf, 0xd1, 0xf7, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0xdb, 0xef, + 0xff, 0xf5, 0xfd, 0xff, 0xff, + 0xff, 0xf6, 0x8b, 0xf2, 0x94, 0xff, 0xf1, 0xf7, + 0xff, 0xff, 0xf7, 0xef, 0xd7, 0xf7, 0xdf, 0xee, + 0xfb, 0xff, 0xef, 0xff, 0xf7, + 0xff, 0xf3, 0xcb, 0xff, 0xe6, 0xff, 0xf1, 0xef, + 0xff, 0xef, 0xff, 0xe7, 0xd7, 0x7f, 0xdb, 0x7e, + 0xfd, 0xf7, 0xff, 0xef, 0xef, + 0xff, 0xfe, 0xcf, 0xff, 0xc4, 0xff, 0xf2, 0x9f, + 0xff, 0xe0, 0xf7, 0xff, 0xdf, 0xff, 0xdf, 0x7f, + 0xdb, 0xac, 0xef, 0xf1, 0xf7, + 0x7f, 0xef, 0x0f, 0x5f, 0xb4, 0x8f, 0xff, 0xf6, + 0xfd, 0xff, 0x6f, 0xff, 0x8f, 0xff, 0xe9, 0x8d, + 0x7f, 0xf1, 0xd1, 0xf7, 0xfe, + 0xff, 0xe7, 0x7f, 0x87, 0xfd, 0xe7, 0x8f, 0x9b, + 0x00, 0xff, 0xb0, 0x7d, 0xfd, 0xcf, 0xfb, 0xfd, + 0x8f, 0x7f, 0x81, 0x6d, 0xd1, + 0xff, 0xbc, 0xed, 0xff, 0x86, 0x6e, 0x10, 0xf1, + 0xf4, 0x5f, 0x7f, 0xfe, 0x9f, 0x37, 0xc3, 0x8f, + 0xf7, 0xe5, 0xfb, 0xff, 0xff, + 0x7f, 0xfe, 0xff, 0xfd, 0x97, 0xff, 0xfb, 0xff, + 0x3f, 0xff, 0xf9, 0xc3, 0x1f, 0xf8, 0xff, 0xb5, + 0x5f, 0xef, 0xdc, 0xff, 0xbe, + 0xff, 0xcb, 0xe7, 0xfd, 0x69, 0xe7, 0xfc, 0xb6, + 0xef, 0x9a, 0x77, 0xb6, 0x67, 0xdf, 0xef, 0xf7, + 0xfe, 0xdf, 0xff, 0xf5, 0x7f, + 0xff, 0xf7, 0x97, 0xbe, 0xf4, 0xff, 0xf1, 0xba, + 0xfe, 0xff, 0x97, 0x7f, 0xbf, 0x77, 0x55, 0xdf, + 0xd9, 0xf1, 0xff, 0xdf, 0xff, + 0xbf, 0xbf, 0x72, 0xf2, 0xdd, 0xff, 0xe4, 0xff, + 0x7f, 0xef, 0xff, 0xf7, 0xfe, 0xfb, 0xb9, 0xff, + 0xff, 0xf5, 0xff, 0xfb, 0x96, + 0xff, 0x7f, 0xf7, 0xef, 0x83, 0xf7, 0xf7, 0xff, + 0xdf, 0xff, 0xf7, 0xfd, 0xd5, 0x9f, 0x0f, 0x7f, + 0xf0, 0xfb, 0xae, 0xff, 0xec, + 0xff, 0x7b, 0x85, 0xf7, 0xf3, 0xef, 0xff, 0xf7, + 0xff, 0xed, 0xff, 0xe7, 0x8f, 0x7f, 0xc7, 0x97, + 0x3f, 0xfc, 0xff, 0xf7, 0xde, + 0xff, 0xfd, 0x8b, 0xff, 0xf7, 0x1f, 0xfb, 0xff, + 0x2f, 0xfb, 0xf7, 0xff, 0xbf, 0xff, 0xff, 0x6f, + 0xf7, 0xf9, 0xe7, 0xff, 0x33, + 0xff, 0x9e, 0xe7, 0x8b, 0xf0, 0x50, 0xf1, 0xde, + 0xff, 0x9f, 0x1b, 0x28, 0x1b, 0x8d, 0xb4, 0xe1, + 0xf5, 0xf3, 0xfe, 0xef, 0xfa, + 0xff, 0x7f, 0xf6, 0xff, 0xfe, 0x07, 0xec, 0xfb, + 0x7f, 0xff, 0xfd, 0xff, 0xd6, 0x8f, 0xff, 0xf9, + 0xff, 0x37, 0x7f, 0xfb, 0xdd, + 0xff, 0xff, 0xff, 0x63, 0xef, 0xdf, 0xfa, 0xf1, + 0xff, 0xfc, 0xfe, 0xdf, 0xfb, 0xff, 0x8f, 0x7f, + 0xf9, 0xeb, 0xef, 0xfd, 0xff, + 0x7f, 0x7f, 0xfb, 0xe7, 0x9f, 0x9b, 0xe5, 0xcf, + 0xfd, 0xf7, 0xcf, 0xff, 0xf3, 0xbf, 0x5f, 0x5d, + 0x67, 0x9f, 0xdf, 0x7f, 0xf9, + 0xff, 0xff, 0xff, 0x1f, 0xfe, 0xff, 0xf5, 0xdf, + 0x5f, 0xfb, 0xfb, 0xbf, 0xcf, 0xdf, 0xfb, 0x7f, + 0xb7, 0xff, 0xfb, 0xff, 0xf7, + 0x3f, 0x78, 0xfc, 0xf3, 0xff, 0xff, 0xdf, 0xbf, + 0xf3, 0x05, 0x3f, 0xc1, 0xf1, 0xff, 0xf7, 0xef, + 0xef, 0xff, 0xfb, 0x97, 0x1f, + 0xff, 0xd8, 0x7f, 0xfb, 0x7b, 0xfb, 0xf7, 0xbf, + 0xbb, 0x8e, 0xd3, 0xe1, 0xff, 0xfd, 0xf7, 0xed, + 0xfe, 0x8b, 0x5e, 0x0f, 0x69, + 0xbf, 0xf8, 0xfc, 0xfb, 0x7b, 0xff, 0xdf, 0xed, + 0xf7, 0x8f, 0xbf, 0xce, 0xfe, 0xff, 0xf3, 0xff, + 0xf6, 0xff, 0xfe, 0x8f, 0x0f, + 0xff, 0xfc, 0x7d, 0xff, 0xff, 0xfd, 0xf3, 0xff, + 0xbf, 0x8f, 0xe3, 0xf0, 0xfe, 0xff, 0xfb, 0xff, + 0xff, 0xff, 0xae, 0x0f, 0x5d, + 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xd1, + 0xfd, 0xf1, 0xd3, 0xdd, 0xfd, 0xf1, 0xfb, 0xff, + 0xfb, 0xfd, 0xff, 0xfd, 0xf6, + 0xff, 0xff, 0x7f, 0xfe, 0xfd, 0xff, 0x87, 0xff, + 0xcc, 0xf3, 0xdf, 0xcb, 0xff, 0xfb, 0xfb, 0xff, + 0x8b, 0x7f, 0xfa, 0xff, 0xff, + 0x7f, 0xf8, 0xfe, 0xff, 0xef, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xe8, 0xff, 0xff, 0xf9, 0xff, + 0xfb, 0xaf, 0x7f, 0x8f, 0x7e, + 0xbf, 0xfb, 0x78, 0xff, 0xff, 0xff, 0xd7, 0xd3, + 0xfd, 0xc3, 0x95, 0xc5, 0xf8, 0xff, 0xfb, 0xff, + 0xfb, 0xff, 0xfc, 0xf2, 0x8f, + 0xff, 0x8b, 0x7b, 0xff, 0xff, 0xdf, 0xff, 0xfd, + 0x8f, 0xef, 0xf4, 0xb7, 0xff, 0xfe, 0xff, 0xfe, + 0xff, 0xff, 0x8f, 0x6f, 0xf4, + 0xff, 0xfd, 0xff, 0xfe, 0xff, 0xdf, 0xdf, 0xfd, + 0xf1, 0xb3, 0xff, 0xd8, 0xff, 0xfd, 0xff, 0xff, + 0xff, 0xfd, 0xf5, 0x87, 0x7f, + 0x3f, 0xef, 0xff, 0xff, 0x8f, 0x5f, 0xf0, 0xff, + 0xf1, 0xef, 0x39, 0xc7, 0x7e, 0xf3, 0x8f, 0x7e, + 0xf1, 0xbd, 0xed, 0xfa, 0x9a, + 0xff, 0x98, 0x7f, 0xfa, 0xff, 0x7f, 0xff, 0xff, + 0xf3, 0x8f, 0x5f, 0x8a, 0xfb, 0xf1, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0xaf, 0x5f, + 0xff, 0x86, 0xff, 0xfc, 0xff, 0xff, 0xdf, 0xff, + 0x7f, 0xbf, 0xcb, 0xbd, 0x77, 0xf2, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xbf, 0x77, + 0xff, 0xff, 0xef, 0xff, 0xed, 0xdf, 0xff, 0xdd, + 0x11, 0x73, 0xfc, 0xfc, 0xef, 0xff, 0xfb, 0xff, + 0xfd, 0xfd, 0x9d, 0xf3, 0xff, + 0xff, 0xf9, 0xef, 0xff, 0xf3, 0x0f, 0x83, 0x9e, + 0xf0, 0xf0, 0xff, 0xed, 0xef, 0xff, 0xe9, 0x8e, + 0x7b, 0x9d, 0x70, 0xe9, 0xf7, + 0xff, 0xff, 0xef, 0xff, 0xef, 0xff, 0xf3, 0xf9, + 0xf7, 0xff, 0xfb, 0xf3, 0xef, 0xfd, 0xeb, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xf8, + 0x3f, 0x87, 0xec, 0xf8, 0xe5, 0x7f, 0xfb, 0xff, + 0xff, 0xff, 0x8f, 0x87, 0xe8, 0xf0, 0xeb, 0xff, + 0xff, 0xfd, 0xff, 0xff, 0x97, + 0xff, 0xff, 0xef, 0xff, 0xed, 0xdf, 0xd3, 0xbf, + 0x7f, 0xfe, 0xff, 0xff, 0xef, 0xff, 0xe3, 0xef, + 0xff, 0xff, 0xff, 0xfe, 0xff, + 0xff, 0x77, 0xef, 0xfa, 0xe7, 0xff, 0xfb, 0xff, + 0xff, 0xff, 0xef, 0xef, 0xef, 0xf7, 0xea, 0xfe, + 0xf3, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xf7, 0xeb, 0xf3, 0xef, 0xff, 0xf3, 0xff, + 0xf1, 0x7f, 0xff, 0xe7, 0xe7, 0xf7, 0xea, 0xee, + 0xf7, 0xff, 0xf1, 0xff, 0xe7, + 0xff, 0xfb, 0x6f, 0xf6, 0xe5, 0xff, 0xeb, 0xdf, + 0xef, 0xff, 0xff, 0xf7, 0xef, 0xff, 0xe3, 0xef, + 0xff, 0xfe, 0xff, 0xfe, 0xf7, + 0x7f, 0xff, 0x4f, 0x5f, 0xe1, 0xc7, 0xef, 0xf1, + 0xfe, 0x7f, 0x7b, 0xff, 0x6f, 0xff, 0x93, 0x0b, + 0x7f, 0xf1, 0xfa, 0xdf, 0xff, + 0xff, 0xfb, 0x7f, 0xdf, 0xf7, 0xef, 0x8f, 0xff, + 0x00, 0xef, 0xf0, 0xdf, 0x7f, 0xef, 0xff, 0xfb, + 0x8f, 0x7f, 0x81, 0x6f, 0xd1, + 0xff, 0xde, 0xff, 0xef, 0xb9, 0x49, 0x74, 0xf3, + 0xef, 0x7b, 0x7f, 0xff, 0xeb, 0xf7, 0x85, 0x67, + 0xf1, 0xf0, 0xe1, 0xff, 0xf7, + 0x3f, 0xab, 0xff, 0xc4, 0xbb, 0xff, 0x8c, 0x9d, + 0x7e, 0x3a, 0xb5, 0xbb, 0xe3, 0xfb, 0xf3, 0xcd, + 0xe3, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xdc, 0xf7, 0xf8, 0x77, 0x8f, 0xf7, 0xfe, + 0x9f, 0x97, 0x7a, 0xf2, 0x7f, 0xfb, 0x8f, 0x1f, + 0x7d, 0xfd, 0xef, 0xb1, 0x7d, + 0xff, 0xef, 0xa6, 0xef, 0x98, 0x9d, 0xf0, 0xf4, + 0xf4, 0xff, 0xff, 0x7f, 0x8f, 0x7f, 0x89, 0x7f, + 0xe7, 0xff, 0xff, 0xf7, 0xfb, + 0xbf, 0xa7, 0xb7, 0xdf, 0xba, 0xfd, 0xfe, 0xeb, + 0xff, 0xff, 0xc4, 0xef, 0x8f, 0x7c, 0xf7, 0x8f, + 0x7f, 0xf9, 0xfb, 0xff, 0xfb, + 0xff, 0xff, 0xff, 0xeb, 0x87, 0xfd, 0xf4, 0xf7, + 0x6f, 0xff, 0xbf, 0xff, 0xff, 0xef, 0xef, 0xdf, + 0xff, 0xff, 0xff, 0xf7, 0xff, + 0xff, 0xf7, 0x85, 0xdb, 0xf2, 0xbf, 0xd7, 0xff, + 0xff, 0xfd, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xaf, + 0x7d, 0xff, 0xf7, 0xeb, 0xff, + 0xbf, 0xfd, 0x8f, 0xff, 0xfa, 0x3f, 0xff, 0xf6, + 0xb7, 0xff, 0xfe, 0xfb, 0x8f, 0x7f, 0xff, 0xff, + 0xf3, 0xee, 0xbf, 0x7f, 0xff, + 0xff, 0x67, 0xc6, 0xaf, 0xc3, 0x74, 0xf7, 0xfe, + 0xee, 0x8a, 0x37, 0x6e, 0xec, 0x87, 0x71, 0x91, + 0x13, 0x7d, 0xec, 0x87, 0xff, + 0xbf, 0x7b, 0xf0, 0xef, 0xfb, 0x3f, 0xb7, 0xfc, + 0xff, 0xff, 0x97, 0x7d, 0xe8, 0xef, 0x9d, 0x77, + 0xfd, 0xfb, 0xff, 0xfb, 0xbf, + 0xff, 0xff, 0xde, 0x77, 0xcd, 0xff, 0xf1, 0xfb, + 0xff, 0xff, 0xf9, 0xe3, 0xff, 0xff, 0xef, 0xff, + 0xff, 0xfc, 0xcf, 0xff, 0xf3, + 0x7f, 0xff, 0xfe, 0x77, 0xaf, 0xf7, 0xf8, 0xef, + 0xff, 0x76, 0xfa, 0xff, 0x99, 0x6d, 0x9f, 0x6f, + 0xf1, 0xbf, 0x7f, 0x7f, 0xfc, + 0xff, 0xff, 0xef, 0xbf, 0xeb, 0xfa, 0xdd, 0xef, + 0xbc, 0xfd, 0xfd, 0xdf, 0xff, 0xf7, 0xff, 0xff, + 0xd1, 0xfe, 0xff, 0xfb, 0xff, + 0x3f, 0x70, 0xf8, 0xff, 0xf5, 0xff, 0xff, 0x9f, + 0xf3, 0x09, 0x1f, 0xe1, 0xf3, 0xfd, 0xfd, 0xff, + 0xef, 0xff, 0xf7, 0x8e, 0x1e, + 0xff, 0xf8, 0x7f, 0xff, 0x77, 0xff, 0xff, 0x9b, + 0x8f, 0x8e, 0xfb, 0xf1, 0xef, 0xe5, 0xfd, 0xef, + 0xfe, 0x9f, 0x16, 0x03, 0x61, + 0xbf, 0xf8, 0xfa, 0xfd, 0x73, 0xff, 0xff, 0xf7, + 0xf7, 0x8d, 0x9f, 0xe1, 0xf1, 0xff, 0xef, 0xff, + 0xfc, 0xff, 0xff, 0x8f, 0x0f, + 0xff, 0xf8, 0x7f, 0xff, 0xf7, 0xf7, 0xfd, 0xff, + 0x9f, 0x8f, 0xe1, 0xf1, 0xef, 0xff, 0xff, 0xff, + 0xfd, 0xff, 0x8e, 0x0f, 0x7d, + 0xff, 0xf7, 0xf9, 0xfe, 0xf3, 0x7f, 0xff, 0xf7, + 0xf7, 0xf3, 0xfd, 0xef, 0xff, 0xf9, 0xed, 0xff, + 0xff, 0xef, 0xff, 0xf7, 0xff, + 0xff, 0xf7, 0x7e, 0xfe, 0xf7, 0xff, 0x8b, 0xf7, + 0xfc, 0xeb, 0xeb, 0xed, 0xeb, 0xf9, 0xfd, 0xff, + 0x8f, 0x7f, 0xf2, 0xfe, 0xed, + 0x7f, 0xf8, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, + 0xf7, 0x8d, 0xff, 0xe8, 0xff, 0xfd, 0xef, 0xfe, + 0xfd, 0xdf, 0xf6, 0x8f, 0x6f, + 0xbf, 0xff, 0x78, 0xff, 0xf7, 0xff, 0xfb, 0xff, + 0xff, 0xe3, 0x9f, 0xe5, 0xea, 0xf5, 0xfd, 0xff, + 0xed, 0xef, 0xff, 0xf7, 0x8f, + 0xff, 0x07, 0xff, 0xf9, 0xff, 0xff, 0xff, 0xf7, + 0x8f, 0xff, 0xf3, 0x93, 0xff, 0xff, 0xff, 0xef, + 0xff, 0xf7, 0x8f, 0x7f, 0xf3, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x8b, 0xff, 0xe8, 0xfb, 0xff, 0xff, 0xef, + 0xef, 0xf7, 0xf5, 0x8e, 0x7f, + 0x3f, 0xec, 0xf9, 0xfc, 0x8f, 0x7f, 0xf0, 0xef, + 0xef, 0xff, 0x1d, 0xed, 0x7e, 0xfd, 0x8f, 0x6e, + 0xf1, 0xd7, 0xf7, 0xde, 0x8c, + 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xfb, 0x8f, 0x6f, 0x90, 0xff, 0xf3, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x8f, 0x7f, + 0xff, 0x87, 0xfb, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x9f, 0xff, 0x93, 0x7f, 0xf2, 0xff, 0xfe, + 0xef, 0xff, 0xff, 0x9f, 0x69, + 0xff, 0xfb, 0xef, 0xff, 0xf6, 0xff, 0xff, 0xff, + 0x1f, 0x73, 0xfe, 0xf6, 0xff, 0xff, 0xff, 0xef, + 0xef, 0xe7, 0x97, 0x77, 0xf7, + 0xff, 0xff, 0xff, 0xff, 0xe7, 0x1f, 0x86, 0x95, + 0xf0, 0xf6, 0xf7, 0xff, 0xff, 0xff, 0xfe, 0x8f, + 0x6d, 0x93, 0x71, 0xf8, 0xfd, + 0xff, 0xfe, 0xef, 0xfd, 0xf2, 0xff, 0xf6, 0xff, + 0x6f, 0xef, 0xf7, 0xfd, 0xff, 0xff, 0xfd, 0xff, + 0xfd, 0xff, 0xef, 0xff, 0xf5, + 0x3f, 0x82, 0xf8, 0xf8, 0xe6, 0x7f, 0xf2, 0xff, + 0xff, 0xff, 0x87, 0x87, 0xf0, 0xf0, 0xfc, 0xef, + 0xfd, 0xf7, 0xef, 0xee, 0x87, + 0xff, 0xff, 0xef, 0xff, 0xe7, 0xff, 0xf6, 0xf7, + 0x7f, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, + 0xff, 0xf7, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0xff, 0xf2, 0xe6, 0xff, 0xf5, 0xf7, + 0xff, 0xff, 0xff, 0xe7, 0xff, 0xf7, 0xff, 0xfe, + 0xff, 0xf7, 0xef, 0xff, 0xf7, + 0xff, 0xfa, 0xeb, 0xff, 0xe3, 0xff, 0xf5, 0xff, + 0xff, 0xff, 0xf7, 0xef, 0xf7, 0xff, 0xfd, 0xee, + 0xfd, 0xff, 0xff, 0xef, 0xef, + 0xff, 0xf6, 0xfb, 0x7a, 0xe7, 0xff, 0x91, 0xef, + 0xff, 0xe2, 0xff, 0xf7, 0xf7, 0xf7, 0xfd, 0xff, + 0xfd, 0xef, 0xeb, 0xf5, 0xe7, + 0xff, 0xff, 0x8f, 0xbe, 0xf1, 0x93, 0xfd, 0xf1, + 0xff, 0xff, 0xff, 0xff, 0x2e, 0x2f, 0x59, 0x8f, + 0x6f, 0xf9, 0xf7, 0xff, 0xfa, + 0xff, 0x4f, 0xbf, 0xc4, 0xfb, 0xf5, 0x0f, 0xff, + 0x00, 0xff, 0xd0, 0x7f, 0x70, 0xaf, 0x7f, 0xff, + 0x8f, 0x7f, 0x81, 0x7f, 0xb1, + 0xff, 0xff, 0xda, 0xff, 0x2f, 0x4f, 0x7e, 0xf9, + 0xfb, 0xff, 0x5f, 0xef, 0xff, 0xff, 0x99, 0x29, + 0x71, 0xf1, 0xed, 0xff, 0xff, + 0x3f, 0xb7, 0xef, 0xdf, 0xff, 0xf9, 0xfe, 0xfd, + 0xff, 0xff, 0xb7, 0x9f, 0xff, 0xab, 0x73, 0xfd, + 0xad, 0x3c, 0x6b, 0xff, 0xfa, + 0xff, 0xe8, 0xf7, 0xbf, 0x6f, 0x8f, 0xff, 0xfe, + 0xff, 0x87, 0x7f, 0xe0, 0x7f, 0xbf, 0x5f, 0x93, + 0x7e, 0xe4, 0xf6, 0x97, 0x7b, + 0xff, 0xdf, 0x27, 0xaf, 0xa7, 0xff, 0xf4, 0xf6, + 0xff, 0xff, 0xff, 0x5f, 0xdf, 0xfb, 0x87, 0x1f, + 0x70, 0xf3, 0xfe, 0x7f, 0xfb, + 0xbf, 0xb7, 0x61, 0xb5, 0xfc, 0xff, 0xf7, 0xff, + 0xbf, 0xff, 0xa2, 0xff, 0xd8, 0xa1, 0x77, 0xdf, + 0xe6, 0xff, 0xff, 0x7e, 0xc4, + 0xff, 0xff, 0xf6, 0xd7, 0x97, 0xdb, 0xe8, 0xff, + 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xb9, 0x3b, + 0xf8, 0xff, 0xef, 0xe7, 0xbe, + 0xff, 0xff, 0x86, 0xbf, 0xe2, 0xad, 0xff, 0xff, + 0xff, 0xff, 0x9f, 0xff, 0x8f, 0x3f, 0x63, 0xcf, + 0x7b, 0xfe, 0xff, 0xfd, 0xfe, + 0xff, 0xff, 0xdf, 0xff, 0xba, 0x7f, 0xf7, 0xee, + 0x17, 0xf7, 0xee, 0xef, 0x97, 0x7f, 0xf7, 0xff, + 0xff, 0xfd, 0x9e, 0x77, 0xf3, + 0xff, 0xfb, 0xc3, 0x8f, 0xc1, 0x70, 0x71, 0xff, + 0xf7, 0x9f, 0x77, 0x7e, 0xb6, 0x4f, 0xb9, 0x01, + 0x1f, 0x1b, 0x7a, 0x9a, 0x7e, + 0xbf, 0xff, 0xf0, 0x9f, 0xef, 0x79, 0x3f, 0xf6, + 0xff, 0xfd, 0x9d, 0x7b, 0xf2, 0xff, 0xc9, 0xf3, + 0xff, 0x7d, 0xfb, 0xfd, 0xbf, + 0xff, 0xfd, 0xbf, 0x77, 0x8f, 0xff, 0xf1, 0xf7, + 0xff, 0xff, 0xff, 0xfd, 0xbb, 0x7f, 0xbf, 0x6f, + 0xf3, 0xfe, 0xff, 0xe7, 0xbf, + 0x7f, 0xff, 0xff, 0x5f, 0xaf, 0xf1, 0xfc, 0xf7, + 0xff, 0x77, 0xfe, 0xff, 0xdf, 0xff, 0xdf, 0xff, + 0xe3, 0x9e, 0x7f, 0x7a, 0xe3, + 0xff, 0xff, 0x6f, 0xff, 0xaf, 0xfc, 0xff, 0xff, + 0xfe, 0xfe, 0xfe, 0xff, 0xff, 0xff, 0xf3, 0xfb, + 0xf7, 0xff, 0xf9, 0xfe, 0xff, + 0x3f, 0x70, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff, + 0xff, 0x0f, 0x0f, 0xf1, 0xf1, 0xff, 0xf7, 0xff, + 0xef, 0xff, 0xf7, 0x8c, 0x1e, + 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xf7, 0xff, 0x8f, + 0x8f, 0x88, 0xf1, 0xf1, 0xef, 0xff, 0xf7, 0xff, + 0xee, 0x97, 0x1e, 0x01, 0x61, + 0xbf, 0xf0, 0xfa, 0xfd, 0x75, 0xff, 0xf5, 0xff, + 0xff, 0x8f, 0x9f, 0xe1, 0xf1, 0xff, 0xf7, 0xef, + 0xfe, 0xff, 0xff, 0x8f, 0x1f, + 0xff, 0xfa, 0x7f, 0xff, 0xfd, 0xff, 0xfd, 0xff, + 0x9f, 0x9f, 0xf9, 0xf9, 0xff, 0xef, 0xf7, 0xff, + 0xff, 0xff, 0x9e, 0x0f, 0x75, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xff, 0xf7, 0xf7, 0xff, 0xef, 0xf7, 0xe7, 0xef, + 0xef, 0xef, 0xff, 0xff, 0xef, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xf8, 0xf7, 0xff, 0xf7, 0xff, 0xf7, 0xe7, 0xef, + 0x9f, 0x6f, 0xf0, 0xff, 0xff, + 0x7f, 0xf8, 0xff, 0xff, 0xfd, 0xff, 0xfd, 0x8f, + 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf7, 0xef, + 0xf7, 0xff, 0xff, 0x9d, 0x7e, + 0xbf, 0xff, 0x78, 0xff, 0xfd, 0xff, 0xfd, 0xf7, + 0xff, 0xf7, 0x8f, 0xf7, 0xf0, 0xf7, 0xf7, 0xff, + 0xf7, 0xef, 0xfe, 0xe7, 0x9f, + 0xff, 0x8f, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xf8, 0x8f, 0xff, 0xf8, 0xff, 0xef, + 0xff, 0xff, 0x8e, 0x6f, 0xe1, + 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xef, 0xef, 0xff, 0x9f, 0x7f, + 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x9f, + 0xf7, 0xfb, 0x07, 0xe7, 0x78, 0xf7, 0x8f, 0x7e, + 0xf1, 0x9f, 0x7f, 0xff, 0x9e, + 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xf7, 0x8f, 0x6f, 0x80, 0xff, 0xf1, 0xff, 0xff, + 0xef, 0xff, 0xfe, 0x9f, 0x7f, + 0xff, 0x88, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x9f, 0xef, 0x81, 0x7f, 0xf0, 0xff, 0xfe, + 0xff, 0xff, 0xef, 0x9f, 0x7f, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x97, 0x77, 0xf8, 0xff, 0xef, 0xff, 0xf7, 0xff, + 0xef, 0xef, 0x8f, 0x76, 0xf1, + 0xff, 0xff, 0xff, 0xff, 0xf7, 0x0f, 0xf7, 0x88, + 0xf7, 0xf0, 0xff, 0xff, 0xef, 0xff, 0xef, 0x8e, + 0x07, 0x99, 0x61, 0xe1, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xf7, + 0xff, 0xff, 0xf7, 0xf7, 0xef, 0xff, 0xe7, 0xee, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xf7, 0xff, + 0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xef, 0xff, + 0xf7, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xef, 0xff, 0xe7, 0xff, + 0xf6, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xff, + 0xf7, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x6f, 0xff, 0xe7, 0xff, + 0xf7, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xf7, 0xff, + 0xff, 0xf7, 0xff, 0xff, 0xef, 0xff, 0xef, 0xff, + 0x97, 0xee, 0xf9, 0xf7, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x80, 0x88, 0xff, 0xf8, + 0xff, 0xff, 0xf7, 0xff, 0x0f, 0x1f, 0x79, 0x9b, + 0x7f, 0xf0, 0xfe, 0xff, 0xff, + 0xff, 0x4f, 0x7b, 0xf7, 0xf7, 0xf8, 0x0f, 0xff, + 0x00, 0xff, 0xd0, 0x4f, 0x75, 0x8c, 0x79, 0xff, + 0x8f, 0x7f, 0x81, 0x7e, 0xb1, + 0xff, 0xf7, 0xff, 0xfe, 0x8f, 0x7f, 0x70, 0xf0, + 0xff, 0xf7, 0x7f, 0xff, 0xf7, 0xff, 0x84, 0x0e, + 0x73, 0xff, 0xf7, 0xff, 0xff, + 0x3f, 0xbd, 0xfd, 0xfb, 0xf7, 0xe8, 0xff, 0xff, + 0x78, 0xf0, 0x3f, 0xbf, 0xe3, 0x9b, 0x6f, 0xff, + 0x97, 0x1f, 0x7f, 0xcf, 0xfe, + 0xff, 0xf8, 0xf7, 0xff, 0x8f, 0x80, 0xff, 0xf8, + 0xff, 0x8f, 0x78, 0xf0, 0x7f, 0x9f, 0x7f, 0x9b, + 0x7f, 0xf1, 0xff, 0x97, 0x7f, + 0xff, 0xff, 0x07, 0xff, 0x87, 0x7f, 0xf0, 0xf8, + 0xff, 0x7f, 0xfb, 0x7f, 0xee, 0xfb, 0x99, 0x19, + 0x73, 0xef, 0xf7, 0xef, 0xff, + 0xbf, 0x87, 0x04, 0xfc, 0xff, 0x08, 0xf7, 0xff, + 0x7b, 0x7f, 0x8e, 0x8f, 0xf9, 0x98, 0x6f, 0xf3, + 0xff, 0xef, 0xff, 0xff, 0xdf, + 0xff, 0xff, 0x73, 0xff, 0xf7, 0x9f, 0xf8, 0xfb, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x3d, + 0x61, 0xff, 0xef, 0xff, 0xff, + 0xff, 0x7f, 0x07, 0xff, 0xf8, 0x78, 0xff, 0xee, + 0xfb, 0xff, 0xff, 0xff, 0x87, 0x1f, 0x71, 0xe3, + 0xff, 0xfb, 0xff, 0xff, 0xff, + 0xff, 0x77, 0x8b, 0x7f, 0xf8, 0x7f, 0xff, 0xff, + 0x07, 0xe7, 0xfa, 0x77, 0x8f, 0x7f, 0xff, 0xef, + 0xf1, 0xef, 0x9f, 0x77, 0xf9, + 0xff, 0xf8, 0x73, 0x8f, 0xf8, 0x0f, 0x88, 0x88, + 0xf8, 0x98, 0x77, 0x78, 0x8f, 0x6f, 0x87, 0x7b, + 0xf7, 0xff, 0xef, 0x87, 0x6f, + 0xbf, 0x7f, 0xf0, 0xff, 0x8f, 0x7f, 0xff, 0xff, + 0x7e, 0xff, 0x9f, 0x7f, 0xf0, 0xff, 0xff, 0xeb, + 0xef, 0xff, 0xfb, 0xff, 0x9f, + 0xff, 0xff, 0xff, 0x77, 0xf8, 0x7f, 0xf8, 0xf7, + 0xff, 0x7f, 0xf7, 0xff, 0x9f, 0x7f, 0x9b, 0x6f, + 0xf1, 0xfe, 0xff, 0xfe, 0xff, + 0x7f, 0x7f, 0x8f, 0xff, 0x8f, 0xff, 0x7f, 0x8f, + 0xff, 0x70, 0xfb, 0x6f, 0xff, 0xff, 0xff, 0xf5, + 0xf9, 0xff, 0xff, 0xff, 0xf4, + 0xff, 0x87, 0xff, 0x74, 0xff, 0x7f, 0xff, 0xff, + 0x7e, 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, + 0xe9, 0xff, 0xf7, 0xff, 0xff, + 0xbf, 0x78, 0xf8, 0x7f, 0xf7, 0xff, 0xff, 0xff, + 0xf7, 0x07, 0x1f, 0xe1, 0xf1, 0xff, 0xf7, 0xff, + 0xef, 0xef, 0xff, 0x8e, 0x0f, + 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, + 0x9f, 0x88, 0xf1, 0xe1, 0xff, 0xef, 0xf7, 0xef, + 0xfe, 0x9f, 0x0f, 0x09, 0x71, + 0xbf, 0xf0, 0xf8, 0xff, 0x77, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xf7, 0xff, + 0xfe, 0xf7, 0xff, 0x8e, 0x1f, + 0x7f, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x8f, 0xf9, 0xf8, 0xfe, 0xff, 0xe7, 0xf7, + 0xff, 0xff, 0x96, 0x0f, 0x61, + 0x7f, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0xef, 0xff, 0xf7, 0xe7, 0xef, + 0xff, 0xe7, 0xff, 0xf7, 0xfe, + 0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xf8, 0xef, 0xef, 0xef, 0xff, 0xf7, 0xf7, 0xff, + 0x9f, 0x67, 0xf0, 0xff, 0xff, + 0x7f, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0x8f, 0xff, 0xe0, 0xf7, 0xff, 0xf7, 0xfe, + 0xf7, 0xf7, 0xff, 0x8f, 0x6e, + 0x3f, 0xfb, 0x7c, 0xff, 0xff, 0xff, 0xf7, 0xff, + 0xff, 0xe7, 0x9f, 0xef, 0xf0, 0xff, 0xe7, 0xef, + 0xf7, 0xef, 0xf6, 0xf6, 0x87, + 0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xf4, 0x9f, 0xff, 0xfc, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0x7f, 0xf0, + 0x7f, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x87, 0xff, 0xe8, 0xff, 0xf7, 0xff, 0xff, + 0xef, 0xe7, 0xf7, 0x8f, 0x6f, + 0x3f, 0xff, 0xfc, 0xff, 0x8f, 0x7f, 0xf0, 0xcf, + 0xef, 0xe8, 0x1b, 0xef, 0x7c, 0xff, 0x8f, 0x7e, + 0xe1, 0x97, 0x77, 0xff, 0x9e, + 0xff, 0x80, 0x7f, 0xfc, 0xff, 0x7f, 0xff, 0xff, + 0xf7, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xfe, + 0xef, 0xff, 0xff, 0x9f, 0x7f, + 0xff, 0x84, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x6f, 0x9f, 0xff, 0x91, 0x7f, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xff, 0xfb, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, + 0x1f, 0x77, 0xf8, 0xf7, 0xef, 0xff, 0xf7, 0xff, + 0xf7, 0xef, 0x87, 0x67, 0xf1, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x8b, 0x8c, + 0xf0, 0xf8, 0xf7, 0xff, 0xef, 0xff, 0xe7, 0x9e, + 0x67, 0x89, 0x77, 0xf1, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, + 0xff, 0xef, 0xfb, 0xff, 0xef, 0xff, 0xe7, 0xff, + 0xf7, 0xf7, 0xff, 0xff, 0xf7, + 0xbf, 0x87, 0xf8, 0xf8, 0xf7, 0x7f, 0xfb, 0xff, + 0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xe7, 0xfe, + 0xf7, 0xff, 0xff, 0xff, 0x8e, + 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xfb, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, + 0xf7, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0xfb, 0xff, 0xfb, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, + 0xf7, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x7f, 0xf7, 0xff, 0x8b, 0xff, + 0xfc, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xee, 0xff, 0xf6, 0xff, + 0xff, 0xf7, 0x8f, 0xbf, 0xf9, 0x8f, 0xff, 0xf0, + 0xff, 0xff, 0x7f, 0xff, 0x1f, 0x1f, 0x71, 0x89, + 0x7f, 0xf1, 0xff, 0xff, 0xff, + 0xff, 0x4f, 0xb8, 0xc6, 0xfb, 0xfd, 0x0f, 0xff, + 0x00, 0xff, 0xd0, 0x7f, 0x79, 0x90, 0x7f, 0xf9, + 0x8f, 0x7f, 0x81, 0x7f, 0x81, + 0xff, 0xff, 0xcf, 0xff, 0xb0, 0x4f, 0x77, 0xf4, + 0xff, 0xff, 0x7f, 0xe7, 0xee, 0xff, 0x97, 0x07, + 0x69, 0xf1, 0xf7, 0xff, 0xff, + 0x3f, 0xba, 0xff, 0x4d, 0xfe, 0xe5, 0xff, 0xff, + 0x7f, 0xef, 0xbf, 0x9f, 0xe7, 0x9f, 0x77, 0xe9, + 0x9f, 0x1f, 0x79, 0xc1, 0xfe, + 0xff, 0xf8, 0xf7, 0x3f, 0xff, 0x9f, 0xf7, 0xf8, + 0xff, 0x87, 0x7f, 0xf0, 0x7f, 0x97, 0x7f, 0x89, + 0x7e, 0xf1, 0xff, 0x9f, 0x7f, + 0xff, 0xff, 0x37, 0xbf, 0xb3, 0x7f, 0xf2, 0xff, + 0xff, 0xf7, 0xff, 0x7f, 0x7b, 0xfe, 0x87, 0x1f, + 0x71, 0xf1, 0xff, 0x7f, 0xfb, + 0xff, 0xff, 0x70, 0xb7, 0xfe, 0x7b, 0xff, 0xf3, + 0xbf, 0xf7, 0xff, 0xff, 0xf9, 0x9f, 0x7f, 0xf1, + 0xff, 0xf7, 0xff, 0xff, 0xfb, + 0xbf, 0xff, 0xf4, 0xcf, 0x87, 0xd8, 0xf8, 0xf8, + 0xff, 0xff, 0x8f, 0xff, 0xe9, 0xff, 0x8f, 0x1f, + 0x71, 0xff, 0xef, 0xff, 0x8d, + 0xff, 0xff, 0x87, 0xbf, 0xf9, 0x3f, 0xff, 0xf7, + 0xff, 0xff, 0xff, 0xff, 0x9f, 0x1f, 0x71, 0xf9, + 0xff, 0x7b, 0xff, 0xfe, 0xff, + 0xff, 0xff, 0xcb, 0xff, 0xbd, 0x7f, 0xfb, 0xff, + 0x8f, 0xff, 0xf8, 0x7f, 0x9f, 0x7f, 0xf1, 0xef, + 0xff, 0xf7, 0x8f, 0x7f, 0xf9, + 0xff, 0xf8, 0x43, 0x8f, 0xc4, 0x75, 0x7d, 0xff, + 0xff, 0x97, 0x7f, 0x78, 0x8f, 0x6f, 0x99, 0x17, + 0x19, 0x71, 0xf9, 0x8f, 0x6f, + 0xbf, 0x7f, 0xf0, 0x8f, 0xf6, 0x7d, 0x37, 0xff, + 0xff, 0xff, 0x9f, 0x7f, 0xe0, 0xff, 0xff, 0xef, + 0xff, 0xf7, 0xfb, 0xff, 0x8f, + 0xff, 0xff, 0xbf, 0x77, 0x8e, 0xff, 0xf0, 0xff, + 0xff, 0xf7, 0xf7, 0x7f, 0x97, 0x7f, 0x99, 0x7f, + 0xf9, 0xfe, 0xff, 0xfe, 0xff, + 0x7f, 0xff, 0xff, 0xcf, 0xbf, 0xf9, 0xfa, 0xff, + 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xf7, 0x8f, 0x7f, 0x71, 0xf6, + 0xff, 0xff, 0xff, 0x7f, 0xb7, 0xfe, 0xfb, 0xff, + 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xff, 0xff, 0xf7, 0xff, 0xff, + 0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0x08, 0x0f, 0xf1, 0xf1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8e, 0x0e, + 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f, + 0x8f, 0x80, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0x8f, 0x0e, 0x01, 0x71, + 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0x8f, 0x0f, + 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8e, 0x0f, 0x71, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x7f, 0xf0, 0xff, 0xff, + 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0x88, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7e, + 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf7, 0x8f, 0xf7, 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0xff, 0x8f, + 0xff, 0x87, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xf8, 0x8f, 0xf7, 0xf8, 0xff, 0xff, + 0xff, 0xff, 0x8e, 0x7f, 0xf1, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xdf, + 0xff, 0xf6, 0x07, 0xff, 0x78, 0xff, 0x8f, 0x7e, + 0xf1, 0x9f, 0x7f, 0xfd, 0x8e, + 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xf7, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x8f, 0x7f, + 0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x77, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0x6e, 0xf1, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x8f, 0x88, + 0xf0, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8e, + 0x7f, 0x81, 0x7f, 0xf1, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xf7, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0x87, 0xff, + 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xfe, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x3f, 0x8f, 0xf0, 0x85, 0xff, 0xf0, + 0xff, 0xff, 0xff, 0x7f, 0x0d, 0x0f, 0x71, 0x81, + 0x7e, 0xf1, 0xfe, 0xff, 0xff, + 0xff, 0x5f, 0x3d, 0xf0, 0xf5, 0xfa, 0x0f, 0xff, + 0x00, 0xff, 0x80, 0x0f, 0xf1, 0x88, 0x7f, 0xf1, + 0x8f, 0x7e, 0x81, 0x7e, 0xc1, + 0xff, 0xff, 0xff, 0xff, 0xba, 0x4f, 0x75, 0xfa, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0x0f, + 0x71, 0xf1, 0xff, 0xff, 0xff, + 0x3f, 0xbf, 0xff, 0xcf, 0xff, 0xfa, 0xff, 0xfe, + 0x7f, 0xdf, 0x7f, 0xf4, 0xff, 0x8f, 0x7f, 0xf1, + 0x8f, 0x0f, 0x71, 0xf1, 0xbe, + 0xff, 0xf8, 0xf7, 0xbb, 0x7f, 0x85, 0xff, 0xf0, + 0xff, 0x8f, 0x7f, 0xf0, 0x7f, 0x87, 0x7f, 0x81, + 0x7e, 0xf1, 0x8f, 0x0f, 0x71, + 0xff, 0xff, 0x87, 0x8f, 0x8d, 0xfd, 0xf5, 0xff, + 0xfb, 0xff, 0xff, 0xff, 0xf7, 0xfe, 0x8f, 0x0f, + 0x71, 0xf1, 0xfe, 0x7f, 0xf7, + 0xbf, 0x07, 0xc0, 0xbf, 0xf7, 0xfd, 0xff, 0xff, + 0xbf, 0xff, 0x85, 0x8f, 0xf9, 0x8f, 0x7f, 0xf1, + 0xff, 0x7f, 0xf6, 0xff, 0x83, + 0xff, 0xff, 0xf4, 0xff, 0x8f, 0xda, 0xf0, 0xb6, + 0xdf, 0xfd, 0xf6, 0xff, 0xf9, 0xff, 0x8f, 0x1f, + 0x71, 0xfd, 0x8f, 0x7b, 0xfd, + 0xff, 0xff, 0xb7, 0x8f, 0xf0, 0xbd, 0xff, 0xfd, + 0xf7, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0xf1, + 0xff, 0x7b, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xba, 0x7f, 0xf5, 0xf7, + 0x0f, 0xf7, 0xf0, 0x7f, 0x87, 0x7f, 0xf1, 0xff, + 0xff, 0xfe, 0x8f, 0x7f, 0xf1, + 0xff, 0xf8, 0x47, 0x8f, 0xca, 0x70, 0x7a, 0xff, + 0xff, 0x8f, 0x7f, 0x70, 0x8f, 0x7f, 0x81, 0x0e, + 0x01, 0x01, 0x71, 0x81, 0x7f, + 0xbf, 0x7f, 0xf0, 0x8f, 0xff, 0x70, 0x3f, 0xff, + 0xfd, 0xfe, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0xfb, 0xff, 0x8f, + 0xff, 0xff, 0xbf, 0x7f, 0x85, 0x7f, 0xf0, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0x81, 0x7f, + 0x81, 0xfe, 0xf1, 0xff, 0xff, + 0x7f, 0xff, 0xff, 0xcf, 0x87, 0xfa, 0x75, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0x7f, 0x70, 0xfe, + 0xff, 0x87, 0xff, 0x4b, 0xbf, 0x7f, 0xfd, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xfe, 0xff, 0xfe, 0xff, + 0x3f, 0x78, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0x7f, 0xff, + 0xff, 0xff, 0xff, 0x8e, 0x0e, + 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0x7f, 0x8f, + 0x8f, 0x00, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0x8f, 0x0e, 0x01, 0x71, + 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0x7f, 0xff, + 0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0x8f, 0x0f, + 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8e, 0x0f, 0x71, + 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0x7f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0x7f, 0x8f, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x7f, 0xf0, 0xff, 0xff, + 0x7f, 0xf8, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff, + 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7e, + 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0x7f, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0xff, 0x8f, + 0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff, + 0xff, 0xff, 0x8e, 0x7f, 0xf1, + 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x8f, + 0xff, 0xfc, 0x8f, 0xff, 0xf0, 0xff, 0x8f, 0x7e, + 0xf1, 0x8f, 0x7f, 0xf3, 0x8e, + 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0x8f, 0x7f, 0x80, 0x7f, 0xf1, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x8f, 0x7f, + 0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x8f, 0x7f, 0x81, 0x7f, 0xf0, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0x7f, 0xf1, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0xff, 0x80, + 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x8e, + 0x0f, 0x01, 0x71, 0xf0, 0xff, + 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xef, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0xff, 0xff, 0xf7, + 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, + 0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, 0xfe, 0xff, + 0xff, 0xff, 0xff, 0xfe, 0x8f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7e, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7e, + 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0xff, + 0x7f, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, + 0x8f, 0xfe, 0xf0, 0xff, 0xff, + 0xbf, 0xff, 0x0e, 0x8f, 0x70, 0x80, 0xff, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0x0f, 0x7f, 0xf1, 0x0f, + 0x7f, 0xf1, 0xfe, 0xff, 0x9f, + 0xbf, 0x1f, 0xfb, 0x0c, 0xff, 0xf0, 0x8f, 0xff, + 0x00, 0xff, 0xb0, 0x3f, 0x71, 0x80, 0xff, 0xf1, + 0x8f, 0x7f, 0x81, 0x7e, 0xc1, + 0xff, 0xff, 0xff, 0x7f, 0x8f, 0x0f, 0x70, 0xf0, + 0x8f, 0x7f, 0x70, 0xcf, 0x8f, 0xff, 0x71, 0x0f, + 0x7e, 0xf1, 0x8f, 0x7f, 0xf1, + 0x7f, 0xff, 0x7f, 0x0f, 0xff, 0x78, 0x8f, 0x8f, + 0x70, 0x70, 0x7f, 0xfe, 0xff, 0x8f, 0xff, 0x70, + 0xff, 0xfe, 0xff, 0xff, 0xbe, + 0xff, 0xf8, 0xf7, 0x0b, 0xf7, 0x88, 0xf7, 0xf0, + 0x8f, 0x8f, 0x70, 0xf0, 0x7e, 0x73, 0xff, 0x8f, + 0x7e, 0xf0, 0xff, 0x8f, 0x7f, + 0xff, 0x78, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, + 0xff, 0x8f, 0x77, 0x70, 0x77, 0x7f, 0xff, 0x7f, + 0xff, 0xff, 0xfe, 0x8f, 0x7f, + 0xff, 0xff, 0x77, 0x8f, 0xff, 0xf0, 0xff, 0xff, + 0x77, 0x7f, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xef, 0x7f, 0xff, 0xbf, + 0xbf, 0xff, 0x74, 0xff, 0xff, 0x8f, 0xff, 0xfc, + 0x0f, 0xf3, 0x8c, 0xff, 0xfd, 0xff, 0xff, 0x8f, + 0x7f, 0xf1, 0x8f, 0x7d, 0x83, + 0xff, 0x7f, 0x77, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0xf7, 0x7f, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x78, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, + 0x0f, 0x8f, 0x70, 0x70, 0xf7, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8e, 0x0f, 0x71, + 0xff, 0xf8, 0xf7, 0x7f, 0xff, 0x8f, 0x8f, 0x80, + 0x80, 0x81, 0x70, 0x70, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0x6f, 0x8f, 0x0f, 0x71, + 0xbf, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7b, 0xff, 0x9f, 0xff, 0x70, 0xff, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xfe, 0x8f, + 0xff, 0x87, 0x7f, 0x78, 0xfe, 0xff, 0x9e, 0xff, + 0xf2, 0x7f, 0xff, 0x0f, 0xff, 0xf0, 0xff, 0xef, + 0xff, 0x7f, 0xff, 0xff, 0xff, + 0x7f, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0xfe, 0x8f, + 0xff, 0x70, 0xff, 0x7f, 0xff, 0xff, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xfe, + 0xff, 0xff, 0x7f, 0xf7, 0xff, 0xfe, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xaf, 0x0f, + 0x70, 0xd1, 0xff, 0xf8, 0xfe, + 0xff, 0xff, 0xff, 0xf7, 0xaf, 0x8f, 0xfa, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0x8f, 0x0f, + 0x79, 0xe1, 0xff, 0xfe, 0xff, + 0xbf, 0xff, 0xff, 0x7a, 0x8f, 0xff, 0xf0, 0xef, + 0xff, 0xfb, 0xff, 0xaf, 0xff, 0xfb, 0x8f, 0x7f, + 0xf1, 0xdf, 0xff, 0xf9, 0xff, + 0xbf, 0xff, 0xff, 0xf7, 0xff, 0xaf, 0xff, 0xba, + 0xaf, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xef, 0xdf, + 0xff, 0xfd, 0xbe, 0xf7, 0xf5, + 0xff, 0xf8, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, + 0xff, 0x8f, 0xf7, 0xf0, 0xff, 0xff, 0x8f, 0x3f, + 0x11, 0xeb, 0xdb, 0xcf, 0x7f, + 0xbf, 0xf0, 0x8f, 0x87, 0xf0, 0xf0, 0xff, 0xbf, + 0xff, 0x8f, 0xff, 0xf1, 0x8f, 0x0f, 0x31, 0xf1, + 0x9f, 0xdf, 0xf9, 0x85, 0x7f, + 0xbf, 0xff, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, + 0xee, 0xff, 0xfb, 0xf7, 0x8f, 0x7f, 0xb1, 0xff, + 0xff, 0xff, 0xff, 0xdf, 0xfd, + 0xff, 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0x80, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x2f, 0x71, + 0xc1, 0x7f, 0xf1, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xbf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xd1, + 0x9f, 0xff, 0x7b, 0xb7, 0xff, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x8f, 0xff, 0xf1, 0xff, 0xff, + 0xff, 0xff, 0xbf, 0xb7, 0xff, + 0xff, 0xa4, 0xf7, 0x88, 0xff, 0xf0, 0xaf, 0xbf, + 0xfb, 0xef, 0xff, 0xf7, 0xff, 0x8f, 0x7f, 0xf1, + 0xff, 0xdd, 0xf7, 0x97, 0x7f, + 0xff, 0xff, 0xf7, 0xff, 0x8f, 0xff, 0xf0, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0xaf, 0x0f, 0xa0, 0xf0, + 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f, + 0x71, 0xb1, 0x37, 0xf7, 0xff, + 0xff, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf0, 0xfe, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xbf, 0xff, 0xf8, 0xf7, 0xff, 0xa7, 0xff, 0xf0, + 0xff, 0xff, 0x8f, 0xfe, 0xf0, 0xff, 0xff, 0x8f, + 0x7f, 0xf1, 0xff, 0xff, 0xcf, + 0xff, 0xff, 0xf7, 0x9f, 0xf7, 0xf3, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0xbf, 0x7f, 0xf9, + 0xff, 0xfe, 0xff, 0xff, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, + 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xbf, 0xbf, + 0xff, 0xff, 0xff, 0xaf, 0xff, 0xf0, 0xff, 0xff, + 0x9f, 0xfe, 0xf1, 0xff, 0xff, 0xcf, 0x7f, 0xf1, + 0xff, 0xff, 0xdf, 0xff, 0xf1, + 0xbf, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xbf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x6f, + 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xbf, + 0xff, 0xf8, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xcf, 0xff, + 0xff, 0xd8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x3f, + 0xff, 0xdf, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff, + 0xff, 0xff, 0xff, 0xef, 0xff, 0xdf, 0x8e, 0x7f, + 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0xbf, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xe1, 0xff, + 0xdf, 0xff, 0x7f, 0xff, 0xbf, + 0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff, + 0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xb1, + 0xff, 0xef, 0xff, 0x7f, 0xff, diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c new file mode 100644 index 0000000..867589f --- /dev/null +++ b/board/sixnet/sixnet.c @@ -0,0 +1,603 @@ +/* + * (C) Copyright 2001, 2002 + * Dave Ellis, SIXNET, dge@sixnetio.com. + * Based on code by: + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * and other contributors to U-Boot. See file CREDITS for list + * of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* for eth_init() */ +#include +#include "sixnet.h" +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +#endif + +#define ORMASK(size) ((-size) & OR_AM_MSK) + +static long ram_size(ulong *, long); + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress (int status) +{ +#if defined(CONFIG_STATUS_LED) +# if defined(STATUS_LED_BOOT) + if (status == 15) { + /* ready to transfer to kernel, make sure LED is proper state */ + status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE); + } +# endif /* STATUS_LED_BOOT */ +#endif /* CONFIG_STATUS_LED */ +} +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + * returns 0 if recognized, -1 if unknown + */ + +int checkboard (void) +{ + puts ("Board: SIXNET SXNI855T\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#error "SXNI855T has no PCMCIA port" +#endif /* CFG_CMD_PCMCIA */ + +/* ------------------------------------------------------------------------- */ + +#define _not_used_ 0xffffffff + +/* UPMB table for dual UART. */ + +/* this table is for 50MHz operation, it should work at all lower speeds */ +const uint duart_table[] = +{ + /* single read. (offset 0 in upm RAM) */ + 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04, + 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05, + + /* burst read. (offset 8 in upm RAM) */ + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* single write. (offset 18 in upm RAM) */ + 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04, + 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05, + + /* burst write. (offset 20 in upm RAM) */ + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* refresh. (offset 30 in upm RAM) */ + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* exception. (offset 3c in upm RAM) */ + _not_used_, _not_used_, _not_used_, _not_used_, +}; + +/* Load FPGA very early in boot sequence, since it must be + * loaded before the 16C2550 serial channels can be used as + * console channels. + * + * Note: Much of the configuration is not complete. The + * stack is in DPRAM since SDRAM has not been initialized, + * so the stack must be kept small. Global variables + * are still in FLASH, so they cannot be written. + * Only the FLASH, DPRAM, immap and FPGA can be addressed, + * the other chip selects may not have been initialized. + * The clocks have been initialized, so udelay() can be + * used. + */ +#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */ +#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */ +#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */ +#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */ + +int board_postclk_init (void) +{ + + /* the data to load to the XCSxxXL FPGA */ + static const unsigned char fpgadata[] = { +# include "fpgadata.c" + }; + + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; +#define porta (immap->im_ioport.iop_padat) + const unsigned char* pdata; + + /* /INITFPGA and DONEFPGA signals are inputs */ + immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE); + + /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */ + porta &= ~FPGA_PROGRAM_L; + + /* Set FPGA as an output */ + immap->im_ioport.iop_padir |= FPGA_PROGRAM_L; + + /* delay a little to make sure FPGA sees it, really + * only need less than a microsecond. + */ + udelay(10); + + /* unassert /PROGRAM */ + porta |= FPGA_PROGRAM_L; + + /* delay while FPGA does last erase, indicated by + * /INITFPGA going high. This should happen within a + * few milliseconds. + */ + /* ### FIXME - a timeout check would be good, maybe flash + * the status LED to indicate the error? + */ + while ((porta & FPGA_INIT_L) == 0) + ; /* waiting */ + + /* write program data to FPGA at the programming address + * so extra /CS1 strobes at end of configuration don't actually + * write to any registers. + */ + fpga = 0xff; /* first write is ignored */ + fpga = 0xff; /* fill byte */ + fpga = 0xff; /* fill byte */ + fpga = 0x4f; /* preamble code */ + fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */ + fpga = 0x4b; /* field check code */ + + pdata = fpgadata; + /* while no error write out each of the 28 byte frames */ + while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L + && pdata < fpgadata + sizeof(fpgadata)) { + + fpga = 0x4f; /* preamble code */ + + /* 21 bytes of data in a frame */ + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); fpga = *(pdata++); + fpga = *(pdata++); + + fpga = 0x4b; /* field check code */ + fpga = 0xff; /* extended write cycle */ + fpga = 0x4b; /* extended write cycle + * (actually 0x4b from bitgen.exe) + */ + fpga = 0xff; /* extended write cycle */ + fpga = 0xff; /* extended write cycle */ + fpga = 0xff; /* extended write cycle */ + } + + fpga = 0xff; /* startup byte */ + fpga = 0xff; /* startup byte */ + fpga = 0xff; /* startup byte */ + fpga = 0xff; /* startup byte */ + +#if 0 /* ### FIXME */ + /* If didn't load all the data or FPGA_DONE is low the load failed. + * Maybe someday stop here and flash the status LED? The console + * is not configured, so can't print an error message. Can't write + * global variables to set a flag (except gd?). + * For now it must work. + */ +#endif + + /* Now that the FPGA is loaded, set up the Dual UART chip + * selects. Must be done here since it may be used as the console. + */ + upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint)); + + memctl->memc_mbmr = DUART_MBMR; + memctl->memc_or5 = DUART_OR_VALUE; + memctl->memc_br5 = DUART_BR5_VALUE; + memctl->memc_or6 = DUART_OR_VALUE; + memctl->memc_br6 = DUART_BR6_VALUE; + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +/* base address for SRAM, assume 32-bit port, valid */ +#define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V) + +/* up to 64MB - will be adjusted for actual size */ +#define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \ + | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR) +/* + * Miscellaneous platform dependent initializations after running in RAM. + */ + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + char* s; + char* e; + int reg; + bd_t *bd = gd->bd; + + memctl->memc_or2 = NVRAM_OR_PRELIM; + memctl->memc_br2 = NVRAM_BR_VALUE; + + /* Is there any SRAM? Is it 16 or 32 bits wide? */ + + /* First look for 32-bit SRAM */ + bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); + + if (bd->bi_sramsize == 0) { + /* no 32-bit SRAM, but there could be 16-bit SRAM since + * it would report size 0 when configured for 32-bit bus. + * Try again with a 16-bit bus. + */ + memctl->memc_br2 |= BR_PS_16; + bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); + } + + if (bd->bi_sramsize == 0) { + memctl->memc_br2 = 0; /* disable select since nothing there */ + } + else { + /* adjust or2 for actual size of SRAM */ + memctl->memc_or2 |= ORMASK(bd->bi_sramsize); + bd->bi_sramstart = CFG_SRAM_BASE; + printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10); + } + + + /* set standard MPC8xx clock so kernel will see the time + * even if it doesn't have a DS1306 clock driver. + * This helps with experimenting with standard kernels. + */ + { + ulong tim; + struct rtc_time tmp; + + rtc_get(&tmp); /* get time from DS1306 RTC */ + + /* convert to seconds since 1970 */ + tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday, + tmp.tm_hour, tmp.tm_min, tmp.tm_sec); + + immap->im_sitk.sitk_rtck = KAPWR_KEY; + immap->im_sit.sit_rtc = tim; + } + + /* set up ethernet address for SCC ethernet. If eth1addr + * is present it gets a unique address, otherwise it + * shares the FEC address. + */ + s = getenv("eth1addr"); + if (s == NULL) + s = getenv("ethaddr"); + for (reg=0; reg<6; ++reg) { + bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e+1 : e; + } + + return (0); +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +void nand_init(void) +{ + unsigned long totlen = nand_probe(CFG_DFLASH_BASE); + + printf ("%4lu MB\n", totlen >> 20); +} +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. + * + * The memory size MUST be a power of 2 for this to work. + * + * The only memory modified is 8 bytes at offset 0. This is important + * since for the SRAM this location is reserved for autosizing, so if + * it is modified and the board is reset before ram_size() completes + * no damage is done. Normally even the memory at 0 is preserved. The + * higher SRAM addresses may contain battery backed RAM disk data which + * must never be corrupted. + */ + +static long ram_size(ulong *base, long maxsize) +{ + volatile long *test_addr; + volatile ulong *base_addr = base; + ulong ofs; /* byte offset from base_addr */ + ulong save; /* to make test non-destructive */ + ulong save2; /* to make test non-destructive */ + long ramsize = -1; /* size not determined yet */ + + save = *base_addr; /* save value at 0 so can restore */ + save2 = *(base_addr+1); /* save value at 4 so can restore */ + + /* is any SRAM present? */ + *base_addr = 0x5555aaaa; + + /* It is important to drive the data bus with different data so + * it doesn't remember the value and look like RAM that isn't there. + */ + *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */ + + if (*base_addr != 0x5555aaaa) + ramsize = 0; /* no RAM present, or defective */ + else { + *base_addr = 0xaaaa5555; + *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */ + if (*base_addr != 0xaaaa5555) + ramsize = 0; /* no RAM present, or defective */ + } + + /* now size it if any is present */ + for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) { + test_addr = (long*)((long)base_addr + ofs); /* location to test */ + + *base_addr = ~*test_addr; + if (*base_addr == *test_addr) + ramsize = ofs; /* wrapped back to 0, so this is the size */ + } + + *base_addr = save; /* restore value at 0 */ + *(base_addr+1) = save2; /* restore value at 4 */ + return (ramsize); +} + +/* ------------------------------------------------------------------------- */ +/* sdram table based on the FADS manual */ +/* for chip MB811171622A-100 */ + +/* this table is for 50MHz operation, it should work at all lower speeds */ + +const uint sdram_table[] = +{ + /* single read. (offset 0 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, + 0x1ff77c47, + + /* precharge and Mode Register Set initialization (offset 5). + * This is also entered at offset 6 to do Mode Register Set + * without the precharge. + */ + 0x1ff77c34, 0xefeabc34, 0x1fb57c35, + + /* burst read. (offset 8 in upm RAM) */ + 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, + 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* single write. (offset 18 in upm RAM) */ + /* FADS had 0x1f27fc04, ... + * but most other boards have 0x1f07fc04, which + * sets GPL0 from A11MPC to 0 1/4 clock earlier, + * like the single read. + * This seems better so I am going with the change. + */ + 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* burst write. (offset 20 in upm RAM) */ + 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, + 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* refresh. (offset 30 in upm RAM) */ + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, + _not_used_, _not_used_, _not_used_, _not_used_, + + /* exception. (offset 3c in upm RAM) */ + 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; + +/* ------------------------------------------------------------------------- */ + +#define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */ + +/* precharge and set Mode Register */ +#define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ + MCR_MB_CS3 | /* chip select */ \ + MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */ + +/* set Mode Register, no precharge */ +#define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ + MCR_MB_CS3 | /* chip select */ \ + MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */ + +/* runs refresh loop twice so get 8 refresh cycles */ +#define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ + MCR_MB_CS3 | /* chip select */ \ + MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */ + +/* MAMR values work in either mamr or mbmr */ +#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \ + ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \ + | MAMR_DSA_1_CYCL /* 1 cycle disable */ \ + | MAMR_RLFA_1X /* Read loop 1 time */ \ + | MAMR_WLFA_1X /* Write loop 1 time */ \ + | MAMR_TLFA_4X) /* Timer loop 4 times */ +/* 8 column SDRAM */ +#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \ + | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \ + | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */ + +/* 9 column SDRAM */ +#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \ + | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \ + | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */ + +/* base address 0, 32-bit port, SDRAM UPM, valid */ +#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V) + +/* up to 256MB, SAM, G5LS - will be adjusted for actual size */ +#define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS) + +/* This is the Mode Select Register value for the SDRAM. + * Burst length: 4 + * Burst Type: sequential + * CAS Latency: 2 + * Write Burst Length: burst + */ +#define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */ + +/* ------------------------------------------------------------------------- */ + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + uint size_sdram = 0; + uint size_sdram9 = 0; + uint base = 0; /* SDRAM must start at 0 */ + int i; + + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + /* Configure the refresh (mostly). This needs to be + * based upon processor clock speed and optimized to provide + * the highest level of performance. + * + * Preliminary prescaler for refresh. + * This value is selected for four cycles in 31.2 us, + * which gives 8192 cycles in 64 milliseconds. + * This may be too fast, but works for any memory. + * It is adjusted to 4096 cycles in 64 milliseconds if + * possible once we know what memory we have. + * + * We have to be careful changing UPM registers after we + * ask it to run these commands. + * + * PTA - periodic timer period for our design is + * 50 MHz x 31.2us + * --------------- = 195 + * 1 x 8 x 1 + * + * 50MHz clock + * 31.2us refresh interval + * SCCR[DFBRG] 0 + * PTP divide by 8 + * 1 chip select + */ + memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */ + memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */ + + /* The SDRAM Mode Register value is shifted left 2 bits since + * A30 and A31 don't connect to the SDRAM for 32-bit wide memory. + */ + memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */ + udelay(200); /* SDRAM needs 200uS before set it up */ + + /* Now run the precharge/nop/mrs commands. */ + memctl->memc_mcr = SDRAM_MCR_PRE; + udelay(2); + + /* Run 8 refresh cycles (2 sets of 4) */ + memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */ + udelay(2); + + /* some brands want Mode Register set after the refresh + * cycles. This shouldn't hurt anything for the brands + * that were happy with the first time we set it. + */ + memctl->memc_mcr = SDRAM_MCR_MRS; + udelay(2); + + memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */ + memctl->memc_or3 = SDRAM_OR_PRELIM; + memctl->memc_br3 = SDRAM_BR_VALUE + base; + + /* Some brands need at least 10 DRAM accesses to stabilize. + * It wont hurt the brands that don't. + */ + for (i=0; i<10; ++i) { + volatile ulong *addr = (volatile ulong *)base; + ulong val; + + val = *(addr + i); + *(addr + i) = val; + } + + /* Check SDRAM memory Size in 8 column mode. + * For a 9 column memory we will get half the actual size. + */ + size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE); + + /* Check SDRAM memory Size in 9 column mode. + * For an 8 column memory we will see at most 4 megabytes. + */ + memctl->memc_mamr = SDRAM_MAMR_9COL; + size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE); + + if (size_sdram < size_sdram9) /* leave configuration at 9 columns */ + size_sdram = size_sdram9; + else /* go back to 8 columns */ + memctl->memc_mamr = SDRAM_MAMR_8COL; + + /* adjust or3 for actual size of SDRAM + */ + memctl->memc_or3 |= ORMASK(size_sdram); + + /* Adjust refresh rate depending on SDRAM type. + * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave + * it at the current (fast) rate. + * For 16, 64 and 128 MBit half the rate will do. + */ + if (size_sdram <= 32 * 1024 * 1024) + memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */ + + return (size_sdram); +} diff --git a/board/sixnet/sixnet.h b/board/sixnet/sixnet.h new file mode 100644 index 0000000..e631874 --- /dev/null +++ b/board/sixnet/sixnet.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Memory map: + * + * ff100000 -> ff13ffff : FPGA CS1 + * ff030000 -> ff03ffff : EXPANSION CS7 + * ff020000 -> ff02ffff : DATA FLASH CS4 + * ff018000 -> ff01ffff : UART B CS6/UPMB + * ff010000 -> ff017fff : UART A CS5/UPMB + * ff000000 -> ff00ffff : IMAP internal to the MPC855T + * f8000000 -> fbffffff : FLASH CS0 up to 64MB + * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB + * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB + */ diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds new file mode 100644 index 0000000..1513a85 --- /dev/null +++ b/board/sixnet/u-boot.lds @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sl8245/Makefile b/board/sl8245/Makefile new file mode 100644 index 0000000..6d11240 --- /dev/null +++ b/board/sl8245/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 - 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sl8245/config.mk b/board/sl8245/config.mk new file mode 100644 index 0000000..022512b --- /dev/null +++ b/board/sl8245/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2001 - 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# SL8245 board +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) +PLATFORM_LIBS += $(shell $(CC) -print-libgcc-file-name) diff --git a/board/sl8245/flash.c b/board/sl8245/flash.c new file mode 100644 index 0000000..553dc98 --- /dev/null +++ b/board/sl8245/flash.c @@ -0,0 +1,488 @@ +/* + * (C) Copyright 2001 - 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#define FLASH_BANK_SIZE 0x800000 +#define MAIN_SECT_SIZE 0x40000 +#define PARAM_SECT1_SIZE 0x20000 +#define PARAM_SECT23_SIZE 0x8000 +#define PARAM_SECT4_SIZE 0x10000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static int write_data (flash_info_t *info, ulong dest, ulong *data); +static void write_via_fpu(vu_long *addr, ulong *data); +static __inline__ unsigned long get_msr(void); +static __inline__ void set_msr(unsigned long msr); + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +/*---------------------------------------------------------------------*/ +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +#define __align__ __attribute__ ((aligned (8))) +static __align__ ulong precmd0[2] = { 0x00aa00aa, 0x00aa00aa }; +static __align__ ulong precmd1[2] = { 0x00550055, 0x00550055 }; +static __align__ ulong cmdid[2] = { 0x00900090, 0x00900090 }; +static __align__ ulong cmderase[2] = { 0x00800080, 0x00800080 }; +static __align__ ulong cmdersusp[2] = { 0x00b000b0, 0x00b000b0 }; +static __align__ ulong cmdsecter[2] = { 0x00300030, 0x00300030 }; +static __align__ ulong cmdprog[2] = { 0x00a000a0, 0x00a000a0 }; +static __align__ ulong cmdres[2] = { 0x00f000f0, 0x00f000f0 }; + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + + write_via_fpu (&addr[0xaaa], precmd0); + write_via_fpu (&addr[0x554], precmd1); + write_via_fpu (&addr[0xaaa], cmdid); + + DEBUGF ("Flash bank # %d:\n" + "\tManuf. ID @ 0x%08lX: 0x%08lX\n" + "\tDevice ID @ 0x%08lX: 0x%08lX\n", + i, + (ulong) (&addr[0]), addr[0], + (ulong) (&addr[2]), addr[2]); + + if ((addr[0] == addr[1]) && (addr[0] == AMD_MANUFACT) && + (addr[2] == addr[3]) && (addr[2] == AMD_ID_LV160T)) { + flash_info[i].flash_id = (FLASH_MAN_AMD & FLASH_VENDMASK) | + (FLASH_AM160T & FLASH_TYPEMASK); + } else { + flash_info[i].flash_id = FLASH_UNKNOWN; + write_via_fpu (addr, cmdres); + goto Done; + } + + DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); + + write_via_fpu (addr, cmdres); + + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + for (j = 0; j < 32; j++) { + flash_info[i].start[j] = CFG_FLASH_BASE + + i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE; + } + flash_info[i].start[32] = + flash_info[i].start[31] + PARAM_SECT1_SIZE; + flash_info[i].start[33] = + flash_info[i].start[32] + PARAM_SECT23_SIZE; + flash_info[i].start[34] = + flash_info[i].start[33] + PARAM_SECT23_SIZE; + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE + flash_protect ( FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[1]); +#else + flash_protect ( FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); +#else + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif +#endif + +Done: + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch ((i = info->flash_id & FLASH_VENDMASK)) { + case (FLASH_MAN_AMD & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor 0x%04x ", i); + break; + } + + switch ((i = info->flash_id & FLASH_TYPEMASK)) { + case (FLASH_AM160T & FLASH_TYPEMASK): + printf ("AM29LV160BT (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type 0x%04x\n", i); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done: + return; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + DEBUGF ("Erase flash bank %d sect %d ... %d\n", + info - &flash_info[0], s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (FLASH_MAN_AMD & FLASH_VENDMASK)) { + printf ("Can erase only AMD flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *) (info->start[sect]); + + DEBUGF ("Erase sect %d @ 0x%08lX\n", sect, (ulong) addr); + + /* Disable interrupts which might cause a timeout + * here. + */ + flag = disable_interrupts (); + + write_via_fpu (&addr[0xaaa], precmd0); + write_via_fpu (&addr[0x554], precmd1); + write_via_fpu (&addr[0xaaa], cmderase); + write_via_fpu (&addr[0xaaa], precmd0); + write_via_fpu (&addr[0x554], precmd1); + write_via_fpu (&addr[0xaaa], cmdsecter); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((addr[0] & 0x00800080) != 0x00800080) || + ((addr[1] & 0x00800080) != 0x00800080)) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + write_via_fpu (addr, cmdersusp); + write_via_fpu (addr, cmdres); + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + write_via_fpu (addr, cmdres); + } + } + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 8 /* flash bus width in bytes */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, cp, msr; + int l, rc, i; + ulong data[2]; + ulong *datah = &data[0]; + ulong *datal = &data[1]; + + DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", + addr, (ulong) src, cnt); + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + msr = get_msr (); + set_msr (msr | MSR_FP); + + wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + *datah = *datal = 0; + + for (i = 0, cp = wp; i < l; i++, cp++) { + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | (*(uchar *) cp); + } + for (; i < FLASH_WIDTH && cnt > 0; ++i) { + char tmp; + + tmp = *src; + + src++; + + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | tmp; + + --cnt; + ++cp; + } + + for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datah << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, data)) != 0) { + set_msr (msr); + return (rc); + } + + wp += FLASH_WIDTH; + } + + /* + * handle FLASH_WIDTH aligned part + */ + while (cnt >= FLASH_WIDTH) { + *datah = *(ulong *) src; + *datal = *(ulong *) (src + 4); + if ((rc = write_data (info, wp, data)) != 0) { + set_msr (msr); + return (rc); + } + wp += FLASH_WIDTH; + cnt -= FLASH_WIDTH; + src += FLASH_WIDTH; + } + + if (cnt == 0) { + set_msr (msr); + return (0); + } + + /* + * handle unaligned tail bytes + */ + *datah = *datal = 0; + for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { + char tmp; + + tmp = *src; + + src++; + + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | tmp; + + --cnt; + } + + for (; i < FLASH_WIDTH; ++i, ++cp) { + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | (*(uchar *) cp); + } + + rc = write_data (info, wp, data); + set_msr (msr); + + return (rc); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, ulong * data) +{ + vu_long *chip = (vu_long *) (info->start[0]); + vu_long *addr = (vu_long *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if (((addr[0] & data[0]) != data[0]) || + ((addr[1] & data[1]) != data[1])) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + write_via_fpu (&chip[0xaaa], precmd0); + write_via_fpu (&chip[0x554], precmd1); + write_via_fpu (&chip[0xaaa], cmdprog); + write_via_fpu (addr, data); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + + while (((addr[0] & 0x00800080) != (data[0] & 0x00800080)) || + ((addr[1] & 0x00800080) != (data[1] & 0x00800080))) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + write_via_fpu (chip, cmdres); + return (1); + } + } + + write_via_fpu (chip, cmdres); + + return (0); +} + +/*----------------------------------------------------------------------- + */ +static void write_via_fpu (vu_long * addr, ulong * data) +{ + __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); + __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); +} + +/*----------------------------------------------------------------------- + */ +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + return msr; +} + +static __inline__ void set_msr (unsigned long msr) +{ + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); +} diff --git a/board/sl8245/sl8245.c b/board/sl8245/sl8245.c new file mode 100644 index 0000000..593eb4e --- /dev/null +++ b/board/sl8245/sl8245.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int checkboard (void) +{ + ulong busfreq = get_bus_freq(0); + char buf[32]; + + printf("Board: SL8245, local bus @ %s MHz\n", strmhz(buf, busfreq)); + return 0; +} + +long int initdram (int board_type) +{ +#ifndef CFG_RAMBOOT + long size; + long new_bank0_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +#else + return CFG_MAX_RAM_SIZE; +#endif +} + +static struct pci_controller hose; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} diff --git a/board/sl8245/u-boot.lds b/board/sl8245/u-boot.lds new file mode 100644 index 0000000..acb9ffd --- /dev/null +++ b/board/sl8245/u-boot.lds @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/smdk2400/Makefile b/board/smdk2400/Makefile new file mode 100644 index 0000000..fc3d48f --- /dev/null +++ b/board/smdk2400/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := smdk2400.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/smdk2400/config.mk b/board/smdk2400/config.mk new file mode 100644 index 0000000..82400bf --- /dev/null +++ b/board/smdk2400/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# SAMSUNG board with S3C2400X (ARM920T) CPU +# +# see http://www.samsung.com/ for more information on SAMSUNG +# + +# +# SAMSUNG has 1 bank of 32 MB DRAM +# +# 0C00'0000 to 0E00'0000 +# +# Linux-Kernel is expected to be at 0cf0'0000, entry 0cf0'0000 +# optionally with a ramdisk at 0c80'0000 +# +# we load ourself to 0CF80000 (must be high enough not to be +# overwritten by the uncompessing Linux kernel) +# +# download area is 0C80'0000 +# + + +TEXT_BASE = 0x0CF80000 diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c new file mode 100644 index 0000000..a108af7 --- /dev/null +++ b/board/smdk2400/flash.c @@ -0,0 +1,491 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include + +#define FLASH_BANK_SIZE 0x1000000 /* 2 x 8 MB */ +#define MAIN_SECT_SIZE 0x40000 /* 2 x 128 kB */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +#define CMD_READ_ARRAY 0x00FF00FF +#define CMD_IDENTIFY 0x00900090 +#define CMD_ERASE_SETUP 0x00200020 +#define CMD_ERASE_CONFIRM 0x00D000D0 +#define CMD_PROGRAM 0x00400040 +#define CMD_RESUME 0x00D000D0 +#define CMD_SUSPEND 0x00B000B0 +#define CMD_STATUS_READ 0x00700070 +#define CMD_STATUS_RESET 0x00500050 + +#define BIT_BUSY 0x00800080 +#define BIT_ERASE_SUSPEND 0x00400040 +#define BIT_ERASE_ERROR 0x00200020 +#define BIT_PROGRAM_ERROR 0x00100010 +#define BIT_VPP_RANGE_ERROR 0x00080008 +#define BIT_PROGRAM_SUSPEND 0x00040004 +#define BIT_PROTECT_ERROR 0x00020002 +#define BIT_UNDEFINED 0x00010001 + +#define BIT_SEQUENCE_ERROR 0x00300030 +#define BIT_TIMEOUT 0x80000000 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F640J3A & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = CFG_FLASH_BASE; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase; + + /* uniform sector size */ + flashbase += MAIN_SECT_SIZE; + } + size += flash_info[i].size; + } + + /* + * Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): + printf ("2x 28F640J3A (64Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: ; +} + +/*----------------------------------------------------------------------- + */ + +int flash_error (ulong code) +{ + /* Check bit patterns */ + /* SR.7=0 is busy, SR.7=1 is ready */ + /* all other flags indicate error on 1 */ + /* SR.0 is undefined */ + /* Timeout is our faked flag */ + + /* sequence is described in Intel 290644-005 document */ + + /* check Timeout */ + if (code & BIT_TIMEOUT) { + puts ("Timeout\n"); + return ERR_TIMOUT; + } + + /* check Busy, SR.7 */ + if (~code & BIT_BUSY) { + puts ("Busy\n"); + return ERR_PROG_ERROR; + } + + /* check Vpp low, SR.3 */ + if (code & BIT_VPP_RANGE_ERROR) { + puts ("Vpp range error\n"); + return ERR_PROG_ERROR; + } + + /* check Device Protect Error, SR.1 */ + if (code & BIT_PROTECT_ERROR) { + puts ("Device protect error\n"); + return ERR_PROG_ERROR; + } + + /* check Command Seq Error, SR.4 & SR.5 */ + if (code & BIT_SEQUENCE_ERROR) { + puts ("Command seqence error\n"); + return ERR_PROG_ERROR; + } + + /* check Block Erase Error, SR.5 */ + if (code & BIT_ERASE_ERROR) { + puts ("Block erase error\n"); + return ERR_PROG_ERROR; + } + + /* check Program Error, SR.4 */ + if (code & BIT_PROGRAM_ERROR) { + puts ("Program error\n"); + return ERR_PROG_ERROR; + } + + /* check Block Erase Suspended, SR.6 */ + if (code & BIT_ERASE_SUSPEND) { + puts ("Block erase suspended\n"); + return ERR_PROG_ERROR; + } + + /* check Program Suspended, SR.2 */ + if (code & BIT_PROGRAM_SUSPEND) { + puts ("Program suspended\n"); + return ERR_PROG_ERROR; + } + + /* OK, no error */ + return ERR_OK; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result, result1; + int iflag, prot, sect; + int rc = ERR_OK; + +#ifdef USE_920T_MMU + int cflag; +#endif + + debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (INTEL_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ +#ifdef USE_920T_MMU + cflag = dcache_status (); + dcache_disable (); +#endif + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + + debug ("Erasing sector %2d @ %08lX... ", + sect, info->start[sect]); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *) (info->start[sect]); + ulong bsR7, bsR7_2, bsR5, bsR5_2; + + /* *addr = CMD_STATUS_RESET; */ + *addr = CMD_ERASE_SETUP; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + do { + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + *addr = CMD_STATUS_RESET; + result = BIT_TIMEOUT; + break; + } + + *addr = CMD_STATUS_READ; + result = *addr; + bsR7 = result & (1 << 7); + bsR7_2 = result & (1 << 23); + } while (!bsR7 | !bsR7_2); + + *addr = CMD_STATUS_READ; + result1 = *addr; + bsR5 = result1 & (1 << 5); + bsR5_2 = result1 & (1 << 21); +#ifdef SAMSUNG_FLASH_DEBUG + printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); + if (bsR5 != 0 && bsR5_2 != 0) + printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); +#endif + + *addr = CMD_READ_ARRAY; + *addr = CMD_RESUME; + + if ((rc = flash_error (result)) != ERR_OK) + goto outahere; +#if 0 + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); +#endif + } + } + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + +#ifdef USE_920T_MMU + if (cflag) + dcache_enable (); +#endif + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_word (flash_info_t * info, ulong dest, + ulong data) +{ + vu_long *addr = (vu_long *) dest; + ulong result; + int rc = ERR_OK; + int iflag; + +#ifdef USE_920T_MMU + int cflag; +#endif + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ +#ifdef USE_920T_MMU + cflag = dcache_status (); + dcache_disable (); +#endif + iflag = disable_interrupts (); + + /* *addr = CMD_STATUS_RESET; */ + *addr = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + do { + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + *addr = CMD_SUSPEND; + result = BIT_TIMEOUT; + break; + } + + *addr = CMD_STATUS_READ; + result = *addr; + } while (~result & BIT_BUSY); + + /* *addr = CMD_READ_ARRAY; */ + *addr = CMD_STATUS_READ; + result = *addr; + + rc = flash_error (result); + + if (iflag) + enable_interrupts (); + +#ifdef USE_920T_MMU + if (cflag) + dcache_enable (); +#endif + *addr = CMD_READ_ARRAY; + *addr = CMD_RESUME; + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = *((vu_long *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 4; + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + + return write_word (info, wp, data); +} diff --git a/board/smdk2400/lowlevel_init.S b/board/smdk2400/lowlevel_init.S new file mode 100644 index 0000000..a5de806 --- /dev/null +++ b/board/smdk2400/lowlevel_init.S @@ -0,0 +1,163 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the Samsung development board by + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +/* + * + * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S + * + * Copyright (C) 2001 Samsung Electronics by chc, 010406 + * + * S3C2400 specific tweaks. + * + */ + +/* memory controller */ +#define BWSCON 0x14000000 +#define BANKCON3 0x14000010 /* for cs8900, ethernet */ + +/* Bank0 */ +#define B0_Tacs 0x0 /* 0 clk */ +#define B0_Tcos 0x0 /* 0 clk */ +#define B0_Tacc 0x7 /* 14 clk */ +#define B0_Tcoh 0x0 /* 0 clk */ +#define B0_Tah 0x0 /* 0 clk */ +#define B0_Tacp 0x0 +#define B0_PMC 0x0 /* normal */ + +/* Bank1 */ +#define B1_Tacs 0x0 /* 0 clk */ +#define B1_Tcos 0x0 /* 0 clk */ +#define B1_Tacc 0x7 /* 14 clk */ +#define B1_Tcoh 0x0 /* 0 clk */ +#define B1_Tah 0x0 /* 0 clk */ +#define B1_Tacp 0x0 +#define B1_PMC 0x0 /* normal */ + +/* Bank2 */ +#define B2_Tacs 0x0 /* 0 clk */ +#define B2_Tcos 0x0 /* 0 clk */ +#define B2_Tacc 0x7 /* 14 clk */ +#define B2_Tcoh 0x0 /* 0 clk */ +#define B2_Tah 0x0 /* 0 clk */ +#define B2_Tacp 0x0 +#define B2_PMC 0x0 /* normal */ + +/* Bank3 - setup for the cs8900 */ +#define B3_Tacs 0x0 /* 0 clk */ +#define B3_Tcos 0x3 /* 4 clk */ +#define B3_Tacc 0x7 /* 14 clk */ +#define B3_Tcoh 0x1 /* 1 clk */ +#define B3_Tah 0x0 /* 0 clk */ +#define B3_Tacp 0x3 /* 6 clk */ +#define B3_PMC 0x0 /* normal */ + +/* Bank4 */ +#define B4_Tacs 0x0 /* 0 clk */ +#define B4_Tcos 0x0 /* 0 clk */ +#define B4_Tacc 0x7 /* 14 clk */ +#define B4_Tcoh 0x0 /* 0 clk */ +#define B4_Tah 0x0 /* 0 clk */ +#define B4_Tacp 0x0 +#define B4_PMC 0x0 /* normal */ + +/* Bank5 */ +#define B5_Tacs 0x0 /* 0 clk */ +#define B5_Tcos 0x0 /* 0 clk */ +#define B5_Tacc 0x7 /* 14 clk */ +#define B5_Tcoh 0x0 /* 0 clk */ +#define B5_Tah 0x0 /* 0 clk */ +#define B5_Tacp 0x0 +#define B5_PMC 0x0 /* normal */ + +/* Bank6 */ +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 /* 3clk */ +#define B6_SCAN 0x1 /* 9 bit */ + +/* Bank7 */ +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x1 /* 9 bit */ + +/* refresh parameter */ +#define REFEN 0x1 /* enable refresh */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ +#define Trp 0x0 /* 2 clk */ +#define Trc 0x3 /* 7 clk */ +#define Tchr 0x2 /* 3 clk */ + +#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */ + + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #52 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word 0x2211d114 /* d->Ethernet, BUSWIDTH=32 */ + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */ + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */ + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */ + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */ + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */ + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */ + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */ + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */ + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */ + .word 0x30 /* MRSR6, CL=3clk */ + .word 0x30 /* MRSR7 */ diff --git a/board/smdk2400/smdk2400.c b/board/smdk2400/smdk2400.c new file mode 100644 index 0000000..cb70218 --- /dev/null +++ b/board/smdk2400/smdk2400.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_MODEM_SUPPORT +static int key_pressed(void); +int mdm_init (bd_t *); +extern void disable_putc(void); +extern void enable_putc(void); +extern int hwflow_onoff(int); +extern int do_mdm_init; /* defined in common/main.c */ +#endif /* CONFIG_MODEM_SUPPORT */ + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* memory and cpu-speed are setup before relocation */ + /* change the clock to be 50 MHz 1:1:1 */ + clk_power->MPLLCON = 0x5c042; + clk_power->CLKDIVN = 0; + /* set up the I/O ports */ + gpio->PACON = 0x3ffff; + gpio->PBCON = 0xaaaaaaaa; + gpio->PBUP = 0xffff; + gpio->PECON = 0x0; + gpio->PEUP = 0x0; +#ifdef CONFIG_HWFLOW + /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */ + /* 10, 10, 00, 00, 10, 00, 10 */ + gpio->PFCON=0xa22; + /* Disable pull-up on Rx, Tx, CTS and RTS pins */ + gpio->PFUP=0x35; +#else + /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ + /* 00, 00, 00, 00, 10, 00, 10 */ + gpio->PFCON = 0x22; + /* Disable pull-up on Rx and Tx pins */ + gpio->PFUP = 0x5; +#endif /* CONFIG_HWFLOW */ + gpio->PGCON = 0x0; + gpio->PGUP = 0x0; + gpio->OPENCR = 0x0; + + /* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */ + gd->bd->bi_arch_number = MACH_TYPE_SMDK2400; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x0C000100; + +#ifdef CONFIG_MODEM_SUPPORT + if (key_pressed()) { + disable_putc(); /* modem doesn't understand banner etc */ + do_mdm_init = 1; + } +#endif /* CONFIG_MODEM_SUPPORT */ + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_MODEM_SUPPORT +static int key_pressed(void) +{ + int rc; + if (1) { /* check for button push here, now just return 1 */ + rc = 1; + } + + return rc; +} +#endif /* CONFIG_MODEM_SUPPORT */ diff --git a/board/smdk2400/u-boot.lds b/board/smdk2400/u-boot.lds new file mode 100644 index 0000000..f4fbf96 --- /dev/null +++ b/board/smdk2400/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/smdk2410/Makefile b/board/smdk2410/Makefile new file mode 100644 index 0000000..4ee21f5 --- /dev/null +++ b/board/smdk2410/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := smdk2410.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/smdk2410/config.mk b/board/smdk2410/config.mk new file mode 100644 index 0000000..1af85da --- /dev/null +++ b/board/smdk2410/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# + +# +# SMDK2410 has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3400'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 33F8'0000 +# +# download area is 3300'0000 +# + + +TEXT_BASE = 0x33F80000 diff --git a/board/smdk2410/flash.c b/board/smdk2410/flash.c new file mode 100644 index 0000000..993946b --- /dev/null +++ b/board/smdk2410/flash.c @@ -0,0 +1,433 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +ulong myflush (void); + + +#define FLASH_BANK_SIZE PHYS_FLASH_SIZE +#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +#define CMD_READ_ARRAY 0x000000F0 +#define CMD_UNLOCK1 0x000000AA +#define CMD_UNLOCK2 0x00000055 +#define CMD_ERASE_SETUP 0x00000080 +#define CMD_ERASE_CONFIRM 0x00000030 +#define CMD_PROGRAM 0x000000A0 +#define CMD_UNLOCK_BYPASS 0x00000020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) + +#define BIT_ERASE_DONE 0x00000080 +#define BIT_RDY_MASK 0x00000080 +#define BIT_PROGRAM_ERROR 0x00000020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = +#if defined(CONFIG_AMD_LV400) + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV400B & FLASH_TYPEMASK); +#elif defined(CONFIG_AMD_LV800) + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV800B & FLASH_TYPEMASK); +#else +#error "Unknown flash configured" +#endif + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j <= 3) { + /* 1st one is 16 KB */ + if (j == 0) { + flash_info[i].start[j] = + flashbase + 0; + } + + /* 2nd and 3rd are both 8 KB */ + if ((j == 1) || (j == 2)) { + flash_info[i].start[j] = + flashbase + 0x4000 + (j - + 1) * + 0x2000; + } + + /* 4th 32 KB */ + if (j == 3) { + flash_info[i].start[j] = + flashbase + 0x8000; + } + } else { + flash_info[i].start[j] = + flashbase + (j - 3) * MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV400B & FLASH_TYPEMASK): + printf ("1x Amd29LV400BB (4Mbit)\n"); + break; + case (AMD_ID_LV800B & FLASH_TYPEMASK): + printf ("1x Amd29LV800BB (8Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done:; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ushort result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip = TMO; + break; + } + + if (!chip + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip = READY; + + if (!chip + && (result & 0xFFFF) & BIT_PROGRAM_ERROR) + chip = ERR; + + } while (!chip); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest; + ushort result; + int rc = ERR_OK; + int cflag, iflag; + int chip; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; + *addr = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + chip = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + chip = ERR | TMO; + break; + } + if (!chip && ((result & 0x80) == (data & 0x80))) + chip = READY; + + if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { + result = *addr; + + if ((result & 0x80) == (data & 0x80)) + chip = READY; + else + chip = ERR; + } + + } while (!chip); + + *addr = CMD_READ_ARRAY; + + if (chip == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + int l; + int i, rc; + ushort data; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_hword (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_hword (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_hword (info, wp, data); +} diff --git a/board/smdk2410/lowlevel_init.S b/board/smdk2410/lowlevel_init.S new file mode 100644 index 0000000..310f2a0 --- /dev/null +++ b/board/smdk2410/lowlevel_init.S @@ -0,0 +1,167 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +/* + * + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S + * + * Copyright (C) 2002 Samsung Electronics SW.LEE + * + */ + +#define BWSCON 0x48000000 + +/* BWSCON */ +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +#define B1_BWSCON (DW32) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) + +/* BANK0CON */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x0 /* 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 +#define B0_PMC 0x0 /* normal */ + +/* BANK1CON */ +#define B1_Tacs 0x0 /* 0clk */ +#define B1_Tcos 0x0 /* 0clk */ +#define B1_Tacc 0x7 /* 14clk */ +#define B1_Tcoh 0x0 /* 0clk */ +#define B1_Tah 0x0 /* 0clk */ +#define B1_Tacp 0x0 +#define B1_PMC 0x0 + +#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0 + +#define B3_Tacs 0x0 /* 0clk */ +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 /* 14clk */ +#define B3_Tcoh 0x1 /* 1clk */ +#define B3_Tah 0x0 /* 0clk */ +#define B3_Tacp 0x3 /* 6clk */ +#define B3_PMC 0x0 /* normal */ + +#define B4_Tacs 0x0 /* 0clk */ +#define B4_Tcos 0x0 /* 0clk */ +#define B4_Tacc 0x7 /* 14clk */ +#define B4_Tcoh 0x0 /* 0clk */ +#define B4_Tah 0x0 /* 0clk */ +#define B4_Tacp 0x0 +#define B4_PMC 0x0 /* normal */ + +#define B5_Tacs 0x0 /* 0clk */ +#define B5_Tcos 0x0 /* 0clk */ +#define B5_Tacc 0x7 /* 14clk */ +#define B5_Tcoh 0x0 /* 0clk */ +#define B5_Tah 0x0 /* 0clk */ +#define B5_Tacp 0x0 +#define B5_PMC 0x0 /* normal */ + +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 +#define B6_SCAN 0x1 /* 9bit */ + +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x1 /* 9bit */ + +/* REFRESH parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x0 /* 2clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x2 /* 3clk */ +#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +/**************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0x32 + .word 0x30 + .word 0x30 diff --git a/board/smdk2410/smdk2410.c b/board/smdk2410/smdk2410.c new file mode 100644 index 0000000..9623aef --- /dev/null +++ b/board/smdk2410/smdk2410.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +#define FCLK_SPEED 1 + +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ +#define M_MDIV 0xC3 +#define M_PDIV 0x4 +#define M_SDIV 0x1 +#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ +#define M_MDIV 0xA1 +#define M_PDIV 0x3 +#define M_SDIV 0x1 +#endif + +#define USB_CLOCK 1 + +#if USB_CLOCK==0 +#define U_M_MDIV 0xA1 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x1 +#elif USB_CLOCK==1 +#define U_M_MDIV 0x48 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x2 +#endif + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->LOCKTIME = 0xFFFFFF; + + /* configure MPLL */ + clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (4000); + + /* configure UPLL */ + clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (8000); + + /* set up the I/O ports */ + gpio->GPACON = 0x007FFFFF; + gpio->GPBCON = 0x00044555; + gpio->GPBUP = 0x000007FF; + gpio->GPCCON = 0xAAAAAAAA; + gpio->GPCUP = 0x0000FFFF; + gpio->GPDCON = 0xAAAAAAAA; + gpio->GPDUP = 0x0000FFFF; + gpio->GPECON = 0xAAAAAAAA; + gpio->GPEUP = 0x0000FFFF; + gpio->GPFCON = 0x000055AA; + gpio->GPFUP = 0x000000FF; + gpio->GPGCON = 0xFF95FFBA; + gpio->GPGUP = 0x0000FFFF; + gpio->GPHCON = 0x002AFAAA; + gpio->GPHUP = 0x000007FF; + + /* arch number of SMDK2410-Board */ + gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + icache_enable(); + dcache_enable(); + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/board/smdk2410/u-boot.lds b/board/smdk2410/u-boot.lds new file mode 100644 index 0000000..f4fbf96 --- /dev/null +++ b/board/smdk2410/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/snmc/qs850/Makefile b/board/snmc/qs850/Makefile new file mode 100644 index 0000000..e5d8446 --- /dev/null +++ b/board/snmc/qs850/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/snmc/qs850/config.mk b/board/snmc/qs850/config.mk new file mode 100644 index 0000000..905f692 --- /dev/null +++ b/board/snmc/qs850/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2002-2003 +# Simple Network Magic Corporation, dnevil@snmc.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# QS850 +# Start address of Bootloader in Flash +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c new file mode 100644 index 0000000..d2f169b --- /dev/null +++ b/board/snmc/qs850/flash.c @@ -0,0 +1,616 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +#define FLASH_WORD_SIZE unsigned long +#define FLASH_ID_MASK 0xFFFFFFFF + +/*----------------------------------------------------------------------- + * Functions + */ +/* stolen from esteem192e/flash.c */ +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); + +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + volatile FLASH_WORD_SIZE* flash_base; + + /* Init: no FLASHes known */ + for (i=0; isize / (info->sector_count - 8 + 1); + small_sect_size = large_sect_size / 8; + + if (info->flash_id & FLASH_BTYPE) { + + /* set sector offsets for bottom boot block type */ + for (i = 0; i < 7; i++) { + info->start[i] = base; + base += small_sect_size; + } + + for (; i < info->sector_count; i++) { + info->start[i] = base; + base += large_sect_size; + } + } + else + { + /* set sector offsets for top boot block type */ + for (i = 0; i < (info->sector_count - 8); i++) { + info->start[i] = base; + base += large_sect_size; + } + + for (; i < info->sector_count; i++) { + info->start[i] = base; + base += small_sect_size; + } + } +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar botboot[]=", bottom boot sect)\n"; + uchar topboot[]=", top boot sector)\n"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_SST: + printf ("SST "); + break; + case FLASH_MAN_STM: + printf ("STM "); + break; + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + if (info->flash_id & 0x0001 ) { + boottype = botboot; + } else { + boottype = topboot; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit%s",boottype); + break; + case FLASH_AM160T: + printf ("AM29LV160T (16 Mbit%s",boottype); + break; + case FLASH_AMDL163T: + printf ("AM29DL163T (16 Mbit%s",boottype); + break; + case FLASH_AMDL163B: + printf ("AM29DL163B (16 Mbit%s",boottype); + break; + case FLASH_AM320B: + printf ("AM29LV320B (32 Mbit%s",boottype); + break; + case FLASH_AM320T: + printf ("AM29LV320T (32 Mbit%s",boottype); + break; + case FLASH_AMDL323T: + printf ("AM29DL323T (32 Mbit%s",boottype); + break; + case FLASH_AMDL323B: + printf ("AM29DL323B (32 Mbit%s",boottype); + break; + case FLASH_AMDL322T: + printf ("AM29DL322T (32 Mbit%s",boottype); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + + +/*----------------------------------------------------------------------- + * The following code cannot be run from FLASH! + */ +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) +{ + short i; + ulong base = (ulong)addr; + FLASH_WORD_SIZE value; + + /* Write auto select command: read Manufacturer ID */ + + /* + * Note: if it is an AMD flash and the word at addr[0000] + * is 0x00890089 this routine will think it is an Intel + * flash device and may(most likely) cause trouble. + */ + + addr[0x0000] = 0x00900090; + if(addr[0x0000] != 0x00890089){ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + } + value = addr[0]; + + switch (value) { + case (AMD_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_FUJ; + break; + case (STM_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_STM; + break; + case (SST_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_SST; + break; + case (INTEL_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case (AMD_ID_LV160T & FLASH_ID_MASK): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV160B & FLASH_ID_MASK): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_DL163T & FLASH_ID_MASK): + info->flash_id += FLASH_AMDL163T; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_DL163B & FLASH_ID_MASK): + info->flash_id += FLASH_AMDL163B; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_DL323T & FLASH_ID_MASK): + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (AMD_ID_DL323B & FLASH_ID_MASK): + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (AMD_ID_DL322T & FLASH_ID_MASK): + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + default: + /* FIXME*/ + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets(base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP) ) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); + addr[0] = (0x00300030 & FLASH_ID_MASK); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); + while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != + (0x00800080&FLASH_ID_MASK) ) + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* AMD stuff */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + return (0); +} diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c new file mode 100644 index 0000000..637f125 --- /dev/null +++ b/board/snmc/qs850/qs850.c @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2002 + * Simple Network Magic Corporation, dnevil@snmc.com + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "mpc8xx.h" + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04, + 0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00, + 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05, + 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, + 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07, + 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00, + 0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04, + 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, + 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04, + 0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04, + 0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37 +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Test ID string (QS850, QS823, ...) + * + * Always return 1 + */ + +int checkboard (void) +{ + char *s, *e; + char buf[64]; + int i; + + i = getenv_r("serial#", buf, sizeof(buf)); + s = (i>0) ? buf : NULL; + +#ifdef CONFIG_QS850 + if (!s || strncmp(s, "QS850", 5)) { + puts ("### No HW ID - assuming QS850"); +#endif +#ifdef CONFIG_QS823 + if (!s || strncmp(s, "QS823", 5)) { + puts ("### No HW ID - assuming QS823"); +#endif + } else { + for (e=s; *e; ++e) { + if (*e == ' ') + break; + } + + for ( ; sim_memctl; + long int size; + + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + /* + * Prescaler for refresh + */ + memctl->memc_mptpr = CFG_MPTPR; + + /* + * Map controller bank 1 to the SDRAM address + */ + memctl->memc_or1 = CFG_OR1; + memctl->memc_br1 = CFG_BR1; + udelay(1000); + + /* perform SDRAM initialization sequence */ + memctl->memc_mamr = CFG_16M_MAMR; + udelay(100); + + /* Program the SDRAM's Mode Register */ + memctl->memc_mar = SDRAM_MODE_REG; + + /* Run the Prechard Pattern at 0x3C */ + memctl->memc_mcr = UPMA_RUN(1,0x3c); + udelay(1); + + /* Run the Refresh program residing at MAD index 0x30 */ + /* This contains the CBR Refresh command with a loop */ + /* The SDRAM must be refreshed at least 2 times */ + /* Please note a value of zero = 16 loops */ + memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30); + udelay(1); + + /* Run the Exception program residing at MAD index 0x3E */ + /* This contains the Write Mode Register command */ + /* The Write Mode Register command uses the value written to MAR */ + memctl->memc_mcr = UPMA_RUN(1,0x3e); + + udelay (1000); + + /* + * Check for 32M SDRAM Memory Size + */ + size = dram_size(CFG_32M_MAMR|MAMR_PTAE, + (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE); + udelay (1000); + + /* + * Check for 16M SDRAM Memory Size + */ + if (size != SDRAM_32M_MAX_SIZE) { + size = dram_size(CFG_16M_MAMR|MAMR_PTAE, + (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); + udelay (1000); + } + + udelay(10000); + return (size); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds new file mode 100644 index 0000000..cb3f456 --- /dev/null +++ b/board/snmc/qs850/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/snmc/qs860t/Makefile b/board/snmc/qs860t/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/snmc/qs860t/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/snmc/qs860t/config.mk b/board/snmc/qs860t/config.mk new file mode 100644 index 0000000..f6ab260 --- /dev/null +++ b/board/snmc/qs860t/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2002 +# Simple Network Magic Corporation, dnevil@snmc.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# QS860T +# Start address of 512K Socketed Flash +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c new file mode 100644 index 0000000..c84d08d --- /dev/null +++ b/board/snmc/qs860t/flash.c @@ -0,0 +1,1120 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +#ifdef CFG_FLASH_16BIT +#define FLASH_WORD_SIZE unsigned short +#define FLASH_ID_MASK 0xFFFF +#else +#define FLASH_WORD_SIZE unsigned long +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +/* stolen from esteem192e/flash.c */ +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); + +#ifndef CFG_FLASH_16BIT +static int write_word (flash_info_t *info, ulong dest, ulong data); +#else +static int write_short (flash_info_t *info, ulong dest, ushort data); +#endif +static void flash_get_offsets (ulong base, flash_info_t *info); + + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i=0; iflash_id & FLASH_TYPEMASK) == INTEL_ID_28F320J3A || + (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F640J3A || + (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F128J3A) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * info->size/info->sector_count); + } + } + else if (info->flash_id & FLASH_BTYPE) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CFG_FLASH_16BIT + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00008000; + info->start[3] = base + 0x0000C000; + info->start[4] = base + 0x00010000; + info->start[5] = base + 0x00014000; + info->start[6] = base + 0x00018000; + info->start[7] = base + 0x0001C000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x000E0000; + } + } else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } +#else + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000A000; + info->start[6] = base + 0x0000C000; + info->start[7] = base + 0x0000E000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00070000; + } + } else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } +#endif + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CFG_FLASH_16BIT + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00014000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x0001C000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } else { + + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +#else + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000A000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x0000E000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } else { + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } +#endif + } +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + uchar *boottype; + uchar botboot[]=", bottom boot sect)\n"; + uchar topboot[]=", top boot sector)\n"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + if (info->flash_id & 0x0001 ) { + boottype = botboot; + } else { + boottype = topboot; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype); + break; + case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype); + break; + case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype); + break; + case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype); + break; + case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype); + break; + case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype); + break; + case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype); + break; + case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit%s",boottype); + break; + +#if 0 /* enable when devices are available */ + + case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype); + break; + case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype); + break; +#endif + case INTEL_ID_28F320J3A: printf ("INTEL28F320JA3 (32 Mbit%s",boottype); + break; + case INTEL_ID_28F640J3A: printf ("INTEL28F640JA3 (64 Mbit%s",boottype); + break; + case INTEL_ID_28F128J3A: printf ("INTEL28F128JA3 (128 Mbit%s",boottype); + break; + + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) +{ + short i; + ulong base = (ulong)addr; + FLASH_WORD_SIZE value; + + /* Write auto select command: read Manufacturer ID */ + + +#ifndef CFG_FLASH_16BIT + + /* + * Note: if it is an AMD flash and the word at addr[0000] + * is 0x00890089 this routine will think it is an Intel + * flash device and may(most likely) cause trouble. + */ + + addr[0x0000] = 0x00900090; + if(addr[0x0000] != 0x00890089){ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; +#else + + /* + * Note: if it is an AMD flash and the word at addr[0000] + * is 0x0089 this routine will think it is an Intel + * flash device and may(most likely) cause trouble. + */ + + addr[0x0000] = 0x0090; + + if(addr[0x0000] != 0x0089){ + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0090; +#endif + } + value = addr[0]; + + switch (value) { + case (AMD_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_FUJ; + break; + case (STM_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_STM; + break; + case (SST_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_SST; + break; + case (INTEL_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + + } + + value = addr[1]; /* device ID */ + + switch (value) { + + case (AMD_ID_LV400T & FLASH_ID_MASK): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV400B & FLASH_ID_MASK): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800T & FLASH_ID_MASK): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV800B & FLASH_ID_MASK): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160T & FLASH_ID_MASK): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV160B & FLASH_ID_MASK): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & FLASH_ID_MASK): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (AMD_ID_LV320B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + + case (AMD_ID_DL322T & FLASH_ID_MASK): + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (INTEL_ID_28F800B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL800T; + info->sector_count = 23; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (INTEL_ID_28F800B3B & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (INTEL_ID_28F160B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL160T; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (INTEL_ID_28F160B3B & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (INTEL_ID_28F320B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL320T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (INTEL_ID_28F320B3B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + +#if 0 /* enable when devices are available */ + case (INTEL_ID_28F320B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL320T; + info->sector_count = 135; + info->size = 0x01000000; + break; /* => 16 MB */ + + case (INTEL_ID_28F320B3B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 135; + info->size = 0x01000000; + break; /* => 16 MB */ +#endif + case (INTEL_ID_28F320J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 32 MBit */ + case (INTEL_ID_28F640J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 64 MBit */ + case (INTEL_ID_28F128J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 128 MBit */ + + default: + /* FIXME*/ + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets(base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){ + *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { + *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ + } + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + + volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); + int flag, prot, sect, l_sect, barf; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + ((info->flash_id > FLASH_AMD_COMP) && + ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){ + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + if(info->flash_id < FLASH_AMD_COMP) { +#ifndef CFG_FLASH_16BIT + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; +#else + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0080; + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; +#endif + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); + addr[0] = (0x00300030 & FLASH_ID_MASK); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); + while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != + (0x00800080&FLASH_ID_MASK) ) + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + barf = 0; +#ifndef CFG_FLASH_16BIT + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00200020; + addr[0] = 0x00D000D0; + while(!(addr[0] & 0x00800080)); /* wait for error or finish */ + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; + } + } +#else + addr = (vu_short*)(info->start[sect]); + addr[0] = 0x0020; + addr[0] = 0x00D0; + while(!(addr[0] & 0x0080)); /* wait for error or finish */ + if( addr[0] & 0x003A) /* check for error */ + barf = addr[0] & 0x003A; +#endif + if(barf) { + printf("\nFlash error in sector at %lx\n",(unsigned long)addr); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if((barf & 0x0030) == 0x0030) + printf("Command Sequence error.\n"); + if((barf & 0x0030) == 0x0020) + printf("Block Erase error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + rcode = 1; + } else printf("."); + l_sect = sect; + } + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ + + } + + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ + +/*flash_info_t *addr2info (ulong addr) +{ + flash_info_t *info; + int i; + + for (i=0, info=&flash_info[0]; i= info->start[0]) && + (addr < (info->start[0] + info->size)) ) { + return (info); + } + } + + return (NULL); +} +*/ +/*----------------------------------------------------------------------- + * Copy memory to flash. + * Make sure all target addresses are within Flash bounds, + * and no protected sectors are hit. + * Returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - target range includes protected sectors + * 8 - target address not in Flash memory + */ + +/*int flash_write (uchar *src, ulong addr, ulong cnt) +{ + int i; + ulong end = addr + cnt - 1; + flash_info_t *info_first = addr2info (addr); + flash_info_t *info_last = addr2info (end ); + flash_info_t *info; + + if (cnt == 0) { + return (0); + } + + if (!info_first || !info_last) { + return (8); + } + + for (info = info_first; info <= info_last; ++info) { + ulong b_end = info->start[0] + info->size;*/ /* bank end addr */ +/* short s_end = info->sector_count - 1; + for (i=0; isector_count; ++i) { + ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; + + if ((end >= info->start[i]) && (addr < e_addr) && + (info->protect[i] != 0) ) { + return (4); + } + } + } + +*/ /* finally write data to flash */ +/* for (info = info_first; info <= info_last && cnt>0; ++info) { + ulong len; + + len = info->start[0] + info->size - addr; + if (len > cnt) + len = cnt; + if ((i = write_buff(info, src, addr, len)) != 0) { + return (i); + } + cnt -= len; + addr += len; + src += len; + } + return (0); +} +*/ +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ +#ifndef CFG_FLASH_16BIT + ulong cp, wp, data; + int l; +#else + ulong cp, wp; + ushort data; +#endif + int i, rc; + +#ifndef CFG_FLASH_16BIT + + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); + +#else + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start byte + */ + if (addr - wp) { + data = 0; + data = (data << 8) | *src++; + --cnt; + if ((rc = write_short(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ +/* l = 0; used for debuging */ + while (cnt >= 2) { + data = 0; + for (i=0; i<2; ++i) { + data = (data << 8) | *src++; + } + +/* if(!l){ + printf("%x",data); + l = 1; + } used for debuging */ + + if ((rc = write_short(info, wp, data)) != 0) { + return (rc); + } + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<2; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_short(info, wp, data)); + + +#endif +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifndef CFG_FLASH_16BIT +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start,barf; + int flag; + + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if(info->flash_id > FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + } else { + /* intel stuff */ + *addr = 0x00400040; + } + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + + if(info->flash_id > FLASH_AMD_COMP) { + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } else { + while(!(addr[0] & 0x00800080)) { /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; + } + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + } + + return (0); +} + +#else + +static int write_short (flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short*)(info->start[0]); + ulong start,barf; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_short *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x00A0; + } else { + /* intel stuff */ + *addr = 0x00D0; + *addr = 0x0040; + } + *((vu_short *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + } else { + /* intel stuff */ + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + + if( addr[0] & 0x003A) { /* check for error */ + barf = addr[0] & 0x003A; + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + *addr = 0x00B0; + *addr = 0x0070; + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + *addr = 0x00FF; + } + return (0); +} + + +#endif + +/*----------------------------------------------------------------------- + */ diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c new file mode 100644 index 0000000..a11d863 --- /dev/null +++ b/board/snmc/qs860t/qs860t.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2002 + * Simple Network Magic Corporation, dnevil@snmc.com + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "mpc8xx.h" + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, + 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, + 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, + 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04, + 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, + 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04, + 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04 +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Test ID string (QS860T...) + * + * Always return 1 + */ + +int checkboard (void) +{ + char *s, *e; + char buf[64]; + int i; + + i = getenv_r("serial#", buf, sizeof(buf)); + s = (i>0) ? buf : NULL; + + if (!s || strncmp(s, "QS860T", 6)) { + puts ("### No HW ID - assuming QS860T"); + } else { + for (e=s; *e; ++e) { + if (*e == ' ') + break; + } + + for ( ; sim_memctl; + long int size; + + upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + /* + * Prescaler for refresh + */ + memctl->memc_mptpr = 0x0400; + + /* + * Map controller bank 2 to the SDRAM address + */ + memctl->memc_or2 = CFG_OR2; + memctl->memc_br2 = CFG_BR2; + udelay(200); + + /* perform SDRAM initialization sequence */ + memctl->memc_mbmr = CFG_16M_MBMR; + udelay(100); + + memctl->memc_mar = 0x00000088; + memctl->memc_mcr = 0x80804105; /* run precharge pattern */ + udelay(1); + + /* Run two refresh cycles on SDRAM */ + memctl->memc_mbmr = 0x18802118; + memctl->memc_mcr = 0x80804130; + memctl->memc_mbmr = 0x18802114; + memctl->memc_mcr = 0x80804106; + + udelay (1000); + +#if 0 + /* + * Check for 64M SDRAM Memory Size + */ + size = dram_size (CFG_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE); + udelay (1000); + + /* + * Check for 16M SDRAM Memory Size + */ + if (size != SDRAM_64M_MAX_SIZE) { +#endif + size = dram_size (CFG_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); + udelay (1000); +#if 0 + } + + memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; +#endif + + + udelay(10000); + + +#if 0 + + /* + * Also, map other memory to correct position + */ + + /* + * Map the 8M Intel Flash device to chip select 1 + */ + memctl->memc_or1 = CFG_OR1; + memctl->memc_br1 = CFG_BR1; + + + /* + * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg + * to chip select 3 + */ + memctl->memc_or3 = CFG_OR3; + memctl->memc_br3 = CFG_BR3; + + /* + * Map chip selects 4, 5, 6, & 7 for external expansion connector + */ + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; + + memctl->memc_or5 = CFG_OR5; + memctl->memc_br5 = CFG_BR5; + + memctl->memc_or6 = CFG_OR6; + memctl->memc_br6 = CFG_BR6; + + memctl->memc_or7 = CFG_OR7; + memctl->memc_br7 = CFG_BR7; + +#endif + + return (size); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mbmr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mbmr = mbmr_value; + + return (get_ram_size(base, maxsize)); +} diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds new file mode 100644 index 0000000..cb3f456 --- /dev/null +++ b/board/snmc/qs860t/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sorcery/Makefile b/board/sorcery/Makefile new file mode 100644 index 0000000..3d6d673 --- /dev/null +++ b/board/sorcery/Makefile @@ -0,0 +1,45 @@ +# (C) Copyright 2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sorcery/config.mk b/board/sorcery/config.mk new file mode 100644 index 0000000..25de0b5 --- /dev/null +++ b/board/sorcery/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# sorcery board +# + +TEXT_BASE = 0xfff00000 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c new file mode 100644 index 0000000..35d6a06 --- /dev/null +++ b/board/sorcery/sorcery.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2004, Freescale Inc. + * TsiChung Liew, Tsi-Chung.Liew@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +long int initdram (int board_type) +{ + ulong size; + + size = dramSetup (); + + return get_ram_size((ulong *)CFG_SDRAM_BASE, size); +} + +int checkboard (void) +{ + puts ("Board: Sorcery-C MPC8220\n"); + + return 0; +} + +#if defined(CONFIG_PCI) +/* + * Initialize PCI devices, report devices found. + */ +static struct pci_controller hose; + +#endif /* CONFIG_PCI */ + +void pci_init_board (void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc8220_init (struct pci_controller *hose); + pci_mpc8220_init (&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/sorcery/u-boot.lds b/board/sorcery/u-boot.lds new file mode 100644 index 0000000..889bc77 --- /dev/null +++ b/board/sorcery/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8220/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/spd8xx/Makefile b/board/spd8xx/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/spd8xx/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/spd8xx/config.mk b/board/spd8xx/config.mk new file mode 100644 index 0000000..e1e0192 --- /dev/null +++ b/board/spd8xx/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# SPD823TS boards +# + +TEXT_BASE = 0xFF000000 diff --git a/board/spd8xx/flash.c b/board/spd8xx/flash.c new file mode 100644 index 0000000..8c0bb4f --- /dev/null +++ b/board/spd8xx/flash.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + /* All Speech Design board memory (DRAM and EPROM) initialisation is + done in dram_init(). + The caller of ths function here expects the total size and will hang, + if we give here back 0. So we return the EPROM size. */ + + return (1024 * 1024); /* 1 MB */ +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + printf("no FLASH memory in MPC823TS board\n"); + return; +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + return 1; +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c new file mode 100644 index 0000000..c79b9b0 --- /dev/null +++ b/board/spd8xx/spd8xx.c @@ -0,0 +1,294 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sharc_table[] = { + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04, + 0xFFFFEC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04, + 0xFFFFEC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPM RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPM RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPM RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPM RAM) + */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPM RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPM RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPM RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + */ + +int checkboard (void) +{ + puts ("Board: SPD823TS\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0; + +#if 0 + /* + * Map controller bank 2 to the SRAM bank at preliminary address. + */ + memctl->memc_or2 = CFG_OR2; + memctl->memc_br2 = CFG_BR2; +#endif + + /* + * Map controller bank 4 to the PER8 bank. + */ + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; + +#if 0 + /* Configure SHARC at UMA */ + upmconfig (UPMA, (uint *) sharc_table, + sizeof (sharc_table) / sizeof (uint)); + /* Map controller bank 5 to the SHARC */ + memctl->memc_or5 = CFG_OR5; + memctl->memc_br5 = CFG_BR5; +#endif + + memctl->memc_mamr = 0x00001000; + + /* Configure SDRAM at UMB */ + upmconfig (UPMB, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + + memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ + + udelay (200); + memctl->memc_mcr = 0x80806105; + udelay (1); + memctl->memc_mcr = 0x80806130; + udelay (1); + memctl->memc_mcr = 0x80806130; + udelay (1); + memctl->memc_mcr = 0x80806106; + + memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ + + /* + * Check Bank 0 Memory Size for re-configuration + */ + size_b0 = + dram_size (CFG_MBMR_8COL, SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); + + memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mbmr = mamr_value; + + return (get_ram_size (base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +void reset_phy (void) +{ + immap_t *immr = (immap_t *) CFG_IMMR; + ushort sreg; + + /* Configure extra port pins for NS DP83843 PHY */ + immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO); + + sreg = immr->im_ioport.iop_padir; + sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */ + sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */ + immr->im_ioport.iop_padir = sreg; + + immr->im_ioport.iop_padat &= ~(PA_ENET_MDC); /* set MDC = 0 */ + + /* + * RESET in implemented by a positive pulse of at least 1 us + * at the reset pin. + * + * Configure RESET pins for NS DP83843 PHY, and RESET chip. + * + * Note: The RESET pin is high active, but there is an + * inverter on the SPD823TS board... + */ + immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET); + immr->im_ioport.iop_pcdir |= PC_ENET_RESET; + /* assert RESET signal of PHY */ + immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET); + udelay (10); + /* de-assert RESET signal of PHY */ + immr->im_ioport.iop_pcdat |= PC_ENET_RESET; + udelay (10); +} + +/* ------------------------------------------------------------------------- */ + +void ide_set_reset (int on) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* + * Configure PC for IDE Reset Pin + */ + if (on) { /* assert RESET */ + immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); + } else { /* release RESET */ + immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; + } + + /* program port pin as GPIO output */ + immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds new file mode 100644 index 0000000..f9150ab --- /dev/null +++ b/board/spd8xx/u-boot.lds @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + common/environment.o(.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug new file mode 100644 index 0000000..650572d --- /dev/null +++ b/board/spd8xx/u-boot.lds.debug @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ssv/adnpesc1/Makefile b/board/ssv/adnpesc1/Makefile new file mode 100644 index 0000000..9182a4e --- /dev/null +++ b/board/ssv/adnpesc1/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o misc.o + +SOBJS = vectors.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ssv/adnpesc1/adnpesc1.c b/board/ssv/adnpesc1/adnpesc1.c new file mode 100644 index 0000000..2f704a0 --- /dev/null +++ b/board/ssv/adnpesc1/adnpesc1.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_HW_WATCHDOG) +extern void ssv_wd_pio_init(void); /* comes from ../common/wd_pio.c + included by ./misc.c */ +#endif + +void _default_hdlr (void) +{ + printf ("default_hdlr\n"); +} + +int board_early_init_f (void) +{ +#if defined(CONFIG_HW_WATCHDOG) + ssv_wd_pio_init(); +#endif + return 0; +} + +int checkboard (void) +{ + puts ( "Board: SSV DilNetPC ADNP/ESC1" +#if defined(CONFIG_DNPEVA2) + " on DNP/EVA2" +#endif + "\n"); +#if defined(CONFIG_NIOS_BASE_32) + puts ("Conf.: SSV Base 32 (nios_32)\n"); +#endif + + return 0; +} + +long int initdram (int board_type) +{ + return (0); +} + +/* + * The following are used to control the SPI chip selects for the SPI command. + */ +#if (CONFIG_COMMANDS & CFG_CMD_SPI) && CONFIG_NIOS_SPI + +#define SPI_RTC_CS_MASK 0x00000001 + +void spi_rtc_chipsel(int cs) +{ + nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; + + if (cs) + spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */ + else + spi->slaveselect = 0; /* deactivate (0) */ +} + +/* + * The SPI command uses this table of functions for controlling the SPI + * chip selects: it calls the appropriate function to control the SPI + * chip selects. + */ +spi_chipsel_type spi_chipsel[] = { + spi_rtc_chipsel +}; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +#endif /* CFG_CMD_SPI */ + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ diff --git a/board/ssv/adnpesc1/config.mk b/board/ssv/adnpesc1/config.mk new file mode 100644 index 0000000..7d8eb03 --- /dev/null +++ b/board/ssv/adnpesc1/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2004 +# Li-Pro.Net +# Stephan Linz +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x02fc0000 # ATTENTION: notice your CFG_MONITOR_LEN setting + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/ssv/adnpesc1/flash.c b/board/ssv/adnpesc1/flash.c new file mode 100644 index 0000000..fd8379b --- /dev/null +++ b/board/ssv/adnpesc1/flash.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +/* + * include common flash code (for ssv boards) + */ +#include "../common/flash.c" + +/*---------------------------------------------------------------------*/ +#define BANKSZ (8 * 1024 * 1024) +#define SECTSZ (64 * 1024) +#define UBOOTSECS ((CFG_MONITOR_LEN + CFG_ENV_SIZE) / SECTSZ) +#define UBOOTAREA (UBOOTSECS * 64 * 1024) /* monitor / env area */ + +/*---------------------------------------------------------------------*/ +unsigned long flash_init (void) +{ + int i; + unsigned long addr; + flash_info_t *fli = &flash_info[0]; + + fli->size = BANKSZ; + fli->sector_count = CFG_MAX_FLASH_SECT; + fli->flash_id = FLASH_MAN_AMD + FLASH_AMLV640U; + + addr = CFG_FLASH_BASE; + for (i = 0; i < fli->sector_count; ++i) { + fli->start[i] = addr; + addr += SECTSZ; + + /* Protect monitor / environment area */ + if (addr <= (CFG_FLASH_BASE + UBOOTAREA)) + fli->protect[i] = 1; + else + fli->protect[i] = 0; + } + + return (BANKSZ); +} diff --git a/board/ssv/adnpesc1/misc.c b/board/ssv/adnpesc1/misc.c new file mode 100644 index 0000000..1c5fcb9 --- /dev/null +++ b/board/ssv/adnpesc1/misc.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * board/ssv/adnpesc1/misc.c + * + * miscellaneous board interfaces / drivers + */ + +#include + +#if defined(CONFIG_STATUS_LED) +#include "../common/cmd_sled.c" +#endif + +#if defined(CONFIG_HW_WATCHDOG) +#include "../common/wd_pio.c" +#endif + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) +#include "../common/post.c" +#endif diff --git a/board/ssv/adnpesc1/u-boot.lds b/board/ssv/adnpesc1/u-boot.lds new file mode 100644 index 0000000..8b01f45 --- /dev/null +++ b/board/ssv/adnpesc1/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-nios") +OUTPUT_ARCH(nios) +ENTRY(_start) + +SECTIONS +{ + .text : + { + cpu/nios/start.o (.text) + *(.text) + } + __text_end = .; + + . = ALIGN(4); + .rodata : + { + *(.rodata) + } + __rodata_end = .; + + . = ALIGN(4); + .data : + { + *(.data) + } + . = ALIGN(4); + __data_end = .; + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + __bss_start = .; + . = ALIGN(4); + .bss : + { + *(.bss) + } + . = ALIGN(4); + __bss_end = .; +} diff --git a/board/ssv/adnpesc1/vectors.S b/board/ssv/adnpesc1/vectors.S new file mode 100644 index 0000000..fb7e17e --- /dev/null +++ b/board/ssv/adnpesc1/vectors.S @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + +/************************************************************************* + * Exception Vector Table + * + * This could have gone in the cpu soure tree, but the whole point of + * Nios is customization -- and polluting the cpu source tree with + * board-specific ifdef's really defeats the purpose, no? With this in + * the board-specific tree, each board has the freedom to organize + * vectors/traps, etc anyway it wants. The init code copies this table + * to the proper location. + * + * Each board can do what it likes here. But there are four "standard" + * handlers availble: + * + * _cwp_lolimit -Handles register window underflows. + * _cwp_hilimit -Handles register window overflows. + * _timebase_int -Increments the timebase. + * _def_xhandler -Default exception handler. + * + * _timebase_int handles a Nios Timer interrupt and increments the + * timestamp used for the get_timer(), reset_timer(), etc. routines. It + * expects the timer to be configured like the standard-32 low priority + * timer. + * + * _def_xhandler dispatches exceptions/traps via the external_interrupt() + * routine. This lets you use the irq_install_handler() and handle your + * interrupts/traps with code written in C. + ************************************************************************/ + + .data + .global _vectors + .align 4 +_vectors: + +#if defined(CFG_NIOS_CPU_OCI_BASE) + /* OCI does the reset job */ + .long _def_xhandler@h /* Vector 0 - NMI / Reset */ +#else + /* there is no OCI, so we have to do a direct reset jump here */ + .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ +#endif + .long _cwp_lolimit@h /* Vector 1 - underflow */ + .long _cwp_hilimit@h /* Vector 2 - overflow */ + + .long _def_xhandler@h /* Vector 3 - GNUPro debug */ + .long _def_xhandler@h /* Vector 4 - GNUPro debug */ + .long _def_xhandler@h /* Vector 5 - GNUPro debug */ + .long _def_xhandler@h /* Vector 6 - future reserved */ + .long _def_xhandler@h /* Vector 7 - future reserved */ + .long _def_xhandler@h /* Vector 8 - future reserved */ + .long _def_xhandler@h /* Vector 9 - future reserved */ + .long _def_xhandler@h /* Vector 10 - future reserved */ + .long _def_xhandler@h /* Vector 11 - future reserved */ + .long _def_xhandler@h /* Vector 12 - future reserved */ + .long _def_xhandler@h /* Vector 13 - future reserved */ + .long _def_xhandler@h /* Vector 14 - future reserved */ + .long _def_xhandler@h /* Vector 15 - future reserved */ +#if (CFG_NIOS_TMRIRQ == 16) + .long _timebase_int@h /* Vector 16 - lopri timer*/ +#else + .long _def_xhandler@h /* Vector 16 */ +#endif + .long _def_xhandler@h /* Vector 17 */ + .long _def_xhandler@h /* Vector 18 */ + .long _def_xhandler@h /* Vector 19 */ + .long _def_xhandler@h /* Vector 20 */ + .long _def_xhandler@h /* Vector 21 */ + .long _def_xhandler@h /* Vector 22 */ + .long _def_xhandler@h /* Vector 23 */ + .long _def_xhandler@h /* Vector 24 */ + .long _def_xhandler@h /* Vector 25 */ + .long _def_xhandler@h /* Vector 26 */ + .long _def_xhandler@h /* Vector 27 */ + .long _def_xhandler@h /* Vector 28 */ + .long _def_xhandler@h /* Vector 29 */ + .long _def_xhandler@h /* Vector 30 */ + .long _def_xhandler@h /* Vector 31 */ + .long _def_xhandler@h /* Vector 32 */ + .long _def_xhandler@h /* Vector 33 */ + .long _def_xhandler@h /* Vector 34 */ + .long _def_xhandler@h /* Vector 35 */ + .long _def_xhandler@h /* Vector 36 */ + .long _def_xhandler@h /* Vector 37 */ + .long _def_xhandler@h /* Vector 38 */ + .long _def_xhandler@h /* Vector 39 */ + .long _def_xhandler@h /* Vector 40 */ + .long _def_xhandler@h /* Vector 41 */ + .long _def_xhandler@h /* Vector 42 */ + .long _def_xhandler@h /* Vector 43 */ + .long _def_xhandler@h /* Vector 44 */ + .long _def_xhandler@h /* Vector 45 */ + .long _def_xhandler@h /* Vector 46 */ + .long _def_xhandler@h /* Vector 47 */ + .long _def_xhandler@h /* Vector 48 */ + .long _def_xhandler@h /* Vector 49 */ +#if (CFG_NIOS_TMRIRQ == 50) + .long _timebase_int@h /* Vector 50 - lopri timer*/ +#else + .long _def_xhandler@h /* Vector 50 */ +#endif + .long _def_xhandler@h /* Vector 51 */ + .long _def_xhandler@h /* Vector 52 */ + .long _def_xhandler@h /* Vector 53 */ + .long _def_xhandler@h /* Vector 54 */ + .long _def_xhandler@h /* Vector 55 */ + .long _def_xhandler@h /* Vector 56 */ + .long _def_xhandler@h /* Vector 57 */ + .long _def_xhandler@h /* Vector 58 */ + .long _def_xhandler@h /* Vector 59 */ + .long _def_xhandler@h /* Vector 60 */ + .long _def_xhandler@h /* Vector 61 */ + .long _def_xhandler@h /* Vector 62 */ + .long _def_xhandler@h /* Vector 63 */ diff --git a/board/ssv/common/cmd_sled.c b/board/ssv/common/cmd_sled.c new file mode 100644 index 0000000..d61fa3e --- /dev/null +++ b/board/ssv/common/cmd_sled.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_STATUS_LED) + +/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * !!!!! Q u i c k & D i r t y H a c k !!!!! + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * !!!!! !!!!! + * !!!!! Next type definition was coming from original !!!!! + * !!!!! status LED driver drivers/status_led.c and !!!!! + * !!!!! should exported for using here. !!!!! + * !!!!! !!!!! + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ + +typedef struct { + led_id_t mask; + int state; + int period; + int cnt; +} led_dev_t; + +extern led_dev_t led_dev[]; + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int led_id = 0; + + if (argc > 1) { +#ifdef STATUS_LED_BOOT + if (!strcmp (argv[1], "boot")) { + led_id = STATUS_LED_BOOT + 1; + } +#endif +#ifdef STATUS_LED_RED + if (!strcmp (argv[1], "red")) { + led_id = STATUS_LED_RED + 1; + } +#endif +#ifdef STATUS_LED_YELLOW + if (!strcmp (argv[1], "yellow")) { + led_id = STATUS_LED_YELLOW + 1; + } +#endif +#ifdef STATUS_LED_GREEN + if (!strcmp (argv[1], "green")) { + led_id = STATUS_LED_GREEN + 1; + } +#endif + } + + switch (argc) { + case 1: +#if (STATUS_LED_BITS > 3) + for (; led_id < 4; led_id++) +#elif (STATUS_LED_BITS > 2) + for (; led_id < 3; led_id++) +#elif (STATUS_LED_BITS > 1) + for (; led_id < 2; led_id++) +#elif (STATUS_LED_BITS > 0) + for (; led_id < 1; led_id++) +#else +#error "*** STATUS_LED_BITS not correct defined ***" +#endif + { + printf ("Status LED '%s' is %s\n", + led_id == STATUS_LED_BOOT ? "boot" + : led_id == STATUS_LED_RED ? "red" + : led_id == STATUS_LED_YELLOW ? "yellow" + : led_id == + STATUS_LED_GREEN ? "green" : "unknown", + led_dev[led_id].state == + STATUS_LED_ON ? "on" : led_dev[led_id]. + state == + STATUS_LED_OFF ? "off" : led_dev[led_id]. + state == + STATUS_LED_BLINKING ? "blinking" : "unknown"); + } + return 0; + case 2: + if (led_id) { + printf ("Status LED '%s' is %s\n", argv[1], + led_dev[led_id - 1].state == + STATUS_LED_ON ? "on" : led_dev[led_id - + 1].state == + STATUS_LED_OFF ? "off" : led_dev[led_id - + 1].state == + STATUS_LED_BLINKING ? "blinking" : "unknown"); + return 0; + } else + break; + case 3: + if (led_id) { + if (!strcmp (argv[2], "on")) { + status_led_set (led_id - 1, STATUS_LED_ON); + return 0; + } else if (!strcmp (argv[2], "off")) { + status_led_set (led_id - 1, STATUS_LED_OFF); + return 0; + } else if (!strcmp (argv[2], "blink")) { + status_led_set (led_id - 1, + STATUS_LED_BLINKING); + return 0; + } else + break; + } else + break; + default: + break; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +#ifdef STATUS_LED_BOOT +#ifdef STATUS_LED_RED +#ifdef STATUS_LED_YELLOW +#ifdef STATUS_LED_GREEN +#define __NAME_STR " - name: boot|red|yellow|green\n" +#else +#define __NAME_STR " - name: boot|red|yellow\n" +#endif +#else +#define __NAME_STR " - name: boot|red\n" +#endif +#else +#define __NAME_STR " - name: boot\n" +#endif +#else +#define __NAME_STR " - name: (no such defined)\n" +#endif + +U_BOOT_CMD (sled, 3, 0, do_sled, + "sled - check and set status led\n", + "sled [name [state]]\n" __NAME_STR " - state: on|off|blink\n"); +#endif /* CFG_CMD_BSP */ +#endif /* CONFIG_STATUS_LED */ diff --git a/board/ssv/common/flash.c b/board/ssv/common/flash.c new file mode 100644 index 0000000..70cab7f --- /dev/null +++ b/board/ssv/common/flash.c @@ -0,0 +1,207 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/*--------------------------------------------------------------------*/ +void flash_print_info (flash_info_t * info) +{ + int i, k; + unsigned long size; + int erased; + volatile unsigned char *flash; + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + + /* Check if whole sector is erased */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned char *) info->start[i]; + for (k = 0; k < size; k++) { + if (*flash++ != 0xff) { + erased = 0; + break; + } + } + + /* Print the info */ + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", info->start[i], erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf ("\n"); +} + +/*-------------------------------------------------------------------*/ + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int prot, sect, wait; + unsigned oldpri; + ulong start; + + /* Some sanity checking */ + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + +#ifdef DEBUG + for (sect = s_first; sect <= s_last; sect++) { + printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]); + } +#endif + + /* NOTE: disabling interrupts on Nios can be very bad since it + * also disables the LO_LIMIT exception. It's better here to + * set the interrupt priority to 3 & restore it when we're done. + */ + oldpri = ipri (3); + + /* It's ok to erase multiple sectors provided we don't delay more + * than 50 usec between cmds ... at which point the erase time-out + * occurs. So don't go and put printf() calls in the loop ... it + * won't be very helpful ;-) + */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + *addr = 0xf0; + *(addr+0xAAA/2) = 0xaa; + *(addr+0x554/2) = 0x55; + *(addr+0xAAA/2) = 0x80; + *(addr+0xAAA/2) = 0xaa; + *(addr+0x554/2) = 0x55; + *addr2 = 0x30; + /* Now just wait for 0xffff & provide some user + * feedback while we wait. Here we have to grant + * timer interrupts. Otherwise get_timer() can't + * work right. */ + ipri(oldpri); + start = get_timer (0); + while (*addr2 != 0xffff) { + for (wait = 8; wait; wait--) { + udelay (125 * 1000); + } + putc ('.'); + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + printf ("timeout\n"); + return 1; + } + } + oldpri = ipri (3); /* disallow non important irqs again */ + } + } + + printf ("\n"); + *addr = 0xf0; + + /* Restore interrupt priority */ + ipri (oldpri); + + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * srcbuffer, ulong addr, ulong cnt) +{ + + volatile CFG_FLASH_WORD_SIZE *cmd = (vu_short *) info->start[0]; + volatile CFG_FLASH_WORD_SIZE *dst = (vu_short *) addr; + CFG_FLASH_WORD_SIZE *src = (void *) srcbuffer; + CFG_FLASH_WORD_SIZE b; + unsigned oldpri; + ulong start; + + cnt /= sizeof(CFG_FLASH_WORD_SIZE); + while (cnt) { + /* Check for sufficient erase */ + b = *src; + if ((*dst & b) != b) { + printf ("%02x : %02x\n", *dst, b); + return (2); + } + + /* Disable interrupts other than window underflow + * (interrupt priority 2) + */ + oldpri = ipri (3); + *(cmd+0xAAA/2) = 0xaa; + *(cmd+0x554/2) = 0x55; + *(cmd+0xAAA/2) = 0xa0; + ipri (oldpri); + *dst = b; + + /* Verify write */ + start = get_timer (0); + while (*dst != b) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *cmd = 0xf0; + return 1; + } + } + dst++; + src++; + cnt--; + } + + *cmd = 0xf0; + return (0); +} diff --git a/board/ssv/common/post.c b/board/ssv/common/post.c new file mode 100644 index 0000000..a5f29c1 --- /dev/null +++ b/board/ssv/common/post.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + +#if !defined(CFG_NIOS_POST_WORD_ADDR) +#error "*** CFG_NIOS_POST_WORD_ADDR not defined ***" +#endif + +void post_word_store (ulong a) +{ + volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR); + *(volatile ulong *) save_addr = a; +} + +ulong post_word_load (void) +{ + volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR); + return *(volatile ulong *) save_addr; +} + +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ diff --git a/board/ssv/common/wd_pio.c b/board/ssv/common/wd_pio.c new file mode 100644 index 0000000..3215ac9 --- /dev/null +++ b/board/ssv/common/wd_pio.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if defined(CONFIG_HW_WATCHDOG) + +#if !defined(CONFIG_HW_WDENA_BASE) +#error "*** CONFIG_HW_WDENA_BASE not defined ***" +#if !defined(CONFIG_HW_WDENA_BIT) +#error "*** CONFIG_HW_WDENA_BIT not defined ***" +#endif +#endif + +#if !defined(CONFIG_HW_WDTOG_BASE) +#error "*** CONFIG_HW_WDTOG_BASE not defined ***" +#if !defined(CONFIG_HW_WDTOG_BIT) +#error "*** CONFIG_HW_WDTOG_BIT not defined ***" +#endif +#endif + +#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */ +static unsigned __wd_ena_pio_portval = 0; +#endif + +#define WD_PIO_INIT_DONE(V) ((V) & (1 << CONFIG_HW_WDENA_BIT)) + +void ssv_wd_pio_init(void) +{ + nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE; + nios_pio_t *trg_piop = (nios_pio_t*)CONFIG_HW_WDTOG_BASE; + + trg_piop->data &= ~(1 << CONFIG_HW_WDTOG_BIT); + +#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */ + + __wd_ena_pio_portval |= (1 << CONFIG_HW_WDENA_BIT); + ena_piop->data = __wd_ena_pio_portval; + +#else /* !CONFIG_HW_WDPORT_WRONLY */ + + trg_piop->direction |= (1 << CONFIG_HW_WDTOG_BIT); + + ena_piop->data |= (1 << CONFIG_HW_WDENA_BIT); + ena_piop->direction |= (1 << CONFIG_HW_WDENA_BIT); + +#endif /* CONFIG_HW_WDPORT_WRONLY */ +} + +void ssv_wd_pio_done(void) +{ + nios_pio_t *piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE; + +#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */ + + __wd_ena_pio_portval &= ~(1 << CONFIG_HW_WDENA_BIT); + piop->data = __wd_ena_pio_portval; + +#else /* !CONFIG_HW_WDPORT_WRONLY */ + + piop->data &= ~(1 << CONFIG_HW_WDENA_BIT); + +#endif /* CONFIG_HW_WDPORT_WRONLY */ +} + +void ssv_wd_pio_reset(void) +{ + nios_pio_t *trg_piop = (nios_pio_t*)CONFIG_HW_WDTOG_BASE; + +#ifdef CONFIG_HW_WDPORT_WRONLY + if (WD_PIO_INIT_DONE(__wd_ena_pio_portval)) +#else + nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE; + + if (WD_PIO_INIT_DONE(ena_piop->data)) +#endif + { + trg_piop->data |= (1 << CONFIG_HW_WDTOG_BIT); + trg_piop->data &= ~(1 << CONFIG_HW_WDTOG_BIT); + } +} + +void hw_watchdog_reset(void) +{ + int re_enable = disable_interrupts (); + + ssv_wd_pio_reset(); + if (re_enable) + enable_interrupts (); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE; + + switch (argc) + { + case 1: + printf ("Watchdog timer status is %s\n", +#ifdef CONFIG_HW_WDPORT_WRONLY + WD_PIO_INIT_DONE(__wd_ena_pio_portval) +#else + WD_PIO_INIT_DONE(ena_piop->data) +#endif + ? "on" : "off"); + return 0; + case 2: + if (!strcmp(argv[1],"on")) + { + ssv_wd_pio_init(); + printf("Watchdog timer now is on\n"); + return 0; + } + else if (!strcmp(argv[1],"off")) + { + ssv_wd_pio_done(); + printf("Watchdog timer now is off\n"); + return 0; + } + break; + default: + break; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + wd, 2, 1, do_wd, + "wd - check and set watchdog\n", + "on - switch watchDog on\n" + "wd off - switch watchdog off\n" + "wd - print current status\n" +); +#endif /* CFG_CMD_BSP */ +#endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile new file mode 100644 index 0000000..d150df8 --- /dev/null +++ b/board/stxgp3/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/stxgp3/config.mk b/board/stxgp3/config.mk new file mode 100644 index 0000000..2427818 --- /dev/null +++ b/board/stxgp3/config.mk @@ -0,0 +1,32 @@ +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,2003 Motorola Inc. +# +# Copied from ADS85xx for STx GP3 - Dan Malek +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/stxgp3/flash.c b/board/stxgp3/flash.c new file mode 100644 index 0000000..032989b --- /dev/null +++ b/board/stxgp3/flash.c @@ -0,0 +1,515 @@ +/* + * (C) Copyright 2003, Dan Malek, Embedded Edge, LLC. + * Copied from ADS85xx. + * Updated to support the Silicon Tx GP3 8560. We should only find + * two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash), + * but I left other code here in case people order custom boards. + * + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao,(X.Xiao@motorola.com) + * + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Add support the Sharp chips on the mpc8260ads. + * I started with board/ip860/flash.c and made changes I found in + * the MTD project by David Schleef. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if !defined(CFG_NO_FLASH) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#undef DEBUG + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static int clear_block_lock_bit(vu_long * addr); +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: enable write, + * or we cannot even write flash commands + */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_SHARP: printf ("Sharp "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F640C3T: printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + ulong sector_offset; + +#ifdef DEBUG + printf("Check flash at 0x%08x\n",(uint)addr); +#endif + /* Write "Intelligent Identifier" command: read Manufacturer ID */ + *addr = 0x90909090; + udelay(20); + asm("sync"); + + value = addr[0] & 0x00FF00FF; + +#ifdef DEBUG + printf("manufacturer=0x%x\n",(uint)value); +#endif + switch (value) { + case MT_MANUFACT: /* SHARP, MT or => Intel */ + case INTEL_ALT_MANU: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + printf("unknown manufacturer: %x\n", (unsigned int)value); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + +#ifdef DEBUG + printf("deviceID=0x%x\n",(uint)value); +#endif + switch (value) { + + case (INTEL_ID_28F640C3T): + info->flash_id += FLASH_28F640C3T; + info->sector_count = 135; + info->size = 0x01000000; + sector_offset = 0x20000; + break; /* => 2x8 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table + * The first 127 blocks are large, the last 8 are small. + */ + for (i = 0; i < 127; i++) { + info->start[i] = base; + base += sector_offset; + /* Sectors are locked upon reset */ + info->protect[i] = 0; + } + for (i = 127; i < 135; i++) { + info->start[i] = base; + base += 0x4000; + /* Sectors are locked upon reset */ + info->protect[i] = 0; + } + + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_long *)info->start[0]; + *addr = 0xFFFFFF; /* reset bank to read array mode */ + asm("sync"); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) + && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + +#ifdef DEBUG + printf("\nFlash Erase:\n"); +#endif + /* Make Sure Block Lock Bit is not set. */ + if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ + return 1; + } + + /* Start erase on unprotected sectors */ +#if defined(DEBUG) + printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); +#endif + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + asm("sync"); + + last = start = get_timer (0); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + /* Single Block Erase Command */ + *addr = 0x20202020; + asm("sync"); + /* Confirm */ + *addr = 0xD0D0D0D0; + asm("sync"); + + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr = 0xD0D0D0D0; + asm("sync"); + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + while ((*addr & 0x00800080) != 0x00800080) { + if(*addr & 0x00200020){ + printf("Error in Block Erase - Lock Bit may be set!\n"); + printf("Status Register = 0x%X\n", (uint)*addr); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + /* reset to read mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + } + } + + printf ("flash erase done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong start, csr; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = 0x10101010; + asm("sync"); + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + flag = 0; + + while (((csr = *addr) & 0x00800080) != 0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x40404040) { + printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + + /* Clear Status Registers Command */ + *addr = 0x50505050; + asm("sync"); + /* Reset to read array mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + + return (flag); +} + +/*----------------------------------------------------------------------- + * Clear Block Lock Bit, returns: + * 0 - OK + * 1 - Timeout + */ + +static int clear_block_lock_bit(vu_long * addr) +{ + ulong start, now; + + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + + *addr = 0x60606060; + asm("sync"); + *addr = 0xd0d0d0d0; + asm("sync"); + + start = get_timer (0); + while((*addr & 0x00800080) != 0x00800080){ + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout on clearing Block Lock Bit\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + } + return 0; +} + +#endif /* !CFG_NO_FLASH */ diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S new file mode 100644 index 0000000..d504289 --- /dev/null +++ b/board/stxgp3/init.S @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2004 Embedded Edge, LLC + * Dan Malek + * Copied from ADS85xx. + * Updates for Silicon Tx GP3 8560. We only support 32-bit flash + * and DDR with SPD EEPROM configuration. + * + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \ + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \ + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \ + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \ + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \ + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \ + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \ + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \ + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \ + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \ + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \ + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \ + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xfc000000 16K Configuration Latch register + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + .long TLB1_MAS0(1, 8, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1, 9, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xfc00_0000 0xfc00_ffff Config Latch 64K + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c new file mode 100644 index 0000000..2b3949c --- /dev/null +++ b/board/stxgp3/stxgp3.c @@ -0,0 +1,382 @@ +/* + * (C) Copyright 2003, Embedded Edge, LLC + * Dan Malek, + * Copied from ADS85xx. + * Updates for Silicon Tx GP3 8560 + * + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +extern long int spd_sdram (void); + +#include +#include +#include +#include +#include +#include +#include +#include + +long int fixed_sdram (void); + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +static uint64_t next_led_update; +static uint led_bit; + +int +board_early_init_f(void) +{ +#if defined(CONFIG_PCI) + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; + + pci->peer &= 0xfffffffdf; /* disable master abort */ +#endif + return 0; +} + +void +reset_phy(void) +{ + volatile uint *blatch; + + blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE; + + /* reset Giga bit Ethernet port if needed here */ + + *blatch &= ~0x000000c0; + udelay(100); + *blatch = 0x000000c1; /* Light one led, too */ + udelay(1000); + +#if 0 /* This is the port we really want to use for debugging. */ + /* reset the CPM FEC port */ +#if (CONFIG_ETHER_INDEX == 2) + bcsr->bcsr2 &= ~FETH2_RST; + udelay(2); + bcsr->bcsr2 |= FETH2_RST; + udelay(1000); +#elif (CONFIG_ETHER_INDEX == 3) + bcsr->bcsr3 &= ~FETH3_RST; + udelay(2); + bcsr->bcsr3 |= FETH3_RST; + udelay(1000); +#endif +#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) + /* reset PHY */ + miiphy_reset("FCC1 ETHERNET", 0x0); + + /* change PHY address to 0x02 */ + bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + + bb_miiphy_write(NULL, 0x02, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#endif /* CONFIG_MII */ +#endif +} + +int +checkboard(void) +{ + printf ("Board: Silicon Tx GPPP 8560 Board\n"); + return (0); +} + +/* Blinkin' LEDS for Robert. +*/ +void +show_activity(int flag) +{ + volatile uint *blatch; + + if (next_led_update > get_ticks()) + return; + + blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE; + + led_bit >>= 1; + if (led_bit == 0) + led_bit = 0x08; + *blatch = (0xc0 | led_bit); + eieio(); + next_led_update += (get_tbclk() / 4); +} + +long int +initdram (int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + uint temp_ddrdll = 0; + + /* Work around to stabilize DDR DLL */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); + } +#endif + + dram_size = spd_sdram (); + +#if defined(CONFIG_DDR_ECC) + /* Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + return dram_size; +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) + +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_stxgp3_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_stxgp3_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds new file mode 100644 index 0000000..3bc6150 --- /dev/null +++ b/board/stxgp3/u-boot.lds @@ -0,0 +1,159 @@ +/* + * (C) Copyright 2003 Embedded Edge, LLC + * Dan Malek, + * Copied from ADS85xx. + * Updates for Silicon Tx GP3 8560. + * + * (C) Copyright 2002,2003,Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/stxgp3/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/stxgp3/init.o (.text) + cpu/mpc85xx/commproc.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/serial_scc.o (.text) + cpu/mpc85xx/ether_fcc.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/i2c.o (.text) + cpu/mpc85xx/spd_sdram.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/stxxtc/Makefile b/board/stxxtc/Makefile new file mode 100644 index 0000000..11065cf --- /dev/null +++ b/board/stxxtc/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o oftree.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +%.dtb: %.dts + dtc -f -V 0x10 -I dts -O dtb $< >$@ + +%.c: %.dtb + xxd -i $< \ + | sed -e "s/^unsigned char/const unsigned char/g" \ + | sed -e "s/^unsigned int/const unsigned int/g" > $@ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/stxxtc/config.mk b/board/stxxtc/config.mk new file mode 100644 index 0000000..f5dc034 --- /dev/null +++ b/board/stxxtc/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# STx XTc +# + +TEXT_BASE = 0x40F00000 diff --git a/board/stxxtc/oftree.dts b/board/stxxtc/oftree.dts new file mode 100644 index 0000000..e3f3017 --- /dev/null +++ b/board/stxxtc/oftree.dts @@ -0,0 +1,52 @@ +/ { + model = "STXXTC V1"; + compatible = "STXXTC"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + linux,phandle = <1>; + #address-cells = <1>; + #size-cells = <0>; + PowerPC,MPC870@0 { + linux,phandle = <3>; + name = "PowerPC,MPC870"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <0>; /* place-holder for runtime fillup */ + timebase-frequency = <0>; /* dido */ + linux,boot-cpu; + i-cache-size = <2000>; + d-cache-size = <2000>; + 32-bit; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <00000000 00000000 00000000 20000000>; + }; + + /* copy of the bd_t information (place-holders) */ + bd_t { + memstart = <0>; + memsize = <0>; + flashstart = <0>; + flashsize = <0>; + flashoffset = <0>; + sramstart = <0>; + sramsize = <0>; + + immr_base = <0>; + + bootflags = <0>; + ip_addr = <0>; + enetaddr = [ 00 00 00 00 00 00 ]; + ethspeed = <0>; + intfreq = <0>; + busfreq = <0>; + + baudrate = <0>; + }; + +}; diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c new file mode 100644 index 0000000..aa3d129 --- /dev/null +++ b/board/stxxtc/stxxtc.c @@ -0,0 +1,638 @@ +/* + * (C) Copyright 2000-2004 + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2005 + * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot port on STx XTc board + * Mostly copied from Netta + */ + +#include +#include + +#include "mpc8xx.h" + +#ifdef CONFIG_HW_WATCHDOG +#include +#endif + +/****************************************************************/ + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +/****************************************************************/ + +/* + * Check Board Identity: + * + * Return 1 always. + */ + +int checkboard(void) +{ + printf ("Silicon Turnkey eXpress XTc\n"); + return (0); +} + +/****************************************************************/ + +#define _NOT_USED_ 0xFFFFFFFF + +/****************************************************************/ + +#define CS_0000 0x00000000 +#define CS_0001 0x10000000 +#define CS_0010 0x20000000 +#define CS_0011 0x30000000 +#define CS_0100 0x40000000 +#define CS_0101 0x50000000 +#define CS_0110 0x60000000 +#define CS_0111 0x70000000 +#define CS_1000 0x80000000 +#define CS_1001 0x90000000 +#define CS_1010 0xA0000000 +#define CS_1011 0xB0000000 +#define CS_1100 0xC0000000 +#define CS_1101 0xD0000000 +#define CS_1110 0xE0000000 +#define CS_1111 0xF0000000 + +#define BS_0000 0x00000000 +#define BS_0001 0x01000000 +#define BS_0010 0x02000000 +#define BS_0011 0x03000000 +#define BS_0100 0x04000000 +#define BS_0101 0x05000000 +#define BS_0110 0x06000000 +#define BS_0111 0x07000000 +#define BS_1000 0x08000000 +#define BS_1001 0x09000000 +#define BS_1010 0x0A000000 +#define BS_1011 0x0B000000 +#define BS_1100 0x0C000000 +#define BS_1101 0x0D000000 +#define BS_1110 0x0E000000 +#define BS_1111 0x0F000000 + +#define GPL0_AAAA 0x00000000 +#define GPL0_AAA0 0x00200000 +#define GPL0_AAA1 0x00300000 +#define GPL0_000A 0x00800000 +#define GPL0_0000 0x00A00000 +#define GPL0_0001 0x00B00000 +#define GPL0_111A 0x00C00000 +#define GPL0_1110 0x00E00000 +#define GPL0_1111 0x00F00000 + +#define GPL1_0000 0x00000000 +#define GPL1_0001 0x00040000 +#define GPL1_1110 0x00080000 +#define GPL1_1111 0x000C0000 + +#define GPL2_0000 0x00000000 +#define GPL2_0001 0x00010000 +#define GPL2_1110 0x00020000 +#define GPL2_1111 0x00030000 + +#define GPL3_0000 0x00000000 +#define GPL3_0001 0x00004000 +#define GPL3_1110 0x00008000 +#define GPL3_1111 0x0000C000 + +#define GPL4_0000 0x00000000 +#define GPL4_0001 0x00001000 +#define GPL4_1110 0x00002000 +#define GPL4_1111 0x00003000 + +#define GPL5_0000 0x00000000 +#define GPL5_0001 0x00000400 +#define GPL5_1110 0x00000800 +#define GPL5_1111 0x00000C00 +#define LOOP 0x00000080 + +#define EXEN 0x00000040 + +#define AMX_COL 0x00000000 +#define AMX_ROW 0x00000020 +#define AMX_MAR 0x00000030 + +#define NA 0x00000008 + +#define UTA 0x00000004 + +#define TODT 0x00000002 + +#define LAST 0x00000001 + +#define A10_AAAA GPL0_AAAA +#define A10_AAA0 GPL0_AAA0 +#define A10_AAA1 GPL0_AAA1 +#define A10_000A GPL0_000A +#define A10_0000 GPL0_0000 +#define A10_0001 GPL0_0001 +#define A10_111A GPL0_111A +#define A10_1110 GPL0_1110 +#define A10_1111 GPL0_1111 + +#define RAS_0000 GPL1_0000 +#define RAS_0001 GPL1_0001 +#define RAS_1110 GPL1_1110 +#define RAS_1111 GPL1_1111 + +#define CAS_0000 GPL2_0000 +#define CAS_0001 GPL2_0001 +#define CAS_1110 GPL2_1110 +#define CAS_1111 GPL2_1111 + +#define WE_0000 GPL3_0000 +#define WE_0001 GPL3_0001 +#define WE_1110 GPL3_1110 +#define WE_1111 GPL3_1111 + +/* #define CAS_LATENCY 3 */ +#define CAS_LATENCY 2 + +const uint sdram_table[0x40] = { + +#if CAS_LATENCY == 3 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, +#endif + +#if CAS_LATENCY == 2 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + +#endif + + /* UPT */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, +}; + +static const uint nandcs_table[0x40] = { + /* RSS */ + CS_1000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1110 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111, + CS_0000 | GPL4_0001 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ + + /* RBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_1000 | GPL4_1111 | GPL5_1110 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0001 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, + + /* WBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* UPT */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 , + CS_0001 | LAST, +}; + +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ +/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ +#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) + +/* 9 */ +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +void check_ram(unsigned int addr, unsigned int size) +{ + unsigned int i, j, v, vv; + volatile unsigned int *p; + unsigned int pv; + + p = (unsigned int *)addr; + pv = (unsigned int)p; + for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) + *p++ = pv; + + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + v = (unsigned int)p; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + p++; + } + + for (j = 0; j < 5; j++) { + switch (j) { + case 0: v = 0x00000000; break; + case 1: v = 0xffffffff; break; + case 2: v = 0x55555555; break; + case 3: v = 0xaaaaaaaa; break; + default:v = 0xdeadbeef; break; + } + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + *p = v; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + *p = ~v; + p++; + } + } +} + +#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0) + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + u32 d1, d2; + + upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = MPTPR_PTP_DIV8; + + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or4 = CFG_OR4_PRELIM; + memctl->memc_br4 = CFG_BR4_PRELIM; + + memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initialisation sequence */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ + udelay(1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay(10000); + + + d1 = 0xAA55AA55; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + DO_LOOP; + } + + d1 = 0x55AA55AA; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + DO_LOOP; + } + + d1 = 0x12345678; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + DO_LOOP; + } + + size = get_ram_size((long *)0, SDRAM_MAX_SIZE); + + return size; +} + +/* ------------------------------------------------------------------------- */ + +void reset_phys(void) +{ + int phyno; + unsigned short v; + + udelay(10000); + /* reset the damn phys */ + mii_init(); + + for (phyno = 0; phyno < 32; ++phyno) { + miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v); + if (v == 0xFFFF) + continue; + miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD); + udelay(10000); + miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); + udelay(10000); + } +} + +/* ------------------------------------------------------------------------- */ + +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + +/* bits that can have a special purpose or can be configured as inputs/outputs */ +#define PA_GP_INMASK _BW(6) +#define PA_GP_OUTMASK (_BW(7)) +#define PA_SP_MASK 0 +#define PA_ODR_VAL 0 +#define PA_GP_OUTVAL (_BW(7)) +#define PA_SP_DIRVAL 0 + +#define PB_GP_INMASK 0 +#define PB_GP_OUTMASK (_B(23)) +#define PB_SP_MASK 0 +#define PB_ODR_VAL 0 +#define PB_GP_OUTVAL (_B(23)) +#define PB_SP_DIRVAL 0 + +#define PC_GP_INMASK 0 +#define PC_GP_OUTMASK (_BW(15)) + +#define PC_SP_MASK 0 +#define PC_SOVAL 0 +#define PC_INTVAL 0 +#define PC_GP_OUTVAL 0 +#define PC_SP_DIRVAL 0 + +#define PE_GP_INMASK 0 +#define PE_GP_OUTMASK 0 +#define PE_GP_OUTVAL 0 + +#define PE_SP_MASK 0 +#define PE_ODR_VAL 0 +#define PE_SP_DIRVAL 0 + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + (void)ioport; + (void)cpm; +#if 1 + /* NAND chip select */ + upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); + memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); + memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB); + memctl->memc_mbmr = 0; /* all clear */ +#endif + + memctl->memc_br5 &= ~BR_V; + memctl->memc_br6 &= ~BR_V; + memctl->memc_br7 &= ~BR_V; + +#if 1 + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + cpm->cp_pedat = PE_GP_OUTVAL; + cpm->cp_peodr = PE_ODR_VAL; + cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; + cpm->cp_pepar = PE_SP_MASK; +#endif + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include + +extern ulong nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + unsigned long totlen; + + totlen = nand_probe(CFG_NAND_BASE); + printf ("%4lu MB\n", totlen >> 20); +} +#endif + +#ifdef CONFIG_HW_WATCHDOG + +void hw_watchdog_reset(void) +{ + /* XXX add here the really funky stuff */ +} + +#endif + +#ifdef CONFIG_SHOW_ACTIVITY + +/* called from timer interrupt every 1/CFG_HZ sec */ +void board_show_activity(ulong timestamp) +{ +} + +/* called when looping */ +void show_activity(int arg) +{ +} + +#endif + +#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + /* printf("overwrite_console called\n"); */ + return 0; +} +#endif + +extern int drv_phone_init(void); +extern int drv_phone_use_me(void); +extern int drv_phone_is_idle(void); + +int misc_init_r(void) +{ + return 0; +} + +int last_stage_init(void) +{ + reset_phys(); + + return 0; +} diff --git a/board/stxxtc/u-boot.lds b/board/stxxtc/u-boot.lds new file mode 100644 index 0000000..9f2901c --- /dev/null +++ b/board/stxxtc/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/stxxtc/u-boot.lds.debug b/board/stxxtc/u-boot.lds.debug new file mode 100644 index 0000000..004e7fd --- /dev/null +++ b/board/stxxtc/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/svm_sc8xx/Makefile b/board/svm_sc8xx/Makefile new file mode 100644 index 0000000..13ce9fc --- /dev/null +++ b/board/svm_sc8xx/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/svm_sc8xx/config.mk b/board/svm_sc8xx/config.mk new file mode 100644 index 0000000..4bec9cb --- /dev/null +++ b/board/svm_sc8xx/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x40000000 diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c new file mode 100644 index 0000000..25e61dd --- /dev/null +++ b/board/svm_sc8xx/flash.c @@ -0,0 +1,797 @@ +/* + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifndef CFG_ENV_ADDR +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word (flash_info_t *info, ulong dest, ulong data); +#if 0 +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static void flash_get_offsets (ulong base, flash_info_t *info); +#endif +#ifdef CONFIG_BOOT_8B +static int my_in_8( unsigned char *addr); +static void my_out_8( unsigned char *addr, int val); +#endif +#ifdef CONFIG_BOOT_16B +static int my_in_be16( unsigned short *addr); +static void my_out_be16( unsigned short *addr, int val); +#endif +#ifdef CONFIG_BOOT_32B +static unsigned my_in_be32( unsigned *addr); +static void my_out_be32( unsigned *addr, int val); +#endif +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + size_b0=0; + size_b1=0; + /* Init: no FLASHes known */ + for (i=0; imemc_or5 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */ + memctl->memc_br5 = CFG_DOC_BASE | 0x401; +#else + memctl->memc_or3 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */ + memctl->memc_br3 = CFG_DOC_BASE | 0x401; +#endif +#endif +#if defined( CONFIG_BOOT_8B) +/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */ +/* memctl->memc_br0 = 0x40000401; */ + size_b0 = 0x80000; /* 512 K */ + flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040; + flash_info[0].sector_count = 8; + flash_info[0].size = 0x00080000; + /* set up sector start address table */ + for (i = 0; i < flash_info[0].sector_count; i++) + flash_info[0].start[i] = 0x40000000 + (i * 0x10000); + /* protect all sectors */ + for (i = 0; i < flash_info[0].sector_count; i++) + flash_info[0].protect[i] = 0x1; +#elif defined (CONFIG_BOOT_16B) +/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */ +/* memctl->memc_br0 = 0x40000401; */ + size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ + flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B; + flash_info[0].sector_count = 67; + flash_info[0].size = 0x00400000; + /* set up sector start address table */ + flash_info[0].start[0] = 0x40000000 ; + flash_info[0].start[1] = 0x40000000 + 0x4000; + flash_info[0].start[2] = 0x40000000 + 0x6000; + flash_info[0].start[3] = 0x40000000 + 0x8000; + for (i = 4; i < flash_info[0].sector_count; i++) + flash_info[0].start[i] = 0x40000000 + 0x10000 + ((i-4) * 0x10000); + /* protect all sectors */ + for (i = 0; i < flash_info[0].sector_count; i++) + flash_info[0].protect[i] = 0x1; +#endif + + +#ifdef CONFIG_BOOT_32B + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0<<20); + } + + size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); + + if (size_b1 > size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + + if (size_b1) { + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V; + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[1]); +#endif + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + +#endif /* CONFIG_BOOT_32B */ + + return (size_b0 + size_b1); +} +#if 0 +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +} +#endif +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +#if 0 +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} +#endif + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect,in_mid,in_did; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); +#if defined (CONFIG_BOOT_8B ) + my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0xaa ); + my_out_8( (unsigned char * ) ((ulong)addr+0x2aa) , 0x55 ); + my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0x90 ); + in_mid=my_in_8( (unsigned char * ) addr ); + in_did=my_in_8( (unsigned char * ) ((ulong)addr+1) ); + printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); + my_out_8( (unsigned char *)addr, 0xf0); + udelay(1); + my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); + my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); + my_out_8( (unsigned char *) ((ulong)addr+0x555),0x80 ); + my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); + my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + /*addr[0] = 0x00300030; */ + my_out_8( (unsigned char *) ((ulong)addr),0x30 ); + l_sect = sect; + } + } +#elif defined(CONFIG_BOOT_16B ) + my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0xaa ); + my_out_be16( (unsigned short * ) ((ulong)addr+ (0x554)) , 0x55 ); + my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0x90 ); + in_mid=my_in_be16( (unsigned short * ) addr ); + in_did=my_in_be16 ( (unsigned short * ) ((ulong)addr+2) ); + printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); + my_out_be16( (unsigned short *)addr, 0xf0); + udelay(1); + my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); + my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); + my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0x80 ); + my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0xaa ); + my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + my_out_be16( (unsigned short *) ((ulong)addr),0x30 ); + l_sect = sect; + } + } + +#elif defined(CONFIG_BOOT_32B) + my_out_be32( (unsigned * ) ((ulong)addr+0x1554) , 0xaa ); + my_out_be32( (unsigned * ) ((ulong)addr+0xaa8) , 0x55 ); + my_out_be32( (unsigned *) ((ulong)addr+0x1554) , 0x90 ); + in_mid=my_in_be32( (unsigned * ) addr ); + in_did=my_in_be32( (unsigned * ) ((ulong)addr+4) ); + printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); + my_out_be32( (unsigned *)addr, 0xf0); + udelay(1); + my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); + my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); + my_out_be32( (unsigned *) ((ulong)addr+0x1554),0x80 ); + my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); + my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + my_out_be32( (unsigned *) ((ulong)addr),0x00300030 ); + l_sect = sect; + } + } + +#else +# error CONFIG_BOOT_(size)B missing. +#endif + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); +#if defined (CONFIG_BOOT_8B) + while ( (my_in_8((unsigned char *)addr) & 0x80) != 0x80 ) +#elif defined(CONFIG_BOOT_16B ) + while ( (my_in_be16((unsigned short *)addr) & 0x0080) != 0x0080 ) +#elif defined(CONFIG_BOOT_32B) + while ( (my_in_be32((unsigned *)addr) & 0x00800080) != 0x00800080 ) +#else +# error CONFIG_BOOT_(size)B missing. +#endif + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; +#if defined (CONFIG_BOOT_8B) + my_out_8( (unsigned char *)addr, 0xf0); +#elif defined(CONFIG_BOOT_16B ) + my_out_be16( (unsigned short * ) addr , 0x00f0 ); +#elif defined(CONFIG_BOOT_32B) + my_out_be32 ( (unsigned *)addr, 0x00F000F0 ); /* reset bank */ +#else +# error CONFIG_BOOT_(size)B missing. +#endif + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + ulong addr = (ulong)(info->start[0]); + ulong start,last; + int flag; + ulong i; + int data_short[2]; + + /* Check if Flash is (sufficiently) erased */ + if ( ((ulong) *(ulong *)dest & data) != data ) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); +#if defined(CONFIG_BOOT_8B) +#ifdef DEBUG + { + int in_mid,in_did; + my_out_8( (unsigned char * ) (addr+0x555) , 0xaa ); + my_out_8( (unsigned char * ) (addr+0x2aa) , 0x55 ); + my_out_8( (unsigned char * ) (addr+0x555) , 0x90 ); + in_mid=my_in_8( (unsigned char * ) addr ); + in_did=my_in_8( (unsigned char * ) (addr+1) ); + printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); + my_out_8( (unsigned char *)addr, 0xf0); + udelay(1); + } +#endif + { + int data_ch[4]; + data_ch[0]=(int ) ((data>>24) & 0xff); + data_ch[1]=(int ) ((data>>16) &0xff ); + data_ch[2]=(int ) ((data >>8) & 0xff); + data_ch[3]=(int ) (data & 0xff); + for (i=0;i<4;i++ ){ + my_out_8( (unsigned char *) (addr+0x555),0xaa); + my_out_8((unsigned char *) (addr+0x2aa),0x55); + my_out_8( (unsigned char *) (addr+0x555),0xa0); + my_out_8((unsigned char *) (dest+i) ,data_ch[i]); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + last = start; + while( ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i] ) ) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) { + return 1; + } + } + }/* for */ + } +#elif defined( CONFIG_BOOT_16B) + data_short[0]=(int) (data>>16) & 0xffff; + data_short[1]=(int ) data & 0xffff ; + for (i=0;i<2;i++ ){ + my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); + my_out_be16( (unsigned short *) ((ulong)addr+ 0x554),0x55 ); + my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xa0 ); + my_out_be16( (unsigned short *) (dest+(i*2)) ,data_short[i]); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + start = get_timer (0); + last = start; + while( ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i] ) ) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) { + return 1; + } + } + } +#elif defined( CONFIG_BOOT_32B) + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } +#endif + + + return (0); +} +#ifdef CONFIG_BOOT_8B +static int my_in_8 ( unsigned char *addr) +{ + int ret; + __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static void my_out_8 ( unsigned char *addr, int val) +{ + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} +#endif +#ifdef CONFIG_BOOT_16B +static int my_in_be16( unsigned short *addr) +{ + int ret; + __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} +static void my_out_be16( unsigned short *addr, int val) +{ + __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} +#endif +#ifdef CONFIG_BOOT_32B +static unsigned my_in_be32( unsigned *addr) +{ + unsigned ret; + __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} +static void my_out_be32( unsigned *addr, int val) +{ + __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} +#endif diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c new file mode 100644 index 0000000..9bb9fd0 --- /dev/null +++ b/board/svm_sc8xx/svm_sc8xx.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ +const uint sdram_table[] = +{ +/*----------------- + UPM A contents: +----------------- */ +/*--------------------------------------------------- + Read Single Beat Cycle. Offset 0 in the RAM array. +---------------------------------------------------- */ +0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 , +0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 , +/*------------------------------------------------ + Read Burst Cycle. Offset 0x8 in the RAM array. +------------------------------------------------ */ +0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, +0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, +0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, +0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, +/*------------------------------------------------------- + Write Single Beat Cycle. Offset 0x18 in the RAM array +------------------------------------------------------- */ +0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 , +0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , +/*------------------------------------------------- + Write Burst Cycle. Offset 0x20 in the RAM array +------------------------------------------------- */ +0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, +0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff, +0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , +0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , +/*------------------------------------------------------------------------ + Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array +------------------------------------------------------------------------ */ +0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, +0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff, +0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , +/*----------- +* Exception: +* ----------- */ +0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff , +}; + +/* ------------------------------------------------------------------------- */ +/* + * Check Board Identity: + * + * Test ID string (SVM8...) + * + * Return 1 for "SC8xx" type, 0 else. + */ + +int checkboard (void) +{ + char *s = getenv("serial#"); + int board_type; + + if (!s || strncmp(s, "SVM8", 4)) { + printf ("### No HW ID - assuming SVM SC8xx\n"); + return (0); + } + + board_type = 1; + + for (; *s; ++s) { + if (*s == ' ') + break; + putc (*s); + } + + putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0 = 0; + + upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + memctl->memc_mptpr = CFG_MPTPR; +#if defined (CONFIG_SDRAM_16M) + memctl->memc_mamr = 0x00802114 | CFG_MxMR_PTx; + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay(1); + memctl->memc_mcr = 0x80002830; + udelay(1); + memctl->memc_mar = 0x00000088; + udelay(1); + memctl->memc_mcr = 0x80002106; + udelay(1); + memctl->memc_or1 = 0xff000a00; + size_b0 = 0x01000000; +#elif defined (CONFIG_SDRAM_32M) + memctl->memc_mamr = 0x00904114 | CFG_MxMR_PTx; + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay(1); + memctl->memc_mcr = 0x80002830; + udelay(1); + memctl->memc_mar = 0x00000088; + udelay(1); + memctl->memc_mcr = 0x80002106; + udelay(1); + memctl->memc_or1 = 0xfe000a00; + size_b0 = 0x02000000; +#elif defined (CONFIG_SDRAM_64M) + memctl->memc_mamr = 0x00a04114 | CFG_MxMR_PTx; + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay(1); + memctl->memc_mcr = 0x80002830; + udelay(1); + memctl->memc_mar = 0x00000088; + udelay(1); + memctl->memc_mcr = 0x80002106; + udelay(1); + memctl->memc_or1 = 0xfc000a00; + size_b0 = 0x04000000; +#else +#error SDRAM size configuration missing. +#endif + memctl->memc_br1 = 0x00000081; + udelay(200); + return (size_b0 ); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds new file mode 100644 index 0000000..d7f7dc1 --- /dev/null +++ b/board/svm_sc8xx/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = env_offset; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug new file mode 100644 index 0000000..894b9bd --- /dev/null +++ b/board/svm_sc8xx/u-boot.lds.debug @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sx1/Makefile b/board/sx1/Makefile new file mode 100644 index 0000000..8fbdf2a --- /dev/null +++ b/board/sx1/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := sx1.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sx1/config.mk b/board/sx1/config.mk new file mode 100644 index 0000000..4902e82 --- /dev/null +++ b/board/sx1/config.mk @@ -0,0 +1,19 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, +# +# SX1 board with OMAP1510 (ARM925T) cpu +# see http://www.ti.com/ for more information on Texas Insturments +# +# SX1 has 1 bank of 256 MB SDRAM +# Physical Address: +# 1000'0000 to 2000'0000 +# +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved) +# +# we load ourself to 1108'0000 +# +# + +TEXT_BASE = 0x11080000 diff --git a/board/sx1/lowlevel_init.S b/board/sx1/lowlevel_init.S new file mode 100644 index 0000000..bdf812e --- /dev/null +++ b/board/sx1/lowlevel_init.S @@ -0,0 +1,397 @@ +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, + * + * -- Some bits of code used from rrload's head_OMAP1510.s -- + * Copyright (C) 2002 RidgeRun, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_OMAP1510) +#include <./configs/omap1510.h> +#endif + +#define OMAP1510_CLKS ((1< + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +static void flash__init (void); +static void ether__init (void); + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of SX1 Board */ + gd->bd->bi_arch_number = MACH_TYPE_SX1; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + +/* kk - this speeds up your boot a quite a bit. However to make it + * work, you need make sure your kernel startup flush bug is fixed. + * ... rkw ... + */ + icache_enable (); + + flash__init (); + ether__init (); + return 0; +} + + +int misc_init_r (void) +{ + /* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ + /* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ + + /* setup gpio direction to match board (no floats!) */ + /**gdir = 0xCFF9; */ + /**mdir = 0x103F; */ + + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +static void flash__init (void) +{ +#define CS0_CHIP_SELECT_REG 0xfffecc10 +#define CS3_CHIP_SELECT_REG 0xfffecc1c +#define EMIFS_GlB_Config_REG 0xfffecc0c + + unsigned int regval; + + regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); + regval = regval | 0x0001; /* Turn off write protection for flash devices. */ + if (regval & 0x0002) { + regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ + /* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ + /* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ + /* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ + } + *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; +} + + +/****************************** + Routine: + Description: +******************************/ +static void ether__init (void) +{ +#define ETH_CONTROL_REG 0x0800000b + /* take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + */ + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; + udelay (3); +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/board/sx1/u-boot.lds b/board/sx1/u-boot.lds new file mode 100644 index 0000000..d28155f --- /dev/null +++ b/board/sx1/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm925t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/tb0229/Makefile b/board/tb0229/Makefile new file mode 100644 index 0000000..4375073 --- /dev/null +++ b/board/tb0229/Makefile @@ -0,0 +1,43 @@ +# +# (C) Masami Komiya 2004 +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o vr4131-pci.o +SOBJS = lowlevel_init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/tb0229/config.mk b/board/tb0229/config.mk new file mode 100644 index 0000000..9a50850 --- /dev/null +++ b/board/tb0229/config.mk @@ -0,0 +1,30 @@ +# +# (C) Masami Komiya 2004 +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# ROM version +TEXT_BASE = 0xBFC00000 + +# RAM version +#TEXT_BASE = 0x80400000 diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c new file mode 100644 index 0000000..e9f6418 --- /dev/null +++ b/board/tb0229/flash.c @@ -0,0 +1,1198 @@ +/* + * (C) Masami Komiya 2004 + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +#ifdef CFG_FLASH_16BIT +#define FLASH_WORD_SIZE unsigned short +#define FLASH_ID_MASK 0xFFFF +#else +#define FLASH_WORD_SIZE unsigned long +#define FLASH_ID_MASK 0xFFFFFFFF +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +/* stolen from esteem192e/flash.c */ +ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info); + +#ifndef CFG_FLASH_16BIT +static int write_word (flash_info_t * info, ulong dest, ulong data); +#else +static int write_short (flash_info_t * info, ulong dest, ushort data); +#endif +static void flash_get_offsets (ulong base, flash_info_t * info); + + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = + flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE, + &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20); + } + + /* Only one bank */ + if (CFG_MAX_FLASH_BANKS == 1) { + /* Setup offsets */ + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + /* Monitor protection ON by default */ +#if 0 /* sand: */ + (void) flash_protect (FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM - monitor_flash_len + + size_b0, + FLASH_BASE0_PRELIM - 1 + size_b0, + &flash_info[0]); +#else + (void) flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - + 1, &flash_info[0]); +#endif + size_b1 = 0; + flash_info[0].size = size_b0; + } +#ifdef CFG_FLASH_BASE_2 + /* 2 banks */ + else { + size_b1 = + flash_get_size ((volatile FLASH_WORD_SIZE *) + CFG_FLASH_BASE_2, &flash_info[1]); + + /* Re-do sizing to get full correct info */ + + if (size_b1) { + mtdcr (ebccfga, pb0cr); + pbcr = mfdcr (ebccfgd); + mtdcr (ebccfga, pb0cr); + base_b1 = -size_b1; + pbcr = (pbcr & 0x0001ffff) | base_b1 | + (((size_b1 / 1024 / 1024) - 1) << 17); + mtdcr (ebccfgd, pbcr); + /* printf("pb1cr = %x\n", pbcr); */ + } + + if (size_b0) { + mtdcr (ebccfga, pb1cr); + pbcr = mfdcr (ebccfgd); + mtdcr (ebccfga, pb1cr); + base_b0 = base_b1 - size_b0; + pbcr = (pbcr & 0x0001ffff) | base_b0 | + (((size_b0 / 1024 / 1024) - 1) << 17); + mtdcr (ebccfgd, pbcr); + /* printf("pb0cr = %x\n", pbcr); */ + } + + size_b0 = + flash_get_size ((volatile FLASH_WORD_SIZE *) base_b0, + &flash_info[0]); + + flash_get_offsets (base_b0, &flash_info[0]); + + /* monitor protection ON by default */ +#if 0 /* sand: */ + (void) flash_protect (FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM - monitor_flash_len + + size_b0, + FLASH_BASE0_PRELIM - 1 + size_b0, + &flash_info[0]); +#else + (void) flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - + 1, &flash_info[0]); +#endif + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = + flash_get_size ((volatile FLASH_WORD_SIZE *) + base_b1, &flash_info[1]); + + flash_get_offsets (base_b1, &flash_info[1]); + + /* monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + base_b1 + size_b1 - + monitor_flash_len, + base_b1 + size_b1 - 1, + &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + (void) flash_protect (FLAG_PROTECT_CLEAR, + base_b0 + size_b0 - + monitor_flash_len, + base_b0 + size_b0 - 1, + &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + } /* else 2 banks */ +#endif + return (size_b0 + size_b1); +} + + +/*----------------------------------------------------------------------- + */ + +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start adress table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F320J3A || + (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A || + (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = + base + (i * info->size / info->sector_count); + } + } else if (info->flash_id & FLASH_BTYPE) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CFG_FLASH_16BIT + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00008000; + info->start[3] = base + 0x0000C000; + info->start[4] = base + 0x00010000; + info->start[5] = base + 0x00014000; + info->start[6] = base + 0x00018000; + info->start[7] = base + 0x0001C000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00020000) - 0x000E0000; + } + } else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00020000) - 0x00060000; + } + } +#else + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000A000; + info->start[6] = base + 0x0000C000; + info->start[7] = base + 0x0000E000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00070000; + } + } else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } +#endif + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + +#ifndef CFG_FLASH_16BIT + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00014000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x0001C000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + + } else { + + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +#else + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000A000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x0000E000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + + } else { + + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } +#endif + } + + +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t * info) +{ + int i; + uchar *boottype; + uchar botboot[] = ", bottom boot sect)\n"; + uchar topboot[] = ", top boot sector)\n"; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_SST: + printf ("SST "); + break; + case FLASH_MAN_STM: + printf ("STM "); + break; + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + if (info->flash_id & 0x0001) { + boottype = botboot; + } else { + boottype = topboot; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: + printf ("AM29LV400B (4 Mbit%s", boottype); + break; + case FLASH_AM400T: + printf ("AM29LV400T (4 Mbit%s", boottype); + break; + case FLASH_AM800B: + printf ("AM29LV800B (8 Mbit%s", boottype); + break; + case FLASH_AM800T: + printf ("AM29LV800T (8 Mbit%s", boottype); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit%s", boottype); + break; + case FLASH_AM160T: + printf ("AM29LV160T (16 Mbit%s", boottype); + break; + case FLASH_AM320B: + printf ("AM29LV320B (32 Mbit%s", boottype); + break; + case FLASH_AM320T: + printf ("AM29LV320T (32 Mbit%s", boottype); + break; + case FLASH_INTEL800B: + printf ("INTEL28F800B (8 Mbit%s", boottype); + break; + case FLASH_INTEL800T: + printf ("INTEL28F800T (8 Mbit%s", boottype); + break; + case FLASH_INTEL160B: + printf ("INTEL28F160B (16 Mbit%s", boottype); + break; + case FLASH_INTEL160T: + printf ("INTEL28F160T (16 Mbit%s", boottype); + break; + case FLASH_INTEL320B: + printf ("INTEL28F320B (32 Mbit%s", boottype); + break; + case FLASH_INTEL320T: + printf ("INTEL28F320T (32 Mbit%s", boottype); + break; + +#if 0 /* enable when devices are available */ + + case FLASH_INTEL640B: + printf ("INTEL28F640B (64 Mbit%s", boottype); + break; + case FLASH_INTEL640T: + printf ("INTEL28F640T (64 Mbit%s", boottype); + break; +#endif + case FLASH_28F320J3A: + printf ("INTEL28F320J3A (32 Mbit%s", boottype); + break; + case FLASH_28F640J3A: + printf ("INTEL28F640J3A (64 Mbit%s", boottype); + break; + case FLASH_28F128J3A: + printf ("INTEL28F128J3A (128 Mbit%s", boottype); + break; + + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) +{ + short i; + ulong base = (ulong) addr; + FLASH_WORD_SIZE value; + + /* Write auto select command: read Manufacturer ID */ + + +#ifndef CFG_FLASH_16BIT + + /* + * Note: if it is an AMD flash and the word at addr[0000] + * is 0x00890089 this routine will think it is an Intel + * flash device and may(most likely) cause trouble. + */ + + addr[0x0000] = 0x00900090; + if (addr[0x0000] != 0x00890089) { + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; +#else + + /* + * Note: if it is an AMD flash and the word at addr[0000] + * is 0x0089 this routine will think it is an Intel + * flash device and may(most likely) cause trouble. + */ + + addr[0x0000] = 0x0090; + + if (addr[0x0000] != 0x0089) { + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0090; +#endif + } + value = addr[0]; + + switch (value) { + case (AMD_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_AMD; + break; + case (FUJ_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_FUJ; + break; + case (STM_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_STM; + break; + case (SST_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_SST; + break; + case (INTEL_MANUFACT & FLASH_ID_MASK): + info->flash_id = FLASH_MAN_INTEL; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + + } + + value = addr[1]; /* device ID */ + + switch (value) { + + case (AMD_ID_LV400T & FLASH_ID_MASK): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV400B & FLASH_ID_MASK): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (AMD_ID_LV800T & FLASH_ID_MASK): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV800B & FLASH_ID_MASK): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (AMD_ID_LV160T & FLASH_ID_MASK): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (AMD_ID_LV160B & FLASH_ID_MASK): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case (AMD_ID_LV320T & FLASH_ID_MASK): + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (AMD_ID_LV320B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + + case (INTEL_ID_28F800B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL800T; + info->sector_count = 23; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (INTEL_ID_28F800B3B & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (INTEL_ID_28F160B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL160T; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (INTEL_ID_28F160B3B & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (INTEL_ID_28F320B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL320T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case (INTEL_ID_28F320B3B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + +#if 0 /* enable when devices are available */ + case (INTEL_ID_28F320B3T & FLASH_ID_MASK): + info->flash_id += FLASH_INTEL320T; + info->sector_count = 135; + info->size = 0x01000000; + break; /* => 16 MB */ + + case (INTEL_ID_28F320B3B & FLASH_ID_MASK): + info->flash_id += FLASH_AM320B; + info->sector_count = 135; + info->size = 0x01000000; + break; /* => 16 MB */ +#endif + case (INTEL_ID_28F320J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000; + break; /* => 32 MBit */ + case (INTEL_ID_28F640J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000; + break; /* => 64 MBit */ + case (INTEL_ID_28F128J3A & FLASH_ID_MASK): + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000; + break; /* => 128 MBit */ + + default: + /* FIXME */ + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets (base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile FLASH_WORD_SIZE *) (info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile FLASH_WORD_SIZE *) info->start[0]; + if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) { + *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { + *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ + } + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + + volatile FLASH_WORD_SIZE *addr = + (volatile FLASH_WORD_SIZE *) (info->start[0]); + int flag, prot, sect, l_sect, barf; + ulong start, now, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + ((info->flash_id > FLASH_AMD_COMP) && + ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + if (info->flash_id < FLASH_AMD_COMP) { +#ifndef CFG_FLASH_16BIT + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; +#else + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0080; + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; +#endif + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (volatile FLASH_WORD_SIZE *) (info-> + start + [sect]); + addr[0] = (0x00300030 & FLASH_ID_MASK); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); + while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != + (0x00800080 & FLASH_ID_MASK)) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (volatile FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { + + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + barf = 0; +#ifndef CFG_FLASH_16BIT + addr = (vu_long *) (info->start[sect]); + addr[0] = 0x00500050; + addr[0] = 0x00200020; + addr[0] = 0x00D000D0; + while (!(addr[0] & 0x00800080)); /* wait for error or finish */ + if (addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if (barf) { + barf >>= 16; + } else { + barf = addr[0] & 0x0000003A; + } + } +#else + addr = (vu_short *) (info->start[sect]); + addr[0] = 0x0050; /* clear status register */ + addr[0] = 0x0020; + addr[0] = 0x00D0; + while (!(addr[0] & 0x0080)); /* wait for error or finish */ + if (addr[0] & 0x003A) /* check for error */ + barf = addr[0] & 0x003A; +#endif + if (barf) { + printf ("\nFlash error in sector at %lx\n", (unsigned long) addr); + if (barf & 0x0002) + printf ("Block locked, not erased.\n"); + if ((barf & 0x0030) == 0x0030) + printf ("Command Sequence error.\n"); + if ((barf & 0x0030) == 0x0020) + printf ("Block Erase error.\n"); + if (barf & 0x0008) + printf ("Vpp Low error.\n"); + rcode = 1; + } else + printf ("."); + l_sect = sect; + } + addr = (volatile FLASH_WORD_SIZE *) info->start[0]; +#ifndef CFG_FLASH_16BIT + addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ +#else + addr[0] = (0x00FF & FLASH_ID_MASK); /* reset bank */ +#endif + } + + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ + +/*flash_info_t *addr2info (ulong addr) +{ + flash_info_t *info; + int i; + + for (i=0, info=&flash_info[0]; i= info->start[0]) && + (addr < (info->start[0] + info->size)) ) { + return (info); + } + } + + return (NULL); +} +*/ +/*----------------------------------------------------------------------- + * Copy memory to flash. + * Make sure all target addresses are within Flash bounds, + * and no protected sectors are hit. + * Returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - target range includes protected sectors + * 8 - target address not in Flash memory + */ + +/*int flash_write (uchar *src, ulong addr, ulong cnt) +{ + int i; + ulong end = addr + cnt - 1; + flash_info_t *info_first = addr2info (addr); + flash_info_t *info_last = addr2info (end ); + flash_info_t *info; + + if (cnt == 0) { + return (0); + } + + if (!info_first || !info_last) { + return (8); + } + + for (info = info_first; info <= info_last; ++info) { + ulong b_end = info->start[0] + info->size;*/ /* bank end addr */ +/* short s_end = info->sector_count - 1; + for (i=0; isector_count; ++i) { + ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; + + if ((end >= info->start[i]) && (addr < e_addr) && + (info->protect[i] != 0) ) { + return (4); + } + } + } + +*/ /* finally write data to flash */ +/* for (info = info_first; info <= info_last && cnt>0; ++info) { + ulong len; + + len = info->start[0] + info->size - addr; + if (len > cnt) + len = cnt; + if ((i = write_buff(info, src, addr, len)) != 0) { + return (i); + } + cnt -= len; + addr += len; + src += len; + } + return (0); +} +*/ +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ +#ifndef CFG_FLASH_16BIT + ulong cp, wp, data; + int l; +#else + ulong cp, wp; + ushort data; +#endif + int i, rc; + +#ifndef CFG_FLASH_16BIT + + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); + +#else + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start byte + */ + if (addr - wp) { + data = 0; + data = (data << 8) | *src++; + --cnt; + if ((rc = write_short (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ +/* l = 0; used for debuging */ + while (cnt >= 2) { + data = 0; + for (i = 0; i < 2; ++i) { + data = (data << 8) | *src++; + } + +/* if(!l){ + printf("%x",data); + l = 1; + } used for debuging */ + + if ((rc = write_short (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_short (info, wp, data)); + + +#endif +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifndef CFG_FLASH_16BIT +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *) (info->start[0]); + ulong start, barf; + int flag; + +#if defined (__MIPSEL__) + data = cpu_to_be32 (data); +#endif + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *) dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + if (info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + } else { + /* intel stuff */ + *addr = 0x00400040; + } + + *((vu_long *) dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + + if (info->flash_id < FLASH_AMD_COMP) { + + while ((*((vu_long *) dest) & 0x00800080) != + (data & 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + printf ("timeout\n"); + return (1); + } + } + + } else { + + while (!(addr[0] & 0x00800080)) { /* wait for error or finish */ + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + printf ("timeout\n"); + return (1); + } + } + + if (addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if (barf) { + barf >>= 16; + } else { + barf = addr[0] & 0x0000003A; + } + printf ("\nFlash write error at address %lx\n", + (unsigned long) dest); + if (barf & 0x0002) + printf ("Block locked, not erased.\n"); + if (barf & 0x0010) + printf ("Programming error.\n"); + if (barf & 0x0008) + printf ("Vpp Low error.\n"); + return (2); + } + + + } + + return (0); +} + +#else + +static int write_short (flash_info_t * info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) (info->start[0]); + ulong start, barf; + int flag; + +#if defined (__MIPSEL__) + data = cpu_to_be16 (data); +#endif + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_short *) dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + if (info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x00A0; + } else { + /* intel stuff */ + *addr = 0x00D0; + *addr = 0x0040; + } + *((vu_short *) dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + + if (info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + } else { + /* intel stuff */ + while (!(addr[0] & 0x0080)) { /* wait for error or finish */ + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + + if (addr[0] & 0x003A) { /* check for error */ + barf = addr[0] & 0x003A; + printf ("\nFlash write error at address %lx\n", + (unsigned long) dest); + if (barf & 0x0002) + printf ("Block locked, not erased.\n"); + if (barf & 0x0010) + printf ("Programming error.\n"); + if (barf & 0x0008) + printf ("Vpp Low error.\n"); + return (2); + } + *addr = 0x00B0; + *addr = 0x0070; + while (!(addr[0] & 0x0080)) { /* wait for error or finish */ + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + + *addr = 0x00FF; + + } + + return (0); + +} +#endif diff --git a/board/tb0229/lowlevel_init.S b/board/tb0229/lowlevel_init.S new file mode 100644 index 0000000..df31806 --- /dev/null +++ b/board/tb0229/lowlevel_init.S @@ -0,0 +1,71 @@ +/* + * Memory sub-system initialization code for TANBAC Evaluation board TB0229. + * + * Copyright (c) 2003 Masami Komiya + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +#include +#include +#include + + + .globl lowlevel_init +lowlevel_init: + + /* BCUCNTREG1 = 0x0040 */ + la t0, 0xaf000000 + li t1, 0x0040 + sh t1, 0(t0) + + /* ROMSIZEREG = 0x3333 */ + la t0, 0xaf000004 + li t1, 0x3333 + sh t1, 0(t0) + + /* ROMSPEEDREG = 0x3003 */ + la t0, 0xaf000006 + li t1, 0x3003 + sh t1, 0(t0) + + /* BCUCNTREG3 = 0 */ + la t0, 0xaf000016 + li t1, 0x0000 + sh t1, 0(t0) + + /* CMUCLKMSK */ + la t0, 0xaf000060 + li t1, 0x39a2 + sh t1, 0(t0) + + /* PMUCNTREG */ + la t0, 0xaf0000c2 + li t1, 0x0006 + sh t1, 0(t0) + + /* SDRAMMODEREG = 0x8029 */ + la t0, 0xaf000400 + li t1, 0x8029 + sh t1, 0(t0) + + /* SDRAMCNTREG = 0x2322 */ + la t0, 0xaf000402 + li t1, 0x2322 + sh t1, 0(t0) + + /* BCURFCNTREG = 0x0106 */ + la t0, 0xaf000404 + li t1, 0x0106 + sh t1, 0(t0) + + /* RAMSZEREG = 0x5555 (64MB Bank) */ + la t0, 0xaf000408 + li t1, 0x5555 + sh t1, 0(t0) + + j ra + nop diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c new file mode 100644 index 0000000..e7914bd --- /dev/null +++ b/board/tb0229/tb0229.c @@ -0,0 +1,42 @@ +/* + * Board initialize code for TANBAC Evaluation board TB0229. + * + * (C) Masami Komiya 2004 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include + +unsigned long mips_io_port_base = 0; + +#if defined(CONFIG_PCI) +static struct pci_controller hose; + +void pci_init_board (void) +{ + init_vr4131_pci(&hose); +} +#endif + + +long int initdram(int board_type) +{ + return get_ram_size (CFG_SDRAM_BASE, 0x8000000); +} + + +int checkboard (void) +{ + printf("Board: TANBAC TB0229 "); + printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000); + + return 0; +} diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds new file mode 100644 index 0000000..30a2bc5 --- /dev/null +++ b/board/tb0229/u-boot.lds @@ -0,0 +1,69 @@ +/* + * (C) Masami Komiya 2004 + * + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") + +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c new file mode 100644 index 0000000..0ee4bf3 --- /dev/null +++ b/board/tb0229/vr4131-pci.c @@ -0,0 +1,254 @@ +/* + * VR4131 PCIU support code for TANBAC Evaluation board TB0229. + * + * (C) Masami Komiya 2004 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +#include +#include +#include + +#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00) +#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04) +#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08) +#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c) +#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10) +#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14) +#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18) +#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c) +#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24) +#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28) +#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c) +#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30) +#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34) +#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38) +#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c) +#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60) +#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00) +#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) +#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) +#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) +#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) +#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) +#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) +#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) +#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) +#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10) +#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14) +#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18) + +/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */ +/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */ +/*#define VR4122_PCI_HOST_BASE 0xa0000000 */ + +volatile unsigned int *pciconfigaddr; +volatile unsigned int *pciconfigdata; + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +/* + * Access PCI Configuration Register for VR4131 + */ + +static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg, + u32 * data) +{ + u32 bus; + u32 device; + + bus = ((dev & 0xff0000) >> 16); + device = ((dev & 0xf800) >> 11); + + if (bus == 0) { + /* Type 0 Configuration */ + *VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc)); + } else { + /* Type 1 Configuration */ + *VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1); + } + + if (access_type == PCI_ACCESS_WRITE) { + *VR4131_PCICONFDREG = *data; + } else { + *data = *VR4131_PCICONFDREG; + } + + return (0); +} + +static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val) +{ + u32 data; + + if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) + return -1; + + *val = (data >> ((reg & 3) << 3)) & 0xff; + + return 0; +} + + +static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val) +{ + u32 data; + + if (reg & 1) + return -1; + + if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) + return -1; + + *val = (data >> ((reg & 3) << 3)) & 0xffff; + + return 0; +} + + +static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg, + u32 * val) +{ + u32 data = 0; + + if (reg & 3) + return -1; + + if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) + return -1; + + *val = data; + + return (0); +} + +static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val) +{ + u32 data = 0; + + if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) + return -1; + + data = (data & ~(0xff << ((reg & 3) << 3))) | (val << + ((reg & 3) << 3)); + + if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) + return -1; + + return 0; +} + + +static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val) +{ + u32 data = 0; + + if (reg & 1) + return -1; + + if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) + return -1; + + data = (data & ~(0xffff << ((reg & 3) << 3))) | (val << + ((reg & 3) << 3)); + + if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) + return -1; + + return 0; +} + +static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val) +{ + u32 data; + + if (reg & 3) { + return -1; + } + + data = val; + + if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) + return -1; + + return (0); +} + + +/* + * Initialize VR4131 PCIU + */ + +vr4131_pciu_init () +{ + /* PCI clock */ + *VR4131_PCICLKSELREG = 0x00000002; + + /* PCI memory and I/O space */ + *VR4131_PCIMMAW1REG = 0x100F9010; + *VR4131_PCIMMAW2REG = 0x140FD014; + *VR4131_PCIMIOAWREG = 0x160FD000; + + /* Target memory window */ + *VR4131_PCITAW1REG = 0x00081000; /* 64MB */ + *VR4131_PCITAW2REG = 0x00000000; + + *VR4131_MAILBAREG = 0UL; + *VR4131_PCIMBA1REG = 0UL; + + *VR4131_PCITRDYREG = 0x00008004; + + *VR4131_PCIENREG = 0x00000004; /* PCI enable */ + *VR4131_COMMANDREG = 0x02000007; +} + +/* + * Initialize Module + */ + +void init_vr4131_pci (struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0xff; + + vr4131_pciu_init (); /* Initialize VR4131 PCIU */ + + /* PCI memory space #1 */ + pci_set_region (hose->regions + 0, + 0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM); + + /* PCI memory space #2 */ + pci_set_region (hose->regions + 1, + 0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM); + + + /* PCI I/O space */ + pci_set_region (hose->regions + 2, + 0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO); + + /* System memory space */ + pci_set_region (hose->regions + 3, + 0x00000000, + 0x80000000, + 0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + hose->read_byte = vr4131_pci_read_config_byte; + hose->read_word = vr4131_pci_read_config_word; + hose->read_dword = vr4131_pci_read_config_dword; + hose->write_byte = vr4131_pci_write_config_byte; + hose->write_word = vr4131_pci_write_config_word; + hose->write_dword = vr4131_pci_write_config_dword; + + pci_register_hose (hose); + + hose->last_busno = pci_hose_scan (hose); + + return; +} diff --git a/board/total5200/Makefile b/board/total5200/Makefile new file mode 100644 index 0000000..232956a --- /dev/null +++ b/board/total5200/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o sdram.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/total5200/config.mk b/board/total5200/config.mk new file mode 100644 index 0000000..1a7a7cf --- /dev/null +++ b/board/total5200/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Total5200 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFE000000 boot low +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h new file mode 100644 index 0000000..5b0923e --- /dev/null +++ b/board/total5200/mt48lc16m16a2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h new file mode 100644 index 0000000..4b5ac80 --- /dev/null +++ b/board/total5200/mt48lc32m16a2-75.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Micron MT48LC32M16A2-75 is compatible to: + * - Infineon HYB39S512160AT-75 + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x514F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#else +#error CONFIG_MPC5200 is not defined +#endif diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c new file mode 100644 index 0000000..a1601f2 --- /dev/null +++ b/board/total5200/sdram.c @@ -0,0 +1,227 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include "sdram.h" + +#ifndef CFG_RAMBOOT +static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + if (sdram_conf->ddr) { + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000; + __asm__ volatile ("sync"); + } + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +#if defined(CONFIG_MPC5200) +long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2; + __asm__ volatile ("sync"); + + if (sdram_conf->ddr) { + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay; + __asm__ volatile ("sync"); + } + + /* find RAM size using SDRAM CS0 only */ + mpc5xxx_sdram_start(sdram_conf, 0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + mpc5xxx_sdram_start(sdram_conf, 1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + mpc5xxx_sdram_start(sdram_conf, 0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + mpc5xxx_sdram_start(sdram_conf, 0); + test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + mpc5xxx_sdram_start(sdram_conf, 1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (test1 > test2) { + mpc5xxx_sdram_start(sdram_conf, 0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize + dramsize2; +} + +#elif defined(CONFIG_MGT5100) + +long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup and enable SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel; + __asm__ volatile ("sync"); + + /* find RAM size */ + mpc5xxx_sdram_start(sdram_conf, 0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + mpc5xxx_sdram_start(sdram_conf, 1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + mpc5xxx_sdram_start(sdram_conf, 0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* set SDRAM end address according to size */ + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); + +#else /* CFG_RAMBOOT */ + + /* Retrieve amount of SDRAM available */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h new file mode 100644 index 0000000..bc21e1d --- /dev/null +++ b/board/total5200/sdram.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +typedef struct { + ulong ddr; + ulong mode; + ulong emode; + ulong control; + ulong config1; + ulong config2; +#if defined(CONFIG_MPC5200) + ulong tapdelay; +#endif +#if defined(CONFIG_MGT5100) + ulong addrsel; +#endif +} sdram_conf_t; + +long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf); diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c new file mode 100644 index 0000000..1a35187 --- /dev/null +++ b/board/total5200/total5200.c @@ -0,0 +1,310 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "sdram.h" + +#if CONFIG_TOTAL5200_REV==2 +#include "mt48lc32m16a2-75.h" +#else +#include "mt48lc16m16a2-75.h" +#endif + +long int initdram (int board_type) +{ + sdram_conf_t sdram_conf; + + sdram_conf.ddr = SDRAM_DDR; + sdram_conf.mode = SDRAM_MODE; + sdram_conf.emode = 0; + sdram_conf.control = SDRAM_CONTROL; + sdram_conf.config1 = SDRAM_CONFIG1; + sdram_conf.config2 = SDRAM_CONFIG2; +#if defined(CONFIG_MPC5200) + sdram_conf.tapdelay = 0; +#endif +#if defined(CONFIG_MGT5100) + sdram_conf.addrsel = SDRAM_ADDRSEL; +#endif + return mpc5xxx_sdram_init (&sdram_conf); +} + +int checkboard (void) +{ +#if defined(CONFIG_MPC5200) +#if CONFIG_TOTAL5200_REV==2 + puts ("Board: Total5200 Rev.2 "); +#else + puts ("Board: Total5200 "); +#endif +#elif defined(CONFIG_MGT5100) + puts ("Board: Total5100 "); +#endif + +/* + * Retrieve FPGA Revision. + */ +printf ("(FPGA %08X)\n", *(vu_long *) (CFG_FPGA_BASE + 0x400)); + +/* + * Take all peripherals in power-up mode. + */ +#if CONFIG_TOTAL5200_REV==2 + *(vu_char *) (CFG_CPLD_BASE + 0x46) = 0x70; +#else + *(vu_long *) (CFG_CPLD_BASE + 0x400) = 0x70; +#endif + + return 0; +} + +#if defined(CONFIG_MGT5100) +int board_early_init_r(void) +{ + /* + * Now, when we are in RAM, enable CS0 + * because CS_BOOT cannot be written. + */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ + + return 0; +} +#endif + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +/* IRDA_1 aka PSC6_3 (pin C13) */ +#define GPIO_IRDA_1 0x20000000UL + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + + /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1; + *(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1; +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { + *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1; + } else { + *(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1; + } +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#ifdef CONFIG_VIDEO_SED13806 +#include + +#define DISPLAY_WIDTH 640 +#define DISPLAY_HEIGHT 480 + +#ifdef CONFIG_VIDEO_SED13806_8BPP +#error CONFIG_VIDEO_SED13806_8BPP not supported. +#endif /* CONFIG_VIDEO_SED13806_8BPP */ + +#ifdef CONFIG_VIDEO_SED13806_16BPP +static const S1D_REGS init_regs [] = +{ + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x00}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ + {0x0008,0x00}, /* General IO Pins Control Register 0 */ + {0x0009,0x00}, /* General IO Pins Control Register 1 */ + {0x0010,0x02}, /* Memory Clock Configuration Register */ + {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x03}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x25}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ + {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x01}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x05}, /* LCD Display Mode Register */ + {0x0041,0x00}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x10}, /* TV Output Control Register */ + {0x0060,0x05}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x00}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01E4,0x00}, /* Look-Up Table Data Register */ + {0x01F0,0x00}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ + {0, 0} +}; +#endif /* CONFIG_VIDEO_SED13806_16BPP */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +/* Return text to be printed besides the logo. */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { +#ifdef CONFIG_MGT5100 + strcpy (info, " Total5100"); +#elif CONFIG_TOTAL5200_REV==1 + strcpy (info, " Total5200"); +#elif CONFIG_TOTAL5200_REV==2 + strcpy (info, " Total5200 Rev.2"); +#else +#error CONFIG_TOTAL5200_REV must be 1 or 2. +#endif + } else { + info [0] = '\0'; + } +} +#endif + +/* Returns SED13806 base address. First thing called in the driver. */ +unsigned int board_video_init (void) +{ + return CFG_LCD_BASE; +} + +/* Called after initializing the SED13806 and before clearing the screen. */ +void board_validate_screen (unsigned int base) +{ +} + +/* Return a pointer to the initialization sequence. */ +const S1D_REGS *board_get_regs (void) +{ + return init_regs; +} + +int board_get_width (void) +{ + return DISPLAY_WIDTH; +} + +int board_get_height (void) +{ + return DISPLAY_HEIGHT; +} + +#endif /* CONFIG_VIDEO_SED13806 */ diff --git a/board/total5200/u-boot.lds b/board/total5200/u-boot.lds new file mode 100644 index 0000000..3cc2968 --- /dev/null +++ b/board/total5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile new file mode 100644 index 0000000..c234332 --- /dev/null +++ b/board/tqm5200/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +#OBJS := $(BOARD).o flash.o +OBJS := $(BOARD).o cmd_stk52xx.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c new file mode 100755 index 0000000..8b9057f --- /dev/null +++ b/board/tqm5200/cmd_stk52xx.c @@ -0,0 +1,1221 @@ +/* + * (C) Copyright 2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * SKT52XX specific functions + */ +/*#define DEBUG*/ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +#define DEFAULT_VOL 45 +#define DEFAULT_FREQ 500 +#define DEFAULT_DURATION 200 +#define LEFT 1 +#define RIGHT 2 +#define LEFT_RIGHT 3 +#define BL_OFF 0 +#define BL_ON 1 + +#define SM501_GPIO_CTRL_LOW 0x00000008UL +#define SM501_GPIO_CTRL_HIGH 0x0000000CUL +#define SM501_POWER_MODE0_GATE 0x00000040UL +#define SM501_POWER_MODE1_GATE 0x00000048UL +#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL +#define SM501_GPIO_DATA_LOW 0x00010000UL +#define SM501_GPIO_DATA_HIGH 0x00010004UL +#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL +#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL +#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL + +static int i2s_squarewave(unsigned long duration, unsigned int freq, + unsigned int channel); +static int i2s_sawtooth(unsigned long duration, unsigned int freq, + unsigned int channel); +static void spi_init(void); +static int spi_transmit(unsigned char data); +static void pcm1772_write_reg(unsigned char addr, unsigned char data); +static void set_attenuation(unsigned char attenuation); + +#ifdef CONFIG_STK52XX +static void spi_init(void) +{ + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; + + /* PSC3 as SPI and GPIOs */ + gpio->port_config &= 0xFFFFF0FF; + gpio->port_config |= 0x00000800; + /* + * Its important to use the correct order when initializing the + * registers + */ + spi->ddr = 0x0F; /* set all SPI pins as output */ + spi->pdr = 0x08; /* set SS high */ + spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */ + spi->cr2 = 0x00; /* normal operation */ + spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */ +} + +static int spi_transmit(unsigned char data) +{ + int dummy; + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; + + spi->dr = data; + /* wait for SPI transmission completed */ + while(!(spi->sr & 0x80)) + { + if (spi->sr & 0x40) /* if write collision occured */ + { + /* do dummy read to clear status register */ + dummy = spi->dr; + printf ("SPI write collision\n"); + return -1; + } + } + return (spi->dr); +} + +static void pcm1772_write_reg(unsigned char addr, unsigned char data) +{ + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; + + spi->pdr = 0x00; /* Set SS low */ + spi_transmit(addr); + spi_transmit(data); + /* wait some time to meet MS# hold time of PCM1772 */ + udelay (1); + spi->pdr = 0x08; /* set SS high */ +} + +static void set_attenuation(unsigned char attenuation) +{ + pcm1772_write_reg(0x01, attenuation); /* left channel */ + debug ("PCM1772 attenuation left set to %d.\n", attenuation); + pcm1772_write_reg(0x02, attenuation); /* right channel */ + debug ("PCM1772 attenuation right set to %d.\n", attenuation); +} + +void amplifier_init(void) +{ + static int init_done = 0; + int i; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; + + /* Do this only once, because of the long time delay */ + if (!init_done) { + /* configure PCM1772 audio format as I2S */ + pcm1772_write_reg(0x03, 0x01); + /* enable audio amplifier */ + gpio->sint_gpioe |= 0x02; /* PSC3_5 as GPIO */ + gpio->sint_ode &= ~0x02; /* PSC3_5 is not open Drain */ + gpio->sint_dvo &= ~0x02; /* PSC3_5 is LOW */ + gpio->sint_ddr |= 0x02; /* PSC3_5 as output */ + /* + * wait some time to allow amplifier to recover from shutdown + * mode. + */ + for(i = 0; i < 350; i++) + udelay(1000); + /* + * The used amplifier (LM4867) has a so called "pop and click" + * elmination filter. The input signal of the amplifier must + * exceed a certain level once after power up to activate the + * generation of the output signal. This is achieved by + * sending a low frequent (nearly inaudible) sawtooth with a + * sufficient signal level. + */ + set_attenuation(50); + i2s_sawtooth (200, 5, LEFT_RIGHT); + init_done = 1; + } +} + +static void i2s_init(void) +{ + unsigned long i; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; + + gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */ + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + psc->sicr = 0x22E00000; /* 16 bit data; I2S */ + + *(vu_long *)(CFG_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK + * 5.617 MHz */ + *(vu_long *)(CFG_MBAR + 0x214) |= 0x00000040; /* CDM clock enable + * register */ + psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ + psc->ctur = 0x0F; /* 16 bit frame width */ + + for(i=0;i<128;i++) + { + psc->psc_buffer_32 = 0; /* clear tx fifo */ + } +} + +static int i2s_play_wave(unsigned long addr, unsigned long len) +{ + unsigned long i; + unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip + * wav header*/ + unsigned char swapped[4]; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; + + /* + * play wave file in memory; bytes/words are be swapped + */ + psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); + + for(i = 0;i < (len / 4); i++) { + swapped[3]=*wave_file++; + swapped[2]=*wave_file++; + swapped[1]=*wave_file++; + swapped[0]=*wave_file++; + psc->psc_buffer_32 = *((unsigned long*)swapped); + while (psc->tfnum > 400) { + if(ctrlc()) + return 0; + } + } + while (psc->tfnum > 0); /* wait for fifo empty */ + udelay (100); + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + return 0; +} + +static int i2s_sawtooth(unsigned long duration, unsigned int freq, + unsigned int channel) +{ + long i,j; + unsigned long data; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; + + psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); + + /* + * Generate sawtooth. Start with middle level up to highest level. Then + * go to lowest level and back to middle level. + */ + for(j = 0; j < ((duration * freq) / 1000); j++) { + for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4)))) { + data = (i & 0xFFFF); + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) { + data = (i & 0xFFFF); + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) { + data = (i & 0xFFFF); + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + } + while (psc->tfnum > 0); /* wait for fifo empty */ + udelay (100); + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + + return 0; +} + +static int i2s_squarewave(unsigned long duration, unsigned int freq, + unsigned int channel) +{ + long i,j; + unsigned long data; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; + + psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); + + /* + * Generate sqarewave. Start with high level, duty cycle 1:1. + */ + for(j = 0; j < ((duration * freq) / 1000); j++) { + for(i = 0; i < (44100/(freq*2)); i ++) { + data = 0x7FFF; + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + for(i = 0; i < (44100/(freq*2)); i ++) { + data = 0x8000; + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + } + while (psc->tfnum > 0); /* wait for fifo empty */ + udelay (100); + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + + return 0; +} + +static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long reg, val, duration; + char *tmp; + unsigned int freq, channel; + unsigned char volume; + int rcode = 1; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif + spi_init(); + i2s_init(); + amplifier_init(); + + if ((tmp = getenv ("volume")) != NULL) { + volume = simple_strtoul (tmp, NULL, 10); + } else { + volume = DEFAULT_VOL; + } + set_attenuation(volume); + + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp(argv[1],"saw",3) == 0) { + printf ("Play sawtooth\n"); + rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + printf ("Play squarewave\n"); + rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strncmp(argv[1],"saw",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + printf ("Play sawtooth\n"); + rcode = i2s_sawtooth (duration, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + printf ("Play squarewave\n"); + rcode = i2s_squarewave (duration, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 4: + if (strncmp(argv[1],"saw",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + printf ("Play sawtooth\n"); + rcode = i2s_sawtooth (duration, freq, + LEFT_RIGHT); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + printf ("Play squarewave\n"); + rcode = i2s_squarewave (duration, freq, + LEFT_RIGHT); + return rcode; + } else if (strcmp(argv[1],"pcm1772") == 0) { + reg = simple_strtoul(argv[2], NULL, 10); + val = simple_strtoul(argv[3], NULL, 10); + printf("Set PCM1772 %lu. %lu\n", reg, val); + pcm1772_write_reg((uchar)reg, (uchar)val); + return 0; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 5: + if (strncmp(argv[1],"saw",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + if (strncmp(argv[4],"l",1) == 0) + channel = LEFT; + else if (strncmp(argv[4],"r",1) == 0) + channel = RIGHT; + else + channel = LEFT_RIGHT; + printf ("Play squarewave\n"); + rcode = i2s_sawtooth (duration, freq, + channel); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + if (strncmp(argv[4],"l",1) == 0) + channel = LEFT; + else if (strncmp(argv[4],"r",1) == 0) + channel = RIGHT; + else + channel = LEFT_RIGHT; + printf ("Play squarewave\n"); + rcode = i2s_squarewave (duration, freq, + channel); + return rcode; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + printf ("Usage:\nsound cmd [arg1] [arg2] ...\n"); + return 1; +} + +static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long length, addr; + unsigned char volume; + int rcode = 1; + char *tmp; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif + spi_init(); + i2s_init(); + amplifier_init(); + + switch (argc) { + + case 3: + length = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[1], NULL, 16); + break; + + case 2: + if ((tmp = getenv ("filesize")) != NULL) { + length = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No filesize provided\n"); + return 1; + } + addr = simple_strtoul(argv[1], NULL, 16); + + case 1: + if ((tmp = getenv ("filesize")) != NULL) { + length = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No filesize provided\n"); + return 1; + } + if ((tmp = getenv ("loadaddr")) != NULL) { + addr = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No loadaddr provided\n"); + return 1; + } + break; + + default: + printf("Usage:\nwav usage); + return 1; + } + + if ((tmp = getenv ("volume")) != NULL) { + volume = simple_strtoul (tmp, NULL, 10); + } else { + volume = DEFAULT_VOL; + } + set_attenuation(volume); + + printf("Beep on "); + if (channel == LEFT) + printf ("left "); + else if (channel == RIGHT) + printf ("right "); + else + printf ("left and right "); + printf ("channel\n"); + + rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel); + + return rcode; +} + +void led_init(void) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + /* configure PSC3 for SPI and GPIO */ + gpio->port_config &= ~(0x00000F00); + gpio->port_config |= 0x00000800; + + gpio->simple_gpioe &= ~(0x00000F00); + gpio->simple_gpioe |= 0x00000F00; + + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000F00; + + /* configure timer 4-7 for simple GPIO output */ + gpt->gpt4.emsr |= 0x00000024; + gpt->gpt5.emsr |= 0x00000024; + gpt->gpt6.emsr |= 0x00000024; + gpt->gpt7.emsr |= 0x00000024; + + + /* enable SM501 GPIO control (in both power modes) */ + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + + /* configure SM501 gpio pins 24-27 as output */ + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24); + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24); + + /* configure SM501 gpio pins 48-51 as output */ + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16); +} + +/* + * return 1 if led number unknown + * return 0 else + */ +int do_led(char *argv[]) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + switch (simple_strtoul(argv[2], NULL, 10)) { + + case 0: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 8); + } else { + gpio->simple_dvo &= ~(1 << 8); + } + break; + + case 1: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 9); + } else { + gpio->simple_dvo &= ~(1 << 9); + } + break; + + case 2: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 10); + } else { + gpio->simple_dvo &= ~(1 << 10); + } + break; + + case 3: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 11); + } else { + gpio->simple_dvo &= ~(1 << 11); + } + break; + + case 4: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt4.emsr |= (1 << 4); + } else { + gpt->gpt4.emsr &= ~(1 << 4); + } + break; + + case 5: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt5.emsr |= (1 << 4); + } else { + gpt->gpt5.emsr &= ~(1 << 4); + } + break; + + case 6: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt6.emsr |= (1 << 4); + } else { + gpt->gpt6.emsr &= ~(1 << 4); + } + break; + + case 7: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt7.emsr |= (1 << 4); + } else { + gpt->gpt7.emsr &= ~(1 << 4); + } + break; + + case 24: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 24); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 24); + } + break; + + case 25: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 25); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 25); + } + break; + + case 26: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 26); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 26); + } + break; + + case 27: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 27); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 27); + } + break; + + case 48: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 16); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 16); + } + break; + + case 49: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 17); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 17); + } + break; + + case 50: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 18); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 18); + } + break; + + case 51: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 19); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 19); + } + break; + + default: + printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]); + return 1; + } + + return 0; +} + +/* + * return 1 on CAN initialization failure + * return 0 if no failure + */ +int can_init(void) +{ + static int init_done = 0; + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + + /* GPIO configuration of the CAN pins is done in TQM5200.h */ + + if (!init_done) { + /* init CAN 1 */ + can1->canctl1 |= 0x80; /* CAN enable */ + udelay(100); + + i = 0; + can1->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can1->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can1->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can1->canctl1 & 0x01)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can1->canctl1 = 0x80; + can1->canctl1 |= 0x40; + can1->canbtr0 = 0x0F; + can1->canbtr1 = 0x7F; + can1->canidac &= ~(0x30); + can1->canidar1 = 0x00; + can1->canidar3 = 0x00; + can1->canidar5 = 0x00; + can1->canidar7 = 0x00; + can1->canidmr0 = 0xFF; + can1->canidmr1 = 0xFF; + can1->canidmr2 = 0xFF; + can1->canidmr3 = 0xFF; + can1->canidmr4 = 0xFF; + can1->canidmr5 = 0xFF; + can1->canidmr6 = 0xFF; + can1->canidmr7 = 0xFF; + + i = 0; + can1->canctl0 &= ~(0x01); /* leave init mode */ + can1->canctl0 &= ~(0x02); + /* wait until init and sleep mode left */ + while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + + /* init CAN 2 */ + can2->canctl1 |= 0x80; /* CAN enable */ + udelay(100); + + i = 0; + can2->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can2->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can2->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can2->canctl1 & 0x01)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can2->canctl1 = 0x80; + can2->canctl1 |= 0x40; + can2->canbtr0 = 0x0F; + can2->canbtr1 = 0x7F; + can2->canidac &= ~(0x30); + can2->canidar1 = 0x00; + can2->canidar3 = 0x00; + can2->canidar5 = 0x00; + can2->canidar7 = 0x00; + can2->canidmr0 = 0xFF; + can2->canidmr1 = 0xFF; + can2->canidmr2 = 0xFF; + can2->canidmr3 = 0xFF; + can2->canidmr4 = 0xFF; + can2->canidmr5 = 0xFF; + can2->canidmr6 = 0xFF; + can2->canidmr7 = 0xFF; + can2->canctl0 &= ~(0x01); /* leave init mode */ + can2->canctl0 &= ~(0x02); + + i = 0; + /* wait until init mode left */ + while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + init_done = 1; + } + return 0; +} + +/* + * return 1 on CAN failure + * return 0 if no failure + */ +int do_can(char *argv[]) +{ + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + + /* send a message on CAN1 */ + can1->cantbsel = 0x01; + can1->cantxfg.idr[0] = 0x55; + can1->cantxfg.idr[1] = 0x00; + can1->cantxfg.idr[1] &= ~0x8; + can1->cantxfg.idr[1] &= ~0x10; + can1->cantxfg.dsr[0] = 0xCC; + can1->cantxfg.dlr = 1; + can1->cantxfg.tbpr = 0; + can1->cantflg = 0x01; + + i = 0; + while ((can1->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN1 send timeout, " + "can not send message!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + udelay(1000); + + i = 0; + while (!(can2->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN2 receive timeout, " + "no message received!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + + if (can2->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN2 receive error, " + "data mismatch!\n", + __FUNCTION__); + return 1; + } + + /* send a message on CAN2 */ + can2->cantbsel = 0x01; + can2->cantxfg.idr[0] = 0x55; + can2->cantxfg.idr[1] = 0x00; + can2->cantxfg.idr[1] &= ~0x8; + can2->cantxfg.idr[1] &= ~0x10; + can2->cantxfg.dsr[0] = 0xCC; + can2->cantxfg.dlr = 1; + can2->cantxfg.tbpr = 0; + can2->cantflg = 0x01; + + i = 0; + while ((can2->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN2 send error, " + "can not send message!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + udelay(1000); + + i = 0; + while (!(can1->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN1 receive timeout, " + "no message received!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + + if (can1->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN1 receive error 0x%02x\n", + __FUNCTION__, (can1->canrxfg.dsr[0])); + return 1; + } + + return 0; +} + +/* + * return 1 if rs232 port unknown + * return 2 on txd/rxd failure (only rs232 2) + * return 3 on rts/cts failure + * return 0 if no failure + */ +int do_rs232(char *argv[]) +{ + int error_status = 0; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; + + switch (simple_strtoul(argv[2], NULL, 10)) { + + case 1: + /* check RTS <-> CTS loop */ + /* set rts to 0 */ + psc1->op1 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 0) { + error_status = 3; + printf ("%s: failure at rs232_1, cts status is %d " + "(should be 0)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + /* set rts to 1 */ + psc1->op0 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 1) { + error_status = 3; + printf ("%s: failure at rs232_1, cts status is %d " + "(should be 1)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + break; + + case 2: + /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000500; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000200) { + error_status = 2; + printf ("%s: failure at rs232_2, rxd status is %d " + "(should be 1)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000000) { + error_status = 2; + printf ("%s: failure at rs232_2, rxd status is %d " + "(should be 0)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000800) { + error_status = 3; + printf ("%s: failure at rs232_2, cts status is %d " + "(should be 1)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000000) { + error_status = 3; + printf ("%s: failure at rs232_2, cts status is %d " + "(should be 0)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */ + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000F00; + break; + + default: + printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); + error_status = 1; + break; + } + + return error_status; +} + +static void sm501_backlight (unsigned int state) +{ + if (state == BL_ON) { + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= + (1 << 26) | (1 << 27); + } else if (state == BL_OFF) + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= + ~((1 << 26) | (1 << 27)); +} + +int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif + led_init(); + can_init(); + + switch (argc) { + + case 0: + case 1: + break; + + case 2: + if (strncmp (argv[1], "can", 3) == 0) { + rcode = do_can (argv); + if (rcode == 0) + printf ("OK\n"); + else + printf ("Error\n"); + return rcode; + } + break; + + case 3: + if (strncmp (argv[1], "rs232", 3) == 0) { + rcode = do_rs232 (argv); + if (rcode == 0) + printf ("OK\n"); + else + printf ("Error\n"); + return rcode; + } else if (strncmp (argv[1], "backlight", 4) == 0) { + if (strncmp (argv[2], "on", 2) == 0) { + sm501_backlight (BL_ON); + return 0; + } + else if (strncmp (argv[2], "off", 3) == 0) { + sm501_backlight (BL_OFF); + return 0; + } + } + break; + + case 4: + if (strcmp (argv[1], "led") == 0) { + return (do_led (argv)); + } + break; + + default: + break; + } + + printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n"); + return 1; +} + + +U_BOOT_CMD( + sound , 5, 1, cmd_sound, + "sound - Sound sub-system\n", + "saw [duration] [freq] [channel]\n" + " - generate sawtooth for 'duration' ms with frequency 'freq'\n" + " on left \"l\" or right \"r\" channel\n" + "sound square [duration] [freq] [channel]\n" + " - generate squarewave for 'duration' ms with frequency 'freq'\n" + " on left \"l\" or right \"r\" channel\n" + "pcm1772 reg val\n" +); + +U_BOOT_CMD( + wav , 3, 1, cmd_wav, + "wav - play wav file\n", + "[addr] [bytes]\n" + " - play wav file at address 'addr' with length 'bytes'\n" +); + +U_BOOT_CMD( + beep , 2, 1, cmd_beep, + "beep - play short beep\n", + "[channel]\n" + " - play short beep on \"l\"eft or \"r\"ight channel\n" +); + +U_BOOT_CMD( + fkt , 4, 1, cmd_fkt, + "fkt - Function test routines\n", + "led number on/off\n" + " - 'number's like printed on SKT52XX board\n" + "fkt can\n" + " - loopback plug for X83 required\n" + "fkt rs232 number\n" + " - loopback plug(s) for X2 required\n" + "fkt backlight on/off\n" + " - switch backlight on or off\n" +); +#endif /* CONFIG_STK52XX */ +#endif /* CFG_CMD_BSP */ diff --git a/board/tqm5200/config.mk b/board/tqm5200/config.mk new file mode 100644 index 0000000..585a99a --- /dev/null +++ b/board/tqm5200/config.mk @@ -0,0 +1,41 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM5200 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFC000000 boot low (standard configuration with room for max 64 MByte +# Flash ROM) +# 0x00100000 boot from RAM (for testing only) +# + +ifndef TEXT_BASE +## Standard: boot low +TEXT_BASE = 0xFC000000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/tqm5200/flash.c b/board/tqm5200/flash.c new file mode 100644 index 0000000..af4d78a --- /dev/null +++ b/board/tqm5200/flash.c @@ -0,0 +1,497 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * CPU to flash interface is 32-bit, so make declaration accordingly + */ +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + extern void flash_preinit(void); + ulong flashbase = CFG_FLASH_BASE; + + flash_preinit(); + + /* Init: no FLASHes known */ + memset(&flash_info[0], 0, sizeof(flash_info_t)); + + flash_info[0].size = + flash_get_size((FPW *)flashbase, &flash_info[0]); + + size = flash_info[0].size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMLV128U: + printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + int i; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(100); + switch (addr[0] & 0xff) { + + case (uchar)AMD_MANUFACT: + debug ("Manufacturer: AMD (Spansion)\n"); + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + debug ("Manufacturer: Intel (not supported yet)\n"); + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { + + case (FPW)AMD_ID_LV160B: + debug ("Chip: AM29LV160MB\n"); + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + /* + * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all + * the other ones are 64 kB + */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for( i = 4; i < info->sector_count; i++ ) + info->start[i] = + base + (i * 2 * (64 << 10)) - 0x00060000; + break; /* => 4 MB */ + + case AMD_ID_MIRROR: + debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", + addr[14], addr[15]); + + switch(addr[14]) { + case AMD_ID_LV128U_2: + if (addr[15] != AMD_ID_LV128U_3) { + debug ("Chip: AM29LVxxxM -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + } else { + debug ("Chip: AM29LV128M\n"); + info->flash_id += FLASH_AMLV128U; + info->sector_count = 256; + info->size = 0x02000000; + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x20000; + } + } + break; /* => 32 MB */ + default: + debug ("Chip: *** unknown ***\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + } + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + /* + * Get lower word aligned address. Assumes 32 bit flash bus width. + */ + wp = (addr & ~3); + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word_amd(info, (FPW *)wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + return (1); + } + } + return (0); +} diff --git a/board/tqm5200/mt48lc16m16a2-75.h b/board/tqm5200/mt48lc16m16a2-75.h new file mode 100644 index 0000000..3f1e169 --- /dev/null +++ b/board/tqm5200/mt48lc16m16a2-75.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ +/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ +#define SDRAM_CONFIG2 0x8AD70000 +/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c new file mode 100644 index 0000000..6aad920 --- /dev/null +++ b/board/tqm5200/tqm5200.c @@ -0,0 +1,673 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_VIDEO_SM501 +#include +#endif + +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m16a2-75.h" +#endif + +#ifdef CONFIG_PS2MULT +void ps2mult_early_init(void); +#endif + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +#if defined(CONFIG_MPC5200) +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ + + /* find RAM size using SDRAM CS1 only */ + sdram_start(0); + test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + +/* return dramsize + dramsize2; */ + return dramsize; +} + +#elif defined(CONFIG_MGT5100) + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup and enable SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; + __asm__ volatile ("sync"); + + /* find RAM size */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* set SDRAM end address according to size */ + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); + +#else /* CFG_RAMBOOT */ + + /* Retrieve amount of SDRAM available */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif + +int checkboard (void) +{ +#if defined (CONFIG_AEVFIFO) + puts ("Board: AEVFIFO\n"); + return 0; +#endif +#if defined (CONFIG_TQM5200_AA) + puts ("Board: TQM5200-AA (TQ-Components GmbH)\n"); +#elif defined (CONFIG_TQM5200_AB) + puts ("Board: TQM5200-AB (TQ-Components GmbH)\n"); +#elif defined (CONFIG_TQM5200_AC) + puts ("Board: TQM5200-AC (TQ-Components GmbH)\n"); +#elif defined (CONFIG_TQM5200) + puts ("Board: TQM5200 (TQ-Components GmbH)\n"); +#endif +#if defined (CONFIG_STK52XX) + puts (" on a STK52XX baseboard\n"); +#endif + + return 0; +} + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ +#if defined(CONFIG_MGT5100) + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ +#endif + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#if defined (CONFIG_MINIFAP) +#define SM501_POWER_MODE0_GATE 0x00000040UL +#define SM501_POWER_MODE1_GATE 0x00000048UL +#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL +#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL +#define SM501_GPIO_DATA_HIGH 0x00010004UL +#define SM501_GPIO_51 0x00080000UL +#else +#define GPIO_PSC1_4 0x01000000UL +#endif + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + +#if defined (CONFIG_MINIFAP) + /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */ + + /* enable GPIO control (in both power modes) */ + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + /* configure GPIO51 as output */ + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= + SM501_GPIO_51; +#else + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; +#endif +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + +#if defined (CONFIG_MINIFAP) + if (idereset) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~SM501_GPIO_51; + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + SM501_GPIO_51; + } +#else + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + } +#endif +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#ifdef CONFIG_POST +/* + * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 + * is left open, no keypress is detected. + */ +int post_hotkeys_pressed(void) +{ + struct mpc5xxx_gpio *gpio; + + gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; + + /* + * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in + * CODEC or UART mode. Consumer IrDA should still be possible. + */ + gpio->port_config &= ~(0x07000000); + gpio->port_config |= 0x03000000; + + /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ + gpio->simple_gpioe |= 0x20000000; + + /* Configure GPIO_IRDA_1 as input */ + gpio->simple_ddr &= ~(0x20000000); + + return ((gpio->simple_ival & 0x20000000) ? 0 : 1); +} +#endif + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + +void post_word_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + *save_addr = a; +} + +ulong post_word_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + return *save_addr; +} +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ + +#ifdef CONFIG_PS2MULT +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ + ps2mult_early_init(); + return (0); +} +#endif +#endif /* CONFIG_PS2MULT */ + +#if defined(CONFIG_CS_AUTOCONF) +int last_stage_init (void) +{ + /* + * auto scan for really existing devices and re-set chip select + * configuration. + */ + u16 save, tmp; + int restore; + + /* + * Check for SRAM and SRAM size + */ + + /* save original SRAM content */ + save = *(volatile u16 *)CFG_CS2_START; + restore = 1; + + /* write test pattern to SRAM */ + *(volatile u16 *)CFG_CS2_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in SRAM detection\n"); + + if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { + /* no SRAM at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); + *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { + /* make sure that we access a mirrored address */ + *(volatile u16 *)CFG_CS2_START = 0x1111; + __asm__ volatile ("sync"); + if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { + /* SRAM size = 512 kByte */ + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, + 0x80000); + __asm__ volatile ("sync"); + puts ("SRAM: 512 kB\n"); + } + else + puts ("!! possible error in SRAM detection\n"); + } else { + puts ("SRAM: 1 MB\n"); + } + /* restore origianl SRAM content */ + if (restore) { + *(volatile u16 *)CFG_CS2_START = save; + __asm__ volatile ("sync"); + } + + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); + *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else { + puts ("VGA: SMI501 (Voyager) with 8 MB\n"); + } + /* restore origianl FB content */ + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + + return 0; +} +#endif /* CONFIG_CS_AUTOCONF */ + +#ifdef CONFIG_VIDEO_SM501 + +#define DISPLAY_WIDTH 640 +#define DISPLAY_HEIGHT 480 + +#ifdef CONFIG_VIDEO_SM501_8BPP +#error CONFIG_VIDEO_SM501_8BPP not supported. +#endif /* CONFIG_VIDEO_SM501_8BPP */ + +#ifdef CONFIG_VIDEO_SM501_16BPP +#error CONFIG_VIDEO_SM501_16BPP not supported. +#endif /* CONFIG_VIDEO_SM501_16BPP */ +#ifdef CONFIG_VIDEO_SM501_32BPP +static const SMI_REGS init_regs [] = +{ +#if 0 /* CRT only */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x10090a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x10090a01}, + {0x00054, 0x0}, + {0x80200, 0x00010000}, + {0x80204, 0x0}, + {0x80208, 0x0A000A00}, + {0x8020C, 0x02fa027f}, + {0x80210, 0x004a028b}, + {0x80214, 0x020c01df}, + {0x80218, 0x000201e9}, + {0x80200, 0x00013306}, +#else /* panel + CRT */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x091a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x0f013106}, + {0x80004, 0xc428bb17}, + {0x8000C, 0x00000000}, + {0x80010, 0x0a000a00}, + {0x80014, 0x02800000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00280}, + {0x80024, 0x02fa027f}, + {0x80028, 0x004a028b}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201e9}, + {0x80200, 0x00010000}, +#endif + {0, 0} +}; +#endif /* CONFIG_VIDEO_SM501_32BPP */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { +#if defined (CONFIG_TQM5200_AA) + strcpy (info, " Board: TQM5200-AA (TQ-Components GmbH)"); +#elif defined (CONFIG_TQM5200_AB) + strcpy (info, " Board: TQM5200-AB (TQ-Components GmbH)"); +#elif defined (CONFIG_TQM5200_AC) + strcpy (info, " Board: TQM5200-AC (TQ-Components GmbH)"); +#elif defined (CONFIG_TQM5200) + strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); +#else +#error No supported board selected +#endif +#if defined (CONFIG_STK52XX) + } else if (line_number == 2) { + strcpy (info, " on a STK52XX baseboard"); +#endif + } + else { + info [0] = '\0'; + } +} +#endif + +/* + * Returns SM501 register base address. First thing called in the + * driver. Checks if SM501 is physically present. + */ +unsigned int board_video_init (void) +{ + u16 save, tmp; + int restore, ret; + + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller found */ + restore = 0; + ret = 0; + } else { + ret = SM501_MMIO_BASE; + } + + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + return ret; +} + +/* + * Returns SM501 framebuffer address + */ +unsigned int board_video_get_fb (void) +{ + return SM501_FB_BASE; +} + +/* + * Called after initializing the SM501 and before clearing the screen. + */ +void board_validate_screen (unsigned int base) +{ +} + +/* + * Return a pointer to the initialization sequence. + */ +const SMI_REGS *board_get_regs (void) +{ + return init_regs; +} + +int board_get_width (void) +{ + return DISPLAY_WIDTH; +} + +int board_get_height (void) +{ + return DISPLAY_HEIGHT; +} + +#endif /* CONFIG_VIDEO_SM501 */ diff --git a/board/tqm5200/u-boot.lds b/board/tqm5200/u-boot.lds new file mode 100644 index 0000000..3cc2968 --- /dev/null +++ b/board/tqm5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm8260/Makefile b/board/tqm8260/Makefile new file mode 100644 index 0000000..c10b9fe --- /dev/null +++ b/board/tqm8260/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/tqm8260/config.mk b/board/tqm8260/config.mk new file mode 100644 index 0000000..1fe9952 --- /dev/null +++ b/board/tqm8260/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8260 boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# +TEXT_BASE = 0x40000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/tqm8260/flash.c b/board/tqm8260/flash.c new file mode 100644 index 0000000..056fe81 --- /dev/null +++ b/board/tqm8260/flash.c @@ -0,0 +1,488 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AMD devices on the TQM8260 board + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define V_ULONG(a) (*(volatile unsigned long *)( a )) +#define V_BYTE(a) (*(volatile unsigned char *)( a )) + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +/*----------------------------------------------------------------------- + */ +void flash_reset (void) +{ + if (flash_info[0].flash_id != FLASH_UNKNOWN) { + V_ULONG (flash_info[0].start[0]) = 0x00F000F0; + V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0; + } +} + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size (ulong baseaddr, flash_info_t * info) +{ + short i; + unsigned long flashtest_h, flashtest_l; + + /* Write auto select command sequence and test FLASH answer */ + V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA; + V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055; + V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090; + V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA; + V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055; + V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090; + + flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */ + flashtest_l = V_ULONG (baseaddr + 4); + + switch ((int) flashtest_h) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + flashtest_h = V_ULONG (baseaddr + 8); /* device ID */ + flashtest_l = V_ULONG (baseaddr + 12); + if (flashtest_h != flashtest_l) { + info->flash_id = FLASH_UNKNOWN; + } else { + switch (flashtest_h) { + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00400000; + break; /* 4 * 1 MB = 4 MB */ + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00400000; + break; /* 4 * 1 MB = 4 MB */ + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00800000; + break; /* 4 * 2 MB = 8 MB */ + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00800000; + break; /* 4 * 2 MB = 8 MB */ + case AMD_ID_DL322T: + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_DL322B: + info->flash_id += FLASH_AMDL322B; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_DL323T: + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_DL323B: + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_LV640U: + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x02000000; + break; /* 4 * 8 MB = 32 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* no or unknown flash */ + } + } + + if (flashtest_h == AMD_ID_LV640U) { + + /* set up sector start adress table (uniform sector type) */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = baseaddr + (i * 0x00040000); + + } else if (info->flash_id & FLASH_BTYPE) { + + /* set up sector start adress table (bottom sector type) */ + info->start[0] = baseaddr + 0x00000000; + info->start[1] = baseaddr + 0x00010000; + info->start[2] = baseaddr + 0x00018000; + info->start[3] = baseaddr + 0x00020000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; + } + + } else { + + /* set up sector start adress table (top sector type) */ + i = info->sector_count - 1; + info->start[i--] = baseaddr + info->size - 0x00010000; + info->start[i--] = baseaddr + info->size - 0x00018000; + info->start[i--] = baseaddr + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = baseaddr + i * 0x00040000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + if ((V_ULONG (info->start[i] + 16) & 0x00010001) || + (V_ULONG (info->start[i] + 20) & 0x00010001)) { + info->protect[i] = 1; /* D0 = 1 if protected */ + } else { + info->protect[i] = 0; + } + } + + flash_reset (); + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here (only one bank) */ + + size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]); + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + /* + * protect monitor and environment sectors + */ + +#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM800T: + printf ("29LV800T (8 M, top sector)\n"); + break; + case FLASH_AM800B: + printf ("29LV800T (8 M, bottom sector)\n"); + break; + case FLASH_AM160T: + printf ("29LV160T (16 M, top sector)\n"); + break; + case FLASH_AM160B: + printf ("29LV160B (16 M, bottom sector)\n"); + break; + case FLASH_AMDL322T: + printf ("29DL322T (32 M, top sector)\n"); + break; + case FLASH_AMDL322B: + printf ("29DL322B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL323T: + printf ("29DL323T (32 M, top sector)\n"); + break; + case FLASH_AMDL323B: + printf ("29DL323B (32 M, bottom sector)\n"); + break; + case FLASH_AM640U: + printf ("29LV640D (64 M, uniform sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080; + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; + udelay (1000); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + V_ULONG (info->start[sect]) = 0x00300030; + V_ULONG (info->start[sect] + 4) = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || + (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) + { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + flash_reset (); + + printf (" done\n"); + return 0; +} + +static int write_dword (flash_info_t *, ulong, unsigned char *); + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong dp; + static unsigned char bb[8]; + int i, l, rc, cc = cnt; + + dp = (addr & ~7); /* get lower dword aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - dp) != 0) { + for (i = 0; i < 8; i++) + bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++; + if ((rc = write_dword (info, dp, bb)) != 0) { + return (rc); + } + dp += 8; + cc -= 8 - l; + } + + /* + * handle word aligned part + */ + while (cc >= 8) { + if ((rc = write_dword (info, dp, src)) != 0) { + return (rc); + } + dp += 8; + src += 8; + cc -= 8; + } + + if (cc <= 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + for (i = 0; i < 8; i++) { + bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i); + } + return (write_dword (info, dp, bb)); +} + +/*----------------------------------------------------------------------- + * Write a dword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) +{ + ulong start, cl, ch; + int flag, i; + + for (ch = 0, i = 0; i < 4; i++) + ch = (ch << 8) + *pdata++; /* high word */ + for (cl = 0, i = 0; i < 4; i++) + cl = (cl << 8) + *pdata++; /* low word */ + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *) dest) & ch) != ch + || (*((vu_long *) (dest + 4)) & cl) != cl) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0; + V_ULONG (dest) = ch; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0; + V_ULONG (dest + 4) = cl; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || + ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/tqm8260/tqm8260.c b/board/tqm8260/tqm8260.c new file mode 100644 index 0000000..029863b --- /dev/null +++ b/board/tqm8260/tqm8260.c @@ -0,0 +1,368 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ + /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ + /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ + /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ + /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ + /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (!i || strncmp (str, "TQM82", 5)) { + puts ("### No HW ID - assuming TQM8260\n"); + return (0); + } + + puts (str); + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; + orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + long size8, size9; +#endif + long psize, lsize; + + psize = 16 * 1024 * 1024; + lsize = 0; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#if 0 /* Just for debugging */ +#define prt_br_or(brX,orX) do { \ + ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ + ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ + printf ("\n" \ + #brX " 0x%08x " #orX " 0x%08x " \ + "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ + memctl->memc_ ## brX, memctl->memc_ ## orX, \ + start, start+sizem, (sizem+1)>>20); \ + } while (0) + prt_br_or (br0, or0); + prt_br_or (br1, or1); + prt_br_or (br2, or2); + prt_br_or (br3, or3); +#endif + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL - %ld MB, ", psize >> 20); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL - %ld MB, ", psize >> 20); + } + + /* Local SDRAM setup: + */ +#ifdef CFG_INIT_LOCAL_SDRAM + memctl->memc_lsrt = CFG_LSRT; + size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, + (uchar *) SDRAM_BASE2_PRELIM); + + if (size8 < size9) { + lsize = size9; + printf ("Local:9COL - %ld MB) using ", lsize >> 20); + } else { + lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + printf ("Local:8COL - %ld MB) using ", lsize >> 20); + } + +#if 0 + /* Set up BR2 so that the local SDRAM goes + * right after the 60x SDRAM + */ + memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | + (CFG_SDRAM_BASE + psize); +#endif +#endif /* CFG_INIT_LOCAL_SDRAM */ +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/tqm8260/u-boot.lds b/board/tqm8260/u-boot.lds new file mode 100644 index 0000000..05f29c6 --- /dev/null +++ b/board/tqm8260/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm834x/Makefile b/board/tqm834x/Makefile new file mode 100644 index 0000000..3ecc7d0 --- /dev/null +++ b/board/tqm834x/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o pci.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/tqm834x/config.mk b/board/tqm834x/config.mk new file mode 100644 index 0000000..f172c4e --- /dev/null +++ b/board/tqm834x/config.mk @@ -0,0 +1,23 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x80000000 diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c new file mode 100644 index 0000000..5a23e6c --- /dev/null +++ b/board/tqm834x/pci.c @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#ifdef CONFIG_PCI + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_tqm834x_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } + }, + {} +}; +#endif + +static struct pci_controller pci1_hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_tqm834x_config_table, +#endif +}; + + +/************************************************************************** + * pci_init_board() + * + * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since + * per TQM834x design physical connections to external devices (PCI sockets) + * are routed only to the PCI1 we do not account for the second one - this code + * supports PCI1 module only. Should support for the PCI2 be required in the + * future it needs a separate pci_controller structure (above) and handling - + * please refer to other boards' implementation for dual PCI host controllers, + * for example board/Marvell/db64360/pci.c, pci_init_board() + * + */ +void +pci_init_board(void) +{ + volatile immap_t * immr; + volatile clk8349_t * clk; + volatile law8349_t * pci_law; + volatile pot8349_t * pci_pot; + volatile pcictrl8349_t * pci_ctrl; + volatile pciconf8349_t * pci_conf; + u16 reg16; + u32 reg32; + struct pci_controller * hose; + + immr = (immap_t *)CFG_IMMRBAR; + clk = (clk8349_t *)&immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + + hose = &pci1_hose; + + /* + * Configure PCI controller and PCI_CLK_OUTPUT + */ + + /* + * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one + * line actually used for clocking all external PCI devices in TQM83xx. + * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for + * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 + * are known to hang the board; this issue is under investigation + * (13 oct 05) + */ + reg32 = OCCR_PCICOE1; +#if 0 + /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ + reg32 = 0xff000000; +#endif + if (clk->spmr & SPMR_CKID) { + /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR + * fields accordingly */ + reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); + + reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ + | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ + | OCCR_PCICD6 | OCCR_PCICD7); + } + + clk->occr = reg32; + udelay(2000); + + /* + * Release PCI RST Output signal + */ + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + udelay(2000); + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI1 mem space */ + pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); + + /* PCI1 IO space */ + pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 2, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + CONFIG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 3; + + pci_setup_indirect(hose, + (CFG_IMMRBAR+0x8300), + (CFG_IMMRBAR+0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, + ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, + reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, + 0xffff); + pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, + 0x80); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCI */ diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c new file mode 100644 index 0000000..dada673 --- /dev/null +++ b/board/tqm834x/tqm834x.c @@ -0,0 +1,408 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IOSYNC asm("eieio") +#define ISYNC asm("isync") +#define SYNC asm("sync") +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define DDR_MAX_SIZE_PER_CS 0x20000000 + +#if defined(DDR_CASLAT_20) +#define TIMING_CASLAT TIMING_CFG1_CASLAT_20 +#define MODE_CASLAT DDR_MODE_CASLAT_20 +#else +#define TIMING_CASLAT TIMING_CFG1_CASLAT_25 +#define MODE_CASLAT DDR_MODE_CASLAT_25 +#endif + +#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \ + CSCONFIG_COL_BIT_9) + +/* Global variable used to store detected number of banks */ +int tqm834x_num_flash_banks; + +/* External definitions */ +ulong flash_get_size (ulong base, int banknum); +extern flash_info_t flash_info[]; +extern long spd_sdram (void); + +/* Local functions */ +static int detect_num_flash_banks(void); +static long int get_ddr_bank_size(short cs, volatile long *base); +static void set_cs_bounds(short cs, long base, long size); +static void set_cs_config(short cs, long config); +static void set_ddr_config(void); + +/* Local variable */ +static volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + +/************************************************************************** + * Board initialzation after relocation to RAM. Used to detect the number + * of Flash banks on TQM834x. + */ +int board_early_init_r (void) { + /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */ + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return 0; + + /* detect the number of Flash banks */ + return detect_num_flash_banks(); +} + +/************************************************************************** + * DRAM initalization and size detection + */ +long int initdram (int board_type) +{ + long bank_size; + long size; + int cs; + + /* during size detection, set up the max DDRLAW size */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE; + im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); + + /* set CS bounds to maximum size */ + for(cs = 0; cs < 4; ++cs) { + set_cs_bounds(cs, + CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), + DDR_MAX_SIZE_PER_CS); + + set_cs_config(cs, INITIAL_CS_CONFIG); + } + + /* configure ddr controller */ + set_ddr_config(); + + udelay(200); + + /* enable DDR controller */ + im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | + SDRAM_CFG_SREN | + SDRAM_CFG_SDRAM_TYPE_DDR); + SYNC; + + /* size detection */ + debug("\n"); + size = 0; + for(cs = 0; cs < 4; ++cs) { + debug("\nDetecting Bank%d\n", cs); + + bank_size = get_ddr_bank_size(cs, + (volatile long*)(CFG_DDR_BASE + size)); + size += bank_size; + + debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20); + + /* exit if less than one bank */ + if(size < DDR_MAX_SIZE_PER_CS) break; + } + + return size; +} + +/************************************************************************** + * checkboard() + */ +int checkboard (void) +{ + puts("Board: TQM834x\n"); + +#ifdef CONFIG_PCI + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t * immr; + u32 w, f; + + immr = (immap_t *)CFG_IMMRBAR; + if (!(immr->reset.rcwh & RCWH_PCIHOST)) { + printf("PCI: NOT in host mode..?!\n"); + return 0; + } + + /* get bus width */ + w = 32; + if (immr->reset.rcwh & RCWH_PCI64) + w = 64; + + /* get clock */ + f = gd->pci_clk; + + printf("PCI1: %d bit, %d MHz\n", w, f / 1000000); +#else + printf("PCI: disabled\n"); +#endif + return 0; +} + + +/************************************************************************** + * + * Local functions + * + *************************************************************************/ + +/************************************************************************** + * Detect the number of flash banks (1 or 2). Store it in + * a global variable tqm834x_num_flash_banks. + * Bank detection code based on the Monitor code. + */ +static int detect_num_flash_banks(void) +{ + typedef unsigned long FLASH_PORT_WIDTH; + typedef volatile unsigned long FLASH_PORT_WIDTHV; + FPWV *bank1_base; + FPWV *bank2_base; + FPW bank1_read; + FPW bank2_read; + ulong bank1_size; + ulong bank2_size; + ulong total_size; + + tqm834x_num_flash_banks = 2; /* assume two banks */ + + /* Get bank 1 and 2 information */ + bank1_size = flash_get_size(CFG_FLASH_BASE, 0); + debug("Bank1 size: %lu\n", bank1_size); + bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1); + debug("Bank2 size: %lu\n", bank2_size); + total_size = bank1_size + bank2_size; + + if (bank2_size > 0) { + /* Seems like we've got bank 2, but maybe it's mirrored 1 */ + + /* Set the base addresses */ + bank1_base = (FPWV *) (CFG_FLASH_BASE); + bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size); + + /* Put bank 2 into CFI command mode and read */ + bank2_base[0x55] = 0x00980098; + IOSYNC; + ISYNC; + bank2_read = bank2_base[0x10]; + + /* Read from bank 1 (it's in read mode) */ + bank1_read = bank1_base[0x10]; + + /* Reset Flash */ + bank1_base[0] = 0x00F000F0; + bank2_base[0] = 0x00F000F0; + + if (bank2_read == bank1_read) { + /* + * Looks like just one bank, but not sure yet. Let's + * read from bank 2 in autosoelect mode. + */ + bank2_base[0x0555] = 0x00AA00AA; + bank2_base[0x02AA] = 0x00550055; + bank2_base[0x0555] = 0x00900090; + IOSYNC; + ISYNC; + bank2_read = bank2_base[0x10]; + + /* Read from bank 1 (it's in read mode) */ + bank1_read = bank1_base[0x10]; + + /* Reset Flash */ + bank1_base[0] = 0x00F000F0; + bank2_base[0] = 0x00F000F0; + + if (bank2_read == bank1_read) { + /* + * In both CFI command and autoselect modes, + * we got the some data reading from Flash. + * There is only one mirrored bank. + */ + tqm834x_num_flash_banks = 1; + total_size = bank1_size; + } + } + } + + debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks); + + /* set OR0 and BR0 */ + im->lbus.bank[0].or = CFG_OR_TIMING_FLASH | + (-(total_size) & OR_GPCM_AM); + im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) | + (BR_MS_GPCM | BR_PS_32 | BR_V); + + return (0); +} + +/************************************************************************* + * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly. + */ +static long int get_ddr_bank_size(short cs, volatile long *base) +{ + /* This array lists all valid DDR SDRAM configurations, with + * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM). + * The last entry has to to have size equal 0 and is igonred during + * autodection. Bank sizes must be in increasing order of size + */ + struct { + long row; + long col; + long size; + } conf[] = { + {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20}, + {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20}, + {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20}, + {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20}, + {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20}, + {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20}, + {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20}, + {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20}, + {0, 0, 0} + }; + + int i; + int detected; + long size; + + detected = -1; + for(i = 0; conf[i].size != 0; ++i) { + + /* set sdram bank configuration */ + set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row); + + debug("Getting RAM size...\n"); + size = get_ram_size(base, DDR_MAX_SIZE_PER_CS); + + if((size == conf[i].size) && (i == detected + 1)) + detected = i; + + debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n", + conf[i].row, + conf[i].col, + conf[i].size >> 20, + base, + size >> 20); + } + + if(detected == -1){ + /* disable empty cs */ + debug("\nNo valid configurations for CS%d, disabling...\n", cs); + set_cs_config(cs, 0); + return 0; + } + + debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n", + conf[detected].row, conf[detected].col, conf[detected].size >> 20, base); + + /* configure cs ro detected params */ + set_cs_config(cs, CSCONFIG_EN | conf[detected].row | + conf[detected].col); + + set_cs_bounds(cs, (long)base, conf[detected].size); + + return(conf[detected].size); +} + +/************************************************************************** + * Sets DDR bank CS bounds. + */ +static void set_cs_bounds(short cs, long base, long size) +{ + debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs); + if(size == 0){ + im->ddr.csbnds[cs].csbnds = 0x00000000; + } else { + im->ddr.csbnds[cs].csbnds = + ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((base + size - 1) >> CSBNDS_EA_SHIFT) & + CSBNDS_EA); + } + SYNC; +} + +/************************************************************************** + * Sets DDR banks CS configuration. + * config == 0x00000000 disables the CS. + */ +static void set_cs_config(short cs, long config) +{ + debug("Setting config %08x for cs %d\n", config, cs); + im->ddr.cs_config[cs] = config; + SYNC; +} + +/************************************************************************** + * Sets DDR clocks, timings and configuration. + */ +static void set_ddr_config(void) { + /* clock control */ + im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN | + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; + SYNC; + + /* timing configuration */ + im->ddr.timing_cfg_1 = + (4 << TIMING_CFG1_PRETOACT_SHIFT) | + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | + (4 << TIMING_CFG1_ACTTORW_SHIFT) | + (5 << TIMING_CFG1_REFREC_SHIFT) | + (3 << TIMING_CFG1_WRREC_SHIFT) | + (3 << TIMING_CFG1_ACTTOACT_SHIFT) | + (1 << TIMING_CFG1_WRTORD_SHIFT) | + (TIMING_CFG1_CASLAT & TIMING_CASLAT); + + im->ddr.timing_cfg_2 = + TIMING_CFG2_CPO_DEF | + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT); + SYNC; + + /* don't enable DDR controller yet */ + im->ddr.sdram_cfg = + SDRAM_CFG_SREN | + SDRAM_CFG_SDRAM_TYPE_DDR; + SYNC; + + /* Set SDRAM mode */ + im->ddr.sdram_mode = + ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) << + SDRAM_MODE_ESD_SHIFT) | + ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) << + SDRAM_MODE_SD_SHIFT) | + ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) & + MODE_CASLAT); + SYNC; + + /* Set fast SDRAM refresh rate */ + im->ddr.sdram_interval = + (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | + (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); + SYNC; +} diff --git a/board/tqm834x/u-boot.lds b/board/tqm834x/u-boot.lds new file mode 100644 index 0000000..020cfa6 --- /dev/null +++ b/board/tqm834x/u-boot.lds @@ -0,0 +1,122 @@ +/* + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/tqm85xx/Makefile b/board/tqm85xx/Makefile new file mode 100644 index 0000000..3933d46 --- /dev/null +++ b/board/tqm85xx/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o sdram.o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/tqm85xx/config.mk b/board/tqm85xx/config.mk new file mode 100644 index 0000000..52e84ad --- /dev/null +++ b/board/tqm85xx/config.mk @@ -0,0 +1,29 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# tqm85xx board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 256k +# +TEXT_BASE = 0xfffc0000 diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S new file mode 100644 index 0000000..1f61038 --- /dev/null +++ b/board/tqm85xx/init.S @@ -0,0 +1,234 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0, 1: 128M Non-cacheable, guarded + * 0xf8000000 128M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7+8: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS0(1, 8, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c new file mode 100644 index 0000000..9c1f087 --- /dev/null +++ b/board/tqm85xx/sdram.c @@ -0,0 +1,226 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include + +struct sdram_conf_s { + unsigned long size; + unsigned long reg; +}; + +typedef struct sdram_conf_s sdram_conf_t; + +sdram_conf_t ddr_cs_conf[] = { + {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ + {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ + {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ + {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ +}; + +#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) + +int cas_latency(void); + +/* + * Autodetect onboard DDR SDRAM on 85xx platforms + * + * NOTE: Some of the hardcoded values are hardware dependant, + * so this should be extended for other future boards + * using this routine! + */ +long int sdram_setup(int casl) +{ + int i; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr; + unsigned long cfg_ddr_timing1; + unsigned long cfg_ddr_mode; + + /* + * Disable memory controller. + */ + ddr->cs0_config = 0; + ddr->sdram_cfg = 0; + + switch (casl) { + case 20: + cfg_ddr_timing1 = 0x47405331 | (3 << 16); + cfg_ddr_mode = 0x40020002 | (2 << 4); + break; + + case 25: + cfg_ddr_timing1 = 0x47405331 | (4 << 16); + cfg_ddr_mode = 0x40020002 | (6 << 4); + break; + + case 30: + default: + cfg_ddr_timing1 = 0x47405331 | (5 << 16); + cfg_ddr_mode = 0x40020002 | (3 << 4); + break; + } + + ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; + ddr->cs0_config = ddr_cs_conf[0].reg; + ddr->timing_cfg_1 = cfg_ddr_timing1; + ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ + ddr->sdram_mode = cfg_ddr_mode; + ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ + ddr->err_disable = 0x0000000D; + + asm ("sync;isync;msync"); + udelay(1000); + + ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ + asm ("sync; isync; msync"); + udelay(1000); + + for (i=0; ics0_config = ddr_cs_conf[i].reg; + + if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) { + /* + * OK, size detected -> all done + */ + return ddr_cs_conf[i].size; + } + } + + return 0; /* nothing found ! */ +} + +void board_add_ram_info(int use_default) +{ + int casl; + + if (use_default) + casl = CONFIG_DDR_DEFAULT_CL; + else + casl = cas_latency(); + + puts(" (CL="); + switch (casl) { + case 20: + puts("2)"); + break; + + case 25: + puts("2.5)"); + break; + + case 30: + puts("3)"); + break; + } +} + +long int initdram (int board_type) +{ + long dram_size = 0; + int casl; + +#if defined(CONFIG_DDR_DLL) + /* + * This DLL-Override only used on TQM8540 and TQM8560 + */ + { + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_gur_t *gur= &immap->im_gur; + int i,x; + + x = 10; + + /* + * Work around to stabilize DDR DLL + */ + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay (200); + while (gur->ddrdllcr != 0x81000100) { + gur->devdisr = gur->devdisr | 0x00010000; + asm("sync;isync;msync"); + for (i=0; idevdisr = gur->devdisr & 0xfff7ffff; + asm("sync;isync;msync"); + x++; + } + } +#endif + + casl = cas_latency(); + dram_size = sdram_setup(casl); + if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { + /* + * Try again with default CAS latency + */ + puts("Problem with CAS lantency"); + board_add_ram_info(1); + puts(", using default CL!\n"); + casl = CONFIG_DDR_DEFAULT_CL; + dram_size = sdram_setup(casl); + puts(" "); + } + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf ("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test passed.\n"); + return 0; +} +#endif diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c new file mode 100644 index 0000000..13ea6f4 --- /dev/null +++ b/board/tqm85xx/tqm85xx.c @@ -0,0 +1,411 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +void local_bus_init (void); +long int fixed_sdram (void); +ulong flash_get_size (ulong base, int banknum); + +#ifdef CONFIG_CPM2 +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; +#endif /* CONFIG_CPM2 */ + +#define CASL_STRING1 "casl=xx" +#define CASL_STRING2 "casl=" + +static const int casl_table[] = { 20, 25, 30 }; +#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) + +int cas_latency(void) +{ + char *s = getenv("serial#"); + int casl; + int val; + int i; + + casl = CONFIG_DDR_DEFAULT_CL; + + if (s != NULL) { + if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2, + strlen(CASL_STRING2)) == 0) { + val = simple_strtoul(s + strlen(s) - 2, NULL, 10); + + for (i=0; iim_lbc; + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if boot FLASH isn't max size + */ + if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { + memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); + memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + } + + /* + * Check if only one FLASH bank is available + */ + if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { + memctl->or1 = 0; + memctl->br1 = 0; + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + } + + return 0; +} + +/* + * Initialize Local Bus + */ +void local_bus_init (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info (&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->ltedr = 0xa4c80000; /* DK: !!! */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr (); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + udelay (200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm ("sync;isync;msync"); + } +} + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + {} +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void pci_init_board (void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init (struct pci_controller *hose); + + pci_mpc85xx_init (&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/tqm85xx/u-boot.lds b/board/tqm85xx/u-boot.lds new file mode 100644 index 0000000..4cc825b --- /dev/null +++ b/board/tqm85xx/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2002,2003, Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/tqm85xx/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/tqm85xx/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm8xx/Makefile b/board/tqm8xx/Makefile new file mode 100644 index 0000000..2ff9b4d --- /dev/null +++ b/board/tqm8xx/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o load_sernum_ethaddr.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/tqm8xx/config.mk b/board/tqm8xx/config.mk new file mode 100644 index 0000000..9d6080b --- /dev/null +++ b/board/tqm8xx/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8xxL boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c new file mode 100644 index 0000000..97bb5c3 --- /dev/null +++ b/board/tqm8xx/flash.c @@ -0,0 +1,829 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if 0 +#define DEBUG +#endif + +#include +#include +#include + +#include + +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) +# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ +# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) +# endif +#endif /* CONFIG_TQM8xxL/M, !TQM866M */ + +#ifndef CFG_ENV_ADDR +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + +#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ + int scy, trlx, flash_or_timing, clk_diff; + + DECLARE_GLOBAL_DATA_PTR; + + scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; + if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { + trlx = OR_TRLX; + scy *= 2; + } else + trlx = 0; + + /* We assume that each 10MHz of bus clock require 1-clk SCY + * adjustment. + */ + clk_diff = (gd->bus_clk / 1000000) - 50; + + /* We need proper rounding here. This is what the "+5" and "-5" + * are here for. + */ + if (clk_diff >= 0) + scy += (clk_diff + 5) / 10; + else + scy += (clk_diff - 5) / 10; + + /* For bus frequencies above 50MHz, we want to use relaxed timing + * (OR_TRLX). + */ + if (gd->bus_clk >= 50000000) + trlx = OR_TRLX; + else + trlx = 0; + + if (trlx) + scy /= 2; + + if (scy > 0xf) + scy = 0xf; + if (scy < 1) + scy = 1; + + flash_or_timing = (scy << 4) | trlx | + (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); +#endif + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + debug ("## Before remap: " + "BR0: 0x%08x OR0: 0x%08x " + "BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0, + memctl->memc_br1, memctl->memc_or1); + + /* Remap FLASH according to real size */ +#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); +#else + memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK); +#endif + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + debug ("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + debug ("Protect monitor: %08lx ... %08lx\n", + (ulong)CFG_MONITOR_BASE, + (ulong)CFG_MONITOR_BASE + monitor_flash_len - 1); + + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ +# ifdef CFG_ENV_ADDR_REDUND + debug ("Protect primary environment: %08lx ... %08lx\n", + (ulong)CFG_ENV_ADDR, + (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); +# else + debug ("Protect environment: %08lx ... %08lx\n", + (ulong)CFG_ENV_ADDR, + (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); +# endif + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_ADDR_REDUND + debug ("Protect redundand environment: %08lx ... %08lx\n", + (ulong)CFG_ENV_ADDR_REDUND, + (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + if (size_b1) { +#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); +#else + memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000); +#endif + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V; + + debug ("## BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[1]); +#endif + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + flash_info[1].size = 0; + + debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + } + + debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { +#ifdef CONFIG_TQM8xxM /* mirror bit flash */ + case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); + break; + case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n"); + break; + case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n"); + break; + case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n"); + break; +# else /* ! TQM8xxM */ + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; +#endif /* TQM8xxM */ + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AMDL163B: printf ("AM29DL163B (16 Mbit, bottom boot sect)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value) { + case AMD_MANUFACT: + debug ("Manufacturer: AMD\n"); + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + debug ("Manufacturer: FUJITSU\n"); + info->flash_id = FLASH_MAN_FUJ; + break; + default: + debug ("Manufacturer: *** unknown ***\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value) { +#ifdef CONFIG_TQM8xxM /* mirror bit flash */ + case AMD_ID_MIRROR: + debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", + addr[14], addr[15]); + /* Special case for AMLV320MH/L */ + if ((addr[14] & 0x00ff00ff) == 0x001d001d && + (addr[15] & 0x00ff00ff) == 0x00000000) { + debug ("Chip: AMLV320MH/L\n"); + info->flash_id += FLASH_AMLV320U; + info->sector_count = 64; + info->size = 0x00800000; /* => 8 MB */ + break; + } + switch(addr[14]) { + case AMD_ID_LV128U_2: + if (addr[15] != AMD_ID_LV128U_3) { + debug ("Chip: AMLV128U -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + debug ("Chip: AMLV128U\n"); + info->flash_id += FLASH_AMLV128U; + info->sector_count = 256; + info->size = 0x02000000; + } + break; /* => 32 MB */ + case AMD_ID_LV640U_2: + if (addr[15] != AMD_ID_LV640U_3) { + debug ("Chip: AMLV640U -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + debug ("Chip: AMLV640U\n"); + info->flash_id += FLASH_AMLV640U; + info->sector_count = 128; + info->size = 0x01000000; + } + break; /* => 16 MB */ + case AMD_ID_LV320B_2: + if (addr[15] != AMD_ID_LV320B_3) { + debug ("Chip: AMLV320B -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + debug ("Chip: AMLV320B\n"); + info->flash_id += FLASH_AMLV320B; + info->sector_count = 71; + info->size = 0x00800000; + } + break; /* => 8 MB */ + default: + debug ("Chip: *** unknown ***\n"); + info->flash_id = FLASH_UNKNOWN; + break; + } + break; +# else /* ! TQM8xxM */ + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif /* TQM8xxM */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_DL163B: + info->flash_id += FLASH_AMDL163B; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + switch (value) { +#ifdef CONFIG_TQM8xxM /* mirror bit flash */ + case AMD_ID_MIRROR: + switch (info->flash_id & FLASH_TYPEMASK) { + /* only known types here - no default */ + case FLASH_AMLV128U: + case FLASH_AMLV640U: + case FLASH_AMLV320U: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x20000; + } + break; + case FLASH_AMLV320B: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The first 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < 8) + ? 2 * ( 8 << 10) + : 2 * (64 << 10); + } + break; + } + break; +# else /* ! TQM8xxM */ + case AMD_ID_LV400B: + case AMD_ID_LV800B: + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + break; + case AMD_ID_LV400T: + case AMD_ID_LV800T: + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + break; + case AMD_ID_LV320B: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The first 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < 8) + ? 2 * ( 8 << 10) + : 2 * (64 << 10); + } + break; + case AMD_ID_LV320T: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The last 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < (info->sector_count - 8)) + ? 2 * (64 << 10) + : 2 * ( 8 << 10); + } + break; +#endif /* TQM8xxM */ + case AMD_ID_LV160B: + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + break; + case AMD_ID_LV160T: + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + break; + case AMD_ID_DL163B: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The first 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < 8) + ? 2 * ( 8 << 10) + : 2 * (64 << 10); + } + break; + default: + return (0); + break; + } + +#if 0 + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } +#endif + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/tqm8xx/load_sernum_ethaddr.c b/board/tqm8xx/load_sernum_ethaddr.c new file mode 100644 index 0000000..143f368 --- /dev/null +++ b/board/tqm8xx/load_sernum_ethaddr.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/*----------------------------------------------------------------------- + * Process Hardware Information Block: + * + * If we boot on a system fresh from factory, check if the Hardware + * Information Block exists and save the information it contains. + * + * The TQM8xxL / TQM82xx Hardware Information Block is defined as + * follows: + * - located in first flash bank + * - starts at offset 0x0003FFC0 + * - size 0x00000040 + * + * Internal structure: + * - sequence of ASCII character strings + * - fields separated by a single space character (0x20) + * - last field terminated by NUL character (0x00) + * - remaining space filled with NUL characters (0x00) + * + * Fields in Hardware Information Block: + * 1) Module Type + * 2) Serial Number + * 3) First MAC Address + * 4) Number of additional MAC addresses + */ + +void load_sernum_ethaddr (void) +{ + unsigned char *hwi; + unsigned char serial [CFG_HWINFO_SIZE]; + unsigned char ethaddr[CFG_HWINFO_SIZE]; + unsigned short ih, is, ie, part; + + hwi = (unsigned char *)(CFG_FLASH_BASE + CFG_HWINFO_OFFSET); + ih = is = ie = 0; + + if (*((unsigned long *)hwi) != (unsigned long)CFG_HWINFO_MAGIC) { + return; + } + + part = 1; + + /* copy serial # / MAC address */ + while ((hwi[ih] != '\0') && (ih < CFG_HWINFO_SIZE)) { + if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */ + return; + } + switch (part) { + default: /* Copy serial # */ + if (hwi[ih] == ' ') { + ++part; + } + serial[is++] = hwi[ih]; + break; + case 3: /* Copy MAC address */ + if (hwi[ih] == ' ') { + ++part; + break; + } + ethaddr[ie++] = hwi[ih]; + if ((ie % 3) == 2) + ethaddr[ie++] = ':'; + break; + } + ++ih; + } + serial[is] = '\0'; + if (ie && ethaddr[ie-1] == ':') + --ie; + ethaddr[ie] = '\0'; + + /* set serial# and ethaddr if not yet defined */ + if (getenv("serial#") == NULL) { + setenv ((char *)"serial#", (char *)serial); + } + + if (getenv("ethaddr") == NULL) { + setenv ((char *)"ethaddr", (char *)ethaddr); + } +} diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c new file mode 100644 index 0000000..017bdf9 --- /dev/null +++ b/board/tqm8xx/tqm8xx.c @@ -0,0 +1,501 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if 0 +#define DEBUG +#endif + +#include +#include +#ifdef CONFIG_PS2MULT +#include +#endif + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, + 0x1FF5FC47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Test TQ ID string (TQM8xx...) + * If present, check for "L" type (no second DRAM bank), + * otherwise "L" type is assumed as default. + * + * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else. + */ + +int checkboard (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char *s = getenv ("serial#"); + + puts ("Board: "); + + if (!s || strncmp (s, "TQM8", 4)) { + puts ("### No HW ID - assuming TQM8xxL\n"); + return (0); + } + + if ((*(s + 6) == 'L')) { /* a TQM8xxL type */ + gd->board_type = 'L'; + } + + if ((*(s + 6) == 'M')) { /* a TQM8xxM type */ + gd->board_type = 'M'; + } + + for (; *s; ++s) { + if (*s == ' ') + break; + putc (*s); + } + putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size8, size9, size10; + long int size_b0 = 0; + long int size_b1 = 0; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + /* + * The following value is used as an address (i.e. opcode) for + * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If + * the port size is 32bit the SDRAM does NOT "see" the lower two + * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for + * MICRON SDRAMs: + * -> 0 00 010 0 010 + * | | | | +- Burst Length = 4 + * | | | +----- Burst Type = Sequential + * | | +------- CAS Latency = 2 + * | +----------- Operating Mode = Standard + * +-------------- Write Burst Mode = Programmed Burst Length + */ + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + +#ifndef CONFIG_CAN_DRIVER + if ((board_type != 'L') && + (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + } +#endif /* CONFIG_CAN_DRIVER */ + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ + udelay (1); + +#ifndef CONFIG_CAN_DRIVER + if ((board_type != 'L') && + (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */ + memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ + udelay (1); + memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ + udelay (1); + } +#endif /* CONFIG_CAN_DRIVER */ + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); + + udelay(1000); + +#if defined(CFG_MAMR_10COL) + /* + * try 10 column mode + */ + size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM, + SDRAM_MAX_SIZE); + debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); +#else + size10 = 0; +#endif /* CFG_MAMR_10COL */ + + if ((size8 < size10) && (size9 < size10)) { + size_b0 = size10; + } else if ((size8 < size9) && (size10 < size9)) { + size_b0 = size9; + memctl->memc_mamr = CFG_MAMR_9COL; + udelay (500); + } else { + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); + } + debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20); + +#ifndef CONFIG_CAN_DRIVER + if ((board_type != 'L') && + (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */ + /* + * Check Bank 1 Memory Size + * use current column settings + * [9 column SDRAM may also be used in 8 column mode, + * but then only half the real size will be used.] + */ + size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); + debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20); + } else { + size_b1 = 0; + } +#endif /* CONFIG_CAN_DRIVER */ + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping: map bigger bank first + */ + if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ + + memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b0 > 0) { + /* + * Position Bank 0 immediately above Bank 1 + */ + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + + size_b1; + } else { + unsigned long reg; + + /* + * No bank 0 + * + * invalidate bank + */ + memctl->memc_br2 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + + } else { /* SDRAM Bank 0 is bigger - map first */ + + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b1 > 0) { + /* + * Position Bank 1 immediately above Bank 0 + */ + memctl->memc_or3 = + ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = + ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + + size_b0; + } else { + unsigned long reg; + +#ifndef CONFIG_CAN_DRIVER + /* + * No bank 1 + * + * invalidate bank + */ + memctl->memc_br3 = 0; +#endif /* CONFIG_CAN_DRIVER */ + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + } + + udelay (10000); + +#ifdef CONFIG_CAN_DRIVER + /* Initialize OR3 / BR3 */ + memctl->memc_or3 = CFG_OR3_CAN; + memctl->memc_br3 = CFG_BR3_CAN; + + /* Initialize MBMR */ + memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ + + /* Initialize UPMB for CAN: single read */ + memctl->memc_mdr = 0xFFFFC004; + memctl->memc_mcr = 0x0100 | UPMB; + + memctl->memc_mdr = 0x0FFFD004; + memctl->memc_mcr = 0x0101 | UPMB; + + memctl->memc_mdr = 0x0FFFC000; + memctl->memc_mcr = 0x0102 | UPMB; + + memctl->memc_mdr = 0x3FFFC004; + memctl->memc_mcr = 0x0103 | UPMB; + + memctl->memc_mdr = 0xFFFFDC05; + memctl->memc_mcr = 0x0104 | UPMB; + + /* Initialize UPMB for CAN: single write */ + memctl->memc_mdr = 0xFFFCC004; + memctl->memc_mcr = 0x0118 | UPMB; + + memctl->memc_mdr = 0xCFFCD004; + memctl->memc_mcr = 0x0119 | UPMB; + + memctl->memc_mdr = 0x0FFCC000; + memctl->memc_mcr = 0x011A | UPMB; + + memctl->memc_mdr = 0x7FFCC004; + memctl->memc_mcr = 0x011B | UPMB; + + memctl->memc_mdr = 0xFFFDCC05; + memctl->memc_mcr = 0x011C | UPMB; +#endif /* CONFIG_CAN_DRIVER */ + +#ifdef CONFIG_ISP1362_USB + /* Initialize OR5 / BR5 */ + memctl->memc_or5 = CFG_OR5_ISP1362; + memctl->memc_br5 = CFG_BR5_ISP1362; +#endif /* CONFIG_ISP1362_USB */ + + + return (size_b0 + size_b1); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_PS2MULT + +#ifdef CONFIG_HMI10 +#define BASE_BAUD ( 1843200 / 16 ) +struct serial_state rs_table[] = { + { BASE_BAUD, 4, (void*)0xec140000 }, + { BASE_BAUD, 2, (void*)0xec150000 }, + { BASE_BAUD, 6, (void*)0xec160000 }, + { BASE_BAUD, 10, (void*)0xec170000 }, +}; + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ + ps2mult_early_init(); + return (0); +} +#endif +#endif /* CONFIG_HMI10 */ + +#endif /* CONFIG_PS2MULT */ + +/* ---------------------------------------------------------------------------- */ +/* HMI10 specific stuff */ +/* ---------------------------------------------------------------------------- */ +#ifdef CONFIG_HMI10 + +int misc_init_r (void) +{ +# ifdef CONFIG_IDE_LED + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* Configure PA15 as output port */ + immap->im_ioport.iop_padir |= 0x0001; + immap->im_ioport.iop_paodr |= 0x0001; + immap->im_ioport.iop_papar &= ~0x0001; + immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ +# endif + return (0); +} + +# ifdef CONFIG_IDE_LED +void ide_led (uchar led, uchar status) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* We have one led for both pcmcia slots */ + if (status) { /* led on */ + immap->im_ioport.iop_padat |= 0x0001; + } else { + immap->im_ioport.iop_padat &= ~0x0001; + } +} +# endif +#endif /* CONFIG_HMI10 */ + +/* ---------------------------------------------------------------------------- */ +/* NSCU specific stuff */ +/* ---------------------------------------------------------------------------- */ +#ifdef CONFIG_NSCU + +int misc_init_r (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* wake up ethernet module */ + immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ + immr->im_ioport.iop_pcdir |= 0x0004; /* output */ + immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ + immr->im_ioport.iop_pcdat |= 0x0004; /* enable */ + + return (0); +} +#endif /* CONFIG_NSCU */ + +/* ------------------------------------------------------------------------- */ diff --git a/board/tqm8xx/u-boot.lds b/board/tqm8xx/u-boot.lds new file mode 100644 index 0000000..d526d1d --- /dev/null +++ b/board/tqm8xx/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm8xx/u-boot.lds.debug b/board/tqm8xx/u-boot.lds.debug new file mode 100644 index 0000000..ddd4678 --- /dev/null +++ b/board/tqm8xx/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/trab/Makefile b/board/trab/Makefile new file mode 100644 index 0000000..ced9bc5 --- /dev/null +++ b/board/trab/Makefile @@ -0,0 +1,65 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o +SOBJS := lowlevel_init.o + +gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) + +LOAD_ADDR = 0xc100000 + +######################################################################### + +all: $(LIB) trab_fkt.srec trab_fkt.bin + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +trab_fkt.srec: trab_fkt.o rs485.o tsc2000.o $(LIB) + $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ $(LIB) \ + -L../../examples -lstubs \ + -L../../lib_generic -lgeneric \ + -L$(gcclibdir) -lgcc + $(OBJCOPY) -O srec $(<:.o=) $@ + +trab_fkt.bin: trab_fkt.srec + $(OBJCOPY) -O binary $< $@ 2>/dev/null + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/trab/Pt1000_temp_data.h b/board/trab/Pt1000_temp_data.h new file mode 100644 index 0000000..17e9ed7 --- /dev/null +++ b/board/trab/Pt1000_temp_data.h @@ -0,0 +1,71 @@ +/* + * Data file for tsc2000 driver. + * Copyright (C) 2002, 2003 DENX Software Engineering, Wolfgang Denk, wd@denx.de + */ + +#ifndef _PT1000_TEMP_DATA_H +#define _PT1000_TEMP_DATA_H + +long Pt1000_temp_table[][2] = { + /* For quick range checking the largest element + * is placed at index 0. + * U, nV T, C*100 + */ + { 44000000 , 12165 }, + { -10000000 , -2644 }, + { -9000000 , -2381 }, + { -8000000 , -2118 }, + { -7000000 , -1855 }, + { -6000000 , -1591 }, + { -5000000 , -1327 }, + { -4000000 , -1063 }, + { -3000000 , -798 }, + { -2000000 , -532 }, + { -1000000 , -266 }, + { 0 , 000 }, + { 1000000 , 267 }, + { 2000000 , 534 }, + { 3000000 , 802 }, + { 4000000 , 1070 }, + { 5000000 , 1338 }, + { 6000000 , 1607 }, + { 7000000 , 1876 }, + { 8000000 , 2146 }, + { 9000000 , 2416 }, + { 10000000 , 2687 }, + { 11000000 , 2958 }, + { 12000000 , 3230 }, + { 13000000 , 3502 }, + { 14000000 , 3774 }, + { 15000000 , 4047 }, + { 16000000 , 4321 }, + { 17000000 , 4595 }, + { 18000000 , 4869 }, + { 19000000 , 5144 }, + { 20000000 , 5419 }, + { 21000000 , 5694 }, + { 22000000 , 5971 }, + { 23000000 , 6247 }, + { 24000000 , 6524 }, + { 25000000 , 6802 }, + { 26000000 , 7080 }, + { 27000000 , 7358 }, + { 28000000 , 7637 }, + { 29000000 , 7916 }, + { 30000000 , 8196 }, + { 31000000 , 8476 }, + { 32000000 , 8757 }, + { 33000000 , 9039 }, + { 34000000 , 9320 }, + { 35000000 , 9602 }, + { 36000000 , 9885 }, + { 37000000 , 10168 }, + { 38000000 , 10452 }, + { 39000000 , 10736 }, + { 40000000 , 11021 }, + { 41000000 , 11306 }, + { 42000000 , 11592 }, + { 43000000 , 11879 }, + { 44000000 , 12165 }, +}; +#endif /* _PT1000_TEMP_DATA_H */ diff --git a/board/trab/README.kbd b/board/trab/README.kbd new file mode 100644 index 0000000..3db00bc --- /dev/null +++ b/board/trab/README.kbd @@ -0,0 +1,44 @@ + +The TRAB keyboard implementation is similar to that for LWMON and +R360MPI boards. The only difference concerns key naming. There are 4 +keys on TRAB: 1, 2, 3, 4. + +1) The "kbd" command provides information about the current state of + the keys. For example, + + TRAB # kbd + Keys: 1 0 1 0 + + means that keys 1 and 3 are pressed. The keyboard status is also + stored in the "keybd" environment variable. In this example we get + + keybd=1010 + +2) The "preboot" variable is set according to current environment + settings and keys pressed. This is an example: + + TRAB # setenv magic_keys XY + TRAB # setenv key_magicX 12 + TRAB # setenv key_cmdX echo ## Keys 1 + 2 pressed ##\;echo + TRAB # setenv key_magicY 13 + TRAB # setenv key_cmdY echo ## Keys 1 + 3 pressed ##\;echo + + Here "magic_keys=XY" means that the "key_magicX" and "key_magicY" + variables will be checked for a match. Each variable "key_magic*" + defines a set of keys. In the our example, if keys 1 and 3 are + pressed during reset, then "key_magicY" matches, so the "preboot" + variable will be set to the contents of "key_cmdY": + + preboot=echo ## Keys 1 + 3 pressed ##;echo + +3) The TRAB board has optional modem support. When a certain key + combination is pressed on the keyboard at power-on, the firmware + performs the necessary initialization of the modem and allows for + dial-in. The key combination is specified in the + "include/configs/trab.h" file. For example: + + #define CONFIG_MODEM_KEY_MAGIC "23" + + means that modem will be initialized if and only if both keys 2, 3 + are pressed. Note that the format of this string is similar to the + format of "key_magic*" environment variables described above. diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c new file mode 100644 index 0000000..056e562 --- /dev/null +++ b/board/trab/auto_update.c @@ -0,0 +1,656 @@ +/* + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CFG_HUSH_PARSER +#include +#endif + +#ifdef CONFIG_AUTO_UPDATE + +#ifndef CONFIG_USB_OHCI +#error "must define CONFIG_USB_OHCI" +#endif + +#ifndef CONFIG_USB_STORAGE +#error "must define CONFIG_USB_STORAGE" +#endif + +#ifndef CFG_HUSH_PARSER +#error "must define CFG_HUSH_PARSER" +#endif + +#if !(CONFIG_COMMANDS & CFG_CMD_FAT) +#error "must define CFG_CMD_FAT" +#endif + +/* + * Check whether a USB memory stick is plugged in. + * If one is found: + * 1) if prepare.img ist found load it into memory. If it is + * valid then run it. + * 2) if preinst.img is found load it into memory. If it is + * valid then run it. Update the EEPROM. + * 3) if firmware.img is found load it into memory. If it is valid, + * burn it into FLASH and update the EEPROM. + * 4) if kernel.img is found load it into memory. If it is valid, + * burn it into FLASH and update the EEPROM. + * 5) if app.img is found load it into memory. If it is valid, + * burn it into FLASH and update the EEPROM. + * 6) if disk.img is found load it into memory. If it is valid, + * burn it into FLASH and update the EEPROM. + * 7) if postinst.img is found load it into memory. If it is + * valid then run it. Update the EEPROM. + */ + +#undef AU_DEBUG + +#undef debug +#ifdef AU_DEBUG +#define debug(fmt,args...) printf (fmt ,##args) +#else +#define debug(fmt,args...) +#endif /* AU_DEBUG */ + +/* possible names of files on the USB stick. */ +#define AU_PREPARE "prepare.img" +#define AU_PREINST "preinst.img" +#define AU_FIRMWARE "firmware.img" +#define AU_KERNEL "kernel.img" +#define AU_APP "app.img" +#define AU_DISK "disk.img" +#define AU_POSTINST "postinst.img" + +struct flash_layout +{ + long start; + long end; +}; + +/* layout of the FLASH. ST = start address, ND = end address. */ +#ifndef CONFIG_FLASH_8MB /* 16 MB Flash, 32 MB RAM */ +#define AU_FL_FIRMWARE_ST 0x00000000 +#define AU_FL_FIRMWARE_ND 0x0009FFFF +#define AU_FL_VFD_ST 0x000A0000 +#define AU_FL_VFD_ND 0x000BFFFF +#define AU_FL_KERNEL_ST 0x000C0000 +#define AU_FL_KERNEL_ND 0x001BFFFF +#define AU_FL_APP_ST 0x001C0000 +#define AU_FL_APP_ND 0x005BFFFF +#define AU_FL_DISK_ST 0x005C0000 +#define AU_FL_DISK_ND 0x00FFFFFF +#else /* 8 MB Flash, 32 MB RAM */ +#define AU_FL_FIRMWARE_ST 0x00000000 +#define AU_FL_FIRMWARE_ND 0x0005FFFF +#define AU_FL_KERNEL_ST 0x00060000 +#define AU_FL_KERNEL_ND 0x0013FFFF +#define AU_FL_APP_ST 0x00140000 +#define AU_FL_APP_ND 0x0067FFFF +#define AU_FL_DISK_ST 0x00680000 +#define AU_FL_DISK_ND 0x007DFFFF +#define AU_FL_VFD_ST 0x007E0000 +#define AU_FL_VFD_ND 0x007FFFFF +#endif /* CONFIG_FLASH_8MB */ + +/* a structure with the offsets to values in the EEPROM */ +struct eeprom_layout +{ + int time; + int size; + int dcrc; +}; + +/* layout of the EEPROM - offset from the start. All entries are 32 bit. */ +#define AU_EEPROM_TIME_PREINST 64 +#define AU_EEPROM_SIZE_PREINST 68 +#define AU_EEPROM_DCRC_PREINST 72 +#define AU_EEPROM_TIME_FIRMWARE 76 +#define AU_EEPROM_SIZE_FIRMWARE 80 +#define AU_EEPROM_DCRC_FIRMWARE 84 +#define AU_EEPROM_TIME_KERNEL 88 +#define AU_EEPROM_SIZE_KERNEL 92 +#define AU_EEPROM_DCRC_KERNEL 96 +#define AU_EEPROM_TIME_APP 100 +#define AU_EEPROM_SIZE_APP 104 +#define AU_EEPROM_DCRC_APP 108 +#define AU_EEPROM_TIME_DISK 112 +#define AU_EEPROM_SIZE_DISK 116 +#define AU_EEPROM_DCRC_DISK 120 +#define AU_EEPROM_TIME_POSTINST 124 +#define AU_EEPROM_SIZE_POSTINST 128 +#define AU_EEPROM_DCRC_POSTINST 132 + +static int au_usb_stor_curr_dev; /* current device */ + +/* index of each file in the following arrays */ +#define IDX_PREPARE 0 +#define IDX_PREINST 1 +#define IDX_FIRMWARE 2 +#define IDX_KERNEL 3 +#define IDX_APP 4 +#define IDX_DISK 5 +#define IDX_POSTINST 6 +/* max. number of files which could interest us */ +#define AU_MAXFILES 7 +/* pointers to file names */ +char *aufile[AU_MAXFILES]; +/* sizes of flash areas for each file */ +long ausize[AU_MAXFILES]; +/* offsets into the EEEPROM */ +struct eeprom_layout auee_off[AU_MAXFILES] = { \ + {0}, \ + {AU_EEPROM_TIME_PREINST, AU_EEPROM_SIZE_PREINST, AU_EEPROM_DCRC_PREINST,}, \ + {AU_EEPROM_TIME_FIRMWARE, AU_EEPROM_SIZE_FIRMWARE, AU_EEPROM_DCRC_FIRMWARE,}, \ + {AU_EEPROM_TIME_KERNEL, AU_EEPROM_SIZE_KERNEL, AU_EEPROM_DCRC_KERNEL,}, \ + {AU_EEPROM_TIME_APP, AU_EEPROM_SIZE_APP, AU_EEPROM_DCRC_APP,}, \ + {AU_EEPROM_TIME_DISK, AU_EEPROM_SIZE_DISK, AU_EEPROM_DCRC_DISK,}, \ + {AU_EEPROM_TIME_POSTINST, AU_EEPROM_SIZE_POSTINST, AU_EEPROM_DCRC_POSTINST,} \ + }; +/* array of flash areas start and end addresses */ +struct flash_layout aufl_layout[AU_MAXFILES - 3] = { \ + {AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \ + {AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \ + {AU_FL_APP_ST, AU_FL_APP_ND,}, \ + {AU_FL_DISK_ST, AU_FL_DISK_ND,}, \ +}; +/* convert the index into aufile[] to an index into aufl_layout[] */ +#define FIDX_TO_LIDX(idx) ((idx) - 2) + +/* where to load files into memory */ +#define LOAD_ADDR ((unsigned char *)0x0C100000) +/* the app is the largest image */ +#define MAX_LOADSZ ausize[IDX_APP] + +/* externals */ +extern int fat_register_device(block_dev_desc_t *, int); +extern int file_fat_detectfs(void); +extern long file_fat_read(const char *, void *, unsigned long); +extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int); +extern int i2c_write (uchar, uint, int , uchar* , int); +#ifdef CONFIG_VFD +extern int trab_vfd (ulong); +extern int transfer_pic(unsigned char, unsigned char *, int, int); +#endif +extern int flash_sect_erase(ulong, ulong); +extern int flash_sect_protect (int, ulong, ulong); +extern int flash_write (char *, ulong, ulong); +/* change char* to void* to shutup the compiler */ +extern int i2c_write_multiple (uchar, uint, int, void *, int); +extern int i2c_read_multiple (uchar, uint, int, void *, int); +extern block_dev_desc_t *get_dev (char*, int); +extern int u_boot_hush_start(void); + +int +au_check_cksum_valid(int idx, long nbytes) +{ + image_header_t *hdr; + unsigned long checksum; + + hdr = (image_header_t *)LOAD_ADDR; + + if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) + { + printf ("Image %s bad total SIZE\n", aufile[idx]); + return -1; + } + /* check the data CRC */ + checksum = ntohl(hdr->ih_dcrc); + + if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) + != checksum) + { + printf ("Image %s bad data checksum\n", aufile[idx]); + return -1; + } + return 0; +} + +int +au_check_header_valid(int idx, long nbytes) +{ + image_header_t *hdr; + unsigned long checksum; + unsigned char buf[4]; + + hdr = (image_header_t *)LOAD_ADDR; + /* check the easy ones first */ +#undef CHECK_VALID_DEBUG +#ifdef CHECK_VALID_DEBUG + printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC); + printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_ARM); + printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes); + printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL); +#endif + if (nbytes < sizeof(*hdr)) + { + printf ("Image %s bad header SIZE\n", aufile[idx]); + return -1; + } + if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_ARM) + { + printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); + return -1; + } + /* check the hdr CRC */ + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) { + printf ("Image %s bad header checksum\n", aufile[idx]); + return -1; + } + hdr->ih_hcrc = htonl(checksum); + /* check the type - could do this all in one gigantic if() */ + if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) { + printf ("Image %s wrong type\n", aufile[idx]); + return -1; + } + if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) { + printf ("Image %s wrong type\n", aufile[idx]); + return -1; + } + if ((idx == IDX_DISK) && (hdr->ih_type != IH_TYPE_FILESYSTEM)) { + printf ("Image %s wrong type\n", aufile[idx]); + return -1; + } + if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK) + && (hdr->ih_type != IH_TYPE_FILESYSTEM)) { + printf ("Image %s wrong type\n", aufile[idx]); + return -1; + } + if ((idx == IDX_PREPARE || idx == IDX_PREINST || idx == IDX_POSTINST) + && (hdr->ih_type != IH_TYPE_SCRIPT)) + { + printf ("Image %s wrong type\n", aufile[idx]); + return -1; + } + /* special case for prepare.img */ + if (idx == IDX_PREPARE) + return 0; + /* recycle checksum */ + checksum = ntohl(hdr->ih_size); + /* for kernel and app the image header must also fit into flash */ + if ((idx != IDX_DISK) && (idx != IDX_FIRMWARE)) + checksum += sizeof(*hdr); + /* check the size does not exceed space in flash. HUSH scripts */ + /* all have ausize[] set to 0 */ + if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { + printf ("Image %s is bigger than FLASH\n", aufile[idx]); + return -1; + } + /* check the time stamp from the EEPROM */ + /* read it in */ + i2c_read_multiple(0x54, auee_off[idx].time, 1, buf, sizeof(buf)); +#ifdef CHECK_VALID_DEBUG + printf ("buf[0] %#x buf[1] %#x buf[2] %#x buf[3] %#x " + "as int %#x time %#x\n", + buf[0], buf[1], buf[2], buf[3], + *((unsigned int *)buf), ntohl(hdr->ih_time)); +#endif + /* check it */ + if (*((unsigned int *)buf) >= ntohl(hdr->ih_time)) { + printf ("Image %s is too old\n", aufile[idx]); + return -1; + } + + return 0; +} + +/* power control defines */ +#define CPLD_VFD_BK ((volatile char *)0x04038002) +#define POWER_OFF (1 << 1) + +int +au_do_update(int idx, long sz) +{ + image_header_t *hdr; + char *addr; + long start, end; + int off, rc; + uint nbytes; + + hdr = (image_header_t *)LOAD_ADDR; + + /* disable the power switch */ + *CPLD_VFD_BK |= POWER_OFF; + + /* execute a script */ + if (hdr->ih_type == IH_TYPE_SCRIPT) { + addr = (char *)((char *)hdr + sizeof(*hdr)); + /* stick a NULL at the end of the script, otherwise */ + /* parse_string_outer() runs off the end. */ + addr[ntohl(hdr->ih_size)] = 0; + addr += 8; + parse_string_outer(addr, FLAG_PARSE_SEMICOLON); + return 0; + } + + start = aufl_layout[FIDX_TO_LIDX(idx)].start; + end = aufl_layout[FIDX_TO_LIDX(idx)].end; + + /* unprotect the address range */ + /* this assumes that ONLY the firmware is protected! */ + if (idx == IDX_FIRMWARE) { +#undef AU_UPDATE_TEST +#ifdef AU_UPDATE_TEST + /* erase it where Linux goes */ + start = aufl_layout[1].start; + end = aufl_layout[1].end; +#endif + flash_sect_protect(0, start, end); + } + + /* + * erase the address range. + */ + debug ("flash_sect_erase(%lx, %lx);\n", start, end); + flash_sect_erase(start, end); + wait_ms(100); + /* strip the header - except for the kernel and ramdisk */ + if (hdr->ih_type == IH_TYPE_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK) { + addr = (char *)hdr; + off = sizeof(*hdr); + nbytes = sizeof(*hdr) + ntohl(hdr->ih_size); + } else { + addr = (char *)((char *)hdr + sizeof(*hdr)); +#ifdef AU_UPDATE_TEST + /* copy it to where Linux goes */ + if (idx == IDX_FIRMWARE) + start = aufl_layout[1].start; +#endif + off = 0; + nbytes = ntohl(hdr->ih_size); + } + + /* copy the data from RAM to FLASH */ + debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); + rc = flash_write(addr, start, nbytes); + if (rc != 0) { + printf("Flashing failed due to error %d\n", rc); + return -1; + } + + /* check the dcrc of the copy */ + if (crc32 (0, (char *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) { + printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]); + return -1; + } + + /* protect the address range */ + /* this assumes that ONLY the firmware is protected! */ + if (idx == IDX_FIRMWARE) + flash_sect_protect(1, start, end); + return 0; +} + +int +au_update_eeprom(int idx) +{ + image_header_t *hdr; + int off; + uint32_t val; + + /* special case for prepare.img */ + if (idx == IDX_PREPARE) { + /* enable the power switch */ + *CPLD_VFD_BK &= ~POWER_OFF; + return 0; + } + + hdr = (image_header_t *)LOAD_ADDR; + /* write the time field into EEPROM */ + off = auee_off[idx].time; + val = ntohl(hdr->ih_time); + i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); + /* write the size field into EEPROM */ + off = auee_off[idx].size; + val = ntohl(hdr->ih_size); + i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); + /* write the dcrc field into EEPROM */ + off = auee_off[idx].dcrc; + val = ntohl(hdr->ih_dcrc); + i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); + /* enable the power switch */ + *CPLD_VFD_BK &= ~POWER_OFF; + return 0; +} + +/* + * this is called from board_init() after the hardware has been set up + * and is usable. That seems like a good time to do this. + * Right now the return value is ignored. + */ +int +do_auto_update(void) +{ + block_dev_desc_t *stor_dev; + long sz; + int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc; + char *env; + long start, end; + +#undef ERASE_EEPROM +#ifdef ERASE_EEPROM + int arr[18]; + memset(arr, 0, sizeof(arr)); + i2c_write_multiple(0x54, 64, 1, arr, sizeof(arr)); +#endif + au_usb_stor_curr_dev = -1; + /* start USB */ + if (usb_stop() < 0) { + debug ("usb_stop failed\n"); + return -1; + } + if (usb_init() < 0) { + debug ("usb_init failed\n"); + return -1; + } + /* + * check whether a storage device is attached (assume that it's + * a USB memory stick, since nothing else should be attached). + */ + au_usb_stor_curr_dev = usb_stor_scan(0); + if (au_usb_stor_curr_dev == -1) { + debug ("No device found. Not initialized?\n"); + return -1; + } + /* check whether it has a partition table */ + stor_dev = get_dev("usb", 0); + if (stor_dev == NULL) { + debug ("uknown device type\n"); + return -1; + } + if (fat_register_device(stor_dev, 1) != 0) { + debug ("Unable to use USB %d:%d for fatls\n", + au_usb_stor_curr_dev, 1); + return -1; + } + if (file_fat_detectfs() != 0) { + debug ("file_fat_detectfs failed\n"); + } + + /* initialize the array of file names */ + memset(aufile, 0, sizeof(aufile)); + aufile[IDX_PREPARE] = AU_PREPARE; + aufile[IDX_PREINST] = AU_PREINST; + aufile[IDX_FIRMWARE] = AU_FIRMWARE; + aufile[IDX_KERNEL] = AU_KERNEL; + aufile[IDX_APP] = AU_APP; + aufile[IDX_DISK] = AU_DISK; + aufile[IDX_POSTINST] = AU_POSTINST; + /* initialize the array of flash sizes */ + memset(ausize, 0, sizeof(ausize)); + ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST; + ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST; + ausize[IDX_APP] = (AU_FL_APP_ND + 1) - AU_FL_APP_ST; + ausize[IDX_DISK] = (AU_FL_DISK_ND + 1) - AU_FL_DISK_ST; + /* + * now check whether start and end are defined using environment + * variables. + */ + start = -1; + end = 0; + env = getenv("firmware_st"); + if (env != NULL) + start = simple_strtoul(env, NULL, 16); + env = getenv("firmware_nd"); + if (env != NULL) + end = simple_strtoul(env, NULL, 16); + if (start >= 0 && end && end > start) { + ausize[IDX_FIRMWARE] = (end + 1) - start; + aufl_layout[0].start = start; + aufl_layout[0].end = end; + } + start = -1; + end = 0; + env = getenv("kernel_st"); + if (env != NULL) + start = simple_strtoul(env, NULL, 16); + env = getenv("kernel_nd"); + if (env != NULL) + end = simple_strtoul(env, NULL, 16); + if (start >= 0 && end && end > start) { + ausize[IDX_KERNEL] = (end + 1) - start; + aufl_layout[1].start = start; + aufl_layout[1].end = end; + } + start = -1; + end = 0; + env = getenv("app_st"); + if (env != NULL) + start = simple_strtoul(env, NULL, 16); + env = getenv("app_nd"); + if (env != NULL) + end = simple_strtoul(env, NULL, 16); + if (start >= 0 && end && end > start) { + ausize[IDX_APP] = (end + 1) - start; + aufl_layout[2].start = start; + aufl_layout[2].end = end; + } + start = -1; + end = 0; + env = getenv("disk_st"); + if (env != NULL) + start = simple_strtoul(env, NULL, 16); + env = getenv("disk_nd"); + if (env != NULL) + end = simple_strtoul(env, NULL, 16); + if (start >= 0 && end && end > start) { + ausize[IDX_DISK] = (end + 1) - start; + aufl_layout[3].start = start; + aufl_layout[3].end = end; + } + /* make certain that HUSH is runnable */ + u_boot_hush_start(); + /* make sure that we see CTRL-C and save the old state */ + old_ctrlc = disable_ctrlc(0); + + bitmap_first = 0; + /* just loop thru all the possible files */ + for (i = 0; i < AU_MAXFILES; i++) { + /* just read the header */ + sz = file_fat_read(aufile[i], LOAD_ADDR, sizeof(image_header_t)); + debug ("read %s sz %ld hdr %d\n", + aufile[i], sz, sizeof(image_header_t)); + if (sz <= 0 || sz < sizeof(image_header_t)) { + debug ("%s not found\n", aufile[i]); + continue; + } + if (au_check_header_valid(i, sz) < 0) { + debug ("%s header not valid\n", aufile[i]); + continue; + } + sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ); + debug ("read %s sz %ld hdr %d\n", + aufile[i], sz, sizeof(image_header_t)); + if (sz <= 0 || sz <= sizeof(image_header_t)) { + debug ("%s not found\n", aufile[i]); + continue; + } + if (au_check_cksum_valid(i, sz) < 0) { + debug ("%s checksum not valid\n", aufile[i]); + continue; + } +#ifdef CONFIG_VFD + /* now that we have a valid file we can display the */ + /* bitmap. */ + if (bitmap_first == 0) { + env = getenv("bitmap2"); + if (env == NULL) { + trab_vfd(0); + } else { + /* not so simple - bitmap2 is supposed to */ + /* contain the address of the bitmap */ + env = (char *)simple_strtoul(env, NULL, 16); +/* NOTE: these are taken from vfd_logo.h. If that file changes then */ +/* these defines MUST also be updated! These may be wrong for bitmap2. */ +#define VFD_LOGO_WIDTH 112 +#define VFD_LOGO_HEIGHT 72 + /* must call transfer_pic directly */ + transfer_pic(3, env, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH); + } + bitmap_first = 1; + } +#endif + /* this is really not a good idea, but it's what the */ + /* customer wants. */ + cnt = 0; + got_ctrlc = 0; + do { + res = au_do_update(i, sz); + /* let the user break out of the loop */ + if (ctrlc() || had_ctrlc()) { + clear_ctrlc(); + if (res < 0) + got_ctrlc = 1; + break; + } + cnt++; +#ifdef AU_TEST_ONLY + } while (res < 0 && cnt < 3); + if (cnt < 3) +#else + } while (res < 0); +#endif + /* + * it doesn't make sense to update the EEPROM if the + * update was interrupted by the user due to errors. + */ + if (got_ctrlc == 0) + au_update_eeprom(i); + else + /* enable the power switch */ + *CPLD_VFD_BK &= ~POWER_OFF; + } + usb_stop(); + /* restore the old state */ + disable_ctrlc(old_ctrlc); + return 0; +} +#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c new file mode 100644 index 0000000..00eb385 --- /dev/null +++ b/board/trab/cmd_trab.c @@ -0,0 +1,895 @@ +/* + * (C) Copyright 2003 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#undef DEBUG + +#include +#include +#include +#include + +/* + * TRAB board specific commands. Especially commands for burn-in and function + * test. + */ +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +/* limits for valid range of VCC5V in mV */ +#define VCC5V_MIN 4500 +#define VCC5V_MAX 5500 + +/* + * Test strings for EEPROM test. Length of string 2 must not exceed length of + * string 1. Otherwise a buffer overrun could occur! + */ +#define EEPROM_TEST_STRING_1 "0987654321 :tset a si siht" +#define EEPROM_TEST_STRING_2 "this is a test: 1234567890" + +/* + * min/max limits for valid contact temperature during burn in test (in + * degree Centigrade * 100) + */ +#define MIN_CONTACT_TEMP -1000 +#define MAX_CONTACT_TEMP +9000 + +/* blinking frequency of status LED */ +#define LED_BLINK_FREQ 5 + +/* delay time between burn in cycles in seconds */ +#ifndef BURN_IN_CYCLE_DELAY /* if not defined in include/configs/trab.h */ +#define BURN_IN_CYCLE_DELAY 5 +#endif + +/* physical SRAM parameters */ +#define SRAM_ADDR 0x02000000 /* GCS1 */ +#define SRAM_SIZE 0x40000 /* 256 kByte */ + +/* CPLD-Register for controlling TRAB hardware functions */ +#define CPLD_BUTTONS ((volatile unsigned long *)0x04020000) +#define CPLD_FILL_LEVEL ((volatile unsigned long *)0x04008000) +#define CPLD_ROTARY_SWITCH ((volatile unsigned long *)0x04018000) +#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) + +/* I2C EEPROM device address */ +#define I2C_EEPROM_DEV_ADDR 0x54 + +/* EEPROM address map */ +#define EE_ADDR_TEST 192 +#define EE_ADDR_MAX_CYCLES 256 +#define EE_ADDR_STATUS 258 +#define EE_ADDR_PASS_CYCLES 259 +#define EE_ADDR_FIRST_ERROR_CYCLE 261 +#define EE_ADDR_FIRST_ERROR_NUM 263 +#define EE_ADDR_FIRST_ERROR_NAME 264 +#define EE_ADDR_ACT_CYCLE 280 + +/* Bit definitions for ADCCON */ +#define ADC_ENABLE_START 0x1 +#define ADC_READ_START 0x2 +#define ADC_STDBM 0x4 +#define ADC_INP_AIN0 (0x0 << 3) +#define ADC_INP_AIN1 (0x1 << 3) +#define ADC_INP_AIN2 (0x2 << 3) +#define ADC_INP_AIN3 (0x3 << 3) +#define ADC_INP_AIN4 (0x4 << 3) +#define ADC_INP_AIN5 (0x5 << 3) +#define ADC_INP_AIN6 (0x6 << 3) +#define ADC_INP_AIN7 (0x7 << 3) +#define ADC_PRSCEN 0x4000 +#define ADC_ECFLG 0x800 + +/* misc */ + +/* externals */ +extern int memory_post_tests (unsigned long start, unsigned long size); +extern int i2c_write (uchar, uint, int , uchar* , int); +extern int i2c_read (uchar, uint, int , uchar* , int); +extern void tsc2000_reg_init (void); +extern s32 tsc2000_contact_temp (void); +extern void spi_init(void); + +/* function declarations */ +int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int i2c_write_multiple (uchar chip, uint addr, int alen, + uchar *buffer, int len); +int i2c_read_multiple (uchar chip, uint addr, int alen, + uchar *buffer, int len); +int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* helper functions */ +static void adc_init (void); +static int adc_read (unsigned int channel); +static int read_dip (void); +static int read_vcc5v (void); +static int test_dip (void); +static int test_vcc5v (void); +static int test_rotary_switch (void); +static int test_sram (void); +static int test_eeprom (void); +static int test_contact_temp (void); +static void led_set (unsigned int); +static void led_blink (void); +static void led_init (void); +static void sdelay (unsigned long seconds); /* delay in seconds */ +static int dummy (void); +static int read_max_cycles(void); +static void test_function_table_init (void); +static void global_vars_init (void); +static int global_vars_write_to_eeprom (void); + +/* globals */ +u16 max_cycles; +u8 status; +u16 pass_cycles; +u16 first_error_cycle; +u8 first_error_num; +unsigned char first_error_name[16]; +u16 act_cycle; + +typedef struct test_function_s { + unsigned char *name; + int (*pf)(void); +} test_function_t; + +/* max number of Burn In Functions */ +#define BIF_MAX 6 + +/* table with burn in functions */ +test_function_t test_function[BIF_MAX]; + + +int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + int cycle_status; + + if (argc > 1) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + led_init (); + global_vars_init (); + test_function_table_init (); + spi_init (); + + if (global_vars_write_to_eeprom () != 0) { + printf ("%s: error writing global_vars to eeprom\n", + __FUNCTION__); + return (1); + } + + if (read_max_cycles () != 0) { + printf ("%s: error reading max_cycles from eeprom\n", + __FUNCTION__); + return (1); + } + + if (max_cycles == 0) { + printf ("%s: error, burn in max_cycles = 0\n", __FUNCTION__); + return (1); + } + + status = 0; + for (act_cycle = 1; act_cycle <= max_cycles; act_cycle++) { + + cycle_status = 0; + + /* + * avoid timestamp overflow problem after about 68 minutes of + * udelay() time. + */ + reset_timer_masked (); + for (i = 0; i < BIF_MAX; i++) { + + /* call test function */ + if ((*test_function[i].pf)() != 0) { + printf ("error in %s test\n", + test_function[i].name); + + /* is it the first error? */ + if (status == 0) { + status = 1; + first_error_cycle = act_cycle; + + /* do not use error_num 0 */ + first_error_num = i+1; + strncpy (first_error_name, + test_function[i].name, + sizeof (first_error_name)); + led_set (0); + } + cycle_status = 1; + } + } + /* were all tests of actual cycle OK? */ + if (cycle_status == 0) + pass_cycles++; + + /* set status LED if no error is occoured since yet */ + if (status == 0) + led_set (1); + + printf ("%s: cycle %d finished\n", __FUNCTION__, act_cycle); + + /* pause between cycles */ + sdelay (BURN_IN_CYCLE_DELAY); + } + + if (global_vars_write_to_eeprom () != 0) { + led_set (0); + printf ("%s: error writing global_vars to eeprom\n", + __FUNCTION__); + status = 1; + } + + if (status == 0) { + led_blink (); /* endless loop!! */ + return (0); + } else { + led_set (0); + return (1); + } +} + +U_BOOT_CMD( + burn_in, 1, 1, do_burn_in, + "burn_in - start burn-in test application on TRAB\n", + "\n" + " - start burn-in test application\n" + " The burn-in test could took a while to finish!\n" + " The content of the onboard EEPROM is modified!\n" +); + + +int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i, dip; + + if (argc > 1) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((dip = read_dip ()) == -1) { + return 1; + } + + for (i = 0; i < 4; i++) { + if ((dip & (1 << i)) == 0) + printf("0"); + else + printf("1"); + } + printf("\n"); + + return 0; +} + +U_BOOT_CMD( + dip, 1, 1, do_dip, + "dip - read dip switch on TRAB\n", + "\n" + " - read state of dip switch (S1) on TRAB board\n" + " read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\"\n" +); + + +int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int vcc5v; + + if (argc > 1) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((vcc5v = read_vcc5v ()) == -1) { + return (1); + } + + printf ("%d", (vcc5v / 1000)); + printf (".%d", (vcc5v % 1000) / 100); + printf ("%d V\n", (vcc5v % 100) / 10) ; + + return 0; +} + +U_BOOT_CMD( + vcc5v, 1, 1, do_vcc5v, + "vcc5v - read VCC5V on TRAB\n", + "\n" + " - read actual value of voltage VCC5V\n" +); + + +int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int contact_temp; + + if (argc > 1) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + spi_init (); + + contact_temp = tsc2000_contact_temp(); + printf ("%d degree C * 100\n", contact_temp) ; + + return 0; +} + +U_BOOT_CMD( + c_temp, 1, 1, do_contact_temp, + "c_temp - read contact temperature on TRAB\n", + "\n" + " - reads the onboard temperature (=contact temperature)\n" +); + + +int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc > 1) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1, + (unsigned char*) &status, 1)) { + return (1); + } + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1, + (unsigned char*) &pass_cycles, 2)) { + return (1); + } + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE, + 1, (unsigned char*) &first_error_cycle, 2)) { + return (1); + } + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM, + 1, (unsigned char*) &first_error_num, 1)) { + return (1); + } + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, + 1, first_error_name, + sizeof (first_error_name))) { + return (1); + } + + if (read_max_cycles () != 0) { + return (1); + } + + printf ("max_cycles = %d\n", max_cycles); + printf ("status = %d\n", status); + printf ("pass_cycles = %d\n", pass_cycles); + printf ("first_error_cycle = %d\n", first_error_cycle); + printf ("first_error_num = %d\n", first_error_num); + printf ("first_error_name = %.*s\n",(int) sizeof(first_error_name), + first_error_name); + + return 0; +} + +U_BOOT_CMD( + bis, 1, 1, do_burn_in_status, + "bis - print burn in status on TRAB\n", + "\n" + " - prints the status variables of the last burn in test\n" + " stored in the onboard EEPROM on TRAB board\n" +); + +static int read_dip (void) +{ + unsigned int result = 0; + int adc_val; + int i; + + /*********************************************************** + DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3): + SW1 - AIN4 + SW2 - AIN5 + SW3 - AIN6 + SW4 - AIN7 + + "On" DIP switch position short-circuits the voltage from + the input channel (i.e. '0' conversion result means "on"). + *************************************************************/ + + for (i = 7; i > 3; i--) { + + if ((adc_val = adc_read (i)) == -1) { + printf ("%s: Channel %d could not be read\n", + __FUNCTION__, i); + return (-1); + } + + /* + * Input voltage (switch open) is 1.8 V. + * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736 + * Set trigger at halve that value. + */ + if (adc_val < 368) + result |= (1 << (i-4)); + } + return (result); +} + + +static int read_vcc5v (void) +{ + s32 result; + + /* VCC5V is connected to channel 2 */ + + if ((result = adc_read (2)) == -1) { + printf ("%s: VCC5V could not be read\n", __FUNCTION__); + return (-1); + } + /* + * Calculate voltage value. Split in two parts because there is no + * floating point support. VCC5V is connected over an resistor divider: + * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K. + */ + result = result * 10 * 1000 / 1023; /* result in mV */ + + return (result); +} + + +static int test_dip (void) +{ + static int first_run = 1; + static int first_dip; + + if (first_run) { + if ((first_dip = read_dip ()) == -1) { + return (1); + } + first_run = 0; + debug ("%s: first_dip=%d\n", __FUNCTION__, first_dip); + } + if (first_dip != read_dip ()) { + return (1); + } else { + return (0); + } +} + + +static int test_vcc5v (void) +{ + int vcc5v; + + if ((vcc5v = read_vcc5v ()) == -1) { + return (1); + } + + if ((vcc5v > VCC5V_MAX) || (vcc5v < VCC5V_MIN)) { + printf ("%s: vcc5v[V/100]=%d\n", __FUNCTION__, vcc5v); + return (1); + } else { + return (0); + } +} + + +static int test_rotary_switch (void) +{ + static int first_run = 1; + static int first_rs; + + if (first_run) { + /* + * clear bits in CPLD, because they have random values after + * power-up or reset. + */ + *CPLD_ROTARY_SWITCH |= (1 << 16) | (1 << 17); + + first_rs = ((*CPLD_ROTARY_SWITCH >> 16) & 0x7); + first_run = 0; + debug ("%s: first_rs=%d\n", __FUNCTION__, first_rs); + } + + if (first_rs != ((*CPLD_ROTARY_SWITCH >> 16) & 0x7)) { + return (1); + } else { + return (0); + } +} + + +static int test_sram (void) +{ + return (memory_post_tests (SRAM_ADDR, SRAM_SIZE)); +} + + +static int test_eeprom (void) +{ + unsigned char temp[sizeof (EEPROM_TEST_STRING_1)]; + int result = 0; + + /* write test string 1, read back and verify */ + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, + EEPROM_TEST_STRING_1, + sizeof (EEPROM_TEST_STRING_1))) { + return (1); + } + + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, + temp, sizeof (EEPROM_TEST_STRING_1))) { + return (1); + } + + if (strcmp (temp, EEPROM_TEST_STRING_1) != 0) { + result = 1; + printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp); + } + + /* write test string 2, read back and verify */ + if (result == 0) { + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, + EEPROM_TEST_STRING_2, + sizeof (EEPROM_TEST_STRING_2))) { + return (1); + } + + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, + temp, sizeof (EEPROM_TEST_STRING_2))) { + return (1); + } + + if (strcmp (temp, EEPROM_TEST_STRING_2) != 0) { + result = 1; + printf ("%s: error; read str = \"%s\"\n", + __FUNCTION__, temp); + } + } + return (result); +} + + +static int test_contact_temp (void) +{ + int contact_temp; + + contact_temp = tsc2000_contact_temp (); + + if ((contact_temp < MIN_CONTACT_TEMP) + || (contact_temp > MAX_CONTACT_TEMP)) + return (1); + else + return (0); +} + + +int i2c_write_multiple (uchar chip, uint addr, int alen, + uchar *buffer, int len) +{ + int i; + + if (alen != 1) { + printf ("%s: addr len other than 1 not supported\n", + __FUNCTION__); + return (1); + } + + for (i = 0; i < len; i++) { + if (i2c_write (chip, addr+i, alen, buffer+i, 1)) { + printf ("%s: could not write to i2c device %d" + ", addr %d\n", __FUNCTION__, chip, addr); + return (1); + } +#if 0 + printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" + "%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i, + alen, buffer, i, buffer+i, buffer+i); +#endif + + udelay (30000); + } + return (0); +} + + +int i2c_read_multiple ( uchar chip, uint addr, int alen, + uchar *buffer, int len) +{ + int i; + + if (alen != 1) { + printf ("%s: addr len other than 1 not supported\n", + __FUNCTION__); + return (1); + } + + for (i = 0; i < len; i++) { + if (i2c_read (chip, addr+i, alen, buffer+i, 1)) { + printf ("%s: could not read from i2c device %#x" + ", addr %d\n", __FUNCTION__, chip, addr); + return (1); + } + } + return (0); +} + + +static int adc_read (unsigned int channel) +{ + int j = 1000; /* timeout value for wait loop in us */ + int result; + S3C2400_ADC *padc; + + padc = S3C2400_GetBase_ADC(); + channel &= 0x7; + + adc_init (); + + padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ + padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ + padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + + while (j--) { + if ((padc->ADCCON & ADC_ENABLE_START) == 0) + break; + udelay (1); + } + + if (j == 0) { + printf("%s: ADC timeout\n", __FUNCTION__); + padc->ADCCON |= ADC_STDBM; /* select standby mode */ + return -1; + } + + result = padc->ADCDAT & 0x3FF; + + padc->ADCCON |= ADC_STDBM; /* select standby mode */ + + debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, + (padc->ADCCON >> 3) & 0x7, result); + + /* + * Wait for ADC to be ready for next conversion. This delay value was + * estimated, because the datasheet does not specify a value. + */ + udelay (1000); + + return (result); +} + + +static void adc_init (void) +{ + S3C2400_ADC *padc; + + padc = S3C2400_GetBase_ADC(); + + padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ + padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + + /* + * Wait some time to avoid problem with very first call of + * adc_read(). Without this delay, sometimes the first read + * adc value is 0. Perhaps because the adjustment of prescaler + * takes some clock cycles? + */ + udelay (1000); + + return; +} + + +static void led_set (unsigned int state) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + led_init (); + + switch (state) { + case 0: /* turn LED off */ + gpio->PADAT |= (1 << 12); + break; + case 1: /* turn LED on */ + gpio->PADAT &= ~(1 << 12); + break; + default: + break; + } +} + +static void led_blink (void) +{ + led_init (); + + /* blink LED. This function does not return! */ + while (1) { + led_set (1); + udelay (1000000 / LED_BLINK_FREQ / 2); + led_set (0); + udelay (1000000 / LED_BLINK_FREQ / 2); + } +} + + +static void led_init (void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* configure GPA12 as output and set to High -> LED off */ + gpio->PACON &= ~(1 << 12); + gpio->PADAT |= (1 << 12); +} + + +static void sdelay (unsigned long seconds) +{ + unsigned long i; + + for (i = 0; i < seconds; i++) { + udelay (1000000); + } +} + + +static int global_vars_write_to_eeprom (void) +{ + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1, + (unsigned char*) &status, 1)) { + return (1); + } + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1, + (unsigned char*) &pass_cycles, 2)) { + return (1); + } + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE, + 1, (unsigned char*) &first_error_cycle, 2)) { + return (1); + } + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM, + 1, (unsigned char*) &first_error_num, 1)) { + return (1); + } + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, + 1, first_error_name, + sizeof(first_error_name))) { + return (1); + } + return (0); +} + +static void global_vars_init (void) +{ + status = 1; /* error */ + pass_cycles = 0; + first_error_cycle = 0; + first_error_num = 0; + first_error_name[0] = '\0'; + act_cycle = 0; + max_cycles = 0; +} + + +static void test_function_table_init (void) +{ + int i; + + for (i = 0; i < BIF_MAX; i++) + test_function[i].pf = dummy; + + /* + * the length of "name" must not exceed 16, including the '\0' + * termination. See also the EEPROM address map. + */ + test_function[0].pf = test_dip; + test_function[0].name = "dip"; + + test_function[1].pf = test_vcc5v; + test_function[1].name = "vcc5v"; + + test_function[2].pf = test_rotary_switch; + test_function[2].name = "rotary_switch"; + + test_function[3].pf = test_sram; + test_function[3].name = "sram"; + + test_function[4].pf = test_eeprom; + test_function[4].name = "eeprom"; + + test_function[5].pf = test_contact_temp; + test_function[5].name = "contact_temp"; +} + + +static int read_max_cycles (void) +{ + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_MAX_CYCLES, 1, + (unsigned char *) &max_cycles, 2) != 0) { + return (1); + } + + return (0); +} + +static int dummy(void) +{ + return (0); +} + +int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int contact_temp; + int delay = 0; +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + struct rtc_time tm; +#endif + + if (argc > 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (argc > 1) { + delay = simple_strtoul(argv[1], NULL, 10); + } + + spi_init (); + while (1) { + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + rtc_get (&tm); + printf ("%4d-%02d-%02d %2d:%02d:%02d - ", + tm.tm_year, tm.tm_mon, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec); +#endif + + contact_temp = tsc2000_contact_temp(); + printf ("%d\n", contact_temp) ; + + if (delay != 0) + /* + * reset timer to avoid timestamp overflow problem + * after about 68 minutes of udelay() time. + */ + reset_timer_masked (); + sdelay (delay); + } + + return 0; +} + +U_BOOT_CMD( + tlog, 2, 1, do_temp_log, + "tlog - log contact temperature [1/100 C] to console (endlessly)\n", + "delay\n" + " - contact temperature [1/100 C] is printed endlessly to console\n" + " specifies the seconds to wait between two measurements\n" + " For each measurment a timestamp is printeted\n" +); + +#endif /* CFG_CMD_BSP */ diff --git a/board/trab/config.mk b/board/trab/config.mk new file mode 100644 index 0000000..f2411d0 --- /dev/null +++ b/board/trab/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# TRAB board with S3C2400X (arm920t) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# + +# +# TRAB has 1 bank of 16 MB or 32 MB DRAM +# +# 0c00'0000 to 0e00'0000 +# +# Linux-Kernel is expected to be at 0c00'8000, entry 0c00'8000 +# +# we load ourself to 0CF0'0000 / 0DF0'0000 +# +# download areas is 0C80'0000 +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0x0DF40000 +endif diff --git a/board/trab/flash.c b/board/trab/flash.c new file mode 100644 index 0000000..b4435e3 --- /dev/null +++ b/board/trab/flash.c @@ -0,0 +1,568 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include + +static ulong flash_get_size (vu_long *addr, flash_info_t *info); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +#define CMD_READ_ARRAY 0x00F000F0 +#define CMD_UNLOCK1 0x00AA00AA +#define CMD_UNLOCK2 0x00550055 +#define CMD_ERASE_SETUP 0x00800080 +#define CMD_ERASE_CONFIRM 0x00300030 +#define CMD_PROGRAM 0x00A000A0 +#define CMD_UNLOCK_BYPASS 0x00200020 +#define CMD_READ_MANF_ID 0x00900090 +#define CMD_UNLOCK_BYPASS_RES1 0x00900090 +#define CMD_UNLOCK_BYPASS_RES2 0x00000000 + +#define MEM_FLASH_ADDR (*(volatile u32 *)CFG_FLASH_BASE) +#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2))) +#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2))) + +#define BIT_ERASE_DONE 0x00800080 +#define BIT_RDY_MASK 0x00800080 +#define BIT_PROGRAM_ERROR 0x00200020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i=0; iflash_id = FLASH_UNKNOWN; + + size += flash_get_size (CFG_FLASH_BASE, info); + + if (i == 0) + flashbase = CFG_FLASH_BASE; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < info->sector_count; j++) { + + info->protect[j] = 0; + info->start[j] = flashbase; + + switch (info->flash_id & FLASH_TYPEMASK) { + case (FLASH_AM320B & FLASH_TYPEMASK): + case (FLASH_MXLV320B & FLASH_TYPEMASK): + /* Boot sector type: 8 x 8 + N x 128 kB */ + flashbase += (j < 8) ? 0x4000 : 0x20000; + break; + case (FLASH_AM640U & FLASH_TYPEMASK): + /* Uniform sector type: 128 kB */ + flashbase += 0x20000; + break; + default: + printf ("## Bad flash chip type 0x%04lX\n", + info->flash_id & FLASH_TYPEMASK); + } + } + } + + /* + * Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (FLASH_MAN_AMD & FLASH_VENDMASK): + printf ("AMD "); break; + case (FLASH_MAN_FUJ & FLASH_VENDMASK): + printf ("FUJITSU "); break; + case (FLASH_MAN_MX & FLASH_VENDMASK): + printf ("MACRONIX "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (FLASH_AM320B & FLASH_TYPEMASK): + printf ("2x Am29LV320DB (32Mbit)\n"); + break; + case (FLASH_MXLV320B & FLASH_TYPEMASK): + printf ("2x MX29LV320DB (32Mbit)\n"); + break; + case (FLASH_AM640U & FLASH_TYPEMASK): + printf ("2x Am29LV640D (64Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: ; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + +#if 0 + int cflag; +#endif + int iflag, prot, sect; + int rc = ERR_OK; + int chip1, chip2; + + debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case (FLASH_MAN_AMD & FLASH_VENDMASK): break; /* OK */ + case (FLASH_MAN_FUJ & FLASH_VENDMASK): break; /* OK */ + case (FLASH_MAN_MX & FLASH_VENDMASK): break; /* OK */ + default: + debug ("## flash_erase: unknown manufacturer\n"); + return (ERR_UNKNOWN_FLASH_VENDOR); + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ +#if 0 + cflag = icache_status (); + icache_disable (); +#endif + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + + debug ("Erasing sector %2d @ %08lX... ", + sect, info->start[sect]); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = chip2 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) + chip1 = ERR; + + if (!chip2 && (result >> 16) & BIT_ERASE_DONE) + chip2 = READY; + + if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) + chip2 = ERR; + + } while (!chip1 || !chip2); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR || chip2 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + } + } + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + +#if 0 + if (cflag) + icache_enable (); +#endif + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_word (flash_info_t * info, ulong dest, + ulong data) +{ + vu_long *addr = (vu_long *) dest; + ulong result; + int rc = ERR_OK; + +#if 0 + int cflag; +#endif + int iflag; + int chip1, chip2; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ +#if 0 + cflag = icache_status (); + icache_disable (); +#endif + iflag = disable_interrupts (); + + *addr = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + chip1 = chip2 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { + result = *addr; + + if ((result & 0x80) == (data & 0x80)) + chip1 = READY; + else + chip1 = ERR; + } + + if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) + chip2 = READY; + + if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) { + result = *addr; + + if ((result & (0x80 << 16)) == (data & (0x80 << 16))) + chip2 = READY; + else + chip2 = ERR; + } + + } while (!chip1 || !chip2); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || chip2 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + +#if 0 + if (cflag) + icache_enable (); +#endif + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int l; + int i, rc; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + + if ((rc = write_word (info, wp, data)) != 0) { + goto Done; + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + if (((ulong)src) & 0x3) { + for (i = 0; i < 4; i++) { + ((char *)&data)[i] = ((vu_char *)src)[i]; + } + } + else { + data = *((vu_long *) src); + } + + if ((rc = write_word (info, wp, data)) != 0) { + goto Done; + } + src += 4; + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + rc = ERR_OK; + goto Done; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 24); + } + + rc = write_word (info, wp, data); + + Done: + + MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES1; + MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES2; + + return (rc); +} + +/*----------------------------------------------------------------------- + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + ulong value; + + /* Write auto select command sequence and read Manufacturer ID */ + addr[0x0555] = CMD_UNLOCK1; + addr[0x02AA] = CMD_UNLOCK2; + addr[0x0555] = CMD_READ_MANF_ID; + + value = addr[0]; + + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case MX_MANUFACT: + info->flash_id = FLASH_MAN_MX; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = 0x00FF00FF; /* restore read mode */ + debug ("## flash_init: unknown manufacturer\n"); + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value) { + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00800000; + + addr[0] = 0x00FF00FF; /* restore read mode */ + break; /* => 8 MB */ + + case AMD_ID_LV640U: + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x01000000; + + addr[0] = 0x00F000F0; /* restore read mode */ + break; /* => 16 MB */ + + case MX_ID_LV320B: + info->flash_id += FLASH_MXLV320B; + info->sector_count = 71; + info->size = 0x00800000; + + addr[0] = 0x00FF00FF; /* restore read mode */ + break; /* => 8 MB */ + + default: + debug ("## flash_init: unknown flash chip\n"); + info->flash_id = FLASH_UNKNOWN; + addr[0] = 0x00FF00FF; /* restore read mode */ + return (0); /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + return (info->size); +} diff --git a/board/trab/lowlevel_init.S b/board/trab/lowlevel_init.S new file mode 100644 index 0000000..128ae7e --- /dev/null +++ b/board/trab/lowlevel_init.S @@ -0,0 +1,182 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the TRAB board by + * (C) Copyright 2002-2003 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +/* + * + * Copied from linux/arch/arm/boot/compressed/head-s3c2400.S + * + * Copyright (C) 2001 Samsung Electronics by chc, 010406 + * + * TRAB specific tweaks. + * + */ + +/* memory controller */ +#define BWSCON 0x14000000 + +/* Bank0 */ +#define B0_Tacs 0x1 /* 1 clk */ +#define B0_Tcos 0x1 /* 1 clk */ +#define B0_Tacc 0x5 /* 8 clk */ +#define B0_Tcoh 0x1 /* 1 clk */ +#define B0_Tah 0x1 /* 1 clk */ +#define B0_Tacp 0x0 +#define B0_PMC 0x0 /* normal */ + +/* Bank1 - SRAM */ +#define B1_Tacs 0x1 /* 1 clk */ +#define B1_Tcos 0x1 /* 1 clk */ +#define B1_Tacc 0x5 /* 8 clk */ +#define B1_Tcoh 0x1 /* 1 clk */ +#define B1_Tah 0x1 /* 1 clk */ +#define B1_Tacp 0x0 +#define B1_PMC 0x0 /* normal */ + +/* Bank2 - CPLD */ +#define B2_Tacs 0x1 /* 1 clk */ +#define B2_Tcos 0x1 /* 1 clk */ +#define B2_Tacc 0x5 /* 8 clk */ +#define B2_Tcoh 0x1 /* 1 clk */ +#define B2_Tah 0x1 /* 1 clk */ +#define B2_Tacp 0x0 +#define B2_PMC 0x0 /* normal */ + +/* Bank3 - setup for the cs8900 */ +#define B3_Tacs 0x3 /* 4 clk */ +#define B3_Tcos 0x3 /* 4 clk */ +#define B3_Tacc 0x7 /* 14 clk */ +#define B3_Tcoh 0x1 /* 1 clk */ +#define B3_Tah 0x0 /* 0 clk */ +#define B3_Tacp 0x3 /* 6 clk */ +#define B3_PMC 0x0 /* normal */ + +/* Bank4 */ +#define B4_Tacs 0x0 /* 0 clk */ +#define B4_Tcos 0x0 /* 0 clk */ +#define B4_Tacc 0x7 /* 14 clk */ +#define B4_Tcoh 0x0 /* 0 clk */ +#define B4_Tah 0x0 /* 0 clk */ +#define B4_Tacp 0x0 +#define B4_PMC 0x0 /* normal */ + +/* Bank5 */ +#define B5_Tacs 0x0 /* 0 clk */ +#define B5_Tcos 0x0 /* 0 clk */ +#define B5_Tacc 0x7 /* 14 clk */ +#define B5_Tcoh 0x0 /* 0 clk */ +#define B5_Tah 0x0 /* 0 clk */ +#define B5_Tacp 0x0 +#define B5_PMC 0x0 /* normal */ + +#ifndef CONFIG_RAM_16MB /* 32 MB RAM */ +/* Bank6 */ +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x0 /* 2clk */ +#define B6_SCAN 0x1 /* 9 bit */ + +/* Bank7 */ +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x0 /* 2clk */ +#define B7_SCAN 0x1 /* 9 bit */ +#else /* CONFIG_RAM_16MB = 16 MB RAM */ +/* Bank6 */ +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 /* 2clk */ +#define B6_SCAN 0x0 /* 8 bit */ + +/* Bank7 */ +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 2clk */ +#define B7_SCAN 0x0 /* 8 bit */ +#endif /* CONFIG_RAM_16MB */ + +/* refresh parameter */ +#define REFEN 0x1 /* enable refresh */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ +#define Trp 0x0 /* 2 clk */ +#define Trc 0x3 /* 7 clk */ +#define Tchr 0x2 /* 3 clk */ + +#ifdef CONFIG_TRAB_50MHZ +#define REFCNT 1269 /* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */ +#else +#define REFCNT 1011 /* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */ +#endif + + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #52 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word 0x2211d644 /* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */ + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */ + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */ + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */ + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */ + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */ + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */ + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */ + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */ + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) +#ifndef CONFIG_RAM_16MB /* 32 MB RAM */ + .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */ +#else /* CONFIG_RAM_16MB = 16 MB RAM */ + .word 0x17 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */ +#endif /* CONFIG_RAM_16MB */ + .word 0x20 /* MRSR6, CL=2clk */ + .word 0x20 /* MRSR7 */ diff --git a/board/trab/memory.c b/board/trab/memory.c new file mode 100644 index 0000000..9104413 --- /dev/null +++ b/board/trab/memory.c @@ -0,0 +1,485 @@ +/* + * (C) Copyright 2002-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* Memory test + * + * General observations: + * o The recommended test sequence is to test the data lines: if they are + * broken, nothing else will work properly. Then test the address + * lines. Finally, test the cells in the memory now that the test + * program knows that the address and data lines work properly. + * This sequence also helps isolate and identify what is faulty. + * + * o For the address line test, it is a good idea to use the base + * address of the lowest memory location, which causes a '1' bit to + * walk through a field of zeros on the address lines and the highest + * memory location, which causes a '0' bit to walk through a field of + * '1's on the address line. + * + * o Floating buses can fool memory tests if the test routine writes + * a value and then reads it back immediately. The problem is, the + * write will charge the residual capacitance on the data bus so the + * bus retains its state briefely. When the test program reads the + * value back immediately, the capacitance of the bus can allow it + * to read back what was written, even though the memory circuitry + * is broken. To avoid this, the test program should write a test + * pattern to the target location, write a different pattern elsewhere + * to charge the residual capacitance in a differnt manner, then read + * the target location back. + * + * o Always read the target location EXACTLY ONCE and save it in a local + * variable. The problem with reading the target location more than + * once is that the second and subsequent reads may work properly, + * resulting in a failed test that tells the poor technician that + * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which + * doesn't help him one bit and causes puzzled phone calls. Been there, + * done that. + * + * Data line test: + * --------------- + * This tests data lines for shorts and opens by forcing adjacent data + * to opposite states. Because the data lines could be routed in an + * arbitrary manner the must ensure test patterns ensure that every case + * is tested. By using the following series of binary patterns every + * combination of adjacent bits is test regardless of routing. + * + * ...101010101010101010101010 + * ...110011001100110011001100 + * ...111100001111000011110000 + * ...111111110000000011111111 + * + * Carrying this out, gives us six hex patterns as follows: + * + * 0xaaaaaaaaaaaaaaaa + * 0xcccccccccccccccc + * 0xf0f0f0f0f0f0f0f0 + * 0xff00ff00ff00ff00 + * 0xffff0000ffff0000 + * 0xffffffff00000000 + * + * To test for short and opens to other signals on our boards, we + * simply test with the 1's complemnt of the paterns as well, resulting + * in twelve patterns total. + * + * After writing a test pattern. a special pattern 0x0123456789ABCDEF is + * written to a different address in case the data lines are floating. + * Thus, if a byte lane fails, you will see part of the special + * pattern in that byte lane when the test runs. For example, if the + * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa + * (for the 'a' test pattern). + * + * Address line test: + * ------------------ + * This function performs a test to verify that all the address lines + * hooked up to the RAM work properly. If there is an address line + * fault, it usually shows up as two different locations in the address + * map (related by the faulty address line) mapping to one physical + * memory storage location. The artifact that shows up is writing to + * the first location "changes" the second location. + * + * To test all address lines, we start with the given base address and + * xor the address with a '1' bit to flip one address line. For each + * test, we shift the '1' bit left to test the next address line. + * + * In the actual code, we start with address sizeof(ulong) since our + * test pattern we use is a ulong and thus, if we tried to test lower + * order address bits, it wouldn't work because our pattern would + * overwrite itself. + * + * Example for a 4 bit address space with the base at 0000: + * 0000 <- base + * 0001 <- test 1 + * 0010 <- test 2 + * 0100 <- test 3 + * 1000 <- test 4 + * Example for a 4 bit address space with the base at 0010: + * 0010 <- base + * 0011 <- test 1 + * 0000 <- (below the base address, skipped) + * 0110 <- test 2 + * 1010 <- test 3 + * + * The test locations are successively tested to make sure that they are + * not "mirrored" onto the base address due to a faulty address line. + * Note that the base and each test location are related by one address + * line flipped. Note that the base address need not be all zeros. + * + * Memory tests 1-4: + * ----------------- + * These tests verify RAM using sequential writes and reads + * to/from RAM. There are several test cases that use different patterns to + * verify RAM. Each test case fills a region of RAM with one pattern and + * then reads the region back and compares its contents with the pattern. + * The following patterns are used: + * + * 1a) zero pattern (0x00000000) + * 1b) negative pattern (0xffffffff) + * 1c) checkerboard pattern (0x55555555) + * 1d) checkerboard pattern (0xaaaaaaaa) + * 2) bit-flip pattern ((1 << (offset % 32)) + * 3) address pattern (offset) + * 4) address pattern (~offset) + * + * Being run in normal mode, the test verifies only small 4Kb + * regions of RAM around each 1Mb boundary. For example, for 64Mb + * RAM the following areas are verified: 0x00000000-0x00000800, + * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- + * 0x04000000. If the test is run in slow-test mode, it verifies + * the whole RAM. + */ + +/* #ifdef CONFIG_POST */ + +#include +#include + +/* #if CONFIG_POST & CFG_POST_MEMORY */ + +/* + * Define INJECT_*_ERRORS for testing error detection in the presence of + * _good_ hardware. + */ +#undef INJECT_DATA_ERRORS +#undef INJECT_ADDRESS_ERRORS + +#ifdef INJECT_DATA_ERRORS +#warning "Injecting data line errors for testing purposes" +#endif + +#ifdef INJECT_ADDRESS_ERRORS +#warning "Injecting address line errors for testing purposes" +#endif + + +/* + * This function performs a double word move from the data at + * the source pointer to the location at the destination pointer. + * This is helpful for testing memory on processors which have a 64 bit + * wide data bus. + * + * On those PowerPC with FPU, use assembly and a floating point move: + * this does a 64 bit move. + * + * For other processors, let the compiler generate the best code it can. + */ +static void move64(unsigned long long *src, unsigned long long *dest) +{ +#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) + asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : : "fr0" ); /* Clobbers fr0 */ + return; +#else + *dest = *src; +#endif +} + +/* + * This is 64 bit wide test patterns. Note that they reside in ROM + * (which presumably works) and the tests write them to RAM which may + * not work. + * + * The "otherpattern" is written to drive the data bus to values other + * than the test pattern. This is for detecting floating bus lines. + * + */ +const static unsigned long long pattern[] = { + 0xaaaaaaaaaaaaaaaaULL, + 0xccccccccccccccccULL, + 0xf0f0f0f0f0f0f0f0ULL, + 0xff00ff00ff00ff00ULL, + 0xffff0000ffff0000ULL, + 0xffffffff00000000ULL, + 0x00000000ffffffffULL, + 0x0000ffff0000ffffULL, + 0x00ff00ff00ff00ffULL, + 0x0f0f0f0f0f0f0f0fULL, + 0x3333333333333333ULL, + 0x5555555555555555ULL, +}; +const unsigned long long otherpattern = 0x0123456789abcdefULL; + + +static int memory_post_dataline(unsigned long long * pmem) +{ + unsigned long long temp64; + int num_patterns = sizeof(pattern)/ sizeof(pattern[0]); + int i; + unsigned int hi, lo, pathi, patlo; + int ret = 0; + + for ( i = 0; i < num_patterns; i++) { + move64((unsigned long long *)&(pattern[i]), pmem++); + /* + * Put a different pattern on the data lines: otherwise they + * may float long enough to read back what we wrote. + */ + move64((unsigned long long *)&otherpattern, pmem--); + move64(pmem, &temp64); + +#ifdef INJECT_DATA_ERRORS + temp64 ^= 0x00008000; +#endif + + if (temp64 != pattern[i]){ + pathi = (pattern[i]>>32) & 0xffffffff; + patlo = pattern[i] & 0xffffffff; + + hi = (temp64>>32) & 0xffffffff; + lo = temp64 & 0xffffffff; + + printf ("Memory (date line) error at %08lx, " + "wrote %08x%08x, read %08x%08x !\n", + (ulong)pmem, pathi, patlo, hi, lo); + ret = -1; + } + } + return ret; +} + +static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) +{ + ulong *target; + ulong *end; + ulong readback; + ulong xor; + int ret = 0; + + end = (ulong *)((ulong)base + size); /* pointer arith! */ + xor = 0; + for(xor = sizeof(ulong); xor > 0; xor <<= 1) { + target = (ulong *)((ulong)testaddr ^ xor); + if((target >= base) && (target < end)) { + *testaddr = ~*target; + readback = *target; + +#ifdef INJECT_ADDRESS_ERRORS + if(xor == 0x00008000) { + readback = *testaddr; + } +#endif + if(readback == *testaddr) { + printf ("Memory (address line) error at %08lx<->%08lx, " + "XOR value %08lx !\n", + (ulong)testaddr, (ulong)target, + xor); + ret = -1; + } + } + } + return ret; +} + +static int memory_post_test1 (unsigned long start, + unsigned long size, + unsigned long val) +{ + unsigned long i; + ulong *mem = (ulong *) start; + ulong readback; + int ret = 0; + + for (i = 0; i < size / sizeof (ulong); i++) { + mem[i] = val; + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { + readback = mem[i]; + if (readback != val) { + printf ("Memory error at %08lx, " + "wrote %08lx, read %08lx !\n", + (ulong)(mem + i), val, readback); + + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + return ret; +} + +static int memory_post_test2 (unsigned long start, unsigned long size) +{ + unsigned long i; + ulong *mem = (ulong *) start; + ulong readback; + int ret = 0; + + for (i = 0; i < size / sizeof (ulong); i++) { + mem[i] = 1 << (i % 32); + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { + readback = mem[i]; + if (readback != (1 << (i % 32))) { + printf ("Memory error at %08lx, " + "wrote %08x, read %08lx !\n", + (ulong)(mem + i), 1 << (i % 32), readback); + + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + return ret; +} + +static int memory_post_test3 (unsigned long start, unsigned long size) +{ + unsigned long i; + ulong *mem = (ulong *) start; + ulong readback; + int ret = 0; + + for (i = 0; i < size / sizeof (ulong); i++) { + mem[i] = i; + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { + readback = mem[i]; + if (readback != i) { + printf ("Memory error at %08lx, " + "wrote %08lx, read %08lx !\n", + (ulong)(mem + i), i, readback); + + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + return ret; +} + +static int memory_post_test4 (unsigned long start, unsigned long size) +{ + unsigned long i; + ulong *mem = (ulong *) start; + ulong readback; + int ret = 0; + + for (i = 0; i < size / sizeof (ulong); i++) { + mem[i] = ~i; + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { + readback = mem[i]; + if (readback != ~i) { + printf ("Memory error at %08lx, " + "wrote %08lx, read %08lx !\n", + (ulong)(mem + i), ~i, readback); + + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + return ret; +} + +int memory_post_tests (unsigned long start, unsigned long size) +{ + int ret = 0; + + if (ret == 0) + ret = memory_post_dataline ((long long *)start); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_addrline ((long *)start, (long *)start, size); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_addrline ((long *)(start + size - 8), + (long *)start, size); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test1 (start, size, 0x00000000); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test1 (start, size, 0xffffffff); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test1 (start, size, 0x55555555); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test1 (start, size, 0xaaaaaaaa); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test2 (start, size); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test3 (start, size); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test4 (start, size); + WATCHDOG_RESET (); + + return ret; +} + +#if 0 +int memory_post_test (int flags) +{ + int ret = 0; + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; + unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? + 256 << 20 : bd->bi_memsize) - (1 << 20); + + + if (flags & POST_SLOWTEST) { + ret = memory_post_tests (CFG_SDRAM_BASE, memsize); + } else { /* POST_NORMAL */ + + unsigned long i; + + for (i = 0; i < (memsize >> 20) && ret == 0; i++) { + if (ret == 0) + ret = memory_post_tests (i << 20, 0x800); + if (ret == 0) + ret = memory_post_tests ((i << 20) + 0xff800, 0x800); + } + } + + return ret; +} +#endif /* 0 */ + +/* #endif */ /* CONFIG_POST & CFG_POST_MEMORY */ +/* #endif */ /* CONFIG_POST */ diff --git a/board/trab/rs485.c b/board/trab/rs485.c new file mode 100644 index 0000000..2aedd2d --- /dev/null +++ b/board/trab/rs485.c @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2003 + * Martin Krause, TQ-Systems GmbH, + * + * Based on cpu/arm920t/serial.c, by Gary Jennejohn + * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include "rs485.h" + +static void rs485_setbrg (void); +static void rs485_cfgio (void); +static void set_rs485re(unsigned char rs485re_state); +static void set_rs485de(unsigned char rs485de_state); +static void rs485_setbrg (void); +#ifdef NOT_USED +static void trab_rs485_disable_tx(void); +static void trab_rs485_disable_rx(void); +#endif + +#define UART_NR S3C24X0_UART1 + +/* CPLD-Register for controlling TRAB hardware functions */ +#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) + +static void rs485_setbrg (void) +{ + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + int i; + unsigned int reg = 0; + + /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ + /* reg = (33000000 / (16 * gd->baudrate)) - 1; */ + reg = (33000000 / (16 * 38400)) - 1; + + /* FIFO enable, Tx/Rx FIFO clear */ + uart->UFCON = 0x07; + uart->UMCON = 0x0; + /* Normal,No parity,1 stop,8 bit */ + uart->ULCON = 0x3; + /* + * tx=level,rx=edge,disable timeout int.,enable rx error int., + * normal,interrupt or polling + */ + uart->UCON = 0x245; + uart->UBRDIV = reg; + + for (i = 0; i < 100; i++); +} + +static void rs485_cfgio (void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + gpio->PFCON &= ~(0x3 << 2); + gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */ + + gpio->PFCON &= ~(0x3 << 6); + gpio->PFCON |= (0x2 << 6); /* configure GPF3 as TXD1 */ + + gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */ + gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */ + + gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */ +} + +/* + * Initialise the rs485 port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int rs485_init (void) +{ + rs485_cfgio (); + rs485_setbrg (); + + return (0); +} + +/* + * Read a single byte from the rs485 port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int rs485_getc (void) +{ + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + + /* wait for character to arrive */ + while (!(uart->UTRSTAT & 0x1)); + + return uart->URXH & 0xff; +} + +/* + * Output a single byte to the rs485 port. + */ +void rs485_putc (const char c) +{ + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + + /* wait for room in the tx FIFO */ + while (!(uart->UTRSTAT & 0x2)); + + uart->UTXH = c; + + /* If \n, also do \r */ + if (c == '\n') + rs485_putc ('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int rs485_tstc (void) +{ + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + + return uart->UTRSTAT & 0x1; +} + +void rs485_puts (const char *s) +{ + while (*s) { + rs485_putc (*s++); + } +} + + +/* + * State table: + * RE DE Result + * 1 1 XMIT + * 0 0 RCV + * 1 0 Shutdown + */ + +/* function that controls the receiver enable for the rs485 */ +/* rs485re_state reflects the level (0/1) of the RE pin */ + +static void set_rs485re(unsigned char rs485re_state) +{ + if(rs485re_state) + *CPLD_RS485_RE = 0x010000; + else + *CPLD_RS485_RE = 0x0; +} + +/* function that controls the sender enable for the rs485 */ +/* rs485de_state reflects the level (0/1) of the DE pin */ + +static void set_rs485de(unsigned char rs485de_state) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* This is on PORT A bit 11 */ + if(rs485de_state) + gpio->PADAT |= (1 << 11); + else + gpio->PADAT &= ~(1 << 11); +} + + +void trab_rs485_enable_tx(void) +{ + set_rs485de(1); + set_rs485re(1); +} + +void trab_rs485_enable_rx(void) +{ + set_rs485re(0); + set_rs485de(0); +} + +#ifdef NOT_USED +static void trab_rs485_disable_tx(void) +{ + set_rs485de(0); +} + +static void trab_rs485_disable_rx(void) +{ + set_rs485re(1); +} +#endif diff --git a/board/trab/rs485.h b/board/trab/rs485.h new file mode 100644 index 0000000..d4a008a --- /dev/null +++ b/board/trab/rs485.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2003 + * Martin Krause, TQ-Systems GmbH, + * + * Based on cpu/arm920t/serial.c, by Gary Jennejohn + * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef _RS485_H_ +#define _RS485_H_ + +#include + +int rs485_init (void); +int rs485_getc (void); +void rs485_putc (const char c); +int rs485_tstc (void); +void rs485_puts (const char *s); +void trab_rs485_enable_tx(void); +void trab_rs485_enable_rx(void); + +#endif /* _RS485_H_ */ diff --git a/board/trab/trab.c b/board/trab/trab.c new file mode 100644 index 0000000..e8dfd2c --- /dev/null +++ b/board/trab/trab.c @@ -0,0 +1,412 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#ifdef CFG_BRIGHTNESS +static void spi_init(void); +static void wait_transmit_done(void); +static void tsc2000_write(unsigned int page, unsigned int reg, + unsigned int data); +static void tsc2000_set_brightness(void); +#endif +#ifdef CONFIG_MODEM_SUPPORT +static int key_pressed(void); +extern void disable_putc(void); +extern int do_mdm_init; /* defined in common/main.c */ + +/* + * We need a delay of at least 500 us after turning on the VFD clock + * before we can read any useful information for the CPLD controlling + * the keyboard switches. Let's play safe and wait 5 ms. The problem + * is that timers are not available yet, so we use a manually timed + * loop. + */ +#define KBD_MDELAY 5000 +static void udelay_no_timer (int usec) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + int delay = usec * 3; + + for (i = 0; i < delay; i ++) gd->bd->bi_arch_number = MACH_TYPE_TRAB; +} +#endif /* CONFIG_MODEM_SUPPORT */ + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init () +{ +#if defined(CONFIG_VFD) + extern int vfd_init_clocks(void); +#endif + DECLARE_GLOBAL_DATA_PTR; + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* memory and cpu-speed are setup before relocation */ +#ifdef CONFIG_TRAB_50MHZ + /* change the clock to be 50 MHz 1:1:1 */ + /* MDIV:0x5c PDIV:4 SDIV:2 */ + clk_power->MPLLCON = 0x5c042; + clk_power->CLKDIVN = 0; +#else + /* change the clock to be 133 MHz 1:2:4 */ + /* MDIV:0x7d PDIV:4 SDIV:1 */ + clk_power->MPLLCON = 0x7d041; + clk_power->CLKDIVN = 3; +#endif + + /* set up the I/O ports */ + gpio->PACON = 0x3ffff; + gpio->PBCON = 0xaaaaaaaa; + gpio->PBUP = 0xffff; + /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */ + /* 00, 10, 10, 10, 10, 10, 10 */ + gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10); +#ifdef CONFIG_HWFLOW + /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */ + gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5); +#else + /* do not pull up RXD0, RXD1, TXD0, TXD1 */ + gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3); +#endif + gpio->PGCON = 0x0; + gpio->PGUP = 0x0; + gpio->OPENCR= 0x0; + + /* suppress flicker of the VFDs */ + gpio->MISCCR = 0x40; + gpio->PFCON |= (2<<12); + + gd->bd->bi_arch_number = MACH_TYPE_TRAB; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x0c000100; + + /* Make sure both buzzers are turned off */ + gpio->PDCON |= 0x5400; + gpio->PDDAT &= ~0xE0; + +#ifdef CONFIG_VFD + vfd_init_clocks(); +#endif /* CONFIG_VFD */ + +#ifdef CONFIG_MODEM_SUPPORT + udelay_no_timer (KBD_MDELAY); + + if (key_pressed()) { + disable_putc(); /* modem doesn't understand banner etc */ + do_mdm_init = 1; + } +#endif /* CONFIG_MODEM_SUPPORT */ + +#ifdef CONFIG_DRIVER_S3C24X0_I2C + /* Configure I/O ports PG5 und PG6 for I2C */ + gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00; +#endif /* CONFIG_DRIVER_S3C24X0_I2C */ + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/*----------------------------------------------------------------------- + * Keyboard Controller + */ + +/* Maximum key number */ +#define KEYBD_KEY_NUM 4 + +#define KBD_DATA (((*(volatile ulong *)0x04020000) >> 16) & 0xF) + +static uchar *key_match (ulong); + +int misc_init_r (void) +{ + ulong kbd_data = KBD_DATA; + uchar keybd_env[KEYBD_KEY_NUM + 1]; + uchar *str; + int i; + +#ifdef CONFIG_AUTO_UPDATE + extern int do_auto_update(void); + /* this has priority over all else */ + do_auto_update(); +#endif + + for (i = 0; i < KEYBD_KEY_NUM; ++i) { + keybd_env[i] = '0' + ((kbd_data >> i) & 1); + } + keybd_env[i] = '\0'; + debug ("** Setting keybd=\"%s\"\n", keybd_env); + setenv ("keybd", keybd_env); + + str = strdup (key_match (kbd_data)); /* decode keys */ + +#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ + debug ("** Setting preboot=\"%s\"\n", str); + setenv ("preboot", str); /* set or delete definition */ +#endif /* CONFIG_PREBOOT */ + if (str != NULL) { + free (str); + } + +#ifdef CFG_BRIGHTNESS + tsc2000_set_brightness(); +#endif + return (0); +} + +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +static int compare_magic (ulong kbd_data, uchar *str) +{ + uchar key_mask; + + debug ("compare_magic: kbd: %04lx str: \"%s\"\n",kbd_data,str); + for (; *str; str++) + { + uchar c = *str - '1'; + + if (c >= KEYBD_KEY_NUM) /* bad key number */ + return -1; + + key_mask = 1 << c; + + if (!(kbd_data & key_mask)) { /* key not pressed */ + debug ( "compare_magic: " + "kbd: %04lx mask: %04lx - key not pressed\n", + kbd_data, key_mask ); + return -1; + } + + kbd_data &= ~key_mask; + } + + if (kbd_data) { /* key(s) not released */ + debug ( "compare_magic: " + "kbd: %04lx - key(s) not released\n", kbd_data); + return -1; + } + + return 0; +} + +/*----------------------------------------------------------------------- + * Check if pressed key(s) match magic sequence, + * and return the command string associated with that key(s). + * + * If no key press was decoded, NULL is returned. + * + * Note: the first character of the argument will be overwritten with + * the "magic charcter code" of the decoded key(s), or '\0'. + * + * + * Note: the string points to static environment data and must be + * saved before you call any function that modifies the environment. + */ +static uchar *key_match (ulong kbd_data) +{ + uchar magic[sizeof (kbd_magic_prefix) + 1]; + uchar cmd_name[sizeof (kbd_command_prefix) + 1]; + uchar *suffix; + uchar *kbd_magic_keys; + + /* + * The following string defines the characters that can pe appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + debug ("key_match: magic_keys=\"%s\"\n", kbd_magic_keys); + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix=kbd_magic_keys; *suffix || suffix==kbd_magic_keys; ++suffix) + { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); + + debug ("key_match: magic=\"%s\"\n", + getenv(magic) ? getenv(magic) : ""); + + if (compare_magic(kbd_data, getenv(magic)) == 0) + { + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + debug ("key_match: cmdname %s=\"%s\"\n", + cmd_name, + getenv (cmd_name) ? + getenv (cmd_name) : + ""); + return (getenv (cmd_name)); + } + } + debug ("key_match: no match\n"); + return (NULL); +} +#endif /* CONFIG_PREBOOT */ + +/* Read Keyboard status */ +int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong kbd_data = KBD_DATA; + uchar keybd_env[KEYBD_KEY_NUM + 1]; + int i; + + puts ("Keys:"); + for (i = 0; i < KEYBD_KEY_NUM; ++i) { + keybd_env[i] = '0' + ((kbd_data >> i) & 1); + printf (" %c", keybd_env[i]); + } + keybd_env[i] = '\0'; + putc ('\n'); + setenv ("keybd", keybd_env); + return 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "kbd - read keyboard status\n", + NULL +); + +#ifdef CONFIG_MODEM_SUPPORT +static int key_pressed(void) +{ + return (compare_magic(KBD_DATA, CONFIG_MODEM_KEY_MAGIC) == 0); +} +#endif /* CONFIG_MODEM_SUPPORT */ + +#ifdef CFG_BRIGHTNESS + +static inline void SET_CS_TOUCH(void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + gpio->PDDAT &= 0x5FF; +} + +static inline void CLR_CS_TOUCH(void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + gpio->PDDAT |= 0x200; +} + +static void spi_init(void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); + int i; + + /* Configure I/O ports. */ + gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; + gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; + gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; + gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + + CLR_CS_TOUCH(); + + spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */ + spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */ + spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ + + /* Dummy byte ensures clock to be low. */ + for (i = 0; i < 10; i++) { + spi->ch[0].SPTDAT = 0xFF; + } + wait_transmit_done(); +} + +static void wait_transmit_done(void) +{ + S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); + + while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */ +} + +static void tsc2000_write(unsigned int page, unsigned int reg, + unsigned int data) +{ + S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); + unsigned int command; + + SET_CS_TOUCH(); + command = 0x0000; + command |= (page << 11); + command |= (reg << 5); + + spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + wait_transmit_done(); + spi->ch[0].SPTDAT = (command & 0x00FF); + wait_transmit_done(); + spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + wait_transmit_done(); + spi->ch[0].SPTDAT = (data & 0x00FF); + wait_transmit_done(); + + CLR_CS_TOUCH(); +} + +static void tsc2000_set_brightness(void) +{ + uchar tmp[10]; + int i, br; + + spi_init(); + tsc2000_write(1, 2, 0x0); /* Power up DAC */ + + i = getenv_r("brightness", tmp, sizeof(tmp)); + br = (i > 0) + ? (int) simple_strtoul (tmp, NULL, 10) + : CFG_BRIGHTNESS; + + tsc2000_write(0, 0xb, br & 0xff); +} +#endif diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c new file mode 100644 index 0000000..abb3b29 --- /dev/null +++ b/board/trab/trab_fkt.c @@ -0,0 +1,1411 @@ +/* + * (C) Copyright 2003 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define DEBUG + +#include +#include +#include +#include "tsc2000.h" +#include "rs485.h" + +/* + * define, to wait for the touch to be pressed, before reading coordinates in + * command do_touch. If not defined, an error message is printed, when the + * command do_touch is invoked and the touch is not pressed within an specific + * interval. + */ +#undef CONFIG_TOUCH_WAIT_PRESSED + +/* max time to wait for touch is pressed */ +#ifndef CONFIG_TOUCH_WAIT_PRESSED +#define TOUCH_TIMEOUT 5 +#endif /* !CONFIG_TOUCH_WAIT_PRESSED */ + +/* assignment of CPU internal ADC channels with TRAB hardware */ +#define VCC5V 2 +#define VCC12V 3 + +/* CPLD-Register for controlling TRAB hardware functions */ +#define CPLD_BUTTONS ((volatile unsigned long *)0x04020000) +#define CPLD_FILL_LEVEL ((volatile unsigned long *)0x04008000) +#define CPLD_ROTARY_SWITCH ((volatile unsigned long *)0x04018000) +#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) + +/* timer configuration bits for buzzer and PWM */ +#define START2 (1 << 12) +#define UPDATE2 (1 << 13) +#define INVERT2 (1 << 14) +#define RELOAD2 (1 << 15) +#define START3 (1 << 16) +#define UPDATE3 (1 << 17) +#define INVERT3 (1 << 18) +#define RELOAD3 (1 << 19) + +#define PCLK 66000000 +#define BUZZER_FREQ 1000 /* frequency in Hz */ +#define PWM_FREQ 500 + + +/* definitions of I2C EEPROM device address */ +#define I2C_EEPROM_DEV_ADDR 0x54 + +/* definition for touch panel calibration points */ +#define CALIB_TL 0 /* calibration point in (T)op (L)eft corner */ +#define CALIB_DR 1 /* calibration point in (D)own (R)ight corner */ + +/* EEPROM address map */ +#define SERIAL_NUMBER 8 +#define TOUCH_X0 52 +#define TOUCH_Y0 54 +#define TOUCH_X1 56 +#define TOUCH_Y1 58 +#define CRC16 60 + +/* EEPROM stuff */ +#define EEPROM_MAX_CRC_BUF 64 + +/* RS485 stuff */ +#define RS485_MAX_RECEIVE_BUF_LEN 100 + +/* Bit definitions for ADCCON */ +#define ADC_ENABLE_START 0x1 +#define ADC_READ_START 0x2 +#define ADC_STDBM 0x4 +#define ADC_INP_AIN0 (0x0 << 3) +#define ADC_INP_AIN1 (0x1 << 3) +#define ADC_INP_AIN2 (0x2 << 3) +#define ADC_INP_AIN3 (0x3 << 3) +#define ADC_INP_AIN4 (0x4 << 3) +#define ADC_INP_AIN5 (0x5 << 3) +#define ADC_INP_AIN6 (0x6 << 3) +#define ADC_INP_AIN7 (0x7 << 3) +#define ADC_PRSCEN 0x4000 +#define ADC_ECFLG 0x8000 + +/* function test functions */ +int do_dip (void); +int do_info (void); +int do_vcc5v (void); +int do_vcc12v (void); +int do_buttons (void); +int do_fill_level (void); +int do_rotary_switch (void); +int do_pressure (void); +int do_v_bat (void); +int do_vfd_id (void); +int do_buzzer (char **); +int do_led (char **); +int do_full_bridge (char **); +int do_dac (char **); +int do_motor_contact (void); +int do_motor (char **); +int do_pwm (char **); +int do_thermo (char **); +int do_touch (char **); +int do_rs485 (char **); +int do_serial_number (char **); +int do_crc16 (void); +int do_power_switch (void); +int do_gain (char **); +int do_eeprom (char **); + +/* helper functions */ +static void adc_init (void); +static int adc_read (unsigned int channel); +static void print_identifier (void); + +#ifdef CONFIG_TOUCH_WAIT_PRESSED +static void touch_wait_pressed (void); +#else +static int touch_check_pressed (void); +#endif /* CONFIG_TOUCH_WAIT_PRESSED */ + +static void touch_read_x_y (int *x, int *y); +static int touch_write_clibration_values (int calib_point, int x, int y); +static int rs485_send_line (const char *data); +static int rs485_receive_chars (char *data, int timeout); +static unsigned short updcrc(unsigned short icrc, unsigned char *icp, + unsigned int icnt); + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +static int trab_eeprom_read (char **argv); +static int trab_eeprom_write (char **argv); +int i2c_write_multiple (uchar chip, uint addr, int alen, uchar *buffer, + int len); +int i2c_read_multiple ( uchar chip, uint addr, int alen, uchar *buffer, + int len); +#endif /* CFG_CMD_I2C */ + +/* + * TRAB board specific commands. Especially commands for burn-in and function + * test. + */ + +int trab_fkt (int argc, char *argv[]) +{ + int i; + + app_startup(argv); + if (get_version () != XF_VERSION) { + printf ("Wrong XF_VERSION. Please re-compile with actual " + "u-boot sources\n"); + printf ("Example expects ABI version %d\n", XF_VERSION); + printf ("Actual U-Boot ABI version %d\n", (int)get_version()); + return 1; + } + + debug ("argc = %d\n", argc); + + for (i=0; i<=argc; ++i) { + debug ("argv[%d] = \"%s\"\n", i, argv[i] ? argv[i] : ""); + } + + adc_init (); + + switch (argc) { + + case 0: + case 1: + break; + + case 2: + if (strcmp (argv[1], "info") == 0) { + return (do_info ()); + } + if (strcmp (argv[1], "dip") == 0) { + return (do_dip ()); + } + if (strcmp (argv[1], "vcc5v") == 0) { + return (do_vcc5v ()); + } + if (strcmp (argv[1], "vcc12v") == 0) { + return (do_vcc12v ()); + } + if (strcmp (argv[1], "buttons") == 0) { + return (do_buttons ()); + } + if (strcmp (argv[1], "fill_level") == 0) { + return (do_fill_level ()); + } + if (strcmp (argv[1], "rotary_switch") == 0) { + return (do_rotary_switch ()); + } + if (strcmp (argv[1], "pressure") == 0) { + return (do_pressure ()); + } + if (strcmp (argv[1], "v_bat") == 0) { + return (do_v_bat ()); + } + if (strcmp (argv[1], "vfd_id") == 0) { + return (do_vfd_id ()); + } + if (strcmp (argv[1], "motor_contact") == 0) { + return (do_motor_contact ()); + } + if (strcmp (argv[1], "crc16") == 0) { + return (do_crc16 ()); + } + if (strcmp (argv[1], "power_switch") == 0) { + return (do_power_switch ()); + } + break; + + case 3: + if (strcmp (argv[1], "full_bridge") == 0) { + return (do_full_bridge (argv)); + } + if (strcmp (argv[1], "dac") == 0) { + return (do_dac (argv)); + } + if (strcmp (argv[1], "motor") == 0) { + return (do_motor (argv)); + } + if (strcmp (argv[1], "pwm") == 0) { + return (do_pwm (argv)); + } + if (strcmp (argv[1], "thermo") == 0) { + return (do_thermo (argv)); + } + if (strcmp (argv[1], "touch") == 0) { + return (do_touch (argv)); + } + if (strcmp (argv[1], "serial_number") == 0) { + return (do_serial_number (argv)); + } + if (strcmp (argv[1], "buzzer") == 0) { + return (do_buzzer (argv)); + } + if (strcmp (argv[1], "gain") == 0) { + return (do_gain (argv)); + } + break; + + case 4: + if (strcmp (argv[1], "led") == 0) { + return (do_led (argv)); + } + if (strcmp (argv[1], "rs485") == 0) { + return (do_rs485 (argv)); + } + if (strcmp (argv[1], "serial_number") == 0) { + return (do_serial_number (argv)); + } + break; + + case 5: + if (strcmp (argv[1], "eeprom") == 0) { + return (do_eeprom (argv)); + } + break; + + case 6: + if (strcmp (argv[1], "eeprom") == 0) { + return (do_eeprom (argv)); + } + break; + + default: + break; + } + + printf ("Usage:\n ...\n"); + return 1; +} + +int do_info (void) +{ + printf ("Stand-alone application for TRAB board function test\n"); + printf ("Built: %s at %s\n", __DATE__ , __TIME__ ); + + return 0; +} + +int do_dip (void) +{ + unsigned int result = 0; + int adc_val; + int i; + + /*********************************************************** + DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3): + SW1 - AIN4 + SW2 - AIN5 + SW3 - AIN6 + SW4 - AIN7 + + "On" DIP switch position short-circuits the voltage from + the input channel (i.e. '0' conversion result means "on"). + *************************************************************/ + + for (i = 7; i > 3; i--) { + + if ((adc_val = adc_read (i)) == -1) { + printf ("Channel %d could not be read\n", i); + return 1; + } + + /* + * Input voltage (switch open) is 1.8 V. + * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736 + * Set trigger at halve that value. + */ + if (adc_val < 368) + result |= (1 << (i-4)); + } + + /* print result to console */ + print_identifier (); + for (i = 0; i < 4; i++) { + if ((result & (1 << i)) == 0) + printf("0"); + else + printf("1"); + } + printf("\n"); + + return 0; +} + + +int do_vcc5v (void) +{ + int result; + + /* VCC5V is connected to channel 2 */ + + if ((result = adc_read (VCC5V)) == -1) { + printf ("VCC5V could not be read\n"); + return 1; + } + + /* + * Calculate voltage value. Split in two parts because there is no + * floating point support. VCC5V is connected over an resistor divider: + * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K. + */ + print_identifier (); + printf ("%d", (result & 0x3FF)* 10 / 1023); + printf (".%d", ((result & 0x3FF)* 10 % 1023)* 10 / 1023); + printf ("%d V\n", (((result & 0x3FF) * 10 % 1023 ) * 10 % 1023) + * 10 / 1024); + + return 0; +} + + +int do_vcc12v (void) +{ + int result; + + if ((result = adc_read (VCC12V)) == -1) { + printf ("VCC12V could not be read\n"); + return 1; + } + + /* + * Calculate voltage value. Split in two parts because there is no + * floating point support. VCC5V is connected over an resistor divider: + * VCC12V=ADCval*2,5V/1023*(30K+270K)/30K. + */ + print_identifier (); + printf ("%d", (result & 0x3FF)* 25 / 1023); + printf (".%d V\n", ((result & 0x3FF)* 25 % 1023) * 10 / 1023); + + return 0; +} + +static int adc_read (unsigned int channel) +{ + int j = 1000; /* timeout value for wait loop in us */ + int result; + S3C2400_ADC *padc; + + padc = S3C2400_GetBase_ADC(); + channel &= 0x7; + + padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ + padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ + padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + + while (j--) { + if ((padc->ADCCON & ADC_ENABLE_START) == 0) + break; + udelay (1); + } + + if (j == 0) { + printf("%s: ADC timeout\n", __FUNCTION__); + padc->ADCCON |= ADC_STDBM; /* select standby mode */ + return -1; + } + + result = padc->ADCDAT & 0x3FF; + + padc->ADCCON |= ADC_STDBM; /* select standby mode */ + + debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, + (padc->ADCCON >> 3) & 0x7, result); + + /* + * Wait for ADC to be ready for next conversion. This delay value was + * estimated, because the datasheet does not specify a value. + */ + udelay (1000); + + return (result); +} + + +static void adc_init (void) +{ + S3C2400_ADC *padc; + + padc = S3C2400_GetBase_ADC(); + + padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ + padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + + /* + * Wait some time to avoid problem with very first call of + * adc_read(). Without * this delay, sometimes the first read adc + * value is 0. Perhaps because the * adjustment of prescaler takes + * some clock cycles? + */ + udelay (1000); + + return; +} + + +int do_buttons (void) +{ + int result; + int i; + + result = *CPLD_BUTTONS; /* read CPLD */ + debug ("%s: cpld_taster (32 bit) %#x\n", __FUNCTION__, result); + + /* print result to console */ + print_identifier (); + for (i = 16; i <= 19; i++) { + if ((result & (1 << i)) == 0) + printf("0"); + else + printf("1"); + } + printf("\n"); + return 0; +} + + +int do_power_switch (void) +{ + int result; + + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* configure GPE7 as input */ + gpio->PECON &= ~(0x3 << (2 * 7)); + + /* signal GPE7 from power switch is low active: 0=on , 1=off */ + result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1; + + print_identifier (); + printf("%d\n", result); + return 0; +} + + +int do_fill_level (void) +{ + int result; + + result = *CPLD_FILL_LEVEL; /* read CPLD */ + debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result); + + /* print result to console */ + print_identifier (); + if ((result & (1 << 16)) == 0) + printf("0\n"); + else + printf("1\n"); + return 0; +} + + +int do_rotary_switch (void) +{ + int result; + /* + * Please note, that the default values of the direction bits are + * undefined after reset. So it is a good idea, to make first a dummy + * call to this function, to clear the direction bits and set so to + * proper values. + */ + + result = *CPLD_ROTARY_SWITCH; /* read CPLD */ + debug ("%s: cpld_inc (32 bit) %#x\n", __FUNCTION__, result); + + *CPLD_ROTARY_SWITCH |= (3 << 16); /* clear direction bits in CPLD */ + + /* print result to console */ + print_identifier (); + if ((result & (1 << 16)) == (1 << 16)) + printf("R"); + if ((result & (1 << 17)) == (1 << 17)) + printf("L"); + if (((result & (1 << 16)) == 0) && ((result & (1 << 17)) == 0)) + printf("0"); + if ((result & (1 << 18)) == 0) + printf("0\n"); + else + printf("1\n"); + return 0; +} + + +int do_vfd_id (void) +{ + int i; + long int pcup_old, pccon_old; + int vfd_board_id; + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* try to red vfd board id from the value defined by pull-ups */ + + pcup_old = gpio->PCUP; + pccon_old = gpio->PCCON; + + gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pull-ups */ + gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as + * inputs */ + udelay (10); /* allow signals to settle */ + vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */ + + gpio->PCCON = pccon_old; + gpio->PCUP = pcup_old; + + /* print vfd_board_id to console */ + print_identifier (); + for (i = 0; i < 4; i++) { + if ((vfd_board_id & (1 << i)) == 0) + printf("0"); + else + printf("1"); + } + printf("\n"); + return 0; +} + +int do_buzzer (char **argv) +{ + int counter; + + S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* set prescaler for timer 2, 3 and 4 */ + timers->TCFG0 &= ~0xFF00; + timers->TCFG0 |= 0x0F00; + + /* set divider for timer 2 */ + timers->TCFG1 &= ~0xF00; + timers->TCFG1 |= 0x300; + + /* set frequency */ + counter = (PCLK / BUZZER_FREQ) >> 9; + timers->ch[2].TCNTB = counter; + timers->ch[2].TCMPB = counter / 2; + + if (strcmp (argv[2], "on") == 0) { + debug ("%s: frequency: %d\n", __FUNCTION__, + BUZZER_FREQ); + + /* configure pin GPD7 as TOUT2 */ + gpio->PDCON &= ~0xC000; + gpio->PDCON |= 0x8000; + + /* start */ + timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) & + ~INVERT2; + timers->TCON = (timers->TCON | START2) & ~UPDATE2; + return (0); + } + else if (strcmp (argv[2], "off") == 0) { + /* stop */ + timers->TCON &= ~(START2 | RELOAD2); + + /* configure GPD7 as output and set to low */ + gpio->PDCON &= ~0xC000; + gpio->PDCON |= 0x4000; + gpio->PDDAT &= ~0x80; + return (0); + } + + printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); + return 1; +} + + +int do_led (char **argv) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* configure PC14 and PC15 as output */ + gpio->PCCON &= ~(0xF << 28); + gpio->PCCON |= (0x5 << 28); + + /* configure PD0 and PD4 as output */ + gpio->PDCON &= ~((0x3 << 8) | 0x3); + gpio->PDCON |= ((0x1 << 8) | 0x1); + + switch (simple_strtoul(argv[2], NULL, 10)) { + + case 0: + case 1: + break; + + case 2: + if (strcmp (argv[3], "on") == 0) + gpio->PCDAT |= (1 << 14); + else + gpio->PCDAT &= ~(1 << 14); + return 0; + + case 3: + if (strcmp (argv[3], "on") == 0) + gpio->PCDAT |= (1 << 15); + else + gpio->PCDAT &= ~(1 << 15); + return 0; + + case 4: + if (strcmp (argv[3], "on") == 0) + gpio->PDDAT |= (1 << 0); + else + gpio->PDDAT &= ~(1 << 0); + return 0; + + case 5: + if (strcmp (argv[3], "on") == 0) + gpio->PDDAT |= (1 << 4); + else + gpio->PDDAT &= ~(1 << 4); + return 0; + + default: + break; + + } + printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); + return 1; +} + + +int do_full_bridge (char **argv) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* configure PD5 and PD6 as output */ + gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2)); + gpio->PDCON |= ((0x1 << 5*2) | (0x1 << 6*2)); + + if (strcmp (argv[2], "+") == 0) { + gpio->PDDAT |= (1 << 5); + gpio->PDDAT |= (1 << 6); + return 0; + } + else if (strcmp (argv[2], "-") == 0) { + gpio->PDDAT &= ~(1 << 5); + gpio->PDDAT |= (1 << 6); + return 0; + } + else if (strcmp (argv[2], "off") == 0) { + gpio->PDDAT &= ~(1 << 5); + gpio->PDDAT &= ~(1 << 6); + return 0; + } + printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); + return 1; +} + +/* val must be in [0, 4095] */ +static inline unsigned long tsc2000_to_uv (u16 val) +{ + return ((250000 * val) / 4096) * 10; +} + + +int do_dac (char **argv) +{ + int brightness; + + /* initialize SPI */ + spi_init (); + + if (((brightness = simple_strtoul (argv[2], NULL, 10)) < 0) || + (brightness > 255)) { + printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); + return 1; + } + tsc2000_write(TSC2000_REG_DACCTL, 0x0); /* Power up DAC */ + tsc2000_write(TSC2000_REG_DAC, brightness & 0xff); + + return 0; +} + + +int do_v_bat (void) +{ + unsigned long ret, res; + + /* initialize SPI */ + spi_init (); + + tsc2000_write(TSC2000_REG_ADC, 0x1836); + + /* now wait for data available */ + adc_wait_conversion_done(); + + ret = tsc2000_read(TSC2000_REG_BAT1); + res = (tsc2000_to_uv(ret) + 1250) / 2500; + res += (ERROR_BATTERY * res) / 1000; + + print_identifier (); + printf ("%ld", (res / 100)); + printf (".%ld", ((res % 100) / 10)); + printf ("%ld V\n", (res % 10)); + return 0; +} + + +int do_pressure (void) +{ + /* initialize SPI */ + spi_init (); + + tsc2000_write(TSC2000_REG_ADC, 0x2436); + + /* now wait for data available */ + adc_wait_conversion_done(); + + print_identifier (); + printf ("%d\n", tsc2000_read(TSC2000_REG_AUX2)); + return 0; +} + + +int do_motor_contact (void) +{ + int result; + + result = *CPLD_FILL_LEVEL; /* read CPLD */ + debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result); + + /* print result to console */ + print_identifier (); + if ((result & (1 << 17)) == 0) + printf("0\n"); + else + printf("1\n"); + return 0; +} + +int do_motor (char **argv) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* Configure I/O port */ + gpio->PGCON &= ~(0x3 << 0); + gpio->PGCON |= (0x1 << 0); + + if (strcmp (argv[2], "on") == 0) { + gpio->PGDAT &= ~(1 << 0); + return 0; + } + if (strcmp (argv[2], "off") == 0) { + gpio->PGDAT |= (1 << 0); + return 0; + } + printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); + return 1; +} + +static void print_identifier (void) +{ + printf ("## FKT: "); +} + +int do_pwm (char **argv) +{ + int counter; + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); + + if (strcmp (argv[2], "on") == 0) { + /* configure pin GPD8 as TOUT3 */ + gpio->PDCON &= ~(0x3 << 8*2); + gpio->PDCON |= (0x2 << 8*2); + + /* set prescaler for timer 2, 3 and 4 */ + timers->TCFG0 &= ~0xFF00; + timers->TCFG0 |= 0x0F00; + + /* set divider for timer 3 */ + timers->TCFG1 &= ~(0xf << 12); + timers->TCFG1 |= (0x3 << 12); + + /* set frequency */ + counter = (PCLK / PWM_FREQ) >> 9; + timers->ch[3].TCNTB = counter; + timers->ch[3].TCMPB = counter / 2; + + /* start timer */ + timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; + timers->TCON = (timers->TCON | START3) & ~UPDATE3; + return 0; + } + if (strcmp (argv[2], "off") == 0) { + + /* stop timer */ + timers->TCON &= ~(START2 | RELOAD2); + + /* configure pin GPD8 as output and set to 0 */ + gpio->PDCON &= ~(0x3 << 8*2); + gpio->PDCON |= (0x1 << 8*2); + gpio->PDDAT &= ~(1 << 8); + return 0; + } + printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); + return 1; +} + + +int do_thermo (char **argv) +{ + int channel, res; + + tsc2000_reg_init (); + + if (strcmp (argv[2], "all") == 0) { + int i; + for (i=0; i <= 15; i++) { + res = tsc2000_read_channel(i); + print_identifier (); + printf ("c%d: %d\n", i, res); + } + return 0; + } + channel = simple_strtoul (argv[2], NULL, 10); + res = tsc2000_read_channel(channel); + print_identifier (); + printf ("%d\n", res); + return 0; /* return OK */ +} + + +int do_touch (char **argv) +{ + int x, y; + + if (strcmp (argv[2], "tl") == 0) { +#ifdef CONFIG_TOUCH_WAIT_PRESSED + touch_wait_pressed(); +#else + { + int i; + for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) { + if (touch_check_pressed ()) { + break; + } + udelay (1000); /* pause 1 ms */ + } + } + if (!touch_check_pressed()) { + print_identifier (); + printf ("error: touch not pressed\n"); + return 1; + } +#endif /* CONFIG_TOUCH_WAIT_PRESSED */ + touch_read_x_y (&x, &y); + + print_identifier (); + printf ("x=%d y=%d\n", x, y); + return touch_write_clibration_values (CALIB_TL, x, y); + } + else if (strcmp (argv[2], "dr") == 0) { +#ifdef CONFIG_TOUCH_WAIT_PRESSED + touch_wait_pressed(); +#else + { + int i; + for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) { + if (touch_check_pressed ()) { + break; + } + udelay (1000); /* pause 1 ms */ + } + } + if (!touch_check_pressed()) { + print_identifier (); + printf ("error: touch not pressed\n"); + return 1; + } +#endif /* CONFIG_TOUCH_WAIT_PRESSED */ + touch_read_x_y (&x, &y); + + print_identifier (); + printf ("x=%d y=%d\n", x, y); + + return touch_write_clibration_values (CALIB_DR, x, y); + } + return 1; /* not "tl", nor "dr", so return error */ +} + + +#ifdef CONFIG_TOUCH_WAIT_PRESSED +static void touch_wait_pressed (void) +{ + while (!(tsc2000_read(TSC2000_REG_ADC) & TC_PSM)); +} + +#else +static int touch_check_pressed (void) +{ + return (tsc2000_read(TSC2000_REG_ADC) & TC_PSM); +} +#endif /* CONFIG_TOUCH_WAIT_PRESSED */ + +static int touch_write_clibration_values (int calib_point, int x, int y) +{ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) + int x_verify = 0; + int y_verify = 0; + + tsc2000_reg_init (); + + if (calib_point == CALIB_TL) { + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1, + (char *)&x, 2)) { + return 1; + } + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1, + (char *)&y, 2)) { + return 1; + } + + /* verify written values */ + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1, + (char *)&x_verify, 2)) { + return 1; + } + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1, + (char *)&y_verify, 2)) { + return 1; + } + if ((y != y_verify) || (x != x_verify)) { + print_identifier (); + printf ("error: verify error\n"); + return 1; + } + return 0; /* no error */ + } + else if (calib_point == CALIB_DR) { + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1, + (char *)&x, 2)) { + return 1; + } + if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1, + (char *)&y, 2)) { + return 1; + } + + /* verify written values */ + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1, + (char *)&x_verify, 2)) { + return 1; + } + if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1, + (char *)&y_verify, 2)) { + return 1; + } + if ((y != y_verify) || (x != x_verify)) { + print_identifier (); + printf ("error: verify error\n"); + return 1; + } + return 0; + } + return 1; +#else + printf ("No I2C support enabled (CFG_CMD_I2C), could not write " + "to EEPROM\n"); + return (1); +#endif /* CFG_CMD_I2C */ +} + + +static void touch_read_x_y (int *px, int *py) +{ + tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD0 | TC_AD1); + adc_wait_conversion_done(); + *px = tsc2000_read(TSC2000_REG_X); + + tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD2); + adc_wait_conversion_done(); + *py = tsc2000_read(TSC2000_REG_Y); +} + + +int do_rs485 (char **argv) +{ + int timeout; + char data[RS485_MAX_RECEIVE_BUF_LEN]; + + if (strcmp (argv[2], "send") == 0) { + return (rs485_send_line (argv[3])); + } + else if (strcmp (argv[2], "receive") == 0) { + timeout = simple_strtoul(argv[3], NULL, 10); + if (rs485_receive_chars (data, timeout) != 0) { + print_identifier (); + printf ("## nothing received\n"); + return (1); + } + else { + print_identifier (); + printf ("%s\n", data); + return (0); + } + } + printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]); + return (1); /* unknown command, return error */ +} + + +static int rs485_send_line (const char *data) +{ + rs485_init (); + trab_rs485_enable_tx (); + rs485_puts (data); + rs485_putc ('\n'); + + return (0); +} + + +static int rs485_receive_chars (char *data, int timeout) +{ + int i; + int receive_count = 0; + + rs485_init (); + trab_rs485_enable_rx (); + + /* test every 1 ms for received characters to avoid a receive FIFO + * overrun (@ 38.400 Baud) */ + for (i = 0; i < (timeout * 1000); i++) { + while (rs485_tstc ()) { + if (receive_count >= RS485_MAX_RECEIVE_BUF_LEN-1) + break; + *data++ = rs485_getc (); + receive_count++; + } + udelay (1000); /* pause 1 ms */ + } + *data = '\0'; /* terminate string */ + + if (receive_count == 0) + return (1); + else + return (0); +} + + +int do_serial_number (char **argv) +{ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) + unsigned int serial_number; + + if (strcmp (argv[2], "read") == 0) { + if (i2c_read (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1, + (char *)&serial_number, 4)) { + printf ("could not read from eeprom\n"); + return (1); + } + print_identifier (); + printf ("%08d\n", serial_number); + return (0); + } + else if (strcmp (argv[2], "write") == 0) { + serial_number = simple_strtoul(argv[3], NULL, 10); + if (i2c_write (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1, + (char *)&serial_number, 4)) { + printf ("could not write to eeprom\n"); + return (1); + } + return (0); + } + printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]); + return (1); /* unknown command, return error */ +#else + printf ("No I2C support enabled (CFG_CMD_I2C), could not write " + "to EEPROM\n"); + return (1); +#endif /* CFG_CMD_I2C */ +} + + +int do_crc16 (void) +{ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) + int crc; + char buf[EEPROM_MAX_CRC_BUF]; + + if (i2c_read (I2C_EEPROM_DEV_ADDR, 0, 1, buf, 60)) { + printf ("could not read from eeprom\n"); + return (1); + } + crc = 0; /* start value of crc calculation */ + crc = updcrc (crc, buf, 60); + + print_identifier (); + printf ("crc16=%#04x\n", crc); + + if (i2c_write (I2C_EEPROM_DEV_ADDR, CRC16, 1, (char *)&crc, + sizeof (crc))) { + printf ("could not read from eeprom\n"); + return (1); + } + return (0); +#else + printf ("No I2C support enabled (CFG_CMD_I2C), could not write " + "to EEPROM\n"); + return (1); +#endif /* CFG_CMD_I2C */ +} + + +/* + * Calculate, intelligently, the CRC of a dataset incrementally given a + * buffer full at a time. + * Initialize crc to 0 for XMODEM, -1 for CCITT. + * + * Usage: + * newcrc = updcrc( oldcrc, bufadr, buflen ) + * unsigned int oldcrc, buflen; + * char *bufadr; + * + * Compile with -DTEST to generate program that prints CRC of stdin to stdout. + * Compile with -DMAKETAB to print values for crctab to stdout + */ + + /* the CRC polynomial. This is used by XMODEM (almost CCITT). + * If you change P, you must change crctab[]'s initial value to what is + * printed by initcrctab() + */ +#define P 0x1021 + + /* number of bits in CRC: don't change it. */ +#define W 16 + + /* this the number of bits per char: don't change it. */ +#define B 8 + +static unsigned short crctab[1<>(W-B)) ^ *cp++]; + + return (crc); +} + + +int do_gain (char **argv) +{ + int range; + + range = simple_strtoul (argv[2], NULL, 10); + if ((range < 1) || (range > 3)) + { + printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); + return 1; + } + + tsc2000_set_range (range); + return (0); +} + + +int do_eeprom (char **argv) +{ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) + if (strcmp (argv[2], "read") == 0) { + return (trab_eeprom_read (argv)); + } + + else if (strcmp (argv[2], "write") == 0) { + return (trab_eeprom_write (argv)); + } + + printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); + return (1); +#else + printf ("No I2C support enabled (CFG_CMD_I2C), could not write " + "to EEPROM\n"); + return (1); +#endif /* CFG_CMD_I2C */ +} + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +static int trab_eeprom_read (char **argv) +{ + int i; + int len; + unsigned int addr; + long int value = 0; + uchar *buffer; + + buffer = (uchar *) &value; + addr = simple_strtoul (argv[3], NULL, 10); + addr &= 0xfff; + len = simple_strtoul (argv[4], NULL, 10); + if ((len < 1) || (len > 4)) { + printf ("%s: invalid parameter %s\n", __FUNCTION__, + argv[4]); + return (1); + } + for (i = 0; i < len; i++) { + if (i2c_read (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) { + printf ("%s: could not read from i2c device %#x" + ", addr %d\n", __FUNCTION__, + I2C_EEPROM_DEV_ADDR, addr); + return (1); + } + } + print_identifier (); + if (strcmp (argv[5], "-") == 0) { + if (len == 1) + printf ("%d\n", (signed char) value); + else if (len == 2) + printf ("%d\n", (signed short int) value); + else + printf ("%ld\n", value); + } + else { + if (len == 1) + printf ("%d\n", (unsigned char) value); + else if (len == 2) + printf ("%d\n", (unsigned short int) value); + else + printf ("%ld\n", (unsigned long int) value); + } + return (0); +} + +static int trab_eeprom_write (char **argv) +{ + int i; + int len; + unsigned int addr; + long int value = 0; + uchar *buffer; + + buffer = (uchar *) &value; + addr = simple_strtoul (argv[3], NULL, 10); + addr &= 0xfff; + len = simple_strtoul (argv[4], NULL, 10); + if ((len < 1) || (len > 4)) { + printf ("%s: invalid parameter %s\n", __FUNCTION__, + argv[4]); + return (1); + } + value = simple_strtol (argv[5], NULL, 10); + debug ("value=%ld\n", value); + for (i = 0; i < len; i++) { + if (i2c_write (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) { + printf ("%s: could not write to i2c device %d" + ", addr %d\n", __FUNCTION__, + I2C_EEPROM_DEV_ADDR, addr); + return (1); + } +#if 0 + printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" + "%#x+%d=%p=%#x \n",I2C_EEPROM_DEV_ADDR_DEV_ADDR , addr, + i, addr+i, 1, buffer, i, buffer+i, *(buffer+i)); +#endif + udelay (30000); /* wait for EEPROM ready */ + } + return (0); +} + +int i2c_write_multiple (uchar chip, uint addr, int alen, + uchar *buffer, int len) +{ + int i; + + if (alen != 1) { + printf ("%s: addr len other than 1 not supported\n", + __FUNCTION__); + return (1); + } + + for (i = 0; i < len; i++) { + if (i2c_write (chip, addr+i, alen, buffer+i, 1)) { + printf ("%s: could not write to i2c device %d" + ", addr %d\n", __FUNCTION__, chip, addr); + return (1); + } +#if 0 + printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" + "%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i, + alen, buffer, i, buffer+i, buffer+i); +#endif + + udelay (30000); + } + return (0); +} + +int i2c_read_multiple ( uchar chip, uint addr, int alen, + uchar *buffer, int len) +{ + int i; + + if (alen != 1) { + printf ("%s: addr len other than 1 not supported\n", + __FUNCTION__); + return (1); + } + + for (i = 0; i < len; i++) { + if (i2c_read (chip, addr+i, alen, buffer+i, 1)) { + printf ("%s: could not read from i2c device %#x" + ", addr %d\n", __FUNCTION__, chip, addr); + return (1); + } + } + return (0); +} +#endif /* CFG_CMD_I2C */ diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c new file mode 100644 index 0000000..ca68682 --- /dev/null +++ b/board/trab/tsc2000.c @@ -0,0 +1,362 @@ +/* + * Functions to access the TSC2000 controller on TRAB board (used for scanning + * thermo sensors) + * + * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "tsc2000.h" + +#include "Pt1000_temp_data.h" + +/* helper function */ +#define abs(value) (((value) < 0) ? ((value)*-1) : (value)) + +/* + * Maximal allowed deviation between two immediate meassurments of an analog + * thermo channel. 1 DIGIT = 0.0276 °C. This is used to filter sporadic + * "jumps" in measurment. + */ +#define MAX_DEVIATION 18 /* unit: DIGITs of adc; 18 DIGIT = 0.5 °C */ + +void spi_init(void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); + int i; + + /* Configure I/O ports. */ + gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; + gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; + gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; + gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + + CLR_CS_TOUCH(); + + spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */ + spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */ + spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, + CPHA=1 */ + + /* Dummy byte ensures clock to be low. */ + for (i = 0; i < 10; i++) { + spi->ch[0].SPTDAT = 0xFF; + } + spi_wait_transmit_done(); +} + + +void spi_wait_transmit_done(void) +{ + S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); + + while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */ +} + + +void tsc2000_write(unsigned short reg, unsigned short data) +{ + S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); + unsigned int command; + + SET_CS_TOUCH(); + command = reg; + spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + spi_wait_transmit_done(); + spi->ch[0].SPTDAT = (command & 0x00FF); + spi_wait_transmit_done(); + spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + spi_wait_transmit_done(); + spi->ch[0].SPTDAT = (data & 0x00FF); + spi_wait_transmit_done(); + + CLR_CS_TOUCH(); +} + + +unsigned short tsc2000_read (unsigned short reg) +{ + unsigned short command, data; + S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); + + SET_CS_TOUCH(); + command = 0x8000 | reg; + + spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + spi_wait_transmit_done(); + spi->ch[0].SPTDAT = (command & 0x00FF); + spi_wait_transmit_done(); + + spi->ch[0].SPTDAT = 0xFF; + spi_wait_transmit_done(); + data = spi->ch[0].SPRDAT; + spi->ch[0].SPTDAT = 0xFF; + spi_wait_transmit_done(); + + CLR_CS_TOUCH(); + return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8); +} + + +void tsc2000_set_mux (unsigned int channel) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + CLR_MUX1_ENABLE; CLR_MUX2_ENABLE; + CLR_MUX3_ENABLE; CLR_MUX4_ENABLE; + switch (channel) { + case 0: + CLR_MUX0; CLR_MUX1; + SET_MUX1_ENABLE; + break; + case 1: + SET_MUX0; CLR_MUX1; + SET_MUX1_ENABLE; + break; + case 2: + CLR_MUX0; SET_MUX1; + SET_MUX1_ENABLE; + break; + case 3: + SET_MUX0; SET_MUX1; + SET_MUX1_ENABLE; + break; + case 4: + CLR_MUX0; CLR_MUX1; + SET_MUX2_ENABLE; + break; + case 5: + SET_MUX0; CLR_MUX1; + SET_MUX2_ENABLE; + break; + case 6: + CLR_MUX0; SET_MUX1; + SET_MUX2_ENABLE; + break; + case 7: + SET_MUX0; SET_MUX1; + SET_MUX2_ENABLE; + break; + case 8: + CLR_MUX0; CLR_MUX1; + SET_MUX3_ENABLE; + break; + case 9: + SET_MUX0; CLR_MUX1; + SET_MUX3_ENABLE; + break; + case 10: + CLR_MUX0; SET_MUX1; + SET_MUX3_ENABLE; + break; + case 11: + SET_MUX0; SET_MUX1; + SET_MUX3_ENABLE; + break; + case 12: + CLR_MUX0; CLR_MUX1; + SET_MUX4_ENABLE; + break; + case 13: + SET_MUX0; CLR_MUX1; + SET_MUX4_ENABLE; + break; + case 14: + CLR_MUX0; SET_MUX1; + SET_MUX4_ENABLE; + break; + case 15: + SET_MUX0; SET_MUX1; + SET_MUX4_ENABLE; + break; + default: + CLR_MUX0; CLR_MUX1; + } +} + + +void tsc2000_set_range (unsigned int range) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + switch (range) { + case 1: + CLR_SEL_TEMP_V_0; SET_SEL_TEMP_V_1; + CLR_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3; + break; + case 2: + CLR_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1; + CLR_SEL_TEMP_V_2; SET_SEL_TEMP_V_3; + break; + case 3: + SET_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1; + SET_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3; + break; + } +} + + +u16 tsc2000_read_channel (unsigned int channel) +{ + u16 res; + + tsc2000_set_mux(channel); + udelay(3 * TSC2000_DELAY_BASE); + + tsc2000_write(TSC2000_REG_ADC, 0x2036); + adc_wait_conversion_done (); + res = tsc2000_read(TSC2000_REG_AUX1); + return res; +} + + +s32 tsc2000_contact_temp (void) +{ + long adc_pt1000, offset; + long u_pt1000; + long contact_temp; + long temp1, temp2; + + tsc2000_reg_init (); + tsc2000_set_range (3); + + /* + * Because of sporadic "jumps" in the measured adc values every + * channel is read two times. If there is a significant difference + * between the two measurements, then print an error and do a third + * measurement, because it is very unlikely that a successive third + * measurement goes also wrong. + */ + temp1 = tsc2000_read_channel (14); + temp2 = tsc2000_read_channel (14); + if (abs(temp2 - temp1) < MAX_DEVIATION) + adc_pt1000 = temp2; + else { + printf ("%s: read adc value (channel 14) exceeded max allowed " + "deviation: %d * 0.0276 °C\n", + __FUNCTION__, MAX_DEVIATION); + printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n", + temp1, temp2); + adc_pt1000 = tsc2000_read_channel (14); + printf ("use (third read) adc value: adc_pt1000 = " + "%ld DIGITs\n", adc_pt1000); + } + debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000); + + temp1 = tsc2000_read_channel (15); + temp2 = tsc2000_read_channel (15); + if (abs(temp2 - temp1) < MAX_DEVIATION) + offset = temp2; + else { + printf ("%s: read adc value (channel 15) exceeded max allowed " + "deviation: %d * 0.0276 °C\n", + __FUNCTION__, MAX_DEVIATION); + printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n", + temp1, temp2); + offset = tsc2000_read_channel (15); + printf ("use (third read) adc value: offset = %ld DIGITs\n", + offset); + } + debug ("read channel 15 (offset): %ld\n", offset); + + /* + * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 = + * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3: + * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The + * error correction Values err_vref and err_amp3 are assumed as 0 in + * u-boot, because this could cause only a very small error (< 1%). + */ + u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10; + debug ("u_pt1000: %ld\n", u_pt1000); + + if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table, + &contact_temp) == -1) { + printf ("%s: error interpolating PT1000 vlaue\n", + __FUNCTION__); + return (-1000); + } + debug ("contact_temp: %ld\n", contact_temp); + + return contact_temp; +} + + +void tsc2000_reg_init (void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + tsc2000_write(TSC2000_REG_ADC, 0x2036); + tsc2000_write(TSC2000_REG_REF, 0x0011); + tsc2000_write(TSC2000_REG_DACCTL, 0x0000); + + CON_MUX0; + CON_MUX1; + + CON_MUX1_ENABLE; + CON_MUX2_ENABLE; + CON_MUX3_ENABLE; + CON_MUX4_ENABLE; + + CON_SEL_TEMP_V_0; + CON_SEL_TEMP_V_1; + CON_SEL_TEMP_V_2; + CON_SEL_TEMP_V_3; + + tsc2000_set_mux(0); + tsc2000_set_range(0); +} + + +int tsc2000_interpolate(long value, long data[][2], long *result) +{ + int i; + + /* the data is sorted and the first element is upper + * limit so we can easily check for out-of-band values + */ + if (data[0][0] < value || data[1][0] > value) + return -1; + + i = 1; + while (data[i][0] < value) + i++; + + /* To prevent overflow we have to store the intermediate + result in 'long long'. + */ + + *result = data[i-1][1] + + ((unsigned long long)(data[i][1] - data[i-1][1]) + * (unsigned long long)(value - data[i-1][0])) + / (data[i][0] - data[i-1][0]); + + return 0; +} + + +void adc_wait_conversion_done(void) +{ + while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14))); +} diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h new file mode 100644 index 0000000..aac9c0c --- /dev/null +++ b/board/trab/tsc2000.h @@ -0,0 +1,145 @@ +/* + * Functions to access the TSC2000 controller on TRAB board (used for scanning + * thermo sensors) + * + * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TSC2000_H_ +#define _TSC2000_H_ + +/* temperature channel multiplexer definitions */ +#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100) +#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF) +#define SET_MUX0 (gpio->PCDAT |= 0x00010) + +#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400) +#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF) +#define SET_MUX1 (gpio->PCDAT |= 0x00020) + +#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000) +#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040) +#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF) + +#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000) +#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080) +#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F) + +#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000) +#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100) +#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF) + +#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000) +#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200) +#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF) + +#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000) +#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF) +#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400) + +#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000) +#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF) +#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800) + +#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000) +#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF) +#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000) + +#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000) +#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF) +#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000) + +/* TSC2000 register definition */ +#define TSC2000_REG_X ((0 << 11) | (0 << 5)) +#define TSC2000_REG_Y ((0 << 11) | (1 << 5)) +#define TSC2000_REG_Z1 ((0 << 11) | (2 << 5)) +#define TSC2000_REG_Z2 ((0 << 11) | (3 << 5)) +#define TSC2000_REG_BAT1 ((0 << 11) | (5 << 5)) +#define TSC2000_REG_BAT2 ((0 << 11) | (6 << 5)) +#define TSC2000_REG_AUX1 ((0 << 11) | (7 << 5)) +#define TSC2000_REG_AUX2 ((0 << 11) | (8 << 5)) +#define TSC2000_REG_TEMP1 ((0 << 11) | (9 << 5)) +#define TSC2000_REG_TEMP2 ((0 << 11) | (0xA << 5)) +#define TSC2000_REG_DAC ((0 << 11) | (0xB << 5)) +#define TSC2000_REG_ZERO ((0 << 11) | (0x10 << 5)) +#define TSC2000_REG_ADC ((1 << 11) | (0 << 5)) +#define TSC2000_REG_DACCTL ((1 << 11) | (2 << 5)) +#define TSC2000_REG_REF ((1 << 11) | (3 << 5)) +#define TSC2000_REG_RESET ((1 << 11) | (4 << 5)) +#define TSC2000_REG_CONFIG ((1 << 11) | (5 << 5)) + +/* bit definition of TSC2000 ADC register */ +#define TC_PSM (1 << 15) +#define TC_STS (1 << 14) +#define TC_AD3 (1 << 13) +#define TC_AD2 (1 << 12) +#define TC_AD1 (1 << 11) +#define TC_AD0 (1 << 10) +#define TC_RS1 (1 << 9) +#define TC_RS0 (1 << 8) +#define TC_AV1 (1 << 7) +#define TC_AV0 (1 << 6) +#define TC_CL1 (1 << 5) +#define TC_CL0 (1 << 4) +#define TC_PV2 (1 << 3) +#define TC_PV1 (1 << 2) +#define TC_PV0 (1 << 1) + +/* default value for TSC2000 ADC register for use with touch functions */ +#define DEFAULT_ADC (TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0) + +#define TSC2000_DELAY_BASE 500 +#define TSC2000_NO_SENSOR -0x10000 + +#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on + * TRAB */ + +void tsc2000_write(unsigned short, unsigned short); +unsigned short tsc2000_read (unsigned short); +u16 tsc2000_read_channel (unsigned int); +void tsc2000_set_mux (unsigned int); +void tsc2000_set_range (unsigned int); +void tsc2000_reg_init (void); +s32 tsc2000_contact_temp (void); +void spi_wait_transmit_done (void); +void spi_init(void); +int tsc2000_interpolate(long value, long data[][2], long *result); +void adc_wait_conversion_done(void); + + +static inline void SET_CS_TOUCH(void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + gpio->PDDAT &= 0x5FF; +} + + +static inline void CLR_CS_TOUCH(void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + gpio->PDDAT |= 0x200; +} + +#endif /* _TSC2000_H_ */ diff --git a/board/trab/u-boot.lds b/board/trab/u-boot.lds new file mode 100644 index 0000000..e56cdd3 --- /dev/null +++ b/board/trab/u-boot.lds @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + lib_arm/_umodsi3.o (.text) + lib_generic/zlib.o (.text) + lib_generic/crc32.o (.text) + lib_generic/string.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/trab/vfd.c b/board/trab/vfd.c new file mode 100644 index 0000000..f510ee5 --- /dev/null +++ b/board/trab/vfd.c @@ -0,0 +1,571 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering -- wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************/ +/* ** DEBUG SETTINGS */ +/************************************************************************/ + +/* #define DEBUG */ + +/************************************************************************/ +/* ** HEADER FILES */ +/************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_VFD + +/************************************************************************/ +/* ** CONFIG STUFF -- should be moved to board config file */ +/************************************************************************/ + +/************************************************************************/ + +#ifndef PAGE_SIZE +#define PAGE_SIZE 4096 +#endif + +#define ROT 0x09 +#define BLAU 0x0C +#define VIOLETT 0X0D + +/* MAGIC */ +#define FRAME_BUF_SIZE ((256*4*56)/8) +#define frame_buf_offs 4 + +/* defines for starting Timer3 as CPLD-Clk */ +#define START3 (1 << 16) +#define UPDATE3 (1 << 17) +#define INVERT3 (1 << 18) +#define RELOAD3 (1 << 19) + +/* CPLD-Register for controlling vfd-blank-signal */ +#define VFD_DISABLE (*(volatile uchar *)0x04038000=0x0000) +#define VFD_ENABLE (*(volatile uchar *)0x04038000=0x0001) + +/* Supported VFD Types */ +#define VFD_TYPE_T119C 1 /* Noritake T119C VFD */ +#define VFD_TYPE_MN11236 2 + +/*#define NEW_CPLD_CLK*/ + +int vfd_board_id; + +/* taken from armboot/common/vfd.c */ +unsigned long adr_vfd_table[112][18][2][4][2]; +unsigned char bit_vfd_table[112][18][2][4][2]; + +/* + * initialize the values for the VFD-grid-control in the framebuffer + */ +void init_grid_ctrl(void) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong adr, grid_cycle; + unsigned int bit, display; + unsigned char temp, bit_nr; + + /* + * clear frame buffer (logical clear => set to "black") + */ + memset ((void *)(gd->fb_base), 0, FRAME_BUF_SIZE); + + switch (gd->vfd_type) { + case VFD_TYPE_T119C: + for (display=0; display<4; display++) { + for(grid_cycle=0; grid_cycle<56; grid_cycle++) { + bit = grid_cycle * 256 * 4 + + (grid_cycle + 200) * 4 + + frame_buf_offs + display; + /* wrap arround if offset (see manual S3C2400) */ + if (bit>=FRAME_BUF_SIZE*8) + bit = bit - (FRAME_BUF_SIZE * 8); + adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8); + bit_nr = bit % 8; + bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4; + temp=(*(volatile unsigned char*)(adr)); + temp |= (1<=FRAME_BUF_SIZE*8) + bit = bit-(FRAME_BUF_SIZE*8); + adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8); + bit_nr = bit%8; + bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; + temp=(*(volatile unsigned char*)(adr)); + temp |= (1<=FRAME_BUF_SIZE*8) + bit = bit - (FRAME_BUF_SIZE * 8); + adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8); + bit_nr = bit % 8; + bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4; + temp=(*(volatile unsigned char*)(adr)); + temp |= (1<=FRAME_BUF_SIZE*8) + bit = bit-(FRAME_BUF_SIZE*8); + adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8); + bit_nr = bit%8; + bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; + temp=(*(volatile unsigned char*)(adr)); + temp |= (1<vfd_type) { + case VFD_TYPE_T119C: + for(y=0; y<=17; y++) { /* Line */ + for(x=0; x<=111; x++) { /* Column */ + for(display=0; display <=3; display++) { + + /* Display 0 blue pixels */ + vfd_table[x][y][0][display][0] = + (x==0) ? y*16+display + : (x%4)*4+y*16+((x-1)/2)*1024+display; + /* Display 0 red pixels */ + vfd_table[x][y][1][display][0] = + (x==0) ? y*16+512+display + : (x%4)*4+y*16+((x-1)/2)*1024+512+display; + } + } + } + break; + case VFD_TYPE_MN11236: + for(y=0; y<=17; y++) { /* Line */ + for(x=0; x<=111; x++) { /* Column */ + for(display=0; display <=3; display++) { + + vfd_table[x][y][0][display][0]=0; + vfd_table[x][y][0][display][1]=0; + vfd_table[x][y][1][display][0]=0; + vfd_table[x][y][1][display][1]=0; + + switch (x%6) { + case 0: x_abcdef=0; break; /* a -> a */ + case 1: x_abcdef=2; break; /* b -> c */ + case 2: x_abcdef=4; break; /* c -> e */ + case 3: x_abcdef=5; break; /* d -> f */ + case 4: x_abcdef=3; break; /* e -> d */ + case 5: x_abcdef=1; break; /* f -> b */ + } + + /* blue pixels */ + vfd_table[x][y][0][display][0] = + (x>1) ? x_abcdef*4+((x-1)/3)*1024+y*48+display + : x_abcdef*4+ 0+y*48+display; + /* blue pixels */ + if (x>1 && (x-1)%3) + vfd_table[x][y][0][display][1] = x_abcdef*4+((x-1)/3+1)*1024+y*48+display; + + /* red pixels */ + vfd_table[x][y][1][display][0] = + (x>1) ? x_abcdef*4+24+((x-1)/3)*1024+y*48+display + : x_abcdef*4+24+ 0+y*48+display; + /* red pixels */ + if (x>1 && (x-1)%3) + vfd_table[x][y][1][display][1] = x_abcdef*4+24+((x-1)/3+1)*1024+y*48+display; + } + } + } + break; + default: + /* do nothing */ + return; + } + + /* + * Create table with entries for physical byte adresses and + * bit-number within the byte + * from table with bit-numbers within the total framebuffer + */ + for(y=0;y<18;y++) { + for(x=0;x<112;x++) { + for(color=0;color<2;color++) { + for(display=0;display<4;display++) { + for(entry=0;entry<2;entry++) { + unsigned long adr = gd->fb_base; + unsigned int bit_nr = 0; + + if (vfd_table[x][y][color][display][entry]) { + + pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs; + /* + * wrap arround if offset + * (see manual S3C2400) + */ + if (pixel>=FRAME_BUF_SIZE*8) + pixel = pixel-(FRAME_BUF_SIZE*8); + adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8); + bit_nr = pixel%8; + bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; + } + adr_vfd_table[x][y][color][display][entry] = adr; + bit_vfd_table[x][y][color][display][entry] = bit_nr; + } + } + } + } + } +} + +/* + * Set/clear pixel of the VFDs + */ +void set_vfd_pixel(unsigned char x, unsigned char y, + unsigned char color, unsigned char display, + unsigned char value) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong adr; + unsigned char bit_nr, temp; + + if (! gd->vfd_type) { + /* Unknown type. */ + return; + } + + /* Pixel-Eintrag Nr. 1 */ + adr = adr_vfd_table[x][y][color][display][0]; + /* Pixel-Eintrag Nr. 1 */ + bit_nr = bit_vfd_table[x][y][color][display][0]; + temp=(*(volatile unsigned char*)(adr)); + + if (value) + temp |= (1< 0; height -= 18) + { + if (height > 18) + y = 18; + else + y = height; + for (; y > 0; y--) + { + for (x = 0; x < width; x += 2) + { + temp = *adr++; + set_vfd_pixel(x, y-1, 0, display, 0); + set_vfd_pixel(x, y-1, 1, display, 0); + if ((temp >> 4) == BLAU) + set_vfd_pixel(x, y-1, 0, display, 1); + else if ((temp >> 4) == ROT) + set_vfd_pixel(x, y-1, 1, display, 1); + else if ((temp >> 4) == VIOLETT) + { + set_vfd_pixel(x, y-1, 0, display, 1); + set_vfd_pixel(x, y-1, 1, display, 1); + } + set_vfd_pixel(x+1, y-1, 0, display, 0); + set_vfd_pixel(x+1, y-1, 1, display, 0); + if ((temp & 0x0F) == BLAU) + set_vfd_pixel(x+1, y-1, 0, display, 1); + else if ((temp & 0x0F) == ROT) + set_vfd_pixel(x+1, y-1, 1, display, 1); + else if ((temp & 0x0F) == VIOLETT) + { + set_vfd_pixel(x+1, y-1, 0, display, 1); + set_vfd_pixel(x+1, y-1, 1, display, 1); + } + } + } + if (display > 0) + display--; + else + display = 3; + } +} + +/* + * This function initializes VFD clock that is needed for the CPLD that + * manages the keyboard. + */ +int vfd_init_clocks (void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); + S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); + + /* try to determine display type from the value + * defined by pull-ups + */ + gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */ + gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */ + udelay (10); /* allow signals to settle */ + vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */ + + VFD_DISABLE; /* activate blank for the vfd */ + +#define NEW_CPLD_CLK + +#ifdef NEW_CPLD_CLK + if (vfd_board_id) { + /* If new board revision, then use PWM 3 as cpld-clock */ + /* Enable 500 Hz timer for fill level sensor to operate properly */ + /* Configure TOUT3 as functional pin, disable pull-up */ + gpio->PDCON &= ~0x30000; + gpio->PDCON |= 0x20000; + gpio->PDUP |= (1 << 8); + + /* Configure the prescaler */ + timers->TCFG0 &= ~0xff00; + timers->TCFG0 |= 0x0f00; + + /* Select MUX input (divider) for timer3 (1/16) */ + timers->TCFG1 &= ~0xf000; + timers->TCFG1 |= 0x3000; + + /* Enable autoreload and set the counter and compare + * registers to values for the 500 Hz clock + * (for a given prescaler (15) and divider (16)): + * counter = (66000000 / 500) >> 9; + */ + timers->ch[3].TCNTB = 0x101; + timers->ch[3].TCMPB = 0x101 / 2; + + /* Start timer */ + timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; + timers->TCON = (timers->TCON | START3) & ~UPDATE3; + } +#endif + /* If old board revision, then use vm-signal as cpld-clock */ + lcd->LCDCON2 = 0x00FFC000; + lcd->LCDCON3 = 0x0007FF00; + lcd->LCDCON4 = 0x00000000; + lcd->LCDCON5 = 0x00000400; + lcd->LCDCON1 = 0x00000B75; + /* VM (GPD1) is used as clock for the CPLD */ + gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008; + + return 0; +} + +/* + * initialize LCD-Controller of the S3C2400 for using VFDs + * + * VFD detection depends on the board revision: + * starting from Rev. 200 a type code can be read from the data pins, + * driven by some pull-up resistors; all earlier systems must be + * manually configured. The type is set in the "vfd_type" environment + * variable. + */ +int drv_vfd_init(void) +{ + S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + char *tmp; + ulong palette; + static int vfd_init_done = 0; + int vfd_inv_data = 0; + + DECLARE_GLOBAL_DATA_PTR; + + if (vfd_init_done != 0) + return (0); + vfd_init_done = 1; + + debug("Detecting Revison of WA4-VFD: ID=0x%X\n", vfd_board_id); + + switch (vfd_board_id) { + case 0: /* board revision < Rev.200 */ + if ((tmp = getenv ("vfd_type")) == NULL) { + break; + } + if (strcmp(tmp, "T119C") == 0) { + gd->vfd_type = VFD_TYPE_T119C; + } else if (strcmp(tmp, "MN11236") == 0) { + gd->vfd_type = VFD_TYPE_MN11236; + } else { + /* cannot use printf for a warning here */ + gd->vfd_type = 0; /* unknown */ + } + + break; + default: /* default to MN11236, data inverted */ + gd->vfd_type = VFD_TYPE_MN11236; + vfd_inv_data = 1; + setenv ("vfd_type", "MN11236"); + } + debug ("VFD type: %s%s\n", + (gd->vfd_type == VFD_TYPE_T119C) ? "T119C" : + (gd->vfd_type == VFD_TYPE_MN11236) ? "MN11236" : + "unknown", + vfd_inv_data ? ", inverted data" : ""); + + gd->fb_base = gd->fb_base; + create_vfd_table(); + init_grid_ctrl(); + + for (palette=0; palette < 16; palette++) + (*(volatile unsigned int*)(PALETTE+(palette*4)))=palette; + for (palette=16; palette < 256; palette++) + (*(volatile unsigned int*)(PALETTE+(palette*4)))=0x00; + + /* + * Hinweis: Der Framebuffer ist um genau ein Nibble verschoben + * Das erste angezeigte Pixel wird aus dem zweiten Nibble geholt + * das letzte angezeigte Pixel wird aus dem ersten Nibble geholt + * (wrap around) + * see manual S3C2400 + */ + /* Stopp LCD-Controller */ + lcd->LCDCON1 = 0x00000000; + /* frame buffer startadr */ + lcd->LCDSADDR1 = gd->fb_base >> 1; + /* frame buffer endadr */ + lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; + lcd->LCDSADDR3 = ((256/4)); + lcd->LCDCON2 = 0x000DC000; + if(gd->vfd_type == VFD_TYPE_MN11236) + lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */ + else + lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */ + lcd->LCDCON3 = 0x0051000A; + lcd->LCDCON4 = 0x00000001; + if (gd->vfd_type && vfd_inv_data) + lcd->LCDCON5 = 0x000004C0; + else + lcd->LCDCON5 = 0x00000440; + + /* Port pins as LCD output */ + gpio->PCCON = (gpio->PCCON & 0xFFFFFF00)| 0x000000AA; + gpio->PDCON = (gpio->PDCON & 0xFFFFFF03)| 0x000000A8; + + /* Synchronize VFD enable with LCD controller to avoid flicker */ + lcd->LCDCON1 = 0x00000B75; /* Start LCD-Controller */ + while((lcd->LCDCON5 & 0x180000)!=0x100000); /* Wait for end of VSYNC */ + while((lcd->LCDCON5 & 0x060000)!=0x040000); /* Wait for next HSYNC */ + while((lcd->LCDCON5 & 0x060000)==0x040000); + while((lcd->LCDCON5 & 0x060000)!=0x000000); + if(gd->vfd_type) + VFD_ENABLE; + + debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1); + debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2); + debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3); + + return 0; +} + +/* + * Disable VFD: should be run before resetting the system: + * disable VM, enable pull-up + */ +void disable_vfd (void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + VFD_DISABLE; + gpio->PDCON &= ~0xC; + gpio->PDUP &= ~0x2; +} + +/************************************************************************/ +/* ** ROM capable initialization part - needed to reserve FB memory */ +/************************************************************************/ + +/* + * This is called early in the system initialization to grab memory + * for the VFD controller. + * + * Note that this is running from ROM, so no write access to global data. + */ +ulong vfd_setmem (ulong addr) +{ + ulong size; + + /* Round up to nearest full page */ + size = (FRAME_BUF_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); + + debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr); + + return (size); +} + +/* + * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, + * descriptors and palette areas. + */ +ulong calc_fbsize (void) +{ + return FRAME_BUF_SIZE; +} + +#endif /* CONFIG_VFD */ diff --git a/board/uc100/Makefile b/board/uc100/Makefile new file mode 100644 index 0000000..eb81625 --- /dev/null +++ b/board/uc100/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +#OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/uc100/config.mk b/board/uc100/config.mk new file mode 100644 index 0000000..a65a8ba --- /dev/null +++ b/board/uc100/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# UC100 boards +# + +#TEXT_BASE = 0x40000000 +TEXT_BASE = 0x40700000 diff --git a/board/uc100/u-boot.lds b/board/uc100/u-boot.lds new file mode 100644 index 0000000..d7c798e --- /dev/null +++ b/board/uc100/u-boot.lds @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/uc100/u-boot.lds.debug b/board/uc100/u-boot.lds.debug new file mode 100644 index 0000000..d9bb868 --- /dev/null +++ b/board/uc100/u-boot.lds.debug @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c new file mode 100644 index 0000000..4f2cff6 --- /dev/null +++ b/board/uc100/uc100.c @@ -0,0 +1,282 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include + +int fec8xx_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); + +/*********************************************************************/ +/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */ +/*********************************************************************/ +const uint sdram_init_upm_table[] = { + /* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */ + /* NOP - Precharge - AutoRefr - NOP - NOP */ + /* NOP - AutoRefr - NOP */ + /* NOP - NOP - LoadModeR - NOP - Active */ + /* Position of Single Read */ + 0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04, + 0x0ffffc04, 0x0ff5fc04, 0x0ffffc04, + + /* Burst Read. (offset 8 in UPMA RAM) */ + /* Cycle lent for Initialisation WV */ + 0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Single Write. (offset 18 in UPMA RAM) */ + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Burst Write. (offset 20 in UPMA RAM) */ + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Refresh (offset 30 in UPMA RAM) */ + 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04, + 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, + + /* Exception. (offset 3c in UPMA RAM) */ + 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +}; + +/*********************************************************************/ +/* UPMA initilization table. */ +/*********************************************************************/ +const uint sdram_upm_table[] = { + /* single read. (offset 0 in UPMA RAM) */ + 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */ + + /* Burst Read. (offset 8 in UPMA RAM) */ + 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00, + 0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Single Write. (offset 18 in UPMA RAM) */ + 0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04, + 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Burst Write. (offset 20 in UPMA RAM) */ + 0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00, + 0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Refresh (offset 30 in UPMA RAM) */ + 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04, + 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, + + /* Exception. (offset 3c in UPMA RAM) */ + 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */ +}; + +/*********************************************************************/ +/* UPMB initilization table. */ +/*********************************************************************/ +const uint mpm_upm_table[] = { + /* single read. (offset 0 in upm RAM) */ + 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001, + 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* burst read. (Offset 8 in upm RAM) */ + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* single write. (Offset 0x18 in upm RAM) */ + 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004, + 0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, + + /* burst write. (Offset 0x20 in upm RAM) */ + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Refresh cycle, offset 0x30 */ + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Exception, 0ffset 0x3C */ + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +}; + + +int board_switch(void) +{ + volatile pcmconf8xx_t *pcmp; + + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + return ((pcmp->pcmc_pipr >> 24) & 0xf); +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming UC100"); + } else { + puts(str); + } + + printf (" (SWITCH=%1X)\n", board_switch()); + + return 0; +} + + +/* + * Initialize SDRAM + */ +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /*---------------------------------------------------------------------*/ + /* Initialize the UPMA/UPMB registers with the appropriate table. */ + /*---------------------------------------------------------------------*/ + upmconfig (UPMA, (uint *) sdram_init_upm_table, + sizeof (sdram_init_upm_table) / sizeof (uint)); + upmconfig (UPMB, (uint *) mpm_upm_table, + sizeof (mpm_upm_table) / sizeof (uint)); + + /*---------------------------------------------------------------------*/ + /* Memory Periodic Timer Prescaler: divide by 16 */ + /*---------------------------------------------------------------------*/ + memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */ + + memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */ + memctl->memc_mbmr = CFG_MBMR_VAL; + + /*---------------------------------------------------------------------*/ + /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */ + /* for SDRAM */ + /* */ + /* NOTE: The refresh rate in MAMR reg is set according to the lowest */ + /* clock rate (16.67MHz) to allow proper operation for all ADS */ + /* clock frequencies. */ + /*---------------------------------------------------------------------*/ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + /*-------------------------------------------------------------------*/ + /* Wait at least 200 usec for DRAM to stabilize, this magic number */ + /* obtained from the init code. */ + /*-------------------------------------------------------------------*/ + udelay(200); + + memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08; + + memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CFG_OR1_PRELIM; + + /*---------------------------------------------------------------------*/ + /* run MRS command in location 5-8 of UPMB. */ + /*---------------------------------------------------------------------*/ + memctl->memc_mar = 0x88; + /* RUN UPMA on CS1 1-time from UPMA addr 0x05 */ + + memctl->memc_mcr = 0x80002100; + /* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */ + + udelay(200); + + /*---------------------------------------------------------------------*/ + /* Initialisation for normal access WV */ + /*---------------------------------------------------------------------*/ + + /*---------------------------------------------------------------------*/ + /* Initialize the UPMA register with the appropriate table. */ + /*---------------------------------------------------------------------*/ + upmconfig (UPMA, (uint *) sdram_upm_table, + sizeof (sdram_upm_table) / sizeof (uint)); + + /*---------------------------------------------------------------------*/ + /* rerstore MBMR value (4-beat refresh burst.) */ + /*---------------------------------------------------------------------*/ + memctl->memc_mamr = CFG_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */ + + udelay(200); + + return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */ +} + + +int misc_init_r (void) +{ + uchar val; + + /* + * Make sure that RTC has clock output enabled (triggers watchdog!) + */ + val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D); + val |= 0x80; + i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val); + + /* + * Configure PHY to setup LED's correctly and use 100MBit, FD + */ + mii_init(); + + /* disable auto-negotiation, 100mbit, full-duplex */ + fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100); + + /* set LED's to Link, Transmit, Receive */ + fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122); + + return 0; +} + + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed (void) +{ + return 0; /* No hotkeys supported */ +} +#endif diff --git a/board/utx8245/Makefile b/board/utx8245/Makefile new file mode 100644 index 0000000..e698afc --- /dev/null +++ b/board/utx8245/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Gregory E. Allen, gallen@arlut.utexas.edu +# Matthew E. Karger, karger@arlut.utexas.edu +# Applied Research Laboratories, The University of Texas at Austin +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +SOBJS = + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/utx8245/config.mk b/board/utx8245/config.mk new file mode 100644 index 0000000..a33faa7 --- /dev/null +++ b/board/utx8245/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Gregory E. Allen, gallen@arlut.utexas.edu +# Matthew E. Karger, karger@arlut.utexas.edu +# Applied Research Laboratories, The University of Texas at Austin +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# UTX8245 boards +# +TEXT_BASE = 0xFFF00000 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c new file mode 100644 index 0000000..3271827 --- /dev/null +++ b/board/utx8245/flash.c @@ -0,0 +1,560 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Gregory E. Allen, gallen@arlut.utexas.edu + * Matthew E. Karger, karger@arlut.utexas.edu + * Applied Research Laboratories, The University of Texas at Austin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define ROM_CS0_START 0xFF800000 +#define ROM_CS1_START 0xFF000000 + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#define FLASH_BANK_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ +#define MAIN_SECT_SIZE 0x10000 +#define SECT_SIZE_32KB 0x8000 +#define SECT_SIZE_8KB 0x2000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static int write_word (flash_info_t * info, ulong dest, ulong data); +#if 0 +static void write_via_fpu (vu_long * addr, ulong * data); +#endif +static __inline__ unsigned long get_msr (void); +static __inline__ void set_msr (unsigned long msr); + +/*flash command address offsets*/ +#define ADDR0 (0x555) +#define ADDR1 (0xAAA) +#define ADDR3 (0x001) + +#define FLASH_WORD_SIZE unsigned char + +/*---------------------------------------------------------------------*/ +/*#define DEBUG_FLASH 1 */ + +/*---------------------------------------------------------------------*/ + +unsigned long flash_init (void) +{ + int i; /* flash bank counter */ + int j; /* flash device sector counter */ + int k; /* flash size calculation loop counter */ + int N; /* pow(2,N) is flash size, but we don't have */ + ulong total_size = 0, device_size = 1; + unsigned char manuf_id, device_id; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + vu_char *addr = (vu_char *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + + addr[0x555] = 0xAA; /* get manuf/device info command */ + addr[0x2AA] = 0x55; /* 3-cycle command */ + addr[0x555] = 0x90; + + manuf_id = addr[0]; /* read back manuf/device info */ + device_id = addr[1]; + + addr[0x55] = 0x98; /* CFI command */ + N = addr[0x27]; /* read back device_size = pow(2,N) */ + + for (k = 0; k < N; k++) /* calculate device_size = pow(2,N) */ + device_size *= 2; + + flash_info[i].size = device_size; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + +#if defined DEBUG_FLASH + printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id); +#endif + /* find out what kind of flash we are using */ + if ((manuf_id == (uchar) (AMD_MANUFACT)) + && (device_id == AMD_ID_LV033C)) { + flash_info[i].flash_id = + ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | + (FLASH_AM033C & FLASH_TYPEMASK); + + /* set individual sector start addresses */ + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = + (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE); + } + } + + else if ((manuf_id == (uchar) (AMD_MANUFACT)) && + (device_id == AMD_ID_LV116DT)) { + flash_info[i].flash_id = + ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | + (FLASH_AM160T & FLASH_TYPEMASK); + + /* set individual sector start addresses */ + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = + (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE); + + if (j < (CFG_MAX_FLASH_SECT - 3)) { + flash_info[i].start[j] = + (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE); + } else if (j == (CFG_MAX_FLASH_SECT - 3)) { + flash_info[i].start[j] = + (flash_info[i].start[j - 1] + SECT_SIZE_32KB); + + } else { + flash_info[i].start[j] = + (flash_info[i].start[j - 1] + SECT_SIZE_8KB); + } + } + } + + else { + flash_info[i].flash_id = FLASH_UNKNOWN; + addr[0] = 0xFF; + goto Done; + } + +#if defined DEBUG_FLASH + printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id); +#endif + + addr[0] = 0xFF; + + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + + total_size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) + flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + + Done: + return total_size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + static const char unk[] = "Unknown"; + const char *mfct = unk, *type = unk; + unsigned int i; + + if (info->flash_id != FLASH_UNKNOWN) { + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + mfct = "AMD"; + break; + case FLASH_MAN_FUJ: + mfct = "FUJITSU"; + break; + case FLASH_MAN_STM: + mfct = "STM"; + break; + case FLASH_MAN_SST: + mfct = "SST"; + break; + case FLASH_MAN_BM: + mfct = "Bright Microelectonics"; + break; + case FLASH_MAN_INTEL: + mfct = "Intel"; + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM033C: + type = "AM29LV033C (32 Mbit, uniform sector size)"; + break; + case FLASH_AM160T: + type = "AM29LV160T (16 Mbit, top boot sector)"; + break; + case FLASH_AM040: + type = "AM29F040B (512K * 8, uniform sector size)"; + break; + case FLASH_AM400B: + type = "AM29LV400B (4 Mbit, bottom boot sect)"; + break; + case FLASH_AM400T: + type = "AM29LV400T (4 Mbit, top boot sector)"; + break; + case FLASH_AM800B: + type = "AM29LV800B (8 Mbit, bottom boot sect)"; + break; + case FLASH_AM800T: + type = "AM29LV800T (8 Mbit, top boot sector)"; + break; + case FLASH_AM320B: + type = "AM29LV320B (32 Mbit, bottom boot sect)"; + break; + case FLASH_AM320T: + type = "AM29LV320T (32 Mbit, top boot sector)"; + break; + case FLASH_STM800AB: + type = "M29W800AB (8 Mbit, bottom boot sect)"; + break; + case FLASH_SST800A: + type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; + break; + case FLASH_SST160A: + type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; + break; + } + } + + printf ("\n Brand: %s Type: %s\n" + " Size: %lu KB in %d Sectors\n", + mfct, type, info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; i++) { + unsigned long size; + unsigned int erased; + unsigned long *flash = (unsigned long *) info->start[i]; + + /* + * Check if whole sector is erased + */ + size = (i != (info->sector_count - 1)) ? + (info->start[i + 1] - info->start[i]) >> 2 : + (info->start[0] + info->size - info->start[i]) >> 2; + + for (flash = (unsigned long *) info->start[i], erased = 1; + (flash != (unsigned long *) info->start[i] + size) && erased; + flash++) + erased = *flash == ~0x0UL; + + printf ("%s %08lX %s %s", + (i % 5) ? "" : "\n ", + info->start[i], + erased ? "E" : " ", info->protect[i] ? "RO" : " "); + } + + puts ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + unsigned char sh8b; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) + && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info-> + start[sect] - + info-> + start[0]) << + sh8b)); + + if (info->flash_id & FLASH_MAN_SST) { + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ + udelay (30000); /* wait 30 ms */ + } else { + addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - + info-> + start[0]) << sh8b)); + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; + volatile FLASH_WORD_SIZE *dest2; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int flag; + int i; + unsigned char sh8b; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) + && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; + + dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + + info->start[0]); + + /* Check if Flash is (sufficiently) erased */ + if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i << sh8b] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ +#if 0 +static void write_via_fpu (vu_long * addr, ulong * data) +{ + __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); + __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); +} +#endif + +/*----------------------------------------------------------------------- + */ +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + return msr; +} + +static __inline__ void set_msr (unsigned long msr) +{ + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); +} diff --git a/board/utx8245/u-boot.lds b/board/utx8245/u-boot.lds new file mode 100644 index 0000000..45f3018 --- /dev/null +++ b/board/utx8245/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Gregory E. Allen, gallen@arlut.utexas.edu + * Matthew E. Karger, karger@arlut.utexas.edu + * Applied Research Laboratories, The University of Texas at Austin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c new file mode 100644 index 0000000..834fd84 --- /dev/null +++ b/board/utx8245/utx8245.c @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2002 + * Gregory E. Allen, gallen@arlut.utexas.edu + * Matthew E. Karger, karger@arlut.utexas.edu + * Applied Research Laboratories, The University of Texas at Austin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#define SAVE_SZ 32 + + +int checkboard(void) +{ + ulong busfreq = get_bus_freq(0); + char buf[32]; + + printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq)); + return 0; +} + + +long int initdram(int board_type) +{ + long size; + long new_bank0_end; + long new_bank1_end; + long mear1; + long emear1; + + size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + + new_bank0_end = size/2 - 1; + new_bank1_end = size - 1; + mear1 = mpc824x_mpc107_getreg(MEAR1); + emear1 = mpc824x_mpc107_getreg(EMEAR1); + + mear1 = (mear1 & 0xFFFF0000) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + ((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8); + emear1 = (emear1 & 0xFFFF0000) | + ((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + ((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8); + + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + return (size); +} + + +/* + * Initialize PCI Devices, report devices found. + */ + +static struct pci_config_table pci_utx8245_config_table[] = { +#ifndef CONFIG_PCI_PNP + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR, + PCI_FIREWIRE_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, +#endif /*CONFIG_PCI_PNP*/ + { } +}; + + +static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + if (PCI_DEV(dev) == 11) + /* assign serial interrupt line 9 (int25) to FireWire */ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25); + + else if (PCI_DEV(dev) == 12) + /* assign serial interrupt line 8 (int24) to Ethernet */ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24); + + else if (PCI_DEV(dev) == 14) + /* assign serial interrupt line 0 (int16) to PMC slot 0 */ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16); + + else if (PCI_DEV(dev) == 15) + /* assign serial interrupt line 1 (int17) to PMC slot 1 */ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17); +} + +static struct pci_controller utx8245_hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_utx8245_config_table, + fixup_irq: pci_utx8245_fixup_irq, + write_byte: pci_hose_write_config_byte +#endif /*CONFIG_PCI_PNP*/ +}; + +void pci_init_board (void) +{ + pci_mpc824x_init(&utx8245_hose); + + icache_enable(); +} diff --git a/board/v37/Makefile b/board/v37/Makefile new file mode 100644 index 0000000..7a17067 --- /dev/null +++ b/board/v37/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/v37/config.mk b/board/v37/config.mk new file mode 100644 index 0000000..50cac97 --- /dev/null +++ b/board/v37/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Marel V37 boards +# +TEXT_BASE = 0x40000000 diff --git a/board/v37/flash.c b/board/v37/flash.c new file mode 100644 index 0000000..6a31972 --- /dev/null +++ b/board/v37/flash.c @@ -0,0 +1,559 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * U-Boot port on RPXlite board + * + * Some of flash control words are modified. (from 2x16bit device + * to 4x8bit device) + * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices + * are not tested. + * + * (?) Does an RPXLite board which + * does not use AM29LV800 flash memory exist ? + * I don't know... + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips); +static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id); +static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + short manu, dev_id; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (0 - size_b0); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE0 + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + + flash_get_id_long((void*)CFG_FLASH_BASE1,&manu,&dev_id); + + size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]); + + flash_get_offsets(CFG_FLASH_BASE1, &flash_info[1],1); + + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (0 - size_b1); + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0+size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips) +{ + int i, addr_shift; + vu_short *addr = (vu_short*)base; + + addr[0x555] = 0x00AA ; + addr[0xAAA] = 0x0055 ; + addr[0x555] = 0x0090 ; + + addr_shift = (two_chips ? 2 : 1 ); + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + (0x00000000<start[1] = base + (0x00002000<start[2] = base + (0x00003000<start[3] = base + (0x00004000<sector_count; i++) { + info->start[i] = base + ((i-3) * (0x00008000<sector_count - 1; + info->start[i--] = base + info->size - (0x00002000<start[i--] = base + info->size - (0x00003000<start[i--] = base + info->size - (0x00004000<= 0; i--) { + info->start[i] = base + i * (0x00008000<sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (vu_short *)(info->start[i]); + info->protect[i] = addr[1<start[0]; + *addr = 0xF0F0; /* reset bank */ +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_TOSH: printf ("TOSHIBA "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id) +{ + vu_short *addr = (vu_short*)ptr; + + addr[0x555] = 0x00AA ; + addr[0xAAA] = 0x0055 ; + addr[0x555] = 0x0090 ; + + *ptr_manuf = addr[0]; + *ptr_dev_id = addr[1]; + + addr[0] = 0xf0f0; /* return to normal */ +} + +static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id) +{ + vu_short *addr = (vu_short*)ptr; + vu_short *addr1, *addr2, *addr3; + + addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); + addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) ); + addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); + + *addr1 = 0xAAAA; + *addr2 = 0x5555; + *addr3 = 0x9090; + + *ptr_manuf = addr[0]; + *ptr_dev_id = addr[2]; + + addr[0] = 0xf0f0; /* return to normal */ +} + +static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info) +{ + switch (manu) { + case ((short)AMD_MANUFACT): + info->flash_id = FLASH_MAN_AMD; + break; + case ((short)FUJ_MANUFACT): + info->flash_id = FLASH_MAN_FUJ; + break; + case ((short)TOSH_MANUFACT): + info->flash_id = FLASH_MAN_TOSH; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + + switch (dev_id) { + case ((short)TOSH_ID_FVT160): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 1 MB */ + + case ((short)TOSH_ID_FVB160): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 1 MB */ + + case ((short)AMD_ID_LV400T): + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case ((short)AMD_ID_LV400B): + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case ((short)AMD_ID_LV800T): + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case ((short)AMD_ID_LV800B): + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00400000; /*%%% Size doubled by yooth */ + break; /* => 4 MB */ + + case ((short)AMD_ID_LV160T): + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 4 MB */ + + case ((short)AMD_ID_LV160B): + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 4 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_short *addr = (vu_short*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x555] = (vu_short)0xAAAAAAAA; + addr[0xAAA] = (vu_short)0x55555555; + addr[0x555] = (vu_short)0x80808080; + addr[0x555] = (vu_short)0xAAAAAAAA; + addr[0xAAA] = (vu_short)0x55555555; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_short *)(info->start[sect]) ; + addr[0] = (vu_short)0x30303030 ; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_short *)(info->start[l_sect]); + while ((addr[0] & 0x8080) != 0x8080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (vu_short *)info->start[0]; + addr[0] = (vu_short)0xF0F0F0F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_short *addr = (vu_short *)(info->start[0]); + vu_short sdata; + + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + /* First write upper 16 bits */ + sdata = (short)(data>>16); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x555] = 0xAAAA; + addr[0xAAA] = 0x5555; + addr[0x555] = 0xA0A0; + + *((vu_short *)dest) = sdata; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + + /* Now write lower 16 bits */ + sdata = (short)(data&0xffff); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x555] = 0xAAAA; + addr[0xAAA] = 0x5555; + addr[0x555] = 0xA0A0; + + *((vu_short *)dest + 1) = sdata; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds new file mode 100644 index 0000000..f9722db --- /dev/null +++ b/board/v37/u-boot.lds @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + +/* + . = env_offset; +*/ + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/v37/v37.c b/board/v37/v37.c new file mode 100644 index 0000000..1ef879d --- /dev/null +++ b/board/v37/v37.c @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * U-Boot port on RPXlite board + * + * DRAM related UPMA register values are modified. + * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS + */ + +#include +#include "mpc8xx.h" + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (void); + +/* ------------------------------------------------------------------------- */ + +#define MBYTE (1024*1024) +#define DRAM_DELAY 0x00000379 /* DRAM delay count */ +#define _NOT_USED_ 0xFFFFCC25 + +const uint sdram_table[] = +{ + /* single read. (offset 0 in upm RAM) */ + 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000, + 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, + + /* burst read. (Offset 8 in upm RAM) */ + 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000, + 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* single write. (Offset 0x18 in upm RAM) */ + 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* burst write. (Offset 0x20 in upm RAM) */ + 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000, + 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Refresh cycle, offset 0x30 */ + 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + + /* Exception, 0ffset 0x3C */ + 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +}; +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Return 1 for now. + * + */ + +int checkboard (void) +{ + printf("Marel V37\n") ; + return (0) ; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long temp; + volatile int delay_cnt; + long int ramsize; + + ramsize = dram_size(); + + /* Refresh clock prescalar */ + memctl->memc_mptpr = 0x400 ; + + if( ramsize == 32*MBYTE ) + temp = 0xd0904110; + else /* 16MB */ + temp = 0xd0802110; + + memctl->memc_mbmr = temp; + + upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + /* Map controller banks 2 to the SDRAM bank */ + memctl->memc_or2 = 0xA00 | (0 - ramsize); + memctl->memc_br2 = 0xC1; + + memctl->memc_mbmr = temp | 0x08; + memctl->memc_mcr = 0x80804130; + + delay_cnt = 0; + while( delay_cnt++ < DRAM_DELAY ) + ; + + /* Run MRS command in location 5-8 of UPMB */ + + memctl->memc_mbmr = temp | 0x04; + memctl->memc_mar = 0x88; + + memctl->memc_mcr = 0x80804105; + + delay_cnt = 0; + while( delay_cnt++ < DRAM_DELAY ) + ; + +#ifdef CONFIG_CAN_DRIVER + /* Initialize OR3 / BR3 */ + memctl->memc_or3 = CFG_OR3_CAN; + memctl->memc_br3 = CFG_BR3_CAN; + + /* Initialize MBMR */ + memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */ + + /* Initialize UPMB for CAN: single read */ + memctl->memc_mdr = 0xFFFFC004; + memctl->memc_mcr = 0x0100 | UPMA; + + memctl->memc_mdr = 0x0FFFD004; + memctl->memc_mcr = 0x0101 | UPMA; + + memctl->memc_mdr = 0x0FFFC000; + memctl->memc_mcr = 0x0102 | UPMA; + + memctl->memc_mdr = 0x3FFFC004; + memctl->memc_mcr = 0x0103 | UPMA; + + memctl->memc_mdr = 0xFFFFDC05; + memctl->memc_mcr = 0x0104 | UPMA; + + /* Initialize UPMB for CAN: single write */ + memctl->memc_mdr = 0xFFFCC004; + memctl->memc_mcr = 0x0118 | UPMA; + + memctl->memc_mdr = 0xCFFCD004; + memctl->memc_mcr = 0x0119 | UPMA; + + memctl->memc_mdr = 0x0FFCC000; + memctl->memc_mcr = 0x011A | UPMA; + + memctl->memc_mdr = 0x7FFCC004; + memctl->memc_mcr = 0x011B | UPMA; + + memctl->memc_mdr = 0xFFFDCC05; + memctl->memc_mcr = 0x011C | UPMA; +#endif /* CONFIG_CAN_DRIVER */ + + return (dram_size()); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Find size of RAM from configuration pins. + * The input pins that contain the memory size are also the debug port + * pins. Normally they are configured as debug port pins. To be able + * to read the memory configuration, we must deactivate the debug port + * and enable the pcmcia input pins. Then return the register to + * previous state. + */ + +static long int dram_size () +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile sysconf8xx_t *siu = &immap->im_siu_conf; + volatile pcmconf8xx_t *pcm = &immap->im_pcmcia; + long int i, memory=1; + unsigned long siu_mcr; + + siu_mcr = siu->sc_siumcr; + siu->sc_siumcr = siu_mcr & 0xFF9FFFFF; + for(i=0; i<10; i++) i = i; + + memory = (pcm->pcmc_pipr>>12) & 0x3; + + siu->sc_siumcr = siu_mcr; + + switch( memory ) + { + case 1: + return( 32*MBYTE ); + case 2: + return( 64*MBYTE ); + default: + break; + } + return( 16*MBYTE ); +} diff --git a/board/versatile/Makefile b/board/versatile/Makefile new file mode 100644 index 0000000..fbdc627 --- /dev/null +++ b/board/versatile/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := versatile.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/versatile/config.mk b/board/versatile/config.mk new file mode 100644 index 0000000..25b79b3 --- /dev/null +++ b/board/versatile/config.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x01000000 +# + +TEXT_BASE = 0x01000000 diff --git a/board/versatile/flash.c b/board/versatile/flash.c new file mode 100644 index 0000000..7153371 --- /dev/null +++ b/board/versatile/flash.c @@ -0,0 +1,514 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256K3[] = { + {256, 128 * 1024}, /* 256 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); + +/*----------------------------------------------------------------------- + */ + +static void flash_vpp(int on) +{ + unsigned int tmp; + + tmp = *(unsigned int *)(VERSATILE_FLASHCTRL); + + if (on) + tmp |= VERSATILE_FLASHPROG_FLVPPEN; + else + tmp &= ~VERSATILE_FLASHPROG_FLVPPEN; + + *(unsigned int *)(VERSATILE_FLASHCTRL) = tmp; +} + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_vpp(1); + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + flash_vpp(0); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + OrgDef *pOrgDef; + + pOrgDef = OrgIntel_28F256K3; + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 255) { + info->start[i] = base + (i * 0x8000); + info->protect[i] = 0; + } else { + info->start[i] = base + + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + case FLASH_28F256K3: + printf ("FLASH 28F256K3\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; + info->size = 0x02000000; + break; /* => 32 MB */ + + case (FPW)(INTEL_ID_28F256K3): + info->flash_id += FLASH_28F256K3; + info->sector_count = 256; + info->size = 0x02000000; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + flash_vpp(1); + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } + + flash_vpp(0); + + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + flash_vpp(1); + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + flash_vpp(0); + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + flash_vpp(0); + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + flash_vpp(0); + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + rc = write_data (info, wp, SWAP (data)); + + flash_vpp(0); + + return rc; +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + + flash_vpp(1); + + flash_unprotect_sectors (addr); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + flash_vpp(0); + return (1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + flash_vpp(0); + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/versatile/lowlevel_init.S b/board/versatile/lowlevel_init.S new file mode 100644 index 0000000..bdfce2d --- /dev/null +++ b/board/versatile/lowlevel_init.S @@ -0,0 +1,34 @@ +/* + * Board specific setup info + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + + /* All done by Versatile's boot monitor! */ + mov pc, lr diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh new file mode 100755 index 0000000..35c663e --- /dev/null +++ b/board/versatile/split_by_variant.sh @@ -0,0 +1,40 @@ +#!/bin/sh +# --------------------------------------------------------- +# Set the core module defines according to Core Module +# --------------------------------------------------------- +# --------------------------------------------------------- +# Set up the Versatile type define +# --------------------------------------------------------- +variant=PB926EJ-S +if [ "$1" == "" ] +then + echo "$0:: No parameters - using versatilepb_config" + echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h + variant=PB926EJ-S +else + case "$1" in + versatilepb_config | \ + versatile_config) + echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h + ;; + + versatileab_config) + echo "#define CONFIG_ARCH_VERSATILE_AB" > ./include/config.h + variant=AB926EJ-S + ;; + + + *) + echo "$0:: Unrecognised config - using versatilepb_config" + echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h + variant=PB926EJ-S + ;; + + esac + +fi +# --------------------------------------------------------- +# Complete the configuration +# --------------------------------------------------------- +./mkconfig -a versatile arm arm926ejs versatile +echo "Variant:: $variant" diff --git a/board/versatile/u-boot.lds b/board/versatile/u-boot.lds new file mode 100644 index 0000000..cb6ee18 --- /dev/null +++ b/board/versatile/u-boot.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c new file mode 100644 index 0000000..0274027 --- /dev/null +++ b/board/versatile/versatile.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +void flash__init (void); +void ether__init (void); +void peripheral_power_enable (void); + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + + /* + * set clock frequency: + * VERSATILE_REFCLK is 32KHz + * VERSATILE_TIMCLK is 1MHz + */ + *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |= + ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel)); + + /* arch number of Versatile Board */ + gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + gd->flags = 0; + + icache_enable (); + + flash__init (); + ether__init (); + return 0; +} + + +int misc_init_r (void) +{ + setenv("verify", "n"); + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ +} +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + return 0; +} diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile new file mode 100644 index 0000000..6302fa8 --- /dev/null +++ b/board/voiceblue/Makefile @@ -0,0 +1,66 @@ +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de +# +# (C) Copyright 2005 +# Ladislav Michl, 2N Telekomunikace, michl@2n.cz +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := voiceblue.o +SOBJS := setup.o + +gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) + +LOAD_ADDR = 0x10400000 +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds + +all: $(LIB) eeprom.srec eeprom.bin + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +eeprom.srec: eeprom.o eeprom_start.o + $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ + -o $(<:.o=) -e $(<:.o=) $^ \ + -L../../examples -lstubs \ + -L../../lib_generic -lgeneric \ + -L$(gcclibdir) -lgcc + $(OBJCOPY) -O srec $(<:.o=) $@ + +eeprom.bin: eeprom.srec + $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null + +clean: + rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin + +distclean: clean + rm -f $(LIB) core config.tmp *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/voiceblue/config.mk b/board/voiceblue/config.mk new file mode 100644 index 0000000..c73cd27 --- /dev/null +++ b/board/voiceblue/config.mk @@ -0,0 +1,16 @@ +# +# Linux-Kernel is expected to be at 1000'8000, +# entry 1000'8000 (mem base + reserved) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifeq ($(VOICEBLUE_SMALL_FLASH),y) +# We load ourself to internal SRAM at 2001'2000 +# Check map file when changing TEXT_BASE. +# Everything has fit into 192kB internal SRAM! +TEXT_BASE = 0x20012000 +else +# Running in SDRAM... +TEXT_BASE = 0x13000000 +endif diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c new file mode 100644 index 0000000..0ad1b66 --- /dev/null +++ b/board/voiceblue/eeprom.c @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, michl@2n.cz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Some code shamelessly stolen back from Robin Getz. + */ + +#define DEBUG + +#include +#include +#include "../drivers/smc91111.h" + +#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE + +static u16 read_eeprom_reg(u16 reg) +{ + int timeout; + + SMC_SELECT_BANK(2); + SMC_outw(reg, PTR_REG); + + SMC_SELECT_BANK(1); + SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, + CTL_REG); + timeout = 100; + while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) + udelay(100); + if (timeout == 0) { + printf("Timeout Reading EEPROM register %02x\n", reg); + return 0; + } + + return SMC_inw (GP_REG); +} + +static int write_eeprom_reg(u16 value, u16 reg) +{ + int timeout; + + SMC_SELECT_BANK(2); + SMC_outw(reg, PTR_REG); + + SMC_SELECT_BANK(1); + SMC_outw(value, GP_REG); + SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); + timeout = 100; + while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout) + udelay (100); + if (timeout == 0) { + printf("Timeout Writing EEPROM register %02x\n", reg); + return 0; + } + + return 1; +} + +static int write_data(u16 *buf, int len) +{ + u16 reg = 0x23; + + while (len--) + write_eeprom_reg(*buf++, reg++); + + return 0; +} + +static int verify_macaddr(char *s) +{ + u16 reg; + int i, err = 0; + + printf("MAC Address: "); + err = i = 0; + for (i = 0; i < 3; i++) { + reg = read_eeprom_reg(0x20 + i); + printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); + if (s) + err |= reg != ((u16 *)s)[i]; + } + + return err ? 0 : 1; +} + +static int set_mac(char *s) +{ + int i; + char *e, eaddr[6]; + + /* turn string into mac value */ + for (i = 0; i < 6; i++) { + eaddr[i] = simple_strtoul(s, &e, 16); + s = (*e) ? e+1 : e; + } + + for (i = 0; i < 3; i++) + write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); + + return 0; +} + +static int parse_element(char *s, unsigned char *buf, int len) +{ + int cnt; + char *p, num[3]; + unsigned char id; + + id = simple_strtoul(s, &p, 16); + if (*p++ != ':') + return -1; + cnt = 2; + num[2] = 0; + for (; *p; p += 2) { + if (p[1] == 0) + return -2; + if (cnt + 3 > len) + return -3; + num[0] = p[0]; + num[1] = p[1]; + buf[cnt++] = simple_strtoul(num, NULL, 16); + } + buf[0] = id; + buf[1] = cnt - 2; + + return cnt; +} + +int eeprom(int argc, char *argv[]) +{ + int i, len, ret; + unsigned char buf[58], *p; + + app_startup(argv); + if (get_version() != XF_VERSION) { + printf("Wrong XF_VERSION.\n"); + printf("Application expects ABI version %d\n", XF_VERSION); + printf("Actual U-Boot ABI version %d\n", (int)get_version()); + return 1; + } + + if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + printf("SMSC91111 not found.\n"); + return 2; + } + + /* Called without parameters - print MAC address */ + if (argc < 2) { + verify_macaddr(NULL); + return 0; + } + + /* Print help message */ + if (argv[1][1] == 'h') { + printf("VoiceBlue EEPROM writer\n"); + printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf("Usage:\n\t [] [<...>]\n"); + return 0; + } + + /* Try to parse information elements */ + len = sizeof(buf); + p = buf; + for (i = 2; i < argc; i++) { + ret = parse_element(argv[i], p, len); + switch (ret) { + case -1: + printf("Element %d: malformed\n", i - 1); + return 3; + case -2: + printf("Element %d: odd character count\n", i - 1); + return 3; + case -3: + printf("Out of EEPROM memory\n"); + return 3; + default: + p += ret; + len -= ret; + } + } + + /* First argument (MAC) is mandatory */ + set_mac(argv[1]); + if (verify_macaddr(argv[1])) { + printf("*** MAC address does not match! ***\n"); + return 4; + } + + while (len--) + *p++ = 0; + + write_data((u16 *)buf, sizeof(buf) >> 1); + + return 0; +} diff --git a/board/voiceblue/eeprom.lds b/board/voiceblue/eeprom.lds new file mode 100644 index 0000000..317550d --- /dev/null +++ b/board/voiceblue/eeprom.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : + { + eeprom_start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/voiceblue/eeprom_start.S b/board/voiceblue/eeprom_start.S new file mode 100644 index 0000000..8f88de5 --- /dev/null +++ b/board/voiceblue/eeprom_start.S @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2005 2N Telekomunikace + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +.globl _start +_start: b eeprom diff --git a/board/voiceblue/setup.S b/board/voiceblue/setup.S new file mode 100644 index 0000000..dcf37b5 --- /dev/null +++ b/board/voiceblue/setup.S @@ -0,0 +1,280 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004 Ales Jindra + * (C) Copyright 2005 Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* SDRAM load addr from config.mk */ + +OMAP5910_LPG1_BASE: .word 0xfffbd000 +OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 +OMAP5910_MPU_TC_BASE: .word 0xfffecc00 +OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 +OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 +OMAP5910_DPLL1_BASE: .word 0xfffecf00 +OMAP5910_GPIO_BASE: .word 0xfffce000 +OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 +OMAP5910_MPUI_BASE: .word 0xfffec900 + +_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL +_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK + +OMAP5910_MPUI_CTRL: .word 0x0000ff1b + +VAL_EMIFS_CS0_CONFIG: .word 0x00009090 +VAL_EMIFS_CS1_CONFIG: .word 0x00003031 +VAL_EMIFS_CS2_CONFIG: .word 0x00003031 +VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 +VAL_EMIFS_DYN_WAIT: .word 0x00000000 +/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ + /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ +VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) +VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 +VAL_EMIFF_MRS: .word 0x00000037 + +/* + * GPIO04 - D4 (Onboard LED) + * GPIO07 - LAN91C111 reset + */ +GPIO_DIRECTION: + .word 0x0000ff6f +/* + * Disable everything, but D4 LED (connected through invertor) + */ +GPIO_OUTPUT: + .word 0x00000010 + +MUX_CONFIG_BASE: + .word 0xfffe1000 + +MUX_CONFIG_VALUES: + .align 4 + .word 0x00000000 @ FUNC_MUX_CTRL_0 + .word 0x00000000 @ FUNC_MUX_CTRL_1 + .word 0x00000000 @ FUNC_MUX_CTRL_2 + .word 0x00000000 @ FUNC_MUX_CTRL_3 + .word 0x00000000 @ FUNC_MUX_CTRL_4 + .word 0x12082480 @ FUNC_MUX_CTRL_5 + .word 0x00000004 @ FUNC_MUX_CTRL_6 + .word 0x00000003 @ FUNC_MUX_CTRL_7 + .word 0x10001200 @ FUNC_MUX_CTRL_8 + .word 0x01201012 @ FUNC_MUX_CTRL_9 + .word 0x02081248 @ FUNC_MUX_CTRL_A + .word 0x00001248 @ FUNC_MUX_CTRL_B + .word 0x12240000 @ FUNC_MUX_CTRL_C + .word 0x00002000 @ FUNC_MUX_CTRL_D + .word 0x00000000 @ PULL_DWN_CTRL_0 + .word 0x0000085f @ PULL_DWN_CTRL_1 + .word 0x01001000 @ PULL_DWN_CTRL_2 + .word 0x00000000 @ PULL_DWN_CTRL_3 + .word 0x00000000 @ GATE_INH_CTRL_0 + .word 0x00000000 @ VOLTAGE_CTRL_0 + .word 0x00000000 @ TEST_DBG_CTRL_0 + .word 0x00000006 @ MOD_CONF_CTRL_0 + .word 0x0000eaef @ COMP_MODE_CTRL_0 + +MUX_CONFIG_OFFSETS: + .align 1 + .byte 0x00 @ FUNC_MUX_CTRL_0 + .byte 0x04 @ FUNC_MUX_CTRL_1 + .byte 0x08 @ FUNC_MUX_CTRL_2 + .byte 0x10 @ FUNC_MUX_CTRL_3 + .byte 0x14 @ FUNC_MUX_CTRL_4 + .byte 0x18 @ FUNC_MUX_CTRL_5 + .byte 0x1c @ FUNC_MUX_CTRL_6 + .byte 0x20 @ FUNC_MUX_CTRL_7 + .byte 0x24 @ FUNC_MUX_CTRL_8 + .byte 0x28 @ FUNC_MUX_CTRL_9 + .byte 0x2c @ FUNC_MUX_CTRL_A + .byte 0x30 @ FUNC_MUX_CTRL_B + .byte 0x34 @ FUNC_MUX_CTRL_C + .byte 0x38 @ FUNC_MUX_CTRL_D + .byte 0x40 @ PULL_DWN_CTRL_0 + .byte 0x44 @ PULL_DWN_CTRL_1 + .byte 0x48 @ PULL_DWN_CTRL_2 + .byte 0x4c @ PULL_DWN_CTRL_3 + .byte 0x50 @ GATE_INH_CTRL_0 + .byte 0x60 @ VOLTAGE_CTRL_0 + .byte 0x70 @ TEST_DBG_CTRL_0 + .byte 0x80 @ MOD_CONF_CTRL_0 + .byte 0x0c @ COMP_MODE_CTRL_0 + .byte 0xff + +.globl lowlevel_init +lowlevel_init: + /* Improve performance a bit... */ + mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register + mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register + mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register + orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 + mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register + mov r1, #0x00 + mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache + nop + nop + nop + nop + + /* Setup clocking mode */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit + ldrh r1, [r0, #0x18] @ get reset status + bic r1, r1, #(7 << 11) @ clear clock select + orr r1, r1, #(2 << 11) @ set synchronous scalable + mov r2, #0 @ set wait counter to 100 clock cycles + +icache_loop: + cmp r2, #0x01 + streqh r1, [r0, #0x18] + add r2, r2, #0x01 + cmp r2, #0x10 + bne icache_loop + nop + + /* Setup clock divisors */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + ldr r1, _OMAP5910_ARM_CKCTL + orr r1, r1, #0x2000 @ enable DSP clock + strh r1, [r0, #0x00] @ setup clock divisors + + /* Setup DPLL to generate requested freq */ + ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF + orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF + strh r1, [r0] @ write + +locking: + ldrh r1, [r0] @ get DPLL value + tst r1, #0x01 + beq locking @ while LOCK not set + + /* Enable clock */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + mov r1, #(1 << 10) @ disable idle mode do not check + @ nWAKEUP pin, other remain active + strh r1, [r0, #0x04] + ldr r1, _OMAP5910_ARM_EN_CLK + strh r1, [r0, #0x08] + mov r1, #0x003f @ FLASH.RP not enabled in idle and + @ max delayed ( 32 x CLKIN ) + strh r1, [r0, #0x0c] + + /* Configure 5910 pins functions to match our board. */ + ldr r0, MUX_CONFIG_BASE + adr r1, MUX_CONFIG_VALUES + adr r2, MUX_CONFIG_OFFSETS +next_mux_cfg: + ldrb r3, [r2], #1 + ldr r4, [r1], #4 + cmp r3, #0xff + strne r4, [r0, r3] + bne next_mux_cfg + + /* Configure GPIO pins (also enables onboard LED) */ + ldr r0, OMAP5910_GPIO_BASE + ldr r1, GPIO_OUTPUT + strh r1, [r0, #0x04] + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] + + /* EnablePeripherals */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit + mov r1, #0x0001 @ Peripheral enable + strh r1, [r0, #0x14] + + /* Program LED Pulse Generator */ + ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator + mov r1, #0x7F @ Set obscure frequency in + strb r1, [r0, #0x00] @ LCR + mov r1, #0x01 @ Enable clock (CLK_EN) in + strb r1, [r0, #0x04] @ PMR + + /* TIPB Lock UART1 */ + ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches + mov r1, #1 @ ARM allocated + strh r1, [r0,#0x04] @ clear IRQ line and status bits + strh r1, [r0,#0x00] + ldrh r1, [r0,#0x04] + + /* Disable watchdog */ + ldr r0, OMAP5910_MPU_WD_TIMER_BASE + mov r1, #0xf5 + strh r1, [r0, #0x8] + mov r1, #0xa0 + strh r1, [r0, #0x8] + + /* Enable MCLK */ + ldr r0, OMAP5910_ULPD_PWR_MNG_BASE + mov r1, #0x6 + strh r1, [r0, #0x34] + strh r1, [r0, #0x34] + + /* Setup clock divisors */ + ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register + + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + strh r1, [r0] @ write + +ulocking: + ldrh r1, [r0] @ get DPLL value + tst r1, #1 + beq ulocking @ while LOCK not set + + /* EMIF init */ + ldr r0, OMAP5910_MPU_TC_BASE + ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG + bic r1, r1, #0x0c @ pwr down disabled, flash WP + orr r1, r1, #0x01 + str r1, [r0, #0x0c] + + ldr r1, VAL_EMIFS_CS0_CONFIG + str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG + ldr r1, VAL_EMIFS_CS1_CONFIG + str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG + ldr r1, VAL_EMIFS_CS2_CONFIG + str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG + ldr r1, VAL_EMIFS_CS3_CONFIG + str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG + ldr r1, VAL_EMIFS_DYN_WAIT + str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT + + /* Setup SDRAM */ + ldr r1, VAL_EMIFF_SDRAM_CONFIG + str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG + ldr r1, VAL_EMIFF_SDRAM_CONFIG2 + str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2 + ldr r1, VAL_EMIFF_MRS + str r1, [r0, #0x24] @ EMIFF_MRS + /* SDRAM needs 100us to stabilize */ + mov r0, #0x4000 +sdelay: + subs r0, r0, #0x1 + bne sdelay + + /* back to arch calling code */ + mov pc, lr +.end diff --git a/board/voiceblue/u-boot.lds b/board/voiceblue/u-boot.lds new file mode 100644 index 0000000..f35a3ab --- /dev/null +++ b/board/voiceblue/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm925t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c new file mode 100644 index 0000000..7a2d243 --- /dev/null +++ b/board/voiceblue/voiceblue.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa; + + /* arch number of VoiceBlue board */ + /* TODO: use define from asm/mach-types.h */ + gd->bd->bi_arch_number = 218; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff; + + /* Take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. */ + *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; + udelay(10); /* doesn't work before interrupt_init call */ + *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; + udelay(500); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int misc_init_r(void) +{ + *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55; + + return 0; +} + +int board_late_init(void) +{ + *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00; + + return 0; +} diff --git a/board/w7o/Makefile b/board/w7o/Makefile new file mode 100644 index 0000000..d008f89 --- /dev/null +++ b/board/w7o/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \ + watchdog.o +SOBJS = init.o post1.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c new file mode 100644 index 0000000..449089e --- /dev/null +++ b/board/w7o/cmd_vpd.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +#include "vpd.h" + +/* ====================================================================== + * Interpreter command to retrieve board specific Vital Product Data, "VPD" + * ====================================================================== + */ +int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + VPD vpd; /* Board specific data struct */ + uchar dev_addr = CFG_DEF_EEPROM_ADDR; + + /* Validate usage */ + if (argc > 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Passed in EEPROM address */ + if (argc == 2) + dev_addr = (uchar) simple_strtoul (argv[1], NULL, 16); + + /* Read VPD and output it */ + if (!vpd_get_data (dev_addr, &vpd)) { + vpd_print (&vpd); + return 0; + } + + return 1; +} + +U_BOOT_CMD( + vpd, 2, 1, do_vpd, + "vpd - Read Vital Product Data\n", + "[dev_addr]\n" + " - Read VPD Data from default address, or device address 'dev_addr'.\n" +); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_BSP) */ diff --git a/board/w7o/config.mk b/board/w7o/config.mk new file mode 100644 index 0000000..bc341ca --- /dev/null +++ b/board/w7o/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2001 +# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Wave 7 Optics boards +# + +#TEXT_BASE = 0xFFF80000 +TEXT_BASE = 0xFFFC0000 + +#PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARD) diff --git a/board/w7o/errors.h b/board/w7o/errors.h new file mode 100644 index 0000000..05b4eae --- /dev/null +++ b/board/w7o/errors.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ERRORS_H_ +#define _ERRORS_H_ + +#define ERR_FF -1 /* led test value(2) */ +#define ERR_00 0x0000 /* led test value(2) */ +#define ERR_LED 0x01 /* led test failed (1)(3)(4) */ +#define ERR_RAMG 0x04 /* start SDRAM data bus test (2) */ +#define ERR_RAML 0x05 /* SDRAM data bus fault in LSW chip (5) */ +#define ERR_RAMH 0x06 /* SDRAM data bus fault in MSW chip (6) */ +#define ERR_RAMB 0x07 /* SDRAM data bus fault both chips (5)(6)(7) */ +#define ERR_ADDG 0x08 /* start Address ghosting test (13) */ +#define ERR_ADDF 0x09 /* fault during Address ghosting test (13) */ +#define ERR_POST1 0x0a /* post1 tests complete */ +#define ERR_TMP1 0x0b /* */ +#define ERR_R55G 0x0c /* start SDRAM fill 55 test (2) */ +#define ERR_R55L 0x0d /* SDRAM fill test 55 failed in LSW chip (8) */ +#define ERR_R55H 0x0e /* SDRAM fill test 55 failed in MSW chip (9) */ +#define ERR_R55B 0x0f /* SDRAM fill test 55 fail in both chips (10) */ +#define ERR_RAAG 0x10 /* start SDRAM fill aa test (2) */ +#define ERR_RAAL 0x11 /* SDRAM fill test aa failed in LSW chip (8) */ +#define ERR_RAAH 0x12 /* SDRAM fill test aa failed in MSW chip (9) */ +#define ERR_RAAB 0x13 /* SDRAM fill test aa fail in both chips (10) */ +#define ERR_R00G 0x14 /* start SDRAM fill 00 test (2) */ +#define ERR_R00L 0x15 /* SDRAM fill test 00 failed in LSW chip (8) */ +#define ERR_R00H 0x16 /* SDRAM fill test 00 failed in MSW chip (9) */ +#define ERR_R00B 0x17 /* SDRAM fill test 00 fail in both chips (10) */ +#define ERR_RTCG 0x18 /* start RTC test */ +#define ERR_RTCBAT 0x19 /* RTC battery failure */ +#define ERR_RTCTIM 0x1A /* RTC invalid time/date values */ +#define ERR_RTCVAL 0x1B /* RTC NVRAM not accessable */ +#define ERR_FPGAG 0x20 /* fault during FPGA programming */ +#define ERR_XRW1 0x21 /* Xilinx - can't read/write regs on FPGA 1 */ +#define ERR_XRW2 0x22 /* Xilinx - can't read/write regs on FPGA 2 */ +#define ERR_XRW3 0x23 /* Xilinx - can't read/write regs on FPGA 3 */ +#define ERR_XRW4 0x24 /* Xilinx - can't read/write regs on FPGA 4 */ +#define ERR_XRW5 0x25 /* Xilinx - can't read/write regs on FPGA 5 */ +#define ERR_XRW6 0x26 /* Xilinx - can't read/write regs on FPGA 6 */ +#define ERR_XINIT0 0x27 /* Xilinx - INIT line failed to go low */ +#define ERR_XINIT1 0x28 /* Xilinx - INIT line failed to go high */ +#define ERR_XDONE1 0x29 /* Xilinx - DONE line failed to go high */ +#define ERR_XIMAGE 0x2A /* Xilinx - Bad FPGA image in Flash */ +#define ERR_TempG 0x2b /* start temp sensor tests */ +#define ERR_Tinit0 0x2C /* temp sensor 0 failed to init */ +#define ERR_Tinit1 0x2D /* temp sensor 1 failed to init */ +#define ERR_Ttest0 0x2E /* temp sensor 0 failed test */ +#define ERR_Ttest1 0x2F /* temp sensor 1 failed test */ +#define ERR_lm75r 0x30 /* temp sensor read failure */ +#define ERR_lm75w 0x31 /* temp sensor write failure */ + + +#define ERR_POSTOK 0x55 /* PANIC: psych... OK */ + +#if !defined(__ASSEMBLY__) +extern void log_stat(int errcode); +extern void log_warn(int errcode); +extern void log_err(int errcode); +#endif + +/* +Debugging suggestions: +(1) periferal data bus shorted or crossed +(2) general processor halt, check reset, watch dog, power supply ripple, processor clock. +(3) check p_we, p_r/w, p_oe, p_rdy lines. +(4) check LED buffers +(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip. +(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip. +(7) check SDRAM control lines and clocks +(8) check decoupling caps, replace LSW SDRAM +(9) check decoupling caps, replace MSW SDRAM +(10) +(11) +(12) +(13) SDRAM address shorted or unconnected, check sdram caps +*/ +#endif /* _ERRORS_H_ */ diff --git a/board/w7o/flash.c b/board/w7o/flash.c new file mode 100644 index 0000000..32815fb --- /dev/null +++ b/board/w7o/flash.c @@ -0,0 +1,940 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * Based on code by: + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word8(flash_info_t *info, ulong dest, ulong data); +static int write_word32 (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + unsigned long size_b0, base_b0; + unsigned long size_b1, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Get Size of Boot and Main Flashes */ + size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0<<20); + return 0; + } + size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); + if (flash_info[1].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", + size_b1, size_b1<<20); + return 0; + } + + /* Calculate base addresses */ + base_b0 = -size_b0; + base_b1 = -size_b1; + + /* Setup offsets for Boot Flash */ + flash_get_offsets (base_b0, &flash_info[0]); + + /* Protect board level data */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b0, + flash_info[0].start[1] - 1, + &flash_info[0]); + + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, + &flash_info[0]); + + /* Protect the FPGA image */ + (void)flash_protect(FLAG_PROTECT_SET, + FLASH_BASE1_PRELIM, + FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN - 1, + &flash_info[1]); + + /* Protect the default boot image */ + (void)flash_protect(FLAG_PROTECT_SET, + FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN, + FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN + 0x600000 - 1, + &flash_info[1]); + + /* Setup offsets for Main Flash */ + flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[1]); + + return (size_b0 + size_b1); +} /* end flash_init() */ + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table - FOR BOOT ROM ONLY!!! */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } +} /* end flash_get_offsets() */ + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("1 x AMD "); break; + case FLASH_MAN_STM: printf ("1 x STM "); break; + case FLASH_MAN_INTEL: printf ("2 x Intel "); break; + default: printf ("Unknown Vendor "); + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + printf ("AM29LV040 (4096 Kbit, uniform sector size)\n"); + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) + printf ("M29W040B (4096 Kbit, uniform block size)\n"); + else + printf ("UNKNOWN 29x040x (4096 Kbit, uniform sector size)\n"); + break; + case FLASH_28F320J3A: + printf ("28F320J3A (32 Mbit = 128K x 32)\n"); + break; + case FLASH_28F640J3A: + printf ("28F640J3A (64 Mbit = 128K x 64)\n"); + break; + case FLASH_28F128J3A: + printf ("28F128J3A (128 Mbit = 128K x 128)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) { + printf (" Size: %ld KB in %d Blocks\n", + info->size >> 10, info->sector_count); + } else { + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + } + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); +} /* end flash_print_info() */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong base = (ulong)addr; + + /* Setup default type */ + info->flash_id = FLASH_UNKNOWN; + info->sector_count =0; + info->size = 0; + + /* Test for Boot Flash */ + if (base == FLASH_BASE0_PRELIM) { + unsigned char value; + volatile unsigned char * addr2 = (unsigned char *)addr; + + /* Write auto select command: read Manufacturer ID */ + *(addr2 + 0x555) = 0xaa; + *(addr2 + 0x2aa) = 0x55; + *(addr2 + 0x555) = 0x90; + + /* Manufacture ID */ + value = *addr2; + switch (value) { + case (unsigned char)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (unsigned char)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + *addr2 = 0xf0; /* no or unknown flash */ + return 0; + } + + /* Device ID */ + value = *(addr2 + 1); + switch (value) { + case (unsigned char)AMD_ID_LV040B: + case (unsigned char)STM_ID_29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512Kb */ + default: + *addr2 = 0xf0; /* => no or unknown flash */ + return 0; + } + } + else { /* MAIN Flash */ + unsigned long value; + volatile unsigned long * addr2 = (unsigned long *)addr; + + /* Write auto select command: read Manufacturer ID */ + *addr2 = 0x90909090; + + /* Manufacture ID */ + value = *addr2; + switch (value) { + case (unsigned long)INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + *addr2 = 0xff; /* no or unknown flash */ + return 0; + } + + /* Device ID - This shit is interleaved... */ + value = *(addr2 + 1); + switch (value) { + case (unsigned long)INTEL_ID_28F320J3A: + info->flash_id += FLASH_28F320J3A; + info->sector_count = 32; + info->size = 0x00400000 * 2; + break; /* => 2 X 4 MB */ + case (unsigned long)INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x00800000 * 2; + break; /* => 2 X 8 MB */ + case (unsigned long)INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x01000000 * 2; + break; /* => 2 X 16 MB */ + default: + *addr2 = 0xff; /* => no or unknown flash */ + } + } + + /* Make sure we don't exceed CFG_MAX_FLASH_SECT */ + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + /* set up sector start address table */ + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + break; + case FLASH_28F320J3A: + case FLASH_28F640J3A: + case FLASH_28F128J3A: + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00020000 * 2); /* 2 Banks */ + break; + } + + /* Test for Boot Flash */ + if (base == FLASH_BASE0_PRELIM) { + volatile unsigned char *addr2; + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (AX .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile unsigned char *)(info->start[i]); + info->protect[i] = *(addr2 + 2) & 1; + } + + /* Restore read mode */ + *(unsigned char *)base = 0xF0; /* Reset NORMAL Flash */ + } + else { /* Main Flash */ + volatile unsigned long *addr2; + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (AX .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile unsigned long *)(info->start[i]); + info->protect[i] = *(addr2 + 2) & 0x1; + } + + /* Restore read mode */ + *(unsigned long *)base = 0xFFFFFFFF; /* Reset Flash */ + } + + return (info->size); +} /* end flash_get_size() */ + +/*----------------------------------------------------------------------- + */ + +static int wait_for_DQ7(ulong addr, uchar cmp_val, ulong tout) +{ + int i; + + volatile uchar *vaddr = (uchar *)addr; + + /* Loop X times */ + for (i = 1; i <= (100 * tout); i++) { /* Wait up to tout ms */ + udelay(10); + /* Pause 10 us */ + + /* Check for completion */ + if ((vaddr[0] & 0x80) == (cmp_val & 0x80)) { + return 0; + } + + /* KEEP THE LUSER HAPPY - Print a dot every 1.1 seconds */ + if (!(i % 110000)) + putc('.'); + + /* Kick the dog if needed */ + WATCHDOG_RESET(); + } + + return 1; +} /* wait_for_DQ7() */ + +/*----------------------------------------------------------------------- + */ + +static int flash_erase8(flash_info_t *info, int s_first, int s_last) +{ + int tcode, rcode = 0; + volatile uchar *addr = (uchar *)(info->start[0]); + volatile uchar *sector_addr; + int flag, prot, sect; + + /* Validate arguments */ + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf ("- missing\n"); + else + printf ("- no sectors to erase\n"); + return 1; + } + + /* Check for KNOWN flash type */ + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + /* Check for protected sectors */ + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + sector_addr = (uchar *)(info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) + printf("Erasing block %p\n", sector_addr); + else + printf("Erasing sector %p\n", sector_addr); + + /* Disable interrupts which might cause Flash to timeout */ + flag = disable_interrupts(); + + *(addr + 0x555) = (uchar)0xAA; + *(addr + 0x2aa) = (uchar)0x55; + *(addr + 0x555) = (uchar)0x80; + *(addr + 0x555) = (uchar)0xAA; + *(addr + 0x2aa) = (uchar)0x55; + *sector_addr = (uchar)0x30; /* sector erase */ + + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + * Takes up to 6 seconds. + */ + tcode = wait_for_DQ7((ulong)sector_addr, 0x80, 6000); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* Make sure we didn't timeout */ + if (tcode) { + printf ("Timeout\n"); + rcode = 1; + } + } + } + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* reset to read mode */ + addr = (uchar *)info->start[0]; + *addr = (uchar)0xF0; /* reset bank */ + + printf (" done\n"); + return rcode; +} /* end flash_erase8() */ + +static int flash_erase32(flash_info_t *info, int s_first, int s_last) +{ + int flag, sect; + ulong start, now, last; + int prot = 0; + + /* Validate arguments */ + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf ("- missing\n"); + else + printf ("- no sectors to erase\n"); + return 1; + } + + /* Check for KNOWN flash type */ + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + /* Check for protected sectors */ + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + WATCHDOG_RESET(); + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + unsigned long status; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = 0x00500050; /* clear status register */ + *addr = 0x00200020; /* erase setup */ + *addr = 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* Wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((status = *addr) & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0x00B000B0; /* suspend erase */ + *addr = 0x00FF00FF; /* reset to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 990) { /* every second */ + putc ('.'); + last = now; + } + } + *addr = 0x00FF00FF; /* reset to read mode */ + } + } + printf (" done\n"); + return 0; +} /* end flash_erase32() */ + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) + return flash_erase8(info, s_first, s_last); + else + return flash_erase32(info, s_first, s_last); +} /* end flash_erase() */ + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_buff8(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + ulong start; + int i, l, rc; + + start = get_timer (0); + + wp = (addr & ~3); /* get lower word + aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word8(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word8(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + if (get_timer(start) > 1000) { /* every second */ + WATCHDOG_RESET(); + putc ('.'); + start = get_timer(0); + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word8(info, wp, data)); +} /* end write_buff8() */ + +#define FLASH_WIDTH 4 /* flash bus width in bytes */ +static int write_buff32 (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + ulong start; + + start = get_timer (0); + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i= FLASH_WIDTH) { + data = 0; + for (i=0; i 990) { /* every second */ + putc ('.'); + start = get_timer(0); + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; iflash_id & FLASH_TYPEMASK) == FLASH_AM040) + retval = write_buff8(info, src, addr, cnt); + else + retval = write_buff32(info, src, addr, cnt); + + return retval; +} /* end write_buff() */ + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +static int write_word8(flash_info_t *info, ulong dest, ulong data) +{ + volatile uchar *addr2 = (uchar *)(info->start[0]); + volatile uchar *dest2 = (uchar *)dest; + volatile uchar *data2 = (uchar *)&data; + int flag; + int i, tcode, rcode = 0; + + /* Check if Flash is (sufficently) erased */ + if ((*((volatile uchar *)dest) & + (uchar)data) != (uchar)data) { + return (2); + } + + for (i=0; i < (4 / sizeof(uchar)); i++) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *(addr2 + 0x555) = (uchar)0xAA; + *(addr2 + 0x2aa) = (uchar)0x55; + *(addr2 + 0x555) = (uchar)0xA0; + + dest2[i] = data2[i]; + + /* Wait for write to complete, up to 1ms */ + tcode = wait_for_DQ7((ulong)&dest2[i], data2[i], 1); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* Make sure we didn't timeout */ + if (tcode) { + rcode = 1; + } + } + + return rcode; +} /* end write_word8() */ + +static int write_word32(flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong status; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *addr = 0x00400040; /* write setup */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (((status = *addr) & 0x00800080) != 0x00800080) { + WATCHDOG_RESET(); + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = 0x00FF00FF; /* restore read mode */ + + return (0); +} /* end write_word32() */ + + +static int _flash_protect(flash_info_t *info, long sector) +{ + int i; + int flag; + ulong status; + int rcode = 0; + volatile long *addr = (long *)sector; + + switch(info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: + case FLASH_28F640J3A: + case FLASH_28F128J3A: + /* Disable interrupts which might cause Flash to timeout */ + flag = disable_interrupts(); + + /* Issue command */ + *addr = 0x00500050L; /* Clear the status register */ + *addr = 0x00600060L; /* Set lock bit setup */ + *addr = 0x00010001L; /* Set lock bit confirm */ + + /* Wait for command completion */ + for (i = 0; i < 10; i++) { /* 75us timeout, wait 100us */ + udelay(10); + if ((*addr & 0x00800080L) == 0x00800080L) + break; + } + + /* Not successful? */ + status = *addr; + if (status != 0x00800080L) { + printf("Protect %x sector failed: %x\n", + (uint)sector, (uint)status); + rcode = 1; + } + + /* Restore read mode */ + *addr = 0x00ff00ffL; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + break; + case FLASH_AM040: /* No soft sector protection */ + break; + } + + /* Turn protection on for this sector */ + for (i = 0; i < info->sector_count; i++) { + if (info->start[i] == sector) { + info->protect[i] = 1; + break; + } + } + + return rcode; +} /* end _flash_protect() */ + +static int _flash_unprotect(flash_info_t *info, long sector) +{ + int i; + int flag; + ulong status; + int rcode = 0; + volatile long *addr = (long *)sector; + + switch(info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F320J3A: + case FLASH_28F640J3A: + case FLASH_28F128J3A: + /* Disable interrupts which might cause Flash to timeout */ + flag = disable_interrupts(); + + *addr = 0x00500050L; /* Clear the status register */ + *addr = 0x00600060L; /* Clear lock bit setup */ + *addr = 0x00D000D0L; /* Clear lock bit confirm */ + + /* Wait for command completion */ + for (i = 0; i < 80 ; i++) { /* 700ms timeout, wait 800 */ + udelay(10000); /* Delay 10ms */ + if ((*addr & 0x00800080L) == 0x00800080L) + break; + } + + /* Not successful? */ + status = *addr; + if (status != 0x00800080L) { + printf("Un-protect %x sector failed: %x\n", + (uint)sector, (uint)status); + *addr = 0x00ff00ffL; + rcode = 1; + } + + /* restore read mode */ + *addr = 0x00ff00ffL; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + break; + case FLASH_AM040: /* No soft sector protection */ + break; + } + + /* + * Fix Intel's little red wagon. Reprotect + * sectors that were protected before we undid + * protection on a specific sector. + */ + for (i = 0; i < info->sector_count; i++) { + if (info->start[i] != sector) { + if (info->protect[i]) { + if (_flash_protect(info, info->start[i])) + rcode = 1; + } + } + else /* Turn protection off for this sector */ + info->protect[i] = 0; + } + + return rcode; +} /* end _flash_unprotect() */ + + +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int rcode; + + if (prot) + rcode = _flash_protect(info, info->start[sector]); + else + rcode = _flash_unprotect(info, info->start[sector]); + + return rcode; +} /* end flash_real_protect() */ + +/*----------------------------------------------------------------------- + */ diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c new file mode 100644 index 0000000..100bce4 --- /dev/null +++ b/board/w7o/fpga.c @@ -0,0 +1,379 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * and + * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include "w7o.h" +#include +#include "errors.h" + +static void +fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr) +{ + unsigned long i; + volatile unsigned long val; + volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */ + + for (i = 0; i < len; i++, src++) { + val = *src; + *dest = (unsigned short)((val & 0xff000000L) >> 16); + *dest = (unsigned short)((val & 0x00ff0000L) >> 8); + *dest = (unsigned short)(val & 0x0000ff00L); + *dest = (unsigned short)((val & 0x000000ffL) << 8); + } + + /* Terminate programming with 4 C clocks */ + dest = daddr; + val = *(unsigned short *)dest; + val = *(unsigned short *)dest; + val = *(unsigned short *)dest; + val = *(unsigned short *)dest; + +} + + +int +fpgaDownload(unsigned char *saddr, + unsigned long size, + unsigned short *daddr) +{ + int i; /* index, intr disable flag */ + int start; /* timer */ + unsigned long greg, grego; /* GPIO & output register */ + unsigned long length; /* image size in words */ + unsigned long *source; /* image source addr */ + unsigned short *dest; /* destination FPGA addr */ + volatile unsigned short *ndest; /* temp dest FPGA addr */ + volatile unsigned short val; /* temp val */ + unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */ + unsigned long eirq = GPIO_XCV_IRQ; + int retval = -1; /* Function return value */ + + /* Setup some basic values */ + length = (size / 4) + 1; /* size in words, rounding UP + is OK */ + source = (unsigned long *)saddr; + dest = (unsigned short *)daddr; + + /* Get DCR output register */ + grego = in32(PPC405GP_GPIO0_OR); + + /* Reset FPGA */ + grego &= ~GPIO_XCV_PROG; /* PROG line low */ + out32(PPC405GP_GPIO0_OR, grego); + + /* Setup timeout timer */ + start = get_timer(0); + + /* Wait for FPGA init line */ + while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */ + /* Check for timeout - 100us max, so use 3ms */ + if (get_timer(start) > 3) { + printf(" failed to start init.\n"); + log_warn(ERR_XINIT0); /* Don't halt */ + + /* Reset line stays low */ + goto done; /* I like gotos... */ + } + } + + /* Unreset FPGA */ + grego |= GPIO_XCV_PROG; /* PROG line high */ + out32(PPC405GP_GPIO0_OR, grego); + + /* Wait for FPGA end of init period . */ + while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */ + + /* Check for timeout */ + if (get_timer(start) > 3) { + printf(" failed to exit init.\n"); + log_warn(ERR_XINIT1); + + /* Reset FPGA */ + grego &= ~GPIO_XCV_PROG; /* PROG line low */ + out32(PPC405GP_GPIO0_OR, grego); + + goto done; + } + } + + /* Now program FPGA ... */ + ndest = dest; + for (i = 0; i < CONFIG_NUM_FPGAS; i++) { + /* Toggle IRQ/GPIO */ + greg = mfdcr(CPC0_CR0); /* get chip ctrl register */ + greg |= eirq; /* toggle irq/gpio */ + mtdcr(CPC0_CR0, greg); /* ... just do it */ + + /* turn on open drain for CNFG */ + greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */ + greg |= cnfg; /* CNFG open drain */ + out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */ + + /* Turn output enable on for CNFG */ + greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */ + greg |= cnfg; /* CNFG tristate inactive */ + out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */ + + /* Setup FPGA for programming */ + grego &= ~cnfg; /* CONFIG line low */ + out32(PPC405GP_GPIO0_OR, grego); + + /* + * Program the FPGA + */ + printf("\n destination: 0x%lx ", (unsigned long)ndest); + + fpga_img_write(source, length, (unsigned short *)ndest); + + /* Done programming */ + grego |= cnfg; /* CONFIG line high */ + out32(PPC405GP_GPIO0_OR, grego); + + /* Turn output enable OFF for CNFG */ + greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */ + greg &= ~cnfg; /* CNFG tristate inactive */ + out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */ + + /* Toggle IRQ/GPIO */ + greg = mfdcr(CPC0_CR0); /* get chip ctrl register */ + greg &= ~eirq; /* toggle irq/gpio */ + mtdcr(CPC0_CR0, greg); /* ... just do it */ + + ndest = (unsigned short *)((char *)ndest + 0x00100000L); /* XXX - Next FPGA addr */ + cnfg >>= 1; /* XXX - Next */ + eirq >>= 1; + } + + /* Terminate programming with 4 C clocks */ + ndest = dest; + for (i = 0; i < CONFIG_NUM_FPGAS; i++) { + val = *ndest; + val = *ndest; + val = *ndest; + val = *ndest; + ndest = (unsigned short *)((char *)ndest + 0x00100000L); + } + + /* Setup timer */ + start = get_timer(0); + + /* Wait for FPGA end of programming period . */ + while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */ + + /* Check for timeout */ + if (get_timer(start) > 3) { + printf(" done failed to come high.\n"); + log_warn(ERR_XDONE1); + + /* Reset FPGA */ + grego &= ~GPIO_XCV_PROG; /* PROG line low */ + out32(PPC405GP_GPIO0_OR, grego); + + goto done; + } + } + + printf("\n FPGA load succeeded\n"); + retval = 0; /* Program OK */ + +done: + return retval; +} + +/* FPGA image is stored in flash */ +extern flash_info_t flash_info[]; + +int init_fpga(void) +{ + unsigned int i,j,ptr; /* General purpose */ + unsigned char bufchar; /* General purpose character */ + unsigned char *buf; /* Start of image pointer */ + unsigned long len; /* Length of image */ + unsigned char *fn_buf; /* Start of filename string */ + unsigned int fn_len; /* Length of filename string */ + unsigned char *xcv_buf; /* Pointer to start of image */ + unsigned long xcv_len; /* Length of image */ + unsigned long crc; /* 30bit crc in image */ + unsigned long calc_crc; /* Calc'd 30bit crc */ + int retval = -1; + + /* Tell the world what we are doing */ + printf("FPGA: "); + + /* + * Get address of first sector where the FPGA + * image is stored. + */ + buf = (unsigned char *)flash_info[1].start[0]; + + /* + * Get the stored image's CRC & length. + */ + crc = *(unsigned long *)(buf+4); /* CRC is first long word */ + len = *(unsigned long *)(buf+8); /* Image len is next long */ + + /* Pedantic */ + if ((len < 0x133A4) || (len > 0x80000)) + goto bad_image; + + /* + * Get the file name pointer and length. + */ + fn_len = (*(unsigned short *)(buf+12) & 0xff); /* filename length + is next short */ + fn_buf = buf + 14; + + /* + * Get the FPGA image pointer and length length. + */ + xcv_buf = fn_buf + fn_len; /* pointer to fpga image */ + xcv_len = len - 14 - fn_len; /* fpga image length */ + + /* Check for uninitialized FLASH */ + if ((strncmp((char *)buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0)) + goto bad_image; + + /* + * Calculate and Check the image's CRC. + */ + calc_crc = crc32(0, xcv_buf, xcv_len); + if (crc != calc_crc) { + printf("\nfailed - bad CRC\n"); + goto done; + } + + /* Output the file name */ + printf("file name : "); + for (i=0;i'~') bufchar = '.'; + putc(bufchar); + } + + /* + * find rest of display data + */ + ptr = 15; /* Offset to ncd filename + length in fpga image */ + j = xcv_buf[ptr]; /* Get len of ncd filename */ + if (j > 32) goto bad_image; + ptr = ptr + j + 3; /* skip ncd filename string + + 3 bytes more bytes */ + + /* + * output target device string + */ + j = xcv_buf[ptr++] - 1; /* len of targ str less term */ + if (j > 32) goto bad_image; + printf("\n target : "); + for (i = 0; i < j; i++) { + bufchar = (xcv_buf[ptr++]); + if (bufchar<' ' || bufchar>'~') bufchar = '.'; + putc(bufchar); + } + + /* + * output compilation date string and time string + */ + ptr += 3; /* skip 2 bytes */ + printf("\n synth time : "); + j = (xcv_buf[ptr++] - 1); /* len of date str less term */ + if (j > 32) goto bad_image; + for (i = 0; i < j; i++) { + bufchar = (xcv_buf[ptr++]); + if (bufchar<' ' || bufchar>'~') bufchar = '.'; + putc(bufchar); + } + + ptr += 3; /* Skip 2 bytes */ + printf(" - "); + j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */ + if (j > 32) goto bad_image; + for (i = 0; i < j; i++) { + bufchar = (xcv_buf[ptr++]); + if (bufchar<' ' || bufchar>'~') bufchar = '.'; + putc(bufchar); + } + + /* + * output crc and length strings + */ + printf("\n len & crc : 0x%lx 0x%lx", len, crc); + + /* + * Program the FPGA. + */ + retval = fpgaDownload((unsigned char*)xcv_buf, xcv_len, + (unsigned short *)0xfd000000L); + return retval; + +bad_image: + printf("\n BAD FPGA image format @ %lx\n", flash_info[1].start[0]); + log_warn(ERR_XIMAGE); +done: + return retval; +} + +void test_fpga(unsigned short *daddr) +{ + int i; + volatile unsigned short *ndest = daddr; + + for (i = 0; i < CONFIG_NUM_FPGAS; i++) { +#if defined(CONFIG_W7OLMG) + ndest[0x7e] = 0x55aa; + if (ndest[0x7e] != 0x55aa) + log_warn(ERR_XRW1 + i); + ndest[0x7e] = 0xaa55; + if (ndest[0x7e] != 0xaa55) + log_warn(ERR_XRW1 + i); + ndest[0x7e] = 0xc318; + if (ndest[0x7e] != 0xc318) + log_warn(ERR_XRW1 + i); + +#elif defined(CONFIG_W7OLMC) + ndest[0x800] = 0x55aa; + ndest[0x801] = 0xaa55; + ndest[0x802] = 0xc318; + ndest[0x4800] = 0x55aa; + ndest[0x4801] = 0xaa55; + ndest[0x4802] = 0xc318; + if ((ndest[0x800] != 0x55aa) || + (ndest[0x801] != 0xaa55) || + (ndest[0x802] != 0xc318)) + log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */ + if ((ndest[0x4800] != 0x55aa) || + (ndest[0x4801] != 0xaa55) || + (ndest[0x4802] != 0xc318)) + log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */ + +#else +# error "Unknown W7O board configuration" +#endif + } + + printf(" FPGA ready\n"); + return; +} diff --git a/board/w7o/fsboot.c b/board/w7o/fsboot.c new file mode 100644 index 0000000..0ef9a61 --- /dev/null +++ b/board/w7o/fsboot.c @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2001 + * Wave 7 Optics, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * FIXME: Add code to test image and it's header. + */ +extern int valid_elf_image (unsigned long addr); + +static int +image_check(ulong addr) +{ + return valid_elf_image(addr); +} + +void +init_fsboot(void) +{ + char *envp; + ulong loadaddr; + ulong testaddr; + ulong alt_loadaddr; + char buf[9]; + + /* + * Get test image address + */ + if ((envp = getenv("testaddr")) != NULL) + testaddr = simple_strtoul(envp, NULL, 16); + else + testaddr = -1; + + /* + * Are we going to test boot and image? + */ + if ((testaddr != -1) && image_check(testaddr)) { + + /* Set alt_loadaddr */ + alt_loadaddr = testaddr; + sprintf(buf, "%lX", alt_loadaddr); + setenv("alt_loadaddr", buf); + + /* Clear test_addr */ + setenv("testaddr", NULL); + + /* + * Save current environment with alt_loadaddr, + * and cleared testaddr. + */ + saveenv(); + + /* + * Setup temporary loadaddr to alt_loadaddr + * XXX - DO NOT SAVE ENVIRONMENT! + */ + loadaddr = alt_loadaddr; + sprintf(buf, "%lX", loadaddr); + setenv("loadaddr", buf); + + } else { /* Normal boot */ + setenv("alt_loadaddr", NULL); /* Clear alt_loadaddr */ + setenv("testaddr", NULL); /* Clear testaddr */ + saveenv(); + } + + return; +} diff --git a/board/w7o/init.S b/board/w7o/init.S new file mode 100644 index 0000000..35d7dbc --- /dev/null +++ b/board/w7o/init.S @@ -0,0 +1,264 @@ +/****************************************************************************** + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + * + *****************************************************************************/ +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +/****************************************************************************** + * Function: ext_bus_cntlr_init + * + * Description: Configures EBC Controller and a few basic chip selects. + * + * CS0 is setup to get the Boot Flash out of the addresss range + * so that we may setup a stack. CS7 is setup so that we can + * access and reset the hardware watchdog. + * + * IMPORTANT: For pass1 this code must run from + * cache since you can not reliably change a peripheral banks + * timing register (pbxap) while running code from that bank. + * For ex., since we are running from ROM on bank 0, we can NOT + * execute the code that modifies bank 0 timings from ROM, so + * we run it from cache. + * + * Notes: Does NOT use the stack. + *****************************************************************************/ + .section ".text" + .align 2 + .globl ext_bus_cntlr_init + .type ext_bus_cntlr_init, @function +ext_bus_cntlr_init: + mflr r0 + /******************************************************************** + * Prefetch entire ext_bus_cntrl_init function into the icache. + * This is necessary because we are going to change the same CS we + * are executing from. Otherwise a CPU lockup may occur. + *******************************************************************/ + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + + /* Calculate number of cache lines for this function */ + addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) + mtctr r4 +..ebcloop: + icbt r0, r3 /* prefetch cache line for addr in r3*/ + addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ + bdnz ..ebcloop /* continue for $CTR cache lines */ + + /******************************************************************** + * Delay to ensure all accesses to ROM are complete before changing + * bank 0 timings. 200usec should be enough. + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. + *******************************************************************/ + addis r3, 0, 0x0 + ori r3, r3, 0xA000 /* wait 200us from reset */ + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + /******************************************************************** + * Setup External Bus Controller (EBC). + *******************************************************************/ + addi r3, 0, epcr + mtdcr ebccfga, r3 + addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */ + ori r4, r4, 0x0 /* Drive CS with external master */ + mtdcr ebccfgd, r4 + + /******************************************************************** + * Change PCIINT signal to PerWE + *******************************************************************/ + mfdcr r4, cntrl1 + ori r4, r4, 0x4000 + mtdcr cntrl1, r4 + + /******************************************************************** + * Memory Bank 0 (Flash Bank 0) initialization + *******************************************************************/ + addi r3, 0, pb0ap + mtdcr ebccfga, r3 + addis r4, 0, CFG_W7O_EBC_PB0AP@h + ori r4, r4, CFG_W7O_EBC_PB0AP@l + mtdcr ebccfgd, r4 + + addi r3, 0, pb0cr + mtdcr ebccfga, r3 + addis r4, 0, CFG_W7O_EBC_PB0CR@h + ori r4, r4, CFG_W7O_EBC_PB0CR@l + mtdcr ebccfgd, r4 + + /******************************************************************** + * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs. + *******************************************************************/ + addi r3, 0, pb7ap + mtdcr ebccfga, r3 + addis r4, 0, CFG_W7O_EBC_PB7AP@h + ori r4, r4, CFG_W7O_EBC_PB7AP@l + mtdcr ebccfgd, r4 + + addi r3, 0, pb7cr + mtdcr ebccfga, r3 + addis r4, 0, CFG_W7O_EBC_PB7CR@h + ori r4, r4, CFG_W7O_EBC_PB7CR@l + mtdcr ebccfgd, r4 + + /* We are all done */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ +.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init +/* end ext_bus_cntlr_init() */ + +/****************************************************************************** + * Function: sdram_init + * + * Description: Configures SDRAM memory banks. + * + * Serial Presence Detect, "SPD," reads the SDRAM EEPROM + * via the IIC bus and then configures the SDRAM memory + * banks appropriately. If Auto Memory Configuration is + * is not used, it is assumed that a 4MB 11x8x2, non-ECC, + * SDRAM is soldered down. + * + * Notes: Expects that the stack is already setup. + *****************************************************************************/ + .section ".text" + .align 2 + .globl sdram_init + .type sdram_init, @function +sdram_init: + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save link register */ + + /* + * First call spd_sdram to try to init SDRAM according to the + * contents of the SPD EEPROM. If the SPD EEPROM is blank or + * erronious, spd_sdram returns 0 in R3. + */ + li r3,0 + bl spd_sdram + addic. r3, r3, 0 /* Check for error, save dram size */ + bne ..sdri_done /* If it worked, we're done... */ + + /******************************************************************** + * If SPD detection fails, we'll default to 4MB, 11x8x2, as this + * is the SMALLEST SDRAM size the 405 supports. We can do this + * because W7O boards have soldered on RAM, and there will always + * be some amount present. If we were using DIMMs, we should hang + * the board instead, since it doesn't have any RAM to continue + * running with. + *******************************************************************/ + + /* + * Disable memory controller to allow + * values to be changed. + */ + addi r3, 0, mem_mcopt1 + mtdcr memcfga, r3 + addis r4, 0, 0x0 + ori r4, r4, 0x0 + mtdcr memcfgd, r4 + + /* + * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 + * All other banks are disabled. + */ + addi r3, 0, mem_mb0cf + mtdcr memcfga, r3 + addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ + ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ + mtdcr memcfgd, r4 + + /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */ + addi r4, 0, 0 /* Zero the data reg */ + + addi r3, r3, 4 /* Point to MB1CF reg */ + mtdcr memcfga, r3 /* Set the address */ + mtdcr memcfgd, r4 /* Zero the reg */ + + addi r3, r3, 4 /* Point to MB2CF reg */ + mtdcr memcfga, r3 /* Set the address */ + mtdcr memcfgd, r4 /* Zero the reg */ + + addi r3, r3, 4 /* Point to MB3CF reg */ + mtdcr memcfga, r3 /* Set the address */ + mtdcr memcfgd, r4 /* Zero the reg */ + + /******************************************************************** + * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. + * To set the appropriate timings, we assume sdram is + * 100MHz (pc100 compliant). + *******************************************************************/ + + /* + * Set up SDTR1 + */ + addi r3, 0, mem_sdtr1 + mtdcr memcfga, r3 + addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ + ori r4, r4, 0x400D + mtdcr memcfgd, r4 + + /* + * Set RTR + */ + addi r3, 0, mem_rtr + mtdcr memcfga, r3 + addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ + mtdcr memcfgd, r4 + + /******************************************************************** + * Delay to ensure 200usec have elapsed since reset. Assume worst + * case that the core is running 200Mhz: + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + *******************************************************************/ + addis r3, 0, 0x0000 + ori r3, r3, 0xA000 /* Wait 200us from reset */ + mtctr r3 +..spinlp2: + bdnz ..spinlp2 /* spin loop */ + + /******************************************************************** + * Set memory controller options reg, MCOPT1. + *******************************************************************/ + addi r3, 0, mem_mcopt1 + mtdcr memcfga, r3 + addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ + ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ + mtdcr memcfgd, r4 /* EMDULR=1 */ + +..sdri_done: + /* restore and return */ + lwz r0, +12(r1) /* Get saved link register */ + addi r1, r1, +8 /* Remove frame from stack */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ +.Lfe1: .size sdram_init,.Lfe1-sdram_init +/* end sdram_init() */ diff --git a/board/w7o/post1.S b/board/w7o/post1.S new file mode 100644 index 0000000..21d206e --- /dev/null +++ b/board/w7o/post1.S @@ -0,0 +1,742 @@ +/* + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net + * and + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Description: + * Routine to exercise memory for the bringing up of our boards. + */ +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#include + +#include "errors.h" + +#define _ASMLANGUAGE + + .globl test_sdram + .globl test_led + .globl log_stat + .globl log_warn + .globl log_err + .globl temp_uart_init + .globl post_puts + .globl disp_hex + +/***************************************************** +******* Text Strings for low level printing ****** +******* In section got2 ******* +*****************************************************/ + +/* + * Define the text strings for errors and warnings. + * Switch to .data section. + */ + .section ".data" +err_str: .asciz "*** POST ERROR = " +warn_str: .asciz "*** POST WARNING = " +end_str: .asciz "\r\n" + +/* + * Enter the labels in Global Entry Table (GOT). + * Switch to .got2 section. + */ + START_GOT + GOT_ENTRY(err_str) + GOT_ENTRY(warn_str) + GOT_ENTRY(end_str) + END_GOT + +/* + * Switch back to .text section. + */ + .text + +/**************************************** + **************************************** + ******** LED register test ******** + **************************************** + ***************************************/ +test_led: + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -12(r1) /* Save back chain and move SP */ + stw r0, +16(r1) /* Save link register */ + stw r4, +8(r1) /* save R4 */ + + WATCHDOG_RESET /* Reset the watchdog */ + + addi r3, 0, ERR_FF /* first test value is ffff */ + addi r4, r3, 0 /* save copy of pattern */ + bl set_led /* store first test value */ + bl get_led /* read it back */ + xor. r4, r4, r3 /* compare to original */ +#if defined(CONFIG_W7OLMC) + andi. r4, r4, 0x00ff /* lmc has 8 bits */ +#else + andi. r4, r4, 0xffff /* lmg has 16 bits */ +#endif + beq LED2 /* next test */ + addi r3, 0, ERR_LED /* error code = 1 */ + bl log_err /* display error and halt */ +LED2: addi r3, 0, ERR_00 /* 2nd test value is 0000 */ + addi r4, r3, 0 /* save copy of pattern */ + bl set_led /* store first test value */ + bl get_led /* read it back */ + xor. r4, r4, r3 /* compare to original */ +#if defined(CONFIG_W7OLMC) + andi. r4, r4, 0x00ff /* lmc has 8 bits */ +#else + andi. r4, r4, 0xffff /* lmg has 16 bits */ +#endif + beq LED3 /* next test */ + addi r3, 0, ERR_LED /* error code = 1 */ + bl log_err /* display error and halt */ + +LED3: /* restore stack and return */ + lwz r0, +16(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + lwz r4, +8(r1) /* restore r4 */ + addi r1, r1, +12 /* Remove frame from stack */ + blr /* Return to calling function */ + +/**************************************** + **************************************** + ******** SDRAM TESTS ******** + **************************************** + ***************************************/ +test_sdram: + /* called with mem size in r3 */ + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -16(r1) /* Save back chain and move SP */ + stw r0, +20(r1) /* Save link register */ + stmw r30, +8(r1) /* save R30,R31 */ + /* r30 is log2(mem size) */ + /* r31 is mem size */ + + /* take log2 of total mem size */ + addi r31, r3, 0 /* save total mem size */ + addi r30, 0, 0 /* clear r30 */ +l2_loop: + srwi. r31, r31, 1 /* shift right 1 */ + addi r30, r30, 1 /* count shifts */ + bne l2_loop /* loop till done */ + addi r30, r30, -1 /* correct for over count */ + addi r31, r3, 0 /* save original size */ + + /* now kick the dog and test the mem */ + WATCHDOG_RESET /* Reset the watchdog */ + bl Data_Buster /* test crossed/shorted data lines */ + addi r3, r30, 0 /* get log2(memsize) */ + addi r4, r31, 0 /* get memsize */ + bl Ghost_Buster /* test crossed/shorted addr lines */ + addi r3, r31, 0 /* get mem size */ + bl Bit_Buster /* check for bad internal bits */ + + /* restore stack and return */ + lmw r30, +8(r1) /* Restore r30, r31 */ + lwz r0, +20(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + addi r1, r1, +16 /* Remove frame from stack */ + blr /* Return to calling function */ + + +/**************************************** + ******** sdram data bus test ******** + ***************************************/ +Data_Buster: + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -24(r1) /* Save back chain and move SP */ + stw r0, +28(r1) /* Save link register */ + stmw r28, 8(r1) /* save r28 - r31 on stack */ + /* r31 i/o register */ + /* r30 sdram base address */ + /* r29 5555 syndrom */ + /* r28 aaaa syndrom */ + + /* set up led register for this test */ + addi r3, 0, ERR_RAMG /* set led code to 1 */ + bl log_stat /* store test value */ + /* now test the dram data bus */ + xor r30, r30, r30 /* load r30 with base addr of sdram */ + addis r31, 0, 0x5555 /* load r31 with test value */ + ori r31, r31, 0x5555 + stw r31,0(r30) /* sto the value */ + lwz r29,0(r30) /* read it back */ + xor r29,r31,r29 /* compare it to original */ + addis r31, 0, 0xaaaa /* load r31 with test value */ + ori r31, r31, 0xaaaa + stw r31,0(r30) /* sto the value */ + lwz r28,0(r30) /* read it back */ + xor r28,r31,r28 /* compare it to original */ + or r3,r28,r29 /* or together both error terms */ + /* + * Now that we have the error bits, + * we have to decide which part they are in. + */ + bl get_idx /* r5 is now index to error */ + addi r3, r3, ERR_RAMG + cmpwi r3, ERR_RAMG /* check for errors */ + beq db_done /* skip if no errors */ + bl log_err /* log the error */ + +db_done: + lmw r28, 8(r1) /* restore r28 - r31 from stack */ + lwz r0, +28(r1) /* Get saved link register */ + addi r1, r1, +24 /* Remove frame from stack */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ + + +/**************************************************** + ******** test for address ghosting in dram ******** + ***************************************************/ + +Ghost_Buster: + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -36(r1) /* Save back chain and move SP */ + stw r0, +40(r1) /* Save link register */ + stmw r25, 8(r1) /* save r25 - r31 on stack */ + /* r31 = scratch register */ + /* r30 is main referance loop counter, + 0 to 23 */ + /* r29 is ghost loop count, 0 to 22 */ + /* r28 is referance address */ + /* r27 is ghost address */ + /* r26 is log2 (mem size) = + number of byte addr bits */ + /* r25 is mem size */ + + /* save the log2(mem size) and mem size */ + addi r26, r3, 0 /* r26 is number of byte addr bits */ + addi r25, r4, 0 /* r25 is mem size in bytes */ + + /* set the leds for address ghost test */ + addi r3, 0, ERR_ADDG + bl set_led + + /* first fill memory with zeros */ + srwi r31, r25, 2 /* convert bytes to longs */ + mtctr r31 /* setup byte counter */ + addi r28, 0, 0 /* start at address at 0 */ + addi r31, 0, 0 /* data value = 0 */ +clr_loop: + stw r31, 0(r28) /* Store zero value */ + addi r28, r28, 4 /* Increment to next word */ + andi. r27, r28, 0xffff /* check for 2^16 loops */ + bne clr_skip /* if not there, then skip */ + WATCHDOG_RESET /* kick the dog every now and then */ +clr_skip: + bdnz clr_loop /* Round and round... */ + + /* now do main test */ + addi r30, 0, 0 /* start referance counter at 0 */ +outside: + /* + * Calculate the referance address + * the referance address is calculated by setting the (r30-1) + * bit of the base address + * when r30=0, the referance address is the base address. + * thus the sequence 0,1,2,4,8,..,2^(n-1) + * setting the bit is done with the following shift functions. + */ + WATCHDOG_RESET /* Reset the watchdog */ + + addi r31, 0, 1 /* r31 = 1 */ + slw r28, r31, r30 /* set bit coresponding to loop cnt */ + srwi r28, r28, 1 /* then shift it right one so */ + /* we start at location 0 */ + /* fill referance address with Fs */ + addi r31, 0, 0x00ff /* r31 = one byte of set bits */ + stb r31,0(r28) /* save ff in referance address */ + + /* ghost (inner) loop, now check all posible ghosted addresses */ + addi r29, 0, 0 /* start ghosted loop counter at 0 */ +inside: + /* + * Calculate the ghost address by flipping one + * bit of referance address. This gives the + * sequence 1,2,4,8,...,2^(n-1) + */ + addi r31, 0, 1 /* r31 = 1 */ + slw r27, r31, r29 /* set bit coresponding to loop cnt */ + xor r27, r28, r27 /* ghost address = ref addr with + bit flipped*/ + + /* now check for ghosting */ + lbz r31,0(r27) /* get content of ghost addr */ + cmpwi r31, 0 /* compare read value to 0 */ + bne Casper /* we found a ghost! */ + + /* now close ghost ( inner ) loop */ + addi r29, r29, 1 /* increment inner loop counter */ + cmpw r29, r26 /* check for last inner loop */ + blt inside /* do more inner loops */ + + /* now close referance ( outer ) loop */ + addi r31, 0, 0 /* r31 = zero */ + stb r31, 0(28) /* zero out the altered address loc. */ + /* + * Increment and check for end, count is zero based. + * With the ble, this gives us one more loops than + * address bits for sequence 0,1,2,4,8,...2^(n-1) + */ + addi r30, r30, 1 /* increment outer loop counter */ + cmpw r30, r26 /* check for last inner loop */ + ble outside /* do more outer loops */ + + /* were done, lets go home */ + b gb_done +Casper: /* we found a ghost !! */ + addi r3, 0, ERR_ADDF /* get indexed error message */ + bl log_err /* log error led error code */ +gb_done: /* pack your bags, and go home */ + lmw r25, 8(r1) /* restore r25 - r31 from stack */ + lwz r0, +40(r1) /* Get saved link register */ + addi r1, r1, +36 /* Remove frame from stack */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ + +/**************************************************** + ******** SDRAM data fill tests ********** + ***************************************************/ +Bit_Buster: + /* called with mem size in r3 */ + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -16(r1) /* Save back chain and move SP */ + stw r0, +20(r1) /* Save link register */ + stw r4, +8(r1) /* save R4 */ + stw r5, +12(r1) /* save r5 */ + + addis r5, r3, 0 /* save mem size */ + + /* Test 55555555 */ + addi r3, 0, ERR_R55G /* set up error code in case we fail */ + bl log_stat /* store test value */ + addis r4, 0, 0x5555 + ori r4, r4, 0x5555 + bl fill_test + + /* Test aaaaaaaa */ + addi r3, 0, ERR_RAAG /* set up error code in case we fail */ + bl log_stat /* store test value */ + addis r4, 0, 0xAAAA + ori r4, r4, 0xAAAA + bl fill_test + + /* Test 00000000 */ + addi r3, 0, ERR_R00G /* set up error code in case we fail */ + bl log_stat /* store test value */ + addis r4, 0, 0 + ori r4, r4, 0 + bl fill_test + + /* restore stack and return */ + lwz r5, +12(r1) /* restore r4 */ + lwz r4, +8(r1) /* restore r4 */ + lwz r0, +20(r1) /* Get saved link register */ + addi r1, r1, +16 /* Remove frame from stack */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ + + +/**************************************************** + ******** fill test ******** + ***************************************************/ +/* tests memory by filling with value, and reading back */ +/* r5 = Size of memory in bytes */ +/* r4 = Value to write */ +/* r3 = Error code */ +fill_test: + mflr r0 /* Get link register */ + stwu r1, -32(r1) /* Save back chain and move SP */ + stw r0, +36(r1) /* Save link register */ + stmw r27, 8(r1) /* save r27 - r31 on stack */ + /* r31 - scratch register */ + /* r30 - memory address */ + mr r27, r3 + mr r28, r4 + mr r29, r5 + + WATCHDOG_RESET /* Reset the watchdog */ + + /* first fill memory with Value */ + srawi r31, r29, 2 /* convert bytes to longs */ + mtctr r31 /* setup counter */ + addi r30, 0, 0 /* Make r30 = addr 0 */ +ft_0: stw r28, 0(r30) /* Store value */ + addi r30, r30, 4 /* Increment to next word */ + andi. r31, r30, 0xffff /* check for 2^16 loops */ + bne ft_0a /* if not there, then skip */ + WATCHDOG_RESET /* kick the dog every now and then */ +ft_0a: bdnz ft_0 /* Round and round... */ + + WATCHDOG_RESET /* Reset the watchdog */ + + /* Now confirm Value is in memory */ + srawi r31, r29, 2 /* convert bytes to longs */ + mtctr r31 /* setup counter */ + addi r30, 0, 0 /* Make r30 = addr 0 */ +ft_1: lwz r31, 0(r30) /* get value from memory */ + xor. r31, r31, r28 /* Writen = Read ? */ + bne ft_err /* If bad, than halt */ + addi r30, r30, 4 /* Increment to next word */ + andi. r31, r30, 0xffff /* check for 2^16 loops*/ + bne ft_1a /* if not there, then skip */ + WATCHDOG_RESET /* kick the dog every now and then */ +ft_1a: bdnz ft_1 /* Round and round... */ + + WATCHDOG_RESET /* Reset the watchdog */ + + b fill_done /* restore and return */ + +ft_err: addi r29, r27, 0 /* save current led code */ + addi r27, r31, 0 /* get pattern in r27 */ + bl get_idx /* get index from r27 */ + add r27, r27, r29 /* add index to old led code */ + bl log_err /* output led err code, halt CPU */ + +fill_done: + lmw r27, 8(r1) /* restore r27 - r31 from stack */ + lwz r0, +36(r1) /* Get saved link register */ + addi r1, r1, +32 /* Remove frame from stack */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ + + +/**************************************************** + ******* get error index from r3 pattern ******** + ***************************************************/ +get_idx: /* r3 = (MSW(r3) !=0)*2 + + (LSW(r3) !=0) */ + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -12(r1) /* Save back chain and move SP */ + stw r0, +16(r1) /* Save link register */ + stw r4, +8(r1) /* save R4 */ + + andi. r4, r3, 0xffff /* check for lower bits */ + beq gi2 /* skip if no bits set */ + andis. r4, r3, 0xffff /* check for upper bits */ + beq gi3 /* skip if no bits set */ + addi r3, 0, 3 /* both upper and lower bits set */ + b gi_done +gi2: andis. r4, r3, 0xffff /* check for upper bits*/ + beq gi4 /* skip if no bits set */ + addi r3, 0, 2 /* only upper bits set */ + b gi_done +gi3: addi r3, 0, 1 /* only lower bits set */ + b gi_done +gi4: addi r3, 0, 0 /* no bits set */ +gi_done: + /* restore stack and return */ + lwz r0, +16(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + lwz r4, +8(r1) /* restore r4 */ + addi r1, r1, +12 /* Remove frame from stack */ + blr /* Return to calling function */ + +/**************************************************** + ******** set LED to R5 and hang ******** + ***************************************************/ +log_stat: /* output a led code and continue */ +set_led: + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -12(r1) /* Save back chain and move SP */ + stw r0, +16(r1) /* Save link register */ + stw r4, +8(r1) /* save R4 */ + + addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */ +#if defined(CONFIG_W7OLMG) /* only on gateway, invert outputs */ + xori r3,r3, 0xffff /* complement led code, active low */ + sth r3, 0(r4) /* store first test value */ + xori r3,r3, 0xffff /* complement led code, active low */ +#else /* if not gateway, then don't invert */ + sth r3, 0(r4) /* store first test value */ +#endif + + /* restore stack and return */ + lwz r0, +16(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + lwz r4, +8(r1) /* restore r4 */ + addi r1, r1, +12 /* Remove frame from stack */ + blr /* Return to calling function */ + +get_led: + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -12(r1) /* Save back chain and move SP */ + stw r0, +16(r1) /* Save link register */ + stw r4, +8(r1) /* save R4 */ + + addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */ + lhz r3, 0(r4) /* store first test value */ +#if defined(CONFIG_W7OLMG) /* only on gateway, invert inputs */ + xori r3,r3, 0xffff /* complement led code, active low */ +#endif + + /* restore stack and return */ + lwz r0, +16(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + lwz r4, +8(r1) /* restore r4 */ + addi r1, r1, +12 /* Remove frame from stack */ + blr /* Return to calling function */ + +log_err: /* output the error and hang the board ( for now ) */ + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -12(r1) /* Save back chain and move SP */ + stw r0, +16(r1) /* Save link register */ + stw r3, +8(r1) /* save a copy of error code */ + bl set_led /* set the led pattern */ + GET_GOT /* get GOT address in r14 */ + lwz r3,GOT(err_str) /* get address of string */ + bl post_puts /* output the warning string */ + lwz r3, +8(r1) /* get error code */ + addi r4, 0, 2 /* set disp length to 2 nibbles */ + bl disp_hex /* output the error code */ + lwz r3,GOT(end_str) /* get address of string */ + bl post_puts /* output the warning string */ +halt: + b halt /* hang */ + + /* restore stack and return */ + lwz r0, +16(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + addi r1, r1, +12 /* Remove frame from stack */ + blr /* Return to calling function */ + +log_warn: /* output a warning, then continue with operations */ + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -16(r1) /* Save back chain and move SP */ + stw r0, +20(r1) /* Save link register */ + stw r3, +8(r1) /* save a copy of error code */ + stw r14, +12(r1) /* save a copy of r14 (used by GOT) */ + + bl set_led /* set the led pattern */ + GET_GOT /* get GOT address in r14 */ + lwz r3,GOT(warn_str) /* get address of string */ + bl post_puts /* output the warning string */ + lwz r3, +8(r1) /* get error code */ + addi r4, 0, 2 /* set disp length to 2 nibbles */ + bl disp_hex /* output the error code */ + lwz r3,GOT(end_str) /* get address of string */ + bl post_puts /* output the warning string */ + + addis r3, 0, 64 /* has a long delay */ + mtctr r3 +log_2: + WATCHDOG_RESET /* this keeps dog from barking, */ + /* and takes time */ + bdnz log_2 /* loop till time expires */ + + /* restore stack and return */ + lwz r0, +20(r1) /* Get saved link register */ + lwz r14, +12(r1) /* restore r14 */ + mtlr r0 /* Restore link register */ + addi r1, r1, +16 /* Remove frame from stack */ + blr /* Return to calling function */ + +/******************************************************************* + * temp_uart_init + * Temporary UART initialization routine + * Sets up UART0 to run at 9600N81 off of the internal clock. + * R3-R4 are used. + ******************************************************************/ +temp_uart_init: + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save link register */ + + addis r3, 0, 0xef60 + ori r3, r3, 0x0303 /* r3 = UART0_LCR */ + addi r4, 0, 0x83 /* n81 format, divisor regs enabled */ + stb r4, 0(r3) + + /* set baud rate to use internal clock, + baud = (200e6/16)/31/42 = 9600 */ + + addis r3, 0, 0xef60 /* Address of baud divisor reg */ + ori r3, r3, 0x0300 /* UART0_DLM */ + addi r4, 0, +42 /* uart baud divisor LSB = 93 */ + stb r4, 0(r3) /* baud = (200 /16)/14/93 */ + + addi r3, r3, 0x0001 /* uart baud divisor addr */ + addi r4, 0, 0 + stb r4, 0(r3) /* Divisor Latch MSB = 0 */ + + addis r3, 0, 0xef60 + ori r3, r3, 0x0303 /* r3 = UART0_LCR */ + addi r4, 0, 0x03 /* n81 format, tx/rx regs enabled */ + stb r4, 0(r3) + + /* output a few line feeds */ + addi r3, 0, '\n' /* load line feed */ + bl post_putc /* output the char */ + addi r3, 0, '\n' /* load line feed */ + bl post_putc /* output the char */ + + /* restore stack and return */ + lwz r0, +12(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + addi r1, r1, +8 /* Remove frame from stack */ + blr /* Return to calling function */ + +/********************************************************************** + ** post_putc + ** outputs charactor in R3 + ** r3 returns the error code ( -1 if there is an error ) + *********************************************************************/ + +post_putc: + + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -20(r1) /* Save back chain and move SP */ + stw r0, +24(r1) /* Save link register */ + stmw r29, 8(r1) /* save r29 - r31 on stack + r31 - uart base address + r30 - delay counter + r29 - scratch reg */ + + addis r31, 0, 0xef60 /* Point to uart base */ + ori r31, r31, 0x0300 + addis r30, 0, 152 /* Load about 10,000,000 ticks. */ +pputc_lp: + lbz r29, 5(r31) /* Read Line Status Register */ + andi. r29, r29, 0x20 /* Check THRE status */ + bne thre_set /* Branch if FIFO empty */ + addic. r30, r30, -1 /* Decrement and check if empty. */ + bne pputc_lp /* Try, try again */ + addi r3, 0, -1 /* Load error code for timeout */ + b pputc_done /* Bail out with error code set */ +thre_set: + stb r3, 0(r31) /* Store character to UART */ + addi r3, 0, 0 /* clear error code */ +pputc_done: + lmw r29, 8(r1) /*restore r29 - r31 from stack */ + lwz r0, +24(r1) /* Get saved link register */ + addi r1, r1, +20 /* Remove frame from stack */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ + + +/**************************************************************** + post_puts + Accepts a null-terminated string pointed to by R3 + Outputs to the serial port until 0x00 is found. + r3 returns the error code ( -1 if there is an error ) +*****************************************************************/ +post_puts: + + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -12(r1) /* Save back chain and move SP */ + stw r0, +16(r1) /* Save link register */ + stw r31, 8(r1) /* save r31 - char pointer */ + + addi r31, r3, 0 /* move pointer to R31 */ +pputs_nxt: + lbz r3, 0(r31) /* Get next character */ + addic. r3, r3, 0 /* Check for zero */ + beq pputs_term /* bail out if zero */ + bl post_putc /* output the char */ + addic. r3, r3, 0 /* check for error */ + bne pputs_err + addi r31, r31, 1 /* point to next char */ + b pputs_nxt /* loop till term */ +pputs_err: + addi r3, 0, -1 /* set error code */ + b pputs_end /* were outa here */ +pputs_term: + addi r3, 0, 1 /* set success code */ + /* restore stack and return */ +pputs_end: + lwz r31, 8(r1) /* restore r27 - r31 from stack */ + lwz r0, +16(r1) /* Get saved link register */ + addi r1, r1, +12 /* Remove frame from stack */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ + + +/******************************************************************** + ***** disp_hex + ***** Routine to display a hex value from a register. + ***** R3 is value to display + ***** R4 is number of nibbles to display ie 2 for byte 8 for (long)word + ***** Returns -1 in R3 if there is an error ( ie serial port hangs ) + ***** Returns 0 in R3 if no error + *******************************************************************/ +disp_hex: + /* save the return info on stack */ + mflr r0 /* Get link register */ + stwu r1, -16(r1) /* Save back chain and move SP */ + stw r0, +20(r1) /* Save link register */ + stmw r30, 8(r1) /* save r30 - r31 on stack */ + /* r31 output char */ + /* r30 uart base address */ + addi r30, 0, 8 /* Go through 8 nibbles. */ + addi r31, r3, 0 +pputh_nxt: + rlwinm r31, r31, 4, 0, 31 /* Rotate next nibble into position */ + andi. r3, r31, 0x0f /* Get nibble. */ + addi r3, r3, 0x30 /* Add zero's ASCII code. */ + cmpwi r3, 0x03a + blt pputh_out + addi r3, r3, 0x07 /* 0x27 for lower case. */ +pputh_out: + cmpw r30, r4 + bgt pputh_skip + bl post_putc + addic. r3, r3, 0 /* check for error */ + bne pputh_err +pputh_skip: + addic. r30, r30, -1 + bne pputh_nxt + xor r3, r3, r3 /* Clear error code */ + b pputh_done +pputh_err: + addi r3, 0, -1 /* set error code */ +pputh_done: + /* restore stack and return */ + lmw r30, 8(r1) /* restore r30 - r31 from stack */ + lwz r0, +20(r1) /* Get saved link register */ + addi r1, r1, +16 /* Remove frame from stack */ + mtlr r0 /* Restore link register */ + blr /* Return to calling function */ diff --git a/board/w7o/post2.c b/board/w7o/post2.c new file mode 100644 index 0000000..e590128 --- /dev/null +++ b/board/w7o/post2.c @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * and + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "errors.h" +#include "dtt.h" + +#if defined(CONFIG_RTC_M48T35A) +void rtctest(void) +{ + volatile uchar *tchar = (uchar*)(CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 9); + struct rtc_time tmp; + + /* set up led code for RTC tests */ + log_stat(ERR_RTCG); + + /* + * Do RTC battery test. The first write after power up + * fails if battery is low. + */ + *tchar = 0xaa; + if ((*tchar ^ 0xaa) != 0x0) log_warn(ERR_RTCBAT); + *tchar = 0x55; /* Reset test address */ + + /* + * Now lets check the validity of the values in the RTC. + */ + rtc_get(&tmp); + if ((tmp.tm_sec < 0) | (tmp.tm_sec > 59) | + (tmp.tm_min < 0) | (tmp.tm_min > 59) | + (tmp.tm_hour < 0) | (tmp.tm_hour > 23) | + (tmp.tm_mday < 1 ) | (tmp.tm_mday > 31) | + (tmp.tm_mon < 1 ) | (tmp.tm_mon > 12) | + (tmp.tm_year < 2000) | (tmp.tm_year > 2500) | + (tmp.tm_wday < 1 ) | (tmp.tm_wday > 7)) { + log_warn(ERR_RTCTIM); + rtc_reset(); + } + + /* + * Now lets do a check to see if the NV RAM is there. + */ + *tchar = 0xaa; + if ((*tchar ^ 0xaa) != 0x0) log_err(ERR_RTCVAL); + *tchar = 0x55; /* Reset test address */ + +} /* rtctest() */ +#endif /* CONFIG_RTC_M48T35A */ + + +#ifdef CONFIG_DTT_LM75 +int dtt_test(int sensor) +{ + short temp, trip, hyst; + + /* get values */ + temp = dtt_read(sensor, DTT_READ_TEMP) / 256; + trip = dtt_read(sensor, DTT_TEMP_SET) / 256; + hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256; + + /* check values */ + if ((hyst != (CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS)) || + (trip != CFG_DTT_MAX_TEMP) || + (temp < CFG_DTT_LOW_TEMP) || (temp > CFG_DTT_MAX_TEMP)) + return 1; + + return 0; +} /* dtt_test() */ +#endif /* CONFIG_DTT_LM75 */ + +/*****************************************/ + +void post2(void) +{ +#if defined(CONFIG_RTC_M48T35A) + rtctest(); +#endif /* CONFIG_RTC_M48T35A */ + +#ifdef CONFIG_DTT_LM75 + log_stat(ERR_TempG); + if(dtt_test(2) != 0) log_warn(ERR_Ttest0); + if(dtt_test(4) != 0) log_warn(ERR_Ttest1); +#endif /* CONFIG_DTT_LM75 */ +} /* post2() */ diff --git a/board/w7o/u-boot.lds b/board/w7o/u-boot.lds new file mode 100644 index 0000000..7e3e15d --- /dev/null +++ b/board/w7o/u-boot.lds @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + board/w7o/init.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug new file mode 100644 index 0000000..a0c72c9 --- /dev/null +++ b/board/w7o/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/w7o/vpd.c b/board/w7o/vpd.c new file mode 100644 index 0000000..2ce1568 --- /dev/null +++ b/board/w7o/vpd.c @@ -0,0 +1,407 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(VXWORKS) +# include +# include +# define CFG_DEF_EEPROM_ADDR 0xa0 +extern char iicReadByte( char, char ); +extern ulong_t crc32( unsigned char *, unsigned long ); +#else +#include +#endif + +#include "vpd.h" + +/* + * vpd_reader() - reads VPD data from I2C EEPROMS. + * returns pointer to buffer or NULL. + */ +static unsigned char * +vpd_reader(unsigned char *buf, unsigned dev_addr, unsigned off, unsigned count) +{ + unsigned offset = off; /* Calculated offset */ + + /* + * The main board EEPROM contains + * SDRAM SPD in the first 128 bytes, + * so skew the offset. + */ + if (dev_addr == CFG_DEF_EEPROM_ADDR) + offset += SDRAM_SPD_DATA_SIZE; + + /* Try to read the I2C EEPROM */ +#if defined(VXWORKS) + { + int i; + for( i = 0; i < count; ++i ) { + buf[ i ] = iicReadByte( dev_addr, offset+i ); + } + } +#else + if (eeprom_read(dev_addr, offset, buf, count)) { + printf("Failed to read %d bytes from VPD EEPROM 0x%x @ 0x%x\n", + count, dev_addr, offset); + return NULL; + } +#endif + + return buf; +} /* vpd_reader() */ + + +/* + * vpd_get_packet() - returns next VPD packet or NULL. + */ +static vpd_packet_t *vpd_get_packet(vpd_packet_t *vpd_packet) +{ + vpd_packet_t *packet = vpd_packet; + + if (packet != NULL) { + if (packet->identifier == VPD_PID_TERM) + return NULL; + else + packet = (vpd_packet_t *)((char *)packet + packet->size + 2); + } + + return packet; +} /* vpd_get_packet() */ + + +/* + * vpd_find_packet() - Locates and returns the specified + * VPD packet or NULL on error. + */ +static vpd_packet_t *vpd_find_packet(vpd_t *vpd, unsigned char ident) +{ + vpd_packet_t *packet = (vpd_packet_t *)&vpd->packets; + + /* Guaranteed illegal */ + if (ident == VPD_PID_GI) + return NULL; + + /* Scan tuples looking for a match */ + while ((packet->identifier != ident) && + (packet->identifier != VPD_PID_TERM)) + packet = vpd_get_packet(packet); + + /* Did we find it? */ + if ((packet->identifier) && (packet->identifier != ident)) + return NULL; + return packet; +} + + +/* + * vpd_is_valid() - Validates contents of VPD data + * in I2C EEPROM. Returns 1 for + * success or 0 for failure. + */ +static int vpd_is_valid(unsigned dev_addr, unsigned char *buf) +{ + unsigned num_bytes; + vpd_packet_t *packet; + vpd_t *vpd = (vpd_t *)buf; + unsigned short stored_crc16, calc_crc16 = 0xffff; + + /* Check Eyecatcher */ + if (strncmp((char *)(vpd->header.eyecatcher), VPD_EYECATCHER, VPD_EYE_SIZE) != 0) { + unsigned offset = 0; + if (dev_addr == CFG_DEF_EEPROM_ADDR) + offset += SDRAM_SPD_DATA_SIZE; + printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr, offset); + + return 0; + } + + /* Check Length */ + if (vpd->header.size> VPD_MAX_EEPROM_SIZE) { + printf("Error: VPD EEPROM 0x%x contains bad size 0x%x\n", + dev_addr, vpd->header.size); + return 0; + } + + /* Now find the termination packet */ + if ((packet = vpd_find_packet(vpd, VPD_PID_TERM)) == NULL) { + printf("Error: VPD EEPROM 0x%x missing termination packet\n", + dev_addr); + return 0; + } + + /* Calculate data size */ + num_bytes = (unsigned long)((unsigned char *)packet - + (unsigned char *)vpd + sizeof(vpd_packet_t)); + + /* Find stored CRC and clear it */ + if ((packet = vpd_find_packet(vpd, VPD_PID_CRC)) == NULL) { + printf("Error: VPD EEPROM 0x%x missing CRC\n", dev_addr); + return 0; + } + stored_crc16 = *((ushort *)packet->data); + *(ushort *)packet->data = 0; + + /* OK, lets calculate the CRC and check it */ +#if defined(VXWORKS) + calc_crc16 = (0xffff & crc32(buf, num_bytes)); +#else + calc_crc16 = (0xffff & crc32(0, buf, num_bytes)); +#endif + *(ushort *)packet->data = stored_crc16; /* Now restore the CRC */ + if (stored_crc16 != calc_crc16) { + printf("Error: VPD EEPROM 0x%x has bad CRC 0x%x\n", + dev_addr, stored_crc16); + return 0; + } + + return 1; +} /* vpd_is_valid() */ + + +/* + * size_ok() - Check to see if packet size matches + * size of data we want. Returns 1 for + * good match or 0 for failure. + */ +static int size_ok(vpd_packet_t *packet, unsigned long size) +{ + if (packet->size != size) { + printf("VPD Packet 0x%x corrupt.\n", packet->identifier); + return 0; + } + return 1; +} /* size_ok() */ + + +/* + * strlen_ok() - Check to see if packet size matches + * strlen of the string we want to populate. + * Returns 1 for valid length or 0 for failure. + */ +static int strlen_ok(vpd_packet_t *packet, unsigned long length) +{ + if (packet->size >= length) { + printf("VPD Packet 0x%x corrupt.\n", packet->identifier); + return 0; + } + return 1; +} /* strlen_ok() */ + + +/* + * get_vpd_data() - populates the passed VPD structure 'vpdInfo' + * with data obtained from the specified + * I2C EEPROM 'dev_addr'. Returns 0 for + * success or 1 for failure. + */ +int vpd_get_data(unsigned char dev_addr, VPD *vpdInfo) +{ + unsigned char buf[VPD_EEPROM_SIZE]; + vpd_t *vpd = (vpd_t *)buf; + vpd_packet_t *packet; + + if (vpdInfo == NULL) + return 1; + + /* + * Fill vpdInfo with 0s to blank out + * unused fields, fill vpdInfo->ethAddrs + * with all 0xffs so that other's code can + * determine how many real Ethernet addresses + * there are. OUIs starting with 0xff are + * broadcast addresses, and would never be + * permantely stored. + */ + memset((void *)vpdInfo, 0, sizeof(VPD)); + memset((void *)&vpdInfo->ethAddrs, 0xff, sizeof(vpdInfo->ethAddrs)); + vpdInfo->_devAddr = dev_addr; + + /* Read the minimum size first */ + if (vpd_reader(buf, dev_addr, 0, VPD_EEPROM_SIZE) == NULL) { + return 1; + } + + /* Check validity of VPD data */ + if (!vpd_is_valid(dev_addr, buf)) { + printf("VPD Data is INVALID!\n"); + return 1; + } + + /* + * Walk all the packets and populate + * the VPD info structure. + */ + packet = (vpd_packet_t *)&vpd->packets; + do { + switch (packet->identifier) { + case VPD_PID_GI: + printf("Error: Illegal VPD value\n"); + break; + case VPD_PID_PID: + if (strlen_ok(packet, MAX_PROD_ID)) { + strncpy(vpdInfo->productId, + (char *)(packet->data), packet->size); + } + break; + case VPD_PID_REV: + if (size_ok(packet, sizeof(char))) + vpdInfo->revisionId = *packet->data; + break; + case VPD_PID_SN: + if (size_ok(packet, sizeof(unsigned long))) { + vpdInfo->serialNum = + *(unsigned long *)packet->data; + } + break; + case VPD_PID_MANID: + if (size_ok(packet, sizeof(unsigned char))) + vpdInfo->manuID = *packet->data; + break; + case VPD_PID_PCO: + if (size_ok(packet, sizeof(unsigned long))) { + vpdInfo->configOpt = + *(unsigned long *)packet->data; + } + break; + case VPD_PID_SYSCLK: + if (size_ok(packet, sizeof(unsigned long))) + vpdInfo->sysClk = *(unsigned long *)packet->data; + break; + case VPD_PID_SERCLK: + if (size_ok(packet, sizeof(unsigned long))) + vpdInfo->serClk = *(unsigned long *)packet->data; + break; + case VPD_PID_FLASH: + if (size_ok(packet, 9)) { /* XXX - hardcoded, + padding in struct */ + memcpy(&vpdInfo->flashCfg, packet->data, 9); + } + break; + case VPD_PID_ETHADDR: + memcpy(vpdInfo->ethAddrs, packet->data, packet->size); + break; + case VPD_PID_POTS: + if (size_ok(packet, sizeof(char))) + vpdInfo->numPOTS = (unsigned)*packet->data; + break; + case VPD_PID_DS1: + if (size_ok(packet, sizeof(char))) + vpdInfo->numDS1 = (unsigned)*packet->data; + case VPD_PID_GAL: + case VPD_PID_CRC: + case VPD_PID_TERM: + break; + default: + printf("Warning: Found unknown VPD packet ID 0x%x\n", + packet->identifier); + break; + } + } while ((packet = vpd_get_packet(packet))); + + return 0; +} /* end get_vpd_data() */ + + +/* + * vpd_init() - Initialize default VPD environment + */ +int vpd_init(unsigned char dev_addr) +{ + return (0); +} /* vpd_init() */ + + +/* + * vpd_print() - Pretty print the VPD data. + */ +void vpd_print(VPD *vpdInfo) +{ + const char *const sp = ""; + const char *const sfmt = "%4s%-20s: \"%s\"\n"; + const char *const cfmt = "%4s%-20s: '%c'\n"; + const char *const dfmt = "%4s%-20s: %ld\n"; + const char *const hfmt = "%4s%-20s: %08lX\n"; + const char *const dsfmt = "%4s%-20s: %d\n"; + const char *const hsfmt = "%4s%-20s: %04X\n"; + const char *const dhfmt = "%4s%-20s: %ld (%lX)\n"; + + printf("VPD read from I2C device: %02X\n", vpdInfo->_devAddr); + + if (vpdInfo->productId[0]) + printf(sfmt, sp, "Product ID", vpdInfo->productId); + else + printf(sfmt, sp, "Product ID", "UNKNOWN"); + + if (vpdInfo->revisionId) + printf(cfmt, sp, "Revision ID", vpdInfo->revisionId); + + if (vpdInfo->serialNum) + printf(dfmt, sp, "Serial Number", vpdInfo->serialNum); + + if (vpdInfo->manuID) + printf(dfmt, sp, "Manufacture ID", (long)vpdInfo->manuID); + + if (vpdInfo->configOpt) + printf(hfmt, sp, "Configuration", vpdInfo->configOpt); + + if (vpdInfo->sysClk) + printf(dhfmt, sp, "System Clock", vpdInfo->sysClk, vpdInfo->sysClk); + + if (vpdInfo->serClk) + printf(dhfmt, sp, "Serial Clock", vpdInfo->serClk, vpdInfo->serClk); + + if (vpdInfo->numPOTS) + printf(dfmt, sp, "Number of POTS lines", vpdInfo->numPOTS); + + if (vpdInfo->numDS1) + printf(dfmt, sp, "Number of DS1s", vpdInfo->numDS1); + + /* Print Ethernet Addresses */ + if (vpdInfo->ethAddrs[0][0] != 0xff) { + int i, j; + printf("%4sEtherNet Address(es): ", sp); + for (i = 0; i < MAX_ETH_ADDRS; i++) { + if (vpdInfo->ethAddrs[i][0] != 0xff) { + for (j = 0; j < 6; j++) { + printf("%02X", vpdInfo->ethAddrs[i][j]); + if (((j + 1) % 6) != 0) + printf(":"); + else + printf(" "); + } + if (((i + 1) % 3) == 0) printf("\n%24s: ", sp); + } + } + printf("\n"); + } + + if (vpdInfo->flashCfg.mfg && vpdInfo->flashCfg.dev) { + printf("Main Flash Configuration:\n"); + printf(hsfmt, sp, "Manufacture ID", vpdInfo->flashCfg.mfg); + printf(hsfmt, sp, "Device ID", vpdInfo->flashCfg.dev); + printf(dsfmt, sp, "Device Width", vpdInfo->flashCfg.devWidth); + printf(dsfmt, sp, "Num. Devices", vpdInfo->flashCfg.numDevs); + printf(dsfmt, sp, "Num. Columns", vpdInfo->flashCfg.numCols); + printf(dsfmt, sp, "Column Width", vpdInfo->flashCfg.colWidth); + printf(dsfmt, sp, "WE Data Width", vpdInfo->flashCfg.weDataWidth); + } +} /* vpd_print() */ diff --git a/board/w7o/vpd.h b/board/w7o/vpd.h new file mode 100644 index 0000000..1b71c8d --- /dev/null +++ b/board/w7o/vpd.h @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _VPD_H_ +#define _VPD_H_ + +/* + * Main Flash Configuration. + */ +typedef struct flashCfg_s { + unsigned short mfg; /* Manufacture ID */ + unsigned short dev; /* Device ID */ + unsigned char devWidth; /* Device Width */ + unsigned char numDevs; /* Number of devices */ + unsigned char numCols; /* Number of columns */ + unsigned char colWidth; /* Width of a column */ + unsigned char weDataWidth; /* Write/Erase Data Width */ +} flashCfg_t; + +/* + * Vital Product Data - VPD + */ +#define MAX_PROD_ID 15 +#define MAX_ETH_ADDRS 10 +typedef unsigned char EthAddr[6]; +typedef struct vpd { + unsigned char _devAddr; /* Device address during read */ + char productId[MAX_PROD_ID]; /* Product ID */ + char revisionId; /* Revision ID as a char */ + unsigned long serialNum; /* Serial number */ + unsigned char manuID; /* Manufact ID - byte int */ + unsigned long configOpt; /* Config Option - bit field */ + unsigned long sysClk; /* System clock in Hertz */ + unsigned long serClk; /* Ext. clock in Hertz */ + flashCfg_t flashCfg; /* Flash configuration */ + unsigned long numPOTS; /* Number of POTS lines */ + unsigned long numDS1; /* Number of DS1 circuits */ + EthAddr ethAddrs[MAX_ETH_ADDRS]; /* Ethernet MAC, 1st = craft */ +} VPD; + + +#define VPD_MAX_EEPROM_SIZE 512 /* Max size VPD EEPROM */ +#define SDRAM_SPD_DATA_SIZE 128 /* Size SPD in VPD EEPROM */ + +/* + * PIDs - Packet Identifiers + */ +#define VPD_PID_GI 0x0 /* Guaranted Illegal */ +#define VPD_PID_PID 0x1 /* Product Identifier */ +#define VPD_PID_REV 0x2 /* Product Revision */ +#define VPD_PID_SN 0x3 /* Serial Number */ +#define VPD_PID_MANID 0x4 /* Manufacture ID */ +#define VPD_PID_PCO 0x5 /* Product configuration */ +#define VPD_PID_SYSCLK 0x6 /* System Clock */ +#define VPD_PID_SERCLK 0x7 /* Ser. Clk. Speed in Hertz */ +#define VPD_PID_CRC 0x8 /* VPD CRC */ +#define VPD_PID_FLASH 0x9 /* Flash Configuration */ +#define VPD_PID_ETHADDR 0xA /* Ethernet Address(es) */ +#define VPD_PID_GAL 0xB /* Galileo Switch Config */ +#define VPD_PID_POTS 0xC /* Number of POTS Lines */ +#define VPD_PID_DS1 0xD /* Number of DS1s */ +#define VPD_PID_TERM 0xFF /* Termination packet */ + +/* + * VPD - Eyecatcher/Magic + */ +#define VPD_EYECATCHER "W7O" +#define VPD_EYE_SIZE 3 +typedef struct vpd_header { + unsigned char eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "W7O" */ + unsigned short size __attribute__((packed)); /* size of EEPROM */ +} vpd_header_t; + + +#define VPD_DATA_SIZE (VPD_MAX_EEPROM_SIZE - SDRAM_SPD_DATA_SIZE - \ + sizeof(vpd_header_t)) +typedef struct vpd_s { + vpd_header_t header; + unsigned char packets[VPD_DATA_SIZE]; +} vpd_t; + +typedef struct vpd_packet { + unsigned char identifier; + unsigned char size; + unsigned char data[1]; +} vpd_packet_t; + +/* + * VPD configOpt bit mask + */ +#define VPD_HAS_BBRAM 0x1 /* Battery backed SRAM */ +#define VPD_HAS_RTC 0x2 /* Battery backed RTC */ +#define VPD_HAS_EXT_SER_CLK 0x4 /* External serial clock */ +#define VPD_HAS_SER_TRANS_1 0x8 /* COM1 transceiver */ +#define VPD_HAS_SER_TRANS_2 0x10 /* COM2 transceiver */ +#define VPD_HAS_CRAFT_PHY 0x20 /* CRAFT Ethernet */ +#define VPD_HAS_DTT_1 0x40 /* I2C Digital therm. #1 */ +#define VPD_HAS_DTT_2 0x80 /* I2C Digital therm. #2 */ +#define VPD_HAS_1000_UP_LASER 0x100 /* GMM - 1000Mbit Uplink */ +#define VPD_HAS_70KM_UP_LASER 0x200 /* CMM - 70KM Uplink laser */ +#define VPD_HAS_2_UPLINKS 0x400 /* CMM - 2 uplink lasers */ +#define VPD_HAS_FPGA 0x800 /* Has 1 or more FPGAs */ +#define VPD_HAS_DFA 0x1000 /* CLM - Has 2 Fiber Inter. */ +#define VPD_HAS_GAL_SWITCH 0x2000 /* GMM - Has a Gal switch */ +#define VPD_HAS_POTS_LINES 0x4000 /* GMM - Has POTS lines */ +#define VPD_HAS_DS1_CHANNELS 0x8000 /* GMM - Has DS1 channels */ +#define VPD_HAS_CABLE_RETURN 0x10000 /* GBM/GBR - Cable ret. path */ + +#define VPD_EEPROM_SIZE (256 - SDRAM_SPD_DATA_SIZE) /* Size EEPROM */ + +extern int vpd_get_data(unsigned char dev_addr, VPD *vpd); +extern void vpd_print(VPD *vpdInfo); + +#endif /* _VPD_H_ */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c new file mode 100644 index 0000000..c56c269 --- /dev/null +++ b/board/w7o/w7o.c @@ -0,0 +1,272 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "w7o.h" +#include + +#include "vpd.h" +#include "errors.h" +#include + +unsigned long get_dram_size (void); + +/* + * Macros to transform values + * into environment strings. + */ +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +/* ------------------------------------------------------------------------- */ + +int board_early_init_f (void) +{ +#if defined(CONFIG_W7OLMG) + /* + * Setup GPIO pins - reset devices. + */ + out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ + out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ + out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive + * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive + * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive + * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive + * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive + * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive + */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0, + INT0 highest priority */ + + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + +#elif defined(CONFIG_W7OLMC) + /* + * Setup GPIO pins + */ + out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ + out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */ + out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive + * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive + * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive + * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive + */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0, + INT0 highest priority */ + + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + +#else /* Unknown */ +# error "Unknown W7O board configuration" +#endif + + WATCHDOG_RESET (); /* Reset the watchdog */ + temp_uart_init (); /* init the uart for debug */ + WATCHDOG_RESET (); /* Reset the watchdog */ + test_led (); /* test the LEDs */ + test_sdram (get_dram_size ()); /* test the dram */ + log_stat (ERR_POST1); /* log status,post1 complete */ + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + VPD vpd; + + puts ("Board: "); + + /* VPD data present in I2C EEPROM */ + if (vpd_get_data (CFG_DEF_EEPROM_ADDR, &vpd) == 0) { + /* + * Known board type. + */ + if (vpd.productId[0] && + ((strncmp (vpd.productId, "GMM", 3) == 0) || + (strncmp (vpd.productId, "CMM", 3) == 0))) { + + /* Output board information on startup */ + printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID); + return (0); + } + } + + puts ("### Unknown HW ID - assuming NOTHING\n"); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + return get_dram_size (); +} + +unsigned long get_dram_size (void) +{ + int tmp, i, regs[4]; + int size = 0; + + /* Get bank Size registers */ + mtdcr (memcfga, mem_mb0cf); /* get bank 0 config reg */ + regs[0] = mfdcr (memcfgd); + + mtdcr (memcfga, mem_mb1cf); /* get bank 1 config reg */ + regs[1] = mfdcr (memcfgd); + + mtdcr (memcfga, mem_mb2cf); /* get bank 2 config reg */ + regs[2] = mfdcr (memcfgd); + + mtdcr (memcfga, mem_mb3cf); /* get bank 3 config reg */ + regs[3] = mfdcr (memcfgd); + + /* compute the size, add each bank if enabled */ + for (i = 0; i < 4; i++) { + if (regs[i] & 0x0001) { /* if enabled, */ + tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */ + tmp = 0x400000 << tmp; /* Size bits X 4MB = size */ + size += tmp; + } + } + + return size; +} + +int misc_init_f (void) +{ + return 0; +} + +static void w7o_env_init (VPD * vpd) +{ + /* + * Read VPD + */ + if (vpd_get_data (CFG_DEF_EEPROM_ADDR, vpd) != 0) + return; + + /* + * Known board type. + */ + if (vpd->productId[0] && + ((strncmp (vpd->productId, "GMM", 3) == 0) || + (strncmp (vpd->productId, "CMM", 3) == 0))) { + char buf[30]; + char *eth; + char *serial = getenv ("serial#"); + char *ethaddr = getenv ("ethaddr"); + + /* Set 'serial#' envvar if serial# isn't set */ + if (!serial) { + sprintf (buf, "%s-%ld", vpd->productId, + vpd->serialNum); + setenv ("serial#", buf); + } + + /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */ + eth = (char *)(vpd->ethAddrs[0]); + if (ethaddr + && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) { + /* Now setup ethaddr */ + sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", + eth[0], eth[1], eth[2], eth[3], eth[4], + eth[5]); + setenv ("ethaddr", buf); + } + } +} /* w7o_env_init() */ + + +int misc_init_r (void) +{ + VPD vpd; /* VPD information */ + +#if defined(CONFIG_W7OLMG) + unsigned long greg; /* GPIO Register */ + + greg = in32 (PPC405GP_GPIO0_OR); + + /* + * XXX - Unreset devices - this should be moved into VxWorks driver code + */ + greg |= 0x41800000L; /* SAM, PHY, Galileo */ + + out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */ +#endif /* CONFIG_W7OLMG */ + + /* + * Initialize W7O environment variables + */ + w7o_env_init (&vpd); + + /* + * Initialize the FPGA(s). + */ + if (init_fpga () == 0) + test_fpga ((unsigned short *) CONFIG_FPGAS_BASE); + + /* More POST testing. */ + post2 (); + + /* Done with hardware initialization and POST. */ + log_stat (ERR_POSTOK); + + /* Call silly, fail safe boot init routine */ + init_fsboot (); + + return (0); +} diff --git a/board/w7o/w7o.h b/board/w7o/w7o.h new file mode 100644 index 0000000..d6f50e2 --- /dev/null +++ b/board/w7o/w7o.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _W7O_H_ +#define _W7O_H_ +#include + +/* AMCC 405GP PowerPC GPIO registers */ +#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */ +#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */ +#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */ +#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */ + +/* AMCC 405GP DCRs */ +#define CPC0_CR0 0xb1 /* Chip control register 0 */ + +/* LMG FPGA <=> CPU GPIO signals */ +#define LMG_XCV_INIT 0x10000000L +#define LMG_XCV_PROG 0x04000000L +#define LMG_XCV_DONE 0x00400000L +#define LMG_XCV_CNFG_0 0x08000000L +#define LMG_XCV_IRQ_0 0x0L + +/* LMC FPGA <=> CPU GPIO signals */ +#define LMC_XCV_INIT 0x00800000L +#define LMC_XCV_PROG 0x40000000L +#define LMC_XCV_DONE 0x01000000L +#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */ +#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */ +#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */ +#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */ +#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */ +#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */ + + +/* + * Setup FPGA <=> GPIO mappings + */ +#if defined(CONFIG_W7OLMG) +# define GPIO_XCV_INIT LMG_XCV_INIT +# define GPIO_XCV_PROG LMG_XCV_PROG +# define GPIO_XCV_DONE LMG_XCV_DONE +# define GPIO_XCV_CNFG LMG_XCV_CNFG_0 +# define GPIO_XCV_IRQ LMG_XCV_IRQ_0 +# define GPIO_GPIO_1 0x40000000L +# define GPIO_GPIO_6 0x02000000L +# define GPIO_GPIO_7 0x01000000L +# define GPIO_GPIO_8 0x00800000L +#elif defined(CONFIG_W7OLMC) +# define GPIO_XCV_INIT LMC_XCV_INIT +# define GPIO_XCV_PROG LMC_XCV_PROG +# define GPIO_XCV_DONE LMC_XCV_DONE +# define GPIO_XCV_CNFG LMC_XCV_CNFG_0 +# define GPIO_XCV_IRQ LMC_XCV_IRQ_0 +#else +# error "Unknown W7O board configuration" +#endif + +/* Power On Self Tests */ +extern void post2(void); +extern int test_led(void); +extern int test_sdram(unsigned long size); +extern void test_fpga(unsigned short *daddr); + +/* FGPA */ +extern int init_fpga(void); + +/* Misc */ +extern int temp_uart_init(void); +extern void init_fsboot(void); + +#endif /* _W7O_H_ */ diff --git a/board/w7o/watchdog.c b/board/w7o/watchdog.c new file mode 100644 index 0000000..4bbd94f --- /dev/null +++ b/board/w7o/watchdog.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * W7O board level hardware watchdog. + */ +#include +#include + +#ifdef CONFIG_HW_WATCHDOG +#include + +void hw_watchdog_reset(void) +{ + volatile ushort *hwd = (ushort *)(CFG_W7O_EBC_PB7CR & 0xfff00000); + + /* + * Read the LMG's hwd register and toggle the + * watchdog bit to reset it. On the LMC, just + * reading it is enough, but toggling the bit + * doen't hurt either. + */ + *hwd = *hwd ^ 0x8000; + +} /* hw_watchdog_reset() */ + +#endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/wepep250/Makefile b/board/wepep250/Makefile new file mode 100644 index 0000000..11ad8fb --- /dev/null +++ b/board/wepep250/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := wepep250.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/wepep250/config.mk b/board/wepep250/config.mk new file mode 100644 index 0000000..8701581 --- /dev/null +++ b/board/wepep250/config.mk @@ -0,0 +1,11 @@ +# +# This is config used for compilation of WEP EP250 sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +# + +TEXT_BASE = 0xa1fe0000 +#TEXT_BASE = 0xa1001000 diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c new file mode 100644 index 0000000..2a32290 --- /dev/null +++ b/board/wepep250/flash.c @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This code was inspired by Marius Groeger and Kyle Harris code + * available in other board ports for U-Boot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#include +#include "intel.h" + + +/* + * This code should handle CFI FLASH memory device. This code is very + * minimalistic approach without many essential error handling code as well. + * Because U-Boot actually is missing smart handling of FLASH device, + * we just set flash_id to anything else to FLASH_UNKNOW, so common code + * can call us without any restrictions. + * TODO: Add CFI Query, to be able to determine FLASH device. + * TODO: Add error handling code + * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but + * hopefully may work with other configurations. + */ + +#if ( WEP_FLASH_BUS_WIDTH == 1 ) +# define FLASH_BUS vu_char +# if ( WEP_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# else +# error "With 8bit bus only one chip is allowed" +# endif + + +#elif ( WEP_FLASH_BUS_WIDTH == 2 ) +# define FLASH_BUS vu_short +# if ( WEP_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( WEP_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 8 )| x ) +# else +# error "With 16bit bus only 1 or 2 chip(s) are allowed" +# endif + + +#elif ( WEP_FLASH_BUS_WIDTH == 4 ) +# define FLASH_BUS vu_long +# if ( WEP_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( WEP_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 16 )| x ) +# elif ( WEP_FLASH_INTERLEAVE == 4 ) +# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) +# else +# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" +# endif + +#else +# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" +#endif + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static FLASH_BUS flash_status_reg (void) +{ + + FLASH_BUS *addr = (FLASH_BUS *) 0; + + *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); + + return *addr; +} + +static int flash_ready (ulong timeout) +{ + int ok = 1; + + reset_timer_masked (); + while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != + FLASH_CMD (CFI_INTEL_SR_READY)) { + if (get_timer_masked () > timeout && timeout != 0) { + ok = 0; + break; + } + } + return ok; +} + +#if ( CFG_MAX_FLASH_BANKS != 1 ) +# error "WEP platform has only one flash bank!" +#endif + + +ulong flash_init (void) +{ + int i; + FLASH_BUS address = WEP_FLASH_BASE; + + flash_info[0].size = WEP_FLASH_BANK_SIZE; + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + flash_info[0].flash_id = INTEL_MANUFACT; + memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + + for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { + flash_info[0].start[i] = address; +#ifdef WEP_FLASH_UNLOCK + /* Some devices are hw locked after start. */ + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); + flash_ready (0); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); +#endif + address += WEP_FLASH_SECT_SIZE; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return WEP_FLASH_BANK_SIZE; +} + +void flash_print_info (flash_info_t * info) +{ + int i; + + printf (" Intel vendor\n"); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if (!(i % 5)) { + printf ("\n"); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, non_protected = 0, sector; + int rc = ERR_OK; + + FLASH_BUS *address; + + for (sector = s_first; sector <= s_last; sector++) { + if (!info->protect[sector]) { + non_protected++; + } + } + + if (!non_protected) { + return ERR_PROTECTED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + + /* Start erase on unprotected sectors */ + for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { + if (info->protect[sector]) { + printf ("Protected sector %2d skipping...\n", sector); + continue; + } else { + printf ("Erasing sector %2d ... ", sector); + } + + address = (FLASH_BUS *) (info->start[sector]); + + *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); + *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); + if (flash_ready (CFG_FLASH_ERASE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + printf ("ok.\n"); + } else { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + break; + } + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) +{ + FLASH_BUS *address = (FLASH_BUS *) dest; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*address & data) != data) { + return ERR_NOT_ERASED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + flag = disable_interrupts (); + + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); + *address = data; + + if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + } + + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong read_addr, write_addr; + FLASH_BUS data; + int i, result = ERR_OK; + + + read_addr = addr & ~(sizeof (FLASH_BUS) - 1); + write_addr = read_addr; + if (read_addr != addr) { + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (read_addr < addr || cnt == 0) { + data |= *((uchar *) read_addr) << i * 8; + } else { + data |= (*src++) << i * 8; + cnt--; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + } + for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { + if ((result = write_data (info, write_addr, + *((FLASH_BUS *) src))) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + src += sizeof (FLASH_BUS); + } + if (cnt > 0) { + read_addr = write_addr; + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (cnt > 0) { + data |= (*src++) << i * 8; + cnt--; + } else { + data |= *((uchar *) read_addr) << i * 8; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != 0) { + return result; + } + } + return ERR_OK; +} diff --git a/board/wepep250/intel.h b/board/wepep250/intel.h new file mode 100644 index 0000000..77498b6 --- /dev/null +++ b/board/wepep250/intel.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2002 ETC s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Marcel Telka , 2002. + * + * Documentation: + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + */ + +#ifndef FLASH_INTEL_H +#define FLASH_INTEL_H + +#include + +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ + +#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ + +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ + +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ + +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ + +#define CFI_CHIP_INTEL_28F320J3A 0x0016 +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" +#define CFI_CHIP_INTEL_28F640J3A 0x0017 +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" +#define CFI_CHIP_INTEL_28F128J3A 0x0018 +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" + +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ + +#define CFI_CHIP_INTEL_28F640K3 0x8801 +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" +#define CFI_CHIP_INTEL_28F128K3 0x8802 +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" +#define CFI_CHIP_INTEL_28F256K3 0x8803 +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" +#define CFI_CHIP_INTEL_28F640K18 0x8805 +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" +#define CFI_CHIP_INTEL_28F128K18 0x8806 +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" +#define CFI_CHIP_INTEL_28F256K18 0x8807 +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" + +#endif /* FLASH_INTEL_H */ diff --git a/board/wepep250/lowlevel_init.S b/board/wepep250/lowlevel_init.S new file mode 100644 index 0000000..b172cea --- /dev/null +++ b/board/wepep250/lowlevel_init.S @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2001, 2002 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + * 02111-1307, USA. + * + * Written by Marcel Telka , 2001, 2002. + * Changes for U-Boot Peter Figuli , 2003. + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + * Documentation: + * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors + * Developer's Manual", February 2002, Order Number: 278522-001 + * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P", + * Revision 1.0, February 2002 + * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)", + * Revision 1.0, February 2002 + * +*/ + +#include +#include +#include + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + +/* setup memory - see 6.12 in [1] + * Step 1 - wait 200 us + */ + mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */ +1: subs r0, r0, #1 + bne 1b +/* TODO: complete step 1 for Synchronous Static memory*/ + + ldr r0, =0x48000000 /* MC_BASE */ + + +/* step 1.a - setup MSCx + */ + ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */ + str r1, [r0, #0x8] /* MSC0_OFFSET */ + +/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI + * see AUTO REFRESH chapter in section D. in [2] and in [3] + * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633 + * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633 + * TODO: complete for Synchronous Static memory + */ + ldr r1, [r0, #4] /* MDREFR_OFFSET */ + ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */ + bic r1, r1, r2 +#if defined( WEP_SDRAM_K4S281633 ) + orr r1, r1, #48 /* MDREFR_DRI(48) */ +#elif defined( WEP_SDRAM_K4S561633 ) + orr r1, r1, #24 /* MDREFR_DRI(24) */ +#else +#error SDRAM chip is not defined +#endif + + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 2 - only for Synchronous Static memory (TODO) + * + * Step 3 - same as step 4 + * + * Step 4 + * + * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2 + */ + orr r1, r1, #0x00010000 /* MDREFR_K1RUN */ + bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */ + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 4.b - clear MDREFR:SLFRSH */ + bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */ + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 4.c - set MDREFR:E1PIN */ + orr r1, r1, #0x00008000 /* MDREFR_E1PIN */ + str r1, [r0, #4] /* MDREFR_OFFSET */ + +/* Step 4.d - automatically done + * + * Steps 4.e and 4.f - configure SDRAM + */ +#if defined( WEP_SDRAM_K4S281633 ) + ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */ +#elif defined( WEP_SDRAM_K4S561633 ) + ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */ +#else +#error SDRAM chip is not defined +#endif + str r1, [r0, #0] /* MDCNFG_OFFSET */ + +/* Step 5 - wait at least 200 us for SDRAM + * see section B. in [2] + */ + mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */ +1: subs r2, r2, #1 + bne 1b + +/* Step 6 - after reset dcache is disabled, so automatically done + * + * Step 7 - eight refresh cycles + */ + mov r2, #0xA0000000 + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + ldr r3, [r2] + +/* Step 8 - we don't need dcache now + * + * Step 9 - enable SDRAM partition 0 + */ + orr r1, r1, #1 /* MDCNFG_DE0 */ + str r1, [r0, #0] /* MDCNFG_OFFSET */ + +/* Step 10 - write MDMRS */ + mov r1, #0 + str r1, [r0, #0x40] /* MDMRS_OFFSET */ + +/* Step 11 - optional (TODO) */ + + mov pc,r10 diff --git a/board/wepep250/u-boot.lds b/board/wepep250/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/wepep250/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c new file mode 100644 index 0000000..56cb855 --- /dev/null +++ b/board/wepep250/wepep250.c @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#include +#include + +int board_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250; + gd->bd->bi_boot_params = 0xa0000000; +/* + * Setup GPIO stuff to get serial working + */ +#if defined( CONFIG_FFUART ) + GPDR1 = 0x80; + GAFR1_L = 0x8010; +#elif defined( CONFIG_BTUART ) + GPDR1 = 0x800; + GAFR1_L = 0x900000; +#endif + PSSR = 0x20; + + return 0; +} + +int dram_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + +#if ( CONFIG_NR_DRAM_BANKS > 0 ) + gd->bd->bi_dram[0].start = WEP_SDRAM_1; + gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 1 ) + gd->bd->bi_dram[1].start = WEP_SDRAM_2; + gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 2 ) + gd->bd->bi_dram[2].start = WEP_SDRAM_3; + gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 3 ) + gd->bd->bi_dram[3].start = WEP_SDRAM_4; + gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE; +#endif + + return 0; +} diff --git a/board/westel/amx860/Makefile b/board/westel/amx860/Makefile new file mode 100644 index 0000000..7a2014d --- /dev/null +++ b/board/westel/amx860/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c new file mode 100644 index 0000000..8826667 --- /dev/null +++ b/board/westel/amx860/amx860.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint edo_60ns[] = +{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04, + 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_, + 0x8fffec24, 0x0ffbec04, 0x08f3ec04, 0x07f3ec08, + 0x08f3ec04, 0x07f3ec48, 0x08f3ec04, 0x07f3ec48, + 0x08f3ec04, 0x07f3ec48, 0x1ff7ec47, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, + 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, + 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + puts ("Board: AMX860\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */ + + upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint)); + +#ifndef CONFIG_AMX_RAM_EXT + memctl->memc_mptpr = 0x0400; /* divide by 16 */ +#else + memctl->memc_mptpr = 0x0200; +#endif + + memctl->memc_mamr = 0x30a21114; + memctl->memc_or2 = 0xffc00800; +#ifndef CONFIG_AMX_RAM_EXT + memctl->memc_br2 = 0x81; + + return (4 << 20); +#else + memctl->memc_or1 = 0xff000800; + memctl->memc_br1 = 0x00000081; + memctl->memc_br2 = 0x01000081; + + return (20 << 20); +#endif +} diff --git a/board/westel/amx860/config.mk b/board/westel/amx860/config.mk new file mode 100644 index 0000000..d0ee4a2 --- /dev/null +++ b/board/westel/amx860/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +#TEXT_BASE = 0xFE000000 +TEXT_BASE = 0x40000000 +OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data diff --git a/board/westel/amx860/flash.c b/board/westel/amx860/flash.c new file mode 100644 index 0000000..12a1335 --- /dev/null +++ b/board/westel/amx860/flash.c @@ -0,0 +1,637 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } +#else + size_b1 = 0; +#endif /* FLASH_BASE1_PRELIM */ + + DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); + + DEBUGF ("## Before remap: " + "BR0: 0x%08x OR0: 0x%08x " + "BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0, + memctl->memc_br1, memctl->memc_or1); + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size_b0; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + + if (size_b1) { + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK); + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V; + + DEBUGF("## BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + + flash_info[1].size = size_b1; + + flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + +# if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +# endif + +# ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[1]); +#endif + } else { +#ifndef CONFIG_AMX_RAM_EXT + memctl->memc_br1 = 0; /* invalidate bank */ + memctl->memc_or1 = 0; /* invalidate bank */ +#endif + + DEBUGF("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + flash_info[1].size = 0; + } + + DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { + /* set sector offsets for uniform sector type */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00040000); + } + } else if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + DEBUGF("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + DEBUGF("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value) { + case AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds new file mode 100644 index 0000000..cdf550f --- /dev/null +++ b/board/westel/amx860/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug new file mode 100644 index 0000000..87f228b --- /dev/null +++ b/board/westel/amx860/u-boot.lds.debug @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile new file mode 100644 index 0000000..7c5f0cd --- /dev/null +++ b/board/xaeniax/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := xaeniax.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/xaeniax/config.mk b/board/xaeniax/config.mk new file mode 100644 index 0000000..45079a0 --- /dev/null +++ b/board/xaeniax/config.mk @@ -0,0 +1,2 @@ +TEXT_BASE = 0xa3FB0000 +#TEXT_BASE = 0 diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c new file mode 100644 index 0000000..9874a14 --- /dev/null +++ b/board/xaeniax/flash.c @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0] ); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S new file mode 100644 index 0000000..fe3e712 --- /dev/null +++ b/board/xaeniax/lowlevel_init.S @@ -0,0 +1,424 @@ + /* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0,=GPSR0 + ldr r1,=CFG_GPSR0_VAL + str r1,[r0] + + ldr r0,=GPSR1 + ldr r1,=CFG_GPSR1_VAL + str r1,[r0] + + ldr r0,=GPSR2 + ldr r1,=CFG_GPSR2_VAL + str r1,[r0] + + ldr r0,=GPCR0 + ldr r1,=CFG_GPCR0_VAL + str r1,[r0] + + ldr r0,=GPCR1 + ldr r1,=CFG_GPCR1_VAL + str r1,[r0] + + ldr r0,=GPCR2 + ldr r1,=CFG_GPCR2_VAL + str r1,[r0] + + ldr r0,=GPDR0 + ldr r1,=CFG_GPDR0_VAL + str r1,[r0] + + ldr r0,=GPDR1 + ldr r1,=CFG_GPDR1_VAL + str r1,[r0] + + ldr r0,=GPDR2 + ldr r1,=CFG_GPDR2_VAL + str r1,[r0] + + ldr r0,=GAFR0_L + ldr r1,=CFG_GAFR0_L_VAL + str r1,[r0] + + ldr r0,=GAFR0_U + ldr r1,=CFG_GAFR0_U_VAL + str r1,[r0] + + ldr r0,=GAFR1_L + ldr r1,=CFG_GAFR1_L_VAL + str r1,[r0] + + ldr r0,=GAFR1_U + ldr r1,=CFG_GAFR1_U_VAL + str r1,[r0] + + ldr r0,=GAFR2_L + ldr r1,=CFG_GAFR2_L_VAL + str r1,[r0] + + ldr r0,=GAFR2_U + ldr r1,=CFG_GAFR2_U_VAL + str r1,[r0] + + ldr r0,=PSSR /* enable GPIO pins */ + ldr r1,=CFG_PSSR_VAL + str r1,[r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1,=MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2,=CFG_MSC0_VAL + str r2,[r1, #MSC0_OFFSET] + ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */ + + /* MSC1: nCS(2,3) */ + ldr r2,=CFG_MSC1_VAL + str r2,[r1, #MSC1_OFFSET] + ldr r2,[r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2,=CFG_MSC2_VAL + str r2,[r1, #MSC2_OFFSET] + ldr r2,[r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2,=CFG_MECR_VAL + str r2,[r1, #MECR_OFFSET] + ldr r2,[r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2,=CFG_MCMEM0_VAL + str r2,[r1, #MCMEM0_OFFSET] + ldr r2,[r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2,=CFG_MCMEM1_VAL + str r2,[r1, #MCMEM1_OFFSET] + ldr r2,[r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2,=CFG_MCATT0_VAL + str r2,[r1, #MCATT0_OFFSET] + ldr r2,[r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2,=CFG_MCATT1_VAL + str r2,[r1, #MCATT1_OFFSET] + ldr r2,[r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2,=CFG_MCIO0_VAL + str r2,[r1, #MCIO0_OFFSET] + ldr r2,[r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2,=CFG_MCIO1_VAL + str r2,[r1, #MCIO1_OFFSET] + ldr r2,[r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + @ get the mdrefr settings + ldr r4,=CFG_MDREFR_VAL + + @ write back mdrefr + str r4,[r1, #MDREFR_OFFSET] + ldr r4,[r1, #MDREFR_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + @ set K1RUN for bank 0 + @ + orr r4, r4, #MDREFR_K1RUN + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + @ deassert SLFRSH + @ + bic r4, r4, #MDREFR_SLFRSH + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + @ assert E1PIN + @ if E0PIN is also used: #(MDREFR_E1PIN|MDREFR_E0PIN) + orr r4, r4, #(MDREFR_E1PIN) + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + nop + nop + + /* Step 4d: */ + /* fetch platform value of mdcnfg */ + @ + ldr r2, =CFG_MDCNFG_VAL + + @ disable all sdram banks + @ + bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) + bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) + + @ program banks 0/1 for bus width + @ + bic r2, r2, #MDCNFG_DWID0 @0=32-bit + + @ write initial value of mdcnfg, w/o enabling sdram banks + @ + str r2, [r1, #MDCNFG_OFFSET] + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* get memory controller base address */ + ldr r1, =MEMC_BASE + + @fetch current mdcnfg value + @ + ldr r3, [r1, #MDCNFG_OFFSET] + + @enable sdram bank 0 if installed (must do for any populated bank) + @ + orr r3, r3, #MDCNFG_DE0 + + @write back mdcnfg, enabling the sdram bank(s) + @ + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + + /* We are finished with Intel's memory controller initialisation */ + + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r1, =CFG_ICMR_VAL /* mask all interrupts at the controller */ + ldr r2, =ICMR + str r1, [r2] + + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + /* (hard-coding at 398.12MHz for now). */ + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + + /* default value */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + @ Turn on needed clocks + @ +test: + ldr r1, =CKEN + ldr r2, =CFG_CKEN_VAL + str r2, [r1] + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size ?*/ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* FIXME */ + +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/xaeniax/u-boot.lds b/board/xaeniax/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/xaeniax/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c new file mode 100644 index 0000000..26fb312 --- /dev/null +++ b/board/xaeniax/xaeniax.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2004 + * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of xaeniax */ + gd->bd->bi_arch_number = 585; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + /* gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/ + /* gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/ + /* gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */ + /* gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */ + /* gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */ + /* gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */ + + return 0; +} diff --git a/board/xilinx/common/xbasic_types.c b/board/xilinx/common/xbasic_types.c new file mode 100644 index 0000000..c3a171a --- /dev/null +++ b/board/xilinx/common/xbasic_types.c @@ -0,0 +1,165 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* + * +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xbasic_types.c +* +* This file contains basic functions for Xilinx software IP. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/** + * This variable allows testing to be done easier with asserts. An assert + * sets this variable such that a driver can evaluate this variable + * to determine if an assert occurred. + */ +unsigned int XAssertStatus; + +/** + * This variable allows the assert functionality to be changed for testing + * such that it does not wait infinitely. Use the debugger to disable the + * waiting during testing of asserts. + */ +u32 XWaitInAssert = TRUE; + +/* The callback function to be invoked when an assert is taken */ +static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL; + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* Implements assert. Currently, it calls a user-defined callback function +* if one has been set. Then, it potentially enters an infinite loop depending +* on the value of the XWaitInAssert variable. +* +* @param File is the name of the filename of the source +* @param Line is the linenumber within File +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void +XAssert(char *File, int Line) +{ + /* if the callback has been set then invoke it */ + if (XAssertCallbackRoutine != NULL) { + (*XAssertCallbackRoutine) (File, Line); + } + + /* if specified, wait indefinitely such that the assert will show up + * in testing + */ + while (XWaitInAssert) { + } +} + +/*****************************************************************************/ +/** +* +* Sets up a callback function to be invoked when an assert occurs. If there +* was already a callback installed, then it is replaced. +* +* @param Routine is the callback to be invoked when an assert is taken +* +* @return +* +* None. +* +* @note +* +* This function has no effect if NDEBUG is set +* +******************************************************************************/ +void +XAssertSetCallback(XAssertCallback Routine) +{ + XAssertCallbackRoutine = Routine; +} + +/*****************************************************************************/ +/** +* +* Null handler function. This follows the XInterruptHandler signature for +* interrupt handlers. It can be used to assign a null handler (a stub) to an +* interrupt controller vector table. +* +* @param NullParameter is an arbitrary void pointer and not used. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void +XNullHandler(void *NullParameter) +{ +} diff --git a/board/xilinx/common/xbasic_types.h b/board/xilinx/common/xbasic_types.h new file mode 100644 index 0000000..ef0b7c2 --- /dev/null +++ b/board/xilinx/common/xbasic_types.h @@ -0,0 +1,283 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xbasic_types.h +* +* This file contains basic types for Xilinx software IP. These types do not +* follow the standard naming convention with respect to using the component +* name in front of each name because they are considered to be primitives. +* +* @note +* +* This file contains items which are architecture dependent. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rmm  12/14/01 First release
+*	rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
+*		      compiler warnings
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+*
+* +******************************************************************************/ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef NULL +#define NULL 0 +#endif +/** Null */ + +#define XCOMPONENT_IS_READY 0x11111111 /* component has been initialized */ +#define XCOMPONENT_IS_STARTED 0x22222222 /* component has been started */ + +/* the following constants and declarations are for unit test purposes and are + * designed to be used in test applications. + */ +#define XTEST_PASSED 0 +#define XTEST_FAILED 1 + +#define XASSERT_NONE 0 +#define XASSERT_OCCURRED 1 + +extern unsigned int XAssertStatus; +extern void XAssert(char *, int); + +/**************************** Type Definitions *******************************/ + +/** @name Primitive types + * These primitive types are created for transportability. + * They are dependent upon the target architecture. + * @{ + */ +#include + +typedef struct { + u32 Upper; + u32 Lower; +} Xuint64; + +/*@}*/ + +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber); + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return +* +* The upper 32 bits of the 64 bit word. +* +* @note +* +* None. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return +* +* The lower 32 bits of the 64 bit word. +* +* @note +* +* None. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do not return anything +* (void). This in conjunction with the XWaitInAssert boolean can be used to +* accomodate tests so that asserts which fail allow execution to continue. +* +* @param expression is the expression to evaluate. If it evaluates to false, +* the assert occurs. +* +* @return +* +* Returns void unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_VOID(expression) \ +{ \ + if (expression) { \ + XAssertStatus = XASSERT_NONE; \ + } else { \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do return a value. This in +* conjunction with the XWaitInAssert boolean can be used to accomodate tests so +* that asserts which fail allow execution to continue. +* +* @param expression is the expression to evaluate. If it evaluates to false, +* the assert occurs. +* +* @return +* +* Returns 0 unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_NONVOID(expression) \ +{ \ + if (expression) { \ + XAssertStatus = XASSERT_NONE; \ + } else { \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do not +* return anything (void). Use for instances where an assert should always +* occur. +* +* @return +* +* Returns void unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_VOID_ALWAYS() \ +{ \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do return +* a value. Use for instances where an assert should always occur. +* +* @return +* +* Returns void unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_NONVOID_ALWAYS() \ +{ \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return 0; \ +} + +#else + +#define XASSERT_VOID(expression) +#define XASSERT_VOID_ALWAYS() +#define XASSERT_NONVOID(expression) +#define XASSERT_NONVOID_ALWAYS() +#endif + +/************************** Function Prototypes ******************************/ + +void XAssertSetCallback(XAssertCallback Routine); +void XNullHandler(void *NullParameter); + +#endif /* end of protection macro */ diff --git a/board/xilinx/common/xbuf_descriptor.h b/board/xilinx/common/xbuf_descriptor.h new file mode 100644 index 0000000..fdd51d5 --- /dev/null +++ b/board/xilinx/common/xbuf_descriptor.h @@ -0,0 +1,252 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +* FILENAME: +* +* xbuf_descriptor.h +* +* DESCRIPTION: +* +* This file contains the interface for the XBufDescriptor component. +* The XBufDescriptor component is a passive component that only maps over +* a buffer descriptor data structure shared by the scatter gather DMA hardware +* and software. The component's primary purpose is to provide encapsulation of +* the buffer descriptor processing. See the source file xbuf_descriptor.c for +* details. +* +* NOTES: +* +* Most of the functions of this component are implemented as macros in order +* to optimize the processing. The names are not all uppercase such that they +* can be switched between macros and functions easily. +* +******************************************************************************/ + +#ifndef XBUF_DESCRIPTOR_H /* prevent circular inclusions */ +#define XBUF_DESCRIPTOR_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xdma_channel_i.h" + +/************************** Constant Definitions *****************************/ + +/* The following constants allow access to all fields of a buffer descriptor + * and are necessary at this level of visibility to allow macros to access + * and modify the fields of a buffer descriptor. It is not expected that the + * user of a buffer descriptor would need to use these constants. + */ + +#define XBD_DEVICE_STATUS_OFFSET 0 +#define XBD_CONTROL_OFFSET 1 +#define XBD_SOURCE_OFFSET 2 +#define XBD_DESTINATION_OFFSET 3 +#define XBD_LENGTH_OFFSET 4 +#define XBD_STATUS_OFFSET 5 +#define XBD_NEXT_PTR_OFFSET 6 +#define XBD_ID_OFFSET 7 +#define XBD_FLAGS_OFFSET 8 +#define XBD_RQSTED_LENGTH_OFFSET 9 + +#define XBD_SIZE_IN_WORDS 10 + +/* + * The following constants define the bits of the flags field of a buffer + * descriptor + */ + +#define XBD_FLAGS_LOCKED_MASK 1UL + +/**************************** Type Definitions *******************************/ + +typedef u32 XBufDescriptor[XBD_SIZE_IN_WORDS]; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/* each of the following macros are named the same as functions rather than all + * upper case in order to allow either the macros or the functions to be + * used, see the source file xbuf_descriptor.c for documentation + */ + +#define XBufDescriptor_Initialize(InstancePtr) \ +{ \ + (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = 0); \ + (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = 0); \ + (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = 0); \ + (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = 0); \ + (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = 0); \ + (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = 0); \ + (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = 0); \ + (*((u32 *)InstancePtr + XBD_ID_OFFSET) = 0); \ + (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = 0); \ + (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = 0); \ +} + +#define XBufDescriptor_GetControl(InstancePtr) \ + (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET)) + +#define XBufDescriptor_SetControl(InstancePtr, Control) \ + (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = (u32)Control) + +#define XBufDescriptor_IsLastControl(InstancePtr) \ + (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) & \ + XDC_CONTROL_LAST_BD_MASK) + +#define XBufDescriptor_SetLast(InstancePtr) \ + (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) |= XDC_CONTROL_LAST_BD_MASK) + +#define XBufDescriptor_GetSrcAddress(InstancePtr) \ + ((u32 *)(*((u32 *)InstancePtr + XBD_SOURCE_OFFSET))) + +#define XBufDescriptor_SetSrcAddress(InstancePtr, Source) \ + (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = (u32)Source) + +#define XBufDescriptor_GetDestAddress(InstancePtr) \ + ((u32 *)(*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET))) + +#define XBufDescriptor_SetDestAddress(InstancePtr, Destination) \ + (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = (u32)Destination) + +#define XBufDescriptor_GetLength(InstancePtr) \ + (u32)(*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) - \ + *((u32 *)InstancePtr + XBD_LENGTH_OFFSET)) + +#define XBufDescriptor_SetLength(InstancePtr, Length) \ +{ \ + (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = (u32)(Length)); \ + (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = (u32)(Length));\ +} + +#define XBufDescriptor_GetStatus(InstancePtr) \ + (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET)) + +#define XBufDescriptor_SetStatus(InstancePtr, Status) \ + (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = (u32)Status) + +#define XBufDescriptor_IsLastStatus(InstancePtr) \ + (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET) & \ + XDC_STATUS_LAST_BD_MASK) + +#define XBufDescriptor_GetDeviceStatus(InstancePtr) \ + ((u32)(*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET))) + +#define XBufDescriptor_SetDeviceStatus(InstancePtr, Status) \ + (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = (u32)Status) + +#define XBufDescriptor_GetNextPtr(InstancePtr) \ + (XBufDescriptor *)(*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET)) + +#define XBufDescriptor_SetNextPtr(InstancePtr, NextPtr) \ + (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = (u32)NextPtr) + +#define XBufDescriptor_GetId(InstancePtr) \ + (u32)(*((u32 *)InstancePtr + XBD_ID_OFFSET)) + +#define XBufDescriptor_SetId(InstancePtr, Id) \ + (*((u32 *)InstancePtr + XBD_ID_OFFSET) = (u32)Id) + +#define XBufDescriptor_GetFlags(InstancePtr) \ + (u32)(*((u32 *)InstancePtr + XBD_FLAGS_OFFSET)) + +#define XBufDescriptor_SetFlags(InstancePtr, Flags) \ + (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = (u32)Flags) + +#define XBufDescriptor_Lock(InstancePtr) \ + (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) |= XBD_FLAGS_LOCKED_MASK) + +#define XBufDescriptor_Unlock(InstancePtr) \ + (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) &= ~XBD_FLAGS_LOCKED_MASK) + +#define XBufDescriptor_IsLocked(InstancePtr) \ + (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) & XBD_FLAGS_LOCKED_MASK) + +/************************** Function Prototypes ******************************/ + +/* The following prototypes are provided to allow each of the functions to + * be implemented as a function rather than a macro, and to provide the + * syntax to allow users to understand how to call the macros, they are + * commented out to prevent linker errors + * + +u32 XBufDescriptor_Initialize(XBufDescriptor* InstancePtr); + +u32 XBufDescriptor_GetControl(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetControl(XBufDescriptor* InstancePtr, u32 Control); + +u32 XBufDescriptor_IsLastControl(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetLast(XBufDescriptor* InstancePtr); + +u32 XBufDescriptor_GetLength(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetLength(XBufDescriptor* InstancePtr, u32 Length); + +u32 XBufDescriptor_GetStatus(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetStatus(XBufDescriptor* InstancePtr, u32 Status); +u32 XBufDescriptor_IsLastStatus(XBufDescriptor* InstancePtr); + +u32 XBufDescriptor_GetDeviceStatus(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetDeviceStatus(XBufDescriptor* InstancePtr, + u32 Status); + +u32 XBufDescriptor_GetSrcAddress(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetSrcAddress(XBufDescriptor* InstancePtr, + u32 SourceAddress); + +u32 XBufDescriptor_GetDestAddress(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetDestAddress(XBufDescriptor* InstancePtr, + u32 DestinationAddress); + +XBufDescriptor* XBufDescriptor_GetNextPtr(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetNextPtr(XBufDescriptor* InstancePtr, + XBufDescriptor* NextPtr); + +u32 XBufDescriptor_GetId(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetId(XBufDescriptor* InstancePtr, u32 Id); + +u32 XBufDescriptor_GetFlags(XBufDescriptor* InstancePtr); +void XBufDescriptor_SetFlags(XBufDescriptor* InstancePtr, u32 Flags); + +void XBufDescriptor_Lock(XBufDescriptor* InstancePtr); +void XBufDescriptor_Unlock(XBufDescriptor* InstancePtr); +u32 XBufDescriptor_IsLocked(XBufDescriptor* InstancePtr); + +void XBufDescriptor_Copy(XBufDescriptor* InstancePtr, + XBufDescriptor* DestinationPtr); + +*/ + +#endif /* end of protection macro */ diff --git a/board/xilinx/common/xdma_channel.c b/board/xilinx/common/xdma_channel.c new file mode 100644 index 0000000..3d5fc75 --- /dev/null +++ b/board/xilinx/common/xdma_channel.c @@ -0,0 +1,738 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +* FILENAME: +* +* xdma_channel.c +* +* DESCRIPTION: +* +* This file contains the DMA channel component. This component supports +* a distributed DMA design in which each device can have it's own dedicated +* DMA channel, as opposed to a centralized DMA design. This component +* performs processing for DMA on all devices. +* +* See xdma_channel.h for more information about this component. +* +* NOTES: +* +* None. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdma_channel.h" +#include "xbasic_types.h" +#include "xio.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_Initialize +* +* DESCRIPTION: +* +* This function initializes a DMA channel. This function must be called +* prior to using a DMA channel. Initialization of a channel includes setting +* up the registers base address, and resetting the channel such that it's in a +* known state. Interrupts for the channel are disabled when the channel is +* reset. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* BaseAddress contains the base address of the registers for the DMA channel. +* +* RETURN VALUE: +* +* XST_SUCCESS indicating initialization was successful. +* +* NOTES: +* +* None. +* +******************************************************************************/ +XStatus +XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress) +{ + /* assert to verify input arguments, don't assert base address */ + + XASSERT_NONVOID(InstancePtr != NULL); + + /* setup the base address of the registers for the DMA channel such + * that register accesses can be done + */ + InstancePtr->RegBaseAddress = BaseAddress; + + /* initialize the scatter gather list such that it indicates it has not + * been created yet and the DMA channel is ready to use (initialized) + */ + InstancePtr->GetPtr = NULL; + InstancePtr->PutPtr = NULL; + InstancePtr->CommitPtr = NULL; + InstancePtr->LastPtr = NULL; + + InstancePtr->TotalDescriptorCount = 0; + InstancePtr->ActiveDescriptorCount = 0; + InstancePtr->IsReady = XCOMPONENT_IS_READY; + + /* initialize the version of the component + */ + XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a"); + + /* reset the DMA channel such that it's in a known state and ready + * and indicate the initialization occured with no errors, note that + * the is ready variable must be set before this call or reset will assert + */ + XDmaChannel_Reset(InstancePtr); + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_IsReady +* +* DESCRIPTION: +* +* This function determines if a DMA channel component has been successfully +* initialized such that it's ready to use. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* RETURN VALUE: +* +* TRUE if the DMA channel component is ready, FALSE otherwise. +* +* NOTES: +* +* None. +* +******************************************************************************/ +u32 +XDmaChannel_IsReady(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments used by the base component */ + + XASSERT_NONVOID(InstancePtr != NULL); + + return InstancePtr->IsReady == XCOMPONENT_IS_READY; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_GetVersion +* +* DESCRIPTION: +* +* This function gets the software version for the specified DMA channel +* component. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* RETURN VALUE: +* +* A pointer to the software version of the specified DMA channel. +* +* NOTES: +* +* None. +* +******************************************************************************/ +XVersion * +XDmaChannel_GetVersion(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* return a pointer to the version of the DMA channel */ + + return &InstancePtr->Version; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_SelfTest +* +* DESCRIPTION: +* +* This function performs a self test on the specified DMA channel. This self +* test is destructive as the DMA channel is reset and a register default is +* verified. +* +* ARGUMENTS: +* +* InstancePtr is a pointer to the DMA channel to be operated on. +* +* RETURN VALUE: +* +* XST_SUCCESS is returned if the self test is successful, or one of the +* following errors. +* +* XST_DMA_RESET_REGISTER_ERROR Indicates the control register value +* after a reset was not correct +* +* NOTES: +* +* This test does not performs a DMA transfer to test the channel because the +* DMA hardware will not currently allow a non-local memory transfer to non-local +* memory (memory copy), but only allows a non-local memory to or from the device +* memory (typically a FIFO). +* +******************************************************************************/ + +#define XDC_CONTROL_REG_RESET_MASK 0x98000000UL /* control reg reset value */ + +XStatus +XDmaChannel_SelfTest(XDmaChannel * InstancePtr) +{ + u32 ControlReg; + + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* reset the DMA channel such that it's in a known state before the test + * it resets to no interrupts enabled, the desired state for the test + */ + XDmaChannel_Reset(InstancePtr); + + /* this should be the first test to help prevent a lock up with the polling + * loop that occurs later in the test, check the reset value of the DMA + * control register to make sure it's correct, return with an error if not + */ + ControlReg = XDmaChannel_GetControl(InstancePtr); + if (ControlReg != XDC_CONTROL_REG_RESET_MASK) { + return XST_DMA_RESET_REGISTER_ERROR; + } + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_Reset +* +* DESCRIPTION: +* +* This function resets the DMA channel. This is a destructive operation such +* that it should not be done while a channel is being used. If the DMA channel +* is transferring data into other blocks, such as a FIFO, it may be necessary +* to reset other blocks. This function does not modify the contents of a +* scatter gather list for a DMA channel such that the user is responsible for +* getting buffer descriptors from the list if necessary. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +void +XDmaChannel_Reset(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* reset the DMA channel such that it's in a known state, the reset + * register is self clearing such that it only has to be set + */ + XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET, + XDC_RESET_MASK); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_GetControl +* +* DESCRIPTION: +* +* This function gets the control register contents of the DMA channel. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* RETURN VALUE: +* +* The control register contents of the DMA channel. One or more of the +* following values may be contained the register. Each of the values are +* unique bit masks. +* +* XDC_DMACR_SOURCE_INCR_MASK Increment the source address +* XDC_DMACR_DEST_INCR_MASK Increment the destination address +* XDC_DMACR_SOURCE_LOCAL_MASK Local source address +* XDC_DMACR_DEST_LOCAL_MASK Local destination address +* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable +* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt +* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet +* +* NOTES: +* +* None. +* +******************************************************************************/ +u32 +XDmaChannel_GetControl(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* return the contents of the DMA control register */ + + return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_SetControl +* +* DESCRIPTION: +* +* This function sets the control register of the specified DMA channel. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* Control contains the value to be written to the control register of the DMA +* channel. One or more of the following values may be contained the register. +* Each of the values are unique bit masks such that they may be ORed together +* to enable multiple bits or inverted and ANDed to disable multiple bits. +* +* XDC_DMACR_SOURCE_INCR_MASK Increment the source address +* XDC_DMACR_DEST_INCR_MASK Increment the destination address +* XDC_DMACR_SOURCE_LOCAL_MASK Local source address +* XDC_DMACR_DEST_LOCAL_MASK Local destination address +* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable +* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt +* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +void +XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control) +{ + /* assert to verify input arguments except the control which can't be + * asserted since all values are valid + */ + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* set the DMA control register to the specified value */ + + XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, Control); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_GetStatus +* +* DESCRIPTION: +* +* This function gets the status register contents of the DMA channel. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* RETURN VALUE: +* +* The status register contents of the DMA channel. One or more of the +* following values may be contained the register. Each of the values are +* unique bit masks. +* +* XDC_DMASR_BUSY_MASK The DMA channel is busy +* XDC_DMASR_BUS_ERROR_MASK A bus error occurred +* XDC_DMASR_BUS_TIMEOUT_MASK A bus timeout occurred +* XDC_DMASR_LAST_BD_MASK The last buffer descriptor of a packet +* +* NOTES: +* +* None. +* +******************************************************************************/ +u32 +XDmaChannel_GetStatus(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* return the contents of the DMA status register */ + + return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_SetIntrStatus +* +* DESCRIPTION: +* +* This function sets the interrupt status register of the specified DMA channel. +* Setting any bit of the interrupt status register will clear the bit to +* indicate the interrupt processing has been completed. The definitions of each +* bit in the register match the definition of the bits in the interrupt enable +* register. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* Status contains the value to be written to the status register of the DMA +* channel. One or more of the following values may be contained the register. +* Each of the values are unique bit masks such that they may be ORed together +* to enable multiple bits or inverted and ANDed to disable multiple bits. +* +* XDC_IXR_DMA_DONE_MASK The dma operation is done +* XDC_IXR_DMA_ERROR_MASK The dma operation had an error +* XDC_IXR_PKT_DONE_MASK A packet is complete +* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached +* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached +* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed +* XDC_IXR_BD_MASK A buffer descriptor is done +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +void +XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status) +{ + /* assert to verify input arguments except the status which can't be + * asserted since all values are valid + */ + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* set the interrupt status register with the specified value such that + * all bits which are set in the register are cleared effectively clearing + * any active interrupts + */ + XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_GetIntrStatus +* +* DESCRIPTION: +* +* This function gets the interrupt status register of the specified DMA channel. +* The interrupt status register indicates which interrupts are active +* for the DMA channel. If an interrupt is active, the status register must be +* set (written) with the bit set for each interrupt which has been processed +* in order to clear the interrupts. The definitions of each bit in the register +* match the definition of the bits in the interrupt enable register. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* RETURN VALUE: +* +* The interrupt status register contents of the specified DMA channel. +* One or more of the following values may be contained the register. +* Each of the values are unique bit masks. +* +* XDC_IXR_DMA_DONE_MASK The dma operation is done +* XDC_IXR_DMA_ERROR_MASK The dma operation had an error +* XDC_IXR_PKT_DONE_MASK A packet is complete +* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached +* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached +* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed +* XDC_IXR_SG_END_MASK Current descriptor was the end of the list +* XDC_IXR_BD_MASK A buffer descriptor is done +* +* NOTES: +* +* None. +* +******************************************************************************/ +u32 +XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* return the contents of the interrupt status register */ + + return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_SetIntrEnable +* +* DESCRIPTION: +* +* This function sets the interrupt enable register of the specified DMA +* channel. The interrupt enable register contains bits which enable +* individual interrupts for the DMA channel. The definitions of each bit +* in the register match the definition of the bits in the interrupt status +* register. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* Enable contains the interrupt enable register contents to be written +* in the DMA channel. One or more of the following values may be contained +* the register. Each of the values are unique bit masks such that they may be +* ORed together to enable multiple bits or inverted and ANDed to disable +* multiple bits. +* +* XDC_IXR_DMA_DONE_MASK The dma operation is done +* XDC_IXR_DMA_ERROR_MASK The dma operation had an error +* XDC_IXR_PKT_DONE_MASK A packet is complete +* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached +* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached +* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed +* XDC_IXR_SG_END_MASK Current descriptor was the end of the list +* XDC_IXR_BD_MASK A buffer descriptor is done +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +void +XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable) +{ + /* assert to verify input arguments except the enable which can't be + * asserted since all values are valid + */ + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* set the interrupt enable register to the specified value */ + + XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_GetIntrEnable +* +* DESCRIPTION: +* +* This function gets the interrupt enable of the DMA channel. The +* interrupt enable contains flags which enable individual interrupts for the +* DMA channel. The definitions of each bit in the register match the definition +* of the bits in the interrupt status register. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* RETURN VALUE: +* +* The interrupt enable of the DMA channel. One or more of the following values +* may be contained the register. Each of the values are unique bit masks. +* +* XDC_IXR_DMA_DONE_MASK The dma operation is done +* XDC_IXR_DMA_ERROR_MASK The dma operation had an error +* XDC_IXR_PKT_DONE_MASK A packet is complete +* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached +* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached +* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed +* XDC_IXR_BD_MASK A buffer descriptor is done +* +* NOTES: +* +* None. +* +******************************************************************************/ +u32 +XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* return the contents of the interrupt enable register */ + + return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_Transfer +* +* DESCRIPTION: +* +* This function starts the DMA channel transferring data from a memory source +* to a memory destination. This function only starts the operation and returns +* before the operation may be complete. If the interrupt is enabled, an +* interrupt will be generated when the operation is complete, otherwise it is +* necessary to poll the channel status to determine when it's complete. It is +* the responsibility of the caller to determine when the operation is complete +* by handling the generated interrupt or polling the status. It is also the +* responsibility of the caller to ensure that the DMA channel is not busy with +* another transfer before calling this function. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. +* +* SourcePtr contains a pointer to the source memory where the data is to +* be tranferred from and must be 32 bit aligned. +* +* DestinationPtr contains a pointer to the destination memory where the data +* is to be transferred and must be 32 bit aligned. +* +* ByteCount contains the number of bytes to transfer during the DMA operation. +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* The DMA h/w will not currently allow a non-local memory transfer to non-local +* memory (memory copy), but only allows a non-local memory to or from the device +* memory (typically a FIFO). +* +* It is the responsibility of the caller to ensure that the cache is +* flushed and invalidated both before and after the DMA operation completes +* if the memory pointed to is cached. The caller must also ensure that the +* pointers contain a physical address rather than a virtual address +* if address translation is being used. +* +******************************************************************************/ +void +XDmaChannel_Transfer(XDmaChannel * InstancePtr, + u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount) +{ + /* assert to verify input arguments and the alignment of any arguments + * which have expected alignments + */ + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(SourcePtr != NULL); + XASSERT_VOID(((u32) SourcePtr & 3) == 0); + XASSERT_VOID(DestinationPtr != NULL); + XASSERT_VOID(((u32) DestinationPtr & 3) == 0); + XASSERT_VOID(ByteCount != 0); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* setup the source and destination address registers for the transfer */ + + XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET, + (u32) SourcePtr); + + XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET, + (u32) DestinationPtr); + + /* start the DMA transfer to copy from the source buffer to the + * destination buffer by writing the length to the length register + */ + XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount); +} diff --git a/board/xilinx/common/xdma_channel.h b/board/xilinx/common/xdma_channel.h new file mode 100644 index 0000000..06976c3 --- /dev/null +++ b/board/xilinx/common/xdma_channel.h @@ -0,0 +1,291 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +* FILENAME: +* +* xdma_channel.h +* +* DESCRIPTION: +* +* This file contains the DMA channel component implementation. This component +* supports a distributed DMA design in which each device can have it's own +* dedicated DMA channel, as opposed to a centralized DMA design. +* A device which uses DMA typically contains two DMA channels, one for +* sending data and the other for receiving data. +* +* This component is designed to be used as a basic building block for +* designing a device driver. It provides registers accesses such that all +* DMA processing can be maintained easier, but the device driver designer +* must still understand all the details of the DMA channel. +* +* The DMA channel allows a CPU to minimize the CPU interaction required to move +* data between a memory and a device. The CPU requests the DMA channel to +* perform a DMA operation and typically continues performing other processing +* until the DMA operation completes. DMA could be considered a primitive form +* of multiprocessing such that caching and address translation can be an issue. +* +* Scatter Gather Operations +* +* The DMA channel may support scatter gather operations. A scatter gather +* operation automates the DMA channel such that multiple buffers can be +* sent or received with minimal software interaction with the hardware. Buffer +* descriptors, contained in the XBufDescriptor component, are used by the +* scatter gather operations of the DMA channel to describe the buffers to be +* processed. +* +* Scatter Gather List Operations +* +* A scatter gather list may be supported by each DMA channel. The scatter +* gather list allows buffer descriptors to be put into the list by a device +* driver which requires scatter gather. The hardware processes the buffer +* descriptors which are contained in the list and modifies the buffer +* descriptors to reflect the status of the DMA operations. The device driver +* is notified by interrupt that specific DMA events occur including scatter +* gather events. The device driver removes the completed buffer descriptors +* from the scatter gather list to evaluate the status of each DMA operation. +* +* The scatter gather list is created and buffer descriptors are inserted into +* the list. Buffer descriptors are never removed from the list after it's +* creation such that a put operation copies from a temporary buffer descriptor +* to a buffer descriptor in the list. Get operations don't copy from the list +* to a temporary, but return a pointer to the buffer descriptor in the list. +* A buffer descriptor in the list may be locked to prevent it from being +* overwritten by a put operation. This allows the device driver to get a +* descriptor from a scatter gather list and prevent it from being overwritten +* until the buffer associated with the buffer descriptor has been processed. +* +* Typical Scatter Gather Processing +* +* The following steps illustrate the typical processing to use the +* scatter gather features of a DMA channel. +* +* 1. Create a scatter gather list for the DMA channel which puts empty buffer +* descriptors into the list. +* 2. Create buffer descriptors which describe the buffers to be filled with +* receive data or the buffers which contain data to be sent. +* 3. Put buffer descriptors into the DMA channel scatter list such that scatter +* gather operations are requested. +* 4. Commit the buffer descriptors in the list such that they are ready to be +* used by the DMA channel hardware. +* 5. Start the scatter gather operations of the DMA channel. +* 6. Process any interrupts which occur as a result of the scatter gather +* operations or poll the DMA channel to determine the status. +* +* Interrupts +* +* Each DMA channel has the ability to generate an interrupt. This component +* does not perform processing for the interrupt as this processing is typically +* tightly coupled with the device which is using the DMA channel. It is the +* responsibility of the caller of DMA functions to manage the interrupt +* including connecting to the interrupt and enabling/disabling the interrupt. +* +* Critical Sections +* +* It is the responsibility of the device driver designer to use critical +* sections as necessary when calling functions of the DMA channel. This +* component does not use critical sections and it does access registers using +* read-modify-write operations. Calls to DMA functions from a main thread +* and from an interrupt context could produce unpredictable behavior such that +* the caller must provide the appropriate critical sections. +* +* Address Translation +* +* All addresses of data structures which are passed to DMA functions must +* be physical (real) addresses as opposed to logical (virtual) addresses. +* +* Caching +* +* The memory which is passed to the function which creates the scatter gather +* list must not be cached such that buffer descriptors are non-cached. This +* is necessary because the buffer descriptors are kept in a ring buffer and +* not directly accessible to the caller of DMA functions. +* +* The caller of DMA functions is responsible for ensuring that any data +* buffers which are passed to the DMA channel are cache-line aligned if +* necessary. +* +* The caller of DMA functions is responsible for ensuring that any data +* buffers which are passed to the DMA channel have been flushed from the cache. +* +* The caller of DMA functions is responsible for ensuring that the cache is +* invalidated prior to using any data buffers which are the result of a DMA +* operation. +* +* Memory Alignment +* +* The addresses of data buffers which are passed to DMA functions must be +* 32 bit word aligned since the DMA hardware performs 32 bit word transfers. +* +* Mutual Exclusion +* +* The functions of the DMA channel are not thread safe such that the caller +* of all DMA functions is responsible for ensuring mutual exclusion for a +* DMA channel. Mutual exclusion across multiple DMA channels is not +* necessary. +* +* NOTES: +* +* Many of the provided functions which are register accessors don't provide +* a lot of error detection. The caller is expected to understand the impact +* of a function call based upon the current state of the DMA channel. This +* is done to minimize the overhead in this component. +* +******************************************************************************/ + +#ifndef XDMA_CHANNEL_H /* prevent circular inclusions */ +#define XDMA_CHANNEL_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xdma_channel_i.h" /* constants shared with buffer descriptor */ +#include "xbasic_types.h" +#include "xstatus.h" +#include "xversion.h" +#include "xbuf_descriptor.h" + +/************************** Constant Definitions *****************************/ + +/* the following constants provide access to the bit fields of the DMA control + * register (DMACR) + */ +#define XDC_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */ +#define XDC_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */ +#define XDC_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */ +#define XDC_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */ +#define XDC_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */ +#define XDC_DMACR_GEN_BD_INTR_MASK 0x04000000UL /* descriptor interrupt */ +#define XDC_DMACR_LAST_BD_MASK XDC_CONTROL_LAST_BD_MASK /* last buffer */ + /* descriptor */ + +/* the following constants provide access to the bit fields of the DMA status + * register (DMASR) + */ +#define XDC_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */ +#define XDC_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */ +#define XDC_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */ +#define XDC_DMASR_LAST_BD_MASK XDC_STATUS_LAST_BD_MASK /* last buffer */ + /* descriptor */ +#define XDC_DMASR_SG_BUSY_MASK 0x08000000UL /* scatter gather is busy */ + +/* the following constants provide access to the bit fields of the interrupt + * status register (ISR) and the interrupt enable register (IER), bit masks + * match for both registers such that they are named IXR + */ +#define XDC_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */ +#define XDC_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */ +#define XDC_IXR_PKT_DONE_MASK 0x4UL /* packet done */ +#define XDC_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */ +#define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */ +#define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable + acknowledge occurred */ +#define XDC_IXR_SG_END_MASK 0x40UL /* last buffer descriptor + disabled scatter gather */ +#define XDC_IXR_BD_MASK 0x80UL /* buffer descriptor done */ + +/**************************** Type Definitions *******************************/ + +/* + * the following structure contains data which is on a per instance basis + * for the XDmaChannel component + */ +typedef struct XDmaChannelTag { + XVersion Version; /* version of the driver */ + u32 RegBaseAddress; /* base address of registers */ + u32 IsReady; /* device is initialized and ready */ + + XBufDescriptor *PutPtr; /* keep track of where to put into list */ + XBufDescriptor *GetPtr; /* keep track of where to get from list */ + XBufDescriptor *CommitPtr; /* keep track of where to commit in list */ + XBufDescriptor *LastPtr; /* keep track of the last put in the list */ + u32 TotalDescriptorCount; /* total # of descriptors in the list */ + u32 ActiveDescriptorCount; /* # of descriptors pointing to buffers + * in the buffer descriptor list */ +} XDmaChannel; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +XStatus XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress); +u32 XDmaChannel_IsReady(XDmaChannel * InstancePtr); +XVersion *XDmaChannel_GetVersion(XDmaChannel * InstancePtr); +XStatus XDmaChannel_SelfTest(XDmaChannel * InstancePtr); +void XDmaChannel_Reset(XDmaChannel * InstancePtr); + +/* Control functions */ + +u32 XDmaChannel_GetControl(XDmaChannel * InstancePtr); +void XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control); + +/* Status functions */ + +u32 XDmaChannel_GetStatus(XDmaChannel * InstancePtr); +void XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status); +u32 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr); +void XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable); +u32 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr); + +/* DMA without scatter gather functions */ + +void XDmaChannel_Transfer(XDmaChannel * InstancePtr, + u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount); + +/* Scatter gather functions */ + +XStatus XDmaChannel_SgStart(XDmaChannel * InstancePtr); +XStatus XDmaChannel_SgStop(XDmaChannel * InstancePtr, + XBufDescriptor ** BufDescriptorPtr); +XStatus XDmaChannel_CreateSgList(XDmaChannel * InstancePtr, + u32 * MemoryPtr, u32 ByteCount); +u32 XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr); + +XStatus XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr, + XBufDescriptor * BufDescriptorPtr); +XStatus XDmaChannel_CommitPuts(XDmaChannel * InstancePtr); +XStatus XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr, + XBufDescriptor ** BufDescriptorPtr); + +/* Packet functions for interrupt collescing */ + +u32 XDmaChannel_GetPktCount(XDmaChannel * InstancePtr); +void XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr); +XStatus XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold); +u8 XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr); +void XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound); +u32 XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr); + +#endif /* end of protection macro */ diff --git a/board/xilinx/common/xdma_channel_i.h b/board/xilinx/common/xdma_channel_i.h new file mode 100644 index 0000000..e9f343b --- /dev/null +++ b/board/xilinx/common/xdma_channel_i.h @@ -0,0 +1,110 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +* FILENAME: +* +* xdma_channel_i.h +* +* DESCRIPTION: +* +* This file contains data which is shared internal data for the DMA channel +* component. It is also shared with the buffer descriptor component which is +* very tightly coupled with the DMA channel component. +* +* NOTES: +* +* The last buffer descriptor constants must be located here to prevent a +* circular dependency between the DMA channel component and the buffer +* descriptor component. +* +******************************************************************************/ + +#ifndef XDMA_CHANNEL_I_H /* prevent circular inclusions */ +#define XDMA_CHANNEL_I_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xstatus.h" +#include "xversion.h" + +/************************** Constant Definitions *****************************/ + +#define XDC_DMA_CHANNEL_V1_00_A "1.00a" + +/* the following constant provides access to the bit fields of the DMA control + * register (DMACR) which must be shared between the DMA channel component + * and the buffer descriptor component + */ +#define XDC_CONTROL_LAST_BD_MASK 0x02000000UL /* last buffer descriptor */ + +/* the following constant provides access to the bit fields of the DMA status + * register (DMASR) which must be shared between the DMA channel component + * and the buffer descriptor component + */ +#define XDC_STATUS_LAST_BD_MASK 0x10000000UL /* last buffer descriptor */ + +/* the following constants provide access to each of the registers of a DMA + * channel + */ +#define XDC_RST_REG_OFFSET 0 /* reset register */ +#define XDC_MI_REG_OFFSET 0 /* module information register */ +#define XDC_DMAC_REG_OFFSET 4 /* DMA control register */ +#define XDC_SA_REG_OFFSET 8 /* source address register */ +#define XDC_DA_REG_OFFSET 12 /* destination address register */ +#define XDC_LEN_REG_OFFSET 16 /* length register */ +#define XDC_DMAS_REG_OFFSET 20 /* DMA status register */ +#define XDC_BDA_REG_OFFSET 24 /* buffer descriptor address register */ +#define XDC_SWCR_REG_OFFSET 28 /* software control register */ +#define XDC_UPC_REG_OFFSET 32 /* unserviced packet count register */ +#define XDC_PCT_REG_OFFSET 36 /* packet count threshold register */ +#define XDC_PWB_REG_OFFSET 40 /* packet wait bound register */ +#define XDC_IS_REG_OFFSET 44 /* interrupt status register */ +#define XDC_IE_REG_OFFSET 48 /* interrupt enable register */ + +/* the following constant is written to the reset register to reset the + * DMA channel + */ +#define XDC_RESET_MASK 0x0000000AUL + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +#endif /* end of protection macro */ diff --git a/board/xilinx/common/xdma_channel_sg.c b/board/xilinx/common/xdma_channel_sg.c new file mode 100644 index 0000000..a8e9462 --- /dev/null +++ b/board/xilinx/common/xdma_channel_sg.c @@ -0,0 +1,1317 @@ +/* $Id: xdma_channel_sg.c,v 1.6 2003/02/03 19:50:33 moleres Exp $ */ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +* FILENAME: +* +* xdma_channel_sg.c +* +* DESCRIPTION: +* +* This file contains the implementation of the XDmaChannel component which is +* related to scatter gather operations. +* +* Scatter Gather Operations +* +* The DMA channel may support scatter gather operations. A scatter gather +* operation automates the DMA channel such that multiple buffers can be +* sent or received with minimal software interaction with the hardware. Buffer +* descriptors, contained in the XBufDescriptor component, are used by the +* scatter gather operations of the DMA channel to describe the buffers to be +* processed. +* +* Scatter Gather List Operations +* +* A scatter gather list may be supported by each DMA channel. The scatter +* gather list allows buffer descriptors to be put into the list by a device +* driver which requires scatter gather. The hardware processes the buffer +* descriptors which are contained in the list and modifies the buffer +* descriptors to reflect the status of the DMA operations. The device driver +* is notified by interrupt that specific DMA events occur including scatter +* gather events. The device driver removes the completed buffer descriptors +* from the scatter gather list to evaluate the status of each DMA operation. +* +* The scatter gather list is created and buffer descriptors are inserted into +* the list. Buffer descriptors are never removed from the list after it's +* creation such that a put operation copies from a temporary buffer descriptor +* to a buffer descriptor in the list. Get operations don't copy from the list +* to a temporary, but return a pointer to the buffer descriptor in the list. +* A buffer descriptor in the list may be locked to prevent it from being +* overwritten by a put operation. This allows the device driver to get a +* descriptor from a scatter gather list and prevent it from being overwritten +* until the buffer associated with the buffer descriptor has been processed. +* +* The get and put functions only operate on the list and are asynchronous from +* the hardware which may be using the list of descriptors. This is important +* because there are no checks in the get and put functions to ensure that the +* hardware has processed the descriptors. This must be handled by the driver +* using the DMA scatter gather channel through the use of the other functions. +* When a scatter gather operation is started, the start function does ensure +* that the descriptor to start has not already been processed by the hardware +* and is not the first of a series of descriptors that have not been committed +* yet. +* +* Descriptors are put into the list but not marked as ready to use by the +* hardware until a commit operation is done. This allows multiple descriptors +* which may contain a single packet of information for a protocol to be +* guaranteed not to cause any underflow conditions during transmission. The +* hardware design only allows descriptors to cause it to stop after a descriptor +* has been processed rather than before it is processed. A series of +* descriptors are put into the list followed by a commit operation, or each +* descriptor may be commited. A commit operation is performed by changing a +* single descriptor, the first of the series of puts, to indicate that the +* hardware may now use all descriptors after it. The last descriptor in the +* list is always set to cause the hardware to stop after it is processed. +* +* Typical Scatter Gather Processing +* +* The following steps illustrate the typical processing to use the +* scatter gather features of a DMA channel. +* +* 1. Create a scatter gather list for the DMA channel which puts empty buffer +* descriptors into the list. +* 2. Create buffer descriptors which describe the buffers to be filled with +* receive data or the buffers which contain data to be sent. +* 3. Put buffer descriptors into the DMA channel scatter list such that scatter +* gather operations are requested. +* 4. Commit the buffer descriptors in the list such that they are ready to be +* used by the DMA channel hardware. +* 5. Start the scatter gather operations of the DMA channel. +* 6. Process any interrupts which occur as a result of the scatter gather +* operations or poll the DMA channel to determine the status. This may +* be accomplished by getting the packet count for the channel and then +* getting the appropriate number of descriptors from the list for that +* number of packets. +* +* Minimizing Interrupts +* +* The Scatter Gather operating mode is designed to reduce the amount of CPU +* throughput necessary to manage the hardware for devices. A key to the CPU +* throughput is the number and rate of interrupts that the CPU must service. +* Devices with higher data rates can cause larger numbers of interrupts and +* higher frequency interrupts. Ideally the number of interrupts can be reduced +* by only generating an interrupt when a specific amount of data has been +* received from the interface. This design suffers from a lack of interrupts +* when the amount of data received is less than the specified amount of data +* to generate an interrupt. In order to help minimize the number of interrupts +* which the CPU must service, an algorithm referred to as "interrupt coalescing" +* is utilized. +* +* Interrupt Coalescing +* +* The principle of interrupt coalescing is to wait before generating an +* interrupt until a certain number of packets have been received or sent. An +* interrupt is also generated if a smaller number of packets have been received +* followed by a certain period of time with no packet reception. This is a +* trade-off of latency for bandwidth and is accomplished using several +* mechanisms of the hardware including a counter for packets received or +* transmitted and a packet timer. These two hardware mechanisms work in +* combination to allow a reduction in the number of interrupts processed by the +* CPU for packet reception. +* +* Unserviced Packet Count +* +* The purpose of the packet counter is to count the number of packets received +* or transmitted and provide an interrupt when a specific number of packets +* have been processed by the hardware. An interrupt is generated whenever the +* counter is greater than or equal to the Packet Count Threshold. This counter +* contains an accurate count of the number of packets that the hardware has +* processed, either received or transmitted, and the software has not serviced. +* +* The packet counter allows the number of interrupts to be reduced by waiting +* to generate an interrupt until enough packets are received. For packet +* reception, packet counts of less than the number to generate an interrupt +* would not be serviced without the addition of a packet timer. This counter is +* continuously updated by the hardware, not latched to the value at the time +* the interrupt occurred. +* +* The packet counter can be used within the interrupt service routine for the +* device to reduce the number of interrupts. The interrupt service routine +* loops while performing processing for each packet which has been received or +* transmitted and decrements the counter by a specified value. At the same time, +* the hardware is possibly continuing to receive or transmit more packets such +* that the software may choose, based upon the value in the packet counter, to +* remain in the interrupt service routine rather than exiting and immediately +* returning. This feature should be used with caution as reducing the number of +* interrupts is beneficial, but unbounded interrupt processing is not desirable. +* +* Since the hardware may be incrementing the packet counter simultaneously +* with the software decrementing the counter, there is a need for atomic +* operations. The hardware ensures that the operation is atomic such that +* simultaneous accesses are properly handled. +* +* Packet Wait Bound +* +* The purpose of the packet wait bound is to augment the unserviced packet +* count. Whenever there is no pending interrupt for the channel and the +* unserviced packet count is non-zero, a timer starts counting timeout at the +* value contained the the packet wait bound register. If the timeout is +* reached, an interrupt is generated such that the software may service the +* data which was buffered. +* +* NOTES: +* +* Special Test Conditions: +* +* The scatter gather list processing must be thoroughly tested if changes are +* made. Testing should include putting and committing single descriptors and +* putting multiple descriptors followed by a single commit. There are some +* conditions in the code which handle the exception conditions. +* +* The Put Pointer points to the next location in the descriptor list to copy +* in a new descriptor. The Get Pointer points to the next location in the +* list to get a descriptor from. The Get Pointer only allows software to +* have a traverse the list after the hardware has finished processing some +* number of descriptors. The Commit Pointer points to the descriptor in the +* list which is to be committed. It is also used to determine that no +* descriptor is waiting to be commited (NULL). The Last Pointer points to +* the last descriptor that was put into the list. It typically points +* to the previous descriptor to the one pointed to by the Put Pointer. +* Comparisons are done between these pointers to determine when the following +* special conditions exist. + +* Single Put And Commit +* +* The buffer descriptor is ready to be used by the hardware so it is important +* for the descriptor to not appear to be waiting to be committed. The commit +* pointer is reset when a commit is done indicating there are no descriptors +* waiting to be committed. In all cases but this one, the descriptor is +* changed to cause the hardware to go to the next descriptor after processing +* this one. But in this case, this is the last descriptor in the list such +* that it must not be changed. +* +* 3 Or More Puts And Commit +* +* A series of 3 or more puts followed by a single commit is different in that +* only the 1st descriptor put into the list is changed when the commit is done. +* This requires each put starting on the 3rd to change the previous descriptor +* so that it allows the hardware to continue to the next descriptor in the list. +* +* The 1st Put Following A Commit +* +* The commit caused the commit pointer to be NULL indicating that there are no +* descriptors waiting to be committed. It is necessary for the next put to set +* the commit pointer so that a commit must follow the put for the hardware to +* use the descriptor. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- ------------------------------------------------------
+* 1.00a rpm  02/03/03 Removed the XST_DMA_SG_COUNT_EXCEEDED return code
+*		      from SetPktThreshold.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdma_channel.h" +#include "xbasic_types.h" +#include "xio.h" +#include "xbuf_descriptor.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +#define XDC_SWCR_SG_ENABLE_MASK 0x80000000UL /* scatter gather enable */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/* the following macro copies selected fields of a buffer descriptor to another + * buffer descriptor, this was provided by the buffer descriptor component but + * was moved here since it is only used internally to this component and since + * it does not copy all fields + */ +#define CopyBufferDescriptor(InstancePtr, DestinationPtr) \ +{ \ + *((u32 *)DestinationPtr + XBD_CONTROL_OFFSET) = \ + *((u32 *)InstancePtr + XBD_CONTROL_OFFSET); \ + *((u32 *)DestinationPtr + XBD_SOURCE_OFFSET) = \ + *((u32 *)InstancePtr + XBD_SOURCE_OFFSET); \ + *((u32 *)DestinationPtr + XBD_DESTINATION_OFFSET) = \ + *((u32 *)InstancePtr + XBD_DESTINATION_OFFSET); \ + *((u32 *)DestinationPtr + XBD_LENGTH_OFFSET) = \ + *((u32 *)InstancePtr + XBD_LENGTH_OFFSET); \ + *((u32 *)DestinationPtr + XBD_STATUS_OFFSET) = \ + *((u32 *)InstancePtr + XBD_STATUS_OFFSET); \ + *((u32 *)DestinationPtr + XBD_DEVICE_STATUS_OFFSET) = \ + *((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET); \ + *((u32 *)DestinationPtr + XBD_ID_OFFSET) = \ + *((u32 *)InstancePtr + XBD_ID_OFFSET); \ + *((u32 *)DestinationPtr + XBD_FLAGS_OFFSET) = \ + *((u32 *)InstancePtr + XBD_FLAGS_OFFSET); \ + *((u32 *)DestinationPtr + XBD_RQSTED_LENGTH_OFFSET) = \ + *((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET); \ +} + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_SgStart +* +* DESCRIPTION: +* +* This function starts a scatter gather operation for a scatter gather +* DMA channel. The first buffer descriptor in the buffer descriptor list +* will be started with the scatter gather operation. A scatter gather list +* should have previously been created for the DMA channel and buffer +* descriptors put into the scatter gather list such that there are scatter +* operations ready to be performed. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* RETURN VALUE: +* +* A status containing XST_SUCCESS if scatter gather was started successfully +* for the DMA channel. +* +* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not +* been created. +* +* A value of XST_DMA_SG_LIST_EMPTY indicates scatter gather was not started +* because the scatter gather list of the DMA channel does not contain any +* buffer descriptors that are ready to be processed by the hardware. +* +* A value of XST_DMA_SG_IS_STARTED indicates scatter gather was not started +* because the scatter gather was not stopped, but was already started. +* +* A value of XST_DMA_SG_BD_NOT_COMMITTED indicates the buffer descriptor of +* scatter gather list which was to be started is not committed to the list. +* This status is more likely if this function is being called from an ISR +* and non-ISR processing is putting descriptors into the list. +* +* A value of XST_DMA_SG_NO_DATA indicates that the buffer descriptor of the +* scatter gather list which was to be started had already been used by the +* hardware for a DMA transfer that has been completed. +* +* NOTES: +* +* It is the responsibility of the caller to get all the buffer descriptors +* after performing a stop operation and before performing a start operation. +* If buffer descriptors are not retrieved between stop and start operations, +* buffer descriptors may be processed by the hardware more than once. +* +******************************************************************************/ +XStatus +XDmaChannel_SgStart(XDmaChannel * InstancePtr) +{ + u32 Register; + XBufDescriptor *LastDescriptorPtr; + + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* if a scatter gather list has not been created yet, return a status */ + + if (InstancePtr->TotalDescriptorCount == 0) { + return XST_DMA_SG_NO_LIST; + } + + /* if the scatter gather list exists but is empty then return a status */ + + if (XDmaChannel_IsSgListEmpty(InstancePtr)) { + return XST_DMA_SG_LIST_EMPTY; + } + + /* if scatter gather is busy for the DMA channel, return a status because + * restarting it could lose data + */ + + Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET); + if (Register & XDC_DMASR_SG_BUSY_MASK) { + return XST_DMA_SG_IS_STARTED; + } + + /* get the address of the last buffer descriptor which the DMA hardware + * finished processing + */ + LastDescriptorPtr = + (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress + + XDC_BDA_REG_OFFSET); + + /* setup the first buffer descriptor that will be sent when the scatter + * gather channel is enabled, this is only necessary one time since + * the BDA register of the channel maintains the last buffer descriptor + * processed + */ + if (LastDescriptorPtr == NULL) { + XIo_Out32(InstancePtr->RegBaseAddress + XDC_BDA_REG_OFFSET, + (u32) InstancePtr->GetPtr); + } else { + XBufDescriptor *NextDescriptorPtr; + + /* get the next descriptor to be started, if the status indicates it + * hasn't already been used by the h/w, then it's OK to start it, + * s/w sets the status of each descriptor to busy and then h/w clears + * the busy when it is complete + */ + NextDescriptorPtr = + XBufDescriptor_GetNextPtr(LastDescriptorPtr); + + if ((XBufDescriptor_GetStatus(NextDescriptorPtr) & + XDC_DMASR_BUSY_MASK) == 0) { + return XST_DMA_SG_NO_DATA; + } + /* don't start the DMA SG channel if the descriptor to be processed + * by h/w is to be committed by the s/w, this function can be called + * such that it interrupts a thread that was putting into the list + */ + if (NextDescriptorPtr == InstancePtr->CommitPtr) { + return XST_DMA_SG_BD_NOT_COMMITTED; + } + } + + /* start the scatter gather operation by clearing the stop bit in the + * control register and setting the enable bit in the s/w control register, + * both of these are necessary to cause it to start, right now the order of + * these statements is important, the software control register should be + * set 1st. The other order can cause the CPU to have a loss of sync + * because it cannot read/write the register while the DMA operation is + * running + */ + + Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET); + + XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET, + Register | XDC_SWCR_SG_ENABLE_MASK); + + Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET); + + XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, + Register & ~XDC_DMACR_SG_DISABLE_MASK); + + /* indicate the DMA channel scatter gather operation was started + * successfully + */ + return XST_SUCCESS; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_SgStop +* +* DESCRIPTION: +* +* This function stops a scatter gather operation for a scatter gather +* DMA channel. This function starts the process of stopping a scatter +* gather operation that is in progress and waits for the stop to be completed. +* Since it waits for the operation to stopped before returning, this function +* could take an amount of time relative to the size of the DMA scatter gather +* operation which is in progress. The scatter gather list of the DMA channel +* is not modified by this function such that starting the scatter gather +* channel after stopping it will cause it to resume. This operation is +* considered to be a graceful stop in that the scatter gather operation +* completes the current buffer descriptor before stopping. +* +* If the interrupt is enabled, an interrupt will be generated when the +* operation is stopped and the caller is responsible for handling the +* interrupt. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* BufDescriptorPtr is also a return value which contains a pointer to the +* buffer descriptor which the scatter gather operation completed when it +* was stopped. +* +* RETURN VALUE: +* +* A status containing XST_SUCCESS if scatter gather was stopped successfully +* for the DMA channel. +* +* A value of XST_DMA_SG_IS_STOPPED indicates scatter gather was not stoppped +* because the scatter gather is not started, but was already stopped. +* +* BufDescriptorPtr contains a pointer to the buffer descriptor which was +* completed when the operation was stopped. +* +* NOTES: +* +* This function implements a loop which polls the hardware for an infinite +* amount of time. If the hardware is not operating correctly, this function +* may never return. +* +******************************************************************************/ +XStatus +XDmaChannel_SgStop(XDmaChannel * InstancePtr, + XBufDescriptor ** BufDescriptorPtr) +{ + u32 Register; + + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(BufDescriptorPtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* get the contents of the software control register, if scatter gather is not + * enabled (started), then return a status because the disable acknowledge + * would not be generated + */ + Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET); + + if ((Register & XDC_SWCR_SG_ENABLE_MASK) == 0) { + return XST_DMA_SG_IS_STOPPED; + } + + /* Ensure the interrupt status for the scatter gather is cleared such + * that this function will wait til the disable has occurred, writing + * a 1 to only that bit in the register will clear only it + */ + XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, + XDC_IXR_SG_DISABLE_ACK_MASK); + + /* disable scatter gather by writing to the software control register + * without modifying any other bits of the register + */ + XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET, + Register & ~XDC_SWCR_SG_ENABLE_MASK); + + /* scatter gather does not disable immediately, but after the current + * buffer descriptor is complete, so wait for the DMA channel to indicate + * the disable is complete + */ + do { + Register = + XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET); + } while ((Register & XDC_IXR_SG_DISABLE_ACK_MASK) == 0); + + /* Ensure the interrupt status for the scatter gather disable is cleared, + * writing a 1 to only that bit in the register will clear only it + */ + XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, + XDC_IXR_SG_DISABLE_ACK_MASK); + + /* set the specified buffer descriptor pointer to point to the buffer + * descriptor that the scatter gather DMA channel was processing + */ + *BufDescriptorPtr = + (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress + + XDC_BDA_REG_OFFSET); + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_CreateSgList +* +* DESCRIPTION: +* +* This function creates a scatter gather list in the DMA channel. A scatter +* gather list consists of a list of buffer descriptors that are available to +* be used for scatter gather operations. Buffer descriptors are put into the +* list to request a scatter gather operation to be performed. +* +* A number of buffer descriptors are created from the specified memory and put +* into a buffer descriptor list as empty buffer descriptors. This function must +* be called before non-empty buffer descriptors may be put into the DMA channel +* to request scatter gather operations. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* MemoryPtr contains a pointer to the memory which is to be used for buffer +* descriptors and must not be cached. +* +* ByteCount contains the number of bytes for the specified memory to be used +* for buffer descriptors. +* +* RETURN VALUE: +* +* A status contains XST_SUCCESS if the scatter gather list was successfully +* created. +* +* A value of XST_DMA_SG_LIST_EXISTS indicates that the scatter gather list +* was not created because the list has already been created. +* +* NOTES: +* +* None. +* +******************************************************************************/ +XStatus +XDmaChannel_CreateSgList(XDmaChannel * InstancePtr, + u32 * MemoryPtr, u32 ByteCount) +{ + XBufDescriptor *BufferDescriptorPtr = (XBufDescriptor *) MemoryPtr; + XBufDescriptor *PreviousDescriptorPtr = NULL; + XBufDescriptor *StartOfListPtr = BufferDescriptorPtr; + u32 UsedByteCount; + + /* assert to verify valid input arguments, alignment for those + * arguments that have alignment restrictions, and at least enough + * memory for one buffer descriptor + */ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(MemoryPtr != NULL); + XASSERT_NONVOID(((u32) MemoryPtr & 3) == 0); + XASSERT_NONVOID(ByteCount != 0); + XASSERT_NONVOID(ByteCount >= sizeof (XBufDescriptor)); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* if the scatter gather list has already been created, then return + * with a status + */ + if (InstancePtr->TotalDescriptorCount != 0) { + return XST_DMA_SG_LIST_EXISTS; + } + + /* loop thru the specified memory block and create as many buffer + * descriptors as possible putting each into the list which is + * implemented as a ring buffer, make sure not to use any memory which + * is not large enough for a complete buffer descriptor + */ + UsedByteCount = 0; + while ((UsedByteCount + sizeof (XBufDescriptor)) <= ByteCount) { + /* setup a pointer to the next buffer descriptor in the memory and + * update # of used bytes to know when all of memory is used + */ + BufferDescriptorPtr = (XBufDescriptor *) ((u32) MemoryPtr + + UsedByteCount); + + /* initialize the new buffer descriptor such that it doesn't contain + * garbage which could be used by the DMA hardware + */ + XBufDescriptor_Initialize(BufferDescriptorPtr); + + /* if this is not the first buffer descriptor to be created, + * then link it to the last created buffer descriptor + */ + if (PreviousDescriptorPtr != NULL) { + XBufDescriptor_SetNextPtr(PreviousDescriptorPtr, + BufferDescriptorPtr); + } + + /* always keep a pointer to the last created buffer descriptor such + * that they can be linked together in the ring buffer + */ + PreviousDescriptorPtr = BufferDescriptorPtr; + + /* keep a count of the number of descriptors in the list to allow + * error processing to be performed + */ + InstancePtr->TotalDescriptorCount++; + + UsedByteCount += sizeof (XBufDescriptor); + } + + /* connect the last buffer descriptor created and inserted in the list + * to the first such that a ring buffer is created + */ + XBufDescriptor_SetNextPtr(BufferDescriptorPtr, StartOfListPtr); + + /* initialize the ring buffer to indicate that there are no + * buffer descriptors in the list which point to valid data buffers + */ + InstancePtr->PutPtr = BufferDescriptorPtr; + InstancePtr->GetPtr = BufferDescriptorPtr; + InstancePtr->CommitPtr = NULL; + InstancePtr->LastPtr = BufferDescriptorPtr; + InstancePtr->ActiveDescriptorCount = 0; + + /* indicate the scatter gather list was successfully created */ + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_IsSgListEmpty +* +* DESCRIPTION: +* +* This function determines if the scatter gather list of a DMA channel is +* empty with regard to buffer descriptors which are pointing to buffers to be +* used for scatter gather operations. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* RETURN VALUE: +* +* A value of TRUE if the scatter gather list is empty, otherwise a value of +* FALSE. +* +* NOTES: +* +* None. +* +******************************************************************************/ +u32 +XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr) +{ + /* assert to verify valid input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* if the number of descriptors which are being used in the list is zero + * then the list is empty + */ + return (InstancePtr->ActiveDescriptorCount == 0); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_PutDescriptor +* +* DESCRIPTION: +* +* This function puts a buffer descriptor into the DMA channel scatter +* gather list. A DMA channel maintains a list of buffer descriptors which are +* to be processed. This function puts the specified buffer descriptor +* at the next location in the list. Note that since the list is already intact, +* the information in the parameter is copied into the list (rather than modify +* list pointers on the fly). +* +* After buffer descriptors are put into the list, they must also be committed +* by calling another function. This allows multiple buffer descriptors which +* span a single packet to be put into the list while preventing the hardware +* from starting the first buffer descriptor of the packet. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* BufferDescriptorPtr is a pointer to the buffer descriptor to be put into +* the next available location of the scatter gather list. +* +* RETURN VALUE: +* +* A status which indicates XST_SUCCESS if the buffer descriptor was +* successfully put into the scatter gather list. +* +* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not +* been created. +* +* A value of XST_DMA_SG_LIST_FULL indicates the buffer descriptor was not +* put into the list because the list was full. +* +* A value of XST_DMA_SG_BD_LOCKED indicates the buffer descriptor was not +* put into the list because the buffer descriptor in the list which is to +* be overwritten was locked. A locked buffer descriptor indicates the higher +* layered software is still using the buffer descriptor. +* +* NOTES: +* +* It is necessary to create a scatter gather list for a DMA channel before +* putting buffer descriptors into it. +* +******************************************************************************/ +XStatus +XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr, + XBufDescriptor * BufferDescriptorPtr) +{ + u32 Control; + + /* assert to verify valid input arguments and alignment for those + * arguments that have alignment restrictions + */ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(BufferDescriptorPtr != NULL); + XASSERT_NONVOID(((u32) BufferDescriptorPtr & 3) == 0); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* if a scatter gather list has not been created yet, return a status */ + + if (InstancePtr->TotalDescriptorCount == 0) { + return XST_DMA_SG_NO_LIST; + } + + /* if the list is full because all descriptors are pointing to valid + * buffers, then indicate an error, this code assumes no list or an + * empty list is detected above + */ + if (InstancePtr->ActiveDescriptorCount == + InstancePtr->TotalDescriptorCount) { + return XST_DMA_SG_LIST_FULL; + } + + /* if the buffer descriptor in the list which is to be overwritten is + * locked, then don't overwrite it and return a status + */ + if (XBufDescriptor_IsLocked(InstancePtr->PutPtr)) { + return XST_DMA_SG_BD_LOCKED; + } + + /* set the scatter gather stop bit in the control word of the descriptor + * to cause the h/w to stop after it processes this descriptor since it + * will be the last in the list + */ + Control = XBufDescriptor_GetControl(BufferDescriptorPtr); + XBufDescriptor_SetControl(BufferDescriptorPtr, + Control | XDC_DMACR_SG_DISABLE_MASK); + + /* set both statuses in the descriptor so we tell if they are updated with + * the status of the transfer, the hardware should change the busy in the + * DMA status to be false when it completes + */ + XBufDescriptor_SetStatus(BufferDescriptorPtr, XDC_DMASR_BUSY_MASK); + XBufDescriptor_SetDeviceStatus(BufferDescriptorPtr, 0); + + /* copy the descriptor into the next position in the list so it's ready to + * be used by the h/w, this assumes the descriptor in the list prior to this + * one still has the stop bit in the control word set such that the h/w + * use this one yet + */ + CopyBufferDescriptor(BufferDescriptorPtr, InstancePtr->PutPtr); + + /* only the last in the list and the one to be committed have scatter gather + * disabled in the control word, a commit requires only one descriptor + * to be changed, when # of descriptors to commit > 2 all others except the + * 1st and last have scatter gather enabled + */ + if ((InstancePtr->CommitPtr != InstancePtr->LastPtr) && + (InstancePtr->CommitPtr != NULL)) { + Control = XBufDescriptor_GetControl(InstancePtr->LastPtr); + XBufDescriptor_SetControl(InstancePtr->LastPtr, + Control & ~XDC_DMACR_SG_DISABLE_MASK); + } + + /* update the list data based upon putting a descriptor into the list, + * these operations must be last + */ + InstancePtr->ActiveDescriptorCount++; + + /* only update the commit pointer if it is not already active, this allows + * it to be deactivated after every commit such that a single descriptor + * which is committed does not appear to be waiting to be committed + */ + if (InstancePtr->CommitPtr == NULL) { + InstancePtr->CommitPtr = InstancePtr->LastPtr; + } + + /* these updates MUST BE LAST after the commit pointer update in order for + * the commit pointer to track the correct descriptor to be committed + */ + InstancePtr->LastPtr = InstancePtr->PutPtr; + InstancePtr->PutPtr = XBufDescriptor_GetNextPtr(InstancePtr->PutPtr); + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_CommitPuts +* +* DESCRIPTION: +* +* This function commits the buffer descriptors which have been put into the +* scatter list for the DMA channel since the last commit operation was +* performed. This enables the calling functions to put several buffer +* descriptors into the list (e.g.,a packet's worth) before allowing the scatter +* gather operations to start. This prevents the DMA channel hardware from +* starting to use the buffer descriptors in the list before they are ready +* to be used (multiple buffer descriptors for a single packet). +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* RETURN VALUE: +* +* A status indicating XST_SUCCESS if the buffer descriptors of the list were +* successfully committed. +* +* A value of XST_DMA_SG_NOTHING_TO_COMMIT indicates that the buffer descriptors +* were not committed because there was nothing to commit in the list. All the +* buffer descriptors which are in the list are commited. +* +* NOTES: +* +* None. +* +******************************************************************************/ +XStatus +XDmaChannel_CommitPuts(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* if the buffer descriptor to be committed is already committed or + * the list is empty (none have been put in), then indicate an error + */ + if ((InstancePtr->CommitPtr == NULL) || + XDmaChannel_IsSgListEmpty(InstancePtr)) { + return XST_DMA_SG_NOTHING_TO_COMMIT; + } + + /* last descriptor in the list must have scatter gather disabled so the end + * of the list is hit by h/w, if descriptor to commit is not last in list, + * commit descriptors by enabling scatter gather in the descriptor + */ + if (InstancePtr->CommitPtr != InstancePtr->LastPtr) { + u32 Control; + + Control = XBufDescriptor_GetControl(InstancePtr->CommitPtr); + XBufDescriptor_SetControl(InstancePtr->CommitPtr, Control & + ~XDC_DMACR_SG_DISABLE_MASK); + } + /* Update the commit pointer to indicate that there is nothing to be + * committed, this state is used by start processing to know that the + * buffer descriptor to start is not waiting to be committed + */ + InstancePtr->CommitPtr = NULL; + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_GetDescriptor +* +* DESCRIPTION: +* +* This function gets a buffer descriptor from the scatter gather list of the +* DMA channel. The buffer descriptor is retrieved from the scatter gather list +* and the scatter gather list is updated to not include the retrieved buffer +* descriptor. This is typically done after a scatter gather operation +* completes indicating that a data buffer has been successfully sent or data +* has been received into the data buffer. The purpose of this function is to +* allow the device using the scatter gather operation to get the results of the +* operation. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* BufDescriptorPtr is a pointer to a pointer to the buffer descriptor which +* was retrieved from the list. The buffer descriptor is not really removed +* from the list, but it is changed to a state such that the hardware will not +* use it again until it is put into the scatter gather list of the DMA channel. +* +* RETURN VALUE: +* +* A status indicating XST_SUCCESS if a buffer descriptor was retrieved from +* the scatter gather list of the DMA channel. +* +* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not +* been created. +* +* A value of XST_DMA_SG_LIST_EMPTY indicates no buffer descriptor was +* retrieved from the list because there are no buffer descriptors to be +* processed in the list. +* +* BufDescriptorPtr is updated to point to the buffer descriptor which was +* retrieved from the list if the status indicates success. +* +* NOTES: +* +* None. +* +******************************************************************************/ +XStatus +XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr, + XBufDescriptor ** BufDescriptorPtr) +{ + u32 Control; + + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(BufDescriptorPtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* if a scatter gather list has not been created yet, return a status */ + + if (InstancePtr->TotalDescriptorCount == 0) { + return XST_DMA_SG_NO_LIST; + } + + /* if the buffer descriptor list is empty, then indicate an error */ + + if (XDmaChannel_IsSgListEmpty(InstancePtr)) { + return XST_DMA_SG_LIST_EMPTY; + } + + /* retrieve the next buffer descriptor which is ready to be processed from + * the buffer descriptor list for the DMA channel, set the control word + * such that hardware will stop after the descriptor has been processed + */ + Control = XBufDescriptor_GetControl(InstancePtr->GetPtr); + XBufDescriptor_SetControl(InstancePtr->GetPtr, + Control | XDC_DMACR_SG_DISABLE_MASK); + + /* set the input argument, which is also an output, to point to the + * buffer descriptor which is to be retrieved from the list + */ + *BufDescriptorPtr = InstancePtr->GetPtr; + + /* update the pointer of the DMA channel to reflect the buffer descriptor + * was retrieved from the list by setting it to the next buffer descriptor + * in the list and indicate one less descriptor in the list now + */ + InstancePtr->GetPtr = XBufDescriptor_GetNextPtr(InstancePtr->GetPtr); + InstancePtr->ActiveDescriptorCount--; + + return XST_SUCCESS; +} + +/*********************** Interrupt Collescing Functions **********************/ + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_GetPktCount +* +* DESCRIPTION: +* +* This function returns the value of the unserviced packet count register of +* the DMA channel. This count represents the number of packets that have been +* sent or received by the hardware, but not processed by software. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* RETURN VALUE: +* +* The unserviced packet counter register contents for the DMA channel. +* +* NOTES: +* +* None. +* +******************************************************************************/ +u32 +XDmaChannel_GetPktCount(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* get the unserviced packet count from the register and return it */ + + return XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_DecrementPktCount +* +* DESCRIPTION: +* +* This function decrements the value of the unserviced packet count register. +* This informs the hardware that the software has processed a packet. The +* unserviced packet count register may only be decremented by one in the +* hardware. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +void +XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr) +{ + u32 Register; + + /* assert to verify input arguments */ + + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* if the unserviced packet count register can be decremented (rather + * than rolling over) decrement it by writing a 1 to the register, + * this is the only valid write to the register as it serves as an + * acknowledge that a packet was handled by the software + */ + Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET); + if (Register > 0) { + XIo_Out32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET, + 1UL); + } +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_SetPktThreshold +* +* DESCRIPTION: +* +* This function sets the value of the packet count threshold register of the +* DMA channel. It reflects the number of packets that must be sent or +* received before generating an interrupt. This value helps implement +* a concept called "interrupt coalescing", which is used to reduce the number +* of interrupts from devices with high data rates. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* Threshold is the value that is written to the threshold register of the +* DMA channel. +* +* RETURN VALUE: +* +* A status containing XST_SUCCESS if the packet count threshold was +* successfully set. +* +* NOTES: +* +* The packet threshold could be set to larger than the number of descriptors +* allocated to the DMA channel. In this case, the wait bound will take over +* and always indicate data arrival. There was a check in this function that +* returned an error if the treshold was larger than the number of descriptors, +* but that was removed because users would then have to set the threshold +* only after they set descriptor space, which is an order dependency that +* caused confustion. +* +******************************************************************************/ +XStatus +XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold) +{ + /* assert to verify input arguments, don't assert the threshold since + * it's range is unknown + */ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* set the packet count threshold in the register such that an interrupt + * may be generated, if enabled, when the packet count threshold is + * reached or exceeded + */ + XIo_Out32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET, + (u32) Threshold); + + /* indicate the packet count threshold was successfully set */ + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_GetPktThreshold +* +* DESCRIPTION: +* +* This function gets the value of the packet count threshold register of the +* DMA channel. This value reflects the number of packets that must be sent or +* received before generating an interrupt. This value helps implement a concept +* called "interrupt coalescing", which is used to reduce the number of +* interrupts from devices with high data rates. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* RETURN VALUE: +* +* The packet threshold register contents for the DMA channel and is a value in +* the range 0 - 1023. A value of 0 indicates the packet wait bound timer is +* disabled. +* +* NOTES: +* +* None. +* +******************************************************************************/ +u8 +XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* get the packet count threshold from the register and return it, + * since only 8 bits are used, cast it to return only those bits */ + + return (u8) XIo_In32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_SetPktWaitBound +* +* DESCRIPTION: +* +* This function sets the value of the packet wait bound register of the +* DMA channel. This value reflects the timer value used to trigger an +* interrupt when not enough packets have been received to reach the packet +* count threshold. +* +* The timer is in millisecond units with +/- 33% accuracy. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* WaitBound is the value, in milliseconds, to be stored in the wait bound +* register of the DMA channel and is a value in the range 0 - 1023. A value +* of 0 disables the packet wait bound timer. +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +void +XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound) +{ + /* assert to verify input arguments */ + + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(WaitBound < 1024); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* set the packet wait bound in the register such that interrupt may be + * generated, if enabled, when packets have not been handled for a specific + * amount of time + */ + XIo_Out32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET, WaitBound); +} + +/****************************************************************************** +* +* FUNCTION: +* +* XDmaChannel_GetPktWaitBound +* +* DESCRIPTION: +* +* This function gets the value of the packet wait bound register of the +* DMA channel. This value contains the timer value used to trigger an +* interrupt when not enough packets have been received to reach the packet +* count threshold. +* +* The timer is in millisecond units with +/- 33% accuracy. +* +* ARGUMENTS: +* +* InstancePtr contains a pointer to the DMA channel to operate on. The DMA +* channel should be configured to use scatter gather in order for this function +* to be called. +* +* RETURN VALUE: +* +* The packet wait bound register contents for the DMA channel. +* +* NOTES: +* +* None. +* +******************************************************************************/ +u32 +XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* get the packet wait bound from the register and return it */ + + return XIo_In32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET); +} diff --git a/board/xilinx/common/xio.h b/board/xilinx/common/xio.h new file mode 100644 index 0000000..5bb09c8 --- /dev/null +++ b/board/xilinx/common/xio.h @@ -0,0 +1,81 @@ +/* + * xio.h + * + * Defines XIo functions for Xilinx OCP in terms of Linux primitives + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef XIO_H +#define XIO_H + +#include "xbasic_types.h" +#include + +typedef u32 XIo_Address; + +extern inline u8 +XIo_In8(XIo_Address InAddress) +{ + return (u8) in_8((volatile unsigned char *) InAddress); +} +extern inline u16 +XIo_In16(XIo_Address InAddress) +{ + return (u16) in_be16((volatile unsigned short *) InAddress); +} +extern inline u32 +XIo_In32(XIo_Address InAddress) +{ + return (u32) in_be32((volatile unsigned *) InAddress); +} +extern inline void +XIo_Out8(XIo_Address OutAddress, u8 Value) +{ + out_8((volatile unsigned char *) OutAddress, Value); +} +extern inline void +XIo_Out16(XIo_Address OutAddress, u16 Value) +{ + out_be16((volatile unsigned short *) OutAddress, Value); +} +extern inline void +XIo_Out32(XIo_Address OutAddress, u32 Value) +{ + out_be32((volatile unsigned *) OutAddress, Value); +} + +#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s))) +#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s))) +#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s))) +#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s))) + +#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s))) +#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s))) +#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s))) +#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s))) + +#endif /* XIO_H */ diff --git a/board/xilinx/common/xipif_v1_23_b.c b/board/xilinx/common/xipif_v1_23_b.c new file mode 100644 index 0000000..c7311ab --- /dev/null +++ b/board/xilinx/common/xipif_v1_23_b.c @@ -0,0 +1,331 @@ +/* $Id: xipif_v1_23_b.c,v 1.1 2002/03/18 23:24:52 linnj Exp $ */ +/****************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002 Xilinx Inc. +* All rights reserved. +* +******************************************************************************/ +/****************************************************************************** +* +* FILENAME: +* +* xipif.c +* +* DESCRIPTION: +* +* This file contains the implementation of the XIpIf component. The +* XIpIf component encapsulates the IPIF, which is the standard interface +* that IP must adhere to when connecting to a bus. The purpose of this +* component is to encapsulate the IPIF processing such that maintainability +* is increased. This component does not provide a lot of abstraction from +* from the details of the IPIF as it is considered a building block for +* device drivers. A device driver designer must be familiar with the +* details of the IPIF hardware to use this component. +* +* The IPIF hardware provides a building block for all hardware devices such +* that each device does not need to reimplement these building blocks. The +* IPIF contains other building blocks, such as FIFOs and DMA channels, which +* are also common to many devices. These blocks are implemented as separate +* hardware blocks and instantiated within the IPIF. The primary hardware of +* the IPIF which is implemented by this software component is the interrupt +* architecture. Since there are many blocks of a device which may generate +* interrupts, all the interrupt processing is contained in the common part +* of the device, the IPIF. This interrupt processing is for the device level +* only and does not include any processing for the interrupt controller. +* +* A device is a mechanism such as an Ethernet MAC. The device is made +* up of several parts which include an IPIF and the IP. The IPIF contains most +* of the device infrastructure which is common to all devices, such as +* interrupt processing, DMA channels, and FIFOs. The infrastructure may also +* be referred to as IPIF internal blocks since they are part of the IPIF and +* are separate blocks that can be selected based upon the needs of the device. +* The IP of the device is the logic that is unique to the device and interfaces +* to the IPIF of the device. +* +* In general, there are two levels of registers within the IPIF. The first +* level, referred to as the device level, contains registers which are for the +* entire device. The second level, referred to as the IP level, contains +* registers which are specific to the IP of the device. The two levels of +* registers are designed to be hierarchical such that the device level is +* is a more general register set above the more specific registers of the IP. +* The IP level of registers provides functionality which is typically common +* across all devices and allows IP designers to focus on the unique aspects +* of the IP. +* +* The interrupt registers of the IPIF are parameterizable such that the only +* the number of bits necessary for the device are implemented. The functions +* of this component do not attempt to validate that the passed in arguments are +* valid based upon the number of implemented bits. This is necessary to +* maintain the level of performance required for the common components. Bits +* of the registers are assigned starting at the least significant bit of the +* registers. +* +* Critical Sections +* +* It is the responsibility of the device driver designer to use critical +* sections as necessary when calling functions of the IPIF. This component +* does not use critical sections and it does access registers using +* read-modify-write operations. Calls to IPIF functions from a main thread +* and from an interrupt context could produce unpredictable behavior such that +* the caller must provide the appropriate critical sections. +* +* Mutual Exclusion +* +* The functions of the IPIF are not thread safe such that the caller of all +* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual +* exclusion across multiple IPIF components is not necessary. +* +* NOTES: +* +* None. +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.23b jhl 02/27/01 Repartioned to reduce size +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xipif_v1_23_b.h" +#include "xio.h" + +/************************** Constant Definitions *****************************/ + +/* the following constant is used to generate bit masks for register testing + * in the self test functions, it defines the starting bit mask that is to be + * shifted from the LSB to MSB in creating a register test mask + */ +#define XIIF_V123B_FIRST_BIT_MASK 1UL + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +static XStatus IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth); + +/****************************************************************************** +* +* FUNCTION: +* +* XIpIf_SelfTest +* +* DESCRIPTION: +* +* This function performs a self test on the specified IPIF component. Many +* of the registers in the IPIF are tested to ensure proper operation. This +* function is destructive because the IPIF is reset at the start of the test +* and at the end of the test to ensure predictable results. The IPIF reset +* also resets the entire device that uses the IPIF. This function exits with +* all interrupts for the device disabled. +* +* ARGUMENTS: +* +* InstancePtr points to the XIpIf to operate on. +* +* DeviceRegistersWidth contains the number of bits in the device interrupt +* registers. The hardware is parameterizable such that only the number of bits +* necessary to support a device are implemented. This value must be between 0 +* and 32 with 0 indicating there are no device interrupt registers used. +* +* IpRegistersWidth contains the number of bits in the IP interrupt registers +* of the device. The hardware is parameterizable such that only the number of +* bits necessary to support a device are implemented. This value must be +* between 0 and 32 with 0 indicating there are no IP interrupt registers used. +* +* RETURN VALUE: +* +* A value of XST_SUCCESS indicates the test was successful with no errors. +* Any one of the following error values may also be returned. +* +* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was +* not valid +* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status +* register did not read back correctly +* XST_IPIF_IP_ACK_ERROR One or more bits in the IP interrupt +* status register did not reset when acked +* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register +* did not read back correctly based upon +* what was written to it +* +* NOTES: +* +* None. +* +******************************************************************************/ + +/* the following constant defines the maximum number of bits which may be + * used in the registers at the device and IP levels, this is based upon the + * number of bits available in the registers + */ +#define XIIF_V123B_MAX_REG_BIT_COUNT 32 + +XStatus +XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth) +{ + XStatus Status; + + /* assert to verify arguments are valid */ + + XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT); + + /* reset the IPIF such that it's in a known state before the test + * and interrupts are globally disabled + */ + XIIF_V123B_RESET(RegBaseAddress); + + /* perform the self test on the IP interrupt registers, if + * it is not successful exit with the status + */ + Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth); + if (Status != XST_SUCCESS) { + return Status; + } + + /* reset the IPIF such that it's in a known state before exiting test */ + + XIIF_V123B_RESET(RegBaseAddress); + + /* reaching this point means there were no errors, return success */ + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* FUNCTION: +* +* IpIntrSelfTest +* +* DESCRIPTION: +* +* Perform a self test on the IP interrupt registers of the IPIF. This +* function modifies registers of the IPIF such that they are not guaranteed +* to be in the same state when it returns. Any bits in the IP interrupt +* status register which are set are assumed to be set by default after a reset +* and are not tested in the test. +* +* ARGUMENTS: +* +* InstancePtr points to the XIpIf to operate on. +* +* IpRegistersWidth contains the number of bits in the IP interrupt registers +* of the device. The hardware is parameterizable such that only the number of +* bits necessary to support a device are implemented. This value must be +* between 0 and 32 with 0 indicating there are no IP interrupt registers used. +* +* RETURN VALUE: +* +* A status indicating XST_SUCCESS if the test was successful. Otherwise, one +* of the following values is returned. +* +* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was +* not valid +* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status +* register did not read back correctly +* XST_IPIF_IP_ACK_ERROR One or more bits in the IP status +* register did not reset when acked +* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register +* did not read back correctly based upon +* what was written to it +* NOTES: +* +* None. +* +******************************************************************************/ +static XStatus +IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth) +{ + /* ensure that the IP interrupt interrupt enable register is zero + * as it should be at reset, the interrupt status is dependent upon the + * IP such that it's reset value is not known + */ + if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) { + return XST_IPIF_RESET_REGISTER_ERROR; + } + + /* if there are any used IP interrupts, then test all of the interrupt + * bits in all testable registers + */ + if (IpRegistersWidth > 0) { + u32 BitCount; + u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK; + u32 Mask = XIIF_V123B_FIRST_BIT_MASK; /* bits assigned MSB to LSB */ + u32 InterruptStatus; + + /* generate the register masks to be used for IP register tests, the + * number of bits supported by the hardware is parameterizable such + * that only that number of bits are implemented in the registers, the + * bits are allocated starting at the MSB of the registers + */ + for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) { + Mask = Mask << 1; + IpInterruptMask |= Mask; + } + + /* get the current IP interrupt status register contents, any bits + * already set must default to 1 at reset in the device and these + * bits can't be tested in the following test, remove these bits from + * the mask that was generated for the test + */ + InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress); + IpInterruptMask &= ~InterruptStatus; + + /* set the bits in the device status register and verify them by reading + * the register again, all bits of the register are latched + */ + XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask); + InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress); + if ((InterruptStatus & IpInterruptMask) != IpInterruptMask) + { + return XST_IPIF_IP_STATUS_ERROR; + } + + /* test to ensure that the bits set in the IP interrupt status register + * can be cleared by acknowledging them in the IP interrupt status + * register then read it again and verify it was cleared + */ + XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask); + InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress); + if ((InterruptStatus & IpInterruptMask) != 0) { + return XST_IPIF_IP_ACK_ERROR; + } + + /* set the IP interrupt enable set register and then read the IP + * interrupt enable register and verify the interrupts were enabled + */ + XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask); + if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) { + return XST_IPIF_IP_ENABLE_ERROR; + } + + /* clear the IP interrupt enable register and then read the + * IP interrupt enable register and verify the interrupts were disabled + */ + XIIF_V123B_WRITE_IIER(RegBaseAddress, 0); + if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) { + return XST_IPIF_IP_ENABLE_ERROR; + } + } + return XST_SUCCESS; +} diff --git a/board/xilinx/common/xipif_v1_23_b.h b/board/xilinx/common/xipif_v1_23_b.h new file mode 100644 index 0000000..3ce1fff --- /dev/null +++ b/board/xilinx/common/xipif_v1_23_b.h @@ -0,0 +1,746 @@ +/* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */ +/****************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002 Xilinx Inc. +* All rights reserved. +* +******************************************************************************/ +/****************************************************************************** +* +* FILENAME: +* +* xipif.h +* +* DESCRIPTION: +* +* The XIpIf component encapsulates the IPIF, which is the standard interface +* that IP must adhere to when connecting to a bus. The purpose of this +* component is to encapsulate the IPIF processing such that maintainability +* is increased. This component does not provide a lot of abstraction from +* from the details of the IPIF as it is considered a building block for +* device drivers. A device driver designer must be familiar with the +* details of the IPIF hardware to use this component. +* +* The IPIF hardware provides a building block for all hardware devices such +* that each device does not need to reimplement these building blocks. The +* IPIF contains other building blocks, such as FIFOs and DMA channels, which +* are also common to many devices. These blocks are implemented as separate +* hardware blocks and instantiated within the IPIF. The primary hardware of +* the IPIF which is implemented by this software component is the interrupt +* architecture. Since there are many blocks of a device which may generate +* interrupts, all the interrupt processing is contained in the common part +* of the device, the IPIF. This interrupt processing is for the device level +* only and does not include any processing for the interrupt controller. +* +* A device is a mechanism such as an Ethernet MAC. The device is made +* up of several parts which include an IPIF and the IP. The IPIF contains most +* of the device infrastructure which is common to all devices, such as +* interrupt processing, DMA channels, and FIFOs. The infrastructure may also +* be referred to as IPIF internal blocks since they are part of the IPIF and +* are separate blocks that can be selected based upon the needs of the device. +* The IP of the device is the logic that is unique to the device and interfaces +* to the IPIF of the device. +* +* In general, there are two levels of registers within the IPIF. The first +* level, referred to as the device level, contains registers which are for the +* entire device. The second level, referred to as the IP level, contains +* registers which are specific to the IP of the device. The two levels of +* registers are designed to be hierarchical such that the device level is +* is a more general register set above the more specific registers of the IP. +* The IP level of registers provides functionality which is typically common +* across all devices and allows IP designers to focus on the unique aspects +* of the IP. +* +* Critical Sections +* +* It is the responsibility of the device driver designer to use critical +* sections as necessary when calling functions of the IPIF. This component +* does not use critical sections and it does access registers using +* read-modify-write operations. Calls to IPIF functions from a main thread +* and from an interrupt context could produce unpredictable behavior such that +* the caller must provide the appropriate critical sections. +* +* Mutual Exclusion +* +* The functions of the IPIF are not thread safe such that the caller of all +* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual +* exclusion across multiple IPIF components is not necessary. +* +* NOTES: +* +* None. +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.23b jhl 02/27/01 Repartioned to minimize size +* +******************************************************************************/ + +#ifndef XIPIF_H /* prevent circular inclusions */ +#define XIPIF_H /* by using protection macros */ + +/***************************** Include Files *********************************/ +#include "xbasic_types.h" +#include "xstatus.h" +#include "xversion.h" + +/************************** Constant Definitions *****************************/ + +/* the following constants define the register offsets for the registers of the + * IPIF, there are some holes in the memory map for reserved addresses to allow + * other registers to be added and still match the memory map of the interrupt + * controller registers + */ +#define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */ +#define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */ +#define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */ +#define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */ +#define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */ +#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ +#define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */ +#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ + +#define XIIF_V123B_RESET_MASK 0xAUL + +/* the following constant is used for the device global interrupt enable + * register, to enable all interrupts for the device, this is the only bit + * in the register + */ +#define XIIF_V123B_GINTR_ENABLE_MASK 0x80000000UL + +/* the following constants contain the masks to identify each internal IPIF + * condition in the device registers of the IPIF, interrupts are assigned + * in the register from LSB to the MSB + */ +#define XIIF_V123B_ERROR_MASK 1UL /* LSB of the register */ + +/* The following constants contain interrupt IDs which identify each internal + * IPIF condition, this value must correlate with the mask constant for the + * error + */ +#define XIIF_V123B_ERROR_INTERRUPT_ID 0 /* interrupt bit #, (LSB = 0) */ +#define XIIF_V123B_NO_INTERRUPT_ID 128 /* no interrupts are pending */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_RESET +* +* DESCRIPTION: +* +* Reset the IPIF component and hardware. This is a destructive operation that +* could cause the loss of data since resetting the IPIF of a device also +* resets the device using the IPIF and any blocks, such as FIFOs or DMA +* channels, within the IPIF. All registers of the IPIF will contain their +* reset value when this function returns. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ + +/* the following constant is used in the reset register to cause the IPIF to + * reset + */ +#define XIIF_V123B_RESET(RegBaseAddress) \ + XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_WRITE_DISR +* +* DESCRIPTION: +* +* This function sets the device interrupt status register to the value. +* This register indicates the status of interrupt sources for a device +* which contains the IPIF. The status is independent of whether interrupts +* are enabled and could be used for polling a device at a higher level rather +* than a more detailed level. +* +* Each bit of the register correlates to a specific interrupt source within the +* device which contains the IPIF. With the exception of some internal IPIF +* conditions, the contents of this register are not latched but indicate +* the live status of the interrupt sources within the device. Writing any of +* the non-latched bits of the register will have no effect on the register. +* +* For the latched bits of this register only, setting a bit which is zero +* within this register causes an interrupt to generated. The device global +* interrupt enable register and the device interrupt enable register must be set +* appropriately to allow an interrupt to be passed out of the device. The +* interrupt is cleared by writing to this register with the bits to be +* cleared set to a one and all others to zero. This register implements a +* toggle on write functionality meaning any bits which are set in the value +* written cause the bits in the register to change to the opposite state. +* +* This function writes the specified value to the register such that +* some bits may be set and others cleared. It is the caller's responsibility +* to get the value of the register prior to setting the value to prevent a +* destructive behavior. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* Status contains the value to be written to the interrupt status register of +* the device. The only bits which can be written are the latched bits which +* contain the internal IPIF conditions. The following values may be used to +* set the status register or clear an interrupt condition. +* +* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \ + XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status)) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_READ_DISR +* +* DESCRIPTION: +* +* This function gets the device interrupt status register contents. +* This register indicates the status of interrupt sources for a device +* which contains the IPIF. The status is independent of whether interrupts +* are enabled and could be used for polling a device at a higher level. +* +* Each bit of the register correlates to a specific interrupt source within the +* device which contains the IPIF. With the exception of some internal IPIF +* conditions, the contents of this register are not latched but indicate +* the live status of the interrupt sources within the device. +* +* For only the latched bits of this register, the interrupt may be cleared by +* writing to these bits in the status register. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* A status which contains the value read from the interrupt status register of +* the device. The bit definitions are specific to the device with +* the exception of the latched internal IPIF condition bits. The following +* values may be used to detect internal IPIF conditions in the status. +* +* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_READ_DISR(RegBaseAddress) \ + XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_WRITE_DIER +* +* DESCRIPTION: +* +* This function sets the device interrupt enable register contents. +* This register controls which interrupt sources of the device are allowed to +* generate an interrupt. The device global interrupt enable register must also +* be set appropriately for an interrupt to be passed out of the device. +* +* Each bit of the register correlates to a specific interrupt source within the +* device which contains the IPIF. Setting a bit in this register enables that +* interrupt source to generate an interrupt. Clearing a bit in this register +* disables interrupt generation for that interrupt source. +* +* This function writes only the specified value to the register such that +* some interrupts source may be enabled and others disabled. It is the +* caller's responsibility to get the value of the interrupt enable register +* prior to setting the value to prevent an destructive behavior. +* +* An interrupt source may not be enabled to generate an interrupt, but can +* still be polled in the interrupt status register. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* Enable contains the value to be written to the interrupt enable register +* of the device. The bit definitions are specific to the device with +* the exception of the internal IPIF conditions. The following +* values may be used to enable the internal IPIF conditions interrupts. +* +* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress, +* u32 Enable) +* +******************************************************************************/ +#define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \ + XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable)) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_READ_DIER +* +* DESCRIPTION: +* +* This function gets the device interrupt enable register contents. +* This register controls which interrupt sources of the device +* are allowed to generate an interrupt. The device global interrupt enable +* register and the device interrupt enable register must also be set +* appropriately for an interrupt to be passed out of the device. +* +* Each bit of the register correlates to a specific interrupt source within the +* device which contains the IPIF. Setting a bit in this register enables that +* interrupt source to generate an interrupt if the global enable is set +* appropriately. Clearing a bit in this register disables interrupt generation +* for that interrupt source regardless of the global interrupt enable. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* The value read from the interrupt enable register of the device. The bit +* definitions are specific to the device with the exception of the internal +* IPIF conditions. The following values may be used to determine from the +* value if the internal IPIF conditions interrupts are enabled. +* +* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_READ_DIER(RegBaseAddress) \ + XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_READ_DIPR +* +* DESCRIPTION: +* +* This function gets the device interrupt pending register contents. +* This register indicates the pending interrupt sources, those that are waiting +* to be serviced by the software, for a device which contains the IPIF. +* An interrupt must be enabled in the interrupt enable register of the IPIF to +* be pending. +* +* Each bit of the register correlates to a specific interrupt source within the +* the device which contains the IPIF. With the exception of some internal IPIF +* conditions, the contents of this register are not latched since the condition +* is latched in the IP interrupt status register, by an internal block of the +* IPIF such as a FIFO or DMA channel, or by the IP of the device. This register +* is read only and is not latched, but it is necessary to acknowledge (clear) +* the interrupt condition by performing the appropriate processing for the IP +* or block within the IPIF. +* +* This register can be thought of as the contents of the interrupt status +* register ANDed with the contents of the interrupt enable register. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* The value read from the interrupt pending register of the device. The bit +* definitions are specific to the device with the exception of the latched +* internal IPIF condition bits. The following values may be used to detect +* internal IPIF conditions in the value. +* +* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_READ_DIPR(RegBaseAddress) \ + XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_READ_DIIR +* +* DESCRIPTION: +* +* This function gets the device interrupt ID for the highest priority interrupt +* which is pending from the interrupt ID register. This function provides +* priority resolution such that faster interrupt processing is possible. +* Without priority resolution, it is necessary for the software to read the +* interrupt pending register and then check each interrupt source to determine +* if an interrupt is pending. Priority resolution becomes more important as the +* number of interrupt sources becomes larger. +* +* Interrupt priorities are based upon the bit position of the interrupt in the +* interrupt pending register with bit 0 being the highest priority. The +* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the +* highest priority. The interrupt ID register is live rather than latched such +* that multiple calls to this function may not yield the same results. A +* special value, outside of the interrupt priority range of 0 - 31, is +* contained in the register which indicates that no interrupt is pending. This +* may be useful for allowing software to continue processing interrupts in a +* loop until there are no longer any interrupts pending. +* +* The interrupt ID is designed to allow a function pointer table to be used +* in the software such that the interrupt ID is used as an index into that +* table. The function pointer table could contain an instance pointer, such +* as to DMA channel, and a function pointer to the function which handles +* that interrupt. This design requires the interrupt processing of the device +* driver to be partitioned into smaller more granular pieces based upon +* hardware used by the device, such as DMA channels and FIFOs. +* +* It is not mandatory that this function be used by the device driver software. +* It may choose to read the pending register and resolve the pending interrupt +* priorities on it's own. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* An interrupt ID, 0 - 31, which identifies the highest priority interrupt +* which is pending. A value of XIIF_NO_INTERRUPT_ID indicates that there is +* no interrupt pending. The following values may be used to identify the +* interrupt ID for the internal IPIF interrupts. +* +* XIIF_V123B_ERROR_INTERRUPT_ID Indicates a device error in the IPIF +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_READ_DIIR(RegBaseAddress) \ + XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_GLOBAL_INTR_DISABLE +* +* DESCRIPTION: +* +* This function disables all interrupts for the device by writing to the global +* interrupt enable register. This register provides the ability to disable +* interrupts without any modifications to the interrupt enable register such +* that it is minimal effort to restore the interrupts to the previous enabled +* state. The corresponding function, XIpIf_GlobalIntrEnable, is provided to +* restore the interrupts to the previous enabled state. This function is +* designed to be used in critical sections of device drivers such that it is +* not necessary to disable other device interrupts. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \ + XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_GINTR_ENABLE +* +* DESCRIPTION: +* +* This function writes to the global interrupt enable register to enable +* interrupts from the device. This register provides the ability to enable +* interrupts without any modifications to the interrupt enable register such +* that it is minimal effort to restore the interrupts to the previous enabled +* state. This function does not enable individual interrupts as the interrupt +* enable register must be set appropriately. This function is designed to be +* used in critical sections of device drivers such that it is not necessary to +* disable other device interrupts. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress) \ + XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \ + XIIF_V123B_GINTR_ENABLE_MASK) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_IS_GINTR_ENABLED +* +* DESCRIPTION: +* +* This function determines if interrupts are enabled at the global level by +* reading the gloabl interrupt register. This register provides the ability to +* disable interrupts without any modifications to the interrupt enable register +* such that it is minimal effort to restore the interrupts to the previous +* enabled state. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise. +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress) \ + (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) == \ + XIIF_V123B_GINTR_ENABLE_MASK) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_WRITE_IISR +* +* DESCRIPTION: +* +* This function sets the IP interrupt status register to the specified value. +* This register indicates the status of interrupt sources for the IP of the +* device. The IP is defined as the part of the device that connects to the +* IPIF. The status is independent of whether interrupts are enabled such that +* the status register may also be polled when interrupts are not enabled. +* +* Each bit of the register correlates to a specific interrupt source within the +* IP. All bits of this register are latched. Setting a bit which is zero +* within this register causes an interrupt to be generated. The device global +* interrupt enable register and the device interrupt enable register must be set +* appropriately to allow an interrupt to be passed out of the device. The +* interrupt is cleared by writing to this register with the bits to be +* cleared set to a one and all others to zero. This register implements a +* toggle on write functionality meaning any bits which are set in the value +* written cause the bits in the register to change to the opposite state. +* +* This function writes only the specified value to the register such that +* some status bits may be set and others cleared. It is the caller's +* responsibility to get the value of the register prior to setting the value +* to prevent an destructive behavior. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* Status contains the value to be written to the IP interrupt status +* register. The bit definitions are specific to the device IP. +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \ + XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status)) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_READ_IISR +* +* DESCRIPTION: +* +* This function gets the contents of the IP interrupt status register. +* This register indicates the status of interrupt sources for the IP of the +* device. The IP is defined as the part of the device that connects to the +* IPIF. The status is independent of whether interrupts are enabled such +* that the status register may also be polled when interrupts are not enabled. +* +* Each bit of the register correlates to a specific interrupt source within the +* device. All bits of this register are latched. Writing a 1 to a bit within +* this register causes an interrupt to be generated if enabled in the interrupt +* enable register and the global interrupt enable is set. Since the status is +* latched, each status bit must be acknowledged in order for the bit in the +* status register to be updated. Each bit can be acknowledged by writing a +* 0 to the bit in the status register. + +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* A status which contains the value read from the IP interrupt status register. +* The bit definitions are specific to the device IP. +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_READ_IISR(RegBaseAddress) \ + XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_WRITE_IIER +* +* DESCRIPTION: +* +* This function sets the IP interrupt enable register contents. This register +* controls which interrupt sources of the IP are allowed to generate an +* interrupt. The global interrupt enable register and the device interrupt +* enable register must also be set appropriately for an interrupt to be +* passed out of the device containing the IPIF and the IP. +* +* Each bit of the register correlates to a specific interrupt source within the +* IP. Setting a bit in this register enables the interrupt source to generate +* an interrupt. Clearing a bit in this register disables interrupt generation +* for that interrupt source. +* +* This function writes only the specified value to the register such that +* some interrupt sources may be enabled and others disabled. It is the +* caller's responsibility to get the value of the interrupt enable register +* prior to setting the value to prevent an destructive behavior. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* Enable contains the value to be written to the IP interrupt enable register. +* The bit definitions are specific to the device IP. +* +* RETURN VALUE: +* +* None. +* +* NOTES: +* +* None. +* +******************************************************************************/ +#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \ + XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable)) + +/****************************************************************************** +* +* MACRO: +* +* XIIF_V123B_READ_IIER +* +* DESCRIPTION: +* +* +* This function gets the IP interrupt enable register contents. This register +* controls which interrupt sources of the IP are allowed to generate an +* interrupt. The global interrupt enable register and the device interrupt +* enable register must also be set appropriately for an interrupt to be +* passed out of the device containing the IPIF and the IP. +* +* Each bit of the register correlates to a specific interrupt source within the +* IP. Setting a bit in this register enables the interrupt source to generate +* an interrupt. Clearing a bit in this register disables interrupt generation +* for that interrupt source. +* +* ARGUMENTS: +* +* RegBaseAddress contains the base address of the IPIF registers. +* +* RETURN VALUE: +* +* The contents read from the IP interrupt enable register. The bit definitions +* are specific to the device IP. +* +* NOTES: +* +* Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress) +* +******************************************************************************/ +#define XIIF_V123B_READ_IIER(RegBaseAddress) \ + XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET) + +/************************** Function Prototypes ******************************/ + +/* + * Initialization Functions + */ +XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth); + +#endif /* end of protection macro */ diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.c b/board/xilinx/common/xpacket_fifo_v1_00_b.c new file mode 100644 index 0000000..ae2d6d4 --- /dev/null +++ b/board/xilinx/common/xpacket_fifo_v1_00_b.c @@ -0,0 +1,448 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/* +* +* @file xpacket_fifo_v1_00_b.c +* +* Contains functions for the XPacketFifoV100b component. See xpacket_fifo_v1_00_b.h +* for more information about the component. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm 03/26/02  First release
+*
+* +*****************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xio.h" +#include "xstatus.h" +#include "xpacket_fifo_v1_00_b.h" + +/************************** Constant Definitions *****************************/ + +/* width of a FIFO word */ + +#define XPF_FIFO_WIDTH_BYTE_COUNT 4UL + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************* Variable Definitions ******************************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/* +* +* This function initializes a packet FIFO. Initialization resets the +* FIFO such that it's empty and ready to use. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* @param RegBaseAddress contains the base address of the registers for +* the packet FIFO. +* @param DataBaseAddress contains the base address of the data for +* the packet FIFO. +* +* @return +* +* Always returns XST_SUCCESS. +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr, + u32 RegBaseAddress, u32 DataBaseAddress) +{ + /* assert to verify input argument are valid */ + + XASSERT_NONVOID(InstancePtr != NULL); + + /* initialize the component variables to the specified state */ + + InstancePtr->RegBaseAddress = RegBaseAddress; + InstancePtr->DataBaseAddress = DataBaseAddress; + InstancePtr->IsReady = XCOMPONENT_IS_READY; + + /* reset the FIFO such that it's empty and ready to use and indicate the + * initialization was successful, note that the is ready variable must be + * set prior to calling the reset function to prevent an assert + */ + XPF_V100B_RESET(InstancePtr); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/* +* +* This function performs a self-test on the specified packet FIFO. The self +* test resets the FIFO and reads a register to determine if it is the correct +* reset value. This test is destructive in that any data in the FIFO will +* be lost. +* +* @param InstancePtr is a pointer to the packet FIFO to be operated on. +* +* @param FifoType specifies the type of FIFO, read or write, for the self test. +* The FIFO type is specified by the values XPF_READ_FIFO_TYPE or +* XPF_WRITE_FIFO_TYPE. +* +* @return +* +* XST_SUCCESS is returned if the selftest is successful, or +* XST_PFIFO_BAD_REG_VALUE indicating that the value readback from the +* occupancy/vacancy count register after a reset does not match the +* specified reset value. +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType) +{ + u32 Register; + + /* assert to verify valid input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID((FifoType == XPF_READ_FIFO_TYPE) || + (FifoType == XPF_WRITE_FIFO_TYPE)); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* reset the fifo and then check to make sure the occupancy/vacancy + * register contents are correct for a reset condition + */ + XPF_V100B_RESET(InstancePtr); + + Register = XIo_In32(InstancePtr->RegBaseAddress + + XPF_COUNT_STATUS_REG_OFFSET); + + /* check the value of the register to ensure that it's correct for the + * specified FIFO type since both FIFO types reset to empty, but a bit + * in the register changes definition based upon FIFO type + */ + + if (FifoType == XPF_READ_FIFO_TYPE) { + /* check the regiser value for a read FIFO which should be empty */ + + if (Register != XPF_EMPTY_FULL_MASK) { + return XST_PFIFO_BAD_REG_VALUE; + } + } else { + /* check the register value for a write FIFO which should not be full + * on reset + */ + if ((Register & XPF_EMPTY_FULL_MASK) != 0) { + return XST_PFIFO_BAD_REG_VALUE; + } + } + + /* the test was successful */ + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/* +* +* Read data from a FIFO and puts it into a specified buffer. The packet FIFO is +* currently 32 bits wide such that an input buffer which is a series of bytes +* is filled from the FIFO a word at a time. If the requested byte count is not +* a multiple of 32 bit words, it is necessary for this function to format the +* remaining 32 bit word from the FIFO into a series of bytes in the buffer. +* There may be up to 3 extra bytes which must be extracted from the last word +* of the FIFO and put into the buffer. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* @param BufferPtr points to the memory buffer to write the data into. This +* buffer must be 32 bit aligned or an alignment exception could be +* generated. Since this buffer is a byte buffer, the data is assumed to +* be endian independent. +* @param ByteCount contains the number of bytes to read from the FIFO. This +* number of bytes must be present in the FIFO or an error will be +* returned. +* +* @return +* +* XST_SUCCESS indicates the operation was successful. If the number of +* bytes specified by the byte count is not present in the FIFO +* XST_PFIFO_LACK_OF_DATA is returned. +* +* If the function was successful, the specified buffer is modified to contain +* the bytes which were removed from the FIFO. +* +* @note +* +* Note that the exact number of bytes which are present in the FIFO is +* not known by this function. It can only check for a number of 32 bit +* words such that if the byte count specified is incorrect, but is still +* possible based on the number of words in the FIFO, up to 3 garbage bytes +* may be present at the end of the buffer. +*

+* This function assumes that if the device consuming data from the FIFO is +* a byte device, the order of the bytes to be consumed is from the most +* significant byte to the least significant byte of a 32 bit word removed +* from the FIFO. +* +******************************************************************************/ +XStatus +XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr, + u8 * BufferPtr, u32 ByteCount) +{ + u32 FifoCount; + u32 WordCount; + u32 ExtraByteCount; + u32 *WordBuffer = (u32 *) BufferPtr; + + /* assert to verify valid input arguments including 32 bit alignment of + * the buffer pointer + */ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(BufferPtr != NULL); + XASSERT_NONVOID(((u32) BufferPtr & + (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0); + XASSERT_NONVOID(ByteCount != 0); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* get the count of how many 32 bit words are in the FIFO, if there aren't + * enought words to satisfy the request, return an error + */ + + FifoCount = XIo_In32(InstancePtr->RegBaseAddress + + XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; + + if ((FifoCount * XPF_FIFO_WIDTH_BYTE_COUNT) < ByteCount) { + return XST_PFIFO_LACK_OF_DATA; + } + + /* calculate the number of words to read from the FIFO before the word + * containing the extra bytes, and calculate the number of extra bytes + * the extra bytes are defined as those at the end of the buffer when + * the buffer does not end on a 32 bit boundary + */ + WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT; + ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT; + + /* Read the 32 bit words from the FIFO for all the buffer except the + * last word which contains the extra bytes, the following code assumes + * that the buffer is 32 bit aligned, otherwise an alignment exception could + * be generated + */ + for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { + WordBuffer[FifoCount] = XIo_In32(InstancePtr->DataBaseAddress); + } + + /* if there are extra bytes to handle, read the last word from the FIFO + * and insert the extra bytes into the buffer + */ + if (ExtraByteCount > 0) { + u32 LastWord; + u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount); + + /* get the last word from the FIFO for the extra bytes */ + + LastWord = XIo_In32(InstancePtr->DataBaseAddress); + + /* one extra byte in the last word, put the byte into the next location + * of the buffer, bytes in a word of the FIFO are ordered from most + * significant byte to least + */ + if (ExtraByteCount == 1) { + ExtraBytesBuffer[0] = (u8) (LastWord >> 24); + } + + /* two extra bytes in the last word, put each byte into the next two + * locations of the buffer + */ + else if (ExtraByteCount == 2) { + ExtraBytesBuffer[0] = (u8) (LastWord >> 24); + ExtraBytesBuffer[1] = (u8) (LastWord >> 16); + } + /* three extra bytes in the last word, put each byte into the next three + * locations of the buffer + */ + else if (ExtraByteCount == 3) { + ExtraBytesBuffer[0] = (u8) (LastWord >> 24); + ExtraBytesBuffer[1] = (u8) (LastWord >> 16); + ExtraBytesBuffer[2] = (u8) (LastWord >> 8); + } + } + return XST_SUCCESS; +} + +/*****************************************************************************/ +/* +* +* Write data into a packet FIFO. The packet FIFO is currently 32 bits wide +* such that an input buffer which is a series of bytes must be written into the +* FIFO a word at a time. If the buffer is not a multiple of 32 bit words, it is +* necessary for this function to format the remaining bytes into a single 32 +* bit word to be inserted into the FIFO. This is necessary to avoid any +* accesses past the end of the buffer. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* @param BufferPtr points to the memory buffer that data is to be read from +* and written into the FIFO. Since this buffer is a byte buffer, the data +* is assumed to be endian independent. This buffer must be 32 bit aligned +* or an alignment exception could be generated. +* @param ByteCount contains the number of bytes to read from the buffer and to +* write to the FIFO. +* +* @return +* +* XST_SUCCESS is returned if the operation succeeded. If there is not enough +* room in the FIFO to hold the specified bytes, XST_PFIFO_NO_ROOM is +* returned. +* +* @note +* +* This function assumes that if the device inserting data into the FIFO is +* a byte device, the order of the bytes in each 32 bit word is from the most +* significant byte to the least significant byte. +* +******************************************************************************/ +XStatus +XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr, + u8 * BufferPtr, u32 ByteCount) +{ + u32 FifoCount; + u32 WordCount; + u32 ExtraByteCount; + u32 *WordBuffer = (u32 *) BufferPtr; + + /* assert to verify valid input arguments including 32 bit alignment of + * the buffer pointer + */ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(BufferPtr != NULL); + XASSERT_NONVOID(((u32) BufferPtr & + (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0); + XASSERT_NONVOID(ByteCount != 0); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* get the count of how many words may be inserted into the FIFO */ + + FifoCount = XIo_In32(InstancePtr->RegBaseAddress + + XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; + + /* Calculate the number of 32 bit words required to insert the specified + * number of bytes in the FIFO and determine the number of extra bytes + * if the buffer length is not a multiple of 32 bit words + */ + + WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT; + ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT; + + /* take into account the extra bytes in the total word count */ + + if (ExtraByteCount > 0) { + WordCount++; + } + + /* if there's not enough room in the FIFO to hold the specified + * number of bytes, then indicate an error, + */ + if (FifoCount < WordCount) { + return XST_PFIFO_NO_ROOM; + } + + /* readjust the word count to not take into account the extra bytes */ + + if (ExtraByteCount > 0) { + WordCount--; + } + + /* Write all the bytes of the buffer which can be written as 32 bit + * words into the FIFO, waiting to handle the extra bytes seperately + */ + for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { + XIo_Out32(InstancePtr->DataBaseAddress, WordBuffer[FifoCount]); + } + + /* if there are extra bytes to handle, extract them from the buffer + * and create a 32 bit word and write it to the FIFO + */ + if (ExtraByteCount > 0) { + u32 LastWord = 0; + u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount); + + /* one extra byte in the buffer, put the byte into the last word + * to be inserted into the FIFO, perform this processing inline rather + * than in a loop to help performance + */ + if (ExtraByteCount == 1) { + LastWord = ExtraBytesBuffer[0] << 24; + } + + /* two extra bytes in the buffer, put each byte into the last word + * to be inserted into the FIFO + */ + else if (ExtraByteCount == 2) { + LastWord = ExtraBytesBuffer[0] << 24 | + ExtraBytesBuffer[1] << 16; + } + + /* three extra bytes in the buffer, put each byte into the last word + * to be inserted into the FIFO + */ + else if (ExtraByteCount == 3) { + LastWord = ExtraBytesBuffer[0] << 24 | + ExtraBytesBuffer[1] << 16 | + ExtraBytesBuffer[2] << 8; + } + + /* write the last 32 bit word to the FIFO and return with no errors */ + + XIo_Out32(InstancePtr->DataBaseAddress, LastWord); + } + + return XST_SUCCESS; +} diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.h b/board/xilinx/common/xpacket_fifo_v1_00_b.h new file mode 100644 index 0000000..1cda0e8 --- /dev/null +++ b/board/xilinx/common/xpacket_fifo_v1_00_b.h @@ -0,0 +1,306 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/* +* +* @file xpacket_fifo_v1_00_b.h +* +* This component is a common component because it's primary purpose is to +* prevent code duplication in drivers. A driver which must handle a packet +* FIFO uses this component rather than directly manipulating a packet FIFO. +* +* A FIFO is a device which has dual port memory such that one user may be +* inserting data into the FIFO while another is consuming data from the FIFO. +* A packet FIFO is designed for use with packet protocols such as Ethernet and +* ATM. It is typically only used with devices when DMA and/or Scatter Gather +* is used. It differs from a nonpacket FIFO in that it does not provide any +* interrupts for thresholds of the FIFO such that it is less useful without +* DMA. +* +* @note +* +* This component has the capability to generate an interrupt when an error +* condition occurs. It is the user's responsibility to provide the interrupt +* processing to handle the interrupt. This component provides the ability to +* determine if that interrupt is active, a deadlock condition, and the ability +* to reset the FIFO to clear the condition. In this condition, the device which +* is using the FIFO should also be reset to prevent other problems. This error +* condition could occur as a normal part of operation if the size of the FIFO +* is not setup correctly. See the hardware IP specification for more details. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm 03/26/02  First release
+*
+* +*****************************************************************************/ +#ifndef XPACKET_FIFO_H /* prevent circular inclusions */ +#define XPACKET_FIFO_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/* + * These constants specify the FIFO type and are mutually exclusive + */ +#define XPF_READ_FIFO_TYPE 0 /* a read FIFO */ +#define XPF_WRITE_FIFO_TYPE 1 /* a write FIFO */ + +/* + * These constants define the offsets to each of the registers from the + * register base address, each of the constants are a number of bytes + */ +#define XPF_RESET_REG_OFFSET 0UL +#define XPF_MODULE_INFO_REG_OFFSET 0UL +#define XPF_COUNT_STATUS_REG_OFFSET 4UL + +/* + * This constant is used with the Reset Register + */ +#define XPF_RESET_FIFO_MASK 0x0000000A + +/* + * These constants are used with the Occupancy/Vacancy Count Register. This + * register also contains FIFO status + */ +#define XPF_COUNT_MASK 0x0000FFFF +#define XPF_DEADLOCK_MASK 0x20000000 +#define XPF_ALMOST_EMPTY_FULL_MASK 0x40000000 +#define XPF_EMPTY_FULL_MASK 0x80000000 + +/**************************** Type Definitions *******************************/ + +/* + * The XPacketFifo driver instance data. The driver is required to allocate a + * variable of this type for every packet FIFO in the device. + */ +typedef struct { + u32 RegBaseAddress; /* Base address of registers */ + u32 IsReady; /* Device is initialized and ready */ + u32 DataBaseAddress; /* Base address of data for FIFOs */ +} XPacketFifoV100b; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/* +* +* Reset the specified packet FIFO. Resetting a FIFO will cause any data +* contained in the FIFO to be lost. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* +* @return +* +* None. +* +* @note +* +* Signature: void XPF_V100B_RESET(XPacketFifoV100b *InstancePtr) +* +******************************************************************************/ +#define XPF_V100B_RESET(InstancePtr) \ + XIo_Out32((InstancePtr)->RegBaseAddress + XPF_RESET_REG_OFFSET, XPF_RESET_FIFO_MASK); + +/*****************************************************************************/ +/* +* +* Get the occupancy count for a read packet FIFO and the vacancy count for a +* write packet FIFO. These counts indicate the number of 32-bit words +* contained (occupancy) in the FIFO or the number of 32-bit words available +* to write (vacancy) in the FIFO. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* +* @return +* +* The occupancy or vacancy count for the specified packet FIFO. +* +* @note +* +* Signature: u32 XPF_V100B_GET_COUNT(XPacketFifoV100b *InstancePtr) +* +******************************************************************************/ +#define XPF_V100B_GET_COUNT(InstancePtr) \ + (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ + XPF_COUNT_MASK) + +/*****************************************************************************/ +/* +* +* Determine if the specified packet FIFO is almost empty. Almost empty is +* defined for a read FIFO when there is only one data word in the FIFO. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* +* @return +* +* TRUE if the packet FIFO is almost empty, FALSE otherwise. +* +* @note +* +* Signature: u32 XPF_V100B_IS_ALMOST_EMPTY(XPacketFifoV100b *InstancePtr) +* +******************************************************************************/ +#define XPF_V100B_IS_ALMOST_EMPTY(InstancePtr) \ + (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ + XPF_ALMOST_EMPTY_FULL_MASK) + +/*****************************************************************************/ +/* +* +* Determine if the specified packet FIFO is almost full. Almost full is +* defined for a write FIFO when there is only one available data word in the +* FIFO. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* +* @return +* +* TRUE if the packet FIFO is almost full, FALSE otherwise. +* +* @note +* +* Signature: u32 XPF_V100B_IS_ALMOST_FULL(XPacketFifoV100b *InstancePtr) +* +******************************************************************************/ +#define XPF_V100B_IS_ALMOST_FULL(InstancePtr) \ + (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ + XPF_ALMOST_EMPTY_FULL_MASK) + +/*****************************************************************************/ +/* +* +* Determine if the specified packet FIFO is empty. This applies only to a +* read FIFO. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* +* @return +* +* TRUE if the packet FIFO is empty, FALSE otherwise. +* +* @note +* +* Signature: u32 XPF_V100B_IS_EMPTY(XPacketFifoV100b *InstancePtr) +* +******************************************************************************/ +#define XPF_V100B_IS_EMPTY(InstancePtr) \ + (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ + XPF_EMPTY_FULL_MASK) + +/*****************************************************************************/ +/* +* +* Determine if the specified packet FIFO is full. This applies only to a +* write FIFO. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* +* @return +* +* TRUE if the packet FIFO is full, FALSE otherwise. +* +* @note +* +* Signature: u32 XPF_V100B_IS_FULL(XPacketFifoV100b *InstancePtr) +* +******************************************************************************/ +#define XPF_V100B_IS_FULL(InstancePtr) \ + (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ + XPF_EMPTY_FULL_MASK) + +/*****************************************************************************/ +/* +* +* Determine if the specified packet FIFO is deadlocked. This condition occurs +* when the FIFO is full and empty at the same time and is caused by a packet +* being written to the FIFO which exceeds the total data capacity of the FIFO. +* It occurs because of the mark/restore features of the packet FIFO which allow +* retransmission of a packet. The software should reset the FIFO and any devices +* using the FIFO when this condition occurs. +* +* @param InstancePtr contains a pointer to the FIFO to operate on. +* +* @return +* +* TRUE if the packet FIFO is deadlocked, FALSE otherwise. +* +* @note +* +* This component has the capability to generate an interrupt when an error +* condition occurs. It is the user's responsibility to provide the interrupt +* processing to handle the interrupt. This function provides the ability to +* determine if a deadlock condition, and the ability to reset the FIFO to +* clear the condition. +* +* In this condition, the device which is using the FIFO should also be reset +* to prevent other problems. This error condition could occur as a normal part +* of operation if the size of the FIFO is not setup correctly. +* +* Signature: u32 XPF_V100B_IS_DEADLOCKED(XPacketFifoV100b *InstancePtr) +* +******************************************************************************/ +#define XPF_V100B_IS_DEADLOCKED(InstancePtr) \ + (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ + XPF_DEADLOCK_MASK) + +/************************** Function Prototypes ******************************/ + +/* Standard functions */ + +XStatus XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr, + u32 RegBaseAddress, u32 DataBaseAddress); +XStatus XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType); + +/* Data functions */ + +XStatus XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr, + u8 * ReadBufferPtr, u32 ByteCount); +XStatus XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr, + u8 * WriteBufferPtr, u32 ByteCount); + +#endif /* end of protection macro */ diff --git a/board/xilinx/common/xstatus.h b/board/xilinx/common/xstatus.h new file mode 100644 index 0000000..ffda4d7 --- /dev/null +++ b/board/xilinx/common/xstatus.h @@ -0,0 +1,347 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* This file contains Xilinx software status codes. Status codes have their +* own data type called XStatus. These codes are used throughout the Xilinx +* device drivers. +* +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ + +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /* an error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /* an error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /* a DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /* the device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /* there was no data available */ +#define XST_REGISTER_ERROR 14L /* a register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /* an invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /* the device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ +#define XST_NO_CALLBACK 18L /* a callback has not yet been + * registered */ +#define XST_NO_FEATURE 19L /* device is not configured with + * the requested feature */ +#define XST_NOT_INTERRUPT 20L /* device is not configured for + * interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /* device is busy */ +#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device + * have maxed out */ +#define XST_IS_STARTED 23L /* used when part of device is + * already started i.e. + * sub channel */ +#define XST_IS_STOPPED 24L /* used when part of device is + * already stopped i.e. + * sub channel */ + +/***************** Utility Component statuses 401 - 500 *********************/ + +#define XST_MEMTEST_FAILED 401L /* memory test failed */ + +/***************** Common Components statuses 501 - 1000 *********************/ + +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value + was invalid after reset */ + +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ + +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register + did not indicate the expected + value */ + +/****************** Device specific statuses 1001 - 4095 *********************/ + +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ +#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Adapter is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /* Invalid adapter init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late + * collision on polled send */ + +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ +#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ + +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ + +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming */ +#define XST_FLASH_READY 1127L /* Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /* Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ + +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ + +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ + +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ + +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ + +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L + +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L + +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L + +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L + +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ + +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L + +/**************************** Type Definitions *******************************/ + +/** + * The status typedef. + */ +typedef u32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +#endif /* end of protection macro */ diff --git a/board/xilinx/common/xversion.c b/board/xilinx/common/xversion.c new file mode 100644 index 0000000..c8a6915 --- /dev/null +++ b/board/xilinx/common/xversion.c @@ -0,0 +1,350 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/***************************************************************************** +* +* This file contains the implementation of the XVersion component. This +* component represents a version ID. It is encapsulated within a component +* so that it's type and implementation can change without affecting users of +* it. +* +* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z +* X is the major revision, YY is the minor revision, and Z is the +* compatability revision. +* +* Packed versions are also utilized for the configuration ROM such that +* memory is minimized. A packed version consumes only 16 bits and is +* formatted as follows. +* +* 
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xversion.h" + +/************************** Constant Definitions *****************************/ + +/* the following constants define the masks and shift values to allow the + * revisions to be packed and unpacked, a packed version is packed into a 16 + * bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the + * major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability + * revision + */ +#define XVE_MAJOR_SHIFT_VALUE 12 +#define XVE_MINOR_ONLY_MASK 0x0FE0 +#define XVE_MINOR_SHIFT_VALUE 5 +#define XVE_COMP_ONLY_MASK 0x001F + +/* the following constants define the specific characters of a version string + * for each character of the revision, a version string is in the following + * format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor + * revision (00 - 99), and Z is the compatability revision (a - z) + */ +#define XVE_MAJOR_CHAR 0 /* major revision 0 - 9 */ +#define XVE_MINOR_TENS_CHAR 2 /* minor revision tens 0 - 9 */ +#define XVE_MINOR_ONES_CHAR 3 /* minor revision ones 0 - 9 */ +#define XVE_COMP_CHAR 4 /* compatability revision a - z */ +#define XVE_END_STRING_CHAR 5 + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +static u32 IsVersionStringValid(s8 * StringPtr); + +/***************************************************************************** +* +* Unpacks a packed version into the specified version. Versions are packed +* into the configuration ROM to reduce the amount storage. A packed version +* is a binary format as oppossed to a non-packed version which is implemented +* as a string. +* +* @param InstancePtr points to the version to unpack the packed version into. +* @param PackedVersion contains the packed version to unpack. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void +XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion) +{ + /* not implemented yet since CROM related */ +} + +/***************************************************************************** +* +* Packs a version into the specified packed version. Versions are packed into +* the configuration ROM to reduce the amount storage. +* +* @param InstancePtr points to the version to pack. +* @param PackedVersionPtr points to the packed version which will receive +* the new packed version. +* +* @return +* +* A status, XST_SUCCESS, indicating the packing was accomplished +* successfully, or an error, XST_INVALID_VERSION, indicating the specified +* input version was not valid such that the pack did not occur +*

+* The packed version pointed to by PackedVersionPtr is modified with the new +* packed version if the status indicates success. +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersionPtr) +{ + /* not implemented yet since CROM related */ + + return XST_SUCCESS; +} + +/***************************************************************************** +* +* Determines if two versions are equal. +* +* @param InstancePtr points to the first version to be compared. +* @param VersionPtr points to a second version to be compared. +* +* @return +* +* TRUE if the versions are equal, FALSE otherwise. +* +* @note +* +* None. +* +******************************************************************************/ +u32 +XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr) +{ + u8 *Version1 = (u8 *) InstancePtr; + u8 *Version2 = (u8 *) VersionPtr; + int Index; + + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(VersionPtr != NULL); + + /* check each byte of the versions to see if they are the same, + * return at any point a byte differs between them + */ + for (Index = 0; Index < sizeof (XVersion); Index++) { + if (Version1[Index] != Version2[Index]) { + return FALSE; + } + } + + /* No byte was found to be different between the versions, so indicate + * the versions are equal + */ + return TRUE; +} + +/***************************************************************************** +* +* Converts a version to a null terminated string. +* +* @param InstancePtr points to the version to convert. +* @param StringPtr points to the string which will be the result of the +* conversion. This does not need to point to a null terminated +* string as an input, but must point to storage which is an adequate +* amount to hold the result string. +* +* @return +* +* The null terminated string is inserted at the location pointed to by +* StringPtr if the status indicates success. +* +* @note +* +* It is necessary for the caller to have already allocated the storage to +* contain the string. The amount of memory necessary for the string is +* specified in the version header file. +* +******************************************************************************/ +void +XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr) +{ + /* assert to verify input arguments */ + + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(StringPtr != NULL); + + /* since version is implemented as a string, just copy the specified + * input into the specified output + */ + XVersion_Copy(InstancePtr, (XVersion *) StringPtr); +} + +/***************************************************************************** +* +* Initializes a version from a null terminated string. Since the string may not +* be a format which is compatible with the version, an error could occur. +* +* @param InstancePtr points to the version which is to be initialized. +* @param StringPtr points to a null terminated string which will be +* converted to a version. The format of the string must match the +* version string format which is X.YYX where X = 0 - 9, YY = 00 - 99, +* Z = a - z. +* +* @return +* +* A status, XST_SUCCESS, indicating the conversion was accomplished +* successfully, or XST_INVALID_VERSION indicating the version string format +* was not valid. +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr) +{ + /* assert to verify input arguments */ + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(StringPtr != NULL); + + /* if the version string specified is not valid, return an error */ + + if (!IsVersionStringValid(StringPtr)) { + return XST_INVALID_VERSION; + } + + /* copy the specified string into the specified version and indicate the + * conversion was successful + */ + XVersion_Copy((XVersion *) StringPtr, InstancePtr); + + return XST_SUCCESS; +} + +/***************************************************************************** +* +* Copies the contents of a version to another version. +* +* @param InstancePtr points to the version which is the source of data for +* the copy operation. +* @param VersionPtr points to another version which is the destination of +* the copy operation. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void +XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr) +{ + u8 *Source = (u8 *) InstancePtr; + u8 *Destination = (u8 *) VersionPtr; + int Index; + + /* assert to verify input arguments */ + + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(VersionPtr != NULL); + + /* copy each byte of the source version to the destination version */ + + for (Index = 0; Index < sizeof (XVersion); Index++) { + Destination[Index] = Source[Index]; + } +} + +/***************************************************************************** +* +* Determines if the specified version is valid. +* +* @param StringPtr points to the string to be validated. +* +* @return +* +* TRUE if the version string is a valid format, FALSE otherwise. +* +* @note +* +* None. +* +******************************************************************************/ +static u32 +IsVersionStringValid(s8 * StringPtr) +{ + /* if the input string is not a valid format, "X.YYZ" where X = 0 - 9, + * YY = 00 - 99, and Z = a - z, then indicate it's not valid + */ + if ((StringPtr[XVE_MAJOR_CHAR] < '0') || + (StringPtr[XVE_MAJOR_CHAR] > '9') || + (StringPtr[XVE_MINOR_TENS_CHAR] < '0') || + (StringPtr[XVE_MINOR_TENS_CHAR] > '9') || + (StringPtr[XVE_MINOR_ONES_CHAR] < '0') || + (StringPtr[XVE_MINOR_ONES_CHAR] > '9') || + (StringPtr[XVE_COMP_CHAR] < 'a') || + (StringPtr[XVE_COMP_CHAR] > 'z')) { + return FALSE; + } + + return TRUE; +} diff --git a/board/xilinx/common/xversion.h b/board/xilinx/common/xversion.h new file mode 100644 index 0000000..17f9da7 --- /dev/null +++ b/board/xilinx/common/xversion.h @@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/***************************************************************************** +* +* This file contains the interface for the XVersion component. This +* component represents a version ID. It is encapsulated within a component +* so that it's type and implementation can change without affecting users of +* it. +* +* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z +* X is the major revision, YY is the minor revision, and Z is the +* compatability revision. +* +* Packed versions are also utilized for the configuration ROM such that +* memory is minimized. A packed version consumes only 16 bits and is +* formatted as follows. +* +* 
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+*
+* +******************************************************************************/ + +#ifndef XVERSION_H /* prevent circular inclusions */ +#define XVERSION_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/* the following data type is used to hold a null terminated version string + * consisting of the following format, "X.YYX" + */ +typedef s8 XVersion[6]; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +void XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion); + +XStatus XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersion); + +u32 XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr); + +void XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr); + +XStatus XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr); + +void XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr); + +#endif /* end of protection macro */ diff --git a/board/xilinx/ml300/Makefile b/board/xilinx/ml300/Makefile new file mode 100644 index 0000000..880c494 --- /dev/null +++ b/board/xilinx/ml300/Makefile @@ -0,0 +1,58 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +CFLAGS += -I../ml300 -I../common -I../xilinx_enet -I../xilinx_iic + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o \ + serial.o \ + ../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \ + ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \ + ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \ + ../xilinx_enet/xemac_intr_dma.o ../xilinx_iic/iic_adapter.o \ + ../xilinx_iic/xiic_l.o ../common/xipif_v1_23_b.o \ + ../common/xbasic_types.o ../common/xdma_channel.o \ + ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \ + ../common/xversion.o \ + +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/xilinx/ml300/config.mk b/board/xilinx/ml300/config.mk new file mode 100644 index 0000000..57ddb2f --- /dev/null +++ b/board/xilinx/ml300/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 +TEXT_BASE = 0x04000000 diff --git a/board/xilinx/ml300/init.S b/board/xilinx/ml300/init.S new file mode 100644 index 0000000..f753df8 --- /dev/null +++ b/board/xilinx/ml300/init.S @@ -0,0 +1,48 @@ +/* + * init.S: Stubs for U-Boot initialization + * + * Author: Xilinx, Inc. + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, + * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE + * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING + * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY + * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM + * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * + * Xilinx hardware products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * + * (c) Copyright 2002-2004 Xilinx Inc. + * All rights reserved. + * + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + */ + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + blr + + .globl sdram_init +sdram_init: + blr diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c new file mode 100644 index 0000000..dad562f --- /dev/null +++ b/board/xilinx/ml300/ml300.c @@ -0,0 +1,128 @@ +/* + * ml300.c: U-Boot platform support for Xilinx ML300 board + * + * Author: Xilinx, Inc. + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, + * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE + * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING + * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY + * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM + * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * + * Xilinx hardware products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * + * (c) Copyright 2002-2004 Xilinx Inc. + * All rights reserved. + * + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include "xparameters.h" + +#ifdef CFG_ENV_IS_IN_EEPROM +extern void convert_env(void); +#endif + +int +board_pre_init(void) +{ + return 0; +} + +int +checkboard(void) +{ + char tmp[64]; /* long enough for environment variables */ + char *s, *e; + int i = getenv_r("L", tmp, sizeof (tmp)); + + if (i < 0) { + printf("### No HW ID - assuming ML300"); + } else { + for (e = tmp; *e; ++e) { + if (*e == ' ') + break; + } + + printf("### Board Serial# is "); + + for (s = tmp; s < e; ++s) { + putc(*s); + } + + } + putc('\n'); + + return (0); +} + +long int +initdram(int board_type) +{ + return 128 * 1024 * 1024; +} + +int +testdram(void) +{ + printf("test: xxx MB - ok\n"); + + return (0); +} + +/* implement functions originally in cpu/ppc4xx/speed.c */ +void +get_sys_info(sys_info_t * sysInfo) +{ + sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + + /* only correct if the PLB and OPB run at the same frequency */ + sysInfo->freqPLB = XPAR_UARTNS550_0_CLOCK_FREQ_HZ; + sysInfo->freqPCI = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 3; +} + +ulong +get_PCI_freq(void) +{ + ulong val; + PPC405_SYS_INFO sys_info; + + get_sys_info(&sys_info); + val = sys_info.freqPCI; + return val; +} + +#ifdef CONFIG_MISC_INIT_R + +int +misc_init_r() +{ + /* convert env name and value to u-boot standard */ + convert_env(); + return 0; +} + +#endif diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c new file mode 100644 index 0000000..19bcc6f --- /dev/null +++ b/board/xilinx/ml300/serial.c @@ -0,0 +1,155 @@ +/* + * Author: Xilinx, Inc. + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, + * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE + * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING + * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY + * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM + * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * + * Xilinx hardware products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * + * (c) Copyright 2002-2004 Xilinx Inc. + * All rights reserved. + * + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include "xparameters.h" + +#define USE_CHAN1 \ + ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CFG_INIT_CHAN1)) +#define USE_CHAN2 \ + ((defined XPAR_UARTNS550_1_BASEADDR) && (defined CFG_INIT_CHAN2)) + +#if USE_CHAN1 +#include +#endif + +#if USE_CHAN1 +const NS16550_t COM_PORTS[] = { (NS16550_t) (XPAR_UARTNS550_0_BASEADDR + 3) +#if USE_CHAN2 + , (NS16550_t) (XPAR_UARTNS550_1_BASEADDR + 3) +#endif +}; +#endif + +int +serial_init(void) +{ +#if USE_CHAN1 + DECLARE_GLOBAL_DATA_PTR; + int clock_divisor; + + clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; + (void) NS16550_init(COM_PORTS[0], clock_divisor); +#if USE_CHAN2 + clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; + (void) NS16550_init(COM_PORTS[1], clock_divisor); +#endif +#endif + return 0; + +} + +void +serial_putc(const char c) +{ + if (c == '\n') + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); + + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); +} + +int +serial_getc(void) +{ + return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); +} + +int +serial_tstc(void) +{ + return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); +} + +void +serial_setbrg(void) +{ +#if USE_CHAN1 + DECLARE_GLOBAL_DATA_PTR; + int clock_divisor; + + clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; + NS16550_reinit(COM_PORTS[0], clock_divisor); +#if USE_CHAN2 + clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; + NS16550_reinit(COM_PORTS[1], clock_divisor); +#endif +#endif +} + +void +serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +void +kgdb_serial_init(void) +{ +} + +void +putDebugChar(int c) +{ + serial_putc(c); +} + +void +putDebugStr(const char *str) +{ + serial_puts(str); +} + +int +getDebugChar(void) +{ + return serial_getc(); +} + +void +kgdb_interruptible(int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes new file mode 100644 index 0000000..9daf147 --- /dev/null +++ b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes @@ -0,0 +1,55 @@ +#!/bin/bash + +if [ $# -ne 1 ] +then + echo "usage: Ltypes filename" >&2 + exit 2 +fi + +FILE="$1" +#TMPFILE='mktemp "${FILE}.XXXXXX"' || exit 1 +TMPFILE=${FILE}.`date "+%s"` +touch $TMPFILE || exit 1 + +# Change all the Xilinx types to Linux types and put the result into a temp file +sed \ + -e 's/\bXTRUE\b/TRUE/g' \ + -e 's/\bXFALSE\b/FALSE/g' \ + -e 's/\bXNULL\b/NULL/g' \ + -e 's/"xenv.h"//g' \ + -e 's/\bXENV_USLEEP\b/udelay/g' \ + -e 's/\bXuint8\b/u8/g' \ + -e 's/\bXuint16\b/u16/g' \ + -e 's/\bXuint32\b/u32/g' \ + -e 's/\bXint8\b/s8/g' \ + -e 's/\bXint16\b/s16/g' \ + -e 's/\bXint32\b/s32/g' \ + -e 's/\bXboolean\b/u32/g' \ + "${FILE}" > "${TMPFILE}" + +# Overlay the original file with the temp file +mv "${TMPFILE}" "${FILE}" + +# Are we doing xbasic_types.h? +if [ "${FILE##*/}" = xbasic_types.h ] +then + # Remember as you're reading this that we've already gone through the prior + # sed script. We need to do some other things to xbasic_types.h: + # 1) Add ifndefs around TRUE and FALSE defines + # 2) Remove definition of NULL as NULL + # 3) Replace most of the primitive types section with a #include + sed \ + -e '/u32 true/,/#define false/Ic\ +#ifndef TRUE\ +#define TRUE 1\ +#endif\ +#ifndef FALSE\ +#define FALSE 0\ +#endif' \ + -e '/#define[[:space:]][[:space:]]*NULL[[:space:]][[:space:]]*NULL/d' \ + -e '/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*char[[:space:]][[:space:]]*u8/,/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*long[[:space:]][[:space:]]*u32.*boolean/c\ +#include ' \ + "${FILE}" > "${TMPFILE}" + + mv "${TMPFILE}" "${FILE}" +fi diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld new file mode 100644 index 0000000..5169241 --- /dev/null +++ b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld @@ -0,0 +1,52 @@ +# (c) Copyright 2004 Xilinx Inc. +# Author: Xilinx, Inc. +# +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the +# Free Software Foundation; either version 2 of the License, or (at your +# option) any later version. +# +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +# XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +# FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +# ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +# WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +# CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +# FITNESS FOR A PARTICULAR PURPOSE. +# +# +# Xilinx hardware products are not intended for use in life support +# appliances, devices, or systems. Use in such applications is +# expressly prohibited. +# +# +# (c) Copyright 2002-2004 Xilinx Inc. +# All rights reserved. +# +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 675 Mass Ave, Cambridge, MA 02139, USA. + +OPTION psf_version = 2.1; + +BEGIN LIBRARY uboot OPTION DRC = uboot_drc; + +BEGIN ARRAY connected_periphs PROPERTY desc = "Peripherals connected to U-Boot"; +PROPERTY size = 0; +PARAM name = periph_name, desc = "Name of Peripheral connected", type = string; +END ARRAY + PARAMETER name = TARGET_DIR, desc = "Target Directory for U-Boot BSP", type = string; + +# location of persistent storage in the IIC EEPROM (defaults are set for ML300) +PARAMETER name = IIC_PERSISTENT_BASEADDR, desc = "Start of persistent storage block in the EEPROM address space", type = int, default = 1024; +PARAMETER name = IIC_PERSISTENT_HIGHADDR, desc = "End of persistent storage block in the EEPROM address space", type = int, default = 2047; +PARAMETER name = IIC_PERSISTENT_EEPROMADDR, desc = "Address of the EEPROM on the IIC bus", type = int, default = 0xA0; + +END LIBRARY diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl new file mode 100644 index 0000000..9d44f44 --- /dev/null +++ b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl @@ -0,0 +1,325 @@ +# +# Author: Xilinx, Inc. +# +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the +# Free Software Foundation; either version 2 of the License, or (at your +# option) any later version. +# +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +# XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +# FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +# ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +# WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +# CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +# FITNESS FOR A PARTICULAR PURPOSE. +# +# +# Xilinx hardware products are not intended for use in life support +# appliances, devices, or systems. Use in such applications is +# expressly prohibited. +# +# +# (c) Copyright 2002-2004 Xilinx Inc. +# All rights reserved. +# +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Globals +lappend drvlist +set ltypes "../../../sw_services/uboot_v1_00_a/data/Ltypes" + +proc uboot_drc {lib_handle} { + puts "U-Boot DRC..." +} + +proc generate {libname} { + + global drvlist + + # Get list of peripherals connected to uboot + set conn_periphs [xget_handle $libname "ARRAY" "connected_periphs"] + #lappend drvlist + if {[string compare -nocase $conn_periphs ""] != 0} { + set conn_periphs_elems [xget_handle $conn_periphs "ELEMENTS" "*"] + # For each periph + foreach periph_elem $conn_periphs_elems { + set periph [xget_value $periph_elem "PARAMETER" "periph_name"] + # 1. Get driver + set drv [xget_swhandle $periph] + set posn [lsearch -exact $drvlist $drv] + if {$posn == -1} { + lappend drvlist $drv + } + } + + set file_handle [xopen_include_file "xparameters.h"] + puts $file_handle "\n/******************************************************************/\n" + puts $file_handle "/* U-Boot Redefines */" + puts $file_handle "\n/******************************************************************/\n" + close $file_handle + + foreach drv $drvlist { + set drvname [xget_value $drv "NAME"] + + #Redefines xparameters.h + if {[string compare -nocase $drvname "uartns550"] == 0} { + xredefine_uartns550 $drv "xparameters.h" + } elseif {[string compare -nocase $drvname "emac"] == 0} { + xredefine_emac $drv "xparameters.h" + } elseif {[string compare -nocase $drvname "iic"] == 0} { + xredefine_iic $drv "xparameters.h" + } + } + } + + # define core_clock + xredefine_params $libname "xparameters.h" "CORE_CLOCK_FREQ_HZ" + + # define the values for the persistent storage in IIC + xredefine_params $libname "xparameters.h" "IIC_PERSISTENT_BASEADDR" "IIC_PERSISTENT_HIGHADDR" "IIC_PERSISTENT_EEPROMADDR" + +} + +proc xget_corefreq {} { + set processor [xget_processor] + set name [xget_value $processor "NAME"] + puts "procname : $name" + set processor_driver [xget_swhandle [xget_value $processor "NAME"]] + puts "procdrv : $processor_driver" + if {[string compare -nocase $processor_driver ""] != 0} { + set arg "CORE_CLOCK_FREQ_HZ" + #set retval [xget_value $processor_driver "PARAMETER" $arg] + set retval [xget_dname [xget_value $processor_driver "NAME"] $arg] + return $retval + } +} + +# procedure that adds # defines to xparameters.h as XPAR_argument +proc xredefine_params {handle file_name args} { + + puts "xredfine ..." + # Open include file + set file_handle [xopen_include_file $file_name] + puts "args : $args" + + foreach arg $args { + if {[string compare -nocase $arg "CORE_CLOCK_FREQ_HZ"] == 0} { + set value [xget_corefreq] + puts "corefreq : $value" + } else { + set value [xget_value $handle "PARAMETER" $arg] + puts "value : $value" + } + + if {$value != ""} { + set value [xformat_addr_string $value $arg] + + if {[string compare -nocase $arg "IIC_PERSISTENT_BASEADDR"] == 0} { + set name "PERSISTENT_0_IIC_0_BASEADDR" + } elseif {[string compare -nocase $arg "IIC_PERSISTENT_HIGHADDR"] == 0} { + set name "PERSISTENT_0_IIC_0_HIGHADDR" + } elseif {[string compare -nocase $arg "IIC_PERSISTENT_EEPROMADDR"] == 0} { + set name "PERSISTENT_0_IIC_0_EEPROMADDR" + } else { + set name [string toupper $arg] + } + set name [format "XPAR_%s" $name] + puts $file_handle "#define $name $value" + } + } + + puts $file_handle "\n/******************************************************************/\n" + close $file_handle +} + +# uart redefines... +proc xredefine_uartns550 {drvhandle file_name} { + + xredefine_include_file $drvhandle $file_name "uartns550" "C_BASEADDR" "C_HIGHADDR" "CLOCK_HZ" "DEVICE_ID" + +} + +proc xredefine_emac {drvhandle file_name} { + + xredefine_include_file $drvhandle $file_name "emac" "C_BASEADDR" "C_HIGHADDR" "C_DMA_PRESENT" "C_MII_EXIST" "C_ERR_COUNT_EXIST" "DEVICE_ID" + +} + +proc xredefine_iic {drvhandle file_name} { + xredefine_include_file $drvhandle $file_name "iic" "C_BASEADDR" "C_HIGHADDR" "C_TEN_BIT_ADR" "DEVICE_ID" + +} + +####################### + +proc xredefine_include_file {drv_handle file_name drv_string args} { + + # Open include file + set file_handle [xopen_include_file $file_name] + + # Get all peripherals connected to this driver + set periphs [xget_periphs $drv_handle] + + set pname [format "XPAR_%s_" [string toupper $drv_string]] + + # Print all parameters for all peripherals + set device_id 0 + set sub_periphs 1 + foreach periph $periphs { + puts "$periph : $drv_string : $sub_periphs" + + for {set i 0} {$i < $sub_periphs} {incr i} { + foreach arg $args { + set name "${pname}${device_id}_" + + if {[string compare -nocase "CLOCK_HZ" $arg] == 0} { + set xdrv_string [format "%s%s" "X" $drv_string] + set value [xget_dname $xdrv_string $arg] + set name "${name}CLOCK_FREQ_HZ" + } else { + if {[string match C_* $arg]} { + set name [format "%s%s" $name [string range $arg 2 end]] + } else { + set name "${name}${arg}" + } + set value [xget_name $periph $arg] + } + + if {[string compare -nocase "uartns550" $drv_string] == 0} { + if {[string compare -nocase "C_BASEADDR" $arg] == 0} { + set value [format "(%s%s%s)" $value "+" "0x1000"] + } + } + + puts $file_handle "#define $name $value" + if {[string compare -nocase "DEVICE_ID" $arg] == 0} { + incr device_id + } + } + } + } + puts $file_handle "\n/******************************************************************/\n" + close $file_handle +} + +################################################## +# procedure post_generate +# This generates the drivers directory for uboot +# and runs the ltypes script +################################################## + +proc post_generate {lib_handle} { + + global drvlist + + # Create U-Boot tree structure + set pwd [pwd] + set common_dir "uboot/board/xilinx/common" + set xilinx_enet_dir "uboot/board/xilinx/xilinx_enet" + set ml300_dir "uboot/board/xilinx/ml300" + + exec bash -c "mkdir -p $common_dir $xilinx_enet_dir $ml300_dir" + + # Copy files for xilinx_ocp + xcopy_commonfiles + + foreach drv $drvlist { + set drvname [xget_value $drv "NAME"] + set ver [xget_value $drv "PARAMETER" "DRIVER_VER"] + set ver [string map {. _} $ver] + set dirname [format "%s_v%s" $drvname $ver] + + if {[string compare -nocase $drvname "emac"] == 0} { + xcopy_emac $drv $dirname + } elseif {[string compare -nocase $drvname "iic"] == 0} { + xcopy_iic $drv $dirname + } + } + + # Call Ltypes Script here + set uboot "uboot" + xltype_file $uboot + + # Move xparameters.h around + exec bash -c "cp ../../include/xparameters.h $ml300_dir" + + # copy the whole U-Boot BSP to its final destination + set value [xget_value $lib_handle "PARAMETER" TARGET_DIR] + puts "TARGET_DIR : $value" + + if {$value != ""} { + if {[file isdirectory $value] == 0} { + exec bash -c "mkdir -p $value" + } + exec bash -c "cp -Rp uboot/* $value" + } +} + +proc xcopy_commonfiles {} { + + global drvlist + + set common_dir "uboot/board/xilinx/common" + + foreach drv $drvlist { + set depends [xget_value $drv "OPTION" "DEPENDS"] + foreach dep $depends { + puts "dep : $dep" + if {[file isdirectory "../$dep"] == 1} { + exec bash -c "cp -f ../$dep/src/*.c $common_dir" + exec bash -c "cp -f ../$dep/src/*.h $common_dir" + } + } + } + +} + +proc xcopy_emac {drv_handle dirname} { + set emac "board/xilinx/xilinx_enet" + xcopy_dir $dirname $emac +} + +proc xcopy_iic {drv_handle dirname} { + set iic "board/xilinx/xilinx_iic" + xcopy_dir $dirname $iic +} + +proc xcopy_dir {srcdir dstdir} { + + set dstdirname [format "%s%s" "uboot/" $dstdir] + if {[file isdirectory "../$srcdir"] == 1} { + # Copy files from src to dst + exec bash -c "mkdir -p $dstdirname" + exec bash -c "cp -f ../$srcdir/src/*.c $dstdirname" + exec bash -c "cp -f ../$srcdir/src/*.h $dstdirname" + } else { + puts "$srcdir does not exist ..." + } +} + + +proc xltype_file {filename} { + + global ltypes + + puts $filename + + if {[file isdirectory $filename]} { + foreach entry [glob -nocomplain [file join $filename *]] { + xltype_file $entry + } + } else { + exec bash -c "$ltypes $filename" + } + +} diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds new file mode 100644 index 0000000..b6d748e --- /dev/null +++ b/board/xilinx/ml300/u-boot.lds @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +ENTRY(_start) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ +/* + cpu/ppc4xx/start.o (.text) + board/xilinx/ml300/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/4xx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) +*/ +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/ml300/u-boot.lds.debug b/board/xilinx/ml300/u-boot.lds.debug new file mode 100644 index 0000000..1608f8c --- /dev/null +++ b/board/xilinx/ml300/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/ml300/xparameters.h b/board/xilinx/ml300/xparameters.h new file mode 100644 index 0000000..2c56737 --- /dev/null +++ b/board/xilinx/ml300/xparameters.h @@ -0,0 +1,196 @@ +/******************************************************************* +* +* CAUTION: This file is automatically generated by libgen. +* Version: Xilinx EDK 6.2 EDK_Gm.11 +* DO NOT EDIT. +* +* Copyright (c) 2003 Xilinx, Inc. All rights reserved. +* +* Description: Driver parameters +* +*******************************************************************/ + +/******************************************************************/ + +/* U-Boot Redefines */ + +/******************************************************************/ + +#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) +#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ +#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID +#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000) +#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR +#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ +#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID + +/******************************************************************/ + +#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR +#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR +#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR +#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR +#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR +#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT +#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST +#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST +#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ + +/******************************************************************/ + +#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 +#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF +#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 + +/******************************************************************/ + +#define XPAR_XPCI_NUM_INSTANCES 1 +#define XPAR_XPCI_CLOCK_HZ 33333333 +#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0 +#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000 +#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF +#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000 +#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004 +#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000 +#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000 +#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF +#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000 +#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF + +/******************************************************************/ + +#define XPAR_XEMAC_NUM_INSTANCES 1 +#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF +#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 +#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 +#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 +#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 + +/******************************************************************/ + +#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0 +#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000 +#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7) +#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1 +#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8) +#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F) +#define XPAR_XGPIO_NUM_INSTANCES 2 + +/******************************************************************/ + +#define XPAR_XIIC_NUM_INSTANCES 1 +#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 +#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF +#define XPAR_OPB_IIC_0_DEVICE_ID 0 +#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 + +/******************************************************************/ + +#define XPAR_XUARTNS550_NUM_INSTANCES 2 +#define XPAR_XUARTNS550_CLOCK_HZ 100000000 +#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 +#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF +#define XPAR_OPB_UART16550_0_DEVICE_ID 0 +#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000 +#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF +#define XPAR_OPB_UART16550_1_DEVICE_ID 1 + +/******************************************************************/ + +#define XPAR_XSPI_NUM_INSTANCES 1 +#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000 +#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F +#define XPAR_OPB_SPI_0_DEVICE_ID 0 +#define XPAR_OPB_SPI_0_FIFO_EXIST 1 +#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0 +#define XPAR_OPB_SPI_0_NUM_SS_BITS 1 + +/******************************************************************/ + +#define XPAR_XPS2_NUM_INSTANCES 2 +#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 +#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 +#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) +#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 +#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) +#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) + +/******************************************************************/ + +#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1 +#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000 +#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007 +#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0 + +/******************************************************************/ + +#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF +#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000 +#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF +#define XPAR_PLB_DDR_0_BASEADDR 0x00000000 +#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF + +/******************************************************************/ + +#define XPAR_XINTC_HAS_IPR 1 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18 +#define XPAR_XINTC_USE_DCR 0 +#define XPAR_XINTC_NUM_INSTANCES 1 +#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0 +#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF +#define XPAR_DCR_INTC_0_DEVICE_ID 0 +#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000 + +/******************************************************************/ + +#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0 +#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1 +#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2 +#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3 +#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4 +#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5 +#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6 +#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7 +#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 +#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9 +#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10 +#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11 +#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12 +#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13 +#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14 +#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15 +#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16 +#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17 + +/******************************************************************/ + +#define XPAR_XTFT_NUM_INSTANCES 1 +#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 +#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 +#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 + +/******************************************************************/ + +#define XPAR_XSYSACE_MEM_WIDTH 8 +#define XPAR_XSYSACE_NUM_INSTANCES 1 +#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 +#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF +#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 +#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8 + +/******************************************************************/ + +#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 + +/******************************************************************/ diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c new file mode 100644 index 0000000..1076345 --- /dev/null +++ b/board/xilinx/xilinx_enet/emac_adapter.c @@ -0,0 +1,158 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ + +#include +#include +#include +#include "xparameters.h" +#include "xemac.h" + +#if defined(XPAR_EMAC_0_DEVICE_ID) +/* + * ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from + * PKTSIZE and PKTSIZE_ALIGN (include/net.h) + */ + +#define ENET_MAX_MTU PKTSIZE +#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN +#define ENET_ADDR_LENGTH 6 + +static XEmac Emac; +static char etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ + +/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ +#ifdef CFG_ENV_IS_NOWHERE +static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; +#endif + +static int initialized = 0; + +void +eth_halt(void) +{ + if (initialized) + (void) XEmac_Stop(&Emac); +} + +int +eth_init(bd_t * bis) +{ + u32 Options; + XStatus Result; + +#ifdef DEBUG + printf("EMAC Initialization Started\n\r"); +#endif + + Result = XEmac_Initialize(&Emac, XPAR_EMAC_0_DEVICE_ID); + if (Result != XST_SUCCESS) { + return 0; + } + + /* make sure the Emac is stopped before it is started */ + (void) XEmac_Stop(&Emac); + +#ifdef CFG_ENV_IS_NOWHERE + memcpy(bis->bi_enetaddr, EMACAddr, 6); +#endif + + Result = XEmac_SetMacAddress(&Emac, bis->bi_enetaddr); + if (Result != XST_SUCCESS) { + return 0; + } + + Options = + (XEM_POLLED_OPTION | XEM_UNICAST_OPTION | XEM_BROADCAST_OPTION | + XEM_FDUPLEX_OPTION | XEM_INSERT_FCS_OPTION | + XEM_INSERT_PAD_OPTION); + Result = XEmac_SetOptions(&Emac, Options); + if (Result != XST_SUCCESS) { + return 0; + } + + Result = XEmac_Start(&Emac); + if (Result != XST_SUCCESS) { + return 0; + } +#ifdef DEBUG + printf("EMAC Initialization complete\n\r"); +#endif + + initialized = 1; + + return (0); +} + +/*-----------------------------------------------------------------------------+ ++-----------------------------------------------------------------------------*/ +int +eth_send(volatile void *ptr, int len) +{ + XStatus Result; + + if (len > ENET_MAX_MTU) + len = ENET_MAX_MTU; + + Result = XEmac_PollSend(&Emac, (u8 *) ptr, len); + if (Result == XST_SUCCESS) { + return (1); + } else { + printf("Error while sending frame\n\r"); + return (0); + } + +} + +int +eth_rx(void) +{ + u32 RecvFrameLength; + XStatus Result; + + RecvFrameLength = PKTSIZE; + Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength); + if (Result == XST_SUCCESS) { + NetReceive((uchar)etherrxbuff, RecvFrameLength); + return (1); + } else { + return (0); + } +} + +#endif diff --git a/board/xilinx/xilinx_enet/xemac.c b/board/xilinx/xilinx_enet/xemac.c new file mode 100644 index 0000000..48b4ede --- /dev/null +++ b/board/xilinx/xilinx_enet/xemac.c @@ -0,0 +1,844 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemac.c +* +* The XEmac driver. Functions in this file are the minimum required functions +* for this driver. See xemac.h for a detailed description of the driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00b rpm  07/23/02 Removed the PHY reset from Initialize()
+* 1.00b rmm  09/23/02 Removed commented code in Initialize(). Recycled as
+*                     XEmac_mPhyReset macro in xemac_l.h.
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* 1.00c rpm  12/12/02 Changed location of IsStarted assignment in XEmac_Start
+*                     to be sure the flag is set before the device and
+*                     interrupts are enabled.
+* 1.00c rpm  02/03/03 SelfTest was not clearing polled mode. Take driver out
+*                     of polled mode in XEmac_Reset() to fix this problem.
+* 1.00c rmm  05/13/03 Fixed diab compiler warnings relating to asserts.
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xemac_i.h" +#include "xio.h" +#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +static XStatus ConfigureDma(XEmac * InstancePtr); +static XStatus ConfigureFifo(XEmac * InstancePtr); +static void StubFifoHandler(void *CallBackRef); +static void StubErrorHandler(void *CallBackRef, XStatus ErrorCode); +static void StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr, + u32 NumBds); + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* Initialize a specific XEmac instance/driver. The initialization entails: +* - Initialize fields of the XEmac structure +* - Clear the Ethernet statistics for this device +* - Initialize the IPIF component with its register base address +* - Configure the FIFO components with their register base addresses. +* - If the device is configured with DMA, configure the DMA channel components +* with their register base addresses. At some later time, memory pools for +* the scatter-gather descriptor lists may be passed to the driver. +* - Reset the Ethernet MAC +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param DeviceId is the unique id of the device controlled by this XEmac +* instance. Passing in a device id associates the generic XEmac +* instance to a specific device, as chosen by the caller or application +* developer. +* +* @return +* +* - XST_SUCCESS if initialization was successful +* - XST_DEVICE_IS_STARTED if the device has already been started +* - XST_DEVICE_NOT_FOUND if device configuration information was not found for +* a device with the supplied device ID. +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId) +{ + XStatus Result; + XEmac_Config *ConfigPtr; /* configuration information */ + + XASSERT_NONVOID(InstancePtr != NULL); + + /* + * If the device is started, disallow the initialize and return a status + * indicating it is started. This allows the user to stop the device + * and reinitialize, but prevents a user from inadvertently initializing + */ + if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + /* + * Lookup the device configuration in the temporary CROM table. Use this + * configuration info down below when initializing this component. + */ + ConfigPtr = XEmac_LookupConfig(DeviceId); + if (ConfigPtr == NULL) { + return XST_DEVICE_NOT_FOUND; + } + + /* + * Set some default values + */ + InstancePtr->IsReady = 0; + InstancePtr->IsStarted = 0; + InstancePtr->IpIfDmaConfig = ConfigPtr->IpIfDmaConfig; + InstancePtr->HasMii = ConfigPtr->HasMii; + InstancePtr->HasMulticastHash = FALSE; + + /* Always default polled to false, let user configure this mode */ + InstancePtr->IsPolled = FALSE; + InstancePtr->FifoRecvHandler = StubFifoHandler; + InstancePtr->FifoSendHandler = StubFifoHandler; + InstancePtr->ErrorHandler = StubErrorHandler; + InstancePtr->SgRecvHandler = StubSgHandler; + InstancePtr->SgSendHandler = StubSgHandler; + + /* + * Clear the statistics for this driver + */ + XEmac_mClearStruct((u8 *) & InstancePtr->Stats, sizeof (XEmac_Stats)); + + /* + * Initialize the device register base addresses + */ + InstancePtr->BaseAddress = ConfigPtr->BaseAddress; + + /* + * Configure the send and receive FIFOs in the MAC + */ + Result = ConfigureFifo(InstancePtr); + if (Result != XST_SUCCESS) { + return Result; + } + + /* + * If the device is configured for DMA, configure the send and receive DMA + * channels in the MAC. + */ + if (XEmac_mIsDma(InstancePtr)) { + Result = ConfigureDma(InstancePtr); + if (Result != XST_SUCCESS) { + return Result; + } + } + + /* + * Indicate the component is now ready to use. Note that this is done before + * we reset the device and the PHY below, which may seem a bit odd. The + * choice was made to move it here rather than remove the asserts in various + * functions (e.g., Reset() and all functions that it calls). Applications + * that use multiple threads, one to initialize the XEmac driver and one + * waiting on the IsReady condition could have a problem with this sequence. + */ + InstancePtr->IsReady = XCOMPONENT_IS_READY; + + /* + * Reset the MAC to get it into its initial state. It is expected that + * device configuration by the user will take place after this + * initialization is done, but before the device is started. + */ + XEmac_Reset(InstancePtr); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Start the Ethernet controller as follows: +* - If not in polled mode +* - Set the internal interrupt enable registers appropriately +* - Enable interrupts within the device itself. Note that connection of +* the driver's interrupt handler to the interrupt source (typically +* done using the interrupt controller component) is done by the higher +* layer software. +* - If the device is configured with scatter-gather DMA, start the DMA +* channels if the descriptor lists are not empty +* - Enable the transmitter +* - Enable the receiver +* +* The PHY is enabled after driver initialization. We assume the upper layer +* software has configured it and the EMAC appropriately before this function +* is called. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* - XST_SUCCESS if the device was started successfully +* - XST_NO_CALLBACK if a callback function has not yet been registered using +* the SetxxxHandler function. This is required if in interrupt mode. +* - XST_DEVICE_IS_STARTED if the device is already started +* - XST_DMA_SG_NO_LIST if configured for scatter-gather DMA and a descriptor +* list has not yet been created for the send or receive channel. +* +* @note +* +* The driver tries to match the hardware configuration. So if the hardware +* is configured with scatter-gather DMA, the driver expects to start the +* scatter-gather channels and expects that the user has set up the buffer +* descriptor lists already. If the user expects to use the driver in a mode +* different than how the hardware is configured, the user should modify the +* configuration table to reflect the mode to be used. Modifying the config +* table is a workaround for now until we get some experience with how users +* are intending to use the hardware in its different configurations. For +* example, if the hardware is built with scatter-gather DMA but the user is +* intending to use only simple DMA, the user either needs to modify the config +* table as a workaround or rebuild the hardware with only simple DMA. +* +* This function makes use of internal resources that are shared between the +* Start, Stop, and SetOptions functions. So if one task might be setting device +* options while another is trying to start the device, the user is required to +* provide protection of this shared data (typically using a semaphore). +* +******************************************************************************/ +XStatus +XEmac_Start(XEmac * InstancePtr) +{ + u32 ControlReg; + XStatus Result; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * If it is already started, return a status indicating so + */ + if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + /* + * If not polled, enable interrupts + */ + if (!InstancePtr->IsPolled) { + /* + * Verify that the callbacks have been registered, then enable + * interrupts + */ + if (XEmac_mIsSgDma(InstancePtr)) { + if ((InstancePtr->SgRecvHandler == StubSgHandler) || + (InstancePtr->SgSendHandler == StubSgHandler)) { + return XST_NO_CALLBACK; + } + + /* Enable IPIF interrupts */ + XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress, + XEM_IPIF_DMA_DFT_MASK | + XIIF_V123B_ERROR_MASK); + XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, + XEM_EIR_DFT_SG_MASK); + + /* Enable scatter-gather DMA interrupts */ + XDmaChannel_SetIntrEnable(&InstancePtr->RecvChannel, + XEM_DMA_SG_INTR_MASK); + XDmaChannel_SetIntrEnable(&InstancePtr->SendChannel, + XEM_DMA_SG_INTR_MASK); + } else { + if ((InstancePtr->FifoRecvHandler == StubFifoHandler) || + (InstancePtr->FifoSendHandler == StubFifoHandler)) { + return XST_NO_CALLBACK; + } + + /* Enable IPIF interrupts (used by simple DMA also) */ + XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress, + XEM_IPIF_FIFO_DFT_MASK | + XIIF_V123B_ERROR_MASK); + XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, + XEM_EIR_DFT_FIFO_MASK); + } + + /* Enable the global IPIF interrupt output */ + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + } + + /* + * Indicate that the device is started before we enable the transmitter + * or receiver. This needs to be done before because as soon as the + * receiver is enabled we may get an interrupt, and there are functions + * in the interrupt handling path that rely on the IsStarted flag. + */ + InstancePtr->IsStarted = XCOMPONENT_IS_STARTED; + + /* + * Enable the transmitter, and receiver (do a read/modify/write to preserve + * current settings). There is no critical section here since this register + * is not modified during interrupt context. + */ + ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET); + ControlReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); + ControlReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); + + XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg); + + /* + * If configured with scatter-gather DMA and not polled, restart the + * DMA channels in case there are buffers ready to be sent or received into. + * The DMA SgStart function uses data that can be modified during interrupt + * context, so a critical section is required here. + */ + if ((XEmac_mIsSgDma(InstancePtr)) && (!InstancePtr->IsPolled)) { + XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); + + /* + * The only error we care about is if the list has not yet been + * created, or on receive, if no buffer descriptors have been + * added yet (the list is empty). Other errors are benign at this point. + */ + Result = XDmaChannel_SgStart(&InstancePtr->RecvChannel); + if ((Result == XST_DMA_SG_NO_LIST) + || (Result == XST_DMA_SG_LIST_EMPTY)) { + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + return Result; + } + + Result = XDmaChannel_SgStart(&InstancePtr->SendChannel); + if (Result == XST_DMA_SG_NO_LIST) { + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + return Result; + } + + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Stop the Ethernet MAC as follows: +* - If the device is configured with scatter-gather DMA, stop the DMA +* channels (wait for acknowledgment of stop) +* - Disable the transmitter and receiver +* - Disable interrupts if not in polled mode (the higher layer software is +* responsible for disabling interrupts at the interrupt controller) +* +* The PHY is left enabled after a Stop is called. +* +* If the device is configured for scatter-gather DMA, the DMA engine stops at +* the next buffer descriptor in its list. The remaining descriptors in the list +* are not removed, so anything in the list will be transmitted or received when +* the device is restarted. The side effect of doing this is that the last +* buffer descriptor processed by the DMA engine before stopping may not be the +* last descriptor in the Ethernet frame. So when the device is restarted, a +* partial frame (i.e., a bad frame) may be transmitted/received. This is only a +* concern if a frame can span multiple buffer descriptors, which is dependent +* on the size of the network buffers. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* - XST_SUCCESS if the device was stopped successfully +* - XST_DEVICE_IS_STOPPED if the device is already stopped +* +* @note +* +* This function makes use of internal resources that are shared between the +* Start, Stop, and SetOptions functions. So if one task might be setting device +* options while another is trying to start the device, the user is required to +* provide protection of this shared data (typically using a semaphore). +* +******************************************************************************/ +XStatus +XEmac_Stop(XEmac * InstancePtr) +{ + u32 ControlReg; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * If the device is already stopped, do nothing but return a status + * indicating so + */ + if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STOPPED; + } + + /* + * If configured for scatter-gather DMA, stop the DMA channels. Ignore + * the XST_DMA_SG_IS_STOPPED return code. There is a critical section + * here between SgStart and SgStop, and SgStart can be called in interrupt + * context, so disable interrupts while calling SgStop. + */ + if (XEmac_mIsSgDma(InstancePtr)) { + XBufDescriptor *BdTemp; /* temporary descriptor pointer */ + + XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); + + (void) XDmaChannel_SgStop(&InstancePtr->SendChannel, &BdTemp); + (void) XDmaChannel_SgStop(&InstancePtr->RecvChannel, &BdTemp); + + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + } + + /* + * Disable the transmitter and receiver. There is no critical section + * here since this register is not modified during interrupt context. + */ + ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET); + ControlReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); + XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg); + + /* + * If not in polled mode, disable interrupts for IPIF (includes MAC and + * DMAs) + */ + if (!InstancePtr->IsPolled) { + XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); + } + + InstancePtr->IsStarted = 0; + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Reset the Ethernet MAC. This is a graceful reset in that the device is stopped +* first. Resets the DMA channels, the FIFOs, the transmitter, and the receiver. +* The PHY is not reset. Any frames in the scatter-gather descriptor lists will +* remain in the lists. The side effect of doing this is that after a reset and +* following a restart of the device, frames that were in the list before the +* reset may be transmitted or received. Reset must only be called after the +* driver has been initialized. +* +* The driver is also taken out of polled mode if polled mode was set. The user +* is responsbile for re-configuring the driver into polled mode after the +* reset if desired. +* +* The configuration after this reset is as follows: +* - Half duplex +* - Disabled transmitter and receiver +* - Enabled PHY (the PHY is not reset) +* - MAC transmitter does pad insertion, FCS insertion, and source address +* overwrite. +* - MAC receiver does not strip padding or FCS +* - Interframe Gap as recommended by IEEE Std. 802.3 (96 bit times) +* - Unicast addressing enabled +* - Broadcast addressing enabled +* - Multicast addressing disabled (addresses are preserved) +* - Promiscuous addressing disabled +* - Default packet threshold and packet wait bound register values for +* scatter-gather DMA operation +* - MAC address of all zeros +* - Non-polled mode +* +* The upper layer software is responsible for re-configuring (if necessary) +* and restarting the MAC after the reset. Note that the PHY is not reset. PHY +* control is left to the upper layer software. Note also that driver statistics +* are not cleared on reset. It is up to the upper layer software to clear the +* statistics if needed. +* +* When a reset is required due to an internal error, the driver notifies the +* upper layer software of this need through the ErrorHandler callback and +* specific status codes. The upper layer software is responsible for calling +* this Reset function and then re-configuring the device. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* None. +* +* @note +* +* None. +* +* @internal +* +* The reset is accomplished by setting the IPIF reset register. This takes +* care of resetting all hardware blocks, including the MAC. +* +******************************************************************************/ +void +XEmac_Reset(XEmac * InstancePtr) +{ + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * Stop the device first + */ + (void) XEmac_Stop(InstancePtr); + + /* + * Take the driver out of polled mode + */ + InstancePtr->IsPolled = FALSE; + + /* + * Reset the entire IPIF at once. If we choose someday to reset each + * hardware block separately, the reset should occur in the direction of + * data flow. For example, for the send direction the reset order is DMA + * first, then FIFO, then the MAC transmitter. + */ + XIIF_V123B_RESET(InstancePtr->BaseAddress); + + if (XEmac_mIsSgDma(InstancePtr)) { + /* + * After reset, configure the scatter-gather DMA packet threshold and + * packet wait bound registers to default values. Ignore the return + * values of these functions since they only return error if the device + * is not stopped. + */ + (void) XEmac_SetPktThreshold(InstancePtr, XEM_SEND, + XEM_SGDMA_DFT_THRESHOLD); + (void) XEmac_SetPktThreshold(InstancePtr, XEM_RECV, + XEM_SGDMA_DFT_THRESHOLD); + (void) XEmac_SetPktWaitBound(InstancePtr, XEM_SEND, + XEM_SGDMA_DFT_WAITBOUND); + (void) XEmac_SetPktWaitBound(InstancePtr, XEM_RECV, + XEM_SGDMA_DFT_WAITBOUND); + } +} + +/*****************************************************************************/ +/** +* +* Set the MAC address for this driver/device. The address is a 48-bit value. +* The device must be stopped before calling this function. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param AddressPtr is a pointer to a 6-byte MAC address. +* +* @return +* +* - XST_SUCCESS if the MAC address was set successfully +* - XST_DEVICE_IS_STARTED if the device has not yet been stopped +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr) +{ + u32 MacAddr = 0; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(AddressPtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * The device must be stopped before setting the MAC address + */ + if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + /* + * Set the device station address high and low registers + */ + MacAddr = (AddressPtr[0] << 8) | AddressPtr[1]; + XIo_Out32(InstancePtr->BaseAddress + XEM_SAH_OFFSET, MacAddr); + + MacAddr = (AddressPtr[2] << 24) | (AddressPtr[3] << 16) | + (AddressPtr[4] << 8) | AddressPtr[5]; + + XIo_Out32(InstancePtr->BaseAddress + XEM_SAL_OFFSET, MacAddr); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Get the MAC address for this driver/device. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param BufferPtr is an output parameter, and is a pointer to a buffer into +* which the current MAC address will be copied. The buffer must be at +* least 6 bytes. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void +XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr) +{ + u32 MacAddrHi; + u32 MacAddrLo; + + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(BufferPtr != NULL); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + MacAddrHi = XIo_In32(InstancePtr->BaseAddress + XEM_SAH_OFFSET); + MacAddrLo = XIo_In32(InstancePtr->BaseAddress + XEM_SAL_OFFSET); + + BufferPtr[0] = (u8) (MacAddrHi >> 8); + BufferPtr[1] = (u8) MacAddrHi; + BufferPtr[2] = (u8) (MacAddrLo >> 24); + BufferPtr[3] = (u8) (MacAddrLo >> 16); + BufferPtr[4] = (u8) (MacAddrLo >> 8); + BufferPtr[5] = (u8) MacAddrLo; +} + +/******************************************************************************/ +/** +* +* Configure DMA capabilities. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* - XST_SUCCESS if successful initialization of DMA +* +* @note +* +* None. +* +******************************************************************************/ +static XStatus +ConfigureDma(XEmac * InstancePtr) +{ + XStatus Result; + + /* + * Initialize the DMA channels with their base addresses. We assume + * scatter-gather DMA is the only possible configuration. Descriptor space + * will need to be set later by the upper layer. + */ + Result = XDmaChannel_Initialize(&InstancePtr->RecvChannel, + InstancePtr->BaseAddress + + XEM_DMA_RECV_OFFSET); + if (Result != XST_SUCCESS) { + return Result; + } + + Result = XDmaChannel_Initialize(&InstancePtr->SendChannel, + InstancePtr->BaseAddress + + XEM_DMA_SEND_OFFSET); + + return Result; +} + +/******************************************************************************/ +/** +* +* Configure the send and receive FIFO components with their base addresses +* and interrupt masks. Currently the base addresses are defined constants. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* XST_SUCCESS if successful initialization of the packet FIFOs +* +* @note +* +* None. +* +******************************************************************************/ +static XStatus +ConfigureFifo(XEmac * InstancePtr) +{ + XStatus Result; + + /* + * Return status from the packet FIFOs initialization is ignored since + * they always return success. + */ + Result = XPacketFifoV100b_Initialize(&InstancePtr->RecvFifo, + InstancePtr->BaseAddress + + XEM_PFIFO_RXREG_OFFSET, + InstancePtr->BaseAddress + + XEM_PFIFO_RXDATA_OFFSET); + if (Result != XST_SUCCESS) { + return Result; + } + + Result = XPacketFifoV100b_Initialize(&InstancePtr->SendFifo, + InstancePtr->BaseAddress + + XEM_PFIFO_TXREG_OFFSET, + InstancePtr->BaseAddress + + XEM_PFIFO_TXDATA_OFFSET); + return Result; +} + +/******************************************************************************/ +/** +* +* This is a stub for the scatter-gather send and recv callbacks. The stub +* is here in case the upper layers forget to set the handlers. +* +* @param CallBackRef is a pointer to the upper layer callback reference +* @param BdPtr is a pointer to the first buffer descriptor in a list +* @param NumBds is the number of descriptors in the list. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +static void +StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr, u32 NumBds) +{ + XASSERT_VOID_ALWAYS(); +} + +/******************************************************************************/ +/** +* +* This is a stub for the non-DMA send and recv callbacks. The stub is here in +* case the upper layers forget to set the handlers. +* +* @param CallBackRef is a pointer to the upper layer callback reference +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +static void +StubFifoHandler(void *CallBackRef) +{ + XASSERT_VOID_ALWAYS(); +} + +/******************************************************************************/ +/** +* +* This is a stub for the asynchronous error callback. The stub is here in +* case the upper layers forget to set the handler. +* +* @param CallBackRef is a pointer to the upper layer callback reference +* @param ErrorCode is the Xilinx error code, indicating the cause of the error +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +static void +StubErrorHandler(void *CallBackRef, XStatus ErrorCode) +{ + XASSERT_VOID_ALWAYS(); +} + +/*****************************************************************************/ +/** +* +* Lookup the device configuration based on the unique device ID. The table +* EmacConfigTable contains the configuration info for each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return +* +* A pointer to the configuration table entry corresponding to the given +* device ID, or NULL if no match is found. +* +* @note +* +* None. +* +******************************************************************************/ +XEmac_Config * +XEmac_LookupConfig(u16 DeviceId) +{ + XEmac_Config *CfgPtr = NULL; + int i; + + for (i = 0; i < XPAR_XEMAC_NUM_INSTANCES; i++) { + if (XEmac_ConfigTable[i].DeviceId == DeviceId) { + CfgPtr = &XEmac_ConfigTable[i]; + break; + } + } + + return CfgPtr; +} diff --git a/board/xilinx/xilinx_enet/xemac.h b/board/xilinx/xilinx_enet/xemac.h new file mode 100644 index 0000000..ed704bf --- /dev/null +++ b/board/xilinx/xilinx_enet/xemac.h @@ -0,0 +1,673 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemac.h +* +* The Xilinx Ethernet driver component. This component supports the Xilinx +* Ethernet 10/100 MAC (EMAC). +* +* The Xilinx Ethernet 10/100 MAC supports the following features: +* - Simple and scatter-gather DMA operations, as well as simple memory +* mapped direct I/O interface (FIFOs). +* - Media Independent Interface (MII) for connection to external +* 10/100 Mbps PHY transceivers. +* - MII management control reads and writes with MII PHYs +* - Independent internal transmit and receive FIFOs +* - CSMA/CD compliant operations for half-duplex modes +* - Programmable PHY reset signal +* - Unicast, broadcast, and promiscuous address filtering (no multicast yet) +* - Internal loopback +* - Automatic source address insertion or overwrite (programmable) +* - Automatic FCS insertion and stripping (programmable) +* - Automatic pad insertion and stripping (programmable) +* - Pause frame (flow control) detection in full-duplex mode +* - Programmable interframe gap +* - VLAN frame support. +* - Pause frame support +* +* The device driver supports all the features listed above. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the EMAC. The driver handles transmission and reception of +* Ethernet frames, as well as configuration of the controller. It does not +* handle protocol stack functionality such as Link Layer Control (LLC) or the +* Address Resolution Protocol (ARP). The protocol stack that makes use of the +* driver handles this functionality. This implies that the driver is simply a +* pass-through mechanism between a protocol stack and the EMAC. A single device +* driver can support multiple EMACs. +* +* The driver is designed for a zero-copy buffer scheme. That is, the driver will +* not copy buffers. This avoids potential throughput bottlenecks within the +* driver. +* +* Since the driver is a simple pass-through mechanism between a protocol stack +* and the EMAC, no assembly or disassembly of Ethernet frames is done at the +* driver-level. This assumes that the protocol stack passes a correctly +* formatted Ethernet frame to the driver for transmission, and that the driver +* does not validate the contents of an incoming frame +* +* PHY Communication +* +* The driver provides rudimentary read and write functions to allow the higher +* layer software to access the PHY. The EMAC provides MII registers for the +* driver to access. This management interface can be parameterized away in the +* FPGA implementation process. If this is the case, the PHY read and write +* functions of the driver return XST_NO_FEATURE. +* +* External loopback is usually supported at the PHY. It is up to the user to +* turn external loopback on or off at the PHY. The driver simply provides pass- +* through functions for configuring the PHY. The driver does not read, write, +* or reset the PHY on its own. All control of the PHY must be done by the user. +* +* Asynchronous Callbacks +* +* The driver services interrupts and passes Ethernet frames to the higher layer +* software through asynchronous callback functions. When using the driver +* directly (i.e., not with the RTOS protocol stack), the higher layer +* software must register its callback functions during initialization. The +* driver requires callback functions for received frames, for confirmation of +* transmitted frames, and for asynchronous errors. +* +* Interrupts +* +* The driver has no dependencies on the interrupt controller. The driver +* provides two interrupt handlers. XEmac_IntrHandlerDma() handles interrupts +* when the EMAC is configured with scatter-gather DMA. XEmac_IntrHandlerFifo() +* handles interrupts when the EMAC is configured for direct FIFO I/O or simple +* DMA. Either of these routines can be connected to the system interrupt +* controller by the user. +* +* Interrupt Frequency +* +* When the EMAC is configured with scatter-gather DMA, the frequency of +* interrupts can be controlled with the interrupt coalescing features of the +* scatter-gather DMA engine. The frequency of interrupts can be adjusted using +* the driver API functions for setting the packet count threshold and the packet +* wait bound values. +* +* The scatter-gather DMA engine only interrupts when the packet count threshold +* is reached, instead of interrupting for each packet. A packet is a generic +* term used by the scatter-gather DMA engine, and is equivalent to an Ethernet +* frame in our case. +* +* The packet wait bound is a timer value used during interrupt coalescing to +* trigger an interrupt when not enough packets have been received to reach the +* packet count threshold. +* +* These values can be tuned by the user to meet their needs. If there appear to +* be interrupt latency problems or delays in packet arrival that are longer than +* might be expected, the user should verify that the packet count threshold is +* set low enough to receive interrupts before the wait bound timer goes off. +* +* Device Reset +* +* Some errors that can occur in the device require a device reset. These errors +* are listed in the XEmac_SetErrorHandler() function header. The user's error +* handler is responsible for resetting the device and re-configuring it based on +* its needs (the driver does not save the current configuration). When +* integrating into an RTOS, these reset and re-configure obligations are +* taken care of by the Xilinx adapter software if it exists for that RTOS. +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xemac_g.c files. +* A table is defined where each entry contains configuration information +* for an EMAC device. This information includes such things as the base address +* of the memory-mapped device, the base addresses of IPIF, DMA, and FIFO modules +* within the device, and whether the device has DMA, counter registers, +* multicast support, MII support, and flow control. +* +* The driver tries to use the features built into the device. So if, for +* example, the hardware is configured with scatter-gather DMA, the driver +* expects to start the scatter-gather channels and expects that the user has set +* up the buffer descriptor lists already. If the user expects to use the driver +* in a mode different than how the hardware is configured, the user should +* modify the configuration table to reflect the mode to be used. Modifying the +* configuration table is a workaround for now until we get some experience with +* how users are intending to use the hardware in its different configurations. +* For example, if the hardware is built with scatter-gather DMA but the user is +* intending to use only simple DMA, the user either needs to modify the config +* table as a workaround or rebuild the hardware with only simple DMA. The +* recommendation at this point is to build the hardware with the features you +* intend to use. If you're inclined to modify the table, do so before the call +* to XEmac_Initialize(). Here is a snippet of code that changes a device to +* simple DMA (the hardware needs to have DMA for this to work of course): +* 
+*	 XEmac_Config *ConfigPtr;
+*
+*	 ConfigPtr = XEmac_LookupConfig(DeviceId);
+*	 ConfigPtr->IpIfDmaConfig = XEM_CFG_SIMPLE_DMA;
+*
+* +* Simple DMA +* +* Simple DMA is supported through the FIFO functions, FifoSend and FifoRecv, of +* the driver (i.e., there is no separate interface for it). The driver makes use +* of the DMA engine for a simple DMA transfer if the device is configured with +* DMA, otherwise it uses the FIFOs directly. While the simple DMA interface is +* therefore transparent to the user, the caching of network buffers is not. +* If the device is configured with DMA and the FIFO interface is used, the user +* must ensure that the network buffers are not cached or are cache coherent, +* since DMA will be used to transfer to and from the Emac device. If the device +* is configured with DMA and the user really wants to use the FIFOs directly, +* the user should rebuild the hardware without DMA. If unable to do this, there +* is a workaround (described above in Device Configuration) to modify the +* configuration table of the driver to fake the driver into thinking the device +* has no DMA. A code snippet follows: +* 
+*	 XEmac_Config *ConfigPtr;
+*
+*	 ConfigPtr = XEmac_LookupConfig(DeviceId);
+*	 ConfigPtr->IpIfDmaConfig = XEM_CFG_NO_DMA;
+*
+* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XEmac driver is composed of several source files. Why so many? This +* allows the user to build and link only those parts of the driver that are +* necessary. Since the EMAC hardware can be configured in various ways (e.g., +* with or without DMA), the driver too can be built with varying features. +* For the most part, this means that besides always linking in xemac.c, you +* link in only the driver functionality you want. Some of the choices you have +* are polled vs. interrupt, interrupt with FIFOs only vs. interrupt with DMA, +* self-test diagnostics, and driver statistics. Note that currently the DMA code +* must be linked in, even if you don't have DMA in the device. +* +* @note +* +* Xilinx drivers are typically composed of two components, one is the driver +* and the other is the adapter. The driver is independent of OS and processor +* and is intended to be highly portable. The adapter is OS-specific and +* facilitates communication between the driver and an OS. +*

+* This driver is intended to be RTOS and processor independent. It works +* with physical addresses only. Any needs for dynamic memory management, +* threads or thread mutual exclusion, virtual memory, or cache control must +* be satisfied by the layer above this driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00b rpm  10/08/02 Replaced HasSgDma boolean with IpifDmaConfig enumerated
+*		      configuration parameter
+* 1.00c rpm  12/05/02 New version includes support for simple DMA and the delay
+*		      argument to SgSend
+* 1.00c rpm  02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
+*		      from SetPktThreshold in the internal DMA driver. Also
+*		      avoided compiler warnings by initializing Result in the
+*		      DMA interrupt service routines.
+*
+* +******************************************************************************/ + +#ifndef XEMAC_H /* prevent circular inclusions */ +#define XEMAC_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xstatus.h" +#include "xparameters.h" +#include "xpacket_fifo_v1_00_b.h" /* Uses v1.00b of Packet Fifo */ +#include "xdma_channel.h" + +/************************** Constant Definitions *****************************/ + +/* + * Device information + */ +#define XEM_DEVICE_NAME "xemac" +#define XEM_DEVICE_DESC "Xilinx Ethernet 10/100 MAC" + +/** @name Configuration options + * + * Device configuration options (see the XEmac_SetOptions() and + * XEmac_GetOptions() for information on how to use these options) + * @{ + */ +/** + * 
+ *   XEM_BROADCAST_OPTION	 Broadcast addressing on or off (default is on)
+ *   XEM_UNICAST_OPTION		 Unicast addressing on or off (default is on)
+ *   XEM_PROMISC_OPTION		 Promiscuous addressing on or off (default is off)
+ *   XEM_FDUPLEX_OPTION		 Full duplex on or off (default is off)
+ *   XEM_POLLED_OPTION		 Polled mode on or off (default is off)
+ *   XEM_LOOPBACK_OPTION	 Internal loopback on or off (default is off)
+ *   XEM_FLOW_CONTROL_OPTION	 Interpret pause frames in full duplex mode
+ *				 (default is off)
+ *   XEM_INSERT_PAD_OPTION	 Pad short frames on transmit (default is on)
+ *   XEM_INSERT_FCS_OPTION	 Insert FCS (CRC) on transmit (default is on)
+ *   XEM_INSERT_ADDR_OPTION	 Insert source address on transmit (default is on)
+ *   XEM_OVWRT_ADDR_OPTION	 Overwrite source address on transmit. This is
+ *				 only used if source address insertion is on.
+ *				 (default is on)
+ *   XEM_STRIP_PAD_FCS_OPTION	 Strip FCS and padding from received frames
+ *				 (default is off)
+  *
+ */ +#define XEM_UNICAST_OPTION 0x00000001UL +#define XEM_BROADCAST_OPTION 0x00000002UL +#define XEM_PROMISC_OPTION 0x00000004UL +#define XEM_FDUPLEX_OPTION 0x00000008UL +#define XEM_POLLED_OPTION 0x00000010UL +#define XEM_LOOPBACK_OPTION 0x00000020UL +#define XEM_FLOW_CONTROL_OPTION 0x00000080UL +#define XEM_INSERT_PAD_OPTION 0x00000100UL +#define XEM_INSERT_FCS_OPTION 0x00000200UL +#define XEM_INSERT_ADDR_OPTION 0x00000400UL +#define XEM_OVWRT_ADDR_OPTION 0x00000800UL +#define XEM_STRIP_PAD_FCS_OPTION 0x00002000UL +/*@}*/ +/* + * Not supported yet: + * XEM_MULTICAST_OPTION Multicast addressing on or off (default is off) + */ +/* NOT SUPPORTED YET... */ +#define XEM_MULTICAST_OPTION 0x00000040UL + +/* + * Some default values for interrupt coalescing within the scatter-gather + * DMA engine. + */ +#define XEM_SGDMA_DFT_THRESHOLD 1 /* Default pkt threshold */ +#define XEM_SGDMA_MAX_THRESHOLD 255 /* Maximum pkt theshold */ +#define XEM_SGDMA_DFT_WAITBOUND 5 /* Default pkt wait bound (msec) */ +#define XEM_SGDMA_MAX_WAITBOUND 1023 /* Maximum pkt wait bound (msec) */ + +/* + * Direction identifiers. These are used for setting values like packet + * thresholds and wait bound for specific channels + */ +#define XEM_SEND 1 +#define XEM_RECV 2 + +/* + * Arguments to SgSend function to indicate whether to hold off starting + * the scatter-gather engine. + */ +#define XEM_SGDMA_NODELAY 0 /* start SG DMA immediately */ +#define XEM_SGDMA_DELAY 1 /* do not start SG DMA */ + +/* + * Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEM_CFG_NO_IPIF 0 /* Not supported by the driver */ +#define XEM_CFG_NO_DMA 1 /* No DMA */ +#define XEM_CFG_SIMPLE_DMA 2 /* Simple DMA */ +#define XEM_CFG_DMA_SG 3 /* DMA scatter gather */ + +/* + * The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEM_MAC_ADDR_SIZE 6 /* six-byte MAC address */ +#define XEM_MTU 1500 /* max size of Ethernet frame */ +#define XEM_HDR_SIZE 14 /* size of Ethernet header */ +#define XEM_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */ +#define XEM_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ +#define XEM_MAX_FRAME_SIZE (XEM_MTU + XEM_HDR_SIZE + XEM_TRL_SIZE) +#define XEM_MAX_VLAN_FRAME_SIZE (XEM_MTU + XEM_HDR_VLAN_SIZE + XEM_TRL_SIZE) + +/* + * Define a default number of send and receive buffers + */ +#define XEM_MIN_RECV_BUFS 32 /* minimum # of recv buffers */ +#define XEM_DFT_RECV_BUFS 64 /* default # of recv buffers */ + +#define XEM_MIN_SEND_BUFS 16 /* minimum # of send buffers */ +#define XEM_DFT_SEND_BUFS 32 /* default # of send buffers */ + +#define XEM_MIN_BUFFERS (XEM_MIN_RECV_BUFS + XEM_MIN_SEND_BUFS) +#define XEM_DFT_BUFFERS (XEM_DFT_RECV_BUFS + XEM_DFT_SEND_BUFS) + +/* + * Define the number of send and receive buffer descriptors, used for + * scatter-gather DMA + */ +#define XEM_MIN_RECV_DESC 16 /* minimum # of recv descriptors */ +#define XEM_DFT_RECV_DESC 32 /* default # of recv descriptors */ + +#define XEM_MIN_SEND_DESC 8 /* minimum # of send descriptors */ +#define XEM_DFT_SEND_DESC 16 /* default # of send descriptors */ + +/**************************** Type Definitions *******************************/ + +/** + * Ethernet statistics (see XEmac_GetStats() and XEmac_ClearStats()) + */ +typedef struct { + u32 XmitFrames; /**< Number of frames transmitted */ + u32 XmitBytes; /**< Number of bytes transmitted */ + u32 XmitLateCollisionErrors; + /**< Number of transmission failures + due to late collisions */ + u32 XmitExcessDeferral; /**< Number of transmission failures + due o excess collision deferrals */ + u32 XmitOverrunErrors; /**< Number of transmit overrun errors */ + u32 XmitUnderrunErrors; /**< Number of transmit underrun errors */ + u32 RecvFrames; /**< Number of frames received */ + u32 RecvBytes; /**< Number of bytes received */ + u32 RecvFcsErrors; /**< Number of frames discarded due + to FCS errors */ + u32 RecvAlignmentErrors; /**< Number of frames received with + alignment errors */ + u32 RecvOverrunErrors; /**< Number of frames discarded due + to overrun errors */ + u32 RecvUnderrunErrors; /**< Number of recv underrun errors */ + u32 RecvMissedFrameErrors; + /**< Number of frames missed by MAC */ + u32 RecvCollisionErrors; /**< Number of frames discarded due + to collisions */ + u32 RecvLengthFieldErrors; + /**< Number of frames discarded with + invalid length field */ + u32 RecvShortErrors; /**< Number of short frames discarded */ + u32 RecvLongErrors; /**< Number of long frames discarded */ + u32 DmaErrors; /**< Number of DMA errors since init */ + u32 FifoErrors; /**< Number of FIFO errors since init */ + u32 RecvInterrupts; /**< Number of receive interrupts */ + u32 XmitInterrupts; /**< Number of transmit interrupts */ + u32 EmacInterrupts; /**< Number of MAC (device) interrupts */ + u32 TotalIntrs; /**< Total interrupts */ +} XEmac_Stats; + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Register base address */ + u32 HasCounters; /**< Does device have counters? */ + u8 IpIfDmaConfig; /**< IPIF/DMA hardware configuration */ + u32 HasMii; /**< Does device support MII? */ + +} XEmac_Config; + +/** @name Typedefs for callbacks + * Callback functions. + * @{ + */ +/** + * Callback when data is sent or received with scatter-gather DMA. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the upper + * layer when the callback is invoked. + * @param BdPtr is a pointer to the first buffer descriptor in a list of + * buffer descriptors. + * @param NumBds is the number of buffer descriptors in the list pointed + * to by BdPtr. + */ +typedef void (*XEmac_SgHandler) (void *CallBackRef, XBufDescriptor * BdPtr, + u32 NumBds); + +/** + * Callback when data is sent or received with direct FIFO communication or + * simple DMA. The user typically defines two callacks, one for send and one + * for receive. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the upper + * layer when the callback is invoked. + */ +typedef void (*XEmac_FifoHandler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the upper + * layer when the callback is invoked. + * @param ErrorCode is a Xilinx error code defined in xstatus.h. Also see + * XEmac_SetErrorHandler() for a description of possible errors. + */ +typedef void (*XEmac_ErrorHandler) (void *CallBackRef, XStatus ErrorCode); +/*@}*/ + +/** + * The XEmac driver instance data. The user is required to allocate a + * variable of this type for every EMAC device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + u32 BaseAddress; /* Base address (of IPIF) */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 IsPolled; /* Device is in polled mode */ + u8 IpIfDmaConfig; /* IPIF/DMA hardware configuration */ + u32 HasMii; /* Does device support MII? */ + u32 HasMulticastHash; /* Does device support multicast hash table? */ + + XEmac_Stats Stats; + XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */ + XPacketFifoV100b SendFifo; /* FIFO used to send frames */ + + /* + * Callbacks + */ + XEmac_FifoHandler FifoRecvHandler; /* for non-DMA/simple DMA interrupts */ + void *FifoRecvRef; + XEmac_FifoHandler FifoSendHandler; /* for non-DMA/simple DMA interrupts */ + void *FifoSendRef; + XEmac_ErrorHandler ErrorHandler; /* for asynchronous errors */ + void *ErrorRef; + + XDmaChannel RecvChannel; /* DMA receive channel driver */ + XDmaChannel SendChannel; /* DMA send channel driver */ + + XEmac_SgHandler SgRecvHandler; /* callback for scatter-gather DMA */ + void *SgRecvRef; + XEmac_SgHandler SgSendHandler; /* callback for scatter-gather DMA */ + void *SgSendRef; +} XEmac; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* This macro determines if the device is currently configured for +* scatter-gather DMA. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured for scatter-gather DMA, or FALSE +* if it is not. +* +* @note +* +* Signature: u32 XEmac_mIsSgDma(XEmac *InstancePtr) +* +******************************************************************************/ +#define XEmac_mIsSgDma(InstancePtr) \ + ((InstancePtr)->IpIfDmaConfig == XEM_CFG_DMA_SG) + +/*****************************************************************************/ +/** +* +* This macro determines if the device is currently configured for simple DMA. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured for simple DMA, or FALSE otherwise +* +* @note +* +* Signature: u32 XEmac_mIsSimpleDma(XEmac *InstancePtr) +* +******************************************************************************/ +#define XEmac_mIsSimpleDma(InstancePtr) \ + ((InstancePtr)->IpIfDmaConfig == XEM_CFG_SIMPLE_DMA) + +/*****************************************************************************/ +/** +* +* This macro determines if the device is currently configured with DMA (either +* simple DMA or scatter-gather DMA) +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with DMA, or FALSE otherwise +* +* @note +* +* Signature: u32 XEmac_mIsDma(XEmac *InstancePtr) +* +******************************************************************************/ +#define XEmac_mIsDma(InstancePtr) \ + (XEmac_mIsSimpleDma(InstancePtr) || XEmac_mIsSgDma(InstancePtr)) + +/************************** Function Prototypes ******************************/ + +/* + * Initialization functions in xemac.c + */ +XStatus XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId); +XStatus XEmac_Start(XEmac * InstancePtr); +XStatus XEmac_Stop(XEmac * InstancePtr); +void XEmac_Reset(XEmac * InstancePtr); +XEmac_Config *XEmac_LookupConfig(u16 DeviceId); + +/* + * Diagnostic functions in xemac_selftest.c + */ +XStatus XEmac_SelfTest(XEmac * InstancePtr); + +/* + * Polled functions in xemac_polled.c + */ +XStatus XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount); +XStatus XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr); + +/* + * Interrupts with scatter-gather DMA functions in xemac_intr_dma.c + */ +XStatus XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay); +XStatus XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr); +XStatus XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold); +XStatus XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction, + u8 * ThreshPtr); +XStatus XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction, + u32 TimerValue); +XStatus XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction, + u32 * WaitPtr); +XStatus XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr, + u32 ByteCount); +XStatus XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr, + u32 ByteCount); +void XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef, + XEmac_SgHandler FuncPtr); +void XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef, + XEmac_SgHandler FuncPtr); + +void XEmac_IntrHandlerDma(void *InstancePtr); /* interrupt handler */ + +/* + * Interrupts with direct FIFO functions in xemac_intr_fifo.c. Also used + * for simple DMA. + */ +XStatus XEmac_FifoSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount); +XStatus XEmac_FifoRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr); +void XEmac_SetFifoRecvHandler(XEmac * InstancePtr, void *CallBackRef, + XEmac_FifoHandler FuncPtr); +void XEmac_SetFifoSendHandler(XEmac * InstancePtr, void *CallBackRef, + XEmac_FifoHandler FuncPtr); + +void XEmac_IntrHandlerFifo(void *InstancePtr); /* interrupt handler */ + +/* + * General interrupt-related functions in xemac_intr.c + */ +void XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef, + XEmac_ErrorHandler FuncPtr); + +/* + * MAC configuration in xemac_options.c + */ +XStatus XEmac_SetOptions(XEmac * InstancePtr, u32 OptionFlag); +u32 XEmac_GetOptions(XEmac * InstancePtr); +XStatus XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr); +void XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr); +XStatus XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2); +void XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr); + +/* + * Multicast functions in xemac_multicast.c (not supported by EMAC yet) + */ +XStatus XEmac_MulticastAdd(XEmac * InstancePtr, u8 * AddressPtr); +XStatus XEmac_MulticastClear(XEmac * InstancePtr); + +/* + * PHY configuration in xemac_phy.c + */ +XStatus XEmac_PhyRead(XEmac * InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 * PhyDataPtr); +XStatus XEmac_PhyWrite(XEmac * InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); + +/* + * Statistics in xemac_stats.c + */ +void XEmac_GetStats(XEmac * InstancePtr, XEmac_Stats * StatsPtr); +void XEmac_ClearStats(XEmac * InstancePtr); + +#endif /* end of protection macro */ diff --git a/board/xilinx/xilinx_enet/xemac_g.c b/board/xilinx/xilinx_enet/xemac_g.c new file mode 100644 index 0000000..9340f91 --- /dev/null +++ b/board/xilinx/xilinx_enet/xemac_g.c @@ -0,0 +1,60 @@ +/******************************************************************* +* +* CAUTION: This file is automatically generated by libgen. +* Version: Xilinx EDK 6.1.2 EDK_G.14 +* DO NOT EDIT. +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xemac.h" + +/* +* The configuration table for devices +*/ + +XEmac_Config XEmac_ConfigTable[] = { + { + XPAR_OPB_ETHERNET_0_DEVICE_ID, + XPAR_OPB_ETHERNET_0_BASEADDR, + XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST, + XPAR_OPB_ETHERNET_0_DMA_PRESENT, + XPAR_OPB_ETHERNET_0_MII_EXIST} +}; diff --git a/board/xilinx/xilinx_enet/xemac_i.h b/board/xilinx/xilinx_enet/xemac_i.h new file mode 100644 index 0000000..9c160f3 --- /dev/null +++ b/board/xilinx/xilinx_enet/xemac_i.h @@ -0,0 +1,207 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemac_i.h +* +* This header file contains internal identifiers, which are those shared +* between XEmac components. The identifiers in this file are not intended for +* use external to the driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00b rpm  04/29/02 Moved register definitions to xemac_l.h
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+*
+* +******************************************************************************/ + +#ifndef XEMAC_I_H /* prevent circular inclusions */ +#define XEMAC_I_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xemac.h" +#include "xemac_l.h" + +/************************** Constant Definitions *****************************/ + +/* + * Default buffer descriptor control word masks. The default send BD control + * is set for incrementing the source address by one for each byte transferred, + * and specify that the destination address (FIFO) is local to the device. The + * default receive BD control is set for incrementing the destination address + * by one for each byte transferred, and specify that the source address is + * local to the device. + */ +#define XEM_DFT_SEND_BD_MASK (XDC_DMACR_SOURCE_INCR_MASK | \ + XDC_DMACR_DEST_LOCAL_MASK) +#define XEM_DFT_RECV_BD_MASK (XDC_DMACR_DEST_INCR_MASK | \ + XDC_DMACR_SOURCE_LOCAL_MASK) + +/* + * Masks for the IPIF Device Interrupt enable and status registers. + */ +#define XEM_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */ +#define XEM_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */ +#define XEM_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */ +#define XEM_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */ +#define XEM_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */ + +/* + * Default IPIF Device Interrupt mask when configured for DMA + */ +#define XEM_IPIF_DMA_DFT_MASK (XEM_IPIF_SEND_DMA_MASK | \ + XEM_IPIF_RECV_DMA_MASK | \ + XEM_IPIF_EMAC_MASK | \ + XEM_IPIF_SEND_FIFO_MASK | \ + XEM_IPIF_RECV_FIFO_MASK) + +/* + * Default IPIF Device Interrupt mask when configured without DMA + */ +#define XEM_IPIF_FIFO_DFT_MASK (XEM_IPIF_EMAC_MASK | \ + XEM_IPIF_SEND_FIFO_MASK | \ + XEM_IPIF_RECV_FIFO_MASK) + +#define XEM_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */ +#define XEM_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */ +#define XEM_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */ +#define XEM_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */ + +/* a mask for all transmit interrupts, used in polled mode */ +#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \ + XEM_EIR_XMIT_ERROR_MASK | \ + XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \ + XEM_EIR_XMIT_LFIFO_FULL_MASK) + +/* a mask for all receive interrupts, used in polled mode */ +#define XEM_EIR_RECV_ALL_MASK (XEM_EIR_RECV_DONE_MASK | \ + XEM_EIR_RECV_ERROR_MASK | \ + XEM_EIR_RECV_LFIFO_EMPTY_MASK | \ + XEM_EIR_RECV_LFIFO_OVER_MASK | \ + XEM_EIR_RECV_LFIFO_UNDER_MASK | \ + XEM_EIR_RECV_DFIFO_OVER_MASK | \ + XEM_EIR_RECV_MISSED_FRAME_MASK | \ + XEM_EIR_RECV_COLLISION_MASK | \ + XEM_EIR_RECV_FCS_ERROR_MASK | \ + XEM_EIR_RECV_LEN_ERROR_MASK | \ + XEM_EIR_RECV_SHORT_ERROR_MASK | \ + XEM_EIR_RECV_LONG_ERROR_MASK | \ + XEM_EIR_RECV_ALIGN_ERROR_MASK) + +/* a default interrupt mask for scatter-gather DMA operation */ +#define XEM_EIR_DFT_SG_MASK (XEM_EIR_RECV_ERROR_MASK | \ + XEM_EIR_RECV_LFIFO_OVER_MASK | \ + XEM_EIR_RECV_LFIFO_UNDER_MASK | \ + XEM_EIR_XMIT_SFIFO_OVER_MASK | \ + XEM_EIR_XMIT_SFIFO_UNDER_MASK | \ + XEM_EIR_XMIT_LFIFO_OVER_MASK | \ + XEM_EIR_XMIT_LFIFO_UNDER_MASK | \ + XEM_EIR_RECV_DFIFO_OVER_MASK | \ + XEM_EIR_RECV_MISSED_FRAME_MASK | \ + XEM_EIR_RECV_COLLISION_MASK | \ + XEM_EIR_RECV_FCS_ERROR_MASK | \ + XEM_EIR_RECV_LEN_ERROR_MASK | \ + XEM_EIR_RECV_SHORT_ERROR_MASK | \ + XEM_EIR_RECV_LONG_ERROR_MASK | \ + XEM_EIR_RECV_ALIGN_ERROR_MASK) + +/* a default interrupt mask for non-DMA operation (direct FIFOs) */ +#define XEM_EIR_DFT_FIFO_MASK (XEM_EIR_XMIT_DONE_MASK | \ + XEM_EIR_RECV_DONE_MASK | \ + XEM_EIR_DFT_SG_MASK) + +/* + * Mask for the DMA interrupt enable and status registers when configured + * for scatter-gather DMA. + */ +#define XEM_DMA_SG_INTR_MASK (XDC_IXR_DMA_ERROR_MASK | \ + XDC_IXR_PKT_THRESHOLD_MASK | \ + XDC_IXR_PKT_WAIT_BOUND_MASK | \ + XDC_IXR_SG_END_MASK) + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/* +* +* Clears a structure of given size, in bytes, by setting each byte to 0. +* +* @param StructPtr is a pointer to the structure to be cleared. +* @param NumBytes is the number of bytes in the structure. +* +* @return +* +* None. +* +* @note +* +* Signature: void XEmac_mClearStruct(u8 *StructPtr, unsigned int NumBytes) +* +******************************************************************************/ +#define XEmac_mClearStruct(StructPtr, NumBytes) \ +{ \ + int i; \ + u8 *BytePtr = (u8 *)(StructPtr); \ + for (i=0; i < (unsigned int)(NumBytes); i++) \ + { \ + *BytePtr++ = 0; \ + } \ +} + +/************************** Variable Definitions *****************************/ + +extern XEmac_Config XEmac_ConfigTable[]; + +/************************** Function Prototypes ******************************/ + +void XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus); +void XEmac_CheckFifoRecvError(XEmac * InstancePtr); +void XEmac_CheckFifoSendError(XEmac * InstancePtr); + +#endif /* end of protection macro */ diff --git a/board/xilinx/xilinx_enet/xemac_intr.c b/board/xilinx/xilinx_enet/xemac_intr.c new file mode 100644 index 0000000..b9a2621 --- /dev/null +++ b/board/xilinx/xilinx_enet/xemac_intr.c @@ -0,0 +1,402 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemac_intr.c +* +* This file contains general interrupt-related functions of the XEmac driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* 1.00c rpm  03/31/03 Added comment to indicate that no Receive Length FIFO
+*                     overrun interrupts occur in v1.00l and later of the EMAC
+*                     device. This avoids the need to reset the device on
+*                     receive overruns.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xemac_i.h" +#include "xio.h" +#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* Set the callback function for handling asynchronous errors. The upper layer +* software should call this function during initialization. +* +* The error callback is invoked by the driver within interrupt context, so it +* needs to do its job quickly. If there are potentially slow operations within +* the callback, these should be done at task-level. +* +* The Xilinx errors that must be handled by the callback are: +* - XST_DMA_ERROR indicates an unrecoverable DMA error occurred. This is +* typically a bus error or bus timeout. The handler must reset and +* re-configure the device. +* - XST_FIFO_ERROR indicates an unrecoverable FIFO error occurred. This is a +* deadlock condition in the packet FIFO. The handler must reset and +* re-configure the device. +* - XST_RESET_ERROR indicates an unrecoverable MAC error occurred, usually an +* overrun or underrun. The handler must reset and re-configure the device. +* - XST_DMA_SG_NO_LIST indicates an attempt was made to access a scatter-gather +* DMA list that has not yet been created. +* - XST_DMA_SG_LIST_EMPTY indicates the driver tried to get a descriptor from +* the receive descriptor list, but the list was empty. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param CallBackRef is a reference pointer to be passed back to the adapter in +* the callback. This helps the adapter correlate the callback to a +* particular driver. +* @param FuncPtr is the pointer to the callback function. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void +XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef, + XEmac_ErrorHandler FuncPtr) +{ + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(FuncPtr != NULL); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + InstancePtr->ErrorHandler = FuncPtr; + InstancePtr->ErrorRef = CallBackRef; +} + +/****************************************************************************/ +/* +* +* Check the interrupt status bits of the Ethernet MAC for errors. Errors +* currently handled are: +* - Receive length FIFO overrun. Indicates data was lost due to the receive +* length FIFO becoming full during the reception of a packet. Only a device +* reset clears this condition. +* - Receive length FIFO underrun. An attempt to read an empty FIFO. Only a +* device reset clears this condition. +* - Transmit status FIFO overrun. Indicates data was lost due to the transmit +* status FIFO becoming full following the transmission of a packet. Only a +* device reset clears this condition. +* - Transmit status FIFO underrun. An attempt to read an empty FIFO. Only a +* device reset clears this condition. +* - Transmit length FIFO overrun. Indicates data was lost due to the transmit +* length FIFO becoming full following the transmission of a packet. Only a +* device reset clears this condition. +* - Transmit length FIFO underrun. An attempt to read an empty FIFO. Only a +* device reset clears this condition. +* - Receive data FIFO overrun. Indicates data was lost due to the receive data +* FIFO becoming full during the reception of a packet. +* - Receive data errors: +* - Receive missed frame error. Valid data was lost by the MAC. +* - Receive collision error. Data was lost by the MAC due to a collision. +* - Receive FCS error. Data was dicarded by the MAC due to FCS error. +* - Receive length field error. Data was dicarded by the MAC due to an invalid +* length field in the packet. +* - Receive short error. Data was dicarded by the MAC because a packet was +* shorter than allowed. +* - Receive long error. Data was dicarded by the MAC because a packet was +* longer than allowed. +* - Receive alignment error. Data was truncated by the MAC because its length +* was not byte-aligned. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param IntrStatus is the contents of the interrupt status register to be checked +* +* @return +* +* None. +* +* @note +* +* This function is intended for internal use only. +* +******************************************************************************/ +void +XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus) +{ + u32 ResetError = FALSE; + + /* + * First check for receive fifo overrun/underrun errors. Most require a + * reset by the user to clear, but the data FIFO overrun error does not. + */ + if (IntrStatus & XEM_EIR_RECV_DFIFO_OVER_MASK) { + InstancePtr->Stats.RecvOverrunErrors++; + InstancePtr->Stats.FifoErrors++; + } + + if (IntrStatus & XEM_EIR_RECV_LFIFO_OVER_MASK) { + /* + * Receive Length FIFO overrun interrupts no longer occur in v1.00l + * and later of the EMAC device. Frames are just dropped by the EMAC + * if the length FIFO is full. The user would notice the Receive Missed + * Frame count incrementing without any other errors being reported. + * This code is left here for backward compatibility with v1.00k and + * older EMAC devices. + */ + InstancePtr->Stats.RecvOverrunErrors++; + InstancePtr->Stats.FifoErrors++; + ResetError = TRUE; /* requires a reset */ + } + + if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) { + InstancePtr->Stats.RecvUnderrunErrors++; + InstancePtr->Stats.FifoErrors++; + ResetError = TRUE; /* requires a reset */ + } + + /* + * Now check for general receive errors. Get the latest count where + * available, otherwise just bump the statistic so we know the interrupt + * occurred. + */ + if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) { + if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) { + /* + * Caused by length FIFO or data FIFO overruns on receive side + */ + InstancePtr->Stats.RecvMissedFrameErrors = + XIo_In32(InstancePtr->BaseAddress + + XEM_RMFC_OFFSET); + } + + if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) { + InstancePtr->Stats.RecvCollisionErrors = + XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET); + } + + if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) { + InstancePtr->Stats.RecvFcsErrors = + XIo_In32(InstancePtr->BaseAddress + + XEM_RFCSEC_OFFSET); + } + + if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) { + InstancePtr->Stats.RecvLengthFieldErrors++; + } + + if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) { + InstancePtr->Stats.RecvShortErrors++; + } + + if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) { + InstancePtr->Stats.RecvLongErrors++; + } + + if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) { + InstancePtr->Stats.RecvAlignmentErrors = + XIo_In32(InstancePtr->BaseAddress + + XEM_RAEC_OFFSET); + } + + /* + * Bump recv interrupts stats only if not scatter-gather DMA (this + * stat gets bumped elsewhere in that case) + */ + if (!XEmac_mIsSgDma(InstancePtr)) { + InstancePtr->Stats.RecvInterrupts++; /* TODO: double bump? */ + } + + } + + /* + * Check for transmit errors. These apply to both DMA and non-DMA modes + * of operation. The entire device should be reset after overruns or + * underruns. + */ + if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | + XEM_EIR_XMIT_LFIFO_OVER_MASK)) { + InstancePtr->Stats.XmitOverrunErrors++; + InstancePtr->Stats.FifoErrors++; + ResetError = TRUE; + } + + if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | + XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { + InstancePtr->Stats.XmitUnderrunErrors++; + InstancePtr->Stats.FifoErrors++; + ResetError = TRUE; + } + + if (ResetError) { + /* + * If a reset error occurred, disable the EMAC interrupts since the + * reset-causing interrupt(s) is latched in the EMAC - meaning it will + * keep occurring until the device is reset. In order to give the higher + * layer software time to reset the device, we have to disable the + * overrun/underrun interrupts until that happens. We trust that the + * higher layer resets the device. We are able to get away with disabling + * all EMAC interrupts since the only interrupts it generates are for + * error conditions, and we don't care about any more errors right now. + */ + XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, 0); + + /* + * Invoke the error handler callback, which should result in a reset + * of the device by the upper layer software. + */ + InstancePtr->ErrorHandler(InstancePtr->ErrorRef, + XST_RESET_ERROR); + } +} + +/*****************************************************************************/ +/* +* +* Check the receive packet FIFO for errors. FIFO error interrupts are: +* - Deadlock. See the XPacketFifo component for a description of deadlock on a +* FIFO. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* Although the function returns void, it can return an asynchronous error to the +* application through the error handler. It can return XST_FIFO_ERROR if a FIFO +* error occurred. +* +* @note +* +* This function is intended for internal use only. +* +******************************************************************************/ +void +XEmac_CheckFifoRecvError(XEmac * InstancePtr) +{ + /* + * Although the deadlock is currently the only interrupt from a packet + * FIFO, make sure it is deadlocked before taking action. There is no + * need to clear this interrupt since it requires a reset of the device. + */ + if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) { + u32 IntrEnable; + + InstancePtr->Stats.FifoErrors++; + + /* + * Invoke the error callback function, which should result in a reset + * of the device by the upper layer software. We first need to disable + * the FIFO interrupt, since otherwise the upper layer thread that + * handles the reset may never run because this interrupt condition + * doesn't go away until a reset occurs (there is no way to ack it). + */ + IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress); + XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress, + IntrEnable & ~XEM_IPIF_RECV_FIFO_MASK); + + InstancePtr->ErrorHandler(InstancePtr->ErrorRef, + XST_FIFO_ERROR); + } +} + +/*****************************************************************************/ +/* +* +* Check the send packet FIFO for errors. FIFO error interrupts are: +* - Deadlock. See the XPacketFifo component for a description of deadlock on a +* FIFO. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* Although the function returns void, it can return an asynchronous error to the +* application through the error handler. It can return XST_FIFO_ERROR if a FIFO +* error occurred. +* +* @note +* +* This function is intended for internal use only. +* +******************************************************************************/ +void +XEmac_CheckFifoSendError(XEmac * InstancePtr) +{ + /* + * Although the deadlock is currently the only interrupt from a packet + * FIFO, make sure it is deadlocked before taking action. There is no + * need to clear this interrupt since it requires a reset of the device. + */ + if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) { + u32 IntrEnable; + + InstancePtr->Stats.FifoErrors++; + + /* + * Invoke the error callback function, which should result in a reset + * of the device by the upper layer software. We first need to disable + * the FIFO interrupt, since otherwise the upper layer thread that + * handles the reset may never run because this interrupt condition + * doesn't go away until a reset occurs (there is no way to ack it). + */ + IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress); + XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress, + IntrEnable & ~XEM_IPIF_SEND_FIFO_MASK); + + InstancePtr->ErrorHandler(InstancePtr->ErrorRef, + XST_FIFO_ERROR); + } +} diff --git a/board/xilinx/xilinx_enet/xemac_intr_dma.c b/board/xilinx/xilinx_enet/xemac_intr_dma.c new file mode 100644 index 0000000..567abb4 --- /dev/null +++ b/board/xilinx/xilinx_enet/xemac_intr_dma.c @@ -0,0 +1,1344 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemac_intr_dma.c +* +* Contains functions used in interrupt mode when configured with scatter-gather +* DMA. +* +* The interrupt handler, XEmac_IntrHandlerDma(), must be connected by the user +* to the interrupt controller. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA and the delay
+*                     argument to SgSend
+* 1.00c rpm  02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
+*                     from SetPktThreshold in the internal DMA driver. Also
+*                     avoided compiler warnings by initializing Result in the
+*                     interrupt service routines.
+* 1.00c rpm  03/26/03 Fixed a problem in the interrupt service routines where
+*                     the interrupt status was toggled clear after a call to
+*                     ErrorHandler, but if ErrorHandler reset the device the
+*                     toggle actually asserted the interrupt because the
+*                     reset had cleared it.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xemac_i.h" +#include "xio.h" +#include "xbuf_descriptor.h" +#include "xdma_channel.h" +#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +static void HandleDmaRecvIntr(XEmac * InstancePtr); +static void HandleDmaSendIntr(XEmac * InstancePtr); +static void HandleEmacDmaIntr(XEmac * InstancePtr); + +/*****************************************************************************/ +/** +* +* Send an Ethernet frame using scatter-gather DMA. The caller attaches the +* frame to one or more buffer descriptors, then calls this function once for +* each descriptor. The caller is responsible for allocating and setting up the +* descriptor. An entire Ethernet frame may or may not be contained within one +* descriptor. This function simply inserts the descriptor into the scatter- +* gather engine's transmit list. The caller is responsible for providing mutual +* exclusion to guarantee that a frame is contiguous in the transmit list. The +* buffer attached to the descriptor must be word-aligned. +* +* The driver updates the descriptor with the device control register before +* being inserted into the transmit list. If this is the last descriptor in +* the frame, the inserts are committed, which means the descriptors for this +* frame are now available for transmission. +* +* It is assumed that the upper layer software supplies a correctly formatted +* Ethernet frame, including the destination and source addresses, the +* type/length field, and the data field. It is also assumed that upper layer +* software does not append FCS at the end of the frame. +* +* The buffer attached to the descriptor must be word-aligned on the front end. +* +* This call is non-blocking. Notification of error or successful transmission +* is done asynchronously through the send or error callback function. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param BdPtr is the address of a descriptor to be inserted into the transmit +* ring. +* @param Delay indicates whether to start the scatter-gather DMA channel +* immediately, or whether to wait. This allows the user to build up a +* list of more than one descriptor before starting the transmission of +* the packets, which allows the application to keep up with DMA and have +* a constant stream of frames being transmitted. Use XEM_SGDMA_NODELAY or +* XEM_SGDMA_DELAY, defined in xemac.h, as the value of this argument. If +* the user chooses to delay and build a list, the user must call this +* function with the XEM_SGDMA_NODELAY option or call XEmac_Start() to +* kick off the tranmissions. +* +* @return +* +* - XST_SUCCESS if the buffer was successfull sent +* - XST_DEVICE_IS_STOPPED if the Ethernet MAC has not been started yet +* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode +* - XST_DMA_SG_LIST_FULL if the descriptor list for the DMA channel is full +* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into +* the list because a locked descriptor exists at the insert point +* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the +* list, the DMA channel believes there are no new descriptors to commit. If +* this is ever encountered, there is likely a thread mutual exclusion problem +* on transmit. +* +* @note +* +* This function is not thread-safe. The user must provide mutually exclusive +* access to this function if there are to be multiple threads that can call it. +* +* @internal +* +* A status that should never be returned from this function, although +* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device +* requires a list to be created, and this function requires the device to be +* started. +* +******************************************************************************/ +XStatus +XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay) +{ + XStatus Result; + u32 BdControl; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(BdPtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * Be sure the device is configured for scatter-gather DMA, then be sure + * it is started. + */ + if (!XEmac_mIsSgDma(InstancePtr)) { + return XST_NOT_SGDMA; + } + + /* + * Set some descriptor control word defaults (source address increment + * and local destination address) and the destination address + * (the FIFO). These are the same for every transmit descriptor. + */ + BdControl = XBufDescriptor_GetControl(BdPtr); + XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_SEND_BD_MASK); + + XBufDescriptor_SetDestAddress(BdPtr, + InstancePtr->BaseAddress + + XEM_PFIFO_TXDATA_OFFSET); + + /* + * Put the descriptor in the send list. The DMA component accesses data + * here that can also be modified in interrupt context, so a critical + * section is required. + */ + XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); + + Result = XDmaChannel_PutDescriptor(&InstancePtr->SendChannel, BdPtr); + if (Result != XST_SUCCESS) { + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + return Result; + } + + /* + * If this is the last buffer in the frame, commit the inserts and start + * the DMA engine if necessary + */ + if (XBufDescriptor_IsLastControl(BdPtr)) { + Result = XDmaChannel_CommitPuts(&InstancePtr->SendChannel); + if (Result != XST_SUCCESS) { + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + return Result; + } + + if (Delay == XEM_SGDMA_NODELAY) { + /* + * Start the DMA channel. Ignore the return status since we know the + * list exists and has at least one entry and we don't care if the + * channel is already started. The DMA component accesses data here + * that can be modified at interrupt or task levels, so a critical + * section is required. + */ + (void) XDmaChannel_SgStart(&InstancePtr->SendChannel); + } + } + + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Add a descriptor, with an attached empty buffer, into the receive descriptor +* list. The buffer attached to the descriptor must be word-aligned. This is +* used by the upper layer software during initialization when first setting up +* the receive descriptors, and also during reception of frames to replace +* filled buffers with empty buffers. This function can be called when the +* device is started or stopped. Note that it does start the scatter-gather DMA +* engine. Although this is not necessary during initialization, it is not a +* problem during initialization because the MAC receiver is not yet started. +* +* The buffer attached to the descriptor must be word-aligned on both the front +* end and the back end. +* +* Notification of received frames are done asynchronously through the receive +* callback function. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param BdPtr is a pointer to the buffer descriptor that will be added to the +* descriptor list. +* +* @return +* +* - XST_SUCCESS if a descriptor was successfully returned to the driver +* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode +* - XST_DMA_SG_LIST_FULL if the receive descriptor list is full +* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into +* the list because a locked descriptor exists at the insert point. +* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the +* list, the DMA channel believes there are no new descriptors to commit. +* +* @internal +* +* A status that should never be returned from this function, although +* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device +* requires a list to be created, and this function requires the device to be +* started. +* +******************************************************************************/ +XStatus +XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr) +{ + XStatus Result; + u32 BdControl; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(BdPtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * Be sure the device is configured for scatter-gather DMA + */ + if (!XEmac_mIsSgDma(InstancePtr)) { + return XST_NOT_SGDMA; + } + + /* + * Set some descriptor control word defaults (destination address increment + * and local source address) and the source address (the FIFO). These are + * the same for every receive descriptor. + */ + BdControl = XBufDescriptor_GetControl(BdPtr); + XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_RECV_BD_MASK); + XBufDescriptor_SetSrcAddress(BdPtr, + InstancePtr->BaseAddress + + XEM_PFIFO_RXDATA_OFFSET); + + /* + * Put the descriptor into the channel's descriptor list and commit. + * Although this function is likely called within interrupt context, there + * is the possibility that the upper layer software queues it to a task. + * In this case, a critical section is needed here to protect shared data + * in the DMA component. + */ + XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); + + Result = XDmaChannel_PutDescriptor(&InstancePtr->RecvChannel, BdPtr); + if (Result != XST_SUCCESS) { + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + return Result; + } + + Result = XDmaChannel_CommitPuts(&InstancePtr->RecvChannel); + if (Result != XST_SUCCESS) { + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + return Result; + } + + /* + * Start the DMA channel. Ignore the return status since we know the list + * exists and has at least one entry and we don't care if the channel is + * already started. The DMA component accesses data here that can be + * modified at interrupt or task levels, so a critical section is required. + */ + (void) XDmaChannel_SgStart(&InstancePtr->RecvChannel); + + XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* The interrupt handler for the Ethernet driver when configured with scatter- +* gather DMA. +* +* Get the interrupt status from the IpIf to determine the source of the +* interrupt. The source can be: MAC, Recv Packet FIFO, Send Packet FIFO, Recv +* DMA channel, or Send DMA channel. The packet FIFOs only interrupt during +* "deadlock" conditions. +* +* @param InstancePtr is a pointer to the XEmac instance that just interrupted. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void +XEmac_IntrHandlerDma(void *InstancePtr) +{ + u32 IntrStatus; + XEmac *EmacPtr = (XEmac *) InstancePtr; + + EmacPtr->Stats.TotalIntrs++; + + /* + * Get the interrupt status from the IPIF. There is no clearing of + * interrupts in the IPIF. Interrupts must be cleared at the source. + */ + IntrStatus = XIIF_V123B_READ_DIPR(EmacPtr->BaseAddress); + + /* + * See which type of interrupt is being requested, and service it + */ + if (IntrStatus & XEM_IPIF_RECV_DMA_MASK) { /* Receive DMA interrupt */ + EmacPtr->Stats.RecvInterrupts++; + HandleDmaRecvIntr(EmacPtr); + } + + if (IntrStatus & XEM_IPIF_SEND_DMA_MASK) { /* Send DMA interrupt */ + EmacPtr->Stats.XmitInterrupts++; + HandleDmaSendIntr(EmacPtr); + } + + if (IntrStatus & XEM_IPIF_EMAC_MASK) { /* MAC interrupt */ + EmacPtr->Stats.EmacInterrupts++; + HandleEmacDmaIntr(EmacPtr); + } + + if (IntrStatus & XEM_IPIF_RECV_FIFO_MASK) { /* Receive FIFO interrupt */ + EmacPtr->Stats.RecvInterrupts++; + XEmac_CheckFifoRecvError(EmacPtr); + } + + if (IntrStatus & XEM_IPIF_SEND_FIFO_MASK) { /* Send FIFO interrupt */ + EmacPtr->Stats.XmitInterrupts++; + XEmac_CheckFifoSendError(EmacPtr); + } + + if (IntrStatus & XIIF_V123B_ERROR_MASK) { + /* + * An error occurred internal to the IPIF. This is more of a debug and + * integration issue rather than a production error. Don't do anything + * other than clear it, which provides a spot for software to trap + * on the interrupt and begin debugging. + */ + XIIF_V123B_WRITE_DISR(EmacPtr->BaseAddress, + XIIF_V123B_ERROR_MASK); + } +} + +/*****************************************************************************/ +/** +* +* Set the packet count threshold for this device. The device must be stopped +* before setting the threshold. The packet count threshold is used for interrupt +* coalescing, which reduces the frequency of interrupts from the device to the +* processor. In this case, the scatter-gather DMA engine only interrupts when +* the packet count threshold is reached, instead of interrupting for each packet. +* A packet is a generic term used by the scatter-gather DMA engine, and is +* equivalent to an Ethernet frame in our case. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param Direction indicates the channel, send or receive, from which the +* threshold register is read. +* @param Threshold is the value of the packet threshold count used during +* interrupt coalescing. A value of 0 disables the use of packet threshold +* by the hardware. +* +* @return +* +* - XST_SUCCESS if the threshold was successfully set +* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA +* - XST_DEVICE_IS_STARTED if the device has not been stopped +* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on +* asserts would also catch this error. +* +* @note +* +* The packet threshold could be set to larger than the number of descriptors +* allocated to the DMA channel. In this case, the wait bound will take over +* and always indicate data arrival. There was a check in this function that +* returned an error if the treshold was larger than the number of descriptors, +* but that was removed because users would then have to set the threshold +* only after they set descriptor space, which is an order dependency that +* caused confustion. +* +******************************************************************************/ +XStatus +XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold) +{ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * Be sure device is configured for scatter-gather DMA and has been stopped + */ + if (!XEmac_mIsSgDma(InstancePtr)) { + return XST_NOT_SGDMA; + } + + if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + /* + * Based on the direction, set the packet threshold in the + * corresponding DMA channel component. Default to the receive + * channel threshold register (if an invalid Direction is passed). + */ + switch (Direction) { + case XEM_SEND: + return XDmaChannel_SetPktThreshold(&InstancePtr->SendChannel, + Threshold); + + case XEM_RECV: + return XDmaChannel_SetPktThreshold(&InstancePtr->RecvChannel, + Threshold); + + default: + return XST_INVALID_PARAM; + } +} + +/*****************************************************************************/ +/** +* +* Get the value of the packet count threshold for this driver/device. The packet +* count threshold is used for interrupt coalescing, which reduces the frequency +* of interrupts from the device to the processor. In this case, the +* scatter-gather DMA engine only interrupts when the packet count threshold is +* reached, instead of interrupting for each packet. A packet is a generic term +* used by the scatter-gather DMA engine, and is equivalent to an Ethernet frame +* in our case. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param Direction indicates the channel, send or receive, from which the +* threshold register is read. +* @param ThreshPtr is a pointer to the byte into which the current value of the +* packet threshold register will be copied. An output parameter. A value +* of 0 indicates the use of packet threshold by the hardware is disabled. +* +* @return +* +* - XST_SUCCESS if the packet threshold was retrieved successfully +* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA +* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on +* asserts would also catch this error. +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 * ThreshPtr) +{ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV); + XASSERT_NONVOID(ThreshPtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + if (!XEmac_mIsSgDma(InstancePtr)) { + return XST_NOT_SGDMA; + } + + /* + * Based on the direction, return the packet threshold set in the + * corresponding DMA channel component. Default to the value in + * the receive channel threshold register (if an invalid Direction + * is passed). + */ + switch (Direction) { + case XEM_SEND: + *ThreshPtr = + XDmaChannel_GetPktThreshold(&InstancePtr->SendChannel); + break; + + case XEM_RECV: + *ThreshPtr = + XDmaChannel_GetPktThreshold(&InstancePtr->RecvChannel); + break; + + default: + return XST_INVALID_PARAM; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Set the packet wait bound timer for this driver/device. The device must be +* stopped before setting the timer value. The packet wait bound is used during +* interrupt coalescing to trigger an interrupt when not enough packets have been +* received to reach the packet count threshold. A packet is a generic term used +* by the scatter-gather DMA engine, and is equivalent to an Ethernet frame in +* our case. The timer is in milliseconds. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param Direction indicates the channel, send or receive, from which the +* threshold register is read. +* @param TimerValue is the value of the packet wait bound used during interrupt +* coalescing. It is in milliseconds in the range 0 - 1023. A value of 0 +* disables the packet wait bound timer. +* +* @return +* +* - XST_SUCCESS if the packet wait bound was set successfully +* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA +* - XST_DEVICE_IS_STARTED if the device has not been stopped +* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on +* asserts would also catch this error. +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 TimerValue) +{ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV); + XASSERT_NONVOID(TimerValue <= XEM_SGDMA_MAX_WAITBOUND); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * Be sure device is configured for scatter-gather DMA and has been stopped + */ + if (!XEmac_mIsSgDma(InstancePtr)) { + return XST_NOT_SGDMA; + } + + if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + /* + * Based on the direction, set the packet wait bound in the + * corresponding DMA channel component. Default to the receive + * channel wait bound register (if an invalid Direction is passed). + */ + switch (Direction) { + case XEM_SEND: + XDmaChannel_SetPktWaitBound(&InstancePtr->SendChannel, + TimerValue); + break; + + case XEM_RECV: + XDmaChannel_SetPktWaitBound(&InstancePtr->RecvChannel, + TimerValue); + break; + + default: + return XST_INVALID_PARAM; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Get the packet wait bound timer for this driver/device. The packet wait bound +* is used during interrupt coalescing to trigger an interrupt when not enough +* packets have been received to reach the packet count threshold. A packet is a +* generic term used by the scatter-gather DMA engine, and is equivalent to an +* Ethernet frame in our case. The timer is in milliseconds. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param Direction indicates the channel, send or receive, from which the +* threshold register is read. +* @param WaitPtr is a pointer to the byte into which the current value of the +* packet wait bound register will be copied. An output parameter. Units +* are in milliseconds in the range 0 - 1023. A value of 0 indicates the +* packet wait bound timer is disabled. +* +* @return +* +* - XST_SUCCESS if the packet wait bound was retrieved successfully +* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA +* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on +* asserts would also catch this error. +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 * WaitPtr) +{ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV); + XASSERT_NONVOID(WaitPtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + if (!XEmac_mIsSgDma(InstancePtr)) { + return XST_NOT_SGDMA; + } + + /* + * Based on the direction, return the packet wait bound set in the + * corresponding DMA channel component. Default to the value in + * the receive channel wait bound register (if an invalid Direction + * is passed). + */ + switch (Direction) { + case XEM_SEND: + *WaitPtr = + XDmaChannel_GetPktWaitBound(&InstancePtr->SendChannel); + break; + + case XEM_RECV: + *WaitPtr = + XDmaChannel_GetPktWaitBound(&InstancePtr->RecvChannel); + break; + + default: + return XST_INVALID_PARAM; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Give the driver the memory space to be used for the scatter-gather DMA +* receive descriptor list. This function should only be called once, during +* initialization of the Ethernet driver. The memory space must be big enough +* to hold some number of descriptors, depending on the needs of the system. +* The xemac.h file defines minimum and default numbers of descriptors +* which can be used to allocate this memory space. +* +* The memory space must be word-aligned. An assert will occur if asserts are +* turned on and the memory is not word-aligned. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param MemoryPtr is a pointer to the word-aligned memory. +* @param ByteCount is the length, in bytes, of the memory space. +* +* @return +* +* - XST_SUCCESS if the space was initialized successfully +* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA +* - XST_DMA_SG_LIST_EXISTS if this list space has already been created +* +* @note +* +* If the device is configured for scatter-gather DMA, this function must be +* called AFTER the XEmac_Initialize() function because the DMA channel +* components must be initialized before the memory space is set. +* +******************************************************************************/ +XStatus +XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount) +{ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(MemoryPtr != NULL); + XASSERT_NONVOID(ByteCount != 0); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + if (!XEmac_mIsSgDma(InstancePtr)) { + return XST_NOT_SGDMA; + } + + return XDmaChannel_CreateSgList(&InstancePtr->RecvChannel, MemoryPtr, + ByteCount); +} + +/*****************************************************************************/ +/** +* +* Give the driver the memory space to be used for the scatter-gather DMA +* transmit descriptor list. This function should only be called once, during +* initialization of the Ethernet driver. The memory space must be big enough +* to hold some number of descriptors, depending on the needs of the system. +* The xemac.h file defines minimum and default numbers of descriptors +* which can be used to allocate this memory space. +* +* The memory space must be word-aligned. An assert will occur if asserts are +* turned on and the memory is not word-aligned. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param MemoryPtr is a pointer to the word-aligned memory. +* @param ByteCount is the length, in bytes, of the memory space. +* +* @return +* +* - XST_SUCCESS if the space was initialized successfully +* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA +* - XST_DMA_SG_LIST_EXISTS if this list space has already been created +* +* @note +* +* If the device is configured for scatter-gather DMA, this function must be +* called AFTER the XEmac_Initialize() function because the DMA channel +* components must be initialized before the memory space is set. +* +******************************************************************************/ +XStatus +XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount) +{ + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(MemoryPtr != NULL); + XASSERT_NONVOID(ByteCount != 0); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + if (!XEmac_mIsSgDma(InstancePtr)) { + return XST_NOT_SGDMA; + } + + return XDmaChannel_CreateSgList(&InstancePtr->SendChannel, MemoryPtr, + ByteCount); +} + +/*****************************************************************************/ +/** +* +* Set the callback function for handling received frames in scatter-gather DMA +* mode. The upper layer software should call this function during +* initialization. The callback is called once per frame received. The head of +* a descriptor list is passed in along with the number of descriptors in the +* list. Before leaving the callback, the upper layer software should attach a +* new buffer to each descriptor in the list. +* +* The callback is invoked by the driver within interrupt context, so it needs +* to do its job quickly. Sending the received frame up the protocol stack +* should be done at task-level. If there are other potentially slow operations +* within the callback, these too should be done at task-level. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param CallBackRef is a reference pointer to be passed back to the adapter in +* the callback. This helps the adapter correlate the callback to a +* particular driver. +* @param FuncPtr is the pointer to the callback function. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void +XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef, + XEmac_SgHandler FuncPtr) +{ + /* + * Asserted IsDmaSg here instead of run-time check because there is really + * no ill-effects of setting these when not configured for scatter-gather. + */ + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(FuncPtr != NULL); + XASSERT_VOID(XEmac_mIsSgDma(InstancePtr)); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + InstancePtr->SgRecvHandler = FuncPtr; + InstancePtr->SgRecvRef = CallBackRef; +} + +/*****************************************************************************/ +/** +* +* Set the callback function for handling confirmation of transmitted frames in +* scatter-gather DMA mode. The upper layer software should call this function +* during initialization. The callback is called once per frame sent. The head +* of a descriptor list is passed in along with the number of descriptors in +* the list. The callback is responsible for freeing buffers attached to these +* descriptors. +* +* The callback is invoked by the driver within interrupt context, so it needs +* to do its job quickly. If there are potentially slow operations within the +* callback, these should be done at task-level. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param CallBackRef is a reference pointer to be passed back to the adapter in +* the callback. This helps the adapter correlate the callback to a +* particular driver. +* @param FuncPtr is the pointer to the callback function. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +void +XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef, + XEmac_SgHandler FuncPtr) +{ + /* + * Asserted IsDmaSg here instead of run-time check because there is really + * no ill-effects of setting these when not configured for scatter-gather. + */ + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(FuncPtr != NULL); + XASSERT_VOID(XEmac_mIsSgDma(InstancePtr)); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + InstancePtr->SgSendHandler = FuncPtr; + InstancePtr->SgSendRef = CallBackRef; +} + +/*****************************************************************************/ +/* +* +* Handle an interrupt from the DMA receive channel. DMA interrupts are: +* +* - DMA error. DMA encountered a bus error or timeout. This is a fatal error +* that requires reset of the channel. The driver calls the error handler +* of the upper layer software with an error code indicating the device should +* be reset. +* - Packet count threshold reached. For scatter-gather operations, indicates +* the threshold for the number of packets not serviced by software has been +* reached. The driver behaves as follows: +* - Get the value of the packet counter, which tells us how many packets +* are ready to be serviced +* - For each packet +* - For each descriptor, remove it from the scatter-gather list +* - Check for the last descriptor in the frame, and if set +* - Bump frame statistics +* - Call the scatter-gather receive callback function +* - Decrement the packet counter by one +* Note that there are no receive errors reported in the status word of +* the buffer descriptor. If receive errors occur, the MAC drops the +* packet, and we only find out about the errors through various error +* count registers. +* - Packet wait bound reached. For scatter-gather, indicates the time to wait +* for the next packet has expired. The driver follows the same logic as when +* the packet count threshold interrupt is received. +* - Scatter-gather end acknowledge. Hardware has reached the end of the +* descriptor list. The driver follows the same logic as when the packet count +* threshold interrupt is received. In addition, the driver restarts the DMA +* scatter-gather channel in case there are newly inserted descriptors. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* Although the function returns void, there are asynchronous errors that can +* be generated (by calling the ErrorHandler) from this function. These are: +* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from the +* DMA channel, but there was not one ready for software. +* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a fatal +* error that requires reset. +* +* @note +* +* None. +* +******************************************************************************/ +static void +HandleDmaRecvIntr(XEmac * InstancePtr) +{ + u32 IntrStatus; + + /* + * Read the interrupt status + */ + IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->RecvChannel); + + /* + * For packet threshold or wait bound interrupts, process desciptors. Also + * process descriptors on a SG end acknowledgement, which means the end of + * the descriptor list has been reached by the hardware. For receive, this + * is potentially trouble since it means the descriptor list is full, + * unless software can process enough packets quickly enough so the + * hardware has room to put new packets. + */ + if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK | + XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) { + XStatus Result = XST_SUCCESS; + u32 NumFrames; + u32 NumProcessed; + u32 NumBuffers; + u32 NumBytes; + u32 IsLast; + XBufDescriptor *FirstBdPtr; + XBufDescriptor *BdPtr; + + /* + * Get the number of unserviced packets + */ + NumFrames = XDmaChannel_GetPktCount(&InstancePtr->RecvChannel); + + for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) { + IsLast = FALSE; + FirstBdPtr = NULL; + NumBuffers = 0; + NumBytes = 0; + + /* + * For each packet, get the descriptor from the list. On the + * last one in the frame, make the callback to the upper layer. + */ + while (!IsLast) { + Result = + XDmaChannel_GetDescriptor(&InstancePtr-> + RecvChannel, + &BdPtr); + if (Result != XST_SUCCESS) { + /* + * An error getting a buffer descriptor from the list. + * This should not happen, but if it does, report it to + * the error callback and break out of the loops to service + * other interrupts. + */ + InstancePtr->ErrorHandler(InstancePtr-> + ErrorRef, + Result); + break; + } + + /* + * Keep a pointer to the first descriptor in the list, as it + * will be passed to the upper layers in a bit. By the fact + * that we received this packet means no errors occurred, so + * no need to check the device status word for errors. + */ + if (FirstBdPtr == NULL) { + FirstBdPtr = BdPtr; + } + + NumBytes += XBufDescriptor_GetLength(BdPtr); + + /* + * Check to see if this is the last descriptor in the frame, + * and if so, set the IsLast flag to get out of the loop. + */ + if (XBufDescriptor_IsLastStatus(BdPtr)) { + IsLast = TRUE; + } + + /* + * Bump the number of buffers in this packet + */ + NumBuffers++; + + } /* end while loop */ + + /* + * Check for error that occurred inside the while loop, and break + * out of the for loop if there was one so other interrupts can + * be serviced. + */ + if (Result != XST_SUCCESS) { + break; + } + + InstancePtr->Stats.RecvFrames++; + InstancePtr->Stats.RecvBytes += NumBytes; + + /* + * Make the callback to the upper layers, passing it the first + * descriptor in the packet and the number of descriptors in the + * packet. + */ + InstancePtr->SgRecvHandler(InstancePtr->SgRecvRef, + FirstBdPtr, NumBuffers); + + /* + * Decrement the packet count register to reflect the fact we + * just processed a packet + */ + XDmaChannel_DecrementPktCount(&InstancePtr-> + RecvChannel); + + } /* end for loop */ + + /* + * If the interrupt was an end-ack, check the descriptor list again to + * see if it is empty. If not, go ahead and restart the scatter-gather + * channel. This is to fix a possible race condition where, on receive, + * the driver attempted to start a scatter-gather channel that was + * already started, which resulted in no action from the XDmaChannel + * component. But, just after the XDmaChannel component saw that the + * hardware was already started, the hardware stopped because it + * reached the end of the list. In that case, this interrupt is + * generated and we can restart the hardware here. + */ + if (IntrStatus & XDC_IXR_SG_END_MASK) { + /* + * Ignore the return status since we know the list exists and we + * don't care if the list is empty or the channel is already started. + */ + (void) XDmaChannel_SgStart(&InstancePtr->RecvChannel); + } + } + + /* + * All interrupts are handled (except the error below) so acknowledge + * (clear) the interrupts by writing the value read above back to the status + * register. The packet count interrupt must be acknowledged after the + * decrement, otherwise it will come right back. We clear the interrupts + * before we handle the error interrupt because the ErrorHandler should + * result in a reset, which clears the interrupt status register. So we + * don't want to toggle the interrupt back on by writing the interrupt + * status register with an old value after a reset. + */ + XDmaChannel_SetIntrStatus(&InstancePtr->RecvChannel, IntrStatus); + + /* + * Check for DMA errors and call the error callback function if an error + * occurred (DMA bus or timeout error), which should result in a reset of + * the device by the upper layer software. + */ + if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) { + InstancePtr->Stats.DmaErrors++; + InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR); + } +} + +/*****************************************************************************/ +/* +* +* Handle an interrupt from the DMA send channel. DMA interrupts are: +* +* - DMA error. DMA encountered a bus error or timeout. This is a fatal error +* that requires reset of the channel. The driver calls the error handler +* of the upper layer software with an error code indicating the device should +* be reset. +* - Packet count threshold reached. For scatter-gather operations, indicates +* the threshold for the number of packets not serviced by software has been +* reached. The driver behaves as follows: +* - Get the value of the packet counter, which tells us how many packets +* are ready to be serviced +* - For each packet +* - For each descriptor, remove it from the scatter-gather list +* - Check for the last descriptor in the frame, and if set +* - Bump frame statistics +* - Call the scatter-gather receive callback function +* - Decrement the packet counter by one +* Note that there are no receive errors reported in the status word of +* the buffer descriptor. If receive errors occur, the MAC drops the +* packet, and we only find out about the errors through various error +* count registers. +* - Packet wait bound reached. For scatter-gather, indicates the time to wait +* for the next packet has expired. The driver follows the same logic as when +* the packet count threshold interrupt is received. +* - Scatter-gather end acknowledge. Hardware has reached the end of the +* descriptor list. The driver follows the same logic as when the packet count +* threshold interrupt is received. In addition, the driver restarts the DMA +* scatter-gather channel in case there are newly inserted descriptors. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* Although the function returns void, there are asynchronous errors +* that can be generated from this function. These are: +* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from +* the DMA channel, but there was not one ready for software. +* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a +* fatal error that requires reset. +* +* @note +* +* None. +* +******************************************************************************/ +static void +HandleDmaSendIntr(XEmac * InstancePtr) +{ + u32 IntrStatus; + + /* + * Read the interrupt status + */ + IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->SendChannel); + + /* + * For packet threshold or wait bound interrupt, process descriptors. Also + * process descriptors on a SG end acknowledgement, which means the end of + * the descriptor list has been reached by the hardware. For transmit, + * this is a normal condition during times of light traffic. In fact, the + * wait bound interrupt may be masked for transmit since the end-ack would + * always occur before the wait bound expires. + */ + if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK | + XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) { + XStatus Result = XST_SUCCESS; + u32 NumFrames; + u32 NumProcessed; + u32 NumBuffers; + u32 NumBytes; + u32 IsLast; + XBufDescriptor *FirstBdPtr; + XBufDescriptor *BdPtr; + + /* + * Get the number of unserviced packets + */ + NumFrames = XDmaChannel_GetPktCount(&InstancePtr->SendChannel); + + for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) { + IsLast = FALSE; + FirstBdPtr = NULL; + NumBuffers = 0; + NumBytes = 0; + + /* + * For each frame, traverse the descriptor list and look for + * errors. On the last one in the frame, make the callback. + */ + while (!IsLast) { + Result = + XDmaChannel_GetDescriptor(&InstancePtr-> + SendChannel, + &BdPtr); + if (Result != XST_SUCCESS) { + /* + * An error getting a buffer descriptor from the list. + * This should not happen, but if it does, report it to + * the error callback and break out of the loops to service + * other interrupts + */ + InstancePtr->ErrorHandler(InstancePtr-> + ErrorRef, + Result); + break; + } + + /* + * Keep a pointer to the first descriptor in the list and + * check the device status for errors. The device status is + * only available in the first descriptor of a packet. + */ + if (FirstBdPtr == NULL) { + u32 XmitStatus; + + FirstBdPtr = BdPtr; + + XmitStatus = + XBufDescriptor_GetDeviceStatus + (BdPtr); + if (XmitStatus & + XEM_TSR_EXCESS_DEFERRAL_MASK) { + InstancePtr->Stats. + XmitExcessDeferral++; + } + + if (XmitStatus & + XEM_TSR_LATE_COLLISION_MASK) { + InstancePtr->Stats. + XmitLateCollisionErrors++; + } + } + + NumBytes += XBufDescriptor_GetLength(BdPtr); + + /* + * Check to see if this is the last descriptor in the frame, + * and if so, set the IsLast flag to get out of the loop. The + * transmit channel must check the last bit in the control + * word, not the status word (the DMA engine does not update + * the last bit in the status word for the transmit direction). + */ + if (XBufDescriptor_IsLastControl(BdPtr)) { + IsLast = TRUE; + } + + /* + * Bump the number of buffers in this packet + */ + NumBuffers++; + + } /* end while loop */ + + /* + * Check for error that occurred inside the while loop, and break + * out of the for loop if there was one so other interrupts can + * be serviced. + */ + if (Result != XST_SUCCESS) { + break; + } + + InstancePtr->Stats.XmitFrames++; + InstancePtr->Stats.XmitBytes += NumBytes; + + /* + * Make the callback to the upper layers, passing it the first + * descriptor in the packet and the number of descriptors in the + * packet. + */ + InstancePtr->SgSendHandler(InstancePtr->SgSendRef, + FirstBdPtr, NumBuffers); + + /* + * Decrement the packet count register to reflect the fact we + * just processed a packet + */ + XDmaChannel_DecrementPktCount(&InstancePtr-> + SendChannel); + + } /* end for loop */ + + /* + * If the interrupt was an end-ack, check the descriptor list again to + * see if it is empty. If not, go ahead and restart the scatter-gather + * channel. This is to fix a possible race condition where, on transmit, + * the driver attempted to start a scatter-gather channel that was + * already started, which resulted in no action from the XDmaChannel + * component. But, just after the XDmaChannel component saw that the + * hardware was already started, the hardware stopped because it + * reached the end of the list. In that case, this interrupt is + * generated and we can restart the hardware here. + */ + if (IntrStatus & XDC_IXR_SG_END_MASK) { + /* + * Ignore the return status since we know the list exists and we + * don't care if the list is empty or the channel is already started. + */ + (void) XDmaChannel_SgStart(&InstancePtr->SendChannel); + } + } + + /* + * All interrupts are handled (except the error below) so acknowledge + * (clear) the interrupts by writing the value read above back to the status + * register. The packet count interrupt must be acknowledged after the + * decrement, otherwise it will come right back. We clear the interrupts + * before we handle the error interrupt because the ErrorHandler should + * result in a reset, which clears the interrupt status register. So we + * don't want to toggle the interrupt back on by writing the interrupt + * status register with an old value after a reset. + */ + XDmaChannel_SetIntrStatus(&InstancePtr->SendChannel, IntrStatus); + + /* + * Check for DMA errors and call the error callback function if an error + * occurred (DMA bus or timeout error), which should result in a reset of + * the device by the upper layer software. + */ + if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) { + InstancePtr->Stats.DmaErrors++; + InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR); + } +} + +/*****************************************************************************/ +/* +* +* Handle an interrupt from the Ethernet MAC when configured with scatter-gather +* DMA. The only interrupts handled in this case are errors. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* None. +* +* @note +* +* None. +* +******************************************************************************/ +static void +HandleEmacDmaIntr(XEmac * InstancePtr) +{ + u32 IntrStatus; + + /* + * When configured with DMA, the EMAC generates interrupts only when errors + * occur. We clear the interrupts immediately so that any latched status + * interrupt bits will reflect the true status of the device, and so any + * pulsed interrupts (non-status) generated during the Isr will not be lost. + */ + IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); + XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, IntrStatus); + + /* + * Check the MAC for errors + */ + XEmac_CheckEmacError(InstancePtr, IntrStatus); +} diff --git a/board/xilinx/xilinx_enet/xemac_l.h b/board/xilinx/xilinx_enet/xemac_l.h new file mode 100644 index 0000000..a463937 --- /dev/null +++ b/board/xilinx/xilinx_enet/xemac_l.h @@ -0,0 +1,462 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemac_l.h +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the device. High-level driver functions +* are defined in xemac.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm  04/26/02 First release
+* 1.00b rmm  09/23/02 Added XEmac_mPhyReset macro
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+*
+* +******************************************************************************/ + +#ifndef XEMAC_L_H /* prevent circular inclusions */ +#define XEMAC_L_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xio.h" + +/************************** Constant Definitions *****************************/ + +/* Offset of the MAC registers from the IPIF base address */ +#define XEM_REG_OFFSET 0x1100UL + +/* + * Register offsets for the Ethernet MAC. Each register is 32 bits. + */ +#define XEM_EMIR_OFFSET (XEM_REG_OFFSET + 0x0) /* EMAC Module ID */ +#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ +#define XEM_IFGP_OFFSET (XEM_REG_OFFSET + 0x8) /* Interframe Gap */ +#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ +#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ +#define XEM_MGTCR_OFFSET (XEM_REG_OFFSET + 0x14) /* MII mgmt control */ +#define XEM_MGTDR_OFFSET (XEM_REG_OFFSET + 0x18) /* MII mgmt data */ +#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ +#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ +#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ +#define XEM_RMFC_OFFSET (XEM_REG_OFFSET + 0x28) /* Rx missed frames */ +#define XEM_RCC_OFFSET (XEM_REG_OFFSET + 0x2C) /* Rx collisions */ +#define XEM_RFCSEC_OFFSET (XEM_REG_OFFSET + 0x30) /* Rx FCS errors */ +#define XEM_RAEC_OFFSET (XEM_REG_OFFSET + 0x34) /* Rx alignment errors */ +#define XEM_TEDC_OFFSET (XEM_REG_OFFSET + 0x38) /* Transmit excess + * deferral cnt */ + +/* + * Register offsets for the IPIF components + */ +#define XEM_ISR_OFFSET 0x20UL /* Interrupt status */ + +#define XEM_DMA_OFFSET 0x2300UL +#define XEM_DMA_SEND_OFFSET (XEM_DMA_OFFSET + 0x0) /* DMA send channel */ +#define XEM_DMA_RECV_OFFSET (XEM_DMA_OFFSET + 0x40) /* DMA recv channel */ + +#define XEM_PFIFO_OFFSET 0x2000UL +#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) /* Tx registers */ +#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) /* Rx registers */ +#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) /* Tx keyhole */ +#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* Rx keyhole */ + +/* + * EMAC Module Identification Register (EMIR) + */ +#define XEM_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */ +#define XEM_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */ + +/* + * EMAC Control Register (ECR) + */ +#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL /* Full duplex mode */ +#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL /* Reset transmitter */ +#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL /* Enable transmitter */ +#define XEM_ECR_RECV_RESET_MASK 0x10000000UL /* Reset receiver */ +#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL /* Enable receiver */ +#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL /* Enable PHY */ +#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad insert */ +#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS insert */ +#define XEM_ECR_XMIT_ADDR_INSERT_MASK 0x00800000UL /* Enable xmit source addr + * insertion */ +#define XEM_ECR_XMIT_ERROR_INSERT_MASK 0x00400000UL /* Insert xmit error */ +#define XEM_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000UL /* Enable xmit source addr + * overwrite */ +#define XEM_ECR_LOOPBACK_MASK 0x00100000UL /* Enable internal + * loopback */ +#define XEM_ECR_RECV_STRIP_ENABLE_MASK 0x00080000UL /* Enable recv pad/fcs strip */ +#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast addr */ +#define XEM_ECR_MULTI_ENABLE_MASK 0x00010000UL /* Enable multicast addr */ +#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast addr */ +#define XEM_ECR_PROMISC_ENABLE_MASK 0x00004000UL /* Enable promiscuous mode */ +#define XEM_ECR_RECV_ALL_MASK 0x00002000UL /* Receive all frames */ +#define XEM_ECR_RESERVED2_MASK 0x00001000UL /* Reserved */ +#define XEM_ECR_MULTI_HASH_ENABLE_MASK 0x00000800UL /* Enable multicast hash */ +#define XEM_ECR_PAUSE_FRAME_MASK 0x00000400UL /* Interpret pause frames */ +#define XEM_ECR_CLEAR_HASH_MASK 0x00000200UL /* Clear hash table */ +#define XEM_ECR_ADD_HASH_ADDR_MASK 0x00000100UL /* Add hash table address */ + +/* + * Interframe Gap Register (IFGR) + */ +#define XEM_IFGP_PART1_MASK 0xF8000000UL /* Interframe Gap Part1 */ +#define XEM_IFGP_PART1_SHIFT 27 +#define XEM_IFGP_PART2_MASK 0x07C00000UL /* Interframe Gap Part2 */ +#define XEM_IFGP_PART2_SHIFT 22 + +/* + * Station Address High Register (SAH) + */ +#define XEM_SAH_ADDR_MASK 0x0000FFFFUL /* Station address high bytes */ + +/* + * Station Address Low Register (SAL) + */ +#define XEM_SAL_ADDR_MASK 0xFFFFFFFFUL /* Station address low bytes */ + +/* + * MII Management Control Register (MGTCR) + */ +#define XEM_MGTCR_START_MASK 0x80000000UL /* Start/Busy */ +#define XEM_MGTCR_RW_NOT_MASK 0x40000000UL /* Read/Write Not (direction) */ +#define XEM_MGTCR_PHY_ADDR_MASK 0x3E000000UL /* PHY address */ +#define XEM_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */ +#define XEM_MGTCR_REG_ADDR_MASK 0x01F00000UL /* Register address */ +#define XEM_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */ +#define XEM_MGTCR_MII_ENABLE_MASK 0x00080000UL /* Enable MII from EMAC */ +#define XEM_MGTCR_RD_ERROR_MASK 0x00040000UL /* MII mgmt read error */ + +/* + * MII Management Data Register (MGTDR) + */ +#define XEM_MGTDR_DATA_MASK 0x0000FFFFUL /* MII data */ + +/* + * Receive Packet Length Register (RPLR) + */ +#define XEM_RPLR_LENGTH_MASK 0x0000FFFFUL /* Receive packet length */ + +/* + * Transmit Packet Length Register (TPLR) + */ +#define XEM_TPLR_LENGTH_MASK 0x0000FFFFUL /* Transmit packet length */ + +/* + * Transmit Status Register (TSR) + */ +#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */ +#define XEM_TSR_FIFO_UNDERRUN_MASK 0x40000000UL /* Packet FIFO underrun */ +#define XEM_TSR_ATTEMPTS_MASK 0x3E000000UL /* Transmission attempts */ +#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */ + +/* + * Receive Missed Frame Count (RMFC) + */ +#define XEM_RMFC_DATA_MASK 0x0000FFFFUL + +/* + * Receive Collision Count (RCC) + */ +#define XEM_RCC_DATA_MASK 0x0000FFFFUL + +/* + * Receive FCS Error Count (RFCSEC) + */ +#define XEM_RFCSEC_DATA_MASK 0x0000FFFFUL + +/* + * Receive Alignment Error Count (RALN) + */ +#define XEM_RAEC_DATA_MASK 0x0000FFFFUL + +/* + * Transmit Excess Deferral Count (TEDC) + */ +#define XEM_TEDC_DATA_MASK 0x0000FFFFUL + +/* + * EMAC Interrupt Registers (Status and Enable) masks. These registers are + * part of the IPIF IP Interrupt registers + */ +#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */ +#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */ +#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */ +#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */ +#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */ +#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */ +#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */ +#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo + * overrun */ +#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo + * underrun */ +#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo + * overrun */ +#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo + * underrun */ +#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo + * overrun */ +#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo + * underrun */ +#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt + * received */ +#define XEM_EIR_RECV_DFIFO_OVER_MASK 0x00004000UL /* Receive data fifo + * overrun */ +#define XEM_EIR_RECV_MISSED_FRAME_MASK 0x00008000UL /* Receive missed frame + * error */ +#define XEM_EIR_RECV_COLLISION_MASK 0x00010000UL /* Receive collision + * error */ +#define XEM_EIR_RECV_FCS_ERROR_MASK 0x00020000UL /* Receive FCS error */ +#define XEM_EIR_RECV_LEN_ERROR_MASK 0x00040000UL /* Receive length field + * error */ +#define XEM_EIR_RECV_SHORT_ERROR_MASK 0x00080000UL /* Receive short frame + * error */ +#define XEM_EIR_RECV_LONG_ERROR_MASK 0x00100000UL /* Receive long frame + * error */ +#define XEM_EIR_RECV_ALIGN_ERROR_MASK 0x00200000UL /* Receive alignment + * error */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/***************************************************************************** +* +* Low-level driver macros and functions. The list below provides signatures +* to help the user use the macros. +* +* u32 XEmac_mReadReg(u32 BaseAddress, int RegOffset) +* void XEmac_mWriteReg(u32 BaseAddress, int RegOffset, u32 Mask) +* +* void XEmac_mSetControlReg(u32 BaseAddress, u32 Mask) +* void XEmac_mSetMacAddress(u32 BaseAddress, u8 *AddressPtr) +* +* void XEmac_mEnable(u32 BaseAddress) +* void XEmac_mDisable(u32 BaseAddress) +* +* u32 XEmac_mIsTxDone(u32 BaseAddress) +* u32 XEmac_mIsRxEmpty(u32 BaseAddress) +* +* void XEmac_SendFrame(u32 BaseAddress, u8 *FramePtr, int Size) +* int XEmac_RecvFrame(u32 BaseAddress, u8 *FramePtr) +* +*****************************************************************************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XEmac_mReadReg(BaseAddress, RegOffset) \ + XIo_In32((BaseAddress) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XEmac_mWriteReg(BaseAddress, RegOffset, Data) \ + XIo_Out32((BaseAddress) + (RegOffset), (Data)) + +/****************************************************************************/ +/** +* +* Set the contents of the control register. Use the XEM_ECR_* constants +* defined above to create the bit-mask to be written to the register. +* +* @param BaseAddress is the base address of the device +* @param Mask is the 16-bit value to write to the control register +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XEmac_mSetControlReg(BaseAddress, Mask) \ + XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, (Mask)) + +/****************************************************************************/ +/** +* +* Set the station address of the EMAC device. +* +* @param BaseAddress is the base address of the device +* @param AddressPtr is a pointer to a 6-byte MAC address +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XEmac_mSetMacAddress(BaseAddress, AddressPtr) \ +{ \ + u32 MacAddr; \ + \ + MacAddr = ((AddressPtr)[0] << 8) | (AddressPtr)[1]; \ + XIo_Out32((BaseAddress) + XEM_SAH_OFFSET, MacAddr); \ + \ + MacAddr = ((AddressPtr)[2] << 24) | ((AddressPtr)[3] << 16) | \ + ((AddressPtr)[4] << 8) | (AddressPtr)[5]; \ + \ + XIo_Out32((BaseAddress) + XEM_SAL_OFFSET, MacAddr); \ +} + +/****************************************************************************/ +/** +* +* Enable the transmitter and receiver. Preserve the contents of the control +* register. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XEmac_mEnable(BaseAddress) \ +{ \ + u32 Control; \ + Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \ + Control &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); \ + Control |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); \ + XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \ +} + +/****************************************************************************/ +/** +* +* Disable the transmitter and receiver. Preserve the contents of the control +* register. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XEmac_mDisable(BaseAddress) \ + XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, \ + XIo_In32((BaseAddress) + XEM_ECR_OFFSET) & \ + ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK)) + +/****************************************************************************/ +/** +* +* Check to see if the transmission is complete. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if it is done, or FALSE if it is not. +* +* @note None. +* +*****************************************************************************/ +#define XEmac_mIsTxDone(BaseAddress) \ + (XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_XMIT_DONE_MASK) + +/****************************************************************************/ +/** +* +* Check to see if the receive FIFO is empty. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if it is empty, or FALSE if it is not. +* +* @note None. +* +*****************************************************************************/ +#define XEmac_mIsRxEmpty(BaseAddress) \ + (!(XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_RECV_DONE_MASK)) + +/****************************************************************************/ +/** +* +* Reset MII compliant PHY +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XEmac_mPhyReset(BaseAddress) \ +{ \ + u32 Control; \ + Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \ + Control &= ~XEM_ECR_PHY_ENABLE_MASK; \ + XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \ + Control |= XEM_ECR_PHY_ENABLE_MASK; \ + XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \ +} + +/************************** Function Prototypes ******************************/ + +void XEmac_SendFrame(u32 BaseAddress, u8 * FramePtr, int Size); +int XEmac_RecvFrame(u32 BaseAddress, u8 * FramePtr); + +#endif /* end of protection macro */ diff --git a/board/xilinx/xilinx_enet/xemac_options.c b/board/xilinx/xilinx_enet/xemac_options.c new file mode 100644 index 0000000..1f225f8 --- /dev/null +++ b/board/xilinx/xilinx_enet/xemac_options.c @@ -0,0 +1,318 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemac_options.c +* +* Functions in this file handle configuration of the XEmac driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xemac_i.h" +#include "xio.h" + +/************************** Constant Definitions *****************************/ + +#define XEM_MAX_IFG 32 /* Maximum Interframe gap value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/* + * A table of options and masks. This table maps the user-visible options with + * the control register masks. It is used in Set/GetOptions as an alternative + * to a series of if/else pairs. Note that the polled options does not have a + * corresponding entry in the control register, so it does not exist in the + * table. + */ +typedef struct { + u32 Option; + u32 Mask; +} OptionMap; + +static OptionMap OptionsTable[] = { + {XEM_UNICAST_OPTION, XEM_ECR_UNICAST_ENABLE_MASK}, + {XEM_BROADCAST_OPTION, XEM_ECR_BROAD_ENABLE_MASK}, + {XEM_PROMISC_OPTION, XEM_ECR_PROMISC_ENABLE_MASK}, + {XEM_FDUPLEX_OPTION, XEM_ECR_FULL_DUPLEX_MASK}, + {XEM_LOOPBACK_OPTION, XEM_ECR_LOOPBACK_MASK}, + {XEM_MULTICAST_OPTION, XEM_ECR_MULTI_ENABLE_MASK}, + {XEM_FLOW_CONTROL_OPTION, XEM_ECR_PAUSE_FRAME_MASK}, + {XEM_INSERT_PAD_OPTION, XEM_ECR_XMIT_PAD_ENABLE_MASK}, + {XEM_INSERT_FCS_OPTION, XEM_ECR_XMIT_FCS_ENABLE_MASK}, + {XEM_INSERT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_INSERT_MASK}, + {XEM_OVWRT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_OVWRT_MASK}, + {XEM_STRIP_PAD_FCS_OPTION, XEM_ECR_RECV_STRIP_ENABLE_MASK} +}; + +#define XEM_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionMap)) + +/*****************************************************************************/ +/** +* +* Set Ethernet driver/device options. The device must be stopped before +* calling this function. The options are contained within a bit-mask with each +* bit representing an option (i.e., you can OR the options together). A one (1) +* in the bit-mask turns an option on, and a zero (0) turns the option off. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param OptionsFlag is a bit-mask representing the Ethernet options to turn on +* or off. See xemac.h for a description of the available options. +* +* @return +* +* - XST_SUCCESS if the options were set successfully +* - XST_DEVICE_IS_STARTED if the device has not yet been stopped +* +* @note +* +* This function is not thread-safe and makes use of internal resources that are +* shared between the Start, Stop, and SetOptions functions, so if one task +* might be setting device options while another is trying to start the device, +* protection of this shared data (typically using a semaphore) is required. +* +******************************************************************************/ +XStatus +XEmac_SetOptions(XEmac * InstancePtr, u32 OptionsFlag) +{ + u32 ControlReg; + int Index; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET); + + /* + * Loop through the options table, turning the option on or off + * depending on whether the bit is set in the incoming options flag. + */ + for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) { + if (OptionsFlag & OptionsTable[Index].Option) { + ControlReg |= OptionsTable[Index].Mask; /* turn it on */ + } else { + ControlReg &= ~OptionsTable[Index].Mask; /* turn it off */ + } + } + + /* + * TODO: need to validate addr-overwrite only if addr-insert? + */ + + /* + * Now write the control register. Leave it to the upper layers + * to restart the device. + */ + XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg); + + /* + * Check the polled option + */ + if (OptionsFlag & XEM_POLLED_OPTION) { + InstancePtr->IsPolled = TRUE; + } else { + InstancePtr->IsPolled = FALSE; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Get Ethernet driver/device options. The 32-bit value returned is a bit-mask +* representing the options. A one (1) in the bit-mask means the option is on, +* and a zero (0) means the option is off. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* +* @return +* +* The 32-bit value of the Ethernet options. The value is a bit-mask +* representing all options that are currently enabled. See xemac.h for a +* description of the available options. +* +* @note +* +* None. +* +******************************************************************************/ +u32 +XEmac_GetOptions(XEmac * InstancePtr) +{ + u32 OptionsFlag = 0; + u32 ControlReg; + int Index; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * Get the control register to determine which options are currently set. + */ + ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET); + + /* + * Loop through the options table to determine which options are set + */ + for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) { + if (ControlReg & OptionsTable[Index].Mask) { + OptionsFlag |= OptionsTable[Index].Option; + } + } + + if (InstancePtr->IsPolled) { + OptionsFlag |= XEM_POLLED_OPTION; + } + + return OptionsFlag; +} + +/*****************************************************************************/ +/** +* +* Set the Interframe Gap (IFG), which is the time the MAC delays between +* transmitting frames. There are two parts required. The total interframe gap +* is the total of the two parts. The values provided for the Part1 and Part2 +* parameters are multiplied by 4 to obtain the bit-time interval. The first +* part should be the first 2/3 of the total interframe gap. The MAC will reset +* the interframe gap timer if carrier sense becomes true during the period +* defined by interframe gap Part1. Part1 may be shorter than 2/3 the total and +* can be as small as zero. The second part should be the last 1/3 of the total +* interframe gap, but can be as large as the total interframe gap. The MAC +* will not reset the interframe gap timer if carrier sense becomes true during +* the period defined by interframe gap Part2. +* +* The device must be stopped before setting the interframe gap. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param Part1 is the interframe gap part 1 (which will be multiplied by 4 to +* get the bit-time interval). +* @param Part2 is the interframe gap part 2 (which will be multiplied by 4 to +* get the bit-time interval). +* +* @return +* +* - XST_SUCCESS if the interframe gap was set successfully +* - XST_DEVICE_IS_STARTED if the device has not been stopped +* +* @note +* +* None. +* +******************************************************************************/ +XStatus +XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2) +{ + u32 Ifg; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(Part1 < XEM_MAX_IFG); + XASSERT_NONVOID(Part2 < XEM_MAX_IFG); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * Be sure device has been stopped + */ + if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + Ifg = Part1 << XEM_IFGP_PART1_SHIFT; + Ifg |= (Part2 << XEM_IFGP_PART2_SHIFT); + XIo_Out32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET, Ifg); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Get the interframe gap, parts 1 and 2. See the description of interframe gap +* above in XEmac_SetInterframeGap(). +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param Part1Ptr is a pointer to an 8-bit buffer into which the interframe gap +* part 1 value will be copied. +* @param Part2Ptr is a pointer to an 8-bit buffer into which the interframe gap +* part 2 value will be copied. +* +* @return +* +* None. The values of the interframe gap parts are copied into the +* output parameters. +* +******************************************************************************/ +void +XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr) +{ + u32 Ifg; + + XASSERT_VOID(InstancePtr != NULL); + XASSERT_VOID(Part1Ptr != NULL); + XASSERT_VOID(Part2Ptr != NULL); + XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + Ifg = XIo_In32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET); + *Part1Ptr = (Ifg & XEM_IFGP_PART1_MASK) >> XEM_IFGP_PART1_SHIFT; + *Part2Ptr = (Ifg & XEM_IFGP_PART2_MASK) >> XEM_IFGP_PART2_SHIFT; +} diff --git a/board/xilinx/xilinx_enet/xemac_polled.c b/board/xilinx/xilinx_enet/xemac_polled.c new file mode 100644 index 0000000..23768bc --- /dev/null +++ b/board/xilinx/xilinx_enet/xemac_polled.c @@ -0,0 +1,482 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemac_polled.c +* +* Contains functions used when the driver is in polled mode. Use the +* XEmac_SetOptions() function to put the driver into polled mode. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xbasic_types.h" +#include "xemac_i.h" +#include "xio.h" +#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* Send an Ethernet frame in polled mode. The device/driver must be in polled +* mode before calling this function. The driver writes the frame directly to +* the MAC's packet FIFO, then enters a loop checking the device status for +* completion or error. Statistics are updated if an error occurs. The buffer +* to be sent must be word-aligned. +* +* It is assumed that the upper layer software supplies a correctly formatted +* Ethernet frame, including the destination and source addresses, the +* type/length field, and the data field. It is also assumed that upper layer +* software does not append FCS at the end of the frame. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param BufPtr is a pointer to a word-aligned buffer containing the Ethernet +* frame to be sent. +* @param ByteCount is the size of the Ethernet frame. +* +* @return +* +* - XST_SUCCESS if the frame was sent successfully +* - XST_DEVICE_IS_STOPPED if the device has not yet been started +* - XST_NOT_POLLED if the device is not in polled mode +* - XST_FIFO_NO_ROOM if there is no room in the EMAC's length FIFO for this frame +* - XST_FIFO_ERROR if the FIFO was overrun or underrun. This error is critical +* and requires the caller to reset the device. +* - XST_EMAC_COLLISION if the send failed due to excess deferral or late +* collision +* +* @note +* +* There is the possibility that this function will not return if the hardware +* is broken (i.e., it never sets the status bit indicating that transmission is +* done). If this is of concern to the user, the user should provide protection +* from this problem - perhaps by using a different timer thread to monitor the +* PollSend thread. On a 10Mbps MAC, it takes about 1.21 msecs to transmit a +* maximum size Ethernet frame (1518 bytes). On a 100Mbps MAC, it takes about +* 121 usecs to transmit a maximum size Ethernet frame. +* +* @internal +* +* The EMAC uses FIFOs behind its length and status registers. For this reason, +* it is important to keep the length, status, and data FIFOs in sync when +* reading or writing to them. +* +******************************************************************************/ +XStatus +XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount) +{ + u32 IntrStatus; + u32 XmitStatus; + XStatus Result; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(BufPtr != NULL); + XASSERT_NONVOID(ByteCount > XEM_HDR_SIZE); /* send at least 1 byte */ + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * Be sure the device is configured for polled mode and it is started + */ + if (!InstancePtr->IsPolled) { + return XST_NOT_POLLED; + } + + if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STOPPED; + } + + /* + * Check for overruns and underruns for the transmit status and length + * FIFOs and make sure the send packet FIFO is not deadlocked. Any of these + * conditions is bad enough that we do not want to continue. The upper layer + * software should reset the device to resolve the error. + */ + IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); + + /* + * Overrun errors + */ + if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | + XEM_EIR_XMIT_LFIFO_OVER_MASK)) { + InstancePtr->Stats.XmitOverrunErrors++; + InstancePtr->Stats.FifoErrors++; + return XST_FIFO_ERROR; + } + + /* + * Underrun errors + */ + if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | + XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { + InstancePtr->Stats.XmitUnderrunErrors++; + InstancePtr->Stats.FifoErrors++; + return XST_FIFO_ERROR; + } + + if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) { + InstancePtr->Stats.FifoErrors++; + return XST_FIFO_ERROR; + } + + /* + * Before writing to the data FIFO, make sure the length FIFO is not + * full. The data FIFO might not be full yet even though the length FIFO + * is. This avoids an overrun condition on the length FIFO and keeps the + * FIFOs in sync. + */ + if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { + /* + * Clear the latched LFIFO_FULL bit so next time around the most + * current status is represented + */ + XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, + XEM_EIR_XMIT_LFIFO_FULL_MASK); + return XST_FIFO_NO_ROOM; + } + + /* + * This is a non-blocking write. The packet FIFO returns an error if there + * is not enough room in the FIFO for this frame. + */ + Result = + XPacketFifoV100b_Write(&InstancePtr->SendFifo, BufPtr, ByteCount); + if (Result != XST_SUCCESS) { + return Result; + } + + /* + * Loop on the MAC's status to wait for any pause to complete. + */ + IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); + + while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { + IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); + /* + * Clear the pause status from the transmit status register + */ + XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, + IntrStatus & XEM_EIR_XMIT_PAUSE_MASK); + } + + /* + * Set the MAC's transmit packet length register to tell it to transmit + */ + XIo_Out32(InstancePtr->BaseAddress + XEM_TPLR_OFFSET, ByteCount); + + /* + * Loop on the MAC's status to wait for the transmit to complete. The + * transmit status is in the FIFO when the XMIT_DONE bit is set. + */ + do { + IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); + } + while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0); + + XmitStatus = XIo_In32(InstancePtr->BaseAddress + XEM_TSR_OFFSET); + + InstancePtr->Stats.XmitFrames++; + InstancePtr->Stats.XmitBytes += ByteCount; + + /* + * Check for various errors, bump statistics, and return an error status. + */ + + /* + * Overrun errors + */ + if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | + XEM_EIR_XMIT_LFIFO_OVER_MASK)) { + InstancePtr->Stats.XmitOverrunErrors++; + InstancePtr->Stats.FifoErrors++; + return XST_FIFO_ERROR; + } + + /* + * Underrun errors + */ + if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | + XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { + InstancePtr->Stats.XmitUnderrunErrors++; + InstancePtr->Stats.FifoErrors++; + return XST_FIFO_ERROR; + } + + /* + * Clear the interrupt status register of transmit statuses + */ + XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, + IntrStatus & XEM_EIR_XMIT_ALL_MASK); + + /* + * Collision errors are stored in the transmit status register + * instead of the interrupt status register + */ + if (XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) { + InstancePtr->Stats.XmitExcessDeferral++; + return XST_EMAC_COLLISION_ERROR; + } + + if (XmitStatus & XEM_TSR_LATE_COLLISION_MASK) { + InstancePtr->Stats.XmitLateCollisionErrors++; + return XST_EMAC_COLLISION_ERROR; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* Receive an Ethernet frame in polled mode. The device/driver must be in polled +* mode before calling this function. The driver receives the frame directly +* from the MAC's packet FIFO. This is a non-blocking receive, in that if there +* is no frame ready to be received at the device, the function returns with an +* error. The MAC's error status is not checked, so statistics are not updated +* for polled receive. The buffer into which the frame will be received must be +* word-aligned. +* +* @param InstancePtr is a pointer to the XEmac instance to be worked on. +* @param BufPtr is a pointer to a word-aligned buffer into which the received +* Ethernet frame will be copied. +* @param ByteCountPtr is both an input and an output parameter. It is a pointer +* to a 32-bit word that contains the size of the buffer on entry into the +* function and the size the received frame on return from the function. +* +* @return +* +* - XST_SUCCESS if the frame was sent successfully +* - XST_DEVICE_IS_STOPPED if the device has not yet been started +* - XST_NOT_POLLED if the device is not in polled mode +* - XST_NO_DATA if there is no frame to be received from the FIFO +* - XST_BUFFER_TOO_SMALL if the buffer to receive the frame is too small for +* the frame waiting in the FIFO. +* +* @note +* +* Input buffer must be big enough to hold the largest Ethernet frame. Buffer +* must also be 32-bit aligned. +* +* @internal +* +* The EMAC uses FIFOs behind its length and status registers. For this reason, +* it is important to keep the length, status, and data FIFOs in sync when +* reading or writing to them. +* +******************************************************************************/ +XStatus +XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr) +{ + XStatus Result; + u32 PktLength; + u32 IntrStatus; + + XASSERT_NONVOID(InstancePtr != NULL); + XASSERT_NONVOID(BufPtr != NULL); + XASSERT_NONVOID(ByteCountPtr != NULL); + XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); + + /* + * Be sure the device is configured for polled mode and it is started + */ + if (!InstancePtr->IsPolled) { + return XST_NOT_POLLED; + } + + if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STOPPED; + } + + /* + * Make sure the buffer is big enough to hold the maximum frame size. + * We need to do this because as soon as we read the MAC's packet length + * register, which is actually a FIFO, we remove that length from the + * FIFO. We do not want to read the length FIFO without also reading the + * data FIFO since this would get the FIFOs out of sync. So we have to + * make this restriction. + */ + if (*ByteCountPtr < XEM_MAX_FRAME_SIZE) { + return XST_BUFFER_TOO_SMALL; + } + + /* + * First check for packet FIFO deadlock and return an error if it has + * occurred. A reset by the caller is necessary to correct this problem. + */ + if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) { + InstancePtr->Stats.FifoErrors++; + return XST_FIFO_ERROR; + } + + /* + * Get the interrupt status to know what happened (whether an error occurred + * and/or whether frames have been received successfully). When clearing the + * intr status register, clear only statuses that pertain to receive. + */ + IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); + XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, + IntrStatus & XEM_EIR_RECV_ALL_MASK); + + /* + * Check receive errors and bump statistics so the caller will have a clue + * as to why data may not have been received. We continue on if an error + * occurred since there still may be frames that were received successfully. + */ + if (IntrStatus & (XEM_EIR_RECV_LFIFO_OVER_MASK | + XEM_EIR_RECV_DFIFO_OVER_MASK)) { + InstancePtr->Stats.RecvOverrunErrors++; + InstancePtr->Stats.FifoErrors++; + } + + if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) { + InstancePtr->Stats.RecvUnderrunErrors++; + InstancePtr->Stats.FifoErrors++; + } + + /* + * General receive errors + */ + if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) { + if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) { + InstancePtr->Stats.RecvMissedFrameErrors = + XIo_In32(InstancePtr->BaseAddress + + XEM_RMFC_OFFSET); + } + + if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) { + InstancePtr->Stats.RecvCollisionErrors = + XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET); + } + + if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) { + InstancePtr->Stats.RecvFcsErrors = + XIo_In32(InstancePtr->BaseAddress + + XEM_RFCSEC_OFFSET); + } + + if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) { + InstancePtr->Stats.RecvLengthFieldErrors++; + } + + if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) { + InstancePtr->Stats.RecvShortErrors++; + } + + if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) { + InstancePtr->Stats.RecvLongErrors++; + } + + if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) { + InstancePtr->Stats.RecvAlignmentErrors = + XIo_In32(InstancePtr->BaseAddress + + XEM_RAEC_OFFSET); + } + } + + /* + * Before reading from the length FIFO, make sure the length FIFO is not + * empty. We could cause an underrun error if we try to read from an + * empty FIFO. + */ + if ((IntrStatus & XEM_EIR_RECV_DONE_MASK) == 0) { + return XST_NO_DATA; + } + + /* + * Determine, from the MAC, the length of the next packet available + * in the data FIFO (there should be a non-zero length here) + */ + PktLength = XIo_In32(InstancePtr->BaseAddress + XEM_RPLR_OFFSET); + if (PktLength == 0) { + return XST_NO_DATA; + } + + /* + * Write the RECV_DONE bit in the status register to clear it. This bit + * indicates the RPLR is non-empty, and we know it's set at this point. + * We clear it so that subsequent entry into this routine will reflect the + * current status. This is done because the non-empty bit is latched in the + * IPIF, which means it may indicate a non-empty condition even though + * there is something in the FIFO. + */ + XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, XEM_EIR_RECV_DONE_MASK); + + /* + * We assume that the MAC never has a length bigger than the largest + * Ethernet frame, so no need to make another check here. + */ + + /* + * This is a non-blocking read. The FIFO returns an error if there is + * not at least the requested amount of data in the FIFO. + */ + Result = + XPacketFifoV100b_Read(&InstancePtr->RecvFifo, BufPtr, PktLength); + if (Result != XST_SUCCESS) { + return Result; + } + + InstancePtr->Stats.RecvFrames++; + InstancePtr->Stats.RecvBytes += PktLength; + + *ByteCountPtr = PktLength; + + return XST_SUCCESS; +} diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c new file mode 100644 index 0000000..f3ecba7 --- /dev/null +++ b/board/xilinx/xilinx_iic/iic_adapter.c @@ -0,0 +1,530 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2004 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ + +#include +#include +#include +#include +#include "xparameters.h" + +#ifdef CFG_ENV_IS_IN_EEPROM +#include +#include "xiic_l.h" + +#define IIC_DELAY 5000 + +static u8 envStep = 0; /* 0 means crc has not been read */ +const u8 hex[] = "0123456789ABCDEF"; /* lookup table for ML300 CRC */ + +/************************************************************************ + * Use Xilinx provided driver to send data to EEPROM using iic bus. + */ +static void +send(u32 adr, u8 * data, u32 len) +{ + u8 sendBuf[34]; /* first 2-bit is address and others are data */ + u32 pos, wlen; + u32 ret; + + wlen = 32; + for (pos = 0; pos < len; pos += 32) { + if ((len - pos) < 32) + wlen = len - pos; + + /* Put address and data bits together */ + sendBuf[0] = (u8) ((adr + pos) >> 8); + sendBuf[1] = (u8) (adr + pos); + memcpy(&sendBuf[2], &data[pos], wlen); + + /* Send to EEPROM through iic bus */ + ret = XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, + sendBuf, wlen + 2); + + udelay(IIC_DELAY); + } +} + +/************************************************************************ + * Use Xilinx provided driver to read data from EEPROM using the iic bus. + */ +static void +receive(u32 adr, u8 * data, u32 len) +{ + u8 address[2]; + u32 ret; + + address[0] = (u8) (adr >> 8); + address[1] = (u8) adr; + + /* Provide EEPROM address */ + ret = + XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, address, + 2); + /* Receive data from EEPROM */ + ret = + XIic_Recv(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, data, len); +} + +/************************************************************************ + * Convert a hexadecimal string to its equivalent integer value. + */ +static u8 +axtoi(u8 * hexStg) +{ + u8 n; /* position in string */ + u8 m; /* position in digit[] to shift */ + u8 count; /* loop index */ + u8 intValue; /* integer value of hex string */ + u8 digit[2]; /* hold values to convert */ + + for (n = 0; n < 2; n++) { + if (hexStg[n] == '\0') + break; + if (hexStg[n] > 0x29 && hexStg[n] < 0x40) + digit[n] = hexStg[n] & 0x0f; + else if (hexStg[n] >= 'a' && hexStg[n] <= 'f') + digit[n] = (hexStg[n] & 0x0f) + 9; + else if (hexStg[n] >= 'A' && hexStg[n] <= 'F') + digit[n] = (hexStg[n] & 0x0f) + 9; + else + break; + } + + intValue = 0; + count = n; + m = n - 1; + n = 0; + while (n < count) { + intValue = intValue | (digit[n] << (m << 2)); + m--; /* adjust the position to set */ + n++; /* next digit to process */ + } + + return (intValue); +} + +/************************************************************************ + * Convert an integer string to its equivalent value. + */ +static u8 +atoi(uchar * string) +{ + u8 res = 0; + while (*string >= '0' && *string <= '9') { + res *= 10; + res += *string - '0'; + string++; + } + + return res; +} + +/************************************************************************ + * Key-value pairs are separated by "=" sign. + */ +static void +findKey(uchar * buffer, int *loc, u8 len) +{ + u32 i; + + for (i = 0; i < len; i++) + if (buffer[i] == '=') { + *loc = i; + return; + } + + /* return -1 is no "=" sign found */ + *loc = -1; +} + +/************************************************************************ + * Compute a new ML300 CRC when user calls the saveenv command. + * Also update EEPROM with new CRC value. + */ +static u8 +update_crc(u32 len, uchar * data) +{ + uchar temp[6] = { 'C', '=', 0x00, 0x00, 0x00, 0x00 }; + u32 crc; /* new crc value */ + u32 i; + + crc = 0; + + /* calculate new CRC */ + for (i = 0; i < len; i++) + crc += data[i]; + + /* CRC includes key for check sum */ + crc += 'C' + '='; + + /* compose new CRC to be updated */ + temp[2] = hex[(crc >> 4) & 0xf]; + temp[3] = hex[crc & 0xf]; + + /* check to see if env size exceeded */ + if (len + 6 > ENV_SIZE) { + printf("ERROR: not enough space to store CRC on EEPROM"); + return 1; + } + + memcpy(data + len, temp, 6); + return 0; +} + +/************************************************************************ + * Read out ML300 CRC and compare it with a runtime calculated ML300 CRC. + * If equal, then pass back a u-boot CRC value, otherwise pass back + * junk to indicate CRC error. +*/ +static void +read_crc(uchar * buffer, int len) +{ + u32 addr, n; + u32 crc; /* runtime crc */ + u8 old[2] = { 0xff, 0xff }; /* current CRC in EEPROM */ + u8 stop; /* indication of end of env data */ + u8 pre; /* previous EEPROM data bit */ + int i, loc; + + addr = CFG_ENV_OFFSET; /* start from first env address */ + n = 0; + pre = 1; + stop = 1; + crc = 0; + + /* calculate runtime CRC according to ML300 and read back + old CRC stored in the EEPROM */ + while (n < CFG_ENV_SIZE) { + receive(addr, buffer, len); + + /* found two null chars, end of env */ + if ((pre || buffer[0]) == 0) + break; + + findKey(buffer, &loc, len); + + /* found old check sum, read and store old CRC */ + if ((loc == 0 && pre == 'C') + || (loc > 0 && buffer[loc - 1] == 'C')) + receive(addr + loc + 1, old, 2); + + pre = buffer[len - 1]; + + /* calculate runtime ML300 CRC */ + crc += buffer[0]; + i = 1; + do { + crc += buffer[i]; + stop = buffer[i] || buffer[i - 1]; + i++; + } while (stop && (i < len)); + + if (stop == 0) + break; + + n += len; + addr += len; + } + + /* exclude old CRC from runtime calculation */ + crc -= (old[0] + old[1]); + + /* match CRC values, send back u-boot CRC */ + if ((old[0] == hex[(crc >> 4) & 0xf]) + && (old[1] == hex[crc & 0xf])) { + crc = 0; + n = 0; + addr = + CFG_ENV_OFFSET - offsetof(env_t, crc) + offsetof(env_t, + data); + /* calculate u-boot crc */ + while (n < ENV_SIZE) { + receive(addr, buffer, len); + crc = crc32(crc, buffer, len); + n += len; + addr += len; + } + + memcpy(buffer, &crc, 4); + } +} + +/************************************************************************ + * Convert IP address to hexadecimals. + */ +static void +ip_ml300(uchar * s, uchar * res) +{ + char temp[2]; + u8 i; + + res[0] = 0x00; + + for (i = 0; i < 4; i++) { + sprintf(temp, "%02x", atoi(s)); + s = (uchar *)strchr((char *)s, '.') + 1; + strcat((char *)res, temp); + } +} + +/************************************************************************ + * Change 0xff (255), a dummy null char to 0x00. + */ +static void +change_null(uchar * s) +{ + if (s != NULL) { + change_null((uchar *)strchr((char *)s + 1, 255)); + *(strchr((char *)s, 255)) = '\0'; + } +} + +/************************************************************************ + * Update environment variable name and values to u-boot standard. + */ +void +convert_env(void) +{ + char *s; /* pointer to env value */ + char temp[20]; /* temp storage for addresses */ + + /* E -> ethaddr */ + s = getenv("E"); + if (s != NULL) { + sprintf(temp, "%c%c.%c%c.%c%c.%c%c.%c%c.%c%c", + s[0], s[1], s[ 2], s[ 3], + s[4], s[5], s[ 6], s[ 7], + s[8], s[9], s[10], s[11] ); + setenv("ethaddr", temp); + setenv("E", NULL); + } + + /* L -> serial# */ + s = getenv("L"); + if (s != NULL) { + setenv("serial#", s); + setenv("L", NULL); + } + + /* I -> ipaddr */ + s = getenv("I"); + if (s != NULL) { + sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)), + axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6))); + setenv("ipaddr", temp); + setenv("I", NULL); + } + + /* S -> serverip */ + s = getenv("S"); + if (s != NULL) { + sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)), + axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6))); + setenv("serverip", temp); + setenv("S", NULL); + } + + /* A -> bootargs */ + s = getenv("A"); + if (s != NULL) { + setenv("bootargs", s); + setenv("A", NULL); + } + + /* F -> bootfile */ + s = getenv("F"); + if (s != NULL) { + setenv("bootfile", s); + setenv("F", NULL); + } + + /* M -> bootcmd */ + s = getenv("M"); + if (s != NULL) { + setenv("bootcmd", s); + setenv("M", NULL); + } + + /* Don't include C (CRC) */ + setenv("C", NULL); +} + +/************************************************************************ + * Save user modified environment values back to EEPROM. + */ +static void +save_env(void) +{ + char eprom[ENV_SIZE]; /* buffer to be written back to EEPROM */ + char *s, temp[20]; + char ff[] = { 0xff, 0x00 }; /* dummy null value */ + u32 len; /* length of env to be written to EEPROM */ + + eprom[0] = 0x00; + + /* ethaddr -> E */ + s = getenv("ethaddr"); + if (s != NULL) { + strcat(eprom, "E="); + sprintf(temp, "%c%c%c%c%c%c%c%c%c%c%c%c", + *s, *(s + 1), *(s + 3), *(s + 4), *(s + 6), *(s + 7), + *(s + 9), *(s + 10), *(s + 12), *(s + 13), *(s + 15), + *(s + 16)); + strcat(eprom, temp); + strcat(eprom, ff); + } + + /* serial# -> L */ + s = getenv("serial#"); + if (s != NULL) { + strcat(eprom, "L="); + strcat(eprom, s); + strcat(eprom, ff); + } + + /* ipaddr -> I */ + s = getenv("ipaddr"); + if (s != NULL) { + strcat(eprom, "I="); + ip_ml300((uchar *)s, (uchar *)temp); + strcat(eprom, temp); + strcat(eprom, ff); + } + + /* serverip -> S */ + s = getenv("serverip"); + if (s != NULL) { + strcat(eprom, "S="); + ip_ml300((uchar *)s, (uchar *)temp); + strcat(eprom, temp); + strcat(eprom, ff); + } + + /* bootargs -> A */ + s = getenv("bootargs"); + if (s != NULL) { + strcat(eprom, "A="); + strcat(eprom, s); + strcat(eprom, ff); + } + + /* bootfile -> F */ + s = getenv("bootfile"); + if (s != NULL) { + strcat(eprom, "F="); + strcat(eprom, s); + strcat(eprom, ff); + } + + /* bootcmd -> M */ + s = getenv("bootcmd"); + if (s != NULL) { + strcat(eprom, "M="); + strcat(eprom, s); + strcat(eprom, ff); + } + + len = strlen(eprom); /* find env length without crc */ + change_null((uchar *)eprom); /* change 0xff to 0x00 */ + + /* update EEPROM env values if there is enough space */ + if (update_crc(len, (uchar *)eprom) == 0) + send(CFG_ENV_OFFSET, (uchar *)eprom, len + 6); +} + +/************************************************************************ + * U-boot call for EEPROM read associated activities. + */ +int +i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + + if (envStep == 0) { + /* first read call is for crc */ + read_crc(buffer, len); + ++envStep; + return 0; + } else if (envStep == 1) { + /* then read out EEPROM content for runtime u-boot CRC calculation */ + receive(addr, buffer, len); + + if (addr + len - CFG_ENV_OFFSET == CFG_ENV_SIZE) + /* end of runtime crc read */ + ++envStep; + return 0; + } + + if (len < 2) { + /* when call getenv_r */ + receive(addr, buffer, len); + } else if (addr + len < CFG_ENV_OFFSET + CFG_ENV_SIZE) { + /* calling env_relocate(), but don't read out + crc value from EEPROM */ + receive(addr, buffer + 4, len); + } else { + receive(addr, buffer + 4, len - 4); + } + + return 0; + +} + +/************************************************************************ + * U-boot call for EEPROM write acativities. + */ +int +i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + /* save env on last page write called by u-boot */ + if (addr + len >= CFG_ENV_OFFSET + CFG_ENV_SIZE) + save_env(); + + return 0; +} + +/************************************************************************ + * Dummy function. + */ +int +i2c_probe(uchar chip) +{ + return 1; +} + +#endif diff --git a/board/xilinx/xilinx_iic/xiic_l.c b/board/xilinx/xilinx_iic/xiic_l.c new file mode 100644 index 0000000..6b78163 --- /dev/null +++ b/board/xilinx/xilinx_iic/xiic_l.c @@ -0,0 +1,484 @@ +/* $Id: xiic_l.c,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */ +/****************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002 Xilinx Inc. +* All rights reserved. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xiic_l.c +* +* This file contains low-level driver functions that can be used to access the +* device. The user should refer to the hardware device specification for more +* details of the device operation. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- --- -------  -----------------------------------------------
+* 1.01b jhl 5/13/02  First release
+* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup of the
+*		     interrupt status mask was not being done in the loop such
+*		     that a read would sometimes fail on the last byte because
+*		     the transmit error which should have been ignored was
+*		     being used.  This would leave an extra byte in the FIFO
+*		     and the bus throttled such that the next operation would
+*		     also fail.	 Also updated the receive function to not
+*		     disable the device after the last byte until after the
+*		     bus transitions to not busy which is more consistent
+*		     with the expected behavior.
+* 1.01c ecm 12/05/02 new rev
+*
+* +****************************************************************************/ + +/***************************** Include Files *******************************/ + +#include "xbasic_types.h" +#include "xio.h" +#include "xipif_v1_23_b.h" +#include "xiic_l.h" + +/************************** Constant Definitions ***************************/ + +/**************************** Type Definitions *****************************/ + + +/***************** Macros (Inline Functions) Definitions *******************/ + + +/****************************************************************************** +* +* This macro clears the specified interrupt in the IPIF interrupt status +* register. It is non-destructive in that the register is read and only the +* interrupt specified is cleared. Clearing an interrupt acknowledges it. +* +* @param BaseAddress contains the IPIF registers base address. +* +* @param InterruptMask contains the interrupts to be disabled +* +* @return +* +* None. +* +* @note +* +* Signature: void XIic_mClearIisr(u32 BaseAddress, +* u32 InterruptMask); +* +******************************************************************************/ +#define XIic_mClearIisr(BaseAddress, InterruptMask) \ + XIIF_V123B_WRITE_IISR((BaseAddress), \ + XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask)) + +/****************************************************************************** +* +* This macro sends the address for a 7 bit address during both read and write +* operations. It takes care of the details to format the address correctly. +* This macro is designed to be called internally to the drivers. +* +* @param SlaveAddress contains the address of the slave to send to. +* +* @param Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION +* +* @return +* +* None. +* +* @note +* +* Signature: void XIic_mSend7BitAddr(u16 SlaveAddress, u8 Operation); +* +******************************************************************************/ +#define XIic_mSend7BitAddress(BaseAddress, SlaveAddress, Operation) \ +{ \ + u8 LocalAddr = (u8)(SlaveAddress << 1); \ + LocalAddr = (LocalAddr & 0xFE) | (Operation); \ + XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr); \ +} + +/************************** Function Prototypes ****************************/ + +static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, + unsigned ByteCount); +static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, + unsigned ByteCount); + +/************************** Variable Definitions **************************/ + + +/****************************************************************************/ +/** +* Receive data as a master on the IIC bus. This function receives the data +* using polled I/O and blocks until the data has been received. It only +* supports 7 bit addressing and non-repeated start modes of operation. The +* user is responsible for ensuring the bus is not busy if multiple masters +* are present on the bus. +* +* @param BaseAddress contains the base address of the IIC device. +* @param Address contains the 7 bit IIC address of the device to send the +* specified data to. +* @param BufferPtr points to the data to be sent. +* @param ByteCount is the number of bytes to be sent. +* +* @return +* +* The number of bytes received. +* +* @note +* +* None +* +******************************************************************************/ +unsigned XIic_Recv (u32 BaseAddress, u8 Address, + u8 * BufferPtr, unsigned ByteCount) +{ + u8 CntlReg; + unsigned RemainingByteCount; + + /* Tx error is enabled incase the address (7 or 10) has no device to answer + * with Ack. When only one byte of data, must set NO ACK before address goes + * out therefore Tx error must not be enabled as it will go off immediately + * and the Rx full interrupt will be checked. If full, then the one byte + * was received and the Tx error will be disabled without sending an error + * callback msg. + */ + XIic_mClearIisr (BaseAddress, + XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_ARB_LOST_MASK); + + /* Set receive FIFO occupancy depth for 1 byte (zero based) + */ + XIo_Out8 (BaseAddress + XIIC_RFD_REG_OFFSET, 0); + + /* 7 bit slave address, send the address for a read operation + * and set the state to indicate the address has been sent + */ + XIic_mSend7BitAddress (BaseAddress, Address, XIIC_READ_OPERATION); + + /* MSMS gets set after putting data in FIFO. Start the master receive + * operation by setting CR Bits MSMS to Master, if the buffer is only one + * byte, then it should not be acknowledged to indicate the end of data + */ + CntlReg = XIIC_CR_MSMS_MASK | XIIC_CR_ENABLE_DEVICE_MASK; + if (ByteCount == 1) { + CntlReg |= XIIC_CR_NO_ACK_MASK; + } + + /* Write out the control register to start receiving data and call the + * function to receive each byte into the buffer + */ + XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, CntlReg); + + /* Clear the latched interrupt status for the bus not busy bit which must + * be done while the bus is busy + */ + XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK); + + /* Try to receive the data from the IIC bus */ + + RemainingByteCount = RecvData (BaseAddress, BufferPtr, ByteCount); + /* + * The receive is complete, disable the IIC device and return the number of + * bytes that was received + */ + XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0); + + /* Return the number of bytes that was received */ + + return ByteCount - RemainingByteCount; +} + +/****************************************************************************** +* +* Receive the specified data from the device that has been previously addressed +* on the IIC bus. This function assumes that the 7 bit address has been sent +* and it should wait for the transmit of the address to complete. +* +* @param BaseAddress contains the base address of the IIC device. +* @param BufferPtr points to the buffer to hold the data that is received. +* @param ByteCount is the number of bytes to be received. +* +* @return +* +* The number of bytes remaining to be received. +* +* @note +* +* This function does not take advantage of the receive FIFO because it is +* designed for minimal code space and complexity. It contains loops that +* that could cause the function not to return if the hardware is not working. +* +* This function assumes that the calling function will disable the IIC device +* after this function returns. +* +******************************************************************************/ +static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount) +{ + u8 CntlReg; + u32 IntrStatusMask; + u32 IntrStatus; + + /* Attempt to receive the specified number of bytes on the IIC bus */ + + while (ByteCount > 0) { + /* Setup the mask to use for checking errors because when receiving one + * byte OR the last byte of a multibyte message an error naturally + * occurs when the no ack is done to tell the slave the last byte + */ + if (ByteCount == 1) { + IntrStatusMask = + XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK; + } else { + IntrStatusMask = + XIIC_INTR_ARB_LOST_MASK | + XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK; + } + + /* Wait for the previous transmit and the 1st receive to complete + * by checking the interrupt status register of the IPIF + */ + while (1) { + IntrStatus = XIIF_V123B_READ_IISR (BaseAddress); + if (IntrStatus & XIIC_INTR_RX_FULL_MASK) { + break; + } + /* Check the transmit error after the receive full because when + * sending only one byte transmit error will occur because of the + * no ack to indicate the end of the data + */ + if (IntrStatus & IntrStatusMask) { + return ByteCount; + } + } + + CntlReg = XIo_In8 (BaseAddress + XIIC_CR_REG_OFFSET); + + /* Special conditions exist for the last two bytes so check for them + * Note that the control register must be setup for these conditions + * before the data byte which was already received is read from the + * receive FIFO (while the bus is throttled + */ + if (ByteCount == 1) { + /* For the last data byte, it has already been read and no ack + * has been done, so clear MSMS while leaving the device enabled + * so it can get off the IIC bus appropriately with a stop. + */ + XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, + XIIC_CR_ENABLE_DEVICE_MASK); + } + + /* Before the last byte is received, set NOACK to tell the slave IIC + * device that it is the end, this must be done before reading the byte + * from the FIFO + */ + if (ByteCount == 2) { + /* Write control reg with NO ACK allowing last byte to + * have the No ack set to indicate to slave last byte read. + */ + XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, + CntlReg | XIIC_CR_NO_ACK_MASK); + } + + /* Read in data from the FIFO and unthrottle the bus such that the + * next byte is read from the IIC bus + */ + *BufferPtr++ = XIo_In8 (BaseAddress + XIIC_DRR_REG_OFFSET); + + /* Clear the latched interrupt status so that it will be updated with + * the new state when it changes, this must be done after the receive + * register is read + */ + XIic_mClearIisr (BaseAddress, XIIC_INTR_RX_FULL_MASK | + XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_ARB_LOST_MASK); + ByteCount--; + } + + /* Wait for the bus to transition to not busy before returning, the IIC + * device cannot be disabled until this occurs. It should transition as + * the MSMS bit of the control register was cleared before the last byte + * was read from the FIFO. + */ + while (1) { + if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) { + break; + } + } + + return ByteCount; +} + +/****************************************************************************/ +/** +* Send data as a master on the IIC bus. This function sends the data +* using polled I/O and blocks until the data has been sent. It only supports +* 7 bit addressing and non-repeated start modes of operation. The user is +* responsible for ensuring the bus is not busy if multiple masters are present +* on the bus. +* +* @param BaseAddress contains the base address of the IIC device. +* @param Address contains the 7 bit IIC address of the device to send the +* specified data to. +* @param BufferPtr points to the data to be sent. +* @param ByteCount is the number of bytes to be sent. +* +* @return +* +* The number of bytes sent. +* +* @note +* +* None +* +******************************************************************************/ +unsigned XIic_Send (u32 BaseAddress, u8 Address, + u8 * BufferPtr, unsigned ByteCount) +{ + unsigned RemainingByteCount; + + /* Put the address into the FIFO to be sent and indicate that the operation + * to be performed on the bus is a write operation + */ + XIic_mSend7BitAddress (BaseAddress, Address, XIIC_WRITE_OPERATION); + + /* Clear the latched interrupt status so that it will be updated with the + * new state when it changes, this must be done after the address is put + * in the FIFO + */ + XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK | + XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK); + + /* MSMS must be set after putting data into transmit FIFO, indicate the + * direction is transmit, this device is master and enable the IIC device + */ + XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, + XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK | + XIIC_CR_ENABLE_DEVICE_MASK); + + /* Clear the latched interrupt + * status for the bus not busy bit which must be done while the bus is busy + */ + XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK); + + /* Send the specified data to the device on the IIC bus specified by the + * the address + */ + RemainingByteCount = SendData (BaseAddress, BufferPtr, ByteCount); + + /* + * The send is complete, disable the IIC device and return the number of + * bytes that was sent + */ + XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0); + + return ByteCount - RemainingByteCount; +} + +/****************************************************************************** +* +* Send the specified buffer to the device that has been previously addressed +* on the IIC bus. This function assumes that the 7 bit address has been sent +* and it should wait for the transmit of the address to complete. +* +* @param BaseAddress contains the base address of the IIC device. +* @param BufferPtr points to the data to be sent. +* @param ByteCount is the number of bytes to be sent. +* +* @return +* +* The number of bytes remaining to be sent. +* +* @note +* +* This function does not take advantage of the transmit FIFO because it is +* designed for minimal code space and complexity. It contains loops that +* that could cause the function not to return if the hardware is not working. +* +******************************************************************************/ +static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount) +{ + u32 IntrStatus; + + /* Send the specified number of bytes in the specified buffer by polling + * the device registers and blocking until complete + */ + while (ByteCount > 0) { + /* Wait for the transmit to be empty before sending any more data + * by polling the interrupt status register + */ + while (1) { + IntrStatus = XIIF_V123B_READ_IISR (BaseAddress); + + if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_ARB_LOST_MASK | + XIIC_INTR_BNB_MASK)) { + return ByteCount; + } + + if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) { + break; + } + } + /* If there is more than one byte to send then put the next byte to send + * into the transmit FIFO + */ + if (ByteCount > 1) { + XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET, + *BufferPtr++); + } else { + /* Set the stop condition before sending the last byte of data so that + * the stop condition will be generated immediately following the data + * This is done by clearing the MSMS bit in the control register. + */ + XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, + XIIC_CR_ENABLE_DEVICE_MASK | + XIIC_CR_DIR_IS_TX_MASK); + + /* Put the last byte to send in the transmit FIFO */ + + XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET, + *BufferPtr++); + } + + /* Clear the latched interrupt status register and this must be done after + * the transmit FIFO has been written to or it won't clear + */ + XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK); + + /* Update the byte count to reflect the byte sent and clear the latched + * interrupt status so it will be updated for the new state + */ + ByteCount--; + } + + /* Wait for the bus to transition to not busy before returning, the IIC + * device cannot be disabled until this occurs. + * Note that this is different from a receive operation because the stop + * condition causes the bus to go not busy. + */ + while (1) { + if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) { + break; + } + } + + return ByteCount; +} diff --git a/board/xilinx/xilinx_iic/xiic_l.h b/board/xilinx/xilinx_iic/xiic_l.h new file mode 100644 index 0000000..a2c4c49 --- /dev/null +++ b/board/xilinx/xilinx_iic/xiic_l.h @@ -0,0 +1,150 @@ +/* $Id: xiic_l.h,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */ +/***************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002 Xilinx Inc. +* All rights reserved. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xiic_l.h +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the device. High-level driver functions +* are defined in xiic.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  05/07/02 First release
+* 1.01c ecm  12/05/02 new rev
+*
+* +*****************************************************************************/ + +#ifndef XIIC_L_H /* prevent circular inclusions */ +#define XIIC_L_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xbasic_types.h" + +/************************** Constant Definitions ****************************/ + +#define XIIC_MSB_OFFSET 3 + +#define XIIC_REG_OFFSET 0x100 + XIIC_MSB_OFFSET + +/* + * Register offsets in bytes from RegisterBase. Three is added to the + * base offset to access LSB (IBM style) of the word + */ +#define XIIC_CR_REG_OFFSET 0x00+XIIC_REG_OFFSET /* Control Register */ +#define XIIC_SR_REG_OFFSET 0x04+XIIC_REG_OFFSET /* Status Register */ +#define XIIC_DTR_REG_OFFSET 0x08+XIIC_REG_OFFSET /* Data Tx Register */ +#define XIIC_DRR_REG_OFFSET 0x0C+XIIC_REG_OFFSET /* Data Rx Register */ +#define XIIC_ADR_REG_OFFSET 0x10+XIIC_REG_OFFSET /* Address Register */ +#define XIIC_TFO_REG_OFFSET 0x14+XIIC_REG_OFFSET /* Tx FIFO Occupancy */ +#define XIIC_RFO_REG_OFFSET 0x18+XIIC_REG_OFFSET /* Rx FIFO Occupancy */ +#define XIIC_TBA_REG_OFFSET 0x1C+XIIC_REG_OFFSET /* 10 Bit Address reg */ +#define XIIC_RFD_REG_OFFSET 0x20+XIIC_REG_OFFSET /* Rx FIFO Depth reg */ + +/* Control Register masks */ + +#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ +#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ +#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ +#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ +#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ +#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ +#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ + +/* Status Register masks */ + +#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ +#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ +#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ +#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ +#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ +#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ +#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ + +/* IPIF Interrupt Status Register masks Interrupt occurs when... */ + +#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ +#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete*/ +#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ +#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level*/ +#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ +#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ +#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ +#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ + +/* IPIF Device Interrupt Register masks */ + +#define XIIC_IPIF_IIC_MASK 0x00000004UL /* 1=inter enabled */ +#define XIIC_IPIF_ERROR_MASK 0x00000001UL /* 1=inter enabled */ +#define XIIC_IPIF_INTER_ENABLE_MASK (XIIC_IPIF_IIC_MASK | \ + XIIC_IPIF_ERROR_MASK) + +#define XIIC_TX_ADDR_SENT 0x00 +#define XIIC_TX_ADDR_MSTR_RECV_MASK 0x02 + +/* The following constants specify the depth of the FIFOs */ + +#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ +#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ + +/* The following constants specify groups of interrupts that are typically + * enabled or disables at the same time + */ +#define XIIC_TX_INTERRUPTS \ + (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | \ + XIIC_INTR_TX_HALF_MASK) + +#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) + +/* The following constants are used with the following macros to specify the + * operation, a read or write operation. + */ +#define XIIC_READ_OPERATION 1 +#define XIIC_WRITE_OPERATION 0 + +/* The following constants are used with the transmit FIFO fill function to + * specify the role which the IIC device is acting as, a master or a slave. + */ +#define XIIC_MASTER_ROLE 1 +#define XIIC_SLAVE_ROLE 0 + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Function Prototypes *****************************/ + +unsigned XIic_Recv(u32 BaseAddress, u8 Address, + u8 *BufferPtr, unsigned ByteCount); + +unsigned XIic_Send(u32 BaseAddress, u8 Address, + u8 *BufferPtr, unsigned ByteCount); + +#endif /* end of protection macro */ diff --git a/board/xm250/Makefile b/board/xm250/Makefile new file mode 100644 index 0000000..1b0a3f0 --- /dev/null +++ b/board/xm250/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := xm250.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/xm250/config.mk b/board/xm250/config.mk new file mode 100644 index 0000000..8ce0c48 --- /dev/null +++ b/board/xm250/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MicroSys XM250 board: +# + + +# This is the address where U-Boot lives in flash: +#TEXT_BASE = 0 + +# FIXME: armboot does only work correctly when being compiled +# for the addresses _after_ relocation to RAM!! Otherwhise the +# .bss segment is assumed in flash... +TEXT_BASE = 0xA3F80000 diff --git a/board/xm250/flash.c b/board/xm250/flash.c new file mode 100644 index 0000000..aab47a0 --- /dev/null +++ b/board/xm250/flash.c @@ -0,0 +1,536 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +/* Intel-compatible flash ID */ +#define INTEL_COMPAT 0x00890089 +#define INTEL_ALT 0x00B000B0 + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_RESET 0xFFFFFFFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + break; + default: + panic ("configured to many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0] ); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + + case FLASH_28F640J3A: + printf ("28F640J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 32 MB */ + + case (FPW) INTEL_ID_28F640J3A: + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x01000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +/*----------------------------------------------------------------------- + * Set/Clear sector's lock bit, returns: + * 0 - OK + * 1 - Error (timeout, voltage problems, etc.) + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int i; + int rc = 0; + vu_long *addr = (vu_long *)(info->start[sector]); + int flag = disable_interrupts(); + + *addr = INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + } + else { /* Clear sector lock bit */ + *addr = INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = INTEL_CONFIRM; /* clear */ + } + + reset_timer_masked (); + + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + + if (*addr != INTEL_OK) { + printf("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + rc = 1; + } + + if (!rc) + info->protect[sector] = prot; + + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + */ + if (!prot) + { + for (i = 0; i < info->sector_count; i++) + { + if (info->protect[i]) + { + reset_timer_masked (); + addr = (vu_long *)(info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) + { + if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) + { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + } + } + } + + if (flag) + enable_interrupts(); + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} diff --git a/board/xm250/lowlevel_init.S b/board/xm250/lowlevel_init.S new file mode 100644 index 0000000..2ebd395 --- /dev/null +++ b/board/xm250/lowlevel_init.S @@ -0,0 +1,519 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm +/* + .macro SET_LED val + ldr r6, =CRADLE_LED_CLR_REG + ldr r7, =0 + str r7, [r6] + ldr r6, =CRADLE_LED_SET_REG + ldr r7, =\val + str r7, [r6] + .endm +*/ + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + + /* Set up GPIO pins first */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + /* enable GPIO pins */ + ldr r0, =PSSR + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* SET_LED 1 */ + + ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */ + ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */ + str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */ + ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */ + + +/********************************************************************* + * Initlialize Memory Controller + * + * See PXA250 Operating System Developer's Guide + * + * pause for 200 uSecs- allow internal clocks to settle + * *Note: only need this if hard reset... doing it anyway for now + */ + + @ Step 1 + @ ---- Wait 200 usec + ldr r3, =OSCR @ reset the OS Timer Count to zero + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + /* SET_LED 2 */ + +mem_init: + @ get memory controller base address + ldr r1, =MEMC_BASE + + +@**************************************************************************** +@ Step 2 +@ + + @ Step 2a + @ write msc0, read back to ensure data latches + @ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] + + @ write msc1 + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + @ write msc2 + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + @ Step 2b + @ write mecr + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + + @ write mcmem0 + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + + @ write mcmem1 + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + + @ write mcatt0 + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + + @ write mcatt1 + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + + @ write mcio0 + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + + @ write mcio1 + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + + /*SET_LED 3 */ + + @ Step 2c + @ fly-by-dma is defeatured on this part + @ write flycnfg + @ldr r2, =CFG_FLYCNFG_VAL + @str r2, [r1, #FLYCNFG_OFFSET] + +/* FIXME Does this sequence really make sense */ +#ifdef REDBOOT_WAY + @ Step 2d + @ get the mdrefr settings + ldr r3, =CFG_MDREFR_VAL + + @ extract DRI field (we need a valid DRI field) + @ + ldr r2, =0xFFF + + @ valid DRI field in r3 + @ + and r3, r3, r2 + + @ get the reset state of MDREFR + @ + ldr r4, [r1, #MDREFR_OFFSET] + + @ clear the DRI field + @ + bic r4, r4, r2 + + @ insert the valid DRI field loaded above + @ + orr r4, r4, r3 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ *Note: preserve the mdrefr value in r4 * + + /*SET_LED 4 */ + +@**************************************************************************** +@ Step 3 +@ +@ NO SRAM + + mov pc, r10 + + +@**************************************************************************** +@ Step 4 +@ + + @ Assumes previous mdrefr value in r4, if not then read current mdrefr + + @ clear the free-running clock bits + @ (clear K0Free, K1Free, K2Free + @ + bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000) + + @ set K0RUN for CPLD clock + @ + orr r4, r4, #0x00002000 + + @ set K1RUN if bank 0 installed + @ + orr r4, r4, #0x00010000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + @ deassert SLFRSH + @ + bic r4, r4, #0x00400000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ assert E1PIN + @ + orr r4, r4, #0x00008000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + nop + nop +#else + @ Step 2d + @ get the mdrefr settings + ldr r4, =CFG_MDREFR_VAL + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ Step 4 + + @ set K0RUN for FLASH clock + @ + orr r4, r4, #0x00002000 + + @ set K1RUN for bank DRAM 0 + @ + orr r4, r4, #0x00010000 + + @ set K2RUN for bank PLD + @ + orr r4, r4, #0x00040000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + @ deassert SLFRSH + @ + bic r4, r4, #0x00400000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + + @ assert E1PIN + @ + orr r4, r4, #0x00008000 + + @ write back mdrefr + @ + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + nop + nop +#endif + + @ Step 4d + @ fetch platform value of mdcnfg + @ + ldr r2, =CFG_MDCNFG_VAL + + @ disable all sdram banks + @ + bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) + bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) + + @ program banks 0/1 for bus width + @ + bic r2, r2, #MDCNFG_DWID0 @0=32-bit + + @ write initial value of mdcnfg, w/o enabling sdram banks + @ + str r2, [r1, #MDCNFG_OFFSET] + + @ Step 4e + @ pause for 200 uSecs + @ + ldr r3, =OSCR @ reset the OS Timer Count to zero + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + /*SET_LED 5 */ + + /* Why is this here??? */ + mov r0, #0x78 @turn everything off + mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.) + + @ Step 4f + @ Access memory *not yet enabled* for CBR refresh cycles (8) + @ - CBR is generated for all banks + + ldr r2, =CFG_DRAM_BASE + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + + @ Step 4g + @get memory controller base address + @ + ldr r1, =MEMC_BASE + + @fetch current mdcnfg value + @ + ldr r3, [r1, #MDCNFG_OFFSET] + + @enable sdram bank 0 if installed (must do for any populated bank) + @ + orr r3, r3, #MDCNFG_DE0 + + @write back mdcnfg, enabling the sdram bank(s) + @ + str r3, [r1, #MDCNFG_OFFSET] + + @ Step 4h + @ write mdmrs + @ + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + @ Done Memory Init + + /*SET_LED 6 */ + + @******************************************************************** + @ Disable (mask) all interrupts at the interrupt controller + @ + + @ clear the interrupt level register (use IRQ, not FIQ) + @ + mov r1, #0 + ldr r2, =ICLR + str r1, [r2] + + @ Set interrupt mask register + @ + ldr r1, =CFG_ICMR_VAL + ldr r2, =ICMR + str r1, [r2] + + @ ******************************************************************** + @ Disable the peripheral clocks, and set the core clock + @ + + @ Turn Off ALL on-chip peripheral clocks for re-configuration + @ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + @ set core clocks + @ + ldr r2, =CFG_CCCR_VAL + ldr r1, =CCCR + str r2, [r1] + +#ifdef ENABLE32KHZ + @ enable the 32Khz oscillator for RTC and PowerManager + @ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + @ NOTE: spin here until OSCC.OOK get set, + @ meaning the PLL has settled. + @ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + @ Turn on needed clocks + @ + ldr r1, =CKEN + ldr r2, =CFG_CKEN_VAL + str r2, [r1] + + /*SET_LED 7 */ + +/* Is this needed???? */ +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + +#endif + + /*SET_LED 8 */ + + mov pc, r10 + +@ End lowlevel_init diff --git a/board/xm250/u-boot.lds b/board/xm250/u-boot.lds new file mode 100644 index 0000000..db83875 --- /dev/null +++ b/board/xm250/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c new file mode 100644 index 0000000..ef5e9da --- /dev/null +++ b/board/xm250/xm250.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------- */ + +/* local prototypes */ + +inline void sleep (int i); + +inline void +/**********************************************************/ +sleep (int i) +/**********************************************************/ +{ + while (i--) { + udelay (1000000); + } +} + +/* + * Miscelaneous platform dependent initialisations + */ + +int +/**********************************************************/ +board_post_init (void) +/**********************************************************/ +{ + return (0); +} + +int +/**********************************************************/ +board_init (void) +/**********************************************************/ +{ + DECLARE_GLOBAL_DATA_PTR; + /* arch number of MicroSys XM250 */ + gd->bd->bi_arch_number = MACH_TYPE_XM250; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int +/**********************************************************/ +dram_init (void) +/**********************************************************/ +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return (0); +} diff --git a/board/xpedite1k/Makefile b/board/xpedite1k/Makefile new file mode 100644 index 0000000..c5c0915 --- /dev/null +++ b/board/xpedite1k/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +OBJS +=flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/xpedite1k/config.mk b/board/xpedite1k/config.mk new file mode 100644 index 0000000..e42b273 --- /dev/null +++ b/board/xpedite1k/config.mk @@ -0,0 +1,42 @@ +# +# (C) Copyright 2002-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# XES XPedite1000 PPC440GX +# + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/xpedite1k/flash.c b/board/xpedite1k/flash.c new file mode 100644 index 0000000..ce5d4e1 --- /dev/null +++ b/board/xpedite1k/flash.c @@ -0,0 +1,607 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +/* + * Ported to XPedite1000, 1/2 mb boot flash only + * Travis B. Sawyer, + */ + +#include +#include +#include + + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define BOOT_SMALL_FLASH 32 /* 00100000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +#define BOOT_SMALL_FLASH_VAL 4 +#define FLASH_ONBD_N_VAL 2 +#define FLASH_SRAM_SEL_VAL 1 + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { + {0xfff80000}, /* 0:000: configuraton 3 */ + {0xfff90000}, /* 1:001: configuraton 4 */ + {0xfffa0000}, /* 2:010: configuraton 7 */ + {0xfffb0000}, /* 3:011: configuraton 8 */ + {0xfffc0000}, /* 4:100: configuraton 1 */ + {0xfffd0000}, /* 5:101: configuraton 2 */ + {0xfffe0000}, /* 6:110: configuraton 5 */ + {0xffff0000} /* 7:111: configuraton 6 */ +}; + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + + +#ifdef CONFIG_XPEDITE1K +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char +#endif + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i=0; iflash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n"); + break; + case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; + } + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); + + /* Write auto select command: read Manufacturer ID */ + udelay(10000); + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + udelay(1000); + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + udelay(1000); + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; + udelay(1000); + +#ifdef CONFIG_ADCIOP + value = addr2[2]; +#else + value = addr2[0]; +#endif + + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE)FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE)SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + +#ifdef CONFIG_ADCIOP + value = addr2[0]; /* device ID */ + debug ("\ndev_code=%x\n", value); +#else + value = addr2[1]; /* device ID */ +#endif + + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; /* => 512 kb */ + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040) || + (info->flash_id == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ +#ifdef CONFIG_ADCIOP + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + info->protect[i] = addr2[4] & 1; +#else + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; +#endif + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { +#if 0 /* test-only */ +#ifdef CONFIG_ADCIOP + addr2 = (volatile unsigned char *)info->start[0]; + addr2[ADDR0] = 0xAA; + addr2[ADDR1] = 0x55; + addr2[ADDR0] = 0xF0; /* reset bank */ +#else + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ +#endif +#else /* test-only */ + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ +#endif /* test-only */ + } + + return (info->size); +} + +int wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + printf("Erasing sector %p\n", addr2); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + for (i=0; i<50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#if 0 + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + wait_for_DQ7(info, l_sect); + +DONE: +#endif + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/xpedite1k/init.S b/board/xpedite1k/init.S new file mode 100644 index 0000000..6cb20e4 --- /dev/null +++ b/board/xpedite1k/init.S @@ -0,0 +1,96 @@ +/* +* Copyright (C) 2002 Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/xpedite1k/u-boot.lds b/board/xpedite1k/u-boot.lds new file mode 100644 index 0000000..0f08637 --- /dev/null +++ b/board/xpedite1k/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/xpedite1k/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xpedite1k/u-boot.lds.debug b/board/xpedite1k/u-boot.lds.debug new file mode 100644 index 0000000..5066326 --- /dev/null +++ b/board/xpedite1k/u-boot.lds.debug @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/xpedite1k/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c new file mode 100644 index 0000000..bb36c96 --- /dev/null +++ b/board/xpedite1k/xpedite1k.c @@ -0,0 +1,351 @@ +/* + * Copyright (C) 2003 Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include + +#define BOOT_SMALL_FLASH 32 /* 00100000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +long int fixed_sdram (void); + +int board_early_init_f(void) +{ + unsigned long sdrreg; + /* TBS: Setup the GPIO access for the user LEDs */ + mfsdr(sdr_pfc0, sdrreg); + mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00); + out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); + LED0_OFF(); + LED1_OFF(); + LED2_OFF(); + LED3_OFF(); + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + + /* set the bus controller */ + mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */ + mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ + mtebc (pb1ap, 0x04055200); /* FLASH/SRAM */ + mtebc (pb1cr, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */ + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */ + mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */ + mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */ + mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); /* */ + mtdcr (uicb0tr, 0x00000000); /* */ + mtdcr (uicb0vr, 0x00000001); /* */ + + LED0_ON(); + + + return 0; +} + +int checkboard (void) +{ + printf ("Board: XES XPedite1000 440GX\n"); + + return (0); +} + + +long int initdram (int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (0); +#else + dram_size = fixed_sdram (); +#endif + return dram_size; +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + * + * Assumes: 128 MB, non-ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +long int fixed_sdram (void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + /* RA=10 RD=3 */ + mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + udelay (400); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + for (;;) { + mfsdram (mem_mcsts, reg); + if (reg & 0x80000000) + break; + } + + return (128 * 1024 * 1024); /* 128 MB */ +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + /* See if we're supposed to setup the pci */ + mfsdr(sdr_sdstp1, strap); + if ((strap & 0x00010000) == 0) { + return (0); + } + +#if defined(CFG_PCI_FORCE_PCI_CONV) + /* Setup System Device Register PCIX0_XCR */ + mfsdr(sdr_xcr, strap); + strap &= 0x0f000000; + mtsdr(sdr_xcr, strap); +#endif + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return ((in32(CFG_GPIO_BASE + 0x1C) & 0x00000800) == 0); +} +#endif /* defined(CONFIG_PCI) */ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + + return (ctrlc()); +} + +void post_word_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_POST_WORD_ADDR); + + *save_addr = a; +} + +ulong post_word_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_POST_WORD_ADDR); + + return *save_addr; +} +#endif + +/*----------------------------------------------------------------------------- + * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM + *----------------------------------------------------------------------------- + */ +static int enetaddr_num = 0; +void board_get_enetaddr (uchar * enet) +{ + int i; + unsigned char buff[0x100], *cp; + + /* Initialize I2C */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read 256 bytes in EEPROM */ + i2c_read (0x50, 0, 1, buff, 0x100); + + if (enetaddr_num == 0) { + cp = &buff[0xF4]; + enetaddr_num = 1; + } + else + cp = &buff[0xFA]; + + for (i = 0; i < 6; i++,cp++) + enet[i] = *cp; + + printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n", + enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]); + +} diff --git a/board/xsengine/Makefile b/board/xsengine/Makefile new file mode 100644 index 0000000..ed1464a --- /dev/null +++ b/board/xsengine/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := xsengine.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/xsengine/config.mk b/board/xsengine/config.mk new file mode 100644 index 0000000..148c519 --- /dev/null +++ b/board/xsengine/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xA3F80000 diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c new file mode 100644 index 0000000..2b9afc7 --- /dev/null +++ b/board/xsengine/flash.c @@ -0,0 +1,470 @@ +/* + * (C) Copyright 2002 + * Robert Schwebel, Pengutronix, + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define SWAP(x) __swab32(x) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Functions */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors */ + flash_protect ( FLAG_PROTECT_SET,CFG_FLASH_BASE,CFG_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] ); + flash_protect ( FLAG_PROTECT_SET,CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) return; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n"); + break; + case FLASH_S29GL064M: printf ("S29GL064M (64Mbit, top boot sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value) { + case AMD_MANUFACT: + debug ("Manufacturer: AMD\n"); + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + debug ("Manufacturer: FUJITSU\n"); + info->flash_id = FLASH_MAN_FUJ; + break; + default: + debug ("Manufacturer: *** unknown ***\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value) { + + case AMD_ID_MIRROR: + debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", + addr[14], addr[15]); + switch(addr[14]) { + case AMD_ID_LV640U_2: + if (addr[15] != AMD_ID_LV640U_3) { + debug ("Chip: AMLV640U -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + debug ("Chip: AMLV640U\n"); + info->flash_id += FLASH_AMLV640U; + info->sector_count = 128; + info->size = 0x01000000; + } + break; /* => 16 MB */ + case AMD_ID_GL064MT_2: + if (addr[15] != AMD_ID_GL064MT_3) { + debug ("Chip: S29GL064M-R3 -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + debug ("Chip: S29GL064M-R3\n"); + info->flash_id += FLASH_S29GL064M; + info->sector_count = 128; + info->size = 0x01000000; + } + break; /* => 16 MB */ + default: + debug ("Chip: *** unknown ***\n"); + info->flash_id = FLASH_UNKNOWN; + break; + } + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + switch (value) { + case AMD_ID_MIRROR: + switch (info->flash_id & FLASH_TYPEMASK) { + /* only known types here - no default */ + case FLASH_AMLV128U: + case FLASH_AMLV640U: + case FLASH_AMLV320U: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x20000; + } + break; + case FLASH_AMLV320B: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The first 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < 8) + ? 2 * ( 8 << 10) + : 2 * (64 << 10); + } + break; + } + break; + + default: + return (0); + break; + } + +#if 0 + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } +#endif + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 100000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, SWAP(data))) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, SWAP(data))) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, SWAP(data))); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S new file mode 100644 index 0000000..309faab --- /dev/null +++ b/board/xsengine/lowlevel_init.S @@ -0,0 +1,221 @@ +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + +/* ---- GPIO INITIALISATION ---- */ +/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */ + + /* General purpose set registers */ + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + /* General purpose clear registers */ + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + /* General rising edge registers */ + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + /* General falling edge registers */ + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + /* General edge detect registers */ + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + /* General alternate function registers */ + ldr r0, =GAFR0_L /* [0:15] */ + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + ldr r0, =GAFR0_U /* [31:16] */ + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + ldr r0, =GAFR1_L /* [47:32] */ + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + ldr r0, =GAFR1_U /* [63:48] */ + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + ldr r0, =GAFR2_L /* [79:64] */ + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + ldr r0, =GAFR2_U /* [80] */ + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + /* General purpose direction registers */ + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + /* Power manager sleep status */ + ldr r0, =PSSR + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + +/* ---- MEMORY INITIALISATION ---- */ +/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */ +/* pause for 200 uSecs- allow internal clocks to settle */ + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: +/* get memory controller base address */ + ldr r1, =MEMC_BASE + +/* ---- FLASH INITIALISATION ---- */ +/* Write MSC0 and read back to ensure data change is accepted by cpu */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] + +/* ---- SDRAM INITIALISATION ---- */ +/* get the MDREFR settings */ + ldr r2, =CFG_MDREFR_VAL + str r2, [r1, #MDREFR_OFFSET] + +/* fetch platform value of MDCNFG */ + ldr r2, =CFG_MDCNFG_VAL + +/* disable all sdram banks */ + bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) + bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) + +/* write initial value of MDCNFG, w/o enabling sdram banks */ + str r2, [r1, #MDCNFG_OFFSET] + +/* pause for 200 uSecs */ + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* about 200 usec */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +/* Access memory *not yet enabled* for CBR refresh cycles (8) */ +/* CBR is generated for all banks */ + + ldr r2, =CFG_DRAM_BASE + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + str r2, [r2] + +/* get memory controller base address */ + ldr r2, =MEMC_BASE + +/* Enable SDRAM bank 0 in MDCNFG register */ + ldr r2, [r1, #MDCNFG_OFFSET] + orr r2, r2, #MDCNFG_DE0 + str r2, [r1, #MDCNFG_OFFSET] + +/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */ + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + +/* ---- INTERRUPT INITIALISATION ---- */ +/* Disable (mask) all interrupts at the interrupt controller */ +/* clear the interrupt level register (use IRQ, not FIQ) */ + mov r1, #0 + ldr r2, =ICLR + str r1, [r2] + +/* Set interrupt mask register */ + ldr r1, =CFG_ICMR_VAL + ldr r2, =ICMR + str r1, [r2] + +/* ---- CLOCK INITIALISATION ---- */ +/* Disable the peripheral clocks, and set the core clock */ + +/* Turn Off ALL on-chip peripheral clocks for re-configuration */ + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + +/* set core clocks */ + ldr r2, =CFG_CCCR_VAL + ldr r1, =CCCR + str r2, [r1] + +#ifdef ENABLE32KHZ +/* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + +/* NOTE: spin here until OSCC.OOK get set, meaning the PLL has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + +/* Turn on needed clocks */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN_VAL + str r2, [r1] + + mov pc, r10 diff --git a/board/xsengine/u-boot.lds b/board/xsengine/u-boot.lds new file mode 100644 index 0000000..db83875 --- /dev/null +++ b/board/xsengine/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c new file mode 100644 index 0000000..a9919db --- /dev/null +++ b/board/xsengine/xsengine.c @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number */ + gd->bd->bi_arch_number = MACH_TYPE_XSENGINE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_post_init (void) +{ + setenv ("stdout", "serial"); + setenv ("stderr", "serial"); + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile new file mode 100644 index 0000000..8b10993 --- /dev/null +++ b/board/zpc1900/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/zpc1900/config.mk b/board/zpc1900/config.mk new file mode 100644 index 0000000..1072dc7 --- /dev/null +++ b/board/zpc1900/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Yuli Barcohen, Arabella Software Ltd. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# ZPC.1900 board +# + +TEXT_BASE = 0xFFE00000 diff --git a/board/zpc1900/u-boot.lds b/board/zpc1900/u-boot.lds new file mode 100644 index 0000000..18c4b46 --- /dev/null +++ b/board/zpc1900/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c new file mode 100644 index 0000000..6d16a0d --- /dev/null +++ b/board/zpc1900/zpc1900.c @@ -0,0 +1,308 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 Arabella Software Ltd. + * Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +#ifdef CFG_NVRAM_ACCESS_ROUTINE +void *nvram_read(void *dest, long src, size_t count) +{ + return memcpy(dest, (const void *)src, count); +} + +void nvram_write(long dest, const void *src, size_t count) +{ + vu_char *p1 = (vu_char *)(CFG_EEPROM + 0x1555); + vu_char *p2 = (vu_char *)(CFG_EEPROM + 0x0AAA); + vu_char *d = (vu_char *)dest; + const uchar *s = (const uchar *)src; + + /* Unprotect the EEPROM */ + *p1 = 0xAA; + *p2 = 0x55; + *p1 = 0x80; + *p1 = 0xAA; + *p2 = 0x55; + *p1 = 0x20; + udelay(10000); + + /* Write the data to the EEPROM */ + while (count--) { + *d++ = *s++; + while (*(d - 1) != *(s - 1)) + /* wait */; + } + + /* Protect the EEPROM */ + *p1 = 0xAA; + *p2 = 0x55; + *p1 = 0xA0; + udelay(10000); +} +#endif /* CFG_NVRAM_ACCESS_ROUTINE */ + +long int initdram(int board_type) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + vu_char *ramaddr; + uchar c = 0xFF; + long int msize = CFG_SDRAM_SIZE; + uint psdmr = CFG_PSDMR; + int i; + + if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */ + immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; + immap->im_siu_conf.sc_siumcr = + (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) + | SIUMCR_LBPC01; + } + +#ifndef CFG_RAMBOOT + immap->im_siu_conf.sc_ppc_acr = 0x03; + immap->im_siu_conf.sc_ppc_alrh = 0x30126745; + immap->im_siu_conf.sc_tescr1 = 0x00004000; + + memctl->memc_mptpr = CFG_MPTPR; + +#ifdef CFG_LSDRAM_BASE + /* + Initialise local bus SDRAM only if the pins + are configured as local bus pins and not as PCI. + */ + if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { + memctl->memc_lsrt = CFG_LSRT; + memctl->memc_or4 = 0xFFC01480; + memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; + memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; + ramaddr = (vu_char *)CFG_LSDRAM_BASE; + *ramaddr = c; + memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_MRW; + *ramaddr = c; + memctl->memc_lsdmr = CFG_LSDMR | PSDMR_RFEN; + } +#endif /* CFG_LSDRAM_BASE */ + + /* Initialise 60x bus SDRAM */ + memctl->memc_psrt = CFG_PSRT; + memctl->memc_or2 = 0xFC0028C0; + memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; + /* + * The mode data for Mode Register Write command must appear on + * the address lines during a mode-set cycle. It is driven by + * the memory controller, in single PowerQUICC II mode, + * according to PSDMR[CL] and PSDMR[BL] fields. In + * 60x-compatible mode, software must drive the correct value on + * the address lines. BL=0 because for 64-bit port size burst + * length must be 4. + */ + ramaddr = (vu_char *)(CFG_SDRAM_BASE | + ((psdmr & PSDMR_CL_MSK) << 7) | 0x10); + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + for (i = 0; i < 8; i++) + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ + *ramaddr = c; +#endif /* CFG_RAMBOOT */ + + /* Return total 60x bus SDRAM size */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40); + return 0; +} diff --git a/common/ACEX1K.c b/common/ACEX1K.c new file mode 100644 index 0000000..2a421e2 --- /dev/null +++ b/common/ACEX1K.c @@ -0,0 +1,366 @@ +/* + * (C) Copyright 2003 + * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de + * + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include /* core U-Boot definitions */ +#include /* ACEX device family */ + +#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) + +/* Define FPGA_DEBUG to get debug printf's */ +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* Note: The assumption is that we cannot possibly run fast enough to + * overrun the device (the Slave Parallel mode can free run at 50MHz). + * If there is a need to operate slower, define CONFIG_FPGA_DELAY in + * the board config file to slow things down. + */ +#ifndef CONFIG_FPGA_DELAY +#define CONFIG_FPGA_DELAY() +#endif + +#ifndef CFG_FPGA_WAIT +#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */ +#endif + +static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize ); +static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); +/* static int ACEX1K_ps_info( Altera_desc *desc ); */ +static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset ); + +/* ------------------------------------------------------------------------- */ +/* ACEX1K Generic Implementation */ +int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); + ret_val = ACEX1K_ps_load (desc, buf, bsize); + break; + + /* Add new interface types here */ + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); + ret_val = ACEX1K_ps_dump (desc, buf, bsize); + break; + + /* Add new interface types here */ + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int ACEX1K_info( Altera_desc *desc ) +{ + return FPGA_SUCCESS; +} + + +int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (desc->family != Altera_ACEX1K) { + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + return FPGA_FAIL; + } else + switch (desc->iface) { + case passive_serial: + ret_val = ACEX1K_ps_reloc (desc, reloc_offset); + break; + + /* Add new interface types here */ + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + + +/* ------------------------------------------------------------------------- */ +/* ACEX1K Passive Serial Generic Implementation */ + +static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns; + int i; + + PRINTF ("%s: start with interface functions @ 0x%p\n", + __FUNCTION__, fn); + + if (fn) { + size_t bytecount = 0; + unsigned char *data = (unsigned char *) buf; + int cookie = desc->cookie; /* make a local copy */ + unsigned long ts; /* timestamp */ + + PRINTF ("%s: Function Table:\n" + "ptr:\t0x%p\n" + "struct: 0x%p\n" + "config:\t0x%p\n" + "status:\t0x%p\n" + "clk:\t0x%p\n" + "data:\t0x%p\n" + "done:\t0x%p\n\n", + __FUNCTION__, &fn, fn, fn->config, fn->status, + fn->clk, fn->data, fn->done); +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("Loading FPGA Device %d...", cookie); +#endif + + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) { + (*fn->pre) (cookie); + } + + /* Establish the initial state */ + (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ + + udelay(2); /* T_cfg > 2us */ + + /* nSTATUS should be asserted now */ + (*fn->done) (cookie); + if ( !(*fn->status) (cookie) ) { + puts ("** nSTATUS is not asserted.\n"); + (*fn->abort) (cookie); + return FPGA_FAIL; + } + + (*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */ + udelay(2); /* T_cf2st1 < 4us */ + + /* Wait for nSTATUS to be released (i.e. deasserted) */ + ts = get_timer (0); /* get current time */ + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for STATUS to go high.\n"); + (*fn->abort) (cookie); + return FPGA_FAIL; + } + (*fn->done) (cookie); + } while ((*fn->status) (cookie)); + + /* Get ready for the burn */ + CONFIG_FPGA_DELAY (); + + /* Load the data */ + while (bytecount < bsize) { + unsigned char val=0; +#ifdef CFG_FPGA_CHECK_CTRLC + if (ctrlc ()) { + (*fn->abort) (cookie); + return FPGA_FAIL; + } +#endif + /* Altera detects an error if INIT goes low (active) + while DONE is low (inactive) */ +#if 0 /* not yet implemented */ + if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { + puts ("** CRC error during FPGA load.\n"); + (*fn->abort) (cookie); + return (FPGA_FAIL); + } +#endif + val = data [bytecount ++ ]; + i = 8; + do { + /* Deassert the clock */ + (*fn->clk) (FALSE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Write data */ + (*fn->data) ( (val & 0x01), TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Assert the clock */ + (*fn->clk) (TRUE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + val >>= 1; + i --; + } while (i > 0); + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ +#endif + } + + CONFIG_FPGA_DELAY (); + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc (' '); /* terminate the dotted line */ +#endif + + /* + * Checking FPGA's CONF_DONE signal - correctly booted ? + */ + + if ( ! (*fn->done) (cookie) ) { + puts ("** Booting failed! CONF_DONE is still deasserted.\n"); + (*fn->abort) (cookie); + return (FPGA_FAIL); + } + + /* + * "DCLK must be clocked an additional 10 times fpr ACEX 1K..." + */ + + for (i = 0; i < 12; i++) { + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + } + + ret_val = FPGA_SUCCESS; + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (ret_val == FPGA_SUCCESS) { + puts ("Done.\n"); + } + else { + puts ("Fail.\n"); + } +#endif + (*fn->post) (cookie); + + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + +static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +{ + /* Readback is only available through the Slave Parallel and */ + /* boundary-scan interfaces. */ + printf ("%s: Passive Serial Dumping is unavailable\n", + __FUNCTION__); + return FPGA_FAIL; +} + +static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn = + (Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns); + + if (fn) { + ulong addr; + + /* Get the relocated table address */ + addr = (ulong) fn + reloc_offset; + fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr; + + if (!fn_r->relocated) { + + if (memcmp (fn_r, fn, + sizeof (Altera_ACEX1K_Passive_Serial_fns)) + == 0) { + /* good copy of the table, fix the descriptor pointer */ + desc->iface_fns = fn_r; + } else { + PRINTF ("%s: Invalid function table at 0x%p\n", + __FUNCTION__, fn_r); + return FPGA_FAIL; + } + + PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, + desc); + + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Altera_pre_fn) addr; + + addr = (ulong) (fn->config) + reloc_offset; + fn_r->config = (Altera_config_fn) addr; + + addr = (ulong) (fn->status) + reloc_offset; + fn_r->status = (Altera_status_fn) addr; + + addr = (ulong) (fn->done) + reloc_offset; + fn_r->done = (Altera_done_fn) addr; + + addr = (ulong) (fn->clk) + reloc_offset; + fn_r->clk = (Altera_clk_fn) addr; + + addr = (ulong) (fn->data) + reloc_offset; + fn_r->data = (Altera_data_fn) addr; + + addr = (ulong) (fn->abort) + reloc_offset; + fn_r->abort = (Altera_abort_fn) addr; + + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Altera_post_fn) addr; + + fn_r->relocated = TRUE; + + } else { + /* this table has already been moved */ + /* XXX - should check to see if the descriptor is correct */ + desc->iface_fns = fn_r; + } + + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; + +} + +#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */ diff --git a/common/Makefile b/common/Makefile new file mode 100644 index 0000000..7dbf84a --- /dev/null +++ b/common/Makefile @@ -0,0 +1,80 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libcommon.a + +AOBJS = + +COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ + cmd_ace.o cmd_autoscript.o \ + cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \ + cmd_cache.o cmd_console.o \ + cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \ + cmd_eeprom.o cmd_elf.o cmd_ext2.o \ + cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \ + cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \ + cmd_load.o cmd_log.o \ + cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ + cmd_nand.o cmd_net.o cmd_nvedit.o \ + cmd_pci.o cmd_pcmcia.o cmd_portio.o \ + cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \ + cmd_usb.o cmd_vfd.o \ + command.o console.o devices.o dlmalloc.o docecc.o \ + environment.o env_common.o \ + env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ + env_nvram.o env_nowhere.o \ + exports.o \ + flash.o fpga.o ft_build.o \ + hush.o kgdb.o lcd.o lists.o lynxkdi.o \ + memsize.o miiphybb.o miiphyutil.o \ + s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ + usb.o usb_kbd.o usb_storage.o \ + virtex2.o xilinx.o + +OBJS = $(AOBJS) $(COBJS) + +CPPFLAGS += -I.. + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +environment.o: environment.c ../tools/envcrc + $(CC) $(AFLAGS) -Wa,--no-warn \ + -DENV_CRC=$(shell ../tools/envcrc) \ + -c -o $@ environment.c + +../tools/envcrc: + $(MAKE) -C ../tools + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/common/altera.c b/common/altera.c new file mode 100644 index 0000000..ebd5038 --- /dev/null +++ b/common/altera.c @@ -0,0 +1,233 @@ +/* + * (C) Copyright 2003 + * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de + * + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Altera FPGA support + */ +#include +#include + +/* Define FPGA_DEBUG to get debug printf's */ +/* #define FPGA_DEBUG */ + +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#if (CONFIG_FPGA & CFG_FPGA_ALTERA) + +/* Local Static Functions */ +static int altera_validate (Altera_desc * desc, char *fn); + +/* ------------------------------------------------------------------------- */ +int altera_load( Altera_desc *desc, void *buf, size_t bsize ) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (!altera_validate (desc, __FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } else { + switch (desc->family) { + case Altera_ACEX1K: +#if (CONFIG_FPGA & CFG_ACEX1K) + PRINTF ("%s: Launching the ACEX1K Loader...\n", + __FUNCTION__); + ret_val = ACEX1K_load (desc, buf, bsize); +#else + printf ("%s: No support for ACEX1K devices.\n", + __FUNCTION__); +#endif + break; + + default: + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + } + } + + return ret_val; +} + +int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (!altera_validate (desc, __FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } else { + switch (desc->family) { + case Altera_ACEX1K: +#if (CONFIG_FPGA & CFG_ACEX) + PRINTF ("%s: Launching the ACEX1K Reader...\n", + __FUNCTION__); + ret_val = ACEX1K_dump (desc, buf, bsize); +#else + printf ("%s: No support for ACEX1K devices.\n", + __FUNCTION__); +#endif + break; + + default: + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + } + } + + return ret_val; +} + +int altera_info( Altera_desc *desc ) +{ + int ret_val = FPGA_FAIL; + + if (altera_validate (desc, __FUNCTION__)) { + printf ("Family: \t"); + switch (desc->family) { + case Altera_ACEX1K: + printf ("ACEX1K\n"); + break; + /* Add new family types here */ + default: + printf ("Unknown family type, %d\n", desc->family); + } + + printf ("Interface type:\t"); + switch (desc->iface) { + case passive_serial: + printf ("Passive Serial (PS)\n"); + break; + case passive_parallel_synchronous: + printf ("Passive Parallel Synchronous (PPS)\n"); + break; + case passive_parallel_asynchronous: + printf ("Passive Parallel Asynchronous (PPA)\n"); + break; + case passive_serial_asynchronous: + printf ("Passive Serial Asynchronous (PSA)\n"); + break; + case altera_jtag_mode: /* Not used */ + printf ("JTAG Mode\n"); + break; + /* Add new interface types here */ + default: + printf ("Unsupported interface type, %d\n", desc->iface); + } + + printf ("Device Size: \t%d bytes\n" + "Cookie: \t0x%x (%d)\n", + desc->size, desc->cookie, desc->cookie); + + if (desc->iface_fns) { + printf ("Device Function Table @ 0x%p\n", desc->iface_fns); + switch (desc->family) { + case Altera_ACEX1K: +#if (CONFIG_FPGA & CFG_ACEX1K) + ACEX1K_info (desc); +#else + /* just in case */ + printf ("%s: No support for ACEX1K devices.\n", + __FUNCTION__); +#endif + break; + /* Add new family types here */ + default: + /* we don't need a message here - we give one up above */ + break; + } + } else { + printf ("No Device Function Table.\n"); + } + + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } + + return ret_val; +} + +int altera_reloc( Altera_desc *desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (!altera_validate (desc, __FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } else { + switch (desc->family) { + case Altera_ACEX1K: +#if (CONFIG_FPGA & CFG_ACEX1K) + ret_val = ACEX1K_reloc (desc, reloc_offset); +#else + printf ("%s: No support for ACEX devices.\n", + __FUNCTION__); +#endif + break; + /* Add new family types here */ + default: + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + } + } + + return ret_val; +} + +/* ------------------------------------------------------------------------- */ + +static int altera_validate (Altera_desc * desc, char *fn) +{ + int ret_val = FALSE; + + if (desc) { + if ((desc->family > min_altera_type) && + (desc->family < max_altera_type)) { + if ((desc->iface > min_altera_iface_type) && + (desc->iface < max_altera_iface_type)) { + if (desc->size) { + ret_val = TRUE; + } else { + printf ("%s: NULL part size\n", fn); + } + } else { + printf ("%s: Invalid Interface type, %d\n", + fn, desc->iface); + } + } else { + printf ("%s: Invalid family type, %d\n", fn, desc->family); + } + } else { + printf ("%s: NULL descriptor!\n", fn); + } + + return ret_val; +} + +/* ------------------------------------------------------------------------- */ + +#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */ diff --git a/common/bedbug.c b/common/bedbug.c new file mode 100644 index 0000000..6966de7 --- /dev/null +++ b/common/bedbug.c @@ -0,0 +1,1256 @@ +/* $Id$ */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + +#include +#include +#include +#include +#include + +#define Elf32_Word unsigned long + +/* USE_SOURCE_CODE enables some symbolic debugging functions of this + code. This is only useful if the program will have access to the + source code for the binary being examined. +*/ + +/* #define USE_SOURCE_CODE 1 */ + +#ifdef USE_SOURCE_CODE +extern int line_info_from_addr __P ((Elf32_Word, char *, char *, int *)); +extern struct symreflist *symByAddr; +extern char *symbol_name_from_addr __P ((Elf32_Word, int, int *)); +#endif /* USE_SOURCE_CODE */ + +int print_operands __P ((struct ppc_ctx *)); +int get_operand_value __P ((struct opcode *, unsigned long, + enum OP_FIELD, unsigned long *)); +struct opcode *find_opcode __P ((unsigned long)); +struct opcode *find_opcode_by_name __P ((char *)); +char *spr_name __P ((int)); +int spr_value __P ((char *)); +char *tbr_name __P ((int)); +int tbr_value __P ((char *)); +int parse_operand __P ((unsigned long, struct opcode *, + struct operand *, char *, int *)); +int get_word __P ((char **, char *)); +long read_number __P ((char *)); +int downstring __P ((char *)); + + +/*====================================================================== + * Entry point for the PPC disassembler. + * + * Arguments: + * memaddr The address to start disassembling from. + * + * virtual If this value is non-zero, then this will be + * used as the base address for the output and + * symbol lookups. If this value is zero then + * memaddr is used as the absolute address. + * + * num_instr The number of instructions to disassemble. Since + * each instruction is 32 bits long, this can be + * computed if you know the total size of the region. + * + * pfunc The address of a function that is called to print + * each line of output. The function should take a + * single character pointer as its parameters a la puts. + * + * flags Sets options for the output. This is a + * bitwise-inclusive-OR of the following + * values. Note that only one of the radix + * options may be set. + * + * F_RADOCTAL - output radix is unsigned base 8. + * F_RADUDECIMAL - output radix is unsigned base 10. + * F_RADSDECIMAL - output radix is signed base 10. + * F_RADHEX - output radix is unsigned base 16. + * F_SIMPLE - use simplified mnemonics. + * F_SYMBOL - lookup symbols for addresses. + * F_INSTR - output raw instruction. + * F_LINENO - show line # info if available. + * + * Returns TRUE if the area was successfully disassembled or FALSE if + * a problem was encountered with accessing the memory. + */ + +int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr, + int (*pfunc) (const char *), unsigned long flags) +{ + int i; + struct ppc_ctx ctx; + +#ifdef USE_SOURCE_CODE + int line_no = 0; + int last_line_no = 0; + char funcname[128] = { 0 }; + char filename[256] = { 0 }; + char last_funcname[128] = { 0 }; + int symoffset; + char *symname; + char *cursym = (char *) 0; +#endif /* USE_SOURCE_CODE */ + /*------------------------------------------------------------*/ + + ctx.flags = flags; + ctx.virtual = virtual; + + /* Figure out the output radix before we go any further */ + + if (ctx.flags & F_RADOCTAL) { + /* Unsigned octal output */ + strcpy (ctx.radix_fmt, "O%o"); + } else if (ctx.flags & F_RADUDECIMAL) { + /* Unsigned decimal output */ + strcpy (ctx.radix_fmt, "%u"); + } else if (ctx.flags & F_RADSDECIMAL) { + /* Signed decimal output */ + strcpy (ctx.radix_fmt, "%d"); + } else { + /* Unsigned hex output */ + strcpy (ctx.radix_fmt, "0x%x"); + } + + if (ctx.virtual == 0) { + ctx.virtual = memaddr; + } +#ifdef USE_SOURCE_CODE + if (ctx.flags & F_SYMBOL) { + if (symByAddr == 0) /* no symbols loaded */ + ctx.flags &= ~F_SYMBOL; + else { + cursym = (char *) 0; + symoffset = 0; + } + } +#endif /* USE_SOURCE_CODE */ + + /* format each line as "XXXXXXXX: IIIIIIII disassembly" where, + XXXXXXXX is the memory address in hex, + is the symbolic location if F_SYMBOL is set. + IIIIIIII is the raw machine code in hex if F_INSTR is set, + and disassembly is the disassembled machine code with numbers + formatted according to the 'radix' parameter */ + + for (i = 0; i < num_instr; ++i, memaddr += 4, ctx.virtual += 4) { +#ifdef USE_SOURCE_CODE + if (ctx.flags & F_LINENO) { + if ((line_info_from_addr ((Elf32_Word) ctx.virtual, filename, + funcname, &line_no) == TRUE) && + ((line_no != last_line_no) || + (strcmp (last_funcname, funcname) != 0))) { + print_source_line (filename, funcname, line_no, pfunc); + } + last_line_no = line_no; + strcpy (last_funcname, funcname); + } +#endif /* USE_SOURCE_CODE */ + + sprintf (ctx.data, "%08lx: ", (unsigned long) ctx.virtual); + ctx.datalen = 10; + +#ifdef USE_SOURCE_CODE + if (ctx.flags & F_SYMBOL) { + if ((symname = + symbol_name_from_addr ((Elf32_Word) ctx.virtual, + TRUE, 0)) != 0) { + cursym = symname; + symoffset = 0; + } else { + if ((cursym == 0) && + ((symname = + symbol_name_from_addr ((Elf32_Word) ctx.virtual, + FALSE, &symoffset)) != 0)) { + cursym = symname; + } else { + symoffset += 4; + } + } + + if (cursym != 0) { + sprintf (&ctx.data[ctx.datalen], "<%s+", cursym); + ctx.datalen = strlen (ctx.data); + sprintf (&ctx.data[ctx.datalen], ctx.radix_fmt, symoffset); + strcat (ctx.data, ">"); + ctx.datalen = strlen (ctx.data); + } + } +#endif /* USE_SOURCE_CODE */ + + ctx.instr = INSTRUCTION (memaddr); + + if (ctx.flags & F_INSTR) { + /* Find the opcode structure for this opcode. If one is not found + then it must be an illegal instruction */ + sprintf (&ctx.data[ctx.datalen], + " %02lx %02lx %02lx %02lx ", + ((ctx.instr >> 24) & 0xff), + ((ctx.instr >> 16) & 0xff), ((ctx.instr >> 8) & 0xff), + (ctx.instr & 0xff)); + ctx.datalen += 18; + } else { + strcat (ctx.data, " "); + ctx.datalen += 3; + } + + if ((ctx.op = find_opcode (ctx.instr)) == 0) { + /* Illegal Opcode */ + sprintf (&ctx.data[ctx.datalen], " .long 0x%08lx", + ctx.instr); + ctx.datalen += 24; + (*pfunc) (ctx.data); + continue; + } + + if (((ctx.flags & F_SIMPLE) == 0) || + (ctx.op->hfunc == 0) || ((*ctx.op->hfunc) (&ctx) == FALSE)) { + sprintf (&ctx.data[ctx.datalen], "%-7s ", ctx.op->name); + ctx.datalen += 8; + print_operands (&ctx); + } + + (*pfunc) (ctx.data); + } + + return TRUE; +} /* disppc */ + + + +/*====================================================================== + * Called by the disassembler to print the operands for an instruction. + * + * Arguments: + * ctx A pointer to the disassembler context record. + * + * always returns 0. + */ + +int print_operands (struct ppc_ctx *ctx) +{ + int open_parens = 0; + int field; + unsigned long operand; + struct operand *opr; + +#ifdef USE_SOURCE_CODE + char *symname; + int offset; +#endif /* USE_SOURCE_CODE */ + /*------------------------------------------------------------*/ + + /* Walk through the operands and list each in order */ + for (field = 0; ctx->op->fields[field] != 0; ++field) { + if (ctx->op->fields[field] > n_operands) { + continue; /* bad operand ?! */ + } + + opr = &operands[ctx->op->fields[field] - 1]; + + if (opr->hint & OH_SILENT) { + continue; + } + + if ((field > 0) && !open_parens) { + strcat (ctx->data, ","); + ctx->datalen++; + } + + operand = (ctx->instr >> opr->shift) & ((1 << opr->bits) - 1); + + if (opr->hint & OH_ADDR) { + if ((operand & (1 << (opr->bits - 1))) != 0) { + operand = operand - (1 << opr->bits); + } + + if (ctx->op->hint & H_RELATIVE) + operand = (operand << 2) + (unsigned long) ctx->virtual; + else + operand = (operand << 2); + + + sprintf (&ctx->data[ctx->datalen], "0x%lx", operand); + ctx->datalen = strlen (ctx->data); + +#ifdef USE_SOURCE_CODE + if ((ctx->flags & F_SYMBOL) && + ((symname = + symbol_name_from_addr (operand, 0, &offset)) != 0)) { + sprintf (&ctx->data[ctx->datalen], " <%s", symname); + if (offset != 0) { + strcat (ctx->data, "+"); + ctx->datalen = strlen (ctx->data); + sprintf (&ctx->data[ctx->datalen], ctx->radix_fmt, + offset); + } + strcat (ctx->data, ">"); + } +#endif /* USE_SOURCE_CODE */ + } + + else if (opr->hint & OH_REG) { + if ((operand == 0) && + (opr->field == O_rA) && (ctx->op->hint & H_RA0_IS_0)) { + strcat (ctx->data, "0"); + } else { + sprintf (&ctx->data[ctx->datalen], "r%d", (short) operand); + } + + if (open_parens) { + strcat (ctx->data, ")"); + open_parens--; + } + } + + else if (opr->hint & OH_SPR) { + strcat (ctx->data, spr_name (operand)); + } + + else if (opr->hint & OH_TBR) { + strcat (ctx->data, tbr_name (operand)); + } + + else if (opr->hint & OH_LITERAL) { + switch (opr->field) { + case O_cr2: + strcat (ctx->data, "cr2"); + ctx->datalen += 3; + break; + + default: + break; + } + } + + else { + sprintf (&ctx->data[ctx->datalen], ctx->radix_fmt, + (unsigned short) operand); + + if (open_parens) { + strcat (ctx->data, ")"); + open_parens--; + } + + else if (opr->hint & OH_OFFSET) { + strcat (ctx->data, "("); + open_parens++; + } + } + + ctx->datalen = strlen (ctx->data); + } + + return 0; +} /* print_operands */ + + + +/*====================================================================== + * Called to get the value of an arbitrary operand with in an instruction. + * + * Arguments: + * op The pointer to the opcode structure to which + * the operands belong. + * + * instr The instruction (32 bits) containing the opcode + * and the operands to print. By the time that + * this routine is called the operand has already + * been added to the output. + * + * field The field (operand) to get the value of. + * + * value The address of an unsigned long to be filled in + * with the value of the operand if it is found. This + * will only be filled in if the function returns + * TRUE. This may be passed as 0 if the value is + * not required. + * + * Returns TRUE if the operand was found or FALSE if it was not. + */ + +int get_operand_value (struct opcode *op, unsigned long instr, + enum OP_FIELD field, unsigned long *value) +{ + int i; + struct operand *opr; + + /*------------------------------------------------------------*/ + + if (field > n_operands) { + return FALSE; /* bad operand ?! */ + } + + /* Walk through the operands and list each in order */ + for (i = 0; op->fields[i] != 0; ++i) { + if (op->fields[i] != field) { + continue; + } + + opr = &operands[op->fields[i] - 1]; + + if (value) { + *value = (instr >> opr->shift) & ((1 << opr->bits) - 1); + } + return TRUE; + } + + return FALSE; +} /* operand_value */ + + + +/*====================================================================== + * Called by the disassembler to match an opcode value to an opcode structure. + * + * Arguments: + * instr The instruction (32 bits) to match. This value + * may contain operand values as well as the opcode + * since they will be masked out anyway for this + * search. + * + * Returns the address of an opcode struct (from the opcode table) if the + * operand successfully matched an entry, or 0 if no match was found. + */ + +struct opcode *find_opcode (unsigned long instr) +{ + struct opcode *ptr; + int top = 0; + int bottom = n_opcodes - 1; + int idx; + + /*------------------------------------------------------------*/ + + while (top <= bottom) { + idx = (top + bottom) >> 1; + ptr = &opcodes[idx]; + + if ((instr & ptr->mask) < ptr->opcode) { + bottom = idx - 1; + } else if ((instr & ptr->mask) > ptr->opcode) { + top = idx + 1; + } else { + return ptr; + } + } + + return (struct opcode *) 0; +} /* find_opcode */ + + + +/*====================================================================== + * Called by the assembler to match an opcode name to an opcode structure. + * + * Arguments: + * name The text name of the opcode, e.g. "b", "mtspr", etc. + * + * The opcodes are sorted numerically by their instruction binary code + * so a search for the name cannot use the binary search used by the + * other find routine. + * + * Returns the address of an opcode struct (from the opcode table) if the + * name successfully matched an entry, or 0 if no match was found. + */ + +struct opcode *find_opcode_by_name (char *name) +{ + int idx; + + /*------------------------------------------------------------*/ + + downstring (name); + + for (idx = 0; idx < n_opcodes; ++idx) { + if (!strcmp (name, opcodes[idx].name)) + return &opcodes[idx]; + } + + return (struct opcode *) 0; +} /* find_opcode_by_name */ + + + +/*====================================================================== + * Convert the 'spr' operand from its numeric value to its symbolic name. + * + * Arguments: + * value The value of the 'spr' operand. This value should + * be unmodified from its encoding in the instruction. + * the split-field computations will be performed + * here before the switch. + * + * Returns the address of a character array containing the name of the + * special purpose register defined by the 'value' parameter, or the + * address of a character array containing "???" if no match was found. + */ + +char *spr_name (int value) +{ + unsigned short spr; + static char other[10]; + int i; + + /*------------------------------------------------------------*/ + + /* spr is a 10 bit field whose interpretation has the high and low + five-bit fields reversed from their encoding in the operand */ + + spr = ((value >> 5) & 0x1f) | ((value & 0x1f) << 5); + + for (i = 0; i < n_sprs; ++i) { + if (spr == spr_map[i].spr_val) + return spr_map[i].spr_name; + } + + sprintf (other, "%d", spr); + return other; +} /* spr_name */ + + + +/*====================================================================== + * Convert the 'spr' operand from its symbolic name to its numeric value + * + * Arguments: + * name The symbolic name of the 'spr' operand. The + * split-field encoding will be done by this routine. + * NOTE: name can be a number. + * + * Returns the numeric value for the spr appropriate for encoding a machine + * instruction. Returns 0 if unable to find the SPR. + */ + +int spr_value (char *name) +{ + struct spr_info *sprp; + int spr; + int i; + + /*------------------------------------------------------------*/ + + if (!name || !*name) + return 0; + + if (isdigit ((int) name[0])) { + i = htonl (read_number (name)); + spr = ((i >> 5) & 0x1f) | ((i & 0x1f) << 5); + return spr; + } + + downstring (name); + + for (i = 0; i < n_sprs; ++i) { + sprp = &spr_map[i]; + + if (strcmp (name, sprp->spr_name) == 0) { + /* spr is a 10 bit field whose interpretation has the high and low + five-bit fields reversed from their encoding in the operand */ + i = htonl (sprp->spr_val); + spr = ((i >> 5) & 0x1f) | ((i & 0x1f) << 5); + + return spr; + } + } + + return 0; +} /* spr_value */ + + + +/*====================================================================== + * Convert the 'tbr' operand from its numeric value to its symbolic name. + * + * Arguments: + * value The value of the 'tbr' operand. This value should + * be unmodified from its encoding in the instruction. + * the split-field computations will be performed + * here before the switch. + * + * Returns the address of a character array containing the name of the + * time base register defined by the 'value' parameter, or the address + * of a character array containing "???" if no match was found. + */ + +char *tbr_name (int value) +{ + unsigned short tbr; + + /*------------------------------------------------------------*/ + + /* tbr is a 10 bit field whose interpretation has the high and low + five-bit fields reversed from their encoding in the operand */ + + tbr = ((value >> 5) & 0x1f) | ((value & 0x1f) << 5); + + if (tbr == 268) + return "TBL"; + + else if (tbr == 269) + return "TBU"; + + + return "???"; +} /* tbr_name */ + + + +/*====================================================================== + * Convert the 'tbr' operand from its symbolic name to its numeric value. + * + * Arguments: + * name The symbolic name of the 'tbr' operand. The + * split-field encoding will be done by this routine. + * + * Returns the numeric value for the spr appropriate for encoding a machine + * instruction. Returns 0 if unable to find the TBR. + */ + +int tbr_value (char *name) +{ + int tbr; + int val; + + /*------------------------------------------------------------*/ + + if (!name || !*name) + return 0; + + downstring (name); + + if (isdigit ((int) name[0])) { + val = read_number (name); + + if (val != 268 && val != 269) + return 0; + } else if (strcmp (name, "tbl") == 0) + val = 268; + else if (strcmp (name, "tbu") == 0) + val = 269; + else + return 0; + + /* tbr is a 10 bit field whose interpretation has the high and low + five-bit fields reversed from their encoding in the operand */ + + val = htonl (val); + tbr = ((val >> 5) & 0x1f) | ((val & 0x1f) << 5); + return tbr; +} /* tbr_name */ + + + +/*====================================================================== + * The next several functions (handle_xxx) are the routines that handle + * disassembling the opcodes with simplified mnemonics. + * + * Arguments: + * ctx A pointer to the disassembler context record. + * + * Returns TRUE if the simpler form was printed or FALSE if it was not. + */ + +int handle_bc (struct ppc_ctx *ctx) +{ + unsigned long bo; + unsigned long bi; + static struct opcode blt = { B_OPCODE (16, 0, 0), B_MASK, {O_BD, 0}, + 0, "blt", H_RELATIVE + }; + static struct opcode bne = + { B_OPCODE (16, 0, 0), B_MASK, {O_cr2, O_BD, 0}, + 0, "bne", H_RELATIVE + }; + static struct opcode bdnz = { B_OPCODE (16, 0, 0), B_MASK, {O_BD, 0}, + 0, "bdnz", H_RELATIVE + }; + + /*------------------------------------------------------------*/ + + if (get_operand_value (ctx->op, ctx->instr, O_BO, &bo) == FALSE) + return FALSE; + + if (get_operand_value (ctx->op, ctx->instr, O_BI, &bi) == FALSE) + return FALSE; + + if ((bo == 12) && (bi == 0)) { + ctx->op = &blt; + sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name); + ctx->datalen += 8; + print_operands (ctx); + return TRUE; + } else if ((bo == 4) && (bi == 10)) { + ctx->op = =⃥ + sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name); + ctx->datalen += 8; + print_operands (ctx); + return TRUE; + } else if ((bo == 16) && (bi == 0)) { + ctx->op = &bdnz; + sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name); + ctx->datalen += 8; + print_operands (ctx); + return TRUE; + } + + return FALSE; +} /* handle_blt */ + + + +/*====================================================================== + * Outputs source line information for the disassembler. This should + * be modified in the future to lookup the actual line of source code + * from the file, but for now this will do. + * + * Arguments: + * filename The address of a character array containing the + * absolute path and file name of the source file. + * + * funcname The address of a character array containing the + * name of the function (not C++ demangled (yet)) + * to which this code belongs. + * + * line_no An integer specifying the source line number that + * generated this code. + * + * pfunc The address of a function to call to print the output. + * + * + * Returns TRUE if it was able to output the line info, or false if it was + * not. + */ + +int print_source_line (char *filename, char *funcname, + int line_no, int (*pfunc) (const char *)) +{ + char out_buf[256]; + + /*------------------------------------------------------------*/ + + (*pfunc) (""); /* output a newline */ + sprintf (out_buf, "%s %s(): line %d", filename, funcname, line_no); + (*pfunc) (out_buf); + + return TRUE; +} /* print_source_line */ + + + +/*====================================================================== + * Entry point for the PPC assembler. + * + * Arguments: + * asm_buf An array of characters containing the assembly opcode + * and operands to convert to a POWERPC machine + * instruction. + * + * Returns the machine instruction or zero. + */ + +unsigned long asmppc (unsigned long memaddr, char *asm_buf, int *err) +{ + struct opcode *opc; + struct operand *oper[MAX_OPERANDS]; + unsigned long instr; + unsigned long param; + char *ptr = asm_buf; + char scratch[20]; + int i; + int w_operands = 0; /* wanted # of operands */ + int n_operands = 0; /* # of operands read */ + int asm_debug = 0; + + /*------------------------------------------------------------*/ + + if (err) + *err = 0; + + if (get_word (&ptr, scratch) == 0) + return 0; + + /* Lookup the opcode structure based on the opcode name */ + if ((opc = find_opcode_by_name (scratch)) == (struct opcode *) 0) { + if (err) + *err = E_ASM_BAD_OPCODE; + return 0; + } + + if (asm_debug) { + printf ("asmppc: Opcode = \"%s\"\n", opc->name); + } + + for (i = 0; i < 8; ++i) { + if (opc->fields[i] == 0) + break; + ++w_operands; + } + + if (asm_debug) { + printf ("asmppc: Expecting %d operands\n", w_operands); + } + + instr = opc->opcode; + + /* read each operand */ + while (n_operands < w_operands) { + + oper[n_operands] = &operands[opc->fields[n_operands] - 1]; + + if (oper[n_operands]->hint & OH_SILENT) { + /* Skip silent operands, they are covered in opc->opcode */ + + if (asm_debug) { + printf ("asmppc: Operand %d \"%s\" SILENT\n", n_operands, + oper[n_operands]->name); + } + + ++n_operands; + continue; + } + + if (get_word (&ptr, scratch) == 0) + break; + + if (asm_debug) { + printf ("asmppc: Operand %d \"%s\" : \"%s\"\n", n_operands, + oper[n_operands]->name, scratch); + } + + if ((param = parse_operand (memaddr, opc, oper[n_operands], + scratch, err)) == -1) + return 0; + + instr |= param; + ++n_operands; + } + + if (n_operands < w_operands) { + if (err) + *err = E_ASM_NUM_OPERANDS; + return 0; + } + + if (asm_debug) { + printf ("asmppc: Instruction = 0x%08lx\n", instr); + } + + return instr; +} /* asmppc */ + + + +/*====================================================================== + * Called by the assembler to interpret a single operand + * + * Arguments: + * ctx A pointer to the disassembler context record. + * + * Returns 0 if the operand is ok, or -1 if it is bad. + */ + +int parse_operand (unsigned long memaddr, struct opcode *opc, + struct operand *oper, char *txt, int *err) +{ + long data; + long mask; + int is_neg = 0; + + /*------------------------------------------------------------*/ + + mask = (1 << oper->bits) - 1; + + if (oper->hint & OH_ADDR) { + data = read_number (txt); + + if (opc->hint & H_RELATIVE) + data = data - memaddr; + + if (data < 0) + is_neg = 1; + + data >>= 2; + data &= (mask >> 1); + + if (is_neg) + data |= 1 << (oper->bits - 1); + } + + else if (oper->hint & OH_REG) { + if (txt[0] == 'r' || txt[0] == 'R') + txt++; + else if (txt[0] == '%' && (txt[1] == 'r' || txt[1] == 'R')) + txt += 2; + + data = read_number (txt); + if (data > 31) { + if (err) + *err = E_ASM_BAD_REGISTER; + return -1; + } + + data = htonl (data); + } + + else if (oper->hint & OH_SPR) { + if ((data = spr_value (txt)) == 0) { + if (err) + *err = E_ASM_BAD_SPR; + return -1; + } + } + + else if (oper->hint & OH_TBR) { + if ((data = tbr_value (txt)) == 0) { + if (err) + *err = E_ASM_BAD_TBR; + return -1; + } + } + + else { + data = htonl (read_number (txt)); + } + + return (data & mask) << oper->shift; +} /* parse_operand */ + + +char *asm_error_str (int err) +{ + switch (err) { + case E_ASM_BAD_OPCODE: + return "Bad opcode"; + case E_ASM_NUM_OPERANDS: + return "Bad number of operands"; + case E_ASM_BAD_REGISTER: + return "Bad register number"; + case E_ASM_BAD_SPR: + return "Bad SPR name or number"; + case E_ASM_BAD_TBR: + return "Bad TBR name or number"; + } + + return ""; +} /* asm_error_str */ + + + +/*====================================================================== + * Copy a word from one buffer to another, ignores leading white spaces. + * + * Arguments: + * src The address of a character pointer to the + * source buffer. + * dest A pointer to a character buffer to write the word + * into. + * + * Returns the number of non-white space characters copied, or zero. + */ + +int get_word (char **src, char *dest) +{ + char *ptr = *src; + int nchars = 0; + + /*------------------------------------------------------------*/ + + /* Eat white spaces */ + while (*ptr && isblank (*ptr)) + ptr++; + + if (*ptr == 0) { + *src = ptr; + return 0; + } + + /* Find the text of the word */ + while (*ptr && !isblank (*ptr) && (*ptr != ',')) + dest[nchars++] = *ptr++; + ptr = (*ptr == ',') ? ptr + 1 : ptr; + dest[nchars] = 0; + + *src = ptr; + return nchars; +} /* get_word */ + + + +/*====================================================================== + * Convert a numeric string to a number, be aware of base notations. + * + * Arguments: + * txt The numeric string. + * + * Returns the converted numeric value. + */ + +long read_number (char *txt) +{ + long val; + int is_neg = 0; + + /*------------------------------------------------------------*/ + + if (txt == 0 || *txt == 0) + return 0; + + if (*txt == '-') { + is_neg = 1; + ++txt; + } + + if (txt[0] == '0' && (txt[1] == 'x' || txt[1] == 'X')) /* hex */ + val = simple_strtoul (&txt[2], NULL, 16); + else /* decimal */ + val = simple_strtoul (txt, NULL, 10); + + if (is_neg) + val = -val; + + return val; +} /* read_number */ + + +int downstring (char *s) +{ + if (!s || !*s) + return 0; + + while (*s) { + if (isupper (*s)) + *s = tolower (*s); + s++; + } + + return 0; +} /* downstring */ + + + +/*====================================================================== + * Examines the instruction at the current address and determines the + * next address to be executed. This will take into account branches + * of different types so that a "step" and "next" operations can be + * supported. + * + * Arguments: + * nextaddr The address (to be filled in) of the next + * instruction to execute. This will only be a valid + * address if TRUE is returned. + * + * step_over A flag indicating how to compute addresses for + * branch statements: + * TRUE = Step over the branch (next) + * FALSE = step into the branch (step) + * + * Returns TRUE if it was able to compute the address. Returns FALSE if + * it has a problem reading the current instruction or one of the registers. + */ + +int find_next_address (unsigned char *nextaddr, int step_over, + struct pt_regs *regs) +{ + unsigned long pc; /* SRR0 register from PPC */ + unsigned long ctr; /* CTR register from PPC */ + unsigned long cr; /* CR register from PPC */ + unsigned long lr; /* LR register from PPC */ + unsigned long instr; /* instruction at SRR0 */ + unsigned long next; /* computed instruction for 'next' */ + unsigned long step; /* computed instruction for 'step' */ + unsigned long addr = 0; /* target address operand */ + unsigned long aa = 0; /* AA operand */ + unsigned long lk = 0; /* LK operand */ + unsigned long bo = 0; /* BO operand */ + unsigned long bi = 0; /* BI operand */ + struct opcode *op = 0; /* opcode structure for 'instr' */ + int ctr_ok = 0; + int cond_ok = 0; + int conditional = 0; + int branch = 0; + + /*------------------------------------------------------------*/ + + if (nextaddr == 0 || regs == 0) { + printf ("find_next_address: bad args"); + return FALSE; + } + + pc = regs->nip & 0xfffffffc; + instr = INSTRUCTION (pc); + + if ((op = find_opcode (instr)) == (struct opcode *) 0) { + printf ("find_next_address: can't parse opcode 0x%lx", instr); + return FALSE; + } + + ctr = regs->ctr; + cr = regs->ccr; + lr = regs->link; + + switch (op->opcode) { + case B_OPCODE (16, 0, 0): /* bc */ + case B_OPCODE (16, 0, 1): /* bcl */ + case B_OPCODE (16, 1, 0): /* bca */ + case B_OPCODE (16, 1, 1): /* bcla */ + if (!get_operand_value (op, instr, O_BD, &addr) || + !get_operand_value (op, instr, O_BO, &bo) || + !get_operand_value (op, instr, O_BI, &bi) || + !get_operand_value (op, instr, O_AA, &aa) || + !get_operand_value (op, instr, O_LK, &lk)) + return FALSE; + + if ((addr & (1 << 13)) != 0) + addr = addr - (1 << 14); + addr <<= 2; + conditional = 1; + branch = 1; + break; + + case I_OPCODE (18, 0, 0): /* b */ + case I_OPCODE (18, 0, 1): /* bl */ + case I_OPCODE (18, 1, 0): /* ba */ + case I_OPCODE (18, 1, 1): /* bla */ + if (!get_operand_value (op, instr, O_LI, &addr) || + !get_operand_value (op, instr, O_AA, &aa) || + !get_operand_value (op, instr, O_LK, &lk)) + return FALSE; + + if ((addr & (1 << 23)) != 0) + addr = addr - (1 << 24); + addr <<= 2; + conditional = 0; + branch = 1; + break; + + case XL_OPCODE (19, 528, 0): /* bcctr */ + case XL_OPCODE (19, 528, 1): /* bcctrl */ + if (!get_operand_value (op, instr, O_BO, &bo) || + !get_operand_value (op, instr, O_BI, &bi) || + !get_operand_value (op, instr, O_LK, &lk)) + return FALSE; + + addr = ctr; + aa = 1; + conditional = 1; + branch = 1; + break; + + case XL_OPCODE (19, 16, 0): /* bclr */ + case XL_OPCODE (19, 16, 1): /* bclrl */ + if (!get_operand_value (op, instr, O_BO, &bo) || + !get_operand_value (op, instr, O_BI, &bi) || + !get_operand_value (op, instr, O_LK, &lk)) + return FALSE; + + addr = lr; + aa = 1; + conditional = 1; + branch = 1; + break; + + default: + conditional = 0; + branch = 0; + break; + } + + if (conditional) { + switch ((bo & 0x1e) >> 1) { + case 0: /* 0000y */ + if (--ctr != 0) + ctr_ok = 1; + + cond_ok = !(cr & (1 << (31 - bi))); + break; + + case 1: /* 0001y */ + if (--ctr == 0) + ctr_ok = 1; + + cond_ok = !(cr & (1 << (31 - bi))); + break; + + case 2: /* 001zy */ + ctr_ok = 1; + cond_ok = !(cr & (1 << (31 - bi))); + break; + + case 4: /* 0100y */ + if (--ctr != 0) + ctr_ok = 1; + + cond_ok = cr & (1 << (31 - bi)); + break; + + case 5: /* 0101y */ + if (--ctr == 0) + ctr_ok = 1; + + cond_ok = cr & (1 << (31 - bi)); + break; + + case 6: /* 011zy */ + ctr_ok = 1; + cond_ok = cr & (1 << (31 - bi)); + break; + + case 8: /* 1z00y */ + if (--ctr != 0) + ctr_ok = cond_ok = 1; + break; + + case 9: /* 1z01y */ + if (--ctr == 0) + ctr_ok = cond_ok = 1; + break; + + case 10: /* 1z1zz */ + ctr_ok = cond_ok = 1; + break; + } + } + + if (branch && (!conditional || (ctr_ok && cond_ok))) { + if (aa) + step = addr; + else + step = addr + pc; + + if (lk) + next = pc + 4; + else + next = step; + } else { + step = next = pc + 4; + } + + if (step_over == TRUE) + *(unsigned long *) nextaddr = next; + else + *(unsigned long *) nextaddr = step; + + return TRUE; +} /* find_next_address */ + + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ + +#endif /* CONFIG_COMMANDS & CFG_CMD_BEDBUG */ diff --git a/common/circbuf.c b/common/circbuf.c new file mode 100644 index 0000000..2332c63 --- /dev/null +++ b/common/circbuf.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +#include + + +int buf_init (circbuf_t * buf, unsigned int size) +{ + assert (buf != NULL); + + buf->size = 0; + buf->totalsize = size; + buf->data = (char *) malloc (sizeof (char) * size); + assert (buf->data != NULL); + + buf->top = buf->data; + buf->tail = buf->data; + buf->end = &(buf->data[size]); + + return 1; +} + +int buf_free (circbuf_t * buf) +{ + assert (buf != NULL); + assert (buf->data != NULL); + + free (buf->data); + memset (buf, 0, sizeof (circbuf_t)); + + return 1; +} + +int buf_pop (circbuf_t * buf, char *dest, unsigned int len) +{ + unsigned int i; + char *p = buf->top; + + assert (buf != NULL); + assert (dest != NULL); + + /* Cap to number of bytes in buffer */ + if (len > buf->size) + len = buf->size; + + for (i = 0; i < len; i++) { + dest[i] = *p++; + /* Bounds check. */ + if (p == buf->end) { + p = buf->data; + } + } + + /* Update 'top' pointer */ + buf->top = p; + buf->size -= len; + + return len; +} + +int buf_push (circbuf_t * buf, const char *src, unsigned int len) +{ + /* NOTE: this function allows push to overwrite old data. */ + unsigned int i; + char *p = buf->tail; + + assert (buf != NULL); + assert (src != NULL); + + for (i = 0; i < len; i++) { + *p++ = src[i]; + if (p == buf->end) { + p = buf->data; + } + /* Make sure pushing too much data just replaces old data */ + if (buf->size < buf->totalsize) { + buf->size++; + } else { + buf->top++; + if (buf->top == buf->end) { + buf->top = buf->data; + } + } + } + + /* Update 'tail' pointer */ + buf->tail = p; + + return len; +} diff --git a/common/cmd_ace.c b/common/cmd_ace.c new file mode 100644 index 0000000..b6d6105 --- /dev/null +++ b/common/cmd_ace.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2004 Picture Elements, Inc. + * Stephen Williams (XXXXXXXXXXXXXXXX) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +#ident "$Id:$" + +/* + * The Xilinx SystemACE chip support is activated by defining + * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE + * to set the base address of the device. This code currently + * assumes that the chip is connected via a byte-wide bus. + * + * The CONFIG_SYSTEMACE also adds to fat support the device class + * "ace" that allows the user to execute "fatls ace 0" and the + * like. This works by making the systemace_get_dev function + * available to cmd_fat.c:get_dev and filling in a block device + * description that has all the bits needed for FAT support to + * read sectors. + * + * According to Xilinx technical support, before accessing the + * SystemACE CF you need to set the following control bits: + * FORCECFGMODE : 1 + * CFGMODE : 0 + * CFGSTART : 0 + */ + +# include +# include +# include +# include +# include + +#ifdef CONFIG_SYSTEMACE + +/* + * The ace_readw and writew functions read/write 16bit words, but the + * offset value is the BYTE offset as most used in the Xilinx + * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined + * to be the base address for the chip, usually in the local + * peripheral bus. + */ +static unsigned ace_readw(unsigned offset) +{ +#if (CFG_SYSTEMACE_WIDTH == 8) + u16 temp; + +#if !defined(__BIG_ENDIAN) + temp =((u16)readb(CFG_SYSTEMACE_BASE+offset) << 8); + temp |= (u16)readb(CFG_SYSTEMACE_BASE+offset+1); +#else + temp = (u16)readb(CFG_SYSTEMACE_BASE+offset); + temp |=((u16)readb(CFG_SYSTEMACE_BASE+offset+1) << 8); +#endif + return temp; +#else + return readw(CFG_SYSTEMACE_BASE+offset); +#endif +} + +static void ace_writew(unsigned val, unsigned offset) +{ +#if (CFG_SYSTEMACE_WIDTH == 8) +#if !defined(__BIG_ENDIAN) + writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset); + writeb((u8)val, CFG_SYSTEMACE_BASE+offset+1); +#else + writeb((u8)val, CFG_SYSTEMACE_BASE+offset); + writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset+1); +#endif +#else + writew(val, CFG_SYSTEMACE_BASE+offset); +#endif +} + +/* */ + +static unsigned long systemace_read(int dev, + unsigned long start, + unsigned long blkcnt, + unsigned long *buffer); + +static block_dev_desc_t systemace_dev = {0}; + +static int get_cf_lock(void) +{ + int retry = 10; + + /* CONTROLREG = LOCKREG */ + unsigned val=ace_readw(0x18); + val|=0x0002; + ace_writew((val&0xffff), 0x18); + + /* Wait for MPULOCK in STATUSREG[15:0] */ + while (! (ace_readw(0x04) & 0x0002)) { + + if (retry < 0) + return -1; + + udelay(100000); + retry -= 1; + } + + return 0; +} + +static void release_cf_lock(void) +{ + unsigned val=ace_readw(0x18); + val&=~(0x0002); + ace_writew((val&0xffff), 0x18); +} + +block_dev_desc_t * systemace_get_dev(int dev) +{ + /* The first time through this, the systemace_dev object is + not yet initialized. In that case, fill it in. */ + if (systemace_dev.blksz == 0) { + systemace_dev.if_type = IF_TYPE_UNKNOWN; + systemace_dev.dev = 0; + systemace_dev.part_type = PART_TYPE_UNKNOWN; + systemace_dev.type = DEV_TYPE_HARDDISK; + systemace_dev.blksz = 512; + systemace_dev.removable = 1; + systemace_dev.block_read = systemace_read; + + init_part(&systemace_dev); + + } + + return &systemace_dev; +} + +/* + * This function is called (by dereferencing the block_read pointer in + * the dev_desc) to read blocks of data. The return value is the + * number of blocks read. A zero return indicates an error. + */ +static unsigned long systemace_read(int dev, + unsigned long start, + unsigned long blkcnt, + unsigned long *buffer) +{ + int retry; + unsigned blk_countdown; + unsigned char*dp = (unsigned char*)buffer; + unsigned val; + + if (get_cf_lock() < 0) { + unsigned status = ace_readw(0x04); + + /* If CFDETECT is false, card is missing. */ + if (! (status&0x0010)) { + printf("** CompactFlash card not present. **\n"); + return 0; + } + + printf("**** ACE locked away from me (STATUSREG=%04x)\n", status); + return 0; + } + +#ifdef DEBUG_SYSTEMACE + printf("... systemace read %lu sectors at %lu\n", blkcnt, start); +#endif + + retry = 2000; + for (;;) { + val = ace_readw(0x04); + + /* If CFDETECT is false, card is missing. */ + if (! (val & 0x0010)) { + printf("**** ACE CompactFlash not found.\n"); + release_cf_lock(); + return 0; + } + + /* If RDYFORCMD, then we are ready to go. */ + if (val & 0x0100) + break; + + if (retry < 0) { + printf("**** SystemACE not ready.\n"); + release_cf_lock(); + return 0; + } + + udelay(1000); + retry -= 1; + } + + /* The SystemACE can only transfer 256 sectors at a time, so + limit the current chunk of sectors. The blk_countdown + variable is the number of sectors left to transfer. */ + + blk_countdown = blkcnt; + while (blk_countdown > 0) { + unsigned trans = blk_countdown; + + if (trans > 256) trans = 256; + +#ifdef DEBUG_SYSTEMACE + printf("... transfer %lu sector in a chunk\n", trans); +#endif + /* Write LBA block address */ + ace_writew((start>> 0) & 0xffff, 0x10); + ace_writew((start>>16) & 0x00ff, 0x12); + + /* NOTE: in the Write Sector count below, a count of 0 + causes a transfer of 256, so &0xff gives the right + value for whatever transfer count we want. */ + + /* Write sector count | ReadMemCardData. */ + ace_writew((trans&0xff) | 0x0300, 0x14); + + /* Reset the configruation controller */ + val = ace_readw(0x18); + val|=0x0080; + ace_writew(val, 0x18); + + retry = trans * 16; + while (retry > 0) { + int idx; + + /* Wait for buffer to become ready. */ + while (! (ace_readw(0x04) & 0x0020)) { + udelay(100); + } + + /* Read 16 words of 2bytes from the sector buffer. */ + for (idx = 0 ; idx < 16 ; idx += 1) { + unsigned short val = ace_readw(0x40); + *dp++ = val & 0xff; + *dp++ = (val>>8) & 0xff; + } + + retry -= 1; + } + + /* Clear the configruation controller reset */ + val = ace_readw(0x18); + val&=~0x0080; + ace_writew(val, 0x18); + + /* Count the blocks we transfer this time. */ + start += trans; + blk_countdown -= trans; + } + + release_cf_lock(); + + return blkcnt; +} +#endif /* CONFIG_SYSTEMACE */ diff --git a/common/cmd_autoscript.c b/common/cmd_autoscript.c new file mode 100644 index 0000000..e325302 --- /dev/null +++ b/common/cmd_autoscript.c @@ -0,0 +1,182 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, kharris@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * autoscript allows a remote host to download a command file and, + * optionally, binary data for automatically updating the target. For + * example, you create a new kernel image and want the user to be + * able to simply download the image and the machine does the rest. + * The kernel image is postprocessed with mkimage, which creates an + * image with a script file prepended. If enabled, autoscript will + * verify the script and contents of the download and execute the + * script portion. This would be responsible for erasing flash, + * copying the new image, and rebooting the machine. + */ + +/* #define DEBUG */ + +#include +#include +#include +#include +#include +#if defined(CONFIG_8xx) +#include +#endif +#ifdef CFG_HUSH_PARSER +#include +#endif + +#if defined(CONFIG_AUTOSCRIPT) || \ + (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT ) + +extern image_header_t header; /* from cmd_bootm.c */ +int +autoscript (ulong addr) +{ + ulong crc, data, len; + image_header_t *hdr = &header; + ulong *len_ptr; + char *cmd; + int rcode = 0; + int verify; + + cmd = getenv ("verify"); + verify = (cmd && (*cmd == 'n')) ? 0 : 1; + + + memmove (hdr, (char *)addr, sizeof(image_header_t)); + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts ("Bad magic number\n"); + return 1; + } + + crc = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + len = sizeof (image_header_t); + data = (ulong)hdr; + if (crc32(0, (uchar *)data, len) != crc) { + puts ("Bad header crc\n"); + return 1; + } + + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + if (verify) { + if (crc32(0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { + puts ("Bad data crc\n"); + return 1; + } + } + + if (hdr->ih_type != IH_TYPE_SCRIPT) { + puts ("Bad image type\n"); + return 1; + } + + /* get length of script */ + len_ptr = (ulong *)data; + + if ((len = ntohl(*len_ptr)) == 0) { + puts ("Empty Script\n"); + return 1; + } + + debug ("** Script length: %ld\n", len); + + if ((cmd = malloc (len + 1)) == NULL) { + return 1; + } + + while (*len_ptr++); + + /* make sure cmd is null terminated */ + memmove (cmd, (char *)len_ptr, len); + *(cmd + len) = 0; + +#ifdef CFG_HUSH_PARSER /*?? */ + rcode = parse_string_outer (cmd, FLAG_PARSE_SEMICOLON); +#else + { + char *line = cmd; + char *next = cmd; + + /* + * break into individual lines, + * and execute each line; + * terminate on error. + */ + while (*next) { + if (*next == '\n') { + *next = '\0'; + /* run only non-empty commands */ + if ((next - line) > 1) { + debug ("** exec: \"%s\"\n", + line); + if (run_command (line, 0) < 0) { + rcode = 1; + break; + } + } + line = next + 1; + } + ++next; + } + } +#endif + free (cmd); + return rcode; +} + +#endif /* CONFIG_AUTOSCRIPT || CFG_CMD_AUTOSCRIPT */ +/**************************************************/ +#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) +int +do_autoscript (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + int rcode; + + if (argc < 2) { + addr = CFG_LOAD_ADDR; + } else { + addr = simple_strtoul (argv[1],0,16); + } + + printf ("## Executing script at %08lx\n",addr); + rcode = autoscript (addr); + return rcode; +} + +#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) +U_BOOT_CMD( + autoscr, 2, 0, do_autoscript, + "autoscr - run script from memory\n", + "[addr] - run script starting at addr" + " - A valid autoscr header must be present\n" +); +#endif /* CFG_CMD_AUTOSCRIPT */ + +#endif /* CONFIG_AUTOSCRIPT || CFG_CMD_AUTOSCRIPT */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c new file mode 100644 index 0000000..40e28dd --- /dev/null +++ b/common/cmd_bdinfo.c @@ -0,0 +1,268 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Boot support + */ +#include +#include +#include /* for print_IPaddr */ + + +#if (CONFIG_COMMANDS & CFG_CMD_BDI) +static void print_num(const char *, ulong); + +#ifndef CONFIG_ARM /* PowerPC and other */ + +#ifdef CONFIG_PPC +static void print_str(const char *, const char *); + +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + bd_t *bd = gd->bd; + char buf[32]; + +#ifdef DEBUG + print_num ("bd address", (ulong)bd ); +#endif + print_num ("memstart", bd->bi_memstart ); + print_num ("memsize", bd->bi_memsize ); + print_num ("flashstart", bd->bi_flashstart ); + print_num ("flashsize", bd->bi_flashsize ); + print_num ("flashoffset", bd->bi_flashoffset ); + print_num ("sramstart", bd->bi_sramstart ); + print_num ("sramsize", bd->bi_sramsize ); +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \ + defined(CONFIG_8260) || defined(CONFIG_E500) + print_num ("immr_base", bd->bi_immr_base ); +#endif + print_num ("bootflags", bd->bi_bootflags ); +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) + print_str ("procfreq", strmhz(buf, bd->bi_procfreq)); + print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq)); +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) + print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq)); +#endif +#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */ +#if defined(CONFIG_CPM2) + print_str ("vco", strmhz(buf, bd->bi_vco)); + print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq)); + print_str ("brgfreq", strmhz(buf, bd->bi_brgfreq)); +#endif + print_str ("intfreq", strmhz(buf, bd->bi_intfreq)); +#if defined(CONFIG_CPM2) + print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq)); +#endif + print_str ("busfreq", strmhz(buf, bd->bi_busfreq)); +#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */ +#if defined(CONFIG_MPC8220) + print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq)); + print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq)); + print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq)); + print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq)); + print_str ("pevfreq", strmhz(buf, bd->bi_pevfreq)); +#endif + + puts ("ethaddr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + } + +#if defined(CONFIG_HAS_ETH1) + puts ("\neth1addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]); + } +#endif + +#if defined(CONFIG_HAS_ETH2) + puts ("\neth2addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]); + } +#endif + +#if defined(CONFIG_HAS_ETH3) + puts ("\neth3addr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]); + } +#endif + +#ifdef CONFIG_HERMES + print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed)); +#endif + puts ("\nIP addr = "); print_IPaddr (bd->bi_ip_addr); + printf ("\nbaudrate = %6ld bps\n", bd->bi_baudrate ); + return 0; +} + +#elif defined(CONFIG_NIOS) /* NIOS*/ + +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + bd_t *bd = gd->bd; + + print_num ("memstart", (ulong)bd->bi_memstart); + print_num ("memsize", (ulong)bd->bi_memsize); + print_num ("flashstart", (ulong)bd->bi_flashstart); + print_num ("flashsize", (ulong)bd->bi_flashsize); + print_num ("flashoffset", (ulong)bd->bi_flashoffset); + + puts ("ethaddr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + } + puts ("\nip_addr = "); + print_IPaddr (bd->bi_ip_addr); + printf ("\nbaudrate = %ld bps\n", bd->bi_baudrate); + + return 0; +} + +#elif defined(CONFIG_NIOS2) /* Nios-II */ + +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + bd_t *bd = gd->bd; + + print_num ("mem start", (ulong)bd->bi_memstart); + print_num ("mem size", (ulong)bd->bi_memsize); + print_num ("flash start", (ulong)bd->bi_flashstart); + print_num ("flash size", (ulong)bd->bi_flashsize); + print_num ("flash offset", (ulong)bd->bi_flashoffset); + +#if defined(CFG_SRAM_BASE) + print_num ("sram start", (ulong)bd->bi_sramstart); + print_num ("sram size", (ulong)bd->bi_sramsize); +#endif + +#if defined(CFG_CMD_NET) + puts ("ethaddr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + } + puts ("\nip_addr = "); + print_IPaddr (bd->bi_ip_addr); +#endif + + printf ("\nbaudrate = %ld bps\n", bd->bi_baudrate); + + return 0; +} + +#else /* ! PPC, which leaves MIPS */ + +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + bd_t *bd = gd->bd; + + print_num ("boot_params", (ulong)bd->bi_boot_params); + print_num ("memstart", (ulong)bd->bi_memstart); + print_num ("memsize", (ulong)bd->bi_memsize); + print_num ("flashstart", (ulong)bd->bi_flashstart); + print_num ("flashsize", (ulong)bd->bi_flashsize); + print_num ("flashoffset", (ulong)bd->bi_flashoffset); + + puts ("ethaddr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + } + puts ("\nip_addr = "); + print_IPaddr (bd->bi_ip_addr); + printf ("\nbaudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} +#endif /* MIPS */ + +#else /* ARM */ + +int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + bd_t *bd = gd->bd; + + print_num ("arch_number", bd->bi_arch_number); + print_num ("env_t", (ulong)bd->bi_env); + print_num ("boot_params", (ulong)bd->bi_boot_params); + + for (i=0; i start", bd->bi_dram[i].start); + print_num("-> size", bd->bi_dram[i].size); + } + + puts ("ethaddr ="); + for (i=0; i<6; ++i) { + printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); + } + puts ( "\n" + "ip_addr = "); + print_IPaddr (bd->bi_ip_addr); + printf ("\n" + "baudrate = %d bps\n", bd->bi_baudrate); + + return 0; +} + +#endif /* CONFIG_ARM XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ + +static void print_num(const char *name, ulong value) +{ + printf ("%-12s= 0x%08lX\n", name, value); +} + +#ifdef CONFIG_PPC +static void print_str(const char *name, const char *str) +{ + printf ("%-12s= %6s MHz\n", name, str); +} +#endif /* CONFIG_PPC */ + + +/* -------------------------------------------------------------------- */ + +U_BOOT_CMD( + bdinfo, 1, 1, do_bdinfo, + "bdinfo - print Board Info structure\n", + NULL +); +#endif /* CFG_CMD_BDI */ diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c new file mode 100644 index 0000000..cdb379d --- /dev/null +++ b/common/cmd_bedbug.c @@ -0,0 +1,449 @@ +/* + * BedBug Functions + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + +#ifndef MAX +#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif + +extern void show_regs __P((struct pt_regs*)); +extern int run_command __P((const char*, int)); +extern char console_buffer[]; + +ulong dis_last_addr = 0; /* Last address disassembled */ +ulong dis_last_len = 20; /* Default disassembler length */ +CPU_DEBUG_CTX bug_ctx; /* Bedbug context structure */ + + +/* ====================================================================== + * U-Boot's puts function does not append a newline, so the bedbug stuff + * will use this for the output of the dis/assembler. + * ====================================================================== */ + +int bedbug_puts(const char *str) +{ + /* -------------------------------------------------- */ + + printf( "%s\r\n", str ); + return 0; +} /* bedbug_puts */ + + + +/* ====================================================================== + * Initialize the bug_ctx structure used by the bedbug debugger. This is + * specific to the CPU since each has different debug registers and + * settings. + * ====================================================================== */ + +void bedbug_init( void ) +{ + /* -------------------------------------------------- */ + +#if defined(CONFIG_4xx) + void bedbug405_init( void ); + bedbug405_init(); +#elif defined(CONFIG_8xx) + void bedbug860_init( void ); + bedbug860_init(); +#endif + +#if defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260) + /* Processors that are 603e core based */ + void bedbug603e_init( void ); + + bedbug603e_init(); +#endif + + return; +} /* bedbug_init */ + + + +/* ====================================================================== + * Entry point from the interpreter to the disassembler. Repeated calls + * will resume from the last disassembled address. + * ====================================================================== */ +int do_bedbug_dis (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; /* Address to start disassembly from */ + ulong len; /* # of instructions to disassemble */ + /* -------------------------------------------------- */ + + /* Setup to go from the last address if none is given */ + addr = dis_last_addr; + len = dis_last_len; + + if (argc < 2) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if(( flag & CMD_FLAG_REPEAT ) == 0 ) + { + /* New command */ + addr = simple_strtoul( argv[1], NULL, 16 ); + + /* If an extra param is given then it is the length */ + if( argc > 2 ) + len = simple_strtoul( argv[2], NULL, 16 ); + } + + /* Run the disassembler */ + disppc( (unsigned char *)addr, 0, len, bedbug_puts, F_RADHEX ); + + dis_last_addr = addr + (len * 4); + dis_last_len = len; + return 0; +} /* do_bedbug_dis */ +U_BOOT_CMD( + ds, 3, 1, do_bedbug_dis, + "ds - disassemble memory\n", + "ds
[# instructions]\n" +); + +/* ====================================================================== + * Entry point from the interpreter to the assembler. Assembles + * instructions in consecutive memory locations until a '.' (period) is + * entered on a line by itself. + * ====================================================================== */ +int do_bedbug_asm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + long mem_addr; /* Address to assemble into */ + unsigned long instr; /* Machine code for text */ + char prompt[ 15 ]; /* Prompt string for user input */ + int asm_err; /* Error code from the assembler*/ + /* -------------------------------------------------- */ + int rcode = 0; + + if (argc < 2) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + printf( "\nEnter '.' when done\n" ); + mem_addr = simple_strtoul( argv[ 1 ], NULL, 16 ); + + while( 1 ) + { + putc( '\n' ); + disppc( (unsigned char *)mem_addr, 0, 1, bedbug_puts, F_RADHEX ); + + sprintf( prompt, "%08lx: ", mem_addr ); + readline( prompt ); + + if( console_buffer[ 0 ] && strcmp( console_buffer, "." )) + { + if(( instr = asmppc( mem_addr, console_buffer, &asm_err )) != 0 ) + { + *(unsigned long *)mem_addr = instr; + mem_addr += 4; + } + else + { + printf( "*** Error: %s ***\n", asm_error_str( asm_err )); + rcode = 1; + } + } + else + { + break; + } + } + return rcode; +} /* do_bedbug_asm */ +U_BOOT_CMD( + as, 2, 0, do_bedbug_asm, + "as - assemble memory\n", + "as
\n" +); + +/* ====================================================================== + * Used to set a break point from the interpreter. Simply calls into the + * CPU-specific break point set routine. + * ====================================================================== */ + +int do_bedbug_break (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + /* -------------------------------------------------- */ + if( bug_ctx.do_break ) + (*bug_ctx.do_break)( cmdtp, flag, argc, argv ); + return 0; + +} /* do_bedbug_break */ +U_BOOT_CMD( + break, 3, 0, do_bedbug_break, + "break - set or clear a breakpoint\n", + " - Set or clear a breakpoint\n" + "break
- Break at an address\n" + "break off - Disable breakpoint.\n" + "break show - List breakpoints.\n" +); + +/* ====================================================================== + * Called from the debug interrupt routine. Simply calls the CPU-specific + * breakpoint handling routine. + * ====================================================================== */ + +void do_bedbug_breakpoint (struct pt_regs *regs) +{ + /* -------------------------------------------------- */ + + if( bug_ctx.break_isr ) + (*bug_ctx.break_isr)( regs ); + + return; +} /* do_bedbug_breakpoint */ + + + +/* ====================================================================== + * Called from the CPU-specific breakpoint handling routine. Enter a + * mini main loop until the stopped flag is cleared from the breakpoint + * context. + * + * This handles the parts of the debugger that are common to all CPU's. + * ====================================================================== */ + +void bedbug_main_loop( unsigned long addr, struct pt_regs *regs ) +{ + int len; /* Length of command line */ + int flag; /* Command flags */ + int rc = 0; /* Result from run_command*/ + char prompt_str[ 20 ]; /* Prompt string */ + static char lastcommand[ CFG_CBSIZE ] = {0}; /* previous command */ + /* -------------------------------------------------- */ + + if( bug_ctx.clear ) + (*bug_ctx.clear)( bug_ctx.current_bp ); + + printf( "Breakpoint %d: ", bug_ctx.current_bp ); + disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); + + bug_ctx.stopped = 1; + bug_ctx.regs = regs; + + sprintf( prompt_str, "BEDBUG.%d =>", bug_ctx.current_bp ); + + /* A miniature main loop */ + while( bug_ctx.stopped ) + { + len = readline( prompt_str ); + + flag = 0; /* assume no special flags for now */ + + if (len > 0) + strcpy( lastcommand, console_buffer ); + else if( len == 0 ) + flag |= CMD_FLAG_REPEAT; + + if (len == -1) + printf ("\n"); + else + rc = run_command( lastcommand, flag ); + + if (rc <= 0) { + /* invalid command or not repeatable, forget it */ + lastcommand[0] = 0; + } + } + + bug_ctx.regs = NULL; + bug_ctx.current_bp = 0; + + return; +} /* bedbug_main_loop */ + + + +/* ====================================================================== + * Interpreter command to continue from a breakpoint. Just clears the + * stopped flag in the context so that the breakpoint routine will + * return. + * ====================================================================== */ +int do_bedbug_continue (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + +{ + /* -------------------------------------------------- */ + + if( ! bug_ctx.stopped ) + { + printf( "Not at a breakpoint\n" ); + return 1; + } + + bug_ctx.stopped = 0; + return 0; +} /* do_bedbug_continue */ +U_BOOT_CMD( + continue, 1, 0, do_bedbug_continue, + "continue- continue from a breakpoint\n", + " - continue from a breakpoint.\n" +); + +/* ====================================================================== + * Interpreter command to continue to the next instruction, stepping into + * subroutines. Works by calling the find_next_addr() routine to compute + * the address passes control to the CPU-specific set breakpoint routine + * for the current breakpoint number. + * ====================================================================== */ +int do_bedbug_step (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long addr; /* Address to stop at */ + /* -------------------------------------------------- */ + + if( ! bug_ctx.stopped ) + { + printf( "Not at a breakpoint\n" ); + return 1; + } + + if( !find_next_address( (unsigned char *)&addr, FALSE, bug_ctx.regs )) + return 1; + + if( bug_ctx.set ) + (*bug_ctx.set)( bug_ctx.current_bp, addr ); + + bug_ctx.stopped = 0; + return 0; +} /* do_bedbug_step */ +U_BOOT_CMD( + step, 1, 1, do_bedbug_step, + "step - single step execution.\n", + " - single step execution.\n" +); + +/* ====================================================================== + * Interpreter command to continue to the next instruction, stepping over + * subroutines. Works by calling the find_next_addr() routine to compute + * the address passes control to the CPU-specific set breakpoint routine + * for the current breakpoint number. + * ====================================================================== */ +int do_bedbug_next (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long addr; /* Address to stop at */ + /* -------------------------------------------------- */ + + if( ! bug_ctx.stopped ) + { + printf( "Not at a breakpoint\n" ); + return 1; + } + + if( !find_next_address( (unsigned char *)&addr, TRUE, bug_ctx.regs )) + return 1; + + if( bug_ctx.set ) + (*bug_ctx.set)( bug_ctx.current_bp, addr ); + + bug_ctx.stopped = 0; + return 0; +} /* do_bedbug_next */ +U_BOOT_CMD( + next, 1, 1, do_bedbug_next, + "next - single step execution, stepping over subroutines.\n", + " - single step execution, stepping over subroutines.\n" +); + +/* ====================================================================== + * Interpreter command to print the current stack. This assumes an EABI + * architecture, so it starts with GPR R1 and works back up the stack. + * ====================================================================== */ +int do_bedbug_stack (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long sp; /* Stack pointer */ + unsigned long func; /* LR from stack */ + int depth; /* Stack iteration level */ + int skip = 1; /* Flag to skip the first entry */ + unsigned long top; /* Top of memory address */ + /* -------------------------------------------------- */ + + if( ! bug_ctx.stopped ) + { + printf( "Not at a breakpoint\n" ); + return 1; + } + + top = gd->bd->bi_memstart + gd->bd->bi_memsize; + depth = 0; + + printf( "Depth PC\n" ); + printf( "----- --------\n" ); + printf( "%5d %08lx\n", depth++, bug_ctx.regs->nip ); + + sp = bug_ctx.regs->gpr[ 1 ]; + func = *(unsigned long *)(sp+4); + + while(( func < top ) && ( sp < top )) + { + if( !skip ) + printf( "%5d %08lx\n", depth++, func ); + else + --skip; + + sp = *(unsigned long *)sp; + func = *(unsigned long *)(sp+4); + } + return 0; +} /* do_bedbug_stack */ +U_BOOT_CMD( + where, 1, 1, do_bedbug_stack, + "where - Print the running stack.\n", + " - Print the running stack.\n" +); + +/* ====================================================================== + * Interpreter command to dump the registers. Calls the CPU-specific + * show registers routine. + * ====================================================================== */ +int do_bedbug_rdump (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + /* -------------------------------------------------- */ + + if( ! bug_ctx.stopped ) + { + printf( "Not at a breakpoint\n" ); + return 1; + } + + show_regs( bug_ctx.regs ); + return 0; +} /* do_bedbug_rdump */ +U_BOOT_CMD( + rdump, 1, 1, do_bedbug_rdump, + "rdump - Show registers.\n", + " - Show registers.\n" +); +/* ====================================================================== */ +#endif /* CFG_CMD_BEDBUG */ + + +/* + * Copyright (c) 2001 William L. Pitts + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c new file mode 100644 index 0000000..ad412c8 --- /dev/null +++ b/common/cmd_bmp.c @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2002 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * BMP handling routines + */ + +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BMP) + +static int bmp_info (ulong addr); +static int bmp_display (ulong addr, int x, int y); + +int gunzip(void *, int, unsigned char *, unsigned long *); + +/* + * Subroutine: do_bmp + * + * Description: Handler for 'bmp' command.. + * + * Inputs: argv[1] contains the subcommand + * + * Return: None + * + */ +int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + int x = 0, y = 0; + + switch (argc) { + case 2: /* use load_addr as default address */ + addr = load_addr; + break; + case 3: /* use argument */ + addr = simple_strtoul(argv[2], NULL, 16); + break; + case 5: + addr = simple_strtoul(argv[2], NULL, 16); + x = simple_strtoul(argv[3], NULL, 10); + y = simple_strtoul(argv[4], NULL, 10); + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Allow for short names + * Adjust length if more sub-commands get added + */ + if (strncmp(argv[1],"info",1) == 0) { + return (bmp_info(addr)); + } else if (strncmp(argv[1],"display",1) == 0) { + return (bmp_display(addr, x, y)); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + bmp, 5, 1, do_bmp, + "bmp - manipulate BMP image data\n", + "info - display image info\n" + "bmp display [x y] - display image at x,y\n" +); + +/* + * Subroutine: bmp_info + * + * Description: Show information about bmp file in memory + * + * Inputs: addr address of the bmp file + * + * Return: None + * + */ +static int bmp_info(ulong addr) +{ + bmp_image_t *bmp=(bmp_image_t *)addr; +#ifdef CONFIG_VIDEO_BMP_GZIP + unsigned char *dst = NULL; + ulong len; +#endif /* CONFIG_VIDEO_BMP_GZIP */ + + if (!((bmp->header.signature[0]=='B') && + (bmp->header.signature[1]=='M'))) { + +#ifdef CONFIG_VIDEO_BMP_GZIP + /* + * Decompress bmp image + */ + len = CFG_VIDEO_LOGO_MAX_SIZE; + dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); + if (dst == NULL) { + printf("Error: malloc in gunzip failed!\n"); + return(1); + } + if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) { + printf("There is no valid bmp file at the given address\n"); + return(1); + } + if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); + } + + /* + * Set addr to decompressed image + */ + bmp = (bmp_image_t *)dst; + + /* + * Check for bmp mark 'BM' + */ + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + printf("There is no valid bmp file at the given address\n"); + free(dst); + return(1); + } + + printf("Gzipped BMP image detected!\n"); +#else /* CONFIG_VIDEO_BMP_GZIP */ + printf("There is no valid bmp file at the given address\n"); + return(1); +#endif /* CONFIG_VIDEO_BMP_GZIP */ + } + printf("Image size : %d x %d\n", le32_to_cpu(bmp->header.width), + le32_to_cpu(bmp->header.height)); + printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count)); + printf("Compression : %d\n", le32_to_cpu(bmp->header.compression)); + +#ifdef CONFIG_VIDEO_BMP_GZIP + if (dst) { + free(dst); + } +#endif /* CONFIG_VIDEO_BMP_GZIP */ + + return(0); +} + +/* + * Subroutine: bmp_display + * + * Description: Display bmp file located in memory + * + * Inputs: addr address of the bmp file + * + * Return: None + * + */ +static int bmp_display(ulong addr, int x, int y) +{ +#if defined(CONFIG_LCD) + extern int lcd_display_bitmap (ulong, int, int); + + return (lcd_display_bitmap (addr, x, y)); +#elif defined(CONFIG_VIDEO) + extern int video_display_bitmap (ulong, int, int); + return (video_display_bitmap (addr, x, y)); +#else +# error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO +#endif +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) */ diff --git a/common/cmd_boot.c b/common/cmd_boot.c new file mode 100644 index 0000000..5b58d4e --- /dev/null +++ b/common/cmd_boot.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Misc boot support + */ +#include +#include +#include + + +/* -------------------------------------------------------------------- */ + +int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_I386) + DECLARE_GLOBAL_DATA_PTR; +#endif + ulong addr, rc; + int rcode = 0; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + addr = simple_strtoul(argv[1], NULL, 16); + + printf ("## Starting application at 0x%08lX ...\n", addr); + + /* + * pass address parameter as argv[0] (aka command name), + * and all remaining args + */ +#if defined(CONFIG_I386) + /* + * x86 does not use a dedicated register to pass the pointer + * to the global_data + */ + argv[0] = (char *)gd; +#endif +#if !defined(CONFIG_NIOS) + rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]); +#else + /* + * Nios function pointers are address >> 1 + */ + rc = ((ulong (*)(int, char *[]))(addr>>1)) (--argc, &argv[1]); +#endif + if (rc != 0) rcode = 1; + + printf ("## Application terminated, rc = 0x%lX\n", rc); + return rcode; +} + +/* -------------------------------------------------------------------- */ + +U_BOOT_CMD( + go, CFG_MAXARGS, 1, do_go, + "go - start application at address 'addr'\n", + "addr [arg ...]\n - start application at address 'addr'\n" + " passing 'arg' as arguments\n" +); + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +U_BOOT_CMD( + reset, 1, 0, do_reset, + "reset - Perform RESET of the CPU\n", + NULL +); diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c new file mode 100644 index 0000000..8599a49 --- /dev/null +++ b/common/cmd_bootm.c @@ -0,0 +1,1421 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Boot support + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_OF_FLAT_TREE +#include +#endif + + /*cmd_boot.c*/ + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) +#include +#endif + +#ifdef CFG_HUSH_PARSER +#include +#endif + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#ifdef CFG_INIT_RAM_LOCK +#include +#endif + +#ifdef CONFIG_LOGBUFFER +#include +#endif + +#ifdef CONFIG_HAS_DATAFLASH +#include +#endif + +/* + * Some systems (for example LWMON) have very short watchdog periods; + * we must make sure to split long operations like memmove() or + * crc32() into reasonable chunks. + */ +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +# define CHUNKSZ (64 * 1024) +#endif + +int gunzip (void *, int, unsigned char *, unsigned long *); + +static void *zalloc(void *, unsigned, unsigned); +static void zfree(void *, void *, unsigned); + +#if (CONFIG_COMMANDS & CFG_CMD_IMI) +static int image_info (unsigned long addr); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IMLS) +#include +extern flash_info_t flash_info[]; /* info for FLASH chips */ +static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +#endif + +static void print_type (image_header_t *hdr); + +#ifdef __I386__ +image_header_t *fake_header(image_header_t *hdr, void *ptr, int size); +#endif + +/* + * Continue booting an OS image; caller already has: + * - copied image header to global variable `header' + * - checked header magic number, checksums (both header & image), + * - verified image architecture (PPC) and type (KERNEL or MULTI), + * - loaded (first part of) image to header load address, + * - disabled interrupts. + */ +typedef void boot_os_Fcn (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, /* of image to boot */ + ulong *len_ptr, /* multi-file image length table */ + int verify); /* getenv("verify")[0] != 'n' */ + +#ifdef DEBUG +extern int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +#endif + +#ifdef CONFIG_PPC +static boot_os_Fcn do_bootm_linux; +#else +extern boot_os_Fcn do_bootm_linux; +#endif +#ifdef CONFIG_SILENT_CONSOLE +static void fixup_silent_linux (void); +#endif +static boot_os_Fcn do_bootm_netbsd; +static boot_os_Fcn do_bootm_rtems; +#if (CONFIG_COMMANDS & CFG_CMD_ELF) +static boot_os_Fcn do_bootm_vxworks; +static boot_os_Fcn do_bootm_qnxelf; +int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ); +int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ); +#endif /* CFG_CMD_ELF */ +#if defined(CONFIG_ARTOS) && defined(CONFIG_PPC) +static boot_os_Fcn do_bootm_artos; +#endif +#ifdef CONFIG_LYNXKDI +static boot_os_Fcn do_bootm_lynxkdi; +extern void lynxkdi_boot( image_header_t * ); +#endif + +image_header_t header; + +ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */ + +int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong iflag; + ulong addr; + ulong data, len, checksum; + ulong *len_ptr; + uint unc_len = 0x400000; + int i, verify; + char *name, *s; + int (*appl)(int, char *[]); + image_header_t *hdr = &header; + + s = getenv ("verify"); + verify = (s && (*s == 'n')) ? 0 : 1; + + if (argc < 2) { + addr = load_addr; + } else { + addr = simple_strtoul(argv[1], NULL, 16); + } + + SHOW_BOOT_PROGRESS (1); + printf ("## Booting image at %08lx ...\n", addr); + + /* Copy header so we can blank CRC field for re-calculation */ +#ifdef CONFIG_HAS_DATAFLASH + if (addr_dataflash(addr)){ + read_dataflash(addr, sizeof(image_header_t), (char *)&header); + } else +#endif + memmove (&header, (char *)addr, sizeof(image_header_t)); + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { +#ifdef __I386__ /* correct image format not implemented yet - fake it */ + if (fake_header(hdr, (void*)addr, -1) != NULL) { + /* to compensate for the addition below */ + addr -= sizeof(image_header_t); + /* turnof verify, + * fake_header() does not fake the data crc + */ + verify = 0; + } else +#endif /* __I386__ */ + { + puts ("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + } + SHOW_BOOT_PROGRESS (2); + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)data, len) != checksum) { + puts ("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS (-2); + return 1; + } + SHOW_BOOT_PROGRESS (3); + +#ifdef CONFIG_HAS_DATAFLASH + if (addr_dataflash(addr)){ + len = ntohl(hdr->ih_size) + sizeof(image_header_t); + read_dataflash(addr, len, (char *)CFG_LOAD_ADDR); + addr = CFG_LOAD_ADDR; + } +#endif + + + /* for multi-file images we need the data part, too */ + print_image_hdr ((image_header_t *)addr); + + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + if (verify) { + puts (" Verifying Checksum ... "); + if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { + printf ("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS (-3); + return 1; + } + puts ("OK\n"); + } + SHOW_BOOT_PROGRESS (4); + + len_ptr = (ulong *)data; + +#if defined(__PPC__) + if (hdr->ih_arch != IH_CPU_PPC) +#elif defined(__ARM__) + if (hdr->ih_arch != IH_CPU_ARM) +#elif defined(__I386__) + if (hdr->ih_arch != IH_CPU_I386) +#elif defined(__mips__) + if (hdr->ih_arch != IH_CPU_MIPS) +#elif defined(__nios__) + if (hdr->ih_arch != IH_CPU_NIOS) +#elif defined(__M68K__) + if (hdr->ih_arch != IH_CPU_M68K) +#elif defined(__microblaze__) + if (hdr->ih_arch != IH_CPU_MICROBLAZE) +#elif defined(__nios2__) + if (hdr->ih_arch != IH_CPU_NIOS2) +#else +# error Unknown CPU type +#endif + { + printf ("Unsupported Architecture 0x%x\n", hdr->ih_arch); + SHOW_BOOT_PROGRESS (-4); + return 1; + } + SHOW_BOOT_PROGRESS (5); + + switch (hdr->ih_type) { + case IH_TYPE_STANDALONE: + name = "Standalone Application"; + /* A second argument overwrites the load address */ + if (argc > 2) { + hdr->ih_load = htonl(simple_strtoul(argv[2], NULL, 16)); + } + break; + case IH_TYPE_KERNEL: + name = "Kernel Image"; + break; + case IH_TYPE_MULTI: + name = "Multi-File Image"; + len = ntohl(len_ptr[0]); + /* OS kernel is always the first image */ + data += 8; /* kernel_len + terminator */ + for (i=1; len_ptr[i]; ++i) + data += 4; + break; + default: printf ("Wrong Image Type for %s command\n", cmdtp->name); + SHOW_BOOT_PROGRESS (-5); + return 1; + } + SHOW_BOOT_PROGRESS (6); + + /* + * We have reached the point of no return: we are going to + * overwrite all exception vector code, so we cannot easily + * recover from any failures any more... + */ + + iflag = disable_interrupts(); + +#ifdef CONFIG_AMIGAONEG3SE + /* + * We've possible left the caches enabled during + * bios emulation, so turn them off again + */ + icache_disable(); + invalidate_l1_instruction_cache(); + flush_data_cache(); + dcache_disable(); +#endif + + switch (hdr->ih_comp) { + case IH_COMP_NONE: + if(ntohl(hdr->ih_load) == addr) { + printf (" XIP %s ... ", name); + } else { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + size_t l = len; + void *to = (void *)ntohl(hdr->ih_load); + void *from = (void *)data; + + printf (" Loading %s ... ", name); + + while (l > 0) { + size_t tail = (l > CHUNKSZ) ? CHUNKSZ : l; + WATCHDOG_RESET(); + memmove (to, from, tail); + to += tail; + from += tail; + l -= tail; + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove ((void *) ntohl(hdr->ih_load), (uchar *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + } + break; + case IH_COMP_GZIP: + printf (" Uncompressing %s ... ", name); + if (gunzip ((void *)ntohl(hdr->ih_load), unc_len, + (uchar *)data, &len) != 0) { + puts ("GUNZIP ERROR - must RESET board to recover\n"); + SHOW_BOOT_PROGRESS (-6); + do_reset (cmdtp, flag, argc, argv); + } + break; +#ifdef CONFIG_BZIP2 + case IH_COMP_BZIP2: + printf (" Uncompressing %s ... ", name); + /* + * If we've got less than 4 MB of malloc() space, + * use slower decompression algorithm which requires + * at most 2300 KB of memory. + */ + i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load), + &unc_len, (char *)data, len, + CFG_MALLOC_LEN < (4096 * 1024), 0); + if (i != BZ_OK) { + printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i); + SHOW_BOOT_PROGRESS (-6); + udelay(100000); + do_reset (cmdtp, flag, argc, argv); + } + break; +#endif /* CONFIG_BZIP2 */ + default: + if (iflag) + enable_interrupts(); + printf ("Unimplemented compression type %d\n", hdr->ih_comp); + SHOW_BOOT_PROGRESS (-7); + return 1; + } + puts ("OK\n"); + SHOW_BOOT_PROGRESS (7); + + switch (hdr->ih_type) { + case IH_TYPE_STANDALONE: + if (iflag) + enable_interrupts(); + + /* load (and uncompress), but don't start if "autostart" + * is set to "no" + */ + if (((s = getenv("autostart")) != NULL) && (strcmp(s,"no") == 0)) { + char buf[32]; + sprintf(buf, "%lX", len); + setenv("filesize", buf); + return 0; + } + appl = (int (*)(int, char *[]))ntohl(hdr->ih_ep); + (*appl)(argc-1, &argv[1]); + return 0; + case IH_TYPE_KERNEL: + case IH_TYPE_MULTI: + /* handled below */ + break; + default: + if (iflag) + enable_interrupts(); + printf ("Can't boot image type %d\n", hdr->ih_type); + SHOW_BOOT_PROGRESS (-8); + return 1; + } + SHOW_BOOT_PROGRESS (8); + + switch (hdr->ih_os) { + default: /* handled by (original) Linux case */ + case IH_OS_LINUX: +#ifdef CONFIG_SILENT_CONSOLE + fixup_silent_linux(); +#endif + do_bootm_linux (cmdtp, flag, argc, argv, + addr, len_ptr, verify); + break; + case IH_OS_NETBSD: + do_bootm_netbsd (cmdtp, flag, argc, argv, + addr, len_ptr, verify); + break; + +#ifdef CONFIG_LYNXKDI + case IH_OS_LYNXOS: + do_bootm_lynxkdi (cmdtp, flag, argc, argv, + addr, len_ptr, verify); + break; +#endif + + case IH_OS_RTEMS: + do_bootm_rtems (cmdtp, flag, argc, argv, + addr, len_ptr, verify); + break; + +#if (CONFIG_COMMANDS & CFG_CMD_ELF) + case IH_OS_VXWORKS: + do_bootm_vxworks (cmdtp, flag, argc, argv, + addr, len_ptr, verify); + break; + case IH_OS_QNX: + do_bootm_qnxelf (cmdtp, flag, argc, argv, + addr, len_ptr, verify); + break; +#endif /* CFG_CMD_ELF */ +#ifdef CONFIG_ARTOS + case IH_OS_ARTOS: + do_bootm_artos (cmdtp, flag, argc, argv, + addr, len_ptr, verify); + break; +#endif + } + + SHOW_BOOT_PROGRESS (-9); +#ifdef DEBUG + puts ("\n## Control returned to monitor - resetting...\n"); + do_reset (cmdtp, flag, argc, argv); +#endif + return 1; +} + +U_BOOT_CMD( + bootm, CFG_MAXARGS, 1, do_bootm, + "bootm - boot application image from memory\n", + "[addr [arg ...]]\n - boot application image stored in memory\n" + "\tpassing arguments 'arg ...'; when booting a Linux kernel,\n" + "\t'arg' can be the address of an initrd image\n" +); + +#ifdef CONFIG_SILENT_CONSOLE +static void +fixup_silent_linux () +{ + DECLARE_GLOBAL_DATA_PTR; + char buf[256], *start, *end; + char *cmdline = getenv ("bootargs"); + + /* Only fix cmdline when requested */ + if (!(gd->flags & GD_FLG_SILENT)) + return; + + debug ("before silent fix-up: %s\n", cmdline); + if (cmdline) { + if ((start = strstr (cmdline, "console=")) != NULL) { + end = strchr (start, ' '); + strncpy (buf, cmdline, (start - cmdline + 8)); + if (end) + strcpy (buf + (start - cmdline + 8), end); + else + buf[start - cmdline + 8] = '\0'; + } else { + strcpy (buf, cmdline); + strcat (buf, " console="); + } + } else { + strcpy (buf, "console="); + } + + setenv ("bootargs", buf); + debug ("after silent fix-up: %s\n", buf); +} +#endif /* CONFIG_SILENT_CONSOLE */ + +#ifdef CONFIG_OF_FLAT_TREE +extern const unsigned char oftree_dtb[]; +extern const unsigned int oftree_dtb_len; +#endif + +#ifdef CONFIG_PPC +static void +do_bootm_linux (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, + ulong *len_ptr, + int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong sp; + ulong len, checksum; + ulong initrd_start, initrd_end; + ulong cmd_start, cmd_end; + ulong initrd_high; + ulong data; + int initrd_copy_to_ram = 1; + char *cmdline; + char *s; + bd_t *kbd; + void (*kernel)(bd_t *, ulong, ulong, ulong, ulong); + image_header_t *hdr = &header; +#ifdef CONFIG_OF_FLAT_TREE + char *of_flat_tree; +#endif + + if ((s = getenv ("initrd_high")) != NULL) { + /* a value of "no" or a similar string will act like 0, + * turning the "load high" feature off. This is intentional. + */ + initrd_high = simple_strtoul(s, NULL, 16); + if (initrd_high == ~0) + initrd_copy_to_ram = 0; + } else { /* not set, no restrictions to load high */ + initrd_high = ~0; + } + +#ifdef CONFIG_LOGBUFFER + kbd=gd->bd; + /* Prevent initrd from overwriting logbuffer */ + if (initrd_high < (kbd->bi_memsize-LOGBUFF_LEN-LOGBUFF_OVERHEAD)) + initrd_high = kbd->bi_memsize-LOGBUFF_LEN-LOGBUFF_OVERHEAD; + debug ("## Logbuffer at 0x%08lX ", kbd->bi_memsize-LOGBUFF_LEN); +#endif + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CFG_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + + asm( "mr %0,1": "=r"(sp) : ); + + debug ("## Current stack ends at 0x%08lX ", sp); + + sp -= 2048; /* just to be sure */ + if (sp > CFG_BOOTMAPSZ) + sp = CFG_BOOTMAPSZ; + sp &= ~0xF; + + debug ("=> set upper limit to 0x%08lX\n", sp); + + cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF); + kbd = (bd_t *)(((ulong)cmdline - sizeof(bd_t)) & ~0xF); + + if ((s = getenv("bootargs")) == NULL) + s = ""; + + strcpy (cmdline, s); + + cmd_start = (ulong)&cmdline[0]; + cmd_end = cmd_start + strlen(cmdline); + + *kbd = *(gd->bd); + +#ifdef DEBUG + printf ("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end); + + do_bdinfo (NULL, 0, 0, NULL); +#endif + + if ((s = getenv ("clocks_in_mhz")) != NULL) { + /* convert all clock information to MHz */ + kbd->bi_intfreq /= 1000000L; + kbd->bi_busfreq /= 1000000L; +#if defined(CONFIG_MPC8220) + kbd->bi_inpfreq /= 1000000L; + kbd->bi_pcifreq /= 1000000L; + kbd->bi_pevfreq /= 1000000L; + kbd->bi_flbfreq /= 1000000L; + kbd->bi_vcofreq /= 1000000L; +#endif +#if defined(CONFIG_CPM2) + kbd->bi_cpmfreq /= 1000000L; + kbd->bi_brgfreq /= 1000000L; + kbd->bi_sccfreq /= 1000000L; + kbd->bi_vco /= 1000000L; +#endif +#if defined(CONFIG_MPC5xxx) + kbd->bi_ipbfreq /= 1000000L; + kbd->bi_pcifreq /= 1000000L; +#endif /* CONFIG_MPC5xxx */ + } + + kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))hdr->ih_ep; + + /* + * Check if there is an initrd image + */ + if (argc >= 3) { + SHOW_BOOT_PROGRESS (9); + + addr = simple_strtoul(argv[2], NULL, 16); + + printf ("## Loading RAMDisk Image at %08lx ...\n", addr); + + /* Copy header so we can blank CRC field for re-calculation */ + memmove (&header, (char *)addr, sizeof(image_header_t)); + + if (hdr->ih_magic != IH_MAGIC) { + puts ("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS (-10); + do_reset (cmdtp, flag, argc, argv); + } + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = hdr->ih_hcrc; + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)data, len) != checksum) { + puts ("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS (-11); + do_reset (cmdtp, flag, argc, argv); + } + + SHOW_BOOT_PROGRESS (10); + + print_image_hdr (hdr); + + data = addr + sizeof(image_header_t); + len = hdr->ih_size; + + if (verify) { + ulong csum = 0; +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + ulong cdata = data, edata = cdata + len; +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + + puts (" Verifying Checksum ... "); + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + + while (cdata < edata) { + ulong chunk = edata - cdata; + + if (chunk > CHUNKSZ) + chunk = CHUNKSZ; + csum = crc32 (csum, (uchar *)cdata, chunk); + cdata += chunk; + + WATCHDOG_RESET(); + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + csum = crc32 (0, (uchar *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + + if (csum != hdr->ih_dcrc) { + puts ("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS (-12); + do_reset (cmdtp, flag, argc, argv); + } + puts ("OK\n"); + } + + SHOW_BOOT_PROGRESS (11); + + if ((hdr->ih_os != IH_OS_LINUX) || + (hdr->ih_arch != IH_CPU_PPC) || + (hdr->ih_type != IH_TYPE_RAMDISK) ) { + puts ("No Linux PPC Ramdisk Image\n"); + SHOW_BOOT_PROGRESS (-13); + do_reset (cmdtp, flag, argc, argv); + } + + /* + * Now check if we have a multifile image + */ + } else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) { + u_long tail = ntohl(len_ptr[0]) % 4; + int i; + + SHOW_BOOT_PROGRESS (13); + + /* skip kernel length and terminator */ + data = (ulong)(&len_ptr[2]); + /* skip any additional image length fields */ + for (i=1; len_ptr[i]; ++i) + data += 4; + /* add kernel length, and align */ + data += ntohl(len_ptr[0]); + if (tail) { + data += 4 - tail; + } + + len = ntohl(len_ptr[1]); + + } else { + /* + * no initrd image + */ + SHOW_BOOT_PROGRESS (14); + + len = data = 0; + } + + if (!data) { + debug ("No initrd\n"); + } + + if (data) { + if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = (ulong)kbd - len; + initrd_start &= ~(4096 - 1); /* align on page */ + + if (initrd_high) { + ulong nsp; + + /* + * the inital ramdisk does not need to be within + * CFG_BOOTMAPSZ as it is not accessed until after + * the mm system is initialised. + * + * do the stack bottom calculation again and see if + * the initrd will fit just below the monitor stack + * bottom without overwriting the area allocated + * above for command line args and board info. + */ + asm( "mr %0,1": "=r"(nsp) : ); + nsp -= 2048; /* just to be sure */ + nsp &= ~0xF; + if (nsp > initrd_high) /* limit as specified */ + nsp = initrd_high; + nsp -= len; + nsp &= ~(4096 - 1); /* align on page */ + if (nsp >= sp) + initrd_start = nsp; + } + + SHOW_BOOT_PROGRESS (12); + + debug ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", + data, data + len - 1, len, len); + + initrd_end = initrd_start + len; + printf (" Loading Ramdisk to %08lx, end %08lx ... ", + initrd_start, initrd_end); +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + { + size_t l = len; + void *to = (void *)initrd_start; + void *from = (void *)data; + + while (l > 0) { + size_t tail = (l > CHUNKSZ) ? CHUNKSZ : l; + WATCHDOG_RESET(); + memmove (to, from, tail); + to += tail; + from += tail; + l -= tail; + } + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove ((void *)initrd_start, (void *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + puts ("OK\n"); + } + } else { + initrd_start = 0; + initrd_end = 0; + } + +#ifdef CONFIG_OF_FLAT_TREE + if (initrd_start == 0) + of_flat_tree = (char *)(((ulong)kbd - OF_FLAT_TREE_MAX_SIZE - + sizeof(bd_t)) & ~0xF); + else + of_flat_tree = (char *)((initrd_start - OF_FLAT_TREE_MAX_SIZE - + sizeof(bd_t)) & ~0xF); +#endif + + debug ("## Transferring control to Linux (at address %08lx) ...\n", + (ulong)kernel); + + SHOW_BOOT_PROGRESS (15); + +#ifndef CONFIG_OF_FLAT_TREE + +#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) + unlock_ram_in_cache(); +#endif + + /* + * Linux Kernel Parameters: + * r3: ptr to board info data + * r4: initrd_start or 0 if no initrd + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + */ + (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); + +#else + ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd); + /* ft_dump_blob(of_flat_tree); */ + +#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) + unlock_ram_in_cache(); +#endif + /* + * Linux Kernel Parameters: + * r3: ptr to OF flat tree, followed by the board info data + * r4: initrd_start or 0 if no initrd + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + */ + (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end, cmd_start, cmd_end); + +#endif +} +#endif /* CONFIG_PPC */ + +static void +do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, + ulong *len_ptr, + int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + + image_header_t *hdr = &header; + + void (*loader)(bd_t *, image_header_t *, char *, char *); + image_header_t *img_addr; + char *consdev; + char *cmdline; + + + /* + * Booting a (NetBSD) kernel image + * + * This process is pretty similar to a standalone application: + * The (first part of an multi-) image must be a stage-2 loader, + * which in turn is responsible for loading & invoking the actual + * kernel. The only differences are the parameters being passed: + * besides the board info strucure, the loader expects a command + * line, the name of the console device, and (optionally) the + * address of the original image header. + */ + + img_addr = 0; + if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) + img_addr = (image_header_t *) addr; + + + consdev = ""; +#if defined (CONFIG_8xx_CONS_SMC1) + consdev = "smc1"; +#elif defined (CONFIG_8xx_CONS_SMC2) + consdev = "smc2"; +#elif defined (CONFIG_8xx_CONS_SCC2) + consdev = "scc2"; +#elif defined (CONFIG_8xx_CONS_SCC3) + consdev = "scc3"; +#endif + + if (argc > 2) { + ulong len; + int i; + + for (i=2, len=0 ; i 2) + cmdline[len++] = ' '; + strcpy (&cmdline[len], argv[i]); + len += strlen (argv[i]); + } + } else if ((cmdline = getenv("bootargs")) == NULL) { + cmdline = ""; + } + + loader = (void (*)(bd_t *, image_header_t *, char *, char *)) hdr->ih_ep; + + printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n", + (ulong)loader); + + SHOW_BOOT_PROGRESS (15); + + /* + * NetBSD Stage-2 Loader Parameters: + * r3: ptr to board info data + * r4: image address + * r5: console device + * r6: boot args string + */ + (*loader) (gd->bd, img_addr, consdev, cmdline); +} + +#if defined(CONFIG_ARTOS) && defined(CONFIG_PPC) + +/* Function that returns a character from the environment */ +extern uchar (*env_get_char)(int); + +static void +do_bootm_artos (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, + ulong *len_ptr, + int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong top; + char *s, *cmdline; + char **fwenv, **ss; + int i, j, nxt, len, envno, envsz; + bd_t *kbd; + void (*entry)(bd_t *bd, char *cmdline, char **fwenv, ulong top); + image_header_t *hdr = &header; + + /* + * Booting an ARTOS kernel image + application + */ + + /* this used to be the top of memory, but was wrong... */ +#ifdef CONFIG_PPC + /* get stack pointer */ + asm volatile ("mr %0,1" : "=r"(top) ); +#endif + debug ("## Current stack ends at 0x%08lX ", top); + + top -= 2048; /* just to be sure */ + if (top > CFG_BOOTMAPSZ) + top = CFG_BOOTMAPSZ; + top &= ~0xF; + + debug ("=> set upper limit to 0x%08lX\n", top); + + /* first check the artos specific boot args, then the linux args*/ + if ((s = getenv("abootargs")) == NULL && (s = getenv("bootargs")) == NULL) + s = ""; + + /* get length of cmdline, and place it */ + len = strlen(s); + top = (top - (len + 1)) & ~0xF; + cmdline = (char *)top; + debug ("## cmdline at 0x%08lX ", top); + strcpy(cmdline, s); + + /* copy bdinfo */ + top = (top - sizeof(bd_t)) & ~0xF; + debug ("## bd at 0x%08lX ", top); + kbd = (bd_t *)top; + memcpy(kbd, gd->bd, sizeof(bd_t)); + + /* first find number of env entries, and their size */ + envno = 0; + envsz = 0; + for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { + for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) + ; + envno++; + envsz += (nxt - i) + 1; /* plus trailing zero */ + } + envno++; /* plus the terminating zero */ + debug ("## %u envvars total size %u ", envno, envsz); + + top = (top - sizeof(char **)*envno) & ~0xF; + fwenv = (char **)top; + debug ("## fwenv at 0x%08lX ", top); + + top = (top - envsz) & ~0xF; + s = (char *)top; + ss = fwenv; + + /* now copy them */ + for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { + for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) + ; + *ss++ = s; + for (j = i; j < nxt; ++j) + *s++ = env_get_char(j); + *s++ = '\0'; + } + *ss++ = NULL; /* terminate */ + + entry = (void (*)(bd_t *, char *, char **, ulong))ntohl(hdr->ih_ep); + (*entry)(kbd, cmdline, fwenv, top); +} +#endif + + +#if (CONFIG_COMMANDS & CFG_CMD_BOOTD) +int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; +#ifndef CFG_HUSH_PARSER + if (run_command (getenv ("bootcmd"), flag) < 0) rcode = 1; +#else + if (parse_string_outer(getenv("bootcmd"), + FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0 ) rcode = 1; +#endif + return rcode; +} + +U_BOOT_CMD( + boot, 1, 1, do_bootd, + "boot - boot default, i.e., run 'bootcmd'\n", + NULL +); + +/* keep old command name "bootd" for backward compatibility */ +U_BOOT_CMD( + bootd, 1, 1, do_bootd, + "bootd - boot default, i.e., run 'bootcmd'\n", + NULL +); + +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IMI) +int do_iminfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int arg; + ulong addr; + int rcode=0; + + if (argc < 2) { + return image_info (load_addr); + } + + for (arg=1; arg ih_magic) != IH_MAGIC) { + puts (" Bad Magic Number\n"); + return 1; + } + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)data, len) != checksum) { + puts (" Bad Header Checksum\n"); + return 1; + } + + /* for multi-file images we need the data part, too */ + print_image_hdr ((image_header_t *)addr); + + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + puts (" Verifying Checksum ... "); + if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { + puts (" Bad Data CRC\n"); + return 1; + } + puts ("OK\n"); + return 0; +} + +U_BOOT_CMD( + iminfo, CFG_MAXARGS, 1, do_iminfo, + "iminfo - print header information for application image\n", + "addr [addr ...]\n" + " - print header information for application image starting at\n" + " address 'addr' in memory; this includes verification of the\n" + " image contents (magic number, header and payload checksums)\n" +); + +#endif /* CFG_CMD_IMI */ + +#if (CONFIG_COMMANDS & CFG_CMD_IMLS) +/*----------------------------------------------------------------------- + * List all images found in flash. + */ +int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + flash_info_t *info; + int i, j; + image_header_t *hdr; + ulong data, len, checksum; + + for (i=0, info=&flash_info[0]; iflash_id == FLASH_UNKNOWN) + goto next_bank; + for (j=0; jsector_count; ++j) { + + if (!(hdr=(image_header_t *)info->start[j]) || + (ntohl(hdr->ih_magic) != IH_MAGIC)) + goto next_sector; + + /* Copy header so we can blank CRC field for re-calculation */ + memmove (&header, (char *)hdr, sizeof(image_header_t)); + + checksum = ntohl(header.ih_hcrc); + header.ih_hcrc = 0; + + if (crc32 (0, (uchar *)&header, sizeof(image_header_t)) + != checksum) + goto next_sector; + + printf ("Image at %08lX:\n", (ulong)hdr); + print_image_hdr( hdr ); + + data = (ulong)hdr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + puts (" Verifying Checksum ... "); + if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { + puts (" Bad Data CRC\n"); + } + puts ("OK\n"); +next_sector: ; + } +next_bank: ; + } + + return (0); +} + +U_BOOT_CMD( + imls, 1, 1, do_imls, + "imls - list all images found in flash\n", + "\n" + " - Prints information about all images found at sector\n" + " boundaries in flash.\n" +); +#endif /* CFG_CMD_IMLS */ + +void +print_image_hdr (image_header_t *hdr) +{ +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) + time_t timestamp = (time_t)ntohl(hdr->ih_time); + struct rtc_time tm; +#endif + + printf (" Image Name: %.*s\n", IH_NMLEN, hdr->ih_name); +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) + to_tm (timestamp, &tm); + printf (" Created: %4d-%02d-%02d %2d:%02d:%02d UTC\n", + tm.tm_year, tm.tm_mon, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec); +#endif /* CFG_CMD_DATE, CONFIG_TIMESTAMP */ + puts (" Image Type: "); print_type(hdr); + printf ("\n Data Size: %d Bytes = ", ntohl(hdr->ih_size)); + print_size (ntohl(hdr->ih_size), "\n"); + printf (" Load Address: %08x\n" + " Entry Point: %08x\n", + ntohl(hdr->ih_load), ntohl(hdr->ih_ep)); + + if (hdr->ih_type == IH_TYPE_MULTI) { + int i; + ulong len; + ulong *len_ptr = (ulong *)((ulong)hdr + sizeof(image_header_t)); + + puts (" Contents:\n"); + for (i=0; (len = ntohl(*len_ptr)); ++i, ++len_ptr) { + printf (" Image %d: %8ld Bytes = ", i, len); + print_size (len, "\n"); + } + } +} + + +static void +print_type (image_header_t *hdr) +{ + char *os, *arch, *type, *comp; + + switch (hdr->ih_os) { + case IH_OS_INVALID: os = "Invalid OS"; break; + case IH_OS_NETBSD: os = "NetBSD"; break; + case IH_OS_LINUX: os = "Linux"; break; + case IH_OS_VXWORKS: os = "VxWorks"; break; + case IH_OS_QNX: os = "QNX"; break; + case IH_OS_U_BOOT: os = "U-Boot"; break; + case IH_OS_RTEMS: os = "RTEMS"; break; +#ifdef CONFIG_ARTOS + case IH_OS_ARTOS: os = "ARTOS"; break; +#endif +#ifdef CONFIG_LYNXKDI + case IH_OS_LYNXOS: os = "LynxOS"; break; +#endif + default: os = "Unknown OS"; break; + } + + switch (hdr->ih_arch) { + case IH_CPU_INVALID: arch = "Invalid CPU"; break; + case IH_CPU_ALPHA: arch = "Alpha"; break; + case IH_CPU_ARM: arch = "ARM"; break; + case IH_CPU_I386: arch = "Intel x86"; break; + case IH_CPU_IA64: arch = "IA64"; break; + case IH_CPU_MIPS: arch = "MIPS"; break; + case IH_CPU_MIPS64: arch = "MIPS 64 Bit"; break; + case IH_CPU_PPC: arch = "PowerPC"; break; + case IH_CPU_S390: arch = "IBM S390"; break; + case IH_CPU_SH: arch = "SuperH"; break; + case IH_CPU_SPARC: arch = "SPARC"; break; + case IH_CPU_SPARC64: arch = "SPARC 64 Bit"; break; + case IH_CPU_M68K: arch = "M68K"; break; + case IH_CPU_MICROBLAZE: arch = "Microblaze"; break; + case IH_CPU_NIOS: arch = "Nios"; break; + case IH_CPU_NIOS2: arch = "Nios-II"; break; + default: arch = "Unknown Architecture"; break; + } + + switch (hdr->ih_type) { + case IH_TYPE_INVALID: type = "Invalid Image"; break; + case IH_TYPE_STANDALONE:type = "Standalone Program"; break; + case IH_TYPE_KERNEL: type = "Kernel Image"; break; + case IH_TYPE_RAMDISK: type = "RAMDisk Image"; break; + case IH_TYPE_MULTI: type = "Multi-File Image"; break; + case IH_TYPE_FIRMWARE: type = "Firmware"; break; + case IH_TYPE_SCRIPT: type = "Script"; break; + default: type = "Unknown Image"; break; + } + + switch (hdr->ih_comp) { + case IH_COMP_NONE: comp = "uncompressed"; break; + case IH_COMP_GZIP: comp = "gzip compressed"; break; + case IH_COMP_BZIP2: comp = "bzip2 compressed"; break; + default: comp = "unknown compression"; break; + } + + printf ("%s %s %s (%s)", arch, os, type, comp); +} + +#define ZALLOC_ALIGNMENT 16 + +static void *zalloc(void *x, unsigned items, unsigned size) +{ + void *p; + + size *= items; + size = (size + ZALLOC_ALIGNMENT - 1) & ~(ZALLOC_ALIGNMENT - 1); + + p = malloc (size); + + return (p); +} + +static void zfree(void *x, void *addr, unsigned nb) +{ + free (addr); +} + +#define HEAD_CRC 2 +#define EXTRA_FIELD 4 +#define ORIG_NAME 8 +#define COMMENT 0x10 +#define RESERVED 0xe0 + +#define DEFLATED 8 + +int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) +{ + z_stream s; + int r, i, flags; + + /* skip header */ + i = 10; + flags = src[3]; + if (src[2] != DEFLATED || (flags & RESERVED) != 0) { + puts ("Error: Bad gzipped data\n"); + return (-1); + } + if ((flags & EXTRA_FIELD) != 0) + i = 12 + src[10] + (src[11] << 8); + if ((flags & ORIG_NAME) != 0) + while (src[i++] != 0) + ; + if ((flags & COMMENT) != 0) + while (src[i++] != 0) + ; + if ((flags & HEAD_CRC) != 0) + i += 2; + if (i >= *lenp) { + puts ("Error: gunzip out of data in header\n"); + return (-1); + } + + s.zalloc = zalloc; + s.zfree = zfree; +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + s.outcb = (cb_func)WATCHDOG_RESET; +#else + s.outcb = Z_NULL; +#endif /* CONFIG_HW_WATCHDOG */ + + r = inflateInit2(&s, -MAX_WBITS); + if (r != Z_OK) { + printf ("Error: inflateInit2() returned %d\n", r); + return (-1); + } + s.next_in = src + i; + s.avail_in = *lenp - i; + s.next_out = dst; + s.avail_out = dstlen; + r = inflate(&s, Z_FINISH); + if (r != Z_OK && r != Z_STREAM_END) { + printf ("Error: inflate() returned %d\n", r); + return (-1); + } + *lenp = s.next_out - (unsigned char *) dst; + inflateEnd(&s); + + return (0); +} + +#ifdef CONFIG_BZIP2 +void bz_internal_error(int errcode) +{ + printf ("BZIP2 internal error %d\n", errcode); +} +#endif /* CONFIG_BZIP2 */ + +static void +do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + image_header_t *hdr = &header; + void (*entry_point)(bd_t *); + + entry_point = (void (*)(bd_t *)) hdr->ih_ep; + + printf ("## Transferring control to RTEMS (at address %08lx) ...\n", + (ulong)entry_point); + + SHOW_BOOT_PROGRESS (15); + + /* + * RTEMS Parameters: + * r3: ptr to board info data + */ + + (*entry_point ) ( gd->bd ); +} + +#if (CONFIG_COMMANDS & CFG_CMD_ELF) +static void +do_bootm_vxworks (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + image_header_t *hdr = &header; + char str[80]; + + sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */ + setenv("loadaddr", str); + do_bootvx(cmdtp, 0, 0, NULL); +} + +static void +do_bootm_qnxelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + image_header_t *hdr = &header; + char *local_args[2]; + char str[16]; + + sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */ + local_args[0] = argv[0]; + local_args[1] = str; /* and provide it via the arguments */ + do_bootelf(cmdtp, 0, 2, local_args); +} +#endif /* CFG_CMD_ELF */ + +#ifdef CONFIG_LYNXKDI +static void +do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, + ulong *len_ptr, + int verify) +{ + lynxkdi_boot( &header ); +} + +#endif /* CONFIG_LYNXKDI */ diff --git a/common/cmd_cache.c b/common/cmd_cache.c new file mode 100644 index 0000000..6c250bc --- /dev/null +++ b/common/cmd_cache.c @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Cache support: switch on or off, get status + */ +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) + +static int on_off (const char *); + +int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + switch (argc) { + case 2: /* on / off */ + switch (on_off(argv[1])) { +#if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */ + default: printf ("Usage:\n%s\n", cmdtp->usage); + return; +#endif + case 0: icache_disable(); + break; + case 1: icache_enable (); + break; + } + /* FALL TROUGH */ + case 1: /* get status */ + printf ("Instruction Cache is %s\n", + icache_status() ? "ON" : "OFF"); + return 0; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + return 0; +} + +int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + switch (argc) { + case 2: /* on / off */ + switch (on_off(argv[1])) { +#if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */ + default: printf ("Usage:\n%s\n", cmdtp->usage); + return; +#endif + case 0: dcache_disable(); + break; + case 1: dcache_enable (); + break; + } + /* FALL TROUGH */ + case 1: /* get status */ + printf ("Data (writethrough) Cache is %s\n", + dcache_status() ? "ON" : "OFF"); + return 0; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + return 0; + +} + +static int on_off (const char *s) +{ + if (strcmp(s, "on") == 0) { + return (1); + } else if (strcmp(s, "off") == 0) { + return (0); + } + return (-1); +} + + +U_BOOT_CMD( + icache, 2, 1, do_icache, + "icache - enable or disable instruction cache\n", + "[on, off]\n" + " - enable or disable instruction cache\n" +); + +U_BOOT_CMD( + dcache, 2, 1, do_dcache, + "dcache - enable or disable data cache\n", + "[on, off]\n" + " - enable or disable data (writethrough) cache\n" +); + +#endif /* CFG_CMD_CACHE */ diff --git a/common/cmd_console.c b/common/cmd_console.c new file mode 100644 index 0000000..1bd3709 --- /dev/null +++ b/common/cmd_console.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Boot support + */ +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_CONSOLE) + +extern void _do_coninfo (void); +int do_coninfo (cmd_tbl_t * cmd, int flag, int argc, char *argv[]) +{ + int i, l; + + /* Scan for valid output and input devices */ + + puts ("List of available devices:\n"); + + for (i = 1; i <= ListNumItems (devlist); i++) { + device_t *dev = ListGetPtrToItem (devlist, i); + + printf ("%-8s %08x %c%c%c ", + dev->name, + dev->flags, + (dev->flags & DEV_FLAGS_SYSTEM) ? 'S' : '.', + (dev->flags & DEV_FLAGS_INPUT) ? 'I' : '.', + (dev->flags & DEV_FLAGS_OUTPUT) ? 'O' : '.'); + + for (l = 0; l < MAX_FILES; l++) { + if (stdio_devices[l] == dev) { + printf ("%s ", stdio_names[l]); + } + } + putc ('\n'); + } + return 0; +} + + +/***************************************************/ + +U_BOOT_CMD( + coninfo, 3, 1, do_coninfo, + "coninfo - print console devices and information\n", + "" +); + +#endif /* CFG_CMD_CONSOLE */ diff --git a/common/cmd_date.c b/common/cmd_date.c new file mode 100644 index 0000000..a569d78 --- /dev/null +++ b/common/cmd_date.c @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * RTC, Date & Time support: get and set date & time + */ +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + +const char *weekdays[] = { + "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", +}; + +#define RELOC(a) ((typeof(a))((unsigned long)(a) + gd->reloc_off)) + +int mk_date (char *, struct rtc_time *); + +int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + struct rtc_time tm; + int rcode = 0; + + switch (argc) { + case 2: /* set date & time */ + if (strcmp(argv[1],"reset") == 0) { + puts ("Reset RTC...\n"); + rtc_reset (); + } else { + /* initialize tm with current time */ + rtc_get (&tm); + /* insert new date & time */ + if (mk_date (argv[1], &tm) != 0) { + puts ("## Bad date format\n"); + return 1; + } + /* and write to RTC */ + rtc_set (&tm); + } + /* FALL TROUGH */ + case 1: /* get date & time */ + rtc_get (&tm); + + printf ("Date: %4d-%02d-%02d (%sday) Time: %2d:%02d:%02d\n", + tm.tm_year, tm.tm_mon, tm.tm_mday, + (tm.tm_wday<0 || tm.tm_wday>6) ? + "unknown " : RELOC(weekdays[tm.tm_wday]), + tm.tm_hour, tm.tm_min, tm.tm_sec); + + return 0; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + rcode = 1; + } + return rcode; +} + +/* + * simple conversion of two-digit string with error checking + */ +static int cnvrt2 (char *str, int *valp) +{ + int val; + + if ((*str < '0') || (*str > '9')) + return (-1); + + val = *str - '0'; + + ++str; + + if ((*str < '0') || (*str > '9')) + return (-1); + + *valp = 10 * val + (*str - '0'); + + return (0); +} + +/* + * Convert date string: MMDDhhmm[[CC]YY][.ss] + * + * Some basic checking for valid values is done, but this will not catch + * all possible error conditions. + */ +int mk_date (char *datestr, struct rtc_time *tmp) +{ + int len, val; + char *ptr; + + ptr = strchr (datestr,'.'); + len = strlen (datestr); + + /* Set seconds */ + if (ptr) { + int sec; + + *ptr++ = '\0'; + if ((len - (ptr - datestr)) != 2) + return (-1); + + len = strlen (datestr); + + if (cnvrt2 (ptr, &sec)) + return (-1); + + tmp->tm_sec = sec; + } else { + tmp->tm_sec = 0; + } + + if (len == 12) { /* MMDDhhmmCCYY */ + int year, century; + + if (cnvrt2 (datestr+ 8, ¢ury) || + cnvrt2 (datestr+10, &year) ) { + return (-1); + } + tmp->tm_year = 100 * century + year; + } else if (len == 10) { /* MMDDhhmmYY */ + int year, century; + + century = tmp->tm_year / 100; + if (cnvrt2 (datestr+ 8, &year)) + return (-1); + tmp->tm_year = 100 * century + year; + } + + switch (len) { + case 8: /* MMDDhhmm */ + /* fall thru */ + case 10: /* MMDDhhmmYY */ + /* fall thru */ + case 12: /* MMDDhhmmCCYY */ + if (cnvrt2 (datestr+0, &val) || + val > 12) { + break; + } + tmp->tm_mon = val; + if (cnvrt2 (datestr+2, &val) || + val > ((tmp->tm_mon==2) ? 29 : 31)) { + break; + } + tmp->tm_mday = val; + + if (cnvrt2 (datestr+4, &val) || + val > 23) { + break; + } + tmp->tm_hour = val; + + if (cnvrt2 (datestr+6, &val) || + val > 59) { + break; + } + tmp->tm_min = val; + + /* calculate day of week */ + GregorianDay (tmp); + + return (0); + default: + break; + } + + return (-1); +} + +/***************************************************/ + +U_BOOT_CMD( + date, 2, 1, do_date, + "date - get/set/reset date & time\n", + "[MMDDhhmm[[CC]YY][.ss]]\ndate reset\n" + " - without arguments: print date & time\n" + " - with numeric argument: set the system date & time\n" + " - with 'reset' argument: reset the RTC\n" +); + +#endif /* CFG_CMD_DATE */ diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c new file mode 100644 index 0000000..5842471 --- /dev/null +++ b/common/cmd_dcr.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * AMCC 4XX DCR Functions + */ + +#include +#include +#include + +#if defined(CONFIG_4xx) && (CONFIG_COMMANDS & CFG_CMD_SETGETDCR) + +/* ======================================================================= + * Interpreter command to retrieve an AMCC PPC 4xx Device Control Register + * ======================================================================= + */ +int do_getdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + unsigned short dcrn; /* Device Control Register Num */ + unsigned long value; /* DCR's value */ + + unsigned long get_dcr (unsigned short); + + /* Validate arguments */ + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Get a DCR */ + dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16); + value = get_dcr (dcrn); + + printf ("%04x: %08lx\n", dcrn, value); + + return 0; +} + + +/* ====================================================================== + * Interpreter command to set an AMCC PPC 4xx Device Control Register + * ====================================================================== +*/ +int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long get_dcr (unsigned short); + unsigned long set_dcr (unsigned short, unsigned long); + unsigned short dcrn; /* Device Control Register Num */ + unsigned long value; + + /* DCR's value */ + int nbytes; + extern char console_buffer[]; + + /* Validate arguments */ + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Set a DCR */ + dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16); + do { + value = get_dcr (dcrn); + printf ("%04x: %08lx", dcrn, value); + nbytes = readline (" ? "); + if (nbytes == 0) { + /* + * pressed as only input, don't modify current + * location and exit command. + */ + nbytes = 1; + return 0; + } else { + unsigned long i; + char *endp; + + i = simple_strtoul (console_buffer, &endp, 16); + nbytes = endp - console_buffer; + if (nbytes) + set_dcr (dcrn, i); + } + } while (nbytes); + + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + getdcr, 2, 1, do_getdcr, + "getdcr - Get an AMCC PPC 4xx DCR's value\n", + "dcrn - return a DCR's value.\n" +); +U_BOOT_CMD( + setdcr, 2, 1, do_setdcr, + "setdcr - Set an AMCC PPC 4xx DCR's value\n", + "dcrn - set a DCR's value.\n" +); + +#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ diff --git a/common/cmd_diag.c b/common/cmd_diag.c new file mode 100644 index 0000000..45c4b31 --- /dev/null +++ b/common/cmd_diag.c @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Diagnostics support + */ +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_DIAG) && defined(CONFIG_POST) + +int do_diag (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int i; + + if (argc == 1 || strcmp (argv[1], "run") != 0) { + /* List test info */ + if (argc == 1) { + puts ("Available hardware tests:\n"); + post_info (NULL); + puts ("Use 'diag [ [ ...]]'" + " to get more info.\n"); + puts ("Use 'diag run [ [ ...]]'" + " to run tests.\n"); + } else { + for (i = 1; i < argc; i++) { + if (post_info (argv[i]) != 0) + printf ("%s - no such test\n", argv[i]); + } + } + } else { + /* Run tests */ + if (argc == 2) { + post_run (NULL, POST_RAM | POST_MANUAL); + } else { + for (i = 2; i < argc; i++) { + if (post_run (argv[i], POST_RAM | POST_MANUAL) != 0) + printf ("%s - unable to execute the test\n", + argv[i]); + } + } + } + + return 0; +} +/***************************************************/ + +U_BOOT_CMD( + diag, CFG_MAXARGS, 0, do_diag, + "diag - perform board diagnostics\n", + " - print list of available tests\n" + "diag [test1 [test2]]\n" + " - print information about specified tests\n" + "diag run - run all available tests\n" + "diag run [test1 [test2]]\n" + " - run specified tests\n" +); + +#endif /* CFG_CMD_DIAG */ diff --git a/common/cmd_display.c b/common/cmd_display.c new file mode 100644 index 0000000..abee844 --- /dev/null +++ b/common/cmd_display.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_DISPLAY) + +#undef DEBUG_DISP + +#define DISP_SIZE 8 +#define CWORD_CLEAR 0x80 +#define CLEAR_DELAY (110 * 2) + +int do_display (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + int pos; + + /* Clear display */ + *((volatile char*)(CFG_DISP_CWORD)) = CWORD_CLEAR; + udelay(1000 * CLEAR_DELAY); + + if (argc < 2) + return (0); + + for (pos = 0, i = 1; i < argc && pos < DISP_SIZE; i++) { + char *p = argv[i], c; + + if (i > 1) { + *((volatile uchar *) (CFG_DISP_CHR_RAM + pos++)) = ' '; +#ifdef DEBUG_DISP + putc(' '); +#endif + } + + while ((c = *p++) != '\0' && pos < DISP_SIZE) { + *((volatile uchar *) (CFG_DISP_CHR_RAM + pos++)) = c; +#ifdef DEBUG_DISP + putc(c); +#endif + } + } + +#ifdef DEBUG_DISP + putc('\n'); +#endif + + return (0); +} + +/***************************************************/ + +U_BOOT_CMD( + display, CFG_MAXARGS, 1, do_display, + "display- display string on dot matrix display\n", + "[]\n" + " - with argument: display on dot matrix display\n" + " - without arguments: clear dot matrix display\n" +); + +#endif /* CFG_CMD_DISPLAY */ diff --git a/common/cmd_doc.c b/common/cmd_doc.c new file mode 100644 index 0000000..5e9bea3 --- /dev/null +++ b/common/cmd_doc.c @@ -0,0 +1,1588 @@ +/* + * Driver for Disk-On-Chip 2000 and Millennium + * (c) 1999 Machine Vision Holdings, Inc. + * (c) 1999, 2000 David Woodhouse + * + * $Id: doc2000.c,v 1.46 2001/10/02 15:05:13 dwmw2 Exp $ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) + +#include +#include +#include +#include +#include + +#ifdef CFG_DOC_SUPPORT_2000 +#define DoC_is_2000(doc) (doc->ChipID == DOC_ChipID_Doc2k) +#else +#define DoC_is_2000(doc) (0) +#endif + +#ifdef CFG_DOC_SUPPORT_MILLENNIUM +#define DoC_is_Millennium(doc) (doc->ChipID == DOC_ChipID_DocMil) +#else +#define DoC_is_Millennium(doc) (0) +#endif + +/* CFG_DOC_PASSIVE_PROBE: + In order to ensure that the BIOS checksum is correct at boot time, and + hence that the onboard BIOS extension gets executed, the DiskOnChip + goes into reset mode when it is read sequentially: all registers + return 0xff until the chip is woken up again by writing to the + DOCControl register. + + Unfortunately, this means that the probe for the DiskOnChip is unsafe, + because one of the first things it does is write to where it thinks + the DOCControl register should be - which may well be shared memory + for another device. I've had machines which lock up when this is + attempted. Hence the possibility to do a passive probe, which will fail + to detect a chip in reset mode, but is at least guaranteed not to lock + the machine. + + If you have this problem, uncomment the following line: +#define CFG_DOC_PASSIVE_PROBE +*/ + +#undef DOC_DEBUG +#undef ECC_DEBUG +#undef PSYCHO_DEBUG +#undef NFTL_DEBUG + +static struct DiskOnChip doc_dev_desc[CFG_MAX_DOC_DEVICE]; + +/* Current DOC Device */ +static int curr_device = -1; + +/* ------------------------------------------------------------------------- */ + +int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; + + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strcmp(argv[1],"info") == 0) { + int i; + + putc ('\n'); + + for (i=0; i= CFG_MAX_DOC_DEVICE)) { + puts ("\nno devices available\n"); + return 1; + } + printf ("\nDevice %d: ", curr_device); + doc_print(&doc_dev_desc[curr_device]); + return 0; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strcmp(argv[1],"device") == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + + printf ("\nDevice %d: ", dev); + if (dev >= CFG_MAX_DOC_DEVICE) { + puts ("unknown device\n"); + return 1; + } + doc_print(&doc_dev_desc[dev]); + /*doc_print (dev);*/ + + if (doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN) { + return 1; + } + + curr_device = dev; + + puts ("... is now current device\n"); + + return 0; + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + /* at least 4 args */ + + if (strcmp(argv[1],"read") == 0 || strcmp(argv[1],"write") == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong off = simple_strtoul(argv[3], NULL, 16); + ulong size = simple_strtoul(argv[4], NULL, 16); + int cmd = (strcmp(argv[1],"read") == 0); + int ret, total; + + printf ("\nDOC %s: device %d offset %ld, size %ld ... ", + cmd ? "read" : "write", curr_device, off, size); + + ret = doc_rw(doc_dev_desc + curr_device, cmd, off, size, + (size_t *)&total, (u_char*)addr); + + printf ("%d bytes %s: %s\n", total, cmd ? "read" : "write", + ret ? "ERROR" : "OK"); + + return ret; + } else if (strcmp(argv[1],"erase") == 0) { + ulong off = simple_strtoul(argv[2], NULL, 16); + ulong size = simple_strtoul(argv[3], NULL, 16); + int ret; + + printf ("\nDOC erase: device %d offset %ld, size %ld ... ", + curr_device, off, size); + + ret = doc_erase (doc_dev_desc + curr_device, off, size); + + printf("%s\n", ret ? "ERROR" : "OK"); + + return ret; + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + rcode = 1; + } + + return rcode; + } +} +U_BOOT_CMD( + doc, 5, 1, do_doc, + "doc - Disk-On-Chip sub-system\n", + "info - show available DOC devices\n" + "doc device [dev] - show or set current device\n" + "doc read addr off size\n" + "doc write addr off size - read/write `size'" + " bytes starting at offset `off'\n" + " to/from memory address `addr'\n" + "doc erase off size - erase `size' bytes of DOC from offset `off'\n" +); + +int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + char *ep; + int dev; + ulong cnt; + ulong addr; + ulong offset = 0; + image_header_t *hdr; + int rcode = 0; + + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_device = getenv ("bootdevice"); + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = getenv ("bootdevice"); + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + case 4: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + offset = simple_strtoul(argv[3], NULL, 16); + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + if (!boot_device) { + puts ("\n** No boot device **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + dev = simple_strtoul(boot_device, &ep, 16); + + if ((dev >= CFG_MAX_DOC_DEVICE) || + (doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN)) { + printf ("\n** Device %d not available\n", dev); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n", + dev, doc_dev_desc[dev].name, doc_dev_desc[dev].physadr, + offset); + + if (doc_rw (doc_dev_desc + dev, 1, offset, + SECTORSIZE, NULL, (u_char *)addr)) { + printf ("** Read error on %d\n", dev); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + hdr = (image_header_t *)addr; + + if (hdr->ih_magic == IH_MAGIC) { + + print_image_hdr (hdr); + + cnt = (hdr->ih_size + sizeof(image_header_t)); + cnt -= SECTORSIZE; + } else { + puts ("\n** Bad Magic Number **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + if (doc_rw (doc_dev_desc + dev, 1, offset + SECTORSIZE, cnt, + NULL, (u_char *)(addr+SECTORSIZE))) { + printf ("** Read error on %d\n", dev); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + /* Loading ok, update default load address */ + + load_addr = addr; + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { + char *local_args[2]; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + + local_args[0] = argv[0]; + local_args[1] = NULL; + + printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); + + do_bootm (cmdtp, 0, 1, local_args); + rcode = 1; + } + return rcode; +} + +U_BOOT_CMD( + docboot, 4, 1, do_docboot, + "docboot - boot from DOC device\n", + "loadAddr dev\n" +); + +int doc_rw (struct DiskOnChip* this, int cmd, + loff_t from, size_t len, + size_t * retlen, u_char * buf) +{ + int noecc, ret = 0, n, total = 0; + char eccbuf[6]; + + while(len) { + /* The ECC will not be calculated correctly if + less than 512 is written or read */ + noecc = (from != (from | 0x1ff) + 1) || (len < 0x200); + + if (cmd) + ret = doc_read_ecc(this, from, len, + (size_t *)&n, (u_char*)buf, + noecc ? (uchar *)NULL : (uchar *)eccbuf); + else + ret = doc_write_ecc(this, from, len, + (size_t *)&n, (u_char*)buf, + noecc ? (uchar *)NULL : (uchar *)eccbuf); + + if (ret) + break; + + from += n; + buf += n; + total += n; + len -= n; + } + + if (retlen) + *retlen = total; + + return ret; +} + +void doc_print(struct DiskOnChip *this) { + printf("%s at 0x%lX,\n" + "\t %d chip%s %s, size %d MB, \n" + "\t total size %ld MB, sector size %ld kB\n", + this->name, this->physadr, this->numchips, + this->numchips>1 ? "s" : "", this->chips_name, + 1 << (this->chipshift - 20), + this->totlen >> 20, this->erasesize >> 10); + + if (this->nftl_found) { + struct NFTLrecord *nftl = &this->nftl; + unsigned long bin_size, flash_size; + + bin_size = nftl->nb_boot_blocks * this->erasesize; + flash_size = (nftl->nb_blocks - nftl->nb_boot_blocks) * this->erasesize; + + printf("\t NFTL boot record:\n" + "\t Binary partition: size %ld%s\n" + "\t Flash disk partition: size %ld%s, offset 0x%lx\n", + bin_size > (1 << 20) ? bin_size >> 20 : bin_size >> 10, + bin_size > (1 << 20) ? "MB" : "kB", + flash_size > (1 << 20) ? flash_size >> 20 : flash_size >> 10, + flash_size > (1 << 20) ? "MB" : "kB", bin_size); + } else { + puts ("\t No NFTL boot record found.\n"); + } +} + +/* ------------------------------------------------------------------------- */ + +/* This function is needed to avoid calls of the __ashrdi3 function. */ +static int shr(int val, int shift) { + return val >> shift; +} + +/* Perform the required delay cycles by reading from the appropriate register */ +static void DoC_Delay(struct DiskOnChip *doc, unsigned short cycles) +{ + volatile char dummy; + int i; + + for (i = 0; i < cycles; i++) { + if (DoC_is_Millennium(doc)) + dummy = ReadDOC(doc->virtadr, NOP); + else + dummy = ReadDOC(doc->virtadr, DOCStatus); + } + +} + +/* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */ +static int _DoC_WaitReady(struct DiskOnChip *doc) +{ + unsigned long docptr = doc->virtadr; + unsigned long start = get_timer(0); + +#ifdef PSYCHO_DEBUG + puts ("_DoC_WaitReady called for out-of-line wait\n"); +#endif + + /* Out-of-line routine to wait for chip response */ + while (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { +#ifdef CFG_DOC_SHORT_TIMEOUT + /* it seems that after a certain time the DoC deasserts + * the CDSN_CTRL_FR_B although it is not ready... + * using a short timout solve this (timer increments every ms) */ + if (get_timer(start) > 10) { + return DOC_ETIMEOUT; + } +#else + if (get_timer(start) > 10 * 1000) { + puts ("_DoC_WaitReady timed out.\n"); + return DOC_ETIMEOUT; + } +#endif + udelay(1); + } + + return 0; +} + +static int DoC_WaitReady(struct DiskOnChip *doc) +{ + unsigned long docptr = doc->virtadr; + /* This is inline, to optimise the common case, where it's ready instantly */ + int ret = 0; + + /* 4 read form NOP register should be issued in prior to the read from CDSNControl + see Software Requirement 11.4 item 2. */ + DoC_Delay(doc, 4); + + if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) + /* Call the out-of-line routine to wait */ + ret = _DoC_WaitReady(doc); + + /* issue 2 read from NOP register after reading from CDSNControl register + see Software Requirement 11.4 item 2. */ + DoC_Delay(doc, 2); + + return ret; +} + +/* DoC_Command: Send a flash command to the flash chip through the CDSN Slow IO register to + bypass the internal pipeline. Each of 4 delay cycles (read from the NOP register) is + required after writing to CDSN Control register, see Software Requirement 11.4 item 3. */ + +static inline int DoC_Command(struct DiskOnChip *doc, unsigned char command, + unsigned char xtraflags) +{ + unsigned long docptr = doc->virtadr; + + if (DoC_is_2000(doc)) + xtraflags |= CDSN_CTRL_FLASH_IO; + + /* Assert the CLE (Command Latch Enable) line to the flash chip */ + WriteDOC(xtraflags | CDSN_CTRL_CLE | CDSN_CTRL_CE, docptr, CDSNControl); + DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */ + + if (DoC_is_Millennium(doc)) + WriteDOC(command, docptr, CDSNSlowIO); + + /* Send the command */ + WriteDOC_(command, docptr, doc->ioreg); + + /* Lower the CLE line */ + WriteDOC(xtraflags | CDSN_CTRL_CE, docptr, CDSNControl); + DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */ + + /* Wait for the chip to respond - Software requirement 11.4.1 (extended for any command) */ + return DoC_WaitReady(doc); +} + +/* DoC_Address: Set the current address for the flash chip through the CDSN Slow IO register to + bypass the internal pipeline. Each of 4 delay cycles (read from the NOP register) is + required after writing to CDSN Control register, see Software Requirement 11.4 item 3. */ + +static int DoC_Address(struct DiskOnChip *doc, int numbytes, unsigned long ofs, + unsigned char xtraflags1, unsigned char xtraflags2) +{ + unsigned long docptr; + int i; + + docptr = doc->virtadr; + + if (DoC_is_2000(doc)) + xtraflags1 |= CDSN_CTRL_FLASH_IO; + + /* Assert the ALE (Address Latch Enable) line to the flash chip */ + WriteDOC(xtraflags1 | CDSN_CTRL_ALE | CDSN_CTRL_CE, docptr, CDSNControl); + + DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */ + + /* Send the address */ + /* Devices with 256-byte page are addressed as: + Column (bits 0-7), Page (bits 8-15, 16-23, 24-31) + * there is no device on the market with page256 + and more than 24 bits. + Devices with 512-byte page are addressed as: + Column (bits 0-7), Page (bits 9-16, 17-24, 25-31) + * 25-31 is sent only if the chip support it. + * bit 8 changes the read command to be sent + (NAND_CMD_READ0 or NAND_CMD_READ1). + */ + + if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) { + if (DoC_is_Millennium(doc)) + WriteDOC(ofs & 0xff, docptr, CDSNSlowIO); + WriteDOC_(ofs & 0xff, docptr, doc->ioreg); + } + + if (doc->page256) { + ofs = ofs >> 8; + } else { + ofs = ofs >> 9; + } + + if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) { + for (i = 0; i < doc->pageadrlen; i++, ofs = ofs >> 8) { + if (DoC_is_Millennium(doc)) + WriteDOC(ofs & 0xff, docptr, CDSNSlowIO); + WriteDOC_(ofs & 0xff, docptr, doc->ioreg); + } + } + + DoC_Delay(doc, 2); /* Needed for some slow flash chips. mf. */ + + /* FIXME: The SlowIO's for millennium could be replaced by + a single WritePipeTerm here. mf. */ + + /* Lower the ALE line */ + WriteDOC(xtraflags1 | xtraflags2 | CDSN_CTRL_CE, docptr, + CDSNControl); + + DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */ + + /* Wait for the chip to respond - Software requirement 11.4.1 */ + return DoC_WaitReady(doc); +} + +/* Read a buffer from DoC, taking care of Millennium oddities */ +static void DoC_ReadBuf(struct DiskOnChip *doc, u_char * buf, int len) +{ + volatile int dummy; + int modulus = 0xffff; + unsigned long docptr; + int i; + + docptr = doc->virtadr; + + if (len <= 0) + return; + + if (DoC_is_Millennium(doc)) { + /* Read the data via the internal pipeline through CDSN IO register, + see Pipelined Read Operations 11.3 */ + dummy = ReadDOC(docptr, ReadPipeInit); + + /* Millennium should use the LastDataRead register - Pipeline Reads */ + len--; + + /* This is needed for correctly ECC calculation */ + modulus = 0xff; + } + + for (i = 0; i < len; i++) + buf[i] = ReadDOC_(docptr, doc->ioreg + (i & modulus)); + + if (DoC_is_Millennium(doc)) { + buf[i] = ReadDOC(docptr, LastDataRead); + } +} + +/* Write a buffer to DoC, taking care of Millennium oddities */ +static void DoC_WriteBuf(struct DiskOnChip *doc, const u_char * buf, int len) +{ + unsigned long docptr; + int i; + + docptr = doc->virtadr; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) + WriteDOC_(buf[i], docptr, doc->ioreg + i); + + if (DoC_is_Millennium(doc)) { + WriteDOC(0x00, docptr, WritePipeTerm); + } +} + + +/* DoC_SelectChip: Select a given flash chip within the current floor */ + +static inline int DoC_SelectChip(struct DiskOnChip *doc, int chip) +{ + unsigned long docptr = doc->virtadr; + + /* Software requirement 11.4.4 before writing DeviceSelect */ + /* Deassert the CE line to eliminate glitches on the FCE# outputs */ + WriteDOC(CDSN_CTRL_WP, docptr, CDSNControl); + DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */ + + /* Select the individual flash chip requested */ + WriteDOC(chip, docptr, CDSNDeviceSelect); + DoC_Delay(doc, 4); + + /* Reassert the CE line */ + WriteDOC(CDSN_CTRL_CE | CDSN_CTRL_FLASH_IO | CDSN_CTRL_WP, docptr, + CDSNControl); + DoC_Delay(doc, 4); /* Software requirement 11.4.3 for Millennium */ + + /* Wait for it to be ready */ + return DoC_WaitReady(doc); +} + +/* DoC_SelectFloor: Select a given floor (bank of flash chips) */ + +static inline int DoC_SelectFloor(struct DiskOnChip *doc, int floor) +{ + unsigned long docptr = doc->virtadr; + + /* Select the floor (bank) of chips required */ + WriteDOC(floor, docptr, FloorSelect); + + /* Wait for the chip to be ready */ + return DoC_WaitReady(doc); +} + +/* DoC_IdentChip: Identify a given NAND chip given {floor,chip} */ + +static int DoC_IdentChip(struct DiskOnChip *doc, int floor, int chip) +{ + int mfr, id, i; + volatile char dummy; + + /* Page in the required floor/chip */ + DoC_SelectFloor(doc, floor); + DoC_SelectChip(doc, chip); + + /* Reset the chip */ + if (DoC_Command(doc, NAND_CMD_RESET, CDSN_CTRL_WP)) { +#ifdef DOC_DEBUG + printf("DoC_Command (reset) for %d,%d returned true\n", + floor, chip); +#endif + return 0; + } + + + /* Read the NAND chip ID: 1. Send ReadID command */ + if (DoC_Command(doc, NAND_CMD_READID, CDSN_CTRL_WP)) { +#ifdef DOC_DEBUG + printf("DoC_Command (ReadID) for %d,%d returned true\n", + floor, chip); +#endif + return 0; + } + + /* Read the NAND chip ID: 2. Send address byte zero */ + DoC_Address(doc, ADDR_COLUMN, 0, CDSN_CTRL_WP, 0); + + /* Read the manufacturer and device id codes from the device */ + + /* CDSN Slow IO register see Software Requirement 11.4 item 5. */ + dummy = ReadDOC(doc->virtadr, CDSNSlowIO); + DoC_Delay(doc, 2); + mfr = ReadDOC_(doc->virtadr, doc->ioreg); + + /* CDSN Slow IO register see Software Requirement 11.4 item 5. */ + dummy = ReadDOC(doc->virtadr, CDSNSlowIO); + DoC_Delay(doc, 2); + id = ReadDOC_(doc->virtadr, doc->ioreg); + + /* No response - return failure */ + if (mfr == 0xff || mfr == 0) + return 0; + + /* Check it's the same as the first chip we identified. + * M-Systems say that any given DiskOnChip device should only + * contain _one_ type of flash part, although that's not a + * hardware restriction. */ + if (doc->mfr) { + if (doc->mfr == mfr && doc->id == id) + return 1; /* This is another the same the first */ + else + printf("Flash chip at floor %d, chip %d is different:\n", + floor, chip); + } + + /* Print and store the manufacturer and ID codes. */ + for (i = 0; nand_flash_ids[i].name != NULL; i++) { + if (mfr == nand_flash_ids[i].manufacture_id && + id == nand_flash_ids[i].model_id) { +#ifdef DOC_DEBUG + printf("Flash chip found: Manufacturer ID: %2.2X, " + "Chip ID: %2.2X (%s)\n", mfr, id, + nand_flash_ids[i].name); +#endif + if (!doc->mfr) { + doc->mfr = mfr; + doc->id = id; + doc->chipshift = + nand_flash_ids[i].chipshift; + doc->page256 = nand_flash_ids[i].page256; + doc->pageadrlen = + nand_flash_ids[i].pageadrlen; + doc->erasesize = + nand_flash_ids[i].erasesize; + doc->chips_name = + nand_flash_ids[i].name; + return 1; + } + return 0; + } + } + + +#ifdef DOC_DEBUG + /* We haven't fully identified the chip. Print as much as we know. */ + printf("Unknown flash chip found: %2.2X %2.2X\n", + id, mfr); +#endif + + return 0; +} + +/* DoC_ScanChips: Find all NAND chips present in a DiskOnChip, and identify them */ + +static void DoC_ScanChips(struct DiskOnChip *this) +{ + int floor, chip; + int numchips[MAX_FLOORS]; + int maxchips = MAX_CHIPS; + int ret = 1; + + this->numchips = 0; + this->mfr = 0; + this->id = 0; + + if (DoC_is_Millennium(this)) + maxchips = MAX_CHIPS_MIL; + + /* For each floor, find the number of valid chips it contains */ + for (floor = 0; floor < MAX_FLOORS; floor++) { + ret = 1; + numchips[floor] = 0; + for (chip = 0; chip < maxchips && ret != 0; chip++) { + + ret = DoC_IdentChip(this, floor, chip); + if (ret) { + numchips[floor]++; + this->numchips++; + } + } + } + + /* If there are none at all that we recognise, bail */ + if (!this->numchips) { + puts ("No flash chips recognised.\n"); + return; + } + + /* Allocate an array to hold the information for each chip */ + this->chips = malloc(sizeof(struct Nand) * this->numchips); + if (!this->chips) { + puts ("No memory for allocating chip info structures\n"); + return; + } + + ret = 0; + + /* Fill out the chip array with {floor, chipno} for each + * detected chip in the device. */ + for (floor = 0; floor < MAX_FLOORS; floor++) { + for (chip = 0; chip < numchips[floor]; chip++) { + this->chips[ret].floor = floor; + this->chips[ret].chip = chip; + this->chips[ret].curadr = 0; + this->chips[ret].curmode = 0x50; + ret++; + } + } + + /* Calculate and print the total size of the device */ + this->totlen = this->numchips * (1 << this->chipshift); + +#ifdef DOC_DEBUG + printf("%d flash chips found. Total DiskOnChip size: %ld MB\n", + this->numchips, this->totlen >> 20); +#endif +} + +/* find_boot_record: Find the NFTL Media Header and its Spare copy which contains the + * various device information of the NFTL partition and Bad Unit Table. Update + * the ReplUnitTable[] table accroding to the Bad Unit Table. ReplUnitTable[] + * is used for management of Erase Unit in other routines in nftl.c and nftlmount.c + */ +static int find_boot_record(struct NFTLrecord *nftl) +{ + struct nftl_uci1 h1; + struct nftl_oob oob; + unsigned int block, boot_record_count = 0; + int retlen; + u8 buf[SECTORSIZE]; + struct NFTLMediaHeader *mh = &nftl->MediaHdr; + unsigned int i; + + nftl->MediaUnit = BLOCK_NIL; + nftl->SpareMediaUnit = BLOCK_NIL; + + /* search for a valid boot record */ + for (block = 0; block < nftl->nb_blocks; block++) { + int ret; + + /* Check for ANAND header first. Then can whinge if it's found but later + checks fail */ + if ((ret = doc_read_ecc(nftl->mtd, block * nftl->EraseSize, SECTORSIZE, + (size_t *)&retlen, buf, NULL))) { + static int warncount = 5; + + if (warncount) { + printf("Block read at 0x%x failed\n", block * nftl->EraseSize); + if (!--warncount) + puts ("Further failures for this block will not be printed\n"); + } + continue; + } + + if (retlen < 6 || memcmp(buf, "ANAND", 6)) { + /* ANAND\0 not found. Continue */ +#ifdef PSYCHO_DEBUG + printf("ANAND header not found at 0x%x\n", block * nftl->EraseSize); +#endif + continue; + } + +#ifdef NFTL_DEBUG + printf("ANAND header found at 0x%x\n", block * nftl->EraseSize); +#endif + + /* To be safer with BIOS, also use erase mark as discriminant */ + if ((ret = doc_read_oob(nftl->mtd, block * nftl->EraseSize + SECTORSIZE + 8, + 8, (size_t *)&retlen, (uchar *)&h1) < 0)) { +#ifdef NFTL_DEBUG + printf("ANAND header found at 0x%x, but OOB data read failed\n", + block * nftl->EraseSize); +#endif + continue; + } + + /* OK, we like it. */ + + if (boot_record_count) { + /* We've already processed one. So we just check if + this one is the same as the first one we found */ + if (memcmp(mh, buf, sizeof(struct NFTLMediaHeader))) { +#ifdef NFTL_DEBUG + printf("NFTL Media Headers at 0x%x and 0x%x disagree.\n", + nftl->MediaUnit * nftl->EraseSize, block * nftl->EraseSize); +#endif + /* if (debug) Print both side by side */ + return -1; + } + if (boot_record_count == 1) + nftl->SpareMediaUnit = block; + + boot_record_count++; + continue; + } + + /* This is the first we've seen. Copy the media header structure into place */ + memcpy(mh, buf, sizeof(struct NFTLMediaHeader)); + + /* Do some sanity checks on it */ + if (mh->UnitSizeFactor == 0) { +#ifdef NFTL_DEBUG + puts ("UnitSizeFactor 0x00 detected.\n" + "This violates the spec but we think we know what it means...\n"); +#endif + } else if (mh->UnitSizeFactor != 0xff) { + printf ("Sorry, we don't support UnitSizeFactor " + "of != 1 yet.\n"); + return -1; + } + + nftl->nb_boot_blocks = le16_to_cpu(mh->FirstPhysicalEUN); + if ((nftl->nb_boot_blocks + 2) >= nftl->nb_blocks) { + printf ("NFTL Media Header sanity check failed:\n" + "nb_boot_blocks (%d) + 2 > nb_blocks (%d)\n", + nftl->nb_boot_blocks, nftl->nb_blocks); + return -1; + } + + nftl->numvunits = le32_to_cpu(mh->FormattedSize) / nftl->EraseSize; + if (nftl->numvunits > (nftl->nb_blocks - nftl->nb_boot_blocks - 2)) { + printf ("NFTL Media Header sanity check failed:\n" + "numvunits (%d) > nb_blocks (%d) - nb_boot_blocks(%d) - 2\n", + nftl->numvunits, + nftl->nb_blocks, + nftl->nb_boot_blocks); + return -1; + } + + nftl->nr_sects = nftl->numvunits * (nftl->EraseSize / SECTORSIZE); + + /* If we're not using the last sectors in the device for some reason, + reduce nb_blocks accordingly so we forget they're there */ + nftl->nb_blocks = le16_to_cpu(mh->NumEraseUnits) + le16_to_cpu(mh->FirstPhysicalEUN); + + /* read the Bad Erase Unit Table and modify ReplUnitTable[] accordingly */ + for (i = 0; i < nftl->nb_blocks; i++) { + if ((i & (SECTORSIZE - 1)) == 0) { + /* read one sector for every SECTORSIZE of blocks */ + if ((ret = doc_read_ecc(nftl->mtd, block * nftl->EraseSize + + i + SECTORSIZE, SECTORSIZE, + (size_t *)&retlen, buf, (uchar *)&oob)) < 0) { + puts ("Read of bad sector table failed\n"); + return -1; + } + } + /* mark the Bad Erase Unit as RESERVED in ReplUnitTable */ + if (buf[i & (SECTORSIZE - 1)] != 0xff) + nftl->ReplUnitTable[i] = BLOCK_RESERVED; + } + + nftl->MediaUnit = block; + boot_record_count++; + + } /* foreach (block) */ + + return boot_record_count?0:-1; +} + +/* This routine is made available to other mtd code via + * inter_module_register. It must only be accessed through + * inter_module_get which will bump the use count of this module. The + * addresses passed back in mtd are valid as long as the use count of + * this module is non-zero, i.e. between inter_module_get and + * inter_module_put. Keith Owens 29 Oct 2000. + */ +static void DoC2k_init(struct DiskOnChip* this) +{ + struct NFTLrecord *nftl; + + switch (this->ChipID) { + case DOC_ChipID_Doc2k: + this->name = "DiskOnChip 2000"; + this->ioreg = DoC_2k_CDSN_IO; + break; + case DOC_ChipID_DocMil: + this->name = "DiskOnChip Millennium"; + this->ioreg = DoC_Mil_CDSN_IO; + break; + } + +#ifdef DOC_DEBUG + printf("%s found at address 0x%lX\n", this->name, + this->physadr); +#endif + + this->totlen = 0; + this->numchips = 0; + + this->curfloor = -1; + this->curchip = -1; + + /* Ident all the chips present. */ + DoC_ScanChips(this); + if ((!this->numchips) || (!this->chips)) + return; + + nftl = &this->nftl; + + /* Get physical parameters */ + nftl->EraseSize = this->erasesize; + nftl->nb_blocks = this->totlen / this->erasesize; + nftl->mtd = this; + + if (find_boot_record(nftl) != 0) + this->nftl_found = 0; + else + this->nftl_found = 1; + + printf("%s @ 0x%lX, %ld MB\n", this->name, this->physadr, this->totlen >> 20); +} + +int doc_read_ecc(struct DiskOnChip* this, loff_t from, size_t len, + size_t * retlen, u_char * buf, u_char * eccbuf) +{ + unsigned long docptr; + struct Nand *mychip; + unsigned char syndrome[6]; + volatile char dummy; + int i, len256 = 0, ret=0; + + docptr = this->virtadr; + + /* Don't allow read past end of device */ + if (from >= this->totlen) { + puts ("Out of flash\n"); + return DOC_EINVAL; + } + + /* Don't allow a single read to cross a 512-byte block boundary */ + if (from + len > ((from | 0x1ff) + 1)) + len = ((from | 0x1ff) + 1) - from; + + /* The ECC will not be calculated correctly if less than 512 is read */ + if (len != 0x200 && eccbuf) + printf("ECC needs a full sector read (adr: %lx size %lx)\n", + (long) from, (long) len); + +#ifdef PSYCHO_DEBUG + printf("DoC_Read (adr: %lx size %lx)\n", (long) from, (long) len); +#endif + + /* Find the chip which is to be used and select it */ + mychip = &this->chips[shr(from, this->chipshift)]; + + if (this->curfloor != mychip->floor) { + DoC_SelectFloor(this, mychip->floor); + DoC_SelectChip(this, mychip->chip); + } else if (this->curchip != mychip->chip) { + DoC_SelectChip(this, mychip->chip); + } + + this->curfloor = mychip->floor; + this->curchip = mychip->chip; + + DoC_Command(this, + (!this->page256 + && (from & 0x100)) ? NAND_CMD_READ1 : NAND_CMD_READ0, + CDSN_CTRL_WP); + DoC_Address(this, ADDR_COLUMN_PAGE, from, CDSN_CTRL_WP, + CDSN_CTRL_ECC_IO); + + if (eccbuf) { + /* Prime the ECC engine */ + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_EN, docptr, ECCConf); + } else { + /* disable the ECC engine */ + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_DIS, docptr, ECCConf); + } + + /* treat crossing 256-byte sector for 2M x 8bits devices */ + if (this->page256 && from + len > (from | 0xff) + 1) { + len256 = (from | 0xff) + 1 - from; + DoC_ReadBuf(this, buf, len256); + + DoC_Command(this, NAND_CMD_READ0, CDSN_CTRL_WP); + DoC_Address(this, ADDR_COLUMN_PAGE, from + len256, + CDSN_CTRL_WP, CDSN_CTRL_ECC_IO); + } + + DoC_ReadBuf(this, &buf[len256], len - len256); + + /* Let the caller know we completed it */ + *retlen = len; + + if (eccbuf) { + /* Read the ECC data through the DiskOnChip ECC logic */ + /* Note: this will work even with 2M x 8bit devices as */ + /* they have 8 bytes of OOB per 256 page. mf. */ + DoC_ReadBuf(this, eccbuf, 6); + + /* Flush the pipeline */ + if (DoC_is_Millennium(this)) { + dummy = ReadDOC(docptr, ECCConf); + dummy = ReadDOC(docptr, ECCConf); + i = ReadDOC(docptr, ECCConf); + } else { + dummy = ReadDOC(docptr, 2k_ECCStatus); + dummy = ReadDOC(docptr, 2k_ECCStatus); + i = ReadDOC(docptr, 2k_ECCStatus); + } + + /* Check the ECC Status */ + if (i & 0x80) { + int nb_errors; + /* There was an ECC error */ +#ifdef ECC_DEBUG + printf("DiskOnChip ECC Error: Read at %lx\n", (long)from); +#endif + /* Read the ECC syndrom through the DiskOnChip ECC logic. + These syndrome will be all ZERO when there is no error */ + for (i = 0; i < 6; i++) { + syndrome[i] = + ReadDOC(docptr, ECCSyndrome0 + i); + } + nb_errors = doc_decode_ecc(buf, syndrome); + +#ifdef ECC_DEBUG + printf("Errors corrected: %x\n", nb_errors); +#endif + if (nb_errors < 0) { + /* We return error, but have actually done the read. Not that + this can be told to user-space, via sys_read(), but at least + MTD-aware stuff can know about it by checking *retlen */ + printf("ECC Errors at %lx\n", (long)from); + ret = DOC_EECC; + } + } + +#ifdef PSYCHO_DEBUG + printf("ECC DATA at %lxB: %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X\n", + (long)from, eccbuf[0], eccbuf[1], eccbuf[2], + eccbuf[3], eccbuf[4], eccbuf[5]); +#endif + + /* disable the ECC engine */ + WriteDOC(DOC_ECC_DIS, docptr , ECCConf); + } + + /* according to 11.4.1, we need to wait for the busy line + * drop if we read to the end of the page. */ + if(0 == ((from + *retlen) & 0x1ff)) + { + DoC_WaitReady(this); + } + + return ret; +} + +int doc_write_ecc(struct DiskOnChip* this, loff_t to, size_t len, + size_t * retlen, const u_char * buf, + u_char * eccbuf) +{ + int di; /* Yes, DI is a hangover from when I was disassembling the binary driver */ + unsigned long docptr; + volatile char dummy; + int len256 = 0; + struct Nand *mychip; + + docptr = this->virtadr; + + /* Don't allow write past end of device */ + if (to >= this->totlen) { + puts ("Out of flash\n"); + return DOC_EINVAL; + } + + /* Don't allow a single write to cross a 512-byte block boundary */ + if (to + len > ((to | 0x1ff) + 1)) + len = ((to | 0x1ff) + 1) - to; + + /* The ECC will not be calculated correctly if less than 512 is written */ + if (len != 0x200 && eccbuf) + printf("ECC needs a full sector write (adr: %lx size %lx)\n", + (long) to, (long) len); + + /* printf("DoC_Write (adr: %lx size %lx)\n", (long) to, (long) len); */ + + /* Find the chip which is to be used and select it */ + mychip = &this->chips[shr(to, this->chipshift)]; + + if (this->curfloor != mychip->floor) { + DoC_SelectFloor(this, mychip->floor); + DoC_SelectChip(this, mychip->chip); + } else if (this->curchip != mychip->chip) { + DoC_SelectChip(this, mychip->chip); + } + + this->curfloor = mychip->floor; + this->curchip = mychip->chip; + + /* Set device to main plane of flash */ + DoC_Command(this, NAND_CMD_RESET, CDSN_CTRL_WP); + DoC_Command(this, + (!this->page256 + && (to & 0x100)) ? NAND_CMD_READ1 : NAND_CMD_READ0, + CDSN_CTRL_WP); + + DoC_Command(this, NAND_CMD_SEQIN, 0); + DoC_Address(this, ADDR_COLUMN_PAGE, to, 0, CDSN_CTRL_ECC_IO); + + if (eccbuf) { + /* Prime the ECC engine */ + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, ECCConf); + } else { + /* disable the ECC engine */ + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_DIS, docptr, ECCConf); + } + + /* treat crossing 256-byte sector for 2M x 8bits devices */ + if (this->page256 && to + len > (to | 0xff) + 1) { + len256 = (to | 0xff) + 1 - to; + DoC_WriteBuf(this, buf, len256); + + DoC_Command(this, NAND_CMD_PAGEPROG, 0); + + DoC_Command(this, NAND_CMD_STATUS, CDSN_CTRL_WP); + /* There's an implicit DoC_WaitReady() in DoC_Command */ + + dummy = ReadDOC(docptr, CDSNSlowIO); + DoC_Delay(this, 2); + + if (ReadDOC_(docptr, this->ioreg) & 1) { + puts ("Error programming flash\n"); + /* Error in programming */ + *retlen = 0; + return DOC_EIO; + } + + DoC_Command(this, NAND_CMD_SEQIN, 0); + DoC_Address(this, ADDR_COLUMN_PAGE, to + len256, 0, + CDSN_CTRL_ECC_IO); + } + + DoC_WriteBuf(this, &buf[len256], len - len256); + + if (eccbuf) { + WriteDOC(CDSN_CTRL_ECC_IO | CDSN_CTRL_CE, docptr, + CDSNControl); + + if (DoC_is_Millennium(this)) { + WriteDOC(0, docptr, NOP); + WriteDOC(0, docptr, NOP); + WriteDOC(0, docptr, NOP); + } else { + WriteDOC_(0, docptr, this->ioreg); + WriteDOC_(0, docptr, this->ioreg); + WriteDOC_(0, docptr, this->ioreg); + } + + /* Read the ECC data through the DiskOnChip ECC logic */ + for (di = 0; di < 6; di++) { + eccbuf[di] = ReadDOC(docptr, ECCSyndrome0 + di); + } + + /* Reset the ECC engine */ + WriteDOC(DOC_ECC_DIS, docptr, ECCConf); + +#ifdef PSYCHO_DEBUG + printf + ("OOB data at %lx is %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X\n", + (long) to, eccbuf[0], eccbuf[1], eccbuf[2], eccbuf[3], + eccbuf[4], eccbuf[5]); +#endif + } + + DoC_Command(this, NAND_CMD_PAGEPROG, 0); + + DoC_Command(this, NAND_CMD_STATUS, CDSN_CTRL_WP); + /* There's an implicit DoC_WaitReady() in DoC_Command */ + + dummy = ReadDOC(docptr, CDSNSlowIO); + DoC_Delay(this, 2); + + if (ReadDOC_(docptr, this->ioreg) & 1) { + puts ("Error programming flash\n"); + /* Error in programming */ + *retlen = 0; + return DOC_EIO; + } + + /* Let the caller know we completed it */ + *retlen = len; + + if (eccbuf) { + unsigned char x[8]; + size_t dummy; + int ret; + + /* Write the ECC data to flash */ + for (di=0; di<6; di++) + x[di] = eccbuf[di]; + + x[6]=0x55; + x[7]=0x55; + + ret = doc_write_oob(this, to, 8, &dummy, x); + return ret; + } + return 0; +} + +int doc_read_oob(struct DiskOnChip* this, loff_t ofs, size_t len, + size_t * retlen, u_char * buf) +{ + int len256 = 0, ret; + unsigned long docptr; + struct Nand *mychip; + + docptr = this->virtadr; + + mychip = &this->chips[shr(ofs, this->chipshift)]; + + if (this->curfloor != mychip->floor) { + DoC_SelectFloor(this, mychip->floor); + DoC_SelectChip(this, mychip->chip); + } else if (this->curchip != mychip->chip) { + DoC_SelectChip(this, mychip->chip); + } + this->curfloor = mychip->floor; + this->curchip = mychip->chip; + + /* update address for 2M x 8bit devices. OOB starts on the second */ + /* page to maintain compatibility with doc_read_ecc. */ + if (this->page256) { + if (!(ofs & 0x8)) + ofs += 0x100; + else + ofs -= 0x8; + } + + DoC_Command(this, NAND_CMD_READOOB, CDSN_CTRL_WP); + DoC_Address(this, ADDR_COLUMN_PAGE, ofs, CDSN_CTRL_WP, 0); + + /* treat crossing 8-byte OOB data for 2M x 8bit devices */ + /* Note: datasheet says it should automaticaly wrap to the */ + /* next OOB block, but it didn't work here. mf. */ + if (this->page256 && ofs + len > (ofs | 0x7) + 1) { + len256 = (ofs | 0x7) + 1 - ofs; + DoC_ReadBuf(this, buf, len256); + + DoC_Command(this, NAND_CMD_READOOB, CDSN_CTRL_WP); + DoC_Address(this, ADDR_COLUMN_PAGE, ofs & (~0x1ff), + CDSN_CTRL_WP, 0); + } + + DoC_ReadBuf(this, &buf[len256], len - len256); + + *retlen = len; + /* Reading the full OOB data drops us off of the end of the page, + * causing the flash device to go into busy mode, so we need + * to wait until ready 11.4.1 and Toshiba TC58256FT docs */ + + ret = DoC_WaitReady(this); + + return ret; + +} + +int doc_write_oob(struct DiskOnChip* this, loff_t ofs, size_t len, + size_t * retlen, const u_char * buf) +{ + int len256 = 0; + unsigned long docptr = this->virtadr; + struct Nand *mychip = &this->chips[shr(ofs, this->chipshift)]; + volatile int dummy; + +#ifdef PSYCHO_DEBUG + printf("doc_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n", + (long)ofs, len, buf[0], buf[1], buf[2], buf[3], + buf[8], buf[9], buf[14],buf[15]); +#endif + + /* Find the chip which is to be used and select it */ + if (this->curfloor != mychip->floor) { + DoC_SelectFloor(this, mychip->floor); + DoC_SelectChip(this, mychip->chip); + } else if (this->curchip != mychip->chip) { + DoC_SelectChip(this, mychip->chip); + } + this->curfloor = mychip->floor; + this->curchip = mychip->chip; + + /* disable the ECC engine */ + WriteDOC (DOC_ECC_RESET, docptr, ECCConf); + WriteDOC (DOC_ECC_DIS, docptr, ECCConf); + + /* Reset the chip, see Software Requirement 11.4 item 1. */ + DoC_Command(this, NAND_CMD_RESET, CDSN_CTRL_WP); + + /* issue the Read2 command to set the pointer to the Spare Data Area. */ + DoC_Command(this, NAND_CMD_READOOB, CDSN_CTRL_WP); + + /* update address for 2M x 8bit devices. OOB starts on the second */ + /* page to maintain compatibility with doc_read_ecc. */ + if (this->page256) { + if (!(ofs & 0x8)) + ofs += 0x100; + else + ofs -= 0x8; + } + + /* issue the Serial Data In command to initial the Page Program process */ + DoC_Command(this, NAND_CMD_SEQIN, 0); + DoC_Address(this, ADDR_COLUMN_PAGE, ofs, 0, 0); + + /* treat crossing 8-byte OOB data for 2M x 8bit devices */ + /* Note: datasheet says it should automaticaly wrap to the */ + /* next OOB block, but it didn't work here. mf. */ + if (this->page256 && ofs + len > (ofs | 0x7) + 1) { + len256 = (ofs | 0x7) + 1 - ofs; + DoC_WriteBuf(this, buf, len256); + + DoC_Command(this, NAND_CMD_PAGEPROG, 0); + DoC_Command(this, NAND_CMD_STATUS, 0); + /* DoC_WaitReady() is implicit in DoC_Command */ + + dummy = ReadDOC(docptr, CDSNSlowIO); + DoC_Delay(this, 2); + + if (ReadDOC_(docptr, this->ioreg) & 1) { + puts ("Error programming oob data\n"); + /* There was an error */ + *retlen = 0; + return DOC_EIO; + } + DoC_Command(this, NAND_CMD_SEQIN, 0); + DoC_Address(this, ADDR_COLUMN_PAGE, ofs & (~0x1ff), 0, 0); + } + + DoC_WriteBuf(this, &buf[len256], len - len256); + + DoC_Command(this, NAND_CMD_PAGEPROG, 0); + DoC_Command(this, NAND_CMD_STATUS, 0); + /* DoC_WaitReady() is implicit in DoC_Command */ + + dummy = ReadDOC(docptr, CDSNSlowIO); + DoC_Delay(this, 2); + + if (ReadDOC_(docptr, this->ioreg) & 1) { + puts ("Error programming oob data\n"); + /* There was an error */ + *retlen = 0; + return DOC_EIO; + } + + *retlen = len; + return 0; + +} + +int doc_erase(struct DiskOnChip* this, loff_t ofs, size_t len) +{ + volatile int dummy; + unsigned long docptr; + struct Nand *mychip; + + if (ofs & (this->erasesize-1) || len & (this->erasesize-1)) { + puts ("Offset and size must be sector aligned\n"); + return DOC_EINVAL; + } + + docptr = this->virtadr; + + /* FIXME: Do this in the background. Use timers or schedule_task() */ + while(len) { + mychip = &this->chips[shr(ofs, this->chipshift)]; + + if (this->curfloor != mychip->floor) { + DoC_SelectFloor(this, mychip->floor); + DoC_SelectChip(this, mychip->chip); + } else if (this->curchip != mychip->chip) { + DoC_SelectChip(this, mychip->chip); + } + this->curfloor = mychip->floor; + this->curchip = mychip->chip; + + DoC_Command(this, NAND_CMD_ERASE1, 0); + DoC_Address(this, ADDR_PAGE, ofs, 0, 0); + DoC_Command(this, NAND_CMD_ERASE2, 0); + + DoC_Command(this, NAND_CMD_STATUS, CDSN_CTRL_WP); + + dummy = ReadDOC(docptr, CDSNSlowIO); + DoC_Delay(this, 2); + + if (ReadDOC_(docptr, this->ioreg) & 1) { + printf("Error erasing at 0x%lx\n", (long)ofs); + /* There was an error */ + goto callback; + } + ofs += this->erasesize; + len -= this->erasesize; + } + + callback: + return 0; +} + +static inline int doccheck(unsigned long potential, unsigned long physadr) +{ + unsigned long window=potential; + unsigned char tmp, ChipID; +#ifndef DOC_PASSIVE_PROBE + unsigned char tmp2; +#endif + + /* Routine copied from the Linux DOC driver */ + +#ifdef CFG_DOCPROBE_55AA + /* Check for 0x55 0xAA signature at beginning of window, + this is no longer true once we remove the IPL (for Millennium */ + if (ReadDOC(window, Sig1) != 0x55 || ReadDOC(window, Sig2) != 0xaa) + return 0; +#endif /* CFG_DOCPROBE_55AA */ + +#ifndef DOC_PASSIVE_PROBE + /* It's not possible to cleanly detect the DiskOnChip - the + * bootup procedure will put the device into reset mode, and + * it's not possible to talk to it without actually writing + * to the DOCControl register. So we store the current contents + * of the DOCControl register's location, in case we later decide + * that it's not a DiskOnChip, and want to put it back how we + * found it. + */ + tmp2 = ReadDOC(window, DOCControl); + + /* Reset the DiskOnChip ASIC */ + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, + window, DOCControl); + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, + window, DOCControl); + + /* Enable the DiskOnChip ASIC */ + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, + window, DOCControl); + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, + window, DOCControl); +#endif /* !DOC_PASSIVE_PROBE */ + + ChipID = ReadDOC(window, ChipID); + + switch (ChipID) { + case DOC_ChipID_Doc2k: + /* Check the TOGGLE bit in the ECC register */ + tmp = ReadDOC(window, 2k_ECCStatus) & DOC_TOGGLE_BIT; + if ((ReadDOC(window, 2k_ECCStatus) & DOC_TOGGLE_BIT) != tmp) + return ChipID; + break; + + case DOC_ChipID_DocMil: + /* Check the TOGGLE bit in the ECC register */ + tmp = ReadDOC(window, ECCConf) & DOC_TOGGLE_BIT; + if ((ReadDOC(window, ECCConf) & DOC_TOGGLE_BIT) != tmp) + return ChipID; + break; + + default: +#ifndef CFG_DOCPROBE_55AA +/* + * if the ID isn't the DoC2000 or DoCMillenium ID, so we can assume + * the DOC is missing + */ +# if 0 + printf("Possible DiskOnChip with unknown ChipID %2.2X found at 0x%lx\n", + ChipID, physadr); +# endif +#endif +#ifndef DOC_PASSIVE_PROBE + /* Put back the contents of the DOCControl register, in case it's not + * actually a DiskOnChip. + */ + WriteDOC(tmp2, window, DOCControl); +#endif + return 0; + } + + puts ("DiskOnChip failed TOGGLE test, dropping.\n"); + +#ifndef DOC_PASSIVE_PROBE + /* Put back the contents of the DOCControl register: it's not a DiskOnChip */ + WriteDOC(tmp2, window, DOCControl); +#endif + return 0; +} + +void doc_probe(unsigned long physadr) +{ + struct DiskOnChip *this = NULL; + int i=0, ChipID; + + if ((ChipID = doccheck(physadr, physadr))) { + + for (i=0; ivirtadr = physadr; + this->physadr = physadr; + this->ChipID = ChipID; + + DoC2k_init(this); + } else { + puts ("No DiskOnChip found\n"); + } +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_DOC) */ diff --git a/common/cmd_dtt.c b/common/cmd_dtt.c new file mode 100644 index 0000000..9db64e9 --- /dev/null +++ b/common/cmd_dtt.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_DTT) + +#include + +int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + + /* + * Loop through sensors, read + * temperature, and output it. + */ + for (i = 0; i < sizeof (sensors); i++) { + printf ("DTT%d: %i C\n", i + 1, dtt_get_temp (sensors[i])); + } + + return 0; +} /* do_dtt() */ + +/***************************************************/ + +U_BOOT_CMD( + dtt, 1, 1, do_dtt, + "dtt - Digital Thermometer and Themostat\n", + " - Read temperature from digital thermometer and thermostat.\n" +); + +#endif /* CONFIG_COMMANDS & CFG_CMD_DTT */ diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c new file mode 100644 index 0000000..d15a412 --- /dev/null +++ b/common/cmd_eeprom.c @@ -0,0 +1,448 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Support for read and write access to EEPROM like memory devices. This + * includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM). + * FRAM devices read and write data at bus speed. In particular, there is no + * write delay. Also, there is no limit imposed on the numer of bytes that can + * be transferred with a single read or write. + * + * Use the following configuration options to ensure no unneeded performance + * degradation (typical for EEPROM) is incured for FRAM memory: + * + * #define CFG_I2C_FRAM + * #undef CFG_EEPROM_PAGE_WRITE_DELAY_MS + * + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM) + +extern void eeprom_init (void); +extern int eeprom_read (unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt); +extern int eeprom_write (unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt); +#if defined(CFG_EEPROM_WREN) +extern int eeprom_write_enable (unsigned dev_addr, int state); +#endif +#endif + + +#if defined(CFG_EEPROM_X40430) + /* Maximum number of times to poll for acknowledge after write */ +#define MAX_ACKNOWLEDGE_POLLS 10 +#endif + +/* ------------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) +int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + const char *const fmt = + "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... "; + +#if defined(CFG_I2C_MULTI_EEPROMS) + if (argc == 6) { + ulong dev_addr = simple_strtoul (argv[2], NULL, 16); + ulong addr = simple_strtoul (argv[3], NULL, 16); + ulong off = simple_strtoul (argv[4], NULL, 16); + ulong cnt = simple_strtoul (argv[5], NULL, 16); +#else + if (argc == 5) { + ulong dev_addr = CFG_DEF_EEPROM_ADDR; + ulong addr = simple_strtoul (argv[2], NULL, 16); + ulong off = simple_strtoul (argv[3], NULL, 16); + ulong cnt = simple_strtoul (argv[4], NULL, 16); +#endif /* CFG_I2C_MULTI_EEPROMS */ + +# ifndef CONFIG_SPI + eeprom_init (); +# endif /* !CONFIG_SPI */ + + if (strcmp (argv[1], "read") == 0) { + int rcode; + + printf (fmt, dev_addr, argv[1], addr, off, cnt); + + rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt); + + puts ("done\n"); + return rcode; + } else if (strcmp (argv[1], "write") == 0) { + int rcode; + + printf (fmt, dev_addr, argv[1], addr, off, cnt); + + rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt); + + puts ("done\n"); + return rcode; + } + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} +#endif /* CFG_CMD_EEPROM */ + +/*----------------------------------------------------------------------- + * + * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is + * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. + * + * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is + * 0x00000nxx for EEPROM address selectors and page number at n. + */ + +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM) + +#ifndef CONFIG_SPI +#if !defined(CFG_I2C_EEPROM_ADDR_LEN) || CFG_I2C_EEPROM_ADDR_LEN < 1 || CFG_I2C_EEPROM_ADDR_LEN > 2 +#error CFG_I2C_EEPROM_ADDR_LEN must be 1 or 2 +#endif +#endif + +int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +{ + unsigned end = offset + cnt; + unsigned blk_off; + int rcode = 0; + + /* Read data until done or would cross a page boundary. + * We must write the address again when changing pages + * because the next page may be in a different device. + */ + while (offset < end) { + unsigned alen, len; +#if !defined(CFG_I2C_FRAM) + unsigned maxlen; +#endif + +#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) + uchar addr[2]; + + blk_off = offset & 0xFF; /* block offset */ + + addr[0] = offset >> 8; /* block number */ + addr[1] = blk_off; /* block offset */ + alen = 2; +#else + uchar addr[3]; + + blk_off = offset & 0xFF; /* block offset */ + + addr[0] = offset >> 16; /* block number */ + addr[1] = offset >> 8; /* upper address octet */ + addr[2] = blk_off; /* lower address octet */ + alen = 3; +#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ + + addr[0] |= dev_addr; /* insert device address */ + + len = end - offset; + + /* + * For a FRAM device there is no limit on the number of the + * bytes that can be ccessed with the single read or write + * operation. + */ +#if !defined(CFG_I2C_FRAM) + maxlen = 0x100 - blk_off; + if (maxlen > I2C_RXTX_LEN) + maxlen = I2C_RXTX_LEN; + if (len > maxlen) + len = maxlen; +#endif + +#ifdef CONFIG_SPI + spi_read (addr, alen, buffer, len); +#else + if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0) + rcode = 1; +#endif + buffer += len; + offset += len; + } + + return rcode; +} + +/*----------------------------------------------------------------------- + * + * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is + * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. + * + * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is + * 0x00000nxx for EEPROM address selectors and page number at n. + */ + +int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +{ + unsigned end = offset + cnt; + unsigned blk_off; + int rcode = 0; + +#if defined(CFG_EEPROM_X40430) + uchar contr_r_addr[2]; + uchar addr_void[2]; + uchar contr_reg[2]; + uchar ctrl_reg_v; + int i; +#endif + +#if defined(CFG_EEPROM_WREN) + eeprom_write_enable (dev_addr,1); +#endif + /* Write data until done or would cross a write page boundary. + * We must write the address again when changing pages + * because the address counter only increments within a page. + */ + + while (offset < end) { + unsigned alen, len; +#if !defined(CFG_I2C_FRAM) + unsigned maxlen; +#endif + +#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) + uchar addr[2]; + + blk_off = offset & 0xFF; /* block offset */ + + addr[0] = offset >> 8; /* block number */ + addr[1] = blk_off; /* block offset */ + alen = 2; +#else + uchar addr[3]; + + blk_off = offset & 0xFF; /* block offset */ + + addr[0] = offset >> 16; /* block number */ + addr[1] = offset >> 8; /* upper address octet */ + addr[2] = blk_off; /* lower address octet */ + alen = 3; +#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ + + addr[0] |= dev_addr; /* insert device address */ + + len = end - offset; + + /* + * For a FRAM device there is no limit on the number of the + * bytes that can be ccessed with the single read or write + * operation. + */ +#if !defined(CFG_I2C_FRAM) + +#if defined(CFG_EEPROM_PAGE_WRITE_BITS) + +#define EEPROM_PAGE_SIZE (1 << CFG_EEPROM_PAGE_WRITE_BITS) +#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1)) + + maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off); +#else + maxlen = 0x100 - blk_off; +#endif + if (maxlen > I2C_RXTX_LEN) + maxlen = I2C_RXTX_LEN; + + if (len > maxlen) + len = maxlen; +#endif + +#ifdef CONFIG_SPI + spi_write (addr, alen, buffer, len); +#else +#if defined(CFG_EEPROM_X40430) + /* Get the value of the control register. + * Set current address (internal pointer in the x40430) + * to 0x1ff. + */ + contr_r_addr[0] = 9; + contr_r_addr[1] = 0xff; + addr_void[0] = 0; + addr_void[1] = addr[1]; +#ifdef CFG_I2C_EEPROM_ADDR + contr_r_addr[0] |= CFG_I2C_EEPROM_ADDR; + addr_void[0] |= CFG_I2C_EEPROM_ADDR; +#endif + contr_reg[0] = 0xff; + if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) { + rcode = 1; + } + ctrl_reg_v = contr_reg[0]; + + /* Are any of the eeprom blocks write protected? + */ + if (ctrl_reg_v & 0x18) { + ctrl_reg_v &= ~0x18; /* reset block protect bits */ + ctrl_reg_v |= 0x02; /* set write enable latch */ + ctrl_reg_v &= ~0x04; /* clear RWEL */ + + /* Set write enable latch. + */ + contr_reg[0] = 0x02; + if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) { + rcode = 1; + } + + /* Set register write enable latch. + */ + contr_reg[0] = 0x06; + if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { + rcode = 1; + } + + /* Modify ctrl register. + */ + contr_reg[0] = ctrl_reg_v; + if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { + rcode = 1; + } + + /* The write (above) is an operation on NV memory. + * These can take some time (~5ms), and the device + * will not respond to further I2C messages till + * it's completed the write. + * So poll device for an I2C acknowledge. + * When we get one we know we can continue with other + * operations. + */ + contr_reg[0] = 0; + for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) { + if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0) + break; /* got ack */ +#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#endif + } + if (i == MAX_ACKNOWLEDGE_POLLS) { + puts ("EEPROM poll acknowledge failed\n"); + rcode = 1; + } + } + + /* Is the write enable latch on?. + */ + else if (!(ctrl_reg_v & 0x02)) { + /* Set write enable latch. + */ + contr_reg[0] = 0x02; + if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { + rcode = 1; + } + } + /* Write is enabled ... now write eeprom value. + */ +#endif + if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0) + rcode = 1; + +#endif + buffer += len; + offset += len; + +#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#endif + } +#if defined(CFG_EEPROM_WREN) + eeprom_write_enable (dev_addr,0); +#endif + return rcode; +} + +#ifndef CONFIG_SPI +int +eeprom_probe (unsigned dev_addr, unsigned offset) +{ + unsigned char chip; + + /* Probe the chip address + */ +#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) + chip = offset >> 8; /* block number */ +#else + chip = offset >> 16; /* block number */ +#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ + + chip |= dev_addr; /* insert device address */ + + return (i2c_probe (chip)); +} +#endif + +/*----------------------------------------------------------------------- + * Set default values + */ +#ifndef CFG_I2C_SPEED +#define CFG_I2C_SPEED 50000 +#endif + +#ifndef CFG_I2C_SLAVE +#define CFG_I2C_SLAVE 0xFE +#endif + +void eeprom_init (void) +{ +#if defined(CONFIG_SPI) + spi_init_f (); +#endif +#if defined(CONFIG_HARD_I2C) || \ + defined(CONFIG_SOFT_I2C) + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); +#endif +} +/*----------------------------------------------------------------------- + */ +#endif /* CFG_CMD_EEPROM */ +/***************************************************/ + +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) + +#ifdef CFG_I2C_MULTI_EEPROMS +U_BOOT_CMD( + eeprom, 6, 1, do_eeprom, + "eeprom - EEPROM sub-system\n", + "read devaddr addr off cnt\n" + "eeprom write devaddr addr off cnt\n" + " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'\n" +); +#else /* One EEPROM */ +U_BOOT_CMD( + eeprom, 5, 1, do_eeprom, + "eeprom - EEPROM sub-system\n", + "read addr off cnt\n" + "eeprom write addr off cnt\n" + " - read/write `cnt' bytes at EEPROM offset `off'\n" +); +#endif /* CFG_I2C_MULTI_EEPROMS */ + +#endif /* CFG_CMD_EEPROM */ diff --git a/common/cmd_elf.c b/common/cmd_elf.c new file mode 100644 index 0000000..eccf2e9 --- /dev/null +++ b/common/cmd_elf.c @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2001 William L. Pitts + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ + +#include +#include +#include +#include +#include + + +#if (CONFIG_COMMANDS & CFG_CMD_ELF) + +#ifndef MAX +#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif + +int valid_elf_image (unsigned long addr); +unsigned long load_elf_image (unsigned long addr); + +/* ====================================================================== + * Interpreter command to boot an arbitrary ELF image from memory. + * ====================================================================== */ +int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long addr; /* Address of the ELF image */ + unsigned long rc; /* Return value from user code */ + + /* -------------------------------------------------- */ + int rcode = 0; + + if (argc < 2) + addr = load_addr; + else + addr = simple_strtoul (argv[1], NULL, 16); + + if (!valid_elf_image (addr)) + return 1; + + addr = load_elf_image (addr); + + printf ("## Starting application at 0x%08lx ...\n", addr); + + /* + * QNX images require the data cache is disabled. + * Data cache is already flushed, so just turn it off. + */ + if (dcache_status ()) + dcache_disable (); + + /* + * pass address parameter as argv[0] (aka command name), + * and all remaining args + */ + rc = ((ulong (*)(int, char *[])) addr) (--argc, &argv[1]); + if (rc != 0) + rcode = 1; + + printf ("## Application terminated, rc = 0x%lx\n", rc); + return rcode; +} + +/* ====================================================================== + * Interpreter command to boot VxWorks from a memory image. The image can + * be either an ELF image or a raw binary. Will attempt to setup the + * bootline and other parameters correctly. + * ====================================================================== */ +int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_WALNUT) || \ + defined(CFG_VXWORKS_MAC_PTR) + DECLARE_GLOBAL_DATA_PTR; +#endif + + unsigned long addr; /* Address of image */ + unsigned long bootaddr; /* Address to put the bootline */ + char *bootline; /* Text of the bootline */ + char *tmp; /* Temporary char pointer */ + +#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) + char build_buf[80]; /* Buffer for building the bootline */ +#endif + /* -------------------------------------------------- */ + + /* + * Check the loadaddr variable. + * If we don't know where the image is then we're done. + */ + + if ((tmp = getenv ("loadaddr")) != NULL) { + addr = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No load address provided\n"); + return 1; + } + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + /* Check to see if we need to tftp the image ourselves before starting */ + + if ((argc == 2) && (strcmp (argv[1], "tftp") == 0)) { + if (NetLoop (TFTP) <= 0) + return 1; + printf ("Automatic boot of VxWorks image at address 0x%08lx ... \n", addr); + } +#endif + + /* This should equate + * to NV_RAM_ADRS + NV_BOOT_OFFSET + NV_ENET_OFFSET + * from the VxWorks BSP header files. + * This will vary from board to board + */ + +#if defined(CONFIG_WALNUT) + tmp = (char *) CFG_NVRAM_BASE_ADDR + 0x500; + memcpy ((char *) tmp, (char *) &gd->bd->bi_enetaddr[3], 3); +#elif defined(CFG_VXWORKS_MAC_PTR) + tmp = (char *) CFG_VXWORKS_MAC_PTR; + memcpy ((char *) tmp, (char *) &gd->bd->bi_enetaddr[0], 6); +#else + puts ("## Ethernet MAC address not copied to NV RAM\n"); +#endif + + /* + * Use bootaddr to find the location in memory that VxWorks + * will look for the bootline string. The default value for + * PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which + * defaults to 0x4200 + */ + + if ((tmp = getenv ("bootaddr")) == NULL) + bootaddr = 0x4200; + else + bootaddr = simple_strtoul (tmp, NULL, 16); + + /* + * Check to see if the bootline is defined in the 'bootargs' + * parameter. If it is not defined, we may be able to + * construct the info + */ + + if ((bootline = getenv ("bootargs")) != NULL) { + memcpy ((void *) bootaddr, bootline, MAX(strlen(bootline), 255)); + flush_cache (bootaddr, MAX(strlen(bootline), 255)); + } else { +#if defined(CONFIG_4xx) + sprintf (build_buf, "ibmEmac(0,0)"); + + if ((tmp = getenv ("hostname")) != NULL) { + sprintf (&build_buf[strlen (build_buf - 1)], + "host:%s ", tmp); + } else { + sprintf (&build_buf[strlen (build_buf - 1)], + ": "); + } + + if ((tmp = getenv ("ipaddr")) != NULL) { + sprintf (&build_buf[strlen (build_buf - 1)], + "e=%s ", tmp); + } + memcpy ((void *)bootaddr, build_buf, MAX(strlen(build_buf), 255)); + flush_cache (bootaddr, MAX(strlen(build_buf), 255)); +#elif defined(CONFIG_IOP480) + sprintf (build_buf, "dc(0,0)"); + + if ((tmp = getenv ("hostname")) != NULL) { + sprintf (&build_buf[strlen (build_buf - 1)], + "host:%s ", tmp); + } else { + sprintf (&build_buf[strlen (build_buf - 1)], + ": "); + } + + if ((tmp = getenv ("ipaddr")) != NULL) { + sprintf (&build_buf[strlen (build_buf - 1)], + "e=%s ", tmp); + } + memcpy ((void *) bootaddr, build_buf, MAX(strlen(build_buf), 255)); + flush_cache (bootaddr, MAX(strlen(build_buf), 255)); +#else + + /* + * I'm not sure what the device should be for other + * PPC flavors, the hostname and ipaddr should be ok + * to just copy + */ + + puts ("No bootargs defined\n"); + return 1; +#endif + } + + /* + * If the data at the load address is an elf image, then + * treat it like an elf image. Otherwise, assume that it is a + * binary image + */ + + if (valid_elf_image (addr)) { + addr = load_elf_image (addr); + } else { + puts ("## Not an ELF image, assuming binary\n"); + /* leave addr as load_addr */ + } + + printf ("## Using bootline (@ 0x%lx): %s\n", bootaddr, + (char *) bootaddr); + printf ("## Starting vxWorks at 0x%08lx ...\n", addr); + + ((void (*)(void)) addr) (); + + puts ("## vxWorks terminated\n"); + return 1; +} + +/* ====================================================================== + * Determine if a valid ELF image exists at the given memory location. + * First looks at the ELF header magic field, the makes sure that it is + * executable and makes sure that it is for a PowerPC. + * ====================================================================== */ +int valid_elf_image (unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* Elf header structure pointer */ + + /* -------------------------------------------------- */ + + ehdr = (Elf32_Ehdr *) addr; + + if (!IS_ELF (*ehdr)) { + printf ("## No elf image at address 0x%08lx\n", addr); + return 0; + } + + if (ehdr->e_type != ET_EXEC) { + printf ("## Not a 32-bit elf image at address 0x%08lx\n", + addr); + return 0; + } + +#if 0 + if (ehdr->e_machine != EM_PPC) { + printf ("## Not a PowerPC elf image at address 0x%08lx\n", + addr); + return 0; + } +#endif + + return 1; +} + + +/* ====================================================================== + * A very simple elf loader, assumes the image is valid, returns the + * entry point address. + * ====================================================================== */ +unsigned long load_elf_image (unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* Elf header structure pointer */ + Elf32_Shdr *shdr; /* Section header structure pointer */ + unsigned char *strtab = 0; /* String table pointer */ + unsigned char *image; /* Binary image pointer */ + int i; /* Loop counter */ + + /* -------------------------------------------------- */ + + ehdr = (Elf32_Ehdr *) addr; + + /* Find the section header string table for output info */ + shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff + + (ehdr->e_shstrndx * sizeof (Elf32_Shdr))); + + if (shdr->sh_type == SHT_STRTAB) + strtab = (unsigned char *) (addr + shdr->sh_offset); + + /* Load each appropriate section */ + for (i = 0; i < ehdr->e_shnum; ++i) { + shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff + + (i * sizeof (Elf32_Shdr))); + + if (!(shdr->sh_flags & SHF_ALLOC) + || shdr->sh_addr == 0 || shdr->sh_size == 0) { + continue; + } + + if (strtab) { + printf ("%sing %s @ 0x%08lx (%ld bytes)\n", + (shdr->sh_type == SHT_NOBITS) ? + "Clear" : "Load", + &strtab[shdr->sh_name], + (unsigned long) shdr->sh_addr, + (long) shdr->sh_size); + } + + if (shdr->sh_type == SHT_NOBITS) { + memset ((void *)shdr->sh_addr, 0, shdr->sh_size); + } else { + image = (unsigned char *) addr + shdr->sh_offset; + memcpy ((void *) shdr->sh_addr, + (const void *) image, + shdr->sh_size); + } + flush_cache (shdr->sh_addr, shdr->sh_size); + } + + return ehdr->e_entry; +} + +/* ====================================================================== */ +U_BOOT_CMD( + bootelf, 2, 0, do_bootelf, + "bootelf - Boot from an ELF image in memory\n", + " [address] - load address of ELF image.\n" +); + +U_BOOT_CMD( + bootvx, 2, 0, do_bootvx, + "bootvx - Boot vxWorks from an ELF image\n", + " [address] - load address of vxWorks ELF image.\n" +); + +#endif /* CFG_CMD_ELF */ diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c new file mode 100644 index 0000000..5db42f2 --- /dev/null +++ b/common/cmd_ext2.c @@ -0,0 +1,297 @@ +/* + * (C) Copyright 2004 + * esd gmbh + * Reinhard Arlt + * + * made from cmd_reiserfs by + * + * (C) Copyright 2003 - 2004 + * Sysgo Real-Time Solutions, AG + * Pavel Bartusek + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Ext2fs support + */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_EXT2) +#include +#include +#include +#include +#include +#include +#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE)) +#include +#endif + +#ifndef CONFIG_DOS_PARTITION +#error DOS partition support must be selected +#endif + +/* #define EXT2_DEBUG */ + +#ifdef EXT2_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +static block_dev_desc_t *get_dev (char* ifname, int dev) +{ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + if (strncmp(ifname,"ide",3)==0) { + extern block_dev_desc_t * ide_get_dev(int dev); + return((dev >= CFG_IDE_MAXDEVICE) ? NULL : ide_get_dev(dev)); + } +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + if (strncmp(ifname,"scsi",4)==0) { + extern block_dev_desc_t * scsi_get_dev(int dev); + return((dev >= CFG_SCSI_MAXDEVICE) ? NULL : scsi_get_dev(dev)); + } +#endif +#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE)) + if (strncmp(ifname,"usb",3)==0) { + extern block_dev_desc_t * usb_stor_get_dev(int dev); + return((dev >= USB_MAX_STOR_DEV) ? NULL : usb_stor_get_dev(dev)); + } +#endif +#if defined(CONFIG_MMC) + if (strncmp(ifname,"mmc",3)==0) { + extern block_dev_desc_t * mmc_get_dev(int dev); + return((dev >= 1) ? NULL : mmc_get_dev(dev)); + } +#endif +#if defined(CONFIG_SYSTEMACE) + if (strcmp(ifname,"ace")==0) { + extern block_dev_desc_t * systemace_get_dev(int dev); + return((dev >= 1) ? NULL : systemace_get_dev(dev)); + } +#endif + return(NULL); +} + +int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *filename = "/"; + int dev=0; + int part=1; + char *ep; + block_dev_desc_t *dev_desc=NULL; + int part_length; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return(1); + } + dev = (int)simple_strtoul (argv[2], &ep, 16); + dev_desc=get_dev(argv[1],dev); + + if (dev_desc == NULL) { + printf ("\n** Block device %s %d not supported\n", argv[1], dev); + return(1); + } + + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + return(1); + } + part = (int)simple_strtoul(++ep, NULL, 16); + } + + if (argc == 4) { + filename = argv[3]; + } + + PRINTF("Using device %s %d:%d, directory: %s\n", argv[1], dev, part, filename); + + if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) { + printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part); + ext2fs_close(); + return(1); + } + + if (!ext2fs_mount(part_length)) { + printf ("** Bad ext2 partition or disk - %s %d:%d **\n", argv[1], dev, part); + ext2fs_close(); + return(1); + } + + if (ext2fs_ls (filename)) { + printf ("** Error ext2fs_ls() **\n"); + ext2fs_close(); + return(1); + }; + + ext2fs_close(); + + return(0); +} + +U_BOOT_CMD( + ext2ls, 4, 1, do_ext2ls, + "ext2ls - list files in a directory (default /)\n", + " [directory]\n" + " - list files from 'dev' on 'interface' in a 'directory'\n" +); + +/****************************************************************************** + * Ext2fs boot command intepreter. Derived from diskboot + */ +int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *filename = NULL; + char *ep; + int dev, part = 1; + ulong addr = 0, part_length, filelen; + disk_partition_t info; + block_dev_desc_t *dev_desc = NULL; + char buf [12]; + unsigned long count; + char *addr_str; + + switch (argc) { + case 3: + addr_str = getenv("loadaddr"); + if (addr_str != NULL) { + addr = simple_strtoul (addr_str, NULL, 16); + } else { + addr = CFG_LOAD_ADDR; + } + filename = getenv ("bootfile"); + count = 0; + break; + case 4: + addr = simple_strtoul (argv[3], NULL, 16); + filename = getenv ("bootfile"); + count = 0; + break; + case 5: + addr = simple_strtoul (argv[3], NULL, 16); + filename = argv[4]; + count = 0; + break; + case 6: + addr = simple_strtoul (argv[3], NULL, 16); + filename = argv[4]; + count = simple_strtoul (argv[5], NULL, 16); + break; + + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return(1); + } + + if (!filename) { + puts ("\n** No boot file defined **\n"); + return(1); + } + + dev = (int)simple_strtoul (argv[2], &ep, 16); + dev_desc=get_dev(argv[1],dev); + if (dev_desc==NULL) { + printf ("\n** Block device %s %d not supported\n", argv[1], dev); + return(1); + } + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + return(1); + } + part = (int)simple_strtoul(++ep, NULL, 16); + } + + PRINTF("Using device %s%d, partition %d\n", argv[1], dev, part); + + if (part != 0) { + if (get_partition_info (dev_desc, part, &info)) { + printf ("** Bad partition %d **\n", part); + return(1); + } + + if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) { + printf ("\n** Invalid partition type \"%.32s\"" + " (expect \"" BOOT_PART_TYPE "\")\n", + info.type); + return(1); + } + PRINTF ("\nLoading from block device %s device %d, partition %d: " + "Name: %.32s Type: %.32s File:%s\n", + argv[1], dev, part, info.name, info.type, filename); + } else { + PRINTF ("\nLoading from block device %s device %d, File:%s\n", + argv[1], dev, filename); + } + + + if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) { + printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part); + ext2fs_close(); + return(1); + } + + if (!ext2fs_mount(part_length)) { + printf ("** Bad ext2 partition or disk - %s %d:%d **\n", argv[1], dev, part); + ext2fs_close(); + return(1); + } + + filelen = ext2fs_open(filename); + if (filelen < 0) { + printf("** File not found %s\n", filename); + ext2fs_close(); + return(1); + } + if ((count < filelen) && (count != 0)) { + filelen = count; + } + + if (ext2fs_read((char *)addr, filelen) != filelen) { + printf("\n** Unable to read \"%s\" from %s %d:%d **\n", filename, argv[1], dev, part); + ext2fs_close(); + return(1); + } + + ext2fs_close(); + + /* Loading ok, update default load address */ + load_addr = addr; + + printf ("\n%ld bytes read\n", filelen); + sprintf(buf, "%lX", filelen); + setenv("filesize", buf); + + return(filelen); +} + +U_BOOT_CMD( + ext2load, 6, 0, do_ext2load, + "ext2load- load binary file from a Ext2 filesystem\n", + " [addr] [filename] [bytes]\n" + " - load binary file 'filename' from 'dev' on 'interface'\n" + " to address 'addr' from ext2 filesystem\n" +); + +#endif /* CONFIG_COMMANDS & CFG_CMD_EXT2 */ diff --git a/common/cmd_fat.c b/common/cmd_fat.c new file mode 100644 index 0000000..6844c10 --- /dev/null +++ b/common/cmd_fat.c @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2002 + * Richard Jones, rjones@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Boot support + */ +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FAT) + +#undef DEBUG + +#include + + +block_dev_desc_t *get_dev (char* ifname, int dev) +{ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + if (strncmp(ifname,"ide",3)==0) { + extern block_dev_desc_t * ide_get_dev(int dev); + return(ide_get_dev(dev)); + } +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + if (strncmp(ifname,"scsi",4)==0) { + extern block_dev_desc_t * scsi_get_dev(int dev); + return(scsi_get_dev(dev)); + } +#endif +#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE)) + if (strncmp(ifname,"usb",3)==0) { + extern block_dev_desc_t * usb_stor_get_dev(int dev); + return(usb_stor_get_dev(dev)); + } +#endif +#if defined(CONFIG_MMC) + if (strncmp(ifname,"mmc",3)==0) { + extern block_dev_desc_t * mmc_get_dev(int dev); + return(mmc_get_dev(dev)); + } +#endif +#if defined(CONFIG_SYSTEMACE) + if (strcmp(ifname,"ace")==0) { + extern block_dev_desc_t * systemace_get_dev(int dev); + return(systemace_get_dev(dev)); + } +#endif + return NULL; +} + + +int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + long size; + unsigned long offset; + unsigned long count; + char buf [12]; + block_dev_desc_t *dev_desc=NULL; + int dev=0; + int part=1; + char *ep; + + if (argc < 5) { + printf ("usage: fatload [bytes]\n"); + return 1; + } + dev = (int)simple_strtoul (argv[2], &ep, 16); + dev_desc=get_dev(argv[1],dev); + if (dev_desc==NULL) { + puts ("\n** Invalid boot device **\n"); + return 1; + } + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + return 1; + } + part = (int)simple_strtoul(++ep, NULL, 16); + } + if (fat_register_device(dev_desc,part)!=0) { + printf ("\n** Unable to use %s %d:%d for fatload **\n",argv[1],dev,part); + return 1; + } + offset = simple_strtoul (argv[3], NULL, 16); + if (argc == 6) + count = simple_strtoul (argv[5], NULL, 16); + else + count = 0; + size = file_fat_read (argv[4], (unsigned char *) offset, count); + + if(size==-1) { + printf("\n** Unable to read \"%s\" from %s %d:%d **\n",argv[4],argv[1],dev,part); + return 1; + } + + printf ("\n%ld bytes read\n", size); + + sprintf(buf, "%lX", size); + setenv("filesize", buf); + + return 0; +} + + +U_BOOT_CMD( + fatload, 6, 0, do_fat_fsload, + "fatload - load binary file from a dos filesystem\n", + " [bytes]\n" + " - load binary file 'filename' from 'dev' on 'interface'\n" + " to address 'addr' from dos filesystem\n" +); + +int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *filename = "/"; + int ret; + int dev=0; + int part=1; + char *ep; + block_dev_desc_t *dev_desc=NULL; + + if (argc < 3) { + printf ("usage: fatls [directory]\n"); + return (0); + } + dev = (int)simple_strtoul (argv[2], &ep, 16); + dev_desc=get_dev(argv[1],dev); + if (dev_desc==NULL) { + puts ("\n** Invalid boot device **\n"); + return 1; + } + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + return 1; + } + part = (int)simple_strtoul(++ep, NULL, 16); + } + if (fat_register_device(dev_desc,part)!=0) { + printf ("\n** Unable to use %s %d:%d for fatls **\n",argv[1],dev,part); + return 1; + } + if (argc == 4) + ret = file_fat_ls (argv[3]); + else + ret = file_fat_ls (filename); + + if(ret!=0) + printf("No Fat FS detected\n"); + return (ret); +} + +U_BOOT_CMD( + fatls, 4, 1, do_fat_ls, + "fatls - list files in a directory (default /)\n", + " [directory]\n" + " - list files from 'dev' on 'interface' in a 'directory'\n" +); + +int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int dev=0; + int part=1; + char *ep; + block_dev_desc_t *dev_desc=NULL; + + if (argc < 2) { + printf ("usage: fatinfo \n"); + return (0); + } + dev = (int)simple_strtoul (argv[2], &ep, 16); + dev_desc=get_dev(argv[1],dev); + if (dev_desc==NULL) { + puts ("\n** Invalid boot device **\n"); + return 1; + } + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + return 1; + } + part = (int)simple_strtoul(++ep, NULL, 16); + } + if (fat_register_device(dev_desc,part)!=0) { + printf ("\n** Unable to use %s %d:%d for fatinfo **\n",argv[1],dev,part); + return 1; + } + return (file_fat_detectfs ()); +} + +U_BOOT_CMD( + fatinfo, 3, 1, do_fat_fsinfo, + "fatinfo - print information about filesystem\n", + " \n" + " - print information about filesystem from 'dev' on 'interface'\n" +); + +#ifdef NOT_IMPLEMENTED_YET +/* find first device whose first partition is a DOS filesystem */ +int find_fat_partition (void) +{ + int i, j; + block_dev_desc_t *dev_desc; + unsigned char *part_table; + unsigned char buffer[ATA_BLOCKSIZE]; + + for (i = 0; i < CFG_IDE_MAXDEVICE; i++) { + dev_desc = ide_get_dev (i); + if (!dev_desc) { + debug ("couldn't get ide device!\n"); + return (-1); + } + if (dev_desc->part_type == PART_TYPE_DOS) { + if (dev_desc-> + block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) { + debug ("can't perform block_read!\n"); + return (-1); + } + part_table = &buffer[0x1be]; /* start with partition #4 */ + for (j = 0; j < 4; j++) { + if ((part_table[4] == 1 || /* 12-bit FAT */ + part_table[4] == 4 || /* 16-bit FAT */ + part_table[4] == 6) && /* > 32Meg part */ + part_table[0] == 0x80) { /* bootable? */ + curr_dev = i; + part_offset = part_table[11]; + part_offset <<= 8; + part_offset |= part_table[10]; + part_offset <<= 8; + part_offset |= part_table[9]; + part_offset <<= 8; + part_offset |= part_table[8]; + debug ("found partition start at %ld\n", part_offset); + return (0); + } + part_table += 16; + } + } + } + + debug ("no valid devices found!\n"); + return (-1); +} + +int +do_fat_dump (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + __u8 block[1024]; + int ret; + int bknum; + + ret = 0; + + if (argc != 2) { + printf ("needs an argument!\n"); + return (0); + } + + bknum = simple_strtoul (argv[1], NULL, 10); + + if (disk_read (0, bknum, block) != 0) { + printf ("Error: reading block\n"); + return -1; + } + printf ("FAT dump: %d\n", bknum); + hexdump (512, block); + + return (ret); +} + +int disk_read (__u32 startblock, __u32 getsize, __u8 *bufptr) +{ + ulong tot; + block_dev_desc_t *dev_desc; + + if (curr_dev < 0) { + if (find_fat_partition () != 0) + return (-1); + } + + dev_desc = ide_get_dev (curr_dev); + if (!dev_desc) { + debug ("couldn't get ide device\n"); + return (-1); + } + + tot = dev_desc->block_read (0, startblock + part_offset, + getsize, (ulong *) bufptr); + + /* should we do this here? + flush_cache ((ulong)buf, cnt*ide_dev_desc[device].blksz); + */ + + if (tot == getsize) + return (0); + + debug ("unable to read from device!\n"); + + return (-1); +} + + +static int isprint (unsigned char ch) +{ + if (ch >= 32 && ch < 127) + return (1); + + return (0); +} + + +void hexdump (int cnt, unsigned char *data) +{ + int i; + int run; + int offset; + + offset = 0; + while (cnt) { + printf ("%04X : ", offset); + if (cnt >= 16) + run = 16; + else + run = cnt; + cnt -= run; + for (i = 0; i < run; i++) + printf ("%02X ", (unsigned int) data[i]); + printf (": "); + for (i = 0; i < run; i++) + printf ("%c", isprint (data[i]) ? data[i] : '.'); + printf ("\n"); + data = &data[16]; + offset += run; + } +} +#endif /* NOT_IMPLEMENTED_YET */ + +#endif /* CFG_CMD_FAT */ diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c new file mode 100644 index 0000000..02dffa3 --- /dev/null +++ b/common/cmd_fdc.c @@ -0,0 +1,896 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG, d.peter@mpl.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * Floppy Disk support + */ + +#include +#include +#include +#include + + +#undef FDC_DEBUG + +#ifdef FDC_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + + +/*#if (CONFIG_COMMANDS & CFG_CMD_DATE) */ +/*#include */ +/*#endif */ + +#if ((CONFIG_COMMANDS & CFG_CMD_FDC) || (CONFIG_COMMANDS & CFG_CMD_FDOS)) + + +typedef struct { + int flags; /* connected drives ect */ + unsigned long blnr; /* Logical block nr */ + uchar drive; /* drive no */ + uchar cmdlen; /* cmd length */ + uchar cmd[16]; /* cmd desc */ + uchar dma; /* if > 0 dma enabled */ + uchar result[11];/* status information */ + uchar resultlen; /* lenght of result */ +} FDC_COMMAND_STRUCT; +/* flags: only the lower 8bit used: + * bit 0 if set drive 0 is present + * bit 1 if set drive 1 is present + * bit 2 if set drive 2 is present + * bit 3 if set drive 3 is present + * bit 4 if set disk in drive 0 is inserted + * bit 5 if set disk in drive 1 is inserted + * bit 6 if set disk in drive 2 is inserted + * bit 7 if set disk in drive 4 is inserted + */ + + +/* cmd indexes */ +#define COMMAND 0 +#define DRIVE 1 +#define CONFIG0 1 +#define SPEC_HUTSRT 1 +#define TRACK 2 +#define CONFIG1 2 +#define SPEC_HLT 2 +#define HEAD 3 +#define CONFIG2 3 +#define SECTOR 4 +#define SECTOR_SIZE 5 +#define LAST_TRACK 6 +#define GAP 7 +#define DTL 8 +/* result indexes */ +#define STATUS_0 0 +#define STATUS_PCN 1 +#define STATUS_1 1 +#define STATUS_2 2 +#define STATUS_TRACK 3 +#define STATUS_HEAD 4 +#define STATUS_SECT 5 +#define STATUS_SECT_SIZE 6 + + +/* Register addresses */ +#define FDC_BASE 0x3F0 +#define FDC_SRA FDC_BASE + 0 /* Status Register A */ +#define FDC_SRB FDC_BASE + 1 /* Status Register B */ +#define FDC_DOR FDC_BASE + 2 /* Digital Output Register */ +#define FDC_TDR FDC_BASE + 3 /* Tape Drive Register */ +#define FDC_DSR FDC_BASE + 4 /* Data rate Register */ +#define FDC_MSR FDC_BASE + 4 /* Main Status Register */ +#define FDC_FIFO FDC_BASE + 5 /* FIFO */ +#define FDC_DIR FDC_BASE + 6 /* Digital Input Register */ +#define FDC_CCR FDC_BASE + 7 /* Configuration Control */ +/* Commands */ +#define FDC_CMD_SENSE_INT 0x08 +#define FDC_CMD_CONFIGURE 0x13 +#define FDC_CMD_SPECIFY 0x03 +#define FDC_CMD_RECALIBRATE 0x07 +#define FDC_CMD_READ 0x06 +#define FDC_CMD_READ_TRACK 0x02 +#define FDC_CMD_READ_ID 0x0A +#define FDC_CMD_DUMP_REG 0x0E +#define FDC_CMD_SEEK 0x0F + +#define FDC_CMD_SENSE_INT_LEN 0x01 +#define FDC_CMD_CONFIGURE_LEN 0x04 +#define FDC_CMD_SPECIFY_LEN 0x03 +#define FDC_CMD_RECALIBRATE_LEN 0x02 +#define FDC_CMD_READ_LEN 0x09 +#define FDC_CMD_READ_TRACK_LEN 0x09 +#define FDC_CMD_READ_ID_LEN 0x02 +#define FDC_CMD_DUMP_REG_LEN 0x01 +#define FDC_CMD_SEEK_LEN 0x03 + +#define FDC_FIFO_THR 0x0C +#define FDC_FIFO_DIS 0x00 +#define FDC_IMPLIED_SEEK 0x01 +#define FDC_POLL_DIS 0x00 +#define FDC_PRE_TRK 0x00 +#define FDC_CONFIGURE FDC_FIFO_THR | (FDC_POLL_DIS<<4) | (FDC_FIFO_DIS<<5) | (FDC_IMPLIED_SEEK << 6) +#define FDC_MFM_MODE 0x01 /* MFM enable */ +#define FDC_SKIP_MODE 0x00 /* skip enable */ + +#define FDC_TIME_OUT 100000 /* time out */ +#define FDC_RW_RETRIES 3 /* read write retries */ +#define FDC_CAL_RETRIES 3 /* calibration and seek retries */ + + +/* Disk structure */ +typedef struct { + unsigned int size; /* nr of sectors total */ + unsigned int sect; /* sectors per track */ + unsigned int head; /* nr of heads */ + unsigned int track; /* nr of tracks */ + unsigned int stretch; /* !=0 means double track steps */ + unsigned char gap; /* gap1 size */ + unsigned char rate; /* data rate. |= 0x40 for perpendicular */ + unsigned char spec1; /* stepping rate, head unload time */ + unsigned char fmt_gap; /* gap2 size */ + unsigned char hlt; /* head load time */ + unsigned char sect_code; /* Sector Size code */ + const char * name; /* used only for predefined formats */ +} FD_GEO_STRUCT; + + +/* supported Floppy types (currently only one) */ +const static FD_GEO_STRUCT floppy_type[2] = { + { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,16,2,"H1440" }, /* 7 1.44MB 3.5" */ + { 0, 0,0, 0,0,0x00,0x00,0x00,0x00, 0,0,NULL }, /* end of table */ +}; + +static FDC_COMMAND_STRUCT cmd; /* global command struct */ + +/* If the boot drive number is undefined, we assume it's drive 0 */ +#ifndef CFG_FDC_DRIVE_NUMBER +#define CFG_FDC_DRIVE_NUMBER 0 +#endif + +/* Hardware access */ +#ifndef CFG_ISA_IO_STRIDE +#define CFG_ISA_IO_STRIDE 1 +#endif + +#ifndef CFG_ISA_IO_OFFSET +#define CFG_ISA_IO_OFFSET 0 +#endif + + +#ifdef CONFIG_AMIGAONEG3SE +unsigned char INT6_Status; + +void fdc_interrupt(void) +{ + INT6_Status = 0x80; +} + +/* waits for an interrupt (polling) */ +int wait_for_fdc_int(void) +{ + unsigned long timeout; + timeout = FDC_TIME_OUT; + while(((volatile)INT6_Status & 0x80) == 0) { + timeout--; + udelay(10); + if(timeout == 0) /* timeout occured */ + return FALSE; + } + INT6_Status = 0; + return TRUE; +} +#endif + +/* Supporting Functions */ +/* reads a Register of the FDC */ +unsigned char read_fdc_reg(unsigned int addr) +{ + volatile unsigned char *val = + (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS + + (addr * CFG_ISA_IO_STRIDE) + + CFG_ISA_IO_OFFSET); + + return val [0]; +} + +/* writes a Register of the FDC */ +void write_fdc_reg(unsigned int addr, unsigned char val) +{ + volatile unsigned char *tmp = + (volatile unsigned char *)(CFG_ISA_IO_BASE_ADDRESS + + (addr * CFG_ISA_IO_STRIDE) + + CFG_ISA_IO_OFFSET); + tmp[0]=val; +} + +#ifndef CONFIG_AMIGAONEG3SE +/* waits for an interrupt (polling) */ +int wait_for_fdc_int(void) +{ + unsigned long timeout; + timeout = FDC_TIME_OUT; + while((read_fdc_reg(FDC_SRA)&0x80)==0) { + timeout--; + udelay(10); + if(timeout==0) /* timeout occured */ + return FALSE; + } + return TRUE; +} + +#endif + +/* reads a byte from the FIFO of the FDC and checks direction and RQM bit + of the MSR. returns -1 if timeout, or byte if ok */ +int read_fdc_byte(void) +{ + unsigned long timeout; + timeout = FDC_TIME_OUT; + while((read_fdc_reg(FDC_MSR)&0xC0)!=0xC0) { + /* direction out and ready */ + udelay(10); + timeout--; + if(timeout==0) /* timeout occured */ + return -1; + } + return read_fdc_reg(FDC_FIFO); +} + +/* if the direction of the FIFO is wrong, this routine is used to + empty the FIFO. Should _not_ be used */ +int fdc_need_more_output(void) +{ + unsigned char c; + while((read_fdc_reg(FDC_MSR)&0xC0)==0xC0) { + c=(unsigned char)read_fdc_byte(); + printf("Error: more output: %x\n",c); + } + return TRUE; +} + + +/* writes a byte to the FIFO of the FDC and checks direction and RQM bit + of the MSR */ +int write_fdc_byte(unsigned char val) +{ + unsigned long timeout; + timeout = FDC_TIME_OUT; + while((read_fdc_reg(FDC_MSR)&0xC0)!=0x80) { + /* direction in and ready for byte */ + timeout--; + udelay(10); + fdc_need_more_output(); + if(timeout==0) /* timeout occured */ + return FALSE; + } + write_fdc_reg(FDC_FIFO,val); + return TRUE; +} + +/* sets up all FDC commands and issues it to the FDC. If + the command causes direct results (no Execution Phase) + the result is be read as well. */ + +int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG) +{ + int i; + unsigned long head,track,sect,timeout; + track = pCMD->blnr / (pFG->sect * pFG->head); /* track nr */ + sect = pCMD->blnr % (pFG->sect * pFG->head); /* remaining blocks */ + head = sect / pFG->sect; /* head nr */ + sect = sect % pFG->sect; /* remaining blocks */ + sect++; /* sectors are 1 based */ + PRINTF("Cmd 0x%02x Track %ld, Head %ld, Sector %ld, Drive %d (blnr %ld)\n", + pCMD->cmd[0],track,head,sect,pCMD->drive,pCMD->blnr); + + if(head|=0) { /* max heads = 2 */ + pCMD->cmd[DRIVE]=pCMD->drive | 0x04; /* head 1 */ + pCMD->cmd[HEAD]=(unsigned char) head; /* head register */ + } + else { + pCMD->cmd[DRIVE]=pCMD->drive; /* head 0 */ + pCMD->cmd[HEAD]=(unsigned char) head; /* head register */ + } + pCMD->cmd[TRACK]=(unsigned char) track; /* track */ + switch (pCMD->cmd[COMMAND]) { + case FDC_CMD_READ: + pCMD->cmd[SECTOR]=(unsigned char) sect; /* sector */ + pCMD->cmd[SECTOR_SIZE]=pFG->sect_code; /* sector size code */ + pCMD->cmd[LAST_TRACK]=pFG->sect; /* End of track */ + pCMD->cmd[GAP]=pFG->gap; /* gap */ + pCMD->cmd[DTL]=0xFF; /* DTL */ + pCMD->cmdlen=FDC_CMD_READ_LEN; + pCMD->cmd[COMMAND]|=(FDC_MFM_MODE<<6); /* set MFM bit */ + pCMD->cmd[COMMAND]|=(FDC_SKIP_MODE<<5); /* set Skip bit */ + pCMD->resultlen=0; /* result only after execution */ + break; + case FDC_CMD_SEEK: + pCMD->cmdlen=FDC_CMD_SEEK_LEN; + pCMD->resultlen=0; /* no result */ + break; + case FDC_CMD_CONFIGURE: + pCMD->cmd[CONFIG0]=0; + pCMD->cmd[CONFIG1]=FDC_CONFIGURE; /* FIFO Threshold, Poll, Enable FIFO */ + pCMD->cmd[CONFIG2]=FDC_PRE_TRK; /* Precompensation Track */ + pCMD->cmdlen=FDC_CMD_CONFIGURE_LEN; + pCMD->resultlen=0; /* no result */ + break; + case FDC_CMD_SPECIFY: + pCMD->cmd[SPEC_HUTSRT]=pFG->spec1; + pCMD->cmd[SPEC_HLT]=(pFG->hlt)<<1; /* head load time */ + if(pCMD->dma==0) + pCMD->cmd[SPEC_HLT]|=0x1; /* no dma */ + pCMD->cmdlen=FDC_CMD_SPECIFY_LEN; + pCMD->resultlen=0; /* no result */ + break; + case FDC_CMD_DUMP_REG: + pCMD->cmdlen=FDC_CMD_DUMP_REG_LEN; + pCMD->resultlen=10; /* 10 byte result */ + break; + case FDC_CMD_READ_ID: + pCMD->cmd[COMMAND]|=(FDC_MFM_MODE<<6); /* set MFM bit */ + pCMD->cmdlen=FDC_CMD_READ_ID_LEN; + pCMD->resultlen=7; /* 7 byte result */ + break; + case FDC_CMD_RECALIBRATE: + pCMD->cmd[DRIVE]&=0x03; /* don't set the head bit */ + pCMD->cmdlen=FDC_CMD_RECALIBRATE_LEN; + pCMD->resultlen=0; /* no result */ + break; + break; + case FDC_CMD_SENSE_INT: + pCMD->cmdlen=FDC_CMD_SENSE_INT_LEN; + pCMD->resultlen=2; + break; + } + for(i=0;icmdlen;i++) { + /* PRINTF("write cmd%d = 0x%02X\n",i,pCMD->cmd[i]); */ + if(write_fdc_byte(pCMD->cmd[i])==FALSE) { + PRINTF("Error: timeout while issue cmd%d\n",i); + return FALSE; + } + } + timeout=FDC_TIME_OUT; + for(i=0;iresultlen;i++) { + while((read_fdc_reg(FDC_MSR)&0xC0)!=0xC0) { + timeout--; + if(timeout==0) { + PRINTF(" timeout while reading result%d MSR=0x%02X\n",i,read_fdc_reg(FDC_MSR)); + return FALSE; + } + } + pCMD->result[i]=(unsigned char)read_fdc_byte(); + } + return TRUE; +} + +/* selects the drive assigned in the cmd structur and + switches on the Motor */ +void select_fdc_drive(FDC_COMMAND_STRUCT *pCMD) +{ + unsigned char val; + + val=(1<<(4+pCMD->drive))|pCMD->drive|0xC; /* set reset, dma gate and motor bits */ + if((read_fdc_reg(FDC_DOR)&val)!=val) { + write_fdc_reg(FDC_DOR,val); + for(val=0;val<255;val++) + udelay(500); /* wait some time to start motor */ + } +} + +/* switches off the Motor of the specified drive */ +void stop_fdc_drive(FDC_COMMAND_STRUCT *pCMD) +{ + unsigned char val; + + val=(1<<(4+pCMD->drive))|pCMD->drive; /* sets motor bits */ + write_fdc_reg(FDC_DOR,(read_fdc_reg(FDC_DOR)&~val)); +} + +/* issues a recalibrate command, waits for interrupt and + * issues a sense_interrupt */ +int fdc_recalibrate(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG) +{ + pCMD->cmd[COMMAND]=FDC_CMD_RECALIBRATE; + if(fdc_issue_cmd(pCMD,pFG)==FALSE) + return FALSE; + while(wait_for_fdc_int()!=TRUE); + pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT; + return(fdc_issue_cmd(pCMD,pFG)); +} + +/* issues a recalibrate command, waits for interrupt and + * issues a sense_interrupt */ +int fdc_seek(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG) +{ + pCMD->cmd[COMMAND]=FDC_CMD_SEEK; + if(fdc_issue_cmd(pCMD,pFG)==FALSE) + return FALSE; + while(wait_for_fdc_int()!=TRUE); + pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT; + return(fdc_issue_cmd(pCMD,pFG)); +} + +#ifndef CONFIG_AMIGAONEG3SE +/* terminates current command, by not servicing the FIFO + * waits for interrupt and fills in the result bytes */ +int fdc_terminate(FDC_COMMAND_STRUCT *pCMD) +{ + int i; + for(i=0;i<100;i++) + udelay(500); /* wait 500usec for fifo overrun */ + while((read_fdc_reg(FDC_SRA)&0x80)==0x00); /* wait as long as no int has occured */ + for(i=0;i<7;i++) { + pCMD->result[i]=(unsigned char)read_fdc_byte(); + } + return TRUE; +} +#endif +#ifdef CONFIG_AMIGAONEG3SE +int fdc_terminate(FDC_COMMAND_STRUCT *pCMD) +{ + int i; + for(i=0;i<100;i++) + udelay(500); /* wait 500usec for fifo overrun */ + while((INT6_Status&0x80)==0x00); /* wait as long as no int has occured */ + for(i=0;i<7;i++) { + pCMD->result[i]=(unsigned char)read_fdc_byte(); + } + INT6_Status = 0; + return TRUE; +} + +#endif + +#ifdef CONFIG_AMIGAONEG3SE +#define disable_interrupts() 0 +#define enable_interrupts() (void)0 +#endif + +/* reads data from FDC, seek commands are issued automatic */ +int fdc_read_data(unsigned char *buffer, unsigned long blocks,FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) +{ + /* first seek to start address */ + unsigned long len,lastblk,readblk,i,timeout,ii,offset; + unsigned char pcn,c,retriesrw,retriescal; + unsigned char *bufferw; /* working buffer */ + int sect_size; + int flags; + + flags=disable_interrupts(); /* switch off all Interrupts */ + select_fdc_drive(pCMD); /* switch on drive */ + sect_size=0x080<sect_code; + retriesrw=0; + retriescal=0; + offset=0; + if(fdc_seek(pCMD,pFG)==FALSE) { + stop_fdc_drive(pCMD); + enable_interrupts(); + return FALSE; + } + if((pCMD->result[STATUS_0]&0x20)!=0x20) { + printf("Seek error Status: %02X\n",pCMD->result[STATUS_0]); + stop_fdc_drive(pCMD); + enable_interrupts(); + return FALSE; + } + pcn=pCMD->result[STATUS_PCN]; /* current track */ + /* now determine the next seek point */ + lastblk=pCMD->blnr + blocks; + /* readblk=(pFG->head*pFG->sect)-(pCMD->blnr%(pFG->head*pFG->sect)); */ + readblk=pFG->sect-(pCMD->blnr%pFG->sect); + PRINTF("1st nr of block possible read %ld start %ld\n",readblk,pCMD->blnr); + if(readblk>blocks) /* is end within 1st track */ + readblk=blocks; /* yes, correct it */ + PRINTF("we read %ld blocks start %ld\n",readblk,pCMD->blnr); + bufferw=&buffer[0]; /* setup working buffer */ + do { +retryrw: + len=sect_size * readblk; + pCMD->cmd[COMMAND]=FDC_CMD_READ; + if(fdc_issue_cmd(pCMD,pFG)==FALSE) { + stop_fdc_drive(pCMD); + enable_interrupts(); + return FALSE; + } + for (i=0;i6) { + for(ii=0;ii<7;ii++) { + pCMD->result[ii]=bufferw[(i-7+ii)]; + } /* for */ + } + if(retriesrw++>FDC_RW_RETRIES) { + if (retriescal++>FDC_CAL_RETRIES) { + stop_fdc_drive(pCMD); + enable_interrupts(); + return FALSE; + } + else { + PRINTF(" trying to recalibrate Try %d\n",retriescal); + if(fdc_recalibrate(pCMD,pFG)==FALSE) { + stop_fdc_drive(pCMD); + enable_interrupts(); + return FALSE; + } + retriesrw=0; + goto retrycal; + } /* else >FDC_CAL_RETRIES */ + } + else { + PRINTF("Read retry %d\n",retriesrw); + goto retryrw; + } /* else >FDC_RW_RETRIES */ + }/* if output */ + timeout--; + }while(TRUE); + } /* for len */ + /* the last sector of a track or all data has been read, + * we need to get the results */ + fdc_terminate(pCMD); + offset+=(sect_size*readblk); /* set up buffer pointer */ + bufferw=&buffer[offset]; + pCMD->blnr+=readblk; /* update current block nr */ + blocks-=readblk; /* update blocks */ + if(blocks==0) + break; /* we are finish */ + /* setup new read blocks */ + /* readblk=pFG->head*pFG->sect; */ + readblk=pFG->sect; + if(readblk>blocks) + readblk=blocks; +retrycal: + /* a seek is necessary */ + if(fdc_seek(pCMD,pFG)==FALSE) { + stop_fdc_drive(pCMD); + enable_interrupts(); + return FALSE; + } + if((pCMD->result[STATUS_0]&0x20)!=0x20) { + PRINTF("Seek error Status: %02X\n",pCMD->result[STATUS_0]); + stop_fdc_drive(pCMD); + return FALSE; + } + pcn=pCMD->result[STATUS_PCN]; /* current track */ + }while(TRUE); /* start over */ + stop_fdc_drive(pCMD); /* switch off drive */ + enable_interrupts(); + return TRUE; +} + +#ifdef CONFIG_AMIGAONEG3SE +#undef disable_interrupts() +#undef enable_interrupts() +#endif + +/* Scan all drives and check if drive is present and disk is inserted */ +int fdc_check_drive(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) +{ + int i,drives,state; + /* OK procedure of data book is satisfied. + * trying to get some information over the drives */ + state=0; /* no drives, no disks */ + for(drives=0;drives<4;drives++) { + pCMD->drive=drives; + select_fdc_drive(pCMD); + pCMD->blnr=0; /* set to the 1st block */ + if(fdc_recalibrate(pCMD,pFG)==FALSE) + continue; + if((pCMD->result[STATUS_0]&0x10)==0x10) + continue; + /* ok drive connected check for disk */ + state|=(1<blnr=pFG->size; /* set to the last block */ + if(fdc_seek(pCMD,pFG)==FALSE) + continue; + pCMD->blnr=0; /* set to the 1st block */ + if(fdc_recalibrate(pCMD,pFG)==FALSE) + continue; + pCMD->cmd[COMMAND]=FDC_CMD_READ_ID; + if(fdc_issue_cmd(pCMD,pFG)==FALSE) + continue; + state|=(0x10<name : ""); + } + pCMD->flags=state; + return TRUE; +} + + +/************************************************************************** +* int fdc_setup +* setup the fdc according the datasheet +* assuming in PS2 Mode +*/ +int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) +{ + int i; + +#ifdef CONFIG_AMIGAONEG3SE + irq_install_handler(6, (interrupt_handler_t *)fdc_interrupt, NULL); + i8259_unmask_irq(6); +#endif + +#ifdef CFG_FDC_HW_INIT + fdc_hw_init (); +#endif + /* first, we reset the FDC via the DOR */ + write_fdc_reg(FDC_DOR,0x00); + for(i=0; i<255; i++) /* then we wait some time */ + udelay(500); + /* then, we clear the reset in the DOR */ + pCMD->drive=drive; + select_fdc_drive(pCMD); + /* initialize the CCR */ + write_fdc_reg(FDC_CCR,pFG->rate); + /* then initialize the DSR */ + write_fdc_reg(FDC_DSR,pFG->rate); + if(wait_for_fdc_int()==FALSE) { + PRINTF("Time Out after writing CCR\n"); + return FALSE; + } + /* now issue sense Interrupt and status command + * assuming only one drive present (drive 0) */ + pCMD->dma=0; /* we don't use any dma at all */ + for(i=0;i<4;i++) { + /* issue sense interrupt for all 4 possible drives */ + pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT; + if(fdc_issue_cmd(pCMD,pFG)==FALSE) { + PRINTF("Sense Interrupt for drive %d failed\n",i); + } + } + /* issue the configure command */ + pCMD->drive=drive; + select_fdc_drive(pCMD); + pCMD->cmd[COMMAND]=FDC_CMD_CONFIGURE; + if(fdc_issue_cmd(pCMD,pFG)==FALSE) { + PRINTF(" configure timeout\n"); + stop_fdc_drive(pCMD); + return FALSE; + } + /* issue specify command */ + pCMD->cmd[COMMAND]=FDC_CMD_SPECIFY; + if(fdc_issue_cmd(pCMD,pFG)==FALSE) { + PRINTF(" specify timeout\n"); + stop_fdc_drive(pCMD); + return FALSE; + + } + /* then, we clear the reset in the DOR */ + /* fdc_check_drive(pCMD,pFG); */ + /* write_fdc_reg(FDC_DOR,0x04); */ + + return TRUE; +} +#endif /* ((CONFIG_COMMANDS & CFG_CMD_FDC)||(CONFIG_COMMANDS & CFG_CMD_FDOS))*/ + +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) + +/* Low level functions for the Floppy-DOS layer */ + +/************************************************************************** +* int fdc_fdos_init +* initialize the FDC layer +* +*/ +int fdc_fdos_init (int drive) +{ + FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; + FDC_COMMAND_STRUCT *pCMD = &cmd; + + /* setup FDC and scan for drives */ + if(fdc_setup(drive,pCMD,pFG)==FALSE) { + printf("\n** Error in setup FDC **\n"); + return FALSE; + } + if(fdc_check_drive(pCMD,pFG)==FALSE) { + printf("\n** Error in check_drives **\n"); + return FALSE; + } + if((pCMD->flags&(1<flags&(0x10<drive=drive; + + /* read first block */ + pCMD->blnr=0; + return TRUE; +} +/************************************************************************** +* int fdc_fdos_seek +* parameter is a block number +*/ +int fdc_fdos_seek (int where) +{ + FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; + FDC_COMMAND_STRUCT *pCMD = &cmd; + + pCMD -> blnr = where ; + return (fdc_seek (pCMD, pFG)); +} +/************************************************************************** +* int fdc_fdos_read +* the length is in block number +*/ +int fdc_fdos_read (void *buffer, int len) +{ + FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; + FDC_COMMAND_STRUCT *pCMD = &cmd; + + return (fdc_read_data (buffer, len, pCMD, pFG)); +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_FDOS) */ + +#if (CONFIG_COMMANDS & CFG_CMD_FDC) +/**************************************************************************** + * main routine do_fdcboot + */ +int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type; + FDC_COMMAND_STRUCT *pCMD = &cmd; + unsigned long addr,imsize; + image_header_t *hdr; /* used for fdc boot */ + unsigned char boot_drive; + int i,nrofblk; + char *ep; + int rcode = 0; + + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_drive=CFG_FDC_DRIVE_NUMBER; + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_drive=CFG_FDC_DRIVE_NUMBER; + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_drive=simple_strtoul(argv[2], NULL, 10); + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + /* setup FDC and scan for drives */ + if(fdc_setup(boot_drive,pCMD,pFG)==FALSE) { + printf("\n** Error in setup FDC **\n"); + return 1; + } + if(fdc_check_drive(pCMD,pFG)==FALSE) { + printf("\n** Error in check_drives **\n"); + return 1; + } + if((pCMD->flags&(1<flags&(0x10<drive=boot_drive; + /* read first block */ + pCMD->blnr=0; + if(fdc_read_data((unsigned char *)addr,1,pCMD,pFG)==FALSE) { + printf("\nRead error:"); + for(i=0;i<7;i++) + printf("result%d: 0x%02X\n",i,pCMD->result[i]); + return 1; + } + hdr = (image_header_t *)addr; + if (hdr->ih_magic != IH_MAGIC) { + printf ("Bad Magic Number\n"); + return 1; + } + print_image_hdr(hdr); + + imsize= hdr->ih_size+sizeof(image_header_t); + nrofblk=imsize/512; + if((imsize%512)>0) + nrofblk++; + printf("Loading %ld Bytes (%d blocks) at 0x%08lx..\n",imsize,nrofblk,addr); + pCMD->blnr=0; + if(fdc_read_data((unsigned char *)addr,nrofblk,pCMD,pFG)==FALSE) { + /* read image block */ + printf("\nRead error:"); + for(i=0;i<7;i++) + printf("result%d: 0x%02X\n",i,pCMD->result[i]); + return 1; + } + printf("OK %ld Bytes loaded.\n",imsize); + + flush_cache (addr, imsize); + /* Loading ok, update default load address */ + + load_addr = addr; + if(hdr->ih_type == IH_TYPE_KERNEL) { + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { + char *local_args[2]; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + + local_args[0] = argv[0]; + local_args[1] = NULL; + + printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); + + do_bootm (cmdtp, 0, 1, local_args); + rcode ++; + } + } + return rcode; +} + + +#endif /* CONFIG_COMMANDS & CFG_CMD_FDC */ + + +/***************************************************/ + + +#if (CONFIG_COMMANDS & CFG_CMD_FDC) + +U_BOOT_CMD( + fdcboot, 3, 1, do_fdcboot, + "fdcboot - boot from floppy device\n", + "loadAddr drive\n" +); +#endif diff --git a/common/cmd_fdos.c b/common/cmd_fdos.c new file mode 100644 index 0000000..dc02b35 --- /dev/null +++ b/common/cmd_fdos.c @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Dos floppy support + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) + +/*----------------------------------------------------------------------------- + * do_fdosboot -- + *----------------------------------------------------------------------------- + */ +int do_fdosboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *name; + char *ep; + int size; + int rcode = 0; + char buf [12]; + int drive = CFG_FDC_DRIVE_NUMBER; + + /* pre-set load_addr */ + if ((ep = getenv("loadaddr")) != NULL) { + load_addr = simple_strtoul(ep, NULL, 16); + } + + /* pre-set Boot file name */ + if ((name = getenv("bootfile")) == NULL) { + name = "uImage"; + } + + switch (argc) { + case 1: + break; + case 2: + /* only one arg - accept two forms: + * just load address, or just boot file name. + * The latter form must be written "filename" here. + */ + if (argv[1][0] == '"') { /* just boot filename */ + name = argv [1]; + } else { /* load address */ + load_addr = simple_strtoul(argv[1], NULL, 16); + } + break; + case 3: + load_addr = simple_strtoul(argv[1], NULL, 16); + name = argv [2]; + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + break; + } + + /* Init physical layer */ + if (!fdc_fdos_init (drive)) { + return (-1); + } + + /* Open file */ + if (dos_open (name) < 0) { + printf ("Unable to open %s\n", name); + return 1; + } + if ((size = dos_read (load_addr)) < 0) { + printf ("boot error\n"); + return 1; + } + flush_cache (load_addr, size); + + sprintf(buf, "%x", size); + setenv("filesize", buf); + + printf("Floppy DOS load complete: %d bytes loaded to 0x%lx\n", + size, load_addr); + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { + char *local_args[2]; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + local_args[0] = argv[0]; + local_args[1] = NULL; + printf ("Automatic boot of image at addr 0x%08lX ...\n", load_addr); + rcode = do_bootm (cmdtp, 0, 1, local_args); + } + return rcode; +} + +/*----------------------------------------------------------------------------- + * do_fdosls -- + *----------------------------------------------------------------------------- + */ +int do_fdosls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *path = ""; + int drive = CFG_FDC_DRIVE_NUMBER; + + switch (argc) { + case 1: + break; + case 2: + path = argv [1]; + break; + } + + /* Init physical layer */ + if (!fdc_fdos_init (drive)) { + return (-1); + } + /* Open directory */ + if (dos_open (path) < 0) { + printf ("Unable to open %s\n", path); + return 1; + } + return (dos_dir ()); +} + +U_BOOT_CMD( + fdosboot, 3, 0, do_fdosboot, + "fdosboot- boot from a dos floppy file\n", + "[loadAddr] [filename]\n" +); + +U_BOOT_CMD( + fdosls, 2, 0, do_fdosls, + "fdosls - list files in a directory\n", + "[directory]\n" +); + +#endif /* CONFIG_COMMANDS & CFG_CMD_FDOS */ diff --git a/common/cmd_flash.c b/common/cmd_flash.c new file mode 100644 index 0000000..0aa4783 --- /dev/null +++ b/common/cmd_flash.c @@ -0,0 +1,735 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * FLASH support + */ +#include +#include + +#ifdef CONFIG_HAS_DATAFLASH +#include +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#include + +/* parition handling routines */ +int mtdparts_init(void); +int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num); +int find_dev_and_part(const char *id, struct mtd_device **dev, + u8 *part_num, struct part_info **part); +#endif + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +/* + * The user interface starts numbering for Flash banks with 1 + * for historical reasons. + */ + +/* + * this routine looks for an abbreviated flash range specification. + * the syntax is B:SF[-SL], where B is the bank number, SF is the first + * sector to erase, and SL is the last sector to erase (defaults to SF). + * bank numbers start at 1 to be consistent with other specs, sector numbers + * start at zero. + * + * returns: 1 - correct spec; *pinfo, *psf and *psl are + * set appropriately + * 0 - doesn't look like an abbreviated spec + * -1 - looks like an abbreviated spec, but got + * a parsing error, a number out of range, + * or an invalid flash bank. + */ +static int +abbrev_spec (char *str, flash_info_t ** pinfo, int *psf, int *psl) +{ + flash_info_t *fp; + int bank, first, last; + char *p, *ep; + + if ((p = strchr (str, ':')) == NULL) + return 0; + *p++ = '\0'; + + bank = simple_strtoul (str, &ep, 10); + if (ep == str || *ep != '\0' || + bank < 1 || bank > CFG_MAX_FLASH_BANKS || + (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN) + return -1; + + str = p; + if ((p = strchr (str, '-')) != NULL) + *p++ = '\0'; + + first = simple_strtoul (str, &ep, 10); + if (ep == str || *ep != '\0' || first >= fp->sector_count) + return -1; + + if (p != NULL) { + last = simple_strtoul (p, &ep, 10); + if (ep == p || *ep != '\0' || + last < first || last >= fp->sector_count) + return -1; + } else { + last = first; + } + + *pinfo = fp; + *psf = first; + *psl = last; + + return 1; +} + +/* + * This function computes the start and end addresses for both + * erase and protect commands. The range of the addresses on which + * either of the commands is to operate can be given in two forms: + * 1. start end - operate on <'start', 'end') + * 2. start +length - operate on <'start', start + length) + * If the second form is used and the end address doesn't fall on the + * sector boundary, than it will be adjusted to the next sector boundary. + * If it isn't in the flash, the function will fail (return -1). + * Input: + * arg1, arg2: address specification (i.e. both command arguments) + * Output: + * addr_first, addr_last: computed address range + * Return: + * 1: success + * -1: failure (bad format, bad address). +*/ +static int +addr_spec(char *arg1, char *arg2, ulong *addr_first, ulong *addr_last) +{ + char len_used = 0; /* indicates if the "start +length" form used */ + char *ep; + + *addr_first = simple_strtoul(arg1, &ep, 16); + if (ep == arg1 || *ep != '\0') + return -1; + + if (arg2 && *arg2 == '+'){ + len_used = 1; + ++arg2; + } + + *addr_last = simple_strtoul(arg2, &ep, 16); + if (ep == arg2 || *ep != '\0') + return -1; + + if (len_used){ + char found = 0; + ulong bank; + + /* + * *addr_last has the length, compute correct *addr_last + * XXX watch out for the integer overflow! Right now it is + * checked for in both the callers. + */ + *addr_last = *addr_first + *addr_last - 1; + + /* + * It may happen that *addr_last doesn't fall on the sector + * boundary. We want to round such an address to the next + * sector boundary, so that the commands don't fail later on. + */ + + /* find the end addr of the sector where the *addr_last is */ + for (bank = 0; bank < CFG_MAX_FLASH_BANKS && !found; ++bank){ + int i; + flash_info_t *info = &flash_info[bank]; + for (i = 0; i < info->sector_count && !found; ++i){ + /* get the end address of the sector */ + ulong sector_end_addr; + if (i == info->sector_count - 1){ + sector_end_addr = + info->start[0] + info->size - 1; + } else { + sector_end_addr = + info->start[i+1] - 1; + } + if (*addr_last <= sector_end_addr && + *addr_last >= info->start[i]){ + /* sector found */ + found = 1; + /* adjust *addr_last if necessary */ + if (*addr_last < sector_end_addr){ + *addr_last = sector_end_addr; + } + } + } /* sector */ + } /* bank */ + if (!found){ + /* error, addres not in flash */ + printf("Error: end address (0x%08lx) not in flash!\n", + *addr_last); + return -1; + } + } /* "start +length" from used */ + + return 1; +} + +static int +flash_fill_sect_ranges (ulong addr_first, ulong addr_last, + int *s_first, int *s_last, + int *s_count ) +{ + flash_info_t *info; + ulong bank; + int rcode = 0; + + *s_count = 0; + + for (bank=0; bank < CFG_MAX_FLASH_BANKS; ++bank) { + s_first[bank] = -1; /* first sector to erase */ + s_last [bank] = -1; /* last sector to erase */ + } + + for (bank=0,info=&flash_info[0]; + (bank < CFG_MAX_FLASH_BANKS) && (addr_first <= addr_last); + ++bank, ++info) { + ulong b_end; + int sect; + short s_end; + + if (info->flash_id == FLASH_UNKNOWN) { + continue; + } + + b_end = info->start[0] + info->size - 1; /* bank end addr */ + s_end = info->sector_count - 1; /* last sector */ + + + for (sect=0; sect < info->sector_count; ++sect) { + ulong end; /* last address in current sect */ + + end = (sect == s_end) ? b_end : info->start[sect + 1] - 1; + + if (addr_first > end) + continue; + if (addr_last < info->start[sect]) + continue; + + if (addr_first == info->start[sect]) { + s_first[bank] = sect; + } + if (addr_last == end) { + s_last[bank] = sect; + } + } + if (s_first[bank] >= 0) { + if (s_last[bank] < 0) { + if (addr_last > b_end) { + s_last[bank] = s_end; + } else { + puts ("Error: end address" + " not on sector boundary\n"); + rcode = 1; + break; + } + } + if (s_last[bank] < s_first[bank]) { + puts ("Error: end sector" + " precedes start sector\n"); + rcode = 1; + break; + } + sect = s_last[bank]; + addr_first = (sect == s_end) ? b_end + 1: info->start[sect + 1]; + (*s_count) += s_last[bank] - s_first[bank] + 1; + } else if (addr_first >= info->start[0] && addr_first < b_end) { + puts ("Error: start address not on sector boundary\n"); + rcode = 1; + break; + } else if (s_last[bank] >= 0) { + puts ("Error: cannot span across banks when they are" + " mapped in reverse order\n"); + rcode = 1; + break; + } + } + + return rcode; +} + +int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong bank; + +#ifdef CONFIG_HAS_DATAFLASH + dataflash_print_info(); +#endif + + if (argc == 1) { /* print info for all FLASH banks */ + for (bank=0; bank CFG_MAX_FLASH_BANKS)) { + printf ("Only FLASH Banks # 1 ... # %d supported\n", + CFG_MAX_FLASH_BANKS); + return 1; + } + printf ("\nBank # %ld: ", bank); + flash_print_info (&flash_info[bank-1]); + return 0; +} + +int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + flash_info_t *info; + ulong bank, addr_first, addr_last; + int n, sect_first, sect_last; +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + struct mtd_device *dev; + struct part_info *part; + u8 dev_type, dev_num, pnum; +#endif + int rcode = 0; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "all") == 0) { + for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) { + printf ("Erase Flash Bank # %ld ", bank); + info = &flash_info[bank-1]; + rcode = flash_erase (info, 0, info->sector_count-1); + } + return rcode; + } + + if ((n = abbrev_spec(argv[1], &info, §_first, §_last)) != 0) { + if (n < 0) { + puts ("Bad sector specification\n"); + return 1; + } + printf ("Erase Flash Sectors %d-%d in Bank # %d ", + sect_first, sect_last, (info-flash_info)+1); + rcode = flash_erase(info, sect_first, sect_last); + return rcode; + } + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + /* erase - erase partition */ + if ((argc == 2) && (id_parse(argv[1], NULL, &dev_type, &dev_num) == 0)) { + mtdparts_init(); + if (find_dev_and_part(argv[1], &dev, &pnum, &part) == 0) { + if (dev->id->type == MTD_DEV_TYPE_NOR) { + bank = dev->id->num; + info = &flash_info[bank]; + addr_first = part->offset + info->start[0]; + addr_last = addr_first + part->size - 1; + + printf ("Erase Flash Parition %s, " + "bank %d, 0x%08lx - 0x%08lx ", + argv[1], bank, addr_first, + addr_last); + + rcode = flash_sect_erase(addr_first, addr_last); + return rcode; + } + + printf("cannot erase, not a NOR device\n"); + return 1; + } + } +#endif + + if (argc != 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "bank") == 0) { + bank = simple_strtoul(argv[2], NULL, 16); + if ((bank < 1) || (bank > CFG_MAX_FLASH_BANKS)) { + printf ("Only FLASH Banks # 1 ... # %d supported\n", + CFG_MAX_FLASH_BANKS); + return 1; + } + printf ("Erase Flash Bank # %ld ", bank); + info = &flash_info[bank-1]; + rcode = flash_erase (info, 0, info->sector_count-1); + return rcode; + } + + if (addr_spec(argv[1], argv[2], &addr_first, &addr_last) < 0){ + printf ("Bad address format\n"); + return 1; + } + + if (addr_first >= addr_last) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + rcode = flash_sect_erase(addr_first, addr_last); + return rcode; +} + +int flash_sect_erase (ulong addr_first, ulong addr_last) +{ + flash_info_t *info; + ulong bank; +#ifdef CFG_MAX_FLASH_BANKS_DETECT + int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT]; +#else + int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS]; +#endif + int erased = 0; + int planned; + int rcode = 0; + + rcode = flash_fill_sect_ranges (addr_first, addr_last, + s_first, s_last, &planned ); + + if (planned && (rcode == 0)) { + for (bank=0,info=&flash_info[0]; + (bank < CFG_MAX_FLASH_BANKS) && (rcode == 0); + ++bank, ++info) { + if (s_first[bank]>=0) { + erased += s_last[bank] - s_first[bank] + 1; + debug ("Erase Flash from 0x%08lx to 0x%08lx " + "in Bank # %ld ", + info->start[s_first[bank]], + (s_last[bank] == info->sector_count) ? + info->start[0] + info->size - 1: + info->start[s_last[bank]+1] - 1, + bank+1); + rcode = flash_erase (info, s_first[bank], s_last[bank]); + } + } + printf ("Erased %d sectors\n", erased); + } else if (rcode == 0) { + puts ("Error: start and/or end address" + " not on sector boundary\n"); + rcode = 1; + } + return rcode; +} + +int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + flash_info_t *info; + ulong bank, addr_first, addr_last; + int i, p, n, sect_first, sect_last; +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + struct mtd_device *dev; + struct part_info *part; + u8 dev_type, dev_num, pnum; +#endif + int rcode = 0; +#ifdef CONFIG_HAS_DATAFLASH + int status; +#endif + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "off") == 0) { + p = 0; + } else if (strcmp(argv[1], "on") == 0) { + p = 1; + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + +#ifdef CONFIG_HAS_DATAFLASH + if ((strcmp(argv[2], "all") != 0) && (strcmp(argv[2], "bank") != 0)) { + addr_first = simple_strtoul(argv[2], NULL, 16); + addr_last = simple_strtoul(argv[3], NULL, 16); + + if (addr_dataflash(addr_first) && addr_dataflash(addr_last)) { + status = dataflash_real_protect(p,addr_first,addr_last); + if (status < 0){ + puts ("Bad DataFlash sector specification\n"); + return 1; + } + printf("%sProtect %d DataFlash Sectors\n", + p ? "" : "Un-", status); + return 0; + } + } +#endif + + if (strcmp(argv[2], "all") == 0) { + for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) { + info = &flash_info[bank-1]; + if (info->flash_id == FLASH_UNKNOWN) { + continue; + } + printf ("%sProtect Flash Bank # %ld\n", + p ? "" : "Un-", bank); + + for (i=0; isector_count; ++i) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, i, p)) + rcode = 1; + putc ('.'); +#else + info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ + } + } + +#if defined(CFG_FLASH_PROTECTION) + if (!rcode) puts (" done\n"); +#endif /* CFG_FLASH_PROTECTION */ + + return rcode; + } + + if ((n = abbrev_spec(argv[2], &info, §_first, §_last)) != 0) { + if (n < 0) { + puts ("Bad sector specification\n"); + return 1; + } + printf("%sProtect Flash Sectors %d-%d in Bank # %d\n", + p ? "" : "Un-", sect_first, sect_last, + (info-flash_info)+1); + for (i = sect_first; i <= sect_last; i++) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, i, p)) + rcode = 1; + putc ('.'); +#else + info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ + } + +#if defined(CFG_FLASH_PROTECTION) + if (!rcode) puts (" done\n"); +#endif /* CFG_FLASH_PROTECTION */ + + return rcode; + } + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + /* protect on/off */ + if ((argc == 3) && (id_parse(argv[2], NULL, &dev_type, &dev_num) == 0)) { + mtdparts_init(); + if (find_dev_and_part(argv[2], &dev, &pnum, &part) == 0) { + if (dev->id->type == MTD_DEV_TYPE_NOR) { + bank = dev->id->num; + info = &flash_info[bank]; + addr_first = part->offset + info->start[0]; + addr_last = addr_first + part->size - 1; + + printf ("%sProtect Flash Parition %s, " + "bank %d, 0x%08lx - 0x%08lx\n", + p ? "" : "Un", argv[1], + bank, addr_first, addr_last); + + rcode = flash_sect_protect (p, addr_first, addr_last); + return rcode; + } + + printf("cannot %sprotect, not a NOR device\n", + p ? "" : "un"); + return 1; + } + } +#endif + + if (argc != 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[2], "bank") == 0) { + bank = simple_strtoul(argv[3], NULL, 16); + if ((bank < 1) || (bank > CFG_MAX_FLASH_BANKS)) { + printf ("Only FLASH Banks # 1 ... # %d supported\n", + CFG_MAX_FLASH_BANKS); + return 1; + } + printf ("%sProtect Flash Bank # %ld\n", + p ? "" : "Un-", bank); + info = &flash_info[bank-1]; + + if (info->flash_id == FLASH_UNKNOWN) { + puts ("missing or unknown FLASH type\n"); + return 1; + } + for (i=0; isector_count; ++i) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, i, p)) + rcode = 1; + putc ('.'); +#else + info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ + } + +#if defined(CFG_FLASH_PROTECTION) + if (!rcode) puts (" done\n"); +#endif /* CFG_FLASH_PROTECTION */ + + return rcode; + } + + if (addr_spec(argv[2], argv[3], &addr_first, &addr_last) < 0){ + printf("Bad address format\n"); + return 1; + } + + if (addr_first >= addr_last) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + rcode = flash_sect_protect (p, addr_first, addr_last); + return rcode; +} + + +int flash_sect_protect (int p, ulong addr_first, ulong addr_last) +{ + flash_info_t *info; + ulong bank; +#ifdef CFG_MAX_FLASH_BANKS_DETECT + int s_first[CFG_MAX_FLASH_BANKS_DETECT], s_last[CFG_MAX_FLASH_BANKS_DETECT]; +#else + int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS]; +#endif + int protected, i; + int planned; + int rcode; + + rcode = flash_fill_sect_ranges( addr_first, addr_last, s_first, s_last, &planned ); + + protected = 0; + + if (planned && (rcode == 0)) { + for (bank=0,info=&flash_info[0]; bank < CFG_MAX_FLASH_BANKS; ++bank, ++info) { + if (info->flash_id == FLASH_UNKNOWN) { + continue; + } + + if (s_first[bank]>=0 && s_first[bank]<=s_last[bank]) { + debug ("%sProtecting sectors %d..%d in bank %ld\n", + p ? "" : "Un-", + s_first[bank], s_last[bank], bank+1); + protected += s_last[bank] - s_first[bank] + 1; + for (i=s_first[bank]; i<=s_last[bank]; ++i) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, i, p)) + rcode = 1; + putc ('.'); +#else + info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ + } + } +#if defined(CFG_FLASH_PROTECTION) + if (!rcode) putc ('\n'); +#endif /* CFG_FLASH_PROTECTION */ + } + + printf ("%sProtected %d sectors\n", + p ? "" : "Un-", protected); + } else if (rcode == 0) { + puts ("Error: start and/or end address" + " not on sector boundary\n"); + rcode = 1; + } + return rcode; +} + + +/**************************************************/ +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +# define TMP_ERASE "erase \n - erase partition\n" +# define TMP_PROT_ON "protect on \n - protect partition\n" +# define TMP_PROT_OFF "protect off \n - make partition writable\n" +#else +# define TMP_ERASE /* empty */ +# define TMP_PROT_ON /* empty */ +# define TMP_PROT_OFF /* empty */ +#endif + +U_BOOT_CMD( + flinfo, 2, 1, do_flinfo, + "flinfo - print FLASH memory information\n", + "\n - print information for all FLASH memory banks\n" + "flinfo N\n - print information for FLASH memory bank # N\n" +); + +U_BOOT_CMD( + erase, 3, 1, do_flerase, + "erase - erase FLASH memory\n", + "start end\n" + " - erase FLASH from addr 'start' to addr 'end'\n" + "erase start +len\n" + " - erase FLASH from addr 'start' to the end of sect " + "w/addr 'start'+'len'-1\n" + "erase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n" + "erase bank N\n - erase FLASH bank # N\n" + TMP_ERASE + "erase all\n - erase all FLASH banks\n" +); + +U_BOOT_CMD( + protect, 4, 1, do_protect, + "protect - enable or disable FLASH write protection\n", + "on start end\n" + " - protect FLASH from addr 'start' to addr 'end'\n" + "protect on start +len\n" + " - protect FLASH from addr 'start' to end of sect " + "w/addr 'start'+'len'-1\n" + "protect on N:SF[-SL]\n" + " - protect sectors SF-SL in FLASH bank # N\n" + "protect on bank N\n - protect FLASH bank # N\n" + TMP_PROT_ON + "protect on all\n - protect all FLASH banks\n" + "protect off start end\n" + " - make FLASH from addr 'start' to addr 'end' writable\n" + "protect off start +len\n" + " - make FLASH from addr 'start' to end of sect " + "w/addr 'start'+'len'-1 wrtable\n" + "protect off N:SF[-SL]\n" + " - make sectors SF-SL writable in FLASH bank # N\n" + "protect off bank N\n - make FLASH bank # N writable\n" + TMP_PROT_OFF + "protect off all\n - make all FLASH banks writable\n" +); + +#undef TMP_ERASE +#undef TMP_PROT_ON +#undef TMP_PROT_OFF + +#endif /* CFG_CMD_FLASH */ diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c new file mode 100644 index 0000000..9a01e7d --- /dev/null +++ b/common/cmd_fpga.c @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2000, 2001 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * FPGA support + */ +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#include +#endif +#include +#include + +#if 0 +#define FPGA_DEBUG +#endif + +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#if defined (CONFIG_FPGA) && ( CONFIG_COMMANDS & CFG_CMD_FPGA ) + +/* Local functions */ +static void fpga_usage (cmd_tbl_t * cmdtp); +static int fpga_get_op (char *opstr); + +/* Local defines */ +#define FPGA_NONE -1 +#define FPGA_INFO 0 +#define FPGA_LOAD 1 +#define FPGA_LOADB 2 +#define FPGA_DUMP 3 + +/* Convert bitstream data and load into the fpga */ +int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) +{ + unsigned int length; + unsigned char* swapdata; + unsigned int swapsize; + char buffer[80]; + unsigned char *ptr; + unsigned char *dataptr; + unsigned char data; + unsigned int i; + int rc; + + dataptr = (unsigned char *)fpgadata; + +#if CFG_FPGA_XILINX + /* skip the first bytes of the bitsteam, their meaning is unknown */ + length = (*dataptr << 8) + *(dataptr+1); + dataptr+=2; + dataptr+=length; + + /* get design name (identifier, length, string) */ + length = (*dataptr << 8) + *(dataptr+1); + dataptr+=2; + if (*dataptr++ != 0x61) { + PRINTF ("%s: Design name identifier not recognized in bitstream\n", + __FUNCTION__ ); + return FPGA_FAIL; + } + + length = (*dataptr << 8) + *(dataptr+1); + dataptr+=2; + for(i=0;i= size) { + printf("%s: Could not find right length of data in bitstream\n", + __FUNCTION__); + return FPGA_FAIL; + } + + /* allocate memory */ + swapdata = (unsigned char *)malloc(swapsize); + if (swapdata == NULL) { + printf("%s: Could not allocate %d bytes memory !\n", + __FUNCTION__, swapsize); + return FPGA_FAIL; + } + + /* read data into memory and swap bits */ + ptr = swapdata; + for (i = 0; i < swapsize; i++) { + data = 0x00; + data |= (*dataptr & 0x01) << 7; + data |= (*dataptr & 0x02) << 5; + data |= (*dataptr & 0x04) << 3; + data |= (*dataptr & 0x08) << 1; + data |= (*dataptr & 0x10) >> 1; + data |= (*dataptr & 0x20) >> 3; + data |= (*dataptr & 0x40) >> 5; + data |= (*dataptr & 0x80) >> 7; + *ptr++ = data; + dataptr++; + } + + rc = fpga_load(dev, swapdata, swapsize); + free(swapdata); + return rc; +#else + printf("Bitstream support only for Xilinx devices\n"); + return FPGA_FAIL; +#endif +} + +/* ------------------------------------------------------------------------- */ +/* command form: + * fpga + * where op is 'load', 'dump', or 'info' + * If there is no device number field, the fpga environment variable is used. + * If there is no data addr field, the fpgadata environment variable is used. + * The info command requires no data address field. + */ +int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int op, dev = FPGA_INVALID_DEVICE; + size_t data_size = 0; + void *fpga_data = NULL; + char *devstr = getenv ("fpga"); + char *datastr = getenv ("fpgadata"); + int rc = FPGA_FAIL; + + if (devstr) + dev = (int) simple_strtoul (devstr, NULL, 16); + if (datastr) + fpga_data = (void *) simple_strtoul (datastr, NULL, 16); + + switch (argc) { + case 5: /* fpga */ + data_size = simple_strtoul (argv[4], NULL, 16); + case 4: /* fpga */ + fpga_data = (void *) simple_strtoul (argv[3], NULL, 16); + PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data); + case 3: /* fpga */ + dev = (int) simple_strtoul (argv[2], NULL, 16); + PRINTF ("%s: device = %d\n", __FUNCTION__, dev); + /* FIXME - this is a really weak test */ + if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */ + PRINTF ("%s: Assuming buffer pointer in arg 3\n", + __FUNCTION__); + fpga_data = (void *) dev; + PRINTF ("%s: fpga_data = 0x%x\n", + __FUNCTION__, (uint) fpga_data); + dev = FPGA_INVALID_DEVICE; /* reset device num */ + } + case 2: /* fpga */ + op = (int) fpga_get_op (argv[1]); + break; + default: + PRINTF ("%s: Too many or too few args (%d)\n", + __FUNCTION__, argc); + op = FPGA_NONE; /* force usage display */ + break; + } + + switch (op) { + case FPGA_NONE: + fpga_usage (cmdtp); + break; + + case FPGA_INFO: + rc = fpga_info (dev); + break; + + case FPGA_LOAD: + rc = fpga_load (dev, fpga_data, data_size); + break; + + case FPGA_LOADB: + rc = fpga_loadbitstream(dev, fpga_data, data_size); + break; + + case FPGA_DUMP: + rc = fpga_dump (dev, fpga_data, data_size); + break; + + default: + printf ("Unknown operation\n"); + fpga_usage (cmdtp); + break; + } + return (rc); +} + +static void fpga_usage (cmd_tbl_t * cmdtp) +{ + printf ("Usage:\n%s\n", cmdtp->usage); +} + +/* + * Map op to supported operations. We don't use a table since we + * would just have to relocate it from flash anyway. + */ +static int fpga_get_op (char *opstr) +{ + int op = FPGA_NONE; + + if (!strcmp ("info", opstr)) { + op = FPGA_INFO; + } else if (!strcmp ("loadb", opstr)) { + op = FPGA_LOADB; + } else if (!strcmp ("load", opstr)) { + op = FPGA_LOAD; + } else if (!strcmp ("dump", opstr)) { + op = FPGA_DUMP; + } + + if (op == FPGA_NONE) { + printf ("Unknown fpga operation \"%s\"\n", opstr); + } + return op; +} + +U_BOOT_CMD (fpga, 6, 1, do_fpga, + "fpga - loadable FPGA image support\n", + "fpga [operation type] [device number] [image address] [image size]\n" + "fpga operations:\n" + "\tinfo\tlist known device information\n" + "\tload\tLoad device from memory buffer\n" + "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n" + "\tdump\tLoad device to memory buffer\n"); +#endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */ diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c new file mode 100644 index 0000000..c543bb5 --- /dev/null +++ b/common/cmd_i2c.c @@ -0,0 +1,933 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * I2C Functions similar to the standard memory functions. + * + * There are several parameters in many of the commands that bear further + * explanations: + * + * Two of the commands (imm and imw) take a byte/word/long modifier + * (e.g. imm.w specifies the word-length modifier). This was done to + * allow manipulating word-length registers. It was not done on any other + * commands because it was not deemed useful. + * + * {i2c_chip} is the I2C chip address (the first byte sent on the bus). + * Each I2C chip on the bus has a unique address. On the I2C data bus, + * the address is the upper seven bits and the LSB is the "read/write" + * bit. Note that the {i2c_chip} address specified on the command + * line is not shifted up: e.g. a typical EEPROM memory chip may have + * an I2C address of 0x50, but the data put on the bus will be 0xA0 + * for write and 0xA1 for read. This "non shifted" address notation + * matches at least half of the data sheets :-/. + * + * {addr} is the address (or offset) within the chip. Small memory + * chips have 8 bit addresses. Large memory chips have 16 bit + * addresses. Other memory chips have 9, 10, or 11 bit addresses. + * Many non-memory chips have multiple registers and {addr} is used + * as the register index. Some non-memory chips have only one register + * and therefore don't need any {addr} parameter. + * + * The default {addr} parameter is one byte (.1) which works well for + * memories and registers with 8 bits of address space. + * + * You can specify the length of the {addr} field with the optional .0, + * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are + * manipulating a single register device which doesn't use an address + * field, use "0.0" for the address and the ".0" length field will + * suppress the address in the I2C data stream. This also works for + * successive reads using the I2C auto-incrementing memory pointer. + * + * If you are manipulating a large memory with 2-byte addresses, use + * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal). + * + * Then there are the unfortunate memory chips that spill the most + * significant 1, 2, or 3 bits of address into the chip address byte. + * This effectively makes one chip (logically) look like 2, 4, or + * 8 chips. This is handled (awkwardly) by #defining + * CFG_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the + * {addr} field (since .1 is the default, it doesn't actually have to + * be specified). Examples: given a memory chip at I2C chip address + * 0x50, the following would happen... + * imd 50 0 10 display 16 bytes starting at 0x000 + * On the bus: A0 00 A1 ... + * imd 50 100 10 display 16 bytes starting at 0x100 + * On the bus: A2 00 A3 ... + * imd 50 210 10 display 16 bytes starting at 0x210 + * On the bus: A4 10 A5 ... + * This is awfully ugly. It would be nice if someone would think up + * a better way of handling this. + * + * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de). + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) + + +/* Display values from last command. + * Memory modify remembered values are different from display memory. + */ +static uchar i2c_dp_last_chip; +static uint i2c_dp_last_addr; +static uint i2c_dp_last_alen; +static uint i2c_dp_last_length = 0x10; + +static uchar i2c_mm_last_chip; +static uint i2c_mm_last_addr; +static uint i2c_mm_last_alen; + +#if defined(CFG_I2C_NOPROBES) +static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; +#endif + +static int +mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]); +extern int cmd_get_data_size(char* arg, int default_size); + +/* + * Syntax: + * imd {i2c_chip} {addr}{.0, .1, .2} {len} + */ +#define DISP_LINE_LEN 16 + +int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u_char chip; + uint addr, alen, length; + int j, nbytes, linebytes; + + /* We use the last specified parameters, unless new ones are + * entered. + */ + chip = i2c_dp_last_chip; + addr = i2c_dp_last_addr; + alen = i2c_dp_last_alen; + length = i2c_dp_last_length; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((flag & CMD_FLAG_REPEAT) == 0) { + /* + * New command specified. + */ + alen = 1; + + /* + * I2C chip address + */ + chip = simple_strtoul(argv[1], NULL, 16); + + /* + * I2C data address within the chip. This can be 1 or + * 2 bytes long. Some day it might be 3 bytes long :-). + */ + addr = simple_strtoul(argv[2], NULL, 16); + alen = 1; + for(j = 0; j < 8; j++) { + if (argv[2][j] == '.') { + alen = argv[2][j+1] - '0'; + if (alen > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; + } else if (argv[2][j] == '\0') { + break; + } + } + + /* + * If another parameter, it is the length to display. + * Length is the number of objects, not number of bytes. + */ + if (argc > 3) + length = simple_strtoul(argv[3], NULL, 16); + } + + /* + * Print the lines. + * + * We buffer all read data, so we can make sure data is read only + * once. + */ + nbytes = length; + do { + unsigned char linebuf[DISP_LINE_LEN]; + unsigned char *cp; + + linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; + + if(i2c_read(chip, addr, alen, linebuf, linebytes) != 0) { + puts ("Error reading the chip.\n"); + } else { + printf("%04x:", addr); + cp = linebuf; + for (j=0; j 0x7e)) + puts ("."); + else + printf("%c", *cp); + cp++; + } + putc ('\n'); + } + nbytes -= linebytes; + } while (nbytes > 0); + + i2c_dp_last_chip = chip; + i2c_dp_last_addr = addr; + i2c_dp_last_alen = alen; + i2c_dp_last_length = length; + + return 0; +} + +int do_i2c_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return mod_i2c_mem (cmdtp, 1, flag, argc, argv); +} + + +int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return mod_i2c_mem (cmdtp, 0, flag, argc, argv); +} + +/* Write (fill) memory + * + * Syntax: + * imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}] + */ +int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar chip; + ulong addr; + uint alen; + uchar byte; + int count; + int j; + + if ((argc < 4) || (argc > 5)) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* + * Chip is always specified. + */ + chip = simple_strtoul(argv[1], NULL, 16); + + /* + * Address is always specified. + */ + addr = simple_strtoul(argv[2], NULL, 16); + alen = 1; + for(j = 0; j < 8; j++) { + if (argv[2][j] == '.') { + alen = argv[2][j+1] - '0'; + if(alen > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; + } else if (argv[2][j] == '\0') { + break; + } + } + + /* + * Value to write is always specified. + */ + byte = simple_strtoul(argv[3], NULL, 16); + + /* + * Optional count + */ + if(argc == 5) { + count = simple_strtoul(argv[4], NULL, 16); + } else { + count = 1; + } + + while (count-- > 0) { + if(i2c_write(chip, addr++, alen, &byte, 1) != 0) { + puts ("Error writing the chip.\n"); + } + /* + * Wait for the write to complete. The write can take + * up to 10mSec (we allow a little more time). + * + * On some chips, while the write is in progress, the + * chip doesn't respond. This apparently isn't a + * universal feature so we don't take advantage of it. + */ +/* + * No write delay with FRAM devices. + */ +#if !defined(CFG_I2C_FRAM) + udelay(11000); +#endif + +#if 0 + for(timeout = 0; timeout < 10; timeout++) { + udelay(2000); + if(i2c_probe(chip) == 0) + break; + } +#endif + } + + return (0); +} + + +/* Calculate a CRC on memory + * + * Syntax: + * icrc32 {i2c_chip} {addr}{.0, .1, .2} {count} + */ +int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar chip; + ulong addr; + uint alen; + int count; + uchar byte; + ulong crc; + ulong err; + int j; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* + * Chip is always specified. + */ + chip = simple_strtoul(argv[1], NULL, 16); + + /* + * Address is always specified. + */ + addr = simple_strtoul(argv[2], NULL, 16); + alen = 1; + for(j = 0; j < 8; j++) { + if (argv[2][j] == '.') { + alen = argv[2][j+1] - '0'; + if(alen > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; + } else if (argv[2][j] == '\0') { + break; + } + } + + /* + * Count is always specified + */ + count = simple_strtoul(argv[3], NULL, 16); + + printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1); + /* + * CRC a byte at a time. This is going to be slooow, but hey, the + * memories are small and slow too so hopefully nobody notices. + */ + crc = 0; + err = 0; + while(count-- > 0) { + if(i2c_read(chip, addr, alen, &byte, 1) != 0) { + err++; + } + crc = crc32 (crc, &byte, 1); + addr++; + } + if(err > 0) + { + puts ("Error reading the chip,\n"); + } else { + printf ("%08lx\n", crc); + } + + return 0; +} + + +/* Modify memory. + * + * Syntax: + * imm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} + * inm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} + */ + +static int +mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) +{ + uchar chip; + ulong addr; + uint alen; + ulong data; + int size = 1; + int nbytes; + int j; + extern char console_buffer[]; + + if (argc != 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + +#ifdef CONFIG_BOOT_RETRY_TIME + reset_cmd_timeout(); /* got a good command to get here */ +#endif + /* + * We use the last specified parameters, unless new ones are + * entered. + */ + chip = i2c_mm_last_chip; + addr = i2c_mm_last_addr; + alen = i2c_mm_last_alen; + + if ((flag & CMD_FLAG_REPEAT) == 0) { + /* + * New command specified. Check for a size specification. + * Defaults to byte if no or incorrect specification. + */ + size = cmd_get_data_size(argv[0], 1); + + /* + * Chip is always specified. + */ + chip = simple_strtoul(argv[1], NULL, 16); + + /* + * Address is always specified. + */ + addr = simple_strtoul(argv[2], NULL, 16); + alen = 1; + for(j = 0; j < 8; j++) { + if (argv[2][j] == '.') { + alen = argv[2][j+1] - '0'; + if(alen > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; + } else if (argv[2][j] == '\0') { + break; + } + } + } + + /* + * Print the address, followed by value. Then accept input for + * the next value. A non-converted value exits. + */ + do { + printf("%08lx:", addr); + if(i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) { + puts ("\nError reading the chip,\n"); + } else { + data = cpu_to_be32(data); + if(size == 1) { + printf(" %02lx", (data >> 24) & 0x000000FF); + } else if(size == 2) { + printf(" %04lx", (data >> 16) & 0x0000FFFF); + } else { + printf(" %08lx", data); + } + } + + nbytes = readline (" ? "); + if (nbytes == 0) { + /* + * pressed as only input, don't modify current + * location and move to next. + */ + if (incrflag) + addr += size; + nbytes = size; +#ifdef CONFIG_BOOT_RETRY_TIME + reset_cmd_timeout(); /* good enough to not time out */ +#endif + } +#ifdef CONFIG_BOOT_RETRY_TIME + else if (nbytes == -2) { + break; /* timed out, exit the command */ + } +#endif + else { + char *endp; + + data = simple_strtoul(console_buffer, &endp, 16); + if(size == 1) { + data = data << 24; + } else if(size == 2) { + data = data << 16; + } + data = be32_to_cpu(data); + nbytes = endp - console_buffer; + if (nbytes) { +#ifdef CONFIG_BOOT_RETRY_TIME + /* + * good enough to not time out + */ + reset_cmd_timeout(); +#endif + if(i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) { + puts ("Error writing the chip.\n"); + } +#ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#endif + if (incrflag) + addr += size; + } + } + } while (nbytes); + + chip = i2c_mm_last_chip; + addr = i2c_mm_last_addr; + alen = i2c_mm_last_alen; + + return 0; +} + +/* + * Syntax: + * iprobe {addr}{.0, .1, .2} + */ +int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int j; +#if defined(CFG_I2C_NOPROBES) + int k, skip; +#endif + + puts ("Valid chip addresses:"); + for(j = 0; j < 128; j++) { +#if defined(CFG_I2C_NOPROBES) + skip = 0; + for (k = 0; k < sizeof(i2c_no_probes); k++){ + if (j == i2c_no_probes[k]){ + skip = 1; + break; + } + } + if (skip) + continue; +#endif + if(i2c_probe(j) == 0) { + printf(" %02X", j); + } + } + putc ('\n'); + +#if defined(CFG_I2C_NOPROBES) + puts ("Excluded chip addresses:"); + for( k = 0; k < sizeof(i2c_no_probes); k++ ) + printf(" %02X", i2c_no_probes[k] ); + putc ('\n'); +#endif + + return 0; +} + + +/* + * Syntax: + * iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}] + * {length} - Number of bytes to read + * {delay} - A DECIMAL number and defaults to 1000 uSec + */ +int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u_char chip; + ulong alen; + uint addr; + uint length; + u_char bytes[16]; + int delay; + int j; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* + * Chip is always specified. + */ + chip = simple_strtoul(argv[1], NULL, 16); + + /* + * Address is always specified. + */ + addr = simple_strtoul(argv[2], NULL, 16); + alen = 1; + for(j = 0; j < 8; j++) { + if (argv[2][j] == '.') { + alen = argv[2][j+1] - '0'; + if (alen > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; + } else if (argv[2][j] == '\0') { + break; + } + } + + /* + * Length is the number of objects, not number of bytes. + */ + length = 1; + length = simple_strtoul(argv[3], NULL, 16); + if(length > sizeof(bytes)) { + length = sizeof(bytes); + } + + /* + * The delay time (uSec) is optional. + */ + delay = 1000; + if (argc > 3) { + delay = simple_strtoul(argv[4], NULL, 10); + } + /* + * Run the loop... + */ + while(1) { + if(i2c_read(chip, addr, alen, bytes, length) != 0) { + puts ("Error reading the chip.\n"); + } + udelay(delay); + } + + /* NOTREACHED */ + return 0; +} + + +/* + * The SDRAM command is separately configured because many + * (most?) embedded boards don't use SDRAM DIMMs. + */ +#if (CONFIG_COMMANDS & CFG_CMD_SDRAM) + +/* + * Syntax: + * sdram {i2c_chip} + */ +int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u_char chip; + u_char data[128]; + u_char cksum; + int j; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + /* + * Chip is always specified. + */ + chip = simple_strtoul(argv[1], NULL, 16); + + if(i2c_read(chip, 0, 1, data, sizeof(data)) != 0) { + puts ("No SDRAM Serial Presence Detect found.\n"); + return 1; + } + + cksum = 0; + for (j = 0; j < 63; j++) { + cksum += data[j]; + } + if(cksum != data[63]) { + printf ("WARNING: Configuration data checksum failure:\n" + " is 0x%02x, calculated 0x%02x\n", + data[63], cksum); + } + printf("SPD data revision %d.%d\n", + (data[62] >> 4) & 0x0F, data[62] & 0x0F); + printf("Bytes used 0x%02X\n", data[0]); + printf("Serial memory size 0x%02X\n", 1 << data[1]); + puts ("Memory type "); + switch(data[2]) { + case 2: puts ("EDO\n"); break; + case 4: puts ("SDRAM\n"); break; + default: puts ("unknown\n"); break; + } + puts ("Row address bits "); + if((data[3] & 0x00F0) == 0) { + printf("%d\n", data[3] & 0x0F); + } else { + printf("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); + } + puts ("Column address bits "); + if((data[4] & 0x00F0) == 0) { + printf("%d\n", data[4] & 0x0F); + } else { + printf("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); + } + printf("Module rows %d\n", data[5]); + printf("Module data width %d bits\n", (data[7] << 8) | data[6]); + puts ("Interface signal levels "); + switch(data[8]) { + case 0: puts ("5.0v/TTL\n"); break; + case 1: puts ("LVTTL\n"); break; + case 2: puts ("HSTL 1.5\n"); break; + case 3: puts ("SSTL 3.3\n"); break; + case 4: puts ("SSTL 2.5\n"); break; + default: puts ("unknown\n"); break; + } + printf("SDRAM cycle time %d.%d nS\n", + (data[9] >> 4) & 0x0F, data[9] & 0x0F); + printf("SDRAM access time %d.%d nS\n", + (data[10] >> 4) & 0x0F, data[10] & 0x0F); + puts ("EDC configuration "); + switch(data[11]) { + case 0: puts ("None\n"); break; + case 1: puts ("Parity\n"); break; + case 2: puts ("ECC\n"); break; + default: puts ("unknown\n"); break; + } + if((data[12] & 0x80) == 0) { + puts ("No self refresh, rate "); + } else { + puts ("Self refresh, rate "); + } + switch(data[12] & 0x7F) { + case 0: puts ("15.625uS\n"); break; + case 1: puts ("3.9uS\n"); break; + case 2: puts ("7.8uS\n"); break; + case 3: puts ("31.3uS\n"); break; + case 4: puts ("62.5uS\n"); break; + case 5: puts ("125uS\n"); break; + default: puts ("unknown\n"); break; + } + printf("SDRAM width (primary) %d\n", data[13] & 0x7F); + if((data[13] & 0x80) != 0) { + printf(" (second bank) %d\n", + 2 * (data[13] & 0x7F)); + } + if(data[14] != 0) { + printf("EDC width %d\n", + data[14] & 0x7F); + if((data[14] & 0x80) != 0) { + printf(" (second bank) %d\n", + 2 * (data[14] & 0x7F)); + } + } + printf("Min clock delay, back-to-back random column addresses %d\n", + data[15]); + puts ("Burst length(s) "); + if (data[16] & 0x80) puts (" Page"); + if (data[16] & 0x08) puts (" 8"); + if (data[16] & 0x04) puts (" 4"); + if (data[16] & 0x02) puts (" 2"); + if (data[16] & 0x01) puts (" 1"); + putc ('\n'); + printf("Number of banks %d\n", data[17]); + puts ("CAS latency(s) "); + if (data[18] & 0x80) puts (" TBD"); + if (data[18] & 0x40) puts (" 7"); + if (data[18] & 0x20) puts (" 6"); + if (data[18] & 0x10) puts (" 5"); + if (data[18] & 0x08) puts (" 4"); + if (data[18] & 0x04) puts (" 3"); + if (data[18] & 0x02) puts (" 2"); + if (data[18] & 0x01) puts (" 1"); + putc ('\n'); + puts ("CS latency(s) "); + if (data[19] & 0x80) puts (" TBD"); + if (data[19] & 0x40) puts (" 6"); + if (data[19] & 0x20) puts (" 5"); + if (data[19] & 0x10) puts (" 4"); + if (data[19] & 0x08) puts (" 3"); + if (data[19] & 0x04) puts (" 2"); + if (data[19] & 0x02) puts (" 1"); + if (data[19] & 0x01) puts (" 0"); + putc ('\n'); + puts ("WE latency(s) "); + if (data[20] & 0x80) puts (" TBD"); + if (data[20] & 0x40) puts (" 6"); + if (data[20] & 0x20) puts (" 5"); + if (data[20] & 0x10) puts (" 4"); + if (data[20] & 0x08) puts (" 3"); + if (data[20] & 0x04) puts (" 2"); + if (data[20] & 0x02) puts (" 1"); + if (data[20] & 0x01) puts (" 0"); + putc ('\n'); + puts ("Module attributes:\n"); + if (!data[21]) puts (" (none)\n"); + if (data[21] & 0x80) puts (" TBD (bit 7)\n"); + if (data[21] & 0x40) puts (" Redundant row address\n"); + if (data[21] & 0x20) puts (" Differential clock input\n"); + if (data[21] & 0x10) puts (" Registerd DQMB inputs\n"); + if (data[21] & 0x08) puts (" Buffered DQMB inputs\n"); + if (data[21] & 0x04) puts (" On-card PLL\n"); + if (data[21] & 0x02) puts (" Registered address/control lines\n"); + if (data[21] & 0x01) puts (" Buffered address/control lines\n"); + puts ("Device attributes:\n"); + if (data[22] & 0x80) puts (" TBD (bit 7)\n"); + if (data[22] & 0x40) puts (" TBD (bit 6)\n"); + if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n"); + else puts (" Upper Vcc tolerance 10%\n"); + if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n"); + else puts (" Lower Vcc tolerance 10%\n"); + if (data[22] & 0x08) puts (" Supports write1/read burst\n"); + if (data[22] & 0x04) puts (" Supports precharge all\n"); + if (data[22] & 0x02) puts (" Supports auto precharge\n"); + if (data[22] & 0x01) puts (" Supports early RAS# precharge\n"); + printf("SDRAM cycle time (2nd highest CAS latency) %d.%d nS\n", + (data[23] >> 4) & 0x0F, data[23] & 0x0F); + printf("SDRAM access from clock (2nd highest CAS latency) %d.%d nS\n", + (data[24] >> 4) & 0x0F, data[24] & 0x0F); + printf("SDRAM cycle time (3rd highest CAS latency) %d.%d nS\n", + (data[25] >> 4) & 0x0F, data[25] & 0x0F); + printf("SDRAM access from clock (3rd highest CAS latency) %d.%d nS\n", + (data[26] >> 4) & 0x0F, data[26] & 0x0F); + printf("Minimum row precharge %d nS\n", data[27]); + printf("Row active to row active min %d nS\n", data[28]); + printf("RAS to CAS delay min %d nS\n", data[29]); + printf("Minimum RAS pulse width %d nS\n", data[30]); + puts ("Density of each row "); + if (data[31] & 0x80) puts (" 512"); + if (data[31] & 0x40) puts (" 256"); + if (data[31] & 0x20) puts (" 128"); + if (data[31] & 0x10) puts (" 64"); + if (data[31] & 0x08) puts (" 32"); + if (data[31] & 0x04) puts (" 16"); + if (data[31] & 0x02) puts (" 8"); + if (data[31] & 0x01) puts (" 4"); + puts ("MByte\n"); + printf("Command and Address setup %c%d.%d nS\n", + (data[32] & 0x80) ? '-' : '+', + (data[32] >> 4) & 0x07, data[32] & 0x0F); + printf("Command and Address hold %c%d.%d nS\n", + (data[33] & 0x80) ? '-' : '+', + (data[33] >> 4) & 0x07, data[33] & 0x0F); + printf("Data signal input setup %c%d.%d nS\n", + (data[34] & 0x80) ? '-' : '+', + (data[34] >> 4) & 0x07, data[34] & 0x0F); + printf("Data signal input hold %c%d.%d nS\n", + (data[35] & 0x80) ? '-' : '+', + (data[35] >> 4) & 0x07, data[35] & 0x0F); + puts ("Manufacturer's JEDEC ID "); + for(j = 64; j <= 71; j++) + printf("%02X ", data[j]); + putc ('\n'); + printf("Manufacturing Location %02X\n", data[72]); + puts ("Manufacturer's Part Number "); + for(j = 73; j <= 90; j++) + printf("%02X ", data[j]); + putc ('\n'); + printf("Revision Code %02X %02X\n", data[91], data[92]); + printf("Manufacturing Date %02X %02X\n", data[93], data[94]); + puts ("Assembly Serial Number "); + for(j = 95; j <= 98; j++) + printf("%02X ", data[j]); + putc ('\n'); + printf("Speed rating PC%d\n", + data[126] == 0x66 ? 66 : data[126]); + + return 0; +} +#endif /* CFG_CMD_SDRAM */ + + +/***************************************************/ + +U_BOOT_CMD( + imd, 4, 1, do_i2c_md, \ + "imd - i2c memory display\n", \ + "chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \ +); + +U_BOOT_CMD( + imm, 3, 1, do_i2c_mm, + "imm - i2c memory modify (auto-incrementing)\n", + "chip address[.0, .1, .2]\n" + " - memory modify, auto increment address\n" +); +U_BOOT_CMD( + inm, 3, 1, do_i2c_nm, + "inm - memory modify (constant address)\n", + "chip address[.0, .1, .2]\n - memory modify, read and keep address\n" +); + +U_BOOT_CMD( + imw, 5, 1, do_i2c_mw, + "imw - memory write (fill)\n", + "chip address[.0, .1, .2] value [count]\n - memory write (fill)\n" +); + +U_BOOT_CMD( + icrc32, 5, 1, do_i2c_crc, + "icrc32 - checksum calculation\n", + "chip address[.0, .1, .2] count\n - compute CRC32 checksum\n" +); + +U_BOOT_CMD( + iprobe, 1, 1, do_i2c_probe, + "iprobe - probe to discover valid I2C chip addresses\n", + "\n -discover valid I2C chip addresses\n" +); + +/* + * Require full name for "iloop" because it is an infinite loop! + */ +U_BOOT_CMD( + iloop, 5, 1, do_i2c_loop, + "iloop - infinite loop on address range\n", + "chip address[.0, .1, .2] [# of objects]\n" + " - loop, reading a set of addresses\n" +); + +#if (CONFIG_COMMANDS & CFG_CMD_SDRAM) +U_BOOT_CMD( + isdram, 2, 1, do_sdram, + "isdram - print SDRAM configuration information\n", + "chip\n - print SDRAM configuration information\n" + " (valid chip values 50..57)\n" +); +#endif +#endif /* CFG_CMD_I2C */ diff --git a/common/cmd_ide.c b/common/cmd_ide.c new file mode 100644 index 0000000..b67d35a --- /dev/null +++ b/common/cmd_ide.c @@ -0,0 +1,2068 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * IDE support + */ +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA) +# include +#endif +#ifdef CONFIG_8xx +# include +#endif +#ifdef CONFIG_MPC5xxx +#include +#endif +#include +#include +#ifdef CONFIG_STATUS_LED +# include +#endif +#ifndef __PPC__ +#include +#ifdef __MIPS__ +/* Macros depend on this variable */ +unsigned long mips_io_port_base = 0; +#endif +#endif + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#ifdef __PPC__ +# define EIEIO __asm__ volatile ("eieio") +# define SYNC __asm__ volatile ("sync") +#else +# define EIEIO /* nothing */ +# define SYNC /* nothing */ +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + +#ifdef CONFIG_IDE_8xx_DIRECT +/* Timings for IDE Interface + * + * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk + * 70 165 30 PIO-Mode 0, [ns] + * 4 9 2 [Cycles] + * 50 125 20 PIO-Mode 1, [ns] + * 3 7 2 [Cycles] + * 30 100 15 PIO-Mode 2, [ns] + * 2 6 1 [Cycles] + * 30 80 10 PIO-Mode 3, [ns] + * 2 5 1 [Cycles] + * 25 70 10 PIO-Mode 4, [ns] + * 2 4 1 [Cycles] + */ + +const static pio_config_t pio_config_ns [IDE_MAX_PIO_MODE+1] = +{ + /* Setup Length Hold */ + { 70, 165, 30 }, /* PIO-Mode 0, [ns] */ + { 50, 125, 20 }, /* PIO-Mode 1, [ns] */ + { 30, 101, 15 }, /* PIO-Mode 2, [ns] */ + { 30, 80, 10 }, /* PIO-Mode 3, [ns] */ + { 25, 70, 10 }, /* PIO-Mode 4, [ns] */ +}; + +static pio_config_t pio_config_clk [IDE_MAX_PIO_MODE+1]; + +#ifndef CFG_PIO_MODE +#define CFG_PIO_MODE 0 /* use a relaxed default */ +#endif +static int pio_mode = CFG_PIO_MODE; + +/* Make clock cycles and always round up */ + +#define PCMCIA_MK_CLKS( t, T ) (( (t) * (T) + 999U ) / 1000U ) + +#endif /* CONFIG_IDE_8xx_DIRECT */ + +/* ------------------------------------------------------------------------- */ + +/* Current I/O Device */ +static int curr_device = -1; + +/* Current offset for IDE0 / IDE1 bus access */ +ulong ide_bus_offset[CFG_IDE_MAXBUS] = { +#if defined(CFG_ATA_IDE0_OFFSET) + CFG_ATA_IDE0_OFFSET, +#endif +#if defined(CFG_ATA_IDE1_OFFSET) && (CFG_IDE_MAXBUS > 1) + CFG_ATA_IDE1_OFFSET, +#endif +}; + + +#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) + +#ifndef CONFIG_AMIGAONEG3SE +static int ide_bus_ok[CFG_IDE_MAXBUS]; +#else +static int ide_bus_ok[CFG_IDE_MAXBUS] = {0,}; +#endif + +block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_IDE_LED +#if !defined(CONFIG_KUP4K) && !defined(CONFIG_KUP4X) &&!defined(CONFIG_BMS2003) &&!defined(CONFIG_CPC45) +static void ide_led (uchar led, uchar status); +#else +extern void ide_led (uchar led, uchar status); +#endif +#else +#ifndef CONFIG_AMIGAONEG3SE +#define ide_led(a,b) /* dummy */ +#else +extern void ide_led(uchar led, uchar status); +#define LED_IDE1 1 +#define LED_IDE2 2 +#define CONFIG_IDE_LED 1 +#define DEVICE_LED(x) 1 +#endif +#endif + +#ifdef CONFIG_IDE_RESET +static void ide_reset (void); +#else +#define ide_reset() /* dummy */ +#endif + +static void ide_ident (block_dev_desc_t *dev_desc); +static uchar ide_wait (int dev, ulong t); + +#define IDE_TIME_OUT 2000 /* 2 sec timeout */ + +#define ATAPI_TIME_OUT 7000 /* 7 sec timeout (5 sec seems to work...) */ + +#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */ + +static void __inline__ ide_outb(int dev, int port, unsigned char val); +static unsigned char __inline__ ide_inb(int dev, int port); +static void input_data(int dev, ulong *sect_buf, int words); +static void output_data(int dev, ulong *sect_buf, int words); +static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); + + +#ifdef CONFIG_ATAPI +static void atapi_inquiry(block_dev_desc_t *dev_desc); +ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer); +#endif + + +#ifdef CONFIG_IDE_8xx_DIRECT +static void set_pcmcia_timing (int pmode); +#endif + +/* ------------------------------------------------------------------------- */ + +int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; + + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp(argv[1],"res",3) == 0) { + puts ("\nReset IDE" +#ifdef CONFIG_IDE_8xx_DIRECT + " on PCMCIA " PCMCIA_SLOT_MSG +#endif + ": "); + + ide_init (); + return 0; + } else if (strncmp(argv[1],"inf",3) == 0) { + int i; + + putc ('\n'); + + for (i=0; i= CFG_IDE_MAXDEVICE)) { + puts ("\nno IDE devices available\n"); + return 1; + } + printf ("\nIDE device %d: ", curr_device); + dev_print(&ide_dev_desc[curr_device]); + return 0; + } else if (strncmp(argv[1],"part",4) == 0) { + int dev, ok; + + for (ok=0, dev=0; devusage); + return 1; + case 3: + if (strncmp(argv[1],"dev",3) == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + + printf ("\nIDE device %d: ", dev); + if (dev >= CFG_IDE_MAXDEVICE) { + puts ("unknown device\n"); + return 1; + } + dev_print(&ide_dev_desc[dev]); + /*ide_print (dev);*/ + + if (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN) { + return 1; + } + + curr_device = dev; + + puts ("... is now current device\n"); + + return 0; + } else if (strncmp(argv[1],"part",4) == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + + if (ide_dev_desc[dev].part_type!=PART_TYPE_UNKNOWN) { + print_part(&ide_dev_desc[dev]); + } else { + printf ("\nIDE device %d not available\n", dev); + rcode = 1; + } + return rcode; +#if 0 + } else if (strncmp(argv[1],"pio",4) == 0) { + int mode = (int)simple_strtoul(argv[2], NULL, 10); + + if ((mode >= 0) && (mode <= IDE_MAX_PIO_MODE)) { + puts ("\nSetting "); + pio_mode = mode; + ide_init (); + } else { + printf ("\nInvalid PIO mode %d (0 ... %d only)\n", + mode, IDE_MAX_PIO_MODE); + } + return; +#endif + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + /* at least 4 args */ + + if (strcmp(argv[1],"read") == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong cnt = simple_strtoul(argv[4], NULL, 16); + ulong n; +#ifdef CFG_64BIT_STRTOUL + lbaint_t blk = simple_strtoull(argv[3], NULL, 16); + + printf ("\nIDE read: device %d block # %qd, count %ld ... ", + curr_device, blk, cnt); +#else + lbaint_t blk = simple_strtoul(argv[3], NULL, 16); + + printf ("\nIDE read: device %d block # %ld, count %ld ... ", + curr_device, blk, cnt); +#endif + + n = ide_dev_desc[curr_device].block_read (curr_device, + blk, cnt, + (ulong *)addr); + /* flush cache after read */ + flush_cache (addr, cnt*ide_dev_desc[curr_device].blksz); + + printf ("%ld blocks read: %s\n", + n, (n==cnt) ? "OK" : "ERROR"); + if (n==cnt) { + return 0; + } else { + return 1; + } + } else if (strcmp(argv[1],"write") == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong cnt = simple_strtoul(argv[4], NULL, 16); + ulong n; +#ifdef CFG_64BIT_STRTOUL + lbaint_t blk = simple_strtoull(argv[3], NULL, 16); + + printf ("\nIDE write: device %d block # %qd, count %ld ... ", + curr_device, blk, cnt); +#else + lbaint_t blk = simple_strtoul(argv[3], NULL, 16); + + printf ("\nIDE write: device %d block # %ld, count %ld ... ", + curr_device, blk, cnt); +#endif + + n = ide_write (curr_device, blk, cnt, (ulong *)addr); + + printf ("%ld blocks written: %s\n", + n, (n==cnt) ? "OK" : "ERROR"); + if (n==cnt) { + return 0; + } else { + return 1; + } + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + rcode = 1; + } + + return rcode; + } +} + +int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + char *ep; + int dev, part = 0; + ulong addr, cnt, checksum; + disk_partition_t info; + image_header_t *hdr; + int rcode = 0; + + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_device = getenv ("bootdevice"); + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = getenv ("bootdevice"); + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + if (!boot_device) { + puts ("\n** No boot device **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + dev = simple_strtoul(boot_device, &ep, 16); + + if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) { + printf ("\n** Device %d not available\n", dev); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + part = simple_strtoul(++ep, NULL, 16); + } + if (get_partition_info (ide_dev_desc, part, &info)) { + SHOW_BOOT_PROGRESS (-1); + return 1; + } + if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) && + (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) { + printf ("\n** Invalid partition type \"%.32s\"" + " (expect \"" BOOT_PART_TYPE "\")\n", + info.type); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + printf ("\nLoading from IDE device %d, partition %d: " + "Name: %.32s Type: %.32s\n", + dev, part, info.name, info.type); + + debug ("First Block: %ld, # of blocks: %ld, Block Size: %ld\n", + info.start, info.size, info.blksz); + + if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) { + printf ("** Read error on %d:%d\n", dev, part); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + hdr = (image_header_t *)addr; + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + printf("\n** Bad Magic Number **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) { + puts ("\n** Bad Header Checksum **\n"); + SHOW_BOOT_PROGRESS (-2); + return 1; + } + hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */ + + print_image_hdr (hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); + cnt += info.blksz - 1; + cnt /= info.blksz; + cnt -= 1; + + if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt, + (ulong *)(addr+info.blksz)) != cnt) { + printf ("** Read error on %d:%d\n", dev, part); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + + /* Loading ok, update default load address */ + + load_addr = addr; + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { + char *local_args[2]; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + + local_args[0] = argv[0]; + local_args[1] = NULL; + + printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); + + do_bootm (cmdtp, 0, 1, local_args); + rcode = 1; + } + return rcode; +} + +/* ------------------------------------------------------------------------- */ + +void ide_init (void) +{ + +#ifdef CONFIG_IDE_8xx_DIRECT + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); +#endif + unsigned char c; + int i, bus; +#ifdef CONFIG_AMIGAONEG3SE + unsigned int max_bus_scan; + unsigned int ata_reset_time; + char *s; +#endif +#ifdef CONFIG_IDE_8xx_PCCARD + extern int pcmcia_on (void); + extern int ide_devices_found; /* Initialized in check_ide_device() */ +#endif /* CONFIG_IDE_8xx_PCCARD */ + +#ifdef CONFIG_IDE_PREINIT + extern int ide_preinit (void); + WATCHDOG_RESET(); + + if (ide_preinit ()) { + puts ("ide_preinit failed\n"); + return; + } +#endif /* CONFIG_IDE_PREINIT */ + +#ifdef CONFIG_IDE_8xx_PCCARD + extern int pcmcia_on (void); + extern int ide_devices_found; /* Initialized in check_ide_device() */ + + WATCHDOG_RESET(); + + ide_devices_found = 0; + /* initialize the PCMCIA IDE adapter card */ + pcmcia_on(); + if (!ide_devices_found) + return; + udelay (1000000); /* 1 s */ +#endif /* CONFIG_IDE_8xx_PCCARD */ + + WATCHDOG_RESET(); + +#ifdef CONFIG_IDE_8xx_DIRECT + /* Initialize PIO timing tables */ + for (i=0; i <= IDE_MAX_PIO_MODE; ++i) { + pio_config_clk[i].t_setup = PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, + gd->bus_clk); + pio_config_clk[i].t_length = PCMCIA_MK_CLKS(pio_config_ns[i].t_length, + gd->bus_clk); + pio_config_clk[i].t_hold = PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, + gd->bus_clk); + debug ( "PIO Mode %d: setup=%2d ns/%d clk" + " len=%3d ns/%d clk" + " hold=%2d ns/%d clk\n", + i, + pio_config_ns[i].t_setup, pio_config_clk[i].t_setup, + pio_config_ns[i].t_length, pio_config_clk[i].t_length, + pio_config_ns[i].t_hold, pio_config_clk[i].t_hold); + } +#endif /* CONFIG_IDE_8xx_DIRECT */ + + /* Reset the IDE just to be sure. + * Light LED's to show + */ + ide_led ((LED_IDE1 | LED_IDE2), 1); /* LED's on */ + ide_reset (); /* ATAPI Drives seems to need a proper IDE Reset */ + +#ifdef CONFIG_IDE_8xx_DIRECT + /* PCMCIA / IDE initialization for common mem space */ + pcmp->pcmc_pgcrb = 0; + + /* start in PIO mode 0 - most relaxed timings */ + pio_mode = 0; + set_pcmcia_timing (pio_mode); +#endif /* CONFIG_IDE_8xx_DIRECT */ + + /* + * Wait for IDE to get ready. + * According to spec, this can take up to 31 seconds! + */ +#ifndef CONFIG_AMIGAONEG3SE + for (bus=0; bus (ata_reset_time * 100)) { +#else + if (i > (ATA_RESET_TIME * 100)) { +#endif + puts ("** Timeout **\n"); + ide_led ((LED_IDE1 | LED_IDE2), 0); /* LED's off */ +#ifdef CONFIG_AMIGAONEG3SE + /* If this is the second bus, the first one was OK */ + if (bus != 0) { + ide_bus_ok[bus] = 0; + goto skip_bus; + } +#endif + return; + } + if ((i >= 100) && ((i%100)==0)) { + putc ('.'); + } + } while (c & ATA_STAT_BUSY); + + if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) { + puts ("not available "); + debug ("Status = 0x%02X ", c); +#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */ + } else if ((c & ATA_STAT_READY) == 0) { + puts ("not available "); + debug ("Status = 0x%02X ", c); +#endif + } else { + puts ("OK "); + ide_bus_ok[bus] = 1; + } + WATCHDOG_RESET(); + } + +#ifdef CONFIG_AMIGAONEG3SE + skip_bus: +#endif + putc ('\n'); + + ide_led ((LED_IDE1 | LED_IDE2), 0); /* LED's off */ + + curr_device = -1; + for (i=0; i 0) && (ide_dev_desc[i].blksz > 0)) { + init_part (&ide_dev_desc[i]); /* initialize partition type */ + if (curr_device < 0) + curr_device = i; + } + } + WATCHDOG_RESET(); +} + +/* ------------------------------------------------------------------------- */ + +block_dev_desc_t * ide_get_dev(int dev) +{ + return ((block_dev_desc_t *)&ide_dev_desc[dev]); +} + + +#ifdef CONFIG_IDE_8xx_DIRECT + +static void +set_pcmcia_timing (int pmode) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); + ulong timings; + + debug ("Set timing for PIO Mode %d\n", pmode); + + timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold) + | PCMCIA_SST(pio_config_clk[pmode].t_setup) + | PCMCIA_SL (pio_config_clk[pmode].t_length) + ; + + /* IDE 0 + */ + pcmp->pcmc_pbr0 = CFG_PCMCIA_PBR0; + pcmp->pcmc_por0 = CFG_PCMCIA_POR0 +#if (CFG_PCMCIA_POR0 != 0) + | timings +#endif + ; + debug ("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0); + + pcmp->pcmc_pbr1 = CFG_PCMCIA_PBR1; + pcmp->pcmc_por1 = CFG_PCMCIA_POR1 +#if (CFG_PCMCIA_POR1 != 0) + | timings +#endif + ; + debug ("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1); + + pcmp->pcmc_pbr2 = CFG_PCMCIA_PBR2; + pcmp->pcmc_por2 = CFG_PCMCIA_POR2 +#if (CFG_PCMCIA_POR2 != 0) + | timings +#endif + ; + debug ("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2); + + pcmp->pcmc_pbr3 = CFG_PCMCIA_PBR3; + pcmp->pcmc_por3 = CFG_PCMCIA_POR3 +#if (CFG_PCMCIA_POR3 != 0) + | timings +#endif + ; + debug ("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3); + + /* IDE 1 + */ + pcmp->pcmc_pbr4 = CFG_PCMCIA_PBR4; + pcmp->pcmc_por4 = CFG_PCMCIA_POR4 +#if (CFG_PCMCIA_POR4 != 0) + | timings +#endif + ; + debug ("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4); + + pcmp->pcmc_pbr5 = CFG_PCMCIA_PBR5; + pcmp->pcmc_por5 = CFG_PCMCIA_POR5 +#if (CFG_PCMCIA_POR5 != 0) + | timings +#endif + ; + debug ("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5); + + pcmp->pcmc_pbr6 = CFG_PCMCIA_PBR6; + pcmp->pcmc_por6 = CFG_PCMCIA_POR6 +#if (CFG_PCMCIA_POR6 != 0) + | timings +#endif + ; + debug ("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6); + + pcmp->pcmc_pbr7 = CFG_PCMCIA_PBR7; + pcmp->pcmc_por7 = CFG_PCMCIA_POR7 +#if (CFG_PCMCIA_POR7 != 0) + | timings +#endif + ; + debug ("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7); + +} + +#endif /* CONFIG_IDE_8xx_DIRECT */ + +/* ------------------------------------------------------------------------- */ + +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +static void __inline__ +ide_outb(int dev, int port, unsigned char val) +{ + debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", + dev, port, val, (ATA_CURR_BASE(dev)+port)); + + /* Ensure I/O operations complete */ + EIEIO; + *((uchar *)(ATA_CURR_BASE(dev)+port)) = val; +} +#else /* ! __PPC__ */ +static void __inline__ +ide_outb(int dev, int port, unsigned char val) +{ + outb(val, ATA_CURR_BASE(dev)+port); +} +#endif /* __PPC__ */ + + +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +static unsigned char __inline__ +ide_inb(int dev, int port) +{ + uchar val; + /* Ensure I/O operations complete */ + EIEIO; + val = *((uchar *)(ATA_CURR_BASE(dev)+port)); + debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", + dev, port, (ATA_CURR_BASE(dev)+port), val); + return (val); +} +#else /* ! __PPC__ */ +static unsigned char __inline__ +ide_inb(int dev, int port) +{ + return inb(ATA_CURR_BASE(dev)+port); +} +#endif /* __PPC__ */ + +#ifdef __PPC__ +# ifdef CONFIG_AMIGAONEG3SE +static void +output_data_short(int dev, ulong *sect_buf, int words) +{ + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); + dbuf = (ushort *)sect_buf; + while (words--) { + EIEIO; + *pbuf = *dbuf++; + EIEIO; + } + + if (words&1) + *pbuf = 0; +} +# endif /* CONFIG_AMIGAONEG3SE */ +#endif /* __PPC_ */ + +/* We only need to swap data if we are running on a big endian cpu. */ +/* But Au1x00 cpu:s already swaps data in big endian mode! */ +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_AU1X00) +#define input_swap_data(x,y,z) input_data(x,y,z) +#else +static void +input_swap_data(int dev, ulong *sect_buf, int words) +{ +#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) + uchar i; + volatile uchar *pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN); + volatile uchar *pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD); + ushort *dbuf = (ushort *)sect_buf; + + while (words--) { + for (i=0; i<2; i++) { + *(((uchar *)(dbuf)) + 1) = *pbuf_even; + *(uchar *)dbuf = *pbuf_odd; + dbuf+=1; + } + } +#else + volatile ushort *pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); + ushort *dbuf = (ushort *)sect_buf; + + debug("in input swap data base for read is %lx\n", (unsigned long) pbuf); + + while (words--) { + *dbuf++ = ld_le16(pbuf); + *dbuf++ = ld_le16(pbuf); + } +#endif +} +#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */ + + +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +static void +output_data(int dev, ulong *sect_buf, int words) +{ +#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN); + pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD); + dbuf = (uchar *)sect_buf; + while (words--) { + EIEIO; + *pbuf_even = *dbuf++; + EIEIO; + *pbuf_odd = *dbuf++; + EIEIO; + *pbuf_even = *dbuf++; + EIEIO; + *pbuf_odd = *dbuf++; + } +#else + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); + dbuf = (ushort *)sect_buf; + while (words--) { + EIEIO; + *pbuf = *dbuf++; + EIEIO; + *pbuf = *dbuf++; + } +#endif +} +#else /* ! __PPC__ */ +static void +output_data(int dev, ulong *sect_buf, int words) +{ + outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words<<1); +} +#endif /* __PPC__ */ + +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +static void +input_data(int dev, ulong *sect_buf, int words) +{ +#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN); + pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD); + dbuf = (uchar *)sect_buf; + while (words--) { + *dbuf++ = *pbuf_even; + EIEIO; + SYNC; + *dbuf++ = *pbuf_odd; + EIEIO; + SYNC; + *dbuf++ = *pbuf_even; + EIEIO; + SYNC; + *dbuf++ = *pbuf_odd; + EIEIO; + SYNC; + } +#else + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); + dbuf = (ushort *)sect_buf; + + debug("in input data base for read is %lx\n", (unsigned long) pbuf); + + while (words--) { + EIEIO; + *dbuf++ = *pbuf; + EIEIO; + *dbuf++ = *pbuf; + } +#endif +} +#else /* ! __PPC__ */ +static void +input_data(int dev, ulong *sect_buf, int words) +{ + insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1); +} + +#endif /* __PPC__ */ + +#ifdef CONFIG_AMIGAONEG3SE +static void +input_data_short(int dev, ulong *sect_buf, int words) +{ + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); + dbuf = (ushort *)sect_buf; + while (words--) { + EIEIO; + *dbuf++ = *pbuf; + EIEIO; + } + + if (words&1) { + ushort dummy; + dummy = *pbuf; + } +} +#endif + +/* ------------------------------------------------------------------------- + */ +static void ide_ident (block_dev_desc_t *dev_desc) +{ + ulong iobuf[ATA_SECTORWORDS]; + unsigned char c; + hd_driveid_t *iop = (hd_driveid_t *)iobuf; + +#ifdef CONFIG_AMIGAONEG3SE + int max_bus_scan; + char *s; +#endif +#ifdef CONFIG_ATAPI + int retries = 0; + int do_retry = 0; +#endif + +#if 0 + int mode, cycle_time; +#endif + int device; + device=dev_desc->dev; + printf (" Device %d: ", device); + +#ifdef CONFIG_AMIGAONEG3SE + s = getenv("ide_maxbus"); + if (s) { + max_bus_scan = simple_strtol(s, NULL, 10); + } else { + max_bus_scan = CFG_IDE_MAXBUS; + } + if (device >= max_bus_scan*2) { + dev_desc->type=DEV_TYPE_UNKNOWN; + return; + } +#endif + + ide_led (DEVICE_LED(device), 1); /* LED on */ + /* Select device + */ + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); + dev_desc->if_type=IF_TYPE_IDE; +#ifdef CONFIG_ATAPI + + do_retry = 0; + retries = 0; + + /* Warning: This will be tricky to read */ + while (retries <= 1) { + /* check signature */ + if ((ide_inb(device,ATA_SECT_CNT) == 0x01) && + (ide_inb(device,ATA_SECT_NUM) == 0x01) && + (ide_inb(device,ATA_CYL_LOW) == 0x14) && + (ide_inb(device,ATA_CYL_HIGH) == 0xEB)) { + /* ATAPI Signature found */ + dev_desc->if_type=IF_TYPE_ATAPI; + /* Start Ident Command + */ + ide_outb (device, ATA_COMMAND, ATAPI_CMD_IDENT); + /* + * Wait for completion - ATAPI devices need more time + * to become ready + */ + c = ide_wait (device, ATAPI_TIME_OUT); + } else +#endif + { + /* Start Ident Command + */ + ide_outb (device, ATA_COMMAND, ATA_CMD_IDENT); + + /* Wait for completion + */ + c = ide_wait (device, IDE_TIME_OUT); + } + ide_led (DEVICE_LED(device), 0); /* LED off */ + + if (((c & ATA_STAT_DRQ) == 0) || + ((c & (ATA_STAT_FAULT|ATA_STAT_ERR)) != 0) ) { +#ifdef CONFIG_ATAPI +#ifdef CONFIG_AMIGAONEG3SE + s = getenv("ide_doreset"); + if (s && strcmp(s, "on") == 0) +#endif + { + /* Need to soft reset the device in case it's an ATAPI... */ + debug ("Retrying...\n"); + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); + udelay(100000); + ide_outb (device, ATA_COMMAND, 0x08); + udelay (500000); /* 500 ms */ + } + /* Select device + */ + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); + retries++; +#else + return; +#endif + } +#ifdef CONFIG_ATAPI + else + break; + } /* see above - ugly to read */ + + if (retries == 2) /* Not found */ + return; +#endif + + input_swap_data (device, iobuf, ATA_SECTORWORDS); + + ident_cpy (dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision)); + ident_cpy (dev_desc->vendor, iop->model, sizeof(dev_desc->vendor)); + ident_cpy (dev_desc->product, iop->serial_no, sizeof(dev_desc->product)); +#ifdef __LITTLE_ENDIAN + /* + * firmware revision and model number have Big Endian Byte + * order in Word. Convert both to little endian. + * + * See CF+ and CompactFlash Specification Revision 2.0: + * 6.2.1.6: Identfy Drive, Table 39 for more details + */ + + strswab (dev_desc->revision); + strswab (dev_desc->vendor); +#endif /* __LITTLE_ENDIAN */ + + if ((iop->config & 0x0080)==0x0080) + dev_desc->removable = 1; + else + dev_desc->removable = 0; + +#if 0 + /* + * Drive PIO mode autoselection + */ + mode = iop->tPIO; + + printf ("tPIO = 0x%02x = %d\n",mode, mode); + if (mode > 2) { /* 2 is maximum allowed tPIO value */ + mode = 2; + debug ("Override tPIO -> 2\n"); + } + if (iop->field_valid & 2) { /* drive implements ATA2? */ + debug ("Drive implements ATA2\n"); + if (iop->capability & 8) { /* drive supports use_iordy? */ + cycle_time = iop->eide_pio_iordy; + } else { + cycle_time = iop->eide_pio; + } + debug ("cycle time = %d\n", cycle_time); + mode = 4; + if (cycle_time > 120) mode = 3; /* 120 ns for PIO mode 4 */ + if (cycle_time > 180) mode = 2; /* 180 ns for PIO mode 3 */ + if (cycle_time > 240) mode = 1; /* 240 ns for PIO mode 4 */ + if (cycle_time > 383) mode = 0; /* 383 ns for PIO mode 4 */ + } + printf ("PIO mode to use: PIO %d\n", mode); +#endif /* 0 */ + +#ifdef CONFIG_ATAPI + if (dev_desc->if_type==IF_TYPE_ATAPI) { + atapi_inquiry(dev_desc); + return; + } +#endif /* CONFIG_ATAPI */ + +#ifdef __BIG_ENDIAN + /* swap shorts */ + dev_desc->lba = (iop->lba_capacity << 16) | (iop->lba_capacity >> 16); +#else /* ! __BIG_ENDIAN */ + /* + * do not swap shorts on little endian + * + * See CF+ and CompactFlash Specification Revision 2.0: + * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details. + */ + dev_desc->lba = iop->lba_capacity; +#endif /* __BIG_ENDIAN */ + +#ifdef CONFIG_LBA48 + if (iop->command_set_2 & 0x0400) { /* LBA 48 support */ + dev_desc->lba48 = 1; + dev_desc->lba = (unsigned long long)iop->lba48_capacity[0] | + ((unsigned long long)iop->lba48_capacity[1] << 16) | + ((unsigned long long)iop->lba48_capacity[2] << 32) | + ((unsigned long long)iop->lba48_capacity[3] << 48); + } else { + dev_desc->lba48 = 0; + } +#endif /* CONFIG_LBA48 */ + /* assuming HD */ + dev_desc->type=DEV_TYPE_HARDDISK; + dev_desc->blksz=ATA_BLOCKSIZE; + dev_desc->lun=0; /* just to fill something in... */ + +#if 0 /* only used to test the powersaving mode, + * if enabled, the drive goes after 5 sec + * in standby mode */ + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); + c = ide_wait (device, IDE_TIME_OUT); + ide_outb (device, ATA_SECT_CNT, 1); + ide_outb (device, ATA_LBA_LOW, 0); + ide_outb (device, ATA_LBA_MID, 0); + ide_outb (device, ATA_LBA_HIGH, 0); + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); + ide_outb (device, ATA_COMMAND, 0xe3); + udelay (50); + c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */ +#endif +} + + +/* ------------------------------------------------------------------------- */ + +ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer) +{ + ulong n = 0; + unsigned char c; + unsigned char pwrsave=0; /* power save */ +#ifdef CONFIG_LBA48 + unsigned char lba48 = 0; + + if (blknr & 0x0000fffff0000000) { + /* more than 28 bits used, use 48bit mode */ + lba48 = 1; + } +#endif + debug ("ide_read dev %d start %qX, blocks %lX buffer at %lX\n", + device, blknr, blkcnt, (ulong)buffer); + + ide_led (DEVICE_LED(device), 1); /* LED on */ + + /* Select device + */ + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); + c = ide_wait (device, IDE_TIME_OUT); + + if (c & ATA_STAT_BUSY) { + printf ("IDE read: device %d not ready\n", device); + goto IDE_READ_E; + } + + /* first check if the drive is in Powersaving mode, if yes, + * increase the timeout value */ + ide_outb (device, ATA_COMMAND, ATA_CMD_CHK_PWR); + udelay (50); + + c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */ + + if (c & ATA_STAT_BUSY) { + printf ("IDE read: device %d not ready\n", device); + goto IDE_READ_E; + } + if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) { + printf ("No Powersaving mode %X\n", c); + } else { + c = ide_inb(device,ATA_SECT_CNT); + debug ("Powersaving %02X\n",c); + if(c==0) + pwrsave=1; + } + + + while (blkcnt-- > 0) { + + c = ide_wait (device, IDE_TIME_OUT); + + if (c & ATA_STAT_BUSY) { + printf ("IDE read: device %d not ready\n", device); + break; + } +#ifdef CONFIG_LBA48 + if (lba48) { + /* write high bits */ + ide_outb (device, ATA_SECT_CNT, 0); + ide_outb (device, ATA_LBA_LOW, (blknr >> 24) & 0xFF); + ide_outb (device, ATA_LBA_MID, (blknr >> 32) & 0xFF); + ide_outb (device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF); + } +#endif + ide_outb (device, ATA_SECT_CNT, 1); + ide_outb (device, ATA_LBA_LOW, (blknr >> 0) & 0xFF); + ide_outb (device, ATA_LBA_MID, (blknr >> 8) & 0xFF); + ide_outb (device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF); + +#ifdef CONFIG_LBA48 + if (lba48) { + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) ); + ide_outb (device, ATA_COMMAND, ATA_CMD_READ_EXT); + + } else +#endif + { + ide_outb (device, ATA_DEV_HD, ATA_LBA | + ATA_DEVICE(device) | + ((blknr >> 24) & 0xF) ); + ide_outb (device, ATA_COMMAND, ATA_CMD_READ); + } + + udelay (50); + + if(pwrsave) { + c = ide_wait (device, IDE_SPIN_UP_TIME_OUT); /* may take up to 4 sec */ + pwrsave=0; + } else { + c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */ + } + + if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) { +#if defined(CFG_64BIT_LBA) && defined(CFG_64BIT_VSPRINTF) + printf ("Error (no IRQ) dev %d blk %qd: status 0x%02x\n", + device, blknr, c); +#else + printf ("Error (no IRQ) dev %d blk %ld: status 0x%02x\n", + device, (ulong)blknr, c); +#endif + break; + } + + input_data (device, buffer, ATA_SECTORWORDS); + (void) ide_inb (device, ATA_STATUS); /* clear IRQ */ + + ++n; + ++blknr; + buffer += ATA_SECTORWORDS; + } +IDE_READ_E: + ide_led (DEVICE_LED(device), 0); /* LED off */ + return (n); +} + +/* ------------------------------------------------------------------------- */ + + +ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer) +{ + ulong n = 0; + unsigned char c; +#ifdef CONFIG_LBA48 + unsigned char lba48 = 0; + + if (blknr & 0x0000fffff0000000) { + /* more than 28 bits used, use 48bit mode */ + lba48 = 1; + } +#endif + + ide_led (DEVICE_LED(device), 1); /* LED on */ + + /* Select device + */ + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); + + while (blkcnt-- > 0) { + + c = ide_wait (device, IDE_TIME_OUT); + + if (c & ATA_STAT_BUSY) { + printf ("IDE read: device %d not ready\n", device); + goto WR_OUT; + } +#ifdef CONFIG_LBA48 + if (lba48) { + /* write high bits */ + ide_outb (device, ATA_SECT_CNT, 0); + ide_outb (device, ATA_LBA_LOW, (blknr >> 24) & 0xFF); + ide_outb (device, ATA_LBA_MID, (blknr >> 32) & 0xFF); + ide_outb (device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF); + } +#endif + ide_outb (device, ATA_SECT_CNT, 1); + ide_outb (device, ATA_LBA_LOW, (blknr >> 0) & 0xFF); + ide_outb (device, ATA_LBA_MID, (blknr >> 8) & 0xFF); + ide_outb (device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF); + +#ifdef CONFIG_LBA48 + if (lba48) { + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) ); + ide_outb (device, ATA_COMMAND, ATA_CMD_WRITE_EXT); + + } else +#endif + { + ide_outb (device, ATA_DEV_HD, ATA_LBA | + ATA_DEVICE(device) | + ((blknr >> 24) & 0xF) ); + ide_outb (device, ATA_COMMAND, ATA_CMD_WRITE); + } + + udelay (50); + + c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */ + + if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) { +#if defined(CFG_64BIT_LBA) && defined(CFG_64BIT_VSPRINTF) + printf ("Error (no IRQ) dev %d blk %qd: status 0x%02x\n", + device, blknr, c); +#else + printf ("Error (no IRQ) dev %d blk %ld: status 0x%02x\n", + device, (ulong)blknr, c); +#endif + goto WR_OUT; + } + + output_data (device, buffer, ATA_SECTORWORDS); + c = ide_inb (device, ATA_STATUS); /* clear IRQ */ + ++n; + ++blknr; + buffer += ATA_SECTORWORDS; + } +WR_OUT: + ide_led (DEVICE_LED(device), 0); /* LED off */ + return (n); +} + +/* ------------------------------------------------------------------------- */ + +/* + * copy src to dest, skipping leading and trailing blanks and null + * terminate the string + * "len" is the size of available memory including the terminating '\0' + */ +static void ident_cpy (unsigned char *dst, unsigned char *src, unsigned int len) +{ + unsigned char *end, *last; + + last = dst; + end = src + len - 1; + + /* reserve space for '\0' */ + if (len < 2) + goto OUT; + + /* skip leading white space */ + while ((*src) && (srcim_cpm.cp_pbdat &= ~(CFG_PB_12V_ENABLE); /* 12V Enable output OFF */ + immr->im_cpm.cp_pbpar &= ~(CFG_PB_12V_ENABLE); + immr->im_cpm.cp_pbodr &= ~(CFG_PB_12V_ENABLE); + immr->im_cpm.cp_pbdir |= CFG_PB_12V_ENABLE; + + /* wait 500 ms for the voltage to stabilize + */ + for (i=0; i<500; ++i) { + udelay (1000); + } + + immr->im_cpm.cp_pbdat |= CFG_PB_12V_ENABLE; /* 12V Enable output ON */ +#endif /* CFG_PB_12V_ENABLE */ + +#ifdef CFG_PB_IDE_MOTOR + /* configure IDE Motor voltage monitor pin as input */ + immr->im_cpm.cp_pbpar &= ~(CFG_PB_IDE_MOTOR); + immr->im_cpm.cp_pbodr &= ~(CFG_PB_IDE_MOTOR); + immr->im_cpm.cp_pbdir &= ~(CFG_PB_IDE_MOTOR); + + /* wait up to 1 s for the motor voltage to stabilize + */ + for (i=0; i<1000; ++i) { + if ((immr->im_cpm.cp_pbdat & CFG_PB_IDE_MOTOR) != 0) { + break; + } + udelay (1000); + } + + if (i == 1000) { /* Timeout */ + printf ("\nWarning: 5V for IDE Motor missing\n"); +# ifdef CONFIG_STATUS_LED +# ifdef STATUS_LED_YELLOW + status_led_set (STATUS_LED_YELLOW, STATUS_LED_ON ); +# endif +# ifdef STATUS_LED_GREEN + status_led_set (STATUS_LED_GREEN, STATUS_LED_OFF); +# endif +# endif /* CONFIG_STATUS_LED */ + } +#endif /* CFG_PB_IDE_MOTOR */ + + WATCHDOG_RESET(); + + /* de-assert RESET signal */ + ide_set_reset(0); + + /* wait 250 ms */ + for (i=0; i<250; ++i) { + udelay (1000); + } +} + +#endif /* CONFIG_IDE_RESET */ + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_IDE_LED) && \ + !defined(CONFIG_AMIGAONEG3SE)&& \ + !defined(CONFIG_CPC45) && \ + !defined(CONFIG_HMI10) && \ + !defined(CONFIG_KUP4K) && \ + !defined(CONFIG_KUP4X) + +static uchar led_buffer = 0; /* Buffer for current LED status */ + +static void ide_led (uchar led, uchar status) +{ + uchar *led_port = LED_PORT; + + if (status) { /* switch LED on */ + led_buffer |= led; + } else { /* switch LED off */ + led_buffer &= ~led; + } + + *led_port = led_buffer; +} + +#endif /* CONFIG_IDE_LED */ + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_ATAPI +/**************************************************************************** + * ATAPI Support + */ + +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +/* since ATAPI may use commands with not 4 bytes alligned length + * we have our own transfer functions, 2 bytes alligned */ +static void +output_data_shorts(int dev, ushort *sect_buf, int shorts) +{ +#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN); + pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD); + while (shorts--) { + EIEIO; + *pbuf_even = *dbuf++; + EIEIO; + *pbuf_odd = *dbuf++; + } +#else + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); + dbuf = (ushort *)sect_buf; + + debug ("in output data shorts base for read is %lx\n", (unsigned long) pbuf); + + while (shorts--) { + EIEIO; + *pbuf = *dbuf++; + } +#endif +} + +static void +input_data_shorts(int dev, ushort *sect_buf, int shorts) +{ +#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN); + pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD); + while (shorts--) { + EIEIO; + *dbuf++ = *pbuf_even; + EIEIO; + *dbuf++ = *pbuf_odd; + } +#else + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); + dbuf = (ushort *)sect_buf; + + debug("in input data shorts base for read is %lx\n", (unsigned long) pbuf); + + while (shorts--) { + EIEIO; + *dbuf++ = *pbuf; + } +#endif +} + +#else /* ! __PPC__ */ +static void +output_data_shorts(int dev, ushort *sect_buf, int shorts) +{ + outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, shorts); +} + +static void +input_data_shorts(int dev, ushort *sect_buf, int shorts) +{ + insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, shorts); +} + +#endif /* __PPC__ */ + +/* + * Wait until (Status & mask) == res, or timeout (in ms) + * Return last status + * This is used since some ATAPI CD ROMs clears their Busy Bit first + * and then they set their DRQ Bit + */ +static uchar atapi_wait_mask (int dev, ulong t,uchar mask, uchar res) +{ + ulong delay = 10 * t; /* poll every 100 us */ + uchar c; + + c = ide_inb(dev,ATA_DEV_CTL); /* prevents to read the status before valid */ + while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) { + /* break if error occurs (doesn't make sense to wait more) */ + if((c & ATA_STAT_ERR)==ATA_STAT_ERR) + break; + udelay (100); + if (delay-- == 0) { + break; + } + } + return (c); +} + +/* + * issue an atapi command + */ +unsigned char atapi_issue(int device,unsigned char* ccb,int ccblen, unsigned char * buffer,int buflen) +{ + unsigned char c,err,mask,res; + int n; + ide_led (DEVICE_LED(device), 1); /* LED on */ + + /* Select device + */ + mask = ATA_STAT_BUSY|ATA_STAT_DRQ; + res = 0; +#ifdef CONFIG_AMIGAONEG3SE +# warning THF: Removed LBA mode ??? +#endif + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); + c = atapi_wait_mask(device,ATAPI_TIME_OUT,mask,res); + if ((c & mask) != res) { + printf ("ATAPI_ISSUE: device %d not ready status %X\n", device,c); + err=0xFF; + goto AI_OUT; + } + /* write taskfile */ + ide_outb (device, ATA_ERROR_REG, 0); /* no DMA, no overlaped */ + ide_outb (device, ATA_SECT_CNT, 0); + ide_outb (device, ATA_SECT_NUM, 0); + ide_outb (device, ATA_CYL_LOW, (unsigned char)(buflen & 0xFF)); + ide_outb (device, ATA_CYL_HIGH, (unsigned char)((buflen>>8) & 0xFF)); +#ifdef CONFIG_AMIGAONEG3SE +# warning THF: Removed LBA mode ??? +#endif + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); + + ide_outb (device, ATA_COMMAND, ATAPI_CMD_PACKET); + udelay (50); + + mask = ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR; + res = ATA_STAT_DRQ; + c = atapi_wait_mask(device,ATAPI_TIME_OUT,mask,res); + + if ((c & mask) != res) { /* DRQ must be 1, BSY 0 */ + printf ("ATTAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",device,c); + err=0xFF; + goto AI_OUT; + } + + output_data_shorts (device, (unsigned short *)ccb,ccblen/2); /* write command block */ + /* ATAPI Command written wait for completition */ + udelay (5000); /* device must set bsy */ + + mask = ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR; + /* if no data wait for DRQ = 0 BSY = 0 + * if data wait for DRQ = 1 BSY = 0 */ + res=0; + if(buflen) + res = ATA_STAT_DRQ; + c = atapi_wait_mask(device,ATAPI_TIME_OUT,mask,res); + if ((c & mask) != res ) { + if (c & ATA_STAT_ERR) { + err=(ide_inb(device,ATA_ERROR_REG))>>4; + debug ("atapi_issue 1 returned sense key %X status %02X\n",err,c); + } else { + printf ("ATTAPI_ISSUE: (no DRQ) after sending ccb (%x) status 0x%02x\n", ccb[0],c); + err=0xFF; + } + goto AI_OUT; + } + n=ide_inb(device, ATA_CYL_HIGH); + n<<=8; + n+=ide_inb(device, ATA_CYL_LOW); + if(n>buflen) { + printf("ERROR, transfer bytes %d requested only %d\n",n,buflen); + err=0xff; + goto AI_OUT; + } + if((n==0)&&(buflen<0)) { + printf("ERROR, transfer bytes %d requested %d\n",n,buflen); + err=0xff; + goto AI_OUT; + } + if(n!=buflen) { + debug ("WARNING, transfer bytes %d not equal with requested %d\n",n,buflen); + } + if(n!=0) { /* data transfer */ + debug ("ATAPI_ISSUE: %d Bytes to transfer\n",n); + /* we transfer shorts */ + n>>=1; + /* ok now decide if it is an in or output */ + if ((ide_inb(device, ATA_SECT_CNT)&0x02)==0) { + debug ("Write to device\n"); + output_data_shorts(device,(unsigned short *)buffer,n); + } else { + debug ("Read from device @ %p shorts %d\n",buffer,n); + input_data_shorts(device,(unsigned short *)buffer,n); + } + } + udelay(5000); /* seems that some CD ROMs need this... */ + mask = ATA_STAT_BUSY|ATA_STAT_ERR; + res=0; + c = atapi_wait_mask(device,ATAPI_TIME_OUT,mask,res); + if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) { + err=(ide_inb(device,ATA_ERROR_REG) >> 4); + debug ("atapi_issue 2 returned sense key %X status %X\n",err,c); + } else { + err = 0; + } +AI_OUT: + ide_led (DEVICE_LED(device), 0); /* LED off */ + return (err); +} + +/* + * sending the command to atapi_issue. If an status other than good + * returns, an request_sense will be issued + */ + +#define ATAPI_DRIVE_NOT_READY 100 +#define ATAPI_UNIT_ATTN 10 + +unsigned char atapi_issue_autoreq (int device, + unsigned char* ccb, + int ccblen, + unsigned char *buffer, + int buflen) +{ + unsigned char sense_data[18],sense_ccb[12]; + unsigned char res,key,asc,ascq; + int notready,unitattn; + +#ifdef CONFIG_AMIGAONEG3SE + char *s; + unsigned int timeout, retrycnt; + + s = getenv("ide_cd_timeout"); + timeout = s ? (simple_strtol(s, NULL, 10)*1000000)/5 : 0; + + retrycnt = 0; +#endif + + unitattn=ATAPI_UNIT_ATTN; + notready=ATAPI_DRIVE_NOT_READY; + +retry: + res= atapi_issue(device,ccb,ccblen,buffer,buflen); + if (res==0) + return (0); /* Ok */ + + if (res==0xFF) + return (0xFF); /* error */ + + debug ("(auto_req)atapi_issue returned sense key %X\n",res); + + memset(sense_ccb,0,sizeof(sense_ccb)); + memset(sense_data,0,sizeof(sense_data)); + sense_ccb[0]=ATAPI_CMD_REQ_SENSE; + sense_ccb[4]=18; /* allocation Length */ + + res=atapi_issue(device,sense_ccb,12,sense_data,18); + key=(sense_data[2]&0xF); + asc=(sense_data[12]); + ascq=(sense_data[13]); + + debug ("ATAPI_CMD_REQ_SENSE returned %x\n",res); + debug (" Sense page: %02X key %02X ASC %02X ASCQ %02X\n", + sense_data[0], + key, + asc, + ascq); + + if((key==0)) + return 0; /* ok device ready */ + + if((key==6)|| (asc==0x29) || (asc==0x28)) { /* Unit Attention */ + if(unitattn-->0) { + udelay(200*1000); + goto retry; + } + printf("Unit Attention, tried %d\n",ATAPI_UNIT_ATTN); + goto error; + } + if((asc==0x4) && (ascq==0x1)) { /* not ready, but will be ready soon */ + if (notready-->0) { + udelay(200*1000); + goto retry; + } + printf("Drive not ready, tried %d times\n",ATAPI_DRIVE_NOT_READY); + goto error; + } + if(asc==0x3a) { + debug ("Media not present\n"); + goto error; + } + +#ifdef CONFIG_AMIGAONEG3SE + if ((sense_data[2]&0xF)==0x0B) { + debug ("ABORTED COMMAND...retry\n"); + if (retrycnt++ < 4) + goto retry; + return (0xFF); + } + + if ((sense_data[2]&0xf) == 0x02 && + sense_data[12] == 0x04 && + sense_data[13] == 0x01 ) { + debug ("Waiting for unit to become active\n"); + udelay(timeout); + if (retrycnt++ < 4) + goto retry; + return 0xFF; + } +#endif /* CONFIG_AMIGAONEG3SE */ + + printf ("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n",key,asc,ascq); +error: + debug ("ERROR Sense key %02X ASC %02X ASCQ %02X\n",key,asc,ascq); + return (0xFF); +} + + +static void atapi_inquiry(block_dev_desc_t * dev_desc) +{ + unsigned char ccb[12]; /* Command descriptor block */ + unsigned char iobuf[64]; /* temp buf */ + unsigned char c; + int device; + + device=dev_desc->dev; + dev_desc->type=DEV_TYPE_UNKNOWN; /* not yet valid */ + dev_desc->block_read=atapi_read; + + memset(ccb,0,sizeof(ccb)); + memset(iobuf,0,sizeof(iobuf)); + + ccb[0]=ATAPI_CMD_INQUIRY; + ccb[4]=40; /* allocation Legnth */ + c=atapi_issue_autoreq(device,ccb,12,(unsigned char *)iobuf,40); + + debug ("ATAPI_CMD_INQUIRY returned %x\n",c); + if (c!=0) + return; + + /* copy device ident strings */ + ident_cpy(dev_desc->vendor,&iobuf[8],8); + ident_cpy(dev_desc->product,&iobuf[16],16); + ident_cpy(dev_desc->revision,&iobuf[32],5); + + dev_desc->lun=0; + dev_desc->lba=0; + dev_desc->blksz=0; + dev_desc->type=iobuf[0] & 0x1f; + + if ((iobuf[1]&0x80)==0x80) + dev_desc->removable = 1; + else + dev_desc->removable = 0; + + memset(ccb,0,sizeof(ccb)); + memset(iobuf,0,sizeof(iobuf)); + ccb[0]=ATAPI_CMD_START_STOP; + ccb[4]=0x03; /* start */ + + c=atapi_issue_autoreq(device,ccb,12,(unsigned char *)iobuf,0); + + debug ("ATAPI_CMD_START_STOP returned %x\n",c); + if (c!=0) + return; + + memset(ccb,0,sizeof(ccb)); + memset(iobuf,0,sizeof(iobuf)); + c=atapi_issue_autoreq(device,ccb,12,(unsigned char *)iobuf,0); + + debug ("ATAPI_CMD_UNIT_TEST_READY returned %x\n",c); + if (c!=0) + return; + + memset(ccb,0,sizeof(ccb)); + memset(iobuf,0,sizeof(iobuf)); + ccb[0]=ATAPI_CMD_READ_CAP; + c=atapi_issue_autoreq(device,ccb,12,(unsigned char *)iobuf,8); + debug ("ATAPI_CMD_READ_CAP returned %x\n",c); + if (c!=0) + return; + + debug ("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n", + iobuf[0],iobuf[1],iobuf[2],iobuf[3], + iobuf[4],iobuf[5],iobuf[6],iobuf[7]); + + dev_desc->lba =((unsigned long)iobuf[0]<<24) + + ((unsigned long)iobuf[1]<<16) + + ((unsigned long)iobuf[2]<< 8) + + ((unsigned long)iobuf[3]); + dev_desc->blksz=((unsigned long)iobuf[4]<<24) + + ((unsigned long)iobuf[5]<<16) + + ((unsigned long)iobuf[6]<< 8) + + ((unsigned long)iobuf[7]); +#ifdef CONFIG_LBA48 + dev_desc->lba48 = 0; /* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */ +#endif + return; +} + + +/* + * atapi_read: + * we transfer only one block per command, since the multiple DRQ per + * command is not yet implemented + */ +#define ATAPI_READ_MAX_BYTES 2048 /* we read max 2kbytes */ +#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */ +#define ATAPI_READ_MAX_BLOCK ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE /* max blocks */ + +ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer) +{ + ulong n = 0; + unsigned char ccb[12]; /* Command descriptor block */ + ulong cnt; + + debug ("atapi_read dev %d start %lX, blocks %lX buffer at %lX\n", + device, blknr, blkcnt, (ulong)buffer); + + do { + if (blkcnt>ATAPI_READ_MAX_BLOCK) { + cnt=ATAPI_READ_MAX_BLOCK; + } else { + cnt=blkcnt; + } + ccb[0]=ATAPI_CMD_READ_12; + ccb[1]=0; /* reserved */ + ccb[2]=(unsigned char) (blknr>>24) & 0xFF; /* MSB Block */ + ccb[3]=(unsigned char) (blknr>>16) & 0xFF; /* */ + ccb[4]=(unsigned char) (blknr>> 8) & 0xFF; + ccb[5]=(unsigned char) blknr & 0xFF; /* LSB Block */ + ccb[6]=(unsigned char) (cnt >>24) & 0xFF; /* MSB Block count */ + ccb[7]=(unsigned char) (cnt >>16) & 0xFF; + ccb[8]=(unsigned char) (cnt >> 8) & 0xFF; + ccb[9]=(unsigned char) cnt & 0xFF; /* LSB Block */ + ccb[10]=0; /* reserved */ + ccb[11]=0; /* reserved */ + + if (atapi_issue_autoreq(device,ccb,12, + (unsigned char *)buffer, + cnt*ATAPI_READ_BLOCK_SIZE) == 0xFF) { + return (n); + } + n+=cnt; + blkcnt-=cnt; + blknr+=cnt; + buffer+=cnt*(ATAPI_READ_BLOCK_SIZE/4); /* ulong blocksize in ulong */ + } while (blkcnt > 0); + return (n); +} + +/* ------------------------------------------------------------------------- */ + +#endif /* CONFIG_ATAPI */ + +U_BOOT_CMD( + ide, 5, 1, do_ide, + "ide - IDE sub-system\n", + "reset - reset IDE controller\n" + "ide info - show available IDE devices\n" + "ide device [dev] - show or set current device\n" + "ide part [dev] - print partition table of one or all IDE devices\n" + "ide read addr blk# cnt\n" + "ide write addr blk# cnt - read/write `cnt'" + " blocks starting at block `blk#'\n" + " to/from memory address `addr'\n" +); + +U_BOOT_CMD( + diskboot, 3, 1, do_diskboot, + "diskboot- boot from IDE device\n", + "loadAddr dev:part\n" +); + +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ diff --git a/common/cmd_immap.c b/common/cmd_immap.c new file mode 100644 index 0000000..559d7b4 --- /dev/null +++ b/common/cmd_immap.c @@ -0,0 +1,721 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8xx/MPC8260 Internal Memory Map Functions + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_IMMAP) && \ + (defined(CONFIG_8xx) || defined(CONFIG_8260)) + +#if defined(CONFIG_8xx) +#include +#include +#include +#elif defined(CONFIG_8260) +#include +#include +#include +#endif + +static void +unimplemented ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf ("Sorry, but the '%s' command has not been implemented\n", + cmdtp->name); +} + +int +do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + +#if defined(CONFIG_8xx) + volatile sysconf8xx_t *sc = &immap->im_siu_conf; +#elif defined(CONFIG_8260) + volatile sysconf8260_t *sc = &immap->im_siu_conf; +#endif + + printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr); +#if defined(CONFIG_8xx) + printf ("SWT = %08x\n", sc->sc_swt); + printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask); + printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec); + printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr); +#elif defined(CONFIG_8260) + printf ("BCR = %08x\n", sc->sc_bcr); + printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n", + sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl); + printf ("L_ACR = %02x L_ALRH= %08x L_ALRL= %08x\n", + sc->sc_lcl_acr, sc->sc_lcl_alrh, sc->sc_lcl_alrl); + printf ("PTESR1= %08x PTESR2= %08x\n", sc->sc_tescr1, sc->sc_tescr2); + printf ("LTESR1= %08x LTESR2= %08x\n", sc->sc_ltescr1, sc->sc_ltescr2); + printf ("PDTEA = %08x PDTEM = %02x\n", sc->sc_pdtea, sc->sc_pdtem); + printf ("LDTEA = %08x LDTEM = %02x\n", sc->sc_ldtea, sc->sc_ldtem); +#endif + return 0; +} + +int +do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + +#if defined(CONFIG_8xx) + volatile memctl8xx_t *memctl = &immap->im_memctl; + int nbanks = 8; +#elif defined(CONFIG_8260) + volatile memctl8260_t *memctl = &immap->im_memctl; + int nbanks = 12; +#endif + volatile uint *p = &memctl->memc_br0; + int i; + + for (i = 0; i < nbanks; i++, p += 2) { + if (i < 10) { + printf ("BR%d = %08x OR%d = %08x\n", + i, p[0], i, p[1]); + } else { + printf ("BR%d = %08x OR%d = %08x\n", + i, p[0], i, p[1]); + } + } + + printf ("MAR = %08x", memctl->memc_mar); +#if defined(CONFIG_8xx) + printf (" MCR = %08x\n", memctl->memc_mcr); +#elif defined(CONFIG_8260) + putc ('\n'); +#endif + printf ("MAMR = %08x MBMR = %08x", + memctl->memc_mamr, memctl->memc_mbmr); +#if defined(CONFIG_8xx) + printf ("\nMSTAT = %04x\n", memctl->memc_mstat); +#elif defined(CONFIG_8260) + printf (" MCMR = %08x\n", memctl->memc_mcmr); +#endif + printf ("MPTPR = %04x MDR = %08x\n", + memctl->memc_mptpr, memctl->memc_mdr); +#if defined(CONFIG_8260) + printf ("PSDMR = %08x LSDMR = %08x\n", + memctl->memc_psdmr, memctl->memc_lsdmr); + printf ("PURT = %02x PSRT = %02x\n", + memctl->memc_purt, memctl->memc_psrt); + printf ("LURT = %02x LSRT = %02x\n", + memctl->memc_lurt, memctl->memc_lsrt); + printf ("IMMR = %08x\n", memctl->memc_immr); +#endif + return 0; +} + +int +do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +#ifdef CONFIG_8260 +int +do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} +#endif + +int +do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + +#if defined(CONFIG_8xx) + volatile car8xx_t *car = &immap->im_clkrst; +#elif defined(CONFIG_8260) + volatile car8260_t *car = &immap->im_clkrst; +#endif + +#if defined(CONFIG_8xx) + printf ("SCCR = %08x\n", car->car_sccr); + printf ("PLPRCR= %08x\n", car->car_plprcr); + printf ("RSR = %08x\n", car->car_rsr); +#elif defined(CONFIG_8260) + printf ("SCCR = %08x\n", car->car_sccr); + printf ("SCMR = %08x\n", car->car_scmr); + printf ("RSR = %08x\n", car->car_rsr); + printf ("RMR = %08x\n", car->car_rmr); +#endif + return 0; +} + +static int counter; + +static void +header(void) +{ + char *data = "\ + -------------------------------- --------------------------------\ + 00000000001111111111222222222233 00000000001111111111222222222233\ + 01234567890123456789012345678901 01234567890123456789012345678901\ + -------------------------------- --------------------------------\ + "; + int i; + + if (counter % 2) + putc('\n'); + counter = 0; + + for (i = 0; i < 4; i++, data += 79) + printf("%.79s\n", data); +} + +static void binary (char *label, uint value, int nbits) +{ + uint mask = 1 << (nbits - 1); + int i, second = (counter++ % 2); + + if (second) + putc (' '); + puts (label); + for (i = 32 + 1; i != nbits; i--) + putc (' '); + + while (mask != 0) { + if (value & mask) + putc ('1'); + else + putc ('0'); + mask >>= 1; + } + + if (second) + putc ('\n'); +} + +#if defined(CONFIG_8xx) +#define PA_NBITS 16 +#define PA_NB_ODR 8 +#define PB_NBITS 18 +#define PB_NB_ODR 16 +#define PC_NBITS 12 +#define PD_NBITS 13 +#elif defined(CONFIG_8260) +#define PA_NBITS 32 +#define PA_NB_ODR 32 +#define PB_NBITS 28 +#define PB_NB_ODR 28 +#define PC_NBITS 32 +#define PD_NBITS 28 +#endif + +int +do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + +#if defined(CONFIG_8xx) + volatile iop8xx_t *iop = &immap->im_ioport; + volatile ushort *l, *r; +#elif defined(CONFIG_8260) + volatile iop8260_t *iop = &immap->im_ioport; + volatile uint *l, *r; +#endif + volatile uint *R; + + counter = 0; + header (); + + /* + * Ports A & B + */ + +#if defined(CONFIG_8xx) + l = &iop->iop_padir; + R = &immap->im_cpm.cp_pbdir; +#elif defined(CONFIG_8260) + l = &iop->iop_pdira; + R = &iop->iop_pdirb; +#endif + binary ("PA_DIR", *l++, PA_NBITS); + binary ("PB_DIR", *R++, PB_NBITS); + binary ("PA_PAR", *l++, PA_NBITS); + binary ("PB_PAR", *R++, PB_NBITS); +#if defined(CONFIG_8260) + binary ("PA_SOR", *l++, PA_NBITS); + binary ("PB_SOR", *R++, PB_NBITS); +#endif + binary ("PA_ODR", *l++, PA_NB_ODR); + binary ("PB_ODR", *R++, PB_NB_ODR); + binary ("PA_DAT", *l++, PA_NBITS); + binary ("PB_DAT", *R++, PB_NBITS); + + header (); + + /* + * Ports C & D + */ + +#if defined(CONFIG_8xx) + l = &iop->iop_pcdir; + r = &iop->iop_pddir; +#elif defined(CONFIG_8260) + l = &iop->iop_pdirc; + r = &iop->iop_pdird; +#endif + binary ("PC_DIR", *l++, PC_NBITS); + binary ("PD_DIR", *r++, PD_NBITS); + binary ("PC_PAR", *l++, PC_NBITS); + binary ("PD_PAR", *r++, PD_NBITS); +#if defined(CONFIG_8xx) + binary ("PC_SO ", *l++, PC_NBITS); + binary (" ", 0, 0); + r++; +#elif defined(CONFIG_8260) + binary ("PC_SOR", *l++, PC_NBITS); + binary ("PD_SOR", *r++, PD_NBITS); + binary ("PC_ODR", *l++, PC_NBITS); + binary ("PD_ODR", *r++, PD_NBITS); +#endif + binary ("PC_DAT", *l++, PC_NBITS); + binary ("PD_DAT", *r++, PD_NBITS); +#if defined(CONFIG_8xx) + binary ("PC_INT", *l++, PC_NBITS); +#endif + + header (); + return 0; +} + +/* + * set the io pins + * this needs a clean up for smaller tighter code + * use *uint and set the address based on cmd + port + */ +int +do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uint rcode = 0; + iopin_t iopin; + static uint port = 0; + static uint pin = 0; + static uint value = 0; + static enum { + DIR, + PAR, + SOR, + ODR, + DAT, +#if defined(CONFIG_8xx) + INT +#endif + } cmd = DAT; + + if (argc != 5) { + puts ("iopset PORT PIN CMD VALUE\n"); + return 1; + } + port = argv[1][0] - 'A'; + if (port > 3) + port -= 0x20; + if (port > 3) + rcode = 1; + pin = simple_strtol (argv[2], NULL, 10); + if (pin > 31) + rcode = 1; + + + switch (argv[3][0]) { + case 'd': + if (argv[3][1] == 'a') + cmd = DAT; + else if (argv[3][1] == 'i') + cmd = DIR; + else + rcode = 1; + break; + case 'p': + cmd = PAR; + break; + case 'o': + cmd = ODR; + break; + case 's': + cmd = SOR; + break; +#if defined(CONFIG_8xx) + case 'i': + cmd = INT; + break; +#endif + default: + printf ("iopset: unknown command %s\n", argv[3]); + rcode = 1; + } + if (argv[4][0] == '1') + value = 1; + else if (argv[4][0] == '0') + value = 0; + else + rcode = 1; + if (rcode == 0) { + iopin.port = port; + iopin.pin = pin; + iopin.flag = 0; + switch (cmd) { + case DIR: + if (value) + iopin_set_out (&iopin); + else + iopin_set_in (&iopin); + break; + case PAR: + if (value) + iopin_set_ded (&iopin); + else + iopin_set_gen (&iopin); + break; + case SOR: + if (value) + iopin_set_opt2 (&iopin); + else + iopin_set_opt1 (&iopin); + break; + case ODR: + if (value) + iopin_set_odr (&iopin); + else + iopin_set_act (&iopin); + break; + case DAT: + if (value) + iopin_set_high (&iopin); + else + iopin_set_low (&iopin); + break; +#if defined(CONFIG_8xx) + case INT: + if (value) + iopin_set_falledge (&iopin); + else + iopin_set_anyedge (&iopin); + break; +#endif + } + + } + return rcode; +} + +int +do_dmainfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_fccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +static void prbrg (int n, uint val) +{ + uint extc = (val >> 14) & 3; + uint cd = (val & CPM_BRG_CD_MASK) >> 1; + uint div16 = (val & CPM_BRG_DIV16) != 0; + +#if defined(CONFIG_8xx) + DECLARE_GLOBAL_DATA_PTR; + ulong clock = gd->cpu_clk; +#elif defined(CONFIG_8260) + DECLARE_GLOBAL_DATA_PTR; + ulong clock = gd->brg_clk; +#endif + + printf ("BRG%d:", n); + + if (val & CPM_BRG_RST) + puts (" RESET"); + else + puts (" "); + + if (val & CPM_BRG_EN) + puts (" ENABLED"); + else + puts (" DISABLED"); + + printf (" EXTC=%d", extc); + + if (val & CPM_BRG_ATB) + puts (" ATB"); + else + puts (" "); + + printf (" DIVIDER=%4d", cd); + if (extc == 0 && cd != 0) { + uint baudrate; + + if (div16) + baudrate = (clock / 16) / (cd + 1); + else + baudrate = clock / (cd + 1); + + printf ("=%6d bps", baudrate); + } else { + puts (" "); + } + + if (val & CPM_BRG_DIV16) + puts (" DIV16"); + else + puts (" "); + + putc ('\n'); +} + +int +do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + +#if defined(CONFIG_8xx) + volatile cpm8xx_t *cp = &immap->im_cpm; + volatile uint *p = &cp->cp_brgc1; +#elif defined(CONFIG_8260) + volatile uint *p = &immap->im_brgc1; +#endif + int i = 1; + + while (i <= 4) + prbrg (i++, *p++); + +#if defined(CONFIG_8260) + p = &immap->im_brgc5; + while (i <= 8) + prbrg (i++, *p++); +#endif + return 0; +} + +int +do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + +#if defined(CONFIG_8xx) + volatile i2c8xx_t *i2c = &immap->im_i2c; + volatile cpm8xx_t *cp = &immap->im_cpm; + volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC]; +#elif defined(CONFIG_8260) + volatile i2c8260_t *i2c = &immap->im_i2c; + volatile iic_t *iip; + uint dpaddr; + + dpaddr = *((unsigned short *) (&immap->im_dprambase[PROFF_I2C_BASE])); + if (dpaddr == 0) + iip = NULL; + else + iip = (iic_t *) & immap->im_dprambase[dpaddr]; +#endif + + printf ("I2MOD = %02x I2ADD = %02x\n", i2c->i2c_i2mod, i2c->i2c_i2add); + printf ("I2BRG = %02x I2COM = %02x\n", i2c->i2c_i2brg, i2c->i2c_i2com); + printf ("I2CER = %02x I2CMR = %02x\n", i2c->i2c_i2cer, i2c->i2c_i2cmr); + + if (iip == NULL) + puts ("i2c parameter ram not allocated\n"); + else { + printf ("RBASE = %08x TBASE = %08x\n", + iip->iic_rbase, iip->iic_tbase); + printf ("RFCR = %02x TFCR = %02x\n", + iip->iic_rfcr, iip->iic_tfcr); + printf ("MRBLR = %04x\n", iip->iic_mrblr); + printf ("RSTATE= %08x RDP = %08x\n", + iip->iic_rstate, iip->iic_rdp); + printf ("RBPTR = %04x RBC = %04x\n", + iip->iic_rbptr, iip->iic_rbc); + printf ("RXTMP = %08x\n", iip->iic_rxtmp); + printf ("TSTATE= %08x TDP = %08x\n", + iip->iic_tstate, iip->iic_tdp); + printf ("TBPTR = %04x TBC = %04x\n", + iip->iic_tbptr, iip->iic_tbc); + printf ("TXTMP = %08x\n", iip->iic_txtmp); + } + return 0; +} + +int +do_sccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_smcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_spiinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_muxinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_siinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + siuinfo, 1, 1, do_siuinfo, + "siuinfo - print System Interface Unit (SIU) registers\n", + NULL +); + +U_BOOT_CMD( + memcinfo, 1, 1, do_memcinfo, + "memcinfo- print Memory Controller registers\n", + NULL +); + +U_BOOT_CMD( + sitinfo, 1, 1, do_sitinfo, + "sitinfo - print System Integration Timers (SIT) registers\n", + NULL +); + +#ifdef CONFIG_8260 +U_BOOT_CMD( + icinfo, 1, 1, do_icinfo, + "icinfo - print Interrupt Controller registers\n", + NULL +); +#endif + +U_BOOT_CMD( + carinfo, 1, 1, do_carinfo, + "carinfo - print Clocks and Reset registers\n", + NULL +); + +U_BOOT_CMD( + iopinfo, 1, 1, do_iopinfo, + "iopinfo - print I/O Port registers\n", + NULL +); + +U_BOOT_CMD( + iopset, 5, 0, do_iopset, + "iopset - set I/O Port registers\n", + "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1" +); + +U_BOOT_CMD( + dmainfo, 1, 1, do_dmainfo, + "dmainfo - print SDMA/IDMA registers\n", + NULL +); + +U_BOOT_CMD( + fccinfo, 1, 1, do_fccinfo, + "fccinfo - print FCC registers\n", + NULL +); + +U_BOOT_CMD( + brginfo, 1, 1, do_brginfo, + "brginfo - print Baud Rate Generator (BRG) registers\n", + NULL +); + +U_BOOT_CMD( + i2cinfo, 1, 1, do_i2cinfo, + "i2cinfo - print I2C registers\n", + NULL +); + +U_BOOT_CMD( + sccinfo, 1, 1, do_sccinfo, + "sccinfo - print SCC registers\n", + NULL +); + +U_BOOT_CMD( + smcinfo, 1, 1, do_smcinfo, + "smcinfo - print SMC registers\n", + NULL +); + +U_BOOT_CMD( + spiinfo, 1, 1, do_spiinfo, + "spiinfo - print Serial Peripheral Interface (SPI) registers\n", + NULL +); + +U_BOOT_CMD( + muxinfo, 1, 1, do_muxinfo, + "muxinfo - print CPM Multiplexing registers\n", + NULL +); + +U_BOOT_CMD( + siinfo, 1, 1, do_siinfo, + "siinfo - print Serial Interface (SI) registers\n", + NULL +); + +U_BOOT_CMD( + mccinfo, 1, 1, do_mccinfo, + "mccinfo - print MCC registers\n", + NULL +); + + +#endif /* CFG_CMD_IMMAP && (CONFIG_8xx || CONFIG_8260) */ diff --git a/common/cmd_itest.c b/common/cmd_itest.c new file mode 100644 index 0000000..8ad134f --- /dev/null +++ b/common/cmd_itest.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2003 + * Tait Electronics Limited, Christchurch, New Zealand + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file provides a shell like 'test' function to return + * true/false from an integer or string compare of two memory + * locations or a location and a scalar/literal. + * A few parts were lifted from bash 'test' command + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_ITEST) + +#define EQ 0 +#define NE 1 +#define LT 2 +#define GT 3 +#define LE 4 +#define GE 5 + +struct op_tbl_s { + char *op; /* operator string */ + int opcode; /* internal representation of opcode */ +}; + +typedef struct op_tbl_s op_tbl_t; + +op_tbl_t op_table [] = { + { "-lt", LT }, + { "<" , LT }, + { "-gt", GT }, + { ">" , GT }, + { "-eq", EQ }, + { "==" , EQ }, + { "-ne", NE }, + { "!=" , NE }, + { "<>" , NE }, + { "-ge", GE }, + { ">=" , GE }, + { "-le", LE }, + { "<=" , LE }, +}; + +#define op_tbl_size (sizeof(op_table)/sizeof(op_table[0])) + +extern int cmd_get_data_size(char* arg, int default_size); + +static long evalexp(char *s, int w) +{ + long l, *p; + + /* if the parameter starts with a * then assume is a pointer to the value we want */ + if (s[0] == '*') { + p = (long *)simple_strtoul(&s[1], NULL, 16); + l = *p; + } else { + l = simple_strtoul(s, NULL, 16); + } + + return (l & ((1 << (w * 8)) - 1)); +} + +static char * evalstr(char *s) +{ + /* if the parameter starts with a * then assume a string pointer else its a literal */ + if (s[0] == '*') { + return (char *)simple_strtoul(&s[1], NULL, 16); + } else { + return s; + } +} + +static int stringcomp(char *s, char *t, int op) +{ + int n, p; + char *l, *r; + + l = evalstr(s); + r = evalstr(t); + + /* we'll do a compare based on the length of the shortest string */ + n = min(strlen(l), strlen(r)); + + p = strncmp(l, r, n); + switch (op) { + case EQ: return (p == 0); + case NE: return (p != 0); + case LT: return (p < 0); + case GT: return (p > 0); + case LE: return (p <= 0); + case GE: return (p >= 0); + } + return (0); +} + +static int arithcomp (char *s, char *t, int op, int w) +{ + long l, r; + + l = evalexp (s, w); + r = evalexp (t, w); + + switch (op) { + case EQ: return (l == r); + case NE: return (l != r); + case LT: return (l < r); + case GT: return (l > r); + case LE: return (l <= r); + case GE: return (l >= r); + } + return (0); +} + +int binary_test (char *op, char *arg1, char *arg2, int w) +{ + int len, i; + op_tbl_t *optp; + + len = strlen(op); + + for (optp = (op_tbl_t *)&op_table, i = 0; + i < op_tbl_size; + optp++, i++) { + + if ((strncmp (op, optp->op, len) == 0) && (len == strlen (optp->op))) { + if (w == 0) { + return (stringcomp(arg1, arg2, optp->opcode)); + } else { + return (arithcomp (arg1, arg2, optp->opcode, w)); + } + } + } + + printf("Unknown operator '%s'\n", op); + return 0; /* op code not found */ +} + +/* command line interface to the shell test */ +int do_itest ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + int value, w; + + /* Validate arguments */ + if ((argc != 4)){ + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Check for a data width specification. + * Defaults to long (4) if no specification. + * Uses -2 as 'width' for .s (string) so as not to upset existing code + */ + switch (w = cmd_get_data_size(argv[0], 4)) { + case 1: + case 2: + case 4: + value = binary_test (argv[2], argv[1], argv[3], w); + break; + case -2: + value = binary_test (argv[2], argv[1], argv[3], 0); + break; + case -1: + default: + puts("Invalid data width specifier\n"); + value = 0; + break; + } + + return !value; +} + +U_BOOT_CMD( + itest, 4, 0, do_itest, + "itest\t- return true/false on integer compare\n", + "[.b, .w, .l, .s] [*]value1 [*]value2\n" +); +#endif /* CONFIG_COMMANDS & CFG_CMD_ITEST */ diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c new file mode 100644 index 0000000..34920b1 --- /dev/null +++ b/common/cmd_jffs2.c @@ -0,0 +1,2168 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Robert Schwebel, Pengutronix, + * + * (C) Copyright 2003 + * Kai-Uwe Bloem, Auerswald GmbH & Co KG, + * + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Added support for reading flash partition table from environment. + * Parsing routines are based on driver/mtd/cmdline.c from the linux 2.4 + * kernel tree. + * + * $Id: cmdlinepart.c,v 1.17 2004/11/26 11:18:47 lavinen Exp $ + * Copyright 2002 SYSGO Real-Time Solutions GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Three environment variables are used by the parsing routines: + * + * 'partition' - keeps current partition identifier + * + * partition := + * := ,part_num + * + * + * 'mtdids' - linux kernel mtd device id <-> u-boot device id mapping + * + * mtdids=[,,...] + * + * := = + * := 'nand'|'nor' + * := mtd device number, 0... + * := unique device tag used by linux kernel to find mtd device (mtd->name) + * + * + * 'mtdparts' - partition list + * + * mtdparts=mtdparts=[;...] + * + * := :[,...] + * := unique device tag used by linux kernel to find mtd device (mtd->name) + * := [@][][] + * := standard linux memsize OR '-' to denote all remaining space + * := partition start offset within the device + * := '(' NAME ')' + * := when set to 'ro' makes partition read-only (not used, passed to kernel) + * + * Notes: + * - each used in mtdparts must albo exist in 'mtddis' mapping + * - if the above variables are not set defaults for a given target are used + * + * Examples: + * + * 1 NOR Flash, with 1 single writable partition: + * mtdids=nor0=edb7312-nor + * mtdparts=mtdparts=edb7312-nor:- + * + * 1 NOR Flash with 2 partitions, 1 NAND with one + * mtdids=nor0=edb7312-nor,nand0=edb7312-nand + * mtdparts=mtdparts=edb7312-nor:256k(ARMboot)ro,-(root);edb7312-nand:-(home) + * + */ + +/* + * JFFS2/CRAMFS support + */ +#include +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include + +/* enable/disable debugging messages */ +#define DEBUG +#undef DEBUG + +#ifdef DEBUG +# define DEBUGF(fmt, args...) printf(fmt ,##args) +#else +# define DEBUGF(fmt, args...) +#endif + +/* special size referring to all the remaining space in a partition */ +#define SIZE_REMAINING 0xFFFFFFFF + +/* special offset value, it is used when not provided by user + * + * this value is used temporarily during parsing, later such offests + * are recalculated */ +#define OFFSET_NOT_SPECIFIED 0xFFFFFFFF + +/* minimum partition size */ +#define MIN_PART_SIZE 4096 + +/* this flag needs to be set in part_info struct mask_flags + * field for read-only partitions */ +#define MTD_WRITEABLE 1 + +#ifdef CONFIG_JFFS2_CMDLINE +/* default values for mtdids and mtdparts variables */ +#if defined(MTDIDS_DEFAULT) +static const char *const mtdids_default = MTDIDS_DEFAULT; +#else +#warning "MTDIDS_DEFAULT not defined!" +static const char *const mtdids_default = NULL; +#endif + +#if defined(MTDPARTS_DEFAULT) +static const char *const mtdparts_default = MTDPARTS_DEFAULT; +#else +#warning "MTDPARTS_DEFAULT not defined!" +static const char *const mtdparts_default = NULL; +#endif + +/* copies of last seen 'mtdids', 'mtdparts' and 'partition' env variables */ +#define MTDIDS_MAXLEN 128 +#define MTDPARTS_MAXLEN 512 +#define PARTITION_MAXLEN 16 +static char last_ids[MTDIDS_MAXLEN]; +static char last_parts[MTDPARTS_MAXLEN]; +static char last_partition[PARTITION_MAXLEN]; + +/* low level jffs2 cache cleaning routine */ +extern void jffs2_free_cache(struct part_info *part); + +/* mtdids mapping list, filled by parse_ids() */ +struct list_head mtdids; + +/* device/partition list, parse_cmdline() parses into here */ +struct list_head devices; +#endif /* #ifdef CONFIG_JFFS2_CMDLINE */ + +/* current active device and partition number */ +static struct mtd_device *current_dev = NULL; +static u8 current_partnum = 0; + +extern int cramfs_check (struct part_info *info); +extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename); +extern int cramfs_ls (struct part_info *info, char *filename); +extern int cramfs_info (struct part_info *info); + +static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num); + +/* command line only routines */ +#ifdef CONFIG_JFFS2_CMDLINE + +static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len); +static int device_del(struct mtd_device *dev); + +/** + * Parses a string into a number. The number stored at ptr is + * potentially suffixed with K (for kilobytes, or 1024 bytes), + * M (for megabytes, or 1048576 bytes), or G (for gigabytes, or + * 1073741824). If the number is suffixed with K, M, or G, then + * the return value is the number multiplied by one kilobyte, one + * megabyte, or one gigabyte, respectively. + * + * @param ptr where parse begins + * @param retptr output pointer to next char after parse completes (output) + * @return resulting unsigned int + */ +static unsigned long memsize_parse (const char *const ptr, const char **retptr) +{ + unsigned long ret = simple_strtoul(ptr, (char **)retptr, 0); + + switch (**retptr) { + case 'G': + case 'g': + ret <<= 10; + case 'M': + case 'm': + ret <<= 10; + case 'K': + case 'k': + ret <<= 10; + (*retptr)++; + default: + break; + } + + return ret; +} + +/** + * Format string describing supplied size. This routine does the opposite job + * to memsize_parse(). Size in bytes is converted to string and if possible + * shortened by using k (kilobytes), m (megabytes) or g (gigabytes) suffix. + * + * Note, that this routine does not check for buffer overflow, it's the caller + * who must assure enough space. + * + * @param buf output buffer + * @param size size to be converted to string + */ +static void memsize_format(char *buf, u32 size) +{ +#define SIZE_GB ((u32)1024*1024*1024) +#define SIZE_MB ((u32)1024*1024) +#define SIZE_KB ((u32)1024) + + if ((size % SIZE_GB) == 0) + sprintf(buf, "%lug", size/SIZE_GB); + else if ((size % SIZE_MB) == 0) + sprintf(buf, "%lum", size/SIZE_MB); + else if (size % SIZE_KB == 0) + sprintf(buf, "%luk", size/SIZE_KB); + else + sprintf(buf, "%lu", size); +} + +/** + * This routine does global indexing of all partitions. Resulting index for + * current partition is saved in 'mtddevnum'. Current partition name in + * 'mtddevname'. + */ +static void index_partitions(void) +{ + char buf[16]; + u16 mtddevnum; + struct part_info *part; + struct list_head *dentry; + struct mtd_device *dev; + + DEBUGF("--- index partitions ---\n"); + + if (current_dev) { + mtddevnum = 0; + list_for_each(dentry, &devices) { + dev = list_entry(dentry, struct mtd_device, link); + if (dev == current_dev) { + mtddevnum += current_partnum; + sprintf(buf, "%d", mtddevnum); + setenv("mtddevnum", buf); + break; + } + mtddevnum += dev->num_parts; + } + + part = jffs2_part_info(current_dev, current_partnum); + setenv("mtddevname", part->name); + + DEBUGF("=> mtddevnum %d,\n=> mtddevname %s\n", mtddevnum, part->name); + } else { + setenv("mtddevnum", NULL); + setenv("mtddevname", NULL); + + DEBUGF("=> mtddevnum NULL\n=> mtddevname NULL\n"); + } +} + +/** + * Save current device and partition in environment variable 'partition'. + */ +static void current_save(void) +{ + char buf[16]; + + DEBUGF("--- current_save ---\n"); + + if (current_dev) { + sprintf(buf, "%s%d,%d", MTD_DEV_TYPE(current_dev->id->type), + current_dev->id->num, current_partnum); + + setenv("partition", buf); + strncpy(last_partition, buf, 16); + + DEBUGF("=> partition %s\n", buf); + } else { + setenv("partition", NULL); + last_partition[0] = '\0'; + + DEBUGF("=> partition NULL\n"); + } + index_partitions(); +} + +/** + * Performs sanity check for supplied NOR flash partition. Table of existing + * NOR flash devices is searched and partition device is located. Alignment + * with the granularity of NOR flash sectors is verified. + * + * @param id of the parent device + * @param part partition to validate + * @return 0 if partition is valid, 1 otherwise + */ +static int part_validate_nor(struct mtdids *id, struct part_info *part) +{ +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + /* info for FLASH chips */ + extern flash_info_t flash_info[]; + flash_info_t *flash; + int offset_aligned; + u32 end_offset; + int i; + + flash = &flash_info[id->num]; + + offset_aligned = 0; + for (i = 0; i < flash->sector_count; i++) { + if ((flash->start[i] - flash->start[0]) == part->offset) { + offset_aligned = 1; + break; + } + } + if (offset_aligned == 0) { + printf("%s%d: partition (%s) start offset alignment incorrect\n", + MTD_DEV_TYPE(id->type), id->num, part->name); + return 1; + } + + end_offset = part->offset + part->size; + for (i = 0; i < flash->sector_count; i++) { + if ((flash->start[i] - flash->start[0]) == end_offset) + return 0; + } + + if (flash->size == end_offset) + return 0; + + printf("%s%d: partition (%s) size alignment incorrect\n", + MTD_DEV_TYPE(id->type), id->num, part->name); +#endif + return 1; +} + +/** + * Performs sanity check for supplied NAND flash partition. Table of existing + * NAND flash devices is searched and partition device is located. Alignment + * with the granularity of nand erasesize is verified. + * + * @param id of the parent device + * @param part partition to validate + * @return 0 if partition is valid, 1 otherwise + */ +static int part_validate_nand(struct mtdids *id, struct part_info *part) +{ +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) + /* info for NAND chips */ + extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + struct nand_chip *nand; + + nand = &nand_dev_desc[id->num]; + + if ((unsigned long)(part->offset) % nand->erasesize) { + printf("%s%d: partition (%s) start offset alignment incorrect\n", + MTD_DEV_TYPE(id->type), id->num, part->name); + return 1; + } + + if (part->size % nand->erasesize) { + printf("%s%d: partition (%s) size alignment incorrect\n", + MTD_DEV_TYPE(id->type), id->num, part->name); + return 1; + } + + return 0; +#else + return 1; +#endif +} + +/** + * Performs sanity check for supplied partition. Offset and size are verified + * to be within valid range. Partition type is checked and either + * parts_validate_nor() or parts_validate_nand() is called with the argument + * of part. + * + * @param id of the parent device + * @param part partition to validate + * @return 0 if partition is valid, 1 otherwise + */ +static int part_validate(struct mtdids *id, struct part_info *part) +{ + if (part->size == SIZE_REMAINING) + part->size = id->size - part->offset; + + if (part->offset > id->size) { + printf("%s: offset %08lx beyond flash size %08lx\n", + id->mtd_id, part->offset, id->size); + return 1; + } + + if ((part->offset + part->size) <= part->offset) { + printf("%s%d: partition (%s) size too big\n", + MTD_DEV_TYPE(id->type), id->num, part->name); + return 1; + } + + if (part->offset + part->size > id->size) { + printf("%s: partitioning exceeds flash size\n", id->mtd_id); + return 1; + } + + if (id->type == MTD_DEV_TYPE_NAND) + return part_validate_nand(id, part); + else if (id->type == MTD_DEV_TYPE_NOR) + return part_validate_nor(id, part); + else + DEBUGF("part_validate: invalid dev type\n"); + + return 1; +} + +/** + * Delete selected partition from the partion list of the specified device. + * + * @param dev device to delete partition from + * @param part partition to delete + * @return 0 on success, 1 otherwise + */ +static int part_del(struct mtd_device *dev, struct part_info *part) +{ + u8 current_save_needed = 0; + + /* if there is only one partition, remove whole device */ + if (dev->num_parts == 1) + return device_del(dev); + + /* otherwise just delete this partition */ + + if (dev == current_dev) { + /* we are modyfing partitions for the current device, + * update current */ + struct part_info *curr_pi; + curr_pi = jffs2_part_info(current_dev, current_partnum); + + if (curr_pi) { + if (curr_pi == part) { + printf("current partition deleted, resetting current to 0\n"); + current_partnum = 0; + } else if (part->offset <= curr_pi->offset) { + current_partnum--; + } + current_save_needed = 1; + } + } + + jffs2_free_cache(part); + list_del(&part->link); + free(part); + dev->num_parts--; + + if (current_save_needed > 0) + current_save(); + else + index_partitions(); + + return 0; +} + +/** + * Delete all partitions from parts head list, free memory. + * + * @param head list of partitions to delete + */ +static void part_delall(struct list_head *head) +{ + struct list_head *entry, *n; + struct part_info *part_tmp; + + /* clean tmp_list and free allocated memory */ + list_for_each_safe(entry, n, head) { + part_tmp = list_entry(entry, struct part_info, link); + + jffs2_free_cache(part_tmp); + list_del(entry); + free(part_tmp); + } +} + +/** + * Add new partition to the supplied partition list. Make sure partitions are + * sorted by offset in ascending order. + * + * @param head list this partition is to be added to + * @param new partition to be added + */ +static int part_sort_add(struct mtd_device *dev, struct part_info *part) +{ + struct list_head *entry; + struct part_info *new_pi, *curr_pi; + + /* link partition to parrent dev */ + part->dev = dev; + + if (list_empty(&dev->parts)) { + DEBUGF("part_sort_add: list empty\n"); + list_add(&part->link, &dev->parts); + dev->num_parts++; + index_partitions(); + return 0; + } + + new_pi = list_entry(&part->link, struct part_info, link); + + /* get current partition info if we are updating current device */ + curr_pi = NULL; + if (dev == current_dev) + curr_pi = jffs2_part_info(current_dev, current_partnum); + + list_for_each(entry, &dev->parts) { + struct part_info *pi; + + pi = list_entry(entry, struct part_info, link); + + /* be compliant with kernel cmdline, allow only one partition at offset zero */ + if ((new_pi->offset == pi->offset) && (pi->offset == 0)) { + printf("cannot add second partition at offset 0\n"); + return 1; + } + + if (new_pi->offset <= pi->offset) { + list_add_tail(&part->link, entry); + dev->num_parts++; + + if (curr_pi && (pi->offset <= curr_pi->offset)) { + /* we are modyfing partitions for the current + * device, update current */ + current_partnum++; + current_save(); + } else { + index_partitions(); + } + return 0; + } + } + + list_add_tail(&part->link, &dev->parts); + dev->num_parts++; + index_partitions(); + return 0; +} + +/** + * Add provided partition to the partition list of a given device. + * + * @param dev device to which partition is added + * @param part partition to be added + * @return 0 on success, 1 otherwise + */ +static int part_add(struct mtd_device *dev, struct part_info *part) +{ + /* verify alignment and size */ + if (part_validate(dev->id, part) != 0) + return 1; + + /* partition is ok, add it to the list */ + if (part_sort_add(dev, part) != 0) + return 1; + + return 0; +} + +/** + * Parse one partition definition, allocate memory and return pointer to this + * location in retpart. + * + * @param partdef pointer to the partition definition string i.e. + * @param ret output pointer to next char after parse completes (output) + * @param retpart pointer to the allocated partition (output) + * @return 0 on success, 1 otherwise + */ +static int part_parse(const char *const partdef, const char **ret, struct part_info **retpart) +{ + struct part_info *part; + unsigned long size; + unsigned long offset; + const char *name; + int name_len; + unsigned int mask_flags; + const char *p; + + p = partdef; + *retpart = NULL; + *ret = NULL; + + /* fetch the partition size */ + if (*p == '-') { + /* assign all remaining space to this partition */ + DEBUGF("'-': remaining size assigned\n"); + size = SIZE_REMAINING; + p++; + } else { + size = memsize_parse(p, &p); + if (size < MIN_PART_SIZE) { + printf("partition size too small (%lx)\n", size); + return 1; + } + } + + /* check for offset */ + offset = OFFSET_NOT_SPECIFIED; + if (*p == '@') { + p++; + offset = memsize_parse(p, &p); + } + + /* now look for the name */ + if (*p == '(') { + name = ++p; + if ((p = strchr(name, ')')) == NULL) { + printf("no closing ) found in partition name\n"); + return 1; + } + name_len = p - name + 1; + if ((name_len - 1) == 0) { + printf("empty partition name\n"); + return 1; + } + p++; + } else { + /* 0x00000000@0x00000000 */ + name_len = 22; + name = NULL; + } + + /* test for options */ + mask_flags = 0; + if (strncmp(p, "ro", 2) == 0) { + mask_flags |= MTD_WRITEABLE; + p += 2; + } + + /* check for next partition definition */ + if (*p == ',') { + if (size == SIZE_REMAINING) { + *ret = NULL; + printf("no partitions allowed after a fill-up partition\n"); + return 1; + } + *ret = ++p; + } else if ((*p == ';') || (*p == '\0')) { + *ret = p; + } else { + printf("unexpected character '%c' at the end of partition\n", *p); + *ret = NULL; + return 1; + } + + /* allocate memory */ + part = (struct part_info *)malloc(sizeof(struct part_info) + name_len); + if (!part) { + printf("out of memory\n"); + return 1; + } + memset(part, 0, sizeof(struct part_info) + name_len); + part->size = size; + part->offset = offset; + part->mask_flags = mask_flags; + part->name = (char *)(part + 1); + + if (name) { + /* copy user provided name */ + strncpy(part->name, name, name_len - 1); + part->auto_name = 0; + } else { + /* auto generated name in form of size@offset */ + sprintf(part->name, "0x%08lx@0x%08lx", size, offset); + part->auto_name = 1; + } + + part->name[name_len - 1] = '\0'; + INIT_LIST_HEAD(&part->link); + + DEBUGF("+ partition: name %-22s size 0x%08x offset 0x%08x mask flags %d\n", + part->name, part->size, + part->offset, part->mask_flags); + + *retpart = part; + return 0; +} +#endif/* #ifdef CONFIG_JFFS2_CMDLINE */ + +/** + * Check device number to be within valid range for given device type. + * + * @param dev device to validate + * @return 0 if device is valid, 1 otherwise + */ +static int device_validate(u8 type, u8 num, u32 *size) +{ + if (type == MTD_DEV_TYPE_NOR) { +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + if (num < CFG_MAX_FLASH_BANKS) { + extern flash_info_t flash_info[]; + *size = flash_info[num].size; + return 0; + } + + printf("no such FLASH device: %s%d (valid range 0 ... %d\n", + MTD_DEV_TYPE(type), num, CFG_MAX_FLASH_BANKS - 1); +#else + printf("support for FLASH devices not present\n"); +#endif + } else if (type == MTD_DEV_TYPE_NAND) { +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) + if (num < CFG_MAX_NAND_DEVICE) { + extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + *size = nand_dev_desc[num].totlen; + return 0; + } + + printf("no such NAND device: %s%d (valid range 0 ... %d)\n", + MTD_DEV_TYPE(type), num, CFG_MAX_NAND_DEVICE - 1); +#else + printf("support for NAND devices not present\n"); +#endif + } + + return 1; +} + +#ifdef CONFIG_JFFS2_CMDLINE +/** + * Delete all mtd devices from a supplied devices list, free memory allocated for + * each device and delete all device partitions. + * + * @return 0 on success, 1 otherwise + */ +static int device_delall(struct list_head *head) +{ + struct list_head *entry, *n; + struct mtd_device *dev_tmp; + + /* clean devices list */ + list_for_each_safe(entry, n, head) { + dev_tmp = list_entry(entry, struct mtd_device, link); + list_del(entry); + part_delall(&dev_tmp->parts); + free(dev_tmp); + } + INIT_LIST_HEAD(&devices); + + return 0; +} + +/** + * If provided device exists it's partitions are deleted, device is removed + * from device list and device memory is freed. + * + * @param dev device to be deleted + * @return 0 on success, 1 otherwise + */ +static int device_del(struct mtd_device *dev) +{ + part_delall(&dev->parts); + list_del(&dev->link); + free(dev); + + if (dev == current_dev) { + /* we just deleted current device */ + if (list_empty(&devices)) { + current_dev = NULL; + } else { + /* reset first partition from first dev from the + * devices list as current */ + current_dev = list_entry(devices.next, struct mtd_device, link); + current_partnum = 0; + } + current_save(); + return 0; + } + + index_partitions(); + return 0; +} + +/** + * Search global device list and return pointer to the device of type and num + * specified. + * + * @param type device type + * @param num device number + * @return NULL if requested device does not exist + */ +static struct mtd_device* device_find(u8 type, u8 num) +{ + struct list_head *entry; + struct mtd_device *dev_tmp; + + list_for_each(entry, &devices) { + dev_tmp = list_entry(entry, struct mtd_device, link); + + if ((dev_tmp->id->type == type) && (dev_tmp->id->num == num)) + return dev_tmp; + } + + return NULL; +} + +/** + * Add specified device to the global device list. + * + * @param dev device to be added + */ +static void device_add(struct mtd_device *dev) +{ + u8 current_save_needed = 0; + + if (list_empty(&devices)) { + current_dev = dev; + current_partnum = 0; + current_save_needed = 1; + } + + list_add_tail(&dev->link, &devices); + + if (current_save_needed > 0) + current_save(); + else + index_partitions(); +} + +/** + * Parse device type, name and mtd-id. If syntax is ok allocate memory and + * return pointer to the device structure. + * + * @param mtd_dev pointer to the device definition string i.e. + * @param ret output pointer to next char after parse completes (output) + * @param retdev pointer to the allocated device (output) + * @return 0 on success, 1 otherwise + */ +static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_device **retdev) +{ + struct mtd_device *dev; + struct part_info *part; + struct mtdids *id; + const char *mtd_id; + unsigned int mtd_id_len; + const char *p, *pend; + LIST_HEAD(tmp_list); + struct list_head *entry, *n; + u16 num_parts; + u32 offset; + int err = 1; + + p = mtd_dev; + *retdev = NULL; + *ret = NULL; + + DEBUGF("===device_parse===\n"); + + /* fetch */ + mtd_id = p; + if (!(p = strchr(mtd_id, ':'))) { + printf("no identifier\n"); + return 1; + } + mtd_id_len = p - mtd_id + 1; + p++; + + /* verify if we have a valid device specified */ + if ((id = id_find_by_mtd_id(mtd_id, mtd_id_len - 1)) == NULL) { + printf("invalid mtd device '%.*s'\n", mtd_id_len - 1, mtd_id); + return 1; + } + + DEBUGF("dev type = %d (%s), dev num = %d, mtd-id = %s\n", + id->type, MTD_DEV_TYPE(id->type), + id->num, id->mtd_id); + pend = strchr(p, ';'); + DEBUGF("parsing partitions %.*s\n", (pend ? pend - p : strlen(p)), p); + + + /* parse partitions */ + num_parts = 0; + + offset = 0; + if ((dev = device_find(id->type, id->num)) != NULL) { + /* if device already exists start at the end of the last partition */ + part = list_entry(dev->parts.prev, struct part_info, link); + offset = part->offset + part->size; + } + + while (p && (*p != '\0') && (*p != ';')) { + err = 1; + if ((part_parse(p, &p, &part) != 0) || (!part)) + break; + + /* calculate offset when not specified */ + if (part->offset == OFFSET_NOT_SPECIFIED) + part->offset = offset; + else + offset = part->offset; + + /* verify alignment and size */ + if (part_validate(id, part) != 0) + break; + + offset += part->size; + + /* partition is ok, add it to the list */ + list_add_tail(&part->link, &tmp_list); + num_parts++; + err = 0; + } + if (err == 1) { + part_delall(&tmp_list); + return 1; + } + + if (num_parts == 0) { + printf("no partitions for device %s%d (%s)\n", + MTD_DEV_TYPE(id->type), id->num, id->mtd_id); + return 1; + } + + DEBUGF("\ntotal partitions: %d\n", num_parts); + + /* check for next device presence */ + if (p) { + if (*p == ';') { + *ret = ++p; + } else if (*p == '\0') { + *ret = p; + } else { + printf("unexpected character '%c' at the end of device\n", *p); + *ret = NULL; + return 1; + } + } + + /* allocate memory for mtd_device structure */ + if ((dev = (struct mtd_device *)malloc(sizeof(struct mtd_device))) == NULL) { + printf("out of memory\n"); + return 1; + } + memset(dev, 0, sizeof(struct mtd_device)); + dev->id = id; + dev->num_parts = 0; /* part_sort_add increments num_parts */ + INIT_LIST_HEAD(&dev->parts); + INIT_LIST_HEAD(&dev->link); + + /* move partitions from tmp_list to dev->parts */ + list_for_each_safe(entry, n, &tmp_list) { + part = list_entry(entry, struct part_info, link); + list_del(entry); + if (part_sort_add(dev, part) != 0) { + device_del(dev); + return 1; + } + } + + *retdev = dev; + + DEBUGF("===\n\n"); + return 0; +} + +/** + * Initialize global device list. + * + * @return 0 on success, 1 otherwise + */ +static int devices_init(void) +{ + last_parts[0] = '\0'; + current_dev = NULL; + current_save(); + + return device_delall(&devices); +} + +/* + * Search global mtdids list and find id of requested type and number. + * + * @return pointer to the id if it exists, NULL otherwise + */ +static struct mtdids* id_find(u8 type, u8 num) +{ + struct list_head *entry; + struct mtdids *id; + + list_for_each(entry, &mtdids) { + id = list_entry(entry, struct mtdids, link); + + if ((id->type == type) && (id->num == num)) + return id; + } + + return NULL; +} + +/** + * Search global mtdids list and find id of a requested mtd_id. + * + * Note: first argument is not null terminated. + * + * @param mtd_id string containing requested mtd_id + * @param mtd_id_len length of supplied mtd_id + * @return pointer to the id if it exists, NULL otherwise + */ +static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len) +{ + struct list_head *entry; + struct mtdids *id; + + DEBUGF("--- id_find_by_mtd_id: '%.*s' (len = %d)\n", + mtd_id_len, mtd_id, mtd_id_len); + + list_for_each(entry, &mtdids) { + id = list_entry(entry, struct mtdids, link); + + DEBUGF("entry: '%s' (len = %d)\n", + id->mtd_id, strlen(id->mtd_id)); + + if (mtd_id_len != strlen(id->mtd_id)) + continue; + if (strncmp(id->mtd_id, mtd_id, mtd_id_len) == 0) + return id; + } + + return NULL; +} +#endif /* #ifdef CONFIG_JFFS2_CMDLINE */ + +/** + * Parse device id string := 'nand'|'nor', return device + * type and number. + * + * @param id string describing device id + * @param ret_id output pointer to next char after parse completes (output) + * @param dev_type parsed device type (output) + * @param dev_num parsed device number (output) + * @return 0 on success, 1 otherwise + */ +int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num) +{ + const char *p = id; + + *dev_type = 0; + if (strncmp(p, "nand", 4) == 0) { + *dev_type = MTD_DEV_TYPE_NAND; + p += 4; + } else if (strncmp(p, "nor", 3) == 0) { + *dev_type = MTD_DEV_TYPE_NOR; + p += 3; + } else { + printf("incorrect device type in %s\n", id); + return 1; + } + + if (!isdigit(*p)) { + printf("incorrect device number in %s\n", id); + return 1; + } + + *dev_num = simple_strtoul(p, (char **)&p, 0); + if (ret_id) + *ret_id = p; + return 0; +} + +#ifdef CONFIG_JFFS2_CMDLINE +/** + * Process all devices and generate corresponding mtdparts string describing + * all partitions on all devices. + * + * @param buf output buffer holding generated mtdparts string (output) + * @param buflen buffer size + * @return 0 on success, 1 otherwise + */ +static int generate_mtdparts(char *buf, u32 buflen) +{ + struct list_head *pentry, *dentry; + struct mtd_device *dev; + struct part_info *part, *prev_part; + char *p = buf; + char tmpbuf[32]; + u32 size, offset, len, part_cnt; + u32 maxlen = buflen - 1; + + DEBUGF("--- generate_mtdparts ---\n"); + + if (list_empty(&devices)) { + buf[0] = '\0'; + return 0; + } + + sprintf(p, "mtdparts="); + p += 9; + + list_for_each(dentry, &devices) { + dev = list_entry(dentry, struct mtd_device, link); + + /* copy mtd_id */ + len = strlen(dev->id->mtd_id) + 1; + if (len > maxlen) + goto cleanup; + memcpy(p, dev->id->mtd_id, len - 1); + p += len - 1; + *(p++) = ':'; + maxlen -= len; + + /* format partitions */ + prev_part = NULL; + part_cnt = 0; + list_for_each(pentry, &dev->parts) { + part = list_entry(pentry, struct part_info, link); + size = part->size; + offset = part->offset; + part_cnt++; + + /* partition size */ + memsize_format(tmpbuf, size); + len = strlen(tmpbuf); + if (len > maxlen) + goto cleanup; + memcpy(p, tmpbuf, len); + p += len; + maxlen -= len; + + + /* add offset only when there is a gap between + * partitions */ + if ((!prev_part && (offset != 0)) || + (prev_part && ((prev_part->offset + prev_part->size) != part->offset))) { + + memsize_format(tmpbuf, offset); + len = strlen(tmpbuf) + 1; + if (len > maxlen) + goto cleanup; + *(p++) = '@'; + memcpy(p, tmpbuf, len - 1); + p += len - 1; + maxlen -= len; + } + + /* copy name only if user supplied */ + if(!part->auto_name) { + len = strlen(part->name) + 2; + if (len > maxlen) + goto cleanup; + + *(p++) = '('; + memcpy(p, part->name, len - 2); + p += len - 2; + *(p++) = ')'; + maxlen -= len; + } + + /* ro mask flag */ + if (part->mask_flags && MTD_WRITEABLE) { + len = 2; + if (len > maxlen) + goto cleanup; + *(p++) = 'r'; + *(p++) = 'o'; + maxlen -= 2; + } + + /* print ',' separator if there are other partitions + * following */ + if (dev->num_parts > part_cnt) { + if (1 > maxlen) + goto cleanup; + *(p++) = ','; + maxlen--; + } + prev_part = part; + } + /* print ';' separator if there are other devices following */ + if (dentry->next != &devices) { + if (1 > maxlen) + goto cleanup; + *(p++) = ';'; + maxlen--; + } + } + + /* we still have at least one char left, as we decremented maxlen at + * the begining */ + *p = '\0'; + + return 0; + +cleanup: + last_parts[0] = '\0'; + return 1; +} + +/** + * Call generate_mtdparts to process all devices and generate corresponding + * mtdparts string, save it in mtdparts environment variable. + * + * @param buf output buffer holding generated mtdparts string (output) + * @param buflen buffer size + * @return 0 on success, 1 otherwise + */ +static int generate_mtdparts_save(char *buf, u32 buflen) +{ + int ret; + + ret = generate_mtdparts(buf, buflen); + + if ((buf[0] != '\0') && (ret == 0)) + setenv("mtdparts", buf); + else + setenv("mtdparts", NULL); + + return ret; +} + +/** + * Format and print out a partition list for each device from global device + * list. + */ +static void list_partitions(void) +{ + struct list_head *dentry, *pentry; + struct part_info *part; + struct mtd_device *dev; + int part_num; + + DEBUGF("\n---list_partitions---\n"); + list_for_each(dentry, &devices) { + dev = list_entry(dentry, struct mtd_device, link); + printf("\ndevice %s%d <%s>, # parts = %d\n", + MTD_DEV_TYPE(dev->id->type), dev->id->num, + dev->id->mtd_id, dev->num_parts); + printf(" #: name\t\t\tsize\t\toffset\t\tmask_flags\n"); + + /* list partitions for given device */ + part_num = 0; + list_for_each(pentry, &dev->parts) { + part = list_entry(pentry, struct part_info, link); + printf(" %d: %-22s\t0x%08x\t0x%08x\t%d\n", + part_num, part->name, part->size, + part->offset, part->mask_flags); + + part_num++; + } + } + if (list_empty(&devices)) + printf("no partitions defined\n"); + + /* current_dev is not NULL only when we have non empty device list */ + if (current_dev) { + part = jffs2_part_info(current_dev, current_partnum); + if (part) { + printf("\nactive partition: %s%d,%d - (%s) 0x%08lx @ 0x%08lx\n", + MTD_DEV_TYPE(current_dev->id->type), + current_dev->id->num, current_partnum, + part->name, part->size, part->offset); + } else { + printf("could not get current partition info\n\n"); + } + } + + printf("\ndefaults:\n"); + printf("mtdids : %s\n", mtdids_default); + printf("mtdparts: %s\n", mtdparts_default); +} + +/** + * Given partition identifier in form of , find + * corresponding device and verify partition number. + * + * @param id string describing device and partition + * @param dev pointer to the requested device (output) + * @param part_num verified partition number (output) + * @param part pointer to requested partition (output) + * @return 0 on success, 1 otherwise + */ +int find_dev_and_part(const char *id, struct mtd_device **dev, + u8 *part_num, struct part_info **part) +{ + u8 type, dnum, pnum; + const char *p; + + DEBUGF("--- find_dev_and_part ---\nid = %s\n", id); + + p = id; + *dev = NULL; + *part = NULL; + *part_num = 0; + + if (id_parse(p, &p, &type, &dnum) != 0) + return 1; + + if ((*p++ != ',') || (*p == '\0')) { + printf("no partition number specified\n"); + return 1; + } + pnum = simple_strtoul(p, (char **)&p, 0); + if (*p != '\0') { + printf("unexpected trailing character '%c'\n", *p); + return 1; + } + + if ((*dev = device_find(type, dnum)) == NULL) { + printf("no such device %s%d\n", MTD_DEV_TYPE(type), dnum); + return 1; + } + + if ((*part = jffs2_part_info(*dev, pnum)) == NULL) { + printf("no such partition\n"); + *dev = NULL; + return 1; + } + + *part_num = pnum; + + return 0; +} + +/** + * Find and delete partition. For partition id format see find_dev_and_part(). + * + * @param id string describing device and partition + * @return 0 on success, 1 otherwise + */ +static int delete_partition(const char *id) +{ + u8 pnum; + struct mtd_device *dev; + struct part_info *part; + + if (find_dev_and_part(id, &dev, &pnum, &part) == 0) { + + DEBUGF("delete_partition: device = %s%d, partition %d = (%s) 0x%08lx@0x%08lx\n", + MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum, + part->name, part->size, part->offset); + + if (part_del(dev, part) != 0) + return 1; + + if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) { + printf("generated mtdparts too long, reseting to null\n"); + return 1; + } + return 0; + } + + printf("partition %s not found\n", id); + return 1; +} + +/** + * Accept character string describing mtd partitions and call device_parse() + * for each entry. Add created devices to the global devices list. + * + * @param mtdparts string specifing mtd partitions + * @return 0 on success, 1 otherwise + */ +static int parse_mtdparts(const char *const mtdparts) +{ + const char *p = mtdparts; + struct mtd_device *dev; + int err = 1; + + DEBUGF("\n---parse_mtdparts---\nmtdparts = %s\n\n", p); + + /* delete all devices and partitions */ + if (devices_init() != 0) { + printf("could not initialise device list\n"); + return err; + } + + /* re-read 'mtdparts' variable, devices_init may be updating env */ + p = getenv("mtdparts"); + + if (strncmp(p, "mtdparts=", 9) != 0) { + printf("mtdparts variable doesn't start with 'mtdparts='\n"); + return err; + } + p += 9; + + while (p && (*p != '\0')) { + err = 1; + if ((device_parse(p, &p, &dev) != 0) || (!dev)) + break; + + DEBUGF("+ device: %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type), + dev->id->num, dev->id->mtd_id); + + /* check if parsed device is already on the list */ + if (device_find(dev->id->type, dev->id->num) != NULL) { + printf("device %s%d redefined, please correct mtdparts variable\n", + MTD_DEV_TYPE(dev->id->type), dev->id->num); + break; + } + + list_add_tail(&dev->link, &devices); + err = 0; + } + if (err == 1) { + device_delall(&devices); + return 1; + } + + return 0; +} + +/** + * Parse provided string describing mtdids mapping (see file header for mtdids + * variable format). Allocate memory for each entry and add all found entries + * to the global mtdids list. + * + * @param ids mapping string + * @return 0 on success, 1 otherwise + */ +static int parse_mtdids(const char *const ids) +{ + const char *p = ids; + const char *mtd_id; + int mtd_id_len; + struct mtdids *id; + struct list_head *entry, *n; + struct mtdids *id_tmp; + u8 type, num; + u32 size; + int ret = 1; + + DEBUGF("\n---parse_mtdids---\nmtdids = %s\n\n", ids); + + /* clean global mtdids list */ + list_for_each_safe(entry, n, &mtdids) { + id_tmp = list_entry(entry, struct mtdids, link); + DEBUGF("mtdids del: %d %d\n", id_tmp->type, id_tmp->num); + list_del(entry); + free(id_tmp); + } + last_ids[0] = '\0'; + INIT_LIST_HEAD(&mtdids); + + while(p && (*p != '\0')) { + + ret = 1; + /* parse 'nor'|'nand' */ + if (id_parse(p, &p, &type, &num) != 0) + break; + + if (*p != '=') { + printf("mtdids: incorrect \n"); + break; + } + p++; + + /* check if requested device exists */ + if (device_validate(type, num, &size) != 0) + return 1; + + /* locate */ + mtd_id = p; + if ((p = strchr(mtd_id, ',')) != NULL) { + mtd_id_len = p - mtd_id + 1; + p++; + } else { + mtd_id_len = strlen(mtd_id) + 1; + } + if (mtd_id_len == 0) { + printf("mtdids: no identifier\n"); + break; + } + + /* check if this id is already on the list */ + int double_entry = 0; + list_for_each(entry, &mtdids) { + id_tmp = list_entry(entry, struct mtdids, link); + if ((id_tmp->type == type) && (id_tmp->num == num)) { + double_entry = 1; + break; + } + } + if (double_entry) { + printf("device id %s%d redefined, please correct mtdids variable\n", + MTD_DEV_TYPE(type), num); + break; + } + + /* allocate mtdids structure */ + if (!(id = (struct mtdids *)malloc(sizeof(struct mtdids) + mtd_id_len))) { + printf("out of memory\n"); + break; + } + memset(id, 0, sizeof(struct mtdids) + mtd_id_len); + id->num = num; + id->type = type; + id->size = size; + id->mtd_id = (char *)(id + 1); + strncpy(id->mtd_id, mtd_id, mtd_id_len - 1); + id->mtd_id[mtd_id_len - 1] = '\0'; + INIT_LIST_HEAD(&id->link); + + DEBUGF("+ id %s%d\t%16d bytes\t%s\n", + MTD_DEV_TYPE(id->type), id->num, + id->size, id->mtd_id); + + list_add_tail(&id->link, &mtdids); + ret = 0; + } + if (ret == 1) { + /* clean mtdids list and free allocated memory */ + list_for_each_safe(entry, n, &mtdids) { + id_tmp = list_entry(entry, struct mtdids, link); + list_del(entry); + free(id_tmp); + } + return 1; + } + + return 0; +} + +/** + * Parse and initialize global mtdids mapping and create global + * device/partition list. + * + * @return 0 on success, 1 otherwise + */ +int mtdparts_init(void) +{ + static int initialized = 0; + const char *ids, *parts; + const char *current_partition; + int ids_changed; + char tmp_ep[PARTITION_MAXLEN]; + + DEBUGF("\n---mtdparts_init---\n"); + if (!initialized) { + INIT_LIST_HEAD(&mtdids); + INIT_LIST_HEAD(&devices); + memset(last_ids, 0, MTDIDS_MAXLEN); + memset(last_parts, 0, MTDPARTS_MAXLEN); + memset(last_partition, 0, PARTITION_MAXLEN); + initialized = 1; + } + + /* get variables */ + ids = getenv("mtdids"); + parts = getenv("mtdparts"); + current_partition = getenv("partition"); + + /* save it for later parsing, cannot rely on current partition pointer + * as 'partition' variable may be updated during init */ + tmp_ep[0] = '\0'; + if (current_partition) + strncpy(tmp_ep, current_partition, PARTITION_MAXLEN); + + DEBUGF("last_ids : %s\n", last_ids); + DEBUGF("env_ids : %s\n", ids); + DEBUGF("last_parts: %s\n", last_parts); + DEBUGF("env_parts : %s\n\n", parts); + + DEBUGF("last_partition : %s\n", last_partition); + DEBUGF("env_partition : %s\n", current_partition); + + /* if mtdids varible is empty try to use defaults */ + if (!ids) { + if (mtdids_default) { + DEBUGF("mtdids variable not defined, using default\n"); + ids = mtdids_default; + setenv("mtdids", (char *)ids); + } else { + printf("mtdids not defined, no default present\n"); + return 1; + } + } + if (strlen(ids) > MTDIDS_MAXLEN - 1) { + printf("mtdids too long (> %d)\n", MTDIDS_MAXLEN); + return 1; + } + + /* do no try to use defaults when mtdparts variable is not defined, + * just check the length */ + if (!parts) + printf("mtdparts variable not set, see 'help mtdparts'\n"); + + if (parts && (strlen(parts) > MTDPARTS_MAXLEN - 1)) { + printf("mtdparts too long (> %d)\n", MTDPARTS_MAXLEN); + return 1; + } + + /* check if we have already parsed those mtdids */ + if ((last_ids[0] != '\0') && (strcmp(last_ids, ids) == 0)) { + ids_changed = 0; + } else { + ids_changed = 1; + + if (parse_mtdids(ids) != 0) { + devices_init(); + return 1; + } + + /* ok it's good, save new ids */ + strncpy(last_ids, ids, MTDIDS_MAXLEN); + } + + /* parse partitions if either mtdparts or mtdids were updated */ + if (parts && ((last_parts[0] == '\0') || ((strcmp(last_parts, parts) != 0)) || ids_changed)) { + if (parse_mtdparts(parts) != 0) + return 1; + + if (list_empty(&devices)) { + printf("mtdparts_init: no valid partitions\n"); + return 1; + } + + /* ok it's good, save new parts */ + strncpy(last_parts, parts, MTDPARTS_MAXLEN); + + /* reset first partition from first dev from the list as current */ + current_dev = list_entry(devices.next, struct mtd_device, link); + current_partnum = 0; + current_save(); + + DEBUGF("mtdparts_init: current_dev = %s%d, current_partnum = %d\n", + MTD_DEV_TYPE(current_dev->id->type), + current_dev->id->num, current_partnum); + } + + /* mtdparts variable was reset to NULL, delete all devices/partitions */ + if (!parts && (last_parts[0] != '\0')) + return devices_init(); + + /* do not process current partition if mtdparts variable is null */ + if (!parts) + return 0; + + /* is current partition set in environment? if so, use it */ + if ((tmp_ep[0] != '\0') && (strcmp(tmp_ep, last_partition) != 0)) { + struct part_info *p; + struct mtd_device *cdev; + u8 pnum; + + DEBUGF("--- getting current partition: %s\n", tmp_ep); + + if (find_dev_and_part(tmp_ep, &cdev, &pnum, &p) == 0) { + current_dev = cdev; + current_partnum = pnum; + current_save(); + } + } else if (getenv("partition") == NULL) { + DEBUGF("no partition variable set, setting...\n"); + current_save(); + } + + return 0; +} +#else /* #ifdef CONFIG_JFFS2_CMDLINE */ +/* + * 'Static' version of command line mtdparts_init() routine. Single partition on + * a single device configuration. + */ + +/** + * Parse and initialize global mtdids mapping and create global + * device/partition list. + * + * @return 0 on success, 1 otherwise + */ +int mtdparts_init(void) +{ + static int initialized = 0; + u32 size; + char *dev_name; + + DEBUGF("\n---mtdparts_init---\n"); + if (!initialized) { + struct mtdids *id; + struct part_info *part; + + initialized = 1; + current_dev = (struct mtd_device *) + malloc(sizeof(struct mtd_device) + + sizeof(struct part_info) + + sizeof(struct mtdids)); + if (!current_dev) { + printf("out of memory\n"); + return 1; + } + memset(current_dev, 0, sizeof(struct mtd_device) + + sizeof(struct part_info) + sizeof(struct mtdids)); + + id = (struct mtdids *)(current_dev + 1); + part = (struct part_info *)(id + 1); + + /* id */ + id->mtd_id = "single part"; + +#if defined(CONFIG_JFFS2_DEV) + dev_name = CONFIG_JFFS2_DEV; +#else + dev_name = "nor0"; +#endif + + if ((id_parse(dev_name, NULL, &id->type, &id->num) != 0) || + (device_validate(id->type, id->num, &size) != 0)) { + printf("incorrect device: %s%d\n", MTD_DEV_TYPE(id->type), id->num); + free(current_dev); + return 1; + } + id->size = size; + INIT_LIST_HEAD(&id->link); + + DEBUGF("dev id: type = %d, num = %d, size = 0x%08lx, mtd_id = %s\n", + id->type, id->num, id->size, id->mtd_id); + + /* partition */ + part->name = "static"; + part->auto_name = 0; + +#if defined(CONFIG_JFFS2_PART_SIZE) + part->size = CONFIG_JFFS2_PART_SIZE; +#else + part->size = SIZE_REMAINING; +#endif + +#if defined(CONFIG_JFFS2_PART_OFFSET) + part->offset = CONFIG_JFFS2_PART_OFFSET; +#else + part->offset = 0x00000000; +#endif + + part->dev = current_dev; + INIT_LIST_HEAD(&part->link); + + /* recalculate size if needed */ + if (part->size == SIZE_REMAINING) + part->size = id->size - part->offset; + + DEBUGF("part : name = %s, size = 0x%08lx, offset = 0x%08lx\n", + part->name, part->size, part->offset); + + /* device */ + current_dev->id = id; + INIT_LIST_HEAD(¤t_dev->link); + current_dev->num_parts = 1; + INIT_LIST_HEAD(¤t_dev->parts); + list_add(&part->link, ¤t_dev->parts); + } + + return 0; +} +#endif /* #ifdef CONFIG_JFFS2_CMDLINE */ + +/** + * Return pointer to the partition of a requested number from a requested + * device. + * + * @param dev device that is to be searched for a partition + * @param part_num requested partition number + * @return pointer to the part_info, NULL otherwise + */ +static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num) +{ + struct list_head *entry; + struct part_info *part; + int num; + + if (!dev) + return NULL; + + DEBUGF("\n--- jffs2_part_info: partition number %d for device %s%d (%s)\n", + part_num, MTD_DEV_TYPE(dev->id->type), + dev->id->num, dev->id->mtd_id); + + if (part_num >= dev->num_parts) { + printf("invalid partition number %d for device %s%d (%s)\n", + part_num, MTD_DEV_TYPE(dev->id->type), + dev->id->num, dev->id->mtd_id); + return NULL; + } + + /* locate partition number, return it */ + num = 0; + list_for_each(entry, &dev->parts) { + part = list_entry(entry, struct part_info, link); + + if (part_num == num++) { + return part; + } + } + + return NULL; +} + +/***************************************************/ +/* U-boot commands */ +/***************************************************/ + +/** + * Routine implementing fsload u-boot command. This routine tries to load + * a requested file from jffs2/cramfs filesystem on a current partition. + * + * @param cmdtp command internal data + * @param flag command flag + * @param argc number of arguments supplied to the command + * @param argv arguments list + * @return 0 on success, 1 otherwise + */ +int do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *fsname; + char *filename; + int size; + struct part_info *part; + ulong offset = load_addr; + + /* pre-set Boot file name */ + if ((filename = getenv("bootfile")) == NULL) { + filename = "uImage"; + } + + if (argc == 2) { + filename = argv[1]; + } + if (argc == 3) { + offset = simple_strtoul(argv[1], NULL, 16); + load_addr = offset; + filename = argv[2]; + } + + /* make sure we are in sync with env variables */ + if (mtdparts_init() !=0) + return 1; + + if ((part = jffs2_part_info(current_dev, current_partnum))){ + + /* check partition type for cramfs */ + fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2"); + printf("### %s loading '%s' to 0x%lx\n", fsname, filename, offset); + + if (cramfs_check(part)) { + size = cramfs_load ((char *) offset, part, filename); + } else { + /* if this is not cramfs assume jffs2 */ + size = jffs2_1pass_load((char *)offset, part, filename); + } + + if (size > 0) { + char buf[10]; + printf("### %s load complete: %d bytes loaded to 0x%lx\n", + fsname, size, offset); + sprintf(buf, "%x", size); + setenv("filesize", buf); + } else { + printf("### %s LOAD ERROR<%x> for %s!\n", fsname, size, filename); + } + + return !(size > 0); + } + return 1; +} + +/** + * Routine implementing u-boot ls command which lists content of a given + * directory on a current partition. + * + * @param cmdtp command internal data + * @param flag command flag + * @param argc number of arguments supplied to the command + * @param argv arguments list + * @return 0 on success, 1 otherwise + */ +int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *filename = "/"; + int ret; + struct part_info *part; + + if (argc == 2) + filename = argv[1]; + + /* make sure we are in sync with env variables */ + if (mtdparts_init() !=0) + return 1; + + if ((part = jffs2_part_info(current_dev, current_partnum))){ + + /* check partition type for cramfs */ + if (cramfs_check(part)) { + ret = cramfs_ls (part, filename); + } else { + /* if this is not cramfs assume jffs2 */ + ret = jffs2_1pass_ls(part, filename); + } + + return ret ? 0 : 1; + } + return 1; +} + +/** + * Routine implementing u-boot fsinfo command. This routine prints out + * miscellaneous filesystem informations/statistics. + * + * @param cmdtp command internal data + * @param flag command flag + * @param argc number of arguments supplied to the command + * @param argv arguments list + * @return 0 on success, 1 otherwise + */ +int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + struct part_info *part; + char *fsname; + int ret; + + /* make sure we are in sync with env variables */ + if (mtdparts_init() !=0) + return 1; + + if ((part = jffs2_part_info(current_dev, current_partnum))){ + + /* check partition type for cramfs */ + fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2"); + printf("### filesystem type is %s\n", fsname); + + if (cramfs_check(part)) { + ret = cramfs_info (part); + } else { + /* if this is not cramfs assume jffs2 */ + ret = jffs2_1pass_info(part); + } + + return ret ? 0 : 1; + } + return 1; +} + +/* command line only */ +#ifdef CONFIG_JFFS2_CMDLINE +/** + * Routine implementing u-boot chpart command. Sets new current partition based + * on the user supplied partition id. For partition id format see find_dev_and_part(). + * + * @param cmdtp command internal data + * @param flag command flag + * @param argc number of arguments supplied to the command + * @param argv arguments list + * @return 0 on success, 1 otherwise + */ +int do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +/* command line only */ + struct mtd_device *dev; + struct part_info *part; + u8 pnum; + + if (mtdparts_init() !=0) + return 1; + + if (argc < 2) { + printf("no partition id specified\n"); + return 1; + } + + if (find_dev_and_part(argv[1], &dev, &pnum, &part) != 0) + return 1; + + current_dev = dev; + current_partnum = pnum; + current_save(); + + printf("partition changed to %s%d,%d\n", + MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum); + + return 0; +} + +/** + * Routine implementing u-boot mtdparts command. Initialize/update default global + * partition list and process user partition request (list, add, del). + * + * @param cmdtp command internal data + * @param flag command flag + * @param argc number of arguments supplied to the command + * @param argv arguments list + * @return 0 on success, 1 otherwise + */ +int do_jffs2_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc == 2) { + if (strcmp(argv[1], "default") == 0) { + setenv("mtdids", (char *)mtdids_default); + setenv("mtdparts", (char *)mtdparts_default); + setenv("partition", NULL); + + mtdparts_init(); + return 0; + } else if (strcmp(argv[1], "delall") == 0) { + /* this may be the first run, initialize lists if needed */ + mtdparts_init(); + + setenv("mtdparts", NULL); + + /* devices_init() calls current_save() */ + return devices_init(); + } + } + + /* make sure we are in sync with env variables */ + if (mtdparts_init() != 0) + return 1; + + if (argc == 1) { + list_partitions(); + return 0; + } + + /* mtdparts add [@] [ro] */ + if (((argc == 5) || (argc == 6)) && (strcmp(argv[1], "add") == 0)) { +#define PART_ADD_DESC_MAXLEN 64 + char tmpbuf[PART_ADD_DESC_MAXLEN]; + u8 type, num, len; + struct mtd_device *dev; + struct mtd_device *dev_tmp; + struct mtdids *id; + struct part_info *p; + + if (id_parse(argv[2], NULL, &type, &num) != 0) + return 1; + + if ((id = id_find(type, num)) == NULL) { + printf("no such device %s defined in mtdids variable\n", argv[2]); + return 1; + } + + len = strlen(id->mtd_id) + 1; /* 'mtd_id:' */ + len += strlen(argv[3]); /* size@offset */ + len += strlen(argv[4]) + 2; /* '(' name ')' */ + if (argv[5] && (strlen(argv[5]) == 2)) + len += 2; /* 'ro' */ + + if (len >= PART_ADD_DESC_MAXLEN) { + printf("too long partition description\n"); + return 1; + } + sprintf(tmpbuf, "%s:%s(%s)%s", + id->mtd_id, argv[3], argv[4], argv[5] ? argv[5] : ""); + DEBUGF("add tmpbuf: %s\n", tmpbuf); + + if ((device_parse(tmpbuf, NULL, &dev) != 0) || (!dev)) + return 1; + + DEBUGF("+ %s\t%d\t%s\n", MTD_DEV_TYPE(dev->id->type), + dev->id->num, dev->id->mtd_id); + + if ((dev_tmp = device_find(dev->id->type, dev->id->num)) == NULL) { + device_add(dev); + } else { + /* merge new partition with existing ones*/ + p = list_entry(dev->parts.next, struct part_info, link); + if (part_add(dev_tmp, p) != 0) { + device_del(dev); + return 1; + } + } + + if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) { + printf("generated mtdparts too long, reseting to null\n"); + return 1; + } + + return 0; + } + + /* mtdparts del part-id */ + if ((argc == 3) && (strcmp(argv[1], "del") == 0)) { + DEBUGF("del: part-id = %s\n", argv[2]); + + return delete_partition(argv[2]); + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} +#endif /* #ifdef CONFIG_JFFS2_CMDLINE */ + +/***************************************************/ +U_BOOT_CMD( + fsload, 3, 0, do_jffs2_fsload, + "fsload\t- load binary file from a filesystem image\n", + "[ off ] [ filename ]\n" + " - load binary file from flash bank\n" + " with offset 'off'\n" +); +U_BOOT_CMD( + ls, 2, 1, do_jffs2_ls, + "ls\t- list files in a directory (default /)\n", + "[ directory ]\n" + " - list files in a directory.\n" +); + +U_BOOT_CMD( + fsinfo, 1, 1, do_jffs2_fsinfo, + "fsinfo\t- print information about filesystems\n", + " - print information about filesystems\n" +); + +#ifdef CONFIG_JFFS2_CMDLINE +U_BOOT_CMD( + chpart, 2, 0, do_jffs2_chpart, + "chpart\t- change active partition\n", + "part-id\n" + " - change active partition (e.g. part-id = nand0,1)\n" +); + +U_BOOT_CMD( + mtdparts, 6, 0, do_jffs2_mtdparts, + "mtdparts- define flash/nand partitions\n", + "\n" + " - list partition table\n" + "mtdparts delall\n" + " - delete all partitions\n" + "mtdparts del part-id\n" + " - delete partition (e.g. part-id = nand0,1)\n" + "mtdparts add [@] [] [ro]\n" + " - add partition\n" + "mtdparts default\n" + " - reset partition table to defaults\n\n" + "-----\n\n" + "this command uses three environment variables:\n\n" + "'partition' - keeps current partition identifier\n\n" + "partition := \n" + " := ,part_num\n\n" + "'mtdids' - linux kernel mtd device id <-> u-boot device id mapping\n\n" + "mtdids=[,,...]\n\n" + " := =\n" + " := 'nand'|'nor'\n" + " := mtd device number, 0...\n" + " := unique device tag used by linux kernel to find mtd device (mtd->name)\n\n" + "'mtdparts' - partition list\n\n" + "mtdparts=mtdparts=[;...]\n\n" + " := :[,...]\n" + " := unique device tag used by linux kernel to find mtd device (mtd->name)\n" + " := [@][][]\n" + " := standard linux memsize OR '-' to denote all remaining space\n" + " := partition start offset within the device\n" + " := '(' NAME ')'\n" + " := when set to 'ro' makes partition read-only (not used, passed to kernel)\n" +); +#endif /* #ifdef CONFIG_JFFS2_CMDLINE */ + +/***************************************************/ + +#endif /* CFG_CMD_JFFS2 */ diff --git a/common/cmd_load.c b/common/cmd_load.c new file mode 100644 index 0000000..7498497 --- /dev/null +++ b/common/cmd_load.c @@ -0,0 +1,1055 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Serial up- and download support + */ +#include +#include +#include +#include +#include + + +#if (CONFIG_COMMANDS & CFG_CMD_LOADS) +static ulong load_serial (ulong offset); +static int read_record (char *buf, ulong len); +# if (CONFIG_COMMANDS & CFG_CMD_SAVES) +static int save_serial (ulong offset, ulong size); +static int write_record (char *buf); +# endif /* CFG_CMD_SAVES */ + +static int do_echo = 1; +#endif /* CFG_CMD_LOADS */ + +/* -------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_LOADS) +int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong offset = 0; + ulong addr; + int i; + char *env_echo; + int rcode = 0; +#ifdef CFG_LOADS_BAUD_CHANGE + DECLARE_GLOBAL_DATA_PTR; + int load_baudrate, current_baudrate; + + load_baudrate = current_baudrate = gd->baudrate; +#endif + + if (((env_echo = getenv("loads_echo")) != NULL) && (*env_echo == '1')) { + do_echo = 1; + } else { + do_echo = 0; + } + +#ifdef CFG_LOADS_BAUD_CHANGE + if (argc >= 2) { + offset = simple_strtoul(argv[1], NULL, 16); + } + if (argc == 3) { + load_baudrate = (int)simple_strtoul(argv[2], NULL, 10); + + /* default to current baudrate */ + if (load_baudrate == 0) + load_baudrate = current_baudrate; + } + if (load_baudrate != current_baudrate) { + printf ("## Switch baudrate to %d bps and press ENTER ...\n", + load_baudrate); + udelay(50000); + gd->baudrate = load_baudrate; + serial_setbrg (); + udelay(50000); + for (;;) { + if (getc() == '\r') + break; + } + } +#else /* ! CFG_LOADS_BAUD_CHANGE */ + if (argc == 2) { + offset = simple_strtoul(argv[1], NULL, 16); + } +#endif /* CFG_LOADS_BAUD_CHANGE */ + + printf ("## Ready for S-Record download ...\n"); + + addr = load_serial (offset); + + /* + * Gather any trailing characters (for instance, the ^D which + * is sent by 'cu' after sending a file), and give the + * box some time (100 * 1 ms) + */ + for (i=0; i<100; ++i) { + if (tstc()) { + (void) getc(); + } + udelay(1000); + } + + if (addr == ~0) { + printf ("## S-Record download aborted\n"); + rcode = 1; + } else { + printf ("## Start Addr = 0x%08lX\n", addr); + load_addr = addr; + } + +#ifdef CFG_LOADS_BAUD_CHANGE + if (load_baudrate != current_baudrate) { + printf ("## Switch baudrate to %d bps and press ESC ...\n", + current_baudrate); + udelay (50000); + gd->baudrate = current_baudrate; + serial_setbrg (); + udelay (50000); + for (;;) { + if (getc() == 0x1B) /* ESC */ + break; + } + } +#endif + return rcode; +} + +static ulong +load_serial (ulong offset) +{ + char record[SREC_MAXRECLEN + 1]; /* buffer for one S-Record */ + char binbuf[SREC_MAXBINLEN]; /* buffer for binary data */ + int binlen; /* no. of data bytes in S-Rec. */ + int type; /* return code for record type */ + ulong addr; /* load address from S-Record */ + ulong size; /* number of bytes transferred */ + char buf[32]; + ulong store_addr; + ulong start_addr = ~0; + ulong end_addr = 0; + int line_count = 0; + + while (read_record(record, SREC_MAXRECLEN + 1) >= 0) { + type = srec_decode (record, &binlen, &addr, binbuf); + + if (type < 0) { + return (~0); /* Invalid S-Record */ + } + + switch (type) { + case SREC_DATA2: + case SREC_DATA3: + case SREC_DATA4: + store_addr = addr + offset; +#ifndef CFG_NO_FLASH + if (addr2info(store_addr)) { + int rc; + + rc = flash_write((char *)binbuf,store_addr,binlen); + if (rc != 0) { + flash_perror (rc); + return (~0); + } + } else +#endif + { + memcpy ((char *)(store_addr), binbuf, binlen); + } + if ((store_addr) < start_addr) + start_addr = store_addr; + if ((store_addr + binlen - 1) > end_addr) + end_addr = store_addr + binlen - 1; + break; + case SREC_END2: + case SREC_END3: + case SREC_END4: + udelay (10000); + size = end_addr - start_addr + 1; + printf ("\n" + "## First Load Addr = 0x%08lX\n" + "## Last Load Addr = 0x%08lX\n" + "## Total Size = 0x%08lX = %ld Bytes\n", + start_addr, end_addr, size, size + ); + flush_cache (start_addr, size); + sprintf(buf, "%lX", size); + setenv("filesize", buf); + return (addr); + case SREC_START: + break; + default: + break; + } + if (!do_echo) { /* print a '.' every 100 lines */ + if ((++line_count % 100) == 0) + putc ('.'); + } + } + + return (~0); /* Download aborted */ +} + +static int +read_record (char *buf, ulong len) +{ + DECLARE_GLOBAL_DATA_PTR; + char *p; + char c; + + --len; /* always leave room for terminating '\0' byte */ + + for (p=buf; p < buf+len; ++p) { + c = getc(); /* read character */ + if (do_echo) + putc (c); /* ... and echo it */ + + switch (c) { + case '\r': + case '\n': + *p = '\0'; + return (p - buf); + case '\0': + case 0x03: /* ^C - Control C */ + return (-1); + default: + *p = c; + } + + /* Check for the console hangup (if any different from serial) */ + if (gd->jt[XF_getc] != getc) { + if (ctrlc()) { + return (-1); + } + } + } + + /* line too long - truncate */ + *p = '\0'; + return (p - buf); +} + +#if (CONFIG_COMMANDS & CFG_CMD_SAVES) + +int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong offset = 0; + ulong size = 0; +#ifdef CFG_LOADS_BAUD_CHANGE + DECLARE_GLOBAL_DATA_PTR; + int save_baudrate, current_baudrate; + + save_baudrate = current_baudrate = gd->baudrate; +#endif + + if (argc >= 2) { + offset = simple_strtoul(argv[1], NULL, 16); + } +#ifdef CFG_LOADS_BAUD_CHANGE + if (argc >= 3) { + size = simple_strtoul(argv[2], NULL, 16); + } + if (argc == 4) { + save_baudrate = (int)simple_strtoul(argv[3], NULL, 10); + + /* default to current baudrate */ + if (save_baudrate == 0) + save_baudrate = current_baudrate; + } + if (save_baudrate != current_baudrate) { + printf ("## Switch baudrate to %d bps and press ENTER ...\n", + save_baudrate); + udelay(50000); + gd->baudrate = save_baudrate; + serial_setbrg (); + udelay(50000); + for (;;) { + if (getc() == '\r') + break; + } + } +#else /* ! CFG_LOADS_BAUD_CHANGE */ + if (argc == 3) { + size = simple_strtoul(argv[2], NULL, 16); + } +#endif /* CFG_LOADS_BAUD_CHANGE */ + + printf ("## Ready for S-Record upload, press ENTER to proceed ...\n"); + for (;;) { + if (getc() == '\r') + break; + } + if(save_serial (offset, size)) { + printf ("## S-Record upload aborted\n"); + } else { + printf ("## S-Record upload complete\n"); + } +#ifdef CFG_LOADS_BAUD_CHANGE + if (save_baudrate != current_baudrate) { + printf ("## Switch baudrate to %d bps and press ESC ...\n", + (int)current_baudrate); + udelay (50000); + gd->baudrate = current_baudrate; + serial_setbrg (); + udelay (50000); + for (;;) { + if (getc() == 0x1B) /* ESC */ + break; + } + } +#endif + return 0; +} + +#define SREC3_START "S0030000FC\n" +#define SREC3_FORMAT "S3%02X%08lX%s%02X\n" +#define SREC3_END "S70500000000FA\n" +#define SREC_BYTES_PER_RECORD 16 + +static int save_serial (ulong address, ulong count) +{ + int i, c, reclen, checksum, length; + char *hex = "0123456789ABCDEF"; + char record[2*SREC_BYTES_PER_RECORD+16]; /* buffer for one S-Record */ + char data[2*SREC_BYTES_PER_RECORD+1]; /* buffer for hex data */ + + reclen = 0; + checksum = 0; + + if(write_record(SREC3_START)) /* write the header */ + return (-1); + do { + if(count) { /* collect hex data in the buffer */ + c = *(volatile uchar*)(address + reclen); /* get one byte */ + checksum += c; /* accumulate checksum */ + data[2*reclen] = hex[(c>>4)&0x0f]; + data[2*reclen+1] = hex[c & 0x0f]; + data[2*reclen+2] = '\0'; + ++reclen; + --count; + } + if(reclen == SREC_BYTES_PER_RECORD || count == 0) { + /* enough data collected for one record: dump it */ + if(reclen) { /* build & write a data record: */ + /* address + data + checksum */ + length = 4 + reclen + 1; + + /* accumulate length bytes into checksum */ + for(i = 0; i < 2; i++) + checksum += (length >> (8*i)) & 0xff; + + /* accumulate address bytes into checksum: */ + for(i = 0; i < 4; i++) + checksum += (address >> (8*i)) & 0xff; + + /* make proper checksum byte: */ + checksum = ~checksum & 0xff; + + /* output one record: */ + sprintf(record, SREC3_FORMAT, length, address, data, checksum); + if(write_record(record)) + return (-1); + } + address += reclen; /* increment address */ + checksum = 0; + reclen = 0; + } + } + while(count); + if(write_record(SREC3_END)) /* write the final record */ + return (-1); + return(0); +} + +static int +write_record (char *buf) +{ + char c; + + while((c = *buf++)) + putc(c); + + /* Check for the console hangup (if any different from serial) */ + + if (ctrlc()) { + return (-1); + } + return (0); +} +# endif /* CFG_CMD_SAVES */ + +#endif /* CFG_CMD_LOADS */ + + +#if (CONFIG_COMMANDS & CFG_CMD_LOADB) /* loadb command (load binary) included */ + +#define XON_CHAR 17 +#define XOFF_CHAR 19 +#define START_CHAR 0x01 +#define ETX_CHAR 0x03 +#define END_CHAR 0x0D +#define SPACE 0x20 +#define K_ESCAPE 0x23 +#define SEND_TYPE 'S' +#define DATA_TYPE 'D' +#define ACK_TYPE 'Y' +#define NACK_TYPE 'N' +#define BREAK_TYPE 'B' +#define tochar(x) ((char) (((x) + SPACE) & 0xff)) +#define untochar(x) ((int) (((x) - SPACE) & 0xff)) + +extern int os_data_count; +extern int os_data_header[8]; + +static void set_kerm_bin_mode(unsigned long *); +static int k_recv(void); +static ulong load_serial_bin (ulong offset); + + +char his_eol; /* character he needs at end of packet */ +int his_pad_count; /* number of pad chars he needs */ +char his_pad_char; /* pad chars he needs */ +char his_quote; /* quote chars he'll use */ + +int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong offset = 0; + ulong addr; + int load_baudrate, current_baudrate; + int rcode = 0; + char *s; + + /* pre-set offset from CFG_LOAD_ADDR */ + offset = CFG_LOAD_ADDR; + + /* pre-set offset from $loadaddr */ + if ((s = getenv("loadaddr")) != NULL) { + offset = simple_strtoul(s, NULL, 16); + } + + load_baudrate = current_baudrate = gd->baudrate; + + if (argc >= 2) { + offset = simple_strtoul(argv[1], NULL, 16); + } + if (argc == 3) { + load_baudrate = (int)simple_strtoul(argv[2], NULL, 10); + + /* default to current baudrate */ + if (load_baudrate == 0) + load_baudrate = current_baudrate; + } + + if (load_baudrate != current_baudrate) { + printf ("## Switch baudrate to %d bps and press ENTER ...\n", + load_baudrate); + udelay(50000); + gd->baudrate = load_baudrate; + serial_setbrg (); + udelay(50000); + for (;;) { + if (getc() == '\r') + break; + } + } + + printf ("## Ready for binary (kermit) download " + "to 0x%08lX at %d bps...\n", + offset, + load_baudrate); + addr = load_serial_bin (offset); + + if (addr == ~0) { + load_addr = 0; + printf ("## Binary (kermit) download aborted\n"); + rcode = 1; + } else { + printf ("## Start Addr = 0x%08lX\n", addr); + load_addr = addr; + } + + if (load_baudrate != current_baudrate) { + printf ("## Switch baudrate to %d bps and press ESC ...\n", + current_baudrate); + udelay (50000); + gd->baudrate = current_baudrate; + serial_setbrg (); + udelay (50000); + for (;;) { + if (getc() == 0x1B) /* ESC */ + break; + } + } + +#ifdef CONFIG_AUTOSCRIPT + if (load_addr) { + char *s; + + if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { + printf("Running autoscript at addr 0x%08lX ...\n", load_addr); + rcode = autoscript (load_addr); + } + } +#endif + return rcode; +} + + +static ulong load_serial_bin (ulong offset) +{ + int size, i; + char buf[32]; + + set_kerm_bin_mode ((ulong *) offset); + size = k_recv (); + + /* + * Gather any trailing characters (for instance, the ^D which + * is sent by 'cu' after sending a file), and give the + * box some time (100 * 1 ms) + */ + for (i=0; i<100; ++i) { + if (tstc()) { + (void) getc(); + } + udelay(1000); + } + + flush_cache (offset, size); + + printf("## Total Size = 0x%08x = %d Bytes\n", size, size); + sprintf(buf, "%X", size); + setenv("filesize", buf); + + return offset; +} + +void send_pad (void) +{ + int count = his_pad_count; + + while (count-- > 0) + putc (his_pad_char); +} + +/* converts escaped kermit char to binary char */ +char ktrans (char in) +{ + if ((in & 0x60) == 0x40) { + return (char) (in & ~0x40); + } else if ((in & 0x7f) == 0x3f) { + return (char) (in | 0x40); + } else + return in; +} + +int chk1 (char *buffer) +{ + int total = 0; + + while (*buffer) { + total += *buffer++; + } + return (int) ((total + ((total >> 6) & 0x03)) & 0x3f); +} + +void s1_sendpacket (char *packet) +{ + send_pad (); + while (*packet) { + putc (*packet++); + } +} + +static char a_b[24]; +void send_ack (int n) +{ + a_b[0] = START_CHAR; + a_b[1] = tochar (3); + a_b[2] = tochar (n); + a_b[3] = ACK_TYPE; + a_b[4] = '\0'; + a_b[4] = tochar (chk1 (&a_b[1])); + a_b[5] = his_eol; + a_b[6] = '\0'; + s1_sendpacket (a_b); +} + +void send_nack (int n) +{ + a_b[0] = START_CHAR; + a_b[1] = tochar (3); + a_b[2] = tochar (n); + a_b[3] = NACK_TYPE; + a_b[4] = '\0'; + a_b[4] = tochar (chk1 (&a_b[1])); + a_b[5] = his_eol; + a_b[6] = '\0'; + s1_sendpacket (a_b); +} + + +/* os_data_* takes an OS Open image and puts it into memory, and + puts the boot header in an array named os_data_header + + if image is binary, no header is stored in os_data_header. +*/ +void (*os_data_init) (void); +void (*os_data_char) (char new_char); +static int os_data_state, os_data_state_saved; +int os_data_count; +static int os_data_count_saved; +static char *os_data_addr, *os_data_addr_saved; +static char *bin_start_address; +int os_data_header[8]; +static void bin_data_init (void) +{ + os_data_state = 0; + os_data_count = 0; + os_data_addr = bin_start_address; +} +static void os_data_save (void) +{ + os_data_state_saved = os_data_state; + os_data_count_saved = os_data_count; + os_data_addr_saved = os_data_addr; +} +static void os_data_restore (void) +{ + os_data_state = os_data_state_saved; + os_data_count = os_data_count_saved; + os_data_addr = os_data_addr_saved; +} +static void bin_data_char (char new_char) +{ + switch (os_data_state) { + case 0: /* data */ + *os_data_addr++ = new_char; + --os_data_count; + break; + } +} +static void set_kerm_bin_mode (unsigned long *addr) +{ + bin_start_address = (char *) addr; + os_data_init = bin_data_init; + os_data_char = bin_data_char; +} + + +/* k_data_* simply handles the kermit escape translations */ +static int k_data_escape, k_data_escape_saved; +void k_data_init (void) +{ + k_data_escape = 0; + os_data_init (); +} +void k_data_save (void) +{ + k_data_escape_saved = k_data_escape; + os_data_save (); +} +void k_data_restore (void) +{ + k_data_escape = k_data_escape_saved; + os_data_restore (); +} +void k_data_char (char new_char) +{ + if (k_data_escape) { + /* last char was escape - translate this character */ + os_data_char (ktrans (new_char)); + k_data_escape = 0; + } else { + if (new_char == his_quote) { + /* this char is escape - remember */ + k_data_escape = 1; + } else { + /* otherwise send this char as-is */ + os_data_char (new_char); + } + } +} + +#define SEND_DATA_SIZE 20 +char send_parms[SEND_DATA_SIZE]; +char *send_ptr; + +/* handle_send_packet interprits the protocol info and builds and + sends an appropriate ack for what we can do */ +void handle_send_packet (int n) +{ + int length = 3; + int bytes; + + /* initialize some protocol parameters */ + his_eol = END_CHAR; /* default end of line character */ + his_pad_count = 0; + his_pad_char = '\0'; + his_quote = K_ESCAPE; + + /* ignore last character if it filled the buffer */ + if (send_ptr == &send_parms[SEND_DATA_SIZE - 1]) + --send_ptr; + bytes = send_ptr - send_parms; /* how many bytes we'll process */ + do { + if (bytes-- <= 0) + break; + /* handle MAXL - max length */ + /* ignore what he says - most I'll take (here) is 94 */ + a_b[++length] = tochar (94); + if (bytes-- <= 0) + break; + /* handle TIME - time you should wait for my packets */ + /* ignore what he says - don't wait for my ack longer than 1 second */ + a_b[++length] = tochar (1); + if (bytes-- <= 0) + break; + /* handle NPAD - number of pad chars I need */ + /* remember what he says - I need none */ + his_pad_count = untochar (send_parms[2]); + a_b[++length] = tochar (0); + if (bytes-- <= 0) + break; + /* handle PADC - pad chars I need */ + /* remember what he says - I need none */ + his_pad_char = ktrans (send_parms[3]); + a_b[++length] = 0x40; /* He should ignore this */ + if (bytes-- <= 0) + break; + /* handle EOL - end of line he needs */ + /* remember what he says - I need CR */ + his_eol = untochar (send_parms[4]); + a_b[++length] = tochar (END_CHAR); + if (bytes-- <= 0) + break; + /* handle QCTL - quote control char he'll use */ + /* remember what he says - I'll use '#' */ + his_quote = send_parms[5]; + a_b[++length] = '#'; + if (bytes-- <= 0) + break; + /* handle QBIN - 8-th bit prefixing */ + /* ignore what he says - I refuse */ + a_b[++length] = 'N'; + if (bytes-- <= 0) + break; + /* handle CHKT - the clock check type */ + /* ignore what he says - I do type 1 (for now) */ + a_b[++length] = '1'; + if (bytes-- <= 0) + break; + /* handle REPT - the repeat prefix */ + /* ignore what he says - I refuse (for now) */ + a_b[++length] = 'N'; + if (bytes-- <= 0) + break; + /* handle CAPAS - the capabilities mask */ + /* ignore what he says - I only do long packets - I don't do windows */ + a_b[++length] = tochar (2); /* only long packets */ + a_b[++length] = tochar (0); /* no windows */ + a_b[++length] = tochar (94); /* large packet msb */ + a_b[++length] = tochar (94); /* large packet lsb */ + } while (0); + + a_b[0] = START_CHAR; + a_b[1] = tochar (length); + a_b[2] = tochar (n); + a_b[3] = ACK_TYPE; + a_b[++length] = '\0'; + a_b[length] = tochar (chk1 (&a_b[1])); + a_b[++length] = his_eol; + a_b[++length] = '\0'; + s1_sendpacket (a_b); +} + +/* k_recv receives a OS Open image file over kermit line */ +static int k_recv (void) +{ + char new_char; + char k_state, k_state_saved; + int sum; + int done; + int length; + int n, last_n; + int z = 0; + int len_lo, len_hi; + + /* initialize some protocol parameters */ + his_eol = END_CHAR; /* default end of line character */ + his_pad_count = 0; + his_pad_char = '\0'; + his_quote = K_ESCAPE; + + /* initialize the k_recv and k_data state machine */ + done = 0; + k_state = 0; + k_data_init (); + k_state_saved = k_state; + k_data_save (); + n = 0; /* just to get rid of a warning */ + last_n = -1; + + /* expect this "type" sequence (but don't check): + S: send initiate + F: file header + D: data (multiple) + Z: end of file + B: break transmission + */ + + /* enter main loop */ + while (!done) { + /* set the send packet pointer to begining of send packet parms */ + send_ptr = send_parms; + + /* With each packet, start summing the bytes starting with the length. + Save the current sequence number. + Note the type of the packet. + If a character less than SPACE (0x20) is received - error. + */ + +#if 0 + /* OLD CODE, Prior to checking sequence numbers */ + /* first have all state machines save current states */ + k_state_saved = k_state; + k_data_save (); +#endif + + /* get a packet */ + /* wait for the starting character or ^C */ + for (;;) { + switch (getc ()) { + case START_CHAR: /* start packet */ + goto START; + case ETX_CHAR: /* ^C waiting for packet */ + return (0); + default: + ; + } + } +START: + /* get length of packet */ + sum = 0; + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + length = untochar (new_char); + /* get sequence number */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + n = untochar (new_char); + --length; + + /* NEW CODE - check sequence numbers for retried packets */ + /* Note - this new code assumes that the sequence number is correctly + * received. Handling an invalid sequence number adds another layer + * of complexity that may not be needed - yet! At this time, I'm hoping + * that I don't need to buffer the incoming data packets and can write + * the data into memory in real time. + */ + if (n == last_n) { + /* same sequence number, restore the previous state */ + k_state = k_state_saved; + k_data_restore (); + } else { + /* new sequence number, checkpoint the download */ + last_n = n; + k_state_saved = k_state; + k_data_save (); + } + /* END NEW CODE */ + + /* get packet type */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + k_state = new_char; + --length; + /* check for extended length */ + if (length == -2) { + /* (length byte was 0, decremented twice) */ + /* get the two length bytes */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + len_hi = untochar (new_char); + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + len_lo = untochar (new_char); + length = len_hi * 95 + len_lo; + /* check header checksum */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) + goto packet_error; + sum += new_char & 0xff; +/* --length; */ /* new length includes only data and block check to come */ + } + /* bring in rest of packet */ + while (length > 1) { + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + --length; + if (k_state == DATA_TYPE) { + /* pass on the data if this is a data packet */ + k_data_char (new_char); + } else if (k_state == SEND_TYPE) { + /* save send pack in buffer as is */ + *send_ptr++ = new_char; + /* if too much data, back off the pointer */ + if (send_ptr >= &send_parms[SEND_DATA_SIZE]) + --send_ptr; + } + } + /* get and validate checksum character */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) + goto packet_error; + /* get END_CHAR */ + new_char = getc (); + if (new_char != END_CHAR) { + packet_error: + /* restore state machines */ + k_state = k_state_saved; + k_data_restore (); + /* send a negative acknowledge packet in */ + send_nack (n); + } else if (k_state == SEND_TYPE) { + /* crack the protocol parms, build an appropriate ack packet */ + handle_send_packet (n); + } else { + /* send simple acknowledge packet in */ + send_ack (n); + /* quit if end of transmission */ + if (k_state == BREAK_TYPE) + done = 1; + } + ++z; + } + return ((ulong) os_data_addr - (ulong) bin_start_address); +} +#endif /* CFG_CMD_LOADB */ + +/* -------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_LOADS) + +#ifdef CFG_LOADS_BAUD_CHANGE +U_BOOT_CMD( + loads, 3, 0, do_load_serial, + "loads - load S-Record file over serial line\n", + "[ off ] [ baud ]\n" + " - load S-Record file over serial line" + " with offset 'off' and baudrate 'baud'\n" +); + +#else /* ! CFG_LOADS_BAUD_CHANGE */ +U_BOOT_CMD( + loads, 2, 0, do_load_serial, + "loads - load S-Record file over serial line\n", + "[ off ]\n" + " - load S-Record file over serial line with offset 'off'\n" +); +#endif /* CFG_LOADS_BAUD_CHANGE */ + +/* + * SAVES always requires LOADS support, but not vice versa + */ + + +#if (CONFIG_COMMANDS & CFG_CMD_SAVES) +#ifdef CFG_LOADS_BAUD_CHANGE +U_BOOT_CMD( + saves, 4, 0, do_save_serial, + "saves - save S-Record file over serial line\n", + "[ off ] [size] [ baud ]\n" + " - save S-Record file over serial line" + " with offset 'off', size 'size' and baudrate 'baud'\n" +); +#else /* ! CFG_LOADS_BAUD_CHANGE */ +U_BOOT_CMD( + saves, 3, 0, do_save_serial, + "saves - save S-Record file over serial line\n", + "[ off ] [size]\n" + " - save S-Record file over serial line with offset 'off' and size 'size'\n" +); +#endif /* CFG_LOADS_BAUD_CHANGE */ +#endif /* CFG_CMD_SAVES */ +#endif /* CFG_CMD_LOADS */ + + +#if (CONFIG_COMMANDS & CFG_CMD_LOADB) +U_BOOT_CMD( + loadb, 3, 0, do_load_serial_bin, + "loadb - load binary file over serial line (kermit mode)\n", + "[ off ] [ baud ]\n" + " - load binary file over serial line" + " with offset 'off' and baudrate 'baud'\n" +); + +#endif /* CFG_CMD_LOADB */ + +/* -------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_HWFLOW) +int do_hwflow (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern int hwflow_onoff(int); + + if (argc == 2) { + if (strcmp(argv[1], "off") == 0) + hwflow_onoff(-1); + else + if (strcmp(argv[1], "on") == 0) + hwflow_onoff(1); + else + printf("Usage: %s\n", cmdtp->usage); + } + printf("RTS/CTS hardware flow control: %s\n", hwflow_onoff(0) ? "on" : "off"); + return 0; +} + +/* -------------------------------------------------------------------- */ + +U_BOOT_CMD( + hwflow, 2, 0, do_hwflow, + "hwflow - turn the harwdare flow control on/off\n", + "[on|off]\n - change RTS/CTS hardware flow control over serial line\n" +); + +#endif /* CFG_CMD_HWFLOW */ diff --git a/common/cmd_log.c b/common/cmd_log.c new file mode 100644 index 0000000..efc9689 --- /dev/null +++ b/common/cmd_log.c @@ -0,0 +1,266 @@ +/* + * (C) Copyright 2002 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de. + * + * Code used from linux/kernel/printk.c + * Copyright (C) 1991, 1992 Linus Torvalds + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Comments: + * + * After relocating the code, the environment variable "loglevel" is + * copied to console_loglevel. The functionality is similar to the + * handling in the Linux kernel, i.e. messages logged with a priority + * less than console_loglevel are also output to stdout. + * + * If you want messages with the default level (e.g. POST messages) to + * appear on stdout also, make sure the environment variable + * "loglevel" is set at boot time to a number higher than + * default_message_loglevel below. + */ + +/* + * Logbuffer handling routines + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_LOGBUFFER) + +/* Local prototypes */ +static void logbuff_putc (const char c); +static void logbuff_puts (const char *s); +static int logbuff_printk(const char *line); + +static char buf[1024]; + +/* This combination will not print messages with the default loglevel */ +static unsigned console_loglevel = 3; +static unsigned default_message_loglevel = 4; +static unsigned char *log_buf = NULL; +static unsigned long *ext_log_size; +static unsigned long *ext_log_start; +static unsigned long *ext_logged_chars; +#define log_size (*ext_log_size) +#define log_start (*ext_log_start) +#define logged_chars (*ext_logged_chars) + +/* Forced by code, eh! */ +#define LOGBUFF_MAGIC 0xc0de4ced + +/* The mapping used here has to be the same as in setup_ext_logbuff () + in linux/kernel/printk */ +void logbuff_init_ptrs (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long *ext_tag; + unsigned long post_word; + char *s; + + log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN); + ext_tag = (unsigned long *)(log_buf)-4; + ext_log_start = (unsigned long *)(log_buf)-3; + ext_log_size = (unsigned long *)(log_buf)-2; + ext_logged_chars = (unsigned long *)(log_buf)-1; + post_word = post_word_load(); +#ifdef CONFIG_POST + /* The post routines have setup the word so we can simply test it */ + if (post_word_load () & POST_COLDBOOT) { + logged_chars = log_size = log_start = 0; + *ext_tag = LOGBUFF_MAGIC; + } +#else + /* No post routines, so we do our own checking */ + if (post_word != LOGBUFF_MAGIC) { + logged_chars = log_size = log_start = 0; + post_word_store (LOGBUFF_MAGIC); + *ext_tag = LOGBUFF_MAGIC; + } +#endif + /* Initialize default loglevel if present */ + if ((s = getenv ("loglevel")) != NULL) + console_loglevel = (int)simple_strtoul (s, NULL, 10); + + gd->post_log_word |= LOGBUFF_INITIALIZED; +} + +int drv_logbuff_init (void) +{ + device_t logdev; + int rc; + + /* Device initialization */ + memset (&logdev, 0, sizeof (logdev)); + + strcpy (logdev.name, "logbuff"); + logdev.ext = 0; /* No extensions */ + logdev.flags = DEV_FLAGS_OUTPUT; /* Output only */ + logdev.putc = logbuff_putc; /* 'putc' function */ + logdev.puts = logbuff_puts; /* 'puts' function */ + + rc = device_register (&logdev); + + return (rc == 0) ? 1 : rc; +} + +static void logbuff_putc (const char c) +{ + char buf[2]; + buf[0] = c; + buf[1] = '\0'; + logbuff_printk (buf); +} + +static void logbuff_puts (const char *s) +{ + logbuff_printk (s); +} + +void logbuff_log(char *msg) +{ + DECLARE_GLOBAL_DATA_PTR; + + if ((gd->post_log_word & LOGBUFF_INITIALIZED)) { + logbuff_printk (msg); + } else { + /* Can happen only for pre-relocated errors as logging */ + /* at that stage should be disabled */ + puts (msg); + } +} + +/* + * Subroutine: do_log + * + * Description: Handler for 'log' command.. + * + * Inputs: argv[1] contains the subcommand + * + * Return: None + * + */ +int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *s; + unsigned long i; + + if (strcmp(argv[1],"append") == 0) { + /* Log concatenation of all arguments separated by spaces */ + for (i=2; iusage); + return 1; + + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} +#if defined(CONFIG_LOGBUFFER) +U_BOOT_CMD( + log, 255, 1, do_log, + "log - manipulate logbuffer\n", + "info - show pointer details\n" + "log reset - clear contents\n" + "log show - show contents\n" + "log append - append to the logbuffer\n" +); +#endif /* CONFIG_LOGBUFFER */ +static int logbuff_printk(const char *line) +{ + int i; + char *msg, *p, *buf_end; + int line_feed; + static signed char msg_level = -1; + + strcpy (buf + 3, line); + i = strlen (line); + buf_end = buf + 3 + i; + for (p = buf + 3; p < buf_end; p++) { + msg = p; + if (msg_level < 0) { + if ( + p[0] != '<' || + p[1] < '0' || + p[1] > '7' || + p[2] != '>' + ) { + p -= 3; + p[0] = '<'; + p[1] = default_message_loglevel + '0'; + p[2] = '>'; + } else + msg += 3; + msg_level = p[1] - '0'; + } + line_feed = 0; + for (; p < buf_end; p++) { + log_buf[(log_start+log_size) & LOGBUFF_MASK] = *p; + if (log_size < LOGBUFF_LEN) + log_size++; + else + log_start++; + + logged_chars++; + if (*p == '\n') { + line_feed = 1; + break; + } + } + if (msg_level < console_loglevel) { + printf("%s", msg); + } + if (line_feed) + msg_level = -1; + } + return i; +} + +#endif /* (CONFIG_LOGBUFFER) */ diff --git a/common/cmd_mem.c b/common/cmd_mem.c new file mode 100644 index 0000000..0f4f9b7 --- /dev/null +++ b/common/cmd_mem.c @@ -0,0 +1,1292 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Memory Functions + * + * Copied from FADS ROM, Dan Malek (dmalek@jlc.net) + */ + +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_MMC) +#include +#endif +#ifdef CONFIG_HAS_DATAFLASH +#include +#endif + +#if (CONFIG_COMMANDS & (CFG_CMD_MEMORY | \ + CFG_CMD_I2C | \ + CFG_CMD_ITEST | \ + CFG_CMD_PCI | \ + CMD_CMD_PORTIO ) ) +int cmd_get_data_size(char* arg, int default_size) +{ + /* Check for a size specification .b, .w or .l. + */ + int len = strlen(arg); + if (len > 2 && arg[len-2] == '.') { + switch(arg[len-1]) { + case 'b': + return 1; + case 'w': + return 2; + case 'l': + return 4; + case 's': + return -2; + default: + return -1; + } + } + return default_size; +} +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_MEMORY) + +#ifdef CMD_MEM_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +static int mod_mem(cmd_tbl_t *, int, int, int, char *[]); + +/* Display values from last command. + * Memory modify remembered values are different from display memory. + */ +uint dp_last_addr, dp_last_size; +uint dp_last_length = 0x40; +uint mm_last_addr, mm_last_size; + +static ulong base_address = 0; + +/* Memory Display + * + * Syntax: + * md{.b, .w, .l} {addr} {len} + */ +#define DISP_LINE_LEN 16 +int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, length; + ulong i, nbytes, linebytes; + u_char *cp; + int size; + int rc = 0; + + /* We use the last specified parameters, unless new ones are + * entered. + */ + addr = dp_last_addr; + size = dp_last_size; + length = dp_last_length; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((flag & CMD_FLAG_REPEAT) == 0) { + /* New command specified. Check for a size specification. + * Defaults to long if no or incorrect specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 0) + return 1; + + /* Address is specified since argc > 1 + */ + addr = simple_strtoul(argv[1], NULL, 16); + addr += base_address; + + /* If another parameter, it is the length to display. + * Length is the number of objects, not number of bytes. + */ + if (argc > 2) + length = simple_strtoul(argv[2], NULL, 16); + } + + /* Print the lines. + * + * We buffer all read data, so we can make sure data is read only + * once, and all accesses are with the specified bus width. + */ + nbytes = length * size; + do { + char linebuf[DISP_LINE_LEN]; + uint *uip = (uint *)linebuf; + ushort *usp = (ushort *)linebuf; + u_char *ucp = (u_char *)linebuf; +#ifdef CONFIG_HAS_DATAFLASH + int rc; +#endif + printf("%08lx:", addr); + linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; + +#ifdef CONFIG_HAS_DATAFLASH + if ((rc = read_dataflash(addr, (linebytes/size)*size, linebuf)) == DATAFLASH_OK){ + /* if outside dataflash */ + /*if (rc != 1) { + dataflash_perror (rc); + return (1); + }*/ + for (i=0; i 0x7e)) + putc ('.'); + else + printf("%c", *cp); + cp++; + } + putc ('\n'); + nbytes -= linebytes; + if (ctrlc()) { + rc = 1; + break; + } + } while (nbytes > 0); + + dp_last_addr = addr; + dp_last_length = length; + dp_last_size = size; + return (rc); +} + +int do_mem_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return mod_mem (cmdtp, 1, flag, argc, argv); +} +int do_mem_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return mod_mem (cmdtp, 0, flag, argc, argv); +} + +int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, writeval, count; + int size; + + if ((argc < 3) || (argc > 4)) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Check for size specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 1) + return 1; + + /* Address is specified since argc > 1 + */ + addr = simple_strtoul(argv[1], NULL, 16); + addr += base_address; + + /* Get the value to write. + */ + writeval = simple_strtoul(argv[2], NULL, 16); + + /* Count ? */ + if (argc == 4) { + count = simple_strtoul(argv[3], NULL, 16); + } else { + count = 1; + } + + while (count-- > 0) { + if (size == 4) + *((ulong *)addr) = (ulong )writeval; + else if (size == 2) + *((ushort *)addr) = (ushort)writeval; + else + *((u_char *)addr) = (u_char)writeval; + addr += size; + } + return 0; +} + +#ifdef CONFIG_MX_CYCLIC +int do_mem_mdc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + ulong count; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + count = simple_strtoul(argv[3], NULL, 10); + + for (;;) { + do_mem_md (NULL, 0, 3, argv); + + /* delay for ms... */ + for (i=0; iusage); + return 1; + } + + count = simple_strtoul(argv[3], NULL, 10); + + for (;;) { + do_mem_mw (NULL, 0, 3, argv); + + /* delay for ms... */ + for (i=0; iusage); + return 1; + } + + /* Check for size specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 0) + return 1; + + addr1 = simple_strtoul(argv[1], NULL, 16); + addr1 += base_address; + + addr2 = simple_strtoul(argv[2], NULL, 16); + addr2 += base_address; + + count = simple_strtoul(argv[3], NULL, 16); + +#ifdef CONFIG_HAS_DATAFLASH + if (addr_dataflash(addr1) | addr_dataflash(addr2)){ + puts ("Comparison with DataFlash space not supported.\n\r"); + return 0; + } +#endif + + ngood = 0; + + while (count-- > 0) { + if (size == 4) { + ulong word1 = *(ulong *)addr1; + ulong word2 = *(ulong *)addr2; + if (word1 != word2) { + printf("word at 0x%08lx (0x%08lx) " + "!= word at 0x%08lx (0x%08lx)\n", + addr1, word1, addr2, word2); + rcode = 1; + break; + } + } + else if (size == 2) { + ushort hword1 = *(ushort *)addr1; + ushort hword2 = *(ushort *)addr2; + if (hword1 != hword2) { + printf("halfword at 0x%08lx (0x%04x) " + "!= halfword at 0x%08lx (0x%04x)\n", + addr1, hword1, addr2, hword2); + rcode = 1; + break; + } + } + else { + u_char byte1 = *(u_char *)addr1; + u_char byte2 = *(u_char *)addr2; + if (byte1 != byte2) { + printf("byte at 0x%08lx (0x%02x) " + "!= byte at 0x%08lx (0x%02x)\n", + addr1, byte1, addr2, byte2); + rcode = 1; + break; + } + } + ngood++; + addr1 += size; + addr2 += size; + } + + printf("Total of %ld %s%s were the same\n", + ngood, size == 4 ? "word" : size == 2 ? "halfword" : "byte", + ngood == 1 ? "" : "s"); + return rcode; +} + +int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, dest, count; + int size; + + if (argc != 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Check for size specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 0) + return 1; + + addr = simple_strtoul(argv[1], NULL, 16); + addr += base_address; + + dest = simple_strtoul(argv[2], NULL, 16); + dest += base_address; + + count = simple_strtoul(argv[3], NULL, 16); + + if (count == 0) { + puts ("Zero length ???\n"); + return 1; + } + +#ifndef CFG_NO_FLASH + /* check if we are copying to Flash */ + if ( (addr2info(dest) != NULL) +#ifdef CONFIG_HAS_DATAFLASH + && (!addr_dataflash(addr)) +#endif + ) { + int rc; + + puts ("Copy to Flash... "); + + rc = flash_write ((char *)addr, dest, count*size); + if (rc != 0) { + flash_perror (rc); + return (1); + } + puts ("done\n"); + return 0; + } +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_MMC) + if (mmc2info(dest)) { + int rc; + + puts ("Copy to MMC... "); + switch (rc = mmc_write ((uchar *)addr, dest, count*size)) { + case 0: + putc ('\n'); + return 1; + case -1: + puts ("failed\n"); + return 1; + default: + printf ("%s[%d] FIXME: rc=%d\n",__FILE__,__LINE__,rc); + return 1; + } + puts ("done\n"); + return 0; + } + + if (mmc2info(addr)) { + int rc; + + puts ("Copy from MMC... "); + switch (rc = mmc_read (addr, (uchar *)dest, count*size)) { + case 0: + putc ('\n'); + return 1; + case -1: + puts ("failed\n"); + return 1; + default: + printf ("%s[%d] FIXME: rc=%d\n",__FILE__,__LINE__,rc); + return 1; + } + puts ("done\n"); + return 0; + } +#endif + +#ifdef CONFIG_HAS_DATAFLASH + /* Check if we are copying from RAM or Flash to DataFlash */ + if (addr_dataflash(dest) && !addr_dataflash(addr)){ + int rc; + + puts ("Copy to DataFlash... "); + + rc = write_dataflash (dest, addr, count*size); + + if (rc != 1) { + dataflash_perror (rc); + return (1); + } + puts ("done\n"); + return 0; + } + + /* Check if we are copying from DataFlash to RAM */ + if (addr_dataflash(addr) && !addr_dataflash(dest) && (addr2info(dest)==NULL) ){ + int rc; + rc = read_dataflash(addr, count * size, (char *) dest); + if (rc != 1) { + dataflash_perror (rc); + return (1); + } + return 0; + } + + if (addr_dataflash(addr) && addr_dataflash(dest)){ + puts ("Unsupported combination of source/destination.\n\r"); + return 1; + } +#endif + + while (count-- > 0) { + if (size == 4) + *((ulong *)dest) = *((ulong *)addr); + else if (size == 2) + *((ushort *)dest) = *((ushort *)addr); + else + *((u_char *)dest) = *((u_char *)addr); + addr += size; + dest += size; + } + return 0; +} + +int do_mem_base (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc > 1) { + /* Set new base address. + */ + base_address = simple_strtoul(argv[1], NULL, 16); + } + /* Print the current base address. + */ + printf("Base Address: 0x%08lx\n", base_address); + return 0; +} + +int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, length, i, junk; + int size; + volatile uint *longp; + volatile ushort *shortp; + volatile u_char *cp; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Check for a size spefication. + * Defaults to long if no or incorrect specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 0) + return 1; + + /* Address is always specified. + */ + addr = simple_strtoul(argv[1], NULL, 16); + + /* Length is the number of objects, not number of bytes. + */ + length = simple_strtoul(argv[2], NULL, 16); + + /* We want to optimize the loops to run as fast as possible. + * If we have only one object, just run infinite loops. + */ + if (length == 1) { + if (size == 4) { + longp = (uint *)addr; + for (;;) + i = *longp; + } + if (size == 2) { + shortp = (ushort *)addr; + for (;;) + i = *shortp; + } + cp = (u_char *)addr; + for (;;) + i = *cp; + } + + if (size == 4) { + for (;;) { + longp = (uint *)addr; + i = length; + while (i-- > 0) + junk = *longp++; + } + } + if (size == 2) { + for (;;) { + shortp = (ushort *)addr; + i = length; + while (i-- > 0) + junk = *shortp++; + } + } + for (;;) { + cp = (u_char *)addr; + i = length; + while (i-- > 0) + junk = *cp++; + } +} + +#ifdef CONFIG_LOOPW +int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, length, i, data; + int size; + volatile uint *longp; + volatile ushort *shortp; + volatile u_char *cp; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Check for a size spefication. + * Defaults to long if no or incorrect specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 0) + return 1; + + /* Address is always specified. + */ + addr = simple_strtoul(argv[1], NULL, 16); + + /* Length is the number of objects, not number of bytes. + */ + length = simple_strtoul(argv[2], NULL, 16); + + /* data to write */ + data = simple_strtoul(argv[3], NULL, 16); + + /* We want to optimize the loops to run as fast as possible. + * If we have only one object, just run infinite loops. + */ + if (length == 1) { + if (size == 4) { + longp = (uint *)addr; + for (;;) + *longp = data; + } + if (size == 2) { + shortp = (ushort *)addr; + for (;;) + *shortp = data; + } + cp = (u_char *)addr; + for (;;) + *cp = data; + } + + if (size == 4) { + for (;;) { + longp = (uint *)addr; + i = length; + while (i-- > 0) + *longp++ = data; + } + } + if (size == 2) { + for (;;) { + shortp = (ushort *)addr; + i = length; + while (i-- > 0) + *shortp++ = data; + } + } + for (;;) { + cp = (u_char *)addr; + i = length; + while (i-- > 0) + *cp++ = data; + } +} +#endif /* CONFIG_LOOPW */ + +/* + * Perform a memory test. A more complete alternative test can be + * configured using CFG_ALT_MEMTEST. The complete test loops until + * interrupted by ctrl-c or by a failure of one of the sub-tests. + */ +int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + vu_long *addr, *start, *end; + ulong val; + ulong readback; + +#if defined(CFG_ALT_MEMTEST) + vu_long addr_mask; + vu_long offset; + vu_long test_offset; + vu_long pattern; + vu_long temp; + vu_long anti_pattern; + vu_long num_words; +#if defined(CFG_MEMTEST_SCRATCH) + vu_long *dummy = (vu_long*)CFG_MEMTEST_SCRATCH; +#else + vu_long *dummy = NULL; +#endif + int j; + int iterations = 1; + + static const ulong bitpattern[] = { + 0x00000001, /* single bit */ + 0x00000003, /* two adjacent bits */ + 0x00000007, /* three adjacent bits */ + 0x0000000F, /* four adjacent bits */ + 0x00000005, /* two non-adjacent bits */ + 0x00000015, /* three non-adjacent bits */ + 0x00000055, /* four non-adjacent bits */ + 0xaaaaaaaa, /* alternating 1/0 */ + }; +#else + ulong incr; + ulong pattern; + int rcode = 0; +#endif + + if (argc > 1) { + start = (ulong *)simple_strtoul(argv[1], NULL, 16); + } else { + start = (ulong *)CFG_MEMTEST_START; + } + + if (argc > 2) { + end = (ulong *)simple_strtoul(argv[2], NULL, 16); + } else { + end = (ulong *)(CFG_MEMTEST_END); + } + + if (argc > 3) { + pattern = (ulong)simple_strtoul(argv[3], NULL, 16); + } else { + pattern = 0; + } + +#if defined(CFG_ALT_MEMTEST) + printf ("Testing %08x ... %08x:\n", (uint)start, (uint)end); + PRINTF("%s:%d: start 0x%p end 0x%p\n", + __FUNCTION__, __LINE__, start, end); + + for (;;) { + if (ctrlc()) { + putc ('\n'); + return 1; + } + + printf("Iteration: %6d\r", iterations); + PRINTF("Iteration: %6d\n", iterations); + iterations++; + + /* + * Data line test: write a pattern to the first + * location, write the 1's complement to a 'parking' + * address (changes the state of the data bus so a + * floating bus doen't give a false OK), and then + * read the value back. Note that we read it back + * into a variable because the next time we read it, + * it might be right (been there, tough to explain to + * the quality guys why it prints a failure when the + * "is" and "should be" are obviously the same in the + * error message). + * + * Rather than exhaustively testing, we test some + * patterns by shifting '1' bits through a field of + * '0's and '0' bits through a field of '1's (i.e. + * pattern and ~pattern). + */ + addr = start; + for (j = 0; j < sizeof(bitpattern)/sizeof(bitpattern[0]); j++) { + val = bitpattern[j]; + for(; val != 0; val <<= 1) { + *addr = val; + *dummy = ~val; /* clear the test data off of the bus */ + readback = *addr; + if(readback != val) { + printf ("FAILURE (data line): " + "expected %08lx, actual %08lx\n", + val, readback); + } + *addr = ~val; + *dummy = val; + readback = *addr; + if(readback != ~val) { + printf ("FAILURE (data line): " + "Is %08lx, should be %08lx\n", + readback, ~val); + } + } + } + + /* + * Based on code whose Original Author and Copyright + * information follows: Copyright (c) 1998 by Michael + * Barr. This software is placed into the public + * domain and may be used for any purpose. However, + * this notice must not be changed or removed and no + * warranty is either expressed or implied by its + * publication or distribution. + */ + + /* + * Address line test + * + * Description: Test the address bus wiring in a + * memory region by performing a walking + * 1's test on the relevant bits of the + * address and checking for aliasing. + * This test will find single-bit + * address failures such as stuck -high, + * stuck-low, and shorted pins. The base + * address and size of the region are + * selected by the caller. + * + * Notes: For best results, the selected base + * address should have enough LSB 0's to + * guarantee single address bit changes. + * For example, to test a 64-Kbyte + * region, select a base address on a + * 64-Kbyte boundary. Also, select the + * region size as a power-of-two if at + * all possible. + * + * Returns: 0 if the test succeeds, 1 if the test fails. + * + * ## NOTE ## Be sure to specify start and end + * addresses such that addr_mask has + * lots of bits set. For example an + * address range of 01000000 02000000 is + * bad while a range of 01000000 + * 01ffffff is perfect. + */ + addr_mask = ((ulong)end - (ulong)start)/sizeof(vu_long); + pattern = (vu_long) 0xaaaaaaaa; + anti_pattern = (vu_long) 0x55555555; + + PRINTF("%s:%d: addr mask = 0x%.8lx\n", + __FUNCTION__, __LINE__, + addr_mask); + /* + * Write the default pattern at each of the + * power-of-two offsets. + */ + for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) { + start[offset] = pattern; + } + + /* + * Check for address bits stuck high. + */ + test_offset = 0; + start[test_offset] = anti_pattern; + + for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) { + temp = start[offset]; + if (temp != pattern) { + printf ("\nFAILURE: Address bit stuck high @ 0x%.8lx:" + " expected 0x%.8lx, actual 0x%.8lx\n", + (ulong)&start[offset], pattern, temp); + return 1; + } + } + start[test_offset] = pattern; + + /* + * Check for addr bits stuck low or shorted. + */ + for (test_offset = 1; (test_offset & addr_mask) != 0; test_offset <<= 1) { + start[test_offset] = anti_pattern; + + for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) { + temp = start[offset]; + if ((temp != pattern) && (offset != test_offset)) { + printf ("\nFAILURE: Address bit stuck low or shorted @" + " 0x%.8lx: expected 0x%.8lx, actual 0x%.8lx\n", + (ulong)&start[offset], pattern, temp); + return 1; + } + } + start[test_offset] = pattern; + } + + /* + * Description: Test the integrity of a physical + * memory device by performing an + * increment/decrement test over the + * entire region. In the process every + * storage bit in the device is tested + * as a zero and a one. The base address + * and the size of the region are + * selected by the caller. + * + * Returns: 0 if the test succeeds, 1 if the test fails. + */ + num_words = ((ulong)end - (ulong)start)/sizeof(vu_long) + 1; + + /* + * Fill memory with a known pattern. + */ + for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) { + start[offset] = pattern; + } + + /* + * Check each location and invert it for the second pass. + */ + for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) { + temp = start[offset]; + if (temp != pattern) { + printf ("\nFAILURE (read/write) @ 0x%.8lx:" + " expected 0x%.8lx, actual 0x%.8lx)\n", + (ulong)&start[offset], pattern, temp); + return 1; + } + + anti_pattern = ~pattern; + start[offset] = anti_pattern; + } + + /* + * Check each location for the inverted pattern and zero it. + */ + for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) { + anti_pattern = ~pattern; + temp = start[offset]; + if (temp != anti_pattern) { + printf ("\nFAILURE (read/write): @ 0x%.8lx:" + " expected 0x%.8lx, actual 0x%.8lx)\n", + (ulong)&start[offset], anti_pattern, temp); + return 1; + } + start[offset] = 0; + } + } + +#else /* The original, quickie test */ + incr = 1; + for (;;) { + if (ctrlc()) { + putc ('\n'); + return 1; + } + + printf ("\rPattern %08lX Writing..." + "%12s" + "\b\b\b\b\b\b\b\b\b\b", + pattern, ""); + + for (addr=start,val=pattern; addrusage); + return 1; + } + +#ifdef CONFIG_BOOT_RETRY_TIME + reset_cmd_timeout(); /* got a good command to get here */ +#endif + /* We use the last specified parameters, unless new ones are + * entered. + */ + addr = mm_last_addr; + size = mm_last_size; + + if ((flag & CMD_FLAG_REPEAT) == 0) { + /* New command specified. Check for a size specification. + * Defaults to long if no or incorrect specification. + */ + if ((size = cmd_get_data_size(argv[0], 4)) < 0) + return 1; + + /* Address is specified since argc > 1 + */ + addr = simple_strtoul(argv[1], NULL, 16); + addr += base_address; + } + +#ifdef CONFIG_HAS_DATAFLASH + if (addr_dataflash(addr)){ + puts ("Can't modify DataFlash in place. Use cp instead.\n\r"); + return 0; + } +#endif + + /* Print the address, followed by value. Then accept input for + * the next value. A non-converted value exits. + */ + do { + printf("%08lx:", addr); + if (size == 4) + printf(" %08x", *((uint *)addr)); + else if (size == 2) + printf(" %04x", *((ushort *)addr)); + else + printf(" %02x", *((u_char *)addr)); + + nbytes = readline (" ? "); + if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { + /* pressed as only input, don't modify current + * location and move to next. "-" pressed will go back. + */ + if (incrflag) + addr += nbytes ? -size : size; + nbytes = 1; +#ifdef CONFIG_BOOT_RETRY_TIME + reset_cmd_timeout(); /* good enough to not time out */ +#endif + } +#ifdef CONFIG_BOOT_RETRY_TIME + else if (nbytes == -2) { + break; /* timed out, exit the command */ + } +#endif + else { + char *endp; + i = simple_strtoul(console_buffer, &endp, 16); + nbytes = endp - console_buffer; + if (nbytes) { +#ifdef CONFIG_BOOT_RETRY_TIME + /* good enough to not time out + */ + reset_cmd_timeout(); +#endif + if (size == 4) + *((uint *)addr) = i; + else if (size == 2) + *((ushort *)addr) = i; + else + *((u_char *)addr) = i; + if (incrflag) + addr += size; + } + } + } while (nbytes); + + mm_last_addr = addr; + mm_last_size = size; + return 0; +} + +#ifndef CONFIG_CRC32_VERIFY + +int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, length; + ulong crc; + ulong *ptr; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + addr = simple_strtoul (argv[1], NULL, 16); + addr += base_address; + + length = simple_strtoul (argv[2], NULL, 16); + + crc = crc32 (0, (const uchar *) addr, length); + + printf ("CRC32 for %08lx ... %08lx ==> %08lx\n", + addr, addr + length - 1, crc); + + if (argc > 3) { + ptr = (ulong *) simple_strtoul (argv[3], NULL, 16); + *ptr = crc; + } + + return 0; +} + +#else /* CONFIG_CRC32_VERIFY */ + +int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr, length; + ulong crc; + ulong *ptr; + ulong vcrc; + int verify; + int ac; + char **av; + + if (argc < 3) { + usage: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + av = argv + 1; + ac = argc - 1; + if (strcmp(*av, "-v") == 0) { + verify = 1; + av++; + ac--; + if (ac < 3) + goto usage; + } else + verify = 0; + + addr = simple_strtoul(*av++, NULL, 16); + addr += base_address; + length = simple_strtoul(*av++, NULL, 16); + + crc = crc32(0, (const uchar *) addr, length); + + if (!verify) { + printf ("CRC32 for %08lx ... %08lx ==> %08lx\n", + addr, addr + length - 1, crc); + if (ac > 2) { + ptr = (ulong *) simple_strtoul (*av++, NULL, 16); + *ptr = crc; + } + } else { + vcrc = simple_strtoul(*av++, NULL, 16); + if (vcrc != crc) { + printf ("CRC32 for %08lx ... %08lx ==> %08lx != %08lx ** ERROR **\n", + addr, addr + length - 1, crc, vcrc); + return 1; + } + } + + return 0; + +} +#endif /* CONFIG_CRC32_VERIFY */ + +/**************************************************/ +#if (CONFIG_COMMANDS & CFG_CMD_MEMORY) +U_BOOT_CMD( + md, 3, 1, do_mem_md, + "md - memory display\n", + "[.b, .w, .l] address [# of objects]\n - memory display\n" +); + + +U_BOOT_CMD( + mm, 2, 1, do_mem_mm, + "mm - memory modify (auto-incrementing)\n", + "[.b, .w, .l] address\n" " - memory modify, auto increment address\n" +); + + +U_BOOT_CMD( + nm, 2, 1, do_mem_nm, + "nm - memory modify (constant address)\n", + "[.b, .w, .l] address\n - memory modify, read and keep address\n" +); + +U_BOOT_CMD( + mw, 4, 1, do_mem_mw, + "mw - memory write (fill)\n", + "[.b, .w, .l] address value [count]\n - write memory\n" +); + +U_BOOT_CMD( + cp, 4, 1, do_mem_cp, + "cp - memory copy\n", + "[.b, .w, .l] source target count\n - copy memory\n" +); + +U_BOOT_CMD( + cmp, 4, 1, do_mem_cmp, + "cmp - memory compare\n", + "[.b, .w, .l] addr1 addr2 count\n - compare memory\n" +); + +#ifndef CONFIG_CRC32_VERIFY + +U_BOOT_CMD( + crc32, 4, 1, do_mem_crc, + "crc32 - checksum calculation\n", + "address count [addr]\n - compute CRC32 checksum [save at addr]\n" +); + +#else /* CONFIG_CRC32_VERIFY */ + +U_BOOT_CMD( + crc32, 5, 1, do_mem_crc, + "crc32 - checksum calculation\n", + "address count [addr]\n - compute CRC32 checksum [save at addr]\n" + "-v address count crc\n - verify crc of memory area\n" +); + +#endif /* CONFIG_CRC32_VERIFY */ + +U_BOOT_CMD( + base, 2, 1, do_mem_base, + "base - print or set address offset\n", + "\n - print address offset for memory commands\n" + "base off\n - set address offset for memory commands to 'off'\n" +); + +U_BOOT_CMD( + loop, 3, 1, do_mem_loop, + "loop - infinite loop on address range\n", + "[.b, .w, .l] address number_of_objects\n" + " - loop on a set of addresses\n" +); + +#ifdef CONFIG_LOOPW +U_BOOT_CMD( + loopw, 4, 1, do_mem_loopw, + "loopw - infinite write loop on address range\n", + "[.b, .w, .l] address number_of_objects data_to_write\n" + " - loop on a set of addresses\n" +); +#endif /* CONFIG_LOOPW */ + +U_BOOT_CMD( + mtest, 4, 1, do_mem_mtest, + "mtest - simple RAM test\n", + "[start [end [pattern]]]\n" + " - simple RAM read/write test\n" +); + +#ifdef CONFIG_MX_CYCLIC +U_BOOT_CMD( + mdc, 4, 1, do_mem_mdc, + "mdc - memory display cyclic\n", + "[.b, .w, .l] address count delay(ms)\n - memory display cyclic\n" +); + +U_BOOT_CMD( + mwc, 4, 1, do_mem_mwc, + "mwc - memory write cyclic\n", + "[.b, .w, .l] address value delay(ms)\n - memory write cyclic\n" +); +#endif /* CONFIG_MX_CYCLIC */ + +#endif +#endif /* CFG_CMD_MEMORY */ diff --git a/common/cmd_mii.c b/common/cmd_mii.c new file mode 100644 index 0000000..48a4e77 --- /dev/null +++ b/common/cmd_mii.c @@ -0,0 +1,597 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MII Utilities + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_MII) +#include + +#ifdef CONFIG_TERSE_MII +/* + * Display values from last command. + */ +uint last_op; +uint last_addr; +uint last_data; +uint last_reg; + +/* + * MII device/info/read/write + * + * Syntax: + * mii device {devname} + * mii info {addr} + * mii read {addr} {reg} + * mii write {addr} {reg} {data} + */ +int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char op; + unsigned char addr, reg; + unsigned short data; + int rcode = 0; + char *devname; + +#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2) + mii_init (); +#endif + + /* + * We use the last specified parameters, unless new ones are + * entered. + */ + op = last_op; + addr = last_addr; + data = last_data; + reg = last_reg; + + if ((flag & CMD_FLAG_REPEAT) == 0) { + op = argv[1][0]; + if (argc >= 3) + addr = simple_strtoul (argv[2], NULL, 16); + if (argc >= 4) + reg = simple_strtoul (argv[3], NULL, 16); + if (argc >= 5) + data = simple_strtoul (argv[4], NULL, 16); + } + + /* use current device */ + devname = miiphy_get_current_dev(); + + /* + * check device/read/write/list. + */ + if (op == 'i') { + unsigned char j, start, end; + unsigned int oui; + unsigned char model; + unsigned char rev; + + /* + * Look for any and all PHYs. Valid addresses are 0..31. + */ + if (argc >= 3) { + start = addr; end = addr + 1; + } else { + start = 0; end = 31; + } + + for (j = start; j < end; j++) { + if (miiphy_info (devname, j, &oui, &model, &rev) == 0) { + printf ("PHY 0x%02X: " + "OUI = 0x%04X, " + "Model = 0x%02X, " + "Rev = 0x%02X, " + "%3dbaseT, %s\n", + j, oui, model, rev, + miiphy_speed (devname, j), + (miiphy_duplex (devname, j) == FULL) + ? "FDX" : "HDX"); + } else { + puts ("Error reading info from the PHY\n"); + } + } + } else if (op == 'r') { + if (miiphy_read (devname, addr, reg, &data) != 0) { + puts ("Error reading from the PHY\n"); + rcode = 1; + } else { + printf ("%04X\n", data & 0x0000FFFF); + } + } else if (op == 'w') { + if (miiphy_write (devname, addr, reg, data) != 0) { + puts ("Error writing to the PHY\n"); + rcode = 1; + } + } else if (op == 'd') { + if (argc == 2) + miiphy_listdev (); + else + miiphy_set_current_dev (argv[2]); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* + * Save the parameters for repeats. + */ + last_op = op; + last_addr = addr; + last_data = data; + last_reg = reg; + + return rcode; +} + +/***************************************************/ + +U_BOOT_CMD( + mii, 5, 1, do_mii, + "mii - MII utility commands\n", + "device - list available devices\n" + "mii device - set current device\n" + "mii info - display MII PHY info\n" + "mii read - read MII PHY register \n" + "mii write - write MII PHY register \n" +); + +#else /* ! CONFIG_TERSE_MII ================================================= */ + +typedef struct _MII_reg_desc_t { + ushort regno; + char * name; +} MII_reg_desc_t; + +MII_reg_desc_t reg_0_5_desc_tbl[] = { + { 0, "PHY control register" }, + { 1, "PHY status register" }, + { 2, "PHY ID 1 register" }, + { 3, "PHY ID 2 register" }, + { 4, "Autonegotiation advertisement register" }, + { 5, "Autonegotiation partner abilities register" }, +}; + +typedef struct _MII_field_desc_t { + ushort hi; + ushort lo; + ushort mask; + char * name; +} MII_field_desc_t; + +MII_field_desc_t reg_0_desc_tbl[] = { + { 15, 15, 0x01, "reset" }, + { 14, 14, 0x01, "loopback" }, + { 13, 6, 0x81, "speed selection" }, /* special */ + { 12, 12, 0x01, "A/N enable" }, + { 11, 11, 0x01, "power-down" }, + { 10, 10, 0x01, "isolate" }, + { 9, 9, 0x01, "restart A/N" }, + { 8, 8, 0x01, "duplex" }, /* special */ + { 7, 7, 0x01, "collision test enable" }, + { 5, 0, 0x3f, "(reserved)" } +}; + +MII_field_desc_t reg_1_desc_tbl[] = { + { 15, 15, 0x01, "100BASE-T4 able" }, + { 14, 14, 0x01, "100BASE-X full duplex able" }, + { 13, 13, 0x01, "100BASE-X half duplex able" }, + { 12, 12, 0x01, "10 Mbps full duplex able" }, + { 11, 11, 0x01, "10 Mbps half duplex able" }, + { 10, 10, 0x01, "100BASE-T2 full duplex able" }, + { 9, 9, 0x01, "100BASE-T2 half duplex able" }, + { 8, 8, 0x01, "extended status" }, + { 7, 7, 0x01, "(reserved)" }, + { 6, 6, 0x01, "MF preamble suppression" }, + { 5, 5, 0x01, "A/N complete" }, + { 4, 4, 0x01, "remote fault" }, + { 3, 3, 0x01, "A/N able" }, + { 2, 2, 0x01, "link status" }, + { 1, 1, 0x01, "jabber detect" }, + { 0, 0, 0x01, "extended capabilities" }, +}; + +MII_field_desc_t reg_2_desc_tbl[] = { + { 15, 0, 0xffff, "OUI portion" }, +}; + +MII_field_desc_t reg_3_desc_tbl[] = { + { 15, 10, 0x3f, "OUI portion" }, + { 9, 4, 0x3f, "manufacturer part number" }, + { 3, 0, 0x0f, "manufacturer rev. number" }, +}; + +MII_field_desc_t reg_4_desc_tbl[] = { + { 15, 15, 0x01, "next page able" }, + { 14, 14, 0x01, "reserved" }, + { 13, 13, 0x01, "remote fault" }, + { 12, 12, 0x01, "reserved" }, + { 11, 11, 0x01, "asymmetric pause" }, + { 10, 10, 0x01, "pause enable" }, + { 9, 9, 0x01, "100BASE-T4 able" }, + { 8, 8, 0x01, "100BASE-TX full duplex able" }, + { 7, 7, 0x01, "100BASE-TX able" }, + { 6, 6, 0x01, "10BASE-T full duplex able" }, + { 5, 5, 0x01, "10BASE-T able" }, + { 4, 0, 0x1f, "xxx to do" }, +}; + +MII_field_desc_t reg_5_desc_tbl[] = { + { 15, 15, 0x01, "next page able" }, + { 14, 14, 0x01, "acknowledge" }, + { 13, 13, 0x01, "remote fault" }, + { 12, 12, 0x01, "(reserved)" }, + { 11, 11, 0x01, "asymmetric pause able" }, + { 10, 10, 0x01, "pause able" }, + { 9, 9, 0x01, "100BASE-T4 able" }, + { 8, 8, 0x01, "100BASE-X full duplex able" }, + { 7, 7, 0x01, "100BASE-TX able" }, + { 6, 6, 0x01, "10BASE-T full duplex able" }, + { 5, 5, 0x01, "10BASE-T able" }, + { 4, 0, 0x1f, "xxx to do" }, +}; + +#define DESC0LEN (sizeof(reg_0_desc_tbl)/sizeof(reg_0_desc_tbl[0])) +#define DESC1LEN (sizeof(reg_1_desc_tbl)/sizeof(reg_1_desc_tbl[0])) +#define DESC2LEN (sizeof(reg_2_desc_tbl)/sizeof(reg_2_desc_tbl[0])) +#define DESC3LEN (sizeof(reg_3_desc_tbl)/sizeof(reg_3_desc_tbl[0])) +#define DESC4LEN (sizeof(reg_4_desc_tbl)/sizeof(reg_4_desc_tbl[0])) +#define DESC5LEN (sizeof(reg_5_desc_tbl)/sizeof(reg_5_desc_tbl[0])) + +typedef struct _MII_field_desc_and_len_t { + MII_field_desc_t * pdesc; + ushort len; +} MII_field_desc_and_len_t; + +MII_field_desc_and_len_t desc_and_len_tbl[] = { + { reg_0_desc_tbl, DESC0LEN }, + { reg_1_desc_tbl, DESC1LEN }, + { reg_2_desc_tbl, DESC2LEN }, + { reg_3_desc_tbl, DESC3LEN }, + { reg_4_desc_tbl, DESC4LEN }, + { reg_5_desc_tbl, DESC5LEN }, +}; + +static void dump_reg( + ushort regval, + MII_reg_desc_t * prd, + MII_field_desc_and_len_t * pdl); + +static int special_field( + ushort regno, + MII_field_desc_t * pdesc, + ushort regval); + +void MII_dump_0_to_5( + ushort regvals[6], + uchar reglo, + uchar reghi) +{ + ulong i; + + for (i = 0; i < 6; i++) { + if ((reglo <= i) && (i <= reghi)) + dump_reg(regvals[i], ®_0_5_desc_tbl[i], + &desc_and_len_tbl[i]); + } +} + +static void dump_reg( + ushort regval, + MII_reg_desc_t * prd, + MII_field_desc_and_len_t * pdl) +{ + ulong i; + ushort mask_in_place; + MII_field_desc_t * pdesc; + + printf("%u. (%04hx) -- %s --\n", + prd->regno, regval, prd->name); + + for (i = 0; i < pdl->len; i++) { + pdesc = &pdl->pdesc[i]; + + mask_in_place = pdesc->mask << pdesc->lo; + + printf(" (%04hx:%04hx) %u.", + mask_in_place, + regval & mask_in_place, + prd->regno); + + if (special_field(prd->regno, pdesc, regval)) { + } + else { + if (pdesc->hi == pdesc->lo) + printf("%2u ", pdesc->lo); + else + printf("%2u-%2u", pdesc->hi, pdesc->lo); + printf(" = %5u %s", + (regval & mask_in_place) >> pdesc->lo, + pdesc->name); + } + printf("\n"); + + } + printf("\n"); +} + +/* Special fields: +** 0.6,13 +** 0.8 +** 2.15-0 +** 3.15-0 +** 4.4-0 +** 5.4-0 +*/ + +static int special_field( + ushort regno, + MII_field_desc_t * pdesc, + ushort regval) +{ + if ((regno == 0) && (pdesc->lo == 6)) { + ushort speed_bits = regval & PHY_BMCR_SPEED_MASK; + printf("%2u,%2u = b%u%u speed selection = %s Mbps", + 6, 13, + (regval >> 6) & 1, + (regval >> 13) & 1, + speed_bits == PHY_BMCR_1000_MBPS ? "1000" : + speed_bits == PHY_BMCR_100_MBPS ? "100" : + speed_bits == PHY_BMCR_10_MBPS ? "10" : + "???"); + return 1; + } + + else if ((regno == 0) && (pdesc->lo == 8)) { + printf("%2u = %5u duplex = %s", + pdesc->lo, + (regval >> pdesc->lo) & 1, + ((regval >> pdesc->lo) & 1) ? "full" : "half"); + return 1; + } + + else if ((regno == 4) && (pdesc->lo == 0)) { + ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; + printf("%2u-%2u = %5u selector = %s", + pdesc->hi, pdesc->lo, sel_bits, + sel_bits == PHY_ANLPAR_PSB_802_3 ? + "IEEE 802.3" : + sel_bits == PHY_ANLPAR_PSB_802_9 ? + "IEEE 802.9 ISLAN-16T" : + "???"); + return 1; + } + + else if ((regno == 5) && (pdesc->lo == 0)) { + ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; + printf("%2u-%2u = %u selector = %s", + pdesc->hi, pdesc->lo, sel_bits, + sel_bits == PHY_ANLPAR_PSB_802_3 ? + "IEEE 802.3" : + sel_bits == PHY_ANLPAR_PSB_802_9 ? + "IEEE 802.9 ISLAN-16T" : + "???"); + return 1; + } + + return 0; +} + +char last_op[2]; +uint last_data; +uint last_addr_lo; +uint last_addr_hi; +uint last_reg_lo; +uint last_reg_hi; + +static void extract_range( + char * input, + unsigned char * plo, + unsigned char * phi) +{ + char * end; + *plo = simple_strtoul(input, &end, 16); + if (*end == '-') { + end++; + *phi = simple_strtoul(end, NULL, 16); + } + else { + *phi = *plo; + } +} + +/* ---------------------------------------------------------------- */ +int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char op[2]; + unsigned char addrlo, addrhi, reglo, reghi; + unsigned char addr, reg; + unsigned short data; + int rcode = 0; + char *devname; + +#ifdef CONFIG_8xx + mii_init (); +#endif + + /* + * We use the last specified parameters, unless new ones are + * entered. + */ + op[0] = last_op[0]; + op[1] = last_op[1]; + addrlo = last_addr_lo; + addrhi = last_addr_hi; + reglo = last_reg_lo; + reghi = last_reg_hi; + data = last_data; + + if ((flag & CMD_FLAG_REPEAT) == 0) { + op[0] = argv[1][0]; + if (strlen(argv[1]) > 1) + op[1] = argv[1][1]; + else + op[1] = '\0'; + + if (argc >= 3) + extract_range(argv[2], &addrlo, &addrhi); + if (argc >= 4) + extract_range(argv[3], ®lo, ®hi); + if (argc >= 5) + data = simple_strtoul (argv[4], NULL, 16); + } + + /* use current device */ + devname = miiphy_get_current_dev(); + + /* + * check info/read/write. + */ + if (op[0] == 'i') { + unsigned char j, start, end; + unsigned int oui; + unsigned char model; + unsigned char rev; + + /* + * Look for any and all PHYs. Valid addresses are 0..31. + */ + if (argc >= 3) { + start = addrlo; end = addrhi; + } else { + start = 0; end = 31; + } + + for (j = start; j <= end; j++) { + if (miiphy_info (devname, j, &oui, &model, &rev) == 0) { + printf("PHY 0x%02X: " + "OUI = 0x%04X, " + "Model = 0x%02X, " + "Rev = 0x%02X, " + "%3dbaseT, %s\n", + j, oui, model, rev, + miiphy_speed (devname, j), + (miiphy_duplex (devname, j) == FULL) + ? "FDX" : "HDX"); + } else { + puts ("Error reading info from the PHY\n"); + } + } + } else if (op[0] == 'r') { + for (addr = addrlo; addr <= addrhi; addr++) { + for (reg = reglo; reg <= reghi; reg++) { + data = 0xffff; + if (miiphy_read (devname, addr, reg, &data) != 0) { + printf( + "Error reading from the PHY addr=%02x reg=%02x\n", + addr, reg); + rcode = 1; + } else { + if ((addrlo != addrhi) || (reglo != reghi)) + printf("addr=%02x reg=%02x data=", + (uint)addr, (uint)reg); + printf("%04X\n", data & 0x0000FFFF); + } + } + if ((addrlo != addrhi) && (reglo != reghi)) + printf("\n"); + } + } else if (op[0] == 'w') { + for (addr = addrlo; addr <= addrhi; addr++) { + for (reg = reglo; reg <= reghi; reg++) { + if (miiphy_write (devname, addr, reg, data) != 0) { + printf("Error writing to the PHY addr=%02x reg=%02x\n", + addr, reg); + rcode = 1; + } + } + } + } else if (strncmp(op, "du", 2) == 0) { + ushort regs[6]; + int ok = 1; + if ((reglo > 5) || (reghi > 5)) { + printf( + "The MII dump command only formats the " + "standard MII registers, 0-5.\n"); + return 1; + } + for (addr = addrlo; addr <= addrhi; addr++) { + for (reg = reglo; reg < reghi + 1; reg++) { + if (miiphy_read(devname, addr, reg, ®s[reg]) != 0) { + ok = 0; + printf( + "Error reading from the PHY addr=%02x reg=%02x\n", + addr, reg); + rcode = 1; + } + } + if (ok) + MII_dump_0_to_5(regs, reglo, reghi); + printf("\n"); + } + } else if (strncmp(op, "de", 2) == 0) { + if (argc == 2) + miiphy_listdev (); + else + miiphy_set_current_dev (argv[2]); + } else { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* + * Save the parameters for repeats. + */ + last_op[0] = op[0]; + last_op[1] = op[1]; + last_addr_lo = addrlo; + last_addr_hi = addrhi; + last_reg_lo = reglo; + last_reg_hi = reghi; + last_data = data; + + return rcode; +} + +/***************************************************/ + +U_BOOT_CMD( + mii, 5, 1, do_mii, + "mii - MII utility commands\n", + "device - list available devices\n" + "mii device - set current device\n" + "mii info - display MII PHY info\n" + "mii read - read MII PHY register \n" + "mii write - write MII PHY register \n" + "mii dump - pretty-print (0-5 only)\n" + "Addr and/or reg may be ranges, e.g. 2-7.\n" +); + +#endif /* CONFIG_TERSE_MII */ + +#endif /* CFG_CMD_MII */ diff --git a/common/cmd_misc.c b/common/cmd_misc.c new file mode 100644 index 0000000..67ee9e8 --- /dev/null +++ b/common/cmd_misc.c @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Misc functions + */ +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_MISC) + +int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong start = get_timer(0); + ulong delay; + + if (argc != 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + delay = simple_strtoul(argv[1], NULL, 10) * CFG_HZ; + + while (get_timer(start) < delay) { + if (ctrlc ()) { + return (-1); + } + udelay (100); + } + + return 0; +} + +/* Implemented in $(CPU)/interrupts.c */ +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +U_BOOT_CMD( + irqinfo, 1, 1, do_irqinfo, + "irqinfo - print information about IRQs\n", + NULL +); +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ + +U_BOOT_CMD( + sleep , 2, 2, do_sleep, + "sleep - delay execution for some time\n", + "N\n" + " - delay execution for N seconds (N is _decimal_ !!!)\n" +); + +#endif /* CFG_CMD_MISC */ diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c new file mode 100644 index 0000000..573eb97 --- /dev/null +++ b/common/cmd_mmc.c @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2003 + * Kyle Harris, kharris@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_MMC) + +#include + +int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (mmc_init (1) != 0) { + printf ("No MMC card found\n"); + return 1; + } + return 0; +} + +U_BOOT_CMD( + mmcinit, 1, 0, do_mmc, + "mmcinit - init mmc card\n", + NULL +); + +#endif /* CFG_CMD_MMC */ diff --git a/common/cmd_nand.c b/common/cmd_nand.c new file mode 100644 index 0000000..b0c01d1 --- /dev/null +++ b/common/cmd_nand.c @@ -0,0 +1,1898 @@ +/* + * Driver for NAND support, Rick Bronson + * borrowed heavily from: + * (c) 1999 Machine Vision Holdings, Inc. + * (c) 1999, 2000 David Woodhouse + * + * Added 16-bit nand support + * (C) 2004 Texas Instruments + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include +#include +#include + +#ifdef CONFIG_OMAP1510 +void archflashwp(void *archdata, int wp); +#endif + +#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) + +/* + * Definition of the out of band configuration structure + */ +struct nand_oob_config { + int ecc_pos[6]; /* position of ECC bytes inside oob */ + int badblock_pos; /* position of bad block flag inside oob -1 = inactive */ + int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */ +} oob_config = { {0}, 0, 0}; + +#undef NAND_DEBUG +#undef PSYCHO_DEBUG + +/* ****************** WARNING ********************* + * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will + * erase (or at least attempt to erase) blocks that are marked + * bad. This can be very handy if you are _sure_ that the block + * is OK, say because you marked a good block bad to test bad + * block handling and you are done testing, or if you have + * accidentally marked blocks bad. + * + * Erasing factory marked bad blocks is a _bad_ idea. If the + * erase succeeds there is no reliable way to find them again, + * and attempting to program or erase bad blocks can affect + * the data in _other_ (good) blocks. + */ +#define ALLOW_ERASE_BAD_DEBUG 0 + +#define CONFIG_MTD_NAND_ECC /* enable ECC */ +#define CONFIG_MTD_NAND_ECC_JFFS2 + +/* bits for nand_rw() `cmd'; or together as needed */ +#define NANDRW_READ 0x01 +#define NANDRW_WRITE 0x00 +#define NANDRW_JFFS2 0x02 +#define NANDRW_JFFS2_SKIP 0x04 + +/* + * Function Prototypes + */ +static void nand_print(struct nand_chip *nand); +int nand_rw (struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf); +int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); +static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, + size_t * retlen, u_char *buf, u_char *ecc_code); +static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * ecc_code); +static void nand_print_bad(struct nand_chip *nand); +static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, u_char * buf); +static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, const u_char * buf); +static int NanD_WaitReady(struct nand_chip *nand, int ale_wait); +#ifdef CONFIG_MTD_NAND_ECC +static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); +static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); +#endif + +struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}}; + +/* Current NAND Device */ +static int curr_device = -1; + +/* ------------------------------------------------------------------------- */ + +int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; + + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strcmp(argv[1],"info") == 0) { + int i; + + putc ('\n'); + + for (i=0; i= CFG_MAX_NAND_DEVICE)) { + puts ("\nno devices available\n"); + return 1; + } + printf ("\nDevice %d: ", curr_device); + nand_print(&nand_dev_desc[curr_device]); + return 0; + + } else if (strcmp(argv[1],"bad") == 0) { + if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { + puts ("\nno devices available\n"); + return 1; + } + printf ("\nDevice %d bad blocks:\n", curr_device); + nand_print_bad(&nand_dev_desc[curr_device]); + return 0; + + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strcmp(argv[1],"device") == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + + printf ("\nDevice %d: ", dev); + if (dev >= CFG_MAX_NAND_DEVICE) { + puts ("unknown device\n"); + return 1; + } + nand_print(&nand_dev_desc[dev]); + /*nand_print (dev);*/ + + if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { + return 1; + } + + curr_device = dev; + + puts ("... is now current device\n"); + + return 0; + } + else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) { + struct nand_chip* nand = &nand_dev_desc[curr_device]; + ulong off = 0; + ulong size = nand->totlen; + int ret; + + printf ("\nNAND erase: device %d offset %ld, size %ld ... ", + curr_device, off, size); + + ret = nand_erase (nand, off, size, 1); + + printf("%s\n", ret ? "ERROR" : "OK"); + + return ret; + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + /* at least 4 args */ + + if (strncmp(argv[1], "read", 4) == 0 || + strncmp(argv[1], "write", 5) == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong off = simple_strtoul(argv[3], NULL, 16); + ulong size = simple_strtoul(argv[4], NULL, 16); + int cmd = (strncmp(argv[1], "read", 4) == 0) ? + NANDRW_READ : NANDRW_WRITE; + int ret, total; + char* cmdtail = strchr(argv[1], '.'); + + if (cmdtail && !strncmp(cmdtail, ".oob", 2)) { + /* read out-of-band data */ + if (cmd & NANDRW_READ) { + ret = nand_read_oob(nand_dev_desc + curr_device, + off, size, (size_t *)&total, + (u_char*)addr); + } + else { + ret = nand_write_oob(nand_dev_desc + curr_device, + off, size, (size_t *)&total, + (u_char*)addr); + } + return ret; + } + else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2)) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ + else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) { + cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ + if (cmd & NANDRW_READ) + cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ + } +#ifdef SXNI855T + /* need ".e" same as ".j" for compatibility with older units */ + else if (cmdtail && !strcmp(cmdtail, ".e")) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ +#endif +#ifdef CFG_NAND_SKIP_BAD_DOT_I + /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ + /* ".i" for image -> read skips bad block (no 0xff) */ + else if (cmdtail && !strcmp(cmdtail, ".i")) { + cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ + if (cmd & NANDRW_READ) + cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ + } +#endif /* CFG_NAND_SKIP_BAD_DOT_I */ + else if (cmdtail) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + printf ("\nNAND %s: device %d offset %ld, size %ld ... ", + (cmd & NANDRW_READ) ? "read" : "write", + curr_device, off, size); + + ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size, + (size_t *)&total, (u_char*)addr); + + printf (" %d bytes %s: %s\n", total, + (cmd & NANDRW_READ) ? "read" : "written", + ret ? "ERROR" : "OK"); + + return ret; + } else if (strcmp(argv[1],"erase") == 0 && + (argc == 4 || strcmp("clean", argv[2]) == 0)) { + int clean = argc == 5; + ulong off = simple_strtoul(argv[2 + clean], NULL, 16); + ulong size = simple_strtoul(argv[3 + clean], NULL, 16); + int ret; + + printf ("\nNAND erase: device %d offset %ld, size %ld ... ", + curr_device, off, size); + + ret = nand_erase (nand_dev_desc + curr_device, off, size, clean); + + printf("%s\n", ret ? "ERROR" : "OK"); + + return ret; + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + rcode = 1; + } + + return rcode; + } +} + +U_BOOT_CMD( + nand, 5, 1, do_nand, + "nand - NAND sub-system\n", + "info - show available NAND devices\n" + "nand device [dev] - show or set current device\n" + "nand read[.jffs2[s]] addr off size\n" + "nand write[.jffs2] addr off size - read/write `size' bytes starting\n" + " at offset `off' to/from memory address `addr'\n" + "nand erase [clean] [off size] - erase `size' bytes from\n" + " offset `off' (entire device if not specified)\n" + "nand bad - show bad blocks\n" + "nand read.oob addr off size - read out-of-band data\n" + "nand write.oob addr off size - read out-of-band data\n" +); + +int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + char *ep; + int dev; + ulong cnt; + ulong addr; + ulong offset = 0; + image_header_t *hdr; + int rcode = 0; + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_device = getenv ("bootdevice"); + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = getenv ("bootdevice"); + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + case 4: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + offset = simple_strtoul(argv[3], NULL, 16); + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + if (!boot_device) { + puts ("\n** No boot device **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + dev = simple_strtoul(boot_device, &ep, 16); + + if ((dev >= CFG_MAX_NAND_DEVICE) || + (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) { + printf ("\n** Device %d not available\n", dev); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n", + dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR, + offset); + + if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset, + SECTORSIZE, NULL, (u_char *)addr)) { + printf ("** Read error on %d\n", dev); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + hdr = (image_header_t *)addr; + + if (ntohl(hdr->ih_magic) == IH_MAGIC) { + + print_image_hdr (hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); + cnt -= SECTORSIZE; + } else { + printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt, + NULL, (u_char *)(addr+SECTORSIZE))) { + printf ("** Read error on %d\n", dev); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + /* Loading ok, update default load address */ + + load_addr = addr; + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { + char *local_args[2]; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + + local_args[0] = argv[0]; + local_args[1] = NULL; + + printf ("Automatic boot of image at addr 0x%08lx ...\n", addr); + + do_bootm (cmdtp, 0, 1, local_args); + rcode = 1; + } + return rcode; +} + +U_BOOT_CMD( + nboot, 4, 1, do_nandboot, + "nboot - boot from NAND device\n", + "loadAddr dev\n" +); + +/* returns 0 if block containing pos is OK: + * valid erase block and + * not marked bad, or no bad mark position is specified + * returns 1 if marked bad or otherwise invalid + */ +int check_block (struct nand_chip *nand, unsigned long pos) +{ + size_t retlen; + uint8_t oob_data; + uint16_t oob_data16[6]; + int page0 = pos & (-nand->erasesize); + int page1 = page0 + nand->oobblock; + int badpos = oob_config.badblock_pos; + + if (pos >= nand->totlen) + return 1; + + if (badpos < 0) + return 0; /* no way to check, assume OK */ + + if (nand->bus16) { + if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16) + || (oob_data16[2] & 0xff00) != 0xff00) + return 1; + if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16) + || (oob_data16[2] & 0xff00) != 0xff00) + return 1; + } else { + /* Note - bad block marker can be on first or second page */ + if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data) + || oob_data != 0xff + || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data) + || oob_data != 0xff) + return 1; + } + + return 0; +} + +/* print bad blocks in NAND flash */ +static void nand_print_bad(struct nand_chip* nand) +{ + unsigned long pos; + + for (pos = 0; pos < nand->totlen; pos += nand->erasesize) { + if (check_block(nand, pos)) + printf(" 0x%8.8lx\n", pos); + } + puts("\n"); +} + +/* cmd: 0: NANDRW_WRITE write, fail on bad block + * 1: NANDRW_READ read, fail on bad block + * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks + * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks + * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks + */ +int nand_rw (struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf) +{ + int ret = 0, n, total = 0; + char eccbuf[6]; + /* eblk (once set) is the start of the erase block containing the + * data being processed. + */ + unsigned long eblk = ~0; /* force mismatch on first pass */ + unsigned long erasesize = nand->erasesize; + + while (len) { + if ((start & (-erasesize)) != eblk) { + /* have crossed into new erase block, deal with + * it if it is sure marked bad. + */ + eblk = start & (-erasesize); /* start of block */ + if (check_block(nand, eblk)) { + if (cmd == (NANDRW_READ | NANDRW_JFFS2)) { + while (len > 0 && + start - eblk < erasesize) { + *(buf++) = 0xff; + ++start; + ++total; + --len; + } + continue; + } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) { + start += erasesize; + continue; + } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) { + /* skip bad block */ + start += erasesize; + continue; + } else { + ret = 1; + break; + } + } + } + /* The ECC will not be calculated correctly if + less than 512 is written or read */ + /* Is request at least 512 bytes AND it starts on a proper boundry */ + if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200)) + printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n"); + + if (cmd & NANDRW_READ) { + ret = nand_read_ecc(nand, start, + min(len, eblk + erasesize - start), + (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); + } else { + ret = nand_write_ecc(nand, start, + min(len, eblk + erasesize - start), + (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); + } + + if (ret) + break; + + start += n; + buf += n; + total += n; + len -= n; + } + if (retlen) + *retlen = total; + + return ret; +} + +static void nand_print(struct nand_chip *nand) +{ + if (nand->numchips > 1) { + printf("%s at 0x%lx,\n" + "\t %d chips %s, size %d MB, \n" + "\t total size %ld MB, sector size %ld kB\n", + nand->name, nand->IO_ADDR, nand->numchips, + nand->chips_name, 1 << (nand->chipshift - 20), + nand->totlen >> 20, nand->erasesize >> 10); + } + else { + printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR); + print_size(nand->totlen, ", "); + print_size(nand->erasesize, " sector)\n"); + } +} + +/* ------------------------------------------------------------------------- */ + +static int NanD_WaitReady(struct nand_chip *nand, int ale_wait) +{ + /* This is inline, to optimise the common case, where it's ready instantly */ + int ret = 0; + +#ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */ + if(ale_wait) + NAND_WAIT_READY(nand); /* do the worst case 25us wait */ + else + udelay(10); +#else /* has functional r/b signal */ + NAND_WAIT_READY(nand); +#endif + return ret; +} + +/* NanD_Command: Send a flash command to the flash chip */ + +static inline int NanD_Command(struct nand_chip *nand, unsigned char command) +{ + unsigned long nandptr = nand->IO_ADDR; + + /* Assert the CLE (Command Latch Enable) line to the flash chip */ + NAND_CTL_SETCLE(nandptr); + + /* Send the command */ + WRITE_NAND_COMMAND(command, nandptr); + + /* Lower the CLE line */ + NAND_CTL_CLRCLE(nandptr); + +#ifdef NAND_NO_RB + if(command == NAND_CMD_RESET){ + u_char ret_val; + NanD_Command(nand, NAND_CMD_STATUS); + do { + ret_val = READ_NAND(nandptr);/* wait till ready */ + } while((ret_val & 0x40) != 0x40); + } +#endif + return NanD_WaitReady(nand, 0); +} + +/* NanD_Address: Set the current address for the flash chip */ + +static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs) +{ + unsigned long nandptr; + int i; + + nandptr = nand->IO_ADDR; + + /* Assert the ALE (Address Latch Enable) line to the flash chip */ + NAND_CTL_SETALE(nandptr); + + /* Send the address */ + /* Devices with 256-byte page are addressed as: + * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31) + * there is no device on the market with page256 + * and more than 24 bits. + * Devices with 512-byte page are addressed as: + * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31) + * 25-31 is sent only if the chip support it. + * bit 8 changes the read command to be sent + * (NAND_CMD_READ0 or NAND_CMD_READ1). + */ + + if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) + WRITE_NAND_ADDRESS(ofs, nandptr); + + ofs = ofs >> nand->page_shift; + + if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) { + for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) { + WRITE_NAND_ADDRESS(ofs, nandptr); + } + } + + /* Lower the ALE line */ + NAND_CTL_CLRALE(nandptr); + + /* Wait for the chip to respond */ + return NanD_WaitReady(nand, 1); +} + +/* NanD_SelectChip: Select a given flash chip within the current floor */ + +static inline int NanD_SelectChip(struct nand_chip *nand, int chip) +{ + /* Wait for it to be ready */ + return NanD_WaitReady(nand, 0); +} + +/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */ + +static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip) +{ + int mfr, id, i; + + NAND_ENABLE_CE(nand); /* set pin low */ + /* Reset the chip */ + if (NanD_Command(nand, NAND_CMD_RESET)) { +#ifdef NAND_DEBUG + printf("NanD_Command (reset) for %d,%d returned true\n", + floor, chip); +#endif + NAND_DISABLE_CE(nand); /* set pin high */ + return 0; + } + + /* Read the NAND chip ID: 1. Send ReadID command */ + if (NanD_Command(nand, NAND_CMD_READID)) { +#ifdef NAND_DEBUG + printf("NanD_Command (ReadID) for %d,%d returned true\n", + floor, chip); +#endif + NAND_DISABLE_CE(nand); /* set pin high */ + return 0; + } + + /* Read the NAND chip ID: 2. Send address byte zero */ + NanD_Address(nand, ADDR_COLUMN, 0); + + /* Read the manufacturer and device id codes from the device */ + + mfr = READ_NAND(nand->IO_ADDR); + + id = READ_NAND(nand->IO_ADDR); + + NAND_DISABLE_CE(nand); /* set pin high */ + +#ifdef NAND_DEBUG + printf("NanD_Command (ReadID) got %x %x\n", mfr, id); +#endif + if (mfr == 0xff || mfr == 0) { + /* No response - return failure */ + return 0; + } + + /* Check it's the same as the first chip we identified. + * M-Systems say that any given nand_chip device should only + * contain _one_ type of flash part, although that's not a + * hardware restriction. */ + if (nand->mfr) { + if (nand->mfr == mfr && nand->id == id) { + return 1; /* This is another the same the first */ + } else { + printf("Flash chip at floor %d, chip %d is different:\n", + floor, chip); + } + } + + /* Print and store the manufacturer and ID codes. */ + for (i = 0; nand_flash_ids[i].name != NULL; i++) { + if (mfr == nand_flash_ids[i].manufacture_id && + id == nand_flash_ids[i].model_id) { +#ifdef NAND_DEBUG + printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, " + "Chip ID: 0x%2.2X (%s)\n", mfr, id, + nand_flash_ids[i].name); +#endif + if (!nand->mfr) { + nand->mfr = mfr; + nand->id = id; + nand->chipshift = + nand_flash_ids[i].chipshift; + nand->page256 = nand_flash_ids[i].page256; + nand->eccsize = 256; + if (nand->page256) { + nand->oobblock = 256; + nand->oobsize = 8; + nand->page_shift = 8; + } else { + nand->oobblock = 512; + nand->oobsize = 16; + nand->page_shift = 9; + } + nand->pageadrlen = nand_flash_ids[i].pageadrlen; + nand->erasesize = nand_flash_ids[i].erasesize; + nand->chips_name = nand_flash_ids[i].name; + nand->bus16 = nand_flash_ids[i].bus16; + return 1; + } + return 0; + } + } + + +#ifdef NAND_DEBUG + /* We haven't fully identified the chip. Print as much as we know. */ + printf("Unknown flash chip found: %2.2X %2.2X\n", + id, mfr); +#endif + + return 0; +} + +/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */ + +static void NanD_ScanChips(struct nand_chip *nand) +{ + int floor, chip; + int numchips[NAND_MAX_FLOORS]; + int maxchips = NAND_MAX_CHIPS; + int ret = 1; + + nand->numchips = 0; + nand->mfr = 0; + nand->id = 0; + + + /* For each floor, find the number of valid chips it contains */ + for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { + ret = 1; + numchips[floor] = 0; + for (chip = 0; chip < maxchips && ret != 0; chip++) { + + ret = NanD_IdentChip(nand, floor, chip); + if (ret) { + numchips[floor]++; + nand->numchips++; + } + } + } + + /* If there are none at all that we recognise, bail */ + if (!nand->numchips) { +#ifdef NAND_DEBUG + puts ("No NAND flash chips recognised.\n"); +#endif + return; + } + + /* Allocate an array to hold the information for each chip */ + nand->chips = malloc(sizeof(struct Nand) * nand->numchips); + if (!nand->chips) { + puts ("No memory for allocating chip info structures\n"); + return; + } + + ret = 0; + + /* Fill out the chip array with {floor, chipno} for each + * detected chip in the device. */ + for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { + for (chip = 0; chip < numchips[floor]; chip++) { + nand->chips[ret].floor = floor; + nand->chips[ret].chip = chip; + nand->chips[ret].curadr = 0; + nand->chips[ret].curmode = 0x50; + ret++; + } + } + + /* Calculate and print the total size of the device */ + nand->totlen = nand->numchips * (1 << nand->chipshift); + +#ifdef NAND_DEBUG + printf("%d flash chips found. Total nand_chip size: %ld MB\n", + nand->numchips, nand->totlen >> 20); +#endif +} + +/* we need to be fast here, 1 us per read translates to 1 second per meg */ +static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr) +{ + unsigned long nandptr = nand->IO_ADDR; + + NanD_Command (nand, NAND_CMD_READ0); + + if (nand->bus16) { + u16 val; + + while (cntr >= 16) { + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + cntr -= 16; + } + + while (cntr > 0) { + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + cntr -= 2; + } + } else { + while (cntr >= 16) { + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + cntr -= 16; + } + + while (cntr > 0) { + *data_buf++ = READ_NAND (nandptr); + cntr--; + } + } +} + +/* + * NAND read with ECC + */ +static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, + size_t * retlen, u_char *buf, u_char *ecc_code) +{ + int col, page; + int ecc_status = 0; +#ifdef CONFIG_MTD_NAND_ECC + int j; + int ecc_failed = 0; + u_char *data_poi; + u_char ecc_calc[6]; +#endif + + /* Do not allow reads past end of device */ + if ((start + len) > nand->totlen) { + printf ("%s: Attempt read beyond end of device %x %x %x\n", + __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen); + *retlen = 0; + return -1; + } + + /* First we calculate the starting page */ + /*page = shr(start, nand->page_shift);*/ + page = start >> nand->page_shift; + + /* Get raw starting column */ + col = start & (nand->oobblock - 1); + + /* Initialize return value */ + *retlen = 0; + + /* Select the NAND device */ + NAND_ENABLE_CE(nand); /* set pin low */ + + /* Loop until all data read */ + while (*retlen < len) { + +#ifdef CONFIG_MTD_NAND_ECC + /* Do we have this page in cache ? */ + if (nand->cache_page == page) + goto readdata; + /* Send the read command */ + NanD_Command(nand, NAND_CMD_READ0); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Read in a page + oob data */ + NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize); + + /* copy data into cache, for read out of cache and if ecc fails */ + if (nand->data_cache) { + memcpy (nand->data_cache, nand->data_buf, + nand->oobblock + nand->oobsize); + } + + /* Pick the ECC bytes out of the oob data */ + for (j = 0; j < 6; j++) { + ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])]; + } + + /* Calculate the ECC and verify it */ + /* If block was not written with ECC, skip ECC */ + if (oob_config.eccvalid_pos != -1 && + (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) { + + nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]); + switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) { + case -1: + printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); + ecc_failed++; + break; + case 1: + case 2: /* transfer ECC corrected data to cache */ + if (nand->data_cache) + memcpy (nand->data_cache, nand->data_buf, 256); + break; + } + } + + if (oob_config.eccvalid_pos != -1 && + nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) { + + nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]); + switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) { + case -1: + printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); + ecc_failed++; + break; + case 1: + case 2: /* transfer ECC corrected data to cache */ + if (nand->data_cache) + memcpy (&nand->data_cache[256], &nand->data_buf[256], 256); + break; + } + } +readdata: + /* Read the data from ECC data buffer into return buffer */ + data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf; + data_poi += col; + if ((*retlen + (nand->oobblock - col)) >= len) { + memcpy (buf + *retlen, data_poi, len - *retlen); + *retlen = len; + } else { + memcpy (buf + *retlen, data_poi, nand->oobblock - col); + *retlen += nand->oobblock - col; + } + /* Set cache page address, invalidate, if ecc_failed */ + nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1; + + ecc_status += ecc_failed; + ecc_failed = 0; + +#else + /* Send the read command */ + NanD_Command(nand, NAND_CMD_READ0); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Read the data directly into the return buffer */ + if ((*retlen + (nand->oobblock - col)) >= len) { + NanD_ReadBuf(nand, buf + *retlen, len - *retlen); + *retlen = len; + /* We're done */ + continue; + } else { + NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col); + *retlen += nand->oobblock - col; + } +#endif + /* For subsequent reads align to page boundary. */ + col = 0; + /* Increment page address */ + page++; + } + + /* De-select the NAND device */ + NAND_DISABLE_CE(nand); /* set pin high */ + + /* + * Return success, if no ECC failures, else -EIO + * fs driver will take care of that, because + * retlen == desired len and result == -EIO + */ + return ecc_status ? -1 : 0; +} + +/* + * Nand_page_program function is used for write and writev ! + */ +static int nand_write_page (struct nand_chip *nand, + int page, int col, int last, u_char * ecc_code) +{ + + int i; + unsigned long nandptr = nand->IO_ADDR; + +#ifdef CONFIG_MTD_NAND_ECC +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + int ecc_bytes = (nand->oobblock == 512) ? 6 : 3; +#endif +#endif + /* pad oob area */ + for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++) + nand->data_buf[i] = 0xff; + +#ifdef CONFIG_MTD_NAND_ECC + /* Zero out the ECC array */ + for (i = 0; i < 6; i++) + ecc_code[i] = 0x00; + + /* Read back previous written data, if col > 0 */ + if (col) { + NanD_Command (nand, NAND_CMD_READ0); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + if (nand->bus16) { + u16 val; + + for (i = 0; i < col; i += 2) { + val = READ_NAND (nandptr); + nand->data_buf[i] = val & 0xff; + nand->data_buf[i + 1] = val >> 8; + } + } else { + for (i = 0; i < col; i++) + nand->data_buf[i] = READ_NAND (nandptr); + } + } + + /* Calculate and write the ECC if we have enough data */ + if ((col < nand->eccsize) && (last >= nand->eccsize)) { + nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0])); + for (i = 0; i < 3; i++) { + nand->data_buf[(nand->oobblock + + oob_config.ecc_pos[i])] = ecc_code[i]; + } + if (oob_config.eccvalid_pos != -1) { + nand->data_buf[nand->oobblock + + oob_config.eccvalid_pos] = 0xf0; + } + } + + /* Calculate and write the second ECC if we have enough data */ + if ((nand->oobblock == 512) && (last == nand->oobblock)) { + nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3])); + for (i = 3; i < 6; i++) { + nand->data_buf[(nand->oobblock + + oob_config.ecc_pos[i])] = ecc_code[i]; + } + if (oob_config.eccvalid_pos != -1) { + nand->data_buf[nand->oobblock + + oob_config.eccvalid_pos] &= 0x0f; + } + } +#endif + /* Prepad for partial page programming !!! */ + for (i = 0; i < col; i++) + nand->data_buf[i] = 0xff; + + /* Postpad for partial page programming !!! oob is already padded */ + for (i = last; i < nand->oobblock; i++) + nand->data_buf[i] = 0xff; + + /* Send command to begin auto page programming */ + NanD_Command (nand, NAND_CMD_READ0); + NanD_Command (nand, NAND_CMD_SEQIN); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Write out complete page of data */ + if (nand->bus16) { + for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) { + WRITE_NAND (nand->data_buf[i] + + (nand->data_buf[i + 1] << 8), + nand->IO_ADDR); + } + } else { + for (i = 0; i < (nand->oobblock + nand->oobsize); i++) + WRITE_NAND (nand->data_buf[i], nand->IO_ADDR); + } + + /* Send command to actually program the data */ + NanD_Command (nand, NAND_CMD_PAGEPROG); + NanD_Command (nand, NAND_CMD_STATUS); +#ifdef NAND_NO_RB + { + u_char ret_val; + + do { + ret_val = READ_NAND (nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + /* See if device thinks it succeeded */ + if (READ_NAND (nand->IO_ADDR) & 0x01) { + printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, + page); + return -1; + } +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* + * The NAND device assumes that it is always writing to + * a cleanly erased page. Hence, it performs its internal + * write verification only on bits that transitioned from + * 1 to 0. The device does NOT verify the whole page on a + * byte by byte basis. It is possible that the page was + * not completely erased or the page is becoming unusable + * due to wear. The read with ECC would catch the error + * later when the ECC page check fails, but we would rather + * catch it early in the page write stage. Better to write + * no data than invalid data. + */ + + /* Send command to read back the page */ + if (col < nand->eccsize) + NanD_Command (nand, NAND_CMD_READ0); + else + NanD_Command (nand, NAND_CMD_READ1); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Loop through and verify the data */ + if (nand->bus16) { + for (i = col; i < last; i = +2) { + if ((nand->data_buf[i] + + (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) { + printf ("%s: Failed write verify, page 0x%08x ", + __FUNCTION__, page); + return -1; + } + } + } else { + for (i = col; i < last; i++) { + if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) { + printf ("%s: Failed write verify, page 0x%08x ", + __FUNCTION__, page); + return -1; + } + } + } + +#ifdef CONFIG_MTD_NAND_ECC + /* + * We also want to check that the ECC bytes wrote + * correctly for the same reasons stated above. + */ + NanD_Command (nand, NAND_CMD_READOOB); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + if (nand->bus16) { + for (i = 0; i < nand->oobsize; i += 2) { + u16 val; + + val = READ_NAND (nand->IO_ADDR); + nand->data_buf[i] = val & 0xff; + nand->data_buf[i + 1] = val >> 8; + } + } else { + for (i = 0; i < nand->oobsize; i++) { + nand->data_buf[i] = READ_NAND (nand->IO_ADDR); + } + } + for (i = 0; i < ecc_bytes; i++) { + if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) { + printf ("%s: Failed ECC write " + "verify, page 0x%08x, " + "%6i bytes were succesful\n", + __FUNCTION__, page, i); + return -1; + } + } +#endif /* CONFIG_MTD_NAND_ECC */ +#endif /* CONFIG_MTD_NAND_VERIFY_WRITE */ + return 0; +} + +static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * ecc_code) +{ + int i, page, col, cnt, ret = 0; + + /* Do not allow write past end of device */ + if ((to + len) > nand->totlen) { + printf ("%s: Attempt to write past end of page\n", __FUNCTION__); + return -1; + } + + /* Shift to get page */ + page = ((int) to) >> nand->page_shift; + + /* Get the starting column */ + col = to & (nand->oobblock - 1); + + /* Initialize return length value */ + *retlen = 0; + + /* Select the NAND device */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,0); +#endif +#ifdef CFG_NAND_WP + NAND_WP_OFF(); +#endif + + NAND_ENABLE_CE(nand); /* set pin low */ + + /* Check the WP bit */ + NanD_Command(nand, NAND_CMD_STATUS); + if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { + printf ("%s: Device is write protected!!!\n", __FUNCTION__); + ret = -1; + goto out; + } + + /* Loop until all data is written */ + while (*retlen < len) { + /* Invalidate cache, if we write to this page */ + if (nand->cache_page == page) + nand->cache_page = -1; + + /* Write data into buffer */ + if ((col + len) >= nand->oobblock) { + for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) { + nand->data_buf[i] = buf[(*retlen + cnt)]; + } + } else { + for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) { + nand->data_buf[i] = buf[(*retlen + cnt)]; + } + } + /* We use the same function for write and writev !) */ + ret = nand_write_page (nand, page, col, i, ecc_code); + if (ret) + goto out; + + /* Next data start at page boundary */ + col = 0; + + /* Update written bytes count */ + *retlen += cnt; + + /* Increment page address */ + page++; + } + + /* Return happy */ + *retlen = len; + +out: + /* De-select the NAND device */ + NAND_DISABLE_CE(nand); /* set pin high */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,1); +#endif +#ifdef CFG_NAND_WP + NAND_WP_ON(); +#endif + + return ret; +} + +/* read from the 16 bytes of oob data that correspond to a 512 byte + * page or 2 256-byte pages. + */ +static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, u_char * buf) +{ + int len256 = 0; + struct Nand *mychip; + int ret = 0; + + mychip = &nand->chips[ofs >> nand->chipshift]; + + /* update address for 2M x 8bit devices. OOB starts on the second */ + /* page to maintain compatibility with nand_read_ecc. */ + if (nand->page256) { + if (!(ofs & 0x8)) + ofs += 0x100; + else + ofs -= 0x8; + } + + NAND_ENABLE_CE(nand); /* set pin low */ + NanD_Command(nand, NAND_CMD_READOOB); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + ((ofs >> nand->page_shift) << nand->page_shift) + + ((ofs & (nand->oobblock - 1)) >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); + } + + /* treat crossing 8-byte OOB data for 2M x 8bit devices */ + /* Note: datasheet says it should automaticaly wrap to the */ + /* next OOB block, but it didn't work here. mf. */ + if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { + len256 = (ofs | 0x7) + 1 - ofs; + NanD_ReadBuf(nand, buf, len256); + + NanD_Command(nand, NAND_CMD_READOOB); + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); + } + + NanD_ReadBuf(nand, &buf[len256], len - len256); + + *retlen = len; + /* Reading the full OOB data drops us off of the end of the page, + * causing the flash device to go into busy mode, so we need + * to wait until ready 11.4.1 and Toshiba TC58256FT nands */ + + ret = NanD_WaitReady(nand, 1); + NAND_DISABLE_CE(nand); /* set pin high */ + + return ret; + +} + +/* write to the 16 bytes of oob data that correspond to a 512 byte + * page or 2 256-byte pages. + */ +static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, const u_char * buf) +{ + int len256 = 0; + int i; + unsigned long nandptr = nand->IO_ADDR; + +#ifdef PSYCHO_DEBUG + printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n", + (long)ofs, len, buf[0], buf[1], buf[2], buf[3], + buf[8], buf[9], buf[14],buf[15]); +#endif + + NAND_ENABLE_CE(nand); /* set pin low to enable chip */ + + /* Reset the chip */ + NanD_Command(nand, NAND_CMD_RESET); + + /* issue the Read2 command to set the pointer to the Spare Data Area. */ + NanD_Command(nand, NAND_CMD_READOOB); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + ((ofs >> nand->page_shift) << nand->page_shift) + + ((ofs & (nand->oobblock - 1)) >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); + } + + /* update address for 2M x 8bit devices. OOB starts on the second */ + /* page to maintain compatibility with nand_read_ecc. */ + if (nand->page256) { + if (!(ofs & 0x8)) + ofs += 0x100; + else + ofs -= 0x8; + } + + /* issue the Serial Data In command to initial the Page Program process */ + NanD_Command(nand, NAND_CMD_SEQIN); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + ((ofs >> nand->page_shift) << nand->page_shift) + + ((ofs & (nand->oobblock - 1)) >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); + } + + /* treat crossing 8-byte OOB data for 2M x 8bit devices */ + /* Note: datasheet says it should automaticaly wrap to the */ + /* next OOB block, but it didn't work here. mf. */ + if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { + len256 = (ofs | 0x7) + 1 - ofs; + for (i = 0; i < len256; i++) + WRITE_NAND(buf[i], nandptr); + + NanD_Command(nand, NAND_CMD_PAGEPROG); + NanD_Command(nand, NAND_CMD_STATUS); +#ifdef NAND_NO_RB + { u_char ret_val; + do { + ret_val = READ_NAND(nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + if (READ_NAND(nandptr) & 1) { + puts ("Error programming oob data\n"); + /* There was an error */ + NAND_DISABLE_CE(nand); /* set pin high */ + *retlen = 0; + return -1; + } + NanD_Command(nand, NAND_CMD_SEQIN); + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); + } + + if (nand->bus16) { + for (i = len256; i < len; i += 2) { + WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr); + } + } else { + for (i = len256; i < len; i++) + WRITE_NAND(buf[i], nandptr); + } + + NanD_Command(nand, NAND_CMD_PAGEPROG); + NanD_Command(nand, NAND_CMD_STATUS); +#ifdef NAND_NO_RB + { u_char ret_val; + do { + ret_val = READ_NAND(nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + if (READ_NAND(nandptr) & 1) { + puts ("Error programming oob data\n"); + /* There was an error */ + NAND_DISABLE_CE(nand); /* set pin high */ + *retlen = 0; + return -1; + } + + NAND_DISABLE_CE(nand); /* set pin high */ + *retlen = len; + return 0; + +} + +int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean) +{ + /* This is defined as a structure so it will work on any system + * using native endian jffs2 (the default). + */ + static struct jffs2_unknown_node clean_marker = { + JFFS2_MAGIC_BITMASK, + JFFS2_NODETYPE_CLEANMARKER, + 8 /* 8 bytes in this node */ + }; + unsigned long nandptr; + struct Nand *mychip; + int ret = 0; + + if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) { + printf ("Offset and size must be sector aligned, erasesize = %d\n", + (int) nand->erasesize); + return -1; + } + + nandptr = nand->IO_ADDR; + + /* Select the NAND device */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,0); +#endif +#ifdef CFG_NAND_WP + NAND_WP_OFF(); +#endif + NAND_ENABLE_CE(nand); /* set pin low */ + + /* Check the WP bit */ + NanD_Command(nand, NAND_CMD_STATUS); + if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { + printf ("nand_write_ecc: Device is write protected!!!\n"); + ret = -1; + goto out; + } + + /* Check the WP bit */ + NanD_Command(nand, NAND_CMD_STATUS); + if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { + printf ("%s: Device is write protected!!!\n", __FUNCTION__); + ret = -1; + goto out; + } + + /* FIXME: Do nand in the background. Use timers or schedule_task() */ + while(len) { + /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/ + mychip = &nand->chips[ofs >> nand->chipshift]; + + /* always check for bad block first, genuine bad blocks + * should _never_ be erased. + */ + if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) { + /* Select the NAND device */ + NAND_ENABLE_CE(nand); /* set pin low */ + + NanD_Command(nand, NAND_CMD_ERASE1); + NanD_Address(nand, ADDR_PAGE, ofs); + NanD_Command(nand, NAND_CMD_ERASE2); + + NanD_Command(nand, NAND_CMD_STATUS); + +#ifdef NAND_NO_RB + { u_char ret_val; + do { + ret_val = READ_NAND(nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + if (READ_NAND(nandptr) & 1) { + printf ("%s: Error erasing at 0x%lx\n", + __FUNCTION__, (long)ofs); + /* There was an error */ + ret = -1; + goto out; + } + if (clean) { + int n; /* return value not used */ + int p, l; + + /* clean marker position and size depend + * on the page size, since 256 byte pages + * only have 8 bytes of oob data + */ + if (nand->page256) { + p = NAND_JFFS2_OOB8_FSDAPOS; + l = NAND_JFFS2_OOB8_FSDALEN; + } else { + p = NAND_JFFS2_OOB16_FSDAPOS; + l = NAND_JFFS2_OOB16_FSDALEN; + } + + ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n, + (u_char *)&clean_marker); + /* quit here if write failed */ + if (ret) + goto out; + } + } + ofs += nand->erasesize; + len -= nand->erasesize; + } + +out: + /* De-select the NAND device */ + NAND_DISABLE_CE(nand); /* set pin high */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,1); +#endif +#ifdef CFG_NAND_WP + NAND_WP_ON(); +#endif + + return ret; +} + +static inline int nandcheck(unsigned long potential, unsigned long physadr) +{ + return 0; +} + +unsigned long nand_probe(unsigned long physadr) +{ + struct nand_chip *nand = NULL; + int i = 0, ChipID = 1; + +#ifdef CONFIG_MTD_NAND_ECC_JFFS2 + oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0; + oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1; + oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2; + oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3; + oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4; + oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5; + oob_config.eccvalid_pos = 4; +#else + oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0; + oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1; + oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2; + oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3; + oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4; + oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5; + oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS; +#endif + oob_config.badblock_pos = 5; + + for (i=0; iIO_ADDR = physadr; + nand->cache_page = -1; /* init the cache page */ + NanD_ScanChips(nand); + + if (nand->totlen == 0) { + /* no chips found, clean up and quit */ + memset((char *)nand, 0, sizeof(struct nand_chip)); + nand->ChipID = NAND_ChipID_UNKNOWN; + return (0); + } + + nand->ChipID = ChipID; + if (curr_device == -1) + curr_device = i; + + nand->data_buf = malloc (nand->oobblock + nand->oobsize); + if (!nand->data_buf) { + puts ("Cannot allocate memory for data structures.\n"); + return (0); + } + + return (nand->totlen); +} + +#ifdef CONFIG_MTD_NAND_ECC +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const u_char nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, + 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, + 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, + 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, + 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, + 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, + 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, + 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, + 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, + 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, + 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, + 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, + 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, + 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, + 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, + 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, + 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 +}; + + +/* + * Creates non-inverted ECC code from line parity + */ +static void nand_trans_result(u_char reg2, u_char reg3, + u_char *ecc_code) +{ + u_char a, b, i, tmp1, tmp2; + + /* Initialize variables */ + a = b = 0x80; + tmp1 = tmp2 = 0; + + /* Calculate first ECC byte */ + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + a >>= 1; + } + + /* Calculate second ECC byte */ + b = 0x80; + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + a >>= 1; + } + + /* Store two of the ECC bytes */ + ecc_code[0] = tmp1; + ecc_code[1] = tmp2; +} + +/* + * Calculate 3 byte ECC code for 256 byte block + */ +static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) +{ + u_char idx, reg1, reg3; + int j; + + /* Initialize variables */ + reg1 = reg3 = 0; + ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; + + /* Build up column parity */ + for(j = 0; j < 256; j++) { + + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[dat[j]]; + reg1 ^= idx; + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (u_char) j; + } + } + + /* Create non-inverted ECC code from line parity */ + nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); + + /* Calculate final ECC code */ + ecc_code[0] = ~ecc_code[0]; + ecc_code[1] = ~ecc_code[1]; + ecc_code[2] = ((~reg1) << 2) | 0x03; +} + +/* + * Detect and correct a 1 bit error for 256 byte block + */ +static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + u_char a, b, c, d1, d2, d3, add, bit, i; + + /* Do error detection */ + d1 = calc_ecc[0] ^ read_ecc[0]; + d2 = calc_ecc[1] ^ read_ecc[1]; + d3 = calc_ecc[2] ^ read_ecc[2]; + + if ((d1 | d2 | d3) == 0) { + /* No errors */ + return 0; + } else { + a = (d1 ^ (d1 >> 1)) & 0x55; + b = (d2 ^ (d2 >> 1)) & 0x55; + c = (d3 ^ (d3 >> 1)) & 0x54; + + /* Found and will correct single bit error in the data */ + if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { + c = 0x80; + add = 0; + a = 0x80; + for (i=0; i<4; i++) { + if (d1 & c) + add |= a; + c >>= 2; + a >>= 1; + } + c = 0x80; + for (i=0; i<4; i++) { + if (d2 & c) + add |= a; + c >>= 2; + a >>= 1; + } + bit = 0; + b = 0x04; + c = 0x80; + for (i=0; i<3; i++) { + if (d3 & c) + bit |= b; + c >>= 2; + b >>= 1; + } + b = 0x01; + a = dat[add]; + a ^= (b << bit); + dat[add] = a; + return 1; + } + else { + i = 0; + while (d1) { + if (d1 & 0x01) + ++i; + d1 >>= 1; + } + while (d2) { + if (d2 & 0x01) + ++i; + d2 >>= 1; + } + while (d3) { + if (d3 & 0x01) + ++i; + d3 >>= 1; + } + if (i == 1) { + /* ECC Code Error Correction */ + read_ecc[0] = calc_ecc[0]; + read_ecc[1] = calc_ecc[1]; + read_ecc[2] = calc_ecc[2]; + return 2; + } + else { + /* Uncorrectable Error */ + return -1; + } + } + } + + /* Should never happen */ + return -1; +} + +#endif + +#ifdef CONFIG_JFFS2_NAND + +int read_jffs2_nand(size_t start, size_t len, + size_t * retlen, u_char * buf, int nanddev) +{ + return nand_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2, + start, len, retlen, buf); +} + +#endif /* CONFIG_JFFS2_NAND */ + + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/common/cmd_net.c b/common/cmd_net.c new file mode 100644 index 0000000..2cb2c5d --- /dev/null +++ b/common/cmd_net.c @@ -0,0 +1,333 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Boot support + */ +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + + +extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + +static int netboot_common (proto_t, cmd_tbl_t *, int , char *[]); + +int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return netboot_common (BOOTP, cmdtp, argc, argv); +} + +U_BOOT_CMD( + bootp, 3, 1, do_bootp, + "bootp\t- boot image via network using BootP/TFTP protocol\n", + "[loadAddress] [bootfilename]\n" +); + +int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return netboot_common (TFTP, cmdtp, argc, argv); +} + +U_BOOT_CMD( + tftpboot, 3, 1, do_tftpb, + "tftpboot- boot image via network using TFTP protocol\n", + "[loadAddress] [bootfilename]\n" +); + +int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return netboot_common (RARP, cmdtp, argc, argv); +} + +U_BOOT_CMD( + rarpboot, 3, 1, do_rarpb, + "rarpboot- boot image via network using RARP/TFTP protocol\n", + "[loadAddress] [bootfilename]\n" +); + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return netboot_common(DHCP, cmdtp, argc, argv); +} + +U_BOOT_CMD( + dhcp, 3, 1, do_dhcp, + "dhcp\t- invoke DHCP client to obtain IP/boot params\n", + "\n" +); +#endif /* CFG_CMD_DHCP */ + +#if (CONFIG_COMMANDS & CFG_CMD_NFS) +int do_nfs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return netboot_common(NFS, cmdtp, argc, argv); +} + +U_BOOT_CMD( + nfs, 3, 1, do_nfs, + "nfs\t- boot image via network using NFS protocol\n", + "[loadAddress] [host ip addr:bootfilename]\n" +); +#endif /* CFG_CMD_NFS */ + +static void netboot_update_env (void) +{ + char tmp[22]; + + if (NetOurGatewayIP) { + ip_to_string (NetOurGatewayIP, tmp); + setenv ("gatewayip", tmp); + } + + if (NetOurSubnetMask) { + ip_to_string (NetOurSubnetMask, tmp); + setenv ("netmask", tmp); + } + + if (NetOurHostName[0]) + setenv ("hostname", NetOurHostName); + + if (NetOurRootPath[0]) + setenv ("rootpath", NetOurRootPath); + + if (NetOurIP) { + ip_to_string (NetOurIP, tmp); + setenv ("ipaddr", tmp); + } + + if (NetServerIP) { + ip_to_string (NetServerIP, tmp); + setenv ("serverip", tmp); + } + + if (NetOurDNSIP) { + ip_to_string (NetOurDNSIP, tmp); + setenv ("dnsip", tmp); + } +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) + if (NetOurDNS2IP) { + ip_to_string (NetOurDNS2IP, tmp); + setenv ("dnsip2", tmp); + } +#endif + if (NetOurNISDomain[0]) + setenv ("domain", NetOurNISDomain); + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) + if (NetTimeOffset) { + sprintf (tmp, "%d", NetTimeOffset); + setenv ("timeoffset", tmp); + } +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) + if (NetNtpServerIP) { + ip_to_string (NetNtpServerIP, tmp); + setenv ("ntpserverip", tmp); + } +#endif +} + +static int +netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) +{ + char *s; + int rcode = 0; + int size; + + /* pre-set load_addr */ + if ((s = getenv("loadaddr")) != NULL) { + load_addr = simple_strtoul(s, NULL, 16); + } + + switch (argc) { + case 1: + break; + + case 2: /* only one arg - accept two forms: + * just load address, or just boot file name. + * The latter form must be written "filename" here. + */ + if (argv[1][0] == '"') { /* just boot filename */ + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } else { /* load address */ + load_addr = simple_strtoul(argv[1], NULL, 16); + } + break; + + case 3: load_addr = simple_strtoul(argv[1], NULL, 16); + copy_filename (BootFile, argv[2], sizeof(BootFile)); + + break; + + default: printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((size = NetLoop(proto)) < 0) + return 1; + + /* NetLoop ok, update environment */ + netboot_update_env(); + + /* done if no file was loaded (no errors though) */ + if (size == 0) + return 0; + + /* flush cache */ + flush_cache(load_addr, size); + + /* Loading ok, check if we should attempt an auto-start */ + if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) { + char *local_args[2]; + local_args[0] = argv[0]; + local_args[1] = NULL; + + printf ("Automatic boot of image at addr 0x%08lX ...\n", + load_addr); + rcode = do_bootm (cmdtp, 0, 1, local_args); + } + +#ifdef CONFIG_AUTOSCRIPT + if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { + printf("Running autoscript at addr 0x%08lX ...\n", load_addr); + rcode = autoscript (load_addr); + } +#endif + return rcode; +} + +#if (CONFIG_COMMANDS & CFG_CMD_PING) +int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc < 2) + return -1; + + NetPingIP = string_to_ip(argv[1]); + if (NetPingIP == 0) { + printf ("Usage:\n%s\n", cmdtp->usage); + return -1; + } + + if (NetLoop(PING) < 0) { + printf("ping failed; host %s is not alive\n", argv[1]); + return 1; + } + + printf("host %s is alive\n", argv[1]); + + return 0; +} + +U_BOOT_CMD( + ping, 2, 1, do_ping, + "ping\t- send ICMP ECHO_REQUEST to network host\n", + "pingAddress\n" +); +#endif /* CFG_CMD_PING */ + +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + +static void cdp_update_env(void) +{ + char tmp[16]; + + if (CDPApplianceVLAN != htons(-1)) { + printf("CDP offered appliance VLAN %d\n", ntohs(CDPApplianceVLAN)); + VLAN_to_string(CDPApplianceVLAN, tmp); + setenv("vlan", tmp); + NetOurVLAN = CDPApplianceVLAN; + } + + if (CDPNativeVLAN != htons(-1)) { + printf("CDP offered native VLAN %d\n", ntohs(CDPNativeVLAN)); + VLAN_to_string(CDPNativeVLAN, tmp); + setenv("nvlan", tmp); + NetOurNativeVLAN = CDPNativeVLAN; + } + +} + +int do_cdp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int r; + + r = NetLoop(CDP); + if (r < 0) { + printf("cdp failed; perhaps not a CISCO switch?\n"); + return 1; + } + + cdp_update_env(); + + return 0; +} + +U_BOOT_CMD( + cdp, 1, 1, do_cdp, + "cdp\t- Perform CDP network configuration\n", +); +#endif /* CFG_CMD_CDP */ + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) +int do_sntp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *toff; + + if (argc < 2) { + NetNtpServerIP = getenv_IPaddr ("ntpserverip"); + if (NetNtpServerIP == 0) { + printf ("ntpserverip not set\n"); + return (1); + } + } else { + NetNtpServerIP = string_to_ip(argv[1]); + if (NetNtpServerIP == 0) { + printf ("Bad NTP server IP address\n"); + return (1); + } + } + + toff = getenv ("timeoffset"); + if (toff == NULL) NetTimeOffset = 0; + else NetTimeOffset = simple_strtol (toff, NULL, 10); + + if (NetLoop(SNTP) < 0) { + printf("SNTP failed: host %s not responding\n", argv[1]); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + sntp, 2, 1, do_sntp, + "sntp\t- synchronize RTC via network\n", + "[NTP server IP]\n" +); +#endif /* CFG_CMD_SNTP */ + +#endif /* CFG_CMD_NET */ diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c new file mode 100644 index 0000000..1babffe --- /dev/null +++ b/common/cmd_nvedit.c @@ -0,0 +1,625 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************** + * + * Support for persistent environment data + * + * The "environment" is stored as a list of '\0' terminated + * "name=value" strings. The end of the list is marked by a double + * '\0'. New entries are always added at the end. Deleting an entry + * shifts the remaining entries to the front. Replacing an entry is a + * combination of deleting the old value and adding the new one. + * + * The environment is preceeded by a 32 bit CRC over the data part. + * + ************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#include +#endif + +#if !defined(CFG_ENV_IS_IN_NVRAM) && \ + !defined(CFG_ENV_IS_IN_EEPROM) && \ + !defined(CFG_ENV_IS_IN_FLASH) && \ + !defined(CFG_ENV_IS_IN_DATAFLASH) && \ + !defined(CFG_ENV_IS_IN_NAND) && \ + !defined(CFG_ENV_IS_NOWHERE) +# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|NOWHERE} +#endif + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +/************************************************************************ +************************************************************************/ + +/* Function that returns a character from the environment */ +extern uchar (*env_get_char)(int); + +/* Function that returns a pointer to a value from the environment */ +/* (Only memory version supported / needed). */ +extern uchar *env_get_addr(int); + +/* Function that updates CRC of the enironment */ +extern void env_crc_update (void); + +/************************************************************************ +************************************************************************/ + +static int envmatch (uchar *, int); + +/* + * Table with supported baudrates (defined in config_xyz.h) + */ +static const unsigned long baudrate_table[] = CFG_BAUDRATE_TABLE; +#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0])) + + +/************************************************************************ + * Command interface: print one or all environment variables + */ + +int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i, j, k, nxt; + int rcode = 0; + + if (argc == 1) { /* Print all env variables */ + for (i=0; env_get_char(i) != '\0'; i=nxt+1) { + for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) + ; + for (k=i; kbd; + + uchar *env_data = env_get_addr(0); + + if (!env_data) /* need copy in RAM */ + return 1; + + name = argv[1]; + + /* + * search if variable with this name already exists + */ + oldval = -1; + for (env=env_data; *env; env=nxt+1) { + for (nxt=env; *nxt; ++nxt) + ; + if ((oldval = envmatch((uchar *)name, env-env_data)) >= 0) + break; + } + + /* + * Delete any existing definition + */ + if (oldval >= 0) { +#ifndef CONFIG_ENV_OVERWRITE + + /* + * Ethernet Address and serial# can be set only once, + * ver is readonly. + */ + if ( (strcmp (name, "serial#") == 0) || + ((strcmp (name, "ethaddr") == 0) +#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) + && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0) +#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */ + ) ) { + printf ("Can't overwrite \"%s\"\n", name); + return 1; + } +#endif + + /* Check for console redirection */ + if (strcmp(name,"stdin") == 0) { + console = stdin; + } else if (strcmp(name,"stdout") == 0) { + console = stdout; + } else if (strcmp(name,"stderr") == 0) { + console = stderr; + } + + if (console != -1) { + if (argc < 3) { /* Cannot delete it! */ + printf("Can't delete \"%s\"\n", name); + return 1; + } + + /* Try assigning specified device */ + if (console_assign (console, argv[2]) < 0) + return 1; + +#ifdef CONFIG_SERIAL_MULTI + if (serial_assign (argv[2]) < 0) + return 1; +#endif + } + + /* + * Switch to new baudrate if new baudrate is supported + */ + if (strcmp(argv[1],"baudrate") == 0) { + int baudrate = simple_strtoul(argv[2], NULL, 10); + int i; + for (i=0; ibaudrate = baudrate; +#ifdef CONFIG_PPC + gd->bd->bi_baudrate = baudrate; +#endif + + serial_setbrg (); + udelay(50000); + for (;;) { + if (getc() == '\r') + break; + } + } + + if (*++nxt == '\0') { + if (env > env_data) { + env--; + } else { + *env = '\0'; + } + } else { + for (;;) { + *env = *nxt++; + if ((*env == '\0') && (*nxt == '\0')) + break; + ++env; + } + } + *++env = '\0'; + } + +#ifdef CONFIG_NET_MULTI + if (strncmp(name, "eth", 3) == 0) { + char *end; + int num = simple_strtoul(name+3, &end, 10); + + if (strcmp(end, "addr") == 0) { + eth_set_enetaddr(num, argv[2]); + } + } +#endif + + + /* Delete only ? */ + if ((argc < 3) || argv[2] == NULL) { + env_crc_update (); + return 0; + } + + /* + * Append new definition at the end + */ + for (env=env_data; *env || *(env+1); ++env) + ; + if (env > env_data) + ++env; + /* + * Overflow when: + * "name" + "=" + "val" +"\0\0" > ENV_SIZE - (env-env_data) + */ + len = strlen(name) + 2; + /* add '=' for first arg, ' ' for all others */ + for (i=2; i (&env_data[ENV_SIZE]-env)) { + printf ("## Error: environment overflow, \"%s\" deleted\n", name); + return 1; + } + while ((*env = *name++) != '\0') + env++; + for (i=2; ibi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) s = (*e) ? e+1 : e; + } +#ifdef CONFIG_NET_MULTI + eth_set_enetaddr(0, argv[2]); +#endif + return 0; + } + + if (strcmp(argv[1],"ipaddr") == 0) { + char *s = argv[2]; /* always use only one arg */ + char *e; + unsigned long addr; + bd->bi_ip_addr = 0; + for (addr=0, i=0; i<4; ++i) { + ulong val = s ? simple_strtoul(s, &e, 10) : 0; + addr <<= 8; + addr |= (val & 0xFF); + if (s) s = (*e) ? e+1 : e; + } + bd->bi_ip_addr = htonl(addr); + return 0; + } + if (strcmp(argv[1],"loadaddr") == 0) { + load_addr = simple_strtoul(argv[2], NULL, 16); + return 0; + } +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if (strcmp(argv[1],"bootfile") == 0) { + copy_filename (BootFile, argv[2], sizeof(BootFile)); + return 0; + } +#endif /* CFG_CMD_NET */ + +#ifdef CONFIG_AMIGAONEG3SE + if (strcmp(argv[1], "vga_fg_color") == 0 || + strcmp(argv[1], "vga_bg_color") == 0 ) { + extern void video_set_color(unsigned char attr); + extern unsigned char video_get_attr(void); + + video_set_color(video_get_attr()); + return 0; + } +#endif /* CONFIG_AMIGAONEG3SE */ + + return 0; +} + +void setenv (char *varname, char *varvalue) +{ + char *argv[4] = { "setenv", varname, varvalue, NULL }; + _do_setenv (0, 3, argv); +} + +int do_setenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return _do_setenv (flag, argc, argv); +} + +/************************************************************************ + * Prompt for environment variable + */ + +#if (CONFIG_COMMANDS & CFG_CMD_ASKENV) +int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern char console_buffer[CFG_CBSIZE]; + char message[CFG_CBSIZE]; + int size = CFG_CBSIZE - 1; + int len; + char *local_args[4]; + + local_args[0] = argv[0]; + local_args[1] = argv[1]; + local_args[2] = NULL; + local_args[3] = NULL; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + /* Check the syntax */ + switch (argc) { + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + + case 2: /* askenv envname */ + sprintf (message, "Please enter '%s':", argv[1]); + break; + + case 3: /* askenv envname size */ + sprintf (message, "Please enter '%s':", argv[1]); + size = simple_strtoul (argv[2], NULL, 10); + break; + + default: /* askenv envname message1 ... messagen size */ + { + int i; + int pos = 0; + + for (i = 2; i < argc - 1; i++) { + if (pos) { + message[pos++] = ' '; + } + strcpy (message+pos, argv[i]); + pos += strlen(argv[i]); + } + message[pos] = '\0'; + size = simple_strtoul (argv[argc - 1], NULL, 10); + } + break; + } + + if (size >= CFG_CBSIZE) + size = CFG_CBSIZE - 1; + + if (size <= 0) + return 1; + + /* prompt for input */ + len = readline (message); + + if (size < len) + console_buffer[size] = '\0'; + + len = 2; + if (console_buffer[0] != '\0') { + local_args[2] = console_buffer; + len = 3; + } + + /* Continue calling setenv code */ + return _do_setenv (flag, len, local_args); +} +#endif /* CFG_CMD_ASKENV */ + +/************************************************************************ + * Look up variable from environment, + * return address of storage for that variable, + * or NULL if not found + */ + +char *getenv (char *name) +{ + int i, nxt; + + WATCHDOG_RESET(); + + for (i=0; env_get_char(i) != '\0'; i=nxt+1) { + int val; + + for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) { + if (nxt >= CFG_ENV_SIZE) { + return (NULL); + } + } + if ((val=envmatch((uchar *)name, i)) < 0) + continue; + return ((char *)env_get_addr(val)); + } + + return (NULL); +} + +int getenv_r (char *name, char *buf, unsigned len) +{ + int i, nxt; + + for (i=0; env_get_char(i) != '\0'; i=nxt+1) { + int val, n; + + for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) { + if (nxt >= CFG_ENV_SIZE) { + return (-1); + } + } + if ((val=envmatch((uchar *)name, i)) < 0) + continue; + /* found; copy out */ + n = 0; + while ((len > n++) && (*buf++ = env_get_char(val++)) != '\0') + ; + if (len == n) + *buf = '\0'; + return (n); + } + return (-1); +} + +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ + (CFG_CMD_ENV|CFG_CMD_FLASH)) +int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern char * env_name_spec; + + printf ("Saving Environment to %s...\n", env_name_spec); + + return (saveenv() ? 1 : 0); +} + + +#endif + + +/************************************************************************ + * Match a name / name=value pair + * + * s1 is either a simple 'name', or a 'name=value' pair. + * i2 is the environment index for a 'name2=value2' pair. + * If the names match, return the index for the value2, else NULL. + */ + +static int +envmatch (uchar *s1, int i2) +{ + + while (*s1 == env_get_char(i2++)) + if (*s1++ == '=') + return(i2); + if (*s1 == '\0' && env_get_char(i2-1) == '=') + return(i2); + return(-1); +} + + +/**************************************************/ + +U_BOOT_CMD( + printenv, CFG_MAXARGS, 1, do_printenv, + "printenv- print environment variables\n", + "\n - print values of all environment variables\n" + "printenv name ...\n" + " - print value of environment variable 'name'\n" +); + +U_BOOT_CMD( + setenv, CFG_MAXARGS, 0, do_setenv, + "setenv - set environment variables\n", + "name value ...\n" + " - set environment variable 'name' to 'value ...'\n" + "setenv name\n" + " - delete environment variable 'name'\n" +); + +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ + (CFG_CMD_ENV|CFG_CMD_FLASH)) +U_BOOT_CMD( + saveenv, 1, 0, do_saveenv, + "saveenv - save environment variables to persistent storage\n", + NULL +); + +#endif /* CFG_CMD_ENV */ + +#if (CONFIG_COMMANDS & CFG_CMD_ASKENV) + +U_BOOT_CMD( + askenv, CFG_MAXARGS, 1, do_askenv, + "askenv - get environment variables from stdin\n", + "name [message] [size]\n" + " - get environment variable 'name' from stdin (max 'size' chars)\n" + "askenv name\n" + " - get environment variable 'name' from stdin\n" + "askenv name size\n" + " - get environment variable 'name' from stdin (max 'size' chars)\n" + "askenv name [message] size\n" + " - display 'message' string and get environment variable 'name'" + "from stdin (max 'size' chars)\n" +); +#endif /* CFG_CMD_ASKENV */ + +#if (CONFIG_COMMANDS & CFG_CMD_RUN) +int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +U_BOOT_CMD( + run, CFG_MAXARGS, 1, do_run, + "run - run commands in an environment variable\n", + "var [...]\n" + " - run the commands in the environment variable(s) 'var'\n" +); +#endif /* CFG_CMD_RUN */ diff --git a/common/cmd_pci.c b/common/cmd_pci.c new file mode 100644 index 0000000..4508546 --- /dev/null +++ b/common/cmd_pci.c @@ -0,0 +1,570 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI routines + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_PCI) + +extern int cmd_get_data_size(char* arg, int default_size); + +unsigned char ShortPCIListing = 1; + +/* + * Follows routines for the output of infos about devices on PCI bus. + */ + +void pci_header_show(pci_dev_t dev); +void pci_header_show_brief(pci_dev_t dev); + +/* + * Subroutine: pciinfo + * + * Description: Show information about devices on PCI bus. + * Depending on the define CFG_SHORT_PCI_LISTING + * the output will be more or less exhaustive. + * + * Inputs: bus_no the number of the bus to be scanned. + * + * Return: None + * + */ +void pciinfo(int BusNum, int ShortPCIListing) +{ + int Device; + int Function; + unsigned char HeaderType; + unsigned short VendorID; + pci_dev_t dev; + + printf("Scanning PCI devices on bus %d\n", BusNum); + + if (ShortPCIListing) { + printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n"); + printf("_____________________________________________________________\n"); + } + + for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) { + HeaderType = 0; + VendorID = 0; + for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) { + /* + * If this is not a multi-function device, we skip the rest. + */ + if (Function && !(HeaderType & 0x80)) + break; + + dev = PCI_BDF(BusNum, Device, Function); + + pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID); + if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) + continue; + + if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType); + + if (ShortPCIListing) + { + printf("%02x.%02x.%02x ", BusNum, Device, Function); + pci_header_show_brief(dev); + } + else + { + printf("\nFound PCI device %02x.%02x.%02x:\n", + BusNum, Device, Function); + pci_header_show(dev); + } + } + } +} + +static char *pci_classes_str(u8 class) +{ + switch (class) { + case PCI_CLASS_NOT_DEFINED: + return "Build before PCI Rev2.0"; + break; + case PCI_BASE_CLASS_STORAGE: + return "Mass storage controller"; + break; + case PCI_BASE_CLASS_NETWORK: + return "Network controller"; + break; + case PCI_BASE_CLASS_DISPLAY: + return "Display controller"; + break; + case PCI_BASE_CLASS_MULTIMEDIA: + return "Multimedia device"; + break; + case PCI_BASE_CLASS_MEMORY: + return "Memory controller"; + break; + case PCI_BASE_CLASS_BRIDGE: + return "Bridge device"; + break; + case PCI_BASE_CLASS_COMMUNICATION: + return "Simple comm. controller"; + break; + case PCI_BASE_CLASS_SYSTEM: + return "Base system peripheral"; + break; + case PCI_BASE_CLASS_INPUT: + return "Input device"; + break; + case PCI_BASE_CLASS_DOCKING: + return "Docking station"; + break; + case PCI_BASE_CLASS_PROCESSOR: + return "Processor"; + break; + case PCI_BASE_CLASS_SERIAL: + return "Serial bus controller"; + break; + case PCI_BASE_CLASS_INTELLIGENT: + return "Intelligent controller"; + break; + case PCI_BASE_CLASS_SATELLITE: + return "Satellite controller"; + break; + case PCI_BASE_CLASS_CRYPT: + return "Cryptographic device"; + break; + case PCI_BASE_CLASS_SIGNAL_PROCESSING: + return "DSP"; + break; + case PCI_CLASS_OTHERS: + return "Does not fit any class"; + break; + default: + return "???"; + break; + }; +} + +/* + * Subroutine: pci_header_show_brief + * + * Description: Reads and prints the header of the + * specified PCI device in short form. + * + * Inputs: dev Bus+Device+Function number + * + * Return: None + * + */ +void pci_header_show_brief(pci_dev_t dev) +{ + u16 vendor, device; + u8 class, subclass; + + pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); + pci_read_config_word(dev, PCI_DEVICE_ID, &device); + pci_read_config_byte(dev, PCI_CLASS_CODE, &class); + pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass); + + printf("0x%.4x 0x%.4x %-23s 0x%.2x\n", + vendor, device, + pci_classes_str(class), subclass); +} + +/* + * Subroutine: PCI_Header_Show + * + * Description: Reads the header of the specified PCI device. + * + * Inputs: BusDevFunc Bus+Device+Function number + * + * Return: None + * + */ +void pci_header_show(pci_dev_t dev) +{ + u8 _byte, header_type; + u16 _word; + u32 _dword; + +#define PRINT(msg, type, reg) \ + pci_read_config_##type(dev, reg, &_##type); \ + printf(msg, _##type) + +#define PRINT2(msg, type, reg, func) \ + pci_read_config_##type(dev, reg, &_##type); \ + printf(msg, _##type, func(_##type)) + + pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); + + PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID); + PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID); + PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND); + PRINT (" status register = 0x%.4x\n", word, PCI_STATUS); + PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID); + PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE, + pci_classes_str); + PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE); + PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG); + PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE); + PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER); + PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE); + PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST); + PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0); + + switch (header_type & 0x03) { + case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */ + PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); + PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2); + PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3); + PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4); + PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5); + PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS); + PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID); + PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID); + PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS); + PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); + PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); + PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT); + PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT); + break; + + case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */ + + PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); + PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS); + PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS); + PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS); + PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER); + PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE); + PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT); + PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS); + PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE); + PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT); + PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE); + PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT); + PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32); + PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32); + PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16); + PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16); + PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1); + PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); + PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); + PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL); + break; + + case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */ + + PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST); + PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS); + PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS); + PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS); + PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS); + PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER); + PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0); + PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0); + PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1); + PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1); + PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0); + PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI); + PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0); + PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI); + PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1); + PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI); + PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1); + PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI); + PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); + PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); + PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL); + PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID); + PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID); + PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE); + break; + + default: + printf("unknown header\n"); + break; + } + +#undef PRINT +#undef PRINT2 +} + +/* Convert the "bus.device.function" identifier into a number. + */ +static pci_dev_t get_pci_dev(char* name) +{ + char cnum[12]; + int len, i, iold, n; + int bdfs[3] = {0,0,0}; + + len = strlen(name); + if (len > 8) + return -1; + for (i = 0, iold = 0, n = 0; i < len; i++) { + if (name[i] == '.') { + memcpy(cnum, &name[iold], i - iold); + cnum[i - iold] = '\0'; + bdfs[n++] = simple_strtoul(cnum, NULL, 16); + iold = i + 1; + } + } + strcpy(cnum, &name[iold]); + if (n == 0) + n = 1; + bdfs[n] = simple_strtoul(cnum, NULL, 16); + return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); +} + +static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length) +{ +#define DISP_LINE_LEN 16 + ulong i, nbytes, linebytes; + int rc = 0; + + if (length == 0) + length = 0x40 / size; /* Standard PCI configuration space */ + + /* Print the lines. + * once, and all accesses are with the specified bus width. + */ + nbytes = length * size; + do { + uint val4; + ushort val2; + u_char val1; + + printf("%08lx:", addr); + linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; + for (i=0; i 0); + + return (rc); +} + +static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value) +{ + if (size == 4) { + pci_write_config_dword(bdf, addr, value); + } + else if (size == 2) { + ushort val = value & 0xffff; + pci_write_config_word(bdf, addr, val); + } + else { + u_char val = value & 0xff; + pci_write_config_byte(bdf, addr, val); + } + return 0; +} + +static int +pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag) +{ + ulong i; + int nbytes; + extern char console_buffer[]; + uint val4; + ushort val2; + u_char val1; + + /* Print the address, followed by value. Then accept input for + * the next value. A non-converted value exits. + */ + do { + printf("%08lx:", addr); + if (size == 4) { + pci_read_config_dword(bdf, addr, &val4); + printf(" %08x", val4); + } + else if (size == 2) { + pci_read_config_word(bdf, addr, &val2); + printf(" %04x", val2); + } + else { + pci_read_config_byte(bdf, addr, &val1); + printf(" %02x", val1); + } + + nbytes = readline (" ? "); + if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { + /* pressed as only input, don't modify current + * location and move to next. "-" pressed will go back. + */ + if (incrflag) + addr += nbytes ? -size : size; + nbytes = 1; +#ifdef CONFIG_BOOT_RETRY_TIME + reset_cmd_timeout(); /* good enough to not time out */ +#endif + } +#ifdef CONFIG_BOOT_RETRY_TIME + else if (nbytes == -2) { + break; /* timed out, exit the command */ + } +#endif + else { + char *endp; + i = simple_strtoul(console_buffer, &endp, 16); + nbytes = endp - console_buffer; + if (nbytes) { +#ifdef CONFIG_BOOT_RETRY_TIME + /* good enough to not time out + */ + reset_cmd_timeout(); +#endif + pci_cfg_write (bdf, addr, size, i); + if (incrflag) + addr += size; + } + } + } while (nbytes); + + return 0; +} + +/* PCI Configuration Space access commands + * + * Syntax: + * pci display[.b, .w, .l] bus.device.function} [addr] [len] + * pci next[.b, .w, .l] bus.device.function [addr] + * pci modify[.b, .w, .l] bus.device.function [addr] + * pci write[.b, .w, .l] bus.device.function addr value + */ +int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr = 0, value = 0, size = 0; + pci_dev_t bdf = 0; + char cmd = 's'; + + if (argc > 1) + cmd = argv[1][0]; + + switch (cmd) { + case 'd': /* display */ + case 'n': /* next */ + case 'm': /* modify */ + case 'w': /* write */ + /* Check for a size specification. */ + size = cmd_get_data_size(argv[1], 4); + if (argc > 3) + addr = simple_strtoul(argv[3], NULL, 16); + if (argc > 4) + value = simple_strtoul(argv[4], NULL, 16); + case 'h': /* header */ + if (argc < 3) + goto usage; + if ((bdf = get_pci_dev(argv[2])) == -1) + return 1; + break; + default: /* scan bus */ + value = 1; /* short listing */ + bdf = 0; /* bus number */ + if (argc > 1) { + if (argv[argc-1][0] == 'l') { + value = 0; + argc--; + } + if (argc > 1) + bdf = simple_strtoul(argv[1], NULL, 16); + } + pciinfo(bdf, value); + return 0; + } + + switch (argv[1][0]) { + case 'h': /* header */ + pci_header_show(bdf); + return 0; + case 'd': /* display */ + return pci_cfg_display(bdf, addr, size, value); + case 'n': /* next */ + if (argc < 4) + goto usage; + return pci_cfg_modify(bdf, addr, size, value, 0); + case 'm': /* modify */ + if (argc < 4) + goto usage; + return pci_cfg_modify(bdf, addr, size, value, 1); + case 'w': /* write */ + if (argc < 5) + goto usage; + return pci_cfg_write(bdf, addr, size, value); + } + + return 1; + usage: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +/***************************************************/ + + +U_BOOT_CMD( + pci, 5, 1, do_pci, + "pci - list and access PCI Configuration Space\n", + "[bus] [long]\n" + " - short or long list of PCI devices on bus 'bus'\n" + "pci header b.d.f\n" + " - show header of PCI device 'bus.device.function'\n" + "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n" + " - display PCI configuration space (CFG)\n" + "pci next[.b, .w, .l] b.d.f address\n" + " - modify, read and keep CFG address\n" + "pci modify[.b, .w, .l] b.d.f address\n" + " - modify, auto increment CFG address\n" + "pci write[.b, .w, .l] b.d.f address value\n" + " - write to CFG address\n" +); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_PCI) */ + +#endif /* CONFIG_PCI */ diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c new file mode 100644 index 0000000..62446d4 --- /dev/null +++ b/common/cmd_pcmcia.c @@ -0,0 +1,3310 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * + * Lots of code copied from: + * + * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. + * (C) 1999-2000 Magnus Damm + * + * "The ExCA standard specifies that socket controllers should provide + * two IO and five memory windows per socket, which can be independently + * configured and positioned in the host address space and mapped to + * arbitrary segments of card address space. " - David A Hinds. 1999 + * + * This controller does _not_ meet the ExCA standard. + * + * m8xx pcmcia controller brief info: + * + 8 windows (attrib, mem, i/o) + * + up to two slots (SLOT_A and SLOT_B) + * + inputpins, outputpins, event and mask registers. + * - no offset register. sigh. + * + * Because of the lacking offset register we must map the whole card. + * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. + * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO + * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. + * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. + * They are maximum 64KByte each... + */ + +/* #define DEBUG 1 */ + +/* + * PCMCIA support + */ +#include +#include +#include +#include +#if defined(CONFIG_8xx) +#include +#endif +#if defined(CONFIG_LWMON) +#include +#endif +#ifdef CONFIG_PXA_PCMCIA +#include +#endif + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \ + ((CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)) + +int pcmcia_on (void); + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int pcmcia_off (void); +#endif + +#ifdef CONFIG_I82365 + +extern int i82365_init (void); +extern void i82365_exit (void); + +#else /* ! CONFIG_I82365 */ + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot); +#endif +static int hardware_enable (int slot); +static int voltage_set(int slot, int vcc, int vpp); + +#if (! defined(CONFIG_I82365)) && (! defined(CONFIG_PXA_PCMCIA)) +static u_int m8xx_get_graycode(u_int size); +#endif /* !CONFIG_I82365, !CONFIG_PXA_PCMCIA */ +#if 0 +static u_int m8xx_get_speed(u_int ns, u_int is_io); +#endif + +/* -------------------------------------------------------------------- */ + +#ifndef CONFIG_PXA_PCMCIA + +/* look up table for pgcrx registers */ + +static u_int *pcmcia_pgcrx[2] = { + &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra, + &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb, +}; +#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) + +#endif /* CONFIG_PXA_PCMCIA */ + +#endif /* CONFIG_I82365 */ + +#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) +static void print_funcid (int func); +static void print_fixed (volatile uchar *p); +static int identify (volatile uchar *p); +static int check_ide_device (int slot); +#endif /* CONFIG_IDE_8xx_PCCARD, CONFIG_PXA_PCMCIA */ + +const char *indent = "\t "; + +/* -------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) + +int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; + + if (argc != 2) { + printf ("Usage: pinit {on | off}\n"); + return 1; + } + if (strcmp(argv[1],"on") == 0) { + rcode = pcmcia_on (); + } else if (strcmp(argv[1],"off") == 0) { + rcode = pcmcia_off (); + } else { + printf ("Usage: pinit {on | off}\n"); + return 1; + } + + return rcode; +} +#endif /* CFG_CMD_PCMCIA */ + +/* -------------------------------------------------------------------- */ + +#ifdef CONFIG_I82365 +int pcmcia_on (void) +{ + u_int rc; + + debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + rc = i82365_init(); + + if (rc == 0) { + rc = check_ide_device(0); + } + + return (rc); +} +#else + +#ifndef CONFIG_PXA_PCMCIA + +#ifdef CONFIG_HMI10 +# define HMI10_FRAM_TIMING (PCMCIA_SHT(2) | PCMCIA_SST(2) | PCMCIA_SL(4)) +#endif +#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU) +# define CFG_PCMCIA_TIMING (PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12)) +#else +# define CFG_PCMCIA_TIMING (PCMCIA_SHT(2) | PCMCIA_SST(4) | PCMCIA_SL(9)) +#endif + +int pcmcia_on (void) +{ + int i; + u_long reg, base; + pcmcia_win_t *win; + u_int slotbit; + u_int rc, slot; + + debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + /* intialize the fixed memory windows */ + win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); + base = CFG_PCMCIA_MEM_ADDR; + + if((reg = m8xx_get_graycode(CFG_PCMCIA_MEM_SIZE)) == -1) { + printf ("Cannot set window size to 0x%08x\n", + CFG_PCMCIA_MEM_SIZE); + return (1); + } + + slotbit = PCMCIA_SLOT_x; + for (i=0; ibr = base; + +#if (PCMCIA_SOCKETS_NO == 2) + if (i == 4) /* Another slot starting from win 4 */ + slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B); +#endif + switch (i) { +#ifdef CONFIG_IDE_8xx_PCCARD + case 4: +#ifdef CONFIG_HMI10 + { /* map FRAM area */ + win->or = ( PCMCIA_BSIZE_256K + | PCMCIA_PPS_8 + | PCMCIA_PRS_ATTR + | slotbit + | PCMCIA_PV + | HMI10_FRAM_TIMING ); + break; + } +#endif + case 0: { /* map attribute memory */ + win->or = ( PCMCIA_BSIZE_64M + | PCMCIA_PPS_8 + | PCMCIA_PRS_ATTR + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } + case 5: + case 1: { /* map I/O window for data reg */ + win->or = ( PCMCIA_BSIZE_1K + | PCMCIA_PPS_16 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } + case 6: + case 2: { /* map I/O window for cmd/ctrl reg block */ + win->or = ( PCMCIA_BSIZE_1K + | PCMCIA_PPS_8 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } +#endif /* CONFIG_IDE_8xx_PCCARD */ +#ifdef CONFIG_HMI10 + case 3: { /* map I/O window for 4xUART data/ctrl */ + win->br += 0x40000; + win->or = ( PCMCIA_BSIZE_256K + | PCMCIA_PPS_8 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } +#endif /* CONFIG_HMI10 */ + default: /* set to not valid */ + win->or = 0; + break; + } + + debug ("MemWin %d: PBR 0x%08lX POR %08lX\n", + i, win->br, win->or); + base += CFG_PCMCIA_MEM_SIZE; + ++win; + } + + for (i=0, rc=0, slot=_slot_; iim_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_); + ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* turn off interrupt and disable CxOE */ + PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE; + + /* turn off memory windows */ + win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); + + for (i=0; ior = 0; + ++win; + } + + /* turn off voltage */ + voltage_set(_slot_, 0, 0); + + /* disable external hardware */ + printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n"); + hardware_disable(_slot_); + return 0; +} + +#endif /* CONFIG_PXA_PCMCIA */ + +#endif /* CONFIG_I82365 */ + +#ifdef CONFIG_PXA_PCMCIA +static int pcmcia_off (void) +{ + return 0; +} +#endif + +#endif /* CFG_CMD_PCMCIA */ + +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) + +#define MAX_TUPEL_SZ 512 +#define MAX_FEATURES 4 + +int ide_devices_found; +static int check_ide_device (int slot) +{ + volatile uchar *ident = NULL; + volatile uchar *feature_p[MAX_FEATURES]; + volatile uchar *p, *start, *addr; + int n_features = 0; + uchar func_id = ~0; + uchar code, len; + ushort config_base = 0; + int found = 0; + int i; + + addr = (volatile uchar *)(CFG_PCMCIA_MEM_ADDR + + CFG_PCMCIA_MEM_SIZE * (slot * 4)); + debug ("PCMCIA MEM: %08lX\n", (ulong)addr); + + start = p = (volatile uchar *) addr; + + while ((p - start) < MAX_TUPEL_SZ) { + + code = *p; p += 2; + + if (code == 0xFF) { /* End of chain */ + break; + } + + len = *p; p += 2; +#if defined(DEBUG) && (DEBUG > 1) + { volatile uchar *q = p; + printf ("\nTuple code %02x length %d\n\tData:", + code, len); + + for (i = 0; i < len; ++i) { + printf (" %02x", *q); + q+= 2; + } + } +#endif /* DEBUG */ + switch (code) { + case CISTPL_VERS_1: + ident = p + 4; + break; + case CISTPL_FUNCID: + /* Fix for broken SanDisk which may have 0x80 bit set */ + func_id = *p & 0x7F; + break; + case CISTPL_FUNCE: + if (n_features < MAX_FEATURES) + feature_p[n_features++] = p; + break; + case CISTPL_CONFIG: + config_base = (*(p+6) << 8) + (*(p+4)); + debug ("\n## Config_base = %04x ###\n", config_base); + default: + break; + } + p += 2 * len; + } + + found = identify (ident); + + if (func_id != ((uchar)~0)) { + print_funcid (func_id); + + if (func_id == CISTPL_FUNCID_FIXED) + found = 1; + else + return (1); /* no disk drive */ + } + + for (i=0; i only valid for ARGOSY D5!!! */ + *((uchar *)(addr + config_base)) = 1; +#endif +#if 0 + printf("\n## Config_base = %04x ###\n", config_base); + printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base); + printf("Card Configuration and Status Register: %02x\n", readb(addr + config_base + 2)); + printf("Pin Replacement Register Register: %02x\n", readb(addr + config_base + 4)); + printf("Socket and Copy Register: %02x\n", readb(addr + config_base + 6)); +#endif + return (0); +} +#endif /* CONFIG_IDE_8xx_PCCARD */ + +/* -------------------------------------------------------------------- */ + + +/* -------------------------------------------------------------------- */ +/* board specific stuff: */ +/* voltage_set(), hardware_enable() and hardware_disable() */ +/* -------------------------------------------------------------------- */ + +/* -------------------------------------------------------------------- */ +/* RPX Boards from Embedded Planet */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) + +/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. + * SYPCR is write once only, therefore must the slowest memory be faster + * than the bus monitor or we will get a machine check due to the bus timeout. + */ + +#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" + +#undef PCMCIA_BMT_LIMIT +#define PCMCIA_BMT_LIMIT (6*8) + +static int voltage_set(int slot, int vcc, int vpp) +{ + u_long reg = 0; + + switch(vcc) { + case 0: break; + case 33: reg |= BCSR1_PCVCTL4; break; + case 50: reg |= BCSR1_PCVCTL5; break; + default: return 1; + } + + switch(vpp) { + case 0: break; + case 33: + case 50: + if(vcc == vpp) + reg |= BCSR1_PCVCTL6; + else + return 1; + break; + case 120: + reg |= BCSR1_PCVCTL7; + default: return 1; + } + + if(vcc == 120) + return 1; + + /* first, turn off all power */ + + *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 + | BCSR1_PCVCTL6 | BCSR1_PCVCTL7); + + /* enable new powersettings */ + + *((uint *)RPX_CSR_ADDR) |= reg; + + return 0; +} + +#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V +static int hardware_enable (int slot) +{ + return 0; /* No hardware to enable */ +} +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + return 0; /* No hardware to disable */ +} +#endif /* CFG_CMD_PCMCIA */ +#endif /* CONFIG_RPXCLASSIC */ + +/* -------------------------------------------------------------------- */ +/* (F)ADS Boards from Motorola */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_ADS) || defined(CONFIG_FADS) + +#ifdef CONFIG_ADS +#define PCMCIA_BOARD_MSG "ADS" +#define PCMCIA_GLITCHY_CD /* My ADS board needs this */ +#else +#define PCMCIA_BOARD_MSG "FADS" +#endif + +static int voltage_set(int slot, int vcc, int vpp) +{ + u_long reg = 0; + + switch(vpp) { + case 0: reg = 0; break; + case 50: reg = 1; break; + case 120: reg = 2; break; + default: return 1; + } + + switch(vcc) { + case 0: reg = 0; break; +#ifdef CONFIG_ADS + case 50: reg = BCSR1_PCCVCCON; break; +#endif +#ifdef CONFIG_FADS + case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break; + case 50: reg = BCSR1_PCCVCC1; break; +#endif + default: return 1; + } + + /* first, turn off all power */ + +#ifdef CONFIG_ADS + *((uint *)BCSR1) |= BCSR1_PCCVCCON; +#endif +#ifdef CONFIG_FADS + *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1); +#endif + *((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK; + + /* enable new powersettings */ + +#ifdef CONFIG_ADS + *((uint *)BCSR1) &= ~reg; +#endif +#ifdef CONFIG_FADS + *((uint *)BCSR1) |= reg; +#endif + + *((uint *)BCSR1) |= reg << 20; + + return 0; +} + +#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V + +static int hardware_enable(int slot) +{ + *((uint *)BCSR1) &= ~BCSR1_PCCEN; + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + *((uint *)BCSR1) &= ~BCSR1_PCCEN; + return 0; +} +#endif /* CFG_CMD_PCMCIA */ + +#endif /* (F)ADS */ + +/* -------------------------------------------------------------------- */ +/* TQM8xxL Boards by TQ Components */ +/* SC8xx Boards by SinoVee Microsystems */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx) + +#if defined(CONFIG_TQM8xxL) +#define PCMCIA_BOARD_MSG "TQM8xxL" +#endif +#if defined(CONFIG_SVM_SC8xx) +#define PCMCIA_BOARD_MSG "SC8xx" +#endif + +static int hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(slot); + pcmp->pcmc_per &= ~PCMCIA_MASK(slot); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ +#ifndef NSCU_OE_INV + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ +#endif + PCMCIA_PGCRX(slot) = reg; + udelay(500); + +#ifndef CONFIG_HMI10 +#ifndef CONFIG_NSCU + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable + */ + immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004); + immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004); + /* remove all power */ + + immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004); +#endif +#else /* CONFIG_HMI10 */ + /* + * Configure Port B pins for + * 5 Volts Enable and 3 Volts enable + */ + immap->im_cpm.cp_pbpar &= ~(0x00000300); + + /* remove all power */ + immap->im_cpm.cp_pbdat |= 0x00000300; +#endif /* CONFIG_HMI10 */ + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); +#ifndef CONFIG_HMI10 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { +#else + if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { +#endif /* CONFIG_HMI10 */ + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); +#ifndef CONFIG_NSCU + if ((reg & mask) == mask) { +#ifndef CONFIG_HMI10 + immap->im_ioport.iop_pcdat |= 0x0004; +#else + immap->im_cpm.cp_pbdat &= ~(0x0000100); +#endif /* CONFIG_HMI10 */ + puts (" 5.0V card found: "); + } else { +#ifndef CONFIG_HMI10 + immap->im_ioport.iop_pcdat |= 0x0002; +#else + immap->im_cpm.cp_pbdat &= ~(0x0000200); +#endif /* CONFIG_HMI10 */ + puts (" 3.3V card found: "); + } +#ifndef CONFIG_HMI10 + immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); +#else + immap->im_cpm.cp_pbdir |= 0x00000300; +#endif /* CONFIG_HMI10 */ +#else + if ((reg & mask) == mask) { + puts (" 5.0V card found: "); + } else { + puts (" 3.3V card found: "); + } +#endif +#if 0 + /* VCC switch error flag, PCMCIA slot INPACK_ pin */ + cp->cp_pbdir &= ~(0x0020 | 0x0010); + cp->cp_pbpar &= ~(0x0020 | 0x0010); + udelay(500000); +#endif + udelay(1000); + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ +#ifndef NSCU_OE_INV + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ +#else + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ +#endif + PCMCIA_PGCRX(slot) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + +#ifndef CONFIG_HMI10 +#ifndef CONFIG_NSCU + /* remove all power */ + immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004); +#endif +#else /* CONFIG_HMI10 */ + immap->im_cpm.cp_pbdat |= 0x00000300; +#endif /* CONFIG_HMI10 */ + + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ +#ifndef NSCU_OE_INV + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ +#endif + PCMCIA_PGCRX(slot) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + +#ifdef CONFIG_NSCU +static int voltage_set(int slot, int vcc, int vpp) +{ + return 0; +} +#else +static int voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ +#ifndef NSCU_OE_INV + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ +#else + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ +#endif + PCMCIA_PGCRX(slot) = reg; + udelay(500); + +#ifndef CONFIG_HMI10 + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn off all power + */ + debug ("PCMCIA power OFF\n"); + immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004); + immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004); + immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004); + + reg = 0; + switch(vcc) { + case 0: break; + case 33: reg |= 0x0002; break; + case 50: reg |= 0x0004; break; + default: goto done; + } +#else /* CONFIG_HMI10 */ + /* + * Configure Port B pins for + * 5 Volts Enable and 3 Volts enable, + * Turn off all power + */ + debug ("PCMCIA power OFF\n"); + immap->im_cpm.cp_pbpar &= ~(0x00000300); + /* remove all power */ + + immap->im_cpm.cp_pbdat |= 0x00000300; + + reg = 0; + switch(vcc) { + case 0: break; + case 33: reg |= 0x00000200; break; + case 50: reg |= 0x00000100; break; + default: goto done; +} +#endif /* CONFIG_HMI10 */ + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + +#ifndef CONFIG_HMI10 + immap->im_ioport.iop_pcdat |= reg; + immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); +#else + immap->im_cpm.cp_pbdat &= !reg; + immap->im_cpm.cp_pbdir |= 0x00000300; +#endif /* CONFIG_HMI10 */ + if (reg) { +#ifndef CONFIG_HMI10 + debug ("PCMCIA powered at %sV\n", + (reg&0x0004) ? "5.0" : "3.3"); +#else + debug ("PCMCIA powered at %sV\n", + (reg&0x00000200) ? "5.0" : "3.3"); +#endif /* CONFIG_HMI10 */ + } else { + debug ("PCMCIA powered down\n"); + } + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ +#ifndef NSCU_OE_INV + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ +#else + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ +#endif + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} +#endif + +#endif /* TQM8xxL */ + + +/* -------------------------------------------------------------------- */ +/* LWMON Board */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_LWMON) + +#define PCMCIA_BOARD_MSG "LWMON" + +/* #define's for MAX1604 Power Switch */ +#define MAX1604_OP_SUS 0x80 +#define MAX1604_VCCBON 0x40 +#define MAX1604_VCC_35 0x20 +#define MAX1604_VCCBHIZ 0x10 +#define MAX1604_VPPBON 0x08 +#define MAX1604_VPPBPBPGM 0x04 +#define MAX1604_VPPBHIZ 0x02 +/* reserved 0x01 */ + +static int hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + uchar val; + + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + /* Switch on PCMCIA port in PIC register 0x60 */ + reg = pic_read (0x60); + debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); + reg &= ~0x10; + /* reg |= 0x08; Vpp not needed */ + pic_write (0x60, reg); +#ifdef DEBUG + reg = pic_read (0x60); + printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); +#endif + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + if ((reg & mask) == mask) { + val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */ + puts (" 5.0V card found: "); + } else { + val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */ + puts (" 3.3V card found: "); + } + + /* switch VCC on */ + val |= MAX1604_OP_SUS | MAX1604_VCCBON; + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + + udelay(500000); + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + uchar val; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* remove all power, put output in high impedance state */ + val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + /* Switch off PCMCIA port in PIC register 0x60 */ + reg = pic_read (0x60); + debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); + reg |= 0x10; + reg &= ~0x08; + pic_write (0x60, reg); +#ifdef DEBUG + reg = pic_read (0x60); + printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); +#endif + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +static int voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + uchar val; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Turn off all power (switch to high impedance) + */ + debug ("PCMCIA power OFF\n"); + val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + + val = 0; + switch(vcc) { + case 0: break; + case 33: val = MAX1604_VCC_35; break; + case 50: break; + default: goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + if (val) { + debug ("PCMCIA powered at %sV\n", + (val & MAX1604_VCC_35) ? "3.3" : "5.0"); + } else { + debug ("PCMCIA powered down\n"); + } + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* LWMON */ + +/* -------------------------------------------------------------------- */ +/* GTH board by Corelatus AB */ +/* -------------------------------------------------------------------- */ +#if defined(CONFIG_GTH) + +#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH" + +static int voltage_set (int slot, int vcc, int vpp) +{ /* Do nothing */ + return 0; +} + +static int hardware_enable (int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: GTH Slot %c\n", 'A' + slot); + + immap = (immap_t *) CFG_IMMR; + sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm)); + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX (_slot_) = reg; + udelay (500); + + /* + * Make sure there is a card in the slot, + * then configure the interface. + */ + udelay (10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__, __FUNCTION__, + &(pcmp->pcmc_pipr), pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & 0x98000000) { + printf (" No Card found\n"); + return (1); + } + + mask = PCMCIA_VS1 (slot) | PCMCIA_VS2 (slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg & PCMCIA_VS1 (slot)) ? "n" : "ff", + (reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX (_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX (_slot_) = reg; + + udelay (250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return 0; +} +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + return 0; /* No hardware to disable */ +} +#endif /* CFG_CMD_PCMCIA */ +#endif /* CONFIG_GTH */ + +/* -------------------------------------------------------------------- */ +/* ICU862 Boards by Cambridge Broadband Ltd. */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_ICU862) + +#define PCMCIA_BOARD_MSG "ICU862" + +static void cfg_port_B (void); + +static int hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, pipr, mask; + int i; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */ + cfg_port_B (); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + pipr = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + pipr, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + + reg = cp->cp_pbdat; + if ((pipr & mask) == mask) { + reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ + TPS2205_VCC3); /* 3V off */ + reg &= ~(TPS2205_VCC5); /* 5V on */ + puts (" 5.0V card found: "); + } else { + reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ + TPS2205_VCC5); /* 5V off */ + reg &= ~(TPS2205_VCC3); /* 3V on */ + puts (" 3.3V card found: "); + } + + debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n", + reg, + (reg & TPS2205_VCC3) ? "off" : "on", + (reg & TPS2205_VCC5) ? "off" : "on", + (reg & TPS2205_VPP_PGM) ? "off" : "on", + (reg & TPS2205_VPP_VCC) ? "off" : "on" ); + + cp->cp_pbdat = reg; + + /* Wait 500 ms; use this to check for over-current */ + for (i=0; i<5000; ++i) { + if ((cp->cp_pbdat & TPS2205_OC) == 0) { + printf (" *** Overcurrent - Safety shutdown ***\n"); + cp->cp_pbdat &= ~(TPS2205_SHDN); + return (1); + } + udelay (100); + } + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* Shut down */ + cp->cp_pbdat &= ~(TPS2205_SHDN); + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +static int voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ + debug ("PCMCIA power OFF\n"); + cfg_port_B (); /* Enables switch, but all in Hi-Z */ + + reg = cp->cp_pbdat; + + switch(vcc) { + case 0: break; /* Switch off */ + case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */ + case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */ + default: goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + cp->cp_pbdat = reg; + +#ifdef DEBUG + { + char *s; + + if ((reg & TPS2205_VCC3) == 0) { + s = "at 3.3V"; + } else if ((reg & TPS2205_VCC5) == 0) { + s = "at 5.0V"; + } else { + s = "down"; + } + printf ("PCMCIA powered %s\n", s); + } +#endif + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +static void cfg_port_B (void) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + uint reg; + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure Port B for TPS2205 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ + reg = cp->cp_pbdat; + reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ + TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */ + TPS2205_SHDN); /* enable switch */ + cp->cp_pbdat = reg; + + cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS); + + reg = cp->cp_pbdir & ~(TPS2205_INPUTS); + cp->cp_pbdir = reg | TPS2205_OUTPUTS; + + debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", + cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); +} + +#endif /* ICU862 */ + + +/* -------------------------------------------------------------------- */ +/* C2MON Boards by TTTech Computertechnik AG */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_C2MON) + +#define PCMCIA_BOARD_MSG "C2MON" + +static void cfg_ports (void); + +static int hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, pipr, mask; + ushort sreg; + int i; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ + cfg_ports (); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + pipr = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + pipr, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + + sreg = immap->im_ioport.iop_pcdat; + if ((pipr & mask) == mask) { + sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */ + TPS2211_VCCD1); /* 5V on */ + sreg &= ~(TPS2211_VCCD0); /* 3V off */ + puts (" 5.0V card found: "); + } else { + sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */ + TPS2211_VCCD0); /* 3V on */ + sreg &= ~(TPS2211_VCCD1); /* 5V off */ + puts (" 3.3V card found: "); + } + + debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n", + sreg, + ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off", + (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) ? "on" : "off" + ); + + immap->im_ioport.iop_pcdat = sreg; + + /* Wait 500 ms; use this to check for over-current */ + for (i=0; i<5000; ++i) { + if ((cp->cp_pbdat & TPS2211_OC) == 0) { + printf (" *** Overcurrent - Safety shutdown ***\n"); + immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1); + return (1); + } + udelay (100); + } + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + /* ALl voltages off / Hi-Z */ + immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 | + TPS2211_VCCD0 | TPS2211_VCCD1 ); + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +static int voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + ushort sreg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ + debug ("PCMCIA power OFF\n"); + cfg_ports (); /* Enables switch, but all in Hi-Z */ + + sreg = immap->im_ioport.iop_pcdat; + sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */ + + switch(vcc) { + case 0: break; /* Switch off */ + case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */ + sreg &= ~TPS2211_VCCD1; + break; + case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */ + sreg |= TPS2211_VCCD1; + break; + default: goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + immap->im_ioport.iop_pcdat = sreg; + +#ifdef DEBUG + { + char *s; + + if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) { + s = "at 3.3V"; + } else if (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) { + s = "at 5.0V"; + } else { + s = "down"; + } + printf ("PCMCIA powered %s\n", s); + } +#endif + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +static void cfg_ports (void) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + ushort sreg; + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure Port C for TPS2211 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ + sreg = immap->im_ioport.iop_pcdat; + sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1); /* VAVPP => Hi-Z */ + sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1); /* 3V and 5V off */ + immap->im_ioport.iop_pcdat = sreg; + + immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS); + immap->im_ioport.iop_pcdir |= TPS2211_OUTPUTS; + + debug ("Set Port C: PAR: %04x DIR: %04x DAT: %04x\n", + immap->im_ioport.iop_pcpar, + immap->im_ioport.iop_pcdir, + immap->im_ioport.iop_pcdat); + + /* + * Configure Port B for TPS2211 PC-Card Power-Interface Switch + * + * Over-Current Input only + */ + cp->cp_pbpar &= ~(TPS2211_INPUTS); + cp->cp_pbdir &= ~(TPS2211_INPUTS); + + debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", + cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); +} + +#endif /* C2MON */ + +/* -------------------------------------------------------------------- */ +/* MBX board from Morotola */ +/* -------------------------------------------------------------------- */ + +#if defined( CONFIG_MBX ) +#include <../board/mbx8xx/csr.h> + +/* A lot of this has been taken from the RPX code in this file it works from me. + I have added the voltage selection for the MBX board. */ + +/* MBX voltage bit in control register #2 */ +#define CR2_VPP12 ((uchar)0x10) +#define CR2_VPPVDD ((uchar)0x20) +#define CR2_VDD5 ((uchar)0x40) +#define CR2_VDD3 ((uchar)0x80) + +#define PCMCIA_BOARD_MSG "MBX860" + +static int voltage_set (int slot, int vcc, int vpp) +{ + uchar reg = 0; + + debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10); + + switch (vcc) { + case 0: + break; + case 33: + reg |= CR2_VDD3; + break; + case 50: + reg |= CR2_VDD5; + break; + default: + return 1; + } + + switch (vpp) { + case 0: + break; + case 33: + case 50: + if (vcc == vpp) { + reg |= CR2_VPPVDD; + } else { + return 1; + } + break; + case 120: + reg |= CR2_VPP12; + break; + default: + return 1; + } + + /* first, turn off all power */ + MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL); + + /* enable new powersettings */ + MBX_CSR2 |= reg; + debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2); + + return (0); +} + +static int hardware_enable (int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", + 'A' + slot); + + udelay (10000); + + immap = (immap_t *) CFG_IMMR; + sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm)); + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX (_slot_) = reg; + udelay (500); + + /* remove all power */ + voltage_set (slot, 0, 0); + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); +#ifndef CONFIG_HMI10 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { +#else + if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { +#endif /* CONFIG_HMI10 */ + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, + (reg & PCMCIA_VS1 (slot)) ? "n" : "ff", + (reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); + + if ((reg & mask) == mask) { + voltage_set (_slot_, 50, 0); + printf (" 5.0V card found: "); + } else { + voltage_set (_slot_, 33, 0); + printf (" 3.3V card found: "); + } + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX (_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX (_slot_) = reg; + + udelay (250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable (int slot) +{ + return 0; /* No hardware to disable */ +} +#endif /* CFG_CMD_PCMCIA */ +#endif /* CONFIG_MBX */ +/* -------------------------------------------------------------------- */ +/* R360MPI Board */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_R360MPI) + +#define PCMCIA_BOARD_MSG "R360MPI" + + +static int hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Ports A, B & C pins for + * 5 Volts Enable and 3 Volts enable + */ + immap->im_ioport.iop_pcpar &= ~(0x0400); + immap->im_ioport.iop_pcso &= ~(0x0400);/* + immap->im_ioport.iop_pcdir |= 0x0400;*/ + + immap->im_ioport.iop_papar &= ~(0x0200);/* + immap->im_ioport.iop_padir |= 0x0200;*/ +#if 0 + immap->im_ioport.iop_pbpar &= ~(0xC000); + immap->im_ioport.iop_pbdir &= ~(0xC000); +#endif + /* remove all power */ + + immap->im_ioport.iop_pcdat |= 0x0400; + immap->im_ioport.iop_padat |= 0x0200; + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + if ((reg & mask) == mask) { + immap->im_ioport.iop_pcdat &= ~(0x4000); + puts (" 5.0V card found: "); + } else { + immap->im_ioport.iop_padat &= ~(0x0002); + puts (" 3.3V card found: "); + } + immap->im_ioport.iop_pcdir |= 0x0400; + immap->im_ioport.iop_padir |= 0x0200; +#if 0 + /* VCC switch error flag, PCMCIA slot INPACK_ pin */ + cp->cp_pbdir &= ~(0x0020 | 0x0010); + cp->cp_pbpar &= ~(0x0020 | 0x0010); + udelay(500000); +#endif + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* remove all power */ + immap->im_ioport.iop_pcdat |= 0x0400; + immap->im_ioport.iop_padat |= 0x0200; + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +static int voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Ports A & C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn off all power + */ + debug ("PCMCIA power OFF\n"); + immap->im_ioport.iop_pcpar &= ~(0x0400); + immap->im_ioport.iop_pcso &= ~(0x0400);/* + immap->im_ioport.iop_pcdir |= 0x0400;*/ + + immap->im_ioport.iop_papar &= ~(0x0200);/* + immap->im_ioport.iop_padir |= 0x0200;*/ + + immap->im_ioport.iop_pcdat |= 0x0400; + immap->im_ioport.iop_padat |= 0x0200; + + reg = 0; + switch(vcc) { + case 0: break; + case 33: reg |= 0x0200; break; + case 50: reg |= 0x0400; break; + default: goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + if (reg & 0x0200) + immap->im_ioport.iop_pcdat &= !reg; + if (reg & 0x0400) + immap->im_ioport.iop_padat &= !reg; + immap->im_ioport.iop_pcdir |= 0x0200; + immap->im_ioport.iop_padir |= 0x0400; + if (reg) { + debug ("PCMCIA powered at %sV\n", + (reg&0x0400) ? "5.0" : "3.3"); + } else { + debug ("PCMCIA powered down\n"); + } + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* R360MPI */ + +/* -------------------------------------------------------------------- */ +/* KUP4K and KUP4X Boards */ +/* -------------------------------------------------------------------- */ +#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) + +#define PCMCIA_BOARD_MSG "KUP" + +#define KUP4K_PCMCIA_B_3V3 (0x00020000) + +static int hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(slot); + pcmp->pcmc_per &= ~PCMCIA_MASK(slot); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + udelay(2500); + + /* + * Configure Port B pins for + * 3 Volts enable + */ + if (slot) { /* Slot A is built-in */ + cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; + cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; + /* remove all power */ + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ + } + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot); + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + if ((reg & mask) == mask) { + puts (" 5.0V card found: NOT SUPPORTED !!!\n"); + } else { + if(slot) + cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; + puts (" 3.3V card found: "); + } +#if 0 + /* VCC switch error flag, PCMCIA slot INPACK_ pin */ + cp->cp_pbdir &= ~(0x0020 | 0x0010); + cp->cp_pbpar &= ~(0x0020 | 0x0010); + udelay(500000); +#endif + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* remove all power */ + if (slot) + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +static int voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " \ + PCMCIA_BOARD_MSG \ + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + if (!slot) /* Slot A is not configurable */ + return 0; + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug ("PCMCIA power OFF\n"); + /* + * Configure Port B pins for + * 3 Volts enable + */ + cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; + cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; + /* remove all power */ + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ + + switch(vcc) { + case 0: break; + case 33: + cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; + debug ("PCMCIA powered at 3.3V\n"); + break; + case 50: + debug ("PCMCIA: 5Volt vcc not supported\n"); + break; + default: + puts("PCMCIA: vcc not supported"); + break; + } + udelay(10000); + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4))) + ? "only 5 V --> NOT SUPPORTED" + : "can do 3.3V"); + + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* KUP4K || KUP4X */ + + +/* -------------------------------------------------------------------- */ +/* End of Board Specific Stuff */ +/* -------------------------------------------------------------------- */ + + +/* -------------------------------------------------------------------- */ +/* MPC8xx Specific Stuff - should go to MPC8xx directory */ +/* -------------------------------------------------------------------- */ + +/* + * Search this table to see if the windowsize is + * supported... + */ + +#define M8XX_SIZES_NO 32 + +static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] = +{ 0x00000001, 0x00000002, 0x00000008, 0x00000004, + 0x00000080, 0x00000040, 0x00000010, 0x00000020, + 0x00008000, 0x00004000, 0x00001000, 0x00002000, + 0x00000100, 0x00000200, 0x00000800, 0x00000400, + + 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x01000000, 0x02000000, 0xffffffff, 0x04000000, + 0x00010000, 0x00020000, 0x00080000, 0x00040000, + 0x00800000, 0x00400000, 0x00100000, 0x00200000 }; + + +/* -------------------------------------------------------------------- */ + +#if ( ! defined(CONFIG_I82365) && ! defined(CONFIG_PXA_PCMCIA) ) + +static u_int m8xx_get_graycode(u_int size) +{ + u_int k; + + for (k = 0; k < M8XX_SIZES_NO; k++) { + if(m8xx_size_to_gray[k] == size) + break; + } + + if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) + k = -1; + + return k; +} + +#endif /* CONFIG_I82365 */ + +/* -------------------------------------------------------------------- */ + +#if 0 +static u_int m8xx_get_speed(u_int ns, u_int is_io) +{ + u_int reg, clocks, psst, psl, psht; + + if(!ns) { + + /* + * We get called with IO maps setup to 0ns + * if not specified by the user. + * They should be 255ns. + */ + + if(is_io) + ns = 255; + else + ns = 100; /* fast memory if 0 */ + } + + /* + * In PSST, PSL, PSHT fields we tell the controller + * timing parameters in CLKOUT clock cycles. + * CLKOUT is the same as GCLK2_50. + */ + +/* how we want to adjust the timing - in percent */ + +#define ADJ 180 /* 80 % longer accesstime - to be sure */ + + clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000; + clocks = (clocks * ADJ) / (100*1000); + + if(clocks >= PCMCIA_BMT_LIMIT) { + DEBUG(0, "Max access time limit reached\n"); + clocks = PCMCIA_BMT_LIMIT-1; + } + + psst = clocks / 7; /* setup time */ + psht = clocks / 7; /* hold time */ + psl = (clocks * 5) / 7; /* strobe length */ + + psst += clocks - (psst + psht + psl); + + reg = psst << 12; + reg |= psl << 7; + reg |= psht << 16; + + return reg; +} +#endif + +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) +static void print_funcid (int func) +{ + puts (indent); + switch (func) { + case CISTPL_FUNCID_MULTI: + puts (" Multi-Function"); + break; + case CISTPL_FUNCID_MEMORY: + puts (" Memory"); + break; + case CISTPL_FUNCID_SERIAL: + puts (" Serial Port"); + break; + case CISTPL_FUNCID_PARALLEL: + puts (" Parallel Port"); + break; + case CISTPL_FUNCID_FIXED: + puts (" Fixed Disk"); + break; + case CISTPL_FUNCID_VIDEO: + puts (" Video Adapter"); + break; + case CISTPL_FUNCID_NETWORK: + puts (" Network Adapter"); + break; + case CISTPL_FUNCID_AIMS: + puts (" AIMS Card"); + break; + case CISTPL_FUNCID_SCSI: + puts (" SCSI Adapter"); + break; + default: + puts (" Unknown"); + break; + } + puts (" Card\n"); +} +#endif /* CONFIG_IDE_8xx_PCCARD */ + +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) +static void print_fixed (volatile uchar *p) +{ + if (p == NULL) + return; + + puts(indent); + + switch (*p) { + case CISTPL_FUNCE_IDE_IFACE: + { uchar iface = *(p+2); + + puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown"); + puts (" interface "); + break; + } + case CISTPL_FUNCE_IDE_MASTER: + case CISTPL_FUNCE_IDE_SLAVE: + { uchar f1 = *(p+2); + uchar f2 = *(p+4); + + puts ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]"); + + if (f1 & CISTPL_IDE_UNIQUE) + puts (" [unique]"); + + puts ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]"); + + if (f2 & CISTPL_IDE_HAS_SLEEP) + puts (" [sleep]"); + + if (f2 & CISTPL_IDE_HAS_STANDBY) + puts (" [standby]"); + + if (f2 & CISTPL_IDE_HAS_IDLE) + puts (" [idle]"); + + if (f2 & CISTPL_IDE_LOW_POWER) + puts (" [low power]"); + + if (f2 & CISTPL_IDE_REG_INHIBIT) + puts (" [reg inhibit]"); + + if (f2 & CISTPL_IDE_HAS_INDEX) + puts (" [index]"); + + if (f2 & CISTPL_IDE_IOIS16) + puts (" [IOis16]"); + + break; + } + } + putc ('\n'); +} +#endif /* CONFIG_IDE_8xx_PCCARD */ + +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) + +#define MAX_IDENT_CHARS 64 +#define MAX_IDENT_FIELDS 4 + +static uchar *known_cards[] = { + (uchar *)"ARGOSY PnPIDE D5", + NULL +}; + +static int identify (volatile uchar *p) +{ + uchar id_str[MAX_IDENT_CHARS]; + uchar data; + uchar *t; + uchar **card; + int i, done; + + if (p == NULL) + return (0); /* Don't know */ + + t = id_str; + done =0; + + for (i=0; i<=4 && !done; ++i, p+=2) { + while ((data = *p) != '\0') { + if (data == 0xFF) { + done = 1; + break; + } + *t++ = data; + if (t == &id_str[MAX_IDENT_CHARS-1]) { + done = 1; + break; + } + p += 2; + } + if (!done) + *t++ = ' '; + } + *t = '\0'; + while (--t > id_str) { + if (*t == ' ') + *t = '\0'; + else + break; + } + puts ((char *)id_str); + putc ('\n'); + + for (card=known_cards; *card; ++card) { + debug ("## Compare against \"%s\"\n", *card); + if (strcmp((char *)*card, (char *)id_str) == 0) { /* found! */ + debug ("## CARD FOUND ##\n"); + return (1); + } + } + + return (0); /* don't know */ +} +#endif /* CONFIG_IDE_8xx_PCCARD */ + +/* -------------------------------------------------------------------- */ +/* NETTA board by Intracom S.A. */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_NETTA) + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +#define PCMCIA_BOARD_MSG "NETTA" + +static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) }; + +static void cfg_vppd(int no) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) + return; + + mask = vppd_masks[no]; + + immap->im_ioport.iop_papar &= ~mask; + immap->im_ioport.iop_paodr &= ~mask; + immap->im_ioport.iop_padir |= mask; +} + +static void set_vppd(int no, int what) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) + return; + + mask = vppd_masks[no]; + + if (what) + immap->im_ioport.iop_padat |= mask; + else + immap->im_ioport.iop_padat &= ~mask; +} + +static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) }; + +static void cfg_vccd(int no) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) + return; + + mask = vccd_masks[no]; + + immap->im_ioport.iop_papar &= ~mask; + immap->im_ioport.iop_paodr &= ~mask; + immap->im_ioport.iop_padir |= mask; +} + +static void set_vccd(int no, int what) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) + return; + + mask = vccd_masks[no]; + + if (what) + immap->im_ioport.iop_padat |= mask; + else + immap->im_ioport.iop_padat &= ~mask; +} + +static const unsigned short oc_mask = _BW(8); + +static void cfg_oc(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask = oc_mask; + + immap->im_ioport.iop_pcdir &= ~mask; + immap->im_ioport.iop_pcso &= ~mask; + immap->im_ioport.iop_pcint &= ~mask; + immap->im_ioport.iop_pcpar &= ~mask; +} + +static int get_oc(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask = oc_mask; + int what; + + what = !!(immap->im_ioport.iop_pcdat & mask);; + return what; +} + +static const unsigned short shdn_mask = _BW(12); + +static void cfg_shdn(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + mask = shdn_mask; + + immap->im_ioport.iop_papar &= ~mask; + immap->im_ioport.iop_paodr &= ~mask; + immap->im_ioport.iop_padir |= mask; +} + +static void set_shdn(int what) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + mask = shdn_mask; + + if (what) + immap->im_ioport.iop_padat |= mask; + else + immap->im_ioport.iop_padat &= ~mask; +} + +static void cfg_ports (void); + +static int hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, pipr, mask; + int i; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ + cfg_ports (); + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + pipr = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + pipr, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + + if ((pipr & mask) == mask) { + set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ + set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */ + puts (" 5.0V card found: "); + } else { + set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ + set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */ + puts (" 3.3V card found: "); + } + + /* Wait 500 ms; use this to check for over-current */ + for (i=0; i<5000; ++i) { + if (!get_oc()) { + printf (" *** Overcurrent - Safety shutdown ***\n"); + set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */ + return (1); + } + udelay (100); + } + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + /* All voltages off / Hi-Z */ + set_vppd(0, 1); set_vppd(1, 1); + set_vccd(0, 1); set_vccd(1, 1); + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +static int voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + ushort sreg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ + debug ("PCMCIA power OFF\n"); + cfg_ports (); /* Enables switch, but all in Hi-Z */ + + sreg = immap->im_ioport.iop_pcdat; + set_vppd(0, 1); set_vppd(1, 1); + + switch(vcc) { + case 0: + break; /* Switch off */ + + case 33: + set_vccd(0, 1); set_vccd(1, 0); + break; + + case 50: + set_vccd(0, 0); set_vccd(1, 1); + break; + + default: + goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +static void cfg_ports (void) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + + cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ + cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */ + cfg_shdn(); + cfg_oc(); + + /* + * Configure Port A for TPS2211 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ + set_vppd(0, 1); set_vppd(1, 1); + set_vccd(0, 0); set_vccd(1, 0); + set_shdn(1); + + udelay(100000); +} + +#endif /* NETTA */ + + +/* -------------------------------------------------------------------- */ +/* UC100 Boards */ +/* -------------------------------------------------------------------- */ + +#if defined(CONFIG_UC100) + +#define PCMCIA_BOARD_MSG "UC100" + +/* + * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board. + * This leads to board-hangup! (sr, 8 Dez. 2004) + */ + +static void cfg_ports (void); + +static int hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ + cfg_ports (); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + if ((reg & mask) == mask) { + puts (" 5.0V card found: "); + } else { + puts (" 3.3V card found: "); + } + + /* switch VCC on */ + immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */ + + udelay(10000); + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* switch VCC off */ + immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */ + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +static int voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ + debug ("PCMCIA power OFF\n"); + cfg_ports (); /* Enables switch, but all in Hi-Z */ + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +static void cfg_ports (void) +{ + volatile immap_t *immap; + + immap = (immap_t *)CFG_IMMR; + + /* + * Configure Port A for MAX1602 PC-Card Power-Interface Switch + */ + immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */ + immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */ + + debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n", + immap->im_ioport.iop_papar, immap->im_ioport.iop_padir, + immap->im_ioport.iop_padat); +} + +#endif /* UC100 */ + + +/* -------------------------------------------------------------------- */ + +#endif /* CFG_CMD_PCMCIA || (CFG_CMD_IDE && CONFIG_IDE_8xx_PCCARD) */ + +/**************************************************/ + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +U_BOOT_CMD( + pinit, 2, 1, do_pinit, + "pinit - PCMCIA sub-system\n", + "on - power on PCMCIA socket\n" + "pinit off - power off PCMCIA socket\n" +); +#endif diff --git a/common/cmd_portio.c b/common/cmd_portio.c new file mode 100644 index 0000000..d2e4c4b --- /dev/null +++ b/common/cmd_portio.c @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2003 + * Marc Singer, elf@buici.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Port I/O Functions + * + * Copied from FADS ROM, Dan Malek (dmalek@jlc.net) + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_PORTIO) + +extern int cmd_get_data_size (char *arg, int default_size); + +/* Display values from last command. + * Memory modify remembered values are different from display memory. + */ +static uint in_last_addr, in_last_size; +static uint out_last_addr, out_last_size, out_last_value; + + +int do_portio_out (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + uint addr = out_last_addr; + uint size = out_last_size; + uint value = out_last_value; + + if (argc != 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((flag & CMD_FLAG_REPEAT) == 0) { + /* New command specified. Check for a size specification. + * Defaults to long if no or incorrect specification. + */ + size = cmd_get_data_size (argv[0], 1); + addr = simple_strtoul (argv[1], NULL, 16); + value = simple_strtoul (argv[2], NULL, 16); + } +#if defined (CONFIG_X86) + + { + unsigned short port = addr; + + switch (size) { + default: + case 1: + { + unsigned char ch = value; + __asm__ volatile ("out %0, %%dx"::"a" (ch), "d" (port)); + } + break; + case 2: + { + unsigned short w = value; + __asm__ volatile ("out %0, %%dx"::"a" (w), "d" (port)); + } + break; + case 4: + __asm__ volatile ("out %0, %%dx"::"a" (value), "d" (port)); + + break; + } + } + +#endif /* CONFIG_X86 */ + + out_last_addr = addr; + out_last_size = size; + out_last_value = value; + + return 0; +} + +U_BOOT_CMD( + out, 3, 1, do_portio_out, + "out - write datum to IO port\n", + "[.b, .w, .l] port value\n - output to IO port\n" +); + +int do_portio_in (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + uint addr = in_last_addr; + uint size = in_last_size; + + if (argc != 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((flag & CMD_FLAG_REPEAT) == 0) { + /* New command specified. Check for a size specification. + * Defaults to long if no or incorrect specification. + */ + size = cmd_get_data_size (argv[0], 1); + addr = simple_strtoul (argv[1], NULL, 16); + } +#if defined (CONFIG_X86) + + { + unsigned short port = addr; + + switch (size) { + default: + case 1: + { + unsigned char ch; + __asm__ volatile ("in %%dx, %0":"=a" (ch):"d" (port)); + + printf (" %02x\n", ch); + } + break; + case 2: + { + unsigned short w; + __asm__ volatile ("in %%dx, %0":"=a" (w):"d" (port)); + + printf (" %04x\n", w); + } + break; + case 4: + { + unsigned long l; + __asm__ volatile ("in %%dx, %0":"=a" (l):"d" (port)); + + printf (" %08lx\n", l); + } + break; + } + } +#endif /* CONFIG_X86 */ + + in_last_addr = addr; + in_last_size = size; + + return 0; +} + +U_BOOT_CMD( + in, 2, 1, do_portio_in, + "in - read data from an IO port\n", + "[.b, .w, .l] port\n" + " - read datum from IO port\n" +); + +#endif /* CFG_CMD_PORTIO */ diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c new file mode 100644 index 0000000..15ac16a --- /dev/null +++ b/common/cmd_reginfo.c @@ -0,0 +1,350 @@ +/* + * (C) Copyright 2000 + * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#if defined(CONFIG_8xx) +#include +#elif defined (CONFIG_405GP) || defined(CONFIG_405EP) +#include +#elif defined (CONFIG_5xx) +#include +#elif defined (CONFIG_MPC5200) +#include +#endif +#if (CONFIG_COMMANDS & CFG_CMD_REGINFO) + +int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_8xx) + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; + volatile sit8xx_t *timers = &immap->im_sit; + + /* Hopefully more PowerPC knowledgable people will add code to display + * other useful registers + */ + + printf ("\nSystem Configuration registers\n" + + "\tIMMR\t0x%08X\n", get_immr(0)); + + printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr); + printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr); + + printf("\tSWT\t0x%08X", sysconf->sc_swt); + printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr); + + printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", + sysconf->sc_sipend, sysconf->sc_simask); + printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", + sysconf->sc_siel, sysconf->sc_sivec); + printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", + sysconf->sc_tesr, sysconf->sc_sdcr); + + printf ("Memory Controller Registers\n" + + "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); + printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); + printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); + printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); + printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4); + printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5); + printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6); + printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7); + printf ("\n" + "\tmamr\t0x%08X\tmbmr\t0x%08X \n", + memctl->memc_mamr, memctl->memc_mbmr ); + printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n", + memctl->memc_mstat, memctl->memc_mptpr ); + printf("\tmdr\t0x%08X \n", memctl->memc_mdr); + + printf ("\nSystem Integration Timers\n" + "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", + timers->sit_tbscr, timers->sit_rtcsc); + printf("\tPISCR\t0x%08X \n", timers->sit_piscr); + + /* + * May be some CPM info here? + */ + +#elif defined (CONFIG_405GP) + printf ("\n405GP registers; MSR=%08x\n",mfmsr()); + printf ("\nUniversal Interrupt Controller Regs\n" + "uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr" + "\n" + "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n", + mfdcr(uicsr), + mfdcr(uicsrs), + mfdcr(uicer), + mfdcr(uiccr), + mfdcr(uicpr), + mfdcr(uictr), + mfdcr(uicmsr), + mfdcr(uicvr), + mfdcr(uicvcr)); + + puts ("\nMemory (SDRAM) Configuration\n" + "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); + + mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); + + puts ("\n" + "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); + mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd)); + + printf ("\n\n" + "DMA Channels\n" + "dmasr dmasgc dmaadr\n" + "%08x %08x %08x\n" + "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" + "%08x %08x %08x %08x %08x\n" + "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" + "%08x %08x %08x %08x %08x\n", + mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr), + mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0), + mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1)); + + printf ( + "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" + "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", + mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2), + mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) ); + + puts ("\n" + "External Bus\n" + "pbear pbesr0 pbesr1 epcr\n"); + mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); + + puts ("\n" + "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); + mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); + + puts ("\n" + "pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n"); + mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd)); + + puts ("\n\n"); + +#elif defined(CONFIG_405EP) + printf ("\n405EP registers; MSR=%08x\n",mfmsr()); + printf ("\nUniversal Interrupt Controller Regs\n" + "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr" + "\n" + "%08x %08x %08x %08x %08x %08x %08x %08x\n", + mfdcr(uicsr), + mfdcr(uicer), + mfdcr(uiccr), + mfdcr(uicpr), + mfdcr(uictr), + mfdcr(uicmsr), + mfdcr(uicvr), + mfdcr(uicvcr)); + + puts ("\nMemory (SDRAM) Configuration\n" + "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); + + mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); + + printf ("\n\n" + "DMA Channels\n" + "dmasr dmasgc dmaadr\n" "%08x %08x %08x\n" + "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" + "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", + mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr), + mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0), + mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1)); + + printf ( + "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" + "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", + mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2), + mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) ); + + puts ("\n" + "External Bus\n" + "pbear pbesr0 pbesr1 epcr\n"); + mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); + + puts ("\n" + "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); + mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); + + puts ("\n" + "pb4cr pb4ap\n"); + mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); + + puts ("\n\n"); +#elif defined(CONFIG_5xx) + + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl5xx_t *memctl = &immap->im_memctl; + volatile sysconf5xx_t *sysconf = &immap->im_siu_conf; + volatile sit5xx_t *timers = &immap->im_sit; + volatile car5xx_t *car = &immap->im_clkrst; + volatile uimb5xx_t *uimb = &immap->im_uimb; + + puts ("\nSystem Configuration registers\n"); + printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr); + printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr); + printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask); + printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec); + printf("\tTESR\t0x%08X\n", sysconf->sc_tesr); + + puts ("\nMemory Controller Registers\n"); + printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); + printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); + printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); + printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); + printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor ); + printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat); + + puts ("\nSystem Integration Timers\n"); + printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc); + printf("\tPISCR\t0x%08X \n", timers->sit_piscr); + + puts ("\nClocks and Reset\n"); + printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr); + + puts ("\nU-Bus to IMB3 Bus Interface\n"); + printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend); + puts ("\n\n"); + +#elif defined(CONFIG_MPC5200) + puts ("\nMPC5200 registers\n"); + printf ("MBAR=%08x\n", CFG_MBAR); + puts ("Memory map registers\n"); + printf ("\tCS0: start %08X\tstop %08X\tconfig %08X\ten %d\n", + *(volatile ulong*)MPC5XXX_CS0_START, + *(volatile ulong*)MPC5XXX_CS0_STOP, + *(volatile ulong*)MPC5XXX_CS0_CFG, + (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0); + printf ("\tCS1: start %08X\tstop %08X\tconfig %08X\ten %d\n", + *(volatile ulong*)MPC5XXX_CS1_START, + *(volatile ulong*)MPC5XXX_CS1_STOP, + *(volatile ulong*)MPC5XXX_CS1_CFG, + (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0); + printf ("\tCS2: start %08X\tstop %08X\tconfig %08X\ten %d\n", + *(volatile ulong*)MPC5XXX_CS2_START, + *(volatile ulong*)MPC5XXX_CS2_STOP, + *(volatile ulong*)MPC5XXX_CS2_CFG, + (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0); + printf ("\tCS3: start %08X\tstop %08X\tconfig %08X\ten %d\n", + *(volatile ulong*)MPC5XXX_CS3_START, + *(volatile ulong*)MPC5XXX_CS3_STOP, + *(volatile ulong*)MPC5XXX_CS3_CFG, + (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0); + printf ("\tCS4: start %08X\tstop %08X\tconfig %08X\ten %d\n", + *(volatile ulong*)MPC5XXX_CS4_START, + *(volatile ulong*)MPC5XXX_CS4_STOP, + *(volatile ulong*)MPC5XXX_CS4_CFG, + (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0); + printf ("\tCS5: start %08X\tstop %08X\tconfig %08X\ten %d\n", + *(volatile ulong*)MPC5XXX_CS5_START, + *(volatile ulong*)MPC5XXX_CS5_STOP, + *(volatile ulong*)MPC5XXX_CS5_CFG, + (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0); + printf ("\tCS6: start %08X\tstop %08X\tconfig %08X\ten %d\n", + *(volatile ulong*)MPC5XXX_CS6_START, + *(volatile ulong*)MPC5XXX_CS6_STOP, + *(volatile ulong*)MPC5XXX_CS6_CFG, + (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0); + printf ("\tCS7: start %08X\tstop %08X\tconfig %08X\ten %d\n", + *(volatile ulong*)MPC5XXX_CS7_START, + *(volatile ulong*)MPC5XXX_CS7_STOP, + *(volatile ulong*)MPC5XXX_CS7_CFG, + (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0); + printf ("\tBOOTCS: start %08X\tstop %08X\tconfig %08X\ten %d\n", + *(volatile ulong*)MPC5XXX_BOOTCS_START, + *(volatile ulong*)MPC5XXX_BOOTCS_STOP, + *(volatile ulong*)MPC5XXX_BOOTCS_CFG, + (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0); + printf ("\tSDRAMCS0: %08X\n", + *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); + printf ("\tSDRAMCS0: %08X\n", + *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); +#endif /* CONFIG_MPC5200 */ + return 0; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_REGINFO */ + + + /**************************************************/ + +#if ( defined(CONFIG_8xx) || defined(CONFIG_405GP) || \ + defined(CONFIG_405EP) || defined(CONFIG_MPC5200) ) && \ + (CONFIG_COMMANDS & CFG_CMD_REGINFO) + +U_BOOT_CMD( + reginfo, 2, 1, do_reginfo, + "reginfo - print register information\n", +); +#endif diff --git a/common/cmd_reiser.c b/common/cmd_reiser.c new file mode 100644 index 0000000..508ffcb --- /dev/null +++ b/common/cmd_reiser.c @@ -0,0 +1,277 @@ +/* + * (C) Copyright 2003 - 2004 + * Sysgo Real-Time Solutions, AG + * Pavel Bartusek + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Reiserfs support + */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_REISER) +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_DOS_PARTITION +#error DOS partition support must be selected +#endif + +/* #define REISER_DEBUG */ + +#ifdef REISER_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +static block_dev_desc_t *get_dev (char* ifname, int dev) +{ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + if (strncmp(ifname,"ide",3)==0) { + extern block_dev_desc_t * ide_get_dev(int dev); + return((dev >= CFG_IDE_MAXDEVICE) ? NULL : ide_get_dev(dev)); + } +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + if (strncmp(ifname,"scsi",4)==0) { + extern block_dev_desc_t * scsi_get_dev(int dev); + return((dev >= CFG_SCSI_MAXDEVICE) ? NULL : scsi_get_dev(dev)); + } +#endif +#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE)) + if (strncmp(ifname,"usb",3)==0) { + extern block_dev_desc_t * usb_stor_get_dev(int dev); + return((dev >= USB_MAX_STOR_DEV) ? NULL : usb_stor_get_dev(dev)); + } +#endif +#if defined(CONFIG_MMC) + if (strncmp(ifname,"mmc",3)==0) { + extern block_dev_desc_t * mmc_get_dev(int dev); + return((dev >= 1) ? NULL : mmc_get_dev(dev)); + } +#endif +#if defined(CONFIG_SYSTEMACE) + if (strcmp(ifname,"ace")==0) { + extern block_dev_desc_t * systemace_get_dev(int dev); + return((dev >= 1) ? NULL : systemace_get_dev(dev)); + } +#endif + return NULL; +} + +int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *filename = "/"; + int dev=0; + int part=1; + char *ep; + block_dev_desc_t *dev_desc=NULL; + int part_length; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + dev = (int)simple_strtoul (argv[2], &ep, 16); + dev_desc=get_dev(argv[1],dev); + + if (dev_desc == NULL) { + printf ("\n** Block device %s %d not supported\n", argv[1], dev); + return 1; + } + + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + return 1; + } + part = (int)simple_strtoul(++ep, NULL, 16); + } + + if (argc == 4) { + filename = argv[3]; + } + + PRINTF("Using device %s %d:%d, directory: %s\n", argv[1], dev, part, filename); + + if ((part_length = reiserfs_set_blk_dev(dev_desc, part)) == 0) { + printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part); + return 1; + } + + if (!reiserfs_mount(part_length)) { + printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part); + return 1; + } + + if (reiserfs_ls (filename)) { + printf ("** Error reiserfs_ls() **\n"); + return 1; + }; + + return 0; +} + +U_BOOT_CMD( + reiserls, 4, 1, do_reiserls, + "reiserls- list files in a directory (default /)\n", + " [directory]\n" + " - list files from 'dev' on 'interface' in a 'directory'\n" +); + +/****************************************************************************** + * Reiserfs boot command intepreter. Derived from diskboot + */ +int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *filename = NULL; + char *ep; + int dev, part = 0; + ulong addr = 0, part_length, filelen; + disk_partition_t info; + block_dev_desc_t *dev_desc = NULL; + char buf [12]; + unsigned long count; + char *addr_str; + + switch (argc) { + case 3: + addr_str = getenv("loadaddr"); + if (addr_str != NULL) { + addr = simple_strtoul (addr_str, NULL, 16); + } else { + addr = CFG_LOAD_ADDR; + } + filename = getenv ("bootfile"); + count = 0; + break; + case 4: + addr = simple_strtoul (argv[3], NULL, 16); + filename = getenv ("bootfile"); + count = 0; + break; + case 5: + addr = simple_strtoul (argv[3], NULL, 16); + filename = argv[4]; + count = 0; + break; + case 6: + addr = simple_strtoul (argv[3], NULL, 16); + filename = argv[4]; + count = simple_strtoul (argv[5], NULL, 16); + break; + + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (!filename) { + puts ("\n** No boot file defined **\n"); + return 1; + } + + dev = (int)simple_strtoul (argv[2], &ep, 16); + dev_desc=get_dev(argv[1],dev); + if (dev_desc==NULL) { + printf ("\n** Block device %s %d not supported\n", argv[1], dev); + return 1; + } + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + return 1; + } + part = (int)simple_strtoul(++ep, NULL, 16); + } + + PRINTF("Using device %s%d, partition %d\n", argv[1], dev, part); + + if (part != 0) { + if (get_partition_info (dev_desc, part, &info)) { + printf ("** Bad partition %d **\n", part); + return 1; + } + + if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) { + printf ("\n** Invalid partition type \"%.32s\"" + " (expect \"" BOOT_PART_TYPE "\")\n", + info.type); + return 1; + } + PRINTF ("\nLoading from block device %s device %d, partition %d: " + "Name: %.32s Type: %.32s File:%s\n", + argv[1], dev, part, info.name, info.type, filename); + } else { + PRINTF ("\nLoading from block device %s device %d, File:%s\n", + argv[1], dev, filename); + } + + + if ((part_length = reiserfs_set_blk_dev(dev_desc, part)) == 0) { + printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part); + return 1; + } + + if (!reiserfs_mount(part_length)) { + printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part); + return 1; + } + + filelen = reiserfs_open(filename); + if (filelen < 0) { + printf("** File not found %s\n", filename); + return 1; + } + if ((count < filelen) && (count != 0)) { + filelen = count; + } + + if (reiserfs_read((char *)addr, filelen) != filelen) { + printf("\n** Unable to read \"%s\" from %s %d:%d **\n", filename, argv[1], dev, part); + return 1; + } + + /* Loading ok, update default load address */ + load_addr = addr; + + printf ("\n%ld bytes read\n", filelen); + sprintf(buf, "%lX", filelen); + setenv("filesize", buf); + + return filelen; +} + +U_BOOT_CMD( + reiserload, 6, 0, do_reiserload, + "reiserload- load binary file from a Reiser filesystem\n", + " [addr] [filename] [bytes]\n" + " - load binary file 'filename' from 'dev' on 'interface'\n" + " to address 'addr' from dos filesystem\n" +); + +#endif /* CONFIG_COMMANDS & CFG_CMD_REISER */ diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c new file mode 100644 index 0000000..e804861 --- /dev/null +++ b/common/cmd_scsi.c @@ -0,0 +1,607 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * + */ + +/* + * SCSI support. + */ +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + +#ifdef CONFIG_SCSI_SYM53C8XX +#define SCSI_VEND_ID 0x1000 +#ifndef CONFIG_SCSI_DEV_ID +#define SCSI_DEV_ID 0x0001 +#else +#define SCSI_DEV_ID CONFIG_SCSI_DEV_ID +#endif +#else +#error CONFIG_SCSI_SYM53C8XX must be defined +#endif + + +static ccb tempccb; /* temporary scsi command buffer */ + +static unsigned char tempbuff[512]; /* temporary data buffer */ + +static int scsi_max_devs; /* number of highest available scsi device */ + +static int scsi_curr_dev; /* current device */ + +static block_dev_desc_t scsi_dev_desc[CFG_SCSI_MAX_DEVICE]; + +/******************************************************************************** + * forward declerations of some Setup Routines + */ +void scsi_setup_test_unit_ready(ccb * pccb); +void scsi_setup_read_capacity(ccb * pccb); +void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks); +void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks); +void scsi_setup_inquiry(ccb * pccb); +void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); + + +ulong scsi_read(int device, ulong blknr, ulong blkcnt, ulong *buffer); + + +/********************************************************************************* + * (re)-scan the scsi bus and reports scsi device info + * to the user if mode = 1 + */ +void scsi_scan(int mode) +{ + unsigned char i,perq,modi,lun; + unsigned long capacity,blksz; + ccb* pccb=(ccb *)&tempccb; + + if(mode==1) { + printf("scanning bus for devices...\n"); + } + for(i=0;itarget=i; + for(lun=0;lunlun=lun; + pccb->pdata=(unsigned char *)&tempbuff; + pccb->datalen=512; + scsi_setup_inquiry(pccb); + if(scsi_exec(pccb)!=TRUE) { + if(pccb->contr_stat==SCSI_SEL_TIME_OUT) { + debug ("Selection timeout ID %d\n",pccb->target); + continue; /* selection timeout => assuming no device present */ + } + scsi_print_error(pccb); + continue; + } + perq=tempbuff[0]; + modi=tempbuff[1]; + if((perq & 0x1f)==0x1f) { + continue; /* skip unknown devices */ + } + if((modi&0x80)==0x80) /* drive is removable */ + scsi_dev_desc[scsi_max_devs].removable=TRUE; + /* get info for this device */ + scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].vendor[0],&tempbuff[8],8); + scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].product[0],&tempbuff[16],16); + scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].revision[0],&tempbuff[32],4); + scsi_dev_desc[scsi_max_devs].target=pccb->target; + scsi_dev_desc[scsi_max_devs].lun=pccb->lun; + + pccb->datalen=0; + scsi_setup_test_unit_ready(pccb); + if(scsi_exec(pccb)!=TRUE) { + if(scsi_dev_desc[scsi_max_devs].removable==TRUE) { + scsi_dev_desc[scsi_max_devs].type=perq; + goto removable; + } + scsi_print_error(pccb); + continue; + } + pccb->datalen=8; + scsi_setup_read_capacity(pccb); + if(scsi_exec(pccb)!=TRUE) { + scsi_print_error(pccb); + continue; + } + capacity=((unsigned long)tempbuff[0]<<24)|((unsigned long)tempbuff[1]<<16)| + ((unsigned long)tempbuff[2]<<8)|((unsigned long)tempbuff[3]); + blksz=((unsigned long)tempbuff[4]<<24)|((unsigned long)tempbuff[5]<<16)| + ((unsigned long)tempbuff[6]<<8)|((unsigned long)tempbuff[7]); + scsi_dev_desc[scsi_max_devs].lba=capacity; + scsi_dev_desc[scsi_max_devs].blksz=blksz; + scsi_dev_desc[scsi_max_devs].type=perq; + init_part(&scsi_dev_desc[scsi_max_devs]); +removable: + if(mode==1) { + printf (" Device %d: ", scsi_max_devs); + dev_print(&scsi_dev_desc[scsi_max_devs]); + } /* if mode */ + scsi_max_devs++; + } /* next LUN */ + } + if(scsi_max_devs>0) + scsi_curr_dev=0; + else + scsi_curr_dev=-1; +} + + +void scsi_init(void) +{ + int busdevfunc; + + busdevfunc=pci_find_device(SCSI_VEND_ID,SCSI_DEV_ID,0); /* get PCI Device ID */ + if(busdevfunc==-1) { + printf("Error SCSI Controller (%04X,%04X) not found\n",SCSI_VEND_ID,SCSI_DEV_ID); + return; + } +#ifdef DEBUG + else { + printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",SCSI_VEND_ID,SCSI_DEV_ID,(busdevfunc>>16)&0xFF,(busdevfunc>>11)&0x1F,(busdevfunc>>8)&0x7); + } +#endif + scsi_low_level_init(busdevfunc); + scsi_scan(1); +} + +block_dev_desc_t * scsi_get_dev(int dev) +{ + return((block_dev_desc_t *)&scsi_dev_desc[dev]); +} + + +/****************************************************************************** + * scsi boot command intepreter. Derived from diskboot + */ +int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + char *ep; + int dev, part = 0; + ulong addr, cnt, checksum; + disk_partition_t info; + image_header_t *hdr; + int rcode = 0; + + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_device = getenv ("bootdevice"); + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = getenv ("bootdevice"); + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (!boot_device) { + puts ("\n** No boot device **\n"); + return 1; + } + + dev = simple_strtoul(boot_device, &ep, 16); + printf("booting from dev %d\n",dev); + if (scsi_dev_desc[dev].type == DEV_TYPE_UNKNOWN) { + printf ("\n** Device %d not available\n", dev); + return 1; + } + + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + return 1; + } + part = simple_strtoul(++ep, NULL, 16); + } + if (get_partition_info (scsi_dev_desc, part, &info)) { + printf("error reading partinfo\n"); + return 1; + } + if ((strncmp((char *)(info.type), BOOT_PART_TYPE, sizeof(info.type)) != 0) && + (strncmp((char *)(info.type), BOOT_PART_COMP, sizeof(info.type)) != 0)) { + printf ("\n** Invalid partition type \"%.32s\"" + " (expect \"" BOOT_PART_TYPE "\")\n", + info.type); + return 1; + } + + printf ("\nLoading from SCSI device %d, partition %d: " + "Name: %.32s Type: %.32s\n", + dev, part, info.name, info.type); + + debug ("First Block: %ld, # of blocks: %ld, Block Size: %ld\n", + info.start, info.size, info.blksz); + + if (scsi_read (dev, info.start, 1, (ulong *)addr) != 1) { + printf ("** Read error on %d:%d\n", dev, part); + return 1; + } + + hdr = (image_header_t *)addr; + + if (ntohl(hdr->ih_magic) == IH_MAGIC) { + printf("\n** Bad Magic Number **\n"); + return 1; + } + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) { + puts ("\n** Bad Header Checksum **\n"); + return 1; + } + hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */ + + print_image_hdr (hdr); + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); + cnt += info.blksz - 1; + cnt /= info.blksz; + cnt -= 1; + + if (scsi_read (dev, info.start+1, cnt, + (ulong *)(addr+info.blksz)) != cnt) { + printf ("** Read error on %d:%d\n", dev, part); + return 1; + } + /* Loading ok, update default load address */ + load_addr = addr; + + flush_cache (addr, (cnt+1)*info.blksz); + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { + char *local_args[2]; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + local_args[0] = argv[0]; + local_args[1] = NULL; + printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); + rcode = do_bootm (cmdtp, 0, 1, local_args); + } + return rcode; +} + +/********************************************************************************* + * scsi command intepreter + */ +int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + switch (argc) { + case 0: + case 1: printf ("Usage:\n%s\n", cmdtp->usage); return 1; + case 2: + if (strncmp(argv[1],"res",3) == 0) { + printf("\nReset SCSI\n"); + scsi_bus_reset(); + scsi_scan(1); + return 0; + } + if (strncmp(argv[1],"inf",3) == 0) { + int i; + for (i=0; i= CFG_SCSI_MAX_DEVICE)) { + printf("\nno SCSI devices available\n"); + return 1; + } + printf ("\n Device %d: ", scsi_curr_dev); + dev_print(&scsi_dev_desc[scsi_curr_dev]); + return 0; + } + if (strncmp(argv[1],"scan",4) == 0) { + scsi_scan(1); + return 0; + } + if (strncmp(argv[1],"part",4) == 0) { + int dev, ok; + for (ok=0, dev=0; devusage); + return 1; + case 3: + if (strncmp(argv[1],"dev",3) == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + printf ("\nSCSI device %d: ", dev); + if (dev >= CFG_SCSI_MAX_DEVICE) { + printf("unknown device\n"); + return 1; + } + printf ("\n Device %d: ", dev); + dev_print(&scsi_dev_desc[dev]); + if(scsi_dev_desc[dev].type == DEV_TYPE_UNKNOWN) { + return 1; + } + scsi_curr_dev = dev; + printf("... is now current device\n"); + return 0; + } + if (strncmp(argv[1],"part",4) == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + if(scsi_dev_desc[dev].type != DEV_TYPE_UNKNOWN) { + print_part(&scsi_dev_desc[dev]); + } + else { + printf ("\nSCSI device %d not available\n", dev); + } + return 1; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + /* at least 4 args */ + if (strcmp(argv[1],"read") == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong blk = simple_strtoul(argv[3], NULL, 16); + ulong cnt = simple_strtoul(argv[4], NULL, 16); + ulong n; + printf ("\nSCSI read: device %d block # %ld, count %ld ... ", + scsi_curr_dev, blk, cnt); + n = scsi_read(scsi_curr_dev, blk, cnt, (ulong *)addr); + printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR"); + return 0; + } + } /* switch */ + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +/**************************************************************************************** + * scsi_read + */ + +#define SCSI_MAX_READ_BLK 0xFFFF /* almost the maximum amount of the scsi_ext command.. */ + +ulong scsi_read(int device, ulong blknr, ulong blkcnt, ulong *buffer) +{ + ulong start,blks, buf_addr; + unsigned short smallblks; + ccb* pccb=(ccb *)&tempccb; + device&=0xff; + /* Setup device + */ + pccb->target=scsi_dev_desc[device].target; + pccb->lun=scsi_dev_desc[device].lun; + buf_addr=(unsigned long)buffer; + start=blknr; + blks=blkcnt; + debug ("\nscsi_read: dev %d startblk %lx, blccnt %lx buffer %lx\n",device,start,blks,(unsigned long)buffer); + do { + pccb->pdata=(unsigned char *)buf_addr; + if(blks>SCSI_MAX_READ_BLK) { + pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK; + smallblks=SCSI_MAX_READ_BLK; + scsi_setup_read_ext(pccb,start,smallblks); + start+=SCSI_MAX_READ_BLK; + blks-=SCSI_MAX_READ_BLK; + } + else { + pccb->datalen=scsi_dev_desc[device].blksz * blks; + smallblks=(unsigned short) blks; + scsi_setup_read_ext(pccb,start,smallblks); + start+=blks; + blks=0; + } + debug ("scsi_read_ext: startblk %lx, blccnt %x buffer %lx\n",start,smallblks,buf_addr); + if(scsi_exec(pccb)!=TRUE) { + scsi_print_error(pccb); + blkcnt-=blks; + break; + } + buf_addr+=pccb->datalen; + } while(blks!=0); + debug ("scsi_read_ext: end startblk %lx, blccnt %x buffer %lx\n",start,smallblks,buf_addr); + return(blkcnt); +} + +/* copy src to dest, skipping leading and trailing blanks + * and null terminate the string + */ +void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len) +{ + int start,end; + + start=0; + while(startstart) { + if(src[end]!=' ') + break; + end--; + } + for( ; start<=end; start++) { + *dest++=src[start]; + } + *dest='\0'; +} + + +/* Trim trailing blanks, and NUL-terminate string + */ +void scsi_trim_trail (unsigned char *str, unsigned int len) +{ + unsigned char *p = str + len - 1; + + while (len-- > 0) { + *p-- = '\0'; + if (*p != ' ') { + return; + } + } +} + + +/************************************************************************************ + * Some setup (fill-in) routines + */ +void scsi_setup_test_unit_ready(ccb * pccb) +{ + pccb->cmd[0]=SCSI_TST_U_RDY; + pccb->cmd[1]=pccb->lun<<5; + pccb->cmd[2]=0; + pccb->cmd[3]=0; + pccb->cmd[4]=0; + pccb->cmd[5]=0; + pccb->cmdlen=6; + pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */ +} + +void scsi_setup_read_capacity(ccb * pccb) +{ + pccb->cmd[0]=SCSI_RD_CAPAC; + pccb->cmd[1]=pccb->lun<<5; + pccb->cmd[2]=0; + pccb->cmd[3]=0; + pccb->cmd[4]=0; + pccb->cmd[5]=0; + pccb->cmd[6]=0; + pccb->cmd[7]=0; + pccb->cmd[8]=0; + pccb->cmd[9]=0; + pccb->cmdlen=10; + pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */ + +} + +void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks) +{ + pccb->cmd[0]=SCSI_READ10; + pccb->cmd[1]=pccb->lun<<5; + pccb->cmd[2]=((unsigned char) (start>>24))&0xff; + pccb->cmd[3]=((unsigned char) (start>>16))&0xff; + pccb->cmd[4]=((unsigned char) (start>>8))&0xff; + pccb->cmd[5]=((unsigned char) (start))&0xff; + pccb->cmd[6]=0; + pccb->cmd[7]=((unsigned char) (blocks>>8))&0xff; + pccb->cmd[8]=(unsigned char) blocks & 0xff; + pccb->cmd[6]=0; + pccb->cmdlen=10; + pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */ + debug ("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n", + pccb->cmd[0],pccb->cmd[1], + pccb->cmd[2],pccb->cmd[3],pccb->cmd[4],pccb->cmd[5], + pccb->cmd[7],pccb->cmd[8]); +} + +void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks) +{ + pccb->cmd[0]=SCSI_READ6; + pccb->cmd[1]=pccb->lun<<5 | (((unsigned char)(start>>16))&0x1f); + pccb->cmd[2]=((unsigned char) (start>>8))&0xff; + pccb->cmd[3]=((unsigned char) (start))&0xff; + pccb->cmd[4]=(unsigned char) blocks & 0xff; + pccb->cmd[5]=0; + pccb->cmdlen=6; + pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */ + debug ("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n", + pccb->cmd[0],pccb->cmd[1], + pccb->cmd[2],pccb->cmd[3],pccb->cmd[4]); +} + + +void scsi_setup_inquiry(ccb * pccb) +{ + pccb->cmd[0]=SCSI_INQUIRY; + pccb->cmd[1]=pccb->lun<<5; + pccb->cmd[2]=0; + pccb->cmd[3]=0; + if(pccb->datalen>255) + pccb->cmd[4]=255; + else + pccb->cmd[4]=(unsigned char)pccb->datalen; + pccb->cmd[5]=0; + pccb->cmdlen=6; + pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */ +} + + +U_BOOT_CMD( + scsi, 5, 1, do_scsi, + "scsi - SCSI sub-system\n", + "reset - reset SCSI controller\n" + "scsi info - show available SCSI devices\n" + "scsi scan - (re-)scan SCSI bus\n" + "scsi device [dev] - show or set current device\n" + "scsi part [dev] - print partition table of one or all SCSI devices\n" + "scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n" + " to memory address `addr'\n" +); + +U_BOOT_CMD( + scsiboot, 3, 1, do_scsiboot, + "scsiboot- boot from SCSI device\n", + "loadAddr dev:part\n" +); + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_SCSI) */ diff --git a/common/cmd_spi.c b/common/cmd_spi.c new file mode 100644 index 0000000..a6fdf7f --- /dev/null +++ b/common/cmd_spi.c @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2002 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * SPI Read/Write Utilities + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_SPI) + +/*----------------------------------------------------------------------- + * Definitions + */ + +#ifndef MAX_SPI_BYTES +# define MAX_SPI_BYTES 32 /* Maximum number of bytes we can handle */ +#endif + +/* + * External table of chip select functions (see the appropriate board + * support for the actual definition of the table). + */ +extern spi_chipsel_type spi_chipsel[]; +extern int spi_chipsel_cnt; + +/* + * Values from last command. + */ +static int device; +static int bitlen; +static uchar dout[MAX_SPI_BYTES]; +static uchar din[MAX_SPI_BYTES]; + +/* + * SPI read/write + * + * Syntax: + * spi {dev} {num_bits} {dout} + * {dev} is the device number for controlling chip select (see TBD) + * {num_bits} is the number of bits to send & receive (base 10) + * {dout} is a hexadecimal string of data to send + * The command prints out the hexadecimal string received via SPI. + */ + +int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *cp = 0; + uchar tmp; + int j; + int rcode = 0; + + /* + * We use the last specified parameters, unless new ones are + * entered. + */ + + if ((flag & CMD_FLAG_REPEAT) == 0) + { + if (argc >= 2) + device = simple_strtoul(argv[1], NULL, 10); + if (argc >= 3) + bitlen = simple_strtoul(argv[2], NULL, 10); + if (argc >= 4) { + cp = argv[3]; + for(j = 0; *cp; j++, cp++) { + tmp = *cp - '0'; + if(tmp > 9) + tmp -= ('A' - '0') - 10; + if(tmp > 15) + tmp -= ('a' - 'A'); + if(tmp > 15) { + printf("Hex conversion error on %c, giving up.\n", *cp); + return 1; + } + if((j % 2) == 0) + dout[j / 2] = (tmp << 4); + else + dout[j / 2] |= tmp; + } + } + } + + if ((device < 0) || (device >= spi_chipsel_cnt)) { + printf("Invalid device %d, giving up.\n", device); + return 1; + } + if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) { + printf("Invalid bitlen %d, giving up.\n", bitlen); + return 1; + } + + debug ("spi_chipsel[%d] = %08X\n", + device, (uint)spi_chipsel[device]); + + if(spi_xfer(spi_chipsel[device], bitlen, dout, din) != 0) { + printf("Error with the SPI transaction.\n"); + rcode = 1; + } else { + cp = (char *)din; + for(j = 0; j < ((bitlen + 7) / 8); j++) { + printf("%02X", *cp++); + } + printf("\n"); + } + + return rcode; +} + +/***************************************************/ + +U_BOOT_CMD( + sspi, 5, 1, do_spi, + "sspi - SPI utility commands\n", + " - Send bits from out the SPI\n" + " - Identifies the chip select of the device\n" + " - Number of bits to send (base 10)\n" + " - Hexadecimal string that gets sent\n" +); + +#endif /* CFG_CMD_SPI */ diff --git a/common/cmd_universe.c b/common/cmd_universe.c new file mode 100644 index 0000000..8d7b6fe --- /dev/null +++ b/common/cmd_universe.c @@ -0,0 +1,390 @@ +/* + * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_UNIVERSE) + +#define PCI_VENDOR PCI_VENDOR_ID_TUNDRA +#define PCI_DEVICE PCI_DEVICE_ID_TUNDRA_CA91C042 + + +typedef struct _UNI_DEV UNI_DEV; + +struct _UNI_DEV { + int bus; + pci_dev_t busdevfn; + UNIVERSE *uregs; + unsigned int pci_bs; +}; + +static UNI_DEV *dev; + + +int universe_init(void) +{ + int j, result, lastError = 0; + pci_dev_t busdevfn; + unsigned int val; + + busdevfn = pci_find_device(PCI_VENDOR, PCI_DEVICE, 0); + if (busdevfn == -1) { + puts("No Tundra Universe found!\n"); + return -1; + } + + /* Lets turn Latency off */ + pci_write_config_dword(busdevfn, 0x0c, 0); + + dev = malloc(sizeof(*dev)); + if (NULL == dev) { + puts("UNIVERSE: No memory!\n"); + result = -1; + goto break_20; + } + + memset(dev, 0, sizeof(*dev)); + dev->busdevfn = busdevfn; + + pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_1, &val); + if (val & 1) { + pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val); + } + val &= ~0xf; + dev->uregs = (UNIVERSE *)val; + + debug ("UNIVERSE-Base : %p\n", dev->uregs); + + /* check mapping */ + debug (" Read via mapping, PCI_ID = %08X\n", readl(&dev->uregs->pci_id)); + if (((PCI_DEVICE <<16) | PCI_VENDOR) != readl(&dev->uregs->pci_id)) { + printf ("UNIVERSE: Cannot read PCI-ID via Mapping: %08x\n", + readl(&dev->uregs->pci_id)); + result = -1; + goto break_30; + } + + debug ("PCI_BS = %08X\n", readl(&dev->uregs->pci_bs)); + + dev->pci_bs = readl(&dev->uregs->pci_bs); + + /* turn off windows */ + for (j=0; j <4; j ++) { + writel(0x00800000, &dev->uregs->lsi[j].ctl); + writel(0x00800000, &dev->uregs->vsi[j].ctl); + } + + /* + * Write to Misc Register + * Set VME Bus Time-out + * Arbitration Mode + * DTACK Enable + */ + writel(0x15040000 | (readl(&dev->uregs->misc_ctl) & 0x00020000), &dev->uregs->misc_ctl); + + if (readl(&dev->uregs->misc_ctl) & 0x00020000) { + debug ("System Controller!\n"); /* test-only */ + } else { + debug ("Not System Controller!\n"); /* test-only */ + } + + /* + * Lets turn off interrupts + */ + writel(0x00000000,&dev->uregs->lint_en); /* Disable interrupts in the Universe first */ + writel(0x0000FFFF,&dev->uregs->lint_stat); /* Clear Any Pending Interrupts */ + eieio(); + writel(0x0000, &dev->uregs->lint_map0); /* Map all ints to 0 */ + writel(0x0000, &dev->uregs->lint_map1); /* Map all ints to 0 */ + eieio(); + + return 0; + + break_30: + free(dev); + break_20: + lastError = result; + + return result; +} + + +/* + * Create pci slave window (access: pci -> vme) + */ +int universe_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int size, int vam, int pms, int vdw) +{ + int result, i; + unsigned int ctl = 0; + + if (NULL == dev) { + result = -1; + goto exit_10; + } + + for (i = 0; i < 4; i++) { + if (0x00800000 == readl(&dev->uregs->lsi[i].ctl)) + break; + } + + if (i == 4) { + printf ("universe: No Image available\n"); + result = -1; + goto exit_10; + } + + debug ("universe: Using image %d\n", i); + + writel(pciAddr , &dev->uregs->lsi[i].bs); + writel((pciAddr + size), &dev->uregs->lsi[i].bd); + writel((vmeAddr - pciAddr), &dev->uregs->lsi[i].to); + + switch (vam & VME_AM_Axx) { + case VME_AM_A16: + ctl = 0x00000000; + break; + case VME_AM_A24: + ctl = 0x00010000; + break; + case VME_AM_A32: + ctl = 0x00020000; + break; + } + + switch (vam & VME_AM_Mxx) { + case VME_AM_DATA: + ctl |= 0x00000000; + break; + case VME_AM_PROG: + ctl |= 0x00008000; + break; + } + + if (vam & VME_AM_SUP) { + ctl |= 0x00001000; + + } + + switch (vdw & VME_FLAG_Dxx) { + case VME_FLAG_D8: + ctl |= 0x00000000; + break; + case VME_FLAG_D16: + ctl |= 0x00400000; + break; + case VME_FLAG_D32: + ctl |= 0x00800000; + break; + } + + switch (pms & PCI_MS_Mxx) { + case PCI_MS_MEM: + ctl |= 0x00000000; + break; + case PCI_MS_IO: + ctl |= 0x00000001; + break; + case PCI_MS_CONFIG: + ctl |= 0x00000002; + break; + } + + ctl |= 0x80000000; /* enable */ + + writel(ctl, &dev->uregs->lsi[i].ctl); + + debug ("universe: window-addr=%p\n", &dev->uregs->lsi[i].ctl); + debug ("universe: pci slave window[%d] ctl=%08x\n", i, readl(&dev->uregs->lsi[i].ctl)); + debug ("universe: pci slave window[%d] bs=%08x\n", i, readl(&dev->uregs->lsi[i].bs)); + debug ("universe: pci slave window[%d] bd=%08x\n", i, readl(&dev->uregs->lsi[i].bd)); + debug ("universe: pci slave window[%d] to=%08x\n", i, readl(&dev->uregs->lsi[i].to)); + + return 0; + + exit_10: + return -result; +} + + +/* + * Create vme slave window (access: vme -> pci) + */ +int universe_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, int size, int vam, int pms) +{ + int result, i; + unsigned int ctl = 0; + + if (NULL == dev) { + result = -1; + goto exit_10; + } + + for (i = 0; i < 4; i++) { + if (0x00800000 == readl(&dev->uregs->vsi[i].ctl)) + break; + } + + if (i == 4) { + printf ("universe: No Image available\n"); + result = -1; + goto exit_10; + } + + debug ("universe: Using image %d\n", i); + + writel(vmeAddr , &dev->uregs->vsi[i].bs); + writel((vmeAddr + size), &dev->uregs->vsi[i].bd); + writel((pciAddr - vmeAddr), &dev->uregs->vsi[i].to); + + switch (vam & VME_AM_Axx) { + case VME_AM_A16: + ctl = 0x00000000; + break; + case VME_AM_A24: + ctl = 0x00010000; + break; + case VME_AM_A32: + ctl = 0x00020000; + break; + } + + switch (vam & VME_AM_Mxx) { + case VME_AM_DATA: + ctl |= 0x00000000; + break; + case VME_AM_PROG: + ctl |= 0x00800000; + break; + } + + if (vam & VME_AM_SUP) { + ctl |= 0x00100000; + + } + + switch (pms & PCI_MS_Mxx) { + case PCI_MS_MEM: + ctl |= 0x00000000; + break; + case PCI_MS_IO: + ctl |= 0x00000001; + break; + case PCI_MS_CONFIG: + ctl |= 0x00000002; + break; + } + + ctl |= 0x80f00000; /* enable */ + + writel(ctl, &dev->uregs->vsi[i].ctl); + + debug ("universe: window-addr=%p\n", &dev->uregs->vsi[i].ctl); + debug ("universe: vme slave window[%d] ctl=%08x\n", i, readl(&dev->uregs->vsi[i].ctl)); + debug ("universe: vme slave window[%d] bs=%08x\n", i, readl(&dev->uregs->vsi[i].bs)); + debug ("universe: vme slave window[%d] bd=%08x\n", i, readl(&dev->uregs->vsi[i].bd)); + debug ("universe: vme slave window[%d] to=%08x\n", i, readl(&dev->uregs->vsi[i].to)); + + return 0; + + exit_10: + return -result; +} + + +/* + * Tundra Universe configuration + */ +int do_universe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, pms = 0, vdw = 0; + char cmd = 'x'; + + /* get parameter */ + if (argc > 1) + cmd = argv[1][0]; + if (argc > 2) + addr1 = simple_strtoul(argv[2], NULL, 16); + if (argc > 3) + addr2 = simple_strtoul(argv[3], NULL, 16); + if (argc > 4) + size = simple_strtoul(argv[4], NULL, 16); + if (argc > 5) + vam = simple_strtoul(argv[5], NULL, 16); + if (argc > 6) + pms = simple_strtoul(argv[6], NULL, 16); + if (argc > 7) + vdw = simple_strtoul(argv[7], NULL, 16); + + switch (cmd) { + case 'i': /* init */ + universe_init(); + break; + case 'v': /* vme */ + printf("Configuring Universe VME Slave Window (VME->PCI):\n"); + printf(" vme=%08lx pci=%08lx size=%08lx vam=%02lx pms=%02lx\n", + addr1, addr2, size, vam, pms); + universe_vme_slave_window(addr1, addr2, size, vam, pms); + break; + case 'p': /* pci */ + printf("Configuring Universe PCI Slave Window (PCI->VME):\n"); + printf(" pci=%08lx vme=%08lx size=%08lx vam=%02lx pms=%02lx vdw=%02lx\n", + addr1, addr2, size, vam, pms, vdw); + universe_pci_slave_window(addr1, addr2, size, vam, pms, vdw); + break; + default: + printf("Universe command %s not supported!\n", argv[1]); + } + + return 0; +} + + +U_BOOT_CMD( + universe, 8, 1, do_universe, + "universe- initialize and configure Turndra Universe\n", + "init\n" + " - initialize universe\n" + "universe vme [vme_addr] [pci_addr] [size] [vam] [pms]\n" + " - create vme slave window (access: vme->pci)\n" + "universe pci [pci_addr] [vme_addr] [size] [vam] [pms] [vdw]\n" + " - create pci slave window (access: pci->vme)\n" + " [vam] = VMEbus Address-Modifier: 01 -> A16 Address Space\n" + " 02 -> A24 Address Space\n" + " 03 -> A32 Address Space\n" + " 04 -> Supervisor AM Code\n" + " 10 -> Data AM Code\n" + " 20 -> Program AM Code\n" + " [pms] = PCI Memory Space: 01 -> Memory Space\n" + " 02 -> I/O Space\n" + " 03 -> Configuration Space\n" + " [vdw] = VMEbus Maximum Datawidth: 01 -> D8 Data Width\n" + " 02 -> D16 Data Width\n" + " 03 -> D32 Data Width\n" +); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_UNIVERSE) */ diff --git a/common/cmd_usb.c b/common/cmd_usb.c new file mode 100644 index 0000000..fdfd042 --- /dev/null +++ b/common/cmd_usb.c @@ -0,0 +1,642 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * Most of this source has been derived from the Linux USB + * project. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_USB) + +#include + +#ifdef CONFIG_USB_STORAGE +static int usb_stor_curr_dev=-1; /* current device */ +#endif + +/* some display routines (info command) */ +char * usb_get_class_desc(unsigned char dclass) +{ + switch(dclass) { + case USB_CLASS_PER_INTERFACE: + return("See Interface"); + case USB_CLASS_AUDIO: + return("Audio"); + case USB_CLASS_COMM: + return("Communication"); + case USB_CLASS_HID: + return("Human Interface"); + case USB_CLASS_PRINTER: + return("Printer"); + case USB_CLASS_MASS_STORAGE: + return("Mass Storage"); + case USB_CLASS_HUB: + return("Hub"); + case USB_CLASS_DATA: + return("CDC Data"); + case USB_CLASS_VENDOR_SPEC: + return("Vendor specific"); + default : + return(""); + } +} + +void usb_display_class_sub(unsigned char dclass,unsigned char subclass,unsigned char proto) +{ + switch(dclass) { + case USB_CLASS_PER_INTERFACE: + printf("See Interface"); + break; + case USB_CLASS_HID: + printf("Human Interface, Subclass: "); + switch(subclass) { + case USB_SUB_HID_NONE: + printf("None"); + break; + case USB_SUB_HID_BOOT: + printf("Boot "); + switch(proto) { + case USB_PROT_HID_NONE: + printf("None"); + break; + case USB_PROT_HID_KEYBOARD: + printf("Keyboard"); + break; + case USB_PROT_HID_MOUSE: + printf("Mouse"); + break; + default: + printf("reserved"); + } + break; + default: + printf("reserved"); + } + break; + case USB_CLASS_MASS_STORAGE: + printf("Mass Storage, "); + switch(subclass) { + case US_SC_RBC: + printf("RBC "); + break; + case US_SC_8020: + printf("SFF-8020i (ATAPI)"); + break; + case US_SC_QIC: + printf("QIC-157 (Tape)"); + break; + case US_SC_UFI: + printf("UFI"); + break; + case US_SC_8070: + printf("SFF-8070"); + break; + case US_SC_SCSI: + printf("Transp. SCSI"); + break; + default: + printf("reserved"); + break; + } + printf(", "); + switch(proto) { + case US_PR_CB: + printf("Command/Bulk"); + break; + case US_PR_CBI: + printf("Command/Bulk/Int"); + break; + case US_PR_BULK: + printf("Bulk only"); + break; + default: + printf("reserved"); + } + break; + default: + printf("%s",usb_get_class_desc(dclass)); + } +} + +void usb_display_string(struct usb_device *dev,int index) +{ + char buffer[256]; + if (index!=0) { + if (usb_string(dev,index,&buffer[0],256)>0); + printf("String: \"%s\"",buffer); + } +} + +void usb_display_desc(struct usb_device *dev) +{ + if (dev->descriptor.bDescriptorType==USB_DT_DEVICE) { + printf("%d: %s, USB Revision %x.%x\n",dev->devnum,usb_get_class_desc(dev->config.if_desc[0].bInterfaceClass), + (dev->descriptor.bcdUSB>>8) & 0xff,dev->descriptor.bcdUSB & 0xff); + if (strlen(dev->mf) || strlen(dev->prod) || strlen(dev->serial)) + printf(" - %s %s %s\n",dev->mf,dev->prod,dev->serial); + if (dev->descriptor.bDeviceClass) { + printf(" - Class: "); + usb_display_class_sub(dev->descriptor.bDeviceClass,dev->descriptor.bDeviceSubClass,dev->descriptor.bDeviceProtocol); + printf("\n"); + } + else { + printf(" - Class: (from Interface) %s\n",usb_get_class_desc(dev->config.if_desc[0].bInterfaceClass)); + } + printf(" - PacketSize: %d Configurations: %d\n",dev->descriptor.bMaxPacketSize0,dev->descriptor.bNumConfigurations); + printf(" - Vendor: 0x%04x Product 0x%04x Version %d.%d\n",dev->descriptor.idVendor,dev->descriptor.idProduct,(dev->descriptor.bcdDevice>>8) & 0xff,dev->descriptor.bcdDevice & 0xff); + } + +} + +void usb_display_conf_desc(struct usb_config_descriptor *config,struct usb_device *dev) +{ + printf(" Configuration: %d\n",config->bConfigurationValue); + printf(" - Interfaces: %d %s%s%dmA\n",config->bNumInterfaces,(config->bmAttributes & 0x40) ? "Self Powered " : "Bus Powered ", + (config->bmAttributes & 0x20) ? "Remote Wakeup " : "",config->MaxPower*2); + if (config->iConfiguration) { + printf(" - "); + usb_display_string(dev,config->iConfiguration); + printf("\n"); + } +} + +void usb_display_if_desc(struct usb_interface_descriptor *ifdesc,struct usb_device *dev) +{ + printf(" Interface: %d\n",ifdesc->bInterfaceNumber); + printf(" - Alternate Settings %d, Endpoints: %d\n",ifdesc->bAlternateSetting,ifdesc->bNumEndpoints); + printf(" - Class "); + usb_display_class_sub(ifdesc->bInterfaceClass,ifdesc->bInterfaceSubClass,ifdesc->bInterfaceProtocol); + printf("\n"); + if (ifdesc->iInterface) { + printf(" - "); + usb_display_string(dev,ifdesc->iInterface); + printf("\n"); + } +} + +void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc) +{ + printf(" - Endpoint %d %s ",epdesc->bEndpointAddress & 0xf,(epdesc->bEndpointAddress & 0x80) ? "In" : "Out"); + switch((epdesc->bmAttributes & 0x03)) + { + case 0: printf("Control"); break; + case 1: printf("Isochronous"); break; + case 2: printf("Bulk"); break; + case 3: printf("Interrupt"); break; + } + printf(" MaxPacket %d",epdesc->wMaxPacketSize); + if ((epdesc->bmAttributes & 0x03)==0x3) + printf(" Interval %dms",epdesc->bInterval); + printf("\n"); +} + +/* main routine to diasplay the configs, interfaces and endpoints */ +void usb_display_config(struct usb_device *dev) +{ + struct usb_config_descriptor *config; + struct usb_interface_descriptor *ifdesc; + struct usb_endpoint_descriptor *epdesc; + int i,ii; + + config= &dev->config; + usb_display_conf_desc(config,dev); + for(i=0;ino_of_if;i++) { + ifdesc= &config->if_desc[i]; + usb_display_if_desc(ifdesc,dev); + for(ii=0;iino_of_ep;ii++) { + epdesc= &ifdesc->ep_desc[ii]; + usb_display_ep_desc(epdesc); + } + } + printf("\n"); +} + +/* shows the device tree recursively */ +void usb_show_tree_graph(struct usb_device *dev,char *pre) +{ + int i,index; + int has_child,last_child,port; + + index=strlen(pre); + printf(" %s",pre); + /* check if the device has connected children */ + has_child=0; + for(i=0;imaxchild;i++) { + if (dev->children[i]!=NULL) + has_child=1; + } + /* check if we are the last one */ + last_child=1; + if (dev->parent!=NULL) { + for(i=0;iparent->maxchild;i++) { + /* search for children */ + if (dev->parent->children[i]==dev) { + /* found our pointer, see if we have a little sister */ + port=i; + while(i++parent->maxchild) { + if (dev->parent->children[i]!=NULL) { + /* found a sister */ + last_child=0; + break; + } /* if */ + } /* while */ + } /* device found */ + } /* for all children of the parent */ + printf("\b+-"); + /* correct last child */ + if (last_child) { + pre[index-1]=' '; + } + } /* if not root hub */ + else + printf(" "); + printf("%d ",dev->devnum); + pre[index++]=' '; + pre[index++]= has_child ? '|' : ' '; + pre[index]=0; + printf(" %s (%s, %dmA)\n",usb_get_class_desc(dev->config.if_desc[0].bInterfaceClass), + dev->slow ? "1.5MBit/s" : "12MBit/s",dev->config.MaxPower * 2); + if (strlen(dev->mf) || + strlen(dev->prod) || + strlen(dev->serial)) + printf(" %s %s %s %s\n",pre,dev->mf,dev->prod,dev->serial); + printf(" %s\n",pre); + if (dev->maxchild>0) { + for(i=0;imaxchild;i++) { + if (dev->children[i]!=NULL) { + usb_show_tree_graph(dev->children[i],pre); + pre[index]=0; + } + } + } +} + +/* main routine for the tree command */ +void usb_show_tree(struct usb_device *dev) +{ + char preamble[32]; + + memset(preamble,0,32); + usb_show_tree_graph(dev,&preamble[0]); +} + + +/****************************************************************************** + * usb boot command intepreter. Derived from diskboot + */ +#ifdef CONFIG_USB_STORAGE +int do_usbboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + char *ep; + int dev, part=1, rcode; + ulong addr, cnt, checksum; + disk_partition_t info; + image_header_t *hdr; + block_dev_desc_t *stor_dev; + + + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_device = getenv ("bootdevice"); + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = getenv ("bootdevice"); + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (!boot_device) { + puts ("\n** No boot device **\n"); + return 1; + } + + dev = simple_strtoul(boot_device, &ep, 16); + stor_dev=usb_stor_get_dev(dev); + if (stor_dev->type == DEV_TYPE_UNKNOWN) { + printf ("\n** Device %d not available\n", dev); + return 1; + } + if (stor_dev->block_read==NULL) { + printf("storage device not initialized. Use usb scan\n"); + return 1; + } + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + return 1; + } + part = simple_strtoul(++ep, NULL, 16); + } + + if (get_partition_info (stor_dev, part, &info)) { + /* try to boot raw .... */ + strncpy((char *)&info.type[0], BOOT_PART_TYPE, sizeof(BOOT_PART_TYPE)); + strncpy((char *)&info.name[0], "Raw", 4); + info.start=0; + info.blksz=0x200; + info.size=2880; + printf("error reading partinfo...try to boot raw\n"); + } + if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) && + (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) { + printf ("\n** Invalid partition type \"%.32s\"" + " (expect \"" BOOT_PART_TYPE "\")\n", + info.type); + return 1; + } + printf ("\nLoading from USB device %d, partition %d: " + "Name: %.32s Type: %.32s\n", + dev, part, info.name, info.type); + + debug ("First Block: %ld, # of blocks: %ld, Block Size: %ld\n", + info.start, info.size, info.blksz); + + if (stor_dev->block_read(dev, info.start, 1, (ulong *)addr) != 1) { + printf ("** Read error on %d:%d\n", dev, part); + return 1; + } + + hdr = (image_header_t *)addr; + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + printf("\n** Bad Magic Number **\n"); + return 1; + } + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) { + puts ("\n** Bad Header Checksum **\n"); + return 1; + } + hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */ + + print_image_hdr (hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); + cnt += info.blksz - 1; + cnt /= info.blksz; + cnt -= 1; + + if (stor_dev->block_read (dev, info.start+1, cnt, + (ulong *)(addr+info.blksz)) != cnt) { + printf ("\n** Read error on %d:%d\n", dev, part); + return 1; + } + /* Loading ok, update default load address */ + load_addr = addr; + + flush_cache (addr, (cnt+1)*info.blksz); + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { + char *local_args[2]; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + local_args[0] = argv[0]; + local_args[1] = NULL; + printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); + rcode=do_bootm (cmdtp, 0, 1, local_args); + return rcode; + } + return 0; +} +#endif /* CONFIG_USB_STORAGE */ + + +/********************************************************************************* + * usb command intepreter + */ +int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + int i; + struct usb_device *dev = NULL; +#ifdef CONFIG_USB_STORAGE + block_dev_desc_t *stor_dev; +#endif + + if ((strncmp(argv[1], "reset", 5) == 0) || + (strncmp(argv[1], "start", 5) == 0)){ + usb_stop(); + printf("(Re)start USB...\n"); + i = usb_init(); +#ifdef CONFIG_USB_STORAGE + /* try to recognize storage devices immediately */ + if (i >= 0) + usb_stor_curr_dev = usb_stor_scan(1); +#endif + return 0; + } + if (strncmp(argv[1],"stop",4) == 0) { +#ifdef CONFIG_USB_KEYBOARD + if (argc==2) { + if (usb_kbd_deregister()!=0) { + printf("USB not stopped: usbkbd still using USB\n"); + return 1; + } + } + else { /* forced stop, switch console in to serial */ + console_assign(stdin,"serial"); + usb_kbd_deregister(); + } +#endif + printf("stopping USB..\n"); + usb_stop(); + return 0; + } + if (strncmp(argv[1],"tree",4) == 0) { + printf("\nDevice Tree:\n"); + usb_show_tree(usb_get_dev_index(0)); + return 0; + } + if (strncmp(argv[1],"inf",3) == 0) { + int d; + if (argc==2) { + for(d=0;ddevnum==i) + break; + } + if (dev==NULL) { + printf("*** NO Device avaiable ***\n"); + return 0; + } + else { + usb_display_desc(dev); + usb_display_config(dev); + } + } + return 0; + } +#ifdef CONFIG_USB_STORAGE + if (strncmp(argv[1], "scan", 4) == 0) { + printf(" NOTE: this command is obsolete and will be phased out\n"); + printf(" please use 'usb storage' for USB storage devices information\n\n"); + usb_stor_info(); + return 0; + } + + if (strncmp(argv[1], "stor", 4) == 0) { + usb_stor_info(); + return 0; + } + + if (strncmp(argv[1],"part",4) == 0) { + int devno, ok; + for (ok=0, devno=0; devnotype!=DEV_TYPE_UNKNOWN) { + ok++; + if (devno) + printf("\n"); + printf("print_part of %x\n",devno); + print_part(stor_dev); + } + } + if (!ok) { + printf("\nno USB devices available\n"); + return 1; + } + return 0; + } + if (strcmp(argv[1],"read") == 0) { + if (usb_stor_curr_dev<0) { + printf("no current device selected\n"); + return 1; + } + if (argc==5) { + unsigned long addr = simple_strtoul(argv[2], NULL, 16); + unsigned long blk = simple_strtoul(argv[3], NULL, 16); + unsigned long cnt = simple_strtoul(argv[4], NULL, 16); + unsigned long n; + printf ("\nUSB read: device %d block # %ld, count %ld ... ", + usb_stor_curr_dev, blk, cnt); + stor_dev=usb_stor_get_dev(usb_stor_curr_dev); + n = stor_dev->block_read(usb_stor_curr_dev, blk, cnt, (ulong *)addr); + printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR"); + if (n==cnt) + return 0; + return 1; + } + } + if (strncmp(argv[1], "dev", 3) == 0) { + if (argc == 3) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + printf ("\nUSB device %d: ", dev); + if (dev >= USB_MAX_STOR_DEV) { + printf("unknown device\n"); + return 1; + } + printf ("\n Device %d: ", dev); + stor_dev=usb_stor_get_dev(dev); + dev_print(stor_dev); + if (stor_dev->type == DEV_TYPE_UNKNOWN) { + return 1; + } + usb_stor_curr_dev = dev; + printf("... is now current device\n"); + return 0; + } + else { + printf ("\nUSB device %d: ", usb_stor_curr_dev); + stor_dev=usb_stor_get_dev(usb_stor_curr_dev); + dev_print(stor_dev); + if (stor_dev->type == DEV_TYPE_UNKNOWN) { + return 1; + } + return 0; + } + return 0; + } +#endif /* CONFIG_USB_STORAGE */ + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + + +#endif /* (CONFIG_COMMANDS & CFG_CMD_USB) */ + + +#if (CONFIG_COMMANDS & CFG_CMD_USB) + +#ifdef CONFIG_USB_STORAGE +U_BOOT_CMD( + usb, 5, 1, do_usb, + "usb - USB sub-system\n", + "reset - reset (rescan) USB controller\n" + "usb stop [f] - stop USB [f]=force stop\n" + "usb tree - show USB device tree\n" + "usb info [dev] - show available USB devices\n" + "usb storage - show details of USB storage devices\n" + "usb dev [dev] - show or set current USB storage device\n" + "usb part [dev] - print partition table of one or all USB storage devices\n" + "usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n" + " to memory address `addr'\n" +); + + +U_BOOT_CMD( + usbboot, 3, 1, do_usbboot, + "usbboot - boot from USB device\n", + "loadAddr dev:part\n" +); + +#else +U_BOOT_CMD( + usb, 5, 1, do_usb, + "usb - USB sub-system\n", + "reset - reset (rescan) USB controller\n" + "usb tree - show USB device tree\n" + "usb info [dev] - show available USB devices\n" +); +#endif +#endif diff --git a/common/cmd_vfd.c b/common/cmd_vfd.c new file mode 100644 index 0000000..5e623a2 --- /dev/null +++ b/common/cmd_vfd.c @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Command to load a splash screen to the VFDs. + * NOTE that this will be controlled by a key combination when + * the keyboard stuff works. For now the user has to enter a + * bitmap number (only VFD_TEST_LOGO is supported now - 16.10.2002). + * Added VFD_REMOTE_LOGO (same as VFD_TEST_LOGO but a different color) + * on 20.10.2002. + * + * This rather crudely requires that each bitmap be included as a + * header file. + */ +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_VFD) + +#include +#define VFD_TEST_LOGO_BMPNR 0 +#define VFD_REMOTE_LOGO_BMPNR 1 + +extern int transfer_pic(unsigned char, unsigned char *, int, int); + +int trab_vfd (ulong bitmap); + +int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong bitmap; + + if (argc != 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (argv[1][0] == '/') { /* select bitmap by number */ + bitmap = simple_strtoul(argv[1]+1, NULL, 10); + return (trab_vfd(bitmap)); + } + + /* display bitmap at given address */ + bitmap = simple_strtoul(argv[1], NULL, 16); + transfer_pic(3, (uchar *)bitmap, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH); + return 0; +} + +U_BOOT_CMD( + vfd, 2, 0, do_vfd, + "vfd - load a bitmap to the VFDs on TRAB\n", + "/N\n" + " - load bitmap N to the VFDs (N is _decimal_ !!!)\n" + "vfd ADDR\n" + " - load bitmap at address ADDR\n" +); +#endif /* CFG_CMD_VFD */ + +#ifdef CONFIG_VFD +int trab_vfd (ulong bitmap) +{ + uchar *addr; + char *s; + + switch (bitmap) { + case VFD_TEST_LOGO_BMPNR: + if ((s = getenv ("bitmap0")) != NULL) { + addr = (uchar *)simple_strtoul (s, NULL, 16); + } else { + addr = &vfd_test_logo_bitmap[0]; + } + break; + case VFD_REMOTE_LOGO_BMPNR: + if ((s = getenv ("bitmap1")) != NULL) { + addr = (uchar *)simple_strtoul (s, NULL, 16); + } else { + addr = &vfd_remote_logo_bitmap[0]; + } + break; + default: + printf("Unknown bitmap %ld\n", bitmap); + return 1; + } + transfer_pic(3, addr, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH); + return 0; +} +#endif /* CONFIG_VFD */ diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c new file mode 100644 index 0000000..8359153 --- /dev/null +++ b/common/cmd_ximg.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Kai-Uwe Bloem, Auerswald GmbH & Co KG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if (CONFIG_COMMANDS & CFG_CMD_XIMG) + +/* + * Multi Image extract + */ +#include +#include +#include +#include + +int +do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr = load_addr, dest = 0; + ulong data, len, checksum; + ulong *len_ptr; + int i, verify, part = 0; + char pbuf[10], *s; + image_header_t header; + + s = getenv("verify"); + verify = (s && (*s == 'n')) ? 0 : 1; + + if (argc > 1) { + addr = simple_strtoul(argv[1], NULL, 16); + } + if (argc > 2) { + part = simple_strtoul(argv[2], NULL, 16); + } + if (argc > 3) { + dest = simple_strtoul(argv[3], NULL, 16); + } + + printf("## Copying from image at %08lx ...\n", addr); + + /* Copy header so we can blank CRC field for re-calculation */ + memmove(&header, (char *) addr, sizeof (image_header_t)); + + if (ntohl(header.ih_magic) != IH_MAGIC) { + printf("Bad Magic Number\n"); + return 1; + } + + data = (ulong) & header; + len = sizeof (image_header_t); + + checksum = ntohl(header.ih_hcrc); + header.ih_hcrc = 0; + + if (crc32(0, (char *) data, len) != checksum) { + printf("Bad Header Checksum\n"); + return 1; + } +#ifdef DEBUG + print_image_hdr((image_header_t *) addr); +#endif + + data = addr + sizeof (image_header_t); + len = ntohl(header.ih_size); + + if (header.ih_type != IH_TYPE_MULTI) { + printf("Wrong Image Type for %s command\n", cmdtp->name); + return 1; + } + + if (header.ih_comp != IH_COMP_NONE) { + printf("Wrong Compression Type for %s command\n", cmdtp->name); + return 1; + } + + if (verify) { + printf(" Verifying Checksum ... "); + if (crc32(0, (char *) data, len) != ntohl(header.ih_dcrc)) { + printf("Bad Data CRC\n"); + return 1; + } + printf("OK\n"); + } + + len_ptr = (ulong *) data; + + data += 4; /* terminator */ + for (i = 0; len_ptr[i]; ++i) { + data += 4; + if (argc > 2 && part > i) { + u_long tail; + len = ntohl(len_ptr[i]); + tail = len % 4; + data += len; + if (tail) { + data += 4 - tail; + } + } + } + if (argc > 2 && part >= i) { + printf("Bad Image Part\n"); + return 1; + } + len = ntohl(len_ptr[part]); + + if (argc > 3) { + memcpy((char *) dest, (char *) data, len); + } + + sprintf(pbuf, "%8lx", data); + setenv("fileaddr", pbuf); + sprintf(pbuf, "%8lx", len); + setenv("filesize", pbuf); + + return 0; +} + +U_BOOT_CMD(imxtract, 4, 1, do_imgextract, + "imxtract- extract a part of a multi-image\n", + "addr part [dest]\n" + " - extract from image at and copy to \n"); + +#endif /* CONFIG_COMMANDS & CFG_CMD_XIMG */ diff --git a/common/command.c b/common/command.c new file mode 100644 index 0000000..2b4c554 --- /dev/null +++ b/common/command.c @@ -0,0 +1,654 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Command Processor Table + */ + +#include +#include + +int +do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern char version_string[]; + printf ("\n%s\n", version_string); + return 0; +} + +U_BOOT_CMD( + version, 1, 1, do_version, + "version - print monitor version\n", + NULL +); + +int +do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i, putnl = 1; + + for (i = 1; i < argc; i++) { + char *p = argv[i], c; + + if (i > 1) + putc(' '); + while ((c = *p++) != '\0') { + if (c == '\\' && *p == 'c') { + putnl = 0; + p++; + } else { + putc(c); + } + } + } + + if (putnl) + putc('\n'); + return 0; +} + +U_BOOT_CMD( + echo, CFG_MAXARGS, 1, do_echo, + "echo - echo args to console\n", + "[args..]\n" + " - echo args to console; \\c suppresses newline\n" +); + +#ifdef CFG_HUSH_PARSER + +int +do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char **ap; + int left, adv, expr, last_expr, neg, last_cmp; + + /* args? */ + if (argc < 3) + return 1; + +#if 0 + { + printf("test:"); + left = 1; + while (argv[left]) + printf(" %s", argv[left++]); + } +#endif + + last_expr = 0; + left = argc - 1; ap = argv + 1; + if (left > 0 && strcmp(ap[0], "!") == 0) { + neg = 1; + ap++; + left--; + } else + neg = 0; + + expr = -1; + last_cmp = -1; + last_expr = -1; + while (left > 0) { + + if (strcmp(ap[0], "-o") == 0 || strcmp(ap[0], "-a") == 0) + adv = 1; + else if (strcmp(ap[0], "-z") == 0 || strcmp(ap[0], "-n") == 0) + adv = 2; + else + adv = 3; + + if (left < adv) { + expr = 1; + break; + } + + if (adv == 1) { + if (strcmp(ap[0], "-o") == 0) { + last_expr = expr; + last_cmp = 0; + } else if (strcmp(ap[0], "-a") == 0) { + last_expr = expr; + last_cmp = 1; + } else { + expr = 1; + break; + } + } + + if (adv == 2) { + if (strcmp(ap[0], "-z") == 0) + expr = strlen(ap[1]) == 0 ? 1 : 0; + else if (strcmp(ap[0], "-n") == 0) + expr = strlen(ap[1]) == 0 ? 0 : 1; + else { + expr = 1; + break; + } + + if (last_cmp == 0) + expr = last_expr || expr; + else if (last_cmp == 1) + expr = last_expr && expr; + last_cmp = -1; + } + + if (adv == 3) { + if (strcmp(ap[1], "=") == 0) + expr = strcmp(ap[0], ap[2]) == 0; + else if (strcmp(ap[1], "!=") == 0) + expr = strcmp(ap[0], ap[2]) != 0; + else if (strcmp(ap[1], ">") == 0) + expr = strcmp(ap[0], ap[2]) > 0; + else if (strcmp(ap[1], "<") == 0) + expr = strcmp(ap[0], ap[2]) < 0; + else if (strcmp(ap[1], "-eq") == 0) + expr = simple_strtol(ap[0], NULL, 10) == simple_strtol(ap[2], NULL, 10); + else if (strcmp(ap[1], "-ne") == 0) + expr = simple_strtol(ap[0], NULL, 10) != simple_strtol(ap[2], NULL, 10); + else if (strcmp(ap[1], "-lt") == 0) + expr = simple_strtol(ap[0], NULL, 10) < simple_strtol(ap[2], NULL, 10); + else if (strcmp(ap[1], "-le") == 0) + expr = simple_strtol(ap[0], NULL, 10) <= simple_strtol(ap[2], NULL, 10); + else if (strcmp(ap[1], "-gt") == 0) + expr = simple_strtol(ap[0], NULL, 10) > simple_strtol(ap[2], NULL, 10); + else if (strcmp(ap[1], "-ge") == 0) + expr = simple_strtol(ap[0], NULL, 10) >= simple_strtol(ap[2], NULL, 10); + else { + expr = 1; + break; + } + + if (last_cmp == 0) + expr = last_expr || expr; + else if (last_cmp == 1) + expr = last_expr && expr; + last_cmp = -1; + } + + ap += adv; left -= adv; + } + + if (neg) + expr = !expr; + + expr = !expr; + +#if 0 + printf(": returns %d\n", expr); +#endif + + return expr; +} + +U_BOOT_CMD( + test, CFG_MAXARGS, 1, do_test, + "test - minimal test like /bin/sh\n", + "[args..]\n" + " - test functionality\n" +); + +int +do_exit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int r; + + r = 0; + if (argc > 1) + r = simple_strtoul(argv[1], NULL, 10); + + return -r - 2; +} + +U_BOOT_CMD( + exit, 2, 1, do_exit, + "exit - exit script\n", + " - exit functionality\n" +); + + +#endif + +/* + * Use puts() instead of printf() to avoid printf buffer overflow + * for long help messages + */ +int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i; + int rcode = 0; + + if (argc == 1) { /*show list of commands */ + + int cmd_items = &__u_boot_cmd_end - + &__u_boot_cmd_start; /* pointer arith! */ + cmd_tbl_t *cmd_array[cmd_items]; + int i, j, swaps; + + /* Make array of commands from .uboot_cmd section */ + cmdtp = &__u_boot_cmd_start; + for (i = 0; i < cmd_items; i++) { + cmd_array[i] = cmdtp++; + } + + /* Sort command list (trivial bubble sort) */ + for (i = cmd_items - 1; i > 0; --i) { + swaps = 0; + for (j = 0; j < i; ++j) { + if (strcmp (cmd_array[j]->name, + cmd_array[j + 1]->name) > 0) { + cmd_tbl_t *tmp; + tmp = cmd_array[j]; + cmd_array[j] = cmd_array[j + 1]; + cmd_array[j + 1] = tmp; + ++swaps; + } + } + if (!swaps) + break; + } + + /* print short help (usage) */ + for (i = 0; i < cmd_items; i++) { + const char *usage = cmd_array[i]->usage; + + /* allow user abort */ + if (ctrlc ()) + return 1; + if (usage == NULL) + continue; + puts (usage); + } + return 0; + } + /* + * command help (long version) + */ + for (i = 1; i < argc; ++i) { + if ((cmdtp = find_cmd (argv[i])) != NULL) { +#ifdef CFG_LONGHELP + /* found - print (long) help info */ + puts (cmdtp->name); + putc (' '); + if (cmdtp->help) { + puts (cmdtp->help); + } else { + puts ("- No help available.\n"); + rcode = 1; + } + putc ('\n'); +#else /* no long help available */ + if (cmdtp->usage) + puts (cmdtp->usage); +#endif /* CFG_LONGHELP */ + } else { + printf ("Unknown command '%s' - try 'help'" + " without arguments for list of all" + " known commands\n\n", argv[i] + ); + rcode = 1; + } + } + return rcode; +} + + +U_BOOT_CMD( + help, CFG_MAXARGS, 1, do_help, + "help - print online help\n", + "[command ...]\n" + " - show help information (for 'command')\n" + "'help' prints online help for the monitor commands.\n\n" + "Without arguments, it prints a short usage message for all commands.\n\n" + "To get detailed help information for specific commands you can type\n" + "'help' with one or more command names as arguments.\n" +); + +/* This do not ust the U_BOOT_CMD macro as ? can't be used in symbol names */ +#ifdef CFG_LONGHELP +cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = { + "?", CFG_MAXARGS, 1, do_help, + "? - alias for 'help'\n", + NULL +}; +#else +cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = { + "?", CFG_MAXARGS, 1, do_help, + "? - alias for 'help'\n" +}; +#endif /* CFG_LONGHELP */ + +/*************************************************************************** + * find command table entry for a command + */ +cmd_tbl_t *find_cmd (const char *cmd) +{ + cmd_tbl_t *cmdtp; + cmd_tbl_t *cmdtp_temp = &__u_boot_cmd_start; /*Init value */ + const char *p; + int len; + int n_found = 0; + + /* + * Some commands allow length modifiers (like "cp.b"); + * compare command name only until first dot. + */ + len = ((p = strchr(cmd, '.')) == NULL) ? strlen (cmd) : (p - cmd); + + for (cmdtp = &__u_boot_cmd_start; + cmdtp != &__u_boot_cmd_end; + cmdtp++) { + if (strncmp (cmd, cmdtp->name, len) == 0) { + if (len == strlen (cmdtp->name)) + return cmdtp; /* full match */ + + cmdtp_temp = cmdtp; /* abbreviated command ? */ + n_found++; + } + } + if (n_found == 1) { /* exactly one match */ + return cmdtp_temp; + } + + return NULL; /* not found or ambiguous command */ +} + +#ifdef CONFIG_AUTO_COMPLETE + +int var_complete(int argc, char *argv[], char last_char, int maxv, char *cmdv[]) +{ + static char tmp_buf[512]; + int space; + + space = last_char == '\0' || last_char == ' ' || last_char == '\t'; + + if (space && argc == 1) + return env_complete("", maxv, cmdv, sizeof(tmp_buf), tmp_buf); + + if (!space && argc == 2) + return env_complete(argv[1], maxv, cmdv, sizeof(tmp_buf), tmp_buf); + + return 0; +} + +static void install_auto_complete_handler(const char *cmd, + int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[])) +{ + cmd_tbl_t *cmdtp; + + cmdtp = find_cmd(cmd); + if (cmdtp == NULL) + return; + + cmdtp->complete = complete; +} + +void install_auto_complete(void) +{ + install_auto_complete_handler("printenv", var_complete); + install_auto_complete_handler("setenv", var_complete); +#if (CONFIG_COMMANDS & CFG_CMD_RUN) + install_auto_complete_handler("run", var_complete); +#endif +} + +/*************************************************************************************/ + +static int complete_cmdv(int argc, char *argv[], char last_char, int maxv, char *cmdv[]) +{ + cmd_tbl_t *cmdtp; + const char *p; + int len, clen; + int n_found = 0; + const char *cmd; + + /* sanity? */ + if (maxv < 2) + return -2; + + cmdv[0] = NULL; + + if (argc == 0) { + /* output full list of commands */ + for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + if (n_found >= maxv - 2) { + cmdv[n_found++] = "..."; + break; + } + cmdv[n_found++] = cmdtp->name; + } + cmdv[n_found] = NULL; + return n_found; + } + + /* more than one arg or one but the start of the next */ + if (argc > 1 || (last_char == '\0' || last_char == ' ' || last_char == '\t')) { + cmdtp = find_cmd(argv[0]); + if (cmdtp == NULL || cmdtp->complete == NULL) { + cmdv[0] = NULL; + return 0; + } + return (*cmdtp->complete)(argc, argv, last_char, maxv, cmdv); + } + + cmd = argv[0]; + /* + * Some commands allow length modifiers (like "cp.b"); + * compare command name only until first dot. + */ + p = strchr(cmd, '.'); + if (p == NULL) + len = strlen(cmd); + else + len = p - cmd; + + /* return the partial matches */ + for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + + clen = strlen(cmdtp->name); + if (clen < len) + continue; + + if (memcmp(cmd, cmdtp->name, len) != 0) + continue; + + /* too many! */ + if (n_found >= maxv - 2) { + cmdv[n_found++] = "..."; + break; + } + + cmdv[n_found++] = cmdtp->name; + } + + cmdv[n_found] = NULL; + return n_found; +} + +static int make_argv(char *s, int argvsz, char *argv[]) +{ + int argc = 0; + + /* split into argv */ + while (argc < argvsz - 1) { + + /* skip any white space */ + while ((*s == ' ') || (*s == '\t')) + ++s; + + if (*s == '\0') /* end of s, no more args */ + break; + + argv[argc++] = s; /* begin of argument string */ + + /* find end of string */ + while (*s && (*s != ' ') && (*s != '\t')) + ++s; + + if (*s == '\0') /* end of s, no more args */ + break; + + *s++ = '\0'; /* terminate current arg */ + } + argv[argc] = NULL; + + return argc; +} + +static void print_argv(const char *banner, const char *leader, const char *sep, int linemax, char *argv[]) +{ + int ll = leader != NULL ? strlen(leader) : 0; + int sl = sep != NULL ? strlen(sep) : 0; + int len, i; + + if (banner) { + puts("\n"); + puts(banner); + } + + i = linemax; /* force leader and newline */ + while (*argv != NULL) { + len = strlen(*argv) + sl; + if (i + len >= linemax) { + puts("\n"); + if (leader) + puts(leader); + i = ll - sl; + } else if (sep) + puts(sep); + puts(*argv++); + i += len; + } + printf("\n"); +} + +static int find_common_prefix(char *argv[]) +{ + int i, len; + char *anchor, *s, *t; + + if (*argv == NULL) + return 0; + + /* begin with max */ + anchor = *argv++; + len = strlen(anchor); + while ((t = *argv++) != NULL) { + s = anchor; + for (i = 0; i < len; i++, t++, s++) { + if (*t != *s) + break; + } + len = s - anchor; + } + return len; +} + +static char tmp_buf[CFG_CBSIZE]; /* copy of console I/O buffer */ + +int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp) +{ + int n = *np, col = *colp; + char *argv[CFG_MAXARGS + 1]; /* NULL terminated */ + char *cmdv[20]; + char *s, *t; + const char *sep; + int i, j, k, len, seplen, argc; + int cnt; + char last_char; + + if (strcmp(prompt, CFG_PROMPT) != 0) + return 0; /* not in normal console */ + + cnt = strlen(buf); + if (cnt >= 1) + last_char = buf[cnt - 1]; + else + last_char = '\0'; + + /* copy to secondary buffer which will be affected */ + strcpy(tmp_buf, buf); + + /* separate into argv */ + argc = make_argv(tmp_buf, sizeof(argv)/sizeof(argv[0]), argv); + + /* do the completion and return the possible completions */ + i = complete_cmdv(argc, argv, last_char, sizeof(cmdv)/sizeof(cmdv[0]), cmdv); + + /* no match; bell and out */ + if (i == 0) { + if (argc > 1) /* allow tab for non command */ + return 0; + putc('\a'); + return 1; + } + + s = NULL; + len = 0; + sep = NULL; + seplen = 0; + if (i == 1) { /* one match; perfect */ + k = strlen(argv[argc - 1]); + s = cmdv[0] + k; + len = strlen(s); + sep = " "; + seplen = 1; + } else if (i > 1 && (j = find_common_prefix(cmdv)) != 0) { /* more */ + k = strlen(argv[argc - 1]); + j -= k; + if (j > 0) { + s = cmdv[0] + k; + len = j; + } + } + + if (s != NULL) { + k = len + seplen; + /* make sure it fits */ + if (n + k >= CFG_CBSIZE - 2) { + putc('\a'); + return 1; + } + + t = buf + cnt; + for (i = 0; i < len; i++) + *t++ = *s++; + if (sep != NULL) + for (i = 0; i < seplen; i++) + *t++ = sep[i]; + *t = '\0'; + n += k; + col += k; + puts(t - k); + if (sep == NULL) + putc('\a'); + *np = n; + *colp = col; + } else { + print_argv(NULL, " ", " ", 78, cmdv); + + puts(prompt); + puts(buf); + } + return 1; +} + +#endif diff --git a/common/console.c b/common/console.c new file mode 100644 index 0000000..3c535d2 --- /dev/null +++ b/common/console.c @@ -0,0 +1,586 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_AMIGAONEG3SE +int console_changed = 0; +#endif + +#ifdef CFG_CONSOLE_IS_IN_ENV +/* + * if overwrite_console returns 1, the stdin, stderr and stdout + * are switched to the serial port, else the settings in the + * environment are used + */ +#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console (void); +#define OVERWRITE_CONSOLE overwrite_console () +#else +#define OVERWRITE_CONSOLE 0 +#endif /* CFG_CONSOLE_OVERWRITE_ROUTINE */ + +#endif /* CFG_CONSOLE_IS_IN_ENV */ + +static int console_setfile (int file, device_t * dev) +{ + DECLARE_GLOBAL_DATA_PTR; + int error = 0; + + if (dev == NULL) + return -1; + + switch (file) { + case stdin: + case stdout: + case stderr: + /* Start new device */ + if (dev->start) { + error = dev->start (); + /* If it's not started dont use it */ + if (error < 0) + break; + } + + /* Assign the new device (leaving the existing one started) */ + stdio_devices[file] = dev; + + /* + * Update monitor functions + * (to use the console stuff by other applications) + */ + switch (file) { + case stdin: + gd->jt[XF_getc] = dev->getc; + gd->jt[XF_tstc] = dev->tstc; + break; + case stdout: + gd->jt[XF_putc] = dev->putc; + gd->jt[XF_puts] = dev->puts; + gd->jt[XF_printf] = printf; + break; + } + break; + + default: /* Invalid file ID */ + error = -1; + } + return error; +} + +/** U-Boot INITIAL CONSOLE-NOT COMPATIBLE FUNCTIONS *************************/ + +void serial_printf (const char *fmt, ...) +{ + va_list args; + uint i; + char printbuffer[CFG_PBSIZE]; + + va_start (args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vsprintf (printbuffer, fmt, args); + va_end (args); + + serial_puts (printbuffer); +} + +int fgetc (int file) +{ + if (file < MAX_FILES) + return stdio_devices[file]->getc (); + + return -1; +} + +int ftstc (int file) +{ + if (file < MAX_FILES) + return stdio_devices[file]->tstc (); + + return -1; +} + +void fputc (int file, const char c) +{ + if (file < MAX_FILES) + stdio_devices[file]->putc (c); +} + +void fputs (int file, const char *s) +{ + if (file < MAX_FILES) + stdio_devices[file]->puts (s); +} + +void fprintf (int file, const char *fmt, ...) +{ + va_list args; + uint i; + char printbuffer[CFG_PBSIZE]; + + va_start (args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vsprintf (printbuffer, fmt, args); + va_end (args); + + /* Send to desired file */ + fputs (file, printbuffer); +} + +/** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/ + +int getc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->flags & GD_FLG_DEVINIT) { + /* Get from the standard input */ + return fgetc (stdin); + } + + /* Send directly to the handler */ + return serial_getc (); +} + +int tstc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->flags & GD_FLG_DEVINIT) { + /* Test the standard input */ + return ftstc (stdin); + } + + /* Send directly to the handler */ + return serial_tstc (); +} + +void putc (const char c) +{ + DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SILENT_CONSOLE + if (gd->flags & GD_FLG_SILENT) + return; +#endif + + if (gd->flags & GD_FLG_DEVINIT) { + /* Send to the standard output */ + fputc (stdout, c); + } else { + /* Send directly to the handler */ + serial_putc (c); + } +} + +void puts (const char *s) +{ + DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SILENT_CONSOLE + if (gd->flags & GD_FLG_SILENT) + return; +#endif + + if (gd->flags & GD_FLG_DEVINIT) { + /* Send to the standard output */ + fputs (stdout, s); + } else { + /* Send directly to the handler */ + serial_puts (s); + } +} + +void printf (const char *fmt, ...) +{ + va_list args; + uint i; + char printbuffer[CFG_PBSIZE]; + + va_start (args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vsprintf (printbuffer, fmt, args); + va_end (args); + + /* Print the string */ + puts (printbuffer); +} + +void vprintf (const char *fmt, va_list args) +{ + uint i; + char printbuffer[CFG_PBSIZE]; + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vsprintf (printbuffer, fmt, args); + + /* Print the string */ + puts (printbuffer); +} + +/* test if ctrl-c was pressed */ +static int ctrlc_disabled = 0; /* see disable_ctrl() */ +static int ctrlc_was_pressed = 0; +int ctrlc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (!ctrlc_disabled && gd->have_console) { + if (tstc ()) { + switch (getc ()) { + case 0x03: /* ^C - Control C */ + ctrlc_was_pressed = 1; + return 1; + default: + break; + } + } + } + return 0; +} + +/* pass 1 to disable ctrlc() checking, 0 to enable. + * returns previous state + */ +int disable_ctrlc (int disable) +{ + int prev = ctrlc_disabled; /* save previous state */ + + ctrlc_disabled = disable; + return prev; +} + +int had_ctrlc (void) +{ + return ctrlc_was_pressed; +} + +void clear_ctrlc (void) +{ + ctrlc_was_pressed = 0; +} + +#ifdef CONFIG_MODEM_SUPPORT_DEBUG +char screen[1024]; +char *cursor = screen; +int once = 0; +inline void dbg(const char *fmt, ...) +{ + va_list args; + uint i; + char printbuffer[CFG_PBSIZE]; + + if (!once) { + memset(screen, 0, sizeof(screen)); + once++; + } + + va_start(args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vsprintf(printbuffer, fmt, args); + va_end(args); + + if ((screen + sizeof(screen) - 1 - cursor) < strlen(printbuffer)+1) { + memset(screen, 0, sizeof(screen)); + cursor = screen; + } + sprintf(cursor, printbuffer); + cursor += strlen(printbuffer); + +} +#else +inline void dbg(const char *fmt, ...) +{ +} +#endif + +/** U-Boot INIT FUNCTIONS *************************************************/ + +int console_assign (int file, char *devname) +{ + int flag, i; + + /* Check for valid file */ + switch (file) { + case stdin: + flag = DEV_FLAGS_INPUT; + break; + case stdout: + case stderr: + flag = DEV_FLAGS_OUTPUT; + break; + default: + return -1; + } + + /* Check for valid device name */ + + for (i = 1; i <= ListNumItems (devlist); i++) { + device_t *dev = ListGetPtrToItem (devlist, i); + + if (strcmp (devname, dev->name) == 0) { + if (dev->flags & flag) + return console_setfile (file, dev); + + return -1; + } + } + + return -1; +} + +/* Called before relocation - use serial functions */ +int console_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->have_console = 1; + +#ifdef CONFIG_SILENT_CONSOLE + if (getenv("silent") != NULL) + gd->flags |= GD_FLG_SILENT; +#endif + + return (0); +} + +#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SPLASH_SCREEN) || defined(CONFIG_SILENT_CONSOLE) +/* search a device */ +device_t *search_device (int flags, char *name) +{ + int i, items; + device_t *dev = NULL; + + items = ListNumItems (devlist); + if (name == NULL) + return dev; + + for (i = 1; i <= items; i++) { + dev = ListGetPtrToItem (devlist, i); + if ((dev->flags & flags) && (strcmp (name, dev->name) == 0)) { + break; + } + } + return dev; +} +#endif /* CFG_CONSOLE_IS_IN_ENV || CONFIG_SPLASH_SCREEN */ + +#ifdef CFG_CONSOLE_IS_IN_ENV +/* Called after the relocation - use desired console functions */ +int console_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + char *stdinname, *stdoutname, *stderrname; + device_t *inputdev = NULL, *outputdev = NULL, *errdev = NULL; +#ifdef CFG_CONSOLE_ENV_OVERWRITE + int i; +#endif /* CFG_CONSOLE_ENV_OVERWRITE */ + + /* set default handlers at first */ + gd->jt[XF_getc] = serial_getc; + gd->jt[XF_tstc] = serial_tstc; + gd->jt[XF_putc] = serial_putc; + gd->jt[XF_puts] = serial_puts; + gd->jt[XF_printf] = serial_printf; + + /* stdin stdout and stderr are in environment */ + /* scan for it */ + stdinname = getenv ("stdin"); + stdoutname = getenv ("stdout"); + stderrname = getenv ("stderr"); + + if (OVERWRITE_CONSOLE == 0) { /* if not overwritten by config switch */ + inputdev = search_device (DEV_FLAGS_INPUT, stdinname); + outputdev = search_device (DEV_FLAGS_OUTPUT, stdoutname); + errdev = search_device (DEV_FLAGS_OUTPUT, stderrname); + } + /* if the devices are overwritten or not found, use default device */ + if (inputdev == NULL) { + inputdev = search_device (DEV_FLAGS_INPUT, "serial"); + } + if (outputdev == NULL) { + outputdev = search_device (DEV_FLAGS_OUTPUT, "serial"); + } + if (errdev == NULL) { + errdev = search_device (DEV_FLAGS_OUTPUT, "serial"); + } + /* Initializes output console first */ + if (outputdev != NULL) { + console_setfile (stdout, outputdev); + } + if (errdev != NULL) { + console_setfile (stderr, errdev); + } + if (inputdev != NULL) { + console_setfile (stdin, inputdev); + } + + gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */ + +#ifndef CFG_CONSOLE_INFO_QUIET + /* Print information */ + puts ("In: "); + if (stdio_devices[stdin] == NULL) { + puts ("No input devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stdin]->name); + } + + puts ("Out: "); + if (stdio_devices[stdout] == NULL) { + puts ("No output devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stdout]->name); + } + + puts ("Err: "); + if (stdio_devices[stderr] == NULL) { + puts ("No error devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stderr]->name); + } +#endif /* CFG_CONSOLE_INFO_QUIET */ + +#ifdef CFG_CONSOLE_ENV_OVERWRITE + /* set the environment variables (will overwrite previous env settings) */ + for (i = 0; i < 3; i++) { + setenv (stdio_names[i], stdio_devices[i]->name); + } +#endif /* CFG_CONSOLE_ENV_OVERWRITE */ + +#if 0 + /* If nothing usable installed, use only the initial console */ + if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL)) + return (0); +#endif + return (0); +} + +#else /* CFG_CONSOLE_IS_IN_ENV */ + +/* Called after the relocation - use desired console functions */ +int console_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + device_t *inputdev = NULL, *outputdev = NULL; + int i, items = ListNumItems (devlist); + +#ifdef CONFIG_SPLASH_SCREEN + /* suppress all output if splash screen is enabled and we have + a bmp to display */ + if (getenv("splashimage") != NULL) + outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev"); +#endif + +#ifdef CONFIG_SILENT_CONSOLE + /* Suppress all output if "silent" mode requested */ + if (gd->flags & GD_FLG_SILENT) + outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev"); +#endif + + /* Scan devices looking for input and output devices */ + for (i = 1; + (i <= items) && ((inputdev == NULL) || (outputdev == NULL)); + i++ + ) { + device_t *dev = ListGetPtrToItem (devlist, i); + + if ((dev->flags & DEV_FLAGS_INPUT) && (inputdev == NULL)) { + inputdev = dev; + } + if ((dev->flags & DEV_FLAGS_OUTPUT) && (outputdev == NULL)) { + outputdev = dev; + } + } + + /* Initializes output console first */ + if (outputdev != NULL) { + console_setfile (stdout, outputdev); + console_setfile (stderr, outputdev); + } + + /* Initializes input console */ + if (inputdev != NULL) { + console_setfile (stdin, inputdev); + } + + gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */ + +#ifndef CFG_CONSOLE_INFO_QUIET + /* Print information */ + puts ("In: "); + if (stdio_devices[stdin] == NULL) { + puts ("No input devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stdin]->name); + } + + puts ("Out: "); + if (stdio_devices[stdout] == NULL) { + puts ("No output devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stdout]->name); + } + + puts ("Err: "); + if (stdio_devices[stderr] == NULL) { + puts ("No error devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stderr]->name); + } +#endif /* CFG_CONSOLE_INFO_QUIET */ + + /* Setting environment variables */ + for (i = 0; i < 3; i++) { + setenv (stdio_names[i], stdio_devices[i]->name); + } + +#if 0 + /* If nothing usable installed, use only the initial console */ + if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL)) + return (0); +#endif + + return (0); +} + +#endif /* CFG_CONSOLE_IS_IN_ENV */ diff --git a/common/devices.c b/common/devices.c new file mode 100644 index 0000000..bd4dfa0 --- /dev/null +++ b/common/devices.c @@ -0,0 +1,216 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_LOGBUFFER +#include +#endif +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +#include +#endif + +list_t devlist = 0; +device_t *stdio_devices[] = { NULL, NULL, NULL }; +char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" }; + +#if defined(CONFIG_SPLASH_SCREEN) && !defined(CFG_DEVICE_NULLDEV) +#define CFG_DEVICE_NULLDEV 1 +#endif + + +#ifdef CFG_DEVICE_NULLDEV +void nulldev_putc(const char c) +{ + /* nulldev is empty! */ +} + +void nulldev_puts(const char *s) +{ + /* nulldev is empty! */ +} + +int nulldev_input(void) +{ + /* nulldev is empty! */ + return 0; +} +#endif + +/************************************************************************** + * SYSTEM DRIVERS + ************************************************************************** + */ + +static void drv_system_init (void) +{ + device_t dev; + + memset (&dev, 0, sizeof (dev)); + + strcpy (dev.name, "serial"); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + dev.putc = serial_buffered_putc; + dev.puts = serial_buffered_puts; + dev.getc = serial_buffered_getc; + dev.tstc = serial_buffered_tstc; +#else + dev.putc = serial_putc; + dev.puts = serial_puts; + dev.getc = serial_getc; + dev.tstc = serial_tstc; +#endif + + device_register (&dev); + +#ifdef CFG_DEVICE_NULLDEV + memset (&dev, 0, sizeof (dev)); + + strcpy (dev.name, "nulldev"); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.putc = nulldev_putc; + dev.puts = nulldev_puts; + dev.getc = nulldev_input; + dev.tstc = nulldev_input; + + device_register (&dev); +#endif +} + +/************************************************************************** + * DEVICES + ************************************************************************** + */ + +int device_register (device_t * dev) +{ + ListInsertItem (devlist, dev, LIST_END); + return 0; +} + +/* deregister the device "devname". + * returns 0 if success, -1 if device is assigned and 1 if devname not found + */ +#ifdef CFG_DEVICE_DEREGISTER +int device_deregister(char *devname) +{ + int i,l,dev_index; + device_t *dev = NULL; + char temp_names[3][8]; + + dev_index=-1; + for (i=1; i<=ListNumItems(devlist); i++) { + dev = ListGetPtrToItem (devlist, i); + if(strcmp(dev->name,devname)==0) { + dev_index=i; + break; + } + } + if(dev_index<0) /* device not found */ + return 0; + /* get stdio devices (ListRemoveItem changes the dev list) */ + for (l=0 ; l< MAX_FILES; l++) { + if (stdio_devices[l] == dev) { + /* Device is assigned -> report error */ + return -1; + } + memcpy (&temp_names[l][0], + stdio_devices[l]->name, + sizeof(stdio_devices[l]->name)); + } + ListRemoveItem(devlist,NULL,dev_index); + /* reassign Device list */ + for (i=1; i<=ListNumItems(devlist); i++) { + dev = ListGetPtrToItem (devlist, i); + for (l=0 ; l< MAX_FILES; l++) { + if(strcmp(dev->name,temp_names[l])==0) { + stdio_devices[l] = dev; + } + } + } + return 0; +} +#endif /* CFG_DEVICE_DEREGISTER */ + +int devices_init (void) +{ +#ifndef CONFIG_ARM /* already relocated for current ARM implementation */ + DECLARE_GLOBAL_DATA_PTR; + + ulong relocation_offset = gd->reloc_off; + int i; + + /* relocate device name pointers */ + for (i = 0; i < (sizeof (stdio_names) / sizeof (char *)); ++i) { + stdio_names[i] = (char *) (((ulong) stdio_names[i]) + + relocation_offset); + } +#endif + + /* Initialize the list */ + devlist = ListCreate (sizeof (device_t)); + + if (devlist == NULL) { + eputs ("Cannot initialize the list of devices!\n"); + return -1; + } +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); +#endif +#ifdef CONFIG_LCD + drv_lcd_init (); +#endif +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + drv_video_init (); +#endif +#ifdef CONFIG_KEYBOARD + drv_keyboard_init (); +#endif +#ifdef CONFIG_LOGBUFFER + drv_logbuff_init (); +#endif + drv_system_init (); +#ifdef CONFIG_SERIAL_MULTI + serial_devices_init (); +#endif +#ifdef CONFIG_USB_TTY + drv_usbtty_init (); +#endif +#ifdef CONFIG_NETCONSOLE + drv_nc_init (); +#endif + + return (0); +} + +int devices_done (void) +{ + ListDispose (devlist); + + return 0; +} diff --git a/common/dlmalloc.c b/common/dlmalloc.c new file mode 100644 index 0000000..0c04872 --- /dev/null +++ b/common/dlmalloc.c @@ -0,0 +1,3302 @@ +#if 0 /* Moved to malloc.h */ +/* ---------- To make a malloc.h, start cutting here ------------ */ + +/* + A version of malloc/free/realloc written by Doug Lea and released to the + public domain. Send questions/comments/complaints/performance data + to dl@cs.oswego.edu + +* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee) + + Note: There may be an updated version of this malloc obtainable at + ftp://g.oswego.edu/pub/misc/malloc.c + Check before installing! + +* Why use this malloc? + + This is not the fastest, most space-conserving, most portable, or + most tunable malloc ever written. However it is among the fastest + while also being among the most space-conserving, portable and tunable. + Consistent balance across these factors results in a good general-purpose + allocator. For a high-level description, see + http://g.oswego.edu/dl/html/malloc.html + +* Synopsis of public routines + + (Much fuller descriptions are contained in the program documentation below.) + + malloc(size_t n); + Return a pointer to a newly allocated chunk of at least n bytes, or null + if no space is available. + free(Void_t* p); + Release the chunk of memory pointed to by p, or no effect if p is null. + realloc(Void_t* p, size_t n); + Return a pointer to a chunk of size n that contains the same data + as does chunk p up to the minimum of (n, p's size) bytes, or null + if no space is available. The returned pointer may or may not be + the same as p. If p is null, equivalent to malloc. Unless the + #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a + size argument of zero (re)allocates a minimum-sized chunk. + memalign(size_t alignment, size_t n); + Return a pointer to a newly allocated chunk of n bytes, aligned + in accord with the alignment argument, which must be a power of + two. + valloc(size_t n); + Equivalent to memalign(pagesize, n), where pagesize is the page + size of the system (or as near to this as can be figured out from + all the includes/defines below.) + pvalloc(size_t n); + Equivalent to valloc(minimum-page-that-holds(n)), that is, + round up n to nearest pagesize. + calloc(size_t unit, size_t quantity); + Returns a pointer to quantity * unit bytes, with all locations + set to zero. + cfree(Void_t* p); + Equivalent to free(p). + malloc_trim(size_t pad); + Release all but pad bytes of freed top-most memory back + to the system. Return 1 if successful, else 0. + malloc_usable_size(Void_t* p); + Report the number usable allocated bytes associated with allocated + chunk p. This may or may not report more bytes than were requested, + due to alignment and minimum size constraints. + malloc_stats(); + Prints brief summary statistics. + mallinfo() + Returns (by copy) a struct containing various summary statistics. + mallopt(int parameter_number, int parameter_value) + Changes one of the tunable parameters described below. Returns + 1 if successful in changing the parameter, else 0. + +* Vital statistics: + + Alignment: 8-byte + 8 byte alignment is currently hardwired into the design. This + seems to suffice for all current machines and C compilers. + + Assumed pointer representation: 4 or 8 bytes + Code for 8-byte pointers is untested by me but has worked + reliably by Wolfram Gloger, who contributed most of the + changes supporting this. + + Assumed size_t representation: 4 or 8 bytes + Note that size_t is allowed to be 4 bytes even if pointers are 8. + + Minimum overhead per allocated chunk: 4 or 8 bytes + Each malloced chunk has a hidden overhead of 4 bytes holding size + and status information. + + Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead) + 8-byte ptrs: 24/32 bytes (including, 4/8 overhead) + + When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte + ptrs but 4 byte size) or 24 (for 8/8) additional bytes are + needed; 4 (8) for a trailing size field + and 8 (16) bytes for free list pointers. Thus, the minimum + allocatable size is 16/24/32 bytes. + + Even a request for zero bytes (i.e., malloc(0)) returns a + pointer to something of the minimum allocatable size. + + Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes + 8-byte size_t: 2^63 - 16 bytes + + It is assumed that (possibly signed) size_t bit values suffice to + represent chunk sizes. `Possibly signed' is due to the fact + that `size_t' may be defined on a system as either a signed or + an unsigned type. To be conservative, values that would appear + as negative numbers are avoided. + Requests for sizes with a negative sign bit when the request + size is treaded as a long will return null. + + Maximum overhead wastage per allocated chunk: normally 15 bytes + + Alignnment demands, plus the minimum allocatable size restriction + make the normal worst-case wastage 15 bytes (i.e., up to 15 + more bytes will be allocated than were requested in malloc), with + two exceptions: + 1. Because requests for zero bytes allocate non-zero space, + the worst case wastage for a request of zero bytes is 24 bytes. + 2. For requests >= mmap_threshold that are serviced via + mmap(), the worst case wastage is 8 bytes plus the remainder + from a system page (the minimal mmap unit); typically 4096 bytes. + +* Limitations + + Here are some features that are NOT currently supported + + * No user-definable hooks for callbacks and the like. + * No automated mechanism for fully checking that all accesses + to malloced memory stay within their bounds. + * No support for compaction. + +* Synopsis of compile-time options: + + People have reported using previous versions of this malloc on all + versions of Unix, sometimes by tweaking some of the defines + below. It has been tested most extensively on Solaris and + Linux. It is also reported to work on WIN32 platforms. + People have also reported adapting this malloc for use in + stand-alone embedded systems. + + The implementation is in straight, hand-tuned ANSI C. Among other + consequences, it uses a lot of macros. Because of this, to be at + all usable, this code should be compiled using an optimizing compiler + (for example gcc -O2) that can simplify expressions and control + paths. + + __STD_C (default: derived from C compiler defines) + Nonzero if using ANSI-standard C compiler, a C++ compiler, or + a C compiler sufficiently close to ANSI to get away with it. + DEBUG (default: NOT defined) + Define to enable debugging. Adds fairly extensive assertion-based + checking to help track down memory errors, but noticeably slows down + execution. + REALLOC_ZERO_BYTES_FREES (default: NOT defined) + Define this if you think that realloc(p, 0) should be equivalent + to free(p). Otherwise, since malloc returns a unique pointer for + malloc(0), so does realloc(p, 0). + HAVE_MEMCPY (default: defined) + Define if you are not otherwise using ANSI STD C, but still + have memcpy and memset in your C library and want to use them. + Otherwise, simple internal versions are supplied. + USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise) + Define as 1 if you want the C library versions of memset and + memcpy called in realloc and calloc (otherwise macro versions are used). + At least on some platforms, the simple macro versions usually + outperform libc versions. + HAVE_MMAP (default: defined as 1) + Define to non-zero to optionally make malloc() use mmap() to + allocate very large blocks. + HAVE_MREMAP (default: defined as 0 unless Linux libc set) + Define to non-zero to optionally make realloc() use mremap() to + reallocate very large blocks. + malloc_getpagesize (default: derived from system #includes) + Either a constant or routine call returning the system page size. + HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined) + Optionally define if you are on a system with a /usr/include/malloc.h + that declares struct mallinfo. It is not at all necessary to + define this even if you do, but will ensure consistency. + INTERNAL_SIZE_T (default: size_t) + Define to a 32-bit type (probably `unsigned int') if you are on a + 64-bit machine, yet do not want or need to allow malloc requests of + greater than 2^31 to be handled. This saves space, especially for + very small chunks. + INTERNAL_LINUX_C_LIB (default: NOT defined) + Defined only when compiled as part of Linux libc. + Also note that there is some odd internal name-mangling via defines + (for example, internally, `malloc' is named `mALLOc') needed + when compiling in this case. These look funny but don't otherwise + affect anything. + WIN32 (default: undefined) + Define this on MS win (95, nt) platforms to compile in sbrk emulation. + LACKS_UNISTD_H (default: undefined if not WIN32) + Define this if your system does not have a . + LACKS_SYS_PARAM_H (default: undefined if not WIN32) + Define this if your system does not have a . + MORECORE (default: sbrk) + The name of the routine to call to obtain more memory from the system. + MORECORE_FAILURE (default: -1) + The value returned upon failure of MORECORE. + MORECORE_CLEARS (default 1) + True (1) if the routine mapped to MORECORE zeroes out memory (which + holds for sbrk). + DEFAULT_TRIM_THRESHOLD + DEFAULT_TOP_PAD + DEFAULT_MMAP_THRESHOLD + DEFAULT_MMAP_MAX + Default values of tunable parameters (described in detail below) + controlling interaction with host system routines (sbrk, mmap, etc). + These values may also be changed dynamically via mallopt(). The + preset defaults are those that give best performance for typical + programs/systems. + USE_DL_PREFIX (default: undefined) + Prefix all public routines with the string 'dl'. Useful to + quickly avoid procedure declaration conflicts and linker symbol + conflicts with existing memory allocation routines. + + +*/ + + + + +/* Preliminaries */ + +#ifndef __STD_C +#ifdef __STDC__ +#define __STD_C 1 +#else +#if __cplusplus +#define __STD_C 1 +#else +#define __STD_C 0 +#endif /*__cplusplus*/ +#endif /*__STDC__*/ +#endif /*__STD_C*/ + +#ifndef Void_t +#if (__STD_C || defined(WIN32)) +#define Void_t void +#else +#define Void_t char +#endif +#endif /*Void_t*/ + +#if __STD_C +#include /* for size_t */ +#else +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include /* needed for malloc_stats */ + + +/* + Compile-time options +*/ + + +/* + Debugging: + + Because freed chunks may be overwritten with link fields, this + malloc will often die when freed memory is overwritten by user + programs. This can be very effective (albeit in an annoying way) + in helping track down dangling pointers. + + If you compile with -DDEBUG, a number of assertion checks are + enabled that will catch more memory errors. You probably won't be + able to make much sense of the actual assertion errors, but they + should help you locate incorrectly overwritten memory. The + checking is fairly extensive, and will slow down execution + noticeably. Calling malloc_stats or mallinfo with DEBUG set will + attempt to check every non-mmapped allocated and free chunk in the + course of computing the summmaries. (By nature, mmapped regions + cannot be checked very much automatically.) + + Setting DEBUG may also be helpful if you are trying to modify + this code. The assertions in the check routines spell out in more + detail the assumptions and invariants underlying the algorithms. + +*/ + +#ifdef DEBUG +#include +#else +#define assert(x) ((void)0) +#endif + + +/* + INTERNAL_SIZE_T is the word-size used for internal bookkeeping + of chunk sizes. On a 64-bit machine, you can reduce malloc + overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' + at the expense of not being able to handle requests greater than + 2^31. This limitation is hardly ever a concern; you are encouraged + to set this. However, the default version is the same as size_t. +*/ + +#ifndef INTERNAL_SIZE_T +#define INTERNAL_SIZE_T size_t +#endif + +/* + REALLOC_ZERO_BYTES_FREES should be set if a call to + realloc with zero bytes should be the same as a call to free. + Some people think it should. Otherwise, since this malloc + returns a unique pointer for malloc(0), so does realloc(p, 0). +*/ + + +/* #define REALLOC_ZERO_BYTES_FREES */ + + +/* + WIN32 causes an emulation of sbrk to be compiled in + mmap-based options are not currently supported in WIN32. +*/ + +/* #define WIN32 */ +#ifdef WIN32 +#define MORECORE wsbrk +#define HAVE_MMAP 0 + +#define LACKS_UNISTD_H +#define LACKS_SYS_PARAM_H + +/* + Include 'windows.h' to get the necessary declarations for the + Microsoft Visual C++ data structures and routines used in the 'sbrk' + emulation. + + Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft + Visual C++ header files are included. +*/ +#define WIN32_LEAN_AND_MEAN +#include +#endif + + +/* + HAVE_MEMCPY should be defined if you are not otherwise using + ANSI STD C, but still have memcpy and memset in your C library + and want to use them in calloc and realloc. Otherwise simple + macro versions are defined here. + + USE_MEMCPY should be defined as 1 if you actually want to + have memset and memcpy called. People report that the macro + versions are often enough faster than libc versions on many + systems that it is better to use them. + +*/ + +#define HAVE_MEMCPY + +#ifndef USE_MEMCPY +#ifdef HAVE_MEMCPY +#define USE_MEMCPY 1 +#else +#define USE_MEMCPY 0 +#endif +#endif + +#if (__STD_C || defined(HAVE_MEMCPY)) + +#if __STD_C +void* memset(void*, int, size_t); +void* memcpy(void*, const void*, size_t); +#else +#ifdef WIN32 +/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */ +/* 'windows.h' */ +#else +Void_t* memset(); +Void_t* memcpy(); +#endif +#endif +#endif + +#if USE_MEMCPY + +/* The following macros are only invoked with (2n+1)-multiples of + INTERNAL_SIZE_T units, with a positive integer n. This is exploited + for fast inline execution when n is small. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T mzsz = (nbytes); \ + if(mzsz <= 9*sizeof(mzsz)) { \ + INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \ + if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; }}} \ + *mz++ = 0; \ + *mz++ = 0; \ + *mz = 0; \ + } else memset((charp), 0, mzsz); \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T mcsz = (nbytes); \ + if(mcsz <= 9*sizeof(mcsz)) { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \ + if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; }}} \ + *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + *mcdst = *mcsrc ; \ + } else memcpy(dest, src, mcsz); \ +} while(0) + +#else /* !USE_MEMCPY */ + +/* Use Duff's device for good zeroing/copying performance. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mzp++ = 0; \ + case 7: *mzp++ = 0; \ + case 6: *mzp++ = 0; \ + case 5: *mzp++ = 0; \ + case 4: *mzp++ = 0; \ + case 3: *mzp++ = 0; \ + case 2: *mzp++ = 0; \ + case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mcdst++ = *mcsrc++; \ + case 7: *mcdst++ = *mcsrc++; \ + case 6: *mcdst++ = *mcsrc++; \ + case 5: *mcdst++ = *mcsrc++; \ + case 4: *mcdst++ = *mcsrc++; \ + case 3: *mcdst++ = *mcsrc++; \ + case 2: *mcdst++ = *mcsrc++; \ + case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#endif + + +/* + Define HAVE_MMAP to optionally make malloc() use mmap() to + allocate very large blocks. These will be returned to the + operating system immediately after a free(). +*/ + +#ifndef HAVE_MMAP +#define HAVE_MMAP 1 +#endif + +/* + Define HAVE_MREMAP to make realloc() use mremap() to re-allocate + large blocks. This is currently only possible on Linux with + kernel versions newer than 1.3.77. +*/ + +#ifndef HAVE_MREMAP +#ifdef INTERNAL_LINUX_C_LIB +#define HAVE_MREMAP 1 +#else +#define HAVE_MREMAP 0 +#endif +#endif + +#if HAVE_MMAP + +#include +#include +#include + +#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON) +#define MAP_ANONYMOUS MAP_ANON +#endif + +#endif /* HAVE_MMAP */ + +/* + Access to system page size. To the extent possible, this malloc + manages memory from the system in page-size units. + + The following mechanics for getpagesize were adapted from + bsd/gnu getpagesize.h +*/ + +#ifndef LACKS_UNISTD_H +# include +#endif + +#ifndef malloc_getpagesize +# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */ +# ifndef _SC_PAGE_SIZE +# define _SC_PAGE_SIZE _SC_PAGESIZE +# endif +# endif +# ifdef _SC_PAGE_SIZE +# define malloc_getpagesize sysconf(_SC_PAGE_SIZE) +# else +# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE) + extern size_t getpagesize(); +# define malloc_getpagesize getpagesize() +# else +# ifdef WIN32 +# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */ +# else +# ifndef LACKS_SYS_PARAM_H +# include +# endif +# ifdef EXEC_PAGESIZE +# define malloc_getpagesize EXEC_PAGESIZE +# else +# ifdef NBPG +# ifndef CLSIZE +# define malloc_getpagesize NBPG +# else +# define malloc_getpagesize (NBPG * CLSIZE) +# endif +# else +# ifdef NBPC +# define malloc_getpagesize NBPC +# else +# ifdef PAGESIZE +# define malloc_getpagesize PAGESIZE +# else +# define malloc_getpagesize (4096) /* just guess */ +# endif +# endif +# endif +# endif +# endif +# endif +# endif +#endif + + +/* + + This version of malloc supports the standard SVID/XPG mallinfo + routine that returns a struct containing the same kind of + information you can get from malloc_stats. It should work on + any SVID/XPG compliant system that has a /usr/include/malloc.h + defining struct mallinfo. (If you'd like to install such a thing + yourself, cut out the preliminary declarations as described above + and below and save them in a malloc.h file. But there's no + compelling reason to bother to do this.) + + The main declaration needed is the mallinfo struct that is returned + (by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a + bunch of fields, most of which are not even meaningful in this + version of malloc. Some of these fields are are instead filled by + mallinfo() with other numbers that might possibly be of interest. + + HAVE_USR_INCLUDE_MALLOC_H should be set if you have a + /usr/include/malloc.h file that includes a declaration of struct + mallinfo. If so, it is included; else an SVID2/XPG2 compliant + version is declared below. These must be precisely the same for + mallinfo() to work. + +*/ + +/* #define HAVE_USR_INCLUDE_MALLOC_H */ + +#if HAVE_USR_INCLUDE_MALLOC_H +#include "/usr/include/malloc.h" +#else + +/* SVID2/XPG mallinfo structure */ + +struct mallinfo { + int arena; /* total space allocated from system */ + int ordblks; /* number of non-inuse chunks */ + int smblks; /* unused -- always zero */ + int hblks; /* number of mmapped regions */ + int hblkhd; /* total space in mmapped regions */ + int usmblks; /* unused -- always zero */ + int fsmblks; /* unused -- always zero */ + int uordblks; /* total allocated space */ + int fordblks; /* total non-inuse space */ + int keepcost; /* top-most, releasable (via malloc_trim) space */ +}; + +/* SVID2/XPG mallopt options */ + +#define M_MXFAST 1 /* UNUSED in this malloc */ +#define M_NLBLKS 2 /* UNUSED in this malloc */ +#define M_GRAIN 3 /* UNUSED in this malloc */ +#define M_KEEP 4 /* UNUSED in this malloc */ + +#endif + +/* mallopt options that actually do something */ + +#define M_TRIM_THRESHOLD -1 +#define M_TOP_PAD -2 +#define M_MMAP_THRESHOLD -3 +#define M_MMAP_MAX -4 + + +#ifndef DEFAULT_TRIM_THRESHOLD +#define DEFAULT_TRIM_THRESHOLD (128 * 1024) +#endif + +/* + M_TRIM_THRESHOLD is the maximum amount of unused top-most memory + to keep before releasing via malloc_trim in free(). + + Automatic trimming is mainly useful in long-lived programs. + Because trimming via sbrk can be slow on some systems, and can + sometimes be wasteful (in cases where programs immediately + afterward allocate more large chunks) the value should be high + enough so that your overall system performance would improve by + releasing. + + The trim threshold and the mmap control parameters (see below) + can be traded off with one another. Trimming and mmapping are + two different ways of releasing unused memory back to the + system. Between these two, it is often possible to keep + system-level demands of a long-lived program down to a bare + minimum. For example, in one test suite of sessions measuring + the XF86 X server on Linux, using a trim threshold of 128K and a + mmap threshold of 192K led to near-minimal long term resource + consumption. + + If you are using this malloc in a long-lived program, it should + pay to experiment with these values. As a rough guide, you + might set to a value close to the average size of a process + (program) running on your system. Releasing this much memory + would allow such a process to run in memory. Generally, it's + worth it to tune for trimming rather tham memory mapping when a + program undergoes phases where several large chunks are + allocated and released in ways that can reuse each other's + storage, perhaps mixed with phases where there are no such + chunks at all. And in well-behaved long-lived programs, + controlling release of large blocks via trimming versus mapping + is usually faster. + + However, in most programs, these parameters serve mainly as + protection against the system-level effects of carrying around + massive amounts of unneeded memory. Since frequent calls to + sbrk, mmap, and munmap otherwise degrade performance, the default + parameters are set to relatively high values that serve only as + safeguards. + + The default trim value is high enough to cause trimming only in + fairly extreme (by current memory consumption standards) cases. + It must be greater than page size to have any useful effect. To + disable trimming completely, you can set to (unsigned long)(-1); + + +*/ + + +#ifndef DEFAULT_TOP_PAD +#define DEFAULT_TOP_PAD (0) +#endif + +/* + M_TOP_PAD is the amount of extra `padding' space to allocate or + retain whenever sbrk is called. It is used in two ways internally: + + * When sbrk is called to extend the top of the arena to satisfy + a new malloc request, this much padding is added to the sbrk + request. + + * When malloc_trim is called automatically from free(), + it is used as the `pad' argument. + + In both cases, the actual amount of padding is rounded + so that the end of the arena is always a system page boundary. + + The main reason for using padding is to avoid calling sbrk so + often. Having even a small pad greatly reduces the likelihood + that nearly every malloc request during program start-up (or + after trimming) will invoke sbrk, which needlessly wastes + time. + + Automatic rounding-up to page-size units is normally sufficient + to avoid measurable overhead, so the default is 0. However, in + systems where sbrk is relatively slow, it can pay to increase + this value, at the expense of carrying around more memory than + the program needs. + +*/ + + +#ifndef DEFAULT_MMAP_THRESHOLD +#define DEFAULT_MMAP_THRESHOLD (128 * 1024) +#endif + +/* + + M_MMAP_THRESHOLD is the request size threshold for using mmap() + to service a request. Requests of at least this size that cannot + be allocated using already-existing space will be serviced via mmap. + (If enough normal freed space already exists it is used instead.) + + Using mmap segregates relatively large chunks of memory so that + they can be individually obtained and released from the host + system. A request serviced through mmap is never reused by any + other request (at least not directly; the system may just so + happen to remap successive requests to the same locations). + + Segregating space in this way has the benefit that mmapped space + can ALWAYS be individually released back to the system, which + helps keep the system level memory demands of a long-lived + program low. Mapped memory can never become `locked' between + other chunks, as can happen with normally allocated chunks, which + menas that even trimming via malloc_trim would not release them. + + However, it has the disadvantages that: + + 1. The space cannot be reclaimed, consolidated, and then + used to service later requests, as happens with normal chunks. + 2. It can lead to more wastage because of mmap page alignment + requirements + 3. It causes malloc performance to be more dependent on host + system memory management support routines which may vary in + implementation quality and may impose arbitrary + limitations. Generally, servicing a request via normal + malloc steps is faster than going through a system's mmap. + + All together, these considerations should lead you to use mmap + only for relatively large requests. + + +*/ + + +#ifndef DEFAULT_MMAP_MAX +#if HAVE_MMAP +#define DEFAULT_MMAP_MAX (64) +#else +#define DEFAULT_MMAP_MAX (0) +#endif +#endif + +/* + M_MMAP_MAX is the maximum number of requests to simultaneously + service using mmap. This parameter exists because: + + 1. Some systems have a limited number of internal tables for + use by mmap. + 2. In most systems, overreliance on mmap can degrade overall + performance. + 3. If a program allocates many large regions, it is probably + better off using normal sbrk-based allocation routines that + can reclaim and reallocate normal heap memory. Using a + small value allows transition into this mode after the + first few allocations. + + Setting to 0 disables all use of mmap. If HAVE_MMAP is not set, + the default value is 0, and attempts to set it to non-zero values + in mallopt will fail. +*/ + + +/* + USE_DL_PREFIX will prefix all public routines with the string 'dl'. + Useful to quickly avoid procedure declaration conflicts and linker + symbol conflicts with existing memory allocation routines. + +*/ + +/* #define USE_DL_PREFIX */ + + +/* + + Special defines for linux libc + + Except when compiled using these special defines for Linux libc + using weak aliases, this malloc is NOT designed to work in + multithreaded applications. No semaphores or other concurrency + control are provided to ensure that multiple malloc or free calls + don't run at the same time, which could be disasterous. A single + semaphore could be used across malloc, realloc, and free (which is + essentially the effect of the linux weak alias approach). It would + be hard to obtain finer granularity. + +*/ + + +#ifdef INTERNAL_LINUX_C_LIB + +#if __STD_C + +Void_t * __default_morecore_init (ptrdiff_t); +Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init; + +#else + +Void_t * __default_morecore_init (); +Void_t *(*__morecore)() = __default_morecore_init; + +#endif + +#define MORECORE (*__morecore) +#define MORECORE_FAILURE 0 +#define MORECORE_CLEARS 1 + +#else /* INTERNAL_LINUX_C_LIB */ + +#if __STD_C +extern Void_t* sbrk(ptrdiff_t); +#else +extern Void_t* sbrk(); +#endif + +#ifndef MORECORE +#define MORECORE sbrk +#endif + +#ifndef MORECORE_FAILURE +#define MORECORE_FAILURE -1 +#endif + +#ifndef MORECORE_CLEARS +#define MORECORE_CLEARS 1 +#endif + +#endif /* INTERNAL_LINUX_C_LIB */ + +#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__) + +#define cALLOc __libc_calloc +#define fREe __libc_free +#define mALLOc __libc_malloc +#define mEMALIGn __libc_memalign +#define rEALLOc __libc_realloc +#define vALLOc __libc_valloc +#define pvALLOc __libc_pvalloc +#define mALLINFo __libc_mallinfo +#define mALLOPt __libc_mallopt + +#pragma weak calloc = __libc_calloc +#pragma weak free = __libc_free +#pragma weak cfree = __libc_free +#pragma weak malloc = __libc_malloc +#pragma weak memalign = __libc_memalign +#pragma weak realloc = __libc_realloc +#pragma weak valloc = __libc_valloc +#pragma weak pvalloc = __libc_pvalloc +#pragma weak mallinfo = __libc_mallinfo +#pragma weak mallopt = __libc_mallopt + +#else + +#ifdef USE_DL_PREFIX +#define cALLOc dlcalloc +#define fREe dlfree +#define mALLOc dlmalloc +#define mEMALIGn dlmemalign +#define rEALLOc dlrealloc +#define vALLOc dlvalloc +#define pvALLOc dlpvalloc +#define mALLINFo dlmallinfo +#define mALLOPt dlmallopt +#else /* USE_DL_PREFIX */ +#define cALLOc calloc +#define fREe free +#define mALLOc malloc +#define mEMALIGn memalign +#define rEALLOc realloc +#define vALLOc valloc +#define pvALLOc pvalloc +#define mALLINFo mallinfo +#define mALLOPt mallopt +#endif /* USE_DL_PREFIX */ + +#endif + +/* Public routines */ + +#if __STD_C + +Void_t* mALLOc(size_t); +void fREe(Void_t*); +Void_t* rEALLOc(Void_t*, size_t); +Void_t* mEMALIGn(size_t, size_t); +Void_t* vALLOc(size_t); +Void_t* pvALLOc(size_t); +Void_t* cALLOc(size_t, size_t); +void cfree(Void_t*); +int malloc_trim(size_t); +size_t malloc_usable_size(Void_t*); +void malloc_stats(); +int mALLOPt(int, int); +struct mallinfo mALLINFo(void); +#else +Void_t* mALLOc(); +void fREe(); +Void_t* rEALLOc(); +Void_t* mEMALIGn(); +Void_t* vALLOc(); +Void_t* pvALLOc(); +Void_t* cALLOc(); +void cfree(); +int malloc_trim(); +size_t malloc_usable_size(); +void malloc_stats(); +int mALLOPt(); +struct mallinfo mALLINFo(); +#endif + + +#ifdef __cplusplus +}; /* end of extern "C" */ +#endif + +/* ---------- To make a malloc.h, end cutting here ------------ */ +#else /* Moved to malloc.h */ + +#include +#if 0 +#if __STD_C +static void malloc_update_mallinfo (void); +void malloc_stats (void); +#else +static void malloc_update_mallinfo (); +void malloc_stats(); +#endif +#endif /* 0 */ + +#endif /* 0 */ /* Moved to malloc.h */ +#include + +/* + Emulation of sbrk for WIN32 + All code within the ifdef WIN32 is untested by me. + + Thanks to Martin Fong and others for supplying this. +*/ + + +#ifdef WIN32 + +#define AlignPage(add) (((add) + (malloc_getpagesize-1)) & \ +~(malloc_getpagesize-1)) +#define AlignPage64K(add) (((add) + (0x10000 - 1)) & ~(0x10000 - 1)) + +/* resrve 64MB to insure large contiguous space */ +#define RESERVED_SIZE (1024*1024*64) +#define NEXT_SIZE (2048*1024) +#define TOP_MEMORY ((unsigned long)2*1024*1024*1024) + +struct GmListElement; +typedef struct GmListElement GmListElement; + +struct GmListElement +{ + GmListElement* next; + void* base; +}; + +static GmListElement* head = 0; +static unsigned int gNextAddress = 0; +static unsigned int gAddressBase = 0; +static unsigned int gAllocatedSize = 0; + +static +GmListElement* makeGmListElement (void* bas) +{ + GmListElement* this; + this = (GmListElement*)(void*)LocalAlloc (0, sizeof (GmListElement)); + assert (this); + if (this) + { + this->base = bas; + this->next = head; + head = this; + } + return this; +} + +void gcleanup () +{ + BOOL rval; + assert ( (head == NULL) || (head->base == (void*)gAddressBase)); + if (gAddressBase && (gNextAddress - gAddressBase)) + { + rval = VirtualFree ((void*)gAddressBase, + gNextAddress - gAddressBase, + MEM_DECOMMIT); + assert (rval); + } + while (head) + { + GmListElement* next = head->next; + rval = VirtualFree (head->base, 0, MEM_RELEASE); + assert (rval); + LocalFree (head); + head = next; + } +} + +static +void* findRegion (void* start_address, unsigned long size) +{ + MEMORY_BASIC_INFORMATION info; + if (size >= TOP_MEMORY) return NULL; + + while ((unsigned long)start_address + size < TOP_MEMORY) + { + VirtualQuery (start_address, &info, sizeof (info)); + if ((info.State == MEM_FREE) && (info.RegionSize >= size)) + return start_address; + else + { + /* Requested region is not available so see if the */ + /* next region is available. Set 'start_address' */ + /* to the next region and call 'VirtualQuery()' */ + /* again. */ + + start_address = (char*)info.BaseAddress + info.RegionSize; + + /* Make sure we start looking for the next region */ + /* on the *next* 64K boundary. Otherwise, even if */ + /* the new region is free according to */ + /* 'VirtualQuery()', the subsequent call to */ + /* 'VirtualAlloc()' (which follows the call to */ + /* this routine in 'wsbrk()') will round *down* */ + /* the requested address to a 64K boundary which */ + /* we already know is an address in the */ + /* unavailable region. Thus, the subsequent call */ + /* to 'VirtualAlloc()' will fail and bring us back */ + /* here, causing us to go into an infinite loop. */ + + start_address = + (void *) AlignPage64K((unsigned long) start_address); + } + } + return NULL; + +} + + +void* wsbrk (long size) +{ + void* tmp; + if (size > 0) + { + if (gAddressBase == 0) + { + gAllocatedSize = max (RESERVED_SIZE, AlignPage (size)); + gNextAddress = gAddressBase = + (unsigned int)VirtualAlloc (NULL, gAllocatedSize, + MEM_RESERVE, PAGE_NOACCESS); + } else if (AlignPage (gNextAddress + size) > (gAddressBase + +gAllocatedSize)) + { + long new_size = max (NEXT_SIZE, AlignPage (size)); + void* new_address = (void*)(gAddressBase+gAllocatedSize); + do + { + new_address = findRegion (new_address, new_size); + + if (new_address == 0) + return (void*)-1; + + gAddressBase = gNextAddress = + (unsigned int)VirtualAlloc (new_address, new_size, + MEM_RESERVE, PAGE_NOACCESS); + /* repeat in case of race condition */ + /* The region that we found has been snagged */ + /* by another thread */ + } + while (gAddressBase == 0); + + assert (new_address == (void*)gAddressBase); + + gAllocatedSize = new_size; + + if (!makeGmListElement ((void*)gAddressBase)) + return (void*)-1; + } + if ((size + gNextAddress) > AlignPage (gNextAddress)) + { + void* res; + res = VirtualAlloc ((void*)AlignPage (gNextAddress), + (size + gNextAddress - + AlignPage (gNextAddress)), + MEM_COMMIT, PAGE_READWRITE); + if (res == 0) + return (void*)-1; + } + tmp = (void*)gNextAddress; + gNextAddress = (unsigned int)tmp + size; + return tmp; + } + else if (size < 0) + { + unsigned int alignedGoal = AlignPage (gNextAddress + size); + /* Trim by releasing the virtual memory */ + if (alignedGoal >= gAddressBase) + { + VirtualFree ((void*)alignedGoal, gNextAddress - alignedGoal, + MEM_DECOMMIT); + gNextAddress = gNextAddress + size; + return (void*)gNextAddress; + } + else + { + VirtualFree ((void*)gAddressBase, gNextAddress - gAddressBase, + MEM_DECOMMIT); + gNextAddress = gAddressBase; + return (void*)-1; + } + } + else + { + return (void*)gNextAddress; + } +} + +#endif + + + +/* + Type declarations +*/ + + +struct malloc_chunk +{ + INTERNAL_SIZE_T prev_size; /* Size of previous chunk (if free). */ + INTERNAL_SIZE_T size; /* Size in bytes, including overhead. */ + struct malloc_chunk* fd; /* double links -- used only if free. */ + struct malloc_chunk* bk; +}; + +typedef struct malloc_chunk* mchunkptr; + +/* + + malloc_chunk details: + + (The following includes lightly edited explanations by Colin Plumb.) + + Chunks of memory are maintained using a `boundary tag' method as + described in e.g., Knuth or Standish. (See the paper by Paul + Wilson ftp://ftp.cs.utexas.edu/pub/garbage/allocsrv.ps for a + survey of such techniques.) Sizes of free chunks are stored both + in the front of each chunk and at the end. This makes + consolidating fragmented chunks into bigger chunks very fast. The + size fields also hold bits representing whether chunks are free or + in use. + + An allocated chunk looks like this: + + + chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of previous chunk, if allocated | | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of chunk, in bytes |P| + mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | User data starts here... . + . . + . (malloc_usable_space() bytes) . + . | +nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of chunk | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + + Where "chunk" is the front of the chunk for the purpose of most of + the malloc code, but "mem" is the pointer that is returned to the + user. "Nextchunk" is the beginning of the next contiguous chunk. + + Chunks always begin on even word boundries, so the mem portion + (which is returned to the user) is also on an even word boundary, and + thus double-word aligned. + + Free chunks are stored in circular doubly-linked lists, and look like this: + + chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of previous chunk | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + `head:' | Size of chunk, in bytes |P| + mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Forward pointer to next chunk in list | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Back pointer to previous chunk in list | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Unused space (may be 0 bytes long) . + . . + . | +nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + `foot:' | Size of chunk, in bytes | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + The P (PREV_INUSE) bit, stored in the unused low-order bit of the + chunk size (which is always a multiple of two words), is an in-use + bit for the *previous* chunk. If that bit is *clear*, then the + word before the current chunk size contains the previous chunk + size, and can be used to find the front of the previous chunk. + (The very first chunk allocated always has this bit set, + preventing access to non-existent (or non-owned) memory.) + + Note that the `foot' of the current chunk is actually represented + as the prev_size of the NEXT chunk. (This makes it easier to + deal with alignments etc). + + The two exceptions to all this are + + 1. The special chunk `top', which doesn't bother using the + trailing size field since there is no + next contiguous chunk that would have to index off it. (After + initialization, `top' is forced to always exist. If it would + become less than MINSIZE bytes long, it is replenished via + malloc_extend_top.) + + 2. Chunks allocated via mmap, which have the second-lowest-order + bit (IS_MMAPPED) set in their size fields. Because they are + never merged or traversed from any other chunk, they have no + foot size or inuse information. + + Available chunks are kept in any of several places (all declared below): + + * `av': An array of chunks serving as bin headers for consolidated + chunks. Each bin is doubly linked. The bins are approximately + proportionally (log) spaced. There are a lot of these bins + (128). This may look excessive, but works very well in + practice. All procedures maintain the invariant that no + consolidated chunk physically borders another one. Chunks in + bins are kept in size order, with ties going to the + approximately least recently used chunk. + + The chunks in each bin are maintained in decreasing sorted order by + size. This is irrelevant for the small bins, which all contain + the same-sized chunks, but facilitates best-fit allocation for + larger chunks. (These lists are just sequential. Keeping them in + order almost never requires enough traversal to warrant using + fancier ordered data structures.) Chunks of the same size are + linked with the most recently freed at the front, and allocations + are taken from the back. This results in LRU or FIFO allocation + order, which tends to give each chunk an equal opportunity to be + consolidated with adjacent freed chunks, resulting in larger free + chunks and less fragmentation. + + * `top': The top-most available chunk (i.e., the one bordering the + end of available memory) is treated specially. It is never + included in any bin, is used only if no other chunk is + available, and is released back to the system if it is very + large (see M_TRIM_THRESHOLD). + + * `last_remainder': A bin holding only the remainder of the + most recently split (non-top) chunk. This bin is checked + before other non-fitting chunks, so as to provide better + locality for runs of sequentially allocated chunks. + + * Implicitly, through the host system's memory mapping tables. + If supported, requests greater than a threshold are usually + serviced via calls to mmap, and then later released via munmap. + +*/ + +/* sizes, alignments */ + +#define SIZE_SZ (sizeof(INTERNAL_SIZE_T)) +#define MALLOC_ALIGNMENT (SIZE_SZ + SIZE_SZ) +#define MALLOC_ALIGN_MASK (MALLOC_ALIGNMENT - 1) +#define MINSIZE (sizeof(struct malloc_chunk)) + +/* conversion from malloc headers to user pointers, and back */ + +#define chunk2mem(p) ((Void_t*)((char*)(p) + 2*SIZE_SZ)) +#define mem2chunk(mem) ((mchunkptr)((char*)(mem) - 2*SIZE_SZ)) + +/* pad request bytes into a usable size */ + +#define request2size(req) \ + (((long)((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) < \ + (long)(MINSIZE + MALLOC_ALIGN_MASK)) ? MINSIZE : \ + (((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) & ~(MALLOC_ALIGN_MASK))) + +/* Check if m has acceptable alignment */ + +#define aligned_OK(m) (((unsigned long)((m)) & (MALLOC_ALIGN_MASK)) == 0) + + + + +/* + Physical chunk operations +*/ + + +/* size field is or'ed with PREV_INUSE when previous adjacent chunk in use */ + +#define PREV_INUSE 0x1 + +/* size field is or'ed with IS_MMAPPED if the chunk was obtained with mmap() */ + +#define IS_MMAPPED 0x2 + +/* Bits to mask off when extracting size */ + +#define SIZE_BITS (PREV_INUSE|IS_MMAPPED) + + +/* Ptr to next physical malloc_chunk. */ + +#define next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~PREV_INUSE) )) + +/* Ptr to previous physical malloc_chunk */ + +#define prev_chunk(p)\ + ((mchunkptr)( ((char*)(p)) - ((p)->prev_size) )) + + +/* Treat space at ptr + offset as a chunk */ + +#define chunk_at_offset(p, s) ((mchunkptr)(((char*)(p)) + (s))) + + + + +/* + Dealing with use bits +*/ + +/* extract p's inuse bit */ + +#define inuse(p)\ +((((mchunkptr)(((char*)(p))+((p)->size & ~PREV_INUSE)))->size) & PREV_INUSE) + +/* extract inuse bit of previous chunk */ + +#define prev_inuse(p) ((p)->size & PREV_INUSE) + +/* check for mmap()'ed chunk */ + +#define chunk_is_mmapped(p) ((p)->size & IS_MMAPPED) + +/* set/clear chunk as in use without otherwise disturbing */ + +#define set_inuse(p)\ +((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size |= PREV_INUSE + +#define clear_inuse(p)\ +((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size &= ~(PREV_INUSE) + +/* check/set/clear inuse bits in known places */ + +#define inuse_bit_at_offset(p, s)\ + (((mchunkptr)(((char*)(p)) + (s)))->size & PREV_INUSE) + +#define set_inuse_bit_at_offset(p, s)\ + (((mchunkptr)(((char*)(p)) + (s)))->size |= PREV_INUSE) + +#define clear_inuse_bit_at_offset(p, s)\ + (((mchunkptr)(((char*)(p)) + (s)))->size &= ~(PREV_INUSE)) + + + + +/* + Dealing with size fields +*/ + +/* Get size, ignoring use bits */ + +#define chunksize(p) ((p)->size & ~(SIZE_BITS)) + +/* Set size at head, without disturbing its use bit */ + +#define set_head_size(p, s) ((p)->size = (((p)->size & PREV_INUSE) | (s))) + +/* Set size/use ignoring previous bits in header */ + +#define set_head(p, s) ((p)->size = (s)) + +/* Set size at footer (only when chunk is not in use) */ + +#define set_foot(p, s) (((mchunkptr)((char*)(p) + (s)))->prev_size = (s)) + + + + + +/* + Bins + + The bins, `av_' are an array of pairs of pointers serving as the + heads of (initially empty) doubly-linked lists of chunks, laid out + in a way so that each pair can be treated as if it were in a + malloc_chunk. (This way, the fd/bk offsets for linking bin heads + and chunks are the same). + + Bins for sizes < 512 bytes contain chunks of all the same size, spaced + 8 bytes apart. Larger bins are approximately logarithmically + spaced. (See the table below.) The `av_' array is never mentioned + directly in the code, but instead via bin access macros. + + Bin layout: + + 64 bins of size 8 + 32 bins of size 64 + 16 bins of size 512 + 8 bins of size 4096 + 4 bins of size 32768 + 2 bins of size 262144 + 1 bin of size what's left + + There is actually a little bit of slop in the numbers in bin_index + for the sake of speed. This makes no difference elsewhere. + + The special chunks `top' and `last_remainder' get their own bins, + (this is implemented via yet more trickery with the av_ array), + although `top' is never properly linked to its bin since it is + always handled specially. + +*/ + +#define NAV 128 /* number of bins */ + +typedef struct malloc_chunk* mbinptr; + +/* access macros */ + +#define bin_at(i) ((mbinptr)((char*)&(av_[2*(i) + 2]) - 2*SIZE_SZ)) +#define next_bin(b) ((mbinptr)((char*)(b) + 2 * sizeof(mbinptr))) +#define prev_bin(b) ((mbinptr)((char*)(b) - 2 * sizeof(mbinptr))) + +/* + The first 2 bins are never indexed. The corresponding av_ cells are instead + used for bookkeeping. This is not to save space, but to simplify + indexing, maintain locality, and avoid some initialization tests. +*/ + +#define top (bin_at(0)->fd) /* The topmost chunk */ +#define last_remainder (bin_at(1)) /* remainder from last split */ + + +/* + Because top initially points to its own bin with initial + zero size, thus forcing extension on the first malloc request, + we avoid having any special code in malloc to check whether + it even exists yet. But we still need to in malloc_extend_top. +*/ + +#define initial_top ((mchunkptr)(bin_at(0))) + +/* Helper macro to initialize bins */ + +#define IAV(i) bin_at(i), bin_at(i) + +static mbinptr av_[NAV * 2 + 2] = { + 0, 0, + IAV(0), IAV(1), IAV(2), IAV(3), IAV(4), IAV(5), IAV(6), IAV(7), + IAV(8), IAV(9), IAV(10), IAV(11), IAV(12), IAV(13), IAV(14), IAV(15), + IAV(16), IAV(17), IAV(18), IAV(19), IAV(20), IAV(21), IAV(22), IAV(23), + IAV(24), IAV(25), IAV(26), IAV(27), IAV(28), IAV(29), IAV(30), IAV(31), + IAV(32), IAV(33), IAV(34), IAV(35), IAV(36), IAV(37), IAV(38), IAV(39), + IAV(40), IAV(41), IAV(42), IAV(43), IAV(44), IAV(45), IAV(46), IAV(47), + IAV(48), IAV(49), IAV(50), IAV(51), IAV(52), IAV(53), IAV(54), IAV(55), + IAV(56), IAV(57), IAV(58), IAV(59), IAV(60), IAV(61), IAV(62), IAV(63), + IAV(64), IAV(65), IAV(66), IAV(67), IAV(68), IAV(69), IAV(70), IAV(71), + IAV(72), IAV(73), IAV(74), IAV(75), IAV(76), IAV(77), IAV(78), IAV(79), + IAV(80), IAV(81), IAV(82), IAV(83), IAV(84), IAV(85), IAV(86), IAV(87), + IAV(88), IAV(89), IAV(90), IAV(91), IAV(92), IAV(93), IAV(94), IAV(95), + IAV(96), IAV(97), IAV(98), IAV(99), IAV(100), IAV(101), IAV(102), IAV(103), + IAV(104), IAV(105), IAV(106), IAV(107), IAV(108), IAV(109), IAV(110), IAV(111), + IAV(112), IAV(113), IAV(114), IAV(115), IAV(116), IAV(117), IAV(118), IAV(119), + IAV(120), IAV(121), IAV(122), IAV(123), IAV(124), IAV(125), IAV(126), IAV(127) +}; + +void malloc_bin_reloc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long *p = (unsigned long *)(&av_[2]); + int i; + for (i=2; i<(sizeof(av_)/sizeof(mbinptr)); ++i) { + *p++ += gd->reloc_off; + } +} + + +/* field-extraction macros */ + +#define first(b) ((b)->fd) +#define last(b) ((b)->bk) + +/* + Indexing into bins +*/ + +#define bin_index(sz) \ +(((((unsigned long)(sz)) >> 9) == 0) ? (((unsigned long)(sz)) >> 3): \ + ((((unsigned long)(sz)) >> 9) <= 4) ? 56 + (((unsigned long)(sz)) >> 6): \ + ((((unsigned long)(sz)) >> 9) <= 20) ? 91 + (((unsigned long)(sz)) >> 9): \ + ((((unsigned long)(sz)) >> 9) <= 84) ? 110 + (((unsigned long)(sz)) >> 12): \ + ((((unsigned long)(sz)) >> 9) <= 340) ? 119 + (((unsigned long)(sz)) >> 15): \ + ((((unsigned long)(sz)) >> 9) <= 1364) ? 124 + (((unsigned long)(sz)) >> 18): \ + 126) +/* + bins for chunks < 512 are all spaced 8 bytes apart, and hold + identically sized chunks. This is exploited in malloc. +*/ + +#define MAX_SMALLBIN 63 +#define MAX_SMALLBIN_SIZE 512 +#define SMALLBIN_WIDTH 8 + +#define smallbin_index(sz) (((unsigned long)(sz)) >> 3) + +/* + Requests are `small' if both the corresponding and the next bin are small +*/ + +#define is_small_request(nb) (nb < MAX_SMALLBIN_SIZE - SMALLBIN_WIDTH) + + + +/* + To help compensate for the large number of bins, a one-level index + structure is used for bin-by-bin searching. `binblocks' is a + one-word bitvector recording whether groups of BINBLOCKWIDTH bins + have any (possibly) non-empty bins, so they can be skipped over + all at once during during traversals. The bits are NOT always + cleared as soon as all bins in a block are empty, but instead only + when all are noticed to be empty during traversal in malloc. +*/ + +#define BINBLOCKWIDTH 4 /* bins per block */ + +#define binblocks (bin_at(0)->size) /* bitvector of nonempty blocks */ + +/* bin<->block macros */ + +#define idx2binblock(ix) ((unsigned)1 << (ix / BINBLOCKWIDTH)) +#define mark_binblock(ii) (binblocks |= idx2binblock(ii)) +#define clear_binblock(ii) (binblocks &= ~(idx2binblock(ii))) + + + + + +/* Other static bookkeeping data */ + +/* variables holding tunable values */ + +static unsigned long trim_threshold = DEFAULT_TRIM_THRESHOLD; +static unsigned long top_pad = DEFAULT_TOP_PAD; +static unsigned int n_mmaps_max = DEFAULT_MMAP_MAX; +static unsigned long mmap_threshold = DEFAULT_MMAP_THRESHOLD; + +/* The first value returned from sbrk */ +static char* sbrk_base = (char*)(-1); + +/* The maximum memory obtained from system via sbrk */ +static unsigned long max_sbrked_mem = 0; + +/* The maximum via either sbrk or mmap */ +static unsigned long max_total_mem = 0; + +/* internal working copy of mallinfo */ +static struct mallinfo current_mallinfo = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + +/* The total memory obtained from system via sbrk */ +#define sbrked_mem (current_mallinfo.arena) + +/* Tracking mmaps */ + +#if 0 +static unsigned int n_mmaps = 0; +#endif /* 0 */ +static unsigned long mmapped_mem = 0; +#if HAVE_MMAP +static unsigned int max_n_mmaps = 0; +static unsigned long max_mmapped_mem = 0; +#endif + + + +/* + Debugging support +*/ + +#ifdef DEBUG + + +/* + These routines make a number of assertions about the states + of data structures that should be true at all times. If any + are not true, it's very likely that a user program has somehow + trashed memory. (It's also possible that there is a coding error + in malloc. In which case, please report it!) +*/ + +#if __STD_C +static void do_check_chunk(mchunkptr p) +#else +static void do_check_chunk(p) mchunkptr p; +#endif +{ +#if 0 /* causes warnings because assert() is off */ + INTERNAL_SIZE_T sz = p->size & ~PREV_INUSE; +#endif /* 0 */ + + /* No checkable chunk is mmapped */ + assert(!chunk_is_mmapped(p)); + + /* Check for legal address ... */ + assert((char*)p >= sbrk_base); + if (p != top) + assert((char*)p + sz <= (char*)top); + else + assert((char*)p + sz <= sbrk_base + sbrked_mem); + +} + + +#if __STD_C +static void do_check_free_chunk(mchunkptr p) +#else +static void do_check_free_chunk(p) mchunkptr p; +#endif +{ + INTERNAL_SIZE_T sz = p->size & ~PREV_INUSE; +#if 0 /* causes warnings because assert() is off */ + mchunkptr next = chunk_at_offset(p, sz); +#endif /* 0 */ + + do_check_chunk(p); + + /* Check whether it claims to be free ... */ + assert(!inuse(p)); + + /* Unless a special marker, must have OK fields */ + if ((long)sz >= (long)MINSIZE) + { + assert((sz & MALLOC_ALIGN_MASK) == 0); + assert(aligned_OK(chunk2mem(p))); + /* ... matching footer field */ + assert(next->prev_size == sz); + /* ... and is fully consolidated */ + assert(prev_inuse(p)); + assert (next == top || inuse(next)); + + /* ... and has minimally sane links */ + assert(p->fd->bk == p); + assert(p->bk->fd == p); + } + else /* markers are always of size SIZE_SZ */ + assert(sz == SIZE_SZ); +} + +#if __STD_C +static void do_check_inuse_chunk(mchunkptr p) +#else +static void do_check_inuse_chunk(p) mchunkptr p; +#endif +{ + mchunkptr next = next_chunk(p); + do_check_chunk(p); + + /* Check whether it claims to be in use ... */ + assert(inuse(p)); + + /* ... and is surrounded by OK chunks. + Since more things can be checked with free chunks than inuse ones, + if an inuse chunk borders them and debug is on, it's worth doing them. + */ + if (!prev_inuse(p)) + { + mchunkptr prv = prev_chunk(p); + assert(next_chunk(prv) == p); + do_check_free_chunk(prv); + } + if (next == top) + { + assert(prev_inuse(next)); + assert(chunksize(next) >= MINSIZE); + } + else if (!inuse(next)) + do_check_free_chunk(next); + +} + +#if __STD_C +static void do_check_malloced_chunk(mchunkptr p, INTERNAL_SIZE_T s) +#else +static void do_check_malloced_chunk(p, s) mchunkptr p; INTERNAL_SIZE_T s; +#endif +{ +#if 0 /* causes warnings because assert() is off */ + INTERNAL_SIZE_T sz = p->size & ~PREV_INUSE; + long room = sz - s; +#endif /* 0 */ + + do_check_inuse_chunk(p); + + /* Legal size ... */ + assert((long)sz >= (long)MINSIZE); + assert((sz & MALLOC_ALIGN_MASK) == 0); + assert(room >= 0); + assert(room < (long)MINSIZE); + + /* ... and alignment */ + assert(aligned_OK(chunk2mem(p))); + + + /* ... and was allocated at front of an available chunk */ + assert(prev_inuse(p)); + +} + + +#define check_free_chunk(P) do_check_free_chunk(P) +#define check_inuse_chunk(P) do_check_inuse_chunk(P) +#define check_chunk(P) do_check_chunk(P) +#define check_malloced_chunk(P,N) do_check_malloced_chunk(P,N) +#else +#define check_free_chunk(P) +#define check_inuse_chunk(P) +#define check_chunk(P) +#define check_malloced_chunk(P,N) +#endif + + + +/* + Macro-based internal utilities +*/ + + +/* + Linking chunks in bin lists. + Call these only with variables, not arbitrary expressions, as arguments. +*/ + +/* + Place chunk p of size s in its bin, in size order, + putting it ahead of others of same size. +*/ + + +#define frontlink(P, S, IDX, BK, FD) \ +{ \ + if (S < MAX_SMALLBIN_SIZE) \ + { \ + IDX = smallbin_index(S); \ + mark_binblock(IDX); \ + BK = bin_at(IDX); \ + FD = BK->fd; \ + P->bk = BK; \ + P->fd = FD; \ + FD->bk = BK->fd = P; \ + } \ + else \ + { \ + IDX = bin_index(S); \ + BK = bin_at(IDX); \ + FD = BK->fd; \ + if (FD == BK) mark_binblock(IDX); \ + else \ + { \ + while (FD != BK && S < chunksize(FD)) FD = FD->fd; \ + BK = FD->bk; \ + } \ + P->bk = BK; \ + P->fd = FD; \ + FD->bk = BK->fd = P; \ + } \ +} + + +/* take a chunk off a list */ + +#define unlink(P, BK, FD) \ +{ \ + BK = P->bk; \ + FD = P->fd; \ + FD->bk = BK; \ + BK->fd = FD; \ +} \ + +/* Place p as the last remainder */ + +#define link_last_remainder(P) \ +{ \ + last_remainder->fd = last_remainder->bk = P; \ + P->fd = P->bk = last_remainder; \ +} + +/* Clear the last_remainder bin */ + +#define clear_last_remainder \ + (last_remainder->fd = last_remainder->bk = last_remainder) + + + + + +/* Routines dealing with mmap(). */ + +#if HAVE_MMAP + +#if __STD_C +static mchunkptr mmap_chunk(size_t size) +#else +static mchunkptr mmap_chunk(size) size_t size; +#endif +{ + size_t page_mask = malloc_getpagesize - 1; + mchunkptr p; + +#ifndef MAP_ANONYMOUS + static int fd = -1; +#endif + + if(n_mmaps >= n_mmaps_max) return 0; /* too many regions */ + + /* For mmapped chunks, the overhead is one SIZE_SZ unit larger, because + * there is no following chunk whose prev_size field could be used. + */ + size = (size + SIZE_SZ + page_mask) & ~page_mask; + +#ifdef MAP_ANONYMOUS + p = (mchunkptr)mmap(0, size, PROT_READ|PROT_WRITE, + MAP_PRIVATE|MAP_ANONYMOUS, -1, 0); +#else /* !MAP_ANONYMOUS */ + if (fd < 0) + { + fd = open("/dev/zero", O_RDWR); + if(fd < 0) return 0; + } + p = (mchunkptr)mmap(0, size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0); +#endif + + if(p == (mchunkptr)-1) return 0; + + n_mmaps++; + if (n_mmaps > max_n_mmaps) max_n_mmaps = n_mmaps; + + /* We demand that eight bytes into a page must be 8-byte aligned. */ + assert(aligned_OK(chunk2mem(p))); + + /* The offset to the start of the mmapped region is stored + * in the prev_size field of the chunk; normally it is zero, + * but that can be changed in memalign(). + */ + p->prev_size = 0; + set_head(p, size|IS_MMAPPED); + + mmapped_mem += size; + if ((unsigned long)mmapped_mem > (unsigned long)max_mmapped_mem) + max_mmapped_mem = mmapped_mem; + if ((unsigned long)(mmapped_mem + sbrked_mem) > (unsigned long)max_total_mem) + max_total_mem = mmapped_mem + sbrked_mem; + return p; +} + +#if __STD_C +static void munmap_chunk(mchunkptr p) +#else +static void munmap_chunk(p) mchunkptr p; +#endif +{ + INTERNAL_SIZE_T size = chunksize(p); + int ret; + + assert (chunk_is_mmapped(p)); + assert(! ((char*)p >= sbrk_base && (char*)p < sbrk_base + sbrked_mem)); + assert((n_mmaps > 0)); + assert(((p->prev_size + size) & (malloc_getpagesize-1)) == 0); + + n_mmaps--; + mmapped_mem -= (size + p->prev_size); + + ret = munmap((char *)p - p->prev_size, size + p->prev_size); + + /* munmap returns non-zero on failure */ + assert(ret == 0); +} + +#if HAVE_MREMAP + +#if __STD_C +static mchunkptr mremap_chunk(mchunkptr p, size_t new_size) +#else +static mchunkptr mremap_chunk(p, new_size) mchunkptr p; size_t new_size; +#endif +{ + size_t page_mask = malloc_getpagesize - 1; + INTERNAL_SIZE_T offset = p->prev_size; + INTERNAL_SIZE_T size = chunksize(p); + char *cp; + + assert (chunk_is_mmapped(p)); + assert(! ((char*)p >= sbrk_base && (char*)p < sbrk_base + sbrked_mem)); + assert((n_mmaps > 0)); + assert(((size + offset) & (malloc_getpagesize-1)) == 0); + + /* Note the extra SIZE_SZ overhead as in mmap_chunk(). */ + new_size = (new_size + offset + SIZE_SZ + page_mask) & ~page_mask; + + cp = (char *)mremap((char *)p - offset, size + offset, new_size, 1); + + if (cp == (char *)-1) return 0; + + p = (mchunkptr)(cp + offset); + + assert(aligned_OK(chunk2mem(p))); + + assert((p->prev_size == offset)); + set_head(p, (new_size - offset)|IS_MMAPPED); + + mmapped_mem -= size + offset; + mmapped_mem += new_size; + if ((unsigned long)mmapped_mem > (unsigned long)max_mmapped_mem) + max_mmapped_mem = mmapped_mem; + if ((unsigned long)(mmapped_mem + sbrked_mem) > (unsigned long)max_total_mem) + max_total_mem = mmapped_mem + sbrked_mem; + return p; +} + +#endif /* HAVE_MREMAP */ + +#endif /* HAVE_MMAP */ + + + + +/* + Extend the top-most chunk by obtaining memory from system. + Main interface to sbrk (but see also malloc_trim). +*/ + +#if __STD_C +static void malloc_extend_top(INTERNAL_SIZE_T nb) +#else +static void malloc_extend_top(nb) INTERNAL_SIZE_T nb; +#endif +{ + char* brk; /* return value from sbrk */ + INTERNAL_SIZE_T front_misalign; /* unusable bytes at front of sbrked space */ + INTERNAL_SIZE_T correction; /* bytes for 2nd sbrk call */ + char* new_brk; /* return of 2nd sbrk call */ + INTERNAL_SIZE_T top_size; /* new size of top chunk */ + + mchunkptr old_top = top; /* Record state of old top */ + INTERNAL_SIZE_T old_top_size = chunksize(old_top); + char* old_end = (char*)(chunk_at_offset(old_top, old_top_size)); + + /* Pad request with top_pad plus minimal overhead */ + + INTERNAL_SIZE_T sbrk_size = nb + top_pad + MINSIZE; + unsigned long pagesz = malloc_getpagesize; + + /* If not the first time through, round to preserve page boundary */ + /* Otherwise, we need to correct to a page size below anyway. */ + /* (We also correct below if an intervening foreign sbrk call.) */ + + if (sbrk_base != (char*)(-1)) + sbrk_size = (sbrk_size + (pagesz - 1)) & ~(pagesz - 1); + + brk = (char*)(MORECORE (sbrk_size)); + + /* Fail if sbrk failed or if a foreign sbrk call killed our space */ + if (brk == (char*)(MORECORE_FAILURE) || + (brk < old_end && old_top != initial_top)) + return; + + sbrked_mem += sbrk_size; + + if (brk == old_end) /* can just add bytes to current top */ + { + top_size = sbrk_size + old_top_size; + set_head(top, top_size | PREV_INUSE); + } + else + { + if (sbrk_base == (char*)(-1)) /* First time through. Record base */ + sbrk_base = brk; + else /* Someone else called sbrk(). Count those bytes as sbrked_mem. */ + sbrked_mem += brk - (char*)old_end; + + /* Guarantee alignment of first new chunk made from this space */ + front_misalign = (unsigned long)chunk2mem(brk) & MALLOC_ALIGN_MASK; + if (front_misalign > 0) + { + correction = (MALLOC_ALIGNMENT) - front_misalign; + brk += correction; + } + else + correction = 0; + + /* Guarantee the next brk will be at a page boundary */ + + correction += ((((unsigned long)(brk + sbrk_size))+(pagesz-1)) & + ~(pagesz - 1)) - ((unsigned long)(brk + sbrk_size)); + + /* Allocate correction */ + new_brk = (char*)(MORECORE (correction)); + if (new_brk == (char*)(MORECORE_FAILURE)) return; + + sbrked_mem += correction; + + top = (mchunkptr)brk; + top_size = new_brk - brk + correction; + set_head(top, top_size | PREV_INUSE); + + if (old_top != initial_top) + { + + /* There must have been an intervening foreign sbrk call. */ + /* A double fencepost is necessary to prevent consolidation */ + + /* If not enough space to do this, then user did something very wrong */ + if (old_top_size < MINSIZE) + { + set_head(top, PREV_INUSE); /* will force null return from malloc */ + return; + } + + /* Also keep size a multiple of MALLOC_ALIGNMENT */ + old_top_size = (old_top_size - 3*SIZE_SZ) & ~MALLOC_ALIGN_MASK; + set_head_size(old_top, old_top_size); + chunk_at_offset(old_top, old_top_size )->size = + SIZE_SZ|PREV_INUSE; + chunk_at_offset(old_top, old_top_size + SIZE_SZ)->size = + SIZE_SZ|PREV_INUSE; + /* If possible, release the rest. */ + if (old_top_size >= MINSIZE) + fREe(chunk2mem(old_top)); + } + } + + if ((unsigned long)sbrked_mem > (unsigned long)max_sbrked_mem) + max_sbrked_mem = sbrked_mem; + if ((unsigned long)(mmapped_mem + sbrked_mem) > (unsigned long)max_total_mem) + max_total_mem = mmapped_mem + sbrked_mem; + + /* We always land on a page boundary */ + assert(((unsigned long)((char*)top + top_size) & (pagesz - 1)) == 0); +} + + + + +/* Main public routines */ + + +/* + Malloc Algorthim: + + The requested size is first converted into a usable form, `nb'. + This currently means to add 4 bytes overhead plus possibly more to + obtain 8-byte alignment and/or to obtain a size of at least + MINSIZE (currently 16 bytes), the smallest allocatable size. + (All fits are considered `exact' if they are within MINSIZE bytes.) + + From there, the first successful of the following steps is taken: + + 1. The bin corresponding to the request size is scanned, and if + a chunk of exactly the right size is found, it is taken. + + 2. The most recently remaindered chunk is used if it is big + enough. This is a form of (roving) first fit, used only in + the absence of exact fits. Runs of consecutive requests use + the remainder of the chunk used for the previous such request + whenever possible. This limited use of a first-fit style + allocation strategy tends to give contiguous chunks + coextensive lifetimes, which improves locality and can reduce + fragmentation in the long run. + + 3. Other bins are scanned in increasing size order, using a + chunk big enough to fulfill the request, and splitting off + any remainder. This search is strictly by best-fit; i.e., + the smallest (with ties going to approximately the least + recently used) chunk that fits is selected. + + 4. If large enough, the chunk bordering the end of memory + (`top') is split off. (This use of `top' is in accord with + the best-fit search rule. In effect, `top' is treated as + larger (and thus less well fitting) than any other available + chunk since it can be extended to be as large as necessary + (up to system limitations). + + 5. If the request size meets the mmap threshold and the + system supports mmap, and there are few enough currently + allocated mmapped regions, and a call to mmap succeeds, + the request is allocated via direct memory mapping. + + 6. Otherwise, the top of memory is extended by + obtaining more space from the system (normally using sbrk, + but definable to anything else via the MORECORE macro). + Memory is gathered from the system (in system page-sized + units) in a way that allows chunks obtained across different + sbrk calls to be consolidated, but does not require + contiguous memory. Thus, it should be safe to intersperse + mallocs with other sbrk calls. + + + All allocations are made from the the `lowest' part of any found + chunk. (The implementation invariant is that prev_inuse is + always true of any allocated chunk; i.e., that each allocated + chunk borders either a previously allocated and still in-use chunk, + or the base of its memory arena.) + +*/ + +#if __STD_C +Void_t* mALLOc(size_t bytes) +#else +Void_t* mALLOc(bytes) size_t bytes; +#endif +{ + mchunkptr victim; /* inspected/selected chunk */ + INTERNAL_SIZE_T victim_size; /* its size */ + int idx; /* index for bin traversal */ + mbinptr bin; /* associated bin */ + mchunkptr remainder; /* remainder from a split */ + long remainder_size; /* its size */ + int remainder_index; /* its bin index */ + unsigned long block; /* block traverser bit */ + int startidx; /* first bin of a traversed block */ + mchunkptr fwd; /* misc temp for linking */ + mchunkptr bck; /* misc temp for linking */ + mbinptr q; /* misc temp */ + + INTERNAL_SIZE_T nb; + + if ((long)bytes < 0) return 0; + + nb = request2size(bytes); /* padded request size; */ + + /* Check for exact match in a bin */ + + if (is_small_request(nb)) /* Faster version for small requests */ + { + idx = smallbin_index(nb); + + /* No traversal or size check necessary for small bins. */ + + q = bin_at(idx); + victim = last(q); + + /* Also scan the next one, since it would have a remainder < MINSIZE */ + if (victim == q) + { + q = next_bin(q); + victim = last(q); + } + if (victim != q) + { + victim_size = chunksize(victim); + unlink(victim, bck, fwd); + set_inuse_bit_at_offset(victim, victim_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + idx += 2; /* Set for bin scan below. We've already scanned 2 bins. */ + + } + else + { + idx = bin_index(nb); + bin = bin_at(idx); + + for (victim = last(bin); victim != bin; victim = victim->bk) + { + victim_size = chunksize(victim); + remainder_size = victim_size - nb; + + if (remainder_size >= (long)MINSIZE) /* too big */ + { + --idx; /* adjust to rescan below after checking last remainder */ + break; + } + + else if (remainder_size >= 0) /* exact fit */ + { + unlink(victim, bck, fwd); + set_inuse_bit_at_offset(victim, victim_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + } + + ++idx; + + } + + /* Try to use the last split-off remainder */ + + if ( (victim = last_remainder->fd) != last_remainder) + { + victim_size = chunksize(victim); + remainder_size = victim_size - nb; + + if (remainder_size >= (long)MINSIZE) /* re-split */ + { + remainder = chunk_at_offset(victim, nb); + set_head(victim, nb | PREV_INUSE); + link_last_remainder(remainder); + set_head(remainder, remainder_size | PREV_INUSE); + set_foot(remainder, remainder_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + clear_last_remainder; + + if (remainder_size >= 0) /* exhaust */ + { + set_inuse_bit_at_offset(victim, victim_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + /* Else place in bin */ + + frontlink(victim, victim_size, remainder_index, bck, fwd); + } + + /* + If there are any possibly nonempty big-enough blocks, + search for best fitting chunk by scanning bins in blockwidth units. + */ + + if ( (block = idx2binblock(idx)) <= binblocks) + { + + /* Get to the first marked block */ + + if ( (block & binblocks) == 0) + { + /* force to an even block boundary */ + idx = (idx & ~(BINBLOCKWIDTH - 1)) + BINBLOCKWIDTH; + block <<= 1; + while ((block & binblocks) == 0) + { + idx += BINBLOCKWIDTH; + block <<= 1; + } + } + + /* For each possibly nonempty block ... */ + for (;;) + { + startidx = idx; /* (track incomplete blocks) */ + q = bin = bin_at(idx); + + /* For each bin in this block ... */ + do + { + /* Find and use first big enough chunk ... */ + + for (victim = last(bin); victim != bin; victim = victim->bk) + { + victim_size = chunksize(victim); + remainder_size = victim_size - nb; + + if (remainder_size >= (long)MINSIZE) /* split */ + { + remainder = chunk_at_offset(victim, nb); + set_head(victim, nb | PREV_INUSE); + unlink(victim, bck, fwd); + link_last_remainder(remainder); + set_head(remainder, remainder_size | PREV_INUSE); + set_foot(remainder, remainder_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + else if (remainder_size >= 0) /* take */ + { + set_inuse_bit_at_offset(victim, victim_size); + unlink(victim, bck, fwd); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + } + + bin = next_bin(bin); + + } while ((++idx & (BINBLOCKWIDTH - 1)) != 0); + + /* Clear out the block bit. */ + + do /* Possibly backtrack to try to clear a partial block */ + { + if ((startidx & (BINBLOCKWIDTH - 1)) == 0) + { + binblocks &= ~block; + break; + } + --startidx; + q = prev_bin(q); + } while (first(q) == q); + + /* Get to the next possibly nonempty block */ + + if ( (block <<= 1) <= binblocks && (block != 0) ) + { + while ((block & binblocks) == 0) + { + idx += BINBLOCKWIDTH; + block <<= 1; + } + } + else + break; + } + } + + + /* Try to use top chunk */ + + /* Require that there be a remainder, ensuring top always exists */ + if ( (remainder_size = chunksize(top) - nb) < (long)MINSIZE) + { + +#if HAVE_MMAP + /* If big and would otherwise need to extend, try to use mmap instead */ + if ((unsigned long)nb >= (unsigned long)mmap_threshold && + (victim = mmap_chunk(nb)) != 0) + return chunk2mem(victim); +#endif + + /* Try to extend */ + malloc_extend_top(nb); + if ( (remainder_size = chunksize(top) - nb) < (long)MINSIZE) + return 0; /* propagate failure */ + } + + victim = top; + set_head(victim, nb | PREV_INUSE); + top = chunk_at_offset(victim, nb); + set_head(top, remainder_size | PREV_INUSE); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + +} + + + + +/* + + free() algorithm : + + cases: + + 1. free(0) has no effect. + + 2. If the chunk was allocated via mmap, it is release via munmap(). + + 3. If a returned chunk borders the current high end of memory, + it is consolidated into the top, and if the total unused + topmost memory exceeds the trim threshold, malloc_trim is + called. + + 4. Other chunks are consolidated as they arrive, and + placed in corresponding bins. (This includes the case of + consolidating with the current `last_remainder'). + +*/ + + +#if __STD_C +void fREe(Void_t* mem) +#else +void fREe(mem) Void_t* mem; +#endif +{ + mchunkptr p; /* chunk corresponding to mem */ + INTERNAL_SIZE_T hd; /* its head field */ + INTERNAL_SIZE_T sz; /* its size */ + int idx; /* its bin index */ + mchunkptr next; /* next contiguous chunk */ + INTERNAL_SIZE_T nextsz; /* its size */ + INTERNAL_SIZE_T prevsz; /* size of previous contiguous chunk */ + mchunkptr bck; /* misc temp for linking */ + mchunkptr fwd; /* misc temp for linking */ + int islr; /* track whether merging with last_remainder */ + + if (mem == 0) /* free(0) has no effect */ + return; + + p = mem2chunk(mem); + hd = p->size; + +#if HAVE_MMAP + if (hd & IS_MMAPPED) /* release mmapped memory. */ + { + munmap_chunk(p); + return; + } +#endif + + check_inuse_chunk(p); + + sz = hd & ~PREV_INUSE; + next = chunk_at_offset(p, sz); + nextsz = chunksize(next); + + if (next == top) /* merge with top */ + { + sz += nextsz; + + if (!(hd & PREV_INUSE)) /* consolidate backward */ + { + prevsz = p->prev_size; + p = chunk_at_offset(p, -((long) prevsz)); + sz += prevsz; + unlink(p, bck, fwd); + } + + set_head(p, sz | PREV_INUSE); + top = p; + if ((unsigned long)(sz) >= (unsigned long)trim_threshold) + malloc_trim(top_pad); + return; + } + + set_head(next, nextsz); /* clear inuse bit */ + + islr = 0; + + if (!(hd & PREV_INUSE)) /* consolidate backward */ + { + prevsz = p->prev_size; + p = chunk_at_offset(p, -((long) prevsz)); + sz += prevsz; + + if (p->fd == last_remainder) /* keep as last_remainder */ + islr = 1; + else + unlink(p, bck, fwd); + } + + if (!(inuse_bit_at_offset(next, nextsz))) /* consolidate forward */ + { + sz += nextsz; + + if (!islr && next->fd == last_remainder) /* re-insert last_remainder */ + { + islr = 1; + link_last_remainder(p); + } + else + unlink(next, bck, fwd); + } + + + set_head(p, sz | PREV_INUSE); + set_foot(p, sz); + if (!islr) + frontlink(p, sz, idx, bck, fwd); +} + + + + + +/* + + Realloc algorithm: + + Chunks that were obtained via mmap cannot be extended or shrunk + unless HAVE_MREMAP is defined, in which case mremap is used. + Otherwise, if their reallocation is for additional space, they are + copied. If for less, they are just left alone. + + Otherwise, if the reallocation is for additional space, and the + chunk can be extended, it is, else a malloc-copy-free sequence is + taken. There are several different ways that a chunk could be + extended. All are tried: + + * Extending forward into following adjacent free chunk. + * Shifting backwards, joining preceding adjacent space + * Both shifting backwards and extending forward. + * Extending into newly sbrked space + + Unless the #define REALLOC_ZERO_BYTES_FREES is set, realloc with a + size argument of zero (re)allocates a minimum-sized chunk. + + If the reallocation is for less space, and the new request is for + a `small' (<512 bytes) size, then the newly unused space is lopped + off and freed. + + The old unix realloc convention of allowing the last-free'd chunk + to be used as an argument to realloc is no longer supported. + I don't know of any programs still relying on this feature, + and allowing it would also allow too many other incorrect + usages of realloc to be sensible. + + +*/ + + +#if __STD_C +Void_t* rEALLOc(Void_t* oldmem, size_t bytes) +#else +Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; +#endif +{ + INTERNAL_SIZE_T nb; /* padded request size */ + + mchunkptr oldp; /* chunk corresponding to oldmem */ + INTERNAL_SIZE_T oldsize; /* its size */ + + mchunkptr newp; /* chunk to return */ + INTERNAL_SIZE_T newsize; /* its size */ + Void_t* newmem; /* corresponding user mem */ + + mchunkptr next; /* next contiguous chunk after oldp */ + INTERNAL_SIZE_T nextsize; /* its size */ + + mchunkptr prev; /* previous contiguous chunk before oldp */ + INTERNAL_SIZE_T prevsize; /* its size */ + + mchunkptr remainder; /* holds split off extra space from newp */ + INTERNAL_SIZE_T remainder_size; /* its size */ + + mchunkptr bck; /* misc temp for linking */ + mchunkptr fwd; /* misc temp for linking */ + +#ifdef REALLOC_ZERO_BYTES_FREES + if (bytes == 0) { fREe(oldmem); return 0; } +#endif + + if ((long)bytes < 0) return 0; + + /* realloc of null is supposed to be same as malloc */ + if (oldmem == 0) return mALLOc(bytes); + + newp = oldp = mem2chunk(oldmem); + newsize = oldsize = chunksize(oldp); + + + nb = request2size(bytes); + +#if HAVE_MMAP + if (chunk_is_mmapped(oldp)) + { +#if HAVE_MREMAP + newp = mremap_chunk(oldp, nb); + if(newp) return chunk2mem(newp); +#endif + /* Note the extra SIZE_SZ overhead. */ + if(oldsize - SIZE_SZ >= nb) return oldmem; /* do nothing */ + /* Must alloc, copy, free. */ + newmem = mALLOc(bytes); + if (newmem == 0) return 0; /* propagate failure */ + MALLOC_COPY(newmem, oldmem, oldsize - 2*SIZE_SZ); + munmap_chunk(oldp); + return newmem; + } +#endif + + check_inuse_chunk(oldp); + + if ((long)(oldsize) < (long)(nb)) + { + + /* Try expanding forward */ + + next = chunk_at_offset(oldp, oldsize); + if (next == top || !inuse(next)) + { + nextsize = chunksize(next); + + /* Forward into top only if a remainder */ + if (next == top) + { + if ((long)(nextsize + newsize) >= (long)(nb + MINSIZE)) + { + newsize += nextsize; + top = chunk_at_offset(oldp, nb); + set_head(top, (newsize - nb) | PREV_INUSE); + set_head_size(oldp, nb); + return chunk2mem(oldp); + } + } + + /* Forward into next chunk */ + else if (((long)(nextsize + newsize) >= (long)(nb))) + { + unlink(next, bck, fwd); + newsize += nextsize; + goto split; + } + } + else + { + next = 0; + nextsize = 0; + } + + /* Try shifting backwards. */ + + if (!prev_inuse(oldp)) + { + prev = prev_chunk(oldp); + prevsize = chunksize(prev); + + /* try forward + backward first to save a later consolidation */ + + if (next != 0) + { + /* into top */ + if (next == top) + { + if ((long)(nextsize + prevsize + newsize) >= (long)(nb + MINSIZE)) + { + unlink(prev, bck, fwd); + newp = prev; + newsize += prevsize + nextsize; + newmem = chunk2mem(newp); + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + top = chunk_at_offset(newp, nb); + set_head(top, (newsize - nb) | PREV_INUSE); + set_head_size(newp, nb); + return newmem; + } + } + + /* into next chunk */ + else if (((long)(nextsize + prevsize + newsize) >= (long)(nb))) + { + unlink(next, bck, fwd); + unlink(prev, bck, fwd); + newp = prev; + newsize += nextsize + prevsize; + newmem = chunk2mem(newp); + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + goto split; + } + } + + /* backward only */ + if (prev != 0 && (long)(prevsize + newsize) >= (long)nb) + { + unlink(prev, bck, fwd); + newp = prev; + newsize += prevsize; + newmem = chunk2mem(newp); + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + goto split; + } + } + + /* Must allocate */ + + newmem = mALLOc (bytes); + + if (newmem == 0) /* propagate failure */ + return 0; + + /* Avoid copy if newp is next chunk after oldp. */ + /* (This can only happen when new chunk is sbrk'ed.) */ + + if ( (newp = mem2chunk(newmem)) == next_chunk(oldp)) + { + newsize += chunksize(newp); + newp = oldp; + goto split; + } + + /* Otherwise copy, free, and exit */ + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + fREe(oldmem); + return newmem; + } + + + split: /* split off extra room in old or expanded chunk */ + + if (newsize - nb >= MINSIZE) /* split off remainder */ + { + remainder = chunk_at_offset(newp, nb); + remainder_size = newsize - nb; + set_head_size(newp, nb); + set_head(remainder, remainder_size | PREV_INUSE); + set_inuse_bit_at_offset(remainder, remainder_size); + fREe(chunk2mem(remainder)); /* let free() deal with it */ + } + else + { + set_head_size(newp, newsize); + set_inuse_bit_at_offset(newp, newsize); + } + + check_inuse_chunk(newp); + return chunk2mem(newp); +} + + + + +/* + + memalign algorithm: + + memalign requests more than enough space from malloc, finds a spot + within that chunk that meets the alignment request, and then + possibly frees the leading and trailing space. + + The alignment argument must be a power of two. This property is not + checked by memalign, so misuse may result in random runtime errors. + + 8-byte alignment is guaranteed by normal malloc calls, so don't + bother calling memalign with an argument of 8 or less. + + Overreliance on memalign is a sure way to fragment space. + +*/ + + +#if __STD_C +Void_t* mEMALIGn(size_t alignment, size_t bytes) +#else +Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; +#endif +{ + INTERNAL_SIZE_T nb; /* padded request size */ + char* m; /* memory returned by malloc call */ + mchunkptr p; /* corresponding chunk */ + char* brk; /* alignment point within p */ + mchunkptr newp; /* chunk to return */ + INTERNAL_SIZE_T newsize; /* its size */ + INTERNAL_SIZE_T leadsize; /* leading space befor alignment point */ + mchunkptr remainder; /* spare room at end to split off */ + long remainder_size; /* its size */ + + if ((long)bytes < 0) return 0; + + /* If need less alignment than we give anyway, just relay to malloc */ + + if (alignment <= MALLOC_ALIGNMENT) return mALLOc(bytes); + + /* Otherwise, ensure that it is at least a minimum chunk size */ + + if (alignment < MINSIZE) alignment = MINSIZE; + + /* Call malloc with worst case padding to hit alignment. */ + + nb = request2size(bytes); + m = (char*)(mALLOc(nb + alignment + MINSIZE)); + + if (m == 0) return 0; /* propagate failure */ + + p = mem2chunk(m); + + if ((((unsigned long)(m)) % alignment) == 0) /* aligned */ + { +#if HAVE_MMAP + if(chunk_is_mmapped(p)) + return chunk2mem(p); /* nothing more to do */ +#endif + } + else /* misaligned */ + { + /* + Find an aligned spot inside chunk. + Since we need to give back leading space in a chunk of at + least MINSIZE, if the first calculation places us at + a spot with less than MINSIZE leader, we can move to the + next aligned spot -- we've allocated enough total room so that + this is always possible. + */ + + brk = (char*)mem2chunk(((unsigned long)(m + alignment - 1)) & -((signed) alignment)); + if ((long)(brk - (char*)(p)) < MINSIZE) brk = brk + alignment; + + newp = (mchunkptr)brk; + leadsize = brk - (char*)(p); + newsize = chunksize(p) - leadsize; + +#if HAVE_MMAP + if(chunk_is_mmapped(p)) + { + newp->prev_size = p->prev_size + leadsize; + set_head(newp, newsize|IS_MMAPPED); + return chunk2mem(newp); + } +#endif + + /* give back leader, use the rest */ + + set_head(newp, newsize | PREV_INUSE); + set_inuse_bit_at_offset(newp, newsize); + set_head_size(p, leadsize); + fREe(chunk2mem(p)); + p = newp; + + assert (newsize >= nb && (((unsigned long)(chunk2mem(p))) % alignment) == 0); + } + + /* Also give back spare room at the end */ + + remainder_size = chunksize(p) - nb; + + if (remainder_size >= (long)MINSIZE) + { + remainder = chunk_at_offset(p, nb); + set_head(remainder, remainder_size | PREV_INUSE); + set_head_size(p, nb); + fREe(chunk2mem(remainder)); + } + + check_inuse_chunk(p); + return chunk2mem(p); + +} + + + + +/* + valloc just invokes memalign with alignment argument equal + to the page size of the system (or as near to this as can + be figured out from all the includes/defines above.) +*/ + +#if __STD_C +Void_t* vALLOc(size_t bytes) +#else +Void_t* vALLOc(bytes) size_t bytes; +#endif +{ + return mEMALIGn (malloc_getpagesize, bytes); +} + +/* + pvalloc just invokes valloc for the nearest pagesize + that will accommodate request +*/ + + +#if __STD_C +Void_t* pvALLOc(size_t bytes) +#else +Void_t* pvALLOc(bytes) size_t bytes; +#endif +{ + size_t pagesize = malloc_getpagesize; + return mEMALIGn (pagesize, (bytes + pagesize - 1) & ~(pagesize - 1)); +} + +/* + + calloc calls malloc, then zeroes out the allocated chunk. + +*/ + +#if __STD_C +Void_t* cALLOc(size_t n, size_t elem_size) +#else +Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; +#endif +{ + mchunkptr p; + INTERNAL_SIZE_T csz; + + INTERNAL_SIZE_T sz = n * elem_size; + + + /* check if expand_top called, in which case don't need to clear */ +#if MORECORE_CLEARS + mchunkptr oldtop = top; + INTERNAL_SIZE_T oldtopsize = chunksize(top); +#endif + Void_t* mem = mALLOc (sz); + + if ((long)n < 0) return 0; + + if (mem == 0) + return 0; + else + { + p = mem2chunk(mem); + + /* Two optional cases in which clearing not necessary */ + + +#if HAVE_MMAP + if (chunk_is_mmapped(p)) return mem; +#endif + + csz = chunksize(p); + +#if MORECORE_CLEARS + if (p == oldtop && csz > oldtopsize) + { + /* clear only the bytes from non-freshly-sbrked memory */ + csz = oldtopsize; + } +#endif + + MALLOC_ZERO(mem, csz - SIZE_SZ); + return mem; + } +} + +/* + + cfree just calls free. It is needed/defined on some systems + that pair it with calloc, presumably for odd historical reasons. + +*/ + +#if !defined(INTERNAL_LINUX_C_LIB) || !defined(__ELF__) +#if __STD_C +void cfree(Void_t *mem) +#else +void cfree(mem) Void_t *mem; +#endif +{ + fREe(mem); +} +#endif + + + +/* + + Malloc_trim gives memory back to the system (via negative + arguments to sbrk) if there is unused memory at the `high' end of + the malloc pool. You can call this after freeing large blocks of + memory to potentially reduce the system-level memory requirements + of a program. However, it cannot guarantee to reduce memory. Under + some allocation patterns, some large free blocks of memory will be + locked between two used chunks, so they cannot be given back to + the system. + + The `pad' argument to malloc_trim represents the amount of free + trailing space to leave untrimmed. If this argument is zero, + only the minimum amount of memory to maintain internal data + structures will be left (one page or less). Non-zero arguments + can be supplied to maintain enough trailing space to service + future expected allocations without having to re-obtain memory + from the system. + + Malloc_trim returns 1 if it actually released any memory, else 0. + +*/ + +#if __STD_C +int malloc_trim(size_t pad) +#else +int malloc_trim(pad) size_t pad; +#endif +{ + long top_size; /* Amount of top-most memory */ + long extra; /* Amount to release */ + char* current_brk; /* address returned by pre-check sbrk call */ + char* new_brk; /* address returned by negative sbrk call */ + + unsigned long pagesz = malloc_getpagesize; + + top_size = chunksize(top); + extra = ((top_size - pad - MINSIZE + (pagesz-1)) / pagesz - 1) * pagesz; + + if (extra < (long)pagesz) /* Not enough memory to release */ + return 0; + + else + { + /* Test to make sure no one else called sbrk */ + current_brk = (char*)(MORECORE (0)); + if (current_brk != (char*)(top) + top_size) + return 0; /* Apparently we don't own memory; must fail */ + + else + { + new_brk = (char*)(MORECORE (-extra)); + + if (new_brk == (char*)(MORECORE_FAILURE)) /* sbrk failed? */ + { + /* Try to figure out what we have */ + current_brk = (char*)(MORECORE (0)); + top_size = current_brk - (char*)top; + if (top_size >= (long)MINSIZE) /* if not, we are very very dead! */ + { + sbrked_mem = current_brk - sbrk_base; + set_head(top, top_size | PREV_INUSE); + } + check_chunk(top); + return 0; + } + + else + { + /* Success. Adjust top accordingly. */ + set_head(top, (top_size - extra) | PREV_INUSE); + sbrked_mem -= extra; + check_chunk(top); + return 1; + } + } + } +} + + + +/* + malloc_usable_size: + + This routine tells you how many bytes you can actually use in an + allocated chunk, which may be more than you requested (although + often not). You can use this many bytes without worrying about + overwriting other allocated objects. Not a particularly great + programming practice, but still sometimes useful. + +*/ + +#if __STD_C +size_t malloc_usable_size(Void_t* mem) +#else +size_t malloc_usable_size(mem) Void_t* mem; +#endif +{ + mchunkptr p; + if (mem == 0) + return 0; + else + { + p = mem2chunk(mem); + if(!chunk_is_mmapped(p)) + { + if (!inuse(p)) return 0; + check_inuse_chunk(p); + return chunksize(p) - SIZE_SZ; + } + return chunksize(p) - 2*SIZE_SZ; + } +} + + + + +/* Utility to update current_mallinfo for malloc_stats and mallinfo() */ + +#if 0 +static void malloc_update_mallinfo() +{ + int i; + mbinptr b; + mchunkptr p; +#ifdef DEBUG + mchunkptr q; +#endif + + INTERNAL_SIZE_T avail = chunksize(top); + int navail = ((long)(avail) >= (long)MINSIZE)? 1 : 0; + + for (i = 1; i < NAV; ++i) + { + b = bin_at(i); + for (p = last(b); p != b; p = p->bk) + { +#ifdef DEBUG + check_free_chunk(p); + for (q = next_chunk(p); + q < top && inuse(q) && (long)(chunksize(q)) >= (long)MINSIZE; + q = next_chunk(q)) + check_inuse_chunk(q); +#endif + avail += chunksize(p); + navail++; + } + } + + current_mallinfo.ordblks = navail; + current_mallinfo.uordblks = sbrked_mem - avail; + current_mallinfo.fordblks = avail; + current_mallinfo.hblks = n_mmaps; + current_mallinfo.hblkhd = mmapped_mem; + current_mallinfo.keepcost = chunksize(top); + +} +#endif /* 0 */ + + + +/* + + malloc_stats: + + Prints on the amount of space obtain from the system (both + via sbrk and mmap), the maximum amount (which may be more than + current if malloc_trim and/or munmap got called), the maximum + number of simultaneous mmap regions used, and the current number + of bytes allocated via malloc (or realloc, etc) but not yet + freed. (Note that this is the number of bytes allocated, not the + number requested. It will be larger than the number requested + because of alignment and bookkeeping overhead.) + +*/ + +#if 0 +void malloc_stats() +{ + malloc_update_mallinfo(); + printf("max system bytes = %10u\n", + (unsigned int)(max_total_mem)); + printf("system bytes = %10u\n", + (unsigned int)(sbrked_mem + mmapped_mem)); + printf("in use bytes = %10u\n", + (unsigned int)(current_mallinfo.uordblks + mmapped_mem)); +#if HAVE_MMAP + printf("max mmap regions = %10u\n", + (unsigned int)max_n_mmaps); +#endif +} +#endif /* 0 */ + +/* + mallinfo returns a copy of updated current mallinfo. +*/ + +#if 0 +struct mallinfo mALLINFo() +{ + malloc_update_mallinfo(); + return current_mallinfo; +} +#endif /* 0 */ + + + + +/* + mallopt: + + mallopt is the general SVID/XPG interface to tunable parameters. + The format is to provide a (parameter-number, parameter-value) pair. + mallopt then sets the corresponding parameter to the argument + value if it can (i.e., so long as the value is meaningful), + and returns 1 if successful else 0. + + See descriptions of tunable parameters above. + +*/ + +#if __STD_C +int mALLOPt(int param_number, int value) +#else +int mALLOPt(param_number, value) int param_number; int value; +#endif +{ + switch(param_number) + { + case M_TRIM_THRESHOLD: + trim_threshold = value; return 1; + case M_TOP_PAD: + top_pad = value; return 1; + case M_MMAP_THRESHOLD: + mmap_threshold = value; return 1; + case M_MMAP_MAX: +#if HAVE_MMAP + n_mmaps_max = value; return 1; +#else + if (value != 0) return 0; else n_mmaps_max = value; return 1; +#endif + + default: + return 0; + } +} + +/* + +History: + + V2.6.6 Sun Dec 5 07:42:19 1999 Doug Lea (dl at gee) + * return null for negative arguments + * Added Several WIN32 cleanups from Martin C. Fong + * Add 'LACKS_SYS_PARAM_H' for those systems without 'sys/param.h' + (e.g. WIN32 platforms) + * Cleanup up header file inclusion for WIN32 platforms + * Cleanup code to avoid Microsoft Visual C++ compiler complaints + * Add 'USE_DL_PREFIX' to quickly allow co-existence with existing + memory allocation routines + * Set 'malloc_getpagesize' for WIN32 platforms (needs more work) + * Use 'assert' rather than 'ASSERT' in WIN32 code to conform to + usage of 'assert' in non-WIN32 code + * Improve WIN32 'sbrk()' emulation's 'findRegion()' routine to + avoid infinite loop + * Always call 'fREe()' rather than 'free()' + + V2.6.5 Wed Jun 17 15:57:31 1998 Doug Lea (dl at gee) + * Fixed ordering problem with boundary-stamping + + V2.6.3 Sun May 19 08:17:58 1996 Doug Lea (dl at gee) + * Added pvalloc, as recommended by H.J. Liu + * Added 64bit pointer support mainly from Wolfram Gloger + * Added anonymously donated WIN32 sbrk emulation + * Malloc, calloc, getpagesize: add optimizations from Raymond Nijssen + * malloc_extend_top: fix mask error that caused wastage after + foreign sbrks + * Add linux mremap support code from HJ Liu + + V2.6.2 Tue Dec 5 06:52:55 1995 Doug Lea (dl at gee) + * Integrated most documentation with the code. + * Add support for mmap, with help from + Wolfram Gloger (Gloger@lrz.uni-muenchen.de). + * Use last_remainder in more cases. + * Pack bins using idea from colin@nyx10.cs.du.edu + * Use ordered bins instead of best-fit threshhold + * Eliminate block-local decls to simplify tracing and debugging. + * Support another case of realloc via move into top + * Fix error occuring when initial sbrk_base not word-aligned. + * Rely on page size for units instead of SBRK_UNIT to + avoid surprises about sbrk alignment conventions. + * Add mallinfo, mallopt. Thanks to Raymond Nijssen + (raymond@es.ele.tue.nl) for the suggestion. + * Add `pad' argument to malloc_trim and top_pad mallopt parameter. + * More precautions for cases where other routines call sbrk, + courtesy of Wolfram Gloger (Gloger@lrz.uni-muenchen.de). + * Added macros etc., allowing use in linux libc from + H.J. Lu (hjl@gnu.ai.mit.edu) + * Inverted this history list + + V2.6.1 Sat Dec 2 14:10:57 1995 Doug Lea (dl at gee) + * Re-tuned and fixed to behave more nicely with V2.6.0 changes. + * Removed all preallocation code since under current scheme + the work required to undo bad preallocations exceeds + the work saved in good cases for most test programs. + * No longer use return list or unconsolidated bins since + no scheme using them consistently outperforms those that don't + given above changes. + * Use best fit for very large chunks to prevent some worst-cases. + * Added some support for debugging + + V2.6.0 Sat Nov 4 07:05:23 1995 Doug Lea (dl at gee) + * Removed footers when chunks are in use. Thanks to + Paul Wilson (wilson@cs.texas.edu) for the suggestion. + + V2.5.4 Wed Nov 1 07:54:51 1995 Doug Lea (dl at gee) + * Added malloc_trim, with help from Wolfram Gloger + (wmglo@Dent.MED.Uni-Muenchen.DE). + + V2.5.3 Tue Apr 26 10:16:01 1994 Doug Lea (dl at g) + + V2.5.2 Tue Apr 5 16:20:40 1994 Doug Lea (dl at g) + * realloc: try to expand in both directions + * malloc: swap order of clean-bin strategy; + * realloc: only conditionally expand backwards + * Try not to scavenge used bins + * Use bin counts as a guide to preallocation + * Occasionally bin return list chunks in first scan + * Add a few optimizations from colin@nyx10.cs.du.edu + + V2.5.1 Sat Aug 14 15:40:43 1993 Doug Lea (dl at g) + * faster bin computation & slightly different binning + * merged all consolidations to one part of malloc proper + (eliminating old malloc_find_space & malloc_clean_bin) + * Scan 2 returns chunks (not just 1) + * Propagate failure in realloc if malloc returns 0 + * Add stuff to allow compilation on non-ANSI compilers + from kpv@research.att.com + + V2.5 Sat Aug 7 07:41:59 1993 Doug Lea (dl at g.oswego.edu) + * removed potential for odd address access in prev_chunk + * removed dependency on getpagesize.h + * misc cosmetics and a bit more internal documentation + * anticosmetics: mangled names in macros to evade debugger strangeness + * tested on sparc, hp-700, dec-mips, rs6000 + with gcc & native cc (hp, dec only) allowing + Detlefs & Zorn comparison study (in SIGPLAN Notices.) + + Trial version Fri Aug 28 13:14:29 1992 Doug Lea (dl at g.oswego.edu) + * Based loosely on libg++-1.2X malloc. (It retains some of the overall + structure of old version, but most details differ.) + +*/ diff --git a/common/dlmalloc.src b/common/dlmalloc.src new file mode 100644 index 0000000..32a38bc --- /dev/null +++ b/common/dlmalloc.src @@ -0,0 +1,3265 @@ +/* ---------- To make a malloc.h, start cutting here ------------ */ + +/* + A version of malloc/free/realloc written by Doug Lea and released to the + public domain. Send questions/comments/complaints/performance data + to dl@cs.oswego.edu + +* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee) + + Note: There may be an updated version of this malloc obtainable at + ftp://g.oswego.edu/pub/misc/malloc.c + Check before installing! + +* Why use this malloc? + + This is not the fastest, most space-conserving, most portable, or + most tunable malloc ever written. However it is among the fastest + while also being among the most space-conserving, portable and tunable. + Consistent balance across these factors results in a good general-purpose + allocator. For a high-level description, see + http://g.oswego.edu/dl/html/malloc.html + +* Synopsis of public routines + + (Much fuller descriptions are contained in the program documentation below.) + + malloc(size_t n); + Return a pointer to a newly allocated chunk of at least n bytes, or null + if no space is available. + free(Void_t* p); + Release the chunk of memory pointed to by p, or no effect if p is null. + realloc(Void_t* p, size_t n); + Return a pointer to a chunk of size n that contains the same data + as does chunk p up to the minimum of (n, p's size) bytes, or null + if no space is available. The returned pointer may or may not be + the same as p. If p is null, equivalent to malloc. Unless the + #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a + size argument of zero (re)allocates a minimum-sized chunk. + memalign(size_t alignment, size_t n); + Return a pointer to a newly allocated chunk of n bytes, aligned + in accord with the alignment argument, which must be a power of + two. + valloc(size_t n); + Equivalent to memalign(pagesize, n), where pagesize is the page + size of the system (or as near to this as can be figured out from + all the includes/defines below.) + pvalloc(size_t n); + Equivalent to valloc(minimum-page-that-holds(n)), that is, + round up n to nearest pagesize. + calloc(size_t unit, size_t quantity); + Returns a pointer to quantity * unit bytes, with all locations + set to zero. + cfree(Void_t* p); + Equivalent to free(p). + malloc_trim(size_t pad); + Release all but pad bytes of freed top-most memory back + to the system. Return 1 if successful, else 0. + malloc_usable_size(Void_t* p); + Report the number usable allocated bytes associated with allocated + chunk p. This may or may not report more bytes than were requested, + due to alignment and minimum size constraints. + malloc_stats(); + Prints brief summary statistics on stderr. + mallinfo() + Returns (by copy) a struct containing various summary statistics. + mallopt(int parameter_number, int parameter_value) + Changes one of the tunable parameters described below. Returns + 1 if successful in changing the parameter, else 0. + +* Vital statistics: + + Alignment: 8-byte + 8 byte alignment is currently hardwired into the design. This + seems to suffice for all current machines and C compilers. + + Assumed pointer representation: 4 or 8 bytes + Code for 8-byte pointers is untested by me but has worked + reliably by Wolfram Gloger, who contributed most of the + changes supporting this. + + Assumed size_t representation: 4 or 8 bytes + Note that size_t is allowed to be 4 bytes even if pointers are 8. + + Minimum overhead per allocated chunk: 4 or 8 bytes + Each malloced chunk has a hidden overhead of 4 bytes holding size + and status information. + + Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead) + 8-byte ptrs: 24/32 bytes (including, 4/8 overhead) + + When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte + ptrs but 4 byte size) or 24 (for 8/8) additional bytes are + needed; 4 (8) for a trailing size field + and 8 (16) bytes for free list pointers. Thus, the minimum + allocatable size is 16/24/32 bytes. + + Even a request for zero bytes (i.e., malloc(0)) returns a + pointer to something of the minimum allocatable size. + + Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes + 8-byte size_t: 2^63 - 16 bytes + + It is assumed that (possibly signed) size_t bit values suffice to + represent chunk sizes. `Possibly signed' is due to the fact + that `size_t' may be defined on a system as either a signed or + an unsigned type. To be conservative, values that would appear + as negative numbers are avoided. + Requests for sizes with a negative sign bit when the request + size is treaded as a long will return null. + + Maximum overhead wastage per allocated chunk: normally 15 bytes + + Alignnment demands, plus the minimum allocatable size restriction + make the normal worst-case wastage 15 bytes (i.e., up to 15 + more bytes will be allocated than were requested in malloc), with + two exceptions: + 1. Because requests for zero bytes allocate non-zero space, + the worst case wastage for a request of zero bytes is 24 bytes. + 2. For requests >= mmap_threshold that are serviced via + mmap(), the worst case wastage is 8 bytes plus the remainder + from a system page (the minimal mmap unit); typically 4096 bytes. + +* Limitations + + Here are some features that are NOT currently supported + + * No user-definable hooks for callbacks and the like. + * No automated mechanism for fully checking that all accesses + to malloced memory stay within their bounds. + * No support for compaction. + +* Synopsis of compile-time options: + + People have reported using previous versions of this malloc on all + versions of Unix, sometimes by tweaking some of the defines + below. It has been tested most extensively on Solaris and + Linux. It is also reported to work on WIN32 platforms. + People have also reported adapting this malloc for use in + stand-alone embedded systems. + + The implementation is in straight, hand-tuned ANSI C. Among other + consequences, it uses a lot of macros. Because of this, to be at + all usable, this code should be compiled using an optimizing compiler + (for example gcc -O2) that can simplify expressions and control + paths. + + __STD_C (default: derived from C compiler defines) + Nonzero if using ANSI-standard C compiler, a C++ compiler, or + a C compiler sufficiently close to ANSI to get away with it. + DEBUG (default: NOT defined) + Define to enable debugging. Adds fairly extensive assertion-based + checking to help track down memory errors, but noticeably slows down + execution. + REALLOC_ZERO_BYTES_FREES (default: NOT defined) + Define this if you think that realloc(p, 0) should be equivalent + to free(p). Otherwise, since malloc returns a unique pointer for + malloc(0), so does realloc(p, 0). + HAVE_MEMCPY (default: defined) + Define if you are not otherwise using ANSI STD C, but still + have memcpy and memset in your C library and want to use them. + Otherwise, simple internal versions are supplied. + USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise) + Define as 1 if you want the C library versions of memset and + memcpy called in realloc and calloc (otherwise macro versions are used). + At least on some platforms, the simple macro versions usually + outperform libc versions. + HAVE_MMAP (default: defined as 1) + Define to non-zero to optionally make malloc() use mmap() to + allocate very large blocks. + HAVE_MREMAP (default: defined as 0 unless Linux libc set) + Define to non-zero to optionally make realloc() use mremap() to + reallocate very large blocks. + malloc_getpagesize (default: derived from system #includes) + Either a constant or routine call returning the system page size. + HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined) + Optionally define if you are on a system with a /usr/include/malloc.h + that declares struct mallinfo. It is not at all necessary to + define this even if you do, but will ensure consistency. + INTERNAL_SIZE_T (default: size_t) + Define to a 32-bit type (probably `unsigned int') if you are on a + 64-bit machine, yet do not want or need to allow malloc requests of + greater than 2^31 to be handled. This saves space, especially for + very small chunks. + INTERNAL_LINUX_C_LIB (default: NOT defined) + Defined only when compiled as part of Linux libc. + Also note that there is some odd internal name-mangling via defines + (for example, internally, `malloc' is named `mALLOc') needed + when compiling in this case. These look funny but don't otherwise + affect anything. + WIN32 (default: undefined) + Define this on MS win (95, nt) platforms to compile in sbrk emulation. + LACKS_UNISTD_H (default: undefined if not WIN32) + Define this if your system does not have a . + LACKS_SYS_PARAM_H (default: undefined if not WIN32) + Define this if your system does not have a . + MORECORE (default: sbrk) + The name of the routine to call to obtain more memory from the system. + MORECORE_FAILURE (default: -1) + The value returned upon failure of MORECORE. + MORECORE_CLEARS (default 1) + True (1) if the routine mapped to MORECORE zeroes out memory (which + holds for sbrk). + DEFAULT_TRIM_THRESHOLD + DEFAULT_TOP_PAD + DEFAULT_MMAP_THRESHOLD + DEFAULT_MMAP_MAX + Default values of tunable parameters (described in detail below) + controlling interaction with host system routines (sbrk, mmap, etc). + These values may also be changed dynamically via mallopt(). The + preset defaults are those that give best performance for typical + programs/systems. + USE_DL_PREFIX (default: undefined) + Prefix all public routines with the string 'dl'. Useful to + quickly avoid procedure declaration conflicts and linker symbol + conflicts with existing memory allocation routines. + + +*/ + + + + +/* Preliminaries */ + +#ifndef __STD_C +#ifdef __STDC__ +#define __STD_C 1 +#else +#if __cplusplus +#define __STD_C 1 +#else +#define __STD_C 0 +#endif /*__cplusplus*/ +#endif /*__STDC__*/ +#endif /*__STD_C*/ + +#ifndef Void_t +#if (__STD_C || defined(WIN32)) +#define Void_t void +#else +#define Void_t char +#endif +#endif /*Void_t*/ + +#if __STD_C +#include /* for size_t */ +#else +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include /* needed for malloc_stats */ + + +/* + Compile-time options +*/ + + +/* + Debugging: + + Because freed chunks may be overwritten with link fields, this + malloc will often die when freed memory is overwritten by user + programs. This can be very effective (albeit in an annoying way) + in helping track down dangling pointers. + + If you compile with -DDEBUG, a number of assertion checks are + enabled that will catch more memory errors. You probably won't be + able to make much sense of the actual assertion errors, but they + should help you locate incorrectly overwritten memory. The + checking is fairly extensive, and will slow down execution + noticeably. Calling malloc_stats or mallinfo with DEBUG set will + attempt to check every non-mmapped allocated and free chunk in the + course of computing the summmaries. (By nature, mmapped regions + cannot be checked very much automatically.) + + Setting DEBUG may also be helpful if you are trying to modify + this code. The assertions in the check routines spell out in more + detail the assumptions and invariants underlying the algorithms. + +*/ + +#if DEBUG +#include +#else +#define assert(x) ((void)0) +#endif + + +/* + INTERNAL_SIZE_T is the word-size used for internal bookkeeping + of chunk sizes. On a 64-bit machine, you can reduce malloc + overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' + at the expense of not being able to handle requests greater than + 2^31. This limitation is hardly ever a concern; you are encouraged + to set this. However, the default version is the same as size_t. +*/ + +#ifndef INTERNAL_SIZE_T +#define INTERNAL_SIZE_T size_t +#endif + +/* + REALLOC_ZERO_BYTES_FREES should be set if a call to + realloc with zero bytes should be the same as a call to free. + Some people think it should. Otherwise, since this malloc + returns a unique pointer for malloc(0), so does realloc(p, 0). +*/ + + +/* #define REALLOC_ZERO_BYTES_FREES */ + + +/* + WIN32 causes an emulation of sbrk to be compiled in + mmap-based options are not currently supported in WIN32. +*/ + +/* #define WIN32 */ +#ifdef WIN32 +#define MORECORE wsbrk +#define HAVE_MMAP 0 + +#define LACKS_UNISTD_H +#define LACKS_SYS_PARAM_H + +/* + Include 'windows.h' to get the necessary declarations for the + Microsoft Visual C++ data structures and routines used in the 'sbrk' + emulation. + + Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft + Visual C++ header files are included. +*/ +#define WIN32_LEAN_AND_MEAN +#include +#endif + + +/* + HAVE_MEMCPY should be defined if you are not otherwise using + ANSI STD C, but still have memcpy and memset in your C library + and want to use them in calloc and realloc. Otherwise simple + macro versions are defined here. + + USE_MEMCPY should be defined as 1 if you actually want to + have memset and memcpy called. People report that the macro + versions are often enough faster than libc versions on many + systems that it is better to use them. + +*/ + +#define HAVE_MEMCPY + +#ifndef USE_MEMCPY +#ifdef HAVE_MEMCPY +#define USE_MEMCPY 1 +#else +#define USE_MEMCPY 0 +#endif +#endif + +#if (__STD_C || defined(HAVE_MEMCPY)) + +#if __STD_C +void* memset(void*, int, size_t); +void* memcpy(void*, const void*, size_t); +#else +#ifdef WIN32 +/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */ +/* 'windows.h' */ +#else +Void_t* memset(); +Void_t* memcpy(); +#endif +#endif +#endif + +#if USE_MEMCPY + +/* The following macros are only invoked with (2n+1)-multiples of + INTERNAL_SIZE_T units, with a positive integer n. This is exploited + for fast inline execution when n is small. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T mzsz = (nbytes); \ + if(mzsz <= 9*sizeof(mzsz)) { \ + INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \ + if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; }}} \ + *mz++ = 0; \ + *mz++ = 0; \ + *mz = 0; \ + } else memset((charp), 0, mzsz); \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T mcsz = (nbytes); \ + if(mcsz <= 9*sizeof(mcsz)) { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \ + if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; }}} \ + *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + *mcdst = *mcsrc ; \ + } else memcpy(dest, src, mcsz); \ +} while(0) + +#else /* !USE_MEMCPY */ + +/* Use Duff's device for good zeroing/copying performance. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mzp++ = 0; \ + case 7: *mzp++ = 0; \ + case 6: *mzp++ = 0; \ + case 5: *mzp++ = 0; \ + case 4: *mzp++ = 0; \ + case 3: *mzp++ = 0; \ + case 2: *mzp++ = 0; \ + case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mcdst++ = *mcsrc++; \ + case 7: *mcdst++ = *mcsrc++; \ + case 6: *mcdst++ = *mcsrc++; \ + case 5: *mcdst++ = *mcsrc++; \ + case 4: *mcdst++ = *mcsrc++; \ + case 3: *mcdst++ = *mcsrc++; \ + case 2: *mcdst++ = *mcsrc++; \ + case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#endif + + +/* + Define HAVE_MMAP to optionally make malloc() use mmap() to + allocate very large blocks. These will be returned to the + operating system immediately after a free(). +*/ + +#ifndef HAVE_MMAP +#define HAVE_MMAP 1 +#endif + +/* + Define HAVE_MREMAP to make realloc() use mremap() to re-allocate + large blocks. This is currently only possible on Linux with + kernel versions newer than 1.3.77. +*/ + +#ifndef HAVE_MREMAP +#ifdef INTERNAL_LINUX_C_LIB +#define HAVE_MREMAP 1 +#else +#define HAVE_MREMAP 0 +#endif +#endif + +#if HAVE_MMAP + +#include +#include +#include + +#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON) +#define MAP_ANONYMOUS MAP_ANON +#endif + +#endif /* HAVE_MMAP */ + +/* + Access to system page size. To the extent possible, this malloc + manages memory from the system in page-size units. + + The following mechanics for getpagesize were adapted from + bsd/gnu getpagesize.h +*/ + +#ifndef LACKS_UNISTD_H +# include +#endif + +#ifndef malloc_getpagesize +# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */ +# ifndef _SC_PAGE_SIZE +# define _SC_PAGE_SIZE _SC_PAGESIZE +# endif +# endif +# ifdef _SC_PAGE_SIZE +# define malloc_getpagesize sysconf(_SC_PAGE_SIZE) +# else +# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE) + extern size_t getpagesize(); +# define malloc_getpagesize getpagesize() +# else +# ifdef WIN32 +# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */ +# else +# ifndef LACKS_SYS_PARAM_H +# include +# endif +# ifdef EXEC_PAGESIZE +# define malloc_getpagesize EXEC_PAGESIZE +# else +# ifdef NBPG +# ifndef CLSIZE +# define malloc_getpagesize NBPG +# else +# define malloc_getpagesize (NBPG * CLSIZE) +# endif +# else +# ifdef NBPC +# define malloc_getpagesize NBPC +# else +# ifdef PAGESIZE +# define malloc_getpagesize PAGESIZE +# else +# define malloc_getpagesize (4096) /* just guess */ +# endif +# endif +# endif +# endif +# endif +# endif +# endif +#endif + + +/* + + This version of malloc supports the standard SVID/XPG mallinfo + routine that returns a struct containing the same kind of + information you can get from malloc_stats. It should work on + any SVID/XPG compliant system that has a /usr/include/malloc.h + defining struct mallinfo. (If you'd like to install such a thing + yourself, cut out the preliminary declarations as described above + and below and save them in a malloc.h file. But there's no + compelling reason to bother to do this.) + + The main declaration needed is the mallinfo struct that is returned + (by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a + bunch of fields, most of which are not even meaningful in this + version of malloc. Some of these fields are are instead filled by + mallinfo() with other numbers that might possibly be of interest. + + HAVE_USR_INCLUDE_MALLOC_H should be set if you have a + /usr/include/malloc.h file that includes a declaration of struct + mallinfo. If so, it is included; else an SVID2/XPG2 compliant + version is declared below. These must be precisely the same for + mallinfo() to work. + +*/ + +/* #define HAVE_USR_INCLUDE_MALLOC_H */ + +#if HAVE_USR_INCLUDE_MALLOC_H +#include "/usr/include/malloc.h" +#else + +/* SVID2/XPG mallinfo structure */ + +struct mallinfo { + int arena; /* total space allocated from system */ + int ordblks; /* number of non-inuse chunks */ + int smblks; /* unused -- always zero */ + int hblks; /* number of mmapped regions */ + int hblkhd; /* total space in mmapped regions */ + int usmblks; /* unused -- always zero */ + int fsmblks; /* unused -- always zero */ + int uordblks; /* total allocated space */ + int fordblks; /* total non-inuse space */ + int keepcost; /* top-most, releasable (via malloc_trim) space */ +}; + +/* SVID2/XPG mallopt options */ + +#define M_MXFAST 1 /* UNUSED in this malloc */ +#define M_NLBLKS 2 /* UNUSED in this malloc */ +#define M_GRAIN 3 /* UNUSED in this malloc */ +#define M_KEEP 4 /* UNUSED in this malloc */ + +#endif + +/* mallopt options that actually do something */ + +#define M_TRIM_THRESHOLD -1 +#define M_TOP_PAD -2 +#define M_MMAP_THRESHOLD -3 +#define M_MMAP_MAX -4 + + +#ifndef DEFAULT_TRIM_THRESHOLD +#define DEFAULT_TRIM_THRESHOLD (128 * 1024) +#endif + +/* + M_TRIM_THRESHOLD is the maximum amount of unused top-most memory + to keep before releasing via malloc_trim in free(). + + Automatic trimming is mainly useful in long-lived programs. + Because trimming via sbrk can be slow on some systems, and can + sometimes be wasteful (in cases where programs immediately + afterward allocate more large chunks) the value should be high + enough so that your overall system performance would improve by + releasing. + + The trim threshold and the mmap control parameters (see below) + can be traded off with one another. Trimming and mmapping are + two different ways of releasing unused memory back to the + system. Between these two, it is often possible to keep + system-level demands of a long-lived program down to a bare + minimum. For example, in one test suite of sessions measuring + the XF86 X server on Linux, using a trim threshold of 128K and a + mmap threshold of 192K led to near-minimal long term resource + consumption. + + If you are using this malloc in a long-lived program, it should + pay to experiment with these values. As a rough guide, you + might set to a value close to the average size of a process + (program) running on your system. Releasing this much memory + would allow such a process to run in memory. Generally, it's + worth it to tune for trimming rather tham memory mapping when a + program undergoes phases where several large chunks are + allocated and released in ways that can reuse each other's + storage, perhaps mixed with phases where there are no such + chunks at all. And in well-behaved long-lived programs, + controlling release of large blocks via trimming versus mapping + is usually faster. + + However, in most programs, these parameters serve mainly as + protection against the system-level effects of carrying around + massive amounts of unneeded memory. Since frequent calls to + sbrk, mmap, and munmap otherwise degrade performance, the default + parameters are set to relatively high values that serve only as + safeguards. + + The default trim value is high enough to cause trimming only in + fairly extreme (by current memory consumption standards) cases. + It must be greater than page size to have any useful effect. To + disable trimming completely, you can set to (unsigned long)(-1); + + +*/ + + +#ifndef DEFAULT_TOP_PAD +#define DEFAULT_TOP_PAD (0) +#endif + +/* + M_TOP_PAD is the amount of extra `padding' space to allocate or + retain whenever sbrk is called. It is used in two ways internally: + + * When sbrk is called to extend the top of the arena to satisfy + a new malloc request, this much padding is added to the sbrk + request. + + * When malloc_trim is called automatically from free(), + it is used as the `pad' argument. + + In both cases, the actual amount of padding is rounded + so that the end of the arena is always a system page boundary. + + The main reason for using padding is to avoid calling sbrk so + often. Having even a small pad greatly reduces the likelihood + that nearly every malloc request during program start-up (or + after trimming) will invoke sbrk, which needlessly wastes + time. + + Automatic rounding-up to page-size units is normally sufficient + to avoid measurable overhead, so the default is 0. However, in + systems where sbrk is relatively slow, it can pay to increase + this value, at the expense of carrying around more memory than + the program needs. + +*/ + + +#ifndef DEFAULT_MMAP_THRESHOLD +#define DEFAULT_MMAP_THRESHOLD (128 * 1024) +#endif + +/* + + M_MMAP_THRESHOLD is the request size threshold for using mmap() + to service a request. Requests of at least this size that cannot + be allocated using already-existing space will be serviced via mmap. + (If enough normal freed space already exists it is used instead.) + + Using mmap segregates relatively large chunks of memory so that + they can be individually obtained and released from the host + system. A request serviced through mmap is never reused by any + other request (at least not directly; the system may just so + happen to remap successive requests to the same locations). + + Segregating space in this way has the benefit that mmapped space + can ALWAYS be individually released back to the system, which + helps keep the system level memory demands of a long-lived + program low. Mapped memory can never become `locked' between + other chunks, as can happen with normally allocated chunks, which + menas that even trimming via malloc_trim would not release them. + + However, it has the disadvantages that: + + 1. The space cannot be reclaimed, consolidated, and then + used to service later requests, as happens with normal chunks. + 2. It can lead to more wastage because of mmap page alignment + requirements + 3. It causes malloc performance to be more dependent on host + system memory management support routines which may vary in + implementation quality and may impose arbitrary + limitations. Generally, servicing a request via normal + malloc steps is faster than going through a system's mmap. + + All together, these considerations should lead you to use mmap + only for relatively large requests. + + +*/ + + +#ifndef DEFAULT_MMAP_MAX +#if HAVE_MMAP +#define DEFAULT_MMAP_MAX (64) +#else +#define DEFAULT_MMAP_MAX (0) +#endif +#endif + +/* + M_MMAP_MAX is the maximum number of requests to simultaneously + service using mmap. This parameter exists because: + + 1. Some systems have a limited number of internal tables for + use by mmap. + 2. In most systems, overreliance on mmap can degrade overall + performance. + 3. If a program allocates many large regions, it is probably + better off using normal sbrk-based allocation routines that + can reclaim and reallocate normal heap memory. Using a + small value allows transition into this mode after the + first few allocations. + + Setting to 0 disables all use of mmap. If HAVE_MMAP is not set, + the default value is 0, and attempts to set it to non-zero values + in mallopt will fail. +*/ + + +/* + USE_DL_PREFIX will prefix all public routines with the string 'dl'. + Useful to quickly avoid procedure declaration conflicts and linker + symbol conflicts with existing memory allocation routines. + +*/ + +/* #define USE_DL_PREFIX */ + + +/* + + Special defines for linux libc + + Except when compiled using these special defines for Linux libc + using weak aliases, this malloc is NOT designed to work in + multithreaded applications. No semaphores or other concurrency + control are provided to ensure that multiple malloc or free calls + don't run at the same time, which could be disasterous. A single + semaphore could be used across malloc, realloc, and free (which is + essentially the effect of the linux weak alias approach). It would + be hard to obtain finer granularity. + +*/ + + +#ifdef INTERNAL_LINUX_C_LIB + +#if __STD_C + +Void_t * __default_morecore_init (ptrdiff_t); +Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init; + +#else + +Void_t * __default_morecore_init (); +Void_t *(*__morecore)() = __default_morecore_init; + +#endif + +#define MORECORE (*__morecore) +#define MORECORE_FAILURE 0 +#define MORECORE_CLEARS 1 + +#else /* INTERNAL_LINUX_C_LIB */ + +#if __STD_C +extern Void_t* sbrk(ptrdiff_t); +#else +extern Void_t* sbrk(); +#endif + +#ifndef MORECORE +#define MORECORE sbrk +#endif + +#ifndef MORECORE_FAILURE +#define MORECORE_FAILURE -1 +#endif + +#ifndef MORECORE_CLEARS +#define MORECORE_CLEARS 1 +#endif + +#endif /* INTERNAL_LINUX_C_LIB */ + +#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__) + +#define cALLOc __libc_calloc +#define fREe __libc_free +#define mALLOc __libc_malloc +#define mEMALIGn __libc_memalign +#define rEALLOc __libc_realloc +#define vALLOc __libc_valloc +#define pvALLOc __libc_pvalloc +#define mALLINFo __libc_mallinfo +#define mALLOPt __libc_mallopt + +#pragma weak calloc = __libc_calloc +#pragma weak free = __libc_free +#pragma weak cfree = __libc_free +#pragma weak malloc = __libc_malloc +#pragma weak memalign = __libc_memalign +#pragma weak realloc = __libc_realloc +#pragma weak valloc = __libc_valloc +#pragma weak pvalloc = __libc_pvalloc +#pragma weak mallinfo = __libc_mallinfo +#pragma weak mallopt = __libc_mallopt + +#else + +#ifdef USE_DL_PREFIX +#define cALLOc dlcalloc +#define fREe dlfree +#define mALLOc dlmalloc +#define mEMALIGn dlmemalign +#define rEALLOc dlrealloc +#define vALLOc dlvalloc +#define pvALLOc dlpvalloc +#define mALLINFo dlmallinfo +#define mALLOPt dlmallopt +#else /* USE_DL_PREFIX */ +#define cALLOc calloc +#define fREe free +#define mALLOc malloc +#define mEMALIGn memalign +#define rEALLOc realloc +#define vALLOc valloc +#define pvALLOc pvalloc +#define mALLINFo mallinfo +#define mALLOPt mallopt +#endif /* USE_DL_PREFIX */ + +#endif + +/* Public routines */ + +#if __STD_C + +Void_t* mALLOc(size_t); +void fREe(Void_t*); +Void_t* rEALLOc(Void_t*, size_t); +Void_t* mEMALIGn(size_t, size_t); +Void_t* vALLOc(size_t); +Void_t* pvALLOc(size_t); +Void_t* cALLOc(size_t, size_t); +void cfree(Void_t*); +int malloc_trim(size_t); +size_t malloc_usable_size(Void_t*); +void malloc_stats(); +int mALLOPt(int, int); +struct mallinfo mALLINFo(void); +#else +Void_t* mALLOc(); +void fREe(); +Void_t* rEALLOc(); +Void_t* mEMALIGn(); +Void_t* vALLOc(); +Void_t* pvALLOc(); +Void_t* cALLOc(); +void cfree(); +int malloc_trim(); +size_t malloc_usable_size(); +void malloc_stats(); +int mALLOPt(); +struct mallinfo mALLINFo(); +#endif + + +#ifdef __cplusplus +}; /* end of extern "C" */ +#endif + +/* ---------- To make a malloc.h, end cutting here ------------ */ + + +/* + Emulation of sbrk for WIN32 + All code within the ifdef WIN32 is untested by me. + + Thanks to Martin Fong and others for supplying this. +*/ + + +#ifdef WIN32 + +#define AlignPage(add) (((add) + (malloc_getpagesize-1)) & \ +~(malloc_getpagesize-1)) +#define AlignPage64K(add) (((add) + (0x10000 - 1)) & ~(0x10000 - 1)) + +/* resrve 64MB to insure large contiguous space */ +#define RESERVED_SIZE (1024*1024*64) +#define NEXT_SIZE (2048*1024) +#define TOP_MEMORY ((unsigned long)2*1024*1024*1024) + +struct GmListElement; +typedef struct GmListElement GmListElement; + +struct GmListElement +{ + GmListElement* next; + void* base; +}; + +static GmListElement* head = 0; +static unsigned int gNextAddress = 0; +static unsigned int gAddressBase = 0; +static unsigned int gAllocatedSize = 0; + +static +GmListElement* makeGmListElement (void* bas) +{ + GmListElement* this; + this = (GmListElement*)(void*)LocalAlloc (0, sizeof (GmListElement)); + assert (this); + if (this) + { + this->base = bas; + this->next = head; + head = this; + } + return this; +} + +void gcleanup () +{ + BOOL rval; + assert ( (head == NULL) || (head->base == (void*)gAddressBase)); + if (gAddressBase && (gNextAddress - gAddressBase)) + { + rval = VirtualFree ((void*)gAddressBase, + gNextAddress - gAddressBase, + MEM_DECOMMIT); + assert (rval); + } + while (head) + { + GmListElement* next = head->next; + rval = VirtualFree (head->base, 0, MEM_RELEASE); + assert (rval); + LocalFree (head); + head = next; + } +} + +static +void* findRegion (void* start_address, unsigned long size) +{ + MEMORY_BASIC_INFORMATION info; + if (size >= TOP_MEMORY) return NULL; + + while ((unsigned long)start_address + size < TOP_MEMORY) + { + VirtualQuery (start_address, &info, sizeof (info)); + if ((info.State == MEM_FREE) && (info.RegionSize >= size)) + return start_address; + else + { + /* Requested region is not available so see if the */ + /* next region is available. Set 'start_address' */ + /* to the next region and call 'VirtualQuery()' */ + /* again. */ + + start_address = (char*)info.BaseAddress + info.RegionSize; + + /* Make sure we start looking for the next region */ + /* on the *next* 64K boundary. Otherwise, even if */ + /* the new region is free according to */ + /* 'VirtualQuery()', the subsequent call to */ + /* 'VirtualAlloc()' (which follows the call to */ + /* this routine in 'wsbrk()') will round *down* */ + /* the requested address to a 64K boundary which */ + /* we already know is an address in the */ + /* unavailable region. Thus, the subsequent call */ + /* to 'VirtualAlloc()' will fail and bring us back */ + /* here, causing us to go into an infinite loop. */ + + start_address = + (void *) AlignPage64K((unsigned long) start_address); + } + } + return NULL; + +} + + +void* wsbrk (long size) +{ + void* tmp; + if (size > 0) + { + if (gAddressBase == 0) + { + gAllocatedSize = max (RESERVED_SIZE, AlignPage (size)); + gNextAddress = gAddressBase = + (unsigned int)VirtualAlloc (NULL, gAllocatedSize, + MEM_RESERVE, PAGE_NOACCESS); + } else if (AlignPage (gNextAddress + size) > (gAddressBase + +gAllocatedSize)) + { + long new_size = max (NEXT_SIZE, AlignPage (size)); + void* new_address = (void*)(gAddressBase+gAllocatedSize); + do + { + new_address = findRegion (new_address, new_size); + + if (new_address == 0) + return (void*)-1; + + gAddressBase = gNextAddress = + (unsigned int)VirtualAlloc (new_address, new_size, + MEM_RESERVE, PAGE_NOACCESS); + /* repeat in case of race condition */ + /* The region that we found has been snagged */ + /* by another thread */ + } + while (gAddressBase == 0); + + assert (new_address == (void*)gAddressBase); + + gAllocatedSize = new_size; + + if (!makeGmListElement ((void*)gAddressBase)) + return (void*)-1; + } + if ((size + gNextAddress) > AlignPage (gNextAddress)) + { + void* res; + res = VirtualAlloc ((void*)AlignPage (gNextAddress), + (size + gNextAddress - + AlignPage (gNextAddress)), + MEM_COMMIT, PAGE_READWRITE); + if (res == 0) + return (void*)-1; + } + tmp = (void*)gNextAddress; + gNextAddress = (unsigned int)tmp + size; + return tmp; + } + else if (size < 0) + { + unsigned int alignedGoal = AlignPage (gNextAddress + size); + /* Trim by releasing the virtual memory */ + if (alignedGoal >= gAddressBase) + { + VirtualFree ((void*)alignedGoal, gNextAddress - alignedGoal, + MEM_DECOMMIT); + gNextAddress = gNextAddress + size; + return (void*)gNextAddress; + } + else + { + VirtualFree ((void*)gAddressBase, gNextAddress - gAddressBase, + MEM_DECOMMIT); + gNextAddress = gAddressBase; + return (void*)-1; + } + } + else + { + return (void*)gNextAddress; + } +} + +#endif + + + +/* + Type declarations +*/ + + +struct malloc_chunk +{ + INTERNAL_SIZE_T prev_size; /* Size of previous chunk (if free). */ + INTERNAL_SIZE_T size; /* Size in bytes, including overhead. */ + struct malloc_chunk* fd; /* double links -- used only if free. */ + struct malloc_chunk* bk; +}; + +typedef struct malloc_chunk* mchunkptr; + +/* + + malloc_chunk details: + + (The following includes lightly edited explanations by Colin Plumb.) + + Chunks of memory are maintained using a `boundary tag' method as + described in e.g., Knuth or Standish. (See the paper by Paul + Wilson ftp://ftp.cs.utexas.edu/pub/garbage/allocsrv.ps for a + survey of such techniques.) Sizes of free chunks are stored both + in the front of each chunk and at the end. This makes + consolidating fragmented chunks into bigger chunks very fast. The + size fields also hold bits representing whether chunks are free or + in use. + + An allocated chunk looks like this: + + + chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of previous chunk, if allocated | | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of chunk, in bytes |P| + mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | User data starts here... . + . . + . (malloc_usable_space() bytes) . + . | +nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of chunk | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + + Where "chunk" is the front of the chunk for the purpose of most of + the malloc code, but "mem" is the pointer that is returned to the + user. "Nextchunk" is the beginning of the next contiguous chunk. + + Chunks always begin on even word boundries, so the mem portion + (which is returned to the user) is also on an even word boundary, and + thus double-word aligned. + + Free chunks are stored in circular doubly-linked lists, and look like this: + + chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of previous chunk | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + `head:' | Size of chunk, in bytes |P| + mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Forward pointer to next chunk in list | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Back pointer to previous chunk in list | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Unused space (may be 0 bytes long) . + . . + . | +nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + `foot:' | Size of chunk, in bytes | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + The P (PREV_INUSE) bit, stored in the unused low-order bit of the + chunk size (which is always a multiple of two words), is an in-use + bit for the *previous* chunk. If that bit is *clear*, then the + word before the current chunk size contains the previous chunk + size, and can be used to find the front of the previous chunk. + (The very first chunk allocated always has this bit set, + preventing access to non-existent (or non-owned) memory.) + + Note that the `foot' of the current chunk is actually represented + as the prev_size of the NEXT chunk. (This makes it easier to + deal with alignments etc). + + The two exceptions to all this are + + 1. The special chunk `top', which doesn't bother using the + trailing size field since there is no + next contiguous chunk that would have to index off it. (After + initialization, `top' is forced to always exist. If it would + become less than MINSIZE bytes long, it is replenished via + malloc_extend_top.) + + 2. Chunks allocated via mmap, which have the second-lowest-order + bit (IS_MMAPPED) set in their size fields. Because they are + never merged or traversed from any other chunk, they have no + foot size or inuse information. + + Available chunks are kept in any of several places (all declared below): + + * `av': An array of chunks serving as bin headers for consolidated + chunks. Each bin is doubly linked. The bins are approximately + proportionally (log) spaced. There are a lot of these bins + (128). This may look excessive, but works very well in + practice. All procedures maintain the invariant that no + consolidated chunk physically borders another one. Chunks in + bins are kept in size order, with ties going to the + approximately least recently used chunk. + + The chunks in each bin are maintained in decreasing sorted order by + size. This is irrelevant for the small bins, which all contain + the same-sized chunks, but facilitates best-fit allocation for + larger chunks. (These lists are just sequential. Keeping them in + order almost never requires enough traversal to warrant using + fancier ordered data structures.) Chunks of the same size are + linked with the most recently freed at the front, and allocations + are taken from the back. This results in LRU or FIFO allocation + order, which tends to give each chunk an equal opportunity to be + consolidated with adjacent freed chunks, resulting in larger free + chunks and less fragmentation. + + * `top': The top-most available chunk (i.e., the one bordering the + end of available memory) is treated specially. It is never + included in any bin, is used only if no other chunk is + available, and is released back to the system if it is very + large (see M_TRIM_THRESHOLD). + + * `last_remainder': A bin holding only the remainder of the + most recently split (non-top) chunk. This bin is checked + before other non-fitting chunks, so as to provide better + locality for runs of sequentially allocated chunks. + + * Implicitly, through the host system's memory mapping tables. + If supported, requests greater than a threshold are usually + serviced via calls to mmap, and then later released via munmap. + +*/ + + + + + +/* sizes, alignments */ + +#define SIZE_SZ (sizeof(INTERNAL_SIZE_T)) +#define MALLOC_ALIGNMENT (SIZE_SZ + SIZE_SZ) +#define MALLOC_ALIGN_MASK (MALLOC_ALIGNMENT - 1) +#define MINSIZE (sizeof(struct malloc_chunk)) + +/* conversion from malloc headers to user pointers, and back */ + +#define chunk2mem(p) ((Void_t*)((char*)(p) + 2*SIZE_SZ)) +#define mem2chunk(mem) ((mchunkptr)((char*)(mem) - 2*SIZE_SZ)) + +/* pad request bytes into a usable size */ + +#define request2size(req) \ + (((long)((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) < \ + (long)(MINSIZE + MALLOC_ALIGN_MASK)) ? MINSIZE : \ + (((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) & ~(MALLOC_ALIGN_MASK))) + +/* Check if m has acceptable alignment */ + +#define aligned_OK(m) (((unsigned long)((m)) & (MALLOC_ALIGN_MASK)) == 0) + + + + +/* + Physical chunk operations +*/ + + +/* size field is or'ed with PREV_INUSE when previous adjacent chunk in use */ + +#define PREV_INUSE 0x1 + +/* size field is or'ed with IS_MMAPPED if the chunk was obtained with mmap() */ + +#define IS_MMAPPED 0x2 + +/* Bits to mask off when extracting size */ + +#define SIZE_BITS (PREV_INUSE|IS_MMAPPED) + + +/* Ptr to next physical malloc_chunk. */ + +#define next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~PREV_INUSE) )) + +/* Ptr to previous physical malloc_chunk */ + +#define prev_chunk(p)\ + ((mchunkptr)( ((char*)(p)) - ((p)->prev_size) )) + + +/* Treat space at ptr + offset as a chunk */ + +#define chunk_at_offset(p, s) ((mchunkptr)(((char*)(p)) + (s))) + + + + +/* + Dealing with use bits +*/ + +/* extract p's inuse bit */ + +#define inuse(p)\ +((((mchunkptr)(((char*)(p))+((p)->size & ~PREV_INUSE)))->size) & PREV_INUSE) + +/* extract inuse bit of previous chunk */ + +#define prev_inuse(p) ((p)->size & PREV_INUSE) + +/* check for mmap()'ed chunk */ + +#define chunk_is_mmapped(p) ((p)->size & IS_MMAPPED) + +/* set/clear chunk as in use without otherwise disturbing */ + +#define set_inuse(p)\ +((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size |= PREV_INUSE + +#define clear_inuse(p)\ +((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size &= ~(PREV_INUSE) + +/* check/set/clear inuse bits in known places */ + +#define inuse_bit_at_offset(p, s)\ + (((mchunkptr)(((char*)(p)) + (s)))->size & PREV_INUSE) + +#define set_inuse_bit_at_offset(p, s)\ + (((mchunkptr)(((char*)(p)) + (s)))->size |= PREV_INUSE) + +#define clear_inuse_bit_at_offset(p, s)\ + (((mchunkptr)(((char*)(p)) + (s)))->size &= ~(PREV_INUSE)) + + + + +/* + Dealing with size fields +*/ + +/* Get size, ignoring use bits */ + +#define chunksize(p) ((p)->size & ~(SIZE_BITS)) + +/* Set size at head, without disturbing its use bit */ + +#define set_head_size(p, s) ((p)->size = (((p)->size & PREV_INUSE) | (s))) + +/* Set size/use ignoring previous bits in header */ + +#define set_head(p, s) ((p)->size = (s)) + +/* Set size at footer (only when chunk is not in use) */ + +#define set_foot(p, s) (((mchunkptr)((char*)(p) + (s)))->prev_size = (s)) + + + + + +/* + Bins + + The bins, `av_' are an array of pairs of pointers serving as the + heads of (initially empty) doubly-linked lists of chunks, laid out + in a way so that each pair can be treated as if it were in a + malloc_chunk. (This way, the fd/bk offsets for linking bin heads + and chunks are the same). + + Bins for sizes < 512 bytes contain chunks of all the same size, spaced + 8 bytes apart. Larger bins are approximately logarithmically + spaced. (See the table below.) The `av_' array is never mentioned + directly in the code, but instead via bin access macros. + + Bin layout: + + 64 bins of size 8 + 32 bins of size 64 + 16 bins of size 512 + 8 bins of size 4096 + 4 bins of size 32768 + 2 bins of size 262144 + 1 bin of size what's left + + There is actually a little bit of slop in the numbers in bin_index + for the sake of speed. This makes no difference elsewhere. + + The special chunks `top' and `last_remainder' get their own bins, + (this is implemented via yet more trickery with the av_ array), + although `top' is never properly linked to its bin since it is + always handled specially. + +*/ + +#define NAV 128 /* number of bins */ + +typedef struct malloc_chunk* mbinptr; + +/* access macros */ + +#define bin_at(i) ((mbinptr)((char*)&(av_[2*(i) + 2]) - 2*SIZE_SZ)) +#define next_bin(b) ((mbinptr)((char*)(b) + 2 * sizeof(mbinptr))) +#define prev_bin(b) ((mbinptr)((char*)(b) - 2 * sizeof(mbinptr))) + +/* + The first 2 bins are never indexed. The corresponding av_ cells are instead + used for bookkeeping. This is not to save space, but to simplify + indexing, maintain locality, and avoid some initialization tests. +*/ + +#define top (bin_at(0)->fd) /* The topmost chunk */ +#define last_remainder (bin_at(1)) /* remainder from last split */ + + +/* + Because top initially points to its own bin with initial + zero size, thus forcing extension on the first malloc request, + we avoid having any special code in malloc to check whether + it even exists yet. But we still need to in malloc_extend_top. +*/ + +#define initial_top ((mchunkptr)(bin_at(0))) + +/* Helper macro to initialize bins */ + +#define IAV(i) bin_at(i), bin_at(i) + +static mbinptr av_[NAV * 2 + 2] = { + 0, 0, + IAV(0), IAV(1), IAV(2), IAV(3), IAV(4), IAV(5), IAV(6), IAV(7), + IAV(8), IAV(9), IAV(10), IAV(11), IAV(12), IAV(13), IAV(14), IAV(15), + IAV(16), IAV(17), IAV(18), IAV(19), IAV(20), IAV(21), IAV(22), IAV(23), + IAV(24), IAV(25), IAV(26), IAV(27), IAV(28), IAV(29), IAV(30), IAV(31), + IAV(32), IAV(33), IAV(34), IAV(35), IAV(36), IAV(37), IAV(38), IAV(39), + IAV(40), IAV(41), IAV(42), IAV(43), IAV(44), IAV(45), IAV(46), IAV(47), + IAV(48), IAV(49), IAV(50), IAV(51), IAV(52), IAV(53), IAV(54), IAV(55), + IAV(56), IAV(57), IAV(58), IAV(59), IAV(60), IAV(61), IAV(62), IAV(63), + IAV(64), IAV(65), IAV(66), IAV(67), IAV(68), IAV(69), IAV(70), IAV(71), + IAV(72), IAV(73), IAV(74), IAV(75), IAV(76), IAV(77), IAV(78), IAV(79), + IAV(80), IAV(81), IAV(82), IAV(83), IAV(84), IAV(85), IAV(86), IAV(87), + IAV(88), IAV(89), IAV(90), IAV(91), IAV(92), IAV(93), IAV(94), IAV(95), + IAV(96), IAV(97), IAV(98), IAV(99), IAV(100), IAV(101), IAV(102), IAV(103), + IAV(104), IAV(105), IAV(106), IAV(107), IAV(108), IAV(109), IAV(110), IAV(111), + IAV(112), IAV(113), IAV(114), IAV(115), IAV(116), IAV(117), IAV(118), IAV(119), + IAV(120), IAV(121), IAV(122), IAV(123), IAV(124), IAV(125), IAV(126), IAV(127) +}; + + + +/* field-extraction macros */ + +#define first(b) ((b)->fd) +#define last(b) ((b)->bk) + +/* + Indexing into bins +*/ + +#define bin_index(sz) \ +(((((unsigned long)(sz)) >> 9) == 0) ? (((unsigned long)(sz)) >> 3): \ + ((((unsigned long)(sz)) >> 9) <= 4) ? 56 + (((unsigned long)(sz)) >> 6): \ + ((((unsigned long)(sz)) >> 9) <= 20) ? 91 + (((unsigned long)(sz)) >> 9): \ + ((((unsigned long)(sz)) >> 9) <= 84) ? 110 + (((unsigned long)(sz)) >> 12): \ + ((((unsigned long)(sz)) >> 9) <= 340) ? 119 + (((unsigned long)(sz)) >> 15): \ + ((((unsigned long)(sz)) >> 9) <= 1364) ? 124 + (((unsigned long)(sz)) >> 18): \ + 126) +/* + bins for chunks < 512 are all spaced 8 bytes apart, and hold + identically sized chunks. This is exploited in malloc. +*/ + +#define MAX_SMALLBIN 63 +#define MAX_SMALLBIN_SIZE 512 +#define SMALLBIN_WIDTH 8 + +#define smallbin_index(sz) (((unsigned long)(sz)) >> 3) + +/* + Requests are `small' if both the corresponding and the next bin are small +*/ + +#define is_small_request(nb) (nb < MAX_SMALLBIN_SIZE - SMALLBIN_WIDTH) + + + +/* + To help compensate for the large number of bins, a one-level index + structure is used for bin-by-bin searching. `binblocks' is a + one-word bitvector recording whether groups of BINBLOCKWIDTH bins + have any (possibly) non-empty bins, so they can be skipped over + all at once during during traversals. The bits are NOT always + cleared as soon as all bins in a block are empty, but instead only + when all are noticed to be empty during traversal in malloc. +*/ + +#define BINBLOCKWIDTH 4 /* bins per block */ + +#define binblocks (bin_at(0)->size) /* bitvector of nonempty blocks */ + +/* bin<->block macros */ + +#define idx2binblock(ix) ((unsigned)1 << (ix / BINBLOCKWIDTH)) +#define mark_binblock(ii) (binblocks |= idx2binblock(ii)) +#define clear_binblock(ii) (binblocks &= ~(idx2binblock(ii))) + + + + + +/* Other static bookkeeping data */ + +/* variables holding tunable values */ + +static unsigned long trim_threshold = DEFAULT_TRIM_THRESHOLD; +static unsigned long top_pad = DEFAULT_TOP_PAD; +static unsigned int n_mmaps_max = DEFAULT_MMAP_MAX; +static unsigned long mmap_threshold = DEFAULT_MMAP_THRESHOLD; + +/* The first value returned from sbrk */ +static char* sbrk_base = (char*)(-1); + +/* The maximum memory obtained from system via sbrk */ +static unsigned long max_sbrked_mem = 0; + +/* The maximum via either sbrk or mmap */ +static unsigned long max_total_mem = 0; + +/* internal working copy of mallinfo */ +static struct mallinfo current_mallinfo = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + +/* The total memory obtained from system via sbrk */ +#define sbrked_mem (current_mallinfo.arena) + +/* Tracking mmaps */ + +static unsigned int n_mmaps = 0; +static unsigned int max_n_mmaps = 0; +static unsigned long mmapped_mem = 0; +static unsigned long max_mmapped_mem = 0; + + + +/* + Debugging support +*/ + +#if DEBUG + + +/* + These routines make a number of assertions about the states + of data structures that should be true at all times. If any + are not true, it's very likely that a user program has somehow + trashed memory. (It's also possible that there is a coding error + in malloc. In which case, please report it!) +*/ + +#if __STD_C +static void do_check_chunk(mchunkptr p) +#else +static void do_check_chunk(p) mchunkptr p; +#endif +{ + INTERNAL_SIZE_T sz = p->size & ~PREV_INUSE; + + /* No checkable chunk is mmapped */ + assert(!chunk_is_mmapped(p)); + + /* Check for legal address ... */ + assert((char*)p >= sbrk_base); + if (p != top) + assert((char*)p + sz <= (char*)top); + else + assert((char*)p + sz <= sbrk_base + sbrked_mem); + +} + + +#if __STD_C +static void do_check_free_chunk(mchunkptr p) +#else +static void do_check_free_chunk(p) mchunkptr p; +#endif +{ + INTERNAL_SIZE_T sz = p->size & ~PREV_INUSE; + mchunkptr next = chunk_at_offset(p, sz); + + do_check_chunk(p); + + /* Check whether it claims to be free ... */ + assert(!inuse(p)); + + /* Unless a special marker, must have OK fields */ + if ((long)sz >= (long)MINSIZE) + { + assert((sz & MALLOC_ALIGN_MASK) == 0); + assert(aligned_OK(chunk2mem(p))); + /* ... matching footer field */ + assert(next->prev_size == sz); + /* ... and is fully consolidated */ + assert(prev_inuse(p)); + assert (next == top || inuse(next)); + + /* ... and has minimally sane links */ + assert(p->fd->bk == p); + assert(p->bk->fd == p); + } + else /* markers are always of size SIZE_SZ */ + assert(sz == SIZE_SZ); +} + +#if __STD_C +static void do_check_inuse_chunk(mchunkptr p) +#else +static void do_check_inuse_chunk(p) mchunkptr p; +#endif +{ + mchunkptr next = next_chunk(p); + do_check_chunk(p); + + /* Check whether it claims to be in use ... */ + assert(inuse(p)); + + /* ... and is surrounded by OK chunks. + Since more things can be checked with free chunks than inuse ones, + if an inuse chunk borders them and debug is on, it's worth doing them. + */ + if (!prev_inuse(p)) + { + mchunkptr prv = prev_chunk(p); + assert(next_chunk(prv) == p); + do_check_free_chunk(prv); + } + if (next == top) + { + assert(prev_inuse(next)); + assert(chunksize(next) >= MINSIZE); + } + else if (!inuse(next)) + do_check_free_chunk(next); + +} + +#if __STD_C +static void do_check_malloced_chunk(mchunkptr p, INTERNAL_SIZE_T s) +#else +static void do_check_malloced_chunk(p, s) mchunkptr p; INTERNAL_SIZE_T s; +#endif +{ + INTERNAL_SIZE_T sz = p->size & ~PREV_INUSE; + long room = sz - s; + + do_check_inuse_chunk(p); + + /* Legal size ... */ + assert((long)sz >= (long)MINSIZE); + assert((sz & MALLOC_ALIGN_MASK) == 0); + assert(room >= 0); + assert(room < (long)MINSIZE); + + /* ... and alignment */ + assert(aligned_OK(chunk2mem(p))); + + + /* ... and was allocated at front of an available chunk */ + assert(prev_inuse(p)); + +} + + +#define check_free_chunk(P) do_check_free_chunk(P) +#define check_inuse_chunk(P) do_check_inuse_chunk(P) +#define check_chunk(P) do_check_chunk(P) +#define check_malloced_chunk(P,N) do_check_malloced_chunk(P,N) +#else +#define check_free_chunk(P) +#define check_inuse_chunk(P) +#define check_chunk(P) +#define check_malloced_chunk(P,N) +#endif + + + +/* + Macro-based internal utilities +*/ + + +/* + Linking chunks in bin lists. + Call these only with variables, not arbitrary expressions, as arguments. +*/ + +/* + Place chunk p of size s in its bin, in size order, + putting it ahead of others of same size. +*/ + + +#define frontlink(P, S, IDX, BK, FD) \ +{ \ + if (S < MAX_SMALLBIN_SIZE) \ + { \ + IDX = smallbin_index(S); \ + mark_binblock(IDX); \ + BK = bin_at(IDX); \ + FD = BK->fd; \ + P->bk = BK; \ + P->fd = FD; \ + FD->bk = BK->fd = P; \ + } \ + else \ + { \ + IDX = bin_index(S); \ + BK = bin_at(IDX); \ + FD = BK->fd; \ + if (FD == BK) mark_binblock(IDX); \ + else \ + { \ + while (FD != BK && S < chunksize(FD)) FD = FD->fd; \ + BK = FD->bk; \ + } \ + P->bk = BK; \ + P->fd = FD; \ + FD->bk = BK->fd = P; \ + } \ +} + + +/* take a chunk off a list */ + +#define unlink(P, BK, FD) \ +{ \ + BK = P->bk; \ + FD = P->fd; \ + FD->bk = BK; \ + BK->fd = FD; \ +} \ + +/* Place p as the last remainder */ + +#define link_last_remainder(P) \ +{ \ + last_remainder->fd = last_remainder->bk = P; \ + P->fd = P->bk = last_remainder; \ +} + +/* Clear the last_remainder bin */ + +#define clear_last_remainder \ + (last_remainder->fd = last_remainder->bk = last_remainder) + + + + + +/* Routines dealing with mmap(). */ + +#if HAVE_MMAP + +#if __STD_C +static mchunkptr mmap_chunk(size_t size) +#else +static mchunkptr mmap_chunk(size) size_t size; +#endif +{ + size_t page_mask = malloc_getpagesize - 1; + mchunkptr p; + +#ifndef MAP_ANONYMOUS + static int fd = -1; +#endif + + if(n_mmaps >= n_mmaps_max) return 0; /* too many regions */ + + /* For mmapped chunks, the overhead is one SIZE_SZ unit larger, because + * there is no following chunk whose prev_size field could be used. + */ + size = (size + SIZE_SZ + page_mask) & ~page_mask; + +#ifdef MAP_ANONYMOUS + p = (mchunkptr)mmap(0, size, PROT_READ|PROT_WRITE, + MAP_PRIVATE|MAP_ANONYMOUS, -1, 0); +#else /* !MAP_ANONYMOUS */ + if (fd < 0) + { + fd = open("/dev/zero", O_RDWR); + if(fd < 0) return 0; + } + p = (mchunkptr)mmap(0, size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0); +#endif + + if(p == (mchunkptr)-1) return 0; + + n_mmaps++; + if (n_mmaps > max_n_mmaps) max_n_mmaps = n_mmaps; + + /* We demand that eight bytes into a page must be 8-byte aligned. */ + assert(aligned_OK(chunk2mem(p))); + + /* The offset to the start of the mmapped region is stored + * in the prev_size field of the chunk; normally it is zero, + * but that can be changed in memalign(). + */ + p->prev_size = 0; + set_head(p, size|IS_MMAPPED); + + mmapped_mem += size; + if ((unsigned long)mmapped_mem > (unsigned long)max_mmapped_mem) + max_mmapped_mem = mmapped_mem; + if ((unsigned long)(mmapped_mem + sbrked_mem) > (unsigned long)max_total_mem) + max_total_mem = mmapped_mem + sbrked_mem; + return p; +} + +#if __STD_C +static void munmap_chunk(mchunkptr p) +#else +static void munmap_chunk(p) mchunkptr p; +#endif +{ + INTERNAL_SIZE_T size = chunksize(p); + int ret; + + assert (chunk_is_mmapped(p)); + assert(! ((char*)p >= sbrk_base && (char*)p < sbrk_base + sbrked_mem)); + assert((n_mmaps > 0)); + assert(((p->prev_size + size) & (malloc_getpagesize-1)) == 0); + + n_mmaps--; + mmapped_mem -= (size + p->prev_size); + + ret = munmap((char *)p - p->prev_size, size + p->prev_size); + + /* munmap returns non-zero on failure */ + assert(ret == 0); +} + +#if HAVE_MREMAP + +#if __STD_C +static mchunkptr mremap_chunk(mchunkptr p, size_t new_size) +#else +static mchunkptr mremap_chunk(p, new_size) mchunkptr p; size_t new_size; +#endif +{ + size_t page_mask = malloc_getpagesize - 1; + INTERNAL_SIZE_T offset = p->prev_size; + INTERNAL_SIZE_T size = chunksize(p); + char *cp; + + assert (chunk_is_mmapped(p)); + assert(! ((char*)p >= sbrk_base && (char*)p < sbrk_base + sbrked_mem)); + assert((n_mmaps > 0)); + assert(((size + offset) & (malloc_getpagesize-1)) == 0); + + /* Note the extra SIZE_SZ overhead as in mmap_chunk(). */ + new_size = (new_size + offset + SIZE_SZ + page_mask) & ~page_mask; + + cp = (char *)mremap((char *)p - offset, size + offset, new_size, 1); + + if (cp == (char *)-1) return 0; + + p = (mchunkptr)(cp + offset); + + assert(aligned_OK(chunk2mem(p))); + + assert((p->prev_size == offset)); + set_head(p, (new_size - offset)|IS_MMAPPED); + + mmapped_mem -= size + offset; + mmapped_mem += new_size; + if ((unsigned long)mmapped_mem > (unsigned long)max_mmapped_mem) + max_mmapped_mem = mmapped_mem; + if ((unsigned long)(mmapped_mem + sbrked_mem) > (unsigned long)max_total_mem) + max_total_mem = mmapped_mem + sbrked_mem; + return p; +} + +#endif /* HAVE_MREMAP */ + +#endif /* HAVE_MMAP */ + + + + +/* + Extend the top-most chunk by obtaining memory from system. + Main interface to sbrk (but see also malloc_trim). +*/ + +#if __STD_C +static void malloc_extend_top(INTERNAL_SIZE_T nb) +#else +static void malloc_extend_top(nb) INTERNAL_SIZE_T nb; +#endif +{ + char* brk; /* return value from sbrk */ + INTERNAL_SIZE_T front_misalign; /* unusable bytes at front of sbrked space */ + INTERNAL_SIZE_T correction; /* bytes for 2nd sbrk call */ + char* new_brk; /* return of 2nd sbrk call */ + INTERNAL_SIZE_T top_size; /* new size of top chunk */ + + mchunkptr old_top = top; /* Record state of old top */ + INTERNAL_SIZE_T old_top_size = chunksize(old_top); + char* old_end = (char*)(chunk_at_offset(old_top, old_top_size)); + + /* Pad request with top_pad plus minimal overhead */ + + INTERNAL_SIZE_T sbrk_size = nb + top_pad + MINSIZE; + unsigned long pagesz = malloc_getpagesize; + + /* If not the first time through, round to preserve page boundary */ + /* Otherwise, we need to correct to a page size below anyway. */ + /* (We also correct below if an intervening foreign sbrk call.) */ + + if (sbrk_base != (char*)(-1)) + sbrk_size = (sbrk_size + (pagesz - 1)) & ~(pagesz - 1); + + brk = (char*)(MORECORE (sbrk_size)); + + /* Fail if sbrk failed or if a foreign sbrk call killed our space */ + if (brk == (char*)(MORECORE_FAILURE) || + (brk < old_end && old_top != initial_top)) + return; + + sbrked_mem += sbrk_size; + + if (brk == old_end) /* can just add bytes to current top */ + { + top_size = sbrk_size + old_top_size; + set_head(top, top_size | PREV_INUSE); + } + else + { + if (sbrk_base == (char*)(-1)) /* First time through. Record base */ + sbrk_base = brk; + else /* Someone else called sbrk(). Count those bytes as sbrked_mem. */ + sbrked_mem += brk - (char*)old_end; + + /* Guarantee alignment of first new chunk made from this space */ + front_misalign = (unsigned long)chunk2mem(brk) & MALLOC_ALIGN_MASK; + if (front_misalign > 0) + { + correction = (MALLOC_ALIGNMENT) - front_misalign; + brk += correction; + } + else + correction = 0; + + /* Guarantee the next brk will be at a page boundary */ + + correction += ((((unsigned long)(brk + sbrk_size))+(pagesz-1)) & + ~(pagesz - 1)) - ((unsigned long)(brk + sbrk_size)); + + /* Allocate correction */ + new_brk = (char*)(MORECORE (correction)); + if (new_brk == (char*)(MORECORE_FAILURE)) return; + + sbrked_mem += correction; + + top = (mchunkptr)brk; + top_size = new_brk - brk + correction; + set_head(top, top_size | PREV_INUSE); + + if (old_top != initial_top) + { + + /* There must have been an intervening foreign sbrk call. */ + /* A double fencepost is necessary to prevent consolidation */ + + /* If not enough space to do this, then user did something very wrong */ + if (old_top_size < MINSIZE) + { + set_head(top, PREV_INUSE); /* will force null return from malloc */ + return; + } + + /* Also keep size a multiple of MALLOC_ALIGNMENT */ + old_top_size = (old_top_size - 3*SIZE_SZ) & ~MALLOC_ALIGN_MASK; + set_head_size(old_top, old_top_size); + chunk_at_offset(old_top, old_top_size )->size = + SIZE_SZ|PREV_INUSE; + chunk_at_offset(old_top, old_top_size + SIZE_SZ)->size = + SIZE_SZ|PREV_INUSE; + /* If possible, release the rest. */ + if (old_top_size >= MINSIZE) + fREe(chunk2mem(old_top)); + } + } + + if ((unsigned long)sbrked_mem > (unsigned long)max_sbrked_mem) + max_sbrked_mem = sbrked_mem; + if ((unsigned long)(mmapped_mem + sbrked_mem) > (unsigned long)max_total_mem) + max_total_mem = mmapped_mem + sbrked_mem; + + /* We always land on a page boundary */ + assert(((unsigned long)((char*)top + top_size) & (pagesz - 1)) == 0); +} + + + + +/* Main public routines */ + + +/* + Malloc Algorthim: + + The requested size is first converted into a usable form, `nb'. + This currently means to add 4 bytes overhead plus possibly more to + obtain 8-byte alignment and/or to obtain a size of at least + MINSIZE (currently 16 bytes), the smallest allocatable size. + (All fits are considered `exact' if they are within MINSIZE bytes.) + + From there, the first successful of the following steps is taken: + + 1. The bin corresponding to the request size is scanned, and if + a chunk of exactly the right size is found, it is taken. + + 2. The most recently remaindered chunk is used if it is big + enough. This is a form of (roving) first fit, used only in + the absence of exact fits. Runs of consecutive requests use + the remainder of the chunk used for the previous such request + whenever possible. This limited use of a first-fit style + allocation strategy tends to give contiguous chunks + coextensive lifetimes, which improves locality and can reduce + fragmentation in the long run. + + 3. Other bins are scanned in increasing size order, using a + chunk big enough to fulfill the request, and splitting off + any remainder. This search is strictly by best-fit; i.e., + the smallest (with ties going to approximately the least + recently used) chunk that fits is selected. + + 4. If large enough, the chunk bordering the end of memory + (`top') is split off. (This use of `top' is in accord with + the best-fit search rule. In effect, `top' is treated as + larger (and thus less well fitting) than any other available + chunk since it can be extended to be as large as necessary + (up to system limitations). + + 5. If the request size meets the mmap threshold and the + system supports mmap, and there are few enough currently + allocated mmapped regions, and a call to mmap succeeds, + the request is allocated via direct memory mapping. + + 6. Otherwise, the top of memory is extended by + obtaining more space from the system (normally using sbrk, + but definable to anything else via the MORECORE macro). + Memory is gathered from the system (in system page-sized + units) in a way that allows chunks obtained across different + sbrk calls to be consolidated, but does not require + contiguous memory. Thus, it should be safe to intersperse + mallocs with other sbrk calls. + + + All allocations are made from the the `lowest' part of any found + chunk. (The implementation invariant is that prev_inuse is + always true of any allocated chunk; i.e., that each allocated + chunk borders either a previously allocated and still in-use chunk, + or the base of its memory arena.) + +*/ + +#if __STD_C +Void_t* mALLOc(size_t bytes) +#else +Void_t* mALLOc(bytes) size_t bytes; +#endif +{ + mchunkptr victim; /* inspected/selected chunk */ + INTERNAL_SIZE_T victim_size; /* its size */ + int idx; /* index for bin traversal */ + mbinptr bin; /* associated bin */ + mchunkptr remainder; /* remainder from a split */ + long remainder_size; /* its size */ + int remainder_index; /* its bin index */ + unsigned long block; /* block traverser bit */ + int startidx; /* first bin of a traversed block */ + mchunkptr fwd; /* misc temp for linking */ + mchunkptr bck; /* misc temp for linking */ + mbinptr q; /* misc temp */ + + INTERNAL_SIZE_T nb; + + if ((long)bytes < 0) return 0; + + nb = request2size(bytes); /* padded request size; */ + + /* Check for exact match in a bin */ + + if (is_small_request(nb)) /* Faster version for small requests */ + { + idx = smallbin_index(nb); + + /* No traversal or size check necessary for small bins. */ + + q = bin_at(idx); + victim = last(q); + + /* Also scan the next one, since it would have a remainder < MINSIZE */ + if (victim == q) + { + q = next_bin(q); + victim = last(q); + } + if (victim != q) + { + victim_size = chunksize(victim); + unlink(victim, bck, fwd); + set_inuse_bit_at_offset(victim, victim_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + idx += 2; /* Set for bin scan below. We've already scanned 2 bins. */ + + } + else + { + idx = bin_index(nb); + bin = bin_at(idx); + + for (victim = last(bin); victim != bin; victim = victim->bk) + { + victim_size = chunksize(victim); + remainder_size = victim_size - nb; + + if (remainder_size >= (long)MINSIZE) /* too big */ + { + --idx; /* adjust to rescan below after checking last remainder */ + break; + } + + else if (remainder_size >= 0) /* exact fit */ + { + unlink(victim, bck, fwd); + set_inuse_bit_at_offset(victim, victim_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + } + + ++idx; + + } + + /* Try to use the last split-off remainder */ + + if ( (victim = last_remainder->fd) != last_remainder) + { + victim_size = chunksize(victim); + remainder_size = victim_size - nb; + + if (remainder_size >= (long)MINSIZE) /* re-split */ + { + remainder = chunk_at_offset(victim, nb); + set_head(victim, nb | PREV_INUSE); + link_last_remainder(remainder); + set_head(remainder, remainder_size | PREV_INUSE); + set_foot(remainder, remainder_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + clear_last_remainder; + + if (remainder_size >= 0) /* exhaust */ + { + set_inuse_bit_at_offset(victim, victim_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + /* Else place in bin */ + + frontlink(victim, victim_size, remainder_index, bck, fwd); + } + + /* + If there are any possibly nonempty big-enough blocks, + search for best fitting chunk by scanning bins in blockwidth units. + */ + + if ( (block = idx2binblock(idx)) <= binblocks) + { + + /* Get to the first marked block */ + + if ( (block & binblocks) == 0) + { + /* force to an even block boundary */ + idx = (idx & ~(BINBLOCKWIDTH - 1)) + BINBLOCKWIDTH; + block <<= 1; + while ((block & binblocks) == 0) + { + idx += BINBLOCKWIDTH; + block <<= 1; + } + } + + /* For each possibly nonempty block ... */ + for (;;) + { + startidx = idx; /* (track incomplete blocks) */ + q = bin = bin_at(idx); + + /* For each bin in this block ... */ + do + { + /* Find and use first big enough chunk ... */ + + for (victim = last(bin); victim != bin; victim = victim->bk) + { + victim_size = chunksize(victim); + remainder_size = victim_size - nb; + + if (remainder_size >= (long)MINSIZE) /* split */ + { + remainder = chunk_at_offset(victim, nb); + set_head(victim, nb | PREV_INUSE); + unlink(victim, bck, fwd); + link_last_remainder(remainder); + set_head(remainder, remainder_size | PREV_INUSE); + set_foot(remainder, remainder_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + else if (remainder_size >= 0) /* take */ + { + set_inuse_bit_at_offset(victim, victim_size); + unlink(victim, bck, fwd); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + } + + bin = next_bin(bin); + + } while ((++idx & (BINBLOCKWIDTH - 1)) != 0); + + /* Clear out the block bit. */ + + do /* Possibly backtrack to try to clear a partial block */ + { + if ((startidx & (BINBLOCKWIDTH - 1)) == 0) + { + binblocks &= ~block; + break; + } + --startidx; + q = prev_bin(q); + } while (first(q) == q); + + /* Get to the next possibly nonempty block */ + + if ( (block <<= 1) <= binblocks && (block != 0) ) + { + while ((block & binblocks) == 0) + { + idx += BINBLOCKWIDTH; + block <<= 1; + } + } + else + break; + } + } + + + /* Try to use top chunk */ + + /* Require that there be a remainder, ensuring top always exists */ + if ( (remainder_size = chunksize(top) - nb) < (long)MINSIZE) + { + +#if HAVE_MMAP + /* If big and would otherwise need to extend, try to use mmap instead */ + if ((unsigned long)nb >= (unsigned long)mmap_threshold && + (victim = mmap_chunk(nb)) != 0) + return chunk2mem(victim); +#endif + + /* Try to extend */ + malloc_extend_top(nb); + if ( (remainder_size = chunksize(top) - nb) < (long)MINSIZE) + return 0; /* propagate failure */ + } + + victim = top; + set_head(victim, nb | PREV_INUSE); + top = chunk_at_offset(victim, nb); + set_head(top, remainder_size | PREV_INUSE); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + +} + + + + +/* + + free() algorithm : + + cases: + + 1. free(0) has no effect. + + 2. If the chunk was allocated via mmap, it is release via munmap(). + + 3. If a returned chunk borders the current high end of memory, + it is consolidated into the top, and if the total unused + topmost memory exceeds the trim threshold, malloc_trim is + called. + + 4. Other chunks are consolidated as they arrive, and + placed in corresponding bins. (This includes the case of + consolidating with the current `last_remainder'). + +*/ + + +#if __STD_C +void fREe(Void_t* mem) +#else +void fREe(mem) Void_t* mem; +#endif +{ + mchunkptr p; /* chunk corresponding to mem */ + INTERNAL_SIZE_T hd; /* its head field */ + INTERNAL_SIZE_T sz; /* its size */ + int idx; /* its bin index */ + mchunkptr next; /* next contiguous chunk */ + INTERNAL_SIZE_T nextsz; /* its size */ + INTERNAL_SIZE_T prevsz; /* size of previous contiguous chunk */ + mchunkptr bck; /* misc temp for linking */ + mchunkptr fwd; /* misc temp for linking */ + int islr; /* track whether merging with last_remainder */ + + if (mem == 0) /* free(0) has no effect */ + return; + + p = mem2chunk(mem); + hd = p->size; + +#if HAVE_MMAP + if (hd & IS_MMAPPED) /* release mmapped memory. */ + { + munmap_chunk(p); + return; + } +#endif + + check_inuse_chunk(p); + + sz = hd & ~PREV_INUSE; + next = chunk_at_offset(p, sz); + nextsz = chunksize(next); + + if (next == top) /* merge with top */ + { + sz += nextsz; + + if (!(hd & PREV_INUSE)) /* consolidate backward */ + { + prevsz = p->prev_size; + p = chunk_at_offset(p, -((long) prevsz)); + sz += prevsz; + unlink(p, bck, fwd); + } + + set_head(p, sz | PREV_INUSE); + top = p; + if ((unsigned long)(sz) >= (unsigned long)trim_threshold) + malloc_trim(top_pad); + return; + } + + set_head(next, nextsz); /* clear inuse bit */ + + islr = 0; + + if (!(hd & PREV_INUSE)) /* consolidate backward */ + { + prevsz = p->prev_size; + p = chunk_at_offset(p, -((long) prevsz)); + sz += prevsz; + + if (p->fd == last_remainder) /* keep as last_remainder */ + islr = 1; + else + unlink(p, bck, fwd); + } + + if (!(inuse_bit_at_offset(next, nextsz))) /* consolidate forward */ + { + sz += nextsz; + + if (!islr && next->fd == last_remainder) /* re-insert last_remainder */ + { + islr = 1; + link_last_remainder(p); + } + else + unlink(next, bck, fwd); + } + + + set_head(p, sz | PREV_INUSE); + set_foot(p, sz); + if (!islr) + frontlink(p, sz, idx, bck, fwd); +} + + + + + +/* + + Realloc algorithm: + + Chunks that were obtained via mmap cannot be extended or shrunk + unless HAVE_MREMAP is defined, in which case mremap is used. + Otherwise, if their reallocation is for additional space, they are + copied. If for less, they are just left alone. + + Otherwise, if the reallocation is for additional space, and the + chunk can be extended, it is, else a malloc-copy-free sequence is + taken. There are several different ways that a chunk could be + extended. All are tried: + + * Extending forward into following adjacent free chunk. + * Shifting backwards, joining preceding adjacent space + * Both shifting backwards and extending forward. + * Extending into newly sbrked space + + Unless the #define REALLOC_ZERO_BYTES_FREES is set, realloc with a + size argument of zero (re)allocates a minimum-sized chunk. + + If the reallocation is for less space, and the new request is for + a `small' (<512 bytes) size, then the newly unused space is lopped + off and freed. + + The old unix realloc convention of allowing the last-free'd chunk + to be used as an argument to realloc is no longer supported. + I don't know of any programs still relying on this feature, + and allowing it would also allow too many other incorrect + usages of realloc to be sensible. + + +*/ + + +#if __STD_C +Void_t* rEALLOc(Void_t* oldmem, size_t bytes) +#else +Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; +#endif +{ + INTERNAL_SIZE_T nb; /* padded request size */ + + mchunkptr oldp; /* chunk corresponding to oldmem */ + INTERNAL_SIZE_T oldsize; /* its size */ + + mchunkptr newp; /* chunk to return */ + INTERNAL_SIZE_T newsize; /* its size */ + Void_t* newmem; /* corresponding user mem */ + + mchunkptr next; /* next contiguous chunk after oldp */ + INTERNAL_SIZE_T nextsize; /* its size */ + + mchunkptr prev; /* previous contiguous chunk before oldp */ + INTERNAL_SIZE_T prevsize; /* its size */ + + mchunkptr remainder; /* holds split off extra space from newp */ + INTERNAL_SIZE_T remainder_size; /* its size */ + + mchunkptr bck; /* misc temp for linking */ + mchunkptr fwd; /* misc temp for linking */ + +#ifdef REALLOC_ZERO_BYTES_FREES + if (bytes == 0) { fREe(oldmem); return 0; } +#endif + + if ((long)bytes < 0) return 0; + + /* realloc of null is supposed to be same as malloc */ + if (oldmem == 0) return mALLOc(bytes); + + newp = oldp = mem2chunk(oldmem); + newsize = oldsize = chunksize(oldp); + + + nb = request2size(bytes); + +#if HAVE_MMAP + if (chunk_is_mmapped(oldp)) + { +#if HAVE_MREMAP + newp = mremap_chunk(oldp, nb); + if(newp) return chunk2mem(newp); +#endif + /* Note the extra SIZE_SZ overhead. */ + if(oldsize - SIZE_SZ >= nb) return oldmem; /* do nothing */ + /* Must alloc, copy, free. */ + newmem = mALLOc(bytes); + if (newmem == 0) return 0; /* propagate failure */ + MALLOC_COPY(newmem, oldmem, oldsize - 2*SIZE_SZ); + munmap_chunk(oldp); + return newmem; + } +#endif + + check_inuse_chunk(oldp); + + if ((long)(oldsize) < (long)(nb)) + { + + /* Try expanding forward */ + + next = chunk_at_offset(oldp, oldsize); + if (next == top || !inuse(next)) + { + nextsize = chunksize(next); + + /* Forward into top only if a remainder */ + if (next == top) + { + if ((long)(nextsize + newsize) >= (long)(nb + MINSIZE)) + { + newsize += nextsize; + top = chunk_at_offset(oldp, nb); + set_head(top, (newsize - nb) | PREV_INUSE); + set_head_size(oldp, nb); + return chunk2mem(oldp); + } + } + + /* Forward into next chunk */ + else if (((long)(nextsize + newsize) >= (long)(nb))) + { + unlink(next, bck, fwd); + newsize += nextsize; + goto split; + } + } + else + { + next = 0; + nextsize = 0; + } + + /* Try shifting backwards. */ + + if (!prev_inuse(oldp)) + { + prev = prev_chunk(oldp); + prevsize = chunksize(prev); + + /* try forward + backward first to save a later consolidation */ + + if (next != 0) + { + /* into top */ + if (next == top) + { + if ((long)(nextsize + prevsize + newsize) >= (long)(nb + MINSIZE)) + { + unlink(prev, bck, fwd); + newp = prev; + newsize += prevsize + nextsize; + newmem = chunk2mem(newp); + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + top = chunk_at_offset(newp, nb); + set_head(top, (newsize - nb) | PREV_INUSE); + set_head_size(newp, nb); + return newmem; + } + } + + /* into next chunk */ + else if (((long)(nextsize + prevsize + newsize) >= (long)(nb))) + { + unlink(next, bck, fwd); + unlink(prev, bck, fwd); + newp = prev; + newsize += nextsize + prevsize; + newmem = chunk2mem(newp); + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + goto split; + } + } + + /* backward only */ + if (prev != 0 && (long)(prevsize + newsize) >= (long)nb) + { + unlink(prev, bck, fwd); + newp = prev; + newsize += prevsize; + newmem = chunk2mem(newp); + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + goto split; + } + } + + /* Must allocate */ + + newmem = mALLOc (bytes); + + if (newmem == 0) /* propagate failure */ + return 0; + + /* Avoid copy if newp is next chunk after oldp. */ + /* (This can only happen when new chunk is sbrk'ed.) */ + + if ( (newp = mem2chunk(newmem)) == next_chunk(oldp)) + { + newsize += chunksize(newp); + newp = oldp; + goto split; + } + + /* Otherwise copy, free, and exit */ + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + fREe(oldmem); + return newmem; + } + + + split: /* split off extra room in old or expanded chunk */ + + if (newsize - nb >= MINSIZE) /* split off remainder */ + { + remainder = chunk_at_offset(newp, nb); + remainder_size = newsize - nb; + set_head_size(newp, nb); + set_head(remainder, remainder_size | PREV_INUSE); + set_inuse_bit_at_offset(remainder, remainder_size); + fREe(chunk2mem(remainder)); /* let free() deal with it */ + } + else + { + set_head_size(newp, newsize); + set_inuse_bit_at_offset(newp, newsize); + } + + check_inuse_chunk(newp); + return chunk2mem(newp); +} + + + + +/* + + memalign algorithm: + + memalign requests more than enough space from malloc, finds a spot + within that chunk that meets the alignment request, and then + possibly frees the leading and trailing space. + + The alignment argument must be a power of two. This property is not + checked by memalign, so misuse may result in random runtime errors. + + 8-byte alignment is guaranteed by normal malloc calls, so don't + bother calling memalign with an argument of 8 or less. + + Overreliance on memalign is a sure way to fragment space. + +*/ + + +#if __STD_C +Void_t* mEMALIGn(size_t alignment, size_t bytes) +#else +Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; +#endif +{ + INTERNAL_SIZE_T nb; /* padded request size */ + char* m; /* memory returned by malloc call */ + mchunkptr p; /* corresponding chunk */ + char* brk; /* alignment point within p */ + mchunkptr newp; /* chunk to return */ + INTERNAL_SIZE_T newsize; /* its size */ + INTERNAL_SIZE_T leadsize; /* leading space befor alignment point */ + mchunkptr remainder; /* spare room at end to split off */ + long remainder_size; /* its size */ + + if ((long)bytes < 0) return 0; + + /* If need less alignment than we give anyway, just relay to malloc */ + + if (alignment <= MALLOC_ALIGNMENT) return mALLOc(bytes); + + /* Otherwise, ensure that it is at least a minimum chunk size */ + + if (alignment < MINSIZE) alignment = MINSIZE; + + /* Call malloc with worst case padding to hit alignment. */ + + nb = request2size(bytes); + m = (char*)(mALLOc(nb + alignment + MINSIZE)); + + if (m == 0) return 0; /* propagate failure */ + + p = mem2chunk(m); + + if ((((unsigned long)(m)) % alignment) == 0) /* aligned */ + { +#if HAVE_MMAP + if(chunk_is_mmapped(p)) + return chunk2mem(p); /* nothing more to do */ +#endif + } + else /* misaligned */ + { + /* + Find an aligned spot inside chunk. + Since we need to give back leading space in a chunk of at + least MINSIZE, if the first calculation places us at + a spot with less than MINSIZE leader, we can move to the + next aligned spot -- we've allocated enough total room so that + this is always possible. + */ + + brk = (char*)mem2chunk(((unsigned long)(m + alignment - 1)) & -((signed) alignment)); + if ((long)(brk - (char*)(p)) < MINSIZE) brk = brk + alignment; + + newp = (mchunkptr)brk; + leadsize = brk - (char*)(p); + newsize = chunksize(p) - leadsize; + +#if HAVE_MMAP + if(chunk_is_mmapped(p)) + { + newp->prev_size = p->prev_size + leadsize; + set_head(newp, newsize|IS_MMAPPED); + return chunk2mem(newp); + } +#endif + + /* give back leader, use the rest */ + + set_head(newp, newsize | PREV_INUSE); + set_inuse_bit_at_offset(newp, newsize); + set_head_size(p, leadsize); + fREe(chunk2mem(p)); + p = newp; + + assert (newsize >= nb && (((unsigned long)(chunk2mem(p))) % alignment) == 0); + } + + /* Also give back spare room at the end */ + + remainder_size = chunksize(p) - nb; + + if (remainder_size >= (long)MINSIZE) + { + remainder = chunk_at_offset(p, nb); + set_head(remainder, remainder_size | PREV_INUSE); + set_head_size(p, nb); + fREe(chunk2mem(remainder)); + } + + check_inuse_chunk(p); + return chunk2mem(p); + +} + + + + +/* + valloc just invokes memalign with alignment argument equal + to the page size of the system (or as near to this as can + be figured out from all the includes/defines above.) +*/ + +#if __STD_C +Void_t* vALLOc(size_t bytes) +#else +Void_t* vALLOc(bytes) size_t bytes; +#endif +{ + return mEMALIGn (malloc_getpagesize, bytes); +} + +/* + pvalloc just invokes valloc for the nearest pagesize + that will accommodate request +*/ + + +#if __STD_C +Void_t* pvALLOc(size_t bytes) +#else +Void_t* pvALLOc(bytes) size_t bytes; +#endif +{ + size_t pagesize = malloc_getpagesize; + return mEMALIGn (pagesize, (bytes + pagesize - 1) & ~(pagesize - 1)); +} + +/* + + calloc calls malloc, then zeroes out the allocated chunk. + +*/ + +#if __STD_C +Void_t* cALLOc(size_t n, size_t elem_size) +#else +Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; +#endif +{ + mchunkptr p; + INTERNAL_SIZE_T csz; + + INTERNAL_SIZE_T sz = n * elem_size; + + + /* check if expand_top called, in which case don't need to clear */ +#if MORECORE_CLEARS + mchunkptr oldtop = top; + INTERNAL_SIZE_T oldtopsize = chunksize(top); +#endif + Void_t* mem = mALLOc (sz); + + if ((long)n < 0) return 0; + + if (mem == 0) + return 0; + else + { + p = mem2chunk(mem); + + /* Two optional cases in which clearing not necessary */ + + +#if HAVE_MMAP + if (chunk_is_mmapped(p)) return mem; +#endif + + csz = chunksize(p); + +#if MORECORE_CLEARS + if (p == oldtop && csz > oldtopsize) + { + /* clear only the bytes from non-freshly-sbrked memory */ + csz = oldtopsize; + } +#endif + + MALLOC_ZERO(mem, csz - SIZE_SZ); + return mem; + } +} + +/* + + cfree just calls free. It is needed/defined on some systems + that pair it with calloc, presumably for odd historical reasons. + +*/ + +#if !defined(INTERNAL_LINUX_C_LIB) || !defined(__ELF__) +#if __STD_C +void cfree(Void_t *mem) +#else +void cfree(mem) Void_t *mem; +#endif +{ + fREe(mem); +} +#endif + + + +/* + + Malloc_trim gives memory back to the system (via negative + arguments to sbrk) if there is unused memory at the `high' end of + the malloc pool. You can call this after freeing large blocks of + memory to potentially reduce the system-level memory requirements + of a program. However, it cannot guarantee to reduce memory. Under + some allocation patterns, some large free blocks of memory will be + locked between two used chunks, so they cannot be given back to + the system. + + The `pad' argument to malloc_trim represents the amount of free + trailing space to leave untrimmed. If this argument is zero, + only the minimum amount of memory to maintain internal data + structures will be left (one page or less). Non-zero arguments + can be supplied to maintain enough trailing space to service + future expected allocations without having to re-obtain memory + from the system. + + Malloc_trim returns 1 if it actually released any memory, else 0. + +*/ + +#if __STD_C +int malloc_trim(size_t pad) +#else +int malloc_trim(pad) size_t pad; +#endif +{ + long top_size; /* Amount of top-most memory */ + long extra; /* Amount to release */ + char* current_brk; /* address returned by pre-check sbrk call */ + char* new_brk; /* address returned by negative sbrk call */ + + unsigned long pagesz = malloc_getpagesize; + + top_size = chunksize(top); + extra = ((top_size - pad - MINSIZE + (pagesz-1)) / pagesz - 1) * pagesz; + + if (extra < (long)pagesz) /* Not enough memory to release */ + return 0; + + else + { + /* Test to make sure no one else called sbrk */ + current_brk = (char*)(MORECORE (0)); + if (current_brk != (char*)(top) + top_size) + return 0; /* Apparently we don't own memory; must fail */ + + else + { + new_brk = (char*)(MORECORE (-extra)); + + if (new_brk == (char*)(MORECORE_FAILURE)) /* sbrk failed? */ + { + /* Try to figure out what we have */ + current_brk = (char*)(MORECORE (0)); + top_size = current_brk - (char*)top; + if (top_size >= (long)MINSIZE) /* if not, we are very very dead! */ + { + sbrked_mem = current_brk - sbrk_base; + set_head(top, top_size | PREV_INUSE); + } + check_chunk(top); + return 0; + } + + else + { + /* Success. Adjust top accordingly. */ + set_head(top, (top_size - extra) | PREV_INUSE); + sbrked_mem -= extra; + check_chunk(top); + return 1; + } + } + } +} + + + +/* + malloc_usable_size: + + This routine tells you how many bytes you can actually use in an + allocated chunk, which may be more than you requested (although + often not). You can use this many bytes without worrying about + overwriting other allocated objects. Not a particularly great + programming practice, but still sometimes useful. + +*/ + +#if __STD_C +size_t malloc_usable_size(Void_t* mem) +#else +size_t malloc_usable_size(mem) Void_t* mem; +#endif +{ + mchunkptr p; + if (mem == 0) + return 0; + else + { + p = mem2chunk(mem); + if(!chunk_is_mmapped(p)) + { + if (!inuse(p)) return 0; + check_inuse_chunk(p); + return chunksize(p) - SIZE_SZ; + } + return chunksize(p) - 2*SIZE_SZ; + } +} + + + + +/* Utility to update current_mallinfo for malloc_stats and mallinfo() */ + +static void malloc_update_mallinfo() +{ + int i; + mbinptr b; + mchunkptr p; +#if DEBUG + mchunkptr q; +#endif + + INTERNAL_SIZE_T avail = chunksize(top); + int navail = ((long)(avail) >= (long)MINSIZE)? 1 : 0; + + for (i = 1; i < NAV; ++i) + { + b = bin_at(i); + for (p = last(b); p != b; p = p->bk) + { +#if DEBUG + check_free_chunk(p); + for (q = next_chunk(p); + q < top && inuse(q) && (long)(chunksize(q)) >= (long)MINSIZE; + q = next_chunk(q)) + check_inuse_chunk(q); +#endif + avail += chunksize(p); + navail++; + } + } + + current_mallinfo.ordblks = navail; + current_mallinfo.uordblks = sbrked_mem - avail; + current_mallinfo.fordblks = avail; + current_mallinfo.hblks = n_mmaps; + current_mallinfo.hblkhd = mmapped_mem; + current_mallinfo.keepcost = chunksize(top); + +} + + + +/* + + malloc_stats: + + Prints on stderr the amount of space obtain from the system (both + via sbrk and mmap), the maximum amount (which may be more than + current if malloc_trim and/or munmap got called), the maximum + number of simultaneous mmap regions used, and the current number + of bytes allocated via malloc (or realloc, etc) but not yet + freed. (Note that this is the number of bytes allocated, not the + number requested. It will be larger than the number requested + because of alignment and bookkeeping overhead.) + +*/ + +void malloc_stats() +{ + malloc_update_mallinfo(); + fprintf(stderr, "max system bytes = %10u\n", + (unsigned int)(max_total_mem)); + fprintf(stderr, "system bytes = %10u\n", + (unsigned int)(sbrked_mem + mmapped_mem)); + fprintf(stderr, "in use bytes = %10u\n", + (unsigned int)(current_mallinfo.uordblks + mmapped_mem)); +#if HAVE_MMAP + fprintf(stderr, "max mmap regions = %10u\n", + (unsigned int)max_n_mmaps); +#endif +} + +/* + mallinfo returns a copy of updated current mallinfo. +*/ + +struct mallinfo mALLINFo() +{ + malloc_update_mallinfo(); + return current_mallinfo; +} + + + + +/* + mallopt: + + mallopt is the general SVID/XPG interface to tunable parameters. + The format is to provide a (parameter-number, parameter-value) pair. + mallopt then sets the corresponding parameter to the argument + value if it can (i.e., so long as the value is meaningful), + and returns 1 if successful else 0. + + See descriptions of tunable parameters above. + +*/ + +#if __STD_C +int mALLOPt(int param_number, int value) +#else +int mALLOPt(param_number, value) int param_number; int value; +#endif +{ + switch(param_number) + { + case M_TRIM_THRESHOLD: + trim_threshold = value; return 1; + case M_TOP_PAD: + top_pad = value; return 1; + case M_MMAP_THRESHOLD: + mmap_threshold = value; return 1; + case M_MMAP_MAX: +#if HAVE_MMAP + n_mmaps_max = value; return 1; +#else + if (value != 0) return 0; else n_mmaps_max = value; return 1; +#endif + + default: + return 0; + } +} + +/* + +History: + + V2.6.6 Sun Dec 5 07:42:19 1999 Doug Lea (dl at gee) + * return null for negative arguments + * Added Several WIN32 cleanups from Martin C. Fong + * Add 'LACKS_SYS_PARAM_H' for those systems without 'sys/param.h' + (e.g. WIN32 platforms) + * Cleanup up header file inclusion for WIN32 platforms + * Cleanup code to avoid Microsoft Visual C++ compiler complaints + * Add 'USE_DL_PREFIX' to quickly allow co-existence with existing + memory allocation routines + * Set 'malloc_getpagesize' for WIN32 platforms (needs more work) + * Use 'assert' rather than 'ASSERT' in WIN32 code to conform to + usage of 'assert' in non-WIN32 code + * Improve WIN32 'sbrk()' emulation's 'findRegion()' routine to + avoid infinite loop + * Always call 'fREe()' rather than 'free()' + + V2.6.5 Wed Jun 17 15:57:31 1998 Doug Lea (dl at gee) + * Fixed ordering problem with boundary-stamping + + V2.6.3 Sun May 19 08:17:58 1996 Doug Lea (dl at gee) + * Added pvalloc, as recommended by H.J. Liu + * Added 64bit pointer support mainly from Wolfram Gloger + * Added anonymously donated WIN32 sbrk emulation + * Malloc, calloc, getpagesize: add optimizations from Raymond Nijssen + * malloc_extend_top: fix mask error that caused wastage after + foreign sbrks + * Add linux mremap support code from HJ Liu + + V2.6.2 Tue Dec 5 06:52:55 1995 Doug Lea (dl at gee) + * Integrated most documentation with the code. + * Add support for mmap, with help from + Wolfram Gloger (Gloger@lrz.uni-muenchen.de). + * Use last_remainder in more cases. + * Pack bins using idea from colin@nyx10.cs.du.edu + * Use ordered bins instead of best-fit threshhold + * Eliminate block-local decls to simplify tracing and debugging. + * Support another case of realloc via move into top + * Fix error occuring when initial sbrk_base not word-aligned. + * Rely on page size for units instead of SBRK_UNIT to + avoid surprises about sbrk alignment conventions. + * Add mallinfo, mallopt. Thanks to Raymond Nijssen + (raymond@es.ele.tue.nl) for the suggestion. + * Add `pad' argument to malloc_trim and top_pad mallopt parameter. + * More precautions for cases where other routines call sbrk, + courtesy of Wolfram Gloger (Gloger@lrz.uni-muenchen.de). + * Added macros etc., allowing use in linux libc from + H.J. Lu (hjl@gnu.ai.mit.edu) + * Inverted this history list + + V2.6.1 Sat Dec 2 14:10:57 1995 Doug Lea (dl at gee) + * Re-tuned and fixed to behave more nicely with V2.6.0 changes. + * Removed all preallocation code since under current scheme + the work required to undo bad preallocations exceeds + the work saved in good cases for most test programs. + * No longer use return list or unconsolidated bins since + no scheme using them consistently outperforms those that don't + given above changes. + * Use best fit for very large chunks to prevent some worst-cases. + * Added some support for debugging + + V2.6.0 Sat Nov 4 07:05:23 1995 Doug Lea (dl at gee) + * Removed footers when chunks are in use. Thanks to + Paul Wilson (wilson@cs.texas.edu) for the suggestion. + + V2.5.4 Wed Nov 1 07:54:51 1995 Doug Lea (dl at gee) + * Added malloc_trim, with help from Wolfram Gloger + (wmglo@Dent.MED.Uni-Muenchen.DE). + + V2.5.3 Tue Apr 26 10:16:01 1994 Doug Lea (dl at g) + + V2.5.2 Tue Apr 5 16:20:40 1994 Doug Lea (dl at g) + * realloc: try to expand in both directions + * malloc: swap order of clean-bin strategy; + * realloc: only conditionally expand backwards + * Try not to scavenge used bins + * Use bin counts as a guide to preallocation + * Occasionally bin return list chunks in first scan + * Add a few optimizations from colin@nyx10.cs.du.edu + + V2.5.1 Sat Aug 14 15:40:43 1993 Doug Lea (dl at g) + * faster bin computation & slightly different binning + * merged all consolidations to one part of malloc proper + (eliminating old malloc_find_space & malloc_clean_bin) + * Scan 2 returns chunks (not just 1) + * Propagate failure in realloc if malloc returns 0 + * Add stuff to allow compilation on non-ANSI compilers + from kpv@research.att.com + + V2.5 Sat Aug 7 07:41:59 1993 Doug Lea (dl at g.oswego.edu) + * removed potential for odd address access in prev_chunk + * removed dependency on getpagesize.h + * misc cosmetics and a bit more internal documentation + * anticosmetics: mangled names in macros to evade debugger strangeness + * tested on sparc, hp-700, dec-mips, rs6000 + with gcc & native cc (hp, dec only) allowing + Detlefs & Zorn comparison study (in SIGPLAN Notices.) + + Trial version Fri Aug 28 13:14:29 1992 Doug Lea (dl at g.oswego.edu) + * Based loosely on libg++-1.2X malloc. (It retains some of the overall + structure of old version, but most details differ.) + +*/ diff --git a/common/docecc.c b/common/docecc.c new file mode 100644 index 0000000..79adb48 --- /dev/null +++ b/common/docecc.c @@ -0,0 +1,517 @@ +/* + * ECC algorithm for M-systems disk on chip. We use the excellent Reed + * Solmon code of Phil Karn (karn@ka9q.ampr.org) available under the + * GNU GPL License. The rest is simply to convert the disk on chip + * syndrom into a standard syndom. + * + * Author: Fabrice Bellard (fabrice.bellard@netgem.com) + * Copyright (C) 2000 Netgem S.A. + * + * $Id: docecc.c,v 1.4 2001/10/02 15:05:13 dwmw2 Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include + +#undef ECC_DEBUG +#undef PSYCHO_DEBUG + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) + +#include + +/* need to undef it (from asm/termbits.h) */ +#undef B0 + +#define MM 10 /* Symbol size in bits */ +#define KK (1023-4) /* Number of data symbols per block */ +#define B0 510 /* First root of generator polynomial, alpha form */ +#define PRIM 1 /* power of alpha used to generate roots of generator poly */ +#define NN ((1 << MM) - 1) + +typedef unsigned short dtype; + +/* 1+x^3+x^10 */ +static const int Pp[MM+1] = { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1 }; + +/* This defines the type used to store an element of the Galois Field + * used by the code. Make sure this is something larger than a char if + * if anything larger than GF(256) is used. + * + * Note: unsigned char will work up to GF(256) but int seems to run + * faster on the Pentium. + */ +typedef int gf; + +/* No legal value in index form represents zero, so + * we need a special value for this purpose + */ +#define A0 (NN) + +/* Compute x % NN, where NN is 2**MM - 1, + * without a slow divide + */ +static inline gf +modnn(int x) +{ + while (x >= NN) { + x -= NN; + x = (x >> MM) + (x & NN); + } + return x; +} + +#define CLEAR(a,n) {\ +int ci;\ +for(ci=(n)-1;ci >=0;ci--)\ +(a)[ci] = 0;\ +} + +#define COPY(a,b,n) {\ +int ci;\ +for(ci=(n)-1;ci >=0;ci--)\ +(a)[ci] = (b)[ci];\ +} + +#define COPYDOWN(a,b,n) {\ +int ci;\ +for(ci=(n)-1;ci >=0;ci--)\ +(a)[ci] = (b)[ci];\ +} + +#define Ldec 1 + +/* generate GF(2**m) from the irreducible polynomial p(X) in Pp[0]..Pp[m] + lookup tables: index->polynomial form alpha_to[] contains j=alpha**i; + polynomial form -> index form index_of[j=alpha**i] = i + alpha=2 is the primitive element of GF(2**m) + HARI's COMMENT: (4/13/94) alpha_to[] can be used as follows: + Let @ represent the primitive element commonly called "alpha" that + is the root of the primitive polynomial p(x). Then in GF(2^m), for any + 0 <= i <= 2^m-2, + @^i = a(0) + a(1) @ + a(2) @^2 + ... + a(m-1) @^(m-1) + where the binary vector (a(0),a(1),a(2),...,a(m-1)) is the representation + of the integer "alpha_to[i]" with a(0) being the LSB and a(m-1) the MSB. Thus for + example the polynomial representation of @^5 would be given by the binary + representation of the integer "alpha_to[5]". + Similarily, index_of[] can be used as follows: + As above, let @ represent the primitive element of GF(2^m) that is + the root of the primitive polynomial p(x). In order to find the power + of @ (alpha) that has the polynomial representation + a(0) + a(1) @ + a(2) @^2 + ... + a(m-1) @^(m-1) + we consider the integer "i" whose binary representation with a(0) being LSB + and a(m-1) MSB is (a(0),a(1),...,a(m-1)) and locate the entry + "index_of[i]". Now, @^index_of[i] is that element whose polynomial + representation is (a(0),a(1),a(2),...,a(m-1)). + NOTE: + The element alpha_to[2^m-1] = 0 always signifying that the + representation of "@^infinity" = 0 is (0,0,0,...,0). + Similarily, the element index_of[0] = A0 always signifying + that the power of alpha which has the polynomial representation + (0,0,...,0) is "infinity". + +*/ + +static void +generate_gf(dtype Alpha_to[NN + 1], dtype Index_of[NN + 1]) +{ + register int i, mask; + + mask = 1; + Alpha_to[MM] = 0; + for (i = 0; i < MM; i++) { + Alpha_to[i] = mask; + Index_of[Alpha_to[i]] = i; + /* If Pp[i] == 1 then, term @^i occurs in poly-repr of @^MM */ + if (Pp[i] != 0) + Alpha_to[MM] ^= mask; /* Bit-wise EXOR operation */ + mask <<= 1; /* single left-shift */ + } + Index_of[Alpha_to[MM]] = MM; + /* + * Have obtained poly-repr of @^MM. Poly-repr of @^(i+1) is given by + * poly-repr of @^i shifted left one-bit and accounting for any @^MM + * term that may occur when poly-repr of @^i is shifted. + */ + mask >>= 1; + for (i = MM + 1; i < NN; i++) { + if (Alpha_to[i - 1] >= mask) + Alpha_to[i] = Alpha_to[MM] ^ ((Alpha_to[i - 1] ^ mask) << 1); + else + Alpha_to[i] = Alpha_to[i - 1] << 1; + Index_of[Alpha_to[i]] = i; + } + Index_of[0] = A0; + Alpha_to[NN] = 0; +} + +/* + * Performs ERRORS+ERASURES decoding of RS codes. bb[] is the content + * of the feedback shift register after having processed the data and + * the ECC. + * + * Return number of symbols corrected, or -1 if codeword is illegal + * or uncorrectable. If eras_pos is non-null, the detected error locations + * are written back. NOTE! This array must be at least NN-KK elements long. + * The corrected data are written in eras_val[]. They must be xor with the data + * to retrieve the correct data : data[erase_pos[i]] ^= erase_val[i] . + * + * First "no_eras" erasures are declared by the calling program. Then, the + * maximum # of errors correctable is t_after_eras = floor((NN-KK-no_eras)/2). + * If the number of channel errors is not greater than "t_after_eras" the + * transmitted codeword will be recovered. Details of algorithm can be found + * in R. Blahut's "Theory ... of Error-Correcting Codes". + + * Warning: the eras_pos[] array must not contain duplicate entries; decoder failure + * will result. The decoder *could* check for this condition, but it would involve + * extra time on every decoding operation. + * */ +static int +eras_dec_rs(dtype Alpha_to[NN + 1], dtype Index_of[NN + 1], + gf bb[NN - KK + 1], gf eras_val[NN-KK], int eras_pos[NN-KK], + int no_eras) +{ + int deg_lambda, el, deg_omega; + int i, j, r,k; + gf u,q,tmp,num1,num2,den,discr_r; + gf lambda[NN-KK + 1], s[NN-KK + 1]; /* Err+Eras Locator poly + * and syndrome poly */ + gf b[NN-KK + 1], t[NN-KK + 1], omega[NN-KK + 1]; + gf root[NN-KK], reg[NN-KK + 1], loc[NN-KK]; + int syn_error, count; + + syn_error = 0; + for(i=0;i 0) { + /* Init lambda to be the erasure locator polynomial */ + lambda[1] = Alpha_to[modnn(PRIM * eras_pos[0])]; + for (i = 1; i < no_eras; i++) { + u = modnn(PRIM*eras_pos[i]); + for (j = i+1; j > 0; j--) { + tmp = Index_of[lambda[j - 1]]; + if(tmp != A0) + lambda[j] ^= Alpha_to[modnn(u + tmp)]; + } + } +#ifdef ECC_DEBUG + /* Test code that verifies the erasure locator polynomial just constructed + Needed only for decoder debugging. */ + + /* find roots of the erasure location polynomial */ + for(i=1;i<=no_eras;i++) + reg[i] = Index_of[lambda[i]]; + count = 0; + for (i = 1,k=NN-Ldec; i <= NN; i++,k = modnn(NN+k-Ldec)) { + q = 1; + for (j = 1; j <= no_eras; j++) + if (reg[j] != A0) { + reg[j] = modnn(reg[j] + j); + q ^= Alpha_to[reg[j]]; + } + if (q != 0) + continue; + /* store root and error location number indices */ + root[count] = i; + loc[count] = k; + count++; + } + if (count != no_eras) { + printf("\n lambda(x) is WRONG\n"); + count = -1; + goto finish; + } +#ifdef PSYCHO_DEBUG + printf("\n Erasure positions as determined by roots of Eras Loc Poly:\n"); + for (i = 0; i < count; i++) + printf("%d ", loc[i]); + printf("\n"); +#endif +#endif + } + for(i=0;i 0; j--){ + if (reg[j] != A0) { + reg[j] = modnn(reg[j] + j); + q ^= Alpha_to[reg[j]]; + } + } + if (q != 0) + continue; + /* store root (index-form) and error location number */ + root[count] = i; + loc[count] = k; + /* If we've already found max possible roots, + * abort the search to save time + */ + if(++count == deg_lambda) + break; + } + if (deg_lambda != count) { + /* + * deg(lambda) unequal to number of roots => uncorrectable + * error detected + */ + count = -1; + goto finish; + } + /* + * Compute err+eras evaluator poly omega(x) = s(x)*lambda(x) (modulo + * x**(NN-KK)). in index form. Also find deg(omega). + */ + deg_omega = 0; + for (i = 0; i < NN-KK;i++){ + tmp = 0; + j = (deg_lambda < i) ? deg_lambda : i; + for(;j >= 0; j--){ + if ((s[i + 1 - j] != A0) && (lambda[j] != A0)) + tmp ^= Alpha_to[modnn(s[i + 1 - j] + lambda[j])]; + } + if(tmp != 0) + deg_omega = i; + omega[i] = Index_of[tmp]; + } + omega[NN-KK] = A0; + + /* + * Compute error values in poly-form. num1 = omega(inv(X(l))), num2 = + * inv(X(l))**(B0-1) and den = lambda_pr(inv(X(l))) all in poly-form + */ + for (j = count-1; j >=0; j--) { + num1 = 0; + for (i = deg_omega; i >= 0; i--) { + if (omega[i] != A0) + num1 ^= Alpha_to[modnn(omega[i] + i * root[j])]; + } + num2 = Alpha_to[modnn(root[j] * (B0 - 1) + NN)]; + den = 0; + + /* lambda[i+1] for i even is the formal derivative lambda_pr of lambda[i] */ + for (i = min(deg_lambda,NN-KK-1) & ~1; i >= 0; i -=2) { + if(lambda[i+1] != A0) + den ^= Alpha_to[modnn(lambda[i+1] + i * root[j])]; + } + if (den == 0) { +#ifdef ECC_DEBUG + printf("\n ERROR: denominator = 0\n"); +#endif + /* Convert to dual- basis */ + count = -1; + goto finish; + } + /* Apply error to data */ + if (num1 != 0) { + eras_val[j] = Alpha_to[modnn(Index_of[num1] + Index_of[num2] + NN - Index_of[den])]; + } else { + eras_val[j] = 0; + } + } + finish: + for(i=0;i> 2) | ((ecc1[2] & 0x0f) << 6); + bb[2] = ((ecc1[2] & 0xf0) >> 4) | ((ecc1[3] & 0x3f) << 4); + bb[3] = ((ecc1[3] & 0xc0) >> 6) | ((ecc1[0] & 0xff) << 2); + + nb_errors = eras_dec_rs(Alpha_to, Index_of, bb, + error_val, error_pos, 0); + if (nb_errors <= 0) + goto the_end; + + /* correct the errors */ + for(i=0;i= NB_DATA && pos < KK) { + nb_errors = -1; + goto the_end; + } + if (pos < NB_DATA) { + /* extract bit position (MSB first) */ + pos = 10 * (NB_DATA - 1 - pos) - 6; + /* now correct the following 10 bits. At most two bytes + can be modified since pos is even */ + index = (pos >> 3) ^ 1; + bitpos = pos & 7; + if ((index >= 0 && index < SECTOR_SIZE) || + index == (SECTOR_SIZE + 1)) { + val = error_val[i] >> (2 + bitpos); + parity ^= val; + if (index < SECTOR_SIZE) + sector[index] ^= val; + } + index = ((pos >> 3) + 1) ^ 1; + bitpos = (bitpos + 10) & 7; + if (bitpos == 0) + bitpos = 8; + if ((index >= 0 && index < SECTOR_SIZE) || + index == (SECTOR_SIZE + 1)) { + val = error_val[i] << (8 - bitpos); + parity ^= val; + if (index < SECTOR_SIZE) + sector[index] ^= val; + } + } + } + + /* use parity to test extra errors */ + if ((parity & 0xff) != 0) + nb_errors = -1; + + the_end: + free(Alpha_to); + free(Index_of); + return nb_errors; +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_DOC) */ diff --git a/common/env_common.c b/common/env_common.c new file mode 100644 index 0000000..3201135 --- /dev/null +++ b/common/env_common.c @@ -0,0 +1,309 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#ifdef CONFIG_AMIGAONEG3SE + extern void enable_nvram(void); + extern void disable_nvram(void); +#endif + +#undef DEBUG_ENV +#ifdef DEBUG_ENV +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif + +extern env_t *env_ptr; + +extern void env_relocate_spec (void); +extern uchar env_get_char_spec(int); + +static uchar env_get_char_init (int index); +uchar (*env_get_char)(int) = env_get_char_init; + +/************************************************************************ + * Default settings to be used when no valid environment is found + */ +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +uchar default_environment[] = { +#ifdef CONFIG_BOOTARGS + "bootargs=" CONFIG_BOOTARGS "\0" +#endif +#ifdef CONFIG_BOOTCOMMAND + "bootcmd=" CONFIG_BOOTCOMMAND "\0" +#endif +#ifdef CONFIG_RAMBOOTCOMMAND + "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" +#endif +#ifdef CONFIG_NFSBOOTCOMMAND + "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0" +#endif +#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) + "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" +#endif +#ifdef CONFIG_LOADS_ECHO + "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0" +#endif +#ifdef CONFIG_ETHADDR + "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0" +#endif +#ifdef CONFIG_ETH1ADDR + "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0" +#endif +#ifdef CONFIG_ETH2ADDR + "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0" +#endif +#ifdef CONFIG_ETH3ADDR + "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0" +#endif +#ifdef CONFIG_IPADDR + "ipaddr=" MK_STR(CONFIG_IPADDR) "\0" +#endif +#ifdef CONFIG_SERVERIP + "serverip=" MK_STR(CONFIG_SERVERIP) "\0" +#endif +#ifdef CFG_AUTOLOAD + "autoload=" CFG_AUTOLOAD "\0" +#endif +#ifdef CONFIG_PREBOOT + "preboot=" CONFIG_PREBOOT "\0" +#endif +#ifdef CONFIG_ROOTPATH + "rootpath=" MK_STR(CONFIG_ROOTPATH) "\0" +#endif +#ifdef CONFIG_GATEWAYIP + "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0" +#endif +#ifdef CONFIG_NETMASK + "netmask=" MK_STR(CONFIG_NETMASK) "\0" +#endif +#ifdef CONFIG_HOSTNAME + "hostname=" MK_STR(CONFIG_HOSTNAME) "\0" +#endif +#ifdef CONFIG_BOOTFILE + "bootfile=" MK_STR(CONFIG_BOOTFILE) "\0" +#endif +#ifdef CONFIG_LOADADDR + "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0" +#endif +#ifdef CONFIG_CLOCKS_IN_MHZ + "clocks_in_mhz=1\0" +#endif +#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) + "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0" +#endif +#ifdef CONFIG_EXTRA_ENV_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS +#endif + "\0" +}; + +#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ +int default_environment_size = sizeof(default_environment); +#endif + +void env_crc_update (void) +{ + env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); +} + +static uchar env_get_char_init (int index) +{ + DECLARE_GLOBAL_DATA_PTR; + uchar c; + + /* if crc was bad, use the default environment */ + if (gd->env_valid) + { + c = env_get_char_spec(index); + } else { + c = default_environment[index]; + } + + return (c); +} + +#ifdef CONFIG_AMIGAONEG3SE +uchar env_get_char_memory (int index) +{ + DECLARE_GLOBAL_DATA_PTR; + uchar retval; + enable_nvram(); + if (gd->env_valid) { + retval = ( *((uchar *)(gd->env_addr + index)) ); + } else { + retval = ( default_environment[index] ); + } + disable_nvram(); + return retval; +} +#else +uchar env_get_char_memory (int index) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->env_valid) { + return ( *((uchar *)(gd->env_addr + index)) ); + } else { + return ( default_environment[index] ); + } +} +#endif + +uchar *env_get_addr (int index) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->env_valid) { + return ( ((uchar *)(gd->env_addr + index)) ); + } else { + return (&default_environment[index]); + } +} + +void env_relocate (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__, + gd->reloc_off); + +#ifdef CONFIG_AMIGAONEG3SE + enable_nvram(); +#endif + +#ifdef ENV_IS_EMBEDDED + /* + * The environment buffer is embedded with the text segment, + * just relocate the environment pointer + */ + env_ptr = (env_t *)((ulong)env_ptr + gd->reloc_off); + DEBUGF ("%s[%d] embedded ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); +#else + /* + * We must allocate a buffer for the environment + */ + env_ptr = (env_t *)malloc (CFG_ENV_SIZE); + DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); +#endif + + /* + * After relocation to RAM, we can always use the "memory" functions + */ + env_get_char = env_get_char_memory; + + if (gd->env_valid == 0) { +#if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */ + puts ("Using default environment\n\n"); +#else + puts ("*** Warning - bad CRC, using default environment\n\n"); + SHOW_BOOT_PROGRESS (-1); +#endif + + if (sizeof(default_environment) > ENV_SIZE) + { + puts ("*** Error - default environment is too large\n\n"); + return; + } + + memset (env_ptr, 0, sizeof(env_t)); + memcpy (env_ptr->data, + default_environment, + sizeof(default_environment)); +#ifdef CFG_REDUNDAND_ENVIRONMENT + env_ptr->flags = 0xFF; +#endif + env_crc_update (); + gd->env_valid = 1; + } + else { + env_relocate_spec (); + } + gd->env_addr = (ulong)&(env_ptr->data); + +#ifdef CONFIG_AMIGAONEG3SE + disable_nvram(); +#endif +} + +#ifdef CONFIG_AUTO_COMPLETE +int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf) +{ + int i, nxt, len, vallen, found; + const char *lval, *rval; + + found = 0; + cmdv[0] = NULL; + + len = strlen(var); + /* now iterate over the variables and select those that match */ + for (i=0; env_get_char(i) != '\0'; i=nxt+1) { + + for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) + ; + + lval = (char *)env_get_addr(i); + rval = strchr(lval, '='); + if (rval != NULL) { + vallen = rval - lval; + rval++; + } else + vallen = strlen(lval); + + if (len > 0 && (vallen < len || memcmp(lval, var, len) != 0)) + continue; + + if (found >= maxv - 2 || bufsz < vallen + 1) { + cmdv[found++] = "..."; + break; + } + cmdv[found++] = buf; + memcpy(buf, lval, vallen); buf += vallen; bufsz -= vallen; + *buf++ = '\0'; bufsz--; + } + + cmdv[found] = NULL; + return found; +} +#endif diff --git a/common/env_dataflash.c b/common/env_dataflash.c new file mode 100644 index 0000000..8834da0 --- /dev/null +++ b/common/env_dataflash.c @@ -0,0 +1,103 @@ +/* LowLevel function for DataFlash environment support + * Author : Gilles Gastaldi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include + +#if defined(CFG_ENV_IS_IN_DATAFLASH) /* Environment is in DataFlash */ + +#include +#include +#include +#include + +env_t *env_ptr = NULL; + +char * env_name_spec = "dataflash"; + +extern int read_dataflash (unsigned long addr, unsigned long size, char +*result); +extern int write_dataflash (unsigned long addr_dest, unsigned long addr_src, + unsigned long size); +extern int AT91F_DataflashInit (void); +extern uchar default_environment[]; +/* extern int default_environment_size; */ + + +uchar env_get_char_spec (int index) +{ + uchar c; + read_dataflash (CFG_ENV_ADDR+index+offsetof(env_t,data),1,&c); + return (c); +} + +void env_relocate_spec (void) +{ + read_dataflash (CFG_ENV_ADDR,CFG_ENV_SIZE,(uchar *)env_ptr); +} + +int saveenv(void) +{ +/* env must be copied to do not alter env structure in memory*/ +unsigned char temp[CFG_ENV_SIZE]; +int i; + memcpy(temp, env_ptr, CFG_ENV_SIZE); + return write_dataflash (CFG_ENV_ADDR, (unsigned long)temp, CFG_ENV_SIZE); +} + +/************************************************************************ + * Initialize Environment use + * + * We are still running from ROM, so data use is limited + * Use a (moderately small) buffer on the stack + */ +int env_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong crc, len, new; + unsigned off; + uchar buf[64]; + if (gd->env_valid == 0){ + AT91F_DataflashInit(); /* prepare for DATAFLASH read/write */ + + /* read old CRC */ + read_dataflash (CFG_ENV_ADDR+offsetof(env_t,crc),sizeof(ulong),&crc); + new = 0; + len = ENV_SIZE; + off = offsetof(env_t,data); + while (len > 0) { + int n = (len > sizeof(buf)) ? sizeof(buf) : len; + read_dataflash (CFG_ENV_ADDR+off,n , buf); + new = crc32 (new, buf, n); + len -= n; + off += n; + } + if (crc == new) { + gd->env_addr = offsetof(env_t,data); + gd->env_valid = 1; + } else { + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 0; + } + } + + return (0); +} + +#endif /* CFG_ENV_IS_IN_DATAFLASH */ diff --git a/common/env_eeprom.c b/common/env_eeprom.c new file mode 100644 index 0000000..50c623e --- /dev/null +++ b/common/env_eeprom.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CFG_ENV_IS_IN_EEPROM) /* Environment is in EEPROM */ + +#include +#include +#include + +env_t *env_ptr = NULL; + +char * env_name_spec = "EEPROM"; + +extern uchar (*env_get_char)(int); +extern uchar env_get_char_memory (int index); + + +uchar env_get_char_spec (int index) +{ + uchar c; + + eeprom_read (CFG_DEF_EEPROM_ADDR, + CFG_ENV_OFFSET+index+offsetof(env_t,data), + &c, 1); + + return (c); +} + +void env_relocate_spec (void) +{ + eeprom_read (CFG_DEF_EEPROM_ADDR, + CFG_ENV_OFFSET, + (uchar*)env_ptr, + CFG_ENV_SIZE); +} + +int saveenv(void) +{ + return eeprom_write (CFG_DEF_EEPROM_ADDR, + CFG_ENV_OFFSET, + (uchar *)env_ptr, + CFG_ENV_SIZE); +} + +/************************************************************************ + * Initialize Environment use + * + * We are still running from ROM, so data use is limited + * Use a (moderately small) buffer on the stack + */ +int env_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong crc, len, new; + unsigned off; + uchar buf[64]; + + eeprom_init (); /* prepare for EEPROM read/write */ + + /* read old CRC */ + eeprom_read (CFG_DEF_EEPROM_ADDR, + CFG_ENV_OFFSET+offsetof(env_t,crc), + (uchar *)&crc, sizeof(ulong)); + + new = 0; + len = ENV_SIZE; + off = offsetof(env_t,data); + while (len > 0) { + int n = (len > sizeof(buf)) ? sizeof(buf) : len; + + eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, buf, n); + new = crc32 (new, buf, n); + len -= n; + off += n; + } + + if (crc == new) { + gd->env_addr = offsetof(env_t,data); + gd->env_valid = 1; + } else { + gd->env_addr = 0; + gd->env_valid = 0; + } + + return (0); +} + +#endif /* CFG_ENV_IS_IN_EEPROM */ diff --git a/common/env_flash.c b/common/env_flash.c new file mode 100644 index 0000000..a2ea9c4 --- /dev/null +++ b/common/env_flash.c @@ -0,0 +1,407 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include + +#if defined(CFG_ENV_IS_IN_FLASH) /* Environment is in Flash */ + +#include +#include +#include +#include + +#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH)) +#define CMD_SAVEENV +#elif defined(CFG_ENV_ADDR_REDUND) +#error Cannot use CFG_ENV_ADDR_REDUND without CFG_CMD_ENV & CFG_CMD_FLASH +#endif + +#if defined(CFG_ENV_SIZE_REDUND) && (CFG_ENV_SIZE_REDUND < CFG_ENV_SIZE) +#error CFG_ENV_SIZE_REDUND should not be less then CFG_ENV_SIZE +#endif + +#ifdef CONFIG_INFERNO +# ifdef CFG_ENV_ADDR_REDUND +#error CFG_ENV_ADDR_REDUND is not implemented for CONFIG_INFERNO +# endif +#endif + +char * env_name_spec = "Flash"; + +#ifdef ENV_IS_EMBEDDED + +extern uchar environment[]; +env_t *env_ptr = (env_t *)(&environment[0]); + +#ifdef CMD_SAVEENV +/* static env_t *flash_addr = (env_t *)(&environment[0]);-broken on ARM-wd-*/ +static env_t *flash_addr = (env_t *)CFG_ENV_ADDR; +#endif + +#else /* ! ENV_IS_EMBEDDED */ + +env_t *env_ptr = (env_t *)CFG_ENV_ADDR; +#ifdef CMD_SAVEENV +static env_t *flash_addr = (env_t *)CFG_ENV_ADDR; +#endif + +#endif /* ENV_IS_EMBEDDED */ + +#ifdef CFG_ENV_ADDR_REDUND +static env_t *flash_addr_new = (env_t *)CFG_ENV_ADDR_REDUND; + +/* CFG_ENV_ADDR is supposed to be on sector boundary */ +static ulong end_addr = CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1; +static ulong end_addr_new = CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1; + +#define ACTIVE_FLAG 1 +#define OBSOLETE_FLAG 0 +#endif /* CFG_ENV_ADDR_REDUND */ + +extern uchar default_environment[]; +extern int default_environment_size; + + +uchar env_get_char_spec (int index) +{ + DECLARE_GLOBAL_DATA_PTR; + + return ( *((uchar *)(gd->env_addr + index)) ); +} + +#ifdef CFG_ENV_ADDR_REDUND + +int env_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + int crc1_ok = 0, crc2_ok = 0; + + uchar flag1 = flash_addr->flags; + uchar flag2 = flash_addr_new->flags; + + ulong addr_default = (ulong)&default_environment[0]; + ulong addr1 = (ulong)&(flash_addr->data); + ulong addr2 = (ulong)&(flash_addr_new->data); + +#ifdef CONFIG_OMAP2420H4 + int flash_probe(void); + + if(flash_probe() == 0) + goto bad_flash; +#endif + + crc1_ok = (crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc); + crc2_ok = (crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc); + + if (crc1_ok && ! crc2_ok) { + gd->env_addr = addr1; + gd->env_valid = 1; + } else if (! crc1_ok && crc2_ok) { + gd->env_addr = addr2; + gd->env_valid = 1; + } else if (! crc1_ok && ! crc2_ok) { + gd->env_addr = addr_default; + gd->env_valid = 0; + } else if (flag1 == ACTIVE_FLAG && flag2 == OBSOLETE_FLAG) { + gd->env_addr = addr1; + gd->env_valid = 1; + } else if (flag1 == OBSOLETE_FLAG && flag2 == ACTIVE_FLAG) { + gd->env_addr = addr2; + gd->env_valid = 1; + } else if (flag1 == flag2) { + gd->env_addr = addr1; + gd->env_valid = 2; + } else if (flag1 == 0xFF) { + gd->env_addr = addr1; + gd->env_valid = 2; + } else if (flag2 == 0xFF) { + gd->env_addr = addr2; + gd->env_valid = 2; + } + +#ifdef CONFIG_OMAP2420H4 +bad_flash: +#endif + return (0); +} + +#ifdef CMD_SAVEENV +int saveenv(void) +{ + char *saved_data = NULL; + int rc = 1; + char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG; +#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE + ulong up_data = 0; +#endif + + debug ("Protect off %08lX ... %08lX\n", + (ulong)flash_addr, end_addr); + + if (flash_sect_protect (0, (ulong)flash_addr, end_addr)) { + goto Done; + } + + debug ("Protect off %08lX ... %08lX\n", + (ulong)flash_addr_new, end_addr_new); + + if (flash_sect_protect (0, (ulong)flash_addr_new, end_addr_new)) { + goto Done; + } + +#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE + up_data = (end_addr_new + 1 - ((long)flash_addr_new + CFG_ENV_SIZE)); + debug ("Data to save 0x%x\n", up_data); + if (up_data) { + if ((saved_data = malloc(up_data)) == NULL) { + printf("Unable to save the rest of sector (%ld)\n", + up_data); + goto Done; + } + memcpy(saved_data, + (void *)((long)flash_addr_new + CFG_ENV_SIZE), up_data); + debug ("Data (start 0x%x, len 0x%x) saved at 0x%x\n", + (long)flash_addr_new + CFG_ENV_SIZE, + up_data, saved_data); + } +#endif + puts ("Erasing Flash..."); + debug (" %08lX ... %08lX ...", + (ulong)flash_addr_new, end_addr_new); + + if (flash_sect_erase ((ulong)flash_addr_new, end_addr_new)) { + goto Done; + } + + puts ("Writing to Flash... "); + debug (" %08lX ... %08lX ...", + (ulong)&(flash_addr_new->data), + sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data)); + if ((rc = flash_write((char *)env_ptr->data, + (ulong)&(flash_addr_new->data), + sizeof(env_ptr->data))) || + (rc = flash_write((char *)&(env_ptr->crc), + (ulong)&(flash_addr_new->crc), + sizeof(env_ptr->crc))) || + (rc = flash_write(&flag, + (ulong)&(flash_addr->flags), + sizeof(flash_addr->flags))) || + (rc = flash_write(&new_flag, + (ulong)&(flash_addr_new->flags), + sizeof(flash_addr_new->flags)))) + { + flash_perror (rc); + goto Done; + } + puts ("done\n"); + +#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE + if (up_data) { /* restore the rest of sector */ + debug ("Restoring the rest of data to 0x%x len 0x%x\n", + (long)flash_addr_new + CFG_ENV_SIZE, up_data); + if (flash_write(saved_data, + (long)flash_addr_new + CFG_ENV_SIZE, + up_data)) { + flash_perror(rc); + goto Done; + } + } +#endif + { + env_t * etmp = flash_addr; + ulong ltmp = end_addr; + + flash_addr = flash_addr_new; + flash_addr_new = etmp; + + end_addr = end_addr_new; + end_addr_new = ltmp; + } + + rc = 0; +Done: + + if (saved_data) + free (saved_data); + /* try to re-protect */ + (void) flash_sect_protect (1, (ulong)flash_addr, end_addr); + (void) flash_sect_protect (1, (ulong)flash_addr_new, end_addr_new); + + return rc; +} +#endif /* CMD_SAVEENV */ + +#else /* ! CFG_ENV_ADDR_REDUND */ + +int env_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_OMAP2420H4 + int flash_probe(void); + + if(flash_probe() == 0) + goto bad_flash; +#endif + if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { + gd->env_addr = (ulong)&(env_ptr->data); + gd->env_valid = 1; + return(0); + } +#ifdef CONFIG_OMAP2420H4 +bad_flash: +#endif + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 0; + return (0); +} + +#ifdef CMD_SAVEENV + +int saveenv(void) +{ + int len, rc; + ulong end_addr; + ulong flash_sect_addr; +#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) + ulong flash_offset; + uchar env_buffer[CFG_ENV_SECT_SIZE]; +#else + uchar *env_buffer = (uchar *)env_ptr; +#endif /* CFG_ENV_SECT_SIZE */ + int rcode = 0; + +#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) + + flash_offset = ((ulong)flash_addr) & (CFG_ENV_SECT_SIZE-1); + flash_sect_addr = ((ulong)flash_addr) & ~(CFG_ENV_SECT_SIZE-1); + + debug ( "copy old content: " + "sect_addr: %08lX env_addr: %08lX offset: %08lX\n", + flash_sect_addr, (ulong)flash_addr, flash_offset); + + /* copy old contents to temporary buffer */ + memcpy (env_buffer, (void *)flash_sect_addr, CFG_ENV_SECT_SIZE); + + /* copy current environment to temporary buffer */ + memcpy ((uchar *)((unsigned long)env_buffer + flash_offset), + env_ptr, + CFG_ENV_SIZE); + + len = CFG_ENV_SECT_SIZE; +#else + flash_sect_addr = (ulong)flash_addr; + len = CFG_ENV_SIZE; +#endif /* CFG_ENV_SECT_SIZE */ + +#ifndef CONFIG_INFERNO + end_addr = flash_sect_addr + len - 1; +#else + /* this is the last sector, and the size is hardcoded here */ + /* otherwise we will get stack problems on loading 128 KB environment */ + end_addr = flash_sect_addr + 0x20000 - 1; +#endif + + debug ("Protect off %08lX ... %08lX\n", + (ulong)flash_sect_addr, end_addr); + + if (flash_sect_protect (0, flash_sect_addr, end_addr)) + return 1; + + puts ("Erasing Flash..."); + if (flash_sect_erase (flash_sect_addr, end_addr)) + return 1; + + puts ("Writing to Flash... "); + rc = flash_write((char *)env_buffer, flash_sect_addr, len); + if (rc != 0) { + flash_perror (rc); + rcode = 1; + } else { + puts ("done\n"); + } + + /* try to re-protect */ + (void) flash_sect_protect (1, flash_sect_addr, end_addr); + return rcode; +} + +#endif /* CMD_SAVEENV */ + +#endif /* CFG_ENV_ADDR_REDUND */ + +void env_relocate_spec (void) +{ +#if !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_ADDR_REDUND) +#ifdef CFG_ENV_ADDR_REDUND + DECLARE_GLOBAL_DATA_PTR; + + if (gd->env_addr != (ulong)&(flash_addr->data)) { + env_t * etmp = flash_addr; + ulong ltmp = end_addr; + + flash_addr = flash_addr_new; + flash_addr_new = etmp; + + end_addr = end_addr_new; + end_addr_new = ltmp; + } + + if (flash_addr_new->flags != OBSOLETE_FLAG && + crc32(0, flash_addr_new->data, ENV_SIZE) == + flash_addr_new->crc) { + char flag = OBSOLETE_FLAG; + + gd->env_valid = 2; + flash_sect_protect (0, (ulong)flash_addr_new, end_addr_new); + flash_write(&flag, + (ulong)&(flash_addr_new->flags), + sizeof(flash_addr_new->flags)); + flash_sect_protect (1, (ulong)flash_addr_new, end_addr_new); + } + + if (flash_addr->flags != ACTIVE_FLAG && + (flash_addr->flags & ACTIVE_FLAG) == ACTIVE_FLAG) { + char flag = ACTIVE_FLAG; + + gd->env_valid = 2; + flash_sect_protect (0, (ulong)flash_addr, end_addr); + flash_write(&flag, + (ulong)&(flash_addr->flags), + sizeof(flash_addr->flags)); + flash_sect_protect (1, (ulong)flash_addr, end_addr); + } + + if (gd->env_valid == 2) + puts ("*** Warning - some problems detected " + "reading environment; recovered successfully\n\n"); +#endif /* CFG_ENV_ADDR_REDUND */ + memcpy (env_ptr, (void*)flash_addr, CFG_ENV_SIZE); +#endif /* ! ENV_IS_EMBEDDED || CFG_ENV_ADDR_REDUND */ +} + +#endif /* CFG_ENV_IS_IN_FLASH */ diff --git a/common/env_nand.c b/common/env_nand.c new file mode 100644 index 0000000..60aba1e --- /dev/null +++ b/common/env_nand.c @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2004 + * Jian Zhang, Texas Instruments, jzhang@ti.com. + + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include + +#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ + +#include +#include +#include +#include + +#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_NAND)) == (CFG_CMD_ENV|CFG_CMD_NAND)) +#define CMD_SAVEENV +#endif + +#if defined(CFG_ENV_SIZE_REDUND) +#error CFG_ENV_SIZE_REDUND not supported yet +#endif + +#if defined(CFG_ENV_ADDR_REDUND) +#error CFG_ENV_ADDR_REDUND and CFG_ENV_IS_IN_NAND not supported yet +#endif + + +#ifdef CONFIG_INFERNO +#error CONFIG_INFERNO not supported yet +#endif + +/* references to names in cmd_nand.c */ +#define NANDRW_READ 0x01 +#define NANDRW_WRITE 0x00 +#define NANDRW_JFFS2 0x02 +extern struct nand_chip nand_dev_desc[]; +int nand_rw (struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf); +int nand_erase(struct nand_chip* nand, size_t ofs, + size_t len, int clean); + +/* references to names in env_common.c */ +extern uchar default_environment[]; +extern int default_environment_size; + +char * env_name_spec = "NAND"; + + +#ifdef ENV_IS_EMBEDDED +extern uchar environment[]; +env_t *env_ptr = (env_t *)(&environment[0]); +#else /* ! ENV_IS_EMBEDDED */ +env_t *env_ptr = 0; +#endif /* ENV_IS_EMBEDDED */ + + +/* local functions */ +static void use_default(void); + + +uchar env_get_char_spec (int index) +{ + DECLARE_GLOBAL_DATA_PTR; + + return ( *((uchar *)(gd->env_addr + index)) ); +} + + +/* this is called before nand_init() + * so we can't read Nand to validate env data. + * Mark it OK for now. env_relocate() in env_common.c + * will call our relocate function which will does + * the real validation. + */ +int env_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 1; + + return (0); +} + +#ifdef CMD_SAVEENV +int saveenv(void) +{ + int total, ret = 0; + puts ("Erasing Nand..."); + if (nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SIZE, 0)) + return 1; + + puts ("Writing to Nand... "); + ret = nand_rw(nand_dev_desc + 0, + NANDRW_WRITE | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE, + &total, (u_char*)env_ptr); + if (ret || total != CFG_ENV_SIZE) + return 1; + + puts ("done\n"); + return ret; +} +#endif /* CMD_SAVEENV */ + + +void env_relocate_spec (void) +{ +#if !defined(ENV_IS_EMBEDDED) + int ret, total; + + ret = nand_rw(nand_dev_desc + 0, + NANDRW_READ | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE, + &total, (u_char*)env_ptr); + if (ret || total != CFG_ENV_SIZE) + return use_default(); + + if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) + return use_default(); +#endif /* ! ENV_IS_EMBEDDED */ + +} + +static void use_default() +{ + DECLARE_GLOBAL_DATA_PTR; + + puts ("*** Warning - bad CRC or NAND, using default environment\n\n"); + + if (default_environment_size > CFG_ENV_SIZE){ + puts ("*** Error - default environment is too large\n\n"); + return; + } + + memset (env_ptr, 0, sizeof(env_t)); + memcpy (env_ptr->data, + default_environment, + default_environment_size); + env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); + gd->env_valid = 1; + +} + +#endif /* CFG_ENV_IS_IN_NAND */ diff --git a/common/env_nowhere.c b/common/env_nowhere.c new file mode 100644 index 0000000..ee4237c --- /dev/null +++ b/common/env_nowhere.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CFG_ENV_IS_NOWHERE) /* Environment is nowhere */ + +#include +#include +#include + +env_t *env_ptr = NULL; + +extern uchar default_environment[]; +extern int default_environment_size; + + +void env_relocate_spec (void) +{ +} + +uchar env_get_char_spec (int index) +{ + DECLARE_GLOBAL_DATA_PTR; + + return ( *((uchar *)(gd->env_addr + index)) ); +} + +/************************************************************************ + * Initialize Environment use + * + * We are still running from ROM, so data use is limited + */ +int env_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 0; + + return (0); +} + +#endif /* CFG_ENV_IS_NOWHERE) */ diff --git a/common/env_nvram.c b/common/env_nvram.c new file mode 100644 index 0000000..a406e42 --- /dev/null +++ b/common/env_nvram.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 09-18-2001 Andreas Heppel, Sysgo RTS GmbH + * + * It might not be possible in all cases to use 'memcpy()' to copy + * the environment to NVRAM, as the NVRAM might not be mapped into + * the memory space. (I.e. this is the case for the BAB750). In those + * cases it might be possible to access the NVRAM using a different + * method. For example, the RTC on the BAB750 is accessible in IO + * space using its address and data registers. To enable usage of + * NVRAM in those cases I invented the functions 'nvram_read()' and + * 'nvram_write()', which will be activated upon the configuration + * #define CFG_NVRAM_ACCESS_ROUTINE. Note, that those functions are + * strongly dependent on the used HW, and must be redefined for each + * board that wants to use them. + */ + +#include + +#ifdef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */ + +#include +#include +#include + +#ifdef CFG_NVRAM_ACCESS_ROUTINE +extern void *nvram_read(void *dest, const long src, size_t count); +extern void nvram_write(long dest, const void *src, size_t count); +env_t *env_ptr = NULL; +#else +env_t *env_ptr = (env_t *)CFG_ENV_ADDR; +#endif + +char * env_name_spec = "NVRAM"; + +extern uchar default_environment[]; +extern int default_environment_size; + +extern uchar (*env_get_char)(int); +extern uchar env_get_char_memory (int index); + +#ifdef CONFIG_AMIGAONEG3SE +uchar env_get_char_spec (int index) +{ +#ifdef CFG_NVRAM_ACCESS_ROUTINE + uchar c; + + nvram_read(&c, CFG_ENV_ADDR+index, 1); + + return c; +#else + DECLARE_GLOBAL_DATA_PTR; + uchar retval; + enable_nvram(); + retval = *((uchar *)(gd->env_addr + index)); + disable_nvram(); + return retval; +#endif +} +#else +uchar env_get_char_spec (int index) +{ +#ifdef CFG_NVRAM_ACCESS_ROUTINE + uchar c; + + nvram_read(&c, CFG_ENV_ADDR+index, 1); + + return c; +#else + DECLARE_GLOBAL_DATA_PTR; + + return *((uchar *)(gd->env_addr + index)); +#endif +} +#endif + +void env_relocate_spec (void) +{ +#if defined(CFG_NVRAM_ACCESS_ROUTINE) + nvram_read(env_ptr, CFG_ENV_ADDR, CFG_ENV_SIZE); +#else + memcpy (env_ptr, (void*)CFG_ENV_ADDR, CFG_ENV_SIZE); +#endif +} + +int saveenv (void) +{ + int rcode = 0; +#ifdef CONFIG_AMIGAONEG3SE + enable_nvram(); +#endif +#ifdef CFG_NVRAM_ACCESS_ROUTINE + nvram_write(CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE); +#else + if (memcpy ((char *)CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE) == NULL) + rcode = 1 ; +#endif +#ifdef CONFIG_AMIGAONEG3SE + udelay(10000); + disable_nvram(); +#endif + return rcode; +} + + +/************************************************************************ + * Initialize Environment use + * + * We are still running from ROM, so data use is limited + */ +int env_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_AMIGAONEG3SE + enable_nvram(); +#endif +#if defined(CFG_NVRAM_ACCESS_ROUTINE) + ulong crc; + uchar data[ENV_SIZE]; + nvram_read (&crc, CFG_ENV_ADDR, sizeof(ulong)); + nvram_read (data, CFG_ENV_ADDR+sizeof(ulong), ENV_SIZE); + + if (crc32(0, data, ENV_SIZE) == crc) { + gd->env_addr = (ulong)CFG_ENV_ADDR + sizeof(long); +#else + if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { + gd->env_addr = (ulong)&(env_ptr->data); +#endif + gd->env_valid = 1; + } else { + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 0; + } +#ifdef CONFIG_AMIGAONEG3SE + disable_nvram(); +#endif + return (0); +} + +#endif /* CFG_ENV_IS_IN_NVRAM */ diff --git a/common/environment.c b/common/environment.c new file mode 100644 index 0000000..c7f54c6 --- /dev/null +++ b/common/environment.c @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ /* Dirty trick to get only #defines */ +#endif +#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */ +#include +#undef __ASSEMBLY__ +#include + +/* + * Handle HOSTS that have prepended + * crap on symbol names, not TARGETS. + */ +#if defined(__APPLE__) +/* Leading underscore on symbols */ +# define SYM_CHAR "_" +#else /* No leading character on symbols */ +# define SYM_CHAR +#endif + +/* + * Generate embedded environment table + * inside U-Boot image, if needed. + */ +#if defined(ENV_IS_EMBEDDED) +/* + * Only put the environment in it's own section when we are building + * U-Boot proper. The host based program "tools/envcrc" does not need + * a seperate section. Note that ENV_CRC is only defined when building + * U-Boot itself. + */ +#if (defined(CONFIG_CMI) || \ + defined(CONFIG_FADS) || \ + defined(CONFIG_HYMOD) || \ + defined(CONFIG_ICU862) || \ + defined(CONFIG_R360MPI) || \ + defined(CONFIG_TQM8xxL) || \ + defined(CONFIG_RRVISION) || \ + defined(CONFIG_TRAB) || \ + defined(CONFIG_PPCHAMELEONEVB) ) && \ + defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */ +/* XXX - This only works with GNU C */ +# define __PPCENV__ __attribute__ ((section(".ppcenv"))) +# define __PPCTEXT__ __attribute__ ((section(".text"))) + +#elif defined(USE_HOSTCC) /* Native for 'tools/envcrc' */ +# define __PPCENV__ /*XXX DO_NOT_DEL_THIS_COMMENT*/ +# define __PPCTEXT__ /*XXX DO_NOT_DEL_THIS_COMMENT*/ + +#else /* Environment is embedded in U-Boot's .text section */ +/* XXX - This only works with GNU C */ +# define __PPCENV__ __attribute__ ((section(".text"))) +# define __PPCTEXT__ __attribute__ ((section(".text"))) +#endif + +/* + * Macros to generate global absolutes. + */ +#define GEN_SYMNAME(str) SYM_CHAR #str +#define GEN_VALUE(str) #str +#define GEN_ABS(name, value) \ + asm (".globl " GEN_SYMNAME(name)); \ + asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) + +/* + * Macros to transform values + * into environment strings. + */ +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +/* + * Check to see if we are building with a + * computed CRC. Otherwise define it as ~0. + */ +#if !defined(ENV_CRC) +# define ENV_CRC ~0 +#endif + +env_t environment __PPCENV__ = { + ENV_CRC, /* CRC Sum */ +#ifdef CFG_REDUNDAND_ENVIRONMENT + 1, /* Flags: valid */ +#endif + { +#if defined(CONFIG_BOOTARGS) + "bootargs=" CONFIG_BOOTARGS "\0" +#endif +#if defined(CONFIG_BOOTCOMMAND) + "bootcmd=" CONFIG_BOOTCOMMAND "\0" +#endif +#if defined(CONFIG_RAMBOOTCOMMAND) + "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_NFSBOOTCOMMAND) + "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0" +#endif +#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) + "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" +#endif +#ifdef CONFIG_LOADS_ECHO + "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0" +#endif +#ifdef CONFIG_ETHADDR + "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0" +#endif +#ifdef CONFIG_ETH1ADDR + "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0" +#endif +#ifdef CONFIG_ETH2ADDR + "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0" +#endif +#ifdef CONFIG_ETH3ADDR + "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0" +#endif +#ifdef CONFIG_ETHPRIME + "ethprime=" CONFIG_ETHPRIME "\0" +#endif +#ifdef CONFIG_IPADDR + "ipaddr=" MK_STR(CONFIG_IPADDR) "\0" +#endif +#ifdef CONFIG_SERVERIP + "serverip=" MK_STR(CONFIG_SERVERIP) "\0" +#endif +#ifdef CFG_AUTOLOAD + "autoload=" CFG_AUTOLOAD "\0" +#endif +#ifdef CONFIG_ROOTPATH + "rootpath=" MK_STR(CONFIG_ROOTPATH) "\0" +#endif +#ifdef CONFIG_GATEWAYIP + "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0" +#endif +#ifdef CONFIG_NETMASK + "netmask=" MK_STR(CONFIG_NETMASK) "\0" +#endif +#ifdef CONFIG_HOSTNAME + "hostname=" MK_STR(CONFIG_HOSTNAME) "\0" +#endif +#ifdef CONFIG_BOOTFILE + "bootfile=" MK_STR(CONFIG_BOOTFILE) "\0" +#endif +#ifdef CONFIG_LOADADDR + "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0" +#endif +#ifdef CONFIG_PREBOOT + "preboot=" CONFIG_PREBOOT "\0" +#endif +#ifdef CONFIG_CLOCKS_IN_MHZ + "clocks_in_mhz=" "1" "\0" +#endif +#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) + "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0" +#endif +#ifdef CONFIG_EXTRA_ENV_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS +#endif + "\0" /* Term. env_t.data with 2 NULs */ + } +}; +#ifdef CFG_ENV_ADDR_REDUND +env_t redundand_environment __PPCENV__ = { + 0, /* CRC Sum: invalid */ + 0, /* Flags: invalid */ + { + "\0" + } +}; +#endif /* CFG_ENV_ADDR_REDUND */ + +/* + * These will end up in the .text section + * if the environment strings are embedded + * in the image. When this is used for + * tools/envcrc, they are placed in the + * .data/.sdata section. + * + */ +unsigned long env_size __PPCTEXT__ = sizeof(env_t); + +/* + * Add in absolutes. + */ +GEN_ABS(env_offset, CFG_ENV_OFFSET); + +#endif /* ENV_IS_EMBEDDED */ diff --git a/common/exports.c b/common/exports.c new file mode 100644 index 0000000..9858217 --- /dev/null +++ b/common/exports.c @@ -0,0 +1,35 @@ +#include +#include + +static void dummy(void) +{ +} + +unsigned long get_version(void) +{ + return XF_VERSION; +} + +void jumptable_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + int i; + + gd->jt = (void **) malloc (XF_MAX * sizeof (void *)); + for (i = 0; i < XF_MAX; i++) + gd->jt[i] = (void *) dummy; + + gd->jt[XF_get_version] = (void *) get_version; + gd->jt[XF_malloc] = (void *) malloc; + gd->jt[XF_free] = (void *) free; + gd->jt[XF_get_timer] = (void *)get_timer; + gd->jt[XF_udelay] = (void *)udelay; +#if defined(CONFIG_I386) || defined(CONFIG_PPC) + gd->jt[XF_install_hdlr] = (void *) irq_install_handler; + gd->jt[XF_free_hdlr] = (void *) irq_free_handler; +#endif /* I386 || PPC */ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) + gd->jt[XF_i2c_write] = (void *) i2c_write; + gd->jt[XF_i2c_read] = (void *) i2c_read; +#endif /* CFG_CMD_I2C */ +} diff --git a/common/flash.c b/common/flash.c new file mode 100644 index 0000000..a64bc98 --- /dev/null +++ b/common/flash.c @@ -0,0 +1,228 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include + +#if !defined(CFG_NO_FLASH) + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +/*----------------------------------------------------------------------- + * Set protection status for monitor sectors + * + * The monitor is always located in the _first_ Flash bank. + * If necessary you have to map the second bank at lower addresses. + */ +void +flash_protect (int flag, ulong from, ulong to, flash_info_t *info) +{ + ulong b_end = info->start[0] + info->size - 1; /* bank end address */ + short s_end = info->sector_count - 1; /* index of last sector */ + int i; + + debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n", + (flag & FLAG_PROTECT_SET) ? "ON" : + (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???", + from, to); + + /* Do nothing if input data is bad. */ + if (info->sector_count == 0 || info->size == 0 || to < from) { + return; + } + + /* There is nothing to do if we have no data about the flash + * or the protect range and flash range don't overlap. + */ + if (info->flash_id == FLASH_UNKNOWN || + to < info->start[0] || from > b_end) { + return; + } + + for (i=0; isector_count; ++i) { + ulong end; /* last address in current sect */ + + end = (i == s_end) ? b_end : info->start[i + 1] - 1; + + /* Update protection if any part of the sector + * is in the specified range. + */ + if (from <= end && to >= info->start[i]) { + if (flag & FLAG_PROTECT_CLEAR) { +#if defined(CFG_FLASH_PROTECTION) + flash_real_protect(info, i, 0); +#else + info->protect[i] = 0; +#endif /* CFG_FLASH_PROTECTION */ + debug ("protect off %d\n", i); + } + else if (flag & FLAG_PROTECT_SET) { +#if defined(CFG_FLASH_PROTECTION) + flash_real_protect(info, i, 1); +#else + info->protect[i] = 1; +#endif /* CFG_FLASH_PROTECTION */ + debug ("protect on %d\n", i); + } + } + } +} + +/*----------------------------------------------------------------------- + */ + +flash_info_t * +addr2info (ulong addr) +{ +#ifndef CONFIG_SPD823TS + flash_info_t *info; + int i; + + for (i=0, info=&flash_info[0]; iflash_id != FLASH_UNKNOWN && + addr >= info->start[0] && + /* WARNING - The '- 1' is needed if the flash + * is at the end of the address space, since + * info->start[0] + info->size wraps back to 0. + * Please don't change this unless you understand this. + */ + addr <= info->start[0] + info->size - 1) { + return (info); + } + } +#endif /* CONFIG_SPD823TS */ + + return (NULL); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + * Make sure all target addresses are within Flash bounds, + * and no protected sectors are hit. + * Returns: + * ERR_OK 0 - OK + * ERR_TIMOUT 1 - write timeout + * ERR_NOT_ERASED 2 - Flash not erased + * ERR_PROTECTED 4 - target range includes protected sectors + * ERR_INVAL 8 - target address not in Flash memory + * ERR_ALIGN 16 - target address not aligned on boundary + * (only some targets require alignment) + */ +int +flash_write (char *src, ulong addr, ulong cnt) +{ +#ifdef CONFIG_SPD823TS + return (ERR_TIMOUT); /* any other error codes are possible as well */ +#else + int i; + ulong end = addr + cnt - 1; + flash_info_t *info_first = addr2info (addr); + flash_info_t *info_last = addr2info (end ); + flash_info_t *info; + + if (cnt == 0) { + return (ERR_OK); + } + + if (!info_first || !info_last) { + return (ERR_INVAL); + } + + for (info = info_first; info <= info_last; ++info) { + ulong b_end = info->start[0] + info->size; /* bank end addr */ + short s_end = info->sector_count - 1; + for (i=0; isector_count; ++i) { + ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; + + if ((end >= info->start[i]) && (addr < e_addr) && + (info->protect[i] != 0) ) { + return (ERR_PROTECTED); + } + } + } + + /* finally write data to flash */ + for (info = info_first; info <= info_last && cnt>0; ++info) { + ulong len; + + len = info->start[0] + info->size - addr; + if (len > cnt) + len = cnt; + if ((i = write_buff(info, (uchar *)src, addr, len)) != 0) { + return (i); + } + cnt -= len; + addr += len; + src += len; + } + return (ERR_OK); +#endif /* CONFIG_SPD823TS */ +} + +/*----------------------------------------------------------------------- + */ + +void flash_perror (int err) +{ + switch (err) { + case ERR_OK: + break; + case ERR_TIMOUT: + puts ("Timeout writing to Flash\n"); + break; + case ERR_NOT_ERASED: + puts ("Flash not Erased\n"); + break; + case ERR_PROTECTED: + puts ("Can't write to protected Flash sectors\n"); + break; + case ERR_INVAL: + puts ("Outside available Flash\n"); + break; + case ERR_ALIGN: + puts ("Start and/or end address not on sector boundary\n"); + break; + case ERR_UNKNOWN_FLASH_VENDOR: + puts ("Unknown Vendor of Flash\n"); + break; + case ERR_UNKNOWN_FLASH_TYPE: + puts ("Unknown Type of Flash\n"); + break; + case ERR_PROG_ERROR: + puts ("General Flash Programming Error\n"); + break; + default: + printf ("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err); + break; + } +} + +/*----------------------------------------------------------------------- + */ +#endif /* !CFG_NO_FLASH */ diff --git a/common/fpga.c b/common/fpga.c new file mode 100644 index 0000000..02d3e42 --- /dev/null +++ b/common/fpga.c @@ -0,0 +1,351 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Generic FPGA support + */ +#include /* core U-Boot definitions */ +#include /* xilinx specific definitions */ +#include /* altera specific definitions */ + +#if defined(CONFIG_FPGA) + +#if 0 +#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */ +#endif + +/* Local definitions */ +#ifndef CONFIG_MAX_FPGA_DEVICES +#define CONFIG_MAX_FPGA_DEVICES 5 +#endif + +/* Enable/Disable debug console messages */ +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* Local static data */ +static ulong relocation_offset = 0; +static int next_desc = FPGA_INVALID_DEVICE; +static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; + +/* Local static functions */ +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum ); +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, + size_t bsize, char *fn ); +static int fpga_dev_info( int devnum ); + + +/* ------------------------------------------------------------------------- */ + +/* fpga_no_sup + * 'no support' message function + */ +static void fpga_no_sup( char *fn, char *msg ) +{ + if ( fn && msg ) { + printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n", + fn, msg, CONFIG_FPGA ); + } else if ( msg ) { + printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n", + msg, CONFIG_FPGA ); + } else { + printf( "No FPGA suport! CONFIG_FPGA defined as 0x%x.\n", + CONFIG_FPGA ); + } +} + + +/* fpga_get_desc + * map a device number to a descriptor + */ +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum ) +{ + fpga_desc *desc = (fpga_desc * )NULL; + + if (( devnum >= 0 ) && (devnum < next_desc )) { + desc = &desc_table[devnum]; + PRINTF( "%s: found fpga descriptor #%d @ 0x%p\n", + __FUNCTION__, devnum, desc ); + } + + return desc; +} + + +/* fpga_validate + * generic parameter checking code + */ +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, + size_t bsize, char *fn ) +{ + fpga_desc * desc = fpga_get_desc( devnum ); + + if ( !desc ) { + printf( "%s: Invalid device number %d\n", fn, devnum ); + } + + if ( !buf ) { + printf( "%s: Null buffer.\n", fn ); + return (fpga_desc * const)NULL; + } + if ( !bsize ) { + printf( "%s: Null buffer size.\n", fn ); + return (fpga_desc * const)NULL; + } + + return desc; +} + + +/* fpga_dev_info + * generic multiplexing code + */ +static int fpga_dev_info( int devnum ) +{ + int ret_val = FPGA_FAIL; /* assume failure */ + const fpga_desc * const desc = fpga_get_desc( devnum ); + + if ( desc ) { + PRINTF( "%s: Device Descriptor @ 0x%p\n", + __FUNCTION__, desc->devdesc ); + + switch ( desc->devtype ) { + case fpga_xilinx: +#if CONFIG_FPGA & CFG_FPGA_XILINX + printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc ); + ret_val = xilinx_info( desc->devdesc ); +#else + fpga_no_sup( __FUNCTION__, "Xilinx devices" ); +#endif + break; + case fpga_altera: +#if CONFIG_FPGA & CFG_FPGA_ALTERA + printf( "Altera Device\nDescriptor @ 0x%p\n", desc ); + ret_val = altera_info( desc->devdesc ); +#else + fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); +#endif + break; + default: + printf( "%s: Invalid or unsupported device type %d\n", + __FUNCTION__, desc->devtype ); + } + } else { + printf( "%s: Invalid device number %d\n", + __FUNCTION__, devnum ); + } + + return ret_val; +} + + +/* fpga_reloc + * generic multiplexing code + */ +int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off ) +{ + int ret_val = FPGA_FAIL; + + PRINTF( "%s: Relocating Device of type %d @ 0x%p with offset %lx\n", + __FUNCTION__, devtype, desc, reloc_off ); + + switch ( devtype ) { + case fpga_xilinx: +#if CONFIG_FPGA & CFG_FPGA_XILINX + ret_val = xilinx_reloc( desc, reloc_off ); +#else + fpga_no_sup( __FUNCTION__, "Xilinx devices" ); +#endif + break; + case fpga_altera: +#if CONFIG_FPGA & CFG_FPGA_ALTERA + ret_val = altera_reloc( desc, reloc_off ); +#else + fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); +#endif + break; + default: + printf( "%s: Invalid or unsupported device type %d\n", + __FUNCTION__, devtype ); + } + + return ret_val; +} + +/* ------------------------------------------------------------------------- */ +/* fgpa_init is usually called from misc_init_r() and MUST be called + * before any of the other fpga functions are used. + */ +void fpga_init( ulong reloc_off ) +{ + relocation_offset = reloc_off; + next_desc = 0; + memset( desc_table, 0, sizeof(desc_table)); + + PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA ); +#if 0 + PRINTF( "%s: CFG_FPGA_XILINX = 0x%x\n", __FUNCTION__, CFG_FPGA_XILINX ); + PRINTF( "%s: CFG_FPGA_ALTERA = 0x%x\n", __FUNCTION__, CFG_FPGA_ALTERA ); +#endif +} + +/* fpga_count + * Basic interface function to get the current number of devices available. + */ +int fpga_count( void ) +{ + return next_desc; +} + +/* fpga_add + * Attempts to relocate the device/board specific interface code + * to the proper RAM locations and adds the device descriptor to + * the device table. + */ +int fpga_add( fpga_type devtype, void *desc ) +{ + int devnum = FPGA_INVALID_DEVICE; + + if ( next_desc < 0 ) { + printf( "%s: FPGA support not initialized!\n", __FUNCTION__ ); + } else if (( devtype > fpga_min_type ) && ( devtype < fpga_undefined )) { + if ( desc ) { + if ( next_desc < CONFIG_MAX_FPGA_DEVICES ) { + if ( fpga_reloc( devtype, desc, relocation_offset ) + == FPGA_SUCCESS ) { + devnum = next_desc; + desc_table[next_desc].devtype = devtype; + desc_table[next_desc++].devdesc = desc; + } else { + printf( "%s: Unable to relocate device interface table!\n", + __FUNCTION__ ); + } + } else { + printf( "%s: Exceeded Max FPGA device count\n", __FUNCTION__ ); + } + } else { + printf( "%s: NULL device descriptor\n", __FUNCTION__ ); + } + } else { + printf( "%s: Unsupported FPGA type %d\n", __FUNCTION__, devtype ); + } + + return devnum; +} + +/* + * Generic multiplexing code + */ +int fpga_load( int devnum, void *buf, size_t bsize ) +{ + int ret_val = FPGA_FAIL; /* assume failure */ + fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); + + if ( desc ) { + switch ( desc->devtype ) { + case fpga_xilinx: +#if CONFIG_FPGA & CFG_FPGA_XILINX + ret_val = xilinx_load( desc->devdesc, buf, bsize ); +#else + fpga_no_sup( __FUNCTION__, "Xilinx devices" ); +#endif + break; + case fpga_altera: +#if CONFIG_FPGA & CFG_FPGA_ALTERA + ret_val = altera_load( desc->devdesc, buf, bsize ); +#else + fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); +#endif + break; + default: + printf( "%s: Invalid or unsupported device type %d\n", + __FUNCTION__, desc->devtype ); + } + } + + return ret_val; +} + +/* fpga_dump + * generic multiplexing code + */ +int fpga_dump( int devnum, void *buf, size_t bsize ) +{ + int ret_val = FPGA_FAIL; /* assume failure */ + fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); + + if ( desc ) { + switch ( desc->devtype ) { + case fpga_xilinx: +#if CONFIG_FPGA & CFG_FPGA_XILINX + ret_val = xilinx_dump( desc->devdesc, buf, bsize ); +#else + fpga_no_sup( __FUNCTION__, "Xilinx devices" ); +#endif + break; + case fpga_altera: +#if CONFIG_FPGA & CFG_FPGA_ALTERA + ret_val = altera_dump( desc->devdesc, buf, bsize ); +#else + fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); +#endif + break; + default: + printf( "%s: Invalid or unsupported device type %d\n", + __FUNCTION__, desc->devtype ); + } + } + + return ret_val; +} + + +/* fpga_info + * front end to fpga_dev_info. If devnum is invalid, report on all + * available devices. + */ +int fpga_info( int devnum ) +{ + if ( devnum == FPGA_INVALID_DEVICE ) { + if ( next_desc > 0 ) { + int dev; + + for ( dev = 0; dev < next_desc; dev++ ) { + fpga_dev_info( dev ); + } + return FPGA_SUCCESS; + } else { + printf( "%s: No FPGA devices available.\n", __FUNCTION__ ); + return FPGA_FAIL; + } + } + else return fpga_dev_info( devnum ); +} + +/* ------------------------------------------------------------------------- */ + +#endif /* CONFIG_FPGA */ diff --git a/common/ft_build.c b/common/ft_build.c new file mode 100644 index 0000000..65a274f --- /dev/null +++ b/common/ft_build.c @@ -0,0 +1,695 @@ +/* + * OF flat tree builder + */ + +#include +#include +#include + +#ifdef CONFIG_OF_FLAT_TREE + +#include +#include + +#include + +/* align addr on a size boundary - adjust address up if needed -- Cort */ +#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1))) + +static void ft_put_word(struct ft_cxt *cxt, u32 v) +{ + if (cxt->overflow) /* do nothing */ + return; + + /* check for overflow */ + if (cxt->p + 4 > cxt->pstr) { + cxt->overflow = 1; + return; + } + + *(u32 *) cxt->p = cpu_to_be32(v); + cxt->p += 4; +} + +static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz) +{ + u8 *p; + + if (cxt->overflow) /* do nothing */ + return; + + /* next pointer pos */ + p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4); + + /* check for overflow */ + if (p > cxt->pstr) { + cxt->overflow = 1; + return; + } + + memcpy(cxt->p, data, sz); + if ((sz & 3) != 0) + memset(cxt->p + sz, 0, 4 - (sz & 3)); + cxt->p = p; +} + +void ft_begin_node(struct ft_cxt *cxt, const char *name) +{ + ft_put_word(cxt, OF_DT_BEGIN_NODE); + ft_put_bin(cxt, name, strlen(name) + 1); +} + +void ft_end_node(struct ft_cxt *cxt) +{ + ft_put_word(cxt, OF_DT_END_NODE); +} + +void ft_nop(struct ft_cxt *cxt) +{ + ft_put_word(cxt, OF_DT_NOP); +} + +static int lookup_string(struct ft_cxt *cxt, const char *name) +{ + u8 *p; + + p = cxt->pstr; + while (p < cxt->pstr_begin) { + if (strcmp(p, name) == 0) + return p - cxt->p_begin; + p += strlen(p) + 1; + } + + return -1; +} + +void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz) +{ + int len, off; + + if (cxt->overflow) + return; + + len = strlen(name) + 1; + + off = lookup_string(cxt, name); + if (off == -1) { + /* check if we have space */ + if (cxt->p + 12 + sz + len > cxt->pstr) { + cxt->overflow = 1; + return; + } + + cxt->pstr -= len; + memcpy(cxt->pstr, name, len); + off = cxt->pstr - cxt->p_begin; + } + + /* now put offset from beginning of *STRUCTURE* */ + /* will be fixed up at the end */ + ft_put_word(cxt, OF_DT_PROP); + ft_put_word(cxt, sz); + ft_put_word(cxt, off); + ft_put_bin(cxt, data, sz); +} + +void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str) +{ + ft_prop(cxt, name, str, strlen(str) + 1); +} + +void ft_prop_int(struct ft_cxt *cxt, const char *name, int val) +{ + u32 v = cpu_to_be32((u32) val); + + ft_prop(cxt, name, &v, 4); +} + +/* start construction of the flat OF tree */ +void ft_begin(struct ft_cxt *cxt, void *blob, int max_size) +{ + struct boot_param_header *bph = blob; + u32 off; + + /* clear the cxt */ + memset(cxt, 0, sizeof(*cxt)); + + cxt->bph = bph; + cxt->max_size = max_size; + + /* zero everything in the header area */ + memset(bph, 0, sizeof(*bph)); + + bph->magic = cpu_to_be32(OF_DT_HEADER); + bph->version = cpu_to_be32(0x10); + bph->last_comp_version = cpu_to_be32(0x10); + + /* start pointers */ + cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8); + cxt->pres = cxt->pres_begin; + + off = (unsigned long)cxt->pres_begin - (unsigned long)bph; + bph->off_mem_rsvmap = cpu_to_be32(off); + + ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ + ((u64 *) cxt->pres)[1] = 0; + + cxt->p_anchor = cxt->pres + 16; /* over the terminator */ +} + +/* add a reserver physical area to the rsvmap */ +void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size) +{ + ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */ + ((u64 *) cxt->pres)[1] = cpu_to_be64(size); + + cxt->pres += 18; /* advance */ + + ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ + ((u64 *) cxt->pres)[1] = 0; + + /* keep track of size */ + cxt->res_size = cxt->pres + 16 - cxt->pres_begin; + + cxt->p_anchor = cxt->pres + 16; /* over the terminator */ +} + +void ft_begin_tree(struct ft_cxt *cxt) +{ + cxt->p_begin = cxt->p_anchor; + cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */ + + cxt->p = cxt->p_begin; + cxt->pstr = cxt->pstr_begin; +} + +int ft_end_tree(struct ft_cxt *cxt) +{ + struct boot_param_header *bph = cxt->bph; + int off, sz, sz1; + u32 tag, v; + u8 *p; + + ft_put_word(cxt, OF_DT_END); + + if (cxt->overflow) + return -ENOMEM; + + /* size of the areas */ + cxt->struct_size = cxt->p - cxt->p_begin; + cxt->strings_size = cxt->pstr_begin - cxt->pstr; + + /* the offset we must move */ + off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size; + + /* the new strings start */ + cxt->pstr_begin = cxt->p_begin + cxt->struct_size; + + /* move the whole string area */ + memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size); + + /* now perform the fixup of the strings */ + p = cxt->p_begin; + while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) { + p += 4; + + if (tag == OF_DT_BEGIN_NODE) { + p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4); + continue; + } + + if (tag == OF_DT_END_NODE || tag == OF_DT_NOP) + continue; + + if (tag != OF_DT_PROP) + return -EINVAL; + + sz = be32_to_cpu(*(u32 *) p); + p += 4; + + v = be32_to_cpu(*(u32 *) p); + v -= off; + *(u32 *) p = cpu_to_be32(v); /* move down */ + p += 4; + + p = (u8 *) _ALIGN((unsigned long)p + sz, 4); + } + + /* fix sizes */ + p = (char *)cxt->bph; + sz = (cxt->pstr_begin + cxt->strings_size) - p; + sz1 = _ALIGN(sz, 16); /* align at 16 bytes */ + if (sz != sz1) + memset(p + sz, 0, sz1 - sz); + bph->totalsize = cpu_to_be32(sz1); + bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p); + bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p); + + /* the new strings start */ + cxt->pstr_begin = cxt->p_begin + cxt->struct_size; + cxt->pstr = cxt->pstr_begin + cxt->strings_size; + + return 0; +} + +/**********************************************************************/ + +static inline int isprint(int c) +{ + return c >= 0x20 && c <= 0x7e; +} + +static int is_printable_string(const void *data, int len) +{ + const char *s = data; + const char *ss; + + /* zero length is not */ + if (len == 0) + return 0; + + /* must terminate with zero */ + if (s[len - 1] != '\0') + return 0; + + ss = s; + while (*s && isprint(*s)) + s++; + + /* not zero, or not done yet */ + if (*s != '\0' || (s + 1 - ss) < len) + return 0; + + return 1; +} + +static void print_data(const void *data, int len) +{ + int i; + const u8 *s; + + /* no data, don't print */ + if (len == 0) + return; + + if (is_printable_string(data, len)) { + printf(" = \"%s\"", (char *)data); + return; + } + + switch (len) { + case 1: /* byte */ + printf(" = <0x%02x>", (*(u8 *) data) & 0xff); + break; + case 2: /* half-word */ + printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); + break; + case 4: /* word */ + printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); + break; + case 8: /* double-word */ + printf(" = <0x%16llx>", be64_to_cpu(*(uint64_t *) data)); + break; + default: /* anything else... hexdump */ + printf(" = ["); + for (i = 0, s = data; i < len; i++) + printf("%02x%s", s[i], i < len - 1 ? " " : ""); + printf("]"); + + break; + } +} + +void ft_dump_blob(const void *bphp) +{ + const struct boot_param_header *bph = bphp; + const uint64_t *p_rsvmap = (const uint64_t *) + ((const char *)bph + be32_to_cpu(bph->off_mem_rsvmap)); + const u32 *p_struct = (const u32 *) + ((const char *)bph + be32_to_cpu(bph->off_dt_struct)); + const u32 *p_strings = (const u32 *) + ((const char *)bph + be32_to_cpu(bph->off_dt_strings)); + u32 tag; + const u32 *p; + const char *s, *t; + int depth, sz, shift; + int i; + uint64_t addr, size; + + if (be32_to_cpu(bph->magic) != OF_DT_HEADER) { + /* not valid tree */ + return; + } + + depth = 0; + shift = 4; + + for (i = 0;; i++) { + addr = be64_to_cpu(p_rsvmap[i * 2]); + size = be64_to_cpu(p_rsvmap[i * 2 + 1]); + if (addr == 0 && size == 0) + break; + + printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size); + } + + p = p_struct; + while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { + + /* printf("tag: 0x%08x (%d)\n", tag, p - p_struct); */ + + if (tag == OF_DT_BEGIN_NODE) { + s = (const char *)p; + p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4); + + printf("%*s%s {\n", depth * shift, "", s); + + depth++; + continue; + } + + if (tag == OF_DT_END_NODE) { + depth--; + + printf("%*s};\n", depth * shift, ""); + continue; + } + + if (tag == OF_DT_NOP) { + printf("%*s[NOP]\n", depth * shift, ""); + continue; + } + + if (tag != OF_DT_PROP) { + fprintf(stderr, "%*s ** Unknown tag 0x%08x\n", + depth * shift, "", tag); + break; + } + sz = be32_to_cpu(*p++); + s = (const char *)p_strings + be32_to_cpu(*p++); + t = (const char *)p; + p = (const u32 *)_ALIGN((unsigned long)p + sz, 4); + printf("%*s%s", depth * shift, "", s); + print_data(t, sz); + printf(";\n"); + } +} + +void ft_backtrack_node(struct ft_cxt *cxt) +{ + if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) + return; /* XXX only for node */ + + cxt->p -= 4; +} + +/* note that the root node of the blob is "peeled" off */ +void ft_merge_blob(struct ft_cxt *cxt, void *blob) +{ + struct boot_param_header *bph = (struct boot_param_header *)blob; + u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct)); + u32 *p_strings = + (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings)); + u32 tag, *p; + char *s, *t; + int depth, sz; + + if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) + return; /* XXX only for node */ + + cxt->p -= 4; + + depth = 0; + p = p_struct; + while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { + + /* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */ + + if (tag == OF_DT_BEGIN_NODE) { + s = (char *)p; + p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4); + + if (depth++ > 0) + ft_begin_node(cxt, s); + + continue; + } + + if (tag == OF_DT_END_NODE) { + ft_end_node(cxt); + if (--depth == 0) + break; + continue; + } + + if (tag == OF_DT_NOP) + continue; + + if (tag != OF_DT_PROP) + break; + + sz = be32_to_cpu(*p++); + s = (char *)p_strings + be32_to_cpu(*p++); + t = (char *)p; + p = (u32 *) _ALIGN((unsigned long)p + sz, 4); + + ft_prop(cxt, s, t, sz); + } +} + +void *ft_get_prop(void *bphp, const char *propname, int *szp) +{ + struct boot_param_header *bph = bphp; + uint32_t *p_struct = + (uint32_t *) ((char *)bph + be32_to_cpu(bph->off_dt_struct)); + uint32_t *p_strings = + (uint32_t *) ((char *)bph + be32_to_cpu(bph->off_dt_strings)); + uint32_t version = be32_to_cpu(bph->version); + uint32_t tag; + uint32_t *p; + char *s, *t; + char *ss; + int sz; + static char path[256], prop[256]; + + path[0] = '\0'; + + p = p_struct; + while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { + + if (tag == OF_DT_BEGIN_NODE) { + s = (char *)p; + p = (uint32_t *) _ALIGN((unsigned long)p + strlen(s) + + 1, 4); + strcat(path, s); + strcat(path, "/"); + continue; + } + + if (tag == OF_DT_END_NODE) { + path[strlen(path) - 1] = '\0'; + ss = strrchr(path, '/'); + if (ss != NULL) + ss[1] = '\0'; + continue; + } + + if (tag == OF_DT_NOP) + continue; + + if (tag != OF_DT_PROP) + break; + + sz = be32_to_cpu(*p++); + s = (char *)p_strings + be32_to_cpu(*p++); + if (version < 0x10 && sz >= 8) + p = (uint32_t *) _ALIGN((unsigned long)p, 8); + t = (char *)p; + p = (uint32_t *) _ALIGN((unsigned long)p + sz, 4); + + strcpy(prop, path); + strcat(prop, s); + + if (strcmp(prop, propname) == 0) { + *szp = sz; + return t; + } + } + + return NULL; +} + +/********************************************************************/ + +extern unsigned char oftree_dtb[]; +extern unsigned int oftree_dtb_len; + +/* Function that returns a character from the environment */ +extern uchar(*env_get_char) (int); + +#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) } + +static const struct { + const char *name; + int offset; +} bd_map[] = { + BDM(memstart), + BDM(memsize), + BDM(flashstart), + BDM(flashsize), + BDM(flashoffset), + BDM(sramstart), + BDM(sramsize), +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ + || defined(CONFIG_E500) + BDM(immr_base), +#endif +#if defined(CONFIG_MPC5xxx) + BDM(mbar_base), +#endif +#if defined(CONFIG_MPC83XX) + BDM(immrbar), +#endif +#if defined(CONFIG_MPC8220) + BDM(mbar_base), + BDM(inpfreq), + BDM(pcifreq), + BDM(pevfreq), + BDM(flbfreq), + BDM(vcofreq), +#endif + BDM(bootflags), + BDM(ip_addr), + BDM(intfreq), + BDM(busfreq), +#ifdef CONFIG_CPM2 + BDM(cpmfreq), + BDM(brgfreq), + BDM(sccfreq), + BDM(vco), +#endif +#if defined(CONFIG_MPC5xxx) + BDM(ipbfreq), + BDM(pcifreq), +#endif + BDM(baudrate), +}; + +void ft_setup(void *blob, int size, bd_t * bd) +{ + DECLARE_GLOBAL_DATA_PTR; + u8 *end; + u32 *p; + int len; + struct ft_cxt cxt; + int i, k, nxt; + static char tmpenv[256]; + char *s, *lval, *rval; + ulong clock; + uint32_t v; + + /* disable OF tree; booting old kernel */ + if (getenv("disable_of") != NULL) { + memcpy(blob, bd, sizeof(*bd)); + return; + } + + ft_begin(&cxt, blob, size); + + /* fs_add_rsvmap not used */ + + ft_begin_tree(&cxt); + + ft_begin_node(&cxt, ""); + + ft_end_node(&cxt); + + /* copy RO tree */ + ft_merge_blob(&cxt, oftree_dtb); + + /* back into root */ + ft_backtrack_node(&cxt); + + ft_begin_node(&cxt, "u-boot-env"); + + for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { + for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) ; + s = tmpenv; + for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k) + *s++ = env_get_char(k); + *s++ = '\0'; + lval = tmpenv; + s = strchr(tmpenv, '='); + if (s != NULL) { + *s++ = '\0'; + rval = s; + } else + continue; + ft_prop_str(&cxt, lval, rval); + } + + ft_end_node(&cxt); + + ft_begin_node(&cxt, "chosen"); + + ft_prop_str(&cxt, "name", "chosen"); + ft_prop_str(&cxt, "bootargs", getenv("bootargs")); + ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */ + + ft_end_node(&cxt); + + ft_end_node(&cxt); /* end root */ + + ft_end_tree(&cxt); + + /* + printf("merged OF-tree\n"); + ft_dump_blob(blob); + */ + + /* paste the bd_t at the end of the flat tree */ + end = (char *)blob + + be32_to_cpu(((struct boot_param_header *)blob)->totalsize); + memcpy(end, bd, sizeof(*bd)); + +#ifdef CONFIG_PPC + + for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) { + sprintf(tmpenv, "/bd_t/%s", bd_map[i].name); + v = *(uint32_t *)((char *)bd + bd_map[i].offset); + + p = ft_get_prop(blob, tmpenv, &len); + if (p != NULL) + *p = cpu_to_be32(v); + } + + p = ft_get_prop(blob, "/bd_t/enetaddr", &len); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); + + p = ft_get_prop(blob, "/bd_t/ethspeed", &len); + if (p != NULL) + *p = cpu_to_be32((uint32_t) bd->bi_ethspeed); + + clock = bd->bi_intfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + +#ifdef OF_TBCLK + clock = OF_TBCLK; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/timebase-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(OF_TBCLK); +#endif + +#endif /* __powerpc__ */ + + /* + printf("final OF-tree\n"); + ft_dump_blob(blob); + */ + +} + +#endif diff --git a/common/hush.c b/common/hush.c new file mode 100644 index 0000000..bb5041a --- /dev/null +++ b/common/hush.c @@ -0,0 +1,3588 @@ +/* vi: set sw=4 ts=4: */ +/* + * sh.c -- a prototype Bourne shell grammar parser + * Intended to follow the original Thompson and Ritchie + * "small and simple is beautiful" philosophy, which + * incidentally is a good match to today's BusyBox. + * + * Copyright (C) 2000,2001 Larry Doolittle + * + * Credits: + * The parser routines proper are all original material, first + * written Dec 2000 and Jan 2001 by Larry Doolittle. + * The execution engine, the builtins, and much of the underlying + * support has been adapted from busybox-0.49pre's lash, + * which is Copyright (C) 2000 by Lineo, Inc., and + * written by Erik Andersen , . + * That, in turn, is based in part on ladsh.c, by Michael K. Johnson and + * Erik W. Troan, which they placed in the public domain. I don't know + * how much of the Johnson/Troan code has survived the repeated rewrites. + * Other credits: + * simple_itoa() was lifted from boa-0.93.15 + * b_addchr() derived from similar w_addchar function in glibc-2.2 + * setup_redirect(), redirect_opt_num(), and big chunks of main() + * and many builtins derived from contributions by Erik Andersen + * miscellaneous bugfixes from Matt Kraai + * + * There are two big (and related) architecture differences between + * this parser and the lash parser. One is that this version is + * actually designed from the ground up to understand nearly all + * of the Bourne grammar. The second, consequential change is that + * the parser and input reader have been turned inside out. Now, + * the parser is in control, and asks for input as needed. The old + * way had the input reader in control, and it asked for parsing to + * take place as needed. The new way makes it much easier to properly + * handle the recursion implicit in the various substitutions, especially + * across continuation lines. + * + * Bash grammar not implemented: (how many of these were in original sh?) + * $@ (those sure look like weird quoting rules) + * $_ + * ! negation operator for pipes + * &> and >& redirection of stdout+stderr + * Brace Expansion + * Tilde Expansion + * fancy forms of Parameter Expansion + * aliases + * Arithmetic Expansion + * <(list) and >(list) Process Substitution + * reserved words: case, esac, select, function + * Here Documents ( << word ) + * Functions + * Major bugs: + * job handling woefully incomplete and buggy + * reserved word execution woefully incomplete and buggy + * to-do: + * port selected bugfixes from post-0.49 busybox lash - done? + * finish implementing reserved words: for, while, until, do, done + * change { and } from special chars to reserved words + * builtins: break, continue, eval, return, set, trap, ulimit + * test magic exec + * handle children going into background + * clean up recognition of null pipes + * check setting of global_argc and global_argv + * control-C handling, probably with longjmp + * follow IFS rules more precisely, including update semantics + * figure out what to do with backslash-newline + * explain why we use signal instead of sigaction + * propagate syntax errors, die on resource errors? + * continuation lines, both explicit and implicit - done? + * memory leak finding and plugging - done? + * more testing, especially quoting rules and redirection + * document how quoting rules not precisely followed for variable assignments + * maybe change map[] to use 2-bit entries + * (eventually) remove all the printf's + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define __U_BOOT__ +#ifdef __U_BOOT__ +#include /* malloc, free, realloc*/ +#include /* isalpha, isdigit */ +#include /* readline */ +#include +#include /* find_cmd */ +/*cmd_boot.c*/ +extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* do_bootd */ +#endif +#ifdef CFG_HUSH_PARSER +#ifndef __U_BOOT__ +#include /* isalpha, isdigit */ +#include /* getpid */ +#include /* getenv, atoi */ +#include /* strchr */ +#include /* popen etc. */ +#include /* glob, of course */ +#include /* va_list */ +#include +#include +#include /* should be pretty obvious */ + +#include /* ulimit */ +#include +#include +#include + +/* #include */ +/* #define DEBUG_SHELL */ + +#if 1 +#include "busybox.h" +#include "cmdedit.h" +#else +#define applet_name "hush" +#include "standalone.h" +#define hush_main main +#undef CONFIG_FEATURE_SH_FANCY_PROMPT +#define BB_BANNER +#endif +#endif +#define SPECIAL_VAR_SYMBOL 03 +#ifndef __U_BOOT__ +#define FLAG_EXIT_FROM_LOOP 1 +#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ +#define FLAG_REPARSING (1 << 2) /* >= 2nd pass */ + +#endif + +#ifdef __U_BOOT__ +#define EXIT_SUCCESS 0 +#define EOF -1 +#define syntax() syntax_err() +#define xstrdup strdup +#define error_msg printf +#else +typedef enum { + REDIRECT_INPUT = 1, + REDIRECT_OVERWRITE = 2, + REDIRECT_APPEND = 3, + REDIRECT_HEREIS = 4, + REDIRECT_IO = 5 +} redir_type; + +/* The descrip member of this structure is only used to make debugging + * output pretty */ +struct {int mode; int default_fd; char *descrip;} redir_table[] = { + { 0, 0, "()" }, + { O_RDONLY, 0, "<" }, + { O_CREAT|O_TRUNC|O_WRONLY, 1, ">" }, + { O_CREAT|O_APPEND|O_WRONLY, 1, ">>" }, + { O_RDONLY, -1, "<<" }, + { O_RDWR, 1, "<>" } +}; +#endif + +typedef enum { + PIPE_SEQ = 1, + PIPE_AND = 2, + PIPE_OR = 3, + PIPE_BG = 4, +} pipe_style; + +/* might eventually control execution */ +typedef enum { + RES_NONE = 0, + RES_IF = 1, + RES_THEN = 2, + RES_ELIF = 3, + RES_ELSE = 4, + RES_FI = 5, + RES_FOR = 6, + RES_WHILE = 7, + RES_UNTIL = 8, + RES_DO = 9, + RES_DONE = 10, + RES_XXXX = 11, + RES_IN = 12, + RES_SNTX = 13 +} reserved_style; +#define FLAG_END (1<, but protected with __USE_GNU */ +#endif + +/* "globals" within this file */ +static uchar *ifs; +static char map[256]; +#ifndef __U_BOOT__ +static int fake_mode; +static int interactive; +static struct close_me *close_me_head; +static const char *cwd; +static struct pipe *job_list; +static unsigned int last_bg_pid; +static unsigned int last_jobid; +static unsigned int shell_terminal; +static char *PS1; +static char *PS2; +struct variables shell_ver = { "HUSH_VERSION", "0.01", 1, 1, 0 }; +struct variables *top_vars = &shell_ver; +#else +static int flag_repeat = 0; +static int do_repeat = 0; +static struct variables *top_vars = NULL ; +#endif /*__U_BOOT__ */ + +#define B_CHUNK (100) +#define B_NOSPAC 1 + +typedef struct { + char *data; + int length; + int maxlen; + int quote; + int nonnull; +} o_string; +#define NULL_O_STRING {NULL,0,0,0,0} +/* used for initialization: + o_string foo = NULL_O_STRING; */ + +/* I can almost use ordinary FILE *. Is open_memstream() universally + * available? Where is it documented? */ +struct in_str { + const char *p; +#ifndef __U_BOOT__ + char peek_buf[2]; +#endif + int __promptme; + int promptmode; +#ifndef __U_BOOT__ + FILE *file; +#endif + int (*get) (struct in_str *); + int (*peek) (struct in_str *); +}; +#define b_getch(input) ((input)->get(input)) +#define b_peek(input) ((input)->peek(input)) + +#ifndef __U_BOOT__ +#define JOB_STATUS_FORMAT "[%d] %-22s %.40s\n" + +struct built_in_command { + char *cmd; /* name */ + char *descr; /* description */ + int (*function) (struct child_prog *); /* function ptr */ +}; +#endif + +/* This should be in utility.c */ +#ifdef DEBUG_SHELL +#ifndef __U_BOOT__ +static void debug_printf(const char *format, ...) +{ + va_list args; + va_start(args, format); + vfprintf(stderr, format, args); + va_end(args); +} +#else +#define debug_printf printf /* U-Boot debug flag */ +#endif +#else +static inline void debug_printf(const char *format, ...) { } +#endif +#define final_printf debug_printf + +#ifdef __U_BOOT__ +static void syntax_err(void) { + printf("syntax error\n"); +} +#else +static void __syntax(char *file, int line) { + error_msg("syntax error %s:%d", file, line); +} +#define syntax() __syntax(__FILE__, __LINE__) +#endif + +#ifdef __U_BOOT__ +static void *xmalloc(size_t size); +static void *xrealloc(void *ptr, size_t size); +#else +/* Index of subroutines: */ +/* function prototypes for builtins */ +static int builtin_cd(struct child_prog *child); +static int builtin_env(struct child_prog *child); +static int builtin_eval(struct child_prog *child); +static int builtin_exec(struct child_prog *child); +static int builtin_exit(struct child_prog *child); +static int builtin_export(struct child_prog *child); +static int builtin_fg_bg(struct child_prog *child); +static int builtin_help(struct child_prog *child); +static int builtin_jobs(struct child_prog *child); +static int builtin_pwd(struct child_prog *child); +static int builtin_read(struct child_prog *child); +static int builtin_set(struct child_prog *child); +static int builtin_shift(struct child_prog *child); +static int builtin_source(struct child_prog *child); +static int builtin_umask(struct child_prog *child); +static int builtin_unset(struct child_prog *child); +static int builtin_not_written(struct child_prog *child); +#endif +/* o_string manipulation: */ +static int b_check_space(o_string *o, int len); +static int b_addchr(o_string *o, int ch); +static void b_reset(o_string *o); +static int b_addqchr(o_string *o, int ch, int quote); +#ifndef __U_BOOT__ +static int b_adduint(o_string *o, unsigned int i); +#endif +/* in_str manipulations: */ +static int static_get(struct in_str *i); +static int static_peek(struct in_str *i); +static int file_get(struct in_str *i); +static int file_peek(struct in_str *i); +#ifndef __U_BOOT__ +static void setup_file_in_str(struct in_str *i, FILE *f); +#else +static void setup_file_in_str(struct in_str *i); +#endif +static void setup_string_in_str(struct in_str *i, const char *s); +#ifndef __U_BOOT__ +/* close_me manipulations: */ +static void mark_open(int fd); +static void mark_closed(int fd); +static void close_all(void); +#endif +/* "run" the final data structures: */ +static char *indenter(int i); +static int free_pipe_list(struct pipe *head, int indent); +static int free_pipe(struct pipe *pi, int indent); +/* really run the final data structures: */ +#ifndef __U_BOOT__ +static int setup_redirects(struct child_prog *prog, int squirrel[]); +#endif +static int run_list_real(struct pipe *pi); +#ifndef __U_BOOT__ +static void pseudo_exec(struct child_prog *child) __attribute__ ((noreturn)); +#endif +static int run_pipe_real(struct pipe *pi); +/* extended glob support: */ +#ifndef __U_BOOT__ +static int globhack(const char *src, int flags, glob_t *pglob); +static int glob_needed(const char *s); +static int xglob(o_string *dest, int flags, glob_t *pglob); +#endif +/* variable assignment: */ +static int is_assignment(const char *s); +/* data structure manipulation: */ +#ifndef __U_BOOT__ +static int setup_redirect(struct p_context *ctx, int fd, redir_type style, struct in_str *input); +#endif +static void initialize_context(struct p_context *ctx); +static int done_word(o_string *dest, struct p_context *ctx); +static int done_command(struct p_context *ctx); +static int done_pipe(struct p_context *ctx, pipe_style type); +/* primary string parsing: */ +#ifndef __U_BOOT__ +static int redirect_dup_num(struct in_str *input); +static int redirect_opt_num(o_string *o); +static int process_command_subs(o_string *dest, struct p_context *ctx, struct in_str *input, int subst_end); +static int parse_group(o_string *dest, struct p_context *ctx, struct in_str *input, int ch); +#endif +static char *lookup_param(char *src); +static char *make_string(char **inp); +static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input); +#ifndef __U_BOOT__ +static int parse_string(o_string *dest, struct p_context *ctx, const char *src); +#endif +static int parse_stream(o_string *dest, struct p_context *ctx, struct in_str *input0, int end_trigger); +/* setup: */ +static int parse_stream_outer(struct in_str *inp, int flag); +#ifndef __U_BOOT__ +static int parse_string_outer(const char *s, int flag); +static int parse_file_outer(FILE *f); +#endif +#ifndef __U_BOOT__ +/* job management: */ +static int checkjobs(struct pipe* fg_pipe); +static void insert_bg_job(struct pipe *pi); +static void remove_bg_job(struct pipe *pi); +#endif +/* local variable support */ +static char **make_list_in(char **inp, char *name); +static char *insert_var_value(char *inp); +static char *get_local_var(const char *var); +#ifndef __U_BOOT__ +static void unset_local_var(const char *name); +#endif +static int set_local_var(const char *s, int flg_export); + +#ifndef __U_BOOT__ +/* Table of built-in functions. They can be forked or not, depending on + * context: within pipes, they fork. As simple commands, they do not. + * When used in non-forking context, they can change global variables + * in the parent shell process. If forked, of course they can not. + * For example, 'unset foo | whatever' will parse and run, but foo will + * still be set at the end. */ +static struct built_in_command bltins[] = { + {"bg", "Resume a job in the background", builtin_fg_bg}, + {"break", "Exit for, while or until loop", builtin_not_written}, + {"cd", "Change working directory", builtin_cd}, + {"continue", "Continue for, while or until loop", builtin_not_written}, + {"env", "Print all environment variables", builtin_env}, + {"eval", "Construct and run shell command", builtin_eval}, + {"exec", "Exec command, replacing this shell with the exec'd process", + builtin_exec}, + {"exit", "Exit from shell()", builtin_exit}, + {"export", "Set environment variable", builtin_export}, + {"fg", "Bring job into the foreground", builtin_fg_bg}, + {"jobs", "Lists the active jobs", builtin_jobs}, + {"pwd", "Print current directory", builtin_pwd}, + {"read", "Input environment variable", builtin_read}, + {"return", "Return from a function", builtin_not_written}, + {"set", "Set/unset shell local variables", builtin_set}, + {"shift", "Shift positional parameters", builtin_shift}, + {"trap", "Trap signals", builtin_not_written}, + {"ulimit","Controls resource limits", builtin_not_written}, + {"umask","Sets file creation mask", builtin_umask}, + {"unset", "Unset environment variable", builtin_unset}, + {".", "Source-in and run commands in a file", builtin_source}, + {"help", "List shell built-in commands", builtin_help}, + {NULL, NULL, NULL} +}; + +static const char *set_cwd(void) +{ + if(cwd==unknown) + cwd = NULL; /* xgetcwd(arg) called free(arg) */ + cwd = xgetcwd((char *)cwd); + if (!cwd) + cwd = unknown; + return cwd; +} + +/* built-in 'eval' handler */ +static int builtin_eval(struct child_prog *child) +{ + char *str = NULL; + int rcode = EXIT_SUCCESS; + + if (child->argv[1]) { + str = make_string(child->argv + 1); + parse_string_outer(str, FLAG_EXIT_FROM_LOOP | + FLAG_PARSE_SEMICOLON); + free(str); + rcode = last_return_code; + } + return rcode; +} + +/* built-in 'cd ' handler */ +static int builtin_cd(struct child_prog *child) +{ + char *newdir; + if (child->argv[1] == NULL) + newdir = getenv("HOME"); + else + newdir = child->argv[1]; + if (chdir(newdir)) { + printf("cd: %s: %s\n", newdir, strerror(errno)); + return EXIT_FAILURE; + } + set_cwd(); + return EXIT_SUCCESS; +} + +/* built-in 'env' handler */ +static int builtin_env(struct child_prog *dummy) +{ + char **e = environ; + if (e == NULL) return EXIT_FAILURE; + for (; *e; e++) { + puts(*e); + } + return EXIT_SUCCESS; +} + +/* built-in 'exec' handler */ +static int builtin_exec(struct child_prog *child) +{ + if (child->argv[1] == NULL) + return EXIT_SUCCESS; /* Really? */ + child->argv++; + pseudo_exec(child); + /* never returns */ +} + +/* built-in 'exit' handler */ +static int builtin_exit(struct child_prog *child) +{ + if (child->argv[1] == NULL) + exit(last_return_code); + exit (atoi(child->argv[1])); +} + +/* built-in 'export VAR=value' handler */ +static int builtin_export(struct child_prog *child) +{ + int res = 0; + char *name = child->argv[1]; + + if (name == NULL) { + return (builtin_env(child)); + } + + name = strdup(name); + + if(name) { + char *value = strchr(name, '='); + + if (!value) { + char *tmp; + /* They are exporting something without an =VALUE */ + + value = get_local_var(name); + if (value) { + size_t ln = strlen(name); + + tmp = realloc(name, ln+strlen(value)+2); + if(tmp==NULL) + res = -1; + else { + sprintf(tmp+ln, "=%s", value); + name = tmp; + } + } else { + /* bash does not return an error when trying to export + * an undefined variable. Do likewise. */ + res = 1; + } + } + } + if (res<0) + perror_msg("export"); + else if(res==0) + res = set_local_var(name, 1); + else + res = 0; + free(name); + return res; +} + +/* built-in 'fg' and 'bg' handler */ +static int builtin_fg_bg(struct child_prog *child) +{ + int i, jobnum; + struct pipe *pi=NULL; + + if (!interactive) + return EXIT_FAILURE; + /* If they gave us no args, assume they want the last backgrounded task */ + if (!child->argv[1]) { + for (pi = job_list; pi; pi = pi->next) { + if (pi->jobid == last_jobid) { + break; + } + } + if (!pi) { + error_msg("%s: no current job", child->argv[0]); + return EXIT_FAILURE; + } + } else { + if (sscanf(child->argv[1], "%%%d", &jobnum) != 1) { + error_msg("%s: bad argument '%s'", child->argv[0], child->argv[1]); + return EXIT_FAILURE; + } + for (pi = job_list; pi; pi = pi->next) { + if (pi->jobid == jobnum) { + break; + } + } + if (!pi) { + error_msg("%s: %d: no such job", child->argv[0], jobnum); + return EXIT_FAILURE; + } + } + + if (*child->argv[0] == 'f') { + /* Put the job into the foreground. */ + tcsetpgrp(shell_terminal, pi->pgrp); + } + + /* Restart the processes in the job */ + for (i = 0; i < pi->num_progs; i++) + pi->progs[i].is_stopped = 0; + + if ( (i=kill(- pi->pgrp, SIGCONT)) < 0) { + if (i == ESRCH) { + remove_bg_job(pi); + } else { + perror_msg("kill (SIGCONT)"); + } + } + + pi->stopped_progs = 0; + return EXIT_SUCCESS; +} + +/* built-in 'help' handler */ +static int builtin_help(struct child_prog *dummy) +{ + struct built_in_command *x; + + printf("\nBuilt-in commands:\n"); + printf("-------------------\n"); + for (x = bltins; x->cmd; x++) { + if (x->descr==NULL) + continue; + printf("%s\t%s\n", x->cmd, x->descr); + } + printf("\n\n"); + return EXIT_SUCCESS; +} + +/* built-in 'jobs' handler */ +static int builtin_jobs(struct child_prog *child) +{ + struct pipe *job; + char *status_string; + + for (job = job_list; job; job = job->next) { + if (job->running_progs == job->stopped_progs) + status_string = "Stopped"; + else + status_string = "Running"; + + printf(JOB_STATUS_FORMAT, job->jobid, status_string, job->text); + } + return EXIT_SUCCESS; +} + + +/* built-in 'pwd' handler */ +static int builtin_pwd(struct child_prog *dummy) +{ + puts(set_cwd()); + return EXIT_SUCCESS; +} + +/* built-in 'read VAR' handler */ +static int builtin_read(struct child_prog *child) +{ + int res; + + if (child->argv[1]) { + char string[BUFSIZ]; + char *var = 0; + + string[0] = 0; /* In case stdin has only EOF */ + /* read string */ + fgets(string, sizeof(string), stdin); + chomp(string); + var = malloc(strlen(child->argv[1])+strlen(string)+2); + if(var) { + sprintf(var, "%s=%s", child->argv[1], string); + res = set_local_var(var, 0); + } else + res = -1; + if (res) + fprintf(stderr, "read: %m\n"); + free(var); /* So not move up to avoid breaking errno */ + return res; + } else { + do res=getchar(); while(res!='\n' && res!=EOF); + return 0; + } +} + +/* built-in 'set VAR=value' handler */ +static int builtin_set(struct child_prog *child) +{ + char *temp = child->argv[1]; + struct variables *e; + + if (temp == NULL) + for(e = top_vars; e; e=e->next) + printf("%s=%s\n", e->name, e->value); + else + set_local_var(temp, 0); + + return EXIT_SUCCESS; +} + + +/* Built-in 'shift' handler */ +static int builtin_shift(struct child_prog *child) +{ + int n=1; + if (child->argv[1]) { + n=atoi(child->argv[1]); + } + if (n>=0 && nargv[1] == NULL) + return EXIT_FAILURE; + + /* XXX search through $PATH is missing */ + input = fopen(child->argv[1], "r"); + if (!input) { + error_msg("Couldn't open file '%s'", child->argv[1]); + return EXIT_FAILURE; + } + + /* Now run the file */ + /* XXX argv and argc are broken; need to save old global_argv + * (pointer only is OK!) on this stack frame, + * set global_argv=child->argv+1, recurse, and restore. */ + mark_open(fileno(input)); + status = parse_file_outer(input); + mark_closed(fileno(input)); + fclose(input); + return (status); +} + +static int builtin_umask(struct child_prog *child) +{ + mode_t new_umask; + const char *arg = child->argv[1]; + char *end; + if (arg) { + new_umask=strtoul(arg, &end, 8); + if (*end!='\0' || end == arg) { + return EXIT_FAILURE; + } + } else { + printf("%.3o\n", (unsigned int) (new_umask=umask(0))); + } + umask(new_umask); + return EXIT_SUCCESS; +} + +/* built-in 'unset VAR' handler */ +static int builtin_unset(struct child_prog *child) +{ + /* bash returned already true */ + unset_local_var(child->argv[1]); + return EXIT_SUCCESS; +} + +static int builtin_not_written(struct child_prog *child) +{ + printf("builtin_%s not written\n",child->argv[0]); + return EXIT_FAILURE; +} +#endif + +static int b_check_space(o_string *o, int len) +{ + /* It would be easy to drop a more restrictive policy + * in here, such as setting a maximum string length */ + if (o->length + len > o->maxlen) { + char *old_data = o->data; + /* assert (data == NULL || o->maxlen != 0); */ + o->maxlen += max(2*len, B_CHUNK); + o->data = realloc(o->data, 1 + o->maxlen); + if (o->data == NULL) { + free(old_data); + } + } + return o->data == NULL; +} + +static int b_addchr(o_string *o, int ch) +{ + debug_printf("b_addchr: %c %d %p\n", ch, o->length, o); + if (b_check_space(o, 1)) return B_NOSPAC; + o->data[o->length] = ch; + o->length++; + o->data[o->length] = '\0'; + return 0; +} + +static void b_reset(o_string *o) +{ + o->length = 0; + o->nonnull = 0; + if (o->data != NULL) *o->data = '\0'; +} + +static void b_free(o_string *o) +{ + b_reset(o); + free(o->data); + o->data = NULL; + o->maxlen = 0; +} + +/* My analysis of quoting semantics tells me that state information + * is associated with a destination, not a source. + */ +static int b_addqchr(o_string *o, int ch, int quote) +{ + if (quote && strchr("*?[\\",ch)) { + int rc; + rc = b_addchr(o, '\\'); + if (rc) return rc; + } + return b_addchr(o, ch); +} + +/* belongs in utility.c */ +char *simple_itoa(unsigned int i) +{ + /* 21 digits plus null terminator, good for 64-bit or smaller ints */ + static char local[22]; + char *p = &local[21]; + *p-- = '\0'; + do { + *p-- = '0' + i % 10; + i /= 10; + } while (i > 0); + return p + 1; +} + +#ifndef __U_BOOT__ +static int b_adduint(o_string *o, unsigned int i) +{ + int r; + char *p = simple_itoa(i); + /* no escape checking necessary */ + do r=b_addchr(o, *p++); while (r==0 && *p); + return r; +} +#endif + +static int static_get(struct in_str *i) +{ + int ch=*i->p++; + if (ch=='\0') return EOF; + return ch; +} + +static int static_peek(struct in_str *i) +{ + return *i->p; +} + +#ifndef __U_BOOT__ +static inline void cmdedit_set_initial_prompt(void) +{ +#ifndef CONFIG_FEATURE_SH_FANCY_PROMPT + PS1 = NULL; +#else + PS1 = getenv("PS1"); + if(PS1==0) + PS1 = "\\w \\$ "; +#endif +} + +static inline void setup_prompt_string(int promptmode, char **prompt_str) +{ + debug_printf("setup_prompt_string %d ",promptmode); +#ifndef CONFIG_FEATURE_SH_FANCY_PROMPT + /* Set up the prompt */ + if (promptmode == 1) { + free(PS1); + PS1=xmalloc(strlen(cwd)+4); + sprintf(PS1, "%s %s", cwd, ( geteuid() != 0 ) ? "$ ":"# "); + *prompt_str = PS1; + } else { + *prompt_str = PS2; + } +#else + *prompt_str = (promptmode==1)? PS1 : PS2; +#endif + debug_printf("result %s\n",*prompt_str); +} +#endif + +static void get_user_input(struct in_str *i) +{ +#ifndef __U_BOOT__ + char *prompt_str; + static char the_command[BUFSIZ]; + + setup_prompt_string(i->promptmode, &prompt_str); +#ifdef CONFIG_FEATURE_COMMAND_EDITING + /* + ** enable command line editing only while a command line + ** is actually being read; otherwise, we'll end up bequeathing + ** atexit() handlers and other unwanted stuff to our + ** child processes (rob@sysgo.de) + */ + cmdedit_read_input(prompt_str, the_command); +#else + fputs(prompt_str, stdout); + fflush(stdout); + the_command[0]=fgetc(i->file); + the_command[1]='\0'; +#endif + fflush(stdout); + i->p = the_command; +#else + extern char console_buffer[CFG_CBSIZE]; + int n; + static char the_command[CFG_CBSIZE]; + +#ifdef CONFIG_BOOT_RETRY_TIME +# ifdef CONFIG_RESET_TO_RETRY + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +# else +# error "This currently only works with CONFIG_RESET_TO_RETRY enabled" +# endif + reset_cmd_timeout(); +#endif + i->__promptme = 1; + if (i->promptmode == 1) { + n = readline(CFG_PROMPT); + } else { + n = readline(CFG_PROMPT_HUSH_PS2); + } +#ifdef CONFIG_BOOT_RETRY_TIME + if (n == -2) { + puts("\nTimeout waiting for command\n"); +# ifdef CONFIG_RESET_TO_RETRY + do_reset(NULL, 0, 0, NULL); +# else +# error "This currently only works with CONFIG_RESET_TO_RETRY enabled" +# endif + } +#endif + if (n == -1 ) { + flag_repeat = 0; + i->__promptme = 0; + } + n = strlen(console_buffer); + console_buffer[n] = '\n'; + console_buffer[n+1]= '\0'; + if (had_ctrlc()) flag_repeat = 0; + clear_ctrlc(); + do_repeat = 0; + if (i->promptmode == 1) { + if (console_buffer[0] == '\n'&& flag_repeat == 0) { + strcpy(the_command,console_buffer); + } + else { + if (console_buffer[0] != '\n') { + strcpy(the_command,console_buffer); + flag_repeat = 1; + } + else { + do_repeat = 1; + } + } + i->p = the_command; + } + else { + if (console_buffer[0] != '\n') { + if (strlen(the_command) + strlen(console_buffer) + < CFG_CBSIZE) { + n = strlen(the_command); + the_command[n-1] = ' '; + strcpy(&the_command[n],console_buffer); + } + else { + the_command[0] = '\n'; + the_command[1] = '\0'; + flag_repeat = 0; + } + } + if (i->__promptme == 0) { + the_command[0] = '\n'; + the_command[1] = '\0'; + } + i->p = console_buffer; + } +#endif +} + +/* This is the magic location that prints prompts + * and gets data back from the user */ +static int file_get(struct in_str *i) +{ + int ch; + + ch = 0; + /* If there is data waiting, eat it up */ + if (i->p && *i->p) { + ch=*i->p++; + } else { + /* need to double check i->file because we might be doing something + * more complicated by now, like sourcing or substituting. */ +#ifndef __U_BOOT__ + if (i->__promptme && interactive && i->file == stdin) { + while(! i->p || (interactive && strlen(i->p)==0) ) { +#else + while(! i->p || strlen(i->p)==0 ) { +#endif + get_user_input(i); + } + i->promptmode=2; +#ifndef __U_BOOT__ + i->__promptme = 0; +#endif + if (i->p && *i->p) { + ch=*i->p++; + } +#ifndef __U_BOOT__ + } else { + ch = fgetc(i->file); + } + +#endif + debug_printf("b_getch: got a %d\n", ch); + } +#ifndef __U_BOOT__ + if (ch == '\n') i->__promptme=1; +#endif + return ch; +} + +/* All the callers guarantee this routine will never be + * used right after a newline, so prompting is not needed. + */ +static int file_peek(struct in_str *i) +{ +#ifndef __U_BOOT__ + if (i->p && *i->p) { +#endif + return *i->p; +#ifndef __U_BOOT__ + } else { + i->peek_buf[0] = fgetc(i->file); + i->peek_buf[1] = '\0'; + i->p = i->peek_buf; + debug_printf("b_peek: got a %d\n", *i->p); + return *i->p; + } +#endif +} + +#ifndef __U_BOOT__ +static void setup_file_in_str(struct in_str *i, FILE *f) +#else +static void setup_file_in_str(struct in_str *i) +#endif +{ + i->peek = file_peek; + i->get = file_get; + i->__promptme=1; + i->promptmode=1; +#ifndef __U_BOOT__ + i->file = f; +#endif + i->p = NULL; +} + +static void setup_string_in_str(struct in_str *i, const char *s) +{ + i->peek = static_peek; + i->get = static_get; + i->__promptme=1; + i->promptmode=1; + i->p = s; +} + +#ifndef __U_BOOT__ +static void mark_open(int fd) +{ + struct close_me *new = xmalloc(sizeof(struct close_me)); + new->fd = fd; + new->next = close_me_head; + close_me_head = new; +} + +static void mark_closed(int fd) +{ + struct close_me *tmp; + if (close_me_head == NULL || close_me_head->fd != fd) + error_msg_and_die("corrupt close_me"); + tmp = close_me_head; + close_me_head = close_me_head->next; + free(tmp); +} + +static void close_all(void) +{ + struct close_me *c; + for (c=close_me_head; c; c=c->next) { + close(c->fd); + } + close_me_head = NULL; +} + +/* squirrel != NULL means we squirrel away copies of stdin, stdout, + * and stderr if they are redirected. */ +static int setup_redirects(struct child_prog *prog, int squirrel[]) +{ + int openfd, mode; + struct redir_struct *redir; + + for (redir=prog->redirects; redir; redir=redir->next) { + if (redir->dup == -1 && redir->word.gl_pathv == NULL) { + /* something went wrong in the parse. Pretend it didn't happen */ + continue; + } + if (redir->dup == -1) { + mode=redir_table[redir->type].mode; + openfd = open(redir->word.gl_pathv[0], mode, 0666); + if (openfd < 0) { + /* this could get lost if stderr has been redirected, but + bash and ash both lose it as well (though zsh doesn't!) */ + perror_msg("error opening %s", redir->word.gl_pathv[0]); + return 1; + } + } else { + openfd = redir->dup; + } + + if (openfd != redir->fd) { + if (squirrel && redir->fd < 3) { + squirrel[redir->fd] = dup(redir->fd); + } + if (openfd == -3) { + close(openfd); + } else { + dup2(openfd, redir->fd); + if (redir->dup == -1) + close (openfd); + } + } + } + return 0; +} + +static void restore_redirects(int squirrel[]) +{ + int i, fd; + for (i=0; i<3; i++) { + fd = squirrel[i]; + if (fd != -1) { + /* No error checking. I sure wouldn't know what + * to do with an error if I found one! */ + dup2(fd, i); + close(fd); + } + } +} + +/* never returns */ +/* XXX no exit() here. If you don't exec, use _exit instead. + * The at_exit handlers apparently confuse the calling process, + * in particular stdin handling. Not sure why? */ +static void pseudo_exec(struct child_prog *child) +{ + int i, rcode; + char *p; + struct built_in_command *x; + if (child->argv) { + for (i=0; is_assignment(child->argv[i]); i++) { + debug_printf("pid %d environment modification: %s\n",getpid(),child->argv[i]); + p = insert_var_value(child->argv[i]); + putenv(strdup(p)); + if (p != child->argv[i]) free(p); + } + child->argv+=i; /* XXX this hack isn't so horrible, since we are about + to exit, and therefore don't need to keep data + structures consistent for free() use. */ + /* If a variable is assigned in a forest, and nobody listens, + * was it ever really set? + */ + if (child->argv[0] == NULL) { + _exit(EXIT_SUCCESS); + } + + /* + * Check if the command matches any of the builtins. + * Depending on context, this might be redundant. But it's + * easier to waste a few CPU cycles than it is to figure out + * if this is one of those cases. + */ + for (x = bltins; x->cmd; x++) { + if (strcmp(child->argv[0], x->cmd) == 0 ) { + debug_printf("builtin exec %s\n", child->argv[0]); + rcode = x->function(child); + fflush(stdout); + _exit(rcode); + } + } + + /* Check if the command matches any busybox internal commands + * ("applets") here. + * FIXME: This feature is not 100% safe, since + * BusyBox is not fully reentrant, so we have no guarantee the things + * from the .bss are still zeroed, or that things from .data are still + * at their defaults. We could exec ourself from /proc/self/exe, but I + * really dislike relying on /proc for things. We could exec ourself + * from global_argv[0], but if we are in a chroot, we may not be able + * to find ourself... */ +#ifdef CONFIG_FEATURE_SH_STANDALONE_SHELL + { + int argc_l; + char** argv_l=child->argv; + char *name = child->argv[0]; + +#ifdef CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN + /* Following discussions from November 2000 on the busybox mailing + * list, the default configuration, (without + * get_last_path_component()) lets the user force use of an + * external command by specifying the full (with slashes) filename. + * If you enable CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN then applets + * _aways_ override external commands, so if you want to run + * /bin/cat, it will use BusyBox cat even if /bin/cat exists on the + * filesystem and is _not_ busybox. Some systems may want this, + * most do not. */ + name = get_last_path_component(name); +#endif + /* Count argc for use in a second... */ + for(argc_l=0;*argv_l!=NULL; argv_l++, argc_l++); + optind = 1; + debug_printf("running applet %s\n", name); + run_applet_by_name(name, argc_l, child->argv); + } +#endif + debug_printf("exec of %s\n",child->argv[0]); + execvp(child->argv[0],child->argv); + perror_msg("couldn't exec: %s",child->argv[0]); + _exit(1); + } else if (child->group) { + debug_printf("runtime nesting to group\n"); + interactive=0; /* crucial!!!! */ + rcode = run_list_real(child->group); + /* OK to leak memory by not calling free_pipe_list, + * since this process is about to exit */ + _exit(rcode); + } else { + /* Can happen. See what bash does with ">foo" by itself. */ + debug_printf("trying to pseudo_exec null command\n"); + _exit(EXIT_SUCCESS); + } +} + +static void insert_bg_job(struct pipe *pi) +{ + struct pipe *thejob; + + /* Linear search for the ID of the job to use */ + pi->jobid = 1; + for (thejob = job_list; thejob; thejob = thejob->next) + if (thejob->jobid >= pi->jobid) + pi->jobid = thejob->jobid + 1; + + /* add thejob to the list of running jobs */ + if (!job_list) { + thejob = job_list = xmalloc(sizeof(*thejob)); + } else { + for (thejob = job_list; thejob->next; thejob = thejob->next) /* nothing */; + thejob->next = xmalloc(sizeof(*thejob)); + thejob = thejob->next; + } + + /* physically copy the struct job */ + memcpy(thejob, pi, sizeof(struct pipe)); + thejob->next = NULL; + thejob->running_progs = thejob->num_progs; + thejob->stopped_progs = 0; + thejob->text = xmalloc(BUFSIZ); /* cmdedit buffer size */ + + /*if (pi->progs[0] && pi->progs[0].argv && pi->progs[0].argv[0]) */ + { + char *bar=thejob->text; + char **foo=pi->progs[0].argv; + while(foo && *foo) { + bar += sprintf(bar, "%s ", *foo++); + } + } + + /* we don't wait for background thejobs to return -- append it + to the list of backgrounded thejobs and leave it alone */ + printf("[%d] %d\n", thejob->jobid, thejob->progs[0].pid); + last_bg_pid = thejob->progs[0].pid; + last_jobid = thejob->jobid; +} + +/* remove a backgrounded job */ +static void remove_bg_job(struct pipe *pi) +{ + struct pipe *prev_pipe; + + if (pi == job_list) { + job_list = pi->next; + } else { + prev_pipe = job_list; + while (prev_pipe->next != pi) + prev_pipe = prev_pipe->next; + prev_pipe->next = pi->next; + } + if (job_list) + last_jobid = job_list->jobid; + else + last_jobid = 0; + + pi->stopped_progs = 0; + free_pipe(pi, 0); + free(pi); +} + +/* Checks to see if any processes have exited -- if they + have, figure out why and see if a job has completed */ +static int checkjobs(struct pipe* fg_pipe) +{ + int attributes; + int status; + int prognum = 0; + struct pipe *pi; + pid_t childpid; + + attributes = WUNTRACED; + if (fg_pipe==NULL) { + attributes |= WNOHANG; + } + + while ((childpid = waitpid(-1, &status, attributes)) > 0) { + if (fg_pipe) { + int i, rcode = 0; + for (i=0; i < fg_pipe->num_progs; i++) { + if (fg_pipe->progs[i].pid == childpid) { + if (i==fg_pipe->num_progs-1) + rcode=WEXITSTATUS(status); + (fg_pipe->num_progs)--; + return(rcode); + } + } + } + + for (pi = job_list; pi; pi = pi->next) { + prognum = 0; + while (prognum < pi->num_progs && pi->progs[prognum].pid != childpid) { + prognum++; + } + if (prognum < pi->num_progs) + break; + } + + if(pi==NULL) { + debug_printf("checkjobs: pid %d was not in our list!\n", childpid); + continue; + } + + if (WIFEXITED(status) || WIFSIGNALED(status)) { + /* child exited */ + pi->running_progs--; + pi->progs[prognum].pid = 0; + + if (!pi->running_progs) { + printf(JOB_STATUS_FORMAT, pi->jobid, "Done", pi->text); + remove_bg_job(pi); + } + } else { + /* child stopped */ + pi->stopped_progs++; + pi->progs[prognum].is_stopped = 1; + +#if 0 + /* Printing this stuff is a pain, since it tends to + * overwrite the prompt an inconveinient moments. So + * don't do that. */ + if (pi->stopped_progs == pi->num_progs) { + printf("\n"JOB_STATUS_FORMAT, pi->jobid, "Stopped", pi->text); + } +#endif + } + } + + if (childpid == -1 && errno != ECHILD) + perror_msg("waitpid"); + + /* move the shell to the foreground */ + /*if (interactive && tcsetpgrp(shell_terminal, getpgid(0))) */ + /* perror_msg("tcsetpgrp-2"); */ + return -1; +} + +/* Figure out our controlling tty, checking in order stderr, + * stdin, and stdout. If check_pgrp is set, also check that + * we belong to the foreground process group associated with + * that tty. The value of shell_terminal is needed in order to call + * tcsetpgrp(shell_terminal, ...); */ +void controlling_tty(int check_pgrp) +{ + pid_t curpgrp; + + if ((curpgrp = tcgetpgrp(shell_terminal = 2)) < 0 + && (curpgrp = tcgetpgrp(shell_terminal = 0)) < 0 + && (curpgrp = tcgetpgrp(shell_terminal = 1)) < 0) + goto shell_terminal_error; + + if (check_pgrp && curpgrp != getpgid(0)) + goto shell_terminal_error; + + return; + +shell_terminal_error: + shell_terminal = -1; + return; +} +#endif + +/* run_pipe_real() starts all the jobs, but doesn't wait for anything + * to finish. See checkjobs(). + * + * return code is normally -1, when the caller has to wait for children + * to finish to determine the exit status of the pipe. If the pipe + * is a simple builtin command, however, the action is done by the + * time run_pipe_real returns, and the exit code is provided as the + * return value. + * + * The input of the pipe is always stdin, the output is always + * stdout. The outpipe[] mechanism in BusyBox-0.48 lash is bogus, + * because it tries to avoid running the command substitution in + * subshell, when that is in fact necessary. The subshell process + * now has its stdout directed to the input of the appropriate pipe, + * so this routine is noticeably simpler. + */ +static int run_pipe_real(struct pipe *pi) +{ + int i; +#ifndef __U_BOOT__ + int nextin, nextout; + int pipefds[2]; /* pipefds[0] is for reading */ + struct child_prog *child; + struct built_in_command *x; + char *p; +# if __GNUC__ + /* Avoid longjmp clobbering */ + (void) &i; + (void) &nextin; + (void) &nextout; + (void) &child; +# endif +#else + int nextin; + int flag = do_repeat ? CMD_FLAG_REPEAT : 0; + struct child_prog *child; + cmd_tbl_t *cmdtp; + char *p; +# if __GNUC__ + /* Avoid longjmp clobbering */ + (void) &i; + (void) &nextin; + (void) &child; +# endif +#endif /* __U_BOOT__ */ + + nextin = 0; +#ifndef __U_BOOT__ + pi->pgrp = -1; +#endif + + /* Check if this is a simple builtin (not part of a pipe). + * Builtins within pipes have to fork anyway, and are handled in + * pseudo_exec. "echo foo | read bar" doesn't work on bash, either. + */ + if (pi->num_progs == 1) child = & (pi->progs[0]); +#ifndef __U_BOOT__ + if (pi->num_progs == 1 && child->group && child->subshell == 0) { + int squirrel[] = {-1, -1, -1}; + int rcode; + debug_printf("non-subshell grouping\n"); + setup_redirects(child, squirrel); + /* XXX could we merge code with following builtin case, + * by creating a pseudo builtin that calls run_list_real? */ + rcode = run_list_real(child->group); + restore_redirects(squirrel); +#else + if (pi->num_progs == 1 && child->group) { + int rcode; + debug_printf("non-subshell grouping\n"); + rcode = run_list_real(child->group); +#endif + return rcode; + } else if (pi->num_progs == 1 && pi->progs[0].argv != NULL) { + for (i=0; is_assignment(child->argv[i]); i++) { /* nothing */ } + if (i!=0 && child->argv[i]==NULL) { + /* assignments, but no command: set the local environment */ + for (i=0; child->argv[i]!=NULL; i++) { + + /* Ok, this case is tricky. We have to decide if this is a + * local variable, or an already exported variable. If it is + * already exported, we have to export the new value. If it is + * not exported, we need only set this as a local variable. + * This junk is all to decide whether or not to export this + * variable. */ + int export_me=0; + char *name, *value; + name = xstrdup(child->argv[i]); + debug_printf("Local environment set: %s\n", name); + value = strchr(name, '='); + if (value) + *value=0; +#ifndef __U_BOOT__ + if ( get_local_var(name)) { + export_me=1; + } +#endif + free(name); + p = insert_var_value(child->argv[i]); + set_local_var(p, export_me); + if (p != child->argv[i]) free(p); + } + return EXIT_SUCCESS; /* don't worry about errors in set_local_var() yet */ + } + for (i = 0; is_assignment(child->argv[i]); i++) { + p = insert_var_value(child->argv[i]); +#ifndef __U_BOOT__ + putenv(strdup(p)); +#else + set_local_var(p, 0); +#endif + if (p != child->argv[i]) { + child->sp--; + free(p); + } + } + if (child->sp) { + char * str = NULL; + + str = make_string((child->argv + i)); + parse_string_outer(str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING); + free(str); + return last_return_code; + } +#ifndef __U_BOOT__ + for (x = bltins; x->cmd; x++) { + if (strcmp(child->argv[i], x->cmd) == 0 ) { + int squirrel[] = {-1, -1, -1}; + int rcode; + if (x->function == builtin_exec && child->argv[i+1]==NULL) { + debug_printf("magic exec\n"); + setup_redirects(child,NULL); + return EXIT_SUCCESS; + } + debug_printf("builtin inline %s\n", child->argv[0]); + /* XXX setup_redirects acts on file descriptors, not FILEs. + * This is perfect for work that comes after exec(). + * Is it really safe for inline use? Experimentally, + * things seem to work with glibc. */ + setup_redirects(child, squirrel); +#else + /* check ";", because ,example , argv consist from + * "help;flinfo" must not execute + */ + if (strchr(child->argv[i], ';')) { + printf ("Unknown command '%s' - try 'help' or use 'run' command\n", + child->argv[i]); + return -1; + } + /* Look up command in command table */ + + + if ((cmdtp = find_cmd(child->argv[i])) == NULL) { + printf ("Unknown command '%s' - try 'help'\n", child->argv[i]); + return -1; /* give up after bad command */ + } else { + int rcode; +#if (CONFIG_COMMANDS & CFG_CMD_BOOTD) + extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + + /* avoid "bootd" recursion */ + if (cmdtp->cmd == do_bootd) { + if (flag & CMD_FLAG_BOOTD) { + printf ("'bootd' recursion detected\n"); + return -1; + } + else + flag |= CMD_FLAG_BOOTD; + } +#endif /* CFG_CMD_BOOTD */ + /* found - check max args */ + if ((child->argc - i) > cmdtp->maxargs) { + printf ("Usage:\n%s\n", cmdtp->usage); + return -1; + } +#endif + child->argv+=i; /* XXX horrible hack */ +#ifndef __U_BOOT__ + rcode = x->function(child); +#else + /* OK - call function to do the command */ + + rcode = (cmdtp->cmd) +(cmdtp, flag,child->argc-i,&child->argv[i]); + if ( !cmdtp->repeatable ) + flag_repeat = 0; + + +#endif + child->argv-=i; /* XXX restore hack so free() can work right */ +#ifndef __U_BOOT__ + + restore_redirects(squirrel); +#endif + + return rcode; + } + } +#ifndef __U_BOOT__ + } + + for (i = 0; i < pi->num_progs; i++) { + child = & (pi->progs[i]); + + /* pipes are inserted between pairs of commands */ + if ((i + 1) < pi->num_progs) { + if (pipe(pipefds)<0) perror_msg_and_die("pipe"); + nextout = pipefds[1]; + } else { + nextout=1; + pipefds[0] = -1; + } + + /* XXX test for failed fork()? */ + if (!(child->pid = fork())) { + /* Set the handling for job control signals back to the default. */ + signal(SIGINT, SIG_DFL); + signal(SIGQUIT, SIG_DFL); + signal(SIGTERM, SIG_DFL); + signal(SIGTSTP, SIG_DFL); + signal(SIGTTIN, SIG_DFL); + signal(SIGTTOU, SIG_DFL); + signal(SIGCHLD, SIG_DFL); + + close_all(); + + if (nextin != 0) { + dup2(nextin, 0); + close(nextin); + } + if (nextout != 1) { + dup2(nextout, 1); + close(nextout); + } + if (pipefds[0]!=-1) { + close(pipefds[0]); /* opposite end of our output pipe */ + } + + /* Like bash, explicit redirects override pipes, + * and the pipe fd is available for dup'ing. */ + setup_redirects(child,NULL); + + if (interactive && pi->followup!=PIPE_BG) { + /* If we (the child) win the race, put ourselves in the process + * group whose leader is the first process in this pipe. */ + if (pi->pgrp < 0) { + pi->pgrp = getpid(); + } + if (setpgid(0, pi->pgrp) == 0) { + tcsetpgrp(2, pi->pgrp); + } + } + + pseudo_exec(child); + } + + + /* put our child in the process group whose leader is the + first process in this pipe */ + if (pi->pgrp < 0) { + pi->pgrp = child->pid; + } + /* Don't check for errors. The child may be dead already, + * in which case setpgid returns error code EACCES. */ + setpgid(child->pid, pi->pgrp); + + if (nextin != 0) + close(nextin); + if (nextout != 1) + close(nextout); + + /* If there isn't another process, nextin is garbage + but it doesn't matter */ + nextin = pipefds[0]; + } +#endif + return -1; +} + +static int run_list_real(struct pipe *pi) +{ + char *save_name = NULL; + char **list = NULL; + char **save_list = NULL; + struct pipe *rpipe; + int flag_rep = 0; +#ifndef __U_BOOT__ + int save_num_progs; +#endif + int rcode=0, flag_skip=1; + int flag_restore = 0; + int if_code=0, next_if_code=0; /* need double-buffer to handle elif */ + reserved_style rmode, skip_more_in_this_rmode=RES_XXXX; + /* check syntax for "for" */ + for (rpipe = pi; rpipe; rpipe = rpipe->next) { + if ((rpipe->r_mode == RES_IN || + rpipe->r_mode == RES_FOR) && + (rpipe->next == NULL)) { + syntax(); +#ifdef __U_BOOT__ + flag_repeat = 0; +#endif + return 1; + } + if ((rpipe->r_mode == RES_IN && + (rpipe->next->r_mode == RES_IN && + rpipe->next->progs->argv != NULL))|| + (rpipe->r_mode == RES_FOR && + rpipe->next->r_mode != RES_IN)) { + syntax(); +#ifdef __U_BOOT__ + flag_repeat = 0; +#endif + return 1; + } + } + for (; pi; pi = (flag_restore != 0) ? rpipe : pi->next) { + if (pi->r_mode == RES_WHILE || pi->r_mode == RES_UNTIL || + pi->r_mode == RES_FOR) { +#ifdef __U_BOOT__ + /* check Ctrl-C */ + ctrlc(); + if ((had_ctrlc())) { + return 1; + } +#endif + flag_restore = 0; + if (!rpipe) { + flag_rep = 0; + rpipe = pi; + } + } + rmode = pi->r_mode; + debug_printf("rmode=%d if_code=%d next_if_code=%d skip_more=%d\n", rmode, if_code, next_if_code, skip_more_in_this_rmode); + if (rmode == skip_more_in_this_rmode && flag_skip) { + if (pi->followup == PIPE_SEQ) flag_skip=0; + continue; + } + flag_skip = 1; + skip_more_in_this_rmode = RES_XXXX; + if (rmode == RES_THEN || rmode == RES_ELSE) if_code = next_if_code; + if (rmode == RES_THEN && if_code) continue; + if (rmode == RES_ELSE && !if_code) continue; + if (rmode == RES_ELIF && !if_code) break; + if (rmode == RES_FOR && pi->num_progs) { + if (!list) { + /* if no variable values after "in" we skip "for" */ + if (!pi->next->progs->argv) continue; + /* create list of variable values */ + list = make_list_in(pi->next->progs->argv, + pi->progs->argv[0]); + save_list = list; + save_name = pi->progs->argv[0]; + pi->progs->argv[0] = NULL; + flag_rep = 1; + } + if (!(*list)) { + free(pi->progs->argv[0]); + free(save_list); + list = NULL; + flag_rep = 0; + pi->progs->argv[0] = save_name; +#ifndef __U_BOOT__ + pi->progs->glob_result.gl_pathv[0] = + pi->progs->argv[0]; +#endif + continue; + } else { + /* insert new value from list for variable */ + if (pi->progs->argv[0]) + free(pi->progs->argv[0]); + pi->progs->argv[0] = *list++; +#ifndef __U_BOOT__ + pi->progs->glob_result.gl_pathv[0] = + pi->progs->argv[0]; +#endif + } + } + if (rmode == RES_IN) continue; + if (rmode == RES_DO) { + if (!flag_rep) continue; + } + if ((rmode == RES_DONE)) { + if (flag_rep) { + flag_restore = 1; + } else { + rpipe = NULL; + } + } + if (pi->num_progs == 0) continue; +#ifndef __U_BOOT__ + save_num_progs = pi->num_progs; /* save number of programs */ +#endif + rcode = run_pipe_real(pi); + debug_printf("run_pipe_real returned %d\n",rcode); +#ifndef __U_BOOT__ + if (rcode!=-1) { + /* We only ran a builtin: rcode was set by the return value + * of run_pipe_real(), and we don't need to wait for anything. */ + } else if (pi->followup==PIPE_BG) { + /* XXX check bash's behavior with nontrivial pipes */ + /* XXX compute jobid */ + /* XXX what does bash do with attempts to background builtins? */ + insert_bg_job(pi); + rcode = EXIT_SUCCESS; + } else { + if (interactive) { + /* move the new process group into the foreground */ + if (tcsetpgrp(shell_terminal, pi->pgrp) && errno != ENOTTY) + perror_msg("tcsetpgrp-3"); + rcode = checkjobs(pi); + /* move the shell to the foreground */ + if (tcsetpgrp(shell_terminal, getpgid(0)) && errno != ENOTTY) + perror_msg("tcsetpgrp-4"); + } else { + rcode = checkjobs(pi); + } + debug_printf("checkjobs returned %d\n",rcode); + } + last_return_code=rcode; +#else + if (rcode < -1) { + last_return_code = -rcode - 2; + return -2; /* exit */ + } + last_return_code=(rcode == 0) ? 0 : 1; +#endif +#ifndef __U_BOOT__ + pi->num_progs = save_num_progs; /* restore number of programs */ +#endif + if ( rmode == RES_IF || rmode == RES_ELIF ) + next_if_code=rcode; /* can be overwritten a number of times */ + if (rmode == RES_WHILE) + flag_rep = !last_return_code; + if (rmode == RES_UNTIL) + flag_rep = last_return_code; + if ( (rcode==EXIT_SUCCESS && pi->followup==PIPE_OR) || + (rcode!=EXIT_SUCCESS && pi->followup==PIPE_AND) ) + skip_more_in_this_rmode=rmode; +#ifndef __U_BOOT__ + checkjobs(NULL); +#endif + } + return rcode; +} + +/* broken, of course, but OK for testing */ +static char *indenter(int i) +{ + static char blanks[]=" "; + return &blanks[sizeof(blanks)-i-1]; +} + +/* return code is the exit status of the pipe */ +static int free_pipe(struct pipe *pi, int indent) +{ + char **p; + struct child_prog *child; +#ifndef __U_BOOT__ + struct redir_struct *r, *rnext; +#endif + int a, i, ret_code=0; + char *ind = indenter(indent); + +#ifndef __U_BOOT__ + if (pi->stopped_progs > 0) + return ret_code; + final_printf("%s run pipe: (pid %d)\n",ind,getpid()); +#endif + for (i=0; inum_progs; i++) { + child = &pi->progs[i]; + final_printf("%s command %d:\n",ind,i); + if (child->argv) { + for (a=0,p=child->argv; *p; a++,p++) { + final_printf("%s argv[%d] = %s\n",ind,a,*p); + } +#ifndef __U_BOOT__ + globfree(&child->glob_result); +#else + for (a = child->argc;a >= 0;a--) { + free(child->argv[a]); + } + free(child->argv); + child->argc = 0; +#endif + child->argv=NULL; + } else if (child->group) { +#ifndef __U_BOOT__ + final_printf("%s begin group (subshell:%d)\n",ind, child->subshell); +#endif + ret_code = free_pipe_list(child->group,indent+3); + final_printf("%s end group\n",ind); + } else { + final_printf("%s (nil)\n",ind); + } +#ifndef __U_BOOT__ + for (r=child->redirects; r; r=rnext) { + final_printf("%s redirect %d%s", ind, r->fd, redir_table[r->type].descrip); + if (r->dup == -1) { + /* guard against the case >$FOO, where foo is unset or blank */ + if (r->word.gl_pathv) { + final_printf(" %s\n", *r->word.gl_pathv); + globfree(&r->word); + } + } else { + final_printf("&%d\n", r->dup); + } + rnext=r->next; + free(r); + } + child->redirects=NULL; +#endif + } + free(pi->progs); /* children are an array, they get freed all at once */ + pi->progs=NULL; + return ret_code; +} + +static int free_pipe_list(struct pipe *head, int indent) +{ + int rcode=0; /* if list has no members */ + struct pipe *pi, *next; + char *ind = indenter(indent); + for (pi=head; pi; pi=next) { + final_printf("%s pipe reserved mode %d\n", ind, pi->r_mode); + rcode = free_pipe(pi, indent); + final_printf("%s pipe followup code %d\n", ind, pi->followup); + next=pi->next; + pi->next=NULL; + free(pi); + } + return rcode; +} + +/* Select which version we will use */ +static int run_list(struct pipe *pi) +{ + int rcode=0; +#ifndef __U_BOOT__ + if (fake_mode==0) { +#endif + rcode = run_list_real(pi); +#ifndef __U_BOOT__ + } +#endif + /* free_pipe_list has the side effect of clearing memory + * In the long run that function can be merged with run_list_real, + * but doing that now would hobble the debugging effort. */ + free_pipe_list(pi,0); + return rcode; +} + +/* The API for glob is arguably broken. This routine pushes a non-matching + * string into the output structure, removing non-backslashed backslashes. + * If someone can prove me wrong, by performing this function within the + * original glob(3) api, feel free to rewrite this routine into oblivion. + * Return code (0 vs. GLOB_NOSPACE) matches glob(3). + * XXX broken if the last character is '\\', check that before calling. + */ +#ifndef __U_BOOT__ +static int globhack(const char *src, int flags, glob_t *pglob) +{ + int cnt=0, pathc; + const char *s; + char *dest; + for (cnt=1, s=src; s && *s; s++) { + if (*s == '\\') s++; + cnt++; + } + dest = malloc(cnt); + if (!dest) return GLOB_NOSPACE; + if (!(flags & GLOB_APPEND)) { + pglob->gl_pathv=NULL; + pglob->gl_pathc=0; + pglob->gl_offs=0; + pglob->gl_offs=0; + } + pathc = ++pglob->gl_pathc; + pglob->gl_pathv = realloc(pglob->gl_pathv, (pathc+1)*sizeof(*pglob->gl_pathv)); + if (pglob->gl_pathv == NULL) return GLOB_NOSPACE; + pglob->gl_pathv[pathc-1]=dest; + pglob->gl_pathv[pathc]=NULL; + for (s=src; s && *s; s++, dest++) { + if (*s == '\\') s++; + *dest = *s; + } + *dest='\0'; + return 0; +} + +/* XXX broken if the last character is '\\', check that before calling */ +static int glob_needed(const char *s) +{ + for (; *s; s++) { + if (*s == '\\') s++; + if (strchr("*[?",*s)) return 1; + } + return 0; +} + +#if 0 +static void globprint(glob_t *pglob) +{ + int i; + debug_printf("glob_t at %p:\n", pglob); + debug_printf(" gl_pathc=%d gl_pathv=%p gl_offs=%d gl_flags=%d\n", + pglob->gl_pathc, pglob->gl_pathv, pglob->gl_offs, pglob->gl_flags); + for (i=0; igl_pathc; i++) + debug_printf("pglob->gl_pathv[%d] = %p = %s\n", i, + pglob->gl_pathv[i], pglob->gl_pathv[i]); +} +#endif + +static int xglob(o_string *dest, int flags, glob_t *pglob) +{ + int gr; + + /* short-circuit for null word */ + /* we can code this better when the debug_printf's are gone */ + if (dest->length == 0) { + if (dest->nonnull) { + /* bash man page calls this an "explicit" null */ + gr = globhack(dest->data, flags, pglob); + debug_printf("globhack returned %d\n",gr); + } else { + return 0; + } + } else if (glob_needed(dest->data)) { + gr = glob(dest->data, flags, NULL, pglob); + debug_printf("glob returned %d\n",gr); + if (gr == GLOB_NOMATCH) { + /* quote removal, or more accurately, backslash removal */ + gr = globhack(dest->data, flags, pglob); + debug_printf("globhack returned %d\n",gr); + } + } else { + gr = globhack(dest->data, flags, pglob); + debug_printf("globhack returned %d\n",gr); + } + if (gr == GLOB_NOSPACE) + error_msg_and_die("out of memory during glob"); + if (gr != 0) { /* GLOB_ABORTED ? */ + error_msg("glob(3) error %d",gr); + } + /* globprint(glob_target); */ + return gr; +} +#endif + +#ifdef __U_BOOT__ +static char *get_dollar_var(char ch); +#endif + +/* This is used to get/check local shell variables */ +static char *get_local_var(const char *s) +{ + struct variables *cur; + + if (!s) + return NULL; + +#ifdef __U_BOOT__ + if (*s == '$') + return get_dollar_var(s[1]); +#endif + + for (cur = top_vars; cur; cur=cur->next) + if(strcmp(cur->name, s)==0) + return cur->value; + return NULL; +} + +/* This is used to set local shell variables + flg_export==0 if only local (not exporting) variable + flg_export==1 if "new" exporting environ + flg_export>1 if current startup environ (not call putenv()) */ +static int set_local_var(const char *s, int flg_export) +{ + char *name, *value; + int result=0; + struct variables *cur; + +#ifdef __U_BOOT__ + /* might be possible! */ + if (!isalpha(*s)) + return -1; +#endif + + name=strdup(s); + +#ifdef __U_BOOT__ + if (getenv(name) != NULL) { + printf ("ERROR: " + "There is a global environment variable with the same name.\n"); + free(name); + return -1; + } +#endif + /* Assume when we enter this function that we are already in + * NAME=VALUE format. So the first order of business is to + * split 's' on the '=' into 'name' and 'value' */ + value = strchr(name, '='); + if (value==0 && ++value==0) { + free(name); + return -1; + } + *value++ = 0; + + for(cur = top_vars; cur; cur = cur->next) { + if(strcmp(cur->name, name)==0) + break; + } + + if(cur) { + if(strcmp(cur->value, value)==0) { + if(flg_export>0 && cur->flg_export==0) + cur->flg_export=flg_export; + else + result++; + } else { + if(cur->flg_read_only) { + error_msg("%s: readonly variable", name); + result = -1; + } else { + if(flg_export>0 || cur->flg_export>1) + cur->flg_export=1; + free(cur->value); + + cur->value = strdup(value); + } + } + } else { + cur = malloc(sizeof(struct variables)); + if(!cur) { + result = -1; + } else { + cur->name = strdup(name); + if(cur->name == 0) { + free(cur); + result = -1; + } else { + struct variables *bottom = top_vars; + cur->value = strdup(value); + cur->next = 0; + cur->flg_export = flg_export; + cur->flg_read_only = 0; + while(bottom->next) bottom=bottom->next; + bottom->next = cur; + } + } + } + +#ifndef __U_BOOT__ + if(result==0 && cur->flg_export==1) { + *(value-1) = '='; + result = putenv(name); + } else { +#endif + free(name); +#ifndef __U_BOOT__ + if(result>0) /* equivalent to previous set */ + result = 0; + } +#endif + return result; +} + +#ifndef __U_BOOT__ +static void unset_local_var(const char *name) +{ + struct variables *cur; + + if (name) { + for (cur = top_vars; cur; cur=cur->next) { + if(strcmp(cur->name, name)==0) + break; + } + if(cur!=0) { + struct variables *next = top_vars; + if(cur->flg_read_only) { + error_msg("%s: readonly variable", name); + return; + } else { + if(cur->flg_export) + unsetenv(cur->name); + free(cur->name); + free(cur->value); + while (next->next != cur) + next = next->next; + next->next = cur->next; + } + free(cur); + } + } +} +#endif + +static int is_assignment(const char *s) +{ + if (s == NULL) + return 0; + + if (!isalpha(*s)) return 0; + ++s; + while(isalnum(*s) || *s=='_') ++s; + return *s=='='; +} + +#ifndef __U_BOOT__ +/* the src parameter allows us to peek forward to a possible &n syntax + * for file descriptor duplication, e.g., "2>&1". + * Return code is 0 normally, 1 if a syntax error is detected in src. + * Resource errors (in xmalloc) cause the process to exit */ +static int setup_redirect(struct p_context *ctx, int fd, redir_type style, + struct in_str *input) +{ + struct child_prog *child=ctx->child; + struct redir_struct *redir = child->redirects; + struct redir_struct *last_redir=NULL; + + /* Create a new redir_struct and drop it onto the end of the linked list */ + while(redir) { + last_redir=redir; + redir=redir->next; + } + redir = xmalloc(sizeof(struct redir_struct)); + redir->next=NULL; + redir->word.gl_pathv=NULL; + if (last_redir) { + last_redir->next=redir; + } else { + child->redirects=redir; + } + + redir->type=style; + redir->fd= (fd==-1) ? redir_table[style].default_fd : fd ; + + debug_printf("Redirect type %d%s\n", redir->fd, redir_table[style].descrip); + + /* Check for a '2>&1' type redirect */ + redir->dup = redirect_dup_num(input); + if (redir->dup == -2) return 1; /* syntax error */ + if (redir->dup != -1) { + /* Erik had a check here that the file descriptor in question + * is legit; I postpone that to "run time" + * A "-" representation of "close me" shows up as a -3 here */ + debug_printf("Duplicating redirect '%d>&%d'\n", redir->fd, redir->dup); + } else { + /* We do _not_ try to open the file that src points to, + * since we need to return and let src be expanded first. + * Set ctx->pending_redirect, so we know what to do at the + * end of the next parsed word. + */ + ctx->pending_redirect = redir; + } + return 0; +} +#endif + +struct pipe *new_pipe(void) { + struct pipe *pi; + pi = xmalloc(sizeof(struct pipe)); + pi->num_progs = 0; + pi->progs = NULL; + pi->next = NULL; + pi->followup = 0; /* invalid */ + pi->r_mode = RES_NONE; + return pi; +} + +static void initialize_context(struct p_context *ctx) +{ + ctx->pipe=NULL; +#ifndef __U_BOOT__ + ctx->pending_redirect=NULL; +#endif + ctx->child=NULL; + ctx->list_head=new_pipe(); + ctx->pipe=ctx->list_head; + ctx->w=RES_NONE; + ctx->stack=NULL; +#ifdef __U_BOOT__ + ctx->old_flag=0; +#endif + done_command(ctx); /* creates the memory for working child */ +} + +/* normal return is 0 + * if a reserved word is found, and processed, return 1 + * should handle if, then, elif, else, fi, for, while, until, do, done. + * case, function, and select are obnoxious, save those for later. + */ +struct reserved_combo { + char *literal; + int code; + long flag; +}; +/* Mostly a list of accepted follow-up reserved words. + * FLAG_END means we are done with the sequence, and are ready + * to turn the compound list into a command. + * FLAG_START means the word must start a new compound list. + */ +static struct reserved_combo reserved_list[] = { + { "if", RES_IF, FLAG_THEN | FLAG_START }, + { "then", RES_THEN, FLAG_ELIF | FLAG_ELSE | FLAG_FI }, + { "elif", RES_ELIF, FLAG_THEN }, + { "else", RES_ELSE, FLAG_FI }, + { "fi", RES_FI, FLAG_END }, + { "for", RES_FOR, FLAG_IN | FLAG_START }, + { "while", RES_WHILE, FLAG_DO | FLAG_START }, + { "until", RES_UNTIL, FLAG_DO | FLAG_START }, + { "in", RES_IN, FLAG_DO }, + { "do", RES_DO, FLAG_DONE }, + { "done", RES_DONE, FLAG_END } +}; +#define NRES (sizeof(reserved_list)/sizeof(struct reserved_combo)) + +int reserved_word(o_string *dest, struct p_context *ctx) +{ + struct reserved_combo *r; + for (r=reserved_list; + rdata, r->literal) == 0) { + debug_printf("found reserved word %s, code %d\n",r->literal,r->code); + if (r->flag & FLAG_START) { + struct p_context *new = xmalloc(sizeof(struct p_context)); + debug_printf("push stack\n"); + if (ctx->w == RES_IN || ctx->w == RES_FOR) { + syntax(); + free(new); + ctx->w = RES_SNTX; + b_reset(dest); + return 1; + } + *new = *ctx; /* physical copy */ + initialize_context(ctx); + ctx->stack=new; + } else if ( ctx->w == RES_NONE || ! (ctx->old_flag & (1<code))) { + syntax(); + ctx->w = RES_SNTX; + b_reset(dest); + return 1; + } + ctx->w=r->code; + ctx->old_flag = r->flag; + if (ctx->old_flag & FLAG_END) { + struct p_context *old; + debug_printf("pop stack\n"); + done_pipe(ctx,PIPE_SEQ); + old = ctx->stack; + old->child->group = ctx->list_head; +#ifndef __U_BOOT__ + old->child->subshell = 0; +#endif + *ctx = *old; /* physical copy */ + free(old); + } + b_reset (dest); + return 1; + } + } + return 0; +} + +/* normal return is 0. + * Syntax or xglob errors return 1. */ +static int done_word(o_string *dest, struct p_context *ctx) +{ + struct child_prog *child=ctx->child; +#ifndef __U_BOOT__ + glob_t *glob_target; + int gr, flags = 0; +#else + char *str, *s; + int argc, cnt; +#endif + + debug_printf("done_word: %s %p\n", dest->data, child); + if (dest->length == 0 && !dest->nonnull) { + debug_printf(" true null, ignored\n"); + return 0; + } +#ifndef __U_BOOT__ + if (ctx->pending_redirect) { + glob_target = &ctx->pending_redirect->word; + } else { +#endif + if (child->group) { + syntax(); + return 1; /* syntax error, groups and arglists don't mix */ + } + if (!child->argv && (ctx->type & FLAG_PARSE_SEMICOLON)) { + debug_printf("checking %s for reserved-ness\n",dest->data); + if (reserved_word(dest,ctx)) return ctx->w==RES_SNTX; + } +#ifndef __U_BOOT__ + glob_target = &child->glob_result; + if (child->argv) flags |= GLOB_APPEND; +#else + for (cnt = 1, s = dest->data; s && *s; s++) { + if (*s == '\\') s++; + cnt++; + } + str = malloc(cnt); + if (!str) return 1; + if ( child->argv == NULL) { + child->argc=0; + } + argc = ++child->argc; + child->argv = realloc(child->argv, (argc+1)*sizeof(*child->argv)); + if (child->argv == NULL) return 1; + child->argv[argc-1]=str; + child->argv[argc]=NULL; + for (s = dest->data; s && *s; s++,str++) { + if (*s == '\\') s++; + *str = *s; + } + *str = '\0'; +#endif +#ifndef __U_BOOT__ + } + gr = xglob(dest, flags, glob_target); + if (gr != 0) return 1; +#endif + + b_reset(dest); +#ifndef __U_BOOT__ + if (ctx->pending_redirect) { + ctx->pending_redirect=NULL; + if (glob_target->gl_pathc != 1) { + error_msg("ambiguous redirect"); + return 1; + } + } else { + child->argv = glob_target->gl_pathv; + } +#endif + if (ctx->w == RES_FOR) { + done_word(dest,ctx); + done_pipe(ctx,PIPE_SEQ); + } + return 0; +} + +/* The only possible error here is out of memory, in which case + * xmalloc exits. */ +static int done_command(struct p_context *ctx) +{ + /* The child is really already in the pipe structure, so + * advance the pipe counter and make a new, null child. + * Only real trickiness here is that the uncommitted + * child structure, to which ctx->child points, is not + * counted in pi->num_progs. */ + struct pipe *pi=ctx->pipe; + struct child_prog *prog=ctx->child; + + if (prog && prog->group == NULL + && prog->argv == NULL +#ifndef __U_BOOT__ + && prog->redirects == NULL) { +#else + ) { +#endif + debug_printf("done_command: skipping null command\n"); + return 0; + } else if (prog) { + pi->num_progs++; + debug_printf("done_command: num_progs incremented to %d\n",pi->num_progs); + } else { + debug_printf("done_command: initializing\n"); + } + pi->progs = xrealloc(pi->progs, sizeof(*pi->progs) * (pi->num_progs+1)); + + prog = pi->progs + pi->num_progs; +#ifndef __U_BOOT__ + prog->redirects = NULL; +#endif + prog->argv = NULL; +#ifndef __U_BOOT__ + prog->is_stopped = 0; +#endif + prog->group = NULL; +#ifndef __U_BOOT__ + prog->glob_result.gl_pathv = NULL; + prog->family = pi; +#endif + prog->sp = 0; + ctx->child = prog; + prog->type = ctx->type; + + /* but ctx->pipe and ctx->list_head remain unchanged */ + return 0; +} + +static int done_pipe(struct p_context *ctx, pipe_style type) +{ + struct pipe *new_p; + done_command(ctx); /* implicit closure of previous command */ + debug_printf("done_pipe, type %d\n", type); + ctx->pipe->followup = type; + ctx->pipe->r_mode = ctx->w; + new_p=new_pipe(); + ctx->pipe->next = new_p; + ctx->pipe = new_p; + ctx->child = NULL; + done_command(ctx); /* set up new pipe to accept commands */ + return 0; +} + +#ifndef __U_BOOT__ +/* peek ahead in the in_str to find out if we have a "&n" construct, + * as in "2>&1", that represents duplicating a file descriptor. + * returns either -2 (syntax error), -1 (no &), or the number found. + */ +static int redirect_dup_num(struct in_str *input) +{ + int ch, d=0, ok=0; + ch = b_peek(input); + if (ch != '&') return -1; + + b_getch(input); /* get the & */ + ch=b_peek(input); + if (ch == '-') { + b_getch(input); + return -3; /* "-" represents "close me" */ + } + while (isdigit(ch)) { + d = d*10+(ch-'0'); + ok=1; + b_getch(input); + ch = b_peek(input); + } + if (ok) return d; + + error_msg("ambiguous redirect"); + return -2; +} + +/* If a redirect is immediately preceded by a number, that number is + * supposed to tell which file descriptor to redirect. This routine + * looks for such preceding numbers. In an ideal world this routine + * needs to handle all the following classes of redirects... + * echo 2>foo # redirects fd 2 to file "foo", nothing passed to echo + * echo 49>foo # redirects fd 49 to file "foo", nothing passed to echo + * echo -2>foo # redirects fd 1 to file "foo", "-2" passed to echo + * echo 49x>foo # redirects fd 1 to file "foo", "49x" passed to echo + * A -1 output from this program means no valid number was found, so the + * caller should use the appropriate default for this redirection. + */ +static int redirect_opt_num(o_string *o) +{ + int num; + + if (o->length==0) return -1; + for(num=0; numlength; num++) { + if (!isdigit(*(o->data+num))) { + return -1; + } + } + /* reuse num (and save an int) */ + num=atoi(o->data); + b_reset(o); + return num; +} + +FILE *generate_stream_from_list(struct pipe *head) +{ + FILE *pf; +#if 1 + int pid, channel[2]; + if (pipe(channel)<0) perror_msg_and_die("pipe"); + pid=fork(); + if (pid<0) { + perror_msg_and_die("fork"); + } else if (pid==0) { + close(channel[0]); + if (channel[1] != 1) { + dup2(channel[1],1); + close(channel[1]); + } +#if 0 +#define SURROGATE "surrogate response" + write(1,SURROGATE,sizeof(SURROGATE)); + _exit(run_list(head)); +#else + _exit(run_list_real(head)); /* leaks memory */ +#endif + } + debug_printf("forked child %d\n",pid); + close(channel[1]); + pf = fdopen(channel[0],"r"); + debug_printf("pipe on FILE *%p\n",pf); +#else + free_pipe_list(head,0); + pf=popen("echo surrogate response","r"); + debug_printf("started fake pipe on FILE *%p\n",pf); +#endif + return pf; +} + +/* this version hacked for testing purposes */ +/* return code is exit status of the process that is run. */ +static int process_command_subs(o_string *dest, struct p_context *ctx, struct in_str *input, int subst_end) +{ + int retcode; + o_string result=NULL_O_STRING; + struct p_context inner; + FILE *p; + struct in_str pipe_str; + initialize_context(&inner); + + /* recursion to generate command */ + retcode = parse_stream(&result, &inner, input, subst_end); + if (retcode != 0) return retcode; /* syntax error or EOF */ + done_word(&result, &inner); + done_pipe(&inner, PIPE_SEQ); + b_free(&result); + + p=generate_stream_from_list(inner.list_head); + if (p==NULL) return 1; + mark_open(fileno(p)); + setup_file_in_str(&pipe_str, p); + + /* now send results of command back into original context */ + retcode = parse_stream(dest, ctx, &pipe_str, '\0'); + /* XXX In case of a syntax error, should we try to kill the child? + * That would be tough to do right, so just read until EOF. */ + if (retcode == 1) { + while (b_getch(&pipe_str)!=EOF) { /* discard */ }; + } + + debug_printf("done reading from pipe, pclose()ing\n"); + /* This is the step that wait()s for the child. Should be pretty + * safe, since we just read an EOF from its stdout. We could try + * to better, by using wait(), and keeping track of background jobs + * at the same time. That would be a lot of work, and contrary + * to the KISS philosophy of this program. */ + mark_closed(fileno(p)); + retcode=pclose(p); + free_pipe_list(inner.list_head,0); + debug_printf("pclosed, retcode=%d\n",retcode); + /* XXX this process fails to trim a single trailing newline */ + return retcode; +} + +static int parse_group(o_string *dest, struct p_context *ctx, + struct in_str *input, int ch) +{ + int rcode, endch=0; + struct p_context sub; + struct child_prog *child = ctx->child; + if (child->argv) { + syntax(); + return 1; /* syntax error, groups and arglists don't mix */ + } + initialize_context(&sub); + switch(ch) { + case '(': endch=')'; child->subshell=1; break; + case '{': endch='}'; break; + default: syntax(); /* really logic error */ + } + rcode=parse_stream(dest,&sub,input,endch); + done_word(dest,&sub); /* finish off the final word in the subcontext */ + done_pipe(&sub, PIPE_SEQ); /* and the final command there, too */ + child->group = sub.list_head; + return rcode; + /* child remains "open", available for possible redirects */ +} +#endif + +/* basically useful version until someone wants to get fancier, + * see the bash man page under "Parameter Expansion" */ +static char *lookup_param(char *src) +{ + char *p; + + if (!src) + return NULL; + + p = getenv(src); + if (!p) + p = get_local_var(src); + + return p; +} + +#ifdef __U_BOOT__ +static char *get_dollar_var(char ch) +{ + static char buf[40]; + + buf[0] = '\0'; + switch (ch) { + case '?': + sprintf(buf, "%u", (unsigned int)last_return_code); + break; + default: + return NULL; + } + return buf; +} +#endif + +/* return code: 0 for OK, 1 for syntax error */ +static int handle_dollar(o_string *dest, struct p_context *ctx, struct in_str *input) +{ +#ifndef __U_BOOT__ + int i, advance=0; +#else + int advance=0; +#endif +#ifndef __U_BOOT__ + char sep[]=" "; +#endif + int ch = input->peek(input); /* first character after the $ */ + debug_printf("handle_dollar: ch=%c\n",ch); + if (isalpha(ch)) { + b_addchr(dest, SPECIAL_VAR_SYMBOL); + ctx->child->sp++; + while(ch=b_peek(input),isalnum(ch) || ch=='_') { + b_getch(input); + b_addchr(dest,ch); + } + b_addchr(dest, SPECIAL_VAR_SYMBOL); +#ifndef __U_BOOT__ + } else if (isdigit(ch)) { + i = ch-'0'; /* XXX is $0 special? */ + if (i 0) b_adduint(dest, last_bg_pid); + advance = 1; + break; +#endif + case '?': +#ifndef __U_BOOT__ + b_adduint(dest,last_return_code); +#else + ctx->child->sp++; + b_addchr(dest, SPECIAL_VAR_SYMBOL); + b_addchr(dest, '$'); + b_addchr(dest, '?'); + b_addchr(dest, SPECIAL_VAR_SYMBOL); +#endif + advance = 1; + break; +#ifndef __U_BOOT__ + case '#': + b_adduint(dest,global_argc ? global_argc-1 : 0); + advance = 1; + break; +#endif + case '{': + b_addchr(dest, SPECIAL_VAR_SYMBOL); + ctx->child->sp++; + b_getch(input); + /* XXX maybe someone will try to escape the '}' */ + while(ch=b_getch(input),ch!=EOF && ch!='}') { + b_addchr(dest,ch); + } + if (ch != '}') { + syntax(); + return 1; + } + b_addchr(dest, SPECIAL_VAR_SYMBOL); + break; +#ifndef __U_BOOT__ + case '(': + b_getch(input); + process_command_subs(dest, ctx, input, ')'); + break; + case '*': + sep[0]=ifs[0]; + for (i=1; iquote); + } + /* Eat the character if the flag was set. If the compiler + * is smart enough, we could substitute "b_getch(input);" + * for all the "advance = 1;" above, and also end up with + * a nice size-optimized program. Hah! That'll be the day. + */ + if (advance) b_getch(input); + return 0; +} + +#ifndef __U_BOOT__ +int parse_string(o_string *dest, struct p_context *ctx, const char *src) +{ + struct in_str foo; + setup_string_in_str(&foo, src); + return parse_stream(dest, ctx, &foo, '\0'); +} +#endif + +/* return code is 0 for normal exit, 1 for syntax error */ +int parse_stream(o_string *dest, struct p_context *ctx, + struct in_str *input, int end_trigger) +{ + unsigned int ch, m; +#ifndef __U_BOOT__ + int redir_fd; + redir_type redir_style; +#endif + int next; + + /* Only double-quote state is handled in the state variable dest->quote. + * A single-quote triggers a bypass of the main loop until its mate is + * found. When recursing, quote state is passed in via dest->quote. */ + + debug_printf("parse_stream, end_trigger=%d\n",end_trigger); + while ((ch=b_getch(input))!=EOF) { + m = map[ch]; +#ifdef __U_BOOT__ + if (input->__promptme == 0) return 1; +#endif + next = (ch == '\n') ? 0 : b_peek(input); + + debug_printf("parse_stream: ch=%c (%d) m=%d quote=%d - %c\n", + ch >= ' ' ? ch : '.', ch, m, + dest->quote, ctx->stack == NULL ? '*' : '.'); + + if (m==0 || ((m==1 || m==2) && dest->quote)) { + b_addqchr(dest, ch, dest->quote); + } else { + if (m==2) { /* unquoted IFS */ + if (done_word(dest, ctx)) { + return 1; + } + /* If we aren't performing a substitution, treat a newline as a + * command separator. */ + if (end_trigger != '\0' && ch=='\n') + done_pipe(ctx,PIPE_SEQ); + } + if (ch == end_trigger && !dest->quote && ctx->w==RES_NONE) { + debug_printf("leaving parse_stream (triggered)\n"); + return 0; + } +#if 0 + if (ch=='\n') { + /* Yahoo! Time to run with it! */ + done_pipe(ctx,PIPE_SEQ); + run_list(ctx->list_head); + initialize_context(ctx); + } +#endif + if (m!=2) switch (ch) { + case '#': + if (dest->length == 0 && !dest->quote) { + while(ch=b_peek(input),ch!=EOF && ch!='\n') { b_getch(input); } + } else { + b_addqchr(dest, ch, dest->quote); + } + break; + case '\\': + if (next == EOF) { + syntax(); + return 1; + } + b_addqchr(dest, '\\', dest->quote); + b_addqchr(dest, b_getch(input), dest->quote); + break; + case '$': + if (handle_dollar(dest, ctx, input)!=0) return 1; + break; + case '\'': + dest->nonnull = 1; + while(ch=b_getch(input),ch!=EOF && ch!='\'') { +#ifdef __U_BOOT__ + if(input->__promptme == 0) return 1; +#endif + b_addchr(dest,ch); + } + if (ch==EOF) { + syntax(); + return 1; + } + break; + case '"': + dest->nonnull = 1; + dest->quote = !dest->quote; + break; +#ifndef __U_BOOT__ + case '`': + process_command_subs(dest, ctx, input, '`'); + break; + case '>': + redir_fd = redirect_opt_num(dest); + done_word(dest, ctx); + redir_style=REDIRECT_OVERWRITE; + if (next == '>') { + redir_style=REDIRECT_APPEND; + b_getch(input); + } else if (next == '(') { + syntax(); /* until we support >(list) Process Substitution */ + return 1; + } + setup_redirect(ctx, redir_fd, redir_style, input); + break; + case '<': + redir_fd = redirect_opt_num(dest); + done_word(dest, ctx); + redir_style=REDIRECT_INPUT; + if (next == '<') { + redir_style=REDIRECT_HEREIS; + b_getch(input); + } else if (next == '>') { + redir_style=REDIRECT_IO; + b_getch(input); + } else if (next == '(') { + syntax(); /* until we support <(list) Process Substitution */ + return 1; + } + setup_redirect(ctx, redir_fd, redir_style, input); + break; +#endif + case ';': + done_word(dest, ctx); + done_pipe(ctx,PIPE_SEQ); + break; + case '&': + done_word(dest, ctx); + if (next=='&') { + b_getch(input); + done_pipe(ctx,PIPE_AND); + } else { +#ifndef __U_BOOT__ + done_pipe(ctx,PIPE_BG); +#else + syntax_err(); + return 1; +#endif + } + break; + case '|': + done_word(dest, ctx); + if (next=='|') { + b_getch(input); + done_pipe(ctx,PIPE_OR); + } else { + /* we could pick up a file descriptor choice here + * with redirect_opt_num(), but bash doesn't do it. + * "echo foo 2| cat" yields "foo 2". */ +#ifndef __U_BOOT__ + done_command(ctx); +#else + syntax_err(); + return 1; +#endif + } + break; +#ifndef __U_BOOT__ + case '(': + case '{': + if (parse_group(dest, ctx, input, ch)!=0) return 1; + break; + case ')': + case '}': + syntax(); /* Proper use of this character caught by end_trigger */ + return 1; + break; +#endif + default: + syntax(); /* this is really an internal logic error */ + return 1; + } + } + } + /* complain if quote? No, maybe we just finished a command substitution + * that was quoted. Example: + * $ echo "`cat foo` plus more" + * and we just got the EOF generated by the subshell that ran "cat foo" + * The only real complaint is if we got an EOF when end_trigger != '\0', + * that is, we were really supposed to get end_trigger, and never got + * one before the EOF. Can't use the standard "syntax error" return code, + * so that parse_stream_outer can distinguish the EOF and exit smoothly. */ + debug_printf("leaving parse_stream (EOF)\n"); + if (end_trigger != '\0') return -1; + return 0; +} + +void mapset(const unsigned char *set, int code) +{ + const unsigned char *s; + for (s=set; *s; s++) map[*s] = code; +} + +void update_ifs_map(void) +{ + /* char *ifs and char map[256] are both globals. */ + ifs = (uchar *)getenv("IFS"); + if (ifs == NULL) ifs=(uchar *)" \t\n"; + /* Precompute a list of 'flow through' behavior so it can be treated + * quickly up front. Computation is necessary because of IFS. + * Special case handling of IFS == " \t\n" is not implemented. + * The map[] array only really needs two bits each, and on most machines + * that would be faster because of the reduced L1 cache footprint. + */ + memset(map,0,sizeof(map)); /* most characters flow through always */ +#ifndef __U_BOOT__ + mapset((uchar *)"\\$'\"`", 3); /* never flow through */ + mapset((uchar *)"<>;&|(){}#", 1); /* flow through if quoted */ +#else + mapset((uchar *)"\\$'\"", 3); /* never flow through */ + mapset((uchar *)";&|#", 1); /* flow through if quoted */ +#endif + mapset(ifs, 2); /* also flow through if quoted */ +} + +/* most recursion does not come through here, the exeception is + * from builtin_source() */ +int parse_stream_outer(struct in_str *inp, int flag) +{ + + struct p_context ctx; + o_string temp=NULL_O_STRING; + int rcode; +#ifdef __U_BOOT__ + int code = 0; +#endif + do { + ctx.type = flag; + initialize_context(&ctx); + update_ifs_map(); + if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset((uchar *)";$&|", 0); + inp->promptmode=1; + rcode = parse_stream(&temp, &ctx, inp, '\n'); +#ifdef __U_BOOT__ + if (rcode == 1) flag_repeat = 0; +#endif + if (rcode != 1 && ctx.old_flag != 0) { + syntax(); +#ifdef __U_BOOT__ + flag_repeat = 0; +#endif + } + if (rcode != 1 && ctx.old_flag == 0) { + done_word(&temp, &ctx); + done_pipe(&ctx,PIPE_SEQ); +#ifndef __U_BOOT__ + run_list(ctx.list_head); +#else + code = run_list(ctx.list_head); + if (code == -2) { /* exit */ + b_free(&temp); + code = 0; + /* XXX hackish way to not allow exit from main loop */ + if (inp->peek == file_peek) { + printf("exit not allowed from main input shell.\n"); + continue; + } + break; + } + if (code == -1) + flag_repeat = 0; +#endif + } else { + if (ctx.old_flag != 0) { + free(ctx.stack); + b_reset(&temp); + } +#ifdef __U_BOOT__ + if (inp->__promptme == 0) printf("\n"); + inp->__promptme = 1; +#endif + temp.nonnull = 0; + temp.quote = 0; + inp->p = NULL; + free_pipe_list(ctx.list_head,0); + } + b_free(&temp); + } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP)); /* loop on syntax errors, return on EOF */ +#ifndef __U_BOOT__ + return 0; +#else + return (code != 0) ? 1 : 0; +#endif /* __U_BOOT__ */ +} + +#ifndef __U_BOOT__ +static int parse_string_outer(const char *s, int flag) +#else +int parse_string_outer(char *s, int flag) +#endif /* __U_BOOT__ */ +{ + struct in_str input; +#ifdef __U_BOOT__ + char *p = NULL; + int rcode; + if ( !s || !*s) + return 1; + if (!(p = strchr(s, '\n')) || *++p) { + p = xmalloc(strlen(s) + 2); + strcpy(p, s); + strcat(p, "\n"); + setup_string_in_str(&input, p); + rcode = parse_stream_outer(&input, flag); + free(p); + return rcode; + } else { +#endif + setup_string_in_str(&input, s); + return parse_stream_outer(&input, flag); +#ifdef __U_BOOT__ + } +#endif +} + +#ifndef __U_BOOT__ +static int parse_file_outer(FILE *f) +#else +int parse_file_outer(void) +#endif +{ + int rcode; + struct in_str input; +#ifndef __U_BOOT__ + setup_file_in_str(&input, f); +#else + setup_file_in_str(&input); +#endif + rcode = parse_stream_outer(&input, FLAG_PARSE_SEMICOLON); + return rcode; +} + +#ifdef __U_BOOT__ +static void u_boot_hush_reloc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long addr; + struct reserved_combo *r; + + for (r=reserved_list; rliteral) + gd->reloc_off; + r->literal = (char *)addr; + } +} + +int u_boot_hush_start(void) +{ + if (top_vars == NULL) { + top_vars = malloc(sizeof(struct variables)); + top_vars->name = "HUSH_VERSION"; + top_vars->value = "0.01"; + top_vars->next = 0; + top_vars->flg_export = 0; + top_vars->flg_read_only = 1; + u_boot_hush_reloc(); + } + return 0; +} + +static void *xmalloc(size_t size) +{ + void *p = NULL; + + if (!(p = malloc(size))) { + printf("ERROR : memory not allocated\n"); + for(;;); + } + return p; +} + +static void *xrealloc(void *ptr, size_t size) +{ + void *p = NULL; + + if (!(p = realloc(ptr, size))) { + printf("ERROR : memory not allocated\n"); + for(;;); + } + return p; +} +#endif /* __U_BOOT__ */ + +#ifndef __U_BOOT__ +/* Make sure we have a controlling tty. If we get started under a job + * aware app (like bash for example), make sure we are now in charge so + * we don't fight over who gets the foreground */ +static void setup_job_control(void) +{ + static pid_t shell_pgrp; + /* Loop until we are in the foreground. */ + while (tcgetpgrp (shell_terminal) != (shell_pgrp = getpgrp ())) + kill (- shell_pgrp, SIGTTIN); + + /* Ignore interactive and job-control signals. */ + signal(SIGINT, SIG_IGN); + signal(SIGQUIT, SIG_IGN); + signal(SIGTERM, SIG_IGN); + signal(SIGTSTP, SIG_IGN); + signal(SIGTTIN, SIG_IGN); + signal(SIGTTOU, SIG_IGN); + signal(SIGCHLD, SIG_IGN); + + /* Put ourselves in our own process group. */ + setsid(); + shell_pgrp = getpid (); + setpgid (shell_pgrp, shell_pgrp); + + /* Grab control of the terminal. */ + tcsetpgrp(shell_terminal, shell_pgrp); +} + +int hush_main(int argc, char **argv) +{ + int opt; + FILE *input; + char **e = environ; + + /* XXX what should these be while sourcing /etc/profile? */ + global_argc = argc; + global_argv = argv; + + /* (re?) initialize globals. Sometimes hush_main() ends up calling + * hush_main(), therefore we cannot rely on the BSS to zero out this + * stuff. Reset these to 0 every time. */ + ifs = NULL; + /* map[] is taken care of with call to update_ifs_map() */ + fake_mode = 0; + interactive = 0; + close_me_head = NULL; + last_bg_pid = 0; + job_list = NULL; + last_jobid = 0; + + /* Initialize some more globals to non-zero values */ + set_cwd(); +#ifdef CONFIG_FEATURE_COMMAND_EDITING + cmdedit_set_initial_prompt(); +#else + PS1 = NULL; +#endif + PS2 = "> "; + + /* initialize our shell local variables with the values + * currently living in the environment */ + if (e) { + for (; *e; e++) + set_local_var(*e, 2); /* without call putenv() */ + } + + last_return_code=EXIT_SUCCESS; + + + if (argv[0] && argv[0][0] == '-') { + debug_printf("\nsourcing /etc/profile\n"); + if ((input = fopen("/etc/profile", "r")) != NULL) { + mark_open(fileno(input)); + parse_file_outer(input); + mark_closed(fileno(input)); + fclose(input); + } + } + input=stdin; + + while ((opt = getopt(argc, argv, "c:xif")) > 0) { + switch (opt) { + case 'c': + { + global_argv = argv+optind; + global_argc = argc-optind; + opt = parse_string_outer(optarg, FLAG_PARSE_SEMICOLON); + goto final_return; + } + break; + case 'i': + interactive++; + break; + case 'f': + fake_mode++; + break; + default: +#ifndef BB_VER + fprintf(stderr, "Usage: sh [FILE]...\n" + " or: sh -c command [args]...\n\n"); + exit(EXIT_FAILURE); +#else + show_usage(); +#endif + } + } + /* A shell is interactive if the `-i' flag was given, or if all of + * the following conditions are met: + * no -c command + * no arguments remaining or the -s flag given + * standard input is a terminal + * standard output is a terminal + * Refer to Posix.2, the description of the `sh' utility. */ + if (argv[optind]==NULL && input==stdin && + isatty(fileno(stdin)) && isatty(fileno(stdout))) { + interactive++; + } + + debug_printf("\ninteractive=%d\n", interactive); + if (interactive) { + /* Looks like they want an interactive shell */ +#ifndef CONFIG_FEATURE_SH_EXTRA_QUIET + printf( "\n\n" BB_BANNER " hush - the humble shell v0.01 (testing)\n"); + printf( "Enter 'help' for a list of built-in commands.\n\n"); +#endif + setup_job_control(); + } + + if (argv[optind]==NULL) { + opt=parse_file_outer(stdin); + goto final_return; + } + + debug_printf("\nrunning script '%s'\n", argv[optind]); + global_argv = argv+optind; + global_argc = argc-optind; + input = xfopen(argv[optind], "r"); + opt = parse_file_outer(input); + +#ifdef CONFIG_FEATURE_CLEAN_UP + fclose(input); + if (cwd && cwd != unknown) + free((char*)cwd); + { + struct variables *cur, *tmp; + for(cur = top_vars; cur; cur = tmp) { + tmp = cur->next; + if (!cur->flg_read_only) { + free(cur->name); + free(cur->value); + free(cur); + } + } + } +#endif + +final_return: + return(opt?opt:last_return_code); +} +#endif + +static char *insert_var_value(char *inp) +{ + int res_str_len = 0; + int len; + int done = 0; + char *p, *p1, *res_str = NULL; + + while ((p = strchr(inp, SPECIAL_VAR_SYMBOL))) { + if (p != inp) { + len = p - inp; + res_str = xrealloc(res_str, (res_str_len + len)); + strncpy((res_str + res_str_len), inp, len); + res_str_len += len; + } + inp = ++p; + p = strchr(inp, SPECIAL_VAR_SYMBOL); + *p = '\0'; + if ((p1 = lookup_param(inp))) { + len = res_str_len + strlen(p1); + res_str = xrealloc(res_str, (1 + len)); + strcpy((res_str + res_str_len), p1); + res_str_len = len; + } + *p = SPECIAL_VAR_SYMBOL; + inp = ++p; + done = 1; + } + if (done) { + res_str = xrealloc(res_str, (1 + res_str_len + strlen(inp))); + strcpy((res_str + res_str_len), inp); + while ((p = strchr(res_str, '\n'))) { + *p = ' '; + } + } + return (res_str == NULL) ? inp : res_str; +} + +static char **make_list_in(char **inp, char *name) +{ + int len, i; + int name_len = strlen(name); + int n = 0; + char **list; + char *p1, *p2, *p3; + + /* create list of variable values */ + list = xmalloc(sizeof(*list)); + for (i = 0; inp[i]; i++) { + p3 = insert_var_value(inp[i]); + p1 = p3; + while (*p1) { + if ((*p1 == ' ')) { + p1++; + continue; + } + if ((p2 = strchr(p1, ' '))) { + len = p2 - p1; + } else { + len = strlen(p1); + p2 = p1 + len; + } + /* we use n + 2 in realloc for list,because we add + * new element and then we will add NULL element */ + list = xrealloc(list, sizeof(*list) * (n + 2)); + list[n] = xmalloc(2 + name_len + len); + strcpy(list[n], name); + strcat(list[n], "="); + strncat(list[n], p1, len); + list[n++][name_len + len + 1] = '\0'; + p1 = p2; + } + if (p3 != inp[i]) free(p3); + } + list[n] = NULL; + return list; +} + +/* Make new string for parser */ +static char * make_string(char ** inp) +{ + char *p; + char *str = NULL; + int n; + int len = 2; + + for (n = 0; inp[n]; n++) { + p = insert_var_value(inp[n]); + str = xrealloc(str, (len + strlen(p))); + if (n) { + strcat(str, " "); + } else { + *str = '\0'; + } + strcat(str, p); + len = strlen(str) + 3; + if (p != inp[n]) free(p); + } + len = strlen(str); + *(str + len) = '\n'; + *(str + len + 1) = '\0'; + return str; +} + +#endif /* CFG_HUSH_PARSER */ +/****************************************************************************/ diff --git a/common/kgdb.c b/common/kgdb.c new file mode 100644 index 0000000..6de6ec9 --- /dev/null +++ b/common/kgdb.c @@ -0,0 +1,594 @@ +/* taken from arch/ppc/kernel/ppc-stub.c */ + +/**************************************************************************** + + THIS SOFTWARE IS NOT COPYRIGHTED + + HP offers the following for use in the public domain. HP makes no + warranty with regard to the software or its performance and the + user accepts the software "AS IS" with all faults. + + HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD + TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES + OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + +****************************************************************************/ + +/**************************************************************************** + * Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $ + * + * Module name: remcom.c $ + * Revision: 1.34 $ + * Date: 91/03/09 12:29:49 $ + * Contributor: Lake Stevens Instrument Division$ + * + * Description: low level support for gdb debugger. $ + * + * Considerations: only works on target hardware $ + * + * Written by: Glenn Engel $ + * ModuleState: Experimental $ + * + * NOTES: See Below $ + * + * Modified for SPARC by Stu Grossman, Cygnus Support. + * + * This code has been extensively tested on the Fujitsu SPARClite demo board. + * + * To enable debugger support, two things need to happen. One, a + * call to set_debug_traps() is necessary in order to allow any breakpoints + * or error conditions to be properly intercepted and reported to gdb. + * Two, a breakpoint needs to be generated to begin communication. This + * is most easily accomplished by a call to breakpoint(). Breakpoint() + * simulates a breakpoint by executing a trap #1. + * + ************* + * + * The following gdb commands are supported: + * + * command function Return value + * + * g return the value of the CPU registers hex data or ENN + * G set the value of the CPU registers OK or ENN + * qOffsets Get section offsets. Reply is Text=xxx;Data=yyy;Bss=zzz + * + * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN + * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN + * + * c Resume at current address SNN ( signal NN) + * cAA..AA Continue at address AA..AA SNN + * + * s Step one instruction SNN + * sAA..AA Step one instruction from AA..AA SNN + * + * k kill + * + * ? What was the last sigval ? SNN (signal NN) + * + * bBB..BB Set baud rate to BB..BB OK or BNN, then sets + * baud rate + * + * All commands and responses are sent with a packet which includes a + * checksum. A packet consists of + * + * $#. + * + * where + * :: + * :: > + * + * When a packet is received, it is first acknowledged with either '+' or '-'. + * '+' indicates a successful transfer. '-' indicates a failed transfer. + * + * Example: + * + * Host: Reply: + * $m0,10#2a +$00010203040506070809101112131415#42 + * + ****************************************************************************/ + +#include + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + +#undef KGDB_DEBUG + +/* + * BUFMAX defines the maximum number of characters in inbound/outbound buffers + */ +#define BUFMAX 1024 +static char remcomInBuffer[BUFMAX]; +static char remcomOutBuffer[BUFMAX]; +static char remcomRegBuffer[BUFMAX]; + +static int initialized = 0; +static int kgdb_active = 0, first_entry = 1; +static struct pt_regs entry_regs; +static u_int error_jmp_buf[BUFMAX/2]; +static int longjmp_on_fault = 0; +#ifdef KGDB_DEBUG +static int kdebug = 1; +#endif + +static const char hexchars[]="0123456789abcdef"; + +/* Convert ch from a hex digit to an int */ +static int +hex(unsigned char ch) +{ + if (ch >= 'a' && ch <= 'f') + return ch-'a'+10; + if (ch >= '0' && ch <= '9') + return ch-'0'; + if (ch >= 'A' && ch <= 'F') + return ch-'A'+10; + return -1; +} + +/* Convert the memory pointed to by mem into hex, placing result in buf. + * Return a pointer to the last char put in buf (null). + */ +static unsigned char * +mem2hex(char *mem, char *buf, int count) +{ + unsigned char ch; + + longjmp_on_fault = 1; + while (count-- > 0) { + ch = *mem++; + *buf++ = hexchars[ch >> 4]; + *buf++ = hexchars[ch & 0xf]; + } + *buf = 0; + longjmp_on_fault = 0; + return (unsigned char *)buf; +} + +/* convert the hex array pointed to by buf into binary to be placed in mem + * return a pointer to the character AFTER the last byte fetched from buf. +*/ +static char * +hex2mem(char *buf, char *mem, int count) +{ + int i, hexValue; + unsigned char ch; + char *mem_start = mem; + + longjmp_on_fault = 1; + for (i=0; i# */ +static void +getpacket(char *buffer) +{ + unsigned char checksum; + unsigned char xmitcsum; + int i; + int count; + unsigned char ch; + + do { + /* wait around for the start character, ignore all other + * characters */ + while ((ch = (getDebugChar() & 0x7f)) != '$') { +#ifdef KGDB_DEBUG + if (kdebug) + putc(ch); +#endif + ; + } + + checksum = 0; + xmitcsum = -1; + + count = 0; + + /* now, read until a # or end of buffer is found */ + while (count < BUFMAX) { + ch = getDebugChar() & 0x7f; + if (ch == '#') + break; + checksum = checksum + ch; + buffer[count] = ch; + count = count + 1; + } + + if (count >= BUFMAX) + continue; + + buffer[count] = 0; + + if (ch == '#') { + xmitcsum = hex(getDebugChar() & 0x7f) << 4; + xmitcsum |= hex(getDebugChar() & 0x7f); + if (checksum != xmitcsum) + putDebugChar('-'); /* failed checksum */ + else { + putDebugChar('+'); /* successful transfer */ + /* if a sequence char is present, reply the ID */ + if (buffer[2] == ':') { + putDebugChar(buffer[0]); + putDebugChar(buffer[1]); + /* remove sequence chars from buffer */ + count = strlen(buffer); + for (i=3; i <= count; i++) + buffer[i-3] = buffer[i]; + } + } + } + } while (checksum != xmitcsum); +} + +/* send the packet in buffer. */ +static void +putpacket(unsigned char *buffer) +{ + unsigned char checksum; + int count; + unsigned char ch, recv; + + /* $#. */ + do { + putDebugChar('$'); + checksum = 0; + count = 0; + + while ((ch = buffer[count])) { + putDebugChar(ch); + checksum += ch; + count += 1; + } + + putDebugChar('#'); + putDebugChar(hexchars[checksum >> 4]); + putDebugChar(hexchars[checksum & 0xf]); + recv = getDebugChar(); + } while ((recv & 0x7f) != '+'); +} + +/* + * This function does all command processing for interfacing to gdb. + */ +static int +handle_exception (struct pt_regs *regs) +{ + int addr; + int length; + char *ptr; + kgdb_data kd; + int i; + + if (!initialized) { + printf("kgdb: exception before kgdb is initialized! huh?\n"); + return (0); + } + + /* probably should check which exception occured as well */ + if (longjmp_on_fault) { + longjmp_on_fault = 0; + kgdb_longjmp((long*)error_jmp_buf, KGDBERR_MEMFAULT); + panic("kgdb longjump failed!\n"); + } + + if (kgdb_active) { + printf("kgdb: unexpected exception from within kgdb\n"); + return (0); + } + kgdb_active = 1; + + kgdb_interruptible(0); + + printf("kgdb: handle_exception; trap [0x%x]\n", kgdb_trap(regs)); + + if (kgdb_setjmp((long*)error_jmp_buf) != 0) + panic("kgdb: error or fault in entry init!\n"); + + kgdb_enter(regs, &kd); + + if (first_entry) { + /* + * the first time we enter kgdb, we save the processor + * state so that we can return to the monitor if the + * remote end quits gdb (or at least, tells us to quit + * with the 'k' packet) + */ + entry_regs = *regs; + first_entry = 0; + } + + ptr = remcomOutBuffer; + + *ptr++ = 'T'; + + *ptr++ = hexchars[kd.sigval >> 4]; + *ptr++ = hexchars[kd.sigval & 0xf]; + + for (i = 0; i < kd.nregs; i++) { + kgdb_reg *rp = &kd.regs[i]; + + *ptr++ = hexchars[rp->num >> 4]; + *ptr++ = hexchars[rp->num & 0xf]; + *ptr++ = ':'; + ptr = (char *)mem2hex((char *)&rp->val, ptr, 4); + *ptr++ = ';'; + } + + *ptr = 0; + +#ifdef KGDB_DEBUG + if (kdebug) + printf("kgdb: remcomOutBuffer: %s\n", remcomOutBuffer); +#endif + + putpacket((unsigned char *)&remcomOutBuffer); + + while (1) { + volatile int errnum; + + remcomOutBuffer[0] = 0; + + getpacket(remcomInBuffer); + ptr = &remcomInBuffer[1]; + +#ifdef KGDB_DEBUG + if (kdebug) + printf("kgdb: remcomInBuffer: %s\n", remcomInBuffer); +#endif + + errnum = kgdb_setjmp((long*)error_jmp_buf); + + if (errnum == 0) switch (remcomInBuffer[0]) { + + case '?': /* report most recent signal */ + remcomOutBuffer[0] = 'S'; + remcomOutBuffer[1] = hexchars[kd.sigval >> 4]; + remcomOutBuffer[2] = hexchars[kd.sigval & 0xf]; + remcomOutBuffer[3] = 0; + break; + +#ifdef KGDB_DEBUG + case 'd': + /* toggle debug flag */ + kdebug ^= 1; + break; +#endif + + case 'g': /* return the value of the CPU registers. */ + length = kgdb_getregs(regs, remcomRegBuffer, BUFMAX); + mem2hex(remcomRegBuffer, remcomOutBuffer, length); + break; + + case 'G': /* set the value of the CPU registers */ + length = strlen(ptr); + if ((length & 1) != 0) kgdb_error(KGDBERR_BADPARAMS); + hex2mem(ptr, remcomRegBuffer, length/2); + kgdb_putregs(regs, remcomRegBuffer, length/2); + strcpy(remcomOutBuffer,"OK"); + break; + + case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */ + /* Try to read %x,%x. */ + + if (hexToInt(&ptr, &addr) + && *ptr++ == ',' + && hexToInt(&ptr, &length)) { + mem2hex((char *)addr, remcomOutBuffer, length); + } else { + kgdb_error(KGDBERR_BADPARAMS); + } + break; + + case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */ + /* Try to read '%x,%x:'. */ + + if (hexToInt(&ptr, &addr) + && *ptr++ == ',' + && hexToInt(&ptr, &length) + && *ptr++ == ':') { + hex2mem(ptr, (char *)addr, length); + strcpy(remcomOutBuffer, "OK"); + } else { + kgdb_error(KGDBERR_BADPARAMS); + } + break; + + + case 'k': /* kill the program, actually return to monitor */ + kd.extype = KGDBEXIT_KILL; + *regs = entry_regs; + first_entry = 1; + goto doexit; + + case 'C': /* CSS continue with signal SS */ + *ptr = '\0'; /* ignore the signal number for now */ + /* fall through */ + + case 'c': /* cAA..AA Continue; address AA..AA optional */ + /* try to read optional parameter, pc unchanged if no parm */ + kd.extype = KGDBEXIT_CONTINUE; + + if (hexToInt(&ptr, &addr)) { + kd.exaddr = addr; + kd.extype |= KGDBEXIT_WITHADDR; + } + + goto doexit; + + case 'S': /* SSS single step with signal SS */ + *ptr = '\0'; /* ignore the signal number for now */ + /* fall through */ + + case 's': + kd.extype = KGDBEXIT_SINGLE; + + if (hexToInt(&ptr, &addr)) { + kd.exaddr = addr; + kd.extype |= KGDBEXIT_WITHADDR; + } + + doexit: +/* Need to flush the instruction cache here, as we may have deposited a + * breakpoint, and the icache probably has no way of knowing that a data ref to + * some location may have changed something that is in the instruction cache. + */ + kgdb_flush_cache_all(); + kgdb_exit(regs, &kd); + kgdb_active = 0; + kgdb_interruptible(1); + return (1); + + case 'r': /* Reset (if user process..exit ???)*/ + panic("kgdb reset."); + break; + + case 'P': /* Pr=v set reg r to value v (r and v are hex) */ + if (hexToInt(&ptr, &addr) + && *ptr++ == '=' + && ((length = strlen(ptr)) & 1) == 0) { + hex2mem(ptr, remcomRegBuffer, length/2); + kgdb_putreg(regs, addr, + remcomRegBuffer, length/2); + strcpy(remcomOutBuffer,"OK"); + } else { + kgdb_error(KGDBERR_BADPARAMS); + } + break; + } /* switch */ + + if (errnum != 0) + sprintf(remcomOutBuffer, "E%02d", errnum); + +#ifdef KGDB_DEBUG + if (kdebug) + printf("kgdb: remcomOutBuffer: %s\n", remcomOutBuffer); +#endif + + /* reply to the request */ + putpacket((unsigned char *)&remcomOutBuffer); + + } /* while(1) */ +} + +/* + * kgdb_init must be called *after* the + * monitor is relocated into ram + */ +void +kgdb_init(void) +{ + kgdb_serial_init(); + debugger_exception_handler = handle_exception; + initialized = 1; + + putDebugStr("kgdb ready\n"); + puts("ready\n"); +} + +void +kgdb_error(int errnum) +{ + longjmp_on_fault = 0; + kgdb_longjmp((long*)error_jmp_buf, errnum); + panic("kgdb_error: longjmp failed!\n"); +} + +/* Output string in GDB O-packet format if GDB has connected. If nothing + output, returns 0 (caller must then handle output). */ +int +kgdb_output_string (const char* s, unsigned int count) +{ + char buffer[512]; + + count = (count <= (sizeof(buffer) / 2 - 2)) + ? count : (sizeof(buffer) / 2 - 2); + + buffer[0] = 'O'; + mem2hex ((char *)s, &buffer[1], count); + putpacket((unsigned char *)&buffer); + + return 1; +} + +void +breakpoint(void) +{ + if (!initialized) { + printf("breakpoint() called b4 kgdb init\n"); + return; + } + + kgdb_breakpoint(0, 0); +} + +int +do_kgdb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("Entering KGDB mode via exception handler...\n\n"); + kgdb_breakpoint(argc - 1, argv + 1); + printf("\nReturned from KGDB mode\n"); + return 0; +} + +U_BOOT_CMD( + kgdb, CFG_MAXARGS, 1, do_kgdb, + "kgdb - enter gdb remote debug mode\n", + "[arg0 arg1 .. argN]\n" + " - executes a breakpoint so that kgdb mode is\n" + " entered via the exception handler. To return\n" + " to the monitor, the remote gdb debugger must\n" + " execute a \"continue\" or \"quit\" command.\n" + "\n" + " if a program is loaded by the remote gdb, any args\n" + " passed to the kgdb command are given to the loaded\n" + " program if it is executed (see the \"hello_world\"\n" + " example program in the U-Boot examples directory)." +); +#else + +int kgdb_not_configured = 1; + +#endif /* CFG_CMD_KGDB */ diff --git a/common/lcd.c b/common/lcd.c new file mode 100644 index 0000000..e64972f --- /dev/null +++ b/common/lcd.c @@ -0,0 +1,756 @@ +/* + * Common LCD routines for supported CPUs + * + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering -- wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************/ +/* ** HEADER FILES */ +/************************************************************************/ + +/* #define DEBUG */ + +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_POST) +#include +#endif +#include +#include + +#if defined(CONFIG_PXA250) +#include +#endif + +#if defined(CONFIG_MPC823) +#include +#endif + + +#ifdef CONFIG_LCD + +/************************************************************************/ +/* ** FONT DATA */ +/************************************************************************/ +#include /* Get font data, width and height */ + +/************************************************************************/ +/* ** LOGO DATA */ +/************************************************************************/ +#ifdef CONFIG_LCD_LOGO +# include /* Get logo data, width and height */ +# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) +# error Default Color Map overlaps with Logo Color Map +# endif +#endif + +ulong lcd_setmem (ulong addr); + +static void lcd_drawchars (ushort x, ushort y, uchar *str, int count); +static inline void lcd_puts_xy (ushort x, ushort y, uchar *s); +static inline void lcd_putc_xy (ushort x, ushort y, uchar c); + +static int lcd_init (void *lcdbase); + +static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); +extern void lcd_ctrl_init (void *lcdbase); +extern void lcd_enable (void); +static void *lcd_logo (void); + + +#if LCD_BPP == LCD_COLOR8 +extern void lcd_setcolreg (ushort regno, + ushort red, ushort green, ushort blue); +#endif +#if LCD_BPP == LCD_MONOCHROME +extern void lcd_initcolregs (void); +#endif + +static int lcd_getbgcolor (void); +static void lcd_setfgcolor (int color); +static void lcd_setbgcolor (int color); + +char lcd_is_enabled = 0; +extern vidinfo_t panel_info; + +#ifdef NOT_USED_SO_FAR +static void lcd_getcolreg (ushort regno, + ushort *red, ushort *green, ushort *blue); +static int lcd_getfgcolor (void); +#endif /* NOT_USED_SO_FAR */ + +/************************************************************************/ + +/*----------------------------------------------------------------------*/ + +static void console_scrollup (void) +{ +#if 1 + /* Copy up rows ignoring the first one */ + memcpy (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE); + + /* Clear the last one */ + memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE); +#else + /* + * Poor attempt to optimize speed by moving "long"s. + * But the code is ugly, and not a bit faster :-( + */ + ulong *t = (ulong *)CONSOLE_ROW_FIRST; + ulong *s = (ulong *)CONSOLE_ROW_SECOND; + ulong l = CONSOLE_SCROLL_SIZE / sizeof(ulong); + uchar c = lcd_color_bg & 0xFF; + ulong val= (c<<24) | (c<<16) | (c<<8) | c; + + while (l--) + *t++ = *s++; + + t = (ulong *)CONSOLE_ROW_LAST; + l = CONSOLE_ROW_SIZE / sizeof(ulong); + + while (l-- > 0) + *t++ = val; +#endif +} + +/*----------------------------------------------------------------------*/ + +static inline void console_back (void) +{ + if (--console_col < 0) { + console_col = CONSOLE_COLS-1 ; + if (--console_row < 0) { + console_row = 0; + } + } + + lcd_putc_xy (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + ' '); +} + +/*----------------------------------------------------------------------*/ + +static inline void console_newline (void) +{ + ++console_row; + console_col = 0; + + /* Check if we need to scroll the terminal */ + if (console_row >= CONSOLE_ROWS) { + /* Scroll everything up */ + console_scrollup () ; + --console_row; + } +} + +/*----------------------------------------------------------------------*/ + +void lcd_putc (const char c) +{ + if (!lcd_is_enabled) { + serial_putc(c); + return; + } + + switch (c) { + case '\r': console_col = 0; + return; + + case '\n': console_newline(); + return; + + case '\t': /* Tab (8 chars alignment) */ + console_col |= 8; + console_col &= ~7; + + if (console_col >= CONSOLE_COLS) { + console_newline(); + } + return; + + case '\b': console_back(); + return; + + default: lcd_putc_xy (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + c); + if (++console_col >= CONSOLE_COLS) { + console_newline(); + } + return; + } + /* NOTREACHED */ +} + +/*----------------------------------------------------------------------*/ + +void lcd_puts (const char *s) +{ + if (!lcd_is_enabled) { + serial_puts (s); + return; + } + + while (*s) { + lcd_putc (*s++); + } +} + +/************************************************************************/ +/* ** Low-Level Graphics Routines */ +/************************************************************************/ + +static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) +{ + uchar *dest; + ushort off, row; + + dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8); + off = x * (1 << LCD_BPP) % 8; + + for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { + uchar *s = str; + uchar *d = dest; + int i; + +#if LCD_BPP == LCD_MONOCHROME + uchar rest = *d & -(1 << (8-off)); + uchar sym; +#endif + for (i=0; i> off); + rest = sym << (8-off); +#elif LCD_BPP == LCD_COLOR8 + for (c=0; c<8; ++c) { + *d++ = (bits & 0x80) ? + lcd_color_fg : lcd_color_bg; + bits <<= 1; + } +#elif LCD_BPP == LCD_COLOR16 + for (c=0; c<16; ++c) { + *d++ = (bits & 0x80) ? + lcd_color_fg : lcd_color_bg; + bits <<= 1; + } +#endif + } +#if LCD_BPP == LCD_MONOCHROME + *d = rest | (*d & ((1 << (8-off)) - 1)); +#endif + } +} + +/*----------------------------------------------------------------------*/ + +static inline void lcd_puts_xy (ushort x, ushort y, uchar *s) +{ +#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) + lcd_drawchars (x, y+BMP_LOGO_HEIGHT, s, strlen ((char *)s)); +#else + lcd_drawchars (x, y, s, strlen ((char *)s)); +#endif +} + +/*----------------------------------------------------------------------*/ + +static inline void lcd_putc_xy (ushort x, ushort y, uchar c) +{ +#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) + lcd_drawchars (x, y+BMP_LOGO_HEIGHT, &c, 1); +#else + lcd_drawchars (x, y, &c, 1); +#endif +} + +/************************************************************************/ +/** Small utility to check that you got the colours right */ +/************************************************************************/ +#ifdef LCD_TEST_PATTERN + +#define N_BLK_VERT 2 +#define N_BLK_HOR 3 + +static int test_colors[N_BLK_HOR*N_BLK_VERT] = { + CONSOLE_COLOR_RED, CONSOLE_COLOR_GREEN, CONSOLE_COLOR_YELLOW, + CONSOLE_COLOR_BLUE, CONSOLE_COLOR_MAGENTA, CONSOLE_COLOR_CYAN, +}; + +static void test_pattern (void) +{ + ushort v_max = panel_info.vl_row; + ushort h_max = panel_info.vl_col; + ushort v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT; + ushort h_step = (h_max + N_BLK_HOR - 1) / N_BLK_HOR; + ushort v, h; + uchar *pix = (uchar *)lcd_base; + + printf ("[LCD] Test Pattern: %d x %d [%d x %d]\n", + h_max, v_max, h_step, v_step); + + /* WARNING: Code silently assumes 8bit/pixel */ + for (v=0; vfb_base); + + lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + + lcd_init (lcd_base); /* LCD initialization */ + + /* Device initialization */ + memset (&lcddev, 0, sizeof (lcddev)); + + strcpy (lcddev.name, "lcd"); + lcddev.ext = 0; /* No extensions */ + lcddev.flags = DEV_FLAGS_OUTPUT; /* Output only */ + lcddev.putc = lcd_putc; /* 'putc' function */ + lcddev.puts = lcd_puts; /* 'puts' function */ + + rc = device_register (&lcddev); + + return (rc == 0) ? 1 : rc; +} + +/*----------------------------------------------------------------------*/ +static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ +#if LCD_BPP == LCD_MONOCHROME + /* Setting the palette */ + lcd_initcolregs(); + +#elif LCD_BPP == LCD_COLOR8 + /* Setting the palette */ + lcd_setcolreg (CONSOLE_COLOR_BLACK, 0, 0, 0); + lcd_setcolreg (CONSOLE_COLOR_RED, 0xFF, 0, 0); + lcd_setcolreg (CONSOLE_COLOR_GREEN, 0, 0xFF, 0); + lcd_setcolreg (CONSOLE_COLOR_YELLOW, 0xFF, 0xFF, 0); + lcd_setcolreg (CONSOLE_COLOR_BLUE, 0, 0, 0xFF); + lcd_setcolreg (CONSOLE_COLOR_MAGENTA, 0xFF, 0, 0xFF); + lcd_setcolreg (CONSOLE_COLOR_CYAN, 0, 0xFF, 0xFF); + lcd_setcolreg (CONSOLE_COLOR_GREY, 0xAA, 0xAA, 0xAA); + lcd_setcolreg (CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF); +#endif + +#ifndef CFG_WHITE_ON_BLACK + lcd_setfgcolor (CONSOLE_COLOR_BLACK); + lcd_setbgcolor (CONSOLE_COLOR_WHITE); +#else + lcd_setfgcolor (CONSOLE_COLOR_WHITE); + lcd_setbgcolor (CONSOLE_COLOR_BLACK); +#endif /* CFG_WHITE_ON_BLACK */ + +#ifdef LCD_TEST_PATTERN + test_pattern(); +#else + /* set framebuffer to background color */ + memset ((char *)lcd_base, + COLOR_MASK(lcd_getbgcolor()), + lcd_line_length*panel_info.vl_row); +#endif + /* Paint the logo and retrieve LCD base address */ + debug ("[LCD] Drawing the logo...\n"); + lcd_console_address = lcd_logo (); + + console_col = 0; + console_row = 0; + + return (0); +} + +U_BOOT_CMD( + cls, 1, 1, lcd_clear, + "cls - clear screen\n", + NULL +); + +/*----------------------------------------------------------------------*/ + +static int lcd_init (void *lcdbase) +{ + /* Initialize the lcd controller */ + debug ("[LCD] Initializing LCD frambuffer at %p\n", lcdbase); + + lcd_ctrl_init (lcdbase); + lcd_clear (NULL, 1, 1, NULL); /* dummy args */ + lcd_enable (); + + /* Initialize the console */ + console_col = 0; +#ifdef CONFIG_LCD_INFO_BELOW_LOGO + console_row = 7 + BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT; +#else + console_row = 1; /* leave 1 blank line below logo */ +#endif + lcd_is_enabled = 1; + + return 0; +} + + +/************************************************************************/ +/* ** ROM capable initialization part - needed to reserve FB memory */ +/************************************************************************/ +/* + * This is called early in the system initialization to grab memory + * for the LCD controller. + * Returns new address for monitor, after reserving LCD buffer memory + * + * Note that this is running from ROM, so no write access to global data. + */ +ulong lcd_setmem (ulong addr) +{ + ulong size; + int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + + debug ("LCD panel info: %d x %d, %d bit/pix\n", + panel_info.vl_col, panel_info.vl_row, NBITS (panel_info.vl_bpix) ); + + size = line_length * panel_info.vl_row; + + /* Round up to nearest full page */ + size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); + + /* Allocate pages for the frame buffer. */ + addr -= size; + + debug ("Reserving %ldk for LCD Framebuffer at: %08lx\n", size>>10, addr); + + return (addr); +} + +/*----------------------------------------------------------------------*/ + +static void lcd_setfgcolor (int color) +{ + lcd_color_fg = color & 0x0F; +} + +/*----------------------------------------------------------------------*/ + +static void lcd_setbgcolor (int color) +{ + lcd_color_bg = color & 0x0F; +} + +/*----------------------------------------------------------------------*/ + +#ifdef NOT_USED_SO_FAR +static int lcd_getfgcolor (void) +{ + return lcd_color_fg; +} +#endif /* NOT_USED_SO_FAR */ + +/*----------------------------------------------------------------------*/ + +static int lcd_getbgcolor (void) +{ + return lcd_color_bg; +} + +/*----------------------------------------------------------------------*/ + +/************************************************************************/ +/* ** Chipset depending Bitmap / Logo stuff... */ +/************************************************************************/ +#ifdef CONFIG_LCD_LOGO +void bitmap_plot (int x, int y) +{ + ushort *cmap; + ushort i, j; + uchar *bmap; + uchar *fb; + ushort *fb16; +#if defined(CONFIG_PXA250) + struct pxafb_info *fbi = &panel_info.pxa; +#elif defined(CONFIG_MPC823) + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = &(immr->im_cpm); +#endif + + debug ("Logo: width %d height %d colors %d cmap %d\n", + BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS, + sizeof(bmp_logo_palette)/(sizeof(ushort))); + + bmap = &bmp_logo_bitmap[0]; + fb = (uchar *)(lcd_base + y * lcd_line_length + x); + + if (NBITS(panel_info.vl_bpix) < 12) { + /* Leave room for default color map */ +#if defined(CONFIG_PXA250) + cmap = (ushort *)fbi->palette; +#elif defined(CONFIG_MPC823) + cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); +#endif + + WATCHDOG_RESET(); + + /* Set color map */ + for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) { + ushort colreg = bmp_logo_palette[i]; +#ifdef CFG_INVERT_COLORS + *cmap++ = 0xffff - colreg; +#else + *cmap++ = colreg; +#endif + } + + WATCHDOG_RESET(); + + for (i=0; iim_cpm); +#endif + + if (!((bmp->header.signature[0]=='B') && + (bmp->header.signature[1]=='M'))) { + printf ("Error: no valid bmp image at %lx\n", bmp_image); + return 1; +} + + width = le32_to_cpu (bmp->header.width); + height = le32_to_cpu (bmp->header.height); + colors = 1<header.bit_count); + compression = le32_to_cpu (bmp->header.compression); + + bpix = NBITS(panel_info.vl_bpix); + + if ((bpix != 1) && (bpix != 8)) { + printf ("Error: %d bit/pixel mode not supported by U-Boot\n", + bpix); + return 1; + } + + if (bpix != le16_to_cpu(bmp->header.bit_count)) { + printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", + bpix, + le16_to_cpu(bmp->header.bit_count)); + return 1; + } + + debug ("Display-bmp: %d x %d with %d colors\n", + (int)width, (int)height, (int)colors); + + if (bpix==8) { +#if defined(CONFIG_PXA250) + cmap = (ushort *)fbi->palette; +#elif defined(CONFIG_MPC823) + cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); +#else +# error "Don't know location of color map" +#endif + + /* Set color map */ + for (i=0; icolor_table[i]; + ushort colreg = + ( ((cte.red) << 8) & 0xf800) | + ( ((cte.green) << 3) & 0x07e0) | + ( ((cte.blue) >> 3) & 0x001f) ; +#ifdef CFG_INVERT_COLORS + *cmap = 0xffff - colreg; +#else + *cmap = colreg; +#endif +#if defined(CONFIG_PXA250) + cmap++; +#elif defined(CONFIG_MPC823) + cmap--; +#endif + } + } + + padded_line = (width&0x3) ? ((width&~0x3)+4) : (width); + if ((x + width)>panel_info.vl_col) + width = panel_info.vl_col - x; + if ((y + height)>panel_info.vl_row) + height = panel_info.vl_row - y; + + bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); + fb = (uchar *) (lcd_base + + (y + height - 1) * lcd_line_length + x); + for (i = 0; i < height; ++i) { + WATCHDOG_RESET(); + for (j = 0; j < width ; j++) +#if defined(CONFIG_PXA250) + *(fb++)=*(bmap++); +#elif defined(CONFIG_MPC823) + *(fb++)=255-*(bmap++); +#endif + bmap += (width - padded_line); + fb -= (width + lcd_line_length); + } + + return (0); +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ + + +static void *lcd_logo (void) +{ +#ifdef CONFIG_LCD_INFO + DECLARE_GLOBAL_DATA_PTR; + + char info[80]; + char temp[32]; +#endif /* CONFIG_LCD_INFO */ + +#ifdef CONFIG_SPLASH_SCREEN + char *s; + ulong addr; + static int do_splash = 1; + + if (do_splash && (s = getenv("splashimage")) != NULL) { + addr = simple_strtoul(s, NULL, 16); + do_splash = 0; + + if (lcd_display_bitmap (addr, 0, 0) == 0) { + return ((void *)lcd_base); + } + } +#endif /* CONFIG_SPLASH_SCREEN */ + +#ifdef CONFIG_LCD_LOGO + bitmap_plot (0, 0); +#endif /* CONFIG_LCD_LOGO */ + +#ifdef CONFIG_MPC823 +# ifdef CONFIG_LCD_INFO + sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info)); + + sprintf (info, "(C) 2004 DENX Software Engineering"); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT, + (uchar *)info, strlen(info)); + + sprintf (info, " Wolfgang DENK, wd@denx.de"); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2, + (uchar *)info, strlen(info)); +# ifdef CONFIG_LCD_INFO_BELOW_LOGO + sprintf (info, "MPC823 CPU at %s MHz", + strmhz(temp, gd->cpu_clk)); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3, + info, strlen(info)); + sprintf (info, " %ld MB RAM, %ld MB Flash", + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4, + info, strlen(info)); +# else + /* leave one blank line */ + + sprintf (info, "MPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash", + strmhz(temp, gd->cpu_clk), + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4, + (uchar *)info, strlen(info)); + +# endif /* CONFIG_LCD_INFO_BELOW_LOGO */ +# endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_MPC823 */ + +#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) + return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length)); +#else + return ((void *)lcd_base); +#endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */ +} + +/************************************************************************/ +/************************************************************************/ + +#endif /* CONFIG_LCD */ diff --git a/common/lists.c b/common/lists.c new file mode 100644 index 0000000..3f117b5 --- /dev/null +++ b/common/lists.c @@ -0,0 +1,734 @@ +#include +#include +#include + +#define MAX(a,b) (((a)>(b)) ? (a) : (b)) +#define MIN(a,b) (((a)<(b)) ? (a) : (b)) +#define CAT4CHARS(a,b,c,d) ((a<<24) | (b<<16) | (c<<8) | d) + +/* increase list size by 10% every time it is full */ +#define kDefaultAllocationPercentIncrease 10 + +/* always increase list size by 4 items when it is full */ +#define kDefaultAllocationminNumItemsIncrease 4 + +/* + * how many items to expand the list by when it becomes full + * = current listSize (in items) + (hiword percent of list size) + loword + */ +#define NUMITEMSPERALLOC(list) MAX(((*list)->listSize * \ + ((*list)->percentIncrease + 100)) / 100, \ + (*list)->minNumItemsIncrease ) + +#define ITEMPTR(list,item) &(((char *)&(*list)->itemList)[(*(list))->itemSize * (item)]) + +#define LIST_SIGNATURE CAT4CHARS('L', 'I', 'S', 'T'); + +#define calloc(size,num) malloc(size*num) + +/********************************************************************/ + +Handle NewHandle (unsigned int numBytes) +{ + void *memPtr; + HandleRecord *hanPtr; + + memPtr = calloc (numBytes, 1); + hanPtr = (HandleRecord *) calloc (sizeof (HandleRecord), 1); + if (hanPtr && (memPtr || numBytes == 0)) { + hanPtr->ptr = memPtr; + hanPtr->size = numBytes; + return (Handle) hanPtr; + } else { + free (memPtr); + free (hanPtr); + return NULL; + } +} +/********************************************************************/ + +void DisposeHandle (Handle handle) +{ + if (handle) { + free (*handle); + free ((void *) handle); + } +} +/********************************************************************/ + +unsigned int GetHandleSize (Handle handle) +{ + return ((HandleRecord *) handle)->size; +} +/********************************************************************/ + +int SetHandleSize (Handle handle, unsigned int newSize) +{ + HandleRecord *hanRecPtr = (HandleRecord *) handle; + void *newPtr, *oldPtr; + unsigned int oldSize; + + + oldPtr = hanRecPtr->ptr; + oldSize = hanRecPtr->size; + + if (oldSize == newSize) + return 1; + + if (oldPtr == NULL) { + newPtr = malloc (newSize); + } else { + newPtr = realloc (oldPtr, newSize); + } + if (newPtr || (newSize == 0)) { + hanRecPtr->ptr = newPtr; + hanRecPtr->size = newSize; + if (newSize > oldSize) + memset ((char *) newPtr + oldSize, 0, newSize - oldSize); + return 1; + } else + return 0; +} + +#ifdef CFG_ALL_LIST_FUNCTIONS + +/* Used to compare list elements by their raw data contents */ +static int ListMemBlockCmp (void *a, void *b, int size) +{ + return memcmp (a, b, size); +} + +/***************************************************************************/ + +/* + * Binary search numElements of size elementSize in array for a match + * to the. item. Return the index of the element that matches + * (0 - numElements - 1). If no match is found return the -i-1 where + * i is the index (0 - numElements) where the item should be placed. + * (*theCmp)(a,b) should return <0 if a0 if a>b. + * + * This function is like the C-Library function bsearch() except that + * this function returns the index where the item should be placed if + * it is not found. + */ +int BinSearch ( void *array, int numElements, int elementSize, + void *itemPtr, CompareFunction compareFunction) +{ + int low, high, mid, cmp; + void *arrayItemPtr; + + for (low = 0, high = numElements - 1, mid = 0, cmp = -1; low <= high;) { + mid = (low + high) >> 1; + + arrayItemPtr = (void *) (((char *) array) + (mid * elementSize)); + cmp = compareFunction + ? compareFunction (itemPtr, arrayItemPtr) + : ListMemBlockCmp (itemPtr, arrayItemPtr, elementSize); + if (cmp == 0) { + return mid; + } else if (cmp < 0) { + high = mid - 1; + } else { + low = mid + 1; + } + } + if (cmp > 0) + mid++; + + return -mid - 1; +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/*******************************************************************************/ + +/* + * If numNewItems == 0 then expand the list by the number of items + * indicated by its allocation policy. + * If numNewItems > 0 then expand the list by exactly the number of + * items indicated. + * If numNewItems < 0 then expand the list by the absolute value of + * numNewItems plus the number of items indicated by its allocation + * policy. + * Returns 1 for success, 0 if out of memory +*/ +static int ExpandListSpace (list_t list, int numNewItems) +{ + if (numNewItems == 0) { + numNewItems = NUMITEMSPERALLOC (list); + } else if (numNewItems < 0) { + numNewItems = (-numNewItems) + NUMITEMSPERALLOC (list); + } + + if (SetHandleSize ((Handle) list, + sizeof (ListStruct) + + ((*list)->listSize + + numNewItems) * (*list)->itemSize)) { + (*list)->listSize += numNewItems; + return 1; + } else { + return 0; + } +} + +/*******************************/ + +#ifdef CFG_ALL_LIST_FUNCTIONS + +/* + * This function reallocate the list, minus any currently unused + * portion of its allotted memory. + */ +void ListCompact (list_t list) +{ + + if (!SetHandleSize ((Handle) list, + sizeof (ListStruct) + + (*list)->numItems * (*list)->itemSize)) { + return; + } + + (*list)->listSize = (*list)->numItems; +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/*******************************/ + +list_t ListCreate (int elementSize) +{ + list_t list; + + list = (list_t) (NewHandle (sizeof (ListStruct))); /* create empty list */ + if (list) { + (*list)->signature = LIST_SIGNATURE; + (*list)->numItems = 0; + (*list)->listSize = 0; + (*list)->itemSize = elementSize; + (*list)->percentIncrease = kDefaultAllocationPercentIncrease; + (*list)->minNumItemsIncrease = + kDefaultAllocationminNumItemsIncrease; + } + + return list; +} + +/*******************************/ + +void ListSetAllocationPolicy (list_t list, int minItemsPerAlloc, + int percentIncreasePerAlloc) +{ + (*list)->percentIncrease = percentIncreasePerAlloc; + (*list)->minNumItemsIncrease = minItemsPerAlloc; +} + +/*******************************/ + +void ListDispose (list_t list) +{ + DisposeHandle ((Handle) list); +} +/*******************************/ + +#ifdef CFG_ALL_LIST_FUNCTIONS + +void ListDisposePtrList (list_t list) +{ + int index; + int numItems; + + if (list) { + numItems = ListNumItems (list); + + for (index = 1; index <= numItems; index++) + free (*(void **) ListGetPtrToItem (list, index)); + + ListDispose (list); + } +} + +/*******************************/ + +/* + * keeps memory, resets the number of items to 0 + */ +void ListClear (list_t list) +{ + if (!list) + return; + (*list)->numItems = 0; +} + +/*******************************/ + +/* + * copy is only as large as necessary + */ +list_t ListCopy (list_t originalList) +{ + list_t tempList = NULL; + int numItems; + + if (!originalList) + return NULL; + + tempList = ListCreate ((*originalList)->itemSize); + if (tempList) { + numItems = ListNumItems (originalList); + + if (!SetHandleSize ((Handle) tempList, + sizeof (ListStruct) + + numItems * (*tempList)->itemSize)) { + ListDispose (tempList); + return NULL; + } + + (*tempList)->numItems = (*originalList)->numItems; + (*tempList)->listSize = (*originalList)->numItems; + (*tempList)->itemSize = (*originalList)->itemSize; + (*tempList)->percentIncrease = (*originalList)->percentIncrease; + (*tempList)->minNumItemsIncrease = + (*originalList)->minNumItemsIncrease; + + memcpy (ITEMPTR (tempList, 0), ITEMPTR (originalList, 0), + numItems * (*tempList)->itemSize); + } + + return tempList; +} + +/********************************/ + +/* + * list1 = list1 + list2 + */ +int ListAppend (list_t list1, list_t list2) +{ + int numItemsL1, numItemsL2; + + if (!list2) + return 1; + + if (!list1) + return 0; + if ((*list1)->itemSize != (*list2)->itemSize) + return 0; + + numItemsL1 = ListNumItems (list1); + numItemsL2 = ListNumItems (list2); + + if (numItemsL2 == 0) + return 1; + + if (!SetHandleSize ((Handle) list1, + sizeof (ListStruct) + (numItemsL1 + numItemsL2) * + (*list1)->itemSize)) { + return 0; + } + + (*list1)->numItems = numItemsL1 + numItemsL2; + (*list1)->listSize = numItemsL1 + numItemsL2; + + memmove (ITEMPTR (list1, numItemsL1), + ITEMPTR (list2, 0), + numItemsL2 * (*list2)->itemSize); + + return 1; +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/*******************************/ + +/* + * returns 1 if the item is inserted, returns 0 if out of memory or + * bad arguments were passed. + */ +int ListInsertItem (list_t list, void *ptrToItem, int itemPosition) +{ + return ListInsertItems (list, ptrToItem, itemPosition, 1); +} + +/*******************************/ + +int ListInsertItems (list_t list, void *ptrToItems, int firstItemPosition, + int numItemsToInsert) +{ + int numItems = (*list)->numItems; + + if (firstItemPosition == numItems + 1) + firstItemPosition = LIST_END; + else if (firstItemPosition > numItems) + return 0; + + if ((*list)->numItems >= (*list)->listSize) { + if (!ExpandListSpace (list, -numItemsToInsert)) + return 0; + } + + if (firstItemPosition == LIST_START) { + if (numItems == 0) { + /* special case for empty list */ + firstItemPosition = LIST_END; + } else { + firstItemPosition = 1; + } + } + + if (firstItemPosition == LIST_END) { /* add at the end of the list */ + if (ptrToItems) + memcpy (ITEMPTR (list, numItems), ptrToItems, + (*list)->itemSize * numItemsToInsert); + else + memset (ITEMPTR (list, numItems), 0, + (*list)->itemSize * numItemsToInsert); + + (*list)->numItems += numItemsToInsert; + } else { /* move part of list up to make room for new item */ + memmove (ITEMPTR (list, firstItemPosition - 1 + numItemsToInsert), + ITEMPTR (list, firstItemPosition - 1), + (numItems + 1 - firstItemPosition) * (*list)->itemSize); + + if (ptrToItems) + memmove (ITEMPTR (list, firstItemPosition - 1), ptrToItems, + (*list)->itemSize * numItemsToInsert); + else + memset (ITEMPTR (list, firstItemPosition - 1), 0, + (*list)->itemSize * numItemsToInsert); + + (*list)->numItems += numItemsToInsert; + } + + return 1; +} + +#ifdef CFG_ALL_LIST_FUNCTIONS + +/*******************************/ + +int ListEqual (list_t list1, list_t list2) +{ + if (list1 == list2) + return 1; + + if (list1 == NULL || list2 == NULL) + return 0; + + if ((*list1)->itemSize == (*list1)->itemSize) { + if ((*list1)->numItems == (*list2)->numItems) { + return (memcmp (ITEMPTR (list1, 0), ITEMPTR (list2, 0), + (*list1)->itemSize * (*list1)->numItems) == 0); + } + } + + return 0; +} + +/*******************************/ + +/* + * The item pointed to by ptrToItem is copied over the current item + * at itemPosition + */ +void ListReplaceItem (list_t list, void *ptrToItem, int itemPosition) +{ + ListReplaceItems (list, ptrToItem, itemPosition, 1); +} + +/*******************************/ + +/* + * The item pointed to by ptrToItems is copied over the current item + * at itemPosition + */ +void ListReplaceItems ( list_t list, void *ptrToItems, + int firstItemPosition, int numItemsToReplace) +{ + + if (firstItemPosition == LIST_END) + firstItemPosition = (*list)->numItems; + else if (firstItemPosition == LIST_START) + firstItemPosition = 1; + + memmove (ITEMPTR (list, firstItemPosition - 1), ptrToItems, + (*list)->itemSize * numItemsToReplace); +} + +/*******************************/ + +void ListGetItem (list_t list, void *itemDestination, int itemPosition) +{ + ListGetItems (list, itemDestination, itemPosition, 1); +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/*******************************/ + +#if defined(CFG_ALL_LIST_FUNCTIONS) || defined(CFG_DEVICE_DEREGISTER) + +void ListRemoveItem (list_t list, void *itemDestination, int itemPosition) +{ + ListRemoveItems (list, itemDestination, itemPosition, 1); +} + +/*******************************/ + +void ListRemoveItems (list_t list, void *itemsDestination, + int firstItemPosition, int numItemsToRemove) +{ + int firstItemAfterChunk, numToMove; + + if (firstItemPosition == LIST_START) + firstItemPosition = 1; + else if (firstItemPosition == LIST_END) + firstItemPosition = (*list)->numItems; + + if (itemsDestination != NULL) + memcpy (itemsDestination, ITEMPTR (list, firstItemPosition - 1), + (*list)->itemSize * numItemsToRemove); + + firstItemAfterChunk = firstItemPosition + numItemsToRemove; + numToMove = (*list)->numItems - (firstItemAfterChunk - 1); + + if (numToMove > 0) { + /* + * move part of list down to cover hole left by removed item + */ + memmove (ITEMPTR (list, firstItemPosition - 1), + ITEMPTR (list, firstItemAfterChunk - 1), + (*list)->itemSize * numToMove); + } + + (*list)->numItems -= numItemsToRemove; +} +#endif /* CFG_ALL_LIST_FUNCTIONS || CFG_DEVICE_DEREGISTER */ + +/*******************************/ + +void ListGetItems (list_t list, void *itemsDestination, + int firstItemPosition, int numItemsToGet) +{ + + if (firstItemPosition == LIST_START) + firstItemPosition = 1; + else if (firstItemPosition == LIST_END) + firstItemPosition = (*list)->numItems; + + memcpy (itemsDestination, + ITEMPTR (list, firstItemPosition - 1), + (*list)->itemSize * numItemsToGet); +} + +/*******************************/ + +/* + * Returns a pointer to the item at itemPosition. returns null if an + * errors occurred. + */ +void *ListGetPtrToItem (list_t list, int itemPosition) +{ + if (itemPosition == LIST_START) + itemPosition = 1; + else if (itemPosition == LIST_END) + itemPosition = (*list)->numItems; + + return ITEMPTR (list, itemPosition - 1); +} + +/*******************************/ + +/* + * returns a pointer the lists data (abstraction violation for + * optimization) + */ +void *ListGetDataPtr (list_t list) +{ + return &((*list)->itemList[0]); +} + +/********************************/ + +#ifdef CFG_ALL_LIST_FUNCTIONS + +int ListApplyToEach (list_t list, int ascending, + ListApplicationFunc funcToApply, + void *callbackData) +{ + int result = 0, index; + + if (!list || !funcToApply) + goto Error; + + if (ascending) { + for (index = 1; index <= ListNumItems (list); index++) { + result = funcToApply (index, + ListGetPtrToItem (list, index), + callbackData); + if (result < 0) + goto Error; + } + } else { + for (index = ListNumItems (list); + index > 0 && index <= ListNumItems (list); + index--) { + result = funcToApply (index, + ListGetPtrToItem (list, index), + callbackData); + if (result < 0) + goto Error; + } + } + +Error: + return result; +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/********************************/ + +int ListGetItemSize (list_t list) +{ + return (*list)->itemSize; +} + +/********************************/ + +int ListNumItems (list_t list) +{ + return (*list)->numItems; +} + +/*******************************/ + +#ifdef CFG_ALL_LIST_FUNCTIONS + +void ListRemoveDuplicates (list_t list, CompareFunction compareFunction) +{ + int numItems, index, startIndexForFind, duplicatesIndex; + + numItems = ListNumItems (list); + + for (index = 1; index < numItems; index++) { + startIndexForFind = index + 1; + while (startIndexForFind <= numItems) { + duplicatesIndex = + ListFindItem (list, + ListGetPtrToItem (list, index), + startIndexForFind, + compareFunction); + if (duplicatesIndex > 0) { + ListRemoveItem (list, NULL, duplicatesIndex); + numItems--; + startIndexForFind = duplicatesIndex; + } else { + break; + } + } + } +} + +/*******************************/ + + +/*******************************/ + +int ListFindItem (list_t list, void *ptrToItem, int startingPosition, + CompareFunction compareFunction) +{ + int numItems, size, index, cmp; + void *listItemPtr; + + if ((numItems = (*list)->numItems) == 0) + return 0; + + size = (*list)->itemSize; + + if (startingPosition == LIST_START) + startingPosition = 1; + else if (startingPosition == LIST_END) + startingPosition = numItems; + + for (index = startingPosition; index <= numItems; index++) { + listItemPtr = ITEMPTR (list, index - 1); + cmp = compareFunction + ? compareFunction (ptrToItem, listItemPtr) + : ListMemBlockCmp (ptrToItem, listItemPtr, size); + if (cmp == 0) + return index; + } + + return 0; +} + +/*******************************/ + +int ShortCompare (void *a, void *b) +{ + if (*(short *) a < *(short *) b) + return -1; + if (*(short *) a > *(short *) b) + return 1; + return 0; +} + +/*******************************/ + +int IntCompare (void *a, void *b) +{ + if (*(int *) a < *(int *) b) + return -1; + if (*(int *) a > *(int *) b) + return 1; + return 0; +} + +/*******************************/ + +int CStringCompare (void *a, void *b) +{ + return strcmp (*(char **) a, *(char **) b); +} + +/*******************************/ + + +int ListBinSearch (list_t list, void *ptrToItem, + CompareFunction compareFunction) +{ + int index; + + index = BinSearch (ITEMPTR (list, 0), + (int) (*list)->numItems, + (int) (*list)->itemSize, ptrToItem, + compareFunction); + + if (index >= 0) + index++; /* lists start from 1 */ + else + index = 0; /* item not found */ + + return index; +} + +/**************************************************************************/ + +/* + * Reserves memory for numItems in the list. If it succeeds then + * numItems items can be inserted without possibility of an out of + * memory error (useful to simplify error recovery in complex + * functions). Returns 1 if success, 0 if out of memory. + */ +int ListPreAllocate (list_t list, int numItems) +{ + if ((*list)->listSize - (*list)->numItems < numItems) { + return ExpandListSpace (list, + numItems - ((*list)->listSize - + (*list)->numItems)); + } else { + return 1; /* enough items are already pre-allocated */ + } +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ diff --git a/common/lynxkdi.c b/common/lynxkdi.c new file mode 100644 index 0000000..797d8cc --- /dev/null +++ b/common/lynxkdi.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) Orbacom Systems, Inc + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ + +#include +#include +#include + +#if defined(CONFIG_LYNXKDI) +#include + +#if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR) +void lynxkdi_boot ( image_header_t *hdr ) +{ + void (*lynxkdi)(void) = (void(*)(void))hdr->ih_ep; + lynxos_bootparms_t *parms = (lynxos_bootparms_t *)0x0020; + bd_t *kbd; + DECLARE_GLOBAL_DATA_PTR; + u32 *psz = (u32 *)(hdr->ih_load + 0x0204); + + memset( parms, 0, sizeof(*parms)); + kbd = gd->bd; + parms->clock_ref = kbd->bi_busfreq; + parms->dramsz = kbd->bi_memsize; + memcpy(parms->ethaddr, kbd->bi_enetaddr, 6); + mtspr(SPRN_SPRG2, 0x0020); + + /* Do a simple check for Bluecat so we can pass the + * kernel command line parameters. + */ + if( le32_to_cpu(*psz) == hdr->ih_size ){ + char *args; + char *cmdline = (char *)(hdr->ih_load + 0x020c); + int len; + + printf("Booting Bluecat KDI ...\n"); + udelay(200*1000); /* Allow serial port to flush */ + if ((args = getenv("bootargs")) == NULL) + args = ""; + /* Prepend the cmdline */ + len = strlen(args); + if( len && (len + strlen(cmdline) + 2 < (0x0400 - 0x020c))) { + memmove( cmdline + strlen(args) + 1, cmdline, strlen(cmdline) ); + strcpy( cmdline, args ); + cmdline[len] = ' '; + } + } + else { + printf("Booting LynxOS KDI ...\n"); + } + + lynxkdi(); +} +#else +#error "Lynx KDI support not implemented for configured CPU" +#endif + +#endif /* CONFIG_LYNXKDI */ diff --git a/common/main.c b/common/main.c new file mode 100644 index 0000000..f042f3a --- /dev/null +++ b/common/main.c @@ -0,0 +1,999 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include +#include +#ifdef CONFIG_MODEM_SUPPORT +#include /* for free() prototype */ +#endif + +#ifdef CFG_HUSH_PARSER +#include +#endif + +#include + +#if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY) +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* for do_reset() prototype */ +#endif + +extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + + +#define MAX_DELAY_STOP_STR 32 + +static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen); +static int parse_line (char *, char *[]); +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) +static int abortboot(int); +#endif + +#undef DEBUG_PARSER + +char console_buffer[CFG_CBSIZE]; /* console I/O buffer */ + +static char erase_seq[] = "\b \b"; /* erase sequence */ +static char tab_seq[] = " "; /* used to expand TABs */ + +#ifdef CONFIG_BOOT_RETRY_TIME +static uint64_t endtime = 0; /* must be set, default is instant timeout */ +static int retry_time = -1; /* -1 so can call readline before main_loop */ +#endif + +#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk()) + +#ifndef CONFIG_BOOT_RETRY_MIN +#define CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME +#endif + +#ifdef CONFIG_MODEM_SUPPORT +int do_mdm_init = 0; +extern void mdm_init(void); /* defined in board.c */ +#endif + +/*************************************************************************** + * Watch for 'delay' seconds for autoboot stop or autoboot delay string. + * returns: 0 - no key string, allow autoboot + * 1 - got key string, abort + */ +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) +# if defined(CONFIG_AUTOBOOT_KEYED) +static __inline__ int abortboot(int bootdelay) +{ + int abort = 0; + uint64_t etime = endtick(bootdelay); + struct + { + char* str; + u_int len; + int retry; + } + delaykey [] = + { + { str: getenv ("bootdelaykey"), retry: 1 }, + { str: getenv ("bootdelaykey2"), retry: 1 }, + { str: getenv ("bootstopkey"), retry: 0 }, + { str: getenv ("bootstopkey2"), retry: 0 }, + }; + + char presskey [MAX_DELAY_STOP_STR]; + u_int presskey_len = 0; + u_int presskey_max = 0; + u_int i; + +#ifdef CONFIG_SILENT_CONSOLE + { + DECLARE_GLOBAL_DATA_PTR; + + if (gd->flags & GD_FLG_SILENT) { + /* Restore serial console */ + console_assign (stdout, "serial"); + console_assign (stderr, "serial"); + } + } +#endif + +# ifdef CONFIG_AUTOBOOT_PROMPT + printf (CONFIG_AUTOBOOT_PROMPT, bootdelay); +# endif + +# ifdef CONFIG_AUTOBOOT_DELAY_STR + if (delaykey[0].str == NULL) + delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR; +# endif +# ifdef CONFIG_AUTOBOOT_DELAY_STR2 + if (delaykey[1].str == NULL) + delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2; +# endif +# ifdef CONFIG_AUTOBOOT_STOP_STR + if (delaykey[2].str == NULL) + delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR; +# endif +# ifdef CONFIG_AUTOBOOT_STOP_STR2 + if (delaykey[3].str == NULL) + delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2; +# endif + + for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) { + delaykey[i].len = delaykey[i].str == NULL ? + 0 : strlen (delaykey[i].str); + delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ? + MAX_DELAY_STOP_STR : delaykey[i].len; + + presskey_max = presskey_max > delaykey[i].len ? + presskey_max : delaykey[i].len; + +# if DEBUG_BOOTKEYS + printf("%s key:<%s>\n", + delaykey[i].retry ? "delay" : "stop", + delaykey[i].str ? delaykey[i].str : "NULL"); +# endif + } + + /* In order to keep up with incoming data, check timeout only + * when catch up. + */ + while (!abort && get_ticks() <= etime) { + for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) { + if (delaykey[i].len > 0 && + presskey_len >= delaykey[i].len && + memcmp (presskey + presskey_len - delaykey[i].len, + delaykey[i].str, + delaykey[i].len) == 0) { +# if DEBUG_BOOTKEYS + printf("got %skey\n", + delaykey[i].retry ? "delay" : "stop"); +# endif + +# ifdef CONFIG_BOOT_RETRY_TIME + /* don't retry auto boot */ + if (! delaykey[i].retry) + retry_time = -1; +# endif + abort = 1; + } + } + + if (tstc()) { + if (presskey_len < presskey_max) { + presskey [presskey_len ++] = getc(); + } + else { + for (i = 0; i < presskey_max - 1; i ++) + presskey [i] = presskey [i + 1]; + + presskey [i] = getc(); + } + } + } +# if DEBUG_BOOTKEYS + if (!abort) + puts ("key timeout\n"); +# endif + +#ifdef CONFIG_SILENT_CONSOLE + { + DECLARE_GLOBAL_DATA_PTR; + + if (abort) { + /* permanently enable normal console output */ + gd->flags &= ~(GD_FLG_SILENT); + } else if (gd->flags & GD_FLG_SILENT) { + /* Restore silent console */ + console_assign (stdout, "nulldev"); + console_assign (stderr, "nulldev"); + } + } +#endif + + return abort; +} + +# else /* !defined(CONFIG_AUTOBOOT_KEYED) */ + +#ifdef CONFIG_MENUKEY +static int menukey = 0; +#endif + +static __inline__ int abortboot(int bootdelay) +{ + int abort = 0; + +#ifdef CONFIG_SILENT_CONSOLE + { + DECLARE_GLOBAL_DATA_PTR; + + if (gd->flags & GD_FLG_SILENT) { + /* Restore serial console */ + console_assign (stdout, "serial"); + console_assign (stderr, "serial"); + } + } +#endif + +#ifdef CONFIG_MENUPROMPT + printf(CONFIG_MENUPROMPT, bootdelay); +#else + printf("Hit any key to stop autoboot: %2d ", bootdelay); +#endif + +#if defined CONFIG_ZERO_BOOTDELAY_CHECK + /* + * Check if key already pressed + * Don't check if bootdelay < 0 + */ + if (bootdelay >= 0) { + if (tstc()) { /* we got a key press */ + (void) getc(); /* consume input */ + puts ("\b\b\b 0"); + abort = 1; /* don't auto boot */ + } + } +#endif + + while ((bootdelay > 0) && (!abort)) { + int i; + + --bootdelay; + /* delay 100 * 10ms */ + for (i=0; !abort && i<100; ++i) { + if (tstc()) { /* we got a key press */ + abort = 1; /* don't auto boot */ + bootdelay = 0; /* no more delay */ +# ifdef CONFIG_MENUKEY + menukey = getc(); +# else + (void) getc(); /* consume input */ +# endif + break; + } + udelay (10000); + } + + printf ("\b\b\b%2d ", bootdelay); + } + + putc ('\n'); + +#ifdef CONFIG_SILENT_CONSOLE + { + DECLARE_GLOBAL_DATA_PTR; + + if (abort) { + /* permanently enable normal console output */ + gd->flags &= ~(GD_FLG_SILENT); + } else if (gd->flags & GD_FLG_SILENT) { + /* Restore silent console */ + console_assign (stdout, "nulldev"); + console_assign (stderr, "nulldev"); + } + } +#endif + + return abort; +} +# endif /* CONFIG_AUTOBOOT_KEYED */ +#endif /* CONFIG_BOOTDELAY >= 0 */ + +/****************************************************************************/ + +void main_loop (void) +{ +#ifndef CFG_HUSH_PARSER + static char lastcommand[CFG_CBSIZE] = { 0, }; + int len; + int rc = 1; + int flag; +#endif + +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + char *s; + int bootdelay; +#endif +#ifdef CONFIG_PREBOOT + char *p; +#endif +#ifdef CONFIG_BOOTCOUNT_LIMIT + unsigned long bootcount = 0; + unsigned long bootlimit = 0; + char *bcs; + char bcs_set[16]; +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + +#if defined(CONFIG_VFD) && defined(VFD_TEST_LOGO) + ulong bmp = 0; /* default bitmap */ + extern int trab_vfd (ulong bitmap); + +#ifdef CONFIG_MODEM_SUPPORT + if (do_mdm_init) + bmp = 1; /* alternate bitmap */ +#endif + trab_vfd (bmp); +#endif /* CONFIG_VFD && VFD_TEST_LOGO */ + +#ifdef CONFIG_BOOTCOUNT_LIMIT + bootcount = bootcount_load(); + bootcount++; + bootcount_store (bootcount); + sprintf (bcs_set, "%lu", bootcount); + setenv ("bootcount", bcs_set); + bcs = getenv ("bootlimit"); + bootlimit = bcs ? simple_strtoul (bcs, NULL, 10) : 0; +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + +#ifdef CONFIG_MODEM_SUPPORT + debug ("DEBUG: main_loop: do_mdm_init=%d\n", do_mdm_init); + if (do_mdm_init) { + char *str = strdup(getenv("mdm_cmd")); + setenv ("preboot", str); /* set or delete definition */ + if (str != NULL) + free (str); + mdm_init(); /* wait for modem connection */ + } +#endif /* CONFIG_MODEM_SUPPORT */ + +#ifdef CONFIG_VERSION_VARIABLE + { + extern char version_string[]; + + setenv ("ver", version_string); /* set version variable */ + } +#endif /* CONFIG_VERSION_VARIABLE */ + +#ifdef CFG_HUSH_PARSER + u_boot_hush_start (); +#endif + +#ifdef CONFIG_AUTO_COMPLETE + install_auto_complete(); +#endif + +#ifdef CONFIG_PREBOOT + if ((p = getenv ("preboot")) != NULL) { +# ifdef CONFIG_AUTOBOOT_KEYED + int prev = disable_ctrlc(1); /* disable Control C checking */ +# endif + +# ifndef CFG_HUSH_PARSER + run_command (p, 0); +# else + parse_string_outer(p, FLAG_PARSE_SEMICOLON | + FLAG_EXIT_FROM_LOOP); +# endif + +# ifdef CONFIG_AUTOBOOT_KEYED + disable_ctrlc(prev); /* restore Control C checking */ +# endif + } +#endif /* CONFIG_PREBOOT */ + +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + s = getenv ("bootdelay"); + bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; + + debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay); + +# ifdef CONFIG_BOOT_RETRY_TIME + init_cmd_timeout (); +# endif /* CONFIG_BOOT_RETRY_TIME */ + +#ifdef CONFIG_BOOTCOUNT_LIMIT + if (bootlimit && (bootcount > bootlimit)) { + printf ("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n", + (unsigned)bootlimit); + s = getenv ("altbootcmd"); + } + else +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + s = getenv ("bootcmd"); + + debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : ""); + + if (bootdelay >= 0 && s && !abortboot (bootdelay)) { +# ifdef CONFIG_AUTOBOOT_KEYED + int prev = disable_ctrlc(1); /* disable Control C checking */ +# endif + +# ifndef CFG_HUSH_PARSER + run_command (s, 0); +# else + parse_string_outer(s, FLAG_PARSE_SEMICOLON | + FLAG_EXIT_FROM_LOOP); +# endif + +# ifdef CONFIG_AUTOBOOT_KEYED + disable_ctrlc(prev); /* restore Control C checking */ +# endif + } + +# ifdef CONFIG_MENUKEY + if (menukey == CONFIG_MENUKEY) { + s = getenv("menucmd"); + if (s) { +# ifndef CFG_HUSH_PARSER + run_command (s, 0); +# else + parse_string_outer(s, FLAG_PARSE_SEMICOLON | + FLAG_EXIT_FROM_LOOP); +# endif + } + } +#endif /* CONFIG_MENUKEY */ +#endif /* CONFIG_BOOTDELAY */ + +#ifdef CONFIG_AMIGAONEG3SE + { + extern void video_banner(void); + video_banner(); + } +#endif + + /* + * Main Loop for Monitor Command Processing + */ +#ifdef CFG_HUSH_PARSER + parse_file_outer(); + /* This point is never reached */ + for (;;); +#else + for (;;) { +#ifdef CONFIG_BOOT_RETRY_TIME + if (rc >= 0) { + /* Saw enough of a valid command to + * restart the timeout. + */ + reset_cmd_timeout(); + } +#endif + len = readline (CFG_PROMPT); + + flag = 0; /* assume no special flags for now */ + if (len > 0) + strcpy (lastcommand, console_buffer); + else if (len == 0) + flag |= CMD_FLAG_REPEAT; +#ifdef CONFIG_BOOT_RETRY_TIME + else if (len == -2) { + /* -2 means timed out, retry autoboot + */ + puts ("\nTimed out waiting for command\n"); +# ifdef CONFIG_RESET_TO_RETRY + /* Reinit board to run initialization code again */ + do_reset (NULL, 0, 0, NULL); +# else + return; /* retry autoboot */ +# endif + } +#endif + + if (len == -1) + puts ("\n"); + else + rc = run_command (lastcommand, flag); + + if (rc <= 0) { + /* invalid command or not repeatable, forget it */ + lastcommand[0] = 0; + } + } +#endif /*CFG_HUSH_PARSER*/ +} + +#ifdef CONFIG_BOOT_RETRY_TIME +/*************************************************************************** + * initialise command line timeout + */ +void init_cmd_timeout(void) +{ + char *s = getenv ("bootretry"); + + if (s != NULL) + retry_time = (int)simple_strtol(s, NULL, 10); + else + retry_time = CONFIG_BOOT_RETRY_TIME; + + if (retry_time >= 0 && retry_time < CONFIG_BOOT_RETRY_MIN) + retry_time = CONFIG_BOOT_RETRY_MIN; +} + +/*************************************************************************** + * reset command line timeout to retry_time seconds + */ +void reset_cmd_timeout(void) +{ + endtime = endtick(retry_time); +} +#endif + +/****************************************************************************/ + +/* + * Prompt for input and read a line. + * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0, + * time out when time goes past endtime (timebase time in ticks). + * Return: number of read characters + * -1 if break + * -2 if timed out + */ +int readline (const char *const prompt) +{ + char *p = console_buffer; + int n = 0; /* buffer index */ + int plen = 0; /* prompt length */ + int col; /* output column cnt */ + char c; + + /* print prompt */ + if (prompt) { + plen = strlen (prompt); + puts (prompt); + } + col = plen; + + for (;;) { +#ifdef CONFIG_BOOT_RETRY_TIME + while (!tstc()) { /* while no incoming data */ + if (retry_time >= 0 && get_ticks() > endtime) + return (-2); /* timed out */ + } +#endif + WATCHDOG_RESET(); /* Trigger watchdog, if needed */ + +#ifdef CONFIG_SHOW_ACTIVITY + while (!tstc()) { + extern void show_activity(int arg); + show_activity(0); + } +#endif + c = getc(); + + /* + * Special character handling + */ + switch (c) { + case '\r': /* Enter */ + case '\n': + *p = '\0'; + puts ("\r\n"); + return (p - console_buffer); + + case '\0': /* nul */ + continue; + + case 0x03: /* ^C - break */ + console_buffer[0] = '\0'; /* discard input */ + return (-1); + + case 0x15: /* ^U - erase line */ + while (col > plen) { + puts (erase_seq); + --col; + } + p = console_buffer; + n = 0; + continue; + + case 0x17: /* ^W - erase word */ + p=delete_char(console_buffer, p, &col, &n, plen); + while ((n > 0) && (*p != ' ')) { + p=delete_char(console_buffer, p, &col, &n, plen); + } + continue; + + case 0x08: /* ^H - backspace */ + case 0x7F: /* DEL - backspace */ + p=delete_char(console_buffer, p, &col, &n, plen); + continue; + + default: + /* + * Must be a normal character then + */ + if (n < CFG_CBSIZE-2) { + if (c == '\t') { /* expand TABs */ +#ifdef CONFIG_AUTO_COMPLETE + /* if auto completion triggered just continue */ + *p = '\0'; + if (cmd_auto_complete(prompt, console_buffer, &n, &col)) { + p = console_buffer + n; /* reset */ + continue; + } +#endif + puts (tab_seq+(col&07)); + col += 8 - (col&07); + } else { + ++col; /* echo input */ + putc (c); + } + *p++ = c; + ++n; + } else { /* Buffer full */ + putc ('\a'); + } + } + } +} + +/****************************************************************************/ + +static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen) +{ + char *s; + + if (*np == 0) { + return (p); + } + + if (*(--p) == '\t') { /* will retype the whole line */ + while (*colp > plen) { + puts (erase_seq); + (*colp)--; + } + for (s=buffer; s= CFG_CBSIZE) { + puts ("## Command too long!\n"); + return -1; + } + + strcpy (cmdbuf, cmd); + + /* Process separators and check for invalid + * repeatable commands + */ + +#ifdef DEBUG_PARSER + printf ("[PROCESS_SEPARATORS] %s\n", cmd); +#endif + while (*str) { + + /* + * Find separator, or string end + * Allow simple escape of ';' by writing "\;" + */ + for (inquotes = 0, sep = str; *sep; sep++) { + if ((*sep=='\'') && + (*(sep-1) != '\\')) + inquotes=!inquotes; + + if (!inquotes && + (*sep == ';') && /* separator */ + ( sep != str) && /* past string start */ + (*(sep-1) != '\\')) /* and NOT escaped */ + break; + } + + /* + * Limit the token to data between separators + */ + token = str; + if (*sep) { + str = sep + 1; /* start of command for next pass */ + *sep = '\0'; + } + else + str = sep; /* no more commands for next pass */ +#ifdef DEBUG_PARSER + printf ("token: \"%s\"\n", token); +#endif + + /* find macros in this token and replace them */ + process_macros (token, finaltoken); + + /* Extract arguments */ + argc = parse_line (finaltoken, argv); + + /* Look up command in command table */ + if ((cmdtp = find_cmd(argv[0])) == NULL) { + printf ("Unknown command '%s' - try 'help'\n", argv[0]); + rc = -1; /* give up after bad command */ + continue; + } + + /* found - check max args */ + if (argc > cmdtp->maxargs) { + printf ("Usage:\n%s\n", cmdtp->usage); + rc = -1; + continue; + } + +#if (CONFIG_COMMANDS & CFG_CMD_BOOTD) + /* avoid "bootd" recursion */ + if (cmdtp->cmd == do_bootd) { +#ifdef DEBUG_PARSER + printf ("[%s]\n", finaltoken); +#endif + if (flag & CMD_FLAG_BOOTD) { + puts ("'bootd' recursion detected\n"); + rc = -1; + continue; + } + else + flag |= CMD_FLAG_BOOTD; + } +#endif /* CFG_CMD_BOOTD */ + + /* OK - call function to do the command */ + if ((cmdtp->cmd) (cmdtp, flag, argc, argv) != 0) { + rc = -1; + } + + repeatable &= cmdtp->repeatable; + + /* Did the user stop this? */ + if (had_ctrlc ()) + return 0; /* if stopped then not repeatable */ + } + + return rc ? rc : repeatable; +} + +/****************************************************************************/ + +#if (CONFIG_COMMANDS & CFG_CMD_RUN) +int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + for (i=1; i> 1; cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + save[i++] = *addr; + *addr = ~cnt; + } + + addr = base; + save[i] = *addr; + *addr = 0; + + if ((val = *addr) != 0) { + /* Restore the original data before leaving the function. + */ + *addr = save[i]; + for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { + addr = base + cnt; + *addr = save[--i]; + } + return (0); + } + + for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + val = *addr; + *addr = save[--i]; + if (val != ~cnt) { + size = cnt * sizeof (long); + /* Restore the original data before leaving the function. + */ + for (cnt <<= 1; cnt < maxsize / sizeof (long); cnt <<= 1) { + addr = base + cnt; + *addr = save[--i]; + } + return (size); + } + } + + return (maxsize); +} diff --git a/common/miiphybb.c b/common/miiphybb.c new file mode 100644 index 0000000..adb697c --- /dev/null +++ b/common/miiphybb.c @@ -0,0 +1,240 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This provides a bit-banged interface to the ethernet MII management + * channel. + */ + +#include +#include +#include + +#ifdef CONFIG_BITBANGMII + + +/***************************************************************************** + * + * Utility to send the preamble, address, and register (common to read + * and write). + */ +static void miiphy_pre (char read, unsigned char addr, unsigned char reg) +{ + int j; /* counter */ +#ifndef CONFIG_EP8248 + volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); +#endif + + /* + * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure. + * The IEEE spec says this is a PHY optional requirement. The AMD + * 79C874 requires one after power up and one after a MII communications + * error. This means that we are doing more preambles than we need, + * but it is safer and will be much more robust. + */ + + MDIO_ACTIVE; + MDIO (1); + for (j = 0; j < 32; j++) { + MDC (0); + MIIDELAY; + MDC (1); + MIIDELAY; + } + + /* send the start bit (01) and the read opcode (10) or write (10) */ + MDC (0); + MDIO (0); + MIIDELAY; + MDC (1); + MIIDELAY; + MDC (0); + MDIO (1); + MIIDELAY; + MDC (1); + MIIDELAY; + MDC (0); + MDIO (read); + MIIDELAY; + MDC (1); + MIIDELAY; + MDC (0); + MDIO (!read); + MIIDELAY; + MDC (1); + MIIDELAY; + + /* send the PHY address */ + for (j = 0; j < 5; j++) { + MDC (0); + if ((addr & 0x10) == 0) { + MDIO (0); + } else { + MDIO (1); + } + MIIDELAY; + MDC (1); + MIIDELAY; + addr <<= 1; + } + + /* send the register address */ + for (j = 0; j < 5; j++) { + MDC (0); + if ((reg & 0x10) == 0) { + MDIO (0); + } else { + MDIO (1); + } + MIIDELAY; + MDC (1); + MIIDELAY; + reg <<= 1; + } +} + + +/***************************************************************************** + * + * Read a MII PHY register. + * + * Returns: + * 0 on success + */ +int bb_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + short rdreg; /* register working value */ + int j; /* counter */ +#ifndef CONFIG_EP8248 + volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); +#endif + + miiphy_pre (1, addr, reg); + + /* tri-state our MDIO I/O pin so we can read */ + MDC (0); + MDIO_TRISTATE; + MIIDELAY; + MDC (1); + MIIDELAY; + + /* check the turnaround bit: the PHY should be driving it to zero */ + if (MDIO_READ != 0) { + /* puts ("PHY didn't drive TA low\n"); */ + for (j = 0; j < 32; j++) { + MDC (0); + MIIDELAY; + MDC (1); + MIIDELAY; + } + return (-1); + } + + MDC (0); + MIIDELAY; + + /* read 16 bits of register data, MSB first */ + rdreg = 0; + for (j = 0; j < 16; j++) { + MDC (1); + MIIDELAY; + rdreg <<= 1; + rdreg |= MDIO_READ; + MDC (0); + MIIDELAY; + } + + MDC (1); + MIIDELAY; + MDC (0); + MIIDELAY; + MDC (1); + MIIDELAY; + + *value = rdreg; + +#ifdef DEBUG + printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value); +#endif + + return 0; +} + + +/***************************************************************************** + * + * Write a MII PHY register. + * + * Returns: + * 0 on success + */ +int bb_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + int j; /* counter */ +#ifndef CONFIG_EP8248 + volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); +#endif + + miiphy_pre (0, addr, reg); + + /* send the turnaround (10) */ + MDC (0); + MDIO (1); + MIIDELAY; + MDC (1); + MIIDELAY; + MDC (0); + MDIO (0); + MIIDELAY; + MDC (1); + MIIDELAY; + + /* write 16 bits of register data, MSB first */ + for (j = 0; j < 16; j++) { + MDC (0); + if ((value & 0x00008000) == 0) { + MDIO (0); + } else { + MDIO (1); + } + MIIDELAY; + MDC (1); + MIIDELAY; + value <<= 1; + } + + /* + * Tri-state the MDIO line. + */ + MDIO_TRISTATE; + MDC (0); + MIIDELAY; + MDC (1); + MIIDELAY; + + return 0; +} + +#endif /* CONFIG_BITBANGMII */ diff --git a/common/miiphyutil.c b/common/miiphyutil.c new file mode 100644 index 0000000..e411e57 --- /dev/null +++ b/common/miiphyutil.c @@ -0,0 +1,473 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This provides a bit-banged interface to the ethernet MII management + * channel. + */ + +#include +#include + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#include +#include +#include +#include + +/* local debug macro */ +#define MII_DEBUG +#undef MII_DEBUG + +#undef debug +#ifdef MII_DEBUG +#define debug(fmt,args...) printf (fmt ,##args) +#else +#define debug(fmt,args...) +#endif /* MII_DEBUG */ + +struct mii_dev { + struct list_head link; + char *name; + int (* read)(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); + int (* write)(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +}; + +static struct list_head mii_devs; +static struct mii_dev *current_mii; + +/***************************************************************************** + * + * Initialize global data. Need to be called before any other miiphy routine. + */ +void miiphy_init() +{ + INIT_LIST_HEAD(&mii_devs); + current_mii = NULL; +} + +/***************************************************************************** + * + * Register read and write MII access routines for the device . + */ +void miiphy_register(char *name, + int (* read)(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value), + int (* write)(char *devname, unsigned char addr, + unsigned char reg, unsigned short value)) +{ + struct list_head *entry; + struct mii_dev *new_dev; + struct mii_dev *miidev; + unsigned int name_len; + + /* check if we have unique name */ + list_for_each(entry, &mii_devs) { + miidev = list_entry(entry, struct mii_dev, link); + if (strcmp(miidev->name, name) == 0) { + printf("miiphy_register: non unique device name '%s'\n", + name); + return; + } + } + + /* allocate memory */ + name_len = strlen(name); + new_dev = (struct mii_dev *)malloc(sizeof(struct mii_dev) + name_len + 1); + + if(new_dev == NULL) { + printf("miiphy_register: cannot allocate memory for '%s'\n", + name); + return; + } + memset(new_dev, 0, sizeof(struct mii_dev) + name_len); + + /* initalize mii_dev struct fields */ + INIT_LIST_HEAD(&new_dev->link); + new_dev->read = read; + new_dev->write = write; + new_dev->name = (char *)(new_dev + 1); + strncpy(new_dev->name, name, name_len); + new_dev->name[name_len] = '\0'; + + debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n", + new_dev->name, new_dev->read, new_dev->write); + + /* add it to the list */ + list_add_tail(&new_dev->link, &mii_devs); + + if (!current_mii) + current_mii = new_dev; +} + +int miiphy_set_current_dev(char *devname) +{ + struct list_head *entry; + struct mii_dev *dev; + + list_for_each(entry, &mii_devs) { + dev = list_entry(entry, struct mii_dev, link); + + if (strcmp(devname, dev->name) == 0) { + current_mii = dev; + return 0; + } + } + + printf("No such device: %s\n", devname); + return 1; +} + +char *miiphy_get_current_dev() +{ + if (current_mii) + return current_mii->name; + + return NULL; +} + +/***************************************************************************** + * + * Read to variable from the PHY attached to device , + * use PHY address and register . + * + * Returns: + * 0 on success + */ +int miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + struct list_head *entry; + struct mii_dev *dev; + int found_dev = 0; + int read_ret = 0; + + if (!devname) { + printf("NULL device name!\n"); + return 1; + } + + list_for_each(entry, &mii_devs) { + dev = list_entry(entry, struct mii_dev, link); + + if (strcmp(devname, dev->name) == 0) { + found_dev = 1; + read_ret = dev->read(devname, addr, reg, value); + break; + } + } + + if (found_dev == 0) + printf("No such device: %s\n", devname); + + return ((found_dev) ? read_ret : 1); +} + +/***************************************************************************** + * + * Write to the PHY attached to device , + * use PHY address and register . + * + * Returns: + * 0 on success + */ +int miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + struct list_head *entry; + struct mii_dev *dev; + int found_dev = 0; + int write_ret = 0; + + if (!devname) { + printf("NULL device name!\n"); + return 1; + } + + list_for_each(entry, &mii_devs) { + dev = list_entry(entry, struct mii_dev, link); + + if (strcmp(devname, dev->name) == 0) { + found_dev = 1; + write_ret = dev->write(devname, addr, reg, value); + break; + } + } + + if (found_dev == 0) + printf("No such device: %s\n", devname); + + return ((found_dev) ? write_ret : 1); +} + +/***************************************************************************** + * + * Print out list of registered MII capable devices. + */ +void miiphy_listdev(void) +{ + struct list_head *entry; + struct mii_dev *dev; + + puts("MII devices: "); + list_for_each(entry, &mii_devs) { + dev = list_entry(entry, struct mii_dev, link); + printf("'%s' ", dev->name); + } + puts("\n"); + + if (current_mii) + printf("Current device: '%s'\n", current_mii->name); +} + + +/***************************************************************************** + * + * Read the OUI, manufacture's model number, and revision number. + * + * OUI: 22 bits (unsigned int) + * Model: 6 bits (unsigned char) + * Revision: 4 bits (unsigned char) + * + * Returns: + * 0 on success + */ +int miiphy_info (char *devname, + unsigned char addr, + unsigned int *oui, + unsigned char *model, unsigned char *rev) +{ + unsigned int reg = 0; + unsigned short tmp; + + if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) { +#ifdef DEBUG + puts ("PHY ID register 2 read failed\n"); +#endif + return (-1); + } + reg = tmp; + +#ifdef DEBUG + printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg); +#endif + if (reg == 0xFFFF) { + /* No physical device present at this address */ + return (-1); + } + + if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) { +#ifdef DEBUG + puts ("PHY ID register 1 read failed\n"); +#endif + return (-1); + } + reg |= tmp << 16; +#ifdef DEBUG + printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg); +#endif + *oui = ( reg >> 10); + *model = (unsigned char) ((reg >> 4) & 0x0000003F); + *rev = (unsigned char) ( reg & 0x0000000F); + return (0); +} + + +/***************************************************************************** + * + * Reset the PHY. + * Returns: + * 0 on success + */ +int miiphy_reset (char *devname, unsigned char addr) +{ + unsigned short reg; + int loop_cnt; + + if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { +#ifdef DEBUG + printf ("PHY status read failed\n"); +#endif + return (-1); + } + if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) { +#ifdef DEBUG + puts ("PHY reset failed\n"); +#endif + return (-1); + } +#ifdef CONFIG_PHY_RESET_DELAY + udelay (CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ +#endif + /* + * Poll the control register for the reset bit to go to 0 (it is + * auto-clearing). This should happen within 0.5 seconds per the + * IEEE spec. + */ + loop_cnt = 0; + reg = 0x8000; + while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) { + if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { +# ifdef DEBUG + puts ("PHY status read failed\n"); +# endif + return (-1); + } + } + if ((reg & 0x8000) == 0) { + return (0); + } else { + puts ("PHY reset timed out\n"); + return (-1); + } + return (0); +} + + +/***************************************************************************** + * + * Determine the ethernet speed (10/100). + */ +int miiphy_speed (char *devname, unsigned char addr) +{ + unsigned short reg; + +#if defined(CONFIG_PHY_GIGE) + if (miiphy_read (devname, addr, PHY_1000BTSR, ®)) { + printf ("PHY 1000BT Status read failed\n"); + } else { + if (reg != 0xFFFF) { + if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) { + return (_1000BASET); + } + } + } +#endif /* CONFIG_PHY_GIGE */ + + /* Check Basic Management Control Register first. */ + if (miiphy_read (devname, addr, PHY_BMCR, ®)) { + puts ("PHY speed read failed, assuming 10bT\n"); + return (_10BASET); + } + /* Check if auto-negotiation is on. */ + if ((reg & PHY_BMCR_AUTON) != 0) { + /* Get auto-negotiation results. */ + if (miiphy_read (devname, addr, PHY_ANLPAR, ®)) { + puts ("PHY AN speed read failed, assuming 10bT\n"); + return (_10BASET); + } + if ((reg & PHY_ANLPAR_100) != 0) { + return (_100BASET); + } else { + return (_10BASET); + } + } + /* Get speed from basic control settings. */ + else if (reg & PHY_BMCR_100MB) { + return (_100BASET); + } else { + return (_10BASET); + } + +} + + +/***************************************************************************** + * + * Determine full/half duplex. + */ +int miiphy_duplex (char *devname, unsigned char addr) +{ + unsigned short reg; + +#if defined(CONFIG_PHY_GIGE) + if (miiphy_read (devname, addr, PHY_1000BTSR, ®)) { + printf ("PHY 1000BT Status read failed\n"); + } else { + if ( (reg != 0xFFFF) && + (reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) { + if ((reg & PHY_1000BTSR_1000FD) !=0) { + return (FULL); + } else { + return (HALF); + } + } + } +#endif /* CONFIG_PHY_GIGE */ + + /* Check Basic Management Control Register first. */ + if (miiphy_read (devname, addr, PHY_BMCR, ®)) { + puts ("PHY duplex read failed, assuming half duplex\n"); + return (HALF); + } + /* Check if auto-negotiation is on. */ + if ((reg & PHY_BMCR_AUTON) != 0) { + /* Get auto-negotiation results. */ + if (miiphy_read (devname, addr, PHY_ANLPAR, ®)) { + puts ("PHY AN duplex read failed, assuming half duplex\n"); + return (HALF); + } + + if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) { + return (FULL); + } else { + return (HALF); + } + } + /* Get speed from basic control settings. */ + else if (reg & PHY_BMCR_DPLX) { + return (FULL); + } else { + return (HALF); + } + +} + +#ifdef CFG_FAULT_ECHO_LINK_DOWN +/***************************************************************************** + * + * Determine link status + */ +int miiphy_link (char *devname, unsigned char addr) +{ + unsigned short reg; + + /* dummy read; needed to latch some phys */ + (void)miiphy_read(devname, addr, PHY_BMSR, ®); + if (miiphy_read (devname, addr, PHY_BMSR, ®)) { + puts ("PHY_BMSR read failed, assuming no link\n"); + return (0); + } + + /* Determine if a link is active */ + if ((reg & PHY_BMSR_LS) != 0) { + return (1); + } else { + return (0); + } +} +#endif + +#endif /* CONFIG_MII || (CONFIG_COMMANDS & CFG_CMD_MII) */ diff --git a/common/s_record.c b/common/s_record.c new file mode 100644 index 0000000..c52bf1b --- /dev/null +++ b/common/s_record.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +static int hex1_bin (char c); +static int hex2_bin (char *s); + +int srec_decode (char *input, int *count, ulong *addr, char *data) +{ + int i; + int v; /* conversion buffer */ + int srec_type; /* S-Record type */ + unsigned char chksum; /* buffer for checksum */ + + chksum = 0; + + /* skip anything before 'S', and the 'S' itself. + * Return error if not found + */ + + for (; *input; ++input) { + if (*input == 'S') { /* skip 'S' */ + ++input; + break; + } + } + if (*input == '\0') { /* no more data? */ + return (SREC_EMPTY); + } + + v = *input++; /* record type */ + + if ((*count = hex2_bin(input)) < 0) { + return (SREC_E_NOSREC); + } + + chksum += *count; + input += 2; + + switch (v) { /* record type */ + + case '0': /* start record */ + srec_type = SREC_START; /* 2 byte addr field */ + *count -= 3; /* - checksum and addr */ + break; + case '1': + srec_type = SREC_DATA2; /* 2 byte addr field */ + *count -= 3; /* - checksum and addr */ + break; + case '2': + srec_type = SREC_DATA3; /* 3 byte addr field */ + *count -= 4; /* - checksum and addr */ + break; + case '3': /* data record with a */ + srec_type = SREC_DATA4; /* 4 byte addr field */ + *count -= 5; /* - checksum and addr */ + break; +/*** case '4' ***/ + case '5': /* count record, addr field contains */ + srec_type = SREC_COUNT; /* a 2 byte record counter */ + *count = 0; /* no data */ + break; +/*** case '6' -- not used ***/ + case '7': /* end record with a */ + srec_type = SREC_END4; /* 4 byte addr field */ + *count -= 5; /* - checksum and addr */ + break; + case '8': /* end record with a */ + srec_type = SREC_END3; /* 3 byte addr field */ + *count -= 4; /* - checksum and addr */ + break; + case '9': /* end record with a */ + srec_type = SREC_END2; /* 2 byte addr field */ + *count -= 3; /* - checksum and addr */ + break; + default: + return (SREC_E_BADTYPE); + } + + /* read address field */ + *addr = 0; + + switch (v) { + case '3': /* 4 byte addr field */ + case '7': + if ((v = hex2_bin(input)) < 0) { + return (SREC_E_NOSREC); + } + *addr += v; + chksum += v; + input += 2; + /* FALL THRU */ + case '2': /* 3 byte addr field */ + case '8': + if ((v = hex2_bin(input)) < 0) { + return (SREC_E_NOSREC); + } + *addr <<= 8; + *addr += v; + chksum += v; + input += 2; + /* FALL THRU */ + case '0': /* 2 byte addr field */ + case '1': + case '5': + case '9': + if ((v = hex2_bin(input)) < 0) { + return (SREC_E_NOSREC); + } + *addr <<= 8; + *addr += v; + chksum += v; + input += 2; + + if ((v = hex2_bin(input)) < 0) { + return (SREC_E_NOSREC); + } + *addr <<= 8; + *addr += v; + chksum += v; + input += 2; + + break; + default: + return (SREC_E_BADTYPE); + } + + /* convert data and calculate checksum */ + for (i=0; i < *count; ++i) { + if ((v = hex2_bin(input)) < 0) { + return (SREC_E_NOSREC); + } + data[i] = v; + chksum += v; + input += 2; + } + + /* read anc check checksum */ + if ((v = hex2_bin(input)) < 0) { + return (SREC_E_NOSREC); + } + + if ((unsigned char)v != (unsigned char)~chksum) { + return (SREC_E_BADCHKS); + } + + return (srec_type); +} + +static int hex1_bin (char c) +{ + if (c >= '0' && c <= '9') + return (c - '0'); + if (c >= 'a' && c <= 'f') + return (c + 10 - 'a'); + if (c >= 'A' && c <= 'F') + return (c + 10 - 'A'); + return (-1); +} + +static int hex2_bin (char *s) +{ + int i, j; + + if ((i = hex1_bin(*s++)) < 0) { + return (-1); + } + if ((j = hex1_bin(*s)) < 0) { + return (-1); + } + + return ((i<<4) + j); +} diff --git a/common/serial.c b/common/serial.c new file mode 100644 index 0000000..22d8fd0 --- /dev/null +++ b/common/serial.c @@ -0,0 +1,213 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_SERIAL_MULTI) + +static struct serial_device *serial_devices = NULL; +static struct serial_device *serial_current = NULL; + +#ifndef CONFIG_LWMON +struct serial_device *default_serial_console (void) +{ +#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) + return &serial_smc_device; +#elif defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \ + || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) + return &serial_scc_device; +#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ + || defined(CONFIG_405EP) + return &serial0_device; +#else +#error No default console +#endif +} +#endif + +static int serial_register (struct serial_device *dev) +{ + DECLARE_GLOBAL_DATA_PTR; + + dev->init += gd->reloc_off; + dev->setbrg += gd->reloc_off; + dev->getc += gd->reloc_off; + dev->tstc += gd->reloc_off; + dev->putc += gd->reloc_off; + dev->puts += gd->reloc_off; + + dev->next = serial_devices; + serial_devices = dev; + + return 0; +} + +void serial_initialize (void) +{ +#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) + serial_register (&serial_smc_device); +#endif +#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \ + || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) + serial_register (&serial_scc_device); +#endif + +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ + || defined(CONFIG_405EP) + serial_register(&serial0_device); + serial_register(&serial1_device); +#endif + + serial_assign (default_serial_console ()->name); +} + +void serial_devices_init (void) +{ + device_t dev; + struct serial_device *s = serial_devices; + + while (s) { + memset (&dev, 0, sizeof (dev)); + + strcpy (dev.name, s->name); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; + + dev.start = s->init; + dev.putc = s->putc; + dev.puts = s->puts; + dev.getc = s->getc; + dev.tstc = s->tstc; + + device_register (&dev); + + s = s->next; + } +} + +int serial_assign (char *name) +{ + struct serial_device *s; + + for (s = serial_devices; s; s = s->next) { + if (strcmp (s->name, name) == 0) { + serial_current = s; + return 0; + } + } + + return 1; +} + +void serial_reinit_all (void) +{ + struct serial_device *s; + + for (s = serial_devices; s; s = s->next) { + s->init (); + } +} + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (!(gd->flags & GD_FLG_RELOC) || !serial_current) { + struct serial_device *dev = default_serial_console (); + + return dev->init (); + } + + return serial_current->init (); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (!(gd->flags & GD_FLG_RELOC) || !serial_current) { + struct serial_device *dev = default_serial_console (); + + dev->setbrg (); + return; + } + + serial_current->setbrg (); +} + +int serial_getc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (!(gd->flags & GD_FLG_RELOC) || !serial_current) { + struct serial_device *dev = default_serial_console (); + + return dev->getc (); + } + + return serial_current->getc (); +} + +int serial_tstc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (!(gd->flags & GD_FLG_RELOC) || !serial_current) { + struct serial_device *dev = default_serial_console (); + + return dev->tstc (); + } + + return serial_current->tstc (); +} + +void serial_putc (const char c) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (!(gd->flags & GD_FLG_RELOC) || !serial_current) { + struct serial_device *dev = default_serial_console (); + + dev->putc (c); + return; + } + + serial_current->putc (c); +} + +void serial_puts (const char *s) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (!(gd->flags & GD_FLG_RELOC) || !serial_current) { + struct serial_device *dev = default_serial_console (); + + dev->puts (s); + return; + } + + serial_current->puts (s); +} + +#endif /* CONFIG_SERIAL_MULTI */ diff --git a/common/soft_i2c.c b/common/soft_i2c.c new file mode 100644 index 0000000..3d0e08c --- /dev/null +++ b/common/soft_i2c.c @@ -0,0 +1,418 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This has been changed substantially by Gerald Van Baren, Custom IDEAS, + * vanbaren@cideas.com. It was heavily influenced by LiMon, written by + * Neil Russell. + */ + +#include +#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ +#include +#endif +#ifdef CONFIG_AT91RM9200DK /* need this for the at91rm9200dk */ +#include +#include +#endif +#include + +#if defined(CONFIG_SOFT_I2C) + +/* #define DEBUG_I2C */ + + +/*----------------------------------------------------------------------- + * Definitions + */ + +#define RETRIES 0 + + +#define I2C_ACK 0 /* PD_SDA level to ack a byte */ +#define I2C_NOACK 1 /* PD_SDA level to noack a byte */ + + +#ifdef DEBUG_I2C +#define PRINTD(fmt,args...) do { \ + DECLARE_GLOBAL_DATA_PTR; \ + if (gd->have_console) \ + printf (fmt ,##args); \ + } while (0) +#else +#define PRINTD(fmt,args...) +#endif + +/*----------------------------------------------------------------------- + * Local functions + */ +static void send_reset (void); +static void send_start (void); +static void send_stop (void); +static void send_ack (int); +static int write_byte (uchar byte); +static uchar read_byte (int); + + +/*----------------------------------------------------------------------- + * Send a reset sequence consisting of 9 clocks with the data signal high + * to clock any confused device back into an idle state. Also send a + * at the end of the sequence for belts & suspenders. + */ +static void send_reset(void) +{ +#ifdef CONFIG_MPC8260 + volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); +#endif +#ifdef CONFIG_8xx + volatile immap_t *immr = (immap_t *)CFG_IMMR; +#endif + int j; + + I2C_SCL(1); + I2C_SDA(1); +#ifdef I2C_INIT + I2C_INIT; +#endif + I2C_TRISTATE; + for(j = 0; j < 9; j++) { + I2C_SCL(0); + I2C_DELAY; + I2C_DELAY; + I2C_SCL(1); + I2C_DELAY; + I2C_DELAY; + } + send_stop(); + I2C_TRISTATE; +} + +/*----------------------------------------------------------------------- + * START: High -> Low on SDA while SCL is High + */ +static void send_start(void) +{ +#ifdef CONFIG_MPC8260 + volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); +#endif +#ifdef CONFIG_8xx + volatile immap_t *immr = (immap_t *)CFG_IMMR; +#endif + + I2C_DELAY; + I2C_SDA(1); + I2C_ACTIVE; + I2C_DELAY; + I2C_SCL(1); + I2C_DELAY; + I2C_SDA(0); + I2C_DELAY; +} + +/*----------------------------------------------------------------------- + * STOP: Low -> High on SDA while SCL is High + */ +static void send_stop(void) +{ +#ifdef CONFIG_MPC8260 + volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); +#endif +#ifdef CONFIG_8xx + volatile immap_t *immr = (immap_t *)CFG_IMMR; +#endif + + I2C_SCL(0); + I2C_DELAY; + I2C_SDA(0); + I2C_ACTIVE; + I2C_DELAY; + I2C_SCL(1); + I2C_DELAY; + I2C_SDA(1); + I2C_DELAY; + I2C_TRISTATE; +} + + +/*----------------------------------------------------------------------- + * ack should be I2C_ACK or I2C_NOACK + */ +static void send_ack(int ack) +{ +#ifdef CONFIG_MPC8260 + volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); +#endif +#ifdef CONFIG_8xx + volatile immap_t *immr = (immap_t *)CFG_IMMR; +#endif + + I2C_ACTIVE; + I2C_SCL(0); + I2C_DELAY; + + I2C_SDA(ack); + + I2C_ACTIVE; + I2C_DELAY; + I2C_SCL(1); + I2C_DELAY; + I2C_DELAY; + I2C_SCL(0); + I2C_DELAY; +} + + +/*----------------------------------------------------------------------- + * Send 8 bits and look for an acknowledgement. + */ +static int write_byte(uchar data) +{ +#ifdef CONFIG_MPC8260 + volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); +#endif +#ifdef CONFIG_8xx + volatile immap_t *immr = (immap_t *)CFG_IMMR; +#endif + int j; + int nack; + + I2C_ACTIVE; + for(j = 0; j < 8; j++) { + I2C_SCL(0); + I2C_DELAY; + I2C_SDA(data & 0x80); + I2C_DELAY; + I2C_SCL(1); + I2C_DELAY; + I2C_DELAY; + + data <<= 1; + } + + /* + * Look for an (negative logic) and return it. + */ + I2C_SCL(0); + I2C_DELAY; + I2C_SDA(1); + I2C_TRISTATE; + I2C_DELAY; + I2C_SCL(1); + I2C_DELAY; + I2C_DELAY; + nack = I2C_READ; + I2C_SCL(0); + I2C_DELAY; + I2C_ACTIVE; + + return(nack); /* not a nack is an ack */ +} + + +/*----------------------------------------------------------------------- + * if ack == I2C_ACK, ACK the byte so can continue reading, else + * send I2C_NOACK to end the read. + */ +static uchar read_byte(int ack) +{ +#ifdef CONFIG_MPC8260 + volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); +#endif +#ifdef CONFIG_8xx + volatile immap_t *immr = (immap_t *)CFG_IMMR; +#endif + int data; + int j; + + /* + * Read 8 bits, MSB first. + */ + I2C_TRISTATE; + data = 0; + for(j = 0; j < 8; j++) { + I2C_SCL(0); + I2C_DELAY; + I2C_SCL(1); + I2C_DELAY; + data <<= 1; + data |= I2C_READ; + I2C_DELAY; + } + send_ack(ack); + + return(data); +} + +/*=====================================================================*/ +/* Public Functions */ +/*=====================================================================*/ + +/*----------------------------------------------------------------------- + * Initialization + */ +void i2c_init (int speed, int slaveaddr) +{ + /* + * WARNING: Do NOT save speed in a static variable: if the + * I2C routines are called before RAM is initialized (to read + * the DIMM SPD, for instance), RAM won't be usable and your + * system will crash. + */ + send_reset (); +} + +/*----------------------------------------------------------------------- + * Probe to see if a chip is present. Also good for checking for the + * completion of EEPROM writes since the chip stops responding until + * the write completes (typically 10mSec). + */ +int i2c_probe(uchar addr) +{ + int rc; + + /* perform 1 byte read transaction */ + send_start(); + rc = write_byte ((addr << 1) | 0); + send_stop(); + + return (rc ? 1 : 0); +} + +/*----------------------------------------------------------------------- + * Read bytes + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int shift; + PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n", + chip, addr, alen, buffer, len); + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + + PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n", + chip, addr); +#endif + + /* + * Do the addressing portion of a write cycle to set the + * chip's address pointer. If the address length is zero, + * don't do the normal write cycle to set the address pointer, + * there is no address pointer in this chip. + */ + send_start(); + if(alen > 0) { + if(write_byte(chip << 1)) { /* write cycle */ + send_stop(); + PRINTD("i2c_read, no chip responded %02X\n", chip); + return(1); + } + shift = (alen-1) * 8; + while(alen-- > 0) { + if(write_byte(addr >> shift)) { + PRINTD("i2c_read, address not ed\n"); + return(1); + } + shift -= 8; + } + send_stop(); /* reportedly some chips need a full stop */ + send_start(); + } + /* + * Send the chip address again, this time for a read cycle. + * Then read the data. On the last byte, we do a NACK instead + * of an ACK(len == 0) to terminate the read. + */ + write_byte((chip << 1) | 1); /* read cycle */ + while(len-- > 0) { + *buffer++ = read_byte(len == 0); + } + send_stop(); + return(0); +} + +/*----------------------------------------------------------------------- + * Write bytes + */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int shift, failures = 0; + + PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n", + chip, addr, alen, buffer, len); + + send_start(); + if(write_byte(chip << 1)) { /* write cycle */ + send_stop(); + PRINTD("i2c_write, no chip responded %02X\n", chip); + return(1); + } + shift = (alen-1) * 8; + while(alen-- > 0) { + if(write_byte(addr >> shift)) { + PRINTD("i2c_write, address not ed\n"); + return(1); + } + shift -= 8; + } + + while(len-- > 0) { + if(write_byte(*buffer++)) { + failures++; + } + } + send_stop(); + return(failures); +} + +/*----------------------------------------------------------------------- + * Read a register + */ +uchar i2c_reg_read(uchar i2c_addr, uchar reg) +{ + uchar buf; + + i2c_read(i2c_addr, reg, 1, &buf, 1); + + return(buf); +} + +/*----------------------------------------------------------------------- + * Write a register + */ +void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write(i2c_addr, reg, 1, &val, 1); +} + + +#endif /* CONFIG_SOFT_I2C */ diff --git a/common/soft_spi.c b/common/soft_spi.c new file mode 100644 index 0000000..00a57de --- /dev/null +++ b/common/soft_spi.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2002 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * Influenced by code from: + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_SOFT_SPI) + +/*----------------------------------------------------------------------- + * Definitions + */ + +#ifdef DEBUG_SPI +#define PRINTD(fmt,args...) printf (fmt ,##args) +#else +#define PRINTD(fmt,args...) +#endif + + +/*=====================================================================*/ +/* Public Functions */ +/*=====================================================================*/ + +/*----------------------------------------------------------------------- + * Initialization + */ +void spi_init (void) +{ +#ifdef SPI_INIT + volatile immap_t *immr = (immap_t *)CFG_IMMR; + + SPI_INIT; +#endif +} + + +/*----------------------------------------------------------------------- + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks + * "bitlen" bits in the SPI MISO port. That's just the way SPI works. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that "dout" + * and "din" can point to the same memory location, in which case the + * input data overwrites the output data (since both are buffered by + * temporary variables, this is OK). + * + * If the chipsel() function is not NULL, it is called with a parameter + * of '1' (chip select active) at the start of the transfer and again with + * a parameter of '0' at the end of the transfer. + * + * If the chipsel() function _is_ NULL, it the responsibility of the + * caller to make the appropriate chip select active before calling + * spi_xfer() and making it inactive after spi_xfer() returns. + */ +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uchar tmpdin = 0; + uchar tmpdout = 0; + int j; + + PRINTD("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", + (int)chipsel, *(uint *)dout, *(uint *)din, bitlen); + + if(chipsel != NULL) { + (*chipsel)(1); /* select the target chip */ + } + + for(j = 0; j < bitlen; j++) { + /* + * Check if it is time to work on a new byte. + */ + if((j % 8) == 0) { + tmpdout = *dout++; + if(j != 0) { + *din++ = tmpdin; + } + tmpdin = 0; + } + SPI_SCL(0); + SPI_SDA(tmpdout & 0x80); + SPI_DELAY; + SPI_SCL(1); + SPI_DELAY; + tmpdin <<= 1; + tmpdin |= SPI_READ; + tmpdout <<= 1; + } + /* + * If the number of bits isn't a multiple of 8, shift the last + * bits over to left-justify them. Then store the last byte + * read in. + */ + if((bitlen % 8) != 0) + tmpdin <<= 8 - (bitlen % 8); + *din++ = tmpdin; + + SPI_SCL(0); /* SPI wants the clock left low for idle */ + + if(chipsel != NULL) { + (*chipsel)(0); /* deselect the target chip */ + + } + + return(0); +} + +#endif /* CONFIG_SOFT_SPI */ diff --git a/common/spartan2.c b/common/spartan2.c new file mode 100644 index 0000000..0fb23b6 --- /dev/null +++ b/common/spartan2.c @@ -0,0 +1,653 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include /* core U-Boot definitions */ +#include /* Spartan-II device family */ + +#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2)) + +/* Define FPGA_DEBUG to get debug printf's */ +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#undef CFG_FPGA_CHECK_BUSY +#undef CFG_FPGA_PROG_FEEDBACK + +/* Note: The assumption is that we cannot possibly run fast enough to + * overrun the device (the Slave Parallel mode can free run at 50MHz). + * If there is a need to operate slower, define CONFIG_FPGA_DELAY in + * the board config file to slow things down. + */ +#ifndef CONFIG_FPGA_DELAY +#define CONFIG_FPGA_DELAY() +#endif + +#ifndef CFG_FPGA_WAIT +#define CFG_FPGA_WAIT CFG_HZ/100 /* 10 ms */ +#endif + +static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); +static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); +/* static int Spartan2_sp_info( Xilinx_desc *desc ); */ +static int Spartan2_sp_reloc( Xilinx_desc *desc, ulong reloc_offset ); + +static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); +static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); +/* static int Spartan2_ss_info( Xilinx_desc *desc ); */ +static int Spartan2_ss_reloc( Xilinx_desc *desc, ulong reloc_offset ); + +/* ------------------------------------------------------------------------- */ +/* Spartan-II Generic Implementation */ +int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case slave_serial: + PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); + ret_val = Spartan2_ss_load (desc, buf, bsize); + break; + + case slave_parallel: + PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); + ret_val = Spartan2_sp_load (desc, buf, bsize); + break; + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case slave_serial: + PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); + ret_val = Spartan2_ss_dump (desc, buf, bsize); + break; + + case slave_parallel: + PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); + ret_val = Spartan2_sp_dump (desc, buf, bsize); + break; + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int Spartan2_info( Xilinx_desc *desc ) +{ + return FPGA_SUCCESS; +} + + +int Spartan2_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (desc->family != Xilinx_Spartan2) { + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + return FPGA_FAIL; + } else + switch (desc->iface) { + case slave_serial: + ret_val = Spartan2_ss_reloc (desc, reloc_offset); + break; + + case slave_parallel: + ret_val = Spartan2_sp_reloc (desc, reloc_offset); + break; + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + + +/* ------------------------------------------------------------------------- */ +/* Spartan-II Slave Parallel Generic Implementation */ + +static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + + PRINTF ("%s: start with interface functions @ 0x%p\n", + __FUNCTION__, fn); + + if (fn) { + size_t bytecount = 0; + unsigned char *data = (unsigned char *) buf; + int cookie = desc->cookie; /* make a local copy */ + unsigned long ts; /* timestamp */ + + PRINTF ("%s: Function Table:\n" + "ptr:\t0x%p\n" + "struct: 0x%p\n" + "pre: 0x%p\n" + "pgm:\t0x%p\n" + "init:\t0x%p\n" + "err:\t0x%p\n" + "clk:\t0x%p\n" + "cs:\t0x%p\n" + "wr:\t0x%p\n" + "read data:\t0x%p\n" + "write data:\t0x%p\n" + "busy:\t0x%p\n" + "abort:\t0x%p\n", + "post:\t0x%p\n\n", + __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err, + fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy, + fn->abort, fn->post); + + /* + * This code is designed to emulate the "Express Style" + * Continuous Data Loading in Slave Parallel Mode for + * the Spartan-II Family. + */ +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("Loading FPGA Device %d...\n", cookie); +#endif + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) { + (*fn->pre) (cookie); + } + + /* Establish the initial state */ + (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + + /* Get ready for the burn */ + CONFIG_FPGA_DELAY (); + (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + + ts = get_timer (0); /* get current time */ + /* Now wait for INIT and BUSY to go high */ + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for INIT to clear.\n"); + (*fn->abort) (cookie); /* abort the burn */ + return FPGA_FAIL; + } + } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); + + (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */ + (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + /* Load the data */ + while (bytecount < bsize) { + /* XXX - do we check for an Ctrl-C press in here ??? */ + /* XXX - Check the error bit? */ + + (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + +#ifdef CFG_FPGA_CHECK_BUSY + ts = get_timer (0); /* get current time */ + while ((*fn->busy) (cookie)) { + /* XXX - we should have a check in here somewhere to + * make sure we aren't busy forever... */ + + CONFIG_FPGA_DELAY (); + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for BUSY to clear.\n"); + (*fn->abort) (cookie); /* abort the burn */ + return FPGA_FAIL; + } + } +#endif + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ +#endif + } + + CONFIG_FPGA_DELAY (); + (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */ + (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */ + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc ('\n'); /* terminate the dotted line */ +#endif + + /* now check for done signal */ + ts = get_timer (0); /* get current time */ + ret_val = FPGA_SUCCESS; + while ((*fn->done) (cookie) == FPGA_FAIL) { + /* XXX - we should have a check in here somewhere to + * make sure we aren't busy forever... */ + + CONFIG_FPGA_DELAY (); + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for DONE to clear.\n"); + (*fn->abort) (cookie); /* abort the burn */ + ret_val = FPGA_FAIL; + break; + } + } + + if (ret_val == FPGA_SUCCESS) { +#ifdef CFG_FPGA_PROG_FEEDBACK + puts ("Done.\n"); +#endif + } + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) { + (*fn->post) (cookie); + } + + else { +#ifdef CFG_FPGA_PROG_FEEDBACK + puts ("Fail.\n"); +#endif + } + + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + +static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + + if (fn) { + unsigned char *data = (unsigned char *) buf; + size_t bytecount = 0; + int cookie = desc->cookie; /* make a local copy */ + + printf ("Starting Dump of FPGA Device %d...\n", cookie); + + (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + /* dump the data */ + while (bytecount < bsize) { + /* XXX - do we check for an Ctrl-C press in here ??? */ + + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */ +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ +#endif + } + + (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */ + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc ('\n'); /* terminate the dotted line */ +#endif + puts ("Done.\n"); + + /* XXX - checksum the data? */ + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + + +static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan2_Slave_Parallel_fns *fn_r, *fn = + (Xilinx_Spartan2_Slave_Parallel_fns *) (desc->iface_fns); + + if (fn) { + ulong addr; + + /* Get the relocated table address */ + addr = (ulong) fn + reloc_offset; + fn_r = (Xilinx_Spartan2_Slave_Parallel_fns *) addr; + + if (!fn_r->relocated) { + + if (memcmp (fn_r, fn, + sizeof (Xilinx_Spartan2_Slave_Parallel_fns)) + == 0) { + /* good copy of the table, fix the descriptor pointer */ + desc->iface_fns = fn_r; + } else { + PRINTF ("%s: Invalid function table at 0x%p\n", + __FUNCTION__, fn_r); + return FPGA_FAIL; + } + + PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, + desc); + + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + + addr = (ulong) (fn->pgm) + reloc_offset; + fn_r->pgm = (Xilinx_pgm_fn) addr; + + addr = (ulong) (fn->init) + reloc_offset; + fn_r->init = (Xilinx_init_fn) addr; + + addr = (ulong) (fn->done) + reloc_offset; + fn_r->done = (Xilinx_done_fn) addr; + + addr = (ulong) (fn->clk) + reloc_offset; + fn_r->clk = (Xilinx_clk_fn) addr; + + addr = (ulong) (fn->err) + reloc_offset; + fn_r->err = (Xilinx_err_fn) addr; + + addr = (ulong) (fn->cs) + reloc_offset; + fn_r->cs = (Xilinx_cs_fn) addr; + + addr = (ulong) (fn->wr) + reloc_offset; + fn_r->wr = (Xilinx_wr_fn) addr; + + addr = (ulong) (fn->rdata) + reloc_offset; + fn_r->rdata = (Xilinx_rdata_fn) addr; + + addr = (ulong) (fn->wdata) + reloc_offset; + fn_r->wdata = (Xilinx_wdata_fn) addr; + + addr = (ulong) (fn->busy) + reloc_offset; + fn_r->busy = (Xilinx_busy_fn) addr; + + addr = (ulong) (fn->abort) + reloc_offset; + fn_r->abort = (Xilinx_abort_fn) addr; + + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Xilinx_post_fn) addr; + + fn_r->relocated = TRUE; + + } else { + /* this table has already been moved */ + /* XXX - should check to see if the descriptor is correct */ + desc->iface_fns = fn_r; + } + + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; + +} + +/* ------------------------------------------------------------------------- */ + +static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; + int i; + char val; + + PRINTF ("%s: start with interface functions @ 0x%p\n", + __FUNCTION__, fn); + + if (fn) { + size_t bytecount = 0; + unsigned char *data = (unsigned char *) buf; + int cookie = desc->cookie; /* make a local copy */ + unsigned long ts; /* timestamp */ + + PRINTF ("%s: Function Table:\n" + "ptr:\t0x%p\n" + "struct: 0x%p\n" + "pgm:\t0x%p\n" + "init:\t0x%p\n" + "clk:\t0x%p\n" + "wr:\t0x%p\n" + "done:\t0x%p\n\n", + __FUNCTION__, &fn, fn, fn->pgm, fn->init, + fn->clk, fn->wr, fn->done); +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("Loading FPGA Device %d...\n", cookie); +#endif + + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) { + (*fn->pre) (cookie); + } + + /* Establish the initial state */ + (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + + /* Wait for INIT state (init low) */ + ts = get_timer (0); /* get current time */ + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for INIT to start.\n"); + return FPGA_FAIL; + } + } while (!(*fn->init) (cookie)); + + /* Get ready for the burn */ + CONFIG_FPGA_DELAY (); + (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + + ts = get_timer (0); /* get current time */ + /* Now wait for INIT to go high */ + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for INIT to clear.\n"); + return FPGA_FAIL; + } + } while ((*fn->init) (cookie)); + + /* Load the data */ + while (bytecount < bsize) { + + /* Xilinx detects an error if INIT goes low (active) + while DONE is low (inactive) */ + if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { + puts ("** CRC error during FPGA load.\n"); + return (FPGA_FAIL); + } + val = data [bytecount ++]; + i = 8; + do { + /* Deassert the clock */ + (*fn->clk) (FALSE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Write data */ + (*fn->wr) ((val < 0), TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Assert the clock */ + (*fn->clk) (TRUE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + val <<= 1; + i --; + } while (i > 0); + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ +#endif + } + + CONFIG_FPGA_DELAY (); + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc ('\n'); /* terminate the dotted line */ +#endif + + /* now check for done signal */ + ts = get_timer (0); /* get current time */ + ret_val = FPGA_SUCCESS; + (*fn->wr) (TRUE, TRUE, cookie); + + while (! (*fn->done) (cookie)) { + /* XXX - we should have a check in here somewhere to + * make sure we aren't busy forever... */ + + CONFIG_FPGA_DELAY (); + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + putc ('*'); + + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for DONE to clear.\n"); + ret_val = FPGA_FAIL; + break; + } + } + putc ('\n'); /* terminate the dotted line */ + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (ret_val == FPGA_SUCCESS) { + puts ("Done.\n"); + } + else { + puts ("Fail.\n"); + } +#endif + + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + +static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + /* Readback is only available through the Slave Parallel and */ + /* boundary-scan interfaces. */ + printf ("%s: Slave Serial Dumping is unavailable\n", + __FUNCTION__); + return FPGA_FAIL; +} + +static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan2_Slave_Serial_fns *fn_r, *fn = + (Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns); + + if (fn) { + ulong addr; + + /* Get the relocated table address */ + addr = (ulong) fn + reloc_offset; + fn_r = (Xilinx_Spartan2_Slave_Serial_fns *) addr; + + if (!fn_r->relocated) { + + if (memcmp (fn_r, fn, + sizeof (Xilinx_Spartan2_Slave_Serial_fns)) + == 0) { + /* good copy of the table, fix the descriptor pointer */ + desc->iface_fns = fn_r; + } else { + PRINTF ("%s: Invalid function table at 0x%p\n", + __FUNCTION__, fn_r); + return FPGA_FAIL; + } + + PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, + desc); + + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + + addr = (ulong) (fn->pgm) + reloc_offset; + fn_r->pgm = (Xilinx_pgm_fn) addr; + + addr = (ulong) (fn->init) + reloc_offset; + fn_r->init = (Xilinx_init_fn) addr; + + addr = (ulong) (fn->done) + reloc_offset; + fn_r->done = (Xilinx_done_fn) addr; + + addr = (ulong) (fn->clk) + reloc_offset; + fn_r->clk = (Xilinx_clk_fn) addr; + + addr = (ulong) (fn->wr) + reloc_offset; + fn_r->wr = (Xilinx_wr_fn) addr; + + fn_r->relocated = TRUE; + + } else { + /* this table has already been moved */ + /* XXX - should check to see if the descriptor is correct */ + desc->iface_fns = fn_r; + } + + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; + +} + +#endif diff --git a/common/spartan3.c b/common/spartan3.c new file mode 100644 index 0000000..c0f2b05 --- /dev/null +++ b/common/spartan3.c @@ -0,0 +1,658 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Configuration support for Xilinx Spartan3 devices. Based + * on spartan2.c (Rich Ireland, rireland@enterasys.com). + */ + +#include /* core U-Boot definitions */ +#include /* Spartan-II device family */ + +#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3)) + +/* Define FPGA_DEBUG to get debug printf's */ +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#undef CFG_FPGA_CHECK_BUSY +#undef CFG_FPGA_PROG_FEEDBACK + +/* Note: The assumption is that we cannot possibly run fast enough to + * overrun the device (the Slave Parallel mode can free run at 50MHz). + * If there is a need to operate slower, define CONFIG_FPGA_DELAY in + * the board config file to slow things down. + */ +#ifndef CONFIG_FPGA_DELAY +#define CONFIG_FPGA_DELAY() +#endif + +#ifndef CFG_FPGA_WAIT +#define CFG_FPGA_WAIT CFG_HZ/100 /* 10 ms */ +#endif + +static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); +static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); +/* static int Spartan3_sp_info( Xilinx_desc *desc ); */ +static int Spartan3_sp_reloc( Xilinx_desc *desc, ulong reloc_offset ); + +static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); +static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); +/* static int Spartan3_ss_info( Xilinx_desc *desc ); */ +static int Spartan3_ss_reloc( Xilinx_desc *desc, ulong reloc_offset ); + +/* ------------------------------------------------------------------------- */ +/* Spartan-II Generic Implementation */ +int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case slave_serial: + PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); + ret_val = Spartan3_ss_load (desc, buf, bsize); + break; + + case slave_parallel: + PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); + ret_val = Spartan3_sp_load (desc, buf, bsize); + break; + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case slave_serial: + PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); + ret_val = Spartan3_ss_dump (desc, buf, bsize); + break; + + case slave_parallel: + PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); + ret_val = Spartan3_sp_dump (desc, buf, bsize); + break; + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int Spartan3_info( Xilinx_desc *desc ) +{ + return FPGA_SUCCESS; +} + + +int Spartan3_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (desc->family != Xilinx_Spartan3) { + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + return FPGA_FAIL; + } else + switch (desc->iface) { + case slave_serial: + ret_val = Spartan3_ss_reloc (desc, reloc_offset); + break; + + case slave_parallel: + ret_val = Spartan3_sp_reloc (desc, reloc_offset); + break; + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + + +/* ------------------------------------------------------------------------- */ +/* Spartan-II Slave Parallel Generic Implementation */ + +static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + + PRINTF ("%s: start with interface functions @ 0x%p\n", + __FUNCTION__, fn); + + if (fn) { + size_t bytecount = 0; + unsigned char *data = (unsigned char *) buf; + int cookie = desc->cookie; /* make a local copy */ + unsigned long ts; /* timestamp */ + + PRINTF ("%s: Function Table:\n" + "ptr:\t0x%p\n" + "struct: 0x%p\n" + "pre: 0x%p\n" + "pgm:\t0x%p\n" + "init:\t0x%p\n" + "err:\t0x%p\n" + "clk:\t0x%p\n" + "cs:\t0x%p\n" + "wr:\t0x%p\n" + "read data:\t0x%p\n" + "write data:\t0x%p\n" + "busy:\t0x%p\n" + "abort:\t0x%p\n", + "post:\t0x%p\n\n", + __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err, + fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy, + fn->abort, fn->post); + + /* + * This code is designed to emulate the "Express Style" + * Continuous Data Loading in Slave Parallel Mode for + * the Spartan-II Family. + */ +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("Loading FPGA Device %d...\n", cookie); +#endif + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) { + (*fn->pre) (cookie); + } + + /* Establish the initial state */ + (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + + /* Get ready for the burn */ + CONFIG_FPGA_DELAY (); + (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + + ts = get_timer (0); /* get current time */ + /* Now wait for INIT and BUSY to go high */ + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for INIT to clear.\n"); + (*fn->abort) (cookie); /* abort the burn */ + return FPGA_FAIL; + } + } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); + + (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */ + (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + /* Load the data */ + while (bytecount < bsize) { + /* XXX - do we check for an Ctrl-C press in here ??? */ + /* XXX - Check the error bit? */ + + (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + +#ifdef CFG_FPGA_CHECK_BUSY + ts = get_timer (0); /* get current time */ + while ((*fn->busy) (cookie)) { + /* XXX - we should have a check in here somewhere to + * make sure we aren't busy forever... */ + + CONFIG_FPGA_DELAY (); + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for BUSY to clear.\n"); + (*fn->abort) (cookie); /* abort the burn */ + return FPGA_FAIL; + } + } +#endif + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ +#endif + } + + CONFIG_FPGA_DELAY (); + (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */ + (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */ + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc ('\n'); /* terminate the dotted line */ +#endif + + /* now check for done signal */ + ts = get_timer (0); /* get current time */ + ret_val = FPGA_SUCCESS; + while ((*fn->done) (cookie) == FPGA_FAIL) { + /* XXX - we should have a check in here somewhere to + * make sure we aren't busy forever... */ + + CONFIG_FPGA_DELAY (); + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for DONE to clear.\n"); + (*fn->abort) (cookie); /* abort the burn */ + ret_val = FPGA_FAIL; + break; + } + } + + if (ret_val == FPGA_SUCCESS) { +#ifdef CFG_FPGA_PROG_FEEDBACK + puts ("Done.\n"); +#endif + } + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) { + (*fn->post) (cookie); + } + + else { +#ifdef CFG_FPGA_PROG_FEEDBACK + puts ("Fail.\n"); +#endif + } + + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + +static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + + if (fn) { + unsigned char *data = (unsigned char *) buf; + size_t bytecount = 0; + int cookie = desc->cookie; /* make a local copy */ + + printf ("Starting Dump of FPGA Device %d...\n", cookie); + + (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + /* dump the data */ + while (bytecount < bsize) { + /* XXX - do we check for an Ctrl-C press in here ??? */ + + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */ +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ +#endif + } + + (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */ + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc ('\n'); /* terminate the dotted line */ +#endif + puts ("Done.\n"); + + /* XXX - checksum the data? */ + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + + +static int Spartan3_sp_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan3_Slave_Parallel_fns *fn_r, *fn = + (Xilinx_Spartan3_Slave_Parallel_fns *) (desc->iface_fns); + + if (fn) { + ulong addr; + + /* Get the relocated table address */ + addr = (ulong) fn + reloc_offset; + fn_r = (Xilinx_Spartan3_Slave_Parallel_fns *) addr; + + if (!fn_r->relocated) { + + if (memcmp (fn_r, fn, + sizeof (Xilinx_Spartan3_Slave_Parallel_fns)) + == 0) { + /* good copy of the table, fix the descriptor pointer */ + desc->iface_fns = fn_r; + } else { + PRINTF ("%s: Invalid function table at 0x%p\n", + __FUNCTION__, fn_r); + return FPGA_FAIL; + } + + PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, + desc); + + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + + addr = (ulong) (fn->pgm) + reloc_offset; + fn_r->pgm = (Xilinx_pgm_fn) addr; + + addr = (ulong) (fn->init) + reloc_offset; + fn_r->init = (Xilinx_init_fn) addr; + + addr = (ulong) (fn->done) + reloc_offset; + fn_r->done = (Xilinx_done_fn) addr; + + addr = (ulong) (fn->clk) + reloc_offset; + fn_r->clk = (Xilinx_clk_fn) addr; + + addr = (ulong) (fn->err) + reloc_offset; + fn_r->err = (Xilinx_err_fn) addr; + + addr = (ulong) (fn->cs) + reloc_offset; + fn_r->cs = (Xilinx_cs_fn) addr; + + addr = (ulong) (fn->wr) + reloc_offset; + fn_r->wr = (Xilinx_wr_fn) addr; + + addr = (ulong) (fn->rdata) + reloc_offset; + fn_r->rdata = (Xilinx_rdata_fn) addr; + + addr = (ulong) (fn->wdata) + reloc_offset; + fn_r->wdata = (Xilinx_wdata_fn) addr; + + addr = (ulong) (fn->busy) + reloc_offset; + fn_r->busy = (Xilinx_busy_fn) addr; + + addr = (ulong) (fn->abort) + reloc_offset; + fn_r->abort = (Xilinx_abort_fn) addr; + + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Xilinx_post_fn) addr; + + fn_r->relocated = TRUE; + + } else { + /* this table has already been moved */ + /* XXX - should check to see if the descriptor is correct */ + desc->iface_fns = fn_r; + } + + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; + +} + +/* ------------------------------------------------------------------------- */ + +static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; + int i; + char val; + + PRINTF ("%s: start with interface functions @ 0x%p\n", + __FUNCTION__, fn); + + if (fn) { + size_t bytecount = 0; + unsigned char *data = (unsigned char *) buf; + int cookie = desc->cookie; /* make a local copy */ + unsigned long ts; /* timestamp */ + + PRINTF ("%s: Function Table:\n" + "ptr:\t0x%p\n" + "struct: 0x%p\n" + "pgm:\t0x%p\n" + "init:\t0x%p\n" + "clk:\t0x%p\n" + "wr:\t0x%p\n" + "done:\t0x%p\n\n", + __FUNCTION__, &fn, fn, fn->pgm, fn->init, + fn->clk, fn->wr, fn->done); +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("Loading FPGA Device %d...\n", cookie); +#endif + + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) { + (*fn->pre) (cookie); + } + + /* Establish the initial state */ + (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + + /* Wait for INIT state (init low) */ + ts = get_timer (0); /* get current time */ + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for INIT to start.\n"); + return FPGA_FAIL; + } + } while (!(*fn->init) (cookie)); + + /* Get ready for the burn */ + CONFIG_FPGA_DELAY (); + (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + + ts = get_timer (0); /* get current time */ + /* Now wait for INIT to go high */ + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for INIT to clear.\n"); + return FPGA_FAIL; + } + } while ((*fn->init) (cookie)); + + /* Load the data */ + while (bytecount < bsize) { + + /* Xilinx detects an error if INIT goes low (active) + while DONE is low (inactive) */ + if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { + puts ("** CRC error during FPGA load.\n"); + return (FPGA_FAIL); + } + val = data [bytecount ++]; + i = 8; + do { + /* Deassert the clock */ + (*fn->clk) (FALSE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Write data */ + (*fn->wr) ((val < 0), TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Assert the clock */ + (*fn->clk) (TRUE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + val <<= 1; + i --; + } while (i > 0); + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ +#endif + } + + CONFIG_FPGA_DELAY (); + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc ('\n'); /* terminate the dotted line */ +#endif + + /* now check for done signal */ + ts = get_timer (0); /* get current time */ + ret_val = FPGA_SUCCESS; + (*fn->wr) (TRUE, TRUE, cookie); + + while (! (*fn->done) (cookie)) { + /* XXX - we should have a check in here somewhere to + * make sure we aren't busy forever... */ + + CONFIG_FPGA_DELAY (); + (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + + putc ('*'); + + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for DONE to clear.\n"); + ret_val = FPGA_FAIL; + break; + } + } + putc ('\n'); /* terminate the dotted line */ + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (ret_val == FPGA_SUCCESS) { + puts ("Done.\n"); + } + else { + puts ("Fail.\n"); + } +#endif + + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + +static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + /* Readback is only available through the Slave Parallel and */ + /* boundary-scan interfaces. */ + printf ("%s: Slave Serial Dumping is unavailable\n", + __FUNCTION__); + return FPGA_FAIL; +} + +static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Xilinx_Spartan3_Slave_Serial_fns *fn_r, *fn = + (Xilinx_Spartan3_Slave_Serial_fns *) (desc->iface_fns); + + if (fn) { + ulong addr; + + /* Get the relocated table address */ + addr = (ulong) fn + reloc_offset; + fn_r = (Xilinx_Spartan3_Slave_Serial_fns *) addr; + + if (!fn_r->relocated) { + + if (memcmp (fn_r, fn, + sizeof (Xilinx_Spartan3_Slave_Serial_fns)) + == 0) { + /* good copy of the table, fix the descriptor pointer */ + desc->iface_fns = fn_r; + } else { + PRINTF ("%s: Invalid function table at 0x%p\n", + __FUNCTION__, fn_r); + return FPGA_FAIL; + } + + PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, + desc); + + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + + addr = (ulong) (fn->pgm) + reloc_offset; + fn_r->pgm = (Xilinx_pgm_fn) addr; + + addr = (ulong) (fn->init) + reloc_offset; + fn_r->init = (Xilinx_init_fn) addr; + + addr = (ulong) (fn->done) + reloc_offset; + fn_r->done = (Xilinx_done_fn) addr; + + addr = (ulong) (fn->clk) + reloc_offset; + fn_r->clk = (Xilinx_clk_fn) addr; + + addr = (ulong) (fn->wr) + reloc_offset; + fn_r->wr = (Xilinx_wr_fn) addr; + + fn_r->relocated = TRUE; + + } else { + /* this table has already been moved */ + /* XXX - should check to see if the descriptor is correct */ + desc->iface_fns = fn_r; + } + + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; + +} + +#endif diff --git a/common/usb.c b/common/usb.c new file mode 100644 index 0000000..d9515e6 --- /dev/null +++ b/common/usb.c @@ -0,0 +1,1227 @@ +/* + * + * Most of this source has been derived from the Linux USB + * project: + * (C) Copyright Linus Torvalds 1999 + * (C) Copyright Johannes Erdfelt 1999-2001 + * (C) Copyright Andreas Gal 1999 + * (C) Copyright Gregory P. Smith 1999 + * (C) Copyright Deti Fliegl 1999 (new USB architecture) + * (C) Copyright Randy Dunlap 2000 + * (C) Copyright David Brownell 2000 (kernel hotplug, usb_device_id) + * (C) Copyright Yggdrasil Computing, Inc. 2000 + * (usb_device_id matching changes by Adam J. Richter) + * + * Adapted for U-Boot: + * (C) Copyright 2001 Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * How it works: + * + * Since this is a bootloader, the devices will not be automatic + * (re)configured on hotplug, but after a restart of the USB the + * device should work. + * + * For each transfer (except "Interrupt") we wait for completion. + */ +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_USB) + +#include +#ifdef CONFIG_4xx +#include <405gp_pci.h> +#endif + +#undef USB_DEBUG + +#ifdef USB_DEBUG +#define USB_PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define USB_PRINTF(fmt,args...) +#endif + +#define USB_BUFSIZ 512 + +static struct usb_device usb_dev[USB_MAX_DEVICE]; +static int dev_index; +static int running; +static int asynch_allowed; +static struct devrequest setup_packet; + +/********************************************************************** + * some forward declerations... + */ +void usb_scan_devices(void); + +int usb_hub_probe(struct usb_device *dev, int ifnum); +void usb_hub_reset(void); + + +/*********************************************************************** + * wait_ms + */ + +void __inline__ wait_ms(unsigned long ms) +{ + while(ms-->0) + udelay(1000); +} +/*************************************************************************** + * Init USB Device + */ + +int usb_init(void) +{ + int result; + + running=0; + dev_index=0; + asynch_allowed=1; + usb_hub_reset(); + /* init low_level USB */ + printf("USB: "); + result = usb_lowlevel_init(); + /* if lowlevel init is OK, scan the bus for devices i.e. search HUBs and configure them */ + if(result==0) { + printf("scanning bus for devices... "); + running=1; + usb_scan_devices(); + return 0; + } + else { + printf("Error, couldn't init Lowlevel part\n"); + return -1; + } +} + +/****************************************************************************** + * Stop USB this stops the LowLevel Part and deregisters USB devices. + */ +int usb_stop(void) +{ + asynch_allowed=1; + usb_hub_reset(); + return usb_lowlevel_stop(); +} + +/* + * disables the asynch behaviour of the control message. This is used for data + * transfers that uses the exclusiv access to the control and bulk messages. + */ +void usb_disable_asynch(int disable) +{ + asynch_allowed=!disable; +} + + +/*------------------------------------------------------------------- + * Message wrappers. + * + */ + +/* + * submits an Interrupt Message + */ +int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe, + void *buffer,int transfer_len, int interval) +{ + return submit_int_msg(dev,pipe,buffer,transfer_len,interval); +} + +/* + * submits a control message and waits for comletion (at least timeout * 1ms) + * If timeout is 0, we don't wait for completion (used as example to set and + * clear keyboards LEDs). For data transfers, (storage transfers) we don't + * allow control messages with 0 timeout, by previousely resetting the flag + * asynch_allowed (usb_disable_asynch(1)). + * returns the transfered length if OK or -1 if error. The transfered length + * and the current status are stored in the dev->act_len and dev->status. + */ +int usb_control_msg(struct usb_device *dev, unsigned int pipe, + unsigned char request, unsigned char requesttype, + unsigned short value, unsigned short index, + void *data, unsigned short size, int timeout) +{ + if((timeout==0)&&(!asynch_allowed)) /* request for a asynch control pipe is not allowed */ + return -1; + + /* set setup command */ + setup_packet.requesttype = requesttype; + setup_packet.request = request; + setup_packet.value = swap_16(value); + setup_packet.index = swap_16(index); + setup_packet.length = swap_16(size); + USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X\nvalue 0x%X index 0x%X length 0x%X\n", + request,requesttype,value,index,size); + dev->status=USB_ST_NOT_PROC; /*not yet processed */ + + submit_control_msg(dev,pipe,data,size,&setup_packet); + if(timeout==0) { + return (int)size; + } + while(timeout--) { + if(!((volatile unsigned long)dev->status & USB_ST_NOT_PROC)) + break; + wait_ms(1); + } + if(dev->status==0) + return dev->act_len; + else { + return -1; + } +} + +/*------------------------------------------------------------------- + * submits bulk message, and waits for completion. returns 0 if Ok or + * -1 if Error. + * synchronous behavior + */ +int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, + void *data, int len, int *actual_length, int timeout) +{ + if (len < 0) + return -1; + dev->status=USB_ST_NOT_PROC; /*not yet processed */ + submit_bulk_msg(dev,pipe,data,len); + while(timeout--) { + if(!((volatile unsigned long)dev->status & USB_ST_NOT_PROC)) + break; + wait_ms(1); + } + *actual_length=dev->act_len; + if(dev->status==0) + return 0; + else + return -1; +} + + +/*------------------------------------------------------------------- + * Max Packet stuff + */ + +/* + * returns the max packet size, depending on the pipe direction and + * the configurations values + */ +int usb_maxpacket(struct usb_device *dev,unsigned long pipe) +{ + if((pipe & USB_DIR_IN)==0) /* direction is out -> use emaxpacket out */ + return(dev->epmaxpacketout[((pipe>>15) & 0xf)]); + else + return(dev->epmaxpacketin[((pipe>>15) & 0xf)]); +} + +/* + * set the max packed value of all endpoints in the given configuration + */ +int usb_set_maxpacket(struct usb_device *dev) +{ + int i,ii,b; + struct usb_endpoint_descriptor *ep; + + for(i=0; iconfig.bNumInterfaces;i++) { + for(ii=0; iiconfig.if_desc[i].bNumEndpoints; ii++) { + ep=&dev->config.if_desc[i].ep_desc[ii]; + b=ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + + if((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)==USB_ENDPOINT_XFER_CONTROL) { /* Control => bidirectional */ + dev->epmaxpacketout[b] = ep->wMaxPacketSize; + dev->epmaxpacketin [b] = ep->wMaxPacketSize; + USB_PRINTF("##Control EP epmaxpacketout/in[%d] = %d\n",b,dev->epmaxpacketin[b]); + } + else { + if ((ep->bEndpointAddress & 0x80)==0) { /* OUT Endpoint */ + if(ep->wMaxPacketSize > dev->epmaxpacketout[b]) { + dev->epmaxpacketout[b] = ep->wMaxPacketSize; + USB_PRINTF("##EP epmaxpacketout[%d] = %d\n",b,dev->epmaxpacketout[b]); + } + } + else { /* IN Endpoint */ + if(ep->wMaxPacketSize > dev->epmaxpacketin[b]) { + dev->epmaxpacketin[b] = ep->wMaxPacketSize; + USB_PRINTF("##EP epmaxpacketin[%d] = %d\n",b,dev->epmaxpacketin[b]); + } + } /* if out */ + } /* if control */ + } /* for each endpoint */ + } + return 0; +} + +/******************************************************************************* + * Parse the config, located in buffer, and fills the dev->config structure. + * Note that all little/big endian swapping are done automatically. + */ +int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) +{ + struct usb_descriptor_header *head; + int index,ifno,epno; + ifno=-1; + epno=-1; + + dev->configno=cfgno; + head =(struct usb_descriptor_header *)&buffer[0]; + if(head->bDescriptorType!=USB_DT_CONFIG) { + printf(" ERROR: NOT USB_CONFIG_DESC %x\n",head->bDescriptorType); + return -1; + } + memcpy(&dev->config,buffer,buffer[0]); + dev->config.wTotalLength=swap_16(dev->config.wTotalLength); + dev->config.no_of_if=0; + + index=dev->config.bLength; + /* Ok the first entry must be a configuration entry, now process the others */ + head=(struct usb_descriptor_header *)&buffer[index]; + while(index+1 < dev->config.wTotalLength) { + switch(head->bDescriptorType) { + case USB_DT_INTERFACE: + ifno=dev->config.no_of_if; + dev->config.no_of_if++; /* found an interface desc, increase numbers */ + memcpy(&dev->config.if_desc[ifno],&buffer[index],buffer[index]); /* copy new desc */ + dev->config.if_desc[ifno].no_of_ep=0; + + break; + case USB_DT_ENDPOINT: + epno=dev->config.if_desc[ifno].no_of_ep; + dev->config.if_desc[ifno].no_of_ep++; /* found an endpoint */ + memcpy(&dev->config.if_desc[ifno].ep_desc[epno],&buffer[index],buffer[index]); + dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize + =swap_16(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize); + USB_PRINTF("if %d, ep %d\n",ifno,epno); + break; + default: + if(head->bLength==0) + return 1; + USB_PRINTF("unknown Description Type : %x\n",head->bDescriptorType); + { + int i; + unsigned char *ch; + ch=(unsigned char *)head; + for(i=0;ibLength; i++) + USB_PRINTF("%02X ",*ch++); + USB_PRINTF("\n\n\n"); + } + break; + } + index+=head->bLength; + head=(struct usb_descriptor_header *)&buffer[index]; + } + return 1; +} + +/*********************************************************************** + * Clears an endpoint + * endp: endpoint number in bits 0-3; + * direction flag in bit 7 (1 = IN, 0 = OUT) + */ +int usb_clear_halt(struct usb_device *dev, int pipe) +{ + int result; + int endp = usb_pipeendpoint(pipe)|(usb_pipein(pipe)<<7); + + result = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, endp, NULL, 0, USB_CNTL_TIMEOUT * 3); + + /* don't clear if failed */ + if (result < 0) + return result; + + /* + * NOTE: we do not get status and verify reset was successful + * as some devices are reported to lock up upon this check.. + */ + + usb_endpoint_running(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + + /* toggle is reset on clear */ + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 0); + return 0; +} + + +/********************************************************************** + * get_descriptor type + */ +int usb_get_descriptor(struct usb_device *dev, unsigned char type, unsigned char index, void *buf, int size) +{ + int res; + res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, + (type << 8) + index, 0, + buf, size, USB_CNTL_TIMEOUT); + return res; +} + +/********************************************************************** + * gets configuration cfgno and store it in the buffer + */ +int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cfgno) +{ + int result; + unsigned int tmp; + struct usb_config_descriptor *config; + + + config=(struct usb_config_descriptor *)&buffer[0]; + result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 8); + if (result < 8) { + if (result < 0) + printf("unable to get descriptor, error %lX\n",dev->status); + else + printf("config descriptor too short (expected %i, got %i)\n",8,result); + return -1; + } + tmp=swap_16(config->wTotalLength); + + if (tmp > USB_BUFSIZ) { + USB_PRINTF("usb_get_configuration_no: failed to get descriptor - too long: %d\n", + tmp); + return -1; + } + + result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, tmp); + USB_PRINTF("get_conf_no %d Result %d, wLength %d\n",cfgno,result,tmp); + return result; +} + +/******************************************************************** + * set address of a device to the value in dev->devnum. + * This can only be done by addressing the device via the default address (0) + */ +int usb_set_address(struct usb_device *dev) +{ + int res; + + USB_PRINTF("set address %d\n",dev->devnum); + res=usb_control_msg(dev, usb_snddefctrl(dev), + USB_REQ_SET_ADDRESS, 0, + (dev->devnum),0, + NULL,0, USB_CNTL_TIMEOUT); + return res; +} + +/******************************************************************** + * set interface number to interface + */ +int usb_set_interface(struct usb_device *dev, int interface, int alternate) +{ + struct usb_interface_descriptor *if_face = NULL; + int ret, i; + + for (i = 0; i < dev->config.bNumInterfaces; i++) { + if (dev->config.if_desc[i].bInterfaceNumber == interface) { + if_face = &dev->config.if_desc[i]; + break; + } + } + if (!if_face) { + printf("selecting invalid interface %d", interface); + return -1; + } + + if ((ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_INTERFACE, USB_RECIP_INTERFACE, alternate, + interface, NULL, 0, USB_CNTL_TIMEOUT * 5)) < 0) + return ret; + + return 0; +} + +/******************************************************************** + * set configuration number to configuration + */ +int usb_set_configuration(struct usb_device *dev, int configuration) +{ + int res; + USB_PRINTF("set configuration %d\n",configuration); + /* set setup command */ + res=usb_control_msg(dev, usb_sndctrlpipe(dev,0), + USB_REQ_SET_CONFIGURATION, 0, + configuration,0, + NULL,0, USB_CNTL_TIMEOUT); + if(res==0) { + dev->toggle[0] = 0; + dev->toggle[1] = 0; + return 0; + } + else + return -1; +} + +/******************************************************************** + * set protocol to protocol + */ +int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_PROTOCOL, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + protocol, ifnum, NULL, 0, USB_CNTL_TIMEOUT); +} + +/******************************************************************** + * set idle + */ +int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id) +{ + return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_IDLE, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + (duration << 8) | report_id, ifnum, NULL, 0, USB_CNTL_TIMEOUT); +} + +/******************************************************************** + * get report + */ +int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, unsigned char id, void *buf, int size) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_REPORT, USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE, + (type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT); +} + +/******************************************************************** + * get class descriptor + */ +int usb_get_class_descriptor(struct usb_device *dev, int ifnum, + unsigned char type, unsigned char id, void *buf, int size) +{ + return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_RECIP_INTERFACE | USB_DIR_IN, + (type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT); +} + +/******************************************************************** + * get string index in buffer + */ +int usb_get_string(struct usb_device *dev, unsigned short langid, unsigned char index, void *buf, int size) +{ + int i; + int result; + + for (i = 0; i < 3; ++i) { + /* some devices are flaky */ + result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, + (USB_DT_STRING << 8) + index, langid, buf, size, + USB_CNTL_TIMEOUT); + + if (result > 0) + break; + } + + return result; +} + + +static void usb_try_string_workarounds(unsigned char *buf, int *length) +{ + int newlength, oldlength = *length; + + for (newlength = 2; newlength + 1 < oldlength; newlength += 2) + if (!isprint(buf[newlength]) || buf[newlength + 1]) + break; + + if (newlength > 2) { + buf[0] = newlength; + *length = newlength; + } +} + + +static int usb_string_sub(struct usb_device *dev, unsigned int langid, + unsigned int index, unsigned char *buf) +{ + int rc; + + /* Try to read the string descriptor by asking for the maximum + * possible number of bytes */ + rc = usb_get_string(dev, langid, index, buf, 255); + + /* If that failed try to read the descriptor length, then + * ask for just that many bytes */ + if (rc < 2) { + rc = usb_get_string(dev, langid, index, buf, 2); + if (rc == 2) + rc = usb_get_string(dev, langid, index, buf, buf[0]); + } + + if (rc >= 2) { + if (!buf[0] && !buf[1]) + usb_try_string_workarounds(buf, &rc); + + /* There might be extra junk at the end of the descriptor */ + if (buf[0] < rc) + rc = buf[0]; + + rc = rc - (rc & 1); /* force a multiple of two */ + } + + if (rc < 2) + rc = -1; + + return rc; +} + + +/******************************************************************** + * usb_string: + * Get string index and translate it to ascii. + * returns string length (> 0) or error (< 0) + */ +int usb_string(struct usb_device *dev, int index, char *buf, size_t size) +{ + unsigned char mybuf[USB_BUFSIZ]; + unsigned char *tbuf; + int err; + unsigned int u, idx; + + if (size <= 0 || !buf || !index) + return -1; + buf[0] = 0; + tbuf=&mybuf[0]; + + /* get langid for strings if it's not yet known */ + if (!dev->have_langid) { + err = usb_string_sub(dev, 0, 0, tbuf); + if (err < 0) { + USB_PRINTF("error getting string descriptor 0 (error=%x)\n",dev->status); + return -1; + } else if (tbuf[0] < 4) { + USB_PRINTF("string descriptor 0 too short\n"); + return -1; + } else { + dev->have_langid = -1; + dev->string_langid = tbuf[2] | (tbuf[3]<< 8); + /* always use the first langid listed */ + USB_PRINTF("USB device number %d default language ID 0x%x\n", + dev->devnum, dev->string_langid); + } + } + + err = usb_string_sub(dev, dev->string_langid, index, tbuf); + if (err < 0) + return err; + + size--; /* leave room for trailing NULL char in output buffer */ + for (idx = 0, u = 2; u < err; u += 2) { + if (idx >= size) + break; + if (tbuf[u+1]) /* high byte */ + buf[idx++] = '?'; /* non-ASCII character */ + else + buf[idx++] = tbuf[u]; + } + buf[idx] = 0; + err = idx; + return err; +} + + +/******************************************************************** + * USB device handling: + * the USB device are static allocated [USB_MAX_DEVICE]. + */ + + +/* returns a pointer to the device with the index [index]. + * if the device is not assigned (dev->devnum==-1) returns NULL + */ +struct usb_device * usb_get_dev_index(int index) +{ + if(usb_dev[index].devnum==-1) + return NULL; + else + return &usb_dev[index]; +} + + +/* returns a pointer of a new device structure or NULL, if + * no device struct is available + */ +struct usb_device * usb_alloc_new_device(void) +{ + int i; + USB_PRINTF("New Device %d\n",dev_index); + if(dev_index==USB_MAX_DEVICE) { + printf("ERROR, too many USB Devices, max=%d\n",USB_MAX_DEVICE); + return NULL; + } + usb_dev[dev_index].devnum=dev_index+1; /* default Address is 0, real addresses start with 1 */ + usb_dev[dev_index].maxchild=0; + for(i=0;idescriptor.bMaxPacketSize0 = 8; /* Start off at 8 bytes */ + dev->maxpacketsize = 0; /* Default to 8 byte max packet size */ + dev->epmaxpacketin [0] = 8; + dev->epmaxpacketout[0] = 8; + + /* We still haven't set the Address yet */ + addr = dev->devnum; + dev->devnum = 0; + +#undef NEW_INIT_SEQ +#ifdef NEW_INIT_SEQ + /* this is a Windows scheme of initialization sequence, with double + * reset of the device. Some equipment is said to work only with such + * init sequence; this patch is based on the work by Alan Stern: + * http://sourceforge.net/mailarchive/forum.php?thread_id=5729457&forum_id=5398 + */ + int j; + struct usb_device_descriptor *desc; + int port = -1; + struct usb_device *parent = dev->parent; + unsigned short portstatus; + + /* send 64-byte GET-DEVICE-DESCRIPTOR request. Since the descriptor is + * only 18 bytes long, this will terminate with a short packet. But if + * the maxpacket size is 8 or 16 the device may be waiting to transmit + * some more. */ + + desc = (struct usb_device_descriptor *)tmpbuf; + desc->bMaxPacketSize0 = 0; + for (j = 0; j < 3; ++j) { + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64); + if (err < 0) { + USB_PRINTF("usb_new_device: 64 byte descr\n"); + break; + } + } + dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0; + + /* find the port number we're at */ + if (parent) { + + for (j = 0; j < parent->maxchild; j++) { + if (parent->children[j] == dev) { + port = j; + break; + } + } + if (port < 0) { + printf("usb_new_device: cannot locate device's port..\n"); + return 1; + } + + /* reset the port for the second time */ + err = hub_port_reset(dev->parent, port, &portstatus); + if (err < 0) { + printf("\n Couldn't reset port %i\n", port); + return 1; + } + } +#else + /* and this is the old and known way of initializing devices */ + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8); + if (err < 8) { + printf("\n USB device not responding, giving up (status=%lX)\n",dev->status); + return 1; + } +#endif + + dev->epmaxpacketin [0] = dev->descriptor.bMaxPacketSize0; + dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0; + switch (dev->descriptor.bMaxPacketSize0) { + case 8: dev->maxpacketsize = 0; break; + case 16: dev->maxpacketsize = 1; break; + case 32: dev->maxpacketsize = 2; break; + case 64: dev->maxpacketsize = 3; break; + } + dev->devnum = addr; + + err = usb_set_address(dev); /* set address */ + + if (err < 0) { + printf("\n USB device not accepting new address (error=%lX)\n", dev->status); + return 1; + } + + wait_ms(10); /* Let the SET_ADDRESS settle */ + + tmp = sizeof(dev->descriptor); + + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, sizeof(dev->descriptor)); + if (err < tmp) { + if (err < 0) + printf("unable to get device descriptor (error=%d)\n",err); + else + printf("USB device descriptor short read (expected %i, got %i)\n",tmp,err); + return 1; + } + /* correct le values */ + dev->descriptor.bcdUSB=swap_16(dev->descriptor.bcdUSB); + dev->descriptor.idVendor=swap_16(dev->descriptor.idVendor); + dev->descriptor.idProduct=swap_16(dev->descriptor.idProduct); + dev->descriptor.bcdDevice=swap_16(dev->descriptor.bcdDevice); + /* only support for one config for now */ + usb_get_configuration_no(dev,&tmpbuf[0],0); + usb_parse_config(dev,&tmpbuf[0],0); + usb_set_maxpacket(dev); + /* we set the default configuration here */ + if (usb_set_configuration(dev, dev->config.bConfigurationValue)) { + printf("failed to set default configuration len %d, status %lX\n",dev->act_len,dev->status); + return -1; + } + USB_PRINTF("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n", + dev->descriptor.iManufacturer, dev->descriptor.iProduct, dev->descriptor.iSerialNumber); + memset(dev->mf, 0, sizeof(dev->mf)); + memset(dev->prod, 0, sizeof(dev->prod)); + memset(dev->serial, 0, sizeof(dev->serial)); + if (dev->descriptor.iManufacturer) + usb_string(dev, dev->descriptor.iManufacturer, dev->mf, sizeof(dev->mf)); + if (dev->descriptor.iProduct) + usb_string(dev, dev->descriptor.iProduct, dev->prod, sizeof(dev->prod)); + if (dev->descriptor.iSerialNumber) + usb_string(dev, dev->descriptor.iSerialNumber, dev->serial, sizeof(dev->serial)); + USB_PRINTF("Manufacturer %s\n", dev->mf); + USB_PRINTF("Product %s\n", dev->prod); + USB_PRINTF("SerialNumber %s\n", dev->serial); + /* now prode if the device is a hub */ + usb_hub_probe(dev,0); + return 0; +} + +/* build device Tree */ +void usb_scan_devices(void) +{ + int i; + struct usb_device *dev; + + /* first make all devices unknown */ + for(i=0;ipusb_dev; + /* Enable power to the ports */ + USB_HUB_PRINTF("enabling power on all ports\n"); + for (i = 0; i < dev->maxchild; i++) { + usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); + USB_HUB_PRINTF("port %d returns %lX\n",i+1,dev->status); + wait_ms(hub->desc.bPwrOn2PwrGood * 2); + } +} + +void usb_hub_reset(void) +{ + usb_hub_index=0; +} + +struct usb_hub_device *usb_hub_allocate(void) +{ + if(usb_hub_indexstatus); + return -1; + } + portstatus = swap_16(portsts.wPortStatus); + portchange = swap_16(portsts.wPortChange); + USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus ,portchange, + portstatus&(1<children[port])) { + USB_HUB_PRINTF("usb_disconnect(&hub->children[port]);\n"); + /* Return now if nothing is connected */ + if (!(portstatus & USB_PORT_STAT_CONNECTION)) + return; + } + wait_ms(200); + + /* Reset the port */ + if (hub_port_reset(dev, port, &portstatus) < 0) { + printf("cannot reset port %i!?\n", port + 1); + return; + } + + wait_ms(200); + + /* Allocate a new device struct for it */ + usb=usb_alloc_new_device(); + usb->slow = (portstatus & USB_PORT_STAT_LOW_SPEED) ? 1 : 0; + + dev->children[port] = usb; + usb->parent=dev; + /* Run it through the hoops (find a driver, etc) */ + if (usb_new_device(usb)) { + /* Woops, disable the port */ + USB_HUB_PRINTF("hub: disabling port %d\n", port + 1); + usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE); + } +} + + +int usb_hub_configure(struct usb_device *dev) +{ + unsigned char buffer[USB_BUFSIZ], *bitmap; + struct usb_hub_descriptor *descriptor; + struct usb_hub_status *hubsts; + int i; + struct usb_hub_device *hub; + + /* "allocate" Hub device */ + hub=usb_hub_allocate(); + if(hub==NULL) + return -1; + hub->pusb_dev=dev; + /* Get the the hub descriptor */ + if (usb_get_hub_descriptor(dev, buffer, 4) < 0) { + USB_HUB_PRINTF("usb_hub_configure: failed to get hub descriptor, giving up %lX\n",dev->status); + return -1; + } + descriptor = (struct usb_hub_descriptor *)buffer; + + /* silence compiler warning if USB_BUFSIZ is > 256 [= sizeof(char)] */ + i = descriptor->bLength; + if (i > USB_BUFSIZ) { + USB_HUB_PRINTF("usb_hub_configure: failed to get hub descriptor - too long: %d\N", + descriptor->bLength); + return -1; + } + + if (usb_get_hub_descriptor(dev, buffer, descriptor->bLength) < 0) { + USB_HUB_PRINTF("usb_hub_configure: failed to get hub descriptor 2nd giving up %lX\n",dev->status); + return -1; + } + memcpy((unsigned char *)&hub->desc,buffer,descriptor->bLength); + /* adjust 16bit values */ + hub->desc.wHubCharacteristics=swap_16(descriptor->wHubCharacteristics); + /* set the bitmap */ + bitmap=(unsigned char *)&hub->desc.DeviceRemovable[0]; + memset(bitmap,0xff,(USB_MAXCHILDREN+1+7)/8); /* devices not removable by default */ + bitmap=(unsigned char *)&hub->desc.PortPowerCtrlMask[0]; + memset(bitmap,0xff,(USB_MAXCHILDREN+1+7)/8); /* PowerMask = 1B */ + for(i=0;i<((hub->desc.bNbrPorts + 1 + 7)/8);i++) { + hub->desc.DeviceRemovable[i]=descriptor->DeviceRemovable[i]; + } + for(i=0;i<((hub->desc.bNbrPorts + 1 + 7)/8);i++) { + hub->desc.DeviceRemovable[i]=descriptor->PortPowerCtrlMask[i]; + } + dev->maxchild = descriptor->bNbrPorts; + USB_HUB_PRINTF("%d ports detected\n", dev->maxchild); + + switch (hub->desc.wHubCharacteristics & HUB_CHAR_LPSM) { + case 0x00: + USB_HUB_PRINTF("ganged power switching\n"); + break; + case 0x01: + USB_HUB_PRINTF("individual port power switching\n"); + break; + case 0x02: + case 0x03: + USB_HUB_PRINTF("unknown reserved power switching mode\n"); + break; + } + + if (hub->desc.wHubCharacteristics & HUB_CHAR_COMPOUND) + USB_HUB_PRINTF("part of a compound device\n"); + else + USB_HUB_PRINTF("standalone hub\n"); + + switch (hub->desc.wHubCharacteristics & HUB_CHAR_OCPM) { + case 0x00: + USB_HUB_PRINTF("global over-current protection\n"); + break; + case 0x08: + USB_HUB_PRINTF("individual port over-current protection\n"); + break; + case 0x10: + case 0x18: + USB_HUB_PRINTF("no over-current protection\n"); + break; + } + USB_HUB_PRINTF("power on to power good time: %dms\n", descriptor->bPwrOn2PwrGood * 2); + USB_HUB_PRINTF("hub controller current requirement: %dmA\n", descriptor->bHubContrCurrent); + for (i = 0; i < dev->maxchild; i++) + USB_HUB_PRINTF("port %d is%s removable\n", i + 1, + hub->desc.DeviceRemovable[(i + 1)/8] & (1 << ((i + 1)%8)) ? " not" : ""); + if (sizeof(struct usb_hub_status) > USB_BUFSIZ) { + USB_HUB_PRINTF("usb_hub_configure: failed to get Status - too long: %d\n", + descriptor->bLength); + return -1; + } + + if (usb_get_hub_status(dev, buffer) < 0) { + USB_HUB_PRINTF("usb_hub_configure: failed to get Status %lX\n",dev->status); + return -1; + } + hubsts = (struct usb_hub_status *)buffer; + USB_HUB_PRINTF("get_hub_status returned status %X, change %X\n", + swap_16(hubsts->wHubStatus),swap_16(hubsts->wHubChange)); + USB_HUB_PRINTF("local power source is %s\n", + (swap_16(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good"); + USB_HUB_PRINTF("%sover-current condition exists\n", + (swap_16(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no "); + usb_hub_power_on(hub); + for (i = 0; i < dev->maxchild; i++) { + struct usb_port_status portsts; + unsigned short portstatus, portchange; + + if (usb_get_port_status(dev, i + 1, &portsts) < 0) { + USB_HUB_PRINTF("get_port_status failed\n"); + continue; + } + portstatus = swap_16(portsts.wPortStatus); + portchange = swap_16(portsts.wPortChange); + USB_HUB_PRINTF("Port %d Status %X Change %X\n",i+1,portstatus,portchange); + if (portchange & USB_PORT_STAT_C_CONNECTION) { + USB_HUB_PRINTF("port %d connection change\n", i + 1); + usb_hub_port_connect_change(dev, i); + } + if (portchange & USB_PORT_STAT_C_ENABLE) { + USB_HUB_PRINTF("port %d enable change, status %x\n", i + 1, portstatus); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_ENABLE); + + /* EM interference sometimes causes bad shielded USB devices to + * be shutdown by the hub, this hack enables them again. + * Works at least with mouse driver */ + if (!(portstatus & USB_PORT_STAT_ENABLE) && + (portstatus & USB_PORT_STAT_CONNECTION) && (dev->children[i])) { + USB_HUB_PRINTF("already running port %i disabled by hub (EMI?), re-enabling...\n", + i + 1); + usb_hub_port_connect_change(dev, i); + } + } + if (portstatus & USB_PORT_STAT_SUSPEND) { + USB_HUB_PRINTF("port %d suspend change\n", i + 1); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_SUSPEND); + } + + if (portchange & USB_PORT_STAT_C_OVERCURRENT) { + USB_HUB_PRINTF("port %d over-current change\n", i + 1); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_OVER_CURRENT); + usb_hub_power_on(hub); + } + + if (portchange & USB_PORT_STAT_C_RESET) { + USB_HUB_PRINTF("port %d reset change\n", i + 1); + usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_RESET); + } + } /* end for i all ports */ + + return 0; +} + +int usb_hub_probe(struct usb_device *dev, int ifnum) +{ + struct usb_interface_descriptor *iface; + struct usb_endpoint_descriptor *ep; + int ret; + + iface = &dev->config.if_desc[ifnum]; + /* Is it a hub? */ + if (iface->bInterfaceClass != USB_CLASS_HUB) + return 0; + /* Some hubs have a subclass of 1, which AFAICT according to the */ + /* specs is not defined, but it works */ + if ((iface->bInterfaceSubClass != 0) && + (iface->bInterfaceSubClass != 1)) + return 0; + /* Multiple endpoints? What kind of mutant ninja-hub is this? */ + if (iface->bNumEndpoints != 1) + return 0; + ep = &iface->ep_desc[0]; + /* Output endpoint? Curiousier and curiousier.. */ + if (!(ep->bEndpointAddress & USB_DIR_IN)) + return 0; + /* If it's not an interrupt endpoint, we'd better punt! */ + if ((ep->bmAttributes & 3) != 3) + return 0; + /* We found a hub */ + USB_HUB_PRINTF("USB hub found\n"); + ret=usb_hub_configure(dev); + return ret; +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_USB) */ + +/* EOF */ diff --git a/common/usb_kbd.c b/common/usb_kbd.c new file mode 100644 index 0000000..56c2166 --- /dev/null +++ b/common/usb_kbd.c @@ -0,0 +1,728 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * Part of this source has been derived from the Linux USB + * project. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include + +#ifdef CONFIG_USB_KEYBOARD + +#include + +#undef USB_KBD_DEBUG +/* + * if overwrite_console returns 1, the stdin, stderr and stdout + * are switched to the serial port, else the settings in the + * environment are used + */ +#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console (void); +#else +int overwrite_console (void) +{ + return (0); +} +#endif + +#ifdef USB_KBD_DEBUG +#define USB_KBD_PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define USB_KBD_PRINTF(fmt,args...) +#endif + + +#define REPEAT_RATE 40/4 /* 40msec -> 25cps */ +#define REPEAT_DELAY 10 /* 10 x REAPEAT_RATE = 400msec */ + +#define NUM_LOCK 0x53 +#define CAPS_LOCK 0x39 +#define SCROLL_LOCK 0x47 + + +/* Modifier bits */ +#define LEFT_CNTR 0 +#define LEFT_SHIFT 1 +#define LEFT_ALT 2 +#define LEFT_GUI 3 +#define RIGHT_CNTR 4 +#define RIGHT_SHIFT 5 +#define RIGHT_ALT 6 +#define RIGHT_GUI 7 + +#define USB_KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ + +static volatile char usb_kbd_buffer[USB_KBD_BUFFER_LEN]; +static volatile int usb_in_pointer = 0; +static volatile int usb_out_pointer = 0; + +unsigned char new[8]; +unsigned char old[8]; +int repeat_delay; +#define DEVNAME "usbkbd" +static unsigned char num_lock = 0; +static unsigned char caps_lock = 0; +static unsigned char scroll_lock = 0; + +static unsigned char leds __attribute__ ((aligned (0x4))); + +static unsigned char usb_kbd_numkey[] = { + '1', '2', '3', '4', '5', '6', '7', '8', '9', '0','\r',0x1b,'\b','\t',' ', '-', + '=', '[', ']','\\', '#', ';', '\'', '`', ',', '.', '/' +}; +static unsigned char usb_kbd_numkey_shifted[] = { + '!', '@', '#', '$', '%', '^', '&', '*', '(', ')','\r',0x1b,'\b','\t',' ', '_', + '+', '{', '}', '|', '~', ':', '"', '~', '<', '>', '?' +}; + +/****************************************************************** + * Queue handling + ******************************************************************/ +/* puts character in the queue and sets up the in and out pointer */ +static void usb_kbd_put_queue(char data) +{ + if((usb_in_pointer+1)==USB_KBD_BUFFER_LEN) { + if(usb_out_pointer==0) { + return; /* buffer full */ + } else{ + usb_in_pointer=0; + } + } else { + if((usb_in_pointer+1)==usb_out_pointer) + return; /* buffer full */ + usb_in_pointer++; + } + usb_kbd_buffer[usb_in_pointer]=data; + return; +} + +/* test if a character is in the queue */ +static int usb_kbd_testc(void) +{ + if(usb_in_pointer==usb_out_pointer) + return(0); /* no data */ + else + return(1); +} +/* gets the character from the queue */ +static int usb_kbd_getc(void) +{ + char c; + while(usb_in_pointer==usb_out_pointer); + if((usb_out_pointer+1)==USB_KBD_BUFFER_LEN) + usb_out_pointer=0; + else + usb_out_pointer++; + c=usb_kbd_buffer[usb_out_pointer]; + return (int)c; + +} + +/* forward decleration */ +static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum); + +/* search for keyboard and register it if found */ +int drv_usb_kbd_init(void) +{ + int error,i,index; + device_t usb_kbd_dev,*old_dev; + struct usb_device *dev; + char *stdinname = getenv ("stdin"); + + usb_in_pointer=0; + usb_out_pointer=0; + /* scan all USB Devices */ + for(i=0;idevnum!=-1) { + if(usb_kbd_probe(dev,0)==1) { /* Ok, we found a keyboard */ + /* check, if it is already registered */ + USB_KBD_PRINTF("USB KBD found set up device.\n"); + for (index=1; index<=ListNumItems(devlist); index++) { + old_dev = ListGetPtrToItem(devlist, index); + if(strcmp(old_dev->name,DEVNAME)==0) { + /* ok, already registered, just return ok */ + USB_KBD_PRINTF("USB KBD is already registered.\n"); + return 1; + } + } + /* register the keyboard */ + USB_KBD_PRINTF("USB KBD register.\n"); + memset (&usb_kbd_dev, 0, sizeof(device_t)); + strcpy(usb_kbd_dev.name, DEVNAME); + usb_kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + usb_kbd_dev.putc = NULL; + usb_kbd_dev.puts = NULL; + usb_kbd_dev.getc = usb_kbd_getc; + usb_kbd_dev.tstc = usb_kbd_testc; + error = device_register (&usb_kbd_dev); + if(error==0) { + /* check if this is the standard input device */ + if(strcmp(stdinname,DEVNAME)==0) { + /* reassign the console */ + if(overwrite_console()) { + return 1; + } + error=console_assign(stdin,DEVNAME); + if(error==0) + return 1; + else + return error; + } + return 1; + } + return error; + } + } + } + /* no USB Keyboard found */ + return -1; +} + + +/* deregistering the keyboard */ +int usb_kbd_deregister(void) +{ + return device_deregister(DEVNAME); +} + +/************************************************************************** + * Low Level drivers + */ + +/* set the LEDs. Since this is used in the irq routine, the control job + is issued with a timeout of 0. This means, that the job is queued without + waiting for job completion */ + +static void usb_kbd_setled(struct usb_device *dev) +{ + struct usb_interface_descriptor *iface; + iface = &dev->config.if_desc[0]; + leds=0; + if(scroll_lock!=0) + leds|=1; + leds<<=1; + if(caps_lock!=0) + leds|=1; + leds<<=1; + if(num_lock!=0) + leds|=1; + usb_control_msg(dev, usb_sndctrlpipe(dev, 0), + USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + 0x200, iface->bInterfaceNumber,(void *)&leds, 1, 0); + +} + + +#define CAPITAL_MASK 0x20 +/* Translate the scancode in ASCII */ +static int usb_kbd_translate(unsigned char scancode,unsigned char modifier,int pressed) +{ + unsigned char keycode; + + if(pressed==0) { + /* key released */ + repeat_delay=0; + return 0; + } + if(pressed==2) { + repeat_delay++; + if(repeat_delay3) && (scancode<0x1d)) { /* alpha numeric values */ + keycode=scancode-4 + 0x61; + if(caps_lock) + keycode&=~CAPITAL_MASK; /* switch to capital Letters */ + if(((modifier&(1<0x1d) && (scancode<0x3A)) { + if(((modifier&(1<irq_status!=0)||(dev->irq_act_len!=8)) + { + USB_KBD_PRINTF("usb_keyboard Error %lX, len %d\n",dev->irq_status,dev->irq_act_len); + return 1; + } + res=0; + for (i = 2; i < 8; i++) { + if (old[i] > 3 && memscan(&new[2], old[i], 6) == &new[8]) { + res|=usb_kbd_translate(old[i],new[0],0); + } + if (new[i] > 3 && memscan(&old[2], new[i], 6) == &old[8]) { + res|=usb_kbd_translate(new[i],new[0],1); + } + } + if((new[2]>3) && (old[2]==new[2])) /* still pressed */ + res|=usb_kbd_translate(new[2],new[0],2); + if(res==1) + usb_kbd_setled(dev); + memcpy(&old[0],&new[0], 8); + return 1; /* install IRQ Handler again */ +} + +/* probes the USB device dev for keyboard type */ +static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) +{ + struct usb_interface_descriptor *iface; + struct usb_endpoint_descriptor *ep; + int pipe,maxp; + + if (dev->descriptor.bNumConfigurations != 1) return 0; + iface = &dev->config.if_desc[ifnum]; + + if (iface->bInterfaceClass != 3) return 0; + if (iface->bInterfaceSubClass != 1) return 0; + if (iface->bInterfaceProtocol != 1) return 0; + if (iface->bNumEndpoints != 1) return 0; + + ep = &iface->ep_desc[0]; + + if (!(ep->bEndpointAddress & 0x80)) return 0; + if ((ep->bmAttributes & 3) != 3) return 0; + USB_KBD_PRINTF("USB KBD found set protocol...\n"); + /* ok, we found a USB Keyboard, install it */ + /* usb_kbd_get_hid_desc(dev); */ + usb_set_protocol(dev, iface->bInterfaceNumber, 0); + USB_KBD_PRINTF("USB KBD found set idle...\n"); + usb_set_idle(dev, iface->bInterfaceNumber, REPEAT_RATE, 0); + memset(&new[0], 0, 8); + memset(&old[0], 0, 8); + repeat_delay=0; + pipe = usb_rcvintpipe(dev, ep->bEndpointAddress); + maxp = usb_maxpacket(dev, pipe); + dev->irq_handle=usb_kbd_irq; + USB_KBD_PRINTF("USB KBD enable interrupt pipe...\n"); + usb_submit_int_msg(dev,pipe,&new[0], maxp > 8 ? 8 : maxp,ep->bInterval); + return 1; +} + + +#if 0 +struct usb_hid_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; /* 0x21 for HID */ + unsigned short bcdHID; /* release number */ + unsigned char bCountryCode; + unsigned char bNumDescriptors; + unsigned char bReportDescriptorType; + unsigned short wDescriptorLength; +} __attribute__ ((packed)); + +/* + * We parse each description item into this structure. Short items data + * values are expanded to 32-bit signed int, long items contain a pointer + * into the data area. + */ + +struct hid_item { + unsigned char format; + unsigned char size; + unsigned char type; + unsigned char tag; + union { + unsigned char u8; + char s8; + unsigned short u16; + short s16; + unsigned long u32; + long s32; + unsigned char *longdata; + } data; +}; + +/* + * HID report item format + */ + +#define HID_ITEM_FORMAT_SHORT 0 +#define HID_ITEM_FORMAT_LONG 1 + +/* + * Special tag indicating long items + */ + +#define HID_ITEM_TAG_LONG 15 + + +static struct usb_hid_descriptor usb_kbd_hid_desc; + +void usb_kbd_display_hid(struct usb_hid_descriptor *hid) +{ + printf("USB_HID_DESC:\n"); + printf(" bLenght 0x%x\n",hid->bLength); + printf(" bcdHID 0x%x\n",hid->bcdHID); + printf(" bCountryCode %d\n",hid->bCountryCode); + printf(" bNumDescriptors 0x%x\n",hid->bNumDescriptors); + printf(" bReportDescriptorType 0x%x\n",hid->bReportDescriptorType); + printf(" wDescriptorLength 0x%x\n",hid->wDescriptorLength); +} + + +/* + * Fetch a report description item from the data stream. We support long + * items, though they are not used yet. + */ + +static int fetch_item(unsigned char *start,unsigned char *end, struct hid_item *item) +{ + if((end - start) > 0) { + unsigned char b = *start++; + item->type = (b >> 2) & 3; + item->tag = (b >> 4) & 15; + if (item->tag == HID_ITEM_TAG_LONG) { + item->format = HID_ITEM_FORMAT_LONG; + if ((end - start) >= 2) { + item->size = *start++; + item->tag = *start++; + if ((end - start) >= item->size) { + item->data.longdata = start; + start += item->size; + return item->size; + } + } + } else { + item->format = HID_ITEM_FORMAT_SHORT; + item->size = b & 3; + switch (item->size) { + case 0: + return item->size; + case 1: + if ((end - start) >= 1) { + item->data.u8 = *start++; + return item->size; + } + break; + case 2: + if ((end - start) >= 2) { + item->data.u16 = swap_16((unsigned short *)start); + start+=2; + return item->size; + } + case 3: + item->size++; + if ((end - start) >= 4) { + item->data.u32 = swap_32((unsigned long *)start); + start+=4; + return item->size; + } + } + } + } + return -1; +} + +/* + * HID report descriptor item type (prefix bit 2,3) + */ + +#define HID_ITEM_TYPE_MAIN 0 +#define HID_ITEM_TYPE_GLOBAL 1 +#define HID_ITEM_TYPE_LOCAL 2 +#define HID_ITEM_TYPE_RESERVED 3 +/* + * HID report descriptor main item tags + */ + +#define HID_MAIN_ITEM_TAG_INPUT 8 +#define HID_MAIN_ITEM_TAG_OUTPUT 9 +#define HID_MAIN_ITEM_TAG_FEATURE 11 +#define HID_MAIN_ITEM_TAG_BEGIN_COLLECTION 10 +#define HID_MAIN_ITEM_TAG_END_COLLECTION 12 +/* + * HID report descriptor main item contents + */ + +#define HID_MAIN_ITEM_CONSTANT 0x001 +#define HID_MAIN_ITEM_VARIABLE 0x002 +#define HID_MAIN_ITEM_RELATIVE 0x004 +#define HID_MAIN_ITEM_WRAP 0x008 +#define HID_MAIN_ITEM_NONLINEAR 0x010 +#define HID_MAIN_ITEM_NO_PREFERRED 0x020 +#define HID_MAIN_ITEM_NULL_STATE 0x040 +#define HID_MAIN_ITEM_VOLATILE 0x080 +#define HID_MAIN_ITEM_BUFFERED_BYTE 0x100 + +/* + * HID report descriptor collection item types + */ + +#define HID_COLLECTION_PHYSICAL 0 +#define HID_COLLECTION_APPLICATION 1 +#define HID_COLLECTION_LOGICAL 2 +/* + * HID report descriptor global item tags + */ + +#define HID_GLOBAL_ITEM_TAG_USAGE_PAGE 0 +#define HID_GLOBAL_ITEM_TAG_LOGICAL_MINIMUM 1 +#define HID_GLOBAL_ITEM_TAG_LOGICAL_MAXIMUM 2 +#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MINIMUM 3 +#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MAXIMUM 4 +#define HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT 5 +#define HID_GLOBAL_ITEM_TAG_UNIT 6 +#define HID_GLOBAL_ITEM_TAG_REPORT_SIZE 7 +#define HID_GLOBAL_ITEM_TAG_REPORT_ID 8 +#define HID_GLOBAL_ITEM_TAG_REPORT_COUNT 9 +#define HID_GLOBAL_ITEM_TAG_PUSH 10 +#define HID_GLOBAL_ITEM_TAG_POP 11 + +/* + * HID report descriptor local item tags + */ + +#define HID_LOCAL_ITEM_TAG_USAGE 0 +#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM 1 +#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM 2 +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 3 +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM 4 +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM 5 +#define HID_LOCAL_ITEM_TAG_STRING_INDEX 7 +#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM 8 +#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM 9 +#define HID_LOCAL_ITEM_TAG_DELIMITER 10 + + +static void usb_kbd_show_item(struct hid_item *item) +{ + switch(item->type) { + case HID_ITEM_TYPE_MAIN: + switch(item->tag) { + case HID_MAIN_ITEM_TAG_INPUT: + printf("Main Input"); + break; + case HID_MAIN_ITEM_TAG_OUTPUT: + printf("Main Output"); + break; + case HID_MAIN_ITEM_TAG_FEATURE: + printf("Main Feature"); + break; + case HID_MAIN_ITEM_TAG_BEGIN_COLLECTION: + printf("Main Begin Collection"); + break; + case HID_MAIN_ITEM_TAG_END_COLLECTION: + printf("Main End Collection"); + break; + default: + printf("Main reserved %d",item->tag); + break; + } + break; + case HID_ITEM_TYPE_GLOBAL: + switch(item->tag) { + case HID_GLOBAL_ITEM_TAG_USAGE_PAGE: + printf("- Global Usage Page"); + break; + case HID_GLOBAL_ITEM_TAG_LOGICAL_MINIMUM: + printf("- Global Logical Minimum"); + break; + case HID_GLOBAL_ITEM_TAG_LOGICAL_MAXIMUM: + printf("- Global Logical Maximum"); + break; + case HID_GLOBAL_ITEM_TAG_PHYSICAL_MINIMUM: + printf("- Global physical Minimum"); + break; + case HID_GLOBAL_ITEM_TAG_PHYSICAL_MAXIMUM: + printf("- Global physical Maximum"); + break; + case HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT: + printf("- Global Unit Exponent"); + break; + case HID_GLOBAL_ITEM_TAG_UNIT: + printf("- Global Unit"); + break; + case HID_GLOBAL_ITEM_TAG_REPORT_SIZE: + printf("- Global Report Size"); + break; + case HID_GLOBAL_ITEM_TAG_REPORT_ID: + printf("- Global Report ID"); + break; + case HID_GLOBAL_ITEM_TAG_REPORT_COUNT: + printf("- Global Report Count"); + break; + case HID_GLOBAL_ITEM_TAG_PUSH: + printf("- Global Push"); + break; + case HID_GLOBAL_ITEM_TAG_POP: + printf("- Global Pop"); + break; + default: + printf("- Global reserved %d",item->tag); + break; + } + break; + case HID_ITEM_TYPE_LOCAL: + switch(item->tag) { + case HID_LOCAL_ITEM_TAG_USAGE: + printf("-- Local Usage"); + break; + case HID_LOCAL_ITEM_TAG_USAGE_MINIMUM: + printf("-- Local Usage Minimum"); + break; + case HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM: + printf("-- Local Usage Maximum"); + break; + case HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX: + printf("-- Local Designator Index"); + break; + case HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM: + printf("-- Local Designator Minimum"); + break; + case HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM: + printf("-- Local Designator Maximum"); + break; + case HID_LOCAL_ITEM_TAG_STRING_INDEX: + printf("-- Local String Index"); + break; + case HID_LOCAL_ITEM_TAG_STRING_MINIMUM: + printf("-- Local String Minimum"); + break; + case HID_LOCAL_ITEM_TAG_STRING_MAXIMUM: + printf("-- Local String Maximum"); + break; + case HID_LOCAL_ITEM_TAG_DELIMITER: + printf("-- Local Delimiter"); + break; + default: + printf("-- Local reserved %d",item->tag); + break; + } + break; + default: + printf("--- reserved %d",item->type); + break; + } + switch(item->size) { + case 1: + printf(" %d",item->data.u8); + break; + case 2: + printf(" %d",item->data.u16); + break; + case 4: + printf(" %ld",item->data.u32); + break; + } + printf("\n"); +} + + +static int usb_kbd_get_hid_desc(struct usb_device *dev) +{ + unsigned char buffer[256]; + struct usb_descriptor_header *head; + struct usb_config_descriptor *config; + int index,len,i; + unsigned char *start, *end; + struct hid_item item; + + if(usb_get_configuration_no(dev,&buffer[0],0)==-1) + return -1; + head =(struct usb_descriptor_header *)&buffer[0]; + if(head->bDescriptorType!=USB_DT_CONFIG) { + printf(" ERROR: NOT USB_CONFIG_DESC %x\n",head->bDescriptorType); + return -1; + } + index=head->bLength; + config=(struct usb_config_descriptor *)&buffer[0]; + len=swap_16(config->wTotalLength); + /* Ok the first entry must be a configuration entry, now process the others */ + head=(struct usb_descriptor_header *)&buffer[index]; + while(index+1 < len) { + if(head->bDescriptorType==USB_DT_HID) { + printf("HID desc found\n"); + memcpy(&usb_kbd_hid_desc,&buffer[index],buffer[index]); + usb_kbd_hid_desc.bcdHID=swap_16(usb_kbd_hid_desc.bcdHID); + usb_kbd_hid_desc.wDescriptorLength=swap_16(usb_kbd_hid_desc.wDescriptorLength); + usb_kbd_display_hid(&usb_kbd_hid_desc); + len=0; + break; + } + index+=head->bLength; + head=(struct usb_descriptor_header *)&buffer[index]; + } + if(len>0) + return -1; + len=usb_kbd_hid_desc.wDescriptorLength; + if((index = usb_get_class_descriptor(dev, 0, USB_DT_REPORT, 0, &buffer[0], len)) < 0) { + printf("reading report descriptor failed\n"); + return -1; + } + printf(" report descriptor (size %u, read %d)\n", len, index); + start=&buffer[0]; + end=&buffer[len]; + i=0; + do { + index=fetch_item(start,end,&item); + i+=index; + i++; + if(index>=0) + usb_kbd_show_item(&item); + + start+=index; + start++; + } while(index>=0); + +} + + +#endif + +#endif /* CONFIG_USB_KEYBOARD */ diff --git a/common/usb_storage.c b/common/usb_storage.c new file mode 100644 index 0000000..99e4ab0 --- /dev/null +++ b/common/usb_storage.c @@ -0,0 +1,1222 @@ +/* + * Most of this source has been derived from the Linux USB + * project: + * (c) 1999-2002 Matthew Dharm (mdharm-usb@one-eyed-alien.net) + * (c) 2000 David L. Brown, Jr. (usb-storage@davidb.org) + * (c) 1999 Michael Gee (michael@linuxspecific.com) + * (c) 2000 Yggdrasil Computing, Inc. + * + * + * Adapted for U-Boot: + * (C) Copyright 2001 Denis Peter, MPL AG Switzerland + * + * For BBB support (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * BBB support based on /sys/dev/usb/umass.c from + * FreeBSD. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* Note: + * Currently only the CBI transport protocoll has been implemented, and it + * is only tested with a TEAC USB Floppy. Other Massstorages with CBI or CB + * transport protocoll may work as well. + */ +/* + * New Note: + * Support for USB Mass Storage Devices (BBB) has been added. It has + * only been tested with USB memory sticks. + * Nota bene: if you are using the BBB support with a little-endian + * CPU then you MUST define LITTLEENDIAN in the configuration file! + */ + + +#include +#include +#include + + +#if (CONFIG_COMMANDS & CFG_CMD_USB) +#include + +#ifdef CONFIG_USB_STORAGE + +#undef USB_STOR_DEBUG +#undef BBB_COMDAT_TRACE +#undef BBB_XPORT_TRACE + +#ifdef USB_STOR_DEBUG +#define USB_STOR_PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define USB_STOR_PRINTF(fmt,args...) +#endif + +#include +/* direction table -- this indicates the direction of the data + * transfer for each command code -- a 1 indicates input + */ +unsigned char us_direction[256/8] = { + 0x28, 0x81, 0x14, 0x14, 0x20, 0x01, 0x90, 0x77, + 0x0C, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +#define US_DIRECTION(x) ((us_direction[x>>3] >> (x & 7)) & 1) + +static unsigned char usb_stor_buf[512]; +static ccb usb_ccb; + +/* + * CBI style + */ + +#define US_CBI_ADSC 0 + +/* + * BULK only + */ +#define US_BBB_RESET 0xff +#define US_BBB_GET_MAX_LUN 0xfe + +/* Command Block Wrapper */ +typedef struct { + __u32 dCBWSignature; +# define CBWSIGNATURE 0x43425355 + __u32 dCBWTag; + __u32 dCBWDataTransferLength; + __u8 bCBWFlags; +# define CBWFLAGS_OUT 0x00 +# define CBWFLAGS_IN 0x80 + __u8 bCBWLUN; + __u8 bCDBLength; +# define CBWCDBLENGTH 16 + __u8 CBWCDB[CBWCDBLENGTH]; +} umass_bbb_cbw_t; +#define UMASS_BBB_CBW_SIZE 31 +static __u32 CBWTag = 0; + +/* Command Status Wrapper */ +typedef struct { + __u32 dCSWSignature; +# define CSWSIGNATURE 0x53425355 + __u32 dCSWTag; + __u32 dCSWDataResidue; + __u8 bCSWStatus; +# define CSWSTATUS_GOOD 0x0 +# define CSWSTATUS_FAILED 0x1 +# define CSWSTATUS_PHASE 0x2 +} umass_bbb_csw_t; +#define UMASS_BBB_CSW_SIZE 13 + +#define USB_MAX_STOR_DEV 5 +static int usb_max_devs = 0; /* number of highest available usb device */ + +static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV]; + +struct us_data; +typedef int (*trans_cmnd)(ccb*, struct us_data*); +typedef int (*trans_reset)(struct us_data*); + +struct us_data { + struct usb_device *pusb_dev; /* this usb_device */ + unsigned int flags; /* from filter initially */ + unsigned char ifnum; /* interface number */ + unsigned char ep_in; /* in endpoint */ + unsigned char ep_out; /* out ....... */ + unsigned char ep_int; /* interrupt . */ + unsigned char subclass; /* as in overview */ + unsigned char protocol; /* .............. */ + unsigned char attention_done; /* force attn on first cmd */ + unsigned short ip_data; /* interrupt data */ + int action; /* what to do */ + int ip_wanted; /* needed */ + int *irq_handle; /* for USB int requests */ + unsigned int irqpipe; /* pipe for release_irq */ + unsigned char irqmaxp; /* max packed for irq Pipe */ + unsigned char irqinterval; /* Intervall for IRQ Pipe */ + ccb *srb; /* current srb */ + trans_reset transport_reset; /* reset routine */ + trans_cmnd transport; /* transport routine */ +}; + +static struct us_data usb_stor[USB_MAX_STOR_DEV]; + + +#define USB_STOR_TRANSPORT_GOOD 0 +#define USB_STOR_TRANSPORT_FAILED -1 +#define USB_STOR_TRANSPORT_ERROR -2 + + +int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc); +int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data *ss); +unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer); +struct usb_device * usb_get_dev_index(int index); +void uhci_show_temp_int_td(void); + +block_dev_desc_t *usb_stor_get_dev(int index) +{ + return &usb_dev_desc[index]; +} + + +void usb_show_progress(void) +{ + printf("."); +} + +/********************************************************************************* + * show info on storage devices; 'usb start/init' must be invoked earlier + * as we only retrieve structures populated during devices initialization + */ +void usb_stor_info(void) +{ + int i; + + if (usb_max_devs > 0) + for (i = 0; i < usb_max_devs; i++) { + printf (" Device %d: ", i); + dev_print(&usb_dev_desc[i]); + } + else + printf("No storage devices, perhaps not 'usb start'ed..?\n"); +} + +/********************************************************************************* + * scan the usb and reports device info + * to the user if mode = 1 + * returns current device or -1 if no + */ +int usb_stor_scan(int mode) +{ + unsigned char i; + struct usb_device *dev; + + /* GJ */ + memset(usb_stor_buf, 0, sizeof(usb_stor_buf)); + + if(mode==1) { + printf(" scanning bus for storage devices... "); + } + usb_disable_asynch(1); /* asynch transfer not allowed */ + + for(i=0;i0) + return 0; + else + return-1; +} + +static int usb_stor_irq(struct usb_device *dev) +{ + struct us_data *us; + us=(struct us_data *)dev->privptr; + + if(us->ip_wanted) { + us->ip_wanted=0; + } + return 0; +} + + +#ifdef USB_STOR_DEBUG + +static void usb_show_srb(ccb * pccb) +{ + int i; + printf("SRB: len %d datalen 0x%lX\n ",pccb->cmdlen,pccb->datalen); + for(i=0;i<12;i++) { + printf("%02X ",pccb->cmd[i]); + } + printf("\n"); +} + +static void display_int_status(unsigned long tmp) +{ + printf("Status: %s %s %s %s %s %s %s\n", + (tmp & USB_ST_ACTIVE) ? "Active" : "", + (tmp & USB_ST_STALLED) ? "Stalled" : "", + (tmp & USB_ST_BUF_ERR) ? "Buffer Error" : "", + (tmp & USB_ST_BABBLE_DET) ? "Babble Det" : "", + (tmp & USB_ST_NAK_REC) ? "NAKed" : "", + (tmp & USB_ST_CRC_ERR) ? "CRC Error" : "", + (tmp & USB_ST_BIT_ERR) ? "Bitstuff Error" : ""); +} +#endif +/*********************************************************************** + * Data transfer routines + ***********************************************************************/ + +static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length) +{ + int max_size; + int this_xfer; + int result; + int partial; + int maxtry; + int stat; + + /* determine the maximum packet size for these transfers */ + max_size = usb_maxpacket(us->pusb_dev, pipe) * 16; + + /* while we have data left to transfer */ + while (length) { + + /* calculate how long this will be -- maximum or a remainder */ + this_xfer = length > max_size ? max_size : length; + length -= this_xfer; + + /* setup the retry counter */ + maxtry = 10; + + /* set up the transfer loop */ + do { + /* transfer the data */ + USB_STOR_PRINTF("Bulk xfer 0x%x(%d) try #%d\n", + (unsigned int)buf, this_xfer, 11 - maxtry); + result = usb_bulk_msg(us->pusb_dev, pipe, buf, + this_xfer, &partial, USB_CNTL_TIMEOUT*5); + USB_STOR_PRINTF("bulk_msg returned %d xferred %d/%d\n", + result, partial, this_xfer); + if(us->pusb_dev->status!=0) { + /* if we stall, we need to clear it before we go on */ +#ifdef USB_STOR_DEBUG + display_int_status(us->pusb_dev->status); +#endif + if (us->pusb_dev->status & USB_ST_STALLED) { + USB_STOR_PRINTF("stalled ->clearing endpoint halt for pipe 0x%x\n", pipe); + stat = us->pusb_dev->status; + usb_clear_halt(us->pusb_dev, pipe); + us->pusb_dev->status=stat; + if(this_xfer == partial) { + USB_STOR_PRINTF("bulk transferred with error %X, but data ok\n",us->pusb_dev->status); + return 0; + } + else + return result; + } + if (us->pusb_dev->status & USB_ST_NAK_REC) { + USB_STOR_PRINTF("Device NAKed bulk_msg\n"); + return result; + } + if(this_xfer == partial) { + USB_STOR_PRINTF("bulk transferred with error %d, but data ok\n",us->pusb_dev->status); + return 0; + } + /* if our try counter reaches 0, bail out */ + USB_STOR_PRINTF("bulk transferred with error %d, data %d\n",us->pusb_dev->status,partial); + if (!maxtry--) + return result; + } + /* update to show what data was transferred */ + this_xfer -= partial; + buf += partial; + /* continue until this transfer is done */ + } while ( this_xfer ); + } + + /* if we get here, we're done and successful */ + return 0; +} + +static int usb_stor_BBB_reset(struct us_data *us) +{ + int result; + unsigned int pipe; + + /* + * Reset recovery (5.3.4 in Universal Serial Bus Mass Storage Class) + * + * For Reset Recovery the host shall issue in the following order: + * a) a Bulk-Only Mass Storage Reset + * b) a Clear Feature HALT to the Bulk-In endpoint + * c) a Clear Feature HALT to the Bulk-Out endpoint + * + * This is done in 3 steps. + * + * If the reset doesn't succeed, the device should be port reset. + * + * This comment stolen from FreeBSD's /sys/dev/usb/umass.c. + */ + USB_STOR_PRINTF("BBB_reset\n"); + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0), + US_BBB_RESET, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + 0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT*5); + + if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) + { + USB_STOR_PRINTF("RESET:stall\n"); + return -1; + } + + /* long wait for reset */ + wait_ms(150); + USB_STOR_PRINTF("BBB_reset result %d: status %X reset\n",result,us->pusb_dev->status); + pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); + result = usb_clear_halt(us->pusb_dev, pipe); + /* long wait for reset */ + wait_ms(150); + USB_STOR_PRINTF("BBB_reset result %d: status %X clearing IN endpoint\n",result,us->pusb_dev->status); + /* long wait for reset */ + pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + result = usb_clear_halt(us->pusb_dev, pipe); + wait_ms(150); + USB_STOR_PRINTF("BBB_reset result %d: status %X clearing OUT endpoint\n",result,us->pusb_dev->status); + USB_STOR_PRINTF("BBB_reset done\n"); + return 0; +} + +/* FIXME: this reset function doesn't really reset the port, and it + * should. Actually it should probably do what it's doing here, and + * reset the port physically + */ +static int usb_stor_CB_reset(struct us_data *us) +{ + unsigned char cmd[12]; + int result; + + USB_STOR_PRINTF("CB_reset\n"); + memset(cmd, 0xFF, sizeof(cmd)); + cmd[0] = SCSI_SEND_DIAG; + cmd[1] = 4; + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0), + US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + 0, us->ifnum, cmd, sizeof(cmd), USB_CNTL_TIMEOUT*5); + + /* long wait for reset */ + wait_ms(1500); + USB_STOR_PRINTF("CB_reset result %d: status %X clearing endpoint halt\n",result,us->pusb_dev->status); + usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_in)); + usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_out)); + + USB_STOR_PRINTF("CB_reset done\n"); + return 0; +} + +/* + * Set up the command for a BBB device. Note that the actual SCSI + * command is copied into cbw.CBWCDB. + */ +int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) +{ + int result; + int actlen; + int dir_in; + unsigned int pipe; + umass_bbb_cbw_t cbw; + + dir_in = US_DIRECTION(srb->cmd[0]); + +#ifdef BBB_COMDAT_TRACE + printf("dir %d lun %d cmdlen %d cmd %p datalen %d pdata %p\n", dir_in, srb->lun, srb->cmdlen, srb->cmd, srb->datalen, srb->pdata); + if (srb->cmdlen) { + for(result = 0;result < srb->cmdlen;result++) + printf("cmd[%d] %#x ", result, srb->cmd[result]); + printf("\n"); + } +#endif + /* sanity checks */ + if (!(srb->cmdlen <= CBWCDBLENGTH)) { + USB_STOR_PRINTF("usb_stor_BBB_comdat:cmdlen too large\n"); + return -1; + } + + /* always OUT to the ep */ + pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + + cbw.dCBWSignature = swap_32(CBWSIGNATURE); + cbw.dCBWTag = swap_32(CBWTag++); + cbw.dCBWDataTransferLength = swap_32(srb->datalen); + cbw.bCBWFlags = (dir_in? CBWFLAGS_IN : CBWFLAGS_OUT); + cbw.bCBWLUN = srb->lun; + cbw.bCDBLength = srb->cmdlen; + /* copy the command data into the CBW command data buffer */ + /* DST SRC LEN!!! */ + memcpy(cbw.CBWCDB, srb->cmd, srb->cmdlen); + result = usb_bulk_msg(us->pusb_dev, pipe, &cbw, UMASS_BBB_CBW_SIZE, &actlen, USB_CNTL_TIMEOUT*5); + if (result < 0) + USB_STOR_PRINTF("usb_stor_BBB_comdat:usb_bulk_msg error\n"); + return result; +} + +/* FIXME: we also need a CBI_command which sets up the completion + * interrupt, and waits for it + */ +int usb_stor_CB_comdat(ccb *srb, struct us_data *us) +{ + int result = 0; + int dir_in,retry; + unsigned int pipe; + unsigned long status; + + retry=5; + dir_in=US_DIRECTION(srb->cmd[0]); + + if(dir_in) + pipe=usb_rcvbulkpipe(us->pusb_dev, us->ep_in); + else + pipe=usb_sndbulkpipe(us->pusb_dev, us->ep_out); + while(retry--) { + USB_STOR_PRINTF("CBI gets a command: Try %d\n",5-retry); +#ifdef USB_STOR_DEBUG + usb_show_srb(srb); +#endif + /* let's send the command via the control pipe */ + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0), + US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + 0, us->ifnum, + srb->cmd, srb->cmdlen, USB_CNTL_TIMEOUT*5); + USB_STOR_PRINTF("CB_transport: control msg returned %d, status %X\n",result,us->pusb_dev->status); + /* check the return code for the command */ + if (result < 0) { + if(us->pusb_dev->status & USB_ST_STALLED) { + status=us->pusb_dev->status; + USB_STOR_PRINTF(" stall during command found, clear pipe\n"); + usb_clear_halt(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0)); + us->pusb_dev->status=status; + } + USB_STOR_PRINTF(" error during command %02X Stat = %X\n",srb->cmd[0],us->pusb_dev->status); + return result; + } + /* transfer the data payload for this command, if one exists*/ + + USB_STOR_PRINTF("CB_transport: control msg returned %d, direction is %s to go 0x%lx\n",result,dir_in ? "IN" : "OUT",srb->datalen); + if (srb->datalen) { + result = us_one_transfer(us, pipe, (char *)srb->pdata,srb->datalen); + USB_STOR_PRINTF("CBI attempted to transfer data, result is %d status %lX, len %d\n", result,us->pusb_dev->status,us->pusb_dev->act_len); + if(!(us->pusb_dev->status & USB_ST_NAK_REC)) + break; + } /* if (srb->datalen) */ + else + break; + } + /* return result */ + + return result; +} + + +int usb_stor_CBI_get_status (ccb * srb, struct us_data *us) +{ + int timeout; + + us->ip_wanted = 1; + submit_int_msg (us->pusb_dev, us->irqpipe, + (void *) &us->ip_data, us->irqmaxp, us->irqinterval); + timeout = 1000; + while (timeout--) { + if ((volatile int *) us->ip_wanted == 0) + break; + wait_ms (10); + } + if (us->ip_wanted) { + printf (" Did not get interrupt on CBI\n"); + us->ip_wanted = 0; + return USB_STOR_TRANSPORT_ERROR; + } + USB_STOR_PRINTF + ("Got interrupt data 0x%x, transfered %d status 0x%lX\n", + us->ip_data, us->pusb_dev->irq_act_len, + us->pusb_dev->irq_status); + /* UFI gives us ASC and ASCQ, like a request sense */ + if (us->subclass == US_SC_UFI) { + if (srb->cmd[0] == SCSI_REQ_SENSE || + srb->cmd[0] == SCSI_INQUIRY) + return USB_STOR_TRANSPORT_GOOD; /* Good */ + else if (us->ip_data) + return USB_STOR_TRANSPORT_FAILED; + else + return USB_STOR_TRANSPORT_GOOD; + } + /* otherwise, we interpret the data normally */ + switch (us->ip_data) { + case 0x0001: + return USB_STOR_TRANSPORT_GOOD; + case 0x0002: + return USB_STOR_TRANSPORT_FAILED; + default: + return USB_STOR_TRANSPORT_ERROR; + } /* switch */ + return USB_STOR_TRANSPORT_ERROR; +} + +#define USB_TRANSPORT_UNKNOWN_RETRY 5 +#define USB_TRANSPORT_NOT_READY_RETRY 10 + +/* clear a stall on an endpoint - special for BBB devices */ +int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt) +{ + int result; + + /* ENDPOINT_HALT = 0, so set value to 0 */ + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0), + USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, + 0, endpt, 0, 0, USB_CNTL_TIMEOUT*5); + return result; +} + +int usb_stor_BBB_transport(ccb *srb, struct us_data *us) +{ + int result, retry; + int dir_in; + int actlen, data_actlen; + unsigned int pipe, pipein, pipeout; + umass_bbb_csw_t csw; +#ifdef BBB_XPORT_TRACE + unsigned char *ptr; + int index; +#endif + + dir_in = US_DIRECTION(srb->cmd[0]); + + /* COMMAND phase */ + USB_STOR_PRINTF("COMMAND phase\n"); + result = usb_stor_BBB_comdat(srb, us); + if (result < 0) { + USB_STOR_PRINTF("failed to send CBW status %ld\n", + us->pusb_dev->status); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } + wait_ms(5); + pipein = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); + pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + /* DATA phase + error handling */ + data_actlen = 0; + /* no data, go immediately to the STATUS phase */ + if (srb->datalen == 0) + goto st; + USB_STOR_PRINTF("DATA phase\n"); + if (dir_in) + pipe = pipein; + else + pipe = pipeout; + result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT*5); + /* special handling of STALL in DATA phase */ + if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { + USB_STOR_PRINTF("DATA:stall\n"); + /* clear the STALL on the endpoint */ + result = usb_stor_BBB_clear_endpt_stall(us, dir_in? us->ep_in : us->ep_out); + if (result >= 0) + /* continue on to STATUS phase */ + goto st; + } + if (result < 0) { + USB_STOR_PRINTF("usb_bulk_msg error status %ld\n", + us->pusb_dev->status); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } +#ifdef BBB_XPORT_TRACE + for (index = 0; index < data_actlen; index++) + printf("pdata[%d] %#x ", index, srb->pdata[index]); + printf("\n"); +#endif + /* STATUS phase + error handling */ + st: + retry = 0; + again: + USB_STOR_PRINTF("STATUS phase\n"); + result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE, + &actlen, USB_CNTL_TIMEOUT*5); + + /* special handling of STALL in STATUS phase */ + if((result < 0) && (retry < 1) && (us->pusb_dev->status & USB_ST_STALLED)) { + USB_STOR_PRINTF("STATUS:stall\n"); + /* clear the STALL on the endpoint */ + result = usb_stor_BBB_clear_endpt_stall(us, us->ep_in); + if (result >= 0 && (retry++ < 1)) + /* do a retry */ + goto again; + } + if (result < 0) { + USB_STOR_PRINTF("usb_bulk_msg error status %ld\n", + us->pusb_dev->status); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } +#ifdef BBB_XPORT_TRACE + ptr = (unsigned char *)&csw; + for (index = 0; index < UMASS_BBB_CSW_SIZE; index++) + printf("ptr[%d] %#x ", index, ptr[index]); + printf("\n"); +#endif + /* misuse pipe to get the residue */ + pipe = swap_32(csw.dCSWDataResidue); + if (pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0) + pipe = srb->datalen - data_actlen; + if (CSWSIGNATURE != swap_32(csw.dCSWSignature)) { + USB_STOR_PRINTF("!CSWSIGNATURE\n"); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } else if ((CBWTag - 1) != swap_32(csw.dCSWTag)) { + USB_STOR_PRINTF("!Tag\n"); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } else if (csw.bCSWStatus > CSWSTATUS_PHASE) { + USB_STOR_PRINTF(">PHASE\n"); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } else if (csw.bCSWStatus == CSWSTATUS_PHASE) { + USB_STOR_PRINTF("=PHASE\n"); + usb_stor_BBB_reset(us); + return USB_STOR_TRANSPORT_FAILED; + } else if (data_actlen > srb->datalen) { + USB_STOR_PRINTF("transferred %dB instead of %dB\n", + data_actlen, srb->datalen); + return USB_STOR_TRANSPORT_FAILED; + } else if (csw.bCSWStatus == CSWSTATUS_FAILED) { + USB_STOR_PRINTF("FAILED\n"); + return USB_STOR_TRANSPORT_FAILED; + } + + return result; +} + +int usb_stor_CB_transport(ccb *srb, struct us_data *us) +{ + int result,status; + ccb *psrb; + ccb reqsrb; + int retry,notready; + + psrb=&reqsrb; + status=USB_STOR_TRANSPORT_GOOD; + retry=0; + notready=0; + /* issue the command */ +do_retry: + result=usb_stor_CB_comdat(srb,us); + USB_STOR_PRINTF("command / Data returned %d, status %X\n",result,us->pusb_dev->status); + /* if this is an CBI Protocol, get IRQ */ + if(us->protocol==US_PR_CBI) { + status=usb_stor_CBI_get_status(srb,us); + /* if the status is error, report it */ + if(status==USB_STOR_TRANSPORT_ERROR) { + USB_STOR_PRINTF(" USB CBI Command Error\n"); + return status; + } + srb->sense_buf[12]=(unsigned char)(us->ip_data>>8); + srb->sense_buf[13]=(unsigned char)(us->ip_data&0xff); + if(!us->ip_data) { + /* if the status is good, report it */ + if(status==USB_STOR_TRANSPORT_GOOD) { + USB_STOR_PRINTF(" USB CBI Command Good\n"); + return status; + } + } + } + /* do we have to issue an auto request? */ + /* HERE we have to check the result */ + if((result<0) && !(us->pusb_dev->status & USB_ST_STALLED)) { + USB_STOR_PRINTF("ERROR %X\n",us->pusb_dev->status); + us->transport_reset(us); + return USB_STOR_TRANSPORT_ERROR; + } + if((us->protocol==US_PR_CBI) && + ((srb->cmd[0]==SCSI_REQ_SENSE) || + (srb->cmd[0]==SCSI_INQUIRY))) { /* do not issue an autorequest after request sense */ + USB_STOR_PRINTF("No auto request and good\n"); + return USB_STOR_TRANSPORT_GOOD; + } + /* issue an request_sense */ + memset(&psrb->cmd[0],0,12); + psrb->cmd[0]=SCSI_REQ_SENSE; + psrb->cmd[1]=srb->lun<<5; + psrb->cmd[4]=18; + psrb->datalen=18; + psrb->pdata=&srb->sense_buf[0]; + psrb->cmdlen=12; + /* issue the command */ + result=usb_stor_CB_comdat(psrb,us); + USB_STOR_PRINTF("auto request returned %d\n",result); + /* if this is an CBI Protocol, get IRQ */ + if(us->protocol==US_PR_CBI) { + status=usb_stor_CBI_get_status(psrb,us); + } + if((result<0)&&!(us->pusb_dev->status & USB_ST_STALLED)) { + USB_STOR_PRINTF(" AUTO REQUEST ERROR %d\n",us->pusb_dev->status); + return USB_STOR_TRANSPORT_ERROR; + } + USB_STOR_PRINTF("autorequest returned 0x%02X 0x%02X 0x%02X 0x%02X\n",srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); + /* Check the auto request result */ + if((srb->sense_buf[2]==0) && + (srb->sense_buf[12]==0) && + (srb->sense_buf[13]==0)) /* ok, no sense */ + return USB_STOR_TRANSPORT_GOOD; + /* Check the auto request result */ + switch(srb->sense_buf[2]) { + case 0x01: /* Recovered Error */ + return USB_STOR_TRANSPORT_GOOD; + break; + case 0x02: /* Not Ready */ + if(notready++ > USB_TRANSPORT_NOT_READY_RETRY) { + printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X (NOT READY)\n", + srb->cmd[0],srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); + return USB_STOR_TRANSPORT_FAILED; + } else { + wait_ms(100); + goto do_retry; + } + break; + default: + if(retry++ > USB_TRANSPORT_UNKNOWN_RETRY) { + printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X\n", + srb->cmd[0],srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); + return USB_STOR_TRANSPORT_FAILED; + } else { + goto do_retry; + } + break; + } + return USB_STOR_TRANSPORT_FAILED; +} + + +static int usb_inquiry(ccb *srb,struct us_data *ss) +{ + int retry,i; + retry=5; + do { + memset(&srb->cmd[0],0,12); + srb->cmd[0]=SCSI_INQUIRY; + srb->cmd[1]=srb->lun<<5; + srb->cmd[4]=36; + srb->datalen=36; + srb->cmdlen=12; + i=ss->transport(srb,ss); + USB_STOR_PRINTF("inquiry returns %d\n",i); + if(i==0) + break; + } while(retry--); + + if(!retry) { + printf("error in inquiry\n"); + return -1; + } + return 0; +} + +static int usb_request_sense(ccb *srb,struct us_data *ss) +{ + char *ptr; + + ptr=(char *)srb->pdata; + memset(&srb->cmd[0],0,12); + srb->cmd[0]=SCSI_REQ_SENSE; + srb->cmd[1]=srb->lun<<5; + srb->cmd[4]=18; + srb->datalen=18; + srb->pdata=&srb->sense_buf[0]; + srb->cmdlen=12; + ss->transport(srb,ss); + USB_STOR_PRINTF("Request Sense returned %02X %02X %02X\n",srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); + srb->pdata=(uchar *)ptr; + return 0; +} + +static int usb_test_unit_ready(ccb *srb,struct us_data *ss) +{ + int retries = 10; + + do { + memset(&srb->cmd[0],0,12); + srb->cmd[0]=SCSI_TST_U_RDY; + srb->cmd[1]=srb->lun<<5; + srb->datalen=0; + srb->cmdlen=12; + if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) { + return 0; + } + usb_request_sense (srb, ss); + wait_ms (100); + } while(retries--); + + return -1; +} + +static int usb_read_capacity(ccb *srb,struct us_data *ss) +{ + int retry; + retry = 3; /* retries */ + do { + memset(&srb->cmd[0],0,12); + srb->cmd[0]=SCSI_RD_CAPAC; + srb->cmd[1]=srb->lun<<5; + srb->datalen=8; + srb->cmdlen=12; + if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) { + return 0; + } + } while(retry--); + + return -1; +} + +static int usb_read_10(ccb *srb,struct us_data *ss, unsigned long start, unsigned short blocks) +{ + memset(&srb->cmd[0],0,12); + srb->cmd[0]=SCSI_READ10; + srb->cmd[1]=srb->lun<<5; + srb->cmd[2]=((unsigned char) (start>>24))&0xff; + srb->cmd[3]=((unsigned char) (start>>16))&0xff; + srb->cmd[4]=((unsigned char) (start>>8))&0xff; + srb->cmd[5]=((unsigned char) (start))&0xff; + srb->cmd[7]=((unsigned char) (blocks>>8))&0xff; + srb->cmd[8]=(unsigned char) blocks & 0xff; + srb->cmdlen=12; + USB_STOR_PRINTF("read10: start %lx blocks %x\n",start,blocks); + return ss->transport(srb,ss); +} + + +#define USB_MAX_READ_BLK 20 + +unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer) +{ + unsigned long start,blks, buf_addr; + unsigned short smallblks; + struct usb_device *dev; + int retry,i; + ccb *srb = &usb_ccb; + + if (blkcnt == 0) + return 0; + + device &= 0xff; + /* Setup device + */ + USB_STOR_PRINTF("\nusb_read: dev %d \n",device); + dev=NULL; + for(i=0;idevnum==usb_dev_desc[device].target) + break; + } + + usb_disable_asynch(1); /* asynch transfer not allowed */ + srb->lun=usb_dev_desc[device].lun; + buf_addr=(unsigned long)buffer; + start=blknr; + blks=blkcnt; + if(usb_test_unit_ready(srb,(struct us_data *)dev->privptr)) { + printf("Device NOT ready\n Request Sense returned %02X %02X %02X\n", + srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); + return 0; + } + USB_STOR_PRINTF("\nusb_read: dev %d startblk %lx, blccnt %lx buffer %lx\n",device,start,blks, buf_addr); + do { + retry=2; + srb->pdata=(unsigned char *)buf_addr; + if(blks>USB_MAX_READ_BLK) { + smallblks=USB_MAX_READ_BLK; + } else { + smallblks=(unsigned short) blks; + } +retry_it: + if(smallblks==USB_MAX_READ_BLK) + usb_show_progress(); + srb->datalen=usb_dev_desc[device].blksz * smallblks; + srb->pdata=(unsigned char *)buf_addr; + if(usb_read_10(srb,(struct us_data *)dev->privptr, start, smallblks)) { + USB_STOR_PRINTF("Read ERROR\n"); + usb_request_sense(srb,(struct us_data *)dev->privptr); + if(retry--) + goto retry_it; + blkcnt-=blks; + break; + } + start+=smallblks; + blks-=smallblks; + buf_addr+=srb->datalen; + } while(blks!=0); + USB_STOR_PRINTF("usb_read: end startblk %lx, blccnt %x buffer %lx\n",start,smallblks,buf_addr); + usb_disable_asynch(0); /* asynch transfer allowed */ + if(blkcnt>=USB_MAX_READ_BLK) + printf("\n"); + return(blkcnt); +} + + +/* Probe to see if a new device is actually a Storage device */ +int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data *ss) +{ + struct usb_interface_descriptor *iface; + int i; + unsigned int flags = 0; + + int protocol = 0; + int subclass = 0; + + /* let's examine the device now */ + iface = &dev->config.if_desc[ifnum]; + +#if 0 + /* this is the place to patch some storage devices */ + USB_STOR_PRINTF("iVendor %X iProduct %X\n",dev->descriptor.idVendor,dev->descriptor.idProduct); + if ((dev->descriptor.idVendor) == 0x066b && (dev->descriptor.idProduct) == 0x0103) { + USB_STOR_PRINTF("patched for E-USB\n"); + protocol = US_PR_CB; + subclass = US_SC_UFI; /* an assumption */ + } +#endif + + if (dev->descriptor.bDeviceClass != 0 || + iface->bInterfaceClass != USB_CLASS_MASS_STORAGE || + iface->bInterfaceSubClass < US_SC_MIN || + iface->bInterfaceSubClass > US_SC_MAX) { + /* if it's not a mass storage, we go no further */ + return 0; + } + + memset(ss, 0, sizeof(struct us_data)); + + /* At this point, we know we've got a live one */ + USB_STOR_PRINTF("\n\nUSB Mass Storage device detected\n"); + + /* Initialize the us_data structure with some useful info */ + ss->flags = flags; + ss->ifnum = ifnum; + ss->pusb_dev = dev; + ss->attention_done = 0; + + /* If the device has subclass and protocol, then use that. Otherwise, + * take data from the specific interface. + */ + if (subclass) { + ss->subclass = subclass; + ss->protocol = protocol; + } else { + ss->subclass = iface->bInterfaceSubClass; + ss->protocol = iface->bInterfaceProtocol; + } + + /* set the handler pointers based on the protocol */ + USB_STOR_PRINTF("Transport: "); + switch (ss->protocol) { + case US_PR_CB: + USB_STOR_PRINTF("Control/Bulk\n"); + ss->transport = usb_stor_CB_transport; + ss->transport_reset = usb_stor_CB_reset; + break; + + case US_PR_CBI: + USB_STOR_PRINTF("Control/Bulk/Interrupt\n"); + ss->transport = usb_stor_CB_transport; + ss->transport_reset = usb_stor_CB_reset; + break; + case US_PR_BULK: + USB_STOR_PRINTF("Bulk/Bulk/Bulk\n"); + ss->transport = usb_stor_BBB_transport; + ss->transport_reset = usb_stor_BBB_reset; + break; + default: + printf("USB Storage Transport unknown / not yet implemented\n"); + return 0; + break; + } + + /* + * We are expecting a minimum of 2 endpoints - in and out (bulk). + * An optional interrupt is OK (necessary for CBI protocol). + * We will ignore any others. + */ + for (i = 0; i < iface->bNumEndpoints; i++) { + /* is it an BULK endpoint? */ + if ((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) + == USB_ENDPOINT_XFER_BULK) { + if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) + ss->ep_in = iface->ep_desc[i].bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + else + ss->ep_out = iface->ep_desc[i].bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + } + + /* is it an interrupt endpoint? */ + if ((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) + == USB_ENDPOINT_XFER_INT) { + ss->ep_int = iface->ep_desc[i].bEndpointAddress & + USB_ENDPOINT_NUMBER_MASK; + ss->irqinterval = iface->ep_desc[i].bInterval; + } + } + USB_STOR_PRINTF("Endpoints In %d Out %d Int %d\n", + ss->ep_in, ss->ep_out, ss->ep_int); + + /* Do some basic sanity checks, and bail if we find a problem */ + if (usb_set_interface(dev, iface->bInterfaceNumber, 0) || + !ss->ep_in || !ss->ep_out || + (ss->protocol == US_PR_CBI && ss->ep_int == 0)) { + USB_STOR_PRINTF("Problems with device\n"); + return 0; + } + /* set class specific stuff */ + /* We only handle certain protocols. Currently, these are + * the only ones. + * The SFF8070 accepts the requests used in u-boot + */ + if (ss->subclass != US_SC_UFI && ss->subclass != US_SC_SCSI && + ss->subclass != US_SC_8070) { + printf("Sorry, protocol %d not yet supported.\n",ss->subclass); + return 0; + } + if(ss->ep_int) { /* we had found an interrupt endpoint, prepare irq pipe */ + /* set up the IRQ pipe and handler */ + + ss->irqinterval = (ss->irqinterval > 0) ? ss->irqinterval : 255; + ss->irqpipe = usb_rcvintpipe(ss->pusb_dev, ss->ep_int); + ss->irqmaxp = usb_maxpacket(dev, ss->irqpipe); + dev->irq_handle=usb_stor_irq; + } + dev->privptr=(void *)ss; + return 1; +} + +int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t *dev_desc) +{ + unsigned char perq,modi; + unsigned long cap[2]; + unsigned long *capacity,*blksz; + ccb *pccb = &usb_ccb; + + /* for some reasons a couple of devices would not survive this reset */ + if ( + /* Sony USM256E */ + (dev->descriptor.idVendor == 0x054c && + dev->descriptor.idProduct == 0x019e) + + || + /* USB007 Mini-USB2 Flash Drive */ + (dev->descriptor.idVendor == 0x066f && + dev->descriptor.idProduct == 0x2010) + ) + USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n"); + else + ss->transport_reset(ss); + + pccb->pdata = usb_stor_buf; + + dev_desc->target = dev->devnum; + pccb->lun = dev_desc->lun; + USB_STOR_PRINTF(" address %d\n",dev_desc->target); + + if(usb_inquiry(pccb,ss)) + return -1; + + perq = usb_stor_buf[0]; + modi = usb_stor_buf[1]; + if((perq & 0x1f) == 0x1f) { + return 0; /* skip unknown devices */ + } + if((modi&0x80) == 0x80) {/* drive is removable */ + dev_desc->removable = 1; + } + memcpy(&dev_desc->vendor[0], &usb_stor_buf[8], 8); + memcpy(&dev_desc->product[0], &usb_stor_buf[16], 16); + memcpy(&dev_desc->revision[0], &usb_stor_buf[32], 4); + dev_desc->vendor[8] = 0; + dev_desc->product[16] = 0; + dev_desc->revision[4] = 0; + USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]); + if(usb_test_unit_ready(pccb,ss)) { + printf("Device NOT ready\n Request Sense returned %02X %02X %02X\n",pccb->sense_buf[2],pccb->sense_buf[12],pccb->sense_buf[13]); + if(dev_desc->removable == 1) { + dev_desc->type = perq; + return 1; + } + else + return 0; + } + pccb->pdata = (unsigned char *)&cap[0]; + memset(pccb->pdata,0,8); + if(usb_read_capacity(pccb,ss) != 0) { + printf("READ_CAP ERROR\n"); + cap[0] = 2880; + cap[1] = 0x200; + } + USB_STOR_PRINTF("Read Capacity returns: 0x%lx, 0x%lx\n",cap[0],cap[1]); +#if 0 + if(cap[0]>(0x200000 * 10)) /* greater than 10 GByte */ + cap[0]>>=16; +#endif +#ifdef LITTLEENDIAN + cap[0] = ((unsigned long)( + (((unsigned long)(cap[0]) & (unsigned long)0x000000ffUL) << 24) | + (((unsigned long)(cap[0]) & (unsigned long)0x0000ff00UL) << 8) | + (((unsigned long)(cap[0]) & (unsigned long)0x00ff0000UL) >> 8) | + (((unsigned long)(cap[0]) & (unsigned long)0xff000000UL) >> 24) )); + cap[1] = ((unsigned long)( + (((unsigned long)(cap[1]) & (unsigned long)0x000000ffUL) << 24) | + (((unsigned long)(cap[1]) & (unsigned long)0x0000ff00UL) << 8) | + (((unsigned long)(cap[1]) & (unsigned long)0x00ff0000UL) >> 8) | + (((unsigned long)(cap[1]) & (unsigned long)0xff000000UL) >> 24) )); +#endif + /* this assumes bigendian! */ + cap[0] += 1; + capacity = &cap[0]; + blksz = &cap[1]; + USB_STOR_PRINTF("Capacity = 0x%lx, blocksz = 0x%lx\n",*capacity,*blksz); + dev_desc->lba = *capacity; + dev_desc->blksz = *blksz; + dev_desc->type = perq; + USB_STOR_PRINTF(" address %d\n",dev_desc->target); + USB_STOR_PRINTF("partype: %d\n",dev_desc->part_type); + + init_part(dev_desc); + + USB_STOR_PRINTF("partype: %d\n",dev_desc->part_type); + return 1; +} + +#endif /* CONFIG_USB_STORAGE */ +#endif /* CFG_CMD_USB */ diff --git a/common/virtex2.c b/common/virtex2.c new file mode 100644 index 0000000..b5dc366 --- /dev/null +++ b/common/virtex2.c @@ -0,0 +1,557 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Configuration support for Xilinx Virtex2 devices. Based + * on spartan2.c (Rich Ireland, rireland@enterasys.com). + */ + +#include +#include + +#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2)) + +#if 0 +#define FPGA_DEBUG +#endif + +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* + * If the SelectMap interface can be overrun by the processor, define + * CFG_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration + * file and add board-specific support for checking BUSY status. By default, + * assume that the SelectMap interface cannot be overrun. + */ +#ifndef CFG_FPGA_CHECK_BUSY +#undef CFG_FPGA_CHECK_BUSY +#endif + +#ifndef CONFIG_FPGA_DELAY +#define CONFIG_FPGA_DELAY() +#endif + +#ifndef CFG_FPGA_PROG_FEEDBACK +#define CFG_FPGA_PROG_FEEDBACK +#endif + +/* + * Don't allow config cycle to be interrupted + */ +#ifndef CFG_FPGA_CHECK_CTRLC +#undef CFG_FPGA_CHECK_CTRLC +#endif + +/* + * Check for errors during configuration by default + */ +#ifndef CFG_FPGA_CHECK_ERROR +#define CFG_FPGA_CHECK_ERROR +#endif + +/* + * The default timeout in mS for INIT_B to deassert after PROG_B has + * been deasserted. Per the latest Virtex II Handbook (page 347), the + * max time from PORG_B deassertion to INIT_B deassertion is 4uS per + * data frame for the XC2V8000. The XC2V8000 has 2860 data frames + * which yields 11.44 mS. So let's make it bigger in order to handle + * an XC2V1000, if anyone can ever get ahold of one. + */ +#ifndef CFG_FPGA_WAIT_INIT +#define CFG_FPGA_WAIT_INIT CFG_HZ/2 /* 500 ms */ +#endif + +/* + * The default timeout for waiting for BUSY to deassert during configuration. + * This is normally not necessary since for most reasonable configuration + * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. + */ +#ifndef CFG_FPGA_WAIT_BUSY +#define CFG_FPGA_WAIT_BUSY CFG_HZ/200 /* 5 ms*/ +#endif + +/* Default timeout for waiting for FPGA to enter operational mode after + * configuration data has been written. + */ +#ifndef CFG_FPGA_WAIT_CONFIG +#define CFG_FPGA_WAIT_CONFIG CFG_HZ/5 /* 200 ms */ +#endif + +static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset); + +static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset); + +int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case slave_serial: + PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); + ret_val = Virtex2_ss_load (desc, buf, bsize); + break; + + case slave_selectmap: + PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); + ret_val = Virtex2_ssm_load (desc, buf, bsize); + break; + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + return ret_val; +} + +int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case slave_serial: + PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); + ret_val = Virtex2_ss_dump (desc, buf, bsize); + break; + + case slave_parallel: + PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); + ret_val = Virtex2_ssm_dump (desc, buf, bsize); + break; + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + return ret_val; +} + +int Virtex2_info (Xilinx_desc * desc) +{ + return FPGA_SUCCESS; +} + +int Virtex2_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; + + if (desc->family != Xilinx_Virtex2) { + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + return FPGA_FAIL; + } else + switch (desc->iface) { + case slave_serial: + ret_val = Virtex2_ss_reloc (desc, reloc_offset); + break; + + case slave_selectmap: + ret_val = Virtex2_ssm_reloc (desc, reloc_offset); + break; + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + return ret_val; +} + +/* + * Virtex-II Slave SelectMap configuration loader. Configuration via + * SelectMap is as follows: + * 1. Set the FPGA's PROG_B line low. + * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high. + * 3. Write data to the SelectMap port. If INIT_B goes low at any time + * this process, a configuration error (most likely CRC failure) has + * ocurred. At this point a status word may be read from the + * SelectMap interface to determine the source of the problem (You + * could, for instance, put this in your 'abort' function handler). + * 4. After all data has been written, test the state of the FPGA + * INIT_B and DONE lines. If both are high, configuration has + * succeeded. Congratulations! + */ +static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + + PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", + __FUNCTION__, __LINE__, fn); + + if (fn) { + size_t bytecount = 0; + unsigned char *data = (unsigned char *) buf; + int cookie = desc->cookie; + unsigned long ts; + + /* Gotta split this one up (so the stack won't blow??) */ + PRINTF ("%s:%d: Function Table:\n" + " base 0x%p\n" + " struct 0x%p\n" + " pre 0x%p\n" + " prog 0x%p\n" + " init 0x%p\n" + " error 0x%p\n", + __FUNCTION__, __LINE__, + &fn, fn, fn->pre, fn->pgm, fn->init, fn->err); + PRINTF (" clock 0x%p\n" + " cs 0x%p\n" + " write 0x%p\n" + " rdata 0x%p\n" + " wdata 0x%p\n" + " busy 0x%p\n" + " abort 0x%p\n" + " post 0x%p\n\n", + fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, + fn->busy, fn->abort, fn->post); + +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("Initializing FPGA Device %d...\n", cookie); +#endif + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) { + (*fn->pre) (cookie); + } + + /* + * Assert the program line. The minimum pulse width for + * Virtex II devices is 300 nS (Tprogram parameter in datasheet). + * There is no maximum value for the pulse width. Check to make + * sure that INIT_B goes low after assertion of PROG_B + */ + (*fn->pgm) (TRUE, TRUE, cookie); + udelay (10); + ts = get_timer (0); + do { + if (get_timer (ts) > CFG_FPGA_WAIT_INIT) { + printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" + " to assert.\n", __FUNCTION__, __LINE__, + CFG_FPGA_WAIT_INIT); + (*fn->abort) (cookie); + return FPGA_FAIL; + } + } while (!(*fn->init) (cookie)); + + (*fn->pgm) (FALSE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); + + /* + * Start a timer and wait for INIT_B to go high + */ + ts = get_timer (0); + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT_INIT) { + printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" + " to deassert.\n", __FUNCTION__, __LINE__, + CFG_FPGA_WAIT_INIT); + (*fn->abort) (cookie); + return FPGA_FAIL; + } + } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); + + (*fn->wr) (TRUE, TRUE, cookie); + (*fn->cs) (TRUE, TRUE, cookie); + + udelay (10000); + + /* + * Load the data byte by byte + */ + while (bytecount < bsize) { +#ifdef CFG_FPGA_CHECK_CTRLC + if (ctrlc ()) { + (*fn->abort) (cookie); + return FPGA_FAIL; + } +#endif + + if ((*fn->done) (cookie) == FPGA_SUCCESS) { + PRINTF ("%s:%d:done went active early, bytecount = %d\n", + __FUNCTION__, __LINE__, bytecount); + break; + } + +#ifdef CFG_FPGA_CHECK_ERROR + if ((*fn->init) (cookie)) { + printf ("\n%s:%d: ** Error: INIT asserted during" + " configuration\n", __FUNCTION__, __LINE__); + printf ("%d = buffer offset, %d = buffer size\n", + bytecount, bsize); + (*fn->abort) (cookie); + return FPGA_FAIL; + } +#endif + + (*fn->wdata) (data[bytecount++], TRUE, cookie); + CONFIG_FPGA_DELAY (); + + /* + * Cycle the clock pin + */ + (*fn->clk) (FALSE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + (*fn->clk) (TRUE, TRUE, cookie); + +#ifdef CFG_FPGA_CHECK_BUSY + ts = get_timer (0); + while ((*fn->busy) (cookie)) { + if (get_timer (ts) > CFG_FPGA_WAIT_BUSY) { + printf ("%s:%d: ** Timeout after %d ticks waiting for" + " BUSY to deassert\n", + __FUNCTION__, __LINE__, CFG_FPGA_WAIT_BUSY); + (*fn->abort) (cookie); + return FPGA_FAIL; + } + } +#endif + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc ('.'); +#endif + } + + /* + * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. + */ + CONFIG_FPGA_DELAY (); + (*fn->cs) (FALSE, TRUE, cookie); + (*fn->wr) (FALSE, TRUE, cookie); + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc ('\n'); +#endif + + /* + * Check for successful configuration. FPGA INIT_B and DONE should + * both be high upon successful configuration. + */ + ts = get_timer (0); + ret_val = FPGA_SUCCESS; + while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) { + if (get_timer (ts) > CFG_FPGA_WAIT_CONFIG) { + printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to" + "assert and INIT to deassert\n", + __FUNCTION__, __LINE__, CFG_FPGA_WAIT_CONFIG); + (*fn->abort) (cookie); + ret_val = FPGA_FAIL; + break; + } + } + + if (ret_val == FPGA_SUCCESS) { +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("Initialization of FPGA device %d complete\n", cookie); +#endif + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) { + (*fn->post) (cookie); + } + } else { +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("** Initialization of FPGA device %d FAILED\n", + cookie); +#endif + } + } else { + printf ("%s:%d: NULL Interface function table!\n", + __FUNCTION__, __LINE__); + } + return ret_val; +} + +/* + * Read the FPGA configuration data + */ +static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + + if (fn) { + unsigned char *data = (unsigned char *) buf; + size_t bytecount = 0; + int cookie = desc->cookie; + + printf ("Starting Dump of FPGA Device %d...\n", cookie); + + (*fn->cs) (TRUE, TRUE, cookie); + (*fn->clk) (TRUE, TRUE, cookie); + + while (bytecount < bsize) { +#ifdef CFG_FPGA_CHECK_CTRLC + if (ctrlc ()) { + (*fn->abort) (cookie); + return FPGA_FAIL; + } +#endif + /* + * Cycle the clock and read the data + */ + (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (TRUE, TRUE, cookie); + (*fn->rdata) (&(data[bytecount++]), cookie); +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc ('.'); +#endif + } + + /* + * Deassert CS_B and cycle the clock to deselect the device. + */ + (*fn->cs) (FALSE, FALSE, cookie); + (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (TRUE, TRUE, cookie); + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc ('\n'); +#endif + puts ("Done.\n"); + } else { + printf ("%s:%d: NULL Interface function table!\n", + __FUNCTION__, __LINE__); + } + return ret_val; +} + +/* + * Relocate the addresses in the function table from FLASH (or ROM, + * or whatever) to RAM. + */ +static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + ulong addr; + int ret_val = FPGA_FAIL; + Xilinx_Virtex2_Slave_SelectMap_fns *fn_r, *fn = + (Xilinx_Virtex2_Slave_SelectMap_fns *) (desc->iface_fns); + + if (fn) { + /* + * Get the relocated table address + */ + addr = (ulong) fn + reloc_offset; + fn_r = (Xilinx_Virtex2_Slave_SelectMap_fns *) addr; + + /* + * Check to see if the table has already been relocated. If not, do + * a sanity check to make sure there is a faithful copy of the + * FLASH based function table in RAM, then adjust the table. + */ + if (!fn_r->relocated) { + if (memcmp + (fn_r, fn, sizeof (Xilinx_Virtex2_Slave_SelectMap_fns)) + == 0) { + desc->iface_fns = fn_r; + } else { + PRINTF ("%s:%d: Invalid function table at 0x%p\n", + __FUNCTION__, __LINE__, fn_r); + return FPGA_FAIL; + } + + PRINTF ("%s:%d: Relocating descriptor at 0x%p\n", + __FUNCTION__, __LINE__, desc); + + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; + addr = (ulong) (fn->pgm) + reloc_offset; + fn_r->pgm = (Xilinx_pgm_fn) addr; + addr = (ulong) (fn->init) + reloc_offset; + fn_r->init = (Xilinx_init_fn) addr; + addr = (ulong) (fn->done) + reloc_offset; + fn_r->done = (Xilinx_done_fn) addr; + addr = (ulong) (fn->err) + reloc_offset; + fn_r->err = (Xilinx_err_fn) addr; + addr = (ulong) (fn->clk) + reloc_offset; + fn_r->clk = (Xilinx_clk_fn) addr; + addr = (ulong) (fn->cs) + reloc_offset; + fn_r->cs = (Xilinx_cs_fn) addr; + addr = (ulong) (fn->wr) + reloc_offset; + fn_r->wr = (Xilinx_wr_fn) addr; + addr = (ulong) (fn->rdata) + reloc_offset; + fn_r->rdata = (Xilinx_rdata_fn) addr; + addr = (ulong) (fn->wdata) + reloc_offset; + fn_r->wdata = (Xilinx_wdata_fn) addr; + addr = (ulong) (fn->busy) + reloc_offset; + fn_r->busy = (Xilinx_busy_fn) addr; + addr = (ulong) (fn->abort) + reloc_offset; + fn_r->abort = (Xilinx_abort_fn) addr; + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Xilinx_post_fn) addr; + fn_r->relocated = TRUE; + } else { + printf ("%s:%d: Function table @0x%p has already been relocated\n", __FUNCTION__, __LINE__, fn_r); + desc->iface_fns = fn_r; + } + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + return ret_val; +} + +static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); + return FPGA_FAIL; +} + +static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); + return FPGA_FAIL; +} + +static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; + Xilinx_Virtex2_Slave_Serial_fns *fn = + (Xilinx_Virtex2_Slave_Serial_fns *) (desc->iface_fns); + + if (fn) { + printf ("%s:%d: Slave Serial Loading is unsupported\n", + __FUNCTION__, __LINE__); + } else { + printf ("%s:%d: NULL Interface function table!\n", + __FUNCTION__, __LINE__); + } + return ret_val; +} +#endif + +/* vim: set ts=4 tw=78: */ diff --git a/common/xilinx.c b/common/xilinx.c new file mode 100644 index 0000000..e03e78c --- /dev/null +++ b/common/xilinx.c @@ -0,0 +1,311 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Xilinx FPGA support + */ + +#include +#include +#include +#include + +#if (CONFIG_FPGA & CFG_FPGA_XILINX) + +#if 0 +#define FPGA_DEBUG +#endif + +/* Define FPGA_DEBUG to get debug printf's */ +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* Local Static Functions */ +static int xilinx_validate (Xilinx_desc * desc, char *fn); + +/* ------------------------------------------------------------------------- */ + +int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (!xilinx_validate (desc, (char *)__FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } else + switch (desc->family) { + case Xilinx_Spartan2: +#if (CONFIG_FPGA & CFG_SPARTAN2) + PRINTF ("%s: Launching the Spartan-II Loader...\n", + __FUNCTION__); + ret_val = Spartan2_load (desc, buf, bsize); +#else + printf ("%s: No support for Spartan-II devices.\n", + __FUNCTION__); +#endif + break; + case Xilinx_Spartan3: +#if (CONFIG_FPGA & CFG_SPARTAN3) + PRINTF ("%s: Launching the Spartan-III Loader...\n", + __FUNCTION__); + ret_val = Spartan3_load (desc, buf, bsize); +#else + printf ("%s: No support for Spartan-III devices.\n", + __FUNCTION__); +#endif + break; + case Xilinx_Virtex2: +#if (CONFIG_FPGA & CFG_VIRTEX2) + PRINTF ("%s: Launching the Virtex-II Loader...\n", + __FUNCTION__); + ret_val = Virtex2_load (desc, buf, bsize); +#else + printf ("%s: No support for Virtex-II devices.\n", + __FUNCTION__); +#endif + break; + + default: + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + } + + return ret_val; +} + +int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (!xilinx_validate (desc, (char *)__FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } else + switch (desc->family) { + case Xilinx_Spartan2: +#if (CONFIG_FPGA & CFG_SPARTAN2) + PRINTF ("%s: Launching the Spartan-II Reader...\n", + __FUNCTION__); + ret_val = Spartan2_dump (desc, buf, bsize); +#else + printf ("%s: No support for Spartan-II devices.\n", + __FUNCTION__); +#endif + break; + case Xilinx_Spartan3: +#if (CONFIG_FPGA & CFG_SPARTAN3) + PRINTF ("%s: Launching the Spartan-III Reader...\n", + __FUNCTION__); + ret_val = Spartan3_dump (desc, buf, bsize); +#else + printf ("%s: No support for Spartan-III devices.\n", + __FUNCTION__); +#endif + break; + case Xilinx_Virtex2: +#if (CONFIG_FPGA & CFG_VIRTEX2) + PRINTF ("%s: Launching the Virtex-II Reader...\n", + __FUNCTION__); + ret_val = Virtex2_dump (desc, buf, bsize); +#else + printf ("%s: No support for Virtex-II devices.\n", + __FUNCTION__); +#endif + break; + + default: + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + } + + return ret_val; +} + +int xilinx_info (Xilinx_desc * desc) +{ + int ret_val = FPGA_FAIL; + + if (xilinx_validate (desc, (char *)__FUNCTION__)) { + printf ("Family: \t"); + switch (desc->family) { + case Xilinx_Spartan2: + printf ("Spartan-II\n"); + break; + case Xilinx_Spartan3: + printf ("Spartan-III\n"); + break; + case Xilinx_Virtex2: + printf ("Virtex-II\n"); + break; + /* Add new family types here */ + default: + printf ("Unknown family type, %d\n", desc->family); + } + + printf ("Interface type:\t"); + switch (desc->iface) { + case slave_serial: + printf ("Slave Serial\n"); + break; + case master_serial: /* Not used */ + printf ("Master Serial\n"); + break; + case slave_parallel: + printf ("Slave Parallel\n"); + break; + case jtag_mode: /* Not used */ + printf ("JTAG Mode\n"); + break; + case slave_selectmap: + printf ("Slave SelectMap Mode\n"); + break; + case master_selectmap: + printf ("Master SelectMap Mode\n"); + break; + /* Add new interface types here */ + default: + printf ("Unsupported interface type, %d\n", desc->iface); + } + + printf ("Device Size: \t%d bytes\n" + "Cookie: \t0x%x (%d)\n", + desc->size, desc->cookie, desc->cookie); + + if (desc->iface_fns) { + printf ("Device Function Table @ 0x%p\n", desc->iface_fns); + switch (desc->family) { + case Xilinx_Spartan2: +#if (CONFIG_FPGA & CFG_SPARTAN2) + Spartan2_info (desc); +#else + /* just in case */ + printf ("%s: No support for Spartan-II devices.\n", + __FUNCTION__); +#endif + break; + case Xilinx_Spartan3: +#if (CONFIG_FPGA & CFG_SPARTAN3) + Spartan3_info (desc); +#else + /* just in case */ + printf ("%s: No support for Spartan-III devices.\n", + __FUNCTION__); +#endif + break; + case Xilinx_Virtex2: +#if (CONFIG_FPGA & CFG_VIRTEX2) + Virtex2_info (desc); +#else + /* just in case */ + printf ("%s: No support for Virtex-II devices.\n", + __FUNCTION__); +#endif + break; + /* Add new family types here */ + default: + /* we don't need a message here - we give one up above */ + ; + } + } else + printf ("No Device Function Table.\n"); + + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } + + return ret_val; +} + +int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (!xilinx_validate (desc, (char *)__FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } else + switch (desc->family) { + case Xilinx_Spartan2: +#if (CONFIG_FPGA & CFG_SPARTAN2) + ret_val = Spartan2_reloc (desc, reloc_offset); +#else + printf ("%s: No support for Spartan-II devices.\n", + __FUNCTION__); +#endif + break; + case Xilinx_Spartan3: +#if (CONFIG_FPGA & CFG_SPARTAN3) + ret_val = Spartan3_reloc (desc, reloc_offset); +#else + printf ("%s: No support for Spartan-III devices.\n", + __FUNCTION__); +#endif + break; + case Xilinx_Virtex2: +#if (CONFIG_FPGA & CFG_VIRTEX2) + ret_val = Virtex2_reloc (desc, reloc_offset); +#else + printf ("%s: No support for Virtex-II devices.\n", + __FUNCTION__); +#endif + break; + /* Add new family types here */ + default: + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + } + + return ret_val; +} + + +/* ------------------------------------------------------------------------- */ + +static int xilinx_validate (Xilinx_desc * desc, char *fn) +{ + int ret_val = FALSE; + + if (desc) { + if ((desc->family > min_xilinx_type) && + (desc->family < max_xilinx_type)) { + if ((desc->iface > min_xilinx_iface_type) && + (desc->iface < max_xilinx_iface_type)) { + if (desc->size) { + ret_val = TRUE; + } else + printf ("%s: NULL part size\n", fn); + } else + printf ("%s: Invalid Interface type, %d\n", + fn, desc->iface); + } else + printf ("%s: Invalid family type, %d\n", fn, desc->family); + } else + printf ("%s: NULL descriptor!\n", fn); + + return ret_val; +} + +#endif /* CONFIG_FPGA & CFG_FPGA_XILINX */ diff --git a/config.mk b/config.mk new file mode 100644 index 0000000..d85ac36 --- /dev/null +++ b/config.mk @@ -0,0 +1,190 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +# clean the slate ... +PLATFORM_RELFLAGS = +PLATFORM_CPPFLAGS = +PLATFORM_LDFLAGS = + +# +# When cross-compiling on NetBSD, we have to define __PPC__ or else we +# will pick up a va_list declaration that is incompatible with the +# actual argument lists emitted by the compiler. +# +# [Tested on NetBSD/i386 1.5 + cross-powerpc-netbsd-1.3] + +ifeq ($(ARCH),ppc) +ifeq ($(CROSS_COMPILE),powerpc-netbsd-) +PLATFORM_CPPFLAGS+= -D__PPC__ +endif +ifeq ($(CROSS_COMPILE),powerpc-openbsd-) +PLATFORM_CPPFLAGS+= -D__PPC__ +endif +endif + +ifeq ($(ARCH),arm) +ifeq ($(CROSS_COMPILE),powerpc-netbsd-) +PLATFORM_CPPFLAGS+= -D__ARM__ +endif +ifeq ($(CROSS_COMPILE),powerpc-openbsd-) +PLATFORM_CPPFLAGS+= -D__ARM__ +endif +endif + +ifdef ARCH +sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules +endif +ifdef CPU +sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules +endif +ifdef SOC +sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk # include SoC specific rules +endif +ifdef VENDOR +BOARDDIR = $(VENDOR)/$(BOARD) +else +BOARDDIR = $(BOARD) +endif +ifdef BOARD +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules +endif + +######################################################################### + +CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi ; fi) + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +HOSTCC = cc +else +HOSTCC = gcc +endif +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer +HOSTSTRIP = strip + +######################################################################### +# +# Option checker (courtesy linux kernel) to ensure +# only supported compiler options are used +# +cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \ + > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;) + +# +# Include the make variables (CC, etc...) +# +AS = $(CROSS_COMPILE)as +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +RANLIB = $(CROSS_COMPILE)RANLIB + +RELFLAGS= $(PLATFORM_RELFLAGS) +DBGFLAGS= -g #-DDEBUG +OPTFLAGS= -Os #-fomit-frame-pointer +ifndef LDSCRIPT +#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds +endif +OBJCFLAGS += --gap-fill=0xff + +gccincdir := $(shell $(CC) -print-file-name=include) + +CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ + -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \ + -I$(TOPDIR)/include \ + -fno-builtin -ffreestanding -nostdinc -isystem \ + $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) + +ifdef BUILD_TAG +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \ + -DBUILD_TAG='"$(BUILD_TAG)"' +else +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes +endif + +# avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9) +# this option have to be placed behind -Wall -- that's why it is here +ifeq ($(ARCH),nios) +ifeq ($(findstring 2.9,$(shell $(CC) --version)),2.9) +CFLAGS := $(CPPFLAGS) -Wall -Wno-trigraphs +endif +endif + +AFLAGS_DEBUG := -Wa,-gstabs +AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) + +LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) + +# Location of a usable BFD library, where we define "usable" as +# "built for ${HOST}, supports ${TARGET}". Sensible values are +# - When cross-compiling: the root of the cross-environment +# - Linux/ppc (native): /usr +# - NetBSD/ppc (native): you lose ... (must extract these from the +# binutils build directory, plus the native and U-Boot include +# files don't like each other) +# +# So far, this is used only by tools/gdb/Makefile. + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +BFD_ROOT_DIR = /usr/local/tools +else +ifeq ($(HOSTARCH),$(ARCH)) +# native +BFD_ROOT_DIR = /usr +else +#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 +#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 +BFD_ROOT_DIR = /opt/powerpc +endif +endif + +ifeq ($(PCI_CLOCK),PCI_66M) +CFLAGS := $(CFLAGS) -DPCI_66M +endif + +######################################################################### + +export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ + AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \ + MAKE +export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS + +######################################################################### + +%.s: %.S + $(CPP) $(AFLAGS) -o $@ $(CURDIR)/$< +%.o: %.S + $(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$< +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +######################################################################### diff --git a/cpu/74xx_7xx/Makefile b/cpu/74xx_7xx/Makefile new file mode 100644 index 0000000..0e10d3a --- /dev/null +++ b/cpu/74xx_7xx/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001 +# Josh Huber , Mission Critical Linux, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +ASOBJS = cache.o kgdb.o io.o +OBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o + +all: .depend $(START) $(ASOBJS) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(ASOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S new file mode 100644 index 0000000..a793d79 --- /dev/null +++ b/cpu/74xx_7xx/cache.S @@ -0,0 +1,381 @@ +#include +#include <74xx_7xx.h> +#include + +#include +#include + +#include +#include + +#ifndef CACHE_LINE_SIZE +# define CACHE_LINE_SIZE L1_CACHE_BYTES +#endif + +#if CACHE_LINE_SIZE == 128 +#define LG_CACHE_LINE_SIZE 7 +#elif CACHE_LINE_SIZE == 32 +#define LG_CACHE_LINE_SIZE 5 +#elif CACHE_LINE_SIZE == 16 +#define LG_CACHE_LINE_SIZE 4 +#elif CACHE_LINE_SIZE == 8 +#define LG_CACHE_LINE_SIZE 3 +#else +# error "Invalid cache line size!" +#endif + +/* + * Invalidate L1 instruction cache. + */ +_GLOBAL(invalidate_l1_instruction_cache) + mfspr r3,PVR + rlwinm r3,r3,16,16,31 + cmpi 0,r3,1 + beqlr /* for 601, do nothing */ + /* 603/604 processor - use invalidate-all bit in HID0 */ + mfspr r3,HID0 + ori r3,r3,HID0_ICFI + mtspr HID0,r3 + isync + blr + +/* + * Invalidate L1 data cache. + */ +_GLOBAL(invalidate_l1_data_cache) + mfspr r3,HID0 + ori r3,r3,HID0_DCFI + mtspr HID0,r3 + isync + blr + +/* + * Flush data cache. + */ +_GLOBAL(flush_data_cache) + lis r3,0 + lis r5,CACHE_LINE_SIZE +flush: + cmp 0,1,r3,r5 + bge done + lwz r5,0(r3) + lis r5,CACHE_LINE_SIZE + addi r3,r3,0x4 + b flush +done: + blr +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * This is a no-op on the 601. + * + * flush_icache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_icache_range) + mfspr r5,PVR + rlwinm r5,r5,16,16,31 + cmpi 0,r5,1 + beqlr /* for 601, do nothing */ + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,CACHE_LINE_SIZE + bdnz 2b + sync /* additional sync needed on g4 */ + isync + blr +/* + * Write any modified data cache blocks out to memory. + * Does not invalidate the corresponding cache lines (especially for + * any corresponding instruction cache). + * + * clean_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(clean_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 /* align r3 down to cache line */ + subf r4,r3,r4 /* r4 = offset of stop from start of cache line */ + add r4,r4,r5 /* r4 += cache_line_size-1 */ + srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */ + beqlr /* if r4 == 0 return */ + mtctr r4 /* ctr = r4 */ + + sync +1: dcbst 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * + * flush_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + + sync +1: dcbf 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbf's to get to ram */ + blr + +/* + * Like above, but invalidate the D-cache. This is used by the 8xx + * to invalidate the cache so the PPC core doesn't get stale data + * from the CPM (no cache snooping here :-). + * + * invalidate_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(invalidate_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + + sync +1: dcbi 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbi's to get to ram */ + blr + +/* + * Flush a particular page from the data cache to RAM. + * Note: this is necessary because the instruction cache does *not* + * snoop from the data cache. + * This is a no-op on the 601 which has a unified cache. + * + * void __flush_page_to_ram(void *page) + */ +_GLOBAL(__flush_page_to_ram) + mfspr r5,PVR + rlwinm r5,r5,16,16,31 + cmpi 0,r5,1 + beqlr /* for 601, do nothing */ + rlwinm r3,r3,0,0,19 /* Get page base address */ + li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + mtctr r4 + mr r6,r3 +0: dcbst 0,r3 /* Write line to ram */ + addi r3,r3,CACHE_LINE_SIZE + bdnz 0b + sync + mtctr r4 +1: icbi 0,r6 + addi r6,r6,CACHE_LINE_SIZE + bdnz 1b + sync + isync + blr + +/* + * Flush a particular page from the instruction cache. + * Note: this is necessary because the instruction cache does *not* + * snoop from the data cache. + * This is a no-op on the 601 which has a unified cache. + * + * void __flush_icache_page(void *page) + */ +_GLOBAL(__flush_icache_page) + mfspr r5,PVR + rlwinm r5,r5,16,16,31 + cmpi 0,r5,1 + beqlr /* for 601, do nothing */ + li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + mtctr r4 +1: icbi 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync + isync + blr + +/* + * Clear a page using the dcbz instruction, which doesn't cause any + * memory traffic (except to write out any cache lines which get + * displaced). This only works on cacheable memory. + */ +_GLOBAL(clear_page) + li r0,4096/CACHE_LINE_SIZE + mtctr r0 +1: dcbz 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + blr + +/* + * Enable L1 Instruction cache + */ +_GLOBAL(icache_enable) + mfspr r3, HID0 + li r5, HID0_ICFI|HID0_ILOCK + andc r3, r3, r5 + ori r3, r3, HID0_ICE + ori r5, r3, HID0_ICFI + mtspr HID0, r5 + mtspr HID0, r3 + isync + blr + +/* + * Disable L1 Instruction cache + */ +_GLOBAL(icache_disable) + mfspr r3, HID0 + li r5, 0 + ori r5, r5, HID0_ICE + andc r3, r3, r5 + mtspr HID0, r3 + isync + blr + +/* + * Is instruction cache enabled? + */ +_GLOBAL(icache_status) + mfspr r3, HID0 + andi. r3, r3, HID0_ICE + blr + + +_GLOBAL(l1dcache_enable) + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync + blr + +/* + * Enable data cache(s) - L1 and optionally L2 + * Calls l2cache_enable. LR saved in r5 + */ +_GLOBAL(dcache_enable) + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync +#ifdef CFG_L2 + mflr r5 + bl l2cache_enable /* uses r3 and r4 */ + sync + mtlr r5 +#endif + blr + + +/* + * Disable data cache(s) - L1 and optionally L2 + * Calls flush_data_cache and l2cache_disable_no_flush. + * LR saved in r4 + */ +_GLOBAL(dcache_disable) + mflr r4 /* save link register */ + bl flush_data_cache /* uses r3 and r5 */ + sync + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + li r5, HID0_DCE|HID0_DCFI + andc r3, r3, r5 /* no enable, no invalidate */ + mtspr HID0, r3 + sync +#ifdef CFG_L2 + bl l2cache_disable_no_flush /* uses r3 */ +#endif + mtlr r4 /* restore link register */ + blr + +/* + * Is data cache enabled? + */ +_GLOBAL(dcache_status) + mfspr r3, HID0 + andi. r3, r3, HID0_DCE + blr + +/* + * Invalidate L2 cache using L2I and polling L2IP + */ +_GLOBAL(l2cache_invalidate) + sync + oris r3, r3, L2CR_L2I@h + sync + mtspr l2cr, r3 + sync +invl2: + mfspr r3, l2cr + andi. r3, r3, L2CR_L2IP + bne invl2 + /* turn off the global invalidate bit */ + mfspr r3, l2cr + rlwinm r3, r3, 0, 11, 9 + sync + mtspr l2cr, r3 + sync + blr + +/* + * Enable L2 cache + * Calls l2cache_invalidate. LR is saved in r4 + */ +_GLOBAL(l2cache_enable) + mflr r4 /* save link register */ + bl l2cache_invalidate /* uses r3 */ + sync + lis r3, L2_ENABLE@h + ori r3, r3, L2_ENABLE@l + mtspr l2cr, r3 + isync + mtlr r4 /* restore link register */ + blr + +/* + * Disable L2 cache + * Calls flush_data_cache. LR is saved in r4 + */ +_GLOBAL(l2cache_disable) + mflr r4 /* save link register */ + bl flush_data_cache /* uses r3 and r5 */ + sync + mtlr r4 /* restore link register */ +l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ + lis r3, L2_INIT@h + ori r3, r3, L2_INIT@l + mtspr l2cr, r3 + isync + blr diff --git a/cpu/74xx_7xx/config.mk b/cpu/74xx_7xx/config.mk new file mode 100644 index 0000000..417d99f --- /dev/null +++ b/cpu/74xx_7xx/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2001 +# Josh Huber , Mission Critical Linux, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing + +PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -ffixed-r29 -mstring diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c new file mode 100644 index 0000000..629ed66 --- /dev/null +++ b/cpu/74xx_7xx/cpu.c @@ -0,0 +1,284 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * cpu.c + * + * CPU specific code + * + * written or collected and sometimes rewritten by + * Magnus Damm + * + * minor modifications by + * Wolfgang Denk + * + * more modifications by + * Josh Huber + * added support for the 74xx series of cpus + * added support for the 7xx series of cpus + * made the code a little less hard-coded, and more auto-detectish + */ + +#include +#include +#include <74xx_7xx.h> +#include + +#ifdef CONFIG_AMIGAONEG3SE +#include "../board/MAI/AmigaOneG3SE/via686.h" +#include "../board/MAI/AmigaOneG3SE/memio.h" +#endif + +cpu_t +get_cpu_type(void) +{ + uint pvr = get_pvr(); + cpu_t type; + + type = CPU_UNKNOWN; + + switch (PVR_VER(pvr)) { + case 0x000c: + type = CPU_7400; + break; + case 0x0008: + type = CPU_750; + + if (((pvr >> 8) & 0xff) == 0x01) { + type = CPU_750CX; /* old CX (80100 and 8010x?)*/ + } else if (((pvr >> 8) & 0xff) == 0x22) { + type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */ + } else if (((pvr >> 8) & 0xff) == 0x33) { + type = CPU_750CX; /* CXe (83311) */ + } else if (((pvr >> 12) & 0xF) == 0x3) { + type = CPU_755; + } + break; + + case 0x7000: + type = CPU_750FX; + break; + + case 0x7002: + type = CPU_750GX; + break; + + case 0x800C: + type = CPU_7410; + break; + + case 0x8000: + type = CPU_7450; + break; + + case 0x8001: + type = CPU_7455; + break; + + case 0x8002: + type = CPU_7457; + break; + + default: + break; + } + + return type; +} + +/* ------------------------------------------------------------------------- */ + +#if !defined(CONFIG_BAB7xx) +int checkcpu (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uint type = get_cpu_type(); + uint pvr = get_pvr(); + ulong clock = gd->cpu_clk; + char buf[32]; + char *str; + + puts ("CPU: "); + + switch (type) { + case CPU_750CX: + printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"", + (pvr>>8) & 0xf, + pvr & 0xf); + goto PR_CLK; + + case CPU_750: + str = "750"; + break; + + case CPU_750FX: + str = "750FX"; + break; + + case CPU_750GX: + str = "750GX"; + break; + + case CPU_755: + str = "755"; + break; + + case CPU_7400: + str = "MPC7400"; + break; + + case CPU_7410: + str = "MPC7410"; + break; + + case CPU_7450: + str = "MPC7450"; + break; + + case CPU_7455: + str = "MPC7455"; + break; + + case CPU_7457: + str = "MPC7457"; + break; + + default: + printf("Unknown CPU -- PVR: 0x%08x\n", pvr); + return -1; + } + + printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF); +PR_CLK: + printf (" @ %s MHz\n", strmhz(buf, clock)); + + return (0); +} +#endif +/* these two functions are unimplemented currently [josh] */ + +/* -------------------------------------------------------------------- */ +/* L1 i-cache */ + +int +checkicache(void) +{ + return 0; /* XXX */ +} + +/* -------------------------------------------------------------------- */ +/* L1 d-cache */ + +int +checkdcache(void) +{ + return 0; /* XXX */ +} + +/* -------------------------------------------------------------------- */ + +static inline void +soft_restart(unsigned long addr) +{ + /* SRR0 has system reset vector, SRR1 has default MSR value */ + /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ + + __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); + __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); + __asm__ __volatile__ ("mtspr 27, 4"); + __asm__ __volatile__ ("rfi"); + + while(1); /* not reached */ +} + + +#if !defined(CONFIG_PCIPPC2) && \ + !defined(CONFIG_BAB7xx) && \ + !defined(CONFIG_ELPPC) +/* no generic way to do board reset. simply call soft_reset. */ +void +do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + /* flush and disable I/D cache */ + __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); + __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); + __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); + __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 4"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 5"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + +#ifdef CFG_RESET_ADDRESS + addr = CFG_RESET_ADDRESS; +#else + /* + * note: when CFG_MONITOR_BASE points to a RAM address, + * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid + * address. Better pick an address known to be invalid on your + * system and assign it to CFG_RESET_ADDRESS. + */ + addr = CFG_MONITOR_BASE - sizeof (ulong); +#endif + soft_restart(addr); + while(1); /* not reached */ +} +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * For the 7400 the TB clock runs at 1/4 the cpu bus speed. + */ +#ifdef CONFIG_AMIGAONEG3SE +unsigned long get_tbclk(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + return (gd->bus_clk / 4); +} +#else /* ! CONFIG_AMIGAONEG3SE */ + +unsigned long get_tbclk (void) +{ + return CFG_BUS_HZ / 4; +} +#endif /* CONFIG_AMIGAONEG3SE */ +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_WATCHDOG) +#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx) +void +watchdog_reset(void) +{ + +} +#endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */ +#endif /* CONFIG_WATCHDOG */ + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/74xx_7xx/cpu_init.c b/cpu/74xx_7xx/cpu_init.c new file mode 100644 index 0000000..93f180f --- /dev/null +++ b/cpu/74xx_7xx/cpu_init.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * cpu_init.c - low level cpu init + * + * there's really nothing going on here yet. future work area? + */ + +#include +#include <74xx_7xx.h> + +/* + * Breath some life into the CPU... + * + * there's basically nothing to do here since the memory controller + * isn't on the CPU in this case. + */ +void +cpu_init_f (void) +{ + switch (get_cpu_type()) { + case CPU_7450: + case CPU_7455: + case CPU_7457: + /* enable the timebase bit in HID0 */ + set_hid0(get_hid0() | 0x4000000); + break; + default: + /* do nothing */ + break; + } +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r (void) +{ + return (0); +} diff --git a/cpu/74xx_7xx/interrupts.c b/cpu/74xx_7xx/interrupts.c new file mode 100644 index 0000000..f0ea485 --- /dev/null +++ b/cpu/74xx_7xx/interrupts.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * interrupts.c - just enough support for the decrementer/timer + */ + +#include +#include +#include +#include +#include +#include + +int interrupt_init_cpu (unsigned *decrementer_count) +{ +#if defined(DEBUG) && !defined(CONFIG_AMIGAONEG3SE) + printf("interrupt_init: GT main cause reg: %08x:%08x\n", + GTREGREAD(LOW_INTERRUPT_CAUSE_REGISTER), + GTREGREAD(HIGH_INTERRUPT_CAUSE_REGISTER)); + printf("interrupt_init: ethernet cause regs: %08x %08x %08x\n", + GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER), + GTREGREAD(ETHERNET1_INTERRUPT_CAUSE_REGISTER), + GTREGREAD(ETHERNET2_INTERRUPT_CAUSE_REGISTER)); + printf("interrupt_init: ethernet mask regs: %08x %08x %08x\n", + GTREGREAD(ETHERNET0_INTERRUPT_MASK_REGISTER), + GTREGREAD(ETHERNET1_INTERRUPT_MASK_REGISTER), + GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER)); + puts("interrupt_init: setting decrementer_count\n"); +#endif + *decrementer_count = get_tbclk() / CFG_HZ; + + return (0); +} + +/****************************************************************************/ + +/* + * Handle external interrupts + */ +void +external_interrupt(struct pt_regs *regs) +{ + puts("external_interrupt (oops!)\n"); +} + +volatile ulong timestamp = 0; + +/* + * timer_interrupt - gets called when the decrementer overflows, + * with interrupts disabled. + * Trivial implementation - no need to be really accurate. + */ +void +timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} + +/****************************************************************************/ + +/* + * Install and free a interrupt handler. + */ + +void +irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +{ + +} + +void +irq_free_handler(int vec) +{ + +} + +/****************************************************************************/ + +void +do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + puts("IRQ related functions are unimplemented currently.\n"); +} diff --git a/cpu/74xx_7xx/io.S b/cpu/74xx_7xx/io.S new file mode 100644 index 0000000..af2e6d1 --- /dev/null +++ b/cpu/74xx_7xx/io.S @@ -0,0 +1,128 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * Copyright (C) 2002 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/* ------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in16 */ +/* Description: Input 16 bits */ +/* ------------------------------------------------------------------------------- */ + .globl in16 +in16: + lhz r3,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in16r */ +/* Description: Input 16 bits and byte reverse */ +/* ------------------------------------------------------------------------------- */ + .globl in16r +in16r: + lhbrx r3,0,r3 + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/* ------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0(3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in32r */ +/* Description: Input 32 bits and byte reverse */ +/* ------------------------------------------------------------------------------- */ + .globl in32r +in32r: + lwbrx r3,0,r3 + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out16 */ +/* Description: Output 16 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out16 +out16: + sth r4,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out16r */ +/* Description: Byte reverse and output 16 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out16r +out16r: + sthbrx r4,0,r3 + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out32r */ +/* Description: Byte reverse and output 32 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out32r +out32r: + stwbrx r4,0,r3 + sync + blr diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S new file mode 100644 index 0000000..e838513 --- /dev/null +++ b/cpu/74xx_7xx/kgdb.S @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2000 Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307USA + */ + +#include +#include +#include <74xx_7xx.h> +#include + +#include +#include + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + + /* + * cache flushing routines for kgdb + */ + + .globl kgdb_flush_cache_all +kgdb_flush_cache_all: + lis r3,0 + addis r4,r0,0x0040 +kgdb_flush_loop: + lwz r5,0(r3) + addi r3,r3,CFG_CACHELINE_SIZE + cmp 0,0,r3,r4 + bne kgdb_flush_loop + SYNC + mfspr r3,1008 + ori r3,r3,0x8800 + mtspr 1008,r3 + sync + blr + + .globl kgdb_flush_cache_range +kgdb_flush_cache_range: + li r5,CFG_CACHELINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,CFG_CACHELINE_SHIFT + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,CFG_CACHELINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,CFG_CACHELINE_SIZE + bdnz 2b + SYNC + blr + +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c new file mode 100644 index 0000000..f94ff78 --- /dev/null +++ b/cpu/74xx_7xx/speed.c @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include <74xx_7xx.h> +#include + +#ifdef CONFIG_AMIGAONEG3SE +#include "../board/MAI/AmigaOneG3SE/via686.h" +#endif + +static const int hid1_multipliers_x_10[] = { + 25, /* 0000 - 2.5x */ + 75, /* 0001 - 7.5x */ + 70, /* 0010 - 7x */ + 10, /* 0011 - bypass */ + 20, /* 0100 - 2x */ + 65, /* 0101 - 6.5x */ + 100, /* 0110 - 10x */ + 45, /* 0111 - 4.5x */ + 30, /* 1000 - 3x */ + 55, /* 1001 - 5.5x */ + 40, /* 1010 - 4x */ + 50, /* 1011 - 5x */ + 80, /* 1100 - 8x */ + 60, /* 1101 - 6x */ + 35, /* 1110 - 3.5x */ + 0 /* 1111 - off */ +}; + +static const int hid1_fx_multipliers_x_10[] = { + 00, /* 0000 - off */ + 00, /* 0001 - off */ + 10, /* 0010 - bypass */ + 10, /* 0011 - bypass */ + 20, /* 0100 - 2x */ + 25, /* 0101 - 2.5x */ + 30, /* 0110 - 3x */ + 35, /* 0111 - 3.5x */ + 40, /* 1000 - 4x */ + 45, /* 1001 - 4.5x */ + 50, /* 1010 - 5x */ + 55, /* 1011 - 5.5x */ + 60, /* 1100 - 6x */ + 65, /* 1101 - 6.5x */ + 70, /* 1110 - 7x */ + 75, /* 1111 - 7.5 */ + 80, /* 10000 - 8x */ + 85, /* 10001 - 8.5x */ + 90, /* 10010 - 9x */ + 95, /* 10011 - 9.5x */ + 100, /* 10100 - 10x */ + 110, /* 10101 - 11x */ + 120, /* 10110 - 12x */ +}; + + +/* ------------------------------------------------------------------------- */ + +/* + * Measure CPU clock speed (core clock GCLK1, GCLK2) + * + * (Approx. GCLK frequency in Hz) + */ + +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong clock = 0; + + /* calculate the clock frequency based upon the CPU type */ + switch (get_cpu_type()) { + case CPU_7455: + case CPU_7457: + /* + * It is assumed that the PLL_EXT line is zero. + * Make sure division is done before multiplication to prevent 32-bit + * arithmetic overflows which will cause a negative number + */ + clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; + break; + + case CPU_750GX: + case CPU_750FX: + clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; + break; + + case CPU_7450: + case CPU_740: + case CPU_740P: + case CPU_745: + case CPU_750CX: + case CPU_750: + case CPU_750P: + case CPU_755: + case CPU_7400: + case CPU_7410: + /* + * Make sure division is done before multiplication to prevent 32-bit + * arithmetic overflows which will cause a negative number + */ + clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28]; + break; + + case CPU_UNKNOWN: + printf ("get_gclk_freq(): unknown CPU type\n"); + clock = 0; + return (1); + } + + gd->cpu_clk = clock; + gd->bus_clk = CFG_BUS_CLK; + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S new file mode 100644 index 0000000..ff1cce5 --- /dev/null +++ b/cpu/74xx_7xx/start.S @@ -0,0 +1,897 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000,2001,2002 Wolfgang Denk + * Copyright (C) 2001 Josh Huber + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* U-Boot - Startup Code for PowerPC based Embedded Boards + * + * + * The processor starts at 0xfff00100 and the code is executed + * from flash. The code is organized to be at an other address + * in memory, but as long we don't jump around before relocating. + * board_init lies at a quite high address and when the cpu has + * jumped there, everything is ok. + */ +#include +#include <74xx_7xx.h> +#include + +#include +#include + +#include +#include + +#if !defined(CONFIG_DB64360) && \ + !defined(CONFIG_DB64460) && \ + !defined(CONFIG_CPCI750) +#include +#endif + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +/* Machine Check and Recoverable Interr. */ +#define MSR_KERNEL ( MSR_ME | MSR_RI ) + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ + b boot_cold + sync + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + sync + + /* the boot code is located below the exception table */ + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + /* No FPU on MPC8xx. This exception is not supposed to happen. + */ + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + /* + * On the MPC8xx, this is a software emulation interrupt. It + * occurs for all unimplemented and illegal instructions. + */ + STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) + + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) + STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) + STD_EXCEPTION(0x1400, DataTLBError, UnknownException) + + STD_EXCEPTION(0x1500, Reserved5, UnknownException) + STD_EXCEPTION(0x1600, Reserved6, UnknownException) + STD_EXCEPTION(0x1700, Reserved7, UnknownException) + STD_EXCEPTION(0x1800, Reserved8, UnknownException) + STD_EXCEPTION(0x1900, Reserved9, UnknownException) + STD_EXCEPTION(0x1a00, ReservedA, UnknownException) + STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + + STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) + STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) + STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) + STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x2000 + +boot_cold: +boot_warm: + /* disable everything */ + li r0, 0 + mtspr HID0, r0 + sync + mtmsr 0 + bl invalidate_bats + sync + +#ifdef CFG_L2 + /* init the L2 cache */ + addis r3, r0, L2_INIT@h + ori r3, r3, L2_INIT@l + sync + mtspr l2cr, r3 +#endif +#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx) + .long 0x7e00066c + /* + * dssall instruction, gas doesn't have it yet + * ...for altivec, data stream stop all this probably + * isn't needed unless we warm (software) reboot U-Boot + */ +#endif + +#ifdef CFG_L2 + /* invalidate the L2 cache */ + bl l2cache_invalidate + sync +#endif +#ifdef CFG_BOARD_ASM_INIT + /* do early init */ + bl board_asm_init +#endif + + /* + * Calculate absolute address in FLASH and jump there + *------------------------------------------------------*/ + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r3 + blr + +in_flash: + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*------------------------------------------------------*/ + + /* perform low-level init */ + /* sdram init, galileo init, etc */ + /* r3: NHR bit from HID0 */ + + /* setup the bats */ + bl setup_bats + sync + + /* + * Cache must be enabled here for stack-in-cache trick. + * This means we need to enable the BATS. + * This means: + * 1) for the EVB, original gt regs need to be mapped + * 2) need to have an IBAT for the 0xf region, + * we are running there! + * Cache should be turned on after BATs, since by default + * everything is write-through. + * The init-mem BAT can be reused after reloc. The old + * gt-regs BAT can be reused after board_init_f calls + * board_early_init_f (EVB only). + */ +#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) + /* enable address translation */ + bl enable_addr_trans + sync + + /* enable and invalidate the data cache */ + bl l1dcache_enable + sync +#endif +#ifdef CFG_INIT_RAM_LOCK + bl lock_ram_in_cache + sync +#endif + + /* set up the stack pointer in our newly created + * cache-ram (r1) */ + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + GET_GOT /* initialize GOT access */ + + /* run low-level CPU init code (from Flash) */ + bl cpu_init_f + sync + + mr r3, r21 + + /* r3: BOOTFLAG */ + /* run 1st part of board init code (from Flash) */ + bl board_init_f + sync + + /* NOTREACHED */ + + .globl invalidate_bats +invalidate_bats: + /* invalidate BATs */ + mtspr IBAT0U, r0 + mtspr IBAT1U, r0 + mtspr IBAT2U, r0 + mtspr IBAT3U, r0 +#ifdef CONFIG_750FX + mtspr IBAT4U, r0 + mtspr IBAT5U, r0 + mtspr IBAT6U, r0 + mtspr IBAT7U, r0 +#endif + isync + mtspr DBAT0U, r0 + mtspr DBAT1U, r0 + mtspr DBAT2U, r0 + mtspr DBAT3U, r0 +#ifdef CONFIG_750FX + mtspr DBAT4U, r0 + mtspr DBAT5U, r0 + mtspr DBAT6U, r0 + mtspr DBAT7U, r0 +#endif + isync + sync + blr + + /* setup_bats - set them up to some initial state */ + .globl setup_bats +setup_bats: + addis r0, r0, 0x0000 + + /* IBAT 0 */ + addis r4, r0, CFG_IBAT0L@h + ori r4, r4, CFG_IBAT0L@l + addis r3, r0, CFG_IBAT0U@h + ori r3, r3, CFG_IBAT0U@l + mtspr IBAT0L, r4 + mtspr IBAT0U, r3 + isync + + /* DBAT 0 */ + addis r4, r0, CFG_DBAT0L@h + ori r4, r4, CFG_DBAT0L@l + addis r3, r0, CFG_DBAT0U@h + ori r3, r3, CFG_DBAT0U@l + mtspr DBAT0L, r4 + mtspr DBAT0U, r3 + isync + + /* IBAT 1 */ + addis r4, r0, CFG_IBAT1L@h + ori r4, r4, CFG_IBAT1L@l + addis r3, r0, CFG_IBAT1U@h + ori r3, r3, CFG_IBAT1U@l + mtspr IBAT1L, r4 + mtspr IBAT1U, r3 + isync + + /* DBAT 1 */ + addis r4, r0, CFG_DBAT1L@h + ori r4, r4, CFG_DBAT1L@l + addis r3, r0, CFG_DBAT1U@h + ori r3, r3, CFG_DBAT1U@l + mtspr DBAT1L, r4 + mtspr DBAT1U, r3 + isync + + /* IBAT 2 */ + addis r4, r0, CFG_IBAT2L@h + ori r4, r4, CFG_IBAT2L@l + addis r3, r0, CFG_IBAT2U@h + ori r3, r3, CFG_IBAT2U@l + mtspr IBAT2L, r4 + mtspr IBAT2U, r3 + isync + + /* DBAT 2 */ + addis r4, r0, CFG_DBAT2L@h + ori r4, r4, CFG_DBAT2L@l + addis r3, r0, CFG_DBAT2U@h + ori r3, r3, CFG_DBAT2U@l + mtspr DBAT2L, r4 + mtspr DBAT2U, r3 + isync + + /* IBAT 3 */ + addis r4, r0, CFG_IBAT3L@h + ori r4, r4, CFG_IBAT3L@l + addis r3, r0, CFG_IBAT3U@h + ori r3, r3, CFG_IBAT3U@l + mtspr IBAT3L, r4 + mtspr IBAT3U, r3 + isync + + /* DBAT 3 */ + addis r4, r0, CFG_DBAT3L@h + ori r4, r4, CFG_DBAT3L@l + addis r3, r0, CFG_DBAT3U@h + ori r3, r3, CFG_DBAT3U@l + mtspr DBAT3L, r4 + mtspr DBAT3U, r3 + isync + +#ifdef CONFIG_750FX + /* IBAT 4 */ + addis r4, r0, CFG_IBAT4L@h + ori r4, r4, CFG_IBAT4L@l + addis r3, r0, CFG_IBAT4U@h + ori r3, r3, CFG_IBAT4U@l + mtspr IBAT4L, r4 + mtspr IBAT4U, r3 + isync + + /* DBAT 4 */ + addis r4, r0, CFG_DBAT4L@h + ori r4, r4, CFG_DBAT4L@l + addis r3, r0, CFG_DBAT4U@h + ori r3, r3, CFG_DBAT4U@l + mtspr DBAT4L, r4 + mtspr DBAT4U, r3 + isync + + /* IBAT 5 */ + addis r4, r0, CFG_IBAT5L@h + ori r4, r4, CFG_IBAT5L@l + addis r3, r0, CFG_IBAT5U@h + ori r3, r3, CFG_IBAT5U@l + mtspr IBAT5L, r4 + mtspr IBAT5U, r3 + isync + + /* DBAT 5 */ + addis r4, r0, CFG_DBAT5L@h + ori r4, r4, CFG_DBAT5L@l + addis r3, r0, CFG_DBAT5U@h + ori r3, r3, CFG_DBAT5U@l + mtspr DBAT5L, r4 + mtspr DBAT5U, r3 + isync + + /* IBAT 6 */ + addis r4, r0, CFG_IBAT6L@h + ori r4, r4, CFG_IBAT6L@l + addis r3, r0, CFG_IBAT6U@h + ori r3, r3, CFG_IBAT6U@l + mtspr IBAT6L, r4 + mtspr IBAT6U, r3 + isync + + /* DBAT 6 */ + addis r4, r0, CFG_DBAT6L@h + ori r4, r4, CFG_DBAT6L@l + addis r3, r0, CFG_DBAT6U@h + ori r3, r3, CFG_DBAT6U@l + mtspr DBAT6L, r4 + mtspr DBAT6U, r3 + isync + + /* IBAT 7 */ + addis r4, r0, CFG_IBAT7L@h + ori r4, r4, CFG_IBAT7L@l + addis r3, r0, CFG_IBAT7U@h + ori r3, r3, CFG_IBAT7U@l + mtspr IBAT7L, r4 + mtspr IBAT7U, r3 + isync + + /* DBAT 7 */ + addis r4, r0, CFG_DBAT7L@h + ori r4, r4, CFG_DBAT7L@l + addis r3, r0, CFG_DBAT7U@h + ori r3, r3, CFG_DBAT7U@l + mtspr DBAT7L, r4 + mtspr DBAT7U, r3 + isync +#endif + + /* bats are done, now invalidate the TLBs */ + + addis r3, 0, 0x0000 + addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ + + isync + +tlblp: + tlbie r3 + sync + addi r3, r3, 0x1000 + cmp 0, 0, r3, r5 + blt tlblp + + blr + + .globl enable_addr_trans +enable_addr_trans: + /* enable address translation */ + mfmsr r5 + ori r5, r5, (MSR_IR | MSR_DR) + mtmsr r5 + isync + blr + + .globl disable_addr_trans +disable_addr_trans: + /* disable address translation */ + mflr r4 + mfmsr r3 + andi. r0, r3, (MSR_IR | MSR_DR) + beqlr + andc r3, r3, r0 + mtspr SRR0, r4 + mtspr SRR1, r3 + rfi + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + + .globl dc_read +dc_read: + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*-----------------------------------------------------------------------*/ +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ +#ifdef CONFIG_ECC + bl board_relocate_rom + sync + mr r3, r10 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ +#else + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b +#endif +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: +#ifdef CONFIG_ECC + bl board_init_ecc +#endif + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +/* clear_bss: */ + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + mr r3, r10 /* Destination Address */ +#if defined(CONFIG_AMIGAONEG3SE) || \ + defined(CONFIG_DB64360) || \ + defined(CONFIG_DB64460) || \ + defined(CONFIG_CPCI750) + mr r4, r9 /* Use RAM copy of the global data */ +#endif + bl after_reloc + + /* not reached - end relocate_code */ +/*-----------------------------------------------------------------------*/ + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + /* enable execptions from RAM vectors */ + mfmsr r7 + li r8,MSR_IP + andc r7,r7,r8 + mtmsr r7 + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + sync + isync + + blr + +#ifdef CFG_INIT_RAM_LOCK +lock_ram_in_cache: + /* Allocate Initial RAM in data cache. + */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2, ((CFG_INIT_RAM_END & ~31) + \ + (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + mtctr r2 +1: + dcbz r0, r3 + addi r3, r3, 32 + bdnz 1b + + /* Lock the data cache */ + mfspr r0, HID0 + ori r0, r0, 0x1000 + sync + mtspr HID0, r0 + sync + blr + +.globl unlock_ram_in_cache +unlock_ram_in_cache: + /* invalidate the INIT_RAM section */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2, ((CFG_INIT_RAM_END & ~31) + \ + (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + mtctr r2 +1: icbi r0, r3 + addi r3, r3, 32 + bdnz 1b + sync /* Wait for all icbi to complete on bus */ + isync + + /* Unlock the data cache and invalidate it */ + mfspr r0, HID0 + li r3,0x1000 + andc r0,r0,r3 + li r3,0x0400 + or r0,r0,r3 + sync + mtspr HID0, r0 + sync + blr +#endif diff --git a/cpu/74xx_7xx/traps.c b/cpu/74xx_7xx/traps.c new file mode 100644 index 0000000..ac5f8bf --- /dev/null +++ b/cpu/74xx_7xx/traps.c @@ -0,0 +1,254 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler)(struct pt_regs *) = 0; +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. +*/ +#ifdef CONFIG_AMIGAONEG3SE +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) +#else +#define END_OF_MEM 0x02000000 +#endif + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ +#ifdef CONFIG_AMIGAONEG3SE + DECLARE_GLOBAL_DATA_PTR; +#endif + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void +show_regs(struct pt_regs * regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS:" + " %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP:" + " %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + printf("Data parity signal\n"); + break; + case (0x80000000>>15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ + unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; + int i, j; + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + + p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0); + p -= 32; + for (i = 0; i < 256; i+=16) { + printf("%08x: ", (unsigned int)p+i); + for (j = 0; j < 16; j++) { + printf("%02x ", p[i+j]); + } + printf("\n"); + } + + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +SoftEmuException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + + +void +UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int +addr_probe(uint *addr) +{ +#if 0 + int retval; + + __asm__ __volatile__( \ + "1: lwz %0,0(%1)\n" \ + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); + + return (retval); +#endif + return 0; +} diff --git a/cpu/arm1136/Makefile b/cpu/arm1136/Makefile new file mode 100644 index 0000000..203278e --- /dev/null +++ b/cpu/arm1136/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = interrupts.o cpu.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk new file mode 100644 index 0000000..e39e774 --- /dev/null +++ b/cpu/arm1136/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +# Make ARMv5 to allow more compilers to work, even though its v6. +PLATFORM_CPPFLAGS += -march=armv5 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c new file mode 100644 index 0000000..85a4849 --- /dev/null +++ b/cpu/arm1136/cpu.c @@ -0,0 +1,163 @@ +/* + * (C) Copyright 2004 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +#include +#endif + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* Many OMAP regs need at least 2 nops */ + for (i = 0; i < 100; i++); +} + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ +#define C1_WB (1<<3) /* merging write buffer on/off */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + +#ifdef CONFIG_LCD + { + extern void lcd_disable(void); + extern void lcd_panel_disable(void); + + lcd_disable(); /* proper disable of lcd & panel */ + lcd_panel_disable(); + } +#endif + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ + return(0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return(0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return(read_p15_c1 () & C1_IC) != 0; +} diff --git a/cpu/arm1136/interrupts.c b/cpu/arm1136/interrupts.c new file mode 100644 index 0000000..1dc36d0 --- /dev/null +++ b/cpu/arm1136/interrupts.c @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2004 + * Texas Instruments + * Richard Woodruff + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +# include +#endif + +#include + +#define TIMER_LOAD_VAL 0 + +/* macro to read the 32 bit timer */ +#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR)) + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return(old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) +/* Use the IntegratorCP function from board/integratorcp.c */ +#else + +static ulong timestamp; +static ulong lastinc; + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init (void) +{ + int32_t val; + + /* Start the counter ticking up */ + *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ + val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ + *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */ + + reset_timer_masked(); /* init the timestamp and lastinc value */ + + return(0); +} +/* + * timer without interrupts + */ +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastinc = READ_TIMER; /* capture current incrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (now >= lastinc) /* normal mode (non roll) */ + timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */ + else /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + lastinc = now; + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} +#endif /* !Integrator/CP */ diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S new file mode 100644 index 0000000..17c7a83 --- /dev/null +++ b/cpu/arm1136/start.S @@ -0,0 +1,417 @@ +/* + * armboot - Startup Code for OMP2420/ARM1136 CPU-core + * + * Copyright (c) 2004 Texas Instruments + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +#include +#endif +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +.global _end_vect +_end_vect: + + .balignl 16,0xdeadbeef +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + +#ifdef CONFIG_OMAP2420H4 + /* Copy vectors to mask ROM indirect addr */ + adr r0, _start /* r0 <- current position of code */ + add r0, r0, #4 /* skip reset vector */ + mov r2, #64 /* r2 <- size to copy */ + add r2, r0, r2 /* r2 <- source end address */ + mov r1, #SRAM_OFFSET0 /* build vect addr */ + mov r3, #SRAM_OFFSET1 + add r1, r1, r3 + mov r3, #SRAM_OFFSET2 + add r1, r1, r3 +next: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next /* loop until equal */ + bl cpy_clk_code /* put dpll adjust code behind vectors */ +#endif + /* the mask ROM code should have PLL and others stable */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 + + /* + * Jump to board specific initialization... The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle wake up conditions. + */ + mov ip, lr /* persevere link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + + ldr r2, _armboot_start + sub r2, r2, #(CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack (enter in banked mode) + sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_bad_stack_swi + sub r13, r13, #4 @ space on current stack for scratch reg. + str r0, [r13] @ save R0's value. + ldr r0, _armboot_start @ get data regions start + sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool + sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack + str lr, [r0] @ save caller lr in position 0 of saved stack + mrs r0, spsr @ get the spsr + str lr, [r0, #4] @ save spsr in position 1 of saved stack + ldr r0, [r13] @ restore r0 + add r13, r13, #4 @ pop stack entry + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack_swi + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + .align 5 +.global arm1136_cache_flush +arm1136_cache_flush: + mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache + mov pc, lr @ back to caller + +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) +/* Use the IntegratorCP function from board/integratorcp/platform.S */ +#else + + .align 5 +.globl reset_cpu +reset_cpu: + ldr r1, rstctl /* get addr for global reset reg */ + mov r3, #0x2 /* full reset pll+mpu */ + str r3, [r1] /* force reset */ + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl: + .word PM_RSTCTRL_WKUP + +#endif diff --git a/cpu/arm720t/Makefile b/cpu/arm720t/Makefile new file mode 100644 index 0000000..f273d92 --- /dev/null +++ b/cpu/arm720t/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = serial.o serial_netarm.o interrupts.o cpu.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm720t/config.mk b/cpu/arm720t/config.mk new file mode 100644 index 0000000..641b91c --- /dev/null +++ b/cpu/arm720t/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c new file mode 100644 index 0000000..a5b6de7 --- /dev/null +++ b/cpu/arm720t/cpu.c @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include +#include + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + * and we set the CPU-speed to 73 MHz - see start.S for details + */ + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) + unsigned long i; + + disable_interrupts (); + + /* turn off I-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~0x1000; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); +#ifdef CONFIG_ARM7_REVD + /* go to high speed */ + IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; +#endif +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) + disable_interrupts (); + /* Nothing more needed */ +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#else +#error No cleanup_before_linux() defined for this CPU type +#endif + return 0; +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +/* + * Instruction and Data cache enable and disable functions + * + */ + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1(void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + /* printf("p15/c1 is = %08lx\n", value); */ + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1(unsigned long value) +{ + /* printf("write %08lx to p15/c1\n", value); */ + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1(); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_IDC (1<<2) /* icache and/or dcache off/on */ +#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_IDC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IDC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IDC) != 0; +} + +void dcache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_IDC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IDC); +} + +int dcache_status (void) +{ + return (read_p15_c1 () & C1_IDC) != 0; +} + +#elif defined(CONFIG_S3C4510B) + +void icache_enable (void) +{ + s32 i; + + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); + + /* 8KB cache, write enable */ + SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); + + /* clear TAG RAM bits */ + for ( i = 0; i < 256; i++) + PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); + + /* clear SET0 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); + + /* clear SET1 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); + + /* enable cache */ + SET_REG( REG_SYSCFG, CACHE_ENABLE); + +} + +void icache_disable (void) +{ + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); +} + +int icache_status (void) +{ + return GET_REG( REG_SYSCFG) & CACHE_ENABLE; +} + +void dcache_enable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_enable(); +} + +void dcache_disable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_disable(); +} + +int dcache_status (void) +{ + /* we don't have seperate instruction/data caches */ + return icache_status(); +} + +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No specific cache setup for IntegratorAP/CM720T as yet */ + void icache_enable (void) + { + } +#else +#error No icache/dcache enable/disable functions defined for this CPU type +#endif diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c new file mode 100644 index 0000000..da62502 --- /dev/null +++ b/cpu/arm720t/interrupts.c @@ -0,0 +1,413 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifndef CONFIG_NETARM +/* we always count down the max. */ +#define TIMER_LOAD_VAL 0xffff +/* macro to read the 16 bit timer */ +#define READ_TIMER (IO_TC1D & 0xffff) +#else +#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) +#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) +#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS)) +#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK +#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) +#endif + +#ifdef CONFIG_S3C4510B +/* require interrupts for the S3C4510B */ +# ifndef CONFIG_USE_IRQ +# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B +# else +static struct _irq_handler IRQ_HANDLER[N_IRQS]; +# endif +#endif /* CONFIG_S3C4510B */ + +#ifdef CONFIG_USE_IRQ +/* enable IRQ/FIQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0x80\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else /* CONFIG_USE_IRQ */ +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = + { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26", +"UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26", + "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", + "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32", + "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +#elif defined(CONFIG_S3C4510B) + unsigned int pending; + + while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */ + IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data); + + /* clear pending interrupt */ + PUT_REG( REG_INTPEND, (1<<(pending>>2))); + } +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No do_irq() for IntegratorAP/CM720T as yet */ +#else +#error do_irq() not defined for this CPU type +#endif +} + + +#ifdef CONFIG_S3C4510B +static void default_isr( void *data) { + printf ("default_isr(): called for IRQ %d\n", (int)data); +} + +static void timer_isr( void *data) { + unsigned int *pTime = (unsigned int *)data; + + (*pTime)++; + if ( !(*pTime % (CFG_HZ/4))) { + /* toggle LED 0 */ + PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1); + } + +} +#endif + +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* Use IntegratorAP routines in board/integratorap.c */ +#else + +static ulong timestamp; +static ulong lastdec; + +int interrupt_init (void) +{ + +#if defined(CONFIG_NETARM) + /* disable all interrupts */ + IRQEN = 0; + + /* operate timer 2 in non-prescale mode */ + TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) | + NETARM_GEN_TCTL_ENABLE | + NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL)); + + /* set timer 2 counter */ + lastdec = TIMER_LOAD_VAL; +#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) + /* disable all interrupts */ + IO_INTMR1 = 0; + + /* operate timer 1 in prescale mode */ + IO_SYSCON1 |= SYSCON1_TC1M; + + /* select 2kHz clock source for timer 1 */ + IO_SYSCON1 &= ~SYSCON1_TC1S; + + /* set timer 1 counter */ + lastdec = IO_TC1D = TIMER_LOAD_VAL; +#elif defined(CONFIG_S3C4510B) + int i; + + /* install default interrupt handlers */ + for ( i = 0; i < N_IRQS; i++) { + IRQ_HANDLER[i].m_data = (void *)i; + IRQ_HANDLER[i].m_func = default_isr; + } + + /* configure interrupts for IRQ mode */ + PUT_REG( REG_INTMODE, 0x0); + /* clear any pending interrupts */ + PUT_REG( REG_INTPEND, 0x1FFFFF); + + lastdec = 0; + + /* install interrupt handler for timer */ + IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp; + IRQ_HANDLER[INT_TIMER0].m_func = timer_isr; + + /* configure free running timer 0 */ + PUT_REG( REG_TMOD, 0x0); + /* Stop timer 0 */ + CLR_REG( REG_TMOD, TM0_RUN); + + /* Configure for interval mode */ + CLR_REG( REG_TMOD, TM1_TOGGLE); + + /* + * Load Timer data register with count down value. + * count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ + */ + PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ)); + + /* + * Enable global interrupt + * Enable timer0 interrupt + */ + CLR_REG( REG_INTMASK, ((1<= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 1000; + } else { + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +#elif defined(CONFIG_S3C4510B) + +ulong get_timer (ulong base) +{ + return timestamp - base; +} + +void udelay (unsigned long usec) +{ + u32 ticks; + + ticks = (usec * CFG_HZ) / 1000000; + + ticks += get_timer (0); + + while (get_timer (0) < ticks) + /*NOP*/; + +} + +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No timer routines for IntegratorAP/CM720T as yet */ +#else +#error Timer routines not defined for this CPU type +#endif diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c new file mode 100644 index 0000000..0f99979 --- /dev/null +++ b/cpu/arm720t/serial.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) + +#include + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned int reg = 0; + + switch (gd->baudrate) { + case 1200: reg = 191; break; + case 9600: reg = 23; break; + case 19200: reg = 11; break; + case 38400: reg = 5; break; + case 57600: reg = 3; break; + case 115200: reg = 1; break; + default: hang (); break; + } + + /* init serial serial 1,2 */ + IO_SYSCON1 = SYSCON1_UART1EN; + IO_SYSCON2 = SYSCON2_UART2EN; + + reg |= UBRLCR_WRDLEN8; + + IO_UBRLCR1 = reg; + IO_UBRLCR2 = reg; +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + serial_setbrg (); + + return (0); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + int tmo; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); + + tmo = get_timer (0) + 1 * CFG_HZ; + while (IO_SYSFLG1 & SYSFLG1_UTXFF) + if (get_timer (0) > tmo) + break; + + IO_UARTDR1 = c; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_tstc (void) +{ + return !(IO_SYSFLG1 & SYSFLG1_URXFE); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + while (IO_SYSFLG1 & SYSFLG1_URXFE); + + return IO_UARTDR1 & 0xff; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) */ diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c new file mode 100644 index 0000000..5ad98f0 --- /dev/null +++ b/cpu/arm720t/serial_netarm.c @@ -0,0 +1,201 @@ +/* + * Serial Port stuff - taken from Linux + * + * (C) Copyright 2002 + * MAZeT GmbH + * Stephan Linz , + * + * (c) 2004 + * IMMS gGmbH + * Thomas Elste + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#ifdef CONFIG_NETARM + +#include + +#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) +#if !defined(CONFIG_NETARM_NS7520) +#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) +#else +#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC)) +#endif + +/* wait until transmitter is ready for another character */ +#define TXWAITRDY(registers) \ +{ \ + ulong tmo = get_timer(0) + 1 * CFG_HZ; \ + while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ + if (get_timer(0) > tmo) \ + break; \ + } \ +} + + +#ifndef CONFIG_UART1_CONSOLE +volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); +volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); +#else +volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(1); +volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(0); +#endif + +extern void _netarm_led_FAIL1(void); + +/* + * Setup both serial i/f with given baudrate + */ +void serial_setbrg (void) +{ + /* get the gd pointer */ + DECLARE_GLOBAL_DATA_PTR; + + /* set 0 ... make sure pins are configured for serial */ +#if !defined(CONFIG_NETARM_NS7520) + PORTA = PORTB = + NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); +#else + PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); + PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); +#endif + + /* first turn em off */ + serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0; + + /* clear match register, we don't need it */ + serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0; + + /* setup bit rate generator and rx buffer gap timer (1 byte only) */ + if ((gd->baudrate >= MIN_BAUD_RATE) + && (gd->baudrate <= MAX_BAUD_RATE)) { + serial_reg_ch1->bitrate = serial_reg_ch2->bitrate = + NETARM_SER_BR_X16 (gd->baudrate); + serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer = + 0; + serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer = + NETARM_SER_RXGAP (gd->baudrate); + } else { + hang (); + } + + /* setup port mode */ + serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b = + ( NETARM_SER_CTLB_RCGT_EN | + NETARM_SER_CTLB_UART_MODE); + serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = + ( NETARM_SER_CTLA_ENABLE | + NETARM_SER_CTLA_P_NONE | + /* see errata */ + NETARM_SER_CTLA_2STOP | + NETARM_SER_CTLA_8BITS | + NETARM_SER_CTLA_DTR_EN | + NETARM_SER_CTLA_RTS_EN); +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +int serial_init (void) +{ + serial_setbrg (); + return 0; +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + volatile unsigned char *fifo; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); + + fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo); + TXWAITRDY (serial_reg_ch1); + *fifo = c; +} + +/* + * Test of a single byte from the serial port. Returns 1 on success, 0 + * otherwise. + */ +int serial_tstc(void) +{ + return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. + */ +int serial_getc (void) +{ + unsigned int ch_uint; + volatile unsigned int *fifo; + volatile unsigned char *fifo_char = NULL; + int buf_count = 0; + + while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY)) + /* NOP */ ; + + fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo); + fifo_char = (unsigned char *) &ch_uint; + ch_uint = *fifo; + + buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a); + switch (buf_count) { + case NETARM_SER_STATA_RXFDB_4BYTES: + buf_count = 4; + break; + case NETARM_SER_STATA_RXFDB_3BYTES: + buf_count = 3; + break; + case NETARM_SER_STATA_RXFDB_2BYTES: + buf_count = 2; + break; + case NETARM_SER_STATA_RXFDB_1BYTES: + buf_count = 1; + break; + default: + /* panic, be never here */ + break; + } + + serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED; + + return ch_uint & 0xff; +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* CONFIG_NETARM */ diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S new file mode 100644 index 0000000..e66d109 --- /dev/null +++ b/cpu/arm720t/start.S @@ -0,0 +1,542 @@ +/* + * armboot - Startup Code for ARM720 CPU-core + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from RAM! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0x13 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + +#if TEXT_BASE + ldr r2, =0x0 /* Relocate the exception vectors */ + cmp r1, r2 /* and associated data to address */ + ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */ + stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */ + ldmneia r0, {r3-r9} + stmneia r2, {r3-r9} + adrne r0, _start /* restore r0 */ +#endif + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) + +/* Interupt-Controller base addresses */ +INTMR1: .word 0x80000280 @ 32 bit size +INTMR2: .word 0x80001280 @ 16 bit size +INTMR3: .word 0x80002280 @ 8 bit size + +/* SYSCONs */ +SYSCON1: .word 0x80000100 +SYSCON2: .word 0x80001100 +SYSCON3: .word 0x80002200 + +#define CLKCTL 0x6 /* mask */ +#define CLKCTL_18 0x0 /* 18.432 MHz */ +#define CLKCTL_36 0x2 /* 36.864 MHz */ +#define CLKCTL_49 0x4 /* 49.152 MHz */ +#define CLKCTL_73 0x6 /* 73.728 MHz */ + +#endif + +cpu_init_crit: +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) + + /* + * mask all IRQs by clearing all bits in the INTMRs + */ + mov r1, #0x00 + ldr r0, INTMR1 + str r1, [r0] + ldr r0, INTMR2 + str r1, [r0] + ldr r0, INTMR3 + str r1, [r0] + + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15,0,r0,c1,c0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + mcr p15,0,r0,c1,c0 +#elif defined(CONFIG_NETARM) + /* + * prior to software reset : need to set pin PORTC4 to be *HRESET + */ + ldr r0, =NETARM_GEN_MODULE_BASE + ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ + NETARM_GEN_PORT_DIR(0x10)) + str r1, [r0, #+NETARM_GEN_PORTC] + /* + * software reset : see HW Ref. Guide 8.2.4 : Software Service register + * for an explanation of this process + */ + ldr r0, =NETARM_GEN_MODULE_BASE + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + /* + * setup PLL and System Config + */ + ldr r0, =NETARM_GEN_MODULE_BASE + + ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ + NETARM_GEN_SYS_CFG_BUSFULL | \ + NETARM_GEN_SYS_CFG_USER_EN | \ + NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ + NETARM_GEN_SYS_CFG_BUSARB_INT | \ + NETARM_GEN_SYS_CFG_BUSMON_EN ) + + str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] + +#ifndef CONFIG_NETARM_PLL_BYPASS + ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ + NETARM_GEN_PLL_CTL_POLTST_DEF | \ + NETARM_GEN_PLL_CTL_INDIV(1) | \ + NETARM_GEN_PLL_CTL_ICP_DEF | \ + NETARM_GEN_PLL_CTL_OUTDIV(2) ) + str r1, [r0, #+NETARM_GEN_PLL_CONTROL] +#endif + + /* + * mask all IRQs by clearing all bits in the INTMRs + */ + mov r1, #0 + ldr r0, =NETARM_GEN_MODULE_BASE + str r1, [r0, #+NETARM_GEN_INTR_ENABLE] + +#elif defined(CONFIG_S3C4510B) + + /* + * Mask off all IRQ sources + */ + ldr r1, =REG_INTMASK + ldr r0, =0x3FFFFF + str r0, [r1] + + /* + * Disable Cache + */ + ldr r0, =REG_SYSCFG + ldr r1, =0x83ffffa0 /* cache-disabled */ + str r1, [r0] + +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No specific initialisation for IntegratorAP/CM720T as yet */ +#else +#error No cpu_init_crit() defined for current CPU type +#endif + +#ifdef CONFIG_ARM7_REVD + /* set clock speed */ + /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */ + /* !!! not doing DRAM refresh properly! */ + ldr r0, SYSCON3 + ldr r1, [r0] + bic r1, r1, #CLKCTL + orr r1, r1, #CLKCTL_36 + str r1, [r0] +#endif + + mov ip, lr + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependent, you will + * find a lowlevel_init.S in your board directory. + */ + bl lowlevel_init + mov lr, ip + + mov pc, lr + + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + msr spsr_c, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) + .align 5 +.globl reset_cpu +reset_cpu: + mov ip, #0 + mcr p15, 0, ip, c7, c7, 0 @ invalidate cache + mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) + mrc p15, 0, ip, c1, c0, 0 @ get ctrl register + bic ip, ip, #0x000f @ ............wcam + bic ip, ip, #0x2100 @ ..v....s........ + mcr p15, 0, ip, c1, c0, 0 @ ctrl register + mov pc, r0 +#elif defined(CONFIG_NETARM) + .align 5 +.globl reset_cpu +reset_cpu: + ldr r1, =NETARM_MEM_MODULE_BASE + ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] + ldr r1, =0xFFFFF000 + and r0, r1, r0 + ldr r1, =(relocate-TEXT_BASE) + add r0, r1, r0 + ldr r4, =NETARM_GEN_MODULE_BASE + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + mov pc, r0 +#elif defined(CONFIG_S3C4510B) +/* Nothing done here as reseting the CPU is board specific, depending + * on external peripherals such as watchdog timers, etc. */ +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) + /* No specific reset actions for IntegratorAP/CM720T as yet */ +#else +#error No reset_cpu() defined for current CPU type +#endif diff --git a/cpu/arm920t/Makefile b/cpu/arm920t/Makefile new file mode 100644 index 0000000..8f256e9 --- /dev/null +++ b/cpu/arm920t/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = cpu.o interrupts.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile new file mode 100644 index 0000000..aec9cb6 --- /dev/null +++ b/cpu/arm920t/at91rm9200/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(SOC).a + +OBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ + lxt972.o serial.o usb_ohci.o +SOBJS = lowlevel_init.o + +all: .depend $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm920t/at91rm9200/bcm5221.c b/cpu/arm920t/at91rm9200/bcm5221.c new file mode 100644 index 0000000..6db1435 --- /dev/null +++ b/cpu/arm920t/at91rm9200/bcm5221.c @@ -0,0 +1,232 @@ +/* + * Broadcom BCM5221 Ethernet PHY + * + * (C) Copyright 2005 REA Elektronik GmbH + * Anders Larsen + * + * (C) Copyright 2003 + * Author : Hamid Ikdoumi (Atmel) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_DRIVER_ETHER + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * bcm5221_IsPhyConnected + * Description: + * Reads the 2 PHY ID registers + * Arguments: + * p_mac - pointer to AT91S_EMAC struct + * Return value: + * TRUE - if id read successfully + * FALSE- if error + */ +unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac) +{ + unsigned short Id1, Id2; + + at91rm9200_EmacEnableMDIO (p_mac); + at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1); + at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2); + at91rm9200_EmacDisableMDIO (p_mac); + + if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) && + ((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK))) + return TRUE; + + return FALSE; +} + +/* + * Name: + * bcm5221_GetLinkSpeed + * Description: + * Link parallel detection status of MAC is checked and set in the + * MAC configuration registers + * Arguments: + * p_mac - pointer to MAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac) +{ + unsigned short stat1, stat2; + + if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1)) + return FALSE; + + if (!(stat1 & BCM5221_LINK_STATUS)) /* link status up? */ + return FALSE; + + if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2)) + return FALSE; + + if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) { + /*set Emac for 100BaseTX and Full Duplex */ + p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } + + if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) { + /*set MII for 100BaseTX and Half Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_SPD; + return TRUE; + } + + if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) { + /*set MII for 10BaseT and Half Duplex */ + p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + return TRUE; + } + return FALSE; +} + + +/* + * Name: + * bcm5221_InitPhy + * Description: + * MAC starts checking its link by using parallel detection and + * Autonegotiation and the same is set in the MAC configuration registers + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac) +{ + unsigned char ret = TRUE; + unsigned short IntValue; + + at91rm9200_EmacEnableMDIO (p_mac); + + if (!bcm5221_GetLinkSpeed (p_mac)) { + /* Try another time */ + ret = bcm5221_GetLinkSpeed (p_mac); + } + + /* Disable PHY Interrupts */ + at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue); + /* clear FDX LED and INTR Enable */ + IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE); + /* set FDX, SPD, Link, INTR masks */ + IntValue |= (BCM5221_FDX_MASK | BCM5221_SPD_MASK | + BCM5221_LINK_MASK | BCM5221_INTR_MASK); + at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue); + at91rm9200_EmacDisableMDIO (p_mac); + + return (ret); +} + + +/* + * Name: + * bcm5221_AutoNegotiate + * Description: + * MAC Autonegotiates with the partner status of same is set in the + * MAC configuration registers + * Arguments: + * dev - pointer to struct net_device + * Return value: + * TRUE - if link status set successfully + * FALSE - if link status not set + */ +unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status) +{ + unsigned short value; + unsigned short PhyAnar; + unsigned short PhyAnalpar; + + /* Set bcm5221 control register */ + if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value)) + return FALSE; + value &= ~BCM5221_AUTONEG; /* remove autonegotiation enable */ + value |= BCM5221_ISOLATE; /* Electrically isolate PHY */ + if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) + return FALSE; + + /* Set the Auto_negotiation Advertisement Register */ + /* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX | + BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3; + if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar)) + return FALSE; + + /* Read the Control Register */ + if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value)) + return FALSE; + + value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE; + if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) + return FALSE; + /* Restart Auto_negotiation */ + value |= BCM5221_RESTART_AUTONEG; + value &= ~BCM5221_ISOLATE; + if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) + return FALSE; + + /*check AutoNegotiate complete */ + udelay (10000); + at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value); + if (!(value & BCM5221_AUTONEG_COMP)) + return FALSE; + + /* Get the AutoNeg Link partner base page */ + if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar)) + return FALSE; + + if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) { + /*set MII for 100BaseTX and Full Duplex */ + p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } + return FALSE; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/dm9161.c b/cpu/arm920t/at91rm9200/dm9161.c new file mode 100644 index 0000000..4b13c23 --- /dev/null +++ b/cpu/arm920t/at91rm9200/dm9161.c @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2003 + * Author : Hamid Ikdoumi (Atmel) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_DRIVER_ETHER + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * dm9161_IsPhyConnected + * Description: + * Reads the 2 PHY ID registers + * Arguments: + * p_mac - pointer to AT91S_EMAC struct + * Return value: + * TRUE - if id read successfully + * FALSE- if error + */ +unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac) +{ + unsigned short Id1, Id2; + + at91rm9200_EmacEnableMDIO (p_mac); + at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1); + at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2); + at91rm9200_EmacDisableMDIO (p_mac); + + if ((Id1 == (DM9161_PHYID1_OUI >> 6)) && + ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK))) + return TRUE; + + return FALSE; +} + +/* + * Name: + * dm9161_GetLinkSpeed + * Description: + * Link parallel detection status of MAC is checked and set in the + * MAC configuration registers + * Arguments: + * p_mac - pointer to MAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac) +{ + unsigned short stat1, stat2; + + if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1)) + return FALSE; + + if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */ + return FALSE; + + if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2)) + return FALSE; + + if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) { + /*set Emac for 100BaseTX and Full Duplex */ + p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } + + if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) { + /*set MII for 100BaseTX and Half Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_SPD; + return TRUE; + } + + if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) { + /*set MII for 10BaseT and Half Duplex */ + p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + return TRUE; + } + return FALSE; +} + + +/* + * Name: + * dm9161_InitPhy + * Description: + * MAC starts checking its link by using parallel detection and + * Autonegotiation and the same is set in the MAC configuration registers + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac) +{ + UCHAR ret = TRUE; + unsigned short IntValue; + + at91rm9200_EmacEnableMDIO (p_mac); + + if (!dm9161_GetLinkSpeed (p_mac)) { + /* Try another time */ + ret = dm9161_GetLinkSpeed (p_mac); + } + + /* Disable PHY Interrupts */ + at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue); + /* set FDX, SPD, Link, INTR masks */ + IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK | + DM9161_LINK_MASK | DM9161_INTR_MASK); + at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue); + at91rm9200_EmacDisableMDIO (p_mac); + + return (ret); +} + + +/* + * Name: + * dm9161_AutoNegotiate + * Description: + * MAC Autonegotiates with the partner status of same is set in the + * MAC configuration registers + * Arguments: + * dev - pointer to struct net_device + * Return value: + * TRUE - if link status set successfully + * FALSE - if link status not set + */ +UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status) +{ + unsigned short value; + unsigned short PhyAnar; + unsigned short PhyAnalpar; + + /* Set dm9161 control register */ + if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value)) + return FALSE; + value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */ + value |= DM9161_ISOLATE; /* Electrically isolate PHY */ + if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) + return FALSE; + + /* Set the Auto_negotiation Advertisement Register */ + /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX | + DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; + if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar)) + return FALSE; + + /* Read the Control Register */ + if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value)) + return FALSE; + + value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE; + if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) + return FALSE; + /* Restart Auto_negotiation */ + value |= DM9161_RESTART_AUTONEG; + value &= ~DM9161_ISOLATE; + if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) + return FALSE; + + /*check AutoNegotiate complete */ + udelay (10000); + at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value); + if (!(value & DM9161_AUTONEG_COMP)) + return FALSE; + + /* Get the AutoNeg Link partner base page */ + if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar)) + return FALSE; + + if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) { + /*set MII for 100BaseTX and Full Duplex */ + p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } + return FALSE; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c new file mode 100644 index 0000000..67008d0 --- /dev/null +++ b/cpu/arm920t/at91rm9200/ether.c @@ -0,0 +1,299 @@ +/* + * (C) Copyright 2003 + * Author : Hamid Ikdoumi (Atmel) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ----- Ethernet Buffer definitions ----- */ + +typedef struct { + unsigned long addr, size; +} rbf_t; + +#define RBF_ADDR 0xfffffffc +#define RBF_OWNER (1<<0) +#define RBF_WRAP (1<<1) +#define RBF_BROADCAST (1<<31) +#define RBF_MULTICAST (1<<30) +#define RBF_UNICAST (1<<29) +#define RBF_EXTERNAL (1<<28) +#define RBF_UNKOWN (1<<27) +#define RBF_SIZE 0x07ff +#define RBF_LOCAL4 (1<<26) +#define RBF_LOCAL3 (1<<25) +#define RBF_LOCAL2 (1<<24) +#define RBF_LOCAL1 (1<<23) + +#define RBF_FRAMEMAX 64 +#define RBF_FRAMELEN 0x600 + +#ifdef CONFIG_DRIVER_ETHER + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* alignment as per Errata #11 (64 bytes) is insufficient! */ +rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512))); +rbf_t *rbfp; + +unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN] __attribute((aligned(4))); + +/* structure to interface the PHY */ +AT91S_PhyOps PhyOps; + +AT91PS_EMAC p_mac; + +/*********** EMAC Phy layer Management functions *************************/ +/* + * Name: + * at91rm9200_EmacEnableMDIO + * Description: + * Enables the MDIO bit in MAC control register + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * none + */ +void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac) +{ + /* Mac CTRL reg set for MDIO enable */ + p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */ +} + +/* + * Name: + * at91rm9200_EmacDisableMDIO + * Description: + * Disables the MDIO bit in MAC control register + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * none + */ +void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac) +{ + /* Mac CTRL reg set for MDIO disable */ + p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */ +} + + +/* + * Name: + * at91rm9200_EmacReadPhy + * Description: + * Reads data from the PHY register + * Arguments: + * dev - pointer to struct net_device + * RegisterAddress - unsigned char + * pInput - pointer to value read from register + * Return value: + * TRUE - if data read successfully + */ +UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac, + unsigned char RegisterAddress, + unsigned short *pInput) +{ + p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) | + (AT91C_EMAC_RW_R) | + (RegisterAddress << 18) | + (AT91C_EMAC_CODE_802_3); + + udelay (10000); + + *pInput = (unsigned short) p_mac->EMAC_MAN; + + return TRUE; +} + + +/* + * Name: + * at91rm9200_EmacWritePhy + * Description: + * Writes data to the PHY register + * Arguments: + * dev - pointer to struct net_device + * RegisterAddress - unsigned char + * pOutput - pointer to value to be written in the register + * Return value: + * TRUE - if data read successfully + */ +UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac, + unsigned char RegisterAddress, + unsigned short *pOutput) +{ + p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) | + AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W | + (RegisterAddress << 18) | *pOutput; + + udelay (10000); + + return TRUE; +} + +int eth_init (bd_t * bd) +{ + int ret; + int i; + + p_mac = AT91C_BASE_EMAC; + + /* PIO Disable Register */ + *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | + AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | + AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | + AT91C_PA7_ETXCK_EREFCK; + +#ifdef CONFIG_AT91C_USE_RMII + *AT91C_PIOB_PDR = AT91C_PB19_ERXCK; + *AT91C_PIOB_BSR = AT91C_PB19_ERXCK; +#else + *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | + AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | + AT91C_PB13_ETX3 | AT91C_PB12_ETX2; + + /* Select B Register */ + *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | + AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | + AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; +#endif + + *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */ + + p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */ + + /* Init Ehternet buffers */ + for (i = 0; i < RBF_FRAMEMAX; i++) { + rbfdt[i].addr = (unsigned long)rbf_framebuf[i]; + rbfdt[i].size = 0; + } + rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; + rbfp = &rbfdt[0]; + + p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16) + | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]); + p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]); + + p_mac->EMAC_RBQP = (long) (&rbfdt[0]); + p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); + + p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC) + & ~AT91C_EMAC_CLK; + +#ifdef CONFIG_AT91C_USE_RMII + p_mac->EMAC_CFG |= AT91C_EMAC_RMII; +#endif + +#if (AT91C_MASTER_CLOCK > 40000000) + /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ + p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64; +#endif + + p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE; + + at91rm9200_GetPhyInterface (& PhyOps); + + if (!PhyOps.IsPhyConnected (p_mac)) + printf ("PHY not connected!!\n\r"); + + /* MII management start from here */ + if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { + if (!(ret = PhyOps.Init (p_mac))) { + printf ("MAC: error during MII initialization\n"); + return 0; + } + } else { + printf ("No link\n\r"); + return 0; + } + + return 0; +} + +int eth_send (volatile void *packet, int length) +{ + while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ)); + p_mac->EMAC_TAR = (long) packet; + p_mac->EMAC_TCR = length; + while (p_mac->EMAC_TCR & 0x7ff); + p_mac->EMAC_TSR |= AT91C_EMAC_COMP; + return 0; +} + +int eth_rx (void) +{ + int size; + + if (!(rbfp->addr & RBF_OWNER)) + return 0; + + size = rbfp->size & RBF_SIZE; + NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size); + + rbfp->addr &= ~RBF_OWNER; + if (rbfp->addr & RBF_WRAP) + rbfp = &rbfdt[0]; + else + rbfp++; + + p_mac->EMAC_RSR |= AT91C_EMAC_REC; + + return size; +} + +void eth_halt (void) +{ +}; + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +int at91rm9200_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short * value) +{ + at91rm9200_EmacEnableMDIO (p_mac); + at91rm9200_EmacReadPhy (p_mac, reg, value); + at91rm9200_EmacDisableMDIO (p_mac); + return 0; +} + +int at91rm9200_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + at91rm9200_EmacEnableMDIO (p_mac); + at91rm9200_EmacWritePhy (p_mac, reg, &value); + at91rm9200_EmacDisableMDIO (p_mac); + return 0; +} + +#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +int at91rm9200_miiphy_initialize(bd_t *bis) +{ +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write); +#endif + return 0; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c new file mode 100644 index 0000000..2565998 --- /dev/null +++ b/cpu/arm920t/at91rm9200/i2c.c @@ -0,0 +1,206 @@ +/* + * i2c Support for Atmel's AT91RM9200 Two-Wire Interface + * + * (c) Rick Bronson + * + * Borrowed heavily from original work by: + * Copyright (c) 2000 Philip Edelbrock + * + * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * +*/ +#include + +#ifdef CONFIG_HARD_I2C + +#include +#include +#include + +#include + +/* define DEBUG */ + +/* + * Poll the i2c status register until the specified bit is set. + * Returns 0 if timed out (100 msec) + */ +static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) { + int loop_cntr = 10000; + do { + udelay(10); + } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0)); + + return (loop_cntr > 0); +} + +/* + * Generic i2c master transfer entrypoint + * + * rw == 1 means that this is a read + */ +static int +at91_xfer(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len, int rw) +{ + AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; + int length; + unsigned char *buf; + /* Set the TWI Master Mode Register */ + twi->TWI_MMR = (chip << 16) | (alen << 8) + | ((rw == 1) ? AT91C_TWI_MREAD : 0); + + /* Set TWI Internal Address Register with first messages data field */ + if (alen > 0) + twi->TWI_IADR = addr; + + length = len; + buf = buffer; + if (length && buf) { /* sanity check */ + if (rw) { + twi->TWI_CR = AT91C_TWI_START; + while (length--) { + if (!length) + twi->TWI_CR = AT91C_TWI_STOP; + /* Wait until transfer is finished */ + if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) { + debug ("at91_i2c: timeout 1\n"); + return 1; + } + *buf++ = twi->TWI_RHR; + } + if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { + debug ("at91_i2c: timeout 2\n"); + return 1; + } + } else { + twi->TWI_CR = AT91C_TWI_START; + while (length--) { + twi->TWI_THR = *buf++; + if (!length) + twi->TWI_CR = AT91C_TWI_STOP; + if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) { + debug ("at91_i2c: timeout 3\n"); + return 1; + } + } + /* Wait until transfer is finished */ + if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { + debug ("at91_i2c: timeout 4\n"); + return 1; + } + } + } + return 0; +} + +int +i2c_probe(unsigned char chip) +{ + char buffer[1]; + + return at91_xfer(chip, 0, 0, buffer, 1, 1); +} + +int +i2c_read (unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len) +{ +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* we only allow one address byte */ + if (alen > 1) + return 1; + /* XXX assume an ATMEL AT24C16 */ + if (alen == 1) { +#if 0 /* EEPROM code already sets this correctly */ + chip |= (addr >> 8) & 0xff; +#endif + addr = addr & 0xff; + } +#endif + return at91_xfer(chip, addr, alen, buffer, len, 1); +} + +int +i2c_write(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len) +{ +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + int i; + unsigned char *buf; + + /* we only allow one address byte */ + if (alen > 1) + return 1; + /* XXX assume an ATMEL AT24C16 */ + if (alen == 1) { + buf = buffer; + /* do single byte writes */ + for (i = 0; i < len; i++) { +#if 0 /* EEPROM code already sets this correctly */ + chip |= (addr >> 8) & 0xff; +#endif + addr = addr & 0xff; + if (at91_xfer(chip, addr, alen, buf++, 1, 0)) + return 1; + addr++; + } + return 0; + } +#endif + return at91_xfer(chip, addr, alen, buffer, len, 0); +} + +/* + * Main initialization routine + */ +void +i2c_init(int speed, int slaveaddr) +{ + AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; + + *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK; + *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK; + *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK; + *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */ + + twi->TWI_IDR = 0x3ff; /* Disable all interrupts */ + twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */ + twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */ + + /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */ + twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8); + + debug ("Found AT91 i2c\n"); + return; +} + +uchar i2c_reg_read(uchar i2c_addr, uchar reg) +{ + char buf; + + i2c_read(i2c_addr, reg, 1, &buf, 1); + + return(buf); +} + +void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write(i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/arm920t/at91rm9200/interrupts.c b/cpu/arm920t/at91rm9200/interrupts.c new file mode 100644 index 0000000..1054602 --- /dev/null +++ b/cpu/arm920t/at91rm9200/interrupts.c @@ -0,0 +1,210 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +/*#include */ +#include +/*#include */ + +/* the number of clocks per CFG_HZ */ +#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ) + +/* macro to read the 16 bit timer */ +#define READ_TIMER (tmr->TC_CV & 0x0000ffff) +AT91PS_TC tmr; + +static ulong timestamp; +static ulong lastinc; + +int interrupt_init (void) +{ + tmr = AT91C_BASE_TC0; + + /* enables TC1.0 clock */ + *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */ + + *AT91C_TCB0_BCR = 0; + *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE; + tmr->TC_CCR = AT91C_TC_CLKDIS; +#define AT91C_TC_CMR_CPCTRG (1 << 14) + /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */ + tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG; + + tmr->TC_IDR = ~0ul; + tmr->TC_RC = TIMER_LOAD_VAL; + lastinc = 0; + tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN; + timestamp = 0; + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + udelay_masked(usec); +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastinc = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_raw (void) +{ + ulong now = READ_TIMER; + + if (now >= lastinc) { + /* normal mode */ + timestamp += now - lastinc; + } else { + /* we have an overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastinc; + } + lastinc = now; + + return timestamp; +} + +ulong get_timer_masked (void) +{ + return get_timer_raw()/TIMER_LOAD_VAL; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + tmo = CFG_HZ_CLOCK / 1000; + tmo *= usec; + tmo /= 1000; + + endtime = get_timer_raw () + tmo; + + do { + ulong now = get_timer_raw (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return tbclk; +} + +/* + * Reset the cpu by setting up the watchdog timer and let him time out + * or toggle a GPIO pin on the AT91RM9200DK board + */ +void reset_cpu (ulong ignored) +{ + +#ifdef CONFIG_DBGU + AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU; +#endif +#ifdef CONFIG_USART0 + AT91PS_USART us = AT91C_BASE_US0; +#endif +#ifdef CONFIG_USART1 + AT91PS_USART us = AT91C_BASE_US1; +#endif +#ifdef CONFIG_AT91RM9200DK + AT91PS_PIO pio = AT91C_BASE_PIOA; +#endif + + /*shutdown the console to avoid strange chars during reset */ + us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX); + +#ifdef CONFIG_AT91RM9200DK + /* Clear PA19 to trigger the hard reset */ + pio->PIO_CODR = 0x00080000; + pio->PIO_OER = 0x00080000; + pio->PIO_PER = 0x00080000; +#endif + + /* this is the way Linux does it */ + + /* FIXME: + * These defines should be moved into + * include/asm-arm/arch-at91rm9200/AT91RM9200.h + * as soon as the whitespace fix gets applied. + */ + #define AT91C_ST_RSTEN (0x1 << 16) + #define AT91C_ST_EXTEN (0x1 << 17) + #define AT91C_ST_WDRST (0x1 << 0) + #define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */ + #define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */ + + ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ; + ST_CR = AT91C_ST_WDRST; + + while (1); + /* Never reached */ +} diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S new file mode 100644 index 0000000..1902bd0 --- /dev/null +++ b/cpu/arm920t/at91rm9200/lowlevel_init.S @@ -0,0 +1,205 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the at91rm9200dk board by + * (C) Copyright 2004 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +/* + * some parameters for the board + * + * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in + * turn is based on the boot.bin code from ATMEL + * + */ + +/* flash */ +#define MC_PUIA 0xFFFFFF10 +#define MC_PUP 0xFFFFFF50 +#define MC_PUER 0xFFFFFF54 +#define MC_ASR 0xFFFFFF04 +#define MC_AASR 0xFFFFFF08 +#define EBI_CFGR 0xFFFFFF64 +#define SMC2_CSR 0xFFFFFF70 + +/* clocks */ +#define PLLAR 0xFFFFFC28 +#define PLLBR 0xFFFFFC2C +#define MCKR 0xFFFFFC30 + +#define AT91C_BASE_CKGR 0xFFFFFC20 +#define CKGR_MOR 0 + +/* sdram */ +#define PIOC_ASR 0xFFFFF870 +#define PIOC_BSR 0xFFFFF874 +#define PIOC_PDR 0xFFFFF804 +#define EBI_CSA 0xFFFFFF60 +#define SDRC_CR 0xFFFFFF98 +#define SDRC_MR 0xFFFFFF90 +#define SDRC_TR 0xFFFFFF94 + + +_MTEXT_BASE: +#undef START_FROM_MEM +#ifdef START_FROM_MEM + .word TEXT_BASE-PHYS_FLASH_1 +#else + .word TEXT_BASE +#endif + +.globl lowlevel_init +lowlevel_init: + /* Get the CKGR Base Address */ + ldr r1, =AT91C_BASE_CKGR + /* Main oscillator Enable register */ +#ifdef CFG_USE_MAIN_OSCILLATOR + ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */ +#else + ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */ +#endif + str r0, [r1, #CKGR_MOR] + /* Add loop to compensate Main Oscillator startup time */ + ldr r0, =0x00000010 +LoopOsc: + subs r0, r0, #1 + bhi LoopOsc + + /* memory control configuration */ + /* this isn't very elegant, but what the heck */ + ldr r0, =SMRDATA + ldr r1, _MTEXT_BASE + sub r0, r0, r1 + add r2, r0, #80 +0: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 0b + /* delay - this is all done by guess */ + ldr r0, =0x00010000 +1: + subs r0, r0, #1 + bhi 1b + ldr r0, =SMRDATA1 + ldr r1, _MTEXT_BASE + sub r0, r0, r1 + add r2, r0, #176 +2: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 2b + + /* switch from FastBus to Asynchronous clock mode */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF) + mcr p15, 0, r0, c1, c0, 0 + + /* everything is fine now */ + mov pc, lr + + .ltorg + +SMRDATA: + .word MC_PUIA + .word MC_PUIA_VAL + .word MC_PUP + .word MC_PUP_VAL + .word MC_PUER + .word MC_PUER_VAL + .word MC_ASR + .word MC_ASR_VAL + .word MC_AASR + .word MC_AASR_VAL + .word EBI_CFGR + .word EBI_CFGR_VAL + .word SMC2_CSR + .word SMC2_CSR_VAL + .word PLLAR + .word PLLAR_VAL + .word PLLBR + .word PLLBR_VAL + .word MCKR + .word MCKR_VAL + /* SMRDATA is 80 bytes long */ + /* here there's a delay of 100 */ +SMRDATA1: + .word PIOC_ASR + .word PIOC_ASR_VAL + .word PIOC_BSR + .word PIOC_BSR_VAL + .word PIOC_PDR + .word PIOC_PDR_VAL + .word EBI_CSA + .word EBI_CSA_VAL + .word SDRC_CR + .word SDRC_CR_VAL + .word SDRC_MR + .word SDRC_MR_VAL + .word SDRAM + .word SDRAM_VAL + .word SDRC_MR + .word SDRC_MR_VAL1 + .word SDRAM + .word SDRAM_VAL + .word SDRAM + .word SDRAM_VAL + .word SDRAM + .word SDRAM_VAL + .word SDRAM + .word SDRAM_VAL + .word SDRAM + .word SDRAM_VAL + .word SDRAM + .word SDRAM_VAL + .word SDRAM + .word SDRAM_VAL + .word SDRAM + .word SDRAM_VAL + .word SDRC_MR + .word SDRC_MR_VAL2 + .word SDRAM1 + .word SDRAM_VAL + .word SDRC_TR + .word SDRC_TR_VAL + .word SDRAM + .word SDRAM_VAL + .word SDRC_MR + .word SDRC_MR_VAL3 + .word SDRAM + .word SDRAM_VAL + /* SMRDATA1 is 176 bytes long */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/cpu/arm920t/at91rm9200/lxt972.c b/cpu/arm920t/at91rm9200/lxt972.c new file mode 100644 index 0000000..f12c59c --- /dev/null +++ b/cpu/arm920t/at91rm9200/lxt972.c @@ -0,0 +1,191 @@ +/* + * + * (C) Copyright 2003 + * Author : Hamid Ikdoumi (Atmel) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Adapted for KwikByte KB920x board: 22APR2005 + */ + +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_ETHER + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * lxt972_IsPhyConnected + * Description: + * Reads the 2 PHY ID registers + * Arguments: + * p_mac - pointer to AT91S_EMAC struct + * Return value: + * TRUE - if id read successfully + * FALSE- if error + */ +unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac) +{ + unsigned short Id1, Id2; + + at91rm9200_EmacEnableMDIO (p_mac); + at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID1, &Id1); + at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID2, &Id2); + at91rm9200_EmacDisableMDIO (p_mac); + + if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0)) + return TRUE; + + return FALSE; +} + +/* + * Name: + * lxt972_GetLinkSpeed + * Description: + * Link parallel detection status of MAC is checked and set in the + * MAC configuration registers + * Arguments: + * p_mac - pointer to MAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac) +{ + unsigned short stat1; + + if (!at91rm9200_EmacReadPhy (p_mac, PHY_LXT971_STAT2, &stat1)) + return FALSE; + + if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link status up? */ + return FALSE; + + if (stat1 & PHY_LXT971_STAT2_100BTX) { + + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + + /*set Emac for 100BaseTX and Full Duplex */ + p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + } else { + + /*set Emac for 100BaseTX and Half Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_SPD; + } + + return TRUE; + + } else { + + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + } else { + + /*set MII for 10BaseT and Half Duplex */ + p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + } + + return TRUE; + } + + return FALSE; +} + + +/* + * Name: + * lxt972_InitPhy + * Description: + * MAC starts checking its link by using parallel detection and + * Autonegotiation and the same is set in the MAC configuration registers + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac) +{ + UCHAR ret = TRUE; + + at91rm9200_EmacEnableMDIO (p_mac); + + if (!lxt972_GetLinkSpeed (p_mac)) { + /* Try another time */ + ret = lxt972_GetLinkSpeed (p_mac); + } + + /* Disable PHY Interrupts */ + at91rm9200_EmacWritePhy (p_mac, PHY_LXT971_INT_ENABLE, 0); + + at91rm9200_EmacDisableMDIO (p_mac); + + return (ret); +} + + +/* + * Name: + * lxt972_AutoNegotiate + * Description: + * MAC Autonegotiates with the partner status of same is set in the + * MAC configuration registers + * Arguments: + * dev - pointer to struct net_device + * Return value: + * TRUE - if link status set successfully + * FALSE - if link status not set + */ +UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) +{ + unsigned short value; + + /* Set lxt972 control register */ + if (!at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_CTRL, &value)) + return FALSE; + + /* Restart Auto_negotiation */ + value |= PHY_COMMON_CTRL_RES_AUTO; + if (!at91rm9200_EmacWritePhy (p_mac, PHY_COMMON_CTRL, &value)) + return FALSE; + + /*check AutoNegotiate complete */ + udelay (10000); + at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_STAT, &value); + if (!(value & PHY_COMMON_STAT_AN_COMP)) + return FALSE; + + return (lxt972_GetLinkSpeed (p_mac)); +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/serial.c b/cpu/arm920t/at91rm9200/serial.c new file mode 100644 index 0000000..a281932 --- /dev/null +++ b/cpu/arm920t/at91rm9200/serial.c @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include + +#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1) +#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1 +#endif + +/* ggi thunder */ +#ifdef CONFIG_DBGU +AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU; +#endif +#ifdef CONFIG_USART0 +AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US0; +#endif +#ifdef CONFIG_USART1 +AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1; +#endif + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + int baudrate; + + if ((baudrate = gd->baudrate) <= 0) + baudrate = CONFIG_BAUDRATE; + /* MASTER_CLOCK/(16 * baudrate) */ + us->US_BRGR = (AT91C_MASTER_CLOCK >> 4) / (unsigned)baudrate; +} + +int serial_init (void) +{ + /* make any port initializations specific to this port */ +#ifdef CONFIG_DBGU + *AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; /* PA 31 & 30 */ + *AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */ +#endif +#ifdef CONFIG_USART0 + *AT91C_PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0; + *AT91C_PMC_PCER |= 1 << AT91C_ID_USART0; /* enable clock */ +#endif +#ifdef CONFIG_USART1 + *AT91C_PIOB_PDR = AT91C_PB21_TXD1 | AT91C_PB20_RXD1; + *AT91C_PMC_PCER |= 1 << AT91C_ID_USART1; /* enable clock */ +#endif + serial_setbrg (); + + us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX; + us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; + us->US_MR = + (AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS | + AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT); + us->US_IMR = ~0ul; + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') + serial_putc ('\r'); + while ((us->US_CSR & AT91C_US_TXRDY) == 0); + us->US_THR = c; +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + while ((us->US_CSR & AT91C_US_RXRDY) == 0); + return us->US_RHR; +} + +int serial_tstc (void) +{ + return ((us->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY); +} diff --git a/cpu/arm920t/at91rm9200/usb_ohci.c b/cpu/arm920t/at91rm9200/usb_ohci.c new file mode 100644 index 0000000..5b2c56c --- /dev/null +++ b/cpu/arm920t/at91rm9200/usb_ohci.c @@ -0,0 +1,1635 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * Modified for the MP2USB by (C) Copyright 2005 Eric Benard + * ebenard@eukrea.com - based on s3c24x0's driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTES + * 1 - you MUST define LITTLEENDIAN in the configuration file for the + * board or this driver will NOT work! + * 2 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG + * to activate workaround for bug #41 or this driver will NOT work! + */ + +#include +/* #include no PCI on the S3C24X0 */ + +#ifdef CONFIG_USB_OHCI + +#include + +#include +#include +#include "usb_ohci.h" + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +#define readl(a) (*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) + +#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +#undef DEBUG +#ifdef DEBUG +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#undef SHOW_INFO +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) swap_16(x) +#define m32_swap(x) swap_32(x) + +/* global ohci_t */ +static ohci_t gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +urb_priv_t urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + +static u32 roothub_a (struct ohci *hc) + { return read_roothub (hc, a, 0xfc0fe000); } +static inline u32 roothub_b (struct ohci *hc) + { return readl (&hc->regs->roothub.b); } +static inline u32 roothub_status (struct ohci *hc) + { return readl (&hc->regs->roothub.status); } +static u32 roothub_portstatus (struct ohci *hc, int i) + { return read_roothub (hc, portstatus [i], 0xffe0fce0); } + + +/* forward declaration */ +static int hc_interrupt (void); +static void +td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv (urb_priv_t * urb) +{ + int i; + int last; + struct td * td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +static int sohci_get_current_frame_number (struct usb_device * dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, char * str, int small) +{ + urb_priv_t * purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number (dev), + usb_pipedevice (pipe), + usb_pipeendpoint (pipe), + usb_pipeout (pipe)? 'O': 'I', + usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): + (usb_pipecontrol (pipe)? "CTRL": "BULK"), + purb->actual_length, + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol (pipe)) { + printf (__FILE__ ": cmd(8):"); + for (i = 0; i < 8 ; i++) + printf (" %02x", ((__u8 *) setup) [i]); + printf ("\n"); + } + if (transfer_len > 0 && buffer) { + printf (__FILE__ ": data(%d/%d):", + purb->actual_length, + transfer_len); + len = usb_pipeout (pipe)? + transfer_len: purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf (" %02x", ((__u8 *) buffer) [i]); + printf ("%s\n", i < len? "...": ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ +void ep_print_int_eds (ohci_t *ohci, char * str) { + int i, j; + __u32 * ed_p; + for (i= 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table [i]); + if (*ed_p == 0) + continue; + printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + ed_t *ed = (ed_t *)m32_swap(ed_p); + printf (" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf ("\n"); + } +} + +static void ohci_dump_intr_mask (char *label, __u32 mask) +{ + dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds (char *label, __u32 value) +{ + ed_t *edp = (ed_t *)value; + + if (value) { + dbg ("%s %08x", label, value); + dbg ("%08x", edp->hwINFO); + dbg ("%08x", edp->hwTailP); + dbg ("%08x", edp->hwHeadP); + dbg ("%08x", edp->hwNextED); + } +} + +static char * hcfs2string (int state) +{ + switch (state) { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status (ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl (®s->revision) & 0xff; + if (temp != 0x10) + dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl (®s->control); + dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string (temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + + temp = readl (®s->cmdstatus); + dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + + ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); + ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); + + maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); + + maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); + maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); + + maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); + maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); + + maybe_print_eds ("donehead", readl (®s->donehead)); +} + +static void ohci_dump_roothub (ohci_t *controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); +#ifdef CONFIG_AT91C_PQFP_UHPBUG + ndp = (ndp == 2) ? 1:0; +#endif + if (verbose) { + dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b (controller); + dbg ("roothub.b: %08x PPCM=%04x DR=%04x", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status (controller); + dbg ("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump (ohci_t *controller, int verbose) +{ + dbg ("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status (controller); + if (verbose) + ep_print_int_eds (controller, "hcca"); + dbg ("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub (controller, 1); +} + + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + ohci_t *ohci; + ed_t * ed; + urb_priv_t *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* every endpoint has a ed, locate and fill it */ + if (!(ed = ep_add_ed (dev, pipe))) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype (pipe)) { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0)? 2: + (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc (dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv (purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv (purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link (ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number (struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + + return m16_swap (ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel (ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel (ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink (ohci_t *ohci, ed_t *ed) +{ + ed->hwINFO |= m32_swap (OHCI_ED_SKIP); + + switch (ed->type) { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_controltail == ed) { + ohci->ed_controltail = ed->ed_prev; + } else { + ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_bulktail == ed) { + ohci->ed_bulktail = ed->ed_prev; + } else { + ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + } + ed->state = ED_UNLINK; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, + * but the USB stack is a little bit stateless so we do it at every transaction + * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK + * in all other cases the state is left unchanged + * the ed info fields are setted anyway even though most of them should not change */ + +static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | + (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc (usb_dev); + ed->hwTailP = m32_swap (td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype (pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = m32_swap (usb_pipedevice (pipe) + | usb_pipeendpoint (pipe) << 7 + | (usb_pipeisoc (pipe)? 0x8000: 0) + | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) + | usb_pipeslow (pipe) << 13 + | usb_maxpacket (usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill (ohci_t *ohci, unsigned int info, + void *data, int len, + struct usb_device *dev, int index, urb_priv_t *urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td [index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32)data; +#ifdef OHCI_FILL_TRACE + if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); + printf("\n"); + } +#endif + if (!len) + data = 0; + + td->hwINFO = m32_swap (info); + td->hwCBP = m32_swap (data); + if (data) + td->hwBE = m32_swap (data + len - 1); + else + td->hwBE = 0; + td->hwNextTD = m32_swap (td_pt); + td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ + +static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ + if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = 0; + + switch (usb_pipetype (pipe)) { + case PIPE_BULK: + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while(data_len > 4096) { + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill (ohci, info, setup, 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout (pipe)? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill (ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill (ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(td_t * td) +{ + __u32 tdINFO, tdBE, tdCBP; + urb_priv_t *lurb_priv = &urb_priv; + + tdINFO = m32_swap (td->hwINFO); + tdBE = m32_swap (td->hwBE); + tdCBP = m32_swap (td->hwCBP); + + + if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && + ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { + if (tdBE != 0) { + if (td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ + +static td_t * dl_reverse_done_list (ohci_t *ohci) +{ + __u32 td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + urb_priv_t *lurb_priv = NULL; + + td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; + ohci->hcca->done_head = 0; + + while (td_list_hc) { + td_list = (td_t *)td_list_hc; + + if (TD_CC_GET (m32_swap (td_list->hwINFO))) { + lurb_priv = &urb_priv; + dbg(" USB-error/status: %x : %p", + TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); + if (td_list->ed->hwHeadP & m32_swap (0x1)) { + if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { + td_list->ed->hwHeadP = + (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | + (td_list->ed->hwHeadP & m32_swap (0x2)); + lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; + } else + td_list->ed->hwHeadP &= m32_swap (0xfffffff2); + } + } + + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; + } + return td_list; +} + +/*-------------------------------------------------------------------------*/ + +/* td done list */ +static int dl_done_list (ohci_t *ohci, td_t *td_list) +{ + td_t *td_list_next = NULL; + ed_t *ed; + int cc = 0; + int stat = 0; + /* urb_t *urb; */ + urb_priv_t *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + + while (td_list) { + td_list_next = td_list->next_dl_td; + + lurb_priv = &urb_priv; + tdINFO = m32_swap (td_list->hwINFO); + + ed = td_list->ed; + + dl_transfer_length(td_list); + + /* error code of transfer */ + cc = TD_CC_GET (tdINFO); + if (cc != 0) { + dbg("ConditionCode %#x", cc); + stat = cc_to_error[cc]; + } + + if (ed->state != ED_NEW) { + edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; + edTailP = m32_swap (ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink (ohci, ed); + } + + td_list = td_list_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + __u32 temp, ndp, i; + int res; + + res = -1; + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); +#ifdef CONFIG_AT91C_PQFP_UHPBUG + ndp = (ndp == 2) ? 1:0; +#endif + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && + ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + void * data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u32 datab[4]; + __u8 *data_buf = (__u8 *)datab; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + +#ifdef DEBUG +urb_priv.actual_length = 0; +pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = m16_swap (cmd->value); + wIndex = m16_swap (cmd->index); + wLength = m16_swap (cmd->length); + + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(__u16 *) data_buf = m16_swap (1); OK (2); + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_CLASS: + *(__u32 *) data_buf = m32_swap ( + RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK (4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + OK(0); + case (RH_C_HUB_OVER_CURRENT): + WR_RH_STAT(RH_HS_OCIC); OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_POCI); OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); + case (RH_C_PORT_CONNECTION): + WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); + case (RH_C_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_PESC); OK (0); + case (RH_C_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); + case (RH_C_PORT_OVER_CURRENT): + WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); + case (RH_C_PORT_RESET): + WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); + case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PRS); + OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PES ); + OK (0); + } + break; + + case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; OK(len); + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; OK(len); + case (0x03): /* string descriptors */ + if(wValue==0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if(wValue==0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a (&gohci); + + data_buf [0] = 9; /* min length; */ + data_buf [1] = 0x29; + data_buf [2] = temp & RH_A_NDP; +#ifdef CONFIG_AT91C_PQFP_UHPBUG + data_buf [2] = (data_buf [2] == 2) ? 1:0; +#endif + data_buf [3] = 0; + if (temp & RH_A_PSM) /* per-port power switching? */ + data_buf [3] |= 0x1; + if (temp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf [3] |= 0x10; + else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + data_buf [3] |= 0x8; + + /* corresponds to data_buf[4-7] */ + datab [1] = 0; + data_buf [5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b (&gohci); + data_buf [7] = temp & RH_B_DR; + if (data_buf [2] < 7) { + data_buf [8] = 0xff; + } else { + data_buf [0] += 2; + data_buf [8] = (temp & RH_B_DR) >> 8; + data_buf [10] = data_buf [9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf [0], wLength)); + OK (len); + } + + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); + + case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); + + default: + dbg ("unsupported root hub command"); + stat = USB_ST_STALLED; + } + +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#else + wait_ms(1); +#endif + + len = min_t(int, len, leni); + if (data != data_buf) + memcpy (data, data_buf, len); + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG + if (transfer_len) + urb_priv.actual_length = transfer_len; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); +#else + wait_ms(1); +#endif + + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if (!maxsize) { + err("submit_common_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { + err("sohci_submit_job failed"); + return -1; + } + + wait_ms(10); + /* ohci_dump_status(&gohci); */ + + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if (usb_pipetype (pipe) == PIPE_BULK) + timeout = BULK_TO; + else + timeout = 100; + + /* wait for it to complete */ + for (;;) { + /* check whether the controller is done */ + stat = hc_interrupt(); + if (stat < 0) { + stat = USB_ST_CRC_ERR; + break; + } + if (stat >= 0 && stat != 0xff) { + /* 0xff is returned for an SF-interrupt */ + break; + } + if (--timeout) { + wait_ms(1); + } else { + err("CTL:TIMEOUT "); + stat = USB_ST_CRC_ERR; + break; + } + } + /* we got an Root Hub Status Change interrupt */ + if (got_rhsc) { +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + got_rhsc = 0; + /* abuse timeout */ + timeout = rh_check_port_status(&gohci); + if (timeout >= 0) { +#if 0 /* this does nothing useful, but leave it here in case that changes */ + /* the called routine adds 1 to the passed value */ + usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); +#endif + /* + * XXX + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } + + dev->status = stat; + dev->act_len = transfer_len; + +#ifdef DEBUG + pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + + /* free TDs in urb_priv */ + urb_free_priv (&urb_priv); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + + info("submit_control_msg"); +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if (!maxsize) { + err("submit_control_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset (ohci_t *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + dbg("%s\n", __FUNCTION__); + + if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ + writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ + info("USB HC TakeOver from SMM"); + while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { + wait_ms (10); + if (--smm_timeout == 0) { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", + ohci->slot_name, + readl(&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + writel (0, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel (OHCI_HCR, &ohci->regs->cmdstatus); + while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { + if (--timeout == 0) { + err("USB HC reset timed out!"); + return -1; + } + udelay (1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start (ohci_t * ohci) +{ + __u32 mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + + writel (0, &ohci->regs->ed_controlhead); + writel (0, &ohci->regs->ed_bulkhead); + + writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + + fminterval = 0x2edf; + writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel (fminterval, &ohci->regs->fminterval); + writel (0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel (mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel (mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel (mask, &ohci->regs->intrenable); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, + &ohci->regs->roothub.a); + writel (RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay ((roothub_a (ohci) >> 23) & 0x1fe); + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static int +hc_interrupt (void) +{ + ohci_t *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { + ints = OHCI_INTR_WDH; + } else { + ints = readl (®s->intrstatus); + } + + /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ + + if (ints & OHCI_INTR_RHSC) { + got_rhsc = 1; + } + + if (ints & OHCI_INTR_UE) { + ohci->disabled++; + err ("OHCI Unrecoverable Error, controller usb-%s disabled", + ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ + +#ifdef DEBUG + ohci_dump (ohci, 1); +#else + wait_ms(1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset (ohci); + return -1; + } + + if (ints & OHCI_INTR_WDH) { + wait_ms(1); + writel (OHCI_INTR_WDH, ®s->intrdisable); + stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); + writel (OHCI_INTR_WDH, ®s->intrenable); + } + + if (ints & OHCI_INTR_SO) { + dbg("USB Schedule overrun\n"); + writel (OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) { + unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; + wait_ms(1); + writel (OHCI_INTR_SF, ®s->intrdisable); + if (ohci->ed_rm_list[frame] != NULL) + writel (OHCI_INTR_SF, ®s->intrenable); + stat = 0xff; + } + + writel (ints, ®s->intrstatus); + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci (ohci_t *ohci) +{ + dbg ("USB HC release ohci usb-%s", ohci->slot_name); + + if (!ohci->disabled) + hc_reset (ohci); +} + +/*-------------------------------------------------------------------------*/ + +/* + * low level initalisation routine, called from usb.c + */ +static char ohci_inited = 0; + +int usb_lowlevel_init(void) +{ + /* + * Enable USB host clock. + */ + *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */ + *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */ + + memset (&gohci, 0, sizeof (ohci_t)); + memset (&urb_priv, 0, sizeof (urb_priv_t)); + + /* align the storage */ + if ((__u32)&ghcca[0] & 0xff) { + err("HCCA not aligned!!"); + return -1; + } + phcca = &ghcca[0]; + info("aligned ghcca %p", phcca); + memset(&ohci_dev, 0, sizeof(struct ohci_device)); + if ((__u32)&ohci_dev.ed[0] & 0x7) { + err("EDs not aligned!!"); + return -1; + } + memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); + if ((__u32)gtd & 0x7) { + err("TDs not aligned!!"); + return -1; + } + ptd = gtd; + gohci.hcca = phcca; + memset (phcca, 0, sizeof (struct ohci_hcca)); + + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + gohci.regs = (struct ohci_regs *)AT91_USB_HOST_BASE; + + gohci.flags = 0; + gohci.slot_name = "at91rm9200"; + + if (hc_reset (&gohci) < 0) { + hc_release_ohci (&gohci); + /* Initialization failed */ + *AT91C_PMC_PCER = AT91C_ID_UHP; + *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ + return -1; + } + + /* FIXME this is a second HC reset; why?? */ +/* writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); + wait_ms (10);*/ + + if (hc_start (&gohci) < 0) { + err ("can't start usb-%s", gohci.slot_name); + hc_release_ohci (&gohci); + /* Initialization failed */ + *AT91C_PMC_PCER = AT91C_ID_UHP; + *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ + return -1; + } + +#ifdef DEBUG + ohci_dump (&gohci, 1); +#else + wait_ms(1); +#endif + ohci_inited = 1; + return 0; +} + +int usb_lowlevel_stop(void) +{ + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if (!ohci_inited) + return 0; + /* TODO release any interrupts, etc. */ + /* call hc_release_ohci() here ? */ + hc_reset (&gohci); + /* may not want to do this */ + *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; + *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ + return 0; +} + +#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/arm920t/at91rm9200/usb_ohci.h b/cpu/arm920t/at91rm9200/usb_ohci.h new file mode 100644 index 0000000..ecb4e93 --- /dev/null +++ b/cpu/arm920t/at91rm9200/usb_ohci.h @@ -0,0 +1,419 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +/* ED States */ + +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute((aligned(16))); +typedef struct ed ed_t; + + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u16 hwPSW[MAXPSW]; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute((aligned(256))); + + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute((aligned(32))); + + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct +{ + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + + +typedef struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma;*/ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +td_t gtd[NUM_TD+1]; +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td * +td_alloc (struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) + { + if (ptd[i].usb_dev == NULL) + { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void +ed_free (struct ed *ed) +{ + ed->usb_dev = NULL; +} diff --git a/cpu/arm920t/config.mk b/cpu/arm920t/config.mk new file mode 100644 index 0000000..8db4adb --- /dev/null +++ b/cpu/arm920t/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c new file mode 100644 index 0000000..2f7963d --- /dev/null +++ b/cpu/arm920t/cpu.c @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM920T Technical reference Manual */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ + +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} + +#ifdef USE_920T_MMU +/* It makes no sense to use the dcache if the MMU is not enabled */ +void dcache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_DC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + reg &= ~C1_DC; + write_p15_c1 (reg); +} + +int dcache_status (void) +{ + return (read_p15_c1 () & C1_DC) != 0; +} +#endif diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile new file mode 100644 index 0000000..8865f82 --- /dev/null +++ b/cpu/arm920t/imx/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(SOC).a + +OBJS = generic.o interrupts.o serial.o speed.o + +all: .depend $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm920t/imx/generic.c b/cpu/arm920t/imx/generic.c new file mode 100644 index 0000000..aa7c8c1 --- /dev/null +++ b/cpu/arm920t/imx/generic.c @@ -0,0 +1,90 @@ +/* + * arch/arm/mach-imx/generic.c + * + * author: Sascha Hauer + * Created: april 20th, 2004 + * Copyright: Synertronixx GmbH + * + * Common code for i.MX machines + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#ifdef CONFIG_IMX + +#include + +void imx_gpio_mode(int gpio_mode) +{ + unsigned int pin = gpio_mode & GPIO_PIN_MASK; + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5; + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10; + unsigned int tmp; + + /* Pullup enable */ + if(gpio_mode & GPIO_PUEN) + PUEN(port) |= (1< + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined (CONFIG_IMX) + +#include +#include + +int interrupt_init (void) +{ + int i; + /* setup GP Timer 1 */ + TCTL1 = TCTL_SWR; + for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */ + TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ + TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ + + reset_timer_masked(); + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked (); +} + +void set_timer (ulong t) +{ + /* nop */ +} + +void reset_timer_masked (void) +{ + TCTL1 &= ~TCTL_TEN; + TCTL1 |= TCTL_TEN; /* Enable timer */ +} + +ulong get_timer_masked (void) +{ + return TCN1; +} + +void udelay_masked (unsigned long usec) +{ + ulong endtime = get_timer_masked() + usec; + signed long diff; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +void udelay (unsigned long usec) +{ + udelay_masked(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + + return tbclk; +} + +/* + * Reset the cpu by setting up the watchdog timer and let him time out + */ +void reset_cpu (ulong ignored) +{ + /* Disable watchdog and set Time-Out field to 0 */ + WCR = 0x00000000; + + /* Write Service Sequence */ + WSR = 0x00005555; + WSR = 0x0000AAAA; + + /* Enable watchdog */ + WCR = 0x00000001; + + while (1); + /*NOTREACHED*/ +} + +#endif /* defined (CONFIG_IMX) */ diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c new file mode 100644 index 0000000..9dbaa56 --- /dev/null +++ b/cpu/arm920t/imx/serial.c @@ -0,0 +1,201 @@ +/* + * (c) 2004 Sascha Hauer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#if defined (CONFIG_IMX) + +#include + +#ifndef CONFIG_IMX_SERIAL_NONE + +#if defined CONFIG_IMX_SERIAL1 +#define UART_BASE IMX_UART1_BASE +#elif defined CONFIG_IMX_SERIAL2 +#define UART_BASE IMX_UART2_BASE +#else +#error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE" +#endif + +struct imx_serial { + volatile uint32_t urxd[16]; + volatile uint32_t utxd[16]; + volatile uint32_t ucr1; + volatile uint32_t ucr2; + volatile uint32_t ucr3; + volatile uint32_t ucr4; + volatile uint32_t ufcr; + volatile uint32_t usr1; + volatile uint32_t usr2; + volatile uint32_t uesc; + volatile uint32_t utim; + volatile uint32_t ubir; + volatile uint32_t ubmr; + volatile uint32_t ubrc; + volatile uint32_t bipr[4]; + volatile uint32_t bmpr[4]; + volatile uint32_t uts; +}; + +void serial_setbrg (void) +{ + serial_init(); +} + +extern void imx_gpio_mode(int gpio_mode); + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; +#ifdef CONFIG_IMX_SERIAL1 + imx_gpio_mode(PC11_PF_UART1_TXD); + imx_gpio_mode(PC12_PF_UART1_RXD); +#else + imx_gpio_mode(PB30_PF_UART2_TXD); + imx_gpio_mode(PB31_PF_UART2_RXD); +#endif + + /* Disable UART */ + base->ucr1 &= ~UCR1_UARTEN; + + /* Set to default POR state */ + + base->ucr1 = 0x00000004; + base->ucr2 = 0x00000000; + base->ucr3 = 0x00000000; + base->ucr4 = 0x00008040; + base->uesc = 0x0000002B; + base->utim = 0x00000000; + base->ubir = 0x00000000; + base->ubmr = 0x00000000; + base->uts = 0x00000000; + /* Set clocks */ + base->ucr4 |= UCR4_REF16; + + /* Configure FIFOs */ + base->ufcr = 0xa81; + + /* Set the numerator value minus one of the BRM ratio */ + base->ubir = (CONFIG_BAUDRATE / 100) - 1; + + /* Set the denominator value minus one of the BRM ratio */ + base->ubmr = 10000 - 1; + + /* Set to 8N1 */ + base->ucr2 &= ~UCR2_PREN; + base->ucr2 |= UCR2_WS; + base->ucr2 &= ~UCR2_STPB; + + /* Ignore RTS */ + base->ucr2 |= UCR2_IRTS; + + /* Enable UART */ + base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN; + + /* Enable FIFOs */ + base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; + + /* Clear status flags */ + base->usr2 |= USR2_ADET | + USR2_DTRF | + USR2_IDLE | + USR2_IRINT | + USR2_WAKE | + USR2_RTSF | + USR2_BRCD | + USR2_ORE | + USR2_RDR; + + /* Clear status flags */ + base->usr1 |= USR1_PARITYERR | + USR1_RTSD | + USR1_ESCF | + USR1_FRAMERR | + USR1_AIRINT | + USR1_AWAKE; + return (0); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is successful, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + unsigned char ch; + + while(base->uts & UTS_RXEMPTY); + + ch = (char)base->urxd[0]; + + return ch; +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ +} +#endif + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + + /* Wait for Tx FIFO not full */ + while (base->uts & UTS_TXFULL); + + base->utxd[0] = c; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc (void) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + + /* If receive fifo is empty, return false */ + if (base->uts & UTS_RXEMPTY) + return 0; + return 1; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} +#endif /* CONFIG_IMX_SERIAL_NONE */ +#endif /* defined CONFIG_IMX */ diff --git a/cpu/arm920t/imx/speed.c b/cpu/arm920t/imx/speed.c new file mode 100644 index 0000000..1e29698 --- /dev/null +++ b/cpu/arm920t/imx/speed.c @@ -0,0 +1,102 @@ +/* + * + * (c) 2004 Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#if defined (CONFIG_IMX) + +#include + +/* ------------------------------------------------------------------------- */ +/* NOTE: This describes the proper use of this file. + * + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. + * SH FIXME: 16780000 in our case + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of + * the specified bus in HZ. + */ +/* ------------------------------------------------------------------------- */ + +ulong get_systemPLLCLK(void) +{ + /* FIXME: We assume System_SEL = 0 here */ + u32 spctl0 = SPCTL0; + u32 mfi = (spctl0 >> 10) & 0xf; + u32 mfn = spctl0 & 0x3f; + u32 mfd = (spctl0 >> 16) & 0x3f; + u32 pd = (spctl0 >> 26) & 0xf; + + mfi = mfi<=5 ? 5 : mfi; + + return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); +} + +ulong get_mcuPLLCLK(void) +{ + /* FIXME: We assume System_SEL = 0 here */ + u32 mpctl0 = MPCTL0; + u32 mfi = (mpctl0 >> 10) & 0xf; + u32 mfn = mpctl0 & 0x3f; + u32 mfd = (mpctl0 >> 16) & 0x3f; + u32 pd = (mpctl0 >> 26) & 0xf; + + mfi = mfi<=5 ? 5 : mfi; + + return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); +} + +ulong get_FCLK(void) +{ + return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK(); +} + +/* return HCLK frequency */ +ulong get_HCLK(void) +{ + u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; + printf("bclkdiv: %d\n", bclkdiv); + return get_systemPLLCLK() / bclkdiv; +} + +/* return BCLK frequency */ +ulong get_BCLK(void) +{ + return get_HCLK(); +} + +ulong get_PERCLK1(void) +{ + return get_systemPLLCLK() / (((PCDR) & 0xf)+1); +} + +ulong get_PERCLK2(void) +{ + return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1); +} + +ulong get_PERCLK3(void) +{ + return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1); +} + +#endif /* defined (CONFIG_IMX) */ diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c new file mode 100644 index 0000000..a43a3ed --- /dev/null +++ b/cpu/arm920t/interrupts.c @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ +#if defined (CONFIG_USE_IRQ) && defined (CONFIG_ARCH_INTEGRATOR) + /* ASSUMED to be a timer interrupt */ + /* Just clear it - count handled in */ + /* integratorap.c */ + *(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0; +#else + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +#endif +} diff --git a/cpu/arm920t/ks8695/Makefile b/cpu/arm920t/ks8695/Makefile new file mode 100644 index 0000000..ac49060 --- /dev/null +++ b/cpu/arm920t/ks8695/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(SOC).a + +OBJS = interrupts.o serial.o +SOBJS = lowlevel_init.o + +all: .depend $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm920t/ks8695/interrupts.c b/cpu/arm920t/ks8695/interrupts.c new file mode 100644 index 0000000..883d689 --- /dev/null +++ b/cpu/arm920t/ks8695/interrupts.c @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2004-2005, Greg Ungerer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * Handy KS8695 register access functions. + */ +#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a))) +#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v) + +int timer_inited; +ulong timer_ticks; + +int interrupt_init (void) +{ + /* nothing happens here - we don't setup any IRQs */ + return (0); +} + +/* + * Initial timer set constants. Nothing complicated, just set for a 1ms + * tick. + */ +#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1) +#define TIMER_COUNT (TIMER_INTERVAL / 2) +#define TIMER_PULSE TIMER_COUNT + +void reset_timer_masked(void) +{ + /* Set the hadware timer for 1ms */ + ks8695_write(KS8695_TIMER1, TIMER_COUNT); + ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); + ks8695_write(KS8695_TIMER_CTRL, 0x2); + timer_ticks = 0; + timer_inited++; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer_masked(void) +{ + /* Check for timer wrap */ + if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) { + /* Clear interrupt condition */ + ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1); + timer_ticks++; + } + return timer_ticks; +} + +ulong get_timer(ulong base) +{ + return (get_timer_masked() - base); +} + +void set_timer(ulong t) +{ + timer_ticks = t; +} + +void udelay(ulong usec) +{ + ulong start = get_timer_masked(); + ulong end; + + if (!timer_inited) + reset_timer(); + + /* Only 1ms resolution :-( */ + end = usec / 1000; + while (get_timer(start) < end) + ; +} + +void reset_cpu (ulong ignored) +{ + ulong tc; + + /* Set timer0 to watchdog, and let it timeout */ + tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2; + ks8695_write(KS8695_TIMER_CTRL, tc); + ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff)); + ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1)); + + /* Should only wait here till watchdog resets */ + for (;;) + ; +} diff --git a/cpu/arm920t/ks8695/lowlevel_init.S b/cpu/arm920t/ks8695/lowlevel_init.S new file mode 100644 index 0000000..e9f1227 --- /dev/null +++ b/cpu/arm920t/ks8695/lowlevel_init.S @@ -0,0 +1,205 @@ +/* + * lowlevel_init.S - basic hardware initialization for the KS8695 CPU + * + * Copyright (c) 2004-2005, Greg Ungerer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +/* + ************************************************************************* + * + * Handy dandy macros + * + ************************************************************************* + */ + +/* Delay a bit */ +.macro DELAY_FOR cycles, reg0 + ldr \reg0, =\cycles + subs \reg0, \reg0, #1 + subne pc, pc, #0xc +.endm + +/* + ************************************************************************* + * + * Some local storage. + * + ************************************************************************* + */ + +/* Should we boot with an interactive console or not */ +.globl serial_console + +/* + ************************************************************************* + * + * Raw hardware initialization code. The important thing is to get + * SDRAM setup and running. We do some other basic things here too, + * like getting the PLL set for high speed, and init the LEDs. + * + ************************************************************************* + */ + +.globl lowlevel_init +lowlevel_init: + +#if DEBUG + /* + * enable UART for early debug trace + */ + ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR) + mov r2, #0xd9 + str r2, [r1] /* 115200 baud */ + ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL) + mov r2, #0x03 + str r2, [r1] /* 8 data bits, no parity, 1 stop */ + ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) + mov r2, #0x41 + str r2, [r1] /* write 'A' */ +#endif +#if DEBUG + ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) + mov r2, #0x42 + str r2, [r1] +#endif + + /* + * remap the memory and flash regions. we want to end up with + * ram from address 0, and flash at 32MB. + */ + ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0) + ldr r2, =0xbfc00040 + str r2, [r1] /* large flash map */ + ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */ +highflash: + ldr r2, =0x8fe00040 + str r2, [r1] /* remap flash range */ + + /* + * remap the second select region to the 4MB immediately after + * the first region. This way if you have a larger flash (say 8Mb) + * then you can have it all mapped nicely. Has no effect if you + * only have a 4Mb or smaller flash. + */ + ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1) + ldr r2, =0x9fe40040 + str r2, [r1] /* remap flash2 region, contiguous */ + ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) + ldr r2, =0x30000005 + str r2, [r1] /* enable both flash selects */ + +#ifdef CONFIG_CM41xx + /* + * map the second flash chip, using the external IO lines. + */ + ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0) + ldr r2, =0xafe80b6d + str r2, [r1] /* remap io0 region, contiguous */ + ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1) + ldr r2, =0xbfec0b6d + str r2, [r1] /* remap io1 region, contiguous */ + ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) + ldr r2, =0x30050005 + str r2, [r1] /* enable second flash */ +#endif + + /* + * before relocating, we have to setup RAM timing + */ + ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0) +#if (PHYS_SDRAM_1_SIZE == 0x02000000) + ldr r2, =0x7fc0000e /* 32MB */ +#else + ldr r2, =0x3fc0000e /* 16MB */ +#endif + str r2, [r1] /* configure sdram bank0 setup */ + ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1) + mov r2, #0 + str r2, [r1] /* configure sdram bank1 setup */ + + ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL) + ldr r2, =0x0000000a + str r2, [r1] /* set RAS/CAS timing */ + + ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) + ldr r2, =0x00030000 + str r2, [r1] /* send NOP command */ + DELAY_FOR 0x100, r0 + ldr r2, =0x00010000 + str r2, [r1] /* send PRECHARGE-ALL */ + DELAY_FOR 0x100, r0 + + ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH) + ldr r2, =0x00000020 + str r2, [r1] /* set for fast refresh */ + DELAY_FOR 0x100, r0 + ldr r2, =0x00000190 + str r2, [r1] /* set normal refresh timing */ + + ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) + ldr r2, =0x00020033 + str r2, [r1] /* send mode command */ + DELAY_FOR 0x100, r0 + ldr r2, =0x01f00000 + str r2, [r1] /* enable sdram fifos */ + + /* + * set pll to top speed + */ + ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK) + mov r2, #0 + str r2, [r1] /* set pll clock to 166MHz */ + + ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0) + ldr r2, [r1] /* Get switch ctrl0 register */ + and r2, r2, #0x0fc00000 /* Mask out LED control bits */ + orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */ + str r2, [r1] + +#ifdef CONFIG_CM4008 + ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE) + ldr r2, =0x0000fe30 + str r2, [r1] /* enable LED's as outputs */ + ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA) + ldr r2, =0x0000fe20 + str r2, [r1] /* turn on power LED */ +#endif +#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx) + ldr r2, [r1] /* get current GPIO input data */ + tst r2, #0x8 /* check if "erase" depressed */ + beq nobutton + mov r2, #0 /* be quiet on boot, no console */ + ldr r1, =serial_console + str r2, [r1] +nobutton: +#endif + + add lr, lr, #0x02000000 /* flash is now mapped high */ + add ip, ip, #0x02000000 /* this is a hack */ + mov pc, lr /* all done, return */ + +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/cpu/arm920t/ks8695/serial.c b/cpu/arm920t/ks8695/serial.c new file mode 100644 index 0000000..0dd91e7 --- /dev/null +++ b/cpu/arm920t/ks8695/serial.c @@ -0,0 +1,116 @@ +/* + * serial.c -- KS8695 serial driver + * + * (C) Copyright 2004, Greg Ungerer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include + +#ifndef CONFIG_SERIAL1 +#error "Bad: you didn't configure serial ..." +#endif + +/* + * Define the UART hardware register access structure. + */ +struct ks8695uart { + unsigned int RX; /* 0x00 - Receive data (r) */ + unsigned int TX; /* 0x04 - Transmit data (w) */ + unsigned int FCR; /* 0x08 - Fifo Control (r/w) */ + unsigned int LCR; /* 0x0c - Line Control (r/w) */ + unsigned int MCR; /* 0x10 - Modem Control (r/w) */ + unsigned int LSR; /* 0x14 - Line Status (r/w) */ + unsigned int MSR; /* 0x18 - Modem Status (r/w) */ + unsigned int BD; /* 0x1c - Baud Rate (r/w) */ + unsigned int SR; /* 0x20 - Status (r/w) */ +}; + +#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER)) +#define KS8695_UART_CLK 25000000 + + +/* + * Under some circumstances we want to be "quiet" and not issue any + * serial output - though we want u-boot to otherwise work and behave + * the same. By default be noisy. + */ +int serial_console = 1; + + +void serial_setbrg(void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile struct ks8695uart *uartp = KS8695_UART_ADDR; + + /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/ + uartp->BD = KS8695_UART_CLK / gd->baudrate; + uartp->LCR = KS8695_UART_LINEC_WLEN8; +} + +int serial_init(void) +{ + serial_console = 1; + serial_setbrg(); + return 0; +} + +void serial_raw_putc(const char c) +{ + volatile struct ks8695uart *uartp = KS8695_UART_ADDR; + int i; + + for (i = 0; (i < 0x100000); i++) { + if (uartp->LSR & KS8695_UART_LINES_TXFE) + break; + } + + uartp->TX = c; +} + +void serial_putc(const char c) +{ + if (serial_console) { + serial_raw_putc(c); + if (c == '\n') + serial_raw_putc('\r'); + } +} + +int serial_tstc(void) +{ + volatile struct ks8695uart *uartp = KS8695_UART_ADDR; + if (serial_console) + return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0); + return 0; +} + +void serial_puts(const char *s) +{ + char c; + while ((c = *s++) != 0) + serial_putc(c); +} + +int serial_getc(void) +{ + volatile struct ks8695uart *uartp = KS8695_UART_ADDR; + + while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0) + ; + return (uartp->RX); +} diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile new file mode 100644 index 0000000..af9e4ef --- /dev/null +++ b/cpu/arm920t/s3c24x0/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(SOC).a + +OBJS = i2c.o interrupts.o serial.o speed.o \ + usb_ohci.o + +all: .depend $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm920t/s3c24x0/i2c.c b/cpu/arm920t/s3c24x0/i2c.c new file mode 100644 index 0000000..ef56cd1 --- /dev/null +++ b/cpu/arm920t/s3c24x0/i2c.c @@ -0,0 +1,447 @@ +/* + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This code should work for both the S3C2400 and the S3C2410 + * as they seem to have the same I2C controller inside. + * The different address mapping is handled by the s3c24xx.h files below. + */ + +#include + +#ifdef CONFIG_DRIVER_S3C24X0_I2C + +#if defined(CONFIG_S3C2400) +#include +#elif defined(CONFIG_S3C2410) +#include +#endif +#include + +#ifdef CONFIG_HARD_I2C + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_OK 0 +#define I2C_NOK 1 +#define I2C_NACK 2 +#define I2C_NOK_LA 3 /* Lost arbitration */ +#define I2C_NOK_TOUT 4 /* time out */ + +#define I2CSTAT_BSY 0x20 /* Busy bit */ +#define I2CSTAT_NACK 0x01 /* Nack bit */ +#define I2CCON_IRPND 0x10 /* Interrupt pending bit */ +#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ +#define I2C_MODE_MR 0x80 /* Master Receive Mode */ +#define I2C_START_STOP 0x20 /* START / STOP */ +#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ + +#define I2C_TIMEOUT 1 /* 1 second */ + + +static int GetI2CSDA(void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + +#ifdef CONFIG_S3C2410 + return (gpio->GPEDAT & 0x8000) >> 15; +#endif +#ifdef CONFIG_S3C2400 + return (gpio->PGDAT & 0x0020) >> 5; +#endif +} + +#if 0 +static void SetI2CSDA(int x) +{ + rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15; +} +#endif + +static void SetI2CSCL(int x) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + +#ifdef CONFIG_S3C2410 + gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; +#endif +#ifdef CONFIG_S3C2400 + gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6; +#endif +} + + +static int WaitForXfer (void) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + int i, status; + + i = I2C_TIMEOUT * 10000; + status = i2c->IICCON; + while ((i > 0) && !(status & I2CCON_IRPND)) { + udelay (100); + status = i2c->IICCON; + i--; + } + + return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; +} + +static int IsACK (void) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + + return (!(i2c->IICSTAT & I2CSTAT_NACK)); +} + +static void ReadWriteByte (void) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + + i2c->IICCON &= ~I2CCON_IRPND; +} + +void i2c_init (int speed, int slaveadd) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO (); + ulong freq, pres = 16, div; + int i, status; + + /* wait for some time to give previous transfer a chance to finish */ + + i = I2C_TIMEOUT * 1000; + status = i2c->IICSTAT; + while ((i > 0) && (status & I2CSTAT_BSY)) { + udelay (1000); + status = i2c->IICSTAT; + i--; + } + + if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) { +#ifdef CONFIG_S3C2410 + ulong old_gpecon = gpio->GPECON; +#endif +#ifdef CONFIG_S3C2400 + ulong old_gpecon = gpio->PGCON; +#endif + /* bus still busy probably by (most) previously interrupted transfer */ + +#ifdef CONFIG_S3C2410 + /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ + gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000; +#endif +#ifdef CONFIG_S3C2400 + /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ + gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00; +#endif + + /* toggle I2CSCL until bus idle */ + SetI2CSCL (0); + udelay (1000); + i = 10; + while ((i > 0) && (GetI2CSDA () != 1)) { + SetI2CSCL (1); + udelay (1000); + SetI2CSCL (0); + udelay (1000); + i--; + } + SetI2CSCL (1); + udelay (1000); + + /* restore pin functions */ +#ifdef CONFIG_S3C2410 + gpio->GPECON = old_gpecon; +#endif +#ifdef CONFIG_S3C2400 + gpio->PGCON = old_gpecon; +#endif + } + + /* calculate prescaler and divisor values */ + freq = get_PCLK (); + if ((freq / pres / (16 + 1)) > speed) + /* set prescaler to 512 */ + pres = 512; + + div = 0; + while ((freq / pres / (div + 1)) > speed) + div++; + + /* set prescaler, divisor according to freq, also set + * ACKGEN, IRQ */ + i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); + + /* init to SLAVE REVEIVE and set slaveaddr */ + i2c->IICSTAT = 0; + i2c->IICADD = slaveadd; + /* program Master Transmit (and implicit STOP) */ + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; + +} + +/* + * cmd_type is 0 for write, 1 for read. + * + * addr_len can take any value from 0-255, it is only limited + * by the char, we could make it larger if needed. If it is + * 0 we skip the address write cycle. + */ +static +int i2c_transfer (unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], unsigned short data_len) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + int i, status, result; + + if (data == 0 || data_len == 0) { + /*Don't support data transfer of no length or to address 0 */ + printf ("i2c_transfer: bad call\n"); + return I2C_NOK; + } + + /* Check I2C bus idle */ + i = I2C_TIMEOUT * 1000; + status = i2c->IICSTAT; + while ((i > 0) && (status & I2CSTAT_BSY)) { + udelay (1000); + status = i2c->IICSTAT; + i--; + } + + if (status & I2CSTAT_BSY) + return I2C_NOK_TOUT; + + i2c->IICCON |= 0x80; + result = I2C_OK; + + switch (cmd_type) { + case I2C_WRITE: + if (addr && addr_len) { + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; + i = 0; + while ((i < addr_len) && (result == I2C_OK)) { + result = WaitForXfer (); + i2c->IICDS = addr[i]; + ReadWriteByte (); + i++; + } + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + result = WaitForXfer (); + i2c->IICDS = data[i]; + ReadWriteByte (); + i++; + } + } else { + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; + i = 0; + while ((i < data_len) && (result = I2C_OK)) { + result = WaitForXfer (); + i2c->IICDS = data[i]; + ReadWriteByte (); + i++; + } + } + + if (result == I2C_OK) + result = WaitForXfer (); + + /* send STOP */ + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; + ReadWriteByte (); + break; + + case I2C_READ: + if (addr && addr_len) { + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT |= I2C_START_STOP; + result = WaitForXfer (); + if (IsACK ()) { + i = 0; + while ((i < addr_len) && (result == I2C_OK)) { + i2c->IICDS = addr[i]; + ReadWriteByte (); + result = WaitForXfer (); + i++; + } + + i2c->IICDS = chip; + /* resend START */ + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | + I2C_START_STOP; + ReadWriteByte (); + result = WaitForXfer (); + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + /* disable ACK for final READ */ + if (i == data_len - 1) + i2c->IICCON &= ~0x80; + ReadWriteByte (); + result = WaitForXfer (); + data[i] = i2c->IICDS; + i++; + } + } else { + result = I2C_NACK; + } + + } else { + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT |= I2C_START_STOP; + result = WaitForXfer (); + + if (IsACK ()) { + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + /* disable ACK for final READ */ + if (i == data_len - 1) + i2c->IICCON &= ~0x80; + ReadWriteByte (); + result = WaitForXfer (); + data[i] = i2c->IICDS; + i++; + } + } else { + result = I2C_NACK; + } + } + + /* send STOP */ + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; + ReadWriteByte (); + break; + + default: + printf ("i2c_transfer: bad call\n"); + result = I2C_NOK; + break; + } + + return (result); +} + +int i2c_probe (uchar chip) +{ + uchar buf[1]; + + buf[0] = 0; + + /* + * What is needed is to send the chip address and verify that the + * address was ed (i.e. there was a chip at that address which + * drove the data line low). + */ + return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK); +} + +int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + int ret; + + if (alen > 4) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + if ((ret = + i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen, + buffer, len)) != 0) { + printf ("I2c read: failed %d\n", ret); + return 1; + } + return 0; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + + if (alen > 4) { + printf ("I2C write: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + return (i2c_transfer + (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, + len) != 0); +} +#endif /* CONFIG_HARD_I2C */ + +#endif /* CONFIG_DRIVER_S3C24X0_I2C */ diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c new file mode 100644 index 0000000..3ec9b54 --- /dev/null +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -0,0 +1,217 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) + +#include +#if defined(CONFIG_S3C2400) +#include +#elif defined(CONFIG_S3C2410) +#include +#endif + +int timer_load_val = 0; + +/* macro to read the 16 bit timer */ +static inline ulong READ_TIMER(void) +{ + S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); + + return (timers->TCNTO4 & 0xffff); +} + +static ulong timestamp; +static ulong lastdec; + +int interrupt_init (void) +{ + S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); + + /* use PWM Timer 4 because it has no output */ + /* prescaler for Timer 4 is 16 */ + timers->TCFG0 = 0x0f00; + if (timer_load_val == 0) + { + /* + * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 + * (default) and prescaler = 16. Should be 10390 + * @33.25MHz and 15625 @ 50 MHz + */ + timer_load_val = get_PCLK()/(2 * 16 * 100); + } + /* load value for 10 ms timeout */ + lastdec = timers->TCNTB4 = timer_load_val; + /* auto load, manual update of Timer 4 */ + timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; + /* auto load, start Timer 4 */ + timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; + timestamp = 0; + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo; + ulong start = get_timer(0); + + tmo = usec / 1000; + tmo *= (timer_load_val * 100); + tmo /= 1000; + + while ((ulong)(get_timer_masked () - start) < tmo) + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + timer_load_val - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= (timer_load_val * 100); + tmo /= 1000; + } else { + tmo = usec * (timer_load_val * 100); + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + +#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) + tbclk = timer_load_val * 100; +#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9) + tbclk = CFG_HZ; +#else +# error "tbclk not configured" +#endif + + return tbclk; +} + +/* + * reset the cpu by setting up the watchdog timer and let him time out + */ +void reset_cpu (ulong ignored) +{ + volatile S3C24X0_WATCHDOG * watchdog; + +#ifdef CONFIG_TRAB + extern void disable_vfd (void); + + disable_vfd(); +#endif + + watchdog = S3C24X0_GetBase_WATCHDOG(); + + /* Disable watchdog */ + watchdog->WTCON = 0x0000; + + /* Initialize watchdog timer count register */ + watchdog->WTCNT = 0x0001; + + /* Enable watchdog timer; assert reset at timer timeout */ + watchdog->WTCON = 0x0021; + + while(1); /* loop forever and wait for reset to happen */ + + /*NOTREACHED*/ +} + +#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/serial.c b/cpu/arm920t/s3c24x0/serial.c new file mode 100644 index 0000000..8327443 --- /dev/null +++ b/cpu/arm920t/s3c24x0/serial.c @@ -0,0 +1,182 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) + +#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) +#include +#elif defined(CONFIG_S3C2410) +#include +#endif + +#ifdef CONFIG_SERIAL1 +#define UART_NR S3C24X0_UART0 + +#elif defined(CONFIG_SERIAL2) +# if defined(CONFIG_TRAB) +# error "TRAB supports only CONFIG_SERIAL1" +# endif +#define UART_NR S3C24X0_UART1 + +#elif defined(CONFIG_SERIAL3) +# if defined(CONFIG_TRAB) +# #error "TRAB supports only CONFIG_SERIAL1" +# endif +#define UART_NR S3C24X0_UART2 + +#else +#error "Bad: you didn't configure serial ..." +#endif + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + int i; + unsigned int reg = 0; + + /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ + reg = get_PCLK() / (16 * gd->baudrate) - 1; + + /* FIFO enable, Tx/Rx FIFO clear */ + uart->UFCON = 0x07; + uart->UMCON = 0x0; + /* Normal,No parity,1 stop,8 bit */ + uart->ULCON = 0x3; + /* + * tx=level,rx=edge,disable timeout int.,enable rx error int., + * normal,interrupt or polling + */ + uart->UCON = 0x245; + uart->UBRDIV = reg; + +#ifdef CONFIG_HWFLOW + uart->UMCON = 0x1; /* RTS up */ +#endif + for (i = 0; i < 100; i++); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + serial_setbrg (); + + return (0); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + + /* wait for character to arrive */ + while (!(uart->UTRSTAT & 0x1)); + + return uart->URXH & 0xff; +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ + switch(on) { + case 0: + default: + break; /* return current */ + case 1: + hwflow = 1; /* turn on */ + break; + case -1: + hwflow = 0; /* turn off */ + break; + } + return hwflow; +} +#endif + +#ifdef CONFIG_MODEM_SUPPORT +static int be_quiet = 0; +void disable_putc(void) +{ + be_quiet = 1; +} + +void enable_putc(void) +{ + be_quiet = 0; +} +#endif + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); +#ifdef CONFIG_MODEM_SUPPORT + if (be_quiet) + return; +#endif + + /* wait for room in the tx FIFO */ + while (!(uart->UTRSTAT & 0x2)); + +#ifdef CONFIG_HWFLOW + /* Wait for CTS up */ + while(hwflow && !(uart->UMSTAT & 0x1)) + ; +#endif + + uart->UTXH = c; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc (void) +{ + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + + return uart->UTRSTAT & 0x1; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c new file mode 100644 index 0000000..e0dca62 --- /dev/null +++ b/cpu/arm920t/s3c24x0/speed.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This code should work for both the S3C2400 and the S3C2410 + * as they seem to have the same PLL and clock machinery inside. + * The different address mapping is handled by the s3c24xx.h files below. + */ + +#include +#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) + +#if defined(CONFIG_S3C2400) +#include +#elif defined(CONFIG_S3C2410) +#include +#endif + +#define MPLL 0 +#define UPLL 1 + +/* ------------------------------------------------------------------------- */ +/* NOTE: This describes the proper use of this file. + * + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. + * + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of + * the specified bus in HZ. + */ +/* ------------------------------------------------------------------------- */ + +static ulong get_PLLCLK(int pllreg) +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + ulong r, m, p, s; + + if (pllreg == MPLL) + r = clk_power->MPLLCON; + else if (pllreg == UPLL) + r = clk_power->UPLLCON; + else + hang(); + + m = ((r & 0xFF000) >> 12) + 8; + p = ((r & 0x003F0) >> 4) + 2; + s = r & 0x3; + + return((CONFIG_SYS_CLK_FREQ * m) / (p << s)); +} + +/* return FCLK frequency */ +ulong get_FCLK(void) +{ + return(get_PLLCLK(MPLL)); +} + +/* return HCLK frequency */ +ulong get_HCLK(void) +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + + return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK()); +} + +/* return PCLK frequency */ +ulong get_PCLK(void) +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + + return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK()); +} + +/* return UCLK frequency */ +ulong get_UCLK(void) +{ + return(get_PLLCLK(UPLL)); +} + +#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c new file mode 100644 index 0000000..b4cc744 --- /dev/null +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -0,0 +1,1688 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTES + * 1 - you MUST define LITTLEENDIAN in the configuration file for the + * board or this driver will NOT work! + * 2 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + */ + +#include +/* #include no PCI on the S3C24X0 */ + +#ifdef CONFIG_USB_OHCI + +#if defined(CONFIG_S3C2400) +#include +#elif defined(CONFIG_S3C2410) +#include +#endif + +#include +#include +#include "usb_ohci.h" + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ + + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +#define readl(a) (*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) + +#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +#undef DEBUG +#ifdef DEBUG +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#undef SHOW_INFO +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) swap_16(x) +#define m32_swap(x) swap_32(x) + +/* global ohci_t */ +static ohci_t gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +urb_priv_t urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; +/* flag guarding URB transation */ +int urb_finished = 0; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + +static u32 roothub_a (struct ohci *hc) + { return read_roothub (hc, a, 0xfc0fe000); } +static inline u32 roothub_b (struct ohci *hc) + { return readl (&hc->regs->roothub.b); } +static inline u32 roothub_status (struct ohci *hc) + { return readl (&hc->regs->roothub.status); } +static u32 roothub_portstatus (struct ohci *hc, int i) + { return read_roothub (hc, portstatus [i], 0xffe0fce0); } + + +/* forward declaration */ +static int hc_interrupt (void); +static void +td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv (urb_priv_t * urb) +{ + int i; + int last; + struct td * td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +static int sohci_get_current_frame_number (struct usb_device * dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, char * str, int small) +{ + urb_priv_t * purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number (dev), + usb_pipedevice (pipe), + usb_pipeendpoint (pipe), + usb_pipeout (pipe)? 'O': 'I', + usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): + (usb_pipecontrol (pipe)? "CTRL": "BULK"), + purb->actual_length, + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol (pipe)) { + printf (__FILE__ ": cmd(8):"); + for (i = 0; i < 8 ; i++) + printf (" %02x", ((__u8 *) setup) [i]); + printf ("\n"); + } + if (transfer_len > 0 && buffer) { + printf (__FILE__ ": data(%d/%d):", + purb->actual_length, + transfer_len); + len = usb_pipeout (pipe)? + transfer_len: purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf (" %02x", ((__u8 *) buffer) [i]); + printf ("%s\n", i < len? "...": ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ +void ep_print_int_eds (ohci_t *ohci, char * str) { + int i, j; + __u32 * ed_p; + for (i= 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table [i]); + if (*ed_p == 0) + continue; + printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + ed_t *ed = (ed_t *)m32_swap(ed_p); + printf (" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf ("\n"); + } +} + +static void ohci_dump_intr_mask (char *label, __u32 mask) +{ + dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds (char *label, __u32 value) +{ + ed_t *edp = (ed_t *)value; + + if (value) { + dbg ("%s %08x", label, value); + dbg ("%08x", edp->hwINFO); + dbg ("%08x", edp->hwTailP); + dbg ("%08x", edp->hwHeadP); + dbg ("%08x", edp->hwNextED); + } +} + +static char * hcfs2string (int state) +{ + switch (state) { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status (ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl (®s->revision) & 0xff; + if (temp != 0x10) + dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl (®s->control); + dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string (temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + + temp = readl (®s->cmdstatus); + dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + + ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); + ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); + + maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); + + maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); + maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); + + maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); + maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); + + maybe_print_eds ("donehead", readl (®s->donehead)); +} + +static void ohci_dump_roothub (ohci_t *controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + + if (verbose) { + dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b (controller); + dbg ("roothub.b: %08x PPCM=%04x DR=%04x", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status (controller); + dbg ("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump (ohci_t *controller, int verbose) +{ + dbg ("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status (controller); + if (verbose) + ep_print_int_eds (controller, "hcca"); + dbg ("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub (controller, 1); +} + + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + ohci_t *ohci; + ed_t * ed; + urb_priv_t *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* if we have an unfinished URB from previous transaction let's + * fail and scream as quickly as possible so as not to corrupt + * further communication */ + if (!urb_finished) { + err("sohci_submit_job: URB NOT FINISHED"); + return -1; + } + /* we're about to begin a new transaction here so mark the URB unfinished */ + urb_finished = 0; + + /* every endpoint has a ed, locate and fill it */ + if (!(ed = ep_add_ed (dev, pipe))) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype (pipe)) { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0)? 2: + (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc (dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv (purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv (purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link (ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number (struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + + return m16_swap (ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel (ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel (ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink (ohci_t *ohci, ed_t *ed) +{ + ed->hwINFO |= m32_swap (OHCI_ED_SKIP); + + switch (ed->type) { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_controltail == ed) { + ohci->ed_controltail = ed->ed_prev; + } else { + ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_bulktail == ed) { + ohci->ed_bulktail = ed->ed_prev; + } else { + ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + } + ed->state = ED_UNLINK; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, + * but the USB stack is a little bit stateless so we do it at every transaction + * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK + * in all other cases the state is left unchanged + * the ed info fields are setted anyway even though most of them should not change */ + +static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | + (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc (usb_dev); + ed->hwTailP = m32_swap (td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype (pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = m32_swap (usb_pipedevice (pipe) + | usb_pipeendpoint (pipe) << 7 + | (usb_pipeisoc (pipe)? 0x8000: 0) + | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) + | usb_pipeslow (pipe) << 13 + | usb_maxpacket (usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill (ohci_t *ohci, unsigned int info, + void *data, int len, + struct usb_device *dev, int index, urb_priv_t *urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td [index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32)data; +#ifdef OHCI_FILL_TRACE + if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); + printf("\n"); + } +#endif + if (!len) + data = 0; + + td->hwINFO = m32_swap (info); + td->hwCBP = m32_swap (data); + if (data) + td->hwBE = m32_swap (data + len - 1); + else + td->hwBE = 0; + td->hwNextTD = m32_swap (td_pt); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ + +static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ + if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = 0; + + switch (usb_pipetype (pipe)) { + case PIPE_BULK: + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while(data_len > 4096) { + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill (ohci, info, setup, 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout (pipe)? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill (ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill (ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(td_t * td) +{ + __u32 tdINFO, tdBE, tdCBP; + urb_priv_t *lurb_priv = &urb_priv; + + tdINFO = m32_swap (td->hwINFO); + tdBE = m32_swap (td->hwBE); + tdCBP = m32_swap (td->hwCBP); + + + if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && + ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { + if (tdBE != 0) { + if (td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ + +static td_t * dl_reverse_done_list (ohci_t *ohci) +{ + __u32 td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + urb_priv_t *lurb_priv = NULL; + + td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; + ohci->hcca->done_head = 0; + + while (td_list_hc) { + td_list = (td_t *)td_list_hc; + + if (TD_CC_GET (m32_swap (td_list->hwINFO))) { + lurb_priv = &urb_priv; + dbg(" USB-error/status: %x : %p", + TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); + if (td_list->ed->hwHeadP & m32_swap (0x1)) { + if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { + td_list->ed->hwHeadP = + (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | + (td_list->ed->hwHeadP & m32_swap (0x2)); + lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; + } else + td_list->ed->hwHeadP &= m32_swap (0xfffffff2); + } + } + + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; + } + + return td_list; +} + +/*-------------------------------------------------------------------------*/ + +/* td done list */ +static int dl_done_list (ohci_t *ohci, td_t *td_list) +{ + td_t *td_list_next = NULL; + ed_t *ed; + int cc = 0; + int stat = 0; + /* urb_t *urb; */ + urb_priv_t *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + + while (td_list) { + td_list_next = td_list->next_dl_td; + + lurb_priv = &urb_priv; + tdINFO = m32_swap (td_list->hwINFO); + + ed = td_list->ed; + + dl_transfer_length(td_list); + + /* error code of transfer */ + cc = TD_CC_GET (tdINFO); + if (cc != 0) { + dbg("ConditionCode %#x", cc); + stat = cc_to_error[cc]; + } + + /* see if this done list makes for all TD's of current URB, + * and mark the URB finished if so */ + if (++(lurb_priv->td_cnt) == lurb_priv->length) { + if ((ed->state & (ED_OPER | ED_UNLINK))) + urb_finished = 1; + else + dbg("dl_done_list: strange.., ED state %x, ed->state\n"); + } else + dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt, + lurb_priv->length); + + if (ed->state != ED_NEW) { + edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; + edTailP = m32_swap (ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink (ohci, ed); + } + + td_list = td_list_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + __u32 temp, ndp, i; + int res; + + res = -1; + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && + ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + void * data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u32 datab[4]; + __u8 *data_buf = (__u8 *)datab; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + +#ifdef DEBUG +urb_priv.actual_length = 0; +pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = m16_swap (cmd->value); + wIndex = m16_swap (cmd->index); + wLength = m16_swap (cmd->length); + + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(__u16 *) data_buf = m16_swap (1); OK (2); + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_CLASS: + *(__u32 *) data_buf = m32_swap ( + RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK (4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + OK(0); + case (RH_C_HUB_OVER_CURRENT): + WR_RH_STAT(RH_HS_OCIC); OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_POCI); OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); + case (RH_C_PORT_CONNECTION): + WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); + case (RH_C_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_PESC); OK (0); + case (RH_C_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); + case (RH_C_PORT_OVER_CURRENT): + WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); + case (RH_C_PORT_RESET): + WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); + case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PRS); + OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PES ); + OK (0); + } + break; + + case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; OK(len); + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; OK(len); + case (0x03): /* string descriptors */ + if(wValue==0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if(wValue==0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a (&gohci); + + data_buf [0] = 9; /* min length; */ + data_buf [1] = 0x29; + data_buf [2] = temp & RH_A_NDP; + data_buf [3] = 0; + if (temp & RH_A_PSM) /* per-port power switching? */ + data_buf [3] |= 0x1; + if (temp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf [3] |= 0x10; + else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + data_buf [3] |= 0x8; + + /* corresponds to data_buf[4-7] */ + datab [1] = 0; + data_buf [5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b (&gohci); + data_buf [7] = temp & RH_B_DR; + if (data_buf [2] < 7) { + data_buf [8] = 0xff; + } else { + data_buf [0] += 2; + data_buf [8] = (temp & RH_B_DR) >> 8; + data_buf [10] = data_buf [9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf [0], wLength)); + OK (len); + } + + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); + + case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); + + default: + dbg ("unsupported root hub command"); + stat = USB_ST_STALLED; + } + +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#else + wait_ms(1); +#endif + + len = min_t(int, len, leni); + if (data != data_buf) + memcpy (data, data_buf, len); + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG + if (transfer_len) + urb_priv.actual_length = transfer_len; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); +#else + wait_ms(1); +#endif + + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if (!maxsize) { + err("submit_common_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { + err("sohci_submit_job failed"); + return -1; + } + + wait_ms(10); + /* ohci_dump_status(&gohci); */ + + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if (usb_pipetype (pipe) == PIPE_BULK) + timeout = BULK_TO; + else + timeout = 100; + + /* wait for it to complete */ + for (;;) { + /* check whether the controller is done */ + stat = hc_interrupt(); + + if (stat < 0) { + stat = USB_ST_CRC_ERR; + break; + } + + /* NOTE: since we are not interrupt driven in U-Boot and always + * handle only one URB at a time, we cannot assume the + * transaction finished on the first successful return from + * hc_interrupt().. unless the flag for current URB is set, + * meaning that all TD's to/from device got actually + * transferred and processed. If the current URB is not + * finished we need to re-iterate this loop so as + * hc_interrupt() gets called again as there needs to be some + * more TD's to process still */ + if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { + /* 0xff is returned for an SF-interrupt */ + break; + } + + if (--timeout) { + wait_ms(1); + if (!urb_finished) + dbg("\%"); + + } else { + err("CTL:TIMEOUT "); + dbg("submit_common_msg: TO status %x\n", stat); + stat = USB_ST_CRC_ERR; + urb_finished = 1; + break; + } + } + +#if 0 + /* we got an Root Hub Status Change interrupt */ + if (got_rhsc) { +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + got_rhsc = 0; + /* abuse timeout */ + timeout = rh_check_port_status(&gohci); + if (timeout >= 0) { +#if 0 /* this does nothing useful, but leave it here in case that changes */ + /* the called routine adds 1 to the passed value */ + usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); +#endif + /* + * XXX + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } +#endif + + dev->status = stat; + dev->act_len = transfer_len; + +#ifdef DEBUG + pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + + /* free TDs in urb_priv */ + urb_free_priv (&urb_priv); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + + info("submit_control_msg"); +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if (!maxsize) { + err("submit_control_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset (ohci_t *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ + writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ + info("USB HC TakeOver from SMM"); + while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { + wait_ms (10); + if (--smm_timeout == 0) { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", + ohci->slot_name, + readl (&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + writel (0, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel (OHCI_HCR, &ohci->regs->cmdstatus); + while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { + if (--timeout == 0) { + err("USB HC reset timed out!"); + return -1; + } + udelay (1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start (ohci_t * ohci) +{ + __u32 mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + + writel (0, &ohci->regs->ed_controlhead); + writel (0, &ohci->regs->ed_bulkhead); + + writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + + fminterval = 0x2edf; + writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel (fminterval, &ohci->regs->fminterval); + writel (0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel (mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel (mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel (mask, &ohci->regs->intrenable); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, + &ohci->regs->roothub.a); + writel (RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay ((roothub_a (ohci) >> 23) & 0x1fe); + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static int +hc_interrupt (void) +{ + ohci_t *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + if ((ohci->hcca->done_head != 0) && + !(m32_swap (ohci->hcca->done_head) & 0x01)) { + + ints = OHCI_INTR_WDH; + + } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { + ohci->disabled++; + err ("%s device removed!", ohci->slot_name); + return -1; + + } else if ((ints &= readl (®s->intrenable)) == 0) { + dbg("hc_interrupt: returning..\n"); + return 0xff; + } + + /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ + + if (ints & OHCI_INTR_RHSC) { + got_rhsc = 1; + stat = 0xff; + } + + if (ints & OHCI_INTR_UE) { + ohci->disabled++; + err ("OHCI Unrecoverable Error, controller usb-%s disabled", + ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ + +#ifdef DEBUG + ohci_dump (ohci, 1); +#else + wait_ms(1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset (ohci); + return -1; + } + + if (ints & OHCI_INTR_WDH) { + wait_ms(1); + + writel (OHCI_INTR_WDH, ®s->intrdisable); + stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); + writel (OHCI_INTR_WDH, ®s->intrenable); + } + + if (ints & OHCI_INTR_SO) { + dbg("USB Schedule overrun\n"); + writel (OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) { + unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; + wait_ms(1); + writel (OHCI_INTR_SF, ®s->intrdisable); + if (ohci->ed_rm_list[frame] != NULL) + writel (OHCI_INTR_SF, ®s->intrenable); + stat = 0xff; + } + + writel (ints, ®s->intrstatus); + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci (ohci_t *ohci) +{ + dbg ("USB HC release ohci usb-%s", ohci->slot_name); + + if (!ohci->disabled) + hc_reset (ohci); +} + +/*-------------------------------------------------------------------------*/ + +/* + * low level initalisation routine, called from usb.c + */ +static char ohci_inited = 0; + +int usb_lowlevel_init(void) +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* + * Set the 48 MHz UPLL clocking. Values are taken from + * "PLL value selection guide", 6-23, s3c2400_UM.pdf. + */ + clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); + gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ + + /* + * Enable USB host clock. + */ + clk_power->CLKCON |= (1 << 4); + + memset (&gohci, 0, sizeof (ohci_t)); + memset (&urb_priv, 0, sizeof (urb_priv_t)); + + /* align the storage */ + if ((__u32)&ghcca[0] & 0xff) { + err("HCCA not aligned!!"); + return -1; + } + phcca = &ghcca[0]; + info("aligned ghcca %p", phcca); + memset(&ohci_dev, 0, sizeof(struct ohci_device)); + if ((__u32)&ohci_dev.ed[0] & 0x7) { + err("EDs not aligned!!"); + return -1; + } + memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); + if ((__u32)gtd & 0x7) { + err("TDs not aligned!!"); + return -1; + } + ptd = gtd; + gohci.hcca = phcca; + memset (phcca, 0, sizeof (struct ohci_hcca)); + + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE; + + gohci.flags = 0; + gohci.slot_name = "s3c2400"; + + if (hc_reset (&gohci) < 0) { + hc_release_ohci (&gohci); + /* Initialization failed */ + clk_power->CLKCON &= ~(1 << 4); + return -1; + } + + /* FIXME this is a second HC reset; why?? */ + writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); + wait_ms (10); + + if (hc_start (&gohci) < 0) { + err ("can't start usb-%s", gohci.slot_name); + hc_release_ohci (&gohci); + /* Initialization failed */ + clk_power->CLKCON &= ~(1 << 4); + return -1; + } + +#ifdef DEBUG + ohci_dump (&gohci, 1); +#else + wait_ms(1); +#endif + ohci_inited = 1; + urb_finished = 1; + + return 0; +} + +int usb_lowlevel_stop(void) +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if (!ohci_inited) + return 0; + /* TODO release any interrupts, etc. */ + /* call hc_release_ohci() here ? */ + hc_reset (&gohci); + /* may not want to do this */ + clk_power->CLKCON &= ~(1 << 4); + return 0; +} + +#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/arm920t/s3c24x0/usb_ohci.h b/cpu/arm920t/s3c24x0/usb_ohci.h new file mode 100644 index 0000000..5e9a0fd --- /dev/null +++ b/cpu/arm920t/s3c24x0/usb_ohci.h @@ -0,0 +1,417 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +/* ED States */ +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute((aligned(16))); +typedef struct ed ed_t; + + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute((aligned(256))); + + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute((aligned(32))); + + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct +{ + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + + +typedef struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma;*/ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +td_t gtd[NUM_TD+1]; +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td * +td_alloc (struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) + { + if (ptd[i].usb_dev == NULL) + { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void +ed_free (struct ed *ed) +{ + ed->usb_dev = NULL; +} diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S new file mode 100644 index 0000000..4603cf5 --- /dev/null +++ b/cpu/arm920t/start.S @@ -0,0 +1,433 @@ +/* + * armboot - Startup Code for ARM920 CPU-core + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + +/* turn off the watchdog */ +#if defined(CONFIG_S3C2400) +# define pWTCON 0x15300000 +# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ +# define CLKDIVN 0x14800014 /* clock divisor register */ +#elif defined(CONFIG_S3C2410) +# define pWTCON 0x53000000 +# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +# define INTSUBMSK 0x4A00001C +# define CLKDIVN 0x4C000014 /* clock divisor register */ +#endif + +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) + ldr r0, =pWTCON + mov r1, #0x0 + str r1, [r0] + + /* + * mask all IRQs by setting all bits in the INTMR - default + */ + mov r1, #0xffffffff + ldr r0, =INTMSK + str r1, [r0] +# if defined(CONFIG_S3C2410) + ldr r1, =0x3ff + ldr r0, =INTSUBMSK + str r1, [r0] +# endif + + /* FCLK:HCLK:PCLK = 1:2:4 */ + /* default FCLK is 120 MHz ! */ + ldr r0, =CLKDIVN + mov r1, #3 + str r1, [r0] +#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + +#if 0 + /* try doing this stuff after the relocation */ + ldr r0, =pWTCON + mov r1, #0x0 + str r1, [r0] + + /* + * mask all IRQs by setting all bits in the INTMR - default + */ + mov r1, #0xffffffff + ldr r0, =INTMR + str r1, [r0] + + /* FCLK:HCLK:PCLK = 1:2:4 */ + /* default FCLK is 120 MHz ! */ + ldr r0, =CLKDIVN + mov r1, #3 + str r1, [r0] + /* END stuff after relocation */ +#endif + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + + +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + mov pc, lr + + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get pc, cpsr + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif diff --git a/cpu/arm925t/Makefile b/cpu/arm925t/Makefile new file mode 100644 index 0000000..a1db818 --- /dev/null +++ b/cpu/arm925t/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = interrupts.o cpu.o omap925.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm925t/config.mk b/cpu/arm925t/config.mk new file mode 100644 index 0000000..8db4adb --- /dev/null +++ b/cpu/arm925t/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c new file mode 100644 index 0000000..c1c6b03 --- /dev/null +++ b/cpu/arm925t/cpu.c @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* Many OMAP regs need at least 2 nops */ + for (i = 0; i < 100; i++); +} + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ +#define C1_WB (1<<3) /* merging write buffer on/off */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c new file mode 100644 index 0000000..57bb4ea --- /dev/null +++ b/cpu/arm925t/interrupts.c @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2003 + * Texas Instruments, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +#define TIMER_LOAD_VAL 0xffffffff + +/* macro to read the 32 bit timer */ +#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +static ulong timestamp; +static ulong lastdec; + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init (void) +{ + int32_t val; + + /* Start the decrementer ticking down from 0xffffffff */ + *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; + val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT); + *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val; + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND preserve advance timestamp value */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + }else{ /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + + while (get_timer_masked () < tmo) /* loop till event */ + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ +#ifdef CONFIG_INNOVATOROMAP1510 + #define LOOPS_PER_MSEC 60 /* tuned on omap1510 */ + volatile int i, time_remaining = LOOPS_PER_MSEC*usec; + for (i=time_remaining; i>0; i--) { } +#else + + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +#endif +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return tbclk; +} diff --git a/cpu/arm925t/omap925.c b/cpu/arm925t/omap925.c new file mode 100644 index 0000000..ae62656 --- /dev/null +++ b/cpu/arm925t/omap925.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +ushort gpioreserved; + +void gpioreserve(ushort mask) +{ + gpioreserved |= mask; +} + +void gpiosetdir(ushort mask, ushort in) +{ + *(ushort *)GPIO_DIR_CONTROL_REG = (*(ushort *)GPIO_DIR_CONTROL_REG & ~mask) | (in & mask); +} + + +void gpiosetout(ushort mask, ushort out) +{ + ushort *r_ptr, r_val; + + r_ptr = (ushort *)GPIO_DATA_OUTPUT_REG; /* set pointer */ + r_val = *r_ptr & ~mask; /* get previous val, clear bits we want to change */ + r_val |= (out & mask); /* set specified bits in value + plus origional ones */ + *r_ptr = r_val; /* write it out */ +/* + * gcc screwed this one up :(. + * + * *(ushort *)GPIO_DATA_OUTPUT_REG = (*(ushort *)GPIO_DATA_OUTPUT_REG & ~mask) | (out & mask); + */ + +} + +void gpioinit(void) +{ +} + + +#define MIF_CONFIG_REG 0xFFFECC0C +#define FLASH_GLOBAL_CTRL_NWP 1 + +void archflashwp (void *archdata, int wp) +{ + ulong *fgc = (ulong *) MIF_CONFIG_REG; + + if (wp == 1) + *fgc &= ~FLASH_GLOBAL_CTRL_NWP; + else + *fgc |= FLASH_GLOBAL_CTRL_NWP; +} diff --git a/cpu/arm925t/start.S b/cpu/arm925t/start.S new file mode 100644 index 0000000..acd7742 --- /dev/null +++ b/cpu/arm925t/start.S @@ -0,0 +1,429 @@ +/* + * armboot - Startup Code for ARM925 CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1510 from ARM920 code ------ + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#if defined(CONFIG_OMAP1510) +#include <./configs/omap1510.h> +#endif + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * Set up 925T mode + */ + mov r1, #0x81 /* Set ARM925T configuration. */ + mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */ + + /* + * turn off the watchdog, unlock/diable sequence + */ + mov r1, #0xF5 + ldr r0, =WDTIM_MODE + strh r1, [r0] + mov r1, #0xA0 + strh r1, [r0] + + /* + * mask all IRQs by setting all bits in the INTMR - default + */ + mov r1, #0xffffffff + ldr r0, =REG_IHL1_MIR + str r1, [r0] + ldr r0, =REG_IHL2_MIR + str r1, [r0] + + /* + * wait for dpll to lock + */ + ldr r0, =CK_DPLL1 + mov r1, #0x10 + strh r1, [r0] +poll1: + ldrh r1, [r0] + ands r1, r1, #0x01 + beq poll1 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + + +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + mov ip, lr /* perserve link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + + .align 5 +.globl reset_cpu +reset_cpu: + ldr r1, rstctl1 /* get clkm1 reset ctl */ + mov r3, #0x3 /* dsp_en + arm_rst = global reset */ + strh r3, [r1] /* force reset */ + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl1: + .word 0xfffece10 diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile new file mode 100644 index 0000000..203278e --- /dev/null +++ b/cpu/arm926ejs/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = interrupts.o cpu.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk new file mode 100644 index 0000000..8db4adb --- /dev/null +++ b/cpu/arm926ejs/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c new file mode 100644 index 0000000..f57c5a5 --- /dev/null +++ b/cpu/arm926ejs/cpu.c @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM926EJ-S Technical Reference Manual */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ + +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c new file mode 100644 index 0000000..0457bff --- /dev/null +++ b/cpu/arm926ejs/interrupts.c @@ -0,0 +1,333 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define TIMER_LOAD_VAL 0xffffffff + +/* macro to read the 32 bit timer */ +#ifdef CONFIG_OMAP +#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) +#endif +#ifdef CONFIG_VERSATILE +#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4)) +#endif + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +#ifdef CONFIG_INTEGRATOR + + /* Timer functionality supplied by Integrator board (AP or CP) */ + +#else + +static ulong timestamp; +static ulong lastdec; + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init (void) +{ +#ifdef CONFIG_OMAP + int32_t val; + + /* Start the decrementer ticking down from 0xffffffff */ + *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; + val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT); + *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val; +#endif /* CONFIG_OMAP */ + +#ifdef CONFIG_VERSATILE + *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */ + *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */ + *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C; +#endif /* CONFIG_VERSATILE */ + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + }else{ /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return tbclk; +} + +#endif /* CONFIG_INTEGRATOR */ diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S new file mode 100644 index 0000000..fc6b20b --- /dev/null +++ b/cpu/arm926ejs/start.S @@ -0,0 +1,416 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#if defined(CONFIG_OMAP1610) +#include <./configs/omap1510.h> +#elif defined(CONFIG_OMAP730) +#include <./configs/omap730.h> +#endif + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: + .word undefined_instruction +_software_interrupt: + .word software_interrupt +_prefetch_abort: + .word prefetch_abort +_data_abort: + .word data_abort +_not_used: + .word not_used +_irq: + .word irq +_fiq: + .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + + ldr pc, _start_armboot + +_start_armboot: + .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + + +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + mov ip, lr /* perserve link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + @ carve out a frame on current user stack + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + @ get values for "aborted" pc and cpsr (into parm regs) + ldmia r2, {r2 - r3} + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + +# ifdef CONFIG_INTEGRATOR + + /* Satisfied by Integrator routine (AP or CP) */ + +#else + + .align 5 +.globl reset_cpu +reset_cpu: + ldr r1, rstctl1 /* get clkm1 reset ctl */ + mov r3, #0x0 + strh r3, [r1] /* clear it */ + mov r3, #0x8 + strh r3, [r1] /* force dsp+arm reset */ +_loop_forever: + b _loop_forever + +rstctl1: + .word 0xfffece10 + +#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/cpu/arm946es/Makefile b/cpu/arm946es/Makefile new file mode 100644 index 0000000..203278e --- /dev/null +++ b/cpu/arm946es/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = interrupts.o cpu.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm946es/config.mk b/cpu/arm946es/config.mk new file mode 100644 index 0000000..81ca288 --- /dev/null +++ b/cpu/arm946es/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c new file mode 100644 index 0000000..ba0a4e4 --- /dev/null +++ b/cpu/arm946es/cpu.c @@ -0,0 +1,163 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM946E-S Technical Reference Manual */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ + +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* ARM926E-S needs the protection unit enabled for the icache to have + * been enabled - left for possible later use + * should turn off the protection unit as well.... + */ + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern void reset_cpu (ulong addr); + + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} +/* ARM926E-S needs the protection unit enabled for this to have any effect + - left for possible later use */ +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} diff --git a/cpu/arm946es/interrupts.c b/cpu/arm946es/interrupts.c new file mode 100644 index 0000000..5728c3a --- /dev/null +++ b/cpu/arm946es/interrupts.c @@ -0,0 +1,292 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define TIMER_LOAD_VAL 0xffffffff +extern void reset_cpu(ulong addr); + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +#ifdef CONFIG_INTEGRATOR + /* Timer functionality supplied by Integrator board (AP or CP) */ +#else + +static ulong timestamp; +static ulong lastdec; + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init (void) +{ + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_raw (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +ulong get_timer_masked (void) +{ + return get_timer_raw() / TIMER_LOAD_VAL; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + ulong tmo; + + if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + }else{ /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ_CLOCK; + tmo /= (1000*1000); + } + + reset_timer_masked (); /* set "advancing" timestamp to 0, set lastdec vaule */ + + while (get_timer_raw () < tmo) /* wait for time stamp to overtake tick number.*/ + /*NOP*/; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return tbclk; +} + +#endif /* CONFIG_INTEGRATOR */ diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S new file mode 100644 index 0000000..e8c908b --- /dev/null +++ b/cpu/arm946es/start.S @@ -0,0 +1,409 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: + .word undefined_instruction +_software_interrupt: + .word software_interrupt +_prefetch_abort: + .word prefetch_abort +_data_abort: + .word data_abort +_not_used: + .word not_used +_irq: + .word irq +_fiq: + .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifdef CONFIG_INIT_CRITICAL + bl cpu_init_crit +#endif + +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + ldr pc, _start_armboot + +_start_armboot: + .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + + +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */ + mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + mov ip, lr /* perserve link reg across call */ + bl lowlevel_init /* go setup memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + @ carve out a frame on current user stack + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + @ get values for "aborted" pc and cpsr (into parm regs) + ldmia r2, {r2 - r3} + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + +# ifdef CONFIG_INTEGRATOR + + /* Satisfied by general board level routine */ + +#else + + .align 5 +.globl reset_cpu +reset_cpu: + + ldr r1, rstctl1 /* get clkm1 reset ctl */ + mov r3, #0x0 + strh r3, [r1] /* clear it */ + mov r3, #0x8 + strh r3, [r1] /* force dsp+arm reset */ +_loop_forever: + b _loop_forever + +rstctl1: + .word 0xfffece10 + +#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/cpu/arm_intcm/Makefile b/cpu/arm_intcm/Makefile new file mode 100644 index 0000000..203278e --- /dev/null +++ b/cpu/arm_intcm/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = interrupts.o cpu.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm_intcm/config.mk b/cpu/arm_intcm/config.mk new file mode 100644 index 0000000..81ca288 --- /dev/null +++ b/cpu/arm_intcm/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c new file mode 100644 index 0000000..d03b09d --- /dev/null +++ b/cpu/arm_intcm/cpu.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code for an unknown cpu + * - hence fairly empty...... + */ + +#include +#include + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + disable_interrupts (); + + /* Since the CM has unknown processor we do not support + * cache operations + */ + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern void reset_cpu (ulong addr); + + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +/* May not be cahed processor on the CM - do nothing */ +void icache_enable (void) +{ +} + +void icache_disable (void) +{ +} + +/* return "disabled" */ +int icache_status (void) +{ + return 0; +} diff --git a/cpu/arm_intcm/interrupts.c b/cpu/arm_intcm/interrupts.c new file mode 100644 index 0000000..1763176 --- /dev/null +++ b/cpu/arm_intcm/interrupts.c @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifndef CONFIG_INTEGRATOR +/* Only to be used for integrator/AP or /CP */ +/* Allows U-Boot to be used with any ARM supplied core module (CM), + * provided the ARM boot monitor, or similar software, + * runs first to set up the platform e.g. map writeable memory to 0x00000000 + * - see Integrator User Guides + * Versatile has a supported cpu - arm926ejs + * Some integrator CMs cpus are supported + * CM926EJ-S, CM946E-S + * For platforms with supported cpus U-Boot can be used as the sole boot + * monitor/loader - it will configure the platform itself + * Also U-Boot may be faster/smaller in those cases since specific + * qualities of the cpu and/or CM can be used e.g i and/or d caches etc. + */ +#endif +extern void reset_cpu(ulong addr); + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +/* The timer functionality is supplied by the Integrator board */ +/* - see board/integrator<>.c */ diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S new file mode 100644 index 0000000..75fe917 --- /dev/null +++ b/cpu/arm_intcm/start.S @@ -0,0 +1,370 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +/* + ************************************************************************* + * + * Jump vector table + * + ************************************************************************* + */ + +.globl _start +_start: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: + .word undefined_instruction +_software_interrupt: + .word software_interrupt +_prefetch_abort: + .word prefetch_abort +_data_abort: + .word data_abort +_not_used: + .word not_used +_irq: + .word irq +_fiq: + .word fiq + + .balignl 16,0xdeadbeef + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE /* address of _start in the linked image */ + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/* + * the actual reset code + */ +.globl reset +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifdef CONFIG_INIT_CRITICAL + bl cpu_init_crit +#endif + +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* pc relative address of label */ + ldr r1, _TEXT_BASE /* linked image address of label */ + cmp r0, r1 /* test if we run from flash or RAM */ + beq stack_setup /* ifeq we are in the RAM copy */ + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + + ldr pc, _start_armboot + +_start_armboot: + .word start_armboot + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + +cpu_init_crit: + /* arm_int_generic assumes the ARM boot monitor, or user software, + * has initialized the platform + */ + mov pc, lr /* back to my caller */ +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + @ carve out a frame on current user stack + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + @ get values for "aborted" pc and cpsr (into parm regs) + ldmia r2, {r2 - r3} + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +.globl undefined_instruction +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +.globl software_interrupt +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +.globl prefetch_abort +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +.globl data_abort +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +.globl not_used +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + .align 5 +.globl irq +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +.globl fiq +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +.globl irq +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +.globl fiq +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile new file mode 100644 index 0000000..c44412a --- /dev/null +++ b/cpu/i386/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o start16.o reset.o +COBJS = serial.o interrupts.o cpu.o timer.o sc520.o +AOBJS = sc520_asm.o + +all: .depend $(START) $(LIB) + +$(LIB): $(COBJS) $(AOBJS) + $(AR) crv $@ $(COBJS) $(AOBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/i386/config.mk b/cpu/i386/config.mk new file mode 100644 index 0000000..16a160d --- /dev/null +++ b/cpu/i386/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += + +PLATFORM_CPPFLAGS += -march=i386 -Werror diff --git a/cpu/i386/cpu.c b/cpu/i386/cpu.c new file mode 100644 index 0000000..5fd37c7 --- /dev/null +++ b/cpu/i386/cpu.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include + +int cpu_init(void) +{ + /* initialize FPU, reset EM, set MP and NE */ + asm ("fninit\n" \ + "movl %cr0, %eax\n" \ + "andl $~0x4, %eax\n" \ + "orl $0x22, %eax\n" \ + "movl %eax, %cr0\n" ); + + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf ("resetting ...\n"); + udelay(50000); /* wait 50 ms */ + disable_interrupts(); + reset_cpu(0); + + /*NOTREACHED*/ + return 0; +} + +void flush_cache (unsigned long dummy1, unsigned long dummy2) +{ + asm("wbinvd\n"); + return; +} diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c new file mode 100644 index 0000000..f340119 --- /dev/null +++ b/cpu/i386/interrupts.c @@ -0,0 +1,525 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + + +struct idt_entry { + u16 base_low; + u16 selector; + u8 res; + u8 access; + u16 base_high; +} __attribute__ ((packed)); + + +struct idt_entry idt[256]; + + +#define MAX_IRQ 16 + +typedef struct irq_handler { + struct irq_handler *next; + interrupt_handler_t* isr_func; + void *isr_data; +} irq_handler_t; + +#define IRQ_DISABLED 1 + +typedef struct { + irq_handler_t *handler; + unsigned long status; +} irq_desc_t; + +static irq_desc_t irq_table[MAX_IRQ]; + +asm ("irq_return:\n" + " addl $4, %esp\n" + " popa\n" + " iret\n"); + +asm ("exp_return:\n" + " addl $12, %esp\n" + " pop %esp\n" + " popa\n" + " iret\n"); + +char exception_stack[4096]; + +#define DECLARE_INTERRUPT(x) \ + asm(".globl irq_"#x"\n" \ + "irq_"#x":\n" \ + "pusha \n" \ + "pushl $"#x"\n" \ + "pushl $irq_return\n" \ + "jmp do_irq\n"); \ + void __attribute__ ((regparm(0))) irq_##x(void) + +#define DECLARE_EXCEPTION(x, f) \ + asm(".globl exp_"#x"\n" \ + "exp_"#x":\n" \ + "pusha \n" \ + "movl %esp, %ebx\n" \ + "movl $exception_stack, %eax\n" \ + "movl %eax, %esp \n" \ + "pushl %ebx\n" \ + "movl 32(%esp), %ebx\n" \ + "xorl %edx, %edx\n" \ + "movw 36(%esp), %dx\n" \ + "pushl %edx\n" \ + "pushl %ebx\n" \ + "pushl $"#x"\n" \ + "pushl $exp_return\n" \ + "jmp "#f"\n"); \ + void __attribute__ ((regparm(0))) exp_##x(void) + +DECLARE_EXCEPTION(0, divide_exception_entry); /* Divide exception */ +DECLARE_EXCEPTION(1, debug_exception_entry); /* Debug exception */ +DECLARE_EXCEPTION(2, nmi_entry); /* NMI */ +DECLARE_EXCEPTION(3, unknown_exception_entry); /* Breakpoint/Coprocessor Error */ +DECLARE_EXCEPTION(4, unknown_exception_entry); /* Overflow */ +DECLARE_EXCEPTION(5, unknown_exception_entry); /* Bounds */ +DECLARE_EXCEPTION(6, invalid_instruction_entry); /* Invalid instruction */ +DECLARE_EXCEPTION(7, unknown_exception_entry); /* Device not present */ +DECLARE_EXCEPTION(8, double_fault_entry); /* Double fault */ +DECLARE_EXCEPTION(9, unknown_exception_entry); /* Co-processor segment overrun */ +DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */ +DECLARE_EXCEPTION(11, seg_fault_entry); /* Segment not present */ +DECLARE_EXCEPTION(12, stack_fault_entry); /* Stack overflow */ +DECLARE_EXCEPTION(13, gpf_entry); /* GPF */ +DECLARE_EXCEPTION(14, page_fault_entry); /* PF */ +DECLARE_EXCEPTION(15, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(16, fp_exception_entry); /* Floating point */ +DECLARE_EXCEPTION(17, alignment_check_entry); /* alignment check */ +DECLARE_EXCEPTION(18, machine_check_entry); /* machine check */ +DECLARE_EXCEPTION(19, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(20, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(21, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(22, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(23, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(24, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(25, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(26, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(27, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(28, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(29, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(30, unknown_exception_entry); /* Reserved */ +DECLARE_EXCEPTION(31, unknown_exception_entry); /* Reserved */ + +DECLARE_INTERRUPT(0); +DECLARE_INTERRUPT(1); +DECLARE_INTERRUPT(3); +DECLARE_INTERRUPT(4); +DECLARE_INTERRUPT(5); +DECLARE_INTERRUPT(6); +DECLARE_INTERRUPT(7); +DECLARE_INTERRUPT(8); +DECLARE_INTERRUPT(9); +DECLARE_INTERRUPT(10); +DECLARE_INTERRUPT(11); +DECLARE_INTERRUPT(12); +DECLARE_INTERRUPT(13); +DECLARE_INTERRUPT(14); +DECLARE_INTERRUPT(15); + +void __attribute__ ((regparm(0))) default_isr(void); +asm ("default_isr: iret\n"); + +void disable_irq(int irq) +{ + if (irq >= MAX_IRQ) { + return; + } + irq_table[irq].status |= IRQ_DISABLED; + +} + +void enable_irq(int irq) +{ + if (irq >= MAX_IRQ) { + return; + } + irq_table[irq].status &= ~IRQ_DISABLED; +} + +/* masks one specific IRQ in the PIC */ +static void unmask_irq(int irq) +{ + int imr_port; + + if (irq >= MAX_IRQ) { + return; + } + if (irq > 7) { + imr_port = SLAVE_PIC + IMR; + } else { + imr_port = MASTER_PIC + IMR; + } + + outb(inb(imr_port)&~(1<<(irq&7)), imr_port); +} + + +/* unmasks one specific IRQ in the PIC */ +static void mask_irq(int irq) +{ + int imr_port; + + if (irq >= MAX_IRQ) { + return; + } + if (irq > 7) { + imr_port = SLAVE_PIC + IMR; + } else { + imr_port = MASTER_PIC + IMR; + } + + outb(inb(imr_port)|(1<<(irq&7)), imr_port); +} + + +/* issue a Specific End Of Interrupt instruciton */ +static void specific_eoi(int irq) +{ + /* If it is on the slave PIC this have to be performed on + * both the master and the slave PICs */ + if (irq > 7) { + outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2); + irq = SEOI_IR2; /* also do IR2 on master */ + } + outb(OCW2_SEOI|irq, MASTER_PIC + OCW2); +} + +void __attribute__ ((regparm(0))) do_irq(int irq) +{ + + mask_irq(irq); + + if (irq_table[irq].status & IRQ_DISABLED) { + unmask_irq(irq); + specific_eoi(irq); + return; + } + + + if (NULL != irq_table[irq].handler) { + irq_handler_t *handler; + for (handler = irq_table[irq].handler; + NULL!= handler; handler = handler->next) { + handler->isr_func(handler->isr_data); + } + } else { + if ((irq & 7) != 7) { + printf("Spurious irq %d\n", irq); + } + } + unmask_irq(irq); + specific_eoi(irq); +} + + +void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg) +{ + printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip); +} + +void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg) +{ + printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip); + while(1); +} + +void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg) +{ + printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip); +} + +void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg) +{ + printf("NMI Interrupt at %04x:%08x\n", seg, ip); +} + +void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg) +{ + printf("Invalid Instruction at %04x:%08x\n", seg, ip); + while(1); +} + +void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg) +{ + printf("Double fault at %04x:%08x\n", seg, ip); + while(1); +} + +void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg) +{ + printf("Invalid TSS at %04x:%08x\n", seg, ip); +} + +void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg) +{ + printf("Segmentation fault at %04x:%08x\n", seg, ip); + while(1); +} + +void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg) +{ + printf("Stack fault at %04x:%08x\n", seg, ip); + while(1); +} + +void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg) +{ + printf("General protection fault at %04x:%08x\n", seg, ip); +} + +void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg) +{ + printf("Page fault at %04x:%08x\n", seg, ip); + while(1); +} + +void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg) +{ + printf("Floating point exception at %04x:%08x\n", seg, ip); +} + +void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg) +{ + printf("Alignment check at %04x:%08x\n", seg, ip); +} + +void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg) +{ + printf("Machine check exception at %04x:%08x\n", seg, ip); +} + + +void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata) +{ + int status; + + if (ino>MAX_IRQ) { + return; + } + + if (NULL != irq_table[ino].handler) { + return; + } + + status = disable_interrupts(); + irq_table[ino].handler = malloc(sizeof(irq_handler_t)); + if (NULL == irq_table[ino].handler) { + return; + } + + memset(irq_table[ino].handler, 0, sizeof(irq_handler_t)); + + irq_table[ino].handler->isr_func = func; + irq_table[ino].handler->isr_data = pdata; + if (status) { + enable_interrupts(); + } + + unmask_irq(ino); + + return; +} + +void irq_free_handler(int ino) +{ + int status; + if (ino>MAX_IRQ) { + return; + } + + status = disable_interrupts(); + mask_irq(ino); + if (NULL == irq_table[ino].handler) { + return; + } + free(irq_table[ino].handler); + irq_table[ino].handler=NULL; + if (status) { + enable_interrupts(); + } + return; +} + + +asm ("idt_ptr:\n" + ".word 0x800\n" /* size of the table 8*256 bytes */ + ".long idt\n" /* offset */ + ".word 0x18\n");/* data segment */ + +static void set_vector(int intnum, void *routine) +{ + idt[intnum].base_high = (u16)((u32)(routine)>>16); + idt[intnum].base_low = (u16)((u32)(routine)&0xffff); +} + + +int interrupt_init(void) +{ + int i; + + /* Just in case... */ + disable_interrupts(); + + /* Initialize the IDT and stuff */ + + + memset(irq_table, 0, sizeof(irq_table)); + + /* Setup the IDT */ + for (i=0;i<256;i++) { + idt[i].access = 0x8e; + idt[i].res = 0; + idt[i].selector = 0x10; + set_vector(i, default_isr); + } + + asm ("cs lidt idt_ptr\n"); + + /* Setup exceptions */ + set_vector(0x00, exp_0); + set_vector(0x01, exp_1); + set_vector(0x02, exp_2); + set_vector(0x03, exp_3); + set_vector(0x04, exp_4); + set_vector(0x05, exp_5); + set_vector(0x06, exp_6); + set_vector(0x07, exp_7); + set_vector(0x08, exp_8); + set_vector(0x09, exp_9); + set_vector(0x0a, exp_10); + set_vector(0x0b, exp_11); + set_vector(0x0c, exp_12); + set_vector(0x0d, exp_13); + set_vector(0x0e, exp_14); + set_vector(0x0f, exp_15); + set_vector(0x10, exp_16); + set_vector(0x11, exp_17); + set_vector(0x12, exp_18); + set_vector(0x13, exp_19); + set_vector(0x14, exp_20); + set_vector(0x15, exp_21); + set_vector(0x16, exp_22); + set_vector(0x17, exp_23); + set_vector(0x18, exp_24); + set_vector(0x19, exp_25); + set_vector(0x1a, exp_26); + set_vector(0x1b, exp_27); + set_vector(0x1c, exp_28); + set_vector(0x1d, exp_29); + set_vector(0x1e, exp_30); + set_vector(0x1f, exp_31); + + + /* Setup interrupts */ + set_vector(0x20, irq_0); + set_vector(0x21, irq_1); + set_vector(0x23, irq_3); + set_vector(0x24, irq_4); + set_vector(0x25, irq_5); + set_vector(0x26, irq_6); + set_vector(0x27, irq_7); + set_vector(0x28, irq_8); + set_vector(0x29, irq_9); + set_vector(0x2a, irq_10); + set_vector(0x2b, irq_11); + set_vector(0x2c, irq_12); + set_vector(0x2d, irq_13); + set_vector(0x2e, irq_14); + set_vector(0x2f, irq_15); + /* vectors 0x30-0x3f are reserved for irq 16-31 */ + + + /* Mask all interrupts */ + outb(0xff, MASTER_PIC + IMR); + outb(0xff, SLAVE_PIC + IMR); + + /* Master PIC */ + outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1); + outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */ + outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */ + outb(ICW4_PM, MASTER_PIC + ICW4); + + for (i=0;i<8;i++) { + outb(OCW2_SEOI|i, MASTER_PIC + OCW2); + } + + /* Slave PIC */ + outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1); + outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */ + outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */ + outb(ICW4_PM, SLAVE_PIC + ICW4); + + for (i=0;i<8;i++) { + outb(OCW2_SEOI|i, SLAVE_PIC + OCW2); + } + + + /* enable cascade interrerupt */ + outb(0xfb, MASTER_PIC + IMR); + outb(0xff, SLAVE_PIC + IMR); + + /* It is now safe to enable interrupts */ + enable_interrupts(); + + return 0; +} + +void enable_interrupts(void) +{ + asm("sti\n"); +} + +int disable_interrupts(void) +{ + long flags; + + asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : ); + + return (flags&0x200); /* IE flags is bit 9 */ +} + + +#ifdef CFG_RESET_GENERIC + +void __attribute__ ((regparm(0))) generate_gpf(void); +asm(".globl generate_gpf\n" + "generate_gpf:\n" + "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not + * exist */ +void reset_cpu(ulong addr) +{ + set_vector(13, generate_gpf); /* general protection fault handler */ + set_vector(8, generate_gpf); /* double fault handler */ + generate_gpf(); /* start the show */ +} +#endif diff --git a/cpu/i386/reset.S b/cpu/i386/reset.S new file mode 100644 index 0000000..07a7384 --- /dev/null +++ b/cpu/i386/reset.S @@ -0,0 +1,37 @@ +/* + * U-boot - i386 Startup Code + * + * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Reset vector, jumps to start16.S */ + +.extern start16 + +.section .reset, "ax" +.code16 +reset_vector: + cli + cld + jmp start16 + + .org 0xf + nop diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c new file mode 100644 index 0000000..689e775 --- /dev/null +++ b/cpu/i386/sc520.c @@ -0,0 +1,501 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* stuff specific for the sc520, + * but idependent of implementation */ + +#include + +#ifdef CONFIG_SC520 + +#include +#include +#include +#include +#include +#include +#include + +/* + * utility functions for boards based on the AMD sc520 + * + * void write_mmcr_byte(u16 mmcr, u8 data) + * void write_mmcr_word(u16 mmcr, u16 data) + * void write_mmcr_long(u16 mmcr, u32 data) + * + * u8 read_mmcr_byte(u16 mmcr) + * u16 read_mmcr_word(u16 mmcr) + * u32 read_mmcr_long(u16 mmcr) + * + * void init_sc520(void) + * unsigned long init_sc520_dram(void) + * void pci_sc520_init(struct pci_controller *hose) + * + * void reset_timer(void) + * ulong get_timer(ulong base) + * void set_timer(ulong t) + * void udelay(unsigned long usec) + * + */ + +static u32 mmcr_base= 0xfffef000; + +void write_mmcr_byte(u16 mmcr, u8 data) +{ + writeb(data, mmcr+mmcr_base); +} + +void write_mmcr_word(u16 mmcr, u16 data) +{ + writew(data, mmcr+mmcr_base); +} + +void write_mmcr_long(u16 mmcr, u32 data) +{ + writel(data, mmcr+mmcr_base); +} + +u8 read_mmcr_byte(u16 mmcr) +{ + return readb(mmcr+mmcr_base); +} + +u16 read_mmcr_word(u16 mmcr) +{ + return readw(mmcr+mmcr_base); +} + +u32 read_mmcr_long(u16 mmcr) +{ + return readl(mmcr+mmcr_base); +} + + +void init_sc520(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Set the UARTxCTL register at it's slower, + * baud clock giving us a 1.8432 MHz reference + */ + write_mmcr_byte(SC520_UART1CTL, 7); + write_mmcr_byte(SC520_UART2CTL, 7); + + /* first set the timer pin mapping */ + write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */ + + /* enable PCI bus arbitrer */ + write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */ + + write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */ + write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */ + + + if (CFG_SC520_HIGH_SPEED) { + write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */ + gd->cpu_clk = 133000000; + printf("## CPU Speed set to 133MHz\n"); + } else { + write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */ + printf("## CPU Speed set to 100MHz\n"); + gd->cpu_clk = 100000000; + } + + + /* wait at least one millisecond */ + asm("movl $0x2000,%%ecx\n" + "wait_loop: pushl %%ecx\n" + "popl %%ecx\n" + "loop wait_loop\n": : : "ecx"); + + /* turn on the SDRAM write buffer */ + write_mmcr_byte(SC520_DBCTL, 0x11); + + /* turn on the cache and disable write through */ + asm("movl %%cr0, %%eax\n" + "andl $0x9fffffff, %%eax\n" + "movl %%eax, %%cr0\n" : : : "eax"); +} + +unsigned long init_sc520_dram(void) +{ + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; + + u32 dram_present=0; + u32 dram_ctrl; + + int val; + + int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY; + int refresh_rate = CFG_SDRAM_REFRESH_RATE; + int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY; + + /* set SDRAM speed here */ + + refresh_rate/=78; + if (refresh_rate<=1) { + val = 0; /* 7.8us */ + } else if (refresh_rate==2) { + val = 1; /* 15.6us */ + } else if (refresh_rate==3 || refresh_rate==4) { + val = 2; /* 31.2us */ + } else { + val = 3; /* 62.4us */ + } + write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4)); + + val = read_mmcr_byte(SC520_DRCTMCTL); + val &= 0xf0; + + if (cas_precharge_delay==3) { + val |= 0x04; /* 3T */ + } else if (cas_precharge_delay==4) { + val |= 0x08; /* 4T */ + } else if (cas_precharge_delay>4) { + val |= 0x0c; + } + + if (ras_cas_delay > 3) { + val |= 2; + } else { + val |= 1; + } + write_mmcr_byte(SC520_DRCTMCTL, val); + + + /* We read-back the configuration of the dram + * controller that the assembly code wrote */ + dram_ctrl = read_mmcr_long(SC520_DRCBENDADR); + + + bd->bi_dram[0].start = 0; + if (dram_ctrl & 0x80) { + /* bank 0 enabled */ + dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; + bd->bi_dram[0].size = bd->bi_dram[1].start; + + } else { + bd->bi_dram[0].size = 0; + bd->bi_dram[1].start = bd->bi_dram[0].start; + } + + if (dram_ctrl & 0x8000) { + /* bank 1 enabled */ + dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14; + bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start; + } else { + bd->bi_dram[1].size = 0; + bd->bi_dram[2].start = bd->bi_dram[1].start; + } + + if (dram_ctrl & 0x800000) { + /* bank 2 enabled */ + dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6; + bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start; + } else { + bd->bi_dram[2].size = 0; + bd->bi_dram[3].start = bd->bi_dram[2].start; + } + + if (dram_ctrl & 0x80000000) { + /* bank 3 enabled */ + dram_present = (dram_ctrl & 0x7f000000) >> 2; + bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start; + } else { + bd->bi_dram[3].size = 0; + } + + +#if 0 + printf("Configured %d bytes of dram\n", dram_present); +#endif + gd->ram_size = dram_present; + + return dram_present; +} + + +#ifdef CONFIG_PCI + + +static struct { + u8 priority; + u16 level_reg; + u8 level_bit; +} sc520_irq[] = { + { SC520_IRQ0, SC520_MPICMODE, 0x01 }, + { SC520_IRQ1, SC520_MPICMODE, 0x02 }, + { SC520_IRQ2, SC520_SL1PICMODE, 0x02 }, + { SC520_IRQ3, SC520_MPICMODE, 0x08 }, + { SC520_IRQ4, SC520_MPICMODE, 0x10 }, + { SC520_IRQ5, SC520_MPICMODE, 0x20 }, + { SC520_IRQ6, SC520_MPICMODE, 0x40 }, + { SC520_IRQ7, SC520_MPICMODE, 0x80 }, + + { SC520_IRQ8, SC520_SL1PICMODE, 0x01 }, + { SC520_IRQ9, SC520_SL1PICMODE, 0x02 }, + { SC520_IRQ10, SC520_SL1PICMODE, 0x04 }, + { SC520_IRQ11, SC520_SL1PICMODE, 0x08 }, + { SC520_IRQ12, SC520_SL1PICMODE, 0x10 }, + { SC520_IRQ13, SC520_SL1PICMODE, 0x20 }, + { SC520_IRQ14, SC520_SL1PICMODE, 0x40 }, + { SC520_IRQ15, SC520_SL1PICMODE, 0x80 } +}; + + +/* The interrupt used for PCI INTA-INTD */ +int sc520_pci_ints[15] = { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 +}; + +/* utility function to configure a pci interrupt */ +int pci_sc520_set_irq(int pci_pin, int irq) +{ + int i; + +# if 0 + printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); +#endif + if (irq < 0 || irq > 15) { + return -1; /* illegal irq */ + } + + if (pci_pin < 0 || pci_pin > 15) { + return -1; /* illegal pci int pin */ + } + + /* first disable any non-pci interrupt source that use + * this level */ + for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) { + if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) { + continue; + } + if (read_mmcr_byte(i) == sc520_irq[irq].priority) { + write_mmcr_byte(i, SC520_IRQ_DISABLED); + } + } + + /* Set the trigger to level */ + write_mmcr_byte(sc520_irq[irq].level_reg, + read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit); + + + if (pci_pin < 4) { + /* PCI INTA-INTD */ + /* route the interrupt */ + write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority); + + + } else { + /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ + write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority); + + /* also set the polarity in this case */ + write_mmcr_word(SC520_INTPINPOL, + read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4))); + + } + + /* register the pin */ + sc520_pci_ints[pci_pin] = irq; + + + return 0; /* OK */ +} + +void pci_sc520_init(struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region(hose->regions + 0, + SC520_PCI_MEMORY_BUS, + SC520_PCI_MEMORY_PHYS, + SC520_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + SC520_PCI_MEM_BUS, + SC520_PCI_MEM_PHYS, + SC520_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 2, + SC520_ISA_MEM_BUS, + SC520_ISA_MEM_PHYS, + SC520_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 3, + SC520_PCI_IO_BUS, + SC520_PCI_IO_PHYS, + SC520_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 4, + SC520_ISA_IO_BUS, + SC520_ISA_IO_PHYS, + SC520_ISA_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 5; + + pci_setup_type1(hose, + SC520_REG_ADDR, + SC520_REG_DATA); + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); + + /* enable target memory acceses on host brige */ + pci_write_config_word(0, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + +} + + +#endif + +#ifdef CFG_TIMER_SC520 + + +void reset_timer(void) +{ + write_mmcr_word(SC520_GPTMR0CNT, 0); + write_mmcr_word(SC520_GPTMR0CTL, 0x6001); + +} + +ulong get_timer(ulong base) +{ + /* fixme: 30 or 33 */ + return read_mmcr_word(SC520_GPTMR0CNT) / 33; +} + +void set_timer(ulong t) +{ + /* FixMe: use two cascade coupled timers */ + write_mmcr_word(SC520_GPTMR0CTL, 0x4001); + write_mmcr_word(SC520_GPTMR0CNT, t*33); + write_mmcr_word(SC520_GPTMR0CTL, 0x6001); +} + + +void udelay(unsigned long usec) +{ + int m=0; + long u; + + read_mmcr_word(SC520_SWTMRMILLI); + read_mmcr_word(SC520_SWTMRMICRO); + +#if 0 + /* do not enable this line, udelay is used in the serial driver -> recursion */ + printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu); +#endif + while (1) { + + m += read_mmcr_word(SC520_SWTMRMILLI); + u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000); + + if (usec <= u) { + break; + } + } +} + +#endif + +int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) +{ + u8 temp=0; + + if (freq >= 8192) { + temp |= CTL_CLK_SEL_4; + } else if (freq >= 4096) { + temp |= CTL_CLK_SEL_8; + } else if (freq >= 2048) { + temp |= CTL_CLK_SEL_16; + } else if (freq >= 1024) { + temp |= CTL_CLK_SEL_32; + } else if (freq >= 512) { + temp |= CTL_CLK_SEL_64; + } else if (freq >= 256) { + temp |= CTL_CLK_SEL_128; + } else if (freq >= 128) { + temp |= CTL_CLK_SEL_256; + } else { + temp |= CTL_CLK_SEL_512; + } + + if (!lsb_first) { + temp |= MSBF_ENB; + } + + if (inv_clock) { + temp |= CLK_INV_ENB; + } + + if (inv_phase) { + temp |= PHS_INV_ENB; + } + + write_mmcr_byte(SC520_SSICTL, temp); + + return 0; +} + +u8 ssi_txrx_byte(u8 data) +{ + write_mmcr_byte(SC520_SSIXMIT, data); + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV); + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + return read_mmcr_byte(SC520_SSIRCV); +} + + +void ssi_tx_byte(u8 data) +{ + write_mmcr_byte(SC520_SSIXMIT, data); + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT); +} + +u8 ssi_rx_byte(void) +{ + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV); + while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); + return read_mmcr_byte(SC520_SSIRCV); +} + +#endif /* CONFIG_SC520 */ diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S new file mode 100644 index 0000000..80464fa --- /dev/null +++ b/cpu/i386/sc520_asm.S @@ -0,0 +1,536 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is largely based on code obtned from AMD. AMD's original + * copyright is included below + */ + +/* + * ============================================================================= + * + * Copyright 1999 Advanced Micro Devices, Inc. + * + * This software is the property of Advanced Micro Devices, Inc (AMD) which + * specifically grants the user the right to modify, use and distribute this + * software provided this COPYRIGHT NOTICE is not removed or altered. All + * other rights are reserved by AMD. + * + * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY + * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF + * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. + * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, LOSS OF INFORMAITON) ARISING OUT OF THE USE OF OR INABILITY + * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR + * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE + * LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors that may appear in + * the Materials nor any responsibility to support or update the Materials. + * AMD retains the right to make changes to its test specifications at any + * time, without notice. + * + * So that all may benefit from your experience, please report any problems + * or suggestions about this software back to AMD. Please include your name, + * company, telephone number, AMD product requiring support and question or + * problem encountered. + * + * Advanced Micro Devices, Inc. Worldwide support and contact + * Embedded Processor Division information available at: + * Systems Engineering epd.support@amd.com + * 5204 E. Ben White Blvd. -or- + * Austin, TX 78741 http://www.amd.com/html/support/techsup.html + * ============================================================================ + */ + + +/******************************************************************************* + * AUTHOR : Buddy Fey - Original. + ******************************************************************************* + */ + + +/******************************************************************************* + * FUNCTIONAL DESCRIPTION: + * This routine is called to autodetect the geometry of the DRAM. + * + * This routine is called to determine the number of column bits for the DRAM + * devices in this external bank. This routine assumes that the external bank + * has been configured for an 11-bit column and for 4 internal banks. This gives + * us the maximum address reach in memory. By writing a test value to the max + * address and locating where it aliases to, we can determine the number of valid + * column bits. + * + * This routine is called to determine the number of internal banks each DRAM + * device has. The external bank (under test) is configured for maximum reach + * with 11-bit columns and 4 internal banks. This routine will write to a max + * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if + * that column is a "don't care". If BA1 does not affect write/read of data, + * then this device has only 2 internal banks. + * + * This routine is called to determine the ending address for this external + * bank of SDRAM. We write to a max address with a data value and then disable + * row address bits looking for "don't care" locations. Each "don't care" bit + * represents a dividing of the maximum density (128M) by 2. By dividing the + * maximum of 32 4M chunks in an external bank down by all the "don't care" bits + * determined during sizing, we set the proper density. + * + * WARNINGS. + * bp must be preserved because it is used for return linkage. + * + * EXIT + * nothing returned - but the memory subsystem is enabled + ******************************************************************************* + */ + +#include +#ifdef CONFIG_SC520 + +.section .text +.equ DRCCTL, 0x0fffef010 /* DRAM control register */ +.equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */ +.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */ +.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */ +.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */ +.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */ + +.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */ +.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */ +.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */ +.equ COL09_ADR, 0x0e000600 /* 9 col addrs */ +.equ COL08_ADR, 0x0e000200 /* 8 col addrs */ +.equ ROW14_ADR, 0x0f000000 /* 14 row addrs */ +.equ ROW13_ADR, 0x07000000 /* 13 row addrs */ +.equ ROW12_ADR, 0x03000000 /* 12 row addrs */ +.equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */ +.equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */ +.equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */ +.equ COL10_DATA, 0x0a0a0a0a /* 10 col data */ +.equ COL09_DATA, 0x09090909 /* 9 col data */ +.equ COL08_DATA, 0x08080808 /* 8 col data */ +.equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */ +.equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */ +.equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */ +.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */ +.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */ + + + /* + * initialize dram controller registers + */ +.globl mem_init +mem_init: + xorw %ax,%ax + movl $DBCTL, %edi + movb %al, (%edi) /* disable write buffer */ + + movl $ECCCTL, %edi + movb %al, (%edi) /* disable ECC */ + + movl $DRCTMCTL, %edi + movb $0x1E,%al /* Set SDRAM timing for slowest */ + movb %al, (%edi) + + /* + * setup loop to do 4 external banks starting with bank 3 + */ + movl $0xff000000,%eax /* enable last bank and setup */ + movl $DRCBENDADR, %edi /* ending address register */ + movl %eax, (%edi) + + movl $DRCCFG, %edi /* setup */ + movw $0xbbbb,%ax /* dram config register for */ + movw %ax, (%edi) + + /* + * issue a NOP to all DRAMs + */ + movl $DRCCTL, %edi /* setup DRAM control register with */ + movb $0x1,%al /* Disable refresh,disable write buffer */ + movb %al, (%edi) + movl $CACHELINESZ, %esi /* just a dummy address to write for */ + movw %ax, (%esi) + /* + * delay for 100 usec? 200? + * ******this is a cludge for now ************* + */ + movw $100,%cx +sizdelay: + loop sizdelay /* we need 100 usec here */ + /***********************************************/ + + /* + * issue all banks precharge + */ + movb $0x2,%al /* All banks precharge */ + movb %al, (%edi) + movw %ax, (%esi) + + /* + * issue 2 auto refreshes to all banks + */ + movb $0x4,%al /* Auto refresh cmd */ + movb %al, (%edi) + movw $2,%cx +refresh1: + movw %ax, (%esi) + loop refresh1 + + /* + * issue LOAD MODE REGISTER command + */ + movb $0x3,%al /* Load mode register cmd */ + movb %al, (%edi) + movw %ax, (%esi) + + /* + * issue 8 more auto refreshes to all banks + */ + movb $0x4,%al /* Auto refresh cmd */ + movb %al, (%edi) + movw $8,%cx +refresh2: + movw %ax, (%esi) + loop refresh2 + + /* + * set control register to NORMAL mode + */ + movb $0x0,%al /* Normal mode value */ + movb %al, (%edi) + + /* + * size dram starting with external bank 3 moving to external bank 0 + */ + movl $0x3,%ecx /* start with external bank 3 */ + +nextbank: + + /* + * write col 11 wrap adr + */ + movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ + movl $COL11_DATA, %eax /* pattern for max supported columns(11) */ + movl %eax, (%esi) /* write max col pattern at max col adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx,%eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + /* + * write col 10 wrap adr + */ + + movl $COL10_ADR, %esi /* set address to 10 col wrap address */ + movl $COL10_DATA, %eax /* pattern for 10 col wrap */ + movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx,%eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + /* + * write col 9 wrap adr + */ + movl $COL09_ADR, %esi /* set address to 9 col wrap address */ + movl $COL09_DATA, %eax /* pattern for 9 col wrap */ + movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx,%eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + /* + * write col 8 wrap adr + */ + movl $COL08_ADR, %esi /* set address to min(8) col wrap address */ + movl $COL08_DATA, %eax /* pattern for min (8) col wrap */ + movl %eax, (%esi) /* write min col pattern @ min col adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx,%eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + /* + * write row 14 wrap adr + */ + movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */ + movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */ + movl %eax, (%esi) /* write max row pattern at max row adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx,%eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + /* + * write row 13 wrap adr + */ + movl $ROW13_ADR, %esi /* set address to 13 row wrap address */ + movl $ROW13_DATA, %eax /* pattern for 13 row wrap */ + movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx,%eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + /* + * write row 12 wrap adr + */ + movl $ROW12_ADR, %esi /* set address to 12 row wrap address */ + movl $ROW12_DATA, %eax /* pattern for 12 row wrap */ + movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx,%eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + /* + * write row 11 wrap adr + */ + movl $ROW11_ADR, %edi /* set address to 11 row wrap address */ + movl $ROW11_DATA, %eax /* pattern for 11 row wrap */ + movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */ + movl (%edi), %ebx /* optional read */ + cmpl %ebx,%eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + /* + * write row 10 wrap adr --- this write is really to determine number of banks + */ + movl $ROW10_ADR, %edi /* set address to 10 row wrap address */ + movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */ + movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */ + movl (%edi), %ebx /* optional read */ + cmpl %ebx,%eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + /* + * read data @ row 12 wrap adr to determine * banks, + * and read data @ row 14 wrap adr to determine * rows. + * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. + * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 + * if data @ row 12 wrap == 11 or 12, we have 4 banks, + */ + xorw %di,%di /* value for 2 banks in DI */ + movl (%esi), %ebx /* read from 12 row wrap to check banks + * (esi is setup from the write to row 12 wrap) */ + cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */ + jz only2 /* if pattern == AA, we only have 2 banks */ + + /* 4 banks */ + + movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */ + cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */ + jz only2 + cmpl $ROW12_DATA, %ebx /* and 12 */ + jnz bad_ram /* its bad if not 11 or 12! */ + + /* fall through */ +only2: + /* + * validate row mask + */ + movl $ROW14_ADR, %esi /* set address back to max row wrap addr */ + movl (%esi), %eax /* read actual number of rows @ row14 adr */ + + cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */ + jb bad_ram + + cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */ + ja bad_ram + + cmpb %ah,%al /* verify all 4 bytes of dword same */ + jnz bad_ram + movl %eax,%ebx + shrl $16,%ebx + cmpw %bx,%ax + jnz bad_ram + /* + * read col 11 wrap adr for real column data value + */ + movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ + movl (%esi), %eax /* read real col number at max col adr */ + /* + * validate column data + */ + cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */ + jb bad_ram + + cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */ + ja bad_ram + + subl $COL08_DATA, %eax /* normalize column data to zero */ + jc bad_ram + cmpb %ah,%al /* verify all 4 bytes of dword equal */ + jnz bad_ram + movl %eax,%edx + shrl $16,%edx + cmpw %dx,%ax + jnz bad_ram + /* + * merge bank and col data together + */ + addw %di,%dx /* merge of bank and col info in dl */ + /* + * fix ending addr mask based upon col info + */ + movb $3,%al + subb %dh,%al /* dh contains the overflow from the bank/col merge */ + movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */ + xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */ + shrb %cl,%dh /* */ + incb %dh /* ending addr is 1 greater than real end */ + xchgw %cx,%ax /* cx is bank number again */ + /* + * issue all banks precharge + */ +bad_reint: + movl $DRCCTL, %esi /* setup DRAM control register with */ + movb $0x2,%al /* All banks precharge */ + movb %al, (%esi) + movl $CACHELINESZ, %esi /* address to init read buffer */ + movw %ax, (%esi) + + /* + * update ENDING ADDRESS REGISTER + */ + movl $DRCBENDADR, %edi /* DRAM ending address register */ + movl %ecx,%ebx + addl %ebx, %edi + movb %dh, (%edi) + /* + * update CONFIG REGISTER + */ + xorb %dh,%dh + movw $0x00f,%bx + movw %cx,%ax + shlw $2,%ax + xchgw %cx,%ax + shlw %cl,%dx + shlw %cl,%bx + notw %bx + xchgw %cx,%ax + movl $DRCCFG, %edi + mov (%edi), %ax + andw %bx,%ax + orw %dx,%ax + movw %ax, (%edi) + jcxz cleanup + + decw %cx + movl %ecx,%ebx + movl $DRCBENDADR, %edi /* DRAM ending address register */ + movb $0xff,%al + addl %ebx, %edi + movb %al, (%edi) + /* + * set control register to NORMAL mode + */ + movl $DRCCTL, %esi /* setup DRAM control register with */ + movb $0x0,%al /* Normal mode value */ + movb %al, (%esi) + movl $CACHELINESZ, %esi /* address to init read buffer */ + movw %ax, (%esi) + jmp nextbank + +cleanup: + movl $DRCBENDADR, %edi /* DRAM ending address register */ + movw $4,%cx + xorw %ax,%ax +cleanuplp: + movb (%edi), %al + orb %al,%al + jz emptybank + + addb %ah,%al + jns nottoomuch + + movb $0x7f,%al +nottoomuch: + movb %al,%ah + orb $0x80,%al + movb %al, (%edi) +emptybank: + incl %edi + loop cleanuplp + +#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T) + /* set the CAS latency now since it is hard to do + * when we run from the RAM */ + movl $DRCTMCTL, %edi /* DRAM timing register */ + movb (%edi), %al +#ifdef CFG_SDRAM_CAS_LATENCY_2T + andb $0xef, %al +#endif +#ifdef CFG_SDRAM_CAS_LATENCY_3T + orb $0x10, %al +#endif + movb %al, (%edi) +#endif + movl $DRCCTL, %edi /* DRAM Control register */ + movb $0x3,%al /* Load mode register cmd */ + movb %al, (%edi) + movw %ax, (%esi) + + + movl $DRCCTL, %edi /* DRAM Control register */ + movb $0x18,%al /* Enable refresh and NORMAL mode */ + movb %al, (%edi) + + jmp dram_done + +bad_ram: + xorl %edx,%edx + xorl %edi,%edi + jmp bad_reint + +dram_done: + + /* readback DRCBENDADR and return the number + * of available ram bytes in %eax */ + + movl $DRCBENDADR, %edi /* DRAM ending address register */ + + movl (%edi), %eax + movl %eax, %ecx + andl $0x80000000, %ecx + jz bank2 + andl $0x7f000000, %eax + shrl $2, %eax + movl %eax, %ebx + +bank2: movl (%edi), %eax + movl %eax, %ecx + andl $0x00800000, %ecx + jz bank1 + andl $0x007f0000, %eax + shll $6, %eax + movl %eax, %ebx + +bank1: movl (%edi), %eax + movl %eax, %ecx + andl $0x00008000, %ecx + jz bank0 + andl $0x00007f00, %eax + shll $14, %eax + movl %eax, %ebx + +bank0: movl (%edi), %eax + movl %eax, %ecx + andl $0x00000080, %ecx + jz done + andl $0x0000007f, %eax + shll $22, %eax + movl %eax, %ebx + +done: movl %ebx, %eax + + jmp *%ebp + + +#endif /* CONFIG_SC520 */ diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c new file mode 100644 index 0000000..db13008 --- /dev/null +++ b/cpu/i386/serial.c @@ -0,0 +1,509 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/*------------------------------------------------------------------------------+ */ + +/* + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + */ +/*------------------------------------------------------------------------------- */ + +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO +#include +#endif + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncLSRDataReady1 0x01 +#define asyncLSROverrunError1 0x02 +#define asyncLSRParityError1 0x04 +#define asyncLSRFramingError1 0x08 +#define asyncLSRBreakInterrupt1 0x10 +#define asyncLSRTxHoldEmpty1 0x20 +#define asyncLSRTxShiftEmpty1 0x40 +#define asyncLSRRxFifoError1 0x80 + + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO +/*-----------------------------------------------------------------------------+ + | Fifo + +-----------------------------------------------------------------------------*/ +typedef struct { + char *rx_buffer; + ulong rx_put; + ulong rx_get; + int cts; +} serial_buffer_t; + +volatile serial_buffer_t buf_info; +static int serial_buffer_active=0; +#endif + + +static int serial_div(int baudrate) +{ + + switch (baudrate) { + case 1200: + return 96; + case 9600: + return 12; + case 19200: + return 6; + case 38400: + return 3; + case 57600: + return 2; + case 115200: + return 1; + } + + return 12; +} + + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +int serial_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile char val; + + int bdiv = serial_div(gd->baudrate); + + + outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ + outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */ + outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ + outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ + outb(0x01, UART0_BASE + UART_FCR); /* enable FIFO */ + outb(0x0b, UART0_BASE + UART_MCR); /* Set DTR and RTS active */ + val = inb(UART0_BASE + UART_LSR); /* clear line status */ + val = inb(UART0_BASE + UART_RBR); /* read receive buffer */ + outb(0x00, UART0_BASE + UART_SCR); /* set scratchpad */ + outb(0x00, UART0_BASE + UART_IER); /* set interrupt enable reg */ + + return 0; +} + + +void serial_setbrg(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned short bdiv; + + bdiv = serial_div(gd->baudrate); + + outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ + outb(bdiv&0xff, UART0_BASE + UART_DLL); /* set baudrate divisor */ + outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ + outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ +} + + +void serial_putc(const char c) +{ + int i; + + if (c == '\n') + serial_putc ('\r'); + + /* check THRE bit, wait for transmiter available */ + for (i = 1; i < 3500; i++) { + if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) { + break; + } + udelay(100); + } + outb(c, UART0_BASE + UART_THR); /* put character out */ +} + + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + + +int serial_getc(void) +{ + unsigned char status = 0; + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + if (serial_buffer_active) { + return serial_buffered_getc(); + } +#endif + + while (1) { +#if defined(CONFIG_HW_WATCHDOG) + WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ +#endif /* CONFIG_HW_WATCHDOG */ + status = inb(UART0_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + outb(asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); + } + } + return (0x000000ff & (int) inb (UART0_BASE)); +} + + +int serial_tstc(void) +{ + unsigned char status; + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + if (serial_buffer_active) { + return serial_buffered_tstc(); + } +#endif + + status = inb(UART0_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) { + return (1); + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + outb(asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); + } + return 0; +} + + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + +void serial_isr(void *arg) +{ + int space; + int c; + int rx_put = buf_info.rx_put; + + if (buf_info.rx_get <= rx_put) { + space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get); + } else { + space = buf_info.rx_get - rx_put; + } + + while (inb(UART0_BASE + UART_LSR) & 1) { + c = inb(UART0_BASE); + if (space) { + buf_info.rx_buffer[rx_put++] = c; + space--; + + if (rx_put == buf_info.rx_get) { + buf_info.rx_get++; + if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { + buf_info.rx_get = 0; + } + } + + if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { + rx_put = 0; + if (0 == buf_info.rx_get) { + buf_info.rx_get = 1; + } + + } + + } + if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { + /* Stop flow by setting RTS inactive */ + outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02), + UART0_BASE + UART_MCR); + } + } + buf_info.rx_put = rx_put; +} + +void serial_buffered_init(void) +{ + serial_puts ("Switching to interrupt driven serial input mode.\n"); + buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); + buf_info.rx_put = 0; + buf_info.rx_get = 0; + + if (inb (UART0_BASE + UART_MSR) & 0x10) { + serial_puts ("Check CTS signal present on serial port: OK.\n"); + buf_info.cts = 1; + } else { + serial_puts ("WARNING: CTS signal not present on serial port.\n"); + buf_info.cts = 0; + } + + irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , + serial_isr /*interrupt_handler_t *handler */ , + (void *) &buf_info /*void *arg */ ); + + /* Enable "RX Data Available" Interrupt on UART */ + /* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */ + outb(0x01, UART0_BASE + UART_IER); + + /* Set DTR and RTS active, enable interrupts */ + outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR); + + /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ + outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR); + + serial_buffer_active = 1; +} + +void serial_buffered_putc (const char c) +{ + int i; + /* Wait for CTS */ +#if defined(CONFIG_HW_WATCHDOG) + while (!(inb (UART0_BASE + UART_MSR) & 0x10)) + WATCHDOG_RESET (); +#else + if (buf_info.cts) { + for (i=0;i<1000;i++) { + if ((inb (UART0_BASE + UART_MSR) & 0x10)) { + break; + } + } + if (i!=1000) { + buf_info.cts = 0; + } + } else { + if ((inb (UART0_BASE + UART_MSR) & 0x10)) { + buf_info.cts = 1; + } + } + +#endif + serial_putc (c); +} + +void serial_buffered_puts(const char *s) +{ + serial_puts (s); +} + +int serial_buffered_getc(void) +{ + int space; + int c; + int rx_get = buf_info.rx_get; + int rx_put; + +#if defined(CONFIG_HW_WATCHDOG) + while (rx_get == buf_info.rx_put) + WATCHDOG_RESET (); +#else + while (rx_get == buf_info.rx_put); +#endif + c = buf_info.rx_buffer[rx_get++]; + if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) { + rx_get = 0; + } + buf_info.rx_get = rx_get; + + rx_put = buf_info.rx_put; + if (rx_get <= rx_put) { + space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); + } else { + space = rx_get - rx_put; + } + if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { + /* Start flow by setting RTS active */ + outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR); + } + + return c; +} + +int serial_buffered_tstc(void) +{ + return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; +} + +#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ + + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +/* + AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port + number 0 or number 1 + - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : + configuration has been already done + - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : + configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE +*/ +#if (CONFIG_KGDB_SER_INDEX & 2) +void kgdb_serial_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile char val; + bdiv = serial_div (CONFIG_KGDB_BAUDRATE); + + /* + * Init onboard 16550 UART + */ + outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */ + outb(bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */ + outb(bdiv >> 8), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */ + outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */ + outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */ + outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */ + val = inb(UART1_BASE + UART_LSR); /* clear line status */ + val = inb(UART1_BASE + UART_RBR); /* read receive buffer */ + outb(0x00, UART1_BASE + UART_SCR); /* set scratchpad */ + outb(0x00, UART1_BASE + UART_IER); /* set interrupt enable reg */ +} + + +void putDebugChar(const char c) +{ + if (c == '\n') + serial_putc ('\r'); + + outb(c, UART1_BASE + UART_THR); /* put character out */ + + /* check THRE bit, wait for transfer done */ + while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20); +} + + +void putDebugStr(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + + +int getDebugChar(void) +{ + unsigned char status = 0; + + while (1) { + status = inb(UART1_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + outb(asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR); + } + } + return (0x000000ff & (int) inb(UART1_BASE)); +} + + +void kgdb_interruptible(int yes) +{ + return; +} + +#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ + +void kgdb_serial_init(void) +{ + serial_printf ("[on serial] "); +} + +void putDebugChar(int c) +{ + serial_putc (c); +} + +void putDebugStr(const char *str) +{ + serial_puts (str); +} + +int getDebugChar(void) +{ + return serial_getc (); +} + +void kgdb_interruptible(int yes) +{ + return; +} +#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/i386/start.S b/cpu/i386/start.S new file mode 100644 index 0000000..afcbb24 --- /dev/null +++ b/cpu/i386/start.S @@ -0,0 +1,196 @@ +/* + * U-boot - i386 Startup Code + * + * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +.section .text +.code32 +.globl _start +.type _start, @function +.globl _i386boot_start +_i386boot_start: +_start: + movl $0x18,%eax /* Load our segement registes, the + * gdt have already been loaded by start16.S */ + movw %ax,%fs + movw %ax,%ds + movw %ax,%gs + movw %ax,%es + movw %ax,%ss + + /* We call a few functions in the board support package + * since we have no stack yet we'll have to use %ebp + * to store the return address */ + + /* Early platform init (setup gpio, etc ) */ + mov $early_board_init_ret, %ebp + jmp early_board_init +early_board_init_ret: + + /* The __port80 entry-point should be usabe by now */ + /* so we try to indicate progress */ + movw $0x01, %ax + movl $.progress0, %ebp + jmp __show_boot_progress +.progress0: + + /* size memory */ + mov $mem_init_ret, %ebp + jmp mem_init +mem_init_ret: + + /* check ammount of configured memory + * (we need atleast bss start+bss size+stack size) */ + movl $_i386boot_bss_start, %ecx /* BSS start */ + addl $_i386boot_bss_size, %ecx /* BSS size */ + addl $CFG_STACK_SIZE, %ecx + cmpl %ecx, %eax + jae mem_ok + + /* indicate (lack of) progress */ + movw $0x81, %ax + movl $.progress0a, %ebp + jmp __show_boot_progress +.progress0a: + jmp die +mem_ok: + + /* indicate progress */ + movw $0x02, %ax + movl $.progress1, %ebp + jmp __show_boot_progress +.progress1: + + /* create a stack after the bss */ + movl $_i386boot_bss_start, %eax + addl $_i386boot_bss_size, %eax + addl $CFG_STACK_SIZE, %eax + movl %eax, %esp + + pushl $0 + popl %eax + cmpl $0, %eax + jne no_stack + push $0x55aa55aa + popl %ebx + cmpl $0x55aa55aa, %ebx + je stack_ok + +no_stack: + /* indicate (lack of) progress */ + movw $0x82, %ax + movl $.progress1a, %ebp + jmp __show_boot_progress +.progress1a: + jmp die + + +stack_ok: + /* indicate progress */ + movw $0x03, %ax + movl $.progress2, %ebp + jmp __show_boot_progress +.progress2: + + /* copy data section to ram, size must be 4-byte aligned */ + movl $_i386boot_romdata_dest, %edi /* destination address */ + movl $_i386boot_romdata_start, %esi /* source address */ + movl $_i386boot_romdata_size, %ecx /* number of bytes to copy */ + movl %ecx, %eax + andl $3, %eax + jnz data_fail + + shrl $2, %ecx /* copy 4 byte each time */ + cld + cmpl $0, %ecx + je data_ok +data_segment: + movsl + loop data_segment + jmp data_ok +data_fail: + /* indicate (lack of) progress */ + movw $0x83, %ax + movl $.progress2a, %ebp + jmp __show_boot_progress +.progress2a: + jmp die + +data_ok: + + /* indicate progress */ + movw $0x04, %ax + movl $.progress3, %ebp + jmp __show_boot_progress +.progress3: + + /* clear bss section in ram, size must be 4-byte aligned */ + movl $_i386boot_bss_start, %eax /* BSS start */ + movl $_i386boot_bss_size, %ecx /* BSS size */ + movl %ecx, %eax + andl $3, %eax + jnz bss_fail + shrl $2, %ecx /* clear 4 byte each time */ + cld + cmpl $0, %ecx + je bss_ok +bss: + movl $0, (%edi) + add $4, %edi + loop bss + jmp bss_ok + +bss_fail: + /* indicate (lack of) progress */ + movw $0x84, %ax + movl $.progress3a, %ebp + jmp __show_boot_progress +.progress3a: + jmp die + +bss_ok: + + wbinvd + + + /* indicate progress */ + movw $0x05, %ax + movl $.progress4, %ebp + jmp __show_boot_progress +.progress4: + + call start_i386boot /* Enter, U-boot! */ + + /* indicate (lack of) progress */ + movw $0x85, %ax + movl $.progress4a, %ebp + jmp __show_boot_progress +.progress4a: + +die: hlt + jmp die + hlt diff --git a/cpu/i386/start16.S b/cpu/i386/start16.S new file mode 100644 index 0000000..239f2ff --- /dev/null +++ b/cpu/i386/start16.S @@ -0,0 +1,112 @@ +/* + * U-boot - i386 Startup Code + * + * Copyright (c) 2002, 2003 Omicron Ceti AB, Daniel Engström + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#define BOOT_SEG 0xffff0000 /* linear segment of boot code */ +#define a32 .byte 0x67; +#define o32 .byte 0x66; + +.section .start16, "ax" +.code16 +.globl start16 +start16: + /* First we let the BSP do some early initialization + * this code have to map the flash to its final position + */ + mov $board_init16_ret, %bp + jmp board_init16 +board_init16_ret: + + /* Turn of cache (this might require a 486-class CPU) */ + movl %cr0, %eax + orl $0x60000000,%eax + movl %eax, %cr0 + wbinvd + + /* load the descriptor tables */ +o32 cs lidt idt_ptr +o32 cs lgdt gdt_ptr + + + /* Now, we enter protected mode */ + movl %cr0, %eax + orl $1,%eax + movl %eax, %cr0 + + /* Flush the prefetch queue */ + jmp ff +ff: + + /* Finally jump to the 32bit initialization code */ + movw $code32start, %ax + movw %ax,%bp +o32 cs ljmp *(%bp) + + /* 48-bit far pointer */ +code32start: + .long _start /* offset */ + .word 0x10 /* segment */ + +idt_ptr: + .word 0 /* limit */ + .long 0 /* base */ + +gdt_ptr: + .word 0x30 /* limit (48 bytes = 6 GDT entries) */ + .long BOOT_SEG + gdt /* base */ + + /* The GDT table ... + * + * Selector Type + * 0x00 NULL + * 0x08 Unused + * 0x10 32bit code + * 0x18 32bit data/stack + * 0x20 16bit code + * 0x28 16bit data/stack + */ + +gdt: + .word 0, 0, 0, 0 /* NULL */ + .word 0, 0, 0, 0 /* unused */ + + .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ + .word 0 /* base address = 0 */ + .word 0x9B00 /* code read/exec */ + .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ + + .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ + .word 0x0 /* base address = 0 */ + .word 0x9300 /* data read/write */ + .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ + + .word 0xFFFF /* 64kb */ + .word 0 /* base address = 0 */ + .word 0x9b00 /* data read/write */ + .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ + + .word 0xFFFF /* 64kb */ + .word 0 /* base address = 0 */ + .word 0x9300 /* data read/write */ + .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ diff --git a/cpu/i386/timer.c b/cpu/i386/timer.c new file mode 100644 index 0000000..486d927 --- /dev/null +++ b/cpu/i386/timer.c @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +static volatile unsigned long system_ticks; +static int timer_init_done =0; + +static void timer_isr(void *unused) +{ + system_ticks++; +} + +unsigned long get_system_ticks(void) +{ + return system_ticks; +} + +#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */ +#define TIMER2_VALUE 0x0a8e /* 440Hz */ + +int timer_init(void) +{ + system_ticks = 0; + + irq_install_handler(0, timer_isr, NULL); + + /* initialize timer 0 and 2 + * + * Timer 0 is used to increment system_tick 1000 times/sec + * Timer 1 was used for DRAM refresh in early PC's + * Timer 2 is used to drive the speaker + * (to stasrt a beep: write 3 to port 0x61, + * to stop it again: write 0) + */ + + outb(PIT_CMD_CTR0|PIT_CMD_BOTH|PIT_CMD_MODE2, PIT_BASE + PIT_COMMAND); + outb(TIMER0_VALUE&0xff, PIT_BASE + PIT_T0); + outb(TIMER0_VALUE>>8, PIT_BASE + PIT_T0); + + outb(PIT_CMD_CTR2|PIT_CMD_BOTH|PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND); + outb(TIMER2_VALUE&0xff, PIT_BASE + PIT_T2); + outb(TIMER2_VALUE>>8, PIT_BASE + PIT_T2); + + timer_init_done = 1; + + return 0; +} + + +#ifdef CFG_TIMER_GENERIC + +/* the unit for these is CFG_HZ */ + +/* FixMe: implement these */ +void reset_timer (void) +{ + system_ticks = 0; +} + +ulong get_timer (ulong base) +{ + return (system_ticks - base); +} + +void set_timer (ulong t) +{ + system_ticks = t; +} + +static u16 read_pit(void) +{ + u8 low; + outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND); + low = inb(PIT_BASE + PIT_T0); + return ((inb(PIT_BASE + PIT_T0) << 8) | low); +} + +/* this is not very exact */ +void udelay (unsigned long usec) +{ + int counter; + int wraps; + + if (!timer_init_done) { + return; + } + counter = read_pit(); + wraps = usec/1000; + usec = usec%1000; + + usec*=1194; + usec/=1000; + usec+=counter; + if (usec > 1194) { + usec-=1194; + wraps++; + } + + while (1) { + int new_count = read_pit(); + + if (((new_count < usec) && !wraps) || wraps < 0) { + break; + } + + if (new_count > counter) { + wraps--; + } + counter = new_count; + } + +} + +#if 0 +/* this is a version with debug output */ +void _udelay (unsigned long usec) +{ + int counter; + int wraps; + + int usec1, usec2, usec3; + int wraps1, wraps2, wraps3, wraps4; + int ctr1, ctr2, ctr3, nct1, nct2; + int i; + usec1=usec; + if (!timer_init_done) { + return; + } + counter = read_pit(); + ctr1 = counter; + wraps = usec/1000; + usec = usec%1000; + + usec2 = usec; + wraps1 = wraps; + + usec*=1194; + usec/=1000; + usec+=counter; + if (usec > 1194) { + usec-=1194; + wraps++; + } + + usec3 = usec; + wraps2 = wraps; + + ctr2 = wraps3 = nct1 = 4711; + ctr3 = wraps4 = nct2 = 4711; + i=0; + while (1) { + int new_count = read_pit(); + i++; + if ((new_count < usec && !wraps) || wraps < 0) { + break; + } + + if (new_count > counter) { + wraps--; + } + if (ctr2==4711) { + ctr2 = counter; + wraps3 = wraps; + nct1 = new_count; + } else { + ctr3 = counter; + wraps4 = wraps; + nct2 = new_count; + } + + counter = new_count; + } + + printf("udelay(%d)\n", usec1); + printf("counter %d\n", ctr1); + printf("1: wraps %d, usec %d\n", wraps1, usec2); + printf("2: wraps %d, usec %d\n", wraps2, usec3); + printf("new_count[0] %d counter %d wraps %d\n", nct1, ctr2, wraps3); + printf("new_count[%d] %d counter %d wraps %d\n", i, nct2, ctr3, wraps4); + + printf("%d %d %d %d %d\n", + read_pit(), read_pit(), read_pit(), + read_pit(), read_pit()); +} +#endif +#endif diff --git a/cpu/ixp/Makefile b/cpu/ixp/Makefile new file mode 100644 index 0000000..ba2e589 --- /dev/null +++ b/cpu/ixp/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = serial.o interrupts.o cpu.o timer.o pci.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/ixp/config.mk b/cpu/ixp/config.mk new file mode 100644 index 0000000..eddda39 --- /dev/null +++ b/cpu/ixp/config.mk @@ -0,0 +1,37 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +BIG_ENDIAN = y + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float -mbig-endian + +PLATFORM_CPPFLAGS += -mbig-endian -march=armv4 -mtune=strongarm1100 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c new file mode 100644 index 0000000..9383473 --- /dev/null +++ b/cpu/ixp/cpu.c @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + + pci_init(); + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * just disable everything that can disturb booting linux + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~0x1000; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf ("resetting ...\n"); + + udelay (50000); /* wait 50 ms */ + disable_interrupts (); + reset_cpu (0); + + /*NOTREACHED*/ + return (0); +} + +/* taken from blob */ +void icache_enable (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* set i-cache */ + i |= 0x1000; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void icache_disable (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* clear i-cache */ + i &= ~0x1000; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush i-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); +} + +int icache_status (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* return bit */ + return (i & 0x1000); +} + +/* we will never enable dcache, because we have to setup MMU first */ +void dcache_enable (void) +{ + return; +} + +void dcache_disable (void) +{ + return; +} + +int dcache_status (void) +{ + return 0; /* always off */ +} + +/* FIXME */ +/* +void pci_init(void) +{ + return; +} +*/ diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c new file mode 100644 index 0000000..e260dea --- /dev/null +++ b/cpu/ixp/interrupts.c @@ -0,0 +1,158 @@ +/* vi: set ts=8 sw=8 noet: */ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_USE_IRQ +/* enable IRQ/FIQ interrupts */ +void enable_interrupts (void) +{ +#error: interrupts not implemented yet +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ +#error: interrupts not implemented yet +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + + +int interrupt_init (void) +{ + /* nothing happens here - we don't setup any IRQs */ + return (0); +} diff --git a/cpu/ixp/pci.c b/cpu/ixp/pci.c new file mode 100644 index 0000000..84c4339 --- /dev/null +++ b/cpu/ixp/pci.c @@ -0,0 +1,575 @@ +/* + * IXP PCI Init + * (C) Copyright 2004 eslab.whut.edu.cn + * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include +#include + +static void non_prefetch_read (unsigned int addr, unsigned int cmd, + unsigned int *data); +static void non_prefetch_write (unsigned int addr, unsigned int cmd, + unsigned int data); +static void configure_pins (void); +static void sys_pci_gpio_clock_config (void); +static void pci_bus_scan (void); +static int pci_device_exists (unsigned int deviceNo); +static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus, + unsigned int dev, unsigned int func); +static void sys_pci_device_bars_write (void); +static void calc_bars (PciBar * Bars[], unsigned int nBars, + unsigned int startAddr); + +#define PCI_MEMORY_BUS 0x00000000 +#define PCI_MEMORY_PHY 0x48000000 +#define PCI_MEMORY_SIZE 0x04000000 + +#define PCI_MEM_BUS 0x40000000 +#define PCI_MEM_PHY 0x00000000 +#define PCI_MEM_SIZE 0x04000000 + +#define PCI_IO_BUS 0x40000000 +#define PCI_IO_PHY 0x50000000 +#define PCI_IO_SIZE 0x10000000 + +struct pci_controller hose; + +unsigned int nDevices; +unsigned int nMBars; +unsigned int nIOBars; +PciBar *memBars[IXP425_PCI_MAX_BAR]; +PciBar *ioBars[IXP425_PCI_MAX_BAR]; +PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS]; + +int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val) +{ + unsigned int retval; + unsigned int addr; + + /*address bits 31:28 specify the device 10:8 specify the function */ + /*Set the address to be read */ + addr = BIT ((31 - dev)) | (where & ~3); + non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval); + + *val = retval; + + return (OK); +} + +int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val) +{ + unsigned int n; + unsigned int retval; + unsigned int addr; + unsigned int byteEnables; + + n = where % 4; + /*byte enables are 4 bits active low, the position of each + bit maps to the byte that it enables */ + byteEnables = + (~(BIT (n) | BIT ((n + 1)))) & + IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; + byteEnables = byteEnables << PCI_NP_CBE_BESL; + /*address bits 31:28 specify the device 10:8 specify the function */ + /*Set the address to be read */ + addr = BIT ((31 - dev)) | (where & ~3); + non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); + + /*Pick out the word we are interested in */ + *val = (retval >> (8 * n)); + + return (OK); +} + +int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val) +{ + unsigned int retval; + unsigned int n; + unsigned int byteEnables; + unsigned int addr; + + n = where % 4; + /*byte enables are 4 bits, active low, the position of each + bit maps to the byte that it enables */ + byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; + byteEnables = byteEnables << PCI_NP_CBE_BESL; + + /*address bits 31:28 specify the device, 10:8 specify the function */ + /*Set the address to be read */ + addr = BIT ((31 - dev)) | (where & ~3); + non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); + /*Pick out the byte we are interested in */ + *val = (retval >> (8 * n)); + + return (OK); +} + +int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val) +{ + unsigned int addr; + unsigned int byteEnables; + unsigned int n; + unsigned int ldata; + + n = where % 4; + /*byte enables are 4 bits active low, the position of each + bit maps to the byte that it enables */ + byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; + byteEnables = byteEnables << PCI_NP_CBE_BESL; + ldata = val << (8 * n); + /*address bits 31:28 specify the device 10:8 specify the function */ + /*Set the address to be written */ + addr = BIT ((31 - dev)) | (where & ~3); + non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); + + return (OK); +} + +int pci_write_config_word (pci_dev_t dev, int where, unsigned short val) +{ + unsigned int addr; + unsigned int byteEnables; + unsigned int n; + unsigned int ldata; + + n = where % 4; + /*byte enables are 4 bits active low, the position of each + bit maps to the byte that it enables */ + byteEnables = + (~(BIT (n) | BIT ((n + 1)))) & + IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; + byteEnables = byteEnables << PCI_NP_CBE_BESL; + ldata = val << (8 * n); + /*address bits 31:28 specify the device 10:8 specify the function */ + /*Set the address to be written */ + addr = BIT (31 - dev) | (where & ~3); + non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); + + return (OK); +} + +int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val) +{ + unsigned int addr; + + /*address bits 31:28 specify the device 10:8 specify the function */ + /*Set the address to be written */ + addr = BIT (31 - dev) | (where & ~3); + non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val); + + return (OK); +} + +void non_prefetch_read (unsigned int addr, + unsigned int cmd, unsigned int *data) +{ + REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); + + /*set up and execute the read */ + REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); + + /*The result of the read is now in np_rdata */ + REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data); + + return; +} + +void non_prefetch_write (unsigned int addr, + unsigned int cmd, unsigned int data) +{ + + REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); + /*set up the write */ + REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); + /*Execute the write by writing to NP_WDATA */ + REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data); + + return; +} + +/* + * PCI controller config registers are accessed through these functions + * i.e. these allow us to set up our own BARs etc. + */ +void crp_read (unsigned int offset, unsigned int *data) +{ + REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset); + REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data); +} + +void crp_write (unsigned int offset, unsigned int data) +{ + /*The CRP address register bit 16 indicates that we want to do a write */ + REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, + PCI_CRP_WRITE | offset); + REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data); +} + +/*struct pci_controller *hose*/ +void pci_ixp_init (struct pci_controller *hose) +{ + unsigned int regval; + + hose->first_busno = 0; + hose->last_busno = 0x00; + + /* System memory space */ + pci_set_region (hose->regions + 0, + PCI_MEMORY_BUS, + PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region (hose->regions + 1, + PCI_MEM_BUS, + PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); + /* PCI I/O space */ + pci_set_region (hose->regions + 2, + PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); + + hose->region_count = 3; + + pci_register_hose (hose); + +/* + ========================================================== + Init IXP PCI + ========================================================== +*/ + REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); + regval |= 1 << 2; + REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); + + configure_pins (); + + READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); + WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13))); + udelay (533); + sys_pci_gpio_clock_config (); + REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0); + udelay (100); + READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); + WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13)); + udelay (533); + crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT); + crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT); + crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT); + crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT); + crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT); + crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT); + /*Setup PCI-AHB and AHB-PCI address mappings */ + REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET, + IXP425_PCI_AHBMEMBASE_DEFAULT); + + REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET, + IXP425_PCI_AHBIOBASE_DEFAULT); + + REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET, + IXP425_PCI_PCIMEMBASE_DEFAULT); + + crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); + + REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); + regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS; + REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); + crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); + udelay (1000); + + pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD); + REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE + | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); +#ifdef CONFIG_PCI_SCAN_SHOW + printf ("Device bus dev func deviceID vendorID \n"); +#endif + pci_bus_scan (); +} + +void configure_pins (void) +{ + unsigned int regval; + + /* Disable clock on GPIO PIN 14 */ + READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); + WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8))); + READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); + + READ_GPIO_REG (IXP425_GPIO_GPOER, regval); + WRITE_GPIO_REG (IXP425_GPIO_GPOER, + (((~(3 << 13)) & regval) | (0xf << 8))); + READ_GPIO_REG (IXP425_GPIO_GPOER, regval); + + READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); + WRITE_GPIO_REG (IXP425_GPIO_GPIT2R, + (regval & + ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1))); + READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); + + READ_GPIO_REG (IXP425_GPIO_GPISR, regval); + WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8))); + READ_GPIO_REG (IXP425_GPIO_GPISR, regval); +} + +void sys_pci_gpio_clock_config (void) +{ + unsigned int regval; + + READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); + regval |= 0x1 << 4; + WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); + READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); + regval |= 0x1 << 8; + WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); +} + +void pci_bus_scan (void) +{ + unsigned int bus = 0, dev, func = 0; + unsigned short data16; + unsigned int data32; + unsigned char intPin; + + /* Assign first device to ourselves */ + devices[0].bus = 0; + devices[0].device = 0; + devices[0].func = 0; + + crp_read (PCI_CFG_VENDOR_ID, &data32); + + devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK; + devices[0].device_id = data32 >> 16; + devices[0].error = FALSE; + devices[0].bar[NO_BAR].size = 0; /*dummy - required */ + + nDevices = 1; + + nMBars = 0; + nIOBars = 0; + + for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) { + + /*Check whether a device is present */ + if (pci_device_exists (dev) != TRUE) { + + /*Clear error bits in ISR, write 1 to clear */ + REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE + | PCI_ISR_PFE | PCI_ISR_PPE | + PCI_ISR_AHBE); + continue; + } + + /*A device is present, add an entry to the array */ + devices[nDevices].bus = bus; + devices[nDevices].device = dev; + devices[nDevices].func = func; + + pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16); + + devices[nDevices].vendor_id = data16; + + pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16); + devices[nDevices].device_id = data16; + + /*The device is functioning correctly, set error to FALSE */ + devices[nDevices].error = FALSE; + + /*Figure out what BARs are on this device */ + sys_pci_bar_info_get (nDevices, bus, dev, func); + /*Figure out what INTX# line the card uses */ + pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin); + + /*assign the appropriate irq line */ + if (intPin > PCI_IRQ_LINES) { + devices[nDevices].error = TRUE; + } else if (intPin != 0) { + /*This device uses an interrupt line */ + /*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */ + devices[nDevices].irq = intPin; + } +#ifdef CONFIG_PCI_SCAN_SHOW + printf ("%06d %03d %03d %04d %08d %08x\n", nDevices, + devices[nDevices].vendor_id); +#endif + nDevices++; + + } + + calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE); + sys_pci_device_bars_write (); + + REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE + | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); +} + +void sys_pci_bar_info_get (unsigned int devnum, + unsigned int bus, + unsigned int dev, unsigned int func) +{ + unsigned int data32; + unsigned int tmp; + unsigned int size; + + pci_write_config_dword (devnum, + PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY); + pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32); + + devices[devnum].bar[0].address = (data32 & 1); + + if (data32 & 1) { + /* IO space */ + tmp = data32 & ~0x3; + size = ~(tmp - 1); + devices[devnum].bar[0].size = size; + + if (nIOBars < IXP425_PCI_MAX_BAR) { + ioBars[nIOBars++] = &devices[devnum].bar[0]; + } + } else { + /* Mem space */ + tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; + size = ~(tmp - 1); + devices[devnum].bar[0].size = size; + + if (nMBars < IXP425_PCI_MAX_BAR) { + memBars[nMBars++] = &devices[devnum].bar[0]; + } else { + devices[devnum].error = TRUE; + } + + } + + devices[devnum].bar[1].size = 0; +} + +void sortBars (PciBar * Bars[], unsigned int nBars) +{ + unsigned int i, j; + PciBar *tmp; + + if (nBars == 0) { + return; + } + + /* Sort biggest to smallest */ + for (i = 0; i < nBars - 1; i++) { + for (j = i + 1; j < nBars; j++) { + if (Bars[j]->size > Bars[i]->size) { + /* swap them */ + tmp = Bars[i]; + Bars[i] = Bars[j]; + Bars[j] = tmp; + } + } + } +} + +void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr) +{ + unsigned int i; + + if (nBars == 0) { + return; + } + + for (i = 0; i < nBars; i++) { + Bars[i]->address |= startAddr; + startAddr += Bars[i]->size; + } +} + +void sys_pci_device_bars_write (void) +{ + unsigned int i; + int addr; + + for (i = 1; i < nDevices; i++) { + if (devices[i].error) { + continue; + } + + pci_write_config_dword (devices[i].device, + PCI_CFG_BASE_ADDRESS_0, + devices[i].bar[0].address); + addr = BIT (31 - devices[i].device) | + (0 << PCI_NP_AD_FUNCSL) | + (PCI_CFG_BASE_ADDRESS_0 & ~3); + pci_write_config_dword (devices[i].device, + PCI_CFG_DEV_INT_LINE, devices[i].irq); + + pci_write_config_word (devices[i].device, + PCI_CFG_COMMAND, INITIAL_PCI_CMD); + + } +} + + +int pci_device_exists (unsigned int deviceNo) +{ + unsigned int vendorId; + unsigned int regval; + + pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId); + + /* There are two ways to find out an empty device. + * 1. check Master Abort bit after the access. + * 2. check whether the vendor id read back is 0x0. + */ + REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval); + if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) { + return TRUE; + } + /*no device present, make sure that the master abort bit is reset */ + + REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE); + return FALSE; +} + +pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo) +{ + unsigned int i; + unsigned int devdidvid; + unsigned int didvid; + unsigned int vendorId, deviceId; + + vendorId = ids->vendor; + deviceId = ids->device; + didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) | + (vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK); + + for (i = devNo + 1; i < nDevices; i++) { + + pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID, + &devdidvid); + + if (devdidvid == didvid) { + return devices[i].device; + } + } + return -1; +} +#endif /* CONFIG_PCI */ diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c new file mode 100644 index 0000000..aea0cf8 --- /dev/null +++ b/cpu/ixp/serial.c @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned int quot = 0; + int uart = CFG_IXP425_CONSOLE; + + if (gd->baudrate == 1200) + quot = 192; + else if (gd->baudrate == 9600) + quot = 96; + else if (gd->baudrate == 19200) + quot = 48; + else if (gd->baudrate == 38400) + quot = 24; + else if (gd->baudrate == 57600) + quot = 16; + else if (gd->baudrate == 115200) + quot = 8; + else + hang (); + + IER(uart) = 0; /* Disable for now */ + FCR(uart) = 0; /* No fifos enabled */ + + /* set baud rate */ + LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; + DLL(uart) = quot & 0xff; + DLH(uart) = quot >> 8; + LCR(uart) = LCR_WLS0 | LCR_WLS1; + + IER(uart) = IER_UUE; +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + serial_setbrg (); + + return (0); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + /* wait for room in the tx FIFO on UART */ + while ((LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0); + + THR(CFG_IXP425_CONSOLE) = c; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_tstc (void) +{ + return LSR(CFG_IXP425_CONSOLE) & LSR_DR; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + while (!(LSR(CFG_IXP425_CONSOLE) & LSR_DR)); + + return (char) RBR(CFG_IXP425_CONSOLE) & 0xff; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} diff --git a/cpu/ixp/start.S b/cpu/ixp/start.S new file mode 100644 index 0000000..2726f65 --- /dev/null +++ b/cpu/ixp/start.S @@ -0,0 +1,499 @@ +/* vi: set ts=8 sw=8 noet: */ +/* + * u-boot - Startup Code for XScale IXP + * + * Copyright (C) 2003 Kyle Harris + * + * Based on startup code example contained in the + * Intel IXP4xx Programmer's Guide and past u-boot Start.S + * samples. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define MMU_Control_M 0x001 /* Enable MMU */ +#define MMU_Control_A 0x002 /* Enable address alignment faults */ +#define MMU_Control_C 0x004 /* Enable cache */ +#define MMU_Control_W 0x008 /* Enable write-buffer */ +#define MMU_Control_P 0x010 /* Compatability: 32 bit code */ +#define MMU_Control_D 0x020 /* Compatability: 32 bit data */ +#define MMU_Control_L 0x040 /* Compatability: */ +#define MMU_Control_B 0x080 /* Enable Big-Endian */ +#define MMU_Control_S 0x100 /* Enable system protection */ +#define MMU_Control_R 0x200 /* Enable ROM protection */ +#define MMU_Control_I 0x1000 /* Enable Instruction cache */ +#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */ +#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) + + +/* + * Macro definitions + */ + /* Delay a bit */ + .macro DELAY_FOR cycles, reg0 + ldr \reg0, =\cycles + subs \reg0, \reg0, #1 + subne pc, pc, #0xc + .endm + + /* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * - relocate armboot to ram + * - setup stack + * - jump to second stage + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/****************************************************************************/ +/* */ +/* the actual reset code */ +/* */ +/****************************************************************************/ + +reset: + /* disable mmu, set big-endian */ + mov r0, #0xf8 + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + /* invalidate I & D caches & BTB */ + mcr p15, 0, r0, c7, c7, 0 + CPWAIT r0 + + /* invalidate I & Data TLB */ + mcr p15, 0, r0, c8, c7, 0 + CPWAIT r0 + + /* drain write and fill buffers */ + mcr p15, 0, r0, c7, c10, 4 + CPWAIT r0 + + /* disable write buffer coalescing */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 1 + CPWAIT r0 + + /* set EXP CS0 to the optimum timing */ + ldr r1, =CFG_EXP_CS0 + ldr r2, =IXP425_EXP_CS0 + str r1, [r2] + + /* make sure flash is visible at 0 */ +#if 0 + ldr r2, =IXP425_EXP_CFG0 + ldr r1, [r2] + orr r1, r1, #0x80000000 + str r1, [r2] +#endif + mov r1, #CFG_SDR_CONFIG + ldr r2, =IXP425_SDR_CONFIG + str r1, [r2] + + /* disable refresh cycles */ + mov r1, #0 + ldr r3, =IXP425_SDR_REFRESH + str r1, [r3] + + /* send nop command */ + mov r1, #3 + ldr r4, =IXP425_SDR_IR + str r1, [r4] + DELAY_FOR 0x4000, r0 + + /* set SDRAM internal refresh val */ + ldr r1, =CFG_SDRAM_REFRESH_CNT + str r1, [r3] + DELAY_FOR 0x4000, r0 + + /* send precharge-all command to close all open banks */ + mov r1, #2 + str r1, [r4] + DELAY_FOR 0x4000, r0 + + /* provide 8 auto-refresh cycles */ + mov r1, #4 + mov r5, #8 +111: str r1, [r4] + DELAY_FOR 0x100, r0 + subs r5, r5, #1 + bne 111b + + /* set mode register in sdram */ + mov r1, #CFG_SDR_MODE_CONFIG + str r1, [r4] + DELAY_FOR 0x4000, r0 + + /* send normal operation command */ + mov r1, #6 + str r1, [r4] + DELAY_FOR 0x4000, r0 + + /* copy */ + mov r0, #0 + mov r4, r0 + add r2, r0, #0x40000 + mov r1, #0x10000000 + mov r5, r1 + + 30: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r0, r2 + bne 30b + + /* invalidate I & D caches & BTB */ + mcr p15, 0, r0, c7, c7, 0 + CPWAIT r0 + + /* invalidate I & Data TLB */ + mcr p15, 0, r0, c8, c7, 0 + CPWAIT r0 + + /* drain write and fill buffers */ + mcr p15, 0, r0, c7, c10, 4 + CPWAIT r0 + + /* move flash to 0x50000000 */ + ldr r2, =IXP425_EXP_CFG0 + ldr r1, [r2] + bic r1, r1, #0x80000000 + str r1, [r2] + + nop + nop + nop + nop + nop + nop + + /* invalidate I & Data TLB */ + mcr p15, 0, r0, c8, c7, 0 + CPWAIT r0 + + /* enable I cache */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_I + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + mrs r0,cpsr /* set the cpu to SVC32 mode */ + bic r0,r0,#0x1f /* (superviser mode, M=10011) */ + orr r0,r0,#0x13 + msr cpsr,r0 + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/****************************************************************************/ +/* */ +/* Interrupt handling */ +/* */ +/****************************************************************************/ + +/* IRQ stack frame */ + +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 + + /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r8, sp, #S_PC + + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ + add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ + mov r0, sp + .endm + + + /* use irq_save_user_regs / irq_restore_user_regs for */ + /* IRQ/FIQ handling */ + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ /* Calling SP, LR */ + str lr, [r8, #0] /* Save calling PC */ + mrs r6, spsr + str r6, [r8, #4] /* Save CPSR */ + str r0, [r8, #8] /* Save OLD_R0 */ + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + msr spsr_c, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + + +/****************************************************************************/ +/* */ +/* exception handlers */ +/* */ +/****************************************************************************/ + + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + irq_save_user_regs /* someone ought to write a more */ + bl do_fiq /* effiction fiq_save_user_regs */ + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + +/****************************************************************************/ +/* */ +/* Reset function: Use Watchdog to reset */ +/* */ +/****************************************************************************/ + + .align 5 +.globl reset_cpu + +reset_cpu: + ldr r1, =0x482e + ldr r2, =IXP425_OSWK + str r1, [r2] + ldr r1, =0x0fff + ldr r2, =IXP425_OSWT + str r1, [r2] + ldr r1, =0x5 + ldr r2, =IXP425_OSWE + str r1, [r2] + b reset_endless + + +reset_endless: + + b reset_endless diff --git a/cpu/ixp/timer.c b/cpu/ixp/timer.c new file mode 100644 index 0000000..8df2a31 --- /dev/null +++ b/cpu/ixp/timer.c @@ -0,0 +1,79 @@ +/* vi: set ts=8 sw=8 noet: */ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void ixp425_udelay(unsigned long usec) +{ + /* + * This function has a max usec, but since it is called from udelay + * we should not have to worry... be happy + */ + unsigned long usecs = CFG_HZ/1000000L & ~IXP425_OST_RELOAD_MASK; + + *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; + usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; + *IXP425_OSRT1 = usecs; + while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)); +} + +void udelay (unsigned long usec) +{ + while (usec--) ixp425_udelay(1); +} + +static ulong reload_constant = 0xfffffff0; + +void reset_timer_masked (void) +{ + ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; + + *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; + *IXP425_OSRT1 = reload; +} + +ulong get_timer_masked (void) +{ + /* + * Note that it is possible for this to wrap! + * In this case we return max. + */ + ulong current = *IXP425_OST1; + if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND) + { + return reload_constant; + } + return (reload_constant - current); +} diff --git a/cpu/lh7a40x/Makefile b/cpu/lh7a40x/Makefile new file mode 100644 index 0000000..b45bd6a --- /dev/null +++ b/cpu/lh7a40x/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = cpu.o speed.o interrupts.o serial.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/lh7a40x/config.mk b/cpu/lh7a40x/config.mk new file mode 100644 index 0000000..10e755b --- /dev/null +++ b/cpu/lh7a40x/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 +# ========================================================================= +# +# Supply options according to compiler version +# +# ======================================================================== +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c new file mode 100644 index 0000000..718f253 --- /dev/null +++ b/cpu/lh7a40x/cpu.c @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + +#ifdef MMU_DEBUG + printf ("p15/c1 is = %08lx\n", value); +#endif + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ +#ifdef MMU_DEBUG + printf ("write %08lx to p15/c1\n", value); +#endif + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_IC); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +int icache_status (void) +{ + return (read_p15_c1 () & C1_IC) != 0; +} + +#ifdef USE_920T_MMU +/* It makes no sense to use the dcache if the MMU is not enabled */ +void dcache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg | C1_DC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + reg &= ~C1_DC; + write_p15_c1 (reg); +} + +int dcache_status (void) +{ + return (read_p15_c1 () & C1_DC) != 0; +} +#endif diff --git a/cpu/lh7a40x/interrupts.c b/cpu/lh7a40x/interrupts.c new file mode 100644 index 0000000..23d8039 --- /dev/null +++ b/cpu/lh7a40x/interrupts.c @@ -0,0 +1,329 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +static ulong timer_load_val = 0; + +/* macro to read the 16 bit timer */ +static inline ulong READ_TIMER(void) +{ + lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; + lh7a40x_timer_t* timer = &timers->timer1; + + return (timer->value & 0x0000ffff); +} + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +static ulong timestamp; +static ulong lastdec; + +int interrupt_init (void) +{ + lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; + lh7a40x_timer_t* timer = &timers->timer1; + + /* a periodic timer using the 508kHz source */ + timer->control = (TIMER_PER | TIMER_CLK508K); + + if (timer_load_val == 0) { + /* + * 10ms period with 508.469kHz clock = 5084 + */ + timer_load_val = CFG_HZ/100; + } + + /* load value for 10 ms timeout */ + lastdec = timer->load = timer_load_val; + + /* auto load, start timer */ + timer->control = timer->control | TIMER_EN; + timestamp = 0; + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return (get_timer_masked() - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo,tmp; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 1000; + } + else { + if (usec > 1) { + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + else + tmo = 1; + } + + /* check for rollover during this delay */ + tmp = get_timer (0); + if ((tmp + tmo) < tmp ) + reset_timer_masked(); /* timer would roll over */ + else + tmo += tmp; + + while (get_timer_masked () < tmo); +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += (lastdec - now); + } else { + /* we have an overflow ... */ + timestamp += ((lastdec + timer_load_val) - now); + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 1000; + } else { + if (usec > 1) { + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } else { + tmo = 1; + } + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = timer_load_val * 100; + + return tbclk; +} diff --git a/cpu/lh7a40x/serial.c b/cpu/lh7a40x/serial.c new file mode 100644 index 0000000..ff5b2d8 --- /dev/null +++ b/cpu/lh7a40x/serial.c @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +#if defined(CONFIG_CONSOLE_UART1) +# define UART_CONSOLE 1 +#elif defined(CONFIG_CONSOLE_UART2) +# define UART_CONSOLE 2 +#elif defined(CONFIG_CONSOLE_UART3) +# define UART_CONSOLE 3 +#else +# error "No console configured ... " +#endif + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); + int i; + unsigned int reg = 0; + + /* + * userguide 15.1.2.4 + * + * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1 + * + * UART_REF_FREQ = external system clock input / 2 (Hz) + * BAUD is desired baudrate (bits/s) + * + * NOTE: we add (divisor/2) to numerator to round for + * more precision + */ + reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1; + uart->brcon = reg; + + for (i = 0; i < 100; i++); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); + + /* UART must be enabled before writing to any config registers */ + uart->con |= (UART_EN); + +#ifdef CONFIG_CONSOLE_UART1 + /* infrared disabled */ + uart->con |= UART_SIRD; +#endif + /* loopback disabled */ + uart->con &= ~(UART_LBE); + + /* modem lines and tx/rx polarities */ + uart->con &= ~(UART_MXP | UART_TXP | UART_RXP); + + /* FIFO enable, N81 */ + uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1); + + /* set baudrate */ + serial_setbrg (); + + /* enable rx interrupt */ + uart->inten |= UART_RI; + + return (0); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); + + /* wait for character to arrive */ + while (uart->status & UART_RXFE); + + return(uart->data & 0xff); +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ + switch(on) { + case 0: + default: + break; /* return current */ + case 1: + hwflow = 1; /* turn on */ + break; + case -1: + hwflow = 0; /* turn off */ + break; + } + return hwflow; +} +#endif + +#ifdef CONFIG_MODEM_SUPPORT +static int be_quiet = 0; +void disable_putc(void) +{ + be_quiet = 1; +} + +void enable_putc(void) +{ + be_quiet = 0; +} +#endif + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); + +#ifdef CONFIG_MODEM_SUPPORT + if (be_quiet) + return; +#endif + + /* wait for room in the tx FIFO */ + while (!(uart->status & UART_TXFE)); + +#ifdef CONFIG_HWFLOW + /* Wait for CTS up */ + while(hwflow && !(uart->status & UART_CTS)); +#endif + + uart->data = c; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc (void) +{ + lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); + + return(!(uart->status & UART_RXFE)); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} diff --git a/cpu/lh7a40x/speed.c b/cpu/lh7a40x/speed.c new file mode 100644 index 0000000..333ebb5 --- /dev/null +++ b/cpu/lh7a40x/speed.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +/* ------------------------------------------------------------------------- */ +/* NOTE: This describes the proper use of this file. + * + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. + * + * get_FCLK(), get_HCLK(), get_PCLK() return the clock of + * the specified bus in HZ. + */ +/* ------------------------------------------------------------------------- */ + +ulong get_PLLCLK (void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +/* return FCLK frequency */ +ulong get_FCLK (void) +{ + lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; + ulong maindiv1, maindiv2, prediv, ps; + + /* + * from userguide 6.1.1.2 + * + * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) / + * ((PREDIV+2) * (2^PS)) + */ + maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; + maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; + prediv = (csc->clkset & CLKSET_PREDIV) >> 2; + ps = (csc->clkset & CLKSET_PS) >> 16; + + return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) / + ((prediv + 2) * (1 << ps))); +} + + +/* return HCLK frequency */ +ulong get_HCLK (void) +{ + lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; + + return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); +} + +/* return PCLK frequency */ +ulong get_PCLK (void) +{ + lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; + + return (get_HCLK () / + (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); +} diff --git a/cpu/lh7a40x/start.S b/cpu/lh7a40x/start.S new file mode 100644 index 0000000..fb748cf --- /dev/null +++ b/cpu/lh7a40x/start.S @@ -0,0 +1,428 @@ +/* + * armboot - Startup Code for ARM920 CPU-core + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + +#define pWDTCTL 0x80001400 /* Watchdog Timer control register */ +#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */ +#define pCLKSET 0x80000420 /* clock divisor register */ + + /* disable watchdog, set watchdog control register to + * all zeros (default reset) + */ + ldr r0, =pWDTCTL + mov r1, #0x0 + str r1, [r0] + + /* + * mask all IRQs by setting all bits in the INTENC register (default) + */ + mov r1, #0xffffffff + ldr r0, =pINTENC + str r1, [r0] + + /* FCLK:HCLK:PCLK = 1:2:2 */ + /* default FCLK is 200 MHz, using 14.7456 MHz fin */ + ldr r0, =pCLKSET + ldr r1, =0x0004ee39 +@ ldr r1, =0x0005ee39 @ 1: 2: 4 + str r1, [r0] + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + blt copy_loop /* a 'ble' here actually copies */ + /* four bytes of bss */ +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + @add r0, r0, #4 /* start at first byte of bss */ + /* why inc. 4 bytes past then? */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + + +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus + mcr p15, 0, r0, c1, c0, 0 + + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + + mov pc, lr + + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get pc, cpsr + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + + .align 5 +.globl reset_cpu +reset_cpu: + bl disable_interrupts + + /* Disable watchdog */ + ldr r1, =pWDTCTL + mov r3, #0 + str r3, [r1] + + /* reset counter */ + ldr r3, =0x00001984 + str r3, [r1, #4] + + /* Enable the watchdog */ + mov r3, #1 + str r3, [r1] + +_loop_forever: + b _loop_forever diff --git a/cpu/mcf52x2/Makefile b/cpu/mcf52x2/Makefile new file mode 100644 index 0000000..879deb7 --- /dev/null +++ b/cpu/mcf52x2/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = +OBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk new file mode 100644 index 0000000..650db85 --- /dev/null +++ b/cpu/mcf52x2/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 Josef Baumgartner +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +PLATFORM_CPPFLAGS += -m5307 diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c new file mode 100644 index 0000000..32a524f --- /dev/null +++ b/cpu/mcf52x2/cpu.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2003 + * Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_M5272 +#include +#include +#endif + +#ifdef CONFIG_M5282 + +#endif + +#ifdef CONFIG_M5249 +#include +#endif + + +#ifdef CONFIG_M5272 +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { + volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR); + + wdp->wdog_wrrr = 0; + udelay (1000); + + /* enable watchdog, set timeout to 0 and wait */ + wdp->wdog_wrrr = 1; + while (1); + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) { + ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR); + uchar msk; + char *suf; + + puts ("CPU: "); + msk = (*dirp > 28) & 0xf; + switch (msk) { + case 0x2: suf = "1K75N"; break; + case 0x4: suf = "3K75N"; break; + default: + suf = NULL; + printf ("MOTOROLA MCF5272 (Mask:%01x)\n", msk); + break; + } + + if (suf) + printf ("MOTOROLA MCF5272 %s\n", suf); + return 0; +}; + + +#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset (void) +{ + volatile immap_t * regp = (volatile immap_t *)CFG_MBAR; + regp->wdog_reg.wdog_wcr = 0; +} + +int watchdog_disable (void) +{ + volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; + + regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ + regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ + regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */ + + puts ("WATCHDOG:disabled\n"); + return (0); +} + +int watchdog_init (void) +{ + volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; + + regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ + + /* set timeout and enable watchdog */ + regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; + regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ + + puts ("WATCHDOG:enabled\n"); + return (0); +} +#endif /* #ifdef CONFIG_WATCHDOG */ + +#endif /* #ifdef CONFIG_M5272 */ + + +#ifdef CONFIG_M5282 +int checkcpu (void) +{ + puts ("CPU: MOTOROLA Coldfire MCF5282\n"); + return 0; +} + +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { + return 0; +}; +#endif + +#ifdef CONFIG_M5249 /* test-only: todo... */ +int checkcpu (void) +{ + char buf[32]; + + printf ("CPU: MOTOROLA Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); + return 0; +} + +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { + /* enable watchdog, set timeout to 0 and wait */ + mbar_writeByte(MCFSIM_SYPCR, 0xc0); + while (1); + + /* we don't return! */ + return 0; +}; +#endif diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c new file mode 100644 index 0000000..350c431 --- /dev/null +++ b/cpu/mcf52x2/cpu_init.c @@ -0,0 +1,252 @@ +/* + * (C) Copyright 2003 + * Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_M5272 +#include +#include +#endif + +#ifdef CONFIG_M5282 +#include +#include +#endif + +#ifdef CONFIG_M5249 +#include +#endif + +#if defined(CONFIG_M5272) +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f (void) +{ + /* if we come from RAM we assume the CPU is + * already initialized. + */ +#ifndef CONFIG_MONITOR_IS_IN_RAM + volatile immap_t *regp = (immap_t *)CFG_MBAR; + + volatile unsigned char *mbar; + mbar = (volatile unsigned char *) CFG_MBAR; + + regp->sysctrl_reg.sc_scr = CFG_SCR; + regp->sysctrl_reg.sc_spr = CFG_SPR; + + /* Setup Ports: */ + regp->gpio_reg.gpio_pacnt = CFG_PACNT; + regp->gpio_reg.gpio_paddr = CFG_PADDR; + regp->gpio_reg.gpio_padat = CFG_PADAT; + regp->gpio_reg.gpio_pbcnt = CFG_PBCNT; + regp->gpio_reg.gpio_pbddr = CFG_PBDDR; + regp->gpio_reg.gpio_pbdat = CFG_PBDAT; + regp->gpio_reg.gpio_pdcnt = CFG_PDCNT; + + /* Memory Controller: */ + regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM; + regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM; + +#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) + regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM; + regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM; +#endif + +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM; + regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM; +#endif + +#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) + regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM; + regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM; +#endif + +#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) + regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM; + regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM; +#endif + +#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) + regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM; + regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM; +#endif + +#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) + regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM; + regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM; +#endif + +#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) + regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM; + regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM; +#endif + +#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ + + /* enable instruction cache now */ + icache_enable(); + +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r (void) +{ + return (0); +} +#endif /* #if defined(CONFIG_M5272) */ + + +#ifdef CONFIG_M5282 +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f (void) +{ + +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r (void) +{ + return (0); +} +#endif + +#if defined(CONFIG_M5249) +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f (void) +{ +#ifndef CFG_PLL_BYPASS + /* + * Setup the PLL to run at the specified speed + * + */ + volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); + unsigned long pllcr; +#ifdef CFG_FAST_CLK + pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ +#else + pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ +#endif + cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ + pllcr ^= 0x00000001; /* Set pll bypass to 1 */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ + udelay(0x20); /* Wait for a lock ... */ +#endif /* #ifndef CFG_PLL_BYPASS */ + + /* + * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins + * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins + * which is their primary function. + * ~Jeremy + */ + mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); + mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); + mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN); + mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN); + mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT); + mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT); + + /* + * dBug Compliance: + * You can verify these values by using dBug's 'ird' + * (Internal Register Display) command + * ~Jeremy + * + */ + mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ + mbar_writeByte(MCFSIM_SYPCR, 0x00); + mbar_writeByte(MCFSIM_SWIVR, 0x0f); + mbar_writeByte(MCFSIM_SWSR, 0x00); + mbar_writeLong(MCFSIM_IMR, 0xfffffbff); + mbar_writeByte(MCFSIM_SWDICR, 0x00); + mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); + mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); + mbar_writeByte(MCFSIM_I2CICR, 0x00); + mbar_writeByte(MCFSIM_UART1ICR, 0x00); + mbar_writeByte(MCFSIM_UART2ICR, 0x00); + mbar_writeByte(MCFSIM_ICR6, 0x00); + mbar_writeByte(MCFSIM_ICR7, 0x00); + mbar_writeByte(MCFSIM_ICR8, 0x00); + mbar_writeByte(MCFSIM_ICR9, 0x00); + mbar_writeByte(MCFSIM_QSPIICR, 0x00); + + mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); + mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ + mbar2_writeByte(MCFSIM_SPURVEC, 0x00); + mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ + + /* Setup interrupt priorities for gpio7 */ + /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ + + /* IDE Config registers */ + mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); + mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); + + /* + * Setup chip selects... + */ + + mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); + mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); + mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); + + mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); + mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); + mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); + + /* enable instruction cache now */ + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r (void) +{ + return (0); +} +#endif /* #if defined(CONFIG_M5249) */ diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c new file mode 100644 index 0000000..a5c50af --- /dev/null +++ b/cpu/mcf52x2/fec.c @@ -0,0 +1,569 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_M5272 +#include +#include +#endif + +#ifdef CONFIG_M5282 +#include +#include +#endif + +#include +#include + +#ifdef CONFIG_M5272 +#define FEC_ADDR (CFG_MBAR + 0x840) +#endif +#ifdef CONFIG_M5282 +#define FEC_ADDR (CFG_MBAR + 0x1000) +#endif + +#undef ET_DEBUG +#undef MII_DEBUG + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) + +#ifdef CFG_DISCOVER_PHY +#include +static void mii_discover_phy (void); +#endif + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +#define TOUT_LOOP 100 + +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 + + +static char txbuf[DBUF_LENGTH]; + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * FEC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +typedef volatile struct CommonBufferDescriptor { + cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ + cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ +} RTXBD; + +static RTXBD *rtx = NULL; + +int eth_send (volatile void *packet, int length) +{ + int j, rc; + volatile fec_t *fecp = (fec_t *) (FEC_ADDR); + + /* section 16.9.23.3 + * Wait for ready + */ + j = 0; + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) + && (j < TOUT_LOOP)) { + udelay (1); + j++; + } + if (j >= TOUT_LOOP) { + printf ("TX not ready\n"); + } + + rtx->txbd[txIdx].cbd_bufaddr = (uint) packet; + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; + + /* Activate transmit Buffer Descriptor polling */ + fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ + + j = 0; + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) + && (j < TOUT_LOOP)) { + udelay (1); + j++; + } + if (j >= TOUT_LOOP) { + printf ("TX timeout\n"); + } +#ifdef ET_DEBUG + printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", + __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc, + (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2); +#endif + + /* return only status bits */ ; + rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); + + txIdx = (txIdx + 1) % TX_BUF_CNT; + + return rc; +} + +int eth_rx (void) +{ + int length; + volatile fec_t *fecp = (fec_t *) FEC_ADDR; + + for (;;) { + /* section 16.9.23.2 */ + if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = rtx->rxbd[rxIdx].cbd_datlen; + + if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { +#ifdef ET_DEBUG + printf ("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + rtx->rxbd[rxIdx].cbd_sc); +#endif + } else { + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[rxIdx], length - 4); + } + + /* Give the buffer back to the FEC. */ + rtx->rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx->rxbd[PKTBUFSRX - 1].cbd_sc = + (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } else { + rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + + /* Try to fill Buffer Descriptors */ + fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ + } + + return length; +} + +/************************************************************** + * + * FEC Ethernet Initialization Routine + * + *************************************************************/ +#define FEC_ECNTRL_ETHER_EN 0x00000002 +#define FEC_ECNTRL_RESET 0x00000001 + +#define FEC_RCNTRL_BC_REJ 0x00000010 +#define FEC_RCNTRL_PROM 0x00000008 +#define FEC_RCNTRL_MII_MODE 0x00000004 +#define FEC_RCNTRL_DRT 0x00000002 +#define FEC_RCNTRL_LOOP 0x00000001 + +#define FEC_TCNTRL_FDEN 0x00000004 +#define FEC_TCNTRL_HBC 0x00000002 +#define FEC_TCNTRL_GTS 0x00000001 + +#define FEC_RESET_DELAY 50000 + +int eth_init (bd_t * bd) +{ + + int i; + volatile fec_t *fecp = (fec_t *) (FEC_ADDR); + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + fecp->fec_ecntrl = FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { + printf ("FEC_RESET_DELAY timeout\n"); + return 0; + } + + /* We use strictly polling mode only + */ + fecp->fec_imask = 0; + + /* Clear any pending interrupt */ + fecp->fec_ievent = 0xffffffff; + + /* Set station address */ +#define ea bd->bi_enetaddr + fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | + (ea[2] << 8) | (ea[3]); + fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16); +#ifdef ET_DEBUG + printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", + ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); +#endif +#undef ea + + /* Clear multicast address hash table + */ + fecp->fec_hash_table_high = 0; + fecp->fec_hash_table_low = 0; + + /* Set maximum receive buffer size. + */ + fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; + + /* + * Setup Buffers and Buffer Desriptors + */ + rxIdx = 0; + txIdx = 0; + + if (!rtx) { + rtx = (RTXBD *) CFG_ENET_BD_BASE; + } + + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + for (i = 0; i < PKTBUFSRX; i++) { + rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx->rxbd[i].cbd_datlen = 0; /* Reset */ + rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Last, Tx CRC + */ + for (i = 0; i < TX_BUF_CNT; i++) { + rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; + rtx->txbd[i].cbd_datlen = 0; /* Reset */ + rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); + } + rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* Set receive and transmit descriptor base + */ + fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); + fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); + + /* Enable MII mode + */ +#if 0 /* Full duplex mode */ + fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; + fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; +#else /* Half duplex mode */ + fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; + fecp->fec_x_cntrl = 0; +#endif + /* Set MII speed */ + fecp->fec_mii_speed = 0x0e; + + /* Configure port B for MII. + */ + /* port initialization was already made in cpu_init_f() */ + + /* Now enable the transmit and receive processing + */ + fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; + +#ifdef CFG_DISCOVER_PHY + /* wait for the PHY to wake up after reset */ + mii_discover_phy (); +#endif + + /* And last, try to fill Rx Buffer Descriptors */ + fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ + + return 1; +} + +void eth_halt (void) +{ + volatile fec_t *fecp = (fec_t *) FEC_ADDR; + + fecp->fec_ecntrl = 0; +} + + +#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) + +static int phyaddr = -1; /* didn't find a PHY yet */ +static uint phytype; + +/* Make MII read/write commands for the FEC. +*/ + +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18) | \ + (VAL & 0xffff)) + +/* Interrupt events/masks. +*/ +#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ +#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ +#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ +#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ +#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ +#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ +#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ +#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ +#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ +#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ + +/* PHY identification + */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ + +/* send command to phy using mii, wait for result */ +static uint mii_send (uint mii_cmd) +{ + uint mii_reply; + volatile fec_t *ep = (fec_t *) (FEC_ADDR); + + ep->fec_mii_data = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */ + mii_reply = ep->fec_mii_data; /* result from phy */ + ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +static void mii_discover_phy (void) +{ +#define MAX_PHY_PASSES 11 + uint phyno; + int pass; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay (10000); /* wait 10ms */ + } + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf ("PHY type 0x%x pass %d type ", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= mii_send (mk_mii_read (phyno, + PHY_PHYIDR2)); + +#ifdef ET_DEBUG + printf ("PHY @ 0x%x pass %d type ", phyno, + pass); + switch (phytype & 0xfffffff0) { + case PHY_ID_LXT970: + printf ("LXT970\n"); + break; + case PHY_ID_LXT971: + printf ("LXT971\n"); + break; + case PHY_ID_82555: + printf ("82555\n"); + break; + case PHY_ID_QS6612: + printf ("QS6612\n"); + break; + case PHY_ID_AMD79C784: + printf ("AMD79C784\n"); + break; + case PHY_ID_LSI80225B: + printf ("LSI L80225/B\n"); + break; + default: + printf ("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) { + printf ("No PHY device found.\n"); + } +} +#endif /* CFG_DISCOVER_PHY */ + +#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) + +static int mii_init_done = 0; + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_init (void) +{ + volatile fec_t *fecp = (fec_t *) (FEC_ADDR); + + int i; + + if (mii_init_done != 0) { + return; + } + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + + fecp->fec_ecntrl = FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { + printf ("FEC_RESET_DELAY timeout\n"); + return; + } + + /* We use strictly polling mode only + */ + fecp->fec_imask = 0; + + /* Clear any pending interrupt + */ + fecp->fec_ievent = 0xffffffff; + + /* Set MII speed */ + fecp->fec_mii_speed = 0x0e; + + /* Configure port B for MII. + */ + /* port initialization was already made in cpu_init_f() */ + + /* Now enable the transmit and receive processing */ + fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; + + mii_init_done = 1; +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcf52x2_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send (mk_mii_read (addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf ("0x%04x\n", *value); +#endif + + return 0; +} + +int mcf52x2_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send (mk_mii_write (addr, reg, value)); + +#ifdef MII_DEBUG + printf ("0x%04x\n", value); +#endif + + return 0; +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */ +#endif /* CFG_CMD_NET, FEC_ENET */ + +int mcf52x2_miiphy_initialize(bd_t *bis) +{ +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) +#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) + miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write); +#endif +#endif + return 0; +} diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c new file mode 100644 index 0000000..868df39 --- /dev/null +++ b/cpu/mcf52x2/interrupts.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2003 Josef Baumgartner + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_M5272 +#include +#include +#endif + +#ifdef CONFIG_M5282 +#include +#include +#endif + +#ifdef CONFIG_M5249 +#include +#endif + + +#define NR_IRQS 31 + +/* + * Interrupt vector functions. + */ +struct interrupt_action { + interrupt_handler_t *handler; + void *arg; +}; + +static struct interrupt_action irq_vecs[NR_IRQS]; + +static __inline__ unsigned short get_sr (void) +{ + unsigned short sr; + + asm volatile ("move.w %%sr,%0":"=r" (sr):); + + return sr; +} + +static __inline__ void set_sr (unsigned short sr) +{ + asm volatile ("move.w %0,%%sr"::"r" (sr)); +} + +/************************************************************************/ +/* + * Install and free an interrupt handler + */ +void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) +{ +#ifdef CONFIG_M5272 + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); +#endif + int vec_base = 0; + +#ifdef CONFIG_M5272 + vec_base = intp->int_pivr & 0xe0; +#endif + + if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { + printf ("irq_install_handler: wrong interrupt vector %d\n", + vec); + return; + } + + irq_vecs[vec - vec_base].handler = handler; + irq_vecs[vec - vec_base].arg = arg; +} + +void irq_free_handler (int vec) +{ +#ifdef CONFIG_M5272 + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); +#endif + int vec_base = 0; + +#ifdef CONFIG_M5272 + vec_base = intp->int_pivr & 0xe0; +#endif + + if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { + return; + } + + irq_vecs[vec - vec_base].handler = NULL; + irq_vecs[vec - vec_base].arg = NULL; +} + +void enable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr & ~0x0700); +} + +int disable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr | 0x0700); + + return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */ +} + +void int_handler (struct pt_regs *fp) +{ +#ifdef CONFIG_M5272 + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); +#endif + int vec, vec_base = 0; + + vec = (fp->vector >> 2) & 0xff; +#ifdef CONFIG_M5272 + vec_base = intp->int_pivr & 0xe0; +#endif + + if (irq_vecs[vec - vec_base].handler != NULL) { + irq_vecs[vec - + vec_base].handler (irq_vecs[vec - vec_base].arg); + } else { + printf ("\nBogus External Interrupt Vector %d\n", vec); + } +} + + +#ifdef CONFIG_M5272 +int interrupt_init (void) +{ + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); + + /* disable all external interrupts */ + intp->int_icr1 = 0x88888888; + intp->int_icr2 = 0x88888888; + intp->int_icr3 = 0x88888888; + intp->int_icr4 = 0x88888888; + intp->int_pitr = 0x00000000; + /* initialize vector register */ + intp->int_pivr = 0x40; + + enable_interrupts (); + + return 0; +} +#endif + +#ifdef CONFIG_M5282 +int interrupt_init (void) +{ + return 0; +} +#endif + +#ifdef CONFIG_M5249 +int interrupt_init (void) +{ + enable_interrupts (); + + return 0; +} +#endif diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c new file mode 100644 index 0000000..c730922 --- /dev/null +++ b/cpu/mcf52x2/serial.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +#ifdef CONFIG_M5272 +#include +#endif + +#ifdef CONFIG_M5282 +#include +#endif + +#ifdef CONFIG_M5249 +#include +#endif + +#ifdef CONFIG_M5249 +#define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a)) +#else +#define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a)) +#endif + +void rs_serial_setbaudrate(int port,int baudrate) +{ +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) + volatile unsigned char *uartp; + double clock, fraction; + + if (port == 0) + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + else + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + + clock = DoubleClock(baudrate); /* Set baud above */ + + fraction = ((clock - (int)clock) * 16.0) + 0.5; + + uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ + uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ + uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ +#endif +}; + +void rs_serial_init(int port,int baudrate) +{ + volatile unsigned char *uartp; + + /* + * Reset UART, get it into known state... + */ + if (port == 0) + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + else + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ + + /* + * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity. + */ + uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8; + uartp[MCFUART_UMR] = MCFUART_MR2_STOP1; + + rs_serial_setbaudrate(port,baudrate); + + uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER; + uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE; + + return; +} + +/****************************************************************************/ +/* + * Output a single character, using UART polled mode. + * This is used for console output. + */ + +void rs_put_char(char ch) +{ + volatile unsigned char *uartp; + int i; + + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + + for (i = 0; (i < 0x10000); i++) { + if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY) + break; + } + uartp[MCFUART_UTB] = ch; + return; +} + +int rs_is_char(void) +{ + volatile unsigned char *uartp; + + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + return((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0); +} + +int rs_get_char(void) +{ + volatile unsigned char *uartp; + + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + return(uartp[MCFUART_URB]); +} + +void serial_setbrg(void) { + DECLARE_GLOBAL_DATA_PTR; + rs_serial_setbaudrate(0,gd->bd->bi_baudrate); +} + +int serial_init(void) { + DECLARE_GLOBAL_DATA_PTR; + rs_serial_init(0,gd->baudrate); + return 0; +} + + +void serial_putc(const char c) { + if (c == '\n') + serial_putc ('\r'); + rs_put_char(c); +} + +void serial_puts (const char *s) { + while (*s) { + serial_putc(*s++); + } +} + +int serial_getc(void) { + while(!rs_is_char()); + return rs_get_char(); +} + +int serial_tstc() { + return rs_is_char(); +} diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c new file mode 100644 index 0000000..519c992 --- /dev/null +++ b/cpu/mcf52x2/speed.c @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2003 + * Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->cpu_clk = CFG_CLK; +#ifdef CONFIG_M5249 + gd->bus_clk = gd->cpu_clk / 2; +#else + gd->bus_clk = gd->cpu_clk; +#endif + return (0); +} diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S new file mode 100644 index 0000000..b4926e2 --- /dev/null +++ b/cpu/mcf52x2/start.S @@ -0,0 +1,345 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + + +#define _START _start +#define _FAULT _fault + + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; \ + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte + +/* If we come from a pre-loader we don't need an initial exception + * table. + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +.long 0x00000000, _START +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +#endif + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr + + /* if we come from a pre-loader we have no exception table and + * therefore no VBR to set + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR +#endif + +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) + move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */ + move.c %d0, %MBAR + + /*** The 5249 has MBAR2 as well ***/ +#ifdef CFG_MBAR2 + move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */ + movec %d0, #0xc0e /* Set MBAR2 */ +#endif + + move.l #(CFG_INIT_RAM_ADDR + 1), %d0 + movec %d0, %RAMBAR0 +#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ + +#ifdef CONFIG_M5282 + /* Initialize IPSBAR */ + move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ + move.l %d0, 0x40000000 + + /* Initialize FLASHBAR: locate internal Flash and validate it */ + move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 + movec %d0, %RAMBAR0 + + /* Initialize RAMBAR1: locate SRAM and validate it */ + move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 + movec %d0, %RAMBAR1 +#endif + + /* invalidate and disable cache */ + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + + .globl _exc_handler +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ +#ifdef CONFIG_M5272 + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0x0000c000, %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + move.l #0xff00c000, %d0 /* Setup cache mask */ + movec %d0, %ACR1 /* Enable cache */ + move.l #0x80000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + moveq #1, %d0 + move.l %d0, icache_state + rts +#endif + +#ifdef CONFIG_M5282 + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0x0000c000, %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + move.l #0xff00c000, %d0 /* Setup cache mask */ + movec %d0, %ACR1 /* Enable cache */ + move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/ + movec %d0, %CACR /* Enable cache */ + moveq #1, %d0 + move.l %d0, icache_state + rts +#endif + +#ifdef CONFIG_M5249 + .globl icache_enable +icache_enable: + /* + * Note: The 5249 Documentation doesn't give a bit position for CINV! + * From the 5272 and the 5307 documentation, I have deduced that it is + * probably CACR[24]. Should someone say something to Motorola? + * ~Jeremy + */ + move.l #0x01000000, %d0 /* Invalidate whole cache */ + move.c %d0,%CACR + move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */ + move.c %d0, %ACR0 + move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */ + move.c %d0, %ACR1 + move.l #0x90000200, %d0 /* Set cache enable cmd */ + move.c %d0,%CACR + moveq #1, %d0 + move.l %d0, icache_state + rts +#endif + + .globl icache_disable +icache_disable: + move.l #0x00000100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + clr.l %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + movec %d0, %ACR1 /* Enable cache */ + moveq #0, %d0 + move.l %d0, icache_state + rts + + .globl icache_status +icache_status: + move.l icache_state, %d0 + rts + + .data +icache_state: + .long 1 + + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile new file mode 100644 index 0000000..610043e --- /dev/null +++ b/cpu/microblaze/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = cpu.o interrupts.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/microblaze/cpu.c b/cpu/microblaze/cpu.c new file mode 100644 index 0000000..4d2b270 --- /dev/null +++ b/cpu/microblaze/cpu.c @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* EMPTY FILE */ diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c new file mode 100644 index 0000000..ccf67e1 --- /dev/null +++ b/cpu/microblaze/interrupts.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +void enable_interrupts(void) +{ +} + +int disable_interrupts(void) +{ + return 0; +} diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S new file mode 100644 index 0000000..7efdbb0 --- /dev/null +++ b/cpu/microblaze/start.S @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + .text + .global _start +_start: + + addi r1, r0, CFG_SDRAM_BASE /* init stack pointer */ + addi r1, r1, CFG_SDRAM_SIZE /* set sp to high up */ + + brai board_init + +1: bri 1b diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile new file mode 100644 index 0000000..c8b30c7 --- /dev/null +++ b/cpu/mips/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \ + cpu.o interrupts.o incaip_clock.o +SOBJS = incaip_wdt.o cache.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c new file mode 100644 index 0000000..d95ec3f --- /dev/null +++ b/cpu/mips/asc_serial.c @@ -0,0 +1,371 @@ +/* + * (INCA) ASC UART support + */ + +#include + +#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP) + +#ifdef CONFIG_PURPLE +#define serial_init asc_serial_init +#define serial_putc asc_serial_putc +#define serial_puts asc_serial_puts +#define serial_getc asc_serial_getc +#define serial_tstc asc_serial_tstc +#define serial_setbrg asc_serial_setbrg +#endif + +#include +#include +#include "asc_serial.h" + +#ifdef CONFIG_PURPLE + +#undef ASC_FIFO_PRESENT +#define TOUT_LOOP 100000 + +/* Set base address for second FPI interrupt control register bank */ +#define SFPI_INTCON_BASEADDR 0xBF0F0000 + +/* Register offset from base address */ +#define FBS_ISR 0x00000000 /* Interrupt status register */ +#define FBS_IMR 0x00000008 /* Interrupt mask register */ +#define FBS_IDIS 0x00000010 /* Interrupt disable register */ + +/* Interrupt status register bits */ +#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */ +#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ +#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */ +#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */ +#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ +#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */ + +#else + +#define ASC_FIFO_PRESENT + +#endif + + +#define SET_BIT(reg, mask) reg |= (mask) +#define CLEAR_BIT(reg, mask) reg &= (~mask) +#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) +#define SET_BITS(reg, mask) SET_BIT(reg, mask) +#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} + +extern uint incaip_get_fpiclk(void); + +static int serial_setopt (void); + +/* pointer to ASC register base address */ +static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC; + +/****************************************************************************** +* +* serial_init - initialize a INCAASC channel +* +* This routine initializes the number of data bits, parity +* and set the selected baud rate. Interrupts are disabled. +* Set the modem control signals if the option is selected. +* +* RETURNS: N/A +*/ + +int serial_init (void) +{ +#ifdef CONFIG_INCA_IP + /* we have to set PMU.EN13 bit to enable an ASC device*/ + INCAASC_PMU_ENABLE(13); +#endif + + /* and we have to set CLC register*/ + CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); + SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); + + /* initialy we are in async mode */ + pAsc->asc_con = ASCCON_M_8ASYNC; + + /* select input port */ + pAsc->asc_pisel = (CONSOLE_TTY & 0x1); + +#ifdef ASC_FIFO_PRESENT + /* TXFIFO's filling level */ + SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, + ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL); + /* enable TXFIFO */ + SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN); + + /* RXFIFO's filling level */ + SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK, + ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL); + /* enable RXFIFO */ + SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); +#endif + + /* enable error signals */ + SET_BIT(pAsc->asc_con, ASCCON_FEN); + SET_BIT(pAsc->asc_con, ASCCON_OEN); + +#ifdef CONFIG_INCA_IP + /* acknowledge ASC interrupts */ + ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL); + + /* disable ASC interrupts */ + ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL); +#endif + +#ifdef ASC_FIFO_PRESENT + /* set FIFOs into the transparent mode */ + SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN); + SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN); +#endif + + /* set baud rate */ + serial_setbrg(); + + /* set the options */ + serial_setopt(); + + return 0; +} + +void serial_setbrg (void) +{ + ulong uiReloadValue, fdv; + ulong f_ASC; + +#ifdef CONFIG_INCA_IP + f_ASC = incaip_get_fpiclk(); +#else + f_ASC = ASC_CLOCK_RATE; +#endif + +#ifndef INCAASC_USE_FDV + fdv = 2; + uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; +#else + fdv = INCAASC_FDV_HIGH_BAUDRATE; + uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; +#endif /* INCAASC_USE_FDV */ + + if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) + { +#ifndef INCAASC_USE_FDV + fdv = 3; + uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; +#else + fdv = INCAASC_FDV_LOW_BAUDRATE; + uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; +#endif /* INCAASC_USE_FDV */ + + if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) + { + return; /* can't impossibly generate that baud rate */ + } + } + + /* Disable Baud Rate Generator; BG should only be written when R=0 */ + CLEAR_BIT(pAsc->asc_con, ASCCON_R); + +#ifndef INCAASC_USE_FDV + /* + * Disable Fractional Divider (FDE) + * Divide clock by reload-value + constant (BRS) + */ + /* FDE = 0 */ + CLEAR_BIT(pAsc->asc_con, ASCCON_FDE); + + if ( fdv == 2 ) + CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */ + else + SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */ + +#else /* INCAASC_USE_FDV */ + + /* Enable Fractional Divider */ + SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */ + + /* Set fractional divider value */ + pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK; + +#endif /* INCAASC_USE_FDV */ + + /* Set reload value in BG */ + pAsc->asc_bg = uiReloadValue; + + /* Enable Baud Rate Generator */ + SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */ +} + +/******************************************************************************* +* +* serial_setopt - set the serial options +* +* Set the channel operating mode to that specified. Following options +* are supported: CREAD, CSIZE, PARENB, and PARODD. +* +* Note, this routine disables the transmitter. The calling routine +* may have to re-enable it. +* +* RETURNS: +* Returns 0 to indicate success, otherwise -1 is returned +*/ + +static int serial_setopt (void) +{ + ulong con; + + switch ( ASC_OPTIONS & ASCOPT_CSIZE ) + { + /* 7-bit-data */ + case ASCOPT_CS7: + con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */ + break; + + /* 8-bit-data */ + case ASCOPT_CS8: + if ( ASC_OPTIONS & ASCOPT_PARENB ) + con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */ + else + con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */ + break; + + /* + * only 7 and 8-bit frames are supported + * if we don't use IOCTL extensions + */ + default: + return -1; + } + + if ( ASC_OPTIONS & ASCOPT_STOPB ) + SET_BIT(con, ASCCON_STP); /* 2 stop bits */ + else + CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */ + + if ( ASC_OPTIONS & ASCOPT_PARENB ) + SET_BIT(con, ASCCON_PEN); /* enable parity checking */ + else + CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */ + + if ( ASC_OPTIONS & ASCOPT_PARODD ) + SET_BIT(con, ASCCON_ODD); /* odd parity */ + else + CLEAR_BIT(con, ASCCON_ODD); /* even parity */ + + if ( ASC_OPTIONS & ASCOPT_CREAD ) + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */ + + pAsc->asc_con |= con; + + return 0; +} + +void serial_putc (const char c) +{ +#ifdef ASC_FIFO_PRESENT + uint txFl = 0; +#else + uint timeout = 0; +#endif + + if (c == '\n') serial_putc ('\r'); + +#ifdef ASC_FIFO_PRESENT + /* check do we have a free space in the TX FIFO */ + /* get current filling level */ + do + { + txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; + } + while ( txFl == INCAASC_TXFIFO_FULL ); +#else + + while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & + FBS_ISR_AB)) + { + if (timeout++ > TOUT_LOOP) + { + break; + } + } +#endif + + pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ + +#ifndef ASC_FIFO_PRESENT + *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB | + FBS_ISR_AT; +#endif + + /* check for errors */ + if ( pAsc->asc_con & ASCCON_OE ) + { + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); + return; + } +} + +void serial_puts (const char *s) +{ + while (*s) + { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + ulong symbol_mask; + char c; + + while (!serial_tstc()); + + symbol_mask = + ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff); + + c = (char)(pAsc->asc_rbuf & symbol_mask); + +#ifndef ASC_FIFO_PRESENT + *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR; +#endif + + return c; +} + +int serial_tstc (void) +{ + int res = 1; + +#ifdef ASC_FIFO_PRESENT + if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) + { + res = 0; + } +#else + if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & + FBS_ISR_AR)) + + { + res = 0; + } +#endif + else if ( pAsc->asc_con & ASCCON_FE ) + { + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); + res = 0; + } + else if ( pAsc->asc_con & ASCCON_PE ) + { + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE); + res = 0; + } + else if ( pAsc->asc_con & ASCCON_OE ) + { + SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); + res = 0; + } + + return res; +} +#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */ diff --git a/cpu/mips/asc_serial.h b/cpu/mips/asc_serial.h new file mode 100644 index 0000000..7ffdcfa --- /dev/null +++ b/cpu/mips/asc_serial.h @@ -0,0 +1,177 @@ +/* incaAscSio.h - (INCA) ASC UART tty driver header */ + +#ifndef __INCincaAscSioh +#define __INCincaAscSioh + +#include + +/* channel operating modes */ +#define ASCOPT_CSIZE 0x00000003 +#define ASCOPT_CS7 0x00000001 +#define ASCOPT_CS8 0x00000002 +#define ASCOPT_PARENB 0x00000004 +#define ASCOPT_STOPB 0x00000008 +#define ASCOPT_PARODD 0x00000010 +#define ASCOPT_CREAD 0x00000020 + +#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) + +/* ASC input select (0 or 1) */ +#define CONSOLE_TTY 0 + +/* use fractional divider for baudrate settings */ +#define INCAASC_USE_FDV + +#ifdef INCAASC_USE_FDV + #define INCAASC_FDV_LOW_BAUDRATE 71 + #define INCAASC_FDV_HIGH_BAUDRATE 453 +#endif /*INCAASC_USE_FDV*/ + + +#define INCAASC_TXFIFO_FL 1 +#define INCAASC_RXFIFO_FL 1 +#define INCAASC_TXFIFO_FULL 16 + +/* interrupt lines masks for the ASC device interrupts*/ +/* change these macroses if it's necessary */ +#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */ + +#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */ +#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */ +#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */ +#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/ + +/* interrupt controller access macros */ +#define ASC_INTERRUPTS_ENABLE(X) \ + *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X; +#define ASC_INTERRUPTS_DISABLE(X) \ + *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X; +#define ASC_INTERRUPTS_CLEAR(X) \ + *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X; + +/* CLC register's bits and bitfields */ +#define ASCCLC_DISR 0x00000001 +#define ASCCLC_DISS 0x00000002 +#define ASCCLC_RMCMASK 0x0000FF00 +#define ASCCLC_RMCOFFSET 8 + +/* CON register's bits and bitfields */ +#define ASCCON_MODEMASK 0x0007 + #define ASCCON_M_8SYNC 0x0 + #define ASCCON_M_8ASYNC 0x1 + #define ASCCON_M_8IRDAASYNC 0x2 + #define ASCCON_M_7ASYNCPAR 0x3 + #define ASCCON_M_9ASYNC 0x4 + #define ASCCON_M_8WAKEUPASYNC 0x5 + #define ASCCON_M_8ASYNCPAR 0x7 +#define ASCCON_STP 0x0008 +#define ASCCON_REN 0x0010 +#define ASCCON_PEN 0x0020 +#define ASCCON_FEN 0x0040 +#define ASCCON_OEN 0x0080 +#define ASCCON_PE 0x0100 +#define ASCCON_FE 0x0200 +#define ASCCON_OE 0x0400 +#define ASCCON_FDE 0x0800 +#define ASCCON_ODD 0x1000 +#define ASCCON_BRS 0x2000 +#define ASCCON_LB 0x4000 +#define ASCCON_R 0x8000 + +/* WHBCON register's bits and bitfields */ +#define ASCWHBCON_CLRREN 0x0010 +#define ASCWHBCON_SETREN 0x0020 +#define ASCWHBCON_CLRPE 0x0100 +#define ASCWHBCON_CLRFE 0x0200 +#define ASCWHBCON_CLROE 0x0400 +#define ASCWHBCON_SETPE 0x0800 +#define ASCWHBCON_SETFE 0x1000 +#define ASCWHBCON_SETOE 0x2000 + +/* ABCON register's bits and bitfields */ +#define ASCABCON_ABEN 0x0001 +#define ASCABCON_AUREN 0x0002 +#define ASCABCON_ABSTEN 0x0004 +#define ASCABCON_ABDETEN 0x0008 +#define ASCABCON_FCDETEN 0x0010 +#define ASCABCON_EMMASK 0x0300 + #define ASCABCON_EMOFF 8 + #define ASCABCON_EM_DISAB 0x0 + #define ASCABCON_EM_DURAB 0x1 + #define ASCABCON_EM_ALWAYS 0x2 +#define ASCABCON_TXINV 0x0400 +#define ASCABCON_RXINV 0x0800 + +/* FDV register mask, offset and bitfields*/ +#define ASCFDV_VALUE_MASK 0x000001FF + +/* WHBABCON register's bits and bitfields */ +#define ASCWHBABCON_SETABEN 0x0001 +#define ASCWHBABCON_CLRABEN 0x0002 + +/* ABSTAT register's bits and bitfields */ +#define ASCABSTAT_FCSDET 0x0001 +#define ASCABSTAT_FCCDET 0x0002 +#define ASCABSTAT_SCSDET 0x0004 +#define ASCABSTAT_SCCDET 0x0008 +#define ASCABSTAT_DETWAIT 0x0010 + +/* WHBABSTAT register's bits and bitfields */ +#define ASCWHBABSTAT_CLRFCSDET 0x0001 +#define ASCWHBABSTAT_SETFCSDET 0x0002 +#define ASCWHBABSTAT_CLRFCCDET 0x0004 +#define ASCWHBABSTAT_SETFCCDET 0x0008 +#define ASCWHBABSTAT_CLRSCSDET 0x0010 +#define ASCWHBABSTAT_SETSCSDET 0x0020 +#define ASCWHBABSTAT_SETSCCDET 0x0040 +#define ASCWHBABSTAT_CLRSCCDET 0x0080 +#define ASCWHBABSTAT_CLRDETWAIT 0x0100 +#define ASCWHBABSTAT_SETDETWAIT 0x0200 + +/* TXFCON register's bits and bitfields */ +#define ASCTXFCON_TXFEN 0x0001 +#define ASCTXFCON_TXFFLU 0x0002 +#define ASCTXFCON_TXTMEN 0x0004 +#define ASCTXFCON_TXFITLMASK 0x3F00 +#define ASCTXFCON_TXFITLOFF 8 + +/* RXFCON register's bits and bitfields */ +#define ASCRXFCON_RXFEN 0x0001 +#define ASCRXFCON_RXFFLU 0x0002 +#define ASCRXFCON_RXTMEN 0x0004 +#define ASCRXFCON_RXFITLMASK 0x3F00 +#define ASCRXFCON_RXFITLOFF 8 + +/* FSTAT register's bits and bitfields */ +#define ASCFSTAT_RXFFLMASK 0x003F +#define ASCFSTAT_TXFFLMASK 0x3F00 +#define ASCFSTAT_TXFFLOFF 8 + +#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT); + +typedef struct /* incaAsc_t */ +{ + volatile unsigned long asc_clc; /*0x0000*/ + volatile unsigned long asc_pisel; /*0x0004*/ + volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/ + volatile unsigned long asc_con; /*0x0010*/ + volatile unsigned long asc_bg; /*0x0014*/ + volatile unsigned long asc_fdv; /*0x0018*/ + volatile unsigned long asc_pmw; /* not used */ /*0x001C*/ + volatile unsigned long asc_tbuf; /*0x0020*/ + volatile unsigned long asc_rbuf; /*0x0024*/ + volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/ + volatile unsigned long asc_abcon; /*0x0030*/ + volatile unsigned long asc_abstat; /* not used */ /*0x0034*/ + volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/ + volatile unsigned long asc_rxfcon; /*0x0040*/ + volatile unsigned long asc_txfcon; /*0x0044*/ + volatile unsigned long asc_fstat; /*0x0048*/ + volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/ + volatile unsigned long asc_whbcon; /*0x0050*/ + volatile unsigned long asc_whbabcon; /*0x0054*/ + volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/ + +} incaAsc_t; + +#endif /* __INCincaAscSioh */ diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c new file mode 100644 index 0000000..9ce9b35 --- /dev/null +++ b/cpu/mips/au1x00_eth.c @@ -0,0 +1,307 @@ +/* Only eth0 supported for now + * + * (C) Copyright 2003 + * Thomas.Lange@corelatus.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CONFIG_AU1X00 + +#if defined(CFG_DISCOVER_PHY) +#error "PHY not supported yet" +/* We just assume that we are running 100FD for now */ +/* We all use switches, right? ;-) */ +#endif + +/* I assume ethernet behaves like au1000 */ + +#ifdef CONFIG_AU1000 +/* Base address differ between cpu:s */ +#define ETH0_BASE AU1000_ETH0_BASE +#define MAC0_ENABLE AU1000_MAC0_ENABLE +#else +#ifdef CONFIG_AU1100 +#define ETH0_BASE AU1100_ETH0_BASE +#define MAC0_ENABLE AU1100_MAC0_ENABLE +#else +#ifdef CONFIG_AU1500 +#define ETH0_BASE AU1500_ETH0_BASE +#define MAC0_ENABLE AU1500_MAC0_ENABLE +#else +#ifdef CONFIG_AU1550 +#define ETH0_BASE AU1550_ETH0_BASE +#define MAC0_ENABLE AU1550_MAC0_ENABLE +#else +#error "No valid cpu set" +#endif +#endif +#endif +#endif + +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_MII) +#include +#endif + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 +#define PKT_MAXBUF_SIZE 1518 + +static char txbuf[DBUF_LENGTH]; + +static int next_tx; +static int next_rx; + +/* 4 rx and 4 tx fifos */ +#define NO_OF_FIFOS 4 + +typedef struct{ + u32 status; + u32 addr; + u32 len; /* Only used for tx */ + u32 not_used; +} mac_fifo_t; + +mac_fifo_t mac_fifo[NO_OF_FIFOS]; + +#define MAX_WAIT 1000 + +static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){ + volatile mac_fifo_t *fifo_tx = + (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); + int i; + int res; + + /* tx fifo should always be idle */ + fifo_tx[next_tx].len = length; + fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE; + au_sync(); + + udelay(1); + i=0; + while(!(fifo_tx[next_tx].addr&TX_T_DONE)){ + if(i>MAX_WAIT){ + printf("TX timeout\n"); + break; + } + udelay(1); + i++; + } + + /* Clear done bit */ + fifo_tx[next_tx].addr = 0; + fifo_tx[next_tx].len = 0; + au_sync(); + + res = fifo_tx[next_tx].status; + + next_tx++; + if(next_tx>=NO_OF_FIFOS){ + next_tx=0; + } + return(res); +} + +static int au1x00_recv(struct eth_device* dev){ + volatile mac_fifo_t *fifo_rx = + (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); + + int length; + u32 status; + + for(;;){ + if(!(fifo_rx[next_rx].addr&RX_T_DONE)){ + /* Nothing has been received */ + return(-1); + } + + status = fifo_rx[next_rx].status; + + length = status&0x3FFF; + + if(status&RX_ERROR){ + printf("Rx error 0x%x\n", status); + } + else{ + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[next_rx], length - 4); + } + + fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE; + + next_rx++; + if(next_rx>=NO_OF_FIFOS){ + next_rx=0; + } + } /* for */ + + return(0); /* Does anyone use this? */ +} + +static int au1x00_init(struct eth_device* dev, bd_t * bd){ + + volatile u32 *macen = (volatile u32*)MAC0_ENABLE; + volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL); + volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH); + volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW); + volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH); + volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW); + volatile mac_fifo_t *fifo_tx = + (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); + volatile mac_fifo_t *fifo_rx = + (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); + int i; + + next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr); + next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr); + + /* We have to enable clocks before releasing reset */ + *macen = MAC_EN_CLOCK_ENABLE; + udelay(10); + + /* Enable MAC0 */ + /* We have to release reset before accessing registers */ + *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0| + MAC_EN_RESET1|MAC_EN_RESET2; + udelay(10); + + for(i=0;ienetaddr + *mac_addr_high = (ea[5] << 8) | (ea[4] ) ; + *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) | + (ea[1] << 8) | (ea[0] ) ; +#undef ea + *mac_mcast_low = 0; + *mac_mcast_high = 0; + + /* Make sure the MAC buffer is in the correct endian mode */ +#ifdef __LITTLE_ENDIAN + *mac_ctrl = MAC_FULL_DUPLEX; + udelay(1); + *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE; +#else + *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX; + udelay(1); + *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE; +#endif + + return(1); +} + +static void au1x00_halt(struct eth_device* dev){ +} + +int au1x00_enet_initialize(bd_t *bis){ + struct eth_device* dev; + + dev = (struct eth_device*) malloc(sizeof *dev); + memset(dev, 0, sizeof *dev); + + sprintf(dev->name, "Au1X00 ETHERNET"); + dev->iobase = 0; + dev->priv = 0; + dev->init = au1x00_init; + dev->halt = au1x00_halt; + dev->send = au1x00_send; + dev->recv = au1x00_recv; + + eth_register(dev); + +#if (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register(dev->name, + au1x00_miiphy_read, au1x00_miiphy_write); +#endif + + return 1; +} + +#if (CONFIG_COMMANDS & CFG_CMD_MII) +int au1x00_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short * value) +{ + volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); + volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); + u32 mii_control; + unsigned int timedout = 20; + + while (*mii_control_reg & MAC_MII_BUSY) { + udelay(1000); + if (--timedout == 0) { + printf("au1x00_eth: miiphy_read busy timeout!!\n"); + return -1; + } + } + + mii_control = MAC_SET_MII_SELECT_REG(reg) | + MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ; + + *mii_control_reg = mii_control; + + timedout = 20; + while (*mii_control_reg & MAC_MII_BUSY) { + udelay(1000); + if (--timedout == 0) { + printf("au1x00_eth: miiphy_read busy timeout!!\n"); + return -1; + } + } + *value = *mii_data_reg; + return 0; +} + +int au1x00_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); + volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); + u32 mii_control; + unsigned int timedout = 20; + + while (*mii_control_reg & MAC_MII_BUSY) { + udelay(1000); + if (--timedout == 0) { + printf("au1x00_eth: miiphy_write busy timeout!!\n"); + return; + } + } + + mii_control = MAC_SET_MII_SELECT_REG(reg) | + MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE; + + *mii_data_reg = value; + *mii_control_reg = mii_control; + return 0; +} +#endif /* CONFIG_COMMANDS & CFG_CMD_MII */ + +#endif /* CONFIG_AU1X00 */ diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c new file mode 100644 index 0000000..42c668e --- /dev/null +++ b/cpu/mips/au1x00_serial.c @@ -0,0 +1,135 @@ +/* + * AU1X00 UART support + * + * Hardcoded to UART 0 for now + * Speed and options also hardcoded to 115200 8N1 + * + * Copyright (c) 2003 Thomas.Lange@corelatus.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_AU1X00 + +#include +#include + +/****************************************************************************** +* +* serial_init - initialize a channel +* +* This routine initializes the number of data bits, parity +* and set the selected baud rate. Interrupts are disabled. +* Set the modem control signals if the option is selected. +* +* RETURNS: N/A +*/ + +int serial_init (void) +{ + volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR); + volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE); + + /* Enable clocks first */ + *uart_enable = UART_EN_CE; + + /* Then release reset */ + /* Must release reset before setting other regs */ + *uart_enable = UART_EN_CE|UART_EN_E; + + /* Activate fifos, reset tx and rx */ + /* Set tx trigger level to 12 */ + *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR| + UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12; + + serial_setbrg(); + + return 0; +} + + +void serial_setbrg (void) +{ + volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK); + volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR); + volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL; + int sd; + int divisorx2; + + /* sd is system clock divisor */ + /* see section 10.4.5 in au1550 datasheet */ + sd = (*sys_powerctrl & 0x03) + 2; + + /* calulate 2x baudrate and round */ + divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE))); + + if (divisorx2 & 0x01) + divisorx2 = divisorx2 + 1; + + *uart_clk = divisorx2 / 2; + + /* Set parity, stop bits and word length to 8N1 */ + *uart_lcr = UART_LCR_WLEN8; +} + +void serial_putc (const char c) +{ + volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); + volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX); + + if (c == '\n') serial_putc ('\r'); + + /* Wait for fifo to shift out some bytes */ + while((*uart_lsr&UART_LSR_THRE)==0); + + *uart_tx = (u32)c; +} + +void serial_puts (const char *s) +{ + while (*s) + { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX); + char c; + + while (!serial_tstc()); + + c = (*uart_rx&0xFF); + return c; +} + +int serial_tstc (void) +{ + volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); + + if(*uart_lsr&UART_LSR_DR){ + /* Data in rfifo */ + return(1); + } + return 0; +} +#endif /* CONFIG_SERIAL_AU1X00 */ diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c new file mode 100644 index 0000000..dbf72dc --- /dev/null +++ b/cpu/mips/au1x00_usb_ohci.c @@ -0,0 +1,1727 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: Part of this code has been derived from linux + * + */ +/* + * IMPORTANT NOTES + * 1 - you MUST define LITTLEENDIAN in the configuration file for the + * board or this driver will NOT work! + * 2 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + */ + +#include + +#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI) + +/* #include no PCI on the AU1x00 */ + +#include +#include +#include +#include +#include +#include "au1x00_usb_ohci.h" + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#define OHCI_VERBOSE_DEBUG /* not always helpful */ +#define OHCI_FILL_TRACE + +#define USBH_ENABLE_BE (1<<0) +#define USBH_ENABLE_C (1<<1) +#define USBH_ENABLE_E (1<<2) +#define USBH_ENABLE_CE (1<<3) +#define USBH_ENABLE_RD (1<<4) + +#ifdef LITTLEENDIAN +#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) +#else +#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE) +#endif + + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +#undef readl +#undef writel + +#define readl(a) au_readl((long)(a)) +#define writel(v,a) au_writel((v),(int)(a)) + +#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +#define DEBUG +#ifdef DEBUG +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#define SHOW_INFO +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) swap_16(x) +#define m32_swap(x) swap_32(x) + +/* global ohci_t */ +static ohci_t gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +urb_priv_t urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + +static u32 roothub_a (struct ohci *hc) + { return read_roothub (hc, a, 0xfc0fe000); } +static inline u32 roothub_b (struct ohci *hc) + { return readl (&hc->regs->roothub.b); } +static inline u32 roothub_status (struct ohci *hc) + { return readl (&hc->regs->roothub.status); } +static u32 roothub_portstatus (struct ohci *hc, int i) + { return read_roothub (hc, portstatus [i], 0xffe0fce0); } + + +/* forward declaration */ +static int hc_interrupt (void); +static void +td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv (urb_priv_t * urb) +{ + int i; + int last; + struct td * td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +static int sohci_get_current_frame_number (struct usb_device * dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, char * str, int small) +{ + urb_priv_t * purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number (dev), + usb_pipedevice (pipe), + usb_pipeendpoint (pipe), + usb_pipeout (pipe)? 'O': 'I', + usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): + (usb_pipecontrol (pipe)? "CTRL": "BULK"), + purb->actual_length, + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol (pipe)) { + printf (__FILE__ ": cmd(8):"); + for (i = 0; i < 8 ; i++) + printf (" %02x", ((__u8 *) setup) [i]); + printf ("\n"); + } + if (transfer_len > 0 && buffer) { + printf (__FILE__ ": data(%d/%d):", + purb->actual_length, + transfer_len); + len = usb_pipeout (pipe)? + transfer_len: purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf (" %02x", ((__u8 *) buffer) [i]); + printf ("%s\n", i < len? "...": ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ +void ep_print_int_eds (ohci_t *ohci, char * str) { + int i, j; + __u32 * ed_p; + for (i= 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table [i]); + if (*ed_p == 0) + continue; + printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + ed_t *ed = (ed_t *)m32_swap(ed_p); + printf (" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf ("\n"); + } +} + +static void ohci_dump_intr_mask (char *label, __u32 mask) +{ + dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds (char *label, __u32 value) +{ + ed_t *edp = (ed_t *)value; + + if (value) { + dbg ("%s %08x", label, value); + dbg ("%08x", edp->hwINFO); + dbg ("%08x", edp->hwTailP); + dbg ("%08x", edp->hwHeadP); + dbg ("%08x", edp->hwNextED); + } +} + +static char * hcfs2string (int state) +{ + switch (state) { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status (ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl (®s->revision) & 0xff; + if (temp != 0x10) + dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl (®s->control); + dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string (temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + + temp = readl (®s->cmdstatus); + dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + + ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); + ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); + + maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); + + maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); + maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); + + maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); + maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); + + maybe_print_eds ("donehead", readl (®s->donehead)); +} + +static void ohci_dump_roothub (ohci_t *controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + + if (verbose) { + dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b (controller); + dbg ("roothub.b: %08x PPCM=%04x DR=%04x", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status (controller); + dbg ("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump (ohci_t *controller, int verbose) +{ + dbg ("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status (controller); + if (verbose) + ep_print_int_eds (controller, "hcca"); + dbg ("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub (controller, 1); +} + + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + ohci_t *ohci; + ed_t * ed; + urb_priv_t *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* every endpoint has a ed, locate and fill it */ + if (!(ed = ep_add_ed (dev, pipe))) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype (pipe)) { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0)? 2: + (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc (dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv (purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv (purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link (ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number (struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + + return m16_swap (ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel ((long)ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel ((long)ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink (ohci_t *ohci, ed_t *ed) +{ + ed->hwINFO |= m32_swap (OHCI_ED_SKIP); + + switch (ed->type) { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_controltail == ed) { + ohci->ed_controltail = ed->ed_prev; + } else { + ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_bulktail == ed) { + ohci->ed_bulktail = ed->ed_prev; + } else { + ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + } + ed->state = ED_UNLINK; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, + * but the USB stack is a little bit stateless so we do it at every transaction + * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK + * in all other cases the state is left unchanged + * the ed info fields are setted anyway even though most of them should not change */ + +static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | + (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc (usb_dev); + ed->hwTailP = m32_swap (td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype (pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = m32_swap (usb_pipedevice (pipe) + | usb_pipeendpoint (pipe) << 7 + | (usb_pipeisoc (pipe)? 0x8000: 0) + | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) + | usb_pipeslow (pipe) << 13 + | usb_maxpacket (usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill (ohci_t *ohci, unsigned int info, + void *data, int len, + struct usb_device *dev, int index, urb_priv_t *urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td [index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32)data; +#ifdef OHCI_FILL_TRACE + if (1 || ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe))) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]); + } +#endif + if (!len) + data = 0; + + td->hwINFO = m32_swap (info); + td->hwCBP = m32_swap (data); + if (data) + td->hwBE = m32_swap (data + len - 1); + else + td->hwBE = 0; + td->hwNextTD = m32_swap (td_pt); + td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ + +#define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000)) + +static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ + if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + urb->td_cnt = 0; + if (data_len) + data = kseg_to_phys(buffer); + else + data = 0; + + switch (usb_pipetype (pipe)) { + case PIPE_BULK: + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while(data_len > 4096) { + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout (pipe)? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill (ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill (ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(td_t * td) +{ + __u32 tdINFO, tdBE, tdCBP; + urb_priv_t *lurb_priv = &urb_priv; + + tdINFO = m32_swap (td->hwINFO); + tdBE = m32_swap (td->hwBE); + tdCBP = m32_swap (td->hwCBP); + + + if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && + ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { + if (tdBE != 0) { + if (td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ + +static td_t * dl_reverse_done_list (ohci_t *ohci) +{ + __u32 td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + urb_priv_t *lurb_priv = NULL; + + td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; + ohci->hcca->done_head = 0; + + while (td_list_hc) { + td_list = (td_t *)td_list_hc; + + if (TD_CC_GET (m32_swap (td_list->hwINFO))) { + lurb_priv = &urb_priv; + dbg(" USB-error/status: %x : %p", + TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); + if (td_list->ed->hwHeadP & m32_swap (0x1)) { + if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { + td_list->ed->hwHeadP = + (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | + (td_list->ed->hwHeadP & m32_swap (0x2)); + lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; + } else + td_list->ed->hwHeadP &= m32_swap (0xfffffff2); + } + } + + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; + } + return td_list; +} + +/*-------------------------------------------------------------------------*/ + +/* td done list */ +static int dl_done_list (ohci_t *ohci, td_t *td_list) +{ + td_t *td_list_next = NULL; + ed_t *ed; + int cc = 0; + int stat = 0; + /* urb_t *urb; */ + urb_priv_t *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + + while (td_list) { + td_list_next = td_list->next_dl_td; + + lurb_priv = &urb_priv; + tdINFO = m32_swap (td_list->hwINFO); + + ed = td_list->ed; + + dl_transfer_length(td_list); + + /* error code of transfer */ + cc = TD_CC_GET (tdINFO); + if (cc != 0) { + dbg("ConditionCode %#x", cc); + stat = cc_to_error[cc]; + } + + if (ed->state != ED_NEW) { + edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; + edTailP = m32_swap (ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink (ohci, ed); + } + + td_list = td_list_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + __u32 temp, ndp, i; + int res; + + res = -1; + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && + ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + void * data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u32 datab[4]; + __u8 *data_buf = (__u8 *)datab; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + +#ifdef DEBUG +urb_priv.actual_length = 0; +pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = m16_swap (cmd->value); + wIndex = m16_swap (cmd->index); + wLength = m16_swap (cmd->length); + + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(__u16 *) data_buf = m16_swap (1); OK (2); + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_CLASS: + *(__u32 *) data_buf = m32_swap ( + RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK (4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + OK(0); + case (RH_C_HUB_OVER_CURRENT): + WR_RH_STAT(RH_HS_OCIC); OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_POCI); OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); + case (RH_C_PORT_CONNECTION): + WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); + case (RH_C_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_PESC); OK (0); + case (RH_C_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); + case (RH_C_PORT_OVER_CURRENT): + WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); + case (RH_C_PORT_RESET): + WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); + case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PRS); + OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PES ); + OK (0); + } + break; + + case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; OK(len); + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; OK(len); + case (0x03): /* string descriptors */ + if(wValue==0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if(wValue==0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a (&gohci); + + data_buf [0] = 9; /* min length; */ + data_buf [1] = 0x29; + data_buf [2] = temp & RH_A_NDP; + data_buf [3] = 0; + if (temp & RH_A_PSM) /* per-port power switching? */ + data_buf [3] |= 0x1; + if (temp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf [3] |= 0x10; + else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + data_buf [3] |= 0x8; + + /* corresponds to data_buf[4-7] */ + datab [1] = 0; + data_buf [5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b (&gohci); + data_buf [7] = temp & RH_B_DR; + if (data_buf [2] < 7) { + data_buf [8] = 0xff; + } else { + data_buf [0] += 2; + data_buf [8] = (temp & RH_B_DR) >> 8; + data_buf [10] = data_buf [9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf [0], wLength)); + OK (len); + } + + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); + + case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); + + default: + dbg ("unsupported root hub command"); + stat = USB_ST_STALLED; + } + +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#else + wait_ms(1); +#endif + + len = min_t(int, len, leni); + if (data != data_buf) + memcpy (data, data_buf, len); + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG + if (transfer_len) + urb_priv.actual_length = transfer_len; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); +#else + wait_ms(1); +#endif + + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if (!maxsize) { + err("submit_common_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { + err("sohci_submit_job failed"); + return -1; + } + + wait_ms(10); + /* ohci_dump_status(&gohci); */ + + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if (usb_pipetype (pipe) == PIPE_BULK) + timeout = BULK_TO; + else + timeout = 100; + + timeout *= 4; + /* wait for it to complete */ + for (;;) { + /* check whether the controller is done */ + stat = hc_interrupt(); + if (stat < 0) { + stat = USB_ST_CRC_ERR; + break; + } + if (stat >= 0 && stat != 0xff) { + /* 0xff is returned for an SF-interrupt */ + break; + } + if (--timeout) { + udelay(250); /* wait_ms(1); */ + } else { + err("CTL:TIMEOUT "); + stat = USB_ST_CRC_ERR; + break; + } + } + /* we got an Root Hub Status Change interrupt */ + if (got_rhsc) { +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + got_rhsc = 0; + /* abuse timeout */ + timeout = rh_check_port_status(&gohci); + if (timeout >= 0) { +#if 0 /* this does nothing useful, but leave it here in case that changes */ + /* the called routine adds 1 to the passed value */ + usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); +#endif + /* + * XXX + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } + + dev->status = stat; + dev->act_len = transfer_len; + +#ifdef DEBUG + pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + + /* free TDs in urb_priv */ + urb_free_priv (&urb_priv); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + + info("submit_control_msg"); +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if (!maxsize) { + err("submit_control_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset (ohci_t *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ + writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ + info("USB HC TakeOver from SMM"); + while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { + wait_ms (10); + if (--smm_timeout == 0) { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", + ohci->slot_name, + readl (&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + writel (0, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel (OHCI_HCR, &ohci->regs->cmdstatus); + while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { + if (--timeout == 0) { + err("USB HC reset timed out!"); + return -1; + } + udelay (1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start (ohci_t * ohci) +{ + __u32 mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + + writel (0, &ohci->regs->ed_controlhead); + writel (0, &ohci->regs->ed_bulkhead); + + writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + + fminterval = 0x2edf; + writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel (fminterval, &ohci->regs->fminterval); + writel (0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel (mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel (mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel (mask, &ohci->regs->intrenable); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, + &ohci->regs->roothub.a); + writel (RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay ((roothub_a (ohci) >> 23) & 0x1fe); + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static int +hc_interrupt (void) +{ + ohci_t *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { + ints = OHCI_INTR_WDH; + } else { + ints = readl (®s->intrstatus); + } + + /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ + + if (ints & OHCI_INTR_RHSC) { + got_rhsc = 1; + } + + if (ints & OHCI_INTR_UE) { + ohci->disabled++; + err ("OHCI Unrecoverable Error, controller usb-%s disabled", + ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ + +#ifdef DEBUG + ohci_dump (ohci, 1); +#else + wait_ms(1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset (ohci); + return -1; + } + + if (ints & OHCI_INTR_WDH) { + wait_ms(1); + writel (OHCI_INTR_WDH, ®s->intrdisable); + stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); + writel (OHCI_INTR_WDH, ®s->intrenable); + } + + if (ints & OHCI_INTR_SO) { + dbg("USB Schedule overrun\n"); + writel (OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) { + unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; + wait_ms(1); + writel (OHCI_INTR_SF, ®s->intrdisable); + if (ohci->ed_rm_list[frame] != NULL) + writel (OHCI_INTR_SF, ®s->intrenable); + stat = 0xff; + } + + writel (ints, ®s->intrstatus); + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci (ohci_t *ohci) +{ + dbg ("USB HC release ohci usb-%s", ohci->slot_name); + + if (!ohci->disabled) + hc_reset (ohci); +} + +/*-------------------------------------------------------------------------*/ + +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define read_c0_prid() __read_32bit_c0_register($15, 0) + +/* + * low level initalisation routine, called from usb.c + */ +static char ohci_inited = 0; + +int usb_lowlevel_init(void) +{ + u32 pin_func; + u32 sys_freqctrl, sys_clksrc; + u32 prid = read_c0_prid(); + + dbg("in usb_lowlevel_init\n"); + + /* zero and disable FREQ2 */ + sys_freqctrl = au_readl(SYS_FREQCTRL0); + sys_freqctrl &= ~0xFFF00000; + au_writel(sys_freqctrl, SYS_FREQCTRL0); + + /* zero and disable USBH/USBD clocks */ + sys_clksrc = au_readl(SYS_CLKSRC); + sys_clksrc &= ~0x00007FE0; + au_writel(sys_clksrc, SYS_CLKSRC); + + sys_freqctrl = au_readl(SYS_FREQCTRL0); + sys_freqctrl &= ~0xFFF00000; + + sys_clksrc = au_readl(SYS_CLKSRC); + sys_clksrc &= ~0x00007FE0; + + switch (prid & 0x000000FF) { + case 0x00: /* DA */ + case 0x01: /* HA */ + case 0x02: /* HB */ + /* CPU core freq to 48MHz to slow it way down... */ + au_writel(4, SYS_CPUPLL); + + /* + * Setup 48MHz FREQ2 from CPUPLL for USB Host + */ + /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */ + sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20)); + au_writel(sys_freqctrl, SYS_FREQCTRL0); + + /* CPU core freq to 384MHz */ + au_writel(0x20, SYS_CPUPLL); + + printf("Au1000: 48MHz OHCI workaround enabled\n"); + break; + + default: /* HC and newer */ + /* FREQ2 = aux/2 = 48 MHz */ + sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); + au_writel(sys_freqctrl, SYS_FREQCTRL0); + break; + } + + /* + * Route 48MHz FREQ2 into USB Host and/or Device + */ + sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); + au_writel(sys_clksrc, SYS_CLKSRC); + + /* configure pins GPIO[14:9] as GPIO */ + pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080); + + au_writel(pin_func, SYS_PINFUNC); + au_writel(0x2800, SYS_TRIOUTCLR); + au_writel(0x0030, SYS_OUTPUTCLR); + + dbg("OHCI board setup complete\n"); + + /* enable host controller */ + au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); + udelay(1000); + au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG); + udelay(1000); + + /* wait for reset complete (read register twice; see au1500 errata) */ + while (au_readl(USB_HOST_CONFIG), + !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) + udelay(1000); + + dbg("OHCI clock running\n"); + + memset (&gohci, 0, sizeof (ohci_t)); + memset (&urb_priv, 0, sizeof (urb_priv_t)); + + /* align the storage */ + if ((__u32)&ghcca[0] & 0xff) { + err("HCCA not aligned!!"); + return -1; + } + phcca = &ghcca[0]; + info("aligned ghcca %p", phcca); + memset(&ohci_dev, 0, sizeof(struct ohci_device)); + if ((__u32)&ohci_dev.ed[0] & 0x7) { + err("EDs not aligned!!"); + return -1; + } + memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); + if ((__u32)gtd & 0x7) { + err("TDs not aligned!!"); + return -1; + } + ptd = gtd; + gohci.hcca = phcca; + memset (phcca, 0, sizeof (struct ohci_hcca)); + + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000); + + gohci.flags = 0; + gohci.slot_name = "au1x00"; + + dbg("OHCI revision: 0x%08x\n" + " RH: a: 0x%08x b: 0x%08x\n", + readl(&gohci.regs->revision), + readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b)); + + if (hc_reset (&gohci) < 0) + goto errout; + + /* FIXME this is a second HC reset; why?? */ + writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); + wait_ms (10); + + if (hc_start (&gohci) < 0) + goto errout; + +#ifdef DEBUG + ohci_dump (&gohci, 1); +#else + wait_ms(1); +#endif + ohci_inited = 1; + return 0; + + errout: + err("OHCI initialization error\n"); + hc_release_ohci (&gohci); + /* Initialization failed */ + au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); + return -1; +} + +int usb_lowlevel_stop(void) +{ + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if (!ohci_inited) + return 0; + /* TODO release any interrupts, etc. */ + /* call hc_release_ohci() here ? */ + hc_reset (&gohci); + /* may not want to do this */ + /* Disable clock */ + au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); + return 0; +} + +#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/mips/au1x00_usb_ohci.h b/cpu/mips/au1x00_usb_ohci.h new file mode 100644 index 0000000..4ef06ff --- /dev/null +++ b/cpu/mips/au1x00_usb_ohci.h @@ -0,0 +1,416 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +/* ED States */ + +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute((aligned(16))); +typedef struct ed ed_t; + + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u16 hwPSW[MAXPSW]; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute((aligned(256))); + + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute((aligned(32))); + + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct +{ + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + + +typedef struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma;*/ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +td_t gtd[NUM_TD+1]; +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td * +td_alloc (struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) { + if (ptd[i].usb_dev == NULL) { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + return td; +} + +static inline void +ed_free (struct ed *ed) +{ + ed->usb_dev = NULL; +} diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S new file mode 100644 index 0000000..aad76e0 --- /dev/null +++ b/cpu/mips/cache.S @@ -0,0 +1,269 @@ +/* + * Cache-handling routined for MIPS 4K CPUs + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include + + + /* 16KB is the maximum size of instruction and data caches on + * MIPS 4K. + */ +#define MIPS_MAX_CACHE_SIZE 0x4000 + + +/* + * cacheop macro to automate cache operations + * first some helpers... + */ +#define _mincache(size, maxsize) \ + bltu size,maxsize,9f ; \ + move size,maxsize ; \ +9: + +#define _align(minaddr, maxaddr, linesize) \ + .set noat ; \ + subu AT,linesize,1 ; \ + not AT ; \ + and minaddr,AT ; \ + addu maxaddr,-1 ; \ + and maxaddr,AT ; \ + .set at + +/* general operations */ +#define doop1(op1) \ + cache op1,0(a0) +#define doop2(op1, op2) \ + cache op1,0(a0) ; \ + nop ; \ + cache op2,0(a0) + +/* specials for cache initialisation */ +#define doop1lw(op1) \ + lw zero,0(a0) +#define doop1lw1(op1) \ + cache op1,0(a0) ; \ + lw zero,0(a0) ; \ + cache op1,0(a0) +#define doop121(op1,op2) \ + cache op1,0(a0) ; \ + nop; \ + cache op2,0(a0) ; \ + nop; \ + cache op1,0(a0) + +#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \ + .set noreorder ; \ +10: doop##tag##ops ; \ + bne minaddr,maxaddr,10b ; \ + add minaddr,linesize ; \ + .set reorder + +/* finally the cache operation macros */ +#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ + blez n,11f ; \ + addu n,kva ; \ + _align(kva, n, cacheLineSize) ; \ + _oploopn(kva, n, cacheLineSize, tag, ops) ; \ +11: + +#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ + _mincache(n, cacheSize); \ + blez n,11f ; \ + addu n,kva ; \ + _align(kva, n, cacheLineSize) ; \ + _oploopn(kva, n, cacheLineSize, tag, ops) ; \ +11: + +#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ + vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) + +#define icacheop(kva, n, cacheSize, cacheLineSize, op) \ + icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) + +/******************************************************************************* +* +* mips_cache_reset - low level initialisation of the primary caches +* +* This routine initialises the primary caches to ensure that they +* have good parity. It must be called by the ROM before any cached locations +* are used to prevent the possibility of data with bad parity being written to +* memory. +* To initialise the instruction cache it is essential that a source of data +* with good parity is available. This routine +* will initialise an area of memory starting at location zero to be used as +* a source of parity. +* +* RETURNS: N/A +* +*/ + .globl mips_cache_reset + .ent mips_cache_reset +mips_cache_reset: + + li t2, CFG_ICACHE_SIZE + li t3, CFG_DCACHE_SIZE + li t4, CFG_CACHELINE_SIZE + move t5, t4 + + + li v0, MIPS_MAX_CACHE_SIZE + + /* Now clear that much memory starting from zero. + */ + + li a0, KSEG1 + addu a1, a0, v0 + +2: sw zero, 0(a0) + sw zero, 4(a0) + sw zero, 8(a0) + sw zero, 12(a0) + sw zero, 16(a0) + sw zero, 20(a0) + sw zero, 24(a0) + sw zero, 28(a0) + addu a0, 32 + bltu a0, a1, 2b + + /* Set invalid tag. + */ + + mtc0 zero, CP0_TAGLO + + /* + * The caches are probably in an indeterminate state, + * so we force good parity into them by doing an + * invalidate, load/fill, invalidate for each line. + */ + + /* Assume bottom of RAM will generate good parity for the cache. + */ + + li a0, K0BASE + move a2, t2 # icacheSize + move a3, t4 # icacheLineSize + move a1, a2 + icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) + + /* To support Orion/R4600, we initialise the data cache in 3 passes. + */ + + /* 1: initialise dcache tags. + */ + + li a0, K0BASE + move a2, t3 # dcacheSize + move a3, t5 # dcacheLineSize + move a1, a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + /* 2: fill dcache. + */ + + li a0, K0BASE + move a2, t3 # dcacheSize + move a3, t5 # dcacheLineSize + move a1, a2 + icacheopn(a0,a1,a2,a3,1lw,(dummy)) + + /* 3: clear dcache tags. + */ + + li a0, K0BASE + move a2, t3 # dcacheSize + move a3, t5 # dcacheLineSize + move a1, a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + j ra + .end mips_cache_reset + + +/******************************************************************************* +* +* dcache_status - get cache status +* +* RETURNS: 0 - cache disabled; 1 - cache enabled +* +*/ + .globl dcache_status + .ent dcache_status +dcache_status: + + mfc0 v0, CP0_CONFIG + andi v0, v0, 1 + j ra + + .end dcache_status + +/******************************************************************************* +* +* dcache_disable - disable cache +* +* RETURNS: N/A +* +*/ + .globl dcache_disable + .ent dcache_disable +dcache_disable: + + mfc0 t0, CP0_CONFIG + li t1, -8 + and t0, t0, t1 + ori t0, t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + j ra + + .end dcache_disable + + +/******************************************************************************* +* +* mips_cache_lock - lock RAM area pointed to by a0 in cache. +* +* RETURNS: N/A +* +*/ +#if defined(CONFIG_PURPLE) +# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2) +#else +# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE) +#endif + .globl mips_cache_lock + .ent mips_cache_lock +mips_cache_lock: + li a1, K0BASE - CACHE_LOCK_SIZE + addu a0, a1 + li a2, CACHE_LOCK_SIZE + li a3, CFG_CACHELINE_SIZE + move a1, a2 + icacheop(a0,a1,a2,a3,0x1d) + + j ra + .end mips_cache_lock diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk new file mode 100644 index 0000000..c357615 --- /dev/null +++ b/cpu/mips/config.mk @@ -0,0 +1,40 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +v=$(shell \ +mips-linux-as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}') +MIPSFLAGS=$(shell \ +if [ "$v" -lt "14" ]; then \ + echo "-mcpu=4kc"; \ +else \ + echo "-march=4kc -mtune=4kc"; \ +fi) + +ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) +ENDIANNESS = -EL +else +ENDIANNESS = -EB +endif + +MIPSFLAGS += $(ENDIANNESS) -mabicalls + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c new file mode 100644 index 0000000..f48675e --- /dev/null +++ b/cpu/mips/cpu.c @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_INCA_IP) + *INCA_IP_WDT_RST_REQ = 0x3f; +#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229) + void (*f)(void) = (void *) 0xbfc00000; + + f(); +#endif + fprintf(stderr, "*** reset failed ***\n"); + return 0; +} + +void flush_cache (ulong start_addr, ulong size) +{ + +} + +void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){ + write_32bit_cp0_register(CP0_ENTRYLO0, low0); + write_32bit_cp0_register(CP0_PAGEMASK, pagemask); + write_32bit_cp0_register(CP0_ENTRYLO1, low1); + write_32bit_cp0_register(CP0_ENTRYHI, hi); + write_32bit_cp0_register(CP0_INDEX, index); + tlb_write_indexed(); +} diff --git a/cpu/mips/incaip_clock.c b/cpu/mips/incaip_clock.c new file mode 100644 index 0000000..d0515ca --- /dev/null +++ b/cpu/mips/incaip_clock.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +/******************************************************************************* +* +* get_cpuclk - returns the frequency of the CPU. +* +* Gets the value directly from the INCA-IP hardware. +* +* RETURNS: +* 150.000.000 for 150 MHz +* 133.333.333 for 133 Mhz (= 400MHz/3) +* 100.000.000 for 100 Mhz (= 400MHz/4) +* NOTE: +* This functions should be used by the hardware driver to get the correct +* frequency of the CPU. Don't use the macros, which are set to init the CPU +* frequency in the ROM code. +*/ +uint incaip_get_cpuclk (void) +{ + /*-------------------------------------------------------------------------*/ + /* CPU Clock Input Multiplexer (MUX I) */ + /* Multiplexer MUX I selects the maximum input clock to the CPU. */ + /*-------------------------------------------------------------------------*/ + if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) & + INCA_IP_CGU_CGU_MUXCR_MUXI) { + /* MUX I set to 150 MHz clock */ + return 150000000; + } else { + /* MUX I set to 100/133 MHz clock */ + if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) { + /* Division value is 1/3, maximum CPU operating */ + /* frequency is 133.3 MHz */ + return 133333333; + } else { + /* Division value is 1/4, maximum CPU operating */ + /* frequency is 100 MHz */ + return 100000000; + } + } +} + +/******************************************************************************* +* +* get_fpiclk - returns the frequency of the FPI bus. +* +* Gets the value directly from the INCA-IP hardware. +* +* RETURNS: Frquency in Hz +* +* NOTE: +* This functions should be used by the hardware driver to get the correct +* frequency of the CPU. Don't use the macros, which are set to init the CPU +* frequency in the ROM code. +* The calculation for the +*/ +uint incaip_get_fpiclk (void) +{ + uint clkCPU; + + clkCPU = incaip_get_cpuclk (); + + switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) { + case 0x4: + return clkCPU >> 1; /* devided by 2 */ + break; + case 0x8: + return clkCPU >> 2; /* devided by 4 */ + break; + default: + return clkCPU; + break; + } +} + +int incaip_set_cpuclk (void) +{ + extern void ebu_init(long); + extern void cgu_init(long); + extern void sdram_init(long); + char tmp[64]; + ulong cpuclk; + + if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) { + cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; + cgu_init (cpuclk); + ebu_init (cpuclk); + sdram_init (cpuclk); + } + + return 0; +} diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S new file mode 100644 index 0000000..71adaa1 --- /dev/null +++ b/cpu/mips/incaip_wdt.S @@ -0,0 +1,72 @@ +/* + * INCA-IP Watchdog timer management code. + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include + + +#define WD_BASE 0xb8000000 +#define WD_CON0(value) 0x0020(value) +#define WD_CON1(value) 0x0024(value) +#define WD_DISABLE 0x00000008 +#define WD_ENABLE 0x00000000 +#define WD_WRITE_PW 0xFFFC00F8 +#define WD_WRITE_ENDINIT 0xFFFC00F3 +#define WD_WRITE_INIT 0xFFFC00F2 + + + .globl disable_incaip_wdt +disable_incaip_wdt: + li t0, WD_BASE + + /* Calculate password. + */ + lw t2, WD_CON1(t0) + and t2, 0xC + + lw t3, WD_CON0(t0) + and t3, 0xFFFFFF01 + + or t3, t2 + or t3, 0xF0 + + sw t3, WD_CON0(t0) /* write password */ + + /* Clear ENDINIT. + */ + li t1, WD_WRITE_INIT + sw t1, WD_CON0(t0) + + + li t1, WD_DISABLE + sw t1, WD_CON1(t0) /* disable watchdog */ + li t1, WD_WRITE_PW + sw t1, WD_CON0(t0) /* write password */ + li t1, WD_WRITE_ENDINIT + sw t1, WD_CON0(t0) /* end command */ + + j ra + nop diff --git a/cpu/mips/interrupts.c b/cpu/mips/interrupts.c new file mode 100644 index 0000000..87f7a9f --- /dev/null +++ b/cpu/mips/interrupts.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +void enable_interrupts(void) +{ +} + +int disable_interrupts(void) +{ + return 0; +} diff --git a/cpu/mips/start.S b/cpu/mips/start.S new file mode 100644 index 0000000..e91e213 --- /dev/null +++ b/cpu/mips/start.S @@ -0,0 +1,390 @@ +/* + * Startup Code for MIPS32 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include + + +#define RVECENT(f,n) \ + b f; nop +#define XVECENT(f,bev) \ + b f ; \ + li k0,bev + + .set noreorder + + .globl _start + .text +_start: + RVECENT(reset,0) /* U-boot entry point */ + RVECENT(reset,1) /* software reboot */ +#if defined(CONFIG_INCA_IP) + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ + .word 0x00000000 /* phase of the flash */ +#elif defined(CONFIG_PURPLE) + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ + .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ +#else + RVECENT(romReserved,2) +#endif + RVECENT(romReserved,3) + RVECENT(romReserved,4) + RVECENT(romReserved,5) + RVECENT(romReserved,6) + RVECENT(romReserved,7) + RVECENT(romReserved,8) + RVECENT(romReserved,9) + RVECENT(romReserved,10) + RVECENT(romReserved,11) + RVECENT(romReserved,12) + RVECENT(romReserved,13) + RVECENT(romReserved,14) + RVECENT(romReserved,15) + RVECENT(romReserved,16) + RVECENT(romReserved,17) + RVECENT(romReserved,18) + RVECENT(romReserved,19) + RVECENT(romReserved,20) + RVECENT(romReserved,21) + RVECENT(romReserved,22) + RVECENT(romReserved,23) + RVECENT(romReserved,24) + RVECENT(romReserved,25) + RVECENT(romReserved,26) + RVECENT(romReserved,27) + RVECENT(romReserved,28) + RVECENT(romReserved,29) + RVECENT(romReserved,30) + RVECENT(romReserved,31) + RVECENT(romReserved,32) + RVECENT(romReserved,33) + RVECENT(romReserved,34) + RVECENT(romReserved,35) + RVECENT(romReserved,36) + RVECENT(romReserved,37) + RVECENT(romReserved,38) + RVECENT(romReserved,39) + RVECENT(romReserved,40) + RVECENT(romReserved,41) + RVECENT(romReserved,42) + RVECENT(romReserved,43) + RVECENT(romReserved,44) + RVECENT(romReserved,45) + RVECENT(romReserved,46) + RVECENT(romReserved,47) + RVECENT(romReserved,48) + RVECENT(romReserved,49) + RVECENT(romReserved,50) + RVECENT(romReserved,51) + RVECENT(romReserved,52) + RVECENT(romReserved,53) + RVECENT(romReserved,54) + RVECENT(romReserved,55) + RVECENT(romReserved,56) + RVECENT(romReserved,57) + RVECENT(romReserved,58) + RVECENT(romReserved,59) + RVECENT(romReserved,60) + RVECENT(romReserved,61) + RVECENT(romReserved,62) + RVECENT(romReserved,63) + XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */ + RVECENT(romReserved,65) + RVECENT(romReserved,66) + RVECENT(romReserved,67) + RVECENT(romReserved,68) + RVECENT(romReserved,69) + RVECENT(romReserved,70) + RVECENT(romReserved,71) + RVECENT(romReserved,72) + RVECENT(romReserved,73) + RVECENT(romReserved,74) + RVECENT(romReserved,75) + RVECENT(romReserved,76) + RVECENT(romReserved,77) + RVECENT(romReserved,78) + RVECENT(romReserved,79) + XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */ + RVECENT(romReserved,81) + RVECENT(romReserved,82) + RVECENT(romReserved,83) + RVECENT(romReserved,84) + RVECENT(romReserved,85) + RVECENT(romReserved,86) + RVECENT(romReserved,87) + RVECENT(romReserved,88) + RVECENT(romReserved,89) + RVECENT(romReserved,90) + RVECENT(romReserved,91) + RVECENT(romReserved,92) + RVECENT(romReserved,93) + RVECENT(romReserved,94) + RVECENT(romReserved,95) + XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */ + RVECENT(romReserved,97) + RVECENT(romReserved,98) + RVECENT(romReserved,99) + RVECENT(romReserved,100) + RVECENT(romReserved,101) + RVECENT(romReserved,102) + RVECENT(romReserved,103) + RVECENT(romReserved,104) + RVECENT(romReserved,105) + RVECENT(romReserved,106) + RVECENT(romReserved,107) + RVECENT(romReserved,108) + RVECENT(romReserved,109) + RVECENT(romReserved,110) + RVECENT(romReserved,111) + XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */ + RVECENT(romReserved,113) + RVECENT(romReserved,114) + RVECENT(romReserved,115) + RVECENT(romReserved,116) + RVECENT(romReserved,116) + RVECENT(romReserved,118) + RVECENT(romReserved,119) + RVECENT(romReserved,120) + RVECENT(romReserved,121) + RVECENT(romReserved,122) + RVECENT(romReserved,123) + RVECENT(romReserved,124) + RVECENT(romReserved,125) + RVECENT(romReserved,126) + RVECENT(romReserved,127) + + /* We hope there are no more reserved vectors! + * 128 * 8 == 1024 == 0x400 + * so this is address R_VEC+0x400 == 0xbfc00400 + */ +#ifdef CONFIG_PURPLE +/* 0xbfc00400 */ + .word 0xdc870000 + .word 0xfca70000 + .word 0x20840008 + .word 0x20a50008 + .word 0x20c6ffff + .word 0x14c0fffa + .word 0x00000000 + .word 0x03e00008 + .word 0x00000000 + .word 0x00000000 +/* 0xbfc00428 */ + .word 0xdc870000 + .word 0xfca70000 + .word 0x20840008 + .word 0x20a50008 + .word 0x20c6ffff + .word 0x14c0fffa + .word 0x00000000 + .word 0x03e00008 + .word 0x00000000 + .word 0x00000000 +#endif /* CONFIG_PURPLE */ + .align 4 +reset: + + /* Clear watch registers. + */ + mtc0 zero, CP0_WATCHLO + mtc0 zero, CP0_WATCHHI + + /* STATUS register */ +#ifdef CONFIG_TB0229 + li k0, ST0_CU0 +#else + mfc0 k0, CP0_STATUS +#endif + li k1, ~ST0_IE + and k0, k1 + mtc0 k0, CP0_STATUS + + /* CAUSE register */ + mtc0 zero, CP0_CAUSE + + /* Init Timer */ + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + + /* CONFIG0 register */ + li t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + + /* Initialize GOT pointer. + */ + bal 1f + nop + .word _GLOBAL_OFFSET_TABLE_ + 1: + move gp, ra + lw t1, 0(ra) + move gp, t1 + +#ifdef CONFIG_INCA_IP + /* Disable INCA-IP Watchdog. + */ + la t9, disable_incaip_wdt + jalr t9 + nop +#endif + + /* Initialize any external memory. + */ + la t9, lowlevel_init + jalr t9 + nop + + /* Initialize caches... + */ + la t9, mips_cache_reset + jalr t9 + nop + + /* ... and enable them. + */ + li t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + + + /* Set up temporary stack. + */ + li a0, CFG_INIT_SP_OFFSET + la t9, mips_cache_lock + jalr t9 + nop + + li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET + la sp, 0(t0) + + la t9, board_init_f + j t9 + nop + + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * a0 = addr_sp + * a1 = gd + * a2 = destination address + */ + .globl relocate_code + .ent relocate_code +relocate_code: + move sp, a0 /* Set new stack pointer */ + + li t0, CFG_MONITOR_BASE + la t3, in_ram + lw t2, -12(t3) /* t2 <-- uboot_end_data */ + move t1, a2 + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + */ + move t6, gp + sub gp, CFG_MONITOR_BASE + add gp, a2 /* gp now adjusted */ + sub t6, gp, t6 /* t6 <-- relocation offset */ + + /* + * t0 = source address + * t1 = target address + * t2 = source end address + */ + /* On the purple board we copy the code earlier in a special way + * in order to solve flash problems + */ +#ifndef CONFIG_PURPLE +1: + lw t3, 0(t0) + sw t3, 0(t1) + addu t0, 4 + ble t0, t2, 1b + addu t1, 4 /* delay slot */ +#endif + + /* If caches were enabled, we would have to flush them here. + */ + + /* Jump to where we've relocated ourselves. + */ + addi t0, a2, in_ram - _start + j t0 + nop + + .word uboot_end_data + .word uboot_end + .word num_got_entries + +in_ram: + /* Now we want to update GOT. + */ + lw t3, -4(t0) /* t3 <-- num_got_entries */ + addi t4, gp, 8 /* Skipping first two entries. */ + li t2, 2 +1: + lw t1, 0(t4) + beqz t1, 2f + add t1, t6 + sw t1, 0(t4) +2: + addi t2, 1 + blt t2, t3, 1b + addi t4, 4 /* delay slot */ + + /* Clear BSS. + */ + lw t1, -12(t0) /* t1 <-- uboot_end_data */ + lw t2, -8(t0) /* t2 <-- uboot_end */ + add t1, t6 /* adjust pointers */ + add t2, t6 + + sub t1, 4 +1: addi t1, 4 + bltl t1, t2, 1b + sw zero, 0(t1) /* delay slot */ + + move a0, a1 + la t9, board_init_r + j t9 + move a1, a2 /* delay slot */ + + .end relocate_code + + + /* Exception handlers. + */ +romReserved: + b romReserved + +romExcHandle: + b romExcHandle diff --git a/cpu/mpc5xx/Makefile b/cpu/mpc5xx/Makefile new file mode 100644 index 0000000..b787b61 --- /dev/null +++ b/cpu/mpc5xx/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2003 +# Martin Winistoerfer, martinwinistoerfer@gmx.ch. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# File: cpu/mpc5xx/Makefile +# +# Discription: Makefile to build mpc5xx cpu configuration. +# Will include top config.mk which itselfs +# uses the definitions made in cpu/mpc5xx/config.mk +# + + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.S +OBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk new file mode 100644 index 0000000..5b26a76 --- /dev/null +++ b/cpu/mpc5xx/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2003 +# Martin Winistoerfer, martinwinistoerfer@gmx.ch. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# File: config.mk +# +# Discription: compiler flags and make definitions +# + + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float diff --git a/cpu/mpc5xx/cpu.c b/cpu/mpc5xx/cpu.c new file mode 100644 index 0000000..0c22a31 --- /dev/null +++ b/cpu/mpc5xx/cpu.c @@ -0,0 +1,173 @@ +/* + * (C) Copyright 2003 + * Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, + */ + +/* + * File: cpu.c + * + * Discription: Some cpu specific function for watchdog, + * cpu version test, clock setting ... + * + */ + + +#include +#include +#include +#include + + +#if (defined(CONFIG_MPC555)) +# define ID_STR "MPC555/556" + +/* + * Check version of cpu with Processor Version Register (PVR) + */ +static int check_cpu_version (long clock, uint pvr, uint immr) +{ + char buf[32]; + /* The highest 16 bits should be 0x0002 for a MPC555/556 */ + if ((pvr >> 16) == 0x0002) { + printf (" " ID_STR " Version %x", (pvr >> 16)); + printf (" at %s MHz:", strmhz (buf, clock)); + } else { + printf ("Not supported cpu version"); + return -1; + } + return 0; +} +#endif /* CONFIG_MPC555 */ + + +/* + * Check version of mpc5xx + */ +int checkcpu (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong clock = gd->cpu_clk; + uint immr = get_immr (0); /* Return full IMMR contents */ + uint pvr = get_pvr (); /* Retrieve PVR register */ + + puts ("CPU: "); + + return check_cpu_version (clock, pvr, immr); +} + +/* + * Called by macro WATCHDOG_RESET + */ +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + int re_enable = disable_interrupts (); + + reset_5xx_watchdog ((immap_t *) CFG_IMMR); + if (re_enable) + enable_interrupts (); +} + +/* + * Will clear software reset + */ +void reset_5xx_watchdog (volatile immap_t * immr) +{ + /* Use the MPC5xx Internal Watchdog */ + immr->im_siu_conf.sc_swsr = 0x556c; /* Prevent SW time-out */ + immr->im_siu_conf.sc_swsr = 0xaa39; +} + +#endif /* CONFIG_WATCHDOG */ + + +/* + * Get timebase clock frequency + */ +unsigned long get_tbclk (void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immr = (volatile immap_t *) CFG_IMMR; + ulong oscclk, factor; + + if (immr->im_clkrst.car_sccr & SCCR_TBS) { + return (gd->cpu_clk / 16); + } + + factor = (((CFG_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1; + + oscclk = gd->cpu_clk / factor; + + if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { + return (oscclk / 4); + } + return (oscclk / 16); +} + +void dcache_enable (void) +{ + return; +} + +void dcache_disable (void) +{ + return; +} + +int dcache_status (void) +{ + return 0; /* always off */ +} + +/* + * Reset board + */ +int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_PATI) + volatile ulong *addr = (ulong *) CFG_RESET_ADDRESS; + *addr = 1; +#else + ulong addr; + + /* Interrupts off, enable reset */ + __asm__ volatile (" mtspr 81, %r0 \n\t" + " mfmsr %r3 \n\t" + " rlwinm %r31,%r3,0,25,23\n\t" + " mtmsr %r31 \n\t"); + /* + * Trying to execute the next instruction at a non-existing address + * should cause a machine check, resulting in reset + */ +#ifdef CFG_RESET_ADDRESS + addr = CFG_RESET_ADDRESS; +#else + /* + * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address + * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. + * "(ulong)-1" used to be a good choice for many systems... + */ + addr = CFG_MONITOR_BASE - sizeof (ulong); +#endif + ((void (*) (void)) addr) (); +#endif /* #if defined(CONFIG_PATI) */ + return 1; +} diff --git a/cpu/mpc5xx/cpu_init.c b/cpu/mpc5xx/cpu_init.c new file mode 100644 index 0000000..f4cd24b --- /dev/null +++ b/cpu/mpc5xx/cpu_init.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, + */ + +/* + * File: cpu_init.c + * + * Discription: Contains initialisation functions to setup + * the cpu properly + * + */ + +#include +#include +#include + +/* + * Setup essential cpu registers to run + */ +void cpu_init_f (volatile immap_t * immr) +{ + volatile memctl5xx_t *memctl = &immr->im_memctl; + ulong reg; + + /* SYPCR - contains watchdog control. This will enable watchdog */ + /* if CONFIG_WATCHDOG is set */ + immr->im_siu_conf.sc_sypcr = CFG_SYPCR; + +#if defined(CONFIG_WATCHDOG) + reset_5xx_watchdog (immr); +#endif + + /* SIUMCR - contains debug pin configuration */ + immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR; + + /* Initialize timebase. Unlock TBSCRK */ + immr->im_sitk.sitk_tbscrk = KAPWR_KEY; + immr->im_sit.sit_tbscr = CFG_TBSCR; + + /* Full IMB bus speed */ + immr->im_uimb.uimb_umcr = CFG_UMCR; + + /* Time base and decrementer will be enables (TBE) */ + /* in init_timebase() in time.c called from board_init_f(). */ + + /* Initialize the PIT. Unlock PISCRK */ + immr->im_sitk.sitk_piscrk = KAPWR_KEY; + immr->im_sit.sit_piscr = CFG_PISCR; + +#if !defined(CONFIG_PATI) + /* PATI sest PLL in start.S */ + /* PLL (CPU clock) settings */ + immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; + + /* If CFG_PLPRCR (set in the various *_config.h files) tries to + * set the MF field, then just copy CFG_PLPRCR over car_plprcr, + * otherwise OR in CFG_PLPRCR so we do not change the currentMF + * field value. + */ +#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0) + reg = CFG_PLPRCR; /* reset control bits */ +#else + reg = immr->im_clkrst.car_plprcr; + reg &= PLPRCR_MF_MSK; /* isolate MF field */ + reg |= CFG_PLPRCR; /* reset control bits */ +#endif + immr->im_clkrst.car_plprcr = reg; + +#endif /* !defined(CONFIG_PATI) */ + + /* System integration timers. CFG_MASK has EBDF configuration */ + immr->im_clkrstk.cark_sccrk = KAPWR_KEY; + reg = immr->im_clkrst.car_sccr; + reg &= SCCR_MASK; + reg |= CFG_SCCR; + immr->im_clkrst.car_sccr = reg; + + /* Memory Controller */ + memctl->memc_br0 = CFG_BR0_PRELIM; + memctl->memc_or0 = CFG_OR0_PRELIM; + +#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; +#endif + +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; +#endif + +#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; +#endif + +} + +/* + * Initialize higher level parts of cpu + */ +int cpu_init_r (void) +{ + /* Nothing to do at the moment */ + return (0); +} diff --git a/cpu/mpc5xx/interrupts.c b/cpu/mpc5xx/interrupts.c new file mode 100644 index 0000000..7f6e136 --- /dev/null +++ b/cpu/mpc5xx/interrupts.c @@ -0,0 +1,207 @@ +/* + * (C) Copyright 2000-2002 Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, + */ + +/* + * File: interrupt.c + * + * Discription: Contains interrupt routines needed by U-Boot + * + */ + +#include +#include +#include +#include + +#if defined(CONFIG_PATI) +/* PATI uses IRQs for PCI doorbell */ +#undef NR_IRQS +#define NR_IRQS 16 +#endif + +struct interrupt_action { + interrupt_handler_t *handler; + void *arg; + int count; +}; + +static struct interrupt_action irq_vecs[NR_IRQS]; + +/* + * Initialise interrupts + */ + +int interrupt_init_cpu (ulong *decrementer_count) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + int vec; + + /* Decrementer used here for status led */ + *decrementer_count = get_tbclk () / CFG_HZ; + + /* Disable all interrupts */ + immr->im_siu_conf.sc_simask = 0; + for (vec=0; vecim_siu_conf.sc_sivec; + irq = vec >> 26; + v_bit = 0x80000000UL >> irq; + + /* + * Read Interrupt Mask Register and Mask Interrupts + */ + simask = immr->im_siu_conf.sc_simask; + newmask = simask & (~(0xFFFF0000 >> irq)); + immr->im_siu_conf.sc_simask = newmask; + + if (!(irq & 0x1)) { /* External Interrupt ? */ + ulong siel; + + /* + * Read Interrupt Edge/Level Register + */ + siel = immr->im_siu_conf.sc_siel; + + if (siel & v_bit) { /* edge triggered interrupt ? */ + /* + * Rewrite SIPEND Register to clear interrupt + */ + immr->im_siu_conf.sc_sipend = v_bit; + } + } + + if (irq_vecs[irq].handler != NULL) { + irq_vecs[irq].handler (irq_vecs[irq].arg); + } else { + printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", + irq, vec); + /* turn off the bogus interrupt to avoid it from now */ + simask &= ~v_bit; + } + /* + * Re-Enable old Interrupt Mask + */ + immr->im_siu_conf.sc_simask = simask; +} + +/* + * Install and free an interrupt handler + */ +void irq_install_handler (int vec, interrupt_handler_t * handler, + void *arg) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + /* SIU interrupt */ + if (irq_vecs[vec].handler != NULL) { + printf ("SIU interrupt %d 0x%x\n", + vec, + (uint) handler); + } + irq_vecs[vec].handler = handler; + irq_vecs[vec].arg = arg; + immr->im_siu_conf.sc_simask |= 1 << (31 - vec); +#if 0 + printf ("Install SIU interrupt for vector %d ==> %p\n", + vec, handler); +#endif +} + +void irq_free_handler (int vec) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + /* SIU interrupt */ +#if 0 + printf ("Free CPM interrupt for vector %d\n", + vec); +#endif + immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); + irq_vecs[vec].handler = NULL; + irq_vecs[vec].arg = NULL; +} + +/* + * Timer interrupt - gets called when bit 0 of DEC changes from + * 0. Decrementer is enabled with bit TBE in TBSCR. + */ +void timer_interrupt_cpu (struct pt_regs *regs) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + +#if 0 + printf ("*** Timer Interrupt *** "); +#endif + /* Reset Timer Status Bit and Timers Interrupt Status */ + immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; + __asm__ ("nop"); + immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST; + + return; +} + +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +/******************************************************************************* + * + * irqinfo - print information about IRQs + * + */ +int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int vec; + + printf ("\nInterrupt-Information:\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec +#include +#include +#include + + +/* + * Local function prototypes + */ + +static int ready_to_send(void); + +/* + * Minimal global serial functions needed to use one of the SCI modules. + */ + +int serial_init (void) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + + serial_setbrg(); + +#if defined(CONFIG_5xx_CONS_SCI1) + /* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */ + immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10; + immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE; +#else + immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10; + immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE; +#endif + return 0; +} + +void serial_putc(const char c) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + + /* Test for completition */ + if(ready_to_send()) { +#if defined(CONFIG_5xx_CONS_SCI1) + immr->im_qsmcm.qsmcm_sc1dr = (short)c; +#else + immr->im_qsmcm.qsmcm_sc2dr = (short)c; +#endif + if(c == '\n') { + if(ready_to_send()); +#if defined(CONFIG_5xx_CONS_SCI1) + immr->im_qsmcm.qsmcm_sc1dr = (short)'\r'; +#else + immr->im_qsmcm.qsmcm_sc2dr = (short)'\r'; +#endif + } + } +} + +int serial_getc(void) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile short status; + unsigned char tmp; + + /* New data ? */ + do { +#if defined(CONFIG_5xx_CONS_SCI1) + status = immr->im_qsmcm.qsmcm_sc1sr; +#else + status = immr->im_qsmcm.qsmcm_sc2sr; +#endif + +#if defined(CONFIG_WATCHDOG) + reset_5xx_watchdog (immr); +#endif + } while ((status & SCI_RDRF) == 0); + + /* Read data */ +#if defined(CONFIG_5xx_CONS_SCI1) + tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK); +#else + tmp = (unsigned char)( immr->im_qsmcm.qsmcm_sc2dr & SCI_SCXDR_MK); +#endif + return tmp; +} + +int serial_tstc() +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + short status; + + /* New data character ? */ +#if defined(CONFIG_5xx_CONS_SCI1) + status = immr->im_qsmcm.qsmcm_sc1sr; +#else + status = immr->im_qsmcm.qsmcm_sc2sr; +#endif + return (status & SCI_RDRF); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + short scxbr; + + /* Set baudrate */ + scxbr = (gd->cpu_clk / (32 * gd->baudrate)); +#if defined(CONFIG_5xx_CONS_SCI1) + immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK); +#else + immr->im_qsmcm.qsmcm_scc2r0 = (scxbr & SCI_SCXBR_MK); +#endif +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc(*s); + ++s; + } +} + +int ready_to_send(void) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile short status; + + do { +#if defined(CONFIG_5xx_CONS_SCI1) + status = immr->im_qsmcm.qsmcm_sc1sr; +#else + status = immr->im_qsmcm.qsmcm_sc2sr; +#endif + +#if defined(CONFIG_WATCHDOG) + reset_5xx_watchdog (immr); +#endif + } while ((status & SCI_TDRE) == 0); + return 1; + +} diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c new file mode 100644 index 0000000..f6097f5 --- /dev/null +++ b/cpu/mpc5xx/speed.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2003 + * Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, + */ + +/* + * File: speed.c + * + * Discription: Provides cpu speed calculation + * + */ + +#include +#include +#include + +/* + * Get cpu and bus clock + */ +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + +#ifndef CONFIG_5xx_GCLK_FREQ + uint divf = (immr->im_clkrst.car_plprcr & PLPRCR_DIVF_MSK); + uint mf = ((immr->im_clkrst.car_plprcr & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT); + ulong vcoout; + + vcoout = (CFG_OSC_CLK / (divf + 1)) * (mf + 1) * 2; + if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) { + gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1)); + } else { + gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK)); + } + +#else /* CONFIG_5xx_GCLK_FREQ */ + gd->bus_clk = CONFIG_5xx_GCLK_FREQ; +#endif /* CONFIG_5xx_GCLK_FREQ */ + + if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) { + /* No Bus Divider active */ + gd->bus_clk = gd->cpu_clk; + } else { + /* CLKOUT is GCLK / 2 */ + gd->bus_clk = gd->cpu_clk / 2; + } + return (0); +} diff --git a/cpu/mpc5xx/spi.c b/cpu/mpc5xx/spi.c new file mode 100644 index 0000000..81c9ddb --- /dev/null +++ b/cpu/mpc5xx/spi.c @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2001 Navin Boppuri / Prashant Patel + * , + * + * Copyright (c) 2001 Gerd Mennchen + * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC5xx CPM SPI interface. + * + * Parts of this code are probably not portable and/or specific to + * the board which I used for the tests. Please send fixes/complaints + * to wd@denx.de + * + * Ported to MPC5xx + * Copyright (c) 2003 Denis Peter, MPL AG Switzerland, d.petr@mpl.ch. + */ + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SPI) + +#undef DEBUG + +#define SPI_EEPROM_WREN 0x06 +#define SPI_EEPROM_RDSR 0x05 +#define SPI_EEPROM_READ 0x03 +#define SPI_EEPROM_WRITE 0x02 + + +#ifdef DEBUG + +#define DPRINT(a) printf a; +/* ----------------------------------------------- + * Helper functions to peek into tx and rx buffers + * ----------------------------------------------- */ +static const char * const hex_digit = "0123456789ABCDEF"; + +static char quickhex (int i) +{ + return hex_digit[i]; +} + +static void memdump (void *pv, int num) +{ + int i; + unsigned char *pc = (unsigned char *) pv; + + for (i = 0; i < num; i++) + printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); + printf ("\t"); + for (i = 0; i < num; i++) + printf ("%c", isprint (pc[i]) ? pc[i] : '.'); + printf ("\n"); +} +#else /* !DEBUG */ + +#define DPRINT(a) + +#endif /* DEBUG */ + +/* ------------------- + * Function prototypes + * ------------------- */ +void spi_init (void); + +ssize_t spi_read (uchar *, int, uchar *, int); +ssize_t spi_write (uchar *, int, uchar *, int); +ssize_t spi_xfer (size_t); + + +/* ************************************************************************** + * + * Function: spi_init_f + * + * Description: Init SPI-Controller (ROM part) + * + * return: --- + * + * *********************************************************************** */ + +void spi_init_f (void) +{ + int i; + + volatile immap_t *immr; + volatile qsmcm5xx_t *qsmcm; + + immr = (immap_t *) CFG_IMMR; + qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; + + qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */ + qsmcm->qsmcm_qspi_il = 0; /* lowest IRQ */ + + /* -------------------------------------------- + * GPIO or per. Function + * PQSPAR[00] = 0 reserved + * PQSPAR[01] = 1 [0x4000] -> PERI: (SPICS3) + * PQSPAR[02] = 0 [0x0000] -> GPIO + * PQSPAR[03] = 0 [0x0000] -> GPIO + * PQSPAR[04] = 1 [0x0800] -> PERI: (SPICS0) + * PQSPAR[05] = 0 reseved + * PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI) + * PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO) + * -------------------------------------------- */ + qsmcm->qsmcm_pqspar = 0x3 | (CFG_SPI_CS_USED << 3); + + /* -------------------------------------------- + * DDRQS[00] = 0 reserved + * DDRQS[01] = 1 [0x0040] -> SPICS3 Output + * DDRQS[02] = 0 [0x0000] -> GPIO Output + * DDRQS[03] = 0 [0x0000] -> GPIO Output + * DDRQS[04] = 1 [0x0008] -> SPICS0 Output + * DDRQS[05] = 1 [0x0004] -> SPICLK Output + * DDRQS[06] = 1 [0x0002] -> SPIMOSI Output + * DDRQS[07] = 0 [0x0001] -> SPIMISO Input + * -------------------------------------------- */ + qsmcm->qsmcm_ddrqs = 0x7E; + /* -------------------------------------------- + * Base state for used SPI CS pins, if base = 0 active must be 1 + * PORTQS[00] = 0 reserved + * PORTQS[01] = 0 reserved + * PORTQS[02] = 0 reserved + * PORTQS[03] = 0 reserved + * PORTQS[04] = 0 [0x0000] RxD2 + * PORTQS[05] = 1 [0x0400] TxD2 + * PORTQS[06] = 0 [0x0000] RxD1 + * PORTQS[07] = 1 [0x0100] TxD1 + * PORTQS[08] = 0 reserved + * PORTQS[09] = 0 [0x0000] -> SPICS3 Base Output + * PORTQS[10] = 0 [0x0000] -> SPICS2 Base Output + * PORTQS[11] = 0 [0x0000] -> SPICS1 Base Output + * PORTQS[12] = 0 [0x0000] -> SPICS0 Base Output + * PORTQS[13] = 0 [0x0004] -> SPICLK Output + * PORTQS[14] = 0 [0x0002] -> SPIMOSI Output + * PORTQS[15] = 0 [0x0001] -> SPIMISO Input + * -------------------------------------------- */ + qsmcm->qsmcm_portqs |= (CFG_SPI_CS_BASE << 3); + /* -------------------------------------------- + * Controll Register 0 + * SPCR0[00] = 1 (0x8000) Master + * SPCR0[01] = 0 (0x0000) Wired-Or + * SPCR0[2..5] = (0x2000) Bits per transfer (default 8) + * SPCR0[06] = 0 (0x0000) Normal polarity + * SPCR0[07] = 0 (0x0000) Normal Clock Phase + * SPCR0[08..15] = 14 1.4MHz + */ + qsmcm->qsmcm_spcr0=0xA00E; + /* -------------------------------------------- + * Controll Register 1 + * SPCR1[00] = 0 (0x0000) QSPI enabled + * SPCR1[1..7] = (0x7F00) Delay before Transfer + * SPCR1[8..15] = (0x0000) Delay After transfer (204.8usec@40MHz) + */ + qsmcm->qsmcm_spcr1=0x7F00; + /* -------------------------------------------- + * Controll Register 2 + * SPCR2[00] = 0 (0x0000) SPI IRQs Disabeld + * SPCR2[01] = 0 (0x0000) No Wrap around + * SPCR2[02] = 0 (0x0000) Wrap to 0 + * SPCR2[3..7] = (0x0000) End Queue pointer = 0 + * SPCR2[8..10] = 0 (0x0000) reserved + * SPCR2[11..15] = 0 (0x0000) NewQueue Address = 0 + */ + qsmcm->qsmcm_spcr2=0x0000; + /* -------------------------------------------- + * Controll Register 3 + * SPCR3[00..04] = 0 (0x0000) reserved + * SPCR3[05] = 0 (0x0000) Feedback disabled + * SPCR3[06] = 0 (0x0000) IRQ on HALTA & MODF disabled + * SPCR3[07] = 0 (0x0000) Not halted + */ + qsmcm->qsmcm_spcr3=0x00; + /* -------------------------------------------- + * SPSR (Controll Register 3) Read only/ reset Flags 08,09,10 + * SPCR3[08] = 1 (0x80) QSPI finished + * SPCR3[09] = 1 (0x40) Mode Fault Flag + * SPCR3[10] = 1 (0x20) HALTA + * SPCR3[11..15] = 0 (0x0000) Last executed command + */ + qsmcm->qsmcm_spsr=0xE0; + /*------------------------------------------- + * Setup RAM + */ + for(i=0;i<32;i++) { + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; + } + return; +} + +/* ************************************************************************** + * + * Function: spi_init_r + * Dummy, all initializations have been done in spi_init_r + * *********************************************************************** */ +void spi_init_r (void) +{ + return; + +} + +/**************************************************************************** + * Function: spi_write + **************************************************************************** */ +ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len) +{ + int i,dlen; + volatile immap_t *immr; + volatile qsmcm5xx_t *qsmcm; + + immr = (immap_t *) CFG_IMMR; + qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; + for(i=0;i<32;i++) { + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; + } + qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */ + spi_xfer(1); + i=0; + qsmcm->qsmcm_tranram[i++] = SPI_EEPROM_WRITE; /* WRITE memory array */ + qsmcm->qsmcm_tranram[i++] = addr[0]; + qsmcm->qsmcm_tranram[i++] = addr[1]; + + for(dlen=0;dlenqsmcm_tranram[i+dlen] = buffer[dlen]; /* WRITE memory array */ + } + /* transmit it */ + spi_xfer(i+dlen); + /* ignore received data */ + for (i = 0; i < 1000; i++) { + qsmcm->qsmcm_tranram[0] = SPI_EEPROM_RDSR; /* read status */ + qsmcm->qsmcm_tranram[1] = 0; + spi_xfer(2); + if (!(qsmcm->qsmcm_recram[1] & 1)) { + break; + } + udelay(1000); + } + if (i >= 1000) { + printf ("*** spi_write: Time out while writing!\n"); + } + return len; +} + +#define TRANSFER_LEN 16 + +ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) +{ + int index,i,newlen; + uchar newaddr[2]; + int curraddr; + + curraddr=(addr[alen-2]<<8)+addr[alen-1]; + i=len; + index=0; + do { + newaddr[1]=(curraddr & 0xff); + newaddr[0]=((curraddr>>8) & 0xff); + if(i>TRANSFER_LEN) { + newlen=TRANSFER_LEN; + i-=TRANSFER_LEN; + } + else { + newlen=i; + i=0; + } + short_spi_write (newaddr, 2, &buffer[index], newlen); + index+=newlen; + curraddr+=newlen; + }while(i); + return (len); +} + +/**************************************************************************** + * Function: spi_read + **************************************************************************** */ +ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len) +{ + int i; + volatile immap_t *immr; + volatile qsmcm5xx_t *qsmcm; + + immr = (immap_t *) CFG_IMMR; + qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; + + for(i=0;i<32;i++) { + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; + } + i=0; + qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */ + qsmcm->qsmcm_tranram[i++] = addr[0] & 0xff; + qsmcm->qsmcm_tranram[i++] = addr[1] & 0xff; + spi_xfer(3 + len); + for(i=0;iqsmcm_recram[i+3]; + } + return len; +} + +ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) +{ + int index,i,newlen; + uchar newaddr[2]; + int curraddr; + + curraddr=(addr[alen-2]<<8)+addr[alen-1]; + i=len; + index=0; + do { + newaddr[1]=(curraddr & 0xff); + newaddr[0]=((curraddr>>8) & 0xff); + if(i>TRANSFER_LEN) { + newlen=TRANSFER_LEN; + i-=TRANSFER_LEN; + } + else { + newlen=i; + i=0; + } + short_spi_read (newaddr, 2, &buffer[index], newlen); + index+=newlen; + curraddr+=newlen; + }while(i); + return (len); +} + +/**************************************************************************** + * Function: spi_xfer + **************************************************************************** */ +ssize_t spi_xfer (size_t count) +{ + volatile immap_t *immr; + volatile qsmcm5xx_t *qsmcm; + int i; + int tm; + ushort status; + immr = (immap_t *) CFG_IMMR; + qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; + DPRINT (("*** spi_xfer entered count %d***\n",count)); + + /* Set CS for device */ + for(i=0;i<(count-1);i++) + qsmcm->qsmcm_comdram[i] = 0x80 | CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ + + qsmcm->qsmcm_comdram[i] = CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ + qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8; + + DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count)); + + qsmcm->qsmcm_spsr=0xE0; /* clear all flags */ + + /* start spi transfer */ + DPRINT (("*** spi_xfer: Performing transfer ...\n")); + qsmcm->qsmcm_spcr1 |= 0x8000; /* Start transmit */ + + /* -------------------------------- + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * -------------------------------- */ + for (tm=0; tm<1000; ++tm) { + status=qsmcm->qsmcm_spcr1; + if((status & 0x8000)==0) + break; + udelay (1000); + } + if (tm >= 1000) { + printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); + } +#ifdef DEBUG + printf ("\nspi_xfer: txbuf after xfer\n"); + memdump ((void *) qsmcm->qsmcm_tranram, 32); /* dump of txbuf before transmit */ + printf ("spi_xfer: rxbuf after xfer\n"); + memdump ((void *) qsmcm->qsmcm_recram, 32); /* dump of rxbuf after transmit */ + printf ("\nspi_xfer: commbuf after xfer\n"); + memdump ((void *) qsmcm->qsmcm_comdram, 32); /* dump of txbuf before transmit */ + printf ("\n"); +#endif + + return count; +} + +#endif /* CONFIG_SPI */ diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S new file mode 100644 index 0000000..087435e --- /dev/null +++ b/cpu/mpc5xx/start.S @@ -0,0 +1,603 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000, 2001, 2002 Wolfgang Denk + * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * File: start.S + * + * Discription: startup code + * + */ + +#include +#include +#include + +#define CONFIG_5xx 1 /* needed for Linux kernel header files */ +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't have a MMU. +*/ +#undef MSR_KERNEL +#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +_start: + mfspr r3, 638 + li r4, CFG_ISB /* Set ISB bit */ + or r3, r3, r4 + mtspr 638, r3 + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ + b boot_cold + + . = EXC_OFF_SYS_RESET + 0x20 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + +boot_cold: +boot_warm: + + /* Initialize machine status; enable machine check interrupt */ + /*----------------------------------------------------------------------*/ + li r3, MSR_KERNEL /* Set ME, RI flags */ + mtmsr r3 + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + /* Initialize debug port registers */ + /*----------------------------------------------------------------------*/ + xor r0, r0, r0 /* Clear R0 */ + mtspr LCTRL1, r0 /* Initialize debug port regs */ + mtspr LCTRL2, r0 + mtspr COUNTA, r0 + mtspr COUNTB, r0 + +#if defined(CONFIG_PATI) + /* the external flash access on PATI fails if programming the PLL to 40MHz. + * Copy the PLL programming code to the internal RAM and execute it + *----------------------------------------------------------------------*/ + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET + + lis r4, CFG_INIT_RAM_ADDR@h + ori r4, r4, CFG_INIT_RAM_ADDR@l + mtlr r4 + addis r5,0,0x0 + ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2) + mtctr r5 + addi r3, r3, -4 + addi r4, r4, -4 +0: + lwzu r0,4(r3) + stwu r0,4(r4) + bdnz 0b /* copy loop */ + blrl +#endif + + /* + * Calculate absolute address in FLASH and jump there + *----------------------------------------------------------------------*/ + + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r3 + blr + +in_flash: + + /* Initialize some SPRs that are hard to access from C */ + /*----------------------------------------------------------------------*/ + + lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */ + lis r2, CFG_INIT_SP_ADDR@h + ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */ + /* Note: R0 is still 0 here */ + stwu r0, -4(r1) /* Clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* + * Disable serialized ifetch and show cycles + * (i.e. set processor to normal mode) for maximum + * performance. + */ + + li r2, 0x0007 + mtspr ICTRL, r2 + + /* Set up debug mode entry */ + + lis r2, CFG_DER@h + ori r2, r2, CFG_DER@l + mtspr DER, r2 + + /* Let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*----------------------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + + mr r3, r21 + /* r3: BOOTFLAG */ + bl board_init_f /* run 1st part of board init code (from Flash) */ + + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + /* FPU on MPC5xx available. We will use it later. + */ + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + /* On the MPC8xx, this is a software emulation interrupt. It occurs + * for all unimplemented and illegal instructions. + */ + STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) + STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) + STD_EXCEPTION(0x1400, DataTLBError, UnknownException) + + STD_EXCEPTION(0x1500, Reserved5, UnknownException) + STD_EXCEPTION(0x1600, Reserved6, UnknownException) + STD_EXCEPTION(0x1700, Reserved7, UnknownException) + STD_EXCEPTION(0x1800, Reserved8, UnknownException) + STD_EXCEPTION(0x1900, Reserved9, UnknownException) + STD_EXCEPTION(0x1a00, ReservedA, UnknownException) + STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + + STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) + STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException) + STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) + STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) + + + .globl _end_of_vectors +_end_of_vectors: + + + . = 0x2000 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + + +/* + * unsigned int get_immr (unsigned int mask) + * + * return (mask ? (IMMR & mask) : IMMR); + */ + .globl get_immr +get_immr: + mr r4,r3 /* save mask */ + mfspr r3, IMMR /* IMMR */ + cmpwi 0,r4,0 /* mask != 0 ? */ + beq 4f + and r3,r3,r4 /* IMMR & mask */ +4: + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer in SRAM */ + mr r9, r4 /* Save copy of global data pointer in SRAM */ + mr r10, r5 /* Save copy of monitor destination Address in SRAM */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* the the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 4f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +4: sync + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + sync + isync + + blr + + +#if defined(CONFIG_PATI) +/* Program the PLL */ +pll_prog_code_start: + lis r4, (CFG_IMMR + 0x002fc384)@h + ori r4, r4, (CFG_IMMR + 0x002fc384)@l + lis r3, (0x55ccaa33)@h + ori r3, r3, (0x55ccaa33)@l + stw r3, 0(r4) + lis r4, (CFG_IMMR + 0x002fc284)@h + ori r4, r4, (CFG_IMMR + 0x002fc284)@l + lis r3, CFG_PLPRCR@h + ori r3, r3, CFG_PLPRCR@l + stw r3, 0(r4) + addis r3,0,0x0 + ori r3,r3,0xA000 + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + blr +pll_prog_code_end: + nop + blr +#endif diff --git a/cpu/mpc5xx/traps.c b/cpu/mpc5xx/traps.c new file mode 100644 index 0000000..14fd59e --- /dev/null +++ b/cpu/mpc5xx/traps.c @@ -0,0 +1,230 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler)(struct pt_regs *) = 0; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint(struct pt_regs *); +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. +*/ +#define END_OF_MEM 0x0001000 + + +/* + * Print stack backtrace + */ +void print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +/* + * Print current registers + */ +void show_regs(struct pt_regs * regs) +{ + int i; + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +/* + * General exception handler routine + */ +void _exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +/* + * Machine check exception handler routine + */ +void MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal\n"); + break; + case (0x80000000>>13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + printf("Data parity signal\n"); + break; + case (0x80000000>>15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +/* + * Alignment exception handler routine + */ +void AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +/* + * Program check exception handler routine + */ +void ProgramCheckException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +/* + * Software emulation exception handler routine + */ +void SoftEmuException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + + +/* + * Unknown exception handler routine + */ +void UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +/* + * Debug exception handler routine + */ +void DebugException(struct pt_regs *regs) +{ + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); +#endif +} diff --git a/cpu/mpc5xxx/Makefile b/cpu/mpc5xxx/Makefile new file mode 100644 index 0000000..a97b625 --- /dev/null +++ b/cpu/mpc5xxx/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o +OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \ + loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o + +all: .depend $(START) $(ASOBJS) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(ASOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk new file mode 100644 index 0000000..ecd94e9 --- /dev/null +++ b/cpu/mpc5xxx/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \ + -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c new file mode 100644 index 0000000..2d695d1 --- /dev/null +++ b/cpu/mpc5xxx/cpu.c @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code for the MPC5xxx CPUs + */ + +#include +#include +#include +#include +#include + +int checkcpu (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong clock = gd->cpu_clk; + char buf[32]; +#ifndef CONFIG_MGT5100 + uint svr; +#endif + + puts ("CPU: "); + +#ifdef CONFIG_MGT5100 + puts (CPU_ID_STR); + printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID); +#else + svr = get_svr (); + switch (SVR_VER (svr)) { + case SVR_MPC5200: + printf ("MPC5200"); + break; + default: + printf ("MPC52?? (SVR %08x)", svr); + break; + } + + printf (" v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr)); +#endif + + printf (" at %s MHz\n", strmhz (buf, clock)); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +int +do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong msr; + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* Charge the watchdog timer */ + *(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f; + *(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */ + while(1); + + return 1; + +} + +/* ------------------------------------------------------------------------- */ + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + * + */ +unsigned long get_tbclk (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong tbclk; + + tbclk = (gd->bus_clk + 3L) / 4L; + + return (tbclk); +} + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c new file mode 100644 index 0000000..3df0050 --- /dev/null +++ b/cpu/mpc5xxx/cpu_init.c @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers. + */ +void cpu_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long addecr = (1 << 25); /* Boot_CS */ +#if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100) + addecr |= (1 << 22); /* SDRAM enable */ +#endif + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* + * Memory Controller: configure chip selects and enable them + */ +#if defined(CFG_BOOTCS_START) && defined(CFG_BOOTCS_SIZE) + *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CFG_BOOTCS_START); + *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CFG_BOOTCS_START, + CFG_BOOTCS_SIZE); +#endif +#if defined(CFG_BOOTCS_CFG) + *(vu_long *)MPC5XXX_BOOTCS_CFG = CFG_BOOTCS_CFG; +#endif + +#if defined(CFG_CS0_START) && defined(CFG_CS0_SIZE) + *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_CS0_START); + *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_CS0_START, CFG_CS0_SIZE); + /* CS0 and BOOT_CS cannot be enabled at once. */ + /* addecr |= (1 << 16); */ +#endif +#if defined(CFG_CS0_CFG) + *(vu_long *)MPC5XXX_CS0_CFG = CFG_CS0_CFG; +#endif + +#if defined(CFG_CS1_START) && defined(CFG_CS1_SIZE) + *(vu_long *)MPC5XXX_CS1_START = START_REG(CFG_CS1_START); + *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CFG_CS1_START, CFG_CS1_SIZE); + addecr |= (1 << 17); +#endif +#if defined(CFG_CS1_CFG) + *(vu_long *)MPC5XXX_CS1_CFG = CFG_CS1_CFG; +#endif + +#if defined(CFG_CS2_START) && defined(CFG_CS2_SIZE) + *(vu_long *)MPC5XXX_CS2_START = START_REG(CFG_CS2_START); + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, CFG_CS2_SIZE); + addecr |= (1 << 18); +#endif +#if defined(CFG_CS2_CFG) + *(vu_long *)MPC5XXX_CS2_CFG = CFG_CS2_CFG; +#endif + +#if defined(CFG_CS3_START) && defined(CFG_CS3_SIZE) + *(vu_long *)MPC5XXX_CS3_START = START_REG(CFG_CS3_START); + *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CFG_CS3_START, CFG_CS3_SIZE); + addecr |= (1 << 19); +#endif +#if defined(CFG_CS3_CFG) + *(vu_long *)MPC5XXX_CS3_CFG = CFG_CS3_CFG; +#endif + +#if defined(CFG_CS4_START) && defined(CFG_CS4_SIZE) + *(vu_long *)MPC5XXX_CS4_START = START_REG(CFG_CS4_START); + *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CFG_CS4_START, CFG_CS4_SIZE); + addecr |= (1 << 20); +#endif +#if defined(CFG_CS4_CFG) + *(vu_long *)MPC5XXX_CS4_CFG = CFG_CS4_CFG; +#endif + +#if defined(CFG_CS5_START) && defined(CFG_CS5_SIZE) + *(vu_long *)MPC5XXX_CS5_START = START_REG(CFG_CS5_START); + *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CFG_CS5_START, CFG_CS5_SIZE); + addecr |= (1 << 21); +#endif +#if defined(CFG_CS5_CFG) + *(vu_long *)MPC5XXX_CS5_CFG = CFG_CS5_CFG; +#endif + +#if defined(CONFIG_MPC5200) + addecr |= 1; +#if defined(CFG_CS6_START) && defined(CFG_CS6_SIZE) + *(vu_long *)MPC5XXX_CS6_START = START_REG(CFG_CS6_START); + *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CFG_CS6_START, CFG_CS6_SIZE); + addecr |= (1 << 26); +#endif +#if defined(CFG_CS6_CFG) + *(vu_long *)MPC5XXX_CS6_CFG = CFG_CS6_CFG; +#endif + +#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE) + *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START); + *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE); + addecr |= (1 << 27); +#endif +#if defined(CFG_CS7_CFG) + *(vu_long *)MPC5XXX_CS7_CFG = CFG_CS7_CFG; +#endif + +#if defined(CFG_CS_BURST) + *(vu_long *)MPC5XXX_CS_BURST = CFG_CS_BURST; +#endif +#if defined(CFG_CS_DEADCYCLE) + *(vu_long *)MPC5XXX_CS_DEADCYCLE = CFG_CS_DEADCYCLE; +#endif +#endif /* CONFIG_MPC5200 */ + + /* Enable chip selects */ + *(vu_long *)MPC5XXX_ADDECR = addecr; + *(vu_long *)MPC5XXX_CS_CTRL = (1 << 24); + + /* Setup pin multiplexing */ +#if defined(CFG_GPS_PORT_CONFIG) + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CFG_GPS_PORT_CONFIG; +#endif + +#if defined(CONFIG_MPC5200) + /* enable timebase */ + *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13); + +# if defined(CFG_IPBSPEED_133) + /* Motorola reports IPB should better run at 133 MHz. */ + *(vu_long *)MPC5XXX_ADDECR |= 1; + /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ + addecr = *(vu_long *)MPC5XXX_CDM_CFG; + addecr &= ~0x103; +# if defined(CFG_PCISPEED_66) + /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ + addecr |= 0x01; +# else + /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ + addecr |= 0x02; +# endif /* CFG_PCISPEED_66 */ + *(vu_long *)MPC5XXX_CDM_CFG = addecr; +# endif /* CFG_IPBSPEED_133 */ + /* Configure the XLB Arbiter */ + *(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff; + *(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111; + +# if defined(CFG_XLB_PIPELINING) + /* Enable piplining */ + *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31); +# endif +#endif /* CONFIG_MPC5200 */ +} + +/* + * initialize higher level parts of CPU like time base and timers + */ +int cpu_init_r (void) +{ + /* mask all interrupts */ +#if defined(CONFIG_MGT5100) + *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xfffffc00; +#elif defined(CONFIG_MPC5200) + *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xffffff00; +#endif + *(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff; + *(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00; + /* route critical ints to normal ints */ + *(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001; + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) + /* load FEC microcode */ + loadtask(0, 2); +#endif + + return (0); +} diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c new file mode 100644 index 0000000..86c8ce6 --- /dev/null +++ b/cpu/mpc5xxx/fec.c @@ -0,0 +1,1043 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on mpc4200fec.c, + * (C) Copyright Motorola, Inc., 2000 + */ + +#include +#include +#include +#include +#include +#include "sdma.h" +#include "fec.h" + +/* #define DEBUG 0x28 */ + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_MPC5xxx_FEC) + +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#if (DEBUG & 0x60) +static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec); +static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec); +#endif /* DEBUG */ + +#if (DEBUG & 0x40) +static uint32 local_crc32(char *string, unsigned int crc_value, int len); +#endif + +typedef struct { + uint8 data[1500]; /* actual data */ + int length; /* actual length */ + int used; /* buffer in use or not */ + uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ +} NBUF; + +int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal); +int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); + +/********************************************************************/ +#if (DEBUG & 0x2) +static void mpc5xxx_fec_phydump (char *devname) +{ + uint16 phyStatus, i; + uint8 phyAddr = CONFIG_PHY_ADDR; + uint8 reg_mask[] = { +#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */ + /* regs to print: 0...7, 16...19, 21, 23, 24 */ + 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, +#else + /* regs to print: 0...8, 16...20 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +#endif + }; + + for (i = 0; i < 32; i++) { + if (reg_mask[i]) { + miiphy_read(devname, phyAddr, i, &phyStatus); + printf("Mii reg %d: 0x%04x\n", i, phyStatus); + } + } +} +#endif + +/********************************************************************/ +static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec) +{ + int ix; + char *data; + static int once = 0; + + for (ix = 0; ix < FEC_RBD_NUM; ix++) { + if (!once) { + data = (char *)malloc(FEC_MAX_PKT_SIZE); + if (data == NULL) { + printf ("RBD INIT FAILED\n"); + return -1; + } + fec->rbdBase[ix].dataPointer = (uint32)data; + } + fec->rbdBase[ix].status = FEC_RBD_EMPTY; + fec->rbdBase[ix].dataLength = 0; + } + once ++; + + /* + * have the last RBD to close the ring + */ + fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP; + fec->rbdIndex = 0; + + return 0; +} + +/********************************************************************/ +static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec) +{ + int ix; + + for (ix = 0; ix < FEC_TBD_NUM; ix++) { + fec->tbdBase[ix].status = 0; + } + + /* + * Have the last TBD to close the ring + */ + fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP; + + /* + * Initialize some indices + */ + fec->tbdIndex = 0; + fec->usedTbdIndex = 0; + fec->cleanTbdNum = FEC_TBD_NUM; +} + +/********************************************************************/ +static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd) +{ + /* + * Reset buffer descriptor as empty + */ + if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) + pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); + else + pRbd->status = FEC_RBD_EMPTY; + + pRbd->dataLength = 0; + + /* + * Now, we have an empty RxBD, restart the SmartDMA receive task + */ + SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); + + /* + * Increment BD count + */ + fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; +} + +/********************************************************************/ +static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec) +{ + volatile FEC_TBD *pUsedTbd; + +#if (DEBUG & 0x1) + printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", + fec->cleanTbdNum, fec->usedTbdIndex); +#endif + + /* + * process all the consumed TBDs + */ + while (fec->cleanTbdNum < FEC_TBD_NUM) { + pUsedTbd = &fec->tbdBase[fec->usedTbdIndex]; + if (pUsedTbd->status & FEC_TBD_READY) { +#if (DEBUG & 0x20) + printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum); +#endif + return; + } + + /* + * clean this buffer descriptor + */ + if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) + pUsedTbd->status = FEC_TBD_WRAP; + else + pUsedTbd->status = 0; + + /* + * update some indeces for a correct handling of the TBD ring + */ + fec->cleanTbdNum++; + fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; + } +} + +/********************************************************************/ +static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac) +{ + uint8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + uint32 crc = 0xffffffff; /* initial value */ + + /* + * The algorithm used is the following: + * we loop on each of the six bytes of the provided address, + * and we compute the CRC by left-shifting the previous + * value by one position, so that each bit in the current + * byte of the address may contribute the calculation. If + * the latter and the MSB in the CRC are different, then + * the CRC value so computed is also ex-ored with the + * "polynomium generator". The current byte of the address + * is also shifted right by one bit at each iteration. + * This is because the CRC generatore in hardware is implemented + * as a shift-register with as many ex-ores as the radixes + * in the polynomium. This suggests that we represent the + * polynomiumm itself as a 32-bit constant. + */ + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* + * Set individual hash table register + */ + if (crc >= 32) { + fec->eth->iaddr1 = (1 << (crc - 32)); + fec->eth->iaddr2 = 0; + } else { + fec->eth->iaddr1 = 0; + fec->eth->iaddr2 = (1 << crc); + } + + /* + * Set physical address + */ + fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; + fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; +} + +/********************************************************************/ +static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) +{ + DECLARE_GLOBAL_DATA_PTR; + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; + +#if (DEBUG & 0x1) + printf ("mpc5xxx_fec_init... Begin\n"); +#endif + + /* + * Initialize RxBD/TxBD rings + */ + mpc5xxx_fec_rbd_init(fec); + mpc5xxx_fec_tbd_init(fec); + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + /* + * Set FEC-Lite receive control register(R_CNTRL): + */ + if (fec->xcv_type == SEVENWIRE) { + /* + * Frame length=1518; 7-wire mode + */ + fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */ + } else { + /* + * Frame length=1518; MII mode; + */ + fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */ + } + + fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */ + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + */ + fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ + } + + /* + * Set Opcode/Pause Duration Register + */ + fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */ + + /* + * Set Rx FIFO alarm and granularity value + */ + fec->eth->rfifo_cntrl = 0x0c000000 + | (fec->eth->rfifo_cntrl & ~0x0f000000); + fec->eth->rfifo_alarm = 0x0000030c; +#if (DEBUG & 0x22) + if (fec->eth->rfifo_status & 0x00700000 ) { + printf("mpc5xxx_fec_init() RFIFO error\n"); + } +#endif + + /* + * Set Tx FIFO granularity value + */ + fec->eth->tfifo_cntrl = 0x0c000000 + | (fec->eth->tfifo_cntrl & ~0x0f000000); +#if (DEBUG & 0x2) + printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status); + printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm); +#endif + + /* + * Set transmit fifo watermark register(X_WMRK), default = 64 + */ + fec->eth->tfifo_alarm = 0x00000080; + fec->eth->x_wmrk = 0x2; + + /* + * Set individual address filter for unicast address + * and set physical address registers. + */ + mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr); + + /* + * Set multicast address filter + */ + fec->eth->gaddr1 = 0x00000000; + fec->eth->gaddr2 = 0x00000000; + + /* + * Turn ON cheater FSM: ???? + */ + fec->eth->xmit_fsm = 0x03000000; + +#if defined(CONFIG_MPC5200) + /* + * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't + * work w/ the current receive task. + */ + sdma->PtdCntrl |= 0x00000001; +#endif + + /* + * Set priority of different initiators + */ + sdma->IPR0 = 7; /* always */ + sdma->IPR3 = 6; /* Eth RX */ + sdma->IPR4 = 5; /* Eth Tx */ + + /* + * Clear SmartDMA task interrupt pending bits + */ + SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO); + + /* + * Initialize SmartDMA parameters stored in SRAM + */ + *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase; + *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase; + *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase; + *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase; + + /* + * Enable FEC-Lite controller + */ + fec->eth->ecntrl |= 0x00000006; + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc5xxx_fec_phydump (); +#endif + + /* + * Enable SmartDMA receive task + */ + SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); + +#if (DEBUG & 0x1) + printf("mpc5xxx_fec_init... Done \n"); +#endif + + return 1; +} + +/********************************************************************/ +static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) +{ + DECLARE_GLOBAL_DATA_PTR; + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ + +#if (DEBUG & 0x1) + printf ("mpc5xxx_fec_init_phy... Begin\n"); +#endif + + /* + * Initialize GPIO pins + */ + if (fec->xcv_type == SEVENWIRE) { + /* 10MBit with 7-wire operation */ +#if defined(CONFIG_TOTAL5200) + /* 7-wire and USB2 on Ethernet */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000; +#else /* !CONFIG_TOTAL5200 */ + /* 7-wire only */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000; +#endif /* CONFIG_TOTAL5200 */ + } else { + /* 100MBit with MD operation */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000; + } + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + */ + fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ + } + + if (fec->xcv_type != SEVENWIRE) { + /* + * Initialize PHY(LXT971A): + * + * Generally, on power up, the LXT971A reads its configuration + * pins to check for forced operation, If not cofigured for + * forced operation, it uses auto-negotiation/parallel detection + * to automatically determine line operating conditions. + * If the PHY device on the other side of the link supports + * auto-negotiation, the LXT971A auto-negotiates with it + * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not + * support auto-negotiation, the LXT971A automatically detects + * the presence of either link pulses(10Mbps PHY) or Idle + * symbols(100Mbps) and sets its operating conditions accordingly. + * + * When auto-negotiation is controlled by software, the following + * steps are recommended. + * + * Note: + * The physical address is dependent on hardware configuration. + * + */ + int timeout = 1; + uint16 phyStatus; + + /* + * Reset PHY, then delay 300ns + */ + miiphy_write(dev->name, phyAddr, 0x0, 0x8000); + udelay(1000); + + if (fec->xcv_type == MII10) { + /* + * Force 10Base-T, FDX operation + */ +#if (DEBUG & 0x2) + printf("Forcing 10 Mbps ethernet link... "); +#endif + miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); + /* + miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100); + */ + miiphy_write(dev->name, phyAddr, 0x0, 0x0180); + + timeout = 20; + do { /* wait for link status to go down */ + udelay(10000); + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf("hmmm, should not have waited..."); +#endif + break; + } + miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf("="); +#endif + } while ((phyStatus & 0x0004)); /* !link up */ + + timeout = 1000; + do { /* wait for link status to come back up */ + udelay(10000); + if ((timeout--) == 0) { + printf("failed. Link is down.\n"); + break; + } + miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf("+"); +#endif + } while (!(phyStatus & 0x0004)); /* !link up */ + +#if (DEBUG & 0x2) + printf ("done.\n"); +#endif + } else { /* MII100 */ + /* + * Set the auto-negotiation advertisement register bits + */ + miiphy_write(dev->name, phyAddr, 0x4, 0x01e1); + + /* + * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation + */ + miiphy_write(dev->name, phyAddr, 0x0, 0x1200); + + /* + * Wait for AN completion + */ + timeout = 5000; + do { + udelay(1000); + + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf("PHY auto neg 0 failed...\n"); +#endif + return -1; + } + + if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) { +#if (DEBUG & 0x2) + printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus); +#endif + return -1; + } + } while (!(phyStatus & 0x0004)); + +#if (DEBUG & 0x2) + printf("PHY auto neg complete! \n"); +#endif + } + + } + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc5xxx_fec_phydump (dev->name); +#endif + + +#if (DEBUG & 0x1) + printf("mpc5xxx_fec_init_phy... Done \n"); +#endif + + return 1; +} + +/********************************************************************/ +static void mpc5xxx_fec_halt(struct eth_device *dev) +{ +#if defined(CONFIG_MPC5200) + struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; +#endif + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + int counter = 0xffff; + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc5xxx_fec_phydump (); +#endif + + /* + * mask FEC chip interrupts + */ + fec->eth->imask = 0; + + /* + * issue graceful stop command to the FEC transmitter if necessary + */ + fec->eth->x_cntrl |= 0x00000001; + + /* + * wait for graceful stop to register + */ + while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ; + + /* + * Disable SmartDMA tasks + */ + SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO); + SDMA_TASK_DISABLE (FEC_RECV_TASK_NO); + +#if defined(CONFIG_MPC5200) + /* + * Turn on COMM bus prefetch in the MGT5200 BestComm after we're + * done. It doesn't work w/ the current receive task. + */ + sdma->PtdCntrl &= ~0x00000001; +#endif + + /* + * Disable the Ethernet Controller + */ + fec->eth->ecntrl &= 0xfffffffd; + + /* + * Clear FIFO status registers + */ + fec->eth->rfifo_status &= 0x00700000; + fec->eth->tfifo_status &= 0x00700000; + + fec->eth->reset_cntrl = 0x01000000; + + /* + * Issue a reset command to the FEC chip + */ + fec->eth->ecntrl |= 0x1; + + /* + * wait at least 16 clock cycles + */ + udelay(10); + +#if (DEBUG & 0x3) + printf("Ethernet task stopped\n"); +#endif +} + +#if (DEBUG & 0x60) +/********************************************************************/ + +static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec) +{ + uint16 phyAddr = CONFIG_PHY_ADDR; + uint16 phyStatus; + + if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr) + || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) { + + miiphy_read(devname, phyAddr, 0x1, &phyStatus); + printf("\nphyStatus: 0x%04x\n", phyStatus); + printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); + printf("ievent: 0x%08x\n", fec->eth->ievent); + printf("x_status: 0x%08x\n", fec->eth->x_status); + printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status); + + printf(" control 0x%08x\n", fec->eth->tfifo_cntrl); + printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr); + printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr); + printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm); + printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr); + printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr); + } +} + +static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec) +{ + uint16 phyAddr = CONFIG_PHY_ADDR; + uint16 phyStatus; + + if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr) + || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) { + + miiphy_read(devname, phyAddr, 0x1, &phyStatus); + printf("\nphyStatus: 0x%04x\n", phyStatus); + printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); + printf("ievent: 0x%08x\n", fec->eth->ievent); + printf("x_status: 0x%08x\n", fec->eth->x_status); + printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status); + + printf(" control 0x%08x\n", fec->eth->rfifo_cntrl); + printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr); + printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr); + printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm); + printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr); + printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr); + } +} +#endif /* DEBUG */ + +/********************************************************************/ + +static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data, + int data_length) +{ + /* + * This routine transmits one frame. This routine only accepts + * 6-byte Ethernet addresses. + */ + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + volatile FEC_TBD *pTbd; + +#if (DEBUG & 0x20) + printf("tbd status: 0x%04x\n", fec->tbdBase[0].status); + tfifo_print(dev->name, fec); +#endif + + /* + * Clear Tx BD ring at first + */ + mpc5xxx_fec_tbd_scrub(fec); + + /* + * Check for valid length of data. + */ + if ((data_length > 1500) || (data_length <= 0)) { + return -1; + } + + /* + * Check the number of vacant TxBDs. + */ + if (fec->cleanTbdNum < 1) { +#if (DEBUG & 0x20) + printf("No available TxBDs ...\n"); +#endif + return -1; + } + + /* + * Get the first TxBD to send the mac header + */ + pTbd = &fec->tbdBase[fec->tbdIndex]; + pTbd->dataLength = data_length; + pTbd->dataPointer = (uint32)eth_data; + pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; + fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; + +#if (DEBUG & 0x100) + printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex); +#endif + + /* + * Kick the MII i/f + */ + if (fec->xcv_type != SEVENWIRE) { + uint16 phyStatus; + miiphy_read(dev->name, 0, 0x1, &phyStatus); + } + + /* + * Enable SmartDMA transmit task + */ + +#if (DEBUG & 0x20) + tfifo_print(dev->name, fec); +#endif + SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO); +#if (DEBUG & 0x20) + tfifo_print(dev->name, fec); +#endif +#if (DEBUG & 0x8) + printf( "+" ); +#endif + + fec->cleanTbdNum -= 1; + +#if (DEBUG & 0x129) && (DEBUG & 0x80000000) + printf ("smartDMA ethernet Tx task enabled\n"); +#endif + /* + * wait until frame is sent . + */ + while (pTbd->status & FEC_TBD_READY) { + udelay(10); +#if (DEBUG & 0x8) + printf ("TDB status = %04x\n", pTbd->status); +#endif + } + + return 0; +} + + +/********************************************************************/ +static int mpc5xxx_fec_recv(struct eth_device *dev) +{ + /* + * This command pulls one frame from the card + */ + mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; + volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex]; + unsigned long ievent; + int frame_length, len = 0; + NBUF *frame; + uchar buff[FEC_MAX_PKT_SIZE]; + +#if (DEBUG & 0x1) + printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex); +#endif +#if (DEBUG & 0x8) + printf( "-" ); +#endif + + /* + * Check if any critical events have happened + */ + ievent = fec->eth->ievent; + fec->eth->ievent = ievent; + if (ievent & 0x20060000) { + /* BABT, Rx/Tx FIFO errors */ + mpc5xxx_fec_halt(dev); + mpc5xxx_fec_init(dev, NULL); + return 0; + } + if (ievent & 0x80000000) { + /* Heartbeat error */ + fec->eth->x_cntrl |= 0x00000001; + } + if (ievent & 0x10000000) { + /* Graceful stop complete */ + if (fec->eth->x_cntrl & 0x00000001) { + mpc5xxx_fec_halt(dev); + fec->eth->x_cntrl &= ~0x00000001; + mpc5xxx_fec_init(dev, NULL); + } + } + + if (!(pRbd->status & FEC_RBD_EMPTY)) { + if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) && + ((pRbd->dataLength - 4) > 14)) { + + /* + * Get buffer address and size + */ + frame = (NBUF *)pRbd->dataPointer; + frame_length = pRbd->dataLength - 4; + +#if (DEBUG & 0x20) + { + int i; + printf("recv data hdr:"); + for (i = 0; i < 14; i++) + printf("%x ", *(frame->head + i)); + printf("\n"); + } +#endif + /* + * Fill the buffer and pass it to upper layers + */ + memcpy(buff, frame->head, 14); + memcpy(buff + 14, frame->data, frame_length); + NetReceive(buff, frame_length); + len = frame_length; + } + /* + * Reset buffer descriptor as empty + */ + mpc5xxx_fec_rbd_clean(fec, pRbd); + } + SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); + return len; +} + + +/********************************************************************/ +int mpc5xxx_fec_initialize(bd_t * bis) +{ + mpc5xxx_fec_priv *fec; + struct eth_device *dev; + char *tmp, *end; + char env_enetaddr[6]; + int i; + + fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec)); + dev = (struct eth_device *)malloc(sizeof(*dev)); + memset(dev, 0, sizeof *dev); + + fec->eth = (ethernet_regs *)MPC5XXX_FEC; + fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; + fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); +#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \ + defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \ + defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \ + defined(CONFIG_TQM5200) || defined(CONFIG_O2DNT) +# ifndef CONFIG_FEC_10MBIT + fec->xcv_type = MII100; +# else + fec->xcv_type = MII10; +# endif +#elif defined(CONFIG_TOTAL5200) + fec->xcv_type = SEVENWIRE; +#else +#error fec->xcv_type not initialized. +#endif + + dev->priv = (void *)fec; + dev->iobase = MPC5XXX_FEC; + dev->init = mpc5xxx_fec_init; + dev->halt = mpc5xxx_fec_halt; + dev->send = mpc5xxx_fec_send; + dev->recv = mpc5xxx_fec_recv; + + sprintf(dev->name, "FEC ETHERNET"); + eth_register(dev); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register (dev->name, + fec5xxx_miiphy_read, fec5xxx_miiphy_write); +#endif + + /* + * Try to set the mac address now. The fec mac address is + * a garbage after reset. When not using fec for booting + * the Linux fec driver will try to work with this garbage. + */ + tmp = getenv("ethaddr"); + if (tmp) { + for (i=0; i<6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + mpc5xxx_fec_set_hwaddr(fec, env_enetaddr); + } + + mpc5xxx_fec_init_phy(dev, bis); + + return 1; +} + +/* MII-interface related functions */ +/********************************************************************/ +int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) +{ + ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + /* + * reading from any PHY's register is done by properly + * programming the FEC's MII data register. + */ + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg); + + /* + * wait for the related interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Read MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear mii interrupt bit + */ + eth->ievent = 0x00800000; + + /* + * it's now safe to read the PHY's register + */ + *retVal = (uint16) eth->mii_data; + + return 0; +} + +/********************************************************************/ +int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) +{ + ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | + FEC_MII_DATA_TA | phy | reg | data); + + /* + * wait for the MII interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Write MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear MII interrupt bit + */ + eth->ievent = 0x00800000; + + return 0; +} + +#if (DEBUG & 0x40) +static uint32 local_crc32(char *string, unsigned int crc_value, int len) +{ + int i; + char c; + unsigned int crc, count; + + /* + * crc32 algorithm + */ + /* + * crc = 0xffffffff; * The initialized value should be 0xffffffff + */ + crc = crc_value; + + for (i = len; --i >= 0;) { + c = *string++; + for (count = 0; count < 8; count++) { + if ((c & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + c >>= 1; + } + } + + /* + * In big endian system, do byte swaping for crc value + */ + /**/ return crc; +} +#endif /* DEBUG */ + +#endif /* CONFIG_MPC5xxx_FEC */ diff --git a/cpu/mpc5xxx/fec.h b/cpu/mpc5xxx/fec.h new file mode 100644 index 0000000..81756a5 --- /dev/null +++ b/cpu/mpc5xxx/fec.h @@ -0,0 +1,286 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on mpc4200fec.h + * (C) Copyright Motorola, Inc., 2000 + * + * odin ethernet header file + */ + +#ifndef __MPC5XXX_FEC_H +#define __MPC5XXX_FEC_H + +#include +#include +#include "sdma.h" + +typedef unsigned long uint32; +typedef unsigned short uint16; +typedef unsigned char uint8; + +typedef struct ethernet_register_set { + +/* [10:2]addr = 00 */ + +/* Control and status Registers (offset 000-1FF) */ + + volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ + volatile uint32 ievent; /* MBAR_ETH + 0x004 */ + volatile uint32 imask; /* MBAR_ETH + 0x008 */ + + volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ + volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ + volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ + volatile uint32 r_des_active_cl; /* MBAR_ETH + 0x018 */ + volatile uint32 x_des_active_cl; /* MBAR_ETH + 0x01C */ + volatile uint32 ivent_set; /* MBAR_ETH + 0x020 */ + volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ + + volatile uint32 RES1[6]; /* MBAR_ETH + 0x028-03C */ + volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ + volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ + volatile uint32 mii_status; /* MBAR_ETH + 0x048 */ + + volatile uint32 RES2[5]; /* MBAR_ETH + 0x04C-05C */ + volatile uint32 mib_data; /* MBAR_ETH + 0x060 */ + volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ + + volatile uint32 RES3[6]; /* MBAR_ETH + 0x068-7C */ + volatile uint32 r_activate; /* MBAR_ETH + 0x080 */ + volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ + volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ + volatile uint32 r_data; /* MBAR_ETH + 0x08C */ + volatile uint32 ar_done; /* MBAR_ETH + 0x090 */ + volatile uint32 r_test; /* MBAR_ETH + 0x094 */ + volatile uint32 r_mib; /* MBAR_ETH + 0x098 */ + volatile uint32 r_da_low; /* MBAR_ETH + 0x09C */ + volatile uint32 r_da_high; /* MBAR_ETH + 0x0A0 */ + + volatile uint32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */ + volatile uint32 x_activate; /* MBAR_ETH + 0x0C0 */ + volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ + volatile uint32 backoff; /* MBAR_ETH + 0x0C8 */ + volatile uint32 x_data; /* MBAR_ETH + 0x0CC */ + volatile uint32 x_status; /* MBAR_ETH + 0x0D0 */ + volatile uint32 x_mib; /* MBAR_ETH + 0x0D4 */ + volatile uint32 x_test; /* MBAR_ETH + 0x0D8 */ + volatile uint32 fdxfc_da1; /* MBAR_ETH + 0x0DC */ + volatile uint32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */ + volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ + volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ + volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ + + volatile uint32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */ + volatile uint32 instr_reg; /* MBAR_ETH + 0x100 */ + volatile uint32 context_reg; /* MBAR_ETH + 0x104 */ + volatile uint32 test_cntrl; /* MBAR_ETH + 0x108 */ + volatile uint32 acc_reg; /* MBAR_ETH + 0x10C */ + volatile uint32 ones; /* MBAR_ETH + 0x110 */ + volatile uint32 zeros; /* MBAR_ETH + 0x114 */ + volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */ + volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */ + volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */ + volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */ + volatile uint32 random; /* MBAR_ETH + 0x128 */ + volatile uint32 rand1; /* MBAR_ETH + 0x12C */ + volatile uint32 tmp; /* MBAR_ETH + 0x130 */ + + volatile uint32 RES6[3]; /* MBAR_ETH + 0x134-13C */ + volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */ + volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */ + volatile uint32 fcntrl; /* MBAR_ETH + 0x148 */ + volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ + volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ + volatile uint32 r_count; /* MBAR_ETH + 0x154 */ + volatile uint32 r_lag; /* MBAR_ETH + 0x158 */ + volatile uint32 r_read; /* MBAR_ETH + 0x15C */ + volatile uint32 r_write; /* MBAR_ETH + 0x160 */ + volatile uint32 x_count; /* MBAR_ETH + 0x164 */ + volatile uint32 x_lag; /* MBAR_ETH + 0x168 */ + volatile uint32 x_retry; /* MBAR_ETH + 0x16C */ + volatile uint32 x_write; /* MBAR_ETH + 0x170 */ + volatile uint32 x_read; /* MBAR_ETH + 0x174 */ + + volatile uint32 RES7[2]; /* MBAR_ETH + 0x178-17C */ + volatile uint32 fm_cntrl; /* MBAR_ETH + 0x180 */ + volatile uint32 rfifo_data; /* MBAR_ETH + 0x184 */ + volatile uint32 rfifo_status; /* MBAR_ETH + 0x188 */ + volatile uint32 rfifo_cntrl; /* MBAR_ETH + 0x18C */ + volatile uint32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */ + volatile uint32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */ + volatile uint32 rfifo_alarm; /* MBAR_ETH + 0x198 */ + volatile uint32 rfifo_rdptr; /* MBAR_ETH + 0x19C */ + volatile uint32 rfifo_wrptr; /* MBAR_ETH + 0x1A0 */ + volatile uint32 tfifo_data; /* MBAR_ETH + 0x1A4 */ + volatile uint32 tfifo_status; /* MBAR_ETH + 0x1A8 */ + volatile uint32 tfifo_cntrl; /* MBAR_ETH + 0x1AC */ + volatile uint32 tfifo_lrf_ptr; /* MBAR_ETH + 0x1B0 */ + volatile uint32 tfifo_lwf_ptr; /* MBAR_ETH + 0x1B4 */ + volatile uint32 tfifo_alarm; /* MBAR_ETH + 0x1B8 */ + volatile uint32 tfifo_rdptr; /* MBAR_ETH + 0x1BC */ + volatile uint32 tfifo_wrptr; /* MBAR_ETH + 0x1C0 */ + + volatile uint32 reset_cntrl; /* MBAR_ETH + 0x1C4 */ + volatile uint32 xmit_fsm; /* MBAR_ETH + 0x1C8 */ + + volatile uint32 RES8[3]; /* MBAR_ETH + 0x1CC-1D4 */ + volatile uint32 rdes_data0; /* MBAR_ETH + 0x1D8 */ + volatile uint32 rdes_data1; /* MBAR_ETH + 0x1DC */ + volatile uint32 r_length; /* MBAR_ETH + 0x1E0 */ + volatile uint32 x_length; /* MBAR_ETH + 0x1E4 */ + volatile uint32 x_addr; /* MBAR_ETH + 0x1E8 */ + volatile uint32 cdes_data; /* MBAR_ETH + 0x1EC */ + volatile uint32 status; /* MBAR_ETH + 0x1F0 */ + volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */ + volatile uint32 des_cmnd; /* MBAR_ETH + 0x1F8 */ + volatile uint32 data; /* MBAR_ETH + 0x1FC */ + +/* MIB COUNTERS (Offset 200-2FF) */ + + volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */ + volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */ + volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ + volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ + volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ + volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ + volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ + volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */ + volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */ + volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */ + volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */ + volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ + volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ + volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ + volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ + volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ + volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ + volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */ + volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */ + volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ + volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */ + volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ + volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */ + volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ + volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */ + volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ + volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ + volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ + volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */ + volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ + + volatile uint32 RES9[2]; /* MBAR_ETH + 0x278-27C */ + volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */ + volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */ + volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ + volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ + volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ + volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ + volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ + volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */ + volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ + + volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ + + volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ + volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ + volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ + volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ + volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ + volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ + volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ + volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ + volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ + volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ + volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ + volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ + volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */ + volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */ + volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ + + volatile uint32 RES10[6]; /* MBAR_ETH + 0x2E4-2FC */ + + volatile uint32 RES11[64]; /* MBAR_ETH + 0x300-3FF */ +} ethernet_regs; + +/* Receive & Transmit Buffer Descriptor definitions */ +typedef struct BufferDescriptor { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_RBD; +typedef struct { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_TBD; + +/* private structure */ +typedef enum { + SEVENWIRE, /* 7-wire */ + MII10, /* MII 10Mbps */ + MII100 /* MII 100Mbps */ +} xceiver_type; + +typedef struct { + ethernet_regs *eth; + xceiver_type xcv_type; /* transceiver type */ + FEC_RBD *rbdBase; /* RBD ring */ + FEC_TBD *tbdBase; /* TBD ring */ + uint16 rbdIndex; /* next receive BD to read */ + uint16 tbdIndex; /* next transmit BD to send */ + uint16 usedTbdIndex; /* next transmit BD to clean */ + uint16 cleanTbdNum; /* the number of available transmit BDs */ +} mpc5xxx_fec_priv; + +/* Ethernet parameter area */ +#define FEC_TBD_BASE (FEC_PARAM_BASE + 0x00) +#define FEC_TBD_NEXT (FEC_PARAM_BASE + 0x04) +#define FEC_RBD_BASE (FEC_PARAM_BASE + 0x08) +#define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c) + +/* BD Numer definitions */ +#define FEC_TBD_NUM 48 /* The user can adjust this value */ +#define FEC_RBD_NUM 32 /* The user can adjust this value */ + +/* packet size limit */ +#define FEC_MAX_PKT_SIZE 1536 + +/* RBD bits definitions */ +#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ +#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_RBD_INT 0x1000 /* Interrupt */ +#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ +#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ +#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ +#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ +#define FEC_RBD_LG 0x0020 /* Frame length violation */ +#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ +#define FEC_RBD_SH 0x0008 /* Short frame */ +#define FEC_RBD_CR 0x0004 /* CRC error */ +#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ +#define FEC_RBD_TR 0x0001 /* Frame is truncated */ +#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ + FEC_RBD_OV | FEC_RBD_TR) + +/* TBD bits definitions */ +#define FEC_TBD_READY 0x8000 /* Buffer is ready */ +#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_TBD_INT 0x1000 /* Interrupt */ +#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ +#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ +#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ + +/* MII-related definitios */ +#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ +#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ +#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ +#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ +#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ +#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ +#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ + +#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ +#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ + +#endif /* __MPC5XXX_FEC_H */ diff --git a/cpu/mpc5xxx/firmware_sc_task.impl.S b/cpu/mpc5xxx/firmware_sc_task.impl.S new file mode 100644 index 0000000..b668ee5 --- /dev/null +++ b/cpu/mpc5xxx/firmware_sc_task.impl.S @@ -0,0 +1,364 @@ +/* + * Copyright (C) 2001, Software Center, Motorola China. + * + * This file contains microcode for the FEC controller of the MGT5100 CPU. + */ + +#include + +#if defined(CONFIG_MGT5100) + +/* sas/sccg, gas target */ +.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ +.section smartdmaTaskTable,"aw",@progbits /* Task tables */ +.globl taskTable +taskTable: +.globl scEthernetRecv_Entry +scEthernetRecv_Entry: /* Task 0 */ +.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ +.long scEthernetRecv_TDT - taskTable + 0x000000a4 +.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ +.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ +.long 0x00000000 +.long 0x00000000 +.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ +.long 0xf0000000 +.globl scEthernetXmit_Entry +scEthernetXmit_Entry: /* Task 1 */ +.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ +.long scEthernetXmit_TDT - taskTable + 0x000000d0 +.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ +.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ +.long 0x00000000 +.long 0x00000000 +.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ +.long 0xf0000000 + + +.globl scEthernetRecv_TDT +scEthernetRecv_TDT: /* Task 0 Descriptor Table */ +.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ +.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ +.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ +.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ +.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x010c504c /* 0020: DRD2B1: var4 = EU1(); EU1(var1,var12) */ +.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ +.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ +.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x018c504e /* 0030: DRD2B1: var6 = EU1(); EU1(var1,var14) */ +.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x020c504f /* 0038: DRD2B1: var8 = EU1(); EU1(var1,var15) */ +.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ +.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ +.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ +.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ +.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ +.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ +.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ +.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ +.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ +.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ +.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ +.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ +.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ +.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ +.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ +.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ +.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ +.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ +.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ +.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x080c504c /* 00A0: DRD2B1: idx0 = EU1(); EU1(var1,var12) */ +.long 0x000001f8 /* 00A4(:0): NOP */ + + +.globl scEthernetXmit_TDT +scEthernetXmit_TDT: /* Task 1 Descriptor Table */ +.long 0x80014800 /* 0000: LCDEXT: idx0 = 0xf0004800; ; */ +.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ +.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ +.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ +.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x024c504d /* 0020: DRD2B1: var9 = EU1(); EU1(var1,var13) */ +.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ +.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ +.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ +.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x010c504e /* 0034: DRD2B1: var4 = EU1(); EU1(var1,var14) */ +.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x014c504f /* 003C: DRD2B1: var5 = EU1(); EU1(var1,var15) */ +.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x028c5050 /* 0044: DRD2B1: var10 = EU1(); EU1(var1,var16) */ +.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x018c5051 /* 004C: DRD2B1: var6 = EU1(); EU1(var1,var17) */ +.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x01cc50a1 /* 0058: DRD2B1: var7 = EU1(); EU1(var2,idx1) */ +.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ +.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ +.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ +.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ +.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ +.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ +.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ +.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ +.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ +.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ +.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x60000100 /* 0088: DRD2A: EU0=0 EU1=1 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x0c4c5c4d /* 008C: DRD2B1: *idx1 = EU1(); EU1(*idx1,var13) */ +.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ +.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ +.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ +.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ +.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ +.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ +.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ +.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ +.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x080c504d /* 00CC: DRD2B1: idx0 = EU1(); EU1(var1,var13) */ +.long 0x000001f8 /* 00D0(:0): NOP */ + +.align 8 + +.globl scEthernetRecv_VarTab +scEthernetRecv_VarTab: /* Task 0 Variable Table */ +.long 0x00000000 /* var[0] */ +.long 0x00000000 /* var[1] */ +.long 0x00000000 /* var[2] */ +.long 0x00000000 /* var[3] */ +.long 0x00000000 /* var[4] */ +.long 0x00000000 /* var[5] */ +.long 0x00000000 /* var[6] */ +.long 0x00000000 /* var[7] */ +.long 0x00000000 /* var[8] */ +.long 0xf0004800 /* var[9] */ +.long 0x00000008 /* var[10] */ +.long 0x0000000c /* var[11] */ +.long 0x80000000 /* var[12] */ +.long 0x00000000 /* var[13] */ +.long 0x10000000 /* var[14] */ +.long 0x20000000 /* var[15] */ +.long 0x000005e4 /* var[16] */ +.long 0x0000000e /* var[17] */ +.long 0x000005e0 /* var[18] */ +.long 0x00000004 /* var[19] */ +.long 0x00000000 /* var[20] */ +.long 0x00000000 /* var[21] */ +.long 0x00000000 /* var[22] */ +.long 0x00000000 /* var[23] */ +.long 0x00000000 /* inc[0] */ +.long 0x60000000 /* inc[1] */ +.long 0x20000001 /* inc[2] */ +.long 0x80000000 /* inc[3] */ +.long 0x40000000 /* inc[4] */ +.long 0x00000000 /* inc[5] */ +.long 0x00000000 /* inc[6] */ +.long 0x00000000 /* inc[7] */ + +.align 8 + +.globl scEthernetXmit_VarTab +scEthernetXmit_VarTab: /* Task 1 Variable Table */ +.long 0x00000000 /* var[0] */ +.long 0x00000000 /* var[1] */ +.long 0x00000000 /* var[2] */ +.long 0x00000000 /* var[3] */ +.long 0x00000000 /* var[4] */ +.long 0x00000000 /* var[5] */ +.long 0x00000000 /* var[6] */ +.long 0x00000000 /* var[7] */ +.long 0x00000000 /* var[8] */ +.long 0x00000000 /* var[9] */ +.long 0x00000000 /* var[10] */ +.long 0xf0004800 /* var[11] */ +.long 0x00000000 /* var[12] */ +.long 0x80000000 /* var[13] */ +.long 0x10000000 /* var[14] */ +.long 0x08000000 /* var[15] */ +.long 0x20000000 /* var[16] */ +.long 0x0000ffff /* var[17] */ +.long 0xffffffff /* var[18] */ +.long 0x00000008 /* var[19] */ +.long 0x00000000 /* var[20] */ +.long 0x00000000 /* var[21] */ +.long 0x00000000 /* var[22] */ +.long 0x00000000 /* var[23] */ +.long 0x00000000 /* inc[0] */ +.long 0x60000000 /* inc[1] */ +.long 0x40000000 /* inc[2] */ +.long 0x4000ffff /* inc[3] */ +.long 0xe0000001 /* inc[4] */ +.long 0x80000000 /* inc[5] */ +.long 0x00000000 /* inc[6] */ +.long 0x00000000 /* inc[7] */ + +.align 8 + +.globl scEthernetRecv_FDT +scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x05800000 /* and(), EU# 1 */ +.long 0x05400000 /* andn(), EU# 1 */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 + +.align 8 + +.globl scEthernetXmit_FDT +scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x05800000 /* and(), EU# 1 */ +.long 0x05400000 /* andn(), EU# 1 */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 + + +.align 8 +.globl scEthernetRecv_CSave +scEthernetRecv_CSave: /* Task 0 context save space */ +.space 256, 0x0 + + +.align 8 +.globl scEthernetXmit_CSave +scEthernetXmit_CSave: /* Task 1 context save space */ +.space 256, 0x0 + +#endif /* CONFIG_MGT5100 */ diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S new file mode 100644 index 0000000..1d83fe2 --- /dev/null +++ b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2001, Software Center, Motorola China. + * + * This file contains microcode for the FEC controller of the MPC5200 CPU. + */ + +#include + +#if defined(CONFIG_MPC5200) + +/* sas/sccg, gas target */ +.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ +.section smartdmaTaskTable,"aw",@progbits /* Task tables */ +.align 9 +.globl taskTable +taskTable: +.globl scEthernetRecv_Entry +scEthernetRecv_Entry: /* Task 0 */ +.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ +.long scEthernetRecv_TDT - taskTable + 0x000000a4 +.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ +.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ +.long 0x00000000 +.long 0x00000000 +.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ +.long 0xf0000000 +.globl scEthernetXmit_Entry +scEthernetXmit_Entry: /* Task 1 */ +.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ +.long scEthernetXmit_TDT - taskTable + 0x000000d0 +.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ +.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ +.long 0x00000000 +.long 0x00000000 +.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ +.long 0xf0000000 + + +.globl scEthernetRecv_TDT +scEthernetRecv_TDT: /* Task 0 Descriptor Table */ +.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ +.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ +.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ +.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ +.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x010cf04c /* 0020: DRD2B1: var4 = EU3(); EU3(var1,var12) */ +.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ +.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ +.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x018cf04e /* 0030: DRD2B1: var6 = EU3(); EU3(var1,var14) */ +.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x020cf04f /* 0038: DRD2B1: var8 = EU3(); EU3(var1,var15) */ +.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ +.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ +.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ +.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ +.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ +.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ +.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ +.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ +.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ +.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ +.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ +.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ +.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ +.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ +.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ +.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ +.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ +.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ +.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ +.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x080cf04c /* 00A0: DRD2B1: idx0 = EU3(); EU3(var1,var12) */ +.long 0x000001f8 /* 00A4(:0): NOP */ + + +.globl scEthernetXmit_TDT +scEthernetXmit_TDT: /* Task 1 Descriptor Table */ +.long 0x80024800 /* 0000: LCDEXT: idx0 = 0xf0008800; ; */ +.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ +.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ +.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ +.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x024cf04d /* 0020: DRD2B1: var9 = EU3(); EU3(var1,var13) */ +.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ +.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ +.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ +.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x010cf04e /* 0034: DRD2B1: var4 = EU3(); EU3(var1,var14) */ +.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x014cf04f /* 003C: DRD2B1: var5 = EU3(); EU3(var1,var15) */ +.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x028cf050 /* 0044: DRD2B1: var10 = EU3(); EU3(var1,var16) */ +.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x018cf051 /* 004C: DRD2B1: var6 = EU3(); EU3(var1,var17) */ +.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x01ccf0a1 /* 0058: DRD2B1: var7 = EU3(); EU3(var2,idx1) */ +.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ +.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ +.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ +.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ +.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ +.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ +.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ +.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ +.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ +.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ +.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x60000001 /* 0088: DRD2A: EU0=0 EU1=0 EU2=0 EU3=1 EXT init=0 WS=0 RS=0 */ +.long 0x0c4cfc4d /* 008C: DRD2B1: *idx1 = EU3(); EU3(*idx1,var13) */ +.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ +.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ +.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ +.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ +.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ +.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ +.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ +.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ +.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x080cf04d /* 00CC: DRD2B1: idx0 = EU3(); EU3(var1,var13) */ +.long 0x000001f8 /* 00D0(:0): NOP */ + +.align 8 + +.globl scEthernetRecv_VarTab +scEthernetRecv_VarTab: /* Task 0 Variable Table */ +.long 0x00000000 /* var[0] */ +.long 0x00000000 /* var[1] */ +.long 0x00000000 /* var[2] */ +.long 0x00000000 /* var[3] */ +.long 0x00000000 /* var[4] */ +.long 0x00000000 /* var[5] */ +.long 0x00000000 /* var[6] */ +.long 0x00000000 /* var[7] */ +.long 0x00000000 /* var[8] */ +.long 0xf0008800 /* var[9] */ +.long 0x00000008 /* var[10] */ +.long 0x0000000c /* var[11] */ +.long 0x80000000 /* var[12] */ +.long 0x00000000 /* var[13] */ +.long 0x10000000 /* var[14] */ +.long 0x20000000 /* var[15] */ +.long 0x000005e4 /* var[16] */ +.long 0x0000000e /* var[17] */ +.long 0x000005e0 /* var[18] */ +.long 0x00000004 /* var[19] */ +.long 0x00000000 /* var[20] */ +.long 0x00000000 /* var[21] */ +.long 0x00000000 /* var[22] */ +.long 0x00000000 /* var[23] */ +.long 0x00000000 /* inc[0] */ +.long 0x60000000 /* inc[1] */ +.long 0x20000001 /* inc[2] */ +.long 0x80000000 /* inc[3] */ +.long 0x40000000 /* inc[4] */ +.long 0x00000000 /* inc[5] */ +.long 0x00000000 /* inc[6] */ +.long 0x00000000 /* inc[7] */ + +.align 8 + +.globl scEthernetXmit_VarTab +scEthernetXmit_VarTab: /* Task 1 Variable Table */ +.long 0x00000000 /* var[0] */ +.long 0x00000000 /* var[1] */ +.long 0x00000000 /* var[2] */ +.long 0x00000000 /* var[3] */ +.long 0x00000000 /* var[4] */ +.long 0x00000000 /* var[5] */ +.long 0x00000000 /* var[6] */ +.long 0x00000000 /* var[7] */ +.long 0x00000000 /* var[8] */ +.long 0x00000000 /* var[9] */ +.long 0x00000000 /* var[10] */ +.long 0xf0008800 /* var[11] */ +.long 0x00000000 /* var[12] */ +.long 0x80000000 /* var[13] */ +.long 0x10000000 /* var[14] */ +.long 0x08000000 /* var[15] */ +.long 0x20000000 /* var[16] */ +.long 0x0000ffff /* var[17] */ +.long 0xffffffff /* var[18] */ +.long 0x00000008 /* var[19] */ +.long 0x00000000 /* var[20] */ +.long 0x00000000 /* var[21] */ +.long 0x00000000 /* var[22] */ +.long 0x00000000 /* var[23] */ +.long 0x00000000 /* inc[0] */ +.long 0x60000000 /* inc[1] */ +.long 0x40000000 /* inc[2] */ +.long 0x4000ffff /* inc[3] */ +.long 0xe0000001 /* inc[4] */ +.long 0x80000000 /* inc[5] */ +.long 0x00000000 /* inc[6] */ +.long 0x00000000 /* inc[7] */ + +.align 8 + +.globl scEthernetRecv_FDT +scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x21800000 /* and(), EU# 3 */ +.long 0x21400000 /* andn(), EU# 3 */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 + +.align 8 + +.globl scEthernetXmit_FDT +scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x21800000 /* and(), EU# 3 */ +.long 0x21400000 /* andn(), EU# 3 */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 + + +.globl scEthernetRecv_CSave +scEthernetRecv_CSave: /* Task 0 context save space */ +.space 128, 0x0 + + +.globl scEthernetXmit_CSave +scEthernetXmit_CSave: /* Task 1 context save space */ +.space 128, 0x0 + +#endif /* CONFIG_MPC5200 */ diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c new file mode 100644 index 0000000..044db46 --- /dev/null +++ b/cpu/mpc5xxx/i2c.c @@ -0,0 +1,398 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_HARD_I2C + +#include +#include + +#if (CFG_I2C_MODULE == 2) +#define I2C_BASE MPC5XXX_I2C2 +#elif (CFG_I2C_MODULE == 1) +#define I2C_BASE MPC5XXX_I2C1 +#else +#error CFG_I2C_MODULE is not properly configured +#endif + +#define I2C_TIMEOUT 100 +#define I2C_RETRIES 3 + +struct mpc5xxx_i2c_tap { + int scl2tap; + int tap2tap; +}; + +static int mpc_reg_in (volatile u32 *reg); +static void mpc_reg_out (volatile u32 *reg, int val, int mask); +static int wait_for_bb (void); +static int wait_for_pin (int *status); +static int do_address (uchar chip, char rdwr_flag); +static int send_bytes (uchar chip, char *buf, int len); +static int receive_bytes (uchar chip, char *buf, int len); +static int mpc_get_fdr (int); + +static int mpc_reg_in(volatile u32 *reg) +{ + int ret = *reg >> 24; + __asm__ __volatile__ ("eieio"); + return ret; +} + +static void mpc_reg_out(volatile u32 *reg, int val, int mask) +{ + int tmp; + + if (!mask) { + *reg = val << 24; + } else { + tmp = mpc_reg_in(reg); + *reg = ((tmp & ~mask) | (val & mask)) << 24; + } + __asm__ __volatile__ ("eieio"); + + return; +} + +static int wait_for_bb(void) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int timeout = I2C_TIMEOUT; + int status; + + status = mpc_reg_in(®s->msr); + + while (timeout-- && (status & I2C_BB)) { +#if 1 + volatile int temp; + mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); + temp = mpc_reg_in(®s->mdr); + mpc_reg_out(®s->mcr, 0, I2C_STA); + mpc_reg_out(®s->mcr, 0, 0); + mpc_reg_out(®s->mcr, I2C_EN, 0); +#endif + udelay(1000); + status = mpc_reg_in(®s->msr); + } + + return (status & I2C_BB); +} + +static int wait_for_pin(int *status) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int timeout = I2C_TIMEOUT; + + *status = mpc_reg_in(®s->msr); + + while (timeout-- && !(*status & I2C_IF)) { + udelay(1000); + *status = mpc_reg_in(®s->msr); + } + + if (!(*status & I2C_IF)) { + return -1; + } + + mpc_reg_out(®s->msr, 0, I2C_IF); + + return 0; +} + +static int do_address(uchar chip, char rdwr_flag) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int status; + + chip <<= 1; + + if (rdwr_flag) { + chip |= 1; + } + + mpc_reg_out(®s->mcr, I2C_TX, I2C_TX); + mpc_reg_out(®s->mdr, chip, 0); + + if (wait_for_pin(&status)) { + return -2; + } + + if (status & I2C_RXAK) { + return -3; + } + + return 0; +} + +static int send_bytes(uchar chip, char *buf, int len) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int wrcount; + int status; + + for (wrcount = 0; wrcount < len; ++wrcount) { + + mpc_reg_out(®s->mdr, buf[wrcount], 0); + + if (wait_for_pin(&status)) { + break; + } + + if (status & I2C_RXAK) { + break; + } + + } + + return !(wrcount == len); +} + +static int receive_bytes(uchar chip, char *buf, int len) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int dummy = 1; + int rdcount = 0; + int status; + int i; + + mpc_reg_out(®s->mcr, 0, I2C_TX); + + for (i = 0; i < len; ++i) { + buf[rdcount] = mpc_reg_in(®s->mdr); + + if (dummy) { + dummy = 0; + } else { + rdcount++; + } + + + if (wait_for_pin(&status)) { + return -4; + } + } + + mpc_reg_out(®s->mcr, I2C_TXAK, I2C_TXAK); + buf[rdcount++] = mpc_reg_in(®s->mdr); + + if (wait_for_pin(&status)) { + return -5; + } + + mpc_reg_out(®s->mcr, 0, I2C_TXAK); + + return 0; +} + +/**************** I2C API ****************/ + +void i2c_init(int speed, int saddr) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + + mpc_reg_out(®s->mcr, 0, 0); + mpc_reg_out(®s->madr, saddr << 1, 0); + + /* Set clock + */ + mpc_reg_out(®s->mfdr, mpc_get_fdr(speed), 0); + + /* Enable module + */ + mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK); + mpc_reg_out(®s->msr, 0, I2C_IF); + + return; +} + +static int mpc_get_fdr(int speed) +{ + DECLARE_GLOBAL_DATA_PTR; + static int fdr = -1; + + if (fdr == -1) { + ulong best_speed = 0; + ulong divider; + ulong ipb, scl; + ulong bestmatch = 0xffffffffUL; + int best_i = 0, best_j = 0, i, j; + int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8}; + struct mpc5xxx_i2c_tap scltap[] = { + {4, 1}, + {4, 2}, + {6, 4}, + {6, 8}, + {14, 16}, + {30, 32}, + {62, 64}, + {126, 128} + }; + + ipb = gd->ipb_clk; + for (i = 7; i >= 0; i--) { + for (j = 7; j >= 0; j--) { + scl = 2 * (scltap[j].scl2tap + + (SCL_Tap[i] - 1) * scltap[j].tap2tap + 2); + if (ipb <= speed*scl) { + if ((speed*scl - ipb) < bestmatch) { + bestmatch = speed*scl - ipb; + best_i = i; + best_j = j; + best_speed = ipb/scl; + } + } + } + } + divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); + if (gd->flags & GD_FLG_RELOC) { + fdr = divider; + } else { + printf("%ld kHz, ", best_speed / 1000); + return divider; + } + } + + return fdr; +} + +int i2c_probe(uchar chip) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int i; + + for (i = 0; i < I2C_RETRIES; i++) { + mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); + + if (! do_address(chip, 0)) { + mpc_reg_out(®s->mcr, 0, I2C_STA); + udelay(500); + break; + } + + mpc_reg_out(®s->mcr, 0, I2C_STA); + udelay(500); + } + + return (i == I2C_RETRIES); +} + +int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + char xaddr[4]; + struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb()) { + printf("i2c_read: bus is busy\n"); + goto Done; + } + + mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); + if (do_address(chip, 0)) { + printf("i2c_read: failed to address chip\n"); + goto Done; + } + + if (send_bytes(chip, &xaddr[4-alen], alen)) { + printf("i2c_read: send_bytes failed\n"); + goto Done; + } + + mpc_reg_out(®s->mcr, I2C_RSTA, I2C_RSTA); + if (do_address(chip, 1)) { + printf("i2c_read: failed to address chip\n"); + goto Done; + } + + if (receive_bytes(chip, (char *)buf, len)) { + printf("i2c_read: receive_bytes failed\n"); + goto Done; + } + + ret = 0; +Done: + mpc_reg_out(®s->mcr, 0, I2C_STA); + return ret; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + char xaddr[4]; + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb()) { + printf("i2c_write: bus is busy\n"); + goto Done; + } + + mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); + if (do_address(chip, 0)) { + printf("i2c_write: failed to address chip\n"); + goto Done; + } + + if (send_bytes(chip, &xaddr[4-alen], alen)) { + printf("i2c_write: send_bytes failed\n"); + goto Done; + } + + if (send_bytes(chip, (char *)buf, len)) { + printf("i2c_write: send_bytes failed\n"); + goto Done; + } + + ret = 0; +Done: + mpc_reg_out(®s->mcr, 0, I2C_STA); + return ret; +} + +uchar i2c_reg_read(uchar chip, uchar reg) +{ + uchar buf; + + i2c_read(chip, reg, 1, &buf, 1); + + return buf; +} + +void i2c_reg_write(uchar chip, uchar reg, uchar val) +{ + i2c_write(chip, reg, 1, &val, 1); + + return; +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c new file mode 100644 index 0000000..1af794c --- /dev/null +++ b/cpu/mpc5xxx/ide.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2004 + * Pierre AUBERT, Staubli Faverges, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Init is derived from Linux code. + */ +#include + +#ifdef CFG_CMD_IDE +#include + +#define CALC_TIMING(t) (t + period - 1) / period + +#ifdef CONFIG_IDE_RESET +extern void init_ide_reset (void); +#endif + +int ide_preinit (void) +{ + DECLARE_GLOBAL_DATA_PTR; + long period, t0, t1, t2_8, t2_16, t4, ta; + vu_long reg; + struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA; + + reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG; +#if defined(CONFIG_TOTAL5200) + /* ATA cs0/1 on i2c2 clk/io */ + reg = (reg & ~0x03000000ul) | 0x02000000ul; +#else + /* ATA cs0/1 on Local Plus cs4/5 */ + reg = (reg & ~0x03000000ul) | 0x01000000ul; +#endif /* CONFIG_TOTAL5200 */ + *(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg; + + /* All sample codes do that... */ + *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0; + + /* Configure and reset host */ + *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY | + MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; + udelay (10); + *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY; + + /* Disable prefetch on Commbus */ + psdma->PtdCntrl |= 1; + + /* Init timings : we use PIO mode 0 timings */ + period = 1000000000 / gd->ipb_clk; /* period in ns */ + + t0 = CALC_TIMING (600); + t2_8 = CALC_TIMING (290); + t2_16 = CALC_TIMING (165); + reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8); + *(vu_long *) MPC5XXX_ATA_PIO1 = reg; + + t4 = CALC_TIMING (30); + t1 = CALC_TIMING (70); + ta = CALC_TIMING (35); + reg = (t4 << 24) | (t1 << 16) | (ta << 8); + + *(vu_long *) MPC5XXX_ATA_PIO2 = reg; + +#ifdef CONFIG_IDE_RESET + init_ide_reset (); +#endif /* CONFIG_IDE_RESET */ + + return (0); +} +#endif /* CFG_CMD_IDE */ diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c new file mode 100644 index 0000000..7bacecd --- /dev/null +++ b/cpu/mpc5xxx/interrupts.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright -2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * interrupts.c - just enough support for the decrementer/timer + */ + +#include +#include +#include + +int interrupt_init_cpu (ulong *decrementer_count) +{ + *decrementer_count = get_tbclk() / CFG_HZ; + + return (0); +} + +/****************************************************************************/ + +/* + * Handle external interrupts + */ +void +external_interrupt(struct pt_regs *regs) +{ + puts("external_interrupt (oops!)\n"); +} + +void +timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} + +/****************************************************************************/ + +/* + * Install and free a interrupt handler. + */ + +void +irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +{ + +} + +void +irq_free_handler(int vec) +{ + +} + +/****************************************************************************/ + +void +do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + puts("IRQ related functions are unimplemented currently.\n"); +} diff --git a/cpu/mpc5xxx/io.S b/cpu/mpc5xxx/io.S new file mode 100644 index 0000000..2178a26 --- /dev/null +++ b/cpu/mpc5xxx/io.S @@ -0,0 +1,128 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * Copyright (C) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/* ------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in16 */ +/* Description: Input 16 bits */ +/* ------------------------------------------------------------------------------- */ + .globl in16 +in16: + lhz r3,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in16r */ +/* Description: Input 16 bits and byte reverse */ +/* ------------------------------------------------------------------------------- */ + .globl in16r +in16r: + lhbrx r3,0,r3 + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/* ------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0(3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in32r */ +/* Description: Input 32 bits and byte reverse */ +/* ------------------------------------------------------------------------------- */ + .globl in32r +in32r: + lwbrx r3,0,r3 + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out16 */ +/* Description: Output 16 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out16 +out16: + sth r4,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out16r */ +/* Description: Byte reverse and output 16 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out16r +out16r: + sthbrx r4,0,r3 + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out32r */ +/* Description: Byte reverse and output 32 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out32r +out32r: + stwbrx r4,0,r3 + sync + blr diff --git a/cpu/mpc5xxx/loadtask.c b/cpu/mpc5xxx/loadtask.c new file mode 100644 index 0000000..47e7b59 --- /dev/null +++ b/cpu/mpc5xxx/loadtask.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on code + * (C) Copyright Motorola, Inc., 2000 + */ + +#include +#include + +/* BestComm/SmartComm microcode */ +extern int taskTable; + +void loadtask(int basetask, int tasks) +{ + int *sram = (int *)MPC5XXX_SRAM; + int *task_org = &taskTable; + unsigned int start, offset, end; + int i; + +#ifdef DEBUG + printf("basetask = %d, tasks = %d\n", basetask, tasks); + printf("task_org = 0x%08x\n", (unsigned int)task_org); +#endif + + /* setup TaskBAR register */ + *(vu_long *)MPC5XXX_SDMA = MPC5XXX_SRAM; + + /* relocate task table entries */ + offset = (unsigned int)sram; + for (i = basetask; i < basetask + tasks; i++) { + sram[i * 8 + 0] = task_org[i * 8 + 0] + offset; + sram[i * 8 + 1] = task_org[i * 8 + 1] + offset; + sram[i * 8 + 2] = task_org[i * 8 + 2] + offset; + sram[i * 8 + 3] = task_org[i * 8 + 3] + offset; + sram[i * 8 + 4] = task_org[i * 8 + 4]; + sram[i * 8 + 5] = task_org[i * 8 + 5]; + sram[i * 8 + 6] = task_org[i * 8 + 6] + offset; + sram[i * 8 + 7] = task_org[i * 8 + 7]; + } + + /* relocate task descriptors */ + start = (sram[basetask * 8] - (unsigned int)sram); + end = (sram[(basetask + tasks - 1) * 8 + 1] - (unsigned int)sram); + +#ifdef DEBUG + printf ("TDT start = 0x%08x, end = 0x%08x\n", start, end); +#endif + + start /= 4; + end /= 4; + for (i = start; i <= end; i++) { + sram[i] = task_org[i]; + } + + /* relocate variables */ + start = (sram[basetask * 8 + 2] - (unsigned int)sram); + end = (sram[(basetask + tasks - 1) * 8 + 2] + 256 - (unsigned int)sram); + start /= 4; + end /= 4; + for (i = start; i < end; i++) { + sram[i] = task_org[i]; + } + + /* relocate function decriptors */ + start = ((sram[basetask * 8 + 3] & 0xfffffffc) - (unsigned int)sram); + end = ((sram[(basetask + tasks - 1) * 8 + 3] & 0xfffffffc) + 256 - (unsigned int)sram); + start /= 4; + end /= 4; + for (i = start; i < end; i++) { + sram[i] = task_org[i]; + } + + asm volatile ("sync"); +} diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c new file mode 100644 index 0000000..1d90345 --- /dev/null +++ b/cpu/mpc5xxx/pci_mpc5200.c @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200) + +#include +#include +#include +#include + +/* System RAM mapped over PCI */ +#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024) + +/* PCIIWCR bit fields */ +#define IWCR_MEM (0 << 3) +#define IWCR_IO (1 << 3) +#define IWCR_READ (0 << 1) +#define IWCR_READLINE (1 << 1) +#define IWCR_READMULT (2 << 1) +#define IWCR_EN (1 << 0) + +static int mpc5200_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32* value) +{ + *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; + eieio(); + udelay(10); +#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200) + if (dev & 0x00ff0000) { + u32 val; + val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2)); + udelay(10); + val = val << 16; + val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0)); + *value = val; + } else { + *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); + } + udelay(10); +#else + *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); +#endif + eieio(); + *(volatile u32 *)MPC5XXX_PCI_CAR = 0; + udelay(10); + return 0; +} + +static int mpc5200_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; + eieio(); + udelay(10); + out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value); + eieio(); + *(volatile u32 *)MPC5XXX_PCI_CAR = 0; + udelay(10); + return 0; +} + +void pci_mpc5xxx_init (struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEMORY_BUS, + CONFIG_PCI_MEMORY_PHYS, + CONFIG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + pci_register_hose(hose); + + /* GPIO Multiplexing - enable PCI */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15); + + /* Set host bridge as pci master and enable memory decoding */ + *(vu_long *)MPC5XXX_PCI_CMD |= + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + + /* Set maximum latency timer */ + *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800); + + /* Set cache line size */ + *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) | + (CFG_CACHELINE_SIZE / 4); + + /* Map MBAR to PCI space */ + *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR; + *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1; + + /* Map RAM to PCI space */ + *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); + *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1; + + /* Enable snooping for RAM */ + *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15); + *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d; + + /* Park XLB on PCI */ + *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5)); + *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5); + + /* Disable interrupts from PCI controller */ + *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12); + *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24); + + /* Set PCI retry counter to 0 = infinite retry. */ + /* The default of 255 is too short for slow devices. */ + *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00; + + /* Disable initiator windows */ + *(vu_long *)MPC5XXX_PCI_IWCR = 0; + + /* Map PCI memory to physical space */ + *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS | + (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) | + (CONFIG_PCI_MEM_BUS >> 16); + *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24; + + /* Map PCI I/O to physical space */ + *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS | + (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) | + (CONFIG_PCI_IO_BUS >> 16); + *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16; + + /* Reset the PCI bus */ + *(vu_long *)MPC5XXX_PCI_GSCR |= 1; + udelay(1000); + *(vu_long *)MPC5XXX_PCI_GSCR &= ~1; + udelay(1000); + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + mpc5200_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + mpc5200_write_config_dword); + + udelay(1000); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCI && CONFIG_MPC5200 */ diff --git a/cpu/mpc5xxx/sdma.h b/cpu/mpc5xxx/sdma.h new file mode 100644 index 0000000..8b740e4 --- /dev/null +++ b/cpu/mpc5xxx/sdma.h @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on code + * (C) Copyright Motorola, Inc., 2000 + * + * odin smartdma header file + */ + +#ifndef __MPC5XXX_SDMA_H +#define __MPC5XXX_SDMA_H + +#include +#include + +/* Task number assignment */ +#define FEC_RECV_TASK_NO 0 +#define FEC_XMIT_TASK_NO 1 + +/*---------------------------------------------------------------------*/ + +/* Stuff for Ethernet Tx/Rx tasks */ + +/*---------------------------------------------------------------------*/ + +/* Layout of Ethernet controller Parameter SRAM area: +---------------------------------------------------------------- +0x00: TBD_BASE, base address of TX BD ring +0x04: TBD_NEXT, address of next TX BD to be processed +0x08: RBD_BASE, base address of RX BD ring +0x0C: RBD_NEXT, address of next RX BD to be processed +--------------------------------------------------------------- +ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH). +*/ + +/* base address of SRAM area to store parameters used by Ethernet tasks */ +#define FEC_PARAM_BASE (MPC5XXX_SRAM + 0x0800) + +/* base address of SRAM area for buffer descriptors */ +#define FEC_BD_BASE (MPC5XXX_SRAM + 0x0820) + +/*---------------------------------------------------------------------*/ + +/* common shortcuts used by driver C code */ + +/*---------------------------------------------------------------------*/ + +/* Disable SmartDMA task */ +#define SDMA_TASK_DISABLE(tasknum) \ +{ \ + volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ + *tcr = (*tcr) & (~0x8000); \ +} + +/* Enable SmartDMA task */ +#define SDMA_TASK_ENABLE(tasknum) \ +{ \ + volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ + *tcr = (*tcr) | 0x8000; \ +} + +/* Enable interrupt */ +#define SDMA_INT_ENABLE(tasknum) \ +{ \ + struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ + sdma->IntMask &= ~(1 << tasknum); \ +} + +/* Disable interrupt */ +#define SDMA_INT_DISABLE(tasknum) \ +{ \ + struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ + sdma->IntMask |= (1 << tasknum); \ +} + + +/* Clear interrupt pending bits */ +#define SDMA_CLEAR_IEVENT(tasknum) \ +{ \ + struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ + sdma->IntPend = (1 << tasknum); \ +} + +/* get interupt pending bit of a task */ +#define SDMA_GET_PENDINGBIT(tasknum) \ + ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum))) + +/* get interupt mask bit of a task */ +#define SDMA_GET_MASKBIT(tasknum) \ + ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum))) + +#endif /* __MPC5XXX_SDMA_H */ diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c new file mode 100644 index 0000000..91e1def --- /dev/null +++ b/cpu/mpc5xxx/serial.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2000 - 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with + * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the + * Linux/PPC sources (m8260_tty.c had no copyright info in it). + */ + +/* + * Minimal serial functions needed to use one of the PSC ports + * as serial console interface. + */ + +#include +#include + +#if defined(CONFIG_PSC_CONSOLE) + +#if CONFIG_PSC_CONSOLE == 1 +#define PSC_BASE MPC5XXX_PSC1 +#elif CONFIG_PSC_CONSOLE == 2 +#define PSC_BASE MPC5XXX_PSC2 +#elif CONFIG_PSC_CONSOLE == 3 +#define PSC_BASE MPC5XXX_PSC3 +#elif defined(CONFIG_MGT5100) +#error CONFIG_PSC_CONSOLE must be in 1, 2 or 3 +#elif CONFIG_PSC_CONSOLE == 4 +#define PSC_BASE MPC5XXX_PSC4 +#elif CONFIG_PSC_CONSOLE == 5 +#define PSC_BASE MPC5XXX_PSC5 +#elif CONFIG_PSC_CONSOLE == 6 +#define PSC_BASE MPC5XXX_PSC6 +#else +#error CONFIG_PSC_CONSOLE must be in 1 ... 6 +#endif + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; + unsigned long baseclk; + int div; + + /* reset PSC */ + psc->command = PSC_SEL_MODE_REG_1; + + /* select clock sources */ +#if defined(CONFIG_MGT5100) + psc->psc_clock_select = 0xdd00; + baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; +#elif defined(CONFIG_MPC5200) + psc->psc_clock_select = 0; + baseclk = (gd->ipb_clk + 16) / 32; +#endif + + /* switch to UART mode */ + psc->sicr = 0; + + /* configure parity, bit length and so on */ +#if defined(CONFIG_MGT5100) + psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; +#elif defined(CONFIG_MPC5200) + psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; +#endif + psc->mode = PSC_MODE_ONE_STOP; + + /* set up UART divisor */ + div = (baseclk + (gd->baudrate/2)) / gd->baudrate; + psc->ctur = (div >> 8) & 0xff; + psc->ctlr = div & 0xff; + + /* disable all interrupts */ + psc->psc_imr = 0; + + /* reset and enable Rx/Tx */ + psc->command = PSC_RST_RX; + psc->command = PSC_RST_TX; + psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; + + return (0); +} + +void +serial_putc(const char c) +{ + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; + + if (c == '\n') + serial_putc('\r'); + + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->psc_buffer_8 = c; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int +serial_getc(void) +{ + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; + + /* Wait for a character to arrive. */ + while (!(psc->psc_status & PSC_SR_RXRDY)) + ; + + return psc->psc_buffer_8; +} + +int +serial_tstc(void) +{ + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; + + return (psc->psc_status & PSC_SR_RXRDY); +} + +void +serial_setbrg(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; + unsigned long baseclk, div; + +#if defined(CONFIG_MGT5100) + baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; +#elif defined(CONFIG_MPC5200) + baseclk = (gd->ipb_clk + 16) / 32; +#endif + + /* set up UART divisor */ + div = (baseclk + (gd->baudrate/2)) / gd->baudrate; + psc->ctur = (div >> 8) & 0xFF; + psc->ctlr = div & 0xff; +} +#endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc5xxx/speed.c b/cpu/mpc5xxx/speed.c new file mode 100644 index 0000000..4f4e814 --- /dev/null +++ b/cpu/mpc5xxx/speed.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +/* Bus-to-Core Multipliers */ + +static int bus2core[] = { + 3, 2, 2, 2, 4, 4, 5, 9, + 6, 11, 8, 10, 3, 12, 7, 0, + 6, 5, 13, 2, 14, 4, 15, 9, + 0, 11, 8, 10, 16, 12, 7, 0 +}; +/* ------------------------------------------------------------------------- */ + +/* + * + */ + +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong val, vco; + +#if !defined(CFG_MPC5XXX_CLKIN) +#error clock measuring not implemented yet - define CFG_MPC5XXX_CLKIN +#endif + + val = *(vu_long *)MPC5XXX_CDM_PORCFG; + if (val & (1 << 6)) { + vco = CFG_MPC5XXX_CLKIN * 12; + } else { + vco = CFG_MPC5XXX_CLKIN * 16; + } + if (val & (1 << 5)) { + gd->bus_clk = vco / 8; + } else { + gd->bus_clk = vco / 4; + } + gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2; + + val = *(vu_long *)MPC5XXX_CDM_CFG; + if (val & (1 << 8)) { + gd->ipb_clk = gd->bus_clk / 2; + } else { + gd->ipb_clk = gd->bus_clk; + } + switch (val & 3) { + case 0: gd->pci_clk = gd->ipb_clk; break; + case 1: gd->pci_clk = gd->ipb_clk / 2; break; + default: gd->pci_clk = gd->bus_clk / 4; break; + } + + return (0); +} + +int prt_mpc5xxx_clks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + printf(" Bus %ld MHz, IPB %ld MHz, PCI %ld MHz\n", + gd->bus_clk / 1000000, gd->ipb_clk / 1000000, + gd->pci_clk / 1000000); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S new file mode 100644 index 0000000..3936b55 --- /dev/null +++ b/cpu/mpc5xxx/start.S @@ -0,0 +1,810 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000 - 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot - Startup Code for MPC5xxx CPUs + */ +#include +#include +#include + +#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +/* Floating Point enable, Machine Check and Recoverable Interr. */ +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * Version string + */ + .data + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + +/* + * Exception vectors + */ + .text + . = EXC_OFF_SYS_RESET + .globl _start +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On */ + nop + b boot_cold + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + +boot_cold: +boot_warm: + mfmsr r5 /* save msr contents */ + + /* Move CSBoot and adjust instruction pointer */ + /*--------------------------------------------------------------*/ + +#if defined(CFG_LOWBOOT) +# if defined(CFG_RAMBOOT) +# error CFG_LOWBOOT is incompatible with CFG_RAMBOOT +# endif /* CFG_RAMBOOT */ +# if defined(CONFIG_MGT5100) +# error CFG_LOWBOOT is incompatible with MGT5100 +# endif /* CONFIG_MGT5100 */ + lis r4, CFG_DEFAULT_MBAR@h + lis r3, START_REG(CFG_BOOTCS_START)@h + ori r3, r3, START_REG(CFG_BOOTCS_START)@l + stw r3, 0x4(r4) /* CS0 start */ + lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h + ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l + stw r3, 0x8(r4) /* CS0 stop */ + lis r3, 0x02010000@h + ori r3, r3, 0x02010000@l + stw r3, 0x54(r4) /* CS0 and Boot enable */ + + lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */ + ori r3, r3, lowboot_reentry@l /* to the address space the linker used */ + mtlr r3 + blr + +lowboot_reentry: + lis r3, START_REG(CFG_BOOTCS_START)@h + ori r3, r3, START_REG(CFG_BOOTCS_START)@l + stw r3, 0x4c(r4) /* Boot start */ + lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h + ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l + stw r3, 0x50(r4) /* Boot stop */ + lis r3, 0x02000001@h + ori r3, r3, 0x02000001@l + stw r3, 0x54(r4) /* Boot enable, CS0 disable */ +#endif /* CFG_LOWBOOT */ + +#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT) + lis r3, CFG_MBAR@h + ori r3, r3, CFG_MBAR@l +#if defined(CONFIG_MPC5200) + /* MBAR is mirrored into the MBAR SPR */ + mtspr MBAR,r3 + rlwinm r3, r3, 16, 16, 31 +#endif +#if defined(CONFIG_MGT5100) + rlwinm r3, r3, 17, 15, 31 +#endif + lis r4, CFG_DEFAULT_MBAR@h + stw r3, 0(r4) +#endif /* CFG_DEFAULT_MBAR */ + + /* Initialise the MPC5xxx processor core */ + /*--------------------------------------------------------------*/ + + bl init_5xxx_core + + /* initialize some things that are hard to access from C */ + /*--------------------------------------------------------------*/ + + /* set up stack in on-chip SRAM */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + ori r1, r3, CFG_INIT_SP_OFFSET + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*--------------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + bl cpu_init_f /* run low-level CPU init code (in Flash)*/ + + mr r3, r21 + /* r3: BOOTFLAG */ + bl board_init_f /* run 1st part of board init code (in Flash)*/ + +/* + * Vector Table + */ + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) +#ifdef DEBUG + . = 0x1300 + /* + * This exception occurs when the program counter matches the + * Instruction Address Breakpoint Register (IABR). + * + * I want the cpu to halt if this occurs so I can hunt around + * with the debugger and look at things. + * + * When DEBUG is defined, both machine check enable (in the MSR) + * and checkstop reset enable (in the reset mode register) are + * turned off and so a checkstop condition will result in the cpu + * halting. + * + * I force the cpu into a checkstop condition by putting an illegal + * instruction here (at least this is the theory). + * + * well - that didnt work, so just do an infinite loop! + */ +1: b 1b +#else + STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) +#endif + STD_EXCEPTION(0x1400, SMI, UnknownException) + + STD_EXCEPTION(0x1500, Trap_15, UnknownException) + STD_EXCEPTION(0x1600, Trap_16, UnknownException) + STD_EXCEPTION(0x1700, Trap_17, UnknownException) + STD_EXCEPTION(0x1800, Trap_18, UnknownException) + STD_EXCEPTION(0x1900, Trap_19, UnknownException) + STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) + STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) + STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) + STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) + STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) + STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) + STD_EXCEPTION(0x2000, Trap_20, UnknownException) + STD_EXCEPTION(0x2100, Trap_21, UnknownException) + STD_EXCEPTION(0x2200, Trap_22, UnknownException) + STD_EXCEPTION(0x2300, Trap_23, UnknownException) + STD_EXCEPTION(0x2400, Trap_24, UnknownException) + STD_EXCEPTION(0x2500, Trap_25, UnknownException) + STD_EXCEPTION(0x2600, Trap_26, UnknownException) + STD_EXCEPTION(0x2700, Trap_27, UnknownException) + STD_EXCEPTION(0x2800, Trap_28, UnknownException) + STD_EXCEPTION(0x2900, Trap_29, UnknownException) + STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) + STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) + STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) + STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) + STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) + STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) + + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x3000 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* + * This code initialises the MPC5xxx processor core + * (conforms to PowerPC 603e spec) + * Note: expects original MSR contents to be in r5. + */ + + .globl init_5xx_core +init_5xxx_core: + + /* Initialize machine status; enable machine check interrupt */ + /*--------------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ +#endif + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*--------------------------------------------------------------*/ + + lis r3, CFG_HID0_INIT@h + ori r3, r3, CFG_HID0_INIT@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID0_FINAL@h + ori r3, r3, CFG_HID0_FINAL@l + SYNC + mtspr HID0, r3 + + /* clear all BAT's */ + /*--------------------------------------------------------------*/ + + li r0, 0 + mtspr DBAT0U, r0 + mtspr DBAT0L, r0 + mtspr DBAT1U, r0 + mtspr DBAT1L, r0 + mtspr DBAT2U, r0 + mtspr DBAT2L, r0 + mtspr DBAT3U, r0 + mtspr DBAT3L, r0 + mtspr DBAT4U, r0 + mtspr DBAT4L, r0 + mtspr DBAT5U, r0 + mtspr DBAT5L, r0 + mtspr DBAT6U, r0 + mtspr DBAT6L, r0 + mtspr DBAT7U, r0 + mtspr DBAT7L, r0 + mtspr IBAT0U, r0 + mtspr IBAT0L, r0 + mtspr IBAT1U, r0 + mtspr IBAT1L, r0 + mtspr IBAT2U, r0 + mtspr IBAT2L, r0 + mtspr IBAT3U, r0 + mtspr IBAT3L, r0 + mtspr IBAT4U, r0 + mtspr IBAT4L, r0 + mtspr IBAT5U, r0 + mtspr IBAT5L, r0 + mtspr IBAT6U, r0 + mtspr IBAT6L, r0 + mtspr IBAT7U, r0 + mtspr IBAT7L, r0 + SYNC + + /* invalidate all tlb's */ + /* */ + /* From the 603e User Manual: "The 603e provides the ability to */ + /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ + /* instruction invalidates the TLB entry indexed by the EA, and */ + /* operates on both the instruction and data TLBs simultaneously*/ + /* invalidating four TLB entries (both sets in each TLB). The */ + /* index corresponds to bits 15-19 of the EA. To invalidate all */ + /* entries within both TLBs, 32 tlbie instructions should be */ + /* issued, incrementing this field by one each time." */ + /* */ + /* "Note that the tlbia instruction is not implemented on the */ + /* 603e." */ + /* */ + /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ + /* incrementing by 0x1000 each time. The code below is sort of */ + /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */ + /* */ + /*--------------------------------------------------------------*/ + + li r3, 32 + mtctr r3 + li r3, 0 +1: tlbie r3 + addi r3, r3, 0x1000 + bdnz 1b + SYNC + + /* Done! */ + /*--------------------------------------------------------------*/ + + blr + +/* Cache functions. + * + * Note: requires that all cache bits in + * HID0 are in the low half word. + */ + .globl icache_enable +icache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_ICE + lis r4, 0 + ori r4, r4, HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_disable +icache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_ICE|HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_status +icache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 + blr + + .globl dcache_enable +dcache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_DCE + lis r4, 0 + ori r4, r4, HID0_DLOCK + andc r3, r3, r4 + ori r4, r3, HID0_DCI + sync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_disable +dcache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_DCE|HID0_DLOCK + andc r3, r3, r4 + ori r4, r3, HID0_DCI + sync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_status +dcache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 + blr + + .globl get_svr +get_svr: + mfspr r3, SVR + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ + rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 + cmpwi r7,0 + beq 9f + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ +9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ + rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 + cmpwi r7,0 + beq 7f + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mfmsr r3 /* now that the vectors have */ + lis r7, MSR_IP@h /* relocated into low memory */ + ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ + andc r3, r3, r7 /* (if it was on) */ + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr diff --git a/cpu/mpc5xxx/traps.c b/cpu/mpc5xxx/traps.c new file mode 100644 index 0000000..2ee782b --- /dev/null +++ b/cpu/mpc5xxx/traps.c @@ -0,0 +1,248 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * fixed Machine Check Reasons by Reinhard Meyer (r.meyer@emk-elektronik.de) + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler)(struct pt_regs *) = 0; +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. +*/ +#define END_OF_MEM 0x02000000 + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ",regs); + /* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */ + switch( regs->msr & 0x000F0000) + { + case (0x80000000>>12) : + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13) : + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14) : + printf("Data parity signal\n"); + break; + case (0x80000000>>15) : + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +SoftEmuException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + + +void +UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint(struct pt_regs *); +#endif + +void +DebugException(struct pt_regs *regs) +{ + + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); +#endif +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int +addr_probe(uint *addr) +{ +#if 0 + int retval; + + __asm__ __volatile__( \ + "1: lwz %0,0(%1)\n" \ + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); + + return (retval); +#endif + return 0; +} diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c new file mode 100644 index 0000000..c774da3 --- /dev/null +++ b/cpu/mpc5xxx/usb_ohci.c @@ -0,0 +1,1649 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200. + * + * (C) Copyright 2003-2004 + * Gary Jennejohn, DENX Software Engineering + * + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTES + * 1 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + */ + +#include + +#ifdef CONFIG_USB_OHCI + +#include +#include +#include "usb_ohci.h" + +#include + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ +#undef DEBUG +#undef SHOW_INFO +#undef OHCI_FILL_TRACE + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +#define readl(a) (*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) + +#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +#ifdef DEBUG +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) swap_16(x) +#define m32_swap(x) swap_32(x) + +#ifdef CONFIG_MPC5200 +#define ohci_cpu_to_le16(x) (x) +#define ohci_cpu_to_le32(x) (x) +#else +#define ohci_cpu_to_le16(x) swap_16(x) +#define ohci_cpu_to_le32(x) swap_32(x) +#endif + +/* global ohci_t */ +static ohci_t gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +urb_priv_t urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; +/* flag guarding URB transation */ +int urb_finished = 0; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + +static u32 roothub_a (struct ohci *hc) + { return read_roothub (hc, a, 0xfc0fe000); } +static inline u32 roothub_b (struct ohci *hc) + { return readl (&hc->regs->roothub.b); } +static inline u32 roothub_status (struct ohci *hc) + { return readl (&hc->regs->roothub.status); } +static u32 roothub_portstatus (struct ohci *hc, int i) + { return read_roothub (hc, portstatus [i], 0xffe0fce0); } + + +/* forward declaration */ +static int hc_interrupt (void); +static void +td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv (urb_priv_t * urb) +{ + int i; + int last; + struct td * td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +static int sohci_get_current_frame_number (struct usb_device * dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, char * str, int small) +{ + urb_priv_t * purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number (dev), + usb_pipedevice (pipe), + usb_pipeendpoint (pipe), + usb_pipeout (pipe)? 'O': 'I', + usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): + (usb_pipecontrol (pipe)? "CTRL": "BULK"), + purb->actual_length, + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol (pipe)) { + printf (__FILE__ ": cmd(8):"); + for (i = 0; i < 8 ; i++) + printf (" %02x", ((__u8 *) setup) [i]); + printf ("\n"); + } + if (transfer_len > 0 && buffer) { + printf (__FILE__ ": data(%d/%d):", + purb->actual_length, + transfer_len); + len = usb_pipeout (pipe)? + transfer_len: purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf (" %02x", ((__u8 *) buffer) [i]); + printf ("%s\n", i < len? "...": ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ +void ep_print_int_eds (ohci_t *ohci, char * str) { + int i, j; + __u32 * ed_p; + for (i= 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table [i]); + if (*ed_p == 0) + continue; + printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p); + printf (" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf ("\n"); + } +} + +static void ohci_dump_intr_mask (char *label, __u32 mask) +{ + dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds (char *label, __u32 value) +{ + ed_t *edp = (ed_t *)value; + + if (value) { + dbg ("%s %08x", label, value); + dbg ("%08x", edp->hwINFO); + dbg ("%08x", edp->hwTailP); + dbg ("%08x", edp->hwHeadP); + dbg ("%08x", edp->hwNextED); + } +} + +static char * hcfs2string (int state) +{ + switch (state) { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status (ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl (®s->revision) & 0xff; + if (temp != 0x10) + dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl (®s->control); + dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string (temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + + temp = readl (®s->cmdstatus); + dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + + ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); + ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); + + maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); + + maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); + maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); + + maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); + maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); + + maybe_print_eds ("donehead", readl (®s->donehead)); +} + +static void ohci_dump_roothub (ohci_t *controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + + if (verbose) { + dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b (controller); + dbg ("roothub.b: %08x PPCM=%04x DR=%04x", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status (controller); + dbg ("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump (ohci_t *controller, int verbose) +{ + dbg ("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status (controller); + if (verbose) + ep_print_int_eds (controller, "hcca"); + dbg ("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub (controller, 1); +} + + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + ohci_t *ohci; + ed_t * ed; + urb_priv_t *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* if we have an unfinished URB from previous transaction let's + * fail and scream as quickly as possible so as not to corrupt + * further communication */ + if (!urb_finished) { + err("sohci_submit_job: URB NOT FINISHED"); + return -1; + } + /* we're about to begin a new transaction here so mark the URB unfinished */ + urb_finished = 0; + + /* every endpoint has a ed, locate and fill it */ + if (!(ed = ep_add_ed (dev, pipe))) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype (pipe)) { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0)? 2: + (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc (dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv (purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv (purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link (ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number (struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + + return ohci_cpu_to_le16 (ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel (ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel (ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP); + + switch (ed->type) { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_controltail == ed) { + ohci->ed_controltail = ed->ed_prev; + } else { + ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_bulktail == ed) { + ohci->ed_bulktail = ed->ed_prev; + } else { + ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + } + ed->state = ED_UNLINK; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, + * but the USB stack is a little bit stateless so we do it at every transaction + * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK + * in all other cases the state is left unchanged + * the ed info fields are setted anyway even though most of them should not change */ + +static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | + (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc (usb_dev); + ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype (pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe) + | usb_pipeendpoint (pipe) << 7 + | (usb_pipeisoc (pipe)? 0x8000: 0) + | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) + | usb_pipeslow (pipe) << 13 + | usb_maxpacket (usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill (ohci_t *ohci, unsigned int info, + void *data, int len, + struct usb_device *dev, int index, urb_priv_t *urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td [index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32)data; +#ifdef OHCI_FILL_TRACE + if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); + printf("\n"); + } +#endif + if (!len) + data = 0; + + td->hwINFO = ohci_cpu_to_le32 (info); + td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data); + if (data) + td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1)); + else + td->hwBE = 0; + td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ +static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ + if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = 0; + + switch (usb_pipetype (pipe)) { + case PIPE_BULK: + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while(data_len > 4096) { + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill (ohci, info, setup, 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout (pipe)? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill (ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill (ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(td_t * td) +{ + __u32 tdINFO, tdBE, tdCBP; + urb_priv_t *lurb_priv = &urb_priv; + + tdINFO = ohci_cpu_to_le32 (td->hwINFO); + tdBE = ohci_cpu_to_le32 (td->hwBE); + tdCBP = ohci_cpu_to_le32 (td->hwCBP); + + + if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && + ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { + if (tdBE != 0) { + if (td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ + +static td_t * dl_reverse_done_list (ohci_t *ohci) +{ + __u32 td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + urb_priv_t *lurb_priv = NULL; + + td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0; + ohci->hcca->done_head = 0; + + while (td_list_hc) { + td_list = (td_t *)td_list_hc; + + if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) { + lurb_priv = &urb_priv; + dbg(" USB-error/status: %x : %p", + TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list); + if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) { + if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { + td_list->ed->hwHeadP = + (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) | + (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2)); + lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; + } else + td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); + } +#ifdef CONFIG_MPC5200 + td_list->hwNextTD = 0; +#endif + } + + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0; + } + return td_list; +} + +/*-------------------------------------------------------------------------*/ + +/* td done list */ +static int dl_done_list (ohci_t *ohci, td_t *td_list) +{ + td_t *td_list_next = NULL; + ed_t *ed; + int cc = 0; + int stat = 0; + /* urb_t *urb; */ + urb_priv_t *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + + while (td_list) { + td_list_next = td_list->next_dl_td; + + lurb_priv = &urb_priv; + tdINFO = ohci_cpu_to_le32 (td_list->hwINFO); + + ed = td_list->ed; + + dl_transfer_length(td_list); + + /* error code of transfer */ + cc = TD_CC_GET (tdINFO); + if (++(lurb_priv->td_cnt) == lurb_priv->length) { + if ((ed->state & (ED_OPER | ED_UNLINK)) + && (lurb_priv->state != URB_DEL)) { + dbg("ConditionCode %#x", cc); + stat = cc_to_error[cc]; + urb_finished = 1; + } + } + + if (ed->state != ED_NEW) { + edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0; + edTailP = ohci_cpu_to_le32 (ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink (ohci, ed); + } + + td_list = td_list_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + __u32 temp, ndp, i; + int res; + + res = -1; + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && + ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + void * data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u32 datab[4]; + __u8 *data_buf = (__u8 *)datab; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + +#ifdef DEBUG +urb_priv.actual_length = 0; +pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +#endif + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = m16_swap (cmd->value); + wIndex = m16_swap (cmd->index); + wLength = m16_swap (cmd->length); + + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(__u16 *) data_buf = m16_swap (1); OK (2); + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_CLASS: + *(__u32 *) data_buf = m32_swap ( + RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK (4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + OK(0); + case (RH_C_HUB_OVER_CURRENT): + WR_RH_STAT(RH_HS_OCIC); OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_POCI); OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); + case (RH_C_PORT_CONNECTION): + WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); + case (RH_C_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_PESC); OK (0); + case (RH_C_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); + case (RH_C_PORT_OVER_CURRENT): + WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); + case (RH_C_PORT_RESET): + WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); + case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PRS); + OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PES ); + OK (0); + } + break; + + case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; OK(len); + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; OK(len); + case (0x03): /* string descriptors */ + if(wValue==0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if(wValue==0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a (&gohci); + + data_buf [0] = 9; /* min length; */ + data_buf [1] = 0x29; + data_buf [2] = temp & RH_A_NDP; + data_buf [3] = 0; + if (temp & RH_A_PSM) /* per-port power switching? */ + data_buf [3] |= 0x1; + if (temp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf [3] |= 0x10; + else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + data_buf [3] |= 0x8; + + /* corresponds to data_buf[4-7] */ + datab [1] = 0; + data_buf [5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b (&gohci); + data_buf [7] = temp & RH_B_DR; + if (data_buf [2] < 7) { + data_buf [8] = 0xff; + } else { + data_buf [0] += 2; + data_buf [8] = (temp & RH_B_DR) >> 8; + data_buf [10] = data_buf [9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf [0], wLength)); + OK (len); + } + + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); + + case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); + + default: + dbg ("unsupported root hub command"); + stat = USB_ST_STALLED; + } + +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + + len = min_t(int, len, leni); + if (data != data_buf) + memcpy (data, data_buf, len); + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG + if (transfer_len) + urb_priv.actual_length = transfer_len; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); +#endif + + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#endif + if (!maxsize) { + err("submit_common_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { + err("sohci_submit_job failed"); + return -1; + } + + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if (usb_pipetype (pipe) == PIPE_BULK) + timeout = BULK_TO; + else + timeout = 100; + + /* wait for it to complete */ + for (;;) { + /* check whether the controller is done */ + stat = hc_interrupt(); + if (stat < 0) { + stat = USB_ST_CRC_ERR; + break; + } + + /* NOTE: since we are not interrupt driven in U-Boot and always + * handle only one URB at a time, we cannot assume the + * transaction finished on the first successful return from + * hc_interrupt().. unless the flag for current URB is set, + * meaning that all TD's to/from device got actually + * transferred and processed. If the current URB is not + * finished we need to re-iterate this loop so as + * hc_interrupt() gets called again as there needs to be some + * more TD's to process still */ + if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { + /* 0xff is returned for an SF-interrupt */ + break; + } + + if (--timeout) { + wait_ms(1); + if (!urb_finished) + dbg("\%"); + + } else { + err("CTL:TIMEOUT "); + dbg("submit_common_msg: TO status %x\n", stat); + stat = USB_ST_CRC_ERR; + urb_finished = 1; + break; + } + } +#if 0 + /* we got an Root Hub Status Change interrupt */ + if (got_rhsc) { +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + got_rhsc = 0; + /* abuse timeout */ + timeout = rh_check_port_status(&gohci); + if (timeout >= 0) { +#if 0 /* this does nothing useful, but leave it here in case that changes */ + /* the called routine adds 1 to the passed value */ + usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); +#endif + /* + * XXX + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } +#endif + + dev->status = stat; + dev->act_len = transfer_len; + +#ifdef DEBUG + pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); +#endif + + /* free TDs in urb_priv */ + urb_free_priv (&urb_priv); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + + info("submit_control_msg"); +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#endif + if (!maxsize) { + err("submit_control_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset (ohci_t *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ + writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ + info("USB HC TakeOver from SMM"); + while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { + wait_ms (10); + if (--smm_timeout == 0) { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", + ohci->slot_name, + readl (&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + ohci->hc_control = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel (OHCI_HCR, &ohci->regs->cmdstatus); + while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { + if (--timeout == 0) { + err("USB HC reset timed out!"); + return -1; + } + udelay (1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start (ohci_t * ohci) +{ + __u32 mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + + writel (0, &ohci->regs->ed_controlhead); + writel (0, &ohci->regs->ed_bulkhead); + + writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + + fminterval = 0x2edf; + writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel (fminterval, &ohci->regs->fminterval); + writel (0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel (mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel (mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel (mask, &ohci->regs->intrenable); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, + &ohci->regs->roothub.a); + writel (RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay ((roothub_a (ohci) >> 23) & 0x1fe); + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static int +hc_interrupt (void) +{ + ohci_t *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + if ((ohci->hcca->done_head != 0) && + !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { + + ints = OHCI_INTR_WDH; + + } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { + ohci->disabled++; + err ("%s device removed!", ohci->slot_name); + return -1; + + } else if ((ints &= readl (®s->intrenable)) == 0) { + dbg("hc_interrupt: returning..\n"); + return 0xff; + } + + /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ + + if (ints & OHCI_INTR_RHSC) { + got_rhsc = 1; + stat = 0xff; + } + + if (ints & OHCI_INTR_UE) { + ohci->disabled++; + err ("OHCI Unrecoverable Error, controller usb-%s disabled", + ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ + +#ifdef DEBUG + ohci_dump (ohci, 1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset (ohci); + return -1; + } + + if (ints & OHCI_INTR_WDH) { + writel (OHCI_INTR_WDH, ®s->intrdisable); + stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); + writel (OHCI_INTR_WDH, ®s->intrenable); + } + + if (ints & OHCI_INTR_SO) { + dbg("USB Schedule overrun\n"); + writel (OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) { + unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; + wait_ms(1); + writel (OHCI_INTR_SF, ®s->intrdisable); + if (ohci->ed_rm_list[frame] != NULL) + writel (OHCI_INTR_SF, ®s->intrenable); + stat = 0xff; + } + + writel (ints, ®s->intrstatus); + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci (ohci_t *ohci) +{ + dbg ("USB HC release ohci usb-%s", ohci->slot_name); + + if (!ohci->disabled) + hc_reset (ohci); +} + +/*-------------------------------------------------------------------------*/ + +/* + * low level initalisation routine, called from usb.c + */ +static char ohci_inited = 0; + +int usb_lowlevel_init(void) +{ + + /* Set the USB Clock */ + *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; + + /* remove all USB bits first before ORing in ours */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000; + + /* Activate USB port */ + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG; + + memset (&gohci, 0, sizeof (ohci_t)); + memset (&urb_priv, 0, sizeof (urb_priv_t)); + + /* align the storage */ + if ((__u32)&ghcca[0] & 0xff) { + err("HCCA not aligned!!"); + return -1; + } + phcca = &ghcca[0]; + info("aligned ghcca %p", phcca); + memset(&ohci_dev, 0, sizeof(struct ohci_device)); + if ((__u32)&ohci_dev.ed[0] & 0x7) { + err("EDs not aligned!!"); + return -1; + } + memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); + if ((__u32)gtd & 0x7) { + err("TDs not aligned!!"); + return -1; + } + ptd = gtd; + gohci.hcca = phcca; + memset (phcca, 0, sizeof (struct ohci_hcca)); + + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + gohci.regs = (struct ohci_regs *)MPC5XXX_USB; + + gohci.flags = 0; + gohci.slot_name = "mpc5200"; + + if (hc_reset (&gohci) < 0) { + hc_release_ohci (&gohci); + return -1; + } + + if (hc_start (&gohci) < 0) { + err ("can't start usb-%s", gohci.slot_name); + hc_release_ohci (&gohci); + return -1; + } + +#ifdef DEBUG + ohci_dump (&gohci, 1); +#endif + ohci_inited = 1; + urb_finished = 1; + + return 0; +} + +int usb_lowlevel_stop(void) +{ + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if (!ohci_inited) + return 0; + /* TODO release any interrupts, etc. */ + /* call hc_release_ohci() here ? */ + hc_reset (&gohci); + return 0; +} + +#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/mpc5xxx/usb_ohci.h b/cpu/mpc5xxx/usb_ohci.h new file mode 100644 index 0000000..884f1d5 --- /dev/null +++ b/cpu/mpc5xxx/usb_ohci.h @@ -0,0 +1,423 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +/* ED States */ + +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute((aligned(16))); +typedef struct ed ed_t; + + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ +#if defined(CONFIG_MPC5200) + __u16 pad1; /* set to 0 on each frame_no change */ + __u16 frame_no; /* current frame number */ +#else + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ +#endif + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute((aligned(256))); + + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute((aligned(32))); + + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct +{ + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + + +typedef struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma;*/ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +td_t gtd[NUM_TD+1]; +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td * +td_alloc (struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) + { + if (ptd[i].usb_dev == NULL) + { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void +ed_free (struct ed *ed) +{ + ed->usb_dev = NULL; +} diff --git a/cpu/mpc8220/Makefile b/cpu/mpc8220/Makefile new file mode 100644 index 0000000..7c9b6c9 --- /dev/null +++ b/cpu/mpc8220/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +ASOBJS = io.o fec_dma_tasks.o +OBJS = cpu.o cpu_init.o dramSetup.o fec.o i2c.o \ + interrupts.o loadtask.o speed.o \ + traps.o uart.o pci.o + +all: .depend $(START) $(ASOBJS) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(ASOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk new file mode 100644 index 0000000..6fec5df --- /dev/null +++ b/cpu/mpc8220/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \ + -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc8220/cpu.c b/cpu/mpc8220/cpu.c new file mode 100644 index 0000000..0cfe808 --- /dev/null +++ b/cpu/mpc8220/cpu.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code for the MPC8220 CPUs + */ + +#include +#include +#include +#include +#include + +int checkcpu (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong clock = gd->cpu_clk; + char buf[32]; + + puts ("CPU: "); + + printf (CPU_ID_STR); + + printf (" (JTAG ID %08lx)", *(vu_long *) (CFG_MBAR + 0x50)); + + printf (" at %s MHz\n", strmhz (buf, clock)); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + volatile gptmr8220_t *gptmr = (volatile gptmr8220_t *) MMAP_GPTMR; + ulong msr; + + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* Charge the watchdog timer */ + gptmr->Prescl = 10; + gptmr->Count = 1; + + gptmr->Mode = GPT_TMS_SGPIO; + + gptmr->Control = GPT_CTRL_WDEN | GPT_CTRL_CE; + + return 1; +} + +/* ------------------------------------------------------------------------- */ + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + * + */ +unsigned long get_tbclk (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong tbclk; + + tbclk = (gd->bus_clk + 3L) / 4L; + + return (tbclk); +} + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c new file mode 100644 index 0000000..8c358a8 --- /dev/null +++ b/cpu/mpc8220/cpu_init.c @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers. + */ +void cpu_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB; + volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG; + volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* Clear all port configuration */ + portcfg->pcfg0 = 0; + portcfg->pcfg1 = 0; + portcfg->pcfg2 = 0; + portcfg->pcfg3 = 0; + portcfg->pcfg2 = CFG_GP1_PORT2_CONFIG; + portcfg->pcfg3 = CFG_PCI_PORT3_CONFIG | CFG_GP2_PORT3_CONFIG; + + /* + * Flexbus Controller: configure chip selects and enable them + */ +#if defined (CFG_CS0_BASE) + flexbus->csar0 = CFG_CS0_BASE; + +/* Sorcery-C can hang-up after CTRL reg initialization */ +#if defined (CFG_CS0_CTRL) + flexbus->cscr0 = CFG_CS0_CTRL; +#endif + flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1; + __asm__ volatile ("sync"); +#endif +#if defined (CFG_CS1_BASE) + flexbus->csar1 = CFG_CS1_BASE; + flexbus->cscr1 = CFG_CS1_CTRL; + flexbus->csmr1 = ((CFG_CS1_MASK - 1) & 0xffff0000) | 1; + __asm__ volatile ("sync"); +#endif +#if defined (CFG_CS2_BASE) + flexbus->csar2 = CFG_CS2_BASE; + flexbus->cscr2 = CFG_CS2_CTRL; + flexbus->csmr2 = ((CFG_CS2_MASK - 1) & 0xffff0000) | 1; + portcfg->pcfg3 |= CFG_CS2_PORT3_CONFIG; + __asm__ volatile ("sync"); +#endif +#if defined (CFG_CS3_BASE) + flexbus->csar3 = CFG_CS3_BASE; + flexbus->cscr3 = CFG_CS3_CTRL; + flexbus->csmr3 = ((CFG_CS3_MASK - 1) & 0xffff0000) | 1; + portcfg->pcfg3 |= CFG_CS3_PORT3_CONFIG; + __asm__ volatile ("sync"); +#endif +#if defined (CFG_CS4_BASE) + flexbus->csar4 = CFG_CS4_BASE; + flexbus->cscr4 = CFG_CS4_CTRL; + flexbus->csmr4 = ((CFG_CS4_MASK - 1) & 0xffff0000) | 1; + portcfg->pcfg3 |= CFG_CS4_PORT3_CONFIG; + __asm__ volatile ("sync"); +#endif +#if defined (CFG_CS5_BASE) + flexbus->csar5 = CFG_CS5_BASE; + flexbus->cscr5 = CFG_CS5_CTRL; + flexbus->csmr5 = ((CFG_CS5_MASK - 1) & 0xffff0000) | 1; + portcfg->pcfg3 |= CFG_CS5_PORT3_CONFIG; + __asm__ volatile ("sync"); +#endif + + /* This section of the code cannot place in cpu_init_r(), + it will cause the system to hang */ + /* enable timebase */ + xlbarb->addrTenTimeOut = 0x1000; + xlbarb->dataTenTimeOut = 0x1000; + xlbarb->busActTimeOut = 0x2000; + + xlbarb->config = 0x00002000; + + /* Master Priority Enable */ + xlbarb->mastPriority = 0; + xlbarb->mastPriEn = 0xff; +} + +/* + * initialize higher level parts of CPU like time base and timers + */ +int cpu_init_r (void) +{ + /* this may belongs to disable interrupt section */ + /* mask all interrupts */ + *(vu_long *) 0xf0000700 = 0xfffffc00; + *(vu_long *) 0xf0000714 |= 0x0001ffff; + *(vu_long *) 0xf0000710 &= ~0x00000f00; + + /* route critical ints to normal ints */ + *(vu_long *) 0xf0000710 |= 0x00000001; + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC8220_FEC) + /* load FEC microcode */ + loadtask (0, 2); +#endif + return (0); +} diff --git a/cpu/mpc8220/dma.h b/cpu/mpc8220/dma.h new file mode 100644 index 0000000..d06ee63 --- /dev/null +++ b/cpu/mpc8220/dma.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on code + * (C) Copyright Motorola, Inc., 2000 + * + * MPC8220 dma header file + */ + +#ifndef __MPC8220_DMA_H +#define __MPC8220_DMA_H + +#include +#include + +/* Task number assignment */ +#define FEC_RECV_TASK_NO 0 +#define FEC_XMIT_TASK_NO 1 + +/*--------------------------------------------------------------------- + * Stuff for Ethernet Tx/Rx tasks + *--------------------------------------------------------------------- + */ + +/* Layout of Ethernet controller Parameter SRAM area: + * ---------------------------------------------------------------- + * 0x00: TBD_BASE, base address of TX BD ring + * 0x04: TBD_NEXT, address of next TX BD to be processed + * 0x08: RBD_BASE, base address of RX BD ring + * 0x0C: RBD_NEXT, address of next RX BD to be processed + * --------------------------------------------------------------- + * ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH). + */ + +/* base address of SRAM area to store parameters used by Ethernet tasks */ +#define FEC_PARAM_BASE (MMAP_SRAM + 0x5b00) + +/* base address of SRAM area for buffer descriptors */ +#define FEC_BD_BASE (MMAP_SRAM + 0x5b20) + +/*--------------------------------------------------------------------- + * common shortcuts used by driver C code + *--------------------------------------------------------------------- + */ + +/* Disable SmartDMA task */ +#define DMA_TASK_DISABLE(tasknum) \ +{ \ + volatile ushort *tcr = (ushort *)(MMAP_DMA + 0x0000001c + 2 * tasknum); \ + *tcr = (*tcr) & (~0x8000); \ +} + +/* Enable SmartDMA task */ +#define DMA_TASK_ENABLE(tasknum) \ +{ \ + volatile ushort *tcr = (ushort *) (MMAP_DMA + 0x0000001c + 2 * tasknum);\ + *tcr = (*tcr) | 0x8000; \ +} + +/* Clear interrupt pending bits */ +#define DMA_CLEAR_IEVENT(tasknum) \ +{ \ + struct mpc8220_dma *dma = (struct mpc8220_dma *)MMAP_DMA; \ + dma->IntPend = (1 << tasknum); \ +} + +#endif /* __MPC8220_DMA_H */ diff --git a/cpu/mpc8220/dramSetup.c b/cpu/mpc8220/dramSetup.c new file mode 100644 index 0000000..1d0d384 --- /dev/null +++ b/cpu/mpc8220/dramSetup.c @@ -0,0 +1,754 @@ +/* + * (C) Copyright 2004, Freescale, Inc + * TsiChung Liew, Tsi-Chung.Liew@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +DESCRIPTION +Read Dram spd and base on its information to calculate the memory size, +characteristics to initialize the dram on MPC8220 +*/ + +#include +#include +#include "i2cCore.h" +#include "dramSetup.h" + +#define SPD_SIZE CFG_SDRAM_SPD_SIZE +#define DRAM_SPD (CFG_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */ +#define TOTAL_BANK CFG_SDRAM_TOTAL_BANKS + +int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse) +{ + int i; + + for (i = 0; i < I2C_POLL_COUNT; i++) { + if ((pi2c->sr & sta_bit) == (truefalse ? sta_bit : 0)) + return (OK); + } + + return (ERROR); +} + +int spd_clear (volatile i2c8220_t * pi2c) +{ + pi2c->adr = 0; + pi2c->fdr = 0; + pi2c->cr = 0; + pi2c->sr = 0; + + return (OK); +} + +int spd_stop (volatile i2c8220_t * pi2c) +{ + pi2c->cr &= ~I2C_CTL_STA; /* Generate stop signal */ + if (spd_status (pi2c, I2C_STA_BB, 0) != OK) + return ERROR; + + return (OK); +} + +int spd_readbyte (volatile i2c8220_t * pi2c, u8 * readb, int *index) +{ + pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt Bit */ + *readb = pi2c->dr; /* Read a byte */ + + /* + Set I2C_CTRL_TXAK will cause Transfer pending and + set I2C_CTRL_STA will cause Interrupt pending + */ + if (*index != 2) { + if (spd_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */ + return ERROR; + } + + if (*index != 1) { + if (spd_status (pi2c, I2C_STA_IF, 1) != OK) + return ERROR; + } + + return (OK); +} + +int readSpdData (u8 * spdData) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile i2c8220_t *pi2cReg; + volatile pcfg8220_t *pcfg; + u8 slvAdr = DRAM_SPD; + u8 Tmp; + int Length = SPD_SIZE; + int i = 0; + + /* Enable Port Configuration for SDA and SDL signals */ + pcfg = (volatile pcfg8220_t *) (MMAP_PCFG); + __asm__ ("sync"); + pcfg->pcfg3 &= ~CFG_I2C_PORT3_CONFIG; + __asm__ ("sync"); + + /* Points the structure to I2c mbar memory offset */ + pi2cReg = (volatile i2c8220_t *) (MMAP_I2C); + + + /* Clear FDR, ADR, SR and CR reg */ + pi2cReg->adr = 0; + pi2cReg->fdr = 0; + pi2cReg->cr = 0; + pi2cReg->sr = 0; + + /* Set for fix XLB Bus Frequency */ + switch (gd->bus_clk) { + case 60000000: + pi2cReg->fdr = 0x15; + break; + case 70000000: + pi2cReg->fdr = 0x16; + break; + case 80000000: + pi2cReg->fdr = 0x3a; + break; + case 90000000: + pi2cReg->fdr = 0x17; + break; + case 100000000: + pi2cReg->fdr = 0x3b; + break; + case 110000000: + pi2cReg->fdr = 0x18; + break; + case 120000000: + pi2cReg->fdr = 0x19; + break; + case 130000000: + pi2cReg->fdr = 0x1a; + break; + } + + pi2cReg->adr = CFG_I2C_SLAVE<<1; + + pi2cReg->cr = I2C_CTL_EN; /* Set Enable */ + + /* + The I2C bus should be in Idle state. If the bus is busy, + clear the STA bit in control register + */ + if (spd_status (pi2cReg, I2C_STA_BB, 0) != OK) { + if ((pi2cReg->cr & I2C_CTL_STA) == I2C_CTL_STA) + pi2cReg->cr &= ~I2C_CTL_STA; + + /* Check again if it is still busy, return error if found */ + if (spd_status (pi2cReg, I2C_STA_BB, 1) == OK) + return ERROR; + } + + pi2cReg->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */ + pi2cReg->cr |= I2C_CTL_STA; /* Generate start signal */ + + if (spd_status (pi2cReg, I2C_STA_BB, 1) != OK) + return ERROR; + + + /* Write slave address */ + pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */ + pi2cReg->dr = slvAdr; /* Write a byte */ + + if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */ + spd_stop (pi2cReg); + return ERROR; + } + + if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) { + spd_stop (pi2cReg); + return ERROR; + } + + + /* Issue the offset to start */ + pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */ + pi2cReg->dr = 0; /* Write a byte */ + + if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */ + spd_stop (pi2cReg); + return ERROR; + } + + if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) { + spd_stop (pi2cReg); + return ERROR; + } + + + /* Set repeat start */ + pi2cReg->cr |= I2C_CTL_RSTA; /* Repeat Start */ + + pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */ + pi2cReg->dr = slvAdr | 1; /* Write a byte */ + + if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */ + spd_stop (pi2cReg); + return ERROR; + } + + if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) { + spd_stop (pi2cReg); + return ERROR; + } + + if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01)) + return ERROR; + + pi2cReg->cr &= ~I2C_CTL_TX; /* Set receive mode */ + + if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01)) + return ERROR; + + /* Dummy Read */ + if (spd_readbyte (pi2cReg, &Tmp, &i) != OK) { + spd_stop (pi2cReg); + return ERROR; + } + + i = 0; + while (Length) { + if (Length == 2) + pi2cReg->cr |= I2C_CTL_TXAK; + + if (Length == 1) + pi2cReg->cr &= ~I2C_CTL_STA; + + if (spd_readbyte (pi2cReg, spdData, &Length) != OK) { + return spd_stop (pi2cReg); + } + i++; + Length--; + spdData++; + } + + /* Stop the service */ + spd_stop (pi2cReg); + + return OK; +} + +int getBankInfo (int bank, draminfo_t * pBank) +{ + int status; + int checksum; + int count; + u8 spdData[SPD_SIZE]; + + + if (bank > 2 || pBank == 0) { + /* illegal values */ + return (-42); + } + + status = readSpdData (&spdData[0]); + if (status < 0) + return (-1); + + /* check the checksum */ + for (count = 0, checksum = 0; count < LOC_CHECKSUM; count++) + checksum += spdData[count]; + + checksum = checksum - ((checksum / 256) * 256); + + if (checksum != spdData[LOC_CHECKSUM]) + return (-2); + + /* Get the memory type */ + if (! + ((spdData[LOC_TYPE] == TYPE_DDR) + || (spdData[LOC_TYPE] == TYPE_SDR))) + /* not one of the types we support */ + return (-3); + + pBank->type = spdData[LOC_TYPE]; + + /* Set logical banks */ + pBank->banks = spdData[LOC_LOGICAL_BANKS]; + + /* Check that we have enough physical banks to cover the bank we are + * figuring out. Odd-numbered banks correspond to the second bank + * on the device. + */ + if (bank & 1) { + /* Second bank of a "device" */ + if (spdData[LOC_PHYS_BANKS] < 2) + /* this bank doesn't exist on the "device" */ + return (-4); + + if (spdData[LOC_ROWS] & 0xf0) + /* Two asymmetric banks */ + pBank->rows = spdData[LOC_ROWS] >> 4; + else + pBank->rows = spdData[LOC_ROWS]; + + if (spdData[LOC_COLS] & 0xf0) + /* Two asymmetric banks */ + pBank->cols = spdData[LOC_COLS] >> 4; + else + pBank->cols = spdData[LOC_COLS]; + } else { + /* First bank of a "device" */ + pBank->rows = spdData[LOC_ROWS]; + pBank->cols = spdData[LOC_COLS]; + } + + pBank->width = spdData[LOC_WIDTH_HIGH] << 8 | spdData[LOC_WIDTH_LOW]; + pBank->bursts = spdData[LOC_BURSTS]; + pBank->CAS = spdData[LOC_CAS]; + pBank->CS = spdData[LOC_CS]; + pBank->WE = spdData[LOC_WE]; + pBank->Trp = spdData[LOC_Trp]; + pBank->Trcd = spdData[LOC_Trcd]; + pBank->buffered = spdData[LOC_Buffered] & 1; + pBank->refresh = spdData[LOC_REFRESH]; + + return (0); +} + + +/* checkMuxSetting -- given a row/column device geometry, return a mask + * of the valid DRAM controller addr_mux settings for + * that geometry. + * + * Arguments: u8 rows: number of row addresses in this device + * u8 columns: number of column addresses in this device + * + * Returns: a mask of the allowed addr_mux settings for this + * geometry. Each bit in the mask represents a + * possible addr_mux settings (for example, the + * (1<<2) bit in the mask represents the 0b10 setting)/ + * + */ +u8 checkMuxSetting (u8 rows, u8 columns) +{ + muxdesc_t *pIdx, *pMux; + u8 mask; + int lrows, lcolumns; + u32 mux[4] = { 0x00080c04, 0x01080d03, 0x02080e02, 0xffffffff }; + + /* Setup MuxDescriptor in SRAM space */ + /* MUXDESC AddressRuns [] = { + { 0, 8, 12, 4 }, / setting, columns, rows, extra columns / + { 1, 8, 13, 3 }, / setting, columns, rows, extra columns / + { 2, 8, 14, 2 }, / setting, columns, rows, extra columns / + { 0xff } / list terminator / + }; */ + + pIdx = (muxdesc_t *) & mux[0]; + + /* Check rows x columns against each possible address mux setting */ + for (pMux = pIdx, mask = 0;; pMux++) { + lrows = rows; + lcolumns = columns; + + if (pMux->MuxValue == 0xff) + break; /* end of list */ + + /* For a given mux setting, since we want all the memory in a + * device to be contiguous, we want the device "use up" the + * address lines such that there are no extra column or row + * address lines on the device. + */ + + lcolumns -= pMux->Columns; + if (lcolumns < 0) + /* Not enough columns to get to the rows */ + continue; + + lrows -= pMux->Rows; + if (lrows > 0) + /* we have extra rows left -- can't do that! */ + continue; + + /* At this point, we either have to have used up all the + * rows or we have to have no columns left. + */ + + if (lcolumns != 0 && lrows != 0) + /* rows AND columns are left. Bad! */ + continue; + + lcolumns -= pMux->MoreColumns; + + if (lcolumns <= 0) + mask |= (1 << pMux->MuxValue); + } + + return (mask); +} + + +u32 dramSetup (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + draminfo_t DramInfo[TOTAL_BANK]; + draminfo_t *pDramInfo; + u32 size, temp, cfg_value, mode_value, refresh; + u8 *ptr; + u8 bursts, Trp, Trcd, type, buffered; + u8 muxmask, rows, columns; + int count, banknum; + u32 *prefresh, *pIdx; + u32 refrate[8] = { 15625, 3900, 7800, 31300, + 62500, 125000, 0xffffffff, 0xffffffff + }; + volatile sysconf8220_t *sysconf; + volatile memctl8220_t *memctl; + + sysconf = (volatile sysconf8220_t *) MMAP_MBAR; + memctl = (volatile memctl8220_t *) MMAP_MEMCTL; + + /* Set everything in the descriptions to zero */ + ptr = (u8 *) & DramInfo[0]; + for (count = 0; count < sizeof (DramInfo); count++) + *ptr++ = 0; + + for (banknum = 0; banknum < TOTAL_BANK; banknum++) + sysconf->cscfg[banknum]; + + /* Descriptions of row/column address muxing for various + * addr_mux settings. + */ + + pIdx = prefresh = (u32 *) & refrate[0]; + + /* Get all the info for all three logical banks */ + bursts = 0xff; + Trp = 0; + Trcd = 0; + type = 0; + buffered = 0xff; + refresh = 0xffffffff; + muxmask = 0xff; + + /* Two bank, CS0 and CS1 */ + for (banknum = 0, pDramInfo = &DramInfo[0]; + banknum < TOTAL_BANK; banknum++, pDramInfo++) { + pDramInfo->ordinal = banknum; /* initial sorting */ + if (getBankInfo (banknum, pDramInfo) < 0) + continue; + + /* get cumulative parameters of all three banks */ + if (type && pDramInfo->type != type) + return 0; + + type = pDramInfo->type; + rows = pDramInfo->rows; + columns = pDramInfo->cols; + + /* This chip only supports 13 DRAM memory lines, but some devices + * have 14 rows. To deal with this, ignore the 14th address line + * by limiting the number of rows (and columns) to 13. This will + * mean that for 14-row devices we will only be able to use + * half of the memory, but it's better than nothing. + */ + if (rows > 13) + rows = 13; + if (columns > 13) + columns = 13; + + pDramInfo->size = + ((1 << (rows + columns)) * pDramInfo->width); + pDramInfo->size *= pDramInfo->banks; + pDramInfo->size >>= 3; + + /* figure out which addr_mux configurations will support this device */ + muxmask &= checkMuxSetting (rows, columns); + if (muxmask == 0) + return 0; + + buffered = pDramInfo->buffered; + bursts &= pDramInfo->bursts; /* union of all bursts */ + if (pDramInfo->Trp > Trp) /* worst case (longest) Trp */ + Trp = pDramInfo->Trp; + + if (pDramInfo->Trcd > Trcd) /* worst case (longest) Trcd */ + Trcd = pDramInfo->Trcd; + + prefresh = pIdx; + /* worst case (shortest) Refresh period */ + if (refresh > prefresh[pDramInfo->refresh & 7]) + refresh = prefresh[pDramInfo->refresh & 7]; + + } /* for loop */ + + + /* We only allow a burst length of 8! */ + if (!(bursts & 8)) + bursts = 8; + + /* Sort the devices. In order to get each chip select region + * aligned properly, put the biggest device at the lowest address. + * A simple bubble sort will do the trick. + */ + for (banknum = 0, pDramInfo = &DramInfo[0]; + banknum < TOTAL_BANK; banknum++, pDramInfo++) { + int i; + + for (i = 0; i < TOTAL_BANK; i++) { + if (pDramInfo->size < DramInfo[i].size && + pDramInfo->ordinal < DramInfo[i].ordinal) { + /* If the current bank is smaller, but if the ordinal is also + * smaller, swap the ordinals + */ + u8 temp8; + + temp8 = DramInfo[i].ordinal; + DramInfo[i].ordinal = pDramInfo->ordinal; + pDramInfo->ordinal = temp8; + } + } + } + + + /* Now figure out the base address for each bank. While + * we're at it, figure out how much memory there is. + * + */ + size = 0; + for (banknum = 0; banknum < TOTAL_BANK; banknum++) { + int i; + + for (i = 0; i < TOTAL_BANK; i++) { + if (DramInfo[i].ordinal == banknum + && DramInfo[i].size != 0) { + DramInfo[i].base = size; + size += DramInfo[i].size; + } + } + } + + /* Set up the Drive Strength register */ + sysconf->sdramds = CFG_SDRAM_DRIVE_STRENGTH; + + /* ********************** Cfg 1 ************************* */ + + /* Set the single read to read/write/precharge delay */ + cfg_value = CFG1_SRD2RWP ((type == TYPE_DDR) ? 7 : 0xb); + + /* Set the single write to read/write/precharge delay. + * This may or may not be correct. The controller spec + * says "tWR", but "tWR" does not appear in the SPD. It + * always seems to be 15nsec for the class of device we're + * using, which turns out to be 2 clock cycles at 133MHz, + * so that's what we're going to use. + * + * HOWEVER, because of a bug in the controller, for DDR + * we need to set this to be the same as the value + * calculated for bwt2rwp. + */ + cfg_value |= CFG1_SWT2RWP ((type == TYPE_DDR) ? 7 : 2); + + /* Set the Read CAS latency. We're going to use a CL of + * 2.5 for DDR and 2 SDR. + */ + cfg_value |= CFG1_RLATENCY ((type == TYPE_DDR) ? 7 : 2); + + + /* Set the Active to Read/Write delay. This depends + * on Trcd which is reported as nanoseconds times 4. + * We want to calculate Trcd (in nanoseconds) times XLB clock (in Hz) + * which gives us a dimensionless quantity. Play games with + * the divisions so we don't run out of dynamic ranges. + */ + /* account for megaherz and the times 4 */ + temp = (Trcd * (gd->bus_clk / 1000000)) / 4; + + /* account for nanoseconds and round up, with a minimum value of 2 */ + temp = ((temp + 999) / 1000) - 1; + if (temp < 2) + temp = 2; + + cfg_value |= CFG1_ACT2WR (temp); + + /* Set the precharge to active delay. This depends + * on Trp which is reported as nanoseconds times 4. + * We want to calculate Trp (in nanoseconds) times XLB clock (in Hz) + * which gives us a dimensionless quantity. Play games with + * the divisions so we don't run out of dynamic ranges. + */ + /* account for megaherz and the times 4 */ + temp = (Trp * (gd->bus_clk / 1000000)) / 4; + + /* account for nanoseconds and round up, then subtract 1, with a + * minumum value of 1 and a maximum value of 7. + */ + temp = (((temp + 999) / 1000) - 1) & 7; + if (temp < 1) + temp = 1; + + cfg_value |= CFG1_PRE2ACT (temp); + + /* Set refresh to active delay. This depends + * on Trfc which is not reported in the SPD. + * We'll use a nominal value of 75nsec which is + * what the controller spec uses. + */ + temp = (75 * (gd->bus_clk / 1000000)); + /* account for nanoseconds and round up, then subtract 1 */ + cfg_value |= CFG1_REF2ACT (((temp + 999) / 1000) - 1); + + /* Set the write latency, using the values given in the controller spec */ + cfg_value |= CFG1_WLATENCY ((type == TYPE_DDR) ? 3 : 0); + memctl->cfg1 = cfg_value; /* cfg 1 */ + asm volatile ("sync"); + + + /* ********************** Cfg 2 ************************* */ + + /* Set the burst read to read/precharge delay */ + cfg_value = CFG2_BRD2RP ((type == TYPE_DDR) ? 5 : 8); + + /* Set the burst write to read/precharge delay. Semi-magic numbers + * based on the controller spec recommendations, assuming tWR is + * two clock cycles. + */ + cfg_value |= CFG2_BWT2RWP ((type == TYPE_DDR) ? 7 : 10); + + /* Set the Burst read to write delay. Semi-magic numbers + * based on the DRAM controller documentation. + */ + cfg_value |= CFG2_BRD2WT ((type == TYPE_DDR) ? 7 : 0xb); + + /* Set the burst length -- must be 8!! Well, 7, actually, becuase + * it's burst lenght minus 1. + */ + cfg_value |= CFG2_BURSTLEN (7); + memctl->cfg2 = cfg_value; /* cfg 2 */ + asm volatile ("sync"); + + + /* ********************** mode ************************* */ + + /* Set enable bit, CKE high/low bits, and the DDR/SDR mode bit, + * disable automatic refresh. + */ + cfg_value = CTL_MODE_ENABLE | CTL_CKE_HIGH | + ((type == TYPE_DDR) ? CTL_DDR_MODE : 0); + + /* Set the address mux based on whichever setting(s) is/are common + * to all the devices we have. If there is more than one, choose + * one arbitrarily. + */ + if (muxmask & 0x4) + cfg_value |= CTL_ADDRMUX (2); + else if (muxmask & 0x2) + cfg_value |= CTL_ADDRMUX (1); + else + cfg_value |= CTL_ADDRMUX (0); + + /* Set the refresh interval. */ + temp = ((refresh * (gd->bus_clk / 1000000)) / (1000 * 64)) - 1; + cfg_value |= CTL_REFRESH_INTERVAL (temp); + + /* Set buffered/non-buffered memory */ + if (buffered) + cfg_value |= CTL_BUFFERED; + + memctl->ctrl = cfg_value; /* ctrl */ + asm volatile ("sync"); + + if (type == TYPE_DDR) { + /* issue precharge all */ + temp = cfg_value | CTL_PRECHARGE_CMD; + memctl->ctrl = temp; /* ctrl */ + asm volatile ("sync"); + } + + + /* Set up mode value for CAS latency */ +#if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */ + mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) | + MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD); +#else + mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) | + MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2) | MODE_CMD); +#endif + asm volatile ("sync"); + + /* Write Extended Mode - enable DLL */ + if (type == TYPE_DDR) { + temp = MODE_EXTENDED | MODE_X_DLL_ENABLE | + MODE_X_DS_NORMAL | MODE_CMD; + memctl->mode = (temp >> 16); /* mode */ + asm volatile ("sync"); + + /* Write Mode - reset DLL, set CAS latency */ + temp = mode_value | MODE_OPMODE (MODE_OPMODE_RESETDLL); + memctl->mode = (temp >> 16); /* mode */ + asm volatile ("sync"); + } + + /* Program the chip selects. */ + for (banknum = 0; banknum < TOTAL_BANK; banknum++) { + if (DramInfo[banknum].size != 0) { + u32 mask; + int i; + + for (i = 0, mask = 1; i < 32; mask <<= 1, i++) { + if (DramInfo[banknum].size & mask) + break; + } + temp = (DramInfo[banknum].base & 0xfff00000) | (i - + 1); + + sysconf->cscfg[banknum] = temp; + asm volatile ("sync"); + } + } + + /* Wait for DLL lock */ + udelay (200); + + temp = cfg_value | CTL_PRECHARGE_CMD; /* issue precharge all */ + memctl->ctrl = temp; /* ctrl */ + asm volatile ("sync"); + + temp = cfg_value | CTL_REFRESH_CMD; /* issue precharge all */ + memctl->ctrl = temp; /* ctrl */ + asm volatile ("sync"); + + memctl->ctrl = temp; /* ctrl */ + asm volatile ("sync"); + + /* Write Mode - DLL normal */ + temp = mode_value | MODE_OPMODE (MODE_OPMODE_NORMAL); + memctl->mode = (temp >> 16); /* mode */ + asm volatile ("sync"); + + /* Enable refresh, enable DQS's (if DDR), and lock the control register */ + cfg_value &= ~CTL_MODE_ENABLE; /* lock register */ + cfg_value |= CTL_REFRESH_ENABLE; /* enable refresh */ + + if (type == TYPE_DDR) + cfg_value |= CTL_DQSOEN (0xf); /* enable DQS's for DDR */ + + memctl->ctrl = cfg_value; /* ctrl */ + asm volatile ("sync"); + + return size; +} diff --git a/cpu/mpc8220/dramSetup.h b/cpu/mpc8220/dramSetup.h new file mode 100644 index 0000000..3b64e08 --- /dev/null +++ b/cpu/mpc8220/dramSetup.h @@ -0,0 +1,108 @@ +/* + * dramSetup.h + * + * Prototypes, etc. for the Motorola MPC8220 + * embedded cpu chips + * + * 2004 (c) Freescale, Inc. + * Author: TsiChung Liew + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __INCdramsetuph +#define __INCdramsetuph +#ifndef __ASSEMBLY__ +/* Where various things are in the SPD */ +#define LOC_TYPE 2 +#define LOC_CHECKSUM 63 +#define LOC_PHYS_BANKS 5 +#define LOC_LOGICAL_BANKS 17 +#define LOC_ROWS 3 +#define LOC_COLS 4 +#define LOC_WIDTH_HIGH 7 +#define LOC_WIDTH_LOW 6 +#define LOC_REFRESH 12 +#define LOC_BURSTS 16 +#define LOC_CAS 18 +#define LOC_CS 19 +#define LOC_WE 20 +#define LOC_Tcyc 9 +#define LOC_Tac 10 +#define LOC_Trp 27 +#define LOC_Trrd 28 +#define LOC_Trcd 29 +#define LOC_Tras 30 +#define LOC_Buffered 21 +/* Types of memory the SPD can tell us about. + * We can actually only use SDRAM and DDR. + */ +#define TYPE_DRAM 1 /* plain old dram */ +#define TYPE_EDO 2 /* EDO dram */ +#define TYPE_Nibble 3 /* serial nibble memory */ +#define TYPE_SDR 4 /* SDRAM */ +#define TYPE_ROM 5 /* */ +#define TYPE_SGRRAM 6 /* graphics memory */ +#define TYPE_DDR 7 /* DDR sdram */ +#define SDRAMDS_MASK 0x3 /* each field is 2 bits wide */ +#define SDRAMDS_SBE_SHIFT 8 /* Clock enable drive strength */ +#define SDRAMDS_SBC_SHIFT 6 /* Clocks drive strength */ +#define SDRAMDS_SBA_SHIFT 4 /* Address drive strength */ +#define SDRAMDS_SBS_SHIFT 2 /* SDR DQS drive strength */ +#define SDRAMDS_SBD_SHIFT 0 /* Data and DQS drive strength */ +#define DRIVE_STRENGTH_HIGH 0 +#define DRIVE_STRENGTH_MED 1 +#define DRIVE_STRENGTH_LOW 2 +#define DRIVE_STRENGTH_OFF 3 + +#define OK 0 +#define ERROR -1 +/* Structure to hold information about address muxing. */ + typedef struct tagMuxDescriptor { + u8 MuxValue; + u8 Columns; + u8 Rows; + u8 MoreColumns; +} muxdesc_t; + +/* Structure to define one physical bank of + * memory. Note that dram size in bytes is + * (2^^(rows+columns)) * width * banks / 8 +*/ +typedef struct tagDramInfo { + u32 size; /* size in bytes */ + u32 base; /* base address */ + u8 ordinal; /* where in the memory map will we put this */ + u8 type; + u8 rows; + u8 cols; + u16 width; /* width of each chip in bits */ + u8 banks; /* number of chips, aka logical banks */ + u8 bursts; /* bit-encoded allowable burst length */ + u8 CAS; /* bit-encoded CAS latency values */ + u8 CS; /* bit-encoded CS latency values */ + u8 WE; /* bit-encoded WE latency values */ + u8 Trp; /* bit-encoded row precharge time */ + u8 Trcd; /* bit-encoded RAS to CAS delay */ + u8 buffered; /* buffered or not */ + u8 refresh; /* encoded refresh rate */ +} draminfo_t; + +#endif /* __ASSEMBLY__ */ + +#endif /* __INCdramsetuph */ diff --git a/cpu/mpc8220/fec.c b/cpu/mpc8220/fec.c new file mode 100644 index 0000000..1201e79 --- /dev/null +++ b/cpu/mpc8220/fec.c @@ -0,0 +1,1000 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on mpc4200fec.c, + * (C) Copyright Motorola, Inc., 2000 + */ + +#include +#include +#include +#include +#include +#include "dma.h" +#include "fec.h" + +#undef DEBUG +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_MPC8220_FEC) + +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#ifdef DEBUG +static void tfifo_print (char *devname, mpc8220_fec_priv * fec); +static void rfifo_print (char *devname, mpc8220_fec_priv * fec); +#endif /* DEBUG */ + +#ifdef DEBUG +static u32 local_crc32 (char *string, unsigned int crc_value, int len); +#endif + +typedef struct { + u8 data[1500]; /* actual data */ + int length; /* actual length */ + int used; /* buffer in use or not */ + u8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ +} NBUF; + +int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal); +int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data); + +/********************************************************************/ +#ifdef DEBUG +static void mpc8220_fec_phydump (char *devname) +{ + u16 phyStatus, i; + u8 phyAddr = CONFIG_PHY_ADDR; + u8 reg_mask[] = { +#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */ + /* regs to print: 0...7, 16...19, 21, 23, 24 */ + 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, +#else + /* regs to print: 0...8, 16...20 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +#endif + }; + + for (i = 0; i < 32; i++) { + if (reg_mask[i]) { + miiphy_read (devname, phyAddr, i, &phyStatus); + printf ("Mii reg %d: 0x%04x\n", i, phyStatus); + } + } +} +#endif + +/********************************************************************/ +static int mpc8220_fec_rbd_init (mpc8220_fec_priv * fec) +{ + int ix; + char *data; + static int once = 0; + + for (ix = 0; ix < FEC_RBD_NUM; ix++) { + if (!once) { + data = (char *) malloc (FEC_MAX_PKT_SIZE); + if (data == NULL) { + printf ("RBD INIT FAILED\n"); + return -1; + } + fec->rbdBase[ix].dataPointer = (u32) data; + } + fec->rbdBase[ix].status = FEC_RBD_EMPTY; + fec->rbdBase[ix].dataLength = 0; + } + once++; + + /* + * have the last RBD to close the ring + */ + fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP; + fec->rbdIndex = 0; + + return 0; +} + +/********************************************************************/ +static void mpc8220_fec_tbd_init (mpc8220_fec_priv * fec) +{ + int ix; + + for (ix = 0; ix < FEC_TBD_NUM; ix++) { + fec->tbdBase[ix].status = 0; + } + + /* + * Have the last TBD to close the ring + */ + fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP; + + /* + * Initialize some indices + */ + fec->tbdIndex = 0; + fec->usedTbdIndex = 0; + fec->cleanTbdNum = FEC_TBD_NUM; +} + +/********************************************************************/ +static void mpc8220_fec_rbd_clean (mpc8220_fec_priv * fec, FEC_RBD * pRbd) +{ + /* + * Reset buffer descriptor as empty + */ + if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) + pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); + else + pRbd->status = FEC_RBD_EMPTY; + + pRbd->dataLength = 0; + + /* + * Now, we have an empty RxBD, restart the SmartDMA receive task + */ + DMA_TASK_ENABLE (FEC_RECV_TASK_NO); + + /* + * Increment BD count + */ + fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; +} + +/********************************************************************/ +static void mpc8220_fec_tbd_scrub (mpc8220_fec_priv * fec) +{ + FEC_TBD *pUsedTbd; + +#ifdef DEBUG + printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", + fec->cleanTbdNum, fec->usedTbdIndex); +#endif + + /* + * process all the consumed TBDs + */ + while (fec->cleanTbdNum < FEC_TBD_NUM) { + pUsedTbd = &fec->tbdBase[fec->usedTbdIndex]; + if (pUsedTbd->status & FEC_TBD_READY) { +#ifdef DEBUG + printf ("Cannot clean TBD %d, in use\n", + fec->cleanTbdNum); +#endif + return; + } + + /* + * clean this buffer descriptor + */ + if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) + pUsedTbd->status = FEC_TBD_WRAP; + else + pUsedTbd->status = 0; + + /* + * update some indeces for a correct handling of the TBD ring + */ + fec->cleanTbdNum++; + fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; + } +} + +/********************************************************************/ +static void mpc8220_fec_set_hwaddr (mpc8220_fec_priv * fec, char *mac) +{ + u8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + u32 crc = 0xffffffff; /* initial value */ + + /* + * The algorithm used is the following: + * we loop on each of the six bytes of the provided address, + * and we compute the CRC by left-shifting the previous + * value by one position, so that each bit in the current + * byte of the address may contribute the calculation. If + * the latter and the MSB in the CRC are different, then + * the CRC value so computed is also ex-ored with the + * "polynomium generator". The current byte of the address + * is also shifted right by one bit at each iteration. + * This is because the CRC generatore in hardware is implemented + * as a shift-register with as many ex-ores as the radixes + * in the polynomium. This suggests that we represent the + * polynomiumm itself as a 32-bit constant. + */ + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* + * Set individual hash table register + */ + if (crc >= 32) { + fec->eth->iaddr1 = (1 << (crc - 32)); + fec->eth->iaddr2 = 0; + } else { + fec->eth->iaddr1 = 0; + fec->eth->iaddr2 = (1 << crc); + } + + /* + * Set physical address + */ + fec->eth->paddr1 = + (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; + fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; +} + +/********************************************************************/ +static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis) +{ + mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv; + struct mpc8220_dma *dma = (struct mpc8220_dma *) MMAP_DMA; + const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ + +#ifdef DEBUG + printf ("mpc8220_fec_init... Begin\n"); +#endif + + /* + * Initialize RxBD/TxBD rings + */ + mpc8220_fec_rbd_init (fec); + mpc8220_fec_tbd_init (fec); + + /* + * Set up Pin Muxing for FEC 1 + */ + *(vu_long *) MMAP_PCFG = 0; + *(vu_long *) (MMAP_PCFG + 4) = 0; + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + /* + * Set FEC-Lite receive control register(R_CNTRL): + */ + if (fec->xcv_type == SEVENWIRE) { + /* + * Frame length=1518; 7-wire mode + */ + fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */ + } else { + /* + * Frame length=1518; MII mode; + */ + fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */ + } + + fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */ + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + */ + /* tbd - rtm */ + /*fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); */ + /* No MII for 7-wire mode */ + fec->eth->mii_speed = 0x00000030; + } + + /* + * Set Opcode/Pause Duration Register + */ + fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */ + + /* + * Set Rx FIFO alarm and granularity value + */ + fec->eth->rfifo_cntrl = 0x0c000000; + fec->eth->rfifo_alarm = 0x0000030c; +#ifdef DEBUG + if (fec->eth->rfifo_status & 0x00700000) { + printf ("mpc8220_fec_init() RFIFO error\n"); + } +#endif + + /* + * Set Tx FIFO granularity value + */ + /*fec->eth->tfifo_cntrl = 0x0c000000; */ /*tbd - rtm */ + fec->eth->tfifo_cntrl = 0x0e000000; +#ifdef DEBUG + printf ("tfifo_status: 0x%08x\n", fec->eth->tfifo_status); + printf ("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm); +#endif + + /* + * Set transmit fifo watermark register(X_WMRK), default = 64 + */ + fec->eth->tfifo_alarm = 0x00000080; + fec->eth->x_wmrk = 0x2; + + /* + * Set individual address filter for unicast address + * and set physical address registers. + */ + mpc8220_fec_set_hwaddr (fec, (char *)(dev->enetaddr)); + + /* + * Set multicast address filter + */ + fec->eth->gaddr1 = 0x00000000; + fec->eth->gaddr2 = 0x00000000; + + /* + * Turn ON cheater FSM: ???? + */ + fec->eth->xmit_fsm = 0x03000000; + +#if 1 +/*#if defined(CONFIG_MPC5200)*/ + /* + * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't + * work w/ the current receive task. + */ + dma->PtdCntrl |= 0x00000001; +#endif + + /* + * Set priority of different initiators + */ + dma->IPR0 = 7; /* always */ + dma->IPR3 = 6; /* Eth RX */ + dma->IPR4 = 5; /* Eth Tx */ + + /* + * Clear SmartDMA task interrupt pending bits + */ + DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); + + /* + * Initialize SmartDMA parameters stored in SRAM + */ + *(int *) FEC_TBD_BASE = (int) fec->tbdBase; + *(int *) FEC_RBD_BASE = (int) fec->rbdBase; + *(int *) FEC_TBD_NEXT = (int) fec->tbdBase; + *(int *) FEC_RBD_NEXT = (int) fec->rbdBase; + + if (fec->xcv_type != SEVENWIRE) { + /* + * Initialize PHY(LXT971A): + * + * Generally, on power up, the LXT971A reads its configuration + * pins to check for forced operation, If not cofigured for + * forced operation, it uses auto-negotiation/parallel detection + * to automatically determine line operating conditions. + * If the PHY device on the other side of the link supports + * auto-negotiation, the LXT971A auto-negotiates with it + * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not + * support auto-negotiation, the LXT971A automatically detects + * the presence of either link pulses(10Mbps PHY) or Idle + * symbols(100Mbps) and sets its operating conditions accordingly. + * + * When auto-negotiation is controlled by software, the following + * steps are recommended. + * + * Note: + * The physical address is dependent on hardware configuration. + * + */ + int timeout = 1; + u16 phyStatus; + + /* + * Reset PHY, then delay 300ns + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x8000); + udelay (1000); + + if (fec->xcv_type == MII10) { + /* + * Force 10Base-T, FDX operation + */ +#ifdef DEBUG + printf ("Forcing 10 Mbps ethernet link... "); +#endif + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); + /* + miiphy_write(fec, phyAddr, 0x0, 0x0100); + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x0180); + + timeout = 20; + do { /* wait for link status to go down */ + udelay (10000); + if ((timeout--) == 0) { +#ifdef DEBUG + printf ("hmmm, should not have waited..."); +#endif + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#ifdef DEBUG + printf ("="); +#endif + } while ((phyStatus & 0x0004)); /* !link up */ + + timeout = 1000; + do { /* wait for link status to come back up */ + udelay (10000); + if ((timeout--) == 0) { + printf ("failed. Link is down.\n"); + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#ifdef DEBUG + printf ("+"); +#endif + } while (!(phyStatus & 0x0004)); /* !link up */ + +#ifdef DEBUG + printf ("done.\n"); +#endif + } else { /* MII100 */ + /* + * Set the auto-negotiation advertisement register bits + */ + miiphy_write (dev->name, phyAddr, 0x4, 0x01e1); + + /* + * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x1200); + + /* + * Wait for AN completion + */ + timeout = 5000; + do { + udelay (1000); + + if ((timeout--) == 0) { +#ifdef DEBUG + printf ("PHY auto neg 0 failed...\n"); +#endif + return -1; + } + + if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != + 0) { +#ifdef DEBUG + printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus); +#endif + return -1; + } + } while (!(phyStatus & 0x0004)); + +#ifdef DEBUG + printf ("PHY auto neg complete! \n"); +#endif + } + + } + + /* + * Enable FEC-Lite controller + */ + fec->eth->ecntrl |= 0x00000006; + +#ifdef DEBUG + if (fec->xcv_type != SEVENWIRE) + mpc8220_fec_phydump (dev->name); +#endif + + /* + * Enable SmartDMA receive task + */ + DMA_TASK_ENABLE (FEC_RECV_TASK_NO); + +#ifdef DEBUG + printf ("mpc8220_fec_init... Done \n"); +#endif + + return 1; +} + +/********************************************************************/ +static void mpc8220_fec_halt (struct eth_device *dev) +{ + mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv; + int counter = 0xffff; + +#ifdef DEBUG + if (fec->xcv_type != SEVENWIRE) + mpc8220_fec_phydump (dev->name); +#endif + + /* + * mask FEC chip interrupts + */ + fec->eth->imask = 0; + + /* + * issue graceful stop command to the FEC transmitter if necessary + */ + fec->eth->x_cntrl |= 0x00000001; + + /* + * wait for graceful stop to register + */ + while ((counter--) && (!(fec->eth->ievent & 0x10000000))); + + /* + * Disable SmartDMA tasks + */ + DMA_TASK_DISABLE (FEC_XMIT_TASK_NO); + DMA_TASK_DISABLE (FEC_RECV_TASK_NO); + + /* + * Disable the Ethernet Controller + */ + fec->eth->ecntrl &= 0xfffffffd; + + /* + * Clear FIFO status registers + */ + fec->eth->rfifo_status &= 0x00700000; + fec->eth->tfifo_status &= 0x00700000; + + fec->eth->reset_cntrl = 0x01000000; + + /* + * Issue a reset command to the FEC chip + */ + fec->eth->ecntrl |= 0x1; + + /* + * wait at least 16 clock cycles + */ + udelay (10); + +#ifdef DEBUG + printf ("Ethernet task stopped\n"); +#endif +} + +#ifdef DEBUG +/********************************************************************/ + +static void tfifo_print (char *devname, mpc8220_fec_priv * fec) +{ + u16 phyAddr = CONFIG_PHY_ADDR; + u16 phyStatus; + + if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr) + || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) { + + miiphy_read (devname, phyAddr, 0x1, &phyStatus); + printf ("\nphyStatus: 0x%04x\n", phyStatus); + printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl); + printf ("ievent: 0x%08x\n", fec->eth->ievent); + printf ("x_status: 0x%08x\n", fec->eth->x_status); + printf ("tfifo: status 0x%08x\n", fec->eth->tfifo_status); + + printf (" control 0x%08x\n", fec->eth->tfifo_cntrl); + printf (" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr); + printf (" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr); + printf (" alarm 0x%08x\n", fec->eth->tfifo_alarm); + printf (" readptr 0x%08x\n", fec->eth->tfifo_rdptr); + printf (" writptr 0x%08x\n", fec->eth->tfifo_wrptr); + } +} + +static void rfifo_print (char *devname, mpc8220_fec_priv * fec) +{ + u16 phyAddr = CONFIG_PHY_ADDR; + u16 phyStatus; + + if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr) + || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) { + + miiphy_read (devname, phyAddr, 0x1, &phyStatus); + printf ("\nphyStatus: 0x%04x\n", phyStatus); + printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl); + printf ("ievent: 0x%08x\n", fec->eth->ievent); + printf ("x_status: 0x%08x\n", fec->eth->x_status); + printf ("rfifo: status 0x%08x\n", fec->eth->rfifo_status); + + printf (" control 0x%08x\n", fec->eth->rfifo_cntrl); + printf (" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr); + printf (" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr); + printf (" alarm 0x%08x\n", fec->eth->rfifo_alarm); + printf (" readptr 0x%08x\n", fec->eth->rfifo_rdptr); + printf (" writptr 0x%08x\n", fec->eth->rfifo_wrptr); + } +} +#endif /* DEBUG */ + +/********************************************************************/ + +static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data, + int data_length) +{ + /* + * This routine transmits one frame. This routine only accepts + * 6-byte Ethernet addresses. + */ + mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv; + FEC_TBD *pTbd; + +#ifdef DEBUG + printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status); + tfifo_print (dev->name, fec); +#endif + + /* + * Clear Tx BD ring at first + */ + mpc8220_fec_tbd_scrub (fec); + + /* + * Check for valid length of data. + */ + if ((data_length > 1500) || (data_length <= 0)) { + return -1; + } + + /* + * Check the number of vacant TxBDs. + */ + if (fec->cleanTbdNum < 1) { +#ifdef DEBUG + printf ("No available TxBDs ...\n"); +#endif + return -1; + } + + /* + * Get the first TxBD to send the mac header + */ + pTbd = &fec->tbdBase[fec->tbdIndex]; + pTbd->dataLength = data_length; + pTbd->dataPointer = (u32) eth_data; + pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; + fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; + +#ifdef DEBUG + printf ("DMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex); +#endif + + /* + * Kick the MII i/f + */ + if (fec->xcv_type != SEVENWIRE) { + u16 phyStatus; + + miiphy_read (dev->name, 0, 0x1, &phyStatus); + } + + /* + * Enable SmartDMA transmit task + */ + +#ifdef DEBUG + tfifo_print (dev->name, fec); +#endif + + DMA_TASK_ENABLE (FEC_XMIT_TASK_NO); + +#ifdef DEBUG + tfifo_print (dev->name, fec); +#endif + +#ifdef DEBUG + printf ("+"); +#endif + + fec->cleanTbdNum -= 1; + +#ifdef DEBUG + printf ("smartDMA ethernet Tx task enabled\n"); +#endif + /* + * wait until frame is sent . + */ + while (pTbd->status & FEC_TBD_READY) { + udelay (10); +#ifdef DEBUG + printf ("TDB status = %04x\n", pTbd->status); +#endif + } + + return 0; +} + + +/********************************************************************/ +static int mpc8220_fec_recv (struct eth_device *dev) +{ + /* + * This command pulls one frame from the card + */ + mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv; + FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex]; + unsigned long ievent; + int frame_length, len = 0; + NBUF *frame; + +#ifdef DEBUG + printf ("mpc8220_fec_recv %d Start...\n", fec->rbdIndex); + printf ("-"); +#endif + + /* + * Check if any critical events have happened + */ + ievent = fec->eth->ievent; + fec->eth->ievent = ievent; + if (ievent & 0x20060000) { + /* BABT, Rx/Tx FIFO errors */ + mpc8220_fec_halt (dev); + mpc8220_fec_init (dev, NULL); + return 0; + } + if (ievent & 0x80000000) { + /* Heartbeat error */ + fec->eth->x_cntrl |= 0x00000001; + } + if (ievent & 0x10000000) { + /* Graceful stop complete */ + if (fec->eth->x_cntrl & 0x00000001) { + mpc8220_fec_halt (dev); + fec->eth->x_cntrl &= ~0x00000001; + mpc8220_fec_init (dev, NULL); + } + } + + if (!(pRbd->status & FEC_RBD_EMPTY)) { + if ((pRbd->status & FEC_RBD_LAST) + && !(pRbd->status & FEC_RBD_ERR) + && ((pRbd->dataLength - 4) > 14)) { + + /* + * Get buffer address and size + */ + frame = (NBUF *) pRbd->dataPointer; + frame_length = pRbd->dataLength - 4; + +#if (0) + { + int i; + + printf ("recv data hdr:"); + for (i = 0; i < 14; i++) + printf ("%x ", *(frame->head + i)); + printf ("\n"); + } +#endif + /* + * Fill the buffer and pass it to upper layers + */ +/* memcpy(buff, frame->head, 14); + memcpy(buff + 14, frame->data, frame_length);*/ + NetReceive ((volatile uchar *) pRbd->dataPointer, + frame_length); + len = frame_length; + } + /* + * Reset buffer descriptor as empty + */ + mpc8220_fec_rbd_clean (fec, pRbd); + } + DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); + return len; +} + + +/********************************************************************/ +int mpc8220_fec_initialize (bd_t * bis) +{ + mpc8220_fec_priv *fec; + +#ifdef CONFIG_HAS_ETH1 + mpc8220_fec_priv *fec2; +#endif + struct eth_device *dev; + char *tmp, *end; + char env_enetaddr[6]; + +#ifdef CONFIG_HAS_ETH1 + char env_enet1addr[6]; +#endif + int i; + + fec = (mpc8220_fec_priv *) malloc (sizeof (*fec)); + dev = (struct eth_device *) malloc (sizeof (*dev)); + memset (dev, 0, sizeof *dev); + + fec->eth = (ethernet_regs *) MMAP_FEC1; +#ifdef CONFIG_HAS_ETH1 + fec2 = (mpc8220_fec_priv *) malloc (sizeof (*fec)); + fec2->eth = (ethernet_regs *) MMAP_FEC2; +#endif + fec->tbdBase = (FEC_TBD *) FEC_BD_BASE; + fec->rbdBase = + (FEC_RBD *) (FEC_BD_BASE + FEC_TBD_NUM * sizeof (FEC_TBD)); + fec->xcv_type = MII100; + + dev->priv = (void *) fec; + dev->iobase = MMAP_FEC1; + dev->init = mpc8220_fec_init; + dev->halt = mpc8220_fec_halt; + dev->send = mpc8220_fec_send; + dev->recv = mpc8220_fec_recv; + + sprintf (dev->name, "FEC ETHERNET"); + eth_register (dev); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register (dev->name, + fec8220_miiphy_read, fec8220_miiphy_write); +#endif + + /* + * Try to set the mac address now. The fec mac address is + * a garbage after reset. When not using fec for booting + * the Linux fec driver will try to work with this garbage. + */ + tmp = getenv ("ethaddr"); + if (tmp) { + for (i = 0; i < 6; i++) { + env_enetaddr[i] = + tmp ? simple_strtoul (tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end + 1 : end; + } + mpc8220_fec_set_hwaddr (fec, env_enetaddr); + } +#ifdef CONFIG_HAS_ETH1 + tmp = getenv ("eth1addr"); + if (tmp) { + for (i = 0; i < 6; i++) { + env_enet1addr[i] = + tmp ? simple_strtoul (tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end + 1 : end; + } + mpc8220_fec_set_hwaddr (fec2, env_enet1addr); + } +#endif + + return 1; +} + +/* MII-interface related functions */ +/********************************************************************/ +int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal) +{ + ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1; + u32 reg; /* convenient holder for the PHY register */ + u32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + /* + * reading from any PHY's register is done by properly + * programming the FEC's MII data register. + */ + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = + (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy + | reg); + + /* + * wait for the related interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))); + + if (timeout == 0) { +#ifdef DEBUG + printf ("Read MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear mii interrupt bit + */ + eth->ievent = 0x00800000; + + /* + * it's now safe to read the PHY's register + */ + *retVal = (u16) eth->mii_data; + + return 0; +} + +/********************************************************************/ +int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data) +{ + ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1; + u32 reg; /* convenient holder for the PHY register */ + u32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | + FEC_MII_DATA_TA | phy | reg | data); + + /* + * wait for the MII interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))); + + if (timeout == 0) { +#ifdef DEBUG + printf ("Write MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear MII interrupt bit + */ + eth->ievent = 0x00800000; + + return 0; +} + +#ifdef DEBUG +static u32 local_crc32 (char *string, unsigned int crc_value, int len) +{ + int i; + char c; + unsigned int crc, count; + + /* + * crc32 algorithm + */ + /* + * crc = 0xffffffff; * The initialized value should be 0xffffffff + */ + crc = crc_value; + + for (i = len; --i >= 0;) { + c = *string++; + for (count = 0; count < 8; count++) { + if ((c & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + c >>= 1; + } + } + + /* + * In big endian system, do byte swaping for crc value + */ + return crc; +} +#endif /* DEBUG */ + +#endif /* CONFIG_MPC8220_FEC */ diff --git a/cpu/mpc8220/fec.h b/cpu/mpc8220/fec.h new file mode 100644 index 0000000..a8927fc --- /dev/null +++ b/cpu/mpc8220/fec.h @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on mpc4200fec.h + * (C) Copyright Motorola, Inc., 2000 + * + * odin ethernet header file + */ + +#ifndef __MPC8220_FEC_H +#define __MPC8220_FEC_H + +#include +#include +#include "dma.h" + +typedef struct ethernet_register_set { + +/* [10:2]addr = 00 */ + +/* Control and status Registers (offset 000-1FF) */ + + volatile u32 fec_id; /* MBAR_ETH + 0x000 */ + volatile u32 ievent; /* MBAR_ETH + 0x004 */ + volatile u32 imask; /* MBAR_ETH + 0x008 */ + + volatile u32 RES0[1]; /* MBAR_ETH + 0x00C */ + volatile u32 r_des_active; /* MBAR_ETH + 0x010 */ + volatile u32 x_des_active; /* MBAR_ETH + 0x014 */ + volatile u32 r_des_active_cl; /* MBAR_ETH + 0x018 */ + volatile u32 x_des_active_cl; /* MBAR_ETH + 0x01C */ + volatile u32 ivent_set; /* MBAR_ETH + 0x020 */ + volatile u32 ecntrl; /* MBAR_ETH + 0x024 */ + + volatile u32 RES1[6]; /* MBAR_ETH + 0x028-03C */ + volatile u32 mii_data; /* MBAR_ETH + 0x040 */ + volatile u32 mii_speed; /* MBAR_ETH + 0x044 */ + volatile u32 mii_status; /* MBAR_ETH + 0x048 */ + + volatile u32 RES2[5]; /* MBAR_ETH + 0x04C-05C */ + volatile u32 mib_data; /* MBAR_ETH + 0x060 */ + volatile u32 mib_control; /* MBAR_ETH + 0x064 */ + + volatile u32 RES3[6]; /* MBAR_ETH + 0x068-7C */ + volatile u32 r_activate; /* MBAR_ETH + 0x080 */ + volatile u32 r_cntrl; /* MBAR_ETH + 0x084 */ + volatile u32 r_hash; /* MBAR_ETH + 0x088 */ + volatile u32 r_data; /* MBAR_ETH + 0x08C */ + volatile u32 ar_done; /* MBAR_ETH + 0x090 */ + volatile u32 r_test; /* MBAR_ETH + 0x094 */ + volatile u32 r_mib; /* MBAR_ETH + 0x098 */ + volatile u32 r_da_low; /* MBAR_ETH + 0x09C */ + volatile u32 r_da_high; /* MBAR_ETH + 0x0A0 */ + + volatile u32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */ + volatile u32 x_activate; /* MBAR_ETH + 0x0C0 */ + volatile u32 x_cntrl; /* MBAR_ETH + 0x0C4 */ + volatile u32 backoff; /* MBAR_ETH + 0x0C8 */ + volatile u32 x_data; /* MBAR_ETH + 0x0CC */ + volatile u32 x_status; /* MBAR_ETH + 0x0D0 */ + volatile u32 x_mib; /* MBAR_ETH + 0x0D4 */ + volatile u32 x_test; /* MBAR_ETH + 0x0D8 */ + volatile u32 fdxfc_da1; /* MBAR_ETH + 0x0DC */ + volatile u32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */ + volatile u32 paddr1; /* MBAR_ETH + 0x0E4 */ + volatile u32 paddr2; /* MBAR_ETH + 0x0E8 */ + volatile u32 op_pause; /* MBAR_ETH + 0x0EC */ + + volatile u32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */ + volatile u32 instr_reg; /* MBAR_ETH + 0x100 */ + volatile u32 context_reg; /* MBAR_ETH + 0x104 */ + volatile u32 test_cntrl; /* MBAR_ETH + 0x108 */ + volatile u32 acc_reg; /* MBAR_ETH + 0x10C */ + volatile u32 ones; /* MBAR_ETH + 0x110 */ + volatile u32 zeros; /* MBAR_ETH + 0x114 */ + volatile u32 iaddr1; /* MBAR_ETH + 0x118 */ + volatile u32 iaddr2; /* MBAR_ETH + 0x11C */ + volatile u32 gaddr1; /* MBAR_ETH + 0x120 */ + volatile u32 gaddr2; /* MBAR_ETH + 0x124 */ + volatile u32 random; /* MBAR_ETH + 0x128 */ + volatile u32 rand1; /* MBAR_ETH + 0x12C */ + volatile u32 tmp; /* MBAR_ETH + 0x130 */ + + volatile u32 RES6[3]; /* MBAR_ETH + 0x134-13C */ + volatile u32 fifo_id; /* MBAR_ETH + 0x140 */ + volatile u32 x_wmrk; /* MBAR_ETH + 0x144 */ + volatile u32 fcntrl; /* MBAR_ETH + 0x148 */ + volatile u32 r_bound; /* MBAR_ETH + 0x14C */ + volatile u32 r_fstart; /* MBAR_ETH + 0x150 */ + volatile u32 r_count; /* MBAR_ETH + 0x154 */ + volatile u32 r_lag; /* MBAR_ETH + 0x158 */ + volatile u32 r_read; /* MBAR_ETH + 0x15C */ + volatile u32 r_write; /* MBAR_ETH + 0x160 */ + volatile u32 x_count; /* MBAR_ETH + 0x164 */ + volatile u32 x_lag; /* MBAR_ETH + 0x168 */ + volatile u32 x_retry; /* MBAR_ETH + 0x16C */ + volatile u32 x_write; /* MBAR_ETH + 0x170 */ + volatile u32 x_read; /* MBAR_ETH + 0x174 */ + + volatile u32 RES7[2]; /* MBAR_ETH + 0x178-17C */ + volatile u32 fm_cntrl; /* MBAR_ETH + 0x180 */ + volatile u32 rfifo_data; /* MBAR_ETH + 0x184 */ + volatile u32 rfifo_status; /* MBAR_ETH + 0x188 */ + volatile u32 rfifo_cntrl; /* MBAR_ETH + 0x18C */ + volatile u32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */ + volatile u32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */ + volatile u32 rfifo_alarm; /* MBAR_ETH + 0x198 */ + volatile u32 rfifo_rdptr; /* MBAR_ETH + 0x19C */ + volatile u32 rfifo_wrptr; /* MBAR_ETH + 0x1A0 */ + volatile u32 tfifo_data; /* MBAR_ETH + 0x1A4 */ + volatile u32 tfifo_status; /* MBAR_ETH + 0x1A8 */ + volatile u32 tfifo_cntrl; /* MBAR_ETH + 0x1AC */ + volatile u32 tfifo_lrf_ptr; /* MBAR_ETH + 0x1B0 */ + volatile u32 tfifo_lwf_ptr; /* MBAR_ETH + 0x1B4 */ + volatile u32 tfifo_alarm; /* MBAR_ETH + 0x1B8 */ + volatile u32 tfifo_rdptr; /* MBAR_ETH + 0x1BC */ + volatile u32 tfifo_wrptr; /* MBAR_ETH + 0x1C0 */ + + volatile u32 reset_cntrl; /* MBAR_ETH + 0x1C4 */ + volatile u32 xmit_fsm; /* MBAR_ETH + 0x1C8 */ + + volatile u32 RES8[3]; /* MBAR_ETH + 0x1CC-1D4 */ + volatile u32 rdes_data0; /* MBAR_ETH + 0x1D8 */ + volatile u32 rdes_data1; /* MBAR_ETH + 0x1DC */ + volatile u32 r_length; /* MBAR_ETH + 0x1E0 */ + volatile u32 x_length; /* MBAR_ETH + 0x1E4 */ + volatile u32 x_addr; /* MBAR_ETH + 0x1E8 */ + volatile u32 cdes_data; /* MBAR_ETH + 0x1EC */ + volatile u32 status; /* MBAR_ETH + 0x1F0 */ + volatile u32 dma_control; /* MBAR_ETH + 0x1F4 */ + volatile u32 des_cmnd; /* MBAR_ETH + 0x1F8 */ + volatile u32 data; /* MBAR_ETH + 0x1FC */ + + /* MIB COUNTERS (Offset 200-2FF) */ + + volatile u32 rmon_t_drop; /* MBAR_ETH + 0x200 */ + volatile u32 rmon_t_packets; /* MBAR_ETH + 0x204 */ + volatile u32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ + volatile u32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ + volatile u32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ + volatile u32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ + volatile u32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ + volatile u32 rmon_t_frag; /* MBAR_ETH + 0x21C */ + volatile u32 rmon_t_jab; /* MBAR_ETH + 0x220 */ + volatile u32 rmon_t_col; /* MBAR_ETH + 0x224 */ + volatile u32 rmon_t_p64; /* MBAR_ETH + 0x228 */ + volatile u32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ + volatile u32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ + volatile u32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ + volatile u32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ + volatile u32 rmon_t_p1024to2047;/* MBAR_ETH + 0x23C */ + volatile u32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ + volatile u32 rmon_t_octets; /* MBAR_ETH + 0x244 */ + volatile u32 ieee_t_drop; /* MBAR_ETH + 0x248 */ + volatile u32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ + volatile u32 ieee_t_1col; /* MBAR_ETH + 0x250 */ + volatile u32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ + volatile u32 ieee_t_def; /* MBAR_ETH + 0x258 */ + volatile u32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ + volatile u32 ieee_t_excol; /* MBAR_ETH + 0x260 */ + volatile u32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ + volatile u32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ + volatile u32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ + volatile u32 t_fdxfc; /* MBAR_ETH + 0x270 */ + volatile u32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ + + volatile u32 RES9[2]; /* MBAR_ETH + 0x278-27C */ + volatile u32 rmon_r_drop; /* MBAR_ETH + 0x280 */ + volatile u32 rmon_r_packets; /* MBAR_ETH + 0x284 */ + volatile u32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ + volatile u32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ + volatile u32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ + volatile u32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ + volatile u32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ + volatile u32 rmon_r_frag; /* MBAR_ETH + 0x29C */ + volatile u32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ + + volatile u32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ + + volatile u32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ + volatile u32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ + volatile u32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ + volatile u32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ + volatile u32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ + volatile u32 rmon_r_p1024to2047;/* MBAR_ETH + 0x2BC */ + volatile u32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ + volatile u32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ + volatile u32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ + volatile u32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ + volatile u32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ + volatile u32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ + volatile u32 r_macerr; /* MBAR_ETH + 0x2D8 */ + volatile u32 r_fdxfc; /* MBAR_ETH + 0x2DC */ + volatile u32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ + + volatile u32 RES10[6]; /* MBAR_ETH + 0x2E4-2FC */ + + volatile u32 RES11[64]; /* MBAR_ETH + 0x300-3FF */ +} ethernet_regs; + +/* Receive & Transmit Buffer Descriptor definitions */ +typedef struct BufferDescriptor { + u16 status; + u16 dataLength; + u32 dataPointer; +} FEC_RBD; + +typedef struct { + u16 status; + u16 dataLength; + u32 dataPointer; +} FEC_TBD; + +/* private structure */ +typedef enum { + SEVENWIRE, /* 7-wire */ + MII10, /* MII 10Mbps */ + MII100 /* MII 100Mbps */ +} xceiver_type; + +typedef struct { + ethernet_regs *eth; + xceiver_type xcv_type; /* transceiver type */ + FEC_RBD *rbdBase; /* RBD ring */ + FEC_TBD *tbdBase; /* TBD ring */ + u16 rbdIndex; /* next receive BD to read */ + u16 tbdIndex; /* next transmit BD to send */ + u16 usedTbdIndex; /* next transmit BD to clean */ + u16 cleanTbdNum; /* the number of available transmit BDs */ +} mpc8220_fec_priv; + +/* Ethernet parameter area */ +#define FEC_TBD_BASE (FEC_PARAM_BASE + 0x00) +#define FEC_TBD_NEXT (FEC_PARAM_BASE + 0x04) +#define FEC_RBD_BASE (FEC_PARAM_BASE + 0x08) +#define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c) + +/* BD Numer definitions */ +#define FEC_TBD_NUM 48 /* The user can adjust this value */ +#define FEC_RBD_NUM 32 /* The user can adjust this value */ + +/* packet size limit */ +#define FEC_MAX_PKT_SIZE 1536 + +/* RBD bits definitions */ +#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ +#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_RBD_INT 0x1000 /* Interrupt */ +#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ +#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ +#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ +#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ +#define FEC_RBD_LG 0x0020 /* Frame length violation */ +#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ +#define FEC_RBD_SH 0x0008 /* Short frame */ +#define FEC_RBD_CR 0x0004 /* CRC error */ +#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ +#define FEC_RBD_TR 0x0001 /* Frame is truncated */ +#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ + FEC_RBD_OV | FEC_RBD_TR) + +/* TBD bits definitions */ +#define FEC_TBD_READY 0x8000 /* Buffer is ready */ +#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_TBD_INT 0x1000 /* Interrupt */ +#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ +#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ +#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ + +/* MII-related definitios */ +#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ +#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ +#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ +#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ +#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ +#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ +#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ + +#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ +#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ + +#endif /* __MPC8220_FEC_H */ diff --git a/cpu/mpc8220/fec_dma_tasks.S b/cpu/mpc8220/fec_dma_tasks.S new file mode 100644 index 0000000..3f8a03b --- /dev/null +++ b/cpu/mpc8220/fec_dma_tasks.S @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2004, Freescale Semiconductor, Inc. + * + * This file contains microcode for the FEC controller of the MPC8220. + */ + +#include + +#if defined(CONFIG_MPC8220) + +/* sas/sccg, gas target */ +.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ +.section smartdmaTaskTable,"aw",@progbits /* Task tables */ +.align 9 +.globl taskTable +taskTable: +.globl scEthernetRecv_Entry +scEthernetRecv_Entry: /* Task 0 */ +.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ +.long scEthernetRecv_TDT - taskTable + 0x00000094 +.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ +.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ +.long 0x00000000 +.long 0x00000000 +.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ +.long 0xf0000000 +.globl scEthernetXmit_Entry +scEthernetXmit_Entry: /* Task 1 */ +.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ +.long scEthernetXmit_TDT - taskTable + 0x000000e0 +.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ +.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ +.long 0x00000000 +.long 0x00000000 +.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ +.long 0xf0000000 + + +.globl scEthernetRecv_TDT +scEthernetRecv_TDT: /* Task 0 Descriptor Table */ +.long 0xc4c50000 /* 0000(153): LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ +.long 0x84c5e000 /* 0004(153): LCD: idx1 = var9 + var11; ; idx1 += inc0 */ +.long 0x10001f08 /* 0008(156): DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x10000380 /* 000C(157): DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f88 /* 0010(158): DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ +.long 0x81980000 /* 0014(162): LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ +.long 0x10000780 /* 0018(164): DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 001C(165): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x010cf04c /* 0020(165): DRD2B1: var4 = EU3(); EU3(var1,var12) */ +.long 0x82180349 /* 0024(169): LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ +.long 0x81c68004 /* 0028(172): LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ +.long 0x70000000 /* 002C(174): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x018cf04e /* 0030(174): DRD2B1: var6 = EU3(); EU3(var1,var14) */ +.long 0x70000000 /* 0034(175): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x020cf04f /* 0038(175): DRD2B1: var8 = EU3(); EU3(var1,var15) */ +.long 0x00000b88 /* 003C(176): DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ +.long 0x80025184 /* 0040(205): LCDEXT: idx1 = 0xf0009184; ; */ +.long 0x86810412 /* 0044(205): LCD: idx2 = var13, idx3 = var2; idx2 < var16; idx2 += inc2, idx3 += inc2 */ +.long 0x0200cf88 /* 0048(209): DRD1A: *idx3 = *idx1; FN=0 init=16 WS=0 RS=0 */ +.long 0x80025184 /* 004C(217): LCDEXT: idx1 = 0xf0009184; ; */ +.long 0x8681845b /* 0050(217): LCD: idx2 = var13, idx3 = var3; idx2 < var17; idx2 += inc3, idx3 += inc3 */ +.long 0x0000cf88 /* 0054(221): DRD1A: *idx3 = *idx1; FN=0 init=0 WS=0 RS=0 */ +.long 0xc31883a4 /* 0058(225): LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc4 */ +.long 0x80190000 /* 005C(225): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +.long 0x04008468 /* 0060(227): DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ +.long 0xc4038360 /* 0064(232): LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc4, idx2 += inc0 */ +.long 0x81c50000 /* 0068(233): LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ +.long 0x1000cb18 /* 006C(235): DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f18 /* 0070(236): DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ +.long 0xc418836d /* 0074(238): LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc5 */ +.long 0x83990000 /* 0078(238): LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ +.long 0x10000c00 /* 007C(240): DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x0000c800 /* 0080(241): DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ +.long 0x81988000 /* 0084(245): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x10000788 /* 0088(247): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 008C(248): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x080cf04c /* 0090(248): DRD2B1: idx0 = EU3(); EU3(var1,var12) */ +.long 0x000001f8 /* 0094(:0): NOP */ + + +.globl scEthernetXmit_TDT +scEthernetXmit_TDT: /* Task 1 Descriptor Table */ +.long 0x80095b00 /* 0000(280): LCDEXT: idx0 = 0xf0025b00; ; */ +.long 0x85c60004 /* 0004(280): LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ +.long 0x10002308 /* 0008(283): DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x10000f88 /* 000C(284): DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000380 /* 0010(285): DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ +.long 0x81980000 /* 0014(288): LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ +.long 0x10000780 /* 0018(290): DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 001C(291): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x024cf04d /* 0020(291): DRD2B1: var9 = EU3(); EU3(var1,var13) */ +.long 0x84980309 /* 0024(294): LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ +.long 0xc0004003 /* 0028(297): LCDEXT: idx1 = 0x00000003; ; */ +.long 0x81c60004 /* 002C(297): LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ +.long 0x70000000 /* 0030(299): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x010cf04e /* 0034(299): DRD2B1: var4 = EU3(); EU3(var1,var14) */ +.long 0x70000000 /* 0038(300): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x014cf04f /* 003C(300): DRD2B1: var5 = EU3(); EU3(var1,var15) */ +.long 0x70000000 /* 0040(301): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x028cf050 /* 0044(301): DRD2B1: var10 = EU3(); EU3(var1,var16) */ +.long 0x70000000 /* 0048(302): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ +.long 0x018cf051 /* 004C(302): DRD2B1: var6 = EU3(); EU3(var1,var17) */ +.long 0x10000b90 /* 0050(303): DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 0054(304): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x01ccf0a1 /* 0058(304): DRD2B1: var7 = EU3(); EU3(var2,idx1) */ +.long 0xc2988312 /* 005C(308): LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ +.long 0x83490000 /* 0060(308): LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ +.long 0x00001b10 /* 0064(310): DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ +.long 0x800251a4 /* 0068(315): LCDEXT: idx1 = 0xf00091a4; ; */ +.long 0xc30104dc /* 006C(315): LCDEXT: idx2 = var6, idx3 = var2; idx2 >= var19; idx2 += inc3, idx3 += inc4 */ +.long 0x839a032d /* 0070(316): LCD: idx4 = var7; idx4 == var12; idx4 += inc5 */ +.long 0x0220c798 /* 0074(321): DRD1A: *idx1 = *idx3; FN=0 init=17 WS=0 RS=0 */ +.long 0x800251a4 /* 0078(329): LCDEXT: idx1 = 0xf00091a4; ; */ +.long 0x99198337 /* 007C(329): LCD: idx2 = idx2, idx3 = idx3; idx2 > var12; idx2 += inc6, idx3 += inc7 */ +.long 0x022ac798 /* 0080(333): DRD1A: *idx1 = *idx3; FN=0 init=17 WS=1 RS=1 */ +.long 0x800251a4 /* 0084(350): LCDEXT: idx1 = 0xf00091a4; ; */ +.long 0xc1430000 /* 0088(350): LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ +.long 0x82998312 /* 008C(351): LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ +.long 0x0a2ac790 /* 0090(354): DRD1A: *idx1 = *idx2; FN=0 TFD init=17 WS=1 RS=1 */ +.long 0x81988000 /* 0094(359): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x60000002 /* 0098(361): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=0 RS=0 */ +.long 0x0c4cfc4d /* 009C(361): DRD2B1: *idx1 = EU3(); EU3(*idx1,var13) */ +.long 0xc21883ad /* 00A0(365): LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ +.long 0x80190000 /* 00A4(365): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +.long 0x04008460 /* 00A8(367): DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ +.long 0xc4052305 /* 00AC(371): LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ +.long 0x81ca0000 /* 00B0(372): LCD: idx3 = var3 + var20; idx3 once var0; idx3 += inc0 */ +.long 0x1000c718 /* 00B4(374): DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00000f18 /* 00B8(375): DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ +.long 0xc4188000 /* 00BC(378): LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ +.long 0x85190312 /* 00C0(378): LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ +.long 0x10000c00 /* 00C4(380): DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x1000c400 /* 00C8(381): DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x00008860 /* 00CC(382): DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ +.long 0x81988000 /* 00D0(386): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +.long 0x10000788 /* 00D4(388): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +.long 0x60000000 /* 00D8(389): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ +.long 0x080cf04d /* 00DC(389): DRD2B1: idx0 = EU3(); EU3(var1,var13) */ +.long 0x000001f8 /* 00E0(:0): NOP */ + +.align 8 + +.globl scEthernetRecv_VarTab +scEthernetRecv_VarTab: /* Task 0 Variable Table */ +.long 0x00000000 /* var[0] */ +.long 0x00000000 /* var[1] */ +.long 0x00000000 /* var[2] */ +.long 0x00000000 /* var[3] */ +.long 0x00000000 /* var[4] */ +.long 0x00000000 /* var[5] */ +.long 0x00000000 /* var[6] */ +.long 0x00000000 /* var[7] */ +.long 0x00000000 /* var[8] */ +.long 0xf0025b00 /* var[9] */ +.long 0x00000008 /* var[10] */ +.long 0x0000000c /* var[11] */ +.long 0x80000000 /* var[12] */ +.long 0x00000000 /* var[13] */ +.long 0x10000000 /* var[14] */ +.long 0x20000000 /* var[15] */ +.long 0x00000800 /* var[16] */ +.long 0x00000001 /* var[17] */ +.long 0x00000000 /* var[18] */ +.long 0x00000000 /* var[19] */ +.long 0x00000000 /* var[20] */ +.long 0x00000000 /* var[21] */ +.long 0x00000000 /* var[22] */ +.long 0x00000000 /* var[23] */ +.long 0x00000000 /* inc[0] */ +.long 0x60000000 /* inc[1] */ +.long 0x20000004 /* inc[2] */ +.long 0x20000001 /* inc[3] */ +.long 0x80000000 /* inc[4] */ +.long 0x40000000 /* inc[5] */ +.long 0x00000000 /* inc[6] */ +.long 0x00000000 /* inc[7] */ + +.align 8 + +.globl scEthernetXmit_VarTab +scEthernetXmit_VarTab: /* Task 1 Variable Table */ +.long 0x00000000 /* var[0] */ +.long 0x00000000 /* var[1] */ +.long 0x00000000 /* var[2] */ +.long 0x00000000 /* var[3] */ +.long 0x00000000 /* var[4] */ +.long 0x00000000 /* var[5] */ +.long 0x00000000 /* var[6] */ +.long 0x00000000 /* var[7] */ +.long 0x00000000 /* var[8] */ +.long 0x00000000 /* var[9] */ +.long 0x00000000 /* var[10] */ +.long 0xf0025b00 /* var[11] */ +.long 0x00000000 /* var[12] */ +.long 0x80000000 /* var[13] */ +.long 0x10000000 /* var[14] */ +.long 0x08000000 /* var[15] */ +.long 0x20000000 /* var[16] */ +.long 0x0000ffff /* var[17] */ +.long 0xffffffff /* var[18] */ +.long 0x00000004 /* var[19] */ +.long 0x00000008 /* var[20] */ +.long 0x00000000 /* var[21] */ +.long 0x00000000 /* var[22] */ +.long 0x00000000 /* var[23] */ +.long 0x00000000 /* inc[0] */ +.long 0x60000000 /* inc[1] */ +.long 0x40000000 /* inc[2] */ +.long 0xc000fffc /* inc[3] */ +.long 0xe0000004 /* inc[4] */ +.long 0x80000000 /* inc[5] */ +.long 0x4000ffff /* inc[6] */ +.long 0xe0000001 /* inc[7] */ + +.align 8 + +.globl scEthernetRecv_FDT +scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x21800000 /* and(), EU# 3 */ +.long 0x21e00000 /* or(), EU# 3 */ +.long 0x21400000 /* andn(), EU# 3 */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 + +.align 8 + +.globl scEthernetXmit_FDT +scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x21800000 /* and(), EU# 3 */ +.long 0x21e00000 /* or(), EU# 3 */ +.long 0x21400000 /* andn(), EU# 3 */ +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 +.long 0x00000000 + + +.globl scEthernetRecv_CSave +scEthernetRecv_CSave: /* Task 0 context save space */ +.space 128, 0x0 + + +.globl scEthernetXmit_CSave +scEthernetXmit_CSave: /* Task 1 context save space */ +.space 128, 0x0 + +#endif diff --git a/cpu/mpc8220/i2c.c b/cpu/mpc8220/i2c.c new file mode 100644 index 0000000..62f7c0f --- /dev/null +++ b/cpu/mpc8220/i2c.c @@ -0,0 +1,405 @@ +/* + * (C) Copyright 2004, Freescale, Inc + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_HARD_I2C + +#include +#include + +typedef struct mpc8220_i2c { + volatile u32 adr; /* I2Cn + 0x00 */ + volatile u32 fdr; /* I2Cn + 0x04 */ + volatile u32 cr; /* I2Cn + 0x08 */ + volatile u32 sr; /* I2Cn + 0x0C */ + volatile u32 dr; /* I2Cn + 0x10 */ +} i2c_t; + +/* I2Cn control register bits */ +#define I2C_EN 0x80 +#define I2C_IEN 0x40 +#define I2C_STA 0x20 +#define I2C_TX 0x10 +#define I2C_TXAK 0x08 +#define I2C_RSTA 0x04 +#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) + +/* I2Cn status register bits */ +#define I2C_CF 0x80 +#define I2C_AAS 0x40 +#define I2C_BB 0x20 +#define I2C_AL 0x10 +#define I2C_SRW 0x04 +#define I2C_IF 0x02 +#define I2C_RXAK 0x01 + +#define I2C_TIMEOUT 100 +#define I2C_RETRIES 1 + +struct mpc8220_i2c_tap { + int scl2tap; + int tap2tap; +}; + +static int mpc_reg_in (volatile u32 * reg); +static void mpc_reg_out (volatile u32 * reg, int val, int mask); +static int wait_for_bb (void); +static int wait_for_pin (int *status); +static int do_address (uchar chip, char rdwr_flag); +static int send_bytes (uchar chip, char *buf, int len); +static int receive_bytes (uchar chip, char *buf, int len); +static int mpc_get_fdr (int); + +static int mpc_reg_in (volatile u32 * reg) +{ + int ret; + ret = *reg >> 24; + __asm__ __volatile__ ("eieio"); + return ret; +} + +static void mpc_reg_out (volatile u32 * reg, int val, int mask) +{ + int tmp; + + if (!mask) { + *reg = val << 24; + } else { + tmp = mpc_reg_in (reg); + *reg = ((tmp & ~mask) | (val & mask)) << 24; + } + __asm__ __volatile__ ("eieio"); + + return; +} + +static int wait_for_bb (void) +{ + i2c_t *regs = (i2c_t *) MMAP_I2C; + int timeout = I2C_TIMEOUT; + int status; + + status = mpc_reg_in (®s->sr); + + while (timeout-- && (status & I2C_BB)) { +#if 1 + volatile int temp; + + mpc_reg_out (®s->cr, I2C_STA, I2C_STA); + temp = mpc_reg_in (®s->dr); + mpc_reg_out (®s->cr, 0, I2C_STA); + mpc_reg_out (®s->cr, 0, 0); + mpc_reg_out (®s->cr, I2C_EN, 0); +#endif + udelay (1000); + status = mpc_reg_in (®s->sr); + } + + return (status & I2C_BB); +} + +static int wait_for_pin (int *status) +{ + i2c_t *regs = (i2c_t *) MMAP_I2C; + int timeout = I2C_TIMEOUT; + + *status = mpc_reg_in (®s->sr); + + while (timeout-- && !(*status & I2C_IF)) { + udelay (1000); + *status = mpc_reg_in (®s->sr); + } + + if (!(*status & I2C_IF)) { + return -1; + } + + mpc_reg_out (®s->sr, 0, I2C_IF); + return 0; +} + +static int do_address (uchar chip, char rdwr_flag) +{ + i2c_t *regs = (i2c_t *) MMAP_I2C; + int status; + + chip <<= 1; + + if (rdwr_flag) + chip |= 1; + + mpc_reg_out (®s->cr, I2C_TX, I2C_TX); + mpc_reg_out (®s->dr, chip, 0); + + if (wait_for_pin (&status)) + return -2; + if (status & I2C_RXAK) + return -3; + return 0; +} + +static int send_bytes (uchar chip, char *buf, int len) +{ + i2c_t *regs = (i2c_t *) MMAP_I2C; + int wrcount; + int status; + + for (wrcount = 0; wrcount < len; ++wrcount) { + + mpc_reg_out (®s->dr, buf[wrcount], 0); + + if (wait_for_pin (&status)) + break; + + if (status & I2C_RXAK) + break; + + } + + return !(wrcount == len); + return 0; +} + +static int receive_bytes (uchar chip, char *buf, int len) +{ + i2c_t *regs = (i2c_t *) MMAP_I2C; + int dummy = 1; + int rdcount = 0; + int status; + int i; + + mpc_reg_out (®s->cr, 0, I2C_TX); + + for (i = 0; i < len; ++i) { + buf[rdcount] = mpc_reg_in (®s->dr); + + if (dummy) + dummy = 0; + else + rdcount++; + + if (wait_for_pin (&status)) + return -4; + } + + mpc_reg_out (®s->cr, I2C_TXAK, I2C_TXAK); + buf[rdcount++] = mpc_reg_in (®s->dr); + + if (wait_for_pin (&status)) + return -5; + + mpc_reg_out (®s->cr, 0, I2C_TXAK); + return 0; +} + +/**************** I2C API ****************/ + +void i2c_init (int speed, int saddr) +{ + i2c_t *regs = (i2c_t *) MMAP_I2C; + + mpc_reg_out (®s->cr, 0, 0); + mpc_reg_out (®s->adr, saddr << 1, 0); + + /* Set clock + */ + mpc_reg_out (®s->fdr, mpc_get_fdr (speed), 0); + + /* Enable module + */ + mpc_reg_out (®s->cr, I2C_EN, I2C_INIT_MASK); + mpc_reg_out (®s->sr, 0, I2C_IF); + return; +} + +static int mpc_get_fdr (int speed) +{ + DECLARE_GLOBAL_DATA_PTR; + static int fdr = -1; + + if (fdr == -1) { + ulong best_speed = 0; + ulong divider; + ulong ipb, scl; + ulong bestmatch = 0xffffffffUL; + int best_i = 0, best_j = 0, i, j; + int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8 }; + struct mpc8220_i2c_tap scltap[] = { + {4, 1}, + {4, 2}, + {6, 4}, + {6, 8}, + {14, 16}, + {30, 32}, + {62, 64}, + {126, 128} + }; + + ipb = gd->bus_clk; + for (i = 7; i >= 0; i--) { + for (j = 7; j >= 0; j--) { + scl = 2 * (scltap[j].scl2tap + + (SCL_Tap[i] - + 1) * scltap[j].tap2tap + 2); + if (ipb <= speed * scl) { + if ((speed * scl - ipb) < bestmatch) { + bestmatch = speed * scl - ipb; + best_i = i; + best_j = j; + best_speed = ipb / scl; + } + } + } + } + divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); + if (gd->flags & GD_FLG_RELOC) { + fdr = divider; + } else { + printf ("%ld kHz, ", best_speed / 1000); + return divider; + } + } + + return fdr; +} + +int i2c_probe (uchar chip) +{ + i2c_t *regs = (i2c_t *) MMAP_I2C; + int i; + + for (i = 0; i < I2C_RETRIES; i++) { + mpc_reg_out (®s->cr, I2C_STA, I2C_STA); + + if (!do_address (chip, 0)) { + mpc_reg_out (®s->cr, 0, I2C_STA); + break; + } + + mpc_reg_out (®s->cr, 0, I2C_STA); + udelay (50); + } + + return (i == I2C_RETRIES); +} + +int i2c_read (uchar chip, uint addr, int alen, uchar * buf, int len) +{ + uchar xaddr[4]; + i2c_t *regs = (i2c_t *) MMAP_I2C; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb ()) { + printf ("i2c_read: bus is busy\n"); + goto Done; + } + + mpc_reg_out (®s->cr, I2C_STA, I2C_STA); + if (do_address (chip, 0)) { + printf ("i2c_read: failed to address chip\n"); + goto Done; + } + + if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) { + printf ("i2c_read: send_bytes failed\n"); + goto Done; + } + + mpc_reg_out (®s->cr, I2C_RSTA, I2C_RSTA); + if (do_address (chip, 1)) { + printf ("i2c_read: failed to address chip\n"); + goto Done; + } + + if (receive_bytes (chip, (char *)buf, len)) { + printf ("i2c_read: receive_bytes failed\n"); + goto Done; + } + + ret = 0; + Done: + mpc_reg_out (®s->cr, 0, I2C_STA); + return ret; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar * buf, int len) +{ + uchar xaddr[4]; + i2c_t *regs = (i2c_t *) MMAP_I2C; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb ()) { + printf ("i2c_write: bus is busy\n"); + goto Done; + } + + mpc_reg_out (®s->cr, I2C_STA, I2C_STA); + if (do_address (chip, 0)) { + printf ("i2c_write: failed to address chip\n"); + goto Done; + } + + if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) { + printf ("i2c_write: send_bytes failed\n"); + goto Done; + } + + if (send_bytes (chip, (char *)buf, len)) { + printf ("i2c_write: send_bytes failed\n"); + goto Done; + } + + ret = 0; + Done: + mpc_reg_out (®s->cr, 0, I2C_STA); + return ret; +} + +uchar i2c_reg_read (uchar chip, uchar reg) +{ + uchar buf; + + i2c_read (chip, reg, 1, &buf, 1); + + return buf; +} + +void i2c_reg_write (uchar chip, uchar reg, uchar val) +{ + i2c_write (chip, reg, 1, &val, 1); + + return; +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8220/i2cCore.c b/cpu/mpc8220/i2cCore.c new file mode 100644 index 0000000..accf43c --- /dev/null +++ b/cpu/mpc8220/i2cCore.c @@ -0,0 +1,627 @@ +/* I2cCore.c - MPC8220 PPC I2C Library */ + +/* Copyright 2004 Freescale Semiconductor, Inc. */ + +/* +modification history +-------------------- +01c,29jun04,tcl 1.3 removed CR. Added two bytes offset support. +01b,19jan04,tcl 1.2 removed i2cMsDelay and sysDecGet. renamed i2cMsDelay + back to sysMsDelay +01a,19jan04,tcl 1.1 created and seperated from i2c.c +*/ + +/* +DESCRIPTION +This file contain I2C low level handling library functions +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* BSP Includes */ +#include "config.h" +#include "mpc8220.h" +#include "i2cCore.h" + +#ifdef DEBUG_I2CCORE +int I2CCDbg = 0; +#endif + +#define ABS(x) ((x < 0)? -x : x) + +char *I2CERR[16] = { + "Transfer in Progress\n", /* 0 */ + "Transfer complete\n", + "Not Addressed\n", /* 2 */ + "Addressed as a slave\n", + "Bus is Idle\n", /* 4 */ + "Bus is busy\n", + "Arbitration Lost\n", /* 6 */ + "Arbitration on Track\n", + "Slave receive, master writing to slave\n", /* 8 */ + "Slave transmit, master reading from slave\n", + "Interrupt is pending\n", /* 10 */ + "Interrupt complete\n", + "Acknowledge received\n", /* 12 */ + "No acknowledge received\n", + "Unknown status\n", /* 14 */ + "\n" +}; + +/****************************************************************************** + * + * chk_status - Check I2C status bit + * + * RETURNS: OK, or ERROR if the bit encounter + * + */ + +STATUS chk_status (PSI2C pi2c, UINT8 sta_bit, UINT8 truefalse) +{ + int i, status = 0; + + for (i = 0; i < I2C_POLL_COUNT; i++) { + if ((pi2c->sr & sta_bit) == (truefalse ? sta_bit : 0)) + return (OK); + } + + I2CCDBG (L2, ("--- sr %x stabit %x truefalse %d\n", + pi2c->sr, sta_bit, truefalse, 0, 0, 0)); + + if (i == I2C_POLL_COUNT) { + switch (sta_bit) { + case I2C_STA_CF: + status = 0; + break; + case I2C_STA_AAS: + status = 2; + break; + case I2C_STA_BB: + status = 4; + break; + case I2C_STA_AL: + status = 6; + break; + case I2C_STA_SRW: + status = 8; + break; + case I2C_STA_IF: + status = 10; + break; + case I2C_STA_RXAK: + status = 12; + break; + default: + status = 14; + break; + } + + if (!truefalse) + status++; + + I2CCDBG (NO, ("--- status %d\n", status, 0, 0, 0, 0, 0)); + I2CCDBG (NO, (I2CERR[status], 0, 0, 0, 0, 0, 0)); + } + + return (ERROR); +} + +/****************************************************************************** + * + * I2C Enable - Enable the I2C Controller + * + */ +STATUS i2c_enable (SI2C * pi2c, PI2CSET pi2cSet) +{ + int fdr = pi2cSet->bit_rate; + UINT8 adr = pi2cSet->i2c_adr; + + I2CCDBG (L2, ("i2c_enable fdr %d adr %x\n", fdr, adr, 0, 0, 0, 0)); + + i2c_clear (pi2c); /* Clear FDR, ADR, SR and CR reg */ + + SetI2cFDR (pi2c, fdr); /* Frequency */ + pi2c->adr = adr; + + pi2c->cr = I2C_CTL_EN; /* Set Enable */ + + /* + The I2C bus should be in Idle state. If the bus is busy, + clear the STA bit in control register + */ + if (chk_status (pi2c, I2C_STA_BB, 0) != OK) { + if ((pi2c->cr & I2C_CTL_STA) == I2C_CTL_STA) + pi2c->cr &= ~I2C_CTL_STA; + + /* Check again if it is still busy, return error if found */ + if (chk_status (pi2c, I2C_STA_BB, 1) == OK) + return ERROR; + } + + return (OK); +} + +/****************************************************************************** + * + * I2C Disable - Disable the I2C Controller + * + */ +STATUS i2c_disable (PSI2C pi2c) +{ + i2c_clear (pi2c); + + pi2c->cr &= I2C_CTL_EN; /* Disable I2c */ + + if ((pi2c->cr & I2C_CTL_STA) == I2C_CTL_STA) + pi2c->cr &= ~I2C_CTL_STA; + + if (chk_status (pi2c, I2C_STA_BB, 0) != OK) + return ERROR; + + return (OK); +} + +/****************************************************************************** + * + * I2C Clear - Clear the I2C Controller + * + */ +STATUS i2c_clear (PSI2C pi2c) +{ + pi2c->adr = 0; + pi2c->fdr = 0; + pi2c->cr = 0; + pi2c->sr = 0; + + return (OK); +} + + +STATUS i2c_start (PSI2C pi2c, PI2CSET pi2cSet) +{ +#ifdef TWOBYTES + UINT16 ByteOffset = pi2cSet->str_adr; +#else + UINT8 ByteOffset = pi2cSet->str_adr; +#endif +#if 1 + UINT8 tmp = 0; +#endif + UINT8 Addr = pi2cSet->slv_adr; + + pi2c->cr |= I2C_CTL_STA; /* Generate start signal */ + + if (chk_status (pi2c, I2C_STA_BB, 1) != OK) + return ERROR; + + /* Write slave address */ + if (i2c_writebyte (pi2c, &Addr) != OK) { + i2c_stop (pi2c); /* Disable I2c */ + return ERROR; + } +#ifdef TWOBYTES +# if 0 + /* Issue the offset to start */ + if (i2c_write2byte (pi2c, &ByteOffset) != OK) { + i2c_stop (pi2c); /* Disable I2c */ + return ERROR; + } +#endif + tmp = (ByteOffset >> 8) & 0xff; + if (i2c_writebyte (pi2c, &tmp) != OK) { + i2c_stop (pi2c); /* Disable I2c */ + return ERROR; + } + tmp = ByteOffset & 0xff; + if (i2c_writebyte (pi2c, &tmp) != OK) { + i2c_stop (pi2c); /* Disable I2c */ + return ERROR; + } +#else + if (i2c_writebyte (pi2c, &ByteOffset) != OK) { + i2c_stop (pi2c); /* Disable I2c */ + return ERROR; + } +#endif + + return (OK); +} + +STATUS i2c_stop (PSI2C pi2c) +{ + pi2c->cr &= ~I2C_CTL_STA; /* Generate stop signal */ + if (chk_status (pi2c, I2C_STA_BB, 0) != OK) + return ERROR; + + return (OK); +} + +/****************************************************************************** + * + * Read Len bytes to the location pointed to by *Data from the device + * with address Addr. + */ +int i2c_readblock (SI2C * pi2c, PI2CSET pi2cSet, UINT8 * Data) +{ + int i = 0; + UINT8 Tmp; + +/* UINT8 ByteOffset = pi2cSet->str_adr; not used? */ + UINT8 Addr = pi2cSet->slv_adr; + int Length = pi2cSet->xfer_size; + + I2CCDBG (L1, ("i2c_readblock addr %x data 0x%08x len %d offset %d\n", + Addr, (int) Data, Length, ByteOffset, 0, 0)); + + if (pi2c->sr & I2C_STA_AL) { /* Check if Arbitration lost */ + I2CCDBG (FN, ("Arbitration lost\n", 0, 0, 0, 0, 0, 0)); + pi2c->sr &= ~I2C_STA_AL; /* Clear Arbitration status bit */ + return ERROR; + } + + pi2c->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */ + + if (i2c_start (pi2c, pi2cSet) == ERROR) + return ERROR; + + pi2c->cr |= I2C_CTL_RSTA; /* Repeat Start */ + + Tmp = Addr | 1; + + if (i2c_writebyte (pi2c, &Tmp) != OK) { + i2c_stop (pi2c); /* Disable I2c */ + return ERROR; + } + + if (((pi2c->sr & 0x07) == 0x07) || (pi2c->sr & 0x01)) + return ERROR; + + pi2c->cr &= ~I2C_CTL_TX; /* Set receive mode */ + + if (((pi2c->sr & 0x07) == 0x07) || (pi2c->sr & 0x01)) + return ERROR; + + /* Dummy Read */ + if (i2c_readbyte (pi2c, &Tmp, &i) != OK) { + i2c_stop (pi2c); /* Disable I2c */ + return ERROR; + } + + i = 0; + while (Length) { + if (Length == 2) + pi2c->cr |= I2C_CTL_TXAK; + + if (Length == 1) + pi2c->cr &= ~I2C_CTL_STA; + + if (i2c_readbyte (pi2c, Data, &Length) != OK) { + return i2c_stop (pi2c); + } + i++; + Length--; + Data++; + } + + if (i2c_stop (pi2c) == ERROR) + return ERROR; + + return i; +} + +STATUS i2c_writeblock (SI2C * pi2c, PI2CSET pi2cSet, UINT8 * Data) +{ + int Length = pi2cSet->xfer_size; + +#ifdef TWOBYTES + UINT16 ByteOffset = pi2cSet->str_adr; +#else + UINT8 ByteOffset = pi2cSet->str_adr; +#endif + int j, k; + + I2CCDBG (L2, ("i2c_writeblock\n", 0, 0, 0, 0, 0, 0)); + + if (pi2c->sr & I2C_STA_AL) { + /* Check if arbitration lost */ + I2CCDBG (L2, ("Arbitration lost\n", 0, 0, 0, 0, 0, 0)); + pi2c->sr &= ~I2C_STA_AL; /* Clear the condition */ + return ERROR; + } + + pi2c->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */ + + /* Do the not even offset first */ + if ((ByteOffset % 8) != 0) { + int remain; + + if (Length > 8) { + remain = 8 - (ByteOffset % 8); + Length -= remain; + + pi2cSet->str_adr = ByteOffset; + + if (i2c_start (pi2c, pi2cSet) == ERROR) + return ERROR; + + for (j = ByteOffset; j < remain; j++) { + if (i2c_writebyte (pi2c, Data++) != OK) + return ERROR; + } + + if (i2c_stop (pi2c) == ERROR) + return ERROR; + + sysMsDelay (32); + + /* Update the new ByteOffset */ + ByteOffset += remain; + } + } + + for (j = ByteOffset, k = 0; j < (Length + ByteOffset); j++) { + if ((j % 8) == 0) { + pi2cSet->str_adr = j; + if (i2c_start (pi2c, pi2cSet) == ERROR) + return ERROR; + } + + k++; + + if (i2c_writebyte (pi2c, Data++) != OK) + return ERROR; + + if ((j == (Length - 1)) || ((k % 8) == 0)) { + if (i2c_stop (pi2c) == ERROR) + return ERROR; + + sysMsDelay (50); + } + + } + + return k; +} + +STATUS i2c_readbyte (SI2C * pi2c, UINT8 * readb, int *index) +{ + pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt Bit */ + *readb = pi2c->dr; /* Read a byte */ + + /* + Set I2C_CTRL_TXAK will cause Transfer pending and + set I2C_CTRL_STA will cause Interrupt pending + */ + if (*index != 2) { + if (chk_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */ + return ERROR; + } + + if (*index != 1) { + if (chk_status (pi2c, I2C_STA_IF, 1) != OK) + return ERROR; + } + + return (OK); +} + + +STATUS i2c_writebyte (SI2C * pi2c, UINT8 * writeb) +{ + pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt */ + pi2c->dr = *writeb; /* Write a byte */ + + if (chk_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */ + return ERROR; + + if (chk_status (pi2c, I2C_STA_IF, 1) != OK) + return ERROR; + + return OK; +} + +STATUS i2c_write2byte (SI2C * pi2c, UINT16 * writeb) +{ + UINT8 data; + + data = (UINT8) ((*writeb >> 8) & 0xff); + if (i2c_writebyte (pi2c, &data) != OK) + return ERROR; + data = (UINT8) (*writeb & 0xff); + if (i2c_writebyte (pi2c, &data) != OK) + return ERROR; + return OK; +} + +/* FDR table base on 33Mhz - more detail please refer to Odini2c_dividers.xls +FDR FDR scl sda scl2tap2 +510 432 tap tap tap tap scl_per sda_hold I2C Freq 0 1 2 3 4 5 +000 000 9 3 4 1 28 Clocks 9 Clocks 1190 KHz 0 0 0 0 0 0 +000 001 9 3 4 2 44 Clocks 11 Clocks 758 KHz 0 0 1 0 0 0 +000 010 9 3 6 4 80 Clocks 17 Clocks 417 KHz 0 0 0 1 0 0 +000 011 9 3 6 8 144 Clocks 25 Clocks 231 KHz 0 0 1 1 0 0 +000 100 9 3 14 16 288 Clocks 49 Clocks 116 KHz 0 0 0 0 1 0 +000 101 9 3 30 32 576 Clocks 97 Clocks 58 KHz 0 0 1 0 1 0 +000 110 9 3 62 64 1152 Clocks 193 Clocks 29 KHz 0 0 0 1 1 0 +000 111 9 3 126 128 2304 Clocks 385 Clocks 14 KHz 0 0 1 1 1 0 +001 000 10 3 4 1 30 Clocks 9 Clocks 1111 KHz1 0 0 0 0 0 +001 001 10 3 4 2 48 Clocks 11 Clocks 694 KHz 1 0 1 0 0 0 +001 010 10 3 6 4 88 Clocks 17 Clocks 379 KHz 1 0 0 1 0 0 +001 011 10 3 6 8 160 Clocks 25 Clocks 208 KHz 1 0 1 1 0 0 +001 100 10 3 14 16 320 Clocks 49 Clocks 104 KHz 1 0 0 0 1 0 +001 101 10 3 30 32 640 Clocks 97 Clocks 52 KHz 1 0 1 0 1 0 +001 110 10 3 62 64 1280 Clocks 193 Clocks 26 KHz 1 0 0 1 1 0 +001 111 10 3 126 128 2560 Clocks 385 Clocks 13 KHz 1 0 1 1 1 0 +010 000 12 4 4 1 34 Clocks 10 Clocks 980 KHz 0 1 0 0 0 0 +010 001 12 4 4 2 56 Clocks 13 Clocks 595 KHz 0 1 1 0 0 0 +010 010 12 4 6 4 104 Clocks 21 Clocks 321 KHz 0 1 0 1 0 0 +010 011 12 4 6 8 192 Clocks 33 Clocks 174 KHz 0 1 1 1 0 0 +010 100 12 4 14 16 384 Clocks 65 Clocks 87 KHz 0 1 0 0 1 0 +010 101 12 4 30 32 768 Clocks 129 Clocks 43 KHz 0 1 1 0 1 0 +010 110 12 4 62 64 1536 Clocks 257 Clocks 22 KHz 0 1 0 1 1 0 +010 111 12 4 126 128 3072 Clocks 513 Clocks 11 KHz 0 1 1 1 1 0 +011 000 15 4 4 1 40 Clocks 10 Clocks 833 KHz 1 1 0 0 0 0 +011 001 15 4 4 2 68 Clocks 13 Clocks 490 KHz 1 1 1 0 0 0 +011 010 15 4 6 4 128 Clocks 21 Clocks 260 KHz 1 1 0 1 0 0 +011 011 15 4 6 8 240 Clocks 33 Clocks 139 KHz 1 1 1 1 0 0 +011 100 15 4 14 16 480 Clocks 65 Clocks 69 KHz 1 1 0 0 1 0 +011 101 15 4 30 32 960 Clocks 129 Clocks 35 KHz 1 1 1 0 1 0 +011 110 15 4 62 64 1920 Clocks 257 Clocks 17 KHz 1 1 0 1 1 0 +011 111 15 4 126 128 3840 Clocks 513 Clocks 9 KHz 1 1 1 1 1 0 +100 000 5 1 4 1 20 Clocks 7 Clocks 1667 KHz 0 0 0 0 0 1 +100 001 5 1 4 2 28 Clocks 7 Clocks 1190 KHz 0 0 1 0 0 1 +100 010 5 1 6 4 48 Clocks 9 Clocks 694 KHz 0 0 0 1 0 1 +100 011 5 1 6 8 80 Clocks 9 Clocks 417 KHz 0 0 1 1 0 1 +100 100 5 1 14 16 160 Clocks 17 Clocks 208 KHz 0 0 0 0 1 1 +100 101 5 1 30 32 320 Clocks 33 Clocks 104 KHz 0 0 1 0 1 1 +100 110 5 1 62 64 640 Clocks 65 Clocks 52 KHz 0 0 0 1 1 1 +100 111 5 1 126 128 1280 Clocks 129 Clocks 26 KHz 0 0 1 1 1 1 +101 000 6 1 4 1 22 Clocks 7 Clocks 1515 KHz 1 0 0 0 0 1 +101 001 6 1 4 2 32 Clocks 7 Clocks 1042 KHz 1 0 1 0 0 1 +101 010 6 1 6 4 56 Clocks 9 Clocks 595 KHz 1 0 0 1 0 1 +101 011 6 1 6 8 96 Clocks 9 Clocks 347 KHz 1 0 1 1 0 1 +101 100 6 1 14 16 192 Clocks 17 Clocks 174 KHz 1 0 0 0 1 1 +101 101 6 1 30 32 384 Clocks 33 Clocks 87 KHz 1 0 1 0 1 1 +101 110 6 1 62 64 768 Clocks 65 Clocks 43 KHz 1 0 0 1 1 1 +101 111 6 1 126 128 1536 Clocks 129 Clocks 22 KHz 1 0 1 1 1 1 +110 000 7 2 4 1 24 Clocks 8 Clocks 1389 KHz 0 1 0 0 0 1 +110 001 7 2 4 2 36 Clocks 9 Clocks 926 KHz 0 1 1 0 0 1 +110 010 7 2 6 4 64 Clocks 13 Clocks 521 KHz 0 1 0 1 0 1 +110 011 7 2 6 8 112 Clocks 17 Clocks 298 KHz 0 1 1 1 0 1 +110 100 7 2 14 16 224 Clocks 33 Clocks 149 KHz 0 1 0 0 1 1 +110 101 7 2 30 32 448 Clocks 65 Clocks 74 KHz 0 1 1 0 1 1 +110 110 7 2 62 64 896 Clocks 129 Clocks 37 KHz 0 1 0 1 1 1 +110 111 7 2 126 128 1792 Clocks 257 Clocks 19 KHz 0 1 1 1 1 1 +111 000 8 2 4 1 26 Clocks 8 Clocks 1282 KHz 1 1 0 0 0 1 +111 001 8 2 4 2 40 Clocks 9 Clocks 833 KHz 1 1 1 0 0 1 +111 010 8 2 6 4 72 Clocks 13 Clocks 463 KHz 1 1 0 1 0 1 +111 011 8 2 6 8 128 Clocks 17 Clocks 260 KHz 1 1 1 1 0 1 +111 100 8 2 14 16 256 Clocks 33 Clocks 130 KHz 1 1 0 0 1 1 +111 101 8 2 30 32 512 Clocks 65 Clocks 65 KHz 1 1 1 0 1 1 +111 110 8 2 62 64 1024 Clocks 129 Clocks 33 KHz 1 1 0 1 1 1 +111 111 8 2 126 128 2048 Clocks 257 Clocks 16 KHz 1 1 1 1 1 1 +*/ +STATUS SetI2cFDR (PSI2C pi2cRegs, int bitrate) +{ +/* Constants */ + const UINT8 div_hold[8][3] = { {9, 3}, {10, 3}, + {12, 4}, {15, 4}, + {5, 1}, {6, 1}, + {7, 2}, {8, 2} + }; + + const UINT8 scl_tap[8][2] = { {4, 1}, {4, 2}, + {6, 4}, {6, 8}, + {14, 16}, {30, 32}, + {62, 64}, {126, 128} + }; + + UINT8 mfdr_bits; + + int i = 0; + int j = 0; + + int Diff, min; + int WhichFreq, iRec, jRec; + int SCL_Period; + int SCL_Hold; + int I2C_Freq; + + I2CCDBG (L2, ("Entering getBitRate: bitrate %d pi2cRegs 0x%08x\n", + bitrate, (int) pi2cRegs, 0, 0, 0, 0)); + + if (bitrate < 0) { + I2CCDBG (NO, ("Invalid bitrate\n", 0, 0, 0, 0, 0, 0)); + return ERROR; + } + + /* Initialize */ + mfdr_bits = 0; + min = 0x7fffffff; + WhichFreq = iRec = jRec = 0; + + for (i = 0; i < 8; i++) { + for (j = 0; j < 8; j++) { + /* SCL Period = 2 * (scl2tap + [(SCL_Tap - 1) * tap2tap] + 2) + * SCL Hold = scl2tap + ((SDA_Tap - 1) * tap2tap) + 3 + * Bit Rate (I2C Freq) = System Freq / SCL Period + */ + SCL_Period = + 2 * (scl_tap[i][0] + + ((div_hold[j][0] - 1) * scl_tap[i][1]) + + 2); + + /* Now get the I2C Freq */ + I2C_Freq = DEV_CLOCK_FREQ / SCL_Period; + + /* Take equal or slower */ + if (I2C_Freq > bitrate) + continue; + + /* Take the differences */ + Diff = I2C_Freq - bitrate; + + Diff = ABS (Diff); + + /* Find the closer value */ + if (Diff < min) { + min = Diff; + WhichFreq = I2C_Freq; + iRec = i; + jRec = j; + } + + I2CCDBG (L2, + ("--- (%d,%d) I2C_Freq %d minDiff %d min %d\n", + i, j, I2C_Freq, Diff, min, 0)); + } + } + + SCL_Period = + 2 * (scl_tap[iRec][0] + + ((div_hold[jRec][0] - 1) * scl_tap[iRec][1]) + 2); + + I2CCDBG (L2, ("\nmin %d WhichFreq %d iRec %d jRec %d\n", + min, WhichFreq, iRec, jRec, 0, 0)); + I2CCDBG (L2, ("--- scl2tap %d SCL_Tap %d tap2tap %d\n", + scl_tap[iRec][0], div_hold[jRec][0], scl_tap[iRec][1], + 0, 0, 0)); + + /* This may no require */ + SCL_Hold = + scl_tap[iRec][0] + + ((div_hold[jRec][1] - 1) * scl_tap[iRec][1]) + 3; + I2CCDBG (L2, + ("--- SCL_Period %d SCL_Hold %d\n", SCL_Period, SCL_Hold, 0, + 0, 0, 0)); + + I2CCDBG (L2, ("--- mfdr_bits %x\n", mfdr_bits, 0, 0, 0, 0, 0)); + + /* FDR 4,3,2 */ + if ((iRec & 1) == 1) + mfdr_bits |= 0x04; /* FDR 2 */ + if ((iRec & 2) == 2) + mfdr_bits |= 0x08; /* FDR 3 */ + if ((iRec & 4) == 4) + mfdr_bits |= 0x10; /* FDR 4 */ + /* FDR 5,1,0 */ + if ((jRec & 1) == 1) + mfdr_bits |= 0x01; /* FDR 0 */ + if ((jRec & 2) == 2) + mfdr_bits |= 0x02; /* FDR 1 */ + if ((jRec & 4) == 4) + mfdr_bits |= 0x20; /* FDR 5 */ + + I2CCDBG (L2, ("--- mfdr_bits %x\n", mfdr_bits, 0, 0, 0, 0, 0)); + + pi2cRegs->fdr = mfdr_bits; + + return OK; +} diff --git a/cpu/mpc8220/i2cCore.h b/cpu/mpc8220/i2cCore.h new file mode 100644 index 0000000..72783fd --- /dev/null +++ b/cpu/mpc8220/i2cCore.h @@ -0,0 +1,103 @@ +/* + * i2cCore.h + * + * Prototypes, etc. for the Motorola MPC8220 + * embedded cpu chips + * + * 2004 (c) Freescale, Inc. + * Author: TsiChung Liew + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __INCi2ccoreh +#define __INCi2ccoreh +#ifndef __ASSEMBLY__ +/* device types */ +#define I2C_DEVICE_TYPE_EEPROM 0 +#define I2C_EEPROM_ADRS 0xa0 +#define I2C_CTRL_ADRS I2C_EEPROM_ADRS +#define EEPROM_ADDR0 0xA2 /* on Dimm SPD eeprom */ +#define EEPROM_ADDR1 0xA4 /* on Board SPD eeprom */ +#define EEPROM_ADDR2 0xD2 /* non-standard eeprom - clock generator */ +/* Control Register */ +#define I2C_CTL_EN 0x80 /* I2C Enable */ +#define I2C_CTL_IEN 0x40 /* I2C Interrupt Enable */ +#define I2C_CTL_STA 0x20 /* Master/Slave Mode select */ +#define I2C_CTL_TX 0x10 /* Transmit/Receive Mode Select */ +#define I2C_CTL_TXAK 0x08 /* Transmit Acknowledge Enable */ +#define I2C_CTL_RSTA 0x04 /* Repeat Start */ +/* Status Register */ +#define I2C_STA_CF 0x80 /* Data Transfer */ +#define I2C_STA_AAS 0x40 /* Adressed As Slave */ +#define I2C_STA_BB 0x20 /* Bus Busy */ +#define I2C_STA_AL 0x10 /* Arbitration Lost */ +#define I2C_STA_SRW 0x04 /* Slave Read/Write */ +#define I2C_STA_IF 0x02 /* I2C Interrupt */ +#define I2C_STA_RXAK 0x01 /* Receive Acknowledge */ +/* Interrupt Contol Register */ +#define I2C_INT_BNBE2 0x80 /* Bus Not Busy Enable 2 */ +#define I2C_INT_TE2 0x40 /* Transmit Enable 2 */ +#define I2C_INT_RE2 0x20 /* Receive Enable 2 */ +#define I2C_INT_IE2 0x10 /* Interrupt Enable 2 */ +#define I2C_INT_BNBE1 0x08 /* Bus Not Busy Enable 1 */ +#define I2C_INT_TE1 0x04 /* Transmit Enable 1 */ +#define I2C_INT_RE1 0x02 /* Receive Enable 1 */ +#define I2C_INT_IE1 0x01 /* Interrupt Enable 1 */ +#define I2C_POLL_COUNT 0x100000 +#define I2C_ENABLE 0x00000001 +#define I2C_DISABLE 0x00000002 +#define I2C_START 0x00000004 +#define I2C_REPSTART 0x00000008 +#define I2C_STOP 0x00000010 +#define I2C_BITRATE 0x00000020 +#define I2C_SLAVEADR 0x00000040 +#define I2C_STARTADR 0x00000080 +#undef TWOBYTES +typedef struct i2c_settings { + /* Device settings */ + int bit_rate; /* Device bit rate */ + u8 i2c_adr; /* I2C address */ + u8 slv_adr; /* Slave address */ +#ifdef TWOBYTES + u16 str_adr; /* Start address */ +#else + u8 str_adr; /* Start address */ +#endif + int xfer_size; /* Transfer Size */ + + int bI2c_en; /* Enable or Disable */ + int cmdFlag; /* I2c Command Flags */ +} i2cset_t; + +/* +int check_status(PSI2C pi2c, u8 sta_bit, u8 truefalse); +int i2c_enable(PSI2C pi2c, PI2CSET pi2cSet); +int i2c_disable(PSI2C pi2c); +int i2c_start(PSI2C pi2c, PI2CSET pi2cSet); +int i2c_stop(PSI2C pi2c); +int i2c_clear(PSI2C pi2c); +int i2c_readblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data); +int i2c_writeblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data); +int i2c_readbyte(PSI2C pi2c, u8 *readb, int *index); +int i2c_writebyte(PSI2C pi2c, u8 *writeb); +int SetI2cFDR( PSI2C pi2cRegs, int bitrate ); +*/ +#endif /* __ASSEMBLY__ */ + +#endif /* __INCi2ccoreh */ diff --git a/cpu/mpc8220/interrupts.c b/cpu/mpc8220/interrupts.c new file mode 100644 index 0000000..036378c --- /dev/null +++ b/cpu/mpc8220/interrupts.c @@ -0,0 +1,80 @@ +/* + * (C) Copyright -2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * interrupts.c - just enough support for the decrementer/timer + */ + +#include +#include +#include + +int interrupt_init_cpu (ulong * decrementer_count) +{ + *decrementer_count = get_tbclk () / CFG_HZ; + + return (0); +} + +/****************************************************************************/ + +/* + * Handle external interrupts + */ +void external_interrupt (struct pt_regs *regs) +{ + puts ("external_interrupt (oops!)\n"); +} + +void timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} + +/****************************************************************************/ + +/* + * Install and free a interrupt handler. + */ + +void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) +{ + +} + +void irq_free_handler (int vec) +{ + +} + +/****************************************************************************/ + +void +do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + puts ("IRQ related functions are unimplemented currently.\n"); +} diff --git a/cpu/mpc8220/io.S b/cpu/mpc8220/io.S new file mode 100644 index 0000000..5ecdf55 --- /dev/null +++ b/cpu/mpc8220/io.S @@ -0,0 +1,128 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * Copyright (C) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* ------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/* ------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in16 */ +/* Description: Input 16 bits */ +/* ------------------------------------------------------------------------------- */ + .globl in16 +in16: + lhz r3,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in16r */ +/* Description: Input 16 bits and byte reverse */ +/* ------------------------------------------------------------------------------- */ + .globl in16r +in16r: + lhbrx r3,0,r3 + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/* ------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0(3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: in32r */ +/* Description: Input 32 bits and byte reverse */ +/* ------------------------------------------------------------------------------- */ + .globl in32r +in32r: + lwbrx r3,0,r3 + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out16 */ +/* Description: Output 16 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out16 +out16: + sth r4,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out16r */ +/* Description: Byte reverse and output 16 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out16r +out16r: + sthbrx r4,0,r3 + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0(r3) + sync + blr + +/* ------------------------------------------------------------------------------- */ +/* Function: out32r */ +/* Description: Byte reverse and output 32 bits */ +/* ------------------------------------------------------------------------------- */ + .globl out32r +out32r: + stwbrx r4,0,r3 + sync + blr diff --git a/cpu/mpc8220/loadtask.c b/cpu/mpc8220/loadtask.c new file mode 100644 index 0000000..6d8b627 --- /dev/null +++ b/cpu/mpc8220/loadtask.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on code + * (C) Copyright Motorola, Inc., 2000 + */ + +#include +#include + +/* Multichannel DMA microcode */ +extern int taskTable; + +void loadtask (int basetask, int tasks) +{ + int *sram = (int *) (MMAP_SRAM + 512); + int *task_org = &taskTable; + unsigned int start, offset, end; + int i; + +#ifdef DEBUG + printf ("basetask = %d, tasks = %d\n", basetask, tasks); + printf ("task_org = 0x%08x\n", (unsigned int) task_org); +#endif + + /* setup TaskBAR register */ + *(vu_long *) MMAP_DMA = (MMAP_SRAM + 512); + + /* relocate task table entries */ + offset = (unsigned int) sram; + for (i = basetask; i < basetask + tasks; i++) { + sram[i * 8 + 0] = task_org[i * 8 + 0] + offset; + sram[i * 8 + 1] = task_org[i * 8 + 1] + offset; + sram[i * 8 + 2] = task_org[i * 8 + 2] + offset; + sram[i * 8 + 3] = task_org[i * 8 + 3] + offset; + sram[i * 8 + 4] = task_org[i * 8 + 4]; + sram[i * 8 + 5] = task_org[i * 8 + 5]; + sram[i * 8 + 6] = task_org[i * 8 + 6] + offset; + sram[i * 8 + 7] = task_org[i * 8 + 7]; + } + + /* relocate task descriptors */ + start = (sram[basetask * 8] - (unsigned int) sram); + end = (sram[(basetask + tasks - 1) * 8 + 1] - (unsigned int) sram); + +#ifdef DEBUG + printf ("TDT start = 0x%08x, end = 0x%08x\n", start, end); +#endif + + start /= 4; + end /= 4; + for (i = start; i <= end; i++) { + sram[i] = task_org[i]; + } + + /* relocate variables */ + start = (sram[basetask * 8 + 2] - (unsigned int) sram); + end = (sram[(basetask + tasks - 1) * 8 + 2] + 256 - + (unsigned int) sram); + start /= 4; + end /= 4; + for (i = start; i < end; i++) { + sram[i] = task_org[i]; + } + + /* relocate function decriptors */ + start = ((sram[basetask * 8 + 3] & 0xfffffffc) - (unsigned int) sram); + end = ((sram[(basetask + tasks - 1) * 8 + 3] & 0xfffffffc) + 256 - + (unsigned int) sram); + start /= 4; + end /= 4; + for (i = start; i < end; i++) { + sram[i] = task_org[i]; + } + + asm volatile ("sync"); +} diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c new file mode 100644 index 0000000..ca4a04d --- /dev/null +++ b/cpu/mpc8220/pci.c @@ -0,0 +1,191 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI Configuration space access support for MPC8220 PCI Bridge + */ +#include +#include +#include +#include + +#if defined(CONFIG_PCI) + +/* System RAM mapped over PCI */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define cfg_read(val, addr, type, op) *val = op((type)(addr)); +#define cfg_write(val, addr, type, op) op((type *)(addr), (val)); + +#define PCI_OP(rw, size, type, op, mask) \ +int mpc8220_pci_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + u32 addr = 0; \ + u16 cfg_type = 0; \ + addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ + out_be32(hose->cfg_addr, addr); \ + __asm__ __volatile__("sync"); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + out_be32(hose->cfg_addr, addr & 0x7fffffff); \ + __asm__ __volatile__("sync"); \ + return 0; \ +} + +PCI_OP(read, byte, u8 *, in_8, 3) +PCI_OP(read, word, u16 *, in_le16, 2) +PCI_OP(write, byte, u8, out_8, 3) +PCI_OP(write, word, u16, out_le16, 2) +PCI_OP(write, dword, u32, out_le32, 0) + +int mpc8220_pci_read_config_dword(struct pci_controller *hose, pci_dev_t dev, + int offset, u32 *val) +{ + u32 addr; + u32 tmpv; + u32 mask = 2; /* word access */ + /* Read lower 16 bits */ + addr = ((offset & 0xfc) | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + __asm__ __volatile__("sync"); + *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + __asm__ __volatile__("sync"); + + /* Read upper 16 bits */ + offset += 2; + addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + __asm__ __volatile__("sync"); + tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + __asm__ __volatile__("sync"); + + /* combine results into dword value */ + *val = (tmpv << 16) | *val; + + return 0; +} + +void +pci_mpc8220_init(struct pci_controller *hose) +{ + u32 win0, win1, win2; + volatile mpc8220_xcpci_t *xcpci = + (volatile mpc8220_xcpci_t *) MMAP_XCPCI; + + volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG; + + win0 = (u32) CONFIG_PCI_MEM_PHYS; + win1 = (u32) CONFIG_PCI_IO_PHYS; + win2 = (u32) CONFIG_PCI_CFG_PHYS; + + /* Assert PCI reset */ + out_be32 (&xcpci->glb_stat_ctl, PCI_GLB_STAT_CTRL_PR); + + /* Disable prefetching but read-multiples will still prefetch */ + out_be32 (&xcpci->target_ctrl, 0x00000000); + + /* Initiator windows */ + out_be32 (&xcpci->init_win0, (win0 >> 16) | win0 | 0x003f0000); + out_be32 (&xcpci->init_win1, ((win1 >> 16) | win1 )); + out_be32 (&xcpci->init_win2, ((win2 >> 16) | win2 )); + + out_be32 (&xcpci->init_win_cfg, + PCI_INIT_WIN_CFG_WIN0_CTRL_EN | + PCI_INIT_WIN_CFG_WIN1_CTRL_EN | PCI_INIT_WIN_CFG_WIN1_CTRL_IO | + PCI_INIT_WIN_CFG_WIN2_CTRL_EN | PCI_INIT_WIN_CFG_WIN2_CTRL_IO); + + out_be32 (&xcpci->init_ctrl, 0x00000000); + + /* Enable bus master and mem access */ + out_be32 (&xcpci->stat_cmd_reg, PCI_STAT_CMD_B | PCI_STAT_CMD_M); + + /* Cache line size and master latency */ + out_be32 (&xcpci->bist_htyp_lat_cshl, (0xf8 << PCI_CFG1_LT_SHIFT)); + + out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */ + out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */ + + out_be32 (&xcpci->target_bar0, + PCI_TARGET_BASE_ADDR_REG0 | PCI_TARGET_BASE_ADDR_EN); + out_be32 (&xcpci->target_bar1, + PCI_TARGET_BASE_ADDR_REG1 | PCI_TARGET_BASE_ADDR_EN); + + /* Deassert reset bit */ + out_be32 (&xcpci->glb_stat_ctl, 0x00000000); + + /* Enable PCI bus master support */ + /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, + PCIREQ2, PCIGNT2 */ + out_be32((volatile u32 *)&portcfg->pcfg3, + (in_be32((volatile u32 *)&portcfg->pcfg3) & 0xFC3FCE7F)); + out_be32((volatile u32 *)&portcfg->pcfg3, + (in_be32((volatile u32 *)&portcfg->pcfg3) | 0x01400180)); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + CONFIG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 3; + + hose->cfg_addr = &(xcpci->cfg_adr); + hose->cfg_data = CONFIG_PCI_CFG_BUS; + + pci_set_ops(hose, + mpc8220_pci_read_config_byte, + mpc8220_pci_read_config_word, + mpc8220_pci_read_config_dword, + mpc8220_pci_write_config_byte, + mpc8220_pci_write_config_word, + mpc8220_pci_write_config_dword); + + /* Hose scan */ + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); + + out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */ + out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */ +} + +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc8220/speed.c b/cpu/mpc8220/speed.c new file mode 100644 index 0000000..8346efe --- /dev/null +++ b/cpu/mpc8220/speed.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2004, Freescale, Inc + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +typedef struct pllmultiplier { + u8 hid1; + int multi; + int vco_div; +} pllcfg_t; + +/* ------------------------------------------------------------------------- */ + +/* + * + */ + +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + pllcfg_t bus2core[] = { + {0x02, 2, 8}, /* 1 */ + {0x01, 2, 4}, + {0x0C, 3, 8}, /* 1.5 */ + {0x00, 3, 4}, + {0x18, 3, 2}, + {0x05, 4, 4}, /* 2 */ + {0x04, 4, 2}, + {0x11, 5, 4}, /* 2.5 */ + {0x06, 5, 2}, + {0x10, 6, 4}, /* 3 */ + {0x08, 6, 2}, + {0x0E, 7, 2}, /* 3.5 */ + {0x0A, 8, 2}, /* 4 */ + {0x07, 9, 2}, /* 4.5 */ + {0x0B, 10, 2}, /* 5 */ + {0x09, 11, 2}, /* 5.5 */ + {0x0D, 12, 2}, /* 6 */ + {0x12, 13, 2}, /* 6.5 */ + {0x14, 14, 2}, /* 7 */ + {0x16, 15, 2}, /* 7.5 */ + {0x1C, 16, 2} /* 8 */ + }; + u32 hid1; + int i, size, pci2bus; + +#if !defined(CFG_MPC8220_CLKIN) +#error clock measuring not implemented yet - define CFG_MPC8220_CLKIN +#endif + + gd->inp_clk = CFG_MPC8220_CLKIN; + + /* Read XLB to PCI(INP) clock multiplier */ + pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) & + PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT; + + /* XLB bus clock */ + gd->bus_clk = CFG_MPC8220_CLKIN * pci2bus; + + /* PCI clock is same as input clock */ + gd->pci_clk = CFG_MPC8220_CLKIN; + + /* FlexBus is temporary set as the same as input clock */ + /* will do dynamic in the future */ + gd->flb_clk = CFG_MPC8220_CLKIN; + + /* CPU Clock - Read HID1 */ + asm volatile ("mfspr %0, 1009":"=r" (hid1):); + + size = sizeof (bus2core) / sizeof (pllcfg_t); + + hid1 >>= 27; + + for (i = 0; i < size; i++) + if (hid1 == bus2core[i].hid1) { + gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1; + gd->vco_clk = CFG_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2; + break; + } + + /* hardcoded 81MHz for now */ + gd->pev_clk = 81000000; + + return (0); +} + +int prt_mpc8220_clks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + printf (" Bus %ld MHz, CPU %ld MHz, PCI %ld MHz, VCO %ld MHz\n", + gd->bus_clk / 1000000, gd->cpu_clk / 1000000, + gd->pci_clk / 1000000, gd->vco_clk / 1000000); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S new file mode 100644 index 0000000..5233202 --- /dev/null +++ b/cpu/mpc8220/start.S @@ -0,0 +1,775 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000 - 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot - Startup Code for MPC8220 CPUs + */ +#include +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +/* Floating Point enable, Machine Check and Recoverable Interr. */ +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * Version string + */ + .data + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + +/* + * Exception vectors + */ + .text + . = EXC_OFF_SYS_RESET + .globl _start +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On */ + nop + b boot_cold + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + +boot_cold: +boot_warm: + mfmsr r5 /* save msr contents */ + + /* replace default MBAR base address from 0x80000000 + to 0xf0000000 */ + +#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT) + lis r3, CFG_MBAR@h + ori r3, r3, CFG_MBAR@l + + /* MBAR is mirrored into the MBAR SPR */ + mtspr MBAR,r3 + mtspr SPRN_SPRG7W,r3 + lis r4, CFG_DEFAULT_MBAR@h + stw r3, 0(r4) +#endif /* CFG_DEFAULT_MBAR */ + + /* Initialise the MPC8220 processor core */ + /*--------------------------------------------------------------*/ + + bl init_8220_core + + /* initialize some things that are hard to access from C */ + /*--------------------------------------------------------------*/ + + /* set up stack in on-chip SRAM */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + ori r1, r3, CFG_INIT_SP_OFFSET + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*--------------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + bl cpu_init_f /* run low-level CPU init code (in Flash)*/ + + mr r3, r21 + /* r3: BOOTFLAG */ + bl board_init_f /* run 1st part of board init code (in Flash)*/ + +/* + * Vector Table + */ + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) +#ifdef DEBUG + . = 0x1300 + /* + * This exception occurs when the program counter matches the + * Instruction Address Breakpoint Register (IABR). + * + * I want the cpu to halt if this occurs so I can hunt around + * with the debugger and look at things. + * + * When DEBUG is defined, both machine check enable (in the MSR) + * and checkstop reset enable (in the reset mode register) are + * turned off and so a checkstop condition will result in the cpu + * halting. + * + * I force the cpu into a checkstop condition by putting an illegal + * instruction here (at least this is the theory). + * + * well - that didnt work, so just do an infinite loop! + */ +1: b 1b +#else + STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) +#endif + STD_EXCEPTION(0x1400, SMI, UnknownException) + + STD_EXCEPTION(0x1500, Trap_15, UnknownException) + STD_EXCEPTION(0x1600, Trap_16, UnknownException) + STD_EXCEPTION(0x1700, Trap_17, UnknownException) + STD_EXCEPTION(0x1800, Trap_18, UnknownException) + STD_EXCEPTION(0x1900, Trap_19, UnknownException) + STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) + STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) + STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) + STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) + STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) + STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) + STD_EXCEPTION(0x2000, Trap_20, UnknownException) + STD_EXCEPTION(0x2100, Trap_21, UnknownException) + STD_EXCEPTION(0x2200, Trap_22, UnknownException) + STD_EXCEPTION(0x2300, Trap_23, UnknownException) + STD_EXCEPTION(0x2400, Trap_24, UnknownException) + STD_EXCEPTION(0x2500, Trap_25, UnknownException) + STD_EXCEPTION(0x2600, Trap_26, UnknownException) + STD_EXCEPTION(0x2700, Trap_27, UnknownException) + STD_EXCEPTION(0x2800, Trap_28, UnknownException) + STD_EXCEPTION(0x2900, Trap_29, UnknownException) + STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) + STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) + STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) + STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) + STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) + STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) + + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x3000 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* + * This code initialises the MPC8220 processor core + * (conforms to PowerPC 603e spec) + * Note: expects original MSR contents to be in r5. + */ + + .globl init_8220_core +init_8220_core: + + /* Initialize machine status; enable machine check interrupt */ + /*--------------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ +#endif + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*--------------------------------------------------------------*/ + + lis r3, CFG_HID0_INIT@h + ori r3, r3, CFG_HID0_INIT@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID0_FINAL@h + ori r3, r3, CFG_HID0_FINAL@l + SYNC + mtspr HID0, r3 + + /* Enable Extra BATs */ + mfspr r3, 1011 /* HID2 */ + lis r4, 0x0004 + ori r4, r4, 0x0000 + or r4, r4, r3 + mtspr 1011, r4 + sync + + /* clear all BAT's */ + /*--------------------------------------------------------------*/ + + li r0, 0 + mtspr DBAT0U, r0 + mtspr DBAT0L, r0 + mtspr DBAT1U, r0 + mtspr DBAT1L, r0 + mtspr DBAT2U, r0 + mtspr DBAT2L, r0 + mtspr DBAT3U, r0 + mtspr DBAT3L, r0 + mtspr DBAT4U, r0 + mtspr DBAT4L, r0 + mtspr DBAT5U, r0 + mtspr DBAT5L, r0 + mtspr DBAT6U, r0 + mtspr DBAT6L, r0 + mtspr DBAT7U, r0 + mtspr DBAT7L, r0 + mtspr IBAT0U, r0 + mtspr IBAT0L, r0 + mtspr IBAT1U, r0 + mtspr IBAT1L, r0 + mtspr IBAT2U, r0 + mtspr IBAT2L, r0 + mtspr IBAT3U, r0 + mtspr IBAT3L, r0 + mtspr IBAT4U, r0 + mtspr IBAT4L, r0 + mtspr IBAT5U, r0 + mtspr IBAT5L, r0 + mtspr IBAT6U, r0 + mtspr IBAT6L, r0 + mtspr IBAT7U, r0 + mtspr IBAT7L, r0 + SYNC + + /* invalidate all tlb's */ + /* */ + /* From the 603e User Manual: "The 603e provides the ability to */ + /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ + /* instruction invalidates the TLB entry indexed by the EA, and */ + /* operates on both the instruction and data TLBs simultaneously*/ + /* invalidating four TLB entries (both sets in each TLB). The */ + /* index corresponds to bits 15-19 of the EA. To invalidate all */ + /* entries within both TLBs, 32 tlbie instructions should be */ + /* issued, incrementing this field by one each time." */ + /* */ + /* "Note that the tlbia instruction is not implemented on the */ + /* 603e." */ + /* */ + /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ + /* incrementing by 0x1000 each time. The code below is sort of */ + /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */ + /* */ + /*--------------------------------------------------------------*/ + + li r3, 32 + mtctr r3 + li r3, 0 +1: tlbie r3 + addi r3, r3, 0x1000 + bdnz 1b + SYNC + + /* Done! */ + /*--------------------------------------------------------------*/ + + blr + +/* Cache functions. + * + * Note: requires that all cache bits in + * HID0 are in the low half word. + */ + .globl icache_enable +icache_enable: + lis r4, 0 + ori r4, r4, CFG_HID0_INIT /* set ICE & ICFI bit */ + rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */ + + /* + * The setting of the instruction cache enable (ICE) bit must be + * preceded by an isync instruction to prevent the cache from being + * enabled or disabled while an instruction access is in progress. + */ + isync + mtspr HID0, r4 /* Enable Instr Cache & Inval cache */ + mtspr HID0, r3 /* using 2 consec instructions */ + isync + blr + + .globl icache_disable +icache_disable: + mfspr r3, HID0 + rlwinm r3, r3, 0, 17, 15 /* clear the ICE bit */ + mtspr HID0, r3 + isync + blr + + .globl icache_status +icache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 + blr + + .globl dcache_enable +dcache_enable: + lis r4, 0 + ori r4, r4, HID0_DCE|HID0_DCFI /* set DCE & DCFI bit */ + rlwinm r3, r4, 0, 22, 20 /* clear the DCFI bit */ + + /* Enable address translation in MSR bit */ + mfmsr r5 + ori r5, r5, 0x + + + /* + * The setting of the instruction cache enable (ICE) bit must be + * preceded by an isync instruction to prevent the cache from being + * enabled or disabled while an instruction access is in progress. + */ + isync + mtspr HID0, r4 /* Enable Data Cache & Inval cache*/ + mtspr HID0, r3 /* using 2 consec instructions */ + isync + blr + + .globl dcache_disable +dcache_disable: + mfspr r3, HID0 + rlwinm r3, r3, 0, 18, 16 /* clear the DCE bit */ + mtspr HID0, r3 + isync + blr + + .globl dcache_status +dcache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ + rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 + cmpwi r7,0 + beq 9f + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ +9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ + rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 + cmpwi r7,0 + beq 7f + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mfmsr r3 /* now that the vectors have */ + lis r7, MSR_IP@h /* relocated into low memory */ + ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ + andc r3, r3, r7 /* (if it was on) */ + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr diff --git a/cpu/mpc8220/traps.c b/cpu/mpc8220/traps.c new file mode 100644 index 0000000..cdee2be --- /dev/null +++ b/cpu/mpc8220/traps.c @@ -0,0 +1,239 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * fixed Machine Check Reasons by Reinhard Meyer (r.meyer@emk-elektronik.de) + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler) (struct pt_regs *) = 0; +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table (unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. +*/ +#define END_OF_MEM 0x02000000 + +/* + * Trap & Exception support + */ + +void print_backtrace (unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + printf ("Call backtrace: "); + while (sp) { + if ((uint) sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf ("\n"); + printf ("%08lX ", i); + if (cnt > 32) + break; + sp = (unsigned long *) *sp; + } + printf ("\n"); +} + +void show_regs (struct pt_regs *regs) +{ + int i; + + printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, + regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0, regs->msr & MSR_ME ? 1 : 0, + regs->msr & MSR_IR ? 1 : 0, regs->msr & MSR_DR ? 1 : 0); + + printf ("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + printf ("GPR%02d: ", i); + } + + printf ("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + printf ("\n"); + } + } +} + + +void _exception (int signr, struct pt_regs *regs) +{ + show_regs (regs); + print_backtrace ((unsigned long *) regs->gpr[1]); + panic ("Exception in kernel pc %lx signal %d", regs->nip, signr); +} + +void MachineCheckException (struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table (regs->nip)) != 0) { + regs->nip = fixup; + return; + } +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler + && (*debugger_exception_handler) (regs)) + return; +#endif + + printf ("Machine check in kernel mode.\n"); + printf ("Caused by (from msr): "); + printf ("regs %p ", regs); + /* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */ + switch (regs->msr & 0x000F0000) { + case (0x80000000 >> 12): + printf ("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000 >> 13): + printf ("Transfer error ack signal\n"); + break; + case (0x80000000 >> 14): + printf ("Data parity signal\n"); + break; + case (0x80000000 >> 15): + printf ("Address parity signal\n"); + break; + default: + printf ("Unknown values in msr\n"); + } + show_regs (regs); + print_backtrace ((unsigned long *) regs->gpr[1]); + panic ("machine check"); +} + +void AlignmentException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler + && (*debugger_exception_handler) (regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *) regs->gpr[1]); + panic ("Alignment Exception"); +} + +void ProgramCheckException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler + && (*debugger_exception_handler) (regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *) regs->gpr[1]); + panic ("Program Check Exception"); +} + +void SoftEmuException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler + && (*debugger_exception_handler) (regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *) regs->gpr[1]); + panic ("Software Emulation Exception"); +} + + +void UnknownException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler + && (*debugger_exception_handler) (regs)) + return; +#endif + printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception (0, regs); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint (struct pt_regs *); +#endif + +void DebugException (struct pt_regs *regs) +{ + + printf ("Debugger trap at @ %lx\n", regs->nip); + show_regs (regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint (regs); +#endif +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int addr_probe (uint * addr) +{ +#if 0 + int retval; + + __asm__ __volatile__ ("1: lwz %0,0(%1)\n" + " eieio\n" + " li %0,0\n" + "2:\n" + ".section .fixup,\"ax\"\n" + "3: li %0,-1\n" + " b 2b\n" + ".section __ex_table,\"a\"\n" + " .align 2\n" + " .long 1b,3b\n" + ".text":"=r" (retval):"r" (addr)); + + return (retval); +#endif + return 0; +} diff --git a/cpu/mpc8220/uart.c b/cpu/mpc8220/uart.c new file mode 100644 index 0000000..5f54aac --- /dev/null +++ b/cpu/mpc8220/uart.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2004, Freescale, Inc + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Minimal serial functions needed to use one of the PSC ports + * as serial console interface. + */ + +#include +#include + +#define PSC_BASE MMAP_PSC1 + +#if defined(CONFIG_PSC_CONSOLE) +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; + u32 counter; + + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ + psc->cr = 0; + psc->ipcr_acr = 0; + psc->isr_imr = 0; + + /* write to CSR: RX/TX baud rate from timers */ + psc->sr_csr = 0xdd000000; + + psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1; + + /* Setting up BaudRate */ + counter = ((gd->bus_clk / gd->baudrate)) >> 5; + counter++; + + /* write to CTUR: divide counter upper byte */ + psc->ctur = ((counter & 0xff00) << 16); + /* write to CTLR: divide counter lower byte */ + psc->ctlr = ((counter & 0x00ff) << 24); + + psc->cr = PSC_CR_RST_RX_CMD; + psc->cr = PSC_CR_RST_TX_CMD; + psc->cr = PSC_CR_RST_ERR_STS_CMD; + psc->cr = PSC_CR_RST_BRK_INT_CMD; + psc->cr = PSC_CR_RST_MR_PTR_CMD; + + psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE; + return (0); +} + +void serial_putc (const char c) +{ + volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; + + if (c == '\n') + serial_putc ('\r'); + + /* Wait for last character to go. */ + while (!(psc->sr_csr & PSC_SR_TXRDY)); + + psc->xmitbuf[0] = c; +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; + + /* Wait for a character to arrive. */ + while (!(psc->sr_csr & PSC_SR_RXRDY)); + return psc->xmitbuf[2]; +} + +int serial_tstc (void) +{ + volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; + + return (psc->sr_csr & PSC_SR_RXRDY); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; + u32 counter; + + counter = ((gd->bus_clk / gd->baudrate)) >> 5; + counter++; + + /* write to CTUR: divide counter upper byte */ + psc->ctur = ((counter & 0xff00) << 16); + /* write to CTLR: divide counter lower byte */ + psc->ctlr = ((counter & 0x00ff) << 24); + + psc->cr = PSC_CR_RST_RX_CMD; + psc->cr = PSC_CR_RST_TX_CMD; + + psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE; +} +#endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc824x/Makefile b/cpu/mpc824x/Makefile new file mode 100644 index 0000000..df0d64e --- /dev/null +++ b/cpu/mpc824x/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.S +OBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \ + drivers/epic/epic1.o drivers/i2c/i2c.o pci.o bedbug_603e.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +bedbug_603e.c: + ln -s ../mpc8260/bedbug_603e.c bedbug_603e.c + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk new file mode 100644 index 0000000..dac61d8 --- /dev/null +++ b/cpu/mpc824x/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing + +PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc824x/cpu.c b/cpu/mpc824x/cpu.c new file mode 100644 index 0000000..312dfe2 --- /dev/null +++ b/cpu/mpc824x/cpu.c @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2000 - 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +int checkcpu (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned int pvr = get_pvr (); + unsigned int version = pvr >> 16; + unsigned char revision; + ulong clock = gd->cpu_clk; + char buf[32]; + + puts ("CPU: "); + + switch (version) { + case CPU_TYPE_8240: + puts ("MPC8240"); + break; + + case CPU_TYPE_8245: + puts ("MPC8245"); + break; + + default: + return -1; /*not valid for this source */ + } + + CONFIG_READ_BYTE (REVID, revision); + + if (revision) { + printf (" Revision %d.%d", + (revision & 0xf0) >> 4, + (revision & 0x0f)); + } else { + return -1; /* no valid CPU revision info */ + } + + printf (" at %s MHz:", strmhz (buf, clock)); + + printf (" %u kB I-Cache", checkicache () >> 10); + printf (" %u kB D-Cache", checkdcache () >> 10); + + puts ("\n"); + + return 0; +} + +/* ------------------------------------------------------------------------- */ +/* L1 i-cache */ + +int checkicache (void) +{ + /*TODO*/ + return 128 * 4 * 32; +}; + +/* ------------------------------------------------------------------------- */ +/* L1 d-cache */ + +int checkdcache (void) +{ + /*TODO*/ + return 128 * 4 * 32; + +}; + +/*------------------------------------------------------------------- */ + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong msr, addr; + + /* Interrupts and MMU off */ + __asm__ ("mtspr 81, 0"); + + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~0x1030; + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* + * Trying to execute the next instruction at a non-existing address + * should cause a machine check, resulting in reset + */ +#ifdef CFG_RESET_ADDRESS + addr = CFG_RESET_ADDRESS; +#else + /* + * note: when CFG_MONITOR_BASE points to a RAM address, + * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid + * address. Better pick an address known to be invalid on + * your system and assign it to CFG_RESET_ADDRESS. + * "(ulong)-1" used to be a good choice for many systems... + */ + addr = CFG_MONITOR_BASE - sizeof (ulong); +#endif + ((void (*)(void)) addr) (); + return 1; + +} + +/* ------------------------------------------------------------------------- */ + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + * This is the sys_logic_clk (memory bus) divided by 4 + */ +unsigned long get_tbclk (void) +{ + return ((get_bus_freq (0) + 2L) / 4L); +} + +/* ------------------------------------------------------------------------- */ + +/* + * The MPC824x has an integrated PCI controller known as the MPC107. + * The following are MPC107 Bridge Controller and PCI Support functions + * + */ + +/* + * This procedure reads a 32-bit address MPC107 register, and returns + * a 32 bit value. It swaps the address to little endian before + * writing it to config address, and swaps the value to big endian + * before returning to the caller. + */ +unsigned int mpc824x_mpc107_getreg (unsigned int regNum) +{ + unsigned int temp; + + /* swap the addr. to little endian */ + *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum); + temp = *(volatile unsigned int *) CHRP_REG_DATA; + return PCISWAP (temp); /* swap the data upon return */ +} + +/* + * This procedure writes a 32-bit address MPC107 register. It swaps + * the address to little endian before writing it to config address. + */ + +void mpc824x_mpc107_setreg (unsigned int regNum, unsigned int regVal) +{ + /* swap the addr. to little endian */ + *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum); + *(volatile unsigned int *) CHRP_REG_DATA = PCISWAP (regVal); + return; +} + + +/* + * Write a byte (8 bits) to a memory location. + */ +void mpc824x_mpc107_write8 (unsigned int addr, unsigned char data) +{ + *(unsigned char *) addr = data; + __asm__ ("sync"); +} + +/* + * Write a word (16 bits) to a memory location after the value + * has been byte swapped (big to little endian or vice versa) + */ + +void mpc824x_mpc107_write16 (unsigned int address, unsigned short data) +{ + *(volatile unsigned short *) address = BYTE_SWAP_16_BIT (data); + __asm__ ("sync"); +} + +/* + * Write a long word (32 bits) to a memory location after the value + * has been byte swapped (big to little endian or vice versa) + */ + +void mpc824x_mpc107_write32 (unsigned int address, unsigned int data) +{ + *(volatile unsigned int *) address = LONGSWAP (data); + __asm__ ("sync"); +} + +/* + * Read a byte (8 bits) from a memory location. + */ +unsigned char mpc824x_mpc107_read8 (unsigned int addr) +{ + return *(volatile unsigned char *) addr; +} + + +/* + * Read a word (16 bits) from a memory location, and byte swap the + * value before returning to the caller. + */ +unsigned short mpc824x_mpc107_read16 (unsigned int address) +{ + unsigned short retVal; + + retVal = BYTE_SWAP_16_BIT (*(unsigned short *) address); + return retVal; +} + + +/* + * Read a long word (32 bits) from a memory location, and byte + * swap the value before returning to the caller. + */ +unsigned int mpc824x_mpc107_read32 (unsigned int address) +{ + unsigned int retVal; + + retVal = LONGSWAP (*(unsigned int *) address); + return (retVal); +} + + +/* + * Read a register in the Embedded Utilities Memory Block address + * space. + * Input: regNum - register number + utility base address. Example, + * the base address of EPIC is 0x40000, the register number + * being passed is 0x40000+the address of the target register. + * (See epic.h for register addresses). + * Output: The 32 bit little endian value of the register. + */ + +unsigned int mpc824x_eummbar_read (unsigned int regNum) +{ + unsigned int temp; + + temp = *(volatile unsigned int *) (EUMBBAR_VAL + regNum); + temp = PCISWAP (temp); + return temp; +} + + +/* + * Write a value to a register in the Embedded Utilities Memory + * Block address space. + * Input: regNum - register number + utility base address. Example, + * the base address of EPIC is 0x40000, the register + * number is 0x40000+the address of the target register. + * (See epic.h for register addresses). + * regVal - value to be written to the register. + */ + +void mpc824x_eummbar_write (unsigned int regNum, unsigned int regVal) +{ + *(volatile unsigned int *) (EUMBBAR_VAL + regNum) = PCISWAP (regVal); + return; +} + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c new file mode 100644 index 0000000..7871031 --- /dev/null +++ b/cpu/mpc824x/cpu_init.c @@ -0,0 +1,417 @@ +/* + * (C) Copyright 2000 + * Rob Taylor. Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifndef CFG_BANK0_ROW +#define CFG_BANK0_ROW 0 +#endif +#ifndef CFG_BANK1_ROW +#define CFG_BANK1_ROW 0 +#endif +#ifndef CFG_BANK2_ROW +#define CFG_BANK2_ROW 0 +#endif +#ifndef CFG_BANK3_ROW +#define CFG_BANK3_ROW 0 +#endif +#ifndef CFG_BANK4_ROW +#define CFG_BANK4_ROW 0 +#endif +#ifndef CFG_BANK5_ROW +#define CFG_BANK5_ROW 0 +#endif +#ifndef CFG_BANK6_ROW +#define CFG_BANK6_ROW 0 +#endif +#ifndef CFG_BANK7_ROW +#define CFG_BANK7_ROW 0 +#endif +#ifndef CFG_DBUS_SIZE2 +#define CFG_DBUS_SIZE2 0 +#endif + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + */ +void +cpu_init_f (void) +{ +/* MOUSSE board is initialized in asm */ +#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW) + register unsigned long val; + CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ +/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ + +#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62) +/* Why is this here, you ask? Try, just try setting 0x8000 + * in PCIACR with CONFIG_WRITE_HALFWORD() + * this one was a stumper, and we are annoyed + */ + +#define M_CONFIG_WRITE_HALFWORD( addr, data ) \ + __asm__ __volatile__(" \ + stw %2,0(%0)\n \ + sync\n \ + sth %3,2(%1)\n \ + sync\n \ + " \ + : /* no output */ \ + : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \ + "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \ + ); + + M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); +#endif + + CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ + CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */ + /* + * Note that although this bit is cleared after a hard reset, it + * must be explicitly set and then cleared by software during + * initialization in order to guarantee correct operation of the + * DLL and the SDRAM_CLK[0:3] signals (if they are used). + */ + CONFIG_READ_BYTE (AMBOR, val); + CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); + CONFIG_WRITE_BYTE(AMBOR, val | 0x20); + CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); +#ifdef CONFIG_MPC8245 + /* silicon bug 28 MPC8245 */ + CONFIG_READ_BYTE(AMBOR,val); + CONFIG_WRITE_BYTE(AMBOR,val|0x1); + +#if 0 + /* + * The following bug only affects older (XPC8245) processors. + * DMA transfers initiated by external devices get corrupted due + * to a hardware scheduling problem. + * + * The effect is: + * when transferring X words, the first 32 words are transferred + * OK, the next 3 x 32 words are 'old' data (from previous DMA) + * while the rest of the X words is xferred fine. + * + * Disabling 3 of the 4 32 word hardware buffers solves the problem + * with no significant performance loss. + */ + + CONFIG_READ_BYTE(PCMBCR,val); + /* in order not to corrupt data which is being read over the PCI bus + * with the PPC as slave, we need to reduce the number of PCMRBs to 1, + * 4.11 in the processor user manual + * */ + +#if 1 + CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */ +#else + CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */ + CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */ + /* default, 4 PCMRBs are used */ +#endif +#endif +#endif + + CONFIG_READ_WORD(PICR1, val); +#if defined(CONFIG_MPC8240) + CONFIG_WRITE_WORD( PICR1, + (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) | + PIRC1_MSK | PICR1_PROC_TYPE_603E | + PICR1_FLASH_WR_EN | PICR1_MCP_EN | + PICR1_CF_DPARK | PICR1_EN_PCS | + PICR1_CF_APARK ); +#elif defined(CONFIG_MPC8245) + CONFIG_WRITE_WORD( PICR1, + (val & (PICR1_RCS0)) | + PICR1_PROC_TYPE_603E | + PICR1_FLASH_WR_EN | PICR1_MCP_EN | + PICR1_CF_DPARK | PICR1_NO_BUSW_CK | + PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */ +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif + + CONFIG_READ_WORD(PICR2, val); + val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/ +#ifndef CONFIG_PN62 + val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/ +#endif + CONFIG_WRITE_WORD(PICR2, val); + + CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR); +#ifndef CFG_RAMBOOT + CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | + (CFG_BANK0_ROW) | + (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) | + (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) | + (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) | + (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) | + (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) | + (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) | + (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) | + (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)); +#endif + +#if defined(CFG_ASRISE) && defined(CFG_ASFALL) + CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT | + CFG_ASRISE << MCCR2_ASRISE_SHIFT | + CFG_ASFALL << MCCR2_ASFALL_SHIFT); +#else + CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT); +#endif + +#if defined(CONFIG_MPC8240) + CONFIG_WRITE_WORD(MCCR3, + (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | + (CFG_REFREC << MCCR3_REFREC_SHIFT) | + (CFG_RDLAT << MCCR3_RDLAT_SHIFT)); +#elif defined(CONFIG_MPC8245) + CONFIG_WRITE_WORD(MCCR3, + (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | + (CFG_REFREC << MCCR3_REFREC_SHIFT)); +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif + +/* this is gross. We think these should all be the same, and various boards + * should define CFG_ACTORW to 0 if they don't want to set it, or even, if + * its not set, we define it to zero in this file + */ +#if defined(CONFIG_CU824) || defined(CONFIG_PN62) + CONFIG_WRITE_WORD(MCCR4, + (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | + (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | + MCCR4_BIT21 | + (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | + ((CFG_BSTOPRE & 0x0003) <> 6) << MCCR4_BSTOPRE6TO9_SHIFT)); +#elif defined(CONFIG_MPC8240) + CONFIG_WRITE_WORD(MCCR4, + (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | + (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | + MCCR4_BIT21 | + (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | + ((CFG_BSTOPRE & 0x0003) <> 6) <> 6) <> MICR_ADDR_SHIFT) | + (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(EMSAR1, + ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(MSAR2, + ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(EMSAR2, + ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(MEAR1, + ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(EMEAR1, + ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(MEAR2, + ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(EMEAR2, + ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + + CONFIG_WRITE_BYTE(ODCR, CFG_ODCR); +#ifdef CFG_DLL_MAX_DELAY + CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY); /* needed to make DLL lock */ +#endif +#if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL) + CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL); +#endif +#if defined(MIOCR2) && defined(CFG_SDRAM_DSCD) + CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */ +#endif /* setup & hold time */ + + CONFIG_WRITE_BYTE(MBER, + CFG_BANK0_ENABLE | + (CFG_BANK1_ENABLE << 1) | + (CFG_BANK2_ENABLE << 2) | + (CFG_BANK3_ENABLE << 3) | + (CFG_BANK4_ENABLE << 4) | + (CFG_BANK5_ENABLE << 5) | + (CFG_BANK6_ENABLE << 6) | + (CFG_BANK7_ENABLE << 7)); + +#ifdef CFG_PGMAX + CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX); +#endif + + /* ! Wait 200us before initialize other registers */ + /*FIXME: write a decent udelay wait */ + __asm__ __volatile__( + " mtctr %0 \n \ + 0: bdnz 0b\n" + : + : "r" (0x10000)); + + CONFIG_READ_WORD(MCCR1, val); + CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */ + __asm__ __volatile__("eieio"); + +#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */ +} + + +#ifdef CONFIG_MOUSSE +#ifdef INCLUDE_MPC107_REPORT +struct MPC107_s { + unsigned int iobase; + char desc[120]; +} MPC107Regs[] = { + { BMC_BASE + 0x00, "MPC107 Vendor/Device ID" }, + { BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" }, + { BMC_BASE + 0x08, "MPC107 Revision" }, + { BMC_BASE + 0x0C, "MPC107 Cache Line Size" }, + { BMC_BASE + 0x10, "MPC107 LMBAR" }, + { BMC_BASE + 0x14, "MPC824x PCSR" }, + { BMC_BASE + 0xA8, "MPC824x PICR1" }, + { BMC_BASE + 0xAC, "MPC824x PICR2" }, + { BMC_BASE + 0x46, "MPC824x PACR" }, + { BMC_BASE + 0x310, "MPC824x ITWR" }, + { BMC_BASE + 0x300, "MPC824x OMBAR" }, + { BMC_BASE + 0x308, "MPC824x OTWR" }, + { BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" }, + { BMC_BASE + 0x78, "MPC107 EUMBAR" }, + { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" }, + { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" }, + { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" }, + { BMC_BASE + 0xE0, "MPC107 AMBOR Register" }, + { BMC_BASE + 0xF0, "MPC107 MCCR1 Register" }, + { BMC_BASE + 0xF4, "MPC107 MCCR2 Register" }, + { BMC_BASE + 0xF8, "MPC107 MCCR3 Register" }, + { BMC_BASE + 0xFC, "MPC107 MCCR4 Register" }, +}; +#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0])) +#endif /* INCLUDE_MPC107_REPORT */ +#endif /* CONFIG_MOUSSE */ + +/* + * initialize higher level parts of CPU like time base and timers + */ +int cpu_init_r (void) +{ +#ifdef CONFIG_MOUSSE +#ifdef INCLUDE_MPC107_REPORT + unsigned int tmp = 0, i; +#endif + /* + * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg). + * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can + * be accessed. + */ + +#ifdef CONFIG_MPC8240 /* only on MPC8240 */ + mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL); + /* MOT/SPS: Issue #10002, PCI (FD Alias enable) */ + mpc824x_mpc107_setreg (AMBOR, 0x000000C0); +#endif + + +#ifdef INCLUDE_MPC107_REPORT + /* Check MPC824x PCI Device and Vendor ID */ + while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) { + printf (" MPC107: offset=0x%x, val = 0x%x\n", + BMC_BASE, + tmp); + } + + for (i = 0; i < N_MPC107_Regs; i++) { + printf (" 0x%x/%s = 0x%x\n", + MPC107Regs[i].iobase, + MPC107Regs[i].desc, + mpc824x_mpc107_getreg (MPC107Regs[i].iobase)); + } + + printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L)); + printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U)); + printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L)); + printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U)); + printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L)); + printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U)); + printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L)); + printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U)); + printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L)); + printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U)); + printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L)); + printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U)); + printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L)); + printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U)); + printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L)); + printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U)); +#endif /* INCLUDE_MPC107_REPORT */ +#endif /* CONFIG_MOUSSE */ + return (0); +} diff --git a/cpu/mpc824x/drivers/dma/Makefile b/cpu/mpc824x/drivers/dma/Makefile new file mode 100644 index 0000000..59e2fac --- /dev/null +++ b/cpu/mpc824x/drivers/dma/Makefile @@ -0,0 +1,83 @@ +########################################################################## +# +# Copyright Motorola, Inc. 1997 +# ALL RIGHTS RESERVED +# +# You are hereby granted a copyright license to use, modify, and +# distribute the SOFTWARE so long as this entire notice is retained +# without alteration in any modified and/or redistributed versions, +# and that such modified versions are clearly identified as such. +# No licenses are granted by implication, estoppel or otherwise under +# any patents or trademarks of Motorola, Inc. +# +# The SOFTWARE is provided on an "AS IS" basis and without warranty. +# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS +# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR +# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH +# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS +# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. +# +# To the maximum extent permitted by applicable law, IN NO EVENT SHALL +# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF +# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR +# INABILITY TO USE THE SOFTWARE. +# +############################################################################ +TARGET = libdma.a + +DEBUG = -DDMADBG +LST = -Hanno -S +OPTIM = +CC = /risc/tools/pkgs/metaware/bin/hcppc +CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc +CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) +PREP = $(CC) $(CFLAGS) -P + +# Assembler used to build the .s files (for the board version) + +ASOPT = -big_si -c +ASDEBUG = -l -fm +AS = /risc/tools/pkgs/metaware/bin/asppc + +# Linker to bring .o files together into an executable. + +LKOPT = -Bbase=0 -q -r -Qn +LKCMD = +LINK = /risc/tools/pkgs/metaware/bin/ldppc $(LKCMD) $(LKOPT) + +# DOS Utilities + +DEL = rm +COPY = cp +LIST = ls + +OBJECTS = dma1.o dma2.o + +all: $(TARGET) + +$(TARGET): $(OBJECTS) + $(LINK) $(OBJECTS) -o $@ + +objects: dma1.o + +clean: + $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) + +.s.o: + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i +# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst + +.c.o: + $(CCobj) $< + +.c.s: + $(CCobj) $(LST) $< + +dma1.o: dma_export.h dma.h dma1.c + +dma2.o: dma.h dma2.s diff --git a/cpu/mpc824x/drivers/dma/Makefile_pc b/cpu/mpc824x/drivers/dma/Makefile_pc new file mode 100644 index 0000000..8df2a3c --- /dev/null +++ b/cpu/mpc824x/drivers/dma/Makefile_pc @@ -0,0 +1,89 @@ +########################################################################## +# +# makefile_pc for use with mksnt tools drivers/dma +# +# Copyright Motorola, Inc. 1997 +# ALL RIGHTS RESERVED +# +# You are hereby granted a copyright license to use, modify, and +# distribute the SOFTWARE so long as this entire notice is retained +# without alteration in any modified and/or redistributed versions, +# and that such modified versions are clearly identified as such. +# No licenses are granted by implication, estoppel or otherwise under +# any patents or trademarks of Motorola, Inc. +# +# The SOFTWARE is provided on an "AS IS" basis and without warranty. +# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS +# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR +# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH +# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS +# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. +# +# To the maximum extent permitted by applicable law, IN NO EVENT SHALL +# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF +# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR +# INABILITY TO USE THE SOFTWARE. +# +############################################################################ +TARGET = libdma.a + +DEBUG = -DDMADBG +LST = -Hanno -S +OPTIM = +CC = m:/old_tools/tools/hcppc/bin/hcppc +CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc +CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) +PREP = $(CC) $(CFLAGS) -P + +# Assembler used to build the .s files (for the board version) + +ASOPT = -big_si -c +ASDEBUG = -l -fm +AS = m:/old_tools/tools/hcppc/bin/asppc + +# Linker to bring .o files together into an executable. + +LKOPT = -Bbase=0 -q -r -Qn +LKCMD = +LINK = m:/old_tools/tools/hcppc/bin/ldppc $(LKCMD) $(LKOPT) + +# DOS Utilities + +DEL = rm +COPY = cp +LIST = ls + +OBJECTS = dma1.o dma2.o + +all: $(TARGET) + +$(TARGET): $(OBJECTS) + $(LINK) $(OBJECTS) -o $@ + +objects: dma1.o + +clean: + $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) + +.s.o: + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i +# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst + +.c.o: + $(CCobj) $< + +.c.s: + $(CCobj) $(LST) $< + +dma1.o: dma_export.h dma.h dma1.c + $(CCobj) $< + +dma2.o: dma.h dma2.s + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i diff --git a/cpu/mpc824x/drivers/dma/README b/cpu/mpc824x/drivers/dma/README new file mode 100644 index 0000000..06f4bc0 --- /dev/null +++ b/cpu/mpc824x/drivers/dma/README @@ -0,0 +1,100 @@ +CONTENT: + + dma.h + dma1.c + dma2.s + +WHAT ARE THESE FILES: + +These files contain MPC8240 (Kahlua) DMA controller +driver routines. The driver routines are not +written for any specific operating system. +They serves the purpose of code sample, and +jump-start for using the MPC8240 DMA controller. + +For the reason of correctness of C language +syntax, these files are compiled by Metaware +C compiler and assembler. + +ENDIAN NOTATION: + +The algorithm is designed for big-endian mode, +software is responsible for byte swapping. + +USAGE: + +1. The host system that is running on MPC8240 + or using MPC8240 as I/O device shall link + the files listed here. The memory location + of driver routines shall take into account of + that driver routines need to run in supervisor + mode and they process DMA controller interrupt. + +2. The host system is responsible for configuring + the MPC8240 including Embedded Utilities Memory + Block. Since the DMA controller on MPC8240 can + be accessed by either local 603e core or the host + that MPC8240 serves as I/O processor through host + PCI configuration, it is important that the local + processor uses EUMBBAR to access its local DMA + controller while the PCI master uses I/O + processor's PCSRBAR to access the DMA controller + on I/O device. + + To qualify whether is EUMBBAR or PCSRBAR, one + additional parameter is requied from the host + system, LOCAL or REMOTE so that the base value + can be correctly interpreted. + +3. If the host system is also using the EPIC unit + on MPC8240, the system can register the + DMA_ISR with the EPIC including other + desired resources. + + If the host system does not using the EPIC unit + on MPC8240, DMA_ISR function can be called for + each desired time interval. + + In both cases, the host system is free to + provide its own interrupt service routine. + +4. To start a direct mode DMA transaction, + use DMA_Bld_Curr with the start parameter + set to 1. + + To start a chaining mode DMA transaction, + the application shall build descriptors + in memory first, next, use DMA_Bld_Desp + with the start parameter set to 1. + +5. DMA_Start function clears, then sets the CS + bit of DMA mode register. + + DMA_Halt function clears the CS bit of DMA + mode register. + + These functions can be used to start and + halt the DMA transaction. + + If the chaining descriptors has been + modified since the last time a DMA + transaction started, use DMA_Chn_Cnt + function to let DMA controller process + the modified descriptor chain without + stopping or disturbing the current DMA + transaction. + + It is the host system's responsibility of + setting up the correct DMA transfer mode + and pass the correct memory address parameters. + +6. It is the host system's responsibility of + queueing the DMA I/O request. The host + system can call the DMA_ISR with its own + desired interrupt service subroutines to + handle each individual interrupt and queued + DMA I/O requests. + +7. The DMA driver routines contains a set + of utilities, Set and Get, for host system + to query and modify the desired DMA registers. diff --git a/cpu/mpc824x/drivers/dma/dma.h b/cpu/mpc824x/drivers/dma/dma.h new file mode 100644 index 0000000..a21be74 --- /dev/null +++ b/cpu/mpc824x/drivers/dma/dma.h @@ -0,0 +1,326 @@ +#ifndef DMA_H +#define DMA_H +/******************************************************* + * + * copyright @ Motorola 1999 + * + *******************************************************/ +#define NUM_DMA_REG 7 +#define DMA_MR_REG 0 +#define DMA_SR_REG 1 +#define DMA_CDAR_REG 2 +#define DMA_SAR_REG 3 +#define DMA_DAR_REG 4 +#define DMA_BCR_REG 5 +#define DMA_NDAR_REG 6 + +typedef enum _dmastatus +{ + DMASUCCESS = 0x1000, + DMALMERROR, + DMAPERROR, + DMACHNBUSY, + DMAEOSINT, + DMAEOCAINT, + DMAINVALID, + DMANOEVENT, +} DMAStatus; + +typedef enum _location +{ + LOCAL = 0, /* local processor accesses on board DMA, + local processor's eumbbar is required */ + REMOTE = 1, /* PCI master accesses DMA on I/O board, + I/O processor's pcsrbar is required */ +} LOCATION; + +typedef enum dma_mr_bit +{ + IRQS = 0x00080000, + PDE = 0x00040000, + DAHTS = 0x00030000, + SAHTS = 0x0000c000, + DAHE = 0x00002000, + SAHE = 0x00001000, + PRC = 0x00000c00, + EIE = 0x00000080, + EOTIE = 0x00000040, + DL = 0x00000008, + CTM = 0x00000004, + CC = 0x00000002, + CS = 0x00000001, +} DMA_MR_BIT; + +typedef enum dma_sr_bit +{ + LME = 0x00000080, + PE = 0x00000010, + CB = 0x00000004, + EOSI = 0x00000002, + EOCAI = 0x00000001, +} DMA_SR_BIT; + +/* structure for DMA Mode Register */ +typedef struct _dma_mr +{ + unsigned int reserved0 : 12; + unsigned int irqs : 1; + unsigned int pde : 1; + unsigned int dahts : 2; + unsigned int sahts : 2; + unsigned int dahe : 1; + unsigned int sahe : 1; + unsigned int prc : 2; + unsigned int reserved1 : 1; + unsigned int eie : 1; + unsigned int eotie : 1; + unsigned int reserved2 : 3; + unsigned int dl : 1; + unsigned int ctm : 1; + /* if chaining mode is enabled, any time, user can modify the + * descriptor and does not need to halt the current DMA transaction. + * Set CC bit, enable DMA to process the modified descriptors + * Hardware will clear this bit each time, DMA starts. + */ + unsigned int cc : 1; + /* cs bit has dua role, halt the current DMA transaction and + * (re)start DMA transaction. In chaining mode, if the descriptor + * needs modification, cs bit shall be used not the cc bit. + * Hardware will not set/clear this bit each time DMA transaction + * stops or starts. Software shall do it. + * + * cs bit shall not be used to halt chaining DMA transaction for + * modifying the descriptor. That is the role of CC bit. + */ + unsigned int cs : 1; +} DMA_MR; + +/* structure for DMA Status register */ +typedef struct _dma_sr +{ + unsigned int reserved0 : 24; + unsigned int lme : 1; + unsigned int reserved1 : 2; + unsigned int pe : 1; + unsigned int reserved2 : 1; + unsigned int cb : 1; + unsigned int eosi : 1; + unsigned int eocai : 1; +} DMA_SR; + +/* structure for DMA current descriptor address register */ +typedef struct _dma_cdar +{ + unsigned int cda : 27; + unsigned int snen : 1; + unsigned int eosie : 1; + unsigned int ctt : 2; + unsigned int eotd : 1; +} DMA_CDAR; + +/* structure for DMA byte count register */ +typedef struct _dma_bcr +{ + unsigned int reserved : 6; + unsigned int bcr : 26; +} DMA_BCR; + +/* structure for DMA Next Descriptor Address register */ +typedef struct _dma_ndar +{ + unsigned int nda : 27; + unsigned int ndsnen : 1; + unsigned int ndeosie: 1; + unsigned int ndctt : 2; + unsigned int eotd : 1; +} DMA_NDAR; + +/* structure for DMA current transaction info */ +typedef struct _dma_curr +{ + unsigned int src_addr; + unsigned int dest_addr; + unsigned int byte_cnt; +} DMA_CURR; + +/************************* Kernel API******************** + * Kernel APIs are used to interface with O.S. kernel. + * They are the functions required by O.S. kernel to + * provide I/O service. + ********************************************************/ + +/**************DMA Device Control Functions ********/ + +/** + * Note: + * + * In all following functions, the host (KAHLUA) processor has a + * choice of accessing on board local DMA (LOCAL), + * or DMA on a distributed KAHLUA (REMOTE). In either case, + * the caller shall pass the configured embedded utility memory + * block base address relative to the DMA. If LOCAL DMA is used, + * this parameter shall be EUMBBAR, if REMOTE is used, the + * parameter shall be the corresponding PCSRBAR. + **/ + +/************************************************************** + * function: DMA_Get_Stat + * + * description: return the content of status register of + * the given DMA channel + * if error, return DMAINVALID. Otherwise return + * DMASUCCESS. + * + **************************************************************/ +static DMAStatus DMA_Get_Stat( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_SR * ); + +/************************************************************** + * function: DMA_Get_Mode + * + * description: return the content of mode register of the + * given DMA channel + * if error, return DMAINVALID. Otherwise return DMASUCCESS. + * + **************************************************************/ +static DMAStatus DMA_Get_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR * ); + +/************************************************************** + * function: DMA_Set_Mode + * + * description: Set a new mode to a given DMA channel + * return DMASUCCESS if success, otherwise return DMACHNINVALID + * + * note: It is not a good idea of changing the DMA mode during + * the middle of a transaction. + **************************************************************/ +static DMAStatus DMA_Set_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR mode ); + +/************************************************************* + * function: DMA_ISR + * + * description: DMA interrupt service routine + * return DMAStatus based on the status + * + *************************************************************/ +static DMAStatus DMA_ISR( unsigned int eumbbar, + unsigned int channel, + DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus )); + +static DMAStatus dma_error_func( unsigned int, unsigned int, DMAStatus ); + +/********************* DMA I/O function ********************/ + +/************************************************************ + * function: DMA_Start + * + * description: start a given DMA channel transaction + * return DMASUCCESS if success, otherwise return DMACHNINVALID + * + * note: this function will clear DMA_MR(CC) first, then + * set DMA_MR(CC). + ***********************************************************/ +static DMAStatus DMA_Start( LOCATION, unsigned int eumbbar,unsigned int channel ); + +/*********************************************************** + * function: DMA_Halt + * + * description: halt the current dma transaction on the specified + * channel. + * return DMASUCCESS if success, otherwise return DMACHNINVALID + * + * note: if the specified DMA channel is idle, nothing happens + *************************************************************/ +static DMAStatus DMA_Halt( LOCATION, unsigned int eumbbar,unsigned int channel ); + +/************************************************************* + * function: DMA_Chn_Cnt + * + * description: set the DMA_MR(CC) bit for a given channel + * that is in chaining mode. + * return DMASUCCESS if successfule, otherwise return DMACHNINVALID + * + * note: if the given channel is not in chaining mode, nothing + * happen. + * + *************************************************************/ +static DMAStatus DMA_Chn_Cnt( LOCATION, unsigned int eumbbar,unsigned int channel ); + +/*********************** App. API *************************** + * App. API are the APIs Kernel provides for the application + * level program + ************************************************************/ +/************************************************************** + * function: DMA_Bld_Curr + * + * description: set current src, dest, byte count registers + * according to the desp for a given channel + * + * if the given channel is busy, no change made, + * return DMACHNBUSY. + * + * otherwise return DMASUCCESS. + * + * note: + **************************************************************/ +static DMAStatus DMA_Bld_Curr( LOCATION, + unsigned int eumbbar, + unsigned int channel, + DMA_CURR desp ); + +/************************************************************** + * function: DMA_Poke_Curr + * + * description: poke the current src, dest, byte count registers + * for a given channel. + * + * return DMASUCCESS if no error otherwise return DMACHNERROR + * + * note: Due to the undeterministic parallelism, in chaining + * mode, the value returned by this function shall + * be taken as reference when the query is made rather + * than the absolute snapshot when the value is returned. + **************************************************************/ +static DMAStatus DMA_Poke_Curr( LOCATION, + unsigned int eumbbar, + unsigned int channel, + DMA_CURR* desp ); + +/************************************************************** + * function: DMA_Bld_Desp + * + * description: set current descriptor address register + * according to the desp for a given channel + * + * if the given channel is busy return DMACHNBUSY + * and no change made, otherwise return DMASUCCESS. + * + * note: + **************************************************************/ +static DMAStatus DMA_Bld_Desp( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CDAR desp ); + +/************************************************************** + * function: DMA_Poke_Desp + * + * description: poke the current descriptor address register + * for a given channel + * + * return DMASUCCESS if no error otherwise return + * DMAINVALID + * + * note: Due to the undeterministic parallellism of DMA operation, + * the value returned by this function shall be taken as + * the most recently used descriptor when the last time + * DMA starts a chaining mode operation. + **************************************************************/ +static DMAStatus DMA_Poke_Desp( LOCATION, + unsigned int eumbbar, + unsigned int channel, + DMA_CDAR *desp ); + +#endif diff --git a/cpu/mpc824x/drivers/dma/dma1.c b/cpu/mpc824x/drivers/dma/dma1.c new file mode 100644 index 0000000..9c85267 --- /dev/null +++ b/cpu/mpc824x/drivers/dma/dma1.c @@ -0,0 +1,801 @@ +/************************************************************ + * + * copyright @ Motorola, 1999 + * + * App. API + * + * App. API are the APIs Kernel provides for the application + * level program + * + ************************************************************/ +#include "dma_export.h" +#include "dma.h" + +/* Define a macro to use an optional application-layer print function, if + * one was passed to the library during initialization. If there was no + * function pointer passed, this protects against referencing a NULL pointer. + * Also define The global variable that holds the passed pointer. + */ +#define PRINT if ( app_print ) app_print +static int (*app_print)(char *,...); + +/* Set by call to get_eumbbar during DMA_Initialize. + * This could be globally available to the library, but there is + * an advantage to passing it as a parameter: it is already in a register + * and doesn't have to be loaded from memory. Also, that is the way the + * library was already implemented and I don't want to change it without + * a more detailed analysis. + * It is being set as a global variable during initialization to hide it from + * the DINK application layer, because it is Kahlua-specific. I think that + * get_eumbbar, load_runtime_reg, and store_runtime_reg should be defined in + * a Kahlua-specific library dealing with the embedded utilities memory block. + * Right now, get_eumbbar is defined in dink32/kahlua.s. The other two are + * defined in dink32/drivers/i2c/i2c2.s, drivers/dma/dma2.s, etc. + */ +static unsigned int Global_eumbbar = 0; +extern unsigned int get_eumbbar(); + + +extern unsigned int load_runtime_reg( unsigned int eumbbar, unsigned int reg ); +#pragma Alias( load_runtime_reg, "load_runtime_reg" ); + +extern void store_runtime_reg( unsigned int eumbbar, unsigned int reg, unsigned int val ); +#pragma Alias( store_runtime_reg, "store_runtime_reg" ); + +unsigned int dma_reg_tb[][14] = { + /* local DMA registers */ + { + /* DMA_0_MR */ 0x00001100, + /* DMA_0_SR */ 0x00001104, + /* DMA_0_CDAR */ 0x00001108, + /* DMA_0_SAR */ 0x00001110, + /* DMA_0_DAR */ 0x00001118, + /* DMA_0_BCR */ 0x00001120, + /* DMA_0_NDAR */ 0x00001124, + /* DMA_1_MR */ 0x00001200, + /* DMA_1_SR */ 0x00001204, + /* DMA_1_CDAR */ 0x00001208, + /* DMA_1_SAR */ 0x00001210, + /* DMA_1_DAR */ 0x00001218, + /* DMA_1_BCR */ 0x00001220, + /* DMA_1_NDAR */ 0x00001224, + }, + /* remote DMA registers */ + { + /* DMA_0_MR */ 0x00000100, + /* DMA_0_SR */ 0x00000104, + /* DMA_0_CDAR */ 0x00000108, + /* DMA_0_SAR */ 0x00000110, + /* DMA_0_DAR */ 0x00000118, + /* DMA_0_BCR */ 0x00000120, + /* DMA_0_NDAR */ 0x00000124, + /* DMA_1_MR */ 0x00000200, + /* DMA_1_SR */ 0x00000204, + /* DMA_1_CDAR */ 0x00000208, + /* DMA_1_SAR */ 0x00000210, + /* DMA_1_DAR */ 0x00000218, + /* DMA_1_BCR */ 0x00000220, + /* DMA_1_NDAR */ 0x00000224, + }, +}; + +/* API functions */ + +/* Initialize DMA unit with the following: + * optional pointer to application layer print function + * + * These parameters may be added: + * ??? + * Interrupt enables, modes, etc. are set for each transfer. + * + * This function must be called before DMA unit can be used. + */ +extern +DMA_Status DMA_Initialize( int (*p)(char *,...)) +{ + DMAStatus status; + /* establish the pointer, if there is one, to the application's "printf" */ + app_print = p; + + /* If this is the first call, get the embedded utilities memory block + * base address. I'm not sure what to do about error handling here: + * if a non-zero value is returned, accept it. + */ + if ( Global_eumbbar == 0) + Global_eumbbar = get_eumbbar(); + if ( Global_eumbbar == 0) + { + PRINT( "DMA_Initialize: can't find EUMBBAR\n" ); + return DMA_ERROR; + } + + return DMA_SUCCESS; +} + + +/* Perform the DMA transfer, only direct mode is currently implemented. + * At this point, I think it would be better to define a different + * function for chaining mode. + * Also, I'm not sure if it is appropriate to have the "generic" API + * accept snoop and int_steer parameters. The DINK user interface allows + * them, so for now I'll leave them. + * + * int_steer controls DMA interrupt steering to PCI or local processor + * type is the type of transfer: M2M, M2P, P2M, P2P + * source is the source address of the data + * dest is the destination address of the data + * len is the length of data to transfer + * channel is the DMA channel to use for the transfer + * snoop is the snoop enable control + */ +extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer, + DMA_TRANSFER_TYPE type, + unsigned int source, + unsigned int dest, + unsigned int len, + DMA_CHANNEL channel, + DMA_SNOOP_MODE snoop) +{ + DMA_MR md; + DMA_CDAR cdar; + /* it's inappropriate for curr to be a struct, but I'll leave it */ + DMA_CURR curr; + + DMAStatus stat; + + /* The rest of this code was moved from device.c test_dma to here. + * It needs to be cleaned up and validated, but at least it is removed + * from the application and API. Most of the mode is left hard coded. + * This should be changed after the final API is defined and the user + * application has a way to control the transfer. + * + */ + + if ( DMA_Get_Mode( LOCAL, Global_eumbbar, channel, &md ) != DMASUCCESS ) + { + return DMA_ERROR; + } + + md.irqs = int_steer; + md.pde = 0; + md.dahts = 3; /* 8 - byte */ + md.sahts = 3; /* 8 - byte */ + md.dahe = 0; + md.sahe = 0; + md.prc = 0; + /* if steering interrupts to local processor, use polling mode */ + if ( int_steer == DMA_INT_STEER_PCI ) + { + md.eie = 1; + md.eotie = 1; + } else { + md.eie = 0; + md.eotie = 0; + } + md.dl = 0; + md.ctm = 1; /* direct mode */ + md.cc = 0; + + /* validate the length range */ + if (len > 0x3ffffff ) + { + PRINT( "dev DMA: length of transfer too large: %d\n", len ); + return DMA_ERROR; + } + + /* inappropriate to use a struct, but leave as is for now */ + curr.src_addr = source; + curr.dest_addr = dest; + curr.byte_cnt = len; + + (void)DMA_Poke_Desp( LOCAL, Global_eumbbar, channel, &cdar ); + cdar.snen = snoop; + cdar.ctt = type; + + if ( ( stat = DMA_Bld_Desp( LOCAL, Global_eumbbar, channel, cdar )) + != DMASUCCESS || + ( stat = DMA_Bld_Curr( LOCAL, Global_eumbbar, channel, curr )) + != DMASUCCESS || + ( stat = DMA_Set_Mode( LOCAL, Global_eumbbar, channel, md )) + != DMASUCCESS || + ( stat = DMA_Start( LOCAL, Global_eumbbar, channel )) + != DMASUCCESS ) + { + if ( stat == DMACHNBUSY ) + { + PRINT( "dev DMA: channel %d busy.\n", channel ); + } + else + { + PRINT( "dev DMA: invalid channel request.\n", channel ); + } + + return DMA_ERROR; + } + +/* Since we are interested at the DMA performace right now, + we are going to do as less as possible to burden the + 603e core. + + if you have epic enabled or don't care the return from + DMA operation, you can just return SUCCESS. + + if you don't have epic enabled and care the DMA result, + you can use the polling method below. + + Note: I'll attempt to activate the code for handling polling. + */ + +#if 0 + /* if steering interrupt to local processor, let it handle results */ + if ( int_steer == DMA_INT_STEER_LOCAL ) + { + return DMA_SUCCESS; + } + + /* polling since interrupt goes to PCI */ + do + { + stat = DMA_ISR( Global_eumbbar, channel, dma_error_func, + dma_error_func, dma_error_func, dma_error_func ); + } + while ( stat == DMANOEVENT ); +#endif + + return DMA_SUCCESS; +} + +/* DMA library internal functions */ + +/** + * Note: + * + * In all following functions, the host (KAHLUA) processor has a + * choice of accessing on board local DMA (LOCAL), + * or DMA on a distributed KAHLUA (REMOTE). In either case, + * the caller shall pass the configured embedded utility memory + * block base address relative to the DMA. If LOCAL DMA is used, + * this parameter shall be EUMBBAR, if REMOTE is used, the + * parameter shall be the corresponding PCSRBAR. + **/ + +/************************************************************** + * function: DMA_Get_Stat + * + * description: return the content of status register of + * the given DMA channel + * + * if error, reserved0 field all 1s. + **************************************************************/ +static +DMAStatus DMA_Get_Stat( LOCATION host, unsigned int eumbbar, unsigned int channel, DMA_SR *stat ) +{ + unsigned int tmp; + + if ( channel != 0 && channel != 1 || stat == 0 ) + { + return DMAINVALID; + } + + tmp = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SR_REG] ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) stat = 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SR_REG], tmp ); +#endif + + stat->reserved0 = ( tmp & 0xffffff00 ) >> 8; + stat->lme = ( tmp & 0x00000080 ) >> 7; + stat->reserved1 = ( tmp & 0x00000060 ) >> 5; + stat->pe = ( tmp & 0x00000010 ) >> 4; + stat->reserved2 = ( tmp & 0x00000008 ) >> 3; + stat->cb = ( tmp & 0x00000004 ) >> 2; + stat->eosi = ( tmp & 0x00000002 ) >> 1; + stat->eocai = ( tmp & 0x00000001 ); + + return DMASUCCESS; +} + +/************************************************************** + * function: DMA_Get_Mode + * + * description: return the content of mode register of the + * given DMA channel + * + * if error, return DMAINVALID, otherwise return + * DMASUCCESS + **************************************************************/ +static +DMAStatus DMA_Get_Mode( LOCATION host, unsigned eumbbar, unsigned int channel, DMA_MR *mode ) +{ + unsigned int tmp; + if ( channel != 0 && channel != 1 || mode == 0 ) + { + return DMAINVALID; + } + + tmp = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_MR_REG] ); + +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) mode = 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_MR_REG], tmp ); +#endif + + mode->reserved0 = (tmp & 0xfff00000) >> 20; + mode->irqs = (tmp & 0x00080000) >> 19; + mode->pde = (tmp & 0x00040000) >> 18; + mode->dahts = (tmp & 0x00030000) >> 16; + mode->sahts = (tmp & 0x0000c000) >> 14; + mode->dahe = (tmp & 0x00002000) >> 13; + mode->sahe = (tmp & 0x00001000) >> 12; + mode->prc = (tmp & 0x00000c00) >> 10; + mode->reserved1 = (tmp & 0x00000200) >> 9; + mode->eie = (tmp & 0x00000100) >> 8; + mode->eotie = (tmp & 0x00000080) >> 7; + mode->reserved2 = (tmp & 0x00000070) >> 4; + mode->dl = (tmp & 0x00000008) >> 3; + mode->ctm = (tmp & 0x00000004) >> 2; + mode->cc = (tmp & 0x00000002) >> 1; + mode->cs = (tmp & 0x00000001); + + return DMASUCCESS; +} + +/************************************************************** + * function: DMA_Set_Mode + * + * description: Set a new mode to a given DMA channel + * + * note: It is not a good idea of changing the DMA mode during + * the middle of a transaction. + **************************************************************/ +static +DMAStatus DMA_Set_Mode( LOCATION host, unsigned eumbbar, unsigned int channel, DMA_MR mode ) +{ + unsigned int tmp; + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + tmp = ( mode.reserved0 & 0xfff ) << 20; + tmp |= ( ( mode.irqs & 0x1 ) << 19); + tmp |= ( ( mode.pde & 0x1 ) << 18 ); + tmp |= ( ( mode.dahts & 0x3 ) << 16 ); + tmp |= ( ( mode.sahts & 0x3 ) << 14 ); + tmp |= ( ( mode.dahe & 0x1 ) << 13 ); + tmp |= ( ( mode.sahe & 0x1 ) << 12 ); + tmp |= ( ( mode.prc & 0x3 ) << 10 ); + tmp |= ( ( mode.reserved1 & 0x1 ) << 9 ); + tmp |= ( ( mode.eie & 0x1 ) << 8 ); + tmp |= ( ( mode.eotie & 0x1 ) << 7 ); + tmp |= ( ( mode.reserved2 & 0x7 ) << 4 ); + tmp |= ( ( mode.dl & 0x1 ) << 3 ); + tmp |= ( ( mode.ctm & 0x1 ) << 2 ); + tmp |= ( ( mode.cc & 0x1 ) << 1 ) ; + tmp |= ( mode.cs & 0x1 ); + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], tmp ); + return DMASUCCESS; +} + +/************************************************************ + * function: DMA_Start + * + * description: start a given DMA channel transaction + * return DMASUCCESS if success otherwise return + * DMAStatus value + * + * note: this function will clear DMA_MR(CC) first, then + * set DMA_MR(CC). + ***********************************************************/ +static +DMAStatus DMA_Start( LOCATION host, unsigned int eumbbar, unsigned int channel ) +{ + DMA_SR stat; + unsigned int mode; + + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + if ( DMA_Get_Stat( host, eumbbar, channel, &stat ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( stat.cb == 1 ) + { + /* DMA is not free */ + return DMACHNBUSY; + } + + mode = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG] ); + /* clear DMA_MR(CS) */ + mode &= 0xfffffffe; + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode ); + + /* set DMA_MR(CS) */ + mode |= CS; + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode ); + return DMASUCCESS; +} + +/*********************************************************** + * function: DMA_Halt + * + * description: halt the current dma transaction on the specified + * channel. + * return DMASUCCESS if success otherwise return DMAINVALID + * + * note: if the specified DMA channel is idle, nothing happens + *************************************************************/ +static +DMAStatus DMA_Halt( LOCATION host, unsigned int eumbbar, unsigned int channel ) +{ + unsigned int mode; + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + mode = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG]); + + /* clear DMA_MR(CS) */ + mode &= 0xfffffffe; + store_runtime_reg(eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode ); + return DMASUCCESS; +} + +/************************************************************* + * function: DMA_Chn_Cnt + * + * description: set the DMA_MR(CC) bit for a given channel + * that is in chaining mode. + * return DMASUCCESS if successfule, otherwise return + * DMAINVALID. + * + * note: if the given channel is not in chaining mode, nothing + * happen. + * + *************************************************************/ +static +DMAStatus DMA_Chn_Cnt( LOCATION host, unsigned int eumbbar, unsigned int channel ) +{ + DMA_MR mode; + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + if ( DMA_Get_Mode( host, eumbbar, channel, &mode ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( mode.ctm == 0 ) + { + /* either illegal mode or not chaining mode */ + return DMAINVALID; + } + + mode.cc = 1; + return DMA_Set_Mode( host, eumbbar, channel, mode ); +} + +/************************************************************** + * function: DMA_Bld_Desp + * + * description: set current descriptor address register + * according to the desp for a given channel + * + * if the given channel is busy return DMACHNBUSY + * and no change made, otherwise return DMASUCCESS. + * + * note: + **************************************************************/ +static +DMAStatus DMA_Bld_Desp( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CDAR desp ) +{ + DMA_SR status; + unsigned int temp; + + if ( channel != 0 && channel != 1 ) + { + /* channel number out of range */ + return DMAINVALID; + } + + if ( DMA_Get_Stat( host, eumbbar, channel, &status ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( status.cb == 1 ) + { + /* channel busy */ + return DMACHNBUSY; + } + + temp = ( desp.cda & 0x7ffffff ) << 5; + temp |= (( desp.snen & 0x1 ) << 4 ); + temp |= (( desp.eosie & 0x1 ) << 3 ); + temp |= (( desp.ctt & 0x3 ) << 1 ); + temp |= ( desp.eotd & 0x1 ); + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], temp ); + +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) cdar := 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], temp ); +#endif + + return DMASUCCESS; +} + +/************************************************************** + * function: DMA_Poke_Desp + * + * description: poke the current descriptor address register + * for a given channel + * + * return DMASUCCESS if no error + * + * note: Due to the undeterministic parallellism of DMA operation, + * the value returned by this function shall be taken as + * the most recently used descriptor when the last time + * DMA starts a chaining mode operation. + **************************************************************/ +static +DMAStatus DMA_Poke_Desp( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CDAR *desp ) +{ + unsigned int cdar; + if ( channel != 0 && channel != 1 || desp == 0 ) + { + return DMAINVALID; + } + + cdar = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG] ); + +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) cdar : 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], cdar ); +#endif + + + desp->cda = ( cdar & 0xffffffe0 ) >> 5; + desp->snen = ( cdar & 0x00000010 ) >> 4; + desp->eosie = ( cdar & 0x00000008 ) >> 3; + desp->ctt = ( cdar & 0x00000006 ) >> 1; + desp->eotd = ( cdar & 0x00000001 ); + + return DMASUCCESS; +} + +/************************************************************** + * function: DMA_Bld_Curr + * + * description: set current src, dest, byte count registers + * according to the desp for a given channel + * return DMASUCCESS if no error. + * + * note: + **************************************************************/ +static +DMAStatus DMA_Bld_Curr( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CURR desp ) +{ + DMA_SR status; + if ( channel != 0 && channel != 1 ) + { + /* channel number out of range */ + return DMAINVALID; + } + + if ( DMA_Get_Stat( host, eumbbar, channel, &status ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( status.cb == 1 ) + { + /* channel busy */ + return DMACHNBUSY; + } + + desp.byte_cnt &= 0x03ffffff; /* upper 6-bits are 0s */ + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SAR_REG], desp.src_addr ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) src := 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.src_addr ); +#endif + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_DAR_REG], desp.dest_addr ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) dest := 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.dest_addr ); +#endif + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_BCR_REG], desp.byte_cnt ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) count := 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.byte_cnt ); +#endif + + + return DMASUCCESS; + +} + +/************************************************************** + * function: DMA_Poke_Curr + * + * description: poke the current src, dest, byte count registers + * for a given channel. + * + * return DMASUCCESS if no error + * + * note: Due to the undeterministic parallelism, in chaining + * mode, the value returned by this function shall + * be taken as reference when the query is made rather + * than the absolute snapshot when the value is returned. + **************************************************************/ +static +DMAStatus DMA_Poke_Curr( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CURR* desp ) +{ + if ( channel != 0 && channel != 1 || desp == 0 ) + { + return DMAINVALID; + } + + desp->src_addr = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SAR_REG] ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) src : 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->src_addr ); +#endif + + desp->dest_addr = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_DAR_REG] ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) dest : 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->dest_addr ); +#endif + + desp->byte_cnt = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_BCR_REG] ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) count : 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->byte_cnt ); +#endif + + + return DMASUCCESS; +} + +/***************************************************************** + * function: dma_error_func + * + * description: display the error information + * + * note: This seems like a highly convoluted way to handle messages, + * but I'll leave it as it was in device.c when I moved it into the + * DMA library source. + ****************************************************************/ +static +DMAStatus dma_error_func( unsigned int eumbbar, unsigned int chn, DMAStatus err) +{ + unsigned char *msg[] = + { + "Local Memory Error", + "PCI Error", + "Channel Busy", + "End-of-Segment Interrupt", + "End-of-Chain/Direct Interrupt", + }; + + if ( err >= DMALMERROR && err <= DMAEOCAINT ) + { + PRINT( "DMA Status: channel %d %s\n", chn, msg[err-DMASUCCESS-1] ); + } + + return err; + +} + +/************************************************************* + * function: DMA_ISR + * + * description: DMA interrupt service routine + * return DMAStatus value based on + * the status + * + *************************************************************/ +static +DMAStatus DMA_ISR( unsigned int eumbbar, + unsigned int channel, + DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus )) +{ + + DMA_SR stat; + DMAStatus rval = DMANOEVENT; + unsigned int temp; + + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + if ( DMA_Get_Stat( LOCAL, eumbbar, channel, &stat ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( stat.lme == 1 ) + { + /* local memory error */ + rval = DMALMERROR; + if ( lme_func != 0 ) + { + rval = (*lme_func)(eumbbar, channel, DMALMERROR ); + } + + } + else if ( stat.pe == 1 ) + { + /* PCI error */ + rval = DMAPERROR; + if ( pe_func != 0 ) + { + rval = (*pe_func)(eumbbar, channel, DMAPERROR ); + } + + } + else if ( stat.eosi == 1 ) + { + /* end-of-segment interrupt */ + rval = DMAEOSINT; + if ( eosi_func != 0 ) + { + rval = (*eosi_func)(eumbbar, channel, DMAEOSINT ); + } + } + else + { + /* End-of-chain/direct interrupt */ + rval = DMAEOCAINT; + if ( eocai_func != 0 ) + { + rval = (*eocai_func)(eumbbar, channel, DMAEOCAINT ); + } + } + + temp = ( stat.reserved0 & 0xffffff ) << 8; + temp |= ( ( stat.lme & 0x1 ) << 7 ); /* write one to clear */ + temp |= ( ( stat.reserved1 & 0x3 ) << 5 ); + temp |= ( ( stat.pe & 0x1 ) << 4 ); /* write one to clear */ + temp |= ( ( stat.reserved2 & 0x1 ) << 3 ); + temp |= ( ( stat.cb & 0x1 ) << 2 ); /* write one to clear */ + temp |= ( ( stat.eosi & 0x1 ) << 1 ); /* write one to clear */ + temp |= ( stat.eocai & 0x1 ); /* write one to clear */ + + store_runtime_reg( eumbbar, dma_reg_tb[LOCAL][channel*NUM_DMA_REG + DMA_SR_REG], temp ); + +#ifdef DMADBG0 + PRINT( "%s(%d): DMA channel %d SR := 0x%08x\n", __FILE__, __LINE__, channel, temp ); +#endif + + return rval; +} diff --git a/cpu/mpc824x/drivers/dma/dma2.S b/cpu/mpc824x/drivers/dma/dma2.S new file mode 100644 index 0000000..ccbc226 --- /dev/null +++ b/cpu/mpc824x/drivers/dma/dma2.S @@ -0,0 +1,42 @@ +/************************************** + * + * copyright @ Motorola, 1999 + * + **************************************/ + +/********************************************************** + * function: load_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * + * output: r3 - register content + **********************************************************/ + .text + .align 2 + .global load_runtime_reg + +load_runtime_reg: + + lwbrx r3,r4,r3 + sync + + bclr 20, 0 + +/**************************************************************** + * function: store_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * r5 - new value to be stored + * + ****************************************************************/ + .text + .align 2 + .global store_runtime_reg +store_runtime_reg: + + stwbrx r5, r4, r3 + sync + + bclr 20,0 diff --git a/cpu/mpc824x/drivers/dma/dma_export.h b/cpu/mpc824x/drivers/dma/dma_export.h new file mode 100644 index 0000000..471e488 --- /dev/null +++ b/cpu/mpc824x/drivers/dma/dma_export.h @@ -0,0 +1,100 @@ +#ifndef DMA_EXPORT_H +#define DMA_EXPORT_H + +/**************************************************** + * $Id: + * + * Copyright Motorola 1999 + * + * $Log: + * + ****************************************************/ + +/* These are the defined return values for the DMA_* functions. + * Any non-zero value indicates failure. Failure modes can be added for + * more detailed error reporting. + */ +typedef enum _dma_status +{ + DMA_SUCCESS = 0, + DMA_ERROR, +} DMA_Status; + +/* These are the defined channel transfer types. */ +typedef enum _dma_transfer_types +{ + DMA_M2M = 0, /* local memory to local memory */ + DMA_M2P = 1, /* local memory to PCI */ + DMA_P2M = 2, /* PCI to local memory */ + DMA_P2P = 3, /* PCI to PCI */ +} DMA_TRANSFER_TYPE; + +typedef enum _dma_interrupt_steer +{ + DMA_INT_STEER_LOCAL = 0, /* steer DMA int to local processor */ + DMA_INT_STEER_PCI = 1, /* steer DMA int to PCI bus through INTA_ */ +} DMA_INTERRUPT_STEER; + +typedef enum _dma_channel +{ + DMA_CHN_0 = 0, /* kahlua has two dma channels: 0 and 1 */ + DMA_CHN_1 = 1, +} DMA_CHANNEL; + +typedef enum _dma_snoop_mode +{ + DMA_SNOOP_DISABLE = 0, + DMA_SNOOP_ENABLE = 1, +} DMA_SNOOP_MODE; + +/******************** App. API ******************** + * The application API is for user level application + * to use the functionality provided by DMA driver. + * This is a "generic" DMA interface, it should contain + * nothing specific to the Kahlua implementation. + * Only the generic functions are exported by the library. + * + * Note: Its App.s responsibility to swap the data + * byte. In our API, we currently transfer whatever + * we are given - Big/Little Endian. This could + * become part of the DMA config, though. + **************************************************/ + + +/* Initialize DMA unit with the following: + * optional pointer to application layer print function + * + * These parameters may be added: + * ??? + * Interrupt enables, modes, etc. are set for each transfer. + * + * This function must be called before DMA unit can be used. + */ +extern DMA_Status DMA_Initialize( + int (*app_print_function)(char *,...)); /* pointer to optional "printf" + * provided by application + */ + +/* Perform the DMA transfer, only direct mode is currently implemented. + * At this point, I think it would be better to define a different + * function for chaining mode. + * Also, I'm not sure if it is appropriate to have the "generic" API + * accept snoop and int_steer parameters. The DINK user interface allows + * them, so for now I'll leave them. + * + * int_steer controls DMA interrupt steering to PCI or local processor + * type is the type of transfer: M2M, M2P, P2M, P2P + * source is the source address of the data + * dest is the destination address of the data + * len is the length of data to transfer + * channel is the DMA channel to use for the transfer + * snoop is the snoop enable control + */ +extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer, + DMA_TRANSFER_TYPE type, + unsigned int source, + unsigned int dest, + unsigned int len, + DMA_CHANNEL channel, + DMA_SNOOP_MODE snoop); +#endif diff --git a/cpu/mpc824x/drivers/dma_export.h b/cpu/mpc824x/drivers/dma_export.h new file mode 100644 index 0000000..471e488 --- /dev/null +++ b/cpu/mpc824x/drivers/dma_export.h @@ -0,0 +1,100 @@ +#ifndef DMA_EXPORT_H +#define DMA_EXPORT_H + +/**************************************************** + * $Id: + * + * Copyright Motorola 1999 + * + * $Log: + * + ****************************************************/ + +/* These are the defined return values for the DMA_* functions. + * Any non-zero value indicates failure. Failure modes can be added for + * more detailed error reporting. + */ +typedef enum _dma_status +{ + DMA_SUCCESS = 0, + DMA_ERROR, +} DMA_Status; + +/* These are the defined channel transfer types. */ +typedef enum _dma_transfer_types +{ + DMA_M2M = 0, /* local memory to local memory */ + DMA_M2P = 1, /* local memory to PCI */ + DMA_P2M = 2, /* PCI to local memory */ + DMA_P2P = 3, /* PCI to PCI */ +} DMA_TRANSFER_TYPE; + +typedef enum _dma_interrupt_steer +{ + DMA_INT_STEER_LOCAL = 0, /* steer DMA int to local processor */ + DMA_INT_STEER_PCI = 1, /* steer DMA int to PCI bus through INTA_ */ +} DMA_INTERRUPT_STEER; + +typedef enum _dma_channel +{ + DMA_CHN_0 = 0, /* kahlua has two dma channels: 0 and 1 */ + DMA_CHN_1 = 1, +} DMA_CHANNEL; + +typedef enum _dma_snoop_mode +{ + DMA_SNOOP_DISABLE = 0, + DMA_SNOOP_ENABLE = 1, +} DMA_SNOOP_MODE; + +/******************** App. API ******************** + * The application API is for user level application + * to use the functionality provided by DMA driver. + * This is a "generic" DMA interface, it should contain + * nothing specific to the Kahlua implementation. + * Only the generic functions are exported by the library. + * + * Note: Its App.s responsibility to swap the data + * byte. In our API, we currently transfer whatever + * we are given - Big/Little Endian. This could + * become part of the DMA config, though. + **************************************************/ + + +/* Initialize DMA unit with the following: + * optional pointer to application layer print function + * + * These parameters may be added: + * ??? + * Interrupt enables, modes, etc. are set for each transfer. + * + * This function must be called before DMA unit can be used. + */ +extern DMA_Status DMA_Initialize( + int (*app_print_function)(char *,...)); /* pointer to optional "printf" + * provided by application + */ + +/* Perform the DMA transfer, only direct mode is currently implemented. + * At this point, I think it would be better to define a different + * function for chaining mode. + * Also, I'm not sure if it is appropriate to have the "generic" API + * accept snoop and int_steer parameters. The DINK user interface allows + * them, so for now I'll leave them. + * + * int_steer controls DMA interrupt steering to PCI or local processor + * type is the type of transfer: M2M, M2P, P2M, P2P + * source is the source address of the data + * dest is the destination address of the data + * len is the length of data to transfer + * channel is the DMA channel to use for the transfer + * snoop is the snoop enable control + */ +extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer, + DMA_TRANSFER_TYPE type, + unsigned int source, + unsigned int dest, + unsigned int len, + DMA_CHANNEL channel, + DMA_SNOOP_MODE snoop); +#endif diff --git a/cpu/mpc824x/drivers/epic.h b/cpu/mpc824x/drivers/epic.h new file mode 100644 index 0000000..2803f63 --- /dev/null +++ b/cpu/mpc824x/drivers/epic.h @@ -0,0 +1 @@ +#include "epic/epic.h" diff --git a/cpu/mpc824x/drivers/epic/README b/cpu/mpc824x/drivers/epic/README new file mode 100644 index 0000000..5798996 --- /dev/null +++ b/cpu/mpc824x/drivers/epic/README @@ -0,0 +1,102 @@ +CONTENT: + + epic.h + epic1.c + epic2.s + +WHAT ARE THESE FILES: + +These files contain MPC8240 (Kahlua) EPIC +driver routines. The driver routines are not +written for any specific operating system. +They serves the purpose of code sample, and +jump-start for using the MPC8240 EPIC unit. + +For the reason of correctness of C language +syntax, these files are compiled by Metaware +C compiler and assembler. + +ENDIAN NOTATION: + +The algorithm is designed for big-endian mode, +software is responsible for byte swapping. + +USAGE: + +1. The host system that is running on MPC8240 + shall link the files listed here. The memory + location of driver routines shall take into + account of that driver routines need to run + in supervisor mode and they process external + interrupts. + + The routine epic_exception shall be called by + exception vector at location 0x500, i.e., + 603e core external exception vector. + +2. The host system is responsible for configuring + the MPC8240 including Embedded Utilities Memory + Block. All EPIC driver functions require the + content of Embedded Utilities Memory Block + Base Address Register, EUMBBAR, as the first + parameter. + +3. Before EPIC unit of MPC8240 can be used, + initialize EPIC unit by calling epicInit + with the corresponding parameters. + + The initialization shall disable the 603e + core External Exception by calling CoreExtIntDisable( ). + Next, call epicInit( ). Last, enable the 603e core + External Exception by calling CoreExtIntEnable( ). + +4. After EPIC unit has been successfully initialized, + epicIntSourceSet( ) shall be used to register each + external interrupt source. Anytime, an external + interrupt source can be disabled or enabled by + calling corresponding function, epicIntDisable( ), + or epicIntEnable( ). + + Global Timers' resource, base count and frequency, + can be changed by calling epicTmFrequencySet( ) + and epicTmBaseSet( ). + + To stop counting a specific global timer, use + the function, epicTmInhibit while epicTmEnable + can be used to start counting a timer. + +5. To mask a set of external interrupts that are + are certain level below, epicIntPrioritySet( ) + can be used. For example, if the processor's + current task priority register is set to 0x7, + only interrupts of priority 0x8 or higher will + be passed to the processor. + + Be careful when using this function. It may + corrupt the current interrupt pending, selector, + and request registers, resulting an invalid vetor. + + After enabling an interrupt, disable it may also + cause an invalid vector. User may consider using + the spurious vector interrupt service routine to + handle this case. + +6. The EPIC driver routines contains a set + of utilities, Set and Get, for host system + to query and modify the desired EPIC source + registers. + +7. Each external interrupt source shall register + its interrupt service routine. The routine + shall contain all interrupt source specific + processes and keep as short as possible. + + Special customized end of interrupt routine + is optional. If it is needed, it shall contain + the external interrupt source specific end of + interrupt process. + + External interrupt exception vector at 0x500 + shall always call the epicEOI just before + rfi instruction. Refer to the routine, + epic_exception, for a code sample. diff --git a/cpu/mpc824x/drivers/epic/epic.h b/cpu/mpc824x/drivers/epic/epic.h new file mode 100644 index 0000000..58f81c5 --- /dev/null +++ b/cpu/mpc824x/drivers/epic/epic.h @@ -0,0 +1,163 @@ +/********************************************************************* + * mpc8240epic.h - EPIC module of the MPC8240 micro-controller + * + * Copyrigh 1999 Motorola Inc. + * + * Modification History: + * ===================== + * 01a,04Feb99,My Created. + * 15Nov200, robt -modified to use in U-Boot + * +*/ + +#ifndef __INCEPICh +#define __INCEPICh + +#define ULONG unsigned long +#define MAXVEC 20 +#define MAXIRQ 5 /* IRQs */ +#define EPIC_DIRECT_IRQ 0 /* Direct interrupt type */ + +/* EPIC register addresses */ + +#define EPIC_EUMBBAR 0x40000 /* EUMBBAR of EPIC */ +#define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */ +#define EPIC_GLOBAL_REG (EPIC_EUMBBAR + 0x01020)/* Global config. */ +#define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */ +#define EPIC_VENDOR_ID_REG (EPIC_EUMBBAR + 0x01080)/* Vendor id */ +#define EPIC_PROC_INIT_REG (EPIC_EUMBBAR + 0x01090)/* Processor init. */ +#define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */ +#define EPIC_TM_FREQ_REG (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */ + +#define EPIC_TM0_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/ +#define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/ +#define EPIC_TM0_VEC_REG (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/ +#define EPIC_TM0_DES_REG (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */ + +#define EPIC_TM1_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/ +#define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/ +#define EPIC_TM1_VEC_REG (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/ +#define EPIC_TM1_DES_REG (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */ + +#define EPIC_TM2_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/ +#define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/ +#define EPIC_TM2_VEC_REG (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/ +#define EPIC_TM2_DES_REG (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */ + +#define EPIC_TM3_CUR_COUNT_REG (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/ +#define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/ +#define EPIC_TM3_VEC_REG (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/ +#define EPIC_TM3_DES_REG (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */ + +#define EPIC_EX_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */ +#define EPIC_EX_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/ +#define EPIC_EX_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */ +#define EPIC_EX_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/ +#define EPIC_EX_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */ +#define EPIC_EX_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/ +#define EPIC_EX_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */ +#define EPIC_EX_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/ +#define EPIC_EX_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */ +#define EPIC_EX_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/ + +#define EPIC_SR_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */ +#define EPIC_SR_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */ +#define EPIC_SR_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */ +#define EPIC_SR_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/ +#define EPIC_SR_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */ +#define EPIC_SR_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/ +#define EPIC_SR_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */ +#define EPIC_SR_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/ +#define EPIC_SR_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */ +#define EPIC_SR_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/ + +#define EPIC_SR_INT5_VEC_REG (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */ +#define EPIC_SR_INT5_DES_REG (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/ +#define EPIC_SR_INT6_VEC_REG (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */ +#define EPIC_SR_INT6_DES_REG (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/ +#define EPIC_SR_INT7_VEC_REG (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */ +#define EPIC_SR_INT7_DES_REG (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/ +#define EPIC_SR_INT8_VEC_REG (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */ +#define EPIC_SR_INT8_DES_REG (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/ +#define EPIC_SR_INT9_VEC_REG (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */ +#define EPIC_SR_INT9_DES_REG (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/ + +#define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */ +#define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/ +#define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */ +#define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/ +#define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */ +#define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/ +#define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */ +#define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/ +#define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */ +#define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/ +#define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */ +#define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/ + +#define EPIC_I2C_INT_VEC_REG (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/ +#define EPIC_I2C_INT_DES_REG (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */ +#define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/ +#define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */ +#define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/ +#define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */ +#define EPIC_MSG_INT_VEC_REG (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/ +#define EPIC_MSG_INT_DES_REG (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest */ + +#define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/ +#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */ +#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */ + +#define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */ +#define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */ + +/* Error code */ + +#define OK 0 +#define ERROR -1 + +/* function prototypes */ + +void epicVendorId( unsigned int *step, + unsigned int *devId, + unsigned int *venId + ); +void epicFeatures( unsigned int *noIRQs, + unsigned int *noCPUs, + unsigned int *VerId ); +extern void epicInit( unsigned int IRQType, unsigned int clkRatio); +ULONG sysEUMBBARRead ( ULONG regNum ); +void sysEUMBBARWrite ( ULONG regNum, ULONG regVal); +extern void epicTmFrequencySet( unsigned int frq ); +extern unsigned int epicTmFrequencyGet(void); +extern unsigned int epicTmBaseSet( ULONG srcAddr, + unsigned int cnt, + unsigned int inhibit ); +extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val ); +extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ); +extern unsigned int epicTmInhibit( unsigned int timer ); +extern unsigned int epicTmEnable( ULONG srcAdr ); +extern void CoreExtIntEnable(void); /* Enable 603e external interrupts */ +extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */ +extern unsigned char epicIntTaskGet(void); +extern void epicIntTaskSet( unsigned char val ); +extern unsigned int epicIntAck(void); +extern void epicSprSet( unsigned int eumbbar, unsigned char ); +extern void epicConfigGet( unsigned int *clkRatio, + unsigned int *serEnable ); +extern void SrcVecTableInit(void); +extern unsigned int epicModeGet(void); +extern void epicIntEnable(int Vect); +extern void epicIntDisable(int Vect); +extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio); +extern unsigned int epicIntAck(void); +extern void epicEOI(void); +extern int epicCurTaskPrioSet(int Vect); + +struct SrcVecTable + { + ULONG srcAddr; + char srcName[40]; + }; + +#endif /* EPIC_H */ diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c new file mode 100644 index 0000000..f89deed --- /dev/null +++ b/cpu/mpc824x/drivers/epic/epic1.c @@ -0,0 +1,517 @@ +/************************************************** + * + * copyright @ motorola, 1999 + * + *************************************************/ +#include +#include +#include "epic.h" + + +#define PRINT(format, args...) printf(format , ## args) + +typedef void (*VOIDFUNCPTR) (void); /* ptr to function returning void */ +struct SrcVecTable SrcVecTable[MAXVEC] = /* Addr/Vector cross-reference tbl */ + { + { EPIC_EX_INT0_VEC_REG, "External Direct/Serial Source 0"}, + { EPIC_EX_INT1_VEC_REG, "External Direct/Serial Source 1"}, + { EPIC_EX_INT2_VEC_REG, "External Direct/Serial Source 2"}, + { EPIC_EX_INT3_VEC_REG, "External Direct/Serial Source 3"}, + { EPIC_EX_INT4_VEC_REG, "External Direct/Serial Source 4"}, + + { EPIC_SR_INT5_VEC_REG, "External Serial Source 5"}, + { EPIC_SR_INT6_VEC_REG, "External Serial Source 6"}, + { EPIC_SR_INT7_VEC_REG, "External Serial Source 7"}, + { EPIC_SR_INT8_VEC_REG, "External Serial Source 8"}, + { EPIC_SR_INT9_VEC_REG, "External Serial Source 9"}, + { EPIC_SR_INT10_VEC_REG, "External Serial Source 10"}, + { EPIC_SR_INT11_VEC_REG, "External Serial Source 11"}, + { EPIC_SR_INT12_VEC_REG, "External Serial Source 12"}, + { EPIC_SR_INT13_VEC_REG, "External Serial Source 13"}, + { EPIC_SR_INT14_VEC_REG, "External Serial Source 14"}, + { EPIC_SR_INT15_VEC_REG, "External Serial Source 15"}, + + { EPIC_I2C_INT_VEC_REG, "Internal I2C Source"}, + { EPIC_DMA0_INT_VEC_REG, "Internal DMA0 Source"}, + { EPIC_DMA1_INT_VEC_REG, "Internal DMA1 Source"}, + { EPIC_MSG_INT_VEC_REG, "Internal Message Source"}, + }; + +VOIDFUNCPTR intVecTbl[MAXVEC]; /* Interrupt vector table */ + + +/**************************************************************************** +* epicInit - Initialize the EPIC registers +* +* This routine resets the Global Configuration Register, thus it: +* - Disables all interrupts +* - Sets epic registers to reset values +* - Sets the value of the Processor Current Task Priority to the +* highest priority (0xF). +* epicInit then sets the EPIC operation mode to Mixed Mode (vs. Pass +* Through or 8259 compatible mode). +* +* If IRQType (input) is Direct IRQs: +* - IRQType is written to the SIE bit of the EPIC Interrupt +* Configuration register (ICR). +* - clkRatio is ignored. +* If IRQType is Serial IRQs: +* - both IRQType and clkRatio will be written to the ICR register +*/ + +void epicInit + ( + unsigned int IRQType, /* Direct or Serial */ + unsigned int clkRatio /* Clk Ratio for Serial IRQs */ + ) + { + ULONG tmp; + + tmp = sysEUMBBARRead(EPIC_GLOBAL_REG); + tmp |= 0xa0000000; /* Set the Global Conf. register */ + sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp); + /* + * Wait for EPIC to reset - CLH + */ + while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1); + sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000); + tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */ + + if (IRQType == EPIC_DIRECT_IRQ) /* direct mode */ + sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff); + else /* Serial mode */ + { + tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */ + sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp); + } + + while (epicIntAck() != 0xff) /* Clear all pending interrupts */ + epicEOI(); +} + +/**************************************************************************** + * epicIntEnable - Enable an interrupt source + * + * This routine clears the mask bit of an external, an internal or + * a Timer register to enable the interrupt. + * + * RETURNS: None + */ +void epicIntEnable(int intVec) +{ + ULONG tmp; + ULONG srAddr; + + srAddr = SrcVecTable[intVec].srcAddr; /* Retrieve src Vec/Prio register */ + tmp = sysEUMBBARRead(srAddr); + tmp &= ~EPIC_VEC_PRI_MASK; /* Clear the mask bit */ + tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16); /* Set priority to Default - CLH */ + tmp |= intVec; /* Set Vector number */ + sysEUMBBARWrite(srAddr, tmp); + + return; + } + +/**************************************************************************** + * epicIntDisable - Disable an interrupt source + * + * This routine sets the mask bit of an external, an internal or + * a Timer register to disable the interrupt. + * + * RETURNS: OK or ERROR + * + */ + +void epicIntDisable + ( + int intVec /* Interrupt vector number */ + ) + { + + ULONG tmp, srAddr; + + srAddr = SrcVecTable[intVec].srcAddr; + tmp = sysEUMBBARRead(srAddr); + tmp |= 0x80000000; /* Set the mask bit */ + sysEUMBBARWrite(srAddr, tmp); + return; + } + +/**************************************************************************** + * epicIntSourceConfig - Set properties of an interrupt source + * + * This function sets interrupt properites (Polarity, Sense, Interrupt + * Prority, and Interrupt Vector) of an Interrupt Source. The properties + * can be set when the current source is not in-request or in-service, + * which is determined by the Activity bit. This routine return ERROR + * if the the Activity bit is 1 (in-request or in-service). + * + * This function assumes that the Source Vector/Priority register (input) + * is a valid address. + * + * RETURNS: OK or ERROR + */ + +int epicIntSourceConfig + ( + int Vect, /* interrupt source vector number */ + int Polarity, /* interrupt source polarity */ + int Sense, /* interrupt source Sense */ + int Prio /* interrupt source priority */ + ) + + { + ULONG tmp, newVal; + ULONG actBit, srAddr; + + srAddr = SrcVecTable[Vect].srcAddr; + tmp = sysEUMBBARRead(srAddr); + actBit = (tmp & 40000000) >> 30; /* retrieve activity bit - bit 30 */ + if (actBit == 1) + return ERROR; + + tmp &= 0xff30ff00; /* Erase previously set P,S,Prio,Vector bits */ + newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect; + sysEUMBBARWrite(srAddr, tmp | newVal ); + return (OK); + } + +/**************************************************************************** + * epicIntAck - acknowledge an interrupt + * + * This function reads the Interrupt acknowldge register and return + * the vector number of the highest pending interrupt. + * + * RETURNS: Interrupt Vector number. + */ + +unsigned int epicIntAck(void) +{ + return(sysEUMBBARRead( EPIC_PROC_INT_ACK_REG )); +} + +/**************************************************************************** + * epicEOI - signal an end of interrupt + * + * This function writes 0x0 to the EOI register to signal end of interrupt. + * It is usually called after an interrupt routine is served. + * + * RETURNS: None + */ + +void epicEOI(void) + { + sysEUMBBARWrite(EPIC_PROC_EOI_REG, 0x0); + } + +/**************************************************************************** + * epicCurTaskPrioSet - sets the priority of the Processor Current Task + * + * This function should be called after epicInit() to lower the priority + * of the processor current task. + * + * RETURNS: OK or ERROR + */ + +int epicCurTaskPrioSet + ( + int prioNum /* New priority value */ + ) + { + + if ( (prioNum < 0) || (prioNum > 0xF)) + return ERROR; + sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum); + return OK; + } + + +/************************************************************************ + * function: epicIntTaskGet + * + * description: Get value of processor current interrupt task priority register + * + * note: + ***********************************************************************/ +unsigned char epicIntTaskGet() +{ + /* get the interrupt task priority register */ + ULONG reg; + unsigned char rec; + + reg = sysEUMBBARRead( EPIC_PROC_CTASK_PRI_REG ); + rec = ( reg & 0x0F ); + return rec; +} + + +/************************************************************** + * function: epicISR + * + * description: EPIC service routine called by the core exception + * at 0x500 + * + * note: + **************************************************************/ +unsigned int epicISR(void) +{ + return 0; +} + + +/************************************************************ + * function: epicModeGet + * + * description: query EPIC mode, return 0 if pass through mode + * return 1 if mixed mode + * + * note: + *************************************************************/ +unsigned int epicModeGet(void) +{ + ULONG val; + + val = sysEUMBBARRead( EPIC_GLOBAL_REG ); + return (( val & 0x20000000 ) >> 29); +} + + +/********************************************* + * function: epicConfigGet + * + * description: Get the EPIC interrupt Configuration + * return 0 if not error, otherwise return 1 + * + * note: + ********************************************/ +void epicConfigGet( unsigned int *clkRatio, unsigned int *serEnable) +{ + ULONG val; + + val = sysEUMBBARRead( EPIC_INT_CONF_REG ); + *clkRatio = ( val & 0x70000000 ) >> 28; + *serEnable = ( val & 0x8000000 ) >> 27; +} + + +/******************************************************************* + * sysEUMBBARRead - Read a 32-bit EUMBBAR register + * + * This routine reads the content of a register in the Embedded + * Utilities Memory Block, and swaps to big endian before returning + * the value. + * + * RETURNS: The content of the specified EUMBBAR register. + */ + +ULONG sysEUMBBARRead + ( + ULONG regNum + ) + { + ULONG temp; + + temp = *(ULONG *) (CFG_EUMB_ADDR + regNum); + return ( LONGSWAP(temp)); + } + +/******************************************************************* + * sysEUMBBARWrite - Write a 32-bit EUMBBAR register + * + * This routine swaps the value to little endian then writes it to + * a register in the Embedded Utilities Memory Block address space. + * + * RETURNS: N/A + */ + +void sysEUMBBARWrite + ( + ULONG regNum, /* EUMBBAR register address */ + ULONG regVal /* Value to be written */ + ) + { + + *(ULONG *) (CFG_EUMB_ADDR + regNum) = LONGSWAP(regVal); + return ; + } + + +/******************************************************** + * function: epicVendorId + * + * description: return the EPIC Vendor Identification + * register: + * + * siliccon version, device id, and vendor id + * + * note: + ********************************************************/ +void epicVendorId + ( + unsigned int *step, + unsigned int *devId, + unsigned int *venId + ) + { + ULONG val; + val = sysEUMBBARRead( EPIC_VENDOR_ID_REG ); + *step = ( val & 0x00FF0000 ) >> 16; + *devId = ( val & 0x0000FF00 ) >> 8; + *venId = ( val & 0x000000FF ); + } + +/************************************************** + * function: epicFeatures + * + * description: return the number of IRQ supported, + * number of CPU, and the version of the + * OpenEPIC + * + * note: + *************************************************/ +void epicFeatures + ( + unsigned int *noIRQs, + unsigned int *noCPUs, + unsigned int *verId + ) + { + ULONG val; + + val = sysEUMBBARRead( EPIC_FEATURES_REG ); + *noIRQs = ( val & 0x07FF0000 ) >> 16; + *noCPUs = ( val & 0x00001F00 ) >> 8; + *verId = ( val & 0x000000FF ); +} + + +/********************************************************* + * function: epciTmFrequncySet + * + * description: Set the timer frequency reporting register + ********************************************************/ +void epicTmFrequencySet( unsigned int frq ) +{ + sysEUMBBARWrite(EPIC_TM_FREQ_REG, frq); +} + +/******************************************************* + * function: epicTmFrequncyGet + * + * description: Get the current value of the Timer Frequency + * Reporting register + * + ******************************************************/ +unsigned int epicTmFrequencyGet(void) +{ + return( sysEUMBBARRead(EPIC_TM_FREQ_REG)) ; +} + + +/**************************************************** + * function: epicTmBaseSet + * + * description: Set the #n global timer base count register + * return 0 if no error, otherwise return 1. + * + * note: + ****************************************************/ +unsigned int epicTmBaseSet + ( + ULONG srcAddr, /* Address of the Timer Base register */ + unsigned int cnt, /* Base count */ + unsigned int inhibit /* 1 - count inhibit */ + ) +{ + + unsigned int val = 0x80000000; + /* First inhibit counting the timer */ + sysEUMBBARWrite(srcAddr, val) ; + + /* set the new value */ + val = (cnt & 0x7fffffff) | ((inhibit & 0x1) << 31); + sysEUMBBARWrite(srcAddr, val) ; + return 0; +} + +/*********************************************************************** + * function: epicTmBaseGet + * + * description: Get the current value of the global timer base count register + * return 0 if no error, otherwise return 1. + * + * note: + ***********************************************************************/ +unsigned int epicTmBaseGet( ULONG srcAddr, unsigned int *val ) +{ + *val = sysEUMBBARRead( srcAddr ); + *val = *val & 0x7fffffff; + return 0; +} + +/*********************************************************** + * function: epicTmCountGet + * + * description: Get the value of a given global timer + * current count register + * return 0 if no error, otherwise return 1 + * note: + **********************************************************/ +unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ) +{ + *val = sysEUMBBARRead( srcAddr ); + *val = *val & 0x7fffffff; + return 0; +} + + +/*********************************************************** + * function: epicTmInhibit + * + * description: Stop counting of a given global timer + * return 0 if no error, otherwise return 1 + * + * note: + ***********************************************************/ +unsigned int epicTmInhibit( unsigned int srcAddr ) +{ + ULONG val; + + val = sysEUMBBARRead( srcAddr ); + val |= 0x80000000; + sysEUMBBARWrite( srcAddr, val ); + return 0; +} + +/****************************************************************** + * function: epicTmEnable + * + * description: Enable counting of a given global timer + * return 0 if no error, otherwise return 1 + * + * note: + *****************************************************************/ +unsigned int epicTmEnable( ULONG srcAddr ) +{ + ULONG val; + + val = sysEUMBBARRead( srcAddr ); + val &= 0x7fffffff; + sysEUMBBARWrite( srcAddr, val ); + return 0; +} + +void epicSourcePrint(int Vect) + { + ULONG srcVal; + + srcVal = sysEUMBBARRead(SrcVecTable[Vect].srcAddr); + PRINT("%s\n", SrcVecTable[Vect].srcName); + PRINT("Address = 0x%lx\n", SrcVecTable[Vect].srcAddr); + PRINT("Vector = %ld\n", (srcVal & 0x000000FF) ); + PRINT("Mask = %ld\n", srcVal >> 31); + PRINT("Activitiy = %ld\n", (srcVal & 40000000) >> 30); + PRINT("Polarity = %ld\n", (srcVal & 0x00800000) >> 23); + PRINT("Sense = %ld\n", (srcVal & 0x00400000) >> 22); + PRINT("Priority = %ld\n", (srcVal & 0x000F0000) >> 16); + } diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S new file mode 100644 index 0000000..8cc2fc6 --- /dev/null +++ b/cpu/mpc824x/drivers/epic/epic2.S @@ -0,0 +1,196 @@ +/************************************** + * + * copyright @ Motorola, 1999 + * + **************************************/ + +#include +#include +#include + +/********************************************* + * function: CoreExtIntEnable + * + * description: Enable 603e core external interrupt + * + * note: mtmsr is context-synchronization + **********************************************/ + .text + .align 2 + .global CoreExtIntEnable +CoreExtIntEnable: + mfmsr r3 + + ori r3,r3,0x8000 /* enable external interrupt */ + mtmsr r3 + + bclr 20, 0 + +/******************************************* + * function: CoreExtIntDisable + * + * description: Disable 603e core external interrupt + * + * note: + *******************************************/ + .text + .align 2 + .global CoreExtIntDisable +CoreExtIntDisable: + mfmsr r4 + + xor r3,r3,r3 + or r3,r3,r4 + + andis. r4,r4,0xffff + andi. r3,r3,0x7fff /* disable external interrupt */ + + or r3,r3,r4 + mtmsr r3 + + bclr 20, 0 + +/********************************************************* + * function: epicEOI + * + * description: signal the EOI and restore machine status + * Input: r3 - value of eumbbar + * Output: r3 - value of eumbbar + * r4 - ISR vector value + * note: + ********************************************************/ + .text + .align 2 + .global epicEOI +epicEOI: + lis r5,0x0006 /* Build End Of Interrupt Register offset */ + ori r5,r5,0x00b0 + xor r7,r7,r7 /* Clear r7 */ + stwbrx r7,r5,r3 /* Save r7, writing to this register will + * intidate the end of processing the + * highest interrupt. + */ + sync + + /* ---RESTORE MACHINE STATE */ + mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */ + or r7,r7,r13 + + andis. r7,r7,0xffff + andi. r13,r13,0x7ffd /* (and disable interrupts) */ + or r13,r13,r7 + mtmsr r13 + + lwz r13,0x1c(r1) /* pull ctr */ + mtctr r13 + + lwz r13,0x18(r1) /* pull xer */ + mtctr r13 + + lwz r13,0x14(r1) /* pull lr */ + mtctr r13 + + lwz r13,0x10(r1) /* Pull SRR1 from stack */ + mtspr SRR1,r13 /* Restore SRR1 */ + + lwz r13,0xc(r1) /* Pull SRR0 from stack */ + mtspr SRR0,r13 /* Restore SRR0 */ + + lwz r13,0x8(r1) /* Pull User stack pointer from stack */ + mtspr SPRG1,r13 /* Restore SPRG1 */ + + lwz r4,0x4(r1) /* vector value */ + lwz r3,0x0(r1) /* eumbbar */ + sync + + addi r1,r1,0x20 /* Deallocate stack */ + mtspr SPRG0,r1 /* Save updated Supervisor stack pointer */ + mfspr r1,SPRG1 /* Restore User stack pointer */ + + bclr 20,0 + +/*********************************************************** + * function: exception routine called by exception vector + * at 0x500, external interrupt + * + * description: Kahlua EPIC controller + * + * input: r3 - content of eumbbar + * output: r3 - ISR return value + * r4 - Interrupt vector number + * note: + ***********************************************************/ + + .text + .align 2 + .global epic_exception + +epic_exception: + + /*---SAVE MACHINE STATE TO A STACK */ + mtspr SPRG1,r1 /* Save User stack pointer to SPRG1 */ + mfspr r1,SPRG0 /* Load Supervisor stack pointer into r1 */ + + stwu r3,-0x20(r1) /* Push the value of eumbbar onto stack */ + + mfspr r3,SPRG1 /* Push User stack pointer onto stack */ + stw r3,0x8(r1) + mfspr r3,SRR0 /* Push SRR0 onto stack */ + stw r1,0xc(r1) + mfspr r3,SRR1 /* Push SRR1 onto stack */ + stw r3,0x10(r1) + mflr r3 + stw r3,0x14(r1) /* Push LR */ + mfxer r3 + stw r3,0x18(r1) /* Push Xer */ + mfctr r3 + stw r3,0x1c(r1) /* Push CTR */ + + mtspr SPRG0,r1 /* Save updated Supervisor stack pointer + * value to SPRG0 + */ + mfmsr r3 + ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */ + mtmsr r3 + + /* ---READ IN THE EUMBAR REGISTER */ + lwz r6,0(r1) /* this is eumbbar */ + sync + + /* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */ + lis r5,0x0006 /* Build Interrupt Acknowledge Register + * offset + */ + ori r5,r5,0x00a0 + lwbrx r7,r5,r6 /* Load interrupt vector into r7 */ + sync + + /* --MASK OFF ALL BITS EXCEPT THE VECTOR */ + xor r3,r3,r3 + xor r4,r4,r4 + or r3, r3, r6 /* eumbbar in r3 */ + andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */ + + stw r4,0x04(r1) /* save the vector value */ + + lis r5,epicISR@ha + ori r5,r5,epicISR@l + mtlr r5 + blrl + + xor r30,r30,r30 + or r30,r30,r3 /* save the r3 which containts the return value from epicISR */ + + /* ---READ IN THE EUMBAR REGISTER */ + lwz r3,0(r1) + sync + + lis r5,epicEOI@ha + ori r5,r5,epicEOI@l + mtlr r5 + blrl + + xor r3,r3,r3 + or r3,r3,r30 /* restore the ISR return value */ + + bclr 20,0 diff --git a/cpu/mpc824x/drivers/epic/epicutil.S b/cpu/mpc824x/drivers/epic/epicutil.S new file mode 100644 index 0000000..4877050 --- /dev/null +++ b/cpu/mpc824x/drivers/epic/epicutil.S @@ -0,0 +1,57 @@ +/************************************** + * + * copyright @ Motorola, 1999 + * + * + * This file contains two commonly used + * lower level utility routines. + * + * The utility routines are also in other + * Kahlua device driver libraries. The + * need to be linked in only once. + **************************************/ + +#include +#include + +/********************************************************** + * function: load_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * + * output: r3 - register content + **********************************************************/ + .text + .align 2 + .global load_runtime_reg + +load_runtime_reg: + + xor r5,r5,r5 + or r5,r5,r3 /* save eumbbar */ + + lwbrx r3,r4,r5 + sync + + bclr 20, 0 + +/**************************************************************** + * function: store_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * r5 - new value to be stored + * + ****************************************************************/ + .text + .align 2 + .global store_runtime_reg +store_runtime_reg: + + xor r0,r0,r0 + + stwbrx r5, r4, r3 + sync + + bclr 20,0 diff --git a/cpu/mpc824x/drivers/errors.h b/cpu/mpc824x/drivers/errors.h new file mode 100644 index 0000000..887f284 --- /dev/null +++ b/cpu/mpc824x/drivers/errors.h @@ -0,0 +1,212 @@ +/* Copyright Motorola, Inc. 1993, 1994 + ALL RIGHTS RESERVED + + You are hereby granted a copyright license to use, modify, and + distribute the SOFTWARE so long as this entire notice is retained + without alteration in any modified and/or redistributed versions, + and that such modified versions are clearly identified as such. + No licenses are granted by implication, estoppel or otherwise under + any patents or trademarks of Motorola, Inc. + + The SOFTWARE is provided on an "AS IS" basis and without warranty. + To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS + ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED + WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS + THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. + + To the maximum extent permitted by applicable law, IN NO EVENT SHALL + MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER + (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF + BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS + INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR + INABILITY TO USE THE SOFTWARE. Motorola assumes no responsibility + for the maintenance and support of the SOFTWARE. + +*/ + + +#include "config.h" + +/* + 1 2 3 4 5 6 7 8 +01234567890123456789012345678901234567890123456789012345678901234567890123456789 +*/ +/* List define statements here */ + +/* These are for all the toolboxes and functions to use. These will help +to standardize the error handling in the current project */ + + /* this is the "data type" for the error + messages in the system */ +#define STATUS unsigned int + + /* this is a success status code */ +#define SUCCESS 1 + + /* likewise this is failure */ +#define FAILURE 0 + +#define NUM_ERRORS 47 + +/* This first section of "defines" are for error codes ONLY. The called + routine will return one of these error codes to the caller. If the final + returned code is "VALID", then everything is a-okay. However, if one + of the functions returns a non-valid status, that error code should be + propogated back to all the callers. At the end, the last caller will + call an error_processing function, and send in the status which was + returned. It's up to the error_processing function to determine which + error occured (as indicated by the status), and print an appropriate + message back to the user. +*/ +/*----------------------------------------------------------------------*/ +/* these are specifically for the parser routines */ + +#define UNKNOWN_COMMAND 0xfb00 /* "unrecognized command " */ +#define UNKNOWN_REGISTER 0xfb01 /* "unknown register "*/ +#define ILLEGAL_RD_STAGE 0xfb02 /* cannot specify reg. family in range*/ +#define ILLEGAL_REG_FAMILY 0xfb03 /* "cannot specify a range of special + or miscellaneous registers"*/ +#define RANGE_CROSS_FAMILY 0xfb04 /* "cannot specify a range across + register families" */ +#define UNIMPLEMENTED_STAGE 0xfb05 /* invalid rd or rmm parameter format */ +#define REG_NOT_WRITEABLE 0xfb06 /* "unknown operator in arguements"*/ +#define INVALID_FILENAME 0xfb07 /* "invalid download filename" */ +#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */ +#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */ +#define FOR_BOARD_ONLY 0xfb0a /* "Not available for Unix." */ + + +/*----------------------------------------------------------------------*/ +/* these are for the error checking toolbox */ + +#define INVALID 0xfd00 /* NOT valid */ +#define VALID 0xfd01 /* valid */ + + /* This error is found in the fcn: + is_right_size_input() to indicate + that the input was not 8 characters + long. */ +#define INVALID_SIZE 0xfd02 + + /* This error is found in the fcn: + is_valid_address_range() to indicate + that the address given falls outside + of valid memory defined by MEM_START + to MEM_END. + */ +#define OUT_OF_BOUNDS_ADDRESS 0xfd03 + + /* This error is found in the fcn: + is_valid_hex_input() to indicate that + one of more of the characters entered + are not valid hex characters. Valid + hex characters are 0-9, A-F, a-f. + */ +#define INVALID_HEX_INPUT 0xfd04 + + /* This error is found in the fcn: + is_valid_register_number() to indicate + that a given register does not exist. + */ +#define REG_NOT_READABLE 0xfd05 + + /* This error is found in the fcn: + is_word_aligned_address() to indicate + that the given address is not word- + aligned. A word-aligned address ends + in 0x0,0x4,0x8,0xc. + */ +#define NOT_WORD_ALIGNED 0xfd07 + + /* This error is found in the fcn: + is_valid_address_range() to indicate + that the starting address is greater + than the ending address. + */ +#define REVERSED_ADDRESS 0xfd08 + + /* this error tells us that the address + specified as the destination is within + the source addresses */ +#define RANGE_OVERLAP 0xfd09 + + +#define ERROR 0xfd0a /* An error occured */ +#define INVALID_PARAM 0xfd0b /* "invalid input parameter " */ + + +#define INVALID_FLAG 0xfd0c /* invalid flag */ + +/*----------------------------------------------------------------------*/ +/* these are for the getarg toolbox */ + +#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */ +#define UNKNOWN_PARAMETER 0xFE01 /* "unknown type of parameter "*/ + + +/*----------------------------------------------------------------------*/ +/* these are for the tokenizer toolbox */ + +#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/ +#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */ +#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/ +#define INVALID_STRING 0xFF03 /* unable to extract string from input */ +#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */ +#define INVALID_MODE 0xFF05 /* input buf is in an unrecognized mode*/ +#define TOK_INTERNAL_ERROR 0xFF06 /* "internal tokenizer error" */ +#define TOO_MANY_IBS 0xFF07 /* "too many open input buffers" */ +#define NO_OPEN_IBS 0xFF08 /* "no open input buffers" */ + + +/* these are for the read from screen toolbox */ + +#define RESERVED_WORD 0xFC00 /* used a reserved word as an arguement*/ + + +/* these are for the breakpoint routines */ + +#define FULL_BPDS 0xFA00 /* breakpoint data structure is full */ + + +/* THESE are for the downloader */ + +#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */ +#define UNREC_RECORD_TYPE 0xf901 /* "unrecognized record type" */ +#define CONVERSION_ERROR 0xf902 /* "ascii to int conversion error" */ +#define INVALID_MEMORY 0xf903 /* "bad s-record memory address " */ + + +/* these are for the compression and decompression stuff */ + +#define COMP_UNK_CHARACTER 0xf800 /* "unknown compressed character " */ + +#define COMP_UNKNOWN_STATE 0xf801 /* "unknown binary state" */ + +#define NOT_IN_COMPRESSED_FORMAT 0xf802 /* not in compressed S-Record format */ + + +/* these are for the DUART handling things */ + + /* "unrecognized serial port configuration" */ +#define UNKNOWN_PORT_STATE 0xf700 + + +/* these are for the register toolbox */ + + /* "cannot find register in special + purpose register file " */ +#define SPR_NOT_FOUND 0xf600 + + +/* these are for the duart specific stuff */ + + /* "transparent mode needs access to + two serial ports" */ +#define TM_NEEDS_BOTH_PORTS 0xf500 + + +/*----------------------------------------------------------------------*/ +/* these are specifically for the flash routines */ +#define FLASH_ERROR 0xf100 /* general flash error */ diff --git a/cpu/mpc824x/drivers/i2c/i2c.c b/cpu/mpc824x/drivers/i2c/i2c.c new file mode 100644 index 0000000..3add687 --- /dev/null +++ b/cpu/mpc824x/drivers/i2c/i2c.c @@ -0,0 +1,284 @@ +/* + * (C) Copyright 2003 + * Gleb Natapov + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk + * + * Hardware I2C driver for MPC107 PCI bridge. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#undef I2CDBG + +#ifdef CONFIG_HARD_I2C +#include + +#define TIMEOUT (CFG_HZ/4) + +#define I2C_Addr ((unsigned *)(CFG_EUMB_ADDR + 0x3000)) + +#define I2CADR &I2C_Addr[0] +#define I2CFDR &I2C_Addr[1] +#define I2CCCR &I2C_Addr[2] +#define I2CCSR &I2C_Addr[3] +#define I2CCDR &I2C_Addr[4] + +#define MPC107_CCR_MEN 0x80 +#define MPC107_CCR_MIEN 0x40 +#define MPC107_CCR_MSTA 0x20 +#define MPC107_CCR_MTX 0x10 +#define MPC107_CCR_TXAK 0x08 +#define MPC107_CCR_RSTA 0x04 + +#define MPC107_CSR_MCF 0x80 +#define MPC107_CSR_MAAS 0x40 +#define MPC107_CSR_MBB 0x20 +#define MPC107_CSR_MAL 0x10 +#define MPC107_CSR_SRW 0x04 +#define MPC107_CSR_MIF 0x02 +#define MPC107_CSR_RXAK 0x01 + +#define I2C_READ 1 +#define I2C_WRITE 0 + +/* taken from linux include/asm-ppc/io.h */ +inline unsigned in_le32 (volatile unsigned *addr) +{ + unsigned ret; + + __asm__ __volatile__ ("lwbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync":"=r" (ret): "r" (addr), "m" (*addr)); + return ret; +} + +inline void out_le32 (volatile unsigned *addr, int val) +{ + __asm__ __volatile__ ("stwbrx %1,0,%2; eieio":"=m" (*addr):"r" (val), + "r" (addr)); +} + +#define writel(val, addr) out_le32(addr, val) +#define readl(addr) in_le32(addr) + +void i2c_init (int speed, int slaveadd) +{ + /* stop I2C controller */ + writel (0x0, I2CCCR); + /* set clock */ + writel (0x1020, I2CFDR); + /* write slave address */ + writel (slaveadd, I2CADR); + /* clear status register */ + writel (0x0, I2CCSR); + /* start I2C controller */ + writel (MPC107_CCR_MEN, I2CCCR); + + return; +} + +static __inline__ int i2c_wait4bus (void) +{ + ulong timeval = get_timer (0); + + while (readl (I2CCSR) & MPC107_CSR_MBB) + if (get_timer (timeval) > TIMEOUT) + return -1; + + return 0; +} + +static __inline__ int i2c_wait (int write) +{ + u32 csr; + ulong timeval = get_timer (0); + + do { + csr = readl (I2CCSR); + + if (!(csr & MPC107_CSR_MIF)) + continue; + + writel (0x0, I2CCSR); + + if (csr & MPC107_CSR_MAL) { +#ifdef I2CDBG + printf ("i2c_wait: MAL\n"); +#endif + return -1; + } + + if (!(csr & MPC107_CSR_MCF)) { +#ifdef I2CDBG + printf ("i2c_wait: unfinished\n"); +#endif + return -1; + } + + if (write == I2C_WRITE && (csr & MPC107_CSR_RXAK)) { +#ifdef I2CDBG + printf ("i2c_wait: No RXACK\n"); +#endif + return -1; + } + + return 0; + } while (get_timer (timeval) < TIMEOUT); + +#ifdef I2CDBG + printf ("i2c_wait: timed out\n"); +#endif + return -1; +} + +static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta) +{ + writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX | + (rsta ? MPC107_CCR_RSTA : 0), I2CCCR); + + writel ((dev << 1) | dir, I2CCDR); + + if (i2c_wait (I2C_WRITE) < 0) + return 0; + + return 1; +} + +static __inline__ int __i2c_write (u8 * data, int length) +{ + int i; + + writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX, I2CCCR); + + for (i = 0; i < length; i++) { + writel (data[i], I2CCDR); + + if (i2c_wait (I2C_WRITE) < 0) + break; + } + + return i; +} + +static __inline__ int __i2c_read (u8 * data, int length) +{ + int i; + + writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | + ((length == 1) ? MPC107_CCR_TXAK : 0), I2CCCR); + + /* dummy read */ + readl (I2CCDR); + + for (i = 0; i < length; i++) { + if (i2c_wait (I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | + MPC107_CCR_TXAK, I2CCCR); + + /* Generate stop on last byte */ + if (i == length - 1) + writel (MPC107_CCR_MEN | MPC107_CCR_TXAK, I2CCCR); + + data[i] = readl (I2CCDR); + } + + return i; +} + +int i2c_read (u8 dev, uint addr, int alen, u8 * data, int length) +{ + int i = 0; + u8 *a = (u8 *) & addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + if (i2c_write_addr (dev, I2C_READ, 1) == 0) + goto exit; + + i = __i2c_read (data, length); + +exit: + writel (MPC107_CCR_MEN, I2CCCR); + + return !(i == length); +} + +int i2c_write (u8 dev, uint addr, int alen, u8 * data, int length) +{ + int i = 0; + u8 *a = (u8 *) & addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + i = __i2c_write (data, length); + +exit: + writel (MPC107_CCR_MEN, I2CCCR); + + return !(i == length); +} + +int i2c_probe (uchar chip) +{ + int tmp; + + /* + * Try to read the first location of the chip. The underlying + * driver doesn't appear to support sending just the chip address + * and looking for an back. + */ + udelay (10000); + return i2c_read (chip, 0, 1, (uchar *) &tmp, 1); +} + +uchar i2c_reg_read (uchar i2c_addr, uchar reg) +{ + uchar buf[1]; + + i2c_read (i2c_addr, reg, 1, buf, 1); + + return (buf[0]); +} + +void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write (i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc824x/drivers/i2c_export.h b/cpu/mpc824x/drivers/i2c_export.h new file mode 100644 index 0000000..6264d18 --- /dev/null +++ b/cpu/mpc824x/drivers/i2c_export.h @@ -0,0 +1,103 @@ +#ifndef I2C_EXPORT_H +#define I2C_EXPORT_H + +/**************************************************** + * + * Copyright Motrola 1999 + * + ****************************************************/ + +/* These are the defined return values for the I2C_do_transaction function. + * Any non-zero value indicates failure. Failure modes can be added for + * more detailed error reporting. + */ +typedef enum _i2c_status +{ + I2C_SUCCESS = 0, + I2C_ERROR, +} I2C_Status; + +/* These are the defined tasks for I2C_do_transaction. + * Modes for SLAVE_RCV and SLAVE_XMIT will be added. + */ +typedef enum _i2c_transaction_mode +{ + I2C_MASTER_RCV = 0, + I2C_MASTER_XMIT = 1, +} I2C_TRANSACTION_MODE; + +typedef enum _i2c_interrupt_mode +{ + I2C_INT_DISABLE = 0, + I2C_INT_ENABLE = 1, +} I2C_INTERRUPT_MODE; + +typedef enum _i2c_stop +{ + I2C_NO_STOP = 0, + I2C_STOP = 1, +} I2C_STOP_MODE; + +typedef enum _i2c_restart +{ + I2C_NO_RESTART = 0, + I2C_RESTART = 1, +} I2C_RESTART_MODE; + +/******************** App. API ******************** + * The application API is for user level application + * to use the functionality provided by I2C driver. + * This is a "generic" I2C interface, it should contain + * nothing specific to the Kahlua implementation. + * Only the generic functions are exported by the library. + * + * Note: Its App.s responsibility to swap the data + * byte. In our API, we just transfer whatever + * we are given + **************************************************/ + + +/* Initialize I2C unit with the following: + * driver's slave address + * interrupt enabled + * optional pointer to application layer print function + * + * These parameters may be added: + * desired clock rate + * digital filter frequency sampling rate + * + * This function must be called before I2C unit can be used. + */ +extern I2C_Status I2C_Initialize( + unsigned char addr, /* driver's I2C slave address */ + I2C_INTERRUPT_MODE en_int, /* 1 - enable I2C interrupt + * 0 - disable I2C interrupt + */ + int (*app_print_function)(char *,...)); /* pointer to optional "printf" + * provided by application + */ + +/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV + * are implemented. Both are only in polling mode. + * + * en_int controls interrupt/polling mode + * act is the type of transaction + * addr is the I2C address of the slave device + * len is the length of data to send or receive + * buffer is the address of the data buffer + * stop = I2C_NO_STOP, don't signal STOP at end of transaction + * I2C_STOP, signal STOP at end of transaction + * retry is the timeout retry value, currently ignored + * rsta = I2C_NO_RESTART, this is not continuation of existing transaction + * I2C_RESTART, this is a continuation of existing transaction + */ +extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int, + I2C_TRANSACTION_MODE act, + unsigned char i2c_addr, + unsigned char data_addr, + int len, + char *buffer, + I2C_STOP_MODE stop, + int retry, + I2C_RESTART_MODE rsta); +#endif diff --git a/cpu/mpc824x/drivers/i2o.h b/cpu/mpc824x/drivers/i2o.h new file mode 100644 index 0000000..c47253d --- /dev/null +++ b/cpu/mpc824x/drivers/i2o.h @@ -0,0 +1,344 @@ +#ifndef I2O_H +#define I2O_H +/********************************************************* + * + * copyright @ Motorola, 1999 + *********************************************************/ + +#define I2O_REG_OFFSET 0x0004 + +#define PCI_CFG_CLA 0x0B +#define PCI_CFG_SCL 0x0A +#define PCI_CFG_PIC 0x09 + +#define I2O_IMR0 0x0050 +#define I2O_IMR1 0x0054 +#define I2O_OMR0 0x0058 +#define I2O_OMR1 0x005C + +#define I2O_ODBR 0x0060 +#define I2O_IDBR 0x0068 + +#define I2O_OMISR 0x0030 +#define I2O_OMIMR 0x0034 +#define I2O_IMISR 0x0100 +#define I2O_IMIMR 0x0104 + +/* accessable to PCI master but local processor */ +#define I2O_IFQPR 0x0040 +#define I2O_OFQPR 0x0044 + +/* accessable to local processor */ +#define I2O_IFHPR 0x0120 +#define I2O_IFTPR 0x0128 +#define I2O_IPHPR 0x0130 +#define I2O_IPTPR 0x0138 +#define I2O_OFHPR 0x0140 +#define I2O_OFTPR 0x0148 +#define I2O_OPHPR 0x0150 +#define I2O_OPTPR 0x0158 +#define I2O_MUCR 0x0164 +#define I2O_QBAR 0x0170 + +#define I2O_NUM_MSG 2 + +typedef enum _i2o_status +{ + I2OSUCCESS = 0, + I2OINVALID, + I2OMSGINVALID, + I2ODBINVALID, + I2OQUEINVALID, + I2OQUEEMPTY, + I2OQUEFULL, + I2ONOEVENT, +} I2OSTATUS; + +typedef enum _queue_size +{ + QSIZE_4K = 0x02, + QSIZE_8K = 0x04, + QSIZE_16K = 0x08, + QSIZE_32K = 0x10, + QSIZe_64K = 0x20, +} QUEUE_SIZE; + +typedef enum _location +{ + LOCAL = 0, /* used by local processor to access its own on board device, + local processor's eumbbar is required */ + REMOTE, /* used by PCI master to access the devices on its PCI device, + device's pcsrbar is required */ +} LOCATION; + +/* door bell */ +typedef enum _i2o_in_db +{ + IN_DB = 1, + MC, /* machine check */ +} I2O_IN_DB; + +/* I2O PCI configuration identification */ +typedef struct _i2o_iop +{ + unsigned int base_class : 8; + unsigned int sub_class : 8; + unsigned int prg_code : 8; +} I2OIOP; + +/* I2O Outbound Message Interrupt Status Register */ +typedef struct _i2o_om_stat +{ + unsigned int rsvd0 : 26; + unsigned int opqi : 1; + unsigned int rsvd1 : 1; + unsigned int odi : 1; + unsigned int rsvd2 : 1; + unsigned int om1i : 1; + unsigned int om0i : 1; +} I2OOMSTAT; + +/* I2O inbound Message Interrupt Status Register */ +typedef struct _i2o_im_stat +{ + unsigned int rsvd0 : 23; + unsigned int ofoi : 1; + unsigned int ipoi : 1; + unsigned int rsvd1 : 1; + unsigned int ipqi : 1; + unsigned int mci : 1; + unsigned int idi : 1; + unsigned int rsvd2 : 1; + unsigned int im1i : 1; + unsigned int im0i : 1; +} I2OIMSTAT; + +/** + Enable the interrupt associated with in/out bound msg + + Inbound message interrupt generated by PCI master and serviced by local processor + local processor needs to enable its inbound interrupts it wants to handle (LOCAL) + + Outbound message interrupt generated by local processor and serviced by PCI master + PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE) + **/ +extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ); /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ + +/** + Disable the interrupt associated with in/out bound msg + + local processor needs to disable its inbound interrupts it is not interested (LOCAL) + + PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE) + **/ +extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ); /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ + +/** + Read the msg register either from local inbound msg 0/1, + or an outbound msg 0/1 of devices. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, outbound msg of the device is read. + Otherwise local inbound msg is read. + **/ +extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int *msg ); + +/** + Write to nth Msg register either on local outbound msg 0/1, + or aninbound msg 0/1 of devices + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, inbound msg on the device is written. + Otherwise local outbound msg is written. + **/ +extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int msg ); + +/** + Enable the In/Out DoorBell Interrupt + + InDoorBell interrupt is generated by PCI master and serviced by local processor + local processor needs to enable its inbound doorbell interrupts it wants to handle + + OutDoorbell interrupt is generated by local processor and serviced by PCI master + PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle + **/ +extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ + +/** + Disable the In/Out DoorBell Interrupt + + local processor needs to disable its inbound doorbell interrupts it is not interested + + PCI master needs to disable outbound doorbell interrupts of devices it is not interested + + **/ +extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ + +/** + Read a local indoorbell register, or an outdoorbell of devices. + Reading a doorbell register, the register will be cleared. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, outdoorbell register on the device is read. + Otherwise local in doorbell is read + **/ +extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */ + unsigned int base); /* pcsrbar/eumbbar */ + +/** + Write to a local outdoorbell register, or an indoorbell register of devices. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, in doorbell register on the device is written. + Otherwise local out doorbell is written + **/ +extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int msg ); /* in / out */ + +/** + Read the outbound msg unit interrupt status of devices. Reading an interrupt status register, + the register will be cleared. + + The outbound interrupt status is AND with the outbound + interrupt mask. The result is returned. + + PCI master must pass the pcsrbar to the function. + **/ +extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * ); + +/** + Read the inbound msg unit interrupt status. Reading an interrupt status register, + the register will be cleared. + + The inbound interrupt status is AND with the inbound + interrupt mask. The result is returned. + + Local process must pass its eumbbar to the function. +**/ +extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * ); + +/** + Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR, + MUCR. + **/ +extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar, + QUEUE_SIZE, + unsigned int qba);/* queue base address that must be aligned at 1M */ +/** + Enable the circular queue + **/ +extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar ); + +/** + Disable the circular queue + **/ +extern void I2OFIFODisable( unsigned int eumbbar ); + +/** + Enable the circular queue interrupt + PCI master enables outbound FIFO interrupt of device + Device enables its inbound FIFO interrupt + **/ +extern void I2OFIFOIntEnable( LOCATION, unsigned int base ); + +/** + Disable the circular queue interrupt + PCI master disables outbound FIFO interrupt of device + Device disables its inbound FIFO interrupt + **/ +extern void I2OFIFOIntDisable( LOCATION, unsigned int base ); + +/** + Enable the circular queue overflow interrupt + **/ +extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar ); + +/** + Disable the circular queue overflow interrupt + **/ +extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar ); + +/** + Allocate a free msg frame from free FIFO. + + PCI Master allocates a free msg frame through inbound queue port of device(IFQPR) + while local processor allocates a free msg frame from outbound free queue(OFTPR) + + Unless both free queues are initialized, allocating a free MF will return 0xffffffff + **/ +extern I2OSTATUS I2OFIFOAlloc( LOCATION, + unsigned int base, + void **pMsg); +/** + Free a used msg frame back to free queue + PCI Master frees a MFA through outbound queue port of device(OFQPR) + while local processor frees a MFA into its inbound free queue(IFHPR) + + Used msg frame does not need to be recycled in the order they + read + + This function has to be called by PCI master to initialize Inbound free queue + and by device to initialize Outbound free queue before I2OFIFOAlloc can be used. + **/ +extern I2OSTATUS I2OFIFOFree( LOCATION, + unsigned int base, + void *pMsg ); + +/** + Post a msg into FIFO + PCI Master posts a msg through inbound queue port of device(IFQPR) + while local processor post a msg into its outbound post queue(OPHPR) + + The total number of msg must be less than the max size of the queue + Otherwise queue overflow interrupt will assert. + **/ +extern I2OSTATUS I2OFIFOPost( LOCATION, + unsigned int base, + void *pMsg ); + +/** + Read a msg from FIFO + PCI Master reads a msg through outbound queue port of device(OFQPR) + while local processor reads a msg from its inbound post queue(IPTPR) + **/ +extern I2OSTATUS I2OFIFOGet( LOCATION, + unsigned int base, + void **pMsg ); + +/** + Get the I2O PCI configuration identification register + **/ +extern I2OSTATUS I2OPCIConfigGet( LOCATION, + unsigned int base, + I2OIOP *); + +#endif diff --git a/cpu/mpc824x/drivers/i2o/Makefile b/cpu/mpc824x/drivers/i2o/Makefile new file mode 100644 index 0000000..3f5ca26 --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/Makefile @@ -0,0 +1,84 @@ +########################################################################## +# +# Copyright Motorola, Inc. 1997 +# ALL RIGHTS RESERVED +# +# You are hereby granted a copyright license to use, modify, and +# distribute the SOFTWARE so long as this entire notice is retained +# without alteration in any modified and/or redistributed versions, +# and that such modified versions are clearly identified as such. +# No licenses are granted by implication, estoppel or otherwise under +# any patents or trademarks of Motorola, Inc. +# +# The SOFTWARE is provided on an "AS IS" basis and without warranty. +# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS +# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR +# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH +# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS +# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. +# +# To the maximum extent permitted by applicable law, IN NO EVENT SHALL +# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF +# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR +# INABILITY TO USE THE SOFTWARE. +# +############################################################################ +TARGET = libi2o.a + +#DEBUG = -g +DEBUG = +LST = -Hanno -S +OPTIM = +CC = /risc/tools/pkgs/metaware/bin/hcppc +CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc +CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) +PREP = $(CC) $(CFLAGS) -P + +# Assembler used to build the .s files (for the board version) + +ASOPT = -big_si -c +ASDEBUG = -l -fm +AS = /risc/tools/pkgs/metaware/bin/asppc + +# Linker to bring .o files together into an executable. + +LKOPT = -Bbase=0 -Qn -q -r +LKCMD = +LINK = /risc/tools/pkgs/metaware/bin/ldppc $(LKCMD) $(LKOPT) + +# DOS Utilities + +DEL = rm +COPY = cp +LIST = ls + +OBJECTS = i2o1.o i2o2.o + +all: $(TARGET) + +$(TARGET): $(OBJECTS) + $(LINK) $(OBJECTS) -o $@ + +objects: i2o1.o + +clean: + $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) + +.s.o: + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i +# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst + +.c.o: + $(CCobj) $< + +.c.s: + $(CCobj) $(LST) $< + +i2o1.o: i2o.h i2o1.c + +i2o2.o: i2o.h i2o2.s diff --git a/cpu/mpc824x/drivers/i2o/Makefile_pc b/cpu/mpc824x/drivers/i2o/Makefile_pc new file mode 100644 index 0000000..6867f58 --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/Makefile_pc @@ -0,0 +1,90 @@ +########################################################################## +# +# makefile_pc for use with PC mksnt tools dink32/drivers/i2o +# +# Copyright Motorola, Inc. 1997 +# ALL RIGHTS RESERVED +# +# You are hereby granted a copyright license to use, modify, and +# distribute the SOFTWARE so long as this entire notice is retained +# without alteration in any modified and/or redistributed versions, +# and that such modified versions are clearly identified as such. +# No licenses are granted by implication, estoppel or otherwise under +# any patents or trademarks of Motorola, Inc. +# +# The SOFTWARE is provided on an "AS IS" basis and without warranty. +# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS +# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR +# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH +# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS +# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. +# +# To the maximum extent permitted by applicable law, IN NO EVENT SHALL +# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF +# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR +# INABILITY TO USE THE SOFTWARE. +# +############################################################################ +TARGET = libi2o.a + +#DEBUG = -g +DEBUG = +LST = -Hanno -S +OPTIM = +CC = m:/old_tools/tools/hcppc/bin/hcppc +CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc +CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) +PREP = $(CC) $(CFLAGS) -P + +# Assembler used to build the .s files (for the board version) + +ASOPT = -big_si -c +ASDEBUG = -l -fm +AS = m:/old_tools/tools/hcppc/bin/asppc + +# Linker to bring .o files together into an executable. + +LKOPT = -Bbase=0 -Qn -q -r +LKCMD = +LINK = m:/old_tools/tools/hcppc/bin/ldppc $(LKCMD) $(LKOPT) + +# DOS Utilities + +DEL = rm +COPY = cp +LIST = ls + +OBJECTS = i2o1.o i2o2.o + +all: $(TARGET) + +$(TARGET): $(OBJECTS) + $(LINK) $(OBJECTS) -o $@ + +objects: i2o1.o + +clean: + $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) + +.s.o: + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i +# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst + +.c.o: + $(CCobj) $< + +.c.s: + $(CCobj) $(LST) $< + +i2o1.o: i2o.h i2o1.c + $(CCobj) $< + +i2o2.o: i2o.h i2o2.s + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i diff --git a/cpu/mpc824x/drivers/i2o/i2o.h b/cpu/mpc824x/drivers/i2o/i2o.h new file mode 100644 index 0000000..71572b2 --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/i2o.h @@ -0,0 +1,345 @@ +#ifndef I2O_H +#define I2O_H +/********************************************************* + * + * copyright @ Motorola, 1999 + * + *********************************************************/ + +#define I2O_REG_OFFSET 0x0004 + +#define PCI_CFG_CLA 0x0B +#define PCI_CFG_SCL 0x0A +#define PCI_CFG_PIC 0x09 + +#define I2O_IMR0 0x0050 +#define I2O_IMR1 0x0054 +#define I2O_OMR0 0x0058 +#define I2O_OMR1 0x005C + +#define I2O_ODBR 0x0060 +#define I2O_IDBR 0x0068 + +#define I2O_OMISR 0x0030 +#define I2O_OMIMR 0x0034 +#define I2O_IMISR 0x0100 +#define I2O_IMIMR 0x0104 + +/* accessable to PCI master but local processor */ +#define I2O_IFQPR 0x0040 +#define I2O_OFQPR 0x0044 + +/* accessable to local processor */ +#define I2O_IFHPR 0x0120 +#define I2O_IFTPR 0x0128 +#define I2O_IPHPR 0x0130 +#define I2O_IPTPR 0x0138 +#define I2O_OFHPR 0x0140 +#define I2O_OFTPR 0x0148 +#define I2O_OPHPR 0x0150 +#define I2O_OPTPR 0x0158 +#define I2O_MUCR 0x0164 +#define I2O_QBAR 0x0170 + +#define I2O_NUM_MSG 2 + +typedef enum _i2o_status +{ + I2OSUCCESS = 0, + I2OINVALID, + I2OMSGINVALID, + I2ODBINVALID, + I2OQUEINVALID, + I2OQUEEMPTY, + I2OQUEFULL, + I2ONOEVENT, +} I2OSTATUS; + +typedef enum _queue_size +{ + QSIZE_4K = 0x02, + QSIZE_8K = 0x04, + QSIZE_16K = 0x08, + QSIZE_32K = 0x10, + QSIZe_64K = 0x20, +} QUEUE_SIZE; + +typedef enum _location +{ + LOCAL = 0, /* used by local processor to access its own on board device, + local processor's eumbbar is required */ + REMOTE, /* used by PCI master to access the devices on its PCI device, + device's pcsrbar is required */ +} LOCATION; + +/* door bell */ +typedef enum _i2o_in_db +{ + IN_DB = 1, + MC, /* machine check */ +} I2O_IN_DB; + +/* I2O PCI configuration identification */ +typedef struct _i2o_iop +{ + unsigned int base_class : 8; + unsigned int sub_class : 8; + unsigned int prg_code : 8; +} I2OIOP; + +/* I2O Outbound Message Interrupt Status Register */ +typedef struct _i2o_om_stat +{ + unsigned int rsvd0 : 26; + unsigned int opqi : 1; + unsigned int rsvd1 : 1; + unsigned int odi : 1; + unsigned int rsvd2 : 1; + unsigned int om1i : 1; + unsigned int om0i : 1; +} I2OOMSTAT; + +/* I2O inbound Message Interrupt Status Register */ +typedef struct _i2o_im_stat +{ + unsigned int rsvd0 : 23; + unsigned int ofoi : 1; + unsigned int ipoi : 1; + unsigned int rsvd1 : 1; + unsigned int ipqi : 1; + unsigned int mci : 1; + unsigned int idi : 1; + unsigned int rsvd2 : 1; + unsigned int im1i : 1; + unsigned int im0i : 1; +} I2OIMSTAT; + +/** + Enable the interrupt associated with in/out bound msg + + Inbound message interrupt generated by PCI master and serviced by local processor + local processor needs to enable its inbound interrupts it wants to handle (LOCAL) + + Outbound message interrupt generated by local processor and serviced by PCI master + PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE) + **/ +extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ); /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ + +/** + Disable the interrupt associated with in/out bound msg + + local processor needs to disable its inbound interrupts it is not interested (LOCAL) + + PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE) + **/ +extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ); /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ + +/** + Read the msg register either from local inbound msg 0/1, + or an outbound msg 0/1 of devices. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, outbound msg of the device is read. + Otherwise local inbound msg is read. + **/ +extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int *msg ); + +/** + Write to nth Msg register either on local outbound msg 0/1, + or aninbound msg 0/1 of devices + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, inbound msg on the device is written. + Otherwise local outbound msg is written. + **/ +extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int msg ); + +/** + Enable the In/Out DoorBell Interrupt + + InDoorBell interrupt is generated by PCI master and serviced by local processor + local processor needs to enable its inbound doorbell interrupts it wants to handle + + OutDoorbell interrupt is generated by local processor and serviced by PCI master + PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle + **/ +extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ + +/** + Disable the In/Out DoorBell Interrupt + + local processor needs to disable its inbound doorbell interrupts it is not interested + + PCI master needs to disable outbound doorbell interrupts of devices it is not interested + + **/ +extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ + +/** + Read a local indoorbell register, or an outdoorbell of devices. + Reading a doorbell register, the register will be cleared. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, outdoorbell register on the device is read. + Otherwise local in doorbell is read + **/ +extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */ + unsigned int base); /* pcsrbar/eumbbar */ + +/** + Write to a local outdoorbell register, or an indoorbell register of devices. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, in doorbell register on the device is written. + Otherwise local out doorbell is written + **/ +extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int msg ); /* in / out */ + +/** + Read the outbound msg unit interrupt status of devices. Reading an interrupt status register, + the register will be cleared. + + The outbound interrupt status is AND with the outbound + interrupt mask. The result is returned. + + PCI master must pass the pcsrbar to the function. + **/ +extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * ); + +/** + Read the inbound msg unit interrupt status. Reading an interrupt status register, + the register will be cleared. + + The inbound interrupt status is AND with the inbound + interrupt mask. The result is returned. + + Local process must pass its eumbbar to the function. +**/ +extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * ); + +/** + Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR, + MUCR. + **/ +extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar, + QUEUE_SIZE, + unsigned int qba);/* queue base address that must be aligned at 1M */ +/** + Enable the circular queue + **/ +extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar ); + +/** + Disable the circular queue + **/ +extern void I2OFIFODisable( unsigned int eumbbar ); + +/** + Enable the circular queue interrupt + PCI master enables outbound FIFO interrupt of device + Device enables its inbound FIFO interrupt + **/ +extern void I2OFIFOIntEnable( LOCATION, unsigned int base ); + +/** + Disable the circular queue interrupt + PCI master disables outbound FIFO interrupt of device + Device disables its inbound FIFO interrupt + **/ +extern void I2OFIFOIntDisable( LOCATION, unsigned int base ); + +/** + Enable the circular queue overflow interrupt + **/ +extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar ); + +/** + Disable the circular queue overflow interrupt + **/ +extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar ); + +/** + Allocate a free msg frame from free FIFO. + + PCI Master allocates a free msg frame through inbound queue port of device(IFQPR) + while local processor allocates a free msg frame from outbound free queue(OFTPR) + + Unless both free queues are initialized, allocating a free MF will return 0xffffffff + **/ +extern I2OSTATUS I2OFIFOAlloc( LOCATION, + unsigned int base, + void **pMsg); +/** + Free a used msg frame back to free queue + PCI Master frees a MFA through outbound queue port of device(OFQPR) + while local processor frees a MFA into its inbound free queue(IFHPR) + + Used msg frame does not need to be recycled in the order they + read + + This function has to be called by PCI master to initialize Inbound free queue + and by device to initialize Outbound free queue before I2OFIFOAlloc can be used. + **/ +extern I2OSTATUS I2OFIFOFree( LOCATION, + unsigned int base, + void *pMsg ); + +/** + Post a msg into FIFO + PCI Master posts a msg through inbound queue port of device(IFQPR) + while local processor post a msg into its outbound post queue(OPHPR) + + The total number of msg must be less than the max size of the queue + Otherwise queue overflow interrupt will assert. + **/ +extern I2OSTATUS I2OFIFOPost( LOCATION, + unsigned int base, + void *pMsg ); + +/** + Read a msg from FIFO + PCI Master reads a msg through outbound queue port of device(OFQPR) + while local processor reads a msg from its inbound post queue(IPTPR) + **/ +extern I2OSTATUS I2OFIFOGet( LOCATION, + unsigned int base, + void **pMsg ); + +/** + Get the I2O PCI configuration identification register + **/ +extern I2OSTATUS I2OPCIConfigGet( LOCATION, + unsigned int base, + I2OIOP *); + +#endif diff --git a/cpu/mpc824x/drivers/i2o/i2o1.c b/cpu/mpc824x/drivers/i2o/i2o1.c new file mode 100644 index 0000000..f058151 --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/i2o1.c @@ -0,0 +1,890 @@ +/********************************************************* + * $Id + * + * copyright @ Motorola, 1999 + *********************************************************/ +#include "i2o.h" + +extern unsigned int load_runtime_reg( unsigned int eumbbar, unsigned int reg ); +#pragma Alias( load_runtime_reg, "load_runtime_reg" ); + +extern void store_runtime_reg( unsigned int eumbbar, unsigned int reg, unsigned int val ); +#pragma Alias( store_runtime_reg, "store_runtime_reg" ); + +typedef struct _fifo_stat +{ + QUEUE_SIZE qsz; + unsigned int qba; +} FIFOSTAT; + +FIFOSTAT fifo_stat = { QSIZE_4K, 0xffffffff }; + +/********************************************************************************** + * function: I2OMsgEnable + * + * description: Enable the interrupt associated with in/out bound msg + * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID. + * + * All previously enabled interrupts are preserved. + * note: + * Inbound message interrupt generated by PCI master and serviced by local processor + * Outbound message interrupt generated by local processor and serviced by PCI master + * + * local processor needs to enable its inbound interrupts it wants to handle(LOCAL) + * PCI master needs to enable the outbound interrupts of devices it wants to handle(REMOTE) + ************************************************************************************/ +I2OSTATUS I2OMsgEnable ( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ) /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ +{ + unsigned int reg, val; + if ( ( n & 0x3 ) == 0 ) + { + /* neither msg 0, nor msg 1 */ + return I2OMSGINVALID; + } + + n = (~n) & 0x3; + /* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base + * LOCAL : enable local inbound message, eumbbar as base + */ + reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); + val = load_runtime_reg( base, reg ); + + val &= 0xfffffffc; /* masked out the msg interrupt bits */ + val |= n; /* LSB are the one we want */ + store_runtime_reg( base, reg, val ); + + return I2OSUCCESS; +} + +/********************************************************************************* + * function: I2OMsgDisable + * + * description: Disable the interrupt associated with in/out bound msg + * Other previously enabled interrupts are preserved. + * return I2OSUCCESS if no error otherwise return I2OMSGINVALID + * + * note: + * local processor needs to disable its inbound interrupts it is not interested(LOCAL) + * PCI master needs to disable outbound interrupts of devices it is not interested(REMOTE) + *********************************************************************************/ +I2OSTATUS I2OMsgDisable( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ) /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ +{ + unsigned int reg, val; + + if ( ( n & 0x3 ) == 0 ) + { + /* neither msg 0, nor msg 1 */ + return I2OMSGINVALID; + } + + /* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base + * LOCAL : disable local inbound message interrupt, eumbbar as base + */ + reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); + val = load_runtime_reg( base, reg ); + + val &= 0xfffffffc; /* masked out the msg interrupt bits */ + val |= ( n & 0x3 ); + store_runtime_reg( base, reg, val ); + + return I2OSUCCESS; + +} + +/************************************************************************** + * function: I2OMsgGet + * + * description: Local processor reads the nth Msg register from its inbound msg, + * or a PCI Master reads nth outbound msg from device + * + * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID. + * + * note: + * If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed. + * If it is remote, outbound msg on the device is read; otherwise local inbound msg is read + *************************************************************************/ +I2OSTATUS I2OMsgGet ( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int *msg ) +{ + if ( n >= I2O_NUM_MSG || msg == 0 ) + { + return I2OMSGINVALID; + } + + if ( loc == REMOTE ) + { + /* read the outbound msg of the device, pcsrbar as base */ + *msg = load_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET ); + } + else + { + /* read the inbound msg sent by PCI master, eumbbar as base */ + *msg = load_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET ); + } + + return I2OSUCCESS; +} + +/*************************************************************** + * function: I2OMsgPost + * + * description: Kahlua writes to its nth outbound msg register + * PCI master writes to nth inbound msg register of device + * + * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID. + * + * note: + * If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed. + * + * If it is remote, inbound msg on the device is written; otherwise local outbound msg is written + ***************************************************************/ +I2OSTATUS I2OMsgPost( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int msg ) +{ + if ( n >= I2O_NUM_MSG ) + { + return I2OMSGINVALID; + } + + if ( loc == REMOTE ) + { + /* write to the inbound msg register of the device, pcsrbar as base */ + store_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET, msg ); + } + else + { + /* write to the outbound msg register for PCI master to read, eumbbar as base */ + store_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET, msg ); + } + + return I2OSUCCESS; +} + +/*********************************************************************** + * function: I2ODBEnable + * + * description: Local processor enables it's inbound doorbell interrupt + * PCI master enables outbound doorbell interrupt of devices + * Other previously enabled interrupts are preserved. + * Return I2OSUCCESS if no error otherwise return I2ODBINVALID + * + * note: + * In DoorBell interrupt is generated by PCI master and serviced by local processor + * Out Doorbell interrupt is generated by local processor and serviced by PCI master + * + * Out Doorbell interrupt is generated by local processor and serviced by PCI master + * PCI master needs to enable the outbound doorbell interrupts of device it wants to handle + **********************************************************************/ +I2OSTATUS I2ODBEnable( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ +{ + + /* LOCATION - REMOTE : PCI master initializes outbound doorbell message of device + * LOCAL : Kahlua initializes its inbound doorbell message + */ + unsigned int val; + + if ( loc == LOCAL && ( in_db & 0x3 ) == 0 ) + { + return I2ODBINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is base */ + val = load_runtime_reg( base, I2O_OMIMR ); + val &= 0xfffffff7; + store_runtime_reg( base, I2O_OMIMR , val ); + } + else + { + /* eumbbar is base */ + val = load_runtime_reg( base, I2O_IMIMR); + in_db = ( (~in_db) & 0x3 ) << 3; + val = ( val & 0xffffffe7) | in_db; + store_runtime_reg( base, I2O_IMIMR, val ); + } + + return I2OSUCCESS; +} + +/********************************************************************************** + * function: I2ODBDisable + * + * description: local processor disables its inbound DoorBell Interrupt + * PCI master disables outbound DoorBell interrupt of device + * Other previously enabled interrupts are preserved. + * return I2OSUCCESS if no error.Otherwise return I2ODBINVALID + * + * note: + * local processor needs to disable its inbound doorbell interrupts it is not interested + * + * PCI master needs to disable outbound doorbell interrupts of device it is not interested + ************************************************************************************/ +I2OSTATUS I2ODBDisable( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ +{ + /* LOCATION - REMOTE : handle device's out bound message initialization + * LOCAL : handle local in bound message initialization + */ + unsigned int val; + + if ( loc == LOCAL && ( in_db & 0x3 ) == 0 ) + { + return I2ODBINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base */ + val = load_runtime_reg( base, I2O_OMIMR ); + val |= 0x8; + store_runtime_reg( base, I2O_OMIMR, val ); + } + else + { + val = load_runtime_reg( base, I2O_IMIMR); + in_db = ( in_db & 0x3 ) << 3; + val |= in_db; + store_runtime_reg( base, I2O_IMIMR, val ); + } + + return I2OSUCCESS; +} + +/********************************************************************************** + * function: I2ODBGet + * + * description: Local processor reads its in doorbell register, + * PCI master reads the outdoorbell register of device. + * After a doorbell register is read, the whole register will be cleared. + * Otherwise, HW keeps generating interrupt. + * + * note: + * If it is not local, pcsrbar must be passed to the function. + * Otherwise eumbbar is passed. + * + * If it is remote, out doorbell register on the device is read. + * Otherwise local in doorbell is read + * + * If the register is not cleared by write to it, any remaining bit of b'1's + * will cause interrupt pending. + *********************************************************************************/ +unsigned int I2ODBGet( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base) /* pcsrbar/eumbbar */ +{ + unsigned int msg, val; + + if ( loc == REMOTE ) + { + /* read outbound doorbell register of device, pcsrbar is the base */ + val = load_runtime_reg( base, I2O_ODBR ); + msg = val & 0xe0000000; + store_runtime_reg( base, I2O_ODBR, val ); /* clear the register */ + } + else + { + /* read the inbound doorbell register, eumbbar is the base */ + val = load_runtime_reg( base, I2O_IDBR ); + store_runtime_reg( base, I2O_IDBR, val ); /* clear the register */ + msg = val; + } + + return msg; +} + +/********************************************************************** + * function: I2ODBPost + * + * description: local processor writes to a outbound doorbell register, + * PCI master writes to the inbound doorbell register of device + * + * note: + * If it is not local, pcsrbar must be passed to the function. + * Otherwise eumbbar is passed. + * + * If it is remote, in doorbell register on the device is written. + * Otherwise local out doorbell is written + *********************************************************************/ +void I2ODBPost( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int msg ) /* in / out */ +{ + if ( loc == REMOTE ) + { + /* write to inbound doorbell register of device, pcsrbar is the base */ + store_runtime_reg( base, I2O_IDBR, msg ); + } + else + { + /* write to local outbound doorbell register, eumbbar is the base */ + store_runtime_reg( base, I2O_ODBR, msg & 0x1fffffff ); + } + +} + +/******************************************************************** + * function: I2OOutMsgStatGet + * + * description: PCI master reads device's outbound msg unit interrupt status. + * Reading an interrupt status register, + * the register will be cleared. + * + * The value of the status register is AND with the outbound + * interrupt mask and result is returned. + * + * note: + * pcsrbar must be passed to the function. + ********************************************************************/ +I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT *val ) +{ + unsigned int stat; + unsigned int mask; + + if ( val == 0 ) + { + return I2OINVALID; + } + + /* read device's outbound status */ + stat = load_runtime_reg( pcsrbar, I2O_OMISR ); + mask = load_runtime_reg( pcsrbar, I2O_OMIMR ); + store_runtime_reg( pcsrbar, I2O_OMISR, stat & 0xffffffd7); + + stat &= mask; + val->rsvd0 = ( stat & 0xffffffc0 ) >> 6; + val->opqi = ( stat & 0x00000020 ) >> 5; + val->rsvd1 = ( stat & 0x00000010 ) >> 4; + val->odi = ( stat & 0x00000008 ) >> 3; + val->rsvd2 = ( stat & 0x00000004 ) >> 2; + val->om1i = ( stat & 0x00000002 ) >> 1; + val->om0i = ( stat & 0x00000001 ); + + return I2OSUCCESS; +} + +/******************************************************************** + * function: I2OInMsgStatGet + * + * description: Local processor reads its inbound msg unit interrupt status. + * Reading an interrupt status register, + * the register will be cleared. + * + * The inbound msg interrupt status is AND with the inbound + * msg interrupt mask and result is returned. + * + * note: + * eumbbar must be passed to the function. + ********************************************************************/ +I2OSTATUS I2OInMsgStatGet(unsigned int eumbbar, I2OIMSTAT *val) +{ + unsigned int stat; + unsigned int mask; + + if ( val == 0 ) + { + return I2OINVALID; + } + + /* read device's outbound status */ + stat = load_runtime_reg( eumbbar, I2O_OMISR ); + mask = load_runtime_reg( eumbbar, I2O_OMIMR ); + store_runtime_reg( eumbbar, I2O_OMISR, stat & 0xffffffe7 ); + + stat &= mask; + val->rsvd0 = ( stat & 0xfffffe00 ) >> 9; + val->ofoi = ( stat & 0x00000100 ) >> 8; + val->ipoi = ( stat & 0x00000080 ) >> 7; + val->rsvd1 = ( stat & 0x00000040 ) >> 6; + val->ipqi = ( stat & 0x00000020 ) >> 5; + val->mci = ( stat & 0x00000010 ) >> 4; + val->idi = ( stat & 0x00000008 ) >> 3; + val->rsvd2 = ( stat & 0x00000004 ) >> 2; + val->im1i = ( stat & 0x00000002 ) >> 1; + val->im0i = ( stat & 0x00000001 ); + + return I2OSUCCESS; + +} + +/*********************************************************** + * function: I2OFIFOInit + * + * description: Configure the I2O FIFO, including QBAR, + * IFHPR/IFTPR, IPHPR/IPTPR, OFHPR/OFTPR, + * OPHPR/OPTPR, MUCR. + * + * return I2OSUCCESS if no error, + * otherwise return I2OQUEINVALID + * + * note: It is NOT this driver's responsibility of initializing + * MFA blocks, i.e., FIFO queue itself. The MFA blocks + * must be initialized before I2O unit can be used. + ***********************************************************/ +I2OSTATUS I2OFIFOInit( unsigned int eumbbar, + QUEUE_SIZE sz, /* value of CQS of MUCR */ + unsigned int qba) /* queue base address that must be aligned at 1M */ +{ + + if ( ( qba & 0xfffff ) != 0 ) + { + /* QBA must be aligned at 1Mbyte boundary */ + return I2OQUEINVALID; + } + + store_runtime_reg( eumbbar, I2O_QBAR, qba ); + store_runtime_reg( eumbbar, I2O_MUCR, (unsigned int)sz ); + store_runtime_reg( eumbbar, I2O_IFHPR, qba ); + store_runtime_reg( eumbbar, I2O_IFTPR, qba ); + store_runtime_reg( eumbbar, I2O_IPHPR, qba + 1 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_IPTPR, qba + 1 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_OFHPR, qba + 2 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_OFTPR, qba + 2 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_OPHPR, qba + 3 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_OPTPR, qba + 3 * ( sz << 11 )); + + fifo_stat.qsz = sz; + fifo_stat.qba = qba; + + return I2OSUCCESS; +} + +/************************************************** + * function: I2OFIFOEnable + * + * description: Enable the circular queue + * return I2OSUCCESS if no error. + * Otherwise I2OQUEINVALID is returned. + * + * note: + *************************************************/ +I2OSTATUS I2OFIFOEnable( unsigned int eumbbar ) +{ + unsigned int val; + + if ( fifo_stat.qba == 0xfffffff ) + { + return I2OQUEINVALID; + } + + val = load_runtime_reg( eumbbar, I2O_MUCR ); + store_runtime_reg( eumbbar, I2O_MUCR, val | 0x1 ); + + return I2OSUCCESS; +} + +/************************************************** + * function: I2OFIFODisable + * + * description: Disable the circular queue + * + * note: + *************************************************/ +void I2OFIFODisable( unsigned int eumbbar ) +{ + if ( fifo_stat.qba == 0xffffffff ) + { + /* not enabled */ + return; + } + + unsigned int val = load_runtime_reg( eumbbar, I2O_MUCR ); + store_runtime_reg( eumbbar, I2O_MUCR, val & 0xfffffffe ); +} + +/**************************************************** + * function: I2OFIFOAlloc + * + * description: Allocate a free MFA from free FIFO. + * return I2OSUCCESS if no error. + * return I2OQUEEMPTY if no more free MFA. + * return I2OINVALID on other errors. + * + * A free MFA must be allocated before a + * message can be posted. + * + * note: + * PCI Master allocates a free MFA from inbound queue of device + * (pcsrbar is the base,) through the inbound queue port of device + * while local processor allocates a free MFA from its outbound + * queue (eumbbar is the base.) + * + ****************************************************/ +I2OSTATUS I2OFIFOAlloc( LOCATION loc, + unsigned int base, + void **pMsg ) +{ + I2OSTATUS stat = I2OSUCCESS; + void *pHdr, *pTil; + + if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff ) + { + /* not configured */ + return I2OQUEINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base and read the inbound free tail ptr */ + pTil = (void *)load_runtime_reg( base, I2O_IFQPR ); + if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF ) + { + stat = I2OQUEEMPTY; + } + else + { + *pMsg = pTil; + } + } + else + { + /* eumbbar is the base and read the outbound free tail ptr */ + pHdr = (void *)load_runtime_reg( base, I2O_OFHPR ); /* queue head */ + pTil = (void *)load_runtime_reg( base, I2O_OFTPR ); /* queue tail */ + + /* check underflow */ + if ( pHdr == pTil ) + { + /* hdr and til point to the same fifo item, no free MFA */ + stat = I2OQUEEMPTY; + } + else + { + /* update OFTPR */ + *pMsg = (void *)(*(unsigned char *)pTil); + pTil = (void *)((unsigned int)pTil + 4); + if ( (unsigned int)pTil == fifo_stat.qba + ( 4 * ( fifo_stat.qsz << 11 ) ) ) + { + /* reach the upper limit */ + pTil = (void *)(fifo_stat.qba + ( 3 * (fifo_stat.qsz << 11) )); + } + store_runtime_reg( base, I2O_OFTPR, (unsigned int)pTil ); + } + } + + return stat; +} + +/****************************************************** + * function: I2OFIFOFree + * + * description: Free a used MFA back to free queue after + * use. + * return I2OSUCCESS if no error. + * return I2OQUEFULL if inbound free queue + * overflow + * + * note: PCI Master frees a MFA into device's outbound queue + * (OFQPR) while local processor frees a MFA into its + * inbound queue (IFHPR). + *****************************************************/ +I2OSTATUS I2OFIFOFree( LOCATION loc, + unsigned int base, + void *pMsg ) +{ + void **pHdr, **pTil; + I2OSTATUS stat = I2OSUCCESS; + + if ( fifo_stat.qba == 0xffffffff || pMsg == 0 ) + { + return I2OQUEINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base */ + store_runtime_reg( base, I2O_OFQPR, (unsigned int)pMsg ); + } + else + { + /* eumbbar is the base */ + pHdr = (void **)load_runtime_reg( base, I2O_IFHPR ); + pTil = (void **)load_runtime_reg( base, I2O_IFTPR ); + + /* store MFA */ + *pHdr = pMsg; + + /* update IFHPR */ + pHdr += 4; + + if ( (unsigned int)pHdr == fifo_stat.qba + ( fifo_stat.qsz << 11 ) ) + { + /* reach the upper limit */ + pHdr = (void **)fifo_stat.qba; + } + + /* check inbound free queue overflow */ + if ( pHdr != pTil ) + { + store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr); + } + else + { + stat = I2OQUEFULL; + } + + } + + return stat; + +} + +/********************************************* + * function: I2OFIFOPost + * + * description: Post a msg into FIFO post queue + * the value of msg must be the one + * returned by I2OFIFOAlloc + * + * note: PCI Master posts a msg into device's inbound queue + * (IFQPR) while local processor post a msg into device's + * outbound queue (OPHPR) + *********************************************/ +I2OSTATUS I2OFIFOPost( LOCATION loc, + unsigned int base, + void *pMsg ) +{ + void **pHdr, **pTil; + I2OSTATUS stat = I2OSUCCESS; + + if ( fifo_stat.qba == 0xffffffff || pMsg == 0 ) + { + return I2OQUEINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base */ + store_runtime_reg( base, I2O_IFQPR, (unsigned int)pMsg ); + } + else + { + /* eumbbar is the base */ + pHdr = (void **)load_runtime_reg( base, I2O_OPHPR ); + pTil = (void **)load_runtime_reg( base, I2O_OPTPR ); + + /* store MFA */ + *pHdr = pMsg; + + /* update IFHPR */ + pHdr += 4; + + if ( (unsigned int)pHdr == fifo_stat.qba + 3 * ( fifo_stat.qsz << 11 ) ) + { + /* reach the upper limit */ + pHdr = (void **)(fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) ); + } + + /* check post queue overflow */ + if ( pHdr != pTil ) + { + store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr); + } + else + { + stat = I2OQUEFULL; + } + } + + return stat; +} + +/************************************************ + * function: I2OFIFOGet + * + * description: Read a msg from FIFO + * This function should be called + * only when there is a corresponding + * msg interrupt. + * + * note: PCI Master reads a msg from device's outbound queue + * (OFQPR) while local processor reads a msg from device's + * inbound queue (IPTPR) + ************************************************/ +I2OSTATUS I2OFIFOGet( LOCATION loc, + unsigned int base, + void **pMsg ) +{ + I2OSTATUS stat = I2OSUCCESS; + void *pHdr, *pTil; + + if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff ) + { + /* not configured */ + return I2OQUEINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base */ + pTil = (void *)load_runtime_reg( base, I2O_OFQPR ); + if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF ) + { + stat = I2OQUEEMPTY; + } + else + { + *pMsg = pTil; + } + } + else + { + /* eumbbar is the base and read the outbound free tail ptr */ + pHdr = (void *)load_runtime_reg( base, I2O_IPHPR ); /* queue head */ + pTil = (void *)load_runtime_reg( base, I2O_IPTPR ); /* queue tail */ + + /* check underflow */ + if ( pHdr == pTil ) + { + /* no free MFA */ + stat = I2OQUEEMPTY; + } + else + { + /* update OFTPR */ + *pMsg = (void *)(*(unsigned char *)pTil); + pTil = (void *)((unsigned int)pTil + 4); + if ( (unsigned int)pTil == fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) ) + { + /* reach the upper limit */ + pTil = (void *)(fifo_stat.qba + 1 * (fifo_stat.qsz << 11) ); + } + + store_runtime_reg( base, I2O_IPTPR, (unsigned int)pTil ); + } + } + + return stat; +} + +/******************************************************** + * function: I2OIOP + * + * description: Get the I2O PCI configuration identification + * register. + * + * note: PCI master should pass pcsrbar while local processor + * should pass eumbbar. + *********************************************************/ +I2OSTATUS I2OPCIConfigGet( LOCATION loc, + unsigned int base, + I2OIOP * val) +{ + unsigned int tmp; + if ( val == 0 ) + { + return I2OINVALID; + } + tmp = load_runtime_reg( base, PCI_CFG_CLA ); + val->base_class = ( tmp & 0xFF) << 16; + tmp = load_runtime_reg( base, PCI_CFG_SCL ); + val->sub_class= ( (tmp & 0xFF) << 8 ); + tmp = load_runtime_reg( base, PCI_CFG_PIC ); + val->prg_code = (tmp & 0xFF); + return I2OSUCCESS; +} + +/********************************************************* + * function: I2OFIFOIntEnable + * + * description: Enable the circular post queue interrupt + * + * note: + * PCI master enables outbound FIFO interrupt of device + * pscrbar is the base + * Device enables its inbound FIFO interrupt + * eumbbar is the base + *******************************************************/ +void I2OFIFOIntEnable( LOCATION loc, unsigned int base ) +{ + unsigned int reg, val; + + /* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base + * LOCAL : enable local inbound message, eumbbar as base + */ + reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); + val = load_runtime_reg( base, reg ); + + val &= 0xffffffdf; /* clear the msg interrupt bits */ + store_runtime_reg( base, reg, val ); + +} + +/**************************************************** + * function: I2OFIFOIntDisable + * + * description: Disable the circular post queue interrupt + * + * note: + * PCI master disables outbound FIFO interrupt of device + * (pscrbar is the base) + * Device disables its inbound FIFO interrupt + * (eumbbar is the base) + *****************************************************/ +void I2OFIFOIntDisable( LOCATION loc, unsigned int base ) +{ + + /* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base + * LOCAL : disable local inbound message interrupt, eumbbar as base + */ + unsigned int reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); + unsigned int val = load_runtime_reg( base, reg ); + + val |= 0x00000020; /* masked out the msg interrupt bits */ + store_runtime_reg( base, reg, val ); + +} + +/********************************************************* + * function: I2OFIFOOverflowIntEnable + * + * description: Enable the circular queue overflow interrupt + * + * note: + * Device enables its inbound FIFO post overflow interrupt + * and outbound free overflow interrupt. + * eumbbar is the base + *******************************************************/ +void I2OFIFOOverflowIntEnable( unsigned int eumbbar ) +{ + unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR ); + + val &= 0xfffffe7f; /* clear the two overflow interrupt bits */ + store_runtime_reg( eumbbar, I2O_IMIMR, val ); + +} + +/**************************************************** + * function: I2OFIFOOverflowIntDisable + * + * description: Disable the circular queue overflow interrupt + * + * note: + * Device disables its inbound post FIFO overflow interrupt + * and outbound free FIFO overflow interrupt + * (eumbbar is the base) + *****************************************************/ +void I2OFIFOOverflowIntDisable( unsigned int eumbbar ) +{ + + unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR ); + + val |= 0x00000180; /* masked out the msg overflow interrupt bits */ + store_runtime_reg( eumbbar, I2O_IMIMR, val ); +} diff --git a/cpu/mpc824x/drivers/i2o/i2o2.S b/cpu/mpc824x/drivers/i2o/i2o2.S new file mode 100644 index 0000000..990f9ef --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/i2o2.S @@ -0,0 +1,47 @@ +/************************************** + * + * copyright @ Motorola, 1999 + * + **************************************/ + +/********************************************************** + * function: load_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * + * output: r3 - register content + **********************************************************/ + .text + .align 2 + .global load_runtime_reg + +load_runtime_reg: + + xor r5,r5,r5 + or r5,r5,r3 /* save eumbbar */ + + lwbrx r3,r4,r5 + sync + + bclr 20, 0 + +/**************************************************************** + * function: store_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * r5 - new value to be stored + * + ****************************************************************/ + .text + .align 2 + .global store_runtime_reg +store_runtime_reg: + + xor r0,r0,r0 + + stwbrx r5, r4, r3 + sync + + bclr 20,0 diff --git a/cpu/mpc824x/interrupts.c b/cpu/mpc824x/interrupts.c new file mode 100644 index 0000000..acb8947 --- /dev/null +++ b/cpu/mpc824x/interrupts.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include "drivers/epic.h" + +int interrupt_init_cpu (unsigned *decrementer_count) +{ + *decrementer_count = (get_bus_freq (0) / 4) / CFG_HZ; + + /* + * It's all broken at the moment and I currently don't need + * interrupts. If you want to fix it, have a look at the epic + * drivers in dink32 v12. They do everthing and Motorola said + * I could use the dink source in this project as long as + * copyright notices remain intact. + */ + + epicInit (EPIC_DIRECT_IRQ, 0); + /* EPIC won't generate INT unless Current Task Pri < 15 */ + epicCurTaskPrioSet(0); + + return (0); +} + +/****************************************************************************/ + +/* + * Handle external interrupts + */ +void external_interrupt (struct pt_regs *regs) +{ + register unsigned long temp; + + pci_readl (CFG_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp); + sync (); /* i'm not convinced this is needed, but dink source has it */ + temp &= 0xff; /*get vector */ + + /*TODO: handle them -... */ + epicEOI (); +} + +/****************************************************************************/ + +/* + * blank int handlers. + */ + +void +irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) +{ +} + +void irq_free_handler (int vec) +{ + +} + +/*TODO: some handlers for winbond and 87308 interrupts + and what about generic pci inteerupts? + vga? + */ + +void timer_interrupt_cpu (struct pt_regs *regs, ulong timestamp) +{ + /* nothing to do here */ + return; +} diff --git a/cpu/mpc824x/pci.c b/cpu/mpc824x/pci.c new file mode 100644 index 0000000..7e3c4c3 --- /dev/null +++ b/cpu/mpc824x/pci.c @@ -0,0 +1,78 @@ +/* + * arch/ppc/kernel/mpc10x_common.c + * + * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge, + * Mem ctlr, EPIC, etc. + * + * Author: Mark A. Greer + * mgreer@mvista.com + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include + +void pci_mpc824x_init (struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ + pci_set_region(hose->regions + 0, + CHRP_PCI_MEMORY_BUS, + CHRP_PCI_MEMORY_PHYS, + CHRP_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CHRP_PCI_MEM_BUS, + CHRP_PCI_MEM_PHYS, + CHRP_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 2, + CHRP_ISA_MEM_BUS, + CHRP_ISA_MEM_PHYS, + CHRP_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 3, + CHRP_PCI_IO_BUS, + CHRP_PCI_IO_PHYS, + CHRP_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 4, + CHRP_ISA_IO_BUS, + CHRP_ISA_IO_PHYS, + CHRP_ISA_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 5; + + pci_setup_indirect(hose, + CHRP_REG_ADDR, + CHRP_REG_DATA); + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); +} + +#endif diff --git a/cpu/mpc824x/speed.c b/cpu/mpc824x/speed.c new file mode 100644 index 0000000..a37a087 --- /dev/null +++ b/cpu/mpc824x/speed.c @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Gregory E. Allen, gallen@arlut.utexas.edu + * Applied Research Laboratories, The University of Texas at Austin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ +/* NOTE: This describes the proper use of this file. + * + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency on + * PCI_SYNC_IN . + * + * CONFIG_PLL_PCI_TO_MEM_MULTIPLIER is only required on MPC8240 + * boards. It should be defined as the PCI to Memory Multiplier as + * documented in the MPC8240 Hardware Specs. + * + * Other mpc824x boards don't need CONFIG_PLL_PCI_TO_MEM_MULTIPLIER + * because they can determine it from the PCR. + * + * Gary Milliorn (who should know since + * he designed the Sandpoint) told us that the PCR is not in all revs + * of the MPC8240 CPU, so it's not guaranteeable and we cannot do + * away with CONFIG_PLL_PCI_TO_MEM_MULTIPLIER altogether. + */ +/* ------------------------------------------------------------------------- */ + +/* This gives the PCI to Memory multiplier times 10 */ +/* The index is the value of PLL_CFG[0:4] */ +/* This is documented in the MPC8240/5 Hardware Specs */ + +short pll_pci_to_mem_multiplier[] = { +#if defined(CONFIG_MPC8240) + 30, 30, 10, 10, 20, 10, 0, 10, + 10, 0, 20, 0, 20, 0, 20, 0, + 30, 0, 15, 0, 20, 0, 20, 0, + 25, 0, 10, 0, 15, 15, 0, 0, +#elif defined(CONFIG_MPC8245) + 30, 30, 10, 10, 20, 10, 10, 10, + 10, 20, 20, 15, 20, 15, 20, 30, + 30, 40, 15, 40, 20, 25, 20, 40, + 25, 20, 10, 20, 15, 15, 15, 0, +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif +}; + +#define CU824_PLL_STATE_REG 0xFE80002F +#define PCR 0x800000E2 + +/* ------------------------------------------------------------------------- */ + +/* compute the memory bus clock frequency */ +ulong get_bus_freq (ulong dummy) +{ + unsigned char pll_cfg; +#if defined(CONFIG_MPC8240) && !defined(CONFIG_CU824) + return (CONFIG_SYS_CLK_FREQ) * (CONFIG_PLL_PCI_TO_MEM_MULTIPLIER); +#elif defined(CONFIG_CU824) + pll_cfg = *(volatile unsigned char *) (CU824_PLL_STATE_REG); + pll_cfg &= 0x1f; +#else + CONFIG_READ_BYTE(PCR, pll_cfg); + pll_cfg = (pll_cfg >> 3) & 0x1f; +#endif + return ((CONFIG_SYS_CLK_FREQ) * pll_pci_to_mem_multiplier[pll_cfg] + 5) / 10; +} + + +/* ------------------------------------------------------------------------- */ + +/* This gives the Memory to CPU Core multiplier times 10 */ +/* The index is the value of PLLRATIO in HID1 */ +/* This is documented in the MPC8240 Hardware Specs */ +/* This is not documented for MPC8245 ? FIXME */ +short pllratio_to_factor[] = { + 0, 0, 0, 10, 20, 20, 25, 45, + 30, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 10, 0, 0, 0, 45, + 30, 0, 40, 0, 0, 0, 35, 0, +}; + +/* compute the CPU and memory bus clock frequencies */ +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uint hid1 = mfspr(HID1); + hid1 = (hid1 >> (32-5)) & 0x1f; + gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5) + / 10; + gd->bus_clk = get_bus_freq(0); + return (0); +} diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S new file mode 100644 index 0000000..9ff052c --- /dev/null +++ b/cpu/mpc824x/start.S @@ -0,0 +1,789 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000,2001,2002 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* U-Boot - Startup Code for PowerPC based Embedded Boards + * + * + * The processor starts at 0x00000100 and the code is executed + * from flash. The code is organized to be at an other address + * in memory, but as long we don't jump around before relocating. + * board_init lies at a quite high address and when the cpu has + * jumped there, everything is ok. + * This works because the cpu gives the FLASH (CS0) the whole + * address space at startup, and board_init lies as a echo of + * the flash somewhere up there in the memorymap. + * + * board_init will change CS0 to be positioned at the correct + * address and (s)dram will be positioned at address 0 + */ +#include +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +/* FP, Machine Check and Recoverable Interr. */ +#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI ) + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) +#if defined(CONFIG_FADS) + GOT_ENTRY(environment) +#endif + END_GOT + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ + b boot_cold + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + +boot_cold: +boot_warm: + + /* Initialize machine status; enable machine check interrupt */ + /*----------------------------------------------------------------------*/ + li r3, MSR_KERNEL /* Set FP, ME, RI flags */ + mtmsr r3 + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + addis r0,0,0x0000 /* lets make sure that r0 is really 0 */ + mtspr HID0, r0 /* disable I and D caches */ + + mfspr r3, ICR /* clear Interrupt Cause Register */ + + mfmsr r3 /* turn off address translation */ + addis r4,0,0xffff + ori r4,r4,0xffcf + and r3,r3,r4 + mtmsr r3 + isync + sync /* the MMU should be off... */ + + +in_flash: +#if defined(CONFIG_BMW) + bl early_init_f /* Must be ASM: no stack yet! */ +#endif + /* + * Setup BATs - cannot be done in C since we don't have a stack yet + */ + bl setup_bats + + /* Enable MMU. + */ + mfmsr r3 + ori r3, r3, (MSR_IR | MSR_DR) + mtmsr r3 +#if !defined(CONFIG_BMW) + /* Enable and invalidate data cache. + */ + mfspr r3, HID0 + mr r2, r3 + ori r3, r3, HID0_DCE | HID0_DCI + ori r2, r2, HID0_DCE + sync + mtspr HID0, r3 + mtspr HID0, r2 + sync + + /* Allocate Initial RAM in data cache. + */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + li r2, 128 + mtctr r2 +1: + dcbz r0, r3 + addi r3, r3, 32 + bdnz 1b + + /* Lock way0 in data cache. + */ + mfspr r3, 1011 + lis r2, 0xffff + ori r2, r2, 0xff1f + and r3, r3, r2 + ori r3, r3, 0x0080 + sync + mtspr 1011, r3 +#endif /* !CONFIG_BMW */ + /* + * Thisk the stack pointer *somewhere* sensible. Doesnt + * matter much where as we'll move it when we relocate + */ + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*----------------------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + + mr r3, r21 + /* r3: BOOTFLAG */ + bl board_init_f /* run 1st part of board init code (from Flash) */ + + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException) + +/* Data Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException) + +/* Instruction Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = EXC_OFF_ALIGN +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = EXC_OFF_PROGRAM +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + /* No FPU on MPC8xx. This exception is not supposed to happen. + */ + STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt) + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + + STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException) + + STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException) + STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException) + + STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException) + STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException) + STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException) + STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException) + STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException) + STD_EXCEPTION(0x1500, Reserved5, UnknownException) + STD_EXCEPTION(0x1600, Reserved6, UnknownException) + STD_EXCEPTION(0x1700, Reserved7, UnknownException) + STD_EXCEPTION(0x1800, Reserved8, UnknownException) + STD_EXCEPTION(0x1900, Reserved9, UnknownException) + STD_EXCEPTION(0x1a00, ReservedA, UnknownException) + STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + STD_EXCEPTION(0x1c00, ReservedC, UnknownException) + STD_EXCEPTION(0x1d00, ReservedD, UnknownException) + STD_EXCEPTION(0x1e00, ReservedE, UnknownException) + STD_EXCEPTION(0x1f00, ReservedF, UnknownException) + + STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException) + + .globl _end_of_vectors +_end_of_vectors: + + + . = 0x3000 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) +#if 0 + andi. r23,r23,MSR_PR + mfspr r23,SPRG3 /* if from user, fix up tss.regs */ + beq 2f + addi r24,r1,STACK_FRAME_OVERHEAD + stw r24,PT_REGS(r23) +2: addi r2,r23,-TSS /* set r2 to current */ + tovirt(r2,r2,r23) +#endif + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ +#if 0 + addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */ + cmplw 0,r1,r2 + cmplw 1,r1,r24 + crand 1,1,4 + bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */ +#endif + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + ori r20,r20,0x30 /* enable IR, DR */ + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* Cache functions. +*/ + .globl icache_enable +icache_enable: + mfspr r5,HID0 /* turn on the I cache. */ + ori r5,r5,0x8800 /* Instruction cache only! */ + addis r6,0,0xFFFF + ori r6,r6,0xF7FF + and r6,r5,r6 /* clear the invalidate bit */ + sync + mtspr HID0,r5 + mtspr HID0,r6 + isync + sync + blr + + .globl icache_disable +icache_disable: + mfspr r5,HID0 + addis r6,0,0xFFFF + ori r6,r6,0x7FFF + and r5,r5,r6 + sync + mtspr HID0,r5 + isync + sync + blr + + .globl icache_status +icache_status: + mfspr r3, HID0 + srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */ + andi. r3, r3, 1 + blr + + .globl dcache_enable +dcache_enable: + mfspr r5,HID0 /* turn on the D cache. */ + ori r5,r5,0x4400 /* Data cache only! */ + mfspr r4, PVR /* read PVR */ + srawi r3, r4, 16 /* shift off the least 16 bits */ + cmpi 0, 0, r3, 0xC /* Check for Max pvr */ + bne NotMax + ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */ +NotMax: + addis r6,0,0xFFFF + ori r6,r6,0xFBFF + and r6,r5,r6 /* clear the invalidate bit */ + sync + mtspr HID0,r5 + mtspr HID0,r6 + isync + sync + blr + + .globl dcache_disable +dcache_disable: + mfspr r5,HID0 + addis r6,0,0xFFFF + ori r6,r6,0xBFFF + and r5,r5,r6 + sync + mtspr HID0,r5 + isync + sync + blr + + .globl dcache_status +dcache_status: + mfspr r3, HID0 + srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */ + andi. r3, r3, 1 + blr + + .globl dc_read +dc_read: +/*TODO : who uses this, what should it do? +*/ + blr + + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ +#ifdef CFG_RAMBOOT + lis r4, CFG_SDRAM_BASE@h /* Source Address */ + ori r4, r4, CFG_SDRAM_BASE@l +#else + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l +#endif + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* the the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +4: +#if !defined(CONFIG_BMW) +/* Unlock the data cache and invalidate locked area */ + xor r0, r0, r0 + mtspr 1011, r0 + lis r4, CFG_INIT_RAM_ADDR@h + ori r4, r4, CFG_INIT_RAM_ADDR@l + li r0, 128 + mtctr r0 +41: + dcbi r0, r4 + addi r4, r4, 32 + bdnz 41b +#endif + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ + cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + blt 5b +6: + + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr + + /* Setup the BAT registers. + */ +setup_bats: + lis r4, CFG_IBAT0L@h + ori r4, r4, CFG_IBAT0L@l + lis r3, CFG_IBAT0U@h + ori r3, r3, CFG_IBAT0U@l + mtspr IBAT0L, r4 + mtspr IBAT0U, r3 + isync + + lis r4, CFG_DBAT0L@h + ori r4, r4, CFG_DBAT0L@l + lis r3, CFG_DBAT0U@h + ori r3, r3, CFG_DBAT0U@l + mtspr DBAT0L, r4 + mtspr DBAT0U, r3 + isync + + lis r4, CFG_IBAT1L@h + ori r4, r4, CFG_IBAT1L@l + lis r3, CFG_IBAT1U@h + ori r3, r3, CFG_IBAT1U@l + mtspr IBAT1L, r4 + mtspr IBAT1U, r3 + isync + + lis r4, CFG_DBAT1L@h + ori r4, r4, CFG_DBAT1L@l + lis r3, CFG_DBAT1U@h + ori r3, r3, CFG_DBAT1U@l + mtspr DBAT1L, r4 + mtspr DBAT1U, r3 + isync + + lis r4, CFG_IBAT2L@h + ori r4, r4, CFG_IBAT2L@l + lis r3, CFG_IBAT2U@h + ori r3, r3, CFG_IBAT2U@l + mtspr IBAT2L, r4 + mtspr IBAT2U, r3 + isync + + lis r4, CFG_DBAT2L@h + ori r4, r4, CFG_DBAT2L@l + lis r3, CFG_DBAT2U@h + ori r3, r3, CFG_DBAT2U@l + mtspr DBAT2L, r4 + mtspr DBAT2U, r3 + isync + + lis r4, CFG_IBAT3L@h + ori r4, r4, CFG_IBAT3L@l + lis r3, CFG_IBAT3U@h + ori r3, r3, CFG_IBAT3U@l + mtspr IBAT3L, r4 + mtspr IBAT3U, r3 + isync + + lis r4, CFG_DBAT3L@h + ori r4, r4, CFG_DBAT3L@l + lis r3, CFG_DBAT3U@h + ori r3, r3, CFG_DBAT3U@l + mtspr DBAT3L, r4 + mtspr DBAT3U, r3 + isync + + /* Invalidate TLBs. + * -> for (val = 0; val < 0x20000; val+=0x1000) + * -> tlbie(val); + */ + lis r3, 0 + lis r5, 2 + +1: + tlbie r3 + addi r3, r3, 0x1000 + cmp 0, 0, r3, r5 + blt 1b + + blr diff --git a/cpu/mpc824x/traps.c b/cpu/mpc824x/traps.c new file mode 100644 index 0000000..071d003 --- /dev/null +++ b/cpu/mpc824x/traps.c @@ -0,0 +1,219 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. +*/ +#define END_OF_MEM 0x00400000 + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + printf("Data parity signal\n"); + break; + case (0x80000000>>15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +SoftEmuException(struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + + +void +UnknownException(struct pt_regs *regs) +{ + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint(struct pt_regs *); +#endif + +void +DebugException(struct pt_regs *regs) +{ + + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); +#endif +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int +addr_probe(uint *addr) +{ +#if 0 + int retval; + + __asm__ __volatile__( \ + "1: lwz %0,0(%1)\n" \ + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); + + return (retval); +#endif + return 0; +} diff --git a/cpu/mpc8260/Makefile b/cpu/mpc8260/Makefile new file mode 100644 index 0000000..b4c269f --- /dev/null +++ b/cpu/mpc8260/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o kgdb.o +OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ + interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \ + bedbug_603e.o pci.o spi.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) kgdb.o + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc8260/bedbug_603e.c b/cpu/mpc8260/bedbug_603e.c new file mode 100644 index 0000000..be09cfb --- /dev/null +++ b/cpu/mpc8260/bedbug_603e.c @@ -0,0 +1,237 @@ +/* + * Bedbug Functions specific to the MPC603e core + */ + +#include +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)) + +#define MAX_BREAK_POINTS 1 + +extern CPU_DEBUG_CTX bug_ctx; + +void bedbug603e_init __P((void)); +void bedbug603e_do_break __P((cmd_tbl_t*,int,int,char*[])); +void bedbug603e_break_isr __P((struct pt_regs*)); +int bedbug603e_find_empty __P((void)); +int bedbug603e_set __P((int,unsigned long)); +int bedbug603e_clear __P((int)); + + +/* ====================================================================== + * Initialize the global bug_ctx structure for the processor. Clear all + * of the breakpoints. + * ====================================================================== */ + +void bedbug603e_init( void ) +{ + int i; + /* -------------------------------------------------- */ + + bug_ctx.hw_debug_enabled = 0; + bug_ctx.stopped = 0; + bug_ctx.current_bp = 0; + bug_ctx.regs = NULL; + + bug_ctx.do_break = bedbug603e_do_break; + bug_ctx.break_isr = bedbug603e_break_isr; + bug_ctx.find_empty = bedbug603e_find_empty; + bug_ctx.set = bedbug603e_set; + bug_ctx.clear = bedbug603e_clear; + + for( i = 1; i <= MAX_BREAK_POINTS; ++i ) + (*bug_ctx.clear)( i ); + + puts ("BEDBUG:ready\n"); + return; +} /* bedbug_init_breakpoints */ + + + +/* ====================================================================== + * Set/clear/show the hardware breakpoint for the 603e. The "off" + * string will disable a specific breakpoint. The "show" string will + * display the current breakpoints. Otherwise an address will set a + * breakpoint at that address. Setting a breakpoint uses the CPU-specific + * set routine which will assign a breakpoint number. + * ====================================================================== */ + +void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc, + char *argv[]) +{ + long addr; /* Address to break at */ + int which_bp; /* Breakpoint number */ + /* -------------------------------------------------- */ + + if (argc < 2) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return; + } + + /* Turn off a breakpoint */ + + if( strcmp( argv[ 1 ], "off" ) == 0 ) + { + if( bug_ctx.hw_debug_enabled == 0 ) + { + puts ( "No breakpoints enabled\n" ); + return; + } + + which_bp = simple_strtoul( argv[ 2 ], NULL, 10 ); + + if( bug_ctx.clear ) + (*bug_ctx.clear)( which_bp ); + + printf( "Breakpoint %d removed\n", which_bp ); + return; + } + + /* Show a list of breakpoints */ + + if( strcmp( argv[ 1 ], "show" ) == 0 ) + { + for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp ) + { + + addr = GET_IABR(); + + printf( "Breakpoint [%d]: ", which_bp ); + if( (addr & 0x00000002) == 0 ) + puts ( "NOT SET\n" ); + else + disppc( (unsigned char *)(addr & 0xFFFFFFFC), 0, 1, bedbug_puts, F_RADHEX ); + } + return; + } + + /* Set a breakpoint at the address */ + + if(!(( isdigit( argv[ 1 ][ 0 ] )) || + (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) || + (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' )))) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return; + } + + addr = simple_strtoul( argv[ 1 ], NULL, 16 ); + + if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 ) + { + printf( "Breakpoint [%d]: ", which_bp ); + disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); + } + + return; +} /* bedbug603e_do_break */ + + + +/* ====================================================================== + * Handle a breakpoint. Enter a mini main loop. Stay in the loop until + * the stopped flag in the debug context is cleared. + * ====================================================================== */ + +void bedbug603e_break_isr( struct pt_regs *regs ) +{ + unsigned long addr; /* Address stopped at */ + /* -------------------------------------------------- */ + + bug_ctx.current_bp = 1; + addr = GET_IABR() & 0xFFFFFFFC; + + bedbug_main_loop( addr, regs ); + return; +} /* bedbug603e_break_isr */ + + + +/* ====================================================================== + * See if the hardware breakpoint is available. + * ====================================================================== */ + +int bedbug603e_find_empty( void ) +{ + /* -------------------------------------------------- */ + + if( (GET_IABR() && 0x00000002) == 0 ) + return 1; + + return 0; +} /* bedbug603e_find_empty */ + + + +/* ====================================================================== + * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint + * number, otherwise reassign the given breakpoint. If hardware debugging + * is not enabled, then turn it on via the MSR and DBCR0. Set the break + * address in the IABR register. + * ====================================================================== */ + +int bedbug603e_set( int which_bp, unsigned long addr ) +{ + /* -------------------------------------------------- */ + + if(( addr & 0x00000003 ) != 0 ) + { + puts ( "Breakpoints must be on a 32 bit boundary\n" ); + return 0; + } + + /* Only look if which_bp == 0, else use which_bp */ + if(( bug_ctx.find_empty ) && ( !which_bp ) && + ( which_bp = (*bug_ctx.find_empty)()) == 0 ) + { + puts ( "All breakpoints in use\n" ); + return 0; + } + + if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) + { + printf( "Invalid break point # %d\n", which_bp ); + return 0; + } + + if( ! bug_ctx.hw_debug_enabled ) + { + bug_ctx.hw_debug_enabled = 1; + } + + SET_IABR( addr | 0x00000002 ); + + return which_bp; +} /* bedbug603e_set */ + + + +/* ====================================================================== + * Disable a specific breakoint by setting the IABR register to zero. + * ====================================================================== */ + +int bedbug603e_clear( int which_bp ) +{ + /* -------------------------------------------------- */ + + if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) + { + printf( "Invalid break point # (%d)\n", which_bp ); + return -1; + } + + SET_IABR( 0 ); + + return 0; +} /* bedbug603e_clear */ + + +/* ====================================================================== */ +#endif diff --git a/cpu/mpc8260/commproc.c b/cpu/mpc8260/commproc.c new file mode 100644 index 0000000..e5c5fcf --- /dev/null +++ b/cpu/mpc8260/commproc.c @@ -0,0 +1,227 @@ +/* + * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's + * copyright notice: + * + * General Purpose functions for the global management of the + * 8260 Communication Processor Module. + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) + * 2.3.99 Updates + * + * In addition to the individual control of the communication + * channels, there are a few functions that globally affect the + * communication processor. + * + * Buffer descriptors must be allocated from the dual ported memory + * space. The allocator for that is here. When the communication + * process is reset, we reclaim the memory available. There is + * currently no deallocator for this memory. + */ +#include +#include + +void +m8260_cpm_reset(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ulong count; + + /* Reclaim the DP memory for our use. + */ + gd->dp_alloc_base = CPM_DATAONLY_BASE; + gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE; + + /* + * Reset CPM + */ + immr->im_cpm.cp_cpcr = CPM_CR_RST; + count = 0; + do { /* Spin until command processed */ + __asm__ __volatile__ ("eieio"); + } while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000); + +#ifdef CONFIG_HARD_I2C + *((unsigned short*)(&immr->im_dprambase[PROFF_I2C_BASE])) = 0; +#endif +} + +/* Allocate some memory from the dual ported ram. + * To help protocols with object alignment restrictions, we do that + * if they ask. + */ +uint +m8260_cpm_dpalloc(uint size, uint align) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint retloc; + uint align_mask, off; + uint savebase; + + align_mask = align - 1; + savebase = gd->dp_alloc_base; + + if ((off = (gd->dp_alloc_base & align_mask)) != 0) + gd->dp_alloc_base += (align - off); + + if ((off = size & align_mask) != 0) + size += align - off; + + if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) { + gd->dp_alloc_base = savebase; + panic("m8260_cpm_dpalloc: ran out of dual port ram!"); + } + + retloc = gd->dp_alloc_base; + gd->dp_alloc_base += size; + + memset((void *)&immr->im_dprambase[retloc], 0, size); + + return(retloc); +} + +/* We also own one page of host buffer space for the allocation of + * UART "fifos" and the like. + */ +uint +m8260_cpm_hostalloc(uint size, uint align) +{ + /* the host might not even have RAM yet - just use dual port RAM */ + return (m8260_cpm_dpalloc(size, align)); +} + +/* Set a baud rate generator. This needs lots of work. There are + * eight BRGs, which can be connected to the CPM channels or output + * as clocks. The BRGs are in two different block of internal + * memory mapped space. + * The baud rate clock is the system clock divided by something. + * It was set up long ago during the initial boot phase and is + * is given to us. + * Baud rate clocks are zero-based in the driver code (as that maps + * to port numbers). Documentation uses 1-based numbering. + */ +#define BRG_INT_CLK gd->brg_clk +#define BRG_UART_CLK (BRG_INT_CLK / 16) + +/* This function is used by UARTs, or anything else that uses a 16x + * oversampled clock. + */ +void +m8260_cpm_setbrg(uint brg, uint rate) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uint *bp; + uint cd = BRG_UART_CLK / rate; + + if ((BRG_UART_CLK % rate) < (rate / 2)) + cd--; + if (brg < 4) { + bp = (uint *)&immr->im_brgc1; + } + else { + bp = (uint *)&immr->im_brgc5; + brg -= 4; + } + bp += brg; + *bp = (cd << 1) | CPM_BRG_EN; +} + +/* This function is used to set high speed synchronous baud rate + * clocks. + */ +void +m8260_cpm_fastbrg(uint brg, uint rate, int div16) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uint *bp; + + /* This is good enough to get SMCs running..... + */ + if (brg < 4) { + bp = (uint *)&immr->im_brgc1; + } + else { + bp = (uint *)&immr->im_brgc5; + brg -= 4; + } + bp += brg; + *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; + if (div16) + *bp |= CPM_BRG_DIV16; +} + +/* This function is used to set baud rate generators using an external + * clock source and 16x oversampling. + */ + +void +m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uint *bp; + + if (brg < 4) { + bp = (uint *)&immr->im_brgc1; + } + else { + bp = (uint *)&immr->im_brgc5; + brg -= 4; + } + bp += brg; + *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; + if (pinsel == 0) + *bp |= CPM_BRG_EXTC_CLK3_9; + else + *bp |= CPM_BRG_EXTC_CLK5_15; +} + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + +void post_word_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + + *save_addr = a; +} + +ulong post_word_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + + return *save_addr; +} + +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ + +#ifdef CONFIG_BOOTCOUNT_LIMIT + +void bootcount_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR); + + save_addr[0] = a; + save_addr[1] = BOOTCOUNT_MAGIC; +} + +ulong bootcount_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR); + + if (save_addr[1] != BOOTCOUNT_MAGIC) + return 0; + else + return save_addr[0]; +} + +#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk new file mode 100644 index 0000000..dd7a71f --- /dev/null +++ b/cpu/mpc8260/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \ + -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c new file mode 100644 index 0000000..5d97933 --- /dev/null +++ b/cpu/mpc8260/cpu.c @@ -0,0 +1,289 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x + * + * written or collected and sometimes rewritten by + * Magnus Damm + * + * modified by + * Wolfgang Denk + * + * modified for 8260 by + * Murray Jensen + * + * added 8260 masks by + * Marius Groeger + * + * added HiP7 (824x/827x/8280) processors support by + * Yuli Barcohen + */ + +#include +#include +#include +#include +#include +#include + +int checkcpu (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + ulong clock = gd->cpu_clk; + uint pvr = get_pvr (); + uint immr, rev, m, k; + char buf[32]; + + puts ("CPU: "); + + switch (pvr) { + case PVR_8260: + case PVR_8260_HIP3: + k = 3; + break; + case PVR_8260_HIP4: + k = 4; + break; + case PVR_8260_HIP7R1: + case PVR_8260_HIP7RA: + case PVR_8260_HIP7: + k = 7; + break; + default: + return -1; /* whoops! not an MPC8260 */ + } + rev = pvr & 0xff; + + immr = immap->im_memctl.memc_immr; + if ((immr & IMMR_ISB_MSK) != CFG_IMMR) + return -1; /* whoops! someone moved the IMMR */ + + printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev); + + /* + * the bottom 16 bits of the immr are the Part Number and Mask Number + * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the + * RISC Microcode Revision Number (13-10). + * For the 8260, Motorola doesn't include the Microcode Revision + * in the mask. + */ + m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK); + k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]); + + switch (m) { + case 0x0000: + puts ("0.2 2J24M"); + break; + case 0x0010: + puts ("A.0 K22A"); + break; + case 0x0011: + puts ("A.1 1K22A-XC"); + break; + case 0x0001: + puts ("B.1 1K23A"); + break; + case 0x0021: + puts ("B.2 2K23A-XC"); + break; + case 0x0023: + puts ("B.3 3K23A"); + break; + case 0x0024: + puts ("C.2 6K23A"); + break; + case 0x0060: + puts ("A.0(A) 2K25A"); + break; + case 0x0062: + puts ("B.1 4K25A"); + break; + case 0x0064: + puts ("C.0 5K25A"); + break; + case 0x0A00: + puts ("0.0 0K49M"); + break; + case 0x0A01: + puts ("0.1 1K49M"); + break; + case 0x0A10: + puts ("1.0 1K49M"); + break; + case 0x0C00: + puts ("0.0 0K50M"); + break; + case 0x0C10: + puts ("1.0 1K50M"); + break; + case 0x0D00: + puts ("0.0 0K50M"); + break; + case 0x0D10: + puts ("1.0 1K50M"); + break; + default: + printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); + break; + } + + printf (") at %s MHz\n", strmhz (buf, clock)); + + return 0; +} + +/* ------------------------------------------------------------------------- */ +/* configures a UPM by writing into the UPM RAM array */ +/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */ +/* NOTE: the physical address chosen must not overlap into any other area */ +/* mapped by the memory controller because bank 11 has the lowest priority */ + +void upmconfig (uint upm, uint * table, uint size) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */ + uint i; + + /* first set up bank 11 to reference the correct UPM at a dummy address */ + + memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */ + + switch (upm) { + + case UPMA: + memctl->memc_br11 = + ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA | + BRx_V; + memctl->memc_mamr = MxMR_OP_WARR; + break; + + case UPMB: + memctl->memc_br11 = + ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB | + BRx_V; + memctl->memc_mbmr = MxMR_OP_WARR; + break; + + case UPMC: + memctl->memc_br11 = + ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC | + BRx_V; + memctl->memc_mcmr = MxMR_OP_WARR; + break; + + default: + panic ("upmconfig passed invalid UPM number (%u)\n", upm); + break; + + } + + /* + * at this point, the dummy address is set up to access the selected UPM, + * the MAD pointer is zero, and the MxMR OP is set for writing to RAM + * + * now we simply load the mdr with each word and poke the dummy address. + * the MAD is incremented on each access. + */ + + for (i = 0; i < size; i++) { + memctl->memc_mdr = table[i]; + *dummy = 0; + } + + /* now kill bank 11 */ + memctl->memc_br11 = 0; +} + +/* ------------------------------------------------------------------------- */ + +#if !defined(CONFIG_HAVE_OWN_RESET) +int +do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong msr, addr; + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */ + + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* + * Trying to execute the next instruction at a non-existing address + * should cause a machine check, resulting in reset + */ +#ifdef CFG_RESET_ADDRESS + addr = CFG_RESET_ADDRESS; +#else + /* + * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE + * - sizeof (ulong) is usually a valid address. Better pick an address + * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. + */ + addr = CFG_MONITOR_BASE - sizeof (ulong); +#endif + ((void (*)(void)) addr) (); + return 1; + +} +#endif /* CONFIG_HAVE_OWN_RESET */ + +/* ------------------------------------------------------------------------- */ + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + * + */ +unsigned long get_tbclk (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong tbclk; + + tbclk = (gd->bus_clk + 3L) / 4L; + + return (tbclk); +} + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + int re_enable = disable_interrupts (); + + reset_8260_watchdog ((immap_t *) CFG_IMMR); + if (re_enable) + enable_interrupts (); +} +#endif /* CONFIG_WATCHDOG */ + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c new file mode 100644 index 0000000..babcce4 --- /dev/null +++ b/cpu/mpc8260/cpu_init.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static void config_8260_ioports (volatile immap_t * immr) +{ + int portnum; + + for (portnum = 0; portnum < 4; portnum++) { + uint pmsk = 0, + ppar = 0, + psor = 0, + pdir = 0, + podr = 0, + pdat = 0; + iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; + iop_conf_t *eiopc = iopc + 32; + uint msk = 1; + + /* + * NOTE: + * index 0 refers to pin 31, + * index 31 refers to pin 0 + */ + while (iopc < eiopc) { + if (iopc->conf) { + pmsk |= msk; + if (iopc->ppar) + ppar |= msk; + if (iopc->psor) + psor |= msk; + if (iopc->pdir) + pdir |= msk; + if (iopc->podr) + podr |= msk; + if (iopc->pdat) + pdat |= msk; + } + + msk <<= 1; + iopc++; + } + + if (pmsk != 0) { + volatile ioport_t *iop = ioport_addr (immr, portnum); + uint tpmsk = ~pmsk; + + /* + * the (somewhat confused) paragraph at the + * bottom of page 35-5 warns that there might + * be "unknown behaviour" when programming + * PSORx and PDIRx, if PPARx = 1, so I + * decided this meant I had to disable the + * dedicated function first, and enable it + * last. + */ + iop->ppar &= tpmsk; + iop->psor = (iop->psor & tpmsk) | psor; + iop->podr = (iop->podr & tpmsk) | podr; + iop->pdat = (iop->pdat & tpmsk) | pdat; + iop->pdir = (iop->pdir & tpmsk) | pdir; + iop->ppar |= ppar; + } + } +} + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f (volatile immap_t * immr) +{ + DECLARE_GLOBAL_DATA_PTR; +#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ + uint sccr; +#endif + volatile memctl8260_t *memctl = &immr->im_memctl; + extern void m8260_cpm_reset (void); + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* RSR - Reset Status Register - clear all status (5-4) */ + gd->reset_status = immr->im_clkrst.car_rsr; + immr->im_clkrst.car_rsr = RSR_ALLBITS; + + /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */ + immr->im_clkrst.car_rmr = CFG_RMR; + + /* BCR - Bus Configuration Register (4-25) */ + immr->im_siu_conf.sc_bcr = CFG_BCR; + + /* SIUMCR - contains debug pin configuration (4-31) */ + immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; + + config_8260_ioports (immr); + + /* initialize time counter status and control register (4-40) */ + immr->im_sit.sit_tmcntsc = CFG_TMCNTSC; + + /* initialize the PIT (4-42) */ + immr->im_sit.sit_piscr = CFG_PISCR; + +#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ + /* System clock control register (9-8) */ + sccr = immr->im_clkrst.car_sccr & + (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK); + immr->im_clkrst.car_sccr = sccr | + (CFG_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); +#endif /* !CONFIG_COGENT */ + + /* + * Memory Controller: + */ + + /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary + * addresses - these have to be modified later when FLASH size + * has been determined + */ + +#if defined(CFG_OR0_REMAP) + memctl->memc_or0 = CFG_OR0_REMAP; +#endif +#if defined(CFG_OR1_REMAP) + memctl->memc_or1 = CFG_OR1_REMAP; +#endif + + /* now restrict to preliminary range */ + memctl->memc_br0 = CFG_BR0_PRELIM; + memctl->memc_or0 = CFG_OR0_PRELIM; + +#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; +#endif + +#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; +#endif + +#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; +#endif + +#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) + memctl->memc_or4 = CFG_OR4_PRELIM; + memctl->memc_br4 = CFG_BR4_PRELIM; +#endif + +#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) + memctl->memc_or5 = CFG_OR5_PRELIM; + memctl->memc_br5 = CFG_BR5_PRELIM; +#endif + +#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) + memctl->memc_or6 = CFG_OR6_PRELIM; + memctl->memc_br6 = CFG_BR6_PRELIM; +#endif + +#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) + memctl->memc_or7 = CFG_OR7_PRELIM; + memctl->memc_br7 = CFG_BR7_PRELIM; +#endif + +#if defined(CFG_BR8_PRELIM) && defined(CFG_OR8_PRELIM) + memctl->memc_or8 = CFG_OR8_PRELIM; + memctl->memc_br8 = CFG_BR8_PRELIM; +#endif + +#if defined(CFG_BR9_PRELIM) && defined(CFG_OR9_PRELIM) + memctl->memc_or9 = CFG_OR9_PRELIM; + memctl->memc_br9 = CFG_BR9_PRELIM; +#endif + +#if defined(CFG_BR10_PRELIM) && defined(CFG_OR10_PRELIM) + memctl->memc_or10 = CFG_OR10_PRELIM; + memctl->memc_br10 = CFG_BR10_PRELIM; +#endif + +#if defined(CFG_BR11_PRELIM) && defined(CFG_OR11_PRELIM) + memctl->memc_or11 = CFG_OR11_PRELIM; + memctl->memc_br11 = CFG_BR11_PRELIM; +#endif + + m8260_cpm_reset (); +} + +/* + * initialize higher level parts of CPU like time base and timers + */ +int cpu_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base; + + immr->im_cpm.cp_rccr = CFG_RCCR; + + return (0); +} + +/* + * print out the reason for the reset + */ +int prt_8260_rsr (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + static struct { + ulong mask; + char *desc; + } bits[] = { + { + RSR_JTRS, "JTAG"}, { + RSR_CSRS, "Check Stop"}, { + RSR_SWRS, "Software Watchdog"}, { + RSR_BMRS, "Bus Monitor"}, { + RSR_ESRS, "External Soft"}, { + RSR_EHRS, "External Hard"} + }; + static int n = sizeof bits / sizeof bits[0]; + ulong rsr = gd->reset_status; + int i; + char *sep; + + puts (CPU_ID_STR " Reset Status:"); + + sep = " "; + for (i = 0; i < n; i++) + if (rsr & bits[i].mask) { + printf ("%s%s", sep, bits[i].desc); + sep = ", "; + } + + puts ("\n\n"); + return (0); +} diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c new file mode 100644 index 0000000..ed3515f --- /dev/null +++ b/cpu/mpc8260/ether_fcc.c @@ -0,0 +1,1190 @@ +/* + * MPC8260 FCC Fast Ethernet + * + * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) + * + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8260 FCC Fast Ethernet + * Basic ET HW initialization and packet RX/TX routines + * + * This code will not perform the IO port configuration. This should be + * done in the iop_conf_t structure specific for the board. + * + * TODO: + * add a PHY driver to do the negotiation + * reflect negotiation results in FPSMR + * look for ways to configure the board specific stuff elsewhere, eg. + * config_xxx.h or the board directory + */ + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#include +#endif + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \ + defined(CONFIG_NET_MULTI) + +static struct ether_fcc_info_s +{ + int ether_index; + int proff_enet; + ulong cpm_cr_enet_sblock; + ulong cpm_cr_enet_page; + ulong cmxfcr_mask; + ulong cmxfcr_value; +} + ether_fcc_info[] = +{ +#ifdef CONFIG_ETHER_ON_FCC1 +{ + 0, + PROFF_FCC1, + CPM_CR_FCC1_SBLOCK, + CPM_CR_FCC1_PAGE, + CFG_CMXFCR_MASK1, + CFG_CMXFCR_VALUE1 +}, +#endif + +#ifdef CONFIG_ETHER_ON_FCC2 +{ + 1, + PROFF_FCC2, + CPM_CR_FCC2_SBLOCK, + CPM_CR_FCC2_PAGE, + CFG_CMXFCR_MASK2, + CFG_CMXFCR_VALUE2 +}, +#endif + +#ifdef CONFIG_ETHER_ON_FCC3 +{ + 2, + PROFF_FCC3, + CPM_CR_FCC3_SBLOCK, + CPM_CR_FCC3_PAGE, + CFG_CMXFCR_MASK3, + CFG_CMXFCR_VALUE3 +}, +#endif +}; + +/*---------------------------------------------------------------------*/ + +/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ +#define PKT_MAXDMA_SIZE 1520 + +/* The FCC stores dest/src/type, data, and checksum for receive packets. */ +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 + +/* Maximum input buffer size. Must be a multiple of 32. */ +#define PKT_MAXBLR_SIZE 1536 + +#define TOUT_LOOP 1000000 + +#define TX_BUF_CNT 2 +#ifdef __GNUC__ +static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8))); +#else +#error "txbuf must be 64-bit aligned" +#endif + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * FCC Ethernet Tx and Rx buffer descriptors. + * Provide for Double Buffering + * Note: PKTBUFSRX is defined in net.h + */ + +typedef volatile struct rtxbd { + cbd_t rxbd[PKTBUFSRX]; + cbd_t txbd[TX_BUF_CNT]; +} RTXBD; + +/* Good news: the FCC supports external BDs! */ +#ifdef __GNUC__ +static RTXBD rtx __attribute__ ((aligned(8))); +#else +#error "rtx must be 64-bit aligned" +#endif + +static int fec_send(struct eth_device* dev, volatile void *packet, int length) +{ + int i; + int result = 0; + + if (length <= 0) { + printf("fec: bad packet size: %d\n", length); + goto out; + } + + for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + puts ("fec: tx buffer not ready\n"); + goto out; + } + } + + rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; + rtx.txbd[txIdx].cbd_datlen = length; + rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | + BD_ENET_TX_WRAP); + + for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + puts ("fec: tx error\n"); + goto out; + } + } + +#ifdef ET_DEBUG + printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc); +#endif + + /* return only status bits */ + result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; + +out: + return result; +} + +static int fec_recv(struct eth_device* dev) +{ + int length; + + for (;;) + { + if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + length = rtx.rxbd[rxIdx].cbd_datlen; + + if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { + printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); + } + else { + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[rxIdx], length - 4); + } + + + /* Give the buffer back to the FCC. */ + rtx.rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } + else { + rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + } + return length; +} + + +static int fec_init(struct eth_device* dev, bd_t *bis) +{ + struct ether_fcc_info_s * info = dev->priv; + int i; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile cpm8260_t *cp = &(immr->im_cpm); + fcc_enet_t *pram_ptr; + unsigned long mem_addr; + +#if 0 + mii_discover_phy(); +#endif + + /* 28.9 - (1-2): ioports have been set up already */ + + /* 28.9 - (3): connect FCC's tx and rx clocks */ + immr->im_cpmux.cmx_uar = 0; + immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) | + info->cmxfcr_value; + + /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */ + immr->im_fcc[info->ether_index].fcc_gfmr = + FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + + /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */ + immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + + /* 28.9 - (6): FDSR: Ethernet Syn */ + immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555; + + /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ + rxIdx = 0; + txIdx = 0; + + /* Setup Receiver Buffer Descriptors */ + for (i = 0; i < PKTBUFSRX; i++) + { + rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx.rxbd[i].cbd_datlen = 0; + rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; + } + rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* Setup Ethernet Transmitter Buffer Descriptors */ + for (i = 0; i < TX_BUF_CNT; i++) + { + rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); + rtx.txbd[i].cbd_datlen = 0; + rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; + } + rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* 28.9 - (7): initialise parameter ram */ + pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]); + + /* clear whole structure to make sure all reserved fields are zero */ + memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); + + /* + * common Parameter RAM area + * + * Allocate space in the reserved FCC area of DPRAM for the + * internal buffers. No one uses this space (yet), so we + * can do this. Later, we will add resource management for + * this area. + */ + mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); + pram_ptr->fen_genfcc.fcc_riptr = mem_addr; + pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; + /* + * Set maximum bytes per receive buffer. + * It must be a multiple of 32. + */ + pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; + pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | + CFG_CPMFCR_RAMTYPE) << 24; + pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); + pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | + CFG_CPMFCR_RAMTYPE) << 24; + pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); + + /* protocol-specific area */ + pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ + pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ + pram_ptr->fen_retlim = 15; /* Retry limit threshold */ + pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ + /* + * Set Ethernet station address. + * + * This is supplied in the board information structure, so we + * copy that into the controller. + * So, far we have only been given one Ethernet address. We make + * it unique by setting a few bits in the upper byte of the + * non-static part of the address. + */ +#define ea eth_get_dev()->enetaddr + pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; + pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; + pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; +#undef ea + pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ + /* pad pointer. use tiptr since we don't need a specific padding char */ + pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; + pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */ + pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */ + pram_ptr->fen_rfthr = 1; + pram_ptr->fen_rfcnt = 1; +#if 0 + printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n", + pram_ptr->fen_genfcc.fcc_rbase); + printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n", + pram_ptr->fen_genfcc.fcc_tbase); +#endif + + /* 28.9 - (8): clear out events in FCCE */ + immr->im_fcc[info->ether_index].fcc_fcce = ~0x0; + + /* 28.9 - (9): FCCM: mask all events */ + immr->im_fcc[info->ether_index].fcc_fccm = 0; + + /* 28.9 - (10-12): we don't use ethernet interrupts */ + + /* 28.9 - (13) + * + * Let's re-initialize the channel now. We have to do it later + * than the manual describes because we have just now finished + * the BD initialization. + */ + cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page, + info->cpm_cr_enet_sblock, + 0x0c, + CPM_CR_INIT_TRX) | CPM_CR_FLG; + do { + __asm__ __volatile__ ("eieio"); + } while (cp->cp_cpcr & CPM_CR_FLG); + + /* 28.9 - (14): enable tx/rx in gfmr */ + immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + + return 1; +} + +static void fec_halt(struct eth_device* dev) +{ + struct ether_fcc_info_s * info = dev->priv; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + + /* write GFMR: disable tx/rx */ + immr->im_fcc[info->ether_index].fcc_gfmr &= + ~(FCC_GFMR_ENT | FCC_GFMR_ENR); +} + +int fec_initialize(bd_t *bis) +{ + struct eth_device* dev; + int i; + + for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) + { + dev = (struct eth_device*) malloc(sizeof *dev); + memset(dev, 0, sizeof *dev); + + sprintf(dev->name, "FCC%d ETHERNET", + ether_fcc_info[i].ether_index + 1); + dev->priv = ðer_fcc_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + eth_register(dev); + +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \ + && defined(CONFIG_BITBANGMII) + miiphy_register(dev->name, + bb_miiphy_read, bb_miiphy_write); +#endif + } + + return 1; +} + +#ifdef CONFIG_ETHER_LOOPBACK_TEST + +#define ELBT_BUFSZ 1024 /* must be multiple of 32 */ + +#define ELBT_CRCSZ 4 + +#define ELBT_NRXBD 4 /* must be at least 2 */ +#define ELBT_NTXBD 4 + +#define ELBT_MAXRXERR 32 +#define ELBT_MAXTXERR 32 + +#define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */ + +typedef + struct { + uint off; + char *lab; + } +elbt_prdesc; + +typedef + struct { + uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl; + uint badsrc, badtyp, badlen, badbit; + } +elbt_rxeacc; + +static elbt_prdesc rxeacc_descs[] = { + { offsetof(elbt_rxeacc, _l), "Not Last in Frame" }, + { offsetof(elbt_rxeacc, _f), "Not First in Frame" }, + { offsetof(elbt_rxeacc, m), "Address Miss" }, + { offsetof(elbt_rxeacc, bc), "Broadcast Address" }, + { offsetof(elbt_rxeacc, mc), "Multicast Address" }, + { offsetof(elbt_rxeacc, lg), "Frame Length Violation"}, + { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" }, + { offsetof(elbt_rxeacc, sh), "Short Frame" }, + { offsetof(elbt_rxeacc, cr), "CRC Error" }, + { offsetof(elbt_rxeacc, ov), "Overrun" }, + { offsetof(elbt_rxeacc, cl), "Collision" }, + { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" }, + { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" }, + { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" }, + { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" }, +}; +static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]); + +typedef + struct { + uint def, hb, lc, rl, rc, un, csl; + } +elbt_txeacc; + +static elbt_prdesc txeacc_descs[] = { + { offsetof(elbt_txeacc, def), "Defer Indication" }, + { offsetof(elbt_txeacc, hb), "Heartbeat" }, + { offsetof(elbt_txeacc, lc), "Late Collision" }, + { offsetof(elbt_txeacc, rl), "Retransmission Limit" }, + { offsetof(elbt_txeacc, rc), "Retry Count" }, + { offsetof(elbt_txeacc, un), "Underrun" }, + { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" }, +}; +static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]); + +typedef + struct { + uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ]; + uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ]; + cbd_t rxbd[ELBT_NRXBD]; + cbd_t txbd[ELBT_NTXBD]; + enum { Idle, Running, Closing, Closed } state; + int proff, page, sblock; + uint clstime, nsent, ntxerr, nrcvd, nrxerr; + ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR]; + elbt_rxeacc rxeacc; + elbt_txeacc txeacc; + } __attribute__ ((aligned(8))) +elbt_chan; + +static uchar patbytes[ELBT_NTXBD] = { + 0xff, 0xaa, 0x55, 0x00 +}; +static uint patwords[ELBT_NTXBD] = { + 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000 +}; + +#ifdef __GNUC__ +static elbt_chan elbt_chans[3] __attribute__ ((aligned(8))); +#else +#error "elbt_chans must be 64-bit aligned" +#endif + +#define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005) + +static elbt_prdesc epram_descs[] = { + { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" }, + { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" }, + { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" }, + { offsetof(fcc_enet_t, fen_octc), "Octets" }, + { offsetof(fcc_enet_t, fen_colc), "Collisions" }, + { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" }, + { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" }, + { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" }, + { offsetof(fcc_enet_t, fen_frgc), "Fragments" }, + { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" }, + { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" }, + { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" }, + { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" }, + { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" }, + { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" }, + { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" }, + { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"}, +}; +static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]); + +/* + * given an elbt_prdesc array and an array of base addresses, print + * each prdesc down the screen with the values fetched from each + * base address across the screen + */ +static void +print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase) +{ + elbt_prdesc *dp = descs, *edp = dp + ndesc; + int i; + + printf ("%32s", ""); + + for (i = 0; i < nbase; i++) + printf (" Channel %d", i); + + putc ('\n'); + + while (dp < edp) { + + printf ("%-32s", dp->lab); + + for (i = 0; i < nbase; i++) { + uint val = *(uint *)(bases[i] + dp->off); + + printf (" %10u", val); + } + + putc ('\n'); + + dp++; + } +} + +/* + * return number of bits that are set in a value; value contains + * nbits (right-justified) bits. + */ +static uint __inline__ +nbs (uint value, uint nbits) +{ + uint cnt = 0; +#if 1 + uint pos = sizeof (uint) * 8; + + __asm__ __volatile__ ("\ + mtctr %2\n\ +1: rlwnm. %2,%1,%4,31,31\n\ + beq 2f\n\ + addi %0,%0,1\n\ +2: subi %4,%4,1\n\ + bdnz 1b" + : "=r"(cnt) + : "r"(value), "r"(nbits), "r"(cnt), "r"(pos) + : "ctr", "cc" ); +#else + uint mask = 1; + + do { + if (value & mask) + cnt++; + mask <<= 1; + } while (--nbits); +#endif + + return (cnt); +} + +static ulong +badbits (uchar *bp, int n, ulong pat) +{ + ulong *lp, cnt = 0; + int nl; + + while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) { + uchar diff; + + diff = *bp++ ^ (uchar)pat; + + if (diff) + cnt += nbs ((ulong)diff, 8); + + n--; + } + + lp = (ulong *)bp; + nl = n / sizeof (ulong); + n -= nl * sizeof (ulong); + + while (nl > 0) { + ulong diff; + + diff = *lp++ ^ pat; + + if (diff) + cnt += nbs (diff, 32); + + nl--; + } + + bp = (uchar *)lp; + + while (n > 0) { + uchar diff; + + diff = *bp++ ^ (uchar)pat; + + if (diff) + cnt += nbs ((ulong)diff, 8); + + n--; + } + + return (cnt); +} + +static inline unsigned short +swap16 (unsigned short x) +{ + return (((x & 0xff) << 8) | ((x & 0xff00) >> 8)); +} + +/* broadcast is not an error - we send them like that */ +#define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC) + +void +eth_loopback_test (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile cpm8260_t *cp = &(immr->im_cpm); + int c, nclosed; + ulong runtime, nmsec; + uchar *bases[3]; + + puts ("FCC Ethernet External loopback test\n"); + + memcpy (NetOurEther, gd->bd->bi_enetaddr, 6); + + /* + * global initialisations for all FCC channels + */ + + /* 28.9 - (1-2): ioports have been set up already */ + +#if defined(CONFIG_HYMOD) + /* + * Attention: this is board-specific + * 0, FCC1 + * 1, FCC2 + * 2, FCC3 + */ +# define FCC_START_LOOP 0 +# define FCC_END_LOOP 2 + + /* + * Attention: this is board-specific + * - FCC1 Rx-CLK is CLK10 + * - FCC1 Tx-CLK is CLK11 + * - FCC2 Rx-CLK is CLK13 + * - FCC2 Tx-CLK is CLK14 + * - FCC3 Rx-CLK is CLK15 + * - FCC3 Tx-CLK is CLK16 + */ + + /* 28.9 - (3): connect FCC's tx and rx clocks */ + immr->im_cpmux.cmx_uar = 0; + immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\ + CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\ + CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16; +#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng) + /* + * Attention: this is board-specific + * 1, FCC2 + */ +# define FCC_START_LOOP 1 +# define FCC_END_LOOP 1 + + /* + * Attention: this is board-specific + * - FCC2 Rx-CLK is CLK13 + * - FCC2 Tx-CLK is CLK14 + */ + + /* 28.9 - (3): connect FCC's tx and rx clocks */ + immr->im_cpmux.cmx_uar = 0; + immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14; +#else +#error "eth_loopback_test not supported on your board" +#endif + + puts ("Initialise FCC channels:"); + + for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { + elbt_chan *ecp = &elbt_chans[c]; + volatile fcc_t *fcp = &immr->im_fcc[c]; + volatile fcc_enet_t *fpp; + int i; + ulong addr; + + /* + * initialise channel data + */ + + printf (" %d", c); + + memset ((void *)ecp, 0, sizeof (*ecp)); + + ecp->state = Idle; + + switch (c) { + + case 0: /* FCC1 */ + ecp->proff = PROFF_FCC1; + ecp->page = CPM_CR_FCC1_PAGE; + ecp->sblock = CPM_CR_FCC1_SBLOCK; + break; + + case 1: /* FCC2 */ + ecp->proff = PROFF_FCC2; + ecp->page = CPM_CR_FCC2_PAGE; + ecp->sblock = CPM_CR_FCC2_SBLOCK; + break; + + case 2: /* FCC3 */ + ecp->proff = PROFF_FCC3; + ecp->page = CPM_CR_FCC3_PAGE; + ecp->sblock = CPM_CR_FCC3_SBLOCK; + break; + } + + /* + * set up tx buffers and bds + */ + + for (i = 0; i < ELBT_NTXBD; i++) { + cbd_t *bdp = &ecp->txbd[i]; + uchar *bp = &ecp->txbufs[i][0]; + + bdp->cbd_bufaddr = (uint)bp; + /* room for crc */ + bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ; + bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \ + BD_ENET_TX_LAST | BD_ENET_TX_TC; + + memset ((void *)bp, patbytes[i], ELBT_BUFSZ); + NetSetEther (bp, NetBcastAddr, 0x8000); + } + ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* + * set up rx buffers and bds + */ + + for (i = 0; i < ELBT_NRXBD; i++) { + cbd_t *bdp = &ecp->rxbd[i]; + uchar *bp = &ecp->rxbufs[i][0]; + + bdp->cbd_bufaddr = (uint)bp; + bdp->cbd_datlen = 0; + bdp->cbd_sc = BD_ENET_RX_EMPTY; + + memset ((void *)bp, 0, ELBT_BUFSZ); + } + ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * set up the FCC channel hardware + */ + + /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */ + fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + + /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */ + fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \ + FCC_PSMR_ENCRC | FCC_PSMR_PRO | \ + FCC_PSMR_MON | FCC_PSMR_RSH; + + /* 28.9 - (6): FDSR: Ethernet Syn */ + fcp->fcc_fdsr = 0xD555; + + /* 29.9 - (7): initialise parameter ram */ + fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]); + + /* clear whole struct to make sure all resv fields are zero */ + memset ((void *)fpp, 0, sizeof (fcc_enet_t)); + + /* + * common Parameter RAM area + * + * Allocate space in the reserved FCC area of DPRAM for the + * internal buffers. No one uses this space (yet), so we + * can do this. Later, we will add resource management for + * this area. + */ + addr = CPM_FCC_SPECIAL_BASE + (c * 64); + fpp->fen_genfcc.fcc_riptr = addr; + fpp->fen_genfcc.fcc_tiptr = addr + 32; + + /* + * Set maximum bytes per receive buffer. + * It must be a multiple of 32. + * buffers are in 60x bus memory. + */ + fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; + fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24; + fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]); + fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24; + fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]); + + /* protocol-specific area */ + fpp->fen_cmask = 0xdebb20e3; /* CRC mask */ + fpp->fen_cpres = 0xffffffff; /* CRC preset */ + fpp->fen_retlim = 15; /* Retry limit threshold */ + fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */ + + /* + * Set Ethernet station address. + * + * This is supplied in the board information structure, so we + * copy that into the controller. + * So, far we have only been given one Ethernet address. We use + * the same address for all channels + */ +#define ea gd->bd->bi_enetaddr + fpp->fen_paddrh = (ea[5] << 8) + ea[4]; + fpp->fen_paddrm = (ea[3] << 8) + ea[2]; + fpp->fen_paddrl = (ea[1] << 8) + ea[0]; +#undef ea + + fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */ + /* + * pad pointer. use tiptr since we don't need + * a specific padding char + */ + fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr; + fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */ + fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */ + fpp->fen_rfthr = 1; + fpp->fen_rfcnt = 1; + + /* 28.9 - (8): clear out events in FCCE */ + fcp->fcc_fcce = ~0x0; + + /* 28.9 - (9): FCCM: mask all events */ + fcp->fcc_fccm = 0; + + /* 28.9 - (10-12): we don't use ethernet interrupts */ + + /* 28.9 - (13) + * + * Let's re-initialize the channel now. We have to do it later + * than the manual describes because we have just now finished + * the BD initialization. + */ + cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \ + 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG; + do { + __asm__ __volatile__ ("eieio"); + } while (cp->cp_cpcr & CPM_CR_FLG); + } + + puts (" done\nStarting test... (Ctrl-C to Finish)\n"); + + /* + * Note: don't want serial output from here until the end of the + * test - the delays would probably stuff things up. + */ + + clear_ctrlc (); + runtime = get_timer (0); + + do { + nclosed = 0; + + for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { + volatile fcc_t *fcp = &immr->im_fcc[c]; + elbt_chan *ecp = &elbt_chans[c]; + int i; + + switch (ecp->state) { + + case Idle: + /* + * set the channel Running ... + */ + + /* 28.9 - (14): enable tx/rx in gfmr */ + fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + + ecp->state = Running; + break; + + case Running: + /* + * (while Running only) check for + * termination of the test + */ + + (void)ctrlc (); + + if (had_ctrlc ()) { + /* + * initiate a "graceful stop transmit" + * on the channel + */ + cp->cp_cpcr = mk_cr_cmd (ecp->page, \ + ecp->sblock, 0x0c, \ + CPM_CR_GRACEFUL_STOP_TX) | \ + CPM_CR_FLG; + do { + __asm__ __volatile__ ("eieio"); + } while (cp->cp_cpcr & CPM_CR_FLG); + + ecp->clstime = get_timer (0); + ecp->state = Closing; + } + /* fall through ... */ + + case Closing: + /* + * (while Running or Closing) poll the channel: + * - check for any non-READY tx buffers and + * make them ready + * - check for any non-EMPTY rx buffers and + * check that they were received correctly, + * adjust counters etc, then make empty + */ + + for (i = 0; i < ELBT_NTXBD; i++) { + cbd_t *bdp = &ecp->txbd[i]; + ushort sc = bdp->cbd_sc; + + if ((sc & BD_ENET_TX_READY) != 0) + continue; + + /* + * this frame has finished + * transmitting + */ + ecp->nsent++; + + if (sc & BD_ENET_TX_STATS) { + ulong n; + + /* + * we had an error on + * the transmission + */ + n = ecp->ntxerr++; + if (n < ELBT_MAXTXERR) + ecp->txerrs[n] = sc; + + if (sc & BD_ENET_TX_DEF) + ecp->txeacc.def++; + if (sc & BD_ENET_TX_HB) + ecp->txeacc.hb++; + if (sc & BD_ENET_TX_LC) + ecp->txeacc.lc++; + if (sc & BD_ENET_TX_RL) + ecp->txeacc.rl++; + if (sc & BD_ENET_TX_RCMASK) + ecp->txeacc.rc++; + if (sc & BD_ENET_TX_UN) + ecp->txeacc.un++; + if (sc & BD_ENET_TX_CSL) + ecp->txeacc.csl++; + + bdp->cbd_sc &= \ + ~BD_ENET_TX_STATS; + } + + if (ecp->state == Closing) + ecp->clstime = get_timer (0); + + /* make it ready again */ + bdp->cbd_sc |= BD_ENET_TX_READY; + } + + for (i = 0; i < ELBT_NRXBD; i++) { + cbd_t *bdp = &ecp->rxbd[i]; + ushort sc = bdp->cbd_sc, mask; + + if ((sc & BD_ENET_RX_EMPTY) != 0) + continue; + + /* we have a new frame in this buffer */ + ecp->nrcvd++; + + mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST; + if ((sc & mask) != mask) { + /* somethings wrong here ... */ + if (!(sc & BD_ENET_RX_LAST)) + ecp->rxeacc._l++; + if (!(sc & BD_ENET_RX_FIRST)) + ecp->rxeacc._f++; + } + + if (sc & BD_ENET_RX_ERRS) { + ulong n; + + /* + * we had some sort of error + * on the frame + */ + n = ecp->nrxerr++; + if (n < ELBT_MAXRXERR) + ecp->rxerrs[n] = sc; + + if (sc & BD_ENET_RX_MISS) + ecp->rxeacc.m++; + if (sc & BD_ENET_RX_BC) + ecp->rxeacc.bc++; + if (sc & BD_ENET_RX_MC) + ecp->rxeacc.mc++; + if (sc & BD_ENET_RX_LG) + ecp->rxeacc.lg++; + if (sc & BD_ENET_RX_NO) + ecp->rxeacc.no++; + if (sc & BD_ENET_RX_SH) + ecp->rxeacc.sh++; + if (sc & BD_ENET_RX_CR) + ecp->rxeacc.cr++; + if (sc & BD_ENET_RX_OV) + ecp->rxeacc.ov++; + if (sc & BD_ENET_RX_CL) + ecp->rxeacc.cl++; + + bdp->cbd_sc &= \ + ~BD_ENET_RX_ERRS; + } + else { + ushort datlen = bdp->cbd_datlen; + Ethernet_t *ehp; + ushort prot; + int ours, tb, n, nbytes; + + ehp = (Ethernet_t *) \ + &ecp->rxbufs[i][0]; + + ours = memcmp (ehp->et_src, \ + NetOurEther, 6); + + prot = swap16 (ehp->et_protlen); + tb = prot & 0x8000; + n = prot & 0x7fff; + + nbytes = ELBT_BUFSZ - \ + offsetof (Ethernet_t, \ + et_dsap) - \ + ELBT_CRCSZ; + + /* check the frame is correct */ + if (datlen != ELBT_BUFSZ) + ecp->rxeacc.badlen++; + else if (!ours) + ecp->rxeacc.badsrc++; + else if (!tb || n >= ELBT_NTXBD) + ecp->rxeacc.badtyp++; + else { + ulong patword = \ + patwords[n]; + uint nbb; + + nbb = badbits ( \ + &ehp->et_dsap, \ + nbytes, \ + patword); + + ecp->rxeacc.badbit += \ + nbb; + } + } + + if (ecp->state == Closing) + ecp->clstime = get_timer (0); + + /* make it empty again */ + bdp->cbd_sc |= BD_ENET_RX_EMPTY; + } + + if (ecp->state != Closing) + break; + + /* + * (while Closing) check to see if + * waited long enough + */ + + if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) { + /* write GFMR: disable tx/rx */ + fcp->fcc_gfmr &= \ + ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + ecp->state = Closed; + } + + break; + + case Closed: + nclosed++; + break; + } + } + + } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1)); + + runtime = get_timer (runtime); + if (runtime <= ELBT_CLSWAIT) { + printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n", + runtime, ELBT_CLSWAIT); + return; + } + nmsec = runtime - ELBT_CLSWAIT; + + printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n", + nmsec, ELBT_CLSWAIT); + + /* + * now print stats + */ + + for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { + elbt_chan *ecp = &elbt_chans[c]; + uint rxpps, txpps, nerr; + + rxpps = (ecp->nrcvd * 1000) / nmsec; + txpps = (ecp->nsent * 1000) / nmsec; + + printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), " + "%d sent (%d pps, %d txerrs)\n\n", c, + ecp->nrcvd, rxpps, ecp->nrxerr, + ecp->nsent, txpps, ecp->ntxerr); + + if ((nerr = ecp->nrxerr) > 0) { + ulong i; + + printf ("\tFirst %d rx errs:", nerr); + for (i = 0; i < nerr; i++) + printf (" %04x", ecp->rxerrs[i]); + putc ('\n'); + } + + if ((nerr = ecp->ntxerr) > 0) { + ulong i; + + printf ("\tFirst %d tx errs:", nerr); + for (i = 0; i < nerr; i++) + printf (" %04x", ecp->txerrs[i]); + putc ('\n'); + } + } + + puts ("Receive Error Counts:\n"); + for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) + bases[c] = (uchar *)&elbt_chans[c].rxeacc; + print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3); + + puts ("\nTransmit Error Counts:\n"); + for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) + bases[c] = (uchar *)&elbt_chans[c].txeacc; + print_desc (txeacc_descs, txeacc_ndesc, bases, 3); + + puts ("\nRMON(-like) Counters:\n"); + for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) + bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff]; + print_desc (epram_descs, epram_ndesc, bases, 3); +} + +#endif /* CONFIG_ETHER_LOOPBACK_TEST */ + +#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c new file mode 100644 index 0000000..a733b45 --- /dev/null +++ b/cpu/mpc8260/ether_scc.c @@ -0,0 +1,356 @@ +/* + * MPC8260 SCC Ethernet + * + * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) + * + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright (c) 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_COMMANDS & CFG_CMD_NET) + +#if (CONFIG_ETHER_INDEX == 1) +# define PROFF_ENET PROFF_SCC1 +# define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE +# define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK +# define CMXSCR_MASK (CMXSCR_SC1 |\ + CMXSCR_RS1CS_MSK |\ + CMXSCR_TS1CS_MSK) + +#elif (CONFIG_ETHER_INDEX == 2) +# define PROFF_ENET PROFF_SCC2 +# define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE +# define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK +# define CMXSCR_MASK (CMXSCR_SC2 |\ + CMXSCR_RS2CS_MSK |\ + CMXSCR_TS2CS_MSK) + +#elif (CONFIG_ETHER_INDEX == 3) +# define PROFF_ENET PROFF_SCC3 +# define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE +# define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK +# define CMXSCR_MASK (CMXSCR_SC3 |\ + CMXSCR_RS3CS_MSK |\ + CMXSCR_TS3CS_MSK) +#elif (CONFIG_ETHER_INDEX == 4) +# define PROFF_ENET PROFF_SCC4 +# define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE +# define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK +# define CMXSCR_MASK (CMXSCR_SC4 |\ + CMXSCR_RS4CS_MSK |\ + CMXSCR_TS4CS_MSK) + +#endif + + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +#define TOUT_LOOP 1000000 + +static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * SCC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +typedef volatile struct CommonBufferDescriptor { + cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ + cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ +} RTXBD; + +static RTXBD *rtx; + + +int eth_send(volatile void *packet, int length) +{ + int i; + int result = 0; + + if (length <= 0) { + printf("scc: bad packet size: %d\n", length); + goto out; + } + + for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + puts ("scc: tx buffer not ready\n"); + goto out; + } + } + + rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | + BD_ENET_TX_WRAP); + + for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + puts ("scc: tx error\n"); + goto out; + } + } + + /* return only status bits */ + result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; + + out: + return result; +} + + +int eth_rx(void) +{ + int length; + + for (;;) + { + if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = rtx->rxbd[rxIdx].cbd_datlen; + + if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) + { + printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); + } + else + { + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[rxIdx], length - 4); + } + + + /* Give the buffer back to the SCC. */ + rtx->rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | + BD_ENET_RX_EMPTY); + rxIdx = 0; + } + else { + rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + } + return length; +} + +/************************************************************** + * + * SCC Ethernet Initialization Routine + * + *************************************************************/ + +int eth_init(bd_t *bis) +{ + int i; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + scc_enet_t *pram_ptr; + uint dpaddr; + + rxIdx = 0; + txIdx = 0; + + /* assign static pointer to BD area */ + dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); + rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; + + /* 24.21 - (1-3): ioports have been set up already */ + + /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */ + immr->im_cpmux.cmx_uar = 0; + immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) | + CFG_CMXSCR_VALUE); + + + /* 24.21 (6) write RBASE and TBASE to parameter RAM */ + pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]); + pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); + pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); + + pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */ + pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */ + + pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */ + + pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ + pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ + + + /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */ + while(immr->im_cpm.cp_cpcr & CPM_CR_FLG); + immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE, + CPM_CR_ENET_SBLOCK, + 0x0c, + CPM_CR_INIT_TRX) | CPM_CR_FLG; + + /* 24.21 - (8-18): Set up parameter RAM */ + pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ + pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */ + pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ + + pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ + + pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ + + pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ + pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ + + pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ + pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ + + pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ + pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ + pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ + pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ + +# define ea bis->bi_enetaddr + pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; + pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; + pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; +# undef ea + + pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ + + pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ + pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ + pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ + pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ + + pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ + pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ + pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ + + + /* 24.21 - (19): Initialize RxBD */ + for (i = 0; i < PKTBUFSRX; i++) + { + rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx->rxbd[i].cbd_datlen = 0; /* Reset */ + rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; + } + + rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* 24.21 - (20): Initialize TxBD */ + for (i = 0; i < TX_BUF_CNT; i++) + { + rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | + BD_ENET_TX_LAST | + BD_ENET_TX_TC); + rtx->txbd[i].cbd_datlen = 0; /* Reset */ + rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; + } + + rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* 24.21 - (21): Write 0xffff to SCCE */ + immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0); + + /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */ + immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE | + SCCE_ENET_RXF | + SCCE_ENET_TXB); + + /* 24.21 - (23): we don't use ethernet interrupts */ + + /* 24.21 - (24): Clear GSMR_H to enable normal operations */ + immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0; + + /* 24.21 - (25): Clear GSMR_L to enable normal operations */ + immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI | + SCC_GSMRL_TPL_48 | + SCC_GSMRL_TPP_10 | + SCC_GSMRL_MODE_ENET); + + /* 24.21 - (26): Initialize DSR */ + immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555; + + /* 24.21 - (27): Initialize PSMR2 + * + * Settings: + * CRC = 32-Bit CCITT + * NIB = Begin searching for SFD 22 bits after RENA + * FDE = Full Duplex Enable + * BRO = Reject broadcast packets + * PROMISCOUS = Catch all packets regardless of dest. MAC adress + */ + immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC | + SCC_PSMR_NIB22 | +#if defined(CONFIG_SCC_ENET_FULL_DUPLEX) + SCC_PSMR_FDE | +#endif +#if defined(CONFIG_SCC_ENET_NO_BROADCAST) + SCC_PSMR_BRO | +#endif +#if defined(CONFIG_SCC_ENET_PROMISCOUS) + SCC_PSMR_PRO | +#endif + 0; + + /* 24.21 - (28): Write to GSMR_L to enable SCC */ + immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | + SCC_GSMRL_ENT); + + return 0; +} + + +void eth_halt(void) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | + SCC_GSMRL_ENT); +} + +#if 0 +void restart(void) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | + SCC_GSMRL_ENT); +} +#endif + +#endif /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */ diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c new file mode 100644 index 0000000..ea97ab8 --- /dev/null +++ b/cpu/mpc8260/i2c.c @@ -0,0 +1,768 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_HARD_I2C) + +#include +#include + +/* define to enable debug messages */ +#undef DEBUG_I2C + +/* uSec to wait between polls of the i2c */ +#define DELAY_US 100 +/* uSec to wait for the CPM to start processing the buffer */ +#define START_DELAY_US 1000 + +/* + * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the + * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP + */ +#define TOUT_LOOP 5 + +/*----------------------------------------------------------------------- + * Set default values + */ +#ifndef CFG_I2C_SPEED +#define CFG_I2C_SPEED 50000 +#endif + +#ifndef CFG_I2C_SLAVE +#define CFG_I2C_SLAVE 0xFE +#endif +/*----------------------------------------------------------------------- + */ + +typedef void (*i2c_ecb_t)(int, int, void *); /* error callback function */ + +/* This structure keeps track of the bd and buffer space usage. */ +typedef struct i2c_state { + int rx_idx; /* index to next free Rx BD */ + int tx_idx; /* index to next free Tx BD */ + void *rxbd; /* pointer to next free Rx BD */ + void *txbd; /* pointer to next free Tx BD */ + int tx_space; /* number of Tx bytes left */ + unsigned char *tx_buf; /* pointer to free Tx area */ + i2c_ecb_t err_cb; /* error callback function */ + void *cb_data; /* private data to be passed */ +} i2c_state_t; + +/* flags for i2c_send() and i2c_receive() */ +#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ +#define I2CF_START_COND 0x02 /* tx: generate start condition */ +#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ + +/* return codes */ +#define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */ +#define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */ +#define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */ +#define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/receive */ +#define I2CERR_IO_ERROR 5 /* had an error during comms */ + +/* error callback flags */ +#define I2CECB_RX_ERR 0x10 /* this is a receive error */ +#define I2CECB_RX_OV 0x02 /* receive overrun error */ +#define I2CECB_RX_MASK 0x0f /* mask for error bits */ +#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ +#define I2CECB_TX_CL 0x01 /* transmit collision error */ +#define I2CECB_TX_UN 0x02 /* transmit underflow error */ +#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ +#define I2CECB_TX_MASK 0x0f /* mask for error bits */ +#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ + +#define ERROR_I2C_NONE 0 +#define ERROR_I2C_LENGTH 1 + +#define I2C_WRITE_BIT 0x00 +#define I2C_READ_BIT 0x01 + +#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ + + +#define NUM_RX_BDS 4 +#define NUM_TX_BDS 4 +#define MAX_TX_SPACE 256 + +typedef struct I2C_BD +{ + unsigned short status; + unsigned short length; + unsigned char *addr; +} I2C_BD; +#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ + +#define BD_I2C_TX_CL 0x0001 /* collision error */ +#define BD_I2C_TX_UN 0x0002 /* underflow error */ +#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */ +#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL) + +#define BD_I2C_RX_ERR BD_SC_OV + +#ifdef DEBUG_I2C +#define PRINTD(x) printf x +#else +#define PRINTD(x) +#endif + +/* + * Returns the best value of I2BRG to meet desired clock speed of I2C with + * input parameters (clock speed, filter, and predivider value). + * It returns computer speed value and the difference between it and desired + * speed. + */ +static inline int +i2c_roundrate(int hz, int speed, int filter, int modval, + int *brgval, int *totspeed) +{ + int moddiv = 1 << (5-(modval & 3)), brgdiv, div; + + PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", + hz, speed, filter, modval)); + + div = moddiv * speed; + brgdiv = (hz + div - 1) / div; + + PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv)); + + *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter); + + if ((*brgval < 0) || (*brgval > 255)) { + PRINTD(("\t\trejected brgval=%d\n", *brgval)); + return -1; + } + + brgdiv = 2 * (*brgval + 3 + (2 * filter)); + div = moddiv * brgdiv ; + *totspeed = hz / div; + + PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed)); + + return 0; +} + +/* + * Sets the I2C clock predivider and divider to meet required clock speed. + */ +static int i2c_setrate(int hz, int speed) +{ + immap_t *immap = (immap_t *)CFG_IMMR ; + volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + int brgval, + modval, /* 0-3 */ + bestspeed_diff = speed, + bestspeed_brgval=0, + bestspeed_modval=0, + bestspeed_filter=0, + totspeed, + filter = 0; /* Use this fixed value */ + + for (modval = 0; modval < 4; modval++) + { + if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0) + { + int diff = speed - totspeed ; + + if ((diff >= 0) && (diff < bestspeed_diff)) + { + bestspeed_diff = diff ; + bestspeed_modval = modval; + bestspeed_brgval = brgval; + bestspeed_filter = filter; + } + } + } + + PRINTD(("[I2C] Best is:\n")); + PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", + hz, speed, + bestspeed_filter, bestspeed_modval, bestspeed_brgval, + bestspeed_diff)); + + i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); + i2c->i2c_i2brg = bestspeed_brgval & 0xff; + + PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg)); + + return 1 ; +} + +void i2c_init(int speed, int slaveadd) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm; + volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + volatile iic_t *iip; + ulong rbase, tbase; + volatile I2C_BD *rxbd, *txbd; + uint dpaddr; + +#ifdef CFG_I2C_INIT_BOARD + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#endif + + dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])); + if (dpaddr == 0) { + /* need to allocate dual port ram */ + dpaddr = m8260_cpm_dpalloc(64 + + (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) + + MAX_TX_SPACE, 64); + *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr; + } + + /* + * initialise data in dual port ram: + * + * dpaddr -> parameter ram (64 bytes) + * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes) + * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes) + * tx buffer (MAX_TX_SPACE bytes) + */ + + iip = (iic_t *)&immap->im_dprambase[dpaddr]; + memset((void*)iip, 0, sizeof(iic_t)); + + rbase = dpaddr + 64; + tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD); + + /* Disable interrupts */ + i2c->i2c_i2mod = 0x00; + i2c->i2c_i2cmr = 0x00; + i2c->i2c_i2cer = 0xff; + i2c->i2c_i2add = slaveadd; + + /* + * Set the I2C BRG Clock division factor from desired i2c rate + * and current CPU rate (we assume sccr dfbgr field is 0; + * divide BRGCLK by 1) + */ + PRINTD(("[I2C] Setting rate...\n")); + i2c_setrate (gd->brg_clk, CFG_I2C_SPEED) ; + + /* Set I2C controller in master mode */ + i2c->i2c_i2com = 0x01; + + /* Initialize Tx/Rx parameters */ + iip->iic_rbase = rbase; + iip->iic_tbase = tbase; + rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]); + txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]); + + PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase)); + PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase)); + PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); + PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + + /* Set big endian byte order */ + iip->iic_tfcr = 0x10; + iip->iic_rfcr = 0x10; + + /* Set maximum receive size. */ + iip->iic_mrblr = I2C_RXTX_LEN; + + cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE, + CPM_CR_I2C_SBLOCK, + 0x00, + CPM_CR_INIT_TRX) | CPM_CR_FLG; + do { + __asm__ __volatile__ ("eieio"); + } while (cp->cp_cpcr & CPM_CR_FLG); + + /* Clear events and interrupts */ + i2c->i2c_i2cer = 0xff; + i2c->i2c_i2cmr = 0x00; +} + +static +void i2c_newio(i2c_state_t *state) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile iic_t *iip; + uint dpaddr; + + PRINTD(("[I2C] i2c_newio\n")); + + dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])); + iip = (iic_t *)&immap->im_dprambase[dpaddr]; + state->rx_idx = 0; + state->tx_idx = 0; + state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase]; + state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase]; + state->tx_space = MAX_TX_SPACE; + state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); + state->err_cb = NULL; + state->cb_data = NULL; + + PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd)); + PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd)); + PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf)); + + /* clear the buffer memory */ + memset((char *)state->tx_buf, 0, MAX_TX_SPACE); +} + +static +int i2c_send(i2c_state_t *state, + unsigned char address, + unsigned char secondary_address, + unsigned int flags, + unsigned short size, + unsigned char *dataout) +{ + volatile I2C_BD *txbd; + int i,j; + + PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", + address, secondary_address, flags, size)); + + /* trying to send message larger than BD */ + if (size > I2C_RXTX_LEN) + return I2CERR_MSG_TOO_LONG; + + /* no more free bds */ + if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size)) + return I2CERR_NO_BUFFERS; + + txbd = (I2C_BD *)state->txbd; + txbd->addr = state->tx_buf; + + PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + + if (flags & I2CF_START_COND) + { + PRINTD(("[I2C] Formatting addresses...\n")); + if (flags & I2CF_ENABLE_SECONDARY) + { + txbd->length = size + 2; /* Length of message plus dest addresses */ + txbd->addr[0] = address << 1; + txbd->addr[1] = secondary_address; + i = 2; + } + else + { + txbd->length = size + 1; /* Length of message plus dest address */ + txbd->addr[0] = address << 1; /* Write destination address to BD */ + i = 1; + } + } + else + { + txbd->length = size; /* Length of message */ + i = 0; + } + + /* set up txbd */ + txbd->status = BD_SC_READY; + if (flags & I2CF_START_COND) + txbd->status |= BD_I2C_TX_START; + if (flags & I2CF_STOP_COND) + txbd->status |= BD_SC_LAST | BD_SC_WRAP; + + /* Copy data to send into buffer */ + PRINTD(("[I2C] copy data...\n")); + for(j = 0; j < size; i++, j++) + txbd->addr[i] = dataout[j]; + + PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + txbd->length, + txbd->status, + txbd->addr[0], + txbd->addr[1])); + + /* advance state */ + state->tx_buf += txbd->length; + state->tx_space -= txbd->length; + state->tx_idx++; + state->txbd = (void*)(txbd + 1); + + return 0; +} + +static +int i2c_receive(i2c_state_t *state, + unsigned char address, + unsigned char secondary_address, + unsigned int flags, + unsigned short size_to_expect, + unsigned char *datain) +{ + volatile I2C_BD *rxbd, *txbd; + + PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags)); + + /* Expected to receive too much */ + if (size_to_expect > I2C_RXTX_LEN) + return I2CERR_MSG_TOO_LONG; + + /* no more free bds */ + if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS + || state->tx_space < 2) + return I2CERR_NO_BUFFERS; + + rxbd = (I2C_BD *)state->rxbd; + txbd = (I2C_BD *)state->txbd; + + PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); + PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + + txbd->addr = state->tx_buf; + + /* set up TXBD for destination address */ + if (flags & I2CF_ENABLE_SECONDARY) + { + txbd->length = 2; + txbd->addr[0] = address << 1; /* Write data */ + txbd->addr[1] = secondary_address; /* Internal address */ + txbd->status = BD_SC_READY; + } + else + { + txbd->length = 1 + size_to_expect; + txbd->addr[0] = (address << 1) | 0x01; + txbd->status = BD_SC_READY; + memset(&txbd->addr[1], 0, txbd->length); + } + + /* set up rxbd for reception */ + rxbd->status = BD_SC_EMPTY; + rxbd->length = size_to_expect; + rxbd->addr = datain; + + txbd->status |= BD_I2C_TX_START; + if (flags & I2CF_STOP_COND) + { + txbd->status |= BD_SC_LAST | BD_SC_WRAP; + rxbd->status |= BD_SC_WRAP; + } + + PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + txbd->length, + txbd->status, + txbd->addr[0], + txbd->addr[1])); + PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + rxbd->length, + rxbd->status, + rxbd->addr[0], + rxbd->addr[1])); + + /* advance state */ + state->tx_buf += txbd->length; + state->tx_space -= txbd->length; + state->tx_idx++; + state->txbd = (void*)(txbd + 1); + state->rx_idx++; + state->rxbd = (void*)(rxbd + 1); + + return 0; +} + + +static +int i2c_doio(i2c_state_t *state) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile iic_t *iip; + volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + volatile I2C_BD *txbd, *rxbd; + int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0; + uint dpaddr; + + PRINTD(("[I2C] i2c_doio\n")); + + if (state->tx_idx <= 0 && state->rx_idx <= 0) { + PRINTD(("[I2C] No I/O is queued\n")); + return I2CERR_QUEUE_EMPTY; + } + + dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])); + iip = (iic_t *)&immap->im_dprambase[dpaddr]; + iip->iic_rbptr = iip->iic_rbase; + iip->iic_tbptr = iip->iic_tbase; + + /* Enable I2C */ + PRINTD(("[I2C] Enabling I2C...\n")); + i2c->i2c_i2mod |= 0x01; + + /* Begin transmission */ + i2c->i2c_i2com |= 0x80; + + /* Loop until transmit & receive completed */ + + if ((n = state->tx_idx) > 0) { + + txbd = ((I2C_BD*)state->txbd) - n; + for (i = 0; i < n; i++) { + txtimeo += TOUT_LOOP * txbd->length; + txbd++; + } + + txbd--; /* wait until last in list is done */ + + PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd)); + + udelay(START_DELAY_US); /* give it time to start */ + while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) { + udelay(DELAY_US); + if (ctrlc()) + return (-1); + __asm__ __volatile__ ("eieio"); + } + } + + if (txcnt < txtimeo && (n = state->rx_idx) > 0) { + + rxbd = ((I2C_BD*)state->rxbd) - n; + for (i = 0; i < n; i++) { + rxtimeo += TOUT_LOOP * rxbd->length; + rxbd++; + } + + rxbd--; /* wait until last in list is done */ + + PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd)); + + udelay(START_DELAY_US); /* give it time to start */ + while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) { + udelay(DELAY_US); + if (ctrlc()) + return (-1); + __asm__ __volatile__ ("eieio"); + } + } + + /* Turn off I2C */ + i2c->i2c_i2mod &= ~0x01; + + if ((n = state->tx_idx) > 0) { + for (i = 0; i < n; i++) { + txbd = ((I2C_BD*)state->txbd) - (n - i); + if ((b = txbd->status & BD_I2C_TX_ERR) != 0) { + if (state->err_cb != NULL) + (*state->err_cb)(I2CECB_TX_ERR|b, i, + state->cb_data); + if (rc == 0) + rc = I2CERR_IO_ERROR; + } + } + } + + if ((n = state->rx_idx) > 0) { + for (i = 0; i < n; i++) { + rxbd = ((I2C_BD*)state->rxbd) - (n - i); + if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) { + if (state->err_cb != NULL) + (*state->err_cb)(I2CECB_RX_ERR|b, i, + state->cb_data); + if (rc == 0) + rc = I2CERR_IO_ERROR; + } + } + } + + if ((txtimeo > 0 && txcnt >= txtimeo) || \ + (rxtimeo > 0 && rxcnt >= rxtimeo)) { + if (state->err_cb != NULL) + (*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data); + if (rc == 0) + rc = I2CERR_TIMEOUT; + } + + return (rc); +} + +static void +i2c_probe_callback(int flags, int xnum, void *data) +{ + /* + * the only acceptable errors are a transmit NAK or a receive + * overrun - tx NAK means the device does not exist, rx OV + * means the device must have responded to the slave address + * even though the transfer failed + */ + if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK)) + *(int *)data |= 1; + if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV)) + *(int *)data |= 2; +} + +int +i2c_probe(uchar chip) +{ + i2c_state_t state; + int rc, err_flag; + uchar buf[1]; + + i2c_newio(&state); + + state.err_cb = i2c_probe_callback; + state.cb_data = (void *) &err_flag; + err_flag = 0; + + rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf); + + if (rc != 0) + return (rc); /* probe failed */ + + rc = i2c_doio(&state); + + if (rc == 0) + return (0); /* device exists - read succeeded */ + + if (rc == I2CERR_TIMEOUT) + return (-1); /* device does not exist - timeout */ + + if (rc != I2CERR_IO_ERROR || err_flag == 0) + return (rc); /* probe failed */ + + if (err_flag & 1) + return (-1); /* device does not exist - had transmit NAK */ + + return (0); /* device exists - had receive overrun */ +} + + +int +i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + i2c_state_t state; + uchar xaddr[4]; + int rc; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address + * and the extra bits end up in the "chip address" bit slots. + * This makes a 24WC08 (1Kbyte) chip look like four 256 byte + * chips. + * + * Note that we consider the length of the address field to still + * be one byte because the extra address bits are hidden in the + * chip address. + */ + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + + i2c_newio(&state); + + rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); + if (rc != 0) { + printf("i2c_read: i2c_send failed (%d)\n", rc); + return 1; + } + + rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer); + if (rc != 0) { + printf("i2c_read: i2c_receive failed (%d)\n", rc); + return 1; + } + + rc = i2c_doio(&state); + if (rc != 0) { + printf("i2c_read: i2c_doio failed (%d)\n", rc); + return 1; + } + return 0; +} + +int +i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + i2c_state_t state; + uchar xaddr[4]; + int rc; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address + * and the extra bits end up in the "chip address" bit slots. + * This makes a 24WC08 (1Kbyte) chip look like four 256 byte + * chips. + * + * Note that we consider the length of the address field to still + * be one byte because the extra address bits are hidden in the + * chip address. + */ + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + + i2c_newio(&state); + + rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); + if (rc != 0) { + printf("i2c_write: first i2c_send failed (%d)\n", rc); + return 1; + } + + rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer); + if (rc != 0) { + printf("i2c_write: second i2c_send failed (%d)\n", rc); + return 1; + } + + rc = i2c_doio(&state); + if (rc != 0) { + printf("i2c_write: i2c_doio failed (%d)\n", rc); + return 1; + } + return 0; +} + +uchar +i2c_reg_read(uchar chip, uchar reg) +{ + uchar buf; + + i2c_read(chip, reg, 1, &buf, 1); + + return (buf); +} + +void +i2c_reg_write(uchar chip, uchar reg, uchar val) +{ + i2c_write(chip, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c new file mode 100644 index 0000000..b2e4d83 --- /dev/null +++ b/cpu/mpc8260/interrupts.c @@ -0,0 +1,279 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 + */ + +#include +#include +#include +#include +#include + +/****************************************************************************/ + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + ulong count; +}; + +static struct irq_action irq_handlers[NR_IRQS]; + +static ulong ppc_cached_irq_mask[NR_MASK_WORDS]; + +/****************************************************************************/ +/* this section was ripped out of arch/ppc/kernel/ppc8260_pic.c in the */ +/* Linux/PPC 2.4.x source. There was no copyright notice in that file. */ + +/* The 8260 internal interrupt controller. It is usually + * the only interrupt controller. + * There are two 32-bit registers (high/low) for up to 64 + * possible interrupts. + * + * Now, the fun starts.....Interrupt Numbers DO NOT MAP + * in a simple arithmetic fashion to mask or pending registers. + * That is, interrupt 4 does not map to bit position 4. + * We create two tables, indexed by vector number, to indicate + * which register to use and which bit in the register to use. + */ +static u_char irq_to_siureg[] = { + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u_char irq_to_siubit[] = { + 31, 16, 17, 18, 19, 20, 21, 22, + 23, 24, 25, 26, 27, 28, 29, 30, + 29, 30, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 27, 28, 31, + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 15, 14, 13, 12, 11, 10, 9, 8, + 7, 6, 5, 4, 3, 2, 1, 0 +}; + +static void m8260_mask_irq (unsigned int irq_nr) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + int bit, word; + volatile uint *simr; + + bit = irq_to_siubit[irq_nr]; + word = irq_to_siureg[irq_nr]; + + simr = &(immr->im_intctl.ic_simrh); + ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); + simr[word] = ppc_cached_irq_mask[word]; +} + +static void m8260_unmask_irq (unsigned int irq_nr) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + int bit, word; + volatile uint *simr; + + bit = irq_to_siubit[irq_nr]; + word = irq_to_siureg[irq_nr]; + + simr = &(immr->im_intctl.ic_simrh); + ppc_cached_irq_mask[word] |= (1 << (31 - bit)); + simr[word] = ppc_cached_irq_mask[word]; +} + +static void m8260_mask_and_ack (unsigned int irq_nr) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + int bit, word; + volatile uint *simr, *sipnr; + + bit = irq_to_siubit[irq_nr]; + word = irq_to_siureg[irq_nr]; + + simr = &(immr->im_intctl.ic_simrh); + sipnr = &(immr->im_intctl.ic_sipnrh); + ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); + simr[word] = ppc_cached_irq_mask[word]; + sipnr[word] = 1 << (31 - bit); +} + +static int m8260_get_irq (struct pt_regs *regs) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + int irq; + unsigned long bits; + + /* For MPC8260, read the SIVEC register and shift the bits down + * to get the irq number. */ + bits = immr->im_intctl.ic_sivec; + irq = bits >> 26; + return irq; +} + +/* end of code ripped out of arch/ppc/kernel/ppc8260_pic.c */ +/****************************************************************************/ + +int interrupt_init_cpu (unsigned *decrementer_count) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; + + /* Initialize the default interrupt mapping priorities */ + immr->im_intctl.ic_sicr = 0; + immr->im_intctl.ic_siprr = 0x05309770; + immr->im_intctl.ic_scprrh = 0x05309770; + immr->im_intctl.ic_scprrl = 0x05309770; + + /* disable all interrupts and clear all pending bits */ + immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0; + immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0; + immr->im_intctl.ic_sipnrh = 0xffffffff; + immr->im_intctl.ic_sipnrl = 0xffffffff; + +#ifdef CONFIG_HYMOD + /* + * ensure all external interrupt sources default to trigger on + * high-to-low transition (i.e. edge triggered active low) + */ + immr->im_intctl.ic_siexr = -1; +#endif + + return (0); +} + +/****************************************************************************/ + +/* + * Handle external interrupts + */ +void external_interrupt (struct pt_regs *regs) +{ + int irq, unmask = 1; + + irq = m8260_get_irq (regs); + + m8260_mask_and_ack (irq); + + enable_interrupts (); + + if (irq_handlers[irq].handler != NULL) + (*irq_handlers[irq].handler) (irq_handlers[irq].arg); + else { + printf ("\nBogus External Interrupt IRQ %d\n", irq); + /* + * turn off the bogus interrupt, otherwise it + * might repeat forever + */ + unmask = 0; + } + + if (unmask) + m8260_unmask_irq (irq); +} + +/****************************************************************************/ + +/* + * Install and free an interrupt handler. + */ + +void +irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) +{ + if (irq < 0 || irq >= NR_IRQS) { + printf ("irq_install_handler: bad irq number %d\n", irq); + return; + } + + if (irq_handlers[irq].handler != NULL) + printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n", + (ulong) handler, (ulong) irq_handlers[irq].handler); + + irq_handlers[irq].handler = handler; + irq_handlers[irq].arg = arg; + + m8260_unmask_irq (irq); +} + +void irq_free_handler (int irq) +{ + if (irq < 0 || irq >= NR_IRQS) { + printf ("irq_free_handler: bad irq number %d\n", irq); + return; + } + + m8260_mask_irq (irq); + + irq_handlers[irq].handler = NULL; + irq_handlers[irq].arg = NULL; +} + +/****************************************************************************/ + +void timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} + +/****************************************************************************/ + +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) + +/* ripped this out of ppc4xx/interrupts.c */ + +/******************************************************************************* +* +* irqinfo - print information about PCI devices +* +*/ +void +do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + int irq, re_enable; + + re_enable = disable_interrupts (); + + puts ("\nInterrupt-Information:\n" + "Nr Routine Arg Count\n"); + + for (irq = 0; irq < 32; irq++) + if (irq_handlers[irq].handler != NULL) + printf ("%02d %08lx %08lx %ld\n", irq, + (ulong) irq_handlers[irq].handler, + (ulong) irq_handlers[irq].arg, + irq_handlers[irq].count); + + if (re_enable) + enable_interrupts (); +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S new file mode 100644 index 0000000..2a25024 --- /dev/null +++ b/cpu/mpc8260/kgdb.S @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2000 Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define CONFIG_8260 1 /* needed for Linux kernel header files */ +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + + /* + * cache flushing routines for kgdb + */ + + .globl kgdb_flush_cache_all +kgdb_flush_cache_all: + mfspr r3, HID0 + ori r3, r3, HID0_ICFI|HID0_DCI /* Invalidate All */ + SYNC + mtspr HID0, r3 + blr + + .globl kgdb_flush_cache_range +kgdb_flush_cache_range: + li r5,CFG_CACHELINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,CFG_CACHELINE_SHIFT + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,CFG_CACHELINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,CFG_CACHELINE_SIZE + bdnz 2b + SYNC + blr + +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c new file mode 100644 index 0000000..44576de --- /dev/null +++ b/cpu/mpc8260/pci.c @@ -0,0 +1,449 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (c) 2005 MontaVista Software, Inc. + * Vitaly Bordug + * Added support for PCI bridge on MPC8272ADS + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include +/* + * Local->PCI map (from CPU) controlled by + * MPC826x master window + * + * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0 + * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1 + * + * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1) + * PCI Mem with prefetch + * + * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2) + * PCI Mem w/o prefetch + * + * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3) + * 32-bit PCI IO + * + * PCI->Local map (from PCI) + * MPC826x slave window controlled by + * + * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1) + * MPC826x local memory + */ + +/* + * Slave window that allows PCI masters to access MPC826x local memory. + * This window is set up using the first set of Inbound ATU registers + */ + +#ifndef CFG_PCI_SLV_MEM_LOCAL +#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#else +#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL +#endif + +#ifndef CFG_PCI_SLV_MEM_BUS +#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#else +#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS +#endif + +#ifndef CFG_PICMR0_MASK_ATTRIB +#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ + PICMR_PREFETCH_EN) +#else +#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB +#endif + +/* + * These are the windows that allow the CPU to access PCI address space. + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within + * these windows. + */ + +/* PCIBR0 */ +#ifndef CFG_PCI_MSTR0_LOCAL +#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ +#else +#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL +#endif + +#ifndef CFG_PCIMSK0_MASK +#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ +#else +#define PCIMSK0_MASK CFG_PCIMSK0_MASK +#endif + +/* PCIBR1 */ +#ifndef CFG_PCI_MSTR1_LOCAL +#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ +#else +#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL +#endif + +#ifndef CFG_PCIMSK1_MASK +#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ +#else +#define PCIMSK1_MASK CFG_PCIMSK1_MASK +#endif + +/* + * Master window that allows the CPU to access PCI Memory (prefetch). + * This window will be setup with the first set of Outbound ATU registers + * in the bridge. + */ + +#ifndef CFG_PCI_MSTR_MEM_LOCAL +#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#else +#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#endif + +#ifndef CFG_PCI_MSTR_MEM_BUS +#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#else +#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS +#endif + +#ifndef CFG_CPU_PCI_MEM_START +#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#else +#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START +#endif + +#ifndef CFG_PCI_MSTR_MEM_SIZE +#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ +#else +#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE +#endif + +#ifndef CFG_POCMR0_MASK_ATTRIB +#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) +#else +#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB +#endif + +/* + * Master window that allows the CPU to access PCI Memory (non-prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#ifndef CFG_PCI_MSTR_MEMIO_LOCAL +#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ +#else +#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL +#endif + +#ifndef CFG_PCI_MSTR_MEMIO_BUS +#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ +#else +#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS +#endif + +#ifndef CFG_CPU_PCI_MEMIO_START +#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#else +#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START +#endif + +#ifndef CFG_PCI_MSTR_MEMIO_SIZE +#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ +#else +#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE +#endif + +#ifndef CFG_POCMR1_MASK_ATTRIB +#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) +#else +#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB +#endif + +/* + * Master window that allows the CPU to access PCI IO space. + * This window will be setup with the third set of Outbound ATU registers + * in the bridge. + */ + +#ifndef CFG_PCI_MSTR_IO_LOCAL +#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ +#else +#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL +#endif + +#ifndef CFG_PCI_MSTR_IO_BUS +#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ +#else +#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS +#endif + +#ifndef CFG_CPU_PCI_IO_START +#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#else +#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START +#endif + +#ifndef CFG_PCI_MSTR_IO_SIZE +#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ +#else +#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE +#endif + +#ifndef CFG_POCMR2_MASK_ATTRIB +#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) +#else +#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB +#endif + +/* PCI bus configuration registers. + */ + +#define PCI_CLASS_BRIDGE_CTLR 0x06 + + +static inline void pci_outl (u32 addr, u32 data) +{ + *(volatile u32 *) addr = cpu_to_le32 (data); +} + +void pci_mpc8250_init (struct pci_controller *hose) +{ +#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 + DECLARE_GLOBAL_DATA_PTR; +#endif + u16 tempShort; + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + pci_dev_t host_devno = PCI_BDF (0, 0, 0); + + pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG, + CFG_IMMR + PCI_CFG_DATA_REG); + + /* + * Setting required to enable local bus for PCI (SIUMCR [LBPC]). + */ +#ifdef CONFIG_MPC8266ADS + immap->im_siu_conf.sc_siumcr = + (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) + | SIUMCR_LBPC01; +#elif defined CONFIG_MPC8272 + immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & + ~SIUMCR_BBD & + ~SIUMCR_ESE & + ~SIUMCR_PBSE & + ~SIUMCR_CDIS & + ~SIUMCR_DPPC11 & + ~SIUMCR_L2CPC11 & + ~SIUMCR_LBPC11 & + ~SIUMCR_APPC11 & + ~SIUMCR_CS10PC11 & + ~SIUMCR_BCTLC11 & + ~SIUMCR_MMR11) + | SIUMCR_DPPC11 + | SIUMCR_L2CPC01 + | SIUMCR_LBPC00 + | SIUMCR_APPC10 + | SIUMCR_CS10PC00 + | SIUMCR_BCTLC00 + | SIUMCR_MMR11; + +#else + /* + * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), + * and local bus for PCI (SIUMCR [LBPC]). + */ + immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & + ~SIUMCR_LBPC11 & + ~SIUMCR_CS10PC11 & + ~SIUMCR_LBPC11) | + SIUMCR_LBPC01 | + SIUMCR_CS10PC01 | + SIUMCR_APPC10; +#endif + + /* Make PCI lowest priority */ + /* Each 4 bits is a device bus request and the MS 4bits + is highest priority */ + /* Bus 4bit value + --- ---------- + CPM high 0b0000 + CPM middle 0b0001 + CPM low 0b0010 + PCI reguest 0b0011 + Reserved 0b0100 + Reserved 0b0101 + Internal Core 0b0110 + External Master 1 0b0111 + External Master 2 0b1000 + External Master 3 0b1001 + The rest are reserved */ + immap->im_siu_conf.sc_ppc_alrh = 0x61207893; + + /* Park bus on core while modifying PCI Bus accesses */ + immap->im_siu_conf.sc_ppc_acr = 0x6; + + /* + * Set up master windows that allow the CPU to access PCI space. These + * windows are set up using the two SIU PCIBR registers. + */ + immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; + immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; + +#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 + immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK; + immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE; +#endif + + /* Release PCI RST (by default the PCI RST signal is held low) */ + immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); + + /* give it some time */ + { +#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 + /* Give the PCI cards more time to initialize before query + This might be good for other boards also + */ + int i; + + for (i = 0; i < 1000; ++i) +#endif + udelay (1000); + } + + /* + * Set up master window that allows the CPU to access PCI Memory (prefetch) + * space. This window is set up using the first set of Outbound ATU registers. + */ + immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */ + immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ + immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */ + + /* + * Set up master window that allows the CPU to access PCI Memory (non-prefetch) + * space. This window is set up using the second set of Outbound ATU registers. + */ + immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ + immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ + immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */ + + /* + * Set up master window that allows the CPU to access PCI IO space. This window + * is set up using the third set of Outbound ATU registers. + */ + immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */ + immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */ + immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */ + + /* + * Set up slave window that allows PCI masters to access MPC826x local memory. + * This window is set up using the first set of Inbound ATU registers + */ + immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */ + immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */ + immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ + + /* See above for description - puts PCI request as highest priority */ +#ifdef CONFIG_MPC8272 + immap->im_siu_conf.sc_ppc_alrh = 0x01236745; +#else + immap->im_siu_conf.sc_ppc_alrh = 0x03124567; +#endif + + /* Park the bus on the PCI */ + immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; + + /* Host mode - specify the bridge as a host-PCI bridge */ + + pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE, + PCI_CLASS_BRIDGE_CTLR); + + /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ + pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort); + pci_hose_write_config_word (hose, host_devno, PCI_COMMAND, + tempShort | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); + + /* do some bridge init, should be done on all 8260 based bridges */ + pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, + 0x08); + pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, + 0xF8); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* System memory space */ +#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 + pci_set_region (hose->regions + 0, + PCI_SLV_MEM_BUS, + PCI_SLV_MEM_LOCAL, + gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); +#else + pci_set_region (hose->regions + 0, + CFG_SDRAM_BASE, + CFG_SDRAM_BASE, + 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); +#endif + + /* PCI memory space */ +#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 + pci_set_region (hose->regions + 1, + PCI_MSTR_MEMIO_BUS, + PCI_MSTR_MEMIO_LOCAL, + PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM); +#else + pci_set_region (hose->regions + 1, + PCI_MSTR_MEM_BUS, + PCI_MSTR_MEM_LOCAL, + PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); +#endif + + /* PCI I/O space */ + pci_set_region (hose->regions + 2, + PCI_MSTR_IO_BUS, + PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO); + + hose->region_count = 3; + + pci_register_hose (hose); + /* Mask off master abort machine checks */ + immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP); + eieio (); + + hose->last_busno = pci_hose_scan (hose); + + + /* clear the error in the error status register */ + immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); + + /* unmask master abort machine checks */ + immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); +} + +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c new file mode 100644 index 0000000..32016f2 --- /dev/null +++ b/cpu/mpc8260/serial_scc.c @@ -0,0 +1,498 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00. + */ + +/* + * Minimal serial functions needed to use one of the SCC ports + * as serial console interface. + */ + +#include +#include +#include + +#if defined(CONFIG_CONS_ON_SCC) + +#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ + +#define SCC_INDEX 0 +#define PROFF_SCC PROFF_SCC1 +#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ + CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) +#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK + +#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ + +#define SCC_INDEX 1 +#define PROFF_SCC PROFF_SCC2 +#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ + CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) +#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK + +#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ + +#define SCC_INDEX 2 +#define PROFF_SCC PROFF_SCC3 +#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ + CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) +#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK + +#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ + +#define SCC_INDEX 3 +#define PROFF_SCC PROFF_SCC4 +#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ + CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) +#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK + +#else + +#error "console not correctly defined" + +#endif + +int serial_init (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile scc_t *sp; + volatile scc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile cpm8260_t *cp = &(im->im_cpm); + uint dpaddr; + + /* initialize pointers to SCC */ + + sp = (scc_t *) &(im->im_scc[SCC_INDEX]); + up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; + + /* Disable transmitter/receiver. + */ + sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + /* put the SCC channel into NMSI (non multiplexd serial interface) + * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). + */ + im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE; + + /* Set up the baud rate generator. + */ + serial_setbrg (); + + /* Allocate space for two buffer descriptors in the DP ram. + * damm: allocating space after the two buffers for rx/tx data + */ + + dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; + rbdf->cbd_bufaddr = (uint) (rbdf+2); + rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; + tbdf->cbd_sc = BD_SC_WRAP; + + /* Set up the uart parameters in the parameter ram. + */ + up->scc_genscc.scc_rbase = dpaddr; + up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); + up->scc_genscc.scc_rfcr = CPMFCR_EB; + up->scc_genscc.scc_tfcr = CPMFCR_EB; + up->scc_genscc.scc_mrblr = 1; + up->scc_maxidl = 0; + up->scc_brkcr = 1; + up->scc_parec = 0; + up->scc_frmec = 0; + up->scc_nosec = 0; + up->scc_brkec = 0; + up->scc_uaddr1 = 0; + up->scc_uaddr2 = 0; + up->scc_toseq = 0; + up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; + up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; + up->scc_rccm = 0xc0ff; + + /* Mask all interrupts and remove anything pending. + */ + sp->scc_sccm = 0; + sp->scc_scce = 0xffff; + + /* Set 8 bit FIFO, 16 bit oversampling and UART mode. + */ + sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ + sp->scc_gsmrl = \ + SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; + + /* Set CTS flow control, 1 stop bit, 8 bit character length, + * normal async UART mode, no parity + */ + sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL; + + /* execute the "Init Rx and Tx params" CP command. + */ + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, + 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. + */ + sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; + + return (0); +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CONS_USE_EXTC) + m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate, + CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); +#else + m8260_cpm_setbrg(SCC_INDEX, gd->baudrate); +#endif +} + +void +serial_putc(const char c) +{ + volatile scc_uart_t *up; + volatile cbd_t *tbdf; + volatile immap_t *im; + + if (c == '\n') + serial_putc ('\r'); + + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; + tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; + + /* Wait for last character to go. + */ + while (tbdf->cbd_sc & BD_SC_READY) + ; + + /* Load the character into the transmit buffer. + */ + *(volatile char *)tbdf->cbd_bufaddr = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int +serial_getc(void) +{ + volatile cbd_t *rbdf; + volatile scc_uart_t *up; + volatile immap_t *im; + unsigned char c; + + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; + rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; + + /* Wait for character to show up. + */ + while (rbdf->cbd_sc & BD_SC_EMPTY) + ; + + /* Grab the char and clear the buffer again. + */ + c = *(volatile unsigned char *)rbdf->cbd_bufaddr; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return (c); +} + +int +serial_tstc() +{ + volatile cbd_t *rbdf; + volatile scc_uart_t *up; + volatile immap_t *im; + + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; + rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; + + return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); +} + +#endif /* CONFIG_CONS_ON_SCC */ + +#if defined(CONFIG_KGDB_ON_SCC) + +#if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX +#error Whoops! serial console and kgdb are on the same scc serial port +#endif + +#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SCC1 */ + +#define KGDB_SCC_INDEX 0 +#define KGDB_PROFF_SCC PROFF_SCC1 +#define KGDB_CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ + CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) +#define KGDB_CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) +#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE +#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK + +#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SCC2 */ + +#define KGDB_SCC_INDEX 1 +#define KGDB_PROFF_SCC PROFF_SCC2 +#define KGDB_CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ + CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) +#define KGDB_CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) +#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE +#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK + +#elif CONFIG_KGDB_INDEX == 3 /* KGDB Port on SCC3 */ + +#define KGDB_SCC_INDEX 2 +#define KGDB_PROFF_SCC PROFF_SCC3 +#define KGDB_CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ + CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) +#define KGDB_CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) +#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE +#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK + +#elif CONFIG_KGDB_INDEX == 4 /* KGDB Port on SCC4 */ + +#define KGDB_SCC_INDEX 3 +#define KGDB_PROFF_SCC PROFF_SCC4 +#define KGDB_CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ + CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) +#define KGDB_CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) +#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE +#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK + +#else + +#error "kgdb serial port not correctly defined" + +#endif + +void +kgdb_serial_init (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile scc_t *sp; + volatile scc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile cpm8260_t *cp = &(im->im_cpm); + uint dpaddr, speed = CONFIG_KGDB_BAUDRATE; + char *s, *e; + + if ((s = getenv("kgdbrate")) != NULL && *s != '\0') { + ulong rate = simple_strtoul(s, &e, 10); + if (e > s && *e == '\0') + speed = rate; + } + + /* initialize pointers to SCC */ + + sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]); + up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; + + /* Disable transmitter/receiver. + */ + sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + /* put the SCC channel into NMSI (non multiplexd serial interface) + * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). + */ + im->im_cpmux.cmx_scr = \ + (im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) | KGDB_CMXSCR_VALUE; + + /* Set up the baud rate generator. + */ +#if defined(CONFIG_KGDB_USE_EXTC) + m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed, + CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); +#else + m8260_cpm_setbrg(KGDB_SCC_INDEX, speed); +#endif + + /* Allocate space for two buffer descriptors in the DP ram. + * damm: allocating space after the two buffers for rx/tx data + */ + + dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; + rbdf->cbd_bufaddr = (uint) (rbdf+2); + rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; + tbdf->cbd_sc = BD_SC_WRAP; + + /* Set up the uart parameters in the parameter ram. + */ + up->scc_genscc.scc_rbase = dpaddr; + up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); + up->scc_genscc.scc_rfcr = CPMFCR_EB; + up->scc_genscc.scc_tfcr = CPMFCR_EB; + up->scc_genscc.scc_mrblr = 1; + up->scc_maxidl = 0; + up->scc_brkcr = 1; + up->scc_parec = 0; + up->scc_frmec = 0; + up->scc_nosec = 0; + up->scc_brkec = 0; + up->scc_uaddr1 = 0; + up->scc_uaddr2 = 0; + up->scc_toseq = 0; + up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; + up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; + up->scc_rccm = 0xc0ff; + + /* Mask all interrupts and remove anything pending. + */ + sp->scc_sccm = 0; + sp->scc_scce = 0xffff; + + /* Set 8 bit FIFO, 16 bit oversampling and UART mode. + */ + sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ + sp->scc_gsmrl = \ + SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; + + /* Set CTS flow control, 1 stop bit, 8 bit character length, + * normal async UART mode, no parity + */ + sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL; + + /* execute the "Init Rx and Tx params" CP command. + */ + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK, + 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. + */ + sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; + + printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed); +} + +void +putDebugChar(const char c) +{ + volatile scc_uart_t *up; + volatile cbd_t *tbdf; + volatile immap_t *im; + + if (c == '\n') + putDebugChar ('\r'); + + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; + tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; + + /* Wait for last character to go. + */ + while (tbdf->cbd_sc & BD_SC_READY) + ; + + /* Load the character into the transmit buffer. + */ + *(volatile char *)tbdf->cbd_bufaddr = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; +} + +void +putDebugStr (const char *s) +{ + while (*s) { + putDebugChar (*s++); + } +} + +int +getDebugChar(void) +{ + volatile cbd_t *rbdf; + volatile scc_uart_t *up; + volatile immap_t *im; + unsigned char c; + + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; + rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; + + /* Wait for character to show up. + */ + while (rbdf->cbd_sc & BD_SC_EMPTY) + ; + + /* Grab the char and clear the buffer again. + */ + c = *(volatile unsigned char *)rbdf->cbd_bufaddr; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return (c); +} + +void +kgdb_interruptible(int yes) +{ + return; +} + +#endif /* CONFIG_KGDB_ON_SCC */ diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c new file mode 100644 index 0000000..b486f83 --- /dev/null +++ b/cpu/mpc8260/serial_smc.c @@ -0,0 +1,462 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with + * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the + * Linux/PPC sources (m8260_tty.c had no copyright info in it). + */ + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +#include +#include +#include + +#if defined(CONFIG_CONS_ON_SMC) + +#if CONFIG_CONS_INDEX == 1 /* Console on SMC1 */ + +#define SMC_INDEX 0 +#define PROFF_SMC_BASE PROFF_SMC1_BASE +#define PROFF_SMC PROFF_SMC1 +#define CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE +#define CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK +#define CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK) +#define CMXSMR_VALUE CMXSMR_SMC1CS_BRG7 + +#elif CONFIG_CONS_INDEX == 2 /* Console on SMC2 */ + +#define SMC_INDEX 1 +#define PROFF_SMC_BASE PROFF_SMC2_BASE +#define PROFF_SMC PROFF_SMC2 +#define CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE +#define CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK +#define CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK) +#define CMXSMR_VALUE CMXSMR_SMC2CS_BRG8 + +#else + +#error "console not correctly defined" + +#endif + +/* map rs_table index to baud rate generator index */ +static unsigned char brg_map[] = { + 6, /* BRG7 for SMC1 */ + 7, /* BRG8 for SMC2 */ + 0, /* BRG1 for SCC1 */ + 1, /* BRG1 for SCC2 */ + 2, /* BRG1 for SCC3 */ + 3, /* BRG1 for SCC4 */ +}; + +int serial_init (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile smc_t *sp; + volatile smc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile cpm8260_t *cp = &(im->im_cpm); + uint dpaddr; + + /* initialize pointers to SMC */ + + sp = (smc_t *) &(im->im_smc[SMC_INDEX]); + *(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC; + up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC]; + + /* Disable transmitter/receiver. + */ + sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); + + /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ + + /* Allocate space for two buffer descriptors in the DP ram. + * damm: allocating space after the two buffers for rx/tx data + */ + + dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; + rbdf->cbd_bufaddr = (uint) (rbdf+2); + rbdf->cbd_sc = 0; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; + tbdf->cbd_sc = 0; + + /* Set up the uart parameters in the parameter ram. + */ + up->smc_rbase = dpaddr; + up->smc_tbase = dpaddr+sizeof(cbd_t); + up->smc_rfcr = CPMFCR_EB; + up->smc_tfcr = CPMFCR_EB; + up->smc_brklen = 0; + up->smc_brkec = 0; + up->smc_brkcr = 0; + + /* Set UART mode, 8 bit, no parity, one stop. + * Enable receive and transmit. + */ + sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; + + /* Mask all interrupts and remove anything pending. + */ + sp->smc_smcm = 0; + sp->smc_smce = 0xff; + + /* put the SMC channel into NMSI (non multiplexd serial interface) + * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). + */ + im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE; + + /* Set up the baud rate generator. + */ + serial_setbrg (); + + /* Make the first buffer the only buffer. + */ + tbdf->cbd_sc |= BD_SC_WRAP; + rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + + /* Single character receive. + */ + up->smc_mrblr = 1; + up->smc_maxidl = 0; + + /* Initialize Tx/Rx parameters. + */ + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK, + 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. + */ + sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; + + return (0); +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CONS_USE_EXTC) + m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate, + CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); +#else + m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate); +#endif +} + +void +serial_putc(const char c) +{ + volatile cbd_t *tbdf; + volatile char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + + if (c == '\n') + serial_putc ('\r'); + + up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); + + tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase]; + + /* Wait for last character to go. + */ + buf = (char *)tbdf->cbd_bufaddr; + while (tbdf->cbd_sc & BD_SC_READY) + ; + + *buf = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int +serial_getc(void) +{ + volatile cbd_t *rbdf; + volatile unsigned char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + unsigned char c; + + up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); + + rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; + + /* Wait for character to show up. + */ + buf = (unsigned char *)rbdf->cbd_bufaddr; + while (rbdf->cbd_sc & BD_SC_EMPTY) + ; + c = *buf; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return(c); +} + +int +serial_tstc() +{ + volatile cbd_t *rbdf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + + up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); + + rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; + + return(!(rbdf->cbd_sc & BD_SC_EMPTY)); +} + +#endif /* CONFIG_CONS_ON_SMC */ + +#if defined(CONFIG_KGDB_ON_SMC) + +#if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX +#error Whoops! serial console and kgdb are on the same smc serial port +#endif + +#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SMC1 */ + +#define KGDB_SMC_INDEX 0 +#define KGDB_PROFF_SMC_BASE PROFF_SMC1_BASE +#define KGDB_PROFF_SMC PROFF_SMC1 +#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE +#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK +#define KGDB_CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK) +#define KGDB_CMXSMR_VALUE CMXSMR_SMC1CS_BRG7 + +#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SMC2 */ + +#define KGDB_SMC_INDEX 1 +#define KGDB_PROFF_SMC_BASE PROFF_SMC2_BASE +#define KGDB_PROFF_SMC PROFF_SMC2 +#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE +#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK +#define KGDB_CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK) +#define KGDB_CMXSMR_VALUE CMXSMR_SMC2CS_BRG8 + +#else + +#error "console not correctly defined" + +#endif + +void +kgdb_serial_init (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile smc_t *sp; + volatile smc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile cpm8260_t *cp = &(im->im_cpm); + uint dpaddr, speed = CONFIG_KGDB_BAUDRATE; + char *s, *e; + + if ((s = getenv("kgdbrate")) != NULL && *s != '\0') { + ulong rate = simple_strtoul(s, &e, 10); + if (e > s && *e == '\0') + speed = rate; + } + + /* initialize pointers to SMC */ + + sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]); + *(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC; + up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC]; + + /* Disable transmitter/receiver. + */ + sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); + + /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ + + /* Allocate space for two buffer descriptors in the DP ram. + * damm: allocating space after the two buffers for rx/tx data + */ + + dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; + rbdf->cbd_bufaddr = (uint) (rbdf+2); + rbdf->cbd_sc = 0; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; + tbdf->cbd_sc = 0; + + /* Set up the uart parameters in the parameter ram. + */ + up->smc_rbase = dpaddr; + up->smc_tbase = dpaddr+sizeof(cbd_t); + up->smc_rfcr = CPMFCR_EB; + up->smc_tfcr = CPMFCR_EB; + up->smc_brklen = 0; + up->smc_brkec = 0; + up->smc_brkcr = 0; + + /* Set UART mode, 8 bit, no parity, one stop. + * Enable receive and transmit. + */ + sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; + + /* Mask all interrupts and remove anything pending. + */ + sp->smc_smcm = 0; + sp->smc_smce = 0xff; + + /* put the SMC channel into NMSI (non multiplexd serial interface) + * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). + */ + im->im_cpmux.cmx_smr = + (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE; + + /* Set up the baud rate generator. + */ +#if defined(CONFIG_KGDB_USE_EXTC) + m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed, + CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); +#else + m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed); +#endif + + /* Make the first buffer the only buffer. + */ + tbdf->cbd_sc |= BD_SC_WRAP; + rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + + /* Single character receive. + */ + up->smc_mrblr = 1; + up->smc_maxidl = 0; + + /* Initialize Tx/Rx parameters. + */ + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK, + 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. + */ + sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; + + printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed); +} + +void +putDebugChar(const char c) +{ + volatile cbd_t *tbdf; + volatile char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + + if (c == '\n') + putDebugChar ('\r'); + + up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); + + tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase]; + + /* Wait for last character to go. + */ + buf = (char *)tbdf->cbd_bufaddr; + while (tbdf->cbd_sc & BD_SC_READY) + ; + + *buf = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; +} + +void +putDebugStr (const char *s) +{ + while (*s) { + putDebugChar (*s++); + } +} + +int +getDebugChar(void) +{ + volatile cbd_t *rbdf; + volatile unsigned char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + unsigned char c; + + up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); + + rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; + + /* Wait for character to show up. + */ + buf = (unsigned char *)rbdf->cbd_bufaddr; + while (rbdf->cbd_sc & BD_SC_EMPTY) + ; + c = *buf; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return(c); +} + +void +kgdb_interruptible(int yes) +{ + return; +} + +#endif /* CONFIG_KGDB_ON_SMC */ diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c new file mode 100644 index 0000000..a761a17 --- /dev/null +++ b/cpu/mpc8260/speed.c @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +/* Bus-to-Core Multiplier */ +#define _1x 2 +#define _1_5x 3 +#define _2x 4 +#define _2_5x 5 +#define _3x 6 +#define _3_5x 7 +#define _4x 8 +#define _4_5x 9 +#define _5x 10 +#define _5_5x 11 +#define _6x 12 +#define _6_5x 13 +#define _7x 14 +#define _7_5x 15 +#define _8x 16 +#define _byp -1 +#define _off -2 +#define _unk -3 + +typedef struct { + int b2c_mult; + int vco_div; + char *freq_60x; + char *freq_core; +} corecnf_t; + +/* + * this table based on "Errata to MPC8260 PowerQUICC II User's Manual", + * Rev. 1, 8/2000, page 10. + */ +corecnf_t corecnf_tab[] = { + { _1_5x, 4, " 33-100", " 33-100" }, /* 0x00 */ + { _1x, 4, " 50-150", " 50-150" }, /* 0x01 */ + { _1x, 8, " 25-75 ", " 25-75 " }, /* 0x02 */ + { _byp, -1, " ?-? ", " ?-? " }, /* 0x03 */ + { _2x, 2, " 50-150", "100-300" }, /* 0x04 */ + { _2x, 4, " 25-75 ", " 50-150" }, /* 0x05 */ + { _2_5x, 2, " 40-120", "100-240" }, /* 0x06 */ + { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x07 */ + { _3x, 2, " 33-100", "100-300" }, /* 0x08 */ + { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x09 */ + { _4x, 2, " 25-75 ", "100-300" }, /* 0x0A */ + { _5x, 2, " 20-60 ", "100-300" }, /* 0x0B */ + { _1_5x, 8, " 16-50 ", " 16-50 " }, /* 0x0C */ + { _6x, 2, " 16-50 ", "100-300" }, /* 0x0D */ + { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x0E */ + { _off, -1, " ?-? ", " ?-? " }, /* 0x0F */ + { _3x, 4, " 16-50 ", " 50-150" }, /* 0x10 */ + { _2_5x, 4, " 20-60 ", " 50-120" }, /* 0x11 */ + { _6_5x, 2, " 15-46 ", "100-300" }, /* 0x12 */ + { _byp, -1, " ?-? ", " ?-? " }, /* 0x13 */ + { _7x, 2, " 14-43 ", "100-300" }, /* 0x14 */ + { _2x, 4, " 25-75 ", " 50-150" }, /* 0x15 */ + { _7_5x, 2, " 13-40 ", "100-300" }, /* 0x16 */ + { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x17 */ + { _unk, -1, " ?-? ", " ?-? " }, /* 0x18 */ + { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x19 */ + { _4x, 2, " 25-75 ", "100-300" }, /* 0x1A */ + { _5x, 2, " 20-60 ", "100-300" }, /* 0x1B */ + { _8x, 2, " 12-38 ", "100-300" }, /* 0x1C */ + { _6x, 2, " 16-50 ", "100-300" }, /* 0x1D */ + { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x1E */ + { _off, -1, " ?-? ", " ?-? " }, /* 0x1F */ +}; + +/* ------------------------------------------------------------------------- */ + +/* + * + */ + +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + ulong clkin; + ulong sccr, dfbrg; + ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; + corecnf_t *cp; + +#if !defined(CONFIG_8260_CLKIN) +#error clock measuring not implemented yet - define CONFIG_8260_CLKIN +#else + clkin = CONFIG_8260_CLKIN; +#endif + + sccr = immap->im_clkrst.car_sccr; + dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; + + scmr = immap->im_clkrst.car_scmr; + corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; + cp = &corecnf_tab[corecnf]; + + busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; + cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; + + /* HiP7, HiP7 Rev01, HiP7 RevA */ + if ((get_pvr () == PVR_8260_HIP7) || + (get_pvr () == PVR_8260_HIP7R1) || + (get_pvr () == PVR_8260_HIP7RA)) { + pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT; + gd->vco_out = clkin * (pllmf + 1); + } else { /* HiP3, HiP4 */ + pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; + plldf = (scmr & SCMR_PLLDF) ? 1 : 0; + gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); + } +#if 0 + if (gd->vco_out / (busdf + 1) != clkin) { + /* aaarrrggghhh!!! */ + return (1); + } +#endif + + gd->cpm_clk = gd->vco_out / 2; + gd->bus_clk = clkin; + gd->scc_clk = gd->vco_out / 4; + gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); + + if (cp->b2c_mult > 0) { + gd->cpu_clk = (clkin * cp->b2c_mult) / 2; + } else { + gd->cpu_clk = clkin; + } + + return (0); +} + +int prt_8260_clks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + ulong sccr, dfbrg; + ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; + corecnf_t *cp; + + sccr = immap->im_clkrst.car_sccr; + dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; + + scmr = immap->im_clkrst.car_scmr; + corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; + busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; + cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; + plldf = (scmr & SCMR_PLLDF) ? 1 : 0; + pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; + + cp = &corecnf_tab[corecnf]; + + puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult "); + + switch (cp->b2c_mult) { + case _byp: + puts ("BYPASS"); + break; + + case _off: + puts ("OFF"); + break; + + case _unk: + puts ("UNKNOWN"); + break; + + default: + printf ("%d%sx", + cp->b2c_mult / 2, + (cp->b2c_mult % 2) ? ".5" : ""); + break; + } + + printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n", + cp->vco_div, cp->freq_60x, cp->freq_core); + + printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, " + "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf, + pllmf); + + printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n", + gd->vco_out, gd->scc_clk, gd->brg_clk); + + printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", + gd->cpu_clk, gd->cpm_clk, gd->bus_clk); + + if (sccr & SCCR_PCI_MODE) { + uint pci_div; + + pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) * + ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1); + + printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div); + } + putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8260/speed.h b/cpu/mpc8260/speed.h new file mode 100644 index 0000000..b66393b --- /dev/null +++ b/cpu/mpc8260/speed.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*----------------------------------------------------------------------- + * Timer value for timer 2, ICLK = 10 + * + * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) + * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 + * + * SPEED_FCOUNT2 timer 2 counting frequency + * GCLK CPU clock + * SPEED_TMR2_PS prescaler + */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ + +/*----------------------------------------------------------------------- + * Timer value for PIT + * + * PIT_TIME = SPEED_PITC / PITRTCLK + * PITRTCLK = 8192 + */ +#define SPEED_PITC (82 << 16) /* start counting from 82 */ + +/* + * The new value for PTA is calculated from + * + * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) + * + * gclk CPU clock (not bus clock !) + * Trefresh Refresh cycle * 4 (four word bursts used) + * DFBRG For normal mode (no clock reduction) always 0 + * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) + * NCS Number of SDRAM banks (chip selects) on this UPM. + */ diff --git a/cpu/mpc8260/spi.c b/cpu/mpc8260/spi.c new file mode 100644 index 0000000..c1a607c --- /dev/null +++ b/cpu/mpc8260/spi.c @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2001 Navin Boppuri / Prashant Patel + * , + * + * Copyright (c) 2001 Gerd Mennchen + * Copyright (c) 2001-2003 Wolfgang Denk, DENX Software Engineering, . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8260 CPM SPI interface. + * + * Parts of this code are probably not portable and/or specific to + * the board which I used for the tests. Please send fixes/complaints + * to wd@denx.de + * + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SPI) + +/* Warning: + * You cannot enable DEBUG for early system initalization, i. e. when + * this driver is used to read environment parameters like "baudrate" + * from EEPROM which are used to initialize the serial port which is + * needed to print the debug messages... + */ +#undef DEBUG + +#define SPI_EEPROM_WREN 0x06 +#define SPI_EEPROM_RDSR 0x05 +#define SPI_EEPROM_READ 0x03 +#define SPI_EEPROM_WRITE 0x02 + +/* --------------------------------------------------------------- + * Offset for initial SPI buffers in DPRAM: + * We need a 520 byte scratch DPRAM area to use at an early stage. + * It is used between the two initialization calls (spi_init_f() + * and spi_init_r()). + * The value 0x2000 makes it far enough from the start of the data + * area (as well as from the stack pointer). + * --------------------------------------------------------------- */ +#ifndef CFG_SPI_INIT_OFFSET +#define CFG_SPI_INIT_OFFSET 0x2000 +#endif + +#define CPM_SPI_BASE 0x100 + +#ifdef DEBUG + +#define DPRINT(a) printf a; +/* ----------------------------------------------- + * Helper functions to peek into tx and rx buffers + * ----------------------------------------------- */ +static const char * const hex_digit = "0123456789ABCDEF"; + +static char quickhex (int i) +{ + return hex_digit[i]; +} + +static void memdump (void *pv, int num) +{ + int i; + unsigned char *pc = (unsigned char *) pv; + + for (i = 0; i < num; i++) + printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); + printf ("\t"); + for (i = 0; i < num; i++) + printf ("%c", isprint (pc[i]) ? pc[i] : '.'); + printf ("\n"); +} +#else /* !DEBUG */ + +#define DPRINT(a) + +#endif /* DEBUG */ + +/* ------------------- + * Function prototypes + * ------------------- */ +void spi_init (void); + +ssize_t spi_read (uchar *, int, uchar *, int); +ssize_t spi_write (uchar *, int, uchar *, int); +ssize_t spi_xfer (size_t); + +/* ------------------- + * Variables + * ------------------- */ + +#define MAX_BUFFER 0x104 + +/* ---------------------------------------------------------------------- + * Initially we place the RX and TX buffers at a fixed location in DPRAM! + * ---------------------------------------------------------------------- */ +static uchar *rxbuf = + (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase + [CFG_SPI_INIT_OFFSET]; +static uchar *txbuf = + (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase + [CFG_SPI_INIT_OFFSET+MAX_BUFFER]; + +/* ************************************************************************** + * + * Function: spi_init_f + * + * Description: Init SPI-Controller (ROM part) + * + * return: --- + * + * *********************************************************************** */ +void spi_init_f (void) +{ + unsigned int dpaddr; + + volatile spi_t *spi; + volatile immap_t *immr; + volatile cpm8260_t *cp; + volatile cbd_t *tbdf, *rbdf; + + immr = (immap_t *) CFG_IMMR; + cp = (cpm8260_t *) &immr->im_cpm; + + *(ushort *)(&immr->im_dprambase[PROFF_SPI_BASE]) = PROFF_SPI; + spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; + +/* 1 */ + /* ------------------------------------------------ + * Initialize Port D SPI pins + * (we are only in Master Mode !) + * ------------------------------------------------ */ + + /* -------------------------------------------- + * GPIO or per. Function + * PPARD[16] = 1 [0x00008000] (SPIMISO) + * PPARD[17] = 1 [0x00004000] (SPIMOSI) + * PPARD[18] = 1 [0x00002000] (SPICLK) + * PPARD[12] = 0 [0x00080000] -> GPIO: (CS for ATC EEPROM) + * -------------------------------------------- */ + immr->im_ioport.iop_ppard |= 0x0000E000; /* set bits */ + immr->im_ioport.iop_ppard &= ~0x00080000; /* reset bit */ + + /* ---------------------------------------------- + * In/Out or per. Function 0/1 + * PDIRD[16] = 0 [0x00008000] -> PERI1: SPIMISO + * PDIRD[17] = 0 [0x00004000] -> PERI1: SPIMOSI + * PDIRD[18] = 0 [0x00002000] -> PERI1: SPICLK + * PDIRD[12] = 1 [0x00080000] -> GPIO OUT: CS for ATC EEPROM + * ---------------------------------------------- */ + immr->im_ioport.iop_pdird &= ~0x0000E000; + immr->im_ioport.iop_pdird |= 0x00080000; + + /* ---------------------------------------------- + * special option reg. + * PSORD[16] = 1 [0x00008000] -> SPIMISO + * PSORD[17] = 1 [0x00004000] -> SPIMOSI + * PSORD[18] = 1 [0x00002000] -> SPICLK + * ---------------------------------------------- */ + immr->im_ioport.iop_psord |= 0x0000E000; + + /* Initialize the parameter ram. + * We need to make sure many things are initialized to zero + */ + spi->spi_rstate = 0; + spi->spi_rdp = 0; + spi->spi_rbptr = 0; + spi->spi_rbc = 0; + spi->spi_rxtmp = 0; + spi->spi_tstate = 0; + spi->spi_tdp = 0; + spi->spi_tbptr = 0; + spi->spi_tbc = 0; + spi->spi_txtmp = 0; + + /* Allocate space for one transmit and one receive buffer + * descriptor in the DP ram + */ +#ifdef CFG_ALLOC_DPRAM + dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8); +#else + dpaddr = CPM_SPI_BASE; +#endif + +/* 3 */ + /* Set up the SPI parameters in the parameter ram */ + spi->spi_rbase = dpaddr; + spi->spi_tbase = dpaddr + sizeof (cbd_t); + + /***********IMPORTANT******************/ + + /* + * Setting transmit and receive buffer descriptor pointers + * initially to rbase and tbase. Only the microcode patches + * documentation talks about initializing this pointer. This + * is missing from the sample I2C driver. If you dont + * initialize these pointers, the kernel hangs. + */ + spi->spi_rbptr = spi->spi_rbase; + spi->spi_tbptr = spi->spi_tbase; + +/* 4 */ + /* Init SPI Tx + Rx Parameters */ + while (cp->cp_cpcr & CPM_CR_FLG) + ; + cp->cp_cpcr = mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, + 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; + while (cp->cp_cpcr & CPM_CR_FLG) + ; + +/* 6 */ + /* Set to big endian. */ + spi->spi_tfcr = CPMFCR_EB; + spi->spi_rfcr = CPMFCR_EB; + +/* 7 */ + /* Set maximum receive size. */ + spi->spi_mrblr = MAX_BUFFER; + +/* 8 + 9 */ + /* tx and rx buffer descriptors */ + tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; + rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; + + tbdf->cbd_sc &= ~BD_SC_READY; + rbdf->cbd_sc &= ~BD_SC_EMPTY; + + /* Set the bd's rx and tx buffer address pointers */ + rbdf->cbd_bufaddr = (ulong) rxbuf; + tbdf->cbd_bufaddr = (ulong) txbuf; + +/* 10 + 11 */ + immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ + immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ + + + return; +} + +/* ************************************************************************** + * + * Function: spi_init_r + * + * Description: Init SPI-Controller (RAM part) - + * The malloc engine is ready and we can move our buffers to + * normal RAM + * + * return: --- + * + * *********************************************************************** */ +void spi_init_r (void) +{ + volatile spi_t *spi; + volatile immap_t *immr; + volatile cpm8260_t *cp; + volatile cbd_t *tbdf, *rbdf; + + immr = (immap_t *) CFG_IMMR; + cp = (cpm8260_t *) &immr->im_cpm; + + spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; + + /* tx and rx buffer descriptors */ + tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; + rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; + + /* Allocate memory for RX and TX buffers */ + rxbuf = (uchar *) malloc (MAX_BUFFER); + txbuf = (uchar *) malloc (MAX_BUFFER); + + rbdf->cbd_bufaddr = (ulong) rxbuf; + tbdf->cbd_bufaddr = (ulong) txbuf; + + return; +} + +/**************************************************************************** + * Function: spi_write + **************************************************************************** */ +ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) +{ + int i; + + memset(rxbuf, 0, MAX_BUFFER); + memset(txbuf, 0, MAX_BUFFER); + *txbuf = SPI_EEPROM_WREN; /* write enable */ + spi_xfer(1); + memcpy(txbuf, addr, alen); + *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ + memcpy(alen + txbuf, buffer, len); + spi_xfer(alen + len); + /* ignore received data */ + for (i = 0; i < 1000; i++) { + *txbuf = SPI_EEPROM_RDSR; /* read status */ + txbuf[1] = 0; + spi_xfer(2); + if (!(rxbuf[1] & 1)) { + break; + } + udelay(1000); + } + if (i >= 1000) { + printf ("*** spi_write: Time out while writing!\n"); + } + + return len; +} + +/**************************************************************************** + * Function: spi_read + **************************************************************************** */ +ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) +{ + memset(rxbuf, 0, MAX_BUFFER); + memset(txbuf, 0, MAX_BUFFER); + memcpy(txbuf, addr, alen); + *txbuf = SPI_EEPROM_READ; /* READ memory array */ + + /* + * There is a bug in 860T (?) that cuts the last byte of input + * if we're reading into DPRAM. The solution we choose here is + * to always read len+1 bytes (we have one extra byte at the + * end of the buffer). + */ + spi_xfer(alen + len + 1); + memcpy(buffer, alen + rxbuf, len); + + return len; +} + +/**************************************************************************** + * Function: spi_xfer + **************************************************************************** */ +ssize_t spi_xfer (size_t count) +{ + volatile immap_t *immr; + volatile cpm8260_t *cp; + volatile spi_t *spi; + cbd_t *tbdf, *rbdf; + int tm; + + DPRINT (("*** spi_xfer entered ***\n")); + + immr = (immap_t *) CFG_IMMR; + cp = (cpm8260_t *) &immr->im_cpm; + + spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; + + tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; + rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; + + /* Board-specific: Set CS for device (ATC EEPROM) */ + immr->im_ioport.iop_pdatd &= ~0x00080000; + + /* Setting tx bd status and data length */ + tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; + tbdf->cbd_datlen = count; + + DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", + tbdf->cbd_datlen)); + + /* Setting rx bd status and data length */ + rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; + rbdf->cbd_datlen = 0; /* rx length has no significance */ + + immr->im_spi.spi_spmode = SPMODE_REV | + SPMODE_MSTR | + SPMODE_EN | + SPMODE_LEN(8) | /* 8 Bits per char */ + SPMODE_PM(0x8) ; /* medium speed */ + immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ + immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ + + /* start spi transfer */ + DPRINT (("*** spi_xfer: Performing transfer ...\n")); + immr->im_spi.spi_spcom |= SPI_STR; /* Start transmit */ + + /* -------------------------------- + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * -------------------------------- */ + for (tm=0; tm<1000; ++tm) { + if (immr->im_spi.spi_spie & SPI_TXB) { /* Tx Buffer Empty */ + DPRINT (("*** spi_xfer: Tx buffer empty\n")); + break; + } + if ((tbdf->cbd_sc & BD_SC_READY) == 0) { + DPRINT (("*** spi_xfer: Tx BD done\n")); + break; + } + udelay (1000); + } + if (tm >= 1000) { + printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); + } + DPRINT (("*** spi_xfer: ... transfer ended\n")); + +#ifdef DEBUG + printf ("\nspi_xfer: txbuf after xfer\n"); + memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ + printf ("spi_xfer: rxbuf after xfer\n"); + memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ + printf ("\n"); +#endif + + /* Clear CS for device */ + immr->im_ioport.iop_pdatd |= 0x00080000; + + return count; +} +#endif /* CONFIG_SPI */ diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S new file mode 100644 index 0000000..2e93bbb --- /dev/null +++ b/cpu/mpc8260/start.S @@ -0,0 +1,1046 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000, 2001,2002 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards + */ +#include +#include +#include + +#define CONFIG_8260 1 /* needed for Linux kernel header files */ +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +/* Floating Point enable, Machine Check and Recoverable Interr. */ +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) +#if defined(CONFIG_HYMOD) + GOT_ENTRY(environment) +#endif + END_GOT + +/* + * Version string - must be in data segment because MPC8260 uses the first + * 256 bytes for the Hard Reset Configuration Word table (see below). + * Similarly, can't have the U-Boot Magic Number as the first thing in + * the image - don't know how this will affect the image tools, but I guess + * I'll find out soon + */ + .data + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + +/* + * Hard Reset Configuration Word (HRCW) table + * + * The Hard Reset Configuration Word (HRCW) sets a number of useful things + * such as whether there is an external memory controller, whether the + * PowerPC core is disabled (i.e. only the communications processor is + * active, accessed by another CPU on the bus), whether using external + * arbitration, external bus mode, boot port size, core initial prefix, + * internal space base, boot memory space, etc. + * + * These things dictate where the processor begins execution, where the + * boot ROM appears in memory, the memory controller setup when access + * boot ROM, etc. The HRCW is *extremely* important. + * + * The HRCW is read from the bus during reset. One CPU on the bus will + * be a hard reset configuration master, any others will be hard reset + * configuration slaves. The master reads eight HRCWs from flash during + * reset - the first it uses for itself, the other 7 it communicates to + * up to 7 configuration slaves by some complicated mechanism, which is + * not really important here. + * + * The configuration master performs 32 successive reads starting at address + * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8 + * bits is read, and always from byte lane D[0-7] (so that port size of the + * boot device does not matter). The first four reads form the 32 bit HRCW + * for the master itself. The second four reads form the HRCW for the first + * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by + * concatenating the four bytes, with the first read placed in byte 0 (the + * most significant byte), and so on with the fourth read placed in byte 3 + * (the least significant byte). + */ +#define _HRCW_TABLE_ENTRY(w) \ + .fill 8,1,(((w)>>24)&0xff); \ + .fill 8,1,(((w)>>16)&0xff); \ + .fill 8,1,(((w)>> 8)&0xff); \ + .fill 8,1,(((w) )&0xff) + .text + .globl _hrcw_table +_hrcw_table: + _HRCW_TABLE_ENTRY(CFG_HRCW_MASTER) + _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1) + _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2) + _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3) + _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4) + _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5) + _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6) + _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7) +/* + * After configuration, a system reset exception is executed using the + * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP] + * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address + * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value + * of MSR[IP] is determined by the CIP field in the HRCW. + * + * Other bits in the HRCW set up the Base Address and Port Size in BR0. + * This determines the location of the boot ROM (flash or EPROM) in the + * processor's address space at boot time. As long as the HRCW is set up + * so that we eventually end up executing the code below when the processor + * executes the reset exception, the actual values used should not matter. + * + * Once we have got here, the address mask in OR0 is cleared so that the + * bottom 32K of the boot ROM is effectively repeated all throughout the + * processor's address space, after which we can jump to the absolute + * address at which the boot ROM was linked at compile time, and proceed + * to initialise the memory controller without worrying if the rug will be + * pulled out from under us, so to speak (it will be fine as long as we + * configure BR0 with the same boot ROM link address). + */ + . = EXC_OFF_SYS_RESET + + .globl _start +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/ + nop + b boot_cold + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + +boot_cold: +#if defined(CONFIG_MPC8260ADS) && defined(CFG_DEFAULT_IMMR) + lis r3, CFG_DEFAULT_IMMR@h + nop + lwz r4, 0(r3) + nop + rlwinm r4, r4, 0, 8, 5 + nop + oris r4, r4, 0x0200 + nop + stw r4, 0(r3) + nop +#endif /* CONFIG_MPC8260ADS && CFG_DEFAULT_IMMR */ +boot_warm: + mfmsr r5 /* save msr contents */ + +#if defined(CONFIG_COGENT) + /* this is what the cogent EPROM does */ + li r0, 0 + mtmsr r0 + isync + bl cogent_init_8260 +#endif /* CONFIG_COGENT */ + +#if defined(CFG_DEFAULT_IMMR) + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + lis r4, CFG_DEFAULT_IMMR@h + stw r3, 0x1A8(r4) +#endif /* CFG_DEFAULT_IMMR */ + + /* Initialise the MPC8260 processor core */ + /*--------------------------------------------------------------*/ + + bl init_8260_core + +#ifndef CFG_RAMBOOT + /* When booting from ROM (Flash or EPROM), clear the */ + /* Address Mask in OR0 so ROM appears everywhere */ + /*--------------------------------------------------------------*/ + + lis r3, (CFG_IMMR+IM_REGBASE)@h + lwz r4, IM_OR0@l(r3) + li r5, 0x7fff + and r4, r4, r5 + stw r4, IM_OR0@l(r3) + + /* Calculate absolute address in FLASH and jump there */ + /*--------------------------------------------------------------*/ + + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r3 + blr + +in_flash: +#endif /* CFG_RAMBOOT */ + + /* initialize some things that are hard to access from C */ + /*--------------------------------------------------------------*/ + + lis r3, CFG_IMMR@h /* set up stack in internal DPRAM */ + ori r1, r3, CFG_INIT_SP_OFFSET + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*--------------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + bl cpu_init_f /* run low-level CPU init code (in Flash)*/ + +#ifdef DEBUG + bl init_debug /* set up debugging stuff */ +#endif + + mr r3, r21 + /* r3: BOOTFLAG */ + bl board_init_f /* run 1st part of board init code (in Flash)*/ + +/* + * Vector Table + */ + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) +#ifdef DEBUG + . = 0x1300 + /* + * This exception occurs when the program counter matches the + * Instruction Address Breakpoint Register (IABR). + * + * I want the cpu to halt if this occurs so I can hunt around + * with the debugger and look at things. + * + * When DEBUG is defined, both machine check enable (in the MSR) + * and checkstop reset enable (in the reset mode register) are + * turned off and so a checkstop condition will result in the cpu + * halting. + * + * I force the cpu into a checkstop condition by putting an illegal + * instruction here (at least this is the theory). + * + * well - that didnt work, so just do an infinite loop! + */ +1: b 1b +#else + STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) +#endif + STD_EXCEPTION(0x1400, SMI, UnknownException) + + STD_EXCEPTION(0x1500, Trap_15, UnknownException) + STD_EXCEPTION(0x1600, Trap_16, UnknownException) + STD_EXCEPTION(0x1700, Trap_17, UnknownException) + STD_EXCEPTION(0x1800, Trap_18, UnknownException) + STD_EXCEPTION(0x1900, Trap_19, UnknownException) + STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) + STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) + STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) + STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) + STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) + STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) + STD_EXCEPTION(0x2000, Trap_20, UnknownException) + STD_EXCEPTION(0x2100, Trap_21, UnknownException) + STD_EXCEPTION(0x2200, Trap_22, UnknownException) + STD_EXCEPTION(0x2300, Trap_23, UnknownException) + STD_EXCEPTION(0x2400, Trap_24, UnknownException) + STD_EXCEPTION(0x2500, Trap_25, UnknownException) + STD_EXCEPTION(0x2600, Trap_26, UnknownException) + STD_EXCEPTION(0x2700, Trap_27, UnknownException) + STD_EXCEPTION(0x2800, Trap_28, UnknownException) + STD_EXCEPTION(0x2900, Trap_29, UnknownException) + STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) + STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) + STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) + STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) + STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) + STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) + + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x3000 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +#if defined(CONFIG_COGENT) + +/* + * This code initialises the MPC8260 processor core + * (conforms to PowerPC 603e spec) + */ + + .globl cogent_init_8260 +cogent_init_8260: + + /* Taken from page 14 of CMA282 manual */ + /*--------------------------------------------------------------*/ + + lis r4, (CFG_IMMR+IM_REGBASE)@h + lis r3, CFG_IMMR@h + stw r3, IM_IMMR@l(r4) + lwz r3, IM_IMMR@l(r4) + stw r3, 0(r0) + lis r3, CFG_SYPCR@h + ori r3, r3, CFG_SYPCR@l + stw r3, IM_SYPCR@l(r4) + lwz r3, IM_SYPCR@l(r4) + stw r3, 4(r0) + lis r3, CFG_SCCR@h + ori r3, r3, CFG_SCCR@l + stw r3, IM_SCCR@l(r4) + lwz r3, IM_SCCR@l(r4) + stw r3, 8(r0) + + /* the rest of this was disassembled from the */ + /* EPROM code that came with my CMA282 CPU module */ + /*--------------------------------------------------------------*/ + + lis r1, 0x1234 + ori r1, r1, 0x5678 + stw r1, 0x20(r0) + lwz r1, 0x20(r0) + stw r1, 0x24(r0) + lwz r1, 0x24(r0) + lis r3, 0x0e80 + ori r3, r3, 0 + stw r1, 4(r3) + lwz r1, 4(r3) + + /* Done! */ + /*--------------------------------------------------------------*/ + + blr + +#endif /* CONFIG_COGENT */ + +/* + * This code initialises the MPC8260 processor core + * (conforms to PowerPC 603e spec) + * Note: expects original MSR contents to be in r5. + */ + + .globl init_8260_core +init_8260_core: + + /* Initialize machine status; enable machine check interrupt */ + /*--------------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ +#endif + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + /* Initialise the SYPCR early, and reset the watchdog (if req) */ + /*--------------------------------------------------------------*/ + + lis r3, (CFG_IMMR+IM_REGBASE)@h +#if !defined(CONFIG_COGENT) + lis r4, CFG_SYPCR@h + ori r4, r4, CFG_SYPCR@l + stw r4, IM_SYPCR@l(r3) +#endif /* !CONFIG_COGENT */ +#if defined(CONFIG_WATCHDOG) + li r4, 21868 /* = 0x556c */ + sth r4, IM_SWSR@l(r3) + li r4, -21959 /* = 0xaa39 */ + sth r4, IM_SWSR@l(r3) +#endif /* CONFIG_WATCHDOG */ + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*--------------------------------------------------------------*/ + + lis r3, CFG_HID0_INIT@h + ori r3, r3, CFG_HID0_INIT@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID0_FINAL@h + ori r3, r3, CFG_HID0_FINAL@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID2@h + ori r3, r3, CFG_HID2@l + mtspr HID2, r3 + + /* clear all BAT's */ + /*--------------------------------------------------------------*/ + + li r0, 0 + mtspr DBAT0U, r0 + mtspr DBAT0L, r0 + mtspr DBAT1U, r0 + mtspr DBAT1L, r0 + mtspr DBAT2U, r0 + mtspr DBAT2L, r0 + mtspr DBAT3U, r0 + mtspr DBAT3L, r0 + mtspr IBAT0U, r0 + mtspr IBAT0L, r0 + mtspr IBAT1U, r0 + mtspr IBAT1L, r0 + mtspr IBAT2U, r0 + mtspr IBAT2L, r0 + mtspr IBAT3U, r0 + mtspr IBAT3L, r0 + SYNC + + /* invalidate all tlb's */ + /* */ + /* From the 603e User Manual: "The 603e provides the ability to */ + /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ + /* instruction invalidates the TLB entry indexed by the EA, and */ + /* operates on both the instruction and data TLBs simultaneously*/ + /* invalidating four TLB entries (both sets in each TLB). The */ + /* index corresponds to bits 15-19 of the EA. To invalidate all */ + /* entries within both TLBs, 32 tlbie instructions should be */ + /* issued, incrementing this field by one each time." */ + /* */ + /* "Note that the tlbia instruction is not implemented on the */ + /* 603e." */ + /* */ + /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ + /* incrementing by 0x1000 each time. The code below is sort of */ + /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */ + /* */ + /*--------------------------------------------------------------*/ + + li r3, 32 + mtctr r3 + li r3, 0 +1: tlbie r3 + addi r3, r3, 0x1000 + bdnz 1b + SYNC + + /* Done! */ + /*--------------------------------------------------------------*/ + + blr + +#ifdef DEBUG + +/* + * initialise things related to debugging. + * + * must be called after the global offset table (GOT) is initialised + * (GET_GOT) and after cpu_init_f() has executed. + */ + + .globl init_debug +init_debug: + + lis r3, (CFG_IMMR+IM_REGBASE)@h + + /* Quick and dirty hack to enable the RAM and copy the */ + /* vectors so that we can take exceptions. */ + /*--------------------------------------------------------------*/ + /* write Memory Refresh Prescaler */ + li r4, CFG_MPTPR + sth r4, IM_MPTPR@l(r3) + /* write 60x Refresh Timer */ + li r4, CFG_PSRT + stb r4, IM_PSRT@l(r3) + /* init the 60x SDRAM Mode Register */ + lis r4, (CFG_PSDMR|PSDMR_OP_NORM)@h + ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM)@l + stw r4, IM_PSDMR@l(r3) + /* write Precharge All Banks command */ + lis r4, (CFG_PSDMR|PSDMR_OP_PREA)@h + ori r4, r4, (CFG_PSDMR|PSDMR_OP_PREA)@l + stw r4, IM_PSDMR@l(r3) + stb r0, 0(0) + /* write eight CBR Refresh commands */ + lis r4, (CFG_PSDMR|PSDMR_OP_CBRR)@h + ori r4, r4, (CFG_PSDMR|PSDMR_OP_CBRR)@l + stw r4, IM_PSDMR@l(r3) + stb r0, 0(0) + stb r0, 0(0) + stb r0, 0(0) + stb r0, 0(0) + stb r0, 0(0) + stb r0, 0(0) + stb r0, 0(0) + stb r0, 0(0) + /* write Mode Register Write command */ + lis r4, (CFG_PSDMR|PSDMR_OP_MRW)@h + ori r4, r4, (CFG_PSDMR|PSDMR_OP_MRW)@l + stw r4, IM_PSDMR@l(r3) + stb r0, 0(0) + /* write Normal Operation command and enable Refresh */ + lis r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h + ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l + stw r4, IM_PSDMR@l(r3) + stb r0, 0(0) + /* RAM should now be operational */ + +#define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4) + + lwz r3, GOT(_end_of_vectors) + rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */ + lis r5, VEC_WRD_CNT@h + ori r5, r5, VEC_WRD_CNT@l + mtctr r5 +1: + lwzu r5, -4(r3) + stwu r5, -4(r4) + bdnz 1b + + /* Load the Instruction Address Breakpoint Register (IABR). */ + /* */ + /* The address to load is stored in the first word of dual port */ + /* ram and should be preserved while the power is on, so you */ + /* can plug addresses into that location then reset the cpu and */ + /* this code will load that address into the IABR after the */ + /* reset. */ + /* */ + /* When the program counter matches the contents of the IABR, */ + /* an exception is generated (before the instruction at that */ + /* location completes). The vector for this exception is 0x1300 */ + /*--------------------------------------------------------------*/ + lis r3, CFG_IMMR@h + lwz r3, 0(r3) + mtspr IABR, r3 + + /* Set the entire dual port RAM (where the initial stack */ + /* resides) to a known value - makes it easier to see where */ + /* the stack has been written */ + /*--------------------------------------------------------------*/ + lis r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@h + ori r3, r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@l + li r4, ((CFG_INIT_SP_OFFSET - 4) / 4) + mtctr r4 + lis r4, 0xdeadbeaf@h + ori r4, r4, 0xdeadbeaf@l +1: + stwu r4, -4(r3) + bdnz 1b + + /* Done! */ + /*--------------------------------------------------------------*/ + + blr +#endif + +/* Cache functions. + * + * Note: requires that all cache bits in + * HID0 are in the low half word. + */ + .globl icache_enable +icache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_ICE + lis r4, 0 + ori r4, r4, HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_disable +icache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_ICE|HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_status +icache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 + blr + + .globl dcache_enable +dcache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_DCE + lis r4, 0 + ori r4, r4, HID0_DLOCK + andc r3, r3, r4 + ori r4, r3, HID0_DCI + sync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_disable +dcache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_DCE|HID0_DLOCK + andc r3, r3, r4 + ori r4, r3, HID0_DCI + sync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_status +dcache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ + rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 + cmpwi r7,0 + beq 9f + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ +9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ + rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 + cmpwi r7,0 + beq 7f + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) +#if defined(CONFIG_HYMOD) + /* + * For HYMOD - the environment is the very last item in flash. + * The real .bss stops just before environment starts, so only + * clear up to that point. + * + * taken from mods for FADS board + */ + lwz r4,GOT(environment) +#else + lwz r4,GOT(_end) +#endif + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mfmsr r3 /* now that the vectors have */ + lis r7, MSR_IP@h /* relocated into low memory */ + ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ + andc r3, r3, r7 /* (if it was on) */ + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c new file mode 100644 index 0000000..0c39e43 --- /dev/null +++ b/cpu/mpc8260/traps.c @@ -0,0 +1,276 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler)(struct pt_regs *) = 0; +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. +*/ +#define END_OF_MEM 0x02000000 + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + puts ("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + putc ('\n'); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + putc ('\n'); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + putc ('\n'); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + putc ('\n'); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +#ifdef CONFIG_PCI +void dump_pci (void) +{ + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + printf ("PCI: err status %x err mask %x err ctrl %x\n", + le32_to_cpu (immap->im_pci.pci_esr), + le32_to_cpu (immap->im_pci.pci_emr), + le32_to_cpu (immap->im_pci.pci_ecr)); + printf (" error address %x error data %x ctrl %x\n", + le32_to_cpu (immap->im_pci.pci_eacr), + le32_to_cpu (immap->im_pci.pci_edcr), + le32_to_cpu (immap->im_pci.pci_eccr)); + +} +#endif + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ +#ifdef CONFIG_PCI + volatile immap_t *immap = (immap_t *)CFG_IMMR; +#ifdef DEBUG + dump_pci(); +#endif + /* clear the error in the error status register */ + if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) { + immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP); + return; + } +#endif + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + puts ("Machine check in kernel mode.\n" + "Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + puts ("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + puts ("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + puts ("Data parity signal\n"); + break; + case (0x80000000>>15): + puts ("Address parity signal\n"); + break; + default: + puts ("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); +#ifdef CONFIG_PCI + dump_pci(); +#endif + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +SoftEmuException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + + +void +UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint(struct pt_regs *); +#endif + +void +DebugException(struct pt_regs *regs) +{ + + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); +#endif +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int +addr_probe(uint *addr) +{ +#if 0 + int retval; + + __asm__ __volatile__( \ + "1: lwz %0,0(%1)\n" \ + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); + + return (retval); +#endif + return 0; +} diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile new file mode 100644 index 0000000..60df4cd --- /dev/null +++ b/cpu/mpc83xx/Makefile @@ -0,0 +1,52 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o \ + resetvec.o + +COBJS = traps.o \ + cpu.o \ + cpu_init.o \ + speed.o \ + interrupts.o \ + i2c.o \ + spd_sdram.o + +OBJS = $(COBJS) + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk new file mode 100644 index 0000000..8b4ff92 --- /dev/null +++ b/cpu/mpc83xx/config.mk @@ -0,0 +1,26 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \ + -ffixed-r2 -ffixed-r29 -msoft-float diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c new file mode 100644 index 0000000..8c9b515 --- /dev/null +++ b/cpu/mpc83xx/cpu.c @@ -0,0 +1,153 @@ +/* + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +/* + * CPU specific code for the MPC83xx family. + * + * Derived from the MPC8260 and MPC85xx. + */ + +#include +#include +#include +#include +#include + + +int checkcpu(void) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong clock = gd->cpu_clk; + u32 pvr = get_pvr(); + char buf[32]; + + if ((pvr & 0xFFFF0000) != PVR_83xx) { + puts("Not MPC83xx Family!!!\n"); + return -1; + } + + puts("CPU: MPC83xx, "); + switch(pvr) { + case PVR_8349_REV10: + break; + case PVR_8349_REV11: + break; + default: + puts("Rev: Unknown\n"); + return -1; /* Not sure what this is */ + } + printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4, + (pvr & 0x0f), strmhz(buf, clock)); + + return 0; +} + + +void upmconfig (uint upm, uint *table, uint size) +{ + hang(); /* FIXME: upconfig() needed? */ +} + + +int +do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong msr; +#ifndef MPC83xx_RESET + ulong addr; +#endif + + volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; + +#ifdef MPC83xx_RESET + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~( MSR_EE | MSR_IR | MSR_DR); + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* enable Reset Control Reg */ + immap->reset.rpr = 0x52535445; + + /* confirm Reset Control Reg is enabled */ + while(!((immap->reset.rcer) & RCER_CRE)); + + printf("Resetting the board."); + printf("\n"); + + udelay(200); + + /* perform reset, only one bit */ + immap->reset.rcr = RCR_SWHR; + +#else /* ! MPC83xx_RESET */ + + immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ + + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* + * Trying to execute the next instruction at a non-existing address + * should cause a machine check, resulting in reset + */ + addr = CFG_RESET_ADDRESS; + + printf("resetting the board."); + printf("\n"); + ((void (*)(void)) addr) (); +#endif /* MPC83xx_RESET */ + + return 1; +} + + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + */ + +unsigned long get_tbclk(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong tbclk; + + tbclk = (gd->bus_clk + 3L) / 4L; + + return tbclk; +} + + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + hang(); /* FIXME: implement watchdog_reset()? */ +} +#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c new file mode 100644 index 0000000..dcb3445 --- /dev/null +++ b/cpu/mpc83xx/cpu_init.c @@ -0,0 +1,163 @@ +/* + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +#include +#include +#include + +/* + * Breathe some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f (volatile immap_t * im) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* RSR - Reset Status Register - clear all status (4.6.1.3) */ + gd->reset_status = im->reset.rsr; + im->reset.rsr = ~(RSR_RES); + + /* + * RMR - Reset Mode Register + * contains checkstop reset enable (4.6.1.4) + */ + im->reset.rmr = (RMR_CSRE & (1<lbus.lcrr = CFG_LCRR; + + /* Enable Time Base & Decrimenter ( so we will have udelay() )*/ + im->sysconf.spcr |= SPCR_TBEN; + + /* System General Purpose Register */ + im->sysconf.sicrh = SICRH_TSOBI1; + im->sysconf.sicrl = SICRL_LDP_A; + + /* + * Memory Controller: + */ + + /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary + * addresses - these have to be modified later when FLASH size + * has been determined + */ + +#if defined(CFG_BR0_PRELIM) \ + && defined(CFG_OR0_PRELIM) \ + && defined(CFG_LBLAWBAR0_PRELIM) \ + && defined(CFG_LBLAWAR0_PRELIM) + im->lbus.bank[0].br = CFG_BR0_PRELIM; + im->lbus.bank[0].or = CFG_OR0_PRELIM; + im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM; + im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM; +#else +#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined +#endif + +#if defined(CFG_BR1_PRELIM) \ + && defined(CFG_OR1_PRELIM) \ + && defined(CFG_LBLAWBAR1_PRELIM) \ + && defined(CFG_LBLAWAR1_PRELIM) + im->lbus.bank[1].br = CFG_BR1_PRELIM; + im->lbus.bank[1].or = CFG_OR1_PRELIM; + im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM; + im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM; +#endif +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) + im->lbus.bank[2].br = CFG_BR2_PRELIM; + im->lbus.bank[2].or = CFG_OR2_PRELIM; + im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM; + im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM; +#endif +#if defined(CFG_BR3_PRELIM) \ + && defined(CFG_OR3_PRELIM) \ + && defined(CFG_LBLAWBAR3_PRELIM) \ + && defined(CFG_LBLAWAR3_PRELIM) + im->lbus.bank[3].br = CFG_BR3_PRELIM; + im->lbus.bank[3].or = CFG_OR3_PRELIM; + im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM; + im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM; +#endif +#if defined(CFG_BR4_PRELIM) \ + && defined(CFG_OR4_PRELIM) \ + && defined(CFG_LBLAWBAR4_PRELIM) \ + && defined(CFG_LBLAWAR4_PRELIM) + im->lbus.bank[4].br = CFG_BR4_PRELIM; + im->lbus.bank[4].or = CFG_OR4_PRELIM; + im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM; + im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM; +#endif +#if defined(CFG_BR5_PRELIM) \ + && defined(CFG_OR5_PRELIM) \ + && defined(CFG_LBLAWBAR5_PRELIM) \ + && defined(CFG_LBLAWAR5_PRELIM) + im->lbus.bank[5].br = CFG_BR5_PRELIM; + im->lbus.bank[5].or = CFG_OR5_PRELIM; + im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM; + im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM; +#endif +#if defined(CFG_BR6_PRELIM) \ + && defined(CFG_OR6_PRELIM) \ + && defined(CFG_LBLAWBAR6_PRELIM) \ + && defined(CFG_LBLAWAR6_PRELIM) + im->lbus.bank[6].br = CFG_BR6_PRELIM; + im->lbus.bank[6].or = CFG_OR6_PRELIM; + im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM; + im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM; +#endif +#if defined(CFG_BR7_PRELIM) \ + && defined(CFG_OR7_PRELIM) \ + && defined(CFG_LBLAWBAR7_PRELIM) \ + && defined(CFG_LBLAWAR7_PRELIM) + im->lbus.bank[7].br = CFG_BR7_PRELIM; + im->lbus.bank[7].or = CFG_OR7_PRELIM; + im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM; + im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; +#endif +} + + +/* + * Initialize higher level parts of CPU like time base and timers. + */ + +int cpu_init_r (void) +{ + return 0; +} diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c new file mode 100644 index 0000000..4e70f80 --- /dev/null +++ b/cpu/mpc83xx/i2c.c @@ -0,0 +1,253 @@ +/* + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao + * Adapted for Motorola 85xx chip. + * + * (C) Copyright 2003 + * Gleb Natapov + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk + * + * Hardware I2C driver for MPC107 PCI bridge. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +#include +#include +#include + +#ifdef CONFIG_HARD_I2C +#include +#include + +#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X) +i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); +#endif + +void +i2c_init(int speed, int slaveadd) +{ + /* stop I2C controller */ + writeb(0x00 , &I2C->cr); + + /* set clock */ + writeb(0x3f, &I2C->fdr); + + /* set default filter */ + writeb(0x10,&I2C->dfsrr); + + /* write slave address */ + writeb(slaveadd, &I2C->adr); + + /* clear status register */ + writeb(0x00, &I2C->sr); + + /* start I2C controller */ + writeb(I2C_CR_MEN, &I2C->cr); +} + +static __inline__ int +i2c_wait4bus (void) +{ + ulong timeval = get_timer (0); + while (readb(&I2C->sr) & I2C_SR_MBB) { + if (get_timer (timeval) > I2C_TIMEOUT) { + return -1; + } + } + return 0; +} + +static __inline__ int +i2c_wait (int write) +{ + u32 csr; + ulong timeval = get_timer(0); + do { + csr = readb(&I2C->sr); + + if (!(csr & I2C_SR_MIF)) + continue; + + writeb(0x0, &I2C->sr); + + if (csr & I2C_SR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & I2C_SR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } + + return 0; + } while (get_timer (timeval) < I2C_TIMEOUT); + + debug("i2c_wait: timed out\n"); + return -1; +} + +static __inline__ int +i2c_write_addr (u8 dev, u8 dir, int rsta) +{ + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | + (rsta?I2C_CR_RSTA:0), + &I2C->cr); + + writeb((dev << 1) | dir, &I2C->dr); + + if (i2c_wait (I2C_WRITE) < 0) + return 0; + return 1; +} + +static __inline__ int +__i2c_write (u8 *data, int length) +{ + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, + &I2C->cr); + + for (i=0; i < length; i++) { + writeb(data[i], &I2C->dr); + + if (i2c_wait (I2C_WRITE) < 0) + break; + } + return i; +} + +static __inline__ int +__i2c_read (u8 *data, int length) +{ + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | + ((length == 1) ? I2C_CR_TXAK : 0), + &I2C->cr); + + /* dummy read */ + readb(&I2C->dr); + + for (i=0; i < length; i++) { + if (i2c_wait (I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(I2C_CR_MEN | I2C_CR_MSTA | + I2C_CR_TXAK, + &I2C->cr); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); + + data[i] = readb(&I2C->dr); + } + return i; +} + +int +i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + if (i2c_write_addr (dev, I2C_READ, 1) == 0) + goto exit; + + i = __i2c_read (data, length); + + exit: + writeb(I2C_CR_MEN, &I2C->cr); + return !(i == length); +} + +int +i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + i = __i2c_write (data, length); + + exit: + writeb(I2C_CR_MEN, &I2C->cr); + return !(i == length); +} + +int i2c_probe (uchar chip) +{ + int tmp; + + /* + * Try to read the first location of the chip. The underlying + * driver doesn't appear to support sending just the chip address + * and looking for an back. + */ + udelay(10000); + return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); +} + +uchar i2c_reg_read (uchar i2c_addr, uchar reg) +{ + uchar buf[1]; + + i2c_read (i2c_addr, reg, 1, buf, 1); + + return (buf[0]); +} + +void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write (i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c new file mode 100644 index 0000000..53474f6 --- /dev/null +++ b/cpu/mpc83xx/interrupts.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * + * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +#include +#include +#include +#include + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + ulong count; +}; + +int interrupt_init_cpu (unsigned *decrementer_count) +{ + return 0; +} + + +/* + * Handle external interrupts + */ + +void external_interrupt (struct pt_regs *regs) +{ +} + + +/* + * Install and free an interrupt handler. + */ + +void +irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) +{ +} + + +void irq_free_handler (int irq) +{ +} + + +void timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} + + +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) + +/* ripped this out of ppc4xx/interrupts.c */ + +/* + * irqinfo - print information about PCI devices + */ + +void +do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc83xx/resetvec.S b/cpu/mpc83xx/resetvec.S new file mode 100644 index 0000000..3dfcd0d --- /dev/null +++ b/cpu/mpc83xx/resetvec.S @@ -0,0 +1,6 @@ + .section .resetvec,"ax" +#ifndef FIXME +#if 0 + b _start_e500 +#endif +#endif diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c new file mode 100644 index 0000000..63dcd66 --- /dev/null +++ b/cpu/mpc83xx/spd_sdram.c @@ -0,0 +1,408 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPD_EEPROM + +#if defined(CONFIG_DDR_ECC) +extern void dma_init(void); +extern uint dma_check(void); +extern int dma_xfer(void *dest, uint count, void *src); +#endif + +#ifndef CFG_READ_SPD +#define CFG_READ_SPD i2c_read +#endif + +/* + * Convert picoseconds into clock cycles (rounding up if needed). + */ + +int +picos_to_clk(int picos) +{ + int clks; + + clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); + if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + clks++; + } + + return clks; +} + +unsigned int +banksize(unsigned char row_dens) +{ + return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; +} + +long int spd_sdram(int(read_spd)(uint addr)) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile ddr8349_t *ddr = &immap->ddr; + volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0]; + spd_eeprom_t spd; + unsigned tmp, tmp1; + unsigned int memsize; + unsigned int law_size; + unsigned char caslat; + unsigned int trfc, trfc_clk, trfc_low; + +#warning Current spd_sdram does not fit its usage... adjust implementation or API... + + CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); + + if (spd.nrows > 2) { + puts("DDR:Only two chip selects are supported on ADS.\n"); + return 0; + } + + if (spd.nrow_addr < 12 + || spd.nrow_addr > 14 + || spd.ncol_addr < 8 + || spd.ncol_addr > 11) { + puts("DDR:Row or Col number unsupported.\n"); + return 0; + } + + ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; + ddr->cs_config[2] = ( 1 << 31 + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("\n"); + debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); + debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); + + if (spd.nrows == 2) { + ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) + | ((banksize(spd.row_dens) >> 23) - 1) ); + ddr->cs_config[3] = ( 1<<31 + | (spd.nrow_addr-12) << 8 + | (spd.ncol_addr-8) ); + debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); + debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); + } + + if (spd.mem_type != 0x07) { + puts("No DDR module found!\n"); + return 0; + } + + /* + * Figure out memory size in Megabytes. + */ + memsize = spd.nrows * banksize(spd.row_dens) / 0x100000; + + /* + * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. + */ + law_size = 19 + __ilog2(memsize); + + /* + * Set up LAWBAR for all of DDR. + */ + ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); + debug("DDR:bar=0x%08x\n", ecm->bar); + debug("DDR:ar=0x%08x\n", ecm->ar); + + /* + * find the largest CAS + */ + if(spd.cas_lat & 0x40) { + caslat = 7; + } else if (spd.cas_lat & 0x20) { + caslat = 6; + } else if (spd.cas_lat & 0x10) { + caslat = 5; + } else if (spd.cas_lat & 0x08) { + caslat = 4; + } else if (spd.cas_lat & 0x04) { + caslat = 3; + } else if (spd.cas_lat & 0x02) { + caslat = 2; + } else if (spd.cas_lat & 0x01) { + caslat = 1; + } else { + puts("DDR:no valid CAS Latency information.\n"); + return 0; + } + + tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10 + + (spd.clk_cycle & 0x0f)); + debug("DDR:Module maximum data rate is: %dMhz\n", tmp); + + tmp1 = get_bus_freq(0) / 1000000; + if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) { + /* 90~230 range, treated as DDR 200 */ + if (spd.clk_cycle3 == 0xa0) + caslat -= 2; + else if(spd.clk_cycle2 == 0xa0) + caslat--; + } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) { + /* 230-280 range, treated as DDR 266 */ + if (spd.clk_cycle3 == 0x75) + caslat -= 2; + else if (spd.clk_cycle2 == 0x75) + caslat--; + } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) { + /* 280~350 range, treated as DDR 333 */ + if (spd.clk_cycle3 == 0x60) + caslat -= 2; + else if (spd.clk_cycle2 == 0x60) + caslat--; + } else if (tmp1 < 90 || tmp1 >= 350) { + /* DDR rate out-of-range */ + puts("DDR:platform frequency is not fit for DDR rate\n"); + return 0; + } + + /* + * note: caslat must also be programmed into ddr->sdram_mode + * register. + * + * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD, + * use conservative value here. + */ + trfc = spd.trfc * 1000; /* up to ps */ + trfc_clk = picos_to_clk(trfc); + trfc_low = (trfc_clk - 8) & 0xf; + + ddr->timing_cfg_1 = + (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | + ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | + ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | + ((caslat & 0x07) << 16 ) | + (trfc_low << 12 ) | + ( 0x300 ) | + ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1); + + ddr->timing_cfg_2 = 0x00000800; + + debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); + debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); + + /* + * Only DDR I is supported + * DDR I and II have different mode-register-set definition + */ + + /* burst length is always 4 */ + switch(caslat) { + case 2: + ddr->sdram_mode = 0x52; /* 1.5 */ + break; + case 3: + ddr->sdram_mode = 0x22; /* 2.0 */ + break; + case 4: + ddr->sdram_mode = 0x62; /* 2.5 */ + break; + case 5: + ddr->sdram_mode = 0x32; /* 3.0 */ + break; + default: + puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n"); + return 0; + } + debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); + + switch(spd.refresh) { + case 0x00: + case 0x80: + tmp = picos_to_clk(15625000); + break; + case 0x01: + case 0x81: + tmp = picos_to_clk(3900000); + break; + case 0x02: + case 0x82: + tmp = picos_to_clk(7800000); + break; + case 0x03: + case 0x83: + tmp = picos_to_clk(31300000); + break; + case 0x04: + case 0x84: + tmp = picos_to_clk(62500000); + break; + case 0x05: + case 0x85: + tmp = picos_to_clk(125000000); + break; + default: + tmp = 0x512; + break; + } + + /* + * Set BSTOPRE to 0x100 for page mode + * If auto-charge is used, set BSTOPRE = 0 + */ + ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100; + debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); + + /* + * Is this an ECC DDR chip? + */ +#if defined(CONFIG_DDR_ECC) + if (spd.config == 0x02) { + ddr->err_disable = 0x0000000d; + ddr->err_sbe = 0x00ff0000; + } + debug("DDR:err_disable=0x%08x\n", ddr->err_disable); + debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); +#endif + asm("sync;isync"); + + udelay(500); + + /* + * SS_EN=1, + * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM + * clock cycle after address/command + */ + ddr->sdram_clk_cntl = 0x82000000; + + /* + * Figure out the settings for the sdram_cfg register. Build up + * the entire register in 'tmp' before writing since the write into + * the register will actually enable the memory controller, and all + * settings must be done before enabling. + * + * sdram_cfg[0] = 1 (ddr sdram logic enable) + * sdram_cfg[1] = 1 (self-refresh-enable) + * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM) + */ + tmp = 0xc2000000; + + /* + * sdram_cfg[3] = RD_EN - registered DIMM enable + * A value of 0x26 indicates micron registered DIMMS (micron.com) + */ + if (spd.mod_attr == 0x26) { + tmp |= 0x10000000; + } + +#if defined(CONFIG_DDR_ECC) + /* + * If the user wanted ECC (enabled via sdram_cfg[2]) + */ + if (spd.config == 0x02) { + tmp |= 0x20000000; + } +#endif + +#if defined(CONFIG_DDR_2T_TIMING) + /* + * Enable 2T timing by setting sdram_cfg[16]. + */ + tmp |= SDRAM_CFG_2T_EN; +#endif + + ddr->sdram_cfg = tmp; + asm("sync;isync"); + udelay(500); + + debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); + + return memsize;/*in MBytes*/ +} +#endif /* CONFIG_SPD_EEPROM */ + + +#if defined(CONFIG_DDR_ECC) +/* + * Initialize all of memory for ECC, then enable errors. + */ + +void +ddr_enable_ecc(unsigned int dram_size) +{ +#ifndef FIXME + uint *p = 0; + uint i = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + dma_init(); + + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((unsigned int)p & 0x1f) == 0) { + ppcDcbz((unsigned long) p); + } + *p = (unsigned int)0xdeadbeef; + if (((unsigned int)p & 0x1c) == 0x1c) { + ppcDcbf((unsigned long) p); + } + } + + /* 8K */ + dma_xfer((uint *)0x2000, 0x2000, (uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000, 0x4000, (uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000, 0x8000, (uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000, 0x10000, (uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000, 0x20000, (uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000, 0x40000, (uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000, 0x80000, (uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000, 0x100000, (uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000, 0x200000, (uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000, 0x400000, (uint *)0); + + for (i = 1; i < dram_size / 0x800000; i++) { + dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); + } + + /* + * Enable errors for ECC. + */ + ddr->err_disable = 0x00000000; + asm("sync;isync"); +#endif +} + +#endif /* CONFIG_DDR_ECC */ diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c new file mode 100644 index 0000000..1368fc3 --- /dev/null +++ b/cpu/mpc83xx/speed.c @@ -0,0 +1,366 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +#include +#include +#include + +/* ----------------------------------------------------------------- */ + +typedef enum { + _unk, + _off, + _byp, + _x8, + _x4, + _x2, + _x1, + _1x, + _1_5x, + _2x, + _2_5x, + _3x +} mult_t; + +typedef struct { + mult_t core_csb_ratio; + mult_t vco_divider; +} corecnf_t; + +corecnf_t corecnf_tab[] = { + { _byp, _byp}, /* 0x00 */ + { _byp, _byp}, /* 0x01 */ + { _byp, _byp}, /* 0x02 */ + { _byp, _byp}, /* 0x03 */ + { _byp, _byp}, /* 0x04 */ + { _byp, _byp}, /* 0x05 */ + { _byp, _byp}, /* 0x06 */ + { _byp, _byp}, /* 0x07 */ + { _1x, _x2}, /* 0x08 */ + { _1x, _x4}, /* 0x09 */ + { _1x, _x8}, /* 0x0A */ + { _1x, _x8}, /* 0x0B */ + {_1_5x, _x2}, /* 0x0C */ + {_1_5x, _x4}, /* 0x0D */ + {_1_5x, _x8}, /* 0x0E */ + {_1_5x, _x8}, /* 0x0F */ + { _2x, _x2}, /* 0x10 */ + { _2x, _x4}, /* 0x11 */ + { _2x, _x8}, /* 0x12 */ + { _2x, _x8}, /* 0x13 */ + {_2_5x, _x2}, /* 0x14 */ + {_2_5x, _x4}, /* 0x15 */ + {_2_5x, _x8}, /* 0x16 */ + {_2_5x, _x8}, /* 0x17 */ + { _3x, _x2}, /* 0x18 */ + { _3x, _x4}, /* 0x19 */ + { _3x, _x8}, /* 0x1A */ + { _3x, _x8}, /* 0x1B */ +}; + +/* ----------------------------------------------------------------- */ + +/* + * + */ +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 pci_sync_in; + u8 spmf; + u8 clkin_div; + u32 sccr; + u32 corecnf_tab_index; + u8 corepll; + u32 lcrr; + + u32 csb_clk; + u32 tsec1_clk; + u32 tsec2_clk; + u32 core_clk; + u32 usbmph_clk; + u32 usbdr_clk; + u32 i2c_clk; + u32 enc_clk; + u32 lbiu_clk; + u32 lclk_clk; + u32 ddr_clk; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + +#ifndef CFG_HRCW_HIGH +# error "CFG_HRCW_HIGH must be defined in board config file" +#endif /* CFG_HCWD_HIGH */ + +#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST) + +# ifndef CONFIG_83XX_CLKIN +# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file" +# endif /* CONFIG_83XX_CLKIN */ +# ifdef CONFIG_83XX_PCICLK +# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred" +# endif /* CONFIG_83XX_PCICLK */ + + /* PCI Host Mode */ + if (!(im->reset.rcwh & RCWH_PCIHOST)) { + /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH + * the im->reset.rcwhr PCI Host Mode is disabled + * FIXME: findout if there is a way to issue some warning */ + return -2; + } + if (im->clk.spmr & SPMR_CKID) { + /* PCI Clock is half CONFIG_83XX_CLKIN */ + pci_sync_in = CONFIG_83XX_CLKIN / 2; + } + else { + pci_sync_in = CONFIG_83XX_CLKIN; + } + +#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */ + +# ifdef CONFIG_83XX_CLKIN +# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred" +# endif /* CONFIG_83XX_CLKIN */ +# ifndef CONFIG_83XX_PCICLK +# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file" +# endif /* CONFIG_83XX_PCICLK */ + + /* PCI Agent Mode */ + if (im->reset.rcwh & RCWH_PCIHOST) { + /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH + * the im->reset.rcwhr PCI Host Mode is enabled */ + return -3; + } + pci_sync_in = CONFIG_83XX_PCICLK; + +#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */ + + /* we have up to date pci_sync_in */ + spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); + clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); + + if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) { + csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2; + } + else { + csb_clk = pci_sync_in * spmf * (1 + clkin_div); + } + + sccr = im->clk.sccr; + switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { + case 0: + tsec1_clk = 0; + break; + case 1: + tsec1_clk = csb_clk; + break; + case 2: + tsec1_clk = csb_clk / 2; + break; + case 3: + tsec1_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_TSEC1CM value */ + return -4; + } + + switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { + case 0: + tsec2_clk = 0; + break; + case 1: + tsec2_clk = csb_clk; + break; + case 2: + tsec2_clk = csb_clk / 2; + break; + case 3: + tsec2_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_TSEC2CM value */ + return -5; + } + i2c_clk = tsec2_clk; + + switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { + case 0: + enc_clk = 0; + break; + case 1: + enc_clk = csb_clk; + break; + case 2: + enc_clk = csb_clk / 2; + break; + case 3: + enc_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_ENCCM value */ + return -6; + } + + switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { + case 0: + usbmph_clk = 0; + break; + case 1: + usbmph_clk = csb_clk; + break; + case 2: + usbmph_clk = csb_clk / 2; + break; + case 3: + usbmph_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_USBMPHCM value */ + return -7; + } + + switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { + case 0: + usbdr_clk = 0; + break; + case 1: + usbdr_clk = csb_clk; + break; + case 2: + usbdr_clk = csb_clk / 2; + break; + case 3: + usbdr_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_USBDRCM value */ + return -8; + } + + if (usbmph_clk != 0 + && usbdr_clk != 0 + && usbmph_clk != usbdr_clk ) { + /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */ + return -9; + } + + lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); + lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; + switch (lcrr) { + case 2: + case 4: + case 8: + lclk_clk = lbiu_clk / lcrr; + break; + default: + /* unknown lcrr */ + return -10; + } + + ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); + + corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; + corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); + if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) { + /* corecnf_tab_index is too high, possibly worng value */ + return -11; + } + switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { + case _byp: + case _x1: + case _1x: + core_clk = csb_clk; + break; + case _1_5x: + core_clk = (3 * csb_clk) / 2; + break; + case _2x: + core_clk = 2 * csb_clk; + break; + case _2_5x: + core_clk = ( 5 * csb_clk) / 2; + break; + case _3x: + core_clk = 3 * csb_clk; + break; + default: + /* unkown core to csb ratio */ + return -12; + } + + gd->csb_clk = csb_clk ; + gd->tsec1_clk = tsec1_clk ; + gd->tsec2_clk = tsec2_clk ; + gd->core_clk = core_clk ; + gd->usbmph_clk = usbmph_clk; + gd->usbdr_clk = usbdr_clk ; + gd->i2c_clk = i2c_clk ; + gd->enc_clk = enc_clk ; + gd->lbiu_clk = lbiu_clk ; + gd->lclk_clk = lclk_clk ; + gd->ddr_clk = ddr_clk ; + gd->pci_clk = pci_sync_in; + + gd->cpu_clk = gd->core_clk; + gd->bus_clk = gd->lbiu_clk; + return 0; +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + DECLARE_GLOBAL_DATA_PTR; + return gd->csb_clk; +} + +int print_clock_conf (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + printf("Clock configuration:\n"); + printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000); + printf(" Core: %4d MHz\n",gd->core_clk/1000000); + debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000); + printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000); + debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000); + debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000); + debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000); + debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000); + debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000); + debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000); + + return 0; +} diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S new file mode 100644 index 0000000..fb001a6 --- /dev/null +++ b/cpu/mpc83xx/start.S @@ -0,0 +1,1093 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000, 2001,2002 Wolfgang Denk + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards + */ + +#include +#include +#include + +#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC83XX" +#endif + +/* We don't want the MMU yet. + */ +#undef MSR_KERNEL + +/* + * Floating Point enable, Machine Check and Recoverable Interr. + */ +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * Version string - must be in data segment because MPC83xx uses the + * first 256 bytes for the Hard Reset Configuration Word table (see + * below). Similarly, can't have the U-Boot Magic Number as the first + * thing in the image - don't know how this will affect the image tools, + * but I guess I'll find out soon. + */ + .data + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii " ", CONFIG_IDENT_STRING, "\0" + + .text +#define _HRCW_TABLE_ENTRY(w) \ + .fill 8,1,(((w)>>24)&0xff); \ + .fill 8,1,(((w)>>16)&0xff); \ + .fill 8,1,(((w)>> 8)&0xff); \ + .fill 8,1,(((w) )&0xff) + + _HRCW_TABLE_ENTRY(CFG_HRCW_LOW) + _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH) + + +#ifndef CONFIG_DEFAULT_IMMR +#error CONFIG_DEFAULT_IMMR must be defined +#endif /* CFG_DEFAULT_IMMR */ +#ifndef CFG_IMMRBAR +#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR +#endif /* CFG_IMMRBAR */ + +/* + * After configuration, a system reset exception is executed using the + * vector at offset 0x100 relative to the base set by MSR[IP]. If + * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the + * base address is 0xfff00000. In the case of a Power On Reset or Hard + * Reset, the value of MSR[IP] is determined by the CIP field in the + * HRCW. + * + * Other bits in the HRCW set up the Base Address and Port Size in BR0. + * This determines the location of the boot ROM (flash or EPROM) in the + * processor's address space at boot time. As long as the HRCW is set up + * so that we eventually end up executing the code below when the + * processor executes the reset exception, the actual values used should + * not matter. + * + * Once we have got here, the address mask in OR0 is cleared so that the + * bottom 32K of the boot ROM is effectively repeated all throughout the + * processor's address space, after which we can jump to the absolute + * address at which the boot ROM was linked at compile time, and proceed + * to initialise the memory controller without worrying if the rug will + * be pulled out from under us, so to speak (it will be fine as long as + * we configure BR0 with the same boot ROM link address). + */ + . = EXC_OFF_SYS_RESET + + .globl _start +_start: /* time t 0 */ + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/ + nop + b boot_cold + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + + +boot_cold: /* time t 3 */ + lis r4, CONFIG_DEFAULT_IMMR@h + nop +boot_warm: /* time t 5 */ + mfmsr r5 /* save msr contents */ + lis r3, CFG_IMMRBAR@h + ori r3, r3, CFG_IMMRBAR@l + stw r3, IMMRBAR(r4) + + /* Initialise the E300 processor core */ + /*------------------------------------------*/ + + bl init_e300_core + +#ifndef CFG_RAMBOOT + + /* Inflate flash location so it appears everywhere, calculate */ + /* the absolute address in final location of the FLASH, jump */ + /* there and deflate the flash size back to minimal size */ + /*------------------------------------------------------------*/ + bl map_flash_by_law1 + lis r4, (CFG_MONITOR_BASE)@h + ori r4, r4, (CFG_MONITOR_BASE)@l + addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r5 + blr +in_flash: +#if 1 /* Remapping flash with LAW0. */ + bl remap_flash_by_law0 +#endif +#endif /* CFG_RAMBOOT */ + + bl setup_stack_in_data_cache_on_r1 + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable & stack humble */ + /*------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + lis r3, CFG_IMMRBAR@h + /* run low-level CPU init code (in Flash)*/ + bl cpu_init_f + + /* r3: BOOTFLAG */ + mr r3, r21 + /* run 1st part of board init code (in Flash)*/ + bl board_init_f + +/* + * Vector Table + */ + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ +#ifndef FIXME + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) +#endif + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) +#ifdef DEBUG + . = 0x1300 + /* + * This exception occurs when the program counter matches the + * Instruction Address Breakpoint Register (IABR). + * + * I want the cpu to halt if this occurs so I can hunt around + * with the debugger and look at things. + * + * When DEBUG is defined, both machine check enable (in the MSR) + * and checkstop reset enable (in the reset mode register) are + * turned off and so a checkstop condition will result in the cpu + * halting. + * + * I force the cpu into a checkstop condition by putting an illegal + * instruction here (at least this is the theory). + * + * well - that didnt work, so just do an infinite loop! + */ +1: b 1b +#else + STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) +#endif + STD_EXCEPTION(0x1400, SMI, UnknownException) + + STD_EXCEPTION(0x1500, Trap_15, UnknownException) + STD_EXCEPTION(0x1600, Trap_16, UnknownException) + STD_EXCEPTION(0x1700, Trap_17, UnknownException) + STD_EXCEPTION(0x1800, Trap_18, UnknownException) + STD_EXCEPTION(0x1900, Trap_19, UnknownException) + STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) + STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) + STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) + STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) + STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) + STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) + STD_EXCEPTION(0x2000, Trap_20, UnknownException) + STD_EXCEPTION(0x2100, Trap_21, UnknownException) + STD_EXCEPTION(0x2200, Trap_22, UnknownException) + STD_EXCEPTION(0x2300, Trap_23, UnknownException) + STD_EXCEPTION(0x2400, Trap_24, UnknownException) + STD_EXCEPTION(0x2500, Trap_25, UnknownException) + STD_EXCEPTION(0x2600, Trap_26, UnknownException) + STD_EXCEPTION(0x2700, Trap_27, UnknownException) + STD_EXCEPTION(0x2800, Trap_28, UnknownException) + STD_EXCEPTION(0x2900, Trap_29, UnknownException) + STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) + STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) + STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) + STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) + STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) + STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) + + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x3000 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* + * This code initialises the E300 processor core + * (conforms to PowerPC 603e spec) + * Note: expects original MSR contents to be in r5. + */ + .globl init_e300_core +init_e300_core: /* time t 10 */ + /* Initialize machine status; enable machine check interrupt */ + /*-----------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ +#endif + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + + lis r3, CFG_IMMRBAR@h +#if defined(CONFIG_WATCHDOG) + /* Initialise the Wathcdog values and reset it (if req) */ + /*------------------------------------------------------*/ + lis r4, CFG_WATCHDOG_VALUE + ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + stw r4, SWCRR(r3) + + /* and reset it */ + + li r4, 0x556C + sth r4, SWSRR@l(r3) + li r4, 0xAA39 + sth r4, SWSRR@l(r3) +#else + /* Disable Wathcdog */ + /*-------------------*/ + xor r4, r4, r4 + stw r4, SWCRR(r3) +#endif /* CONFIG_WATCHDOG */ + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*------------------------------------------------------*/ + + lis r3, CFG_HID0_INIT@h + ori r3, r3, CFG_HID0_INIT@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID0_FINAL@h + ori r3, r3, CFG_HID0_FINAL@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID2@h + ori r3, r3, CFG_HID2@l + SYNC + mtspr HID2, r3 + + /* clear all BAT's */ + /*----------------------------------*/ + + xor r0, r0, r0 + mtspr DBAT0U, r0 + mtspr DBAT0L, r0 + mtspr DBAT1U, r0 + mtspr DBAT1L, r0 + mtspr DBAT2U, r0 + mtspr DBAT2L, r0 + mtspr DBAT3U, r0 + mtspr DBAT3L, r0 + mtspr IBAT0U, r0 + mtspr IBAT0L, r0 + mtspr IBAT1U, r0 + mtspr IBAT1L, r0 + mtspr IBAT2U, r0 + mtspr IBAT2L, r0 + mtspr IBAT3U, r0 + mtspr IBAT3L, r0 + SYNC + + /* invalidate all tlb's + * + * From the 603e User Manual: "The 603e provides the ability to + * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) + * instruction invalidates the TLB entry indexed by the EA, and + * operates on both the instruction and data TLBs simultaneously + * invalidating four TLB entries (both sets in each TLB). The + * index corresponds to bits 15-19 of the EA. To invalidate all + * entries within both TLBs, 32 tlbie instructions should be + * issued, incrementing this field by one each time." + * + * "Note that the tlbia instruction is not implemented on the + * 603e." + * + * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 + * incrementing by 0x1000 each time. The code below is sort of + * based on code in "flush_tlbs" from arch/ppc/kernel/head.S + * + */ + + li r3, 32 + mtctr r3 + li r3, 0 +1: tlbie r3 + addi r3, r3, 0x1000 + bdnz 1b + SYNC + + /* Done! */ + /*------------------------------*/ + blr + +/* Cache functions. + * + * Note: requires that all cache bits in + * HID0 are in the low half word. + */ + .globl icache_enable +icache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_ICE + lis r4, 0 + ori r4, r4, HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_disable +icache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_ICE|HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_status +icache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_ICE_SHIFT, 31, 31 + blr + + .globl dcache_enable +dcache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_ENABLE_DATA_CACHE + lis r4, 0 + ori r4, r4, HID0_LOCK_DATA_CACHE + andc r3, r3, r4 + ori r4, r3, HID0_LOCK_INSTRUCTION_CACHE + sync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_disable +dcache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE + andc r3, r3, r4 + ori r4, r3, HID0_INVALIDATE_DATA_CACHE + sync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_status +dcache_status: + mfspr r3, HID0 + rlwinm r3, r3, HID0_DCE_SHIFT, 31, 31 + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*-------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + * + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + la r8,-4(r4) + la r7,-4(r3) + + /* copy */ +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + + addi r0,r5,3 + srwi. r0,r0,2 + mtctr r0 + la r8,-4(r4) + la r7,-4(r3) + + /* and compare */ +20: lwzu r20,4(r8) + lwzu r21,4(r7) + xor. r22, r20, r21 + bne 30f + bdnz 20b + b 4f + + /* compare failed */ +30: li r3, 0 + blr + +2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: + bl un_setup_stack_in_data_cache + mr r7, r3 + mr r8, r4 + bl dcache_disable + mr r3, r7 + mr r4, r8 + + cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mfspr r7,HID0 /* don't do dcbst if dcache is disabled*/ + rlwinm r7,r7,HID0_DCE_SHIFT,31,31 + cmpwi r7,0 + beq 9f + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ +9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ + rlwinm r7,r7,HID0_DCE_SHIFT,31,31 + cmpwi r7,0 + beq 7f + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) +#if defined(CONFIG_HYMOD) + /* + * For HYMOD - the environment is the very last item in flash. + * The real .bss stops just before environment starts, so only + * clear up to that point. + * + * taken from mods for FADS board + */ + lwz r4,GOT(environment) +#else + lwz r4,GOT(_end) +#endif + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mfmsr r3 /* now that the vectors have */ + lis r7, MSR_IP@h /* relocated into low memory */ + ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ + andc r3, r3, r7 /* (if it was on) */ + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr + +#ifdef CFG_INIT_RAM_LOCK +.globl unlock_ram_in_cache +unlock_ram_in_cache: + /* invalidate the INIT_RAM section */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2,512 + mtctr r2 +1: icbi r0, r3 + dcbi r0, r3 + addi r3, r3, 32 + bdnz 1b + sync /* Wait for all icbi to complete on bus */ + isync + blr +#endif + +map_flash_by_law1: + /* When booting from ROM (Flash or EPROM), clear the */ + /* Address Mask in OR0 so ROM appears everywhere */ + /*----------------------------------------------------*/ + lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */ + lwz r4, OR0@l(r3) + li r5, 0x7fff /* r5 <= 0x00007FFFF */ + and r4, r4, r5 + stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ + + /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, + * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] + * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot + * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is + * 0xFF800. From the hard resetting to here, the processor fetched and + * executed the instructions one by one. There is not absolutely + * jumping happened. Laterly, the u-boot code has to do an absolutely + * jumping to tell the CPU instruction fetching component what the + * u-boot TEXT base address is. Because the TEXT base resides in the + * boot ROM memory space, to garantee the code can run smoothly after + * that jumping, we must map in the entire boot ROM by Local Access + * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting + * address for boot ROM, such as 0xFE000000. In this case, the default + * LBIU Local Access Widow 0 will not cover this memory space. So, we + * need another window to map in it. + */ + lis r4, (CFG_FLASH_BASE)@h + ori r4, r4, (CFG_FLASH_BASE)@l + stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */ + lis r4, (0x80000016)@h + ori r4, r4, (0x80000016)@l + stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ + blr + + /* Though all the LBIU Local Access Windows and LBC Banks will be + * initialized in the C code, we'd better configure boot ROM's + * window 0 and bank 0 correctly at here. + */ +remap_flash_by_law0: + /* Initialize the BR0 with the boot ROM starting address. */ + lwz r4, BR0(r3) + li r5, 0x7FFF + and r4, r4, r5 + lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h + ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l + or r5, r5, r4 + stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ + + lwz r4, OR0(r3) + lis r5, 0xFF80 /* 8M */ + or r4, r4, r5 + stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */ + + lis r4, (CFG_FLASH_BASE)@h + ori r4, r4, (CFG_FLASH_BASE)@l + stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */ + + lis r4, (0x80000016)@h + ori r4, r4, (0x80000016)@l + stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */ + + xor r4, r4, r4 + stw r4, LBLAWBAR1(r3) + stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ + blr + +setup_stack_in_data_cache_on_r1: + lis r3, (CFG_IMMRBAR)@h + + /* setup D-BAT for the D-Cache (with out real memory backup) */ + + lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h + mtspr DBAT0U, r4 + ori r4, r4, 0x0002 + mtspr DBAT0L, r4 + isync + +#if 0 + /* Enable MMU */ + mfmsr r4 + ori r4, r4, (MSR_DR | MSR_IR)@l + mtmsr r4 +#endif + + /* Enable and invalidate data cache. */ + mfspr r4, HID0 + mr r5, r4 + ori r4, r4, HID0_DCE | HID0_DCI + ori r5, r5, HID0_DCE + sync + mtspr HID0, r4 + mtspr HID0, r5 + sync + + /* Allocate Initial RAM in data cache.*/ + li r0, 0 + lis r4, (CFG_INIT_RAM_ADDR)@h + ori r4, r4, (CFG_INIT_RAM_ADDR)@l + li r5, 128*8 /* 128*8*32=32Kb */ + mtctr r5 +1: + dcbz r0, r4 + addi r4, r4, 32 + bdnz 1b + isync + + /* Lock all the D-cache, basically leaving the reset of the program without dcache */ + mfspr r4, HID0 + ori r4, r4, (HID0_DLOCK)@l + sync + mtspr HID0 , r4 + + /* setup the stack pointer in r1 */ + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + li r0, 0 /* Make room for stack frame header and */ + + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + blr + +un_setup_stack_in_data_cache: + blr + mr r14, r4 + mr r15, r5 + + + lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h + mtspr DBAT0U, r4 + ori r4, r4, 0x0002 + mtspr DBAT0L, r4 + isync + + /* un lock all the D-cache */ + mfspr r4, HID0 + lis r5, (~(HID0_DLOCK))@h + ori r5, r5, (~(HID0_DLOCK))@l + and r4, r4, r5 + sync + mtspr HID0 , r4 + + /* Re - Allocate Initial RAM in data cache.*/ + li r0, 0 + lis r4, (CFG_INIT_RAM_ADDR)@h + ori r4, r4, (CFG_INIT_RAM_ADDR)@l + li r5, 128*8 /* 128*8*32=32Kb */ + mtctr r5 +1: + dcbz r0, r4 + addi r4, r4, 32 + bdnz 1b + isync + + mflr r16 + bl dcache_disable + mtlr r16 + + blr + +#if 0 +#define GREEN_LIGHT 0x2B0D4046 +#define RED_LIGHT 0x250D4046 +#define LIB_CNT 0x4FFF + +/* + * Lib Light + */ + + .globl liblight +liblight: + lis r3, CFG_IMMRBAR@h + ori r3, r3, CFG_IMMRBAR@l + li r4, 0x3002 + mtmsr r4 + xor r4, r4, r4 + mtspr HID0, r4 + mtspr HID2, r4 + lis r4, 0xF8000000@h + ori r4, r4, 0xF8000000@l + stw r4, LBLAWBAR1(r3) + lis r4, 0x8000000E@h + ori r4, r4, 0x8000000E@l + stw r4, LBLAWAR1(r3) + lis r4, 0xF8000801@h + ori r4, r4, 0xF8000801@l + stw r4, BR1(r3) + lis r4, 0xFFFFE8f0@h + ori r4, r4, 0xFFFFE8f0@l + stw r4, OR1(r3) + + lis r4, 0xF8000000@h + ori r4, r4, 0xF8000000@l + lis r5, GREEN_LIGHT@h + ori r5, r5, GREEN_LIGHT@l + lis r6, RED_LIGHT@h + ori r6, r6, RED_LIGHT@l + lis r7, LIB_CNT@h + ori r7, r7, LIB_CNT@l + +1: + stw r5, 0(r4) + mtctr r7 +2: bdnz 2b + stw r6, 0(r4) + mtctr r7 +3: bdnz 3b + b 1b + +#endif diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c new file mode 100644 index 0000000..c7a5638 --- /dev/null +++ b/cpu/mpc83xx/traps.c @@ -0,0 +1,274 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +/* + * This file handles the architecture-dependent parts of hardware + * exceptions + */ + +#include +#include +#include +#include + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ + DECLARE_GLOBAL_DATA_PTR; + int cnt = 0; + unsigned long i; + + puts ("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + putc ('\n'); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + putc ('\n'); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + putc ('\n'); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + putc ('\n'); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +#ifdef CONFIG_PCI +void dump_pci (void) +{ +/* + volatile immap_t *immap = (immap_t *) CFG_IMMR; + printf ("PCI: err status %x err mask %x err ctrl %x\n", + le32_to_cpu (immap->im_pci.pci_esr), + le32_to_cpu (immap->im_pci.pci_emr), + le32_to_cpu (immap->im_pci.pci_ecr)); + printf (" error address %x error data %x ctrl %x\n", + le32_to_cpu (immap->im_pci.pci_eacr), + le32_to_cpu (immap->im_pci.pci_edcr), + le32_to_cpu (immap->im_pci.pci_eccr)); +*/ +} +#endif + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ +#ifdef CONFIG_PCI +#if 0 + volatile immap_t *immap = (immap_t *)CFG_IMMR; +#ifdef DEBUG + dump_pci(); +#endif + /* clear the error in the error status register */ + if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) { + immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP); + return; + } +#endif +#endif /* CONFIG_PCI */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + puts ("Machine check in kernel mode.\n" + "Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + puts ("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + puts ("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + puts ("Data parity signal\n"); + break; + case (0x80000000>>15): + puts ("Address parity signal\n"); + break; + default: + puts ("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); +#ifdef CONFIG_PCI + dump_pci(); +#endif + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +SoftEmuException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + + +void +UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint(struct pt_regs *); +#endif + +void +DebugException(struct pt_regs *regs) +{ + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); +#endif +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int +addr_probe(uint *addr) +{ +#if 0 + int retval; + + __asm__ __volatile__( \ + "1: lwz %0,0(%1)\n" \ + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); + + return (retval); +#endif + return 0; +} diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile new file mode 100644 index 0000000..5298dc1 --- /dev/null +++ b/cpu/mpc85xx/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2002,2003 Motorola Inc. +# Xianghua Xiao,X.Xiao@motorola.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o resetvec.o +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ + pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o +OBJS = $(COBJS) + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c new file mode 100644 index 0000000..aa8a5a5 --- /dev/null +++ b/cpu/mpc85xx/commproc.c @@ -0,0 +1,214 @@ +/* + * Adapted for Motorola MPC8560 chips + * Xianghua Xiao + * + * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's + * copyright notice: + * + * General Purpose functions for the global management of the + * 8220 Communication Processor Module. + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) + * 2.3.99 Updates + * Copyright (c) 2003 Motorola,Inc. + * + * In addition to the individual control of the communication + * channels, there are a few functions that globally affect the + * communication processor. + * + * Buffer descriptors must be allocated from the dual ported memory + * space. The allocator for that is here. When the communication + * process is reset, we reclaim the memory available. There is + * currently no deallocator for this memory. + */ +#include +#include + +#if defined(CONFIG_CPM2) +/* + * because we have stack and init data in dual port ram + * we must reduce the size + */ +#undef CPM_DATAONLY_SIZE +#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) + +void +m8560_cpm_reset(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ulong count; + + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Reclaim the DP memory for our use. + */ + gd->dp_alloc_base = CPM_DATAONLY_BASE; + gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE; + + /* + * Reset CPM + */ + immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST; + count = 0; + do { /* Spin until command processed */ + __asm__ __volatile__ ("eieio"); + } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); +} + +/* Allocate some memory from the dual ported ram. + * To help protocols with object alignment restrictions, we do that + * if they ask. + */ +uint +m8560_cpm_dpalloc(uint size, uint align) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *)CFG_IMMR; + uint retloc; + uint align_mask, off; + uint savebase; + + align_mask = align - 1; + savebase = gd->dp_alloc_base; + + if ((off = (gd->dp_alloc_base & align_mask)) != 0) + gd->dp_alloc_base += (align - off); + + if ((off = size & align_mask) != 0) + size += align - off; + + if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) { + gd->dp_alloc_base = savebase; + panic("m8560_cpm_dpalloc: ran out of dual port ram!"); + } + + retloc = gd->dp_alloc_base; + gd->dp_alloc_base += size; + + memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size); + + return(retloc); +} + +/* We also own one page of host buffer space for the allocation of + * UART "fifos" and the like. + */ +uint +m8560_cpm_hostalloc(uint size, uint align) +{ + /* the host might not even have RAM yet - just use dual port RAM */ + return (m8560_cpm_dpalloc(size, align)); +} + +/* Set a baud rate generator. This needs lots of work. There are + * eight BRGs, which can be connected to the CPM channels or output + * as clocks. The BRGs are in two different block of internal + * memory mapped space. + * The baud rate clock is the system clock divided by something. + * It was set up long ago during the initial boot phase and is + * is given to us. + * Baud rate clocks are zero-based in the driver code (as that maps + * to port numbers). Documentation uses 1-based numbering. + */ +#define BRG_INT_CLK gd->brg_clk +#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16) + +/* This function is used by UARTS, or anything else that uses a 16x + * oversampled clock. + */ +void +m8560_cpm_setbrg(uint brg, uint rate) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uint *bp; + + /* This is good enough to get SMCs running..... + */ + if (brg < 4) { + bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); + } + else { + bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); + brg -= 4; + } + bp += brg; + *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; +} + +/* This function is used to set high speed synchronous baud rate + * clocks. + */ +void +m8560_cpm_fastbrg(uint brg, uint rate, int div16) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uint *bp; + + /* This is good enough to get SMCs running..... + */ + if (brg < 4) { + bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); + } + else { + bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); + brg -= 4; + } + bp += brg; + *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; + if (div16) + *bp |= CPM_BRG_DIV16; +} + +/* This function is used to set baud rate generators using an external + * clock source and 16x oversampling. + */ + +void +m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile uint *bp; + + if (brg < 4) { + bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); + } + else { + bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); + brg -= 4; + } + bp += brg; + *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; + if (pinsel == 0) + *bp |= CPM_BRG_EXTC_CLK3_9; + else + *bp |= CPM_BRG_EXTC_CLK5_15; +} + +#ifdef CONFIG_POST + +void post_word_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + + *save_addr = a; +} + +ulong post_word_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + + return *save_addr; +} + +#endif /* CONFIG_POST */ + +#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk new file mode 100644 index 0000000..6121074 --- /dev/null +++ b/cpu/mpc85xx/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2002,2003 Motorola Inc. +# Xianghua Xiao, X.Xiao@motorola.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500 -msoft-float -mno-string diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c new file mode 100644 index 0000000..f7fe22e --- /dev/null +++ b/cpu/mpc85xx/cpu.c @@ -0,0 +1,229 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002, 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +int checkcpu (void) +{ + sys_info_t sysinfo; + uint lcrr; /* local bus clock ratio register */ + uint clkdiv; /* clock divider portion of lcrr */ + uint pvr, svr; + uint fam; + uint ver; + uint major, minor; + + svr = get_svr(); + ver = SVR_VER(svr); + major = SVR_MAJ(svr); + minor = SVR_MIN(svr); + + puts("CPU: "); + switch (ver) { + case SVR_8540: + puts("8540"); + break; + case SVR_8541: + puts("8541"); + break; + case SVR_8555: + puts("8555"); + break; + case SVR_8560: + puts("8560"); + break; + case SVR_8548: + puts("8548"); + break; + case SVR_8548_E: + puts("8548_E"); + break; + default: + puts("Unknown"); + break; + } + printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); + + pvr = get_pvr(); + fam = PVR_FAM(pvr); + ver = PVR_VER(pvr); + major = PVR_MAJ(pvr); + minor = PVR_MIN(pvr); + + printf("Core: "); + switch (fam) { + case PVR_FAM(PVR_85xx): + puts("E500"); + break; + default: + puts("Unknown"); + break; + } + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); + + get_sys_info(&sysinfo); + + puts("Clock Configuration:\n"); + printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); + printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000); + printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); + +#if defined(CFG_LBC_LCRR) + lcrr = CFG_LBC_LCRR; +#else + { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + + lcrr = lbc->lcrr; + } +#endif + clkdiv = lcrr & 0x0f; + if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { +#ifdef CONFIG_MPC8548 + /* + * Yes, the entire PQ38 family use the same + * bit-representation for twice the clock divider values. + */ + clkdiv *= 2; +#endif + printf("LBC:%4lu MHz\n", + sysinfo.freqSystemBus / 1000000 / clkdiv); + } else { + printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); + } + + if (ver == SVR_8560) { + printf("CPM: %lu Mhz\n", + sysinfo.freqSystemBus / 1000000); + } + + puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + /* + * Initiate hard reset in debug control register DBCR0 + * Make sure MSR[DE] = 1 + */ + unsigned long val; + + val = mfspr(DBCR0); + val |= 0x70000000; + mtspr(DBCR0,val); + + return 1; +} + + +/* + * Get timebase clock frequency + */ +unsigned long get_tbclk (void) +{ + + sys_info_t sys_info; + + get_sys_info(&sys_info); + return ((sys_info.freqSystemBus + 7L) / 8L); +} + + +#if defined(CONFIG_WATCHDOG) +void +watchdog_reset(void) +{ + int re_enable = disable_interrupts(); + reset_85xx_watchdog(); + if (re_enable) enable_interrupts(); +} + +void +reset_85xx_watchdog(void) +{ + /* + * Clear TSR(WIS) bit by writing 1 + */ + unsigned long val; + val = mfspr(tsr); + val |= 0x40000000; + mtspr(tsr, val); +} +#endif /* CONFIG_WATCHDOG */ + +#if defined(CONFIG_DDR_ECC) +void dma_init(void) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; + + dma->satr0 = 0x02c40000; + dma->datr0 = 0x02c40000; + asm("sync; isync; msync"); + return; +} + +uint dma_check(void) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; + volatile uint status = dma->sr0; + + /* While the channel is busy, spin */ + while((status & 4) == 4) { + status = dma->sr0; + } + + if (status != 0) { + printf ("DMA Error: status = %x\n", status); + } + return status; +} + +int dma_xfer(void *dest, uint count, void *src) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; + + dma->dar0 = (uint) dest; + dma->sar0 = (uint) src; + dma->bcr0 = count; + dma->mr0 = 0xf000004; + asm("sync;isync;msync"); + dma->mr0 = 0xf000005; + asm("sync;isync;msync"); + return dma_check(); +} +#endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c new file mode 100644 index 0000000..efde9cc --- /dev/null +++ b/cpu/mpc85xx/cpu_init.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2003 Motorola Inc. + * Modified by Xianghua Xiao, X.Xiao@motorola.com + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_CPM2 +static void config_8560_ioports (volatile immap_t * immr) +{ + int portnum; + + for (portnum = 0; portnum < 4; portnum++) { + uint pmsk = 0, + ppar = 0, + psor = 0, + pdir = 0, + podr = 0, + pdat = 0; + iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; + iop_conf_t *eiopc = iopc + 32; + uint msk = 1; + + /* + * NOTE: + * index 0 refers to pin 31, + * index 31 refers to pin 0 + */ + while (iopc < eiopc) { + if (iopc->conf) { + pmsk |= msk; + if (iopc->ppar) + ppar |= msk; + if (iopc->psor) + psor |= msk; + if (iopc->pdir) + pdir |= msk; + if (iopc->podr) + podr |= msk; + if (iopc->pdat) + pdat |= msk; + } + + msk <<= 1; + iopc++; + } + + if (pmsk != 0) { + volatile ioport_t *iop = ioport_addr (immr, portnum); + uint tpmsk = ~pmsk; + + /* + * the (somewhat confused) paragraph at the + * bottom of page 35-5 warns that there might + * be "unknown behaviour" when programming + * PSORx and PDIRx, if PPARx = 1, so I + * decided this meant I had to disable the + * dedicated function first, and enable it + * last. + */ + iop->ppar &= tpmsk; + iop->psor = (iop->psor & tpmsk) | psor; + iop->podr = (iop->podr & tpmsk) | podr; + iop->pdat = (iop->pdat & tpmsk) | pdat; + iop->pdir = (iop->pdir & tpmsk) | pdir; + iop->ppar |= ppar; + } + } +} +#endif + +/* + * Breathe some life into the CPU... + * + * Set up the memory map + * initialize a bunch of registers + */ + +void cpu_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *memctl = &immap->im_lbc; + extern void m8560_cpm_reset (void); + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + +#ifdef CONFIG_CPM2 + config_8560_ioports(immap); +#endif + + /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary + * addresses - these have to be modified later when FLASH size + * has been determined + */ +#if defined(CFG_OR0_REMAP) + memctl->or0 = CFG_OR0_REMAP; +#endif +#if defined(CFG_OR1_REMAP) + memctl->or1 = CFG_OR1_REMAP; +#endif + + /* now restrict to preliminary range */ +#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) + memctl->br0 = CFG_BR0_PRELIM; + memctl->or0 = CFG_OR0_PRELIM; +#endif + +#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) + memctl->or1 = CFG_OR1_PRELIM; + memctl->br1 = CFG_BR1_PRELIM; +#endif + +#if !defined(CONFIG_MPC85xx) +#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) + memctl->or2 = CFG_OR2_PRELIM; + memctl->br2 = CFG_BR2_PRELIM; +#endif +#endif + +#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) + memctl->or3 = CFG_OR3_PRELIM; + memctl->br3 = CFG_BR3_PRELIM; +#endif + +#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) + memctl->or4 = CFG_OR4_PRELIM; + memctl->br4 = CFG_BR4_PRELIM; +#endif + +#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) + memctl->or5 = CFG_OR5_PRELIM; + memctl->br5 = CFG_BR5_PRELIM; +#endif + +#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) + memctl->or6 = CFG_OR6_PRELIM; + memctl->br6 = CFG_BR6_PRELIM; +#endif + +#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) + memctl->or7 = CFG_OR7_PRELIM; + memctl->br7 = CFG_BR7_PRELIM; +#endif + +#if defined(CONFIG_CPM2) + m8560_cpm_reset(); +#endif +} + + +/* + * Initialize L2 as cache. + * + * The newer 8548, etc, parts have twice as much cache, but + * use the same bit-encoding as the older 8555, etc, parts. + * + * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()? + */ + +int cpu_init_r(void) +{ +#if defined(CONFIG_L2_CACHE) + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; + volatile uint cache_ctl; + uint svr, ver; + + svr = get_svr(); + ver = SVR_VER(svr); + + asm("msync;isync"); + cache_ctl = l2cache->l2ctl; + + switch (cache_ctl & 0x30000000) { + case 0x20000000: + if (ver == SVR_8548 || ver == SVR_8548_E) { + printf ("L2 cache 512KB:"); + } else { + printf ("L2 cache 256KB:"); + } + break; + case 0x00000000: + case 0x10000000: + case 0x30000000: + default: + printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); + return -1; + } + + asm("msync;isync"); + l2cache->l2ctl = 0x68000000; /* invalidate */ + cache_ctl = l2cache->l2ctl; + asm("msync;isync"); + + l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */ + cache_ctl = l2cache->l2ctl; + asm("msync;isync"); + + printf(" enabled\n"); +#else + printf("L2 cache: disabled\n"); +#endif + + return 0; +} diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c new file mode 100644 index 0000000..d15d242 --- /dev/null +++ b/cpu/mpc85xx/ether_fcc.c @@ -0,0 +1,473 @@ +/* + * MPC8560 FCC Fast Ethernet + * Copyright (c) 2003 Motorola,Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) + * + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8560 FCC Fast Ethernet + * Basic ET HW initialization and packet RX/TX routines + * + * This code will not perform the IO port configuration. This should be + * done in the iop_conf_t structure specific for the board. + * + * TODO: + * add a PHY driver to do the negotiation + * reflect negotiation results in FPSMR + * look for ways to configure the board specific stuff elsewhere, eg. + * config_xxx.h or the board directory + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#include +#endif + +#if defined(CONFIG_CPM2) + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \ + defined(CONFIG_NET_MULTI) + +static struct ether_fcc_info_s +{ + int ether_index; + int proff_enet; + ulong cpm_cr_enet_sblock; + ulong cpm_cr_enet_page; + ulong cmxfcr_mask; + ulong cmxfcr_value; +} + ether_fcc_info[] = +{ +#ifdef CONFIG_ETHER_ON_FCC1 +{ + 0, + PROFF_FCC1, + CPM_CR_FCC1_SBLOCK, + CPM_CR_FCC1_PAGE, + CFG_CMXFCR_MASK1, + CFG_CMXFCR_VALUE1 +}, +#endif + +#ifdef CONFIG_ETHER_ON_FCC2 +{ + 1, + PROFF_FCC2, + CPM_CR_FCC2_SBLOCK, + CPM_CR_FCC2_PAGE, + CFG_CMXFCR_MASK2, + CFG_CMXFCR_VALUE2 +}, +#endif + +#ifdef CONFIG_ETHER_ON_FCC3 +{ + 2, + PROFF_FCC3, + CPM_CR_FCC3_SBLOCK, + CPM_CR_FCC3_PAGE, + CFG_CMXFCR_MASK3, + CFG_CMXFCR_VALUE3 +}, +#endif +}; + +/*---------------------------------------------------------------------*/ + +/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ +#define PKT_MAXDMA_SIZE 1520 + +/* The FCC stores dest/src/type, data, and checksum for receive packets. */ +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 + +/* Maximum input buffer size. Must be a multiple of 32. */ +#define PKT_MAXBLR_SIZE 1536 + +#define TOUT_LOOP 1000000 + +#define TX_BUF_CNT 2 + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * FCC Ethernet Tx and Rx buffer descriptors. + * Provide for Double Buffering + * Note: PKTBUFSRX is defined in net.h + */ + +typedef volatile struct rtxbd { + cbd_t rxbd[PKTBUFSRX]; + cbd_t txbd[TX_BUF_CNT]; +} RTXBD; + +/* Good news: the FCC supports external BDs! */ +#ifdef __GNUC__ +static RTXBD rtx __attribute__ ((aligned(8))); +#else +#error "rtx must be 64-bit aligned" +#endif + +#undef ET_DEBUG + +static int fec_send(struct eth_device* dev, volatile void *packet, int length) +{ + int i = 0; + int result = 0; + + if (length <= 0) { + printf("fec: bad packet size: %d\n", length); + goto out; + } + + for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + printf("fec: tx buffer not ready\n"); + goto out; + } + } + + rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; + rtx.txbd[txIdx].cbd_datlen = length; + rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \ + BD_ENET_TX_TC | BD_ENET_TX_PAD); + + for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + printf("fec: tx error\n"); + goto out; + } + } + +#ifdef ET_DEBUG + printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc); + printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length); + for(i=0;i<(length/16 + 1);i++) { + printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\ + *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \ + *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3)); + } +#endif + + /* return only status bits */ + result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; + txIdx = (txIdx + 1) % TX_BUF_CNT; + +out: + return result; +} + +static int fec_recv(struct eth_device* dev) +{ + int length; + + for (;;) + { + if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + length = rtx.rxbd[rxIdx].cbd_datlen; + + if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { + printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); + } + else { + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[rxIdx], length - 4); + } + + + /* Give the buffer back to the FCC. */ + rtx.rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } + else { + rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + } + return length; +} + + +static int fec_init(struct eth_device* dev, bd_t *bis) +{ + struct ether_fcc_info_s * info = dev->priv; + int i; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp); + fcc_enet_t *pram_ptr; + unsigned long mem_addr; + +#if 0 + mii_discover_phy(); +#endif + + /* 28.9 - (1-2): ioports have been set up already */ + + /* 28.9 - (3): connect FCC's tx and rx clocks */ + immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */ + immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | + info->cmxfcr_value; + + /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ + if(info->ether_index == 0) { + immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + } else if (info->ether_index == 1) { + immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + } else if (info->ether_index == 2) { + immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + } + + /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ + if(info->ether_index == 0) { + immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + } else if (info->ether_index == 1){ + immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + } else if (info->ether_index == 2){ + immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + } + + /* 28.9 - (6): FDSR: Ethernet Syn */ + if(info->ether_index == 0) { + immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555; + } else if (info->ether_index == 1) { + immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555; + } else if (info->ether_index == 2) { + immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555; + } + + /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ + rxIdx = 0; + txIdx = 0; + + /* Setup Receiver Buffer Descriptors */ + for (i = 0; i < PKTBUFSRX; i++) + { + rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx.rxbd[i].cbd_datlen = 0; + rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; + } + rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* Setup Ethernet Transmitter Buffer Descriptors */ + for (i = 0; i < TX_BUF_CNT; i++) + { + rtx.txbd[i].cbd_sc = 0; + rtx.txbd[i].cbd_datlen = 0; + rtx.txbd[i].cbd_bufaddr = 0; + } + rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* 28.9 - (7): initialize parameter ram */ + pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]); + + /* clear whole structure to make sure all reserved fields are zero */ + memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); + + /* + * common Parameter RAM area + * + * Allocate space in the reserved FCC area of DPRAM for the + * internal buffers. No one uses this space (yet), so we + * can do this. Later, we will add resource management for + * this area. + * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560 + * 0x9000 for MPC8541, MPC8555 + */ + mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); + pram_ptr->fen_genfcc.fcc_riptr = mem_addr; + pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; + /* + * Set maximum bytes per receive buffer. + * It must be a multiple of 32. + */ + pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ + /* localbus SDRAM should be preferred */ + pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | + CFG_CPMFCR_RAMTYPE) << 24; + pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); + pram_ptr->fen_genfcc.fcc_rbdstat = 0; + pram_ptr->fen_genfcc.fcc_rbdlen = 0; + pram_ptr->fen_genfcc.fcc_rdptr = 0; + /* localbus SDRAM should be preferred */ + pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | + CFG_CPMFCR_RAMTYPE) << 24; + pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); + pram_ptr->fen_genfcc.fcc_tbdstat = 0; + pram_ptr->fen_genfcc.fcc_tbdlen = 0; + pram_ptr->fen_genfcc.fcc_tdptr = 0; + + /* protocol-specific area */ + pram_ptr->fen_statbuf = 0x0; + pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ + pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ + pram_ptr->fen_crcec = 0; + pram_ptr->fen_alec = 0; + pram_ptr->fen_disfc = 0; + pram_ptr->fen_retlim = 15; /* Retry limit threshold */ + pram_ptr->fen_retcnt = 0; + pram_ptr->fen_pper = 0; + pram_ptr->fen_boffcnt = 0; + pram_ptr->fen_gaddrh = 0; + pram_ptr->fen_gaddrl = 0; + pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ + /* + * Set Ethernet station address. + * + * This is supplied in the board information structure, so we + * copy that into the controller. + * So far we have only been given one Ethernet address. We make + * it unique by setting a few bits in the upper byte of the + * non-static part of the address. + */ +#define ea eth_get_dev()->enetaddr + pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; + pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; + pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; +#undef ea + pram_ptr->fen_ibdcount = 0; + pram_ptr->fen_ibdstart = 0; + pram_ptr->fen_ibdend = 0; + pram_ptr->fen_txlen = 0; + pram_ptr->fen_iaddrh = 0; /* disable hash */ + pram_ptr->fen_iaddrl = 0; + pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */ + /* pad pointer. use tiptr since we don't need a specific padding char */ + pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; + pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */ + pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */ + +#if defined(ET_DEBUG) + printf("parm_ptr(0xff788500) = %p\n",pram_ptr); + printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n", + pram_ptr->fen_genfcc.fcc_rbase); + printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n", + pram_ptr->fen_genfcc.fcc_tbase); +#endif + + /* 28.9 - (8)(9): clear out events in FCCE */ + /* 28.9 - (9): FCCM: mask all events */ + if(info->ether_index == 0) { + immr->im_cpm.im_cpm_fcc1.fcce = ~0x0; + immr->im_cpm.im_cpm_fcc1.fccm = 0; + } else if (info->ether_index == 1) { + immr->im_cpm.im_cpm_fcc2.fcce = ~0x0; + immr->im_cpm.im_cpm_fcc2.fccm = 0; + } else if (info->ether_index == 2) { + immr->im_cpm.im_cpm_fcc3.fcce = ~0x0; + immr->im_cpm.im_cpm_fcc3.fccm = 0; + } + + /* 28.9 - (10-12): we don't use ethernet interrupts */ + + /* 28.9 - (13) + * + * Let's re-initialize the channel now. We have to do it later + * than the manual describes because we have just now finished + * the BD initialization. + */ + cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page, + info->cpm_cr_enet_sblock, + 0x0c, + CPM_CR_INIT_TRX) | CPM_CR_FLG; + do { + __asm__ __volatile__ ("eieio"); + } while (cp->cpcr & CPM_CR_FLG); + + /* 28.9 - (14): enable tx/rx in gfmr */ + if(info->ether_index == 0) { + immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + } else if (info->ether_index == 1) { + immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + } else if (info->ether_index == 2) { + immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + } + + return 1; +} + +static void fec_halt(struct eth_device* dev) +{ + struct ether_fcc_info_s * info = dev->priv; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + + /* write GFMR: disable tx/rx */ + if(info->ether_index == 0) { + immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + } else if(info->ether_index == 1) { + immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + } else if(info->ether_index == 2) { + immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + } +} + +int fec_initialize(bd_t *bis) +{ + struct eth_device* dev; + int i; + + for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) + { + dev = (struct eth_device*) malloc(sizeof *dev); + memset(dev, 0, sizeof *dev); + + sprintf(dev->name, "FCC%d ETHERNET", + ether_fcc_info[i].ether_index + 1); + dev->priv = ðer_fcc_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + eth_register(dev); + +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \ + && defined(CONFIG_BITBANGMII) + miiphy_register(dev->name, + bb_miiphy_read, bb_miiphy_write); +#endif + } + + return 1; +} + +#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ + +#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/i2c.c b/cpu/mpc85xx/i2c.c new file mode 100644 index 0000000..32dcf5d --- /dev/null +++ b/cpu/mpc85xx/i2c.c @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao + * Adapted for Motorola 85xx chip. + * + * (C) Copyright 2003 + * Gleb Natapov + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk + * + * Hardware I2C driver for MPC107 PCI bridge. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_HARD_I2C +#include + +#define TIMEOUT (CFG_HZ/4) + +#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000)) + +#define I2CADR &I2C_Addr[0] +#define I2CFDR &I2C_Addr[4] +#define I2CCCR &I2C_Addr[8] +#define I2CCSR &I2C_Addr[12] +#define I2CCDR &I2C_Addr[16] +#define I2CDFSRR &I2C_Addr[20] + +#define I2C_READ 1 +#define I2C_WRITE 0 + +void +i2c_init(int speed, int slaveadd) +{ + /* stop I2C controller */ + writeb(0x0, I2CCCR); + + /* set clock */ + writeb(0x3f, I2CFDR); + + /* set default filter */ + writeb(0x10,I2CDFSRR); + + /* write slave address */ + writeb(slaveadd, I2CADR); + + /* clear status register */ + writeb(0x0, I2CCSR); + + /* start I2C controller */ + writeb(MPC85xx_I2CCR_MEN, I2CCCR); +} + +static __inline__ int +i2c_wait4bus (void) +{ + ulong timeval = get_timer (0); + + while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) { + if (get_timer (timeval) > TIMEOUT) { + return -1; + } + } + + return 0; +} + +static __inline__ int +i2c_wait (int write) +{ + u32 csr; + ulong timeval = get_timer (0); + + do { + csr = readb(I2CCSR); + + if (!(csr & MPC85xx_I2CSR_MIF)) + continue; + + writeb(0x0, I2CCSR); + + if (csr & MPC85xx_I2CSR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & MPC85xx_I2CSR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } + + return 0; + } while (get_timer (timeval) < TIMEOUT); + + debug("i2c_wait: timed out\n"); + return -1; +} + +static __inline__ int +i2c_write_addr (u8 dev, u8 dir, int rsta) +{ + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | + (rsta?MPC85xx_I2CCR_RSTA:0), + I2CCCR); + + writeb((dev << 1) | dir, I2CCDR); + + if (i2c_wait (I2C_WRITE) < 0) + return 0; + + return 1; +} + +static __inline__ int +__i2c_write (u8 *data, int length) +{ + int i; + + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, + I2CCCR); + + for (i=0; i < length; i++) { + writeb(data[i], I2CCDR); + + if (i2c_wait (I2C_WRITE) < 0) + break; + } + + return i; +} + +static __inline__ int +__i2c_read (u8 *data, int length) +{ + int i; + + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | + ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), + I2CCCR); + + /* dummy read */ + readb(I2CCDR); + + for (i=0; i < length; i++) { + if (i2c_wait (I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | + MPC85xx_I2CCR_TXAK, + I2CCCR); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); + + data[i] = readb(I2CCDR); + } + + return i; +} + +int +i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + if (i2c_write_addr (dev, I2C_READ, 1) == 0) + goto exit; + + i = __i2c_read (data, length); + + exit: + writeb(MPC85xx_I2CCR_MEN, I2CCCR); + + return !(i == length); +} + +int +i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + i = __i2c_write (data, length); + + exit: + writeb(MPC85xx_I2CCR_MEN, I2CCCR); + + return !(i == length); +} + +int i2c_probe (uchar chip) +{ + int tmp; + + /* + * Try to read the first location of the chip. The underlying + * driver doesn't appear to support sending just the chip address + * and looking for an back. + */ + udelay(10000); + return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); +} + +uchar i2c_reg_read (uchar i2c_addr, uchar reg) +{ + uchar buf[1]; + + i2c_read (i2c_addr, reg, 1, buf, 1); + + return (buf[0]); +} + +void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write (i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c new file mode 100644 index 0000000..832781b --- /dev/null +++ b/cpu/mpc85xx/interrupts.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 (440 port) + * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com + * + * (C) Copyright 2003 Motorola Inc. (MPC85xx port) + * Xianghua Xiao (X.Xiao@motorola.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +unsigned decrementer_count; /* count value for 1e6/HZ microseconds */ + +static __inline__ unsigned long get_msr(void) +{ + unsigned long msr; + + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr(unsigned long msr) +{ + asm volatile("mtmsr %0" : : "r" (msr)); + asm volatile("isync"); +} + +static __inline__ unsigned long get_dec (void) +{ + unsigned long val; + + asm volatile ("mfdec %0":"=r" (val):); + + return val; +} + + +static __inline__ void set_dec (unsigned long val) +{ + if (val) + asm volatile ("mtdec %0"::"r" (val)); +} + +void enable_interrupts (void) +{ + set_msr (get_msr() | MSR_EE); +} + +/* returns flag if MSR_EE was set before */ +int disable_interrupts (void) +{ + ulong msr = get_msr(); + set_msr (msr & ~MSR_EE); + return ((msr & MSR_EE) != 0); +} + +int interrupt_init (void) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + + immr->im_pic.gcr = MPC85xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC85xx_PICGCR_RST); + immr->im_pic.gcr = MPC85xx_PICGCR_M; + decrementer_count = get_tbclk() / CFG_HZ; + mtspr(SPRN_TCR, TCR_PIE); + set_dec (decrementer_count); + set_msr (get_msr () | MSR_EE); + return (0); +} + +/* + * Install and free a interrupt handler. Not implemented yet. + */ + +void +irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +{ + return; +} + +void +irq_free_handler(int vec) +{ + return; +} + +/****************************************************************************/ + + +volatile ulong timestamp = 0; + +/* + * timer_interrupt - gets called when the decrementer overflows, + * with interrupts disabled. + * Trivial implementation - no need to be really accurate. + */ +void timer_interrupt(struct pt_regs *regs) +{ + timestamp++; + set_dec (decrementer_count); + mtspr(SPRN_TSR, TSR_PIS); +#if defined(CONFIG_WATCHDOG) + if ((timestamp % 1000) == 0) + reset_85xx_watchdog(); +#endif /* CONFIG_WATCHDOG */ +} + +void reset_timer (void) +{ + timestamp = 0; +} + +ulong get_timer (ulong base) +{ + return (timestamp - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) + +/******************************************************************************* + * + * irqinfo - print information about PCI devices,not implemented. + * + */ +int +do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf ("\nInterrupt-unsupported:\n"); + + return 0; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c new file mode 100644 index 0000000..a94493e --- /dev/null +++ b/cpu/mpc85xx/pci.c @@ -0,0 +1,122 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI Configuration space access support for MPC85xx PCI Bridge + */ +#include +#include +#include + + +#if defined(CONFIG_PCI) + +void +pci_mpc85xx_init(struct pci_controller *hose) +{ + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; + volatile ccsr_pcix_t *pcix = &immap->im_pcix; + + u16 reg16; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 2; + + pci_setup_indirect(hose, + (CFG_IMMR+0x8000), + (CFG_IMMR+0x8004)); + + pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->potear1 = 0x00000000; + pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->powbear1 = 0x00000000; + pcix->powar1 = 0x8004401c; /* 512M MEM space */ + + pcix->potar2 = 0x00000000; + pcix->potear2 = 0x00000000; + pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->powbear2 = 0x00000000; + pcix->powar2 = 0x80088017; /* 16M IO space */ + + pcix->pitar1 = 0x00000000; + pcix->piwbar1 = 0x00000000; + pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, + * Snoop R/W, 2G */ + + /* + * Hose scan. + */ + pci_register_hose(hose); + + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + +#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) + /* + * This is a SW workaround for an apparent HW problem + * in the PCI controller on the MPC85555/41 CDS boards. + * The first config cycle must be to a valid, known + * device on the PCI bus in order to trick the PCI + * controller state machine into a known valid state. + * Without this, the first config cycle has the chance + * of hanging the controller permanently, just leaving + * it in a semi-working state, or leaving it working. + * + * Pick on the Tundra, Device 17, to get it right. + */ + { + u8 header_type; + + pci_hose_read_config_byte(hose, + PCI_BDF(0,17,0), + PCI_HEADER_TYPE, + &header_type); + } +#endif + + hose->last_busno = pci_hose_scan(hose); +} + +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc85xx/resetvec.S b/cpu/mpc85xx/resetvec.S new file mode 100644 index 0000000..29555d4 --- /dev/null +++ b/cpu/mpc85xx/resetvec.S @@ -0,0 +1,2 @@ + .section .resetvec,"ax" + b _start_e500 diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c new file mode 100644 index 0000000..cf060d6 --- /dev/null +++ b/cpu/mpc85xx/serial_scc.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * Modified based on 8260 for 8560. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00. + */ + +/* + * Minimal serial functions needed to use one of the SCC ports + * as serial console interface. + */ + +#include +#include + +#if defined(CONFIG_CPM2) +#if defined(CONFIG_CONS_ON_SCC) + +#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ + +#define SCC_INDEX 0 +#define PROFF_SCC PROFF_SCC1 +#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ + CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) +#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK + +#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ + +#define SCC_INDEX 1 +#define PROFF_SCC PROFF_SCC2 +#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ + CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) +#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK + +#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ + +#define SCC_INDEX 2 +#define PROFF_SCC PROFF_SCC3 +#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ + CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) +#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK + +#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ + +#define SCC_INDEX 3 +#define PROFF_SCC PROFF_SCC4 +#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ + CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) +#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK + +#else + +#error "console not correctly defined" + +#endif + +int serial_init (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_scc_t *sp; + volatile scc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp); + uint dpaddr; + + /* initialize pointers to SCC */ + + sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]); + up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); + + /* Disable transmitter/receiver. + */ + sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + /* put the SCC channel into NMSI (non multiplexd serial interface) + * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). + */ + im->im_cpm.im_cpm_mux.cmxscr = \ + (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; + + /* Set up the baud rate generator. + */ + serial_setbrg (); + + /* Allocate space for two buffer descriptors in the DP ram. + * damm: allocating space after the two buffers for rx/tx data + */ + + dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]); + rbdf->cbd_bufaddr = (uint) (rbdf+2); + rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; + tbdf->cbd_sc = BD_SC_WRAP; + + /* Set up the uart parameters in the parameter ram. + */ + up->scc_genscc.scc_rbase = dpaddr; + up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); + up->scc_genscc.scc_rfcr = CPMFCR_EB; + up->scc_genscc.scc_tfcr = CPMFCR_EB; + up->scc_genscc.scc_mrblr = 1; + up->scc_maxidl = 0; + up->scc_brkcr = 1; + up->scc_parec = 0; + up->scc_frmec = 0; + up->scc_nosec = 0; + up->scc_brkec = 0; + up->scc_uaddr1 = 0; + up->scc_uaddr2 = 0; + up->scc_toseq = 0; + up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; + up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; + up->scc_rccm = 0xc0ff; + + /* Mask all interrupts and remove anything pending. + */ + sp->sccm = 0; + sp->scce = 0xffff; + + /* Set 8 bit FIFO, 16 bit oversampling and UART mode. + */ + sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ + sp->gsmrl = \ + SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; + + /* Set CTS no flow control, 1 stop bit, 8 bit character length, + * normal async UART mode, no parity + */ + sp->psmr = SCU_PSMR_CL; + + /* execute the "Init Rx and Tx params" CP command. + */ + + while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, + 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. + */ + sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; + + return (0); +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CONS_USE_EXTC) + m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate, + CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); +#else + m8560_cpm_setbrg(SCC_INDEX, gd->baudrate); +#endif +} + +void +serial_putc(const char c) +{ + volatile scc_uart_t *up; + volatile cbd_t *tbdf; + volatile immap_t *im; + + if (c == '\n') + serial_putc ('\r'); + + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); + tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]); + + /* Wait for last character to go. + */ + while (tbdf->cbd_sc & BD_SC_READY) + ; + + /* Load the character into the transmit buffer. + */ + *(volatile char *)tbdf->cbd_bufaddr = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int +serial_getc(void) +{ + volatile cbd_t *rbdf; + volatile scc_uart_t *up; + volatile immap_t *im; + unsigned char c; + + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); + + /* Wait for character to show up. + */ + while (rbdf->cbd_sc & BD_SC_EMPTY) + ; + + /* Grab the char and clear the buffer again. + */ + c = *(volatile unsigned char *)rbdf->cbd_bufaddr; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return (c); +} + +int +serial_tstc() +{ + volatile cbd_t *rbdf; + volatile scc_uart_t *up; + volatile immap_t *im; + + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); + + return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); +} + +#endif /* CONFIG_CONS_ON_SCC */ + +#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c new file mode 100644 index 0000000..af99282 --- /dev/null +++ b/cpu/mpc85xx/spd_sdram.c @@ -0,0 +1,1118 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void dma_init(void); +extern uint dma_check(void); +extern int dma_xfer(void *dest, uint count, void *src); +#endif + +#ifdef CONFIG_SPD_EEPROM + +#ifndef CFG_READ_SPD +#define CFG_READ_SPD i2c_read +#endif + +static unsigned int setup_laws_and_tlbs(unsigned int memsize); + + +/* + * Convert picoseconds into clock cycles (rounding up if needed). + */ + +int +picos_to_clk(int picos) +{ + int clks; + + clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); + if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + clks++; + } + + return clks; +} + + +/* + * Calculate the Density of each Physical Rank. + * Returned size is in bytes. + * + * Study these table from Byte 31 of JEDEC SPD Spec. + * + * DDR I DDR II + * Bit Size Size + * --- ----- ------ + * 7 high 512MB 512MB + * 6 256MB 256MB + * 5 128MB 128MB + * 4 64MB 16GB + * 3 32MB 8GB + * 2 16MB 4GB + * 1 2GB 2GB + * 0 low 1GB 1GB + * + * Reorder Table to be linear by stripping the bottom + * 2 or 5 bits off and shifting them up to the top. + */ + +unsigned int +compute_banksize(unsigned int mem_type, unsigned char row_dens) +{ + unsigned int bsize; + + if (mem_type == SPD_MEMTYPE_DDR) { + /* Bottom 2 bits up to the top. */ + bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; + debug("DDR: DDR I rank density = 0x%08x\n", bsize); + } else { + /* Bottom 5 bits up to the top. */ + bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27; + debug("DDR: DDR II rank density = 0x%08x\n", bsize); + } + return bsize; +} + + +/* + * Convert a two-nibble BCD value into a cycle time. + * While the spec calls for nano-seconds, picos are returned. + * + * This implements the tables for bytes 9, 23 and 25 for both + * DDR I and II. No allowance for distinguishing the invalid + * fields absent for DDR I yet present in DDR II is made. + * (That is, cycle times of .25, .33, .66 and .75 ns are + * allowed for both DDR II and I.) + */ + +unsigned int +convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) +{ + /* + * Table look up the lower nibble, allow DDR I & II. + */ + unsigned int tenths_ps[16] = { + 0, + 100, + 200, + 300, + 400, + 500, + 600, + 700, + 800, + 900, + 250, + 330, /* FIXME: Is 333 better/valid? */ + 660, /* FIXME: Is 667 better/valid? */ + 750, + 0, /* undefined */ + 0 /* undefined */ + }; + + unsigned int whole_ns = (spd_val & 0xF0) >> 4; + unsigned int tenth_ns = spd_val & 0x0F; + unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; + + return ps; +} + + +long int +spd_sdram(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr; + volatile ccsr_gur_t *gur = &immap->im_gur; + spd_eeprom_t spd; + unsigned int n_ranks; + unsigned int rank_density; + unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned int odt_cfg, mode_odt_enable; + unsigned int dqs_cfg; + unsigned char twr_clk, twtr_clk, twr_auto_clk; + unsigned int tCKmin_ps, tCKmax_ps; + unsigned int max_data_rate, effective_data_rate; + unsigned int busfreq; + unsigned sdram_cfg; + unsigned int memsize; + unsigned char caslat, caslat_ctrl; + unsigned int trfc, trfc_clk, trfc_low, trfc_high; + unsigned int trcd_clk; + unsigned int trtp_clk; + unsigned char cke_min_clk; + unsigned char add_lat; + unsigned char wr_lat; + unsigned char wr_data_delay; + unsigned char four_act; + unsigned char cpo; + unsigned char burst_len; + unsigned int mode_caslat; + unsigned char sdram_type; + unsigned char d_init; + + /* + * Read SPD information. + */ + CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd)); + + /* + * Check for supported memory module types. + */ + if (spd.mem_type != SPD_MEMTYPE_DDR && + spd.mem_type != SPD_MEMTYPE_DDR2) { + printf("Unable to locate DDR I or DDR II module.\n" + " Fundamental memory type is 0x%0x\n", + spd.mem_type); + return 0; + } + + /* + * These test gloss over DDR I and II differences in interpretation + * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks + * are not supported on DDR I; and not encoded on DDR II. + * + * Also note that the 8548 controller can support: + * 12 <= nrow <= 16 + * and + * 8 <= ncol <= 11 (still, for DDR) + * 6 <= ncol <= 9 (for FCRAM) + */ + if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { + printf("DDR: Unsupported number of Row Addr lines: %d.\n", + spd.nrow_addr); + return 0; + } + if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { + printf("DDR: Unsupported number of Column Addr lines: %d.\n", + spd.ncol_addr); + return 0; + } + + /* + * Determine the number of physical banks controlled by + * different Chip Select signals. This is not quite the + * same as the number of DIMM modules on the board. Feh. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + n_ranks = spd.nrows; + } else { + n_ranks = (spd.nrows & 0x7) + 1; + } + + debug("DDR: number of ranks = %d\n", n_ranks); + + if (n_ranks > 2) { + printf("DDR: Only 2 chip selects are supported: %d\n", + n_ranks); + return 0; + } + + /* + * Adjust DDR II IO voltage biasing. It just makes it work. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + gur->ddrioovcr = (0 + | 0x80000000 /* Enable */ + | 0x10000000 /* VSEL to 1.8V */ + ); + } + + /* + * Determine the size of each Rank in bytes. + */ + rank_density = compute_banksize(spd.mem_type, spd.row_dens); + + + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr->cs0_bnds = (rank_density >> 24) - 1; + + /* + * ODT configuration recommendation from DDR Controller Chapter. + */ + odt_rd_cfg = 0; /* Never assert ODT */ + odt_wr_cfg = 0; /* Never assert ODT */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ +#if 0 + /* FIXME: How to determine the number of dimm modules? */ + if (n_dimm_modules == 2) { + odt_rd_cfg = 1; /* Assert ODT on reads to CS0 */ + } +#endif + } + + ddr->cs0_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("\n"); + debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg + */ + ddr->cs1_bnds = ( (rank_density >> 8) + | ((rank_density >> (24 - 1)) - 1) ); + ddr->cs1_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); + debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config); + } + + + /* + * Find the largest CAS by locating the highest 1 bit + * in the spd.cas_lat field. Translate it to a DDR + * controller field value: + * + * CAS Lat DDR I DDR II Ctrl + * Clocks SPD Bit SPD Bit Value + * ------- ------- ------- ----- + * 1.0 0 0001 + * 1.5 1 0010 + * 2.0 2 2 0011 + * 2.5 3 0100 + * 3.0 4 3 0101 + * 3.5 5 0110 + * 4.0 4 0111 + * 4.5 1000 + * 5.0 5 1001 + */ + caslat = __ilog2(spd.cas_lat); + if ((spd.mem_type == SPD_MEMTYPE_DDR) + && (caslat > 5)) { + printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); + return 0; + + } else if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (caslat < 2 || caslat > 5)) { + printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", + spd.cas_lat); + return 0; + } + debug("DDR: caslat SPD bit is %d\n", caslat); + + /* + * Calculate the Maximum Data Rate based on the Minimum Cycle time. + * The SPD clk_cycle field (tCKmin) is measured in tenths of + * nanoseconds and represented as BCD. + */ + tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle); + debug("DDR: tCKmin = %d ps\n", tCKmin_ps); + + /* + * Double-data rate, scaled 1000 to picoseconds, and back down to MHz. + */ + max_data_rate = 2 * 1000 * 1000 / tCKmin_ps; + debug("DDR: Module max data rate = %d Mhz\n", max_data_rate); + + + /* + * Adjust the CAS Latency to allow for bus speeds that + * are slower than the DDR module. + */ + busfreq = get_bus_freq(0) / 1000000; /* MHz */ + + effective_data_rate = max_data_rate; + if (busfreq < 90) { + /* DDR rate out-of-range */ + puts("DDR: platform frequency is not fit for DDR rate\n"); + return 0; + + } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) { + /* + * busfreq 90~230 range, treated as DDR 200. + */ + effective_data_rate = 200; + if (spd.clk_cycle3 == 0xa0) /* 10 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0xa0) + caslat--; + + } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) { + /* + * busfreq 230~280 range, treated as DDR 266. + */ + effective_data_rate = 266; + if (spd.clk_cycle3 == 0x75) /* 7.5 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x75) + caslat--; + + } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) { + /* + * busfreq 280~350 range, treated as DDR 333. + */ + effective_data_rate = 333; + if (spd.clk_cycle3 == 0x60) /* 6.0 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x60) + caslat--; + + } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) { + /* + * busfreq 350~460 range, treated as DDR 400. + */ + effective_data_rate = 400; + if (spd.clk_cycle3 == 0x50) /* 5.0 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x50) + caslat--; + + } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) { + /* + * busfreq 460~560 range, treated as DDR 533. + */ + effective_data_rate = 533; + if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x3D) + caslat--; + + } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) { + /* + * busfreq 560~700 range, treated as DDR 667. + */ + effective_data_rate = 667; + if (spd.clk_cycle3 == 0x30) /* 3.0 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x30) + caslat--; + + } else if (700 <= busfreq) { + /* + * DDR rate out-of-range + */ + printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n", + busfreq, max_data_rate); + return 0; + } + + + /* + * Convert caslat clocks to DDR controller value. + * Force caslat_ctrl to be DDR Controller field-sized. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + caslat_ctrl = (caslat + 1) & 0x07; + } else { + caslat_ctrl = (2 * caslat - 1) & 0x0f; + } + + debug("DDR: effective data rate is %d MHz\n", effective_data_rate); + debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", + caslat, caslat_ctrl); + + /* + * Timing Config 0. + * Avoid writing for DDR I. The new PQ38 DDR controller + * dreams up non-zero default values to be backwards compatible. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + unsigned char taxpd_clk = 8; /* By the book. */ + unsigned char tmrd_clk = 2; /* By the book. */ + unsigned char act_pd_exit = 2; /* Empirical? */ + unsigned char pre_pd_exit = 6; /* Empirical? */ + + ddr->timing_cfg_0 = (0 + | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ + | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ + | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ + | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ + ); +#if 0 + ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */ +#endif + debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); + + } else { +#if 0 + /* + * Force extra cycles with 0xaa bits. + * Incidentally supply the dreamt-up backwards compat value! + */ + ddr->timing_cfg_0 = 0x00110105; /* backwards compat value */ + ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */ + debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); +#endif + } + + + /* + * Some Timing Config 1 values now. + * Sneak Extended Refresh Recovery in here too. + */ + + /* + * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, + * use conservative value. + * For DDR II, they are bytes 36 and 37, in quarter nanos. + */ + + if (spd.mem_type == SPD_MEMTYPE_DDR) { + twr_clk = 3; /* Clocks */ + twtr_clk = 1; /* Clocks */ + } else { + twr_clk = picos_to_clk(spd.twr * 250); + twtr_clk = picos_to_clk(spd.twtr * 250); + } + + /* + * Calculate Trfc, in picos. + * DDR I: Byte 42 straight up in ns. + * DDR II: Byte 40 and 42 swizzled some, in ns. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + trfc = spd.trfc * 1000; /* up to ps */ + } else { + unsigned int byte40_table_ps[8] = { + 0, + 250, + 330, + 500, + 660, + 750, + 0, + 0 + }; + + trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 + + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; + } + trfc_clk = picos_to_clk(trfc); + + /* + * Trcd, Byte 29, from quarter nanos to ps and clocks. + */ + trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; + + /* + * Convert trfc_clk to DDR controller fields. DDR I should + * fit in the REFREC field (16-19) of TIMING_CFG_1, but the + * 8548 controller has an extended REFREC field of three bits. + * The controller automatically adds 8 clocks to this value, + * so preadjust it down 8 first before splitting it up. + */ + trfc_low = (trfc_clk - 8) & 0xf; + trfc_high = ((trfc_clk - 8) >> 4) & 0x3; + + /* + * Sneak in some Extended Refresh Recovery. + */ + ddr->ext_refrec = (trfc_high << 16); + debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); + + ddr->timing_cfg_1 = + (0 + | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */ + | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */ + | (trcd_clk << 20) /* ACTTORW */ + | (caslat_ctrl << 16) /* CASLAT */ + | (trfc_low << 12) /* REFEC */ + | ((twr_clk & 0x07) << 8) /* WRRREC */ + | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */ + | ((twtr_clk & 0x07) << 0) /* WRTORD */ + ); + + debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); + + + /* + * Timing_Config_2 + * Was: 0x00000800; + */ + + /* + * Additive Latency + * For DDR I, 0. + * For DDR II, with ODT enabled, use "a value" less than ACTTORW, + * which comes from Trcd, and also note that: + * add_lat + caslat must be >= 4 + */ + add_lat = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (odt_wr_cfg || odt_rd_cfg) + && (caslat < 4)) { + add_lat = 4 - caslat; + if (add_lat > trcd_clk) { + add_lat = trcd_clk - 1; + } + } + + /* + * Write Data Delay + * Historically 0x2 == 4/8 clock delay. + * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. + */ + wr_data_delay = 3; + + /* + * Write Latency + * Read to Precharge + * Minimum CKE Pulse Width. + * Four Activate Window + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + /* + * This is a lie. It should really be 1, but if it is + * set to 1, bits overlap into the old controller's + * otherwise unused ACSM field. If we leave it 0, then + * the HW will magically treat it as 1 for DDR 1. Oh Yea. + */ + wr_lat = 0; + + trtp_clk = 2; /* By the book. */ + cke_min_clk = 1; /* By the book. */ + four_act = 1; /* By the book. */ + + } else { + wr_lat = caslat - 1; + + /* Convert SPD value from quarter nanos to picos. */ + trtp_clk = picos_to_clk(spd.trtp * 250); + + cke_min_clk = 3; /* By the book. */ + four_act = picos_to_clk(37500); /* By the book. 1k pages? */ + } + + /* + * Empirically set ~MCAS-to-preamble override for DDR 2. + * Your milage will vary. + */ + cpo = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (effective_data_rate == 266 || effective_data_rate == 333) { + cpo = 0x7; /* READ_LAT + 5/4 */ + } else if (effective_data_rate == 400) { + cpo = 0x9; /* READ_LAT + 7/4 */ + } else { + /* Pure speculation */ + cpo = 0xb; + } + } + + ddr->timing_cfg_2 = (0 + | ((add_lat & 0x7) << 28) /* ADD_LAT */ + | ((cpo & 0x1f) << 23) /* CPO */ + | ((wr_lat & 0x7) << 19) /* WR_LAT */ + | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ + | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ + | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ + | ((four_act & 0x1f) << 0) /* FOUR_ACT */ + ); + + debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); + + + /* + * Determine the Mode Register Set. + * + * This is nominally part specific, but it appears to be + * consistent for all DDR I devices, and for all DDR II devices. + * + * caslat must be programmed + * burst length is always 4 + * burst type is sequential + * + * For DDR I: + * operating mode is "normal" + * + * For DDR II: + * other stuff + */ + + mode_caslat = 0; + + /* + * Table lookup from DDR I or II Device Operation Specs. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + if (1 <= caslat && caslat <= 4) { + unsigned char mode_caslat_table[4] = { + 0x5, /* 1.5 clocks */ + 0x2, /* 2.0 clocks */ + 0x6, /* 2.5 clocks */ + 0x3 /* 3.0 clocks */ + }; + mode_caslat = mode_caslat_table[caslat - 1]; + } else { + puts("DDR I: Only CAS Latencies of 1.5, 2.0, " + "2.5 and 3.0 clocks are supported.\n"); + return 0; + } + + } else { + if (2 <= caslat && caslat <= 5) { + mode_caslat = caslat; + } else { + puts("DDR II: Only CAS Latencies of 2.0, 3.0, " + "4.0 and 5.0 clocks are supported.\n"); + return 0; + } + } + + /* + * Encoded Burst Lenght of 4. + */ + burst_len = 2; /* Fiat. */ + + if (spd.mem_type == SPD_MEMTYPE_DDR) { + twr_auto_clk = 0; /* Historical */ + } else { + /* + * Determine tCK max in picos. Grab tWR and convert to picos. + * Auto-precharge write recovery is: + * WR = roundup(tWR_ns/tCKmax_ns). + * + * Ponder: Is twr_auto_clk different than twr_clk? + */ + tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax); + twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps; + } + + + /* + * Mode Reg in bits 16 ~ 31, + * Extended Mode Reg 1 in bits 0 ~ 15. + */ + mode_odt_enable = 0x0; /* Default disabled */ + if (odt_wr_cfg || odt_rd_cfg) { + /* + * Bits 6 and 2 in Extended MRS(1) + * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. + * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. + */ + mode_odt_enable = 0x40; /* 150 Ohm */ + } + + ddr->sdram_mode = + (0 + | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ + | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ + | (twr_auto_clk << 9) /* Write Recovery Autopre */ + | (mode_caslat << 4) /* caslat */ + | (burst_len << 0) /* Burst length */ + ); + + debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode); + + + /* + * Clear EMRS2 and EMRS3. + */ + ddr->sdram_mode_2 = 0; + debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); + + + /* + * Determine Refresh Rate. Ignore self refresh bit on DDR I. + * Table from SPD Spec, Byte 12, converted to picoseconds and + * filled in with "default" normal values. + */ + { + unsigned int refresh_clk; + unsigned int refresh_time_ns[8] = { + 15625000, /* 0 Normal 1.00x */ + 3900000, /* 1 Reduced .25x */ + 7800000, /* 2 Extended .50x */ + 31300000, /* 3 Extended 2.00x */ + 62500000, /* 4 Extended 4.00x */ + 125000000, /* 5 Extended 8.00x */ + 15625000, /* 6 Normal 1.00x filler */ + 15625000, /* 7 Normal 1.00x filler */ + }; + + refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]); + + /* + * Set BSTOPRE to 0x100 for page mode + * If auto-charge is used, set BSTOPRE = 0 + */ + ddr->sdram_interval = + (0 + | (refresh_clk & 0x3fff) << 16 + | 0x100 + ); + debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); + } + + /* + * Is this an ECC DDR chip? + * But don't mess with it if the DDR controller will init mem. + */ +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + if (spd.config == 0x02) { + ddr->err_disable = 0x0000000d; + ddr->err_sbe = 0x00ff0000; + } + debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); + debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); +#endif + + asm("sync;isync;msync"); + udelay(500); + + /* + * SDRAM Cfg 2 + */ + + /* + * When ODT is enabled, Chap 9 suggests asserting ODT to + * internal IOs only during reads. + */ + odt_cfg = 0; + if (odt_rd_cfg | odt_wr_cfg) { + odt_cfg = 0x2; /* ODT to IOs during reads */ + } + + /* + * Try to use differential DQS with DDR II. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + dqs_cfg = 0; /* No Differential DQS for DDR I */ + } else { + dqs_cfg = 0x1; /* Differential DQS for DDR II */ + } + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Use the DDR controller to auto initialize memory. + */ + d_init = 1; + ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE; + debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init); +#else + /* + * Memory will be initialized via DMA, or not at all. + */ + d_init = 0; +#endif + + ddr->sdram_cfg_2 = (0 + | (dqs_cfg << 26) /* Differential DQS */ + | (odt_cfg << 21) /* ODT */ + | (d_init << 4) /* D_INIT auto init DDR */ + ); + + debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2); + + +#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL + { + unsigned char clk_adjust; + + /* + * Setup the clock control. + * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 + * SDRAM_CLK_CNTL[5-7] = Clock Adjust + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + clk_adjust = 0x6; + } else { + clk_adjust = 0x7; + } + + ddr->sdram_clk_cntl = (0 + | 0x80000000 + | (clk_adjust << 23) + ); + debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); + } +#endif + + /* + * Figure out the settings for the sdram_cfg register. + * Build up the entire register in 'sdram_cfg' before writing + * since the write into the register will actually enable the + * memory controller; all settings must be done before enabling. + * + * sdram_cfg[0] = 1 (ddr sdram logic enable) + * sdram_cfg[1] = 1 (self-refresh-enable) + * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) + * 010 DDR 1 SDRAM + * 011 DDR 2 SDRAM + */ + sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; + sdram_cfg = (0 + | (1 << 31) /* Enable */ + | (1 << 30) /* Self refresh */ + | (sdram_type << 24) /* SDRAM type */ + ); + + /* + * sdram_cfg[3] = RD_EN - registered DIMM enable + * A value of 0x26 indicates micron registered DIMMS (micron.com) + */ + if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) { + sdram_cfg |= 0x10000000; /* RD_EN */ + } + +#if defined(CONFIG_DDR_ECC) + /* + * If the user wanted ECC (enabled via sdram_cfg[2]) + */ + if (spd.config == 0x02) { + sdram_cfg |= 0x20000000; /* ECC_EN */ + } +#endif + + /* + * REV1 uses 1T timing. + * REV2 may use 1T or 2T as configured by the user. + */ + { + uint pvr = get_pvr(); + + if (pvr != PVR_85xx_REV1) { +#if defined(CONFIG_DDR_2T_TIMING) + /* + * Enable 2T timing by setting sdram_cfg[16]. + */ + sdram_cfg |= 0x8000; /* 2T_EN */ +#endif + } + } + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + + /* + * Go! + */ + ddr->sdram_cfg = sdram_cfg; + + asm("sync;isync;msync"); + udelay(500); + + debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg); + + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { + udelay(1000); + } +#endif + + + /* + * Figure out memory size in Megabytes. + */ + memsize = n_ranks * rank_density / 0x100000; + + /* + * Establish Local Access Window and TLB mappings for DDR memory. + */ + memsize = setup_laws_and_tlbs(memsize); + if (memsize == 0) { + return 0; + } + + return memsize * 1024 * 1024; +} + + +/* + * Setup Local Access Window and TLB1 mappings for the requested + * amount of memory. Returns the amount of memory actually mapped + * (usually the original request size), or 0 on error. + */ + +static unsigned int +setup_laws_and_tlbs(unsigned int memsize) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + unsigned int tlb_size; + unsigned int law_size; + unsigned int ram_tlb_index; + unsigned int ram_tlb_address; + + /* + * Determine size of each TLB1 entry. + */ + switch (memsize) { + case 16: + case 32: + tlb_size = BOOKE_PAGESZ_16M; + break; + case 64: + case 128: + tlb_size = BOOKE_PAGESZ_64M; + break; + case 256: + case 512: + case 1024: + case 2048: + tlb_size = BOOKE_PAGESZ_256M; + break; + default: + puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n"); + + /* + * The memory was not able to be mapped. + */ + return 0; + break; + } + + /* + * Configure DDR TLB1 entries. + * Starting at TLB1 8, use no more than 8 TLB1 entries. + */ + ram_tlb_index = 8; + ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; + while (ram_tlb_address < (memsize * 1024 * 1024) + && ram_tlb_index < 16) { + mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0)); + mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size)); + mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), + 0, 0, 0, 0, 0, 0, 0, 0)); + mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), + 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + asm volatile("isync;msync;tlbwe;isync"); + + debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0)); + debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size)); + debug("DDR: MAS2=0x%08x\n", + TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), + 0, 0, 0, 0, 0, 0, 0, 0)); + debug("DDR: MAS3=0x%08x\n", + TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), + 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + + ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); + ram_tlb_index++; + } + + + /* + * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. + */ + law_size = 19 + __ilog2(memsize); + + /* + * Set up LAWBAR for all of DDR. + */ + ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + ecm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR + | (LAWAR_SIZE & law_size)); + debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1); + debug("DDR: LARAR1=0x%08x\n", ecm->lawar1); + + /* + * Confirm that the requested amount of memory was mapped. + */ + return memsize; +} + +#endif /* CONFIG_SPD_EEPROM */ + + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + +/* + * Initialize all of memory for ECC, then enable errors. + */ + +void +ddr_enable_ecc(unsigned int dram_size) +{ + uint *p = 0; + uint i = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + dma_init(); + + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((unsigned int)p & 0x1f) == 0) { + ppcDcbz((unsigned long) p); + } + *p = (unsigned int)CONFIG_MEM_INIT_VALUE; + if (((unsigned int)p & 0x1c) == 0x1c) { + ppcDcbf((unsigned long) p); + } + } + + /* 8K */ + dma_xfer((uint *)0x2000, 0x2000, (uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000, 0x4000, (uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000, 0x8000, (uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000, 0x10000, (uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000, 0x20000, (uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000, 0x40000, (uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000, 0x80000, (uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000, 0x100000, (uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000, 0x200000, (uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000, 0x400000, (uint *)0); + + for (i = 1; i < dram_size / 0x800000; i++) { + dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); + } + + /* + * Enable errors for ECC. + */ + debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); + ddr->err_disable = 0x00000000; + asm("sync;isync;msync"); + debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); +} + +#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c new file mode 100644 index 0000000..d736742 --- /dev/null +++ b/cpu/mpc85xx/speed.c @@ -0,0 +1,123 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* --------------------------------------------------------------- */ + +void get_sys_info (sys_info_t * sysInfo) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint plat_ratio,e500_ratio; + + plat_ratio = (gur->porpllsr) & 0x0000003e; + plat_ratio >>= 1; + switch(plat_ratio) { + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x08: + case 0x09: + case 0x0a: + case 0x0c: + case 0x10: + sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + break; + default: + sysInfo->freqSystemBus = 0; + break; + } + + e500_ratio = (gur->porpllsr) & 0x003f0000; + e500_ratio >>= 16; + switch(e500_ratio) { + case 0x04: + sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; + break; + case 0x05: + sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; + break; + case 0x06: + sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + break; + case 0x07: + sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; + break; + default: + sysInfo->freqProcessor = 0; + break; + } +} + +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + sys_info_t sys_info; +#if defined(CONFIG_CPM2) + volatile immap_t *immap = (immap_t *) CFG_IMMR; + uint sccr, dfbrg; + + /* set VCO = 4 * BRG */ + immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc; + sccr = immap->im_cpm.im_cpm_intctl.sccr; + dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; +#endif + get_sys_info (&sys_info); + gd->cpu_clk = sys_info.freqProcessor; + gd->bus_clk = sys_info.freqSystemBus; +#if defined(CONFIG_CPM2) + gd->vco_out = 2*sys_info.freqSystemBus; + gd->cpm_clk = gd->vco_out / 2; + gd->scc_clk = gd->vco_out / 4; + gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); +#endif + + if(gd->cpu_clk != 0) return (0); + else return (1); +} + + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + ulong val; + + sys_info_t sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqSystemBus; + + return val; +} diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S new file mode 100644 index 0000000..7ac6573 --- /dev/null +++ b/cpu/mpc85xx/start.S @@ -0,0 +1,1157 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2003 Motorola,Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards + * + * The processor starts at 0xfffffffc and the code is first executed in the + * last 4K page(0xfffff000-0xffffffff) in flash/rom. + * + */ + +#include +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#undef MSR_KERNEL +#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * e500 Startup -- after reset only the last 4KB of the effective + * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg + * section is located at THIS LAST page and basically does three + * things: clear some registers, set up exception tables and + * add more TLB entries for 'larger spaces'(e.g. the boot rom) to + * continue the boot procedure. + + * Once the boot rom is mapped by TLB entries we can proceed + * with normal startup. + * + */ + + .section .bootpg,"ax" + .globl _start_e500 + +_start_e500: + mfspr r0, PVR + lis r1, PVR_85xx_REV1@h + ori r1, r1, PVR_85xx_REV1@l + cmpw r0, r1 + bne 1f + + /* Semi-bogus errata fixup for Rev 1 */ + li r0,0x2000 + mtspr 977,r0 + + /* + * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then + * write it back immediately to fixup a Rev 1 bug (Errata CPU4) + * for this initial TLB1 entry 0, otherwise the TLB1 entry 0 + * will be invalidated (incorrectly). + */ + lis r2,0x1000 + mtspr MAS0,r2 + tlbre + tlbwe + isync + +1: + /* + * Clear and set up some registers. + * Note: Some registers need strict synchronization by + * sync/mbar/msync/isync when being "mtspr". + * BookE: isync before PID,tlbivax,tlbwe + * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe + * E500: msync,isync before L1CSR0 + * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1, + * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2], + * SPEFCSR + */ + + /* invalidate d-cache */ + mfspr r0,L1CSR0 + ori r0,r0,0x0002 + msync + isync + mtspr L1CSR0,r0 + isync + + /* disable d-cache */ + li r0,0x0 + mtspr L1CSR0,r0 + + /* invalidate i-cache */ + mfspr r0,L1CSR1 + ori r0,r0,0x0002 + mtspr L1CSR1,r0 + isync + + /* disable i-cache */ + li r0,0x0 + mtspr L1CSR1,r0 + isync + + /* clear registers */ + li r0,0 + mtspr SRR0,r0 + mtspr SRR1,r0 + mtspr CSRR0,r0 + mtspr CSRR1,r0 + mtspr MCSRR0,r0 + mtspr MCSRR1,r0 + + mtspr ESR,r0 + mtspr MCSR,r0 + mtspr DEAR,r0 + + /* not needed and conflicts with some debuggers */ + /* mtspr DBCR0,r0 */ + mtspr DBCR1,r0 + mtspr DBCR2,r0 + /* not needed and conflicts with some debuggers */ + /* mtspr IAC1,r0 */ + /* mtspr IAC2,r0 */ + mtspr DAC1,r0 + mtspr DAC2,r0 + + mfspr r1,DBSR + mtspr DBSR,r1 /* Clear all valid bits */ + + mtspr PID0,r0 + mtspr PID1,r0 + mtspr PID2,r0 + mtspr TCR,r0 + + mtspr BUCSR,r0 /* disable branch prediction */ + mtspr MAS4,r0 + mtspr MAS6,r0 +#if defined(CONFIG_ENABLE_36BIT_PHYS) + mtspr MAS7,r0 +#endif + isync + + /* Setup interrupt vectors */ + lis r1,TEXT_BASE@h + mtspr IVPR, r1 + + li r1,0x0100 + mtspr IVOR0,r1 /* 0: Critical input */ + li r1,0x0200 + mtspr IVOR1,r1 /* 1: Machine check */ + li r1,0x0300 + mtspr IVOR2,r1 /* 2: Data storage */ + li r1,0x0400 + mtspr IVOR3,r1 /* 3: Instruction storage */ + li r1,0x0500 + mtspr IVOR4,r1 /* 4: External interrupt */ + li r1,0x0600 + mtspr IVOR5,r1 /* 5: Alignment */ + li r1,0x0700 + mtspr IVOR6,r1 /* 6: Program check */ + li r1,0x0800 + mtspr IVOR7,r1 /* 7: floating point unavailable */ + li r1,0x0900 + mtspr IVOR8,r1 /* 8: System call */ + /* 9: Auxiliary processor unavailable(unsupported) */ + li r1,0x0a00 + mtspr IVOR10,r1 /* 10: Decrementer */ + li r1,0x0b00 + mtspr IVOR11,r1 /* 11: Interval timer */ + li r1,0x0c00 + mtspr IVOR12,r1 /* 12: Watchdog timer */ + li r1,0x0d00 + mtspr IVOR13,r1 /* 13: Data TLB error */ + li r1,0x0e00 + mtspr IVOR14,r1 /* 14: Instruction TLB error */ + li r1,0x0f00 + mtspr IVOR15,r1 /* 15: Debug */ + + /* + * Invalidate MMU L1/L2 + * + * Note: There is a fixup earlier for Errata CPU4 on + * Rev 1 parts that must precede this MMU invalidation. + */ + li r2, 0x001e + mtspr MMUCSR0, r2 + isync + + /* + * Invalidate all TLB0 entries. + */ + li r3,4 + li r4,0 + tlbivax r4,r3 + /* + * To avoid REV1 Errata CPU6 issues, make sure + * the instruction following tlbivax is not a store. + */ + + /* + * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. + * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB + * region before we can access any CCSR registers such as L2 + * registers, Local Access Registers,etc. We will also re-allocate + * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup. + * + * Please refer to board-specif directory for TLB1 entry configuration. + * (e.g. board//init.S) + * + */ + bl tlb1_entry + mr r5,r0 + li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */ + mtctr r1 + lwzu r4,0(r5) /* how many TLB1 entries we actually use */ + +0: cmpwi r4,0 + beq 1f + lwzu r0,4(r5) + lwzu r1,4(r5) + lwzu r2,4(r5) + lwzu r3,4(r5) + mtspr MAS0,r0 + mtspr MAS1,r1 + mtspr MAS2,r2 + mtspr MAS3,r3 + isync + msync + tlbwe + isync + addi r4,r4,-1 + bdnz 0b + +1: +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* Special sequence needed to update CCSRBAR itself */ + lis r4, CFG_CCSRBAR_DEFAULT@h + ori r4, r4, CFG_CCSRBAR_DEFAULT@l + + lis r5, CFG_CCSRBAR@h + ori r5, r5, CFG_CCSRBAR@l + srwi r6,r5,12 + stw r6, 0(r4) + isync + + lis r5, 0xffff + ori r5,r5,0xf000 + lwz r5, 0(r5) + isync + + lis r3, CFG_CCSRBAR@h + lwz r5, CFG_CCSRBAR@l(r3) + isync +#endif + + + /* set up local access windows, defined at board//init.S */ + lis r7,CFG_CCSRBAR@h + ori r7,r7,CFG_CCSRBAR@l + + bl law_entry + mr r6,r0 + li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */ + mtctr r1 + lwzu r5,0(r6) /* how many windows we actually use */ + + li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ + li r1,0x0c30 + +0: cmpwi r5,0 + beq 1f + lwzu r4,4(r6) + lwzu r3,4(r6) + stwx r4,r7,r2 + stwx r3,r7,r1 + addi r5,r5,-1 + addi r2,r2,0x0020 + addi r1,r1,0x0020 + bdnz 0b + + /* Jump out the last 4K page and continue to 'normal' start */ +1: bl 3f + b _start + +3: li r0,0 + mtspr SRR1,r0 /* Keep things disabled for now */ + mflr r1 + mtspr SRR0,r1 + rfi + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-BOOT Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +_start: + /* Clear and set up some registers. */ + li r0,0x0000 + lis r1,0xffff + mtspr DEC,r0 /* prevent dec exceptions */ + mttbl r0 /* prevent fit & wdt exceptions */ + mttbu r0 + mtspr TSR,r1 /* clear all timer exception status */ + mtspr TCR,r0 /* disable all */ + mtspr ESR,r0 /* clear exception syndrome register */ + mtspr MCSR,r0 /* machine check syndrome register */ + mtxer r0 /* clear integer exception register */ + lis r1,0x0002 /* set CE bit (Critical Exceptions) */ + ori r1,r1,0x1200 /* set ME/DE bit */ + mtmsr r1 /* change MSR */ + isync + + /* Enable Time Base and Select Time Base Clock */ + lis r0,HID0_EMCP@h /* Enable machine check */ + ori r0,r0,0x4000 /* time base is processor clock */ +#if defined(CONFIG_ENABLE_36BIT_PHYS) + ori r0,r0,0x0080 /* enable MAS7 updates */ +#endif + mtspr HID0,r0 + +#if defined(CONFIG_ADDR_STREAMING) + li r0,0x3000 +#else + li r0,0x1000 +#endif + mtspr HID1,r0 + + /* Enable Branch Prediction */ +#if defined(CONFIG_BTB) + li r0,0x201 /* BBFI = 1, BPEN = 1 */ + mtspr BUCSR,r0 +#endif + +#if defined(CFG_INIT_DBCR) + lis r1,0xffff + ori r1,r1,0xffff + mtspr DBSR,r1 /* Clear all status bits */ + lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */ + ori r0,r0,CFG_INIT_DBCR@l + mtspr DBCR0,r0 +#endif + +/* L1 DCache is used for initial RAM */ + mfspr r2, L1CSR0 + ori r2, r2, 0x0003 + oris r2, r2, 0x0001 + mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */ + isync + + /* Allocate Initial RAM in data cache. + */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + li r2, 512 /* 512*32=16K */ + mtctr r2 + li r0, 0 +1: + dcbz r0, r3 + dcbtls 0,r0, r3 + addi r3, r3, 32 + bdnz 1b + +#ifndef CFG_RAMBOOT + /* Calculate absolute address in FLASH and jump there */ + /*--------------------------------------------------------------*/ + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r3 + blr + +in_flash: +#endif /* CFG_RAMBOOT */ + + /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ + lis r1,CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET@l + + li r0,0 + stwu r0,-4(r1) + stwu r0,-4(r1) /* Terminate call chain */ + + stwu r1,-8(r1) /* Save back chain and move SP */ + lis r0,RESET_VECTOR@h /* Address of reset vector */ + ori r0,r0, RESET_VECTOR@l + stwu r1,-8(r1) /* Save back chain and move SP */ + stw r0,+12(r1) /* Save return addr (underflow vect) */ + + GET_GOT + bl cpu_init_f + bl icache_enable + bl board_init_f + isync + +/* --FIXME-- machine check with MCSRRn and rfmci */ + + .globl _start_of_vectors +_start_of_vectors: +#if 0 +/* Critical input. */ + CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException) +#endif +/* Machine check --FIXME-- Should be MACH_EXCEPTION */ + CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x0300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x0400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException) + +/* Alignment exception. */ + . = 0x0600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x0700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + /* No FPU on MPC85xx. This exception is not supposed to happen. + */ + STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) + + . = 0x0900 +/* + * r0 - SYSCALL number + * r3-... arguments + */ +SystemCall: + addis r11,r0,0 /* get functions table addr */ + ori r11,r11,0 /* Note: this code is patched in trap_init */ + addis r12,r0,0 /* get number of functions */ + ori r12,r12,0 + + cmplw 0, r0, r12 + bge 1f + + rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ + add r11,r11,r0 + lwz r11,0(r11) + + li r20,0xd00-4 /* Get stack pointer */ + lwz r12,0(r20) + subi r12,r12,12 /* Adjust stack pointer */ + li r0,0xc00+_end_back-SystemCall + cmplw 0, r0, r12 /* Check stack overflow */ + bgt 1f + stw r12,0(r20) + + mflr r0 + stw r0,0(r12) + mfspr r0,SRR0 + stw r0,4(r12) + mfspr r0,SRR1 + stw r0,8(r12) + + li r12,0xc00+_back-SystemCall + mtlr r12 + mtspr SRR0,r11 + +1: SYNC + rfi +_back: + + mfmsr r11 /* Disable interrupts */ + li r12,0 + ori r12,r12,MSR_EE + andc r11,r11,r12 + SYNC /* Some chip revs need this... */ + mtmsr r11 + SYNC + + li r12,0xd00-4 /* restore regs */ + lwz r12,0(r12) + + lwz r11,0(r12) + mtlr r11 + lwz r11,4(r12) + mtspr SRR0,r11 + lwz r11,8(r12) + mtspr SRR1,r11 + + addi r12,r12,12 /* Adjust stack pointer */ + li r20,0xd00-4 + stw r12,0(r20) + + SYNC + rfi +_end_back: + + STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) + STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) + STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) + + STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) + STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) + + CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) + + .globl _end_of_vectors +_end_of_vectors: + + + . = 0x2100 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +crit_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr 990,r2 /* SRR2 */ + mtspr 991,r0 /* SRR3 */ + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfci + +/* Cache functions. +*/ +invalidate_icache: + mfspr r0,L1CSR1 + ori r0,r0,0x0002 + mtspr L1CSR1,r0 + isync + blr /* entire I cache */ + +invalidate_dcache: + mfspr r0,L1CSR0 + ori r0,r0,0x0002 + msync + isync + mtspr L1CSR0,r0 + isync + blr + + .globl icache_enable +icache_enable: + mflr r8 + bl invalidate_icache + mtlr r8 + isync + mfspr r4,L1CSR1 + ori r4,r4,0x0001 + oris r4,r4,0x0001 + mtspr L1CSR1,r4 + isync + blr + + .globl icache_disable +icache_disable: + mfspr r0,L1CSR1 + lis r1,0xfffffffe@h + ori r1,r1,0xfffffffe@l + and r0,r0,r1 + mtspr L1CSR1,r0 + isync + blr + + .globl icache_status +icache_status: + mfspr r3,L1CSR1 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl dcache_enable +dcache_enable: + mflr r8 + bl invalidate_dcache + mtlr r8 + isync + mfspr r0,L1CSR0 + ori r0,r0,0x0001 + oris r0,r0,0x0001 + msync + isync + mtspr L1CSR0,r0 + isync + blr + + .globl dcache_disable +dcache_disable: + mfspr r0,L1CSR0 + lis r1,0xfffffffe@h + ori r1,r1,0xfffffffe@l + and r0,r0,r1 + msync + isync + mtspr L1CSR0,r0 + isync + blr + + .globl dcache_status +dcache_status: + mfspr r3,L1CSR0 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl get_pir +get_pir: + mfspr r3, PIR + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + + .globl get_svr +get_svr: + mfspr r3, SVR + blr + + .globl wr_tcr +wr_tcr: + mtspr TCR, r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16 */ +/* Description: Output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16 +out16: + sth r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16r */ +/* Description: Byte reverse and output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16r +out16r: + sthbrx r4,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32r */ +/* Description: Byte reverse and output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32r +out32r: + stwbrx r4,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16 */ +/* Description: Input 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl in16 +in16: + lhz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16r */ +/* Description: Input 16 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in16r +in16r: + lhbrx r3,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0x0000(3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32r */ +/* Description: Input 32 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in32r +in32r: + lwbrx r3,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcSync */ +/* Description: Processor Synchronize */ +/* Input: none. */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcSync +ppcSync: + sync + blr + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Init Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5,GOT(__init_end) + sub r5,r5,r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* the the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + + /* + * Re-point the IVPR at RAM + */ + mtspr IVPR,r10 + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr /* NEVER RETURNS! */ + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Init Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET + bl trap_reloc + li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + lis r7,0x0 + mtspr IVPR, r7 + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr + +#ifdef CFG_INIT_RAM_LOCK +.globl unlock_ram_in_cache +unlock_ram_in_cache: + /* invalidate the INIT_RAM section */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2,512 + mtctr r2 +1: icbi r0, r3 + dcbi r0, r3 + addi r3, r3, 32 + bdnz 1b + sync /* Wait for all icbi to complete on bus */ + isync + blr +#endif diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c new file mode 100644 index 0000000..a87eed2 --- /dev/null +++ b/cpu/mpc85xx/traps.c @@ -0,0 +1,273 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 2003 Motorola + * Modified by Xianghua Xiao(x.xiao@motorola.com) + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler)(struct pt_regs *) = 0; +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* + * End of memory as shown by board info and determined by DDR setup. + */ +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) + + +static __inline__ void set_tsr(unsigned long val) +{ + asm volatile("mtspr 0x150, %0" : : "r" (val)); +} + +static __inline__ unsigned long get_esr(void) +{ + unsigned long val; + asm volatile("mfspr %0, 0x03e" : "=r" (val) :); + return val; +} + +#define ESR_MCI 0x80000000 +#define ESR_PIL 0x08000000 +#define ESR_PPR 0x04000000 +#define ESR_PTR 0x02000000 +#define ESR_DST 0x00800000 +#define ESR_DIZ 0x00400000 +#define ESR_U0F 0x00008000 + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint(struct pt_regs *); +#endif + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ + DECLARE_GLOBAL_DATA_PTR; + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +void +CritcalInputException(struct pt_regs *regs) +{ + panic("Critical Input Exception"); +} + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + printf("Data parity signal\n"); + break; + case (0x80000000>>15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ + long esr_val; + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + show_regs(regs); + + esr_val = get_esr(); + if( esr_val & ESR_PIL ) + printf( "** Illegal Instruction **\n" ); + else if( esr_val & ESR_PPR ) + printf( "** Privileged Instruction **\n" ); + else if( esr_val & ESR_PTR ) + printf( "** Trap Instruction **\n" ); + + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +PITException(struct pt_regs *regs) +{ + /* + * Reset PIT interrupt + */ + set_tsr(0x0c000000); + + /* + * Call timer_interrupt routine in interrupts.c + */ + timer_interrupt(NULL); +} + + +void +UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +void +DebugException(struct pt_regs *regs) +{ + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); +#endif +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int +addr_probe(uint *addr) +{ + return 0; +} diff --git a/cpu/mpc8xx/Makefile b/cpu/mpc8xx/Makefile new file mode 100644 index 0000000..de75fad --- /dev/null +++ b/cpu/mpc8xx/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = start.o kgdb.o +OBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \ + fec.o i2c.o interrupts.o lcd.o scc.o \ + serial.o speed.o spi.o \ + traps.o upatch.o video.o +SOBJS = plprcr_write.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) kgdb.o + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc8xx/bedbug_860.c b/cpu/mpc8xx/bedbug_860.c new file mode 100644 index 0000000..e91a100 --- /dev/null +++ b/cpu/mpc8xx/bedbug_860.c @@ -0,0 +1,316 @@ +/* + * Bedbug Functions specific to the MPC860 chip + */ + +#include +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_8xx) + +#define MAX_BREAK_POINTS 2 + +extern CPU_DEBUG_CTX bug_ctx; + +void bedbug860_init __P((void)); +void bedbug860_do_break __P((cmd_tbl_t*,int,int,char*[])); +void bedbug860_break_isr __P((struct pt_regs*)); +int bedbug860_find_empty __P((void)); +int bedbug860_set __P((int,unsigned long)); +int bedbug860_clear __P((int)); + + +/* ====================================================================== + * Initialize the global bug_ctx structure for the MPC860. Clear all + * of the breakpoints. + * ====================================================================== */ + +void bedbug860_init( void ) +{ + int i; + /* -------------------------------------------------- */ + + bug_ctx.hw_debug_enabled = 0; + bug_ctx.stopped = 0; + bug_ctx.current_bp = 0; + bug_ctx.regs = NULL; + + bug_ctx.do_break = bedbug860_do_break; + bug_ctx.break_isr = bedbug860_break_isr; + bug_ctx.find_empty = bedbug860_find_empty; + bug_ctx.set = bedbug860_set; + bug_ctx.clear = bedbug860_clear; + + for( i = 1; i <= MAX_BREAK_POINTS; ++i ) + (*bug_ctx.clear)( i ); + + puts ("BEDBUG:ready\n"); + return; +} /* bedbug_init_breakpoints */ + + + +/* ====================================================================== + * Set/clear/show one of the hardware breakpoints for the 860. The "off" + * string will disable a specific breakpoint. The "show" string will + * display the current breakpoints. Otherwise an address will set a + * breakpoint at that address. Setting a breakpoint uses the CPU-specific + * set routine which will assign a breakpoint number. + * ====================================================================== */ + +void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc, + char *argv[]) +{ + long addr = 0; /* Address to break at */ + int which_bp; /* Breakpoint number */ + /* -------------------------------------------------- */ + + if (argc < 2) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return; + } + + /* Turn off a breakpoint */ + + if( strcmp( argv[ 1 ], "off" ) == 0 ) + { + if( bug_ctx.hw_debug_enabled == 0 ) + { + printf( "No breakpoints enabled\n" ); + return; + } + + which_bp = simple_strtoul( argv[ 2 ], NULL, 10 ); + + if( bug_ctx.clear ) + (*bug_ctx.clear)( which_bp ); + + printf( "Breakpoint %d removed\n", which_bp ); + return; + } + + /* Show a list of breakpoints */ + + if( strcmp( argv[ 1 ], "show" ) == 0 ) + { + for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp ) + { + + switch( which_bp ) + { + case 1: addr = GET_CMPA(); break; + case 2: addr = GET_CMPB(); break; + case 3: addr = GET_CMPC(); break; + case 4: addr = GET_CMPD(); break; + } + + printf( "Breakpoint [%d]: ", which_bp ); + if( addr == 0 ) + printf( "NOT SET\n" ); + else + disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); + } + return; + } + + /* Set a breakpoint at the address */ + + if( !isdigit( argv[ 1 ][ 0 ])) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return; + } + + addr = simple_strtoul( argv[ 1 ], NULL, 16 ) & 0xfffffffc; + + if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 ) + { + printf( "Breakpoint [%d]: ", which_bp ); + disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); + } + + return; +} /* bedbug860_do_break */ + + + +/* ====================================================================== + * Handle a breakpoint. First determine which breakpoint was hit by + * looking at the DeBug Status Register (DBSR), clear the breakpoint + * and enter a mini main loop. Stay in the loop until the stopped flag + * in the debug context is cleared. + * ====================================================================== */ + +void bedbug860_break_isr( struct pt_regs *regs ) +{ + unsigned long addr; /* Address stopped at */ + unsigned long cause; /* Address stopped at */ + /* -------------------------------------------------- */ + + cause = GET_ICR(); + + if( !(cause & 0x00000004)) { + printf( "Not an instruction breakpoint (ICR 0x%08lx)\n", cause ); + return; + } + + addr = regs->nip; + + if( addr == GET_CMPA() ) + { + bug_ctx.current_bp = 1; + } + else if( addr == GET_CMPB() ) + { + bug_ctx.current_bp = 2; + } + else if( addr == GET_CMPC() ) + { + bug_ctx.current_bp = 3; + } + else if( addr == GET_CMPD() ) + { + bug_ctx.current_bp = 4; + } + + bedbug_main_loop( addr, regs ); + return; +} /* bedbug860_break_isr */ + + + +/* ====================================================================== + * Look through all of the hardware breakpoints available to see if one + * is unused. + * ====================================================================== */ + +int bedbug860_find_empty( void ) +{ + /* -------------------------------------------------- */ + + if( GET_CMPA() == 0 ) + return 1; + + if( GET_CMPB() == 0 ) + return 2; + + if( GET_CMPC() == 0 ) + return 3; + + if( GET_CMPD() == 0 ) + return 4; + + return 0; +} /* bedbug860_find_empty */ + + + +/* ====================================================================== + * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint + * number, otherwise reassign the given breakpoint. If hardware debugging + * is not enabled, then turn it on via the MSR and DBCR0. Set the break + * address in the appropriate IACx register and enable proper address + * beakpoint in DBCR0. + * ====================================================================== */ + +int bedbug860_set( int which_bp, unsigned long addr ) +{ + /* -------------------------------------------------- */ + + /* Only look if which_bp == 0, else use which_bp */ + if(( bug_ctx.find_empty ) && ( !which_bp ) && + ( which_bp = (*bug_ctx.find_empty)()) == 0 ) + { + printf( "All breakpoints in use\n" ); + return 0; + } + + if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) + { + printf( "Invalid break point # %d\n", which_bp ); + return 0; + } + + if( ! bug_ctx.hw_debug_enabled ) + { + bug_ctx.hw_debug_enabled = 1; + SET_DER( GET_DER() | 0x00000004 ); + } + + switch( which_bp ) + { + case 1: + SET_CMPA( addr ); + SET_ICTRL( GET_ICTRL() | 0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */ + break; + + case 2: + SET_CMPB( addr ); + SET_ICTRL( GET_ICTRL() | 0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */ + break; + + case 3: + SET_CMPC( addr ); + SET_ICTRL( GET_ICTRL() | 0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */ + break; + + case 4: + SET_CMPD( addr ); + SET_ICTRL( GET_ICTRL() | 0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */ + break; + } + + return which_bp; +} /* bedbug860_set */ + + + +/* ====================================================================== + * Disable a specific breakoint by setting the appropriate IACx register + * to zero and claring the instruction address breakpoint in DBCR0. + * ====================================================================== */ + +int bedbug860_clear( int which_bp ) +{ + /* -------------------------------------------------- */ + + if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) + { + printf( "Invalid break point # (%d)\n", which_bp ); + return -1; + } + + switch( which_bp ) + { + case 1: + SET_CMPA( 0 ); + SET_ICTRL( GET_ICTRL() & ~0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */ + break; + + case 2: + SET_CMPB( 0 ); + SET_ICTRL( GET_ICTRL() & ~0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */ + break; + + case 3: + SET_CMPC( 0 ); + SET_ICTRL( GET_ICTRL() & ~0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */ + break; + + case 4: + SET_CMPD( 0 ); + SET_ICTRL( GET_ICTRL() & ~0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */ + break; + } + + return 0; +} /* bedbug860_clear */ + + +/* ====================================================================== */ +#endif diff --git a/cpu/mpc8xx/commproc.c b/cpu/mpc8xx/commproc.c new file mode 100644 index 0000000..75740e0 --- /dev/null +++ b/cpu/mpc8xx/commproc.c @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CFG_ALLOC_DPRAM + +int dpram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Reclaim the DP memory for our use. */ + gd->dp_alloc_base = CPM_DATAONLY_BASE; + gd->dp_alloc_top = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE; + + return (0); +} + +/* Allocate some memory from the dual ported ram. We may want to + * enforce alignment restrictions, but right now everyone is a good + * citizen. + */ +uint dpram_alloc (uint size) +{ + DECLARE_GLOBAL_DATA_PTR; + uint addr = gd->dp_alloc_base; + + if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) + return (CPM_DP_NOSPACE); + + gd->dp_alloc_base += size; + + return addr; +} + +uint dpram_base (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + return gd->dp_alloc_base; +} + +/* Allocate some memory from the dual ported ram. We may want to + * enforce alignment restrictions, but right now everyone is a good + * citizen. + */ +uint dpram_alloc_align (uint size, uint align) +{ + DECLARE_GLOBAL_DATA_PTR; + + uint addr, mask = align - 1; + + addr = (gd->dp_alloc_base + mask) & ~mask; + + if ((addr + size) >= gd->dp_alloc_top) + return (CPM_DP_NOSPACE); + + gd->dp_alloc_base = addr + size; + + return addr; +} + +uint dpram_base_align (uint align) +{ + DECLARE_GLOBAL_DATA_PTR; + + uint mask = align - 1; + + return (gd->dp_alloc_base + mask) & ~mask; +} +#endif /* CFG_ALLOC_DPRAM */ + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + +void post_word_store (ulong a) +{ + volatile void *save_addr = + ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR; + + *(volatile ulong *) save_addr = a; +} + +ulong post_word_load (void) +{ + volatile void *save_addr = + ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR; + + return *(volatile ulong *) save_addr; +} + +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ + +#ifdef CONFIG_BOOTCOUNT_LIMIT + +void bootcount_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + + CPM_BOOTCOUNT_ADDR ); + + save_addr[0] = a; + save_addr[1] = BOOTCOUNT_MAGIC; +} + +ulong bootcount_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + + CPM_BOOTCOUNT_ADDR ); + + if (save_addr[1] != BOOTCOUNT_MAGIC) + return 0; + else + return save_addr[0]; +} + +#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk new file mode 100644 index 0000000..bfa6625 --- /dev/null +++ b/cpu/mpc8xx/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing + +PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -ffixed-r29 -mstring -mcpu=860 -msoft-float diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c new file mode 100644 index 0000000..4a32986 --- /dev/null +++ b/cpu/mpc8xx/cpu.c @@ -0,0 +1,631 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * m8xx.c + * + * CPU specific code + * + * written or collected and sometimes rewritten by + * Magnus Damm + * + * minor modifications by + * Wolfgang Denk + */ + +#include +#include +#include +#include +#include + +static char *cpu_warning = "\n " \ + "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***"; + +#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \ + !defined(CONFIG_MPC862)) + +static int check_CPU (long clock, uint pvr, uint immr) +{ + char *id_str = +# if defined(CONFIG_MPC855) + "PC855"; +# elif defined(CONFIG_MPC860P) + "PC860P"; +# else + NULL; +# endif + volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); + uint k, m; + char buf[32]; + char pre = 'X'; + char *mid = "xx"; + char *suf; + + /* the highest 16 bits should be 0x0050 for a 860 */ + + if ((pvr >> 16) != 0x0050) + return -1; + + k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); + m = 0; + + /* + * Some boards use sockets so different CPUs can be used. + * We have to check chip version in run time. + */ + switch (k) { + case 0x00020001: pre = 'P'; suf = ""; break; + case 0x00030001: suf = ""; break; + case 0x00120003: suf = "A"; break; + case 0x00130003: suf = "A3"; break; + + case 0x00200004: suf = "B"; break; + + case 0x00300004: suf = "C"; break; + case 0x00310004: suf = "C1"; m = 1; break; + + case 0x00200064: mid = "SR"; suf = "B"; break; + case 0x00300065: mid = "SR"; suf = "C"; break; + case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; + case 0x05010000: suf = "D3"; m = 1; break; + case 0x05020000: suf = "D4"; m = 1; break; + /* this value is not documented anywhere */ + case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; + /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ + case 0x08000003: pre = 'M'; suf = ""; m = 1; + if (id_str == NULL) + id_str = +# if defined(CONFIG_MPC852T) + "PC852T"; +# elif defined(CONFIG_MPC859T) + "PC859T"; +# elif defined(CONFIG_MPC859DSL) + "PC859DSL"; +# elif defined(CONFIG_MPC866T) + "PC866T"; +# else + "PC866x"; /* Unknown chip from MPC866 family */ +# endif + break; + case 0x09000000: pre = 'M'; mid = suf = ""; m = 1; + if (id_str == NULL) + id_str = "PC885"; /* 870/875/880/885 */ + break; + + default: suf = NULL; break; + } + + if (id_str == NULL) + id_str = "PC86x"; /* Unknown 86x chip */ + if (suf) + printf ("%c%s%sZPnn%s", pre, id_str, mid, suf); + else + printf ("unknown M%s (0x%08x)", id_str, k); + + +#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX) + printf (" at %s MHz [%d.%d...%d.%d MHz]\n ", + strmhz (buf, clock), + CFG_8xx_CPUCLK_MIN / 1000000, + ((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000, + CFG_8xx_CPUCLK_MAX / 1000000, + ((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000 + ); +#else + printf (" at %s MHz: ", strmhz (buf, clock)); +#endif + printf ("%u kB I-Cache %u kB D-Cache", + checkicache () >> 10, + checkdcache () >> 10 + ); + + /* do we have a FEC (860T/P or 852/859/866/885)? */ + + immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; + if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { + printf (" FEC present"); + } + + if (!m) { + puts (cpu_warning); + } + + putc ('\n'); + +#ifdef DEBUG + if(clock != measure_gclk()) { + printf ("clock %ldHz != %dHz\n", clock, measure_gclk()); + } +#endif + + return 0; +} + +#elif defined(CONFIG_MPC862) + +static int check_CPU (long clock, uint pvr, uint immr) +{ + volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); + uint k, m; + char buf[32]; + char pre = 'X'; + char *mid = "xx"; + char *suf; + + /* the highest 16 bits should be 0x0050 for a 8xx */ + + if ((pvr >> 16) != 0x0050) + return -1; + + k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); + m = 0; + + switch (k) { + + /* this value is not documented anywhere */ + case 0x06000000: mid = "P"; suf = "0"; break; + case 0x06010001: mid = "P"; suf = "A"; m = 1; break; + case 0x07000003: mid = "P"; suf = "B"; m = 1; break; + default: suf = NULL; break; + } + +#ifndef CONFIG_MPC857 + if (suf) + printf ("%cPC862%sZPnn%s", pre, mid, suf); + else + printf ("unknown MPC862 (0x%08x)", k); +#else + if (suf) + printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */ + else + printf ("unknown MPC857 (0x%08x)", k); +#endif + + printf (" at %s MHz:", strmhz (buf, clock)); + + printf (" %u kB I-Cache", checkicache () >> 10); + printf (" %u kB D-Cache", checkdcache () >> 10); + + /* lets check and see if we're running on a 862T (or P?) */ + + immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; + if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { + printf (" FEC present"); + } + + if (!m) { + puts (cpu_warning); + } + + putc ('\n'); + + return 0; +} + +#elif defined(CONFIG_MPC823) + +static int check_CPU (long clock, uint pvr, uint immr) +{ + volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); + uint k, m; + char buf[32]; + char *suf; + + /* the highest 16 bits should be 0x0050 for a 8xx */ + + if ((pvr >> 16) != 0x0050) + return -1; + + k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); + m = 0; + + switch (k) { + /* MPC823 */ + case 0x20000000: suf = "0"; break; + case 0x20010000: suf = "0.1"; break; + case 0x20020000: suf = "Z2/3"; break; + case 0x20020001: suf = "Z3"; break; + case 0x21000000: suf = "A"; break; + case 0x21010000: suf = "B"; m = 1; break; + case 0x21010001: suf = "B2"; m = 1; break; + /* MPC823E */ + case 0x24010000: suf = NULL; + puts ("PPC823EZTnnB2"); + m = 1; + break; + default: + suf = NULL; + printf ("unknown MPC823 (0x%08x)", k); + break; + } + if (suf) + printf ("PPC823ZTnn%s", suf); + + printf (" at %s MHz:", strmhz (buf, clock)); + + printf (" %u kB I-Cache", checkicache () >> 10); + printf (" %u kB D-Cache", checkdcache () >> 10); + + /* lets check and see if we're running on a 860T (or P?) */ + + immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; + if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { + puts (" FEC present"); + } + + if (!m) { + puts (cpu_warning); + } + + putc ('\n'); + + return 0; +} + +#elif defined(CONFIG_MPC850) + +static int check_CPU (long clock, uint pvr, uint immr) +{ + volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); + uint k, m; + char buf[32]; + + /* the highest 16 bits should be 0x0050 for a 8xx */ + + if ((pvr >> 16) != 0x0050) + return -1; + + k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); + m = 0; + + switch (k) { + case 0x20020001: + printf ("XPC850xxZT"); + break; + case 0x21000065: + printf ("XPC850xxZTA"); + break; + case 0x21010067: + printf ("XPC850xxZTB"); + m = 1; + break; + case 0x21020068: + printf ("XPC850xxZTC"); + m = 1; + break; + default: + printf ("unknown MPC850 (0x%08x)", k); + } + printf (" at %s MHz:", strmhz (buf, clock)); + + printf (" %u kB I-Cache", checkicache () >> 10); + printf (" %u kB D-Cache", checkdcache () >> 10); + + /* lets check and see if we're running on a 850T (or P?) */ + + immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; + if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { + printf (" FEC present"); + } + + if (!m) { + puts (cpu_warning); + } + + putc ('\n'); + + return 0; +} +#else +#error CPU undefined +#endif +/* ------------------------------------------------------------------------- */ + +int checkcpu (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong clock = gd->cpu_clk; + uint immr = get_immr (0); /* Return full IMMR contents */ + uint pvr = get_pvr (); + + puts ("CPU: "); + + /* 850 has PARTNUM 20 */ + /* 801 has PARTNUM 10 */ + return check_CPU (clock, pvr, immr); +} + +/* ------------------------------------------------------------------------- */ +/* L1 i-cache */ +/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ +/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */ + +int checkicache (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + u32 cacheon = rd_ic_cst () & IDC_ENABLED; + +#ifdef CONFIG_IP86x + u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ +#else + u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ +#endif + u32 m; + u32 lines = -1; + + wr_ic_cst (IDC_UNALL); + wr_ic_cst (IDC_INVALL); + wr_ic_cst (IDC_DISABLE); + __asm__ volatile ("isync"); + + while (!((m = rd_ic_cst ()) & IDC_CERR2)) { + wr_ic_adr (k); + wr_ic_cst (IDC_LDLCK); + __asm__ volatile ("isync"); + + lines++; + k += 0x10; /* the number of bytes in a cacheline */ + } + + wr_ic_cst (IDC_UNALL); + wr_ic_cst (IDC_INVALL); + + if (cacheon) + wr_ic_cst (IDC_ENABLE); + else + wr_ic_cst (IDC_DISABLE); + + __asm__ volatile ("isync"); + + return lines << 4; +}; + +/* ------------------------------------------------------------------------- */ +/* L1 d-cache */ +/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ +/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */ +/* call with cache disabled */ + +int checkdcache (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + u32 cacheon = rd_dc_cst () & IDC_ENABLED; + +#ifdef CONFIG_IP86x + u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ +#else + u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ +#endif + u32 m; + u32 lines = -1; + + wr_dc_cst (IDC_UNALL); + wr_dc_cst (IDC_INVALL); + wr_dc_cst (IDC_DISABLE); + + while (!((m = rd_dc_cst ()) & IDC_CERR2)) { + wr_dc_adr (k); + wr_dc_cst (IDC_LDLCK); + lines++; + k += 0x10; /* the number of bytes in a cacheline */ + } + + wr_dc_cst (IDC_UNALL); + wr_dc_cst (IDC_INVALL); + + if (cacheon) + wr_dc_cst (IDC_ENABLE); + else + wr_dc_cst (IDC_DISABLE); + + return lines << 4; +}; + +/* ------------------------------------------------------------------------- */ + +void upmconfig (uint upm, uint * table, uint size) +{ + uint i; + uint addr = 0; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + for (i = 0; i < size; i++) { + memctl->memc_mdr = table[i]; /* (16-15) */ + memctl->memc_mcr = addr | upm; /* (16-16) */ + addr++; + } +} + +/* ------------------------------------------------------------------------- */ + +#ifndef CONFIG_LWMON + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong msr, addr; + + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ + + /* Interrupts and MMU off */ + __asm__ volatile ("mtspr 81, 0"); + __asm__ volatile ("mfmsr %0":"=r" (msr)); + + msr &= ~0x1030; + __asm__ volatile ("mtmsr %0"::"r" (msr)); + + /* + * Trying to execute the next instruction at a non-existing address + * should cause a machine check, resulting in reset + */ +#ifdef CFG_RESET_ADDRESS + addr = CFG_RESET_ADDRESS; +#else + /* + * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE + * - sizeof (ulong) is usually a valid address. Better pick an address + * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. + * "(ulong)-1" used to be a good choice for many systems... + */ + addr = CFG_MONITOR_BASE - sizeof (ulong); +#endif + ((void (*)(void)) addr) (); + return 1; +} + +#else /* CONFIG_LWMON */ + +/* + * On the LWMON board, the MCLR reset input of the PIC's on the board + * uses a 47K/1n RC combination which has a 47us time constant. The + * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us + * and thus too short to reset the external hardware. So we use the + * watchdog to reset the board. + */ +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + /* prevent triggering the watchdog */ + disable_interrupts (); + + /* make sure the watchdog is running */ + reset_8xx_watchdog ((immap_t *) CFG_IMMR); + + /* wait for watchdog reset */ + while (1) {}; + + /* NOTREACHED */ + return 1; +} + +#endif /* CONFIG_LWMON */ + +/* ------------------------------------------------------------------------- */ + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + * + * See sections 14.2 and 14.6 of the User's Manual + */ +unsigned long get_tbclk (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uint immr = get_immr (0); /* Return full IMMR contents */ + volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000); + ulong oscclk, factor, pll; + + if (immap->im_clkrst.car_sccr & SCCR_TBS) { + return (gd->cpu_clk / 16); + } + + pll = immap->im_clkrst.car_plprcr; + +#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) + + /* + * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication + * factor is calculated as follows: + * + * MFN + * MFI + ------- + * MFD + 1 + * factor = ----------------- + * (PDF + 1) * 2^S + * + * For older chips, it's just MF field of PLPRCR plus one. + */ + if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ + factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ + (PLPRCR_val(PDF)+1) / (1<cpu_clk / factor; + + if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { + return (oscclk / 4); + } + return (oscclk / 16); +} + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + int re_enable = disable_interrupts (); + + reset_8xx_watchdog ((immap_t *) CFG_IMMR); + if (re_enable) + enable_interrupts (); +} +#endif /* CONFIG_WATCHDOG */ + +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON) + +void reset_8xx_watchdog (volatile immap_t * immr) +{ +# if defined(CONFIG_LWMON) + /* + * The LWMON board uses a MAX6301 Watchdog + * with the trigger pin connected to port PA.7 + * + * (The old board version used a MAX706TESA Watchdog, which + * had to be handled exactly the same.) + */ +# define WATCHDOG_BIT 0x0100 + immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ + immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ + immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ + + immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ +# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) + /* + * The KUP4 boards uses a TPS3705 Watchdog + * with the trigger pin connected to port PA.5 + */ +# define WATCHDOG_BIT 0x0400 + immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ + immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ + immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ + + immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ +# else + /* + * All other boards use the MPC8xx Internal Watchdog + */ + immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ + immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ +# endif /* CONFIG_LWMON */ +} + +#endif /* CONFIG_WATCHDOG */ + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c new file mode 100644 index 0000000..b2c59c6 --- /dev/null +++ b/cpu/mpc8xx/cpu_init.c @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) +void cpm_load_patch (volatile immap_t * immr); +#endif + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f (volatile immap_t * immr) +{ +#ifndef CONFIG_MBX + volatile memctl8xx_t *memctl = &immr->im_memctl; +# ifdef CFG_PLPRCR + ulong mfmask; +# endif +#endif + ulong reg; + + /* SYPCR - contains watchdog control (11-9) */ + + immr->im_siu_conf.sc_sypcr = CFG_SYPCR; + +#if defined(CONFIG_WATCHDOG) + reset_8xx_watchdog (immr); +#endif /* CONFIG_WATCHDOG */ + + /* SIUMCR - contains debug pin configuration (11-6) */ +#ifndef CONFIG_SVM_SC8xx + immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR; +#else + immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; +#endif + /* initialize timebase status and control register (11-26) */ + /* unlock TBSCRK */ + + immr->im_sitk.sitk_tbscrk = KAPWR_KEY; + immr->im_sit.sit_tbscr = CFG_TBSCR; + + /* initialize the PIT (11-31) */ + + immr->im_sitk.sitk_piscrk = KAPWR_KEY; + immr->im_sit.sit_piscr = CFG_PISCR; + + /* System integration timers. Don't change EBDF! (15-27) */ + + immr->im_clkrstk.cark_sccrk = KAPWR_KEY; + reg = immr->im_clkrst.car_sccr; + reg &= SCCR_MASK; + reg |= CFG_SCCR; + immr->im_clkrst.car_sccr = reg; + + /* PLL (CPU clock) settings (15-30) */ + + immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; + +#ifndef CONFIG_MBX /* MBX board does things different */ + + /* If CFG_PLPRCR (set in the various *_config.h files) tries to + * set the MF field, then just copy CFG_PLPRCR over car_plprcr, + * otherwise OR in CFG_PLPRCR so we do not change the current MF + * field value. + * + * For newer (starting MPC866) chips PLPRCR layout is different. + */ +#ifdef CFG_PLPRCR + if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) + mfmask = PLPRCR_MFACT_MSK; + else + mfmask = PLPRCR_MF_MSK; + + if ((CFG_PLPRCR & mfmask) != 0) + reg = CFG_PLPRCR; /* reset control bits */ + else { + reg = immr->im_clkrst.car_plprcr; + reg &= mfmask; /* isolate MF-related fields */ + reg |= CFG_PLPRCR; /* reset control bits */ + } + immr->im_clkrst.car_plprcr = reg; +#endif + + /* + * Memory Controller: + */ + + /* perform BR0 reset that MPC850 Rev. A can't guarantee */ + reg = memctl->memc_br0; + reg &= BR_PS_MSK; /* Clear everything except Port Size bits */ + reg |= BR_V; /* then add just the "Bank Valid" bit */ + memctl->memc_br0 = reg; + + /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at + * preliminary addresses - these have to be modified later + * when FLASH size has been determined + * + * Depending on the size of the memory region defined by + * CFG_OR0_REMAP some boards (wide address mask) allow to map the + * CFG_MONITOR_BASE, while others (narrower address mask) can't + * map CFG_MONITOR_BASE. + * + * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is + * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000. + * + * If BR0 wasn't loaded with address base 0xff000000, then BR0's + * base address remains as 0x00000000. However, the address mask + * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped + * into the Bank0. + * + * This is why CONFIG_IVMS8 and similar boards must load BR0 with + * CFG_BR0_PRELIM in advance. + * + * [Thanks to Michael Liao for this explanation. + * I owe him a free beer. - wd] + */ + +#if defined(CONFIG_GTH) || \ + defined(CONFIG_HERMES) || \ + defined(CONFIG_ICU862) || \ + defined(CONFIG_IP860) || \ + defined(CONFIG_IVML24) || \ + defined(CONFIG_IVMS8) || \ + defined(CONFIG_LWMON) || \ + defined(CONFIG_MHPC) || \ + defined(CONFIG_PCU_E) || \ + defined(CONFIG_R360MPI) || \ + defined(CONFIG_RMU) || \ + defined(CONFIG_RPXCLASSIC) || \ + defined(CONFIG_RPXLITE) || \ + defined(CONFIG_SPD823TS) + + memctl->memc_br0 = CFG_BR0_PRELIM; +#endif + +#if defined(CFG_OR0_REMAP) + memctl->memc_or0 = CFG_OR0_REMAP; +#endif +#if defined(CFG_OR1_REMAP) + memctl->memc_or1 = CFG_OR1_REMAP; +#endif +#if defined(CFG_OR5_REMAP) + memctl->memc_or5 = CFG_OR5_REMAP; +#endif + + /* now restrict to preliminary range */ + memctl->memc_br0 = CFG_BR0_PRELIM; + memctl->memc_or0 = CFG_OR0_PRELIM; + +#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; +#endif + +#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */ + memctl->memc_br0 = 0; +#endif + +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; +#endif + +#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; +#endif + +#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) + memctl->memc_or4 = CFG_OR4_PRELIM; + memctl->memc_br4 = CFG_BR4_PRELIM; +#endif + +#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) + memctl->memc_or5 = CFG_OR5_PRELIM; + memctl->memc_br5 = CFG_BR5_PRELIM; +#endif + +#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) + memctl->memc_or6 = CFG_OR6_PRELIM; + memctl->memc_br6 = CFG_BR6_PRELIM; +#endif + +#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) + memctl->memc_or7 = CFG_OR7_PRELIM; + memctl->memc_br7 = CFG_BR7_PRELIM; +#endif + +#endif /* ! CONFIG_MBX */ + + /* + * Reset CPM + */ + immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG; + do { /* Spin until command processed */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + +#ifdef CONFIG_MBX + /* + * on the MBX, things are a little bit different: + * - we need to read the VPD to get board information + * - the plprcr is set up dynamically + * - the memory controller is set up dynamically + */ + mbx_init (); +#endif /* CONFIG_MBX */ + +#ifdef CONFIG_RPXCLASSIC + rpxclassic_init (); +#endif + +#if defined(CONFIG_RPXLITE) && defined(CFG_ENV_IS_IN_NVRAM) + rpxlite_init (); +#endif + +#ifdef CFG_RCCR /* must be done before cpm_load_patch() */ + /* write config value */ + immr->im_cpm.cp_rccr = CFG_RCCR; +#endif + +#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) + cpm_load_patch (immr); /* load mpc8xx microcode patch */ +#endif +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r (void) +{ +#if defined(CFG_RTCSC) || defined(CFG_RMDS) + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd = gd->bd; + volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base); +#endif + +#ifdef CFG_RTCSC + /* Unlock RTSC register */ + immr->im_sitk.sitk_rtcsck = KAPWR_KEY; + /* write config value */ + immr->im_sit.sit_rtcsc = CFG_RTCSC; +#endif + +#ifdef CFG_RMDS + /* write config value */ + immr->im_cpm.cp_rmds = CFG_RMDS; +#endif + return (0); +} diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c new file mode 100644 index 0000000..d2f5d88 --- /dev/null +++ b/cpu/mpc8xx/fec.c @@ -0,0 +1,1020 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#undef ET_DEBUG + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && \ + (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) + +/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ +#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2) +#define CONFIG_ETHER_ON_FEC1 1 +#endif + +/* define WANT_MII when MII support is required */ +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) +#define WANT_MII +#else +#undef WANT_MII +#endif + +#if defined(WANT_MII) +#include + +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#endif + +#if defined(CONFIG_RMII) && !defined(WANT_MII) +#error RMII support is unusable without a working PHY. +#endif + +#ifdef CFG_DISCOVER_PHY +static int mii_discover_phy(struct eth_device *dev); +#endif + +int fec8xx_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +int fec8xx_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); + +static struct ether_fcc_info_s +{ + int ether_index; + int fecp_offset; + int phy_addr; + int actual_phy_addr; + int initialized; +} + ether_fcc_info[] = { +#if defined(CONFIG_ETHER_ON_FEC1) + { + 0, + offsetof(immap_t, im_cpm.cp_fec1), +#if defined(CONFIG_FEC1_PHY) + CONFIG_FEC1_PHY, +#else + -1, /* discover */ +#endif + -1, + 0, + + }, +#endif +#if defined(CONFIG_ETHER_ON_FEC2) + { + 1, + offsetof(immap_t, im_cpm.cp_fec2), +#if defined(CONFIG_FEC2_PHY) + CONFIG_FEC2_PHY, +#else + -1, +#endif + -1, + 0, + }, +#endif +}; + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +#define TOUT_LOOP 100 + +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 + +#ifdef __GNUC__ +static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8))); +#else +#error txbuf must be aligned. +#endif + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * FEC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +typedef volatile struct CommonBufferDescriptor { + cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ + cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ +} RTXBD; + +static RTXBD *rtx = NULL; + +static int fec_send(struct eth_device* dev, volatile void *packet, int length); +static int fec_recv(struct eth_device* dev); +static int fec_init(struct eth_device* dev, bd_t * bd); +static void fec_halt(struct eth_device* dev); + +int fec_initialize(bd_t *bis) +{ + struct eth_device* dev; + struct ether_fcc_info_s *efis; + int i; + + for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) { + + dev = malloc(sizeof(*dev)); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + /* for FEC1 make sure that the name of the interface is the same + as the old one for compatibility reasons */ + if (i == 0) { + sprintf (dev->name, "FEC ETHERNET"); + } else { + sprintf (dev->name, "FEC%d ETHERNET", + ether_fcc_info[i].ether_index + 1); + } + + efis = ðer_fcc_info[i]; + + /* + * reset actual phy addr + */ + efis->actual_phy_addr = -1; + + dev->priv = efis; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + eth_register(dev); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register(dev->name, + fec8xx_miiphy_read, fec8xx_miiphy_write); +#endif + } + return 1; +} + +static int fec_send(struct eth_device* dev, volatile void *packet, int length) +{ + int j, rc; + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + + /* section 16.9.23.3 + * Wait for ready + */ + j = 0; + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) { + printf("TX not ready\n"); + } + + rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; + __asm__ ("eieio"); + + /* Activate transmit Buffer Descriptor polling */ + fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ + + j = 0; + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) { + printf("TX timeout\n"); + } +#ifdef ET_DEBUG + printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", + __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc, + (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2); +#endif + /* return only status bits */; + rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); + + txIdx = (txIdx + 1) % TX_BUF_CNT; + + return rc; +} + +static int fec_recv (struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = + (volatile fec_t *) (CFG_IMMR + efis->fecp_offset); + int length; + + for (;;) { + /* section 16.9.23.2 */ + if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = rtx->rxbd[rxIdx].cbd_datlen; + + if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { +#ifdef ET_DEBUG + printf ("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + rtx->rxbd[rxIdx].cbd_sc); +#endif + } else { + volatile uchar *rx = NetRxPackets[rxIdx]; + + length -= 4; + +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + if ((rx[0] & 1) != 0 + && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0 + && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0) + rx = NULL; +#endif + /* + * Pass the packet up to the protocol layers. + */ + if (rx != NULL) + NetReceive (rx, length); + } + + /* Give the buffer back to the FEC. */ + rtx->rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx->rxbd[PKTBUFSRX - 1].cbd_sc = + (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } else { + rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + + __asm__ ("eieio"); + + /* Try to fill Buffer Descriptors */ + fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ + } + + return length; +} + +/************************************************************** + * + * FEC Ethernet Initialization Routine + * + *************************************************************/ + +#define FEC_ECNTRL_PINMUX 0x00000004 +#define FEC_ECNTRL_ETHER_EN 0x00000002 +#define FEC_ECNTRL_RESET 0x00000001 + +#define FEC_RCNTRL_BC_REJ 0x00000010 +#define FEC_RCNTRL_PROM 0x00000008 +#define FEC_RCNTRL_MII_MODE 0x00000004 +#define FEC_RCNTRL_DRT 0x00000002 +#define FEC_RCNTRL_LOOP 0x00000001 + +#define FEC_TCNTRL_FDEN 0x00000004 +#define FEC_TCNTRL_HBC 0x00000002 +#define FEC_TCNTRL_GTS 0x00000001 + +#define FEC_RESET_DELAY 50 + +#if defined(CONFIG_RMII) + +static inline void fec_10Mbps(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + int fecidx = efis->ether_index; + uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; + + if ((unsigned int)fecidx >= 2) + hang(); + + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask; +} + +static inline void fec_100Mbps(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + int fecidx = efis->ether_index; + uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; + + if ((unsigned int)fecidx >= 2) + hang(); + + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask; +} + +#endif + +static inline void fec_full_duplex(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + + fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT; + fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */ +} + +static inline void fec_half_duplex(struct eth_device *dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + + fecp->fec_r_cntrl |= FEC_RCNTRL_DRT; + fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */ +} + +static void fec_pin_init(int fecidx) +{ + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile fec_t *fecp; + + /* + * only two FECs please + */ + if ((unsigned int)fecidx >= 2) + hang(); + + if (fecidx == 0) + fecp = &immr->im_cpm.cp_fec1; + else + fecp = &immr->im_cpm.cp_fec2; + + /* + * Set MII speed to 2.5 MHz or slightly below. + * * According to the MPC860T (Rev. D) Fast ethernet controller user + * * manual (6.2.14), + * * the MII management interface clock must be less than or equal + * * to 2.5 MHz. + * * This MDC frequency is equal to system clock / (2 * MII_SPEED). + * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. + */ + fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; + +#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) + /* our PHYs are the limit at 2.5 MHz */ + fecp->fec_mii_speed <<= 1; +#endif + +#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) + /* use MDC for MII */ + immr->im_ioport.iop_pdpar |= 0x0080; + immr->im_ioport.iop_pddir &= ~0x0080; +#endif + + if (fecidx == 0) { +#if defined(CONFIG_ETHER_ON_FEC1) + +#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ + +#if !defined(CONFIG_RMII) + + immr->im_ioport.iop_papar |= 0xf830; + immr->im_ioport.iop_padir |= 0x0830; + immr->im_ioport.iop_padir &= ~0xf000; + + immr->im_cpm.cp_pbpar |= 0x00001001; + immr->im_cpm.cp_pbdir &= ~0x00001001; + + immr->im_ioport.iop_pcpar |= 0x000c; + immr->im_ioport.iop_pcdir &= ~0x000c; + + immr->im_cpm.cp_pepar |= 0x00000003; + immr->im_cpm.cp_pedir |= 0x00000003; + immr->im_cpm.cp_peso &= ~0x00000003; + + immr->im_cpm.cp_cptr &= ~0x00000100; + +#else + +#if !defined(CONFIG_FEC1_PHY_NORXERR) + immr->im_ioport.iop_papar |= 0x1000; + immr->im_ioport.iop_padir &= ~0x1000; +#endif + immr->im_ioport.iop_papar |= 0xe810; + immr->im_ioport.iop_padir |= 0x0810; + immr->im_ioport.iop_padir &= ~0xe000; + + immr->im_cpm.cp_pbpar |= 0x00000001; + immr->im_cpm.cp_pbdir &= ~0x00000001; + + immr->im_cpm.cp_cptr |= 0x00000100; + immr->im_cpm.cp_cptr &= ~0x00000050; + +#endif /* !CONFIG_RMII */ + +#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) + /* + * Configure all of port D for MII. + */ + immr->im_ioport.iop_pdpar = 0x1fff; + + /* + * Bits moved from Rev. D onward + */ + if ((get_immr(0) & 0xffff) < 0x0501) + immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ + else + immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ +#else + /* + * Configure port A for MII. + */ + +#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY) + + /* + * On the ICU862 board the MII-MDC pin is routed to PD8 pin + * * of CPU, so for this board we need to configure Utopia and + * * enable PD8 to MII-MDC function + */ + immr->im_ioport.iop_pdpar |= 0x4080; +#endif + + /* + * Has Utopia been configured? + */ + if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) { + /* + * YES - Use MUXED mode for UTOPIA bus. + * This frees Port A for use by MII (see 862UM table 41-6). + */ + immr->im_ioport.utmode &= ~0x80; + } else { + /* + * NO - set SPLIT mode for UTOPIA bus. + * + * This doesn't really effect UTOPIA (which isn't + * enabled anyway) but just tells the 862 + * to use port A for MII (see 862UM table 41-6). + */ + immr->im_ioport.utmode |= 0x80; + } +#endif /* !defined(CONFIG_ICU862) */ + +#endif /* CONFIG_ETHER_ON_FEC1 */ + } else if (fecidx == 1) { + +#if defined(CONFIG_ETHER_ON_FEC2) + +#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ + +#if !defined(CONFIG_RMII) + +#warning this configuration is not tested; please report if it works + immr->im_cpm.cp_pepar |= 0x0003fffc; + immr->im_cpm.cp_pedir |= 0x0003fffc; + immr->im_cpm.cp_peso &= ~0x000087fc; + immr->im_cpm.cp_peso |= 0x00037800; + + immr->im_cpm.cp_cptr &= ~0x00000080; +#else + +#if !defined(CONFIG_FEC2_PHY_NORXERR) + immr->im_cpm.cp_pepar |= 0x00000010; + immr->im_cpm.cp_pedir |= 0x00000010; + immr->im_cpm.cp_peso &= ~0x00000010; +#endif + immr->im_cpm.cp_pepar |= 0x00039620; + immr->im_cpm.cp_pedir |= 0x00039620; + immr->im_cpm.cp_peso |= 0x00031000; + immr->im_cpm.cp_peso &= ~0x00008620; + + immr->im_cpm.cp_cptr |= 0x00000080; + immr->im_cpm.cp_cptr &= ~0x00000028; +#endif /* CONFIG_RMII */ + +#endif /* CONFIG_MPC885_FAMILY */ + +#endif /* CONFIG_ETHER_ON_FEC2 */ + + } +} + +static int fec_init (struct eth_device *dev, bd_t * bd) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile fec_t *fecp = + (volatile fec_t *) (CFG_IMMR + efis->fecp_offset); + int i; + + if (efis->ether_index == 0) { +#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */ +#if defined(CONFIG_MPC885ADS) + *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST); +#else + /* configure FADS for fast (FEC) ethernet, half-duplex */ + /* The LXT970 needs about 50ms to recover from reset, so + * wait for it by discovering the PHY before leaving eth_init(). + */ + { + volatile uint *bcsr4 = (volatile uint *) BCSR4; + + *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1)) + | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | + BCSR4_FETHRST); + + /* reset the LXT970 PHY */ + *bcsr4 &= ~BCSR4_FETHRST; + udelay (10); + *bcsr4 |= BCSR4_FETHRST; + udelay (10); + } +#endif /* CONFIG_MPC885ADS */ +#endif /* CONFIG_FADS */ + } + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { + printf ("FEC_RESET_DELAY timeout\n"); + return 0; + } + + /* We use strictly polling mode only + */ + fecp->fec_imask = 0; + + /* Clear any pending interrupt + */ + fecp->fec_ievent = 0xffc0; + + /* No need to set the IVEC register */ + + /* Set station address + */ +#define ea eth_get_dev()->enetaddr + fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); + fecp->fec_addr_high = (ea[4] << 8) | (ea[5]); +#undef ea + +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + /* + * Turn on multicast address hash table + */ + fecp->fec_hash_table_high = 0xffffffff; + fecp->fec_hash_table_low = 0xffffffff; +#else + /* Clear multicast address hash table + */ + fecp->fec_hash_table_high = 0; + fecp->fec_hash_table_low = 0; +#endif + + /* Set maximum receive buffer size. + */ + fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; + + /* Set maximum frame length + */ + fecp->fec_r_hash = PKT_MAXBUF_SIZE; + + /* + * Setup Buffers and Buffer Desriptors + */ + rxIdx = 0; + txIdx = 0; + + if (!rtx) { +#ifdef CFG_ALLOC_DPRAM + rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + + dpram_alloc_align (sizeof (RTXBD), 8)); +#else + rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE); +#endif + } + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + for (i = 0; i < PKTBUFSRX; i++) { + rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx->rxbd[i].cbd_datlen = 0; /* Reset */ + rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Last, Tx CRC + */ + for (i = 0; i < TX_BUF_CNT; i++) { + rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; + rtx->txbd[i].cbd_datlen = 0; /* Reset */ + rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); + } + rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* Set receive and transmit descriptor base + */ + fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); + fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); + + /* Enable MII mode + */ +#if 0 /* Full duplex mode */ + fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; + fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; +#else /* Half duplex mode */ + fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; + fecp->fec_x_cntrl = 0; +#endif + + /* Enable big endian and don't care about SDMA FC. + */ + fecp->fec_fun_code = 0x78000000; + + /* + * Setup the pin configuration of the FEC + */ + fec_pin_init (efis->ether_index); + + rxIdx = 0; + txIdx = 0; + + /* + * Now enable the transmit and receive processing + */ + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; + + if (efis->phy_addr == -1) { +#ifdef CFG_DISCOVER_PHY + /* + * wait for the PHY to wake up after reset + */ + efis->actual_phy_addr = mii_discover_phy (dev); + + if (efis->actual_phy_addr == -1) { + printf ("Unable to discover phy!\n"); + return 0; + } +#else + efis->actual_phy_addr = -1; +#endif + } else { + efis->actual_phy_addr = efis->phy_addr; + } +#if defined(CONFIG_MII) && defined(CONFIG_RMII) + + /* the MII interface is connected to FEC1 + * so for the miiphy_xxx function to work we must + * call mii_init since fec_halt messes the thing up + */ + if (efis->ether_index != 0) + mii_init(); + + /* + * adapt the RMII speed to the speed of the phy + */ + if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) { + fec_100Mbps (dev); + } else { + fec_10Mbps (dev); + } +#endif + +#if defined(CONFIG_MII) + /* + * adapt to the half/full speed settings + */ + if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) { + fec_full_duplex (dev); + } else { + fec_half_duplex (dev); + } +#endif + + /* And last, try to fill Rx Buffer Descriptors */ + fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ + + efis->initialized = 1; + + return 1; +} + + +static void fec_halt(struct eth_device* dev) +{ + struct ether_fcc_info_s *efis = dev->priv; + volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + int i; + + /* avoid halt if initialized; mii gets stuck otherwise */ + if (!efis->initialized) + return; + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { + printf ("FEC_RESET_DELAY timeout\n"); + return; + } + + efis->initialized = 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + +/* Make MII read/write commands for the FEC. +*/ + +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18) | \ + (VAL & 0xffff)) + +/* Interrupt events/masks. +*/ +#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ +#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ +#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ +#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ +#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ +#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ +#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ +#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ +#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ +#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ + +/* PHY identification + */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */ + +/* send command to phy using mii, wait for result */ +static uint +mii_send(uint mii_cmd) +{ + uint mii_reply; + volatile fec_t *ep; + int cnt; + + ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec); + + ep->fec_mii_data = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + cnt = 0; + while (!(ep->fec_ievent & FEC_ENET_MII)) { + if (++cnt > 1000) { + printf("mii_send STUCK!\n"); + break; + } + } + mii_reply = ep->fec_mii_data; /* result from phy */ + ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ +#if 0 + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply); +#endif + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +static int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + uint phyno; + int pass; + uint phytype; + int phyaddr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type ", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= mii_send(mk_mii_read(phyno, + PHY_PHYIDR2)); + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ",phyno,pass); + switch (phytype & 0xfffffff0) { + case PHY_ID_LXT970: + printf("LXT970\n"); + break; + case PHY_ID_LXT971: + printf("LXT971\n"); + break; + case PHY_ID_82555: + printf("82555\n"); + break; + case PHY_ID_QS6612: + printf("QS6612\n"); + break; + case PHY_ID_AMD79C784: + printf("AMD79C784\n"); + break; + case PHY_ID_LSI80225B: + printf("LSI L80225/B\n"); + break; + case PHY_ID_DM9161: + printf("Davicom DM9161\n"); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) { + printf("No PHY device found.\n"); + } + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII) + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_init (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile fec_t *fecp = &(immr->im_cpm.cp_fec); + int i, j; + + for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) { + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { + printf ("FEC_RESET_DELAY timeout\n"); + return; + } + + /* We use strictly polling mode only + */ + fecp->fec_imask = 0; + + /* Clear any pending interrupt + */ + fecp->fec_ievent = 0xffc0; + + /* Setup the pin configuration of the FEC(s) + */ + fec_pin_init(ether_fcc_info[i].ether_index); + + /* Now enable the transmit and receive processing + */ + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; + } +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int fec8xx_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; +#ifdef MII_DEBUG + printf ("0x%04x\n", *value); +#endif + return 0; +} + +int fec8xx_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + short rdreg; /* register working value */ +#ifdef MII_DEBUG + printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf ("0x%04x\n", value); +#endif + return 0; +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/ + +#endif /* CFG_CMD_NET, FEC_ENET */ diff --git a/cpu/mpc8xx/fec.h b/cpu/mpc8xx/fec.h new file mode 100644 index 0000000..a49417c --- /dev/null +++ b/cpu/mpc8xx/fec.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FEC_H_ +#define _FEC_H_ + + +#endif /* _FEC_H_ */ diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c new file mode 100644 index 0000000..682db53 --- /dev/null +++ b/cpu/mpc8xx/i2c.c @@ -0,0 +1,744 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. + */ + +#include + +#ifdef CONFIG_HARD_I2C + +#include +#include +#ifdef CONFIG_LWMON +#include +#endif + +/* define to enable debug messages */ +#undef DEBUG_I2C + +/*----------------------------------------------------------------------- + * Set default values + */ +#ifndef CFG_I2C_SPEED +#define CFG_I2C_SPEED 50000 +#endif + +#ifndef CFG_I2C_SLAVE +#define CFG_I2C_SLAVE 0xFE +#endif +/*----------------------------------------------------------------------- + */ + +/* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */ +#define TOUT_LOOP 1000000 + +#define NUM_RX_BDS 4 +#define NUM_TX_BDS 4 +#define MAX_TX_SPACE 256 +#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ + +typedef struct I2C_BD +{ + unsigned short status; + unsigned short length; + unsigned char *addr; +} I2C_BD; +#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ + +#define BD_I2C_TX_CL 0x0001 /* collision error */ +#define BD_I2C_TX_UN 0x0002 /* underflow error */ +#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */ +#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL) + +#define BD_I2C_RX_ERR BD_SC_OV + +typedef void (*i2c_ecb_t)(int, int); /* error callback function */ + +/* This structure keeps track of the bd and buffer space usage. */ +typedef struct i2c_state { + int rx_idx; /* index to next free Rx BD */ + int tx_idx; /* index to next free Tx BD */ + void *rxbd; /* pointer to next free Rx BD */ + void *txbd; /* pointer to next free Tx BD */ + int tx_space; /* number of Tx bytes left */ + unsigned char *tx_buf; /* pointer to free Tx area */ + i2c_ecb_t err_cb; /* error callback function */ +} i2c_state_t; + + +/* flags for i2c_send() and i2c_receive() */ +#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ +#define I2CF_START_COND 0x02 /* tx: generate start condition */ +#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ + +/* return codes */ +#define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */ +#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */ +#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */ +#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */ + +/* error callback flags */ +#define I2CECB_RX_ERR 0x10 /* this is a receive error */ +#define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */ +#define I2CECB_RX_MASK 0x0f /* mask for error bits */ +#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ +#define I2CECB_TX_CL 0x01 /* transmit collision error */ +#define I2CECB_TX_UN 0x02 /* transmit underflow error */ +#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ +#define I2CECB_TX_MASK 0x0f /* mask for error bits */ +#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ + +#ifdef DEBUG_I2C +#define PRINTD(x) printf x +#else +#define PRINTD(x) +#endif + +/* + * Returns the best value of I2BRG to meet desired clock speed of I2C with + * input parameters (clock speed, filter, and predivider value). + * It returns computer speed value and the difference between it and desired + * speed. + */ +static inline int +i2c_roundrate(int hz, int speed, int filter, int modval, + int *brgval, int *totspeed) +{ + int moddiv = 1 << (5-(modval & 3)), brgdiv, div; + + PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", + hz, speed, filter, modval)); + + div = moddiv * speed; + brgdiv = (hz + div - 1) / div; + + PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv)); + + *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter); + + if ((*brgval < 0) || (*brgval > 255)) { + PRINTD(("\t\trejected brgval=%d\n", *brgval)); + return -1; + } + + brgdiv = 2 * (*brgval + 3 + (2 * filter)); + div = moddiv * brgdiv ; + *totspeed = hz / div; + + PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed)); + + return 0; +} + +/* + * Sets the I2C clock predivider and divider to meet required clock speed. + */ +static int +i2c_setrate (int hz, int speed) +{ + immap_t *immap = (immap_t *) CFG_IMMR; + volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c; + int brgval, + modval, /* 0-3 */ + bestspeed_diff = speed, + bestspeed_brgval = 0, + bestspeed_modval = 0, + bestspeed_filter = 0, + totspeed, + filter = 0; /* Use this fixed value */ + + for (modval = 0; modval < 4; modval++) { + if (i2c_roundrate(hz,speed,filter,modval,&brgval,&totspeed) == 0) { + int diff = speed - totspeed; + + if ((diff >= 0) && (diff < bestspeed_diff)) { + bestspeed_diff = diff; + bestspeed_modval = modval; + bestspeed_brgval = brgval; + bestspeed_filter = filter; + } + } + } + + PRINTD (("[I2C] Best is:\n")); + PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", + hz, + speed, + bestspeed_filter, + bestspeed_modval, + bestspeed_brgval, + bestspeed_diff)); + + i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); + i2c->i2c_i2brg = bestspeed_brgval & 0xff; + + PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, + i2c->i2c_i2brg)); + + return 1; +} + +void +i2c_init(int speed, int slaveaddr) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; + volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; + volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; + ulong rbase, tbase; + volatile I2C_BD *rxbd, *txbd; + uint dpaddr; + +#ifdef CFG_I2C_INIT_BOARD + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#endif + +#ifdef CFG_I2C_UCODE_PATCH + iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; +#else + /* Disable relocation */ + iip->iic_rpbase = 0; +#endif + +#ifdef CFG_ALLOC_DPRAM + dpaddr = iip->iic_rbase; + if (dpaddr == 0) { + /* need to allocate dual port ram */ + dpaddr = dpram_alloc_align( + (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) + + MAX_TX_SPACE, 8); + } +#else + dpaddr = CPM_I2C_BASE; +#endif + + /* + * initialise data in dual port ram: + * + * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes) + * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes) + * tx buffer (MAX_TX_SPACE bytes) + */ + + rbase = dpaddr; + tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD); + + /* Initialize Port B I2C pins. */ + cp->cp_pbpar |= 0x00000030; + cp->cp_pbdir |= 0x00000030; + cp->cp_pbodr |= 0x00000030; + + /* Disable interrupts */ + i2c->i2c_i2mod = 0x00; + i2c->i2c_i2cmr = 0x00; + i2c->i2c_i2cer = 0xff; + i2c->i2c_i2add = slaveaddr; + + /* + * Set the I2C BRG Clock division factor from desired i2c rate + * and current CPU rate (we assume sccr dfbgr field is 0; + * divide BRGCLK by 1) + */ + PRINTD(("[I2C] Setting rate...\n")); + i2c_setrate (gd->cpu_clk, CFG_I2C_SPEED) ; + + /* Set I2C controller in master mode */ + i2c->i2c_i2com = 0x01; + + /* Set SDMA bus arbitration level to 5 (SDCR) */ + immap->im_siu_conf.sc_sdcr = 0x0001 ; + + /* Initialize Tx/Rx parameters */ + iip->iic_rbase = rbase; + iip->iic_tbase = tbase; + rxbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]); + txbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]); + + PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase)); + PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase)); + PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); + PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + + /* Set big endian byte order */ + iip->iic_tfcr = 0x10; + iip->iic_rfcr = 0x10; + + /* Set maximum receive size. */ + iip->iic_mrblr = I2C_RXTX_LEN; + +#ifdef CFG_I2C_UCODE_PATCH + /* + * Initialize required parameters if using microcode patch. + */ + iip->iic_rbptr = iip->iic_rbase; + iip->iic_tbptr = iip->iic_tbase; + iip->iic_rstate = 0; + iip->iic_tstate = 0; +#else + cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG; + do { + __asm__ __volatile__ ("eieio"); + } while (cp->cp_cpcr & CPM_CR_FLG); +#endif + + /* Clear events and interrupts */ + i2c->i2c_i2cer = 0xff; + i2c->i2c_i2cmr = 0x00; +} + +static void +i2c_newio(i2c_state_t *state) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; + volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; + + PRINTD(("[I2C] i2c_newio\n")); + +#ifdef CFG_I2C_UCODE_PATCH + iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; +#endif + state->rx_idx = 0; + state->tx_idx = 0; + state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase]; + state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase]; + state->tx_space = MAX_TX_SPACE; + state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); + state->err_cb = NULL; + + PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd)); + PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd)); + PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf)); + + /* clear the buffer memory */ + memset((char *)state->tx_buf, 0, MAX_TX_SPACE); +} + +static int +i2c_send(i2c_state_t *state, + unsigned char address, + unsigned char secondary_address, + unsigned int flags, + unsigned short size, + unsigned char *dataout) +{ + volatile I2C_BD *txbd; + int i,j; + + PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", + address, secondary_address, flags, size)); + + /* trying to send message larger than BD */ + if (size > I2C_RXTX_LEN) + return I2CERR_MSG_TOO_LONG; + + /* no more free bds */ + if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size)) + return I2CERR_NO_BUFFERS; + + txbd = (I2C_BD *)state->txbd; + txbd->addr = state->tx_buf; + + PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + + if (flags & I2CF_START_COND) { + PRINTD(("[I2C] Formatting addresses...\n")); + if (flags & I2CF_ENABLE_SECONDARY) { + txbd->length = size + 2; /* Length of msg + dest addr */ + txbd->addr[0] = address << 1; + txbd->addr[1] = secondary_address; + i = 2; + } else { + txbd->length = size + 1; /* Length of msg + dest addr */ + txbd->addr[0] = address << 1; /* Write dest addr to BD */ + i = 1; + } + } else { + txbd->length = size; /* Length of message */ + i = 0; + } + + /* set up txbd */ + txbd->status = BD_SC_READY; + if (flags & I2CF_START_COND) + txbd->status |= BD_I2C_TX_START; + if (flags & I2CF_STOP_COND) + txbd->status |= BD_SC_LAST | BD_SC_WRAP; + + /* Copy data to send into buffer */ + PRINTD(("[I2C] copy data...\n")); + for(j = 0; j < size; i++, j++) + txbd->addr[i] = dataout[j]; + + PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + txbd->length, + txbd->status, + txbd->addr[0], + txbd->addr[1])); + + /* advance state */ + state->tx_buf += txbd->length; + state->tx_space -= txbd->length; + state->tx_idx++; + state->txbd = (void*)(txbd + 1); + + return 0; +} + +static int +i2c_receive(i2c_state_t *state, + unsigned char address, + unsigned char secondary_address, + unsigned int flags, + unsigned short size_to_expect, + unsigned char *datain) +{ + volatile I2C_BD *rxbd, *txbd; + + PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags)); + + /* Expected to receive too much */ + if (size_to_expect > I2C_RXTX_LEN) + return I2CERR_MSG_TOO_LONG; + + /* no more free bds */ + if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS + || state->tx_space < 2) + return I2CERR_NO_BUFFERS; + + rxbd = (I2C_BD *)state->rxbd; + txbd = (I2C_BD *)state->txbd; + + PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); + PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + + txbd->addr = state->tx_buf; + + /* set up TXBD for destination address */ + if (flags & I2CF_ENABLE_SECONDARY) { + txbd->length = 2; + txbd->addr[0] = address << 1; /* Write data */ + txbd->addr[1] = secondary_address; /* Internal address */ + txbd->status = BD_SC_READY; + } else { + txbd->length = 1 + size_to_expect; + txbd->addr[0] = (address << 1) | 0x01; + txbd->status = BD_SC_READY; + memset(&txbd->addr[1], 0, txbd->length); + } + + /* set up rxbd for reception */ + rxbd->status = BD_SC_EMPTY; + rxbd->length = size_to_expect; + rxbd->addr = datain; + + txbd->status |= BD_I2C_TX_START; + if (flags & I2CF_STOP_COND) { + txbd->status |= BD_SC_LAST | BD_SC_WRAP; + rxbd->status |= BD_SC_WRAP; + } + + PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + txbd->length, + txbd->status, + txbd->addr[0], + txbd->addr[1])); + PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + rxbd->length, + rxbd->status, + rxbd->addr[0], + rxbd->addr[1])); + + /* advance state */ + state->tx_buf += txbd->length; + state->tx_space -= txbd->length; + state->tx_idx++; + state->txbd = (void*)(txbd + 1); + state->rx_idx++; + state->rxbd = (void*)(rxbd + 1); + + return 0; +} + + +static int i2c_doio(i2c_state_t *state) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; + volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; + volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; + volatile I2C_BD *txbd, *rxbd; + volatile int j = 0; + + PRINTD(("[I2C] i2c_doio\n")); + +#ifdef CFG_I2C_UCODE_PATCH + iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; +#endif + + if (state->tx_idx <= 0 && state->rx_idx <= 0) { + PRINTD(("[I2C] No I/O is queued\n")); + return I2CERR_QUEUE_EMPTY; + } + + iip->iic_rbptr = iip->iic_rbase; + iip->iic_tbptr = iip->iic_tbase; + + /* Enable I2C */ + PRINTD(("[I2C] Enabling I2C...\n")); + i2c->i2c_i2mod |= 0x01; + + /* Begin transmission */ + i2c->i2c_i2com |= 0x80; + + /* Loop until transmit & receive completed */ + + if (state->tx_idx > 0) { + txbd = ((I2C_BD*)state->txbd) - 1; + PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd)); + while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) { + if (ctrlc()) { + return (-1); + } + __asm__ __volatile__ ("eieio"); + } + } + + if ((state->rx_idx > 0) && (j < TOUT_LOOP)) { + rxbd = ((I2C_BD*)state->rxbd) - 1; + PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd)); + while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) { + if (ctrlc()) { + return (-1); + } + __asm__ __volatile__ ("eieio"); + } + } + + /* Turn off I2C */ + i2c->i2c_i2mod &= ~0x01; + + if (state->err_cb != NULL) { + int n, i, b; + + /* + * if we have an error callback function, look at the + * error bits in the bd status and pass them back + */ + + if ((n = state->tx_idx) > 0) { + for (i = 0; i < n; i++) { + txbd = ((I2C_BD*)state->txbd) - (n - i); + if ((b = txbd->status & BD_I2C_TX_ERR) != 0) + (*state->err_cb)(I2CECB_TX_ERR|b, i); + } + } + + if ((n = state->rx_idx) > 0) { + for (i = 0; i < n; i++) { + rxbd = ((I2C_BD*)state->rxbd) - (n - i); + if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) + (*state->err_cb)(I2CECB_RX_ERR|b, i); + } + } + + if (j >= TOUT_LOOP) + (*state->err_cb)(I2CECB_TIMEOUT, 0); + } + + return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0; +} + +static int had_tx_nak; + +static void +i2c_test_callback(int flags, int xnum) +{ + if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK)) + had_tx_nak = 1; +} + +int i2c_probe(uchar chip) +{ + i2c_state_t state; + int rc; + uchar buf[1]; + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + i2c_newio(&state); + + state.err_cb = i2c_test_callback; + had_tx_nak = 0; + + rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf); + + if (rc != 0) + return (rc); + + rc = i2c_doio(&state); + + if ((rc != 0) && (rc != I2CERR_TIMEOUT)) + return (rc); + + return (had_tx_nak); +} + +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + DECLARE_GLOBAL_DATA_PTR; + + i2c_state_t state; + uchar xaddr[4]; + int rc; + +#ifdef CONFIG_LWMON + WATCHDOG_RESET(); +#endif + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones like + * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the + * extra bits end up in the "chip address" bit slots. This makes + * a 24WC08 (1Kbyte) chip look like four 256 byte chips. + * + * Note that we consider the length of the address field to still + * be one byte because the extra address bits are hidden in the + * chip address. + */ + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + + i2c_newio(&state); + + rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); + if (rc != 0) { + if (gd->have_console) + printf("i2c_read: i2c_send failed (%d)\n", rc); + return 1; + } + + rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer); + if (rc != 0) { + if (gd->have_console) + printf("i2c_read: i2c_receive failed (%d)\n", rc); + return 1; + } + + rc = i2c_doio(&state); + if (rc != 0) { + if (gd->have_console) + printf("i2c_read: i2c_doio failed (%d)\n", rc); + return 1; + } + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + DECLARE_GLOBAL_DATA_PTR; + + i2c_state_t state; + uchar xaddr[4]; + int rc; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones like + * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the + * extra bits end up in the "chip address" bit slots. This makes + * a 24WC08 (1Kbyte) chip look like four 256 byte chips. + * + * Note that we consider the length of the address field to still + * be one byte because the extra address bits are hidden in the + * chip address. + */ + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + + i2c_newio(&state); + + rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); + if (rc != 0) { + if (gd->have_console) + printf("i2c_write: first i2c_send failed (%d)\n", rc); + return 1; + } + + rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer); + if (rc != 0) { + if (gd->have_console) + printf("i2c_write: second i2c_send failed (%d)\n", rc); + return 1; + } + + rc = i2c_doio(&state); + if (rc != 0) { + if (gd->have_console) + printf("i2c_write: i2c_doio failed (%d)\n", rc); + return 1; + } + return 0; +} + +uchar +i2c_reg_read(uchar i2c_addr, uchar reg) +{ + uchar buf; + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + i2c_read(i2c_addr, reg, 1, &buf, 1); + + return (buf); +} + +void +i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + i2c_write(i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8xx/interrupts.c b/cpu/mpc8xx/interrupts.c new file mode 100644 index 0000000..20e7012 --- /dev/null +++ b/cpu/mpc8xx/interrupts.c @@ -0,0 +1,294 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/************************************************************************/ + +/* + * CPM interrupt vector functions. + */ +struct interrupt_action { + interrupt_handler_t *handler; + void *arg; +}; + +static struct interrupt_action cpm_vecs[CPMVEC_NR]; +static struct interrupt_action irq_vecs[NR_IRQS]; + +static void cpm_interrupt_init (void); +static void cpm_interrupt (void *regs); + +/************************************************************************/ + +int interrupt_init_cpu (unsigned *decrementer_count) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + *decrementer_count = get_tbclk () / CFG_HZ; + + /* disable all interrupts */ + immr->im_siu_conf.sc_simask = 0; + + /* Configure CPM interrupts */ + cpm_interrupt_init (); + + return (0); +} + +/************************************************************************/ + +/* + * Handle external interrupts + */ +void external_interrupt (struct pt_regs *regs) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + int irq; + ulong simask, newmask; + ulong vec, v_bit; + + /* + * read the SIVEC register and shift the bits down + * to get the irq number + */ + vec = immr->im_siu_conf.sc_sivec; + irq = vec >> 26; + v_bit = 0x80000000UL >> irq; + + /* + * Read Interrupt Mask Register and Mask Interrupts + */ + simask = immr->im_siu_conf.sc_simask; + newmask = simask & (~(0xFFFF0000 >> irq)); + immr->im_siu_conf.sc_simask = newmask; + + if (!(irq & 0x1)) { /* External Interrupt ? */ + ulong siel; + + /* + * Read Interrupt Edge/Level Register + */ + siel = immr->im_siu_conf.sc_siel; + + if (siel & v_bit) { /* edge triggered interrupt ? */ + /* + * Rewrite SIPEND Register to clear interrupt + */ + immr->im_siu_conf.sc_sipend = v_bit; + } + } + + if (irq_vecs[irq].handler != NULL) { + irq_vecs[irq].handler (irq_vecs[irq].arg); + } else { + printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", + irq, vec); + /* turn off the bogus interrupt to avoid it from now */ + simask &= ~v_bit; + } + /* + * Re-Enable old Interrupt Mask + */ + immr->im_siu_conf.sc_simask = simask; +} + +/************************************************************************/ + +/* + * CPM interrupt handler + */ +static void cpm_interrupt (void *regs) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + uint vec; + + /* + * Get the vector by setting the ACK bit + * and then reading the register. + */ + immr->im_cpic.cpic_civr = 1; + vec = immr->im_cpic.cpic_civr; + vec >>= 11; + + if (cpm_vecs[vec].handler != NULL) { + (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg); + } else { + immr->im_cpic.cpic_cimr &= ~(1 << vec); + printf ("Masking bogus CPM interrupt vector 0x%x\n", vec); + } + /* + * After servicing the interrupt, + * we have to remove the status indicator. + */ + immr->im_cpic.cpic_cisr |= (1 << vec); +} + +/* + * The CPM can generate the error interrupt when there is a race + * condition between generating and masking interrupts. All we have + * to do is ACK it and return. This is a no-op function so we don't + * need any special tests in the interrupt handler. + */ +static void cpm_error_interrupt (void *dummy) +{ +} + +/************************************************************************/ +/* + * Install and free an interrupt handler + */ +void irq_install_handler (int vec, interrupt_handler_t * handler, + void *arg) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + if ((vec & CPMVEC_OFFSET) != 0) { + /* CPM interrupt */ + vec &= 0xffff; + if (cpm_vecs[vec].handler != NULL) { + printf ("CPM interrupt 0x%x replacing 0x%x\n", + (uint) handler, + (uint) cpm_vecs[vec].handler); + } + cpm_vecs[vec].handler = handler; + cpm_vecs[vec].arg = arg; + immr->im_cpic.cpic_cimr |= (1 << vec); +#if 0 + printf ("Install CPM interrupt for vector %d ==> %p\n", + vec, handler); +#endif + } else { + /* SIU interrupt */ + if (irq_vecs[vec].handler != NULL) { + printf ("SIU interrupt %d 0x%x replacing 0x%x\n", + vec, + (uint) handler, + (uint) cpm_vecs[vec].handler); + } + irq_vecs[vec].handler = handler; + irq_vecs[vec].arg = arg; + immr->im_siu_conf.sc_simask |= 1 << (31 - vec); +#if 0 + printf ("Install SIU interrupt for vector %d ==> %p\n", + vec, handler); +#endif + } +} + +void irq_free_handler (int vec) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + if ((vec & CPMVEC_OFFSET) != 0) { + /* CPM interrupt */ + vec &= 0xffff; +#if 0 + printf ("Free CPM interrupt for vector %d ==> %p\n", + vec, cpm_vecs[vec].handler); +#endif + immr->im_cpic.cpic_cimr &= ~(1 << vec); + cpm_vecs[vec].handler = NULL; + cpm_vecs[vec].arg = NULL; + } else { + /* SIU interrupt */ +#if 0 + printf ("Free CPM interrupt for vector %d ==> %p\n", + vec, cpm_vecs[vec].handler); +#endif + immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); + irq_vecs[vec].handler = NULL; + irq_vecs[vec].arg = NULL; + } +} + +/************************************************************************/ + +static void cpm_interrupt_init (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* + * Initialize the CPM interrupt controller. + */ + + immr->im_cpic.cpic_cicr = + (CICR_SCD_SCC4 | + CICR_SCC_SCC3 | + CICR_SCB_SCC2 | + CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK; + + immr->im_cpic.cpic_cimr = 0; + + /* + * Install the error handler. + */ + irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL); + + immr->im_cpic.cpic_cicr |= CICR_IEN; + + /* + * Install the cpm interrupt handler + */ + irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL); +} + +/************************************************************************/ + +/* + * timer_interrupt - gets called when the decrementer overflows, + * with interrupts disabled. + * Trivial implementation - no need to be really accurate. + */ +void timer_interrupt_cpu (struct pt_regs *regs) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + +#if 0 + printf ("*** Timer Interrupt *** "); +#endif + /* Reset Timer Expired and Timers Interrupt Status */ + immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; + __asm__ ("nop"); + /* + Clear TEXPS (and TMIST on older chips). SPLSS (on older + chips) is cleared too. + + Bitwise OR is a read-modify-write operation so ALL bits + which are cleared by writing `1' would be cleared by + operations like + + immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; + + The same can be achieved by simple writing of the PLPRCR + to itself. If a bit value should be preserved, read the + register, ZERO the bit and write, not OR, the result back. + */ + immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr; +} + +/************************************************************************/ diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S new file mode 100644 index 0000000..11c3c69 --- /dev/null +++ b/cpu/mpc8xx/kgdb.S @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2000 Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define CONFIG_8xx 1 /* needed for Linux kernel header files */ +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + + /* + * cache flushing routines for kgdb + */ + + .globl kgdb_flush_cache_all +kgdb_flush_cache_all: + lis r3, IDC_INVALL@h + mtspr DC_CST, r3 + sync + lis r3, IDC_INVALL@h + mtspr IC_CST, r3 + SYNC + blr + + .globl kgdb_flush_cache_range +kgdb_flush_cache_range: + li r5,CFG_CACHELINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,CFG_CACHELINE_SHIFT + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,CFG_CACHELINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,CFG_CACHELINE_SIZE + bdnz 2b + SYNC + blr + +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c new file mode 100644 index 0000000..3c64a9b --- /dev/null +++ b/cpu/mpc8xx/lcd.c @@ -0,0 +1,621 @@ +/* + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering -- wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************/ +/* ** HEADER FILES */ +/************************************************************************/ + +/* #define DEBUG */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_POST) +#include +#endif +#include + +#ifdef CONFIG_LCD + +/************************************************************************/ +/* ** CONFIG STUFF -- should be moved to board config file */ +/************************************************************************/ +#ifndef CONFIG_LCD_INFO +#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ +#endif + +#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10) +#undef CONFIG_LCD_LOGO +#undef CONFIG_LCD_INFO +#endif + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_KYOCERA_KCS057QV1AJ +/* + * Kyocera KCS057QV1AJ-G23. Passive, color, single scan. + */ +#define LCD_BPP LCD_COLOR4 + +vidinfo_t panel_info = { + 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, + LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_KYOCERA_KCS057QV1AJ */ +/*----------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_HITACHI_SP19X001_Z1A +/* + * Hitachi SP19X001-. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 154, 116, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, + LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_HITACHI_SP19X001_Z1A */ +/*----------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_NEC_NL6448AC33 +/* + * NEC NL6448AC33-18. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_NEC_NL6448AC33 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_NEC_NL6448BC20 +/* + * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_NEC_NL6448BC20 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_NEC_NL6448BC33_54 +/* + * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 212, 158, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_NEC_NL6448BC33_54 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_LQ104V7DS01 +/* + * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW, + 3, 0, 0, 1, 1, 25, 1, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ104V7DS01 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_16x9 +/* + * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am + * not sure what it is....... + */ +vidinfo_t panel_info = { + 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, + 3, 0, 0, 1, 1, 15, 4, 0, 3 +}; +#endif /* CONFIG_SHARP_16x9 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_LQ057Q3DC02 +/* + * Sharp LQ057Q3DC02 display. Active, color, single scan. + */ +#undef LCD_DF +#define LCD_DF 12 + +vidinfo_t panel_info = { + 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 3, 0, 0, 1, 1, 15, 4, 0, 3 + /* wbl, vpw, lcdac, wbf */ +}; +#define CONFIG_LCD_INFO_BELOW_LOGO +#endif /* CONFIG_SHARP_LQ057Q3DC02 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_LQ64D341 +/* + * Sharp LQ64D341 display, 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 3, 0, 0, 1, 1, 128, 16, 0, 32 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ64D341 */ + +#ifdef CONFIG_SHARP_LQ065T9DR51U +/* + * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan. + */ +vidinfo_t panel_info = { + 400, 240, 143, 79, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, + 3, 0, 0, 1, 1, 248, 4, 0, 35 + /* wbl, vpw, lcdac, wbf */ +}; +#define CONFIG_LCD_INFO_BELOW_LOGO +#endif /* CONFIG_SHARP_LQ065T9DR51U */ + +#ifdef CONFIG_SHARP_LQ084V1DG21 +/* + * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 171, 129, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW, + 3, 0, 0, 1, 1, 160, 3, 0, 48 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ084V1DG21 */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_HLD1045 +/* + * HLD1045 display, 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 3, 0, 0, 1, 1, 160, 3, 0, 48 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_HLD1045 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_PRIMEVIEW_V16C6448AC +/* + * Prime View V16C6448AC + */ +vidinfo_t panel_info = { + 640, 480, 130, 98, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 35 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_PRIMEVIEW_V16C6448AC */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_OPTREX_BW +/* + * Optrex CBL50840-2 NF-FW 99 22 M5 + * or + * Hitachi LMG6912RPFC-00T + * or + * Hitachi SP14Q002 + * + * 320x240. Black & white. + */ +#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */ + /* 1 - 4 grey levels, 2 bpp */ + /* 2 - 16 grey levels, 4 bpp */ +vidinfo_t panel_info = { + 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW, + OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4 +}; +#endif /* CONFIG_OPTREX_BW */ + +/*-----------------------------------------------------------------*/ +#ifdef CONFIG_EDT32F10 +/* + * Emerging Display Technologies 320x240. Passive, monochrome, single scan. + */ +#define LCD_BPP LCD_MONOCHROME +#define LCD_DF 10 + +vidinfo_t panel_info = { + 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW, + LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0 +}; +#endif +/*----------------------------------------------------------------------*/ + + +int lcd_line_length; + +int lcd_color_fg; +int lcd_color_bg; + +/* + * Frame buffer memory information + */ +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +short console_col; +short console_row; + +/************************************************************************/ + +void lcd_ctrl_init (void *lcdbase); +void lcd_enable (void); +#if LCD_BPP == LCD_COLOR8 +void lcd_setcolreg (ushort regno, + ushort red, ushort green, ushort blue); +#endif +#if LCD_BPP == LCD_MONOCHROME +void lcd_initcolregs (void); +#endif + +#if defined(CONFIG_RBC823) +void lcd_disable (void); +#endif + +/************************************************************************/ + +/************************************************************************/ +/* ----------------- chipset specific functions ----------------------- */ +/************************************************************************/ + +/* + * Calculate fb size for VIDEOLFB_ATAG. + */ +ulong calc_fbsize (void) +{ + ulong size; + int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + + size = line_length * panel_info.vl_row; + + return size; +} + +void lcd_ctrl_init (void *lcdbase) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile lcd823_t *lcdp = &immr->im_lcd; + + uint lccrtmp; + uint lchcr_hpc_tmp; + + /* Initialize the LCD control register according to the LCD + * parameters defined. We do everything here but enable + * the controller. + */ + +#ifdef CONFIG_RPXLITE + /* This is special for RPXlite_DW Software Development Platform **[Sam]** */ + panel_info.vl_dp = CFG_LOW; +#endif + + lccrtmp = LCDBIT (LCCR_BNUM_BIT, + (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); + + lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) | + LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) | + LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) | + LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) | + LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) | + LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) | + LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) | + LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) | + LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) | + LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft); + +#if 0 + lccrtmp |= ((SIU_LEVEL5 / 2) << 12); + lccrtmp |= LCCR_EIEN; +#endif + + lcdp->lcd_lccr = lccrtmp; + lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */ + + /* Initialize LCD controller bus priorities. + */ +#ifdef CONFIG_RBC823 + immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */ +#else + immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ + + /* set SHFT/CLOCK division factor 4 + * This needs to be set based upon display type and processor + * speed. The TFT displays run about 20 to 30 MHz. + * I was running 64 MHz processor speed. + * The value for this divider must be chosen so the result is + * an integer of the processor speed (i.e., divide by 3 with + * 64 MHz would be bad). + */ + immr->im_clkrst.car_sccr &= ~0x1F; + immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ + +#endif /* CONFIG_RBC823 */ + +#if defined(CONFIG_RBC823) + /* Enable LCD on port D. + */ + immr->im_ioport.iop_pddat &= 0x0300; + immr->im_ioport.iop_pdpar |= 0x1CFF; + immr->im_ioport.iop_pddir |= 0x1CFF; + + /* Configure LCD_ON, VEE_ON, CCFL_ON on port B. + */ + immr->im_cpm.cp_pbdat &= ~0x00005001; + immr->im_cpm.cp_pbpar &= ~0x00005001; + immr->im_cpm.cp_pbdir |= 0x00005001; +#elif !defined(CONFIG_EDT32F10) + /* Enable LCD on port D. + */ + immr->im_ioport.iop_pdpar |= 0x1FFF; + immr->im_ioport.iop_pddir |= 0x1FFF; + + /* Enable LCD_A/B/C on port B. + */ + immr->im_cpm.cp_pbpar |= 0x00005001; + immr->im_cpm.cp_pbdir |= 0x00005001; +#else + /* Enable LCD on port D. + */ + immr->im_ioport.iop_pdpar |= 0x1DFF; + immr->im_ioport.iop_pdpar &= ~0x0200; + immr->im_ioport.iop_pddir |= 0x1FFF; + immr->im_ioport.iop_pddat |= 0x0200; +#endif + + /* Load the physical address of the linear frame buffer + * into the LCD controller. + * BIG NOTE: This has to be modified to load A and B depending + * upon the split mode of the LCD. + */ + lcdp->lcd_lcfaa = (ulong)lcd_base; + lcdp->lcd_lcfba = (ulong)lcd_base; + + /* MORE HACKS...This must be updated according to 823 manual + * for different panels. + * Udi Finkelstein - done - see below: + * Note: You better not try unsupported combinations such as + * 4-bit wide passive dual scan LCD at 4/8 Bit color. + */ + lchcr_hpc_tmp = + (panel_info.vl_col * + (panel_info.vl_tft ? 8 : + (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */ + /* use << to mult by: single scan = 1, dual scan = 2 */ + panel_info.vl_splt) * + (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */ + + lcdp->lcd_lchcr = LCHCR_BO | + LCDBIT (LCHCR_AT_BIT, 4) | + LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) | + panel_info.vl_wbl; + + lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) | + LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) | + LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) | + panel_info.vl_wbf; + +} + +/*----------------------------------------------------------------------*/ + +#ifdef NOT_USED_SO_FAR +static void +lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = &(immr->im_cpm); + unsigned short colreg, *cmap_ptr; + + cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; + + colreg = *cmap_ptr; +#ifdef CFG_INVERT_COLORS + colreg ^= 0x0FFF; +#endif + + *red = (colreg >> 8) & 0x0F; + *green = (colreg >> 4) & 0x0F; + *blue = colreg & 0x0F; +} +#endif /* NOT_USED_SO_FAR */ + +/*----------------------------------------------------------------------*/ + +#if LCD_BPP == LCD_COLOR8 +void +lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = &(immr->im_cpm); + unsigned short colreg, *cmap_ptr; + + cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; + + colreg = ((red & 0x0F) << 8) | + ((green & 0x0F) << 4) | + (blue & 0x0F) ; +#ifdef CFG_INVERT_COLORS + colreg ^= 0x0FFF; +#endif + *cmap_ptr = colreg; + + debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n", + regno, &(cp->lcd_cmap[regno * 2]), + red, green, blue, + cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]); +} +#endif /* LCD_COLOR8 */ + +/*----------------------------------------------------------------------*/ + +#if LCD_BPP == LCD_MONOCHROME +static +void lcd_initcolregs (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = &(immr->im_cpm); + ushort regno; + + for (regno = 0; regno < 16; regno++) { + cp->lcd_cmap[regno * 2] = 0; + cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f; + } +} +#endif + +/*----------------------------------------------------------------------*/ + +void lcd_enable (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile lcd823_t *lcdp = &immr->im_lcd; + + /* Enable the LCD panel */ +#ifndef CONFIG_RBC823 + immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ +#endif + lcdp->lcd_lccr |= LCCR_PON; + +#ifdef CONFIG_V37 + /* Turn on display backlight */ + immr->im_cpm.cp_pbpar |= 0x00008000; + immr->im_cpm.cp_pbdir |= 0x00008000; +#elif defined(CONFIG_RBC823) + /* Turn on display backlight */ + immr->im_cpm.cp_pbdat |= 0x00004000; +#endif + +#if defined(CONFIG_LWMON) + { uchar c = pic_read (0x60); +#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CFG_POST_SYSMON) + /* Enable LCD later in sysmon test, only if temperature is OK */ +#else + c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */ +#endif + pic_write (0x60, c); + } +#endif /* CONFIG_LWMON */ + +#if defined(CONFIG_R360MPI) + { + extern void r360_i2c_lcd_write (uchar data0, uchar data1); + unsigned long bgi, ctr; + char *p; + + if ((p = getenv("lcdbgi")) != NULL) { + bgi = simple_strtoul (p, 0, 10) & 0xFFF; + } else { + bgi = 0xFFF; + } + + if ((p = getenv("lcdctr")) != NULL) { + ctr = simple_strtoul (p, 0, 10) & 0xFFF; + } else { + ctr=0x7FF; + } + + r360_i2c_lcd_write(0x10, 0x01); + r360_i2c_lcd_write(0x20, 0x01); + r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF); + r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF); + } +#endif /* CONFIG_R360MPI */ +#ifdef CONFIG_RBC823 + udelay(200000); /* wait 200ms */ + /* Turn VEE_ON first */ + immr->im_cpm.cp_pbdat |= 0x00000001; + udelay(200000); /* wait 200ms */ + /* Now turn on LCD_ON */ + immr->im_cpm.cp_pbdat |= 0x00001000; +#endif +#ifdef CONFIG_RRVISION + debug ("PC4->Output(1): enable LVDS\n"); + debug ("PC5->Output(0): disable PAL clock\n"); + immr->im_ioport.iop_pddir |= 0x1000; + immr->im_ioport.iop_pcpar &= ~(0x0C00); + immr->im_ioport.iop_pcdir |= 0x0C00 ; + immr->im_ioport.iop_pcdat |= 0x0800 ; + immr->im_ioport.iop_pcdat &= ~(0x0400); + debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", + immr->im_ioport.iop_pdpar, + immr->im_ioport.iop_pddir, + immr->im_ioport.iop_pddat); + debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", + immr->im_ioport.iop_pcpar, + immr->im_ioport.iop_pcdir, + immr->im_ioport.iop_pcdat); +#endif +} + +/*----------------------------------------------------------------------*/ + +#if defined (CONFIG_RBC823) +void lcd_disable (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile lcd823_t *lcdp = &immr->im_lcd; + +#if defined(CONFIG_LWMON) + { uchar c = pic_read (0x60); + c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */ + pic_write (0x60, c); + } +#elif defined(CONFIG_R360MPI) + { + extern void r360_i2c_lcd_write (uchar data0, uchar data1); + + r360_i2c_lcd_write(0x10, 0x00); + r360_i2c_lcd_write(0x20, 0x00); + r360_i2c_lcd_write(0x30, 0x00); + r360_i2c_lcd_write(0x40, 0x00); + } +#endif /* CONFIG_LWMON */ + /* Disable the LCD panel */ + lcdp->lcd_lccr &= ~LCCR_PON; +#ifdef CONFIG_RBC823 + /* Turn off display backlight, VEE and LCD_ON */ + immr->im_cpm.cp_pbdat &= ~0x00005001; +#else + immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */ +#endif /* CONFIG_RBC823 */ +} +#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */ + + +/************************************************************************/ + +#endif /* CONFIG_LCD */ diff --git a/cpu/mpc8xx/plprcr_write.S b/cpu/mpc8xx/plprcr_write.S new file mode 100644 index 0000000..e325671 --- /dev/null +++ b/cpu/mpc8xx/plprcr_write.S @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define CACHE_CMD_ENABLE 0x02000000 +#define CACHE_CMD_DISABLE 0x04000000 +#define CACHE_CMD_LOAD_LOCK 0x06000000 +#define CACHE_CMD_UNLOCK_LINE 0x08000000 +#define CACHE_CMD_UNLOCK_ALL 0x0A000000 +#define CACHE_CMD_INVALIDATE 0x0C000000 +#define SPEED_PLPRCR_WAIT_5CYC 150 +#define _CACHE_ALIGN_SIZE 16 + + + .text + .align 2 + .globl plprcr_write_866 + +/* + * void plprcr_write_866 (long plprcr) + * Write PLPRCR, including workaround for device errata SIU4 and SIU9. + */ + +plprcr_write_866: + mfspr r10, LR /* save the Link Register value */ + + /* turn instruction cache on (no MMU required for instructions) + */ + lis r4, CACHE_CMD_ENABLE@h + ori r4, r4, CACHE_CMD_ENABLE@l + mtspr IC_CST, r4 + isync + + /* clear IC_CST error bits + */ + mfspr r4, IC_CST + + bl plprcr_here + +plprcr_here: + mflr r5 + + /* calculate relocation offset + */ + lis r4, plprcr_here@h + ori r4, r4, plprcr_here@l + sub r5, r5, r4 + + /* calculate first address of this function + */ + lis r6, plprcr_write_866@h + ori r6, r6, plprcr_write_866@l + add r6, r6, r5 + + /* calculate end address of this function + */ + lis r7, plprcr_end@h + ori r7, r7, plprcr_end@l + add r7, r7, r5 + + /* load and lock code addresses + */ + mr r5, r6 + +plprcr_loop: + mtspr IC_ADR, r5 + addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */ + + lis r4, CACHE_CMD_LOAD_LOCK@h + ori r4, r4, CACHE_CMD_LOAD_LOCK@l + mtspr IC_CST, r4 + isync + + cmpw r5, r7 + blt plprcr_loop + + /* IC_CST error bits not evaluated + */ + + /* switch PLPRCR + */ + mfspr r4, IMMR /* read IMMR */ + rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */ + + /* write sequence according to MPC866 Errata + */ + stw r3, PLPRCR(r4) + isync + + lis r3, SPEED_PLPRCR_WAIT_5CYC@h + ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l + +plprcr_wait: + cmpwi r3, 0 + beq plprcr_wait_end + nop + subi r3, r3, 1 + b plprcr_wait + +plprcr_wait_end: + + /* unlock instruction cache but leave it enabled + */ + lis r4, CACHE_CMD_UNLOCK_ALL@h + ori r4, r4, CACHE_CMD_UNLOCK_ALL@l + mtspr IC_CST, r4 + isync + + mtspr LR, r10 /* restore original Link Register value */ + blr + +plprcr_end: diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c new file mode 100644 index 0000000..6b9110f --- /dev/null +++ b/cpu/mpc8xx/scc.c @@ -0,0 +1,570 @@ +/* + * File: scc.c + * Description: + * Basic ET HW initialization and packet RX/TX routines + * + * NOTE <<>>: + * Do not cache Rx/Tx buffers! + */ + +/* + * MPC823 <-> MC68160 Connections: + * + * Setup MPC823 to work with MC68160 Enhanced Ethernet + * Serial Tranceiver as follows: + * + * MPC823 Signal MC68160 Comments + * ------ ------ ------- -------- + * PA-12 ETHTX --------> TX Eth. Port Transmit Data + * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable + * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock + * PA-13 ETHRX <-------- RX Eth. Port Receive Data + * PC-8 E_RENA <-------- RENA Eth. Receive Enable + * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock + * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication + * + * FADS Board Signal MC68160 Comments + * ----------------- ------- -------- + * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable + * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable + * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex + * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back + * + */ + +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET) + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +#define TOUT_LOOP 10000 /* 10 ms to have a packet sent */ + +static char txbuf[DBUF_LENGTH]; + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * SCC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +typedef volatile struct CommonBufferDescriptor { + cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ + cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ +} RTXBD; + +static RTXBD *rtx; + +static int scc_send(struct eth_device* dev, volatile void *packet, int length); +static int scc_recv(struct eth_device* dev); +static int scc_init (struct eth_device* dev, bd_t * bd); +static void scc_halt(struct eth_device* dev); + +int scc_initialize(bd_t *bis) +{ + struct eth_device* dev; + + dev = (struct eth_device*) malloc(sizeof *dev); + memset(dev, 0, sizeof *dev); + + sprintf(dev->name, "SCC ETHERNET"); + dev->iobase = 0; + dev->priv = 0; + dev->init = scc_init; + dev->halt = scc_halt; + dev->send = scc_send; + dev->recv = scc_recv; + + eth_register(dev); + + return 1; +} + +static int scc_send(struct eth_device* dev, volatile void *packet, int length) +{ + int i, j=0; +#if 0 + volatile char *in, *out; +#endif + + /* section 16.9.23.3 + * Wait for ready + */ +#if 0 + while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY); + out = (char *)(rtx->txbd[txIdx].cbd_bufaddr); + in = packet; + for(i = 0; i < length; i++) { + *out++ = *in++; + } + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST); + while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++; + +#ifdef ET_DEBUG + printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); +#endif + i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; + + /* wrap around buffer index when necessary */ + if (txIdx >= TX_BUF_CNT) txIdx = 0; +#endif + + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX not ready\n"); + rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP); + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX timeout\n"); +#ifdef ET_DEBUG + printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); +#endif + i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; + return i; +} + +static int scc_recv (struct eth_device *dev) +{ + int length; + + for (;;) { + /* section 16.9.23.2 */ + if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = rtx->rxbd[rxIdx].cbd_datlen; + + if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { +#ifdef ET_DEBUG + printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); +#endif + } else { + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[rxIdx], length - 4); + } + + + /* Give the buffer back to the SCC. */ + rtx->rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx->rxbd[PKTBUFSRX - 1].cbd_sc = + (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } else { + rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + } + return length; +} + +/************************************************************** + * + * SCC Ethernet Initialization Routine + * + *************************************************************/ + +static int scc_init (struct eth_device *dev, bd_t * bis) +{ + + int i; + scc_enet_t *pram_ptr; + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + +#if defined(CONFIG_LWMON) + reset_phy(); +#endif + +#ifdef CONFIG_FADS +#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T) + /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */ + *((uint *) BCSR4) &= ~BCSR4_ETHLOOP; + *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL; + *((uint *) BCSR1) &= ~BCSR1_ETHEN; +#else + *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN); + *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE; + *((uint *) BCSR1) &= ~BCSR1_ETHEN; +#endif +#endif + + pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]); + + rxIdx = 0; + txIdx = 0; + +#ifdef CFG_ALLOC_DPRAM + rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + + dpram_alloc_align (sizeof (RTXBD), 8)); +#else + rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); +#endif /* 0 */ + +#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) + /* Configure port A pins for Txd and Rxd. + */ + immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); + immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); + immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; +#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) + /* Configure port B pins for Txd and Rxd. + */ + immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); + immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); + immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; +#else +#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined +#endif + +#if defined(PC_ENET_LBK) + /* Configure port C pins to disable External Loopback + */ + immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; + immr->im_ioport.iop_pcdir |= PC_ENET_LBK; + immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; + immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ +#endif /* PC_ENET_LBK */ + + /* Configure port C pins to enable CLSN and RENA. + */ + immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); + immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); + immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); + + /* Configure port A for TCLK and RCLK. + */ + immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); + immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); + + /* + * Configure Serial Interface clock routing -- see section 16.7.5.3 + * First, clear all SCC bits to zero, then set the ones we want. + */ + + immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; + immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; + + + /* + * Initialize SDCR -- see section 16.9.23.7 + * SDMA configuration register + */ + immr->im_siu_conf.sc_sdcr = 0x01; + + + /* + * Setup SCC Ethernet Parameter RAM + */ + + pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ + pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ + + pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ + + pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ + pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ + + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + + for (i = 0; i < PKTBUFSRX; i++) { + rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx->rxbd[i].cbd_datlen = 0; /* Reset */ + rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + + rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Add PADs to Short FRAMES, Wrap, Last, Tx CRC + */ + + for (i = 0; i < TX_BUF_CNT; i++) { + rtx->txbd[i].cbd_sc = + (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); + rtx->txbd[i].cbd_datlen = 0; /* Reset */ + rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); + } + + rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* + * Enter Command: Initialize Rx Params for SCC + */ + + do { /* Spin until ready to issue command */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + /* Issue command */ + immr->im_cpm.cp_cpcr = + ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); + do { /* Spin until command processed */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + + /* + * Ethernet Specific Parameter RAM + * see table 13-16, pg. 660, + * pg. 681 (example with suggested settings) + */ + + pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ + pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ + pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ + pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ + pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ + pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ + + pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ + pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ + pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ + + pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ + pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ + + pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ + pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ + pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ + pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ + +#define ea eth_get_dev()->enetaddr + pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; + pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; + pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; +#undef ea + + pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ + pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ + pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ + pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ + pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ + pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ + pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ + pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ + + /* + * Enter Command: Initialize Tx Params for SCC + */ + + do { /* Spin until ready to issue command */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + /* Issue command */ + immr->im_cpm.cp_cpcr = + ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); + do { /* Spin until command processed */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + + /* + * Mask all Events in SCCM - we use polling mode + */ + immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0; + + /* + * Clear Events in SCCE -- Clear bits by writing 1's + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0); + + + /* + * Initialize GSMR High 32-Bits + * Settings: Normal Mode + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0; + + /* + * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive + * Settings: + * TCI = Invert + * TPL = 48 bits + * TPP = Repeating 10's + * MODE = Ethernet + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI | + SCC_GSMRL_TPL_48 | + SCC_GSMRL_TPP_10 | + SCC_GSMRL_MODE_ENET); + + /* + * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555; + + /* + * Initialize the PSMR + * Settings: + * CRC = 32-Bit CCITT + * NIB = Begin searching for SFD 22 bits after RENA + * FDE = Full Duplex Enable + * LPB = Loopback Enable (Needed when FDE is set) + * BRO = Reject broadcast packets + * PROMISCOUS = Catch all packets regardless of dest. MAC adress + */ + immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC | + SCC_PSMR_NIB22 | +#if defined(CONFIG_SCC_ENET_FULL_DUPLEX) + SCC_PSMR_FDE | SCC_PSMR_LPB | +#endif +#if defined(CONFIG_SCC_ENET_NO_BROADCAST) + SCC_PSMR_BRO | +#endif +#if defined(CONFIG_SCC_ENET_PROMISCOUS) + SCC_PSMR_PRO | +#endif + 0; + + /* + * Configure Ethernet TENA Signal + */ + +#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) + immr->im_ioport.iop_pcpar |= PC_ENET_TENA; + immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; +#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) + immr->im_cpm.cp_pbpar |= PB_ENET_TENA; + immr->im_cpm.cp_pbdir |= PB_ENET_TENA; +#else +#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined +#endif + +#if defined(CONFIG_ADS) && defined(CONFIG_MPC860) + /* + * Port C is used to control the PHY,MC68160. + */ + immr->im_ioport.iop_pcdir |= + (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); + + immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; + immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); + *((uint *) BCSR1) &= ~BCSR1_ETHEN; +#endif /* MPC860ADS */ + +#if defined(CONFIG_AMX860) + /* + * Port B is used to control the PHY,MC68160. + */ + immr->im_cpm.cp_pbdir |= + (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL); + + immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL; + immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL); + + immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN; + immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN; +#endif /* AMX860 */ + +#ifdef CONFIG_RPXCLASSIC + *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; + *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); +#endif + +#ifdef CONFIG_RPXLITE + *((uchar *) BCSR0) |= BCSR0_ETHEN; +#endif + +#if defined(CONFIG_QS860T) + /* + * PB27=FDE-, set output low for full duplex + * PB26=Link Test Enable, normally high output + */ + immr->im_cpm.cp_pbdir |= 0x00000030; + immr->im_cpm.cp_pbdat |= 0x00000020; + immr->im_cpm.cp_pbdat &= ~0x00000010; +#endif /* QS860T */ + +#ifdef CONFIG_MBX + board_ether_init (); +#endif + +#if defined(CONFIG_NETVIA) +#if defined(PA_ENET_PDN) + immr->im_ioport.iop_papar &= ~PA_ENET_PDN; + immr->im_ioport.iop_padir |= PA_ENET_PDN; + immr->im_ioport.iop_padat |= PA_ENET_PDN; +#elif defined(PB_ENET_PDN) + immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN; + immr->im_cpm.cp_pbdir |= PB_ENET_PDN; + immr->im_cpm.cp_pbdat |= PB_ENET_PDN; +#elif defined(PC_ENET_PDN) + immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN; + immr->im_ioport.iop_pcdir |= PC_ENET_PDN; + immr->im_ioport.iop_pcdat |= PC_ENET_PDN; +#elif defined(PD_ENET_PDN) + immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN; + immr->im_ioport.iop_pddir |= PD_ENET_PDN; + immr->im_ioport.iop_pddat |= PD_ENET_PDN; +#endif +#endif + + /* + * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive + */ + + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= + (SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + /* + * Work around transmit problem with first eth packet + */ +#if defined (CONFIG_FADS) + udelay (10000); /* wait 10 ms */ +#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC) + udelay (100000); /* wait 100 ms */ +#endif + + return 1; +} + + +static void scc_halt (struct eth_device *dev) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= + ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); +} + +#if 0 +void restart (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= + (SCC_GSMRL_ENR | SCC_GSMRL_ENT); +} +#endif +#endif /* CFG_CMD_NET, SCC_ENET */ diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c new file mode 100644 index 0000000..fa0405f --- /dev/null +++ b/cpu/mpc8xx/serial.c @@ -0,0 +1,722 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ + +#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ +#define SMC_INDEX 0 +#define PROFF_SMC PROFF_SMC1 +#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 + +#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ +#define SMC_INDEX 1 +#define PROFF_SMC PROFF_SMC2 +#define CPM_CR_CH_SMC CPM_CR_CH_SMC2 + +#endif /* CONFIG_8xx_CONS_SMCx */ + +#if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */ +#define SCC_INDEX 0 +#define PROFF_SCC PROFF_SCC1 +#define CPM_CR_CH_SCC CPM_CR_CH_SCC1 + +#elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */ +#define SCC_INDEX 1 +#define PROFF_SCC PROFF_SCC2 +#define CPM_CR_CH_SCC CPM_CR_CH_SCC2 + +#elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */ +#define SCC_INDEX 2 +#define PROFF_SCC PROFF_SCC3 +#define CPM_CR_CH_SCC CPM_CR_CH_SCC3 + +#elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */ +#define SCC_INDEX 3 +#define PROFF_SCC PROFF_SCC4 +#define CPM_CR_CH_SCC CPM_CR_CH_SCC4 + +#endif /* CONFIG_8xx_CONS_SCCx */ + +static void serial_setdivisor(volatile cpm8xx_t *cp) +{ + DECLARE_GLOBAL_DATA_PTR; + int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; + + if(divisor/16>0x1000) { + /* bad divisor, assume 50Mhz clock and 9600 baud */ + divisor=(50*1000*1000 + 8*9600)/16/9600; + } + +#ifdef CFG_BRGCLK_PRESCALE + divisor /= CFG_BRGCLK_PRESCALE; +#endif + + if(divisor<=0x1000) { + cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN; + } else { + cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16; + } +} + +#if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2)) + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +static void smc_setbrg (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + + /* Set up the baud rate generator. + * See 8xx_io/commproc.c for details. + * + * Wire BRG1 to SMCx + */ + + cp->cp_simode = 0x00000000; + + serial_setdivisor(cp); +} + +static int smc_init (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile smc_t *sp; + volatile smc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile cpm8xx_t *cp = &(im->im_cpm); +#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850)) + volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); +#endif + uint dpaddr; + + /* initialize pointers to SMC */ + + sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); + up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; + + /* Disable transmitter/receiver. + */ + sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); + + /* Enable SDMA. + */ + im->im_siu_conf.sc_sdcr = 1; + + /* clear error conditions */ +#ifdef CFG_SDSR + im->im_sdma.sdma_sdsr = CFG_SDSR; +#else + im->im_sdma.sdma_sdsr = 0x83; +#endif + + /* clear SDMA interrupt mask */ +#ifdef CFG_SDMR + im->im_sdma.sdma_sdmr = CFG_SDMR; +#else + im->im_sdma.sdma_sdmr = 0x00; +#endif + +#if defined(CONFIG_8xx_CONS_SMC1) + /* Use Port B for SMC1 instead of other functions. + */ + cp->cp_pbpar |= 0x000000c0; + cp->cp_pbdir &= ~0x000000c0; + cp->cp_pbodr &= ~0x000000c0; +#else /* CONFIG_8xx_CONS_SMC2 */ +# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850) + /* Use Port A for SMC2 instead of other functions. + */ + ip->iop_papar |= 0x00c0; + ip->iop_padir &= ~0x00c0; + ip->iop_paodr &= ~0x00c0; +# else /* must be a 860 then */ + /* Use Port B for SMC2 instead of other functions. + */ + cp->cp_pbpar |= 0x00000c00; + cp->cp_pbdir &= ~0x00000c00; + cp->cp_pbodr &= ~0x00000c00; +# endif +#endif + +#if defined(CONFIG_FADS) || defined(CONFIG_ADS) + /* Enable RS232 */ +#if defined(CONFIG_8xx_CONS_SMC1) + *((uint *) BCSR1) &= ~BCSR1_RS232EN_1; +#else + *((uint *) BCSR1) &= ~BCSR1_RS232EN_2; +#endif +#endif /* CONFIG_FADS */ + +#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) + /* Enable Monitor Port Transceiver */ + *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; +#endif /* CONFIG_RPXLITE */ + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + +#ifdef CFG_ALLOC_DPRAM + dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; +#else + dpaddr = CPM_SERIAL_BASE ; +#endif + + /* Allocate space for two buffer descriptors in the DP ram. + * For now, this address seems OK, but it may have to + * change with newer versions of the firmware. + * damm: allocating space after the two buffers for rx/tx data + */ + + rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; + rbdf->cbd_bufaddr = (uint) (rbdf+2); + rbdf->cbd_sc = 0; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; + tbdf->cbd_sc = 0; + + /* Set up the uart parameters in the parameter ram. + */ + up->smc_rbase = dpaddr; + up->smc_tbase = dpaddr+sizeof(cbd_t); + up->smc_rfcr = SMC_EB; + up->smc_tfcr = SMC_EB; + +#if defined(CONFIG_MBX) + board_serial_init(); +#endif /* CONFIG_MBX */ + + /* Set UART mode, 8 bit, no parity, one stop. + * Enable receive and transmit. + */ + sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; + + /* Mask all interrupts and remove anything pending. + */ + sp->smc_smcm = 0; + sp->smc_smce = 0xff; + + /* Set up the baud rate generator. + */ + smc_setbrg (); + + /* Make the first buffer the only buffer. + */ + tbdf->cbd_sc |= BD_SC_WRAP; + rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + + /* Single character receive. + */ + up->smc_mrblr = 1; + up->smc_maxidl = 0; + + /* Initialize Tx/Rx parameters. + */ + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. + */ + sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; + + return (0); +} + +static void +smc_putc(const char c) +{ + volatile cbd_t *tbdf; + volatile char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + +#ifdef CONFIG_MODEM_SUPPORT + DECLARE_GLOBAL_DATA_PTR; + + if (gd->be_quiet) + return; +#endif + + if (c == '\n') + smc_putc ('\r'); + + up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; + + tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; + + /* Wait for last character to go. + */ + + buf = (char *)tbdf->cbd_bufaddr; + + *buf = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; + __asm__("eieio"); + + while (tbdf->cbd_sc & BD_SC_READY) { + WATCHDOG_RESET (); + __asm__("eieio"); + } +} + +static void +smc_puts (const char *s) +{ + while (*s) { + smc_putc (*s++); + } +} + +static int +smc_getc(void) +{ + volatile cbd_t *rbdf; + volatile unsigned char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + unsigned char c; + + up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; + + rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; + + /* Wait for character to show up. + */ + buf = (unsigned char *)rbdf->cbd_bufaddr; + + while (rbdf->cbd_sc & BD_SC_EMPTY) + WATCHDOG_RESET (); + + c = *buf; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return(c); +} + +static int +smc_tstc(void) +{ + volatile cbd_t *rbdf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + + up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; + + rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; + + return(!(rbdf->cbd_sc & BD_SC_EMPTY)); +} + +struct serial_device serial_smc_device = +{ + "serial_smc", + "SMC", + smc_init, + smc_setbrg, + smc_getc, + smc_tstc, + smc_putc, + smc_puts, +}; + +#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */ + +#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ + defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) + +static void +scc_setbrg (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + + /* Set up the baud rate generator. + * See 8xx_io/commproc.c for details. + * + * Wire BRG1 to SCCx + */ + + cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX)); + + serial_setdivisor(cp); +} + +static int scc_init (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile scc_t *sp; + volatile scc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile cpm8xx_t *cp = &(im->im_cpm); + uint dpaddr; +#if (SCC_INDEX != 2) || !defined(CONFIG_MPC850) + volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); +#endif + + /* initialize pointers to SCC */ + + sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]); + up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC]; + +#if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2) + { /* Disable Ethernet, enable Serial */ + uchar c; + + c = pic_read (0x61); + c &= ~0x40; /* enable COM3 */ + c |= 0x80; /* disable Ethernet */ + pic_write (0x61, c); + + /* enable RTS2 */ + cp->cp_pbpar |= 0x2000; + cp->cp_pbdat |= 0x2000; + cp->cp_pbdir |= 0x2000; + } +#endif /* CONFIG_LWMON */ + + /* Disable transmitter/receiver. + */ + sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + +#if (SCC_INDEX == 2) && defined(CONFIG_MPC850) + /* + * The MPC850 has SCC3 on Port B + */ + cp->cp_pbpar |= 0x06; + cp->cp_pbdir &= ~0x06; + cp->cp_pbodr &= ~0x06; + +#elif (SCC_INDEX < 2) || !defined(CONFIG_IP860) + /* + * Standard configuration for SCC's is on Part A + */ + ip->iop_papar |= ((3 << (2 * SCC_INDEX))); + ip->iop_padir &= ~((3 << (2 * SCC_INDEX))); + ip->iop_paodr &= ~((3 << (2 * SCC_INDEX))); +#else + /* + * The IP860 has SCC3 and SCC4 on Port D + */ + ip->iop_pdpar |= ((3 << (2 * SCC_INDEX))); +#endif + + /* Allocate space for two buffer descriptors in the DP ram. + */ + +#ifdef CFG_ALLOC_DPRAM + dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; +#else + dpaddr = CPM_SERIAL2_BASE ; +#endif + + /* Enable SDMA. + */ + im->im_siu_conf.sc_sdcr = 0x0001; + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + + rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; + rbdf->cbd_bufaddr = (uint) (rbdf+2); + rbdf->cbd_sc = 0; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; + tbdf->cbd_sc = 0; + + /* Set up the baud rate generator. + */ + scc_setbrg (); + + /* Set up the uart parameters in the parameter ram. + */ + up->scc_genscc.scc_rbase = dpaddr; + up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); + + /* Initialize Tx/Rx parameters. + */ + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + up->scc_genscc.scc_rfcr = SCC_EB | 0x05; + up->scc_genscc.scc_tfcr = SCC_EB | 0x05; + + up->scc_genscc.scc_mrblr = 1; /* Single character receive */ + up->scc_maxidl = 0; /* disable max idle */ + up->scc_brkcr = 1; /* send one break character on stop TX */ + up->scc_parec = 0; + up->scc_frmec = 0; + up->scc_nosec = 0; + up->scc_brkec = 0; + up->scc_uaddr1 = 0; + up->scc_uaddr2 = 0; + up->scc_toseq = 0; + up->scc_char1 = 0x8000; + up->scc_char2 = 0x8000; + up->scc_char3 = 0x8000; + up->scc_char4 = 0x8000; + up->scc_char5 = 0x8000; + up->scc_char6 = 0x8000; + up->scc_char7 = 0x8000; + up->scc_char8 = 0x8000; + up->scc_rccm = 0xc0ff; + + /* Set low latency / small fifo. + */ + sp->scc_gsmrh = SCC_GSMRH_RFW; + + /* Set SCC(x) clock mode to 16x + * See 8xx_io/commproc.c for details. + * + * Wire BRG1 to SCCn + */ + + /* Set UART mode, clock divider 16 on Tx and Rx + */ + sp->scc_gsmrl &= ~0xF; + sp->scc_gsmrl |= + (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); + + sp->scc_psmr = 0; + sp->scc_psmr |= SCU_PSMR_CL; + + /* Mask all interrupts and remove anything pending. + */ + sp->scc_sccm = 0; + sp->scc_scce = 0xffff; + sp->scc_dsr = 0x7e7e; + sp->scc_psmr = 0x3000; + + /* Make the first buffer the only buffer. + */ + tbdf->cbd_sc |= BD_SC_WRAP; + rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + + /* Enable transmitter/receiver. + */ + sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + return (0); +} + +static void +scc_putc(const char c) +{ + volatile cbd_t *tbdf; + volatile char *buf; + volatile scc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + +#ifdef CONFIG_MODEM_SUPPORT + DECLARE_GLOBAL_DATA_PTR; + + if (gd->be_quiet) + return; +#endif + + if (c == '\n') + scc_putc ('\r'); + + up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; + + tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; + + /* Wait for last character to go. + */ + + buf = (char *)tbdf->cbd_bufaddr; + + *buf = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; + __asm__("eieio"); + + while (tbdf->cbd_sc & BD_SC_READY) { + __asm__("eieio"); + WATCHDOG_RESET (); + } +} + +static void +scc_puts (const char *s) +{ + while (*s) { + scc_putc (*s++); + } +} + +static int +scc_getc(void) +{ + volatile cbd_t *rbdf; + volatile unsigned char *buf; + volatile scc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + unsigned char c; + + up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; + + rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; + + /* Wait for character to show up. + */ + buf = (unsigned char *)rbdf->cbd_bufaddr; + + while (rbdf->cbd_sc & BD_SC_EMPTY) + WATCHDOG_RESET (); + + c = *buf; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return(c); +} + +static int +scc_tstc(void) +{ + volatile cbd_t *rbdf; + volatile scc_uart_t *up; + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + + up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; + + rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; + + return(!(rbdf->cbd_sc & BD_SC_EMPTY)); +} + +struct serial_device serial_scc_device = +{ + "serial_scc", + "SCC", + scc_init, + scc_setbrg, + scc_getc, + scc_tstc, + scc_putc, + scc_puts, +}; + +#endif /* CONFIG_8xx_CONS_SCCx */ + +#ifdef CONFIG_MODEM_SUPPORT +void disable_putc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->be_quiet = 1; +} + +void enable_putc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->be_quiet = 0; +} +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + +void +kgdb_serial_init(void) +{ + int i = -1; + + if (strcmp(default_serial_console()->ctlr, "SMC") == 0) + { +#if defined(CONFIG_8xx_CONS_SMC1) + i = 1; +#elif defined(CONFIG_8xx_CONS_SMC2) + i = 2; +#endif + } + else if (strcmp(default_serial_console()->ctlr, "SMC") == 0) + { +#if defined(CONFIG_8xx_CONS_SCC1) + i = 1; +#elif defined(CONFIG_8xx_CONS_SCC2) + i = 2; +#elif defined(CONFIG_8xx_CONS_SCC3) + i = 3; +#elif defined(CONFIG_8xx_CONS_SCC4) + i = 4; +#endif + } + + if (i >= 0) + { + serial_printf("[on %s%d] ", default_serial_console()->ctlr, i); + } +} + +void +putDebugChar (int c) +{ + serial_putc (c); +} + +void +putDebugStr (const char *str) +{ + serial_puts (str); +} + +int +getDebugChar (void) +{ + return serial_getc(); +} + +void +kgdb_interruptible (int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ + +#endif /* CONFIG_8xx_CONS_NONE */ diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c new file mode 100644 index 0000000..f038316 --- /dev/null +++ b/cpu/mpc8xx/speed.c @@ -0,0 +1,395 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG) + +#define PITC_SHIFT 16 +#define PITR_SHIFT 16 +/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */ +#define SPEED_PIT_COUNTS 58 +#define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT) +#define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT) + +/* Access functions for the Machine State Register */ +static __inline__ unsigned long get_msr(void) +{ + unsigned long msr; + + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr(unsigned long msr) +{ + asm volatile("mtmsr %0" : : "r" (msr)); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Measure CPU clock speed (core clock GCLK1, GCLK2), + * also determine bus clock speed (checking bus divider factor) + * + * (Approx. GCLK frequency in Hz) + * + * Initializes timer 2 and PIT, but disables them before return. + * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4] + * + * When measuring the CPU clock against the PIT, we count cpu clocks + * for 58/8192 seconds with a prescale divide by 177 for the cpu clock. + * These strange values for the timing interval and prescaling are used + * because the formula for the CPU clock is: + * + * CPU clock = count * (177 * (8192 / 58)) + * + * = count * 24999.7241 + * + * which is very close to + * + * = count * 25000 + * + * Since the count gives the CPU clock divided by 25000, we can get + * the CPU clock rounded to the nearest 0.1 MHz by + * + * CPU clock = ((count + 2) / 4) * 100000; + * + * The rounding is important since the measurement is sometimes going + * to be high or low by 0.025 MHz, depending on exactly how the clocks + * and counters interact. By rounding we get the exact answer for any + * CPU clock that is an even multiple of 0.1 MHz. + */ + +unsigned long measure_gclk(void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer; + ulong timer2_val; + ulong msr_val; + +#ifdef CFG_8XX_XIN + /* dont use OSCM, only use EXTCLK/512 */ + immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV; +#else + immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV); +#endif + + /* Reset + Stop Timer 2, no cascading + */ + timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2); + + /* Keep stopped, halt in debug mode + */ + timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2); + + /* Timer 2 setup: + * Output ref. interrupt disable, int. clock + * Prescale by 177. Note that prescaler divides by value + 1 + * so we must subtract 1 here. + */ + timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN; + + timerp->cpmt_tcn2 = 0; /* reset state */ + timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */ + + /* + * PIT setup: + * + * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz), + * so the count value would be SPEED_PITC_COUNTS - 1. + * But there would be an uncertainty in the start time of 1/4 + * count since when we enable the PIT the count is not + * synchronized to the 32768 Hz oscillator. The trick here is + * to start the count higher and wait until the PIT count + * changes to the required value before starting timer 2. + * + * One count high should be enough, but occasionally the start + * is off by 1 or 2 counts of 32768 Hz. With the start value + * set two counts high it seems very reliable. + */ + + immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */ + immr->im_sit.sit_pitc = SPEED_PITC_INIT; + + immr->im_sitk.sitk_piscrk = KAPWR_KEY; + immr->im_sit.sit_piscr = CFG_PISCR; + + /* + * Start measurement - disable interrupts, just in case + */ + msr_val = get_msr (); + set_msr (msr_val & ~MSR_EE); + + immr->im_sit.sit_piscr |= PISCR_PTE; + + /* spin until get exact count when we want to start */ + while (immr->im_sit.sit_pitr > SPEED_PITC); + + timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */ + while ((immr->im_sit.sit_piscr & PISCR_PS) == 0); + timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */ + + /* re-enable external interrupts if they were on */ + set_msr (msr_val); + + /* Disable timer and PIT + */ + timer2_val = timerp->cpmt_tcn2; /* save before reset timer */ + + timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2); + immr->im_sit.sit_piscr &= ~PISCR_PTE; + +#if defined(CFG_8XX_XIN) + /* not using OSCM, using XIN, so scale appropriately */ + return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L; +#else + return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */ +#endif +} + +#endif + +#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) + +/* + * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ + * or (if it is not defined) measure_gclk() (which uses the ref clock) + * from above. + */ +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uint immr = get_immr (0); /* Return full IMMR contents */ + volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); + uint sccr = immap->im_clkrst.car_sccr; + /* + * If for some reason measuring the gclk frequency won't + * work, we return the hardwired value. + * (For example, the cogent CMA286-60 CPU module has no + * separate oscillator for PITRTCLK) + */ +#if defined(CONFIG_8xx_GCLK_FREQ) + gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; +#elif defined(CONFIG_8xx_OSCLK) +#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) + uint pll = immap->im_clkrst.car_plprcr; + uint clk; + + if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ + clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) * + (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) / + (1<cpu_clk = clk / (2 << ((sccr >> 8) & 7)); + } else { /* High frequency division factor is used */ + gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7)); + } +#else + gd->cpu_clk = measure_gclk(); +#endif /* CONFIG_8xx_GCLK_FREQ */ + + if ((sccr & SCCR_EBDF11) == 0) { + /* No Bus Divider active */ + gd->bus_clk = gd->cpu_clk; + } else { + /* The MPC8xx has only one BDF: half clock speed */ + gd->bus_clk = gd->cpu_clk / 2; + } + + return (0); +} + +#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */ + +static long init_pll_866 (long clk); + +/* This function sets up PLL (init_pll_866() is called) and + * fills gd->cpu_clk and gd->bus_clk according to the environment + * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk' + * contains invalid value). + * This functions requires an MPC866 or newer series CPU. + */ +int get_clocks_866 (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + char tmp[64]; + long cpuclk = 0; + long sccr_reg; + + if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) + cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; + + if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk)) + cpuclk = CONFIG_8xx_CPUCLK_DEFAULT; + + gd->cpu_clk = init_pll_866 (cpuclk); +#if defined(CFG_MEASURE_CPUCLK) + gd->cpu_clk = measure_gclk (); +#endif + + /* if cpu clock <= 66 MHz then set bus division factor to 1, + * otherwise set it to 2 + */ + sccr_reg = immr->im_clkrst.car_sccr; + sccr_reg &= ~SCCR_EBDF11; + if (gd->cpu_clk <= 66000000) { + sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ + gd->bus_clk = gd->cpu_clk; + } else { + sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */ + gd->bus_clk = gd->cpu_clk / 2; + } + immr->im_clkrst.car_sccr = sccr_reg; + + return (0); +} + +/* Adjust sdram refresh rate to actual CPU clock. + */ +int sdram_adjust_866 (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + long mamr; + + mamr = immr->im_memctl.memc_mamr; + mamr &= ~MAMR_PTA_MSK; + mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT); + immr->im_memctl.memc_mamr = mamr; + + return (0); +} + +/* Configure PLL for MPC866/859/885 CPU series + * PLL multiplication factor is set to the value nearest to the desired clk, + * assuming a oscclk of 10 MHz. + */ +static long init_pll_866 (long clk) +{ + extern void plprcr_write_866 (long); + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + long n, plprcr; + char mfi, mfn, mfd, s, pdf; + long step_mfi, step_mfn; + + if (clk < 20000000) { + clk *= 2; + pdf = 1; + } else { + pdf = 0; + } + + if (clk < 40000000) { + s = 2; + step_mfi = CONFIG_8xx_OSCLK / 4; + mfd = 7; + step_mfn = CONFIG_8xx_OSCLK / 30; + } else if (clk < 80000000) { + s = 1; + step_mfi = CONFIG_8xx_OSCLK / 2; + mfd = 14; + step_mfn = CONFIG_8xx_OSCLK / 30; + } else { + s = 0; + step_mfi = CONFIG_8xx_OSCLK; + mfd = 29; + step_mfn = CONFIG_8xx_OSCLK / 30; + } + + /* Calculate integer part of multiplication factor + */ + n = clk / step_mfi; + mfi = (char)n; + + /* Calculate numerator of fractional part of multiplication factor + */ + n = clk - (n * step_mfi); + mfn = (char)(n / step_mfn); + + /* Calculate effective clk + */ + n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1); + + immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; + + plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK + | PLPRCR_MFD_MSK | PLPRCR_S_MSK + | PLPRCR_MFI_MSK | PLPRCR_DBRMO + | PLPRCR_PDF_MSK)) + | (mfn << PLPRCR_MFN_SHIFT) + | (mfd << PLPRCR_MFD_SHIFT) + | (s << PLPRCR_S_SHIFT) + | (mfi << PLPRCR_MFI_SHIFT) + | (pdf << PLPRCR_PDF_SHIFT); + + if( (mfn > 0) && ((mfd / mfn) > 10) ) + plprcr |= PLPRCR_DBRMO; + + plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */ + immr->im_clkrstk.cark_plprcrk = 0x00000000; + + return (n); +} + +#endif /* CONFIG_8xx_CPUCLK_DEFAULT */ + +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) +/* + * Adjust sdram refresh rate to actual CPU clock + * and set timebase source according to actual CPU clock + */ +int adjust_sdram_tbs_8xx (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + long mamr; + long sccr; + + mamr = immr->im_memctl.memc_mamr; + mamr &= ~MAMR_PTA_MSK; + mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT); + immr->im_memctl.memc_mamr = mamr; + + if (gd->cpu_clk < 67000000) { + sccr = immr->im_clkrst.car_sccr; + sccr |= SCCR_TBS; + immr->im_clkrst.car_sccr = sccr; + } + + return (0); +} +#endif /* CONFIG_TQM8xxL/M, !TQM866M */ + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8xx/spi.c b/cpu/mpc8xx/spi.c new file mode 100644 index 0000000..e318ed0 --- /dev/null +++ b/cpu/mpc8xx/spi.c @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2001 Navin Boppuri / Prashant Patel + * , + * + * Copyright (c) 2001 Gerd Mennchen + * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8xx CPM SPI interface. + * + * Parts of this code are probably not portable and/or specific to + * the board which I used for the tests. Please send fixes/complaints + * to wd@denx.de + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#if (defined(CONFIG_SPI)) || (CONFIG_POST & CFG_POST_SPI) + +/* Warning: + * You cannot enable DEBUG for early system initalization, i. e. when + * this driver is used to read environment parameters like "baudrate" + * from EEPROM which are used to initialize the serial port which is + * needed to print the debug messages... + */ +#undef DEBUG + +#define SPI_EEPROM_WREN 0x06 +#define SPI_EEPROM_RDSR 0x05 +#define SPI_EEPROM_READ 0x03 +#define SPI_EEPROM_WRITE 0x02 + +/* --------------------------------------------------------------- + * Offset for initial SPI buffers in DPRAM: + * We need a 520 byte scratch DPRAM area to use at an early stage. + * It is used between the two initialization calls (spi_init_f() + * and spi_init_r()). + * The value 0xb00 makes it far enough from the start of the data + * area (as well as from the stack pointer). + * --------------------------------------------------------------- */ +#ifndef CFG_SPI_INIT_OFFSET +#define CFG_SPI_INIT_OFFSET 0xB00 +#endif + +#ifdef DEBUG + +#define DPRINT(a) printf a; +/* ----------------------------------------------- + * Helper functions to peek into tx and rx buffers + * ----------------------------------------------- */ +static const char * const hex_digit = "0123456789ABCDEF"; + +static char quickhex (int i) +{ + return hex_digit[i]; +} + +static void memdump (void *pv, int num) +{ + int i; + unsigned char *pc = (unsigned char *) pv; + + for (i = 0; i < num; i++) + printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); + printf ("\t"); + for (i = 0; i < num; i++) + printf ("%c", isprint (pc[i]) ? pc[i] : '.'); + printf ("\n"); +} +#else /* !DEBUG */ + +#define DPRINT(a) + +#endif /* DEBUG */ + +/* ------------------- + * Function prototypes + * ------------------- */ +void spi_init (void); + +ssize_t spi_read (uchar *, int, uchar *, int); +ssize_t spi_write (uchar *, int, uchar *, int); +ssize_t spi_xfer (size_t); + +/* ------------------- + * Variables + * ------------------- */ + +#define MAX_BUFFER 0x104 + +/* ---------------------------------------------------------------------- + * Initially we place the RX and TX buffers at a fixed location in DPRAM! + * ---------------------------------------------------------------------- */ +static uchar *rxbuf = + (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem + [CFG_SPI_INIT_OFFSET]; +static uchar *txbuf = + (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem + [CFG_SPI_INIT_OFFSET+MAX_BUFFER]; + +/* ************************************************************************** + * + * Function: spi_init_f + * + * Description: Init SPI-Controller (ROM part) + * + * return: --- + * + * *********************************************************************** */ +void spi_init_f (void) +{ + unsigned int dpaddr; + + volatile spi_t *spi; + volatile immap_t *immr; + volatile cpic8xx_t *cpi; + volatile cpm8xx_t *cp; + volatile iop8xx_t *iop; + volatile cbd_t *tbdf, *rbdf; + + immr = (immap_t *) CFG_IMMR; + cpi = (cpic8xx_t *)&immr->im_cpic; + iop = (iop8xx_t *) &immr->im_ioport; + cp = (cpm8xx_t *) &immr->im_cpm; + +#ifdef CFG_SPI_UCODE_PATCH + spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; +#else + spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; + /* Disable relocation */ + spi->spi_rpbase = 0; +#endif + +/* 1 */ + /* ------------------------------------------------ + * Initialize Port B SPI pins -> page 34-8 MPC860UM + * (we are only in Master Mode !) + * ------------------------------------------------ */ + + /* -------------------------------------------- + * GPIO or per. Function + * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) + * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) + * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) + * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) + * -------------------------------------------- */ + cp->cp_pbpar |= 0x0000000E; /* set bits */ + cp->cp_pbpar &= ~0x00000001; /* reset bit */ + + /* ---------------------------------------------- + * In/Out or per. Function 0/1 + * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO + * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI + * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK + * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM + * ---------------------------------------------- */ + cp->cp_pbdir |= 0x0000000F; + + /* ---------------------------------------------- + * open drain or active output + * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO + * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI + * PBODR[30] = 0 [0x00000002] -> active output: SPICLK + * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM + * ---------------------------------------------- */ + + cp->cp_pbodr |= 0x00000008; + cp->cp_pbodr &= ~0x00000007; + + /* Initialize the parameter ram. + * We need to make sure many things are initialized to zero + */ + spi->spi_rstate = 0; + spi->spi_rdp = 0; + spi->spi_rbptr = 0; + spi->spi_rbc = 0; + spi->spi_rxtmp = 0; + spi->spi_tstate = 0; + spi->spi_tdp = 0; + spi->spi_tbptr = 0; + spi->spi_tbc = 0; + spi->spi_txtmp = 0; + + /* Allocate space for one transmit and one receive buffer + * descriptor in the DP ram + */ +#ifdef CFG_ALLOC_DPRAM + dpaddr = dpram_alloc_align (sizeof(cbd_t)*2, 8); +#else + dpaddr = CPM_SPI_BASE; +#endif + +/* 3 */ + /* Set up the SPI parameters in the parameter ram */ + spi->spi_rbase = dpaddr; + spi->spi_tbase = dpaddr + sizeof (cbd_t); + + /***********IMPORTANT******************/ + + /* + * Setting transmit and receive buffer descriptor pointers + * initially to rbase and tbase. Only the microcode patches + * documentation talks about initializing this pointer. This + * is missing from the sample I2C driver. If you dont + * initialize these pointers, the kernel hangs. + */ + spi->spi_rbptr = spi->spi_rbase; + spi->spi_tbptr = spi->spi_tbase; + +/* 4 */ +#ifdef CFG_SPI_UCODE_PATCH + /* + * Initialize required parameters if using microcode patch. + */ + spi->spi_rstate = 0; + spi->spi_tstate = 0; +#else + /* Init SPI Tx + Rx Parameters */ + while (cp->cp_cpcr & CPM_CR_FLG) + ; + cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG; + while (cp->cp_cpcr & CPM_CR_FLG) + ; +#endif /* CFG_SPI_UCODE_PATCH */ + +/* 5 */ + /* Set SDMA configuration register */ + immr->im_siu_conf.sc_sdcr = 0x0001; + +/* 6 */ + /* Set to big endian. */ + spi->spi_tfcr = SMC_EB; + spi->spi_rfcr = SMC_EB; + +/* 7 */ + /* Set maximum receive size. */ + spi->spi_mrblr = MAX_BUFFER; + +/* 8 + 9 */ + /* tx and rx buffer descriptors */ + tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; + rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; + + tbdf->cbd_sc &= ~BD_SC_READY; + rbdf->cbd_sc &= ~BD_SC_EMPTY; + + /* Set the bd's rx and tx buffer address pointers */ + rbdf->cbd_bufaddr = (ulong) rxbuf; + tbdf->cbd_bufaddr = (ulong) txbuf; + +/* 10 + 11 */ + cp->cp_spim = 0; /* Mask all SPI events */ + cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ + + return; +} + +/* ************************************************************************** + * + * Function: spi_init_r + * + * Description: Init SPI-Controller (RAM part) - + * The malloc engine is ready and we can move our buffers to + * normal RAM + * + * return: --- + * + * *********************************************************************** */ +void spi_init_r (void) +{ + volatile cpm8xx_t *cp; + volatile spi_t *spi; + volatile immap_t *immr; + volatile cbd_t *tbdf, *rbdf; + + immr = (immap_t *) CFG_IMMR; + cp = (cpm8xx_t *) &immr->im_cpm; + +#ifdef CFG_SPI_UCODE_PATCH + spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; +#else + spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; + /* Disable relocation */ + spi->spi_rpbase = 0; +#endif + + /* tx and rx buffer descriptors */ + tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; + rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; + + /* Allocate memory for RX and TX buffers */ + rxbuf = (uchar *) malloc (MAX_BUFFER); + txbuf = (uchar *) malloc (MAX_BUFFER); + + rbdf->cbd_bufaddr = (ulong) rxbuf; + tbdf->cbd_bufaddr = (ulong) txbuf; + + return; +} + +/**************************************************************************** + * Function: spi_write + **************************************************************************** */ +ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) +{ + int i; + + memset(rxbuf, 0, MAX_BUFFER); + memset(txbuf, 0, MAX_BUFFER); + *txbuf = SPI_EEPROM_WREN; /* write enable */ + spi_xfer(1); + memcpy(txbuf, addr, alen); + *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ + memcpy(alen + txbuf, buffer, len); + spi_xfer(alen + len); + /* ignore received data */ + for (i = 0; i < 1000; i++) { + *txbuf = SPI_EEPROM_RDSR; /* read status */ + txbuf[1] = 0; + spi_xfer(2); + if (!(rxbuf[1] & 1)) { + break; + } + udelay(1000); + } + if (i >= 1000) { + printf ("*** spi_write: Time out while writing!\n"); + } + + return len; +} + +/**************************************************************************** + * Function: spi_read + **************************************************************************** */ +ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) +{ + memset(rxbuf, 0, MAX_BUFFER); + memset(txbuf, 0, MAX_BUFFER); + memcpy(txbuf, addr, alen); + *txbuf = SPI_EEPROM_READ; /* READ memory array */ + + /* + * There is a bug in 860T (?) that cuts the last byte of input + * if we're reading into DPRAM. The solution we choose here is + * to always read len+1 bytes (we have one extra byte at the + * end of the buffer). + */ + spi_xfer(alen + len + 1); + memcpy(buffer, alen + rxbuf, len); + + return len; +} + +/**************************************************************************** + * Function: spi_xfer + **************************************************************************** */ +ssize_t spi_xfer (size_t count) +{ + volatile immap_t *immr; + volatile cpm8xx_t *cp; + volatile spi_t *spi; + cbd_t *tbdf, *rbdf; + ushort loop; + int tm; + + DPRINT (("*** spi_xfer entered ***\n")); + + immr = (immap_t *) CFG_IMMR; + cp = (cpm8xx_t *) &immr->im_cpm; + +#ifdef CFG_SPI_UCODE_PATCH + spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; +#else + spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; + /* Disable relocation */ + spi->spi_rpbase = 0; +#endif + + tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; + rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; + + /* Set CS for device */ + cp->cp_pbdat &= ~0x0001; + + /* Setting tx bd status and data length */ + tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; + tbdf->cbd_datlen = count; + + DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", + tbdf->cbd_datlen)); + + /* Setting rx bd status and data length */ + rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; + rbdf->cbd_datlen = 0; /* rx length has no significance */ + + loop = cp->cp_spmode & SPMODE_LOOP; + cp->cp_spmode = /*SPMODE_DIV16 |*/ /* BRG/16 mode not used here */ + loop | + SPMODE_REV | + SPMODE_MSTR | + SPMODE_EN | + SPMODE_LEN(8) | /* 8 Bits per char */ + SPMODE_PM(0x8) ; /* medium speed */ + cp->cp_spim = 0; /* Mask all SPI events */ + cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ + + /* start spi transfer */ + DPRINT (("*** spi_xfer: Performing transfer ...\n")); + cp->cp_spcom |= SPI_STR; /* Start transmit */ + + /* -------------------------------- + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * -------------------------------- */ + for (tm=0; tm<1000; ++tm) { + if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */ + DPRINT (("*** spi_xfer: Tx buffer empty\n")); + break; + } + if ((tbdf->cbd_sc & BD_SC_READY) == 0) { + DPRINT (("*** spi_xfer: Tx BD done\n")); + break; + } + udelay (1000); + } + if (tm >= 1000) { + printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); + } + DPRINT (("*** spi_xfer: ... transfer ended\n")); + +#ifdef DEBUG + printf ("\nspi_xfer: txbuf after xfer\n"); + memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ + printf ("spi_xfer: rxbuf after xfer\n"); + memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ + printf ("\n"); +#endif + + /* Clear CS for device */ + cp->cp_pbdat |= 0x0001; + + return count; +} +#endif /* CONFIG_SPI || (CONFIG_POST & CFG_POST_SPI) */ + +/* + * SPI test + * + * The Serial Peripheral Interface (SPI) is tested in the local loopback mode. + * The interface is configured accordingly and several packets + * are transfered. The configurable test parameters are: + * TEST_MIN_LENGTH - minimum size of packet to transfer + * TEST_MAX_LENGTH - maximum size of packet to transfer + * TEST_NUM - number of tests + */ + +#if CONFIG_POST & CFG_POST_SPI + +#define TEST_MIN_LENGTH 1 +#define TEST_MAX_LENGTH MAX_BUFFER +#define TEST_NUM 1 + +static void packet_fill (char * packet, int length) +{ + char c = (char) length; + int i; + + for (i = 0; i < length; i++) + { + packet[i] = c++; + } +} + +static int packet_check (char * packet, int length) +{ + char c = (char) length; + int i; + + for (i = 0; i < length; i++) { + if (packet[i] != c++) return -1; + } + + return 0; +} + +int spi_post_test (int flags) +{ + int res = -1; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = (cpm8xx_t *) & immr->im_cpm; + int i; + int l; + + spi_init_f (); + spi_init_r (); + + cp->cp_spmode |= SPMODE_LOOP; + + for (i = 0; i < TEST_NUM; i++) { + for (l = TEST_MIN_LENGTH; l <= TEST_MAX_LENGTH; l += 8) { + packet_fill ((char *)txbuf, l); + + spi_xfer (l); + + if (packet_check ((char *)rxbuf, l) < 0) { + goto Done; + } + } + } + + res = 0; + + Done: + + cp->cp_spmode &= ~SPMODE_LOOP; + + /* + * SCC2 parameter RAM space overlaps + * the SPI parameter RAM space. So we need to restore + * the SCC2 configuration if it is used by UART. + */ + +#if !defined(CONFIG_8xx_CONS_NONE) + serial_reinit_all (); +#endif + + if (res != 0) { + post_log ("SPI test failed\n"); + } + + return res; +} +#endif /* CONFIG_POST & CFG_POST_SPI */ diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S new file mode 100644 index 0000000..33a3f6c --- /dev/null +++ b/cpu/mpc8xx/start.S @@ -0,0 +1,710 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000,2001,2002 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* U-Boot - Startup Code for PowerPC based Embedded Boards + * + * + * The processor starts at 0x00000100 and the code is executed + * from flash. The code is organized to be at an other address + * in memory, but as long we don't jump around before relocating, + * board_init lies at a quite high address and when the cpu has + * jumped there, everything is ok. + * This works because the cpu gives the FLASH (CS0) the whole + * address space at startup, and board_init lies as a echo of + * the flash somewhere up there in the memory map. + * + * board_init will change CS0 to be positioned at the correct + * address and (s)dram will be positioned at address 0 + */ +#include +#include +#include + +#define CONFIG_8xx 1 /* needed for Linux kernel header files */ +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +_start: + lis r3, CFG_IMMR@h /* position IMMR */ + mtspr 638, r3 + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ + b boot_cold + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + +boot_cold: +boot_warm: + + /* Initialize machine status; enable machine check interrupt */ + /*----------------------------------------------------------------------*/ + li r3, MSR_KERNEL /* Set ME, RI flags */ + mtmsr r3 + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + mfspr r3, ICR /* clear Interrupt Cause Register */ + + /* Initialize debug port registers */ + /*----------------------------------------------------------------------*/ + xor r0, r0, r0 /* Clear R0 */ + mtspr LCTRL1, r0 /* Initialize debug port regs */ + mtspr LCTRL2, r0 + mtspr COUNTA, r0 + mtspr COUNTB, r0 + + /* Reset the caches */ + /*----------------------------------------------------------------------*/ + + mfspr r3, IC_CST /* Clear error bits */ + mfspr r3, DC_CST + + lis r3, IDC_UNALL@h /* Unlock all */ + mtspr IC_CST, r3 + mtspr DC_CST, r3 + + lis r3, IDC_INVALL@h /* Invalidate all */ + mtspr IC_CST, r3 + mtspr DC_CST, r3 + + lis r3, IDC_DISABLE@h /* Disable data cache */ + mtspr DC_CST, r3 + +#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)) + /* On IP860 and PCU E, + * we cannot enable IC yet + */ + lis r3, IDC_ENABLE@h /* Enable instruction cache */ +#endif + mtspr IC_CST, r3 + + /* invalidate all tlb's */ + /*----------------------------------------------------------------------*/ + + tlbia + isync + + /* + * Calculate absolute address in FLASH and jump there + *----------------------------------------------------------------------*/ + + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r3 + blr + +in_flash: + + /* initialize some SPRs that are hard to access from C */ + /*----------------------------------------------------------------------*/ + + lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */ + ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */ + /* Note: R0 is still 0 here */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* + * Disable serialized ifetch and show cycles + * (i.e. set processor to normal mode). + * This is also a silicon bug workaround, see errata + */ + + li r2, 0x0007 + mtspr ICTRL, r2 + + /* Set up debug mode entry */ + + lis r2, CFG_DER@h + ori r2, r2, CFG_DER@l + mtspr DER, r2 + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*----------------------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + + mr r3, r21 + /* r3: BOOTFLAG */ + bl board_init_f /* run 1st part of board init code (from Flash) */ + + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. "Never" generated on the 860. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + /* No FPU on MPC8xx. This exception is not supposed to happen. + */ + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + /* On the MPC8xx, this is a software emulation interrupt. It occurs + * for all unimplemented and illegal instructions. + */ + STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) + + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) + STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) + STD_EXCEPTION(0x1400, DataTLBError, UnknownException) + + STD_EXCEPTION(0x1500, Reserved5, UnknownException) + STD_EXCEPTION(0x1600, Reserved6, UnknownException) + STD_EXCEPTION(0x1700, Reserved7, UnknownException) + STD_EXCEPTION(0x1800, Reserved8, UnknownException) + STD_EXCEPTION(0x1900, Reserved9, UnknownException) + STD_EXCEPTION(0x1a00, ReservedA, UnknownException) + STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + + STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) + STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException) + STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) + STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) + + + .globl _end_of_vectors +_end_of_vectors: + + + . = 0x2000 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* Cache functions. +*/ + .globl icache_enable +icache_enable: + SYNC + lis r3, IDC_INVALL@h + mtspr IC_CST, r3 + lis r3, IDC_ENABLE@h + mtspr IC_CST, r3 + blr + + .globl icache_disable +icache_disable: + SYNC + lis r3, IDC_DISABLE@h + mtspr IC_CST, r3 + blr + + .globl icache_status +icache_status: + mfspr r3, IC_CST + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl dcache_enable +dcache_enable: +#if 0 + SYNC +#endif +#if 1 + lis r3, 0x0400 /* Set cache mode with MMU off */ + mtspr MD_CTR, r3 +#endif + + lis r3, IDC_INVALL@h + mtspr DC_CST, r3 +#if 0 + lis r3, DC_SFWT@h + mtspr DC_CST, r3 +#endif + lis r3, IDC_ENABLE@h + mtspr DC_CST, r3 + blr + + .globl dcache_disable +dcache_disable: + SYNC + lis r3, IDC_DISABLE@h + mtspr DC_CST, r3 + lis r3, IDC_INVALL@h + mtspr DC_CST, r3 + blr + + .globl dcache_status +dcache_status: + mfspr r3, DC_CST + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl dc_read +dc_read: + mtspr DC_ADR, r3 + mfspr r3, DC_DAT + blr + +/* + * unsigned int get_immr (unsigned int mask) + * + * return (mask ? (IMMR & mask) : IMMR); + */ + .globl get_immr +get_immr: + mr r4,r3 /* save mask */ + mfspr r3, IMMR /* IMMR */ + cmpwi 0,r4,0 /* mask != 0 ? */ + beq 4f + and r3,r3,r4 /* IMMR & mask */ +4: + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + + + .globl wr_ic_cst +wr_ic_cst: + mtspr IC_CST, r3 + blr + + .globl rd_ic_cst +rd_ic_cst: + mfspr r3, IC_CST + blr + + .globl wr_ic_adr +wr_ic_adr: + mtspr IC_ADR, r3 + blr + + + .globl wr_dc_cst +wr_dc_cst: + mtspr DC_CST, r3 + blr + + .globl rd_dc_cst +rd_dc_cst: + mfspr r3, DC_CST + blr + + .globl wr_dc_adr +wr_dc_adr: + mtspr DC_ADR, r3 + blr + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + sync + isync + + blr diff --git a/cpu/mpc8xx/traps.c b/cpu/mpc8xx/traps.c new file mode 100644 index 0000000..67b75cc --- /dev/null +++ b/cpu/mpc8xx/traps.c @@ -0,0 +1,244 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler)(struct pt_regs *) = 0; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint(struct pt_regs *); +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. +*/ +#define END_OF_MEM 0x02000000 + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + printf("Data parity signal\n"); + break; + case (0x80000000>>15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +SoftEmuException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + + +void +UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +void +DebugException(struct pt_regs *regs) +{ + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); +#endif +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int +addr_probe(uint *addr) +{ +#if 0 + int retval; + + __asm__ __volatile__( \ + "1: lwz %0,0(%1)\n" \ + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); + + return (retval); +#endif + return 0; +} diff --git a/cpu/mpc8xx/upatch.c b/cpu/mpc8xx/upatch.c new file mode 100644 index 0000000..eccff64 --- /dev/null +++ b/cpu/mpc8xx/upatch.c @@ -0,0 +1,102 @@ +#include +#include + +#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) + +static void UcodeCopy (volatile cpm8xx_t *cpm); + +void cpm_load_patch (volatile immap_t *immr) +{ + immr->im_cpm.cp_rccr &= ~0x0003; /* Disable microcode program area */ + + UcodeCopy ((cpm8xx_t *)&immr->im_cpm); /* Copy ucode patch to DPRAM */ +#ifdef CFG_SPI_UCODE_PATCH + { + volatile spi_t *spi = (spi_t *) & immr->im_cpm.cp_dparam[PROFF_SPI]; + /* Activate the microcode per the instructions in the microcode manual */ + /* NOTE: We're only relocating the SPI parameters (not I2C). */ + immr->im_cpm.cp_cpmcr1 = 0x802a; /* Write Trap register 1 value */ + immr->im_cpm.cp_cpmcr2 = 0x8028; /* Write Trap register 2 value */ + spi->spi_rpbase = CFG_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */ + } +#endif + +#ifdef CFG_I2C_UCODE_PATCH + { + volatile iic_t *iip = (iic_t *) & immr->im_cpm.cp_dparam[PROFF_IIC]; + /* Activate the microcode per the instructions in the microcode manual */ + /* NOTE: We're only relocating the I2C parameters (not SPI). */ + immr->im_cpm.cp_cpmcr3 = 0x802e; /* Write Trap register 3 value */ + immr->im_cpm.cp_cpmcr4 = 0x802c; /* Write Trap register 4 value */ + iip->iic_rpbase = CFG_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */ + } +#endif + + /* + * Enable DPRAM microcode to execute from the first 512 bytes + * and a 256 byte extension of DPRAM. + */ + immr->im_cpm.cp_rccr |= 0x0001; +} + +static ulong patch_2000[] = { + 0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000, + 0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7, + 0x3A9CFBC8, 0x77CAE1BB, 0xF4DE7FAD, 0xABAE9330, + 0x4E08FDCF, 0x6E0FAFF8, 0x7CCF76CF, 0xFDAFF9CF, + 0xABF88DC8, 0xAB5879F7, 0xB0927383, 0xDFD079F7, + 0xB090E6BB, 0xE5BBE74F, 0xB3FA6F0F, 0x6FFB76CE, + 0xEE0CF9CF, 0x2BFBEFEF, 0xCFEEF9CF, 0x76CEAD23, + 0x90B3DF99, 0x7FDDD0C1, 0x4BF847FD, 0x7CCF76CE, + 0xCFEF77CA, 0x7EAF7FAD, 0x7DFDF0B7, 0xEF7A7FCA, + 0x77CAFBC8, 0x6079E722, 0xFBC85FFF, 0xDFFF5FB3, + 0xFFFBFBC8, 0xF3C894A5, 0xE7C9EDF9, 0x7F9A7FAD, + 0x5F36AFE8, 0x5F5BFFDF, 0xDF95CB9E, 0xAF7D5FC3, + 0xAFED8C1B, 0x5FC3AFDD, 0x5FC5DF99, 0x7EFDB0B3, + 0x5FB3FFFE, 0xABAE5FB3, 0xFFFE5FD0, 0x600BE6BB, + 0x600B5FD0, 0xDFC827FB, 0xEFDF5FCA, 0xCFDE3A9C, + 0xE7C9EDF9, 0xF3C87F9E, 0x54CA7FED, 0x2D3A3637, + 0x756F7E9A, 0xF1CE37EF, 0x2E677FEE, 0x10EBADF8, + 0xEFDECFEA, 0xE52F7D9F, 0xE12BF1CE, 0x5F647E9A, + 0x4DF8CFEA, 0x5F717D9B, 0xEFEECFEA, 0x5F73E522, + 0xEFDE5F73, 0xCFDA0B61, 0x7385DF61, 0xE7C9EDF9, + 0x7E9A30D5, 0x1458BFFF, 0xF3C85FFF, 0xDFFFA7F8, + 0x5F5BBFFE, 0x7F7D10D0, 0x144D5F33, 0xBFFFAF78, + 0x5F5BBFFD, 0xA7F85F33, 0xBFFE77FD, 0x30BD4E08, + 0xFDCFE5FF, 0x6E0FAFF8, 0x7EEF7E9F, 0xFDEFF1CF, + 0x5F17ABF8, 0x0D5B5F5B, 0xFFEF79F7, 0x309EAFDD, + 0x5F3147F8, 0x5F31AFED, 0x7FDD50AF, 0x497847FD, + 0x7F9E7FED, 0x7DFD70A9, 0xEF7E7ECE, 0x6BA07F9E, + 0x2D227EFD, 0x30DB5F5B, 0xFFFD5F5B, 0xFFEF5F5B, + 0xFFDF0C9C, 0xAFED0A9A, 0xAFDD0C37, 0x5F37AFBD, + 0x7FBDB081, 0x5F8147F8, +}; + +static ulong patch_2F00[] = { + 0x3E303430, 0x34343737, 0xABBF9B99, 0x4B4FBDBD, + 0x59949334, 0x9FFF37FB, 0x9B177DD9, 0x936956BB, + 0xFBDD697B, 0xDD2FD113, 0x1DB9F7BB, 0x36313963, + 0x79373369, 0x3193137F, 0x7331737A, 0xF7BB9B99, + 0x9BB19795, 0x77FDFD3D, 0x573B773F, 0x737933F7, + 0xB991D115, 0x31699315, 0x31531694, 0xBF4FBDBD, + 0x35931497, 0x35376956, 0xBD697B9D, 0x96931313, + 0x19797937, 0x69350000, +}; + +static void UcodeCopy (volatile cpm8xx_t *cpm) +{ + vu_long *p; + int i; + + p = (vu_long *)&(cpm->cp_dpmem[0x0000]); + for (i=0; i < sizeof(patch_2000)/4; ++i) { + p[i] = patch_2000[i]; + } + + p = (vu_long *)&(cpm->cp_dpmem[0x0F00]); + for (i=0; i < sizeof(patch_2F00)/4; ++i) { + p[i] = patch_2F00[i]; + } +} + +#endif /* CFG_I2C_UCODE_PATCH, CFG_SPI_UCODE_PATCH */ diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c new file mode 100644 index 0000000..ee60477 --- /dev/null +++ b/cpu/mpc8xx/video.c @@ -0,0 +1,1330 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * (C) Copyright 2002 + * Wolfgang Denk, wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +/************************************************************************/ +/* ** HEADER FILES */ +/************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_VIDEO + +/************************************************************************/ +/* ** DEBUG SETTINGS */ +/************************************************************************/ + +#if 0 +#define VIDEO_DEBUG_COLORBARS /* Force colorbars output */ +#endif + +/************************************************************************/ +/* ** VIDEO MODE SETTINGS */ +/************************************************************************/ + +#if 0 +#define VIDEO_MODE_EXTENDED /* Allow screen size bigger than visible area */ +#define VIDEO_MODE_NTSC +#endif + +#define VIDEO_MODE_PAL + +#if 0 +#define VIDEO_BLINK /* This enables cursor blinking (under construction) */ +#endif + +#define VIDEO_INFO /* Show U-Boot information */ +#define VIDEO_INFO_X VIDEO_LOGO_WIDTH+8 +#define VIDEO_INFO_Y 16 + +/************************************************************************/ +/* ** VIDEO ENCODER CONSTANTS */ +/************************************************************************/ + +#ifdef CONFIG_VIDEO_ENCODER_AD7176 + +#include /* Sets encoder data, mode, and visible and active area */ + +#define VIDEO_I2C 1 +#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7176_ADDR +#endif + +#ifdef CONFIG_VIDEO_ENCODER_AD7177 + +#include /* Sets encoder data, mode, and visible and active area */ + +#define VIDEO_I2C 1 +#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7177_ADDR +#endif + +#ifdef CONFIG_VIDEO_ENCODER_AD7179 + +#include /* Sets encoder data, mode, and visible and active area */ + +#define VIDEO_I2C 1 +#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7179_ADDR +#endif + +/************************************************************************/ +/* ** VIDEO MODE CONSTANTS */ +/************************************************************************/ + +#ifdef VIDEO_MODE_EXTENDED +#define VIDEO_COLS VIDEO_ACTIVE_COLS +#define VIDEO_ROWS VIDEO_ACTIVE_ROWS +#else +#define VIDEO_COLS VIDEO_VISIBLE_COLS +#define VIDEO_ROWS VIDEO_VISIBLE_ROWS +#endif + +#define VIDEO_PIXEL_SIZE (VIDEO_MODE_BPP/8) +#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE) /* Total size of buffer */ +#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2) /* Number of ints */ +#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE) /* Number of bytes per line */ +#define VIDEO_BURST_LEN (VIDEO_COLS/8) + +#ifdef VIDEO_MODE_YUYV +#define VIDEO_BG_COL 0x80D880D8 /* Background color in YUYV format */ +#else +#define VIDEO_BG_COL 0xF8F8F8F8 /* Background color in RGB format */ +#endif + +/************************************************************************/ +/* ** FONT AND LOGO DATA */ +/************************************************************************/ + +#include /* Get font data, width and height */ + +#ifdef CONFIG_VIDEO_LOGO +#include /* Get logo data, width and height */ + +#define VIDEO_LOGO_WIDTH DEF_U_BOOT_LOGO_WIDTH +#define VIDEO_LOGO_HEIGHT DEF_U_BOOT_LOGO_HEIGHT +#define VIDEO_LOGO_ADDR &u_boot_logo +#endif + +/************************************************************************/ +/* ** VIDEO CONTROLLER CONSTANTS */ +/************************************************************************/ + +/* VCCR - VIDEO CONTROLLER CONFIGURATION REGISTER */ + +#define VIDEO_VCCR_VON 0 /* Video controller ON */ +#define VIDEO_VCCR_CSRC 1 /* Clock source */ +#define VIDEO_VCCR_PDF 13 /* Pixel display format */ +#define VIDEO_VCCR_IEN 11 /* Interrupt enable */ + +/* VSR - VIDEO STATUS REGISTER */ + +#define VIDEO_VSR_CAS 6 /* Active set */ +#define VIDEO_VSR_EOF 0 /* End of frame */ + +/* VCMR - VIDEO COMMAND REGISTER */ + +#define VIDEO_VCMR_BD 0 /* Blank display */ +#define VIDEO_VCMR_ASEL 1 /* Active set selection */ + +/* VBCB - VIDEO BACKGROUND COLOR BUFFER REGISTER */ + +#define VIDEO_BCSR4_RESET_BIT 21 /* BCSR4 - Extern video encoder reset */ +#define VIDEO_BCSR4_EXTCLK_BIT 22 /* BCSR4 - Extern clock enable */ +#define VIDEO_BCSR4_VIDLED_BIT 23 /* BCSR4 - Video led disable */ + +/************************************************************************/ +/* ** CONSOLE CONSTANTS */ +/************************************************************************/ + +#ifdef CONFIG_VIDEO_LOGO +#define CONSOLE_ROWS ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / VIDEO_FONT_HEIGHT) +#define VIDEO_LOGO_SKIP (VIDEO_COLS - VIDEO_LOGO_WIDTH) +#else +#define CONSOLE_ROWS (VIDEO_ROWS / VIDEO_FONT_HEIGHT) +#endif + +#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH) +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) +#define CONSOLE_ROW_FIRST (video_console_address) +#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) +#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) +#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) + +/* + * Simple color definitions + */ +#define CONSOLE_COLOR_BLACK 0 +#define CONSOLE_COLOR_RED 1 +#define CONSOLE_COLOR_GREEN 2 +#define CONSOLE_COLOR_YELLOW 3 +#define CONSOLE_COLOR_BLUE 4 +#define CONSOLE_COLOR_MAGENTA 5 +#define CONSOLE_COLOR_CYAN 6 +#define CONSOLE_COLOR_GREY 13 +#define CONSOLE_COLOR_GREY2 14 +#define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ + +/************************************************************************/ +/* ** BITOPS MACROS */ +/************************************************************************/ + +#define HISHORT(i) ((i >> 16)&0xffff) +#define LOSHORT(i) (i & 0xffff) +#define HICHAR(s) ((i >> 8)&0xff) +#define LOCHAR(s) (i & 0xff) +#define HI(c) ((c >> 4)&0xf) +#define LO(c) (c & 0xf) +#define SWAPINT(i) (HISHORT(i) | (LOSHORT(i) << 16)) +#define SWAPSHORT(s) (HICHAR(s) | (LOCHAR(s) << 8)) +#define SWAPCHAR(c) (HI(c) | (LO(c) << 4)) +#define BITMASK(b) (1 << (b)) +#define GETBIT(v,b) (((v) & BITMASK(b)) > 0) +#define SETBIT(v,b,d) (v = (((d)>0) ? (v) | BITMASK(b): (v) & ~BITMASK(b))) + +/************************************************************************/ +/* ** STRUCTURES */ +/************************************************************************/ + +typedef struct { + unsigned char V, Y1, U, Y2; +} tYUYV; + +/* This structure is based on the Video Ram in the MPC823. */ +typedef struct VRAM { + unsigned hx:2, /* Horizontal sync */ + vx:2, /* Vertical sync */ + fx:2, /* Frame */ + bx:2, /* Blank */ + res1:6, /* Reserved */ + vds:2, /* Video Data Select */ + inter:1, /* Interrupt */ + res2:2, /* Reserved */ + lcyc:11, /* Loop/video cycles */ + lp:1, /* Loop start/end */ + lst:1; /* Last entry */ +} VRAM; + +/************************************************************************/ +/* ** VARIABLES */ +/************************************************************************/ + +static int + video_panning_range_x = 0, /* Video mode invisible pixels x range */ + video_panning_range_y = 0, /* Video mode invisible pixels y range */ + video_panning_value_x = 0, /* Video mode x panning value (absolute) */ + video_panning_value_y = 0, /* Video mode y panning value (absolute) */ + video_panning_factor_x = 0, /* Video mode x panning value (-127 +127) */ + video_panning_factor_y = 0, /* Video mode y panning value (-127 +127) */ + console_col = 0, /* Cursor col */ + console_row = 0, /* Cursor row */ + video_palette[16]; /* Our palette */ + +static const int video_font_draw_table[] = + { 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff }; + +static char + video_color_fg = 0, /* Current fg color index (0-15) */ + video_color_bg = 0, /* Current bg color index (0-15) */ + video_enable = 0; /* Video has been initialized? */ + +static void + *video_fb_address, /* Frame buffer address */ + *video_console_address; /* Console frame buffer start address */ + +/************************************************************************/ +/* ** MEMORY FUNCTIONS (32bit) */ +/************************************************************************/ + +static void memsetl (int *p, int c, int v) +{ + while (c--) + *(p++) = v; +} + +static void memcpyl (int *d, int *s, int c) +{ + while (c--) + *(d++) = *(s++); +} + +/************************************************************************/ +/* ** VIDEO DRAWING AND COLOR FUNCTIONS */ +/************************************************************************/ + +static int video_maprgb (int r, int g, int b) +{ +#ifdef VIDEO_MODE_YUYV + unsigned int pR, pG, pB; + tYUYV YUYV; + unsigned int *ret = (unsigned int *) &YUYV; + + /* Transform (0-255) components to (0-100) */ + + pR = r * 100 / 255; + pG = g * 100 / 255; + pB = b * 100 / 255; + + /* Calculate YUV values (0-255) from RGB beetween 0-100 */ + + YUYV.Y1 = YUYV.Y2 = 209 * (pR + pG + pB) / 300 + 16; + YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128; + YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128; + return *ret; +#endif +#ifdef VIDEO_MODE_RGB + return ((r >> 3) << 11) | ((g > 2) << 6) | (b >> 3); +#endif +} + +static void video_setpalette (int color, int r, int g, int b) +{ + color &= 0xf; + + video_palette[color] = video_maprgb (r, g, b); + + /* Swap values if our panning offset is odd */ + if (video_panning_value_x & 1) + video_palette[color] = SWAPINT (video_palette[color]); +} + +static void video_fill (int color) +{ + memsetl (video_fb_address, VIDEO_PIX_BLOCKS, color); +} + +static void video_setfgcolor (int i) +{ + video_color_fg = i & 0xf; +} + +static void video_setbgcolor (int i) +{ + video_color_bg = i & 0xf; +} + +static int video_pickcolor (int i) +{ + return video_palette[i & 0xf]; +} + +/* Absolute console plotting functions */ + +#ifdef VIDEO_BLINK +static void video_revchar (int xx, int yy) +{ + int rows; + u8 *dest; + + dest = video_fb_address + yy * VIDEO_LINE_LEN + xx * 2; + + for (rows = VIDEO_FONT_HEIGHT; rows--; dest += VIDEO_LINE_LEN) { + switch (VIDEO_FONT_WIDTH) { + case 16: + ((u32 *) dest)[6] ^= 0xffffffff; + ((u32 *) dest)[7] ^= 0xffffffff; + /* FALL THROUGH */ + case 12: + ((u32 *) dest)[4] ^= 0xffffffff; + ((u32 *) dest)[5] ^= 0xffffffff; + /* FALL THROUGH */ + case 8: + ((u32 *) dest)[2] ^= 0xffffffff; + ((u32 *) dest)[3] ^= 0xffffffff; + /* FALL THROUGH */ + case 4: + ((u32 *) dest)[0] ^= 0xffffffff; + ((u32 *) dest)[1] ^= 0xffffffff; + } + } +} +#endif + +static void video_drawchars (int xx, int yy, unsigned char *s, int count) +{ + u8 *cdat, *dest, *dest0; + int rows, offset, c; + u32 eorx, fgx, bgx; + + offset = yy * VIDEO_LINE_LEN + xx * 2; + dest0 = video_fb_address + offset; + + fgx = video_pickcolor (video_color_fg); + bgx = video_pickcolor (video_color_bg); + + if (xx & 1) { + fgx = SWAPINT (fgx); + bgx = SWAPINT (bgx); + } + + eorx = fgx ^ bgx; + + switch (VIDEO_FONT_WIDTH) { + case 4: + case 8: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = + (video_font_draw_table[bits >> 6] & eorx) ^ bgx; + ((u32 *) dest)[1] = + (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; + if (VIDEO_FONT_WIDTH == 8) { + ((u32 *) dest)[2] = + (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; + ((u32 *) dest)[3] = + (video_font_draw_table[bits & 3] & eorx) ^ bgx; + } + } + dest0 += VIDEO_FONT_WIDTH * 2; + s++; + } + break; + case 12: + case 16: + while (count--) { + cdat = video_fontdata + (*s) * (VIDEO_FONT_HEIGHT << 1); + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = + (video_font_draw_table[bits >> 6] & eorx) ^ bgx; + ((u32 *) dest)[1] = + (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; + ((u32 *) dest)[2] = + (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; + ((u32 *) dest)[3] = + (video_font_draw_table[bits & 3] & eorx) ^ bgx; + bits = *cdat++; + ((u32 *) dest)[4] = + (video_font_draw_table[bits >> 6] & eorx) ^ bgx; + ((u32 *) dest)[5] = + (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; + if (VIDEO_FONT_WIDTH == 16) { + ((u32 *) dest)[6] = + (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; + ((u32 *) dest)[7] = + (video_font_draw_table[bits & 3] & eorx) ^ bgx; + } + } + s++; + dest0 += VIDEO_FONT_WIDTH * 2; + } + break; + } +} + +static inline void video_drawstring (int xx, int yy, char *s) +{ + video_drawchars (xx, yy, (unsigned char *)s, strlen (s)); +} + +/* Relative to console plotting functions */ + +static void video_putchars (int xx, int yy, unsigned char *s, int count) +{ +#ifdef CONFIG_VIDEO_LOGO + video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, s, count); +#else + video_drawchars (xx, yy, s, count); +#endif +} + +static void video_putchar (int xx, int yy, unsigned char c) +{ +#ifdef CONFIG_VIDEO_LOGO + video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, &c, 1); +#else + video_drawchars (xx, yy, &c, 1); +#endif +} + +static inline void video_putstring (int xx, int yy, unsigned char *s) +{ + video_putchars (xx, yy, (unsigned char *)s, strlen ((char *)s)); +} + +/************************************************************************/ +/* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */ +/************************************************************************/ + +#if !defined(CONFIG_RRVISION) +static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) +{ + int i; + + for (i = 0; i < entries; i++) { + dest[i] = source[i]; /* Copy the entire record */ + dest[i].fx = (!dest[i].fx) * 3; /* Negate field bit */ + } + + dest[0].lcyc++; /* Add a cycle to the first entry */ + dest[entries - 1].lst = 1; /* Set end of ram entries */ +} +#endif + +static void inline video_mode_addentry (VRAM * vr, + int Hx, int Vx, int Fx, int Bx, + int VDS, int INT, int LCYC, int LP, int LST) +{ + vr->hx = Hx; + vr->vx = Vx; + vr->fx = Fx; + vr->bx = Bx; + vr->vds = VDS; + vr->inter = INT; + vr->lcyc = LCYC; + vr->lp = LP; + vr->lst = LST; +} + +#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i) + +static int video_mode_generate (void) +{ + immap_t *immap = (immap_t *) CFG_IMMR; + VRAM *vr = (VRAM *) (((void *) immap) + 0xb00); /* Pointer to the VRAM table */ + int DX, X1, X2, DY, Y1, Y2, entry = 0, fifo; + + /* CHECKING PARAMETERS */ + + if (video_panning_factor_y < -128) + video_panning_factor_y = -128; + + if (video_panning_factor_y > 128) + video_panning_factor_y = 128; + + if (video_panning_factor_x < -128) + video_panning_factor_x = -128; + + if (video_panning_factor_x > 128) + video_panning_factor_x = 128; + + /* Setting panning */ + + DX = video_panning_range_x = (VIDEO_ACTIVE_COLS - VIDEO_COLS) * 2; + DY = video_panning_range_y = (VIDEO_ACTIVE_ROWS - VIDEO_ROWS) / 2; + + video_panning_value_x = (video_panning_factor_x + 128) * DX / 256; + video_panning_value_y = (video_panning_factor_y + 128) * DY / 256; + + /* We assume these are burst units (multiplied by 2, we need it pari) */ + X1 = video_panning_value_x & 0xfffe; + X2 = DX - X1; + + /* We assume these are field line units (divided by 2, we need it pari) */ + Y1 = video_panning_value_y & 0xfffe; + Y2 = DY - Y1; + + debug("X1=%d, X2=%d, Y1=%d, Y2=%d, DX=%d, DY=%d VIDEO_COLS=%d \n", + X1, X2, Y1, Y2, DX, DY, VIDEO_COLS); + +#ifdef VIDEO_MODE_NTSC +/* + * Hx Vx Fx Bx VDS INT LCYC LP LST + * + * Retrace blanking + */ + ADDENTRY (0, 0, 3, 0, 1, 0, 3, 1, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); +/* + * Vertical blanking + */ + ADDENTRY (0, 0, 0, 0, 1, 0, 18, 1, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 243, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); +/* + * Odd field active area (TOP) + */ + if (Y1 > 0) { + ADDENTRY (0, 0, 0, 0, 1, 0, Y1, 1, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); + } +/* + * Odd field active area + */ + ADDENTRY (0, 0, 0, 0, 1, 0, 240 - DY, 1, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, 8 + X1, 0, 0); + ADDENTRY (3, 0, 0, 3, 0, 0, VIDEO_COLS * 2, 0, 0); + + if (X2 > 0) + ADDENTRY (3, 0, 0, 3, 1, 0, X2, 0, 0); + + ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); + +/* + * Odd field active area (BOTTOM) + */ + if (Y1 > 0) { + ADDENTRY (0, 0, 0, 0, 1, 0, Y2, 1, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); + } +/* + * Vertical blanking + */ + ADDENTRY (0, 0, 0, 0, 1, 0, 4, 1, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 243, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); +/* + * Vertical blanking + */ + ADDENTRY (0, 0, 3, 0, 1, 0, 19, 1, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); +/* + * Even field active area (TOP) + */ + if (Y1 > 0) { + ADDENTRY (0, 0, 3, 0, 1, 0, Y1, 1, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); + ADDENTRY (3, 0, 3, 3, 1, 0, 1448, 0, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); + } +/* + * Even field active area (CENTER) + */ + ADDENTRY (0, 0, 3, 0, 1, 0, 240 - DY, 1, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); + ADDENTRY (3, 0, 3, 3, 1, 0, 8 + X1, 0, 0); + ADDENTRY (3, 0, 3, 3, 0, 0, VIDEO_COLS * 2, 0, 0); + + if (X2 > 0) + ADDENTRY (3, 0, 3, 3, 1, 0, X2, 0, 0); + + ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); +/* + * Even field active area (BOTTOM) + */ + if (Y1 > 0) { + ADDENTRY (0, 0, 3, 0, 1, 0, Y2, 1, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); + ADDENTRY (3, 0, 3, 3, 1, 0, 1448, 0, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); + } +/* + * Vertical blanking + */ + ADDENTRY (0, 0, 3, 0, 1, 0, 1, 1, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); + ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); + ADDENTRY (3, 0, 3, 0, 1, 1, 32, 1, 1); +#endif + +#ifdef VIDEO_MODE_PAL + +#if defined(CONFIG_RRVISION) + +#define HPW 160 /* horizontal pulse width (was 139) */ +#define VPW 2 /* vertical pulse width */ +#define HBP 104 /* horizontal back porch (was 112) */ +#define VBP 19 /* vertical back porch (was 19) */ +#define VID_R 240 /* number of rows */ + + debug ("[VIDEO CTRL] Starting to add controller entries..."); +/* + * Even field + */ + ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); + ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); + + ADDENTRY (0, 0, 0, 3, 1, 0, VPW, 1, 0); + ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); + + ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); +/* + * Active area + */ + ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); + ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); + + ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); +/* + * Odd field + */ + ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); + ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); + + ADDENTRY (0, 0, 0, 3, 1, 0, VPW+1, 1, 0); + ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); + + ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); +/* + * Active area + */ + ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); + ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); + + ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); + ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); + + debug ("done\n"); + +#else /* !CONFIG_RRVISION */ + +/* + * Hx Vx Fx Bx VDS INT LCYC LP LST + * + * vertical; blanking + */ + ADDENTRY (0, 0, 0, 0, 1, 0, 22, 1, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 263, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); +/* + * active area (TOP) + */ + if (Y1 > 0) { + ADDENTRY (0, 0, 0, 0, 1, 0, Y1, 1, 0); /* 11? */ + ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); + } +/* + * field active area (CENTER) + */ + ADDENTRY (0, 0, 0, 0, 1, 0, 288 - DY, 1, 0); /* 265? */ + ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, 8 + X1, 0, 0); + ADDENTRY (3, 0, 0, 3, 0, 0, VIDEO_COLS * 2, 0, 0); + + if (X2 > 0) + ADDENTRY (3, 0, 0, 1, 1, 0, X2, 0, 0); + + ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); +/* + * field active area (BOTTOM) + */ + if (Y2 > 0) { + ADDENTRY (0, 0, 0, 0, 1, 0, Y2, 1, 0); /* 12? */ + ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); + ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); + } +/* + * field vertical; blanking + */ + ADDENTRY (0, 0, 0, 0, 1, 0, 2, 1, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 263, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); + ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); +/* + * Create the other field (like this, but whit other field selected, + * one more cycle loop and a last identifier) + */ + video_mode_dupefield (vr, &vr[entry], entry); +#endif /* CONFIG_RRVISION */ + +#endif /* VIDEO_MODE_PAL */ + + /* See what FIFO are we using */ + fifo = GETBIT (immap->im_vid.vid_vsr, VIDEO_VSR_CAS); + + /* Set number of lines and burst (only one frame for now) */ + if (fifo) { + immap->im_vid.vid_vfcr0 = VIDEO_BURST_LEN | + (VIDEO_BURST_LEN << 8) | ((VIDEO_ROWS / 2) << 19); + } else { + immap->im_vid.vid_vfcr1 = VIDEO_BURST_LEN | + (VIDEO_BURST_LEN << 8) | ((VIDEO_ROWS / 2) << 19); + } + + SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_ASEL, !fifo); + +/* + * Wait until changes are applied (not done) + * while (GETBIT(immap->im_vid.vid_vsr, VIDEO_VSR_CAS) == fifo) ; + */ + + /* Return number of VRAM entries */ + return entry * 2; +} + +static void video_encoder_init (void) +{ +#ifdef VIDEO_I2C + int rc; + + /* Initialize the I2C */ + debug ("[VIDEO ENCODER] Initializing I2C bus...\n"); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + +#ifdef CONFIG_FADS + /* Reset ADV7176 chip */ + debug ("[VIDEO ENCODER] Resetting encoder...\n"); + (*(int *) BCSR4) &= ~(1 << 21); + + /* Wait for 5 ms inside the reset */ + debug ("[VIDEO ENCODER] Waiting for encoder reset...\n"); + udelay (5000); + + /* Take ADV7176 out of reset */ + (*(int *) BCSR4) |= 1 << 21; + + /* Wait for 5 ms after the reset */ + udelay (5000); +#endif /* CONFIG_FADS */ + + /* Send configuration */ +#ifdef DEBUG + { + int i; + + puts ("[VIDEO ENCODER] Configuring the encoder...\n"); + + printf ("Sending %d bytes (@ %08lX) to I2C 0x%X:\n ", + sizeof(video_encoder_data), + (ulong)video_encoder_data, + VIDEO_I2C_ADDR); + for (i=0; iim_vid.vid_vbcb = VIDEO_BG_COL; + + /* Show the background */ + debug ("[VIDEO CTRL] Forcing background...\n"); + SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_BD, 1); + + /* Turn off video controller */ + debug ("[VIDEO CTRL] Turning off video controller...\n"); + SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 0); + +#ifdef CONFIG_FADS + /* Turn on Video Port LED */ + debug ("[VIDEO CTRL] Turning off video port led...\n"); + SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 1); + + /* Disable internal clock */ + debug ("[VIDEO CTRL] Disabling internal clock...\n"); + SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 0); +#endif + + /* Generate and make active a new video mode */ + debug ("[VIDEO CTRL] Generating video mode...\n"); + video_mode_generate (); + + /* Start of frame buffer (even and odd frame, to make it working with */ + /* any selected active set) */ + debug ("[VIDEO CTRL] Setting frame buffer address...\n"); + immap->im_vid.vid_vfaa1 = + immap->im_vid.vid_vfaa0 = (u32) video_fb_address; + immap->im_vid.vid_vfba1 = + immap->im_vid.vid_vfba0 = + (u32) video_fb_address + VIDEO_LINE_LEN; + + /* YUV, Big endian, SHIFT/CLK/CLK input (BEFORE ENABLING 27MHZ EXT CLOCK) */ + debug ("[VIDEO CTRL] Setting pixel mode and clocks...\n"); + immap->im_vid.vid_vccr = 0x2042; + + /* Configure port pins */ + debug ("[VIDEO CTRL] Configuring input/output pins...\n"); + immap->im_ioport.iop_pdpar = 0x1fff; + immap->im_ioport.iop_pddir = 0x0000; + +#ifdef CONFIG_FADS + /* Turn on Video Port Clock - ONLY AFTER SET VCCR TO ENABLE EXTERNAL CLOCK */ + debug ("[VIDEO CTRL] Turning on video clock...\n"); + SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 1); + + /* Turn on Video Port LED */ + debug ("[VIDEO CTRL] Turning on video port led...\n"); + SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0); +#endif +#ifdef CONFIG_RRVISION + debug ("PC5->Output(1): enable PAL clock"); + immap->im_ioport.iop_pcpar &= ~(0x0400); + immap->im_ioport.iop_pcdir |= 0x0400 ; + immap->im_ioport.iop_pcdat |= 0x0400 ; + debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", + immap->im_ioport.iop_pdpar, + immap->im_ioport.iop_pddir, + immap->im_ioport.iop_pddat); + debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", + immap->im_ioport.iop_pcpar, + immap->im_ioport.iop_pcdir, + immap->im_ioport.iop_pcdat); +#endif /* CONFIG_RRVISION */ + + /* Blanking the screen. */ + debug ("[VIDEO CTRL] Blanking the screen...\n"); + video_fill (VIDEO_BG_COL); + + /* + * Turns on Aggressive Mode. Normally, turning on the caches + * will cause the screen to flicker when the caches try to + * fill. This gives the FIFO's for the Video Controller + * higher priority and prevents flickering because of + * underrun. This may still be an issue when using FLASH, + * since accessing data from Flash is so slow. + */ + debug ("[VIDEO CTRL] Turning on aggressive mode...\n"); + immap->im_siu_conf.sc_sdcr = 0x40; + + /* Turn on video controller */ + debug ("[VIDEO CTRL] Turning on video controller...\n"); + SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 1); + + /* Show the display */ + debug ("[VIDEO CTRL] Enabling the video...\n"); + SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_BD, 0); +} + +/************************************************************************/ +/* ** CONSOLE FUNCTIONS */ +/************************************************************************/ + +static void console_scrollup (void) +{ + /* Copy up rows ignoring the first one */ + memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE >> 2); + + /* Clear the last one */ + memsetl (CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, VIDEO_BG_COL); +} + +static inline void console_back (void) +{ + console_col--; + + if (console_col < 0) { + console_col = CONSOLE_COLS - 1; + console_row--; + if (console_row < 0) + console_row = 0; + } + + video_putchar ( console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, ' '); +} + +static inline void console_newline (void) +{ + console_row++; + console_col = 0; + + /* Check if we need to scroll the terminal */ + if (console_row >= CONSOLE_ROWS) { + /* Scroll everything up */ + console_scrollup (); + + /* Decrement row number */ + console_row--; + } +} + +void video_putc (const char c) +{ + if (!video_enable) { + serial_putc (c); + return; + } + + switch (c) { + case 13: /* Simply ignore this */ + break; + + case '\n': /* Next line, please */ + console_newline (); + break; + + case 9: /* Tab (8 chars alignment) */ + console_col |= 0x0008; /* Next 8 chars boundary */ + console_col &= ~0x0007; /* Set this bit to zero */ + + if (console_col >= CONSOLE_COLS) + console_newline (); + break; + + case 8: /* Eat last character */ + console_back (); + break; + + default: /* Add to the console */ + video_putchar ( console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, c); + console_col++; + /* Check if we need to go to next row */ + if (console_col >= CONSOLE_COLS) + console_newline (); + } +} + +void video_puts (const char *s) +{ + int count = strlen (s); + + if (!video_enable) + while (count--) + serial_putc (*s++); + else + while (count--) + video_putc (*s++); +} + +/************************************************************************/ +/* ** CURSOR BLINKING FUNCTIONS */ +/************************************************************************/ + +#ifdef VIDEO_BLINK + +#define BLINK_TIMER_ID 0 +#define BLINK_TIMER_HZ 2 + +static unsigned char blink_enabled = 0; +static timer_t blink_timer; + +static void blink_update (void) +{ + static int blink_row = -1, blink_col = -1, blink_old = 0; + + /* Check if we have a new position to invert */ + if ((console_row != blink_row) || (console_col != blink_col)) { + /* Check if we need to reverse last character */ + if (blink_old) + video_revchar ( blink_col * VIDEO_FONT_WIDTH, + (blink_row +#ifdef CONFIG_VIDEO_LOGO + + VIDEO_LOGO_HEIGHT +#endif + ) * VIDEO_FONT_HEIGHT); + + /* Update values */ + blink_row = console_row; + blink_col = console_col; + blink_old = 0; + } + +/* Reverse this character */ + blink_old = !blink_old; + video_revchar ( console_col * VIDEO_FONT_WIDTH, + (console_row +#ifdef CONFIG_VIDEO_LOGO + + VIDEO_LOGO_HEIGHT +#endif + ) * VIDEO_FONT_HEIGHT); + +} + +/* + * Handler for blinking cursor + */ +static void blink_handler (void *arg) +{ +/* Blink */ + blink_update (); +/* Ack the timer */ + timer_ack (&blink_timer); +} + +int blink_set (int blink) +{ + int ret = blink_enabled; + + if (blink) + timer_enable (&blink_timer); + else + timer_disable (&blink_timer); + + blink_enabled = blink; + + return ret; +} + +static inline void blink_close (void) +{ + timer_close (&blink_timer); +} + +static inline void blink_init (void) +{ + timer_init (&blink_timer, + BLINK_TIMER_ID, BLINK_TIMER_HZ, + blink_handler); +} +#endif + +/************************************************************************/ +/* ** LOGO PLOTTING FUNCTIONS */ +/************************************************************************/ + +#ifdef CONFIG_VIDEO_LOGO +void easylogo_plot (fastimage_t * image, void *screen, int width, int x, + int y) +{ + int skip = width - image->width, xcount, ycount = image->height; + +#ifdef VIDEO_MODE_YUYV + ushort *source = (ushort *) image->data; + ushort *dest = (ushort *) screen + y * width + x; + + while (ycount--) { + xcount = image->width; + while (xcount--) + *dest++ = *source++; + dest += skip; + } +#endif +#ifdef VIDEO_MODE_RGB + unsigned char + *source = (unsigned short *) image->data, + *dest = (unsigned short *) screen + ((y * width) + x) * 3; + + while (ycount--) { + xcount = image->width * 3; + memcpy (dest, source, xcount); + source += xcount; + dest += ycount; + } +#endif +} + +static void *video_logo (void) +{ + u16 *screen = video_fb_address, width = VIDEO_COLS; +#ifdef VIDEO_INFO +# ifndef CONFIG_FADS + DECLARE_GLOBAL_DATA_PTR; + char temp[32]; +# endif + char info[80]; +#endif /* VIDEO_INFO */ + + easylogo_plot (VIDEO_LOGO_ADDR, screen, width, 0, 0); + +#ifdef VIDEO_INFO + sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__); + video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info); + + sprintf (info, "(C) 2002 DENX Software Engineering"); + video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, + info); + + sprintf (info, " Wolfgang DENK, wd@denx.de"); + video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, + info); +#ifndef CONFIG_FADS /* all normal boards */ + /* leave one blank line */ + + sprintf (info, "MPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash", + strmhz(temp, gd->cpu_clk), + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); + video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4, + info); +#else /* FADS :-( */ + sprintf (info, "MPC823 CPU at 50 MHz on FADS823 board"); + video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, + info); + + sprintf (info, "2MB FLASH - 8MB DRAM - 4MB SRAM"); + video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, + info); +#endif +#endif + + return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN; +} +#endif + +/************************************************************************/ +/* ** VIDEO HIGH-LEVEL FUNCTIONS */ +/************************************************************************/ + +static int video_init (void *videobase) +{ + /* Initialize the encoder */ + debug ("[VIDEO] Initializing video encoder...\n"); + video_encoder_init (); + + /* Initialize the video controller */ + debug ("[VIDEO] Initializing video controller at %08x...\n", + (int) videobase); + video_ctrl_init (videobase); + + /* Setting the palette */ + video_setpalette (CONSOLE_COLOR_BLACK, 0, 0, 0); + video_setpalette (CONSOLE_COLOR_RED, 0xFF, 0, 0); + video_setpalette (CONSOLE_COLOR_GREEN, 0, 0xFF, 0); + video_setpalette (CONSOLE_COLOR_YELLOW, 0xFF, 0xFF, 0); + video_setpalette (CONSOLE_COLOR_BLUE, 0, 0, 0xFF); + video_setpalette (CONSOLE_COLOR_MAGENTA, 0xFF, 0, 0xFF); + video_setpalette (CONSOLE_COLOR_CYAN, 0, 0xFF, 0xFF); + video_setpalette (CONSOLE_COLOR_GREY, 0xAA, 0xAA, 0xAA); + video_setpalette (CONSOLE_COLOR_GREY2, 0xF8, 0xF8, 0xF8); + video_setpalette (CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF); + +#ifndef CFG_WHITE_ON_BLACK + video_setfgcolor (CONSOLE_COLOR_BLACK); + video_setbgcolor (CONSOLE_COLOR_GREY2); +#else + video_setfgcolor (CONSOLE_COLOR_GREY2); + video_setbgcolor (CONSOLE_COLOR_BLACK); +#endif /* CFG_WHITE_ON_BLACK */ + +#ifdef CONFIG_VIDEO_LOGO + /* Paint the logo and retrieve tv base address */ + debug ("[VIDEO] Drawing the logo...\n"); + video_console_address = video_logo (); +#else + video_console_address = video_fb_address; +#endif + +#ifdef VIDEO_BLINK + /* Enable the blinking (under construction) */ + blink_init (); + blink_set (0); /* To Fix! */ +#endif + + /* Initialize the console */ + console_col = 0; + console_row = 0; + video_enable = 1; + +#ifdef VIDEO_MODE_PAL +# define VIDEO_MODE_TMP1 "PAL" +#endif +#ifdef VIDEO_MODE_NTSC +# define VIDEO_MODE_TMP1 "NTSC" +#endif +#ifdef VIDEO_MODE_YUYV +# define VIDEO_MODE_TMP2 "YCbYCr" +#endif +#ifdef VIDEO_MODE_RGB +# define VIDEO_MODE_TMP2 "RGB" +#endif + debug ( VIDEO_MODE_TMP1 + " %dx%dx%d (" VIDEO_MODE_TMP2 ") on %s - console %dx%d\n", + VIDEO_COLS, VIDEO_ROWS, VIDEO_MODE_BPP, + VIDEO_ENCODER_NAME, CONSOLE_COLS, CONSOLE_ROWS); + return 0; +} + +int drv_video_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int error, devices = 1; + + device_t videodev; + + video_init ((void *)(gd->fb_base)); /* Video initialization */ + +/* Device initialization */ + + memset (&videodev, 0, sizeof (videodev)); + + strcpy (videodev.name, "video"); + videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ + videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ + videodev.putc = video_putc; /* 'putc' function */ + videodev.puts = video_puts; /* 'puts' function */ + + error = device_register (&videodev); + + return (error == 0) ? devices : error; +} + +/************************************************************************/ +/* ** ROM capable initialization part - needed to reserve FB memory */ +/************************************************************************/ + +/* + * This is called early in the system initialization to grab memory + * for the video controller. + * Returns new address for monitor, after reserving video buffer memory + * + * Note that this is running from ROM, so no write access to global data. + */ +ulong video_setmem (ulong addr) +{ + /* Allocate pages for the frame buffer. */ + addr -= VIDEO_SIZE; + + debug ("Reserving %dk for Video Framebuffer at: %08lx\n", + VIDEO_SIZE>>10, addr); + + return (addr); +} + +#endif diff --git a/cpu/mpc8xx/wlkbd.c b/cpu/mpc8xx/wlkbd.c new file mode 100644 index 0000000..13009e2 --- /dev/null +++ b/cpu/mpc8xx/wlkbd.c @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_WL_4PPM_KEYBOARD + +/* WIP: Wireless keyboard on SMC + */ +int drv_wlkbd_init (void) +{ + return 0 ; +} + +#endif /* CONFIG_WL_4PPM_KEYBOARD */ diff --git a/cpu/nios/Makefile b/cpu/nios/Makefile new file mode 100644 index 0000000..7855325 --- /dev/null +++ b/cpu/nios/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +AOBJS = traps.o +OBJS = cpu.o interrupts.o serial.o asmi.o spi.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) $(AOBJS) + $(AR) crv $@ $(OBJS) $(AOBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c new file mode 100644 index 0000000..ce2863e --- /dev/null +++ b/cpu/nios/asmi.c @@ -0,0 +1,695 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_NIOS_ASMI) +#include +#include + +#if !defined(CFG_NIOS_ASMIBASE) +#error "*** CFG_NIOS_ASMIBASE not defined ***" +#endif + +/*-----------------------------------------------------------------------*/ +#define SHORT_HELP\ + "asmi - read/write Cyclone ASMI configuration device.\n" + +#define LONG_HELP\ + "\n"\ + "asmi erase start [end]\n"\ + " - erase sector start or sectors start through end.\n"\ + "asmi info\n"\ + " - display ASMI device information.\n"\ + "asmi protect on | off\n"\ + " - turn device protection on or off.\n"\ + "asmi read addr offset count\n"\ + " - read count bytes from offset to addr.\n"\ + "asmi write addr offset count\n"\ + " - write count bytes to offset from addr.\n"\ + "asmi verify addr offset count\n"\ + " - verify count bytes at offset from addr.\n" + + +/*-----------------------------------------------------------------------*/ +/* Operation codes for serial configuration devices + */ +#define ASMI_WRITE_ENA 0x06 /* Write enable */ +#define ASMI_WRITE_DIS 0x04 /* Write disable */ +#define ASMI_READ_STAT 0x05 /* Read status */ +#define ASMI_READ_BYTES 0x03 /* Read bytes */ +#define ASMI_READ_ID 0xab /* Read silicon id */ +#define ASMI_WRITE_STAT 0x01 /* Write status */ +#define ASMI_WRITE_BYTES 0x02 /* Write bytes */ +#define ASMI_ERASE_BULK 0xc7 /* Erase entire device */ +#define ASMI_ERASE_SECT 0xd8 /* Erase sector */ + +/* Device status register bits + */ +#define ASMI_STATUS_WIP (1<<0) /* Write in progress */ +#define ASMI_STATUS_WEL (1<<1) /* Write enable latch */ + +static nios_asmi_t *asmi = (nios_asmi_t *)CFG_NIOS_ASMIBASE; + +/*********************************************************************** + * Device access + ***********************************************************************/ +static void asmi_cs (int assert) +{ + if (assert) { + asmi->control |= NIOS_ASMI_SSO; + } else { + /* Let all bits shift out */ + while ((asmi->status & NIOS_ASMI_TMT) == 0) + ; + asmi->control &= ~NIOS_ASMI_SSO; + } +} + +static void asmi_tx (unsigned char c) +{ + while ((asmi->status & NIOS_ASMI_TRDY) == 0) + ; + asmi->txdata = c; +} + +static int asmi_rx (void) +{ + while ((asmi->status & NIOS_ASMI_RRDY) == 0) + ; + return (asmi->rxdata); +} + +static unsigned char bitrev[] = { + 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, + 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f +}; + +static unsigned char asmi_bitrev( unsigned char c ) +{ + unsigned char val; + + val = bitrev[c>>4]; + val |= bitrev[c & 0x0f]<<4; + return (val); +} + +static void asmi_rcv (unsigned char *dst, int len) +{ + while (len--) { + asmi_tx (0); + *dst++ = asmi_rx (); + } +} + +static void asmi_rrcv (unsigned char *dst, int len) +{ + while (len--) { + asmi_tx (0); + *dst++ = asmi_bitrev (asmi_rx ()); + } +} + +static void asmi_snd (unsigned char *src, int len) +{ + while (len--) { + asmi_tx (*src++); + asmi_rx (); + } +} + +static void asmi_rsnd (unsigned char *src, int len) +{ + while (len--) { + asmi_tx (asmi_bitrev (*src++)); + asmi_rx (); + } +} + +static void asmi_wr_enable (void) +{ + asmi_cs (1); + asmi_tx (ASMI_WRITE_ENA); + asmi_rx (); + asmi_cs (0); +} + +static unsigned char asmi_status_rd (void) +{ + unsigned char status; + + asmi_cs (1); + asmi_tx (ASMI_READ_STAT); + asmi_rx (); + asmi_tx (0); + status = asmi_rx (); + asmi_cs (0); + return (status); +} + +static void asmi_status_wr (unsigned char status) +{ + asmi_wr_enable (); + asmi_cs (1); + asmi_tx (ASMI_WRITE_STAT); + asmi_rx (); + asmi_tx (status); + asmi_rx (); + asmi_cs (0); + return; +} + +/*********************************************************************** + * Device information + ***********************************************************************/ +typedef struct asmi_devinfo_t { + const char *name; /* Device name */ + unsigned char id; /* Device silicon id */ + unsigned char size; /* Total size log2(bytes)*/ + unsigned char num_sects; /* Number of sectors */ + unsigned char sz_sect; /* Sector size log2(bytes) */ + unsigned char sz_page; /* Page size log2(bytes) */ + unsigned char prot_mask; /* Protection mask */ +}asmi_devinfo_t; + +static struct asmi_devinfo_t devinfo[] = { + { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, + { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, + { 0, 0, 0, 0, 0, 0 } +}; + +static asmi_devinfo_t *asmi_dev_find (void) +{ + unsigned char buf[4]; + unsigned char id; + int i; + struct asmi_devinfo_t *dev = NULL; + + /* Read silicon id requires 3 "dummy bytes" before it's put + * on the wire. + */ + buf[0] = ASMI_READ_ID; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + asmi_cs (1); + asmi_snd (buf,4); + asmi_rcv (buf,1); + asmi_cs (0); + id = buf[0]; + + /* Find the info struct */ + i = 0; + while (devinfo[i].name) { + if (id == devinfo[i].id) { + dev = &devinfo[i]; + break; + } + i++; + } + + return (dev); +} + +/*********************************************************************** + * Misc Utilities + ***********************************************************************/ +static unsigned asmi_cfgsz (void) +{ + unsigned sz = 0; + unsigned char buf[128]; + unsigned char *p; + + /* Read in the first 128 bytes of the device */ + buf[0] = ASMI_READ_BYTES; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + asmi_cs (1); + asmi_snd (buf,4); + asmi_rrcv (buf, sizeof(buf)); + asmi_cs (0); + + /* Search for the starting 0x6a which is followed by the + * 4-byte 'register' and 4-byte bit-count. + */ + p = buf; + while (p < buf + sizeof(buf)-8) { + if ( *p == 0x6a ) { + /* Point to bit count and extract */ + p += 5; + sz = *p++; + sz |= *p++ << 8; + sz |= *p++ << 16; + sz |= *p++ << 24; + /* Convert to byte count */ + sz += 7; + sz >>= 3; + } else if (*p == 0xff) { + /* 0xff is ok ... just skip */ + p++; + continue; + } else { + /* Not 0xff or 0x6a ... something's not + * right ... report 'unknown' (sz=0). + */ + break; + } + } + return (sz); +} + +static int asmi_erase (unsigned start, unsigned end) +{ + unsigned off, sectsz; + unsigned char buf[4]; + struct asmi_devinfo_t *dev = asmi_dev_find (); + + if (!dev || (start>end)) + return (-1); + + /* Erase the requested sectors. An address is required + * that lies within the requested sector -- we'll just + * use the first address in the sector. + */ + printf ("asmi erasing sector %d ", start); + if (start != end) + printf ("to %d ", end); + sectsz = (1 << dev->sz_sect); + while (start <= end) { + off = start * sectsz; + start++; + + buf[0] = ASMI_ERASE_SECT; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + asmi_wr_enable (); + asmi_cs (1); + asmi_snd (buf,4); + asmi_cs (0); + + printf ("."); /* Some user feedback */ + + /* Wait for erase to complete */ + while (asmi_status_rd() & ASMI_STATUS_WIP) + ; + } + printf (" done.\n"); + return (0); +} + +static int asmi_read (ulong addr, ulong off, ulong cnt) +{ + unsigned char buf[4]; + + buf[0] = ASMI_READ_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + asmi_cs (1); + asmi_snd (buf,4); + asmi_rrcv ((unsigned char *)addr, cnt); + asmi_cs (0); + + return (0); +} + +static +int asmi_write (ulong addr, ulong off, ulong cnt) +{ + ulong wrcnt; + unsigned pgsz; + unsigned char buf[4]; + struct asmi_devinfo_t *dev = asmi_dev_find (); + + if (!dev) + return (-1); + + pgsz = (1<sz_page); + while (cnt) { + if (off % pgsz) + wrcnt = pgsz - (off % pgsz); + else + wrcnt = pgsz; + wrcnt = (wrcnt > cnt) ? cnt : wrcnt; + + buf[0] = ASMI_WRITE_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + asmi_wr_enable (); + asmi_cs (1); + asmi_snd (buf,4); + asmi_rsnd ((unsigned char *)addr, wrcnt); + asmi_cs (0); + + /* Wait for write to complete */ + while (asmi_status_rd() & ASMI_STATUS_WIP) + ; + + cnt -= wrcnt; + off += wrcnt; + addr += wrcnt; + } + + return (0); +} + +static +int asmi_verify (ulong addr, ulong off, ulong cnt, ulong *err) +{ + ulong rdcnt; + unsigned char buf[256]; + unsigned char *start,*end; + int i; + + start = end = (unsigned char *)addr; + while (cnt) { + rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; + asmi_read ((ulong)buf, off, rdcnt); + for (i=0; isz_sect); + off = sectsz * sect; + end = off + sectsz; + + while (off < end) { + asmi_read ((ulong)buf, off, sizeof(buf)); + for (i=0; i < sizeof(buf); i++) { + if (buf[i] != 0xff) { + *offset = off + i; + return (0); + } + } + off += sizeof(buf); + } + return (1); +} + + +/*********************************************************************** + * Commands + ***********************************************************************/ +static +void do_asmi_info (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + int i; + unsigned char stat; + unsigned tmp; + int erased; + + /* Basic device info */ + printf ("%s: %d kbytes (%d sectors x %d kbytes," + " %d bytes/page)\n", + dev->name, 1 << (dev->size-10), + dev->num_sects, 1 << (dev->sz_sect-10), + 1 << dev->sz_page ); + + /* Status -- for now protection is all-or-nothing */ + stat = asmi_status_rd(); + printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", + stat, + (stat & ASMI_STATUS_WIP) ? 1 : 0, + (stat & ASMI_STATUS_WEL) ? 1 : 0, + (stat & dev->prot_mask) ? "on" : "off" ); + + /* Configuration */ + tmp = asmi_cfgsz (); + if (tmp) { + printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); + } else { + printf ("config: unknown\n" ); + } + + /* Sector info */ + for (i=0; inum_sects; i++) { + erased = asmi_sect_erased (i, &tmp, dev); + printf (" %d: %06x ", + i, i*(1<sz_sect) ); + if (erased) + printf ("erased\n"); + else + printf ("data @ 0x%06x\n", tmp); + } + + return; +} + +static +void do_asmi_erase (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned start,end; + + if ((argc < 3) || (argc > 4)) { + printf ("USAGE: asmi erase sect [end]\n"); + return; + } + if ((asmi_status_rd() & dev->prot_mask) != 0) { + printf ( "asmi: device protected.\n"); + return; + } + + start = simple_strtoul (argv[2], NULL, 10); + if (argc > 3) + end = simple_strtoul (argv[3], NULL, 10); + else + end = start; + if ((start >= dev->num_sects) || (start > end)) { + printf ("asmi: invalid sector range: [%d:%d]\n", + start, end ); + return; + } + + asmi_erase (start, end); + + return; +} + +static +void do_asmi_protect (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned char stat; + + /* For now protection is all-or-nothing to keep things + * simple. The protection bits don't map in a linear + * fashion ... and we would rather protect the bottom + * of the device since it contains the config data and + * leave the top unprotected for app use. But unfortunately + * protection works from top-to-bottom so it does + * really help very much from a software app point-of-view. + */ + if (argc < 3) { + printf ("USAGE: asmi protect on | off\n"); + return; + } + if (!dev) + return; + + /* Protection on/off is just a matter of setting/clearing + * all protection bits in the status register. + */ + stat = asmi_status_rd (); + if (strcmp ("on", argv[2]) == 0) { + stat |= dev->prot_mask; + } else if (strcmp ("off", argv[2]) == 0 ) { + stat &= ~dev->prot_mask; + } else { + printf ("asmi: unknown protection: %s\n", argv[2]); + return; + } + asmi_status_wr (stat); + return; +} + +static +void do_asmi_read (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + + if (argc < 5) { + printf ("USAGE: asmi read addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("asmi: read %08lx <- %06lx (0x%lx bytes)\n", + addr, off, cnt); + asmi_read (addr, off, cnt); + + return; +} + +static +void do_asmi_write (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: asmi write addr offset count\n"); + return; + } + if ((asmi_status_rd() & dev->prot_mask) != 0) { + printf ( "asmi: device protected.\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("asmi: write %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + asmi_write (addr, off, cnt); + if (asmi_verify (addr, off, cnt, &err) != 0) + printf ("asmi: write error at offset %06lx\n", err); + + return; +} + +static +void do_asmi_verify (struct asmi_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: asmi verify addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("asmi: verify %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + if (asmi_verify (addr, off, cnt, &err) != 0) + printf ("asmi: verify error at offset %06lx\n", err); + + return; +} + +/*-----------------------------------------------------------------------*/ +int do_asmi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int len; + struct asmi_devinfo_t *dev = asmi_dev_find (); + + if (argc < 2) { + printf ("Usage:%s", LONG_HELP); + return (0); + } + + if (!dev) { + printf ("asmi: device not found.\n"); + return (0); + } + + len = strlen (argv[1]); + if (strncmp ("info", argv[1], len) == 0) { + do_asmi_info ( dev, argc, argv); + } else if (strncmp ("erase", argv[1], len) == 0) { + do_asmi_erase (dev, argc, argv); + } else if (strncmp ("protect", argv[1], len) == 0) { + do_asmi_protect (dev, argc, argv); + } else if (strncmp ("read", argv[1], len) == 0) { + do_asmi_read (dev, argc, argv); + } else if (strncmp ("write", argv[1], len) == 0) { + do_asmi_write (dev, argc, argv); + } else if (strncmp ("verify", argv[1], len) == 0) { + do_asmi_verify (dev, argc, argv); + } else { + printf ("asmi: unknown operation: %s\n", argv[1]); + } + + return (0); +} + +/*-----------------------------------------------------------------------*/ + + +U_BOOT_CMD( asmi, 5, 0, do_asmi, SHORT_HELP, LONG_HELP ); + +#endif /* CONFIG_NIOS_ASMI */ diff --git a/cpu/nios/config.mk b/cpu/nios/config.mk new file mode 100644 index 0000000..f228d72 --- /dev/null +++ b/cpu/nios/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += diff --git a/cpu/nios/cpu.c b/cpu/nios/cpu.c new file mode 100644 index 0000000..d2bb2c0 --- /dev/null +++ b/cpu/nios/cpu.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +int checkcpu (void) +{ + unsigned val; + unsigned rev_major; + unsigned rev_minor; + short nregs, hi_limit, lo_limit; + + /* Get cpu version info */ + val = rdctl (CTL_CPU_ID); + printf ("CPU: "); + printf ("%s", (val & 0x00008000) ? "Nios-16 " : "Nios-32 "); + rev_major = (val>>12) & 0x07; + rev_minor = (val>>4) & 0x0ff; + printf ("Rev. %d.%d (0x%04x)", rev_major, rev_minor, + val & 0xffff); + if (rev_major == 0x08) + printf (" [OpenCore (R) Plus]"); + printf ("\n"); + + /* Check register file */ + val = rdctl (CTL_WVALID); + lo_limit = val & 0x01f; + hi_limit = (val>>5) & 0x1f; + nregs = (hi_limit + 2) * 16; + printf ("Reg file size: %d LO_LIMIT/HI_LIMIT: %d/%d\n", + nregs, lo_limit, hi_limit); + + return (0); +} + + +int do_reset (void) +{ + /* trap 0 does the trick ... at least with the OCI debug + * present -- haven't tested without it yet (stm). + */ + disable_interrupts (); + ipri (1); + asm volatile ("trap 0\n"); + + /* No return ;-) */ + + return(0); +} + + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ +} +#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/nios/interrupts.c b/cpu/nios/interrupts.c new file mode 100644 index 0000000..48fc81e --- /dev/null +++ b/cpu/nios/interrupts.c @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_STATUS_LED +#include +#endif + +/****************************************************************************/ + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + int count; +}; + +static struct irq_action irq_vecs[64]; + +/*************************************************************************/ +volatile ulong timestamp = 0; + +void reset_timer (void) +{ + timestamp = 0; +} + +ulong get_timer (ulong base) +{ + WATCHDOG_RESET (); + return (timestamp - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} + + +/* The board must handle this interrupt if a timer is not + * provided. + */ +#if defined(CFG_NIOS_TMRBASE) +void timer_interrupt (struct pt_regs *regs) +{ + /* Interrupt is cleared by writing anything to the + * status register. + */ + nios_timer_t *tmr = (nios_timer_t *)CFG_NIOS_TMRBASE; + tmr->status = 0; + timestamp += CFG_NIOS_TMRMS; +#ifdef CONFIG_STATUS_LED + status_led_tick(timestamp); +#endif +} +#endif + +/*************************************************************************/ +int disable_interrupts (void) +{ + int val = 0; + + /* Writing anything to CLR_IE disables interrupts */ + val = rdctl (CTL_STATUS); + wrctl (CTL_CLR_IE, 0); + return (val & STATUS_IE); +} + +void enable_interrupts( void ) +{ + /* Writing anything SET_IE enables interrupts */ + wrctl (CTL_SET_IE, 0); +} + +void external_interrupt (struct pt_regs *regs) +{ + unsigned vec; + + vec = (regs->status & STATUS_IPRI) >> 9; /* ipri */ + + irq_vecs[vec].count++; + if (irq_vecs[vec].handler != NULL) { + (*irq_vecs[vec].handler)(irq_vecs[vec].arg); + } else { + /* A sad side-effect of masking a bogus interrupt is + * that lower priority interrupts will also be disabled. + * This is probably not what we want ... so hang insted. + */ + printf ("Unhandled interrupt: 0x%x\n", vec); + disable_interrupts (); + hang (); + } +} + +/*************************************************************************/ +int interrupt_init (void) +{ + int vec; + +#if defined(CFG_NIOS_TMRBASE) + nios_timer_t *tmr = (nios_timer_t *)CFG_NIOS_TMRBASE; + + tmr->control &= ~NIOS_TIMER_ITO; + tmr->control |= NIOS_TIMER_STOP; +#if defined(CFG_NIOS_TMRCNT) + tmr->periodl = CFG_NIOS_TMRCNT & 0xffff; + tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff; +#endif +#endif + + for (vec=0; vec<64; vec++ ) { + irq_vecs[vec].handler = NULL; + irq_vecs[vec].arg = NULL; + irq_vecs[vec].count = 0; + } + + /* Need timus interruptus -- start the lopri timer */ +#if defined(CFG_NIOS_TMRBASE) + tmr->control |= ( NIOS_TIMER_ITO | + NIOS_TIMER_CONT | + NIOS_TIMER_START ); + ipri (CFG_NIOS_TMRIRQ + 1); +#endif + enable_interrupts (); + return (0); +} + +void irq_install_handler (int vec, interrupt_handler_t *handler, void *arg) +{ + struct irq_action *irqa = irq_vecs; + int i = vec; + int flag; + + if (irqa[i].handler != NULL) { + printf ("Interrupt vector %d: handler 0x%x " + "replacing 0x%x\n", + vec, (uint)handler, (uint)irqa[i].handler); + } + + flag = disable_interrupts (); + irqa[i].handler = handler; + irqa[i].arg = arg; + if (flag ) + enable_interrupts (); +} + +/*************************************************************************/ +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int vec; + + printf ("\nInterrupt-Information:\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<64; vec++) { + if (irq_vecs[vec].handler != NULL) { + printf ("%02d %08lx %08lx %d\n", + vec, + (ulong)irq_vecs[vec].handler<<1, + (ulong)irq_vecs[vec].arg, + irq_vecs[vec].count); + } + } + + return (0); +} +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/nios/serial.c b/cpu/nios/serial.c new file mode 100644 index 0000000..4bdda25 --- /dev/null +++ b/cpu/nios/serial.c @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include + +/*------------------------------------------------------------------ + * JTAG acts as the serial port + *-----------------------------------------------------------------*/ +#if defined(CONFIG_CONSOLE_JTAG) + +static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE; + +void serial_setbrg( void ){ return; } +int serial_init( void ) { return(0);} + +void serial_putc (char c) +{ + while ((jtag->txcntl & NIOS_JTAG_TRDY) != 0) + WATCHDOG_RESET (); + jtag->txcntl = NIOS_JTAG_TRDY | (unsigned char)c; +} + +void serial_puts (const char *s) +{ + while (*s != 0) + serial_putc (*s++); +} + +int serial_tstc (void) +{ + return (jtag->rxcntl & NIOS_JTAG_RRDY); +} + +int serial_getc (void) +{ + int c; + while (serial_tstc() == 0) + WATCHDOG_RESET (); + c = jtag->rxcntl & 0x0ff; + jtag->rxcntl = 0; + return (c); +} + +/*------------------------------------------------------------------ + * UART the serial port + *-----------------------------------------------------------------*/ +#else + +static nios_uart_t *uart = (nios_uart_t *)CFG_NIOS_CONSOLE; + +#if defined(CFG_NIOS_FIXEDBAUD) + +/* Everything's already setup for fixed-baud PTF + * assignment + */ +void serial_setbrg (void){ return; } +int serial_init (void) { return (0);} + +#else + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned div; + + div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; + uart->divisor = div; + return; +} + +int serial_init (void) +{ + serial_setbrg (); + return (0); +} + +#endif /* CFG_NIOS_FIXEDBAUD */ + + +/*----------------------------------------------------------------------- + * UART CONSOLE + *---------------------------------------------------------------------*/ +void serial_putc (char c) +{ + if (c == '\n') + serial_putc ('\r'); + while ((uart->status & NIOS_UART_TRDY) == 0) + WATCHDOG_RESET (); + uart->txdata = (unsigned char)c; +} + +void serial_puts (const char *s) +{ + while (*s != 0) { + serial_putc (*s++); + } +} + +int serial_tstc (void) +{ + return (uart->status & NIOS_UART_RRDY); +} + +int serial_getc (void) +{ + while (serial_tstc () == 0) + WATCHDOG_RESET (); + return( uart->rxdata & 0x00ff ); +} + +#endif /* CONFIG_JTAG_CONSOLE */ diff --git a/cpu/nios/spi.c b/cpu/nios/spi.c new file mode 100644 index 0000000..f37146b --- /dev/null +++ b/cpu/nios/spi.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_NIOS_SPI) +#include +#include + +#if !defined(CFG_NIOS_SPIBASE) +#error "*** CFG_NIOS_SPIBASE not defined ***" +#endif + +#if !defined(CFG_NIOS_SPIBITS) +#error "*** CFG_NIOS_SPIBITS not defined ***" +#endif + +#if (CFG_NIOS_SPIBITS != 8) && (CFG_NIOS_SPIBITS != 16) +#error "*** CFG_NIOS_SPIBITS should be either 8 or 16 ***" +#endif + +static nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; + +/* Warning: + * You cannot enable DEBUG for early system initalization, i. e. when + * this driver is used to read environment parameters like "baudrate" + * from EEPROM which are used to initialize the serial port which is + * needed to print the debug messages... + */ +#undef DEBUG + +#ifdef DEBUG + +#define DPRINT(a) printf a; +/* ----------------------------------------------- + * Helper functions to peek into tx and rx buffers + * ----------------------------------------------- */ +static const char * const hex_digit = "0123456789ABCDEF"; + +static char quickhex (int i) +{ + return hex_digit[i]; +} + +static void memdump (void *pv, int num) +{ + int i; + unsigned char *pc = (unsigned char *) pv; + + for (i = 0; i < num; i++) + printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); + printf ("\t"); + for (i = 0; i < num; i++) + printf ("%c", isprint (pc[i]) ? pc[i] : '.'); + printf ("\n"); +} +#else /* !DEBUG */ + +#define DPRINT(a) +#define memdump(p,n) + +#endif /* DEBUG */ + + +/* + * SPI transfer: + * + * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf + * for more informations. + */ +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +{ + int j; + + DPRINT(("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", + (int)chipsel, *(uint *)dout, *(uint *)din, bitlen)); + + memdump((void*)dout, (bitlen + 7) / 8); + + if(chipsel != NULL) { + chipsel(1); /* select the target chip */ + } + + if (bitlen > CFG_NIOS_SPIBITS) { /* leave chip select active */ + spi->control |= NIOS_SPI_SSO; + } + + for ( j = 0; /* count each byte in */ + j < ((bitlen + 7) / 8); /* dout[] and din[] */ + +#if (CFG_NIOS_SPIBITS == 8) + j++) { + + while ((spi->status & NIOS_SPI_TRDY) == 0) + ; + spi->txdata = (unsigned)(dout[j]); + + while ((spi->status & NIOS_SPI_RRDY) == 0) + ; + din[j] = (unsigned char)(spi->rxdata & 0xff); + +#elif (CFG_NIOS_SPIBITS == 16) + j++, j++) { + + while ((spi->status & NIOS_SPI_TRDY) == 0) + ; + if ((j+1) < ((bitlen + 7) / 8)) + spi->txdata = (unsigned)((dout[j] << 8) | dout[j+1]); + else + spi->txdata = (unsigned)(dout[j] << 8); + + while ((spi->status & NIOS_SPI_RRDY) == 0) + ; + din[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); + if ((j+1) < ((bitlen + 7) / 8)) + din[j+1] = (unsigned char)(spi->rxdata & 0xff); + +#else +#error "*** unsupported value of CFG_NIOS_SPIBITS ***" +#endif + + } + + if (bitlen > CFG_NIOS_SPIBITS) { + spi->control &= ~NIOS_SPI_SSO; + } + + if(chipsel != NULL) { + chipsel(0); /* deselect the target chip */ + } + + memdump((void*)din, (bitlen + 7) / 8); + + return 0; +} + +#endif /* CONFIG_NIOS_SPI */ diff --git a/cpu/nios/start.S b/cpu/nios/start.S new file mode 100644 index 0000000..cb1af3c --- /dev/null +++ b/cpu/nios/start.S @@ -0,0 +1,237 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#if !defined(CONFIG_IDENT_STRING) +#define CONFIG_IDENT_STRING "" +#endif + +#define STATUS_INIT 0x8600 /* IE=1, IPRI=2 */ + +/************************************************************************* + * RESTART + ************************************************************************/ + + .text + .global _start + +_start: + bsr 0f + nop + .long _start + + /* GERMS -- The "standard-32" configuration GERMS monitor looks + * for the string "Nios" at flash_base + 0xc (actually it only + * tests for 'N', 'i'). You can leave support for this in place + * as it's only a few words. + */ + . = _start + 0x000c + .string "Nios" + + .align 4 +0: + /* + * Early setup -- set cwp = HI_LIMIT, IPRI = 2, IE = 1 to + * enable underflow exceptions. Disable cache. + * NOTE: %o7 has return addr -- save in %g7 use later. + */ + mov %g7, %o7 + + pfx 2 /* WVALID */ + rdctl %g0 + lsri %g0, 1 + pfx %hi(STATUS_INIT) + or %g0, %lo(STATUS_INIT) + wrctl %g0 /* update status */ + nop + + /* + * STACK + */ + pfx %hi(CFG_INIT_SP) + movi %sp, %lo(CFG_INIT_SP) + pfx %xhi(CFG_INIT_SP) + movhi %sp, %xlo(CFG_INIT_SP) + mov %fp, %sp + + pfx %hi(4*16) + subi %sp, %lo(4*16) /* Space for reg window mgmt */ + + /* + * RELOCATE -- %g7 has return addr from bsr at _start. + */ + pfx %hi(__u_boot_cmd_end) + movi %g5, %lo(__u_boot_cmd_end) + pfx %xhi(__u_boot_cmd_end) + movhi %g5, %xlo(__u_boot_cmd_end) /* %g5 <- end address */ + + lsli %g7, 1 /* mem = retaddr << 1 */ + mov %g6, %g7 + subi %g6, 4 /* %g6 <- src addr */ + ld %g7, [%g7] /* %g7 <- dst addr */ + + /* No need to move text sections if we're already located + * at the proper address. + */ + cmp %g7, %g6 + ifs cc_z + br reloc + nop /* delay slot */ + +1: cmp %g7, %g5 + skps cc_nz + br 2f + nop /* delay slot */ + + ld %g0, [%g6] + addi %g6, 4 /* src++ */ + st [%g7], %g0 + addi %g7, 4 /* dst++ */ + br 1b + nop /* delay slot */ +2: + + /* + * Jump to relocation address + */ + pfx %hi(reloc@h) + movi %g0, %lo(reloc@h) + pfx %xhi(reloc@h) + movhi %g0, %xlo(reloc@h) + jmp %g0 + nop /* delay slot */ +reloc: + + /* + * CLEAR BSS + */ + pfx %hi(__bss_end) + movi %g5, %lo(__bss_end) + pfx %xhi(__bss_end) + movhi %g5, %xlo(__bss_end) /* %g5 <- end address */ + pfx %hi(__bss_start) + movi %g7, %lo(__bss_start) + pfx %xhi(__bss_start) + movhi %g7, %xlo(__bss_start) /* %g7 <- end address */ + + movi %g0, 0 +3: cmp %g7, %g5 + skps cc_nz + br 4f + nop /* delay slot */ + + st [%g7], %g0 + addi %g7, 4 /* (delay slot) dst++ */ + br 3b + nop /* delay slot */ +4: + + /* + * INIT VECTOR TABLE + */ + pfx %hi(CFG_VECT_BASE) + movi %g0, %lo(CFG_VECT_BASE) + pfx %xhi(CFG_VECT_BASE) + movhi %g0, %xlo(CFG_VECT_BASE) /* dst */ + mov %l0, %g0 + + pfx %hi(_vectors) + movi %g1, %lo(_vectors) + pfx %xhi(_vectors) + movhi %g1, %xlo(_vectors) /* src */ + bgen %g2, 6 /* cnt = 64 */ + + ldp %g3, [%l0, 3] /* bkpt vector */ + ldp %g4, [%l0, 4] /* single step vector */ + +5: ld %g7, [%g1] + addi %g1, 4 /* src++ */ + st [%g0], %g7 + addi %g0, 4 /* dst++ */ + + subi %g2, 1 /* cnt-- */ + ifrnz %g2 + br 5b + nop /* delay slot */ + +#if defined(CONFIG_ROM_STUBS) + /* Restore the breakpoint and single step exception + * vectors to their original values. + */ + stp [%l0,3], %g3 /* breakpoint */ + stp [%l0,4], %g4 /* single step */ +#endif + + /* For debug startup convenience ... software breakpoints + * set prior to this point may not succeed ;-) + */ + .global __start +__start: + + /* + * Call board_init -- never returns + */ + pfx %hi(board_init@h) + movi %g1, %lo(board_init@h) + pfx %xhi(board_init@h) + movhi %g1, %xlo(board_init@h) + call %g1 + nop /* Delaly slot */ + /* NEVER RETURNS */ + +/* + * dly_clks -- Nios doesn't have a time/clk reference for simple + * delay loops, so we do our best by counting instruction cycles. + * A control register that counts system clock cycles would be + * a handy feature -- hint for Altera ;-) + */ + .globl dly_clks + /* Each loop is 4 instructions as delay slot is always + * executed. Each instruction is approximately 4 clocks + * (according to some lame info from Altera). So ... + * ... each loop is about 16 clocks. + */ + +dly_clks: + lsri %o0, 4 /* cnt/16 */ + +8: skprnz %o0 + br 9f + subi %o0, 1 /* cnt--, Delay slot */ + br 8b + nop + +9: lret + nop /* Delay slot */ + + + .data + .globl version_string + +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/cpu/nios/traps.S b/cpu/nios/traps.S new file mode 100644 index 0000000..bc4d3f6 --- /dev/null +++ b/cpu/nios/traps.S @@ -0,0 +1,582 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/************************************************************************* + * Register window underflow + * + * The register window underflow exception occurs whenever the lowest + * valid register window is in use (CWP=LO_LIMIT) and a save instruction + * is issued. The save moves CWP below LO_LIMIT, %sp is set as normal, + * then the exception is generated prior to executing the instruction + * after the save. + ************************************************************************/ + .text + .global _cwp_lolimit + .align 4 + +_cwp_lolimit: + + /* Sixteen words are always allocated by the compiler in every + * procedure's stack frame, always starting at %sp, for saving + * 'in' and 'local' registers on a window overflow. + * + * Save the 'global' and 'in' regs on stack. They are restored + * at cwp = HI_LIMIT. The 'local' regs aren't in-use at this point. + */ + sts [%sp,0], %g0 /* Save 'global' regs*/ + sts [%sp,1], %g1 + sts [%sp,2], %g2 + sts [%sp,3], %g3 + sts [%sp,4], %g4 + sts [%sp,5], %g5 + sts [%sp,6], %g6 + sts [%sp,7], %g7 + + sts [%sp,8], %i0 /* Save 'in' regs */ + sts [%sp,9], %i1 + sts [%sp,10], %i2 + sts [%sp,11], %i3 + sts [%sp,12], %i4 + sts [%sp,13], %i5 + sts [%sp,14], %i6 + sts [%sp,15], %i7 + + /* Save current %sp and return address in a global so they are + * available at cwp = HI_LIMIT ... where the 'global'/'in' regs + * are restored. NOTE: %sp changes with cwp. + */ + mov %g7, %o7 + mov %g6, %sp + + /* Get LO_LIMIT/HI_LIMIT to know where to start & stop. Note: in + * the underflow exception, cwp is __NOT__ guaranteed to be zero. + * If the OCI debug module is enabled the reset value for LO_LIMIT + * is 2, not 1 -- so cwp can be 1 or 0. + */ + pfx 2 /* WVALID */ + rdctl %g1 + mov %g2, %g1 + pfx 0 + and %g1, 0x1f /* g1 <- LO_LIMIT */ + lsri %g2, 5 + pfx 0 + and %g2,0x1f /* g2 <- HI_LIMIT */ + + /* Set istatus so cwp = HI_LIMIT after tret + */ + movi %g5, 0x1f + lsli %g5, 4 + not %g5 /* mask to clr cwp */ + pfx 1 /* istatus */ + rdctl %g0 + and %g0, %g5 /* clear cwp field */ + + mov %g4, %g2 + lsli %g4, 4 + or %g0, %g4 /* cwp = HI_LIMIT */ + pfx 1 + wrctl %g0 /* update istatus */ + + /* Now move up the register file, saving as we go. When loop + * is first entered, %g1 is at LO_LIMIT. + */ +0: + restore /* cwp++ */ + sts [%sp,0], %l0 /* Save "local" regs*/ + sts [%sp,1], %l1 + sts [%sp,2], %l2 + sts [%sp,3], %l3 + sts [%sp,4], %l4 + sts [%sp,5], %l5 + sts [%sp,6], %l6 + sts [%sp,7], %l7 + + sts [%sp,8], %i0 /* Save 'in' regs */ + sts [%sp,9], %i1 + sts [%sp,10], %i2 + sts [%sp,11], %i3 + sts [%sp,12], %i4 + sts [%sp,13], %i5 + sts [%sp,14], %i6 + sts [%sp,15], %i7 + + cmp %g1, %g2 /* cwp == HI_LIMIT ? */ + skps cc_ne /* if so, we're done */ + br 1f + nop /* delay slot */ + + inc %g1 /* g1 <- cwp++ */ + br 0b + nop /* delay slot */ + + /* At this point cwp = HI_LIMIT, so the global/in regs that were + * in place when the underflow occurred must be restored using + * the original stack pointer (saved in g6). + */ +1: + mov %o7, %g7 /* restore return addr */ + mov %sp, %g6 /* Restore original sp */ + + lds %g0, [%sp,0] /* Restore 'global' regs*/ + lds %g1, [%sp,1] + lds %g2, [%sp,2] + lds %g3, [%sp,3] + lds %g4, [%sp,4] + lds %g5, [%sp,5] + lds %g6, [%sp,6] + lds %g7, [%sp,7] + + lds %i0, [%sp,8] /* Restore 'in' regs*/ + lds %i1, [%sp,9] + lds %i2, [%sp,10] + lds %i3, [%sp,11] + lds %i4, [%sp,12] + lds %i5, [%sp,13] + lds %i6, [%sp,14] + lds %i7, [%sp,15] + + tret %o7 /* All done */ + +/************************************************************************* + * Register window overflow + * + * The register window overflow exception occurs whenever the highest + * valid register window is in use (cwp = HI_LIMIT) and a restore + * instruction is issued. Control is transferred to the overflow handler + * before the instruction following restore is executed. + * + * When a register window overflow exception is taken, the exception + * handler sees cwp at HI_LIMIT. + ************************************************************************/ + .text + .global _cwp_hilimit + .align 4 + +_cwp_hilimit: + + /* Save 'global'/'in' regs on the stack -- will restore when cwp + * is at LO_LIMIT. Locals don't need saving as they are going away. + */ + sts [%sp,0], %g0 /* Save "global" regs*/ + sts [%sp,1], %g1 + sts [%sp,2], %g2 + sts [%sp,3], %g3 + sts [%sp,4], %g4 + sts [%sp,5], %g5 + sts [%sp,6], %g6 + sts [%sp,7], %g7 + + sts [%sp,8], %i0 /* Save 'in' regs */ + sts [%sp,9], %i1 + sts [%sp,10], %i2 + sts [%sp,11], %i3 + sts [%sp,12], %i4 + sts [%sp,13], %i5 + sts [%sp,14], %i6 + sts [%sp,15], %i7 + + /* The current %sp must be available in global to restore regs + * saved on stack. Need return addr as well ;-) + */ + mov %g7, %o7 + mov %g6, %sp + + /* Get HI_LIMIT & LO_LIMIT + */ + pfx 2 /* WVALID */ + rdctl %g1 + mov %g2, %g1 + pfx 0 + and %g1, 0x1f /* g1 <- LO_LIMIT */ + lsri %g2, 5 + pfx 0 + and %g2,0x1f /* g2 <- HI_LIMIT */ + + /* Set istatus so cwp = LO_LIMIT after tret + */ + movi %g5, 0x1f + lsli %g5, 4 + not %g5 /* mask to clr cwp */ + pfx 1 /* istatus */ + rdctl %g0 + and %g0, %g5 /* clear cwp field */ + + mov %g4, %g1 /* g4 <- LO_LIMIT */ + lsli %g4, 4 + or %g0, %g4 /* cwp = LO_LIMIT */ + pfx 1 + wrctl %g0 /* update istatus */ + + /* Move to cwp = LO_LIMIT-1 and restore 'in' regs. + */ + subi %g4,(1 << 4) /* g4 <- LO_LIMIT - 1 */ + rdctl %g0 + and %g0, %g5 /* clear cwp field */ + or %g0, %g4 /* cwp = LO_LIMIT - 1 */ + wrctl %g0 /* update status */ + nop + + mov %sp, %g6 /* Restore sp */ + lds %i0, [%sp,8] /* Restore 'in' regs */ + lds %i1, [%sp,9] + lds %i2, [%sp,10] + lds %i3, [%sp,11] + lds %i4, [%sp,12] + lds %i5, [%sp,13] + lds %i6, [%sp,14] /* sp in next window */ + lds %i7, [%sp,15] + + /* Starting at LO_LIMIT-1, move up the register file, restoring + * along the way. + */ +0: + restore /* cwp++ */ + lds %l0, [%sp,0] /* Restore 'local' regs*/ + lds %l1, [%sp,1] + lds %l2, [%sp,2] + lds %l3, [%sp,3] + lds %l4, [%sp,4] + lds %l5, [%sp,5] + lds %l6, [%sp,6] + lds %l7, [%sp,7] + + lds %i0, [%sp,8] /* Restore 'in' regs */ + lds %i1, [%sp,9] + lds %i2, [%sp,10] + lds %i3, [%sp,11] + lds %i4, [%sp,12] + lds %i5, [%sp,13] + lds %i6, [%sp,14] /* sp in next window */ + lds %i7, [%sp,15] + + cmp %g1, %g2 /* cwp == HI_LIMIT ? */ + skps cc_ne /* if so, we're done */ + br 1f + nop /* delay slot */ + + inc %g1 /* cwp++ */ + br 0b + nop /* delay slot */ + + /* All windows have been updated at this point, but the globals + * still need to be restored. Go to cwp = LO_LIMIT-1 to get + * some registers to use. + */ +1: + rdctl %g0 + and %g0, %g5 /* clear cwp field */ + or %g0, %g4 /* cwp = LO_LIMIT - 1 */ + wrctl %g0 /* update status */ + nop + + /* Now there are some registers available to use in restoring + * the globals. + */ + mov %sp, %g6 + mov %o7, %g7 + + lds %g0, [%sp,0] /* Restore "global" regs*/ + lds %g1, [%sp,1] + lds %g2, [%sp,2] + lds %g3, [%sp,3] + lds %g4, [%sp,4] + lds %g5, [%sp,5] + lds %g6, [%sp,6] + lds %g7, [%sp,7] + + /* The tret moves istatus -> status. istatus was already set for + * cwp = LO_LIMIT. + */ + + tret %o7 /* done */ + +/************************************************************************* + * Default exception handler + * + * The default handler passes control to external_interrupt(). So trap + * or hardware interrupt hanlders can be installed using the familiar + * irq_install_handler(). + * + * Here, the stack is fixed-up and cwp is incremented prior to calling + * external_interrupt(). This lets the underflow and overflow handlers + * operate normally during the exception. + ************************************************************************/ + .text + .global _def_xhandler + .align 4 + +_def_xhandler: + + /* Allocate some stack space: 16 words at %sp to accomodate + * a reg window underflow, 8 words to save interrupted task's + * 'out' regs (which are now the 'in' regs), 8 words to preserve + * the 'global' regs and 3 words to save the return address, + * status and istatus. istatus must be saved in the event an + * underflow occurs in a dispatched handler. status is saved so + * a handler can access it on stack. + */ + pfx %hi((16+16+3) * 4) + subi %fp, %lo((16+16+3) * 4) + mov %sp, %fp + + /* Save the 'global' regs and the interrupted task's 'out' regs + * (our 'in' regs) along with the return addr, status & istatus. + * First 16 words are for underflow exception. + */ + rdctl %l0 /* status */ + pfx 1 /* istatus */ + rdctl %l1 + + sts [%sp,16+0], %g0 /* Save 'global' regs*/ + sts [%sp,16+1], %g1 + sts [%sp,16+2], %g2 + sts [%sp,16+3], %g3 + sts [%sp,16+4], %g4 + sts [%sp,16+5], %g5 + sts [%sp,16+6], %g6 + sts [%sp,16+7], %g7 + + sts [%sp,16+8], %i0 /* Save 'in' regs */ + sts [%sp,16+9], %i1 + sts [%sp,16+10], %i2 + sts [%sp,16+11], %i3 + sts [%sp,16+12], %i4 + sts [%sp,16+13], %i5 + sts [%sp,16+14], %i6 + sts [%sp,16+15], %i7 + + sts [%sp,16+16], %l0 /* status */ + sts [%sp,16+17], %l1 /* istatus */ + sts [%sp,16+18], %o7 /* return addr */ + + /* Move to cwp+1 ... this guarantees cwp is at or above LO_LIMIT. + * Need to set IPRI=3 and IE=1 to enable underflow exceptions. + * NOTE: only the 'out' regs have been saved ... can't touch + * the 'in' or 'local' here. + */ + restore /* cwp++ */ + rdctl %o0 /* o0 <- status */ + + pfx %hi(0x7e00) + movi %o1, %lo(0x7e00) + not %o1 + and %o0, %o1 /* clear IPRI */ + + pfx %hi(0x8600) + movi %o1, %lo(0x8600) + or %o0, %o1 /* IPRI=3, IE=1 */ + + wrctl %o0 /* o0 -> status */ + nop + + /* It's ok to call a C routine now since cwp >= LO_LIMIT, + * interrupt task's registers are/will be preserved, and + * underflow exceptions can be handled. + */ + pfx %hi(external_interrupt@h) + movi %o1, %lo(external_interrupt@h) + pfx %xhi(external_interrupt@h) + movhi %o1, %xlo(external_interrupt@h) + bgen %o0, 4+2 /* 16 * 4 */ + add %o0, %sp /* Ptr to regs */ + call %o1 + nop + + /* Move back to the exception register window, restore the 'out' + * registers, then return from exception. + */ + rdctl %o0 /* o0 <- status */ + subi %o0, 16 + wrctl %o0 /* cwp-- */ + nop + + mov %sp, %fp + lds %g0, [%sp,16+0] /* Restore 'global' regs*/ + lds %g1, [%sp,16+1] + lds %g2, [%sp,16+2] + lds %g3, [%sp,16+3] + lds %g4, [%sp,16+4] + lds %g5, [%sp,16+5] + lds %g6, [%sp,16+6] + lds %g7, [%sp,16+7] + + lds %i0, [%sp,16+8] /* Restore 'in' regs*/ + lds %i1, [%sp,16+9] + lds %i2, [%sp,16+10] + lds %i3, [%sp,16+11] + lds %i4, [%sp,16+12] + lds %i5, [%sp,16+13] + lds %i6, [%sp,16+14] + lds %i7, [%sp,16+15] + + lds %l0, [%sp,16+16] /* status */ + lds %l1, [%sp,16+17] /* istatus */ + lds %o7, [%sp,16+18] /* return addr */ + + pfx 1 + wrctl %l1 /* restore istatus */ + + pfx %hi((16+16+3) * 4) + addi %sp, %lo((16+16+3) * 4) + mov %fp, %sp + + tret %o7 /* Done */ + + +/************************************************************************* + * Timebase Timer Interrupt -- This has identical structure to above, + * but calls timer_interrupt(). Doing it this way keeps things similar + * to other architectures (e.g. ppc). + ************************************************************************/ + .text + .global _timebase_int + .align 4 + +_timebase_int: + + /* Allocate stack space. + */ + pfx %hi((16+16+3) * 4) + subi %fp, %lo((16+16+3) * 4) + mov %sp, %fp + + /* Save the 'global' regs & 'out' regs (our 'in' regs) + */ + rdctl %l0 /* status */ + pfx 1 /* istatus */ + rdctl %l1 + + sts [%sp,16+0], %g0 /* Save 'global' regs*/ + sts [%sp,16+1], %g1 + sts [%sp,16+2], %g2 + sts [%sp,16+3], %g3 + sts [%sp,16+4], %g4 + sts [%sp,16+5], %g5 + sts [%sp,16+6], %g6 + sts [%sp,16+7], %g7 + + sts [%sp,16+8], %i0 /* Save 'in' regs */ + sts [%sp,16+9], %i1 + sts [%sp,16+10], %i2 + sts [%sp,16+11], %i3 + sts [%sp,16+12], %i4 + sts [%sp,16+13], %i5 + sts [%sp,16+14], %i6 + sts [%sp,16+15], %i7 + + sts [%sp,16+16], %l0 /* status */ + sts [%sp,16+17], %l1 /* istatus */ + sts [%sp,16+18], %o7 /* return addr */ + + /* Move to cwp+1. + */ + restore /* cwp++ */ + rdctl %o0 /* o0 <- status */ + + pfx %hi(0x7e00) + movi %o1, %lo(0x7e00) + not %o1 + and %o0, %o1 /* clear IPRI */ + + pfx %hi(0x8600) + movi %o1, %lo(0x8600) + or %o0, %o1 /* IPRI=3, IE=1 */ + + wrctl %o0 /* o0 -> status */ + nop + + /* Call timer_interrupt() + */ + pfx %hi(timer_interrupt@h) + movi %o1, %lo(timer_interrupt@h) + pfx %xhi(timer_interrupt@h) + movhi %o1, %xlo(timer_interrupt@h) + bgen %o0, 4+2 /* 16 * 4 */ + add %o0, %sp /* Ptr to regs */ + call %o1 + nop + + /* Move back to the exception register window, restore the 'out' + * registers, then return from exception. + */ + rdctl %o0 /* o0 <- status */ + subi %o0, 16 + wrctl %o0 /* cwp-- */ + nop + + mov %sp, %fp + lds %g0, [%sp,16+0] /* Restore 'global' regs*/ + lds %g1, [%sp,16+1] + lds %g2, [%sp,16+2] + lds %g3, [%sp,16+3] + lds %g4, [%sp,16+4] + lds %g5, [%sp,16+5] + lds %g6, [%sp,16+6] + lds %g7, [%sp,16+7] + + lds %i0, [%sp,16+8] /* Restore 'in' regs*/ + lds %i1, [%sp,16+9] + lds %i2, [%sp,16+10] + lds %i3, [%sp,16+11] + lds %i4, [%sp,16+12] + lds %i5, [%sp,16+13] + lds %i6, [%sp,16+14] + lds %i7, [%sp,16+15] + + lds %l0, [%sp,16+16] /* status */ + lds %l1, [%sp,16+17] /* istatus */ + lds %o7, [%sp,16+18] /* return addr */ + + pfx 1 + wrctl %l1 /* restore istatus */ + + pfx %hi((16+16+3) * 4) + addi %sp, %lo((16+16+3) * 4) + mov %fp, %sp + + tret %o7 /* Done */ + +/************************************************************************* + * GDB stubs + ************************************************************************/ + .text + .global _brkpt_hw_int, _brkpt_sw_int + .align 4 + +_brkpt_hw_int: + movi %l1, 9 + pfx 3 + wrctl %l1 + pfx 4 + wrctl %l1 + +_brkpt_sw_int: + movi %l1, 9 + pfx 3 + wrctl %l1 + pfx 4 + wrctl %l1 + + tret %o7 diff --git a/cpu/nios2/Makefile b/cpu/nios2/Makefile new file mode 100644 index 0000000..11fda50 --- /dev/null +++ b/cpu/nios2/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +AOBJS = exceptions.o +OBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) $(AOBJS) + $(AR) crv $@ $(OBJS) $(AOBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/nios2/config.mk b/cpu/nios2/config.mk new file mode 100644 index 0000000..f228d72 --- /dev/null +++ b/cpu/nios2/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += diff --git a/cpu/nios2/cpu.c b/cpu/nios2/cpu.c new file mode 100644 index 0000000..f4217a8 --- /dev/null +++ b/cpu/nios2/cpu.c @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined (CFG_NIOS_SYSID_BASE) +extern void display_sysid (void); +#endif /* CFG_NIOS_SYSID_BASE */ + +int checkcpu (void) +{ + printf ("CPU : Nios-II\n"); +#if !defined(CFG_NIOS_SYSID_BASE) + printf ("SYSID : \n"); +#else + display_sysid (); +#endif + return (0); +} + + +int do_reset (void) +{ + void (*rst)(void) = (void(*)(void))CFG_RESET_ADDR; + disable_interrupts (); + rst(); + return(0); +} diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c new file mode 100644 index 0000000..a8851e9 --- /dev/null +++ b/cpu/nios2/epcs.c @@ -0,0 +1,711 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CFG_NIOS_EPCSBASE) +#include +#include +#include +#include + + +/*-----------------------------------------------------------------------*/ +#define SHORT_HELP\ + "epcs - read/write Cyclone EPCS configuration device.\n" + +#define LONG_HELP\ + "\n"\ + "epcs erase start [end]\n"\ + " - erase sector start or sectors start through end.\n"\ + "epcs info\n"\ + " - display EPCS device information.\n"\ + "epcs protect on | off\n"\ + " - turn device protection on or off.\n"\ + "epcs read addr offset count\n"\ + " - read count bytes from offset to addr.\n"\ + "epcs write addr offset count\n"\ + " - write count bytes to offset from addr.\n"\ + "epcs verify addr offset count\n"\ + " - verify count bytes at offset from addr.\n" + + +/*-----------------------------------------------------------------------*/ +/* Operation codes for serial configuration devices + */ +#define EPCS_WRITE_ENA 0x06 /* Write enable */ +#define EPCS_WRITE_DIS 0x04 /* Write disable */ +#define EPCS_READ_STAT 0x05 /* Read status */ +#define EPCS_READ_BYTES 0x03 /* Read bytes */ +#define EPCS_READ_ID 0xab /* Read silicon id */ +#define EPCS_WRITE_STAT 0x01 /* Write status */ +#define EPCS_WRITE_BYTES 0x02 /* Write bytes */ +#define EPCS_ERASE_BULK 0xc7 /* Erase entire device */ +#define EPCS_ERASE_SECT 0xd8 /* Erase sector */ + +/* Device status register bits + */ +#define EPCS_STATUS_WIP (1<<0) /* Write in progress */ +#define EPCS_STATUS_WEL (1<<1) /* Write enable latch */ + +/* Misc + */ +#define EPCS_TIMEOUT 100 /* 100 msec timeout */ + +static nios_spi_t *epcs = + (nios_spi_t *)CACHE_BYPASS(CFG_NIOS_EPCSBASE); + +/*********************************************************************** + * Device access + ***********************************************************************/ +static int epcs_cs (int assert) +{ + ulong start; + + if (assert) { + epcs->control |= NIOS_SPI_SSO; + } else { + /* Let all bits shift out */ + start = get_timer (0); + while ((epcs->status & NIOS_SPI_TMT) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + epcs->control &= ~NIOS_SPI_SSO; + } + return (0); +} + +static int epcs_tx (unsigned char c) +{ + ulong start; + + start = get_timer (0); + while ((epcs->status & NIOS_SPI_TRDY) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + epcs->txdata = c; + return (0); +} + +static int epcs_rx (void) +{ + ulong start; + + start = get_timer (0); + while ((epcs->status & NIOS_SPI_RRDY) == 0) + if (get_timer (start) > EPCS_TIMEOUT) + return (-1); + return (epcs->rxdata); +} + +static unsigned char bitrev[] = { + 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, + 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f +}; + +static unsigned char epcs_bitrev (unsigned char c) +{ + unsigned char val; + + val = bitrev[c>>4]; + val |= bitrev[c & 0x0f]<<4; + return (val); +} + +static void epcs_rcv (unsigned char *dst, int len) +{ + while (len--) { + epcs_tx (0); + *dst++ = epcs_rx (); + } +} + +static void epcs_rrcv (unsigned char *dst, int len) +{ + while (len--) { + epcs_tx (0); + *dst++ = epcs_bitrev (epcs_rx ()); + } +} + +static void epcs_snd (unsigned char *src, int len) +{ + while (len--) { + epcs_tx (*src++); + epcs_rx (); + } +} + +static void epcs_rsnd (unsigned char *src, int len) +{ + while (len--) { + epcs_tx (epcs_bitrev (*src++)); + epcs_rx (); + } +} + +static void epcs_wr_enable (void) +{ + epcs_cs (1); + epcs_tx (EPCS_WRITE_ENA); + epcs_rx (); + epcs_cs (0); +} + +static unsigned char epcs_status_rd (void) +{ + unsigned char status; + + epcs_cs (1); + epcs_tx (EPCS_READ_STAT); + epcs_rx (); + epcs_tx (0); + status = epcs_rx (); + epcs_cs (0); + return (status); +} + +static void epcs_status_wr (unsigned char status) +{ + epcs_wr_enable (); + epcs_cs (1); + epcs_tx (EPCS_WRITE_STAT); + epcs_rx (); + epcs_tx (status); + epcs_rx (); + epcs_cs (0); + return; +} + +/*********************************************************************** + * Device information + ***********************************************************************/ + +static struct epcs_devinfo_t devinfo[] = { + { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, + { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, + { 0, 0, 0, 0, 0, 0 } +}; + +epcs_devinfo_t *epcs_dev_find (void) +{ + unsigned char buf[4]; + unsigned char id; + int i; + struct epcs_devinfo_t *dev = NULL; + + /* Read silicon id requires 3 "dummy bytes" before it's put + * on the wire. + */ + buf[0] = EPCS_READ_ID; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rcv (buf,1); + if (epcs_cs (0) == -1) + return (NULL); + id = buf[0]; + + /* Find the info struct */ + i = 0; + while (devinfo[i].name) { + if (id == devinfo[i].id) { + dev = &devinfo[i]; + break; + } + i++; + } + + return (dev); +} + +/*********************************************************************** + * Misc Utilities + ***********************************************************************/ +int epcs_cfgsz (void) +{ + int sz = 0; + unsigned char buf[128]; + unsigned char *p; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + /* Read in the first 128 bytes of the device */ + buf[0] = EPCS_READ_BYTES; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rrcv (buf, sizeof(buf)); + epcs_cs (0); + + /* Search for the starting 0x6a which is followed by the + * 4-byte 'register' and 4-byte bit-count. + */ + p = buf; + while (p < buf + sizeof(buf)-8) { + if ( *p == 0x6a ) { + /* Point to bit count and extract */ + p += 5; + sz = *p++; + sz |= *p++ << 8; + sz |= *p++ << 16; + sz |= *p++ << 24; + /* Convert to byte count */ + sz += 7; + sz >>= 3; + } else if (*p == 0xff) { + /* 0xff is ok ... just skip */ + p++; + continue; + } else { + /* Not 0xff or 0x6a ... something's not + * right ... report 'unknown' (sz=0). + */ + break; + } + } + return (sz); +} + +int epcs_erase (unsigned start, unsigned end) +{ + unsigned off, sectsz; + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev || (start>end)) + return (-1); + + /* Erase the requested sectors. An address is required + * that lies within the requested sector -- we'll just + * use the first address in the sector. + */ + printf ("epcs erasing sector %d ", start); + if (start != end) + printf ("to %d ", end); + sectsz = (1 << dev->sz_sect); + while (start <= end) { + off = start * sectsz; + start++; + + buf[0] = EPCS_ERASE_SECT; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_wr_enable (); + epcs_cs (1); + epcs_snd (buf,4); + epcs_cs (0); + + printf ("."); /* Some user feedback */ + + /* Wait for erase to complete */ + while (epcs_status_rd() & EPCS_STATUS_WIP) + ; + } + printf (" done.\n"); + return (0); +} + +int epcs_read (ulong addr, ulong off, ulong cnt) +{ + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + buf[0] = EPCS_READ_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_cs (1); + epcs_snd (buf,4); + epcs_rrcv ((unsigned char *)addr, cnt); + epcs_cs (0); + + return (0); +} + +int epcs_write (ulong addr, ulong off, ulong cnt) +{ + ulong wrcnt; + unsigned pgsz; + unsigned char buf[4]; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) + return (-1); + + pgsz = (1<sz_page); + while (cnt) { + if (off % pgsz) + wrcnt = pgsz - (off % pgsz); + else + wrcnt = pgsz; + wrcnt = (wrcnt > cnt) ? cnt : wrcnt; + + buf[0] = EPCS_WRITE_BYTES; + buf[1] = off >> 16; + buf[2] = off >> 8; + buf[3] = off; + + epcs_wr_enable (); + epcs_cs (1); + epcs_snd (buf,4); + epcs_rsnd ((unsigned char *)addr, wrcnt); + epcs_cs (0); + + /* Wait for write to complete */ + while (epcs_status_rd() & EPCS_STATUS_WIP) + ; + + cnt -= wrcnt; + off += wrcnt; + addr += wrcnt; + } + + return (0); +} + +int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err) +{ + ulong rdcnt; + unsigned char buf[256]; + unsigned char *start,*end; + int i; + + start = end = (unsigned char *)addr; + while (cnt) { + rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; + epcs_read ((ulong)buf, off, rdcnt); + for (i=0; isz_sect); + off = sectsz * sect; + end = off + sectsz; + + while (off < end) { + epcs_read ((ulong)buf, off, sizeof(buf)); + for (i=0; i < sizeof(buf); i++) { + if (buf[i] != 0xff) { + *offset = off + i; + return (0); + } + } + off += sizeof(buf); + } + return (1); +} + + +/*********************************************************************** + * Commands + ***********************************************************************/ +static +void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + int i; + unsigned char stat; + unsigned tmp; + int erased; + + /* Basic device info */ + printf ("%s: %d kbytes (%d sectors x %d kbytes," + " %d bytes/page)\n", + dev->name, 1 << (dev->size-10), + dev->num_sects, 1 << (dev->sz_sect-10), + 1 << dev->sz_page ); + + /* Status -- for now protection is all-or-nothing */ + stat = epcs_status_rd(); + printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", + stat, + (stat & EPCS_STATUS_WIP) ? 1 : 0, + (stat & EPCS_STATUS_WEL) ? 1 : 0, + (stat & dev->prot_mask) ? "on" : "off" ); + + /* Configuration */ + tmp = epcs_cfgsz (); + if (tmp) { + printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); + } else { + printf ("config: unknown\n" ); + } + + /* Sector info */ + for (i=0; inum_sects; i++) { + erased = epcs_sect_erased (i, &tmp, dev); + printf (" %d: %06x ", + i, i*(1<sz_sect) ); + if (erased) + printf ("erased\n"); + else + printf ("data @ 0x%06x\n", tmp); + } + + return; +} + +static +void do_epcs_erase (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned start,end; + + if ((argc < 3) || (argc > 4)) { + printf ("USAGE: epcs erase sect [end]\n"); + return; + } + if ((epcs_status_rd() & dev->prot_mask) != 0) { + printf ( "epcs: device protected.\n"); + return; + } + + start = simple_strtoul (argv[2], NULL, 10); + if (argc > 3) + end = simple_strtoul (argv[3], NULL, 10); + else + end = start; + if ((start >= dev->num_sects) || (start > end)) { + printf ("epcs: invalid sector range: [%d:%d]\n", + start, end ); + return; + } + + epcs_erase (start, end); + + return; +} + +static +void do_epcs_protect (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + unsigned char stat; + + /* For now protection is all-or-nothing to keep things + * simple. The protection bits don't map in a linear + * fashion ... and we would rather protect the bottom + * of the device since it contains the config data and + * leave the top unprotected for app use. But unfortunately + * protection works from top-to-bottom so it does + * really help very much from a software app point-of-view. + */ + if (argc < 3) { + printf ("USAGE: epcs protect on | off\n"); + return; + } + if (!dev) + return; + + /* Protection on/off is just a matter of setting/clearing + * all protection bits in the status register. + */ + stat = epcs_status_rd (); + if (strcmp ("on", argv[2]) == 0) { + stat |= dev->prot_mask; + } else if (strcmp ("off", argv[2]) == 0 ) { + stat &= ~dev->prot_mask; + } else { + printf ("epcs: unknown protection: %s\n", argv[2]); + return; + } + epcs_status_wr (stat); + return; +} + +static +void do_epcs_read (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + + if (argc < 5) { + printf ("USAGE: epcs read addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: read %08lx <- %06lx (0x%lx bytes)\n", + addr, off, cnt); + epcs_read (addr, off, cnt); + + return; +} + +static +void do_epcs_write (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: epcs write addr offset count\n"); + return; + } + if ((epcs_status_rd() & dev->prot_mask) != 0) { + printf ( "epcs: device protected.\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: write %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + epcs_write (addr, off, cnt); + if (epcs_verify (addr, off, cnt, &err) != 0) + printf ("epcs: write error at offset %06lx\n", err); + + return; +} + +static +void do_epcs_verify (struct epcs_devinfo_t *dev, int argc, char *argv[]) +{ + ulong addr,off,cnt; + ulong sz; + ulong err; + + if (argc < 5) { + printf ("USAGE: epcs verify addr offset count\n"); + return; + } + + sz = 1 << dev->size; + addr = simple_strtoul (argv[2], NULL, 16); + off = simple_strtoul (argv[3], NULL, 16); + cnt = simple_strtoul (argv[4], NULL, 16); + if (off > sz) { + printf ("offset is greater than device size" + "... aborting.\n"); + return; + } + if ((off + cnt) > sz) { + printf ("request exceeds device size" + "... truncating.\n"); + cnt = sz - off; + } + printf ("epcs: verify %08lx -> %06lx (0x%lx bytes)\n", + addr, off, cnt); + if (epcs_verify (addr, off, cnt, &err) != 0) + printf ("epcs: verify error at offset %06lx\n", err); + + return; +} + +/*-----------------------------------------------------------------------*/ +int do_epcs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int len; + struct epcs_devinfo_t *dev = epcs_dev_find (); + + if (!dev) { + printf ("epcs: device not found.\n"); + return (-1); + } + + if (argc < 2) { + do_epcs_info (dev, argc, argv); + return (0); + } + + len = strlen (argv[1]); + if (strncmp ("info", argv[1], len) == 0) { + do_epcs_info (dev, argc, argv); + } else if (strncmp ("erase", argv[1], len) == 0) { + do_epcs_erase (dev, argc, argv); + } else if (strncmp ("protect", argv[1], len) == 0) { + do_epcs_protect (dev, argc, argv); + } else if (strncmp ("read", argv[1], len) == 0) { + do_epcs_read (dev, argc, argv); + } else if (strncmp ("write", argv[1], len) == 0) { + do_epcs_write (dev, argc, argv); + } else if (strncmp ("verify", argv[1], len) == 0) { + do_epcs_verify (dev, argc, argv); + } else { + printf ("epcs: unknown operation: %s\n", argv[1]); + } + + return (0); +} + +/*-----------------------------------------------------------------------*/ + + +U_BOOT_CMD( epcs, 5, 0, do_epcs, SHORT_HELP, LONG_HELP ); + +#endif /* CONFIG_NIOS_EPCS */ diff --git a/cpu/nios2/exceptions.S b/cpu/nios2/exceptions.S new file mode 100644 index 0000000..d3b95cf --- /dev/null +++ b/cpu/nios2/exceptions.S @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + + .text + .align 4 + + .global _exception + +_exception: + /* SAVE ALL REGS -- this allows trap and unimplemented + * instruction handlers to be coded conveniently in C + */ + addi sp, sp, -(33*4) + stw r0, 0(sp) + stw r1, 4(sp) + stw r2, 8(sp) + stw r3, 12(sp) + stw r4, 16(sp) + stw r5, 20(sp) + stw r6, 24(sp) + stw r7, 28(sp) + stw r8, 32(sp) + stw r9, 36(sp) + stw r10, 40(sp) + stw r11, 44(sp) + stw r12, 48(sp) + stw r13, 52(sp) + stw r14, 56(sp) + stw r15, 60(sp) + stw r16, 64(sp) + stw r17, 68(sp) + stw r19, 72(sp) + stw r19, 76(sp) + stw r20, 80(sp) + stw r21, 84(sp) + stw r22, 88(sp) + stw r23, 92(sp) + stw r24, 96(sp) + stw r25, 100(sp) + stw r26, 104(sp) + stw r27, 108(sp) + stw r28, 112(sp) + stw r29, 116(sp) + stw r30, 120(sp) + stw r31, 124(sp) + rdctl et, estatus + stw et, 128(sp) + + /* If interrupts are disabled -- software interrupt */ + rdctl et, estatus + andi et, et, 1 + beq et, r0, 0f + + /* If no interrupts are pending -- software interrupt */ + rdctl et, ipending + beq et, r0, 0f + + /* HARDWARE INTERRUPT: Call interrupt handler */ + movhi r3, %hi(external_interrupt) + ori r3, r3, %lo(external_interrupt) + mov r4, sp /* ptr to regs */ + callr r3 + + /* Return address fixup: execution resumes by re-issue of + * interrupted instruction at ea-4 (ea == r29). Here we do + * simple fixup to allow common exception return. + */ + ldw r3, 116(sp) + addi r3, r3, -4 + stw r3, 116(sp) + br _exception_return + +0: + /* TRAP EXCEPTION */ + movhi r3, %hi(OPC_TRAP) + ori r3, r3, %lo(OPC_TRAP) + addi r1, ea, -4 + ldw r1, 0(r1) + bne r1, r3, 1f + movhi r3, %hi(trap_handler) + ori r3, r3, %lo(trap_handler) + mov r4, sp /* ptr to regs */ + callr r3 + br _exception_return + +1: + /* UNIMPLEMENTED INSTRUCTION EXCEPTION */ + movhi r3, %hi(soft_emulation) + ori r3, r3, %lo(soft_emulation) + mov r4, sp /* ptr to regs */ + callr r3 + + /* Restore regsisters and return from exception*/ +_exception_return: + ldw r1, 4(sp) + ldw r2, 8(sp) + ldw r3, 12(sp) + ldw r4, 16(sp) + ldw r5, 20(sp) + ldw r6, 24(sp) + ldw r7, 28(sp) + ldw r8, 32(sp) + ldw r9, 36(sp) + ldw r10, 40(sp) + ldw r11, 44(sp) + ldw r12, 48(sp) + ldw r13, 52(sp) + ldw r14, 56(sp) + ldw r15, 60(sp) + ldw r16, 64(sp) + ldw r17, 68(sp) + ldw r19, 72(sp) + ldw r19, 76(sp) + ldw r20, 80(sp) + ldw r21, 84(sp) + ldw r22, 88(sp) + ldw r23, 92(sp) + ldw r24, 96(sp) + ldw r25, 100(sp) + ldw r26, 104(sp) + ldw r27, 108(sp) + ldw r28, 112(sp) + ldw r29, 116(sp) + ldw r30, 120(sp) + ldw r31, 124(sp) + addi sp, sp, (33*4) + eret +/*-------------------------------------------------------------*/ diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c new file mode 100644 index 0000000..4a6da58 --- /dev/null +++ b/cpu/nios2/interrupts.c @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_STATUS_LED +#include +#endif + +#if defined(CFG_NIOS_TMRBASE) && !defined(CFG_NIOS_TMRIRQ) +#error CFG_NIOS_TMRIRQ not defined (see documentation) +#endif + +/****************************************************************************/ + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + int count; +}; + +static struct irq_action vecs[32]; + +/*************************************************************************/ +volatile ulong timestamp = 0; + +void reset_timer (void) +{ + timestamp = 0; +} + +ulong get_timer (ulong base) +{ + WATCHDOG_RESET (); + return (timestamp - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} + + +/* The board must handle this interrupt if a timer is not + * provided. + */ +#if defined(CFG_NIOS_TMRBASE) +void tmr_isr (void *arg) +{ + nios_timer_t *tmr = (nios_timer_t *)arg; + /* Interrupt is cleared by writing anything to the + * status register. + */ + tmr->status = 0; + timestamp += CFG_NIOS_TMRMS; +#ifdef CONFIG_STATUS_LED + status_led_tick(timestamp); +#endif +} + +static void tmr_init (void) +{ + nios_timer_t *tmr =(nios_timer_t *)CACHE_BYPASS(CFG_NIOS_TMRBASE); + + tmr->control &= ~(NIOS_TIMER_START | NIOS_TIMER_ITO); + tmr->control |= NIOS_TIMER_STOP; +#if defined(CFG_NIOS_TMRCNT) + tmr->periodl = CFG_NIOS_TMRCNT & 0xffff; + tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff; +#endif + tmr->control |= ( NIOS_TIMER_ITO | + NIOS_TIMER_CONT | + NIOS_TIMER_START ); + irq_install_handler (CFG_NIOS_TMRIRQ, tmr_isr, (void *)tmr); +} + +#endif /* CFG_NIOS_TMRBASE */ + +/*************************************************************************/ +int disable_interrupts (void) +{ + int val = rdctl (CTL_STATUS); + wrctl (CTL_STATUS, val & ~STATUS_IE); + return (val & STATUS_IE); +} + +void enable_interrupts( void ) +{ + int val = rdctl (CTL_STATUS); + wrctl (CTL_STATUS, val | STATUS_IE); +} + +void external_interrupt (struct pt_regs *regs) +{ + unsigned irqs; + struct irq_action *act; + + /* Evaluate only irqs that are both enabled AND pending */ + irqs = rdctl (CTL_IENABLE) & rdctl (CTL_IPENDING); + act = vecs; + + /* Assume (as does the Nios2 HAL) that bit 0 is highest + * priority. NOTE: There is ALWAYS a handler assigned + * (the default if no other). + */ + while (irqs) { + if (irqs & 1) { + act->handler (act->arg); + act->count++; + } + irqs >>=1; + act++; + } +} + +static void def_hdlr (void *arg) +{ + unsigned irqs = rdctl (CTL_IENABLE); + + /* Disable the individual interrupt -- with gratuitous + * warning. + */ + irqs &= ~(1 << (int)arg); + wrctl (CTL_IENABLE, irqs); + printf ("WARNING: Disabling unhandled interrupt: %d\n", + (int)arg); +} + +/*************************************************************************/ +void irq_install_handler (int irq, interrupt_handler_t *hdlr, void *arg) +{ + + int flag; + struct irq_action *act; + unsigned ena = rdctl (CTL_IENABLE); + + if ((irq < 0) || (irq > 31)) + return; + act = &vecs[irq]; + + flag = disable_interrupts (); + if (hdlr) { + act->handler = hdlr; + act->arg = arg; + ena |= (1 << irq); /* enable */ + } else { + act->handler = def_hdlr; + act->arg = (void *)irq; + ena &= ~(1 << irq); /* disable */ + } + wrctl (CTL_IENABLE, ena); + if (flag) enable_interrupts (); +} + + +int interrupt_init (void) +{ + int i; + + /* Assign the default handler to all */ + for (i = 0; i < 32; i++) { + vecs[i].handler = def_hdlr; + vecs[i].arg = (void *)i; + vecs[i].count = 0; + } + +#if defined(CFG_NIOS_TMRBASE) + tmr_init (); +#endif + + enable_interrupts (); + return (0); +} + + +/*************************************************************************/ +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + struct irq_action *act = vecs; + + printf ("\nInterrupt-Information:\n\n"); + printf ("Nr Routine Arg Count\n"); + printf ("-----------------------------\n"); + + for (i=0; i<32; i++) { + if (act->handler != def_hdlr) { + printf ("%02d %08lx %08lx %d\n", + i, + (ulong)act->handler, + (ulong)act->arg, + act->count); + } + act++; + } + printf ("\n"); + + return (0); +} +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c new file mode 100644 index 0000000..2d08c93 --- /dev/null +++ b/cpu/nios2/serial.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include + +/*------------------------------------------------------------------ + * JTAG acts as the serial port + *-----------------------------------------------------------------*/ +#if defined(CONFIG_CONSOLE_JTAG) + +static nios_jtag_t *jtag = + (nios_jtag_t *)CACHE_BYPASS(CFG_NIOS_CONSOLE); + +void serial_setbrg( void ){ return; } +int serial_init( void ) { return(0);} + +void serial_putc (char c) +{ + unsigned val; + + while (NIOS_JTAG_WSPACE (jtag->control) == 0) + WATCHDOG_RESET (); + jtag->data = (unsigned char)c; +} + +void serial_puts (const char *s) +{ + while (*s != 0) + serial_putc (*s++); +} + +int serial_tstc (void) +{ + return (jtag->control & NIOS_JTAG_RRDY); +} + +int serial_getc (void) +{ + int c; + unsigned val; + + while (1) { + WATCHDOG_RESET (); + val = jtag->data; + if (val & NIOS_JTAG_RVALID) + break; + } + c = val & 0x0ff; + return (c); +} + +/*------------------------------------------------------------------ + * UART the serial port + *-----------------------------------------------------------------*/ +#else + +static nios_uart_t *uart = (nios_uart_t *) + CACHE_BYPASS(CFG_NIOS_CONSOLE); + +#if defined(CFG_NIOS_FIXEDBAUD) + +/* Everything's already setup for fixed-baud PTF + * assignment + */ +void serial_setbrg (void){ return; } +int serial_init (void) { return (0);} + +#else + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned div; + + div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; + uart->divisor = div; + return; +} + +int serial_init (void) +{ + serial_setbrg (); + return (0); +} + +#endif /* CFG_NIOS_FIXEDBAUD */ + + +/*----------------------------------------------------------------------- + * UART CONSOLE + *---------------------------------------------------------------------*/ +void serial_putc (char c) +{ + if (c == '\n') + serial_putc ('\r'); + while ((uart->status & NIOS_UART_TRDY) == 0) + WATCHDOG_RESET (); + uart->txdata = (unsigned char)c; +} + +void serial_puts (const char *s) +{ + while (*s != 0) { + serial_putc (*s++); + } +} + +int serial_tstc (void) +{ + return (uart->status & NIOS_UART_RRDY); +} + +int serial_getc (void) +{ + while (serial_tstc () == 0) + WATCHDOG_RESET (); + return( uart->rxdata & 0x00ff ); +} + +#endif /* CONFIG_JTAG_CONSOLE */ diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S new file mode 100644 index 0000000..4c6e470 --- /dev/null +++ b/cpu/nios2/start.S @@ -0,0 +1,216 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +/************************************************************************* + * RESTART + ************************************************************************/ + + .text + .global _start + +_start: + /* ICACHE INIT -- only the icache line at the reset address + * is invalidated at reset. So the init must stay within + * the cache line size (8 words). If GERMS is used, we'll + * just be invalidating the cache a second time. If cache + * is not implemented initi behaves as nop. + */ + ori r4, r0, %lo(CFG_ICACHELINE_SIZE) + movhi r5, %hi(CFG_ICACHE_SIZE) + ori r5, r5, %lo(CFG_ICACHE_SIZE) + mov r6, r0 +0: initi r6 + add r6, r6, r4 + bltu r6, r5, 0b + br _except_end /* Skip the tramp */ + + /* EXCEPTION TRAMPOLINE -- the following gets copied + * to the exception address (below), but is otherwise at the + * default exception vector offset (0x0020). + */ +_except_start: + movhi et, %hi(_exception) + ori et, et, %lo(_exception) + jmp et +_except_end: + + /* INTERRUPTS -- for now, all interrupts masked and globally + * disabled. + */ + wrctl status, r0 /* Disable interrupts */ + wrctl ienable, r0 /* All disabled */ + + /* DCACHE INIT -- if dcache not implemented, initd behaves as + * nop. + */ + movhi r4, %hi(CFG_DCACHELINE_SIZE) + ori r4, r4, %lo(CFG_DCACHELINE_SIZE) + movhi r5, %hi(CFG_DCACHE_SIZE) + ori r5, r5, %lo(CFG_DCACHE_SIZE) + mov r6, r0 +1: initd 0(r6) + add r6, r6, r4 + bltu r6, r5, 1b + + /* RELOCATE CODE, DATA & COMMAND TABLE -- the following code + * assumes code, data and the command table are all + * contiguous. This lets us relocate everything as a single + * block. Make sure the linker script matches this ;-) + */ + nextpc r4 +_cur: movhi r5, %hi(_cur - _start) + ori r5, r5, %lo(_cur - _start) + sub r4, r4, r5 /* r4 <- cur _start */ + mov r8, r4 + movhi r5, %hi(_start) + ori r5, r5, %lo(_start) /* r5 <- linked _start */ + beq r4, r5, 3f + + movhi r6, %hi(_edata) + ori r6, r6, %lo(_edata) +2: ldwio r7, 0(r4) + addi r4, r4, 4 + stwio r7, 0(r5) + addi r5, r5, 4 + bne r5, r6, 2b +3: + + /* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent + * and between __bss_start and _end. + */ + movhi r5, %hi(__bss_start) + ori r5, r5, %lo(__bss_start) + movhi r6, %hi(_end) + ori r6, r6, %lo(_end) + beq r5, r6, 5f + +4: stwio r0, 0(r5) + addi r5, r5, 4 + bne r5, r6, 4b +5: + + /* GLOBAL POINTER -- the global pointer is used to reference + * "small data" (see -G switch). The linker script must + * provide the gp address. + */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + + /* JUMP TO RELOC ADDR */ + movhi r4, %hi(_reloc) + ori r4, r4, %lo(_reloc) + jmp r4 +_reloc: + + /* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the + * exception address. Define CONFIG_ROM_STUBS to prevent + * the copy (e.g. exception in flash or in other + * softare/firmware component). + */ +#if !defined(CONFIG_ROM_STUBS) + movhi r4, %hi(_except_start) + ori r4, r4, %lo(_except_start) + movhi r5, %hi(_except_end) + ori r5, r5, %lo(_except_end) + movhi r6, %hi(CFG_EXCEPTION_ADDR) + ori r6, r6, %lo(CFG_EXCEPTION_ADDR) + beq r4, r6, 7f /* Skip if at proper addr */ + +6: ldwio r7, 0(r4) + stwio r7, 0(r6) + addi r4, r4, 4 + addi r6, r6, 4 + bne r4, r5, 6b +7: +#endif + + /* STACK INIT -- zero top two words for call back chain. + */ + movhi sp, %hi(CFG_INIT_SP) + ori sp, sp, %lo(CFG_INIT_SP) + addi sp, sp, -8 + stw r0, 0(sp) + stw r0, 4(sp) + mov fp, sp + + /* + * Call board_init -- never returns + */ + movhi r4, %hi(board_init@h) + ori r4, r4, %lo(board_init@h) + callr r4 + + /* NEVER RETURNS -- but branch to the _start just + * in case ;-) + */ + br _start + + +/* + * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in + * the core. For simple delay loops, we do our best by counting + * instruction cycles. + * + * Instruction performance varies based on the core. For cores + * with icache and static/dynamic branch prediction (II/f, II/s): + * + * Normal ALU (e.g. add, cmp, etc): 1 cycle + * Branch (correctly predicted, taken): 2 cycles + * Negative offset is predicted (II/s). + * + * For cores without icache and no branch prediction (II/e): + * + * Normal ALU (e.g. add, cmp, etc): 6 cycles + * Branch (no prediction): 6 cycles + * + * For simplicity, if an instruction cache is implemented we + * assume II/f or II/s. Otherwise, we use the II/e. + * + */ + .globl dly_clks + +dly_clks: + +#if (CFG_ICACHE_SIZE > 0) + subi r4, r4, 3 /* 3 clocks/loop */ +#else + subi r4, r4, 12 /* 12 clocks/loop */ +#endif + bge r4, r0, dly_clks + ret + + +#if !defined(CONFIG_IDENT_STRING) +#define CONFIG_IDENT_STRING "" +#endif + .data + .globl version_string + +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c new file mode 100644 index 0000000..2b7a569 --- /dev/null +++ b/cpu/nios2/sysid.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined (CFG_NIOS_SYSID_BASE) + +#include +#include +#include +#include + +void display_sysid (void) +{ + struct nios_sysid_t *sysid = + (struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE); + struct tm t; + char asc[32]; + + localtime_r ((time_t *)&sysid->timestamp, &t); + asctime_r (&t, asc); + printf ("SYSID : %08x, %s", sysid->id, asc); + +} + +int do_sysid (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + display_sysid (); + return (0); +} + +U_BOOT_CMD( + sysid, 1, 1, do_sysid, + "sysid - display Nios-II system id\n\n", + "\n - display Nios-II system id\n" +); +#endif /* CFG_NIOS_SYSID_BASE */ diff --git a/cpu/nios2/traps.c b/cpu/nios2/traps.c new file mode 100644 index 0000000..3f1517d --- /dev/null +++ b/cpu/nios2/traps.c @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void trap_handler (struct pt_regs *regs) +{ + /* Just issue warning */ + printf ("\n\n*** WARNING: unimplemented trap @ %08x\n\n", + regs->reg[29] - 4); +} + +void soft_emulation (struct pt_regs *regs) +{ + /* TODO: Software emulation of mul/div etc. Until this is + * implemented, generate warning and hang. + */ + printf ("\n\n*** ERROR: unimplemented instruction @ %08x\n", + regs->reg[29] - 4); + hang (); +} diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c new file mode 100644 index 0000000..64431ab --- /dev/null +++ b/cpu/ppc4xx/405gp_pci.c @@ -0,0 +1,553 @@ +/*-----------------------------------------------------------------------------+ + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *-----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ + * + * File Name: 405gp_pci.c + * + * Function: Initialization code for the 405GP PCI Configuration regs. + * + * Author: Mark Game + * + * Change Activity- + * + * Date Description of Change BY + * --------- --------------------- --- + * 09-Sep-98 Created MCG + * 02-Nov-98 Removed External arbiter selected message JWB + * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB + * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG + * from (0 to n) to (1 to n). + * 17-May-99 Port to Walnut JWB + * 17-Jun-99 Updated for VGA support JWB + * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB + * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG + * target latency timer values are not supported). + * Should be fixed in pass 2. + * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB + * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS. + * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB + * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not + * really required after a reset since PMMxMAs are already + * disabled but is a good practice nonetheless. JWB + * 12-Jun-01 stefan.roese@esd-electronics.com + * - PCI host/adapter handling reworked + * 09-Jul-01 stefan.roese@esd-electronics.com + * - PCI host now configures from device 0 (not 1) to max_dev, + * (host configures itself) + * - On CPCI-405 pci base address and size is generated from + * SDRAM and FLASH size (CFG regs not used anymore) + * - Some minor changes for CPCI-405-A (adapter version) + * 14-Sep-01 stefan.roese@esd-electronics.com + * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup + * 28-Sep-01 stefan.roese@esd-electronics.com + * - Changed pci master configuration for linux compatibility + * (no need for bios_fixup() anymore) + * 26-Feb-02 stefan.roese@esd-electronics.com + * - Bug fixed in pci configuration (Andrew May) + * - Removed pci class code init for CPCI405 board + * 15-May-02 stefan.roese@esd-electronics.com + * - New vga device handling + * 29-May-02 stefan.roese@esd-electronics.com + * - PCI class code init added (if defined) + *----------------------------------------------------------------------------*/ + +#include +#include +#if !defined(CONFIG_440) +#include <405gp_pci.h> +#endif +#include +#include + +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) + +#ifdef CONFIG_PCI + +/*#define DEBUG*/ + +/*-----------------------------------------------------------------------------+ + * pci_init. Initializes the 405GP PCI Configuration regs. + *-----------------------------------------------------------------------------*/ +void pci_405gp_init(struct pci_controller *hose) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i, reg_num = 0; + bd_t *bd = gd->bd; + + unsigned short temp_short; + unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; +#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) + unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart}; + unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1}; + char *ptmla_str, *ptmms_str; +#else + unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; + unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; +#endif +#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) + unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; + unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; + unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; + unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; +#else + unsigned long pmmla[3] = {0x80000000, 0,0}; + unsigned long pmmma[3] = {0xC0000001, 0,0}; + unsigned long pmmpcila[3] = {0x80000000, 0,0}; + unsigned long pmmpciha[3] = {0x00000000, 0,0}; +#endif +#ifdef CONFIG_PCI_PNP +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + char *s; +#endif +#endif + +#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) + ptmla_str = getenv("ptm1la"); + ptmms_str = getenv("ptm1ms"); + if(NULL != ptmla_str && NULL != ptmms_str ) { + ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); + ptmms[0] = simple_strtoul (ptmms_str, NULL, 16); + } + + ptmla_str = getenv("ptm2la"); + ptmms_str = getenv("ptm2ms"); + if(NULL != ptmla_str && NULL != ptmms_str ) { + ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); + ptmms[1] = simple_strtoul (ptmms_str, NULL, 16); + } +#endif + + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + MIN_PCI_PCI_IOADDR, + MIN_PLB_PCI_IOADDR, + 0x10000, + PCI_REGION_IO); + + /* PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + 0x00800000, + 0xe8800000, + 0x03800000, + PCI_REGION_IO); + + reg_num = 2; + + /* Memory spaces */ + for (i=0; i<2; i++) + if (ptmms[i] & 1) + { + if (!i) hose->pci_fb = hose->regions + reg_num; + + pci_set_region(hose->regions + reg_num++, + ptmpcila[i], ptmla[i], + ~(ptmms[i] & 0xfffff000) + 1, + PCI_REGION_MEM | + PCI_REGION_MEMORY); + } + + /* PCI memory spaces */ + for (i=0; i<3; i++) + if (pmmma[i] & 1) + { + pci_set_region(hose->regions + reg_num++, + pmmpcila[i], pmmla[i], + ~(pmmma[i] & 0xfffff000) + 1, + PCI_REGION_MEM); + } + + hose->region_count = reg_num; + + pci_setup_indirect(hose, + PCICFGADR, + PCICFGDATA); + + if (hose->pci_fb) + pciauto_region_init(hose->pci_fb); + + pci_register_hose(hose); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Master configuration. + * Map one 512 MB range of PLB/processor addresses to PCI memory space. + * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF + * Use byte reversed out routines to handle endianess. + *--------------------------------------------------------------------------*/ + out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */ + out32r(PMM0LA, pmmla[0]); + out32r(PMM0PCILA, pmmpcila[0]); + out32r(PMM0PCIHA, pmmpciha[0]); + out32r(PMM0MA, pmmma[0]); + + /*--------------------------------------------------------------------------+ + * PMM1 is not used. Initialize them to zero. + *--------------------------------------------------------------------------*/ + out32r(PMM1MA, (pmmma[1]&~0x1)); + out32r(PMM1LA, pmmla[1]); + out32r(PMM1PCILA, pmmpcila[1]); + out32r(PMM1PCIHA, pmmpciha[1]); + out32r(PMM1MA, pmmma[1]); + + /*--------------------------------------------------------------------------+ + * PMM2 is not used. Initialize them to zero. + *--------------------------------------------------------------------------*/ + out32r(PMM2MA, (pmmma[2]&~0x1)); + out32r(PMM2LA, pmmla[2]); + out32r(PMM2PCILA, pmmpcila[2]); + out32r(PMM2PCIHA, pmmpciha[2]); + out32r(PMM2MA, pmmma[2]); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Target configuration. (PTM1) + * Note: PTM1MS is hardwire enabled but we set the enable bit anyway. + *--------------------------------------------------------------------------*/ + out32r(PTM1LA, ptmla[0]); /* insert address */ + out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Target configuration. (PTM2) + *--------------------------------------------------------------------------*/ + out32r(PTM2LA, ptmla[1]); /* insert address */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]); + + if (ptmms[1] == 0) + { + out32r(PTM2MS, 0x00000001); /* set enable bit */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); + out32r(PTM2MS, 0x00000000); /* disable */ + } + else + { + out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ + } + + /* + * Insert Subsystem Vendor and Device ID + */ + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); +#ifdef CONFIG_CPCI405 + if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); + else + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2); +#else + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); +#endif + + /* + * Insert Class-code + */ +#ifdef CFG_PCI_CLASSCODE + pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE); +#endif /* CFG_PCI_CLASSCODE */ + + /*--------------------------------------------------------------------------+ + * If PCI speed = 66Mhz, set 66Mhz capable bit. + *--------------------------------------------------------------------------*/ + if (bd->bi_pci_busfreq >= 66000000) { + pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); + pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); + } + +#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) +#endif + { + /*--------------------------------------------------------------------------+ + * Write the 405GP PCI Configuration regs. + * Enable 405GP to be a master on the PCI bus (PMM). + * Enable 405GP to act as a PCI memory target (PTM). + *--------------------------------------------------------------------------*/ + pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + } +#endif + +#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */ + pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */ +#endif + + /* + * Set HCE bit (Host Configuration Enabled) + */ + pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); + +#ifdef CONFIG_PCI_PNP + /*--------------------------------------------------------------------------+ + * Scan the PCI bus and configure devices found. + *--------------------------------------------------------------------------*/ +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) +#endif + { +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + + hose->last_busno = pci_hose_scan(hose); + } +#endif /* CONFIG_PCI_PNP */ + +} + +/* + * drivers/pci.c skips every host bridge but the 405GP since it could + * be set as an Adapter. + * + * I (Andrew May) don't know what we should do here, but I don't want + * the auto setup of a PCI device disabling what is done pci_405gp_init + * as has happened before. + */ +void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) +{ +#ifdef DEBUG + printf("405gp_setup_bridge\n"); +#endif +} + +/* + * + */ + +void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line = 0xff; + + /* + * Write pci interrupt line register (cpci405 specific) + */ + switch (PCI_DEV(dev) & 0x03) + { + case 0: + int_line = 27 + 2; + break; + case 1: + int_line = 27 + 3; + break; + case 2: + int_line = 27 + 0; + break; + case 3: + int_line = 27 + 1; + break; + } + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); +} + +void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) +{ + unsigned int cmdstat = 0; + + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); + + /* always enable io space on vga boards */ + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); +} + +#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) + +/* + *As is these functs get called out of flash Not a horrible + *thing, but something to keep in mind. (no statics?) + */ +static struct pci_config_table pci_405gp_config_table[] = { +/*if VendID is 0 it terminates the table search (ie Walnut)*/ +#ifdef CFG_PCI_SUBSYS_VENDORID + {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, +#endif + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, + + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, + + { } +}; + +static struct pci_controller hose = { + fixup_irq: pci_405gp_fixup_irq, + config_table: pci_405gp_config_table, +}; + +void pci_init_board(void) +{ + /*we want the ptrs to RAM not flash (ie don't use init list)*/ + hose.fixup_irq = pci_405gp_fixup_irq; + hose.config_table = pci_405gp_config_table; + pci_405gp_init(&hose); +} + +#endif + +#endif /* CONFIG_PCI */ + +#endif /* CONFIG_405GP */ + +/*-----------------------------------------------------------------------------+ + * CONFIG_440 + *-----------------------------------------------------------------------------*/ +#if defined(CONFIG_440) && defined(CONFIG_PCI) + +static struct pci_controller ppc440_hose = {0}; + + +void pci_440_init (struct pci_controller *hose) +{ + int reg_num = 0; + +#ifndef CONFIG_DISABLE_PISE_TEST + /*--------------------------------------------------------------------------+ + * The PCI initialization sequence enable bit must be set ... if not abort + * pci setup since updating the bit requires chip reset. + *--------------------------------------------------------------------------*/ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) + unsigned long strap; + + mfsdr(sdr_sdstp1,strap); + if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { + printf("PCI: SDR0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#elif defined(CONFIG_440GP) + unsigned long strap; + + strap = mfdcr(cpc0_strp1); + if ((strap & CPC0_STRP1_PISE_MASK) == 0) { + printf("PCI: CPC0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#endif +#endif /* CONFIG_DISABLE_PISE_TEST */ + + /*--------------------------------------------------------------------------+ + * PCI controller init + *--------------------------------------------------------------------------*/ + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + reg_num++, + 0x00000000, + PCIX0_IOBASE, + 0x10000, + PCI_REGION_IO); + + pci_set_region(hose->regions + reg_num++, + CFG_PCI_TARGBASE, + CFG_PCI_MEMBASE, + 0x10000000, + PCI_REGION_MEM ); + hose->region_count = reg_num; + + pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); + +#if defined(CFG_PCI_PRE_INIT) + /* Let board change/modify hose & do initial checks */ + if (pci_pre_init (hose) == 0) { + printf("PCI: Board-specific initialization failed.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#endif + + pci_register_hose( hose ); + + /*--------------------------------------------------------------------------+ + * PCI target init + *--------------------------------------------------------------------------*/ +#if defined(CFG_PCI_TARGET_INIT) + pci_target_init(hose); /* Let board setup pci target */ +#else + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID ); + out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ +#endif + +#if defined(CONFIG_440GX) + out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ +#elif defined(PCIX0_BRDGOPT1) + out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ +#endif + + /*--------------------------------------------------------------------------+ + * PCI master init: default is one 256MB region for PCI memory: + * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE + *--------------------------------------------------------------------------*/ +#if defined(CFG_PCI_MASTER_INIT) + pci_master_init(hose); /* Let board setup pci master */ +#else + out32r( PCIX0_POM0SA, 0 ); /* disable */ + out32r( PCIX0_POM1SA, 0 ); /* disable */ + out32r( PCIX0_POM2SA, 0 ); /* disable */ + out32r( PCIX0_POM0LAL, 0x00000000 ); + out32r( PCIX0_POM0LAH, 0x00000003 ); + out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); + out32r( PCIX0_POM0PCIAH, 0x00000000 ); + out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ + out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); +#endif + + /*--------------------------------------------------------------------------+ + * PCI host configuration -- we don't make any assumptions here ... the + * _board_must_indicate_ what to do -- there's just too many runtime + * scenarios in environments like cPCI, PPMC, etc. to make a determination + * based on hard-coded values or state of arbiter enable. + *--------------------------------------------------------------------------*/ + if (is_pci_host(hose)) { +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif +#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) + out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); +#endif + hose->last_busno = pci_hose_scan(hose); + } +} + + +void pci_init_board(void) +{ + pci_440_init (&ppc440_hose); +} + +#endif /* CONFIG_440 & CONFIG_PCI */ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c new file mode 100644 index 0000000..86dc2d0 --- /dev/null +++ b/cpu/ppc4xx/4xx_enet.c @@ -0,0 +1,1564 @@ +/*-----------------------------------------------------------------------------+ + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *-----------------------------------------------------------------------------*/ +/*-----------------------------------------------------------------------------+ + * + * File Name: enetemac.c + * + * Function: Device driver for the ethernet EMAC3 macro on the 405GP. + * + * Author: Mark Wisner + * + * Change Activity- + * + * Date Description of Change BY + * --------- --------------------- --- + * 05-May-99 Created MKW + * 27-Jun-99 Clean up JWB + * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW + * 29-Jul-99 Added Full duplex support MKW + * 06-Aug-99 Changed names for Mal CR reg MKW + * 23-Aug-99 Turned off SYE when running at 10Mbs MKW + * 24-Aug-99 Marked descriptor empty after call_xlc MKW + * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG + * to avoid chaining maximum sized packets. Push starting + * RX descriptor address up to the next cache line boundary. + * 16-Jan-00 Added support for booting with IP of 0x0 MKW + * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the + * EMAC_RXM register. JWB + * 12-Mar-01 anne-sophie.harnois@nextream.fr + * - Variables are compatible with those already defined in + * include/net.h + * - Receive buffer descriptor ring is used to send buffers + * to the user + * - Info print about send/received/handled packet number if + * INFO_405_ENET is set + * 17-Apr-01 stefan.roese@esd-electronics.com + * - MAL reset in "eth_halt" included + * - Enet speed and duplex output now in one line + * 08-May-01 stefan.roese@esd-electronics.com + * - MAL error handling added (eth_init called again) + * 13-Nov-01 stefan.roese@esd-electronics.com + * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex + * 04-Jan-02 stefan.roese@esd-electronics.com + * - Wait for PHY auto negotiation to complete added + * 06-Feb-02 stefan.roese@esd-electronics.com + * - Bug fixed in waiting for auto negotiation to complete + * 26-Feb-02 stefan.roese@esd-electronics.com + * - rx and tx buffer descriptors now allocated (no fixed address + * used anymore) + * 17-Jun-02 stefan.roese@esd-electronics.com + * - MAL error debug printf 'M' removed (rx de interrupt may + * occur upon many incoming packets with only 4 rx buffers). + *-----------------------------------------------------------------------------* + * 17-Nov-03 travis.sawyer@sandburst.com + * - ported from 405gp_enet.c to utilized upto 4 EMAC ports + * in the 440GX. This port should work with the 440GP + * (2 EMACs) also + * 15-Aug-05 sr@denx.de + * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c + now handling all 4xx cpu's. + *-----------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include +#include +#include <405_mal.h> +#include +#include +#include "vecnum.h" + +/* + * Only compile for platform with AMCC EMAC ethernet controller and + * network support enabled. + * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! + */ +#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) + +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI) +#error "CONFIG_NET_MULTI has to be defined for NetConsole" +#endif + +#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ +#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ + +/* Ethernet Transmit and Receive Buffers */ +/* AS.HARNOIS + * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from + * PKTSIZE and PKTSIZE_ALIGN (include/net.h) + */ +#define ENET_MAX_MTU PKTSIZE +#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN + +/*-----------------------------------------------------------------------------+ + * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal + * Interrupt Controller). + *-----------------------------------------------------------------------------*/ +#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) +#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) +#define EMAC_UIC_DEF UIC_ENET +#define EMAC_UIC_DEF1 UIC_ENET1 +#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET ) + +#undef INFO_4XX_ENET + +#define BI_PHYMODE_NONE 0 +#define BI_PHYMODE_ZMII 1 +#define BI_PHYMODE_RGMII 2 + + +/*-----------------------------------------------------------------------------+ + * Global variables. TX and RX descriptors and buffers. + *-----------------------------------------------------------------------------*/ +/* IER globals */ +static uint32_t mal_ier; + +#if !defined(CONFIG_NET_MULTI) +struct eth_device *emac0_dev = NULL; +#endif + +/* + * Get count of EMAC devices (doesn't have to be the max. possible number + * supported by the cpu) + */ +#if defined(CONFIG_HAS_ETH3) +#define LAST_EMAC_NUM 4 +#elif defined(CONFIG_HAS_ETH2) +#define LAST_EMAC_NUM 3 +#elif defined(CONFIG_HAS_ETH1) +#define LAST_EMAC_NUM 2 +#else +#define LAST_EMAC_NUM 1 +#endif + +/*-----------------------------------------------------------------------------+ + * Prototypes and externals. + *-----------------------------------------------------------------------------*/ +static void enet_rcv (struct eth_device *dev, unsigned long malisr); + +int enetInt (struct eth_device *dev); +static void mal_err (struct eth_device *dev, unsigned long isr, + unsigned long uic, unsigned long maldef, + unsigned long mal_errr); +static void emac_err (struct eth_device *dev, unsigned long isr); + +extern int phy_setup_aneg (char *devname, unsigned char addr); +extern int emac4xx_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +extern int emac4xx_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value); + +/*-----------------------------------------------------------------------------+ +| ppc_4xx_eth_halt +| Disable MAL channel, and EMACn ++-----------------------------------------------------------------------------*/ +static void ppc_4xx_eth_halt (struct eth_device *dev) +{ + EMAC_4XX_HW_PST hw_p = dev->priv; + uint32_t failsafe = 10000; + + out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ + + /* 1st reset MAL channel */ + /* Note: writing a 0 to a channel has no effect */ +#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); +#else + mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); +#endif + mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); + + /* wait for reset */ + while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { + udelay (1000); /* Delay 1 MS so as not to hammer the register */ + failsafe--; + if (failsafe == 0) + break; + } + + /* EMAC RESET */ + out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + +#ifndef CONFIG_NETCONSOLE + hw_p->print_speed = 1; /* print speed message again next time */ +#endif + + return; +} + +#if defined (CONFIG_440GX) +int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) +{ + unsigned long pfc1; + unsigned long zmiifer; + unsigned long rmiifer; + + mfsdr(sdr_pfc1, pfc1); + pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); + + zmiifer = 0; + rmiifer = 0; + + switch (pfc1) { + case 1: + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_ZMII; + bis->bi_phymode[3] = BI_PHYMODE_ZMII; + break; + case 2: + zmiifer = ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer = ZMII_FER_SMII << ZMII_FER_V(1); + zmiifer = ZMII_FER_SMII << ZMII_FER_V(2); + zmiifer = ZMII_FER_SMII << ZMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_ZMII; + bis->bi_phymode[3] = BI_PHYMODE_ZMII; + break; + case 3: + zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_NONE; + bis->bi_phymode[2] = BI_PHYMODE_RGMII; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 4: + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_RGMII; + bis->bi_phymode[3] = BI_PHYMODE_RGMII; + break; + case 5: + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_ZMII; + bis->bi_phymode[3] = BI_PHYMODE_RGMII; + break; + case 6: + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); + zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); + rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_RGMII; + break; + case 0: + default: + zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); + rmiifer = 0x0; + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_ZMII; + bis->bi_phymode[3] = BI_PHYMODE_ZMII; + break; + } + + /* Ensure we setup mdio for this devnum and ONLY this devnum */ + zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); + + out32 (ZMII_FER, zmiifer); + out32 (RGMII_FER, rmiifer); + + return ((int)pfc1); + +} +#endif + +static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) +{ + int i, j; + unsigned long reg = 0; + unsigned long msr; + unsigned long speed; + unsigned long duplex; + unsigned long failsafe; + unsigned mode_reg; + unsigned short devnum; + unsigned short reg_short; +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) + sys_info_t sysinfo; +#if defined(CONFIG_440GX) + int ethgroup = -1; +#endif +#endif + + EMAC_4XX_HW_PST hw_p = dev->priv; + + /* before doing anything, figure out if we have a MAC address */ + /* if not, bail */ + if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { + printf("ERROR: ethaddr not set!\n"); + return -1; + } + +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) + /* Need to get the OPB frequency so we can access the PHY */ + get_sys_info (&sysinfo); +#endif + + msr = mfmsr (); + mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ + + devnum = hw_p->devnum; + +#ifdef INFO_4XX_ENET + /* AS.HARNOIS + * We should have : + * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX + * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it + * is possible that new packets (without relationship with + * current transfer) have got the time to arrived before + * netloop calls eth_halt + */ + printf ("About preceeding transfer (eth%d):\n" + "- Sent packet number %d\n" + "- Received packet number %d\n" + "- Handled packet number %d\n", + hw_p->devnum, + hw_p->stats.pkts_tx, + hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); + + hw_p->stats.pkts_tx = 0; + hw_p->stats.pkts_rx = 0; + hw_p->stats.pkts_handled = 0; +#endif + + hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ + hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ + + hw_p->rx_slot = 0; /* MAL Receive Slot */ + hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ + hw_p->rx_u_index = 0; /* Receive User Queue Index */ + + hw_p->tx_slot = 0; /* MAL Transmit Slot */ + hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ + hw_p->tx_u_index = 0; /* Transmit User Queue Index */ + +#if defined(CONFIG_440) && !defined(CONFIG_440SP) + /* set RMII mode */ + /* NOTE: 440GX spec states that mode is mutually exclusive */ + /* NOTE: Therefore, disable all other EMACS, since we handle */ + /* NOTE: only one emac at a time */ + reg = 0; + out32 (ZMII_FER, 0); + udelay (100); + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); +#elif defined(CONFIG_440GX) + ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); +#elif defined(CONFIG_440GP) + /* set RMII mode */ + out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); +#else + if ((devnum == 0) || (devnum == 1)) { + out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); + } + else { /* ((devnum == 2) || (devnum == 3)) */ + out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); + out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | + (RGMII_FER_RGMII << RGMII_FER_V (3)))); + } +#endif + + out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); +#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ + + __asm__ volatile ("eieio"); + + /* reset emac so we have access to the phy */ + + out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + __asm__ volatile ("eieio"); + + failsafe = 1000; + while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { + udelay (1000); + failsafe--; + } + +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) + /* Whack the M1 register */ + mode_reg = 0x0; + mode_reg &= ~0x00000038; + if (sysinfo.freqOPB <= 50000000); + else if (sysinfo.freqOPB <= 66666667) + mode_reg |= EMAC_M1_OBCI_66; + else if (sysinfo.freqOPB <= 83333333) + mode_reg |= EMAC_M1_OBCI_83; + else if (sysinfo.freqOPB <= 100000000) + mode_reg |= EMAC_M1_OBCI_100; + else + mode_reg |= EMAC_M1_OBCI_GT100; + + out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); +#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ + + /* wait for PHY to complete auto negotiation */ + reg_short = 0; +#ifndef CONFIG_CS8952_PHY + switch (devnum) { + case 0: + reg = CONFIG_PHY_ADDR; + break; +#if defined (CONFIG_PHY1_ADDR) + case 1: + reg = CONFIG_PHY1_ADDR; + break; +#endif +#if defined (CONFIG_440GX) + case 2: + reg = CONFIG_PHY2_ADDR; + break; + case 3: + reg = CONFIG_PHY3_ADDR; + break; +#endif + default: + reg = CONFIG_PHY_ADDR; + break; + } + + bis->bi_phynum[devnum] = reg; + +#if defined(CONFIG_PHY_RESET) + /* + * Reset the phy, only if its the first time through + * otherwise, just check the speeds & feeds + */ + if (hw_p->first_init == 0) { + miiphy_reset (dev->name, reg); + +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_CIS8201_PHY) + /* + * Cicada 8201 PHY needs to have an extended register whacked + * for RGMII mode. + */ + if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) { +#if defined(CONFIG_CIS8201_SHORT_ETCH) + miiphy_write (dev->name, reg, 23, 0x1300); +#else + miiphy_write (dev->name, reg, 23, 0x1000); +#endif + /* + * Vitesse VSC8201/Cicada CIS8201 errata: + * Interoperability problem with Intel 82547EI phys + * This work around (provided by Vitesse) changes + * the default timer convergence from 8ms to 12ms + */ + miiphy_write (dev->name, reg, 0x1f, 0x2a30); + miiphy_write (dev->name, reg, 0x08, 0x0200); + miiphy_write (dev->name, reg, 0x1f, 0x52b5); + miiphy_write (dev->name, reg, 0x02, 0x0004); + miiphy_write (dev->name, reg, 0x01, 0x0671); + miiphy_write (dev->name, reg, 0x00, 0x8fae); + miiphy_write (dev->name, reg, 0x1f, 0x2a30); + miiphy_write (dev->name, reg, 0x08, 0x0000); + miiphy_write (dev->name, reg, 0x1f, 0x0000); + /* end Vitesse/Cicada errata */ + } +#endif +#endif + /* Start/Restart autonegotiation */ + phy_setup_aneg (dev->name, reg); + udelay (1000); + } +#endif /* defined(CONFIG_PHY_RESET) */ + + miiphy_read (dev->name, reg, PHY_BMSR, ®_short); + + /* + * Wait if PHY is capable of autonegotiation and autonegotiation is not complete + */ + if ((reg_short & PHY_BMSR_AUTN_ABLE) + && !(reg_short & PHY_BMSR_AUTN_COMP)) { + puts ("Waiting for PHY auto negotiation to complete"); + i = 0; + while (!(reg_short & PHY_BMSR_AUTN_COMP)) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts (" TIMEOUT !\n"); + break; + } + + if ((i++ % 1000) == 0) { + putc ('.'); + } + udelay (1000); /* 1 ms */ + miiphy_read (dev->name, reg, PHY_BMSR, ®_short); + + } + puts (" done\n"); + udelay (500000); /* another 500 ms (results in faster booting) */ + } +#endif /* #ifndef CONFIG_CS8952_PHY */ + + speed = miiphy_speed (dev->name, reg); + duplex = miiphy_duplex (dev->name, reg); + + if (hw_p->print_speed) { + hw_p->print_speed = 0; + printf ("ENET Speed is %d Mbps - %s duplex connection\n", + (int) speed, (duplex == HALF) ? "HALF" : "FULL"); + } + +#if defined(CONFIG_440) && !defined(CONFIG_440SP) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + mfsdr(sdr_mfr, reg); + if (speed == 100) { + reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; + } else { + reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; + } + mtsdr(sdr_mfr, reg); +#endif + + /* Set ZMII/RGMII speed according to the phy link speed */ + reg = in32 (ZMII_SSR); + if ( (speed == 100) || (speed == 1000) ) + out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); + else + out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); + + if ((devnum == 2) || (devnum == 3)) { + if (speed == 1000) + reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); + else if (speed == 100) + reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); + else + reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); + + out32 (RGMII_SSR, reg); + } +#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ + + /* set the Mal configuration reg */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) + mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); +#else + mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); + /* Errata 1.12: MAL_1 -- Disable MAL bursting */ + if (get_pvr() == PVR_440GP_RB) { + mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + } +#endif + + /* Free "old" buffers */ + if (hw_p->alloc_tx_buf) + free (hw_p->alloc_tx_buf); + if (hw_p->alloc_rx_buf) + free (hw_p->alloc_rx_buf); + + /* + * Malloc MAL buffer desciptors, make sure they are + * aligned on cache line boundary size + * (401/403/IOP480 = 16, 405 = 32) + * and doesn't cross cache block boundaries. + */ + hw_p->alloc_tx_buf = + (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) + + ((2 * CFG_CACHELINE_SIZE) - 2)); + if (NULL == hw_p->alloc_tx_buf) + return -1; + if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) { + hw_p->tx = + (mal_desc_t *) ((int) hw_p->alloc_tx_buf + + CFG_CACHELINE_SIZE - + ((int) hw_p-> + alloc_tx_buf & CACHELINE_MASK)); + } else { + hw_p->tx = hw_p->alloc_tx_buf; + } + + hw_p->alloc_rx_buf = + (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) + + ((2 * CFG_CACHELINE_SIZE) - 2)); + if (NULL == hw_p->alloc_rx_buf) { + free(hw_p->alloc_tx_buf); + hw_p->alloc_tx_buf = NULL; + return -1; + } + + if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) { + hw_p->rx = + (mal_desc_t *) ((int) hw_p->alloc_rx_buf + + CFG_CACHELINE_SIZE - + ((int) hw_p-> + alloc_rx_buf & CACHELINE_MASK)); + } else { + hw_p->rx = hw_p->alloc_rx_buf; + } + + for (i = 0; i < NUM_TX_BUFF; i++) { + hw_p->tx[i].ctrl = 0; + hw_p->tx[i].data_len = 0; + if (hw_p->first_init == 0) { + hw_p->txbuf_ptr = + (char *) malloc (ENET_MAX_MTU_ALIGNED); + if (NULL == hw_p->txbuf_ptr) { + free(hw_p->alloc_rx_buf); + free(hw_p->alloc_tx_buf); + hw_p->alloc_rx_buf = NULL; + hw_p->alloc_tx_buf = NULL; + for(j = 0; j < i; j++) { + free(hw_p->tx[i].data_ptr); + hw_p->tx[i].data_ptr = NULL; + } + } + } + hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; + if ((NUM_TX_BUFF - 1) == i) + hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; + hw_p->tx_run[i] = -1; +#if 0 + printf ("TX_BUFF %d @ 0x%08lx\n", i, + (ulong) hw_p->tx[i].data_ptr); +#endif + } + + for (i = 0; i < NUM_RX_BUFF; i++) { + hw_p->rx[i].ctrl = 0; + hw_p->rx[i].data_len = 0; + /* rx[i].data_ptr = (char *) &rx_buff[i]; */ + hw_p->rx[i].data_ptr = (char *) NetRxPackets[i]; + if ((NUM_RX_BUFF - 1) == i) + hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; + hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; + hw_p->rx_ready[i] = -1; +#if 0 + printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); +#endif + } + + reg = 0x00000000; + + reg |= dev->enetaddr[0]; /* set high address */ + reg = reg << 8; + reg |= dev->enetaddr[1]; + + out32 (EMAC_IAH + hw_p->hw_addr, reg); + + reg = 0x00000000; + reg |= dev->enetaddr[2]; /* set low address */ + reg = reg << 8; + reg |= dev->enetaddr[3]; + reg = reg << 8; + reg |= dev->enetaddr[4]; + reg = reg << 8; + reg |= dev->enetaddr[5]; + + out32 (EMAC_IAL + hw_p->hw_addr, reg); + + switch (devnum) { + case 1: + /* setup MAL tx & rx channel pointers */ +#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) + mtdcr (maltxctp2r, hw_p->tx); +#else + mtdcr (maltxctp1r, hw_p->tx); +#endif +#if defined(CONFIG_440) + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); +#endif + mtdcr (malrxctp1r, hw_p->rx); + /* set RX buffer size */ + mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); + break; +#if defined (CONFIG_440GX) + case 2: + /* setup MAL tx & rx channel pointers */ + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); + mtdcr (maltxctp2r, hw_p->tx); + mtdcr (malrxctp2r, hw_p->rx); + /* set RX buffer size */ + mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); + break; + case 3: + /* setup MAL tx & rx channel pointers */ + mtdcr (maltxbattr, 0x0); + mtdcr (maltxctp3r, hw_p->tx); + mtdcr (malrxbattr, 0x0); + mtdcr (malrxctp3r, hw_p->rx); + /* set RX buffer size */ + mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); + break; +#endif /* CONFIG_440GX */ + case 0: + default: + /* setup MAL tx & rx channel pointers */ +#if defined(CONFIG_440) + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); +#endif + mtdcr (maltxctp0r, hw_p->tx); + mtdcr (malrxctp0r, hw_p->rx); + /* set RX buffer size */ + mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); + break; + } + + /* Enable MAL transmit and receive channels */ +#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); +#else + mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); +#endif + mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); + + /* set transmit enable & receive enable */ + out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + + /* set receive fifo to 4k and tx fifo to 2k */ + mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); + mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; + + /* set speed */ + if (speed == _1000BASET) { +#if defined(CONFIG_440SP) +#define SDR0_PFC1_EM_1000 0x00200000 + unsigned long pfc1; + mfsdr (sdr_pfc1, pfc1); + pfc1 |= SDR0_PFC1_EM_1000; + mtsdr (sdr_pfc1, pfc1); +#endif + mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; + } else if (speed == _100BASET) + mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; + else + mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ + if (duplex == FULL) + mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; + + out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); + + /* Enable broadcast and indvidual address */ + /* TBS: enabling runts as some misbehaved nics will send runts */ + out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); + + /* we probably need to set the tx mode1 reg? maybe at tx time */ + + /* set transmit request threshold register */ + out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ + + /* set receive low/high water mark register */ +#if defined(CONFIG_440) + /* 440GP has a 64 byte burst length */ + out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); +#else + /* 405s have a 16 byte burst length */ + out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); +#endif /* defined(CONFIG_440) */ + out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); + + /* Set fifo limit entry in tx mode 0 */ + out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); + /* Frame gap set */ + out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); + + /* Set EMAC IER */ + hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; + if (speed == _100BASET) + hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; + + out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ + out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); + + if (hw_p->first_init == 0) { + /* + * Connect interrupt service routines + */ + irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), + (interrupt_handler_t *) enetInt, dev); + } + + mtmsr (msr); /* enable interrupts again */ + + hw_p->bis = bis; + hw_p->first_init = 1; + + return (1); +} + + +static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, + int len) +{ + struct enet_frame *ef_ptr; + ulong time_start, time_now; + unsigned long temp_txm0; + EMAC_4XX_HW_PST hw_p = dev->priv; + + ef_ptr = (struct enet_frame *) ptr; + + /*-----------------------------------------------------------------------+ + * Copy in our address into the frame. + *-----------------------------------------------------------------------*/ + (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); + + /*-----------------------------------------------------------------------+ + * If frame is too long or too short, modify length. + *-----------------------------------------------------------------------*/ + /* TBS: where does the fragment go???? */ + if (len > ENET_MAX_MTU) + len = ENET_MAX_MTU; + + /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ + memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); + + /*-----------------------------------------------------------------------+ + * set TX Buffer busy, and send it + *-----------------------------------------------------------------------*/ + hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | + EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & + ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); + if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) + hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; + + hw_p->tx[hw_p->tx_slot].data_len = (short) len; + hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; + + __asm__ volatile ("eieio"); + + out32 (EMAC_TXM0 + hw_p->hw_addr, + in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); +#ifdef INFO_4XX_ENET + hw_p->stats.pkts_tx++; +#endif + + /*-----------------------------------------------------------------------+ + * poll unitl the packet is sent and then make sure it is OK + *-----------------------------------------------------------------------*/ + time_start = get_timer (0); + while (1) { + temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); + /* loop until either TINT turns on or 3 seconds elapse */ + if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { + /* transmit is done, so now check for errors + * If there is an error, an interrupt should + * happen when we return + */ + time_now = get_timer (0); + if ((time_now - time_start) > 3000) { + return (-1); + } + } else { + return (len); + } + } +} + + +#if defined (CONFIG_440) + +#if defined(CONFIG_440SP) +/* + * Hack: On 440SP all enet irq sources are located on UIC1 + * Needs some cleanup. --sr + */ +#define UIC0MSR uic1msr +#define UIC0SR uic1sr +#else +#define UIC0MSR uic0msr +#define UIC0SR uic0sr +#endif + +int enetInt (struct eth_device *dev) +{ + int serviced; + int rc = -1; /* default to not us */ + unsigned long mal_isr; + unsigned long emac_isr = 0; + unsigned long mal_rx_eob; + unsigned long my_uic0msr, my_uic1msr; + +#if defined(CONFIG_440GX) + unsigned long my_uic2msr; +#endif + EMAC_4XX_HW_PST hw_p; + + /* + * Because the mal is generic, we need to get the current + * eth device + */ +#if defined(CONFIG_NET_MULTI) + dev = eth_get_dev(); +#else + dev = emac0_dev; +#endif + + hw_p = dev->priv; + + /* enter loop that stays in interrupt code until nothing to service */ + do { + serviced = 0; + + my_uic0msr = mfdcr (UIC0MSR); + my_uic1msr = mfdcr (uic1msr); +#if defined(CONFIG_440GX) + my_uic2msr = mfdcr (uic2msr); +#endif + if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) + && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) { + /* not for us */ + return (rc); + } +#if defined (CONFIG_440GX) + if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) + && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) { + /* not for us */ + return (rc); + } +#endif + /* get and clear controller status interrupts */ + /* look at Mal and EMAC interrupts */ + if ((my_uic0msr & (UIC_MRE | UIC_MTE)) + || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { + /* we have a MAL interrupt */ + mal_isr = mfdcr (malesr); + /* look for mal error */ + if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { + mal_err (dev, mal_isr, my_uic0msr, + MAL_UIC_DEF, MAL_UIC_ERR); + serviced = 1; + rc = 0; + } + } + + /* port by port dispatch of emac interrupts */ + if (hw_p->devnum == 0) { + if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */ + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + if ((hw_p->emac_ier & emac_isr) != 0) { + emac_err (dev, emac_isr); + serviced = 1; + rc = 0; + } + } + if ((hw_p->emac_ier & emac_isr) + || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { + mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ + mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + return (rc); /* we had errors so get out */ + } + } + +#if !defined(CONFIG_440SP) + if (hw_p->devnum == 1) { + if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */ + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + if ((hw_p->emac_ier & emac_isr) != 0) { + emac_err (dev, emac_isr); + serviced = 1; + rc = 0; + } + } + if ((hw_p->emac_ier & emac_isr) + || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { + mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ + mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + return (rc); /* we had errors so get out */ + } + } +#if defined (CONFIG_440GX) + if (hw_p->devnum == 2) { + if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + if ((hw_p->emac_ier & emac_isr) != 0) { + emac_err (dev, emac_isr); + serviced = 1; + rc = 0; + } + } + if ((hw_p->emac_ier & emac_isr) + || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { + mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ + mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (uic2sr, UIC_ETH2); + return (rc); /* we had errors so get out */ + } + } + + if (hw_p->devnum == 3) { + if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + if ((hw_p->emac_ier & emac_isr) != 0) { + emac_err (dev, emac_isr); + serviced = 1; + rc = 0; + } + } + if ((hw_p->emac_ier & emac_isr) + || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { + mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ + mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (uic2sr, UIC_ETH3); + return (rc); /* we had errors so get out */ + } + } +#endif /* CONFIG_440GX */ +#endif /* !CONFIG_440SP */ + + /* handle MAX TX EOB interrupt from a tx */ + if (my_uic0msr & UIC_MTE) { + mal_rx_eob = mfdcr (maltxeobisr); + mtdcr (maltxeobisr, mal_rx_eob); + mtdcr (UIC0SR, UIC_MTE); + } + /* handle MAL RX EOB interupt from a receive */ + /* check for EOB on valid channels */ + if (my_uic0msr & UIC_MRE) { + mal_rx_eob = mfdcr (malrxeobisr); + if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ + /* clear EOB + mtdcr(malrxeobisr, mal_rx_eob); */ + enet_rcv (dev, emac_isr); + /* indicate that we serviced an interrupt */ + serviced = 1; + rc = 0; + } + } + + mtdcr (UIC0SR, UIC_MRE); /* Clear */ + mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + switch (hw_p->devnum) { + case 0: + mtdcr (uic1sr, UIC_ETH0); + break; + case 1: + mtdcr (uic1sr, UIC_ETH1); + break; +#if defined (CONFIG_440GX) + case 2: + mtdcr (uic2sr, UIC_ETH2); + break; + case 3: + mtdcr (uic2sr, UIC_ETH3); + break; +#endif /* CONFIG_440GX */ + default: + break; + } + } while (serviced); + + return (rc); +} + +#else /* CONFIG_440 */ + +int enetInt (struct eth_device *dev) +{ + int serviced; + int rc = -1; /* default to not us */ + unsigned long mal_isr; + unsigned long emac_isr = 0; + unsigned long mal_rx_eob; + unsigned long my_uicmsr; + + EMAC_4XX_HW_PST hw_p; + + /* + * Because the mal is generic, we need to get the current + * eth device + */ +#if defined(CONFIG_NET_MULTI) + dev = eth_get_dev(); +#else + dev = emac0_dev; +#endif + + hw_p = dev->priv; + + /* enter loop that stays in interrupt code until nothing to service */ + do { + serviced = 0; + + my_uicmsr = mfdcr (uicmsr); + + if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */ + return (rc); + } + /* get and clear controller status interrupts */ + /* look at Mal and EMAC interrupts */ + if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */ + mal_isr = mfdcr (malesr); + /* look for mal error */ + if ((my_uicmsr & MAL_UIC_ERR) != 0) { + mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR); + serviced = 1; + rc = 0; + } + } + + /* port by port dispatch of emac interrupts */ + + if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + if ((hw_p->emac_ier & emac_isr) != 0) { + emac_err (dev, emac_isr); + serviced = 1; + rc = 0; + } + } + if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) { + mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */ + return (rc); /* we had errors so get out */ + } + + /* handle MAX TX EOB interrupt from a tx */ + if (my_uicmsr & UIC_MAL_TXEOB) { + mal_rx_eob = mfdcr (maltxeobisr); + mtdcr (maltxeobisr, mal_rx_eob); + mtdcr (uicsr, UIC_MAL_TXEOB); + } + /* handle MAL RX EOB interupt from a receive */ + /* check for EOB on valid channels */ + if (my_uicmsr & UIC_MAL_RXEOB) + { + mal_rx_eob = mfdcr (malrxeobisr); + if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ + /* clear EOB + mtdcr(malrxeobisr, mal_rx_eob); */ + enet_rcv (dev, emac_isr); + /* indicate that we serviced an interrupt */ + serviced = 1; + rc = 0; + } + } + mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ + } + while (serviced); + + return (rc); +} + +#endif /* CONFIG_440 */ + +/*-----------------------------------------------------------------------------+ + * MAL Error Routine + *-----------------------------------------------------------------------------*/ +static void mal_err (struct eth_device *dev, unsigned long isr, + unsigned long uic, unsigned long maldef, + unsigned long mal_errr) +{ + EMAC_4XX_HW_PST hw_p = dev->priv; + + mtdcr (malesr, isr); /* clear interrupt */ + + /* clear DE interrupt */ + mtdcr (maltxdeir, 0xC0000000); + mtdcr (malrxdeir, 0x80000000); + +#ifdef INFO_4XX_ENET + printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); +#endif + + eth_init (hw_p->bis); /* start again... */ +} + +/*-----------------------------------------------------------------------------+ + * EMAC Error Routine + *-----------------------------------------------------------------------------*/ +static void emac_err (struct eth_device *dev, unsigned long isr) +{ + EMAC_4XX_HW_PST hw_p = dev->priv; + + printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); + out32 (EMAC_ISR + hw_p->hw_addr, isr); +} + +/*-----------------------------------------------------------------------------+ + * enet_rcv() handles the ethernet receive data + *-----------------------------------------------------------------------------*/ +static void enet_rcv (struct eth_device *dev, unsigned long malisr) +{ + struct enet_frame *ef_ptr; + unsigned long data_len; + unsigned long rx_eob_isr; + EMAC_4XX_HW_PST hw_p = dev->priv; + + int handled = 0; + int i; + int loop_count = 0; + + rx_eob_isr = mfdcr (malrxeobisr); + if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) { + /* clear EOB */ + mtdcr (malrxeobisr, rx_eob_isr); + + /* EMAC RX done */ + while (1) { /* do all */ + i = hw_p->rx_slot; + + if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) + || (loop_count >= NUM_RX_BUFF)) + break; + loop_count++; + hw_p->rx_slot++; + if (NUM_RX_BUFF == hw_p->rx_slot) + hw_p->rx_slot = 0; + handled++; + data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */ + if (data_len) { + if (data_len > ENET_MAX_MTU) /* Check len */ + data_len = 0; + else { + if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ + data_len = 0; + hw_p->stats.rx_err_log[hw_p-> + rx_err_index] + = hw_p->rx[i].ctrl; + hw_p->rx_err_index++; + if (hw_p->rx_err_index == + MAX_ERR_LOG) + hw_p->rx_err_index = + 0; + } /* emac_erros */ + } /* data_len < max mtu */ + } /* if data_len */ + if (!data_len) { /* no data */ + hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ + + hw_p->stats.data_len_err++; /* Error at Rx */ + } + + /* !data_len */ + /* AS.HARNOIS */ + /* Check if user has already eaten buffer */ + /* if not => ERROR */ + else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { + if (hw_p->is_receiving) + printf ("ERROR : Receive buffers are full!\n"); + break; + } else { + hw_p->stats.rx_frames++; + hw_p->stats.rx += data_len; + ef_ptr = (struct enet_frame *) hw_p->rx[i]. + data_ptr; +#ifdef INFO_4XX_ENET + hw_p->stats.pkts_rx++; +#endif + /* AS.HARNOIS + * use ring buffer + */ + hw_p->rx_ready[hw_p->rx_i_index] = i; + hw_p->rx_i_index++; + if (NUM_RX_BUFF == hw_p->rx_i_index) + hw_p->rx_i_index = 0; + + /* AS.HARNOIS + * free receive buffer only when + * buffer has been handled (eth_rx) + rx[i].ctrl |= MAL_RX_CTRL_EMPTY; + */ + } /* if data_len */ + } /* while */ + } /* if EMACK_RXCHL */ +} + + +static int ppc_4xx_eth_rx (struct eth_device *dev) +{ + int length; + int user_index; + unsigned long msr; + EMAC_4XX_HW_PST hw_p = dev->priv; + + hw_p->is_receiving = 1; /* tell driver */ + + for (;;) { + /* AS.HARNOIS + * use ring buffer and + * get index from rx buffer desciptor queue + */ + user_index = hw_p->rx_ready[hw_p->rx_u_index]; + if (user_index == -1) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + msr = mfmsr (); + mtmsr (msr & ~(MSR_EE)); + + length = hw_p->rx[user_index].data_len; + + /* Pass the packet up to the protocol layers. */ + /* NetReceive(NetRxPackets[rxIdx], length - 4); */ + /* NetReceive(NetRxPackets[i], length); */ + NetReceive (NetRxPackets[user_index], length - 4); + /* Free Recv Buffer */ + hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; + /* Free rx buffer descriptor queue */ + hw_p->rx_ready[hw_p->rx_u_index] = -1; + hw_p->rx_u_index++; + if (NUM_RX_BUFF == hw_p->rx_u_index) + hw_p->rx_u_index = 0; + +#ifdef INFO_4XX_ENET + hw_p->stats.pkts_handled++; +#endif + + mtmsr (msr); /* Enable IRQ's */ + } + + hw_p->is_receiving = 0; /* tell driver */ + + return length; +} + +int ppc_4xx_eth_initialize (bd_t * bis) +{ + static int virgin = 0; + struct eth_device *dev; + int eth_num = 0; + EMAC_4XX_HW_PST hw = NULL; + +#if defined(CONFIG_440GX) + unsigned long pfc1; + + mfsdr (sdr_pfc1, pfc1); + pfc1 &= ~(0x01e00000); + pfc1 |= 0x01200000; + mtsdr (sdr_pfc1, pfc1); +#endif + /* set phy num and mode */ + bis->bi_phynum[0] = CONFIG_PHY_ADDR; +#if defined(CONFIG_PHY1_ADDR) + bis->bi_phynum[1] = CONFIG_PHY1_ADDR; +#endif +#if defined(CONFIG_440GX) + bis->bi_phynum[2] = CONFIG_PHY2_ADDR; + bis->bi_phynum[3] = CONFIG_PHY3_ADDR; + bis->bi_phymode[0] = 0; + bis->bi_phymode[1] = 0; + bis->bi_phymode[2] = 2; + bis->bi_phymode[3] = 2; + +#if defined (CONFIG_440GX) + ppc_4xx_eth_setup_bridge(0, bis); +#endif +#endif + + for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { + + /* See if we can actually bring up the interface, otherwise, skip it */ + switch (eth_num) { + default: /* fall through */ + case 0: + if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; + continue; + } + break; +#ifdef CONFIG_HAS_ETH1 + case 1: + if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; + continue; + } + break; +#endif +#ifdef CONFIG_HAS_ETH2 + case 2: + if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; + continue; + } + break; +#endif +#ifdef CONFIG_HAS_ETH3 + case 3: + if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; + continue; + } + break; +#endif + } + + /* Allocate device structure */ + dev = (struct eth_device *) malloc (sizeof (*dev)); + if (dev == NULL) { + printf ("ppc_4xx_eth_initialize: " + "Cannot allocate eth_device %d\n", eth_num); + return (-1); + } + memset(dev, 0, sizeof(*dev)); + + /* Allocate our private use data */ + hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); + if (hw == NULL) { + printf ("ppc_4xx_eth_initialize: " + "Cannot allocate private hw data for eth_device %d", + eth_num); + free (dev); + return (-1); + } + memset(hw, 0, sizeof(*hw)); + + switch (eth_num) { + default: /* fall through */ + case 0: + hw->hw_addr = 0; + memcpy (dev->enetaddr, bis->bi_enetaddr, 6); + break; +#ifdef CONFIG_HAS_ETH1 + case 1: + hw->hw_addr = 0x100; + memcpy (dev->enetaddr, bis->bi_enet1addr, 6); + break; +#endif +#ifdef CONFIG_HAS_ETH2 + case 2: + hw->hw_addr = 0x400; + memcpy (dev->enetaddr, bis->bi_enet2addr, 6); + break; +#endif +#ifdef CONFIG_HAS_ETH3 + case 3: + hw->hw_addr = 0x600; + memcpy (dev->enetaddr, bis->bi_enet3addr, 6); + break; +#endif + } + + hw->devnum = eth_num; + hw->print_speed = 1; + + sprintf (dev->name, "ppc_4xx_eth%d", eth_num); + dev->priv = (void *) hw; + dev->init = ppc_4xx_eth_init; + dev->halt = ppc_4xx_eth_halt; + dev->send = ppc_4xx_eth_send; + dev->recv = ppc_4xx_eth_rx; + + if (0 == virgin) { + /* set the MAL IER ??? names may change with new spec ??? */ + mal_ier = + MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | + MAL_IER_OPBE | MAL_IER_PLBE; + mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ + mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ + mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ + mtdcr (malier, mal_ier); + + /* install MAL interrupt handler */ + irq_install_handler (VECNUM_MS, + (interrupt_handler_t *) enetInt, + dev); + irq_install_handler (VECNUM_MTE, + (interrupt_handler_t *) enetInt, + dev); + irq_install_handler (VECNUM_MRE, + (interrupt_handler_t *) enetInt, + dev); + irq_install_handler (VECNUM_TXDE, + (interrupt_handler_t *) enetInt, + dev); + irq_install_handler (VECNUM_RXDE, + (interrupt_handler_t *) enetInt, + dev); + virgin = 1; + } + +#if defined(CONFIG_NET_MULTI) + eth_register (dev); +#else + emac0_dev = dev; +#endif +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register (dev->name, + emac4xx_miiphy_read, emac4xx_miiphy_write); +#endif + + } /* end for each supported device */ + return (1); +} + + +#if !defined(CONFIG_NET_MULTI) +void eth_halt (void) { + if (emac0_dev) { + ppc_4xx_eth_halt(emac0_dev); + free(emac0_dev); + emac0_dev = NULL; + } +} + +int eth_init (bd_t *bis) +{ + ppc_4xx_eth_initialize(bis); + if (emac0_dev) { + return ppc_4xx_eth_init(emac0_dev, bis); + } else { + printf("ERROR: ethaddr not set!\n"); + return -1; + } +} + +int eth_send(volatile void *packet, int length) +{ + return (ppc_4xx_eth_send(emac0_dev, packet, length)); +} + +int eth_rx(void) +{ + return (ppc_4xx_eth_rx(emac0_dev)); +} + +int emac4xx_miiphy_initialize (bd_t * bis) +{ +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register ("ppc_4xx_eth0", + emac4xx_miiphy_read, emac4xx_miiphy_write); +#endif + + return 0; +} +#endif /* !defined(CONFIG_NET_MULTI) */ + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile new file mode 100644 index 0000000..c563457 --- /dev/null +++ b/cpu/ppc4xx/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o resetvec.o kgdb.o +AOBJS = dcr.o +COBJS = 405gp_pci.o 4xx_enet.o \ + bedbug_405.o commproc.o \ + cpu.o cpu_init.o i2c.o interrupts.o \ + miiphy.o sdram.o serial.o \ + spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o + +OBJS = $(AOBJS) $(COBJS) + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c new file mode 100644 index 0000000..a3c2119 --- /dev/null +++ b/cpu/ppc4xx/bedbug_405.c @@ -0,0 +1,308 @@ +/* + * Bedbug Functions specific to the PPC405 chip + */ + +#include +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_4xx) + +#define MAX_BREAK_POINTS 4 + +extern CPU_DEBUG_CTX bug_ctx; + +void bedbug405_init __P ((void)); +void bedbug405_do_break __P ((cmd_tbl_t *, int, int, char *[])); +void bedbug405_break_isr __P ((struct pt_regs *)); +int bedbug405_find_empty __P ((void)); +int bedbug405_set __P ((int, unsigned long)); +int bedbug405_clear __P ((int)); + + +/* ====================================================================== + * Initialize the global bug_ctx structure for the AMCC PPC405. Clear all + * of the breakpoints. + * ====================================================================== */ + +void bedbug405_init (void) +{ + int i; + + /* -------------------------------------------------- */ + + bug_ctx.hw_debug_enabled = 0; + bug_ctx.stopped = 0; + bug_ctx.current_bp = 0; + bug_ctx.regs = NULL; + + bug_ctx.do_break = bedbug405_do_break; + bug_ctx.break_isr = bedbug405_break_isr; + bug_ctx.find_empty = bedbug405_find_empty; + bug_ctx.set = bedbug405_set; + bug_ctx.clear = bedbug405_clear; + + for (i = 1; i <= MAX_BREAK_POINTS; ++i) + (*bug_ctx.clear) (i); + + puts ("BEDBUG:ready\n"); + return; +} /* bedbug_init_breakpoints */ + + + +/* ====================================================================== + * Set/clear/show one of the hardware breakpoints for the 405. The "off" + * string will disable a specific breakpoint. The "show" string will + * display the current breakpoints. Otherwise an address will set a + * breakpoint at that address. Setting a breakpoint uses the CPU-specific + * set routine which will assign a breakpoint number. + * ====================================================================== */ + +void bedbug405_do_break (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + long addr = 0; /* Address to break at */ + int which_bp; /* Breakpoint number */ + + /* -------------------------------------------------- */ + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return; + } + + /* Turn off a breakpoint */ + + if (strcmp (argv[1], "off") == 0) { + if (bug_ctx.hw_debug_enabled == 0) { + printf ("No breakpoints enabled\n"); + return; + } + + which_bp = simple_strtoul (argv[2], NULL, 10); + + if (bug_ctx.clear) + (*bug_ctx.clear) (which_bp); + + printf ("Breakpoint %d removed\n", which_bp); + return; + } + + /* Show a list of breakpoints */ + + if (strcmp (argv[1], "show") == 0) { + for (which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp) { + + switch (which_bp) { + case 1: + addr = GET_IAC1 (); + break; + case 2: + addr = GET_IAC2 (); + break; + case 3: + addr = GET_IAC3 (); + break; + case 4: + addr = GET_IAC4 (); + break; + } + + printf ("Breakpoint [%d]: ", which_bp); + if (addr == 0) + printf ("NOT SET\n"); + else + disppc ((unsigned char *) addr, 0, 1, bedbug_puts, + F_RADHEX); + } + return; + } + + /* Set a breakpoint at the address */ + + if (!isdigit (argv[1][0])) { + printf ("Usage:\n%s\n", cmdtp->usage); + return; + } + + addr = simple_strtoul (argv[1], NULL, 16) & 0xfffffffc; + + if ((bug_ctx.set) && (which_bp = (*bug_ctx.set) (0, addr)) > 0) { + printf ("Breakpoint [%d]: ", which_bp); + disppc ((unsigned char *) addr, 0, 1, bedbug_puts, F_RADHEX); + } + + return; +} /* bedbug405_do_break */ + + + +/* ====================================================================== + * Handle a breakpoint. First determine which breakpoint was hit by + * looking at the DeBug Status Register (DBSR), clear the breakpoint + * and enter a mini main loop. Stay in the loop until the stopped flag + * in the debug context is cleared. + * ====================================================================== */ + +void bedbug405_break_isr (struct pt_regs *regs) +{ + unsigned long dbsr_val; /* Value of the DBSR */ + unsigned long addr = 0; /* Address stopped at */ + + /* -------------------------------------------------- */ + + dbsr_val = GET_DBSR (); + + if (dbsr_val & DBSR_IA1) { + bug_ctx.current_bp = 1; + addr = GET_IAC1 (); + SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ + } else if (dbsr_val & DBSR_IA2) { + bug_ctx.current_bp = 2; + addr = GET_IAC2 (); + SET_DBSR (DBSR_IA2); /* Write a 1 to clear */ + } else if (dbsr_val & DBSR_IA3) { + bug_ctx.current_bp = 3; + addr = GET_IAC3 (); + SET_DBSR (DBSR_IA3); /* Write a 1 to clear */ + } else if (dbsr_val & DBSR_IA4) { + bug_ctx.current_bp = 4; + addr = GET_IAC4 (); + SET_DBSR (DBSR_IA4); /* Write a 1 to clear */ + } + + bedbug_main_loop (addr, regs); + return; +} /* bedbug405_break_isr */ + + + +/* ====================================================================== + * Look through all of the hardware breakpoints available to see if one + * is unused. + * ====================================================================== */ + +int bedbug405_find_empty (void) +{ + /* -------------------------------------------------- */ + + if (GET_IAC1 () == 0) + return 1; + + if (GET_IAC2 () == 0) + return 2; + + if (GET_IAC3 () == 0) + return 3; + + if (GET_IAC4 () == 0) + return 4; + + return 0; +} /* bedbug405_find_empty */ + + + +/* ====================================================================== + * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint + * number, otherwise reassign the given breakpoint. If hardware debugging + * is not enabled, then turn it on via the MSR and DBCR0. Set the break + * address in the appropriate IACx register and enable proper address + * beakpoint in DBCR0. + * ====================================================================== */ + +int bedbug405_set (int which_bp, unsigned long addr) +{ + /* -------------------------------------------------- */ + + /* Only look if which_bp == 0, else use which_bp */ + if ((bug_ctx.find_empty) && (!which_bp) && + (which_bp = (*bug_ctx.find_empty) ()) == 0) { + printf ("All breakpoints in use\n"); + return 0; + } + + if (which_bp < 1 || which_bp > MAX_BREAK_POINTS) { + printf ("Invalid break point # %d\n", which_bp); + return 0; + } + + if (!bug_ctx.hw_debug_enabled) { + SET_MSR (GET_MSR () | 0x200); /* set MSR[ DE ] */ + SET_DBCR0 (GET_DBCR0 () | DBCR0_IDM); + bug_ctx.hw_debug_enabled = 1; + } + + switch (which_bp) { + case 1: + SET_IAC1 (addr); + SET_DBCR0 (GET_DBCR0 () | DBCR0_IA1); + break; + + case 2: + SET_IAC2 (addr); + SET_DBCR0 (GET_DBCR0 () | DBCR0_IA2); + break; + + case 3: + SET_IAC3 (addr); + SET_DBCR0 (GET_DBCR0 () | DBCR0_IA3); + break; + + case 4: + SET_IAC4 (addr); + SET_DBCR0 (GET_DBCR0 () | DBCR0_IA4); + break; + } + + return which_bp; +} /* bedbug405_set */ + + + +/* ====================================================================== + * Disable a specific breakoint by setting the appropriate IACx register + * to zero and claring the instruction address breakpoint in DBCR0. + * ====================================================================== */ + +int bedbug405_clear (int which_bp) +{ + /* -------------------------------------------------- */ + + if (which_bp < 1 || which_bp > MAX_BREAK_POINTS) { + printf ("Invalid break point # (%d)\n", which_bp); + return -1; + } + + switch (which_bp) { + case 1: + SET_IAC1 (0); + SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA1); + break; + + case 2: + SET_IAC2 (0); + SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA2); + break; + + case 3: + SET_IAC3 (0); + SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA3); + break; + + case 4: + SET_IAC4 (0); + SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA4); + break; + } + + return 0; +} /* bedbug405_clear */ + + +/* ====================================================================== */ +#endif diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c new file mode 100644 index 0000000..68aab5b --- /dev/null +++ b/cpu/ppc4xx/commproc.c @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * Atapted for ppc4XX by Denis Peter + */ + +#include +#include + + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + +void post_word_store (ulong a) +{ + volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); + *(volatile ulong *) save_addr = a; +} + +ulong post_word_load (void) +{ + volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); + return *(volatile ulong *) save_addr; +} + +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ + +#ifdef CONFIG_BOOTCOUNT_LIMIT + +void bootcount_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR); + + save_addr[0] = a; + save_addr[1] = BOOTCOUNT_MAGIC; +} + +ulong bootcount_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR); + + if (save_addr[1] != BOOTCOUNT_MAGIC) + return 0; + else + return save_addr[0]; +} + +#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk new file mode 100644 index 0000000..119e061 --- /dev/null +++ b/cpu/ppc4xx/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing + +PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c new file mode 100644 index 0000000..a26533c --- /dev/null +++ b/cpu/ppc4xx/cpu.c @@ -0,0 +1,371 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + * + * written or collected and sometimes rewritten by + * Magnus Damm + * + * minor modifications by + * Wolfgang Denk + */ + +#include +#include +#include +#include +#include + + +#if defined(CONFIG_440) +#define FREQ_EBC (sys_info.freqEPB) +#else +#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) +#endif + +#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + +#define PCI_ASYNC + +int pci_async_enabled(void) +{ +#if defined(CONFIG_405GP) + return (mfdcr(strap) & PSR_PCI_ASYNC_EN); +#endif + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + unsigned long val; + + mfsdr(sdr_sdstp1, val); + return (val & SDR0_SDSTP1_PAME_MASK); +#endif +} +#endif + +#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405) +int pci_arbiter_enabled(void) +{ +#if defined(CONFIG_405GP) + return (mfdcr(strap) & PSR_PCI_ARBIT_EN); +#endif + +#if defined(CONFIG_405EP) + return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN); +#endif + +#if defined(CONFIG_440GP) + return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) + unsigned long val; + + mfsdr(sdr_sdstp1, val); + return (val & SDR0_SDSTP1_PAE_MASK); +#endif +} +#endif + +#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440GX) || defined(CONFIG_440SP) + +#define I2C_BOOTROM + +int i2c_bootrom_enabled(void) +{ +#if defined(CONFIG_405EP) + return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) + unsigned long val; + + mfsdr(sdr_sdcs, val); + return (val & SDR0_SDCS_SDD); +#endif +} +#endif + + +#if defined(CONFIG_440) +static int do_chip_reset(unsigned long sys0, unsigned long sys1); +#endif + + +int checkcpu (void) +{ +#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */ + DECLARE_GLOBAL_DATA_PTR; + uint pvr = get_pvr(); + ulong clock = gd->cpu_clk; + char buf[32]; + +#if !defined(CONFIG_IOP480) + sys_info_t sys_info; + + puts ("CPU: "); + + get_sys_info(&sys_info); + + puts("AMCC PowerPC 4"); + +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) + puts("05"); +#endif +#if defined(CONFIG_440) + puts("40"); +#endif + + switch (pvr) { + case PVR_405GP_RB: + puts("GP Rev. B"); + break; + + case PVR_405GP_RC: + puts("GP Rev. C"); + break; + + case PVR_405GP_RD: + puts("GP Rev. D"); + break; + +#ifdef CONFIG_405GP + case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ + puts("GP Rev. E"); + break; +#endif + + case PVR_405CR_RA: + puts("CR Rev. A"); + break; + + case PVR_405CR_RB: + puts("CR Rev. B"); + break; + +#ifdef CONFIG_405CR + case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ + puts("CR Rev. C"); + break; +#endif + + case PVR_405GPR_RB: + puts("GPr Rev. B"); + break; + + case PVR_405EP_RB: + puts("EP Rev. B"); + break; + +#if defined(CONFIG_440) + case PVR_440GP_RB: + puts("GP Rev. B"); + /* See errata 1.12: CHIP_4 */ + if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || + (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ + puts ( "\n\t CPC0_SYSx DCRs corrupted. " + "Resetting chip ...\n"); + udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ + do_chip_reset ( mfdcr(cpc0_strp0), + mfdcr(cpc0_strp1) ); + } + break; + + case PVR_440GP_RC: + puts("GP Rev. C"); + break; + + case PVR_440GX_RA: + puts("GX Rev. A"); + break; + + case PVR_440GX_RB: + puts("GX Rev. B"); + break; + + case PVR_440GX_RC: + puts("GX Rev. C"); + break; + + case PVR_440GX_RF: + puts("GX Rev. F"); + break; + + case PVR_440EP_RA: + puts("EP Rev. A"); + break; + +#ifdef CONFIG_440EP + case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ + puts("EP Rev. B"); + break; +#endif /* CONFIG_440EP */ + +#ifdef CONFIG_440GR + case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ + puts("GR Rev. A"); + break; +#endif /* CONFIG_440GR */ +#endif /* CONFIG_440 */ + + case PVR_440SP_RA: + puts("SP Rev. A"); + break; + + case PVR_440SP_RB: + puts("SP Rev. B"); + break; + + default: + printf (" UNKNOWN (PVR=%08x)", pvr); + break; + } + + printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), + sys_info.freqPLB / 1000000, + sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, + FREQ_EBC / 1000000); + +#if defined(I2C_BOOTROM) + printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); +#endif + +#if defined(CONFIG_PCI) + printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); +#endif + +#if defined(PCI_ASYNC) + if (pci_async_enabled()) { + printf (", PCI async ext clock used"); + } else { + printf (", PCI sync clock at %lu MHz", + sys_info.freqPLB / sys_info.pllPciDiv / 1000000); + } +#endif + +#if defined(CONFIG_PCI) + putc('\n'); +#endif + +#if defined(CONFIG_405EP) + printf (" 16 kB I-Cache 16 kB D-Cache"); +#elif defined(CONFIG_440) + printf (" 32 kB I-Cache 32 kB D-Cache"); +#else + printf (" 16 kB I-Cache %d kB D-Cache", + ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); +#endif +#endif /* !defined(CONFIG_IOP480) */ + +#if defined(CONFIG_IOP480) + printf ("PLX IOP480 (PVR=%08x)", pvr); + printf (" at %s MHz:", strmhz(buf, clock)); + printf (" %u kB I-Cache", 4); + printf (" %u kB D-Cache", 2); +#endif + +#endif /* !defined(CONFIG_405) */ + + putc ('\n'); + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE) + /*give reset to BCSR*/ + *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09; + +#else + + /* + * Initiate system reset in debug control register DBCR + */ + __asm__ __volatile__("lis 3, 0x3000" ::: "r3"); +#if defined(CONFIG_440) + __asm__ __volatile__("mtspr 0x134, 3"); +#else + __asm__ __volatile__("mtspr 0x3f2, 3"); +#endif + +#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/ + return 1; +} + +#if defined(CONFIG_440) +static int do_chip_reset (unsigned long sys0, unsigned long sys1) +{ + /* Changes to cpc0_sys0 and cpc0_sys1 require chip + * reset. + */ + mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ + mtdcr (cpc0_sys0, sys0); + mtdcr (cpc0_sys1, sys1); + mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ + mtspr (dbcr0, 0x20000000); /* Reset the chip */ + + return 1; +} +#endif + + +/* + * Get timebase clock frequency + */ +unsigned long get_tbclk (void) +{ +#if !defined(CONFIG_IOP480) + sys_info_t sys_info; + + get_sys_info(&sys_info); + return (sys_info.freqProcessor); +#else + return (66000000); +#endif + +} + + +#if defined(CONFIG_WATCHDOG) +void +watchdog_reset(void) +{ + int re_enable = disable_interrupts(); + reset_4xx_watchdog(); + if (re_enable) enable_interrupts(); +} + +void +reset_4xx_watchdog(void) +{ + /* + * Clear TSR(WIS) bit + */ + mtspr(tsr, 0x40000000); +} +#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c new file mode 100644 index 0000000..79cfba3 --- /dev/null +++ b/cpu/ppc4xx/cpu_init.c @@ -0,0 +1,268 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + + +#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) + +#ifdef CFG_INIT_DCACHE_CS +# if (CFG_INIT_DCACHE_CS == 0) +# define PBxAP pb0ap +# define PBxCR pb0cr +# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +# define PBxAP_VAL CFG_EBC_PB0AP +# define PBxCR_VAL CFG_EBC_PB0CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 1) +# define PBxAP pb1ap +# define PBxCR pb1cr +# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) +# define PBxAP_VAL CFG_EBC_PB1AP +# define PBxCR_VAL CFG_EBC_PB1CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 2) +# define PBxAP pb2ap +# define PBxCR pb2cr +# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) +# define PBxAP_VAL CFG_EBC_PB2AP +# define PBxCR_VAL CFG_EBC_PB2CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 3) +# define PBxAP pb3ap +# define PBxCR pb3cr +# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) +# define PBxAP_VAL CFG_EBC_PB3AP +# define PBxCR_VAL CFG_EBC_PB3CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 4) +# define PBxAP pb4ap +# define PBxCR pb4cr +# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) +# define PBxAP_VAL CFG_EBC_PB4AP +# define PBxCR_VAL CFG_EBC_PB4CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 5) +# define PBxAP pb5ap +# define PBxCR pb5cr +# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) +# define PBxAP_VAL CFG_EBC_PB5AP +# define PBxCR_VAL CFG_EBC_PB5CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 6) +# define PBxAP pb6ap +# define PBxCR pb6cr +# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) +# define PBxAP_VAL CFG_EBC_PB6AP +# define PBxCR_VAL CFG_EBC_PB6CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 7) +# define PBxAP pb7ap +# define PBxCR pb7cr +# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) +# define PBxAP_VAL CFG_EBC_PB7AP +# define PBxCR_VAL CFG_EBC_PB7CR +# endif +# endif +#endif /* CFG_INIT_DCACHE_CS */ + + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers + */ +void +cpu_init_f (void) +{ +#if defined(CONFIG_405EP) + /* + * GPIO0 setup (select GPIO or alternate function) + */ + out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ + out32(GPIO0_OSRL, CFG_GPIO0_OSRL); + out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ + out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); + out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TSRL, CFG_GPIO0_TSRL); + out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ + + /* + * Set EMAC noise filter bits + */ + mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); +#endif /* CONFIG_405EP */ + + /* + * External Bus Controller (EBC) Setup + */ +#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) + /* + * Move the next instructions into icache, since these modify the flash + * we are running from! + */ + asm volatile(" bl 0f" ::: "lr"); + asm volatile("0: mflr 3" ::: "r3"); + asm volatile(" addi 4, 0, 14" ::: "r4"); + asm volatile(" mtctr 4" ::: "ctr"); + asm volatile("1: icbt 0, 3"); + asm volatile(" addi 3, 3, 32" ::: "r3"); + asm volatile(" bdnz 1b" ::: "ctr", "cr0"); + asm volatile(" addis 3, 0, 0x0" ::: "r3"); + asm volatile(" ori 3, 3, 0xA000" ::: "r3"); + asm volatile(" mtctr 3" ::: "ctr"); + asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); + + mtebc(pb0ap, CFG_EBC_PB0AP); + mtebc(pb0cr, CFG_EBC_PB0CR); +#endif + +#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1)) + mtebc(pb1ap, CFG_EBC_PB1AP); + mtebc(pb1cr, CFG_EBC_PB1CR); +#endif + +#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2)) + mtebc(pb2ap, CFG_EBC_PB2AP); + mtebc(pb2cr, CFG_EBC_PB2CR); +#endif + +#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3)) + mtebc(pb3ap, CFG_EBC_PB3AP); + mtebc(pb3cr, CFG_EBC_PB3CR); +#endif + +#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) + mtebc(pb4ap, CFG_EBC_PB4AP); + mtebc(pb4cr, CFG_EBC_PB4CR); +#endif + +#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5)) + mtebc(pb5ap, CFG_EBC_PB5AP); + mtebc(pb5cr, CFG_EBC_PB5CR); +#endif + +#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6)) + mtebc(pb6ap, CFG_EBC_PB6AP); + mtebc(pb6cr, CFG_EBC_PB6CR); +#endif + +#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7)) + mtebc(pb7ap, CFG_EBC_PB7AP); + mtebc(pb7cr, CFG_EBC_PB7CR); +#endif + +#if defined(CONFIG_WATCHDOG) + unsigned long val; + + val = mfspr(tcr); +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + val |= 0xb8000000; /* generate system reset after 1.34 seconds */ +#else + val |= 0xf0000000; /* generate system reset after 2.684 seconds */ +#endif + mtspr(tcr, val); + + val = mfspr(tsr); + val |= 0x80000000; /* enable watchdog timer */ + mtspr(tsr, val); + + reset_4xx_watchdog(); +#endif /* CONFIG_WATCHDOG */ +} + +/* + * initialize higher level parts of CPU like time base and timers + */ +int cpu_init_r (void) +{ +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd = gd->bd; + unsigned long reg; +#if defined(CONFIG_405GP) + uint pvr = get_pvr(); +#endif + +#ifdef CFG_INIT_DCACHE_CS + /* + * Flush and invalidate dcache, then disable CS for temporary stack. + * Afterwards, this CS can be used for other purposes + */ + dcache_disable(); /* flush and invalidate dcache */ + mtebc(PBxAP, 0); + mtebc(PBxCR, 0); /* disable CS for temporary stack */ + +#if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) + /* + * Write new value into CS register + */ + mtebc(PBxAP, PBxAP_VAL); + mtebc(PBxCR, PBxCR_VAL); +#endif +#endif /* CFG_INIT_DCACHE_CS */ + + /* + * Write Ethernetaddress into on-chip register + */ + reg = 0x00000000; + reg |= bd->bi_enetaddr[0]; /* set high address */ + reg = reg << 8; + reg |= bd->bi_enetaddr[1]; + out32 (EMAC_IAH, reg); + + reg = 0x00000000; + reg |= bd->bi_enetaddr[2]; /* set low address */ + reg = reg << 8; + reg |= bd->bi_enetaddr[3]; + reg = reg << 8; + reg |= bd->bi_enetaddr[4]; + reg = reg << 8; + reg |= bd->bi_enetaddr[5]; + out32 (EMAC_IAL, reg); + +#if defined(CONFIG_405GP) + /* + * Set edge conditioning circuitry on PPC405GPr + * for compatibility to existing PPC405GP designs. + */ + if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { + mtdcr(ecr, 0x60606000); + } +#endif /* defined(CONFIG_405GP) */ +#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ + return (0); +} diff --git a/cpu/ppc4xx/dcr.S b/cpu/ppc4xx/dcr.S new file mode 100644 index 0000000..7102364 --- /dev/null +++ b/cpu/ppc4xx/dcr.S @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR) + +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#define _ASMLANGUAGE + +/***************************************************************************** + * + * XXX - DANGER + * These routines make use of self modifying code. DO NOT CALL THEM + * UNTIL THEY ARE RELOCATED TO RAM. Additionally, I do not + * recommend them for use in anything other than an interactive + * debugging environment. This is mainly due to performance reasons. + * + ****************************************************************************/ + +/* + * static void _create_MFDCR(unsigned short dcrn) + * + * Builds a 'mfdcr' instruction for get_dcr + * function. + */ + .section ".text" + .align 2 + .type _create_MFDCR,@function +_create_MFDCR: + /* + * Build up a 'mfdcr' instruction formatted as follows: + * + * OPCD | RT | DCRF | XO | CR | + * ---------------|--------------|--------------|----| + * 0 5 | 6 10 | 11 20 | 21 30 | 31 | + * | | DCRN | | | + * 31 | %r3 | (5..9|0..4) | 323 | 0 | + * + * Where: + * OPCD = opcode - 31 + * RT = destination register - %r3 return register + * DCRF = DCRN # with upper and lower halves swapped + * XO = extended opcode - 323 + * CR = CR[CR0] NOT undefined - 0 + */ + rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */ + rlwinm r3, r3, 5, 22, 26 + or r3, r3, r0 + slwi r3, r3, 10 + oris r3, r3, 0x3e30 /* RT = %r3 */ + ori r3, r3, 323 /* XO = 323 */ + slwi r3, r3, 1 /* CR = 0 */ + + mflr r4 + stw r3, 0(r4) /* Store instr in get_dcr() */ + dcbst r0, r4 /* Make sure val is written out */ + sync /* Wait for write to complete */ + icbi r0, r4 /* Make sure old instr is dumped */ + isync /* Wait for icbi to complete */ + + blr +.Lfe1: .size _create_MFDCR,.Lfe1-_create_MFDCR +/* end _create_MFDCR() */ + +/* + * static void _create_MTDCR(unsigned short dcrn, unsigned long value) + * + * Builds a 'mtdcr' instruction for set_dcr + * function. + */ + .section ".text" + .align 2 + .type _create_MTDCR,@function +_create_MTDCR: + /* + * Build up a 'mtdcr' instruction formatted as follows: + * + * OPCD | RS | DCRF | XO | CR | + * ---------------|--------------|--------------|----| + * 0 5 | 6 10 | 11 20 | 21 30 | 31 | + * | | DCRN | | | + * 31 | %r3 | (5..9|0..4) | 451 | 0 | + * + * Where: + * OPCD = opcode - 31 + * RS = source register - %r4 + * DCRF = dest. DCRN # with upper and lower halves swapped + * XO = extended opcode - 451 + * CR = CR[CR0] NOT undefined - 0 + */ + rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */ + rlwinm r3, r3, 5, 22, 26 + or r3, r3, r0 + slwi r3, r3, 10 + oris r3, r3, 0x3e40 /* RS = %r4 */ + ori r3, r3, 451 /* XO = 451 */ + slwi r3, r3, 1 /* CR = 0 */ + + mflr r5 + stw r3, 0(r5) /* Store instr in set_dcr() */ + dcbst r0, r5 /* Make sure val is written out */ + sync /* Wait for write to complete */ + icbi r0, r5 /* Make sure old instr is dumped */ + isync /* Wait for icbi to complete */ + + blr +.Lfe2: .size _create_MTDCR,.Lfe2-_create_MTDCR +/* end _create_MTDCR() */ + + +/* + * unsigned long get_dcr(unsigned short dcrn) + * + * Return a given DCR's value. + */ + /* */ + /* XXX - This is self modifying code, hence */ + /* it is in the data section. */ + /* */ + .section ".data" + .align 2 + .globl get_dcr + .type get_dcr,@function +get_dcr: + mflr r0 /* Get link register */ + stwu r1, -32(r1) /* Save back chain and move SP */ + stw r0, +36(r1) /* Save link register */ + + bl _create_MFDCR /* Build following instruction */ + /* XXX - we build this instuction up on the fly. */ + .long 0 /* Get DCR's value */ + + lwz r0, +36(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + addi r1, r1, +32 /* Remove frame from stack */ + blr /* Return to calling function */ +.Lfe3: .size get_dcr,.Lfe3-get_dcr +/* end get_dcr() */ + + +/* + * unsigned void set_dcr(unsigned short dcrn, unsigned long value) + * + * Return a given DCR's value. + */ + /* + * XXX - This is self modifying code, hence + * it is in the data section. + */ + .section ".data" + .align 2 + .globl set_dcr + .type set_dcr,@function +set_dcr: + mflr r0 /* Get link register */ + stwu r1, -32(r1) /* Save back chain and move SP */ + stw r0, +36(r1) /* Save link register */ + + bl _create_MTDCR /* Build following instruction */ + /* XXX - we build this instuction up on the fly. */ + .long 0 /* Set DCR's value */ + + lwz r0, +36(r1) /* Get saved link register */ + mtlr r0 /* Restore link register */ + addi r1, r1, +32 /* Remove frame from stack */ + blr /* Return to calling function */ +.Lfe4: .size set_dcr,.Lfe4-set_dcr +/* end set_dcr() */ +#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c new file mode 100644 index 0000000..be94b57 --- /dev/null +++ b/cpu/ppc4xx/i2c.c @@ -0,0 +1,445 @@ +/*****************************************************************************/ +/* I2C Bus interface initialisation and I2C Commands */ +/* for PPC405GP */ +/* Author : AS HARNOIS */ +/* Date : 13.Dec.00 */ +/*****************************************************************************/ + +#include +#include +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif +#include + +#ifdef CONFIG_HARD_I2C + +#define IIC_OK 0 +#define IIC_NOK 1 +#define IIC_NOK_LA 2 /* Lost arbitration */ +#define IIC_NOK_ICT 3 /* Incomplete transfer */ +#define IIC_NOK_XFRA 4 /* Transfer aborted */ +#define IIC_NOK_DATA 5 /* No data in buffer */ +#define IIC_NOK_TOUT 6 /* Transfer timeout */ + +#define IIC_TIMEOUT 1 /* 1 seconde */ + + +static void _i2c_bus_reset (void) +{ + int i, status; + + /* Reset status register */ + /* write 1 in SCMP and IRQA to clear these fields */ + out8 (IIC_STS, 0x0A); + + /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ + out8 (IIC_EXTSTS, 0x8F); + __asm__ volatile ("eieio"); + + /* + * Get current state, reset bus + * only if no transfers are pending. + */ + i = 10; + do { + /* Get status */ + status = in8 (IIC_STS); + udelay (500); /* 500us */ + i--; + } while ((status & IIC_STS_PT) && (i > 0)); + /* Soft reset controller */ + status = in8 (IIC_XTCNTLSS); + out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST)); + __asm__ volatile ("eieio"); + + /* make sure where in initial state, data hi, clock hi */ + out8 (IIC_DIRECTCNTL, 0xC); + for (i = 0; i < 10; i++) { + if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) { + /* clock until we get to known state */ + out8 (IIC_DIRECTCNTL, 0x8); /* clock lo */ + udelay (100); /* 100us */ + out8 (IIC_DIRECTCNTL, 0xC); /* clock hi */ + udelay (100); /* 100us */ + } else { + break; + } + } + /* send start condition */ + out8 (IIC_DIRECTCNTL, 0x4); + udelay (1000); /* 1ms */ + /* send stop condition */ + out8 (IIC_DIRECTCNTL, 0xC); + udelay (1000); /* 1ms */ + /* Unreset controller */ + out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST)); + udelay (1000); /* 1ms */ +} + +void i2c_init (int speed, int slaveadd) +{ + sys_info_t sysInfo; + unsigned long freqOPB; + int val, divisor; + +#ifdef CFG_I2C_INIT_BOARD + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#endif + + /* Handle possible failed I2C state */ + /* FIXME: put this into i2c_init_board()? */ + _i2c_bus_reset (); + + /* clear lo master address */ + out8 (IIC_LMADR, 0); + + /* clear hi master address */ + out8 (IIC_HMADR, 0); + + /* clear lo slave address */ + out8 (IIC_LSADR, 0); + + /* clear hi slave address */ + out8 (IIC_HSADR, 0); + + /* Clock divide Register */ + /* get OPB frequency */ + get_sys_info (&sysInfo); + freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; + /* set divisor according to freqOPB */ + divisor = (freqOPB - 1) / 10000000; + if (divisor == 0) + divisor = 1; + out8 (IIC_CLKDIV, divisor); + + /* no interrupts */ + out8 (IIC_INTRMSK, 0); + + /* clear transfer count */ + out8 (IIC_XFRCNT, 0); + + /* clear extended control & stat */ + /* write 1 in SRC SRS SWC SWS to clear these fields */ + out8 (IIC_XTCNTLSS, 0xF0); + + /* Mode Control Register + Flush Slave/Master data buffer */ + out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); + __asm__ volatile ("eieio"); + + + val = in8(IIC_MDCNTL); + __asm__ volatile ("eieio"); + + /* Ignore General Call, slave transfers are ignored, + disable interrupts, exit unknown bus state, enable hold + SCL + 100kHz normaly or FastMode for 400kHz and above + */ + + val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL; + if( speed >= 400000 ){ + val |= IIC_MDCNTL_FSM; + } + out8 (IIC_MDCNTL, val); + + /* clear control reg */ + out8 (IIC_CNTL, 0x00); + __asm__ volatile ("eieio"); + +} + +/* + This code tries to use the features of the 405GP i2c + controller. It will transfer up to 4 bytes in one pass + on the loop. It only does out8(lbz) to the buffer when it + is possible to do out16(lhz) transfers. + + cmd_type is 0 for write 1 for read. + + addr_len can take any value from 0-255, it is only limited + by the char, we could make it larger if needed. If it is + 0 we skip the address write cycle. + + Typical case is a Write of an addr followd by a Read. The + IBM FAQ does not cover this. On the last byte of the write + we don't set the creg CHT bit, and on the first bytes of the + read we set the RPST bit. + + It does not support address only transfers, there must be + a data part. If you want to write the address yourself, put + it in the data pointer. + + It does not support transfer to/from address 0. + + It does not check XFRCNT. +*/ +static +int i2c_transfer(unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], + unsigned short data_len ) +{ + unsigned char* ptr; + int reading; + int tran,cnt; + int result; + int status; + int i; + uchar creg; + + if( data == 0 || data_len == 0 ){ + /*Don't support data transfer of no length or to address 0*/ + printf( "i2c_transfer: bad call\n" ); + return IIC_NOK; + } + if( addr && addr_len ){ + ptr = addr; + cnt = addr_len; + reading = 0; + }else{ + ptr = data; + cnt = data_len; + reading = cmd_type; + } + + /*Clear Stop Complete Bit*/ + out8(IIC_STS,IIC_STS_SCMP); + /* Check init */ + i=10; + do { + /* Get status */ + status = in8(IIC_STS); + __asm__ volatile("eieio"); + i--; + } while ((status & IIC_STS_PT) && (i>0)); + + if (status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + return(result); + } + /*flush the Master/Slave Databuffers*/ + out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); + /*need to wait 4 OPB clocks? code below should take that long*/ + + /* 7-bit adressing */ + out8(IIC_HMADR,0); + out8(IIC_LMADR, chip); + __asm__ volatile("eieio"); + + tran = 0; + result = IIC_OK; + creg = 0; + + while ( tran != cnt && (result == IIC_OK)) { + int bc,j; + + /* Control register = + Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start, + Transfer is a sequence of transfers + */ + creg |= IIC_CNTL_PT; + + bc = (cnt - tran) > 4 ? 4 : + cnt - tran; + creg |= (bc-1)<<4; + /* if the real cmd type is write continue trans*/ + if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) ) + creg |= IIC_CNTL_CHT; + + if (reading) + creg |= IIC_CNTL_READ; + else { + for(j=0; j0)); + + if (status & IIC_STS_ERR) { + result = IIC_NOK; + status = in8 (IIC_EXTSTS); + /* Lost arbitration? */ + if (status & IIC_EXTSTS_LA) + result = IIC_NOK_LA; + /* Incomplete transfer? */ + if (status & IIC_EXTSTS_ICT) + result = IIC_NOK_ICT; + /* Transfer aborted? */ + if (status & IIC_EXTSTS_XFRA) + result = IIC_NOK_XFRA; + } else if ( status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + } + /* Command is reading => get buffer */ + if ((reading) && (result == IIC_OK)) { + /* Are there data in buffer */ + if (status & IIC_STS_MDBS) { + /* + even if we have data we have to wait 4OPB clocks + for it to hit the front of the FIFO, after that + we can just read. We should check XFCNT here and + if the FIFO is full there is no need to wait. + */ + udelay (1); + for(j=0;jed (i.e. there was a chip at that address which + * drove the data line low). + */ + return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0); +} + + +int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + int ret; + DECLARE_GLOBAL_DATA_PTR; + + if ( alen > 4 ) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if ( alen > 0 ) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if( alen > 0 ) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { + if (gd->have_console) + printf( "I2c read: failed %d\n", ret); + return 1; + } + return 0; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + + if ( alen > 4 ) { + printf ("I2C write: addr len %d not supported\n", alen); + return 1; + + } + if ( alen > 0 ) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if( alen > 0 ) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + + return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); +} + +/*----------------------------------------------------------------------- + * Read a register + */ +uchar i2c_reg_read(uchar i2c_addr, uchar reg) +{ + uchar buf; + + i2c_read(i2c_addr, reg, 1, &buf, 1); + + return(buf); +} + +/*----------------------------------------------------------------------- + * Write a register + */ +void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write(i2c_addr, reg, 1, &val, 1); +} +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c new file mode 100644 index 0000000..1d8dc7c --- /dev/null +++ b/cpu/ppc4xx/interrupts.c @@ -0,0 +1,571 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 (440 port) + * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com + * + * (C) Copyright 2003 (440GX port) + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "vecnum.h" + +/****************************************************************************/ + +/* + * CPM interrupt vector functions. + */ +struct irq_action { + interrupt_handler_t *handler; + void *arg; + int count; +}; + +static struct irq_action irq_vecs[32]; + +#if defined(CONFIG_440) +static struct irq_action irq_vecs1[32]; /* For UIC1 */ + +void uic1_interrupt( void * parms); /* UIC1 handler */ + +#if defined(CONFIG_440GX) +static struct irq_action irq_vecs2[32]; /* For UIC2 */ + +void uic0_interrupt( void * parms); /* UIC0 handler */ +void uic2_interrupt( void * parms); /* UIC2 handler */ +#endif /* CONFIG_440GX */ + +#endif /* CONFIG_440 */ + +/****************************************************************************/ +#if defined(CONFIG_440) + +/* SPRN changed in 440 */ +static __inline__ void set_evpr(unsigned long val) +{ + asm volatile("mtspr 0x03f,%0" : : "r" (val)); +} + +#else /* !defined(CONFIG_440) */ + +static __inline__ void set_pit(unsigned long val) +{ + asm volatile("mtpit %0" : : "r" (val)); +} + + +static __inline__ void set_tcr(unsigned long val) +{ + asm volatile("mttcr %0" : : "r" (val)); +} + + +static __inline__ void set_evpr(unsigned long val) +{ + asm volatile("mtevpr %0" : : "r" (val)); +} +#endif /* defined(CONFIG_440 */ + +/****************************************************************************/ + +int interrupt_init_cpu (unsigned *decrementer_count) +{ + DECLARE_GLOBAL_DATA_PTR; + + int vec; + unsigned long val; + + /* decrementer is automatically reloaded */ + *decrementer_count = 0; + + /* + * Mark all irqs as free + */ + for (vec=0; vec<32; vec++) { + irq_vecs[vec].handler = NULL; + irq_vecs[vec].arg = NULL; + irq_vecs[vec].count = 0; +#if defined(CONFIG_440) + irq_vecs1[vec].handler = NULL; + irq_vecs1[vec].arg = NULL; + irq_vecs1[vec].count = 0; +#if defined(CONFIG_440GX) + irq_vecs2[vec].handler = NULL; + irq_vecs2[vec].arg = NULL; + irq_vecs2[vec].count = 0; +#endif /* CONFIG_440GX */ +#endif + } + +#ifdef CONFIG_4xx + /* + * Init PIT + */ +#if defined(CONFIG_440) + val = mfspr( tcr ); + val &= (~0x04400000); /* clear DIS & ARE */ + mtspr( tcr, val ); + mtspr( dec, 0 ); /* Prevent exception after TSR clear*/ + mtspr( decar, 0 ); /* clear reload */ + mtspr( tsr, 0x08000000 ); /* clear DEC status */ + val = gd->bd->bi_intfreq/1000; /* 1 msec */ + mtspr( decar, val ); /* Set auto-reload value */ + mtspr( dec, val ); /* Set inital val */ +#else + set_pit(gd->bd->bi_intfreq / 1000); +#endif +#endif /* CONFIG_4xx */ + +#ifdef CONFIG_ADCIOP + /* + * Init PIT + */ + set_pit(66000); +#endif + + /* + * Enable PIT + */ + val = mfspr(tcr); + val |= 0x04400000; + mtspr(tcr, val); + + /* + * Set EVPR to 0 + */ + set_evpr(0x00000000); + +#if defined(CONFIG_440) +#if !defined(CONFIG_440GX) + /* Install the UIC1 handlers */ + irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0); + irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0); +#endif +#endif + +#if defined(CONFIG_440GX) + /* Take the GX out of compatibility mode + * Travis Sawyer, 9 Mar 2004 + * NOTE: 440gx user manual inconsistency here + * Compatibility mode and Ethernet Clock select are not + * correct in the manual + */ + mfsdr(sdr_mfr, val); + val &= ~0x10000000; + mtsdr(sdr_mfr,val); + + /* Enable UIC interrupts via UIC Base Enable Register */ + mtdcr(uicb0sr, UICB0_ALL); + mtdcr(uicb0er, 0x54000000); + /* None are critical */ + mtdcr(uicb0cr, 0); +#endif + + return (0); +} + +/****************************************************************************/ + +/* + * Handle external interrupts + */ +#if defined(CONFIG_440GX) +void external_interrupt(struct pt_regs *regs) +{ + ulong uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + /* 440 GX uses base uic register */ + uic_msr = mfdcr(uicb0msr); + + if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) ) + uic0_interrupt(0); + + if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) + uic1_interrupt(0); + + if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) + uic2_interrupt(0); + + mtdcr(uicb0sr, uic_msr); + + return; + +} /* external_interrupt CONFIG_440GX */ + +#else + +void external_interrupt(struct pt_regs *regs) +{ + ulong uic_msr; + ulong msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = mfdcr(uicmsr); + msr_shift = uic_msr; + vec = 0; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs[vec].count++; + + if (irq_vecs[vec].handler != NULL) { + /* call isr */ + (*irq_vecs[vec].handler)(irq_vecs[vec].arg); + } else { + mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector 0x%x\n", vec); + } + + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uicsr, (0x80000000 >> vec)); + } + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} +#endif + +#if defined(CONFIG_440GX) +/* Handler for UIC0 interrupt */ +void uic0_interrupt( void * parms) +{ + ulong uic_msr; + ulong msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = mfdcr(uicmsr); + msr_shift = uic_msr; + vec = 0; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs[vec].count++; + + if (irq_vecs[vec].handler != NULL) { + /* call isr */ + (*irq_vecs[vec].handler)(irq_vecs[vec].arg); + } else { + mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec); + } + + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uicsr, (0x80000000 >> vec)); + } + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} + +#endif /* CONFIG_440GX */ + +#if defined(CONFIG_440) +/* Handler for UIC1 interrupt */ +void uic1_interrupt( void * parms) +{ + ulong uic1_msr; + ulong msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic1_msr = mfdcr(uic1msr); + msr_shift = uic1_msr; + vec = 0; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs1[vec].count++; + + if (irq_vecs1[vec].handler != NULL) { + /* call isr */ + (*irq_vecs1[vec].handler)(irq_vecs1[vec].arg); + } else { + mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec); + } + + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uic1sr, (0x80000000 >> vec)); + } + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} +#endif /* defined(CONFIG_440) */ + +#if defined(CONFIG_440GX) +/* Handler for UIC1 interrupt */ +void uic2_interrupt( void * parms) +{ + ulong uic2_msr; + ulong msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic2_msr = mfdcr(uic2msr); + msr_shift = uic2_msr; + vec = 0; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs2[vec].count++; + + if (irq_vecs2[vec].handler != NULL) { + /* call isr */ + (*irq_vecs2[vec].handler)(irq_vecs2[vec].arg); + } else { + mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec); + } + + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uic2sr, (0x80000000 >> vec)); + } + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} +#endif /* defined(CONFIG_440GX) */ + +/****************************************************************************/ + +/* + * Install and free a interrupt handler. + */ + +void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) +{ + struct irq_action *irqa = irq_vecs; + int i = vec; + +#if defined(CONFIG_440) +#if defined(CONFIG_440GX) + if ((vec > 31) && (vec < 64)) { + i = vec - 32; + irqa = irq_vecs1; + } else if (vec > 63) { + i = vec - 64; + irqa = irq_vecs2; + } +#else /* CONFIG_440GX */ + if (vec > 31) { + i = vec - 32; + irqa = irq_vecs1; + } +#endif /* CONFIG_440GX */ +#endif /* CONFIG_440 */ + + /* + * print warning when replacing with a different irq vector + */ + if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) { + printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n", + vec, (uint) handler, (uint) irqa[i].handler); + } + irqa[i].handler = handler; + irqa[i].arg = arg; + +#if defined(CONFIG_440) +#if defined(CONFIG_440GX) + if ((vec > 31) && (vec < 64)) + mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); + else if (vec > 63) + mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i)); + else +#endif /* CONFIG_440GX */ + if (vec > 31) + mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); + else +#endif + mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i)); +#if 0 + printf ("Install interrupt for vector %d ==> %p\n", vec, handler); +#endif +} + +void irq_free_handler (int vec) +{ + struct irq_action *irqa = irq_vecs; + int i = vec; + +#if defined(CONFIG_440) +#if defined(CONFIG_440GX) + if ((vec > 31) && (vec < 64)) { + irqa = irq_vecs1; + i = vec - 32; + } else if (vec > 63) { + irqa = irq_vecs2; + i = vec - 64; + } +#endif /* CONFIG_440GX */ + if (vec > 31) { + irqa = irq_vecs1; + i = vec - 32; + } +#endif + +#if 0 + printf ("Free interrupt for vector %d ==> %p\n", + vec, irq_vecs[vec].handler); +#endif + +#if defined(CONFIG_440) +#if defined(CONFIG_440GX) + if ((vec > 31) && (vec < 64)) + mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); + else if (vec > 63) + mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i)); + else +#endif /* CONFIG_440GX */ + if (vec > 31) + mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); + else +#endif + mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i)); + + irqa[i].handler = NULL; + irqa[i].arg = NULL; +} + +/****************************************************************************/ + +void timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} + +/****************************************************************************/ + +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) + +/******************************************************************************* + * + * irqinfo - print information about PCI devices + * + */ +int +do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int vec; + + printf ("\nInterrupt-Information:\n"); +#if defined(CONFIG_440) + printf ("\nUIC 0\n"); +#endif + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<32; vec++) { + if (irq_vecs[vec].handler != NULL) { + printf ("%02d %08lx %08lx %d\n", + vec, + (ulong)irq_vecs[vec].handler, + (ulong)irq_vecs[vec].arg, + irq_vecs[vec].count); + } + } + +#if defined(CONFIG_440) + printf ("\nUIC 1\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<32; vec++) { + if (irq_vecs1[vec].handler != NULL) + printf ("%02d %08lx %08lx %d\n", + vec+31, (ulong)irq_vecs1[vec].handler, + (ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count); + } + printf("\n"); +#endif + +#if defined(CONFIG_440GX) + printf ("\nUIC 2\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<32; vec++) { + if (irq_vecs2[vec].handler != NULL) + printf ("%02d %08lx %08lx %d\n", + vec+63, (ulong)irq_vecs2[vec].handler, + (ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count); + } + printf("\n"); +#endif + + return 0; +} +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S new file mode 100644 index 0000000..be28340 --- /dev/null +++ b/cpu/ppc4xx/kgdb.S @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2000 Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define CONFIG_405GP 1 /* needed for Linux kernel header files */ +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + /* + * cache flushing routines for kgdb + */ + + .globl kgdb_flush_cache_all +kgdb_flush_cache_all: + /* icache */ + iccci r0,r0 /* iccci invalidates the entire I cache */ + /* dcache */ + addi r6,0,0x0000 /* clear GPR 6 */ + addi r7,r0, 128 /* do loop for # of dcache lines */ + /* NOTE: dccci invalidates both */ + mtctr r7 /* ways in the D cache */ +..dcloop: + dccci 0,r6 /* invalidate line */ + addi r6,r6, 32 /* bump to next line */ + bdnz ..dcloop + blr + + .globl kgdb_flush_cache_range +kgdb_flush_cache_range: + li r5,CFG_CACHELINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,CFG_CACHELINE_SHIFT + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,CFG_CACHELINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,CFG_CACHELINE_SIZE + bdnz 2b + SYNC + blr + +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c new file mode 100644 index 0000000..f26f2a2 --- /dev/null +++ b/cpu/ppc4xx/miiphy.c @@ -0,0 +1,260 @@ +/*-----------------------------------------------------------------------------+ + | + | This source code has been made available to you by IBM on an AS-IS + | basis. Anyone receiving this source is licensed under IBM + | copyrights to use it in any way he or she deems fit, including + | copying it, modifying it, compiling it, and redistributing it either + | with or without modifications. No license under IBM patents or + | patent applications is to be implied by the copyright license. + | + | Any user of this software should understand that IBM cannot provide + | technical support for this software and will not be responsible for + | any consequences resulting from the use of this software. + | + | Any person who transfers this source code or any derivative work + | must include the IBM copyright notice, this paragraph, and the + | preceding two paragraphs in the transferred software. + | + | COPYRIGHT I B M CORPORATION 1995 + | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + +-----------------------------------------------------------------------------*/ +/*-----------------------------------------------------------------------------+ + | + | File Name: miiphy.c + | + | Function: This module has utilities for accessing the MII PHY through + | the EMAC3 macro. + | + | Author: Mark Wisner + | + | Change Activity- + | + | Date Description of Change BY + | --------- --------------------- --- + | 05-May-99 Created MKW + | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to + | better match OPB speed. Also modified delay times. JWB + | 29-Jul-99 Added Full duplex support MKW + | 24-Aug-99 Removed printf from dp83843_duplex() JWB + | 19-Jul-00 Ported to esd cpci405 sr + | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS + | + | + +-----------------------------------------------------------------------------*/ + +#include +#include +#include +#include +#include +#include <405_mal.h> +#include + + +/***********************************************************/ +/* Dump out to the screen PHY regs */ +/***********************************************************/ + +void miiphy_dump (char *devname, unsigned char addr) +{ + unsigned long i; + unsigned short data; + + + for (i = 0; i < 0x1A; i++) { + if (miiphy_read (devname, addr, i, &data)) { + printf ("read error for reg %lx\n", i); + return; + } + printf ("Phy reg %lx ==> %4x\n", i, data); + + /* jump to the next set of regs */ + if (i == 0x07) + i = 0x0f; + + } /* end for loop */ +} /* end dump */ + + +/***********************************************************/ +/* (Re)start autonegotiation */ +/***********************************************************/ +int phy_setup_aneg (char *devname, unsigned char addr) +{ + unsigned short ctl, adv; + + /* Setup standard advertise */ + miiphy_read (devname, addr, PHY_ANAR, &adv); + adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | + PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | + PHY_ANLPAR_10); + miiphy_write (devname, addr, PHY_ANAR, adv); + + /* Start/Restart aneg */ + miiphy_read (devname, addr, PHY_BMCR, &ctl); + ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write (devname, addr, PHY_BMCR, ctl); + + return 0; +} + + +/***********************************************************/ +/* read a phy reg and return the value with a rc */ +/***********************************************************/ +unsigned int miiphy_getemac_offset (void) +{ +#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI) + unsigned long zmii; + unsigned long eoffset; + + /* Need to find out which mdi port we're using */ + zmii = in32 (ZMII_FER); + + if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) { + /* using port 0 */ + eoffset = 0; + } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) { + /* using port 1 */ + eoffset = 0x100; + } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) { + /* using port 2 */ + eoffset = 0x400; + } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) { + /* using port 3 */ + eoffset = 0x600; + } else { + /* None of the mdi ports are enabled! */ + /* enable port 0 */ + zmii |= ZMII_FER_MDI << ZMII_FER_V (0); + out32 (ZMII_FER, zmii); + eoffset = 0; + /* need to soft reset port 0 */ + zmii = in32 (EMAC_M0); + zmii |= EMAC_M0_SRST; + out32 (EMAC_M0, zmii); + } + + return (eoffset); +#else + return 0; +#endif +} + + +int emac4xx_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + unsigned long sta_reg; /* STA scratch area */ + unsigned long i; + unsigned long emac_reg; + + + emac_reg = miiphy_getemac_offset (); + /* see if it is ready for 1000 nsec */ + i = 0; + + /* see if it is ready for sec */ + while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { + udelay (7); + if (i > 5) { +#if 0 + printf ("read err 1\n"); +#endif + return -1; + } + i++; + } + sta_reg = reg; /* reg address */ + /* set clock (50Mhz) and read flags */ +#if defined(CONFIG_440GX) + sta_reg |= EMAC_STACR_READ; +#else + sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; +#endif + +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) + sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; +#endif + sta_reg = sta_reg | (addr << 5); /* Phy address */ + + out32 (EMAC_STACR + emac_reg, sta_reg); +#if 0 /* test-only */ + printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif + + sta_reg = in32 (EMAC_STACR + emac_reg); + i = 0; + while ((sta_reg & EMAC_STACR_OC) == 0) { + udelay (7); + if (i > 5) { + return -1; + } + i++; + sta_reg = in32 (EMAC_STACR + emac_reg); + } + if ((sta_reg & EMAC_STACR_PHYE) != 0) { + return -1; + } + + *value = *(short *) (&sta_reg); + return 0; + + +} /* phy_read */ + + +/***********************************************************/ +/* write a phy reg and return the value with a rc */ +/***********************************************************/ + +int emac4xx_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + unsigned long sta_reg; /* STA scratch area */ + unsigned long i; + unsigned long emac_reg; + + emac_reg = miiphy_getemac_offset (); + /* see if it is ready for 1000 nsec */ + i = 0; + + while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { + if (i > 5) + return -1; + udelay (7); + i++; + } + sta_reg = 0; + sta_reg = reg; /* reg address */ + /* set clock (50Mhz) and read flags */ +#if defined(CONFIG_440GX) + sta_reg |= EMAC_STACR_WRITE; +#else + sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; +#endif + +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) + sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ +#endif + sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */ + memcpy (&sta_reg, &value, 2); /* put in data */ + + out32 (EMAC_STACR + emac_reg, sta_reg); + + /* wait for completion */ + i = 0; + sta_reg = in32 (EMAC_STACR + emac_reg); + while ((sta_reg & EMAC_STACR_OC) == 0) { + udelay (7); + if (i > 5) + return -1; + i++; + sta_reg = in32 (EMAC_STACR + emac_reg); + } + + if ((sta_reg & EMAC_STACR_PHYE) != 0) + return -1; + return 0; + +} /* phy_write */ diff --git a/cpu/ppc4xx/resetvec.S b/cpu/ppc4xx/resetvec.S new file mode 100644 index 0000000..b3308bd --- /dev/null +++ b/cpu/ppc4xx/resetvec.S @@ -0,0 +1,12 @@ +/* Copyright MontaVista Software Incorporated, 2000 */ +#include + .section .resetvec,"ax" +#if defined(CONFIG_440) + b _start_440 +#else +#if defined(CONFIG_BOOT_PCI) && defined(CONFIG_MIP405) + b _start_pci +#else + b _start +#endif +#endif diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c new file mode 100644 index 0000000..e9548cd --- /dev/null +++ b/cpu/ppc4xx/sdram.c @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2002-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + + +#ifdef CONFIG_SDRAM_BANK0 + + +#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) + + +struct sdram_conf_s { + unsigned long size; + unsigned long reg; +}; + +typedef struct sdram_conf_s sdram_conf_t; + +#ifndef CFG_SDRAM_TABLE +sdram_conf_t mb0cf[] = { + {(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */ + {(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */ + {(32 << 20), 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */ + {(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */ + {(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */ +}; +#else +sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; +#endif + +#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) + + +#ifndef CONFIG_440 + +/* + * Autodetect onboard SDRAM on 405 platforms + */ +void sdram_init(void) +{ + ulong sdtr1; + ulong rtr; + int i; + + /* + * Support for 100MHz and 133MHz SDRAM + */ + if (get_bus_freq(0) > 100000000) { + /* + * 133 MHz SDRAM + */ + sdtr1 = 0x01074015; + rtr = 0x07f00000; + } else { + /* + * default: 100 MHz SDRAM + */ + sdtr1 = 0x0086400d; + rtr = 0x05f00000; + } + + for (i=0; i all done + */ + return; + } + } +} + +#else /* CONFIG_440 */ + +/* + * Autodetect onboard DDR SDRAM on 440 platforms + * + * NOTE: Some of the hardcoded values are hardware dependant, + * so this should be extended for other future boards + * using this routine! + */ +long int initdram(int board_type) +{ + int i; + + for (i=0; i all done + */ + return mb0cf[i].size; + } + } + + return 0; /* nothing found ! */ +} + +#endif /* CONFIG_440 */ + +#endif /* CONFIG_SDRAM_BANK0 */ diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c new file mode 100644 index 0000000..e7f6bcb --- /dev/null +++ b/cpu/ppc4xx/serial.c @@ -0,0 +1,1064 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/*------------------------------------------------------------------------------+ */ +/* + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + */ +/*------------------------------------------------------------------------------- */ +/* + * Travis Sawyer 15 September 2004 + * Added CONFIG_SERIAL_MULTI support + */ +#include +#include +#include +#include +#include "vecnum.h" + +#ifdef CONFIG_SERIAL_MULTI +#include +#endif + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO +#include +#endif + +/*****************************************************************************/ +#ifdef CONFIG_IOP480 + +#define SPU_BASE 0x40000000 + +#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */ +#define spu_LineStat_w 0x04 /* Line Status Register (Set) */ +#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */ +#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */ +#define spu_BRateDivh 0x10 /* Baud rate divisor high */ +#define spu_BRateDivl 0x14 /* Baud rate divisor low */ +#define spu_CtlReg 0x18 /* Control Register */ +#define spu_RxCmd 0x1c /* Rx Command Register */ +#define spu_TxCmd 0x20 /* Tx Command Register */ +#define spu_RxBuff 0x24 /* Rx data buffer */ +#define spu_TxBuff 0x24 /* Tx data buffer */ + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncLSRport1 0x40000000 +#define asyncLSRport1set 0x40000004 +#define asyncLSRDataReady 0x80 +#define asyncLSRFramingError 0x40 +#define asyncLSROverrunError 0x20 +#define asyncLSRParityError 0x10 +#define asyncLSRBreakInterrupt 0x08 +#define asyncLSRTxHoldEmpty 0x04 +#define asyncLSRTxShiftEmpty 0x02 + +/*-----------------------------------------------------------------------------+ + | Handshake Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncHSRport1 0x40000008 +#define asyncHSRport1set 0x4000000c +#define asyncHSRDsr 0x80 +#define asyncLSRCts 0x40 + +/*-----------------------------------------------------------------------------+ + | Control Register. + +-----------------------------------------------------------------------------*/ +#define asyncCRport1 0x40000018 +#define asyncCRNormal 0x00 +#define asyncCRLoopback 0x40 +#define asyncCRAutoEcho 0x80 +#define asyncCRDtr 0x20 +#define asyncCRRts 0x10 +#define asyncCRWordLength7 0x00 +#define asyncCRWordLength8 0x08 +#define asyncCRParityDisable 0x00 +#define asyncCRParityEnable 0x04 +#define asyncCREvenParity 0x00 +#define asyncCROddParity 0x02 +#define asyncCRStopBitsOne 0x00 +#define asyncCRStopBitsTwo 0x01 +#define asyncCRDisableDtrRts 0x00 + +/*-----------------------------------------------------------------------------+ + | Receiver Command Register. + +-----------------------------------------------------------------------------*/ +#define asyncRCRport1 0x4000001c +#define asyncRCRDisable 0x00 +#define asyncRCREnable 0x80 +#define asyncRCRIntDisable 0x00 +#define asyncRCRIntEnabled 0x20 +#define asyncRCRDMACh2 0x40 +#define asyncRCRDMACh3 0x60 +#define asyncRCRErrorInt 0x10 +#define asyncRCRPauseEnable 0x08 + +/*-----------------------------------------------------------------------------+ + | Transmitter Command Register. + +-----------------------------------------------------------------------------*/ +#define asyncTCRport1 0x40000020 +#define asyncTCRDisable 0x00 +#define asyncTCREnable 0x80 +#define asyncTCRIntDisable 0x00 +#define asyncTCRIntEnabled 0x20 +#define asyncTCRDMACh2 0x40 +#define asyncTCRDMACh3 0x60 +#define asyncTCRTxEmpty 0x10 +#define asyncTCRErrorInt 0x08 +#define asyncTCRStopPause 0x04 +#define asyncTCRBreakGen 0x02 + +/*-----------------------------------------------------------------------------+ + | Miscellanies defines. + +-----------------------------------------------------------------------------*/ +#define asyncTxBufferport1 0x40000024 +#define asyncRxBufferport1 0x40000024 +#define asyncDLABLsbport1 0x40000014 +#define asyncDLABMsbport1 0x40000010 +#define asyncXOFFchar 0x13 +#define asyncXONchar 0x11 + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile char val; + unsigned short br_reg; + + br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); + + /* + * Init onboard UART + */ + out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */ + out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ + out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ + out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */ + out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ + out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ + out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ + + return (0); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned short br_reg; + + br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); + + out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ + out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ +} + +void serial_putc (const char c) +{ + if (c == '\n') + serial_putc ('\r'); + + /* load status from handshake register */ + if (in8 (SPU_BASE + spu_Handshk_rc) != 00) + out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + + out8 (SPU_BASE + spu_TxBuff, c); /* Put char */ + + while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) { + if (in8 (SPU_BASE + spu_Handshk_rc) != 00) + out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + } +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc () +{ + unsigned char status = 0; + + while (1) { + status = in8 (asyncLSRport1); + if ((status & asyncLSRDataReady) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt )) != 0) { + (void) out8 (asyncLSRport1, + asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt ); + } + } + return (0x000000ff & (int) in8 (asyncRxBufferport1)); +} + +int serial_tstc () +{ + unsigned char status; + + status = in8 (asyncLSRport1); + if ((status & asyncLSRDataReady) != 0x0) { + return (1); + } + if ((status & ( asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt )) != 0) { + (void) out8 (asyncLSRport1, + asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt); + } + return 0; +} + +#endif /* CONFIG_IOP480 */ + +/*****************************************************************************/ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP) + +#if defined(CONFIG_440) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 +#else +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#endif + +#if defined(CONFIG_440SP) +#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#define CR0_MASK 0xdfffffff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#else +#define CR0_MASK 0x3fff0000 +#define CR0_EXTCLK_ENA 0x00600000 +#define CR0_UDIV_POS 16 +#endif /* CONFIG_440GX */ +#elif defined(CONFIG_405EP) +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define UCR0_MASK 0x0000007f +#define UCR1_MASK 0x00007f00 +#define UCR0_UDIV_POS 0 +#define UCR1_UDIV_POS 8 +#define UDIV_MAX 127 +#else /* CONFIG_405GP || CONFIG_405CR */ +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define CR0_MASK 0x00001fff +#define CR0_EXTCLK_ENA 0x000000c0 +#define CR0_UDIV_POS 1 +#define UDIV_MAX 32 +#endif + +/* using serial port 0 or 1 as U-Boot console ? */ +#if defined(CONFIG_UART1_CONSOLE) +#define ACTING_UART0_BASE UART1_BASE +#define ACTING_UART1_BASE UART0_BASE +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#define UART0_SDR sdr_uart1 +#define UART1_SDR sdr_uart0 +#endif /* CONFIG_440GX */ +#else +#define ACTING_UART0_BASE UART0_BASE +#define ACTING_UART1_BASE UART1_BASE +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#endif /* CONFIG_440GX */ +#endif + +#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) +#error "External serial clock not supported on AMCC PPC405EP!" +#endif + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */ +#define asyncLSRDataReady1 0x01 +#define asyncLSROverrunError1 0x02 +#define asyncLSRParityError1 0x04 +#define asyncLSRFramingError1 0x08 +#define asyncLSRBreakInterrupt1 0x10 +#define asyncLSRTxHoldEmpty1 0x20 +#define asyncLSRTxShiftEmpty1 0x40 +#define asyncLSRRxFifoError1 0x80 + +/*-----------------------------------------------------------------------------+ + | Miscellanies defines. + +-----------------------------------------------------------------------------*/ +/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ +/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO +/*-----------------------------------------------------------------------------+ + | Fifo + +-----------------------------------------------------------------------------*/ +typedef struct { + char *rx_buffer; + ulong rx_put; + ulong rx_get; +} serial_buffer_t; + +volatile static serial_buffer_t buf_info; +#endif + +#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv ) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + + get_sys_info( &sysinfo ); + + udiv = 32; /* Assume lowest possible serial clk */ + div = sysinfo.freqPLB/(16*baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */ + diff = 32; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (32) to minimize serial clock and constrain + * search to umin. + */ + for( i = 32; i > umin; i-- ){ + ibdiv = div/i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if( idiff == 0 ){ + udiv = i; + break; /* can't do better */ + } + else if( idiff < diff ){ + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + *pbdiv = div/udiv; + +} +#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */ + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +#if defined(CONFIG_440) +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else +int serial_init(void) +#endif +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long reg; + unsigned long udiv; + unsigned short bdiv; + volatile char val; +#ifdef CFG_EXT_SERIAL_CLOCK + unsigned long tmp; +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mfsdr(UART0_SDR,reg); + reg &= ~CR0_MASK; + } else { + mfsdr(UART1_SDR,reg); + reg &= ~CR0_MASK; + } +#else + mfsdr(UART0_SDR,reg); + reg &= ~CR0_MASK; +#endif +#else + reg = mfdcr(cntrl0) & ~CR0_MASK; +#endif /* CONFIG_440GX */ +#ifdef CFG_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + tmp = gd->baudrate * 16; + bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; +#else + /* For 440, the cpu clock is on divider chain A, UART on divider + * chain B ... so cpu clock is irrelevant. Get the "optimized" + * values that are subject to the 1/2 opb clock constraint + */ + serial_divs (gd->baudrate, &udiv, &bdiv); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) + reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */ +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mtsdr (UART0_SDR,reg); + } else { + mtsdr (UART1_SDR,reg); + } +#else + mtsdr (UART0_SDR,reg); +#endif +#else + reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ + mtdcr (cntrl0, reg); +#endif + +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ + out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (dev_base + UART_LSR); /* clear line status */ + val = in8 (dev_base + UART_RBR); /* read receive buffer */ + out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ + out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ +#else + out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#endif + return (0); +} + +#else /* !defined(CONFIG_440) */ + +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else +int serial_init (void) +#endif +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long reg; + unsigned long tmp; + unsigned long clk; + unsigned long udiv; + unsigned short bdiv; + volatile char val; + +#ifdef CONFIG_405EP + reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + clk = gd->cpu_clk; + tmp = CFG_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; + reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ + reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ + mtdcr (cpc0_ucr, reg); +#else /* CONFIG_405EP */ + reg = mfdcr(cntrl0) & ~CR0_MASK; +#ifdef CFG_EXT_SERIAL_CLOCK + clk = CFG_EXT_SERIAL_CLOCK; + udiv = 1; + reg |= CR0_EXTCLK_ENA; +#else + clk = gd->cpu_clk; +#ifdef CFG_405_UART_ERRATA_59 + udiv = 31; /* Errata 59: stuck at 31 */ +#else + tmp = CFG_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; +#endif +#endif + reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ + mtdcr (cntrl0, reg); +#endif /* CONFIG_405EP */ + + tmp = gd->baudrate * udiv * 16; + bdiv = (clk + tmp / 2) / tmp; + +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ + out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (dev_base + UART_LSR); /* clear line status */ + val = in8 (dev_base + UART_RBR); /* read receive buffer */ + out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ + out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ +#else + out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#endif + return (0); +} + +#endif /* if defined(CONFIG_440) */ + +#if defined(CONFIG_SERIAL_MULTI) +void serial_setbrg_dev (unsigned long dev_base) +#else +void serial_setbrg (void) +#endif +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned long tmp; + unsigned long clk; + unsigned long udiv; + unsigned short bdiv; + +#ifdef CFG_EXT_SERIAL_CLOCK + clk = CFG_EXT_SERIAL_CLOCK; +#else + clk = gd->cpu_clk; +#endif + +#ifdef CONFIG_405EP + udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS); +#else + udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1; +#endif /* CONFIG_405EP */ + tmp = gd->baudrate * udiv * 16; + bdiv = (clk + tmp / 2) / tmp; + +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ +#else + out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ +#endif +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_putc_dev (unsigned long dev_base, const char c) +#else +void serial_putc (const char c) +#endif +{ + int i; + + if (c == '\n') +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, '\r'); +#else + serial_putc ('\r'); +#endif + + /* check THRE bit, wait for transmiter available */ + for (i = 1; i < 3500; i++) { +#if defined(CONFIG_SERIAL_MULTI) + if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20) +#else + if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20) +#endif + break; + udelay (100); + } +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_THR, c); /* put character out */ +#else + out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */ +#endif +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_puts_dev (unsigned long dev_base, const char *s) +#else +void serial_puts (const char *s) +#endif +{ + while (*s) { +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, *s++); +#else + serial_putc (*s++); +#endif + } +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_getc_dev (unsigned long dev_base) +#else +int serial_getc (void) +#endif +{ + unsigned char status = 0; + + while (1) { +#if defined(CONFIG_HW_WATCHDOG) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ +#endif /* CONFIG_HW_WATCHDOG */ +#if defined(CONFIG_SERIAL_MULTI) + status = in8 (dev_base + UART_LSR); +#else + status = in8 (ACTING_UART0_BASE + UART_LSR); +#endif + if ((status & asyncLSRDataReady1) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LSR, +#else + out8 (ACTING_UART0_BASE + UART_LSR, +#endif + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + } +#if defined(CONFIG_SERIAL_MULTI) + return (0x000000ff & (int) in8 (dev_base)); +#else + return (0x000000ff & (int) in8 (ACTING_UART0_BASE)); +#endif +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_tstc_dev (unsigned long dev_base) +#else +int serial_tstc (void) +#endif +{ + unsigned char status; + +#if defined(CONFIG_SERIAL_MULTI) + status = in8 (dev_base + UART_LSR); +#else + status = in8 (ACTING_UART0_BASE + UART_LSR); +#endif + if ((status & asyncLSRDataReady1) != 0x0) { + return (1); + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LSR, +#else + out8 (ACTING_UART0_BASE + UART_LSR, +#endif + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + return 0; +} + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + +void serial_isr (void *arg) +{ + int space; + int c; + const int rx_get = buf_info.rx_get; + int rx_put = buf_info.rx_put; + + if (rx_get <= rx_put) { + space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); + } else { + space = rx_get - rx_put; + } + while (serial_tstc_dev (ACTING_UART0_BASE)) { + c = serial_getc_dev (ACTING_UART0_BASE); + if (space) { + buf_info.rx_buffer[rx_put++] = c; + space--; + } + if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) + rx_put = 0; + if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { + /* Stop flow by setting RTS inactive */ + out8 (ACTING_UART0_BASE + UART_MCR, + in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); + } + } + buf_info.rx_put = rx_put; +} + +void serial_buffered_init (void) +{ + serial_puts ("Switching to interrupt driven serial input mode.\n"); + buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); + buf_info.rx_put = 0; + buf_info.rx_get = 0; + + if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) { + serial_puts ("Check CTS signal present on serial port: OK.\n"); + } else { + serial_puts ("WARNING: CTS signal not present on serial port.\n"); + } + + irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , + serial_isr /*interrupt_handler_t *handler */ , + (void *) &buf_info /*void *arg */ ); + + /* Enable "RX Data Available" Interrupt on UART */ + /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */ + out8 (ACTING_UART0_BASE + UART_IER, 0x01); + /* Set DTR active */ + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01); + /* Start flow by setting RTS active */ + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ + out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); +} + +void serial_buffered_putc (const char c) +{ + /* Wait for CTS */ +#if defined(CONFIG_HW_WATCHDOG) + while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) + WATCHDOG_RESET (); +#else + while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); +#endif + serial_putc (c); +} + +void serial_buffered_puts (const char *s) +{ + serial_puts (s); +} + +int serial_buffered_getc (void) +{ + int space; + int c; + int rx_get = buf_info.rx_get; + int rx_put; + +#if defined(CONFIG_HW_WATCHDOG) + while (rx_get == buf_info.rx_put) + WATCHDOG_RESET (); +#else + while (rx_get == buf_info.rx_put); +#endif + c = buf_info.rx_buffer[rx_get++]; + if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) + rx_get = 0; + buf_info.rx_get = rx_get; + + rx_put = buf_info.rx_put; + if (rx_get <= rx_put) { + space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); + } else { + space = rx_get - rx_put; + } + if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { + /* Start flow by setting RTS active */ + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + } + + return c; +} + +int serial_buffered_tstc (void) +{ + return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; +} + +#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +/* + AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port + number 0 or number 1 + - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : + configuration has been already done + - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : + configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE +*/ +#if (CONFIG_KGDB_SER_INDEX & 2) +void kgdb_serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile char val; + unsigned short br_reg; + + get_clocks (); + br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + + 5) / 10; + /* + * Init onboard 16550 UART + */ + out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ + out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ + out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ + out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +} + +void putDebugChar (const char c) +{ + if (c == '\n') + serial_putc ('\r'); + + out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */ + + /* check THRE bit, wait for transfer done */ + while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); +} + +void putDebugStr (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int getDebugChar (void) +{ + unsigned char status = 0; + + while (1) { + status = in8 (ACTING_UART1_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + out8 (ACTING_UART1_BASE + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + } + return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); +} + +void kgdb_interruptible (int yes) +{ + return; +} + +#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ + +void kgdb_serial_init (void) +{ + serial_printf ("[on serial] "); +} + +void putDebugChar (int c) +{ + serial_putc (c); +} + +void putDebugStr (const char *str) +{ + serial_puts (str); +} + +int getDebugChar (void) +{ + return serial_getc (); +} + +void kgdb_interruptible (int yes) +{ + return; +} +#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ +#endif /* CFG_CMD_KGDB */ + + +#if defined(CONFIG_SERIAL_MULTI) +int serial0_init(void) +{ + return (serial_init_dev(UART0_BASE)); +} + +int serial1_init(void) +{ + return (serial_init_dev(UART1_BASE)); +} +void serial0_setbrg (void) +{ + serial_setbrg_dev(UART0_BASE); +} +void serial1_setbrg (void) +{ + serial_setbrg_dev(UART1_BASE); +} + +void serial0_putc(const char c) +{ + serial_putc_dev(UART0_BASE,c); +} + +void serial1_putc(const char c) +{ + serial_putc_dev(UART1_BASE, c); +} +void serial0_puts(const char *s) +{ + serial_puts_dev(UART0_BASE, s); +} + +void serial1_puts(const char *s) +{ + serial_puts_dev(UART1_BASE, s); +} + +int serial0_getc(void) +{ + return(serial_getc_dev(UART0_BASE)); +} + +int serial1_getc(void) +{ + return(serial_getc_dev(UART1_BASE)); +} +int serial0_tstc(void) +{ + return (serial_tstc_dev(UART0_BASE)); +} + +int serial1_tstc(void) +{ + return (serial_tstc_dev(UART1_BASE)); +} + +struct serial_device serial0_device = +{ + "serial0", + "UART0", + serial0_init, + serial0_setbrg, + serial0_getc, + serial0_tstc, + serial0_putc, + serial0_puts, +}; + +struct serial_device serial1_device = +{ + "serial1", + "UART1", + serial1_init, + serial1_setbrg, + serial1_getc, + serial1_tstc, + serial1_putc, + serial1_puts, +}; +#endif /* CONFIG_SERIAL_MULTI */ + +#endif /* CONFIG_405GP || CONFIG_405CR */ diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c new file mode 100644 index 0000000..ebd5f39 --- /dev/null +++ b/cpu/ppc4xx/spd_sdram.c @@ -0,0 +1,1831 @@ +/* + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com + * + * Based on code by: + * + * Kenneth Johansson ,Ericsson AB. + * kenneth.johansson@etx.ericsson.se + * + * hacked up by bill hunter. fixed so we could run before + * serial_init and console_init. previous version avoided this by + * running out of cache memory during serial/console init, then running + * this code later. + * + * (C) Copyright 2002 + * Jun Gu, Artesyn Technology, jung@artesyncp.com + * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CONFIG_SPD_EEPROM + +/* + * Set default values + */ +#ifndef CFG_I2C_SPEED +#define CFG_I2C_SPEED 50000 +#endif + +#ifndef CFG_I2C_SLAVE +#define CFG_I2C_SLAVE 0xFE +#endif + +#define ONE_BILLION 1000000000 + +#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */ + +#define SDRAM0_CFG_DCE 0x80000000 +#define SDRAM0_CFG_SRE 0x40000000 +#define SDRAM0_CFG_PME 0x20000000 +#define SDRAM0_CFG_MEMCHK 0x10000000 +#define SDRAM0_CFG_REGEN 0x08000000 +#define SDRAM0_CFG_ECCDD 0x00400000 +#define SDRAM0_CFG_EMDULR 0x00200000 +#define SDRAM0_CFG_DRW_SHIFT (31-6) +#define SDRAM0_CFG_BRPF_SHIFT (31-8) + +#define SDRAM0_TR_CASL_SHIFT (31-8) +#define SDRAM0_TR_PTA_SHIFT (31-13) +#define SDRAM0_TR_CTP_SHIFT (31-15) +#define SDRAM0_TR_LDF_SHIFT (31-17) +#define SDRAM0_TR_RFTA_SHIFT (31-29) +#define SDRAM0_TR_RCD_SHIFT (31-31) + +#define SDRAM0_RTR_SHIFT (31-15) +#define SDRAM0_ECCCFG_SHIFT (31-11) + +/* SDRAM0_CFG enable macro */ +#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT ) + +#define SDRAM0_BXCR_SZ_MASK 0x000e0000 +#define SDRAM0_BXCR_AM_MASK 0x0000e000 + +#define SDRAM0_BXCR_SZ_SHIFT (31-14) +#define SDRAM0_BXCR_AM_SHIFT (31-18) + +#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) ) +#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) ) + +#ifdef CONFIG_SPDDRAM_SILENT +# define SPD_ERR(x) do { return 0; } while (0) +#else +# define SPD_ERR(x) do { printf(x); return(0); } while (0) +#endif + +#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) + +/* function prototypes */ +int spd_read(uint addr); + + +/* + * This function is reading data from the DIMM module EEPROM over the SPD bus + * and uses that to program the sdram controller. + * + * This works on boards that has the same schematics that the AMCC walnut has. + * + * Input: null for default I2C spd functions or a pointer to a custom function + * returning spd_data. + */ + +long int spd_sdram(int(read_spd)(uint addr)) +{ + int tmp,row,col; + int total_size,bank_size,bank_code; + int ecc_on; + int mode; + int bank_cnt; + + int sdram0_pmit=0x07c00000; +#ifndef CONFIG_405EP /* not on PPC405EP */ + int sdram0_besr0=-1; + int sdram0_besr1=-1; + int sdram0_eccesr=-1; +#endif + int sdram0_ecccfg; + + int sdram0_rtr=0; + int sdram0_tr=0; + + int sdram0_b0cr; + int sdram0_b1cr; + int sdram0_b2cr; + int sdram0_b3cr; + + int sdram0_cfg=0; + + int t_rp; + int t_rcd; + int t_ras; + int t_rc; + int min_cas; + + PPC405_SYS_INFO sys_info; + unsigned long bus_period_x_10; + + /* + * get the board info + */ + get_sys_info(&sys_info); + bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); + + if (read_spd == 0){ + read_spd=spd_read; + /* + * Make sure I2C controller is initialized + * before continuing. + */ + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + } + + /* Make shure we are using SDRAM */ + if (read_spd(2) != 0x04) { + SPD_ERR("SDRAM - non SDRAM memory module found\n"); + } + + /* ------------------------------------------------------------------ + * configure memory timing register + * + * data from DIMM: + * 27 IN Row Precharge Time ( t RP) + * 29 MIN RAS to CAS Delay ( t RCD) + * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS + * -------------------------------------------------------------------*/ + + /* + * first figure out which cas latency mode to use + * use the min supported mode + */ + + tmp = read_spd(127) & 0x6; + if (tmp == 0x02) { /* only cas = 2 supported */ + min_cas = 2; +/* t_ck = read_spd(9); */ +/* t_ac = read_spd(10); */ + } else if (tmp == 0x04) { /* only cas = 3 supported */ + min_cas = 3; +/* t_ck = read_spd(9); */ +/* t_ac = read_spd(10); */ + } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ + min_cas = 2; +/* t_ck = read_spd(23); */ +/* t_ac = read_spd(24); */ + } else { + SPD_ERR("SDRAM - unsupported CAS latency \n"); + } + + /* get some timing values, t_rp,t_rcd,t_ras,t_rc + */ + t_rp = read_spd(27); + t_rcd = read_spd(29); + t_ras = read_spd(30); + t_rc = t_ras + t_rp; + + /* The following timing calcs subtract 1 before deviding. + * this has effect of using ceiling instead of floor rounding, + * and also subtracting 1 to convert number to reg value + */ + /* set up CASL */ + sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT; + /* set up PTA */ + sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT; + /* set up CTP */ + tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3; + if (tmp < 1) + tmp = 1; + sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT; + /* set LDF = 2 cycles, reg value = 1 */ + sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT; + /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */ + tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3; + if (tmp < 0) + tmp = 0; + if (tmp > 6) + tmp = 6; + sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT; + /* set RCD = t_rcd/bus_period*/ + sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ; + + + /*------------------------------------------------------------------ + * configure RTR register + * -------------------------------------------------------------------*/ + row = read_spd(3); + col = read_spd(4); + tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */ + switch (tmp) { + case 0x00: + tmp = 15625; + break; + case 0x01: + tmp = 15625 / 4; + break; + case 0x02: + tmp = 15625 / 2; + break; + case 0x03: + tmp = 15625 * 2; + break; + case 0x04: + tmp = 15625 * 4; + break; + case 0x05: + tmp = 15625 * 8; + break; + default: + SPD_ERR("SDRAM - Bad refresh period \n"); + } + /* convert from nsec to bus cycles */ + tmp = (tmp * 10) / bus_period_x_10; + sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; + + /*------------------------------------------------------------------ + * determine the number of banks used + * -------------------------------------------------------------------*/ + /* byte 7:6 is module data width */ + if (read_spd(7) != 0) + SPD_ERR("SDRAM - unsupported module width\n"); + tmp = read_spd(6); + if (tmp < 32) + SPD_ERR("SDRAM - unsupported module width\n"); + else if (tmp < 64) + bank_cnt = 1; /* one bank per sdram side */ + else if (tmp < 73) + bank_cnt = 2; /* need two banks per side */ + else if (tmp < 161) + bank_cnt = 4; /* need four banks per side */ + else + SPD_ERR("SDRAM - unsupported module width\n"); + + /* byte 5 is the module row count (refered to as dimm "sides") */ + tmp = read_spd(5); + if (tmp == 1) + ; + else if (tmp==2) + bank_cnt *= 2; + else if (tmp==4) + bank_cnt *= 4; + else + bank_cnt = 8; /* 8 is an error code */ + + if (bank_cnt > 4) /* we only have 4 banks to work with */ + SPD_ERR("SDRAM - unsupported module rows for this width\n"); + + /* now check for ECC ability of module. We only support ECC + * on 32 bit wide devices with 8 bit ECC. + */ + if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) { + sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT; + ecc_on = 1; + } else { + sdram0_ecccfg = 0; + ecc_on = 0; + } + + /*------------------------------------------------------------------ + * calculate total size + * -------------------------------------------------------------------*/ + /* calculate total size and do sanity check */ + tmp = read_spd(31); + total_size = 1 << 22; /* total_size = 4MB */ + /* now multiply 4M by the smallest device row density */ + /* note that we don't support asymetric rows */ + while (((tmp & 0x0001) == 0) && (tmp != 0)) { + total_size = total_size << 1; + tmp = tmp >> 1; + } + total_size *= read_spd(5); /* mult by module rows (dimm sides) */ + + /*------------------------------------------------------------------ + * map rows * cols * banks to a mode + * -------------------------------------------------------------------*/ + + switch (row) { + case 11: + switch (col) { + case 8: + mode=4; /* mode 5 */ + break; + case 9: + case 10: + mode=0; /* mode 1 */ + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + break; + case 12: + switch (col) { + case 8: + mode=3; /* mode 4 */ + break; + case 9: + case 10: + mode=1; /* mode 2 */ + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + break; + case 13: + switch (col) { + case 8: + mode=5; /* mode 6 */ + break; + case 9: + case 10: + if (read_spd(17) == 2) + mode = 6; /* mode 7 */ + else + mode = 2; /* mode 3 */ + break; + case 11: + mode = 2; /* mode 3 */ + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + + /*------------------------------------------------------------------ + * using the calculated values, compute the bank + * config register values. + * -------------------------------------------------------------------*/ + sdram0_b1cr = 0; + sdram0_b2cr = 0; + sdram0_b3cr = 0; + + /* compute the size of each bank */ + bank_size = total_size / bank_cnt; + /* convert bank size to bank size code for ppc4xx + by takeing log2(bank_size) - 22 */ + tmp = bank_size; /* start with tmp = bank_size */ + bank_code = 0; /* and bank_code = 0 */ + while (tmp > 1) { /* this takes log2 of tmp */ + bank_code++; /* and stores result in bank_code */ + tmp = tmp >> 1; + } /* bank_code is now log2(bank_size) */ + bank_code -= 22; /* subtract 22 to get the code */ + + tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1; + sdram0_b0cr = (bank_size * 0) | tmp; +#ifndef CONFIG_405EP /* not on PPC405EP */ + if (bank_cnt > 1) + sdram0_b2cr = (bank_size * 1) | tmp; + if (bank_cnt > 2) + sdram0_b1cr = (bank_size * 2) | tmp; + if (bank_cnt > 3) + sdram0_b3cr = (bank_size * 3) | tmp; +#else + /* PPC405EP chip only supports two SDRAM banks */ + if (bank_cnt > 1) + sdram0_b1cr = (bank_size * 1) | tmp; + if (bank_cnt > 2) + total_size = 2 * bank_size; +#endif + + /* + * enable sdram controller DCE=1 + * enable burst read prefetch to 32 bytes BRPF=2 + * leave other functions off + */ + + /*------------------------------------------------------------------ + * now that we've done our calculations, we are ready to + * program all the registers. + * -------------------------------------------------------------------*/ + +#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) + /* disable memcontroller so updates work */ + mtsdram0( mem_mcopt1, 0 ); + +#ifndef CONFIG_405EP /* not on PPC405EP */ + mtsdram0( mem_besra , sdram0_besr0 ); + mtsdram0( mem_besrb , sdram0_besr1 ); + mtsdram0( mem_ecccf , sdram0_ecccfg ); + mtsdram0( mem_eccerr, sdram0_eccesr ); +#endif + mtsdram0( mem_rtr , sdram0_rtr ); + mtsdram0( mem_pmit , sdram0_pmit ); + mtsdram0( mem_mb0cf , sdram0_b0cr ); + mtsdram0( mem_mb1cf , sdram0_b1cr ); +#ifndef CONFIG_405EP /* not on PPC405EP */ + mtsdram0( mem_mb2cf , sdram0_b2cr ); + mtsdram0( mem_mb3cf , sdram0_b3cr ); +#endif + mtsdram0( mem_sdtr1 , sdram0_tr ); + + /* SDRAM have a power on delay, 500 micro should do */ + udelay(500); + sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; + if (ecc_on) + sdram0_cfg |= SDRAM0_CFG_MEMCHK; + mtsdram0(mem_mcopt1, sdram0_cfg); + + return (total_size); +} + +int spd_read(uint addr) +{ + uchar data[2]; + + if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0) + return (int)data[0]; + else + return 0; +} + +#else /* CONFIG_440 */ + +/*----------------------------------------------------------------------------- + | Memory Controller Options 0 + +-----------------------------------------------------------------------------*/ +#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ +#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ +#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ +#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ +#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ +#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ +#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ +#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ +#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ +#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ + +/*----------------------------------------------------------------------------- + | Memory Controller Options 1 + +-----------------------------------------------------------------------------*/ +#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ +#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ + +/*-----------------------------------------------------------------------------+ + | SDRAM DEVPOT Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_DEVOPT_DLL 0x80000000 +#define SDRAM_DEVOPT_DS 0x40000000 + +/*-----------------------------------------------------------------------------+ + | SDRAM MCSTS Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_MCSTS_MRSC 0x80000000 +#define SDRAM_MCSTS_SRMS 0x40000000 +#define SDRAM_MCSTS_CIS 0x20000000 + +/*----------------------------------------------------------------------------- + | SDRAM Refresh Timer Register + +-----------------------------------------------------------------------------*/ +#define SDRAM_RTR_RINT_MASK 0xFFFF0000 +#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) +#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) + +/*-----------------------------------------------------------------------------+ + | SDRAM UABus Base Address Reg + +-----------------------------------------------------------------------------*/ +#define SDRAM_UABBA_UBBA_MASK 0x0000000F + +/*-----------------------------------------------------------------------------+ + | Memory Bank 0-7 configuration + +-----------------------------------------------------------------------------*/ +#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ +#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ +#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ +#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ +#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ +#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ +#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ +#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ +#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ +#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ +#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ +#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ +#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ +#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ +#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ + +/*-----------------------------------------------------------------------------+ + | SDRAM TR0 Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_TR0_SDWR_MASK 0x80000000 +#define SDRAM_TR0_SDWR_2_CLK 0x00000000 +#define SDRAM_TR0_SDWR_3_CLK 0x80000000 +#define SDRAM_TR0_SDWD_MASK 0x40000000 +#define SDRAM_TR0_SDWD_0_CLK 0x00000000 +#define SDRAM_TR0_SDWD_1_CLK 0x40000000 +#define SDRAM_TR0_SDCL_MASK 0x01800000 +#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 +#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 +#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 +#define SDRAM_TR0_SDPA_MASK 0x000C0000 +#define SDRAM_TR0_SDPA_2_CLK 0x00040000 +#define SDRAM_TR0_SDPA_3_CLK 0x00080000 +#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 +#define SDRAM_TR0_SDCP_MASK 0x00030000 +#define SDRAM_TR0_SDCP_2_CLK 0x00000000 +#define SDRAM_TR0_SDCP_3_CLK 0x00010000 +#define SDRAM_TR0_SDCP_4_CLK 0x00020000 +#define SDRAM_TR0_SDCP_5_CLK 0x00030000 +#define SDRAM_TR0_SDLD_MASK 0x0000C000 +#define SDRAM_TR0_SDLD_1_CLK 0x00000000 +#define SDRAM_TR0_SDLD_2_CLK 0x00004000 +#define SDRAM_TR0_SDRA_MASK 0x0000001C +#define SDRAM_TR0_SDRA_6_CLK 0x00000000 +#define SDRAM_TR0_SDRA_7_CLK 0x00000004 +#define SDRAM_TR0_SDRA_8_CLK 0x00000008 +#define SDRAM_TR0_SDRA_9_CLK 0x0000000C +#define SDRAM_TR0_SDRA_10_CLK 0x00000010 +#define SDRAM_TR0_SDRA_11_CLK 0x00000014 +#define SDRAM_TR0_SDRA_12_CLK 0x00000018 +#define SDRAM_TR0_SDRA_13_CLK 0x0000001C +#define SDRAM_TR0_SDRD_MASK 0x00000003 +#define SDRAM_TR0_SDRD_2_CLK 0x00000001 +#define SDRAM_TR0_SDRD_3_CLK 0x00000002 +#define SDRAM_TR0_SDRD_4_CLK 0x00000003 + +/*-----------------------------------------------------------------------------+ + | SDRAM TR1 Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_TR1_RDSS_MASK 0xC0000000 +#define SDRAM_TR1_RDSS_TR0 0x00000000 +#define SDRAM_TR1_RDSS_TR1 0x40000000 +#define SDRAM_TR1_RDSS_TR2 0x80000000 +#define SDRAM_TR1_RDSS_TR3 0xC0000000 +#define SDRAM_TR1_RDSL_MASK 0x00C00000 +#define SDRAM_TR1_RDSL_STAGE1 0x00000000 +#define SDRAM_TR1_RDSL_STAGE2 0x00400000 +#define SDRAM_TR1_RDSL_STAGE3 0x00800000 +#define SDRAM_TR1_RDCD_MASK 0x00000800 +#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 +#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 +#define SDRAM_TR1_RDCT_MASK 0x000001FF +#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) +#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) +#define SDRAM_TR1_RDCT_MIN 0x00000000 +#define SDRAM_TR1_RDCT_MAX 0x000001FF + +/*-----------------------------------------------------------------------------+ + | SDRAM WDDCTR Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 +#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 +#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 +#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 +#define SDRAM_WDDCTR_DCD_MASK 0x000001FF + +/*-----------------------------------------------------------------------------+ + | SDRAM CLKTR Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 +#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 +#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 +#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 +#define SDRAM_CLKTR_DCDT_MASK 0x000001FF + +/*-----------------------------------------------------------------------------+ + | SDRAM DLYCAL Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC +#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) +#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) + +/*-----------------------------------------------------------------------------+ + | General Definition + +-----------------------------------------------------------------------------*/ +#define DEFAULT_SPD_ADDR1 0x53 +#define DEFAULT_SPD_ADDR2 0x52 +#define MAXBANKS 4 /* at most 4 dimm banks */ +#define MAX_SPD_BYTES 256 +#define NUMHALFCYCLES 4 +#define NUMMEMTESTS 8 +#define NUMMEMWORDS 8 +#define MAXBXCR 4 +#define TRUE 1 +#define FALSE 0 + +const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { + {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF}, + {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000}, + {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555}, + {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA}, + {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A}, + {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5}, + {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA}, + {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55} +}; + +/* bank_parms is used to sort the bank sizes by descending order */ +struct bank_param { + unsigned long cr; + unsigned long bank_size_bytes; +}; + +typedef struct bank_param BANKPARMS; + +#ifdef CFG_SIMULATE_SPD_EEPROM +extern unsigned char cfg_simulate_spd_eeprom[128]; +#endif + +unsigned char spd_read(uchar chip, uint addr); + +void get_spd_info(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void check_mem_type +(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void check_volt_type +(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_cfg0(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_cfg1(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_rtr (unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_tr0 (unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_tr1 (void); + +void program_ecc (unsigned long num_bytes); + +unsigned +long program_bxcr(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +/* + * This function is reading data from the DIMM module EEPROM over the SPD bus + * and uses that to program the sdram controller. + * + * This works on boards that has the same schematics that the AMCC walnut has. + * + * BUG: Don't handle ECC memory + * BUG: A few values in the TR register is currently hardcoded + */ + +long int spd_sdram(void) { + unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; + unsigned long dimm_populated[sizeof(iic0_dimm_addr)]; + unsigned long total_size; + unsigned long cfg0; + unsigned long mcsts; + unsigned long num_dimm_banks; /* on board dimm banks */ + + num_dimm_banks = sizeof(iic0_dimm_addr); + + /* + * Make sure I2C controller is initialized + * before continuing. + */ + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* + * Read the SPD information using I2C interface. Check to see if the + * DIMM slots are populated. + */ + get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * Check the memory type for the dimms plugged. + */ + check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * Check the voltage type for the dimms plugged. + */ + check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); + +#if defined(CONFIG_440GX) + /* + * Soft-reset SDRAM controller. + */ + mtsdr(sdr_srst, SDR0_SRST_DMC); + mtsdr(sdr_srst, 0x00000000); +#endif + + /* + * program 440GP SDRAM controller options (SDRAM0_CFG0) + */ + program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program 440GP SDRAM controller options (SDRAM0_CFG1) + */ + program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program SDRAM refresh register (SDRAM0_RTR) + */ + program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program SDRAM Timing Register 0 (SDRAM0_TR0) + */ + program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program the BxCR registers to find out total sdram installed + */ + total_size = program_bxcr(dimm_populated, iic0_dimm_addr, + num_dimm_banks); + + /* + * program SDRAM Clock Timing Register (SDRAM0_CLKTR) + */ + mtsdram(mem_clktr, 0x40000000); + + /* + * delay to ensure 200 usec has elapsed + */ + udelay(400); + + /* + * enable the memory controller + */ + mfsdram(mem_cfg0, cfg0); + mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN); + + /* + * wait for SDRAM_CFG0_DC_EN to complete + */ + while (1) { + mfsdram(mem_mcsts, mcsts); + if ((mcsts & SDRAM_MCSTS_MRSC) != 0) { + break; + } + } + + /* + * program SDRAM Timing Register 1, adding some delays + */ + program_tr1(); + + /* + * if ECC is enabled, initialize parity bits + */ + + return total_size; +} + +unsigned char spd_read(uchar chip, uint addr) +{ + unsigned char data[2]; + +#ifdef CFG_SIMULATE_SPD_EEPROM + if (chip == CFG_SIMULATE_SPD_EEPROM) { + /* + * Onboard spd eeprom requested -> simulate values + */ + return cfg_simulate_spd_eeprom[addr]; + } +#endif /* CFG_SIMULATE_SPD_EEPROM */ + + if (i2c_probe(chip) == 0) { + if (i2c_read(chip, addr, 1, data, 1) == 0) { + return data[0]; + } + } + + return 0; +} + +void get_spd_info(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long dimm_found; + unsigned char num_of_bytes; + unsigned char total_size; + + dimm_found = FALSE; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + num_of_bytes = 0; + total_size = 0; + + num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); + total_size = spd_read(iic0_dimm_addr[dimm_num], 1); + + if ((num_of_bytes != 0) && (total_size != 0)) { + dimm_populated[dimm_num] = TRUE; + dimm_found = TRUE; +#if 0 + printf("DIMM slot %lu: populated\n", dimm_num); +#endif + } else { + dimm_populated[dimm_num] = FALSE; +#if 0 + printf("DIMM slot %lu: Not populated\n", dimm_num); +#endif + } + } + + if (dimm_found == FALSE) { + printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); + hang(); + } +} + +void check_mem_type(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned char dimm_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); + switch (dimm_type) { + case 7: +#if 0 + printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num); +#endif + break; + default: + printf("ERROR: Unsupported DIMM detected in slot %lu.\n", + dimm_num); + printf("Only DDR SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + hang(); + break; + } + } + } +} + + +void check_volt_type(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long voltage_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); + if (voltage_type != 0x04) { + printf("ERROR: DIMM %lu with unsupported voltage level.\n", + dimm_num); + hang(); + } else { +#if 0 + printf("DIMM %lu voltage level supported.\n", dimm_num); +#endif + } + break; + } + } +} + +void program_cfg0(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long cfg0; + unsigned long ecc_enabled; + unsigned char ecc; + unsigned char attributes; + unsigned long data_width; + unsigned long dimm_32bit; + unsigned long dimm_64bit; + + /* + * get Memory Controller Options 0 data + */ + mfsdram(mem_cfg0, cfg0); + + /* + * clear bits + */ + cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK | + SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD | + SDRAM_CFG0_DMWD_MASK | + SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP); + + + /* + * FIXME: assume the DDR SDRAMs in both banks are the same + */ + ecc_enabled = TRUE; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + ecc = spd_read(iic0_dimm_addr[dimm_num], 11); + if (ecc != 0x02) { + ecc_enabled = FALSE; + } + + /* + * program Registered DIMM Enable + */ + attributes = spd_read(iic0_dimm_addr[dimm_num], 21); + if ((attributes & 0x02) != 0x00) { + cfg0 |= SDRAM_CFG0_RDEN; + } + + /* + * program DDR SDRAM Data Width + */ + data_width = + (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) + + (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8); + if (data_width == 64 || data_width == 72) { + dimm_64bit = TRUE; + cfg0 |= SDRAM_CFG0_DMWD_64; + } else if (data_width == 32 || data_width == 40) { + dimm_32bit = TRUE; + cfg0 |= SDRAM_CFG0_DMWD_32; + } else { + printf("WARNING: DIMM with datawidth of %lu bits.\n", + data_width); + printf("Only DIMMs with 32 or 64 bit datawidths supported.\n"); + hang(); + } + break; + } + } + + /* + * program Memory Data Error Checking + */ + if (ecc_enabled == TRUE) { + cfg0 |= SDRAM_CFG0_MCHK_GEN; + } else { + cfg0 |= SDRAM_CFG0_MCHK_NON; + } + + /* + * program Page Management Unit + */ + cfg0 |= SDRAM_CFG0_PMUD; + + /* + * program Memory Controller Options 0 + * Note: DCEN must be enabled after all DDR SDRAM controller + * configuration registers get initialized. + */ + mtsdram(mem_cfg0, cfg0); +} + +void program_cfg1(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long cfg1; + mfsdram(mem_cfg1, cfg1); + + /* + * Self-refresh exit, disable PM + */ + cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN); + + /* + * program Memory Controller Options 1 + */ + mtsdram(mem_cfg1, cfg1); +} + +void program_rtr (unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long bus_period_x_10; + unsigned long refresh_rate = 0; + unsigned char refresh_rate_type; + unsigned long refresh_interval; + unsigned long sdram_rtr; + PPC440_SYS_INFO sys_info; + + /* + * get the board info + */ + get_sys_info(&sys_info); + bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); + + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); + switch (refresh_rate_type) { + case 0x00: + refresh_rate = 15625; + break; + case 0x01: + refresh_rate = 15625/4; + break; + case 0x02: + refresh_rate = 15625/2; + break; + case 0x03: + refresh_rate = 15626*2; + break; + case 0x04: + refresh_rate = 15625*4; + break; + case 0x05: + refresh_rate = 15625*8; + break; + default: + printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n", + dimm_num); + printf("Replace the DIMM module with a supported DIMM.\n"); + break; + } + + break; + } + } + + refresh_interval = refresh_rate * 10 / bus_period_x_10; + sdram_rtr = (refresh_interval & 0x3ff8) << 16; + + /* + * program Refresh Timer Register (SDRAM0_RTR) + */ + mtsdram(mem_rtr, sdram_rtr); +} + +void program_tr0 (unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long tr0; + unsigned char wcsbc; + unsigned char t_rp_ns; + unsigned char t_rcd_ns; + unsigned char t_ras_ns; + unsigned long t_rp_clk; + unsigned long t_ras_rcd_clk; + unsigned long t_rcd_clk; + unsigned long t_rfc_clk; + unsigned long plb_check; + unsigned char cas_bit; + unsigned long cas_index; + unsigned char cas_2_0_available; + unsigned char cas_2_5_available; + unsigned char cas_3_0_available; + unsigned long cycle_time_ns_x_10[3]; + unsigned long tcyc_3_0_ns_x_10; + unsigned long tcyc_2_5_ns_x_10; + unsigned long tcyc_2_0_ns_x_10; + unsigned long tcyc_reg; + unsigned long bus_period_x_10; + PPC440_SYS_INFO sys_info; + unsigned long residue; + + /* + * get the board info + */ + get_sys_info(&sys_info); + bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); + + /* + * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits + */ + mfsdram(mem_tr0, tr0); + tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK | + SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK | + SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK | + SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK); + + /* + * initialization + */ + wcsbc = 0; + t_rp_ns = 0; + t_rcd_ns = 0; + t_ras_ns = 0; + cas_2_0_available = TRUE; + cas_2_5_available = TRUE; + cas_3_0_available = TRUE; + tcyc_2_0_ns_x_10 = 0; + tcyc_2_5_ns_x_10 = 0; + tcyc_3_0_ns_x_10 = 0; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); + t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; + t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; + t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30); + cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); + + for (cas_index = 0; cas_index < 3; cas_index++) { + switch (cas_index) { + case 0: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); + break; + case 1: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); + break; + default: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); + break; + } + + if ((tcyc_reg & 0x0F) >= 10) { + printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n", + dimm_num); + hang(); + } + + cycle_time_ns_x_10[cas_index] = + (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F); + } + + cas_index = 0; + + if ((cas_bit & 0x80) != 0) { + cas_index += 3; + } else if ((cas_bit & 0x40) != 0) { + cas_index += 2; + } else if ((cas_bit & 0x20) != 0) { + cas_index += 1; + } + + if (((cas_bit & 0x10) != 0) && (cas_index < 3)) { + tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; + cas_index++; + } else { + if (cas_index != 0) { + cas_index++; + } + cas_3_0_available = FALSE; + } + + if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { + tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index]; + cas_index++; + } else { + if (cas_index != 0) { + cas_index++; + } + cas_2_5_available = FALSE; + } + + if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { + tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; + cas_index++; + } else { + if (cas_index != 0) { + cas_index++; + } + cas_2_0_available = FALSE; + } + + break; + } + } + + /* + * Program SD_WR and SD_WCSBC fields + */ + tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */ + switch (wcsbc) { + case 0: + tr0 |= SDRAM_TR0_SDWD_0_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDWD_1_CLK; + break; + } + + /* + * Program SD_CASL field + */ + if ((cas_2_0_available == TRUE) && + (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { + tr0 |= SDRAM_TR0_SDCL_2_0_CLK; + } else if ((cas_2_5_available == TRUE) && + (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { + tr0 |= SDRAM_TR0_SDCL_2_5_CLK; + } else if ((cas_3_0_available == TRUE) && + (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { + tr0 |= SDRAM_TR0_SDCL_3_0_CLK; + } else { + printf("ERROR: No supported CAS latency with the installed DIMMs.\n"); + printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); + printf("Make sure the PLB speed is within the supported range.\n"); + hang(); + } + + /* + * Calculate Trp in clock cycles and round up if necessary + * Program SD_PTA field + */ + t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION; + plb_check = ONE_BILLION * t_rp_clk / t_rp_ns; + if (sys_info.freqPLB != plb_check) { + t_rp_clk++; + } + switch ((unsigned long)t_rp_clk) { + case 0: + case 1: + case 2: + tr0 |= SDRAM_TR0_SDPA_2_CLK; + break; + case 3: + tr0 |= SDRAM_TR0_SDPA_3_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDPA_4_CLK; + break; + } + + /* + * Program SD_CTP field + */ + t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION; + plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns); + if (sys_info.freqPLB != plb_check) { + t_ras_rcd_clk++; + } + switch (t_ras_rcd_clk) { + case 0: + case 1: + case 2: + tr0 |= SDRAM_TR0_SDCP_2_CLK; + break; + case 3: + tr0 |= SDRAM_TR0_SDCP_3_CLK; + break; + case 4: + tr0 |= SDRAM_TR0_SDCP_4_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDCP_5_CLK; + break; + } + + /* + * Program SD_LDF field + */ + tr0 |= SDRAM_TR0_SDLD_2_CLK; + + /* + * Program SD_RFTA field + * FIXME tRFC hardcoded as 75 nanoseconds + */ + t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75); + residue = sys_info.freqPLB % (ONE_BILLION / 75); + if (residue >= (ONE_BILLION / 150)) { + t_rfc_clk++; + } + switch (t_rfc_clk) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + tr0 |= SDRAM_TR0_SDRA_6_CLK; + break; + case 7: + tr0 |= SDRAM_TR0_SDRA_7_CLK; + break; + case 8: + tr0 |= SDRAM_TR0_SDRA_8_CLK; + break; + case 9: + tr0 |= SDRAM_TR0_SDRA_9_CLK; + break; + case 10: + tr0 |= SDRAM_TR0_SDRA_10_CLK; + break; + case 11: + tr0 |= SDRAM_TR0_SDRA_11_CLK; + break; + case 12: + tr0 |= SDRAM_TR0_SDRA_12_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDRA_13_CLK; + break; + } + + /* + * Program SD_RCD field + */ + t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION; + plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns; + if (sys_info.freqPLB != plb_check) { + t_rcd_clk++; + } + switch (t_rcd_clk) { + case 0: + case 1: + case 2: + tr0 |= SDRAM_TR0_SDRD_2_CLK; + break; + case 3: + tr0 |= SDRAM_TR0_SDRD_3_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDRD_4_CLK; + break; + } + +#if 0 + printf("tr0: %x\n", tr0); +#endif + mtsdram(mem_tr0, tr0); +} + +void program_tr1 (void) +{ + unsigned long tr0; + unsigned long tr1; + unsigned long cfg0; + unsigned long ecc_temp; + unsigned long dlycal; + unsigned long dly_val; + unsigned long i, j, k; + unsigned long bxcr_num; + unsigned long max_pass_length; + unsigned long current_pass_length; + unsigned long current_fail_length; + unsigned long current_start; + unsigned long rdclt; + unsigned long rdclt_offset; + long max_start; + long max_end; + long rdclt_average; + unsigned char window_found; + unsigned char fail_found; + unsigned char pass_found; + unsigned long * membase; + PPC440_SYS_INFO sys_info; + + /* + * get the board info + */ + get_sys_info(&sys_info); + + /* + * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits + */ + mfsdram(mem_tr1, tr1); + tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK | + SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK); + + mfsdram(mem_tr0, tr0); + if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) && + (sys_info.freqPLB > 100000000)) { + tr1 |= SDRAM_TR1_RDSS_TR2; + tr1 |= SDRAM_TR1_RDSL_STAGE3; + tr1 |= SDRAM_TR1_RDCD_RCD_1_2; + } else { + tr1 |= SDRAM_TR1_RDSS_TR1; + tr1 |= SDRAM_TR1_RDSL_STAGE2; + tr1 |= SDRAM_TR1_RDCD_RCD_0_0; + } + + /* + * save CFG0 ECC setting to a temporary variable and turn ECC off + */ + mfsdram(mem_cfg0, cfg0); + ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK; + mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); + + /* + * get the delay line calibration register value + */ + mfsdram(mem_dlycal, dlycal); + dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; + + max_pass_length = 0; + max_start = 0; + max_end = 0; + current_pass_length = 0; + current_fail_length = 0; + current_start = 0; + rdclt_offset = 0; + window_found = FALSE; + fail_found = FALSE; + pass_found = FALSE; +#ifdef DEBUG + printf("Starting memory test "); +#endif + for (k = 0; k < NUMHALFCYCLES; k++) { + for (rdclt = 0; rdclt < dly_val; rdclt++) { + /* + * Set the timing reg for the test. + */ + mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); + + for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { + mtdcr(memcfga, mem_b0cr + (bxcr_num<<2)); + if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { + /* Bank is enabled */ + membase = (unsigned long*) + (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); + + /* + * Run the short memory test + */ + for (i = 0; i < NUMMEMTESTS; i++) { + for (j = 0; j < NUMMEMWORDS; j++) { + membase[j] = test[i][j]; + ppcDcbf((unsigned long)&(membase[j])); + } + + for (j = 0; j < NUMMEMWORDS; j++) { + if (membase[j] != test[i][j]) { + ppcDcbf((unsigned long)&(membase[j])); + break; + } + ppcDcbf((unsigned long)&(membase[j])); + } + + if (j < NUMMEMWORDS) { + break; + } + } + + /* + * see if the rdclt value passed + */ + if (i < NUMMEMTESTS) { + break; + } + } + } + + if (bxcr_num == MAXBXCR) { + if (fail_found == TRUE) { + pass_found = TRUE; + if (current_pass_length == 0) { + current_start = rdclt_offset + rdclt; + } + + current_fail_length = 0; + current_pass_length++; + + if (current_pass_length > max_pass_length) { + max_pass_length = current_pass_length; + max_start = current_start; + max_end = rdclt_offset + rdclt; + } + } + } else { + current_pass_length = 0; + current_fail_length++; + + if (current_fail_length >= (dly_val>>2)) { + if (fail_found == FALSE) { + fail_found = TRUE; + } else if (pass_found == TRUE) { + window_found = TRUE; + break; + } + } + } + } +#ifdef DEBUG + printf("."); +#endif + if (window_found == TRUE) { + break; + } + + tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; + rdclt_offset += dly_val; + } +#ifdef DEBUG + printf("\n"); +#endif + + /* + * make sure we find the window + */ + if (window_found == FALSE) { + printf("ERROR: Cannot determine a common read delay.\n"); + hang(); + } + + /* + * restore the orignal ECC setting + */ + mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); + + /* + * set the SDRAM TR1 RDCD value + */ + tr1 &= ~SDRAM_TR1_RDCD_MASK; + if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) { + tr1 |= SDRAM_TR1_RDCD_RCD_1_2; + } else { + tr1 |= SDRAM_TR1_RDCD_RCD_0_0; + } + + /* + * set the SDRAM TR1 RDCLT value + */ + tr1 &= ~SDRAM_TR1_RDCT_MASK; + while (max_end >= (dly_val << 1)) { + max_end -= (dly_val << 1); + max_start -= (dly_val << 1); + } + + rdclt_average = ((max_start + max_end) >> 1); + if (rdclt_average >= 0x60) + while (1) + ; + + if (rdclt_average < 0) { + rdclt_average = 0; + } + + if (rdclt_average >= dly_val) { + rdclt_average -= dly_val; + tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; + } + tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average); + +#if 0 + printf("tr1: %x\n", tr1); +#endif + /* + * program SDRAM Timing Register 1 TR1 + */ + mtsdram(mem_tr1, tr1); +} + +unsigned long program_bxcr(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long bank_base_addr; + unsigned long cr; + unsigned long i; + unsigned long j; + unsigned long temp; + unsigned char num_row_addr; + unsigned char num_col_addr; + unsigned char num_banks; + unsigned char bank_size_id; + unsigned long ctrl_bank_num[MAXBANKS]; + unsigned long bx_cr_num; + unsigned long largest_size_index; + unsigned long largest_size; + unsigned long current_size_index; + BANKPARMS bank_parms[MAXBXCR]; + unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */ + unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/ + + /* + * Set the BxCR regs. First, wipe out the bank config registers. + */ + for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { + mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2)); + mtdcr(memcfgd, 0x00000000); + bank_parms[bx_cr_num].bank_size_bytes = 0; + } + +#ifdef CONFIG_BAMBOO + /* + * This next section is hardware dependent and must be programmed + * to match the hardware. For bammboo, the following holds... + * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 + * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1 + * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1 + * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3 + * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM + */ + ctrl_bank_num[0] = 0; + ctrl_bank_num[1] = 1; + ctrl_bank_num[2] = 3; +#else + ctrl_bank_num[0] = 0; + ctrl_bank_num[1] = 1; + ctrl_bank_num[2] = 2; + ctrl_bank_num[3] = 3; +#endif + + /* + * reset the bank_base address + */ + bank_base_addr = CFG_SDRAM_BASE; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); + num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); + num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); + bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); + + /* + * Set the SDRAM0_BxCR regs + */ + cr = 0; + switch (bank_size_id) { + case 0x02: + cr |= SDRAM_BXCR_SDSZ_8; + break; + case 0x04: + cr |= SDRAM_BXCR_SDSZ_16; + break; + case 0x08: + cr |= SDRAM_BXCR_SDSZ_32; + break; + case 0x10: + cr |= SDRAM_BXCR_SDSZ_64; + break; + case 0x20: + cr |= SDRAM_BXCR_SDSZ_128; + break; + case 0x40: + cr |= SDRAM_BXCR_SDSZ_256; + break; + case 0x80: + cr |= SDRAM_BXCR_SDSZ_512; + break; + default: + printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", + dimm_num); + printf("ERROR: Unsupported value for the banksize: %d.\n", + bank_size_id); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + hang(); + } + + switch (num_col_addr) { + case 0x08: + cr |= SDRAM_BXCR_SDAM_1; + break; + case 0x09: + cr |= SDRAM_BXCR_SDAM_2; + break; + case 0x0A: + cr |= SDRAM_BXCR_SDAM_3; + break; + case 0x0B: + cr |= SDRAM_BXCR_SDAM_4; + break; + default: + printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", + dimm_num); + printf("ERROR: Unsupported value for number of " + "column addresses: %d.\n", num_col_addr); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + hang(); + } + + /* + * enable the bank + */ + cr |= SDRAM_BXCR_SDBE; + + for (i = 0; i < num_banks; i++) { + bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = + (4 * 1024 * 1024) * bank_size_id; + bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; + } + } + } + + /* Initialize sort tables */ + for (i = 0; i < MAXBXCR; i++) { + sorted_bank_num[i] = i; + sorted_bank_size[i] = bank_parms[i].bank_size_bytes; + } + + for (i = 0; i < MAXBXCR-1; i++) { + largest_size = sorted_bank_size[i]; + largest_size_index = 255; + + /* Find the largest remaining value */ + for (j = i + 1; j < MAXBXCR; j++) { + if (sorted_bank_size[j] > largest_size) { + /* Save largest remaining value and its index */ + largest_size = sorted_bank_size[j]; + largest_size_index = j; + } + } + + if (largest_size_index != 255) { + /* Swap the current and largest values */ + current_size_index = sorted_bank_num[largest_size_index]; + sorted_bank_size[largest_size_index] = sorted_bank_size[i]; + sorted_bank_size[i] = largest_size; + sorted_bank_num[largest_size_index] = sorted_bank_num[i]; + sorted_bank_num[i] = current_size_index; + } + } + + /* Set the SDRAM0_BxCR regs thanks to sort tables */ + for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { + if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { + mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); + temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | + SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); + temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | + bank_parms[sorted_bank_num[bx_cr_num]].cr; + mtdcr(memcfgd, temp); + bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; + } + } + + return(bank_base_addr); +} + +void program_ecc (unsigned long num_bytes) +{ + unsigned long bank_base_addr; + unsigned long current_address; + unsigned long end_address; + unsigned long address_increment; + unsigned long cfg0; + + /* + * get Memory Controller Options 0 data + */ + mfsdram(mem_cfg0, cfg0); + + /* + * reset the bank_base address + */ + bank_base_addr = CFG_SDRAM_BASE; + + if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { + mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | + SDRAM_CFG0_MCHK_GEN); + + if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) { + address_increment = 4; + } else { + address_increment = 8; + } + + current_address = (unsigned long)(bank_base_addr); + end_address = (unsigned long)(bank_base_addr) + num_bytes; + + while (current_address < end_address) { + *((unsigned long*)current_address) = 0x00000000; + current_address += address_increment; + } + + mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | + SDRAM_CFG0_MCHK_CHK); + } +} + +#endif /* CONFIG_440 */ + +#endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c new file mode 100644 index 0000000..553c491 --- /dev/null +++ b/cpu/ppc4xx/speed.c @@ -0,0 +1,568 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* ------------------------------------------------------------------------- */ + +#define ONE_BILLION 1000000000 + + +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) + +void get_sys_info (PPC405_SYS_INFO * sysInfo) +{ + unsigned long pllmr; + unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); + uint pvr = get_pvr(); + unsigned long psr; + unsigned long m; + + /* + * Read PLL Mode register + */ + pllmr = mfdcr (pllmd); + + /* + * Read Pin Strapping register + */ + psr = mfdcr (strap); + + /* + * Determine FWD_DIV. + */ + sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29); + + /* + * Determine FBK_DIV. + */ + sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25); + if (sysInfo->pllFbkDiv == 0) { + sysInfo->pllFbkDiv = 16; + } + + /* + * Determine PLB_DIV. + */ + sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1; + + /* + * Determine PCI_DIV. + */ + sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1; + + /* + * Determine EXTBUS_DIV. + */ + sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2; + + /* + * Determine OPB_DIV. + */ + sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1; + + /* + * Check if PPC405GPr used (mask minor revision field) + */ + if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { + /* + * Determine FWD_DIV B (only PPC405GPr with new mode strapping). + */ + sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK); + + /* + * Determine factor m depending on PLL feedback clock source + */ + if (!(psr & PSR_PCI_ASYNC_EN)) { + if (psr & PSR_NEW_MODE_EN) { + /* + * sync pci clock used as feedback (new mode) + */ + m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv; + } else { + /* + * sync pci clock used as feedback (legacy mode) + */ + m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv; + } + } else if (psr & PSR_NEW_MODE_EN) { + if (psr & PSR_PERCLK_SYNC_MODE_EN) { + /* + * PerClk used as feedback (new mode) + */ + m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv; + } else { + /* + * CPU clock used as feedback (new mode) + */ + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv; + } + } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) { + /* + * PerClk used as feedback (legacy mode) + */ + m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv; + } else { + /* + * PLB clock used as feedback (legacy mode) + */ + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv; + } + + sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / + (unsigned long long)sysClkPeriodPs; + sysInfo->freqProcessor = sysInfo->freqVCOHz / sysInfo->pllFwdDiv; + sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv); + } else { + /* + * Check pllFwdDiv to see if running in bypass mode where the CPU speed + * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO + * to make sure it is within the proper range. + * spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV + * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding. + */ + if (sysInfo->pllFwdDiv == 1) { + sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ; + sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv; + } else { + sysInfo->freqVCOHz = ( 1000000000000LL * + (unsigned long long)sysInfo->pllFwdDiv * + (unsigned long long)sysInfo->pllFbkDiv * + (unsigned long long)sysInfo->pllPlbDiv + ) / (unsigned long long)sysClkPeriodPs; + sysInfo->freqPLB = (ONE_BILLION / ((sysClkPeriodPs * 10) / + sysInfo->pllFbkDiv)) * 10000; + sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv; + } + } +} + + +/******************************************** + * get_OPB_freq + * return OPB bus freq in Hz + *********************************************/ +ulong get_OPB_freq (void) +{ + ulong val = 0; + + PPC405_SYS_INFO sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqPLB / sys_info.pllOpbDiv; + + return val; +} + + +/******************************************** + * get_PCI_freq + * return PCI bus freq in Hz + *********************************************/ +ulong get_PCI_freq (void) +{ + ulong val; + PPC405_SYS_INFO sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqPLB / sys_info.pllPciDiv; + return val; +} + + +#elif defined(CONFIG_440) + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +void get_sys_info (sys_info_t *sysInfo) +{ + unsigned long temp; + unsigned long reg; + unsigned long lfdiv; + unsigned long m; + unsigned long prbdv0; + /* + WARNING: ASSUMES the following: + ENG=1 + PRADV0=1 + PRBDV0=1 + */ + + /* Decode CPR0_PLLD0 for divisors */ + mfclk(clk_plld, reg); + temp = (reg & PLLD_FWDVA_MASK) >> 16; + sysInfo->pllFwdDivA = temp ? temp : 16; + temp = (reg & PLLD_FWDVB_MASK) >> 8; + sysInfo->pllFwdDivB = temp ? temp: 8 ; + temp = (reg & PLLD_FBDV_MASK) >> 24; + sysInfo->pllFbkDiv = temp ? temp : 32; + lfdiv = reg & PLLD_LFBDV_MASK; + + mfclk(clk_opbd, reg); + temp = (reg & OPBDDV_MASK) >> 24; + sysInfo->pllOpbDiv = temp ? temp : 4; + + mfclk(clk_perd, reg); + temp = (reg & PERDV_MASK) >> 24; + sysInfo->pllExtBusDiv = temp ? temp : 8; + + mfclk(clk_primbd, reg); + temp = (reg & PRBDV_MASK) >> 24; + prbdv0 = temp ? temp : 8; + + mfclk(clk_spcid, reg); + temp = (reg & SPCID_MASK) >> 24; + sysInfo->pllPciDiv = temp ? temp : 4; + + /* Calculate 'M' based on feedback source */ + mfsdr(sdr_sdstp0, reg); + temp = (reg & PLLSYS0_SEL_MASK) >> 27; + if (temp == 0) { /* PLL output */ + /* Figure which pll to use */ + mfclk(clk_pllc, reg); + temp = (reg & PLLC_SRC_MASK) >> 29; + if (!temp) /* PLLOUTA */ + m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; + else /* PLLOUTB */ + m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB; + } + else if (temp == 1) /* CPU output */ + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA; + else /* PerClk */ + m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; + sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; + sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; + sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv; + sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv; + + /* Figure which timer source to use */ + if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */ + temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */ + if (CONFIG_SYS_CLK_FREQ > temp) + sysInfo->freqTmrClk = temp; + else + sysInfo->freqTmrClk = CONFIG_SYS_CLK_FREQ; + } + else /* Internal clock */ + sysInfo->freqTmrClk = sysInfo->freqProcessor; +} +/******************************************** + * get_PCI_freq + * return PCI bus freq in Hz + *********************************************/ +ulong get_PCI_freq (void) +{ + sys_info_t sys_info; + get_sys_info (&sys_info); + return sys_info.freqPCI; +} + +#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) +void get_sys_info (sys_info_t * sysInfo) +{ + unsigned long strp0; + unsigned long temp; + unsigned long m; + + /* Extract configured divisors */ + strp0 = mfdcr( cpc0_strp0 ); + sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15); + sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12); + temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18; + sysInfo->pllFbkDiv = temp ? temp : 16; + sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10); + sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8); + + /* Calculate 'M' based on feedback source */ + if( strp0 & PLLSYS0_EXTSL_MASK ) + m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; + else + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA; + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; + sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB; + if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */ + sysInfo->freqPLB >>= 1; + sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; + sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; + +} +#else +void get_sys_info (sys_info_t * sysInfo) +{ + unsigned long strp0; + unsigned long strp1; + unsigned long temp; + unsigned long temp1; + unsigned long lfdiv; + unsigned long m; + unsigned long prbdv0; + + /* Extract configured divisors */ + mfsdr( sdr_sdstp0,strp0 ); + mfsdr( sdr_sdstp1,strp1 ); + + temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8); + sysInfo->pllFwdDivA = temp ? temp : 16 ; + temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5); + sysInfo->pllFwdDivB = temp ? temp: 8 ; + temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12; + sysInfo->pllFbkDiv = temp ? temp : 32; + temp = (strp0 & PLLSYS0_OPB_DIV_MASK); + sysInfo->pllOpbDiv = temp ? temp : 4; + temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24; + sysInfo->pllExtBusDiv = temp ? temp : 4; + prbdv0 = (strp0 >> 2) & 0x7; + + /* Calculate 'M' based on feedback source */ + temp = (strp0 & PLLSYS0_SEL_MASK) >> 27; + temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26; + lfdiv = temp1 ? temp1 : 64; + if (temp == 0) { /* PLL output */ + /* Figure which pll to use */ + temp = (strp0 & PLLSYS0_SRC_MASK) >> 30; + if (!temp) + m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; + else + m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB; + } + else if (temp == 1) /* CPU output */ + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA; + else /* PerClk */ + m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; + sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; + sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; + sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; + +} +#endif + +ulong get_OPB_freq (void) +{ + + sys_info_t sys_info; + get_sys_info (&sys_info); + return sys_info.freqOPB; +} + +#elif defined(CONFIG_XILINX_ML300) +extern void get_sys_info (sys_info_t * sysInfo); +extern ulong get_PCI_freq (void); + +#elif defined(CONFIG_AP1000) +void get_sys_info (sys_info_t * sysInfo) { + sysInfo->freqProcessor = 240 * 1000 * 1000; + sysInfo->freqPLB = 80 * 1000 * 1000; + sysInfo->freqPCI = 33 * 1000 * 1000; +} + +#elif defined(CONFIG_405) + +void get_sys_info (sys_info_t * sysInfo) { + + sysInfo->freqVCOMhz=3125000; + sysInfo->freqProcessor=12*1000*1000; + sysInfo->freqPLB=50*1000*1000; + sysInfo->freqPCI=66*1000*1000; + +} + +#elif defined(CONFIG_405EP) +void get_sys_info (PPC405_SYS_INFO * sysInfo) +{ + unsigned long pllmr0; + unsigned long pllmr1; + unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); + unsigned long m; + unsigned long pllmr0_ccdv; + + /* + * Read PLL Mode registers + */ + pllmr0 = mfdcr (cpc0_pllmr0); + pllmr1 = mfdcr (cpc0_pllmr1); + + /* + * Determine forward divider A + */ + sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16); + + /* + * Determine forward divider B (should be equal to A) + */ + sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12); + + /* + * Determine FBK_DIV. + */ + sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20); + if (sysInfo->pllFbkDiv == 0) { + sysInfo->pllFbkDiv = 16; + } + + /* + * Determine PLB_DIV. + */ + sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1; + + /* + * Determine PCI_DIV. + */ + sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1; + + /* + * Determine EXTBUS_DIV. + */ + sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2; + + /* + * Determine OPB_DIV. + */ + sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1; + + /* + * Determine the M factor + */ + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; + + /* + * Determine VCO clock frequency + */ + sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / + (unsigned long long)sysClkPeriodPs; + + /* + * Determine CPU clock frequency + */ + pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1; + if (pllmr1 & PLLMR1_SSCS_MASK) { + /* + * This is true if FWDVA == FWDVB: + * sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) + * / pllmr0_ccdv; + */ + sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB) + / sysInfo->pllFwdDiv / pllmr0_ccdv; + } else { + sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv; + } + + /* + * Determine PLB clock frequency + */ + sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv; +} + + +/******************************************** + * get_OPB_freq + * return OPB bus freq in Hz + *********************************************/ +ulong get_OPB_freq (void) +{ + ulong val = 0; + + PPC405_SYS_INFO sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqPLB / sys_info.pllOpbDiv; + + return val; +} + + +/******************************************** + * get_PCI_freq + * return PCI bus freq in Hz + *********************************************/ +ulong get_PCI_freq (void) +{ + ulong val; + PPC405_SYS_INFO sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqPLB / sys_info.pllPciDiv; + return val; +} + +#endif + +int get_clocks (void) +{ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP) + DECLARE_GLOBAL_DATA_PTR; + + sys_info_t sys_info; + + get_sys_info (&sys_info); + gd->cpu_clk = sys_info.freqProcessor; + gd->bus_clk = sys_info.freqPLB; + +#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ + +#ifdef CONFIG_IOP480 + DECLARE_GLOBAL_DATA_PTR; + + gd->cpu_clk = 66000000; + gd->bus_clk = 66000000; +#endif + return (0); +} + + +/******************************************** + * get_bus_freq + * return PLB bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + ulong val; + +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP) + sys_info_t sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqPLB; + +#elif defined(CONFIG_IOP480) + + val = 66; + +#else +# error get_bus_freq() not implemented +#endif + + return val; +} diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S new file mode 100644 index 0000000..48b430d --- /dev/null +++ b/cpu/ppc4xx/start.S @@ -0,0 +1,1687 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000,2001,2002 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/*------------------------------------------------------------------------------+ */ +/* */ +/* This source code has been made available to you by IBM on an AS-IS */ +/* basis. Anyone receiving this source is licensed under IBM */ +/* copyrights to use it in any way he or she deems fit, including */ +/* copying it, modifying it, compiling it, and redistributing it either */ +/* with or without modifications. No license under IBM patents or */ +/* patent applications is to be implied by the copyright license. */ +/* */ +/* Any user of this software should understand that IBM cannot provide */ +/* technical support for this software and will not be responsible for */ +/* any consequences resulting from the use of this software. */ +/* */ +/* Any person who transfers this source code or any derivative work */ +/* must include the IBM copyright notice, this paragraph, and the */ +/* preceding two paragraphs in the transferred software. */ +/* */ +/* COPYRIGHT I B M CORPORATION 1995 */ +/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ +/*------------------------------------------------------------------------------- */ + +/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards + * + * + * The processor starts at 0xfffffffc and the code is executed + * from flash/rom. + * in memory, but as long we don't jump around before relocating. + * board_init lies at a quite high address and when the cpu has + * jumped there, everything is ok. + * This works because the cpu gives the FLASH (CS0) the whole + * address space at startup, and board_init lies as a echo of + * the flash somewhere up there in the memorymap. + * + * board_init will change CS0 to be positioned at the correct + * address and (s)dram will be positioned at address 0 + */ +#include +#include +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#ifdef CFG_INIT_DCACHE_CS +# if (CFG_INIT_DCACHE_CS == 0) +# define PBxAP pb0ap +# define PBxCR pb0cr +# endif +# if (CFG_INIT_DCACHE_CS == 1) +# define PBxAP pb1ap +# define PBxCR pb1cr +# endif +# if (CFG_INIT_DCACHE_CS == 2) +# define PBxAP pb2ap +# define PBxCR pb2cr +# endif +# if (CFG_INIT_DCACHE_CS == 3) +# define PBxAP pb3ap +# define PBxCR pb3cr +# endif +# if (CFG_INIT_DCACHE_CS == 4) +# define PBxAP pb4ap +# define PBxCR pb4cr +# endif +# if (CFG_INIT_DCACHE_CS == 5) +# define PBxAP pb5ap +# define PBxCR pb5cr +# endif +# if (CFG_INIT_DCACHE_CS == 6) +# define PBxAP pb6ap +# define PBxCR pb6cr +# endif +# if (CFG_INIT_DCACHE_CS == 7) +# define PBxAP pb7ap +# define PBxCR pb7cr +# endif +#endif /* CFG_INIT_DCACHE_CS */ + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ + + + .extern ext_bus_cntlr_init + .extern sdram_init + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * 440 Startup -- on reset only the top 4k of the effective + * address space is mapped in by an entry in the instruction + * and data shadow TLB. The .bootpg section is located in the + * top 4k & does only what's necessary to map in the the rest + * of the boot rom. Once the boot rom is mapped in we can + * proceed with normal startup. + * + * NOTE: CS0 only covers the top 2MB of the effective address + * space after reset. + */ + +#if defined(CONFIG_440) + .section .bootpg,"ax" + .globl _start_440 + +/**************************************************************************/ +_start_440: + /*----------------------------------------------------------------*/ + /* Clear and set up some registers. */ + /*----------------------------------------------------------------*/ + iccci r0,r0 /* NOTE: operands not used for 440 */ + dccci r0,r0 /* NOTE: operands not used for 440 */ + sync + li r0,0 + mtspr srr0,r0 + mtspr srr1,r0 + mtspr csrr0,r0 + mtspr csrr1,r0 +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */ + mtspr mcsrr0,r0 + mtspr mcsrr1,r0 + mfspr r1, mcsr + mtspr mcsr,r1 +#endif + /*----------------------------------------------------------------*/ + /* Initialize debug */ + /*----------------------------------------------------------------*/ + mtspr dbcr0,r0 + mtspr dbcr1,r0 + mtspr dbcr2,r0 + mtspr iac1,r0 + mtspr iac2,r0 + mtspr iac3,r0 + mtspr dac1,r0 + mtspr dac2,r0 + mtspr dvc1,r0 + mtspr dvc2,r0 + + mfspr r1,dbsr + mtspr dbsr,r1 /* Clear all valid bits */ + + /*----------------------------------------------------------------*/ + /* CCR0 init */ + /*----------------------------------------------------------------*/ + /* Disable store gathering & broadcast, guarantee inst/data + * cache block touch, force load/store alignment + * (see errata 1.12: 440_33) + */ + lis r1,0x0030 /* store gathering & broadcast disable */ + ori r1,r1,0x6000 /* cache touch */ + mtspr ccr0,r1 + + /*----------------------------------------------------------------*/ + /* Setup interrupt vectors */ + /*----------------------------------------------------------------*/ + mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */ + li r1,0x0100 + mtspr ivor0,r1 /* Critical input */ + li r1,0x0200 + mtspr ivor1,r1 /* Machine check */ + li r1,0x0300 + mtspr ivor2,r1 /* Data storage */ + li r1,0x0400 + mtspr ivor3,r1 /* Instruction storage */ + li r1,0x0500 + mtspr ivor4,r1 /* External interrupt */ + li r1,0x0600 + mtspr ivor5,r1 /* Alignment */ + li r1,0x0700 + mtspr ivor6,r1 /* Program check */ + li r1,0x0800 + mtspr ivor7,r1 /* Floating point unavailable */ + li r1,0x0c00 + mtspr ivor8,r1 /* System call */ + li r1,0x1000 + mtspr ivor10,r1 /* Decrementer (PIT for 440) */ + li r1,0x1400 + mtspr ivor13,r1 /* Data TLB error */ + li r1,0x1300 + mtspr ivor14,r1 /* Instr TLB error */ + li r1,0x2000 + mtspr ivor15,r1 /* Debug */ + + /*----------------------------------------------------------------*/ + /* Configure cache regions */ + /*----------------------------------------------------------------*/ + mtspr inv0,r0 + mtspr inv1,r0 + mtspr inv2,r0 + mtspr inv3,r0 + mtspr dnv0,r0 + mtspr dnv1,r0 + mtspr dnv2,r0 + mtspr dnv3,r0 + mtspr itv0,r0 + mtspr itv1,r0 + mtspr itv2,r0 + mtspr itv3,r0 + mtspr dtv0,r0 + mtspr dtv1,r0 + mtspr dtv2,r0 + mtspr dtv3,r0 + + /*----------------------------------------------------------------*/ + /* Cache victim limits */ + /*----------------------------------------------------------------*/ + /* floors 0, ceiling max to use the entire cache -- nothing locked + */ + lis r1,0x0001 + ori r1,r1,0xf800 + mtspr ivlim,r1 + mtspr dvlim,r1 + + /*----------------------------------------------------------------*/ + /* Clear all TLB entries -- TID = 0, TS = 0 */ + /*----------------------------------------------------------------*/ + mtspr mmucr,r0 + li r1,0x003f /* 64 TLB entries */ + mtctr r1 +0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ + subi r1,r1,0x0001 + bdnz 0b + + /*----------------------------------------------------------------*/ + /* TLB entry setup -- step thru tlbtab */ + /*----------------------------------------------------------------*/ + bl tlbtab /* Get tlbtab pointer */ + mr r5,r0 + li r1,0x003f /* 64 TLB entries max */ + mtctr r1 + li r4,0 /* TLB # */ + + addi r5,r5,-4 +1: lwzu r0,4(r5) + cmpwi r0,0 + beq 2f /* 0 marks end */ + lwzu r1,4(r5) + lwzu r2,4(r5) + tlbwe r0,r4,0 /* TLB Word 0 */ + tlbwe r1,r4,1 /* TLB Word 1 */ + tlbwe r2,r4,2 /* TLB Word 2 */ + addi r4,r4,1 /* Next TLB */ + bdnz 1b + + /*----------------------------------------------------------------*/ + /* Continue from 'normal' start */ + /*----------------------------------------------------------------*/ +2: bl 3f + b _start + +3: li r0,0 + mtspr srr1,r0 /* Keep things disabled for now */ + mflr r1 + mtspr srr0,r1 + rfi +#endif /* CONFIG_440 */ + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + +/* + * Maybe this should be moved somewhere else because the current + * location (0x100) is where the CriticalInput Execption should be. + */ + . = EXC_OFF_SYS_RESET + .globl _start +_start: + +/*****************************************************************************/ +#if defined(CONFIG_440) + + /*----------------------------------------------------------------*/ + /* Clear and set up some registers. */ + /*----------------------------------------------------------------*/ + li r0,0x0000 + lis r1,0xffff + mtspr dec,r0 /* prevent dec exceptions */ + mtspr tbl,r0 /* prevent fit & wdt exceptions */ + mtspr tbu,r0 + mtspr tsr,r1 /* clear all timer exception status */ + mtspr tcr,r0 /* disable all */ + mtspr esr,r0 /* clear exception syndrome register */ + mtxer r0 /* clear integer exception register */ +#if !defined(CONFIG_440GX) + lis r1,0x0002 /* set CE bit (Critical Exceptions) */ + ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */ + mtmsr r1 /* change MSR */ +#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR) + bl __440gx_msr_set + b __440gx_msr_continue + +__440gx_msr_set: + lis r1, 0x0002 /* set CE bit (Critical Exceptions) */ + ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */ + mtspr srr1,r1 + mflr r1 + mtspr srr0,r1 + rfi +__440gx_msr_continue: +#endif + + /*----------------------------------------------------------------*/ + /* Debug setup -- some (not very good) ice's need an event*/ + /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */ + /* value you need in this case 0x8cff 0000 should do the trick */ + /*----------------------------------------------------------------*/ +#if defined(CFG_INIT_DBCR) + lis r1,0xffff + ori r1,r1,0xffff + mtspr dbsr,r1 /* Clear all status bits */ + lis r0,CFG_INIT_DBCR@h + ori r0,r0,CFG_INIT_DBCR@l + mtspr dbcr0,r0 + isync +#endif + + /*----------------------------------------------------------------*/ + /* Setup the internal SRAM */ + /*----------------------------------------------------------------*/ + li r0,0 +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + /* Clear Dcache to use as RAM */ + addis r3,r0,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + addis r4,r0,CFG_INIT_RAM_END@h + ori r4,r4,CFG_INIT_RAM_END@l + rlwinm. r5,r4,0,27,31 + rlwinm r5,r4,27,5,31 + beq ..d_ran + addi r5,r5,0x0001 +..d_ran: + mtctr r5 +..d_ag: + dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag +#else +#if defined (CONFIG_440GX) || defined(CONFIG_440SP) + mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ +#endif + mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ + + li r2,0x7fff + ori r2,r2,0xffff + mfdcr r1,isram0_dpc + and r1,r1,r2 /* Disable parity check */ + mtdcr isram0_dpc,r1 + mfdcr r1,isram0_pmeg + andis. r1,r1,r2 /* Disable pwr mgmt */ + mtdcr isram0_pmeg,r1 + + lis r1,0x8000 /* BAS = 8000_0000 */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) + ori r1,r1,0x0980 /* first 64k */ + mtdcr isram0_sb0cr,r1 + lis r1,0x8001 + ori r1,r1,0x0980 /* second 64k */ + mtdcr isram0_sb1cr,r1 + lis r1, 0x8002 + ori r1,r1, 0x0980 /* third 64k */ + mtdcr isram0_sb2cr,r1 + lis r1, 0x8003 + ori r1,r1, 0x0980 /* fourth 64k */ + mtdcr isram0_sb3cr,r1 +#else + ori r1,r1,0x0380 /* 8k rw */ + mtdcr isram0_sb0cr,r1 +#endif +#endif + + /*----------------------------------------------------------------*/ + /* Setup the stack in internal SRAM */ + /*----------------------------------------------------------------*/ + lis r1,CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET@l + li r0,0 + stwu r0,-4(r1) + stwu r0,-4(r1) /* Terminate call chain */ + + stwu r1,-8(r1) /* Save back chain and move SP */ + lis r0,RESET_VECTOR@h /* Address of reset vector */ + ori r0,r0, RESET_VECTOR@l + stwu r1,-8(r1) /* Save back chain and move SP */ + stw r0,+12(r1) /* Save return addr (underflow vect) */ + + GET_GOT + + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + bl board_init_f + +#endif /* CONFIG_440 */ + +/*****************************************************************************/ +#ifdef CONFIG_IOP480 + /*----------------------------------------------------------------------- */ + /* Set up some machine state registers. */ + /*----------------------------------------------------------------------- */ + addi r0,r0,0x0000 /* initialize r0 to zero */ + mtspr esr,r0 /* clear Exception Syndrome Reg */ + mttcr r0 /* timer control register */ + mtexier r0 /* disable all interrupts */ + addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */ + oris r4,r4,0x2 /* set CE bit (Critical Exceptions) */ + mtmsr r4 /* change MSR */ + addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ + ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ + mtdbsr r4 /* clear/reset the dbsr */ + mtexisr r4 /* clear all pending interrupts */ + addis r4,r0,0x8000 + mtexier r4 /* enable critical exceptions */ + addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ + ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ + mtiocr r4 /* since bit not used) & DRC to latch */ + /* data bus on rising edge of CAS */ + /*----------------------------------------------------------------------- */ + /* Clear XER. */ + /*----------------------------------------------------------------------- */ + mtxer r0 + /*----------------------------------------------------------------------- */ + /* Invalidate i-cache and d-cache TAG arrays. */ + /*----------------------------------------------------------------------- */ + addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ + addi r4,0,1024 /* 1/4 of I-cache */ +..cloop: + iccci 0,r3 + iccci r4,r3 + dccci 0,r3 + addic. r3,r3,-16 /* move back one cache line */ + bne ..cloop /* loop back to do rest until r3 = 0 */ + + /* */ + /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ + /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ + /* */ + + /* first copy IOP480 register base address into r3 */ + addis r3,0,0x5000 /* IOP480 register base address hi */ +/* ori r3,r3,0x0000 / IOP480 register base address lo */ + +#ifdef CONFIG_ADCIOP + /* use r4 as the working variable */ + /* turn on CS3 (LOCCTL.7) */ + lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ + andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ + stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ +#endif + +#ifdef CONFIG_DASA_SIM + /* use r4 as the working variable */ + /* turn on MA17 (LOCCTL.7) */ + lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ + ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ + stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ +#endif + + /* turn on MA16..13 (LCS0BRD.12 = 0) */ + lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ + andi. r4,r4,0xefff /* make bit 12 = 0 */ + stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ + + /* make sure above stores all comlete before going on */ + sync + + /* last thing, set local init status done bit (DEVINIT.31) */ + lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ + oris r4,r4,0x8000 /* make bit 31 = 1 */ + stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ + + /* clear all pending interrupts and disable all interrupts */ + li r4,-1 /* set p1 to 0xffffffff */ + stw r4,0x1b0(r3) /* clear all pending interrupts */ + stw r4,0x1b8(r3) /* clear all pending interrupts */ + li r4,0 /* set r4 to 0 */ + stw r4,0x1b4(r3) /* disable all interrupts */ + stw r4,0x1bc(r3) /* disable all interrupts */ + + /* make sure above stores all comlete before going on */ + sync + + /*----------------------------------------------------------------------- */ + /* Enable two 128MB cachable regions. */ + /*----------------------------------------------------------------------- */ + addis r1,r0,0x8000 + addi r1,r1,0x0001 + mticcr r1 /* instruction cache */ + + addis r1,r0,0x0000 + addi r1,r1,0x0000 + mtdccr r1 /* data cache */ + + addis r1,r0,CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + GET_GOT /* initialize GOT access */ + + bl board_init_f /* run first part of init code (from Flash) */ + +#endif /* CONFIG_IOP480 */ + +/*****************************************************************************/ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP) + /*----------------------------------------------------------------------- */ + /* Clear and set up some registers. */ + /*----------------------------------------------------------------------- */ + addi r4,r0,0x0000 + mtspr sgr,r4 + mtspr dcwr,r4 + mtesr r4 /* clear Exception Syndrome Reg */ + mttcr r4 /* clear Timer Control Reg */ + mtxer r4 /* clear Fixed-Point Exception Reg */ + mtevpr r4 /* clear Exception Vector Prefix Reg */ + addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */ + oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */ + mtmsr r4 /* change MSR */ + addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ + /* dbsr is cleared by setting bits to 1) */ + mtdbsr r4 /* clear/reset the dbsr */ + + /*----------------------------------------------------------------------- */ + /* Invalidate I and D caches. Enable I cache for defined memory regions */ + /* to speed things up. Leave the D cache disabled for now. It will be */ + /* enabled/left disabled later based on user selected menu options. */ + /* Be aware that the I cache may be disabled later based on the menu */ + /* options as well. See miscLib/main.c. */ + /*----------------------------------------------------------------------- */ + bl invalidate_icache + bl invalidate_dcache + + /*----------------------------------------------------------------------- */ + /* Enable two 128MB cachable regions. */ + /*----------------------------------------------------------------------- */ + addis r4,r0,0x8000 + addi r4,r4,0x0001 + mticcr r4 /* instruction cache */ + isync + + addis r4,r0,0x0000 + addi r4,r4,0x0000 + mtdccr r4 /* data cache */ + +#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) + /*----------------------------------------------------------------------- */ + /* Tune the speed and size for flash CS0 */ + /*----------------------------------------------------------------------- */ + bl ext_bus_cntlr_init +#endif + +#if defined(CONFIG_405EP) + /*----------------------------------------------------------------------- */ + /* DMA Status, clear to come up clean */ + /*----------------------------------------------------------------------- */ + addis r3,r0, 0xFFFF /* Clear all existing DMA status */ + ori r3,r3, 0xFFFF + mtdcr dmasr, r3 + + bl ppc405ep_init /* do ppc405ep specific init */ +#endif /* CONFIG_405EP */ + +#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) + /******************************************************************** + * Setup OCM - On Chip Memory + *******************************************************************/ + /* Setup OCM */ + lis r0, 0x7FFF + ori r0, r0, 0xFFFF + mfdcr r3, ocmiscntl /* get instr-side IRAM config */ + mfdcr r4, ocmdscntl /* get data-side IRAM config */ + and r3, r3, r0 /* disable data-side IRAM */ + and r4, r4, r0 /* disable data-side IRAM */ + mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ + mtdcr ocmdscntl, r4 /* set data-side IRAM config */ + isync + + addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */ + mtdcr ocmdsarc, r3 + addis r4, 0, 0xC000 /* OCM data area enabled */ + mtdcr ocmdscntl, r4 + isync +#endif + + /*----------------------------------------------------------------------- */ + /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ + /*----------------------------------------------------------------------- */ +#ifdef CFG_INIT_DCACHE_CS + /*----------------------------------------------------------------------- */ + /* Memory Bank x (nothingness) initialization 1GB+64MEG */ + /* used as temporary stack pointer for stage0 */ + /*----------------------------------------------------------------------- */ + li r4,PBxAP + mtdcr ebccfga,r4 + lis r4,0x0380 + ori r4,r4,0x0480 + mtdcr ebccfgd,r4 + + addi r4,0,PBxCR + mtdcr ebccfga,r4 + lis r4,0x400D + ori r4,r4,0xa000 + mtdcr ebccfgd,r4 + + /* turn on data chache for this region */ + lis r4,0x0080 + mtdccr r4 + + /* set stack pointer and clear stack to known value */ + + lis r1,CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET@l + + li r4,2048 /* we store 2048 words to stack */ + mtctr r4 + + lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */ + ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */ + + lis r4,0xdead /* we store 0xdeaddead in the stack */ + ori r4,r4,0xdead + +..stackloop: + stwu r4,-4(r2) + bdnz ..stackloop + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Set up a dummy frame to store reset vector as return address. + * this causes stack underflow to reset board. + */ + stwu r1, -8(r1) /* Save back chain and move SP */ + addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ + ori r0, r0, RESET_VECTOR@l + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save return addr (underflow vect) */ + +#elif defined(CFG_TEMP_STACK_OCM) && \ + (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)) + /* + * Stack in OCM. + */ + + /* Set up Stack at top of OCM */ + lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l + + /* Set up a zeroized stack frame so that backtrace works right */ + li r0, 0 + stwu r0, -4(r1) + stwu r0, -4(r1) + + /* + * Set up a dummy frame to store reset vector as return address. + * this causes stack underflow to reset board. + */ + stwu r1, -8(r1) /* Save back chain and move SP */ + lis r0, RESET_VECTOR@h /* Address of reset vector */ + ori r0, r0, RESET_VECTOR@l + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save return addr (underflow vect) */ +#endif /* CFG_INIT_DCACHE_CS */ + + /*----------------------------------------------------------------------- */ + /* Initialize SDRAM Controller */ + /*----------------------------------------------------------------------- */ + bl sdram_init + + /* + * Setup temporary stack pointer only for boards + * that do not use SDRAM SPD I2C stuff since it + * is already initialized to use DCACHE or OCM + * stacks. + */ +#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) + lis r1, CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Set up a dummy frame to store reset vector as return address. + * this causes stack underflow to reset board. + */ + stwu r1, -8(r1) /* Save back chain and move SP */ + lis r0, RESET_VECTOR@h /* Address of reset vector */ + ori r0, r0, RESET_VECTOR@l + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save return addr (underflow vect) */ +#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ + + GET_GOT /* initialize GOT access */ + + bl cpu_init_f /* run low-level CPU init code (from Flash) */ + + /* NEVER RETURNS! */ + bl board_init_f /* run first part of init code (from Flash) */ + +#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ + /*----------------------------------------------------------------------- */ + + +/*****************************************************************************/ + .globl _start_of_vectors +_start_of_vectors: + +#if 0 +/*TODO Fixup _start above so we can do this*/ +/* Critical input. */ + CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException) +#endif + +/* Machine check */ + CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + /* No FPU on MPC8xx. This exception is not supposed to happen. + */ + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + /* On the MPC8xx, this is a software emulation interrupt. It occurs + * for all unimplemented and illegal instructions. + */ + STD_EXCEPTION(0x1000, PIT, PITException) + + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) + STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) + STD_EXCEPTION(0x1400, DataTLBError, UnknownException) + + STD_EXCEPTION(0x1500, Reserved5, UnknownException) + STD_EXCEPTION(0x1600, Reserved6, UnknownException) + STD_EXCEPTION(0x1700, Reserved7, UnknownException) + STD_EXCEPTION(0x1800, Reserved8, UnknownException) + STD_EXCEPTION(0x1900, Reserved9, UnknownException) + STD_EXCEPTION(0x1a00, ReservedA, UnknownException) + STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + + STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) + STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) + STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) + STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) + + CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) + + .globl _end_of_vectors +_end_of_vectors: + + + . = 0x2100 + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) +#if 0 + andi. r23,r23,MSR_PR + mfspr r23,SPRG3 /* if from user, fix up tss.regs */ + beq 2f + addi r24,r1,STACK_FRAME_OVERHEAD + stw r24,PT_REGS(r23) +2: addi r2,r23,-TSS /* set r2 to current */ + tovirt(r2,r2,r23) +#endif + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ +#if 0 + addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */ + cmplw 0,r1,r2 + cmplw 1,r1,r24 + crand 1,1,4 + bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */ +#endif + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +crit_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr 990,r2 /* SRR2 */ + mtspr 991,r0 /* SRR3 */ + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfci + +/* Cache functions. +*/ +invalidate_icache: + iccci r0,r0 /* for 405, iccci invalidates the */ + blr /* entire I cache */ + +invalidate_dcache: + addi r6,0,0x0000 /* clear GPR 6 */ + /* Do loop for # of dcache congruence classes. */ + lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ + ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l + /* NOTE: dccci invalidates both */ + mtctr r7 /* ways in the D cache */ +..dcloop: + dccci 0,r6 /* invalidate line */ + addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */ + bdnz ..dcloop + blr + +flush_dcache: + addis r9,r0,0x0002 /* set mask for EE and CE msr bits */ + ori r9,r9,0x8000 + mfmsr r12 /* save msr */ + andc r9,r12,r9 + mtmsr r9 /* disable EE and CE */ + addi r10,r0,0x0001 /* enable data cache for unused memory */ + mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */ + or r10,r10,r9 /* bit 31 in dccr */ + mtdccr r10 + + /* do loop for # of congruence classes. */ + lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */ + ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l + lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */ + ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */ + mtctr r10 + addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */ + add r11,r10,r11 /* add to get to other side of cache line */ +..flush_dcache_loop: + lwz r3,0(r10) /* least recently used side */ + lwz r3,0(r11) /* the other side */ + dccci r0,r11 /* invalidate both sides */ + addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */ + addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */ + bdnz ..flush_dcache_loop + sync /* allow memory access to complete */ + mtdccr r9 /* restore dccr */ + mtmsr r12 /* restore msr */ + blr + + .globl icache_enable +icache_enable: + mflr r8 + bl invalidate_icache + mtlr r8 + isync + addis r3,r0, 0x8000 /* set bit 0 */ + mticcr r3 + blr + + .globl icache_disable +icache_disable: + addis r3,r0, 0x0000 /* clear bit 0 */ + mticcr r3 + isync + blr + + .globl icache_status +icache_status: + mficcr r3 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl dcache_enable +dcache_enable: + mflr r8 + bl invalidate_dcache + mtlr r8 + isync + addis r3,r0, 0x8000 /* set bit 0 */ + mtdccr r3 + blr + + .globl dcache_disable +dcache_disable: + mflr r8 + bl flush_dcache + mtlr r8 + addis r3,r0, 0x0000 /* clear bit 0 */ + mtdccr r3 + blr + + .globl dcache_status +dcache_status: + mfdccr r3 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +#if !defined(CONFIG_440) + .globl wr_pit +wr_pit: + mtspr pit, r3 + blr +#endif + + .globl wr_tcr +wr_tcr: + mtspr tcr, r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16 */ +/* Description: Output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16 +out16: + sth r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16r */ +/* Description: Byte reverse and output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16r +out16r: + sthbrx r4,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32r */ +/* Description: Byte reverse and output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32r +out32r: + stwbrx r4,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16 */ +/* Description: Input 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl in16 +in16: + lhz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16r */ +/* Description: Input 16 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in16r +in16r: + lhbrx r3,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0x0000(3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32r */ +/* Description: Input 32 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in32r +in32r: + lwbrx r3,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcSync */ +/* Description: Processor Synchronize */ +/* Input: none. */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcSync +ppcSync: + sync + blr + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + dccci 0,0 /* Invalidate data cache, now no longer our stack */ + sync + addi r1,r0,0x0000 /* TLB entry #0 */ + tlbre r0,r1,0x0002 /* Read contents */ + ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ + tlbwe r0,r1,0x0002 /* Save it out */ + isync +#endif + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Init Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* the the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr /* NEVER RETURNS! */ + +in_ram: + + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + + mr r3, r9 /* Init Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr + + +/**************************************************************************/ +/* PPC405EP specific stuff */ +/**************************************************************************/ +#ifdef CONFIG_405EP +ppc405ep_init: + +#ifdef CONFIG_BUBINGA + /* + * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate + * function) to support FPGA and NVRAM accesses below. + */ + + lis r3,GPIO0_OSRH@h /* config GPIO output select */ + ori r3,r3,GPIO0_OSRH@l + lis r4,CFG_GPIO0_OSRH@h + ori r4,r4,CFG_GPIO0_OSRH@l + stw r4,0(r3) + lis r3,GPIO0_OSRL@h + ori r3,r3,GPIO0_OSRL@l + lis r4,CFG_GPIO0_OSRL@h + ori r4,r4,CFG_GPIO0_OSRL@l + stw r4,0(r3) + + lis r3,GPIO0_ISR1H@h /* config GPIO input select */ + ori r3,r3,GPIO0_ISR1H@l + lis r4,CFG_GPIO0_ISR1H@h + ori r4,r4,CFG_GPIO0_ISR1H@l + stw r4,0(r3) + lis r3,GPIO0_ISR1L@h + ori r3,r3,GPIO0_ISR1L@l + lis r4,CFG_GPIO0_ISR1L@h + ori r4,r4,CFG_GPIO0_ISR1L@l + stw r4,0(r3) + + lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ + ori r3,r3,GPIO0_TSRH@l + lis r4,CFG_GPIO0_TSRH@h + ori r4,r4,CFG_GPIO0_TSRH@l + stw r4,0(r3) + lis r3,GPIO0_TSRL@h + ori r3,r3,GPIO0_TSRL@l + lis r4,CFG_GPIO0_TSRL@h + ori r4,r4,CFG_GPIO0_TSRL@l + stw r4,0(r3) + + lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ + ori r3,r3,GPIO0_TCR@l + lis r4,CFG_GPIO0_TCR@h + ori r4,r4,CFG_GPIO0_TCR@l + stw r4,0(r3) + + li r3,pb1ap /* program EBC bank 1 for RTC access */ + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB1AP@h + ori r3,r3,CFG_EBC_PB1AP@l + mtdcr ebccfgd,r3 + li r3,pb1cr + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB1CR@h + ori r3,r3,CFG_EBC_PB1CR@l + mtdcr ebccfgd,r3 + + li r3,pb1ap /* program EBC bank 1 for RTC access */ + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB1AP@h + ori r3,r3,CFG_EBC_PB1AP@l + mtdcr ebccfgd,r3 + li r3,pb1cr + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB1CR@h + ori r3,r3,CFG_EBC_PB1CR@l + mtdcr ebccfgd,r3 + + li r3,pb4ap /* program EBC bank 4 for FPGA access */ + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB4AP@h + ori r3,r3,CFG_EBC_PB4AP@l + mtdcr ebccfgd,r3 + li r3,pb4cr + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB4CR@h + ori r3,r3,CFG_EBC_PB4CR@l + mtdcr ebccfgd,r3 +#endif + + addi r3,0,CPC0_PCI_HOST_CFG_EN +#ifdef CONFIG_BUBINGA + /* + !----------------------------------------------------------------------- + ! Check FPGA for PCI internal/external arbitration + ! If board is set to internal arbitration, update cpc0_pci + !----------------------------------------------------------------------- + */ + addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */ + ori r5,r5,FPGA_REG1@l + lbz r5,0x0(r5) /* read to get PCI arb selection */ + andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/ + beq ..pci_cfg_set /* if not set, then bypass reg write*/ +#endif + ori r3,r3,CPC0_PCI_ARBIT_EN +..pci_cfg_set: + mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/ + + /* + !----------------------------------------------------------------------- + ! Check to see if chip is in bypass mode. + ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a + ! CPU reset Otherwise, skip this step and keep going. + ! Note: Running BIOS in bypass mode is not supported since PLB speed + ! will not be fast enough for the SDRAM (min 66MHz) + !----------------------------------------------------------------------- + */ + mfdcr r5, CPC0_PLLMR1 + rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ + cmpi cr0,0,r4,0x1 + + beq pll_done /* if SSCS =b'1' then PLL has */ + /* already been set */ + /* and CPU has been reset */ + /* so skip to next section */ + +#ifdef CONFIG_BUBINGA + /* + !----------------------------------------------------------------------- + ! Read NVRAM to get value to write in PLLMR. + ! If value has not been correctly saved, write default value + ! Default config values (assuming on-board 33MHz SYS_CLK) are above. + ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. + ! + ! WARNING: This code assumes the first three words in the nvram_t + ! structure in openbios.h. Changing the beginning of + ! the structure will break this code. + ! + !----------------------------------------------------------------------- + */ + addis r3,0,NVRAM_BASE@h + addi r3,r3,NVRAM_BASE@l + + lwz r4, 0(r3) + addis r5,0,NVRVFY1@h + addi r5,r5,NVRVFY1@l + cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ + bne ..no_pllset + addi r3,r3,4 + lwz r4, 0(r3) + addis r5,0,NVRVFY2@h + addi r5,r5,NVRVFY2@l + cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ + bne ..no_pllset + addi r3,r3,8 /* Skip over conf_size */ + lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ + lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ + rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ + cmpi cr0,0,r5,1 /* See if PLL is locked */ + beq pll_write +..no_pllset: +#endif /* CONFIG_BUBINGA */ + + addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ + ori r3,r3,PLLMR0_DEFAULT@l /* */ + addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ + ori r4,r4,PLLMR1_DEFAULT@l /* */ + + b pll_write /* Write the CPC0_PLLMR with new value */ + +pll_done: + /* + !----------------------------------------------------------------------- + ! Clear Soft Reset Register + ! This is needed to enable PCI if not booting from serial EPROM + !----------------------------------------------------------------------- + */ + addi r3, 0, 0x0 + mtdcr CPC0_SRR, r3 + + addis r3,0,0x0010 + mtctr r3 +pci_wait: + bdnz pci_wait + + blr /* return to main code */ + +/* +!----------------------------------------------------------------------------- +! Function: pll_write +! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation +! That is: +! 1. Pll is first disabled (de-activated by putting in bypass mode) +! 2. PLL is reset +! 3. Clock dividers are set while PLL is held in reset and bypassed +! 4. PLL Reset is cleared +! 5. Wait 100us for PLL to lock +! 6. A core reset is performed +! Input: r3 = Value to write to CPC0_PLLMR0 +! Input: r4 = Value to write to CPC0_PLLMR1 +! Output r3 = none +!----------------------------------------------------------------------------- +*/ +pll_write: + mfdcr r5, CPC0_UCR + andis. r5,r5,0xFFFF + ori r5,r5,0x0101 /* Stop the UART clocks */ + mtdcr CPC0_UCR,r5 /* Before changing PLL */ + + mfdcr r5, CPC0_PLLMR1 + rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ + mtdcr CPC0_PLLMR1,r5 + oris r5,r5,0x4000 /* Set PLL Reset */ + mtdcr CPC0_PLLMR1,r5 + + mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ + rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ + oris r5,r5,0x4000 /* Set PLL Reset */ + mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ + rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ + mtdcr CPC0_PLLMR1,r5 + + /* + ! Wait min of 100us for PLL to lock. + ! See CMOS 27E databook for more info. + ! At 200MHz, that means waiting 20,000 instructions + */ + addi r3,0,20000 /* 2000 = 0x4e20 */ + mtctr r3 +pll_wait: + bdnz pll_wait + + oris r5,r5,0x8000 /* Enable PLL */ + mtdcr CPC0_PLLMR1,r5 /* Engage */ + + /* + * Reset CPU to guarantee timings are OK + * Not sure if this is needed... + */ + addis r3,0,0x1000 + mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ + /* execution will continue from the poweron */ + /* vector of 0xfffffffc */ +#endif /* CONFIG_405EP */ diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c new file mode 100644 index 0000000..6aecca2 --- /dev/null +++ b/cpu/ppc4xx/traps.c @@ -0,0 +1,290 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler)(struct pt_regs *) = 0; +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. + */ +#define END_OF_MEM 0x00400000 + + +static __inline__ void set_tsr(unsigned long val) +{ +#if defined(CONFIG_440) + asm volatile("mtspr 0x150, %0" : : "r" (val)); +#else + asm volatile("mttsr %0" : : "r" (val)); +#endif +} + +static __inline__ unsigned long get_esr(void) +{ + unsigned long val; + +#if defined(CONFIG_440) + asm volatile("mfspr %0, 0x03e" : "=r" (val) :); +#else + asm volatile("mfesr %0" : "=r" (val) :); +#endif + return val; +} + +#define ESR_MCI 0x80000000 +#define ESR_PIL 0x08000000 +#define ESR_PPR 0x04000000 +#define ESR_PTR 0x02000000 +#define ESR_DST 0x00800000 +#define ESR_DIZ 0x00400000 +#define ESR_U0F 0x00008000 + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint(struct pt_regs *); +#endif + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + printf("Data parity signal\n"); + break; + case (0x80000000>>15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ + long esr_val; + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + show_regs(regs); + + esr_val = get_esr(); + if( esr_val & ESR_PIL ) + printf( "** Illegal Instruction **\n" ); + else if( esr_val & ESR_PPR ) + printf( "** Privileged Instruction **\n" ); + else if( esr_val & ESR_PTR ) + printf( "** Trap Instruction **\n" ); + + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +PITException(struct pt_regs *regs) +{ + /* + * Reset PIT interrupt + */ + set_tsr(0x08000000); + + /* + * Call timer_interrupt routine in interrupts.c + */ + timer_interrupt(NULL); +} + + +void +UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +void +DebugException(struct pt_regs *regs) +{ + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); +#endif +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int +addr_probe(uint *addr) +{ +#if 0 + int retval; + + __asm__ __volatile__( \ + "1: lwz %0,0(%1)\n" \ + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); + + return (retval); +#endif + return 0; +} diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c new file mode 100644 index 0000000..bb57658 --- /dev/null +++ b/cpu/ppc4xx/usb_ohci.c @@ -0,0 +1,1642 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the PPC440EP. + * + * (C) Copyright 2003-2004 + * Gary Jennejohn, DENX Software Engineering + * + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTES + * 1 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + */ + +#include + +#ifdef CONFIG_USB_OHCI + +#include +#include +#include "usb_ohci.h" + +#include "usbdev.h" + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ +#undef DEBUG +#undef SHOW_INFO +#undef OHCI_FILL_TRACE + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +#define readl(a) (*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) + +#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +#ifdef DEBUG +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) swap_16(x) +#define m32_swap(x) swap_32(x) + +#ifdef CONFIG_440EP +#define ohci_cpu_to_le16(x) (x) +#define ohci_cpu_to_le32(x) (x) +#else +#define ohci_cpu_to_le16(x) swap_16(x) +#define ohci_cpu_to_le32(x) swap_32(x) +#endif + +/* global ohci_t */ +static ohci_t gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +urb_priv_t urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; +/* flag guarding URB transation */ +int urb_finished = 0; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + +static u32 roothub_a (struct ohci *hc) + { return read_roothub (hc, a, 0xfc0fe000); } +static inline u32 roothub_b (struct ohci *hc) + { return readl (&hc->regs->roothub.b); } +static inline u32 roothub_status (struct ohci *hc) + { return readl (&hc->regs->roothub.status); } +static u32 roothub_portstatus (struct ohci *hc, int i) + { return read_roothub (hc, portstatus [i], 0xffe0fce0); } + + +/* forward declaration */ +static int hc_interrupt (void); +static void +td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv (urb_priv_t * urb) +{ + int i; + int last; + struct td * td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +static int sohci_get_current_frame_number (struct usb_device * dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, char * str, int small) +{ + urb_priv_t * purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number (dev), + usb_pipedevice (pipe), + usb_pipeendpoint (pipe), + usb_pipeout (pipe)? 'O': 'I', + usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): + (usb_pipecontrol (pipe)? "CTRL": "BULK"), + purb->actual_length, + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol (pipe)) { + printf (__FILE__ ": cmd(8):"); + for (i = 0; i < 8 ; i++) + printf (" %02x", ((__u8 *) setup) [i]); + printf ("\n"); + } + if (transfer_len > 0 && buffer) { + printf (__FILE__ ": data(%d/%d):", + purb->actual_length, + transfer_len); + len = usb_pipeout (pipe)? + transfer_len: purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf (" %02x", ((__u8 *) buffer) [i]); + printf ("%s\n", i < len? "...": ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ +void ep_print_int_eds (ohci_t *ohci, char * str) { + int i, j; + __u32 * ed_p; + for (i= 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table [i]); + if (*ed_p == 0) + continue; + printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p); + printf (" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf ("\n"); + } +} + +static void ohci_dump_intr_mask (char *label, __u32 mask) +{ + dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds (char *label, __u32 value) +{ + ed_t *edp = (ed_t *)value; + + if (value) { + dbg ("%s %08x", label, value); + dbg ("%08x", edp->hwINFO); + dbg ("%08x", edp->hwTailP); + dbg ("%08x", edp->hwHeadP); + dbg ("%08x", edp->hwNextED); + } +} + +static char * hcfs2string (int state) +{ + switch (state) { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status (ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl (®s->revision) & 0xff; + if (temp != 0x10) + dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl (®s->control); + dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string (temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + + temp = readl (®s->cmdstatus); + dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + + ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); + ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); + + maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); + + maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); + maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); + + maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); + maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); + + maybe_print_eds ("donehead", readl (®s->donehead)); +} + +static void ohci_dump_roothub (ohci_t *controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + + if (verbose) { + dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b (controller); + dbg ("roothub.b: %08x PPCM=%04x DR=%04x", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status (controller); + dbg ("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump (ohci_t *controller, int verbose) +{ + dbg ("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status (controller); + if (verbose) + ep_print_int_eds (controller, "hcca"); + dbg ("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub (controller, 1); +} + + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + ohci_t *ohci; + ed_t * ed; + urb_priv_t *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* if we have an unfinished URB from previous transaction let's + * fail and scream as quickly as possible so as not to corrupt + * further communication */ + if (!urb_finished) { + err("sohci_submit_job: URB NOT FINISHED"); + return -1; + } + /* we're about to begin a new transaction here so mark the URB unfinished */ + urb_finished = 0; + + /* every endpoint has a ed, locate and fill it */ + if (!(ed = ep_add_ed (dev, pipe))) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype (pipe)) { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0)? 2: + (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc (dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv (purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv (purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link (ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number (struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + + return ohci_cpu_to_le16 (ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel (ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel (ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP); + + switch (ed->type) { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_controltail == ed) { + ohci->ed_controltail = ed->ed_prev; + } else { + ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_bulktail == ed) { + ohci->ed_bulktail = ed->ed_prev; + } else { + ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + } + ed->state = ED_UNLINK; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, + * but the USB stack is a little bit stateless so we do it at every transaction + * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK + * in all other cases the state is left unchanged + * the ed info fields are setted anyway even though most of them should not change */ + +static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | + (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc (usb_dev); + ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype (pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe) + | usb_pipeendpoint (pipe) << 7 + | (usb_pipeisoc (pipe)? 0x8000: 0) + | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) + | usb_pipeslow (pipe) << 13 + | usb_maxpacket (usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill (ohci_t *ohci, unsigned int info, + void *data, int len, + struct usb_device *dev, int index, urb_priv_t *urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td [index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32)data; +#ifdef OHCI_FILL_TRACE + if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); + printf("\n"); + } +#endif + if (!len) + data = 0; + + td->hwINFO = ohci_cpu_to_le32 (info); + td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data); + if (data) + td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1)); + else + td->hwBE = 0; + td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ +static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ + if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = 0; + + switch (usb_pipetype (pipe)) { + case PIPE_BULK: + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while(data_len > 4096) { + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill (ohci, info, setup, 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout (pipe)? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill (ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill (ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(td_t * td) +{ + __u32 tdINFO, tdBE, tdCBP; + urb_priv_t *lurb_priv = &urb_priv; + + tdINFO = ohci_cpu_to_le32 (td->hwINFO); + tdBE = ohci_cpu_to_le32 (td->hwBE); + tdCBP = ohci_cpu_to_le32 (td->hwCBP); + + + if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && + ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { + if (tdBE != 0) { + if (td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ + +static td_t * dl_reverse_done_list (ohci_t *ohci) +{ + __u32 td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + urb_priv_t *lurb_priv = NULL; + + td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0; + ohci->hcca->done_head = 0; + + while (td_list_hc) { + td_list = (td_t *)td_list_hc; + + if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) { + lurb_priv = &urb_priv; + dbg(" USB-error/status: %x : %p", + TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list); + if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) { + if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { + td_list->ed->hwHeadP = + (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) | + (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2)); + lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; + } else + td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); + } +#ifdef CONFIG_MPC5200 + td_list->hwNextTD = 0; +#endif + } + + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0; + } + return td_list; +} + +/*-------------------------------------------------------------------------*/ + +/* td done list */ +static int dl_done_list (ohci_t *ohci, td_t *td_list) +{ + td_t *td_list_next = NULL; + ed_t *ed; + int cc = 0; + int stat = 0; + /* urb_t *urb; */ + urb_priv_t *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + + while (td_list) { + td_list_next = td_list->next_dl_td; + + lurb_priv = &urb_priv; + tdINFO = ohci_cpu_to_le32 (td_list->hwINFO); + + ed = td_list->ed; + + dl_transfer_length(td_list); + + /* error code of transfer */ + cc = TD_CC_GET (tdINFO); + if (++(lurb_priv->td_cnt) == lurb_priv->length) { + if ((ed->state & (ED_OPER | ED_UNLINK)) + && (lurb_priv->state != URB_DEL)) { + dbg("ConditionCode %#x", cc); + stat = cc_to_error[cc]; + urb_finished = 1; + } + } + + if (ed->state != ED_NEW) { + edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0; + edTailP = ohci_cpu_to_le32 (ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink (ohci, ed); + } + + td_list = td_list_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + __u32 temp, ndp, i; + int res; + + res = -1; + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && + ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + void * data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u32 datab[4]; + __u8 *data_buf = (__u8 *)datab; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + +#ifdef DEBUG +urb_priv.actual_length = 0; +pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +#endif + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = m16_swap (cmd->value); + wIndex = m16_swap (cmd->index); + wLength = m16_swap (cmd->length); + + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(__u16 *) data_buf = m16_swap (1); OK (2); + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_CLASS: + *(__u32 *) data_buf = m32_swap ( + RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK (4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + OK(0); + case (RH_C_HUB_OVER_CURRENT): + WR_RH_STAT(RH_HS_OCIC); OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_POCI); OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); + case (RH_C_PORT_CONNECTION): + WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); + case (RH_C_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_PESC); OK (0); + case (RH_C_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); + case (RH_C_PORT_OVER_CURRENT): + WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); + case (RH_C_PORT_RESET): + WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); + case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PRS); + OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PES ); + OK (0); + } + break; + + case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; OK(len); + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; OK(len); + case (0x03): /* string descriptors */ + if(wValue==0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if(wValue==0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a (&gohci); + + data_buf [0] = 9; /* min length; */ + data_buf [1] = 0x29; + data_buf [2] = temp & RH_A_NDP; + data_buf [3] = 0; + if (temp & RH_A_PSM) /* per-port power switching? */ + data_buf [3] |= 0x1; + if (temp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf [3] |= 0x10; + else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + data_buf [3] |= 0x8; + + /* corresponds to data_buf[4-7] */ + datab [1] = 0; + data_buf [5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b (&gohci); + data_buf [7] = temp & RH_B_DR; + if (data_buf [2] < 7) { + data_buf [8] = 0xff; + } else { + data_buf [0] += 2; + data_buf [8] = (temp & RH_B_DR) >> 8; + data_buf [10] = data_buf [9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf [0], wLength)); + OK (len); + } + + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); + + case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); + + default: + dbg ("unsupported root hub command"); + stat = USB_ST_STALLED; + } + +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + + len = min_t(int, len, leni); + if (data != data_buf) + memcpy (data, data_buf, len); + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG + if (transfer_len) + urb_priv.actual_length = transfer_len; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); +#endif + + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#endif + if (!maxsize) { + err("submit_common_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { + err("sohci_submit_job failed"); + return -1; + } + + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if (usb_pipetype (pipe) == PIPE_BULK) + timeout = BULK_TO; + else + timeout = 100; + + /* wait for it to complete */ + for (;;) { + /* check whether the controller is done */ + stat = hc_interrupt(); + if (stat < 0) { + stat = USB_ST_CRC_ERR; + break; + } + + /* NOTE: since we are not interrupt driven in U-Boot and always + * handle only one URB at a time, we cannot assume the + * transaction finished on the first successful return from + * hc_interrupt().. unless the flag for current URB is set, + * meaning that all TD's to/from device got actually + * transferred and processed. If the current URB is not + * finished we need to re-iterate this loop so as + * hc_interrupt() gets called again as there needs to be some + * more TD's to process still */ + if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { + /* 0xff is returned for an SF-interrupt */ + break; + } + + if (--timeout) { + wait_ms(1); + if (!urb_finished) + dbg("\%"); + + } else { + err("CTL:TIMEOUT "); + dbg("submit_common_msg: TO status %x\n", stat); + stat = USB_ST_CRC_ERR; + urb_finished = 1; + break; + } + } +#if 0 + /* we got an Root Hub Status Change interrupt */ + if (got_rhsc) { +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + got_rhsc = 0; + /* abuse timeout */ + timeout = rh_check_port_status(&gohci); + if (timeout >= 0) { +#if 0 /* this does nothing useful, but leave it here in case that changes */ + /* the called routine adds 1 to the passed value */ + usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); +#endif + /* + * XXX + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } +#endif + + dev->status = stat; + dev->act_len = transfer_len; + +#ifdef DEBUG + pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); +#endif + + /* free TDs in urb_priv */ + urb_free_priv (&urb_priv); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + + info("submit_control_msg"); +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#endif + if (!maxsize) { + err("submit_control_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset (ohci_t *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ + writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ + info("USB HC TakeOver from SMM"); + while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { + wait_ms (10); + if (--smm_timeout == 0) { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", + ohci->slot_name, + readl (&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + ohci->hc_control = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel (OHCI_HCR, &ohci->regs->cmdstatus); + while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { + if (--timeout == 0) { + err("USB HC reset timed out!"); + return -1; + } + udelay (1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start (ohci_t * ohci) +{ + __u32 mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + + writel (0, &ohci->regs->ed_controlhead); + writel (0, &ohci->regs->ed_bulkhead); + + writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + + fminterval = 0x2edf; + writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel (fminterval, &ohci->regs->fminterval); + writel (0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel (mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel (mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel (mask, &ohci->regs->intrenable); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, + &ohci->regs->roothub.a); + writel (RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay ((roothub_a (ohci) >> 23) & 0x1fe); + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static int +hc_interrupt (void) +{ + ohci_t *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + if ((ohci->hcca->done_head != 0) && + !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { + + ints = OHCI_INTR_WDH; + + } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { + ohci->disabled++; + err ("%s device removed!", ohci->slot_name); + return -1; + + } else if ((ints &= readl (®s->intrenable)) == 0) { + dbg("hc_interrupt: returning..\n"); + return 0xff; + } + + /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ + + if (ints & OHCI_INTR_RHSC) { + got_rhsc = 1; + stat = 0xff; + } + + if (ints & OHCI_INTR_UE) { + ohci->disabled++; + err ("OHCI Unrecoverable Error, controller usb-%s disabled", + ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ + +#ifdef DEBUG + ohci_dump (ohci, 1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset (ohci); + return -1; + } + + if (ints & OHCI_INTR_WDH) { + writel (OHCI_INTR_WDH, ®s->intrdisable); + stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); + writel (OHCI_INTR_WDH, ®s->intrenable); + } + + if (ints & OHCI_INTR_SO) { + dbg("USB Schedule overrun\n"); + writel (OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) { + unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; + wait_ms(1); + writel (OHCI_INTR_SF, ®s->intrdisable); + if (ohci->ed_rm_list[frame] != NULL) + writel (OHCI_INTR_SF, ®s->intrenable); + stat = 0xff; + } + + writel (ints, ®s->intrstatus); + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci (ohci_t *ohci) +{ + dbg ("USB HC release ohci usb-%s", ohci->slot_name); + + if (!ohci->disabled) + hc_reset (ohci); +} + +/*-------------------------------------------------------------------------*/ + +/* + * low level initalisation routine, called from usb.c + */ +static char ohci_inited = 0; + +int usb_lowlevel_init(void) +{ + memset (&gohci, 0, sizeof (ohci_t)); + memset (&urb_priv, 0, sizeof (urb_priv_t)); + + /* align the storage */ + if ((__u32)&ghcca[0] & 0xff) { + err("HCCA not aligned!!"); + return -1; + } + phcca = &ghcca[0]; + info("aligned ghcca %p", phcca); + memset(&ohci_dev, 0, sizeof(struct ohci_device)); + if ((__u32)&ohci_dev.ed[0] & 0x7) { + err("EDs not aligned!!"); + return -1; + } + memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); + if ((__u32)gtd & 0x7) { + err("TDs not aligned!!"); + return -1; + } + ptd = gtd; + gohci.hcca = phcca; + memset (phcca, 0, sizeof (struct ohci_hcca)); + + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); + + gohci.flags = 0; + gohci.slot_name = "ppc440"; + + if (hc_reset (&gohci) < 0) { + hc_release_ohci (&gohci); + return -1; + } + + if (hc_start (&gohci) < 0) { + err ("can't start usb-%s", gohci.slot_name); + hc_release_ohci (&gohci); + return -1; + } + +#ifdef DEBUG + ohci_dump (&gohci, 1); +#endif + ohci_inited = 1; + urb_finished = 1; + + /* init the device driver */ + usb_dev_init(); + + return 0; +} + +int usb_lowlevel_stop(void) +{ + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if (!ohci_inited) + return 0; + /* TODO release any interrupts, etc. */ + /* call hc_release_ohci() here ? */ + hc_reset (&gohci); + return 0; +} + +#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/ppc4xx/usb_ohci.h b/cpu/ppc4xx/usb_ohci.h new file mode 100644 index 0000000..706e05e --- /dev/null +++ b/cpu/ppc4xx/usb_ohci.h @@ -0,0 +1,410 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +/* ED States */ + +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute((aligned(16))); +typedef struct ed ed_t; + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u16 hwPSW[MAXPSW]; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ +#if defined(CONFIG_MPC5200) + __u16 pad1; /* set to 0 on each frame_no change */ + __u16 frame_no; /* current frame number */ +#else + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ +#endif + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute((aligned(256))); + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute((aligned(32))); + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status */ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct { + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + +typedef struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma; */ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +td_t gtd[NUM_TD + 1]; +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td *td_alloc(struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) { + if (ptd[i].usb_dev == NULL) { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void ed_free(struct ed *ed) +{ + ed->usb_dev = NULL; +} diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c new file mode 100644 index 0000000..8262c54 --- /dev/null +++ b/cpu/ppc4xx/usbdev.c @@ -0,0 +1,214 @@ +/*USB 1.1,2.0 device*/ + +#include +#include + +#ifdef CONFIG_440EP + +#include +#include "usbdev.h" +#include "vecnum.h" + +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 + +int set_value = -1; + +void process_endpoints(unsigned short usb2d0_intrin) +{ + /*will hold the packet received */ + struct usb_device_descriptor usb_device_packet; + struct usb_config_descriptor usb_config_packet; + struct usb_string_descriptor usb_string_packet; + struct devrequest setup_packet; + unsigned int *setup_packet_pt; + unsigned char *packet_pt = NULL; + int temp, temp1; + + int i; + + /*printf("{USB device} - endpoint 0x%X \n", usb2d0_intrin); */ + + /*set usb address, seems to not work unless it is done in the next + interrupt, so that is why it is done this way */ + if (set_value != -1) + *(unsigned char *)USB2D0_FADDR_8 = (unsigned char)set_value; + + /*endpoint 1 */ + if (usb2d0_intrin & 0x01) { + setup_packet_pt = (unsigned int *)&setup_packet; + + /*copy packet */ + setup_packet_pt[0] = *(unsigned int *)USB2D0_FIFO_0; + setup_packet_pt[1] = *(unsigned int *)USB2D0_FIFO_0; + temp = *(unsigned int *)USB2D0_FIFO_0; + temp1 = *(unsigned int *)USB2D0_FIFO_0; + + /*do some swapping */ + setup_packet.value = swap_16(setup_packet.value); + setup_packet.index = swap_16(setup_packet.index); + setup_packet.length = swap_16(setup_packet.length); + + /*clear rx packet */ + *(unsigned short *)USB2D0_INCSR0_8 = 0x48; + + /*printf("0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", setup_packet.requesttype, + setup_packet.request, setup_packet.value, + setup_packet.index, setup_packet.length, temp, temp1 ); */ + + switch (setup_packet.request) { + case USB_REQ_GET_DESCRIPTOR: + + switch (setup_packet.value >> 8) { + case USB_DT_DEVICE: + /*create packet */ + usb_device_packet.bLength = 18; + usb_device_packet.bDescriptorType = + USB_DT_DEVICE; +#ifdef USB_2_0_DEVICE + usb_device_packet.bcdUSB = swap_16(0x200); +#else + usb_device_packet.bcdUSB = swap_16(0x110); +#endif + usb_device_packet.bDeviceClass = 0xff; + usb_device_packet.bDeviceSubClass = 0; + usb_device_packet.bDeviceProtocol = 0; + usb_device_packet.bMaxPacketSize0 = 32; + usb_device_packet.idVendor = swap_16(1); + usb_device_packet.idProduct = swap_16(2); + usb_device_packet.bcdDevice = swap_16(0x300); + usb_device_packet.iManufacturer = 1; + usb_device_packet.iProduct = 1; + usb_device_packet.iSerialNumber = 1; + usb_device_packet.bNumConfigurations = 1; + + /*put packet in fifo */ + packet_pt = (unsigned char *)&usb_device_packet; + break; + + case USB_DT_CONFIG: + /*create packet */ + usb_config_packet.bLength = 9; + usb_config_packet.bDescriptorType = + USB_DT_CONFIG; + usb_config_packet.wTotalLength = swap_16(25); + usb_config_packet.bNumInterfaces = 1; + usb_config_packet.bConfigurationValue = 1; + usb_config_packet.iConfiguration = 0; + usb_config_packet.bmAttributes = 0x40; + usb_config_packet.MaxPower = 0; + + /*put packet in fifo */ + packet_pt = (unsigned char *)&usb_config_packet; + break; + + case USB_DT_STRING: + /*create packet */ + usb_string_packet.bLength = 2; + usb_string_packet.bDescriptorType = + USB_DT_STRING; + usb_string_packet.wData[0] = 0x0094; + + /*put packet in fifo */ + packet_pt = (unsigned char *)&usb_string_packet; + break; + } + + /*put packet in fifo */ + for (i = 0; i < (setup_packet.length); i++) { + *(unsigned char *)USB2D0_FIFO_0 = packet_pt[i]; + } + + /*give tx command */ + *(unsigned short *)USB2D0_INCSR0_8 = 0x0a; + + break; + + case USB_REQ_SET_ADDRESS: + + /*copy usb address */ + set_value = setup_packet.value; + + break; + } + + } +} + +void process_other(unsigned char usb2d0_intrusb) +{ + + /*check for sof */ + if (usb2d0_intrusb & 0x08) { + /*printf("{USB device} - sof detected\n"); */ + } + + /*check for reset */ + if (usb2d0_intrusb & 0x04) { + /*printf("{USB device} - reset detected\n"); */ + + /*copy usb address of zero, need to do this when usb reset */ + set_value = 0; + } + + if (usb2d0_intrusb & 0x02) { + /*printf("{USB device} - resume detected\n"); */ + } + + if (usb2d0_intrusb & 0x01) { + /*printf("{USB device} - suspend detected\n"); */ + } +} + +int usbInt(void) +{ + /*Must read these 2 registers and use values to clear interrupts. If you + do not read them then the interrupt will not be cleared. If you do not + use the variable the optimizer will not do a read. */ + volatile unsigned short usb2d0_intrin = + *(unsigned short *)USB2D0_INTRIN_16; + volatile unsigned char usb2d0_intrusb = + *(unsigned char *)USB2D0_INTRUSB_8; + + /*check if there was an endpoint interrupt */ + if (usb2d0_intrin != 0) { + process_endpoints(usb2d0_intrin); + } + + /*check for other interrupts */ + if (usb2d0_intrusb != 0) { + process_other(usb2d0_intrusb); + } + + return 0; +} + +void usb_dev_init() +{ +#ifdef USB_2_0_DEVICE + printf("USB 2.0 Device init\n"); + /*select 2.0 device */ + mtsdr(sdr_usb0, 0x0); /* 2.0 */ + + /*usb dev init */ + *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */ +#else + printf("USB 1.1 Device init\n"); + /*select 1.1 device */ + mtsdr(sdr_usb0, 0x2); /* 1.1 */ + + /*usb dev init */ + *(unsigned char *)USB2D0_POWER_8 = 0xc0; /* 1.1 */ +#endif + + /*enable interrupts */ + *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f; + + irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt, + NULL); +} + +#endif /*CONFIG_440EP */ diff --git a/cpu/ppc4xx/usbdev.h b/cpu/ppc4xx/usbdev.h new file mode 100644 index 0000000..3446d98 --- /dev/null +++ b/cpu/ppc4xx/usbdev.h @@ -0,0 +1,31 @@ +#include + +/*Common Registers*/ +#define USB2D0_INTRIN_16 (CFG_USB_DEVICE | 0x100) +#define USB2D0_POWER_8 (CFG_USB_DEVICE | 0x102) +#define USB2D0_FADDR_8 (CFG_USB_DEVICE | 0x103) +#define USB2D0_INTRINE_16 (CFG_USB_DEVICE | 0x104) +#define USB2D0_INTROUT_16 (CFG_USB_DEVICE | 0x106) +#define USB2D0_INTRUSBE_8 (CFG_USB_DEVICE | 0x108) +#define USB2D0_INTRUSB_8 (CFG_USB_DEVICE | 0x109) +#define USB2D0_INTROUTE_16 (CFG_USB_DEVICE | 0x10a) +#define USB2D0_TSTMODE_8 (CFG_USB_DEVICE | 0x10c) +#define USB2D0_INDEX_8 (CFG_USB_DEVICE | 0x10d) +#define USB2D0_FRAME_16 (CFG_USB_DEVICE | 0x10e) + +/*Indexed Registers*/ +#define USB2D0_INCSR0_8 (CFG_USB_DEVICE | 0x110) +#define USB2D0_INCSR_16 (CFG_USB_DEVICE | 0x110) +#define USB2D0_INMAXP_16 (CFG_USB_DEVICE | 0x112) +#define USB2D0_OUTCSR_16 (CFG_USB_DEVICE | 0x114) +#define USB2D0_OUTMAXP_16 (CFG_USB_DEVICE | 0x116) +#define USB2D0_OUTCOUNT0_8 (CFG_USB_DEVICE | 0x11a) +#define USB2D0_OUTCOUNT_16 (CFG_USB_DEVICE | 0x11a) + +/*FIFOs*/ +#define USB2D0_FIFO_0 (CFG_USB_DEVICE | 0x120) +#define USB2D0_FIFO_1 (CFG_USB_DEVICE | 0x124) +#define USB2D0_FIFO_2 (CFG_USB_DEVICE | 0x128) +#define USB2D0_FIFO_3 (CFG_USB_DEVICE | 0x12c) + +void usb_dev_init(void); diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h new file mode 100644 index 0000000..cbfe41d --- /dev/null +++ b/cpu/ppc4xx/vecnum.h @@ -0,0 +1,129 @@ +/* +* Copyright (C) 2002 Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +/* + * Interrupt vector number definitions to ease the + * 405 -- 440 porting pain ;-) + * + * NOTE: They're not all here yet ... update as needed. + * + */ + +#ifndef _VECNUMS_H_ +#define _VECNUMS_H_ + +#if defined(CONFIG_440SP) + +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ +#define VECNUM_MS (32 + 1) /* MAL SERR */ +#define VECNUM_TXDE (32 + 2) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 3) /* MAL RXDE */ +#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ +#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ +#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ +#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ + +#elif defined(CONFIG_440) + +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 7 /* PCI MSI level 0 */ +#define VECNUM_MSI1 8 /* PCI MSI level 0 */ +#define VECNUM_MSI2 9 /* PCI MSI level 0 */ +#define VECNUM_MTE 10 /* MAL TXEOB */ +#define VECNUM_MRE 11 /* MAL RXEOB */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_CT0 18 /* GPT compare timer 0 */ +#define VECNUM_CT1 19 /* GPT compare timer 1 */ +#define VECNUM_CT2 20 /* GPT compare timer 2 */ +#define VECNUM_CT3 21 /* GPT compare timer 3 */ +#define VECNUM_CT4 22 /* GPT compare timer 4 */ +#define VECNUM_EIR0 23 /* External interrupt 0 */ +#define VECNUM_EIR1 24 /* External interrupt 1 */ +#define VECNUM_EIR2 25 /* External interrupt 2 */ +#define VECNUM_EIR3 26 /* External interrupt 3 */ +#define VECNUM_EIR4 27 /* External interrupt 4 */ +#define VECNUM_EIR5 28 /* External interrupt 5 */ +#define VECNUM_EIR6 29 /* External interrupt 6 */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 0 ) /* MAL SERR */ +#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ +#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ + +#else /* !defined(CONFIG_440) */ + +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_D0 5 /* DMA channel 0 */ +#define VECNUM_D1 6 /* DMA channel 1 */ +#define VECNUM_D2 7 /* DMA channel 2 */ +#define VECNUM_D3 8 /* DMA channel 3 */ +#define VECNUM_EWU0 9 /* Ethernet wakeup */ +#define VECNUM_MS 10 /* MAL SERR */ +#define VECNUM_MTE 11 /* MAL TXEOB */ +#define VECNUM_MRE 12 /* MAL RXEOB */ +#define VECNUM_TXDE 13 /* MAL TXDE */ +#define VECNUM_RXDE 14 /* MAL RXDE */ +#define VECNUM_ETH0 15 /* Ethernet interrupt status */ +#define VECNUM_EIR0 25 /* External interrupt 0 */ +#define VECNUM_EIR1 26 /* External interrupt 1 */ +#define VECNUM_EIR2 27 /* External interrupt 2 */ +#define VECNUM_EIR3 28 /* External interrupt 3 */ +#define VECNUM_EIR4 29 /* External interrupt 4 */ +#define VECNUM_EIR5 30 /* External interrupt 5 */ +#define VECNUM_EIR6 31 /* External interrupt 6 */ + +#endif /* defined(CONFIG_440) */ + +#endif /* _VECNUMS_H_ */ diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile new file mode 100644 index 0000000..1af53d6 --- /dev/null +++ b/cpu/pxa/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk new file mode 100644 index 0000000..fb810ca --- /dev/null +++ b/cpu/pxa/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +#PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 +PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale +# ========================================================================= +# +# Supply options according to compiler version +# +# ======================================================================== +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c new file mode 100644 index 0000000..d1551dd --- /dev/null +++ b/cpu/pxa/cpu.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#include + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * just disable everything that can disturb booting linux + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~0x1000; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf ("resetting ...\n"); + + udelay (50000); /* wait 50 ms */ + disable_interrupts (); + reset_cpu (0); + + /*NOTREACHED*/ + return (0); +} + +/* taken from blob */ +void icache_enable (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* set i-cache */ + i |= 0x1000; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void icache_disable (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* clear i-cache */ + i &= ~0x1000; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush i-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); +} + +int icache_status (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* return bit */ + return (i & 0x1000); +} + +/* we will never enable dcache, because we have to setup MMU first */ +void dcache_enable (void) +{ + return; +} + +void dcache_disable (void) +{ + return; +} + +int dcache_status (void) +{ + return 0; /* always off */ +} + +void set_GPIO_mode(int gpio_mode) +{ + int gpio = gpio_mode & GPIO_MD_MASK_NR; + int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; + int gafr; + + if (gpio_mode & GPIO_MD_MASK_DIR) + { + GPDR(gpio) |= GPIO_bit(gpio); + } + else + { + GPDR(gpio) &= ~GPIO_bit(gpio); + } + gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); + GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); +} diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c new file mode 100644 index 0000000..b6155b1 --- /dev/null +++ b/cpu/pxa/i2c.c @@ -0,0 +1,464 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2003 Pengutronix e.K. + * Robert Schwebel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. + */ + +/* FIXME: this file is PXA255 specific! What about other XScales? */ + +#include + +#ifdef CONFIG_HARD_I2C + +/* + * - CFG_I2C_SPEED + * - I2C_PXA_SLAVE_ADDR + */ + +#include +#include +#include + +/*#define DEBUG_I2C 1 /###* activate local debugging output */ +#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ +#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) +#define I2C_ISR_INIT 0x7FF + +#ifdef DEBUG_I2C +#define PRINTD(x) printf x +#else +#define PRINTD(x) +#endif + + +/* Shall the current transfer have a start/stop condition? */ +#define I2C_COND_NORMAL 0 +#define I2C_COND_START 1 +#define I2C_COND_STOP 2 + +/* Shall the current transfer be ack/nacked or being waited for it? */ +#define I2C_ACKNAK_WAITACK 1 +#define I2C_ACKNAK_SENDACK 2 +#define I2C_ACKNAK_SENDNAK 4 + +/* Specify who shall transfer the data (master or slave) */ +#define I2C_READ 0 +#define I2C_WRITE 1 + +/* All transfers are described by this data structure */ +struct i2c_msg { + u8 condition; + u8 acknack; + u8 direction; + u8 data; +}; + + +/** + * i2c_pxa_reset: - reset the host controller + * + */ + +static void i2c_reset( void ) +{ + ICR &= ~ICR_IUE; /* disable unit */ + ICR |= ICR_UR; /* reset the unit */ + udelay(100); + ICR &= ~ICR_IUE; /* disable unit */ + CKEN |= CKEN14_I2C; /* set the global I2C clock on */ + ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ + ICR = I2C_ICR_INIT; /* set control register values */ + ISR = I2C_ISR_INIT; /* set clear interrupt bits */ + ICR |= ICR_IUE; /* enable unit */ + udelay(100); +} + + +/** + * i2c_isr_set_cleared: - wait until certain bits of the I2C status register + * are set and cleared + * + * @return: 0 in case of success, 1 means timeout (no match within 10 ms). + */ + +static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) +{ + int timeout = 10000; + + while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){ + udelay( 10 ); + if( timeout-- < 0 ) return 0; + } + + return 1; +} + + +/** + * i2c_transfer: - Transfer one byte over the i2c bus + * + * This function can tranfer a byte over the i2c bus in both directions. + * It is used by the public API functions. + * + * @return: 0: transfer successful + * -1: message is empty + * -2: transmit timeout + * -3: ACK missing + * -4: receive timeout + * -5: illegal parameters + * -6: bus is busy and couldn't be aquired + */ +int i2c_transfer(struct i2c_msg *msg) +{ + int ret; + + if (!msg) + goto transfer_error_msg_empty; + + switch(msg->direction) { + + case I2C_WRITE: + + /* check if bus is not busy */ + if (!i2c_isr_set_cleared(0,ISR_IBB)) + goto transfer_error_bus_busy; + + /* start transmission */ + ICR &= ~ICR_START; + ICR &= ~ICR_STOP; + IDBR = msg->data; + if (msg->condition == I2C_COND_START) ICR |= ICR_START; + if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; + if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; + if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; + ICR &= ~ICR_ALDIE; + ICR |= ICR_TB; + + /* transmit register empty? */ + if (!i2c_isr_set_cleared(ISR_ITE,0)) + goto transfer_error_transmit_timeout; + + /* clear 'transmit empty' state */ + ISR |= ISR_ITE; + + /* wait for ACK from slave */ + if (msg->acknack == I2C_ACKNAK_WAITACK) + if (!i2c_isr_set_cleared(0,ISR_ACKNAK)) + goto transfer_error_ack_missing; + break; + + case I2C_READ: + + /* check if bus is not busy */ + if (!i2c_isr_set_cleared(0,ISR_IBB)) + goto transfer_error_bus_busy; + + /* start receive */ + ICR &= ~ICR_START; + ICR &= ~ICR_STOP; + if (msg->condition == I2C_COND_START) ICR |= ICR_START; + if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; + if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; + if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; + ICR &= ~ICR_ALDIE; + ICR |= ICR_TB; + + /* receive register full? */ + if (!i2c_isr_set_cleared(ISR_IRF,0)) + goto transfer_error_receive_timeout; + + msg->data = IDBR; + + /* clear 'receive empty' state */ + ISR |= ISR_IRF; + + break; + + default: + + goto transfer_error_illegal_param; + + } + + return 0; + +transfer_error_msg_empty: + PRINTD(("i2c_transfer: error: 'msg' is empty\n")); + ret = -1; goto i2c_transfer_finish; + +transfer_error_transmit_timeout: + PRINTD(("i2c_transfer: error: transmit timeout\n")); + ret = -2; goto i2c_transfer_finish; + +transfer_error_ack_missing: + PRINTD(("i2c_transfer: error: ACK missing\n")); + ret = -3; goto i2c_transfer_finish; + +transfer_error_receive_timeout: + PRINTD(("i2c_transfer: error: receive timeout\n")); + ret = -4; goto i2c_transfer_finish; + +transfer_error_illegal_param: + PRINTD(("i2c_transfer: error: illegal parameters\n")); + ret = -5; goto i2c_transfer_finish; + +transfer_error_bus_busy: + PRINTD(("i2c_transfer: error: bus is busy\n")); + ret = -6; goto i2c_transfer_finish; + +i2c_transfer_finish: + PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR)); + i2c_reset(); + return ret; + +} + +/* ------------------------------------------------------------------------ */ +/* API Functions */ +/* ------------------------------------------------------------------------ */ + +void i2c_init(int speed, int slaveaddr) +{ +#ifdef CFG_I2C_INIT_BOARD + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#endif +} + + +/** + * i2c_probe: - Test if a chip answers for a given i2c address + * + * @chip: address of the chip which is searched for + * @return: 0 if a chip was found, -1 otherwhise + */ + +int i2c_probe(uchar chip) +{ + struct i2c_msg msg; + + i2c_reset(); + + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1) + 1; + if (i2c_transfer(&msg)) return -1; + + msg.condition = I2C_COND_STOP; + msg.acknack = I2C_ACKNAK_SENDNAK; + msg.direction = I2C_READ; + msg.data = 0x00; + if (i2c_transfer(&msg)) return -1; + + return 0; +} + + +/** + * i2c_read: - Read multiple bytes from an i2c device + * + * The higher level routines take into account that this function is only + * called with len < page length of the device (see configuration file) + * + * @chip: address of the chip which is to be read + * @addr: i2c data address within the chip + * @alen: length of the i2c data address (1..2 bytes) + * @buffer: where to write the data + * @len: how much byte do we want to read + * @return: 0 in case of success + */ + +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + struct i2c_msg msg; + u8 addr_bytes[3]; /* lowest...highest byte of data address */ + int ret; + + PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); + + i2c_reset(); + + /* dummy chip address write */ + PRINTD(("i2c_read: dummy chip address write\n")); + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1); + msg.data &= 0xFE; + if ((ret=i2c_transfer(&msg))) return -1; + + /* + * send memory address bytes; + * alen defines how much bytes we have to send. + */ + /*addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1); */ + addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); + addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); + addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); + + while (--alen >= 0) { + + PRINTD(("i2c_read: send memory word address byte %1d\n",alen)); + msg.condition = I2C_COND_NORMAL; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = addr_bytes[alen]; + if ((ret=i2c_transfer(&msg))) return -1; + } + + + /* start read sequence */ + PRINTD(("i2c_read: start read sequence\n")); + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1); + msg.data |= 0x01; + if ((ret=i2c_transfer(&msg))) return -1; + + /* read bytes; send NACK at last byte */ + while (len--) { + + if (len==0) { + msg.condition = I2C_COND_STOP; + msg.acknack = I2C_ACKNAK_SENDNAK; + } else { + msg.condition = I2C_COND_NORMAL; + msg.acknack = I2C_ACKNAK_SENDACK; + } + + msg.direction = I2C_READ; + msg.data = 0x00; + if ((ret=i2c_transfer(&msg))) return -1; + + *(buffer++) = msg.data; + + PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); + + } + + i2c_reset(); + + return 0; +} + + +/** + * i2c_write: - Write multiple bytes to an i2c device + * + * The higher level routines take into account that this function is only + * called with len < page length of the device (see configuration file) + * + * @chip: address of the chip which is to be written + * @addr: i2c data address within the chip + * @alen: length of the i2c data address (1..2 bytes) + * @buffer: where to find the data to be written + * @len: how much byte do we want to read + * @return: 0 in case of success + */ + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + struct i2c_msg msg; + u8 addr_bytes[3]; /* lowest...highest byte of data address */ + + PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); + + i2c_reset(); + + /* chip address write */ + PRINTD(("i2c_write: chip address write\n")); + msg.condition = I2C_COND_START; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = (chip << 1); + msg.data &= 0xFE; + if (i2c_transfer(&msg)) return -1; + + /* + * send memory address bytes; + * alen defines how much bytes we have to send. + */ + addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); + addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); + addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); + + while (--alen >= 0) { + + PRINTD(("i2c_write: send memory word address\n")); + msg.condition = I2C_COND_NORMAL; + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = addr_bytes[alen]; + if (i2c_transfer(&msg)) return -1; + } + + /* write bytes; send NACK at last byte */ + while (len--) { + + PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); + + if (len==0) + msg.condition = I2C_COND_STOP; + else + msg.condition = I2C_COND_NORMAL; + + msg.acknack = I2C_ACKNAK_WAITACK; + msg.direction = I2C_WRITE; + msg.data = *(buffer++); + + if (i2c_transfer(&msg)) return -1; + + } + + i2c_reset(); + + return 0; + +} + +uchar i2c_reg_read (uchar chip, uchar reg) +{ + char buf; + + PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg)); + i2c_read(chip, reg, 1, &buf, 1); + return (buf); +} + +void i2c_reg_write(uchar chip, uchar reg, uchar val) +{ + PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val)); + i2c_write(chip, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c new file mode 100644 index 0000000..0479a10 --- /dev/null +++ b/cpu/pxa/interrupts.c @@ -0,0 +1,231 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_USE_IRQ +/* enable IRQ/FIQ interrupts */ +void enable_interrupts (void) +{ +#error: interrupts not implemented yet +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ +#error: interrupts not implemented yet +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + + +int interrupt_init (void) +{ + /* nothing happens here - we don't setup any IRQs */ + return (0); +} + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + /* nop */ +} + +void udelay (unsigned long usec) +{ + udelay_masked (usec); +} + + +void reset_timer_masked (void) +{ + OSCR = 0; +} + +ulong get_timer_masked (void) +{ + return OSCR; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 1000; + } else { + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c new file mode 100644 index 0000000..f7020ee --- /dev/null +++ b/cpu/pxa/mmc.c @@ -0,0 +1,489 @@ +/* + * (C) Copyright 2003 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MMC + +extern int +fat_register_device(block_dev_desc_t *dev_desc, int part_no); + +static block_dev_desc_t mmc_dev; + +block_dev_desc_t * mmc_get_dev(int dev) +{ + return ((block_dev_desc_t *)&mmc_dev); +} + +/* + * FIXME needs to read cid and csd info to determine block size + * and other parameters + */ +static uchar mmc_buf[MMC_BLOCK_SIZE]; +static mmc_csd_t mmc_csd; +static int mmc_ready = 0; + + +static uchar * +/****************************************************/ +mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) +/****************************************************/ +{ + static uchar resp[20]; + ulong status; + int words, i; + + debug("mmc_cmd %x %x %x %x\n", cmd, argh, argl, cmdat); + MMC_STRPCL = MMC_STRPCL_STOP_CLK; + MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; + while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)); + MMC_CMD = cmd; + MMC_ARGH = argh; + MMC_ARGL = argl; + MMC_CMDAT = cmdat; + MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES; + MMC_STRPCL = MMC_STRPCL_START_CLK; + while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)); + + status = MMC_STAT; + debug("MMC status %x\n", status); + if (status & MMC_STAT_TIME_OUT_RESPONSE) { + return 0; + } + + switch (cmdat & 0x3) { + case MMC_CMDAT_R1: + case MMC_CMDAT_R3: + words = 3; + break; + + case MMC_CMDAT_R2: + words = 8; + break; + + default: + return 0; + } + for (i = words-1; i >= 0; i--) { + ulong res_fifo = MMC_RES; + int offset = i << 1; + + resp[offset] = ((uchar *)&res_fifo)[0]; + resp[offset+1] = ((uchar *)&res_fifo)[1]; + } +#ifdef MMC_DEBUG + for (i=0; i> 16; + argl = len & 0xffff; + + /* set block len */ + resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); + + /* send read command */ + argh = src >> 16; + argl = src & 0xffff; + MMC_STRPCL = MMC_STRPCL_STOP_CLK; + MMC_RDTO = 0xffff; + MMC_NOB = 1; + MMC_BLKLEN = len; + resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, + MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); + + + MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ; + while (len) { + if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) { +#ifdef CONFIG_PXA27X + int i; + for (i=min(len,32); i; i--) { + *dst++ = * ((volatile uchar *) &MMC_RXFIFO); + len--; + } +#else + *dst++ = MMC_RXFIFO; + len--; +#endif + } + status = MMC_STAT; + if (status & MMC_STAT_ERRORS) { + printf("MMC_STAT error %lx\n", status); + return -1; + } + } + MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; + while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)); + status = MMC_STAT; + if (status & MMC_STAT_ERRORS) { + printf("MMC_STAT error %lx\n", status); + return -1; + } + return 0; +} + +int +/****************************************************/ +mmc_block_write(ulong dst, uchar *src, int len) +/****************************************************/ +{ + uchar *resp; + ushort argh, argl; + ulong status; + + if (len == 0) { + return 0; + } + + debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong)src, len); + + argh = len >> 16; + argl = len & 0xffff; + + /* set block len */ + resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); + + /* send write command */ + argh = dst >> 16; + argl = dst & 0xffff; + MMC_STRPCL = MMC_STRPCL_STOP_CLK; + MMC_NOB = 1; + MMC_BLKLEN = len; + resp = mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl, + MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); + + MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ; + while (len) { + if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) { + int i, bytes = min(32,len); + + for (i=0; iid[0], cid->id[1], cid->id[2]); + printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); + cid->hwrev = cid->fwrev = 0; /* null terminate string */ + printf("Product Name = %s\n",cid->name); + printf("Serial Number = %02x%02x%02x\n", + cid->sn[0], cid->sn[1], cid->sn[2]); + printf("Month = %d\n",cid->month); + printf("Year = %d\n",1997 + cid->year); + } + /* fill in device description */ + mmc_dev.if_type = IF_TYPE_MMC; + mmc_dev.part_type = PART_TYPE_DOS; + mmc_dev.dev = 0; + mmc_dev.lun = 0; + mmc_dev.type = 0; + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_dev.blksz = 512; + mmc_dev.lba = 0x10000; + sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", + cid->id[0], cid->id[1], cid->id[2], + cid->sn[0], cid->sn[1], cid->sn[2]); + sprintf(mmc_dev.product,"%s",cid->name); + sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); + mmc_dev.removable = 0; + mmc_dev.block_read = mmc_bread; + + /* MMC exists, get CSD too */ + resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); + resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2); + if (resp) { + mmc_csd_t *csd = (mmc_csd_t *)resp; + memcpy(&mmc_csd, csd, sizeof(csd)); + rc = 0; + mmc_ready = 1; + /* FIXME add verbose printout for csd */ + } + } + +#ifdef CONFIG_PXA27X + MMC_CLKRT = 1; /* 10 MHz - see Intel errata */ +#else + MMC_CLKRT = 0; /* 20 MHz */ +#endif + resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); + + fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ + + return rc; +} + +int +mmc_ident(block_dev_desc_t *dev) +{ + return 0; +} + +int +mmc2info(ulong addr) +{ + /* FIXME hard codes to 32 MB device */ + if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) { + return 1; + } + return 0; +} + +#endif /* CONFIG_MMC */ diff --git a/cpu/pxa/pxafb.c b/cpu/pxa/pxafb.c new file mode 100644 index 0000000..b2caa73 --- /dev/null +++ b/cpu/pxa/pxafb.c @@ -0,0 +1,471 @@ +/* + * PXA LCD Controller + * + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering -- wd@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************/ +/* ** HEADER FILES */ +/************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* #define DEBUG */ + +#ifdef CONFIG_LCD + +/*----------------------------------------------------------------------*/ +/* + * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for + * your display. + */ + +#ifdef CONFIG_PXA_VGA +/* LCD outputs connected to a video DAC */ +# define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f8 +# define REG_LCCR3 0x0300FF01 + +/* 640x480x16 @ 61 Hz */ +vidinfo_t panel_info = { + vl_col: 640, + vl_row: 480, + vl_width: 640, + vl_height: 480, + vl_clkp: CFG_HIGH, + vl_oep: CFG_HIGH, + vl_hsp: CFG_HIGH, + vl_vsp: CFG_HIGH, + vl_dp: CFG_HIGH, + vl_bpix: LCD_BPP, + vl_lbw: 0, + vl_splt: 0, + vl_clor: 0, + vl_tft: 1, + vl_hpw: 40, + vl_blw: 56, + vl_elw: 56, + vl_vpw: 20, + vl_bfw: 8, + vl_efw: 8, +}; +#endif /* CONFIG_PXA_VIDEO */ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_SHARP_LM8V31 + +# define LCD_BPP LCD_COLOR8 +# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */ + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x0030087C +# define REG_LCCR3 0x0340FF08 + +vidinfo_t panel_info = { + vl_col: 640, + vl_row: 480, + vl_width: 157, + vl_height: 118, + vl_clkp: CFG_HIGH, + vl_oep: CFG_HIGH, + vl_hsp: CFG_HIGH, + vl_vsp: CFG_HIGH, + vl_dp: CFG_HIGH, + vl_bpix: LCD_BPP, + vl_lbw: 0, + vl_splt: 1, + vl_clor: 1, + vl_tft: 0, + vl_hpw: 1, + vl_blw: 3, + vl_elw: 3, + vl_vpw: 1, + vl_bfw: 0, + vl_efw: 0, +}; +#endif /* CONFIG_SHARP_LM8V31 */ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_HITACHI_SX14 +/* Hitachi SX14Q004-ZZA color STN LCD */ +#define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +#define REG_LCCR0 0x00301079 +#define REG_LCCR3 0x0340FF20 + +vidinfo_t panel_info = { + vl_col: 320, + vl_row: 240, + vl_width: 167, + vl_height: 109, + vl_clkp: CFG_HIGH, + vl_oep: CFG_HIGH, + vl_hsp: CFG_HIGH, + vl_vsp: CFG_HIGH, + vl_dp: CFG_HIGH, + vl_bpix: LCD_BPP, + vl_lbw: 1, + vl_splt: 0, + vl_clor: 1, + vl_tft: 0, + vl_hpw: 1, + vl_blw: 1, + vl_elw: 1, + vl_vpw: 7, + vl_bfw: 0, + vl_efw: 0, +}; +#endif /* CONFIG_HITACHI_SX14 */ + +/*----------------------------------------------------------------------*/ + +#if LCD_BPP == LCD_COLOR8 +void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); +#endif +#if LCD_BPP == LCD_MONOCHROME +void lcd_initcolregs (void); +#endif + +#ifdef NOT_USED_SO_FAR +void lcd_disable (void); +void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue); +#endif /* NOT_USED_SO_FAR */ + +void lcd_ctrl_init (void *lcdbase); +void lcd_enable (void); + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +short console_col; +short console_row; + +static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid); +static void pxafb_setup_gpio (vidinfo_t *vid); +static void pxafb_enable_controller (vidinfo_t *vid); +static int pxafb_init (vidinfo_t *vid); +/************************************************************************/ + +/************************************************************************/ +/* --------------- PXA chipset specific functions ------------------- */ +/************************************************************************/ + +void lcd_ctrl_init (void *lcdbase) +{ + pxafb_init_mem(lcdbase, &panel_info); + pxafb_init(&panel_info); + pxafb_setup_gpio(&panel_info); + pxafb_enable_controller(&panel_info); +} + +/*----------------------------------------------------------------------*/ +#ifdef NOT_USED_SO_FAR +void +lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) +{ +} +#endif /* NOT_USED_SO_FAR */ + +/*----------------------------------------------------------------------*/ +#if LCD_BPP == LCD_COLOR8 +void +lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) +{ + struct pxafb_info *fbi = &panel_info.pxa; + unsigned short *palette = (unsigned short *)fbi->palette; + u_int val; + + if (regno < fbi->palette_size) { + val = ((red << 8) & 0xf800); + val |= ((green << 4) & 0x07e0); + val |= (blue & 0x001f); + +#ifdef LCD_INVERT_COLORS + palette[regno] = ~val; +#else + palette[regno] = val; +#endif + } + + debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n", + regno, &palette[regno], + red, green, blue, + palette[regno]); +} +#endif /* LCD_COLOR8 */ + +/*----------------------------------------------------------------------*/ +#if LCD_BPP == LCD_MONOCHROME +void lcd_initcolregs (void) +{ + struct pxafb_info *fbi = &panel_info.pxa; + cmap = (ushort *)fbi->palette; + ushort regno; + + for (regno = 0; regno < 16; regno++) { + cmap[regno * 2] = 0; + cmap[(regno * 2) + 1] = regno & 0x0f; + } +} +#endif /* LCD_MONOCHROME */ + +/*----------------------------------------------------------------------*/ +void lcd_enable (void) +{ +} + +/*----------------------------------------------------------------------*/ +#ifdef NOT_USED_SO_FAR +static void lcd_disable (void) +{ +} +#endif /* NOT_USED_SO_FAR */ + +/*----------------------------------------------------------------------*/ + +/************************************************************************/ +/* ** PXA255 specific routines */ +/************************************************************************/ + +/* + * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, + * descriptors and palette areas. + */ +ulong calc_fbsize (void) +{ + ulong size; + int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + + size = line_length * panel_info.vl_row; + size += PAGE_SIZE; + + return size; +} + +static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid) +{ + u_long palette_mem_size; + struct pxafb_info *fbi = &vid->pxa; + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; + + fbi->screen = (u_long)lcdbase; + + fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; + palette_mem_size = fbi->palette_size * sizeof(u16); + + debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); + /* locate palette and descs at end of page following fb */ + fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; + + return 0; +} + +static void pxafb_setup_gpio (vidinfo_t *vid) +{ + u_long lccr0; + + /* + * setup is based on type of panel supported + */ + + lccr0 = vid->pxa.reg_lccr0; + + /* 4 bit interface */ + if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD)) + { + debug("Setting GPIO for 4 bit data\n"); + /* bits 58-61 */ + GPDR1 |= (0xf << 26); + GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20); + + /* bits 74-77 */ + GPDR2 |= (0xf << 10); + GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20); + } + + /* 8 bit interface */ + else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) || + (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS))) + { + debug("Setting GPIO for 8 bit data\n"); + /* bits 58-65 */ + GPDR1 |= (0x3f << 26); + GPDR2 |= (0x3); + + GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20); + GAFR2_L = (GAFR2_L & ~0xf) | (0xa); + + /* bits 74-77 */ + GPDR2 |= (0xf << 10); + GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20); + } + + /* 16 bit interface */ + else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS))) + { + debug("Setting GPIO for 16 bit data\n"); + /* bits 58-77 */ + GPDR1 |= (0x3f << 26); + GPDR2 |= 0x00003fff; + + GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20); + GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa; + } + else + { + printf("pxafb_setup_gpio: unable to determine bits per pixel\n"); + } +} + +static void pxafb_enable_controller (vidinfo_t *vid) +{ + debug("Enabling LCD controller\n"); + + /* Sequence from 11.7.10 */ + LCCR3 = vid->pxa.reg_lccr3; + LCCR2 = vid->pxa.reg_lccr2; + LCCR1 = vid->pxa.reg_lccr1; + LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB; + FDADR0 = vid->pxa.fdadr0; + FDADR1 = vid->pxa.fdadr1; + LCCR0 |= LCCR0_ENB; + + CKEN |= CKEN16_LCD; + + debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0); + debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1); + debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0); + debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1); + debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2); + debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3); +} + +static int pxafb_init (vidinfo_t *vid) +{ + struct pxafb_info *fbi = &vid->pxa; + + debug("Configuring PXA LCD\n"); + + fbi->reg_lccr0 = REG_LCCR0; + fbi->reg_lccr3 = REG_LCCR3; + + debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n", + vid->vl_col, vid->vl_hpw, + vid->vl_blw, vid->vl_elw); + debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n", + vid->vl_row, vid->vl_vpw, + vid->vl_bfw, vid->vl_efw); + + fbi->reg_lccr1 = + LCCR1_DisWdth(vid->vl_col) + + LCCR1_HorSnchWdth(vid->vl_hpw) + + LCCR1_BegLnDel(vid->vl_blw) + + LCCR1_EndLnDel(vid->vl_elw); + + fbi->reg_lccr2 = + LCCR2_DisHght(vid->vl_row) + + LCCR2_VrtSnchWdth(vid->vl_vpw) + + LCCR2_BegFrmDel(vid->vl_bfw) + + LCCR2_EndFrmDel(vid->vl_efw); + + fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP); + fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH) + | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH); + + + /* setup dma descriptors */ + fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); + fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); + fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); + + #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \ + (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \ + (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)) + + /* populate descriptors */ + fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow; + fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL; + fbi->dmadesc_fblow->fidr = 0; + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL; + + fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */ + + fbi->dmadesc_fbhigh->fsadr = fbi->screen; + fbi->dmadesc_fbhigh->fidr = 0; + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL; + + fbi->dmadesc_palette->fsadr = fbi->palette; + fbi->dmadesc_palette->fidr = 0; + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; + + if( NBITS(vid->vl_bpix) < 12) + { + /* assume any mode with <12 bpp is palette driven */ + fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh; + fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette; + /* flips back and forth between pal and fbhigh */ + fbi->fdadr0 = (u_long)fbi->dmadesc_palette; + } + else + { + /* palette shouldn't be loaded in true-color mode */ + fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh; + fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */ + } + + debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow); + debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh); + debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette); + + debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr); + debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr); + debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr); + + debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr); + debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr); + debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr); + + debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd); + debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd); + debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd); + + return 0; +} + +/************************************************************************/ +/************************************************************************/ + +#endif /* CONFIG_LCD */ diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c new file mode 100644 index 0000000..cedebfe --- /dev/null +++ b/cpu/pxa/serial.c @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned int quot = 0; + + if (gd->baudrate == 1200) + quot = 768; + else if (gd->baudrate == 9600) + quot = 96; + else if (gd->baudrate == 19200) + quot = 48; + else if (gd->baudrate == 38400) + quot = 24; + else if (gd->baudrate == 57600) + quot = 16; + else if (gd->baudrate == 115200) + quot = 8; + else + hang (); + +#ifdef CONFIG_FFUART + CKEN |= CKEN6_FFUART; + + FFIER = 0; /* Disable for now */ + FFFCR = 0; /* No fifos enabled */ + + /* set baud rate */ + FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; + FFDLL = quot & 0xff; + FFDLH = quot >> 8; + FFLCR = LCR_WLS0 | LCR_WLS1; + + FFIER = IER_UUE; /* Enable FFUART */ + +#elif defined(CONFIG_BTUART) + CKEN |= CKEN7_BTUART; + + BTIER = 0; + BTFCR = 0; + + /* set baud rate */ + BTLCR = LCR_DLAB; + BTDLL = quot & 0xff; + BTDLH = quot >> 8; + BTLCR = LCR_WLS0 | LCR_WLS1; + + BTIER = IER_UUE; /* Enable BFUART */ + +#elif defined(CONFIG_STUART) + CKEN |= CKEN5_STUART; + + STIER = 0; + STFCR = 0; + + /* set baud rate */ + STLCR = LCR_DLAB; + STDLL = quot & 0xff; + STDLH = quot >> 8; + STLCR = LCR_WLS0 | LCR_WLS1; + + STIER = IER_UUE; /* Enable STUART */ + +#else +#error "Bad: you didn't configure serial ..." +#endif +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + serial_setbrg (); + + return (0); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ +#ifdef CONFIG_FFUART + /* wait for room in the tx FIFO on FFUART */ + while ((FFLSR & LSR_TEMT) == 0) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + FFTHR = c; +#elif defined(CONFIG_BTUART) + while ((BTLSR & LSR_TEMT ) == 0 ) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + BTTHR = c; +#elif defined(CONFIG_STUART) + while ((STLSR & LSR_TEMT ) == 0 ) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + STTHR = c; +#endif + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_tstc (void) +{ +#ifdef CONFIG_FFUART + return FFLSR & LSR_DR; +#elif defined(CONFIG_BTUART) + return BTLSR & LSR_DR; +#elif defined(CONFIG_STUART) + return STLSR & LSR_DR; +#endif +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ +#ifdef CONFIG_FFUART + while (!(FFLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) FFRBR & 0xff; +#elif defined(CONFIG_BTUART) + while (!(BTLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) BTRBR & 0xff; +#elif defined(CONFIG_STUART) + while (!(STLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) STRBR & 0xff; +#endif +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S new file mode 100644 index 0000000..a8cc080 --- /dev/null +++ b/cpu/pxa/start.S @@ -0,0 +1,453 @@ +/* + * armboot - Startup Code for XScale + * + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000 Wolfgang Denk + * Copyright (C) 2001 Alex Zuepke + * Copyright (C) 2002 Kyle Harris + * Copyright (C) 2003 Robert Schwebel + * Copyright (C) 2003 Kai-Uwe Bloem + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + * Startup Code (reset vector) + * + * do important init only if we don't start from RAM! + * - relocate armboot to ram + * - setup stack + * - jump to second stage + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/****************************************************************************/ +/* */ +/* the actual reset code */ +/* */ +/****************************************************************************/ + +reset: + mrs r0,cpsr /* set the cpu to SVC32 mode */ + bic r0,r0,#0x1f /* (superviser mode, M=10011) */ + orr r0,r0,#0x13 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit /* we do sys-critical inits */ +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/****************************************************************************/ +/* */ +/* CPU_init_critical registers */ +/* */ +/* - setup important registers */ +/* - setup memory timing */ +/* */ +/****************************************************************************/ + +/* Interrupt-Controller base address */ +IC_BASE: .word 0x40d00000 +#define ICMR 0x04 + +/* Reset-Controller */ +RST_BASE: .word 0x40f00030 +#define RCSR 0x00 + +/* Operating System Timer */ +OSTIMER_BASE: .word 0x40a00000 +#define OSMR3 0x0C +#define OSCR 0x10 +#define OWER 0x18 +#define OIER 0x1C + +/* Clock Manager Registers */ +#ifdef CFG_CPUSPEED +CC_BASE: .word 0x41300000 +#define CCCR 0x00 +cpuspeed: .word CFG_CPUSPEED +#else +#error "You have to define CFG_CPUSPEED!!" +#endif + + + /* RS: ??? */ + .macro CPWAIT + mrc p15,0,r0,c2,c0,0 + mov r0,r0 + sub pc,pc,#4 + .endm + + +cpu_init_crit: + + /* mask all IRQs */ + ldr r0, IC_BASE + mov r1, #0x00 + str r1, [r0, #ICMR] + +#if defined(CFG_CPUSPEED) + + /* set clock speed */ + ldr r0, CC_BASE + ldr r1, cpuspeed + str r1, [r0, #CCCR] + mov r0, #2 + mcr p14, 0, r0, c6, c0, 0 + +setspeed_done: +#endif + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + + /* Memory interfaces are working. Disable MMU and enable I-cache. */ + + ldr r0, =0x2001 /* enable access to all coproc. */ + mcr p15, 0, r0, c15, c1, 0 + CPWAIT + + mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */ + CPWAIT + + mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ + CPWAIT + + mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */ + CPWAIT + + /* Enable the Icache */ +/* + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x1800 + mcr p15, 0, r0, c1, c0, 0 + CPWAIT +*/ + mov pc, lr + + +/****************************************************************************/ +/* */ +/* Interrupt handling */ +/* */ +/****************************************************************************/ + +/* IRQ stack frame */ + +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 + + /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r8, sp, #S_PC + + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ + add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ + mov r0, sp + .endm + + + /* use irq_save_user_regs / irq_restore_user_regs for */ + /* IRQ/FIQ handling */ + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ /* Calling SP, LR */ + str lr, [r8, #0] /* Save calling PC */ + mrs r6, spsr + str r6, [r8, #4] /* Save CPSR */ + str r0, [r8, #8] /* Save OLD_R0 */ + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + msr spsr_c, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + + +/****************************************************************************/ +/* */ +/* exception handlers */ +/* */ +/****************************************************************************/ + + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + irq_save_user_regs /* someone ought to write a more */ + bl do_fiq /* effiction fiq_save_user_regs */ + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + +/****************************************************************************/ +/* */ +/* Reset function: the PXA250 doesn't have a reset function, so we have to */ +/* perform a watchdog timeout for a soft reset. */ +/* */ +/****************************************************************************/ + + .align 5 +.globl reset_cpu + + /* FIXME: this code is PXA250 specific. How is this handled on */ + /* other XScale processors? */ + +reset_cpu: + + /* We set OWE:WME (watchdog enable) and wait until timeout happens */ + + ldr r0, OSTIMER_BASE + ldr r1, [r0, #OWER] + orr r1, r1, #0x0001 /* bit0: WME */ + str r1, [r0, #OWER] + + /* OS timer does only wrap every 1165 seconds, so we have to set */ + /* the match register as well. */ + + ldr r1, [r0, #OSCR] /* read OS timer */ + add r1, r1, #0x800 /* let OSMR3 match after */ + add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ + str r1, [r0, #OSMR3] + +reset_endless: + + b reset_endless diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile new file mode 100644 index 0000000..d43c73e --- /dev/null +++ b/cpu/s3c44b0/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = serial.o interrupts.o cpu.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/s3c44b0/config.mk b/cpu/s3c44b0/config.mk new file mode 100644 index 0000000..6dc9c46 --- /dev/null +++ b/cpu/s3c44b0/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float +# ========================================================================= +# +# Supply options according to compiler version +# +# ======================================================================== +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c new file mode 100644 index 0000000..5d50b3c --- /dev/null +++ b/cpu/s3c44b0/cpu.c @@ -0,0 +1,509 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * S3C44B0 CPU specific code + */ + +#include +#include +#include + +static void s3c44b0_flush_cache(void) +{ + volatile int i; + /* flush cycle */ + for(i=0x10002000;i<0x10004800;i+=16) + { + *((int *)i)=0x0; + } +} + + +int cpu_init (void) +{ + icache_enable(); + + return 0; +} + +int cleanup_before_linux (void) +{ + /* + cache memory should be enabled before calling + Linux to make the kernel uncompression faster + */ + icache_enable(); + + disable_interrupts (); + + return 0; +} + +void reset_cpu (ulong addr) +{ + /* + reset the cpu using watchdog + */ + + /* Disable the watchdog.*/ + WTCON&=~(1<<5); + + /* set the timeout value to a short time... */ + WTCNT = 0x1; + + /* Enable the watchdog. */ + WTCON|=1; + WTCON|=(1<<5); + + while(1) { + /*NOP*/ + } +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + + /*NOTREACHED*/ + return (0); +} + +void icache_enable (void) +{ + ulong reg; + + s3c44b0_flush_cache(); + + /* + Init cache + Non-cacheable area (everything outside RAM) + 0x0000:0000 - 0x0C00:0000 + */ + NCACHBE0 = 0xC0000000; + NCACHBE1 = 0x00000000; + + /* + Enable chache + */ + reg = SYSCFG; + reg |= 0x00000006; /* 8kB */ + SYSCFG = reg; +} + +void icache_disable (void) +{ + ulong reg; + + reg = SYSCFG; + reg &= ~0x00000006; /* 8kB */ + SYSCFG = reg; +} + +int icache_status (void) +{ + return 0; +} + +void dcache_enable (void) +{ + icache_enable(); +} + +void dcache_disable (void) +{ + icache_disable(); +} + +int dcache_status (void) +{ + return dcache_status(); +} + +/* + RTC stuff +*/ +#include +#ifndef BCD2HEX + #define BCD2HEX(n) ((n>>4)*10+(n&0x0f)) +#endif +#ifndef HEX2BCD + #define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10) +#endif + +void rtc_get (struct rtc_time* tm) +{ + RTCCON |= 1; + tm->tm_year = BCD2HEX(BCDYEAR); + tm->tm_mon = BCD2HEX(BCDMON); + tm->tm_wday = BCD2HEX(BCDDATE); + tm->tm_mday = BCD2HEX(BCDDAY); + tm->tm_hour = BCD2HEX(BCDHOUR); + tm->tm_min = BCD2HEX(BCDMIN); + tm->tm_sec = BCD2HEX(BCDSEC); + + if (tm->tm_sec==0) { + /* we have to re-read the rtc data because of the "one second deviation" problem */ + /* see RTC datasheet for more info about it */ + tm->tm_year = BCD2HEX(BCDYEAR); + tm->tm_mon = BCD2HEX(BCDMON); + tm->tm_mday = BCD2HEX(BCDDAY); + tm->tm_wday = BCD2HEX(BCDDATE); + tm->tm_hour = BCD2HEX(BCDHOUR); + tm->tm_min = BCD2HEX(BCDMIN); + tm->tm_sec = BCD2HEX(BCDSEC); + } + + RTCCON &= ~1; + + if(tm->tm_year >= 70) + tm->tm_year += 1900; + else + tm->tm_year += 2000; +} + +void rtc_set (struct rtc_time* tm) +{ + if(tm->tm_year < 2000) + tm->tm_year -= 1900; + else + tm->tm_year -= 2000; + + RTCCON |= 1; + BCDYEAR = HEX2BCD(tm->tm_year); + BCDMON = HEX2BCD(tm->tm_mon); + BCDDAY = HEX2BCD(tm->tm_mday); + BCDDATE = HEX2BCD(tm->tm_wday); + BCDHOUR = HEX2BCD(tm->tm_hour); + BCDMIN = HEX2BCD(tm->tm_min); + BCDSEC = HEX2BCD(tm->tm_sec); + RTCCON &= 1; +} + +void rtc_reset (void) +{ + RTCCON |= 1; + BCDYEAR = 0; + BCDMON = 0; + BCDDAY = 0; + BCDDATE = 0; + BCDHOUR = 0; + BCDMIN = 0; + BCDSEC = 0; + RTCCON &= 1; +} + + +/* + I2C stuff +*/ + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +void i2c_init(int speed, int slaveaddr) +{ + /* + setting up I2C support + */ + unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; + + save_F = PCONF; + save_PF = PUPF; + + rPCONF = ((save_F & ~(0xF))| 0xa); + rPUPF = (save_PF | 0x3); + PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ + PUPF = rPUPF; /* Disable pull-up */ + + /* Configuring pin for WC pin of EEprom */ + rPCONA = PCONA; + rPCONA &= ~(1<<9); + PCONA = rPCONA; + + rPDATA = PDATA; + rPDATA &= ~(1<<9); + PDATA = rPDATA; + + /* + Enable ACK, IICCLK=MCLK/16, enable interrupt + 75Mhz/16/(12+1) = 390625 Hz + */ + rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); + IICCON = rIICCON; + + IICADD = slaveaddr; +} + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uchar chip) +{ + /* + not implemented + */ + + printf("i2c_probe chip %d\n", (int) chip); + return -1; +} + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ + +#define S3C44B0X_rIIC_INTPEND (1<<4) +#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) +#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) +#define S3C44B0_IIC_TIMEOUT 100 + +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + + int k, j, temp; + u32 rIICSTAT; + + /* + send the device offset + */ + + rIICSTAT = 0xD0; + IICSTAT = rIICSTAT; + + IICDS = chip; /* this is a write operation... */ + + rIICSTAT |= (1<<5); + IICSTAT = rIICSTAT; + + for(k=0; k +#include + +#include + +/* we always count down the max. */ +#define TIMER_LOAD_VAL 0xffff + +/* macro to read the 16 bit timer */ +#define READ_TIMER (TCNTO1 & 0xffff) + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ NOT supported +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = + { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26", + "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26", + "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", + "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32", + "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +static ulong timestamp; +static ulong lastdec; + +int interrupt_init (void) +{ + TCFG0 = 0x000000E9; + TCFG1 = 0x00000004; + TCON = 0x00000900; + TCNTB1 = TIMER_LOAD_VAL; + TCMPB1 = 0; + TCON = 0x00000B00; + TCON = 0x00000900; + + + lastdec = TCNTB1 = TIMER_LOAD_VAL; + timestamp = 0; + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo; + + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 8; + + tmo += get_timer (0); + + while (get_timer_masked () < tmo) + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 8; + } else { + tmo = usec * CFG_HZ; + tmo /= (1000*8); + } + + endtime = get_timer(0) + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} diff --git a/cpu/s3c44b0/serial.c b/cpu/s3c44b0/serial.c new file mode 100644 index 0000000..70b4ee8 --- /dev/null +++ b/cpu/s3c44b0/serial.c @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +/* flush serial input queue. returns 0 on success or negative error + * number otherwise + */ +static int serial_flush_input(void) +{ + volatile u32 tmp; + + /* keep on reading as long as the receiver is not empty */ + while(UTRSTAT0&0x01) { + tmp = REGB(URXH0); + } + + return 0; +} + + +/* flush output queue. returns 0 on success or negative error number + * otherwise + */ +static int serial_flush_output(void) +{ + /* wait until the transmitter is no longer busy */ + while(!(UTRSTAT0 & 0x02)) { + } + + return 0; +} + + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + u32 divisor = 0; + + /* get correct divisor */ + switch(gd->baudrate) { + + case 1200: +#if CONFIG_S3C44B0_CLOCK_SPEED==66 + divisor = 3124; +#elif CONFIG_S3C44B0_CLOCK_SPEED==75 + divisor = 3905; +#else +# error CONFIG_S3C44B0_CLOCK_SPEED undefined +#endif + break; + + case 9600: +#if CONFIG_S3C44B0_CLOCK_SPEED==66 + divisor = 390; +#elif CONFIG_S3C44B0_CLOCK_SPEED==75 + divisor = 487; +#else +# error CONFIG_S3C44B0_CLOCK_SPEED undefined +#endif + break; + + case 19200: +#if CONFIG_S3C44B0_CLOCK_SPEED==66 + divisor = 194; +#elif CONFIG_S3C44B0_CLOCK_SPEED==75 + divisor = 243; +#else +# error CONFIG_S3C44B0_CLOCK_SPEED undefined +#endif + break; + + case 38400: +#if CONFIG_S3C44B0_CLOCK_SPEED==66 + divisor = 97; +#elif CONFIG_S3C44B0_CLOCK_SPEED==75 + divisor = 121; +#else +# error CONFIG_S3C44B0_CLOCK_SPEED undefined +#endif /* break; */ + + case 57600: +#if CONFIG_S3C44B0_CLOCK_SPEED==66 + divisor = 64; +#elif CONFIG_S3C44B0_CLOCK_SPEED==75 + divisor = 80; +#else +# error CONFIG_S3C44B0_CLOCK_SPEED undefined +#endif /* break; */ + + case 115200: +#if CONFIG_S3C44B0_CLOCK_SPEED==66 + divisor = 32; +#elif CONFIG_S3C44B0_CLOCK_SPEED==75 + divisor = 40; +#else +# error CONFIG_S3C44B0_CLOCK_SPEED undefined +#endif /* break; */ + } + + serial_flush_output(); + serial_flush_input(); + UFCON0 = 0x0; + ULCON0 = 0x03; + UCON0 = 0x05; + UBRDIV0 = divisor; + + UFCON1 = 0x0; + ULCON1 = 0x03; + UCON1 = 0x05; + UBRDIV1 = divisor; + + for(divisor=0; divisor<100; divisor++) { + /* NOP */ + } +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + serial_setbrg (); + + return (0); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + /* wait for room in the transmit FIFO */ + while(!(UTRSTAT0 & 0x02)); + + UTXH0 = (unsigned char)c; + + /* + to be polite with serial console add a line feed + to the carriage return character + */ + if (c=='\n') + serial_putc('\r'); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_tstc (void) +{ + return (UTRSTAT0 & 0x01); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + int rv; + + for(;;) { + rv = serial_tstc(); + + if(rv > 0) + return URXH0; + } +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} diff --git a/cpu/s3c44b0/start.S b/cpu/s3c44b0/start.S new file mode 100644 index 0000000..7affe87 --- /dev/null +++ b/cpu/s3c44b0/start.S @@ -0,0 +1,272 @@ +/* + * Startup Code for S3C44B0 CPU-core + * + * (C) Copyright 2004 + * DAVE Srl + * + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* + * Jump vector table + */ + + +.globl _start +_start: b reset + add pc, pc, #0x0c000000 + add pc, pc, #0x0c000000 + add pc, pc, #0x0c000000 + add pc, pc, #0x0c000000 + add pc, pc, #0x0c000000 + add pc, pc, #0x0c000000 + add pc, pc, #0x0c000000 + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate u-boot to ram + * setup stack + * jump to second stage + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0x13 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + bl lowlevel_init +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +/* + now copy to sram the interrupt vector +*/ + adr r0, real_vectors + add r2, r0, #1024 + ldr r1, =0x0c000000 + add r1, r1, #0x08 +vector_copy_loop: + ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + ble vector_copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + +#define INTCON (0x01c00000+0x200000) +#define INTMSK (0x01c00000+0x20000c) +#define LOCKTIME (0x01c00000+0x18000c) +#define PLLCON (0x01c00000+0x180000) +#define CLKCON (0x01c00000+0x180004) +#define WTCON (0x01c00000+0x130000) +cpu_init_crit: + /* disable watch dog */ + ldr r0, =WTCON + ldr r1, =0x0 + str r1, [r0] + + /* + * mask all IRQs by clearing all bits in the INTMRs + */ + ldr r1,=INTMSK + ldr r0, =0x03fffeff + str r0, [r1] + + ldr r1, =INTCON + ldr r0, =0x05 + str r0, [r1] + + /* Set Clock Control Register */ + ldr r1, =LOCKTIME + ldrb r0, =800 + strb r0, [r1] + + ldr r1, =PLLCON + +#if CONFIG_S3C44B0_CLOCK_SPEED==66 + ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ +#elif CONFIG_S3C44B0_CLOCK_SPEED==75 + ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */ +#else +# error CONFIG_S3C44B0_CLOCK_SPEED undefined +#endif + + str r0, [r1] + + ldr r1,=CLKCON + ldr r0, =0x7ff8 + str r0, [r1] + + mov pc, lr + + +/*************************************************/ +/* interrupt vectors */ +/*************************************************/ +real_vectors: + b reset + b undefined_instruction + b software_interrupt + b prefetch_abort + b data_abort + b not_used + b irq + b fiq + +/*************************************************/ + +undefined_instruction: + mov r6, #3 + b reset + +software_interrupt: + mov r6, #4 + b reset + +prefetch_abort: + mov r6, #5 + b reset + +data_abort: + mov r6, #6 + b reset + +not_used: + /* we *should* never reach this */ + mov r6, #7 + b reset + +irq: + mov r6, #8 + b reset + +fiq: + mov r6, #9 + b reset diff --git a/cpu/sa1100/Makefile b/cpu/sa1100/Makefile new file mode 100644 index 0000000..8c950da --- /dev/null +++ b/cpu/sa1100/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = serial.o interrupts.o cpu.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/sa1100/config.mk b/cpu/sa1100/config.mk new file mode 100644 index 0000000..5be7dfb --- /dev/null +++ b/cpu/sa1100/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2002 +# Sysgo Real-Time Solutions, GmbH +# Marius Groeger +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 +# ========================================================================= +# +# Supply options according to compiler version +# +# ======================================================================== +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c new file mode 100644 index 0000000..17e5b0d --- /dev/null +++ b/cpu/sa1100/cpu.c @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + DECLARE_GLOBAL_DATA_PTR; + + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * just disable everything that can disturb booting linux + */ + + unsigned long i; + + disable_interrupts (); + + /* turn off I-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~0x1000; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + + return (0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf ("resetting ...\n"); + + udelay (50000); /* wait 50 ms */ + disable_interrupts (); + reset_cpu (0); + + /*NOTREACHED*/ + return (0); +} + +/* taken from blob */ +void icache_enable (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* set i-cache */ + i |= 0x1000; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void icache_disable (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* clear i-cache */ + i &= ~0x1000; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush i-cache */ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); +} + +int icache_status (void) +{ + register u32 i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + /* return bit */ + return (i & 0x1000); +} + +/* we will never enable dcache, because we have to setup MMU first */ +void dcache_enable (void) +{ + return; +} + +void dcache_disable (void) +{ + return; +} + +int dcache_status (void) +{ + return 0; /* always off */ +} diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/interrupts.c new file mode 100644 index 0000000..b393e0d --- /dev/null +++ b/cpu/sa1100/interrupts.c @@ -0,0 +1,248 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +#ifdef CONFIG_USE_IRQ +/* enable IRQ/FIQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__ ("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old, temp; + __asm__ __volatile__ ("mrs %0, cpsr\n" + "orr %1, %0, #0x80\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + + +int interrupt_init (void) +{ + /* nothing happens here - we don't setup any IRQs */ + return (0); +} + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked (); +} + +void set_timer (ulong t) +{ + /* nop */ +} + +void udelay (unsigned long usec) +{ + udelay_masked (usec); +} + + +void reset_timer_masked (void) +{ + OSCR = 0; +} + +ulong get_timer_masked (void) +{ + return OSCR; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= CFG_HZ; + tmo /= 1000; + } else { + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return tbclk; +} diff --git a/cpu/sa1100/serial.c b/cpu/sa1100/serial.c new file mode 100644 index 0000000..a598489 --- /dev/null +++ b/cpu/sa1100/serial.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned int reg = 0; + + if (gd->baudrate == 1200) + reg = 191; + else if (gd->baudrate == 9600) + reg = 23; + else if (gd->baudrate == 19200) + reg = 11; + else if (gd->baudrate == 38400) + reg = 5; + else if (gd->baudrate == 57600) + reg = 3; + else if (gd->baudrate == 115200) + reg = 1; + else + hang (); + +#ifdef CONFIG_SERIAL1 + /* SA1110 uart function */ + Ser1SDCR0 |= SDCR0_SUS; + + /* Wait until port is ready ... */ + while(Ser1UTSR1 & UTSR1_TBY) {} + + /* init serial serial 1 */ + Ser1UTCR3 = 0x00; + Ser1UTSR0 = 0xff; + Ser1UTCR0 = ( UTCR0_1StpBit | UTCR0_8BitData ); + Ser1UTCR1 = 0; + Ser1UTCR2 = (u32)reg; + Ser1UTCR3 = ( UTCR3_RXE | UTCR3_TXE ); +#elif defined(CONFIG_SERIAL3) + /* Wait until port is ready ... */ + while (Ser3UTSR1 & UTSR1_TBY) { + } + + /* init serial serial 3 */ + Ser3UTCR3 = 0x00; + Ser3UTSR0 = 0xff; + Ser3UTCR0 = (UTCR0_1StpBit | UTCR0_8BitData); + Ser3UTCR1 = 0; + Ser3UTCR2 = (u32) reg; + Ser3UTCR3 = (UTCR3_RXE | UTCR3_TXE); +#else +#error "Bad: you didn't configured serial ..." +#endif +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + serial_setbrg (); + + return (0); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ +#ifdef CONFIG_SERIAL1 + /* wait for room in the tx FIFO on SERIAL1 */ + while ((Ser1UTSR0 & UTSR0_TFS) == 0); + + Ser1UTDR = c; +#elif defined(CONFIG_SERIAL3) + /* wait for room in the tx FIFO on SERIAL3 */ + while ((Ser3UTSR0 & UTSR0_TFS) == 0); + + Ser3UTDR = c; +#endif + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_tstc (void) +{ +#ifdef CONFIG_SERIAL1 + return Ser1UTSR1 & UTSR1_RNE; +#elif defined(CONFIG_SERIAL3) + return Ser3UTSR1 & UTSR1_RNE; +#endif +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ +#ifdef CONFIG_SERIAL1 + while (!(Ser1UTSR1 & UTSR1_RNE)); + + return (char) Ser1UTDR & 0xff; +#elif defined(CONFIG_SERIAL3) + while (!(Ser3UTSR1 & UTSR1_RNE)); + + return (char) Ser3UTDR & 0xff; +#endif +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} diff --git a/cpu/sa1100/start.S b/cpu/sa1100/start.S new file mode 100644 index 0000000..431ee65 --- /dev/null +++ b/cpu/sa1100/start.S @@ -0,0 +1,419 @@ +/* + * armboot - Startup Code for SA1100 CPU + * + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000 Wolfgang Denk + * Copyright (c) 2001 Alex Züpke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * relocate armboot to ram + * setup stack + * jump to second stage + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0x13 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + ble clbss_l + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + + +/* Interupt-Controller base address */ +IC_BASE: .word 0x90050000 +#define ICMR 0x04 + + +/* Reset-Controller */ +RST_BASE: .word 0x90030000 +#define RSRR 0x00 +#define RCSR 0x04 + + +/* PWR */ +PWR_BASE: .word 0x90020000 +#define PSPR 0x08 +#define PPCR 0x14 +cpuspeed: .word CFG_CPUSPEED + + +cpu_init_crit: + /* + * mask all IRQs + */ + ldr r0, IC_BASE + mov r1, #0x00 + str r1, [r0, #ICMR] + + /* set clock speed */ + ldr r0, PWR_BASE + ldr r1, cpuspeed + str r1, [r0, #PPCR] + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + + /* + * disable MMU stuff and enable I-cache + */ + mrc p15,0,r0,c1,c0 + bic r0, r0, #0x00002000 @ clear bit 13 (X) + bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) + orr r0, r0, #0x00001000 @ set bit 12 (I) Icache + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + mcr p15,0,r0,c1,c0 + + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + mov pc, lr + + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 + add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r + mov r0, sp + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + + str lr, [r13] @ save caller lr / spsr + mrs lr, spsr + str lr, [r13, #4] + + mov r13, #MODE_SVC @ prepare SVC-Mode + msr spsr_c, r13 + mov lr, pc + movs pc, lr + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + + .align 5 +.globl reset_cpu +reset_cpu: + ldr r0, RST_BASE + mov r1, #0x0 @ set bit 3-0 ... + str r1, [r0, #RCSR] @ ... to clear in RCSR + mov r1, #0x1 + str r1, [r0, #RSRR] @ and perform reset + b reset_cpu @ silly, but repeat endlessly diff --git a/disk/Makefile b/disk/Makefile new file mode 100644 index 0000000..39677f1 --- /dev/null +++ b/disk/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +#CFLAGS += -DET_DEBUG -DDEBUG + +LIB = libdisk.a + +OBJS = part.o part_mac.o part_dos.o part_iso.o part_amiga.o + +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/disk/part.c b/disk/part.c new file mode 100644 index 0000000..2255e72 --- /dev/null +++ b/disk/part.c @@ -0,0 +1,277 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#undef PART_DEBUG + +#ifdef PART_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) ) + +/* ------------------------------------------------------------------------- */ +/* + * reports device info to the user + */ +void dev_print (block_dev_desc_t *dev_desc) +{ +#ifdef CONFIG_LBA48 + uint64_t lba512; /* number of blocks if 512bytes block size */ +#else + lbaint_t lba512; +#endif + + if (dev_desc->type==DEV_TYPE_UNKNOWN) { + puts ("not available\n"); + return; + } + if (dev_desc->if_type==IF_TYPE_SCSI) { + printf ("(%d:%d) ", dev_desc->target,dev_desc->lun); + } + if (dev_desc->if_type==IF_TYPE_IDE) { + printf ("Model: %s Firm: %s Ser#: %s\n", + dev_desc->vendor, + dev_desc->revision, + dev_desc->product); + } else { + printf ("Vendor: %s Prod.: %s Rev: %s\n", + dev_desc->vendor, + dev_desc->product, + dev_desc->revision); + } + puts (" Type: "); + if (dev_desc->removable) + puts ("Removable "); + switch (dev_desc->type & 0x1F) { + case DEV_TYPE_HARDDISK: puts ("Hard Disk"); + break; + case DEV_TYPE_CDROM: puts ("CD ROM"); + break; + case DEV_TYPE_OPDISK: puts ("Optical Device"); + break; + case DEV_TYPE_TAPE: puts ("Tape"); + break; + default: printf ("# %02X #", dev_desc->type & 0x1F); + break; + } + puts ("\n"); + if ((dev_desc->lba * dev_desc->blksz)>0L) { + ulong mb, mb_quot, mb_rem, gb, gb_quot, gb_rem; + lbaint_t lba; + + lba = dev_desc->lba; + + lba512 = (lba * (dev_desc->blksz/512)); + mb = (10 * lba512) / 2048; /* 2048 = (1024 * 1024) / 512 MB */ + /* round to 1 digit */ + mb_quot = mb / 10; + mb_rem = mb - (10 * mb_quot); + + gb = mb / 1024; + gb_quot = gb / 10; + gb_rem = gb - (10 * gb_quot); +#ifdef CONFIG_LBA48 + if (dev_desc->lba48) + printf (" Supports 48-bit addressing\n"); +#endif +#if defined(CFG_64BIT_LBA) && defined(CFG_64BIT_VSPRINTF) + printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%qd x %ld)\n", + mb_quot, mb_rem, + gb_quot, gb_rem, + lba, + dev_desc->blksz); +#else + printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n", + mb_quot, mb_rem, + gb_quot, gb_rem, + (ulong)lba, + dev_desc->blksz); +#endif + } else { + puts (" Capacity: not available\n"); + } +} +#endif /* CFG_CMD_IDE || CFG_CMD_SCSI || CFG_CMD_USB || CONFIG_MMC */ + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_SYSTEMACE) ) + +#if defined(CONFIG_MAC_PARTITION) || \ + defined(CONFIG_DOS_PARTITION) || \ + defined(CONFIG_ISO_PARTITION) || \ + defined(CONFIG_AMIGA_PARTITION) + +void init_part (block_dev_desc_t * dev_desc) +{ +#ifdef CONFIG_ISO_PARTITION + if (test_part_iso(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_ISO; + return; + } +#endif + +#ifdef CONFIG_MAC_PARTITION + if (test_part_mac(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_MAC; + return; + } +#endif + +#ifdef CONFIG_DOS_PARTITION + if (test_part_dos(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_DOS; + return; + } +#endif + +#ifdef CONFIG_AMIGA_PARTITION + if (test_part_amiga(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_AMIGA; + return; + } +#endif +} + + +int get_partition_info (block_dev_desc_t *dev_desc, int part, disk_partition_t *info) +{ + switch (dev_desc->part_type) { +#ifdef CONFIG_MAC_PARTITION + case PART_TYPE_MAC: + if (get_partition_info_mac(dev_desc,part,info) == 0) { + PRINTF ("## Valid MAC partition found ##\n"); + return (0); + } + break; +#endif + +#ifdef CONFIG_DOS_PARTITION + case PART_TYPE_DOS: + if (get_partition_info_dos(dev_desc,part,info) == 0) { + PRINTF ("## Valid DOS partition found ##\n"); + return (0); + } + break; +#endif + +#ifdef CONFIG_ISO_PARTITION + case PART_TYPE_ISO: + if (get_partition_info_iso(dev_desc,part,info) == 0) { + PRINTF ("## Valid ISO boot partition found ##\n"); + return (0); + } + break; +#endif + +#ifdef CONFIG_AMIGA_PARTITION + case PART_TYPE_AMIGA: + if (get_partition_info_amiga(dev_desc, part, info) == 0) + { + PRINTF ("## Valid Amiga partition found ##\n"); + return (0); + } + break; +#endif + default: + break; + } + return (-1); +} + +static void print_part_header (const char *type, block_dev_desc_t * dev_desc) +{ + puts ("\nPartition Map for "); + switch (dev_desc->if_type) { + case IF_TYPE_IDE: puts ("IDE"); + break; + case IF_TYPE_SCSI: puts ("SCSI"); + break; + case IF_TYPE_ATAPI: puts ("ATAPI"); + break; + case IF_TYPE_USB: puts ("USB"); + break; + case IF_TYPE_DOC: puts ("DOC"); + break; + default: puts ("UNKNOWN"); + break; + } + printf (" device %d -- Partition Type: %s\n\n", + dev_desc->dev, type); +} + +void print_part (block_dev_desc_t * dev_desc) +{ + + switch (dev_desc->part_type) { +#ifdef CONFIG_MAC_PARTITION + case PART_TYPE_MAC: + PRINTF ("## Testing for valid MAC partition ##\n"); + print_part_header ("MAC", dev_desc); + print_part_mac (dev_desc); + return; +#endif +#ifdef CONFIG_DOS_PARTITION + case PART_TYPE_DOS: + PRINTF ("## Testing for valid DOS partition ##\n"); + print_part_header ("DOS", dev_desc); + print_part_dos (dev_desc); + return; +#endif + +#ifdef CONFIG_ISO_PARTITION + case PART_TYPE_ISO: + PRINTF ("## Testing for valid ISO Boot partition ##\n"); + print_part_header ("ISO", dev_desc); + print_part_iso (dev_desc); + return; +#endif + +#ifdef CONFIG_AMIGA_PARTITION + case PART_TYPE_AMIGA: + PRINTF ("## Testing for a valid Amiga partition ##\n"); + print_part_header ("AMIGA", dev_desc); + print_part_amiga (dev_desc); + return; +#endif + } + puts ("## Unknown partition table\n"); +} + + +#else /* neither MAC nor DOS nor ISO partition configured */ +# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION nor CONFIG_ISO_PARTITION configured! +#endif + +#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) || CONFIG_COMMANDS & CFG_CMD_SCSI) */ diff --git a/disk/part_amiga.c b/disk/part_amiga.c new file mode 100644 index 0000000..41e68fc --- /dev/null +++ b/disk/part_amiga.c @@ -0,0 +1,402 @@ +/* + * (C) Copyright 2001 + * Hans-Joerg Frieden, Hyperion Entertainment + * Hans-JoergF@hyperion-entertainment.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include "part_amiga.h" + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_AMIGA_PARTITION) + +#undef AMIGA_DEBUG + +#ifdef AMIGA_DEBUG +#define PRINTF(fmt, args...) printf(fmt ,##args) +#else +#define PRINTF(fmt, args...) +#endif + +struct block_header +{ + u32 id; + u32 summed_longs; + s32 chk_sum; +}; + +static unsigned char block_buffer[DEFAULT_SECTOR_SIZE]; +static struct rigid_disk_block rdb = {0}; +static struct bootcode_block bootcode = {0}; + +/* + * Copy a bcpl to a c string + */ +static void bcpl_strcpy(char *to, char *from) +{ + int len = *from++; + + while (len) + { + *to++ = *from++; + len--; + } + *to = 0; +} + +/* + * Print a BCPL String. BCPL strings start with a byte with the length + * of the string, and don't contain a terminating nul character + */ +static void bstr_print(char *string) +{ + int len = *string++; + char buffer[256]; + int i; + + i = 0; + while (len) + { + buffer[i++] = *string++; + len--; + } + + buffer[i] = 0; + printf("%-10s", buffer); +} + +/* + * Sum a block. The checksum of a block must end up at zero + * to be valid. The chk_sum field is selected so that adding + * it yields zero. + */ +int sum_block(struct block_header *header) +{ + s32 *block = (s32 *)header; + u32 i; + s32 sum = 0; + + for (i = 0; i < header->summed_longs; i++) + sum += *block++; + + return (sum != 0); +} + +/* + * Print an AmigaOS disk type. Disk types are a four-byte identifier + * describing the file system. They are usually written as a three-letter + * word followed by a backslash and a version number. For example, + * DOS\0 would be the original file system. SFS\0 would be SmartFileSystem. + * DOS\1 is FFS. + */ +static void print_disk_type(u32 disk_type) +{ + char buffer[6]; + buffer[0] = (disk_type & 0xFF000000)>>24; + buffer[1] = (disk_type & 0x00FF0000)>>16; + buffer[2] = (disk_type & 0x0000FF00)>>8; + buffer[3] = '\\'; + buffer[4] = (disk_type & 0x000000FF) + '0'; + buffer[5] = 0; + printf("%s", buffer); +} + +/* + * Print the info contained within the given partition block + */ +static void print_part_info(struct partition_block *p) +{ + struct amiga_part_geometry *g; + + g = (struct amiga_part_geometry *)&(p->environment); + + bstr_print(p->drive_name); + printf("%6d\t%6d\t", + g->low_cyl * g->block_per_track * g->surfaces , + (g->high_cyl - g->low_cyl + 1) * g->block_per_track * g->surfaces - 1); + print_disk_type(g->dos_type); + printf("\t%5d\n", g->boot_priority); +} + +/* + * Search for the Rigid Disk Block. The rigid disk block is required + * to be within the first 16 blocks of a drive, needs to have + * the ID AMIGA_ID_RDISK ('RDSK') and needs to have a valid + * sum-to-zero checksum + */ +struct rigid_disk_block *get_rdisk(block_dev_desc_t *dev_desc) +{ + int i; + int limit; + char *s; + + s = getenv("amiga_scanlimit"); + if (s) + limit = atoi(s); + else + limit = AMIGA_BLOCK_LIMIT; + + for (i=0; iblock_read(dev_desc->dev, i, 1, + (ulong *)block_buffer); + if (res == 1) + { + struct rigid_disk_block *trdb = (struct rigid_disk_block *)block_buffer; + if (trdb->id == AMIGA_ID_RDISK) + { + PRINTF("Rigid disk block suspect at %d, checking checksum\n",i); + if (sum_block((struct block_header *)block_buffer) == 0) + { + PRINTF("FOUND\n"); + memcpy(&rdb, trdb, sizeof(struct rigid_disk_block)); + return (struct rigid_disk_block *)&rdb; + } + } + } + } + PRINTF("Done scanning, no RDB found\n"); + return NULL; +} + +/* + * Search for boot code + * Again, the first boot block must be located somewhere in the first 16 blocks, or rooted in the + * Ridgid disk block + */ + +struct bootcode_block *get_bootcode(block_dev_desc_t *dev_desc) +{ + int i; + int limit; + char *s; + + s = getenv("amiga_scanlimit"); + if (s) + limit = atoi(s); + else + limit = AMIGA_BLOCK_LIMIT; + + PRINTF("Scanning for BOOT from 0 to %d\n", limit); + + for (i = 0; i < limit; i++) + { + ulong res = dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)block_buffer); + if (res == 1) + { + struct bootcode_block *boot = (struct bootcode_block *)block_buffer; + if (boot->id == AMIGA_ID_BOOT) + { + PRINTF("BOOT block at %d, checking checksum\n", i); + if (sum_block((struct block_header *)block_buffer) == 0) + { + PRINTF("Found valid bootcode block\n"); + memcpy(&bootcode, boot, sizeof(struct bootcode_block)); + return &bootcode; + } + } + } + } + + PRINTF("No boot code found on disk\n"); + return 0; +} + +/* + * Test if the given partition has an Amiga partition table/Rigid + * Disk block + */ +int test_part_amiga(block_dev_desc_t *dev_desc) +{ + struct rigid_disk_block *rdb; + struct bootcode_block *bootcode; + + PRINTF("test_part_amiga: Testing for an Amiga RDB partition\n"); + + rdb = get_rdisk(dev_desc); + if (rdb) + { + bootcode = get_bootcode(dev_desc); + if (bootcode) + PRINTF("test_part_amiga: bootable Amiga disk\n"); + else + PRINTF("test_part_amiga: non-bootable Amiga disk\n"); + + return 0; + } + else + { + PRINTF("test_part_amiga: no RDB found\n"); + return -1; + } + +} + +/* + * Find partition number partnum on the given drive. + */ +static struct partition_block *find_partition(block_dev_desc_t *dev_desc, int partnum) +{ + struct rigid_disk_block *rdb; + struct partition_block *p; + u32 block; + + PRINTF("Trying to find partition block %d\n", partnum); + rdb = get_rdisk(dev_desc); + if (!rdb) + { + PRINTF("find_partition: no rdb found\n"); + return NULL; + } + + PRINTF("find_partition: Scanning partition list\n"); + + block = rdb->partition_list; + PRINTF("find_partition: partition list at 0x%x\n", block); + + while (block != 0xFFFFFFFF) + { + ulong res = dev_desc->block_read(dev_desc->dev, block, 1, + (ulong *)block_buffer); + if (res == 1) + { + p = (struct partition_block *)block_buffer; + if (p->id == AMIGA_ID_PART) + { + PRINTF("PART block suspect at 0x%x, checking checksum\n",block); + if (sum_block((struct block_header *)p) == 0) + { + if (partnum == 0) break; + else + { + partnum--; + block = p->next; + } + } + } else block = 0xFFFFFFFF; + } else block = 0xFFFFFFFF; + } + + if (block == 0xFFFFFFFF) + { + PRINTF("PART block not found\n"); + return NULL; + } + + return (struct partition_block *)block_buffer; +} + +/* + * Get info about a partition + */ +int get_partition_info_amiga (block_dev_desc_t *dev_desc, int part, disk_partition_t *info) +{ + struct partition_block *p = find_partition(dev_desc, part-1); + struct amiga_part_geometry *g; + u32 disk_type; + + if (!p) return -1; + + g = (struct amiga_part_geometry *)&(p->environment); + info->start = g->low_cyl * g->block_per_track * g->surfaces; + info->size = (g->high_cyl - g->low_cyl + 1) * g->block_per_track * g->surfaces - 1; + info->blksz = rdb.block_bytes; + bcpl_strcpy(info->name, p->drive_name); + + + disk_type = g->dos_type; + + info->type[0] = (disk_type & 0xFF000000)>>24; + info->type[1] = (disk_type & 0x00FF0000)>>16; + info->type[2] = (disk_type & 0x0000FF00)>>8; + info->type[3] = '\\'; + info->type[4] = (disk_type & 0x000000FF) + '0'; + info->type[5] = 0; + + return 0; +} + +void print_part_amiga (block_dev_desc_t *dev_desc) +{ + struct rigid_disk_block *rdb; + struct bootcode_block *boot; + struct partition_block *p; + u32 block; + int i = 1; + + rdb = get_rdisk(dev_desc); + if (!rdb) + { + PRINTF("print_part_amiga: no rdb found\n"); + return; + } + + PRINTF("print_part_amiga: Scanning partition list\n"); + + block = rdb->partition_list; + PRINTF("print_part_amiga: partition list at 0x%x\n", block); + + printf("Summary: DiskBlockSize: %d\n" + " Cylinders : %d\n" + " Sectors/Track: %d\n" + " Heads : %d\n\n", + rdb->block_bytes, rdb->cylinders, rdb->sectors, + rdb->heads); + + printf(" First Num. \n" + "Nr. Part. Name Block Block Type Boot Priority\n"); + + while (block != 0xFFFFFFFF) + { + ulong res; + + PRINTF("Trying to load block #0x%X\n", block); + + res = dev_desc->block_read(dev_desc->dev, block, 1, + (ulong *)block_buffer); + if (res == 1) + { + p = (struct partition_block *)block_buffer; + if (p->id == AMIGA_ID_PART) + { + PRINTF("PART block suspect at 0x%x, checking checksum\n",block); + if (sum_block((struct block_header *)p) == 0) + { + printf("%-4d ", i); i++; + print_part_info(p); + block = p->next; + } + } else block = 0xFFFFFFFF; + } else block = 0xFFFFFFFF; + } + + boot = get_bootcode(dev_desc); + if (boot) + { + printf("Disk is bootable\n"); + } +} + +#endif diff --git a/disk/part_amiga.h b/disk/part_amiga.h new file mode 100644 index 0000000..20a8fdf --- /dev/null +++ b/disk/part_amiga.h @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2000 + * Hans-Joerg Frieden, Hyperion Entertainment + * Hans-JoergF@hyperion-entertainment.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DISK_PART_AMIGA_H +#define _DISK_PART_AMIGA_H +#include + +#ifdef CONFIG_ISO_PARTITION +/* Make the buffers bigger if ISO partition support is enabled -- CD-ROMS + have 2048 byte blocks */ +#define DEFAULT_SECTOR_SIZE 2048 +#else +#define DEFAULT_SECTOR_SIZE 512 +#endif + + +#define AMIGA_BLOCK_LIMIT 16 + +/* + * Amiga disks have a very open structure. The head for the partition table information + * is stored somewhere within the first 16 blocks on disk, and is called the + * "RigidDiskBlock". + */ + +struct rigid_disk_block +{ + u32 id; + u32 summed_longs; + s32 chk_sum; + u32 host_id; + u32 block_bytes; + u32 flags; + u32 bad_block_list; + u32 partition_list; + u32 file_sys_header_list; + u32 drive_init; + u32 bootcode_block; + u32 reserved_1[5]; + + /* Physical drive geometry */ + u32 cylinders; + u32 sectors; + u32 heads; + u32 interleave; + u32 park; + u32 reserved_2[3]; + u32 write_pre_comp; + u32 reduced_write; + u32 step_rate; + u32 reserved_3[5]; + + /* logical drive geometry */ + u32 rdb_blocks_lo; + u32 rdb_blocks_hi; + u32 lo_cylinder; + u32 hi_cylinder; + u32 cyl_blocks; + u32 auto_park_seconds; + u32 high_rdsk_block; + u32 reserved_4; + + char disk_vendor[8]; + char disk_product[16]; + char disk_revision[4]; + char controller_vendor[8]; + char controller_product[16]; + char controller_revision[4]; + + u32 reserved_5[10]; +}; + +/* + * Each partition on this drive is defined by such a block + */ + +struct partition_block +{ + u32 id; + u32 summed_longs; + s32 chk_sum; + u32 host_id; + u32 next; + u32 flags; + u32 reserved_1[2]; + u32 dev_flags; + char drive_name[32]; + u32 reserved_2[15]; + u32 environment[17]; + u32 reserved_3[15]; +}; + +struct bootcode_block +{ + u32 id; + u32 summed_longs; + s32 chk_sum; + u32 host_id; + u32 next; + u32 load_data[123]; +}; + + +#define AMIGA_ID_RDISK 0x5244534B +#define AMIGA_ID_PART 0x50415254 +#define AMIGA_ID_BOOT 0x424f4f54 + +/* + * The environment array in the partition block + * describes the partition + */ + +struct amiga_part_geometry +{ + u32 table_size; + u32 size_blocks; + u32 unused1; + u32 surfaces; + u32 sector_per_block; + u32 block_per_track; + u32 reserved; + u32 prealloc; + u32 interleave; + u32 low_cyl; + u32 high_cyl; + u32 num_buffers; + u32 buf_mem_type; + u32 max_transfer; + u32 mask; + s32 boot_priority; + u32 dos_type; + u32 baud; + u32 control; + u32 boot_blocks; +}; + +#endif /* _DISK_PART_AMIGA_H_ */ diff --git a/disk/part_dos.c b/disk/part_dos.c new file mode 100644 index 0000000..133ee79 --- /dev/null +++ b/disk/part_dos.c @@ -0,0 +1,251 @@ +/* + * (C) Copyright 2001 + * Raymond Lo, lo@routefree.com + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Support for harddisk partitions. + * + * To be compatible with LinuxPPC and Apple we use the standard Apple + * SCSI disk partitioning scheme. For more information see: + * http://developer.apple.com/techpubs/mac/Devices/Devices-126.html#MARKER-14-92 + */ + +#include +#include +#include +#include "part_dos.h" + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_DOS_PARTITION) + +/* Convert char[4] in little endian format to the host format integer + */ +static inline int le32_to_int(unsigned char *le32) +{ + return ((le32[3] << 24) + + (le32[2] << 16) + + (le32[1] << 8) + + le32[0] + ); +} + +static inline int is_extended(int part_type) +{ + return (part_type == 0x5 || + part_type == 0xf || + part_type == 0x85); +} + +static void print_one_part (dos_partition_t *p, int ext_part_sector, int part_num) +{ + int lba_start = ext_part_sector + le32_to_int (p->start4); + int lba_size = le32_to_int (p->size4); + + printf ("%5d\t\t%10d\t%10d\t%2x%s\n", + part_num, lba_start, lba_size, p->sys_ind, + (is_extended (p->sys_ind) ? " Extd" : "")); +} + +static int test_block_type(unsigned char *buffer) +{ + if((buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || + (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) { + return (-1); + } /* no DOS Signature at all */ + if(strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0) + return DOS_PBR; /* is PBR */ + return DOS_MBR; /* Is MBR */ +} + + +int test_part_dos (block_dev_desc_t *dev_desc) +{ + unsigned char buffer[DEFAULT_SECTOR_SIZE]; + + if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) || + (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || + (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) { + return (-1); + } + return (0); +} + +/* Print a partition that is relative to its Extended partition table + */ +static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_sector, int relative, + int part_num) +{ + unsigned char buffer[DEFAULT_SECTOR_SIZE]; + dos_partition_t *pt; + int i; + + if (dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) { + printf ("** Can't read partition table on %d:%d **\n", + dev_desc->dev, ext_part_sector); + return; + } + i=test_block_type(buffer); + if(i==-1) { + printf ("bad MBR sector signature 0x%02x%02x\n", + buffer[DOS_PART_MAGIC_OFFSET], + buffer[DOS_PART_MAGIC_OFFSET + 1]); + return; + } + if(i==DOS_PBR) { + printf (" 1\t\t 0\t%10ld\t%2x\n", + dev_desc->lba, buffer[DOS_PBR_MEDIA_TYPE_OFFSET]); + return; + } + /* Print all primary/logical partitions */ + pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); + for (i = 0; i < 4; i++, pt++) { + /* + * fdisk does not show the extended partitions that + * are not in the MBR + */ + + if ((pt->sys_ind != 0) && + (ext_part_sector == 0 || !is_extended (pt->sys_ind)) ) { + print_one_part (pt, ext_part_sector, part_num); + } + + /* Reverse engr the fdisk part# assignment rule! */ + if ((ext_part_sector == 0) || + (pt->sys_ind != 0 && !is_extended (pt->sys_ind)) ) { + part_num++; + } + } + + /* Follows the extended partitions */ + pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); + for (i = 0; i < 4; i++, pt++) { + if (is_extended (pt->sys_ind)) { + int lba_start = le32_to_int (pt->start4) + relative; + + print_partition_extended (dev_desc, lba_start, + ext_part_sector == 0 ? lba_start + : relative, + part_num); + } + } + + return; +} + + +/* Print a partition that is relative to its Extended partition table + */ +static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part_sector, + int relative, int part_num, + int which_part, disk_partition_t *info) +{ + unsigned char buffer[DEFAULT_SECTOR_SIZE]; + dos_partition_t *pt; + int i; + + if (dev_desc->block_read (dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) { + printf ("** Can't read partition table on %d:%d **\n", + dev_desc->dev, ext_part_sector); + return -1; + } + if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || + buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { + printf ("bad MBR sector signature 0x%02x%02x\n", + buffer[DOS_PART_MAGIC_OFFSET], + buffer[DOS_PART_MAGIC_OFFSET + 1]); + return -1; + } + + /* Print all primary/logical partitions */ + pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); + for (i = 0; i < 4; i++, pt++) { + /* + * fdisk does not show the extended partitions that + * are not in the MBR + */ + if ((pt->sys_ind != 0) && + (part_num == which_part) && + (is_extended(pt->sys_ind) == 0)) { + info->blksz = 512; + info->start = ext_part_sector + le32_to_int (pt->start4); + info->size = le32_to_int (pt->size4); + switch(dev_desc->if_type) { + case IF_TYPE_IDE: + case IF_TYPE_ATAPI: + sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num); + break; + case IF_TYPE_SCSI: + sprintf ((char *)info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num); + break; + case IF_TYPE_USB: + sprintf ((char *)info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num); + break; + case IF_TYPE_DOC: + sprintf ((char *)info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num); + break; + default: + sprintf ((char *)info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num); + break; + } + /* sprintf(info->type, "%d, pt->sys_ind); */ + sprintf ((char *)info->type, "U-Boot"); + return 0; + } + + /* Reverse engr the fdisk part# assignment rule! */ + if ((ext_part_sector == 0) || + (pt->sys_ind != 0 && !is_extended (pt->sys_ind)) ) { + part_num++; + } + } + + /* Follows the extended partitions */ + pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); + for (i = 0; i < 4; i++, pt++) { + if (is_extended (pt->sys_ind)) { + int lba_start = le32_to_int (pt->start4) + relative; + + return get_partition_info_extended (dev_desc, lba_start, + ext_part_sector == 0 ? lba_start : relative, + part_num, which_part, info); + } + } + return -1; +} + +void print_part_dos (block_dev_desc_t *dev_desc) +{ + printf ("Partition Start Sector Num Sectors Type\n"); + print_partition_extended (dev_desc, 0, 0, 1); +} + +int get_partition_info_dos (block_dev_desc_t *dev_desc, int part, disk_partition_t * info) +{ + return get_partition_info_extended (dev_desc, 0, 0, 1, part, info); +} + + +#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) && CONFIG_DOS_PARTITION */ diff --git a/disk/part_dos.h b/disk/part_dos.h new file mode 100644 index 0000000..ac93f20 --- /dev/null +++ b/disk/part_dos.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DISK_PART_DOS_H +#define _DISK_PART_DOS_H + + +#ifdef CONFIG_ISO_PARTITION +/* Make the buffers bigger if ISO partition support is enabled -- CD-ROMS + have 2048 byte blocks */ +#define DEFAULT_SECTOR_SIZE 2048 +#else +#define DEFAULT_SECTOR_SIZE 512 +#endif +#define DOS_PART_TBL_OFFSET 0x1be +#define DOS_PART_MAGIC_OFFSET 0x1fe +#define DOS_PBR_FSTYPE_OFFSET 0x36 +#define DOS_PBR_MEDIA_TYPE_OFFSET 0x15 +#define DOS_MBR 0 +#define DOS_PBR 1 + +typedef struct dos_partition { + unsigned char boot_ind; /* 0x80 - active */ + unsigned char head; /* starting head */ + unsigned char sector; /* starting sector */ + unsigned char cyl; /* starting cylinder */ + unsigned char sys_ind; /* What partition type */ + unsigned char end_head; /* end head */ + unsigned char end_sector; /* end sector */ + unsigned char end_cyl; /* end cylinder */ + unsigned char start4[4]; /* starting sector counting from 0 */ + unsigned char size4[4]; /* nr of sectors in partition */ +} dos_partition_t; + +#endif /* _DISK_PART_DOS_H */ diff --git a/disk/part_iso.c b/disk/part_iso.c new file mode 100644 index 0000000..0735324 --- /dev/null +++ b/disk/part_iso.c @@ -0,0 +1,260 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "part_iso.h" + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_ISO_PARTITION) + +/* #define ISO_PART_DEBUG */ + +#ifdef ISO_PART_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* enable this if CDs are written with the PowerPC Platform ID */ +#undef CHECK_FOR_POWERPC_PLATTFORM +#define CD_SECTSIZE 2048 + +static unsigned char tmpbuf[CD_SECTSIZE]; + +/* Convert char[4] in little endian format to the host format integer + */ +static inline unsigned long le32_to_int(unsigned char *le32) +{ + return ((le32[3] << 24) + + (le32[2] << 16) + + (le32[1] << 8) + + le32[0] + ); +} +/* Convert char[2] in little endian format to the host format integer + */ +static inline unsigned short le16_to_int(unsigned char *le16) +{ + return ((le16[1] << 8) + + le16[0] + ); +} + + +/* only boot records will be listed as valid partitions */ +int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_partition_t * info, int verb) +{ + int i,offset,entry_num; + unsigned short *chksumbuf; + unsigned short chksum; + unsigned long newblkaddr,blkaddr,lastsect,bootaddr; + iso_boot_rec_t *pbr = (iso_boot_rec_t *)tmpbuf; /* boot record */ + iso_pri_rec_t *ppr = (iso_pri_rec_t *)tmpbuf; /* primary desc */ + iso_val_entry_t *pve = (iso_val_entry_t *)tmpbuf; + iso_init_def_entry_t *pide; + + /* the first sector (sector 0x10) must be a primary volume desc */ + blkaddr=PVD_OFFSET; + if (dev_desc->block_read (dev_desc->dev, PVD_OFFSET, 1, (ulong *) tmpbuf) != 1) + return (-1); + if(ppr->desctype!=0x01) { + if(verb) + printf ("** First descriptor is NOT a primary desc on %d:%d **\n", + dev_desc->dev, part_num); + return (-1); + } + if(strncmp((char *)ppr->stand_ident,"CD001",5)!=0) { + if(verb) + printf ("** Wrong ISO Ident: %s on %d:%d **\n", + ppr->stand_ident,dev_desc->dev, part_num); + return (-1); + } + lastsect= ((ppr->firstsek_LEpathtab1_LE & 0x000000ff)<<24) + + ((ppr->firstsek_LEpathtab1_LE & 0x0000ff00)<< 8) + + ((ppr->firstsek_LEpathtab1_LE & 0x00ff0000)>> 8) + + ((ppr->firstsek_LEpathtab1_LE & 0xff000000)>>24) ; + info->blksz=ppr->secsize_BE; /* assuming same block size for all entries */ + PRINTF(" Lastsect:%08lx\n",lastsect); + for(i=blkaddr;iblock_read (dev_desc->dev, i, 1, (ulong *) tmpbuf) != 1) + return (-1); + if(ppr->desctype==0x00) + break; /* boot entry found */ + if(ppr->desctype==0xff) { + if(verb) + printf ("** No valid boot catalog found on %d:%d **\n", + dev_desc->dev, part_num); + return (-1); + } + } + /* boot entry found */ + if(strncmp(pbr->ident_str,"EL TORITO SPECIFICATION",23)!=0) { + if(verb) + printf ("** Wrong El Torito ident: %s on %d:%d **\n", + pbr->ident_str,dev_desc->dev, part_num); + return (-1); + } + bootaddr=le32_to_int(pbr->pointer); + PRINTF(" Boot Entry at: %08lX\n",bootaddr); + if (dev_desc->block_read (dev_desc->dev, bootaddr, 1, (ulong *) tmpbuf) != 1) { + if(verb) + printf ("** Can't read Boot Entry at %lX on %d:%d **\n", + bootaddr,dev_desc->dev, part_num); + return (-1); + } + chksum=0; + chksumbuf = (unsigned short *)tmpbuf; + for(i=0;i<0x10;i++) + chksum+=((chksumbuf[i] &0xff)<<8)+((chksumbuf[i] &0xff00)>>8); + if(chksum!=0) { + if(verb) + printf ("** Checksum Error in booting catalog validation entry on %d:%d **\n", + dev_desc->dev, part_num); + return (-1); + } + if((pve->key[0]!=0x55)||(pve->key[1]!=0xAA)) { + if(verb) + printf ("** Key 0x55 0xAA error on %d:%d **\n", + dev_desc->dev, part_num); + return(-1); + } +#ifdef CHECK_FOR_POWERPC_PLATTFORM + if(pve->platform!=0x01) { + if(verb) + printf ("** No PowerPC platform CD on %d:%d **\n", + dev_desc->dev, part_num); + return(-1); + } +#endif + /* the validation entry seems to be ok, now search the "partition" */ + entry_num=0; + offset=0x20; + sprintf ((char *)info->type, "U-Boot"); + switch(dev_desc->if_type) { + case IF_TYPE_IDE: + case IF_TYPE_ATAPI: + sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num); + break; + case IF_TYPE_SCSI: + sprintf ((char *)info->name, "sd%c%d\n", 'a' + dev_desc->dev, part_num); + break; + case IF_TYPE_USB: + sprintf ((char *)info->name, "usbd%c%d\n", 'a' + dev_desc->dev, part_num); + break; + case IF_TYPE_DOC: + sprintf ((char *)info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num); + break; + default: + sprintf ((char *)info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num); + break; + } + /* the bootcatalog (including validation Entry) is limited to 2048Bytes + * (63 boot entries + validation entry) */ + while(offset<2048) { + pide=(iso_init_def_entry_t *)&tmpbuf[offset]; + if ((pide->boot_ind==0x88) || + (pide->boot_ind==0x00)) { /* Header Id for default Sections Entries */ + if(entry_num==part_num) { /* part found */ + goto found; + } + entry_num++; /* count partitions Entries (boot and non bootables */ + offset+=0x20; + continue; + } + if ((pide->boot_ind==0x90) || /* Section Header Entry */ + (pide->boot_ind==0x91) || /* Section Header Entry (last) */ + (pide->boot_ind==0x44)) { /* Extension Indicator */ + offset+=0x20; /* skip unused entries */ + } + else { + if(verb) + printf ("** Partition %d not found on device %d **\n", + part_num,dev_desc->dev); + return(-1); + } + } + /* if we reach this point entire sector has been + * searched w/o succsess */ + if(verb) + printf ("** Partition %d not found on device %d **\n", + part_num,dev_desc->dev); + return(-1); +found: + if(pide->boot_ind!=0x88) { + if(verb) + printf ("** Partition %d is not bootable on device %d **\n", + part_num,dev_desc->dev); + return (-1); + } + switch(pide->boot_media) { + case 0x00: /* no emulation */ + info->size=le16_to_int(pide->sec_cnt)>>2; + break; + case 0x01: info->size=2400>>2; break; /* 1.2MByte Floppy */ + case 0x02: info->size=2880>>2; break; /* 1.44MByte Floppy */ + case 0x03: info->size=5760>>2; break; /* 2.88MByte Floppy */ + case 0x04: info->size=2880>>2; break; /* dummy (HD Emulation) */ + default: info->size=0; break; + } + newblkaddr=le32_to_int(pide->rel_block_addr); + info->start=newblkaddr; + PRINTF(" part %d found @ %lx size %lx\n",part_num,newblkaddr,info->size); + return 0; +} + +int get_partition_info_iso(block_dev_desc_t * dev_desc, int part_num, disk_partition_t * info) +{ + return(get_partition_info_iso_verb(dev_desc, part_num, info, 1)); +} + + +void print_part_iso(block_dev_desc_t * dev_desc) +{ + disk_partition_t info; + int i; + if(get_partition_info_iso_verb(dev_desc,0,&info,0)==-1) { + printf("** No boot partition found on device %d **\n",dev_desc->dev); + return; + } + printf("Part Start Sect x Size Type\n"); + i=0; + do { + printf (" %2d %8ld %8ld %6ld %.32s\n", + i, info.start, info.size, info.blksz, info.type); + i++; + } while (get_partition_info_iso_verb(dev_desc,i,&info,0)!=-1); +} + +int test_part_iso (block_dev_desc_t *dev_desc) +{ + disk_partition_t info; + + return(get_partition_info_iso_verb(dev_desc,0,&info,0)); +} + +#endif /* ((CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI)) && defined(CONFIG_ISO_PARTITION) */ diff --git a/disk/part_iso.h b/disk/part_iso.h new file mode 100644 index 0000000..2663578 --- /dev/null +++ b/disk/part_iso.h @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _PART_CD_H +#define _PART_CD_H + +#define BRVD 0x11 +#define PVD_OFFSET 0x10 + + +typedef struct iso_boot_rec { + unsigned char desctype; /* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */ + unsigned char stand_ident[5]; /* "CD001" */ + unsigned char vers; /* Version */ + char ident_str[0x20]; /* Ident String "EL TORITO SPECIFICATION" */ + unsigned char unused[0x20]; /* unused */ + unsigned char pointer[4]; /* absolute pointer to Boot Catalog */ +} iso_boot_rec_t; + + +typedef struct iso_pri_rec { + unsigned char desctype; /* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */ + unsigned char stand_ident[5]; /* "CD001" */ + unsigned char vers; /* Version */ + unsigned char unused; + char sysid[32]; /* system Identifier */ + char volid[32]; /* volume Identifier */ + unsigned char zeros1[8]; /* unused */ + unsigned long volsiz_LE; /* volume size Little Endian */ + unsigned long volsiz_BE; /* volume size Big Endian */ + unsigned char zeros2[32]; /* unused */ + unsigned short setsize_LE; /* volume set size LE */ + unsigned short setsize_BE; /* volume set size BE */ + unsigned short seqnum_LE; /* volume sequence number LE */ + unsigned short seqnum_BE; /* volume sequence number BE */ + unsigned short secsize_LE; /* sector size LE */ + unsigned short secsize_BE; /* sector size BE */ + unsigned long pathtablen_LE;/* Path Table size LE */ + unsigned long pathtablen_BE;/* Path Table size BE */ + unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */ + unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */ + unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */ + unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */ + unsigned char rootdir[34]; /* directory record for root dir */ + char volsetid[128];/* Volume set identifier */ + char pubid[128]; /* Publisher identifier */ + char dataprepid[128]; /* data preparer identifier */ + char appid[128]; /* application identifier */ + char copyr[37]; /* copyright string */ + char abstractfileid[37]; /* abstract file identifier */ + char bibliofileid[37]; /* bibliographic file identifier */ + unsigned char creationdate[17]; /* creation date */ + unsigned char modify[17]; /* modification date */ + unsigned char expire[17]; /* expiring date */ + unsigned char effective[17];/* effective date */ + unsigned char filestruc_ver; /* file structur version */ +} iso_pri_rec_t; + +typedef struct iso_sup_rec { + unsigned char desctype; /* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */ + unsigned char stand_ident[5]; /* "CD001" */ + unsigned char vers; /* Version */ + unsigned char volumeflags; /* if bit 0 = 0 => all escape sequences are according ISO 2375 */ + char sysid[32]; /* system Identifier */ + char volid[32]; /* volume Identifier */ + unsigned char zeros1[8]; /* unused */ + unsigned long volsiz_LE; /* volume size Little Endian */ + unsigned long volsiz_BE; /* volume size Big Endian */ + unsigned char escapeseq[32];/* Escape sequences */ + unsigned short setsize_LE; /* volume set size LE */ + unsigned short setsize_BE; /* volume set size BE */ + unsigned short seqnum_LE; /* volume sequence number LE */ + unsigned short seqnum_BE; /* volume sequence number BE */ + unsigned short secsize_LE; /* sector size LE */ + unsigned short secsize_BE; /* sector size BE */ + unsigned long pathtablen_LE;/* Path Table size LE */ + unsigned long pathtablen_BE;/* Path Table size BE */ + unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */ + unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */ + unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */ + unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */ + unsigned char rootdir[34]; /* directory record for root dir */ + char volsetid[128];/* Volume set identifier */ + char pubid[128]; /* Publisher identifier */ + char dataprepid[128]; /* data preparer identifier */ + char appid[128]; /* application identifier */ + char copyr[37]; /* copyright string */ + char abstractfileid[37]; /* abstract file identifier */ + char bibliofileid[37]; /* bibliographic file identifier */ + unsigned char creationdate[17]; /* creation date */ + unsigned char modify[17]; /* modification date */ + unsigned char expire[17]; /* expiring date */ + unsigned char effective[17];/* effective date */ + unsigned char filestruc_ver; /* file structur version */ +}iso_sup_rec_t; + +typedef struct iso_part_rec { + unsigned char desctype; /* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */ + unsigned char stand_ident[5]; /* "CD001" */ + unsigned char vers; /* Version */ + unsigned char unused; + char sysid[32]; /* system Identifier */ + char volid[32]; /* volume partition Identifier */ + unsigned long partloc_LE; /* volume partition location LE */ + unsigned long partloc_BE; /* volume partition location BE */ + unsigned long partsiz_LE; /* volume partition size LE */ + unsigned long partsiz_BE; /* volume partition size BE */ +}iso_part_rec_t; + + +typedef struct iso_val_entry { + unsigned char header_id; /* Header ID must be 0x01 */ + unsigned char platform; /* Platform: 0=x86, 1=PowerPC, 2=MAC */ + unsigned char res[2]; /* reserved */ + char manu_str[0x18]; /* Ident String of manufacturer/developer */ + unsigned char chk_sum[2]; /* Check sum (all words must be zero) */ + unsigned char key[2]; /* key[0]=55, key[1]=0xAA */ +} iso_val_entry_t; + +typedef struct iso_header_entry { + unsigned char header_id; /* Header ID must be 0x90 or 0x91 */ + unsigned char platform; /* Platform: 0=x86, 1=PowerPC, 2=MAC */ + unsigned char numentry[2]; /* number of entries */ + char id_str[0x1C]; /* Ident String of sectionr */ +} iso_header_entry_t; + + +typedef struct iso_init_def_entry { + unsigned char boot_ind; /* Boot indicator 0x88=bootable 0=not bootable */ + unsigned char boot_media; /* boot Media Type: 0=no Emulation, 1=1.2MB floppy, 2=1.44MB floppy, 3=2.88MB floppy 4=hd (0x80) */ + unsigned char ld_seg[2]; /* Load segment (flat model=addr/10) */ + unsigned char systype; /* System Type copy of byte5 of part table */ + unsigned char res; /* reserved */ + unsigned char sec_cnt[2]; /* sector count in VIRTUAL Blocks (0x200) */ + unsigned char rel_block_addr[4]; /* relative Block address */ +} iso_init_def_entry_t; + + +void print_partition_cd(int dev); + +#endif /* _PART_CD_H */ diff --git a/disk/part_mac.c b/disk/part_mac.c new file mode 100644 index 0000000..8c23e21 --- /dev/null +++ b/disk/part_mac.c @@ -0,0 +1,254 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Support for harddisk partitions. + * + * To be compatible with LinuxPPC and Apple we use the standard Apple + * SCSI disk partitioning scheme. For more information see: + * http://developer.apple.com/techpubs/mac/Devices/Devices-126.html#MARKER-14-92 + */ + +#include +#include +#include +#include "part_mac.h" + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_MAC_PARTITION) + +/* stdlib.h causes some compatibility problems; should fixe these! -- wd */ +#ifndef __ldiv_t_defined +typedef struct { + long int quot; /* Quotient */ + long int rem; /* Remainder */ +} ldiv_t; +extern ldiv_t ldiv (long int __numer, long int __denom); +# define __ldiv_t_defined 1 +#endif + + +static int part_mac_read_ddb (block_dev_desc_t *dev_desc, mac_driver_desc_t *ddb_p); +static int part_mac_read_pdb (block_dev_desc_t *dev_desc, int part, mac_partition_t *pdb_p); + +/* + * Test for a valid MAC partition + */ +int test_part_mac (block_dev_desc_t *dev_desc) +{ + mac_driver_desc_t ddesc; + mac_partition_t mpart; + ulong i, n; + + if (part_mac_read_ddb (dev_desc, &ddesc)) { + /* error reading Driver Desriptor Block, or no valid Signature */ + return (-1); + } + + n = 1; /* assuming at least one partition */ + for (i=1; i<=n; ++i) { + if ((dev_desc->block_read(dev_desc->dev, i, 1, (ulong *)&mpart) != 1) || + (mpart.signature != MAC_PARTITION_MAGIC) ) { + return (-1); + } + /* update partition count */ + n = mpart.map_count; + } + return (0); +} + + +void print_part_mac (block_dev_desc_t *dev_desc) +{ + ulong i, n; + mac_driver_desc_t ddesc; + mac_partition_t mpart; + ldiv_t mb, gb; + + if (part_mac_read_ddb (dev_desc, &ddesc)) { + /* error reading Driver Desriptor Block, or no valid Signature */ + return; + } + + n = ddesc.blk_count; + + mb = ldiv(n, ((1024 * 1024) / ddesc.blk_size)); /* MB */ + /* round to 1 digit */ + mb.rem *= 10 * ddesc.blk_size; + mb.rem += 512 * 1024; + mb.rem /= 1024 * 1024; + + gb = ldiv(10 * mb.quot + mb.rem, 10240); + gb.rem += 512; + gb.rem /= 1024; + + + printf ("Block Size=%d, Number of Blocks=%d, " + "Total Capacity: %ld.%ld MB = %ld.%ld GB\n" + "DeviceType=0x%x, DeviceId=0x%x\n\n" + " #: type name" + " length base (size)\n", + ddesc.blk_size, + ddesc.blk_count, + mb.quot, mb.rem, gb.quot, gb.rem, + ddesc.dev_type, ddesc.dev_id + ); + + n = 1; /* assuming at least one partition */ + for (i=1; i<=n; ++i) { + ulong bytes; + char c; + + printf ("%4ld: ", i); + if (dev_desc->block_read (dev_desc->dev, i, 1, (ulong *)&mpart) != 1) { + printf ("** Can't read Partition Map on %d:%ld **\n", + dev_desc->dev, i); + return; + } + + if (mpart.signature != MAC_PARTITION_MAGIC) { + printf ("** Bad Signature on %d:%ld - " + "expected 0x%04x, got 0x%04x\n", + dev_desc->dev, i, MAC_PARTITION_MAGIC, mpart.signature); + return; + } + + /* update partition count */ + n = mpart.map_count; + + c = 'k'; + bytes = mpart.block_count; + bytes /= (1024 / ddesc.blk_size); /* kB; assumes blk_size == 512 */ + if (bytes >= 1024) { + bytes >>= 10; + c = 'M'; + } + if (bytes >= 1024) { + bytes >>= 10; + c = 'G'; + } + + printf ("%20.32s %-18.32s %10u @ %-10u (%3ld%c)\n", + mpart.type, + mpart.name, + mpart.block_count, + mpart.start_block, + bytes, c + ); + } + + return; +} + + +/* + * Read Device Descriptor Block + */ +static int part_mac_read_ddb (block_dev_desc_t *dev_desc, mac_driver_desc_t *ddb_p) +{ + if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)ddb_p) != 1) { + printf ("** Can't read Driver Desriptor Block **\n"); + return (-1); + } + + if (ddb_p->signature != MAC_DRIVER_MAGIC) { +#if 0 + printf ("** Bad Signature: expected 0x%04x, got 0x%04x\n", + MAC_DRIVER_MAGIC, ddb_p->signature); +#endif + return (-1); + } + return (0); +} + +/* + * Read Partition Descriptor Block + */ +static int part_mac_read_pdb (block_dev_desc_t *dev_desc, int part, mac_partition_t *pdb_p) +{ + int n = 1; + + for (;;) { + /* + * We must always read the descritpor block for + * partition 1 first since this is the only way to + * know how many partitions we have. + */ + if (dev_desc->block_read (dev_desc->dev, n, 1, (ulong *)pdb_p) != 1) { + printf ("** Can't read Partition Map on %d:%d **\n", + dev_desc->dev, n); + return (-1); + } + + if (pdb_p->signature != MAC_PARTITION_MAGIC) { + printf ("** Bad Signature on %d:%d: " + "expected 0x%04x, got 0x%04x\n", + dev_desc->dev, n, MAC_PARTITION_MAGIC, pdb_p->signature); + return (-1); + } + + if (n == part) + return (0); + + if ((part < 1) || (part > pdb_p->map_count)) { + printf ("** Invalid partition %d:%d [%d:1...%d:%d only]\n", + dev_desc->dev, part, + dev_desc->dev, + dev_desc->dev, pdb_p->map_count); + return (-1); + } + + /* update partition count */ + n = part; + } + + /* NOTREACHED */ +} + +int get_partition_info_mac (block_dev_desc_t *dev_desc, int part, disk_partition_t *info) +{ + mac_driver_desc_t ddesc; + mac_partition_t mpart; + + if (part_mac_read_ddb (dev_desc, &ddesc)) { + return (-1); + } + + info->blksz = ddesc.blk_size; + + if (part_mac_read_pdb (dev_desc, part, &mpart)) { + return (-1); + } + + info->start = mpart.start_block; + info->size = mpart.block_count; + memcpy (info->type, mpart.type, sizeof(info->type)); + memcpy (info->name, mpart.name, sizeof(info->name)); + + return (0); +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) && CONFIG_MAC_PARTITION */ diff --git a/disk/part_mac.h b/disk/part_mac.h new file mode 100644 index 0000000..a7ad697 --- /dev/null +++ b/disk/part_mac.h @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * See also Linux sources, fs/partitions/mac.h + * + * This file describes structures and values related to the standard + * Apple SCSI disk partitioning scheme. For more information see: + * http://developer.apple.com/techpubs/mac/Devices/Devices-126.html#MARKER-14-92 + */ + +#ifndef _DISK_PART_MAC_H +#define _DISK_PART_MAC_H + +#define MAC_DRIVER_MAGIC 0x4552 + +/* + * Driver Descriptor Structure, in block 0. + * This block is (and shall remain) 512 bytes long. + * Note that there is an alignment problem for the driver descriptor map! + */ +typedef struct mac_driver_desc { + __u16 signature; /* expected to be MAC_DRIVER_MAGIC */ + __u16 blk_size; /* block size of device */ + __u32 blk_count; /* number of blocks on device */ + __u16 dev_type; /* device type */ + __u16 dev_id; /* device id */ + __u32 data; /* reserved */ + __u16 drvr_cnt; /* number of driver descriptor entries */ + __u16 drvr_map[247]; /* driver descriptor map */ +} mac_driver_desc_t; + +/* + * Device Driver Entry + * (Cannot be included in mac_driver_desc because of alignment problems) + */ +typedef struct mac_driver_entry { + __u32 block; /* block number of starting block */ + __u16 size; /* size of driver, in 512 byte blocks */ + __u16 type; /* OS Type */ +} mac_driver_entry_t; + + +#define MAC_PARTITION_MAGIC 0x504d + +/* type field value for A/UX or other Unix partitions */ +#define APPLE_AUX_TYPE "Apple_UNIX_SVR2" + +/* + * Each Partition Map entry (in blocks 1 ... N) has this format: + */ +typedef struct mac_partition { + __u16 signature; /* expected to be MAC_PARTITION_MAGIC */ + __u16 sig_pad; /* reserved */ + __u32 map_count; /* # blocks in partition map */ + __u32 start_block; /* abs. starting block # of partition */ + __u32 block_count; /* number of blocks in partition */ + uchar name[32]; /* partition name */ + uchar type[32]; /* string type description */ + __u32 data_start; /* rel block # of first data block */ + __u32 data_count; /* number of data blocks */ + __u32 status; /* partition status bits */ + __u32 boot_start; /* first block of boot code */ + __u32 boot_size; /* size of boot code, in bytes */ + __u32 boot_load; /* boot code load address */ + __u32 boot_load2; /* reserved */ + __u32 boot_entry; /* boot code entry point */ + __u32 boot_entry2; /* reserved */ + __u32 boot_cksum; /* boot code checksum */ + uchar processor[16]; /* Type of Processor */ + __u16 part_pad[188]; /* reserved */ +#ifdef CONFIG_ISO_PARTITION + uchar iso_dummy[2048];/* Reservere enough room for an ISO partition block to fit */ +#endif +} mac_partition_t; + +#define MAC_STATUS_BOOTABLE 8 /* partition is bootable */ + +#endif /* _DISK_PART_MAC_H */ diff --git a/doc/I2C_Edge_Conditions b/doc/I2C_Edge_Conditions new file mode 100644 index 0000000..44d3478 --- /dev/null +++ b/doc/I2C_Edge_Conditions @@ -0,0 +1,46 @@ +I2C Edge Conditions: +==================== + + I2C devices may be left in a write state if a read was occuring + and the CPU was reset. This may result in EEPROM data corruption. + + The edge condition is as follows: + 1) A read operation begins. + 2) I2C controller issues a start command. + 3) The I2C writes the device address. + 4) The CPU is reset at this point. + + Once the CPU reinitializes and the read is tried again: + 1) The I2C controller issues a start command. + 2) The I2C controller writes the device address. + 3) The I2C controller writes the offset. + + The EEPROM sees: + 1) START + 2) device address + 3) START "this start is ignored by most EEPROMs" + 4) device address "EEPROM interprets this as offset" + 5) Offset in device, "EEPROM interprets this as data to write" + + The device will interpret this sequence as a WRITE command and + write rubbish into itself, i.e. the "offset" will be interpreted + as data to be written in location "device address". + +Notes +----- +!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!! + +This reset edge condition could possibly be present in every I2C +controller and device available. For boards where a I2C bus reset +function can be implemented a i2c_init_board() function should be +provided and enabled by #define'ing CFG_I2C_INIT_BOARD in your +board's config file. Note that this is NOT necessary when using the +bit-banging I2C driver (common/soft_i2c.c) as this already includes +the I2C bus reset sequence. + + +Many thanks to Bill Hunter for finding this serious BUG. +email to: + +Erik Theisen +Tue, 5 Mar 2002 23:02:19 -0500 (Wed 05:02 MET) diff --git a/doc/README-i386 b/doc/README-i386 new file mode 100644 index 0000000..02b753c --- /dev/null +++ b/doc/README-i386 @@ -0,0 +1,74 @@ +This is my attempt to port U-Boot to the i386 platform. This +work was sponsored by my emplyer, Omicron Ceti AB. http://www.omicron.se + +It is currently capable of booting a linux bzImage from flash on +the AMD SC520 CDP platform. + +It was originally based on PPCBoot taken from the CVS October 28 2002. + +To compile: + +1) Unpack the source tree, either from the complete tarball or + from the virgin snapshot + the patch + +2) Configure the source + $ make sc520_cdp_comfig + $ make + +To use this code on the CDP: +1) Make a suitable kernel, I used 2.4.19 with the mtd-support updated + from the MTD CVS and a patch to allow root=/dev/mtdblock1 which I + included at the end of this file. + The following options in the MTD section might be useful: + + CONFIG_MTD_PHYSMAP=y + CONFIG_MTD_PHYSMAP_START=38100000 + CONFIG_MTD_PHYSMAP_LEN=7a0000 + CONFIG_MTD_PHYSMAP_BUSWIDTH=2 + + +2) Program it in to the CDP flashbank with remon + u-boot.bin should be programmed att offset 0x7e000 and the kernel at + offset 0. If you want to use a jffs2 root file system (not included here), + it should be programmed to offset 0x100000. + + remon> z + remon> yi + remon> ns u-boot.bin 7e0000 + remon> ns bzImage 0 + remon> ns image.jffs2 100000 + +3) Connect a terminal to the 25pin serial port at 9600bps, and start the CDP. + + remon> z + remon> g + +4) U-Boot should output some message and a prompt on the terminal, to + start the kernel issue the following command: + + BOOT> bootm + +5) The kernel should boot, and mount the root filesystem if present. + +We hope you find this stuff useful +Daniel Engström, Omicron Ceti AB, daniel@omicron.se + + +--- linux-2.4.19-orig/init/do_mounts.c Sat Aug 3 02:39:46 2002 ++++ linux-2.4.19/init/do_mounts.c Mon Sep 23 16:21:33 2002 +@@ -224,6 +224,14 @@ + { "ftlc", 0x2c10 }, + { "ftld", 0x2c18 }, + { "mtdblock", 0x1f00 }, ++ { "mtdblock0", 0x1f00 }, ++ { "mtdblock1", 0x1f01 }, ++ { "mtdblock2", 0x1f02 }, ++ { "mtdblock3", 0x1f03 }, ++ { "mtdblock4", 0x1f04 }, ++ { "mtdblock5", 0x1f05 }, ++ { "mtdblock6", 0x1f06 }, ++ { "mtdblock7", 0x1f07 }, + { NULL, 0 } + }; + +------------------- diff --git a/doc/README-integrator b/doc/README-integrator new file mode 100644 index 0000000..ce8a9d2 --- /dev/null +++ b/doc/README-integrator @@ -0,0 +1,110 @@ + + U-Boot for ARM Integrator Development Platforms + + Peter Pearse, ARM Ltd. + peter.pearse@arm.com + www.arm.com + +Manuals available from :- +http://www.arm.com/products/DevTools/Hardware_Platforms.html + +Overview : +-------- +There are two Integrator variants - Integrator/AP and Integrator/CP. +Each may be fitted with a variety of core modules (CMs). +Each CM consists of a ARM processor core and associated hardware e.g + FPGA implementing various controllers and/or register + SSRAM + SDRAM + RAM controllers + clock generators etc. +CMs may be fitted with varying amounts of SDRAM using a DIMM socket. + +Boot Methods : +------------ +Integrator platforms can be configured to use U-Boot in at least three ways :- +a) Run ARM boot monitor, manually run U-Boot image from flash +b) Run ARM boot monitor, automatically run U-Boot image from flash +c) Run U-Boot image direct from flash. + +In cases a) and b) the ARM boot monitor will have configured the CM and mapped +writeable memory to 0x00000000 in the Integrator address space. +U-Boot has to carry out minimal configration before standard code is run. + +In case c) it may be necessary for U-Boot to perform CM dependent initialization. + +Configuring U-Boot : +------------------ + The makefile contains targets for Integrator platforms of both types +fitted with all current variants of CM. If these targets are to be used with +boot process c) above then CONFIG_INIT_CRITICAL may need to be defined to ensure +that the CM is correctly configured. + + There are also targets independent of CM. These may not be suitable for +boot process c) above. They have been preserved for backward compatibility with +existing build processes. + +Code Hierarchy Applied : +---------------------- +Code specific to initialization of a particular ARM processor has been placed in +cpu/arm<>/start.S so that it may be used by other boards. + +However, to avoid duplicating code through all processor files, a generic core +for ARM Integrator CMs has been added + + cpu/arm_intcm + +Otherwise. for example, the standard CM reset via the CM control register would +need placing in each CM processor file...... + +Code specific to the initialization of the CM, rather than the cpu, and initialization +of the Integrator board itself, has been placed in + + board/integrator<>/platform.S + board/integrator<>/integrator<>.c + +Targets +======= +The U-Boot make targets map to the available core modules as below. + +Integrator/AP is no longer available from ARM. +Core modules marked ** are also no longer available. + +ap720t_config ** CM720T +ap920t_config ** CM920T +ap926ejs_config Integrator Core Module for ARM926EJ-STM +ap946es_config Integrator Core Module for ARM946E-STM +cp920t_config ** CM920T +cp926ejs_config Integrator Core Module for ARM926EJ-STM +cp946es_config Integrator Core Module for ARM946E-STM +cp1136_config Integrator Core Module ARM1136JF-S TM + +The final groups of targets are for core modules where no explicit cpu +code has yet been added to U-Boot i.e. they all use the same U-Boot binary +using the generic "arm_intcm" core: + +ap966_config Integrator Core Module for ARM966E-S TM +ap922_config Integrator Core Module for ARM922T TM with ETM +ap922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur +ap7_config ** CM7TDMI +integratorap_config +ap_config + + +cp966_config Integrator Core Module for ARM966E-S TM +cp922_config Integrator Core Module for ARM922T TM with ETM +cp922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur +cp1026_config Integrator Core Module ARM1026EJ-S TM +integratorcp_config +cp_config + +The Makefile targets call board/integrator<>/split_by_variant.sh +to configure various defines in include/configs/integrator<>.h +to indicate the core module & core configuration and ensure that +board/integrator<>/u-boot.lds loads the cpu object first in the U-Boot image. + +********************************* +Because of this mechanism +> make clean +must be run before each change in configuration +********************************* diff --git a/doc/README.AMCC-eval-boards-cleanup b/doc/README.AMCC-eval-boards-cleanup new file mode 100644 index 0000000..901bd87 --- /dev/null +++ b/doc/README.AMCC-eval-boards-cleanup @@ -0,0 +1,31 @@ +--------------------------------------------------------------------- +Cleanup of AMCC eval boards (Walnut/Sycamore, Bubinga, Ebony, Ocotea) +--------------------------------------------------------------------- + +Changes to all AMCC eval boards: +-------------------------------- + +o Changed u-boot image size to 256 kBytes instead of 512 kBytes on most + boards. + +o Use 115200 baud as default console baudrate. + +o Added config option to use redundant environment in flash. This is also + the default setting. Option for environment in nvram is still available + for backward compatibility. + +o Merged board specific flash drivers to common flash driver: + board/amcc/common/flash.c + + +Sycamore/Walnut (one port supporting both eval boards): +------------------------------------------------------- + +o Cleanup to allow easier "cloning" for different (custom) boards: + + o Moved EBC configuration from board specific asm-file "init.S" + using defines in board configuration file. No board specific + asm file needed anymore. + + +August 01 2005, Stefan Roese diff --git a/doc/README.ARM-SoC b/doc/README.ARM-SoC new file mode 100644 index 0000000..0f2677f --- /dev/null +++ b/doc/README.ARM-SoC @@ -0,0 +1,31 @@ +[By Steven Scholz , 16 Aug 2004] + +Since the cpu/ directory gets clobbered with peripheral driver code I +started cleaning up cpu/arm920t. + +I introduced the concept of Soc (system on a chip) into the ./cpu +directory. That means that code that is cpu (i.e. core) specific +resides in + + cpu/$(CPU)/ + +and code that is specific to some SoC (i.e. vendor specific +peripherals around the core) is moved into + + cpu/$(CPU)/$(SOC)/ + +Thus a library/archive "cpu/$(CPU)/$(SOC)/lib$(SOC).a" will be build +and linked. Examples will be + + cpu/arm920t/imx/ + cpu/arm920t/s3c24x0 + +One can select an SoC by passing the name of it to ./mkconfig just +like + + @./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0 + +If there's no VENDOR field (like "mpl" in the above line) one has to +pass NULL instead: + + @./mkconfig $(@:_config=) arm arm920t mx1ads NULL imx diff --git a/doc/README.ARM-memory-map b/doc/README.ARM-memory-map new file mode 100644 index 0000000..e2c4e16 --- /dev/null +++ b/doc/README.ARM-memory-map @@ -0,0 +1,17 @@ +Subject: Re: [PATCH][CFT] bring ARM memory layout in line with the documented behaviour +From: "Anders Larsen" +Date: Thu, 18 Sep 2003 14:15:21 +0200 +To: Wolfgang Denk + +... +>I still see references to _armboot_start, _armboot_end_data, and +>_armboot_end - which role do these play now? Can we get rid of them? +> +>How are they (should they be) set in your memory map above? + +_armboot_start contains the value of TEXT_BASE (0xA07E0000); it seems +TEXT_BASE and _armboot_start are both used for the same purpose in +different parts of the (ARM) code. +Furthermore, the startup code (cpu//start.S) internally uses +another variable (_TEXT_BASE) with the same content as _armboot_start. +I agree that this mess should be cleaned up. diff --git a/doc/README.COBRA5272 b/doc/README.COBRA5272 new file mode 100644 index 0000000..2d3f706 --- /dev/null +++ b/doc/README.COBRA5272 @@ -0,0 +1,156 @@ +File: README.COBRA5272 +Author: Florian Schlote for Sentec elektronik (linux@sentec-elektronik.de) +Contents: This is the README of u-boot (Universal bootloader) for our + COBRA5272 board. +Version: v01.00 +Date: Tue Mar 30 00:28:33 CEST 2004 +License: This document is published under the GNU GPL +______________________________________________________________________ + +CHANGES +040330 v01.00 Creation + +______________________________________________________________________ + + +CONFIGURING +----------- + +1. Modify include/configs/cobra5272.h acc. to your prefs + +2. If necessary, modify board/cobra5272/config.mk (see below) + +3. + +> make cobra5272_config + +> make + + +Please refer to u-boot README (general info, u-boot-x-x-x/README), +to u-boot-x-x-x/doc/README.COBRA5272 and +to the comments in u-boot-x-x-x/include/configs/cobra5272.h + +Configuring u-boot is done by commenting/uncommenting preprocessor defines. + +Default configuration is + + FLASH version (for further info see subsection below) + link address 0xffe00000 + + 16 MB RAM + + network enabled + no default IP address for target, host set, no MACaddress set + + bootdelay for autoboot 5 sec. + autoboot disabled + + +#----------------------------------- +# u-boot FLASH version & RAM version +#----------------------------------- + +The u-boot bootloader for Coldfire processors can be configured + + 1. as a standalone bootloader residing in flash & relocating itself to RAM on + startup automatically => "FLASH version" + + 2. as a RAM version which will not load from flash automatically as it needs a + prestage bootloader ("chainloading") & is running only from the RAM address it + is linked to => "RAM version" + + This version may be very helpful when installing u-boot for the first time + since it can be used to make available s. th. like a "bootstrap + mechanism". + + +How to build the different images: + +------------------------------ +Flash version +------------------------------ + +Compile u-boot + +in dir ./u-boot-x-x-x/ + +please first check: + + in ./include/configs/cobra5272.h + + CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows: + + #if 0 + #define CONFIG_MONITOR_IS_IN_RAM + /* define if monitor is started from a pre-loader */ + #endif + + => u-boot as single bootloader starting from flash + + + in board/cobra5272/config.mk TEXT_BASE should be + + TEXT_BASE = 0xffe00000 + + => linking address for u-boot as single bootloader stored in flash + +then: + + host> make cobra5272_config + rm -f include/config.h include/config.mk + Configuring for cobra5272 board... + host> make + [...] + + host> cp u-boot.bin /tftpboot/u-boot_flash.bin + + +------------------------------ +RAM version +------------------------------ + +in dir ./u-boot-x-x-x/ + + host> make distclean + +please modify the settings: + + in ./include/configs/cobra5272.h + + CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows: + + #if 1 + #define CONFIG_MONITOR_IS_IN_RAM + /*define if monitor is started from a pre-loader */ + #endif + + => u-boot as RAM version, chainloaded by another bootloader or using bdm cable + + + in board/cobra5272/config.mk TEXT_BASE should be + + TEXT_BASE = 0x00020000 + + => target linking address for RAM + + +then: + + host> make cobra5272_config + rm -f include/config.h include/config.mk + Configuring for cobra5272 board... + host> make + [...] + + host> cp u-boot.bin /tftpboot/u-boot_ram.bin + + +---- +HINT +---- + +If the m68k-elf-toolchain & the m68k-bdm-gdb is installed you can run the RAM +version by typing (in dir ./u-boot-x-x-x/) +"board/cobra5272/bdm/load-cobra_uboot" , +in ./u-boot-x-x-x/ the RAM version u-boot (elf format) has to be available. diff --git a/doc/README.EVB-64260-750CX b/doc/README.EVB-64260-750CX new file mode 100644 index 0000000..5ea38ea --- /dev/null +++ b/doc/README.EVB-64260-750CX @@ -0,0 +1,7 @@ +The EVB-64260-750CX is quite similar to the EVB-64260-BP already +supported except the following differences: +* It has an IBM-750CXe soldiered on board instead of the slot-1 in the + BP. +* It has a single PCI male connector instead of the 4 PCI female + connectors on the BP. It also gets power trough the PCI connector. +* It has only a single DIMM slot instead of the 2 slots in the BP. diff --git a/doc/README.INCA-IP b/doc/README.INCA-IP new file mode 100644 index 0000000..1329152 --- /dev/null +++ b/doc/README.INCA-IP @@ -0,0 +1,57 @@ + +Flash programming on the INCA-IP board is complicated because of the +EBU swapping unit. A BDI2000 can be used for flash programming only +if the EBU swapping unit is enabled; otherwise it will not detect the +flash memory. But the EBU swapping unit is disadbled after reset, so +if you program some code to flash with the swapping unit on, it will +not be runnable with the swapping unit off. + +The consequence is that you have to write a pre-swapped image to +flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is +provided in the "tools/" directory. Use it as follows: + + bash$ ./inca-swap-bytes u-boot.bin.swp + +Note that the current BDI config file _disables_ the EBU swapping +unit for the flash bank 0. To enable it, (this is required for the +BDI flash commands to work) uncomment the following line in the +config file: + + ;WM32 0xb8000260 0x404161ff ; Swapping unit enabled + +and comment out + + WM32 0xb8000260 0x004161ff ; Swapping unit disabled + +Alternatively, you can use "mm 0xb8000260 " commands to +enable/disable the swapping unit manually. + +Just for reference, here is the complete sequence of actions we took +to install a U-Boot image into flash. + + 1. ./inca-swap-bytes u-boot.bin.swp + + 2. From BDI: + + mm 0xb8000260 0x404161ff + erase 0xb0000000 + erase 0xb0010000 + prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin + mm 0xb8000260 0x004161ff + go 0xb0000000 + + +Ethernet autonegotiation needs some time to complete. Instead of +delaying the boot process in all cases, we just start the +autonegotiation process when U-Boot comes up and that is all. Most +likely, it will complete by the time the network transfer is +attempted for the first time. In the worst case, if a transfer is +attempted before the autonegotiation is complete, just a single +packet would be lost resulting in a single timeout error, and then +the transfer would proceed normally. So the time that we would have +lost unconditionally waiting for the autonegotiation to complete, we +have to wait only if the file transfer is started immediately after +reset. We've verified that this works for all the clock +configurations. + +(C) 2003 Wolfgang Denk diff --git a/doc/README.IPHASE4539 b/doc/README.IPHASE4539 new file mode 100644 index 0000000..defad30 --- /dev/null +++ b/doc/README.IPHASE4539 @@ -0,0 +1,358 @@ + +This file contains basic information on the port of U-Boot to IPHASE4539 +(Interphase 4539 T1/E1/J1 PMC Communications Controller). +All the changes fit in the common U-Boot infrastructure, providing a new +IPHASE4539-specific entry in makefiles. To build U-Boot for IPHASE4539, +type "make IPHASE4539_config", edit the "include/config_IPHASE4539.h" +file if necessary, then type "make". + + +Common file modifications: +-------------------------- + +The following common files have been modified by this project: +(starting from the ppcboot-1.1.5/ directory) + +MAKEALL - IPHASE4539 entry added +Makefile - IPHASE4539_config entry added + + +New files: +---------- + +The following new files have been added by this project: +(starting from the ppcboot-1.1.5/ directory) + +board/iphase4539/ - board-specific directory +board/iphase4539/Makefile - board-specific makefile +board/iphase4539/config.mk - config file +board/iphase4539/flash.c - flash driver (for AM29LV033C) +board/iphase4539/ppcboot.lds - linker script +board/iphase4539/iphase4539.c - ioport and memory initialization +include/config_IPHASE4539.h - main configuration file + + +New configuration options: +-------------------------- + +CONFIG_IPHASE4539 + + Main board-specific option (should be defined for IPHASE4539). + + +Acceptance criteria tests: +-------------------------- + +The following tests have been conducted to validate the port of U-Boot +to IPHASE4539: + +1. Operation on serial console: + +With SMC1 defined as console in the main configuration file, the U-Boot +output appeared on the serial terminal connected to the 2.5mm stereo jack +connector as follows: + +------------------------------------------------------------------------------ +=> help +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootd - boot default, i.e., run 'bootcmd' +cmp - memory compare +coninfo - print console devices and informations +cp - memory copy +crc32 - checksum calculation +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +iminfo - print header information for application image +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loop - infinite loop on address range +md - memory display +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nm - memory modify (constant address) +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +tftpboot- boot image via network using TFTP protocol + and env variables ipaddr and serverip +version - print monitor version +? - alias for 'help' +=> +------------------------------------------------------------------------------ + + +2. Flash driver operation + +The following sequence was performed to test the "flinfo" command: + +------------------------------------------------------------------------------ +=> flinfo + +Bank # 1: AMD AM29LV033C (32 Mbit, uniform sectors) + Size: 4 MB in 64 Sectors + Sector Start Addresses: + FF800000 (RO) FF810000 (RO) FF820000 FF830000 FF840000 + FF850000 FF860000 FF870000 FF880000 FF890000 + FF8A0000 FF8B0000 FF8C0000 FF8D0000 FF8E0000 + FF8F0000 FF900000 FF910000 FF920000 FF930000 + FF940000 FF950000 FF960000 FF970000 FF980000 + FF990000 FF9A0000 FF9B0000 FF9C0000 FF9D0000 + FF9E0000 FF9F0000 FFA00000 FFA10000 FFA20000 + FFA30000 FFA40000 FFA50000 FFA60000 FFA70000 + FFA80000 FFA90000 FFAA0000 FFAB0000 FFAC0000 + FFAD0000 FFAE0000 FFAF0000 FFB00000 (RO) FFB10000 (RO) + FFB20000 (RO) FFB30000 (RO) FFB40000 FFB50000 FFB60000 + FFB70000 FFB80000 FFB90000 FFBA0000 FFBB0000 + FFBC0000 FFBD0000 FFBE0000 FFBF0000 +------------------------------------------------------------------------------ + +Note: the Hardware Configuration Word (HWC) of the 8260 is on the +first sector of the flash and should not be touched. The U-Boot +environment variables are stored on second sector and U-Boot +starts at the address 0xFFB00000. + + +The following sequence was performed to test the erase command: + +------------------------------------------------------------------------------ +=> cp 0 ff880000 10 +Copy to Flash... done +=> md ff880000 20 +ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> erase ff880000 ff88ffff +Erase Flash from 0xff880000 to 0xff88ffff +.. done +Erased 1 sectors +=> md ff880000 +ff880000: ffffffff ffffffff ffffffff ffffffff ................ +ff880010: ffffffff ffffffff ffffffff ffffffff ................ +ff880020: ffffffff ffffffff ffffffff ffffffff ................ +ff880030: ffffffff ffffffff ffffffff ffffffff ................ +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 ff880000 10 +Copy to Flash... done +=> md ff880000 20 +ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> erase 1:8 +Erase Flash Sectors 8-8 in Bank # 1 +.. done +=> md ff880000 20 +ff880000: ffffffff ffffffff ffffffff ffffffff ................ +ff880010: ffffffff ffffffff ffffffff ffffffff ................ +ff880020: ffffffff ffffffff ffffffff ffffffff ................ +ff880030: ffffffff ffffffff ffffffff ffffffff ................ +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 ff880000 10 +Copy to Flash... done +=> cp 0 ff890000 10 +=> md ff880000 20 +ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> md ff890000 +ff890000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff890010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff890020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff890030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff890040: ffffffff ffffffff ffffffff ffffffff ................ +ff890050: ffffffff ffffffff ffffffff ffffffff ................ +ff890060: ffffffff ffffffff ffffffff ffffffff ................ +ff890070: ffffffff ffffffff ffffffff ffffffff ................ +=> erase 1:8-9 +Erase Flash Sectors 8-9 in Bank # 1 +.... done +=> md ff880000 20 +ff880000: ffffffff ffffffff ffffffff ffffffff ................ +ff880010: ffffffff ffffffff ffffffff ffffffff ................ +ff880020: ffffffff ffffffff ffffffff ffffffff ................ +ff880030: ffffffff ffffffff ffffffff ffffffff ................ +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> md ff890000 +ff890000: ffffffff ffffffff ffffffff ffffffff ................ +ff890010: ffffffff ffffffff ffffffff ffffffff ................ +ff890020: ffffffff ffffffff ffffffff ffffffff ................ +ff890030: ffffffff ffffffff ffffffff ffffffff ................ +ff890040: ffffffff ffffffff ffffffff ffffffff ................ +ff890050: ffffffff ffffffff ffffffff ffffffff ................ +ff890060: ffffffff ffffffff ffffffff ffffffff ................ +ff890070: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test the Flash programming commands: + +------------------------------------------------------------------------------ +=> erase ff880000 ff88ffff +Erase Flash from 0xff880000 to 0xff88ffff +.. done +Erased 1 sectors +=> cp 0 ff880000 10 +Copy to Flash... done +=> md 0 20 +00000000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +00000010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +00000020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +00000030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +00000040: 3c83c000 2c040000 40823378 7c0000a6 <...,...@.3x|... +00000050: 60000030 7c1b03a6 3c00c000 600035ec `..0|...<...`.5. +00000060: 7c1a03a6 4c000064 00000000 00000000 |...L..d........ +00000070: 00000000 00000000 00000000 00000000 ................ +=> md ff880000 20 +ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test storage of the environment +variables in Flash: + +------------------------------------------------------------------------------ +=> setenv foo bar +=> saveenv +Un-Protected 1 sectors +Erasing Flash... +.. done +Erased 1 sectors +Saving Environment to Flash... +Protected 1 sectors +=> reset +... +=> printenv +... +foo=bar +... +Environment size: 339/65532 bytes +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test image download and run over +Ethernet interface (both interfaces were tested): + +------------------------------------------------------------------------------ +=> tftpboot 40000 hello_world.bin +ARP broadcast 1 +TFTP from server 10.0.0.1; our IP address is 10.0.0.8 +Filename 'hello_world.bin'. +Load address: 0x40000 +Loading: ############# +done +Bytes transferred = 65932 (1018c hex) +=> go 40004 +## Starting application at 0x00040004 ... +Hello World +argc = 1 +argv[0] = "40004" +argv[1] = "" +Hit any key to exit ... + +## Application terminated, rc = 0x0 +=> +------------------------------------------------------------------------------ + + +3. Known Problems + +None for the moment. + + +---------------------------------------------------------------------------- +U-Boot and Linux for Interphase 4539 T1/E1/J1 PMC Communications Controller +---------------------------------------------------------------------------- + +U-Boot: + + Configure and make U-Boot: + + $ cd /u-boot + $ make IPHASE4539_config + $ make dep + $ make + $ cp -p u-boot.bin /tftpboot + + Load u-boot.bin into the Flash memory at 0xffb00000. + + +Linux: + + Configure and make Linux: + + $ cd /linux-2.4 + $ make IPHASE4539_config + $ make oldconfig + $ make dep + $ make uImage + $ cp -p arch/ppc/mbxboot/uImage /tftpboot + + Load uImage via tftp and boot it. + + +Flash organisation: + + The following preliminary layout of the Flash memory + is defined: + + 0xff800000 ( 0 - 64 kB): Hardware Configuration Word. + 0xff810000 ( 64 kB - 128 kB): U-Boot Environment. + 0xff820000 ( 128 kB - 3 MB): RAMdisk. + 0xffb00000 ( 3 MB - 3328 kB): U-Boot. + 0xffb40000 (3328 KB - 4 MB): Linux Kernel. + + +For further information concerning U-Boot and Linux please consult +the "DENX U-Boot and Linux Guide". + + +(C) 2002 Wolfgang Grandegger, DENX Software Engineering, wg@denx.de +=================================================================== diff --git a/doc/README.IceCube b/doc/README.IceCube new file mode 100644 index 0000000..5252bc9 --- /dev/null +++ b/doc/README.IceCube @@ -0,0 +1,13 @@ +--------------------------------------------------------------------------- +Build target Flash address | BDI "go" command | Reset Vector +--------------------------------------------------------------------------- +Lite5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100 +Lite5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100 +Lite5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 +icecube_5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100 +icecube_5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100 +icecube_5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 +icecube_5200_DDR 0xFFF00000 | 0xFFF00100 | 0xFFF00100 +icecube_5200_DDR_LOWBOOT 0xFF800000 | 0xFF800100 | 0x00000100 +icecube_5200_DDR_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 +--------------------------------------------------------------------------- diff --git a/doc/README.JFFS2 b/doc/README.JFFS2 new file mode 100644 index 0000000..270da90 --- /dev/null +++ b/doc/README.JFFS2 @@ -0,0 +1,74 @@ +JFFS2 options and usage. +----------------------- + +JFFS2 in U-Boot is a read only implementation of the file system in +Linux with the same name. To use JFFS2 define CFG_CMD_JFFS2. + +The module adds three new commands. +fsload - load binary file from a file system image +fsinfo - print information about file systems +ls - list files in a directory +chpart - change active partition + +If you boot from a partition which is mounted writable, and you +update your boot environment by replacing single files on that +partition, you should also define CFG_JFFS2_SORT_FRAGMENTS. Scanning +the JFFS2 filesystem takes *much* longer with this feature, though. +Sorting is done while inserting into the fragment list, which is +more or less a bubble sort. That algorithm is known to be O(n^2), +thus you should really consider if you can avoid it! + + +There is two ways for JFFS2 to find the disk. The default way uses +the flash_info structure to find the start of a JFFS2 disk (called +partition in the code) and you can change where the partition is with +two defines. + +CFG_JFFS2_FIRST_BANK + defined the first flash bank to use + +CFG_JFFS2_FIRST_SECTOR + defines the first sector to use + + +The second way is to define CFG_JFFS_CUSTOM_PART and implement the +jffs2_part_info(int part_num) function in your board specific files. +In this mode CFG_JFFS2_FIRST_BANK and CFG_JFFS2_FIRST_SECTOR is not +used. + +The input is a partition number starting with 0. +Return a pointer to struct part_info or NULL for error; + +Ex jffs2_part_info() for one partition. +--- +#if defined CFG_JFFS_CUSTOM_PART +#include + +static struct part_info part; + +struct part_info* +jffs2_part_info(int part_num) +{ + if(part_num==0){ + if(part.usr_priv==(void*)1) + return ∂ + + memset(&part, 0, sizeof(part)); + part.offset=(char*)0xFF800000; + part.size=1024*1024*8; + + /* Mark the struct as ready */ + part.usr_priv=(void*)1; + + return ∂ + } + return 0; +} +#endif +--- + +TODO. + + Remove the assumption that JFFS can dereference a pointer + into the disk. The current code do not work with memory holes + or hardware with a sliding window (PCMCIA). diff --git a/doc/README.JFFS2_NAND b/doc/README.JFFS2_NAND new file mode 100644 index 0000000..a836d53 --- /dev/null +++ b/doc/README.JFFS2_NAND @@ -0,0 +1,24 @@ +JFFS2 NAND support: + +To ebable, use the following #define in the board configuration file: + +#define CONFIG_JFFS2_NAND 1 + +Configuration of partitions is similar to how this is done in U-Boot +for JFFS2 on top NOR flash. If a single parition is used, it can be +configured using the following #defines in the configuration file: + +#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ +#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */ +#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */ + +If more than a single partition is desired, the user can define a +CFG_JFFS_CUSTOM_PART macro and implement a + + struct part_info* jffs2_part_info(int part_num) + +function in a board-specific module. An example of such function is +available in common/cmd_jffs2.c + +The default configuration for the DAVE board has a single JFFS2 +partition of 2 MB size. diff --git a/doc/README.MBX b/doc/README.MBX new file mode 100644 index 0000000..679228e --- /dev/null +++ b/doc/README.MBX @@ -0,0 +1,68 @@ +IMPORTANT NOTE - read before defining CFG_USE_OSCCLK in your board + config file!!! + + +WARNING: Wrong settings of this parameter have the potential to +damage hardware by running the MBX's CPU at frequencies that exceed +it's rating and/or overdriving the it's SPLL! + + +Ramblings: +1) Motorola offered 12 different variants of the MBX, 6 823s and 6 860s. +2) Of these 12 variants, only 2 were entry level boards. +3) I believe that the 2 entry level boards were the only ones that + used OSCM clocking. I can't be completely certain of this at this + point. +4) Motorola never offered an MBX that ran faster than 50Mhz. +5) The 10, non-entry level boards, ran at 40Mhz. +6) The EXTCLK input has a minimum clock of 15Mhz for the 823/860. +7) Motorola no longer sells MBXs. + +Based on this information, I can surmise that the default power-on +reset clocking was one of the following three options. + +Multiplier SPLL Options +------------------------------------ +513 OSCM is SPLL input +5 OSCM is SPLL input +1 EXTCLK is SPLL input + +The forth option: + +5 EXTCLK is SPLL input + +is not possible on MBXs. This is because the minimum EXTCLK input +frequency is 15Mhz. 5 * 15Mhz = 75 Mhz. There was no variant that ran +above 50 Mhz. + +The board I have borrowed definitely uses a multiplier of 1 for +EXTCLK and runs at 40Mhz. I even went so far as to put a scope on it. + +One of the two default OSCM modes are most likely what was used on +the entry level boards to cheapen them by eliminating the external +crystal oscillator. + +To add insult to injury, the stupid 860 PLPRCR register retains it's +multiplication factor through hard resets. You can't clear it out +because it is battery backed and once it is set wrong, it stays +wrong. The only way to reset it, so that it takes on it's default +multiplier is to disconnect all power including external, batteries, +as well discharging caps on the board. This precludes the fact that +your 860 may be quite DEAD by this time! + +If you don't setup the multiplication factor for boards that use the +OSCM input, they won't run correctly, but at least they won't be +dead. + +Addtionally, there is no good way to determine the clock input source +from CPU register data. The only way to deal with this is either hard +code it, determine the correct value with some rather NASTY timing +loops, or try to grok it from external data sources. Motorola +firmware opts for the NASTY timing loops, but needs to configure the +serial ports to do so. + + +You may have a legitimate need to define CFG_USE_OSCCLK if your +MBX8xx board is using the OSCM clocking mode. + +You better know what you are doing here. diff --git a/doc/README.MPC866 b/doc/README.MPC866 new file mode 100644 index 0000000..c8256a1 --- /dev/null +++ b/doc/README.MPC866 @@ -0,0 +1,24 @@ +The current implementation allows the user to specify the desired CPU +clock value, in MHz, via an environment variable "cpuclk". + +Four compile-time constants are used: + + CONFIG_8xx_OSCLK - input quartz clock + CFG_8xx_CPUCLK_MIN - minimum allowed CPU clock + CFG_8xx_CPUCLK_MAX - maximum allowed CPU clock + CONFIG_8xx_CPUCLK_DEFAULT - default CPU clock value + +If the "cpuclk" environment variable value is within the CPUCLK_MIN / +CPUCLK_MAX limits, the specified value is used. Otherwise, the +default CPU clock value is set. + +Please make sure you understand what you are doing, and understand +the restrictions of your hardware (board, processor). For example, +ethernet will stop working for CPU clock frequencies below 25 MHz. + +Please note that the new clock-handling code is enabled if +CONFIG_8xx_CPUCLK_DEFAULT is defined. Since this mechanism supports +only MPC866 and newer CPUs, this constant MUST NOT be defined for +MPC823/850/860/862 series. The clock generation algorithm for older +chips is different and has not been implemented yet. If you need it, +your patch is welcome. diff --git a/doc/README.Modem b/doc/README.Modem new file mode 100644 index 0000000..1613c11 --- /dev/null +++ b/doc/README.Modem @@ -0,0 +1,72 @@ +How to configure modem support in U-Boot : + +1. Define modem initialization strings: +--------------------------------------- + +The modem initialization strings have following format: + + mdm_init1= + mdm_init2= + ... + +Turning off modem verbose responses with ATV0 or ATQ1 is not allowed; +U-Boot analyzes only verbose (not numeric) result codes. Modem local +command echo can be turned off (ATE0). + +2. RTS/CTS hardware flow control: +--------------------------------- + +You may wish to enable RTS/CTS hardware flow control, if the board's +UART driver supports it (see CONFIG_HWFLOW compile-time flag in +config/.h). This is controlled by the 'mdm_flow_control' +environment variable: + + 'mdm_flow_control=rts/cts' - to enable RTS/CTS flow control. + 'mdm_flow_control=none ' - to disable. + + +The following are the examples using a Rockwell OEM modem +configuration: + +SAMSUNG # setenv mdm_init1 ATZ - reset the modem to + the factory defaults. +SAMSUNG # setenv mdm_init2 ATS0=1 - set modem into + answer mode. +SAMSUNG # setenv mdm_flow_control rts/cts - enable serial port + flow control +SAMSUNG # saveenv + +The example above initializes modem into answer mode to wait for the +incoming call. RTS/CTS flow control is enabled for the serial port. +(The RTS/CTS flow control is enabled by default on the modem). + + +SAMSUNG # setenv mdm_init1 ATZ +SAMSUNG # setenv mdm_init2 ATS39=0+IFC=0,0 - disable modem + RTS/CTS flow control +SAMSUNG # setenv mdm_init3 ATDT1643973 - dial out the number +SAMSUNG # setenv mdm_flow_control none +SAMSUNG # saveenv + +The example above initializes modem to dial-up connection on the +number 1643973. Flow control is disabled. + +Note that flow control must be turned both off or both on for the +board serial port and for the modem. + + +If the connection was set up successfully, the U-Boot prompt appears +on the terminal console. If not (U-Boot modem was configured for +originating the call and connection was not established) - the board +should be reset for another dial-up try. + + +Note on the SMDK2400 board: +--------------------------- + +Since the board serial ports does not have DTR signal wired, modem +should be told to ignore port DTR setting prior to connection to the +SMDK board, and this setting should be stored in modem NVRAM. For the +Rockwell OEM modem this can to be done with the following command: + +AT&D0&W diff --git a/doc/README.NetConsole b/doc/README.NetConsole new file mode 100644 index 0000000..cc35a0a --- /dev/null +++ b/doc/README.NetConsole @@ -0,0 +1,117 @@ + +In U-Boot, we implemented the networked console via the standard +"devices" mechanism, which means that you can switch between the +serial and network input/output devices by adjusting the 'stdin' and +'stdout' environment variables. To switch to the networked console, +set either of these variables to "nc". Input and output can be +switched independently. + +We use an environment variable 'ncip' to set the IP address and the +port of the destination. The format is :. If is +omitted, the value of 6666 is used. If the env var doesn't exist, the +broadcast address and port 6666 are used. If it is set to an IP +address of 0 (or 0.0.0.0) then no messages are sent to the network. + +For example, if your server IP is 192.168.1.1, you could use: + + => setenv nc 'setenv stdout nc;setenv stdin nc' + => setenv ncip 192.168.1.1 + => saveenv + => run nc + + +On the host side, please use this script to access the console: + ++++++++++++++++++++++++++++++++++++++++++++ +#! /bin/bash + +[ $# = 1 ] || { echo "Usage: $0 target_ip" >&2 ; exit 1 ; } +TARGET_IP=$1 + +stty -icanon -echo intr ^T +nc -u -l -p 6666 < /dev/null & +nc -u ${TARGET_IP} 6666 +stty icanon echo intr ^C ++++++++++++++++++++++++++++++++++++++++++++ + +The script expects exactly one argument, which is interpreted as the +target IP address (or host name, assuming DNS is working). The script +can be interrupted by pressing ^T (CTRL-T). + +It turns out that 'netcat' cannot be used to listen to broadcast +packets. We developed our own tool 'ncb' (see tools directory) that +listens to broadcast packets on a given port and dumps them to the +standard output. use it as follows: + ++++++++++++++++++++++++++++++++++++++++++++ +#! /bin/bash + +[ $# = 1 ] || { echo "Usage: $0 target_ip" >&2 ; exit 1 ; } +TARGET_IP=$1 + +stty icanon echo intr ^T +./ncb & +nc -u ${TARGET_IP} 6666 +stty icanon echo intr ^C +kill 0 ++++++++++++++++++++++++++++++++++++++++++++ + +Again, this script takes exactly one argument, which is interpreted +as the target IP address (or host name, assuming DNS is working). The +script can be interrupted by pressing ^T (CTRL-T). + +The 'ncb' tool can be found in the tools directory; it will not be +built by default so you will ither have to adjust the Makefile or +build it manually. + + +For Linux, the network-based console needs special configuration. +Minimally, the host IP address needs to be specified. This can be +done either via the kernel command line, or by passing parameters +while loading the netconsole.o module (when used in a loadable module +configuration). Please refer to Documentation/networking/logging.txt +file for the original Ingo Molnar's documentation on how to pass +parameters to the loadable module. + +The format of the kernel command line parameter (for the static +configuration) is as follows: + + netconsole=[src-port]@[src-ip]/[],[tgt-port]@/[tgt-macaddr] + +where + + src-port source for UDP packets + (defaults to 6665) + src-ip source IP to use + (defaults to the interface's address) + dev network interface + (defaults to eth0) + tgt-port port for logging agent + (defaults to 6666) + tgt-ip IP address for logging agent + (this is the required parameter) + tgt-macaddr ethernet MAC address for logging agent + (defaults to broadcast) + +Examples: + + netconsole=4444@10.0.0.1/eth1,9353@10.0.0.2/12:34:56:78:9a:bc + +or + + netconsole=@/,@192.168.3.1/ + +Please note that for the Linux networked console to work, the +ethernet interface has to be up by the time the netconsole driver is +initialized. This means that in case of static kernel configuration, +the respective Ethernet interface has to be brought up using the "IP +Autoconfiguration" kernel feature, which is usually done by defaults +in the ELDK-NFS-based environment. + +To browse the Linux network console output, use the 'netcat' tool invoked +as follows: + + nc -u -l -p 6666 + +Note that unlike the U-Boot implementation the Linux netconsole is +unidirectional, i. e. you have console output only in Linux. diff --git a/doc/README.OFT b/doc/README.OFT new file mode 100644 index 0000000..dd1c632 --- /dev/null +++ b/doc/README.OFT @@ -0,0 +1,28 @@ +Open Firmware Flat Tree and usage. +---------------------------------- + +As part of the ongoing cleanup of the Linux PPC trees, the preferred +way to pass bootloader and board setup information is the open +firmware flat tree. + +Please take a look at the following email discussion for some +background. + + http://ozlabs.org/pipermail/linuxppc-dev/2005-August/019408.html + http://ozlabs.org/pipermail/linuxppc-dev/2005-August/019362.html + +The generated tree is part static and part dynamic. + +There is a static part which is compiled in with DTC and a dynamic +part which is programmatically appended. + +You'll need a fairly recent DTC tool, which is available by git at + + rsync://ozlabs.org/dtc/dtc.git + +The xxd binary dumper is needed too which I got from + + ftp://ftp.uni-erlangen.de/pub/utilities/etc/xxd-1.10.tar.gz + + +Pantelis Antoniou, 13 Oct 2005 diff --git a/doc/README.OXC b/doc/README.OXC new file mode 100644 index 0000000..c5db5f8 --- /dev/null +++ b/doc/README.OXC @@ -0,0 +1,24 @@ +This document contains different information about the port +of U-Boot for the OXC board designed by Lucent Technologies, +Inc. + +1. Showing activity + +U-Boot for the OXC board can show its current status using +the Active LED. This feature is configured by the following +options: + +CONFIG_SHOW_ACTIVITY + + When this option is on, the Active LED is blinking fast +when U-Boot runs in the idle loop (i.e. waits for user +commands from serial console) and blinking slow when it +downloads an image over network. When U-Boot loads an image +over serial line the Active LED does not blink and its state +is random (i.e. either constant on or constant off). + +CONFIG_SHOW_BOOT_PROGRESS + + When this option is on, U-Boot switches the Active LED +off before booting an image and switches it on if booting +failed due to some reasons. diff --git a/doc/README.PIP405 b/doc/README.PIP405 new file mode 100644 index 0000000..c5ccf18 --- /dev/null +++ b/doc/README.PIP405 @@ -0,0 +1,385 @@ +U-Boot Changes due to PIP405 Port: +=================================== + +Changed files: +============== +- MAKEALL added PIP405 +- makefile added PIP405 +- common/Makefile added Floppy disk and SCSI support +- common/board.c added PIP405, SCSI support, get_PCI_freq() +- common/bootm.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE +- common/cmd_i2c.c added "defined(CONFIG_PIP405)" +- common/cmd_ide.c changed div. functions to work with block device + description + added ATAPI support +- common/command.c added SCSI and Floppy support +- common/console.c replaced // with /* comments + added console settings from environment +- common/devices.c added ISA keyboard init +- common/main.c corrected the read of bootdelay +- cpu/ppc4xx/405gp_pci.c excluded file from PIP405 +- cpu/ppc4xx/i2c.c added 16bit read write I2C support + added page write +- cpu/ppc4xx/speed.c added get_PCI_freq +- cpu/ppc4xx/start.S added CONFIG_IDENT_STRING +- disk/Makefile added part_iso for CD support +- disk/part.c changed to work with block device description + added ISO CD support + added dev_print (was ide_print in cmd_ide.c) +- disk/part_dos.c changed to work with block device description +- disk/part_mac.c changed to work with block device description +- include/ata.h added ATAPI commands +- include/cmd_bsp.h added PIP405 commands definitions +- include/cmd_condefs.h added Floppy and SCSI support +- include/cmd_disk.h changed to work with block device description +- include/config_LANTEC.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from + CONFIG_CMD_FULL +- include/config_hymod.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from + CONFIG_CMD_FULL +- include/flash.h added INTEL_ID_28F320C3T 0x88C488C4 +- include/i2c.h added "defined(CONFIG_PIP405)" +- include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE +- include/u-boot.h moved partitions functions definitions to part.h + added "defined(CONFIG_PIP405)" + added get_PCI_freq() definition +- rtc/Makefile added MC146818 RTC support +- tools/mkimage.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE + +Added files: +============ +- board/pip405 directory for PIP405 +- board/pip405/cmd_pip405.c board specific commands +- board/pip405/config.mk config make +- board/pip405/flash.c flash support +- board/pip405/init.s start-up +- board/pip405/kbd.c keyboard support +- board/pip405/kbd.h keyboard support +- board/pip405/Makefile Makefile +- board/pip405/pci_piix4.h southbridge definitions +- board/pip405/pci_pip405.c PCI support for PIP405 +- board/pip405/pci_pip405.h PCI support for PIP405 +- board/pip405/pip405.c PIP405 board init +- board/pip405/pip405.h PIP405 board init +- board/pip405/pip405_isa.c ISA support +- board/pip405/pip405_isa.h ISA support +- board/pip405/u-boot.lds Linker description +- board/pip405/u-boot.lds.debugLinker description debug +- board/pip405/sym53c8xx.c SYM53C810A support +- board/pip405/sym53c8xx_defs.h SYM53C810A definitions +- board/pip405/vga_table.h definitions of tables for VGA +- board/pip405/video.c CT69000 support +- board/pip405/video.h CT69000 support +- common/cmd_fdc.c Floppy disk support +- common/cmd_scsi.c SCSI support +- disk/part_iso.c ISO CD ROM support +- disk/part_iso.h ISO CD ROM support +- include/cmd_fdc.h command forFloppy disk support +- include/cmd_scsi.h command for SCSI support +- include/part.h partitions functions definitions + (was part of u-boot.h) +- include/scsi.h SCSI support +- rtc/mc146818.c MC146818 RTC support + + +New Config Switches: +==================== +For detailed description, refer to the corresponding paragraph in the +section "Changes". + +New Commands: +------------- +CFG_CMD_SCSI SCSI Support +CFG_CMF_FDC Floppy disk support + +IDE additions: +-------------- +CONFIG_IDE_RESET_ROUTINE defines that instead of a reset Pin, + the routine ide_set_reset(int idereset) is used. +ATAPI support (experimental) +---------------------------- +CONFIG_ATAPI enables ATAPI Support + +SCSI support (experimental) only SYM53C8xx supported +---------------------------------------------------- +CONFIG_SCSI_SYM53C8XX type of SCSI controller +CFG_SCSI_MAX_LUN 8 number of supported LUNs +CFG_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6) +CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN + maximum of Target devices (multiple LUN support + for boot) + +ISO (CD-Boot) partition support (Experimental) +---------------------------------------------- +CONFIG_ISO_PARTITION CD-boot support + +RTC +---- +CONFIG_RTC_MC146818 MC146818 RTC support + +Keyboard: +--------- +CONFIG_ISA_KEYBOARD Standard (PC-Style) Keyboard support + +Video: +------ +CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip + CONFIG_VIDEO must be defined also + +External peripheral base address: +--------------------------------- +CFG_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts + _must_ be defined for ISA-bus parts + +Identify: +--------- +CONFIG_IDENT_STRING added to the U_BOOT_VERSION String + + +I2C stuff: +---------- +CFG_EEPROM_PAGE_WRITE_ENABLE enables page write of the I2C EEPROM + CFG_EEPROM_PAGE_WRITE_BITS _must_ be + defined. + + +Environment / Console: +---------------------- + +CFG_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from + the values stored in the evironment. + +CFG_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the + values stored in the environment or the standard + serial in/out put should be assigned to the console. + +CFG_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching + are stored in the environment. + +PIP405 specific: +---------------- +CONFIG_PORT_ADDR address used to read boot configuration +MULTI_PURPOSE_SOCKET_ADDR address of the multi purpose socked +SDRAM_EEPROM_WRITE_ADDRESS addresses of the serial presence detect +SDRAM_EEPROM_READ_ADDRESS EEPROM on the SDRAM module. + + +Changes: +======== + +Added Devices: +============== + +Floppy support: +--------------- +Support of a standard floppy disk controller at address CFG_ISA_IO_BASE_ADDRESS ++ 0x3F0. Enabled with define CFG_CMD_FDC. Reads a unformated floppy disk with a +image header (see: mkimage). No interrupts and no DMA are used for this. +Added files: +- common/cmd_fdc.c +- include/cmd_fdc.h + +SCSI support: +------------- +Support for Symbios SYM53C810A chip. Implemented as follows: +- without disconnect +- only asynchrounous +- multiple LUN support (caution, needs a lot of RAM. define CFG_SCSI_MAX_LUN 1 to + save RAM) +- multiple SCSI ID support +- no write support +- analyses the MAC, DOS and ISO pratition similar to the IDE support +- allows booting from SCSI devices similar to the IDE support. +The device numbers are not assigned like they are within the IDE support. The first +device found will get the number 0, the next 1 etc. If all SCSI IDs (0..6) and all +LUNs (8) are enabled, 56 boot devices are possible. This uses a lot of RAM since the +device descriptors are not yet dynamically allocated. 56 boot devices are overkill +anyway. Please refer to the section "Todo" chapter "block device support enhancement". +The SYM53C810A uses 1 Interrupt and must be able of mastering the PCI bus. +Added files: +- common/cmd_scsi.c +- common/board.c +- include/cmd_scsi.h +- include/scsi.h +- board/pip405/sym53c8xx.c +- board/pip405/sym53c8xx_defs.h + +ATAPI support (IDE changes): +---------------------------- +Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c. +To support a hardreset, when the IDE reset pin is not connected to the +CFG_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When +this switch is enabled the routine void ide_set_reset(int idereset) must be +within the board specific files. +Only read from ATAPI devices are supported. +Found out that the function trim_trail cuts off the last character if the whole +string is filled. Added function cpy_ident instead, which trims also leading +spaces and copies the string in the buffer. +Changed files: +- common/cmd_ide.c +- include/ata.h + +ISO partition support: +---------------------- +Added CD boot support for El-Torito bootable ISO CDs. The bootfile image must contain +the U-Boot image header. Since CDs do not have "partitions", the boot partition is 0. +The bootcatalog feature has not been tested so far. CD Boot is supported for ATAPI +("diskboot") and SCSI ("scsiboot") devices. +Added files: +- disk/iso_part.c +- disk/iso_part.h + +Block device changes: +--------------------- +To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter +block_dev_desc will be used when accessing the functions in these files. The block +device descriptor (block_dev_desc) contains a pointer to the read routine of the +device, which will be used to read blocks from the device. +Renamed function ide_print to dev_print and moved it to the file disk/part.c to use +it for IDE ATAPI and SCSI devices. +Please refer to the section "Todo" chapter "block device support enhancement". +Added files: +- include/part.h +changed files: +- disk/dos_part.c +- disk/dos_part.h +- disk/mac_part.c +- disk/mac_part.h +- disk/part.c +- common/cmd_ide.c +- include/u-boot.h + + +MC146818 RTC support: +--------------------- +Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO +base address must be defined with CFG_ISA_IO_BASE_ADDRESS. +Added files: +- rtc/mc146818.c + +Standard ISA bus Keyboard support: +---------------------------------- +Added support for the standard PC kyeboard controller. For the PIP405 the superIO +controller must be set up previously. The keyboard uses the standard ISA IRQ, so +the ISA PIC must also be set up. +Added files: +- board/pip405/kbd.c +- board/pip405/kbd.h +- board/pip405/pip405_isa.c +- board/pip405/pip405_isa.h + +Chips and Technologie 69000 VGA controller support: +--------------------------------------------------- +Added support for the CT69000 VGA controller. +Added files: +- board/pip405/video.c +- board/pip405/video.h +- board/pip405/vga_table.h + + +Changed Items: +============== + +Identify: +--------- +Added the config variable CONFIG_IDENT_STRING which will be added to the +"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate +and custom versions. +Changed files: +- cpu/ppc4xx/start.s + +Firmware Image: +--------------- +Added IH_OS_U_BOOT and IH_TYPE_FIRMWARE to the image definitions to allows the +U-Boot update with prior CRC check. +Changed files: +- include/image.h +- tools/mkimage.c +- common/cmd_bootm.c + +Correct PCI Frequency for PPC405: +--------------------------------- +Added function (in cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU. +The PCI Frequency will now be set correct in the board description in common/board.c. +(was set to the busfreq before). +Changed files: +- cpu/ppc4xx/speed.c +- common/board.c + +I2C Stuff: +---------- +Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c. +Added 16bit read/write support for I2C (PPC405), and page write to +I2C EEPROM if defined CFG_EEPROM_PAGE_WRITE_ENABLE. +Changed files: +- cpu/ppc4xx/i2c.c +- common/cmd_i2c.c + +Environment / Console: +---------------------- +Although in README.console described, the U-Boot has not assinged the values +found in the environment to the console. Corrected this behavior, but only if +CFG_CONSOLE_IS_IN_ENV is defined. +If CFG_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the +values stored in the environment or the standard serial in/output should be +assigned to the console. This is useful if the environment values are not correct. +If CFG_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at +start-up time will be written to the environment. This means that if the +environment values are overwritten by the overwrite_console() routine, they will be +stored in the environment. +Changed files: +- common/console.c + +Correct bootdelay intepretation: +-------------------------------- +Changed bootdelay read from the environment from simple_strtoul (unsigned) to +simple_strtol (signed), to be able to get a bootdelay of -1. +Changed files: +- common/main.c + +Todo: +===== + +Block device support enhancement: +--------------------------------- +Consider to unify the block device handling. Instead of using diskboot for IDE, +scsiboot for SCSI and fdcboot for floppy disks, it would make sense to use only +one command ("devboot" ???) with a parameter of the desired device ("hda1", "sda1", +"fd0" ???) to boot from. The other ide commands can be handled in the same way +("dev hda read.." instead of "ide read.." or "dev sda read.." instead of +"scsi read..."). Todo this, a common way of assign a block device to its name +(first found ide device = hda, second found hdb etc., or hda is device 0 on bus 0, +hdb is device 1 on bus 0 etc.) as well as the names (hdx for ide, sdx for scsi, fx for +floppy ???) must be defined. +Maybe there are better ideas to do this. + +Console assingment: +------------------- +Consider to initialize and assign the console stdin, stdout and stderr as soon as +possible to see the boot messages also on an other console than serial. + + +Todo for PIP405: +================ + +LCD support for VGA: +-------------------- +Add LCD support for the CT69000 + +Default environment: +-------------------- +Consider to write a default environment to the OTP part of the EEPROM and use it +if the normal environment is not valid. Useful for serial# and ethaddr values. + +Watchdog: +--------- +Implement Watchdog. + +Files clean-up: +--------------- +Following files needs to be cleaned up: +- cmd_pip405.c +- flash.c +- pci_pip405.c +- pip405.c +- pip405_isa.c +Consider to split up the files in their functions. diff --git a/doc/README.POST b/doc/README.POST new file mode 100644 index 0000000..a81e079 --- /dev/null +++ b/doc/README.POST @@ -0,0 +1,736 @@ +Power-On-Self-Test support in U-Boot +------------------------------------ + +This project is to support Power-On-Self-Test (POST) in U-Boot. + +1. High-level requirements + +The key requirements for this project are as follows: + +1) The project shall develop a flexible framework for implementing + and running Power-On-Self-Test in U-Boot. This framework shall + possess the following features: + + o) Extensibility + + The framework shall allow adding/removing/replacing POST tests. + Also, standalone POST tests shall be supported. + + o) Configurability + + The framework shall allow run-time configuration of the lists + of tests running on normal/power-fail booting. + + o) Controllability + + The framework shall support manual running of the POST tests. + +2) The results of tests shall be saved so that it will be possible to + retrieve them from Linux. + +3) The following POST tests shall be developed for MPC823E-based + boards: + + o) CPU test + o) Cache test + o) Memory test + o) Ethernet test + o) Serial channels test + o) Watchdog timer test + o) RTC test + o) I2C test + o) SPI test + o) USB test + +4) The LWMON board shall be used for reference. + +2. Design + +This section details the key points of the design for the project. +The whole project can be divided into two independent tasks: +enhancing U-Boot/Linux to provide a common framework for running POST +tests and developing such tests for particular hardware. + +2.1. Hardware-independent POST layer + +A new optional module will be added to U-Boot, which will run POST +tests and collect their results at boot time. Also, U-Boot will +support running POST tests manually at any time by executing a +special command from the system console. + +The list of available POST tests will be configured at U-Boot build +time. The POST layer will allow the developer to add any custom POST +tests. All POST tests will be divided into the following groups: + + 1) Tests running on power-on booting only + + This group will contain those tests that run only once on + power-on reset (e.g. watchdog test) + + 2) Tests running on normal booting only + + This group will contain those tests that do not take much + time and can be run on the regular basis (e.g. CPU test) + + 3) Tests running in special "slow test mode" only + + This group will contain POST tests that consume much time + and cannot be run regularly (e.g. strong memory test, I2C test) + + 4) Manually executed tests + + This group will contain those tests that can be run manually. + +If necessary, some tests may belong to several groups simultaneously. +For example, SDRAM test may run in both normal and "slow test" mode. +In normal mode, SDRAM test may perform a fast superficial memory test +only, while running in slow test mode it may perform a full memory +check-up. + +Also, all tests will be discriminated by the moment they run at. +Specifically, the following groups will be singled out: + + 1) Tests running before relocating to RAM + + These tests will run immediately after initializing RAM + as to enable modifying it without taking care of its + contents. Basically, this group will contain memory tests + only. + + 2) Tests running after relocating to RAM + + These tests will run immediately before entering the main + loop as to guarantee full hardware initialization. + +The POST layer will also distinguish a special group of tests that +may cause system rebooting (e.g. watchdog test). For such tests, the +layer will automatically detect rebooting and will notify the test +about it. + +2.1.1. POST layer interfaces + +This section details the interfaces between the POST layer and the +rest of U-Boot. + +The following flags will be defined: + +#define POST_POWERON 0x01 /* test runs on power-on booting */ +#define POST_NORMAL 0x02 /* test runs on normal booting */ +#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */ +#define POST_POWERTEST 0x08 /* test runs after watchdog reset */ +#define POST_ROM 0x100 /* test runs in ROM */ +#define POST_RAM 0x200 /* test runs in RAM */ +#define POST_MANUAL 0x400 /* test can be executed manually */ +#define POST_REBOOT 0x800 /* test may cause rebooting */ +#define POST_PREREL 0x1000 /* test runs before relocation */ + +The POST layer will export the following interface routines: + + o) int post_run(bd_t *bd, char *name, int flags); + + This routine will run the test (or the group of tests) specified + by the name and flag arguments. More specifically, if the name + argument is not NULL, the test with this name will be performed, + otherwise all tests running in ROM/RAM (depending on the flag + argument) will be executed. This routine will be called at least + twice with name set to NULL, once from board_init_f() and once + from board_init_r(). The flags argument will also specify the + mode the test is executed in (power-on, normal, power-fail, + manual). + + o) void post_reloc(ulong offset); + + This routine will be called from board_init_r() and will + relocate the POST test table. + + o) int post_info(char *name); + + This routine will print the list of all POST tests that can be + executed manually if name is NULL, and the description of a + particular test if name is not NULL. + + o) int post_log(char *format, ...); + + This routine will be called from POST tests to log their + results. Basically, this routine will print the results to + stderr. The format of the arguments and the return value + will be identical to the printf() routine. + +Also, the following board-specific routines will be called from the +U-Boot common code: + + o) int board_power_mode(void) + + This routine will return the mode the system is running in + (POST_POWERON, POST_NORMAL or POST_SHUTDOWN). + + o) void board_poweroff(void) + + This routine will turn off the power supply of the board. It + will be called on power-fail booting after running all POST + tests. + + o) int post_hotkeys_pressed(gd_t *gd) + + This routine will scan the keyboard to detect if a magic key + combination has been pressed, or otherwise detect if the + power-on long-running tests shall be executed or not ("normal" + versus "slow" test mode). + +The list of available POST tests be kept in the post_tests array +filled at U-Boot build time. The format of entry in this array will +be as follows: + +struct post_test { + char *name; + char *cmd; + char *desc; + int flags; + int (*test)(bd_t *bd, int flags); +}; + + o) name + + This field will contain a short name of the test, which will be + used in logs and on listing POST tests (e.g. CPU test). + + o) cmd + + This field will keep a name for identifying the test on manual + testing (e.g. cpu). For more information, refer to section + "Command line interface". + + o) desc + + This field will contain a detailed description of the test, + which will be printed on user request. For more information, see + section "Command line interface". + + o) flags + + This field will contain a combination of the bit flags described + above, which will specify the mode the test is running in + (power-on, normal, power-fail or manual mode), the moment it + should be run at (before or after relocating to RAM), whether it + can cause system rebooting or not. + + o) test + + This field will contain a pointer to the routine that will + perform the test, which will take 2 arguments. The first + argument will be a pointer to the board info structure, while + the second will be a combination of bit flags specifying the + mode the test is running in (POST_POWERON, POST_NORMAL, + POST_SLOWTEST, POST_MANUAL) and whether the last execution of + the test caused system rebooting (POST_REBOOT). The routine will + return 0 on successful execution of the test, and 1 if the test + failed. + +The lists of the POST tests that should be run at power-on/normal/ +power-fail booting will be kept in the environment. Namely, the +following environment variables will be used: post_poweron, +powet_normal, post_slowtest. + +2.1.2. Test results + +The results of tests will be collected by the POST layer. The POST +log will have the following format: + +... +-------------------------------------------- +START + +[PASSED|FAILED] +-------------------------------------------- +... + +Basically, the results of tests will be printed to stderr. This +feature may be enhanced in future to spool the log to a serial line, +save it in non-volatile RAM (NVRAM), transfer it to a dedicated +storage server and etc. + +2.1.3. Integration issues + +All POST-related code will be #ifdef'ed with the CONFIG_POST macro. +This macro will be defined in the config_.h file for those +boards that need POST. The CONFIG_POST macro will contain the list of +POST tests for the board. The macro will have the format of array +composed of post_test structures: + +#define CONFIG_POST \ + { + "On-board peripherals test", "board", \ + " This test performs full check-up of the " \ + "on-board hardware.", \ + POST_RAM | POST_SLOWTEST, \ + &board_post_test \ + } + +A new file, post.h, will be created in the include/ directory. This +file will contain common POST declarations and will define a set of +macros that will be reused for defining CONFIG_POST. As an example, +the following macro may be defined: + +#define POST_CACHE \ + { + "Cache test", "cache", \ + " This test verifies the CPU cache operation.", \ + POST_RAM | POST_NORMAL, \ + &cache_post_test \ + } + +A new subdirectory will be created in the U-Boot root directory. It +will contain the source code of the POST layer and most of POST +tests. Each POST test in this directory will be placed into a +separate file (it will be needed for building standalone tests). Some +POST tests (mainly those for testing peripheral devices) will be +located in the source files of the drivers for those devices. This +way will be used only if the test subtantially uses the driver. + +2.1.4. Standalone tests + +The POST framework will allow to develop and run standalone tests. A +user-space library will be developed to provide the POST interface +functions to standalone tests. + +2.1.5. Command line interface + +A new command, diag, will be added to U-Boot. This command will be +used for listing all available hardware tests, getting detailed +descriptions of them and running these tests. + +More specifically, being run without any arguments, this command will +print the list of all available hardware tests: + +=> diag +Available hardware tests: + cache - cache test + cpu - CPU test + enet - SCC/FCC ethernet test +Use 'diag [ []] ... ' to get more info. +Use 'diag run [ []] ... ' to run tests. +=> + +If the first argument to the diag command is not 'run', detailed +descriptions of the specified tests will be printed: + +=> diag cpu cache +cpu - CPU test + This test verifies the arithmetic logic unit of CPU. +cache - cache test + This test verifies the CPU cache operation. +=> + +If the first argument to diag is 'run', the specified tests will be +executed. If no tests are specified, all available tests will be +executed. + +It will be prohibited to execute tests running in ROM manually. The +'diag' command will not display such tests and/or run them. + +2.1.6. Power failure handling + +The Linux kernel will be modified to detect power failures and +automatically reboot the system in such cases. It will be assumed +that the power failure causes a system interrupt. + +To perform correct system shutdown, the kernel will register a +handler of the power-fail IRQ on booting. Being called, the handler +will run /sbin/reboot using the call_usermodehelper() routine. +/sbin/reboot will automatically bring the system down in a secure +way. This feature will be configured in/out from the kernel +configuration file. + +The POST layer of U-Boot will check whether the system runs in +power-fail mode. If it does, the system will be powered off after +executing all hardware tests. + +2.1.7. Hazardous tests + +Some tests may cause system rebooting during their execution. For +some tests, this will indicate a failure, while for the Watchdog +test, this means successful operation of the timer. + +In order to support such tests, the following scheme will be +implemented. All the tests that may cause system rebooting will have +the POST_REBOOT bit flag set in the flag field of the correspondent +post_test structure. Before starting tests marked with this bit flag, +the POST layer will store an identification number of the test in a +location in IMMR. On booting, the POST layer will check the value of +this variable and if it is set will skip over the tests preceding the +failed one. On second execution of the failed test, the POST_REBOOT +bit flag will be set in the flag argument to the test routine. This +will allow to detect system rebooting on the previous iteration. For +example, the watchdog timer test may have the following +declaration/body: + +... +#define POST_WATCHDOG \ + { + "Watchdog timer test", "watchdog", \ + " This test checks the watchdog timer.", \ + POST_RAM | POST_POWERON | POST_REBOOT, \ + &watchdog_post_test \ + } +... + +... +int watchdog_post_test(bd_t *bd, int flags) +{ + unsigned long start_time; + + if (flags & POST_REBOOT) { + /* Test passed */ + return 0; + } else { + /* disable interrupts */ + disable_interrupts(); + /* 10-second delay */ + ... + /* if we've reached this, the watchdog timer does not work */ + enable_interrupts(); + return 1; + } +} +... + +2.2. Hardware-specific details + +This project will also develop a set of POST tests for MPC8xx- based +systems. This section provides technical details of how it will be +done. + +2.2.1. Generic PPC tests + +The following generic POST tests will be developed: + + o) CPU test + + This test will check the arithmetic logic unit (ALU) of CPU. The + test will take several milliseconds and will run on normal + booting. + + o) Cache test + + This test will verify the CPU cache (L1 cache). The test will + run on normal booting. + + o) Memory test + + This test will examine RAM and check it for errors. The test + will always run on booting. On normal booting, only a limited + amount of RAM will be checked. On power-fail booting a fool + memory check-up will be performed. + +2.2.1.1. CPU test + +This test will verify the following ALU instructions: + + o) Condition register istructions + + This group will contain: mtcrf, mfcr, mcrxr, crand, crandc, + cror, crorc, crxor, crnand, crnor, creqv, mcrf. + + The mtcrf/mfcr instructions will be tested by loading different + values into the condition register (mtcrf), moving its value to + a general-purpose register (mfcr) and comparing this value with + the expected one. The mcrxr instruction will be tested by + loading a fixed value into the XER register (mtspr), moving XER + value to the condition register (mcrxr), moving it to a + general-purpose register (mfcr) and comparing the value of this + register with the expected one. The rest of instructions will be + tested by loading a fixed value into the condition register + (mtcrf), executing each instruction several times to modify all + 4-bit condition fields, moving the value of the conditional + register to a general-purpose register (mfcr) and comparing it + with the expected one. + + o) Integer compare instructions + + This group will contain: cmp, cmpi, cmpl, cmpli. + + To verify these instructions the test will run them with + different combinations of operands, read the condition register + value and compare it with the expected one. More specifically, + the test will contain a pre-built table containing the + description of each test case: the instruction, the values of + the operands, the condition field to save the result in and the + expected result. + + o) Arithmetic instructions + + This group will contain: add, addc, adde, addme, addze, subf, + subfc, subfe, subme, subze, mullw, mulhw, mulhwu, divw, divwu, + extsb, extsh. + + The test will contain a pre-built table of instructions, + operands, expected results and expected states of the condition + register. For each table entry, the test will cyclically use + different sets of operand registers and result registers. For + example, for instructions that use 3 registers on the first + iteration r0/r1 will be used as operands and r2 for result. On + the second iteration, r1/r2 will be used as operands and r3 as + for result and so on. This will enable to verify all + general-purpose registers. + + o) Logic instructions + + This group will contain: and, andc, andi, andis, or, orc, ori, + oris, xor, xori, xoris, nand, nor, neg, eqv, cntlzw. + + The test scheme will be identical to that from the previous + point. + + o) Shift instructions + + This group will contain: slw, srw, sraw, srawi, rlwinm, rlwnm, + rlwimi + + The test scheme will be identical to that from the previous + point. + + o) Branch instructions + + This group will contain: b, bl, bc. + + The first 2 instructions (b, bl) will be verified by jumping to + a fixed address and checking whether control was transfered to + that very point. For the bl instruction the value of the link + register will be checked as well (using mfspr). To verify the bc + instruction various combinations of the BI/BO fields, the CTR + and the condition register values will be checked. The list of + such combinations will be pre-built and linked in U-Boot at + build time. + + o) Load/store instructions + + This group will contain: lbz(x)(u), lhz(x)(u), lha(x)(u), + lwz(x)(u), stb(x)(u), sth(x)(u), stw(x)(u). + + All operations will be performed on a 16-byte array. The array + will be 4-byte aligned. The base register will point to offset + 8. The immediate offset (index register) will range in [-8 ... + +7]. The test cases will be composed so that they will not cause + alignment exceptions. The test will contain a pre-built table + describing all test cases. For store instructions, the table + entry will contain: the instruction opcode, the value of the + index register and the value of the source register. After + executing the instruction, the test will verify the contents of + the array and the value of the base register (it must change for + "store with update" instructions). For load instructions, the + table entry will contain: the instruction opcode, the array + contents, the value of the index register and the expected value + of the destination register. After executing the instruction, + the test will verify the value of the destination register and + the value of the base register (it must change for "load with + update" instructions). + + o) Load/store multiple/string instructions + + +The CPU test will run in RAM in order to allow run-time modification +of the code to reduce the memory footprint. + +2.2.1.2 Special-Purpose Registers Tests + +TBD. + +2.2.1.3. Cache test + +To verify the data cache operation the following test scenarios will +be used: + + 1) Basic test #1 + + - turn on the data cache + - switch the data cache to write-back or write-through mode + - invalidate the data cache + - write the negative pattern to a cached area + - read the area + + The negative pattern must be read at the last step + + 2) Basic test #2 + + - turn on the data cache + - switch the data cache to write-back or write-through mode + - invalidate the data cache + - write the zero pattern to a cached area + - turn off the data cache + - write the negative pattern to the area + - turn on the data cache + - read the area + + The negative pattern must be read at the last step + + 3) Write-through mode test + + - turn on the data cache + - switch the data cache to write-through mode + - invalidate the data cache + - write the zero pattern to a cached area + - flush the data cache + - write the negative pattern to the area + - turn off the data cache + - read the area + + The negative pattern must be read at the last step + + 4) Write-back mode test + + - turn on the data cache + - switch the data cache to write-back mode + - invalidate the data cache + - write the negative pattern to a cached area + - flush the data cache + - write the zero pattern to the area + - invalidate the data cache + - read the area + + The negative pattern must be read at the last step + +To verify the instruction cache operation the following test +scenarios will be used: + + 1) Basic test #1 + + - turn on the instruction cache + - unlock the entire instruction cache + - invalidate the instruction cache + - lock a branch instruction in the instruction cache + - replace the branch instruction with "nop" + - jump to the branch instruction + - check that the branch instruction was executed + + 2) Basic test #2 + + - turn on the instruction cache + - unlock the entire instruction cache + - invalidate the instruction cache + - jump to a branch instruction + - check that the branch instruction was executed + - replace the branch instruction with "nop" + - invalidate the instruction cache + - jump to the branch instruction + - check that the "nop" instruction was executed + +The CPU test will run in RAM in order to allow run-time modification +of the code. + +2.2.1.4. Memory test + +The memory test will verify RAM using sequential writes and reads +to/from RAM. Specifically, there will be several test cases that will +use different patterns to verify RAM. Each test case will first fill +a region of RAM with one pattern and then read the region back and +compare its contents with the pattern. The following patterns will be +used: + + 1) zero pattern (0x00000000) + 2) negative pattern (0xffffffff) + 3) checkerboard pattern (0x55555555, 0xaaaaaaaa) + 4) bit-flip pattern ((1 << (offset % 32)), ~(1 << (offset % 32))) + 5) address pattern (offset, ~offset) + +Patterns #1, #2 will help to find unstable bits. Patterns #3, #4 will +be used to detect adherent bits, i.e. bits whose state may randomly +change if adjacent bits are modified. The last pattern will be used +to detect far-located errors, i.e. situations when writing to one +location modifies an area located far from it. Also, usage of the +last pattern will help to detect memory controller misconfigurations +when RAM represents a cyclically repeated portion of a smaller size. + +Being run in normal mode, the test will verify only small 4Kb regions +of RAM around each 1Mb boundary. For example, for 64Mb RAM the +following areas will be verified: 0x00000000-0x00000800, +0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- +0x04000000. If the test is run in power-fail mode, it will verify the +whole RAM. + +The memory test will run in ROM before relocating U-Boot to RAM in +order to allow RAM modification without saving its contents. + +2.2.2. Common tests + +This section describes tests that are not based on any hardware +peculiarities and use common U-Boot interfaces only. These tests do +not need any modifications for porting them to another board/CPU. + +2.2.2.1. I2C test + +For verifying the I2C bus, a full I2C bus scanning will be performed +using the i2c_probe() routine. If any I2C device is found, the test +will be considered as passed, otherwise failed. This particular way +will be used because it provides the most common method of testing. +For example, using the internal loopback mode of the CPM I2C +controller for testing would not work on boards where the software +I2C driver (also known as bit-banged driver) is used. + +2.2.2.2. Watchdog timer test + +To test the watchdog timer the scheme mentioned above (refer to +section "Hazardous tests") will be used. Namely, this test will be +marked with the POST_REBOOT bit flag. On the first iteration, the +test routine will make a 10-second delay. If the system does not +reboot during this delay, the watchdog timer is not operational and +the test fails. If the system reboots, on the second iteration the +POST_REBOOT bit will be set in the flag argument to the test routine. +The test routine will check this bit and report a success if it is +set. + +2.2.2.3. RTC test + +The RTC test will use the rtc_get()/rtc_set() routines. The following +features will be verified: + + o) Time uniformity + + This will be verified by reading RTC in polling within a short + period of time (5-10 seconds). + + o) Passing month boundaries + + This will be checked by setting RTC to a second before a month + boundary and reading it after its passing the boundary. The test + will be performed for both leap- and nonleap-years. + +2.2.3. MPC8xx peripherals tests + +This project will develop a set of tests verifying the peripheral +units of MPC8xx processors. Namely, the following controllers of the +MPC8xx communication processor module (CPM) will be tested: + + o) Serial Management Controllers (SMC) + + o) Serial Communication Controllers (SCC) + +2.2.3.1. Ethernet tests (SCC) + +The internal (local) loopback mode will be used to test SCC. To do +that the controllers will be configured accordingly and several +packets will be transmitted. These tests may be enhanced in future to +use external loopback for testing. That will need appropriate +reconfiguration of the physical interface chip. + +The test routines for the SCC ethernet tests will be located in +cpu/mpc8xx/scc.c. + +2.2.3.2. UART tests (SMC/SCC) + +To perform these tests the internal (local) loopback mode will be +used. The SMC/SCC controllers will be configured to connect the +transmitter output to the receiver input. After that, several bytes +will be transmitted. These tests may be enhanced to make to perform +"external" loopback test using a loopback cable. In this case, the +test will be executed manually. + +The test routine for the SMC/SCC UART tests will be located in +cpu/mpc8xx/serial.c. + +2.2.3.3. USB test + +TBD + +2.2.3.4. SPI test + +TBD diff --git a/doc/README.PXA_CF b/doc/README.PXA_CF new file mode 100644 index 0000000..e443d39 --- /dev/null +++ b/doc/README.PXA_CF @@ -0,0 +1,48 @@ + +These are brief instructions on how to add support for CF adapters to +custom designed PXA boards. You need to set the parameters in the +config file. This should work for most implementations especially if you +follow the connections of the standard lubbock. Anyway just the block +marked memory configuration should be touched since the other parameters +are imposed by the PXA architecture. + +#define CONFIG_PXA_PCMCIA 1 +#define CONFIG_PXA_IDE 1 + +#define CONFIG_PCMCIA_SLOT_A 1 +/* just to keep build system happy */ + +#define CFG_PCMCIA_MEM_ADDR 0x28000000 +#define CFG_PCMCIA_MEM_SIZE 0x10000000 + +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00000000 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00000000 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x00000000 +/* memory configuration */ + +#define CFG_IDE_MAXBUS 1 +/* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 +/* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR 0x20000000 + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 0x1f0 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET 0x1f0 + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x3f0 + + +Another important point is that maybe you have to power the pcmcia +subsystem. This is very board specific, for an example on how to +do it please search for CONFIG_EXADRON1 in cmd_pcmcia.c diff --git a/doc/README.PlanetCore b/doc/README.PlanetCore new file mode 100644 index 0000000..b73c5f5 --- /dev/null +++ b/doc/README.PlanetCore @@ -0,0 +1,163 @@ +After several heart-struck failure, I got one workable way to program +each other in FLASH between PlanetCore and U-Boot. + +Hardware Platform : RPXlite DW(EP 823 H1 DW) + +1. From U-Boot to PlanetCore + +Utilities : PlanetCore Boot Loader - PCL200.mot + +[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot +PCL200.mot pcl200.bin + +[Target Operation] +u-boot>t 100000 pcl200.bin +u-boot>go 0x100000 +## Starting application at 0x00100000 ... + +MPC8xx PlanetCore Flash Burner v2.00 +Copyright 2001 Embedded Planet. All rights reserved. + +Construct Flash Device.....done. + + +Program MPC8xx PlanetCore Boot Loader v2.00 +Built Sep 19, 2001 at 14:34:42 +Image located from FC000000 to FC01B5D1. +(Skipping an image, only loading low boot image) + +Low boot board detected, skipping high boot image. +Erasing, programming and verifying will start in 20 +seconds +Press P to start immediately or ESC to cancel +Press Space or Enter for more options. +.............. + +Erasing +Programming +FLASH programmed successfully! +Press R to induce a hard reset + +MPC8xx PlanetCore Boot Loader v2.00 +Copyright 2001 Embedded Planet. All rights reserved. +DRAM available size = 64 MB +wvCV +DRAM OK +> + +2. From PlanetCore to U-Boot + +Utilities : PlanetCore FLASH Burner - PCB200.mot + +Use Flash Burner to finish the work: + +First, TFTP the U-Boot image file to RAM; For example, +RPXlite_DW.bin to 0x400000 +Second, TFTP FLASH Burner to RAM; For example, +0x100000 +Third, run the FLASH Burner and Program the U-Boot +image into the correct location in FLASH. + +[Target Operation] +MPC8xx PlanetCore Boot Loader v2.00 +Copyright 2001 Embedded Planet. All rights reserved. +DRAM available size = 64 MB +wvCV +DRAM OK +>t +Load using tftp via Ethernet +Enter server IP address <172.16.115.6> : +Enter server filename : RPXlite_DW.bin +Enter (B)inary or (S)record input mode : B +Enter address offset : <00400000 hex> : + +Total bytes = 120096 in 232184 uSecs +Loaded addresses 00400000 through 0041D51F. +Start address = 00400000 +>t +Load using tftp via Ethernet +Enter server IP address <172.16.115.6> : +Enter server filename : PCB200.mot +Enter (B)inary or (S)record input mode : S +Enter address offset : <00000000 hex> : +.512.1024..2048....4096..... +Total bytes = 326280 in 2570249 uSecs +Loaded addresses 00100000 through 0011BB51. +Start address = 00100000 +>go +[Go 00100000] + +MPC8xx PlanetCore Flash Burner v2.00 +Copyright 2001 Embedded Planet. All rights reserved. + +Construct Flash Device.....done. + +Bad start address +Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length = +0xFFFFFFFF +Forcing Menu Interface + +h[elp] Show commands. +c[ode] Show information on code to be loaded. +di[splay] Display all flash sections. +du[mp] Dump memory. d ? for more info. +e[rase] Erase flash sections. +f[ill] Fill flash sections. +im[age] Toggle load high, low, or both flash +images. +in[fo] Show flash information. +ma[p] Show memory map. +mo[dify] Modify memory. m ? for more info. +p[rogram] Erase, program, and verify now. +reset Restart the loader. +s[how] Show flash sections to erase and program. +t[est] Test flash sections. +q[uit] Quit without programming. +#program 400000 ff000000 1D51F +doProgram( 400000 ff000000 1D51F ) + +Start = 0x00400000, target = 0xFF000000, length = +0x0001D51F +Erasing sector 0xFF000000, length 0x008000. +Erasing sector 0xFF008000, length 0x008000. +Erasing sector 0xFF010000, length 0x008000. +Erasing sector 0xFF018000, length 0x008000. +Programming FF000000 through FF01D51E +FLASH programmed successfully! +Press R to induce a hard reset + +Forcing Hard Reset by MachineCheck and +ResetOnCheckstop... + +U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) + +CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB +D-Cache +Board: RPXlite_DW +DRAM: 64 MB +FLASH: 16 MB +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET +u-boot> + +------------------------------------------------- + +Well, sometimes network function of PlanetCore couldn't work when +switching from U-Boot to PlanetCore. For example, you couldn't +download a file from HOST PC via TFTP. Don't worry, just restart your +HOST PC and everything would work as smooth as clockwork. I don't +know the reason WHY:-) + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Merry Christmas and Happy New Year! + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +===== +Best regards, + +Sam diff --git a/doc/README.Purple b/doc/README.Purple new file mode 100644 index 0000000..0098e26 --- /dev/null +++ b/doc/README.Purple @@ -0,0 +1,84 @@ +Installation Instructions: +-------------------------- + +1. Put the s2 switch into the following position: + + Off On + ------ + |x | + | x| + |x | + | X| + ------ + + Put the s3 switch into the following position: + + Off On + ------ + | x | + | x | + | x| + | x| + ------ + + Put the s4 switch into the following position: + + Off On + ------ + |x | + |x | + |x | + |x | + |x | + | x| + | x| + |x | + ------ + +2. Connect to the serial console and to the BDI. Power on. On the + serial line, you should see: + + PURPLE@1.2> + +3. Type '8'. No echo will be displayed. In response, you should get: + + 7A(pass) + +4. From BDI, enter command: + + mmw 0xb800d860 0x0042c7ff + +5. Then, from BDI: + + erase 0xB0000000 + erase 0xB0008000 + erase 0xB000C000 + erase 0xB0010000 + erase 0xB0020000 + + prog 0xB0000000 bin + +6. Power off. Restore the original S2 switch position: + + Off On + ------ + | x| + | x| + |x | + | X| + ------ + + Power on. U-Boot should come up. + + +Implementation Notes: +--------------------- + +Due to the RAM/flash bus arbitration problem the suggested workaround +had to be implemented. It works okay. On the downside is that you +can't really check whether 'erase' is complete by polling flash as it +is usually done. Instead, the flash driver simply waits for a given +time and assumes that erase then has passed. This behaviour is +identical to what the VxWorks driver does; also, the same timeout (6 +seconds) was chosen. Note that this timeout applies for each erase +operation, i. e. per erased sector. diff --git a/doc/README.RPXClassic b/doc/README.RPXClassic new file mode 100644 index 0000000..5344cc6 --- /dev/null +++ b/doc/README.RPXClassic @@ -0,0 +1,19 @@ +# Porting U-Boot onto RPXClassic LF_BW31 board +# Written by Pierre AUBERT +# E-Mail p.aubert@staubli.com +# Stäubli Faverges - +# +# Sept. 20 2001 +# +# Cross compile: Montavista Hardhat ported on HP-UX 10.20 +# + +Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000 +DRAM : 16 Mb from 0 +NVRAM : 512 kb from 0xfa000000 + + +- environment is stored in NVRAM +- Mac address is read from EEPROM +- ethernet on SCC1 or fast ethernet on FEC are running (depending on the + configuration flag CONFIG_FEC_ENET) diff --git a/doc/README.RPXlite b/doc/README.RPXlite new file mode 100644 index 0000000..c8ccc41 --- /dev/null +++ b/doc/README.RPXlite @@ -0,0 +1,877 @@ +# Porting U-Boot onto RPXlite board +# Written by Yoo. Jonghoon +# E-Mail : yooth@ipone.co.kr +# IP ONE Inc. + +# Since 2001. 1. 29 + +# Shell : bash +# Cross-compile tools : Montavista Hardhat +# Debugging tools : Windriver VisionProbe (PowerPC BDM) +# ppcboot ver. : ppcboot-0.8.1 + +############################################################### +# 1. Hardware setting +############################################################### + +1.1. Board, BDM settings + Install board, BDM, connect each other + +1.2. Save Register value + Boot with board-on monitor program and save the + register values with BDM. + +1.3. Configure flash programmer + Check flash memory area in the memory map. + 0xFFC00000 - 0xFFFFFFFF + + Boot monitor program is at + 0xFFF00000 + + You can program on-board flash memory with VisionClick + flash programmer. Set the target flash device as: + + 29DL800B + + (?) The flash memory device in the board *is* 29LV800B, + but I cannot program it with '29LV800B' option. + (in VisionClick flash programming tools) + I don't know why... + +1.4. Save boot monitor program *IMPORTANT* + Upload boot monitor program from board to file. + boot monitor program starts at 0xFFF00000 + +1.5. Test flash memory programming + Try to erase boot program in the flash memory, + and re-write them. + *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE + BEFORE ERASING FLASH + +############################################################### +# 2. U-Boot setting +############################################################### + +2.1. Download U-Boot tarball at + ftp://ftp.denx.de + (The latest version is ppcboot-0.8.1.tar.bz2) + + To extract the archive use the following syntax : + > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - + +2.2. Add the following lines in '.profile' + export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin + +2.3. Make board specific config, for example: + > cd ppcboot-0.8.1 + > make TQM860L_config + + Now we can build ppcboot bin files. + After make all, you must see these files in your + ppcboot root directory. + + ppcboot + ppcboot.bin + ppcboot.srec + ppcboot.map + +2.4. Make your own board directory into the + ppcboot-0.8.1/board + and make your board-specific files here. + + For exmanple, tqm8xx files are composed of + .depend : Nothing + Makefile : To make config file + config.mk : Sets base address + flash.c : Flash memory control files + ppcboot.lds : linker(ld) script? (I don't know this yet) + tqm8xx.c : DRAM control and board check routines + + And, add your board config lines in the + ppcboot-0.8.1/Makefile + + Finally, add config_(your board).h file in the + ppcboot-0.8.1/include/ + + I've made board/rpxlite directory, and just copied + tqm8xx settings for now. + + Rebuild ppcboot for rpxlite board: + > make rpxlite_config + > make + +############################################################### +# 3. U-Boot porting +############################################################### + +3.1. My RPXlite files are based on tqm8xx board files. + > cd board + > cp -r tqm8xx RPXLITE + > cd RPXLITE + > mv tqm8xx.c RPXLITE.c + > cd ../../include + > cp config_tqm8xx.h config_RPXLITE.h + +3.2. Modified files are: + board/RPXLITE/RPXLITE.c /* DRAM-related routines */ + board/RPXLITE/flash.c /* flash-related routines */ + board/RPXLITE/config.mk /* set text base address */ + cpu/mpc8xx/serial.c /* board specific register setting */ + include/config_RPXLITE.h /* board specific registers */ + + See 'reg_config.txt' for register values in detail. + +############################################################### +# 4. Running Linux +############################################################### + + +############################################################### +# Misc Information +############################################################### + +mem_config.txt: +=============== + +Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device +manufacturer id : 01 (AMD) +device id : 5B (AM29LV800B) +size : 4Mbyte +sector # : 19 + +Sector information : + +number start addr. size +00 FFC0_0000 64 +01 FFC1_0000 32 +02 FFC1_8000 32 +03 FFC2_0000 128 +04 FFC4_0000 256 +05 FFC8_0000 256 +06 FFCC_0000 256 +07 FFD0_0000 256 +08 FFD4_0000 256 +09 FFD8_0000 256 +10 FFDC_0000 256 +11 FFE0_0000 256 +12 FFE4_0000 256 +13 FFE8_0000 256 +14 FFEC_0000 256 +15 FFF0_0000 256 +16 FFF4_0000 256 +17 FFF8_0000 256 +18 FFFC_0000 256 + + +reg_config.txt: +=============== + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* SIU (System Interface Unit) */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ + + +/*### IMMR */ +/*### Internal Memory Map Register */ +/*### Chap. 11.4.1 */ + + ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ + PARTNUM = 0x21 + MASKNUM = 0x00 + + => 0xFA20 2100 + +--------------------------------------------------------------------- + +/*### SIUMCR */ +/*### SIU Module Configuration Register */ +/*### Chap. 11.4.2 */ +/*### Offset : 0x0000 0000 */ + + EARB = 0 + EARP = 0 + DSHW = 0 + DBGC = 0 + DBPC = 0 + FRC = 0 + DLK = 0 + OPAR = 0 + PNCS = 0 + DPC = 0 + MPRE = 0 + MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ + AEME = 0 + SEME = 0 + BSC = 0 + GB5E = 0 + B2DD = 0 + B3DD = 0 + + => 0x0000 0800 + +--------------------------------------------------------------------- + +/*### SYPCR */ +/*### System Protection Control Register */ +/*### Chap. 11.4.3 */ +/*### Offset : 0x0000 0004 */ + + SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ + BMT = 0x06 /* BUS monitoring timing */ + BME = 1 /* BUS monitor enable */ + SWF = 1 + SWE = 0 /* SW watchdog disable */ + SWRI = 0 + SWP = 1 + + => 0xFFFF 0689 + +--------------------------------------------------------------------- + +/*### TESR */ +/*### Transfer Error Status Register */ +/*### Chap. 11.4.4 */ +/*### Offset : 0x0000 0020 */ + + IEXT = 0 + ITMT = 0 + IPB = 0000 + DEXT = 0 + DTMT = 0 + DPB = 0000 + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIPEND */ +/*### SIU Interrupt Pending Register */ +/*### Chap. 11.5.4.1 */ +/*### Offset : 0x0000 0010 */ + + IRQ0~IRQ7 = 0 + LVL0~LVL7 = 0 + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIMASK */ +/*### SIU Interrupt Mask Register */ +/*### Chap. 11.5.4.2 */ +/*### Offset : 0x0000 0014 */ + + IRM0~IRM7 = 0 /* Mask all interrupts */ + LVL0~LVL7 = 0 + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIEL */ +/*### SIU Interrupt Edge/Level Register */ +/*### Chap. 11.5.4.3 */ +/*### Offset : 0x0000 0018 */ + + ED0~ED7 = 0 /* Low level triggered */ + WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIVEC */ +/*### SIU Interrupt Vector Register */ +/*### Chap. 11.5.4.4 */ +/*### Offset : 0x0000 001C */ + + INTC = 3C /* The lowest interrupt is pending..(?) */ + + => 0x3C00 0000 + +--------------------------------------------------------------------- + +/*### SWSR */ +/*### Software Service Register */ +/*### Chap. 11.7.1 */ +/*### Offset : 0x0000 001E */ + + SEQ = 0 + + => 0x0000 + +--------------------------------------------------------------------- + +/*### SDCR */ +/*### SDMA Configuration Register */ +/*### Chap. 20.2.1 */ +/*### Offset : 0x0000 0032 */ + + FRZ = 0 + RAID = 01 /* Priority level 5 (BR5) (normal operation) */ + + => 0x0000 0001 + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* UPMA (User Programmable Machine A) */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ + +/*### Chap. 16.6.4.1 */ +/*### Offset = 0x0000 017c */ + + T0 = CFFF CC24 /* Single Read */ + T1 = 0FFF CC04 + T2 = 0CAF CC04 + T3 = 03AF CC08 + T4 = 3FBF CC27 /* last */ + T5 = FFFF CC25 + T6 = FFFF CC25 + T7 = FFFF CC25 + T8 = CFFF CC24 /* Burst Read */ + T9 = 0FFF CC04 + T10 = 0CAF CC84 + T11 = 03AF CC88 + T12 = 3FBF CC27 /* last */ + T13 = FFFF CC25 + T14 = FFFF CC25 + T15 = FFFF CC25 + T16 = FFFF CC25 + T17 = FFFF CC25 + T18 = FFFF CC25 + T19 = FFFF CC25 + T20 = FFFF CC25 + T21 = FFFF CC25 + T22 = FFFF CC25 + T23 = FFFF CC25 + T24 = CFFF CC24 /* Single Write */ + T25 = 0FFF CC04 + T26 = 0CFF CC04 + T27 = 03FF CC00 + T28 = 3FFF CC27 /* last */ + T29 = FFFF CC25 + T30 = FFFF CC25 + T31 = FFFF CC25 + T32 = CFFF CC24 /* Burst Write */ + T33 = 0FFF CC04 + T34 = 0CFF CC80 + T35 = 03FF CC8C + T36 = 0CFF CC00 + T37 = 33FF CC27 /* last */ + T38 = FFFF CC25 + T39 = FFFF CC25 + T40 = FFFF CC25 + T41 = FFFF CC25 + T42 = FFFF CC25 + T43 = FFFF CC25 + T44 = FFFF CC25 + T45 = FFFF CC25 + T46 = FFFF CC25 + T47 = FFFF CC25 + T48 = C0FF CC24 /* Refresh */ + T49 = 03FF CC24 + T50 = 0FFF CC24 + T51 = 0FFF CC24 + T52 = 3FFF CC27 /* last */ + T53 = FFFF CC25 + T54 = FFFF CC25 + T55 = FFFF CC25 + T56 = FFFF CC25 + T57 = FFFF CC25 + T58 = FFFF CC25 + T59 = FFFF CC25 + T60 = FFFF CC25 /* Exception */ + T61 = FFFF CC25 + T62 = FFFF CC25 + T63 = FFFF CC25 + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* UPMB */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### Chap. 16.6.4.1 */ + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* MEMC */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### BR0 & OR0 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ +/*### Flash memory */ + + BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ + AT = 000 + PS = 00 + PARE = 0 + WP = 0 + MS = 0 /* GPCM */ + V = 1 /* Valid */ + + => 0xFE00 0001 + + AM = 1111 1110 0000 0000 0 /* 32MBytes */ + ATM = 000 + CSNT/SAM = 0 + ACS/G5LA,G5LS = 00 + BIH = 1 /* Burst inhibited */ + SCY = 0100 /* cycle length = 4 */ + SETA = 0 + TRLX = 0 + EHTR = 0 + + => 0xFE00 0140 + +/*### BR1 & OR1 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ +/*### SDRAM */ + + BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ + AT = 000 + PS = 00 + PARE = 0 + WP = 0 + MS = 1 /* UPMA */ + V = 1 /* Valid */ + + => 0x0000 0081 + + AM = 1111 1110 0000 0000 /* 32MBytes */ + ATM = 000 + CSNT/SAM = 1 + ACS/G5LA,G5LS = 11 + BIH = 0 + SCY = 0000 /* cycle length = 0 */ + SETA = 0 + TRLX = 0 + EHTR = 0 + + => 0xFE00 0E00 + +/*### BR2 & OR2 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ + + BR2 & OR2 = 0x0000 0000 /* Not used */ + +/*### BR3 & OR3 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ +/*### BCSR */ + + BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ + AT = 000 + PS = 00 + PARE = 0 + WP = 0 + MS = 0 /* GPCM */ + V = 1 /* Valid */ + + => 0xFA40 0001 + + AM = 1111 1111 0111 1111 1 /* (?) */ + ATM = 000 + CSNT/SAM = 1 + ACS/G5LA,G5LS = 00 + BIH = 1 /* Burst inhibited */ + SCY = 0001 /* cycle length = 1 */ + SETA = 0 + TRLX = 0 + + => 0xFF7F 8910 + +/*### BR4 & OR4 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ +/*### NVRAM & SRAM */ + + BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ + AT = 000 + PS = 01 + PARE = 0 + WP = 0 + MS = 0 /* GPCM */ + V = 1 /* Valid */ + + => 0xFA00 0401 + + AM = 1111 1111 1111 1000 0 /* 8MByte */ + ATM = 000 + CSNT/SAM = 1 + ACS/G5LA,G5LS = 00 + BIH = 1 /* Burst inhibited */ + SCY = 0111 /* cycle length = 7 */ + SETA = 0 + TRLX = 0 + + => 0xFFF8 0970 + +/*### BR5 & OR5 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ + + BR5 & OR5 = 0x0000 0000 /* Not used */ + +/*### BR6 & OR6 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ + + BR6 & OR6 = 0x0000 0000 /* Not used */ + +/*### BR7 & OR7 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ + + BR7 & OR7 = 0x0000 0000 /* Not used */ + +/*### MAR */ +/*### Memory Address Register */ +/*### Chap. 16.4.7 */ +/*### Offset : 0x0000 0164 */ + + MA = External memory address + +/*### MCR */ +/*### Memory Command Register */ +/*### Chap. 16.4.5 */ +/*### Offset : 0x0000 0168 */ + + OP = xx /* Command op code */ + UM = 1 /* Select UPMA */ + MB = 001 /* Select CS1 */ + MCLF = xxxx /* Loop times */ + MAD = xx xxxx /* Memory array index */ + +/*### MAMR */ +/*### Machine A Mode Register */ +/*### Chap. 16.4.4 */ +/*### Offset : 0x0000 0170 */ + + PTA = 0101 1000 + PTAE = 1 /* Periodic timer A enabled */ + AMA = 010 + DSA = 00 + G0CLA = 000 + GPLA4DIS = 1 + RLFA = 0100 + WLFA = 0011 + TLFA = 0000 + + => 0x58A0 1430 + +/*### MBMR */ +/*### Machine B Mode Register */ +/*### Chap. 16.4.4 */ +/*### Offset : 0x0000 0174 */ + + PTA = 0100 1110 + PTAE = 0 /* Periodic timer B disabled */ + AMA = 000 + DSA = 00 + G0CLA = 000 + GPLA4DIS = 1 + RLFA = 0000 + WLFA = 0000 + TLFA = 0000 + + => 0x4E00 1000 + +/*### MSTAT */ +/*### Memory Status Register */ +/*### Chap. 16.4.3 */ +/*### Offset : 0x0000 0178 */ + + PER0~PER7 = Parity error + WPER = Write protection error + + => 0x0000 + +/*### MPTPR */ +/*### Memory Periodic Timer Prescaler Register */ +/*### Chap. 16.4.8 */ +/*### Offset : 0x0000 017A */ + + PTP = 0000 1000 /* Divide by 8 */ + + => 0x0800 + +/*### MDR */ +/*### Memory Data Register */ +/*### Chap. 16.4.6 */ +/*### Offset : 0x0000 017C */ + + MD = Memory data contains the RAM array word + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* TIMERS */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### TBREFx */ +/*### Timebase Reference Registers */ +/*### Chap. 11.9.2 */ +/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ +/*### (Locked) */ + + TBREFF0 = 0xFFFF FFFF + TBREFF1 = 0xFFFF FFFF + +--------------------------------------------------------------------- + +/*### TBSCR */ +/*### Timebase Status and Control Registers */ +/*### Chap. 11.9.3 */ +/*### Offset : 0x0000 0200 */ +/*### (Locked) */ + + TBIRQ = 00000000 + REF0 = 0 + REF1 = 0 + REFE0 = 0 /* Reference interrupt disable */ + REFE1 = 0 + TBF = 1 + TBE = 1 /* Timebase enable */ + + => 0x0003 + +--------------------------------------------------------------------- + +/*### RTCSC */ +/*### Real-Time Clock Status and Control Registers */ +/*### Chap. 11.10.1 */ +/*### Offset : 0x0000 0220 */ +/*### (Locked) */ + + RTCIRQ = 00000000 + SEC = 1 + ALR = 0 + 38K = 0 /* PITRTCLK is driven by 32.768KHz */ + SIE = 0 + ALE = 0 + RTF = 0 + RTE = 1 /* Real-Time clock enabled */ + + => 0x0081 + +--------------------------------------------------------------------- + +/*### RTC */ +/*### Real-Time Clock Registers */ +/*### Chap. 11.10.2 */ +/*### Offset : 0x0000 0224 */ +/*### (Locked) */ + + RTC = Real time clock measured in second + +--------------------------------------------------------------------- + +/*### RTCAL */ +/*### Real-Time Clock Alarm Registers */ +/*### Chap. 11.10.3 */ +/*### Offset : 0x0000 022C */ +/*### (Locked) */ + + ALARM = 0xFFFF FFFF + +--------------------------------------------------------------------- + +/*### RTSEC */ +/*### Real-Time Clock Alarm Second Registers */ +/*### Chap. 11.10.4 */ +/*### Offset : 0x0000 0228 */ +/*### (Locked) */ + + COUNTER = Counter bits(fraction of a second) + +--------------------------------------------------------------------- + +/*### PISCR */ +/*### Periodic Interrupt Status and Control Register */ +/*### Chap. 11.11.1 */ +/*### Offset : 0x0000 0240 */ +/*### (Locked) */ + + PIRQ = 0 + PS = 0 /* Write 1 to clear */ + PIE = 0 + PITF = 1 + PTE = 0 /* PIT disabled */ + +--------------------------------------------------------------------- + +/*### PITC */ +/*### PIT Count Register */ +/*### Chap. 11.11.2 */ +/*### Offset : 0x0000 0244 */ +/*### (Locked) */ + + PITC = PIT count + +--------------------------------------------------------------------- + +/*### PITR */ +/*### PIT Register */ +/*### Chap. 11.11.3 */ +/*### Offset : 0x0000 0248 */ +/*### (Locked) */ + + PIT = PIT count /* Read only */ + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* CLOCKS */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + + +--------------------------------------------------------------------- + +/*### SCCR */ +/*### System Clock and Reset Control Register */ +/*### Chap. 15.6.1 */ +/*### Offset : 0x0000 0280 */ +/*### (Locked) */ + + COM = 11 /* Clock output disabled */ + TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ + RTDIV = 0 /* The clock is divided by 4 */ + RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ + CRQEN = 0 + PRQEN = 0 + EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ + DFSYNC = 00 /* Divided by 1 (normal operation) */ + DFBRG = 00 /* Divided by 1 (normal operation) */ + DFNL = 000 + DFNH = 000 + + => 0x6200 0000 + +--------------------------------------------------------------------- + +/*### PLPRCR */ +/*### PLL, Low-Power, and Reset Control Register */ +/*### Chap. 15.6.2 */ +/*### Offset : 0x0000 0284 */ +/*### (Locked) */ + + MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ + SPLSS = 0 + TEXPS = 0 + TMIST = 0 + CSRC = 0 /* The general system clock is generated by the DFNH field */ + LPM = 00 /* Normal high/normal low mode */ + CSR = 0 + LOLRE = 0 + FIOPD = 0 + + => 0x0050 0000 + +--------------------------------------------------------------------- + +/*### RSR */ +/*### Reset Status Register */ +/*### Chap. 12.2 */ +/*### Offset : 0x0000 0288 */ +/*### (Locked) */ + + EHRS = External hard reset + ESRS = External soft reset + LLRS = Loss-of-lock reset + SWRS = Software watchdog reset + CSRS = Check stop reset + DBHRS = Debug port hard reset + DBSRS = Debug port soft reset + JTRS = JTAG reset + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* DMA */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### SDSR */ +/*### SDMA Status Register */ +/*### Chap. 20.2.2 */ +/*### Offset : 0x0000 0908 */ + + SBER = 0 /* SDMA channel bus error */ + DSP2 = 0 /* DSP chain2 (Tx) interrupt */ + DSP1 = 0 /* DSP chain1 (Rx) interrupt */ + + => 0x00 + +/*### SDMR */ +/*### SDMA Mask Register */ +/*### Chap. 20.2.3 */ +/*### Offset : 0x0000 090C */ + + SBER = 0 + DSP2 = 0 + DSP1 = 0 /* All interrupts are masked */ + + => 0x00 + +/*### SDAR */ +/*### SDMA Address Register */ +/*### Chap. 20.2.4 */ +/*### Offset : 0x0000 0904 */ + + AR = 0xxxxx xxxx /* current system address */ + + => 0xFA20 23AC + +/*### IDSRx */ +/*### IDMA Status Register */ +/*### Chap. 20.3.3.2 */ +/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ + + AD = 0 + DONE = 0 + OB = 0 + + => 0x00 + +/*### IDMRx */ +/*### IDMA Mask Register */ +/*### Chap. 20.3.3.3 */ +/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ + + AD = 0 + DONE = 0 + OB = 0 diff --git a/doc/README.SBC8560 b/doc/README.SBC8560 new file mode 100644 index 0000000..c4b6422 --- /dev/null +++ b/doc/README.SBC8560 @@ -0,0 +1,57 @@ +The port was tested on Wind River System Sbc8560 board +. U-Boot was installed on the flash memory of the +CPU card (no the SODIMM). + +NOTE: Please configure uboot compile to the proper PCI frequency and +setup the appropriate DIP switch settings. + +SBC8560 board: + +Make sure boards switches are set to their appropriate conditions. +Refer to the Engineering Reference Guide ERG-00300-002. Of particular +importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which +select the on-board FLASH device (Intel 28F128Jx); 2) The settings +for the Clock SW9 (33 MHz or 66 MHz). + + Note: SW9 Settings: 66 MHz + 4:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on + Note: SW9 Settings: 33 MHz + 8:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on + + +Flashing the FLASH device with the "Wind River ICE": + +1) Properly connect and configure the Wind River ICE to the target + JTAG port. This includes running the SBC8560 register script. Make + sure target memory can be read and written. + +2) Build the u-boot image: + make distclean + make SBC8560_66_config or SBC8560_33_config + make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all + + Note: reference is made to the ELDK3.0 compiler. Further, it seems + the ppc_8xx compiler is required for the 85xx (no 85xx + designated compiler in ELDK3.0) + +3) Convert the uboot (.elf) file to a uboot.bin file (using + visionClick converter). The bin file should be converted from + fffc0000 to ffffffff + +4) Setup the Flash Utility (tools menu) for: + + Do a "dc clr" [visionClick] to load the default register settings + Determine the clock speed of the PCI bus and set SW9 accordingly + Note: the speed of the PCI bus defaults to the slowest PCI card + PlayBack the "default" register file for the SBC8560 + Select the uboot.bin file with zero bias + Select the initialize Target prior to programming + Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm + Select the erase base address from FFFC0000 to FFFFFFFF + Select the start address from 0 with size of 4000 + +5) Erase and Program diff --git a/doc/README.SNTP b/doc/README.SNTP new file mode 100644 index 0000000..fd6f209 --- /dev/null +++ b/doc/README.SNTP @@ -0,0 +1,17 @@ +To use SNTP support, add a define CFG_CMD_SNTP to CONFIG_COMMANDS in +the configuration file of the board. + +The "sntp" command gets network time from NTP time server and +syncronize RTC of the board. This command needs the command line +parameter of server's IP address or environment variable +"ntpserverip". The network time is sent as UTC. So if you want to +set local time to RTC, set the offset in second from UTC to the +enviroment variable "time offset". + +If the DHCP server provides time server's IP or time offset, you +don't need to set the above environment variables yourself. + +Current limitations of SNTP support: +1. The roundtrip time is ignored. +2. Only the 1st NTP server IP, in the option ntp-servers of DHCP, will + be used. diff --git a/doc/README.Sandpoint8240 b/doc/README.Sandpoint8240 new file mode 100644 index 0000000..a41b69a --- /dev/null +++ b/doc/README.Sandpoint8240 @@ -0,0 +1,394 @@ +The port was tested on a Sandpoint 8240 X3 board, with U-Boot +installed in the flash memory of the CPU card. Please use the +following DIP switch settings: + +Motherboard: + +SW1.1: on SW1.2: on SW1.3: on SW1.4: on +SW1.5: on SW1.6: on SW1.7: on SW1.8: on + +SW2.1: on SW2.2: on SW2.3: on SW2.4: on +SW2.5: on SW2.6: on SW2.7: on SW2.8: on + + +CPU Card: + +SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on +SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF + +SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF +SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on + + +The followind detailed description of installation and initial steps +with U-Boot and QNX was provided by Jim Sandoz : + + +Directions for installing U-Boot on Sandpoint+Unity8240 +using the Abatron BDI2000 BDM/JTAG debugger ... + +Background and Reference info: +http://u-boot.sourceforge.net/ +http://www.abatron.ch/ +http://www.abatron.ch/BDI/bdihw.html +http://www.abatron.ch/DataSheets/BDI2000.pdf +http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf +http://e-www.motorola.com/collateral/SPX3UM.pdf +http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf + + +Connection Diagram: + =========== + === ===== |----- | +| | <---------------> | | | | | +|PC | rs232 | BDI |=============[] | | +| | |2000 | BDM probe | | | +| | <---------------> | | |----- | + === ethernet ===== | | + | | + =========== + Sandpoint X3 with + Unity 8240 proc + + +PART 1) + DIP Switch Settings: + +Sandpoint X3 8240 processor board DIP switch settings, with +U-Boot to be installed in the flash memory of the CPU card: + +Motorola Sandpoint X3 Motherboard: +SW1.1: on SW1.2: on SW1.3: on SW1.4: on +SW1.5: on SW1.6: on SW1.7: on SW1.8: on +SW2.1: on SW2.2: on SW2.3: on SW2.4: on +SW2.5: on SW2.6: on SW2.7: on SW2.8: on + +Motorola Unity 8240 CPU Card: +SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on +SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF +SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF +SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on + + +PART 2) + Connect the BDI2000 Cable to the Sandpoint/Unity 8240: + +BDM Pin 1 on the Unity 8240 processor board is towards the +PCI PMC connectors, or away from the socketed SDRAM, i.e.: + + ==================== + | ---------------- | + | | SDRAM | | + | | | | + | ---------------- | + | |~| | + | |B| ++++++ | + | |D| + uP + | + | |M| +8240+ | + | ~ 1 ++++++ | + | | + | | + | | + | PMC conn ====== | + | ===== ====== | + | | + ==================== + + +PART 3) + Setting up the BDI2000, and preparing for TCP/IP network comms: + +Connect the BDI2000 to the PC using the supplied serial cable. +Download the BDI2000 software and install it using setup.exe. + +[Note: of course you can also use the Linux command line tool +"bdisetup" to configure your BDI2000 - the sources are included on +the floppy disk that comes with your BDI2000. Just in case you don't +have any Windows PC's - like me :-) -- wd ] + +Power up the BDI2000; then follow directions to assign the IP +address and related network information. Note that U-Boot +will be loaded to the Sandpoint via tftp. You need to either +use the Abatron-provided tftp application or provide a tftp +server (e.g. Linux/Solaris/*BSD) somewhere on your network. +Once the IP address etc are assigned via the RS232 port, +further communication with the BDI2000 will happen via the +ethernet connection. + +PART 4) + Making a TCP/IP network connection to the Abatron BDI2000: + +Telnet to the Abatron BDI2000. Assuming that all of the +networking info was loaded via RS232 correctly, you will see +the following (scrolling): + +- TARGET: waiting for target Vcc +- TARGET: waiting for target Vcc + + +PART 5) + Power up the target Sandpoint: +If the BDM connections are correct, the following will now appear: + +- TARGET: waiting for target Vcc +- TARGET: waiting for target Vcc +- TARGET: processing power-up delay +- TARGET: processing user reset request +- BDI asserts HRESET +- Reset JTAG controller passed +- Bypass check: 0x55 => 0xAA +- Bypass check: 0x55 => 0xAA +- JTAG exists check passed +- Target PVR is 0x00810101 +- COP status is 0x01 +- Check running state passed +- BDI scans COP freeze command +- BDI removes HRESET +- COP status is 0x05 +- Check stopped state passed +- Check LSRL length passed +- BDI sets breakpoint at 0xFFF00100 +- BDI resumes program execution +- Waiting for target stop passed +- TARGET: Target PVR is 0x00810101 +- TARGET: reseting target passed +- TARGET: processing target startup .... +- TARGET: processing target startup passed +BDI> + + +PART 6) + Erase the current contents of the flash memory: + +BDI>era 0xFFF00000 + Erasing flash at 0xfff00000 + Erasing flash passed +BDI>era 0xFFF04000 + Erasing flash at 0xfff04000 + Erasing flash passed +BDI>era 0xFFF06000 + Erasing flash at 0xfff06000 + Erasing flash passed +BDI>era 0xFFF08000 + Erasing flash at 0xfff08000 + Erasing flash passed +BDI>era 0xFFF10000 + Erasing flash at 0xfff10000 + Erasing flash passed +BDI>era 0xFFF20000 + Erasing flash at 0xfff20000 + Erasing flash passed + + +PART 7) + Program the flash memory with the U-Boot image: + +BDI>prog 0xFFF00000 u-boot.bin bin + Programming u-boot.bin , please wait .... + Programming flash passed + + +PART 8) + Connect PC to Sandpoint: +Using a crossover serial cable, attach the PC serial port to the +Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud. + + +PART 9) + Reset the Unity and begin U-Boot execution: + +BDI>reset +- TARGET: processing user reset request +- TARGET: Target PVR is 0x00810101 +- TARGET: reseting target passed +- TARGET: processing target init list .... +- TARGET: processing target init list passed + +BDI>go + +Now see output from U-Boot running, sent via serial port: + +U-Boot 1.1.4 (Jan 23 2002 - 18:29:19) + +CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache +Board: Sandpoint 8240 Unity +DRAM: 64 MB +FLASH: 2 MB +PCI: scanning bus0 ... + bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE + 00 00 00 1057 0003 060000 13 00000008 00000000 01 00 + 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00 + 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00 +In: serial +Out: serial +Err: serial +=> + + +PART 10) + Set and save any required environmental variables, examples of some: + +=> setenv ethaddr 00:03:47:97:D0:79 +=> setenv bootfile your_qnx_image_here +=> setenv hostname sandpointX +=> setenv netmask 255.255.255.0 +=> setenv ipaddr 192.168.0.11 +=> setenv serverip 192.168.0.10 +=> setenv gatewayip=192.168.0.1 +=> saveenv +Saving Enviroment to Flash... +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + +**** Example environment: **** + +=> printenv +baudrate=9600 +bootfile=telemetry +hostname=sp1 +ethaddr=00:03:47:97:E4:6B +load=tftp 100000 u-boot.bin +update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv +filesize=1f304 +gatewayip=145.17.228.1 +netmask=255.255.255.0 +ipaddr=145.17.228.42 +serverip=145.17.242.46 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 332/8188 bytes +=> + +here's some text useful stuff for cut-n-paste: +setenv hostname sandpoint1 +setenv netmask 255.255.255.0 +setenv ipaddr 145.17.228.81 +setenv serverip 145.17.242.46 +setenv gatewayip 145.17.228.1 +saveenv + +PART 11) + Test U-Boot by tftp'ing new U-Boot, overwriting current: + +=> protect off all +Un-Protect Flash Bank # 1 +=> tftp 100000 u-boot.bin +eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) +ARP broadcast 1 +TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through + gateway 145.17.228.1 +Filename 'u-boot.bin'. +Load address: 0x100000 +Loading: ######################### +done +Bytes transferred = 127628 (1f28c hex) +=> era all +Erase Flash Bank # 1 + done +Erase Flash Bank # 2 - missing +=> cp.b 0x100000 FFF00000 1f28c +Copy to Flash... done +=> saveenv +Saving Enviroment to Flash... +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> reset + +You can put these commands into some environment variables; + +=> setenv load tftp 100000 u-boot.bin +=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv +=> saveenv + +Then you just have to type "run load" then "run update" + +=> run load +eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) +ARP broadcast 1 +TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through + gateway 145.17.228.1 +Filename 'u-boot.bin'. +Load address: 0x100000 +Loading: ######################### +done +Bytes transferred = 127748 (1f304 hex) +=> run update +Un-Protect Flash Bank # 1 +Un-Protect Flash Bank # 2 +Erase Flash from 0xfff00000 to 0xfff3ffff + done +Erased 7 sectors +Copy to Flash... done +Saving Enviroment to Flash... +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + + +PART 12) + Load OS image (ELF format) via U-Boot using tftp + + +=> tftp 800000 sandpoint-simple.elf +eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) +ARP broadcast 1 +TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through + gateway 145.17.228.1 +Filename 'sandpoint-simple.elf'. +Load address: 0x800000 +Loading: ################################################################# + ################################################################# + ################################################################# + ######################## +done +Bytes transferred = 1120284 (11181c hex) +==> + +PART 13) + Begin OS image execution: (note that unless you have the +serial parameters of your OS image set to 9600 (i.e. same as +the U-Boot binary) you will get garbage here until you change +the serial communications speed. + +=> bootelf 800000 +Loading @ 0x001f0100 (1120028 bytes) +## Starting application at 0x001f1d28 ... +Replace init_hwinfo() with a board specific version + +Loading QNX6.... + +Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1 +<...loader and kernel messages snipped...> + +Welcome to Neutrino on the Sandpoint +# + + +other information: + +CVS Retrieval Notes: + +U-Boot's SourceForge CVS repository can be checked out +through anonymous (pserver) CVS with the following +instruction set. The module you wish to check out must +be specified as the modulename. When prompted for a +password for anonymous, simply press the Enter key. + +cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login + +cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot diff --git a/doc/README.TQM8260 b/doc/README.TQM8260 new file mode 100644 index 0000000..0571095 --- /dev/null +++ b/doc/README.TQM8260 @@ -0,0 +1,415 @@ + +This file contains basic information on the port of U-Boot to TQM8260. +All the changes fit in the common U-Boot infrastructure, providing a +new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260, +type "make TQM8260_config", edit the "include/config_TQM8260.h" file +if necessary, then type "make". + + +Common file modifications: +-------------------------- + +The following common files have been modified by this project: +(starting from the ppcboot-0.9.3/ directory) + +MAKEALL - TQM8260 entry added +Makefile - TQM8260_config entry added +cpu/mpc8260/Makefile - soft_i2c.o module added +cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious + bug fixed (fcr -> scr) +cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added +include/flash.h - added definitions for the AM29LV640D Flash chip + + +New files: +---------- + +The following new files have been added by this project: +(starting from the ppcboot-0.9.3/ directory) + +board/tqm8260/ - board-specific directory +board/tqm8260/Makefile - board-specific makefile +board/tqm8260/config.mk - config file +board/tqm8260/flash.c - flash driver (for AM29LV640D) +board/tqm8260/ppcboot.lds - linker script +board/tqm8260/tqm8260.c - ioport and memory initialization +cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver +include/config_TQM8260.h - main configuration file + + +New configuration options: +-------------------------- + +CONFIG_TQM8260 + + Main board-specific option (should be defined for TQM8260). + +CONFIG_82xx_CONS_SMC1 + + If defined, SMC1 will be used as the console + +CONFIG_82xx_CONS_SMC2 + + If defined, SMC2 will be used as the console + +CFG_INIT_LOCAL_SDRAM + + If defined, the SDRAM on the local bus will be initialized and + mapped at BR2. + + +Acceptance criteria tests: +-------------------------- + +The following tests have been conducted to validate the port of U-Boot +to TQM8260: + +1. Operation on serial console: + +With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file, +the U-Boot output appeared on the serial terminal connected to COM1 as +follows: + +------------------------------------------------------------------------------ +=> help +go - start application at address 'addr' +run - run commands in an environment variable +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +tftpboot- boot image via network using TFTP protocol + and env variables ipaddr and serverip +rarpboot- boot image via network using RARP/TFTP protocol +bootd - boot default, i.e., run 'bootcmd' +loads - load S-Record file over serial line +loadb - load binary file over serial line (kermit mode) +md - memory display +mm - memory modify (auto-incrementing) +nm - memory modify (constant address) +mw - memory write (fill) +cp - memory copy +cmp - memory compare +crc32 - checksum calculation +base - print or set address offset +printenv- print environment variables +setenv - set environment variables +saveenv - save environment variables to persistent storage +protect - enable or disable FLASH write protection +erase - erase FLASH memory +flinfo - print FLASH memory information +bdinfo - print Board Info structure +iminfo - print header information for application image +coninfo - print console devices and informations +eeprom - EEPROM sub-system +loop - infinite loop on address range +mtest - simple RAM test +icache - enable or disable instruction cache +dcache - enable or disable data cache +reset - Perform RESET of the CPU +echo - echo args to console +version - print monitor version +help - print online help +? - alias for 'help' +=> +------------------------------------------------------------------------------ + + +2. Flash driver operation + +The following sequence was performed to test the "flinfo" command: + +------------------------------------------------------------------------------ +=> flinfo + +Bank # 1: AMD 29LV640D (64 M, uniform sector) + Size: 32 MB in 128 Sectors + Sector Start Addresses: + 40000000 40040000 (RO) 40080000 400C0000 40100000 + 40140000 40180000 401C0000 40200000 40240000 + 40280000 402C0000 40300000 40340000 40380000 + 403C0000 40400000 40440000 40480000 404C0000 + 40500000 40540000 40580000 405C0000 40600000 + 40640000 40680000 406C0000 40700000 40740000 + 40780000 407C0000 40800000 40840000 40880000 + 408C0000 40900000 40940000 40980000 409C0000 + 40A00000 40A40000 40A80000 40AC0000 40B00000 + 40B40000 40B80000 40BC0000 40C00000 40C40000 + 40C80000 40CC0000 40D00000 40D40000 40D80000 + 40DC0000 40E00000 40E40000 40E80000 40EC0000 + 40F00000 40F40000 40F80000 40FC0000 41000000 + 41040000 41080000 410C0000 41100000 41140000 + 41180000 411C0000 41200000 41240000 41280000 + 412C0000 41300000 41340000 41380000 413C0000 + 41400000 41440000 41480000 414C0000 41500000 + 41540000 41580000 415C0000 41600000 41640000 + 41680000 416C0000 41700000 41740000 41780000 + 417C0000 41800000 41840000 41880000 418C0000 + 41900000 41940000 41980000 419C0000 41A00000 + 41A40000 41A80000 41AC0000 41B00000 41B40000 + 41B80000 41BC0000 41C00000 41C40000 41C80000 + 41CC0000 41D00000 41D40000 41D80000 41DC0000 + 41E00000 41E40000 41E80000 41EC0000 41F00000 + 41F40000 41F80000 41FC0000 +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test the erase command: + +------------------------------------------------------------------------------ +=> cp 0 40080000 10 +Copy to Flash... done +=> erase 40080000 400bffff +Erase Flash from 0x40080000 to 0x400bffff +.. done +Erased 1 sectors +=> md 40080000 +40080000: ffffffff ffffffff ffffffff ffffffff ................ +40080010: ffffffff ffffffff ffffffff ffffffff ................ +40080020: ffffffff ffffffff ffffffff ffffffff ................ +40080030: ffffffff ffffffff ffffffff ffffffff ................ +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 40080000 10 +Copy to Flash... done +=> erase 1:2 +Erase Flash Sectors 2-2 in Bank # 1 +.. done +=> md 40080000 +40080000: ffffffff ffffffff ffffffff ffffffff ................ +40080010: ffffffff ffffffff ffffffff ffffffff ................ +40080020: ffffffff ffffffff ffffffff ffffffff ................ +40080030: ffffffff ffffffff ffffffff ffffffff ................ +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 40080000 10 +Copy to Flash... done +=> cp 0 400c0000 10 +Copy to Flash... done +=> erase 1:2-3 +Erase Flash Sectors 2-3 in Bank # 1 +... done +=> md 40080000 +40080000: ffffffff ffffffff ffffffff ffffffff ................ +40080010: ffffffff ffffffff ffffffff ffffffff ................ +40080020: ffffffff ffffffff ffffffff ffffffff ................ +40080030: ffffffff ffffffff ffffffff ffffffff ................ +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> md 400c0000 +400c0000: ffffffff ffffffff ffffffff ffffffff ................ +400c0010: ffffffff ffffffff ffffffff ffffffff ................ +400c0020: ffffffff ffffffff ffffffff ffffffff ................ +400c0030: ffffffff ffffffff ffffffff ffffffff ................ +400c0040: ffffffff ffffffff ffffffff ffffffff ................ +400c0050: ffffffff ffffffff ffffffff ffffffff ................ +400c0060: ffffffff ffffffff ffffffff ffffffff ................ +400c0070: ffffffff ffffffff ffffffff ffffffff ................ +400c0080: ffffffff ffffffff ffffffff ffffffff ................ +400c0090: ffffffff ffffffff ffffffff ffffffff ................ +400c00a0: ffffffff ffffffff ffffffff ffffffff ................ +400c00b0: ffffffff ffffffff ffffffff ffffffff ................ +400c00c0: ffffffff ffffffff ffffffff ffffffff ................ +400c00d0: ffffffff ffffffff ffffffff ffffffff ................ +400c00e0: ffffffff ffffffff ffffffff ffffffff ................ +400c00f0: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test the Flash programming commands: + +------------------------------------------------------------------------------ +=> erase 40080000 400bffff +Erase Flash from 0x40080000 to 0x400bffff +.. done +Erased 1 sectors +=> cp 0 40080000 10 +Copy to Flash... done +=> md 0 +00000000: 00000000 00000104 61100200 01000000 ........a....... +00000010: 00000000 00000000 81140000 82000100 ................ +00000020: 01080000 00004000 22800000 00000600 ......@."....... +00000030: 00200800 00000000 10000100 00008000 . .............. +00000040: 00812000 00000200 00020000 80000000 .. ............. +00000050: 00028001 00001000 00040400 00000200 ................ +00000060: 20480000 00000000 20090000 00142000 H...... ..... . +00000070: 00000000 00004000 24210000 10000000 ......@.$!...... +00000080: 02440002 10000000 00200008 00000000 .D....... ...... +00000090: 02440900 00000000 30a40000 00004400 .D......0.....D. +000000a0: 04420800 00000000 00000040 00020000 .B.........@.... +000000b0: 05020000 00100000 00060000 00000000 ................ +000000c0: 00400000 00000000 00080000 00040000 .@.............. +000000d0: 10400000 00800004 00000000 00000200 .@.............. +000000e0: 80890000 00010004 00080000 00000020 ............... +000000f0: 08000000 10000000 00010000 00000000 ................ +=> md 40080000 +40080000: 00000000 00000104 61100200 01000000 ........a....... +40080010: 00000000 00000000 81140000 82000100 ................ +40080020: 01080000 00004000 22800000 00000600 ......@."....... +40080030: 00200800 00000000 10000100 00008000 . .............. +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test storage of the environment +variables in Flash: + +------------------------------------------------------------------------------ +=> setenv foo bar +=> saveenv +Un-Protected 1 sectors +Erasing Flash... +.. done +Erased 1 sectors +Saving Environment to Flash... +Protected 1 sectors +=> reset +... +=> printenv +bootdelay=CONFIG_BOOTDELAY +baudrate=9600 +ipaddr=192.168.4.7 +serverip=192.168.4.1 +ethaddr=66:55:44:33:22:11 +foo=bar +stdin=serial +stdout=serial +stderr=serial + +Environment size: 170/262140 bytes +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test image download and run over +Ethernet interface (both interfaces were tested): + +------------------------------------------------------------------------------ +=> tftpboot 40000 hello_world.bin +ARP broadcast 1 +TFTP from server 192.168.2.2; our IP address is 192.168.2.7 +Filename 'hello_world.bin'. +Load address: 0x40000 +Loading: ############# +done +Bytes transferred = 65912 (10178 hex) +=> go 40004 +## Starting application at 0x00040004 ... +Hello World +argc = 1 +argv[0] = "40004" +argv[1] = "" +Hit any key to exit ... + +## Application terminated, rc = 0x0 +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test eeprom read/write commands: + +------------------------------------------------------------------------------ +=> md 40000 +00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. +00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... +00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x +00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. +00040040: 7c0803a6 4e800021 813f004c 7f84e378 |...N..!.?.L...x +00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! +00040060: 7c1be000 4181003c 80bd0000 813f004c |...A..<.....?.L +00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... +00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. +00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... +000400a0: 813f004c 807e8010 80090010 7c0803a6 .?.L.~......|... +000400b0: 4e800021 813f004c 80090004 7c0803a6 N..!.?.L....|... +000400c0: 4e800021 2c030000 4182ffec 813f004c N..!,...A....?.L +000400d0: 80090000 7c0803a6 4e800021 813f004c ....|...N..!.?.L +000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! +000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. +=> eeprom write 40000 0 40 + +EEPROM write: addr 00040000 off 0000 count 64 ... done +=> mw 50000 0 1000 +=> eeprom read 50000 0 40 + +EEPROM read: addr 00050000 off 0000 count 64 ... done +=> md 50000 +00050000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. +00050010: 90010024 48000005 7fc802a6 801effe8 ...$H........... +00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x +00050030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. +00050040: 00000000 00000000 00000000 00000000 ................ +00050050: 00000000 00000000 00000000 00000000 ................ +00050060: 00000000 00000000 00000000 00000000 ................ +00050070: 00000000 00000000 00000000 00000000 ................ +00050080: 00000000 00000000 00000000 00000000 ................ +00050090: 00000000 00000000 00000000 00000000 ................ +000500a0: 00000000 00000000 00000000 00000000 ................ +000500b0: 00000000 00000000 00000000 00000000 ................ +000500c0: 00000000 00000000 00000000 00000000 ................ +000500d0: 00000000 00000000 00000000 00000000 ................ +000500e0: 00000000 00000000 00000000 00000000 ................ +000500f0: 00000000 00000000 00000000 00000000 ................ +=> +------------------------------------------------------------------------------ + + +Patch per Mon, 06 Aug 2001 17:57:27: + +- upgraded Flash support (added support for the following chips: + AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B) +- BCR tweakage for the 8260 bus mode +- SIUMCR tweakage enabling the MI interrupt (IRQ7) + +To simplify switching between the bus modes, a new configuration +option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h" +file. If it is defined, BCR will be configured for the 60x mode, +otherwise - for the 8260 mode. + +Concerning the SIUMCR modification: it's hard to predict whether it +will induce any problems on the other (60x mode) board. However, the +problems (if they appear) should be easy to notice - if the board +does not boot, it's most likely caused by the DPPC configuration in +SIUMCR. diff --git a/doc/README.VLAN b/doc/README.VLAN new file mode 100644 index 0000000..4f86d55 --- /dev/null +++ b/doc/README.VLAN @@ -0,0 +1,15 @@ +U-Boot has networking support for VLANs (802.1q), and CDP (Cisco +Discovery Protocol). + +You control the sending/receiving of VLAN tagged packets with the +"vlan" environmental variable. When not present no tagging is +performed. + +CDP is used mainly to discover your device VLAN(s) when connected to +a Cisco switch. + +Note: In order to enable CDP support a small change is needed in the +networking driver. You have to enable reception of the +01:00:0c:cc:cc:cc MAC address which is a multicast address. + +Various defines control CDP; see the README section. diff --git a/doc/README.adnpesc1 b/doc/README.adnpesc1 new file mode 100644 index 0000000..ded5321 --- /dev/null +++ b/doc/README.adnpesc1 @@ -0,0 +1,235 @@ + + SSV ADNP/ESC1 Embedded Softcore Computing + Nios Softcore, Altera Cyclone FPGA + + Last Update: February 27, 2004 +==================================================================== + +This file contains information regarding U-Boot and the SSV Embedded +Nios Softcore Computing platform ADNP/ESC1. For general Nios +information see doc/README.nios. + +Most stuff of this file was borrowed and based on README.dk1s10, +the Altera DK-1S10 related information file. + +For those interested in contributing ... see HELP WANTED section +in doc/README.nios. + +Contents: + + 1. Files + 2. Memory Organization + 3. CPU Variations + 4. Examples + 5. Programming U-Boot into FLASH with GERMS + 6. Autoboot + 7. U-Boot environment convention and update philosophy + +==================================================================== + +1. Files +========= + board/ssv/adnpesc1/* + include/configs/ADNPESC1.h + include/configs/ADNPESC1_base_32.h + + +2. Memory Organization +======================= + +For the most part, you can put things pretty much anywhere. +This is pretty flexible for Nios. So here we make some arbitrary +choices & assume that the monitor is placed at the end of a memory +resource. So you must make sure TEXT_BASE is chosen appropriately. +This is very important if you plan to move your memory to another +place as configured at this time! + + -The heap is placed below the monitor (U-Boot code). + -Global data is placed below the heap. + -The stack is placed below global data (&grows down). + +(see doc/README.adnpesc1_base32 too) + + +3. CPU Variations +================= + +There are more than one NIOS CPU variation for the ADNP/ESC1 possible. +U-Boot supports the following CPU configurations: + + - SSV Basis 32 (make ADNPESC1_base_32_config) + - SSV Basis 32 at DNP evaluation base board 2 + (make ADNPESC1_DNPEVA2_base_32_config) + + +4. Examples +============ + +The hello_world example works fine. To try out you have to change +the default load address from 0x0100_0000 to 0x0204_0000 in +examples/Makefile (the real SDRAM for default board configuration). + + +5. Programming U-Boot into FLASH with GERMS +============================================ + +The current version of the ADNP/ESC1 port with the default +configuration settings occupies about 97 KBytes of flash. +A minimal configuration occupies less than 70 KByte +(network, SPI, POST and board command support disabled). You +can save more memory by deactivating the Hu-Shell support and +long command help (CFG_HUSH_PARSER, CFG_LONGHELP). + +To program U-Boot into the ADNP/ESC1 flash using GERMS do the +following: + +1. Download U-Boot to its target run space in SDRAM: + + a. Close jumper RCM_EN# and push the reset button. + + b. From the command line, download U-Boot using the + nios-run: + + $ nios-run -r u-boot.srec + + NOTE: In some cases this want fail. I don't know why, + but try again. + +This takes about 1 minute (GERMS is not very speedy here). +After u-boot is downloaded it will be executed. You should +see the following: + + U-Boot 1.0.2 (Jan 30 2004 - 12:59:15) + + CPU: Nios-32 Rev. 3.3 (0x3038) + Reg file size: 512 LO_LIMIT/HI_LIMIT: 1/30 + Board: SSV DilNetPC ADNP/ESC1 + Conf.: SSV Base 32 (nios_32) + In: serial + Out: serial + Err: serial + ADNPESC1 > + + +2. Quit nios-run and start your terminal application (e.g. start + Hyperterminal or minicom). + +3. Download the u-boot code to RAM. When using Hyperterminal, do the + following: + + a. From the u-boot command prompt start a binary download to SDRAM: + + at the SSV Basis 32 to SDRAM: + + ==> loadb 2000100 + + b. Download u-boot.bin using kermit. + +4. From the U-Boot command prompt, erase flash: + + at the SSV Basis 32 from 0x1000000 to 0x103ffff: + + ==> protect off 1:0-3 + ==> erase 1:0-3 + +5. Copy the binary image from SDRAM to flash: + + at the SSV Basis 32 from SDRAM: + + ==> cp.b 2000100 1000000 $filesize + +U-Boot will now automatically start when the board is powered on or +reset using the SSV Basis 32 configuration without closed RCM jumper. +To start U-Boot with closed RCM Jumper, enter the following GERMS +command: + + + g 1000000 + + +6. Autoboot +=========== + +U-Boot will try to boot a valid Nios application from Flash. For this +it will use the deposited Hu-Shell script in environment variable +'bootcmd' which is looking for a valid Nios application identifier +string in Flash and go on at even its entry address. For more +information see the next chapter. + + +7. U-Boot environment convention and update philosophy +====================================================== + +U-Boot for the SSV ADNP/ESC1 target knows about many environment +variables used to control the startup process, update process for +raw Nios applications, and optionally file system image updates. +In default configuration there are two Hu-Shell scripts to update +the Nios application and/or the file system image: + +1. Update Nios application (ex. the uCLinux kernel): + + run 'appl_update' + +2. Update optional file system image (ex. RomFS image used by uCLinux): + + run 'fs_update' + +The Nios application can be any programm code generated in relation +to the Nios application identifier -- the string "Nios" at offset +address 0x0c. To use the scripts like described above in a secure way +you have to check-up the next environment variables: + +1. update_allowed + + - Update switch -- must be set to '1' (one) to allow any update + - default is '0' (zero) + + NOTE: You should avoid to save this variable with non zero + value to Flash. Otherwise it would be allow any + update process at any time! + +2. appl_entry_addr + + - Nios application area start address (usually in Flash) + - this is the startup address for autoboot + - each Nios application code we want to update will be copied + to this address + - default is CFG_ADNPESC1_NIOS_APPL_ENTRY + +3. appl_end_addr + + - Nios application area end address (usually in Flash) + - will be used to unprotect/erase the Flash area while updating + - default is CFG_ADNPESC1_NIOS_APPL_END + +4. appl_ident_addr + + - address of the Nios application identification string + - this is the address checked-up by autoboot + - default is CFG_ADNPESC1_NIOS_APPL_IDENT + +5. appl_ident_str + + - the Nios application identification string itself + - default is CFG_ADNPESC1_NIOS_IDENTIFIER + +6. appl_name + + - name of file we have to download/update + - default is ADNPESC1/base32/linux.bin + +7. fs_base_addr + + - optionally file system area start address (usually in Flash) + - each file system we want to update will be copied to this address + - default is CFG_ADNPESC1_FILESYSTEM_BASE + +8. fs_end_addr + + - optionally file system area end address (usually in Flash) + - will be used to unprotect/erase the Flash area while updating + - default is CFG_ADNPESC1_FILESYSTEM_END + +9. fs_name + + - name of file we have to download/update + - default is ADNPESC1/base32/romfs.img diff --git a/doc/README.adnpesc1_base32 b/doc/README.adnpesc1_base32 new file mode 100644 index 0000000..6576044 --- /dev/null +++ b/doc/README.adnpesc1_base32 @@ -0,0 +1,469 @@ + +TODO: specify IDE i/f + + +=============================================================================== + C P U , M E M O R Y , I N / O U T C O M P O N E N T S +=============================================================================== +see also [1]-[5] + +CPU: "DNP_ESC1" + 32 bit NIOS for 50 MHz + 512 Byte for register file (30 levels) + with out instruction cache + with out data cache + 2 KByte On Chip ROM with GERMS boot monitor + with out On Chip RAM + MSTEP multiplier + no Debug Core + no On Chip Instrumentation (OCI) + + U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 + CFG_NIOS_CPU_ICACHE = (not present) + CFG_NIOS_CPU_DCACHE = (not present) + CFG_NIOS_CPU_REG_NUMS = 512 + CFG_NIOS_CPU_MUL = 0 + CFG_NIOS_CPU_MSTEP = 1 + CFG_NIOS_CPU_DBG_CORE = 0 + +IRQ: Nr. | used by + ------+-------------------------------------------------------- + 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 + 17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17 + 18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18 + 20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = + | PIO6 | CFG_NIOS_CPU_PIO6_IRQ = 20 + 25 | SPI0 | CFG_NIOS_CPU_SPI0_IRQ = 25 + 31 | PIO7 | CFG_NIOS_CPU_PIO7_IRQ = 31 + 32 | PIO8 | CFG_NIOS_CPU_PIO8_IRQ = 32 + 33 | PIO9 | CFG_NIOS_CPU_PIO9_IRQ = 33 + 34 | PIO10 | CFG_NIOS_CPU_PIO10_IRQ = 34 + 35 | PIO11 | CFG_NIOS_CPU_PIO11_IRQ = 35 + 36 | PIO12 | CFG_NIOS_CPU_PIO12_IRQ = + | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 36 + 37 | PIO13 | CFG_NIOS_CPU_PIO13_IRQ = + | IDE1 | CFG_NIOS_CPU_IDE1_IRQ = 37 + +MEMORY: 8 MByte Flash + 16 MByte SDRAM + +Timer: TIMER0: high priority programmable timer (IRQ16) + + U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 + CFG_NIOS_CPU_USER_TIMER = (not present) + +PIO: Nr. | description + ------+-------------------------------------------------------- + PIO0 | PORTA: 8 in/outputs for general purpose usage + PIO1 | PORTB: 8 in/outputs for general purpose usage + PIO2 | PORTC: 4 in/outputs for general purpose usage + PIO3 | RCM: 1 input for RCM_EN# jumper (Req.Conf.Mon.) + PIO4 | WDTENA: 1 output to enable the on-board watchdog + PIO5 | WDTTRIG: 1 output to trigger the on-board watchdog + PIO6 | LAN0INT: 1 input for LAN91C111 irq input (IRQ20) + PIO7 | INT1: 1 input for general purpose irq (IRQ31) + PIO8 | INT2: 1 input for general purpose irq (IRQ32) + PIO9 | INT3: 1 input for general purpose irq (IRQ33) + PIO10| INT4: 1 input for general purpose irq (IRQ34) + PIO11| INT5: 1 input for general purpose irq (IRQ35) + PIO12| INT6: 1 input for general purpose irq (IRQ36) + | IDE0INT: (same) for IDE0 irq input + PIO13| INT7: 1 input for general purpose irq (IRQ37) + | IDE1INT: (same) for IDE1 irq input + + U-Boot CFG: CFG_NIOS_CPU_PORTA_PIO = 0 + CFG_NIOS_CPU_PORTB_PIO = 1 + CFG_NIOS_CPU_PORTC_PIO = 2 + CFG_NIOS_CPU_RCM_PIO = 3 + CFG_NIOS_CPU_WDTENA_PIO = 4 + CFG_NIOS_CPU_WDTTRIG_PIO = 5 + CFG_NIOS_CPU_LED_PIO = (not present) + +UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, RTS/CTS (IRQ17) + UART1: fixed baudrate of 115200, fixed protocol 8N1, + without handshake RTS/CTS (IRQ18) + +SPI: SPI0: master capable, 1 slave selectable, 250kHz target clock, + 2 usec targets delay between slave select and clock, + data is transferred MSB-first / LSB-last (IRQ25) + +LAN: SMsC LAN91C111 with: + - without offset + - data bus width 16 bit (on-board hard wired at 32 bit bus) + - !!! 32 bit bus access --> each address * 2 !!! + +IDE: (TODO) + + +=============================================================================== + M E M O R Y M A P +=============================================================================== + +- - - - - - - - - - - external extension - - - - - - - - - - - - - - - - - - - + + 0x44000000 ---32-----------16|15------------0- + | | | \ + : (real size : : | + EXT3 (CS4) : and content : : > CFG_NIOS_CPU_CS3_SIZE + : unknown) : : | = 0x01000000 + | | | / + 0x43000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS3_BASE + | | | \ + : (real size : : | + EXT2 (CS3) : and content : : > CFG_NIOS_CPU_CS2_SIZE + : unknown) : : | = 0x01000000 + | | | / + 0x42000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS2_BASE + | | | \ + : (real size : : | + EXT1 (CS2) : and content : : > CFG_NIOS_CPU_CS1_SIZE + : unknown) : : | = 0x01000000 + | | | / + 0x41000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS1_BASE + | | | \ + : (real size : : | + EXT0 (CS1) : and content : : > CFG_NIOS_CPU_CS0_SIZE + : unknown) : : | = 0x01000000 + | | | / + 0x40000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS0_BASE + | | + : gap : + : : + +- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x03000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK + | . | \ + | . | | (U-Boot run-time system) + | . | | + | . | > CFG_MONITOR_LEN + | . | | = 0x00040000 + | . | | + | . | / + 0x02fc0000 --+32-----------16|15------------0+ TEXT_BASE + | . | \ + | . | > CFG_MALLOC_LEN (heap) + | . | / + --+32-----------16|15------------0+ + | . | \ + | . | > CFG_GBL_DATA_SIZE (global) + | . | / + --+32-----------16|15------------0+ CFG_INIT_SP (u-boot stack) + | . | \ \ + | . | | | + | . | | > stack area + | . | | | + | . | | V + | . | | + | . | | + SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE + | . | | = 0x01000000 + | . | | + 0x02000100 |- - - - - - - - - - - - - - - -+-|- + | . | | \ + | . | | | + | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | | = 0x00000100 + | | / / + 0x02000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE + 0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + | | \ + : gap : > (space for 2nd Flash) + | | / + 0x01800000 ---32-----------16|15------------0- + | sector 127 | \ + + 0x7f0000 |- - - - - - - - - - - - - - - -| | + | : | | + Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + | sector 1 : | | = 0x00800000 + + 0x010000 |- - - - - - - - - - - - - - - -| | + | sector 0 (size = 0x10000) | / + 0x01000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + | | + : gap : + : : + +- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00010020 ---32-----------16|15------------0- + | | \ + | register bank | | + | size = (real_size << 1) | | + | real_size = 0x10 | | + | +--------.---.---.--- | | + | | bank 0 \ 1 \ 2 \ 3 \ | | + | |---------------------------+ | | + LAN91C111 | | BANK | RESERVED | | > na_enet_size + | |- - - - - - -|- - - - - - -| | | = 0x00000020 + | | RPCR | MIR | | | + | |- - - - - - -|- - - - - - -| | | + | | COUNTER | RCR | | | + | |- - - - - - -|- - - - - - -| | | + | | EPH STATUS | TCR | | | + | +---------------------------+ | / + 0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + | | + : gap : + : : + +- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00001040 ---32-----------16|15------------0- + | | | \ + : : : | + IDE1 i/f : : : > 0x00000020 + [5] : : : | + | | | / + 0x00001020 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE1 + | | | \ + : : : | + IDE0 i/f : : : > 0x00000020 + [5] : : : | + | | | / + 0x00001000 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + | | + : gap : + | | + 0x00000980 ---32-----------16|15------------0- + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO13 | interruptmask (1 bit) (rw) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x00000970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO13 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO12 | interruptmask (1 bit) (rw) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x00000960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO12 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO11 | interruptmask (1 bit) (rw) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x00000950 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO11 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO10 | interruptmask (1 bit) (rw) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x00000940 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO10 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO9 | interruptmask (1 bit) (rw) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x00000930 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO9 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO8 | interruptmask (1 bit) (rw) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x00000920 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO8 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO7 | interruptmask (1 bit) (rw) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x00000910 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO6 | interruptmask (1 bit) (rw) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6 + | | + : gap : + | | + 0x000008e0 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | endofpacket (16 bit) (rw) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | slaveselect (1 bit) (rw) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + SPI0 | (reserved) | | + [4] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | control (11 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (9 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (16 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (16 bit) (ro) | / + 0x000008c0 ---32-----------16|15------------0- CFG_NIOS_CPU_SPI0 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO5 | (unused) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x000008b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO4 | (unused) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO3 | (unused) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x00000890 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO2 | (unused) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (4 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (4 bit) (rw) | / + 0x00000880 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO1 | (unused) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (8 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (8 bit) (rw) | / + 0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO0 | (unused) | | + [3] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (8 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (8 bit) (rw) | / + 0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | snaph (16 bit) (rw) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER0 | snapl (16 bit) (rw) | | + [2] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | periodh (16 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | periodl (16 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (4 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART1 | (unused) | > 0x00000020 + [1] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x00000820 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART0 | (unused) | > 0x00000020 + [1] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + +- - - - - - - - - - - on chip memory 1 - - - - - - - - - - - + + 0x00000800 ---32-----------16|15------------0- + | : | \ + | : | | + GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + | : | | = 0x00000800 + | : | / + 0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT + 0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + + +=============================================================================== + F L A S H M E M O R Y A L L O C A T I O N +=============================================================================== + + 0x01800000 ---8-------------4|3-------------0- + | : | \ + | : | | + | : | > 6 MByte ROM FS + | : | | + | : | / + 0x01200000 --+- - - - - - - -:- - - - - - - -+- - file system image(s) + | : | \ + | : | | + | : | > 1728 kByte ucLinux + | : | | + | : | / + 0x01050000 --+- - - - - - - -:- - - - - - - -+- - os image(s) + | : | \ + 0x01040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment + | : | | + | : | > 320 kByte U-Boot + | : | | + | : | | + | : | / + 0x01000000 --+- - - - - - - -:- - - - - - - -+- - u-boot _start() + 0x01000000 ---8-------------4|3-------------0- + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[2] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[3] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[4] http://www.altera.com/literature/ds/ds_nios_spi.pdf +[5] http://www.t13.org/index.html + + +=============================================================================== +Stephan Linz diff --git a/doc/README.alaska8220 b/doc/README.alaska8220 new file mode 100644 index 0000000..8e659f3 --- /dev/null +++ b/doc/README.alaska8220 @@ -0,0 +1,482 @@ +Freescale Alaska MPC8220 board +============================== + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 9/21/04 +=========================================== + + +Changed files: +============== + +- Makefile added MPC8220 and Alaska8220_config +- MAKEALL added MPC8220 and Alaska8220 +- README added CONFIG_MPC8220, Alaska8220_config + +- common/cmd_bdinfo.c added board information members for MPC8220 +- common/cmd_bootm.c added clocks for MPC8220 in do_bootm_linux() + +- include/common.h added CONFIG_MPC8220 + +- include/asm-ppc/u-boot.h added board information members for MPC8220 +- include/asm-ppc/global_data.h added global variables - inp_clk, pci_clk, + vco_clk, pev_clk, flb_clk, and bExtUart + +- lib_ppc/board.c added CONFIG_MPC8220 support + +- net/eth.c added FEC support for MPC8220 + +Added files: +============ +- board/alaska directory for Alaska MPC8220 +- board/alaska/alaska.c Alaska dram and BATs setup +- board/alaska/extserial.c external serial (debug card serial) support +- board/alaska/flash.c Socket (AMD) and Onboard (INTEL) flash support +- board/alaska/serial.c to determine which int/ext serial to use +- board/alaska/Makefile Makefile +- board/alaska/config.mk config make +- board/alaska/u-boot.lds Linker description + +- cpu/mpc8220/dma.h multi-channel dma header file +- cpu/mpc8220/dramSetup.h dram setup header file +- cpu/mpc8220/fec.h MPC8220 FEC header file +- cpu/mpc8220/cpu.c cpu specific code +- cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup +- cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup +- cpu/mpc8220/fec.c MPC8220 FEC driver +- cpu/mpc8220/i2c.c MPC8220 I2C driver +- cpu/mpc8220/interrupts.c interrupt support (not enable) +- cpu/mpc8220/loadtask.c load dma +- cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock +- cpu/mpc8220/traps.c exception +- cpu/mpc8220/uart.c MPC8220 UART driver +- cpu/mpc8220/Makefile Makefile +- cpu/mpc8220/config.mk config make +- cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program +- cpu/mpc8220/io.S io functions +- cpu/mpc8220/start.S start up + +- include/mpc8220.h + +- include/asm-ppc/immap_8220.h + +- include/configs/Alaska8220.h + + +1. SWITCH SETTINGS +================== +1.1 SW1: 0 - Boot from Socket Flash (AMD) or 1 - Onboard Flash (INTEL) + SW2: 0 - Select MPC8220 UART or 1 - Debug Card UART + SW3: unsed + SW4: 0 - 1284 or 1 - FEC1 + SW5: 0 - PEV or 1 - FEC2 + + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + DDR: 0x00000000-0x1fffffff (max 512MB) + MBAR: 0xf0000000-0xf0027fff (128KB) + CPLD: 0xf1000000-0xf103ffff (256KB) + FPGA: 0xf2000000-0xf203ffff (256KB) + Flash: 0xfe000000-0xffffffff (max 32MB) + +3. DEFINITIONS AND COMPILATION +============================== +3.1 Explanation on NEW definitions in include/configs/alaska8220.h + CONFIG_MPC8220 MPC8220 specific + CONFIG_ALASKA8220 Alaska board specific + CFG_MPC8220_CLKIN Define Alaska Input Clock + CONFIG_PSC_CONSOLE Enable MPC8220 UART + CONFIG_EXTUART_CONSOLE Enable External 16552 UART + CFG_AMD_BOOT To determine the u-boot is booted from AMD or Intel + CFG_MBAR MBAR base address + CFG_DEFAULT_MBAR Reset MBAR base address + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1-1-x + make distclean + make Alaska8220_config + make + + +4. SCREEN DUMP +============== +4.1 Alaska MPC8220 board + Boot from AMD (NOTE: May not show exactly the same) + +U-Boot 1.1.1 (Sep 22 2004 - 22:14:41) + +CPU: MPC8220 (JTAG ID 1640301d) at 300 MHz + Bus 120 MHz, CPU 300 MHz, PCI 30 MHz, VCO 480 MHz +Board: Alaska MPC8220 Evaluation Board +I2C: 93 kHz, ready +DRAM: 256 MB +Reserving 167k for U-Boot at: 0ffd6000 +FLASH: 16.5 MB +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: FEC ETHERNET +=> flinfo + +Bank # 1: INTEL 28F128J3A + Size: 8 MB in 64 Sectors + Sector Start Addresses: + FE000000 FE020000 FE040000 FE060000 FE080000 + FE0A0000 FE0C0000 FE0E0000 FE100000 FE120000 + FE140000 FE160000 FE180000 FE1A0000 FE1C0000 + FE1E0000 FE200000 FE220000 FE240000 FE260000 + FE280000 FE2A0000 FE2C0000 FE2E0000 FE300000 + FE320000 FE340000 FE360000 FE380000 FE3A0000 + FE3C0000 FE3E0000 FE400000 FE420000 FE440000 + FE460000 FE480000 FE4A0000 FE4C0000 FE4E0000 + FE500000 FE520000 FE540000 FE560000 FE580000 + FE5A0000 FE5C0000 FE5E0000 FE600000 FE620000 + FE640000 FE660000 FE680000 FE6A0000 FE6C0000 + FE6E0000 FE700000 FE720000 FE740000 FE760000 + FE780000 FE7A0000 FE7C0000 FE7E0000 + +Bank # 2: INTEL 28F128J3A + Size: 8 MB in 64 Sectors + Sector Start Addresses: + FE800000 FE820000 FE840000 FE860000 FE880000 + FE8A0000 FE8C0000 FE8E0000 FE900000 FE920000 + FE940000 FE960000 FE980000 FE9A0000 FE9C0000 + FE9E0000 FEA00000 FEA20000 FEA40000 FEA60000 + FEA80000 FEAA0000 FEAC0000 FEAE0000 FEB00000 + FEB20000 FEB40000 FEB60000 FEB80000 FEBA0000 + FEBC0000 FEBE0000 FEC00000 FEC20000 FEC40000 + FEC60000 FEC80000 FECA0000 FECC0000 FECE0000 + FED00000 FED20000 FED40000 FED60000 FED80000 + FEDA0000 FEDC0000 FEDE0000 FEE00000 FEE20000 + FEE40000 FEE60000 FEE80000 FEEA0000 FEEC0000 + FEEE0000 FEF00000 (RO) FEF20000 (RO) FEF40000 FEF60000 + FEF80000 FEFA0000 FEFC0000 FEFE0000 (RO) + +Bank # 3: AMD AMD29F040B + Size: 0 MB in 7 Sectors + Sector Start Addresses: + FFF00000 (RO) FFF10000 (RO) FFF20000 (RO) FFF30000 FFF40000 + FFF50000 FFF60000 + +Bank # 4: AMD AMD29F040B + Size: 0 MB in 1 Sectors + Sector Start Addresses: + FFF70000 (RO) +=> bdinfo + +memstart = 0xF0009800 +memsize = 0x10000000 +flashstart = 0xFFF00000 +flashsize = 0x01080000 +flashoffset = 0x00025000 +sramstart = 0xF0020000 +sramsize = 0x00008000 +bootflags = 0x00000001 +intfreq = 300 MHz +busfreq = 120 MHz +inpfreq = 30 MHz +flbfreq = 30 MHz +pcifreq = 30 MHz +vcofreq = 480 MHz +pevfreq = 81 MHz +ethaddr = 00:E0:0C:BC:E0:60 +eth1addr = 00:E0:0C:BC:E0:61 +IP addr = 192.162.1.2 +baudrate = 115200 bps +=> printenv +bootargs=root=/dev/ram rw +bootdelay=5 +baudrate=115200 +ethaddr=00:e0:0c:bc:e0:60 +eth1addr=00:e0:0c:bc:e0:61 +ipaddr=192.162.1.2 +serverip=192.162.1.1 +gatewayip=192.162.1.1 +netmask=255.255.255.0 +hostname=Alaska +stdin=serial +stdout=serial +stderr=serial +ethact=FEC ETHERNET + +Environment size: 268/65532 bytes +=> setenv ipaddr 192.160.1.2 +=> setenv serverip 192.160.1.1 +=> setenv gatewayip 192.160.1.1 +=> saveenv +Saving Environment to Flash... + +. +Un-Protected 1 sectors +Erasing Flash... +Erasing sector 0 ... done +Erased 1 sectors +Writing to Flash... done + +. +Protected 1 sectors +=> tftp 0x10000 linux.elf +Using FEC ETHERNET device +TFTP from server 192.160.1.1; our IP address is 192.160.1.2; sending through gateway 192.160.1.1 +Filename 'linux.elf'. +Load address: 0x10000 +Loading: invalid RARP header +################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################## +done +Bytes transferred = 2917494 (2c8476 hex) +=> bootelf +Loading .text @ 0x00a00000 (23820 bytes) +Loading .data @ 0x00a06000 (2752512 bytes) +Clearing .bss @ 0x00ca6000 (12764 bytes) +## Starting application at 0x00a00000 ... + +Collect some entropy from RAM........done +loaded at: 00A00000 00CA91DC +zimage at: 00A06A93 00AD7756 +initrd at: 00AD8000 00CA5565 +avail ram: 00CAA000 014AA000 + +Linux/PPC load: ip=off console=ttyS0,115200 +Uncompressing Linux...done. +Now booting the kernel +Total memory in system: 256 MB +Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb +Linux version 2.4.21-rc1 (r61688@bluesocks.sps.mot.com) (gcc version 3.3.1) #17 Wed Sep 8 11:49:16 CDT 2004 +Motorola Alaska port (C) 2003 Motorola, Inc. +CPLD rev 3 +CPLD switches 0x1b +Set Pin Mux for FEC1 +Set Pin Mux for FEC2 +Alaska Pin Multiplexing: +Port Configuration Register 0 = 0 +Port Configuration Register 1 = 0 +Port Configuration Register 2 = 0 +Port Configuration Register 3 = 50000000 +Port Configuration Register 3 - PCI = 51400180 +Setup Alaska FPGA PIC: +Interrupt Enable Register *(u32) = 0 +Interrupt Status Register = 2f0000 +Interrupt Enable Register in_be32 = 0 +Interrupt Status Register = 2f0000 +Interrupt Enable Register in_le32 = 0 +Interrupt Status Register = 2f00 +Interrupt Enable Register readl = 0 +Interrupt Status Register = 2f00 +Interrupt Enable Register = 0 +Interrupt Status Register = 2f0000 +Setup Alaska PCI Controller: +On node 0 totalpages: 65536 +zone(0): 65536 pages. +zone(1): 0 pages. +zone(2): 0 pages. +Kernel command line: ip=off console=ttyS0,115200 +Using XLB clock (120.00 MHz) to set up decrementer +Calibrating delay loop... 199.88 BogoMIPS +Memory: 254792k available (1476k kernel code, 708k data, 228k init, 0k highmem) +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes) +Inode cache hash table entries: 16384 (order: 5, 131072 bytes) +Mount cache hash table entries: 512 (order: 0, 4096 bytes) +Buffer-cache hash table entries: 16384 (order: 4, 65536 bytes) +Page-cache hash table entries: 65536 (order: 6, 262144 bytes) +POSIX conformance testing by UNIFIX +PCI: Probing PCI hardware +PCI: (pcibios_init) Global-Hose = 0xc029d000 +Scanning bus 00 +Fixups for bus 00 +Bus scan for 00 returning with max=00 +PCI: (pcibios_init) finished pci_scan_bus(hose->first_busno = 0, hose->ops = c01a1a74, hose = c029d000) +PCI: (pcibios_init) PCI Bus Count = 0 =?= Next Bus# = 1 +PCI: (pcibios_init@pci_fixup_irqs) finished machine dependent PCI interrupt routing! +PCI: bridge rsrc 81000000..81ffffff (100), parent c01a7f88 +PCI: bridge rsrc 84000000..87ffffff (200), parent c01a7fa4 +PCI: (pcibios_init) finished allocating and assigning resources! +initDma! +Using 90 DMA buffer descriptors +descUsed f0023600, descriptors f002360c freeSram f0024140 +unmask SDMA tasks: 0xf0008018 = 0x6f000000 +Linux NET4.0 for Linux 2.4 +Based upon Swansea University Computer Society NET3.039 +Initializing RT netlink socket +Starting kswapd +Journalled Block Device driver loaded +JFFS version 1.0, (C) 1999, 2000 Axis Communications AB +JFFS2 version 2.1. (C) 2001 Red Hat, Inc., designed by Axis Communications AB. +pty: 256 Unix98 ptys configured +tracek: Copyright (C) Motorola, 2003. +Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled +ttyS00 at 0xf1001008 (irq = 73) is a ST16650 +ttyS01 at 0xf1001010 (irq = 74) is a ST16650 +elp-fpanel: Copyright (C) Motorola, 2003. +fpanel: fpanelWait timeout +elp-engine: Copyright (C) Motorola, 2003. +Video disabled due to configuration switch 4 +Alpine 1284 driver: Copyright (C) Motorola, 2003. +1284 disabled due to configuration switch 5 +Alpine USB driver: Copyright (C) Motorola, 2003. +OK +USB: Descriptor download completed OK +enable_irq(41) unbalanced +enable_irq(75) unbalanced +elp-dmaram: Copyright (C) Motorola, 2003. +Total memory in system: 256 MB +elp_dmaram: offset is 0x10000000, size is 0 +Xicor NVRAM driver: Copyright (C) Motorola, 2003. +elp-video: Copyright (C) Motorola, 2003. +Video disabled due to configuration switch 4 +elp-pfm: Copyright (C) Motorola, 2003. +paddle: Copyright (C) Motorola, 2001, present. +RAMDISK driver initialized: 16 RAM disks of 12288K size 1024 blocksize +loop: loaded (max 8 devices) +PPP generic driver version 2.4.2 +PPP Deflate Compression module registered +Uniform Multi-Platform E-IDE driver Revision: 7.00beta-2.4 +ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx +init_alaska_mtd: chip probing count 0 +cfi_cmdset_0001: Erase suspend on write enabled +Using buffer write method +init_alaska_mtd: bank1, name:ALASKA0, size:16777216bytes +ALASKA flash0: Using Static image partition definition +Creating 3 MTD partitions on "ALASKA0": +0x00000000-0x00280000 : "kernel" +0x00280000-0x00fe0000 : "user" +0x00fe0000-0x01000000 : "signature" +mgt_fec_module_init +mgt_fec_init() +mgt_fec_init +mgt_init_fec_dev(0xc05f6000,0) +dev c05f6000 fec_priv c05f6160 fec f0009000 +mgt_init_fec_dev(0xc05f6800,1) +dev c05f6800 fec_priv c05f6960 fec f0009800 +NET4: Linux TCP/IP 1.0 for NET4.0 +IP Protocols: ICMP, UDP, TCP, IGMP +IP: routing cache hash table of 2048 buckets, 16Kbytes +TCP: Hash tables configured (established 16384 bind 32768) +NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. +RAMDISK: Compressed image found at block 0 +Freeing initrd memory: 1845k freed +JFFS: Trying to mount a non-mtd device. +VFS: Mounted root (romfs filesystem) readonly. +Freeing unused kernel memory: 228k init +INIT: version 2.78 booting +INIT: Entering runlevel: 1 +"Space, a great big place of unknown stuff." -Dexter, for our MotD. +[01/Jan/1970:00:00:01 +0000] boa: server version Boa/0.94.8.3 +[01/Jan/1970:00:00:01 +0000] boa: server built Sep 7 2004 at 17:40:55. +[01/Jan/1970:00:00:01 +0000] boa: starting server pid=28, port 80 +Mounting flash filesystem, will take a minute... +/etc/rc: line 30: /dev/lp0: No such devish-2.05b# +sh-2.05b# ifup eth0 +client (v0.9.9-pre) started +adapter index 2 +adapter hardware address 00:e0:0c:bc:e0:60 +execle'ing /usr/share/udhcpc/default.script +/sbin/ifconfig eth0 +eth0 Link encap:Ethernet HWaddr 00:E0:0C:BC:E0:60 + BROADCAST MULTICAST MTU:1500 Metric:1 + mgt_fec_open + Rfec request irq +X fec_open: rcv_ring_size 8, xmt_ring_size 8 +packmgt_fec_open(): call netif_start_queue() +ets:0 errors:0 dropped:0 overruns:0 frame:0 + TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 + collisions:0 txqueuelen:100 + RX bytes:0 (0.0 b) TX bytes:0 (0.0 b) + Base address:0x9000 + +/sbin/ifconfig eth0 up +entering raw listen mode +Opening raw socket on ifindex 2 +adding option 0x35 +adding option 0x3d +adding option 0x3c +Sending discover... +Waiting on select... +unrelated/bogus packet +Waiting on select... +oooooh!!! got some! +adding option 0x35 +adding option 0x3d +adding option 0x3c +adding option 0x32 +adding option 0x36 +Sending select for 163.12.48.146... +Waiting on select... +oooooh!!! got some! +Waiting on select... +oooooh!!! got some! +Lease of 163.12.48.146 obtained, lease time 345600 +execle'ing /usr/share/udhcpc/default.script +/sbin/ifconfig eth0 163.12.48.146 netmask 255.255.254.0 +/sbin/ifconfig eth0 up +deleting routers +/sbin/route del default +/sbin/route add default gw 163.12.49.254 dev eth0 +adding dns 163.12.252.230 +adding dns 192.55.22.4 +adding dns 192.5.249.4 +entering none listen mode +sh-2.05b# + +5. REPROGRAM U-BOOT +=================== +5.1 Reprogram u-boot (boot from AMD) + 1. Unprotect the boot sector + => protect off bank 3 + 2. Download new u-boot binary file + => tftp 0x10000 u-boot.bin + 3. Erase bootsector (max 7 sectors) + => erase 0xfff00000 0xfff6ffff + 4. Program the u-boot to flash + => cp.b 0x10000 0xfff00000 + 5. Reset for the new u-boot to take place + => reset + +5.2 Reprogram u-boot (boot from AMD program at INTEL) + 1. Unprotect the boot sector + => protect off bank 2 + 2. Download new u-boot binary file + => tftp 0x10000 u-boot.bin + 3. Erase bootsector (max 7 sectors) + => erase 0xfef00000 0xfefdffff + 4. Program the u-boot to flash + => cp.b 0x10000 0xfef00000 + 5. Reset for the new u-boot to take place + => reset + +5.3 Reprogram u-boot (boot from INTEL) + 1. Unprotect the boot sector + => protect off bank 4 + 2. Download new u-boot binary file + => tftp 0x10000 u-boot.bin + 3. Erase bootsector (max 7 sectors) + => erase 0xfff00000 0xfffdffff + 4. Program the u-boot to flash + => cp.b 0x10000 0xfff00000 + 5. Reset for the new u-boot to take place + => reset + +5.4 Reprogram u-boot (boot from INTEL program at AMD) + 1. Unprotect the boot sector + => protect off bank 1 + 2. Download new u-boot binary file + => tftp 0x10000 u-boot.bin + 3. Erase bootsector (max 7 sectors) + => erase 0xfe080000 0xfe0effff + 4. Program the u-boot to flash + => cp.b 0x10000 0xfe080000 + 5. Reset for the new u-boot to take place + => reset diff --git a/doc/README.amigaone b/doc/README.amigaone new file mode 100644 index 0000000..9975977 --- /dev/null +++ b/doc/README.amigaone @@ -0,0 +1,12 @@ +AmigaOne U-Boot and the SciTech emulator + +The directory board/MAI/bios_emulator contains the source code +of the SciTech x86 emulator. This emulator is normally available +under a BSD license. However, SciTech kindly gave us permission +to use their emulator in PPCBoot for the AmigaOne. It's available +in this form only under GPL. + +Thanks to Kendall Bennett and the rest of the team at SciTech. +See http://www.scitechsoft.com for their web site + +The GPL license can be found at http://www.gnu.org/licenses/gpl.html diff --git a/doc/README.autoboot b/doc/README.autoboot new file mode 100644 index 0000000..e4c4186 --- /dev/null +++ b/doc/README.autoboot @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2001 + * Dave Ellis, SIXNET, dge@sixnetio.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +Using autoboot configuration options +==================================== + +The basic autoboot configuration options are documented in the main +U-Boot README. See it for details. They are: + + bootdelay + bootcmd + CONFIG_BOOTDELAY + CONFIG_BOOTCOMMAND + +Some additional options that make autoboot safer in a production +product are documented here. + +Why use them? +------------- + +The basic autoboot feature allows a system to automatically boot to +the real application (such as Linux) without a user having to enter +any commands. If any key is pressed before the boot delay time +expires, U-Boot stops the autoboot process, gives a U-Boot prompt +and waits forever for a command. That's a good thing if you pressed a +key because you wanted to get the prompt. + +It's not so good if the key press was a stray character on the +console serial port, say because a user who knows nothing about +U-Boot pressed a key before the system had time to boot. It's even +worse on an embedded product that doesn't have a console during +normal use. The modem plugged into that console port sends a +character at the wrong time and the system hangs, with no clue as to +why it isn't working. + +You might want the system to autoboot to recover after an external +configuration program stops autoboot. If the configuration program +dies or loses its connection (modems can disconnect at the worst +time) U-Boot will patiently wait forever for it to finish. + +These additional configuration options can help provide a system that +boots when it should, but still allows access to U-Boot. + +What they do +------------ + + CONFIG_BOOT_RETRY_TIME + CONFIG_BOOT_RETRY_MIN + + "bootretry" environment variable + + These options determine what happens after autoboot is + stopped and U-Boot is waiting for commands. + + CONFIG_BOOT_RETRY_TIME must be defined to enable the boot + retry feature. If the environment variable "bootretry" is + found then its value is used, otherwise the retry timeout is + CONFIG_BOOT_RETRY_TIME. CONFIG_BOOT_RETRY_MIN is optional and + defaults to CONFIG_BOOT_RETRY_TIME. All times are in seconds. + + If the retry timeout is negative, the U-Boot command prompt + never times out. Otherwise it is forced to be at least + CONFIG_BOOT_RETRY_MIN seconds. If no valid U-Boot command is + entered before the specified time the boot delay sequence is + restarted. Each command that U-Boot executes restarts the + timeout. + + If CONFIG_BOOT_RETRY_TIME < 0 the feature is there, but + doesn't do anything unless the environment variable + "bootretry" is >= 0. + + CONFIG_AUTOBOOT_KEYED + CONFIG_AUTOBOOT_PROMPT + CONFIG_AUTOBOOT_DELAY_STR + CONFIG_AUTOBOOT_STOP_STR + CONFIG_AUTOBOOT_DELAY_STR2 + CONFIG_AUTOBOOT_STOP_STR2 + + "bootdelaykey" environment variable + "bootstopkey" environment variable + "bootdelaykey2" environment variable + "bootstopkey2" environment variable + + These options give more control over stopping autoboot. When + they are used a specific character or string is required to + stop or delay autoboot. + + Define CONFIG_AUTOBOOT_KEYED (no value required) to enable + this group of options. CONFIG_AUTOBOOT_DELAY_STR, + CONFIG_AUTOBOOT_STOP_STR or both should be specified (or + specified by the corresponding environment variable), + otherwise there is no way to stop autoboot. + + CONFIG_AUTOBOOT_PROMPT is displayed before the boot delay + selected by CONFIG_BOOTDELAY starts. If it is not defined + there is no output indicating that autoboot is in progress. + If "%d" is included, it is replaced by the number of seconds + remaining before autoboot will start, but it does not count + down the seconds. "autoboot in %d seconds\n" is a reasonable + prompt. + + If CONFIG_AUTOBOOT_DELAY_STR or "bootdelaykey" is specified + and this string is received from console input before + autoboot starts booting, U-Boot gives a command prompt. The + U-Boot prompt will time out if CONFIG_BOOT_RETRY_TIME is + used, otherwise it never times out. + + If CONFIG_AUTOBOOT_STOP_STR or "bootstopkey" is specified and + this string is received from console input before autoboot + starts booting, U-Boot gives a command prompt. The U-Boot + prompt never times out, even if CONFIG_BOOT_RETRY_TIME is + used. + + The string recognition is not very sophisticated. If a + partial match is detected, the first non-matching character + is checked to see if starts a new match. There is no check + for a shorter partial match, so it's best if the first + character of a key string does not appear in the rest of the + string. + + Using the CONFIG_AUTOBOOT_DELAY_STR2 #define or the + "bootdelaykey2" environment variable and/or the + CONFIG_AUTOBOOT_STOP_STR2 #define or the "bootstopkey" + environment variable you can specify a second, alternate + string (which allows you to have two "password" strings). + + CONFIG_ZERO_BOOTDELAY_CHECK + + If this option is defined, you can stop the autoboot process + by hitting a key even in that case when "bootdelay" has been + set to 0. You can set "bootdelay" to a negative value to + prevent the check for console input. + + CONFIG_RESET_TO_RETRY + + (Only effective when CONFIG_BOOT_RETRY_TIME is also set) + After the countdown timed out, the board will be reset to restart + again. diff --git a/doc/README.bedbug b/doc/README.bedbug new file mode 100644 index 0000000..9cfb421 --- /dev/null +++ b/doc/README.bedbug @@ -0,0 +1,88 @@ +BEDBUG Support for U-Boot +-------------------------- + +These changes implement the bedbug (emBEDded deBUGger) debugger in U-Boot. +A specific implementation is made for the AMCC 405 processor but other flavors +can be easily implemented. + +##################### +### Modifications ### +##################### + +./common/Makefile + Included cmd_bedbug.c and bedbug.c in the Makefile. + +./common/command.c + Added bedbug commands to command table. + +./common/board.c + Added call to initialize debugger on startup. + +./cpu/ppc4xx/Makefile + Added bedbug_405.c to the Makefile. + +./cpu/ppc4xx/start.S + Added code to handle the debug exception (0x2000) on the 405. + Also added code to handle critical exceptions since the debug + is treated as critical on the 405. + +./cpu/ppc4xx/traps.c + Added more detailed output for the program exception to tell + if it is an illegal instruction, privileged instruction or + a trap. Also added debug trap handler. + +./include/cmd_confdefs.h + Added definition of CFG_CMD_BEDBUG. + +./include/config_WALNUT405.h + Added CFG_CMD_BEDBUG to the CONFIG_COMMANDS for the WALNUT. + +./include/ppc_asm.tmpl + Added code to handle critical exceptions + +################# +### New Stuff ### +################# + +./include/bedbug/ppc.h +./include/bedbug/regs.h +./include/bedbug/bedbug.h +./include/bedbug/elf.h [obsoleted by new include/elf.h] +./include/bedbug/tables.h +./include/cmd_bedbug.h +./common/cmd_bedbug.c +./common/bedbug.c + Bedbug library includes code for assembling and disassembling + PowerPC instructions to/from memory as well as handling + hardware breakpoints and stepping through code. These + routines are common to all PowerPC processors. + +./cpu/ppc4xx/bedbug_405.c + AMCC PPC405 specific debugger routines. + + +Bedbug support for the MPC860 +----------------------------- + +Changes: + + common/cmd_bedbug.c + Added call to initialize 860 debugger. + + cpu/mpc8xx/Makefile + Added new file "bedbug_860.c" to the makefile + + cpu/mpc8xx/start.S + Added handler for InstructionBreakpoint (0xfd00) + + cpu/mpc8xx/traps.c + Added new routine DebugException() + + include/config_MBX.h + Added CFG_CMD_BEDBUG to CONFIG_COMMANDS define + + +New Files: + + cpu/mpc8xx/bedbug_860.c + CPU-specific routines for 860 debug registers. diff --git a/doc/README.cmi b/doc/README.cmi new file mode 100644 index 0000000..884854d --- /dev/null +++ b/doc/README.cmi @@ -0,0 +1,84 @@ + +Summary: +======== + +This file contains information about the cmi board configuration. +Please see cmi_mpc5xx_config for further details. The cmi board is +a customer specific board but should work with small modifications +on every board which has a MPC5xx and either a 28F128J3A, +28F320J3A or 28F640J3A Intel flash mounted. + +Board Discription: +================== + +* Motorola MPC555 +* RS232 connection +* Intel flash 28F640J3A +* Micron SRAM 1M +* Altera PLD + +Bootstrap: +========== + +In contrast to the usual boot sequence used in U-Boot, on the +cmi board we don't boot from the external flash directly. +Because of we use a 16-bit flash and don't sample a RCW +from the data bus to set the startup buswidth to 16-bit. +Unfortunatly the default width, sampled from the default RCW +is 32-bit. For this reason we burn the proper RCW into the +internal flash shadow location and boot after power-on or +reset from the internal flash and then branch to 0x02000100 +where the U-Boot reset vector handler is located. + +Memory Map: +=========== + +Memory Map after relocation: + + 0x0000 0000 CFG_SDRAM_BASE + : + 0x000F 9FFF + : + : + 0x0100 0000 CFG_IMMR (Internal memory map base adress) + : + 0x0130 7FFF + : + : + 0x0200 0000 CFG_FLASH_BASE + : + 0x027C FFFF + : + : + 0x0300 0000 PLD_BASE + +Flash Partition: + + 0x0200 0000 Block 0 and 1 contain U-Boot except + : environment + : + 0x0201 FFFF + 0x0202 0000 Block 2 contains environment (.ppcenv) + : + 0x0202 FFFF + +See README file for futher information about U-Boot relocation +and partitioning. + +Tested Features: +================ + +* U-Boot commands: go, loads, loadb, all memory features, printenv, + setenv, saveenv, protect, erase, fli, bdi, mtest, reset, version, + coninfo, help (see configuration file for available commands) + +* Blinking led to indicate boot process + +Added or Changed Files: +======================= + +u-boot-0.2.0/board/cmi/* +u-boot-0.2.0/include/configs/cmi_mpc5xx.h + +Regards, +Martin diff --git a/doc/README.commands b/doc/README.commands new file mode 100644 index 0000000..d678992 --- /dev/null +++ b/doc/README.commands @@ -0,0 +1,31 @@ + +Commands are added to U-Boot by creating a new command structure. +This is done by first including command.h + +Then using the U_BOOT_CMD() macro to fill in a cmd_tbl_t struct. + +U_BOOT_CMD(name,maxargs,repeatable,command,"usage","help") + +name: is the name of the commad. THIS IS NOT a string. +maxargs: the maximumn numbers of arguments this function takes +command: Function pointer (*cmd)(struct cmd_tbl_s *, int, int, char *[]); +usage: Short description. This is a string +help: long description. This is a string + + +**** Behinde the scene ****** + +The structure created is named with a special prefix (__u_boot_cmd_) +and placed by the linker in a special section. + +This makes it possible for the final link to extract all commands +compiled into any object code and construct a static array so the +command can be found in an array starting at __u_boot_cmd_start. + +If a new board is defined do not forget to define the command section +by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these +3 lines: + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; diff --git a/doc/README.commands.itest b/doc/README.commands.itest new file mode 100644 index 0000000..5e0fe86 --- /dev/null +++ b/doc/README.commands.itest @@ -0,0 +1,16 @@ +A slow day today so here is a revised itest command with provisional +support for comparing strings as well :-)) + +Now table driven to allow the operators +-eq, -ne, -lt, -gt, -le, -ge, ==, !=, <>, <, >, <=, >= + +Uses the expected command modifier for integer compares of width 1, 2 or +4 bytes of .b, .w, .l and the new modifer of .s for a string compare. +String comparison is over the length of the shorter, this hopefully +avoids missing terminators when using an indirect pointer. + +eg. +if itest.l *40000 == 12345678 then; .... +if itest.w *40000 != 1234 then; .... +if itest.b *40000 >= 12 then; .... +if itest.s *40000 -eq hello then; .... diff --git a/doc/README.console b/doc/README.console new file mode 100644 index 0000000..6d477df --- /dev/null +++ b/doc/README.console @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +U-Boot console handling +======================== + +HOW THE CONSOLE WORKS? +---------------------- + +At system startup U-Boot initializes a serial console. When U-Boot +relocates itself to RAM, all console drivers are initialized (they +will register all detected console devices to the system for further +use). + +If not defined in the environment, the first input device is assigned +to the 'stdin' file, the first output one to 'stdout' and 'stderr'. + +You can use the command "coninfo" to see all registered console +devices and their flags. You can assign a standard file (stdin, +stdout or stderr) to any device you see in that list simply by +assigning its name to the corresponding environment variable. For +example: + + setenv stdin wl_kbd <- To use the wireless keyboard + setenv stdout video <- To use the video console + +Do a simple "saveenv" to save the console settings in the environment +and get them working on the next startup, too. + +HOW CAN I USE STANDARD FILE INTO THE SOURCES? +--------------------------------------------- + +You can use the following functions to access the console: + +* STDOUT: + putc (to put a char to stdout) + puts (to put a string to stdout) + printf (to format and put a string to stdout) + +* STDIN: + tstc (to test for the presence of a char in stdin) + getc (to get a char from stdin) + +* STDERR: + eputc (to put a char to stderr) + eputs (to put a string to stderr) + eprintf (to format and put a string to stderr) + +* FILE (can be 'stdin', 'stdout', 'stderr'): + fputc (like putc but redirected to a file) + fputs (like puts but redirected to a file) + fprintf (like printf but redirected to a file) + ftstc (like tstc but redirected to a file) + fgetc (like getc but redirected to a file) + +Remember that all FILE-related functions CANNOT be used before +U-Boot relocation (done in 'board_init_r' in common/board.c). + +HOW CAN I USE STANDARD FILE INTO APPLICATIONS? +---------------------------------------------- + +Use the 'bd_mon_fnc' field of the bd_t structure passed to the +application to do everything you want with the console. + +But REMEMBER that that will work only if you have not overwritten any +U-Boot code while loading (or uncompressing) the image of your +application. + +For example, you won't get the console stuff running in the Linux +kernel because the kernel overwrites U-Boot before running. Only +some parameters like the framebuffer descriptors are passed to the +kernel in the high memory area to let the applications (the kernel) +use the framebuffers initialized by U-Boot. + +SUPPORTED DRIVERS +----------------- + +Working drivers: + + serial (architecture dependent serial stuff) + video (mpc8xx video controller) + +Work in progress: + + wl_kbd (Wireless 4PPM keyboard) + +Waiting for volounteers: + + lcd (mpc8xx lcd controller; to ) + +TESTED CONFIGURATIONS +--------------------- + +The driver has been tested with the following configurations (see +CREDITS for other contact informations): + +- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it +- GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it diff --git a/doc/README.db64360 b/doc/README.db64360 new file mode 100644 index 0000000..ebac4ce --- /dev/null +++ b/doc/README.db64360 @@ -0,0 +1,105 @@ +This file contains status information for the port of the U-Boot to the Marvell Development Board DB64360. + +Author: Ronen Shitrit + +This U-Boot version is based on the work of Brian Waite and his team from Sky Computers, THANKS A LOT. + +Supported CPU Types : ++++++++++++++++++++++ + IBM750FX (ver 2.3) + MPC7455 (ver 2.1) + +Supported CPU Cache Library: +++++++++++++++++++++++++++++ + L1 and L2 only. + +CPU Control: +++++++++++++ + Marvell optimized CPU control settings: + Big Endian + Enable CPU pipeline + Data and address parity checking + AACK# assert after 2 cycles + +U-Boot I/O Interface Support: ++++++++++++++++++++++++++++++ +- Serial Interface (UART) + This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module. +- Network Interface + This LSP supports the following network devices: + o MV64360 Gigabit Ethernet Controller device + o Intel 82559 PCI NIC device +- PCI Interface + This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units: + o Local PCI configuration header control. + o External PCI configuration header control (for other agents on the bus). + o PCI configuration application. Scans and configures the PCI agents on the bus. + o PCI Internal Arbiter activation and configuration. + +Memory Interface Support: ++++++++++++++++++++++++++ +- DDR + o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs). + o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma. + +- Devices + o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM. + o JFFS2 + JFFS2 is a crash/power down safe file system for disk-less embedded devices. + This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it. + +Unsupported Features: ++++++++++++++++++++++ + Messaging unit - No support for MV64360 Messaging unit. + Watchdog Timer - No support for MV64360 Watchdog unit. + L3 cache - No support for L3 cache on MPC7455 + Dual PCU - No support for Dual CPU + PCI-X was never tested + IDMA driver - No support for MV64360 IDMA unit. + +BSP Special Considerations: ++++++++++++++++++++++++++++ +- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots. +- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical. + +Test Cases: +########### +UART: ++++++ +Check that the UART baud rate is configured to 57600 and 115200, and check: + Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom. + Load S-Record file over the UART using Windows HyperTerminal. + +Network: +++++++++ +Use TFTP application to load a debugged executable and execute it. +Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC. + +Memory: ++++++++ +Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters: +o 128MB DIMM consist of 16 x 64Mbit devices +o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz. +o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz. +o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz. +o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz. +o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz. +o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered + +For each chip select device perform data access to verify its accessibility. + +Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage. +Load the U-Boot and: +use the ls command to check correct scan of the JFFS2 on the large flash. +Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage. + +PCI: +++++ +1)Insert different PCI cards: +Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10 +on different slots (0-3) of the PCI and check: +o Correct detection of the PCI devices. +o Correct address mapping of the PCI devices. +2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot. + +Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal) diff --git a/doc/README.db64460 b/doc/README.db64460 new file mode 100644 index 0000000..c6e01fe --- /dev/null +++ b/doc/README.db64460 @@ -0,0 +1,105 @@ +This file contains status information for the port of the U-Boot to the Marvell Development Board DB64460. + +Author: Ronen Shitrit + + +Supported CPU Types : ++++++++++++++++++++++ +IBM750Gx Rev 1.0 +MPC7457 Rev 1.1 + +Supported CPU Cache Library: +++++++++++++++++++++++++++++ + L1 and L2 only. + +CPU Control: +++++++++++++ + Marvell optimized CPU control settings: + Big Endian + Enable CPU pipeline + Data and address parity checking + AACK# assert after 2 cycles + +U-Boot I/O Interface Support: ++++++++++++++++++++++++++++++ +- Serial Interface (UART) + This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module. +- Network Interface + This LSP supports the following network devices: + o MV64360 Gigabit Ethernet Controller device + o Intel 82559 PCI NIC device +- PCI Interface + This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units: + o Local PCI configuration header control. + o External PCI configuration header control (for other agents on the bus). + o PCI configuration application. Scans and configures the PCI agents on the bus. + o PCI Internal Arbiter activation and configuration. + +Memory Interface Support: ++++++++++++++++++++++++++ +- DDR + o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs). + o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma. + +- Devices + o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM. + o JFFS2 + JFFS2 is a crash/power down safe file system for disk-less embedded devices. + This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it. + +Unsupported Features: ++++++++++++++++++++++ + Messaging unit - No support for MV64360 Messaging unit. + Watchdog Timer - No support for MV64360 Watchdog unit. + L3 cache - No support for L3 cache on MPC7455 + Dual PCU - No support for Dual CPU + PCI-X was never tested + IDMA driver - No support for MV64360 IDMA unit. + XOR Engine - No support for MV64460 XOR Engine + +BSP Special Considerations: ++++++++++++++++++++++++++++ +- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots. +- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical. + +Test Cases: +########### +UART: ++++++ +Check that the UART baud rate is configured to 57600 and 115200, and check: + Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom. + Load S-Record file over the UART using Windows HyperTerminal. + +Network: +++++++++ +Use TFTP application to load a debugged executable and execute it. +Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC. + +Memory: ++++++++ +Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters: +o 128MB DIMM consist of 16 x 64Mbit devices +o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz. +o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz. +o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz. +o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz. +o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz. +o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered + +For each chip select device perform data access to verify its accessibility. + +Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage. +Load the U-Boot and: +use the ls command to check correct scan of the JFFS2 on the large flash. +Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage. + +PCI: +++++ +1)Insert different PCI cards: +Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10 +on different slots (0-3) of the PCI and check: +o Correct detection of the PCI devices. +o Correct address mapping of the PCI devices. +2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot. + +Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal) diff --git a/doc/README.dk1c20 b/doc/README.dk1c20 new file mode 100644 index 0000000..3c0e41b --- /dev/null +++ b/doc/README.dk1c20 @@ -0,0 +1,153 @@ + + Nios Development Kit + Cyclone Editions + + Last Update: January 2, 2004 +==================================================================== + +This file contains information regarding U-Boot and the Altera +Nios Development Kit, Cyclone Edition (DK-1C20). For general Nios +information see doc/README.nios. + +For those interested in contributing ... see HELP WANTED section +in doc/README.nios. + +Contents: + + 1. Files + 2. Memory Organization + 3. Examples + 4. Programming U-Boot into FLASH with GERMS + 5. Active Serial Memory Interface (ASMI) Support + +==================================================================== + +1. Files +========= + board/altera/dk1c20/* + include/configs/DK1C20.h + +2. Memory Organization +======================= + + -The heap is placed below the monitor (U-Boot code). + -Global data is placed below the heap. + -The stack is placed below global data (&grows down). + +3. Examples +============ + +The hello_world example works fine. The default load address +is 0x0100_0000 (the start of SDRAM). + + +4. Programming U-Boot into FLASH with GERMS +============================================ +The current version of the DK-1C20 port with the default +configuration settings occupies about 81 KBytes of flash. +A minimal configuration occupies less than 60 KByte (asmi +and network support disabled). + +To program U-Boot into the DK-1C20 flash using GERMS do the +following: + +1. From the command line, download U-Boot using the nios-run: + + $ nios-run -r u-boot.srec + +This takes about 45 seconds (GERMS is not very speedy here). +After u-boot is downloaded it will be executed. You should +see the following: + + U-Boot 1.0.0-pre (Oct 4 2003 - 07:39:24) + + CPU: Nios-32 Rev. 3.3 (0x3038) + Reg file size: 256 LO_LIMIT/HI_LIMIT: 2/14 + Board: Altera Nios 1C20 Development Kit + In: serial + Out: serial + Err: serial + ==> + + +2. Quit nios-run and start your terminal application (e.g. start +Hyperterminal or minicom). + +3. Download the u-boot code to RAM. When using Hyperterminal, do the +following: + + a. From the u-boot command prompt start a binary download to SRAM: + + ==> loadb 800000 + + b. Download u-boot.bin using kermit. + +4. From the U-Boot command prompt, erase flash 0x40000 to 0x5ffff: + + ==> erase 1:4-5 + +5. Copy the binary image from SRAM to flash: + + ==> cp.b 800000 40000 10000 + +U-Boot will now automatically start when the board is powered on or +reset using the Standard-32 configuration. To start U-Boot with the +Safe-32 configuration, enter the following GERMS command: + + + g 40000 + +5. Active Serial Memory Interface (ASMI) Support +================================================ +ASMI is fully supported in U-Boot. Please note that ASMI is supported +only on Cyclone devices. Do not expect ASMI to work with Stratix or +APEX devices. + + ************* IMPORTANT ************* + =================================================== + IN ORDER FOR THE NIOS ASMI TO OPERATE PROPERLY, THE + CYCLONE DEVICE MUST BE CONFIGURED USING JTAG OR ASMI. + +There are two techniques you can use to bootstrap the ASMI. The +first is to use the program_epcs utility that is part of Altera's SDK. +But I've found program_epcs to be slow and cumbersome at best. + +An undocumented alternative is to use the Quartus device programing +interface: + + 1. Select "Active Serial" mode. + + 2. Choose the xxx.pof file. For example, for the standard_32 + configuration use the "standard_32.pof" file. + + 3. Attach your ByteBlaster to J28. Make sure you have the + cable attached properly -- the orientation of J28 is + different than J24 (the JTAG header). On J28, pin 1 is on + the bottom row, left-most pin. + + 4. Press and hold the "Power-On Reset" switch (SW10). You will + see the green "Loading" and red "Error" LEDs (LED3 and LED4) + in the on state. + + 5. While holding down the "Power-On Reset" switch, start the + programming sequence. This only takes about 10 seconds. + + 6. After programming is complete, release the "Power-On Reset" + switch. The Cyclone device should now load its configuration + from the EPCS4 (U59). The green "User" LED (LED 1) should be + blinking if the device was successfully loaded via ASMI. + + 7. Remove the ByteBlaster cable. The cable must be removed to + allow the Nios ASMI access to the EPCS4 device. + +After you have successfully programmed a configuration into the +EPCS4, the ASMI will be used to load the Cyclone configuration +unless the "Force Safe" switch (SW9) is pressed. + +NOTE: To maximize the amount of space available for program use, +you can enable configuration compression in Quartus. With compression +enabled, the size of the standard_32 configuration data is +approximately 192 KBytes. + +To use the U-Boot ASMI commands, try typing "help asmi" at the +command prompt. The command "asmi info" will show the current +status of the ASMI. diff --git a/doc/README.dk1c20_std32 b/doc/README.dk1c20_std32 new file mode 100644 index 0000000..521fab7 --- /dev/null +++ b/doc/README.dk1c20_std32 @@ -0,0 +1,366 @@ + +TODO: specify IDE i/f + specify ASMI i/f + specify OCI + + +=============================================================================== + C P U , M E M O R Y , I N / O U T C O M P O N E N T S +=============================================================================== +see also [1]-[6] + +CPU: "standard_32" + 32 bit NIOS for 50 MHz + 256 Byte for register file (15 levels) + 4 KByte instruction cache (2 bytes in each cache line) + 4 KByte data cache (4 bytes in each cache line) + 2 KByte On Chip ROM with GERMS boot monitor + no On Chip RAM + MSTEP multiplier + no Debug Core + On Chip Instrumentation (OCI) enabled + + U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 + CFG_NIOS_CPU_ICACHE = 4096 + CFG_NIOS_CPU_DCACHE = 4096 + CFG_NIOS_CPU_REG_NUMS = 256 + CFG_NIOS_CPU_MUL = 0 + CFG_NIOS_CPU_MSTEP = 1 + CFG_NIOS_CPU_DBG_CORE = 0 + +OCI: (TODO) + +IRQ: Nr. | used by + ------+-------------------------------------------------------- + 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 + 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25 + 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30 + 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35 + 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40 + 45 | ASMI | CFG_NIOS_CPU_ASMI0_IRQ = 45 + 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50 + +MEMORY: 8 MByte Flash + 1 MByte SRAM + 16 MByte SDRAM + +ASMI: (TODO) <-- ASMI part is 4M bits + +Timer: TIMER0: high priority programmable timer (IRQ16) + TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50) + + U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1 + CFG_NIOS_CPU_USER_TIMER = 0 + +PIO: Nr. | description + ------+-------------------------------------------------------- + PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40) + PIO1 | LCD: 11 in/outputs for ASCII LCD + PIO2 | LED: 8 outputs for user LEDs + PIO3 | SEVENSEG: 16 outputs for user seven segment display + PIO4 | RECONF: 1 in/output for . . . . . . . . . . . . + PIO5 | CFPRESENT: 1 input for CF present event (IRQ35) + PIO6 | CFPOWER: 1 output to controll CF power supply + PIO7 | CFATASEL: 1 output to controll CF ATA card select + + U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0 + CFG_NIOS_CPU_LCD_PIO = 1 + CFG_NIOS_CPU_LED_PIO = 2 + CFG_NIOS_CPU_SEVENSEG_PIO = 3 + CFG_NIOS_CPU_RECONF_PIO = 4 + CFG_NIOS_CPU_CFPRESENT_PIO = 5 + CFG_NIOS_CPU_CFPOWER_PIO = 6 + CFG_NIOS_CPU_CFATASEL_PIO = 7 + +UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, + without handshake RTS/CTS (IRQ25) + +LAN: SMsC LAN91C111 with: + - offset 0x300 (LAN91C111_REGISTERS_OFFSET) + - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH) + +IDE: (TODO) + + +=============================================================================== + M E M O R Y M A P +=============================================================================== + +- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - - + + 0x02000000 ---32-----------16|15------------0- + | : | \ + | : | | + SDRAM | : | > CFG_NIOS_CPU_SDRAM_SIZE + | : | | = 0x01000000 + | : | / + 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + | | + : gap : + : : + +- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x________ ---32-----------16|15------------0- + | | | \ + : (real size : : | + ASMI i/f : and content : : > 0x________ + [5] : unknown) : : | + | | | / + 0x00920b00 ---32-----------16|15------------0- CFG_NIOS_CPU_ASMI0 + | | + : gap : + | | + 0x00920a80 ---32-----------16|15------------0- + | | | \ + : (real size : : | + IDE i/f : and content : : > 0x00000080 + [6] : unknown) : : | + | | | / + 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER1 | (unused) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | (unused) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (1 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO7 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO6 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO5 | interruptmask (1 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO4 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (1 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (rw) | / + 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO3 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (16 bit) (wo) | / + 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO2 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (8 bit) (wo) | / + 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO1 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (11 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (11 bit) (rw) | / + 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + | edgecapture (4 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO0 | interruptmask (4 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (4 bit) (ro) | / + 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | snaph (16 bit) (rw) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER0 | snapl (16 bit) (rw) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | periodh (16 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | periodl (16 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (4 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + | | \ + : gap : > (space for UART1) + | | / + 0x00920920 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART0 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + +- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - - + + 0x00920900 ----------------------------------- + | | \ + : (real size : | + OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE + : unknown) : | = 0x00000100 + | | / + 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE + +- - - - - - - - - - - on chip memory - - - - - - - - - - - + + 0x00920800 ---32-----------16|15------------0- + | : | \ + | : | | + GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + | : | | = 0x00000800 + | : | / + 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT + 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + +- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - + + 0x00920000 ---32-----------16|15------------0- + | gap | \ + 0x00910310 --+-------------------------------| | + | | | + | register bank (size = 0x10) | | + | +--------.---.---.--- | | + | | bank 0 \ 1 \ 2 \ 3 \ | | + | |---------------------------+ | | + LAN91C111 | | BANK | RESERVED | | | + | |- - - - - - -|- - - - - - -| | > na_lan91c111_size + | | RPCR | MIR | | | = 0x00010000 + | |- - - - - - -|- - - - - - -| | | + | | COUNTER | RCR | | | + | |- - - - - - -|- - - - - - -| | | + | | EPH STATUS | TCR | | | + | +---------------------------+ | | + 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| | + | gap | / + 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + | | + : gap : + : : + +- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00900000 ---32-----------16|15------------0- + 0x00900000 --+32-----------16|15------------0+ + | : | \ \ + | : | | | + | : | | > CFG_NIOS_CPU_VEC_SIZE + | : | | | = 0x00000100 + | : | | / + 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE + 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CFG_NIOS_CPU_STACK + | : | | \ + | : | | | + | : | | > stack area + | : | | | + | : | | V + | : | | + SRAM | : | > CFG_NIOS_CPU_SRAM_SIZE + | : | | = 0x00100000 + | : | / + 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x00800000 ---8-------------4|3-------------0- + | sector 127 | \ + + 0x7f0000 |- - - - - - - - - - - - - - - -| | + | : | | + Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + | sector 1 : | | = 0x00800000 + + 0x010000 |- - - - - - - - - - - - - - - -| | + | sector 0 (size = 0x10000) | / + 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + + +=============================================================================== + F L A S H M E M O R Y A L L O C A T I O N +=============================================================================== + + 0x00800000 ---8-------------4|3-------------0- + | : | \ + SAFE | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00700000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + USER | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00600000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + WEB pages | : | > 2 MByte + | : | | (provisory usable) + | : | / + 0x00400000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + | : | | + | : | > 4 MByte free for use + | : | | + 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start() + | : | / + 0x00000000 |- - - - - - - -:- - - - - - - -+- - u-boot environment + 0x00000000 ---8-------------4|3-------------0- + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/manual/mnl_nios_board_cyclone_1c20.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf + http://www.altera.com/literature/wp/wp_epcs_cyc.pdf +[6] http://www.opencores.org/projects/ata/ + http://www.t13.org/index.html + + +=============================================================================== +Stephan Linz diff --git a/doc/README.dk1s10 b/doc/README.dk1s10 new file mode 100644 index 0000000..622bef5 --- /dev/null +++ b/doc/README.dk1s10 @@ -0,0 +1,131 @@ + + Nios Development Kit + Startix Editions + + Last Update: January 28, 2004 +==================================================================== + +This file contains information regarding U-Boot and the Altera +Nios Development Kit, Startix Edition (DK-1S10). For general Nios +information see doc/README.nios. + +Most stuff of this file was borrowed and based on README.dk1c20, +the DK-1C20 related information file. + +For those interested in contributing ... see HELP WANTED section +in doc/README.nios. + +Contents: + + 1. Files + 2. Memory Organization + 3. CPU Variations + 4. Examples + 5. Programming U-Boot into FLASH with GERMS + +==================================================================== + +1. Files +========= + board/altera/dk1s10/* + include/configs/DK1S10.h + +2. Memory Organization +======================= + + -The heap is placed below the monitor (U-Boot code). + -Global data is placed below the heap. + -The stack is placed below global data (&grows down). + +3. CPU Variations +================= + +There are more than one NIOS CPU variation for the DK-1S10. U-Boot +supports the following CPU configurations: + + - Altera Standard 32 (make DK1S10_standard_32_config) + - Microtronix LDK 2.0 (make DK1S10_mtx_ldk_20_config) + +4. Examples +============ + +The hello_world example was never tested on DK-1S10. Neverthelse +it should work as far as possible, because the DK-1S10 port is +more than ninetieth percents equal to the DK-1C20 port and at +this platform the hello_world example was already tested +successfully (see README.dk1c20). + + +5. Programming U-Boot into FLASH with GERMS +============================================ +The current version of the DK-1S10 port with the default +configuration settings occupies about 78 KBytes of flash. +A minimal configuration occupies less than 60 KByte +(network support disabled). + +To program U-Boot into the DK-1S10 flash using GERMS do the +following: + +1. From the command line, download U-Boot using the nios-run: + + $ nios-run -r u-boot.srec + +This takes about 45 seconds (GERMS is not very speedy here). +After u-boot is downloaded it will be executed. You should +see the following: + + U-Boot 1.0.2 (Jan 28 2004 - 19:02:30) + + CPU: Nios-32 Rev. 3.3 (0x3038) + Reg file size: 256 LO_LIMIT/HI_LIMIT: 2/14 + Board: Altera Nios 1S10 Development Kit + In: serial + Out: serial + Err: serial + DK1S10 > + + +2. Quit nios-run and start your terminal application (e.g. start + Hyperterminal or minicom). + +3. Download the u-boot code to RAM. When using Hyperterminal, do the + following: + + a. From the u-boot command prompt start a binary download to + SRAM / SDRAM: + + at the Altera Standard 32 to SRAM: + + ==> loadb 800000 + + at the Microtronix LDK 2.0 to SDRAM: + + ==> loadb 1010000 + + b. Download u-boot.bin using kermit. + +4. From the U-Boot command prompt, erase flash: + + at the Altera Standard 32 from 0x40000 to 0x5ffff: + + ==> erase 1:4-5 + + at the Microtronix LDK 2.0 from 0x8000000 to 0x81ffff: + + ==> erase 1:0-1 + +5. Copy the binary image from SRAM / SDRAM to flash: + + at the Altera Standard 32 to SRAM: + + ==> cp.b 800000 40000 ${filesize} + + at the Microtronix LDK 2.0 to SDRAM: + + ==> cp.b 1010000 8000000 ${filesize} + +U-Boot will now automatically start when the board is powered on or +reset using the Standard-32 configuration. To start U-Boot with the +Safe-32 configuration, enter the following GERMS command: + + + g 40000 diff --git a/doc/README.dk1s10_mldk20 b/doc/README.dk1s10_mldk20 new file mode 100644 index 0000000..fcf8170 --- /dev/null +++ b/doc/README.dk1s10_mldk20 @@ -0,0 +1,286 @@ + +TODO: specify IDE i/f + + +=============================================================================== + C P U , M E M O R Y , I N / O U T C O M P O N E N T S +=============================================================================== +see also [1]-[5] + +CPU: "LDK2" + 32 bit NIOS for 75 MHz + 512 Byte for register file (30 levels) + with out instruction cache + with out data cache + 2 KByte On Chip ROM with GERMS boot monitor + with out On Chip RAM + MSTEP multiplier + no Debug Core + no On Chip Instrumentation (OCI) + + U-Boot CFG: CFG_NIOS_CPU_CLK = 75000000 + CFG_NIOS_CPU_ICACHE = (not present) + CFG_NIOS_CPU_DCACHE = (not present) + CFG_NIOS_CPU_REG_NUMS = 512 + CFG_NIOS_CPU_MUL = 0 + CFG_NIOS_CPU_MSTEP = 1 + CFG_NIOS_CPU_DBG_CORE = 0 + +IRQ: Nr. | used by + ------+-------------------------------------------------------- + 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 + 17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17 + 18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18 + 20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 20 + 25 | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 25 + +MEMORY: 8 MByte Flash + 16 MByte SDRAM + +Timer: TIMER0: high priority programmable timer (IRQ16) + + U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 + CFG_NIOS_CPU_USER_TIMER = (not present) + +PIO: Nr. | description + ------+-------------------------------------------------------- + PIO0 | CFPOWER: 1 output to controll CF power supply + PIO1 | BUTTON: 4 inputs for user push buttons (no IRQ) + ------+-------------------------------------------------------- + not | LCD: 11 in/outputs for ASCII LCD + pres.| LED: 8 outputs for user LEDs + | SEVENSEG: 16 outputs for user seven segment display + | RECONF: 1 in/output for . . . . . . . . . . . . + | CFPRESENT: 1 input for CF present event (IRQ35) + | CFATASEL: 1 output to controll CF ATA card select + + U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 1 + CFG_NIOS_CPU_LCD_PIO = (not present) + CFG_NIOS_CPU_LED_PIO = (not present) + CFG_NIOS_CPU_SEVENSEG_PIO = (not present) + CFG_NIOS_CPU_RECONF_PIO = (not present) + CFG_NIOS_CPU_CFPRESENT_PIO = (not present) + CFG_NIOS_CPU_CFPOWER_PIO = 0 + CFG_NIOS_CPU_CFATASEL_PIO = (not present) + +UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, + without handshake RTS/CTS (IRQ17) + UART1: fixed baudrate of 115200, fixed protocol 8N1, + without handshake RTS/CTS (IRQ18) + +LAN: SMsC LAN91C111 with: + - offset 0x300 (LAN91C111_REGISTERS_OFFSET) + - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH) + +IDE: (TODO) + + +=============================================================================== + M E M O R Y M A P +=============================================================================== + +- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - - + + 0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK + 0x02000000 --+32-----------16|15------------0+ + | . | \ \ + | . | | | + | . | | > stack area + | . | | | + | . | | V + | . | | + | . | | + SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE + | . | | = 0x01000000 + | . | | + 0x01000100 |- - - - - - - - - - - - - - - -+-|- + | . | | \ + | . | | | + | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | | = 0x00000100 + | | / / + 0x01000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE + 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + | sector 127 | \ + + 0x7f0000 |- - - - - - - - - - - - - - - -| | + | : | | + Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + | sector 1 : | | = 0x00800000 + + 0x010000 |- - - - - - - - - - - - - - - -| | + | sector 0 (size = 0x10000) | / + 0x00800000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + | | + : gap : + : : + +- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00020000 ---32-----------16|15------------0- + | gap | \ + 0x00010310 --+-------------------------------| | + | | | + | register bank (size = 0x10) | | + | +--------.---.---.--- | | + | | bank 0 \ 1 \ 2 \ 3 \ | | + | |---------------------------+ | | + LAN91C111 | | BANK | RESERVED | | | + | |- - - - - - -|- - - - - - -| | > na_enet_size + | | RPCR | MIR | | | = 0x00010000 + | |- - - - - - -|- - - - - - -| | | + | | COUNTER | RCR | | | + | |- - - - - - -|- - - - - - -| | | + | | EPH STATUS | TCR | | | + | +---------------------------+ | | + 0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| | + | gap | / + 0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + | | + : gap : + : : + +- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00000980 ---32-----------16|15------------0- + | | | \ + : (real size : : | + IDE i/f : and content : : > 0x00000080 + [5] : unknown) : : | + | | | / + 0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + | | \ + : gap : > (space for PIO4..7) + | | / + 0x000008c0 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART1 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 + | | \ + : gap : > (space for PIO2..3) + | | / + 0x00000880 ---32-----------16|15------------0- + | edgecapture (4 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO1 | interruptmask (4 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (4 bit) (ro) | / + 0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO0 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | snaph (16 bit) (rw) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER0 | snapl (16 bit) (rw) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | periodh (16 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | periodl (16 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (4 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + | | \ + : gap : > (space for UART2) + | | / + 0x00000820 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART0 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + +- - - - - - - - - - - on chip memory 1 - - - - - - - - - - - + + 0x00000800 ---32-----------16|15------------0- + | : | \ + | : | | + GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + | : | | = 0x00000800 + | : | / + 0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT + 0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + +=============================================================================== + F L A S H M E M O R Y A L L O C A T I O N +=============================================================================== + + 0x01000000 ---8-------------4|3-------------0- + | : | \ + SAFE | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00f00000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + USER | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00e00000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + WEB pages | : | > 2 MByte + | : | | (provisory usable) + | : | / + 0x00c00000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + | : | | + | : | > 4 MByte free for use + | : | | + 0x00840000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment + | : | / + 0x00800000 |- - - - - - - -:- - - - - - - -+- - u-boot _start() + 0x00800000 ---8-------------4|3-------------0- + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.opencores.org/projects/ata/ + http://www.t13.org/index.html + + +=============================================================================== +Stephan Linz diff --git a/doc/README.dk1s10_std32 b/doc/README.dk1s10_std32 new file mode 100644 index 0000000..d649eb3 --- /dev/null +++ b/doc/README.dk1s10_std32 @@ -0,0 +1,354 @@ + +TODO: specify IDE i/f + specify OCI + + +=============================================================================== + C P U , M E M O R Y , I N / O U T C O M P O N E N T S +=============================================================================== +see also [1]-[5] + +CPU: "standard_32" + 32 bit NIOS for 50 MHz + 256 Byte for register file (15 levels) + 4 KByte instruction cache (4 bytes in each cache line) + 4 KByte data cache (4 bytes in each cache line) + 2 KByte On Chip ROM with GERMS boot monitor + 64 KByte On Chip RAM + MSTEP multiplier + no Debug Core + On Chip Instrumentation (OCI) enabled + + U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 + CFG_NIOS_CPU_ICACHE = 4096 + CFG_NIOS_CPU_DCACHE = 4096 + CFG_NIOS_CPU_REG_NUMS = 256 + CFG_NIOS_CPU_MUL = 0 + CFG_NIOS_CPU_MSTEP = 1 + CFG_NIOS_CPU_DBG_CORE = 0 + +OCI: (TODO) + +IRQ: Nr. | used by + ------+-------------------------------------------------------- + 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 + 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25 + 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30 + 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35 + 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40 + 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50 + +MEMORY: 8 MByte Flash + 1 MByte SRAM + 16 MByte SDRAM + +Timer: TIMER0: high priority programmable timer (IRQ16) + TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50) + + U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1 + CFG_NIOS_CPU_USER_TIMER = 0 + +PIO: Nr. | description + ------+-------------------------------------------------------- + PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40) + PIO1 | LCD: 11 in/outputs for ASCII LCD + PIO2 | LED: 8 outputs for user LEDs + PIO3 | SEVENSEG: 16 outputs for user seven segment display + PIO4 | RECONF: 1 in/output for . . . . . . . . . . . . + PIO5 | CFPRESENT: 1 input for CF present event (IRQ35) + PIO6 | CFPOWER: 1 output to controll CF power supply + PIO7 | CFATASEL: 1 output to controll CF ATA card select + + U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0 + CFG_NIOS_CPU_LCD_PIO = 1 + CFG_NIOS_CPU_LED_PIO = 2 + CFG_NIOS_CPU_SEVENSEG_PIO = 3 + CFG_NIOS_CPU_RECONF_PIO = 4 + CFG_NIOS_CPU_CFPRESENT_PIO = 5 + CFG_NIOS_CPU_CFPOWER_PIO = 6 + CFG_NIOS_CPU_CFATASEL_PIO = 7 + +UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, + without handshake RTS/CTS (IRQ25) + +LAN: SMsC LAN91C111 with: + - offset 0x300 (LAN91C111_REGISTERS_OFFSET) + - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH) + +IDE: (TODO) + + +=============================================================================== + M E M O R Y M A P +=============================================================================== + +- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - - + + 0x02000000 ---32-----------16|15------------0- + | : | \ + | : | | + SDRAM | : | > CFG_NIOS_CPU_SDRAM_SIZE + | : | | = 0x01000000 + | : | / + 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + | | + : gap : + : : + +- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00920a80 ---32-----------16|15------------0- + | | | \ + : (real size : : | + IDE i/f : and content : : > 0x00000080 + [5] : unknown) : : | + | | | / + 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER1 | (unused) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | (unused) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (1 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO7 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO6 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO5 | interruptmask (1 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO4 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (1 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (rw) | / + 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO3 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (16 bit) (wo) | / + 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO2 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (8 bit) (wo) | / + 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO1 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (11 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (11 bit) (rw) | / + 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + | edgecapture (4 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO0 | interruptmask (4 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (4 bit) (ro) | / + 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | snaph (16 bit) (rw) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER0 | snapl (16 bit) (rw) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | periodh (16 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | periodl (16 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (4 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + | | \ + : gap : > (space for UART1) + | | / + 0x00920920 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART0 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + +- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - - + + 0x00920900 ----------------------------------- + | | \ + : (real size : | + OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE + : unknown) : | = 0x00000100 + | | / + 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE + +- - - - - - - - - - - on chip memory 2 - - - - - - - - - - - + + 0x00920800 ---32-----------16|15------------0- + | : | \ + | : | | + GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + | : | | = 0x00000800 + | : | / + 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT + 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + +- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - + + 0x00920000 ---32-----------16|15------------0- + | gap | \ + 0x00910310 --+-------------------------------| | + | | | + | register bank (size = 0x10) | | + | +--------.---.---.--- | | + | | bank 0 \ 1 \ 2 \ 3 \ | | + | |---------------------------+ | | + LAN91C111 | | BANK | RESERVED | | | + | |- - - - - - -|- - - - - - -| | > na_lan91c111_size + | | RPCR | MIR | | | = 0x00010000 + | |- - - - - - -|- - - - - - -| | | + | | COUNTER | RCR | | | + | |- - - - - - -|- - - - - - -| | | + | | EPH STATUS | TCR | | | + | +---------------------------+ | | + 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| | + | gap | / + 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + +- - - - - - - - - - - on chip memory 1 - - - - - - - - - - - + + 0x00910000 ---32-----------16|15------------0- + | : | \ + | : | | + onchip RAM | : | > CFG_NIOS_CPU_RAM_SIZE + | : | | = 0x00010000 + | : | / + 0x00900000 ---32-----------16|15------------0- CFG_NIOS_CPU_RAM_BASE + +- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - - + + 0x00900000 ---32-----------16|15------------0- + 0x00900000 --+32-----------16|15------------0+ + | . | \ \ + | . | | | + | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | | = 0x00000100 + | . | | / + 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE + 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK + | . | | \ + | . | | | + | . | | > stack area + | . | | | + | . | | V + | . | | + SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE + | . | | = 0x00100000 + | | / + 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x00800000 ---8-------------4|3-------------0- + | sector 127 | \ + + 0x7f0000 |- - - - - - - - - - - - - - - -| | + | : | | + Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + | sector 1 : | | = 0x00800000 + + 0x010000 |- - - - - - - - - - - - - - - -| | + | sector 0 (size = 0x10000) | / + 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + + +=============================================================================== + F L A S H M E M O R Y A L L O C A T I O N +=============================================================================== + + 0x00800000 ---8-------------4|3-------------0- + | : | \ + SAFE | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00700000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + USER | : | > 1 MByte + FPGA conf. | : | / (NOT usable by software) + 0x00600000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + WEB pages | : | > 2 MByte + | : | | (provisory usable) + | : | / + 0x00400000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + | : | | + | : | > 4 MByte free for use + | : | | + 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start() + | : | / + 0x00000000 |- - - - - - - -:- - - - - - - -+- - u-boot environment + 0x00000000 ---8-------------4|3-------------0- + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.opencores.org/projects/ata/ + http://www.t13.org/index.html + + +=============================================================================== +Stephan Linz diff --git a/doc/README.dk1s40_std32 b/doc/README.dk1s40_std32 new file mode 100644 index 0000000..08c8244 --- /dev/null +++ b/doc/README.dk1s40_std32 @@ -0,0 +1,355 @@ + +TODO: specify IDE i/f + specify OCI + + +=============================================================================== + C P U , M E M O R Y , I N / O U T C O M P O N E N T S +=============================================================================== +see also [1]-[5] + +CPU: "standard_32" + 32 bit NIOS for 50 MHz + 256 Byte for register file (15 levels) + 4 KByte instruction cache (4 bytes in each cache line) + 4 KByte data cache (4 bytes in each cache line) + 2 KByte On Chip ROM with GERMS boot monitor + 64 KByte On Chip RAM + MSTEP multiplier + no Debug Core + On Chip Instrumentation (OCI) enabled + + U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 + CFG_NIOS_CPU_ICACHE = 4096 + CFG_NIOS_CPU_DCACHE = 4096 + CFG_NIOS_CPU_REG_NUMS = 256 + CFG_NIOS_CPU_MUL = 0 + CFG_NIOS_CPU_MSTEP = 1 + CFG_NIOS_CPU_DBG_CORE = 0 + +OCI: (TODO) + +IRQ: Nr. | used by + ------+-------------------------------------------------------- + 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 + 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25 + 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30 + 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35 + 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40 + 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50 + +MEMORY: 8 MByte Flash + 1 MByte SRAM + 16 MByte SDRAM + +Timer: TIMER0: high priority programmable timer (IRQ16) + TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50) + + U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1 + CFG_NIOS_CPU_USER_TIMER = 0 + +PIO: Nr. | description + ------+-------------------------------------------------------- + PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40) + PIO1 | LCD: 11 in/outputs for ASCII LCD + PIO2 | LED: 8 outputs for user LEDs + PIO3 | SEVENSEG: 16 outputs for user seven segment display + PIO4 | RECONF: 1 in/output for . . . . . . . . . . . . + PIO5 | CFPRESENT: 1 input for CF present event (IRQ35) + PIO6 | CFPOWER: 1 output to controll CF power supply + PIO7 | CFATASEL: 1 output to controll CF ATA card select + + U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0 + CFG_NIOS_CPU_LCD_PIO = 1 + CFG_NIOS_CPU_LED_PIO = 2 + CFG_NIOS_CPU_SEVENSEG_PIO = 3 + CFG_NIOS_CPU_RECONF_PIO = 4 + CFG_NIOS_CPU_CFPRESENT_PIO = 5 + CFG_NIOS_CPU_CFPOWER_PIO = 6 + CFG_NIOS_CPU_CFATASEL_PIO = 7 + +UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, + without handshake RTS/CTS (IRQ25) + +LAN: SMsC LAN91C111 with: + - offset 0x300 (LAN91C111_REGISTERS_OFFSET) + - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH) + +IDE: (TODO) + + +=============================================================================== + M E M O R Y M A P +=============================================================================== + +- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - - + + 0x02000000 ---32-----------16|15------------0- + | : | \ + | : | | + SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE + | : | | = 0x01000000 + | : | / + 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + | | + : gap : + : : + +- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00920a80 ---32-----------16|15------------0- + | | | \ + : (real size : : | + IDE i/f : and content : : > 0x00000080 + [5] : unknown) : : | + | | | / + 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER1 | (unused) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | (unused) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (1 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO7 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO6 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (wo) | / + 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6 + | edgecapture (1 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO5 | interruptmask (1 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (ro) | / + 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO4 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (1 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (1 bit) (rw) | / + 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO3 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (16 bit) (wo) | / + 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO2 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (8 bit) (wo) | / + 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO1 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (11 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (11 bit) (rw) | / + 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + | edgecapture (4 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO0 | interruptmask (4 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (4 bit) (ro) | / + 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | snaph (16 bit) (rw) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER0 | snapl (16 bit) (rw) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | periodh (16 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | periodl (16 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (4 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + | | \ + : gap : > (space for UART1) + | | / + 0x00920920 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART0 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + +- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - - + + 0x00920900 ----------------------------------- + | | \ + : (real size : | + OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE + : unknown) : | = 0x00000100 + | | / + 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE + +- - - - - - - - - - - on chip memory 2 - - - - - - - - - - - + + 0x00920800 ---32-----------16|15------------0- + | : | \ + | : | | + GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + | : | | = 0x00000800 + | : | / + 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT + 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + +- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - + + 0x00920000 ---32-----------16|15------------0- + | gap | \ + 0x00910310 --+-------------------------------| | + | | | + | register bank (size = 0x10) | | + | +--------.---.---.--- | | + | | bank 0 \ 1 \ 2 \ 3 \ | | + | |---------------------------+ | | + LAN91C111 | | BANK | RESERVED | | | + | |- - - - - - -|- - - - - - -| | > na_lan91c111_size + | | RPCR | MIR | | | = 0x00010000 + | |- - - - - - -|- - - - - - -| | | + | | COUNTER | RCR | | | + | |- - - - - - -|- - - - - - -| | | + | | EPH STATUS | TCR | | | + | +---------------------------+ | | + 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| | + | gap | / + 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + +- - - - - - - - - - - on chip memory 1 - - - - - - - - - - - + + 0x00910000 ---32-----------16|15------------0- + | : | \ + | : | | + onchip RAM | : | > CFG_NIOS_CPU_RAM_SIZE + | : | | = 0x00010000 + | : | / + 0x00900000 ---32-----------16|15------------0- CFG_NIOS_CPU_RAM_BASE + +- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - - + + 0x00900000 ---32-----------16|15------------0- + 0x00900000 --+32-----------16|15------------0+ + | . | \ \ + | . | | | + | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | | = 0x00000100 + | . | | / + 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE + 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK + | . | | \ + | . | | | + | . | | > stack area + | . | | | + | . | | V + | . | | + SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE + | . | | = 0x00100000 + | | / + 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x00800000 ---8-------------4|3-------------0- + | sector 127 | \ + + 0x7f0000 |- - - - - - - - - - - - - - - -| | + | : | | + Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + | sector 1 : | | = 0x00800000 + + 0x010000 |- - - - - - - - - - - - - - - -| | + | sector 0 (size = 0x10000) | / + 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + + +=============================================================================== + F L A S H M E M O R Y A L L O C A T I O N +=============================================================================== + + 0x00800000 ---8-------------4|3-------------0- + | : | \ + | : | | + SAFE | : | > 2 MByte + FPGA conf. | : | | (NOT usable by software) + | : | / + 0x00600000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + USER | : | > 2 MByte + FPGA conf. | : | | (NOT usable by software) + | : | / + 0x00400000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + WEB pages | : | > 2 MByte + | : | | (provisory usable) + | : | / + 0x00200000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + | : | > 2 MByte free for use + 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start() + | : | / + 0x00000000 ---8-------------4|3-------------0- + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s40.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.opencores.org/projects/ata/ + http://www.t13.org/index.html + + +=============================================================================== +Stephan Linz diff --git a/doc/README.dk20k200_std32 b/doc/README.dk20k200_std32 new file mode 100644 index 0000000..7b5d4d4 --- /dev/null +++ b/doc/README.dk20k200_std32 @@ -0,0 +1,242 @@ + +=============================================================================== + C P U , M E M O R Y , I N / O U T C O M P O N E N T S +=============================================================================== +see also [1]-[4] + +CPU: "standard_32" + 32 bit NIOS for 33.333 MHz (nasys_clock_freq = 33333000) + 256 Byte for register file (15 levels) + no instruction cache + no data cache + 1 KByte On Chip ROM with GERMS boot monitor + no On Chip RAM + MSTEP multiplier + no Debug Core + no On Chip Instrumentation (OCI) enabled + + U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 + CFG_NIOS_CPU_ICACHE = 0 + CFG_NIOS_CPU_DCACHE = 0 + CFG_NIOS_CPU_REG_NUMS = 256 + CFG_NIOS_CPU_MUL = 0 + CFG_NIOS_CPU_MSTEP = 1 + CFG_NIOS_CPU_DBG_CORE = 0 + +IRQ: Nr. | used by + ------+-------------------------------------------------------- + 25 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 25 + 26 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 26 + 27 | PIO2 | CFG_NIOS_CPU_PIO2_IRQ = 27 + 28 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 28 (debug) + +MEMORY: 1 MByte Flash + 256 KByte SRAM + (SDRAM with standard SODIMM only) + +Timer: TIMER0: high priority programmable timer (IRQ25) + + U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 + +PIO: Nr. | description + ------+-------------------------------------------------------- + PIO0 | SEVENSEG: 16 outputs for user seven segment display + PIO1 | LED: 8 outputs for user LEDs + PIO2 | BUTTON: 4 inputs for user push buttons (IRQ27) + PIO3 | LCD: 11 in/outputs for ASCII LCD + + U-Boot CFG: CFG_NIOS_CPU_SEVENSEG_PIO = 0 + CFG_NIOS_CPU_LED_PIO = 1 + CFG_NIOS_CPU_BUTTON_PIO = 2 + CFG_NIOS_CPU_LCD_PIO = 3 + +UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, + without handshake RTS/CTS (IRQ26) + UART1: fixed baudrate of 115200, fixed protocol 8N1, + without handshake RTS/CTS (IRQ28) + + +=============================================================================== + M E M O R Y M A P +=============================================================================== + +- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - - + + 0x00200000 ---15------------8|7-------------0- + | sector 18 | \ + + 0x0f0000 |- - - - - - - - - - - - - - - -| | + | : | | + Flash |- - - - : - - - -| | + | sector 5 : | | + + 0x020000 |- - - - - - - - -| | + | sector 4 (size = 0x10000) | | + + 0x010000 |- - - - - - - - - - - - - - - -| > CFG_NIOS_CPU_FLASH_SIZE + | sector 3 (size = 0x08000) | | = 0x00100000 + + 0x008000 |- - - - - - - - - - - - - - - -| | + | sector 2 (size = 0x02000) | | + + 0x006000 |- - - - - - - - - - - - - - - -| | + | sector 1 (size = 0x02000) | | + + 0x004000 |- - - - - - - - - - - - - - - -| | + | sector 0 (size = 0x04000) | / + 0x00100000 ---15------------8|7-------------0- CFG_NIOS_CPU_FLASH_BASE + | | + : gap : + | | + 0x00080000 ---32-----------16|15------------0- + 0x00080000 --+32-----------16|15------------0+ + | . | \ \ + | . | | | + | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | | = 0x00000100 + | . | | / + 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE + 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK + | . | | \ + | . | | | + | . | | > stack area + | . | | | + | . | | V + | . | | + SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE + | . | | = 0x00040000 + | | / + 0x00040000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + | | + : gap : + : : + +- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - + + : : + : gap : + | | + 0x00000400 ---32-----------16|15------------0- + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART1 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x000004c0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 + | | + : gap : + | | + 0x00000490 ---32-----------16|15------------0- + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO3 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (11 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (11 bit) (rw) | / + 0x00000480 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + | edgecapture (12 bit) (rw) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO2 | interruptmask (12 bit) (rw) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (12 bit) (ro) | / + 0x00000470 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO1 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | direction (2 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (2 bit) (rw) | / + 0x00000460 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | snaph (16 bit) (rw) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + TIMER0 | snapl (16 bit) (rw) | | + [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 + | periodh (16 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | periodl (16 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | control (4 bit) (rw) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | status (2 bit) (rw) | / + 0x00000440 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + | (unused) | \ + + 0x0c |- - - - - - - - - - - - - - - -| | + PIO0 | (unused) | | + [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 + | (unused) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | data (16 bit) (wo) | / + 0x00000420 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + | (unused) | \ + + 0x1c |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x18 |- - - - - - - - - - - - - - - -| | + | (unused) | | + + 0x14 |- - - - - - - - - - - - - - - -| | + UART0 | (unused) | > 0x00000020 + [2] + 0x10 |- - - - - - - - - - - - - - - -| | + | control (10 bit) (rw) | | + + 0x0c |- - - - - - - - - - - - - - - -| | + | status (10 bit) (rw) | | + + 0x08 |- - - - - - - - - - - - - - - -| | + | txdata (8 bit) (wo) | | + + 0x04 |- - - - - - - - - - - - - - - -| | + | rxdata (8 bit) (ro) | / + 0x00000400 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + +- - - - - - - - - - - on chip memory - - - - - - - - - - - + + 0x00000400 ---32-----------16|15------------0- + | : | \ + | : | | + GERMS | : | > na_boot_monitor_rom_size + | : | | = 0x00000400 + | : | / + 0x00000000 |- - - - - - - - - - - - - - - -+- - nasys_reset_address + 0x00000000 ---32-----------16|15------------0- na_boot_monitor_rom + + +=============================================================================== + F L A S H M E M O R Y A L L O C A T I O N +=============================================================================== + + 0x00200000 ---15------------8|7-------------0- + | : | \ + SAFE | : | > 256 KByte + FPGA conf. | : | / (NOT usable by software) + 0x001c0000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + USER | : | > 256 KByte + FPGA conf. | : | / (NOT usable by software) + 0x00180000 --+- - - - - - - -:- - - - - - - -+- + | : | \ + | : | | + | : | > 512 KByte free for use + 0x00140000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start() + | : | / + 0x00100000 ---15------------8|7-------------0- + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf + + +=============================================================================== +Stephan Linz diff --git a/doc/README.ebony b/doc/README.ebony new file mode 100644 index 0000000..8b030db --- /dev/null +++ b/doc/README.ebony @@ -0,0 +1,136 @@ + AMCC Ebony Board + + Last Update: September 12, 2002 +======================================================================= + +This file contains some handy info regarding U-Boot and the AMCC +Ebony evalutation board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Here's what I've been using successfully. If you feel inclined to +change things ... please read the docs! + +DIPSW U46 U80 +------------------------ +SW 1 off on +SW 2 on on +SW 3 on on +SW 4 off on +SW 5 on off +SW 6 on on +SW 7 on off +SW 8 on off + +J41: strapped +J42: open + +All others are factory default. + + +I2C iprobe +===================== + +The i2c utilities have been tested on both Rev B. and Rev C. and +look good. The CFG_I2C_NOPROBES macro is defined to prevent +probing the CDCV850 clock controller at address 0x69 (since reading +it causes the i2c implementation to misbehave. The output of +iprobe should look like this (assuming you are only using a single +SO-DIMM: + +=> iprobe +Valid chip addresses: 50 53 54 +Excluded chip addresses: 69 + + +GETTING OUT OF I2C TROUBLE +=========================== + +If you're like me ... you may have screwed up your bootstrap serial +eeprom ... or worse, your SPD eeprom when experimenting with the +i2c commands. If so, here are some ideas on how to get out of +trouble: + +Serial bootstrap eeprom corruption: +----------------------------------- +Power down the board and set the following straps: + +J41 - open +J42 - strapped + +This will select the default sys0 and sys1 settings (the serial +eeproms are not used). Then power up the board and fix the serial +eeprom using the imm command. Here are the values I currently +use: + +=> imd 50 0 10 +0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................ + +=> imd 54 0 10 +0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M........... + +Once you have the eeproms set correctly change the +J41/J42 straps as you desire. + +SPD eeprom corruption: +------------------------ +I've corrupted the SPD eeprom several times ... perhaps too much coffee +and not enough presence of mind ;-). By default, the ebony code uses +the SPD to initialize the DDR SDRAM control registers. So if the SPD +eeprom is corrupted, U-Boot will never get into ram. Here's how I got +out of this situation: + +0. First, _before_ playing with the i2c utilities, do an iprobe, then +use imd to capture the various device contents to a file. Some day +you may be glad you did this ... trust me :-). Otherwise try the +following: + +1. In the include/configs/EBONY.h file find the line that defines +the CONFIG_SPD_EEPROM macro and undefine it. E.g: + +#undef CONFIG_SPD_EEPROM + +This will make the code use default SDRAM control register +settings without using the SPD eeprom. + +2. Rebuild U-Boot + +3. Load the new U-Boot image and reboot ebony. + +4. Repair the SPD eeprom using the imm command. Here's the eeprom +contents that work with the default SO-DIMM that comes with the +ebony board (micron 8VDDT164AG-265A1). Note: these are probably +_not_ the factory settings ... but they work. + +=> imd 53 0 10 80 +0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu..... +0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P diff --git a/doc/README.evb64260 b/doc/README.evb64260 new file mode 100644 index 0000000..74211de --- /dev/null +++ b/doc/README.evb64260 @@ -0,0 +1,54 @@ +This file contains status information for the port of U-Boot to the +Galileo Evaluation Board. + +Author: Josh Huber + Mission Critical Linux, Inc. + +The support for the Galileo Evaluation board is fairly minimal now. +It's sufficient to boot Linux, but doesn't provide too much more than +what's required to do this. + +Both DUART channels are supported (to use the second one, you have to +modify the board -- see the schematics for where to solder on the +devices module). The ethernet ports are supported, and the MPSC is +supported as a console driver. (keep in mind that the kernel has no +support for this yet) + +There are still occaisonal lockups with the MPSC console driver due to +(we think!) overrun problems. If you're looking for something stable +to use for Linux development, consider sticking with the DUART console +for now. + +Automatic memory sizing mostly works. We've had problems with some +combinations of memory. Please send us email if you're having trouble +with respect to the memory detection. + +Right now, only the 512k boot flash is supported. Support for the +16MB flash on the devices module is forthcoming. Right now the flash +is stored at the 256k boundry in flash, wasting a whole sector (64k!) +for environment data. This isn't really a big deal since we're not +using the 512k for anything else. (Just U-Boot and the environment) + +Finally, here is a sample output session: + +U-Boot 1.0.0-pre1 (Jun 6 2001 - 12:45:11) + +Initializing... + CPU: MPC7400 (altivec enabled) v2.9 + Board: EVB64260 + DRAM: 256 MB + FLASH: 512 kB + In: serial + Out: serial + Err: serial + +=> + +The default configuration should be correct for the evaluation board, +as it's shipped from Galileo. Keep in mind that the default baudrate +is set to 38400, 8N1. + +Good luck, and make sure to send any bugreports to us (or the +u-boot-users list). + +Josh diff --git a/doc/README.fads b/doc/README.fads new file mode 100644 index 0000000..bae9652 --- /dev/null +++ b/doc/README.fads @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2000 + * Dave Ellis, SIXNET, dge@sixnetio.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +Using the Motorola MPC8XXFADS development board +=============================================== + +CONFIGURATIONS +-------------- + +There are ready-to-use default configurations available for the +FADS823, FADS850SAR and FADS860T. The FADS860T configuration also +works for the 855T processor. + +LOADING U-Boot INTO FADS FLASH MEMORY +-------------------------------------- + +MPC8BUG can load U-Boot into the FLASH memory using LOADF. + + loadf u-boot.srec 100000 + + +STARTING U-Boot FROM MPC8BUG +----------------------------- + +To start U-Boot from MPC8BUG: + +1. Reset the board: + reset :h + +2. Change BR0 and OR0 back to their values at reset: + rms memc br0 00000001 + rms memc or0 00000d34 + +3. Modify DER so MPC8BUG gets control only when it should: + rms der 2002000f + +4. Start as if from reset: + go 100 + +This is NOT exactly the same as starting U-Boot without +MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset. +After it does the reset it writes SYPCR (to disable the watchdog) +and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots +of other initialization). That is why it is necessary to set BR0 +and OR0 to map the FLASH everywhere. U-Boot can't turn on the +watchdog after that, since MPC8BUG has used the only chance to write +to SYPCR. + +Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets +U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T +processor (your mileage may vary). It is probably better (and a lot +easier) just to accept having the watchdog disabled when the debug +cable is connected. + +in MPC8BUG: + reset :h + rms memc br0 00000001 + rms memc or0 00000d34 + rms der 2000f + go 100 + +Now U-Boot is running with the MPC8BUG value for SYPCR. Use the +U-Boot 'reset' command to reset the board. + =>reset +Next, in MPC8BUG: + rms der 2000f + go + +Now U-Boot is running with the U-Boot value for SYPCR. diff --git a/doc/README.idma2intr b/doc/README.idma2intr new file mode 100644 index 0000000..1828b51 --- /dev/null +++ b/doc/README.idma2intr @@ -0,0 +1,10 @@ +(C) 2003 Arun Dharankar + +Attached is an IDMA example code for MPC8260/PPCBoot. I had tried to +search around and could not find any for implementing IDMA, so +implemented one. Its not coded in the best way, but works. + +Also, I was able to test the IDMA specific code under Linux also +(with modifications). My requirement was to implement it for +CompactFlash implemented in memory mode, and it works for it under +PPCBoot and Linux. diff --git a/doc/README.lynxkdi b/doc/README.lynxkdi new file mode 100644 index 0000000..8fdf495 --- /dev/null +++ b/doc/README.lynxkdi @@ -0,0 +1,57 @@ + LYNX KDI SUPPORT + + Last Update: July 20, 2003 +======================================================================= + +This file describes support for LynuxWorks KDI within U-Boot. Support +is enabled by defining CONFIG_LYNXKDI. + + +LYNXOS AND BLUECAT SUPPORTED +============================ +Both LynxOS and BlueCat linux KDIs are supported. The implementation +automatically detects which is being booted. When you use mkimage +you should specify "lynxos" for both (see target-specific notes). + + +SUPPORTED ARCHITECTURE/TARGETS +============================== +The following targets have been tested: + +-PowerPC MPC8260ADS + + +FILES TO LOOK AT +================ +include/lynxkdi.h -defines a simple struct passed to a kdi. +common/lynxkdi.c -implements the call to the kdi. +common/cmd_bootm.c -top-level command implementation ("bootm"). + + +==================================================================== +TARGET SPECIFIC NOTES +==================================================================== + +MPC8260ADS +=========== +The default LynxOS and BlueCat implementations require some +modifications to the config file. + +Edit include/configs/MPC8260ADS.h to use the following: + +#define CFG_IMMR 0xFA200000 +#define CFG_BCSR 0xFA100000 +#define CFG_BR1_PRELIM 0xFA101801 + +When creating a LynxOS or BlueCat u-boot image using mkimage, +you must specify the following: + +Both: -A ppc -O lynxos -T kernel -C none +LynxOS: -a 0x00004000 -e 0x00004020 +BlueCat: -a 0x00500000 -e 0x00507000 + +To pass the MAC address to BlueCat you should define the +"fcc2_ether_addr" parameter in the "bootargs" environment +variable. E.g.: + +==> setenv bootargs fcc2_ether_addr=00:11:22:33:44:55:66 diff --git a/doc/README.m68k b/doc/README.m68k new file mode 100644 index 0000000..d5accdd --- /dev/null +++ b/doc/README.m68k @@ -0,0 +1,136 @@ + +U-Boot for Motorola M68K + +Last Update: January 12, 2004 +==================================================================== + +This file contains status information for the port of U-Boot to the +Motorola M68K series of CPUs. + +1. OVERVIEW +----------- +Bernhard Kuhn ported U-Boot 0.4.0 to the Motorola Coldfire +architecture. The patches of Bernhard support the MCF5272 and +MCF5282. A great disadvantage of these patches was that they needed +a pre-bootloader to start u-boot. Because of this, a new port was +created which no longer needs a first stage booter. + +Although this port is intended to cover all M68k processors, only +the parts for the Motorola Coldfire MCF5272 and MCF5282 are +implemented at the moment. Additional CPUs and boards will be +hopefully added soon! + + +2. SUPPORTED CPUs +----------------- + +2.1 Motorola Coldfire MCF5272 +----------------------------- +CPU specific code is located in: cpu/mcf52x2 + + +2.1 Motorola Coldfire MCF5282 +----------------------------- +CPU specific code is located in: cpu/mcf52x2 + +At the moment the code isn't fully implemented and still needs a pre-loader! +The preloader must initialize the processor and then start u-boot. The board +must be configured for a pre-loader (see 4.1) + +For the preloader, please see +http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html + +U-boot is configured to run at 0x20000 at default. This can be configured by +change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in +include/configs/M5282EVB.h. + + +3. SUPPORTED BOARDs +------------------- + +3.1 Motorola M5272C3 EVB +------------------------ +Board specific code is located in: board/m5272c3 + +To configure the board, type: make M5272C3_config + +U-Boot Memory Map: +------------------ +0xffe00000 - 0xffe3ffff u-boot +0xffe04000 - 0xffe05fff environment (embedded in u-boot!) +0xffe40000 - 0xffffffff free for linux/applications + + +3.2 Motorola M5282 EVB +------------------------ +Board specific code is located in: board/m5282evb + +To configure the board, type: make M5272C3_config + + +4. CONFIGURATION OPTIONS/SETTINGS +---------------------------------- + +4.1 Configuration to use a pre-loader +------------------------------------- +If u-boot should be loaded to RAM and started by a pre-loader +CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the +initial vector table and basic processor initialization will not +be compiled in. The start address of u-boot must be adjusted in +the boards config header file (CFG_MONITOR_BASE) and Makefile +(TEXT_BASE) to the load address. + + +4.1 MCF5272 specific Options/Settings +------------------------------------- + +CONFIG_MCF52x2 -- defined for all MCF52x2 CPUs +CONFIG_M5272 -- defined for all Motorola MCF5272 CPUs + +CONFIG_MONITOR_IS_IN_RAM + -- defined if u-boot is loaded by a pre-loader + +CFG_MBAR -- defines the base address of the MCF5272 configuration registers +CFG_INIT_RAM_ADDR + -- defines the base address of the MCF5272 internal SRAM +CFG_ENET_BD_BASE + -- defines the base addres of the FEC buffer descriptors + +CFG_SCR -- defines the contents of the System Configuration Register +CFG_SPR -- defines the contents of the System Protection Register +CFG_BRx_PRELIM -- defines the contents of the Chip Select Base Registers +CFG_ORx_PRELIM -- defines the contents of the Chip Select Option Registers + +CFG_PxDDR -- defines the contents of the Data Direction Registers +CFG_PxDAT -- defines the contents of the Data Registers +CFG_PXCNT -- defines the contents of the Port Configuration Registers + + +4.2 MCF5282 specific Options/Settings +------------------------------------- + +CONFIG_MCF52x2 -- defined for all MCF52x2 CPUs +CONFIG_M5282 -- defined for all Motorola MCF5282 CPUs + +CONFIG_MONITOR_IS_IN_RAM + -- defined if u-boot is loaded by a pre-loader + +CFG_MBAR -- defines the base address of the MCF5282 internal register space +CFG_INIT_RAM_ADDR + -- defines the base address of the MCF5282 internal SRAM +CFG_INT_FLASH_BASE + -- defines the base address of the MCF5282 internal Flash memory +CFG_ENET_BD_BASE + -- defines the base addres of the FEC buffer descriptors + + +5. COMPILER +----------- +To create U-Boot the gcc-2.95.3 compiler set (m68k-elf-20030314) from uClinux.org was used. +You can download it from: http://www.uclinux.org/pub/uClinux/m68k-elf-tools/ + + +Regards, + +Josef + diff --git a/doc/README.ml300 b/doc/README.ml300 new file mode 100644 index 0000000..27c5b92 --- /dev/null +++ b/doc/README.ml300 @@ -0,0 +1,128 @@ +Xilinx ML300 platform +===================== + +0. Introduction +--------------- + +The Xilinx ML300 board is based on the Virtex-II Pro FPGA with +integrated AMCC PowerPC 405 core. The board is normally booted from +System ACE CF. U-Boot is then run out of main memory. + +An FPGA is a configurable and thus very flexible device. To +accommodate for this flexibility this port of U-Boot includes the +required means to regenerate the drivers and configuration files if +you decide to change the hardware design. The required steps are +described below. + + +1. Requirements +--------------- + +To compile and run U-Boot on the Xilinx ML300 platform you need the +following items. + +- A Xilinx ML300 platform (see http://www.xilinx.com/ml300) +- EDK and ISE development tools (shipping with ML300) +- Parallel4 cable (shipping with ML300) +- The EDK reference design for ML300. You can get this as design #6 from + http://www.xilinx.com/ise/embedded/edk_examples.htm +- A BOOTP/TFTP server + + +2. Quick Start +-------------- + +To compile and run U-Boot on ML300 follow the steps below. Make sure +to consult the documentation for U-Boot, EDK, and the EDK reference +design for ML300 if you have any questions. + +1. Implement the EDK reference design for ML300. You can use any of + the project files, for example from a xygwin shell: + $ xps -nw system_linux.xmp + XPS% run init_bram +2. Configure and compile U-Boot. Change into the root directory of + U-Boot and run: + $ export CROSS_COMPILE=powerpc-eabi- + $ make ml300_config + $ make +3. Set up the ML300, connect the Parallel4 and the serial cable. Start + a terminal on your host computer and set the communication + parameters to 9600,8N1,no handshake. +4. Set up the BOOTP/TFTP server on your host machine. U-Boot is + preconfigured to use a fixed HW MAC address of 00:0A:35:00:22:01. +5. Download the bitstream to the ML300. +6. Use XMD to download and run U-Boot on the ML300: + $ xmd + XMD% ppcconnect + XMD% dow u-boot + XMD% run + +You can now make an ACE file out of bitstream and U-Boot: + $ xmd genace.tcl -jprog -board ml300 -hw \ + implementation/download.bit -elf u-boot -ace top.ace + +Put the ACE file onto the MicroDrive, for example into xilinx/myace, +and reboot ML300. + + +3. Generating a Custom BSP for U-Boot +------------------------------------- + +If you decide to change the EDK reference design for ML300 or if you +build a new design from scratch either with the Base System Builder in +XPS or all by hand you most likely will change the base addresses for +the Uart and the Ethernet peripheral. If you do so you will have two +options: + +1. Edit boards/xilinx/ml300/xparameters.h to reflect the changes you + made to your hardware. +2. Use the MLD technology provided by Xilinx Platform Studio to make + the changes automatically. To do so go to the root directory of the + EDK reference design for ML300. Copy the Linux project file and the + Linux software configuration file: + $ cp system_linux.xmp system_uboot.xmp + $ cp system_linux.mss system_uboot.mss + + Edit system_uboot.xmp and and have it point to system_uboot.mss for + the software configuration. + + Then, copy the sw_services directory in + boards/xilinx/ml300/sw_services to the root directory of the EDK + reference design for ML300. + $ cp -R /boards/xilinx/ml300/sw_services + + Modify system_uboot.mss. Look for the Linux library definition + and change it to generate a BSP for U-Boot. An example, might look + like this: + + BEGIN LIBRARY + PARAMETER LIBRARY_NAME = uboot + PARAMETER LIBRARY_VER = 1.00.a + PARAMETER CONNECTED_PERIPHS = (opb_uart16550_0,opb_ethernet_0) + PARAMETER TARGET_DIR = + END + + Now, you are ready to generate the Xilinx ML300 BSP for U-Boot: + $ xps -nw system_uboot.xmp + XPS% run libs + + If all goes well the new configuration has been copied into the + right places within the U-Boot source tree. Recompile U-Boot and + run it on the ML300. + + +4. ToDo +------- + +- Add support for all other peripherals on ML300. +- Read the MAC address out of the IIC EEPROM. +- Store the bootargs in the IIC EEPROM. + + +5. References +------------- + +ML300: http://www.xilinx.com/ml300 +EDK: http://www.xilinx.com/edk +ISE: http://www.xilinx.com/ise +Reference Design: http://www.xilinx.com/ise/embedded/edk_examples.htm diff --git a/doc/README.modnet50 b/doc/README.modnet50 new file mode 100644 index 0000000..30338ce --- /dev/null +++ b/doc/README.modnet50 @@ -0,0 +1,62 @@ +U-BOOT Port for FSForth ModNET50 Board +-------------------------------------- + +author: Thomas Elste + IMMS gGmbH + +The port based upon an early (partial complete) +armboot-port from Stephan Linz for the ModNET50 Board. + + +Overview: + +- board with Netsilicon NET+50 ARM7TDMI CPU without MMU +- 16 MB SDRAM +- 2 MB Flash (MBL29LV160BE) +- 10/100 Ethernet PHY (LXT971A) + + +Current Configuration (include/configs/modnet50.h): + +Memory Map: 0x00000000 - 0x00FFFFFF 16M SDRAM + 0x10000000 - 0x101FFFFF 2M Flash + +The Flash uses a BB-Architectur with 35 sectors +(0:16K; 1,2:8K; 3:32K; 4-34:64K). U-Boot is located in +the first 5 sectors. + +The environment is located at the end of the 4th Flash +sector (0x1001C000-0x1001FFFF). + +Build: + +U-boot should be build by using the ELDK Toolchain (arm-linux-*). + + make modnet50_config + make + + +Status: + +Everything seems to work fine. Booting images was tested by +booting uCLinux (with and without a separate ramdisk image) from +flash. + + +Files: + +cpu/arm720t/serial_netarm.c .. serial I/O for the cpu + +board/modnet50/lowlevel_init.S .. memory setup for ModNET50 +board/modnet50/flash.c .. flash routines +board/modnet50/modnet50.c .. some board init stuff + +drivers/netarm_eth.c .. ethernet driver for the NET+50 CPU +drivers/netarm_eth.h .. header for ethernet driver + +include/configs/modnet50.h .. configuration file for ModNET50 + +include/netarm_*.h .. register and macro definitions for + the NETARM CPU family + +doc/README.modnet50 .. this readme diff --git a/doc/README.mpc5xx b/doc/README.mpc5xx new file mode 100644 index 0000000..07be863 --- /dev/null +++ b/doc/README.mpc5xx @@ -0,0 +1,48 @@ + +Summary: +======== + +This file contains information about the port of U-Boot to the +Motorola mpc5xx series of CPUs. Most of this code is taken from +existing code mainly from the mpc8xx port. In contrast to mpc8xx, +the mpc5xx has no CPM, MMU and cache facilities. + +The implemented features have been tested on the cmi board, a +customer specific board (see README.cmi). + +Hence this port is only tested on the cmi board further possible +tests on other boards will be very valuable. + +Not Tested Features: +==================== + +* System calls +* Interrupts + +Added or Changed Files: +======================= + +u-boot-0.2.0/common/cmd_boot.c +u-boot-0.2.0/common/cmd_reginfo.c +u-boot-0.2.0/common/environment.c +u-boot-0.2.0/cpu/mpc5xx/* +u-boot-0.2.0/include/cmd_reginfo.h +u-boot-0.2.0/include/common.h +u-boot-0.2.0/include/ppc_asm.tmpl +u-boot-0.2.0/include/watchdog.h +u-boot-0.2.0/include/mpc5xx.h +u-boot-0.2.0/include/status_led.h +u-boot-0.2.0/include/asm-ppc/u-boot.h +u-boot-0.2.0/include/asm-ppc/5xx_immap.h +u-boot-0.2.0/lib_ppc/board.c +u-boot-0.2.0/lib_ppc/cache.c +u-boot-0.2.0/lib_ppc/time.c +u-boot-0.2.0/Makefile +u-boot-0.2.0/CREDITS +u-boot-0.2.0/doc/README.mpc5xx +u-boot-0.2.0/doc/README.cmi +u-boot-0.2.0/README +u-boot-0.2.0/MAKEALL + +Regards, +Martin diff --git a/doc/README.mpc74xx b/doc/README.mpc74xx new file mode 100644 index 0000000..f81f1c2 --- /dev/null +++ b/doc/README.mpc74xx @@ -0,0 +1,22 @@ +This file contains status information for the port of U-Boot to the +Motorola mpc74xx series of CPUs. + +Author: Josh Huber + Mission Critical Linux, Inc. + +Currently the support for these CPUs is pretty minimal, but enough to +get things going. (much like the support for the Galileo Eval Board) + +There is a framework in place to enable the L2 cache, and to program +the BATs. Currently, there are still problems with the code which +sets up the L2 cache, so it's not enabled. (IMHO, it shouldn't be +anyway). Additionally, there is support for enabling the MMU, which +we also don't do. The BATs are programmed just for the benefit of +jumping into Linux in a sane configuration. + +Most of the code was based on other cpus supported by U-Boot. + +If you find any errors in the CPU setup code, please send us a note. + +Thanks, +Josh diff --git a/doc/README.mpc83xxads b/doc/README.mpc83xxads new file mode 100644 index 0000000..d456103 --- /dev/null +++ b/doc/README.mpc83xxads @@ -0,0 +1,98 @@ +Freescale MPC83xx ADS Boards +----------------------------------------- + +0. Toolchain / Building + + $ PATH=$PATH:/usr/powerpc/bin + $ CROSS_COMPILE=powerpc-linux- + $ export PATH CROSS_COMPILE + + $ powerpc-linux-gcc -v + Reading specs from /usr/powerpc/lib/gcc/powerpc-linux/3.4.3/specs + Configured with: ../configure --prefix=/usr/powerpc + --exec-prefix=/usr/powerpc --target=powerpc-linux --enable-shared + --disable-nls --disable-multilib --enable-languages=c,c++,ada,f77,objc + Thread model: posix + gcc version 3.4.3 (Debian) + + $ powerpc-linux-as -v + GNU assembler version 2.15 (powerpc-linux) using BFD version 2.15 + + + $ make MPC8349ADS_config + Configuring for MPC8349ADS board... + + $ make + + +1. Board Switches and Jumpers + + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x9fff_ffff PCI MEM 512M + 0xc000_0000 0xdfff_ffff Rapid IO 512M + 0xe000_0000 0xe00f_ffff CCSR 1M + 0xe200_0000 0xe2ff_ffff PCI IO 16M + 0xf000_0000 0xf7ff_ffff SDRAM 128M + 0xf800_0000 0xf80f_ffff BCSR 1M + 0xfe00_0000 0xffff_ffff FLASH (boot bank) 16M + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC8349ADS.h + + CONFIG_MPC83xx MPC83xx family + CONFIG_MPC8349 MPC8349 specific + CONFIG_MPC8349ADS MPC8349ADS board specific + CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet + + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC8349ADS_config + make + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 10000 u-boot.bin + protect off fe000000 fe09ffff + erase fe000000 fe09ffff + + cp.b 10000 fe000000 xxxx +or + cp.b 10000 fe000000 a0000 + +You might have to supply the correct byte count for 'xxxx' from +the TFTP. Maybe a0000 will work too, that corresponds to the +erased sectors. + + +6. Notes diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads new file mode 100644 index 0000000..f0cf782 --- /dev/null +++ b/doc/README.mpc85xxads @@ -0,0 +1,300 @@ +Motorola MPC8540ADS and MPC8560ADS board + +Created 10/15/03 Xianghua Xiao +Updated 13-July-2004 Jon Loeliger +----------------------------------------- + +0. Toolchain + + The Binutils in current ELDK toolchain will not support MPC85xx + chip. You need to use binutils-2.14.tar.bz2 (or newer) from + http://ftp.gnu.org/gnu/binutils. + + The 8540/8560 ADS code base is known to compile using: + gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a) + + +1. SWITCH SETTINGS & JUMPERS + +1.0 Nomenclature + + For some reason, the HW designers describe the switch settings + in terms of 0 and 1, and then map that to physical switches where + the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1. + Luckily, we're SW types and virtual settings are handled daily. + + The switches for the Rev A board are numbered differently than + for the Pilot board. Oh yeah. + + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the + bits may contribute to signals that are numbered based at 0, + and some of those signals may be high-bit-number-0 too. Heed + well the names and labels and do not get confused. + + "Off" == 1 + "On" == 0 + + SW18 is switch 18 as silk-screened onto the board. + SW4[8] is the bit labled 8 on Switch 4. + SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2 + SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3 + +1.1 For the MPC85xxADS Pilot Board + + First, make sure the board default setting is consistent with the document + shipped with your board. Then apply the following changes: + SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used) + SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560) + SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode) + SW11[7]='ON' (rev2), 'OFF' (rev1) + SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector) + SW22[1-4]="OFF OFF ON OFF" + SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF" + J1 = "Enable Prog" (Make sure your flash is programmable for development) + + If you want to test PCI functionality with a 33Mhz PCI card, you will + have to change the system clock from the default 66Mhz to 33Mhz by + setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need + double your platform clock(SW6) because the system clock is now only + half of its original value. For example, if at 66MHz your system + clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10. + + SW17[8] ------+ SW6 + SW15[1] ----+ | [0:1] + V V V V + 33MHz 1 1 1 0 + 66MHz 0 0 0 1 + + Hmmm... That SW6 setting description is incomplete but it works. + + +1.3 For the MPC85xxADS Rev A Board + + As shipped, the board should be a 33MHz PCI bus with a CPU Clock + rate of 825 +/- fuzz: + + Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz + + For 33MHz PCI, the switch settings should be like this: + + SW18[7:1] = 0100001 = M==33 => 33MHz + SW18[8] = 1 => PWD Divider == 16 + SW16[1:2] = 11 => N == 16 as PWD==1 + + Use the magical formula: + Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz + + SW7[1:4] = 1010 = 10 => 10 x 33 = 330 CCB Sysclk + SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock + + + For 66MHz PCI, the switch settings should be like this: + + SW18[7:1] = 0100001 = M==33 => 33MHz + SW18[8] = 0 => PWD Divider == 1 + SW16[1:2] = 01 => N == 8 as PWD == 0 + + Use the magical formula: + Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz + + SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk + SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock + + +2. MEMORY MAP TO WORK WITH LINUX KERNEL + +2.1. For the initial bringup, we adopted a consistent memory scheme + between u-boot and linux kernel, you can customize it based on your + system requirements: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x9fff_ffff PCI MEM 512M + 0xc000_0000 0xdfff_ffff Rapid IO 512M + 0xe000_0000 0xe00f_ffff CCSR 1M + 0xe200_0000 0xe2ff_ffff PCI IO 16M + 0xf000_0000 0xf7ff_ffff SDRAM 128M + 0xf800_0000 0xf80f_ffff BCSR 1M + 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + +2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You + can download them from linuxppc-2.4 public source. Please make sure the + kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two + default configuration files as your starting points to configure the + kernel: + arch/ppc/configs/mpc8540_ads_defconfig + arch/ppc/configs/mpc8560_ads_defconfig + +3. DEFINITIONS AND COMPILATION + +3.1 Explanation on NEW definitions in: + include/configs/MPC8540ADS.h + include/configs/MPC8560ADS.h + + CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc) + CONFIG_E500 BOOKE e500 family(Motorola) + CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives + CONFIG_MPC8540 MPC8540 specific + CONFIG_MPC8540ADS MPC8540ADS board specific + CONFIG_MPC8560ADS MPC8560ADS board specific + CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking + CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can + also manual config the DDR after undef this + definition. + CONFIG_DDR_ECC only for ECC DDR module + CONFIG_DDR_DLL DLL fix on some ADS boards needed for more + stability. + CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0. + +Other than the above definitions, the rest in the config files are +straightforward. + + +3.2 Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC8560ADS_config (or make MPC8540ADS_config) + make + +4. Notes: + +4.1 When connecting with kermit, the following commands must be present.in + your .kermrc file. These are especially important when booting as + MPC8560, as the serial console will not work without them: + + set speed 115200 + set carrier-watch off + set handshake none + set flow-control none + robust + + +4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC + ethernet. If that happens, you can try the following steps to make + network work: + + MPC8560ADS>tftp 1000000 pImage + (if it hangs, use Ctrl-C to quit) + MPC8560ADS>nm fdf24524 + >0 + >1 + >. (to quit this memory operation) + MPC8560ADS>tftp 1000000 pImage + +4.3 If you're one of the early developers using the Rev1 8540/8560 chips, + please use U-Boot 1.0.0, as the newer silicon will only support Rev2 + and future revisions of 8540/8560. + + +4.4 Reflash U-boot Image using U-boot + + tftp 10000 u-boot.bin + protect off fff80000 ffffffff + erase fff80000 ffffffff + cp.b 10000 fff80000 80000 + + +4.5 Reflash U-Boot with a BDI-2000 + + BDI> erase 0xFFF80000 0x4000 0x20 + BDI> prog 0xfff80000 u-boot.bin.8560ads + BDI> verify + + +5. Screen dump MPC8540ADS board + +U-Boot 1.1.2(pq3-20040707-0) (Jul 6 2004 - 17:34:25) + +Freescale PowerPC + Core: E500, Version: 2.0, (0x80200020) + System: 8540, Version: 2.0, (0x80300020) + Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz + L1 D-cache 32KB, L1 I-cache 32KB enabled. +Board: ADS + PCI1: 32 bit, 66 MHz (compiled) +I2C: ready +DRAM: Initializing + SDRAM: 64 MB + DDR: 256 MB +FLASH: 16 MB +L2 cache enabled: 256KB +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: MOTO ENET0: PHY is Marvell 88E1011S (1410c62) +MOTO ENET1: PHY is Marvell 88E1011S (1410c62) +MOTO ENET2: PHY is Davicom DM9161E (181b881) +MOTO ENET0, MOTO ENET1, MOTO ENET2 +Hit any key to stop autoboot: 0 +=> +=> fli + +Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K) + Size: 16 MB in 64 Sectors + Sector Start Addresses: + FF000000 FF040000 FF080000 FF0C0000 FF100000 + FF140000 FF180000 FF1C0000 FF200000 FF240000 + FF280000 FF2C0000 FF300000 FF340000 FF380000 + FF3C0000 FF400000 FF440000 FF480000 FF4C0000 + FF500000 FF540000 FF580000 FF5C0000 FF600000 + FF640000 FF680000 FF6C0000 FF700000 FF740000 + FF780000 FF7C0000 FF800000 FF840000 FF880000 + FF8C0000 FF900000 FF940000 FF980000 FF9C0000 + FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000 + FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000 + FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000 + FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000 + FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO) + +=> bdinfo +memstart = 0x00000000 +memsize = 0x10000000 +flashstart = 0xFF000000 +flashsize = 0x01000000 +flashoffset = 0x00000000 +sramstart = 0x00000000 +sramsize = 0x00000000 +immr_base = 0xE0000000 +bootflags = 0xE4013F80 +intfreq = 825 MHz +busfreq = 330 MHz +ethaddr = 00:E0:0C:00:00:FD +eth1addr = 00:E0:0C:00:01:FD +eth2addr = 00:E0:0C:00:02:FD +IP addr = 192.168.1.253 +baudrate = 115200 bps + + +=> printenv +bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr +ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr +nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr +bootdelay=10 +baudrate=115200 +loads_echo=1 +ethaddr=00:E0:0C:00:00:FD +eth1addr=00:E0:0C:00:01:FD +eth2addr=00:E0:0C:00:02:FD +ipaddr=192.168.1.253 +serverip=192.168.1.1 +rootpath=/nfsroot +gatewayip=192.168.1.1 +netmask=255.255.255.0 +hostname=unknown +bootfile=your.uImage +loadaddr=200000 +netdev=eth0 +consoledev=ttyS0 +ramdiskaddr=400000 +ramdiskfile=your.ramdisk.u-boot +stdin=serial +stdout=serial +stderr=serial +ethact=MOTO ENET0 + +Environment size: 1020/8188 bytes diff --git a/doc/README.mpc85xxcds b/doc/README.mpc85xxcds new file mode 100644 index 0000000..bc5db0c --- /dev/null +++ b/doc/README.mpc85xxcds @@ -0,0 +1,225 @@ +Motorola MPC85xxCDS boards +-------------------------- + +The CDS family of boards consists of a PCI backplane called the +"Arcadia", a PCI-form-factor carrier card that plugs into a PCI slot, +and a CPU daughter card that bolts onto the daughter card. + +Much of the content of the README.mpc85xxads for the 85xx ADS boards +applies to the 85xx CDS boards as well. In particular the toolchain, +the switch nomenclature, and the basis for the memory map. There are +some differences, though. + + +Building U-Boot +--------------- + +The Binutils in current ELDK toolchain will not support MPC85xx +chip. You need to use binutils-2.14.tar.bz2 (or newer) from + http://ftp.gnu.org/gnu/binutils. + +The 85xx CDS code base is known to compile using: + gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a) + + +Memory Map +---------- + +The memory map for u-boot and linux has been extended w.r.t. the ADS +platform to allow for utilization of all 85xx CDS devices. The memory +map is setup for linux to operate properly. The linux source when +configured for MPC85xx CDS has been updated to reflect the new memory +map. + +The mapping is: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + 0xe000_0000 0xe00f_ffff CCSR 1M + 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + 0xf000_0000 0xf7ff_ffff SDRAM 128M + 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + + (*) The system control registers (CADMUS) start at offset 0xfdb0_4000 + within the NVRAM/CADMUS region of memory. + + +Using Flash +----------- + +The CDS board has two flash banks, each 8MB in size (2^23 = 0x00800000). +There is a switch which allows the boot-bank to be selected. The switch +settings for updating flash are given below. + +The u-boot commands for copying the boot-bank into the secondary bank are +as follows: + + erase ff780000 ff7fffff + cp.b fff80000 ff780000 80000 + + +U-boot/kermit commands for downloading an image, then copying +it into the secondary bank: + + loadb + [Drop to kermit: + ^\c + send + c + ] + + erase ff780000 ff7fffff + cp.b $loadaddr ff780000 80000 + + +U-boot commands for downloading an image via tftp and flashing +it into the second bank: + + tftp 10000 + erase ff780000 ff7fffff + cp.b 10000 ff780000 80000 + + +After copying the image into the second bank of flash, be sure to toggle +SW2[2] on the carrier card before resetting the board in order to set the +secondary bank as the boot-bank. + + +Carrier Board Switches +---------------------- + +As a reminder, you should read the README.mpc85xxads too. + +Most switches on the carrier board should not be changed. The only +user-settable switches on the carrier board are used to configure +the flash banks and determining the PCI slot. + +The first two bits of SW2 control how flash is used on the board: + + 12345678 + -------- + SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available. + 01XXXXXX FLASH: Boot bank 2, bank 1 available (swapped). + 10XXXXXX FLASH: Boot promjet, bank 1 available + 11XXXXXX FLASH: Boot promjet, bank 2 available + +The boot bank is always mapped to FF80_0000 and listed first by +the "flinfo" command. The secondary bank is always FF00_0000. + +When using PCI, linux needs to know to which slot the CDS carrier is +connected.. By convention, the user-specific bits of SW2 are used to +convey this information: + + 12345678 + -------- + SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia + xxxxxx01 PCI SLOT INFORM: The CDS carrier is in slot1 of the Arcadia + xxxxxx10 PCI SLOT INFORM: The CDS carrier is in slot2 of the Arcadia + xxxxxx11 PCI SLOT INFORM: The CDS carrier is in slot3 of the Arcadia + +These are cleverly, er, clearly silkscreened as Slot 1 through 4, +respectively, on the Arcadia near the support posts. + + +The default setting of all switches on the carrier board is: + + 12345678 + -------- + SW1=01101100 + SW2=0x1111yy x=Flash bank, yy=PCI slot + SW3=11101111 + SW4=10001000 + + +8555/41 CPU Card Switches +------------------------- + +Most switches on the CPU Card should not be changed. However, the +frequency can be changed by setting SW3: + + 12345678 + -------- + SW3=XX00XXXX == CORE:CCB 2:1 + XX01XXXX == CORE:CCB 5:2 + XX10XXXX == CORE:CCB 3:1 + XX11XXXX == CORE:CCB 7:2 + XXXX1000 == CCB:SYSCLK 8:1 + XXXX1010 == CCB:SYSCLK 10:1 + +A safe default setting for all switches on the CPU board is: + + 12345678 + -------- + SW1=10001111 + SW2=01000111 + SW3=00001000 + SW4=11111110 + + +8548 CPU Card Switches +---------------------- +And, just to be confusing, in this set of switches: + + ON = 1 + OFF = 0 + +Default + SW1=11111101 + SW2=10011111 + SW3=11001000 (8X) (2:1) + SW4=11110011 + + SW3=X000XXXX == CORE:CCB 4:1 + X001XXXX == CORE:CCB 9:2 + X010XXXX == CORE:CCB 1:1 + X011XXXX == CORE:CCB 3:2 + X100XXXX == CORE:CCB 2:1 + X101XXXX == CORE:CCB 5:2 + X110XXXX == CORE:CCB 3:1 + X111XXXX == CORE:CCB 7:2 + XXXX0000 == CCB:SYSCLK 16:1 + XXXX0001 == RESERVED + XXXX0010 == CCB:SYSCLK 2:1 + XXXX0011 == CCB:SYSCLK 3:1 + XXXX0100 == CCB:SYSCLK 4:1 + XXXX0101 == CCB:SYSCLK 5:1 + XXXX0110 == CCB:SYSCLK 6:1 + XXXX0111 == RESERVED + XXXX1000 == CCB:SYSCLK 8:1 + XXXX1001 == CCB:SYSCLK 9:1 + XXXX1010 == CCB:SYSCLK 10:1 + XXXX1011 == RESERVED + XXXX1100 == CCB:SYSCLK 12:1 + XXXX1101 == CCB:SYSCLK 20:1 + XXXX1110 == RESERVED + XXXX1111 == RESERVED + + +eDINK Info +---------- + +One bank of flash may contain an eDINK image. + +Memory Map: + + CCSRBAR @ 0xe0000000 + Flash Bank 1 @ 0xfe000000 + Flash Bank 2 @ 0xff000000 + Ram @ 0 + +Commands for downloading a u-boot image to memory from edink: + + env -c + time -s 4/8/2004 4:30p + dl -k -b -o 100000 + [Drop to kermit: + ^\c + transmit /binary + c + ] + + fu -l 100000 fe780000 80000 diff --git a/doc/README.nand b/doc/README.nand new file mode 100644 index 0000000..0f2bdc5 --- /dev/null +++ b/doc/README.nand @@ -0,0 +1,175 @@ +NAND FLASH commands and notes + +# (C) Copyright 2003 +# Dave Ellis, SIXNET, dge@sixnetio.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +Commands: + + nand bad + Print a list of all of the bad blocks in the current device. + + nand device + Print information about the current NAND device. + + nand device num + Make device `num' the current device and print information about it. + + nand erase off size + nand erase clean [off size] + Erase `size' bytes starting at offset `off'. Only complete erase + blocks can be erased. + + If `clean' is specified, a JFFS2-style clean marker is written to + each block after it is erased. If `clean' is specified without an + offset or size, the entire flash is erased. + + This command will not erase blocks that are marked bad. There is + a debug option in cmd_nand.c to allow bad blocks to be erased. + Please read the warning there before using it, as blocks marked + bad by the manufacturer must _NEVER_ be erased. + + nand info + Print information about all of the NAND devices found. + + nand read addr ofs size + Read `size' bytes from `ofs' in NAND flash to `addr'. If a page + cannot be read because it is marked bad or an uncorrectable data + error is found the command stops with an error. + + nand read.jffs2 addr ofs size + Like `read', but the data for blocks that are marked bad is read as + 0xff. This gives a readable JFFS2 image that can be processed by + the JFFS2 commands such as ls and fsload. + + nand read.oob addr ofs size + Read `size' bytes from the out-of-band data area corresponding to + `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of + data for one 512-byte page or 2 256-byte pages. There is no check + for bad blocks or ECC errors. + + nand write addr ofs size + Write `size' bytes from `addr' to `ofs' in NAND flash. If a page + cannot be written because it is marked bad or the write fails the + command stops with an error. + + nand write.jffs2 addr ofs size + Like `write', but blocks that are marked bad are skipped and the + is written to the next block instead. This allows writing writing + a JFFS2 image, as long as the image is short enough to fit even + after skipping the bad blocks. Compact images, such as those + produced by mkfs.jffs2 should work well, but loading an image copied + from another flash is going to be trouble if there are any bad blocks. + + nand write.oob addr ofs size + Write `size' bytes from `addr' to the out-of-band data area + corresponding to `ofs' in NAND flash. This is limited to the 16 bytes + of data for one 512-byte page or 2 256-byte pages. There is no check + for bad blocks. + +Configuration Options: + + CFG_CMD_NAND + A good one to add to CONFIG_COMMANDS since it enables NAND support. + + CONFIG_MTD_NAND_ECC_JFFS2 + Define this if you want the Error Correction Code information in + the out-of-band data to be formatted to match the JFFS2 file system. + CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for + someone to implement. + + CFG_MAX_NAND_DEVICE + The maximum number of NAND devices you want to support. + +NAND Interface: + + #define NAND_WAIT_READY(nand) + Wait until the NAND flash is ready. Typically this would be a + loop waiting for the READY/BUSY line from the flash to indicate it + it is ready. + + #define WRITE_NAND_COMMAND(d, adr) + Write the command byte `d' to the flash at `adr' with the + CLE (command latch enable) line true. If your board uses writes to + different addresses to control CLE and ALE, you can modify `adr' + to be the appropriate address here. If your board uses I/O registers + to control them, it is probably better to let NAND_CTL_SETCLE() + and company do it. + + #define WRITE_NAND_ADDRESS(d, adr) + Write the address byte `d' to the flash at `adr' with the + ALE (address latch enable) line true. If your board uses writes to + different addresses to control CLE and ALE, you can modify `adr' + to be the appropriate address here. If your board uses I/O registers + to control them, it is probably better to let NAND_CTL_SETALE() + and company do it. + + #define WRITE_NAND(d, adr) + Write the data byte `d' to the flash at `adr' with the + ALE and CLE lines false. If your board uses writes to + different addresses to control CLE and ALE, you can modify `adr' + to be the appropriate address here. If your board uses I/O registers + to control them, it is probably better to let NAND_CTL_CLRALE() + and company do it. + + #define READ_NAND(adr) + Read a data byte from the flash at `adr' with the + ALE and CLE lines false. If your board uses reads from + different addresses to control CLE and ALE, you can modify `adr' + to be the appropriate address here. If your board uses I/O registers + to control them, it is probably better to let NAND_CTL_CLRALE() + and company do it. + + #define NAND_DISABLE_CE(nand) + Set CE (Chip Enable) low to enable the NAND flash. + + #define NAND_ENABLE_CE(nand) + Set CE (Chip Enable) high to disable the NAND flash. + + #define NAND_CTL_CLRALE(nandptr) + Set ALE (address latch enable) low. If ALE control is handled by + WRITE_NAND_ADDRESS() this can be empty. + + #define NAND_CTL_SETALE(nandptr) + Set ALE (address latch enable) high. If ALE control is handled by + WRITE_NAND_ADDRESS() this can be empty. + + #define NAND_CTL_CLRCLE(nandptr) + Set CLE (command latch enable) low. If CLE control is handled by + WRITE_NAND_ADDRESS() this can be empty. + + #define NAND_CTL_SETCLE(nandptr) + Set CLE (command latch enable) high. If CLE control is handled by + WRITE_NAND_ADDRESS() this can be empty. + +More Definitions: + + These definitions are needed in the board configuration for now, but + may really belong in a header file. + TODO: Figure which ones are truly configuration settings and rename + them to CFG_NAND_... and move the rest somewhere appropriate. + + #define SECTORSIZE 512 + #define ADDR_COLUMN 1 + #define ADDR_PAGE 2 + #define ADDR_COLUMN_PAGE 3 + #define NAND_ChipID_UNKNOWN 0x00 + #define NAND_MAX_FLOORS 1 + #define NAND_MAX_CHIPS 1 diff --git a/doc/README.ne2000 b/doc/README.ne2000 new file mode 100644 index 0000000..d5ae9a9 --- /dev/null +++ b/doc/README.ne2000 @@ -0,0 +1,38 @@ +This driver supports NE2000 compatible cards (those based on DP8390, +DP83902 and similar). It can be used with PCMCIA/CF cards provided +that the CCR is correctly initialized. + +The code is based on sources from the Linux kernel (pcnet_cs.c, +8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 +wonderful world are GPL, so this is, of course, GPL. + +I developed and tested this driver on a custom PXA255 based system and +with a billionton CF network card connected to the PCMCIA interface of +the micro (have a look at README.PXA_CF for the support of this port). + +The options you have to specify in the config file are (with the +value for my board as an example): + +#define CONFIG_DRIVER_NE2000 + +- Enables the driver + +#define CONFIG_DRIVER_NE2000_BASE (0x20000000+0x300) + +- Address where the board is mapped + +#define CONFIG_DRIVER_NE2000_CCR (0x28000000+0x3f8) + +- Address of the CCR (card configuration register). It could be found +by enabling DEBUG in cmd_pcmcia.c. If this is not defined nothing is +done as far as PCMCIA support is concerned. + +#define CONFIG_DRIVER_NE2000_VAL (0x20) + +- The value to be written in the CCR. It selects among different I/O +spaces that could be used by the card. + + +Enjoy! + +Christian Pellegrin diff --git a/doc/README.nios b/doc/README.nios new file mode 100644 index 0000000..671e727 --- /dev/null +++ b/doc/README.nios @@ -0,0 +1,366 @@ + + U-Boot for Nios-32 + + Last Update: February 1, 2004 +==================================================================== + +This file contains information regarding U-Boot and the Altera +Nios CPU. For information regarding U-Boot and the Nios Development +Kits see: + + * Cyclone Edition (DK-1C20), see doc/README.dk1c20 + * Stratix Edition (DK-1S10), see doc/README.dk1s10 (TODO) + * Stratix Edition (DK-1S40), see doc/README.dk1s40 (TODO) + * Stratix Edition (DK-20K200), see doc/README.dk20k200 (TODO) + +For informations regarding Nios Development Kit hardware overview +and the NIOS CPU standard configuration of all known boards made by +Altera see: + + * Development Kit (DK) hardware overview, see doc/README.nios_DK + * NIOS CPU standard_32 at DK-1C20, see doc/README.dk1c20_std32 + * NIOS CPU standard_32 at DK-1S10, see doc/README.dk1s10_std32 + * NIOS CPU standard_32 at DK-1S40, see doc/README.dk1s40_std32 + * NIOS CPU standard_32 at DK-20K200, see doc/README.dk20k200_std32 + +For those interested in contributing ... see HELP WANTED below. + + +1. OVERVIEW +------------ + +U-Boot has been successfully tested on the Nios Cyclone development +board using both the 'safe' and 'standard 32' configurations with +Nios CPU revision 3.1 (CPU_ID = 0x3018). U-Boot can be used with +or without the GERMS monitor. The initial version of U-Boot for the +Cyclone development kit is about 60 Kbyte and will fit in a single +sector of on-board FLASH. Only the Nios 32-bit CPU is supported. + +1.1 GERMS Monitor +------------------ +If GERMS is just not enough, then U-Boot is a great antibiotic. +You will be very pleased with its high degree of configurability +and its rich feature set. + +A few of the most obvious limitations of GERMS are overcome by +using U-Boot (See 'Brain Damage'). Most notably, you can use +minicom or Hyperterminal (duh). + +1.2 Altera Source Code +----------------------- +The Nios port does NOT include ANY sources that Altera has the +copyright. This was a conscious decision ... not an accident. +The Altera license is not clear in terms of distributing Altera +sources (when altera silicon is not involved). This isn't really +a problem as little, if any, of the Altera source contains +features that are not already available in U-Boot. + +1.3 Debugging via OCI +--------------------- +The Nios port supports debugging with gdb and/or nios-console +via the JTAG port. Stubs for debugging with gdb via the serial +port are not currently implemented. + + +2. CONFIGURATION OPTIONS/SETTINGS +---------------------------------- + +2.1 Nios-specific Options/Settings +----------------------------------- +All configuration options/settings that are specific to Nios begin +with "CONFIG_NIOS_", "CFG_NIOS_", or "CFG_NIOS_CPU_". + +The configuration follows a two-stage process. In the first stage +the NIOS CPU core will defined like defined in Alteras SOPC Builder. +At this point we use the "CFG_NIOS_CPU_" defines exclusively. For +more informations about all the definitions you have to setup see +into current board configurations and doc/README.nios_CFG_NIOS_CPU. + +In second stage we bring the NIOS CPU configuration in relation to +U-Boot configuration options/settings. The following is a list of +currently defined Nios-specific options/parameters used inside of +U-Boot. If any options are related to Standard-32 Nios SDK +excalibur.h definitions, the related definition follows the +description). + +CONFIG_NIOS -- defined for all Nios-32 boards. + +CFG_NIOS_CONSOLE -- the base address of the console UART or the JTAG + stdio port. To enable a console via JTAG, define + CONFIG_CONSOLE_JTAG and set CGF_NIOS_CONSOLE to the base address + of the JTAG stdio port (normally OCI base + 0x00fa). Then + run nios-console with the -w option. + (standard-32: nasys_uart_0 resp. na_uart1_base). + +CFG_NIOS_FIXEDBAUD -- defined if the console UART PTF fixed_baud + parameter is set to '1'. + +CFG_NIOS_MULT_HW -- use full hardware multiply (not yet implemented). + +CFG_NIOS_MULT_MSTEP -- use hardware assisted multiply using the + MSTEP instruction (not yet implemented). + +CFG_NIOS_TMRBASE -- the base address of the timer used to support + xxx_timer routines (e.g. set_timer(), get_timer(), etc.). + (standard-32: nasys_timer_1 resp. na_lo_priority_timer2_base). + +CFG_NIOS_TMRIRQ -- the interrupt request (vector number) assigned to + the timer. (standard-32: nasys_timer_1_irq resp. + na_low_priority_timer2_irq). + +CFG_NIOS_TMRMS -- the period of the timer in milliseconds. + +CFG_NIOS_TMRCNT -- the preloadable counter value for the timer if it has + no fixed period. + +CFG_NIOS_ASMIBASE -- the base address of the ASMI peripheral. + (standard-32: na_asmi_base). + +CFG_NIOS_SPIBASE -- the base address of the SPI master (!) peripheral. + (nasys_spi_0) + +CFG_NIOS_SPIBITS -- the amount of configured SPI data bits in PTF. + This value can be 8 or 16 only! (PTF: databits) + + +2.2 Differences in U-Boot Options/Settings +------------------------------------------- +Some 'standard' U-Boot options/settings are treated differently in +the Nios port. These are described below. + +CFG_GBL_DATA_OFFSET -- in the Nios port, this is the offset of the + global data structure in the Nios memory space. More simply, + the address of global data. + + +3. ASSEMBLY CODING +------------------- + +In browsing the assembly source files, you may notice the absence +of the 'magic macros' (e.g. MOVIA, MOVIP, ADDIP etc.). This is +deliberate. The documentation for the magic macros is scant and +it is hard to find ... it does not appear in the Nios programmer's +manual, nor does it appear in the assembler manual. Regardless, +the macros actually do very little to improve readability anyway. + +With this in mind, all assembler modules use only instructions that +appear in the Nios programmer's manual OR are directly supported +by the nios-elf toolchain. For example, the 'dec %rB' instruction +is an alias for 'subi %rB,1' that is supported by the assembler +but does not appear in the programmer's manual. + + +4. BOOT PROCESS +--------------- + +4.1 Boot process over GERMS +--------------------------- +When the NIOS CPU catch a reset signal it will begin to be running +code from CFG_NIOS_CPU_RST_VECT. Normally at this place it will +find the GERMS monitor. That's the case for the generic NIOS CPU +configuration "standard_32". When the GERMS monitor starts running, +it performs important system initializations and then looks for +executable code in flash, using the following steps: + + 1. Examining the two bytes at CFG_NIOS_CPU_FLASH_BASE + 0x04000C. + 2. Examining the button 0 on the PIO CFG_NIOS_CPU_BUTTON_PIO. + 3. If the button is not pressed and the two bytes contain 'N' + and 'i', the monitor executes a CALL to location + CFG_NIOS_CPU_FLASH_BASE + 0x040000. + 4. If the code is not executed in step 3 or the code returns, + then prints an 8-digit version number to STDOUT and waits for + user commands from STDIN. + +In normal case, for "standard_32", STDIN and STDOUT are the first +serial port. + +4.2 Return to GERMS command line +-------------------------------- +During the boot process, the GERMS monitor checks for the existence +of application software in flash memory. If found, the processor +immediately executes the code. To return program execution to the +GERMS monitor (that is, avoid running code stored in flash memory): + + 1. Hold down CFG_NIOS_CPU_BUTTON_PIO, button number 0. + 2. Press then release the CPU reset button. + 3. Release CFG_NIOS_CPU_BUTTON_PIO, button number 0. + + +5. DEBUGGING WITH GDB +--------------------- + +Debug sessions using gdb are currently supported only via JTAG. The +stubs for debugging via a serial port are not implemented. To enable +the gdb JTAG stubs, simply reference _brkpt_hw_int and _brkpt_sw_int +at vector table offsets 3 and 4, respectively. For an example, see +board/altera/dk1c20/vectors.S. + +5.1 Vector Table Initialization and ROM Stubs +--------------------------------------------- +If CONFIG_ROM_STUBS is defined, the debug breakpoint and single step +entries in the vector table are restored to their initial values +immediately _after_ initializing the vector table. Defining this macro +is useful when ROM-based stubs are implemented. + +NOTE: The default GERMS monitor does NOT implement gdb stubs, nor does +it initialize the vector table. Therefore, when debugging U-Boot, you +should NOT set a software breakpoint prior to vector table initialization. + +5.2 Starting a Debug Session +---------------------------- +If you're not familiar with gdb, you follow these step-by-step instructions. +These instructions are NOT the only way to start a debug session, but they +cover most of the individual functions to get you started. + + 1. Start the JTAG gdb server. Open a Nios shell window and start + the server. When the server is started you must provide the base + address of the OCI core. For example, when using the Cyclone + development kit (DK1C20): + + $ nios-gdb-server --ocibase=0x00920800 --tcpport=2342 + + 2. Start gdb. Open a Nios shell window, change to the top-level + U-Boot directory and start gdb, specifying the u-boot elf file: + + $ nios-elf-gdb u-boot + + 3. Update target settings. From the file menu, select + "Target Settings ..." and select the following, then click 'Ok': + + Target: Remote/TCP + Port : 2342 (same as in step 1) + Display download dialog: checked + All other check boxes: unchecked + + 4. Connect to the target. Select menu: 'Run->Connect to target'. + You should see a dialog box indicating the you successfully connected + to the target. + + 5. Download U-Boot. Select menu: 'Run->Download'. + + 6. Open a gdb console window and set the source directory paths. + Select menu: 'View->Console'. In the console window, enter the + following commands, then close the console window: + + (gdb) directory common + (gdb) directory cpu/nios + (gdb) directory lib_nios + (gdb) directory board/altera/dk1c20 + + Note that the last command is for the DK1C20 board only. If you + are using another board, specify that board's directory. + + 7. Open the file board.c (using the file menu in the lower + left hand corner). Scroll to the board_init() routine and set + a breakpoint. + + 8. Run U-Boot. Just click on the run icon, or select menu: + 'Run->Run'. U-Boot should start running, then break at your + breakpoint. + + 9. Have fun & start learning more about gdb. + + +5.3 For advanced Users +---------------------- +A few notes for those more familiar with gdb. + + -Serial port stubs are not implemented. Sorry, but it's just not + worth _my_ effort. The JTAG stubs work great and are ridiculously + simple to implement. + + -If you need to debug the early startup code (prior to the vector + table initialization), use the nios-console debugger. + + - Connect, download & run -- there are some problems here. Connect + download and run seperately to avoid trouble. + +6. BRAIN DAMAGE +---------------- + +This section describes some of the unfortunate and avoidable aspects +of working with the Nios CPU ... and some things you can do to +reduce your pain. + +6.1 GERMS doesn't work with Hyperterminal +------------------------------------------ +GERMS doesn't do CR/LF mapping that is compatible with Hyperterminal +(or minicom) -- geez. Regardless of you opion of Hyperterminal, this +sad design decision is remedied by using U-Boot. + +6.2 cygwin Incompatibility +--------------------------- +The version of cygwin distributed with the nios GNUPro toolchain is +out-of-date and incompatible with the latest cygwin distributions. +In addition, many of the standard utilities are very dated as well. +If you try to download and build the lastest version of grep for +example, you'll quickly realize that a native gcc is not available +(the next topic) which leads to U-Boot build problems (following +topic). + +The solution ... well, you can wait for Altera ... or build as +set of tools for linux. + +6.3 No native gcc +------------------ +I'm not sure how this one slipped through the cracks ... but it is +a real pain. Basically, if you want to build anything for the native +environment -- forget it! A native (cygwin) gcc is not distributed, +and the old version of cygwin makes locating one challenging. + +The solution ... same as above. Just download the gcc source from +Altera and build up a set of cross tools for your favorite linux +distro. Anybody who wants to use an already precompiled NIOS cross +toolchain can it found in the CDK4NIOS project hosted by Source +Forge at http://cdk4nios.sourceforge.net. + +6.4 Can't build default U-Boot +------------------------------- +By default, when you build U-Boot you will be building some native +tools along with the target elf, bin, and srec files. Without a +native gcc, this (obviously) causes problems. + +For developers using the Altera cygwin tools you can remove the +'tools' directory from SUBDIRS in the top-level Makefile. You will +also have to edit common/Makefile: + +Replace: +environment.o: environment.c ../tools/envcrc + $(CC) $(AFLAGS) -Wa,--no-warn \ + -DENV_CRC=$(shell ../tools/envcrc) \ + -c -o $@ environment.c + +With: +environment.o: environment.c + $(CC) $(AFLAGS) -Wa,--no-warn \ + -DENV_CRC=0 \ + -c -o $@ environment.c + +BTW, thats a 'zero' ... not the letter 'O'. And not that the +"../tools/envcrc" dependency is removed. + + +7. HELP WANTED +--------------- + +There are plenty of areas where help is needed. Here's are some ideas +for those interested in contributing: + +-CompactFlash. Port & test CF/FAT. + +-Bedbug. Develop bedbug for Nios ... or at least provide a disassemble + command. + +-Add boot support for ucLinux (niosnommu). + +-Implement (don't copy Altera code) the __mulxx routines using the + MSTEP and MUL instructions (e.g. CFG_NIOS_MULT_HW and CFG_NIOS_MULT_MSTEP). + + +Regards, + +--Scott + + +--Stephan + diff --git a/doc/README.nios_CFG_NIOS_CPU b/doc/README.nios_CFG_NIOS_CPU new file mode 100644 index 0000000..e38ed91 --- /dev/null +++ b/doc/README.nios_CFG_NIOS_CPU @@ -0,0 +1,140 @@ + +=============================================================================== + C F G _ N I O S _ C P U _ * v s . N I O S S D K +=============================================================================== + +When ever you have to make a new NIOS CPU configuration you can use this table +as a reference list to the original NIOS SDK symbols made by Alteras SOPC +Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc. +Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description +(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO. + +C O R E N I O S S D K [1],[7] +------------------------------------------------------------------------------- +CFG_NIOS_CPU_CLK nasys_clock_freq +CFG_NIOS_CPU_ICACHE nasys_icache_size +CFG_NIOS_CPU_DCACHE nasys_dcache_size +CFG_NIOS_CPU_REG_NUMS nasys_nios_num_regs +CFG_NIOS_CPU_MUL __nios_use_multiply__ +CFG_NIOS_CPU_MSTEP __nios_use_mstep__ +CFG_NIOS_CPU_STACK nasys_stack_top +CFG_NIOS_CPU_VEC_BASE nasys_vector_table +CFG_NIOS_CPU_VEC_SIZE nasys_vector_table_size +CFG_NIOS_CPU_VEC_NUMS +CFG_NIOS_CPU_RST_VECT nasys_reset_address +CFG_NIOS_CPU_DBG_CORE nasys_debug_core +CFG_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes +CFG_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size +CFG_NIOS_CPU_ROM_BASE na_boot_monitor_rom +CFG_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size +CFG_NIOS_CPU_OCI_BASE nasys_oci_core +CFG_NIOS_CPU_OCI_SIZE +CFG_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem + nasys_data_mem +CFG_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size + nasys_data_mem_size +CFG_NIOS_CPU_SDRAM_BASE na_sdram +CFG_NIOS_CPU_SDRAM_SIZE na_sdram_size +CFG_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash + nasys_am29lv065d_flash_0 + nasys_flash_0 +CFG_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size + +T I M E R N I O S S D K [3] +------------------------------------------------------------------------------- +CFG_NIOS_CPU_TIMER_NUMS nasys_timer_count +CFG_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9] +CFG_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq +CFG_NIOS_CPU_TIMER[0-9]_PER [ptf]:period + [ptf]:period_units + [ptf]:mult +CFG_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run +CFG_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period +CFG_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot + +U A R T N I O S S D K [2] +------------------------------------------------------------------------------- +CFG_NIOS_CPU_UART_NUMS nasys_uart_count +CFG_NIOS_CPU_UART[0-9] nasys_uart_[0-9] +CFG_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq +CFG_NIOS_CPU_UART[0-9]_BR [ptf]:baud +CFG_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits +CFG_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits +CFG_NIOS_CPU_UART[0-9]_PA [ptf]:parity +CFG_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts +CFG_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register + +P I O N I O S S D K [4] +------------------------------------------------------------------------------- +CFG_NIOS_CPU_PIO_NUMS nasys_pio_count +CFG_NIOS_CPU_PIO[0-9] nasys_pio_[0-9] +CFG_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq +CFG_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width +CFG_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri + [ptf]:has_out + [ptf]:has_in +CFG_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture +CFG_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type +CFG_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type + +S P I N I O S S D K [6] +------------------------------------------------------------------------------- +CFG_NIOS_CPU_SPI_NUMS nasys_spi_count +CFG_NIOS_CPU_SPI[0-9] nasys_spi_[0-9] +CFG_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq +CFG_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits +CFG_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster +CFG_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves +CFG_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock +CFG_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay +CFG_NIOS_CPU_SPI[0-9]_* [ptf]:* + +I D E N I O S S D K +------------------------------------------------------------------------------- +CFG_NIOS_CPU_IDE_NUMS nasys_usersocket_count +CFG_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9] + +A S M I N I O S S D K [5] +------------------------------------------------------------------------------- +CFG_NIOS_CPU_ASMI_NUMS nasys_asmi_count +CFG_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9] +CFG_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq + +E t h e r n e t ( L A N ) N I O S S D K +------------------------------------------------------------------------------- +CFG_NIOS_CPU_LAN_NUMS +CFG_NIOS_CPU_LAN[0-9]_BASE na_lan91c111 +CFG_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET +CFG_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq +CFG_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH +CFG_NIOS_CPU_LAN[0-9]_TYPE + +s y s t e m c o m p o s i n g N I O S S D K +------------------------------------------------------------------------------- +CFG_NIOS_CPU_TICK_TIMER (na_low_priority_timer2) +CFG_NIOS_CPU_USER_TIMER (na_timer1) +CFG_NIOS_CPU_BUTTON_PIO (na_button_pio) +CFG_NIOS_CPU_LCD_PIO (na_lcd_pio) +CFG_NIOS_CPU_LED_PIO (na_led_pio) +CFG_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio) +CFG_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio) +CFG_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio) +CFG_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio) +CFG_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio) +CFG_NIOS_CPU_USER_SPI (na_spi) + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/ds/ds_nioscpu.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf +[6] http://www.altera.com/literature/ds/ds_nios_spi.pdf +[7] http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf + + +=============================================================================== +Stephan Linz diff --git a/doc/README.nios_DK b/doc/README.nios_DK new file mode 100644 index 0000000..b119d76 --- /dev/null +++ b/doc/README.nios_DK @@ -0,0 +1,192 @@ + +=============================================================================== + H A R D W A R E O V E R V I E W +=============================================================================== +===============|===============|===============|===============|=============== + | DK20K200 | DK1C20 | DK1S10 | DK1S40 +---------------|---------------|---------------|---------------|--------------- + | | | | + Schem. Nr. | Nios Dev.Brd. | P06-08713-00 | P06-08468-01 | P06-09178-00 + Rev. | pilot. | 01 | 01 | 00 + Date | 2001/02/06 | 2003/02/20 | 2003/02/14 | 2003/05/14 +[1] | | | | +===============|===============|===============|===============|=============== + | | | | + FPGA | "APEX" | "Cyclon" | "Stratix" | "Stratix" + | EP20K200E | EP1C20 | EP1S10 | EP1S40 + | | | + | (484 FBGA) | (400 FBGA) | (780 FBGA) +[2],[3],[4] | | | +---------------|---------------|---------------|---------------|--------------- + | | + Clock (OSC) | 33.333 MHz | 50 MHz + | | (with ext. supply) + | + | PI49FCT3805 +[5] | +---------------|---------------|---------------|---------------|--------------- + | | + Flash | 1 MByte | 8 MByte + | | + | AM29LV800BB | AM29LV065DU120REI + | 8/16 bit bus | 8 bit bus + | 1 chip | 1 chip +[6],[7] | | +---------------|---------------|---------------|---------------|--------------- + | | | + serial | no such | 4 MBits | no such + Flash | | | + | | EPCS4SI8 | +[8] | | | +---------------|---------------|---------------|---------------|--------------- + | | + Compact | no such, as | see below: prototype adapter + Flash (CF) | module only | + | | +---------------|---------------|---------------|---------------|--------------- + | | + SRAM | 256 KByte | 1 MByte + | | + | IDT71V016S | IDT71V416S10PH + | 32 bit bus | 32 bit bus + | 2 chips | 2 chips + | interlaced | interlaced +[9],[10] | | +---------------|---------------|---------------|---------------|--------------- + | | + SDRAM | SODIMM only | 16 MByte + | | + | | MT48LC4M32B2TG-7 + | 64 bit bus | 32 bit bus + | | 1 chip +[11] | | +===============|===============|===============|===============|=============== + | | + serial I/O | 1 RS232 | 2 RS232 + | | + | LTC1386 | MAX3237CAI + | | + | port 1: | port 1: + | RxD / TxD, | RxD / TxD, + | RTS / CTS | RTS / CTS, DTR / DSR, DCD, RI + | | + | ! ! ! ! ! ! | port 2: | port 2: + | RTS/CTS can | RxD / TxD | RxD / TxD + | be RxD/TxD | | RTS / CTS, DTR / DSR + | of 2nd port | | DCD, RI +[12],[13] | ! ! ! ! ! ! | | +---------------|---------------|---------------|---------------|--------------- + | | + Ethernet | no such, as | 1 10BaseT / 100BaseT + | module only | + | | LAN91C111-NE + | | 32 bit bus + | | no external EEPROM + | | LEDA# for link + | | LEDB# for Rx / Tx +[14] | | +===============|===============|===============|===============|=============== + | | + user | 8 | no such + switches | SW[7..0] | + | | +---------------|---------------|---------------|---------------|--------------- + | + user push | 4 + buttons | PB[3..0] + | +---------------|---------------|---------------|---------------|--------------- + | | + user LEDs | 2 | 8 + | LED[1..0] | LED[7..0] + | | +---------------|---------------|---------------|---------------|--------------- + | + user seven | 2 + segment | HEX[1..0][G..A,DP] + | +===============|===============|===============|===============|=============== + | | + 3.3V proto- | w/o level | no such -- only 5V + type adapter | shift buffer | + | | + | 40 I/O pins | + | 1 card sel. | + | 1 reset out. | + | 1 OSC clock | + | 1 CPU clock | + | 1 clock out. | + | | +---------------|---------------|---------------|---------------|--------------- + | | + 5V prototype | with level | 2 ports -- both card ports supplied with its + adapter | shift buffer | own level shift buffer + | | + | 40 I/O pins | port 1 & 2: + | 1 card sel. | 41 I/O pins + | 1 Vee ? ? ? | 1 card select + | 1 reset out. | 1 reset output (from dev/board) + | 1 OSC clock | 1 OSC clock (from dev/board) + | 1 CPU clock | 1 CPU clock (from dev/board) + | 1 clock inp. | 1 clock input (to dev/board) + | | + | | (special) port 1: + | | 1 CF select + | | 1 CF present + | | 1 CF ATA select + | | 1 CF power + | | + | | NOTE: Both card ports are prepared for raw + | | IDE working. You can connect such + | | devices directly to the 40 pin header. + | | The signal PDIAG (passed diagnostic) + | | is not connected to any I/O signal. + | | Card port 1 is hard wired to the on + | | board Copact Flash adapter together + | | with all other signals needed by CF + | | cards. Hot plug should be working too. +[15],[16] | | +===============|===============|===============|===============|=============== + | | + config. CPLD | EPM7064 | EPM7128 + | | + (alternative | decition by | decision by + FPGA conf.) | jumper | push button + | | + | FPGA config. | FPGA config. | FPGA config. + | from Flash | from Flash | from Flash + | only | and EPCS4 | only + | | | +===============|===============|===============|===============|=============== +=============================================================================== + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/lit-nio.jsp +[2] http://www.altera.com/literature/lit-apx.jsp +[3] http://www.altera.com/literature/lit-cyc.jsp +[4] http://www.altera.com/literature/lit-stx.jsp +[5] http://www.pericom.com/pdf/datasheets/PI49FCT3805.pdf + http://www.pericom.com/products/clock/psempart.php?productID=PI49FCT3805 +[6] http://www.amd.com/us-en/FlashMemory/ProductInformation/0,,37_1447_1623_1468^1532,00.html + http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21490.pdf +[7] http://www.amd.com/us-en/FlashMemory/ProductInformation/0,,37_1447_1623_1468^1596,00.html + http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/23544b.pdf +[8] http://www.altera.com/literature/lit-config.html + http://preview.altera.com/literature/ds/micron.pdf +[9] http://www.idt.com/products/pages/Asynchronous_SRAMs-71V016SA.html +[10] http://www.idt.com/products/pages/Asynchronous_SRAMs-71V416SL.html +[11] http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC4M32B2TG-7 +[12] http://www.linear.com/prod/datasheet.html?datasheet=33 + http://www.linear.com/pdf/1386fa.pdf +[13] http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1068/ln/en + http://pdfserv.maxim-ic.com/en/ds/MAX3222-MAX3241.pdf +[14] http://www.smsc.com/main/catalog/lan91c111.html +[15] http://www.t13.org/index.html +[16] http://www.compactflash.org/faqs/faq.htm + + +=============================================================================== +Stephan Linz diff --git a/doc/README.ns9750dev b/doc/README.ns9750dev new file mode 100644 index 0000000..2991440 --- /dev/null +++ b/doc/README.ns9750dev @@ -0,0 +1,36 @@ +U-Boot Port to the NS9750 DevKit from NetSilicon + +1 Overview +2 Board Configuration +3 Installation + + +1 Overview +---------- + +This port supports these NS9750 features. + +o one UART + +2 Board Configuration +--------------------- + +Switches: +SW10: 4 +SW11: 6,7 +SW16: 6,7,8 +SW17-SW20: 1 +SW4: 3, 6 +SW 1: 1 +SW2: 4 +SW3: 3 +SW8: 3 (rotated by 180 degree!!!!) + +Serial Console is Port B (bottom right port) + +3 Installation +-------------- + +Have fun, +-- +Markus Pietrek diff --git a/doc/README.ocotea b/doc/README.ocotea new file mode 100644 index 0000000..9ac3a18 --- /dev/null +++ b/doc/README.ocotea @@ -0,0 +1,73 @@ + AMCC Ocotea Board + + Last Update: March 2, 2004 +======================================================================= + +This file contains some handy info regarding U-Boot and the AMCC +Ocotea 440gx evalutation board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Here's what I've been using successfully. If you feel inclined to +change things ... please read the docs! + +DIPSW U46 U80 +------------------------ +SW 1 off off +SW 2 on off +SW 3 off off +SW 4 off off +SW 5 off off +SW 6 on on +SW 7 on off +SW 8 on off + +J41: strapped +J42: open + +All others are factory default. + + +I2C Information +===================== + +See README.ebony for information. + +PCI +=========================== + +Untested at the time of writing. + +PPC440GX Ethernet EMACs +=========================== + +All EMAC ports have been tested and are known to work +with EPS Group 4. + +Special note about the Cicada CIS8201: + The CIS8201 Gigabit PHY comes up in GMII mode by default. + One must hit an extended register to allow use of RGMII mode. + This has been done in the 440gx_enet.c file with a #ifdef/endif + pair. + +AMCC does not store the EMAC ethernet addresses within their PIBS bootloader. +The addresses contained in the config header file are from my particular +board and you _*should*_ change them to reflect your board either in the +config file and/or in your environment variables. I found the addresses on +labels on the bottom side of the board. + + +BDI2k or JTAG Debugging +=========================== + +For ease of debugging you can swap the small boot flash and external SRAM +by changing U46:3 to on. You can then use the sram as your boot flash by +loading the sram via the jtag debugger. + + +Regards, +--Travis + diff --git a/doc/README.ocotea-PIBS-to-U-Boot b/doc/README.ocotea-PIBS-to-U-Boot new file mode 100644 index 0000000..25dd2a2 --- /dev/null +++ b/doc/README.ocotea-PIBS-to-U-Boot @@ -0,0 +1,99 @@ +------------------------------------------ +Installation of U-Boot using PIBS firmware +------------------------------------------ + +This document describes how to install U-Boot on the Ocotea PPC440GX +Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the +soldered FLASH. After this you should be able to switch between PIBS and +U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before +continuing. + +Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu +program. See the hints for configuring cu above. Make sure you can +communicate with the PIBS firmware: reset the board and hit ENTER a couple of +times until you see the PIBS prompt (PIBS $). Then proceed as follows: + + +Read MAC Addresses from PIBS +---------------------------- + +To read the configured MAC addresses available on your Ocotea board please use +the following commands: + +PIBS $ echo $hwdaddr0 +000173017FE3 +PIBS $ echo $hwdaddr1 +000173017FE4 +PIBS $ echo $hwdaddr2 +000173017FE1 +PIBS $ echo $hwdaddr3 +000173017FE2 + +In U-Boot this is stored in the following environment variables: + +* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3) +* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4) +* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1) +* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2) + + +Configure the network interface (ent0 == emac0) +----------------------------------------------- + +To download the U-Boot image we need to configure the ethernet interface with +the following commands: + +PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up +PIBS $ set ipdstaddr0=192.168.1.1 +status: writing PIBS variable value to FLASH +PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin +status: writing PIBS variable value to FLASH + +Please insert correct parameters for your configuration (ip-addresses and +file-location). + + +Program U-Boot into soldered User-FLASH +--------------------------------------- + +Please make sure to use a newer version of U-Boot (at least 1.1.3), since +older versions don't support running from user-FLASH. + +To program U-Boot into the soldered user-FLASH use the following command: + +PIBS $ storefile bin eth 0xffbc0000 + +This commands loads the file vis ethernet into ram and copies it into the +user-FLASH. + + +Switch to U-Boot +---------------- + +Now you can turn your board off and switch SW1 (U46) to on (= closed). After +powering the board you should see the following message: + +U-Boot 1.1.3 (Apr 5 2005 - 22:59:57) + +AMCC PowerPC 440 GX Rev. C +Board: AMCC 440GX Evaluation Board + VCO: 1066 MHz + CPU: 533 MHz + PLB: 152 MHz + OPB: 76 MHz + EPB: 76 MHz +I2C: ready +DRAM: 256 MB +FLASH: 5 MB +PCI: Bus Dev VenId DevId Class Int +In: serial +Out: serial +Err: serial +KGDB: kgdb ready +ready +Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3 +BEDBUG:ready +=> + + +April 06 2005, Stefan Roese diff --git a/doc/README.omap730p2 b/doc/README.omap730p2 new file mode 100644 index 0000000..7c70916 --- /dev/null +++ b/doc/README.omap730p2 @@ -0,0 +1,91 @@ + + u-boot for the TI OMAP730 Perseus2 + + Dave Peverley, MPC-Data Limited + http://www.mpc-data.co.uk + + +Overview : + + As the OMAP730 is similar to the OMAP1610 in many ways, this port was based +on the u-boot port to the OMAP1610 Innovator. Supported features are : + + - Serial terminal support + - Onboard NOR Flash + - Ethernet via the seperate debug board + - Tested on Rev4 and Rev5 boards + + It has also been tested to work correctly when built with a 'standard' GCC +3.2.1 cross-compiler as well as Montavista Linux CEE 3.1's toolchain. + + +Hardware Configuration : + + The main dips on the P2 board should be set to 2,3,7 and 9 on with all +others off. On the debug board, dips 1 and 7 should be on with the rest off. +The serial console has been set up to run from the DB9 connector on the +P2 board at 115200 baud, 8 data bits, no stop bits, 1 parity bit. + + It should be noted that the P2 board has NOR flash that is addressable via +either CS0 or CS3. This mode can be changed via DIP9 on the P2 board. + + +Installing u-boot for the P2 : + + You can simply build u-boot for the Perseus by following the instructions +in the main readme file. The target configuration is "omap730p2_config". +Once u-boot has been built, you should strip the executable so it can be +loaded via CCS (which cant cope with the symbols in the ELF binary) : + $ cp u-boot u-boot.out + $ arm-linux-strip u-boot.out + + The method we've used for installing u-boot the first time on a P2 is +as follows : + +1) Configure TI Code Composer Studio to connect to the P2 board via JTAG + as described in the Users Guide. + +2) Set up the P2 to boot from CS3, and connect with CCS. Reset the CPU + and run the "init_mmu" GEL script. + +3) Use the "Load Program" option to send the u-boot.out file to the P2 and + run. + + At this point, u-boot should run and you will see the boot menu on your +serial terminal. You can then load the u-boot image to memory : + + # loadb 0x10000000 + + Send the "u-boot.bin" binary via the serial using Kermit. Once loaded +you can self-flash u-boot : + + # protect off 1:0 + # erase 1:0 + # cp.b 0x10000000 0x0 0x20000 + + You should now be able to reset the board and run u-boot from flash. + + +Alternative flash option : + + Sometimes, if you've been silly, you can get the board into a state where +whats in flash has upset the board so much that you can no longer connect +to the P2 via JTAG. However, you can set DIP9 to off to swap the boot mode +of the P2 so that you boot from RAM instead of NOR flash. This moves NOR +flash up to 0x0C000000. You can build a special version of u-boot to +utilise this by the following config : + + $ make omap730p2_cs0boot_config + + If you load this up via CCS it will detect flash at its alternate location +and allow you to programme your u-boot image (which, remember must be built +for CS3 boot!) Once you do this, you can revert to CS3 boot and it will work +fine again. + + +Errata : + +1) It's been observed that sometimes the tftp transfer of kernels to the + board can have checksum errors or stall. This appears to be an issue + with the lan91c96.c driver, and can normally be worked around by + resetting the board and trying again. diff --git a/doc/README.ppc440 b/doc/README.ppc440 new file mode 100644 index 0000000..08f34f5 --- /dev/null +++ b/doc/README.ppc440 @@ -0,0 +1,202 @@ + PowerPC 440 + + Last Update: September 11, 2002 +======================================================================= + + +OVERVIEW +============ + +Support for the ppc440 is contained in the cpu/ppc44x directory +and enabled via the CONFIG_440 flag. It is largely based on the +405gp code. A sample board support implementation is contained +in the board/ebony directory. + +All testing was performed using the AMCC Ebony board using both +Rev B and Rev C silicon. However, since the Rev B. silicon has +extensive errata, support for Rev B. is minimal (it boots, and +features such as i2c, pci, tftpboot, etc. seem to work ok). +The expectation is that all new board designs will be using +Rev C or later parts -- if not, you may be in for a rough ride ;-) + +The ppc440 port does a fair job of keeping "board-specific" code +out of the "cpu-specific" source. The goal of course was to +provide mechanisms for each board to customize without having +to clutter the cpu-specific source with a lot of ifdefs. Most +of these mechanisms are described in the following sections. + + +MEMORY MANAGEMENT +================= + +The ppc440 doesn't run in "real mode". The MMU must be active +at all times. Additionally, the 440 implements a 36-bit physical +memory space that gets mapped into the PowerPC 32-bit virtual +address space. So things like memory-mapped peripherals, etc must +all be mapped in. Once this is done, the 32-bit virtual address +space is then viewed as though it were physical memory. + +However, this means that memory, peripherals, etc can be configured +to appear (mostly) anywhere in the virtual address space. Each board +must define its own mappings using the tlbtab (see board/ebony/init.S). +The actual TLB setup is performed by the cpu-specific code. + +Although each board is free to define its own mappings, there are +several definitions to be aware of. These definitions may be used in +the cpu-specific code (vs. board-specific code), so you should +at least review these before deciding to make any changes ... it +will probably save you some headaches ;-) + +CFG_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0) + +CFG_FLASH_BASE - The virtual address where FLASH is mapped. + +CFG_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped. + This mapping provides access to PCI-bus memory. + +CFG_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped + peripherals are mapped. (e.g. -- UART registers, IIC registers, etc). + +CFG_ISRAM_BASE - The virtual address where the 440 internal SRAM is + mapped. The internal SRAM is equivalent to 405gp OCM and is used + for the initial stack. + +CFG_PCI_BASE - The virtual address where the 440 PCI-x bridge config + registers are mapped. + +CFG_PCI_TARGBASE - The PCI address that is mapped to the virtual address + defined by CFG_PCI_MEMBASE. + + +UART / SERIAL +================= + +The UART port works fine when an external serial clock is provided +(like the one on the Ebony board) and when using internal clocking. +This is controlled with the CFG_EXT_SERIAL_CLOCK flag. When using +internal clocking, the "ideal baud rate" settings in the 440GP +user manual are automatically calculated. + +CONFIG_SERIAL_SOFTWARE_FIFO enables interrupt-driven serial operation. +But the last time I checked, interrupts were initialized after the +serial port causing the interrupt handler to be removed from the +handler table. This will probably be fixed soon ... or fix it +yourself and submit a patch :-) + + +I2C +================= + +The i2c utilities have been tested on both Rev B. and Rev C. and +look good. The iprobe command implementation has been updated to +allow for 'skipped' addresses. Some i2c slaves are write only and +cause problems when a probe (read) is performed (for example the +CDCV850 clock controller at address 0x69 on the ebony board). + +To prevent probing certain addresses you can define the +CFG_I2C_NOPROBES macro in your board-specific header file. When +defined, all specified addresses are skipped during a probe. +The addresses that are skipped will be displayed in the output +of the iprobe command. + +For example, to prevent probing address 0x69, define the macro as +follows: + +#define CFG_I2C_NOPROBES {0x69} + +Similarly, to prevent probing addresses 0x69 and 0x70, define the +macro a: + +#define CFG_I2C_NOPROBES {0x69, 0x70} + + +DDR SDRAM CONTROLLER +==================== + +SDRAM controller intialization using Serial Presence Detect (SPD) is +now supported (thanks Jun). It is enabled by defining CONFIG_SPD_EEPROM. +The i2c eeprom addresses are controlled by the SPD_EEPROM_ADDRESS macro. + +NOTE: The SPD_EEPROM_ADDRESS macro is defined differently than for other +processors. Traditionally, it defined a single address. For the 440 it +defines an array of addresses to support multiple banks. Address order +is significant: the addresses are used in order to program the BankN +registers. For example, two banks with i2c addresses of 0x53 (bank 0) +and 0x52 (bank 1) would be defined as follows: + +#define SPD_EEPROM_ADDRESS {0x53,0x52} + + +PCI-X BRIDGE +==================== + +PCI is an area that requires lots of flexibility since every board has +its own set of constraints and configuration. This section describes the +440 implementation. + +CPC0_STRP1[PISE] -- if the PISE strap bit is not asserted, PCI init +is aborted and an indication is printed. This is NOT considered an +error -- only an indication that PCI shouldn't be initialized. This +gives you a chance to edit the i2c bootstrap eeproms using the i2c +utilities once you get to the U-Boot command prompt. NOTE: the default +440 bootstrap options (not using i2c eeprom) negates this bit. + +The cpu-specific code sets up a default pci_controller structure +that maps in a single PCI I/O space and PCI memory space. The I/O +space begins at PCI I/O address 0 and the PCI memory space is +256 MB starting at PCI address CFG_PCI_TARGBASE. After the +pci_controller structure is initialized, the cpu-specific code will +call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is +defined. This routine is implemented by board-specific code & is where +the board can over-ride/extend the default pci_controller structure +settings and do other pre-initialization tasks. If pci_pre_init() +returns a value of zero, PCI initialization is aborted; otherwise the +controller structure is registered and initialization continues. + +The default 440GP PCI target configuration is minimal -- it assumes that +the strapping registers are set as necessary. Since the strapping bits +provide very limited flexibility, you may want to customize the boards +target configuration. If CFG_PCI_TARGET_INIT is defined, the cpu-specific +code will call the routine pci_target_init() which you must implement +in your board-specific code. + +Target initialization is completed by the cpu-specific code by +initializing the subsystem id and subsystem vendor id, and then ensuring +that the 'enable host configuration' bit in the PCIX0_BRDGOPT2 is set. + +The default PCI master initialization maps in 256 MB of pci memory +starting at PCI address CFG_PCI_MEMBASE. To customize this, define +PCI_MASTER_INIT. This will call the routine pci_master_init() in your +board-specific code rather than performing the default master +initialization. + +The decision to perform PCI host configuration must often be determined +at run time. The ppc440 port differs from most other implementations in +that it requires the board to determine its host configuration at run +time rather than by using compile-time flags. This shouldn't create a +large impact on the board-specific code since the board only needs to +implement a single routine that returns a zero or non-zero value: +is_pci_host(). + +Justification for this becomes clear when considering systems running +in a cPCI environment: + +1. Arbiter strapping: Many cPCI boards provide an external arbiter (often +part of the PCI-to-PCI bridge). Even though the arbiter is external (the +arbiter strapping is negated), the CPU may still be required to perform +local PCI bus configuration. + +2. Host only: PPMC boards must sample the MONARCH# signal at run-time. +Depending on the configuration of the carrier boar, the PPMC board must +determine if it should configure the PCI bus at run-time. And in most +cases, access to the MONARCH# signal is board-specific (e.g. via +board-specific FPGA registers, etc). + +In any event, the is_pci_host() routine gives each board the opportunity +to decide at run-time. If your board is always configured a certain way, +then just hardcode a return of 1 or 0 as appropriate. + + +Regards, +--Scott + diff --git a/doc/README.sbc8560 b/doc/README.sbc8560 new file mode 100644 index 0000000..52592e3 --- /dev/null +++ b/doc/README.sbc8560 @@ -0,0 +1,53 @@ +The port was tested on Wind River System Sbc8560 board . +U-Boot was installed on the flash memory of the CPU card (no the SODIMM). + +NOTE: Please configure uboot compile to the proper PCI frequency and +setup the appropriate DIP switch settings. + +SBC8560 board: + +Make sure boards switches are set to their appropriate conditions. +Refer to the Engineering Reference Guide ERG-00300-002. Of particular +importance are: 1)Tthe settings for JP4 (JP4 1-3 and 2-4), which +select the on-board FLASH device (Intel 28F128Jx); 2) The settings +for the Clock SW9 (33 MHz or 66 MHz). + + Note: SW9 Settings: 66 MHz + 4:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on + Note: SW9 Settings: 33 MHz + 8:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on + + +Flashing the FLASH device with the "Wind River ICE": + +1) Properly connect and configure the Wind River ICE to the + target JTAG port. This includes running the SBC8560 register script. + Make sure target memory can be read and written. + +2) Build the u-boot image: + make distclean + make SBC8560_66_config or SBC8560_33_config + make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all + + Note: reference is made to the ELDK3.0 compiler but any 85xx cross-compiler + should suffice. + +3) Convert the uboot (.elf) file to a uboot.bin file (using visionClick converter). + The bin file should be converted from fffc0000 to ffffffff + +4) Setup the Flash Utility (tools menu) for: + + Determine the clock speed of the PCI bus and set SW9 accordingly + Note: the speed of the PCI bus defaults to the slowest PCI card + PlayBack the "default" register file for the SBC8560 + Select the uboot.bin file with zero bias + Select the initialize Target prior to programming + Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm + Select the erase base address from FFFC0000 to FFFFFFFF + Select the start address from 0 with size of 4000 + +5) Erase and Program diff --git a/doc/README.sched b/doc/README.sched new file mode 100644 index 0000000..3aa89e6 --- /dev/null +++ b/doc/README.sched @@ -0,0 +1,53 @@ +Notes on the scheduler in sched.c: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + 'sched.c' provides an very simplistic multi-threading scheduler. + See the example, function 'sched(...)', in the same file for its + API usage. + + Until an exhaustive testing can be done, the implementation cannot + qualify as that of production quality. It works with the example + in 'sched.c', it may or may not work in other cases. + + +Limitations: +~~~~~~~~~~~~ + + - There are NO primitives for thread synchronization (locking, + notify etc). + + - Only the GPRs and FPRs context is saved during a thread context + switch. Other registers on the PowerPC processor (60x, 7xx, 7xxx + etc) are NOT saved. + + - The scheduler is NOT transparent to the user. The user + applications must invoke thread_yield() to allow other threads to + scheduler. + + - There are NO priorities, and the scheduling policy is round-robin + based. + + - There are NO capabilities to collect thread CPU usage, scheduler + stats, thread status etc. + + - The semantics are somewhat based on those of pthreads, but NOT + the same. + + - Only seven threads are allowed. These can be easily increased by + changing "#define MAX_THREADS" depending on the available memory. + + - The stack size of each thread is 8KBytes. This can be easily + increased depending on the requirement and the available memory, + by increasing "#define STK_SIZE". + + - Only one master/parent thread is allowed, and it cannot be + stopped or deleted. Any given thread is NOT allowed to stop or + delete itself. + + - There NOT enough safety checks as are probably in the other + threads implementations. + + - There is no parent-child relationship between threads. Only one + thread may thread_join, preferably the master/parent thread. + +(C) 2003 Arun Dharankar diff --git a/doc/README.serial_multi b/doc/README.serial_multi new file mode 100644 index 0000000..a8d48fc --- /dev/null +++ b/doc/README.serial_multi @@ -0,0 +1,54 @@ +The support for multiple serial interfaces as implemented is mainly +intended to allow for modem dial-in / dial-out while still being able +to use a serial console on a (different) serial port. + +MPC8XX Specific +=============== +At the moment, the ports must be split on a SMC and a SCC port on a +8xx processor; other configurations are not (yet) supported. + +Support for hardware handshake has not been implemented yet (but is +in the works). + +*) The default console depends on the keys pressed: + - SMC if keys not pressed (modem not enabled) + - SCC if keys pressed (modem enabled) + +*) The console can be switched to SCC by any of the following commands: + + setenv stdout serial_scc + setenv stdin serial_scc + setenv stderr serial_scc + +*) The console can be switched to SMC by any of the following commands: + + setenv stdout serial_smc + setenv stdin serial_smc + setenv stderr serial_smc + +*) If a file descriptor is set to "serial" then the current serial device +will be used which, in turn, can be switched by above commands. + +*) The baudrate is the same for all serial devices. But it can be switched +just after switching the console: + + setenv sout serial_scc; setenv baudrate 38400 + +After that press 'enter' at the SCC console. Note that baudrates <38400 +are not allowed on LWMON with watchdog enabled (see CFG_BAUDRATE_TABLE in +include/configs/lwmon.h). + + +PPC4XX Specific +=============== +*) The default console is UART0 + +*) The console can be switched to UART1 by any of the following commands: + setenv stdout serial1 + setenv stderr serial1 + setenv stdin serial1 + +*) The console can be switched to UART0 by any of the following commands: + setenv stdout serial0 + setenv stderr serial0 + setenv stdin serial0 diff --git a/doc/README.silent b/doc/README.silent new file mode 100644 index 0000000..6772532 --- /dev/null +++ b/doc/README.silent @@ -0,0 +1,20 @@ +The config option CONFIG_SILENT_CONSOLE can be used to quiet messages +on the console. If the option has been enabled, the output can be +silenced by setting the environment variable "silent". The variable +is latched into the global data at an early stage in the boot process +so deleting it with "setenv" will not take effect until the system is +restarted. + +The following actions are taken if "silent" is set at boot time: + + - Until the console devices have been initialized, output has to be + suppressed by testing for the flag "GD_FLG_SILENT" in "gd->flags". + + - When the console devices have been initialized, "stdout" and + "stderr" are set to "nulldev", so subsequent messages are + suppressed automatically. Make sure to enable "nulldev" by + #defining CFG_DEVICE_NULLDEV in your board config file. + + - When booting a linux kernel, the "bootargs" are fixed up so that + the argument "console=" will be in the command line, no matter how + it was set in "bootargs" before. diff --git a/doc/README.standalone b/doc/README.standalone new file mode 100644 index 0000000..3998831 --- /dev/null +++ b/doc/README.standalone @@ -0,0 +1,96 @@ +Design Notes on Exporting U-Boot Functions to Standalone Applications: +====================================================================== + +1. The functions are exported by U-Boot via a jump table. The jump + table is allocated and initialized in the jumptable_init() routine + (common/exports.c). Other routines may also modify the jump table, + however. The jump table can be accessed as the 'jt' field of the + 'global_data' structure. The slot numbers for the jump table are + defined in the header. E.g., to substitute the + malloc() and free() functions that will be available to standalone + applications, one should do the following: + + DECLARE_GLOBAL_DATA_PTR; + + gd->jt[XF_malloc] = my_malloc; + gd->jt[XF_free] = my_free; + + Note that the pointers to the functions all have 'void *' type and + thus the compiler cannot perform type checks on these assignments. + +2. The pointer to the jump table is passed to the application in a + machine-dependent way. PowerPC, ARM and MIPS architectures use a + dedicated register to hold the pointer to the 'global_data' + structure: r29 on PowerPC, r8 on ARM and k0 on MIPS. The x86 + architecture does not use such a register; instead, the pointer to + the 'global_data' structure is passed as 'argv[-1]' pointer. + + The application can access the 'global_data' structure in the same + way as U-Boot does: + + DECLARE_GLOBAL_DATA_PTR; + + printf("U-Boot relocation offset: %x\n", gd->reloc_off); + +3. The application should call the app_startup() function before any + call to the exported functions. Also, implementor of the + application may want to check the version of the ABI provided by + U-Boot. To facilitate this, a get_version() function is exported + that returns the ABI version of the running U-Boot. I.e., a + typical application startup may look like this: + + int my_app (int argc, char *argv[]) + { + app_startup (argv); + if (get_version () != XF_VERSION) + return 1; + } + +4. The default load and start addresses of the applications are as + follows: + + Load address Start address + x86 0x00040000 0x00040000 + PowerPC 0x00040000 0x00040004 + ARM 0x0c100000 0x0c100000 + MIPS 0x80200000 0x80200000 + + For example, the "hello world" application may be loaded and + executed on a PowerPC board with the following commands: + + => tftp 0x40000 hello_world.bin + => go 0x40004 + +5. To export some additional function foobar(), the following steps + should be undertaken: + + - Append the following line at the end of the include/_exports.h + file: + + EXPORT_FUNC(foobar) + + - Add the prototype for this function to the include/exports.h + file: + + void foobar(void); + + - Add the initialization of the jump table slot wherever + appropriate (most likely, to the jumptable_init() function): + + gd->jt[XF_foobar] = foobar; + + - Increase the XF_VERSION value by one in the include/exports.h + file + +6. The code for exporting the U-Boot functions to applications is + mostly machine-independent. The only places written in assembly + language are stub functions that perform the jump through the jump + table. That said, to port this code to a new architecture, the + only thing to be provided is the code in the examples/stubs.c + file. If this architecture, however, uses some uncommon method of + passing the 'global_data' pointer (like x86 does), one should add + the respective code to the app_startup() function in that file. + + Note that these functions may only use call-clobbered registers; + those registers that are used to pass the function's arguments, + the stack contents and the return address should be left intact. diff --git a/doc/README.stxxtc b/doc/README.stxxtc new file mode 100644 index 0000000..7d9d4d3 --- /dev/null +++ b/doc/README.stxxtc @@ -0,0 +1,59 @@ + + +First, some build notes on the Silicon Turnkey eXpress XTc. + +This board has both 87x/88x procesor options at various +frequencies. The configuration file has some macros for setting +the clock speed, not all have been tested. They all have +a 10MHz input clock. Please do not check in a configuration +file that selects a high speed not available on all processors. +We chose the 66MHz core and bus speed, which should be OK on +all boards. If you have a processor, lucky you! :-) +Just build a new configuration with that speed, check +the macro configuration to ensure it's correct. If the +macro is updated, please check that in, but keep default +processor speed. + +The board is likely to have more than 1Mbyte of NOR boot flash. +It was also configured with a high boot vector (Dan's fault) +so the standard 8xx mapping doesn't work well. We had to move +the addresses around a little bit so one copy would work. The +flash got fragmented, and we are working on a better solution. +There is an "xtc.cfg" floating around for the BDI2000, use +that for programming a new version of U-Boot. You can probably +find it on the Silicon Turnkey eXpress (www.silicontkx.com), +Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de) +servers. + +The board will also have various SDRAM sizes, but the code +should automatically determine the amount of memory. + +There are a couple of different board versions, visually +they use different BGA or surface mount memory parts. However, +they are logically the same board. + +Now, some operational notes. + +The board has the option of sporting two FEC Ethernet ports. +The second port isn't configured to be automatically available +because it would cause U-Boot to generate a board data structure +(the bd_t) with multiple MAC addresses and be incompatible with +standard 8xx kernel builds. You can use/test the second FEC +in U-Boot by assigning an 'eth1addr' and selecting the second +FEC as the port to use. + +Since this is just a development board and not a product, STx +does not assign unique MAC addresses. We just pilfer the +"default" ones used by Wolfgang on some other boards. Please +ensure you assign unique MAC addresses when using these boards. + +The serial port baud rate is 38400, because that's the way +I like it :-) + +Thanks to Pantelis for lots of the work on this board port. + +Have Fun! + + -- Dan + +15 August 2005 diff --git a/doc/README.usb b/doc/README.usb new file mode 100644 index 0000000..41f76f4 --- /dev/null +++ b/doc/README.usb @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +USB Support for PIP405 and MIP405 (UHCI) +======================================== + +The USB support is implemented on the base of the UHCI Host +controller. + +Currently supported are USB Hubs, USB Keyboards and USB Floppys. +Tested with a TEAC Floppy TEAC FD-05PUB and Chicony KU-8933 Keyboard. + +How it works: +------------- + +The USB (at least the USB UHCI) needs a frame list (4k), transfer +descripor and queue headers which are all located in the main memory. +The UHCI allocates every milisecond the PCI bus and reads the current +frame pointer. This may cause to crash the OS during boot. So the USB +_MUST_ be stopped during OS boot. This is the reason, why the USB is +NOT automatically started during start-up. If someone needs the USB +he has to start it and should therefore be aware that he had to stop +it before booting the OS. + +For USB keyboards this can be done by a script which is automatically +started after the U-Boot is up and running. To boot an OS with a an +USB keyboard another script is necessary, which first disables the +USB and then executes the boot command. If the boot command fails, +the script can reenable the USB kbd. + +Common USB Commands: +- usb start: +- usb reset: (re)starts the USB. All USB devices will be + initialized and a device tree is build for them. +- usb tree: shows all USB devices in a tree like display +- usb info [dev]: shows all USB infos of the device dev, or of all + the devices +- usb stop [f]: stops the USB. If f==1 the USB will also stop if + an USB keyboard is assigned as stdin. The stdin + is then switched to serial input. +Storage USB Commands: +- usb scan: scans the USB for storage devices.The USB must be + running for this command (usb start) +- usb device [dev]: show or set current USB staorage device +- usb part [dev]: print partition table of one or all USB storage + devices +- usb read addr blk# cnt: + read `cnt' blocks starting at block `blk#'to + memory address `addr' +- usbboot addr dev:part: + boot from USB device + +Config Switches: +---------------- +CFG_CMD_USB enables basic USB support and the usb command +CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined if + using CFG_CMD_USB +CONFIG_USB_KEYBOARD enables the USB Keyboard +CONFIG_USB_STORAGE enables the USB storage devices diff --git a/doc/README.video b/doc/README.video new file mode 100644 index 0000000..c145d9b --- /dev/null +++ b/doc/README.video @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +U-Boot MPC8xx video controller driver +====================================== + +The driver has been tested with the following configurations: + +- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it +- GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it diff --git a/doc/README.xpedite1k b/doc/README.xpedite1k new file mode 100644 index 0000000..34bba13 --- /dev/null +++ b/doc/README.xpedite1k @@ -0,0 +1,82 @@ + XES XPedite1000 Board + + Last Update: December 29, 2003 +======================================================================= + +This file contains some handy info regarding U-Boot and the XES +XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Jumpers selected for AMD29LV040B flash part as the boot flash. + + +I2C Strap EEPROM & Environment Settings +======================================= + +The XPedite1000 uses a single I2C eeprom for the 440 strappings and for +the environment variables. The first page (256 bytes) contains the +strappings and the 2 EMAC HW Ethernet addresses. Be careful not to +change the 1st page of the EEPROM! Unpopulated jumper J560 can get you +out of trouble as it disables the strapping read from EEPROM. + +I2C iprobe +===================== + +The i2c utilities work and have been tested on Rev B. of the 440GX. See +README.ebony for more information about i2c probing with the 440. + + +GETTING OUT OF I2C TROUBLE +=========================== + +(Direct quote from README.ebony) +If you're like me ... you may have screwed up your bootstrap serial +eeprom ... or worse, your SPD eeprom when experimenting with the +i2c commands. If so, here are some ideas on how to get out of +trouble: + +Serial bootstrap eeprom corruption: +----------------------------------- +Power down the board and set the following straps: + +J560 - closed + +This will select the default sys0 and sys1 settings (the serial +eeproms are not used). Then power up the board and fix the serial +eeprom using the imm command. Here are the values I currently +use: + +=> imd 50 0 10 + +0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00 .}B............. + +Once you have the eeproms set correctly change the +J560 straps as you desire. + + +PPC440GX Ethernet EMACs +======================= + +The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1. PHYs are connected +only to emac 2 & 3. The HW Ethernet addresses are read from the i2c eeprom and +placed in the bd info structure for enet2addr and enet3addr. The ethernet driver +senses that enetaddr and enet1addr are 0's and does not use them. + +As of this writing gigabit ethernet and the TCPIP acceleration hardware is not +supported. + + +Flash Support +============= + +As of this writing, there is support for the 1/2mb boot flash only. User flash +is not yet supported. + + +Regards, +--Travis + diff --git a/doc/TODO-i386 b/doc/TODO-i386 new file mode 100644 index 0000000..84113f8 --- /dev/null +++ b/doc/TODO-i386 @@ -0,0 +1,29 @@ +i386 port missing features: +* i386 cleaness (wbinvld is 486+ ... ) +* Pentium TSC timer/udelay +* setup the BIOS data area and BIOS equipment word to reflect machine config. +* Make reset work (from Linux and from the boot prompt) +* DMA, FDC, RTC, KBC initialization +* split of part of cpu/i386/interrupt.c to cpu/i385/entry.c? +* re-entry of protected mode from real mode, should be added to realmode_switch.S + (and used by INT 10h and INT 16h handlers for console I/O during early + linux boot...) +* missing functions in lib_i386 and cpu/i386 +* speaker beep interface + + +SC520 missing features: +* Watchdog +* SC520 timer/udelay +* SC520 3rd PIC +* SC520 ICE serial +* SC520 MMCR reset + +SC520 CDP board support missing features: +* environment in sram + +SC520 CDP board support bugs: +* SPI EEPROM support does not work +* 0x680 LEDS dos not work for me +* is it possible to make both the internal serial ports and the + ports on the sio work at the same time? diff --git a/drivers/3c589.c b/drivers/3c589.c new file mode 100644 index 0000000..080b686 --- /dev/null +++ b/drivers/3c589.c @@ -0,0 +1,519 @@ +/*------------------------------------------------------------------------ + . 3c589.c + . This is a driver for 3Com's 3C589 (Etherlink III) PCMCIA Ethernet device. + . + . (C) Copyright 2002 + . Sysgo Real-Time Solutions, GmbH + . Rolf Offermanns + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + ----------------------------------------------------------------------------*/ + +#include +#include +#include + +#ifdef CONFIG_DRIVER_3C589 + +#include "3c589.h" + + +/* Use power-down feature of the chip */ +#define POWER_DOWN 0 + +#define NO_AUTOPROBE + +static const char version[] = + "Your ad here! :P\n"; + + +#undef EL_DEBUG + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; +/*------------------------------------------------------------------------ + . + . Configuration options, for the experienced user to change. + . + -------------------------------------------------------------------------*/ + +/* + . Wait time for memory to be free. This probably shouldn't be + . tuned that much, as waiting for this means nothing else happens + . in the system +*/ +#define MEMORY_WAIT_TIME 16 + + +#if (EL_DEBUG > 2 ) +#define PRINTK3(args...) printf(args) +#else +#define PRINTK3(args...) +#endif + +#if EL_DEBUG > 1 +#define PRINTK2(args...) printf(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef EL_DEBUG +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + +#define outb(args...) mmio_outb(args) +#define mmio_outb(value, addr) (*((volatile byte *)(addr)) = value) + +#define inb(args...) mmio_inb(args) +#define mmio_inb(addr) (*((volatile byte *)(addr))) + +#define outw(args...) mmio_outw(args) +#define mmio_outw(value, addr) (*((volatile word *)(addr)) = value) + +#define inw(args...) mmio_inw(args) +#define mmio_inw(addr) (*((volatile word *)(addr))) + +#define outsw(args...) mmio_outsw(args) +#define mmio_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + mmio_outw( *(__b2 + __i), r); \ + } \ + }) + +#define insw(args...) mmio_insw(args) +#define mmio_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = mmio_inw(r); \ + mmio_inw(0); \ + }; \ + }) + +/*------------------------------------------------------------------------ + . + . The internal workings of the driver. If you are changing anything + . here with the 3Com stuff, you should have the datasheet and know + . what you are doing. + . + -------------------------------------------------------------------------*/ +#define EL_BASE_ADDR 0x20000000 + + +/* Offsets from base I/O address. */ +#define EL3_DATA 0x00 +#define EL3_TIMER 0x0a +#define EL3_CMD 0x0e +#define EL3_STATUS 0x0e + +#define EEPROM_READ 0x0080 + +#define EL3WINDOW(win_num) mmio_outw(SelectWindow + (win_num), EL_BASE_ADDR + EL3_CMD) + +/* The top five bits written to EL3_CMD are a command, the lower + 11 bits are the parameter, if applicable. */ +enum c509cmd { + TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11, + RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, RxDiscard = 8<<11, + TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11, + FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11, + SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11, + SetTxThreshold = 18<<11, SetTxStart = 19<<11, StatsEnable = 21<<11, + StatsDisable = 22<<11, StopCoax = 23<<11, +}; + +enum c509status { + IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004, + TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, + IntReq = 0x0040, StatsFull = 0x0080, CmdBusy = 0x1000 +}; + +/* The SetRxFilter command accepts the following classes: */ +enum RxFilter { + RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 +}; + +/* Register window 1 offsets, the window used in normal operation. */ +#define TX_FIFO 0x00 +#define RX_FIFO 0x00 +#define RX_STATUS 0x08 +#define TX_STATUS 0x0B +#define TX_FREE 0x0C /* Remaining free bytes in Tx buffer. */ + + +/* + Read a word from the EEPROM using the regular EEPROM access register. + Assume that we are in register window zero. +*/ +static word read_eeprom(dword ioaddr, int index) +{ + int i; + outw(EEPROM_READ + index, ioaddr + 0xa); + /* Reading the eeprom takes 162 us */ + for (i = 1620; i >= 0; i--) + if ((inw(ioaddr + 10) & EEPROM_BUSY) == 0) + break; + return inw(ioaddr + 0xc); +} + +static void el_get_mac_addr( unsigned char *mac_addr ) +{ + int i; + union + { + word w; + unsigned char b[2]; + } wrd; + unsigned char old_window = inw( EL_BASE_ADDR + EL3_STATUS ) >> 13; + GO_WINDOW(0); + VX_BUSY_WAIT; + for (i = 0; i < 3; i++) + { + wrd.w = read_eeprom(EL_BASE_ADDR, 0xa+i); +#ifdef __BIG_ENDIAN + mac_addr[2*i] = wrd.b[0]; + mac_addr[2*i+1] = wrd.b[1]; +#else + mac_addr[2*i] = wrd.b[1]; + mac_addr[2*i+1] = wrd.b[0]; +#endif + } + GO_WINDOW(old_window); + VX_BUSY_WAIT; +} + + +#if EL_DEBUG > 1 +static void print_packet( byte * buf, int length ) +{ + int i; + int remainder; + int lines; + + PRINTK2("Packet of length %d \n", length ); + + lines = length / 16; + remainder = length % 16; + + for ( i = 0; i < lines ; i ++ ) { + int cur; + + for ( cur = 0; cur < 8; cur ++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + PRINTK2("%02x%02x ", a, b ); + } + PRINTK2("\n"); + } + for ( i = 0; i < remainder/2 ; i++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + PRINTK2("%02x%02x ", a, b ); + } + PRINTK2("\n"); +} +#endif /* EL_DEBUG > 1 */ + + +/************************************************************************** +ETH_RESET - Reset adapter +***************************************************************************/ +static void el_reset(bd_t *bd) +{ + /*********************************************************** + Reset 3Com 595 card + *************************************************************/ + /* QUICK HACK + * - adjust timing for 3c589 + * - enable io for PCMCIA */ + outw(0x0004, 0xa0000018); + udelay(100); + outw(0x0041, 0x28010000); + udelay(100); + + /* issue global reset */ + outw(GLOBAL_RESET, BASE + VX_COMMAND); + + /* must wait for at least 1ms */ + udelay(100000000); + + /* set mac addr */ + { + unsigned char *mac_addr = bd->bi_enetaddr; + int i; + + el_get_mac_addr( mac_addr ); + + GO_WINDOW(2); + VX_BUSY_WAIT; + + printf("3C589 MAC Addr.: "); + for (i = 0; i < 6; i++) + { + printf("%02x", mac_addr[i]); + outb(mac_addr[i], BASE + VX_W2_ADDR_0 + i); + VX_BUSY_WAIT; + } + printf("\n\n"); + } + + /* set RX filter */ + outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + + /* set irq mask and read_zero */ + outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE | + S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE | + S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + /* enable TP Linkbeat */ + GO_WINDOW(4); + VX_BUSY_WAIT; + + outw( ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE); + VX_BUSY_WAIT; + + +/* + * Attempt to get rid of any stray interrupts that occured during + * configuration. On the i386 this isn't possible because one may + * already be queued. However, a single stray interrupt is + * unimportant. + */ + + outw(ACK_INTR | 0xff, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + /* enable TX and RX */ + outw( RX_ENABLE, BASE + VX_COMMAND ); + VX_BUSY_WAIT; + + outw( TX_ENABLE, BASE + VX_COMMAND ); + VX_BUSY_WAIT; + + + /* print the diag. regs. */ + PRINTK2("Diag. Regs\n"); + PRINTK2("--> MEDIA_TYPE: %04x\n", inw(BASE + VX_W4_MEDIA_TYPE)); + PRINTK2("--> NET_DIAG: %04x\n", inw(BASE + VX_W4_NET_DIAG)); + PRINTK2("--> FIFO_DIAG: %04x\n", inw(BASE + VX_W4_FIFO_DIAG)); + PRINTK2("--> CTRLR_STATUS: %04x\n", inw(BASE + VX_W4_CTRLR_STATUS)); + PRINTK2("\n\n"); + + /* enter working mode */ + GO_WINDOW(1); + VX_BUSY_WAIT; + + /* wait for another 1ms */ + udelay(100000000); +} + + +/*----------------------------------------------------------------- + . + . The driver can be entered at any of the following entry points. + . + .------------------------------------------------------------------ */ + +extern int eth_init(bd_t *bd); +extern void eth_halt(void); +extern int eth_rx(void); +extern int eth_send(volatile void *packet, int length); + + +/* + ------------------------------------------------------------ + . + . Internal routines + . + ------------------------------------------------------------ +*/ + +int eth_init(bd_t *bd) +{ + el_reset(bd); + return 0; +} + +void eth_halt() { + return; +} + +#define EDEBUG 1 + + +/************************************************************************** +ETH_POLL - Wait for a frame +***************************************************************************/ + +int eth_rx() +{ + word status, rx_status, packet_size; + + VX_BUSY_WAIT; + + status = inw( BASE + VX_STATUS ); + + if ( (status & S_RX_COMPLETE) == 0 ) return 0; /* nothing to do */ + + /* Packet waiting -> check RX_STATUS */ + rx_status = inw( BASE + VX_W1_RX_STATUS ); + + if ( rx_status & ERR_RX ) + { + /* error in packet -> discard */ + PRINTK("[ERROR] Invalid packet -> discarding\n"); + PRINTK("-- error code 0x%02x\n", rx_status & ERR_MASK); + PRINTK("-- rx bytes 0x%04d\n", rx_status & ((1<<11) - 1)); + PRINTK("[ERROR] Invalid packet -> discarding\n"); + outw( RX_DISCARD_TOP_PACK, BASE + VX_COMMAND ); + return 0; + } + + /* correct pack. waiting in fifo */ + packet_size = rx_status & RX_BYTES_MASK; + + PRINTK("Correct packet waiting in fifo, size: %d\n", packet_size); + + { + volatile word *packet_start = (word *)(BASE + VX_W1_RX_PIO_RD_1); + word *RcvBuffer = (word *)(NetRxPackets[0]); + int wcount = 0; + + for (wcount = 0; wcount < (packet_size >> 1); wcount++) + { + *RcvBuffer++ = *(packet_start); + } + + /* handle odd packets */ + if ( packet_size & 1 ) + { + *RcvBuffer++ = *(packet_start); + } + } + + /* fifo should now be empty (besides the padding bytes) */ + if ( ((*((word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK) > 3 ) + { + PRINTK("[ERROR] Fifo not empty after packet read (remaining pkts: %d)\n", + (((*(word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK)); + } + + /* discard packet */ + *((word *)(BASE + VX_COMMAND)) = RX_DISCARD_TOP_PACK; + + /* Pass Packets to upper Layer */ + NetReceive(NetRxPackets[0], packet_size); + return packet_size; +} + + +/************************************************************************** +ETH_TRANSMIT - Transmit a frame +***************************************************************************/ +static char padmap[] = { + 0, 3, 2, 1}; + + +int eth_send(volatile void *packet, int length) { + int pad; + int status; + volatile word *buf = (word *)packet; + int dummy = 0; + + /* padding stuff */ + pad = padmap[length & 3]; + + PRINTK("eth_send(), length: %d\n", length); + /* drop acknowledgements */ + while(( status=inb(EL_BASE_ADDR + VX_W1_TX_STATUS) )& TXS_COMPLETE ) { + if(status & (TXS_UNDERRUN|TXS_MAX_COLLISION|TXS_STATUS_OVERFLOW)) { + outw(TX_RESET, EL_BASE_ADDR + VX_COMMAND); + outw(TX_ENABLE, EL_BASE_ADDR + VX_COMMAND); + PRINTK("Bad status, resetting and reenabling transmitter\n"); + } + + outb(0x0, EL_BASE_ADDR + VX_W1_TX_STATUS); + } + + + while (inw(EL_BASE_ADDR + VX_W1_FREE_TX) < length + pad + 4) { + /* no room in FIFO */ + if (dummy == 0) + { + PRINTK("No room in FIFO, waiting...\n"); + dummy++; + } + + } + + PRINTK(" ---> FIFO ready\n"); + + + outw(length, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1); + + /* Second dword meaningless */ + outw(0x0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1); + +#if EL_DEBUG > 1 + print_packet((byte *)buf, length); +#endif + + /* write packet */ + { + unsigned int i, totw; + + totw = ((length + 1) >> 1); + PRINTK("Buffer: (totw = %d)\n", totw); + for (i = 0; i < totw; i++) { + outw( *(buf+i), EL_BASE_ADDR + VX_W1_TX_PIO_WR_1); + udelay(10); + } + if(totw & 1) + { /* pad to double word length */ + outw( 0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1); + udelay(10); + } + PRINTK("\n\n"); + } + + /* wait for Tx complete */ + PRINTK("Waiting for Tx to complete...\n"); + while(((status = inw(EL_BASE_ADDR + VX_STATUS)) & S_COMMAND_IN_PROGRESS) != 0) + { + udelay(10); + } + PRINTK(" ---> Tx completed, status = 0x%04x\n", status); + + return length; +} + + +#endif /* CONFIG_DRIVER_3C589 */ diff --git a/drivers/3c589.h b/drivers/3c589.h new file mode 100644 index 0000000..6735bf9 --- /dev/null +++ b/drivers/3c589.h @@ -0,0 +1,435 @@ +/* + * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. 2. The name + * of the author may not be used to endorse or promote products derived from + * this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + October 2, 1994 + + Modified by: Andres Vega Garcia + + INRIA - Sophia Antipolis, France + e-mail: avega@sophia.inria.fr + finger: avega@pax.inria.fr + + */ + +/* + * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the + * 3c590 family. + */ + +/* + * Modified by Shusuke Nisiyama + * for etherboot + * Mar. 14, 2000 +*/ + +/* + * Ethernet software status per interface. + */ + +/* + * Some global constants + */ + +#define TX_INIT_RATE 16 +#define TX_INIT_MAX_RATE 64 +#define RX_INIT_LATENCY 64 +#define RX_INIT_EARLY_THRESH 64 +#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ +#define MIN_RX_EARLY_THRESHL 4 + +#define EEPROMSIZE 0x40 +#define MAX_EEPROMBUSY 1000 +#define VX_LAST_TAG 0xd7 +#define VX_MAX_BOARDS 16 +#define VX_ID_PORT 0x100 + +/* + * some macros to acces long named fields + */ +#define BASE (EL_BASE_ADDR) + +/* + * Commands to read/write EEPROM trough EEPROM command register (Window 0, + * Offset 0xa) + */ +#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ +#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ +#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ +#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ + +#define EEPROM_BUSY (1<<15) + +/* + * Some short functions, worth to let them be a macro + */ + +/************************************************************************** + * * + * These define the EEPROM data structure. They are used in the probe + * function to verify the existence of the adapter after having sent + * the ID_Sequence. + * + * There are others but only the ones we use are defined here. + * + **************************************************************************/ + +#define EEPROM_NODE_ADDR_0 0x0 /* Word */ +#define EEPROM_NODE_ADDR_1 0x1 /* Word */ +#define EEPROM_NODE_ADDR_2 0x2 /* Word */ +#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ +#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ +#define EEPROM_ADDR_CFG 0x8 /* Base addr */ +#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ +#define EEPROM_OEM_ADDR_0 0xa /* Word */ +#define EEPROM_OEM_ADDR_1 0xb /* Word */ +#define EEPROM_OEM_ADDR_2 0xc /* Word */ +#define EEPROM_SOFT_INFO_2 0xf /* Software information 2 */ + +#define NO_RX_OVN_ANOMALY (1<<5) + +/************************************************************************** + * * + * These are the registers for the 3Com 3c509 and their bit patterns when * + * applicable. They have been taken out the the "EtherLink III Parallel * + * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * + * from 3com. * + * * + **************************************************************************/ + +#define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a + * command reg. */ +#define VX_STATUS 0x0e /* Read. BASE+0x0e is always status + * reg. */ +#define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window + * reg. */ +/* + * Window 0 registers. Setup. + */ +/* Write */ +#define VX_W0_EEPROM_DATA 0x0c +#define VX_W0_EEPROM_COMMAND 0x0a +#define VX_W0_RESOURCE_CFG 0x08 +#define VX_W0_ADDRESS_CFG 0x06 +#define VX_W0_CONFIG_CTRL 0x04 + /* Read */ +#define VX_W0_PRODUCT_ID 0x02 +#define VX_W0_MFG_ID 0x00 + + +/* + * Window 1 registers. Operating Set. + */ +/* Write */ +#define VX_W1_TX_PIO_WR_2 0x02 +#define VX_W1_TX_PIO_WR_1 0x00 +/* Read */ +#define VX_W1_FREE_TX 0x0c +#define VX_W1_TX_STATUS 0x0b /* byte */ +#define VX_W1_TIMER 0x0a /* byte */ +#define VX_W1_RX_STATUS 0x08 +#define VX_W1_RX_PIO_RD_2 0x02 +#define VX_W1_RX_PIO_RD_1 0x00 + +/* + * Window 2 registers. Station Address Setup/Read + */ +/* Read/Write */ +#define VX_W2_ADDR_5 0x05 +#define VX_W2_ADDR_4 0x04 +#define VX_W2_ADDR_3 0x03 +#define VX_W2_ADDR_2 0x02 +#define VX_W2_ADDR_1 0x01 +#define VX_W2_ADDR_0 0x00 + +/* + * Window 3 registers. FIFO Management. + */ +/* Read */ +#define VX_W3_INTERNAL_CFG 0x00 +#define VX_W3_RESET_OPT 0x08 +#define VX_W3_FREE_TX 0x0c +#define VX_W3_FREE_RX 0x0a + +/* + * Window 4 registers. Diagnostics. + */ +/* Read/Write */ +#define VX_W4_MEDIA_TYPE 0x0a +#define VX_W4_CTRLR_STATUS 0x08 +#define VX_W4_NET_DIAG 0x06 +#define VX_W4_FIFO_DIAG 0x04 +#define VX_W4_HOST_DIAG 0x02 +#define VX_W4_TX_DIAG 0x00 + +/* + * Window 5 Registers. Results and Internal status. + */ +/* Read */ +#define VX_W5_READ_0_MASK 0x0c +#define VX_W5_INTR_MASK 0x0a +#define VX_W5_RX_FILTER 0x08 +#define VX_W5_RX_EARLY_THRESH 0x06 +#define VX_W5_TX_AVAIL_THRESH 0x02 +#define VX_W5_TX_START_THRESH 0x00 + +/* + * Window 6 registers. Statistics. + */ +/* Read/Write */ +#define TX_TOTAL_OK 0x0c +#define RX_TOTAL_OK 0x0a +#define TX_DEFERRALS 0x08 +#define RX_FRAMES_OK 0x07 +#define TX_FRAMES_OK 0x06 +#define RX_OVERRUNS 0x05 +#define TX_COLLISIONS 0x04 +#define TX_AFTER_1_COLLISION 0x03 +#define TX_AFTER_X_COLLISIONS 0x02 +#define TX_NO_SQE 0x01 +#define TX_CD_LOST 0x00 + +/**************************************** + * + * Register definitions. + * + ****************************************/ + +/* + * Command register. All windows. + * + * 16 bit register. + * 15-11: 5-bit code for command to be executed. + * 10-0: 11-bit arg if any. For commands with no args; + * this can be set to anything. + */ +#define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms + * after issuing */ +#define WINDOW_SELECT (unsigned short) (0x1<<11) +#define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to + * determine whether + * this is needed. If + * so; wait 800 uSec + * before using trans- + * ceiver. */ +#define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on + * power-up */ +#define RX_ENABLE (unsigned short) (0x4<<11) +#define RX_RESET (unsigned short) (0x5<<11) +#define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) +#define TX_ENABLE (unsigned short) (0x9<<11) +#define TX_DISABLE (unsigned short) (0xa<<11) +#define TX_RESET (unsigned short) (0xb<<11) +#define REQ_INTR (unsigned short) (0xc<<11) +/* + * The following C_* acknowledge the various interrupts. Some of them don't + * do anything. See the manual. + */ +#define ACK_INTR (unsigned short) (0x6800) +# define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1) +# define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) +# define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) +# define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8) +# define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) +# define C_RX_EARLY (unsigned short) (ACK_INTR|0x20) +# define C_INT_RQD (unsigned short) (ACK_INTR|0x40) +# define C_UPD_STATS (unsigned short) (ACK_INTR|0x80) +#define SET_INTR_MASK (unsigned short) (0xe<<11) +#define SET_RD_0_MASK (unsigned short) (0xf<<11) +#define SET_RX_FILTER (unsigned short) (0x10<<11) +# define FIL_INDIVIDUAL (unsigned short) (0x1) +# define FIL_MULTICAST (unsigned short) (0x02) +# define FIL_BRDCST (unsigned short) (0x04) +# define FIL_PROMISC (unsigned short) (0x08) +#define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11) +#define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) +#define SET_TX_START_THRESH (unsigned short) (0x13<<11) +#define STATS_ENABLE (unsigned short) (0x15<<11) +#define STATS_DISABLE (unsigned short) (0x16<<11) +#define STOP_TRANSCEIVER (unsigned short) (0x17<<11) + +/* + * Status register. All windows. + * + * 15-13: Window number(0-7). + * 12: Command_in_progress. + * 11: reserved. + * 10: reserved. + * 9: reserved. + * 8: reserved. + * 7: Update Statistics. + * 6: Interrupt Requested. + * 5: RX Early. + * 4: RX Complete. + * 3: TX Available. + * 2: TX Complete. + * 1: Adapter Failure. + * 0: Interrupt Latch. + */ +#define S_INTR_LATCH (unsigned short) (0x1) +#define S_CARD_FAILURE (unsigned short) (0x2) +#define S_TX_COMPLETE (unsigned short) (0x4) +#define S_TX_AVAIL (unsigned short) (0x8) +#define S_RX_COMPLETE (unsigned short) (0x10) +#define S_RX_EARLY (unsigned short) (0x20) +#define S_INT_RQD (unsigned short) (0x40) +#define S_UPD_STATS (unsigned short) (0x80) +#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000) + +#define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) + +/* Address Config. Register. + * Window 0/Port 06 + */ + +#define ACF_CONNECTOR_BITS 14 +#define ACF_CONNECTOR_UTP 0 +#define ACF_CONNECTOR_AUI 1 +#define ACF_CONNECTOR_BNC 3 + +#define INTERNAL_CONNECTOR_BITS 20 +#define INTERNAL_CONNECTOR_MASK 0x01700000 + +/* + * FIFO Registers. RX Status. + * + * 15: Incomplete or FIFO empty. + * 14: 1: Error in RX Packet 0: Incomplete or no error. + * 13-11: Type of error. + * 1000 = Overrun. + * 1011 = Run Packet Error. + * 1100 = Alignment Error. + * 1101 = CRC Error. + * 1001 = Oversize Packet Error (>1514 bytes) + * 0010 = Dribble Bits. + * (all other error codes, no errors.) + * + * 10-0: RX Bytes (0-1514) + */ +#define ERR_INCOMPLETE (unsigned short) (0x8000) +#define ERR_RX (unsigned short) (0x4000) +#define ERR_MASK (unsigned short) (0x7800) +#define ERR_OVERRUN (unsigned short) (0x4000) +#define ERR_RUNT (unsigned short) (0x5800) +#define ERR_ALIGNMENT (unsigned short) (0x6000) +#define ERR_CRC (unsigned short) (0x6800) +#define ERR_OVERSIZE (unsigned short) (0x4800) +#define ERR_DRIBBLE (unsigned short) (0x1000) + +/* + * TX Status. + * + * Reports the transmit status of a completed transmission. Writing this + * register pops the transmit completion stack. + * + * Window 1/Port 0x0b. + * + * 7: Complete + * 6: Interrupt on successful transmission requested. + * 5: Jabber Error (TP Only, TX Reset required. ) + * 4: Underrun (TX Reset required. ) + * 3: Maximum Collisions. + * 2: TX Status Overflow. + * 1-0: Undefined. + * + */ +#define TXS_COMPLETE 0x80 +#define TXS_INTR_REQ 0x40 +#define TXS_JABBER 0x20 +#define TXS_UNDERRUN 0x10 +#define TXS_MAX_COLLISION 0x8 +#define TXS_STATUS_OVERFLOW 0x4 + +#define RS_AUI (1<<5) +#define RS_BNC (1<<4) +#define RS_UTP (1<<3) +#define RS_T4 (1<<0) +#define RS_TX (1<<1) +#define RS_FX (1<<2) +#define RS_MII (1<<6) + + +/* + * FIFO Status (Window 4) + * + * Supports FIFO diagnostics + * + * Window 4/Port 0x04.1 + * + * 15: 1=RX receiving (RO). Set when a packet is being received + * into the RX FIFO. + * 14: Reserved + * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. + * Requires RX Reset or Global Reset command to recover. + * It is generated when you read past the end of a packet - + * reading past what has been received so far will give bad + * data. + * 12: 1=RX status overrun (RO). Set when there are already 8 + * packets in the RX FIFO. While this bit is set, no additional + * packets are received. Requires no action on the part of + * the host. The condition is cleared once a packet has been + * read out of the RX FIFO. + * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there + * may not be an overrun packet yet). While this bit is set, + * no additional packets will be received (some additional + * bytes can still be pending between the wire and the RX + * FIFO). Requires no action on the part of the host. The + * condition is cleared once a few bytes have been read out + * from the RX FIFO. + * 10: 1=TX overrun (RO). Generates adapter failure interrupt. + * Requires TX Reset or Global Reset command to recover. + * Disables Transmitter. + * 9-8: Unassigned. + * 7-0: Built in self test bits for the RX and TX FIFO's. + */ +#define FIFOS_RX_RECEIVING (unsigned short) 0x8000 +#define FIFOS_RX_UNDERRUN (unsigned short) 0x2000 +#define FIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000 +#define FIFOS_RX_OVERRUN (unsigned short) 0x0800 +#define FIFOS_TX_OVERRUN (unsigned short) 0x0400 + +/* + * Misc defines for various things. + */ +#define TAG_ADAPTER 0xd0 +#define ACTIVATE_ADAPTER_TO_CONFIG 0xff +#define ENABLE_DRQ_IRQ 0x0001 +#define MFG_ID 0x506d /* `TCM' */ +#define PROD_ID 0x5090 +#define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND) +#define JABBER_GUARD_ENABLE 0x40 +#define LINKBEAT_ENABLE 0x80 +#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) +#define DISABLE_UTP 0x0 +#define RX_BYTES_MASK (unsigned short) (0x07ff) +#define RX_ERROR 0x4000 +#define RX_INCOMPLETE 0x8000 +#define TX_INDICATE 1<<15 +#define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY) + +#define VX_IOSIZE 0x20 + +#define VX_CONNECTORS 8 + +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/drivers/5701rls.c b/drivers/5701rls.c new file mode 100644 index 0000000..86950d0 --- /dev/null +++ b/drivers/5701rls.c @@ -0,0 +1,46 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* */ +/******************************************************************************/ + +#if INCLUDE_5701_AX_FIX + +#include "bcm570x_mm.h" +#include "5701rls.h" + +LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice) +{ + T3_FWIMG_INFO FwImgInfo; + + FwImgInfo.StartAddress = t3FwStartAddr; + FwImgInfo.Text.Buffer = (PLM_UINT8)t3FwText; + FwImgInfo.Text.Offset = t3FwTextAddr; + FwImgInfo.Text.Length = t3FwTextLen; + FwImgInfo.ROnlyData.Buffer = (PLM_UINT8)t3FwRodata; + FwImgInfo.ROnlyData.Offset = t3FwRodataAddr; + FwImgInfo.ROnlyData.Length = t3FwRodataLen; + FwImgInfo.Data.Buffer = (PLM_UINT8)t3FwData; + FwImgInfo.Data.Offset = t3FwDataAddr; + FwImgInfo.Data.Length = t3FwDataLen; + + if (LM_LoadFirmware(pDevice, + &FwImgInfo, + T3_RX_CPU_ID | T3_TX_CPU_ID, + T3_RX_CPU_ID) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + return LM_STATUS_SUCCESS; +} + +#endif /* INCLUDE_5701_AX_FIX */ diff --git a/drivers/5701rls.h b/drivers/5701rls.h new file mode 100644 index 0000000..30b127a --- /dev/null +++ b/drivers/5701rls.h @@ -0,0 +1,198 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ + +typedef unsigned long U32; +int t3FwReleaseMajor = 0x0; +int t3FwReleaseMinor = 0x0; +int t3FwReleaseFix = 0x0; +U32 t3FwStartAddr = 0x08000000; +U32 t3FwTextAddr = 0x08000000; +int t3FwTextLen = 0x9c0; +U32 t3FwRodataAddr = 0x080009c0; +int t3FwRodataLen = 0x60; +U32 t3FwDataAddr = 0x08000a40; +int t3FwDataLen = 0x20; +U32 t3FwSbssAddr = 0x08000a60; +int t3FwSbssLen = 0xc; +U32 t3FwBssAddr = 0x08000a70; +int t3FwBssLen = 0x10; +U32 t3FwText[(0x9c0/4) + 1] = { +0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c1d0800, 0x37bd3ffc, 0x3a0f021, 0x3c100800, +0x26100000, 0xe000018, 0x0, 0xd, +0x3c1d0800, 0x37bd3ffc, 0x3a0f021, 0x3c100800, +0x26100034, 0xe00021c, 0x0, 0xd, +0x0, 0x0, 0x0, 0x27bdffe0, +0x3c1cc000, 0xafbf0018, 0xaf80680c, 0xe00004c, +0x241b2105, 0x97850000, 0x97870002, 0x9782002c, +0x9783002e, 0x3c040800, 0x248409c0, 0xafa00014, +0x21400, 0x621825, 0x52c00, 0xafa30010, +0x8f860010, 0xe52825, 0xe000060, 0x24070102, +0x3c02ac00, 0x34420100, 0x3c03ac01, 0x34630100, +0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, +0xaf82049c, 0x24020001, 0xaf825ce0, 0xe00003f, +0xaf825d00, 0xe000140, 0x0, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, +0x8f835400, 0x34630400, 0xaf835400, 0xaf825404, +0x3c020800, 0x24420034, 0xaf82541c, 0x3e00008, +0xaf805400, 0x0, 0x0, 0x3c020800, +0x34423000, 0x3c030800, 0x34633000, 0x3c040800, +0x348437ff, 0x3c010800, 0xac220a64, 0x24020040, +0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, +0xac600000, 0x24630004, 0x83102b, 0x5040fffd, +0xac600000, 0x3e00008, 0x0, 0x804821, +0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, +0x8c840a68, 0x8fab0014, 0x24430001, 0x44102b, +0x3c010800, 0xac230a60, 0x14400003, 0x4021, +0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, +0x3c030800, 0x8c630a64, 0x91240000, 0x21140, +0x431021, 0x481021, 0x25080001, 0xa0440000, +0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, +0x8c420a60, 0x3c030800, 0x8c630a64, 0x8f84680c, +0x21140, 0x431021, 0xac440008, 0xac45000c, +0xac460010, 0xac470014, 0xac4a0018, 0x3e00008, +0xac4b001c, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x2000008, +0x0, 0xa0001e3, 0x3c0a0001, 0xa0001e3, +0x3c0a0002, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x3c0a0007, 0xa0001e3, 0x3c0a0008, 0xa0001e3, +0x3c0a0009, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x3c0a000b, 0xa0001e3, +0x3c0a000c, 0xa0001e3, 0x3c0a000d, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x3c0a000e, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x3c0a0013, 0xa0001e3, +0x3c0a0014, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x27bdffe0, +0x1821, 0x1021, 0xafbf0018, 0xafb10014, +0xafb00010, 0x3c010800, 0x220821, 0xac200a70, +0x3c010800, 0x220821, 0xac200a74, 0x3c010800, +0x220821, 0xac200a78, 0x24630001, 0x1860fff5, +0x2442000c, 0x24110001, 0x8f906810, 0x32020004, +0x14400005, 0x24040001, 0x3c020800, 0x8c420a78, +0x18400003, 0x2021, 0xe000182, 0x0, +0x32020001, 0x10400003, 0x0, 0xe000169, +0x0, 0xa000153, 0xaf915028, 0x8fbf0018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0020, +0x3c050800, 0x8ca50a70, 0x3c060800, 0x8cc60a80, +0x3c070800, 0x8ce70a78, 0x27bdffe0, 0x3c040800, +0x248409d0, 0xafbf0018, 0xafa00010, 0xe000060, +0xafa00014, 0xe00017b, 0x2021, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x24020001, 0x8f836810, +0x821004, 0x21027, 0x621824, 0x3e00008, +0xaf836810, 0x27bdffd8, 0xafbf0024, 0x1080002e, +0xafb00020, 0x8f825cec, 0xafa20018, 0x8f825cec, +0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, +0xaf825cec, 0x8e020000, 0x18400016, 0x0, +0x3c020800, 0x94420a74, 0x8fa3001c, 0x221c0, +0xac830004, 0x8fa2001c, 0x3c010800, 0xe000201, +0xac220a74, 0x10400005, 0x0, 0x8e020000, +0x24420001, 0xa0001df, 0xae020000, 0x3c020800, +0x8c420a70, 0x21c02, 0x321c0, 0xa0001c5, +0xafa2001c, 0xe000201, 0x0, 0x1040001f, +0x0, 0x8e020000, 0x8fa3001c, 0x24420001, +0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, +0xa0001df, 0xae020000, 0x3c100800, 0x26100a78, +0x8e020000, 0x18400028, 0x0, 0xe000201, +0x0, 0x14400024, 0x0, 0x8e020000, +0x3c030800, 0x8c630a70, 0x2442ffff, 0xafa3001c, +0x18400006, 0xae020000, 0x31402, 0x221c0, +0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, +0x2442ff00, 0x2c420300, 0x1440000b, 0x24024000, +0x3c040800, 0x248409dc, 0xafa00010, 0xafa00014, +0x8fa6001c, 0x24050008, 0xe000060, 0x3821, +0xa0001df, 0x0, 0xaf825cf8, 0x3c020800, +0x8c420a40, 0x8fa3001c, 0x24420001, 0xaf835cf8, +0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, +0x3e00008, 0x27bd0028, 0x27bdffe0, 0x3c040800, +0x248409e8, 0x2821, 0x3021, 0x3821, +0xafbf0018, 0xafa00010, 0xe000060, 0xafa00014, +0x8fbf0018, 0x3e00008, 0x27bd0020, 0x8f82680c, +0x8f85680c, 0x21827, 0x3182b, 0x31823, +0x431024, 0x441021, 0xa2282b, 0x10a00006, +0x0, 0x401821, 0x8f82680c, 0x43102b, +0x1440fffd, 0x0, 0x3e00008, 0x0, +0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, +0x64102b, 0x54400002, 0x831023, 0x641023, +0x2c420008, 0x3e00008, 0x38420001, 0x27bdffe0, +0x802821, 0x3c040800, 0x24840a00, 0x3021, +0x3821, 0xafbf0018, 0xafa00010, 0xe000060, +0xafa00014, 0xa000216, 0x0, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x0, 0x27bdffe0, +0x3c1cc000, 0xafbf0018, 0xe00004c, 0xaf80680c, +0x3c040800, 0x24840a10, 0x3802821, 0x3021, +0x3821, 0xafa00010, 0xe000060, 0xafa00014, +0x2402ffff, 0xaf825404, 0x3c0200aa, 0xe000234, +0xaf825434, 0x8fbf0018, 0x3e00008, 0x27bd0020, +0x0, 0x0, 0x0, 0x27bdffe8, +0xafb00010, 0x24100001, 0xafbf0014, 0x3c01c003, +0xac200000, 0x8f826810, 0x30422000, 0x10400003, +0x0, 0xe000246, 0x0, 0xa00023a, +0xaf905428, 0x8fbf0014, 0x8fb00010, 0x3e00008, +0x27bd0018, 0x27bdfff8, 0x8f845d0c, 0x3c0200ff, +0x3c030800, 0x8c630a50, 0x3442fff8, 0x821024, +0x1043001e, 0x3c0500ff, 0x34a5fff8, 0x3c06c003, +0x3c074000, 0x851824, 0x8c620010, 0x3c010800, +0xac230a50, 0x30420008, 0x10400005, 0x871025, +0x8cc20000, 0x24420001, 0xacc20000, 0x871025, +0xaf825d0c, 0x8fa20000, 0x24420001, 0xafa20000, +0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, +0x8fa20000, 0x8f845d0c, 0x3c030800, 0x8c630a50, +0x851024, 0x1443ffe8, 0x851824, 0x27bd0008, +0x3e00008, 0x0, 0x0, 0x0 }; +U32 t3FwRodata[(0x60/4) + 1] = { +0x35373031, 0x726c7341, 0x0, +0x0, 0x53774576, 0x656e7430, 0x0, +0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, +0x45766e74, 0x0, 0x0, 0x0, +0x0, 0x66617461, 0x6c457272, 0x0, +0x0, 0x4d61696e, 0x43707542, 0x0, +0x0, 0x0 }; +U32 t3FwData[(0x20/4) + 1] = { +0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0 }; diff --git a/drivers/8390.h b/drivers/8390.h new file mode 100644 index 0000000..f087217 --- /dev/null +++ b/drivers/8390.h @@ -0,0 +1,124 @@ +/* + +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + +*/ + +/* Generic NS8390 register definitions. */ +/* This file is part of Donald Becker's 8390 drivers, and is distributed + under the same license. Auto-loading of 8390.o only in v2.2 - Paul G. + Some of these names and comments originated from the Crynwr + packet drivers, which are distributed under the GPL. */ + +#ifndef _8390_h +#define _8390_h + +/* Some generic ethernet register configurations. */ +#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */ +#define E8390_RX_IRQ_MASK 0x5 +#define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */ +#define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */ +#define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */ +#define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */ + +/* Register accessed at EN_CMD, the 8390 base addr. */ +#define E8390_STOP 0x01 /* Stop and reset the chip */ +#define E8390_START 0x02 /* Start the chip, clear reset */ +#define E8390_TRANS 0x04 /* Transmit a frame */ +#define E8390_RREAD 0x08 /* Remote read */ +#define E8390_RWRITE 0x10 /* Remote write */ +#define E8390_NODMA 0x20 /* Remote DMA */ +#define E8390_PAGE0 0x00 /* Select page chip registers */ +#define E8390_PAGE1 0x40 /* using the two high-order bits */ +#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ + +/* + * Only generate indirect loads given a machine that needs them. + * - removed AMIGA_PCMCIA from this list, handled as ISA io now + */ + +#define n2k_inb(port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE))) +#define n2k_outb(val,port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)) = val) + +#define EI_SHIFT(x) (x) + +#define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */ +/* Page 0 register offsets. */ +#define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */ +#define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */ +#define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */ +#define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */ +#define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */ +#define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */ +#define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */ +#define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */ +#define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */ +#define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */ +#define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */ +#define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ +#define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */ +#define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */ +#define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */ +#define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */ +#define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */ +#define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */ +#define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */ +#define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */ +#define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */ +#define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */ +#define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */ +#define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */ +#define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */ +#define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */ + +/* Bits in EN0_ISR - Interrupt status register */ +#define ENISR_RX 0x01 /* Receiver, no error */ +#define ENISR_TX 0x02 /* Transmitter, no error */ +#define ENISR_RX_ERR 0x04 /* Receiver, with error */ +#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ +#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ +#define ENISR_COUNTERS 0x20 /* Counters need emptying */ +#define ENISR_RDC 0x40 /* remote dma complete */ +#define ENISR_RESET 0x80 /* Reset completed */ +#define ENISR_ALL 0x3f /* Interrupts we will enable */ + +/* Bits in EN0_DCFG - Data config register */ +#define ENDCFG_WTS 0x01 /* word transfer mode selection */ +#define ENDCFG_BOS 0x02 /* byte order selection */ +#define ENDCFG_AUTO_INIT 0x10 /* Auto-init to remove packets from ring */ +#define ENDCFG_FIFO 0x40 /* 8 bytes */ + +/* Page 1 register offsets. */ +#define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */ +#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */ +#define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */ +#define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */ +#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */ + +/* Bits in received packet status byte and EN0_RSR*/ +#define ENRSR_RXOK 0x01 /* Received a good packet */ +#define ENRSR_CRC 0x02 /* CRC error */ +#define ENRSR_FAE 0x04 /* frame alignment error */ +#define ENRSR_FO 0x08 /* FIFO overrun */ +#define ENRSR_MPA 0x10 /* missed pkt */ +#define ENRSR_PHY 0x20 /* physical/multicast address */ +#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ +#define ENRSR_DEF 0x80 /* deferring */ + +/* Transmitted packet status, EN0_TSR. */ +#define ENTSR_PTX 0x01 /* Packet transmitted without error */ +#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ +#define ENTSR_COL 0x04 /* The transmit collided at least once. */ +#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ +#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ +#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ +#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ +#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ + +#define NIC_RECEIVE_MONITOR_MODE 0x20 + +#endif /* _8390_h */ diff --git a/drivers/Makefile b/drivers/Makefile new file mode 100644 index 0000000..e6176ed --- /dev/null +++ b/drivers/Makefile @@ -0,0 +1,65 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG -DDEBUG + +LIB = libdrivers.a + +OBJS = 3c589.o 5701rls.o ali512x.o \ + bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ + cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ + e1000.o eepro100.o \ + i8042.o i82365.o inca-ip_sw.o keyboard.o \ + lan91c96.o \ + natsemi.o ne2000.o netarm_eth.o netconsole.o \ + ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \ + omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \ + pcnet.o plb2800_eth.o \ + ps2ser.o ps2mult.o pc_keyb.o \ + rtl8019.o rtl8139.o rtl8169.o \ + s3c4510b_eth.o s3c4510b_uart.o \ + sed13806.o sed156x.o \ + serial.o serial_max3100.o \ + serial_pl010.o serial_pl011.o serial_xuartlite.o \ + sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ + status_led.o sym53c8xx.o \ + ti_pci1410a.o tigon3.o tsec.o \ + usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ + videomodes.o w83c553f.o \ + ks8695eth.o + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/drivers/ali512x.c b/drivers/ali512x.c new file mode 100644 index 0000000..7b7edc0 --- /dev/null +++ b/drivers/ali512x.c @@ -0,0 +1,423 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Based on sc520cdp.c from rolo 1.6: + *---------------------------------------------------------------------- + * (C) Copyright 2000 + * Sysgo Real-Time Solutions GmbH + * Klein-Winternheim, Germany + *---------------------------------------------------------------------- + */ + +#include + +#ifdef CONFIG_ALI152X + +#include +#include +#include + + +/* ALI M5123 Logical device numbers: + * 0 FDC + * 1 unused? + * 2 unused? + * 3 lpt + * 4 UART1 + * 5 UART2 + * 6 RTC + * 7 mouse/kbd + * 8 CIO + */ + +/* + ************************************************************ + * Some access primitives for the ALi chip: * + ************************************************************ + */ + +static void ali_write(u8 index, u8 value) +{ + /* write an arbirary register */ + outb(index, ALI_INDEX); + outb(value, ALI_DATA); +} + +#if 0 +static int ali_read(u8 index) +{ + outb(index, ALI_INDEX); + return inb(ALI_DATA); +} +#endif + +#define ALI_OPEN() \ + outb(0x51, ALI_INDEX); \ + outb(0x23, ALI_INDEX) + + +#define ALI_CLOSE() \ + outb(0xbb, ALI_INDEX) + +/* Select a logical device */ +#define ALI_SELDEV(dev) \ + ali_write(0x07, dev) + + +void ali512x_init(void) +{ + ALI_OPEN(); + + ali_write(0x02, 0x01); /* soft reset */ + ali_write(0x03, 0x03); /* disable access to CIOs */ + ali_write(0x22, 0x00); /* disable direct powerdown */ + ali_write(0x23, 0x00); /* disable auto powerdown */ + ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */ + + ALI_CLOSE(); +} + +void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel) +{ + ALI_OPEN(); + ALI_SELDEV(0); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x60, io >> 8); + ali_write(0x61, io & 0xff); + ali_write(0x70, irq); + ali_write(0x74, dma_channel); + + /* AT mode, no drive swap */ + ali_write(0xf0, 0x08); + ali_write(0xf1, 0x00); + ali_write(0xf2, 0xff); + ali_write(0xf4, 0x00); + } + ALI_CLOSE(); +} + + +void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel) +{ + ALI_OPEN(); + ALI_SELDEV(3); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x60, io >> 8); + ali_write(0x61, io & 0xff); + ali_write(0x70, irq); + ali_write(0x74, dma_channel); + + /* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */ + ali_write(0xf0, 0xbc); + /* 12 MHz, Burst DMA in ECP */ + ali_write(0xf1, 0x05); + } + ALI_CLOSE(); + +} + +void ali512x_set_uart(int enabled, int index, u16 io, u8 irq) +{ + ALI_OPEN(); + ALI_SELDEV(index?5:4); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x60, io >> 8); + ali_write(0x61, io & 0xff); + ali_write(0x70, irq); + + ali_write(0xf0, 0x00); + ali_write(0xf1, 0x00); + + /* huh? write 0xf2 twice - a typo in rolo + * or some secret ali errata? Who knows? + */ + if (index) { + ali_write(0xf2, 0x00); + } + ali_write(0xf2, 0x0c); + } + ALI_CLOSE(); + +} + +void ali512x_set_uart2_irda(int enabled) +{ + ALI_OPEN(); + ALI_SELDEV(5); + + ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */ + ALI_CLOSE(); + +} + +void ali512x_set_rtc(int enabled, u16 io, u8 irq) +{ + ALI_OPEN(); + ALI_SELDEV(6); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x60, io >> 8); + ali_write(0x61, io & 0xff); + ali_write(0x70, irq); + + ali_write(0xf0, 0x00); + } + ALI_CLOSE(); +} + +void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) +{ + ALI_OPEN(); + ALI_SELDEV(7); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x70, kbc_irq); + ali_write(0x72, mouse_irq); + + ali_write(0xf0, 0x00); + } + ALI_CLOSE(); +} + + +/* Common I/O + * + * (This descripotsion is base on several incompete sources + * since I have not been able to obtain any datasheet for the device + * there may be some mis-understandings burried in here. + * -- Daniel daniel@omicron.se) + * + * There are 22 CIO pins numbered + * 10-17 + * 20-25 + * 30-37 + * + * 20-24 are dedicated CIO pins, the other 17 are muliplexed with + * other functions. + * + * Secondary + * CIO Pin Function Decription + * ======================================================= + * CIO10 IRQIN1 Interrupt input 1? + * CIO11 IRQIN2 Interrupt input 2? + * CIO12 IRRX IrDa Receive + * CIO13 IRTX IrDa Transmit + * CIO14 P21 KBC P21 fucntion + * CIO15 P20 KBC P21 fucntion + * CIO16 I2C_CLK I2C Clock + * CIO17 I2C_DAT I2C Data + * + * CIO20 - + * CIO21 - + * CIO22 - + * CIO23 - + * CIO24 - + * CIO25 LOCK Keylock + * + * CIO30 KBC_CLK Keybaord Clock + * CIO31 CS0J General Chip Select decoder CS0J + * CIO32 CS1J General Chip Select decoder CS1J + * CIO33 ALT_KCLK Alternative Keyboard Clock + * CIO34 ALT_KDAT Alternative Keyboard Data + * CIO35 ALT_MCLK Alternative Mouse Clock + * CIO36 ALT_MDAT Alternative Mouse Data + * CIO37 ALT_KBC Alternative KBC select + * + * The CIO use an indirect address scheme. + * + * Reigster 3 in the SIO is used to select the index and data + * port addresses where the CIO I/O registers show up. + * The function selection registers are accessible under + * function SIO 8. + * + * SIO reigster 3 (CIO Address Selection) bit definitions: + * bit 7 CIO index and data registers enabled + * bit 1-0 CIO indirect registers port address select + * 0 index = 0xE0 data = 0xE1 + * 1 index = 0xE2 data = 0xE3 + * 2 index = 0xE4 data = 0xE5 + * 3 index = 0xEA data = 0xEB + * + * There are three CIO I/O register accessed via CIO index port and CIO data port + * 0x01 CIO 10-17 data + * 0x02 CIO 20-25 data (bits 7-6 unused) + * 0x03 CIO 30-37 data + * + * + * The pin function is accessed through normal + * SIO registers, each register have the same format: + * + * Bit Function Value + * 0 Input/output 1=input + * 1 Polarity of signal 1=inverted + * 2 Unused ?? + * 3 Function (normal or special) 1=special + * 7-4 Unused + * + * SIO REG + * 0xe0 CIO 10 Config + * 0xe1 CIO 11 Config + * 0xe2 CIO 12 Config + * 0xe3 CIO 13 Config + * 0xe4 CIO 14 Config + * 0xe5 CIO 15 Config + * 0xe6 CIO 16 Config + * 0xe7 CIO 16 Config + * + * 0xe8 CIO 20 Config + * 0xe9 CIO 21 Config + * 0xea CIO 22 Config + * 0xeb CIO 23 Config + * 0xec CIO 24 Config + * 0xed CIO 25 Config + * + * 0xf5 CIO 30 Config + * 0xf6 CIO 31 Config + * 0xf7 CIO 32 Config + * 0xf8 CIO 33 Config + * 0xf9 CIO 34 Config + * 0xfa CIO 35 Config + * 0xfb CIO 36 Config + * 0xfc CIO 37 Config + * + */ + +#define ALI_CIO_PORT_SEL 0x83 +#define ALI_CIO_INDEX 0xea +#define ALI_CIO_DATA 0xeb + +void ali512x_set_cio(int enabled) +{ + int i; + + ALI_OPEN(); + + if (enabled) { + ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */ + } else { + ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80); + } + + ALI_SELDEV(8); + + ali_write(0x30, enabled?1:0); + + /* set all pins to input to start with */ + for (i=0xe0;i<0xee;i++) { + ali_write(i, 1); + } + + for (i=0xf5;i<0xfe;i++) { + ali_write(i, 1); + } + + ALI_CLOSE(); +} + + +void ali512x_cio_function(int pin, int special, int inv, int input) +{ + u8 data; + u8 addr; + + /* valid pins are 10-17, 20-25 and 30-37 */ + if (pin >= 10 && pin <= 17) { + addr = 0xe0+(pin&7); + } else if (pin >= 20 && pin <= 25) { + addr = 0xe8+(pin&7); + } else if (pin >= 30 && pin <= 37) { + addr = 0xf5+(pin&7); + } else { + return; + } + + ALI_OPEN(); + + ALI_SELDEV(8); + + + data=0xf4; + if (special) { + data |= 0x08; + } else { + if (inv) { + data |= 0x02; + } + if (input) { + data |= 0x01; + } + } + + ali_write(addr, data); + + ALI_CLOSE(); +} + +void ali512x_cio_out(int pin, int value) +{ + u8 reg; + u8 data; + u8 bit; + + reg = pin/10; + bit = 1 << (pin%10); + + + outb(reg, ALI_CIO_INDEX); /* select I/O register */ + data = inb(ALI_CIO_DATA); + if (value) { + data |= bit; + } else { + data &= ~bit; + } + outb(data, ALI_CIO_DATA); +} + +int ali512x_cio_in(int pin) +{ + u8 reg; + u8 data; + u8 bit; + + /* valid pins are 10-17, 20-25 and 30-37 */ + reg = pin/10; + bit = 1 << (pin%10); + + + outb(reg, ALI_CIO_INDEX); /* select I/O register */ + data = inb(ALI_CIO_DATA); + + return data & bit; +} + + +#endif diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c new file mode 100644 index 0000000..5f632a6 --- /dev/null +++ b/drivers/bcm570x.c @@ -0,0 +1,1691 @@ +/* + * Broadcom BCM570x Ethernet Driver for U-Boot. + * Support 5701, 5702, 5703, and 5704. Single instance driver. + * Copyright (C) 2002 James F. Dougherty (jfd@broadcom.com) + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && (!defined(CONFIG_NET_MULTI)) && \ + defined(CONFIG_BCM570x) + +#ifdef CONFIG_BMW +#include +#endif +#include +#include "bcm570x_mm.h" +#include "bcm570x_autoneg.h" +#include +#include + + +/* + * PCI Registers and definitions. + */ +#define PCI_CMD_MASK 0xffff0000 /* mask to save status bits */ +#define PCI_ANY_ID (~0) + +/* + * PCI memory base for Ethernet device as well as device Interrupt. + */ +#define BCM570X_MBAR 0x80100000 +#define BCM570X_ILINE 1 + + +#define SECOND_USEC 1000000 +#define MAX_PACKET_SIZE 1600 +#define MAX_UNITS 4 + +/* Globals to this module */ +int initialized = 0; +unsigned int ioBase = 0; +volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */ +volatile PUM_DEVICE_BLOCK pUmDevice = NULL; + +/* Used to pass the full-duplex flag, etc. */ +int line_speed[MAX_UNITS] = {0,0,0,0}; +static int full_duplex[MAX_UNITS] = {1,1,1,1}; +static int rx_flow_control[MAX_UNITS] = {0,0,0,0}; +static int tx_flow_control[MAX_UNITS] = {0,0,0,0}; +static int auto_flow_control[MAX_UNITS] = {0,0,0,0}; +static int tx_checksum[MAX_UNITS] = {1,1,1,1}; +static int rx_checksum[MAX_UNITS] = {1,1,1,1}; +static int auto_speed[MAX_UNITS] = {1,1,1,1}; + +#if JUMBO_FRAMES +/* Jumbo MTU for interfaces. */ +static int mtu[MAX_UNITS] = {0,0,0,0}; +#endif + +/* Turn on Wake-on lan for a device unit */ +static int enable_wol[MAX_UNITS] = {0,0,0,0}; + +#define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT +static unsigned int tx_pkt_desc_cnt[MAX_UNITS] = + {TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, TX_DESC_CNT}; + +#define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT +static unsigned int rx_std_desc_cnt[MAX_UNITS] = + {RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT}; + +static unsigned int rx_adaptive_coalesce[MAX_UNITS] = {1,1,1,1}; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT +#define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT +static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] = + {JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT}; +#endif +#define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS +static unsigned int rx_coalesce_ticks[MAX_UNITS] = + {RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK}; + +#define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES +static unsigned int rx_max_coalesce_frames[MAX_UNITS] = + {RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM}; + +#define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS +static unsigned int tx_coalesce_ticks[MAX_UNITS] = + {TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK}; + +#define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES +static unsigned int tx_max_coalesce_frames[MAX_UNITS] = + {TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM}; + +#define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS +static unsigned int stats_coalesce_ticks[MAX_UNITS] = + {ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK}; + + +/* + * Legitimate values for BCM570x device types + */ +typedef enum { + BCM5700VIGIL = 0, + BCM5700A6, + BCM5700T6, + BCM5700A9, + BCM5700T9, + BCM5700, + BCM5701A5, + BCM5701T1, + BCM5701T8, + BCM5701A7, + BCM5701A10, + BCM5701A12, + BCM5701, + BCM5702, + BCM5703, + BCM5703A31, + TC996T, + TC996ST, + TC996SSX, + TC996SX, + TC996BT, + TC997T, + TC997SX, + TC1000T, + TC940BR01, + TC942BR01, + NC6770, + NC7760, + NC7770, + NC7780 +} board_t; + +/* Chip-Rev names for each device-type */ +static struct { + char* name; +} chip_rev[] = { + {"BCM5700VIGIL"}, + {"BCM5700A6"}, + {"BCM5700T6"}, + {"BCM5700A9"}, + {"BCM5700T9"}, + {"BCM5700"}, + {"BCM5701A5"}, + {"BCM5701T1"}, + {"BCM5701T8"}, + {"BCM5701A7"}, + {"BCM5701A10"}, + {"BCM5701A12"}, + {"BCM5701"}, + {"BCM5702"}, + {"BCM5703"}, + {"BCM5703A31"}, + {"TC996T"}, + {"TC996ST"}, + {"TC996SSX"}, + {"TC996SX"}, + {"TC996BT"}, + {"TC997T"}, + {"TC997SX"}, + {"TC1000T"}, + {"TC940BR01"}, + {"TC942BR01"}, + {"NC6770"}, + {"NC7760"}, + {"NC7770"}, + {"NC7780"}, + {0} +}; + + +/* indexed by board_t, above */ +static struct { + char *name; +} board_info[] = { + { "Broadcom Vigil B5700 1000Base-T" }, + { "Broadcom BCM5700 1000Base-T" }, + { "Broadcom BCM5700 1000Base-SX" }, + { "Broadcom BCM5700 1000Base-SX" }, + { "Broadcom BCM5700 1000Base-T" }, + { "Broadcom BCM5700" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-SX" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701" }, + { "Broadcom BCM5702 1000Base-T" }, + { "Broadcom BCM5703 1000Base-T" }, + { "Broadcom BCM5703 1000Base-SX" }, + { "3Com 3C996 10/100/1000 Server NIC" }, + { "3Com 3C996 10/100/1000 Server NIC" }, + { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, + { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, + { "3Com 3C996B Gigabit Server NIC" }, + { "3Com 3C997 Gigabit Server NIC" }, + { "3Com 3C997 Gigabit Fiber-SX Server NIC" }, + { "3Com 3C1000 Gigabit NIC" }, + { "3Com 3C940 Gigabit LOM (21X21)" }, + { "3Com 3C942 Gigabit LOM (31X31)" }, + { "Compaq NC6770 Gigabit Server Adapter" }, + { "Compaq NC7760 Gigabit Server Adapter" }, + { "Compaq NC7770 Gigabit Server Adapter" }, + { "Compaq NC7780 Gigabit Server Adapter" }, + { 0 }, +}; + +/* PCI Devices which use the 570x chipset */ +struct pci_device_table { + unsigned short vendor_id, device_id; /* Vendor/DeviceID */ + unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ + unsigned long board_id; /* Data private to the driver */ + int io_size, min_latency; +} bcm570xDevices[] = { + {0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL ,128,32}, + {0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 ,128,32}, + {0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 ,128,32}, + {0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 ,128,32}, + {0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 ,128,32}, + {0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 ,128,32}, + {0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 ,128,32}, + {0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 ,128,32}, + {0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 ,128,32}, + {0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 ,128,32}, + {0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 ,128,32}, + {0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX ,128,32}, + {0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT ,128,32}, + {0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T ,128,32}, + {0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 ,128,32}, + {0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 ,128,32}, + {0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32}, + {0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32}, + {0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32}, + {0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32}, + {0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32}, + {0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32}, + {0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32}, + {0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32}, + {0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780 ,128,32}, + {0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32}, + {0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32}, + {0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780 ,128,32}, + {0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32} +}; + +#define n570xDevices (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0])) + + +/* + * Allocate a packet buffer from the bcm570x packet pool. + */ +void * +bcm570xPktAlloc(int u, int pksize) +{ + return malloc(pksize); +} + +/* + * Free a packet previously allocated from the bcm570x packet + * buffer pool. + */ +void +bcm570xPktFree(int u, void *p) +{ + free(p); +} + +int +bcm570xReplenishRxBuffers(PUM_DEVICE_BLOCK pUmDevice) +{ + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + void *skb; + int queue_rx = 0; + int ret = 0; + + while ((pUmPacket = (PUM_PACKET) + QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) { + + pPacket = (PLM_PACKET) pUmPacket; + + /* reuse an old skb */ + if (pUmPacket->skbuff) { + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + queue_rx = 1; + continue; + } + if ( ( skb = bcm570xPktAlloc(pUmDevice->index, + pPacket->u.Rx.RxBufferSize + 2)) == 0) { + QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container,pPacket); + printf("NOTICE: Out of RX memory.\n"); + ret = 1; + break; + } + + pUmPacket->skbuff = skb; + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + queue_rx = 1; + } + + if (queue_rx) { + LM_QueueRxPackets(pDevice); + } + + return ret; +} + +/* + * Probe, Map, and Init 570x device. + */ +int eth_init(bd_t *bis) +{ + int i, rv, devFound = FALSE; + pci_dev_t devbusfn; + unsigned short status; + + /* Find PCI device, if it exists, configure ... */ + for( i = 0; i < n570xDevices; i++){ + devbusfn = pci_find_device(bcm570xDevices[i].vendor_id, + bcm570xDevices[i].device_id, 0); + if(devbusfn == -1) { + continue; /* No device of that vendor/device ID */ + } else { + + /* Set ILINE */ + pci_write_config_byte(devbusfn, + PCI_INTERRUPT_LINE, BCM570X_ILINE); + + /* + * 0x10 - 0x14 define one 64-bit MBAR. + * 0x14 is the higher-order address bits of the BAR. + */ + pci_write_config_dword(devbusfn, + PCI_BASE_ADDRESS_1, 0); + + ioBase = BCM570X_MBAR; + + pci_write_config_dword(devbusfn, + PCI_BASE_ADDRESS_0, ioBase); + + /* + * Enable PCI memory, IO, and Master -- don't + * reset any status bits in doing so. + */ + pci_read_config_word(devbusfn, + PCI_COMMAND, &status); + + status |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER; + + pci_write_config_word(devbusfn, + PCI_COMMAND, status); + + printf("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n", + board_info[bcm570xDevices[i].board_id].name, + PCI_BUS(devbusfn), + PCI_DEV(devbusfn), + PCI_FUNC(devbusfn), + ioBase); + + /* Allocate once, but always clear on init */ + if (!pDevice) { + pDevice = malloc(sizeof(UM_DEVICE_BLOCK)); + pUmDevice = (PUM_DEVICE_BLOCK)pDevice; + memset(pDevice, 0x0, sizeof(UM_DEVICE_BLOCK)); + } + + /* Configure pci dev structure */ + pUmDevice->pdev = devbusfn; + pUmDevice->index = 0; + pUmDevice->tx_pkt = 0; + pUmDevice->rx_pkt = 0; + devFound = TRUE; + break; + } + } + + if(!devFound){ + printf("eth_init: FAILURE: no BCM570x Ethernet devices found.\n"); + return -1; + } + + /* Setup defaults for chip */ + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + + if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) { + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + } else { + + if (rx_checksum[i]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_RX_UDP_CHECKSUM; + } + + if (tx_checksum[i]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM; + pDevice->NoTxPseudoHdrChksum = TRUE; + } + } + + /* Set Device PCI Memory base address */ + pDevice->pMappedMemBase = (PLM_UINT8) ioBase; + + /* Pull down adapter info */ + if ((rv = LM_GetAdapterInfo(pDevice)) != LM_STATUS_SUCCESS) { + printf("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv ); + return -2; + } + + /* Lock not needed */ + pUmDevice->do_global_lock = 0; + + if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) { + /* The 5700 chip works best without interleaved register */ + /* accesses on certain machines. */ + pUmDevice->do_global_lock = 1; + } + + /* Setup timer delays */ + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { + pDevice->UseTaggedStatus = TRUE; + pUmDevice->timer_interval = CFG_HZ; + } + else { + pUmDevice->timer_interval = CFG_HZ / 50; + } + + /* Grab name .... */ + pUmDevice->name = + (char*)malloc(strlen(board_info[bcm570xDevices[i].board_id].name)+1); + strcpy(pUmDevice->name,board_info[bcm570xDevices[i].board_id].name); + + memcpy(pDevice->NodeAddress, bis->bi_enetaddr, 6); + LM_SetMacAddress(pDevice, bis->bi_enetaddr); + /* Init queues .. */ + QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container, + MAX_RX_PACKET_DESC_COUNT); + pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0; + + /* delay for 4 seconds */ + pUmDevice->delayed_link_ind = + (4 * CFG_HZ) / pUmDevice->timer_interval; + + pUmDevice->adaptive_expiry = + CFG_HZ / pUmDevice->timer_interval; + + /* Sometimes we get spurious ints. after reset when link is down. */ + /* This field tells the isr to service the int. even if there is */ + /* no status block update. */ + pUmDevice->adapter_just_inited = + (3 * CFG_HZ) / pUmDevice->timer_interval; + + /* Initialize 570x */ + if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) { + printf("ERROR: Adapter initialization failed.\n"); + return ERROR; + } + + /* Enable chip ISR */ + LM_EnableInterrupt(pDevice); + + /* Clear MC table */ + LM_MulticastClear(pDevice); + + /* Enable Multicast */ + LM_SetReceiveMask(pDevice, + pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST); + + pUmDevice->opened = 1; + pUmDevice->tx_full = 0; + pUmDevice->tx_pkt = 0; + pUmDevice->rx_pkt = 0; + printf("eth%d: %s @0x%lx,", + pDevice->index, pUmDevice->name, (unsigned long)ioBase); + printf( "node addr "); + for (i = 0; i < 6; i++) { + printf("%2.2x", pDevice->NodeAddress[i]); + } + printf("\n"); + + printf("eth%d: ", pDevice->index); + printf("%s with ", + chip_rev[bcm570xDevices[i].board_id].name); + + if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID) + printf("Broadcom BCM5400 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + printf("Broadcom BCM5401 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID) + printf("Broadcom BCM5411 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID) + printf("Broadcom BCM5701 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID) + printf("Broadcom BCM5703 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID) + printf("Broadcom BCM8002 SerDes "); + else if (pDevice->EnableTbi) + printf("Agilent HDMP-1636 SerDes "); + else + printf("Unknown "); + printf("transceiver found\n"); + + printf("eth%d: %s, MTU: %d,", + pDevice->index, pDevice->BusSpeedStr, 1500); + + if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && + rx_checksum[i]) + printf("Rx Checksum ON\n"); + else + printf("Rx Checksum OFF\n"); + initialized++; + + return 0; +} + +/* Ethernet Interrupt service routine */ +void +eth_isr(void) +{ + LM_UINT32 oldtag, newtag; + int i; + + pUmDevice->interrupt = 1; + + if (pDevice->UseTaggedStatus) { + if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) || + pUmDevice->adapter_just_inited) { + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); + oldtag = pDevice->pStatusBlkVirt->StatusTag; + + for (i = 0; ; i++) { + pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts(pDevice); + newtag = pDevice->pStatusBlkVirt->StatusTag; + if ((newtag == oldtag) || (i > 50)) { + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24); + if (pDevice->UndiFix) { + REG_WR(pDevice, Grc.LocalCtrl, + pDevice->GrcLocalCtrl | 0x2); + } + break; + } + oldtag = newtag; + } + } + } + else { + while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { + unsigned int dummy; + + pDevice->pMemView->Mailbox.Interrupt[0].Low = 1; + pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts(pDevice); + pDevice->pMemView->Mailbox.Interrupt[0].Low = 0; + dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low; + } + } + + /* Allocate new RX buffers */ + if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) { + bcm570xReplenishRxBuffers(pUmDevice); + } + + /* Queue packets */ + if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) { + LM_QueueRxPackets(pDevice); + } + + if (pUmDevice->tx_queued) { + pUmDevice->tx_queued = 0; + } + + if(pUmDevice->tx_full){ + if(pDevice->LinkStatus != LM_STATUS_LINK_DOWN){ + printf("NOTICE: tx was previously blocked, restarting MUX\n"); + pUmDevice->tx_full = 0; + } + } + + pUmDevice->interrupt = 0; + +} + +int +eth_send(volatile void *packet, int length) +{ + int status = 0; +#if ET_DEBUG + unsigned char* ptr = (unsigned char*)packet; +#endif + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + + /* Link down, return */ + while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) { +#if 0 + printf("eth%d: link down - check cable or link partner.\n", + pUmDevice->index); +#endif + eth_isr(); + + /* Wait to see link for one-half a second before sending ... */ + udelay(1500000); + + } + + /* Clear sent flag */ + pUmDevice->tx_pkt = 0; + + /* Previously blocked */ + if(pUmDevice->tx_full){ + printf("eth%d: tx blocked.\n", pUmDevice->index); + return 0; + } + + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->TxPacketFreeQ.Container); + + if (pPacket == 0) { + pUmDevice->tx_full = 1; + printf("bcm570xEndSend: TX full!\n"); + return 0; + } + + if (pDevice->SendBdLeft.counter == 0) { + pUmDevice->tx_full = 1; + printf("bcm570xEndSend: no more TX descriptors!\n"); + QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + return 0; + } + + if (length <= 0){ + printf("eth: bad packet size: %d\n", length); + goto out; + } + + /* Get packet buffers and fragment list */ + pUmPacket = (PUM_PACKET) pPacket; + /* Single DMA Descriptor transmit. + * Fragments may be provided, but one DMA descriptor max is + * used to send the packet. + */ + if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) { + if (pUmPacket->skbuff == NULL){ + /* Packet was discarded */ + printf("TX: failed (1)\n"); + status = 1; + } else{ + printf("TX: failed (2)\n"); + status = 2; + } + QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); + return status; + } + + /* Copy packet to DMA buffer */ + memset(pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE); + memcpy((void*)pUmPacket->skbuff, (void*)packet, length); + pPacket->PacketSize = length; + pPacket->Flags |= SND_BD_FLAG_END|SND_BD_FLAG_COAL_NOW; + pPacket->u.Tx.FragCount = 1; + /* We've already provided a frame ready for transmission */ + pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM; + + if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){ + /* + * A lower level send failure will push the packet descriptor back + * in the free queue, so just deal with the VxWorks clusters. + */ + if (pUmPacket->skbuff == NULL){ + printf("TX failed (1)!\n"); + /* Packet was discarded */ + status = 3; + } else { + /* A resource problem ... */ + printf("TX failed (2)!\n"); + status = 4; + } + + if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) == 0) { + printf("TX: emptyQ!\n"); + pUmDevice->tx_full = 1; + } + } + + while(pUmDevice->tx_pkt == 0){ + /* Service TX */ + eth_isr(); + } +#if ET_DEBUG + printf("eth_send: 0x%x, %d bytes\n" + "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n", + (int)pPacket, length, + ptr[0],ptr[1],ptr[2],ptr[3],ptr[4],ptr[5], + ptr[6],ptr[7],ptr[8],ptr[9],ptr[10],ptr[11],ptr[12], + ptr[13],ptr[14],ptr[15]); +#endif + pUmDevice->tx_pkt = 0; + QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + + /* Done with send */ + out: + return status; +} + + +/* Ethernet receive */ +int +eth_rx(void) +{ + PLM_PACKET pPacket = NULL; + PUM_PACKET pUmPacket = NULL; + void *skb; + int size=0; + + while(TRUE) { + + bcm570x_service_isr: + /* Pull down packet if it is there */ + eth_isr(); + + /* Indicate RX packets called */ + if(pUmDevice->rx_pkt){ + /* printf("eth_rx: got a packet...\n"); */ + pUmDevice->rx_pkt = 0; + } else { + /* printf("eth_rx: waiting for packet...\n"); */ + goto bcm570x_service_isr; + } + + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->RxPacketReceivedQ.Container); + + if (pPacket == 0){ + printf("eth_rx: empty packet!\n"); + goto bcm570x_service_isr; + } + + pUmPacket = (PUM_PACKET) pPacket; +#if ET_DEBUG + printf("eth_rx: packet @0x%x\n", + (int)pPacket); +#endif + /* If the packet generated an error, reuse buffer */ + if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) || + ((size = pPacket->PacketSize) > pDevice->RxMtu)) { + + /* reuse skb */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + printf("eth_rx: error in packet dma!\n"); + goto bcm570x_service_isr; + } + + /* Set size and address */ + skb = pUmPacket->skbuff; + size = pPacket->PacketSize; + + /* Pass the packet up to the protocol + * layers. + */ + NetReceive(skb, size); + + /* Free packet buffer */ + bcm570xPktFree (pUmDevice->index, skb); + pUmPacket->skbuff = NULL; + + /* Reuse SKB */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + return 0; /* Got a packet, bail ... */ + } + return size; +} + + +/* Shut down device */ +void +eth_halt(void) +{ + int i; + if ( initialized) + if (pDevice && pUmDevice && pUmDevice->opened){ + printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name); + printf("HALT,"); + /* stop device */ + LM_Halt(pDevice); + printf("POWER DOWN,"); + LM_SetPowerState(pDevice, LM_POWER_STATE_D3); + + /* Free the memory allocated by the device in tigon3 */ + for (i = 0; i < pUmDevice->mem_list_num; i++) { + if (pUmDevice->mem_list[i]) { + /* sanity check */ + if (pUmDevice->dma_list[i]) { /* cache-safe memory */ + free(pUmDevice->mem_list[i]); + } else { + free(pUmDevice->mem_list[i]); /* normal memory */ + } + } + } + pUmDevice->opened = 0; + free(pDevice); + pDevice = NULL; + pUmDevice = NULL; + initialized = 0; + printf("done - offline.\n"); + } +} + + +/* + * + * Middle Module: Interface between the HW driver (tigon3 modules) and + * the native (SENS) driver. These routines implement the system + * interface for tigon3 on VxWorks. + */ + +/* Middle module dependency - size of a packet descriptor */ +int MM_Packet_Desc_Size = sizeof(UM_PACKET); + + +LM_STATUS +MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pValue32) +{ + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_dword(pUmDevice->pdev, + Offset, (u32 *) pValue32); + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 Value32) +{ + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_dword(pUmDevice->pdev, + Offset, Value32); + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT16 *pValue16) +{ + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_word(pUmDevice->pdev, + Offset, (u16*) pValue16); + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT16 Value16) +{ + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_word(pUmDevice->pdev, + Offset, Value16); + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt, + PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, + LM_BOOL Cached) +{ + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + dma_addr_t mapping; + + pvirt = malloc(BlockSize); + mapping = (dma_addr_t)(pvirt); + if (!pvirt) + return LM_STATUS_FAILURE; + + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; + memset(pvirt, 0, BlockSize); + + *pMemoryBlockVirt = (PLM_VOID) pvirt; + MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping); + + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt) +{ + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + + pvirt = malloc(BlockSize); + + if (!pvirt) + return LM_STATUS_FAILURE; + + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = 0; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; + memset(pvirt, 0, BlockSize); + *pMemoryBlockVirt = pvirt; + + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_MapMemBase(PLM_DEVICE_BLOCK pDevice) +{ + printf("BCM570x PCI Memory base address @0x%x\n", + (unsigned int)pDevice->pMappedMemBase); + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice) +{ + int i; + void* skb; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PUM_PACKET pUmPacket = NULL; + PLM_PACKET pPacket = NULL; + + for (i = 0; i < pDevice->RxPacketDescCnt; i++) { + pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + pUmPacket = (PUM_PACKET) pPacket; + + if (pPacket == 0) { + printf("MM_InitializeUmPackets: Bad RxPacketFreeQ\n"); + } + + skb = bcm570xPktAlloc(pUmDevice->index, + pPacket->u.Rx.RxBufferSize + 2); + + if (skb == 0) { + pUmPacket->skbuff = 0; + QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket); + printf("MM_InitializeUmPackets: out of buffer.\n"); + continue; + } + + pUmPacket->skbuff = skb; + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } + + pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8; + + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_GetConfig(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + int index = pDevice->index; + + if (auto_speed[index] == 0) + pDevice->DisableAutoNeg = TRUE; + else + pDevice->DisableAutoNeg = FALSE; + + if (line_speed[index] == 0) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->DisableAutoNeg = FALSE; + } + else { + if (line_speed[index] == 1000) { + if (pDevice->EnableTbi) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX; + } + else if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX; + } + else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS; + } + if (!pDevice->EnableTbi) + pDevice->DisableAutoNeg = FALSE; + } + else if (line_speed[index] == 100) { + if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX; + } + else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS; + } + } + else if (line_speed[index] == 10) { + if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX; + } + else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; + } + } + else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->DisableAutoNeg = FALSE; + } + + } + pDevice->FlowControlCap = 0; + if (rx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + if (tx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + if ((auto_flow_control[index] != 0) && + (pDevice->DisableAutoNeg == FALSE)) { + + pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE; + if ((tx_flow_control[index] == 0) && + (rx_flow_control[index] == 0)) { + pDevice->FlowControlCap |= + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + + /* Default MTU for now */ + pUmDevice->mtu = 1500; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if (pUmDevice->mtu > 1500) { + pDevice->RxMtu = pUmDevice->mtu; + pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; + } + else { + pDevice->RxJumboDescCnt = 0; + } + pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index]; +#else + pDevice->RxMtu = pUmDevice->mtu; +#endif + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { + pDevice->UseTaggedStatus = TRUE; + pUmDevice->timer_interval = CFG_HZ; + } + else { + pUmDevice->timer_interval = CFG_HZ/50; + } + + pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index]; + pDevice->RxStdDescCnt = rx_std_desc_cnt[index]; + /* Note: adaptive coalescence really isn't adaptive in this driver */ + pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index]; + if (!pUmDevice->rx_adaptive_coalesce) { + pDevice->RxCoalescingTicks = rx_coalesce_ticks[index]; + if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS) + pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS; + pUmDevice->rx_curr_coalesce_ticks =pDevice->RxCoalescingTicks; + + pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index]; + if (pDevice->RxMaxCoalescedFrames>MAX_RX_MAX_COALESCED_FRAMES) + pDevice->RxMaxCoalescedFrames = + MAX_RX_MAX_COALESCED_FRAMES; + pUmDevice->rx_curr_coalesce_frames = + pDevice->RxMaxCoalescedFrames; + pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index]; + if (pDevice->StatsCoalescingTicks>MAX_STATS_COALESCING_TICKS) + pDevice->StatsCoalescingTicks= + MAX_STATS_COALESCING_TICKS; + } + else { + pUmDevice->rx_curr_coalesce_frames = + DEFAULT_RX_MAX_COALESCED_FRAMES; + pUmDevice->rx_curr_coalesce_ticks = + DEFAULT_RX_COALESCING_TICKS; + } + pDevice->TxCoalescingTicks = tx_coalesce_ticks[index]; + if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS) + pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS; + pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index]; + if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES) + pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES; + + if (enable_wol[index]) { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET; + pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET; + } + pDevice->NicSendBd = TRUE; + + /* Don't update status blocks during interrupt */ + pDevice->RxCoalescingTicksDuringInt = 0; + pDevice->TxCoalescingTicksDuringInt = 0; + + return LM_STATUS_SUCCESS; + +} + + +LM_STATUS +MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + printf("Start TX DMA: dev=%d packet @0x%x\n", + (int)pUmDevice->index, (unsigned int)pPacket); + + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + printf("Complete TX DMA: dev=%d packet @0x%x\n", + (int)pUmDevice->index, (unsigned int)pPacket); + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status) +{ + char buf[128]; + char lcd[4]; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + LM_FLOW_CONTROL flow_control; + + pUmDevice->delayed_link_ind = 0; + memset(lcd, 0x0, 4); + + if (Status == LM_STATUS_LINK_DOWN) { + sprintf(buf,"eth%d: %s: NIC Link is down\n", + pUmDevice->index,pUmDevice->name); + lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?'; + } else if (Status == LM_STATUS_LINK_ACTIVE) { + sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name); + + if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){ + strcat(buf,"1000 Mbps "); + lcd[0] = '1';lcd[1]='G';lcd[2]='B'; + } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){ + strcat(buf,"100 Mbps "); + lcd[0] = '1';lcd[1]='0';lcd[2]='0'; + } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){ + strcat(buf,"10 Mbps "); + lcd[0] = '1';lcd[1]='0';lcd[2]=' '; + } + if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){ + strcat(buf, "full duplex"); + lcd[3] = 'F'; + } else { + strcat(buf, "half duplex"); + lcd[3] = 'H'; + } + strcat(buf, " link up"); + + flow_control = pDevice->FlowControl & + (LM_FLOW_CONTROL_RECEIVE_PAUSE | + LM_FLOW_CONTROL_TRANSMIT_PAUSE); + + if (flow_control) { + if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) { + strcat(buf,", receive "); + if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + strcat(buf," & transmit "); + } + else { + strcat(buf,", transmit "); + } + strcat(buf,"flow control ON"); + } else { + strcat(buf, ", flow control OFF"); + } + strcat(buf,"\n"); + printf("%s",buf); + } +#if 0 + sysLedDsply(lcd[0],lcd[1],lcd[2],lcd[3]); +#endif + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PUM_PACKET pUmPacket; + void *skb; + + pUmPacket = (PUM_PACKET) pPacket; + + if ((skb = pUmPacket->skbuff)) + bcm570xPktFree(pUmDevice->index, skb); + + pUmPacket->skbuff = 0; + + return LM_STATUS_SUCCESS; +} + +unsigned long +MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo) +{ + return get_timer(0); +} + +/* + * Transform an MBUF chain into a single MBUF. + * This routine will fail if the amount of data in the + * chain overflows a transmit buffer. In that case, + * the incoming MBUF chain will be freed. This routine can + * also fail by not being able to allocate a new MBUF (including + * cluster and mbuf headers). In that case the failure is + * non-fatal. The incoming cluster chain is not freed, giving + * the caller the choice of whether to try a retransmit later. + */ +LM_STATUS +MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + void *skbnew; + int len = 0; + + if (len == 0) + return (LM_STATUS_SUCCESS); + + if (len > MAX_PACKET_SIZE){ + printf ("eth%d: xmit frame discarded, too big!, size = %d\n", + pUmDevice->index, len); + return (LM_STATUS_FAILURE); + } + + skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE); + + if (skbnew == NULL) { + pUmDevice->tx_full = 1; + printf ("eth%d: out of transmit buffers", pUmDevice->index); + return (LM_STATUS_FAILURE); + } + + /* New packet values */ + pUmPacket->skbuff = skbnew; + pUmPacket->lm_packet.u.Tx.FragCount = 1; + + return (LM_STATUS_SUCCESS); +} + + +LM_STATUS +MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + pUmDevice->rx_pkt = 1; + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + void *skb; + while ( TRUE ) { + + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->TxPacketXmittedQ.Container); + + if (pPacket == 0) + break; + + pUmPacket = (PUM_PACKET) pPacket; + skb = (void*)pUmPacket->skbuff; + + /* + * Free MBLK if we transmitted a fragmented packet or a + * non-fragmented packet straight from the VxWorks + * buffer pool. If packet was copied to a local transmit + * buffer, then there's no MBUF to free, just free + * the transmit buffer back to the cluster pool. + */ + + if (skb) + bcm570xPktFree (pUmDevice->index, skb); + + pUmPacket->skbuff = 0; + QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); + pUmDevice->tx_pkt = 1; + } + if (pUmDevice->tx_full) { + if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >= + (QQ_GetSize(&pDevice->TxPacketFreeQ.Container) >> 1)) + pUmDevice->tx_full = 0; + } + return LM_STATUS_SUCCESS; +} + +/* + * Scan an MBUF chain until we reach fragment number "frag" + * Return its length and physical address. + */ +void MM_MapTxDma + ( + PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR *paddr, + LM_UINT32 *len, + int frag) +{ + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + *len = pPacket->PacketSize; + MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff); +} + +/* + * Convert an mbuf address, a CPU local virtual address, + * to a physical address as seen from a PCI device. Store the + * result at paddr. + */ +void MM_MapRxDma( + PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR *paddr) +{ + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff); +} + +void +MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr) +{ +#if (BITS_PER_LONG == 64) + paddr->High = ((unsigned long) addr) >> 32; + paddr->Low = ((unsigned long) addr) & 0xffffffff; +#else + paddr->High = 0; + paddr->Low = (unsigned long) addr; +#endif +} + +void +MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr) +{ + unsigned long baddr = (unsigned long) addr; +#if (BITS_PER_LONG == 64) + set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32); +#else + set_64bit_addr(paddr, baddr, 0); +#endif +} + +/* + * This combination of `inline' and `extern' has almost the effect of a + * macro. The way to use it is to put a function definition in a header + * file with these keywords, and put another copy of the definition + * (lacking `inline' and `extern') in a library file. The definition in + * the header file will cause most calls to the function to be inlined. + * If any uses of the function remain, they will refer to the single copy + * in the library. + */ +void +atomic_set(atomic_t* entry, int val) +{ + entry->counter = val; +} +int +atomic_read(atomic_t* entry) +{ + return entry->counter; +} +void +atomic_inc(atomic_t* entry) +{ + if(entry) + entry->counter++; +} + +void +atomic_dec(atomic_t* entry) +{ + if(entry) + entry->counter--; +} + +void +atomic_sub(int a, atomic_t* entry) +{ + if(entry) + entry->counter -= a; +} + +void +atomic_add(int a, atomic_t* entry) +{ + if(entry) + entry->counter += a; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +QQ_InitQueue( +PQQ_CONTAINER pQueue, +unsigned int QueueSize) { + pQueue->Head = 0; + pQueue->Tail = 0; + pQueue->Size = QueueSize+1; + atomic_set(&pQueue->EntryCnt, 0); +} /* QQ_InitQueue */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +char +QQ_Full( +PQQ_CONTAINER pQueue) { + unsigned int NewHead; + + NewHead = (pQueue->Head + 1) % pQueue->Size; + + return(NewHead == pQueue->Tail); +} /* QQ_Full */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +char +QQ_Empty( +PQQ_CONTAINER pQueue) { + return(pQueue->Head == pQueue->Tail); +} /* QQ_Empty */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +unsigned int +QQ_GetSize( +PQQ_CONTAINER pQueue) { + return pQueue->Size; +} /* QQ_GetSize */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +unsigned int +QQ_GetEntryCnt( +PQQ_CONTAINER pQueue) { + return atomic_read(&pQueue->EntryCnt); +} /* QQ_GetEntryCnt */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +char +QQ_PushHead( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Head; + + Head = (pQueue->Head + 1) % pQueue->Size; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Head == pQueue->Tail) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[pQueue->Head] = pEntry; + wmb(); + pQueue->Head = Head; + atomic_inc(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushHead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +char +QQ_PushTail( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Tail; + + Tail = pQueue->Tail; + if(Tail == 0) { + Tail = pQueue->Size; + } /* if */ + Tail--; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Tail == pQueue->Head) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[Tail] = pEntry; + wmb(); + pQueue->Tail = Tail; + atomic_inc(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushTail */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +PQQ_ENTRY +QQ_PopHead( +PQQ_CONTAINER pQueue) { + unsigned int Head; + PQQ_ENTRY Entry; + + Head = pQueue->Head; + +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Head == pQueue->Tail) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + if(Head == 0) { + Head = pQueue->Size; + } /* if */ + Head--; + + Entry = pQueue->Array[Head]; + membar(); + + pQueue->Head = Head; + atomic_dec(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopHead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +PQQ_ENTRY +QQ_PopTail( +PQQ_CONTAINER pQueue) { + unsigned int Tail; + PQQ_ENTRY Entry; + + Tail = pQueue->Tail; + +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Tail == pQueue->Head) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + Entry = pQueue->Array[Tail]; + membar(); + pQueue->Tail = (Tail + 1) % pQueue->Size; + atomic_dec(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopTail */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +PQQ_ENTRY +QQ_GetHead( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= atomic_read(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + if(pQueue->Head > Idx) + { + Idx = pQueue->Head - Idx; + } + else + { + Idx = pQueue->Size - (Idx - pQueue->Head); + } + Idx--; + + return pQueue->Array[Idx]; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +PQQ_ENTRY +QQ_GetTail( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= atomic_read(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + Idx += pQueue->Tail; + if(Idx >= pQueue->Size) + { + Idx = Idx - pQueue->Size; + } + + return pQueue->Array[Idx]; +} + +#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */ diff --git a/drivers/bcm570x_autoneg.c b/drivers/bcm570x_autoneg.c new file mode 100644 index 0000000..9023796 --- /dev/null +++ b/drivers/bcm570x_autoneg.c @@ -0,0 +1,439 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2001 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ +#if !defined(CONFIG_NET_MULTI) +#if INCLUDE_TBI_SUPPORT +#include "bcm570x_autoneg.h" +#include "bcm570x_mm.h" + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +MM_AnTxConfig( + PAN_STATE_INFO pAnInfo) +{ + PLM_DEVICE_BLOCK pDevice; + + pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext; + + REG_WR(pDevice, MacCtrl.TxAutoNeg, (LM_UINT32) pAnInfo->TxConfig.AsUSHORT); + + pDevice->MacMode |= MAC_MODE_SEND_CONFIGS; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +MM_AnTxIdle( + PAN_STATE_INFO pAnInfo) +{ + PLM_DEVICE_BLOCK pDevice; + + pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext; + + pDevice->MacMode &= ~MAC_MODE_SEND_CONFIGS; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +char +MM_AnRxConfig( + PAN_STATE_INFO pAnInfo, + unsigned short *pRxConfig) +{ + PLM_DEVICE_BLOCK pDevice; + LM_UINT32 Value32; + char Retcode; + + Retcode = AN_FALSE; + + pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext; + + Value32 = REG_RD(pDevice, MacCtrl.Status); + if(Value32 & MAC_STATUS_RECEIVING_CFG) + { + Value32 = REG_RD(pDevice, MacCtrl.RxAutoNeg); + *pRxConfig = (unsigned short) Value32; + + Retcode = AN_TRUE; + } + + return Retcode; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +AutonegInit( + PAN_STATE_INFO pAnInfo) +{ + unsigned long j; + + for(j = 0; j < sizeof(AN_STATE_INFO); j++) + { + ((unsigned char *) pAnInfo)[j] = 0; + } + + /* Initialize the default advertisement register. */ + pAnInfo->mr_adv_full_duplex = 1; + pAnInfo->mr_adv_sym_pause = 1; + pAnInfo->mr_adv_asym_pause = 1; + pAnInfo->mr_an_enable = 1; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +AUTONEG_STATUS +Autoneg8023z( + PAN_STATE_INFO pAnInfo) +{ + unsigned short RxConfig; + unsigned long Delta_us; + AUTONEG_STATUS AnRet; + + /* Get the current time. */ + if(pAnInfo->State == AN_STATE_UNKNOWN) + { + pAnInfo->RxConfig.AsUSHORT = 0; + pAnInfo->CurrentTime_us = 0; + pAnInfo->LinkTime_us = 0; + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->IdleMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + } + + /* Increment the timer tick. This function is called every microsecon. */ +/* pAnInfo->CurrentTime_us++; */ + + /* Set the AbilityMatch, IdleMatch, and AckMatch flags if their */ + /* corresponding conditions are satisfied. */ + if(MM_AnRxConfig(pAnInfo, &RxConfig)) + { + if(RxConfig != pAnInfo->AbilityMatchCfg) + { + pAnInfo->AbilityMatchCfg = RxConfig; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->AbilityMatchCnt = 0; + } + else + { + pAnInfo->AbilityMatchCnt++; + if(pAnInfo->AbilityMatchCnt > 1) + { + pAnInfo->AbilityMatch = AN_TRUE; + pAnInfo->AbilityMatchCfg = RxConfig; + } + } + + if(RxConfig & AN_CONFIG_ACK) + { + pAnInfo->AckMatch = AN_TRUE; + } + else + { + pAnInfo->AckMatch = AN_FALSE; + } + + pAnInfo->IdleMatch = AN_FALSE; + } + else + { + pAnInfo->IdleMatch = AN_TRUE; + + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + + RxConfig = 0; + } + + /* Save the last Config. */ + pAnInfo->RxConfig.AsUSHORT = RxConfig; + + /* Default return code. */ + AnRet = AUTONEG_STATUS_OK; + + /* Autoneg state machine as defined in 802.3z section 37.3.1.5. */ + switch(pAnInfo->State) + { + case AN_STATE_UNKNOWN: + if(pAnInfo->mr_an_enable || pAnInfo->mr_restart_an) + { + pAnInfo->CurrentTime_us = 0; + pAnInfo->State = AN_STATE_AN_ENABLE; + } + + /* Fall through.*/ + + case AN_STATE_AN_ENABLE: + pAnInfo->mr_an_complete = AN_FALSE; + pAnInfo->mr_page_rx = AN_FALSE; + + if(pAnInfo->mr_an_enable) + { + pAnInfo->LinkTime_us = 0; + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->IdleMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + + pAnInfo->State = AN_STATE_AN_RESTART_INIT; + } + else + { + pAnInfo->State = AN_STATE_DISABLE_LINK_OK; + } + break; + + case AN_STATE_AN_RESTART_INIT: + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + pAnInfo->mr_np_loaded = AN_FALSE; + + pAnInfo->TxConfig.AsUSHORT = 0; + MM_AnTxConfig(pAnInfo); + + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + pAnInfo->State = AN_STATE_AN_RESTART; + + /* Fall through.*/ + + case AN_STATE_AN_RESTART: + /* Get the current time and compute the delta with the saved */ + /* link timer. */ + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { + pAnInfo->State = AN_STATE_ABILITY_DETECT_INIT; + } + else + { + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + } + break; + + case AN_STATE_DISABLE_LINK_OK: + AnRet = AUTONEG_STATUS_DONE; + break; + + case AN_STATE_ABILITY_DETECT_INIT: + /* Note: in the state diagram, this variable is set to */ + /* mr_adv_ability<12>. Is this right?. */ + pAnInfo->mr_toggle_tx = AN_FALSE; + + /* Send the config as advertised in the advertisement register. */ + pAnInfo->TxConfig.AsUSHORT = 0; + pAnInfo->TxConfig.D5_FD = pAnInfo->mr_adv_full_duplex; + pAnInfo->TxConfig.D6_HD = pAnInfo->mr_adv_half_duplex; + pAnInfo->TxConfig.D7_PS1 = pAnInfo->mr_adv_sym_pause; + pAnInfo->TxConfig.D8_PS2 = pAnInfo->mr_adv_asym_pause; + pAnInfo->TxConfig.D12_RF1 = pAnInfo->mr_adv_remote_fault1; + pAnInfo->TxConfig.D13_RF2 = pAnInfo->mr_adv_remote_fault2; + pAnInfo->TxConfig.D15_NP = pAnInfo->mr_adv_next_page; + + MM_AnTxConfig(pAnInfo); + + pAnInfo->State = AN_STATE_ABILITY_DETECT; + + break; + + case AN_STATE_ABILITY_DETECT: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT != 0) + { + pAnInfo->State = AN_STATE_ACK_DETECT_INIT; + } + + break; + + case AN_STATE_ACK_DETECT_INIT: + pAnInfo->TxConfig.D14_ACK = 1; + MM_AnTxConfig(pAnInfo); + + pAnInfo->State = AN_STATE_ACK_DETECT; + + /* Fall through. */ + + case AN_STATE_ACK_DETECT: + if(pAnInfo->AckMatch == AN_TRUE) + { + if((pAnInfo->RxConfig.AsUSHORT & ~AN_CONFIG_ACK) == + (pAnInfo->AbilityMatchCfg & ~AN_CONFIG_ACK)) + { + pAnInfo->State = AN_STATE_COMPLETE_ACK_INIT; + } + else + { + pAnInfo->State = AN_STATE_AN_ENABLE; + } + } + else if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + } + + break; + + case AN_STATE_COMPLETE_ACK_INIT: + /* Make sure invalid bits are not set. */ + if(pAnInfo->RxConfig.bits.D0 || pAnInfo->RxConfig.bits.D1 || + pAnInfo->RxConfig.bits.D2 || pAnInfo->RxConfig.bits.D3 || + pAnInfo->RxConfig.bits.D4 || pAnInfo->RxConfig.bits.D9 || + pAnInfo->RxConfig.bits.D10 || pAnInfo->RxConfig.bits.D11) + { + AnRet = AUTONEG_STATUS_FAILED; + break; + } + + /* Set up the link partner advertisement register. */ + pAnInfo->mr_lp_adv_full_duplex = pAnInfo->RxConfig.D5_FD; + pAnInfo->mr_lp_adv_half_duplex = pAnInfo->RxConfig.D6_HD; + pAnInfo->mr_lp_adv_sym_pause = pAnInfo->RxConfig.D7_PS1; + pAnInfo->mr_lp_adv_asym_pause = pAnInfo->RxConfig.D8_PS2; + pAnInfo->mr_lp_adv_remote_fault1 = pAnInfo->RxConfig.D12_RF1; + pAnInfo->mr_lp_adv_remote_fault2 = pAnInfo->RxConfig.D13_RF2; + pAnInfo->mr_lp_adv_next_page = pAnInfo->RxConfig.D15_NP; + + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + + pAnInfo->mr_toggle_tx = !pAnInfo->mr_toggle_tx; + pAnInfo->mr_toggle_rx = pAnInfo->RxConfig.bits.D11; + pAnInfo->mr_np_rx = pAnInfo->RxConfig.D15_NP; + pAnInfo->mr_page_rx = AN_TRUE; + + pAnInfo->State = AN_STATE_COMPLETE_ACK; + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + break; + + case AN_STATE_COMPLETE_ACK: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + break; + } + + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { + if(pAnInfo->mr_adv_next_page == 0 || + pAnInfo->mr_lp_adv_next_page == 0) + { + pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; + } + else + { + if(pAnInfo->TxConfig.bits.D15 == 0 && + pAnInfo->mr_np_rx == 0) + { + pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; + } + else + { + AnRet = AUTONEG_STATUS_FAILED; + } + } + } + + break; + + case AN_STATE_IDLE_DETECT_INIT: + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + + MM_AnTxIdle(pAnInfo); + + pAnInfo->State = AN_STATE_IDLE_DETECT; + + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + break; + + case AN_STATE_IDLE_DETECT: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + break; + } + + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { +#if 0 +/* if(pAnInfo->IdleMatch == AN_TRUE) */ +/* { */ +#endif + pAnInfo->State = AN_STATE_LINK_OK; +#if 0 +/* } */ +/* else */ +/* { */ +/* AnRet = AUTONEG_STATUS_FAILED; */ +/* break; */ +/* } */ +#endif + } + + break; + + case AN_STATE_LINK_OK: + pAnInfo->mr_an_complete = AN_TRUE; + pAnInfo->mr_link_ok = AN_TRUE; + AnRet = AUTONEG_STATUS_DONE; + + break; + + case AN_STATE_NEXT_PAGE_WAIT_INIT: + break; + + case AN_STATE_NEXT_PAGE_WAIT: + break; + + default: + AnRet = AUTONEG_STATUS_FAILED; + break; + } + + return AnRet; +} +#endif /* INCLUDE_TBI_SUPPORT */ + +#endif /* !defined(CONFIG_NET_MULTI) */ diff --git a/drivers/bcm570x_autoneg.h b/drivers/bcm570x_autoneg.h new file mode 100644 index 0000000..7830944 --- /dev/null +++ b/drivers/bcm570x_autoneg.h @@ -0,0 +1,408 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2001 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ + + +#ifndef AUTONEG_H +#define AUTONEG_H + + +/******************************************************************************/ +/* Constants. */ +/******************************************************************************/ + +#define AN_LINK_TIMER_INTERVAL_US 9000 /* 10ms */ + +/* TRUE, FALSE */ +#define AN_TRUE 1 +#define AN_FALSE 0 + + +/******************************************************************************/ +/* Main data structure for keeping track of 802.3z auto-negotation state */ +/* variables as shown in Figure 37-6 of the IEEE 802.3z specification. */ +/******************************************************************************/ + +typedef struct +{ + /* Current auto-negotiation state. */ + unsigned long State; + #define AN_STATE_UNKNOWN 0 + #define AN_STATE_AN_ENABLE 1 + #define AN_STATE_AN_RESTART_INIT 2 + #define AN_STATE_AN_RESTART 3 + #define AN_STATE_DISABLE_LINK_OK 4 + #define AN_STATE_ABILITY_DETECT_INIT 5 + #define AN_STATE_ABILITY_DETECT 6 + #define AN_STATE_ACK_DETECT_INIT 7 + #define AN_STATE_ACK_DETECT 8 + #define AN_STATE_COMPLETE_ACK_INIT 9 + #define AN_STATE_COMPLETE_ACK 10 + #define AN_STATE_IDLE_DETECT_INIT 11 + #define AN_STATE_IDLE_DETECT 12 + #define AN_STATE_LINK_OK 13 + #define AN_STATE_NEXT_PAGE_WAIT_INIT 14 + #define AN_STATE_NEXT_PAGE_WAIT 16 + + /* Link timer. */ + unsigned long LinkTime_us; + + /* Current time. */ + unsigned long CurrentTime_us; + + /* Need these values for consistency check. */ + unsigned short AbilityMatchCfg; + + /* Ability, idle, and ack match functions. */ + unsigned long AbilityMatchCnt; + char AbilityMatch; + char IdleMatch; + char AckMatch; + + /* Tx config data */ + union + { + /* The TxConfig register is arranged as follows: */ + /* */ + /* MSB LSB */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + struct + { +#ifdef BIG_ENDIAN_HOST + unsigned int D7:1; /* PS1 */ + unsigned int D6:1; /* HD */ + unsigned int D5:1; /* FD */ + unsigned int D4:1; + unsigned int D3:1; + unsigned int D2:1; + unsigned int D1:1; + unsigned int D0:1; + unsigned int D15:1; /* NP */ + unsigned int D14:1; /* ACK */ + unsigned int D13:1; /* RF2 */ + unsigned int D12:1; /* RF1 */ + unsigned int D11:1; + unsigned int D10:1; + unsigned int D9:1; + unsigned int D8:1; /* PS2 */ +#else /* BIG_ENDIAN_HOST */ + unsigned int D8:1; /* PS2 */ + unsigned int D9:1; + unsigned int D10:1; + unsigned int D11:1; + unsigned int D12:1; /* RF1 */ + unsigned int D13:1; /* RF2 */ + unsigned int D14:1; /* ACK */ + unsigned int D15:1; /* NP */ + unsigned int D0:1; + unsigned int D1:1; + unsigned int D2:1; + unsigned int D3:1; + unsigned int D4:1; + unsigned int D5:1; /* FD */ + unsigned int D6:1; /* HD */ + unsigned int D7:1; /* PS1 */ +#endif + } bits; + + unsigned short AsUSHORT; + + #define D8_PS2 bits.D8 + #define D12_RF1 bits.D12 + #define D13_RF2 bits.D13 + #define D14_ACK bits.D14 + #define D15_NP bits.D15 + #define D5_FD bits.D5 + #define D6_HD bits.D6 + #define D7_PS1 bits.D7 + } TxConfig; + + /* Rx config data */ + union + { + /* The RxConfig register is arranged as follows: */ + /* */ + /* MSB LSB */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + struct + { +#ifdef BIG_ENDIAN_HOST + unsigned int D7:1; /* PS1 */ + unsigned int D6:1; /* HD */ + unsigned int D5:1; /* FD */ + unsigned int D4:1; + unsigned int D3:1; + unsigned int D2:1; + unsigned int D1:1; + unsigned int D0:1; + unsigned int D15:1; /* NP */ + unsigned int D14:1; /* ACK */ + unsigned int D13:1; /* RF2 */ + unsigned int D12:1; /* RF1 */ + unsigned int D11:1; + unsigned int D10:1; + unsigned int D9:1; + unsigned int D8:1; /* PS2 */ +#else /* BIG_ENDIAN_HOST */ + unsigned int D8:1; /* PS2 */ + unsigned int D9:1; + unsigned int D10:1; + unsigned int D11:1; + unsigned int D12:1; /* RF1 */ + unsigned int D13:1; /* RF2 */ + unsigned int D14:1; /* ACK */ + unsigned int D15:1; /* NP */ + unsigned int D0:1; + unsigned int D1:1; + unsigned int D2:1; + unsigned int D3:1; + unsigned int D4:1; + unsigned int D5:1; /* FD */ + unsigned int D6:1; /* HD */ + unsigned int D7:1; /* PS1 */ +#endif + } bits; + + unsigned short AsUSHORT; + } RxConfig; + + #define AN_CONFIG_NP 0x0080 + #define AN_CONFIG_ACK 0x0040 + #define AN_CONFIG_RF2 0x0020 + #define AN_CONFIG_RF1 0x0010 + #define AN_CONFIG_PS2 0x0001 + #define AN_CONFIG_PS1 0x8000 + #define AN_CONFIG_HD 0x4000 + #define AN_CONFIG_FD 0x2000 + + + /* Management registers. */ + + /* Control register. */ + union + { + struct + { + unsigned int an_enable:1; + unsigned int loopback:1; + unsigned int reset:1; + unsigned int restart_an:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_an_enable Mr0.bits.an_enable + #define mr_loopback Mr0.bits.loopback + #define mr_main_reset Mr0.bits.reset + #define mr_restart_an Mr0.bits.restart_an + } Mr0; + + /* Status register. */ + union + { + struct + { + unsigned int an_complete:1; + unsigned int link_ok:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_an_complete Mr1.bits.an_complete + #define mr_link_ok Mr1.bits.link_ok + } Mr1; + + /* Advertisement register. */ + union + { + struct + { + unsigned int reserved_4:5; + unsigned int full_duplex:1; + unsigned int half_duplex:1; + unsigned int sym_pause:1; + unsigned int asym_pause:1; + unsigned int reserved_11:3; + unsigned int remote_fault1:1; + unsigned int remote_fault2:1; + unsigned int reserved_14:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_adv_full_duplex Mr4.bits.full_duplex + #define mr_adv_half_duplex Mr4.bits.half_duplex + #define mr_adv_sym_pause Mr4.bits.sym_pause + #define mr_adv_asym_pause Mr4.bits.asym_pause + #define mr_adv_remote_fault1 Mr4.bits.remote_fault1 + #define mr_adv_remote_fault2 Mr4.bits.remote_fault2 + #define mr_adv_next_page Mr4.bits.next_page + } Mr4; + + /* Link partner advertisement register. */ + union + { + struct + { + unsigned int reserved_4:5; + unsigned int lp_full_duplex:1; + unsigned int lp_half_duplex:1; + unsigned int lp_sym_pause:1; + unsigned int lp_asym_pause:1; + unsigned int reserved_11:3; + unsigned int lp_remote_fault1:1; + unsigned int lp_remote_fault2:1; + unsigned int lp_ack:1; + unsigned int lp_next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_lp_adv_full_duplex Mr5.bits.lp_full_duplex + #define mr_lp_adv_half_duplex Mr5.bits.lp_half_duplex + #define mr_lp_adv_sym_pause Mr5.bits.lp_sym_pause + #define mr_lp_adv_asym_pause Mr5.bits.lp_asym_pause + #define mr_lp_adv_remote_fault1 Mr5.bits.lp_remote_fault1 + #define mr_lp_adv_remote_fault2 Mr5.bits.lp_remote_fault2 + #define mr_lp_adv_next_page Mr5.bits.lp_next_page + } Mr5; + + /* Auto-negotiation expansion register. */ + union + { + struct + { + unsigned int reserved_0:1; + unsigned int page_received:1; + unsigned int next_pageable:1; + unsigned int reserved_15:13; + } bits; + + unsigned short AsUSHORT; + } Mr6; + + /* Auto-negotiation next page transmit register. */ + union + { + struct + { + unsigned int code_field:11; + unsigned int toggle:1; + unsigned int ack2:1; + unsigned int message_page:1; + unsigned int reserved_14:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_np_tx Mr7.AsUSHORT + } Mr7; + + /* Auto-negotiation link partner ability register. */ + union + { + struct + { + unsigned int code_field:11; + unsigned int toggle:1; + unsigned int ack2:1; + unsigned int message_page:1; + unsigned int ack:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_lp_np_rx Mr8.AsUSHORT + } Mr8; + + /* Extended status register. */ + union + { + struct + { + unsigned int reserved_11:12; + unsigned int base1000_t_hd:1; + unsigned int base1000_t_fd:1; + unsigned int base1000_x_hd:1; + unsigned int base1000_x_fd:1; + } bits; + + unsigned short AsUSHORT; + } Mr15; + + /* Miscellaneous state variables. */ + union + { + struct + { + unsigned int toggle_tx:1; + unsigned int toggle_rx:1; + unsigned int np_rx:1; + unsigned int page_rx:1; + unsigned int np_loaded:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_toggle_tx MrMisc.bits.toggle_tx + #define mr_toggle_rx MrMisc.bits.toggle_rx + #define mr_np_rx MrMisc.bits.np_rx + #define mr_page_rx MrMisc.bits.page_rx + #define mr_np_loaded MrMisc.bits.np_loaded + } MrMisc; + + + /* Implement specifics */ + + /* Pointer to the operating system specific data structure. */ + void *pContext; +} AN_STATE_INFO, *PAN_STATE_INFO; + + +/******************************************************************************/ +/* Return code of Autoneg8023z. */ +/******************************************************************************/ + +typedef enum +{ + AUTONEG_STATUS_OK = 0, + AUTONEG_STATUS_DONE = 1, + AUTONEG_STATUS_TIMER_ENABLED = 2, + AUTONEG_STATUS_FAILED = 0xfffffff +} AUTONEG_STATUS, *PAUTONEG_STATUS; + + +/******************************************************************************/ +/* Function prototypes. */ +/******************************************************************************/ + +AUTONEG_STATUS Autoneg8023z(PAN_STATE_INFO pAnInfo); +void AutonegInit(PAN_STATE_INFO pAnInfo); + + +/******************************************************************************/ +/* The following functions are defined in the os-dependent module. */ +/******************************************************************************/ + +void MM_AnTxConfig(PAN_STATE_INFO pAnInfo); +void MM_AnTxIdle(PAN_STATE_INFO pAnInfo); +char MM_AnRxConfig(PAN_STATE_INFO pAnInfo, unsigned short *pRxConfig); + + +#endif /* AUTONEG_H */ diff --git a/drivers/bcm570x_bits.h b/drivers/bcm570x_bits.h new file mode 100644 index 0000000..615d61e --- /dev/null +++ b/drivers/bcm570x_bits.h @@ -0,0 +1,57 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef BITS_H +#define BITS_H + + +/******************************************************************************/ +/* Bit Mask definitions */ +/******************************************************************************/ +#define BIT_NONE 0x00 +#define BIT_0 0x01 +#define BIT_1 0x02 +#define BIT_2 0x04 +#define BIT_3 0x08 +#define BIT_4 0x10 +#define BIT_5 0x20 +#define BIT_6 0x40 +#define BIT_7 0x80 +#define BIT_8 0x0100 +#define BIT_9 0x0200 +#define BIT_10 0x0400 +#define BIT_11 0x0800 +#define BIT_12 0x1000 +#define BIT_13 0x2000 +#define BIT_14 0x4000 +#define BIT_15 0x8000 +#define BIT_16 0x010000 +#define BIT_17 0x020000 +#define BIT_18 0x040000 +#define BIT_19 0x080000 +#define BIT_20 0x100000 +#define BIT_21 0x200000 +#define BIT_22 0x400000 +#define BIT_23 0x800000 +#define BIT_24 0x01000000 +#define BIT_25 0x02000000 +#define BIT_26 0x04000000 +#define BIT_27 0x08000000 +#define BIT_28 0x10000000 +#define BIT_29 0x20000000 +#define BIT_30 0x40000000 +#define BIT_31 0x80000000 + +#endif /* BITS_H */ diff --git a/drivers/bcm570x_debug.h b/drivers/bcm570x_debug.h new file mode 100644 index 0000000..88e209b --- /dev/null +++ b/drivers/bcm570x_debug.h @@ -0,0 +1,109 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef DEBUG_H +#define DEBUG_H + +#ifdef VXWORKS +#include +#endif + +/******************************************************************************/ +/* Debug macros */ +/******************************************************************************/ + +/* Code path for controlling output debug messages. */ +/* Define your code path here. */ +#define CP_INIT 0x010000 +#define CP_SEND 0x020000 +#define CP_RCV 0x040000 +#define CP_INT 0x080000 +#define CP_UINIT 0x100000 +#define CP_RESET 0x200000 + +#define CP_ALL (CP_INIT | CP_SEND | CP_RCV | CP_INT | \ + CP_RESET | CP_UINIT) + +#define CP_MASK 0xffff0000 + + +/* Debug message levels. */ +#define LV_VERBOSE 0x03 +#define LV_INFORM 0x02 +#define LV_WARN 0x01 +#define LV_FATAL 0x00 + +#define LV_MASK 0xffff + + +/* Code path and messsage level combined. These are the first argument of */ +/* the DbgMessage macro. */ +#define INIT_V (CP_INIT | LV_VERBOSE) +#define INIT_I (CP_INIT | LV_INFORM) +#define INIT_W (CP_INIT | LV_WARN) +#define SEND_V (CP_SEND | LV_VERBOSE) +#define SEND_I (CP_SEND | LV_INFORM) +#define SEND_W (CP_SEND | LV_WARN) +#define RCV_V (CP_RCV | LV_VERBOSE) +#define RCV_I (CP_RCV | LV_INFORM) +#define RCV_W (CP_RCV | LV_WARN) +#define INT_V (CP_INT | LV_VERBOSE) +#define INT_I (CP_INT | LV_INFORM) +#define INT_W (CP_INT | LV_WARN) +#define UINIT_V (CP_UINIT | LV_VERBOSE) +#define UINIT_I (CP_UINIT | LV_INFORM) +#define UINIT_W (CP_UINIT | LV_WARN) +#define RESET_V (CP_RESET | LV_VERBOSE) +#define RESET_I (CP_RESET | LV_INFORM) +#define RESET_W (CP_RESET | LV_WARN) +#define CPALL_V (CP_ALL | LV_VERBOSE) +#define CPALL_I (CP_ALL | LV_INFORM) +#define CPALL_W (CP_ALL | LV_WARN) + + +/* All code path message levels. */ +#define FATAL (CP_ALL | LV_FATAL) +#define WARN (CP_ALL | LV_WARN) +#define INFORM (CP_ALL | LV_INFORM) +#define VERBOSE (CP_ALL | LV_VERBOSE) + + +/* These constants control the message output. */ +/* Set your debug message output level and code path here. */ +#ifndef DBG_MSG_CP +#define DBG_MSG_CP CP_ALL /* Where to output messages. */ +#endif + +#ifndef DBG_MSG_LV +#define DBG_MSG_LV LV_VERBOSE /* Level of message output. */ +#endif + +/* DbgMessage macro. */ +#if DBG +#define DbgMessage(CNTRL, MESSAGE) \ + if((CNTRL & DBG_MSG_CP) && ((CNTRL & LV_MASK) <= DBG_MSG_LV)) \ + printf MESSAGE +#define DbgBreak() DbgBreakPoint() +#undef STATIC +#define STATIC +#else +#define DbgMessage(CNTRL, MESSAGE) +#define DbgBreak() +#undef STATIC +#define STATIC static +#endif /* DBG */ + + +#endif /* DEBUG_H */ diff --git a/drivers/bcm570x_lm.h b/drivers/bcm570x_lm.h new file mode 100644 index 0000000..607f3fd --- /dev/null +++ b/drivers/bcm570x_lm.h @@ -0,0 +1,451 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef LM_H +#define LM_H + +#include "bcm570x_queue.h" +#include "bcm570x_bits.h" + + +/******************************************************************************/ +/* Basic types. */ +/******************************************************************************/ + +typedef char LM_CHAR, *PLM_CHAR; +typedef unsigned int LM_UINT, *PLM_UINT; +typedef unsigned char LM_UINT8, *PLM_UINT8; +typedef unsigned short LM_UINT16, *PLM_UINT16; +typedef unsigned int LM_UINT32, *PLM_UINT32; +typedef unsigned int LM_COUNTER, *PLM_COUNTER; +typedef void LM_VOID, *PLM_VOID; +typedef char LM_BOOL, *PLM_BOOL; + +/* 64bit value. */ +typedef struct { +#ifdef BIG_ENDIAN_HOST + LM_UINT32 High; + LM_UINT32 Low; +#else /* BIG_ENDIAN_HOST */ + LM_UINT32 Low; + LM_UINT32 High; +#endif /* !BIG_ENDIAN_HOST */ +} LM_UINT64, *PLM_UINT64; + +typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; + +/* void LM_INC_PHYSICAL_ADDRESS(PLM_PHYSICAL_ADDRESS pAddr,LM_UINT32 IncSize) */ +#define LM_INC_PHYSICAL_ADDRESS(pAddr, IncSize) \ + { \ + LM_UINT32 OrgLow; \ + \ + OrgLow = (pAddr)->Low; \ + (pAddr)->Low += IncSize; \ + if((pAddr)->Low < OrgLow) { \ + (pAddr)->High++; /* Wrap around. */ \ + } \ + } + + +#ifndef NULL +#define NULL ((void *) 0) +#endif /* NULL */ + +#ifndef OFFSETOF +#define OFFSETOF(_s, _m) (MM_UINT_PTR(&(((_s *) 0)->_m))) +#endif /* OFFSETOF */ + + +/******************************************************************************/ +/* Simple macros. */ +/******************************************************************************/ + +#define IS_ETH_BROADCAST(_pEthAddr) \ + (((unsigned char *) (_pEthAddr))[0] == ((unsigned char) 0xff)) + +#define IS_ETH_MULTICAST(_pEthAddr) \ + (((unsigned char *) (_pEthAddr))[0] & ((unsigned char) 0x01)) + +#define IS_ETH_ADDRESS_EQUAL(_pEtherAddr1, _pEtherAddr2) \ + ((((unsigned char *) (_pEtherAddr1))[0] == \ + ((unsigned char *) (_pEtherAddr2))[0]) && \ + (((unsigned char *) (_pEtherAddr1))[1] == \ + ((unsigned char *) (_pEtherAddr2))[1]) && \ + (((unsigned char *) (_pEtherAddr1))[2] == \ + ((unsigned char *) (_pEtherAddr2))[2]) && \ + (((unsigned char *) (_pEtherAddr1))[3] == \ + ((unsigned char *) (_pEtherAddr2))[3]) && \ + (((unsigned char *) (_pEtherAddr1))[4] == \ + ((unsigned char *) (_pEtherAddr2))[4]) && \ + (((unsigned char *) (_pEtherAddr1))[5] == \ + ((unsigned char *) (_pEtherAddr2))[5])) + +#define COPY_ETH_ADDRESS(_Src, _Dst) \ + ((unsigned char *) (_Dst))[0] = ((unsigned char *) (_Src))[0]; \ + ((unsigned char *) (_Dst))[1] = ((unsigned char *) (_Src))[1]; \ + ((unsigned char *) (_Dst))[2] = ((unsigned char *) (_Src))[2]; \ + ((unsigned char *) (_Dst))[3] = ((unsigned char *) (_Src))[3]; \ + ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \ + ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5]; + + +/******************************************************************************/ +/* Constants. */ +/******************************************************************************/ + +#define ETHERNET_ADDRESS_SIZE 6 +#define ETHERNET_PACKET_HEADER_SIZE 14 +#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */ +#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */ +#define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60 +#define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514 +#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */ + +#ifndef LM_MAX_MC_TABLE_SIZE +#define LM_MAX_MC_TABLE_SIZE 32 +#endif /* LM_MAX_MC_TABLE_SIZE */ +#define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1) +#define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1) + + +/* Receive filter masks. */ +#define LM_ACCEPT_UNICAST 0x0001 +#define LM_ACCEPT_MULTICAST 0x0002 +#define LM_ACCEPT_ALL_MULTICAST 0x0004 +#define LM_ACCEPT_BROADCAST 0x0008 +#define LM_ACCEPT_ERROR_PACKET 0x0010 + +#define LM_PROMISCUOUS_MODE 0x10000 + + +/******************************************************************************/ +/* PCI registers. */ +/******************************************************************************/ + +#define PCI_VENDOR_ID_REG 0x00 +#define PCI_DEVICE_ID_REG 0x02 + +#define PCI_COMMAND_REG 0x04 +#define PCI_IO_SPACE_ENABLE 0x0001 +#define PCI_MEM_SPACE_ENABLE 0x0002 +#define PCI_BUSMASTER_ENABLE 0x0004 +#define PCI_MEMORY_WRITE_INVALIDATE 0x0010 +#define PCI_PARITY_ERROR_ENABLE 0x0040 +#define PCI_SYSTEM_ERROR_ENABLE 0x0100 +#define PCI_FAST_BACK_TO_BACK_ENABLE 0x0200 + +#define PCI_STATUS_REG 0x06 +#define PCI_REV_ID_REG 0x08 + +#define PCI_CACHE_LINE_SIZE_REG 0x0c + +#define PCI_IO_BASE_ADDR_REG 0x10 +#define PCI_IO_BASE_ADDR_MASK 0xfffffff0 + +#define PCI_MEM_BASE_ADDR_LOW 0x10 +#define PCI_MEM_BASE_ADDR_HIGH 0x14 + +#define PCI_SUBSYSTEM_VENDOR_ID_REG 0x2c +#define PCI_SUBSYSTEM_ID_REG 0x2e +#define PCI_INT_LINE_REG 0x3c + +#define PCIX_CAP_REG 0x40 +#define PCIX_ENABLE_RELAXED_ORDERING BIT_17 + +/******************************************************************************/ +/* Fragment structure. */ +/******************************************************************************/ + +typedef struct { + LM_UINT32 FragSize; + LM_PHYSICAL_ADDRESS FragBuf; +} LM_FRAG, *PLM_FRAG; + +typedef struct { + /* FragCount is initialized for the caller to the maximum array size, on */ + /* return FragCount is the number of the actual fragments in the array. */ + LM_UINT32 FragCount; + + /* Total buffer size. */ + LM_UINT32 TotalSize; + + /* Fragment array buffer. */ + LM_FRAG Fragments[1]; +} LM_FRAG_LIST, *PLM_FRAG_LIST; + +#define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \ + typedef struct { \ + LM_FRAG_LIST FragList; \ + LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \ + } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME + + +/******************************************************************************/ +/* Status codes. */ +/******************************************************************************/ + +#define LM_STATUS_SUCCESS 0 +#define LM_STATUS_FAILURE 1 + +#define LM_STATUS_INTERRUPT_ACTIVE 2 +#define LM_STATUS_INTERRUPT_NOT_ACTIVE 3 + +#define LM_STATUS_LINK_ACTIVE 4 +#define LM_STATUS_LINK_DOWN 5 +#define LM_STATUS_LINK_SETTING_MISMATCH 6 + +#define LM_STATUS_TOO_MANY_FRAGMENTS 7 +#define LM_STATUS_TRANSMIT_ABORTED 8 +#define LM_STATUS_TRANSMIT_ERROR 9 +#define LM_STATUS_RECEIVE_ABORTED 10 +#define LM_STATUS_RECEIVE_ERROR 11 +#define LM_STATUS_INVALID_PACKET_SIZE 12 +#define LM_STATUS_OUT_OF_MAP_REGISTERS 13 +#define LM_STATUS_UNKNOWN_ADAPTER 14 + +typedef LM_UINT LM_STATUS, *PLM_STATUS; + + +/******************************************************************************/ +/* Requested media type. */ +/******************************************************************************/ + +#define LM_REQUESTED_MEDIA_TYPE_AUTO 0 +#define LM_REQUESTED_MEDIA_TYPE_BNC 1 +#define LM_REQUESTED_MEDIA_TYPE_UTP_AUTO 2 +#define LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS 3 +#define LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX 4 +#define LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS 5 +#define LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX 6 +#define LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS 7 +#define LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX 8 +#define LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS 9 +#define LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX 10 +#define LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS 11 +#define LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX 12 +#define LM_REQUESTED_MEDIA_TYPE_MAC_LOOPBACK 0xfffe +#define LM_REQUESTED_MEDIA_TYPE_PHY_LOOPBACK 0xffff + +typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE; + + +/******************************************************************************/ +/* Media type. */ +/******************************************************************************/ + +#define LM_MEDIA_TYPE_UNKNOWN -1 +#define LM_MEDIA_TYPE_AUTO 0 +#define LM_MEDIA_TYPE_UTP 1 +#define LM_MEDIA_TYPE_BNC 2 +#define LM_MEDIA_TYPE_AUI 3 +#define LM_MEDIA_TYPE_FIBER 4 + +typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE; + + +/******************************************************************************/ +/* Line speed. */ +/******************************************************************************/ + +#define LM_LINE_SPEED_UNKNOWN 0 +#define LM_LINE_SPEED_10MBPS 1 +#define LM_LINE_SPEED_100MBPS 2 +#define LM_LINE_SPEED_1000MBPS 3 + +typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; + + +/******************************************************************************/ +/* Duplex mode. */ +/******************************************************************************/ + +#define LM_DUPLEX_MODE_UNKNOWN 0 +#define LM_DUPLEX_MODE_HALF 1 +#define LM_DUPLEX_MODE_FULL 2 + +typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; + + +/******************************************************************************/ +/* Power state. */ +/******************************************************************************/ + +#define LM_POWER_STATE_D0 0 +#define LM_POWER_STATE_D1 1 +#define LM_POWER_STATE_D2 2 +#define LM_POWER_STATE_D3 3 + +typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; + + +/******************************************************************************/ +/* Task offloading. */ +/******************************************************************************/ + +#define LM_TASK_OFFLOAD_NONE 0x0000 +#define LM_TASK_OFFLOAD_TX_IP_CHECKSUM 0x0001 +#define LM_TASK_OFFLOAD_RX_IP_CHECKSUM 0x0002 +#define LM_TASK_OFFLOAD_TX_TCP_CHECKSUM 0x0004 +#define LM_TASK_OFFLOAD_RX_TCP_CHECKSUM 0x0008 +#define LM_TASK_OFFLOAD_TX_UDP_CHECKSUM 0x0010 +#define LM_TASK_OFFLOAD_RX_UDP_CHECKSUM 0x0020 +#define LM_TASK_OFFLOAD_TCP_SEGMENTATION 0x0040 + +typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; + + +/******************************************************************************/ +/* Flow control. */ +/******************************************************************************/ + +#define LM_FLOW_CONTROL_NONE 0x00 +#define LM_FLOW_CONTROL_RECEIVE_PAUSE 0x01 +#define LM_FLOW_CONTROL_TRANSMIT_PAUSE 0x02 +#define LM_FLOW_CONTROL_RX_TX_PAUSE (LM_FLOW_CONTROL_RECEIVE_PAUSE | \ + LM_FLOW_CONTROL_TRANSMIT_PAUSE) + +/* This value can be or-ed with RECEIVE_PAUSE and TRANSMIT_PAUSE. If the */ +/* auto-negotiation is disabled and the RECEIVE_PAUSE and TRANSMIT_PAUSE */ +/* bits are set, then flow control is enabled regardless of link partner's */ +/* flow control capability. */ +#define LM_FLOW_CONTROL_AUTO_PAUSE 0x80000000 + +typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; + + +/******************************************************************************/ +/* Wake up mode. */ +/******************************************************************************/ + +#define LM_WAKE_UP_MODE_NONE 0 +#define LM_WAKE_UP_MODE_MAGIC_PACKET 1 +#define LM_WAKE_UP_MODE_NWUF 2 +#define LM_WAKE_UP_MODE_LINK_CHANGE 4 + +typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; + + +/******************************************************************************/ +/* Counters. */ +/******************************************************************************/ + +#define LM_COUNTER_FRAMES_XMITTED_OK 0 +#define LM_COUNTER_FRAMES_RECEIVED_OK 1 +#define LM_COUNTER_ERRORED_TRANSMIT_COUNT 2 +#define LM_COUNTER_ERRORED_RECEIVE_COUNT 3 +#define LM_COUNTER_RCV_CRC_ERROR 4 +#define LM_COUNTER_ALIGNMENT_ERROR 5 +#define LM_COUNTER_SINGLE_COLLISION_FRAMES 6 +#define LM_COUNTER_MULTIPLE_COLLISION_FRAMES 7 +#define LM_COUNTER_FRAMES_DEFERRED 8 +#define LM_COUNTER_MAX_COLLISIONS 9 +#define LM_COUNTER_RCV_OVERRUN 10 +#define LM_COUNTER_XMIT_UNDERRUN 11 +#define LM_COUNTER_UNICAST_FRAMES_XMIT 12 +#define LM_COUNTER_MULTICAST_FRAMES_XMIT 13 +#define LM_COUNTER_BROADCAST_FRAMES_XMIT 14 +#define LM_COUNTER_UNICAST_FRAMES_RCV 15 +#define LM_COUNTER_MULTICAST_FRAMES_RCV 16 +#define LM_COUNTER_BROADCAST_FRAMES_RCV 17 + +typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE; + + +/******************************************************************************/ +/* Forward definition. */ +/******************************************************************************/ + +typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK; +typedef struct _LM_PACKET *PLM_PACKET; + + +/******************************************************************************/ +/* Function prototypes. */ +/******************************************************************************/ + +LM_STATUS LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask); +LM_STATUS LM_Halt(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastClear(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress); +LM_STATUS LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress); + +LM_UINT32 LM_GetCrcCounter(PLM_DEVICE_BLOCK pDevice); + +LM_WAKE_UP_MODE LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 *pByteMask, LM_UINT8 *pPattern); +LM_STATUS LM_NwufRemove(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 *pByteMask, LM_UINT8 *pPattern); +LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel); + +LM_VOID LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + PLM_UINT32 pData32); +LM_VOID LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + LM_UINT32 Data32); + +LM_STATUS LM_ControlLoopBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control); +LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice); +int LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration); + + +/******************************************************************************/ +/* These are the OS specific functions called by LMAC. */ +/******************************************************************************/ + +LM_STATUS MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 *pValue16); +LM_STATUS MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 Value16); +LM_STATUS MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 *pValue32); +LM_STATUS MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 Value32); +LM_STATUS MM_MapMemBase(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_MapIoBase(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt); +LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, + LM_BOOL Cached); +LM_STATUS MM_GetConfig(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status); +LM_STATUS MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS LM_MbufWorkAround(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetLinkSpeed(PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); + +#if INCLUDE_5703_A0_FIX +LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice); +#endif + + +#endif /* LM_H */ diff --git a/drivers/bcm570x_mm.h b/drivers/bcm570x_mm.h new file mode 100644 index 0000000..b7cbf8a --- /dev/null +++ b/drivers/bcm570x_mm.h @@ -0,0 +1,160 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/******************************************************************************/ + +#ifndef MM_H +#define MM_H + +#define __raw_readl readl +#define __raw_writel writel + +#define BIG_ENDIAN_HOST 1 +#define readl(addr) (*(volatile unsigned int*)(addr)) +#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) + +/* Define memory barrier function here if needed */ +#define wmb() +#define membar() +#include +#include +#include "bcm570x_lm.h" +#include "bcm570x_queue.h" +#include "tigon3.h" +#include + +#define FALSE 0 +#define TRUE 1 +#define ERROR -1 + +#if DBG +#define STATIC +#else +#define STATIC static +#endif + +extern int MM_Packet_Desc_Size; + +#define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size + +DECLARE_QUEUE_TYPE(UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT+1); + +#define MAX_MEM 16 + +/* Synch */ +typedef int mutex_t; +typedef int spinlock_t; + +/* Embedded device control */ +typedef struct _UM_DEVICE_BLOCK { + LM_DEVICE_BLOCK lm_dev; + pci_dev_t pdev; + char *name; + void *mem_list[MAX_MEM]; + dma_addr_t dma_list[MAX_MEM]; + int mem_size_list[MAX_MEM]; + int mem_list_num; + int mtu; + int index; + int opened; + int delayed_link_ind; /* Delay link status during initial load */ + int adapter_just_inited; /* the first few seconds after init. */ + int spurious_int; /* new -- unsupported */ + int timer_interval; + int adaptive_expiry; + int crc_counter_expiry; /* new -- unsupported */ + int poll_tib_expiry; /* new -- unsupported */ + int tx_full; + int tx_queued; + int line_speed; /* in Mbps, 0 if link is down */ + UM_RX_PACKET_Q rx_out_of_buf_q; + int rx_out_of_buf; + int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */ + int rx_buf_repl_panic_thresh; + int rx_buf_align; /* new -- unsupported */ + int do_global_lock; + mutex_t global_lock; + mutex_t undi_lock; + long undi_flags; + volatile int interrupt; + int tasklet_pending; + int tasklet_busy; /* new -- unsupported */ + int rx_pkt; + int tx_pkt; +#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */ + void (*nice_rx)(void*, void* ); + void* nice_ctx; +#endif /* NICE_SUPPORT */ + int rx_adaptive_coalesce; + unsigned int rx_last_cnt; + unsigned int tx_last_cnt; + unsigned int rx_curr_coalesce_frames; + unsigned int rx_curr_coalesce_ticks; + unsigned int tx_curr_coalesce_frames; /* new -- unsupported */ +#if TIGON3_DEBUG /* new -- unsupported */ + uint tx_zc_count; + uint tx_chksum_count; + uint tx_himem_count; + uint rx_good_chksum_count; +#endif + unsigned int rx_bad_chksum_count; /* new -- unsupported */ + unsigned int rx_misc_errors; /* new -- unsupported */ +} UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK; + + +/* Physical/PCI DMA address */ +typedef union { + dma_addr_t dma_map; +} dma_map_t; + +/* Packet */ +typedef struct +_UM_PACKET { + LM_PACKET lm_packet; + void* skbuff; /* Address of packet buffer */ +} UM_PACKET, *PUM_PACKET; + +#define MM_ACQUIRE_UNDI_LOCK(_pDevice) +#define MM_RELEASE_UNDI_LOCK(_pDevice) +#define MM_ACQUIRE_INT_LOCK(_pDevice) +#define MM_RELEASE_INT_LOCK(_pDevice) +#define MM_UINT_PTR(_ptr) ((unsigned long) (_ptr)) + +/* Macro for setting 64bit address struct */ +#define set_64bit_addr(paddr, low, high) \ + (paddr)->Low = low; \ + (paddr)->High = high; + +/* Assume that PCI controller's view of host memory is same as host */ + +#define MEM_TO_PCI_PHYS(addr) (addr) + +extern void MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr); +extern void MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr); +extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR *paddr, + LM_UINT32 *len, int frag); +extern void MM_MapRxDma ( PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR *paddr); + + +/* BSP needs to provide sysUsecDelay and sysSerialPrintString */ +extern void sysSerialPrintString (char *s); +#define MM_Wait(usec) udelay(usec) + +/* Define memory barrier function here if needed */ +#define wmb() + +#if 0 +#define cpu_to_le32(val) LONGSWAP(val) +#endif +#endif /* MM_H */ diff --git a/drivers/bcm570x_queue.h b/drivers/bcm570x_queue.h new file mode 100644 index 0000000..336b3ca --- /dev/null +++ b/drivers/bcm570x_queue.h @@ -0,0 +1,387 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* Queue functions. */ +/* void QQ_InitQueue(PQQ_CONTAINER pQueue) */ +/* char QQ_Full(PQQ_CONTAINER pQueue) */ +/* char QQ_Empty(PQQ_CONTAINER pQueue) */ +/* unsigned int QQ_GetSize(PQQ_CONTAINER pQueue) */ +/* unsigned int QQ_GetEntryCnt(PQQ_CONTAINER pQueue) */ +/* char QQ_PushHead(PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) */ +/* char QQ_PushTail(PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) */ +/* PQQ_ENTRY QQ_PopHead(PQQ_CONTAINER pQueue) */ +/* PQQ_ENTRY QQ_PopTail(PQQ_CONTAINER pQueue) */ +/* PQQ_ENTRY QQ_GetHead(PQQ_CONTAINER pQueue, unsigned int Idx) */ +/* PQQ_ENTRY QQ_GetTail(PQQ_CONTAINER pQueue, unsigned int Idx) */ +/* */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef BCM_QUEUE_H +#define BCM_QUEUE_H +#ifndef EMBEDDED +#define EMBEDDED 1 +#endif + +/******************************************************************************/ +/* Queue definitions. */ +/******************************************************************************/ + +/* Entry for queueing. */ +typedef void *PQQ_ENTRY; + +/* Linux Atomic Ops support */ +typedef struct { int counter; } atomic_t; + + +/* + * This combination of `inline' and `extern' has almost the effect of a + * macro. The way to use it is to put a function definition in a header + * file with these keywords, and put another copy of the definition + * (lacking `inline' and `extern') in a library file. The definition in + * the header file will cause most calls to the function to be inlined. + * If any uses of the function remain, they will refer to the single copy + * in the library. + */ +extern __inline void +atomic_set(atomic_t* entry, int val) +{ + entry->counter = val; +} +extern __inline int +atomic_read(atomic_t* entry) +{ + return entry->counter; +} +extern __inline void +atomic_inc(atomic_t* entry) +{ + if(entry) + entry->counter++; +} + +extern __inline void +atomic_dec(atomic_t* entry) +{ + if(entry) + entry->counter--; +} + +extern __inline void +atomic_sub(int a, atomic_t* entry) +{ + if(entry) + entry->counter -= a; +} +extern __inline void +atomic_add(int a, atomic_t* entry) +{ + if(entry) + entry->counter += a; +} + + +/* Queue header -- base type. */ +typedef struct { + unsigned int Head; + unsigned int Tail; + unsigned int Size; + atomic_t EntryCnt; + PQQ_ENTRY Array[1]; +} QQ_CONTAINER, *PQQ_CONTAINER; + + +/* Declare queue type macro. */ +#define DECLARE_QUEUE_TYPE(_QUEUE_TYPE, _QUEUE_SIZE) \ + \ + typedef struct { \ + QQ_CONTAINER Container; \ + PQQ_ENTRY EntryBuffer[_QUEUE_SIZE]; \ + } _QUEUE_TYPE, *P##_QUEUE_TYPE + + +/******************************************************************************/ +/* Compilation switches. */ +/******************************************************************************/ + +#if DBG +#undef QQ_NO_OVERFLOW_CHECK +#undef QQ_NO_UNDERFLOW_CHECK +#endif /* DBG */ + +#ifdef QQ_USE_MACROS +/* notdone */ +#else + +#ifdef QQ_NO_INLINE +#define __inline +#endif /* QQ_NO_INLINE */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline void +QQ_InitQueue( +PQQ_CONTAINER pQueue, +unsigned int QueueSize) { + pQueue->Head = 0; + pQueue->Tail = 0; + pQueue->Size = QueueSize+1; + atomic_set(&pQueue->EntryCnt, 0); +} /* QQ_InitQueue */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline char +QQ_Full( +PQQ_CONTAINER pQueue) { + unsigned int NewHead; + + NewHead = (pQueue->Head + 1) % pQueue->Size; + + return(NewHead == pQueue->Tail); +} /* QQ_Full */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline char +QQ_Empty( +PQQ_CONTAINER pQueue) { + return(pQueue->Head == pQueue->Tail); +} /* QQ_Empty */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline unsigned int +QQ_GetSize( +PQQ_CONTAINER pQueue) { + return pQueue->Size; +} /* QQ_GetSize */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline unsigned int +QQ_GetEntryCnt( +PQQ_CONTAINER pQueue) { + return atomic_read(&pQueue->EntryCnt); +} /* QQ_GetEntryCnt */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +extern __inline char +QQ_PushHead( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Head; + + Head = (pQueue->Head + 1) % pQueue->Size; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Head == pQueue->Tail) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[pQueue->Head] = pEntry; + wmb(); + pQueue->Head = Head; + atomic_inc(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushHead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +extern __inline char +QQ_PushTail( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Tail; + + Tail = pQueue->Tail; + if(Tail == 0) { + Tail = pQueue->Size; + } /* if */ + Tail--; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Tail == pQueue->Head) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[Tail] = pEntry; + wmb(); + pQueue->Tail = Tail; + atomic_inc(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushTail */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline PQQ_ENTRY +QQ_PopHead( +PQQ_CONTAINER pQueue) { + unsigned int Head; + PQQ_ENTRY Entry; + + Head = pQueue->Head; + +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Head == pQueue->Tail) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + if(Head == 0) { + Head = pQueue->Size; + } /* if */ + Head--; + + Entry = pQueue->Array[Head]; +#ifdef EMBEDDED + membar(); +#else + mb(); +#endif + pQueue->Head = Head; + atomic_dec(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopHead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline PQQ_ENTRY +QQ_PopTail( +PQQ_CONTAINER pQueue) { + unsigned int Tail; + PQQ_ENTRY Entry; + + Tail = pQueue->Tail; + +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Tail == pQueue->Head) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + Entry = pQueue->Array[Tail]; +#ifdef EMBEDDED + membar(); +#else + mb(); +#endif + pQueue->Tail = (Tail + 1) % pQueue->Size; + atomic_dec(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopTail */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline PQQ_ENTRY +QQ_GetHead( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= atomic_read(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + if(pQueue->Head > Idx) + { + Idx = pQueue->Head - Idx; + } + else + { + Idx = pQueue->Size - (Idx - pQueue->Head); + } + Idx--; + + return pQueue->Array[Idx]; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline PQQ_ENTRY +QQ_GetTail( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= atomic_read(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + Idx += pQueue->Tail; + if(Idx >= pQueue->Size) + { + Idx = Idx - pQueue->Size; + } + + return pQueue->Array[Idx]; +} + +#endif /* QQ_USE_MACROS */ + + +#endif /* QUEUE_H */ diff --git a/drivers/cfb_console.c b/drivers/cfb_console.c new file mode 100644 index 0000000..9727aeb --- /dev/null +++ b/drivers/cfb_console.c @@ -0,0 +1,1274 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * cfb_console.c + * + * Color Framebuffer Console driver for 8/15/16/24/32 bits per pixel. + * + * At the moment only the 8x16 font is tested and the font fore- and + * background color is limited to black/white/gray colors. The Linux + * logo can be placed in the upper left corner and additional board + * information strings (that normaly goes to serial port) can be drawed. + * + * The console driver can use the standard PC keyboard interface (i8042) + * for character input. Character output goes to a memory mapped video + * framebuffer with little or big-endian organisation. + * With environment setting 'console=serial' the console i/o can be + * forced to serial port. + + The driver uses graphic specific defines/parameters/functions: + + (for SMI LynxE graphic chip) + + CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810 + VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian + VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill + VIDEO_HW_BITBLT - graphic driver supports hardware bit blt + + Console Parameters are set by graphic drivers global struct: + + VIDEO_VISIBLE_COLS - x resolution + VIDEO_VISIBLE_ROWS - y resolution + VIDEO_PIXEL_SIZE - storage size in byte per pixel + VIDEO_DATA_FORMAT - graphical data format GDF + VIDEO_FB_ADRS - start of video memory + + CONFIG_I8042_KBD - AT Keyboard driver for i8042 + VIDEO_KBD_INIT_FCT - init function for keyboard + VIDEO_TSTC_FCT - keyboard_tstc function + VIDEO_GETC_FCT - keyboard_getc function + + CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with delay + loop in VIDEO_TSTC_FCT (i8042) + CFG_CONSOLE_BLINK_COUNT - value for delay loop - blink rate + CONFIG_CONSOLE_TIME - display time/date in upper right corner, + needs CFG_CMD_DATE and CONFIG_CONSOLE_CURSOR + CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner + CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo + CONFIG_CONSOLE_EXTRA_INFO - display additional board information strings + that normaly goes to serial port. This define + requires a board specific function: + video_drawstring (VIDEO_INFO_X, + VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, + info); + that fills a info buffer at i=row. + s.a: board/eltec/bab7xx. +CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be initialised + as an output only device. The Keyboard driver + will not be set-up. This may be used, if you + have none or more than one Keyboard devices + (USB Keyboard, AT Keyboard). + +CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last character. No + blinking is provided. Uses the macros CURSOR_SET + and CURSOR_OFF. +CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the + graphic chip. Uses the macro CURSOR_SET. + ATTENTION: If booting an OS, the display driver + must disable the hardware register of the graphic + chip. Otherwise a blinking field is displayed +*/ + +#include + +#ifdef CONFIG_CFB_CONSOLE + +#include + +/*****************************************************************************/ +/* Console device defines with SMI graphic */ +/* Any other graphic must change this section */ +/*****************************************************************************/ + +#ifdef CONFIG_VIDEO_SMI_LYNXEM + +#define VIDEO_FB_LITTLE_ENDIAN +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/*****************************************************************************/ +/* Defines for the CT69000 driver */ +/*****************************************************************************/ +#ifdef CONFIG_VIDEO_CT69000 + +#define VIDEO_FB_LITTLE_ENDIAN +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/*****************************************************************************/ +/* Defines for the SED13806 driver */ +/*****************************************************************************/ +#ifdef CONFIG_VIDEO_SED13806 + +#ifndef CONFIG_TOTAL5200 +#define VIDEO_FB_LITTLE_ENDIAN +#endif +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/*****************************************************************************/ +/* Defines for the SED13806 driver */ +/*****************************************************************************/ +#ifdef CONFIG_VIDEO_SM501 + +#ifdef CONFIG_HH405 +#define VIDEO_FB_LITTLE_ENDIAN +#endif +#endif + +/*****************************************************************************/ +/* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */ +/*****************************************************************************/ +#include + +/*****************************************************************************/ +/* some Macros */ +/*****************************************************************************/ +#define VIDEO_VISIBLE_COLS (pGD->winSizeX) +#define VIDEO_VISIBLE_ROWS (pGD->winSizeY) +#define VIDEO_PIXEL_SIZE (pGD->gdfBytesPP) +#define VIDEO_DATA_FORMAT (pGD->gdfIndex) +#define VIDEO_FB_ADRS (pGD->frameAdrs) + +/*****************************************************************************/ +/* Console device defines with i8042 keyboard controller */ +/* Any other keyboard controller must change this section */ +/*****************************************************************************/ + +#ifdef CONFIG_I8042_KBD +#include + +#define VIDEO_KBD_INIT_FCT i8042_kbd_init() +#define VIDEO_TSTC_FCT i8042_tstc +#define VIDEO_GETC_FCT i8042_getc +#endif + +/*****************************************************************************/ +/* Console device */ +/*****************************************************************************/ + +#include +#include +#include +#include +#ifdef CFG_CMD_DATE +#include + +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#include +#include +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ + +/*****************************************************************************/ +/* Cursor definition: */ +/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/i8042.c) to */ +/* let the cursor blink. Uses the macros CURSOR_OFF */ +/* and CURSOR_ON. */ +/* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No */ +/* blinking is provided. Uses the macros CURSOR_SET */ +/* and CURSOR_OFF. */ +/* CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the */ +/* graphic chip. Uses the macro CURSOR_SET. */ +/* ATTENTION: If booting an OS, the display driver */ +/* must disable the hardware register of the graphic */ +/* chip. Otherwise a blinking field is displayed */ +/*****************************************************************************/ +#if !defined(CONFIG_CONSOLE_CURSOR) && \ + !defined(CONFIG_VIDEO_SW_CURSOR) && \ + !defined(CONFIG_VIDEO_HW_CURSOR) +/* no Cursor defined */ +#define CURSOR_ON +#define CURSOR_OFF +#define CURSOR_SET +#endif + +#ifdef CONFIG_CONSOLE_CURSOR +#ifdef CURSOR_ON +#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined +#endif +void console_cursor (int state); +#define CURSOR_ON console_cursor(1); +#define CURSOR_OFF console_cursor(0); +#define CURSOR_SET +#ifndef CONFIG_I8042_KBD +#warning Cursor drawing on/off needs timer function s.a. drivers/i8042.c +#endif +#else +#ifdef CONFIG_CONSOLE_TIME +#error CONFIG_CONSOLE_CURSOR must be defined for CONFIG_CONSOLE_TIME +#endif +#endif /* CONFIG_CONSOLE_CURSOR */ + +#ifdef CONFIG_VIDEO_SW_CURSOR +#ifdef CURSOR_ON +#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined +#endif +#define CURSOR_ON +#define CURSOR_OFF video_putchar(console_col * VIDEO_FONT_WIDTH,\ + console_row * VIDEO_FONT_HEIGHT, ' '); +#define CURSOR_SET video_set_cursor(); +#endif /* CONFIG_VIDEO_SW_CURSOR */ + + +#ifdef CONFIG_VIDEO_HW_CURSOR +#ifdef CURSOR_ON +#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined +#endif +#define CURSOR_ON +#define CURSOR_OFF +#define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \ + (console_row * VIDEO_FONT_HEIGHT) + VIDEO_LOGO_HEIGHT); +#endif /* CONFIG_VIDEO_HW_CURSOR */ + +#ifdef CONFIG_VIDEO_LOGO +#ifdef CONFIG_VIDEO_BMP_LOGO +#include +#define VIDEO_LOGO_WIDTH BMP_LOGO_WIDTH +#define VIDEO_LOGO_HEIGHT BMP_LOGO_HEIGHT +#define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET +#define VIDEO_LOGO_COLORS BMP_LOGO_COLORS + +#else /* CONFIG_VIDEO_BMP_LOGO */ +#define LINUX_LOGO_WIDTH 80 +#define LINUX_LOGO_HEIGHT 80 +#define LINUX_LOGO_COLORS 214 +#define LINUX_LOGO_LUT_OFFSET 0x20 +#define __initdata +#include +#define VIDEO_LOGO_WIDTH LINUX_LOGO_WIDTH +#define VIDEO_LOGO_HEIGHT LINUX_LOGO_HEIGHT +#define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET +#define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS +#endif /* CONFIG_VIDEO_BMP_LOGO */ +#define VIDEO_INFO_X (VIDEO_LOGO_WIDTH) +#define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2) +#else /* CONFIG_VIDEO_LOGO */ +#define VIDEO_LOGO_WIDTH 0 +#define VIDEO_LOGO_HEIGHT 0 +#endif /* CONFIG_VIDEO_LOGO */ + +#define VIDEO_COLS VIDEO_VISIBLE_COLS +#define VIDEO_ROWS VIDEO_VISIBLE_ROWS +#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE) +#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2) +#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE) +#define VIDEO_BURST_LEN (VIDEO_COLS/8) + +#ifdef CONFIG_VIDEO_LOGO +#define CONSOLE_ROWS ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / VIDEO_FONT_HEIGHT) +#else +#define CONSOLE_ROWS (VIDEO_ROWS / VIDEO_FONT_HEIGHT) +#endif + +#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH) +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) +#define CONSOLE_ROW_FIRST (video_console_address) +#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) +#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) +#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) + +/* Macros */ +#ifdef VIDEO_FB_LITTLE_ENDIAN +#define SWAP16(x) ((((x) & 0x00ff) << 8) | ( (x) >> 8)) +#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ + (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) +#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | (((x) & 0x0000ff00) >> 8)|\ + (((x) & 0x00ff0000) << 8) | (((x) & 0xff000000) >> 8) ) +#else +#define SWAP16(x) (x) +#define SWAP32(x) (x) +#define SHORTSWAP32(x) (x) +#endif + +#if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE) +#define PRINTD(x) printf(x) +#else +#define PRINTD(x) +#endif + + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +extern void video_get_info_str ( /* setup a board string: type, speed, etc. */ + int line_number, /* location to place info string beside logo */ + char *info /* buffer for info string */ + ); + +#endif + +/* Locals */ +static GraphicDevice *pGD; /* Pointer to Graphic array */ + +static void *video_fb_address; /* frame buffer address */ +static void *video_console_address; /* console buffer start address */ + +static int console_col = 0; /* cursor col */ +static int console_row = 0; /* cursor row */ + +static u32 eorx, fgx, bgx; /* color pats */ + +static const int video_font_draw_table8[] = { + 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, + 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, + 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, + 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff }; + +static const int video_font_draw_table15[] = { + 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff }; + +static const int video_font_draw_table16[] = { + 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff }; + +static const int video_font_draw_table24[16][3] = { + { 0x00000000, 0x00000000, 0x00000000 }, + { 0x00000000, 0x00000000, 0x00ffffff }, + { 0x00000000, 0x0000ffff, 0xff000000 }, + { 0x00000000, 0x0000ffff, 0xffffffff }, + { 0x000000ff, 0xffff0000, 0x00000000 }, + { 0x000000ff, 0xffff0000, 0x00ffffff }, + { 0x000000ff, 0xffffffff, 0xff000000 }, + { 0x000000ff, 0xffffffff, 0xffffffff }, + { 0xffffff00, 0x00000000, 0x00000000 }, + { 0xffffff00, 0x00000000, 0x00ffffff }, + { 0xffffff00, 0x0000ffff, 0xff000000 }, + { 0xffffff00, 0x0000ffff, 0xffffffff }, + { 0xffffffff, 0xffff0000, 0x00000000 }, + { 0xffffffff, 0xffff0000, 0x00ffffff }, + { 0xffffffff, 0xffffffff, 0xff000000 }, + { 0xffffffff, 0xffffffff, 0xffffffff } }; + +static const int video_font_draw_table32[16][4] = { + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + { 0x00000000, 0x00000000, 0x00000000, 0x00ffffff }, + { 0x00000000, 0x00000000, 0x00ffffff, 0x00000000 }, + { 0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff }, + { 0x00000000, 0x00ffffff, 0x00000000, 0x00000000 }, + { 0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff }, + { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000 }, + { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff }, + { 0x00ffffff, 0x00000000, 0x00000000, 0x00000000 }, + { 0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff }, + { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000 }, + { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff }, + { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000 }, + { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff }, + { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000 }, + { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } }; + + +int gunzip(void *, int, unsigned char *, unsigned long *); + +/******************************************************************************/ + +static void video_drawchars (int xx, int yy, unsigned char *s, int count) +{ + u8 *cdat, *dest, *dest0; + int rows, offset, c; + + offset = yy * VIDEO_LINE_LEN + xx * VIDEO_PIXEL_SIZE; + dest0 = video_fb_address + offset; + + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + case GDF__8BIT_332RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = (video_font_draw_table8[bits >> 4] & eorx) ^ bgx; + ((u32 *) dest)[1] = (video_font_draw_table8[bits & 15] & eorx) ^ bgx; + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_15BIT_555RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 6] & eorx) ^ bgx); + ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 4 & 3] & eorx) ^ bgx); + ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 2 & 3] & eorx) ^ bgx); + ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table15 [bits & 3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_16BIT_565RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 6] & eorx) ^ bgx); + ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 4 & 3] & eorx) ^ bgx); + ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 2 & 3] & eorx) ^ bgx); + ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table16 [bits & 3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_32BIT_X888RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = SWAP32 ((video_font_draw_table32 [bits >> 4][0] & eorx) ^ bgx); + ((u32 *) dest)[1] = SWAP32 ((video_font_draw_table32 [bits >> 4][1] & eorx) ^ bgx); + ((u32 *) dest)[2] = SWAP32 ((video_font_draw_table32 [bits >> 4][2] & eorx) ^ bgx); + ((u32 *) dest)[3] = SWAP32 ((video_font_draw_table32 [bits >> 4][3] & eorx) ^ bgx); + ((u32 *) dest)[4] = SWAP32 ((video_font_draw_table32 [bits & 15][0] & eorx) ^ bgx); + ((u32 *) dest)[5] = SWAP32 ((video_font_draw_table32 [bits & 15][1] & eorx) ^ bgx); + ((u32 *) dest)[6] = SWAP32 ((video_font_draw_table32 [bits & 15][2] & eorx) ^ bgx); + ((u32 *) dest)[7] = SWAP32 ((video_font_draw_table32 [bits & 15][3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_24BIT_888RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = (video_font_draw_table24[bits >> 4][0] & eorx) ^ bgx; + ((u32 *) dest)[1] = (video_font_draw_table24[bits >> 4][1] & eorx) ^ bgx; + ((u32 *) dest)[2] = (video_font_draw_table24[bits >> 4][2] & eorx) ^ bgx; + ((u32 *) dest)[3] = (video_font_draw_table24[bits & 15][0] & eorx) ^ bgx; + ((u32 *) dest)[4] = (video_font_draw_table24[bits & 15][1] & eorx) ^ bgx; + ((u32 *) dest)[5] = (video_font_draw_table24[bits & 15][2] & eorx) ^ bgx; + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + } +} + +/*****************************************************************************/ + +static inline void video_drawstring (int xx, int yy, unsigned char *s) +{ + video_drawchars (xx, yy, s, strlen ((char *)s)); +} + +/*****************************************************************************/ + +static void video_putchar (int xx, int yy, unsigned char c) +{ + video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, &c, 1); +} + +/*****************************************************************************/ +#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR) +static void video_set_cursor (void) +{ + /* swap drawing colors */ + eorx = fgx; + fgx = bgx; + bgx = eorx; + eorx = fgx ^ bgx; + /* draw cursor */ + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + ' '); + /* restore drawing colors */ + eorx = fgx; + fgx = bgx; + bgx = eorx; + eorx = fgx ^ bgx; +} +#endif +/*****************************************************************************/ +#ifdef CONFIG_CONSOLE_CURSOR +void console_cursor (int state) +{ + static int last_state = 0; + +#ifdef CONFIG_CONSOLE_TIME + struct rtc_time tm; + char info[16]; + + /* time update only if cursor is on (faster scroll) */ + if (state) { + rtc_get (&tm); + + sprintf (info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min, + tm.tm_sec); + video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, + VIDEO_INFO_Y, (uchar *)info); + + sprintf (info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon, + tm.tm_year); + video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, + VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, (uchar *)info); + } +#endif + + if (state && (last_state != state)) { + video_set_cursor (); + } + + if (!state && (last_state != state)) { + /* clear cursor */ + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + ' '); + } + + last_state = state; +} +#endif + +/*****************************************************************************/ + +#ifndef VIDEO_HW_RECTFILL +static void memsetl (int *p, int c, int v) +{ + while (c--) + *(p++) = v; +} +#endif + +/*****************************************************************************/ + +#ifndef VIDEO_HW_BITBLT +static void memcpyl (int *d, int *s, int c) +{ + while (c--) + *(d++) = *(s++); +} +#endif + +/*****************************************************************************/ + +static void console_scrollup (void) +{ + /* copy up rows ignoring the first one */ + +#ifdef VIDEO_HW_BITBLT + video_hw_bitblt (VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* source pos x */ + VIDEO_LOGO_HEIGHT + VIDEO_FONT_HEIGHT, /* source pos y */ + 0, /* dest pos x */ + VIDEO_LOGO_HEIGHT, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT - VIDEO_FONT_HEIGHT /* frame height */ + ); +#else + memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, + CONSOLE_SCROLL_SIZE >> 2); +#endif + + /* clear the last one */ +#ifdef VIDEO_HW_RECTFILL + video_hw_rectfill (VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* dest pos x */ + VIDEO_VISIBLE_ROWS - VIDEO_FONT_HEIGHT, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_FONT_HEIGHT, /* frame height */ + CONSOLE_BG_COL /* fill color */ + ); +#else + memsetl (CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL); +#endif +} + +/*****************************************************************************/ + +static void console_back (void) +{ + CURSOR_OFF console_col--; + + if (console_col < 0) { + console_col = CONSOLE_COLS - 1; + console_row--; + if (console_row < 0) + console_row = 0; + } + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + ' '); +} + +/*****************************************************************************/ + +static void console_newline (void) +{ + CURSOR_OFF console_row++; + console_col = 0; + + /* Check if we need to scroll the terminal */ + if (console_row >= CONSOLE_ROWS) { + /* Scroll everything up */ + console_scrollup (); + + /* Decrement row number */ + console_row--; + } +} + +/*****************************************************************************/ + +void video_putc (const char c) +{ + switch (c) { + case 13: /* ignore */ + break; + + case '\n': /* next line */ + console_newline (); + break; + + case 9: /* tab 8 */ + CURSOR_OFF console_col |= 0x0008; + console_col &= ~0x0007; + + if (console_col >= CONSOLE_COLS) + console_newline (); + break; + + case 8: /* backspace */ + console_back (); + break; + + default: /* draw the char */ + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + c); + console_col++; + + /* check for newline */ + if (console_col >= CONSOLE_COLS) + console_newline (); + } +CURSOR_SET} + + +/*****************************************************************************/ + +void video_puts (const char *s) +{ + int count = strlen (s); + + while (count--) + video_putc (*s++); +} + +/*****************************************************************************/ + +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) + +#define FILL_8BIT_332RGB(r,g,b) { \ + *fb = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6); \ + fb ++; \ +} + +#define FILL_15BIT_555RGB(r,g,b) { \ + *(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \ + fb += 2; \ +} + +#define FILL_16BIT_565RGB(r,g,b) { \ + *(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \ + fb += 2; \ +} + +#define FILL_32BIT_X888RGB(r,g,b) { \ + *(unsigned long *)fb = SWAP32((unsigned long)(((r<<16) | (g<<8) | b))); \ + fb += 4; \ +} + +#ifdef VIDEO_FB_LITTLE_ENDIAN +#define FILL_24BIT_888RGB(r,g,b) { \ + fb[0] = b; \ + fb[1] = g; \ + fb[2] = r; \ + fb += 3; \ +} +#else +#define FILL_24BIT_888RGB(r,g,b) { \ + fb[0] = r; \ + fb[1] = g; \ + fb[2] = b; \ + fb += 3; \ +} +#endif + + +/* + * Display the BMP file located at address bmp_image. + * Only uncompressed + */ +int video_display_bitmap (ulong bmp_image, int x, int y) +{ + ushort xcount, ycount; + uchar *fb; + bmp_image_t *bmp = (bmp_image_t *) bmp_image; + uchar *bmap; + ushort padded_line; + unsigned long width, height, bpp; + unsigned colors; + unsigned long compression; + bmp_color_table_entry_t cte; +#ifdef CONFIG_VIDEO_BMP_GZIP + unsigned char *dst = NULL; + ulong len; +#endif + + WATCHDOG_RESET (); + + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + +#ifdef CONFIG_VIDEO_BMP_GZIP + /* + * Could be a gzipped bmp image, try to decrompress... + */ + len = CFG_VIDEO_LOGO_MAX_SIZE; + dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); + if (dst == NULL) { + printf("Error: malloc in gunzip failed!\n"); + return(1); + } + if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)bmp_image, &len) != 0) { + printf ("Error: no valid bmp or bmp.gz image at %lx\n", bmp_image); + free(dst); + return 1; + } + if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); + } + + /* + * Set addr to decompressed image + */ + bmp = (bmp_image_t *)dst; + + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + printf ("Error: no valid bmp.gz image at %lx\n", bmp_image); + return 1; + } +#else + printf ("Error: no valid bmp image at %lx\n", bmp_image); + return 1; +#endif /* CONFIG_VIDEO_BMP_GZIP */ + } + + width = le32_to_cpu (bmp->header.width); + height = le32_to_cpu (bmp->header.height); + bpp = le16_to_cpu (bmp->header.bit_count); + colors = le32_to_cpu (bmp->header.colors_used); + compression = le32_to_cpu (bmp->header.compression); + + debug ("Display-bmp: %d x %d with %d colors\n", + width, height, colors); + + if (compression != BMP_BI_RGB) { + printf ("Error: compression type %ld not supported\n", + compression); + return 1; + } + + padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3; + + if ((x + width) > VIDEO_VISIBLE_COLS) + width = VIDEO_VISIBLE_COLS - x; + if ((y + height) > VIDEO_VISIBLE_ROWS) + height = VIDEO_VISIBLE_ROWS - y; + + bmap = (uchar *) bmp + le32_to_cpu (bmp->header.data_offset); + fb = (uchar *) (video_fb_address + + ((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) + + x * VIDEO_PIXEL_SIZE); + + /* We handle only 8bpp or 24 bpp bitmap */ + switch (le16_to_cpu (bmp->header.bit_count)) { + case 8: + padded_line -= width; + if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { + /* Copy colormap */ + for (xcount = 0; xcount < colors; ++xcount) { + cte = bmp->color_table[xcount]; + video_set_lut (xcount, cte.red, cte.green, cte.blue); + } + } + ycount = height; + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + *fb++ = *bmap++; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF__8BIT_332RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_8BIT_332RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_15BIT_555RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_15BIT_555RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_16BIT_565RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_16BIT_565RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_32BIT_X888RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_32BIT_X888RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_24BIT_888RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_24BIT_888RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + } + break; + case 24: + padded_line -= 3 * width; + ycount = height; + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_332RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_8BIT_332RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_15BIT_555RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_15BIT_555RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_16BIT_565RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_16BIT_565RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_32BIT_X888RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_32BIT_X888RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_24BIT_888RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_24BIT_888RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + default: + printf ("Error: 24 bits/pixel bitmap incompatible with current video mode\n"); + break; + } + break; + default: + printf ("Error: %d bit/pixel bitmaps not supported by U-Boot\n", + le16_to_cpu (bmp->header.bit_count)); + break; + } + +#ifdef CONFIG_VIDEO_BMP_GZIP + if (dst) { + free(dst); + } +#endif + + return (0); +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ + +/*****************************************************************************/ + +#ifdef CONFIG_VIDEO_LOGO +void logo_plot (void *screen, int width, int x, int y) +{ + + int xcount, i; + int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE; + int ycount = VIDEO_LOGO_HEIGHT; + unsigned char r, g, b, *logo_red, *logo_blue, *logo_green; + unsigned char *source; + unsigned char *dest = (unsigned char *)screen + ((y * width * VIDEO_PIXEL_SIZE) + x); + +#ifdef CONFIG_VIDEO_BMP_LOGO + source = bmp_logo_bitmap; + + /* Allocate temporary space for computing colormap */ + logo_red = malloc (BMP_LOGO_COLORS); + logo_green = malloc (BMP_LOGO_COLORS); + logo_blue = malloc (BMP_LOGO_COLORS); + /* Compute color map */ + for (i = 0; i < VIDEO_LOGO_COLORS; i++) { + logo_red[i] = (bmp_logo_palette[i] & 0x0f00) >> 4; + logo_green[i] = (bmp_logo_palette[i] & 0x00f0); + logo_blue[i] = (bmp_logo_palette[i] & 0x000f) << 4; + } +#else + source = linux_logo; + logo_red = linux_logo_red; + logo_green = linux_logo_green; + logo_blue = linux_logo_blue; +#endif + + if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { + for (i = 0; i < VIDEO_LOGO_COLORS; i++) { + video_set_lut (i + VIDEO_LOGO_LUT_OFFSET, + logo_red[i], logo_green[i], logo_blue[i]); + } + } + + while (ycount--) { + xcount = VIDEO_LOGO_WIDTH; + while (xcount--) { + r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET]; + g = logo_green[*source - VIDEO_LOGO_LUT_OFFSET]; + b = logo_blue[*source - VIDEO_LOGO_LUT_OFFSET]; + + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + *dest = *source; + break; + case GDF__8BIT_332RGB: + *dest = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6); + break; + case GDF_15BIT_555RGB: + *(unsigned short *) dest = + SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3))); + break; + case GDF_16BIT_565RGB: + *(unsigned short *) dest = + SWAP16 ((unsigned short) (((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3))); + break; + case GDF_32BIT_X888RGB: + *(unsigned long *) dest = + SWAP32 ((unsigned long) ((r << 16) | (g << 8) | b)); + break; + case GDF_24BIT_888RGB: +#ifdef VIDEO_FB_LITTLE_ENDIAN + dest[0] = b; + dest[1] = g; + dest[2] = r; +#else + dest[0] = r; + dest[1] = g; + dest[2] = b; +#endif + break; + } + source++; + dest += VIDEO_PIXEL_SIZE; + } + dest += skip; + } +#ifdef CONFIG_VIDEO_BMP_LOGO + free (logo_red); + free (logo_green); + free (logo_blue); +#endif +} + +/*****************************************************************************/ + +static void *video_logo (void) +{ + char info[128]; + extern char version_string; + +#ifdef CONFIG_SPLASH_SCREEN + char *s; + ulong addr; + + if ((s = getenv ("splashimage")) != NULL) { + addr = simple_strtoul (s, NULL, 16); + + if (video_display_bitmap (addr, 0, 0) == 0) { + return ((void *) (video_fb_address)); + } + } +#endif /* CONFIG_SPLASH_SCREEN */ + + logo_plot (video_fb_address, VIDEO_COLS, 0, 0); + + sprintf (info, " %s", &version_string); + video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *)info); + +#ifdef CONFIG_CONSOLE_EXTRA_INFO + { + int i, n = ((VIDEO_LOGO_HEIGHT - VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT); + + for (i = 1; i < n; i++) { + video_get_info_str (i, info); + if (*info) + video_drawstring (VIDEO_INFO_X, + VIDEO_INFO_Y + i * VIDEO_FONT_HEIGHT, + (uchar *)info); + } + } +#endif + + return (video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN); +} +#endif + + +/*****************************************************************************/ + +static int video_init (void) +{ + unsigned char color8; + + if ((pGD = video_hw_init ()) == NULL) + return -1; + + video_fb_address = (void *) VIDEO_FB_ADRS; +#ifdef CONFIG_VIDEO_HW_CURSOR + video_init_hw_cursor (VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT); +#endif + + /* Init drawing pats */ + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + video_set_lut (0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL); + video_set_lut (0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, CONSOLE_BG_COL); + fgx = 0x01010101; + bgx = 0x00000000; + break; + case GDF__8BIT_332RGB: + color8 = ((CONSOLE_FG_COL & 0xe0) | + ((CONSOLE_FG_COL >> 3) & 0x1c) | CONSOLE_FG_COL >> 6); + fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8; + color8 = ((CONSOLE_BG_COL & 0xe0) | + ((CONSOLE_BG_COL >> 3) & 0x1c) | CONSOLE_BG_COL >> 6); + bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8; + break; + case GDF_15BIT_555RGB: + fgx = (((CONSOLE_FG_COL >> 3) << 26) | + ((CONSOLE_FG_COL >> 3) << 21) | ((CONSOLE_FG_COL >> 3) << 16) | + ((CONSOLE_FG_COL >> 3) << 10) | ((CONSOLE_FG_COL >> 3) << 5) | + (CONSOLE_FG_COL >> 3)); + bgx = (((CONSOLE_BG_COL >> 3) << 26) | + ((CONSOLE_BG_COL >> 3) << 21) | ((CONSOLE_BG_COL >> 3) << 16) | + ((CONSOLE_BG_COL >> 3) << 10) | ((CONSOLE_BG_COL >> 3) << 5) | + (CONSOLE_BG_COL >> 3)); + break; + case GDF_16BIT_565RGB: + fgx = (((CONSOLE_FG_COL >> 3) << 27) | + ((CONSOLE_FG_COL >> 2) << 21) | ((CONSOLE_FG_COL >> 3) << 16) | + ((CONSOLE_FG_COL >> 3) << 11) | ((CONSOLE_FG_COL >> 2) << 5) | + (CONSOLE_FG_COL >> 3)); + bgx = (((CONSOLE_BG_COL >> 3) << 27) | + ((CONSOLE_BG_COL >> 2) << 21) | ((CONSOLE_BG_COL >> 3) << 16) | + ((CONSOLE_BG_COL >> 3) << 11) | ((CONSOLE_BG_COL >> 2) << 5) | + (CONSOLE_BG_COL >> 3)); + break; + case GDF_32BIT_X888RGB: + fgx = (CONSOLE_FG_COL << 16) | (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL << 16) | (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL; + break; + case GDF_24BIT_888RGB: + fgx = (CONSOLE_FG_COL << 24) | (CONSOLE_FG_COL << 16) | + (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL << 24) | (CONSOLE_BG_COL << 16) | + (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL; + break; + } + eorx = fgx ^ bgx; + +#ifdef CONFIG_VIDEO_LOGO + /* Plot the logo and get start point of console */ + PRINTD ("Video: Drawing the logo ...\n"); + video_console_address = video_logo (); +#else + video_console_address = video_fb_address; +#endif + + /* Initialize the console */ + console_col = 0; + console_row = 0; + + return 0; +} + + +/*****************************************************************************/ + +int drv_video_init (void) +{ + int skip_dev_init; + device_t console_dev; + + skip_dev_init = 0; + + /* Init video chip - returns with framebuffer cleared */ + if (video_init () == -1) + skip_dev_init = 1; + +#ifdef CONFIG_VGA_AS_SINGLE_DEVICE + /* Devices VGA and Keyboard will be assigned seperately */ + /* Init vga device */ + if (!skip_dev_init) { + memset (&console_dev, 0, sizeof (console_dev)); + strcpy (console_dev.name, "vga"); + console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ + console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; + console_dev.putc = video_putc; /* 'putc' function */ + console_dev.puts = video_puts; /* 'puts' function */ + console_dev.tstc = NULL; /* 'tstc' function */ + console_dev.getc = NULL; /* 'getc' function */ + + if (device_register (&console_dev) == 0) + return 1; + } +#else + PRINTD ("KBD: Keyboard init ...\n"); + if (VIDEO_KBD_INIT_FCT == -1) + skip_dev_init = 1; + + /* Init console device */ + if (!skip_dev_init) { + memset (&console_dev, 0, sizeof (console_dev)); + strcpy (console_dev.name, "vga"); + console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ + console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + console_dev.putc = video_putc; /* 'putc' function */ + console_dev.puts = video_puts; /* 'puts' function */ + console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */ + console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */ + + if (device_register (&console_dev) == 0) + return 1; + } +#endif /* CONFIG_VGA_AS_SINGLE_DEVICE */ + /* No console dev available */ + return 0; +} +#endif /* CONFIG_CFB_CONSOLE */ diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c new file mode 100644 index 0000000..4b7a110 --- /dev/null +++ b/drivers/cfi_flash.c @@ -0,0 +1,1281 @@ +/* + * (C) Copyright 2002-2004 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen + * Modified to work with AMD flashes + * + * Copyright (C) 2004 + * Ed Okerson + * Modified to work with little-endian systems. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * History + * 01/20/2004 - combined variants of original driver. + * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) + * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) + * 01/27/2004 - Little endian support Ed Okerson + * + * Tested Architectures + * Port Width Chip Width # of banks Flash Chip Board + * 32 16 1 28F128J3 seranoa/eagle + * 64 16 1 28F128J3 seranoa/falcon + * + */ + +/* The DEBUG define must be before common to enable debugging */ +/* #define DEBUG */ + +#include +#include +#include +#include +#ifdef CFG_FLASH_CFI_DRIVER + +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation and AMD 29F016D. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query + * Table (ALT) to determine if protection is available + * + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#ifndef CFG_FLASH_BANKS_LIST +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define AMD_CMD_RESET 0xF0 +#define AMD_CMD_WRITE 0xA0 +#define AMD_CMD_ERASE_START 0x80 +#define AMD_CMD_ERASE_SECTOR 0x30 +#define AMD_CMD_UNLOCK_START 0xAA +#define AMD_CMD_UNLOCK_ACK 0x55 + +#define AMD_STATUS_TOGGLE 0x40 +#define AMD_STATUS_ERROR 0x20 +#define AMD_ADDR_ERASE_START 0x555 +#define AMD_ADDR_START 0x555 +#define AMD_ADDR_ACK 0x2AA + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_PRIMARY_VENDOR 0x13 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + + +#define FLASH_MAN_CFI 0x01000000 + +#define CFI_CMDSET_NONE 0 +#define CFI_CMDSET_INTEL_EXTENDED 1 +#define CFI_CMDSET_AMD_STANDARD 2 +#define CFI_CMDSET_INTEL_STANDARD 3 +#define CFI_CMDSET_AMD_EXTENDED 4 +#define CFI_CMDSET_MITSU_STANDARD 256 +#define CFI_CMDSET_MITSU_EXTENDED 257 +#define CFI_CMDSET_SST 258 + + +#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ +# undef FLASH_CMD_RESET +# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ +#endif + + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; + unsigned long long ll; +} cfiword_t; + +typedef union { + volatile unsigned char *cp; + volatile unsigned short *wp; + volatile unsigned long *lp; + volatile unsigned long long *llp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +/* use CFG_MAX_FLASH_BANKS_DETECT if defined */ +#ifdef CFG_MAX_FLASH_BANKS_DETECT +static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST; +flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */ +#else +static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */ +#endif + + +/*----------------------------------------------------------------------- + * Functions + */ + +typedef unsigned long flash_sect_t; + +static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); +static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); +static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static int flash_detect_cfi (flash_info_t * info); +ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); +static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt); +#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +static flash_info_t *flash_get_info(ulong base); +#endif +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len); +#endif + +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset) +{ + return ((uchar *) (info->start[sect] + (offset * info->portwidth))); +} + +#ifdef DEBUG +/*----------------------------------------------------------------------- + * Debug support + */ +void print_longlong (char *str, unsigned long long data) +{ + int i; + char *cp; + + cp = (unsigned char *) &data; + for (i = 0; i < 8; i++) + sprintf (&str[i * 2], "%2.2x", *cp++); +} +static void flash_printqry (flash_info_t * info, flash_sect_t sect) +{ + cfiptr_t cptr; + int x, y; + + for (x = 0; x < 0x40; x += 16U / info->portwidth) { + cptr.cp = + flash_make_addr (info, sect, + x + FLASH_OFFSET_CFI_RESP); + debug ("%p : ", cptr.cp); + for (y = 0; y < 16; y++) { + debug ("%2.2x ", cptr.cp[y]); + } + debug (" "); + for (y = 0; y < 16; y++) { + if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) { + debug ("%c", cptr.cp[y]); + } else { + debug ("."); + } + } + debug ("\n"); + } +} +#endif + + +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar (flash_info_t * info, uint offset) +{ + uchar *cp; + + cp = flash_make_addr (info, 0, offset); +#if defined(__LITTLE_ENDIAN) + return (cp[0]); +#else + return (cp[info->portwidth - 1]); +#endif +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) +{ + uchar *addr; + ushort retval; + +#ifdef DEBUG + int x; +#endif + addr = flash_make_addr (info, sect, offset); + +#ifdef DEBUG + debug ("ushort addr is at %p info->portwidth = %d\n", addr, + info->portwidth); + for (x = 0; x < 2 * info->portwidth; x++) { + debug ("addr[%x] = 0x%x\n", x, addr[x]); + } +#endif +#if defined(__LITTLE_ENDIAN) + retval = ((addr[(info->portwidth)] << 8) | addr[0]); +#else + retval = ((addr[(2 * info->portwidth) - 1] << 8) | + addr[info->portwidth - 1]); +#endif + + debug ("retval = 0x%x\n", retval); + return retval; +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) +{ + uchar *addr; + ulong retval; + +#ifdef DEBUG + int x; +#endif + addr = flash_make_addr (info, sect, offset); + +#ifdef DEBUG + debug ("long addr is at %p info->portwidth = %d\n", addr, + info->portwidth); + for (x = 0; x < 4 * info->portwidth; x++) { + debug ("addr[%x] = 0x%x\n", x, addr[x]); + } +#endif +#if defined(__LITTLE_ENDIAN) + retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) | + (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8); +#else + retval = (addr[(2 * info->portwidth) - 1] << 24) | + (addr[(info->portwidth) - 1] << 16) | + (addr[(4 * info->portwidth) - 1] << 8) | + addr[(3 * info->portwidth) - 1]; +#endif + return retval; +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + size += flash_info[i].size = flash_get_size (bank_base[i], i); + if (flash_info[i].flash_id == FLASH_UNKNOWN) { +#ifndef CFG_FLASH_QUIET_TEST + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, flash_info[i].size, flash_info[i].size << 20); +#endif /* CFG_FLASH_QUIET_TEST */ + } + } + + /* Monitor protection ON by default */ +#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + + /* Environment protection ON by default */ +#ifdef CFG_ENV_IS_IN_FLASH + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + /* Redundant environment protection ON by default */ +#ifdef CFG_ENV_ADDR_REDUND + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + flash_get_info(CFG_ENV_ADDR_REDUND)); +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} +#endif + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + flash_sect_t sect; + + if (info->flash_id != FLASH_MAN_CFI) { + puts ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + puts ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + putc ('\n'); + } + + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + flash_unlock_seq (info, sect); + flash_write_cmd (info, sect, AMD_ADDR_ERASE_START, + AMD_CMD_ERASE_START); + flash_unlock_seq (info, sect); + flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR); + break; + default: + debug ("Unkown flash vendor %d\n", + info->vendor); + break; + } + + if (flash_full_status_check + (info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + putc ('.'); + } + } + puts (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + puts ("missing or unknown FLASH type\n"); + return; + } + + printf ("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3), (info->chipwidth << 3)); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, + info->write_tout, + info->buffer_write_tout, + info->buffer_size); + + puts (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + int k; + int size; + int erased; + volatile unsigned long *flash; + + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *) info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n"); + /* print empty and read-only info */ + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else /* ! CFG_FLASH_EMPTY_INFO */ + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); +#endif + } + putc ('\n'); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + int buffered_size; +#endif + /* get lower aligned address */ + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if ((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for (i = 0; i < aln; ++i, ++cp) + flash_add_byte (info, &cword, (*(uchar *) cp)); + + for (; (i < info->portwidth) && (cnt > 0); i++) { + flash_add_byte (info, &cword, *src++); + cnt--; + cp++; + } + for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte (info, &cword, (*(uchar *) cp)); + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp = cp; + } + + /* handle the aligned part */ +#ifdef CFG_FLASH_USE_BUFFER_WRITE + buffered_size = (info->portwidth / info->chipwidth); + buffered_size *= info->buffer_size; + while (cnt >= info->portwidth) { + i = buffered_size > cnt ? cnt : buffered_size; + if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) + return rc; + i -= i & (info->portwidth - 1); + wp += i; + src += i; + cnt -= i; + } +#else + while (cnt >= info->portwidth) { + cword.l = 0; + for (i = 0; i < info->portwidth; i++) { + flash_add_byte (info, &cword, *src++); + } + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { + flash_add_byte (info, &cword, *src++); + --cnt; + } + for (; i < info->portwidth; ++i, ++cp) { + flash_add_byte (info, &cword, (*(uchar *) cp)); + } + + return flash_write_cfiword (info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +#ifdef CFG_FLASH_PROTECTION + +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); + if (prot) + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if ((retcode = + flash_full_status_check (info, sector, info->erase_blk_tout, + prot ? "protect" : "unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if (prot == 0) { + flash_sect_t i; + + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) + flash_real_protect (info, i, 1); + } + } + } + return retcode; +} + +/*----------------------------------------------------------------------- + * flash_read_user_serial - read the OneTimeProgramming cells + */ +void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, + int len) +{ + uchar *src; + uchar *dst; + + dst = buffer; + src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION); + flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); + memcpy (dst, src + offset, len); + flash_write_cmd (info, 0, 0, info->cmd_reset); +} + +/* + * flash_read_factory_serial - read the device Id from the protection area + */ +void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, + int len) +{ + uchar *src; + + src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION); + flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); + memcpy (buffer, src + offset, len); + flash_write_cmd (info, 0, 0, info->cmd_reset); +} + +#endif /* CFG_FLASH_PROTECTION */ + +/* + * flash_is_busy - check to see if the flash is busy + * This routine checks the status of the chip and returns true if the chip is busy + */ +static int flash_is_busy (flash_info_t * info, flash_sect_t sect) +{ + int retval; + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); + break; + default: + retval = 0; + } + debug ("flash_is_busy: %d\n", retval); + return retval; +} + +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check (flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while (flash_is_busy (info, sector)) { + if (get_timer (start) > info->erase_blk_tout * CFG_HZ) { + printf ("Flash %s timeout at address %lx data %lx\n", + prompt, info->start[sector], + flash_read_long (info, sector, 0)); + flash_write_cmd (info, sector, 0, info->cmd_reset); + return ERR_TIMOUT; + } + } + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt) +{ + int retcode; + + retcode = flash_status_check (info, sector, tout, prompt); + switch (info->vendor) { + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + if ((retcode != ERR_OK) + && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf ("Flash %s error at address %lx\n", prompt, + info->start[sector]); + if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { + puts ("Command Sequence Error.\n"); + } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { + puts ("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { + puts ("Locking Error\n"); + } + if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { + puts ("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) + puts ("Vpp Low Error.\n"); + } + flash_write_cmd (info, sector, 0, info->cmd_reset); + break; + default: + break; + } + return retcode; +} + +/*----------------------------------------------------------------------- + */ +static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) +{ +#if defined(__LITTLE_ENDIAN) + unsigned short w; + unsigned int l; + unsigned long long ll; +#endif + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: +#if defined(__LITTLE_ENDIAN) + w = c; + w <<= 8; + cword->w = (cword->w >> 8) | w; +#else + cword->w = (cword->w << 8) | c; +#endif + break; + case FLASH_CFI_32BIT: +#if defined(__LITTLE_ENDIAN) + l = c; + l <<= 24; + cword->l = (cword->l >> 8) | l; +#else + cword->l = (cword->l << 8) | c; +#endif + break; + case FLASH_CFI_64BIT: +#if defined(__LITTLE_ENDIAN) + ll = c; + ll <<= 56; + cword->ll = (cword->ll >> 8) | ll; +#else + cword->ll = (cword->ll << 8) | c; +#endif + break; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) +{ + int i; + uchar *cp = (uchar *) cmdbuf; + +#if defined(__LITTLE_ENDIAN) + for (i = info->portwidth; i > 0; i--) +#else + for (i = 1; i <= info->portwidth; i++) +#endif + *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + + addr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd, + cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp, + cmd, cword.w, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp, + cmd, cword.l, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + *addr.lp = cword.l; + break; + case FLASH_CFI_64BIT: +#ifdef DEBUG + { + char str[20]; + + print_longlong (str, cword.ll); + + debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", + addr.llp, cmd, str, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + } +#endif + *addr.llp = cword.ll; + break; + } +} + +static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) +{ + flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START); + flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK); +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + + debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + debug ("is= %x %x\n", cptr.cp[0], cword.c); + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w); + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l); + retval = (cptr.lp[0] == cword.l); + break; + case FLASH_CFI_64BIT: +#ifdef DEBUG + { + char str1[20]; + char str2[20]; + + print_longlong (str1, cptr.llp[0]); + print_longlong (str2, cword.ll); + debug ("is= %s %s\n", str1, str2); + } +#endif + retval = (cptr.llp[0] == cword.ll); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + */ +static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + case FLASH_CFI_64BIT: + retval = ((cptr.llp[0] & cword.ll) == cword.ll); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + */ +static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c)); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w)); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l)); + break; + case FLASH_CFI_64BIT: + retval = ((cptr.llp[0] & cword.ll) != + (cptr.llp[0] & cword.ll)); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi (flash_info_t * info) +{ + debug ("flash detect cfi\n"); + + for (info->portwidth = FLASH_CFI_8BIT; + info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { + for (info->chipwidth = FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd (info, 0, 0, info->cmd_reset); + flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') + && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') + && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { + info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE); + debug ("device interface is %d\n", + info->interface); + debug ("found port %d chip %d ", + info->portwidth, info->chipwidth); + debug ("port %d bits chip %d bits\n", + info->portwidth << CFI_FLASH_SHIFT_WIDTH, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + return 1; + } + } + } + debug ("not found\n"); + return 0; +} + +/* + * The following code cannot be run from FLASH! + * + */ +ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + int i, j; + flash_sect_t sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if (flash_detect_cfi (info)) { + info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR); +#ifdef DEBUG + flash_printqry (info, 0); +#endif + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + default: + info->cmd_reset = FLASH_CMD_RESET; + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + info->cmd_reset = AMD_CMD_RESET; + break; + } + + debug ("manufacturer is %d\n", info->vendor); + size_ratio = info->portwidth / info->chipwidth; + /* if the chip is x8/x16 reduce the ratio by half */ + if ((info->interface == FLASH_CFI_X8X16) + && (info->chipwidth == FLASH_CFI_BY8)) { + size_ratio >>= 1; + } + num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS); + debug ("size_ratio %d port %d bits chip %d bits\n", + size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + debug ("found %d erase regions\n", num_erase_regions); + sect_cnt = 0; + sector = base; + for (i = 0; i < num_erase_regions; i++) { + if (i > NUM_ERASE_REGIONS) { + printf ("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long (info, 0, + FLASH_OFFSET_ERASE_REGIONS + + i * 4); + erase_region_size = + (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) + 1; + debug ("erase_region_count = %d erase_region_size = %d\n", + erase_region_count, erase_region_size); + for (j = 0; j < erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + + /* + * Only read protection status from supported devices (intel...) + */ + switch (info->vendor) { + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + info->protect[sect_cnt] = + flash_isset (info, sect_cnt, + FLASH_OFFSET_PROTECT, + FLASH_STATUS_PROTECT); + break; + default: + info->protect[sect_cnt] = 0; /* default: not protected */ + } + + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000; + info->flash_id = FLASH_MAN_CFI; + if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { + info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */ + } + } + + flash_write_cmd (info, 0, 0, info->cmd_reset); + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t * info, ulong dest, + cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr (info, 0, 0); + cptr.cp = (uchar *) dest; + + + /* Check if Flash is (sufficiently) erased */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + case FLASH_CFI_64BIT: + flag = ((cptr.llp[0] & cword.ll) == cword.ll); + break; + default: + return 2; + } + if (!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + switch (info->vendor) { + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); + break; + case CFI_CMDSET_AMD_EXTENDED: + case CFI_CMDSET_AMD_STANDARD: + flash_unlock_seq (info, 0); + flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE); + break; + } + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + case FLASH_CFI_64BIT: + cptr.llp[0] = cword.ll; + break; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + return flash_full_status_check (info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static flash_sect_t find_sector (flash_info_t * info, ulong addr) +{ + flash_sect_t sector; + + for (sector = info->sector_count - 1; sector >= 0; sector--) { + if (addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, + int len) +{ + flash_sect_t sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + /* buffered writes in the AMD chip set is not supported yet */ + if((info->vendor == CFI_CMDSET_AMD_STANDARD) || + (info->vendor == CFI_CMDSET_AMD_EXTENDED)) + return ERR_INVAL; + + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector (info, dest); + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if ((retcode = + flash_status_check (info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + /* reduce the number of loops by the width of the port */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + case FLASH_CFI_64BIT: + cnt = len >> 3; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + case FLASH_CFI_64BIT: + *dst.llp++ = *src.llp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd (info, sector, 0, + FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = + flash_full_status_check (info, sector, + info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CFG_FLASH_CFI */ diff --git a/drivers/cs8900.c b/drivers/cs8900.c new file mode 100644 index 0000000..082434c --- /dev/null +++ b/drivers/cs8900.c @@ -0,0 +1,322 @@ +/* + * Cirrus Logic CS8900A Ethernet + * + * (C) 2003 Wolfgang Denk, wd@denx.de + * Extension to synchronize ethaddr environment variable + * against value in EEPROM + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 1999 Ben Williamson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is loaded into SRAM in bootstrap mode, where it waits + * for commands on UART1 to read and write memory, jump to code etc. + * A design goal for this program is to be entirely independent of the + * target board. Anything with a CL-PS7111 or EP7211 should be able to run + * this code in bootstrap mode. All the board specifics can be handled on + * the host. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include "cs8900.h" +#include + +#ifdef CONFIG_DRIVER_CS8900 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +#undef DEBUG + +/* packet page register access functions */ + +#ifdef CS8900_BUS32 +/* we don't need 16 bit initialisation on 32 bit bus */ +#define get_reg_init_bus(x) get_reg((x)) +#else +static unsigned short get_reg_init_bus (int regno) +{ + /* force 16 bit busmode */ + volatile unsigned char c; + + c = CS8900_BUS16_0; + c = CS8900_BUS16_1; + c = CS8900_BUS16_0; + c = CS8900_BUS16_1; + c = CS8900_BUS16_0; + + CS8900_PPTR = regno; + return (unsigned short) CS8900_PDATA; +} +#endif + +static unsigned short get_reg (int regno) +{ + CS8900_PPTR = regno; + return (unsigned short) CS8900_PDATA; +} + + +static void put_reg (int regno, unsigned short val) +{ + CS8900_PPTR = regno; + CS8900_PDATA = val; +} + +static void eth_reset (void) +{ + int tmo; + unsigned short us; + + /* reset NIC */ + put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset); + + /* wait for 200ms */ + udelay (200000); + /* Wait until the chip is reset */ + + tmo = get_timer (0) + 1 * CFG_HZ; + while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0) + && tmo < get_timer (0)) + /*NOP*/; +} + +static void eth_reginit (void) +{ + /* receive only error free packets addressed to this card */ + put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK); + /* do not generate any interrupts on receive operations */ + put_reg (PP_RxCFG, 0); + /* do not generate any interrupts on transmit operations */ + put_reg (PP_TxCFG, 0); + /* do not generate any interrupts on buffer operations */ + put_reg (PP_BufCFG, 0); + /* enable transmitter/receiver mode */ + put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx); +} + +void cs8900_get_enetaddr (uchar * addr) +{ + int i; + unsigned char env_enetaddr[6]; + char *tmp = getenv ("ethaddr"); + char *end; + + for (i=0; i<6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + + /* verify chip id */ + if (get_reg_init_bus (PP_ChipID) != 0x630e) + return; + eth_reset (); + if ((get_reg (PP_SelfST) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) == + (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) { + + /* Load the MAC from EEPROM */ + for (i = 0; i < 6 / 2; i++) { + unsigned int Addr; + + Addr = get_reg (PP_IA + i * 2); + addr[i * 2] = Addr & 0xFF; + addr[i * 2 + 1] = Addr >> 8; + } + + if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && + memcmp(env_enetaddr, addr, 6) != 0) { + printf ("\nWarning: MAC addresses don't match:\n"); + printf ("\tHW MAC address: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + addr[0], addr[1], + addr[2], addr[3], + addr[4], addr[5] ); + printf ("\t\"ethaddr\" value: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + env_enetaddr[0], env_enetaddr[1], + env_enetaddr[2], env_enetaddr[3], + env_enetaddr[4], env_enetaddr[5]) ; + debug ("### Set MAC addr from environment\n"); + memcpy (addr, env_enetaddr, 6); + } + if (!tmp) { + char ethaddr[20]; + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + addr[0], addr[1], + addr[2], addr[3], + addr[4], addr[5]) ; + debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr); + setenv ("ethaddr", ethaddr); + } + + } +} + +void eth_halt (void) +{ + /* disable transmitter/receiver mode */ + put_reg (PP_LineCTL, 0); + + /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */ + get_reg_init_bus (PP_ChipID); +} + +int eth_init (bd_t * bd) +{ + + /* verify chip id */ + if (get_reg_init_bus (PP_ChipID) != 0x630e) { + printf ("CS8900 Ethernet chip not found?!\n"); + return 0; + } + + eth_reset (); + /* set the ethernet address */ + put_reg (PP_IA + 0, bd->bi_enetaddr[0] | (bd->bi_enetaddr[1] << 8)); + put_reg (PP_IA + 2, bd->bi_enetaddr[2] | (bd->bi_enetaddr[3] << 8)); + put_reg (PP_IA + 4, bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8)); + + eth_reginit (); + return 0; +} + +/* Get a data block via Ethernet */ +extern int eth_rx (void) +{ + int i; + unsigned short rxlen; + unsigned short *addr; + unsigned short status; + + status = get_reg (PP_RER); + + if ((status & PP_RER_RxOK) == 0) + return 0; + + status = CS8900_RTDATA; /* stat */ + rxlen = CS8900_RTDATA; /* len */ + +#ifdef DEBUG + if (rxlen > PKTSIZE_ALIGN + PKTALIGN) + printf ("packet too big!\n"); +#endif + for (addr = (unsigned short *) NetRxPackets[0], i = rxlen >> 1; i > 0; + i--) + *addr++ = CS8900_RTDATA; + if (rxlen & 1) + *addr++ = CS8900_RTDATA; + + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], rxlen); + + return rxlen; +} + +/* Send a data block via Ethernet. */ +extern int eth_send (volatile void *packet, int length) +{ + volatile unsigned short *addr; + int tmo; + unsigned short s; + +retry: + /* initiate a transmit sequence */ + CS8900_TxCMD = PP_TxCmd_TxStart_Full; + CS8900_TxLEN = length; + + /* Test to see if the chip has allocated memory for the packet */ + if ((get_reg (PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) { + /* Oops... this should not happen! */ +#ifdef DEBUG + printf ("cs: unable to send packet; retrying...\n"); +#endif + for (tmo = get_timer (0) + 5 * CFG_HZ; get_timer (0) < tmo;) + /*NOP*/; + eth_reset (); + eth_reginit (); + goto retry; + } + + /* Write the contents of the packet */ + /* assume even number of bytes */ + for (addr = packet; length > 0; length -= 2) + CS8900_RTDATA = *addr++; + + /* wait for transfer to succeed */ + tmo = get_timer (0) + 5 * CFG_HZ; + while ((s = get_reg (PP_TER) & ~0x1F) == 0) { + if (get_timer (0) >= tmo) + break; + } + + /* nothing */ ; + if ((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) { +#ifdef DEBUG + printf ("\ntransmission error %#x\n", s); +#endif + } + + return 0; +} + +static void cs8900_e2prom_ready(void) +{ + while(get_reg(PP_SelfST) & SI_BUSY); +} + +/***********************************************************/ +/* read a 16-bit word out of the EEPROM */ +/***********************************************************/ + +int cs8900_e2prom_read(unsigned char addr, unsigned short *value) +{ + cs8900_e2prom_ready(); + put_reg(PP_EECMD, EEPROM_READ_CMD | addr); + cs8900_e2prom_ready(); + *value = get_reg(PP_EEData); + + return 0; +} + + +/***********************************************************/ +/* write a 16-bit word into the EEPROM */ +/***********************************************************/ + +int cs8900_e2prom_write(unsigned char addr, unsigned short value) +{ + cs8900_e2prom_ready(); + put_reg(PP_EECMD, EEPROM_WRITE_EN); + cs8900_e2prom_ready(); + put_reg(PP_EEData, value); + put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr); + cs8900_e2prom_ready(); + put_reg(PP_EECMD, EEPROM_WRITE_DIS); + cs8900_e2prom_ready(); + + return 0; +} + +#endif /* COMMANDS & CFG_NET */ + +#endif /* CONFIG_DRIVER_CS8900 */ diff --git a/drivers/cs8900.h b/drivers/cs8900.h new file mode 100644 index 0000000..f886d10 --- /dev/null +++ b/drivers/cs8900.h @@ -0,0 +1,258 @@ +/* + * Cirrus Logic CS8900A Ethernet + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 1999 Ben Williamson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is loaded into SRAM in bootstrap mode, where it waits + * for commands on UART1 to read and write memory, jump to code etc. + * A design goal for this program is to be entirely independent of the + * target board. Anything with a CL-PS7111 or EP7211 should be able to run + * this code in bootstrap mode. All the board specifics can be handled on + * the host. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#ifdef CONFIG_DRIVER_CS8900 + +/* although the registers are 16 bit, they are 32-bit aligned on the + EDB7111. so we have to read them as 32-bit registers and ignore the + upper 16-bits. i'm not sure if this holds for the EDB7211. */ + +#ifdef CS8900_BUS16 + /* 16 bit aligned registers, 16 bit wide */ + #define CS8900_REG u16 + #define CS8900_OFF 0x02 + #define CS8900_BUS16_0 *(volatile u8 *)(CS8900_BASE+0x00) + #define CS8900_BUS16_1 *(volatile u8 *)(CS8900_BASE+0x01) +#elif defined(CS8900_BUS32) + /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */ + #define CS8900_REG u32 + #define CS8900_OFF 0x04 +#else + #error unknown bussize ... +#endif + +#define CS8900_RTDATA *(volatile CS8900_REG *)(CS8900_BASE+0x00*CS8900_OFF) +#define CS8900_TxCMD *(volatile CS8900_REG *)(CS8900_BASE+0x02*CS8900_OFF) +#define CS8900_TxLEN *(volatile CS8900_REG *)(CS8900_BASE+0x03*CS8900_OFF) +#define CS8900_ISQ *(volatile CS8900_REG *)(CS8900_BASE+0x04*CS8900_OFF) +#define CS8900_PPTR *(volatile CS8900_REG *)(CS8900_BASE+0x05*CS8900_OFF) +#define CS8900_PDATA *(volatile CS8900_REG *)(CS8900_BASE+0x06*CS8900_OFF) + + +#define ISQ_RxEvent 0x04 +#define ISQ_TxEvent 0x08 +#define ISQ_BufEvent 0x0C +#define ISQ_RxMissEvent 0x10 +#define ISQ_TxColEvent 0x12 +#define ISQ_EventMask 0x3F + +/* packet page register offsets */ + +/* bus interface registers */ +#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */ +#define PP_ChipRev 0x0002 /* Chip revision, model codes */ + +#define PP_IntReg 0x0022 /* Interrupt configuration */ +#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */ +#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */ +#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */ +#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */ + +/* status and control registers */ + +#define PP_RxCFG 0x0102 /* Receiver configuration */ +#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */ +#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */ +#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */ +#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */ +#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */ +#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */ +#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */ +#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */ +#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */ + +#define PP_RxCTL 0x0104 /* Receiver control */ +#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */ +#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */ +#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */ +#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */ +#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */ +#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */ +#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */ +#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */ +#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */ + +#define PP_TxCFG 0x0106 /* Transmit configuration */ +#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */ +#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */ +#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */ +#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */ +#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */ +#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */ +#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */ + +#define PP_TxCmd 0x0108 /* Transmit command status */ +#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */ +#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */ +#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */ +#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */ +#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */ +#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */ +#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */ +#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */ + +#define PP_BufCFG 0x010A /* Buffer configuration */ +#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */ +#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */ +#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */ +#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */ +#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */ +#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */ +#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */ +#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */ +#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */ + +#define PP_LineCTL 0x0112 /* Line control */ +#define PP_LineCTL_Rx 0x0040 /* Enable receiver */ +#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */ +#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */ +#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */ +#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */ +#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */ +#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */ +#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */ + +#define PP_SelfCTL 0x0114 /* Chip self control */ +#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */ +#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */ +#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */ +#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */ +#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */ +#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */ +#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */ +#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */ + +#define PP_BusCTL 0x0116 /* Bus control */ +#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */ +#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */ +#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */ +#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */ +#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */ +#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */ +#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */ +#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */ + +#define PP_TestCTL 0x0118 /* Test control */ +#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */ +#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */ +#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */ +#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */ +#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */ + +#define PP_ISQ 0x0120 /* Interrupt Status Queue */ + +#define PP_RER 0x0124 /* Receive event */ +#define PP_RER_IAHash 0x0040 /* Frame hash match */ +#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */ +#define PP_RER_RxOK 0x0100 /* Frame received with no errors */ +#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */ +#define PP_RER_IA 0x0400 /* Frame address matched IA */ +#define PP_RER_Broadcast 0x0800 /* Broadcast frame */ +#define PP_RER_CRC 0x1000 /* Frame had CRC error */ +#define PP_RER_RUNT 0x2000 /* Runt frame */ +#define PP_RER_EXTRA 0x4000 /* Frame was too long */ + +#define PP_TER 0x0128 /* Transmit event */ +#define PP_TER_CRS 0x0040 /* Carrier lost */ +#define PP_TER_SQE 0x0080 /* Signal Quality Error */ +#define PP_TER_TxOK 0x0100 /* Packet sent without error */ +#define PP_TER_Late 0x0200 /* Out of window */ +#define PP_TER_Jabber 0x0400 /* Stuck transmit? */ +#define PP_TER_NumCollisions 0x7800 /* Number of collisions */ +#define PP_TER_16Collisions 0x8000 /* > 16 collisions */ + +#define PP_BER 0x012C /* Buffer event */ +#define PP_BER_SWint 0x0040 /* Software interrupt */ +#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */ +#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */ +#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */ +#define PP_BER_RxMiss 0x0400 /* Received frame missed */ +#define PP_BER_Rx128 0x0800 /* 128 bytes received */ +#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */ + +#define PP_RxMiss 0x0130 /* Receiver miss counter */ + +#define PP_TxCol 0x0132 /* Transmit collision counter */ + +#define PP_LineSTAT 0x0134 /* Line status */ +#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */ +#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */ +#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */ +#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */ +#define PP_LineSTAT_CRS 0x4000 /* Frame being received */ + +#define PP_SelfSTAT 0x0136 /* Chip self status */ +#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */ +#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */ +#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */ +#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */ +#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */ +#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */ +#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */ + +#define PP_BusSTAT 0x0138 /* Bus status */ +#define PP_BusSTAT_TxBid 0x0080 /* Tx error */ +#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */ + +#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */ + +/* initiate transmit registers */ + +#define PP_TxCommand 0x0144 /* Tx Command */ +#define PP_TxLength 0x0146 /* Tx Length */ + + +/* address filter registers */ + +#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */ +#define PP_IA 0x0158 /* Individual address (MAC) */ + +/* EEPROM Kram */ +#define SI_BUSY 0x0100 +#define PP_SelfST 0x0136 /* Self State register */ +#define PP_EECMD 0x0040 /* NVR Interface Command register */ +#define PP_EEData 0x0042 /* NVR Interface Data Register */ +#define EEPROM_WRITE_EN 0x00F0 +#define EEPROM_WRITE_DIS 0x0000 +#define EEPROM_WRITE_CMD 0x0100 +#define EEPROM_READ_CMD 0x0200 +#define EEPROM_ERASE_CMD 0x0300 + +extern int cs8900_e2prom_read(uchar, ushort *); +extern int cs8900_e2prom_write(uchar, ushort); + +#endif /* CONFIG_DRIVER_CS8900 */ diff --git a/drivers/ct69000.c b/drivers/ct69000.c new file mode 100644 index 0000000..7bcf19f --- /dev/null +++ b/drivers/ct69000.c @@ -0,0 +1,1265 @@ +/* ported from ctfb.c (linux kernel): + * Created in Jan - July 2000 by Thomas Höhenleitner + * + * Ported to U-Boot: + * (C) Copyright 2002 Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_VIDEO + +#include +#include +#include "videomodes.h" + +#ifdef CONFIG_VIDEO_CT69000 + +/* debug */ +#undef VGA_DEBUG +#undef VGA_DUMP_REG +#ifdef VGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* Macros */ +#ifndef min +#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b ) +#endif +#ifndef max +#define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b ) +#endif +#ifdef minmax +#error "term minmax already used." +#endif +#define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) ) +#define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) ) + +/* CT Register Offsets */ +#define CT_AR_O 0x3c0 /* Index and Data write port of the attribute Registers */ +#define CT_GR_O 0x3ce /* Index port of the Graphic Controller Registers */ +#define CT_SR_O 0x3c4 /* Index port of the Sequencer Controller */ +#define CT_CR_O 0x3d4 /* Index port of the CRT Controller */ +#define CT_XR_O 0x3d6 /* Extended Register index */ +#define CT_MSR_W_O 0x3c2 /* Misc. Output Register (write only) */ +#define CT_LUT_MASK_O 0x3c6 /* Color Palette Mask */ +#define CT_LUT_START_O 0x3c8 /* Color Palette Write Mode Index */ +#define CT_LUT_RGB_O 0x3c9 /* Color Palette Data Port */ +#define CT_STATUS_REG0_O 0x3c2 /* Status Register 0 (read only) */ +#define CT_STATUS_REG1_O 0x3da /* Input Status Register 1 (read only) */ + +#define CT_FP_O 0x3d0 /* Index port of the Flat panel Registers */ +#define CT_MR_O 0x3d2 /* Index Port of the Multimedia Extension */ + +/* defines for the memory mapped registers */ +#define BR00_o 0x400000 /* Source and Destination Span Register */ +#define BR01_o 0x400004 /* Pattern/Source Expansion Background Color & Transparency Key Register */ +#define BR02_o 0x400008 /* Pattern/Source Expansion Foreground Color Register */ +#define BR03_o 0x40000C /* Monochrome Source Control Register */ +#define BR04_o 0x400010 /* BitBLT Control Register */ +#define BR05_o 0x400014 /* Pattern Address Registe */ +#define BR06_o 0x400018 /* Source Address Register */ +#define BR07_o 0x40001C /* Destination Address Register */ +#define BR08_o 0x400020 /* Destination Width & Height Register */ +#define BR09_o 0x400024 /* Source Expansion Background Color & Transparency Key Register */ +#define BR0A_o 0x400028 /* Source Expansion Foreground Color Register */ + +#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ +#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ +#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ +#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ + +/* Some Mode definitions */ +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ + +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 + +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ + +#define text 0 +#define fntwidth 8 + +/* table for VGA Initialization */ +typedef struct { + const unsigned char reg; + const unsigned char val; +} CT_CFG_TABLE; + +/* this table provides some basic initialisations such as Memory Clock etc */ +static CT_CFG_TABLE xreg[] = { + {0x09, 0x01}, /* CRT Controller Extensions Enable */ + {0x0A, 0x02}, /* Frame Buffer Mapping */ + {0x0B, 0x01}, /* PCI Write Burst support */ + {0x20, 0x00}, /* BitBLT Configuration */ + {0x40, 0x03}, /* Memory Access Control */ + {0x60, 0x00}, /* Video Pin Control */ + {0x61, 0x00}, /* DPMS Synch control */ + {0x62, 0x00}, /* GPIO Pin Control */ + {0x63, 0xBD}, /* GPIO Pin Data */ + {0x67, 0x00}, /* Pin Tri-State */ + {0x80, 0x80}, /* Pixel Pipeline Config 0 register */ + {0xA0, 0x00}, /* Cursor 1 Control Reg */ + {0xA1, 0x00}, /* Cursor 1 Vertical Extension Reg */ + {0xA2, 0x00}, /* Cursor 1 Base Address Low */ + {0xA3, 0x00}, /* Cursor 1 Base Address High */ + {0xA4, 0x00}, /* Cursor 1 X-Position Low */ + {0xA5, 0x00}, /* Cursor 1 X-Position High */ + {0xA6, 0x00}, /* Cursor 1 Y-Position Low */ + {0xA7, 0x00}, /* Cursor 1 Y-Position High */ + {0xA8, 0x00}, /* Cursor 2 Control Reg */ + {0xA9, 0x00}, /* Cursor 2 Vertical Extension Reg */ + {0xAA, 0x00}, /* Cursor 2 Base Address Low */ + {0xAB, 0x00}, /* Cursor 2 Base Address High */ + {0xAC, 0x00}, /* Cursor 2 X-Position Low */ + {0xAD, 0x00}, /* Cursor 2 X-Position High */ + {0xAE, 0x00}, /* Cursor 2 Y-Position Low */ + {0xAF, 0x00}, /* Cursor 2 Y-Position High */ + {0xC0, 0x7D}, /* Dot Clock 0 VCO M-Divisor */ + {0xC1, 0x07}, /* Dot Clock 0 VCO N-Divisor */ + {0xC3, 0x34}, /* Dot Clock 0 Divisor select */ + {0xC4, 0x55}, /* Dot Clock 1 VCO M-Divisor */ + {0xC5, 0x09}, /* Dot Clock 1 VCO N-Divisor */ + {0xC7, 0x24}, /* Dot Clock 1 Divisor select */ + {0xC8, 0x7D}, /* Dot Clock 2 VCO M-Divisor */ + {0xC9, 0x07}, /* Dot Clock 2 VCO N-Divisor */ + {0xCB, 0x34}, /* Dot Clock 2 Divisor select */ + {0xCC, 0x38}, /* Memory Clock 0 VCO M-Divisor */ + {0xCD, 0x03}, /* Memory Clock 0 VCO N-Divisor */ + {0xCE, 0x90}, /* Memory Clock 0 Divisor select */ + {0xCF, 0x06}, /* Clock Config */ + {0xD0, 0x0F}, /* Power Down */ + {0xD1, 0x01}, /* Power Down BitBLT */ + {0xFF, 0xFF} /* end of table */ +}; +/* Clock Config: + * ============= + * + * PD Registers: + * ------------- + * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor. + * They are encoded as follows: + * + * +---+--------------+ + * | 2 | Loop Divisor | + * +---+--------------+ + * | 1 | 1 | + * +---+--------------+ + * | 0 | 4 | + * +---+--------------+ + * Note: The Memory Clock does not have a Loop Divisor. + * +---+---+---+--------------+ + * | 6 | 5 | 4 | Post Divisor | + * +---+---+---+--------------+ + * | 0 | 0 | 0 | 1 | + * +---+---+---+--------------+ + * | 0 | 0 | 1 | 2 | + * +---+---+---+--------------+ + * | 0 | 1 | 0 | 4 | + * +---+---+---+--------------+ + * | 0 | 1 | 1 | 8 | + * +---+---+---+--------------+ + * | 1 | 0 | 0 | 16 | + * +---+---+---+--------------+ + * | 1 | 0 | 1 | 32 | + * +---+---+---+--------------+ + * | 1 | 1 | X | reserved | + * +---+---+---+--------------+ + * + * All other bits are reserved in these registers. + * + * Clock VCO M Registers: + * ---------------------- + * These Registers contain the M Value -2. + * + * Clock VCO N Registers: + * ---------------------- + * These Registers contain the N Value -2. + * + * Formulas: + * --------- + * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz + * Fout = Fvco / Post Divisor + * + * Dot Clk0 (default 25MHz): + * ------------------------- + * Fvco = 14.318 * 127 / 9 = 202.045MHz + * Fout = 202.045MHz / 8 = 25.25MHz + * Post Divisor = 8 + * Loop Divisor = 1 + * XRC0 = (M - 2) = 125 = 0x7D + * XRC1 = (N - 2) = 7 = 0x07 + * XRC3 = 0x34 + * + * Dot Clk1 (default 28MHz): + * ------------------------- + * Fvco = 14.318 * 87 / 11 = 113.24MHz + * Fout = 113.24MHz / 4 = 28.31MHz + * Post Divisor = 4 + * Loop Divisor = 1 + * XRC4 = (M - 2) = 85 = 0x55 + * XRC5 = (N - 2) = 9 = 0x09 + * XRC7 = 0x24 + * + * Dot Clk2 (variable for extended modes set to 25MHz): + * ---------------------------------------------------- + * Fvco = 14.318 * 127 / 9 = 202.045MHz + * Fout = 202.045MHz / 8 = 25.25MHz + * Post Divisor = 8 + * Loop Divisor = 1 + * XRC8 = (M - 2) = 125 = 0x7D + * XRC9 = (N - 2) = 7 = 0x07 + * XRCB = 0x34 + * + * Memory Clk for most modes >50MHz: + * ---------------------------------- + * Fvco = 14.318 * 58 / 5 = 166MHz + * Fout = 166MHz / 2 = 83MHz + * Post Divisor = 2 + * XRCC = (M - 2) = 57 = 0x38 + * XRCD = (N - 2) = 3 = 0x03 + * XRCE = 0x90 + * + * Note Bit7 enables the clock source from the VCO + * + */ + +/******************************************************************* + * Chips struct + *******************************************************************/ +struct ctfb_chips_properties { + int device_id; /* PCI Device ID */ + unsigned long max_mem; /* memory for frame buffer */ + int vld_set; /* value of VLD if bit2 in clock control is set */ + int vld_not_set; /* value of VLD if bit2 in clock control is set */ + int mn_diff; /* difference between M/N Value + mn_diff = M/N Register */ + int mn_min; /* min value of M/N Value */ + int mn_max; /* max value of M/N Value */ + int vco_min; /* VCO Min in MHz */ + int vco_max; /* VCO Max in MHz */ +}; + +static const struct ctfb_chips_properties chips[] = { + {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220}, + {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */ + {0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */ +}; + +/* + * The Graphic Device + */ +GraphicDevice ctfb; + +/******************************************************************************* +* +* Low Level Routines +*/ + +/******************************************************************************* +* +* Read CT ISA register +*/ +#ifdef VGA_DEBUG +static unsigned char +ctRead (unsigned short index) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + if (index == CT_AR_O) + /* synch the Flip Flop */ + in8 (pGD->isaBase + CT_STATUS_REG1_O); + + return (in8 (pGD->isaBase + index)); +} +#endif +/******************************************************************************* +* +* Write CT ISA register +*/ +static void +ctWrite (unsigned short index, unsigned char val) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + + out8 ((pGD->isaBase + index), val); +} + +/******************************************************************************* +* +* Read CT ISA register indexed +*/ +static unsigned char +ctRead_i (unsigned short index, char reg) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + if (index == CT_AR_O) + /* synch the Flip Flop */ + in8 (pGD->isaBase + CT_STATUS_REG1_O); + out8 ((pGD->isaBase + index), reg); + return (in8 (pGD->isaBase + index + 1)); +} + +/******************************************************************************* +* +* Write CT ISA register indexed +*/ +static void +ctWrite_i (unsigned short index, char reg, char val) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + if (index == CT_AR_O) { + /* synch the Flip Flop */ + in8 (pGD->isaBase + CT_STATUS_REG1_O); + out8 ((pGD->isaBase + index), reg); + out8 ((pGD->isaBase + index), val); + } else { + out8 ((pGD->isaBase + index), reg); + out8 ((pGD->isaBase + index + 1), val); + } +} + +/******************************************************************************* +* +* Write a table of CT ISA register +*/ +static void +ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab) +{ + while (regTab->reg != 0xFF) { + ctWrite_i (index, regTab->reg, regTab->val); + regTab++; + } +} + +/*****************************************************************************/ +static void +SetArRegs (void) +{ + int i, tmp; + + for (i = 0; i < 0x10; i++) + ctWrite_i (CT_AR_O, i, i); + if (text) + tmp = 0x04; + else + tmp = 0x41; + + ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */ + ctWrite_i (CT_AR_O, 0x11, 0x00); /* Overscan Color Register */ + ctWrite_i (CT_AR_O, 0x12, 0x0f); /* Memory Plane Enable Register */ + if (fntwidth == 9) + tmp = 0x08; + else + tmp = 0x00; + ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */ + ctWrite_i (CT_AR_O, 0x14, 0x00); /* Color Select Register */ + ctWrite (CT_AR_O, 0x20); /* enable video */ +} + +/*****************************************************************************/ +static void +SetGrRegs (void) +{ /* Set Graphics Mode */ + int i; + + for (i = 0; i < 0x05; i++) + ctWrite_i (CT_GR_O, i, 0); + if (text) { + ctWrite_i (CT_GR_O, 0x05, 0x10); + ctWrite_i (CT_GR_O, 0x06, 0x02); + } else { + ctWrite_i (CT_GR_O, 0x05, 0x40); + ctWrite_i (CT_GR_O, 0x06, 0x05); + } + ctWrite_i (CT_GR_O, 0x07, 0x0f); + ctWrite_i (CT_GR_O, 0x08, 0xff); +} + +/*****************************************************************************/ +static void +SetSrRegs (void) +{ + int tmp = 0; + + ctWrite_i (CT_SR_O, 0x00, 0x00); /* reset */ + /*rr( sr, 0x01, tmp ); + if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01; + wr( sr, 0x01, tmp ); */ + if (fntwidth == 8) + ctWrite_i (CT_SR_O, 0x01, 0x01); /* Clocking Mode Register */ + else + ctWrite_i (CT_SR_O, 0x01, 0x00); /* Clocking Mode Register */ + ctWrite_i (CT_SR_O, 0x02, 0x0f); /* Enable CPU wr access to given memory plane */ + ctWrite_i (CT_SR_O, 0x03, 0x00); /* Character Map Select Register */ + if (text) + tmp = 0x02; + else + tmp = 0x0e; + ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB + total VGA memory beyond the first 64KB and set + fb mapping mode. */ + ctWrite_i (CT_SR_O, 0x00, 0x03); /* enable */ +} + +/*****************************************************************************/ +static void +SetBitsPerPixelIntoXrRegs (int bpp) +{ + unsigned int n = (bpp >> 3), tmp; /* only for 15, 8, 16, 24 bpp */ + static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */ + static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 }; /* mask */ + static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */ + if (bpp == 15) + n = 0; + tmp = ctRead_i (CT_XR_O, 0x20); + tmp &= off[n]; + tmp |= on[n]; + ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */ + ctWrite_i (CT_XR_O, 0x81, md[n]); +} + +/*****************************************************************************/ +static void +SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel) +{ /* he -le- ht|0 hd -ri- hs -h- he */ + unsigned char cr[0x7a]; + int i, tmp; + unsigned int hd, hs, he, ht, hbe; /* Horizontal. */ + unsigned int vd, vs, ve, vt; /* vertical */ + unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine; + unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay; + unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl; + unsigned int HorizontalEqualizationPulses; + unsigned int HorizontalSerration1Start, HorizontalSerration2Start; + + const int LineCompare = 0x3ff; + unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */ + unsigned int RAMDAC_BlankPedestalEnable = 0; /* 1=en-, 0=disable, see XR82 */ + + hd = (var->xres) / 8; /* HDisp. */ + hs = (var->xres + var->right_margin) / 8; /* HsStrt */ + he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */ + ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */ + hbe = ht - 1; /* HBlankEnable todo docu wants ht here, but it does not work */ + /* ve -up- vt|0 vd -lo- vs -v- ve */ + vd = var->yres; /* VDisplay */ + vs = var->yres + var->lower_margin; /* VSyncStart */ + ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */ + vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */ + bpp = bits_per_pixel; + dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0; + interlaced = var->vmode & FB_VMODE_INTERLACED; + bcast = var->sync & FB_SYNC_BROADCAST; + CrtHalfLine = bcast ? (hd >> 1) : 0; + BlDelayCtrl = bcast ? 1 : 0; + CompSyncCharClkDelay = 0; /* 2 bit */ + CompSyncPixelClkDelay = 0; /* 3 bit */ + if (bcast) { + NTSC_PAL_HorizontalPulseWidth = 7; /*( var->hsync_len >> 1 ) + 1 */ + HorizontalEqualizationPulses = 0; /* inverse value */ + HorizontalSerration1Start = 31; /* ( ht >> 1 ) */ + HorizontalSerration2Start = 89; /* ( ht >> 1 ) */ + } else { + NTSC_PAL_HorizontalPulseWidth = 0; + /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] ) + * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */ + HorizontalEqualizationPulses = 1; /* inverse value */ + HorizontalSerration1Start = 0; /* ( ht >> 1 ) */ + HorizontalSerration2Start = 0; /* ( ht >> 1 ) */ + } + + if (bpp == 15) + bpp = 16; + wd = var->xres * bpp / 64; /* double words per line */ + if (interlaced) { /* we divide all vertical timings, exept vd */ + vs >>= 1; + ve >>= 1; + vt >>= 1; + } + memset (cr, 0, sizeof (cr)); + cr[0x00] = 0xff & (ht - 5); + cr[0x01] = hd - 1; /* soll:4f ist 59 */ + cr[0x02] = hd; + cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd */ + cr[0x04] = hs; + cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); + cr[0x06] = (vt - 2) & 0xFF; + cr[0x30] = (vt - 2) >> 8; + cr[0x07] = ((vt & 0x100) >> 8) + | ((vd & 0x100) >> 7) + | ((vs & 0x100) >> 6) + | ((vs & 0x100) >> 5) + | ((LineCompare & 0x100) >> 4) + | ((vt & 0x200) >> 4) + | ((vd & 0x200) >> 3) + | ((vs & 0x200) >> 2); + cr[0x08] = 0x00; + cr[0x09] = (dblscan << 7) + | ((LineCompare & 0x200) >> 3) + | ((vs & 0x200) >> 4) + | (TextScanLines - 1); + cr[0x10] = vs & 0xff; /* VSyncPulseStart */ + cr[0x32] = (vs & 0xf00) >> 8; /* VSyncPulseStart */ + cr[0x11] = (ve & 0x0f); /* | 0x20; */ + cr[0x12] = (vd - 1) & 0xff; /* LineCount */ + cr[0x31] = ((vd - 1) & 0xf00) >> 8; /* LineCount */ + cr[0x13] = wd & 0xff; + cr[0x41] = (wd & 0xf00) >> 8; + cr[0x15] = vs & 0xff; + cr[0x33] = (vs & 0xf00) >> 8; + cr[0x38] = (0x100 & (ht - 5)) >> 8; + cr[0x3C] = 0xc0 & hbe; + cr[0x16] = (vt - 1) & 0xff; /* vbe - docu wants vt here, */ + cr[0x17] = 0xe3; /* but it does not work */ + cr[0x18] = 0xff & LineCompare; + cr[0x22] = 0xff; /* todo? */ + cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00; /* check:0xa6 */ + cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6) + | (BlDelayCtrl << 5) + | ((0x03 & CompSyncCharClkDelay) << 3) + | (0x07 & CompSyncPixelClkDelay); /* todo: see XR82 */ + cr[0x72] = HorizontalSerration1Start; + cr[0x73] = HorizontalSerration2Start; + cr[0x74] = (HorizontalEqualizationPulses << 5) + | NTSC_PAL_HorizontalPulseWidth; + /* todo: ct69000 has also 0x75-79 */ + /* now set the registers */ + for (i = 0; i <= 0x0d; i++) { /*CR00 .. CR0D */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + for (i = 0x10; i <= 0x18; i++) { /*CR10 .. CR18 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + i = 0x22; /*CR22 */ + ctWrite_i (CT_CR_O, i, cr[i]); + for (i = 0x30; i <= 0x33; i++) { /*CR30 .. CR33 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + i = 0x38; /*CR38 */ + ctWrite_i (CT_CR_O, i, cr[i]); + i = 0x3C; /*CR3C */ + ctWrite_i (CT_CR_O, i, cr[i]); + for (i = 0x40; i <= 0x41; i++) { /*CR40 .. CR41 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + for (i = 0x70; i <= 0x74; i++) { /*CR70 .. CR74 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + tmp = ctRead_i (CT_CR_O, 0x40); + tmp &= 0x0f; + tmp |= 0x80; + ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */ +} + +/* pixelclock control */ + +/***************************************************************************** + We have a rational number p/q and need an m/n which is very close to p/q + but has m and n within mnmin and mnmax. We have no floating point in the + kernel. We can use long long without divide. And we have time to compute... +******************************************************************************/ +static unsigned int +FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin, + unsigned int mnmax, unsigned int *pm, unsigned int *pn) +{ + /* this code is not for general purpose usable but good for our number ranges */ + unsigned int n = mnmin, m = 0; + long long int L = 0, P = p, Q = q, H = P >> 1; + long long int D = 0x7ffffffffffffffLL; + for (n = mnmin; n <= mnmax; n++) { + m = mnmin; /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */ + L = P * n - m * Q; /* n * vco - m * fref should be near 0 */ + while (L > 0 && m < mnmax) { + L -= q; /* difference is greater as 0 subtract fref */ + m++; /* and increment m */ + } + /* difference is less or equal than 0 or m > maximum */ + if (m > mnmax) + break; /* no solution: if we increase n we get the same situation */ + /* L is <= 0 now */ + if (-L > H && m > mnmin) { /* if difference > the half fref */ + L += q; /* we take the situation before */ + m--; /* because its closer to 0 */ + } + L = (L < 0) ? -L : +L; /* absolute value */ + if (D < L) /* if last difference was better take next n */ + continue; + D = L; + *pm = m; + *pn = n; /* keep improved data */ + if (D == 0) + break; /* best result we can get */ + } + return (unsigned int) (0xffffffff & D); +} + +/* that is the hardware < 69000 we have to manage + +---------+ +-------------------+ +----------------------+ +--+ + | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__ + | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | | + +---------+ +-------------------+ +----------------------+ +--+ | + ___________________________________________________________________| + | + | fvco fout + | +--------+ +------------+ +-----+ +-------------------+ +----+ + +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |---> + +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | | + | +--------+ +------------+ +-----+ | +-------------------+ +----+ + | | + | +--+ +---------------+ | + |____|÷M|___|VCO Loop Divide|__________| + | | |(VLD)(÷4, ÷16) | + +--+ +---------------+ +**************************************************************************** + that is the hardware >= 69000 we have to manage + +---------+ +--+ + | REFCLK |__|÷N|__ + | 14.3MHz | | | | + +---------+ +--+ | + __________________| + | + | fvco fout + | +--------+ +------------+ +-----+ +-------------------+ +----+ + +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |---> + +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | | + | +--------+ +------------+ +-----+ | +-------------------+ +----+ + | | + | +--+ +---------------+ | + |____|÷M|___|VCO Loop Divide|__________| + | | |(VLD)(÷1, ÷4) | + +--+ +---------------+ + + +*/ + +#define VIDEO_FREF 14318180; /* Hz */ +/*****************************************************************************/ +static int +ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param) +{ + unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock; + i = 0; + pixclock = -1; + fref = VIDEO_FREF; + m = ctRead_i (CT_XR_O, 0xc8); + n = ctRead_i (CT_XR_O, 0xc9); + m -= param->mn_diff; + n -= param->mn_diff; + xr_cb = ctRead_i (CT_XR_O, 0xcb); + PD = (0x70 & xr_cb) >> 4; + pd = 1; + for (i = 0; i < PD; i++) { + pd *= 2; + } + vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set; + if (n * vld * m) { + unsigned long long p = 1000000000000LL * pd * n; + unsigned long long q = (long long) fref * vld * m; + while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) { + p >>= 1; /* can't divide with long long so we scale down */ + q >>= 1; + } + pixclock = (unsigned) p / (unsigned) q; + } else + printf ("Invalid data in xr regs.\n"); + return pixclock; +} + +/*****************************************************************************/ +static void +FindAndSetPllParamIntoXrRegs (unsigned int pixelclock, + struct ctfb_chips_properties *param) +{ + unsigned int m, n, vld, pd, PD, fref, xr_cb; + unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk; + unsigned int pfreq, fvco, new_pixclock; + unsigned int D,nback,mback; + + fref = VIDEO_FREF; + pd = 1; + PD = 0; + fvcomin = param->vco_min; + fvcomax = param->vco_max; /* MHz */ + pclckmin = 1000000 / fvcomax + 1; /* 4546 */ + pclckmax = 32000000 / fvcomin - 1; /* 666665 */ + pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */ + pfreq = 250 * (4000000000U / pclk); + fvco = pfreq; /* Hz */ + new_pixclock = 0; + while (fvco < fvcomin * 1000000) { + /* double VCO starting with the pixelclock frequency + * as long as it is lower than the minimal VCO frequency */ + fvco *= 2; + pd *= 2; + PD++; + } + /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */ + /* first try */ + vld = param->vld_set; + D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */ + mback=m; + nback=n; + /* second try */ + vld = param->vld_not_set; + if(Dmn_min, param->mn_max, &m, &n)) { /* rds = 1 */ + /* first try was better */ + m=mback; + n=nback; + vld = param->vld_set; + } + m += param->mn_diff; + n += param->mn_diff; + PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld); + xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0); + /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be + * written, and in order from XRC8 to XRCB, before the hardware will + * update the synthesizer s settings. + */ + ctWrite_i (CT_XR_O, 0xc8, m); + ctWrite_i (CT_XR_O, 0xc9, n); /* xrca does not exist in CT69000 and CT69030 */ + ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */ + ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */ + new_pixclock = ReadPixClckFromXrRegsBack (param); + PRINTF ("pixelclock.set = %d, pixelclock.real = %d \n", + pixelclock, new_pixclock); +} + +/*****************************************************************************/ +static void +SetMsrRegs (struct ctfb_res_modes *mode) +{ + unsigned char h_synch_high, v_synch_high; + + h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */ + v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */ + ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29)); + /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01 + * Selects the upper 64KB page.Bit5=1 + * CLK2 (left reserved in standard VGA) Bit3|2=1|0 + * Disables CPU access to frame buffer. Bit1=0 + * Sets the I/O address decode for ST01, FCR, and all CR registers + * to the 3Dx I/O address range (CGA emulation). Bit0=1 + */ +} + +/************************************************************************************/ +#ifdef VGA_DUMP_REG + +static void +ctDispRegs (unsigned short index, int from, int to) +{ + unsigned char status; + int i; + + for (i = from; i < to; i++) { + status = ctRead_i (index, i); + printf ("%02X: is %02X\n", i, status); + } +} + +void +video_dump_reg (void) +{ + int i; + + printf ("Extended Regs:\n"); + ctDispRegs (CT_XR_O, 0, 0xC); + ctDispRegs (CT_XR_O, 0xe, 0xf); + ctDispRegs (CT_XR_O, 0x20, 0x21); + ctDispRegs (CT_XR_O, 0x40, 0x50); + ctDispRegs (CT_XR_O, 0x60, 0x64); + ctDispRegs (CT_XR_O, 0x67, 0x68); + ctDispRegs (CT_XR_O, 0x70, 0x72); + ctDispRegs (CT_XR_O, 0x80, 0x83); + ctDispRegs (CT_XR_O, 0xA0, 0xB0); + ctDispRegs (CT_XR_O, 0xC0, 0xD3); + printf ("Sequencer Regs:\n"); + ctDispRegs (CT_SR_O, 0, 0x8); + printf ("Graphic Regs:\n"); + ctDispRegs (CT_GR_O, 0, 0x9); + printf ("CRT Regs:\n"); + ctDispRegs (CT_CR_O, 0, 0x19); + ctDispRegs (CT_CR_O, 0x22, 0x23); + ctDispRegs (CT_CR_O, 0x30, 0x34); + ctDispRegs (CT_CR_O, 0x38, 0x39); + ctDispRegs (CT_CR_O, 0x3C, 0x3D); + ctDispRegs (CT_CR_O, 0x40, 0x42); + ctDispRegs (CT_CR_O, 0x70, 0x80); + /* don't display the attributes */ +} + +#endif + +#ifdef CONFIG_VIDEO_HW_CURSOR +/*************************************************************** + * Set Hardware Cursor in Pixel + */ +void +video_set_hw_cursor (int x, int y) +{ + int sig_x = 0, sig_y = 0; + if (x < 0) { + x *= -1; + sig_x = 1; + } + if (y < 0) { + y *= -1; + sig_y = 1; + } + ctWrite_i (CT_XR_O, 0xa4, x & 0xff); + ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7); + ctWrite_i (CT_XR_O, 0xa6, y & 0xff); + ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7); +} + +/*************************************************************** + * Init Hardware Cursor. To know the size of the Cursor, + * we have to know the Font size. + */ +void +video_init_hw_cursor (int font_width, int font_height) +{ + unsigned char xr_80; + unsigned long *curs, pattern; + int i; + int cursor_start; + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + + cursor_start = pGD->dprBase; + xr_80 = ctRead_i (CT_XR_O, 0x80); + /* set start address */ + ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0); + ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f); + /* set cursor shape */ + curs = (unsigned long *) cursor_start; + i = 0; + while (i < 0x400) { + curs[i++] = 0xffffffff; /* AND mask */ + curs[i++] = 0xffffffff; /* AND mask */ + curs[i++] = 0; /* XOR mask */ + curs[i++] = 0; /* XOR mask */ + /* Transparent */ + } + pattern = 0xffffffff >> font_width; + i = 0; + while (i < (font_height * 2)) { + curs[i++] = pattern; /* AND mask */ + curs[i++] = pattern; /* AND mask */ + curs[i++] = 0; /* XOR mask */ + curs[i++] = 0; /* XOR mask */ + /* Cursor Color 0 */ + } + /* set blink rate */ + ctWrite_i (CT_FP_O, 0x19, 0xf); + + /* set cursors colors */ + xr_80 = ctRead_i (CT_XR_O, 0x80); + xr_80 |= 0x1; /* alternate palette select */ + ctWrite_i (CT_XR_O, 0x80, xr_80); + video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL); + /* position 4 is color 0 cursor 0 */ + xr_80 &= 0xfe; /* normal palette select */ + ctWrite_i (CT_XR_O, 0x80, xr_80); + /* cursor enable */ + ctWrite_i (CT_XR_O, 0xa0, 0x91); + xr_80 |= 0x10; /* enable hwcursor */ + ctWrite_i (CT_XR_O, 0x80, xr_80); + video_set_hw_cursor (0, 0); +} +#endif /* CONFIG_VIDEO_HW_CURSOR */ + +/*************************************************************** + * Wait for BitBlt ready + */ +static int +video_wait_bitblt (unsigned long addr) +{ + unsigned long br04; + int i = 0; + br04 = in32r (addr); + while (br04 & 0x80000000) { + udelay (1); + br04 = in32r (addr); + if (i++ > 1000000) { + printf ("ERROR Timeout %lx\n", br04); + return 1; + } + } + return 0; +} + +/*************************************************************** + * Set up BitBlt Registrs + */ +static void +SetDrawingEngine (int bits_per_pixel) +{ + unsigned long br04, br00; + unsigned char tmp; + + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + + tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */ + tmp |= 0x02; /* reset BitBLT */ + ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */ + udelay (10); + tmp &= 0xfd; /* release reset BitBLT */ + ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */ + video_wait_bitblt (pGD->pciBase + BR04_o); + + /* set pattern Address */ + out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8); + br04 = 0; + if (bits_per_pixel == 1) { + br04 |= 0x00040000; /* monochome Pattern */ + br04 |= 0x00001000; /* monochome source */ + } + br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP); /* bytes per scanline */ + out32r (pGD->pciBase + BR00_o, br00); /* */ + out32r (pGD->pciBase + BR08_o, (10 << 16) + 10); /* dummy */ + out32r (pGD->pciBase + BR04_o, br04); /* write all 0 */ + out32r (pGD->pciBase + BR07_o, 0); /* destination */ + video_wait_bitblt (pGD->pciBase + BR04_o); +} + +/**************************************************************************** +* supported Video Chips +*/ +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000}, + {} +}; + +/******************************************************************************* +* +* Init video chip +*/ +void * +video_hw_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + unsigned short device_id; + pci_dev_t devbusfn; + int videomode; + unsigned long t1, hsynch, vsynch; + unsigned int pci_mem_base, *vm; + int tmp, i, bits_per_pixel; + char *penv; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + struct ctfb_chips_properties *chips_param; + /* Search for video chip */ + + if ((devbusfn = pci_find_devices (supported, 0)) < 0) { +#ifdef CONFIG_VIDEO_ONBOARD + printf ("Video: Controller not found !\n"); +#endif + return (NULL); + } + + /* PCI setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, + (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base); + pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base); + + /* get chips params */ + for (chips_param = (struct ctfb_chips_properties *) &chips[0]; + chips_param->device_id != 0; chips_param++) { + if (chips_param->device_id == device_id) + break; + } + if (chips_param->device_id == 0) { +#ifdef CONFIG_VIDEO_ONBOARD + printf ("Video: controller 0x%X not supported\n", device_id); +#endif + return NULL; + } + /* supported Video controller found */ + printf ("Video: "); + + tmp = 0; + videomode = 0x301; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x301 "); + i = 0; + } + res_mode = + (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i]. + resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + } else { + + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } + + /* calculate available color depth for controller memory */ + if (bits_per_pixel == 15) + tmp = 2; + else + tmp = bits_per_pixel >> 3; /* /8 */ + if (((chips_param->max_mem - + ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) { + tmp = + ((chips_param->max_mem - + ACCELMEMORY) / (res_mode->xres * res_mode->yres)); + if (tmp == 0) { + printf + ("No matching videomode found .-> reduce resolution\n"); + return NULL; + } else { + printf ("Switching back to %d Bits per Pixel ", + tmp << 3); + bits_per_pixel = tmp << 3; + } + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= + (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); + printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; + switch (bits_per_pixel) { + case 8: + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + case 15: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_15BIT_555RGB; + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + break; + case 24: + pGD->gdfBytesPP = 3; + pGD->gdfIndex = GDF_24BIT_888RGB; + break; + } + pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; + pGD->pciBase = pci_mem_base; + pGD->frameAdrs = pci_mem_base; + pGD->memSize = chips_param->max_mem; + /* Cursor Start Address */ + pGD->dprBase = + (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base; + if ((pGD->dprBase & 0x0fff) != 0) { + /* allign it */ + pGD->dprBase &= 0xfffff000; + pGD->dprBase += 0x00001000; + } + PRINTF ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, + PATTERN_ADR); + pGD->vprBase = pci_mem_base; /* Dummy */ + pGD->cprBase = pci_mem_base; /* Dummy */ + /* set up Hardware */ + + ctWrite (CT_MSR_W_O, 0x01); + + /* set the extended Registers */ + ctLoadRegs (CT_XR_O, xreg); + /* set atribute registers */ + SetArRegs (); + /* set Graphics register */ + SetGrRegs (); + /* set sequencer */ + SetSrRegs (); + + /* set msr */ + SetMsrRegs (res_mode); + + /* set CRT Registers */ + SetCrRegs (res_mode, bits_per_pixel); + /* set color mode */ + SetBitsPerPixelIntoXrRegs (bits_per_pixel); + + /* set PLL */ + FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param); + + ctWrite_i (CT_SR_O, 0, 0x03); /* clear synchronous reset */ + /* Clear video memory */ + i = pGD->memSize / 4; + vm = (unsigned int *) pGD->pciBase; + while (i--) + *vm++ = 0; + SetDrawingEngine (bits_per_pixel); +#ifdef VGA_DUMP_REG + video_dump_reg (); +#endif + + return ((void *) &ctfb); +} + + /******************************************************************************* +* +* Set a RGB color in the LUT (8 bit index) +*/ +void +video_set_lut (unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + + ctWrite (CT_LUT_MASK_O, 0xff); + + ctWrite (CT_LUT_START_O, (char) index); + + ctWrite (CT_LUT_RGB_O, r); /* red */ + ctWrite (CT_LUT_RGB_O, g); /* green */ + ctWrite (CT_LUT_RGB_O, b); /* blue */ + udelay (1); + ctWrite (CT_LUT_MASK_O, 0xff); +} + +/******************************************************************************* +* +* Drawing engine fill on screen region +*/ +void +video_hw_rectfill (unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + unsigned long *p, br04; + + video_wait_bitblt (pGD->pciBase + BR04_o); + + p = (unsigned long *) PATTERN_ADR; + dim_x *= bpp; + if (bpp == 3) + bpp++; /* 24Bit needs a 32bit pattern */ + memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8)); /* 8 x 8 pattern data */ + out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */ + br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00; + br04 |= 0xF0; /* write Pattern P -> D */ + out32r (pGD->pciBase + BR04_o, br04); /* */ + out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* starts the BITBlt */ + video_wait_bitblt (pGD->pciBase + BR04_o); +} + +/******************************************************************************* +* +* Drawing engine bitblt with screen region +*/ +void +video_hw_bitblt (unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + unsigned long br04; + + br04 = in32r (pGD->pciBase + BR04_o); + + /* to prevent data corruption due to overlap, we have to + * find out if, and how the frames overlaps */ + if (src_x < dst_x) { + /* src is more left than dest + * the frame may overlap -> start from right to left */ + br04 |= 0x00000100; /* set bit 8 */ + src_x += dim_x; + dst_x += dim_x; + } else { + br04 &= 0xfffffeff; /* clear bit 8 left to right */ + } + if (src_y < dst_y) { + /* src is higher than dst + * the frame may overlap => start from bottom */ + br04 |= 0x00000200; /* set bit 9 */ + src_y += dim_y; + dst_y += dim_y; + } else { + br04 &= 0xfffffdff; /* clear bit 9 top to bottom */ + } + dim_x *= bpp; + out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP); /* source */ + out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */ + br04 &= 0xffffff00; + br04 |= 0x000000CC; /* S -> D */ + out32r (pGD->pciBase + BR04_o, br04); /* */ + out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* start the BITBlt */ + video_wait_bitblt (pGD->pciBase + BR04_o); +} + +#endif /* CONFIG_CT69000 */ + +#endif /* CONFIG_VIDEO */ diff --git a/drivers/dataflash.c b/drivers/dataflash.c new file mode 100644 index 0000000..ded0395 --- /dev/null +++ b/drivers/dataflash.c @@ -0,0 +1,363 @@ +/* LowLevel function for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#ifdef CONFIG_HAS_DATAFLASH +#include +#include + +AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; +static AT91S_DataFlash DataFlashInst; + +int cs[][CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0, 0x7fff, FLAG_PROTECT_SET}, /* ROM code */ + {0x8000, 0x1ffff, FLAG_PROTECT_SET}, /* u-boot code */ + {0x20000, 0x27fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */ + {0x28000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */ +}; + +extern void AT91F_SpiInit (void); +extern int AT91F_DataflashProbe (int i, AT91PS_DataflashDesc pDesc); +extern int AT91F_DataFlashRead (AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, char *buffer); +extern int AT91F_DataFlashWrite( AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ); + +int AT91F_DataflashInit (void) +{ + int i, j; + int dfcode; + + AT91F_SpiInit (); + + for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + dataflash_info[i].Desc.state = IDLE; + dataflash_info[i].id = 0; + dataflash_info[i].Device.pages_number = 0; + dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc); + + switch (dfcode) { + case AT45DB161: + dataflash_info[i].Device.pages_number = 4096; + dataflash_info[i].Device.pages_size = 528; + dataflash_info[i].Device.page_offset = 10; + dataflash_info[i].Device.byte_mask = 0x300; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + break; + + case AT45DB321: + dataflash_info[i].Device.pages_number = 8192; + dataflash_info[i].Device.pages_size = 528; + dataflash_info[i].Device.page_offset = 10; + dataflash_info[i].Device.byte_mask = 0x300; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + break; + + case AT45DB642: + dataflash_info[i].Device.pages_number = 8192; + dataflash_info[i].Device.pages_size = 1056; + dataflash_info[i].Device.page_offset = 11; + dataflash_info[i].Device.byte_mask = 0x700; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + break; + case AT45DB128: + dataflash_info[i].Device.pages_number = 16384; + dataflash_info[i].Device.pages_size = 1056; + dataflash_info[i].Device.page_offset = 11; + dataflash_info[i].Device.byte_mask = 0x700; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + break; + + default: + break; + } + /* set the last area end to the dataflash size*/ + area_list[NB_DATAFLASH_AREA -1].end = + (dataflash_info[i].Device.pages_number * + dataflash_info[i].Device.pages_size)-1; + + /* set the area addresses */ + for(j = 0; jpDataFlashDesc = &(dataflash_info[i].Desc); + pFlash->pDevice = &(dataflash_info[i].Device); + *addr -= dataflash_info[i].logical_address; + return (pFlash); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : addr_dataflash */ +/* Object : Test if address is valid */ +/*------------------------------------------------------------------------------*/ +int addr_dataflash (unsigned long addr) +{ + int addr_valid = 0; + int i; + + for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + if ((((int) addr) & 0xFF000000) == + dataflash_info[i].logical_address) { + addr_valid = 1; + break; + } + } + + return addr_valid; +} +/*-----------------------------------------------------------------------------*/ +/* Function Name : size_dataflash */ +/* Object : Test if address is valid regarding the size */ +/*-----------------------------------------------------------------------------*/ +int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size) +{ + /* is outside the dataflash */ + if (((int)addr & 0x0FFFFFFF) > (pdataFlash->pDevice->pages_size * + pdataFlash->pDevice->pages_number)) return 0; + /* is too large for the dataflash */ + if (size > ((pdataFlash->pDevice->pages_size * + pdataFlash->pDevice->pages_number) - ((int)addr & 0x0FFFFFFF))) return 0; + + return 1; +} +/*-----------------------------------------------------------------------------*/ +/* Function Name : prot_dataflash */ +/* Object : Test if destination area is protected */ +/*-----------------------------------------------------------------------------*/ +int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr) +{ +int area; + /* find area */ + for (area=0; area < NB_DATAFLASH_AREA; area++) { + if ((addr >= pdataFlash->pDevice->area_list[area].start) && + (addr < pdataFlash->pDevice->area_list[area].end)) + break; + } + if (area == NB_DATAFLASH_AREA) return -1; + /*test protection value*/ + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) return 0; + + return 1; +} +/*-----------------------------------------------------------------------------*/ +/* Function Name : dataflash_real_protect */ +/* Object : protect/unprotect area */ +/*-----------------------------------------------------------------------------*/ +int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr) +{ +int i,j, area1, area2, addr_valid = 0; + /* find dataflash */ + for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + if ((((int) start_addr) & 0xF0000000) == + dataflash_info[i].logical_address) { + addr_valid = 1; + break; + } + } + if (!addr_valid) { + return -1; + } + /* find start area */ + for (area1=0; area1 < NB_DATAFLASH_AREA; area1++) { + if (start_addr == dataflash_info[i].Device.area_list[area1].start) break; + } + if (area1 == NB_DATAFLASH_AREA) return -1; + /* find end area */ + for (area2=0; area2 < NB_DATAFLASH_AREA; area2++) { + if (end_addr == dataflash_info[i].Device.area_list[area2].end) break; + } + if (area2 == NB_DATAFLASH_AREA) return -1; + + /*set protection value*/ + for(j = area1; j < area2+1 ; j++) + if (flag == 0) dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_CLEAR; + else dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_SET; + + return (area2-area1+1); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : read_dataflash */ +/* Object : dataflash memory read */ +/*------------------------------------------------------------------------------*/ +int read_dataflash (unsigned long addr, unsigned long size, char *result) +{ + int AddrToRead = addr; + AT91PS_DataFlash pFlash = &DataFlashInst; + + pFlash = AT91F_DataflashSelect (pFlash, &AddrToRead); + + if (pFlash == 0) + return ERR_UNKNOWN_FLASH_TYPE; + + if (size_dataflash(pFlash,addr,size) == 0) + return ERR_INVAL; + + return (AT91F_DataFlashRead (pFlash, AddrToRead, size, result)); +} + + +/*-----------------------------------------------------------------------------*/ +/* Function Name : write_dataflash */ +/* Object : write a block in dataflash */ +/*-----------------------------------------------------------------------------*/ +int write_dataflash (unsigned long addr_dest, unsigned long addr_src, + unsigned long size) +{ + int AddrToWrite = addr_dest; + AT91PS_DataFlash pFlash = &DataFlashInst; + + pFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite); + + if (pFlash == 0) + return ERR_UNKNOWN_FLASH_TYPE; + + if (size_dataflash(pFlash,addr_dest,size) == 0) + return ERR_INVAL; + + if (prot_dataflash(pFlash,addr_dest) == 0) + return ERR_PROTECTED; + + if (AddrToWrite == -1) + return -1; + + return AT91F_DataFlashWrite (pFlash, (char *) addr_src, AddrToWrite, size); +} + + +void dataflash_perror (int err) +{ + switch (err) { + case ERR_OK: + break; + case ERR_TIMOUT: + printf ("Timeout writing to DataFlash\n"); + break; + case ERR_PROTECTED: + printf ("Can't write to protected DataFlash sectors\n"); + break; + case ERR_INVAL: + printf ("Outside available DataFlash\n"); + break; + case ERR_UNKNOWN_FLASH_TYPE: + printf ("Unknown Type of DataFlash\n"); + break; + case ERR_PROG_ERROR: + printf ("General DataFlash Programming Error\n"); + break; + default: + printf ("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err); + break; + } +} + +#endif diff --git a/drivers/dc2114x.c b/drivers/dc2114x.c new file mode 100644 index 0000000..c43cd5e --- /dev/null +++ b/drivers/dc2114x.c @@ -0,0 +1,771 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_TULIP) + +#include +#include +#include + +#undef DEBUG_SROM +#undef DEBUG_SROM2 + +#undef UPDATE_SROM + +/* PCI Registers. + */ +#define PCI_CFDA_PSM 0x43 + +#define CFRV_RN 0x000000f0 /* Revision Number */ + +#define WAKEUP 0x00 /* Power Saving Wakeup */ +#define SLEEP 0x80 /* Power Saving Sleep Mode */ + +#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ + +/* Ethernet chip registers. + */ +#define DE4X5_BMR 0x000 /* Bus Mode Register */ +#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ +#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ +#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ +#define DE4X5_STS 0x028 /* Status Register */ +#define DE4X5_OMR 0x030 /* Operation Mode Register */ +#define DE4X5_SICR 0x068 /* SIA Connectivity Register */ +#define DE4X5_APROM 0x048 /* Ethernet Address PROM */ + +/* Register bits. + */ +#define BMR_SWR 0x00000001 /* Software Reset */ +#define STS_TS 0x00700000 /* Transmit Process State */ +#define STS_RS 0x000e0000 /* Receive Process State */ +#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ +#define OMR_SR 0x00000002 /* Start/Stop Receive */ +#define OMR_PS 0x00040000 /* Port Select */ +#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ +#define OMR_PM 0x00000080 /* Pass All Multicast */ + +/* Descriptor bits. + */ +#define R_OWN 0x80000000 /* Own Bit */ +#define RD_RER 0x02000000 /* Receive End Of Ring */ +#define RD_LS 0x00000100 /* Last Descriptor */ +#define RD_ES 0x00008000 /* Error Summary */ +#define TD_TER 0x02000000 /* Transmit End Of Ring */ +#define T_OWN 0x80000000 /* Own Bit */ +#define TD_LS 0x40000000 /* Last Segment */ +#define TD_FS 0x20000000 /* First Segment */ +#define TD_ES 0x00008000 /* Error Summary */ +#define TD_SET 0x08000000 /* Setup Packet */ + +/* The EEPROM commands include the alway-set leading bit. */ +#define SROM_WRITE_CMD 5 +#define SROM_READ_CMD 6 +#define SROM_ERASE_CMD 7 + +#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ +#define SROM_RD 0x00004000 /* Read from Boot ROM */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x4801 +#define EE_WRITE_1 0x4805 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define SROM_SR 0x00000800 /* Select Serial ROM when set */ + +#define DT_IN 0x00000004 /* Serial Data In */ +#define DT_CLK 0x00000002 /* Serial ROM Clock */ +#define DT_CS 0x00000001 /* Serial ROM Chip Select */ + +#define POLL_DEMAND 1 + +#ifdef CONFIG_TULIP_FIX_DAVICOM +#define RESET_DM9102(dev) {\ + unsigned long i;\ + i=INL(dev, 0x0);\ + udelay(1000);\ + OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ + udelay(1000);\ +} +#else +#define RESET_DE4X5(dev) {\ + int i;\ + i=INL(dev, DE4X5_BMR);\ + udelay(1000);\ + OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ + udelay(1000);\ + OUTL(dev, i, DE4X5_BMR);\ + udelay(1000);\ + for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ + udelay(1000);\ +} +#endif + +#define START_DE4X5(dev) {\ + s32 omr; \ + omr = INL(dev, DE4X5_OMR);\ + omr |= OMR_ST | OMR_SR;\ + OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\ +} + +#define STOP_DE4X5(dev) {\ + s32 omr; \ + omr = INL(dev, DE4X5_OMR);\ + omr &= ~(OMR_ST|OMR_SR);\ + OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ +} + +#define NUM_RX_DESC PKTBUFSRX +#ifndef CONFIG_TULIP_FIX_DAVICOM + #define NUM_TX_DESC 1 /* Number of TX descriptors */ +#else + #define NUM_TX_DESC 4 +#endif +#define RX_BUFF_SZ PKTSIZE_ALIGN + +#define TOUT_LOOP 1000000 + +#define SETUP_FRAME_LEN 192 +#define ETH_ALEN 6 + +struct de4x5_desc { + volatile s32 status; + u32 des1; + u32 buf; + u32 next; +}; + +static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */ +static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */ +static int rx_new; /* RX descriptor ring pointer */ +static int tx_new; /* TX descriptor ring pointer */ + +static char rxRingSize; +static char txRingSize; + +#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) +static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); +static int getfrom_srom(struct eth_device* dev, u_long addr); +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len); +static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len); +#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ +#ifdef UPDATE_SROM +static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); +static void update_srom(struct eth_device *dev, bd_t *bis); +#endif +#ifndef CONFIG_TULIP_FIX_DAVICOM +static int read_srom(struct eth_device *dev, u_long ioaddr, int index); +static void read_hw_addr(struct eth_device* dev, bd_t * bis); +#endif /* CONFIG_TULIP_FIX_DAVICOM */ +static void send_setup_frame(struct eth_device* dev, bd_t * bis); + +static int dc21x4x_init(struct eth_device* dev, bd_t* bis); +static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length); +static int dc21x4x_recv(struct eth_device* dev); +static void dc21x4x_halt(struct eth_device* dev); +#ifdef CONFIG_TULIP_SELECT_MEDIA +extern void dc21x4x_select_media(struct eth_device* dev); +#endif + +#if defined(CONFIG_E500) +#define phys_to_bus(a) (a) +#else +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) +#endif + +static int INL(struct eth_device* dev, u_long addr) +{ + return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); +} + +static void OUTL(struct eth_device* dev, int command, u_long addr) +{ + *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); +} + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, +#ifdef CONFIG_TULIP_FIX_DAVICOM + { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A }, +#endif + { } +}; + +int dc21x4x_initialize(bd_t *bis) +{ + int idx=0; + int card_number = 0; + unsigned int cfrv; + unsigned char timer; + pci_dev_t devbusfn; + unsigned int iobase; + unsigned short status; + struct eth_device* dev; + + while(1) { + devbusfn = pci_find_devices(supported, idx++); + if (devbusfn == -1) { + break; + } + + /* Get the chip configuration revision register. */ + pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); + +#ifndef CONFIG_TULIP_FIX_DAVICOM + if ((cfrv & CFRV_RN) < DC2114x_BRK ) { + printf("Error: The chip is not DC21143.\n"); + continue; + } +#endif + + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + status |= +#ifdef CONFIG_TULIP_USE_IO + PCI_COMMAND_IO | +#else + PCI_COMMAND_MEMORY | +#endif + PCI_COMMAND_MASTER; + pci_write_config_word(devbusfn, PCI_COMMAND, status); + + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_IO)) { + printf("Error: Can not enable I/O access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_IO)) { + printf("Error: Can not enable I/O access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + /* Check the latency timer for values >= 0x60. */ + pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); + + if (timer < 0x60) { + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); + } + +#ifdef CONFIG_TULIP_USE_IO + /* read BAR for memory space access */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + iobase &= PCI_BASE_ADDRESS_IO_MASK; +#else + /* read BAR for memory space access */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; +#endif + debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); + + dev = (struct eth_device*) malloc(sizeof *dev); + +#ifdef CONFIG_TULIP_FIX_DAVICOM + sprintf(dev->name, "Davicom#%d", card_number); +#else + sprintf(dev->name, "dc21x4x#%d", card_number); +#endif + +#ifdef CONFIG_TULIP_USE_IO + dev->iobase = pci_io_to_phys(devbusfn, iobase); +#else + dev->iobase = pci_mem_to_phys(devbusfn, iobase); +#endif + dev->priv = (void*) devbusfn; + dev->init = dc21x4x_init; + dev->halt = dc21x4x_halt; + dev->send = dc21x4x_send; + dev->recv = dc21x4x_recv; + + /* Ensure we're not sleeping. */ + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); + + udelay(10 * 1000); + +#ifndef CONFIG_TULIP_FIX_DAVICOM + read_hw_addr(dev, bis); +#endif + eth_register(dev); + + card_number++; + } + + return card_number; +} + +static int dc21x4x_init(struct eth_device* dev, bd_t* bis) +{ + int i; + int devbusfn = (int) dev->priv; + + /* Ensure we're not sleeping. */ + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); + +#ifdef CONFIG_TULIP_FIX_DAVICOM + RESET_DM9102(dev); +#else + RESET_DE4X5(dev); +#endif + + if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { + printf("Error: Cannot reset ethernet controller.\n"); + return 0; + } + +#ifdef CONFIG_TULIP_SELECT_MEDIA + dc21x4x_select_media(dev); +#else + OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); +#endif + + for (i = 0; i < NUM_RX_DESC; i++) { + rx_ring[i].status = cpu_to_le32(R_OWN); + rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); + rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i])); +#ifdef CONFIG_TULIP_FIX_DAVICOM + rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC])); +#else + rx_ring[i].next = 0; +#endif + } + + for (i=0; i < NUM_TX_DESC; i++) { + tx_ring[i].status = 0; + tx_ring[i].des1 = 0; + tx_ring[i].buf = 0; + +#ifdef CONFIG_TULIP_FIX_DAVICOM + tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); +#else + tx_ring[i].next = 0; +#endif + } + + rxRingSize = NUM_RX_DESC; + txRingSize = NUM_TX_DESC; + + /* Write the end of list marker to the descriptor lists. */ + rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); + tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); + + /* Tell the adapter where the TX/RX rings are located. */ + OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); + OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); + + START_DE4X5(dev); + + tx_new = 0; + rx_new = 0; + + send_setup_frame(dev, bis); + + return 1; +} + +static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length) +{ + int status = -1; + int i; + + if (length <= 0) { + printf("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx error buffer not ready\n", dev->name); + goto Done; + } + } + + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); + tx_ring[tx_new].status = cpu_to_le32(T_OWN); + + OUTL(dev, POLL_DEMAND, DE4X5_TPD); + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf(".%s: tx buffer not ready\n", dev->name); + goto Done; + } + } + + if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { +#if 0 /* test-only */ + printf("TX error status = 0x%08X\n", + le32_to_cpu(tx_ring[tx_new].status)); +#endif + tx_ring[tx_new].status = 0x0; + goto Done; + } + + status = length; + + Done: + tx_new = (tx_new+1) % NUM_TX_DESC; + return status; +} + +static int dc21x4x_recv(struct eth_device* dev) +{ + s32 status; + int length = 0; + + for ( ; ; ) { + status = (s32)le32_to_cpu(rx_ring[rx_new].status); + + if (status & R_OWN) { + break; + } + + if (status & RD_LS) { + /* Valid frame status. + */ + if (status & RD_ES) { + + /* There was an error. + */ + printf("RX error status = 0x%08X\n", status); + } else { + /* A valid frame received. + */ + length = (le32_to_cpu(rx_ring[rx_new].status) >> 16); + + /* Pass the packet up to the protocol + * layers. + */ + NetReceive(NetRxPackets[rx_new], length - 4); + } + + /* Change buffer ownership for this frame, back + * to the adapter. + */ + rx_ring[rx_new].status = cpu_to_le32(R_OWN); + } + + /* Update entry information. + */ + rx_new = (rx_new + 1) % rxRingSize; + } + + return length; +} + +static void dc21x4x_halt(struct eth_device* dev) +{ + int devbusfn = (int) dev->priv; + + STOP_DE4X5(dev); + OUTL(dev, 0, DE4X5_SICR); + + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); +} + +static void send_setup_frame(struct eth_device* dev, bd_t *bis) +{ + int i; + char setup_frame[SETUP_FRAME_LEN]; + char *pa = &setup_frame[0]; + + memset(pa, 0xff, SETUP_FRAME_LEN); + + for (i = 0; i < ETH_ALEN; i++) { + *(pa + (i & 1)) = dev->enetaddr[i]; + if (i & 0x01) { + pa += 4; + } + } + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx error buffer not ready\n", dev->name); + goto Done; + } + } + + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); + tx_ring[tx_new].status = cpu_to_le32(T_OWN); + + OUTL(dev, POLL_DEMAND, DE4X5_TPD); + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx buffer not ready\n", dev->name); + goto Done; + } + } + + if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { + printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); + } + tx_new = (tx_new+1) % NUM_TX_DESC; + +Done: + return; +} + +#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) +/* SROM Read and write routines. + */ +static void +sendto_srom(struct eth_device* dev, u_int command, u_long addr) +{ + OUTL(dev, command, addr); + udelay(1); +} + +static int +getfrom_srom(struct eth_device* dev, u_long addr) +{ + s32 tmp; + + tmp = INL(dev, addr); + udelay(1); + + return tmp; +} + +/* Note: this routine returns extra data bits for size detection. */ +static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) +{ + int i; + unsigned retval = 0; + int read_cmd = location | (SROM_READ_CMD << addr_len); + + sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + +#ifdef DEBUG_SROM + printf(" EEPROM read at %d ", location); +#endif + + /* Shift the read command bits out. */ + for (i = 4 + addr_len; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); + udelay(10); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); + udelay(10); +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev, ioaddr) & 15); +#endif + retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); + } + + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + +#ifdef DEBUG_SROM2 + printf(" :%X:", getfrom_srom(dev, ioaddr) & 15); +#endif + + for (i = 16; i > 0; i--) { + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); + udelay(10); +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev, ioaddr) & 15); +#endif + retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + udelay(10); + } + + /* Terminate the EEPROM access. */ + sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); + +#ifdef DEBUG_SROM2 + printf(" EEPROM value at %d is %5.5x.\n", location, retval); +#endif + + return retval; +} +#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ + +/* This executes a generic EEPROM command, typically a write or write + * enable. It returns the data output from the EEPROM, and thus may + * also be used for reads. + */ +#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) +{ + unsigned retval = 0; + +#ifdef DEBUG_SROM + printf(" EEPROM op 0x%x: ", cmd); +#endif + + sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); + + /* Shift the command bits out. */ + do { + short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; + sendto_srom(dev,dataval, ioaddr); + udelay(10); + +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev,ioaddr) & 15); +#endif + + sendto_srom(dev,dataval | DT_CLK, ioaddr); + udelay(10); + retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0); + } while (--cmd_len >= 0); + sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr); + + /* Terminate the EEPROM access. */ + sendto_srom(dev,SROM_RD | SROM_SR, ioaddr); + +#ifdef DEBUG_SROM + printf(" EEPROM result is 0x%5.5x.\n", retval); +#endif + + return retval; +} +#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ + +#ifndef CONFIG_TULIP_FIX_DAVICOM +static int read_srom(struct eth_device *dev, u_long ioaddr, int index) +{ + int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + + return do_eeprom_cmd(dev, ioaddr, + (((SROM_READ_CMD << ee_addr_size) | index) << 16) + | 0xffff, 3 + ee_addr_size + 16); +} +#endif /* CONFIG_TULIP_FIX_DAVICOM */ + +#ifdef UPDATE_SROM +static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) +{ + int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + int i; + unsigned short newval; + + udelay(10*1000); /* test-only */ + +#ifdef DEBUG_SROM + printf("ee_addr_size=%d.\n", ee_addr_size); + printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); +#endif + + /* Enable programming modes. */ + do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); + + /* Do the actual write. */ + do_eeprom_cmd(dev, ioaddr, + (((SROM_WRITE_CMD<enetaddr[0]); + int i, j = 0; + + for (i = 0; i < (ETH_ALEN >> 1); i++) { + tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); + *p = le16_to_cpu(tmp); + j += *p++; + } + + if ((j == 0) || (j == 0x2fffd)) { + memset (dev->enetaddr, 0, ETH_ALEN); + debug ("Warning: can't read HW address from SROM.\n"); + goto Done; + } + + return; + +Done: +#ifdef UPDATE_SROM + update_srom(dev, bis); +#endif + return; +} +#endif /* CONFIG_TULIP_FIX_DAVICOM */ + +#ifdef UPDATE_SROM +static void update_srom(struct eth_device *dev, bd_t *bis) +{ + int i; + static unsigned short eeprom[0x40] = { + 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ + 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ + 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ + 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ + 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ + 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ + }; + + /* Ethernet Addr... */ + eeprom[0x0a] = ((bis->bi_enetaddr[1] & 0xff) << 8) | (bis->bi_enetaddr[0] & 0xff); + eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff); + eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff); + + for (i=0; i<0x40; i++) + { + write_srom(dev, DE4X5_APROM, i, eeprom[i]); + } +} +#endif /* UPDATE_SROM */ + +#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_TULIP */ diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c new file mode 100644 index 0000000..0e475d4 --- /dev/null +++ b/drivers/dm9000x.c @@ -0,0 +1,590 @@ +/* + dm9000.c: Version 1.2 12/15/2003 + + A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. + Copyright (C) 1997 Sten Wang + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2 + of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. + +V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match + 06/22/2001 Support DM9801 progrmming + E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 + E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF + 3 + E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF + +v1.00 modify by simon 2001.9.5 + change for kernel 2.4.x + +v1.1 11/09/2001 fix force mode bug + +v1.2 03/18/2003 Weilun Huang : + Fixed phy reset. + Added tx/rx 32 bit mode. + Cleaned up for kernel merge. + +-------------------------------------- + + 12/15/2003 Initial port to u-boot by Sascha Hauer + +TODO: Homerun NIC and longrun NIC are not functional, only internal at the + moment. +*/ + +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_DM9000 + +#include "dm9000x.h" + +/* Board/System/Debug information/definition ---------------- */ + +#define DM9801_NOISE_FLOOR 0x08 +#define DM9802_NOISE_FLOOR 0x05 + +/* #define CONFIG_DM9000_DEBUG */ + +#ifdef CONFIG_DM9000_DEBUG +#define DM9000_DBG(fmt,args...) printf(fmt ,##args) +#else /* */ +#define DM9000_DBG(fmt,args...) +#endif /* */ +enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD = + 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO = + 8, DM9000_1M_HPNA = 0x10 +}; +enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2 +}; + +/* Structure/enum declaration ------------------------------- */ +typedef struct board_info { + u32 runt_length_counter; /* counter: RX length < 64byte */ + u32 long_length_counter; /* counter: RX length > 1514byte */ + u32 reset_counter; /* counter: RESET */ + u32 reset_tx_timeout; /* RESET caused by TX Timeout */ + u32 reset_rx_status; /* RESET caused by RX Statsus wrong */ + u16 tx_pkt_cnt; + u16 queue_start_addr; + u16 dbug_cnt; + u8 phy_addr; + u8 device_wait_reset; /* device state */ + u8 nic_type; /* NIC type */ + unsigned char srom[128]; +} board_info_t; +board_info_t dmfe_info; + +/* For module input parameter */ +static int media_mode = DM9000_AUTO; +static u8 nfloor = 0; + +/* function declaration ------------------------------------- */ +int eth_init(bd_t * bd); +int eth_send(volatile void *, int); +int eth_rx(void); +void eth_halt(void); +static int dm9000_probe(void); +static u16 phy_read(int); +static void phy_write(int, u16); +static u16 read_srom_word(int); +static u8 DM9000_ior(int); +static void DM9000_iow(int reg, u8 value); + +/* DM9000 network board routine ---------------------------- */ + +#define DM9000_outb(d,r) ( *(volatile u8 *)r = d ) +#define DM9000_outw(d,r) ( *(volatile u16 *)r = d ) +#define DM9000_outl(d,r) ( *(volatile u32 *)r = d ) +#define DM9000_inb(r) (*(volatile u8 *)r) +#define DM9000_inw(r) (*(volatile u16 *)r) +#define DM9000_inl(r) (*(volatile u32 *)r) + +#ifdef CONFIG_DM9000_DEBUG +static void +dump_regs(void) +{ + DM9000_DBG("\n"); + DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0)); + DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1)); + DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2)); + DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3)); + DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); + DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); + DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); + DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR)); + DM9000_DBG("\n"); +} +#endif /* */ + +/* + Search DM9000 board, allocate space and register it +*/ +int +dm9000_probe(void) +{ + u32 id_val; + id_val = DM9000_ior(DM9000_VIDL); + id_val |= DM9000_ior(DM9000_VIDH) << 8; + id_val |= DM9000_ior(DM9000_PIDL) << 16; + id_val |= DM9000_ior(DM9000_PIDH) << 24; + if (id_val == DM9000_ID) { + printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, + id_val); + return 0; + } else { + printf("dm9000 not found at 0x%08x id: 0x%08x\n", + CONFIG_DM9000_BASE, id_val); + return -1; + } +} + +/* Set PHY operationg mode +*/ +static void +set_PHY_mode(void) +{ + u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000; + if (!(media_mode & DM9000_AUTO)) { + switch (media_mode) { + case DM9000_10MHD: + phy_reg4 = 0x21; + phy_reg0 = 0x0000; + break; + case DM9000_10MFD: + phy_reg4 = 0x41; + phy_reg0 = 0x1100; + break; + case DM9000_100MHD: + phy_reg4 = 0x81; + phy_reg0 = 0x2000; + break; + case DM9000_100MFD: + phy_reg4 = 0x101; + phy_reg0 = 0x3100; + break; + } + phy_write(4, phy_reg4); /* Set PHY media mode */ + phy_write(0, phy_reg0); /* Tmp */ + } + DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */ + DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */ +} + +/* + Init HomeRun DM9801 +*/ +static void +program_dm9801(u16 HPNA_rev) +{ + __u16 reg16, reg17, reg24, reg25; + if (!nfloor) + nfloor = DM9801_NOISE_FLOOR; + reg16 = phy_read(16); + reg17 = phy_read(17); + reg24 = phy_read(24); + reg25 = phy_read(25); + switch (HPNA_rev) { + case 0xb900: /* DM9801 E3 */ + reg16 |= 0x1000; + reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000; + break; + case 0xb901: /* DM9801 E4 */ + reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200; + reg17 = (reg17 & 0xfff0) + nfloor + 3; + break; + case 0xb902: /* DM9801 E5 */ + case 0xb903: /* DM9801 E6 */ + default: + reg16 |= 0x1000; + reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200; + reg17 = (reg17 & 0xfff0) + nfloor; + } + phy_write(16, reg16); + phy_write(17, reg17); + phy_write(25, reg25); +} + +/* + Init LongRun DM9802 +*/ +static void +program_dm9802(void) +{ + __u16 reg25; + if (!nfloor) + nfloor = DM9802_NOISE_FLOOR; + reg25 = phy_read(25); + reg25 = (reg25 & 0xff00) + nfloor; + phy_write(25, reg25); +} + +/* Identify NIC type +*/ +static void +identify_nic(void) +{ + struct board_info *db = &dmfe_info; /* Point a board information structure */ + u16 phy_reg3; + DM9000_iow(DM9000_NCR, NCR_EXT_PHY); + phy_reg3 = phy_read(3); + switch (phy_reg3 & 0xfff0) { + case 0xb900: + if (phy_read(31) == 0x4404) { + db->nic_type = HOMERUN_NIC; + program_dm9801(phy_reg3); + DM9000_DBG("found homerun NIC\n"); + } else { + db->nic_type = LONGRUN_NIC; + DM9000_DBG("found longrun NIC\n"); + program_dm9802(); + } + break; + default: + db->nic_type = FASTETHER_NIC; + break; + } + DM9000_iow(DM9000_NCR, 0); +} + +/* General Purpose dm9000 reset routine */ +static void +dm9000_reset(void) +{ + DM9000_DBG("resetting\n"); + DM9000_iow(DM9000_NCR, NCR_RST); + udelay(1000); /* delay 1ms */ +} + +/* Initilize dm9000 board +*/ +int +eth_init(bd_t * bd) +{ + int i, oft, lnk; + DM9000_DBG("eth_init()\n"); + + /* RESET device */ + dm9000_reset(); + dm9000_probe(); + + /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ + identify_nic(); + + /* GPIO0 on pre-activate PHY */ + DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */ + + /* Set PHY */ + set_PHY_mode(); + + /* Program operating register */ + DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ + DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ + DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ + DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ + DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ + DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ + DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ + DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ + + /* Set Node address */ + for (i = 0; i < 6; i++) + ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); + printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], + bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], + bd->bi_enetaddr[4], bd->bi_enetaddr[5]); + for (i = 0, oft = 0x10; i < 6; i++, oft++) + DM9000_iow(oft, bd->bi_enetaddr[i]); + for (i = 0, oft = 0x16; i < 8; i++, oft++) + DM9000_iow(oft, 0xff); + + /* read back mac, just to be sure */ + for (i = 0, oft = 0x10; i < 6; i++, oft++) + DM9000_DBG("%02x:", DM9000_ior(oft)); + DM9000_DBG("\n"); + + /* Activate DM9000 */ + DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ + DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ + i = 0; + while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ + udelay(1000); + i++; + if (i == 10000) { + printf("could not establish link\n"); + return 0; + } + } + + /* see what we've got */ + lnk = phy_read(17) >> 12; + printf("operating at "); + switch (lnk) { + case 1: + printf("10M half duplex "); + break; + case 2: + printf("10M full duplex "); + break; + case 4: + printf("100M half duplex "); + break; + case 8: + printf("100M full duplex "); + break; + default: + printf("unknown: %d ", lnk); + break; + } + printf("mode\n"); + return 0; +} + +/* + Hardware start transmission. + Send a packet to media from the upper layer. +*/ +int +eth_send(volatile void *packet, int length) +{ + char *data_ptr; + u32 tmplen, i; + int tmo; + DM9000_DBG("eth_send: length: %d\n", length); + for (i = 0; i < length; i++) { + if (i % 8 == 0) + DM9000_DBG("\nSend: 02x: ", i); + DM9000_DBG("%02x ", ((unsigned char *) packet)[i]); + } DM9000_DBG("\n"); + + /* Move data to DM9000 TX RAM */ + data_ptr = (char *) packet; + DM9000_outb(DM9000_MWCMD, DM9000_IO); + +#ifdef CONFIG_DM9000_USE_8BIT + /* Byte mode */ + for (i = 0; i < length; i++) + DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_16BIT + tmplen = (length + 1) / 2; + for (i = 0; i < tmplen; i++) + DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_32BIT + tmplen = (length + 3) / 4; + for (i = 0; i < tmplen; i++) + DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); + +#endif /* */ + + /* Set TX length to DM9000 */ + DM9000_iow(DM9000_TXPLL, length & 0xff); + DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); + + /* Issue TX polling command */ + DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ + + /* wait for end of transmission */ + tmo = get_timer(0) + 5 * CFG_HZ; + while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) { + if (get_timer(0) >= tmo) { + printf("transmission timeout\n"); + break; + } + } + DM9000_DBG("transmit done\n\n"); + return 0; +} + +/* + Stop the interface. + The interface is stopped when it is brought. +*/ +void +eth_halt(void) +{ + DM9000_DBG("eth_halt\n"); + + /* RESET devie */ + phy_write(0, 0x8000); /* PHY RESET */ + DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ + DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ + DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ +} + +/* + Received a packet and pass to upper layer +*/ +int +eth_rx(void) +{ + u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; + u16 RxStatus, RxLen = 0; + u32 tmplen, i; + + /* Check packet ready or not */ + DM9000_ior(DM9000_MRCMDX); /* Dummy read */ + rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */ + if (rxbyte == 0) + return 0; + + /* Status check: this byte must be 0 or 1 */ + if (rxbyte > 1) { + DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ + DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ + DM9000_DBG("rx status check: %d\n", rxbyte); + } + DM9000_DBG("receiving packet\n"); + + /* A packet ready now & Get status/length */ + DM9000_outb(DM9000_MRCMD, DM9000_IO); + +#ifdef CONFIG_DM9000_USE_8BIT + RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); + RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_16BIT + RxStatus = DM9000_inw(DM9000_DATA); + RxLen = DM9000_inw(DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_32BIT + tmpdata = DM9000_inl(DM9000_DATA); + RxStatus = tmpdata; + RxLen = tmpdata >> 16; + +#endif /* */ + DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); + + /* Move data from DM9000 */ + /* Read received packet from RX SRAM */ +#ifdef CONFIG_DM9000_USE_8BIT + for (i = 0; i < RxLen; i++) + rdptr[i] = DM9000_inb(DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_16BIT + tmplen = (RxLen + 1) / 2; + for (i = 0; i < tmplen; i++) + ((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_32BIT + tmplen = (RxLen + 3) / 4; + for (i = 0; i < tmplen; i++) + ((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA); + +#endif /* */ + if ((RxStatus & 0xbf00) || (RxLen < 0x40) + || (RxLen > DM9000_PKT_MAX)) { + if (RxStatus & 0x100) { + printf("rx fifo error\n"); + } + if (RxStatus & 0x200) { + printf("rx crc error\n"); + } + if (RxStatus & 0x8000) { + printf("rx length error\n"); + } + if (RxLen > DM9000_PKT_MAX) { + printf("rx length too big\n"); + dm9000_reset(); + } + } else { + + /* Pass to upper layer */ + DM9000_DBG("passing packet to upper layer\n"); + NetReceive(NetRxPackets[0], RxLen); + return RxLen; + } + return 0; +} + +/* + Read a word data from SROM +*/ +static u16 +read_srom_word(int offset) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPCR, 0x4); + udelay(200); + DM9000_iow(DM9000_EPCR, 0x0); + return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); +} + +/* + Read a byte from I/O port +*/ +static u8 +DM9000_ior(int reg) +{ + DM9000_outb(reg, DM9000_IO); + return DM9000_inb(DM9000_DATA); +} + +/* + Write a byte to I/O port +*/ +static void +DM9000_iow(int reg, u8 value) +{ + DM9000_outb(reg, DM9000_IO); + DM9000_outb(value, DM9000_DATA); +} + +/* + Read a word from phyxcer +*/ +static u16 +phy_read(int reg) +{ + u16 val; + + /* Fill the phyxcer register into REG_0C */ + DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ + udelay(100); /* Wait read complete */ + DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ + val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); + + /* The read data keeps on REG_0D & REG_0E */ + DM9000_DBG("phy_read(%d): %d\n", reg, val); + return val; +} + +/* + Write a word to phyxcer +*/ +static void +phy_write(int reg, u16 value) +{ + + /* Fill the phyxcer register into REG_0C */ + DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + + /* Fill the written data into REG_0D & REG_0E */ + DM9000_iow(DM9000_EPDRL, (value & 0xff)); + DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); + DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ + udelay(500); /* Wait write complete */ + DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ + DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value); +} +#endif /* CONFIG_DRIVER_DM9000 */ diff --git a/drivers/dm9000x.h b/drivers/dm9000x.h new file mode 100644 index 0000000..f47ff8c --- /dev/null +++ b/drivers/dm9000x.h @@ -0,0 +1,119 @@ +/* + * dm9000 Ethernet + */ + +#ifdef CONFIG_DRIVER_DM9000 + +#define DM9000_ID 0x90000A46 +#define DM9000_PKT_MAX 1536 /* Received packet max size */ +#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */ + +/* although the registers are 16 bit, they are 32-bit aligned. + */ + +#define DM9000_NCR 0x00 +#define DM9000_NSR 0x01 +#define DM9000_TCR 0x02 +#define DM9000_TSR1 0x03 +#define DM9000_TSR2 0x04 +#define DM9000_RCR 0x05 +#define DM9000_RSR 0x06 +#define DM9000_ROCR 0x07 +#define DM9000_BPTR 0x08 +#define DM9000_FCTR 0x09 +#define DM9000_FCR 0x0A +#define DM9000_EPCR 0x0B +#define DM9000_EPAR 0x0C +#define DM9000_EPDRL 0x0D +#define DM9000_EPDRH 0x0E +#define DM9000_WCR 0x0F + +#define DM9000_PAR 0x10 +#define DM9000_MAR 0x16 + +#define DM9000_GPCR 0x1e +#define DM9000_GPR 0x1f +#define DM9000_TRPAL 0x22 +#define DM9000_TRPAH 0x23 +#define DM9000_RWPAL 0x24 +#define DM9000_RWPAH 0x25 + +#define DM9000_VIDL 0x28 +#define DM9000_VIDH 0x29 +#define DM9000_PIDL 0x2A +#define DM9000_PIDH 0x2B + +#define DM9000_CHIPR 0x2C +#define DM9000_SMCR 0x2F + +#define DM9000_PHY 0x40 /* PHY address 0x01 */ + +#define DM9000_MRCMDX 0xF0 +#define DM9000_MRCMD 0xF2 +#define DM9000_MRRL 0xF4 +#define DM9000_MRRH 0xF5 +#define DM9000_MWCMDX 0xF6 +#define DM9000_MWCMD 0xF8 +#define DM9000_MWRL 0xFA +#define DM9000_MWRH 0xFB +#define DM9000_TXPLL 0xFC +#define DM9000_TXPLH 0xFD +#define DM9000_ISR 0xFE +#define DM9000_IMR 0xFF + +#define NCR_EXT_PHY (1<<7) +#define NCR_WAKEEN (1<<6) +#define NCR_FCOL (1<<4) +#define NCR_FDX (1<<3) +#define NCR_LBK (3<<1) +#define NCR_RST (1<<0) + +#define NSR_SPEED (1<<7) +#define NSR_LINKST (1<<6) +#define NSR_WAKEST (1<<5) +#define NSR_TX2END (1<<3) +#define NSR_TX1END (1<<2) +#define NSR_RXOV (1<<1) + +#define TCR_TJDIS (1<<6) +#define TCR_EXCECM (1<<5) +#define TCR_PAD_DIS2 (1<<4) +#define TCR_CRC_DIS2 (1<<3) +#define TCR_PAD_DIS1 (1<<2) +#define TCR_CRC_DIS1 (1<<1) +#define TCR_TXREQ (1<<0) + +#define TSR_TJTO (1<<7) +#define TSR_LC (1<<6) +#define TSR_NC (1<<5) +#define TSR_LCOL (1<<4) +#define TSR_COL (1<<3) +#define TSR_EC (1<<2) + +#define RCR_WTDIS (1<<6) +#define RCR_DIS_LONG (1<<5) +#define RCR_DIS_CRC (1<<4) +#define RCR_ALL (1<<3) +#define RCR_RUNT (1<<2) +#define RCR_PRMSC (1<<1) +#define RCR_RXEN (1<<0) + +#define RSR_RF (1<<7) +#define RSR_MF (1<<6) +#define RSR_LCS (1<<5) +#define RSR_RWTO (1<<4) +#define RSR_PLE (1<<3) +#define RSR_AE (1<<2) +#define RSR_CE (1<<1) +#define RSR_FOE (1<<0) + +#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 ) +#define FCTR_LWOT(ot) ( ot & 0xf ) + +#define IMR_PAR (1<<7) +#define IMR_ROOM (1<<3) +#define IMR_ROM (1<<2) +#define IMR_PTM (1<<1) +#define IMR_PRM (1<<0) + +#endif diff --git a/drivers/ds1722.c b/drivers/ds1722.c new file mode 100644 index 0000000..227d816 --- /dev/null +++ b/drivers/ds1722.c @@ -0,0 +1,142 @@ + +#include + +#include + +#ifdef CONFIG_DS1722 + +static void ds1722_select(int dev) +{ + ssi_set_interface(4096, 0, 0, 0); + ssi_chip_select(0); + udelay(1); + ssi_chip_select(dev); + udelay(1); +} + + +u8 ds1722_read(int dev, int addr) +{ + u8 res; + + ds1722_select(dev); + + ssi_tx_byte(addr); + res = ssi_rx_byte(); + + ssi_chip_select(0); + + return res; +} + +void ds1722_write(int dev, int addr, u8 data) +{ + ds1722_select(dev); + + ssi_tx_byte(0x80|addr); + ssi_tx_byte(data); + + ssi_chip_select(0); +} + + +u16 ds1722_temp(int dev, int resolution) +{ + static int useconds[] = { + 75000, 150000, 300000, 600000, 1200000 + }; + char temp; + u16 res; + + + /* set up the desired resulotion ... */ + ds1722_write(dev, 0, 0xe0 | (resolution << 1)); + + /* wait while the chip measures the tremperature */ + udelay(useconds[resolution]); + + res = (temp = ds1722_read(dev, 2)) << 8; + + if (temp < 0) { + temp = (16 - (ds1722_read(dev, 1) >> 4)) & 0x0f; + } else { + temp = (ds1722_read(dev, 1) >> 4); + } + + switch (temp) { + case 0: + /* .0000 */ + break; + case 1: + /* .0625 */ + res |=1; + break; + case 2: + /* .1250 */ + res |=1; + break; + case 3: + /* .1875 */ + res |=2; + break; + case 4: + /* .2500 */ + res |=3; + break; + case 5: + /* .3125 */ + res |=3; + break; + case 6: + /* .3750 */ + res |=4; + break; + case 7: + /* .4375 */ + res |=4; + break; + case 8: + /* .5000 */ + res |=5; + break; + case 9: + /* .5625 */ + res |=6; + break; + case 10: + /* .6250 */ + res |=6; + break; + case 11: + /* .6875 */ + res |=7; + break; + case 12: + /* .7500 */ + res |=8; + break; + case 13: + /* .8125 */ + res |=8; + break; + case 14: + /* .8750 */ + res |=9; + break; + case 15: + /* .9375 */ + res |=9; + break; + } + return res; + +} + +int ds1722_probe(int dev) +{ + u16 temp = ds1722_temp(dev, DS1722_RESOLUTION_12BIT); + printf("%d.%d deg C\n\n", (char)(temp >> 8), temp & 0xff); + return 0; +} + +#endif diff --git a/drivers/e1000.c b/drivers/e1000.c new file mode 100644 index 0000000..927acbb --- /dev/null +++ b/drivers/e1000.c @@ -0,0 +1,3016 @@ +/************************************************************************** +Inter Pro 1000 for ppcboot/das-u-boot +Drivers are port from Intel's Linux driver e1000-4.3.15 +and from Etherboot pro 1000 driver by mrakes at vivato dot net +tested on both gig copper and gig fiber boards +***************************************************************************/ +/******************************************************************************* + + + Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program; if not, write to the Free Software Foundation, Inc., 59 + Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + The full GNU General Public License is included in this distribution in the + file called LICENSE. + + Contact Information: + Linux NICS + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +*******************************************************************************/ +/* + * Copyright (C) Archway Digital Solutions. + * + * written by Chrsitopher Li or + * 2/9/2002 + * + * Copyright (C) Linux Networx. + * Massive upgrade to work with the new intel gigabit NICs. + * + */ + +#include "e1000.h" + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_E1000) + +#define TOUT_LOOP 100000 + +#undef virt_to_bus +#define virt_to_bus(x) ((unsigned long)x) +#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) +#define mdelay(n) udelay((n)*1000) + +#define E1000_DEFAULT_PBA 0x00000030 + +/* NIC specific static variables go here */ + +static char tx_pool[128 + 16]; +static char rx_pool[128 + 16]; +static char packet[2096]; + +static struct e1000_tx_desc *tx_base; +static struct e1000_rx_desc *rx_base; + +static int tx_tail; +static int rx_tail, rx_last; + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, +}; + +/* Function forward declarations */ +static int e1000_setup_link(struct eth_device *nic); +static int e1000_setup_fiber_link(struct eth_device *nic); +static int e1000_setup_copper_link(struct eth_device *nic); +static int e1000_phy_setup_autoneg(struct e1000_hw *hw); +static void e1000_config_collision_dist(struct e1000_hw *hw); +static int e1000_config_mac_to_phy(struct e1000_hw *hw); +static int e1000_config_fc_after_link_up(struct e1000_hw *hw); +static int e1000_check_for_link(struct eth_device *nic); +static int e1000_wait_autoneg(struct e1000_hw *hw); +static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, + uint16_t * duplex); +static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t * phy_data); +static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t phy_data); +static void e1000_phy_hw_reset(struct e1000_hw *hw); +static int e1000_phy_reset(struct e1000_hw *hw); +static int e1000_detect_gig_phy(struct e1000_hw *hw); + +#define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg))) +#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg)) +#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ + writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) +#define E1000_READ_REG_ARRAY(a, reg, offset) ( \ + readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) +#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} + +#ifndef CONFIG_AP1000 /* remove for warnings */ +/****************************************************************************** + * Raises the EEPROM's clock input. + * + * hw - Struct containing variables accessed by shared code + * eecd - EECD's current value + *****************************************************************************/ +static void +e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) +{ + /* Raise the clock input to the EEPROM (by setting the SK bit), and then + * wait 50 microseconds. + */ + *eecd = *eecd | E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, *eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); +} + +/****************************************************************************** + * Lowers the EEPROM's clock input. + * + * hw - Struct containing variables accessed by shared code + * eecd - EECD's current value + *****************************************************************************/ +static void +e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) +{ + /* Lower the clock input to the EEPROM (by clearing the SK bit), and then + * wait 50 microseconds. + */ + *eecd = *eecd & ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, *eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); +} + +/****************************************************************************** + * Shift data bits out to the EEPROM. + * + * hw - Struct containing variables accessed by shared code + * data - data to send to the EEPROM + * count - number of bits to shift out + *****************************************************************************/ +static void +e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) +{ + uint32_t eecd; + uint32_t mask; + + /* We need to shift "count" bits out to the EEPROM. So, value in the + * "data" parameter will be shifted out to the EEPROM one bit at a time. + * In order to do this, "data" must be broken down into bits. + */ + mask = 0x01 << (count - 1); + eecd = E1000_READ_REG(hw, EECD); + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); + do { + /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", + * and then raising and then lowering the clock (the SK bit controls + * the clock input to the EEPROM). A "0" is shifted out to the EEPROM + * by setting "DI" to "0" and then raising and then lowering the clock. + */ + eecd &= ~E1000_EECD_DI; + + if (data & mask) + eecd |= E1000_EECD_DI; + + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + + udelay(50); + + e1000_raise_ee_clk(hw, &eecd); + e1000_lower_ee_clk(hw, &eecd); + + mask = mask >> 1; + + } while (mask); + + /* We leave the "DI" bit set to "0" when we leave this routine. */ + eecd &= ~E1000_EECD_DI; + E1000_WRITE_REG(hw, EECD, eecd); +} + +/****************************************************************************** + * Shift data bits in from the EEPROM + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static uint16_t +e1000_shift_in_ee_bits(struct e1000_hw *hw) +{ + uint32_t eecd; + uint32_t i; + uint16_t data; + + /* In order to read a register from the EEPROM, we need to shift 16 bits + * in from the EEPROM. Bits are "shifted in" by raising the clock input to + * the EEPROM (setting the SK bit), and then reading the value of the "DO" + * bit. During this "shifting in" process the "DI" bit should always be + * clear.. + */ + + eecd = E1000_READ_REG(hw, EECD); + + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); + data = 0; + + for (i = 0; i < 16; i++) { + data = data << 1; + e1000_raise_ee_clk(hw, &eecd); + + eecd = E1000_READ_REG(hw, EECD); + + eecd &= ~(E1000_EECD_DI); + if (eecd & E1000_EECD_DO) + data |= 1; + + e1000_lower_ee_clk(hw, &eecd); + } + + return data; +} + +/****************************************************************************** + * Prepares EEPROM for access + * + * hw - Struct containing variables accessed by shared code + * + * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This + * function should be called before issuing a command to the EEPROM. + *****************************************************************************/ +static void +e1000_setup_eeprom(struct e1000_hw *hw) +{ + uint32_t eecd; + + eecd = E1000_READ_REG(hw, EECD); + + /* Clear SK and DI */ + eecd &= ~(E1000_EECD_SK | E1000_EECD_DI); + E1000_WRITE_REG(hw, EECD, eecd); + + /* Set CS */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); +} + +/****************************************************************************** + * Returns EEPROM to a "standby" state + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static void +e1000_standby_eeprom(struct e1000_hw *hw) +{ + uint32_t eecd; + + eecd = E1000_READ_REG(hw, EECD); + + /* Deselct EEPROM */ + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); + + /* Clock high */ + eecd |= E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); + + /* Select EEPROM */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); + + /* Clock low */ + eecd &= ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); +} + +/****************************************************************************** + * Reads a 16 bit word from the EEPROM. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to read + * data - word read from the EEPROM + *****************************************************************************/ +static int +e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data) +{ + uint32_t eecd; + uint32_t i = 0; + int large_eeprom = FALSE; + + /* Request EEPROM Access */ + if (hw->mac_type > e1000_82544) { + eecd = E1000_READ_REG(hw, EECD); + if (eecd & E1000_EECD_SIZE) + large_eeprom = TRUE; + eecd |= E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + eecd = E1000_READ_REG(hw, EECD); + while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { + i++; + udelay(10); + eecd = E1000_READ_REG(hw, EECD); + } + if (!(eecd & E1000_EECD_GNT)) { + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + DEBUGOUT("Could not acquire EEPROM grant\n"); + return -E1000_ERR_EEPROM; + } + } + + /* Prepare the EEPROM for reading */ + e1000_setup_eeprom(hw); + + /* Send the READ command (opcode + addr) */ + e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3); + e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6); + + /* Read the data */ + *data = e1000_shift_in_ee_bits(hw); + + /* End this read operation */ + e1000_standby_eeprom(hw); + + /* Stop requesting EEPROM access */ + if (hw->mac_type > e1000_82544) { + eecd = E1000_READ_REG(hw, EECD); + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + } + + return 0; +} + +#if 0 +static void +e1000_eeprom_cleanup(struct e1000_hw *hw) +{ + uint32_t eecd; + + eecd = E1000_READ_REG(hw, EECD); + eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); + E1000_WRITE_REG(hw, EECD, eecd); + e1000_raise_ee_clk(hw, &eecd); + e1000_lower_ee_clk(hw, &eecd); +} + +static uint16_t +e1000_wait_eeprom_done(struct e1000_hw *hw) +{ + uint32_t eecd; + uint32_t i; + + e1000_standby_eeprom(hw); + for (i = 0; i < 200; i++) { + eecd = E1000_READ_REG(hw, EECD); + if (eecd & E1000_EECD_DO) + return (TRUE); + udelay(5); + } + return (FALSE); +} + +static int +e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data) +{ + uint32_t eecd; + int large_eeprom = FALSE; + int i = 0; + + /* Request EEPROM Access */ + if (hw->mac_type > e1000_82544) { + eecd = E1000_READ_REG(hw, EECD); + if (eecd & E1000_EECD_SIZE) + large_eeprom = TRUE; + eecd |= E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + eecd = E1000_READ_REG(hw, EECD); + while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { + i++; + udelay(5); + eecd = E1000_READ_REG(hw, EECD); + } + if (!(eecd & E1000_EECD_GNT)) { + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + DEBUGOUT("Could not acquire EEPROM grant\n"); + return FALSE; + } + } + e1000_setup_eeprom(hw); + e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5); + e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); + e1000_standby_eeprom(hw); + e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3); + e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6); + e1000_shift_out_ee_bits(hw, Data, 16); + if (!e1000_wait_eeprom_done(hw)) { + return FALSE; + } + e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5); + e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); + e1000_eeprom_cleanup(hw); + + /* Stop requesting EEPROM access */ + if (hw->mac_type > e1000_82544) { + eecd = E1000_READ_REG(hw, EECD); + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + } + i = 0; + eecd = E1000_READ_REG(hw, EECD); + while (((eecd & E1000_EECD_GNT)) && (i < 500)) { + i++; + udelay(10); + eecd = E1000_READ_REG(hw, EECD); + } + if ((eecd & E1000_EECD_GNT)) { + DEBUGOUT("Could not release EEPROM grant\n"); + } + return TRUE; +} +#endif + +/****************************************************************************** + * Verifies that the EEPROM has a valid checksum + * + * hw - Struct containing variables accessed by shared code + * + * Reads the first 64 16 bit words of the EEPROM and sums the values read. + * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is + * valid. + *****************************************************************************/ +static int +e1000_validate_eeprom_checksum(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint16_t checksum = 0; + uint16_t i, eeprom_data; + + DEBUGFUNC(); + + for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { + if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + checksum += eeprom_data; + } + + if (checksum == (uint16_t) EEPROM_SUM) { + return 0; + } else { + DEBUGOUT("EEPROM Checksum Invalid\n"); + return -E1000_ERR_EEPROM; + } +} +#endif /* #ifndef CONFIG_AP1000 */ + +/****************************************************************************** + * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the + * second function of dual function devices + * + * nic - Struct containing variables accessed by shared code + *****************************************************************************/ +static int +e1000_read_mac_addr(struct eth_device *nic) +{ +#ifndef CONFIG_AP1000 + struct e1000_hw *hw = nic->priv; + uint16_t offset; + uint16_t eeprom_data; + int i; + + DEBUGFUNC(); + + for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { + offset = i >> 1; + if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + nic->enetaddr[i] = eeprom_data & 0xff; + nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; + } + if ((hw->mac_type == e1000_82546) && + (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + /* Invert the last bit if this is the second device */ + nic->enetaddr[5] += 1; + } +#else + /* + * The AP1000's e1000 has no eeprom; the MAC address is stored in the + * environment variables. Currently this does not support the addition + * of a PMC e1000 card, which is certainly a possibility, so this should + * be updated to properly use the env variable only for the onboard e1000 + */ + + int ii; + char *s, *e; + + DEBUGFUNC(); + + s = getenv ("ethaddr"); + if (s == NULL){ + return -E1000_ERR_EEPROM; + } + else{ + for(ii = 0; ii < 6; ii++) { + nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; + if (s){ + s = (*e) ? e + 1 : e; + } + } + } +#endif + return 0; +} + +/****************************************************************************** + * Initializes receive address filters. + * + * hw - Struct containing variables accessed by shared code + * + * Places the MAC address in receive address register 0 and clears the rest + * of the receive addresss registers. Clears the multicast table. Assumes + * the receiver is in reset when the routine is called. + *****************************************************************************/ +static void +e1000_init_rx_addrs(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t i; + uint32_t addr_low; + uint32_t addr_high; + + DEBUGFUNC(); + + /* Setup the receive address. */ + DEBUGOUT("Programming MAC Address into RAR[0]\n"); + addr_low = (nic->enetaddr[0] | + (nic->enetaddr[1] << 8) | + (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); + + addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); + + E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); + E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); + + /* Zero out the other 15 receive addresses. */ + DEBUGOUT("Clearing RAR[1-15]\n"); + for (i = 1; i < E1000_RAR_ENTRIES; i++) { + E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); + E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); + } +} + +/****************************************************************************** + * Clears the VLAN filer table + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static void +e1000_clear_vfta(struct e1000_hw *hw) +{ + uint32_t offset; + + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) + E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); +} + +/****************************************************************************** + * Set the mac type member in the hw struct. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static int +e1000_set_mac_type(struct e1000_hw *hw) +{ + DEBUGFUNC(); + + switch (hw->device_id) { + case E1000_DEV_ID_82542: + switch (hw->revision_id) { + case E1000_82542_2_0_REV_ID: + hw->mac_type = e1000_82542_rev2_0; + break; + case E1000_82542_2_1_REV_ID: + hw->mac_type = e1000_82542_rev2_1; + break; + default: + /* Invalid 82542 revision ID */ + return -E1000_ERR_MAC_TYPE; + } + break; + case E1000_DEV_ID_82543GC_FIBER: + case E1000_DEV_ID_82543GC_COPPER: + hw->mac_type = e1000_82543; + break; + case E1000_DEV_ID_82544EI_COPPER: + case E1000_DEV_ID_82544EI_FIBER: + case E1000_DEV_ID_82544GC_COPPER: + case E1000_DEV_ID_82544GC_LOM: + hw->mac_type = e1000_82544; + break; + case E1000_DEV_ID_82540EM: + case E1000_DEV_ID_82540EM_LOM: + hw->mac_type = e1000_82540; + break; + case E1000_DEV_ID_82545EM_COPPER: + case E1000_DEV_ID_82545EM_FIBER: + hw->mac_type = e1000_82545; + break; + case E1000_DEV_ID_82546EB_COPPER: + case E1000_DEV_ID_82546EB_FIBER: + hw->mac_type = e1000_82546; + break; + default: + /* Should never have loaded on this device */ + return -E1000_ERR_MAC_TYPE; + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Reset the transmit and receive units; mask and clear all interrupts. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +void +e1000_reset_hw(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint32_t ctrl_ext; + uint32_t icr; + uint32_t manc; + + DEBUGFUNC(); + + /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ + if (hw->mac_type == e1000_82542_rev2_0) { + DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); + pci_write_config_word(hw->pdev, PCI_COMMAND, + hw-> + pci_cmd_word & ~PCI_COMMAND_INVALIDATE); + } + + /* Clear interrupt mask to stop board from generating interrupts */ + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, IMC, 0xffffffff); + + /* Disable the Transmit and Receive units. Then delay to allow + * any pending transactions to complete before we hit the MAC with + * the global reset. + */ + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + + /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ + hw->tbi_compatibility_on = FALSE; + + /* Delay to allow any outstanding PCI transactions to complete before + * resetting the device + */ + mdelay(10); + + /* Issue a global reset to the MAC. This will reset the chip's + * transmit, receive, DMA, and link units. It will not effect + * the current PCI configuration. The global reset bit is self- + * clearing, and should clear within a microsecond. + */ + DEBUGOUT("Issuing a global reset to MAC\n"); + ctrl = E1000_READ_REG(hw, CTRL); + +#if 0 + if (hw->mac_type > e1000_82543) + E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); + else +#endif + E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); + + /* Force a reload from the EEPROM if necessary */ + if (hw->mac_type < e1000_82540) { + /* Wait for reset to complete */ + udelay(10); + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_EE_RST; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + /* Wait for EEPROM reload */ + mdelay(2); + } else { + /* Wait for EEPROM reload (it happens automatically) */ + mdelay(4); + /* Dissable HW ARPs on ASF enabled adapters */ + manc = E1000_READ_REG(hw, MANC); + manc &= ~(E1000_MANC_ARP_EN); + E1000_WRITE_REG(hw, MANC, manc); + } + + /* Clear interrupt mask to stop board from generating interrupts */ + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, IMC, 0xffffffff); + + /* Clear any pending interrupt events. */ + icr = E1000_READ_REG(hw, ICR); + + /* If MWI was previously enabled, reenable it. */ + if (hw->mac_type == e1000_82542_rev2_0) { + pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); + } +} + +/****************************************************************************** + * Performs basic configuration of the adapter. + * + * hw - Struct containing variables accessed by shared code + * + * Assumes that the controller has previously been reset and is in a + * post-reset uninitialized state. Initializes the receive address registers, + * multicast table, and VLAN filter table. Calls routines to setup link + * configuration and flow control settings. Clears all on-chip counters. Leaves + * the transmit and receive units disabled and uninitialized. + *****************************************************************************/ +static int +e1000_init_hw(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t ctrl, status; + uint32_t i; + int32_t ret_val; + uint16_t pcix_cmd_word; + uint16_t pcix_stat_hi_word; + uint16_t cmd_mmrbc; + uint16_t stat_mmrbc; + e1000_bus_type bus_type = e1000_bus_type_unknown; + + DEBUGFUNC(); +#if 0 + /* Initialize Identification LED */ + ret_val = e1000_id_led_init(hw); + if (ret_val < 0) { + DEBUGOUT("Error Initializing Identification LED\n"); + return ret_val; + } +#endif + /* Set the Media Type and exit with error if it is not valid. */ + if (hw->mac_type != e1000_82543) { + /* tbi_compatibility is only valid on 82543 */ + hw->tbi_compatibility_en = FALSE; + } + + if (hw->mac_type >= e1000_82543) { + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_TBIMODE) { + hw->media_type = e1000_media_type_fiber; + /* tbi_compatibility not valid on fiber */ + hw->tbi_compatibility_en = FALSE; + } else { + hw->media_type = e1000_media_type_copper; + } + } else { + /* This is an 82542 (fiber only) */ + hw->media_type = e1000_media_type_fiber; + } + + /* Disabling VLAN filtering. */ + DEBUGOUT("Initializing the IEEE VLAN\n"); + E1000_WRITE_REG(hw, VET, 0); + + e1000_clear_vfta(hw); + + /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ + if (hw->mac_type == e1000_82542_rev2_0) { + DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); + pci_write_config_word(hw->pdev, PCI_COMMAND, + hw-> + pci_cmd_word & ~PCI_COMMAND_INVALIDATE); + E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); + E1000_WRITE_FLUSH(hw); + mdelay(5); + } + + /* Setup the receive address. This involves initializing all of the Receive + * Address Registers (RARs 0 - 15). + */ + e1000_init_rx_addrs(nic); + + /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ + if (hw->mac_type == e1000_82542_rev2_0) { + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_FLUSH(hw); + mdelay(1); + pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); + } + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < E1000_MC_TBL_SIZE; i++) + E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); + +#if 0 + /* Set the PCI priority bit correctly in the CTRL register. This + * determines if the adapter gives priority to receives, or if it + * gives equal priority to transmits and receives. + */ + if (hw->dma_fairness) { + ctrl = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); + } +#endif + if (hw->mac_type >= e1000_82543) { + status = E1000_READ_REG(hw, STATUS); + bus_type = (status & E1000_STATUS_PCIX_MODE) ? + e1000_bus_type_pcix : e1000_bus_type_pci; + } + /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ + if (bus_type == e1000_bus_type_pcix) { + pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, + &pcix_cmd_word); + pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, + &pcix_stat_hi_word); + cmd_mmrbc = + (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> + PCIX_COMMAND_MMRBC_SHIFT; + stat_mmrbc = + (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> + PCIX_STATUS_HI_MMRBC_SHIFT; + if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) + stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; + if (cmd_mmrbc > stat_mmrbc) { + pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; + pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; + pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, + pcix_cmd_word); + } + } + + /* Call a subroutine to configure the link and setup flow control. */ + ret_val = e1000_setup_link(nic); + + /* Set the transmit descriptor write-back policy */ + if (hw->mac_type > e1000_82544) { + ctrl = E1000_READ_REG(hw, TXDCTL); + ctrl = + (ctrl & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB; + E1000_WRITE_REG(hw, TXDCTL, ctrl); + } +#if 0 + /* Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs(hw); +#endif + + return ret_val; +} + +/****************************************************************************** + * Configures flow control and link settings. + * + * hw - Struct containing variables accessed by shared code + * + * Determines which flow control settings to use. Calls the apropriate media- + * specific link configuration function. Configures the flow control settings. + * Assuming the adapter has a valid link partner, a valid link should be + * established. Assumes the hardware has previously been reset and the + * transmitter and receiver are not enabled. + *****************************************************************************/ +static int +e1000_setup_link(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t ctrl_ext; + int32_t ret_val; + uint16_t eeprom_data; + + DEBUGFUNC(); + +#ifndef CONFIG_AP1000 + /* Read and store word 0x0F of the EEPROM. This word contains bits + * that determine the hardware's default PAUSE (flow control) mode, + * a bit that determines whether the HW defaults to enabling or + * disabling auto-negotiation, and the direction of the + * SW defined pins. If there is no SW over-ride of the flow + * control setting, then the variable hw->fc will + * be initialized based on a value in the EEPROM. + */ + if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } +#else + /* we have to hardcode the proper value for our hardware. */ + /* this value is for the 82540EM pci card used for prototyping, and it works. */ + eeprom_data = 0xb220; +#endif + + if (hw->fc == e1000_fc_default) { + if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) + hw->fc = e1000_fc_none; + else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == + EEPROM_WORD0F_ASM_DIR) + hw->fc = e1000_fc_tx_pause; + else + hw->fc = e1000_fc_full; + } + + /* We want to save off the original Flow Control configuration just + * in case we get disconnected and then reconnected into a different + * hub or switch with different Flow Control capabilities. + */ + if (hw->mac_type == e1000_82542_rev2_0) + hw->fc &= (~e1000_fc_tx_pause); + + if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) + hw->fc &= (~e1000_fc_rx_pause); + + hw->original_fc = hw->fc; + + DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); + + /* Take the 4 bits from EEPROM word 0x0F that determine the initial + * polarity value for the SW controlled pins, and setup the + * Extended Device Control reg with that info. + * This is needed because one of the SW controlled pins is used for + * signal detection. So this should be done before e1000_setup_pcs_link() + * or e1000_phy_setup() is called. + */ + if (hw->mac_type == e1000_82543) { + ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << + SWDPIO__EXT_SHIFT); + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + } + + /* Call the necessary subroutine to configure the link. */ + ret_val = (hw->media_type == e1000_media_type_fiber) ? + e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); + if (ret_val < 0) { + return ret_val; + } + + /* Initialize the flow control address, type, and PAUSE timer + * registers to their default values. This is done even if flow + * control is disabled, because it does not hurt anything to + * initialize these registers. + */ + DEBUGOUT + ("Initializing the Flow Control address, type and timer regs\n"); + + E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); + E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); + E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); + E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); + + /* Set the flow control receive threshold registers. Normally, + * these registers will be set to a default threshold that may be + * adjusted later by the driver's runtime code. However, if the + * ability to transmit pause frames in not enabled, then these + * registers will be set to 0. + */ + if (!(hw->fc & e1000_fc_tx_pause)) { + E1000_WRITE_REG(hw, FCRTL, 0); + E1000_WRITE_REG(hw, FCRTH, 0); + } else { + /* We need to set up the Receive Threshold high and low water marks + * as well as (optionally) enabling the transmission of XON frames. + */ + if (hw->fc_send_xon) { + E1000_WRITE_REG(hw, FCRTL, + (hw->fc_low_water | E1000_FCRTL_XONE)); + E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); + } else { + E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); + E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); + } + } + return ret_val; +} + +/****************************************************************************** + * Sets up link for a fiber based adapter + * + * hw - Struct containing variables accessed by shared code + * + * Manipulates Physical Coding Sublayer functions in order to configure + * link. Assumes the hardware has been previously reset and the transmitter + * and receiver are not enabled. + *****************************************************************************/ +static int +e1000_setup_fiber_link(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t ctrl; + uint32_t status; + uint32_t txcw = 0; + uint32_t i; + uint32_t signal; + int32_t ret_val; + + DEBUGFUNC(); + /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be + * set when the optics detect a signal. On older adapters, it will be + * cleared when there is a signal + */ + ctrl = E1000_READ_REG(hw, CTRL); + if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) + signal = E1000_CTRL_SWDPIN1; + else + signal = 0; + + printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, + ctrl); + /* Take the link out of reset */ + ctrl &= ~(E1000_CTRL_LRST); + + e1000_config_collision_dist(hw); + + /* Check for a software override of the flow control settings, and setup + * the device accordingly. If auto-negotiation is enabled, then software + * will have to set the "PAUSE" bits to the correct value in the Tranmsit + * Config Word Register (TXCW) and re-start auto-negotiation. However, if + * auto-negotiation is disabled, then software will have to manually + * configure the two flow control enable bits in the CTRL register. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames, but + * not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames but we do + * not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + */ + switch (hw->fc) { + case e1000_fc_none: + /* Flow control is completely disabled by a software over-ride. */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); + break; + case e1000_fc_rx_pause: + /* RX Flow control is enabled and TX Flow control is disabled by a + * software over-ride. Since there really isn't a way to advertise + * that we are capable of RX Pause ONLY, we will advertise that we + * support both symmetric and asymmetric RX PAUSE. Later, we will + * disable the adapter's ability to send PAUSE frames. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + case e1000_fc_tx_pause: + /* TX Flow control is enabled, and RX Flow control is disabled, by a + * software over-ride. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); + break; + case e1000_fc_full: + /* Flow control (both RX and TX) is enabled by a software over-ride. */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + break; + } + + /* Since auto-negotiation is enabled, take the link out of reset (the link + * will be in reset, because we previously reset the chip). This will + * restart auto-negotiation. If auto-neogtiation is successful then the + * link-up status bit will be set and the flow control enable bits (RFCE + * and TFCE) will be set according to their negotiated value. + */ + DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); + + E1000_WRITE_REG(hw, TXCW, txcw); + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + hw->txcw = txcw; + mdelay(1); + + /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" + * indication in the Device Status Register. Time-out if a link isn't + * seen in 500 milliseconds seconds (Auto-negotiation should complete in + * less than 500 milliseconds even if the other end is doing it in SW). + */ + if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { + DEBUGOUT("Looking for Link\n"); + for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { + mdelay(10); + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_LU) + break; + } + if (i == (LINK_UP_TIMEOUT / 10)) { + /* AutoNeg failed to achieve a link, so we'll call + * e1000_check_for_link. This routine will force the link up if we + * detect a signal. This will allow us to communicate with + * non-autonegotiating link partners. + */ + DEBUGOUT("Never got a valid link from auto-neg!!!\n"); + hw->autoneg_failed = 1; + ret_val = e1000_check_for_link(nic); + if (ret_val < 0) { + DEBUGOUT("Error while checking for link\n"); + return ret_val; + } + hw->autoneg_failed = 0; + } else { + hw->autoneg_failed = 0; + DEBUGOUT("Valid Link Found\n"); + } + } else { + DEBUGOUT("No Signal Detected\n"); + return -E1000_ERR_NOLINK; + } + return 0; +} + +/****************************************************************************** +* Detects which PHY is present and the speed and duplex +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_setup_copper_link(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t ctrl; + int32_t ret_val; + uint16_t i; + uint16_t phy_data; + + DEBUGFUNC(); + + ctrl = E1000_READ_REG(hw, CTRL); + /* With 82543, we need to force speed and duplex on the MAC equal to what + * the PHY speed and duplex configuration is. In addition, we need to + * perform a hardware reset on the PHY to take it out of reset. + */ + if (hw->mac_type > e1000_82543) { + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, CTRL, ctrl); + } else { + ctrl |= + (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); + E1000_WRITE_REG(hw, CTRL, ctrl); + e1000_phy_hw_reset(hw); + } + + /* Make sure we have a valid PHY */ + ret_val = e1000_detect_gig_phy(hw); + if (ret_val < 0) { + DEBUGOUT("Error, did not detect valid phy.\n"); + return ret_val; + } + DEBUGOUT("Phy ID = %x \n", hw->phy_id); + + /* Enable CRS on TX. This must be set for half-duplex operation. */ + if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; + +#if 0 + /* Options: + * MDI/MDI-X = 0 (default) + * 0 - Auto for all speeds + * 1 - MDI mode + * 2 - MDI-X mode + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) + */ + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + switch (hw->mdix) { + case 1: + phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; + break; + case 2: + phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; + break; + case 3: + phy_data |= M88E1000_PSCR_AUTO_X_1000T; + break; + case 0: + default: + phy_data |= M88E1000_PSCR_AUTO_X_MODE; + break; + } +#else + phy_data |= M88E1000_PSCR_AUTO_X_MODE; +#endif + +#if 0 + /* Options: + * disable_polarity_correction = 0 (default) + * Automatic Correction for Reversed Cable Polarity + * 0 - Disabled + * 1 - Enabled + */ + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; + if (hw->disable_polarity_correction == 1) + phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; +#else + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; +#endif + if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + + /* Force TX_CLK in the Extended PHY Specific Control Register + * to 25MHz clock. + */ + if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + phy_data |= M88E1000_EPSCR_TX_CLK_25; + /* Configure Master and Slave downshift values */ + phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | + M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); + phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | + M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); + if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + + /* SW Reset the PHY so all changes take effect */ + ret_val = e1000_phy_reset(hw); + if (ret_val < 0) { + DEBUGOUT("Error Resetting the PHY\n"); + return ret_val; + } + + /* Options: + * autoneg = 1 (default) + * PHY will advertise value(s) parsed from + * autoneg_advertised and fc + * autoneg = 0 + * PHY will be set to 10H, 10F, 100H, or 100F + * depending on value parsed from forced_speed_duplex. + */ + + /* Is autoneg enabled? This is enabled by default or by software override. + * If so, call e1000_phy_setup_autoneg routine to parse the + * autoneg_advertised and fc options. If autoneg is NOT enabled, then the + * user should have provided a speed/duplex override. If so, then call + * e1000_phy_force_speed_duplex to parse and set this up. + */ + /* Perform some bounds checking on the hw->autoneg_advertised + * parameter. If this variable is zero, then set it to the default. + */ + hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; + + /* If autoneg_advertised is zero, we assume it was not defaulted + * by the calling code so we set to advertise full capability. + */ + if (hw->autoneg_advertised == 0) + hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; + + DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); + ret_val = e1000_phy_setup_autoneg(hw); + if (ret_val < 0) { + DEBUGOUT("Error Setting up Auto-Negotiation\n"); + return ret_val; + } + DEBUGOUT("Restarting Auto-Neg\n"); + + /* Restart auto-negotiation by setting the Auto Neg Enable bit and + * the Auto Neg Restart bit in the PHY control register. + */ + if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); + if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } +#if 0 + /* Does the user want to wait for Auto-Neg to complete here, or + * check at a later time (for example, callback routine). + */ + if (hw->wait_autoneg_complete) { + ret_val = e1000_wait_autoneg(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error while waiting for autoneg to complete\n"); + return ret_val; + } + } +#else + /* If we do not wait for autonegtation to complete I + * do not see a valid link status. + */ + ret_val = e1000_wait_autoneg(hw); + if (ret_val < 0) { + DEBUGOUT("Error while waiting for autoneg to complete\n"); + return ret_val; + } +#endif + + /* Check link status. Wait up to 100 microseconds for link to become + * valid. + */ + for (i = 0; i < 10; i++) { + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (phy_data & MII_SR_LINK_STATUS) { + /* We have link, so we need to finish the config process: + * 1) Set up the MAC to the current PHY speed/duplex + * if we are on 82543. If we + * are on newer silicon, we only need to configure + * collision distance in the Transmit Control Register. + * 2) Set up flow control on the MAC to that established with + * the link partner. + */ + if (hw->mac_type >= e1000_82544) { + e1000_config_collision_dist(hw); + } else { + ret_val = e1000_config_mac_to_phy(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error configuring MAC to PHY settings\n"); + return ret_val; + } + } + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val < 0) { + DEBUGOUT("Error Configuring Flow Control\n"); + return ret_val; + } + DEBUGOUT("Valid link established!!!\n"); + return 0; + } + udelay(10); + } + + DEBUGOUT("Unable to establish link!!!\n"); + return -E1000_ERR_NOLINK; +} + +/****************************************************************************** +* Configures PHY autoneg and flow control advertisement settings +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_phy_setup_autoneg(struct e1000_hw *hw) +{ + uint16_t mii_autoneg_adv_reg; + uint16_t mii_1000t_ctrl_reg; + + DEBUGFUNC(); + + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ + if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + /* Read the MII 1000Base-T Control Register (Address 9). */ + if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + /* Need to parse both autoneg_advertised and fc and set up + * the appropriate PHY registers. First we will parse for + * autoneg_advertised software override. Since we can advertise + * a plethora of combinations, we need to check each bit + * individually. + */ + + /* First we clear all the 10/100 mb speed bits in the Auto-Neg + * Advertisement Register (Address 4) and the 1000 mb speed bits in + * the 1000Base-T Control Register (Address 9). + */ + mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; + mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; + + DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); + + /* Do we want to advertise 10 Mb Half Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_10_HALF) { + DEBUGOUT("Advertise 10mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; + } + + /* Do we want to advertise 10 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_10_FULL) { + DEBUGOUT("Advertise 10mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; + } + + /* Do we want to advertise 100 Mb Half Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_100_HALF) { + DEBUGOUT("Advertise 100mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; + } + + /* Do we want to advertise 100 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_100_FULL) { + DEBUGOUT("Advertise 100mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; + } + + /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ + if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { + DEBUGOUT + ("Advertise 1000mb Half duplex requested, request denied!\n"); + } + + /* Do we want to advertise 1000 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { + DEBUGOUT("Advertise 1000mb Full duplex\n"); + mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; + } + + /* Check for a software override of the flow control settings, and + * setup the PHY advertisement registers accordingly. If + * auto-negotiation is enabled, then software will have to set the + * "PAUSE" bits to the correct value in the Auto-Negotiation + * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames + * but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * but we do not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + * other: No software override. The flow control configuration + * in the EEPROM is used. + */ + switch (hw->fc) { + case e1000_fc_none: /* 0 */ + /* Flow control (RX & TX) is completely disabled by a + * software over-ride. + */ + mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case e1000_fc_rx_pause: /* 1 */ + /* RX Flow control is enabled, and TX Flow control is + * disabled, by a software over-ride. + */ + /* Since there really isn't a way to advertise that we are + * capable of RX Pause ONLY, we will advertise that we + * support both symmetric and asymmetric RX PAUSE. Later + * (in e1000_config_fc_after_link_up) we will disable the + *hw's ability to send PAUSE frames. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case e1000_fc_tx_pause: /* 2 */ + /* TX Flow control is enabled, and RX Flow control is + * disabled, by a software over-ride. + */ + mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; + mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; + break; + case e1000_fc_full: /* 3 */ + /* Flow control (both RX and TX) is enabled by a software + * over-ride. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + } + + if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + + DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); + + if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + return 0; +} + +/****************************************************************************** +* Sets the collision distance in the Transmit Control register +* +* hw - Struct containing variables accessed by shared code +* +* Link should have been established previously. Reads the speed and duplex +* information from the Device Status register. +******************************************************************************/ +static void +e1000_config_collision_dist(struct e1000_hw *hw) +{ + uint32_t tctl; + + tctl = E1000_READ_REG(hw, TCTL); + + tctl &= ~E1000_TCTL_COLD; + tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; + + E1000_WRITE_REG(hw, TCTL, tctl); + E1000_WRITE_FLUSH(hw); +} + +/****************************************************************************** +* Sets MAC speed and duplex settings to reflect the those in the PHY +* +* hw - Struct containing variables accessed by shared code +* mii_reg - data to write to the MII control register +* +* The contents of the PHY register containing the needed information need to +* be passed in. +******************************************************************************/ +static int +e1000_config_mac_to_phy(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint16_t phy_data; + + DEBUGFUNC(); + + /* Read the Device Control Register and set the bits to Force Speed + * and Duplex. + */ + ctrl = E1000_READ_REG(hw, CTRL); + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); + + /* Set up duplex in the Device Control and Transmit Control + * registers depending on negotiated values. + */ + if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (phy_data & M88E1000_PSSR_DPLX) + ctrl |= E1000_CTRL_FD; + else + ctrl &= ~E1000_CTRL_FD; + + e1000_config_collision_dist(hw); + + /* Set up speed in the Device Control register depending on + * negotiated values. + */ + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) + ctrl |= E1000_CTRL_SPD_1000; + else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) + ctrl |= E1000_CTRL_SPD_100; + /* Write the configured values back to the Device Control Reg. */ + E1000_WRITE_REG(hw, CTRL, ctrl); + return 0; +} + +/****************************************************************************** + * Forces the MAC's flow control settings. + * + * hw - Struct containing variables accessed by shared code + * + * Sets the TFCE and RFCE bits in the device control register to reflect + * the adapter settings. TFCE and RFCE need to be explicitly set by + * software when a Copper PHY is used because autonegotiation is managed + * by the PHY rather than the MAC. Software must also configure these + * bits when link is forced on a fiber connection. + *****************************************************************************/ +static int +e1000_force_mac_fc(struct e1000_hw *hw) +{ + uint32_t ctrl; + + DEBUGFUNC(); + + /* Get the current configuration of the Device Control Register */ + ctrl = E1000_READ_REG(hw, CTRL); + + /* Because we didn't get link via the internal auto-negotiation + * mechanism (we either forced link or we got link via PHY + * auto-neg), we have to manually enable/disable transmit an + * receive flow control. + * + * The "Case" statement below enables/disable flow control + * according to the "hw->fc" parameter. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause + * frames but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * frames but we do not receive pause frames). + * 3: Both Rx and TX flow control (symmetric) is enabled. + * other: No other values should be possible at this point. + */ + + switch (hw->fc) { + case e1000_fc_none: + ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); + break; + case e1000_fc_rx_pause: + ctrl &= (~E1000_CTRL_TFCE); + ctrl |= E1000_CTRL_RFCE; + break; + case e1000_fc_tx_pause: + ctrl &= (~E1000_CTRL_RFCE); + ctrl |= E1000_CTRL_TFCE; + break; + case e1000_fc_full: + ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + } + + /* Disable TX Flow Control for 82542 (rev 2.0) */ + if (hw->mac_type == e1000_82542_rev2_0) + ctrl &= (~E1000_CTRL_TFCE); + + E1000_WRITE_REG(hw, CTRL, ctrl); + return 0; +} + +/****************************************************************************** + * Configures flow control settings after link is established + * + * hw - Struct containing variables accessed by shared code + * + * Should be called immediately after a valid link has been established. + * Forces MAC flow control settings if link was forced. When in MII/GMII mode + * and autonegotiation is enabled, the MAC flow control settings will be set + * based on the flow control negotiated by the PHY. In TBI mode, the TFCE + * and RFCE bits will be automaticaly set to the negotiated flow control mode. + *****************************************************************************/ +static int +e1000_config_fc_after_link_up(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t mii_status_reg; + uint16_t mii_nway_adv_reg; + uint16_t mii_nway_lp_ability_reg; + uint16_t speed; + uint16_t duplex; + + DEBUGFUNC(); + + /* Check for the case where we have fiber media and auto-neg failed + * so we had to force link. In this case, we need to force the + * configuration of the MAC to match the "fc" parameter. + */ + if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) { + ret_val = e1000_force_mac_fc(hw); + if (ret_val < 0) { + DEBUGOUT("Error forcing flow control settings\n"); + return ret_val; + } + } + + /* Check for the case where we have copper media and auto-neg is + * enabled. In this case, we need to check and see if Auto-Neg + * has completed, and if so, how the PHY and link partner has + * flow control configured. + */ + if (hw->media_type == e1000_media_type_copper) { + /* Read the MII Status Register and check to see if AutoNeg + * has completed. We read this twice because this reg has + * some "sticky" (latched) bits. + */ + if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { + DEBUGOUT("PHY Read Error \n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { + DEBUGOUT("PHY Read Error \n"); + return -E1000_ERR_PHY; + } + + if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { + /* The AutoNeg process has completed, so we now need to + * read both the Auto Negotiation Advertisement Register + * (Address 4) and the Auto_Negotiation Base Page Ability + * Register (Address 5) to determine how flow control was + * negotiated. + */ + if (e1000_read_phy_reg + (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg + (hw, PHY_LP_ABILITY, + &mii_nway_lp_ability_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + /* Two bits in the Auto Negotiation Advertisement Register + * (Address 4) and two bits in the Auto Negotiation Base + * Page Ability Register (Address 5) determine flow control + * for both the PHY and the link partner. The following + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, + * 1999, describes these PAUSE resolution bits and how flow + * control is determined based upon these settings. + * NOTE: DC = Don't Care + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution + *-------|---------|-------|---------|-------------------- + * 0 | 0 | DC | DC | e1000_fc_none + * 0 | 1 | 0 | DC | e1000_fc_none + * 0 | 1 | 1 | 0 | e1000_fc_none + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * 1 | 0 | 0 | DC | e1000_fc_none + * 1 | DC | 1 | DC | e1000_fc_full + * 1 | 1 | 0 | 0 | e1000_fc_none + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + */ + /* Are both PAUSE bits set to 1? If so, this implies + * Symmetric Flow Control is enabled at both ends. The + * ASM_DIR bits are irrelevant per the spec. + * + * For Symmetric Flow Control: + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | DC | 1 | DC | e1000_fc_full + * + */ + if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { + /* Now we need to check if the user selected RX ONLY + * of pause frames. In this case, we had to advertise + * FULL flow control because we could not advertise RX + * ONLY. Hence, we must now check to see if we need to + * turn OFF the TRANSMISSION of PAUSE frames. + */ + if (hw->original_fc == e1000_fc_full) { + hw->fc = e1000_fc_full; + DEBUGOUT("Flow Control = FULL.\r\n"); + } else { + hw->fc = e1000_fc_rx_pause; + DEBUGOUT + ("Flow Control = RX PAUSE frames only.\r\n"); + } + } + /* For receiving PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * + */ + else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) + { + hw->fc = e1000_fc_tx_pause; + DEBUGOUT + ("Flow Control = TX PAUSE frames only.\r\n"); + } + /* For transmitting PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + */ + else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) + { + hw->fc = e1000_fc_rx_pause; + DEBUGOUT + ("Flow Control = RX PAUSE frames only.\r\n"); + } + /* Per the IEEE spec, at this point flow control should be + * disabled. However, we want to consider that we could + * be connected to a legacy switch that doesn't advertise + * desired flow control, but can be forced on the link + * partner. So if we advertised no flow control, that is + * what we will resolve to. If we advertised some kind of + * receive capability (Rx Pause Only or Full Flow Control) + * and the link partner advertised none, we will configure + * ourselves to enable Rx Flow Control only. We can do + * this safely for two reasons: If the link partner really + * didn't want flow control enabled, and we enable Rx, no + * harm done since we won't be receiving any PAUSE frames + * anyway. If the intent on the link partner was to have + * flow control enabled, then by us enabling RX only, we + * can at least receive pause frames and process them. + * This is a good idea because in most cases, since we are + * predominantly a server NIC, more times than not we will + * be asked to delay transmission of packets than asking + * our link partner to pause transmission of frames. + */ + else if (hw->original_fc == e1000_fc_none || + hw->original_fc == e1000_fc_tx_pause) { + hw->fc = e1000_fc_none; + DEBUGOUT("Flow Control = NONE.\r\n"); + } else { + hw->fc = e1000_fc_rx_pause; + DEBUGOUT + ("Flow Control = RX PAUSE frames only.\r\n"); + } + + /* Now we need to do one last check... If we auto- + * negotiated to HALF DUPLEX, flow control should not be + * enabled per IEEE 802.3 spec. + */ + e1000_get_speed_and_duplex(hw, &speed, &duplex); + + if (duplex == HALF_DUPLEX) + hw->fc = e1000_fc_none; + + /* Now we call a subroutine to actually force the MAC + * controller to use the correct flow control settings. + */ + ret_val = e1000_force_mac_fc(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error forcing flow control settings\n"); + return ret_val; + } + } else { + DEBUGOUT + ("Copper PHY and Auto Neg has not completed.\r\n"); + } + } + return 0; +} + +/****************************************************************************** + * Checks to see if the link status of the hardware has changed. + * + * hw - Struct containing variables accessed by shared code + * + * Called by any function that needs to check the link status of the adapter. + *****************************************************************************/ +static int +e1000_check_for_link(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t rxcw; + uint32_t ctrl; + uint32_t status; + uint32_t rctl; + uint32_t signal; + int32_t ret_val; + uint16_t phy_data; + uint16_t lp_capability; + + DEBUGFUNC(); + + /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be + * set when the optics detect a signal. On older adapters, it will be + * cleared when there is a signal + */ + ctrl = E1000_READ_REG(hw, CTRL); + if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) + signal = E1000_CTRL_SWDPIN1; + else + signal = 0; + + status = E1000_READ_REG(hw, STATUS); + rxcw = E1000_READ_REG(hw, RXCW); + DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); + + /* If we have a copper PHY then we only want to go out to the PHY + * registers to see if Auto-Neg has completed and/or if our link + * status has changed. The get_link_status flag will be set if we + * receive a Link Status Change interrupt or we have Rx Sequence + * Errors. + */ + if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { + /* First we want to see if the MII Status Register reports + * link. If so, then we want to get the current speed/duplex + * of the PHY. + * Read the register twice since the link bit is sticky. + */ + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + if (phy_data & MII_SR_LINK_STATUS) { + hw->get_link_status = FALSE; + } else { + /* No link detected */ + return -E1000_ERR_NOLINK; + } + + /* We have a M88E1000 PHY and Auto-Neg is enabled. If we + * have Si on board that is 82544 or newer, Auto + * Speed Detection takes care of MAC speed/duplex + * configuration. So we only need to configure Collision + * Distance in the MAC. Otherwise, we need to force + * speed/duplex on the MAC to the current PHY speed/duplex + * settings. + */ + if (hw->mac_type >= e1000_82544) + e1000_config_collision_dist(hw); + else { + ret_val = e1000_config_mac_to_phy(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error configuring MAC to PHY settings\n"); + return ret_val; + } + } + + /* Configure Flow Control now that Auto-Neg has completed. First, we + * need to restore the desired flow control settings because we may + * have had to re-autoneg with a different link partner. + */ + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val < 0) { + DEBUGOUT("Error configuring flow control\n"); + return ret_val; + } + + /* At this point we know that we are on copper and we have + * auto-negotiated link. These are conditions for checking the link + * parter capability register. We use the link partner capability to + * determine if TBI Compatibility needs to be turned on or off. If + * the link partner advertises any speed in addition to Gigabit, then + * we assume that they are GMII-based, and TBI compatibility is not + * needed. If no other speeds are advertised, we assume the link + * partner is TBI-based, and we turn on TBI Compatibility. + */ + if (hw->tbi_compatibility_en) { + if (e1000_read_phy_reg + (hw, PHY_LP_ABILITY, &lp_capability) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | + NWAY_LPAR_10T_FD_CAPS | + NWAY_LPAR_100TX_HD_CAPS | + NWAY_LPAR_100TX_FD_CAPS | + NWAY_LPAR_100T4_CAPS)) { + /* If our link partner advertises anything in addition to + * gigabit, we do not need to enable TBI compatibility. + */ + if (hw->tbi_compatibility_on) { + /* If we previously were in the mode, turn it off. */ + rctl = E1000_READ_REG(hw, RCTL); + rctl &= ~E1000_RCTL_SBP; + E1000_WRITE_REG(hw, RCTL, rctl); + hw->tbi_compatibility_on = FALSE; + } + } else { + /* If TBI compatibility is was previously off, turn it on. For + * compatibility with a TBI link partner, we will store bad + * packets. Some frames have an additional byte on the end and + * will look like CRC errors to to the hardware. + */ + if (!hw->tbi_compatibility_on) { + hw->tbi_compatibility_on = TRUE; + rctl = E1000_READ_REG(hw, RCTL); + rctl |= E1000_RCTL_SBP; + E1000_WRITE_REG(hw, RCTL, rctl); + } + } + } + } + /* If we don't have link (auto-negotiation failed or link partner cannot + * auto-negotiate), the cable is plugged in (we have signal), and our + * link partner is not trying to auto-negotiate with us (we are receiving + * idles or data), we need to force link up. We also need to give + * auto-negotiation time to complete, in case the cable was just plugged + * in. The autoneg_failed flag does this. + */ + else if ((hw->media_type == e1000_media_type_fiber) && + (!(status & E1000_STATUS_LU)) && + ((ctrl & E1000_CTRL_SWDPIN1) == signal) && + (!(rxcw & E1000_RXCW_C))) { + if (hw->autoneg_failed == 0) { + hw->autoneg_failed = 1; + return 0; + } + DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); + + /* Disable auto-negotiation in the TXCW register */ + E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); + + /* Force link-up and also force full-duplex. */ + ctrl = E1000_READ_REG(hw, CTRL); + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); + E1000_WRITE_REG(hw, CTRL, ctrl); + + /* Configure Flow Control after forcing link up. */ + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val < 0) { + DEBUGOUT("Error configuring flow control\n"); + return ret_val; + } + } + /* If we are forcing link and we are receiving /C/ ordered sets, re-enable + * auto-negotiation in the TXCW register and disable forced link in the + * Device Control register in an attempt to auto-negotiate with our link + * partner. + */ + else if ((hw->media_type == e1000_media_type_fiber) && + (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { + DEBUGOUT + ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); + E1000_WRITE_REG(hw, TXCW, hw->txcw); + E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); + } + return 0; +} + +/****************************************************************************** + * Detects the current speed and duplex settings of the hardware. + * + * hw - Struct containing variables accessed by shared code + * speed - Speed of the connection + * duplex - Duplex setting of the connection + *****************************************************************************/ +static void +e1000_get_speed_and_duplex(struct e1000_hw *hw, + uint16_t * speed, uint16_t * duplex) +{ + uint32_t status; + + DEBUGFUNC(); + + if (hw->mac_type >= e1000_82543) { + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_SPEED_1000) { + *speed = SPEED_1000; + DEBUGOUT("1000 Mbs, "); + } else if (status & E1000_STATUS_SPEED_100) { + *speed = SPEED_100; + DEBUGOUT("100 Mbs, "); + } else { + *speed = SPEED_10; + DEBUGOUT("10 Mbs, "); + } + + if (status & E1000_STATUS_FD) { + *duplex = FULL_DUPLEX; + DEBUGOUT("Full Duplex\r\n"); + } else { + *duplex = HALF_DUPLEX; + DEBUGOUT(" Half Duplex\r\n"); + } + } else { + DEBUGOUT("1000 Mbs, Full Duplex\r\n"); + *speed = SPEED_1000; + *duplex = FULL_DUPLEX; + } +} + +/****************************************************************************** +* Blocks until autoneg completes or times out (~4.5 seconds) +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_wait_autoneg(struct e1000_hw *hw) +{ + uint16_t i; + uint16_t phy_data; + + DEBUGFUNC(); + DEBUGOUT("Waiting for Auto-Neg to complete.\n"); + + /* We will wait for autoneg to complete or 4.5 seconds to expire. */ + for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { + /* Read the MII Status Register and wait for Auto-Neg + * Complete bit to be set. + */ + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (phy_data & MII_SR_AUTONEG_COMPLETE) { + DEBUGOUT("Auto-Neg complete.\n"); + return 0; + } + mdelay(100); + } + DEBUGOUT("Auto-Neg timedout.\n"); + return -E1000_ERR_TIMEOUT; +} + +/****************************************************************************** +* Raises the Management Data Clock +* +* hw - Struct containing variables accessed by shared code +* ctrl - Device control register's current value +******************************************************************************/ +static void +e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) +{ + /* Raise the clock input to the Management Data Clock (by setting the MDC + * bit), and then delay 2 microseconds. + */ + E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + udelay(2); +} + +/****************************************************************************** +* Lowers the Management Data Clock +* +* hw - Struct containing variables accessed by shared code +* ctrl - Device control register's current value +******************************************************************************/ +static void +e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) +{ + /* Lower the clock input to the Management Data Clock (by clearing the MDC + * bit), and then delay 2 microseconds. + */ + E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + udelay(2); +} + +/****************************************************************************** +* Shifts data bits out to the PHY +* +* hw - Struct containing variables accessed by shared code +* data - Data to send out to the PHY +* count - Number of bits to shift out +* +* Bits are shifted out in MSB to LSB order. +******************************************************************************/ +static void +e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) +{ + uint32_t ctrl; + uint32_t mask; + + /* We need to shift "count" number of bits out to the PHY. So, the value + * in the "data" parameter will be shifted out to the PHY one bit at a + * time. In order to do this, "data" must be broken down into bits. + */ + mask = 0x01; + mask <<= (count - 1); + + ctrl = E1000_READ_REG(hw, CTRL); + + /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ + ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); + + while (mask) { + /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and + * then raising and lowering the Management Data Clock. A "0" is + * shifted out to the PHY by setting the MDIO bit to "0" and then + * raising and lowering the clock. + */ + if (data & mask) + ctrl |= E1000_CTRL_MDIO; + else + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + udelay(2); + + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + mask = mask >> 1; + } +} + +/****************************************************************************** +* Shifts data bits in from the PHY +* +* hw - Struct containing variables accessed by shared code +* +* Bits are shifted in in MSB to LSB order. +******************************************************************************/ +static uint16_t +e1000_shift_in_mdi_bits(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint16_t data = 0; + uint8_t i; + + /* In order to read a register from the PHY, we need to shift in a total + * of 18 bits from the PHY. The first two bit (turnaround) times are used + * to avoid contention on the MDIO pin when a read operation is performed. + * These two bits are ignored by us and thrown away. Bits are "shifted in" + * by raising the input to the Management Data Clock (setting the MDC bit), + * and then reading the value of the MDIO bit. + */ + ctrl = E1000_READ_REG(hw, CTRL); + + /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ + ctrl &= ~E1000_CTRL_MDIO_DIR; + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + /* Raise and Lower the clock before reading in the data. This accounts for + * the turnaround bits. The first clock occurred when we clocked out the + * last bit of the Register Address. + */ + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + for (data = 0, i = 0; i < 16; i++) { + data = data << 1; + e1000_raise_mdi_clk(hw, &ctrl); + ctrl = E1000_READ_REG(hw, CTRL); + /* Check to see if we shifted in a "1". */ + if (ctrl & E1000_CTRL_MDIO) + data |= 1; + e1000_lower_mdi_clk(hw, &ctrl); + } + + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + return data; +} + +/***************************************************************************** +* Reads the value from a PHY register +* +* hw - Struct containing variables accessed by shared code +* reg_addr - address of the PHY register to read +******************************************************************************/ +static int +e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) +{ + uint32_t i; + uint32_t mdic = 0; + const uint32_t phy_addr = 1; + + if (reg_addr > MAX_PHY_REG_ADDRESS) { + DEBUGOUT("PHY Address %d is out of range\n", reg_addr); + return -E1000_ERR_PARAM; + } + + if (hw->mac_type > e1000_82543) { + /* Set up Op-code, Phy Address, and register address in the MDI + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ + mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | + (phy_addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_READ)); + + E1000_WRITE_REG(hw, MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < 64; i++) { + udelay(10); + mdic = E1000_READ_REG(hw, MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Read did not complete\n"); + return -E1000_ERR_PHY; + } + if (mdic & E1000_MDIC_ERROR) { + DEBUGOUT("MDI Error\n"); + return -E1000_ERR_PHY; + } + *phy_data = (uint16_t) mdic; + } else { + /* We must first send a preamble through the MDIO pin to signal the + * beginning of an MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* Now combine the next few fields that are required for a read + * operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine five different times. The format of + * a MII read instruction consists of a shift out of 14 bits and is + * defined as follows: + * + * followed by a shift in of 18 bits. This first two bits shifted in + * are TurnAround bits used to avoid contention on the MDIO pin when a + * READ operation is performed. These two bits are thrown away + * followed by a shift in of 16 bits which contains the desired data. + */ + mdic = ((reg_addr) | (phy_addr << 5) | + (PHY_OP_READ << 10) | (PHY_SOF << 12)); + + e1000_shift_out_mdi_bits(hw, mdic, 14); + + /* Now that we've shifted out the read command to the MII, we need to + * "shift in" the 16-bit value (18 total bits) of the requested PHY + * register address. + */ + *phy_data = e1000_shift_in_mdi_bits(hw); + } + return 0; +} + +/****************************************************************************** +* Writes a value to a PHY register +* +* hw - Struct containing variables accessed by shared code +* reg_addr - address of the PHY register to write +* data - data to write to the PHY +******************************************************************************/ +static int +e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) +{ + uint32_t i; + uint32_t mdic = 0; + const uint32_t phy_addr = 1; + + if (reg_addr > MAX_PHY_REG_ADDRESS) { + DEBUGOUT("PHY Address %d is out of range\n", reg_addr); + return -E1000_ERR_PARAM; + } + + if (hw->mac_type > e1000_82543) { + /* Set up Op-code, Phy Address, register address, and data intended + * for the PHY register in the MDI Control register. The MAC will take + * care of interfacing with the PHY to send the desired data. + */ + mdic = (((uint32_t) phy_data) | + (reg_addr << E1000_MDIC_REG_SHIFT) | + (phy_addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_WRITE)); + + E1000_WRITE_REG(hw, MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < 64; i++) { + udelay(10); + mdic = E1000_READ_REG(hw, MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Write did not complete\n"); + return -E1000_ERR_PHY; + } + } else { + /* We'll need to use the SW defined pins to shift the write command + * out to the PHY. We first send a preamble to the PHY to signal the + * beginning of the MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* Now combine the remaining required fields that will indicate a + * write operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine for each field in the command. The + * format of a MII write instruction is as follows: + * . + */ + mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | + (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); + mdic <<= 16; + mdic |= (uint32_t) phy_data; + + e1000_shift_out_mdi_bits(hw, mdic, 32); + } + return 0; +} + +/****************************************************************************** +* Returns the PHY to the power-on reset state +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static void +e1000_phy_hw_reset(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint32_t ctrl_ext; + + DEBUGFUNC(); + + DEBUGOUT("Resetting Phy...\n"); + + if (hw->mac_type > e1000_82543) { + /* Read the device control register and assert the E1000_CTRL_PHY_RST + * bit. Then, take it out of reset. + */ + ctrl = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); + E1000_WRITE_FLUSH(hw); + mdelay(10); + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + } else { + /* Read the Extended Device Control Register, assert the PHY_RESET_DIR + * bit to put the PHY into reset. Then, take it out of reset. + */ + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; + ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + mdelay(10); + ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + } + udelay(150); +} + +/****************************************************************************** +* Resets the PHY +* +* hw - Struct containing variables accessed by shared code +* +* Sets bit 15 of the MII Control regiser +******************************************************************************/ +static int +e1000_phy_reset(struct e1000_hw *hw) +{ + uint16_t phy_data; + + DEBUGFUNC(); + + if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + phy_data |= MII_CR_RESET; + if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + udelay(1); + return 0; +} + +/****************************************************************************** +* Probes the expected PHY address for known PHY IDs +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_detect_gig_phy(struct e1000_hw *hw) +{ + uint16_t phy_id_high, phy_id_low; + int match = FALSE; + + DEBUGFUNC(); + + /* Read the PHY ID Registers to identify which PHY is onboard. */ + if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + hw->phy_id = (uint32_t) (phy_id_high << 16); + udelay(2); + if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); + + switch (hw->mac_type) { + case e1000_82543: + if (hw->phy_id == M88E1000_E_PHY_ID) + match = TRUE; + break; + case e1000_82544: + if (hw->phy_id == M88E1000_I_PHY_ID) + match = TRUE; + break; + case e1000_82540: + case e1000_82545: + case e1000_82546: + if (hw->phy_id == M88E1011_I_PHY_ID) + match = TRUE; + break; + default: + DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); + return -E1000_ERR_CONFIG; + } + if (match) { + DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); + return 0; + } + DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); + return -E1000_ERR_PHY; +} + +/** + * e1000_sw_init - Initialize general software structures (struct e1000_adapter) + * + * e1000_sw_init initializes the Adapter private data structure. + * Fields are initialized based on PCI device information and + * OS network device settings (MTU size). + **/ + +static int +e1000_sw_init(struct eth_device *nic, int cardnum) +{ + struct e1000_hw *hw = (typeof(hw)) nic->priv; + int result; + + /* PCI config space info */ + pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); + pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); + pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, + &hw->subsystem_vendor_id); + pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); + + pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); + pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); + + /* identify the MAC */ + result = e1000_set_mac_type(hw); + if (result) { + E1000_ERR("Unknown MAC Type\n"); + return result; + } + + /* lan a vs. lan b settings */ + if (hw->mac_type == e1000_82546) + /*this also works w/ multiple 82546 cards */ + /*but not if they're intermingled /w other e1000s */ + hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; + else + hw->lan_loc = e1000_lan_a; + + /* flow control settings */ + hw->fc_high_water = E1000_FC_HIGH_THRESH; + hw->fc_low_water = E1000_FC_LOW_THRESH; + hw->fc_pause_time = E1000_FC_PAUSE_TIME; + hw->fc_send_xon = 1; + + /* Media type - copper or fiber */ + + if (hw->mac_type >= e1000_82543) { + uint32_t status = E1000_READ_REG(hw, STATUS); + + if (status & E1000_STATUS_TBIMODE) { + DEBUGOUT("fiber interface\n"); + hw->media_type = e1000_media_type_fiber; + } else { + DEBUGOUT("copper interface\n"); + hw->media_type = e1000_media_type_copper; + } + } else { + hw->media_type = e1000_media_type_fiber; + } + + if (hw->mac_type < e1000_82543) + hw->report_tx_early = 0; + else + hw->report_tx_early = 1; + + hw->tbi_compatibility_en = TRUE; +#if 0 + hw->wait_autoneg_complete = FALSE; + hw->adaptive_ifs = TRUE; + + /* Copper options */ + if (hw->media_type == e1000_media_type_copper) { + hw->mdix = AUTO_ALL_MODES; + hw->disable_polarity_correction = FALSE; + } +#endif + return E1000_SUCCESS; +} + +void +fill_rx(struct e1000_hw *hw) +{ + struct e1000_rx_desc *rd; + + rx_last = rx_tail; + rd = rx_base + rx_tail; + rx_tail = (rx_tail + 1) % 8; + memset(rd, 0, 16); + rd->buffer_addr = cpu_to_le64((u32) & packet); + E1000_WRITE_REG(hw, RDT, rx_tail); +} + +/** + * e1000_configure_tx - Configure 8254x Transmit Unit after Reset + * @adapter: board private structure + * + * Configure the Tx unit of the MAC after a reset. + **/ + +static void +e1000_configure_tx(struct e1000_hw *hw) +{ + unsigned long ptr; + unsigned long tctl; + unsigned long tipg; + + ptr = (u32) tx_pool; + if (ptr & 0xf) + ptr = (ptr + 0x10) & (~0xf); + + tx_base = (typeof(tx_base)) ptr; + + E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); + E1000_WRITE_REG(hw, TDBAH, 0); + + E1000_WRITE_REG(hw, TDLEN, 128); + + /* Setup the HW Tx Head and Tail descriptor pointers */ + E1000_WRITE_REG(hw, TDH, 0); + E1000_WRITE_REG(hw, TDT, 0); + tx_tail = 0; + + /* Set the default values for the Tx Inter Packet Gap timer */ + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + tipg = DEFAULT_82542_TIPG_IPGT; + tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; + tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; + break; + default: + if (hw->media_type == e1000_media_type_fiber) + tipg = DEFAULT_82543_TIPG_IPGT_FIBER; + else + tipg = DEFAULT_82543_TIPG_IPGT_COPPER; + tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; + tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; + } + E1000_WRITE_REG(hw, TIPG, tipg); +#if 0 + /* Set the Tx Interrupt Delay register */ + E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay); + if (hw->mac_type >= e1000_82540) + E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay); +#endif + /* Program the Transmit Control Register */ + tctl = E1000_READ_REG(hw, TCTL); + tctl &= ~E1000_TCTL_CT; + tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | + (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); + E1000_WRITE_REG(hw, TCTL, tctl); + + e1000_config_collision_dist(hw); +#if 0 + /* Setup Transmit Descriptor Settings for this adapter */ + adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE; + + if (adapter->hw.report_tx_early == 1) + adapter->txd_cmd |= E1000_TXD_CMD_RS; + else + adapter->txd_cmd |= E1000_TXD_CMD_RPS; +#endif +} + +/** + * e1000_setup_rctl - configure the receive control register + * @adapter: Board private structure + **/ +static void +e1000_setup_rctl(struct e1000_hw *hw) +{ + uint32_t rctl; + + rctl = E1000_READ_REG(hw, RCTL); + + rctl &= ~(3 << E1000_RCTL_MO_SHIFT); + + rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* | + (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ + + if (hw->tbi_compatibility_on == 1) + rctl |= E1000_RCTL_SBP; + else + rctl &= ~E1000_RCTL_SBP; + + rctl &= ~(E1000_RCTL_SZ_4096); +#if 0 + switch (adapter->rx_buffer_len) { + case E1000_RXBUFFER_2048: + default: +#endif + rctl |= E1000_RCTL_SZ_2048; + rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); +#if 0 + break; + case E1000_RXBUFFER_4096: + rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; + break; + case E1000_RXBUFFER_8192: + rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; + break; + case E1000_RXBUFFER_16384: + rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; + break; + } +#endif + E1000_WRITE_REG(hw, RCTL, rctl); +} + +/** + * e1000_configure_rx - Configure 8254x Receive Unit after Reset + * @adapter: board private structure + * + * Configure the Rx unit of the MAC after a reset. + **/ +static void +e1000_configure_rx(struct e1000_hw *hw) +{ + unsigned long ptr; + unsigned long rctl; +#if 0 + unsigned long rxcsum; +#endif + rx_tail = 0; + /* make sure receives are disabled while setting up the descriptors */ + rctl = E1000_READ_REG(hw, RCTL); + E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); +#if 0 + /* set the Receive Delay Timer Register */ + + E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay); +#endif + if (hw->mac_type >= e1000_82540) { +#if 0 + E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay); +#endif + /* Set the interrupt throttling rate. Value is calculated + * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ +#define MAX_INTS_PER_SEC 8000 +#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) + E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); + } + + /* Setup the Base and Length of the Rx Descriptor Ring */ + ptr = (u32) rx_pool; + if (ptr & 0xf) + ptr = (ptr + 0x10) & (~0xf); + rx_base = (typeof(rx_base)) ptr; + E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); + E1000_WRITE_REG(hw, RDBAH, 0); + + E1000_WRITE_REG(hw, RDLEN, 128); + + /* Setup the HW Rx Head and Tail Descriptor Pointers */ + E1000_WRITE_REG(hw, RDH, 0); + E1000_WRITE_REG(hw, RDT, 0); +#if 0 + /* Enable 82543 Receive Checksum Offload for TCP and UDP */ + if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) { + rxcsum = E1000_READ_REG(hw, RXCSUM); + rxcsum |= E1000_RXCSUM_TUOFL; + E1000_WRITE_REG(hw, RXCSUM, rxcsum); + } +#endif + /* Enable Receives */ + + E1000_WRITE_REG(hw, RCTL, rctl); + fill_rx(hw); +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int +e1000_poll(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + struct e1000_rx_desc *rd; + /* return true if there's an ethernet packet ready to read */ + rd = rx_base + rx_last; + if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) + return 0; + /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ + NetReceive((uchar *)packet, le32_to_cpu(rd->length)); + fill_rx(hw); + return 1; +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static int +e1000_transmit(struct eth_device *nic, volatile void *packet, int length) +{ + struct e1000_hw *hw = nic->priv; + struct e1000_tx_desc *txp; + int i = 0; + + txp = tx_base + tx_tail; + tx_tail = (tx_tail + 1) % 8; + + txp->buffer_addr = cpu_to_le64(virt_to_bus(packet)); + txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | + E1000_TXD_CMD_IFCS | length); + txp->upper.data = 0; + E1000_WRITE_REG(hw, TDT, tx_tail); + + while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { + if (i++ > TOUT_LOOP) { + DEBUGOUT("e1000: tx timeout\n"); + return 0; + } + udelay(10); /* give the nic a chance to write to the register */ + } + return 1; +} + +/*reset function*/ +static inline int +e1000_reset(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + + e1000_reset_hw(hw); + if (hw->mac_type >= e1000_82544) { + E1000_WRITE_REG(hw, WUC, 0); + } + return e1000_init_hw(nic); +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void +e1000_disable(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + + /* Turn off the ethernet interface */ + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_REG(hw, TCTL, 0); + + /* Clear the transmit ring */ + E1000_WRITE_REG(hw, TDH, 0); + E1000_WRITE_REG(hw, TDT, 0); + + /* Clear the receive ring */ + E1000_WRITE_REG(hw, RDH, 0); + E1000_WRITE_REG(hw, RDT, 0); + + /* put the card in its initial state */ +#if 0 + E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); +#endif + mdelay(10); + +} + +/************************************************************************** +INIT - set up ethernet interface(s) +***************************************************************************/ +static int +e1000_init(struct eth_device *nic, bd_t * bis) +{ + struct e1000_hw *hw = nic->priv; + int ret_val = 0; + + ret_val = e1000_reset(nic); + if (ret_val < 0) { + if ((ret_val == -E1000_ERR_NOLINK) || + (ret_val == -E1000_ERR_TIMEOUT)) { + E1000_ERR("Valid Link not detected\n"); + } else { + E1000_ERR("Hardware Initialization Failed\n"); + } + return 0; + } + e1000_configure_tx(hw); + e1000_setup_rctl(hw); + e1000_configure_rx(hw); + return 1; +} + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +You should omit the last argument struct pci_device * for a non-PCI NIC +***************************************************************************/ +int +e1000_initialize(bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *nic = NULL; + struct e1000_hw *hw = NULL; + u32 iobase; + int idx = 0; + u32 PciCommandWord; + + while (1) { /* Find PCI device(s) */ + if ((devno = pci_find_devices(supported, idx++)) < 0) { + break; + } + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */ + DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase); + + pci_write_config_dword(devno, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + /* Check if I/O accesses and Bus Mastering are enabled. */ + pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord); + if (!(PciCommandWord & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEM access.\n"); + continue; + } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + nic = (struct eth_device *) malloc(sizeof (*nic)); + hw = (struct e1000_hw *) malloc(sizeof (*hw)); + hw->pdev = devno; + nic->priv = hw; + nic->iobase = bus_to_phys(devno, iobase); + + sprintf(nic->name, "e1000#%d", card_number); + + /* Are these variables needed? */ +#if 0 + hw->fc = e1000_fc_none; + hw->original_fc = e1000_fc_none; +#else + hw->fc = e1000_fc_default; + hw->original_fc = e1000_fc_default; +#endif + hw->autoneg_failed = 0; + hw->get_link_status = TRUE; + hw->hw_addr = (typeof(hw->hw_addr)) iobase; + hw->mac_type = e1000_undefined; + + /* MAC and Phy settings */ + if (e1000_sw_init(nic, card_number) < 0) { + free(hw); + free(nic); + return 0; + } +#ifndef CONFIG_AP1000 + if (e1000_validate_eeprom_checksum(nic) < 0) { + printf("The EEPROM Checksum Is Not Valid\n"); + free(hw); + free(nic); + return 0; + } +#endif + e1000_read_mac_addr(nic); + + E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); + + printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n", + nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], + nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); + + nic->init = e1000_init; + nic->recv = e1000_poll; + nic->send = e1000_transmit; + nic->halt = e1000_disable; + + eth_register(nic); + + card_number++; + } + return 1; +} + +#endif diff --git a/drivers/e1000.h b/drivers/e1000.h new file mode 100644 index 0000000..0fbdc90 --- /dev/null +++ b/drivers/e1000.h @@ -0,0 +1,1758 @@ +/******************************************************************************* + + + Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program; if not, write to the Free Software Foundation, Inc., 59 + Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + The full GNU General Public License is included in this distribution in the + file called LICENSE. + + Contact Information: + Linux NICS + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +*******************************************************************************/ + +/* e1000_hw.h + * Structures, enums, and macros for the MAC + */ + +#ifndef _E1000_HW_H_ +#define _E1000_HW_H_ + +#include +#include +#include +#include +#include + +#define E1000_ERR(args...) printf("e1000: " args) + +#ifdef E1000_DEBUG +#define E1000_DBG(args...) printf("e1000: " args) +#define DEBUGOUT(fmt,args...) printf(fmt ,##args) +#define DEBUGFUNC() printf("%s\n", __FUNCTION__); +#else +#define E1000_DBG(args...) +#define DEBUGFUNC() +#define DEBUGOUT(fmt,args...) +#endif + +/* Forward declarations of structures used by the shared code */ +struct e1000_hw; +struct e1000_hw_stats; + +typedef enum { + FALSE = 0, + TRUE = 1 +} boolean_t; + +/* Enumerated types specific to the e1000 hardware */ +/* Media Access Controlers */ +typedef enum { + e1000_undefined = 0, + e1000_82542_rev2_0, + e1000_82542_rev2_1, + e1000_82543, + e1000_82544, + e1000_82540, + e1000_82545, + e1000_82546, + e1000_num_macs +} e1000_mac_type; + +/* Media Types */ +typedef enum { + e1000_media_type_copper = 0, + e1000_media_type_fiber = 1, + e1000_num_media_types +} e1000_media_type; + +typedef enum { + e1000_10_half = 0, + e1000_10_full = 1, + e1000_100_half = 2, + e1000_100_full = 3 +} e1000_speed_duplex_type; + +typedef enum { + e1000_lan_a = 0, + e1000_lan_b = 1 +} e1000_lan_loc; + +/* Flow Control Settings */ +typedef enum { + e1000_fc_none = 0, + e1000_fc_rx_pause = 1, + e1000_fc_tx_pause = 2, + e1000_fc_full = 3, + e1000_fc_default = 0xFF +} e1000_fc_type; + +/* PCI bus types */ +typedef enum { + e1000_bus_type_unknown = 0, + e1000_bus_type_pci, + e1000_bus_type_pcix +} e1000_bus_type; + +/* PCI bus speeds */ +typedef enum { + e1000_bus_speed_unknown = 0, + e1000_bus_speed_33, + e1000_bus_speed_66, + e1000_bus_speed_100, + e1000_bus_speed_133, + e1000_bus_speed_reserved +} e1000_bus_speed; + +/* PCI bus widths */ +typedef enum { + e1000_bus_width_unknown = 0, + e1000_bus_width_32, + e1000_bus_width_64 +} e1000_bus_width; + +/* PHY status info structure and supporting enums */ +typedef enum { + e1000_cable_length_50 = 0, + e1000_cable_length_50_80, + e1000_cable_length_80_110, + e1000_cable_length_110_140, + e1000_cable_length_140, + e1000_cable_length_undefined = 0xFF +} e1000_cable_length; + +typedef enum { + e1000_10bt_ext_dist_enable_normal = 0, + e1000_10bt_ext_dist_enable_lower, + e1000_10bt_ext_dist_enable_undefined = 0xFF +} e1000_10bt_ext_dist_enable; + +typedef enum { + e1000_rev_polarity_normal = 0, + e1000_rev_polarity_reversed, + e1000_rev_polarity_undefined = 0xFF +} e1000_rev_polarity; + +typedef enum { + e1000_polarity_reversal_enabled = 0, + e1000_polarity_reversal_disabled, + e1000_polarity_reversal_undefined = 0xFF +} e1000_polarity_reversal; + +typedef enum { + e1000_auto_x_mode_manual_mdi = 0, + e1000_auto_x_mode_manual_mdix, + e1000_auto_x_mode_auto1, + e1000_auto_x_mode_auto2, + e1000_auto_x_mode_undefined = 0xFF +} e1000_auto_x_mode; + +typedef enum { + e1000_1000t_rx_status_not_ok = 0, + e1000_1000t_rx_status_ok, + e1000_1000t_rx_status_undefined = 0xFF +} e1000_1000t_rx_status; + +struct e1000_phy_info { + e1000_cable_length cable_length; + e1000_10bt_ext_dist_enable extended_10bt_distance; + e1000_rev_polarity cable_polarity; + e1000_polarity_reversal polarity_correction; + e1000_auto_x_mode mdix_mode; + e1000_1000t_rx_status local_rx; + e1000_1000t_rx_status remote_rx; +}; + +struct e1000_phy_stats { + uint32_t idle_errors; + uint32_t receive_errors; +}; + +/* Error Codes */ +#define E1000_SUCCESS 0 +#define E1000_ERR_EEPROM 1 +#define E1000_ERR_PHY 2 +#define E1000_ERR_CONFIG 3 +#define E1000_ERR_PARAM 4 +#define E1000_ERR_MAC_TYPE 5 +#define E1000_ERR_NOLINK 6 +#define E1000_ERR_TIMEOUT 7 + +/* PCI Device IDs */ +#define E1000_DEV_ID_82542 0x1000 +#define E1000_DEV_ID_82543GC_FIBER 0x1001 +#define E1000_DEV_ID_82543GC_COPPER 0x1004 +#define E1000_DEV_ID_82544EI_COPPER 0x1008 +#define E1000_DEV_ID_82544EI_FIBER 0x1009 +#define E1000_DEV_ID_82544GC_COPPER 0x100C +#define E1000_DEV_ID_82544GC_LOM 0x100D +#define E1000_DEV_ID_82540EM 0x100E +#define E1000_DEV_ID_82540EM_LOM 0x1015 +#define E1000_DEV_ID_82545EM_COPPER 0x100F +#define E1000_DEV_ID_82545EM_FIBER 0x1011 +#define E1000_DEV_ID_82546EB_COPPER 0x1010 +#define E1000_DEV_ID_82546EB_FIBER 0x1012 +#define NUM_DEV_IDS 13 + +#define NODE_ADDRESS_SIZE 6 +#define ETH_LENGTH_OF_ADDRESS 6 + +/* MAC decode size is 128K - This is the size of BAR0 */ +#define MAC_DECODE_SIZE (128 * 1024) + +#define E1000_82542_2_0_REV_ID 2 +#define E1000_82542_2_1_REV_ID 3 + +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define HALF_DUPLEX 1 +#define FULL_DUPLEX 2 + +/* The sizes (in bytes) of a ethernet packet */ +#define ENET_HEADER_SIZE 14 +#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ +#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ +#define ETHERNET_FCS_SIZE 4 +#define MAXIMUM_ETHERNET_PACKET_SIZE \ + (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) +#define MINIMUM_ETHERNET_PACKET_SIZE \ + (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) +#define CRC_LENGTH ETHERNET_FCS_SIZE +#define MAX_JUMBO_FRAME_SIZE 0x3F00 + +/* 802.1q VLAN Packet Sizes */ +#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ + +/* Ethertype field values */ +#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ +#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ +#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ + +/* Packet Header defines */ +#define IP_PROTOCOL_TCP 6 +#define IP_PROTOCOL_UDP 0x11 + +/* This defines the bits that are set in the Interrupt Mask + * Set/Read Register. Each bit is documented below: + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) + * o RXSEQ = Receive Sequence Error + */ +#define POLL_IMS_ENABLE_MASK ( \ + E1000_IMS_RXDMT0 | \ + E1000_IMS_RXSEQ) + +/* This defines the bits that are set in the Interrupt Mask + * Set/Read Register. Each bit is documented below: + * o RXT0 = Receiver Timer Interrupt (ring 0) + * o TXDW = Transmit Descriptor Written Back + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) + * o RXSEQ = Receive Sequence Error + * o LSC = Link Status Change + */ +#define IMS_ENABLE_MASK ( \ + E1000_IMS_RXT0 | \ + E1000_IMS_TXDW | \ + E1000_IMS_RXDMT0 | \ + E1000_IMS_RXSEQ | \ + E1000_IMS_LSC) + +/* The number of high/low register pairs in the RAR. The RAR (Receive Address + * Registers) holds the directed and multicast addresses that we monitor. We + * reserve one of these spots for our directed address, allowing us room for + * E1000_RAR_ENTRIES - 1 multicast addresses. + */ +#define E1000_RAR_ENTRIES 16 + +#define MIN_NUMBER_OF_DESCRIPTORS 8 +#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 + +/* Receive Descriptor */ +struct e1000_rx_desc { + uint64_t buffer_addr; /* Address of the descriptor's data buffer */ + uint16_t length; /* Length of data DMAed into data buffer */ + uint16_t csum; /* Packet checksum */ + uint8_t status; /* Descriptor status */ + uint8_t errors; /* Descriptor Errors */ + uint16_t special; +}; + +/* Receive Decriptor bit definitions */ +#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ +#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ +#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ +#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ +#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ +#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ +#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ +#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ +#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ +#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ +#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ +#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ +#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ +#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ +#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ +#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ +#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ +#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ + +/* mask to determine if packets should be dropped due to frame errors */ +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ + E1000_RXD_ERR_CE | \ + E1000_RXD_ERR_SE | \ + E1000_RXD_ERR_SEQ | \ + E1000_RXD_ERR_CXE | \ + E1000_RXD_ERR_RXE) + +/* Transmit Descriptor */ +struct e1000_tx_desc { + uint64_t buffer_addr; /* Address of the descriptor's data buffer */ + union { + uint32_t data; + struct { + uint16_t length; /* Data buffer length */ + uint8_t cso; /* Checksum offset */ + uint8_t cmd; /* Descriptor control */ + } flags; + } lower; + union { + uint32_t data; + struct { + uint8_t status; /* Descriptor status */ + uint8_t css; /* Checksum start */ + uint16_t special; + } fields; + } upper; +}; + +/* Transmit Descriptor bit definitions */ +#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ +#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ +#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ +#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ +#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ +#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ +#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ +#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ +#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ +#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ +#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ +#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ +#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ +#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ +#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ +#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ +#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ +#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ +#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ +#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ + +/* Offload Context Descriptor */ +struct e1000_context_desc { + union { + uint32_t ip_config; + struct { + uint8_t ipcss; /* IP checksum start */ + uint8_t ipcso; /* IP checksum offset */ + uint16_t ipcse; /* IP checksum end */ + } ip_fields; + } lower_setup; + union { + uint32_t tcp_config; + struct { + uint8_t tucss; /* TCP checksum start */ + uint8_t tucso; /* TCP checksum offset */ + uint16_t tucse; /* TCP checksum end */ + } tcp_fields; + } upper_setup; + uint32_t cmd_and_length; /* */ + union { + uint32_t data; + struct { + uint8_t status; /* Descriptor status */ + uint8_t hdr_len; /* Header length */ + uint16_t mss; /* Maximum segment size */ + } fields; + } tcp_seg_setup; +}; + +/* Offload data descriptor */ +struct e1000_data_desc { + uint64_t buffer_addr; /* Address of the descriptor's buffer address */ + union { + uint32_t data; + struct { + uint16_t length; /* Data buffer length */ + uint8_t typ_len_ext; /* */ + uint8_t cmd; /* */ + } flags; + } lower; + union { + uint32_t data; + struct { + uint8_t status; /* Descriptor status */ + uint8_t popts; /* Packet Options */ + uint16_t special; /* */ + } fields; + } upper; +}; + +/* Filters */ +#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ +#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ +#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ + +/* Receive Address Register */ +struct e1000_rar { + volatile uint32_t low; /* receive address low */ + volatile uint32_t high; /* receive address high */ +}; + +/* The number of entries in the Multicast Table Array (MTA). */ +#define E1000_NUM_MTA_REGISTERS 128 + +/* IPv4 Address Table Entry */ +struct e1000_ipv4_at_entry { + volatile uint32_t ipv4_addr; /* IP Address (RW) */ + volatile uint32_t reserved; +}; + +/* Four wakeup IP addresses are supported */ +#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 +#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX +#define E1000_IP6AT_SIZE 1 + +/* IPv6 Address Table Entry */ +struct e1000_ipv6_at_entry { + volatile uint8_t ipv6_addr[16]; +}; + +/* Flexible Filter Length Table Entry */ +struct e1000_fflt_entry { + volatile uint32_t length; /* Flexible Filter Length (RW) */ + volatile uint32_t reserved; +}; + +/* Flexible Filter Mask Table Entry */ +struct e1000_ffmt_entry { + volatile uint32_t mask; /* Flexible Filter Mask (RW) */ + volatile uint32_t reserved; +}; + +/* Flexible Filter Value Table Entry */ +struct e1000_ffvt_entry { + volatile uint32_t value; /* Flexible Filter Value (RW) */ + volatile uint32_t reserved; +}; + +/* Four Flexible Filters are supported */ +#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 + +/* Each Flexible Filter is at most 128 (0x80) bytes in length */ +#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 + +#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX +#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX +#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX + +/* Register Set. (82543, 82544) + * + * Registers are defined to be 32 bits and should be accessed as 32 bit values. + * These registers are physically located on the NIC, but are mapped into the + * host memory address space. + * + * RW - register is both readable and writable + * RO - register is read only + * WO - register is write only + * R/clr - register is read only and is cleared when read + * A - register array + */ +#define E1000_CTRL 0x00000 /* Device Control - RW */ +#define E1000_STATUS 0x00008 /* Device Status - RO */ +#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ +#define E1000_EERD 0x00014 /* EEPROM Read - RW */ +#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ +#define E1000_MDIC 0x00020 /* MDI Control - RW */ +#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ +#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ +#define E1000_FCT 0x00030 /* Flow Control Type - RW */ +#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ +#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ +#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ +#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ +#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ +#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ +#define E1000_RCTL 0x00100 /* RX Control - RW */ +#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ +#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ +#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ +#define E1000_TCTL 0x00400 /* TX Control - RW */ +#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ +#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ +#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ +#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ +#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ +#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ +#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ +#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ +#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ +#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ +#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ +#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ +#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ +#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ +#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ +#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ +#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ +#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ +#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ +#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ +#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ +#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ +#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ +#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ +#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ +#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ +#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ +#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ +#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ +#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ +#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ +#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ +#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ +#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ +#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ +#define E1000_COLC 0x04028 /* Collision Count - R/clr */ +#define E1000_DC 0x04030 /* Defer Count - R/clr */ +#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ +#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ +#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ +#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ +#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ +#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ +#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ +#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ +#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ +#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ +#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ +#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ +#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ +#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ +#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ +#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ +#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ +#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ +#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ +#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ +#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ +#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ +#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ +#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ +#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ +#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ +#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ +#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ +#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ +#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ +#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ +#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ +#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ +#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ +#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ +#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ +#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ +#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ +#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ +#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ +#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ +#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ +#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ +#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ +#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ +#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ +#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ +#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ +#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ +#define E1000_RA 0x05400 /* Receive Address - RW Array */ +#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ +#define E1000_WUC 0x05800 /* Wakeup Control - RW */ +#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ +#define E1000_WUS 0x05810 /* Wakeup Status - RO */ +#define E1000_MANC 0x05820 /* Management Control - RW */ +#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ +#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ +#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ +#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ +#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ +#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ +#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ +#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ + +/* Register Set (82542) + * + * Some of the 82542 registers are located at different offsets than they are + * in more current versions of the 8254x. Despite the difference in location, + * the registers function in the same manner. + */ +#define E1000_82542_CTRL E1000_CTRL +#define E1000_82542_STATUS E1000_STATUS +#define E1000_82542_EECD E1000_EECD +#define E1000_82542_EERD E1000_EERD +#define E1000_82542_CTRL_EXT E1000_CTRL_EXT +#define E1000_82542_MDIC E1000_MDIC +#define E1000_82542_FCAL E1000_FCAL +#define E1000_82542_FCAH E1000_FCAH +#define E1000_82542_FCT E1000_FCT +#define E1000_82542_VET E1000_VET +#define E1000_82542_RA 0x00040 +#define E1000_82542_ICR E1000_ICR +#define E1000_82542_ITR E1000_ITR +#define E1000_82542_ICS E1000_ICS +#define E1000_82542_IMS E1000_IMS +#define E1000_82542_IMC E1000_IMC +#define E1000_82542_RCTL E1000_RCTL +#define E1000_82542_RDTR 0x00108 +#define E1000_82542_RDBAL 0x00110 +#define E1000_82542_RDBAH 0x00114 +#define E1000_82542_RDLEN 0x00118 +#define E1000_82542_RDH 0x00120 +#define E1000_82542_RDT 0x00128 +#define E1000_82542_FCRTH 0x00160 +#define E1000_82542_FCRTL 0x00168 +#define E1000_82542_FCTTV E1000_FCTTV +#define E1000_82542_TXCW E1000_TXCW +#define E1000_82542_RXCW E1000_RXCW +#define E1000_82542_MTA 0x00200 +#define E1000_82542_TCTL E1000_TCTL +#define E1000_82542_TIPG E1000_TIPG +#define E1000_82542_TDBAL 0x00420 +#define E1000_82542_TDBAH 0x00424 +#define E1000_82542_TDLEN 0x00428 +#define E1000_82542_TDH 0x00430 +#define E1000_82542_TDT 0x00438 +#define E1000_82542_TIDV 0x00440 +#define E1000_82542_TBT E1000_TBT +#define E1000_82542_AIT E1000_AIT +#define E1000_82542_VFTA 0x00600 +#define E1000_82542_LEDCTL E1000_LEDCTL +#define E1000_82542_PBA E1000_PBA +#define E1000_82542_RXDCTL E1000_RXDCTL +#define E1000_82542_RADV E1000_RADV +#define E1000_82542_RSRPD E1000_RSRPD +#define E1000_82542_TXDMAC E1000_TXDMAC +#define E1000_82542_TXDCTL E1000_TXDCTL +#define E1000_82542_TADV E1000_TADV +#define E1000_82542_TSPMT E1000_TSPMT +#define E1000_82542_CRCERRS E1000_CRCERRS +#define E1000_82542_ALGNERRC E1000_ALGNERRC +#define E1000_82542_SYMERRS E1000_SYMERRS +#define E1000_82542_RXERRC E1000_RXERRC +#define E1000_82542_MPC E1000_MPC +#define E1000_82542_SCC E1000_SCC +#define E1000_82542_ECOL E1000_ECOL +#define E1000_82542_MCC E1000_MCC +#define E1000_82542_LATECOL E1000_LATECOL +#define E1000_82542_COLC E1000_COLC +#define E1000_82542_DC E1000_DC +#define E1000_82542_TNCRS E1000_TNCRS +#define E1000_82542_SEC E1000_SEC +#define E1000_82542_CEXTERR E1000_CEXTERR +#define E1000_82542_RLEC E1000_RLEC +#define E1000_82542_XONRXC E1000_XONRXC +#define E1000_82542_XONTXC E1000_XONTXC +#define E1000_82542_XOFFRXC E1000_XOFFRXC +#define E1000_82542_XOFFTXC E1000_XOFFTXC +#define E1000_82542_FCRUC E1000_FCRUC +#define E1000_82542_PRC64 E1000_PRC64 +#define E1000_82542_PRC127 E1000_PRC127 +#define E1000_82542_PRC255 E1000_PRC255 +#define E1000_82542_PRC511 E1000_PRC511 +#define E1000_82542_PRC1023 E1000_PRC1023 +#define E1000_82542_PRC1522 E1000_PRC1522 +#define E1000_82542_GPRC E1000_GPRC +#define E1000_82542_BPRC E1000_BPRC +#define E1000_82542_MPRC E1000_MPRC +#define E1000_82542_GPTC E1000_GPTC +#define E1000_82542_GORCL E1000_GORCL +#define E1000_82542_GORCH E1000_GORCH +#define E1000_82542_GOTCL E1000_GOTCL +#define E1000_82542_GOTCH E1000_GOTCH +#define E1000_82542_RNBC E1000_RNBC +#define E1000_82542_RUC E1000_RUC +#define E1000_82542_RFC E1000_RFC +#define E1000_82542_ROC E1000_ROC +#define E1000_82542_RJC E1000_RJC +#define E1000_82542_MGTPRC E1000_MGTPRC +#define E1000_82542_MGTPDC E1000_MGTPDC +#define E1000_82542_MGTPTC E1000_MGTPTC +#define E1000_82542_TORL E1000_TORL +#define E1000_82542_TORH E1000_TORH +#define E1000_82542_TOTL E1000_TOTL +#define E1000_82542_TOTH E1000_TOTH +#define E1000_82542_TPR E1000_TPR +#define E1000_82542_TPT E1000_TPT +#define E1000_82542_PTC64 E1000_PTC64 +#define E1000_82542_PTC127 E1000_PTC127 +#define E1000_82542_PTC255 E1000_PTC255 +#define E1000_82542_PTC511 E1000_PTC511 +#define E1000_82542_PTC1023 E1000_PTC1023 +#define E1000_82542_PTC1522 E1000_PTC1522 +#define E1000_82542_MPTC E1000_MPTC +#define E1000_82542_BPTC E1000_BPTC +#define E1000_82542_TSCTC E1000_TSCTC +#define E1000_82542_TSCTFC E1000_TSCTFC +#define E1000_82542_RXCSUM E1000_RXCSUM +#define E1000_82542_WUC E1000_WUC +#define E1000_82542_WUFC E1000_WUFC +#define E1000_82542_WUS E1000_WUS +#define E1000_82542_MANC E1000_MANC +#define E1000_82542_IPAV E1000_IPAV +#define E1000_82542_IP4AT E1000_IP4AT +#define E1000_82542_IP6AT E1000_IP6AT +#define E1000_82542_WUPL E1000_WUPL +#define E1000_82542_WUPM E1000_WUPM +#define E1000_82542_FFLT E1000_FFLT +#define E1000_82542_FFMT E1000_FFMT +#define E1000_82542_FFVT E1000_FFVT + +/* Statistics counters collected by the MAC */ +struct e1000_hw_stats { + uint64_t crcerrs; + uint64_t algnerrc; + uint64_t symerrs; + uint64_t rxerrc; + uint64_t mpc; + uint64_t scc; + uint64_t ecol; + uint64_t mcc; + uint64_t latecol; + uint64_t colc; + uint64_t dc; + uint64_t tncrs; + uint64_t sec; + uint64_t cexterr; + uint64_t rlec; + uint64_t xonrxc; + uint64_t xontxc; + uint64_t xoffrxc; + uint64_t xofftxc; + uint64_t fcruc; + uint64_t prc64; + uint64_t prc127; + uint64_t prc255; + uint64_t prc511; + uint64_t prc1023; + uint64_t prc1522; + uint64_t gprc; + uint64_t bprc; + uint64_t mprc; + uint64_t gptc; + uint64_t gorcl; + uint64_t gorch; + uint64_t gotcl; + uint64_t gotch; + uint64_t rnbc; + uint64_t ruc; + uint64_t rfc; + uint64_t roc; + uint64_t rjc; + uint64_t mgprc; + uint64_t mgpdc; + uint64_t mgptc; + uint64_t torl; + uint64_t torh; + uint64_t totl; + uint64_t toth; + uint64_t tpr; + uint64_t tpt; + uint64_t ptc64; + uint64_t ptc127; + uint64_t ptc255; + uint64_t ptc511; + uint64_t ptc1023; + uint64_t ptc1522; + uint64_t mptc; + uint64_t bptc; + uint64_t tsctc; + uint64_t tsctfc; +}; + +/* Structure containing variables used by the shared code (e1000_hw.c) */ +struct e1000_hw { + pci_dev_t pdev; + uint8_t *hw_addr; + e1000_mac_type mac_type; + e1000_media_type media_type; + e1000_lan_loc lan_loc; + e1000_fc_type fc; +#if 0 + e1000_bus_speed bus_speed; + e1000_bus_width bus_width; + e1000_bus_type bus_type; + uint32_t io_base; +#endif + uint32_t phy_id; + uint32_t phy_addr; + uint32_t original_fc; + uint32_t txcw; + uint32_t autoneg_failed; +#if 0 + uint32_t max_frame_size; + uint32_t min_frame_size; + uint32_t mc_filter_type; + uint32_t num_mc_addrs; + uint32_t collision_delta; + uint32_t tx_packet_delta; + uint32_t ledctl_default; + uint32_t ledctl_mode1; + uint32_t ledctl_mode2; +#endif + uint16_t autoneg_advertised; + uint16_t pci_cmd_word; + uint16_t fc_high_water; + uint16_t fc_low_water; + uint16_t fc_pause_time; +#if 0 + uint16_t current_ifs_val; + uint16_t ifs_min_val; + uint16_t ifs_max_val; + uint16_t ifs_step_size; + uint16_t ifs_ratio; +#endif + uint16_t device_id; + uint16_t vendor_id; + uint16_t subsystem_id; + uint16_t subsystem_vendor_id; + uint8_t revision_id; +#if 0 + uint8_t autoneg; + uint8_t mdix; + uint8_t forced_speed_duplex; + uint8_t wait_autoneg_complete; + uint8_t dma_fairness; +#endif +#if 0 + uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; + boolean_t disable_polarity_correction; +#endif + boolean_t get_link_status; + boolean_t tbi_compatibility_en; + boolean_t tbi_compatibility_on; + boolean_t fc_send_xon; + boolean_t report_tx_early; +#if 0 + boolean_t adaptive_ifs; + boolean_t ifs_params_forced; + boolean_t in_ifs_mode; +#endif +}; + +#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ +#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ + +/* Register Bit Masks */ +/* Device Control */ +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ +#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ +#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ +#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ +#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ +#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ +#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ +#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ +#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ +#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ +#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ +#define E1000_CTRL_RST 0x04000000 /* Global reset */ +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ +#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ + +/* Device Status */ +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ +#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ +#define E1000_STATUS_SPEED_MASK 0x000000C0 +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ +#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ +#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ +#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ +#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ +#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ + +/* Constants used to intrepret the masked PCI-X bus speed. */ +#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ + +/* EEPROM/Flash Control */ +#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ +#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ +#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ +#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ +#define E1000_EECD_FWE_MASK 0x00000030 +#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ +#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ +#define E1000_EECD_FWE_SHIFT 4 +#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ +#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ +#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ +#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ + +/* EEPROM Read */ +#define E1000_EERD_START 0x00000001 /* Start Read */ +#define E1000_EERD_DONE 0x00000010 /* Read Done */ +#define E1000_EERD_ADDR_SHIFT 8 +#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ +#define E1000_EERD_DATA_SHIFT 16 +#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ + +/* Extended Device Control */ +#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ +#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ +#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN +#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ +#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ +#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA +#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ +#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */ +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ +#define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */ +#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ +#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ +#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ +#define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */ +#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ +#define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */ +#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ +#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ +#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ +#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 +#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 +#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 +#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 +#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 +#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 +#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 +#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 + +/* MDI Control */ +#define E1000_MDIC_DATA_MASK 0x0000FFFF +#define E1000_MDIC_REG_MASK 0x001F0000 +#define E1000_MDIC_REG_SHIFT 16 +#define E1000_MDIC_PHY_MASK 0x03E00000 +#define E1000_MDIC_PHY_SHIFT 21 +#define E1000_MDIC_OP_WRITE 0x04000000 +#define E1000_MDIC_OP_READ 0x08000000 +#define E1000_MDIC_READY 0x10000000 +#define E1000_MDIC_INT_EN 0x20000000 +#define E1000_MDIC_ERROR 0x40000000 + +/* LED Control */ +#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F +#define E1000_LEDCTL_LED0_MODE_SHIFT 0 +#define E1000_LEDCTL_LED0_IVRT 0x00000040 +#define E1000_LEDCTL_LED0_BLINK 0x00000080 +#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 +#define E1000_LEDCTL_LED1_MODE_SHIFT 8 +#define E1000_LEDCTL_LED1_IVRT 0x00004000 +#define E1000_LEDCTL_LED1_BLINK 0x00008000 +#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 +#define E1000_LEDCTL_LED2_MODE_SHIFT 16 +#define E1000_LEDCTL_LED2_IVRT 0x00400000 +#define E1000_LEDCTL_LED2_BLINK 0x00800000 +#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 +#define E1000_LEDCTL_LED3_MODE_SHIFT 24 +#define E1000_LEDCTL_LED3_IVRT 0x40000000 +#define E1000_LEDCTL_LED3_BLINK 0x80000000 + +#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 +#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 +#define E1000_LEDCTL_MODE_LINK_UP 0x2 +#define E1000_LEDCTL_MODE_ACTIVITY 0x3 +#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 +#define E1000_LEDCTL_MODE_LINK_10 0x5 +#define E1000_LEDCTL_MODE_LINK_100 0x6 +#define E1000_LEDCTL_MODE_LINK_1000 0x7 +#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 +#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 +#define E1000_LEDCTL_MODE_COLLISION 0xA +#define E1000_LEDCTL_MODE_BUS_SPEED 0xB +#define E1000_LEDCTL_MODE_BUS_SIZE 0xC +#define E1000_LEDCTL_MODE_PAUSED 0xD +#define E1000_LEDCTL_MODE_LED_ON 0xE +#define E1000_LEDCTL_MODE_LED_OFF 0xF + +/* Receive Address */ +#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ + +/* Interrupt Cause Read */ +#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ +#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ +#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ +#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ +#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ +#define E1000_ICR_RXO 0x00000040 /* rx overrun */ +#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ +#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ +#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ +#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ +#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ +#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ +#define E1000_ICR_TXD_LOW 0x00008000 +#define E1000_ICR_SRPD 0x00010000 + +/* Interrupt Cause Set */ +#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_ICS_SRPD E1000_ICR_SRPD + +/* Interrupt Mask Set */ +#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_IMS_SRPD E1000_ICR_SRPD + +/* Interrupt Mask Clear */ +#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_IMC_SRPD E1000_ICR_SRPD + +/* Receive Control */ +#define E1000_RCTL_RST 0x00000001 /* Software reset */ +#define E1000_RCTL_EN 0x00000002 /* enable */ +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ +#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ + +/* Receive Descriptor */ +#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ +#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ +#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ +#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ +#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ + +/* Flow Control */ +#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ +#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ +#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ +#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ + +/* Receive Descriptor Control */ +#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ +#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ +#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ +#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ + +/* Transmit Descriptor Control */ +#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */ +#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */ +#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */ +#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ +#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ + +/* Transmit Configuration Word */ +#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ +#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ +#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ +#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ +#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ +#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ +#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ +#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ +#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ +#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ + +/* Receive Configuration Word */ +#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ +#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ +#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ +#define E1000_RXCW_CC 0x10000000 /* Receive config change */ +#define E1000_RXCW_C 0x20000000 /* Receive config */ +#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ +#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ + +/* Transmit Control */ +#define E1000_TCTL_RST 0x00000001 /* software reset */ +#define E1000_TCTL_EN 0x00000002 /* enable tx */ +#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ +#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ +#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ + +/* Receive Checksum Control */ +#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ +#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ +#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ +#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ + +/* Definitions for power management and wakeup registers */ +/* Wake Up Control */ +#define E1000_WUC_APME 0x00000001 /* APM Enable */ +#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ +#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ +#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ + +/* Wake Up Filter Control */ +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ +#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ +#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ +#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ +#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ +#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ +#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ +#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ +#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ +#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ +#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ +#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ +#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ +#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ +#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ + +/* Wake Up Status */ +#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ +#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ +#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ +#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ +#define E1000_WUS_BC 0x00000010 /* Broadcast Received */ +#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ +#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ +#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ +#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ +#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ +#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ +#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ +#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ + +/* Management Control */ +#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ +#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ +#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ +#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ +#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ +#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ +#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ +#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ +#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ +#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery + * Filtering */ +#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ +#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ +#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ +#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ +#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ +#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ +#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ +#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ +#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ + +#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ +#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ + +/* Wake Up Packet Length */ +#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ + +#define E1000_MDALIGN 4096 + +/* EEPROM Commands */ +#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */ +#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */ +#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */ +#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */ +#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */ + +/* EEPROM Word Offsets */ +#define EEPROM_COMPAT 0x0003 +#define EEPROM_ID_LED_SETTINGS 0x0004 +#define EEPROM_INIT_CONTROL1_REG 0x000A +#define EEPROM_INIT_CONTROL2_REG 0x000F +#define EEPROM_FLASH_VERSION 0x0032 +#define EEPROM_CHECKSUM_REG 0x003F + +/* Word definitions for ID LED Settings */ +#define ID_LED_RESERVED_0000 0x0000 +#define ID_LED_RESERVED_FFFF 0xFFFF +#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ + (ID_LED_OFF1_OFF2 << 8) | \ + (ID_LED_DEF1_DEF2 << 4) | \ + (ID_LED_DEF1_DEF2)) +#define ID_LED_DEF1_DEF2 0x1 +#define ID_LED_DEF1_ON2 0x2 +#define ID_LED_DEF1_OFF2 0x3 +#define ID_LED_ON1_DEF2 0x4 +#define ID_LED_ON1_ON2 0x5 +#define ID_LED_ON1_OFF2 0x6 +#define ID_LED_OFF1_DEF2 0x7 +#define ID_LED_OFF1_ON2 0x8 +#define ID_LED_OFF1_OFF2 0x9 + +/* Mask bits for fields in Word 0x03 of the EEPROM */ +#define EEPROM_COMPAT_SERVER 0x0400 +#define EEPROM_COMPAT_CLIENT 0x0200 + +/* Mask bits for fields in Word 0x0a of the EEPROM */ +#define EEPROM_WORD0A_ILOS 0x0010 +#define EEPROM_WORD0A_SWDPIO 0x01E0 +#define EEPROM_WORD0A_LRST 0x0200 +#define EEPROM_WORD0A_FD 0x0400 +#define EEPROM_WORD0A_66MHZ 0x0800 + +/* Mask bits for fields in Word 0x0f of the EEPROM */ +#define EEPROM_WORD0F_PAUSE_MASK 0x3000 +#define EEPROM_WORD0F_PAUSE 0x1000 +#define EEPROM_WORD0F_ASM_DIR 0x2000 +#define EEPROM_WORD0F_ANE 0x0800 +#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 + +/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ +#define EEPROM_SUM 0xBABA + +/* EEPROM Map defines (WORD OFFSETS)*/ +#define EEPROM_NODE_ADDRESS_BYTE_0 0 +#define EEPROM_PBA_BYTE_1 8 + +/* EEPROM Map Sizes (Byte Counts) */ +#define PBA_SIZE 4 + +/* Collision related configuration parameters */ +#define E1000_COLLISION_THRESHOLD 16 +#define E1000_CT_SHIFT 4 +#define E1000_COLLISION_DISTANCE 64 +#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +#define E1000_GB_HDX_COLLISION_DISTANCE 512 +#define E1000_COLD_SHIFT 12 + +/* The number of Transmit and Receive Descriptors must be a multiple of 8 */ +#define REQ_TX_DESCRIPTOR_MULTIPLE 8 +#define REQ_RX_DESCRIPTOR_MULTIPLE 8 + +/* Default values for the transmit IPG register */ +#define DEFAULT_82542_TIPG_IPGT 10 +#define DEFAULT_82543_TIPG_IPGT_FIBER 9 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8 + +#define E1000_TIPG_IPGT_MASK 0x000003FF +#define E1000_TIPG_IPGR1_MASK 0x000FFC00 +#define E1000_TIPG_IPGR2_MASK 0x3FF00000 + +#define DEFAULT_82542_TIPG_IPGR1 2 +#define DEFAULT_82543_TIPG_IPGR1 8 +#define E1000_TIPG_IPGR1_SHIFT 10 + +#define DEFAULT_82542_TIPG_IPGR2 10 +#define DEFAULT_82543_TIPG_IPGR2 6 +#define E1000_TIPG_IPGR2_SHIFT 20 + +#define E1000_TXDMAC_DPP 0x00000001 + +/* Adaptive IFS defines */ +#define TX_THRESHOLD_START 8 +#define TX_THRESHOLD_INCREMENT 10 +#define TX_THRESHOLD_DECREMENT 1 +#define TX_THRESHOLD_STOP 190 +#define TX_THRESHOLD_DISABLE 0 +#define TX_THRESHOLD_TIMER_MS 10000 +#define MIN_NUM_XMITS 1000 +#define IFS_MAX 80 +#define IFS_STEP 10 +#define IFS_MIN 40 +#define IFS_RATIO 4 + +/* PBA constants */ +#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ +#define E1000_PBA_24K 0x0018 +#define E1000_PBA_40K 0x0028 +#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ + +/* Flow Control Constants */ +#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 +#define FLOW_CONTROL_TYPE 0x8808 + +/* The historical defaults for the flow control values are given below. */ +#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ +#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ +#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ + +/* Flow Control High-Watermark: 43464 bytes */ +#define E1000_FC_HIGH_THRESH 0xA9C8 +/* Flow Control Low-Watermark: 43456 bytes */ +#define E1000_FC_LOW_THRESH 0xA9C0 +/* Flow Control Pause Time: 858 usec */ +#define E1000_FC_PAUSE_TIME 0x0680 + +/* PCIX Config space */ +#define PCIX_COMMAND_REGISTER 0xE6 +#define PCIX_STATUS_REGISTER_LO 0xE8 +#define PCIX_STATUS_REGISTER_HI 0xEA + +#define PCIX_COMMAND_MMRBC_MASK 0x000C +#define PCIX_COMMAND_MMRBC_SHIFT 0x2 +#define PCIX_STATUS_HI_MMRBC_MASK 0x0060 +#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 +#define PCIX_STATUS_HI_MMRBC_4K 0x3 +#define PCIX_STATUS_HI_MMRBC_2K 0x2 + +/* The number of bits that we need to shift right to move the "pause" + * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field + * in the TXCW register + */ +#define PAUSE_SHIFT 5 + +/* The number of bits that we need to shift left to move the "SWDPIO" + * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field + * in the CTRL register + */ +#define SWDPIO_SHIFT 17 + +/* The number of bits that we need to shift left to move the "SWDPIO_EXT" + * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The + * Extended CTRL register. + * in the CTRL register + */ +#define SWDPIO__EXT_SHIFT 4 + +/* The number of bits that we need to shift left to move the "ILOS" + * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field + * in the CTRL register + */ +#define ILOS_SHIFT 3 + +#define RECEIVE_BUFFER_ALIGN_SIZE (256) + +/* The number of milliseconds we wait for auto-negotiation to complete */ +#define LINK_UP_TIMEOUT 500 + +#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) + +/* The carrier extension symbol, as received by the NIC. */ +#define CARRIER_EXTENSION 0x0F + +/* TBI_ACCEPT macro definition: + * + * This macro requires: + * adapter = a pointer to struct e1000_hw + * status = the 8 bit status field of the RX descriptor with EOP set + * error = the 8 bit error field of the RX descriptor with EOP set + * length = the sum of all the length fields of the RX descriptors that + * make up the current frame + * last_byte = the last byte of the frame DMAed by the hardware + * max_frame_length = the maximum frame length we want to accept. + * min_frame_length = the minimum frame length we want to accept. + * + * This macro is a conditional that should be used in the interrupt + * handler's Rx processing routine when RxErrors have been detected. + * + * Typical use: + * ... + * if (TBI_ACCEPT) { + * accept_frame = TRUE; + * e1000_tbi_adjust_stats(adapter, MacAddress); + * frame_length--; + * } else { + * accept_frame = FALSE; + * } + * ... + */ + +#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ + ((adapter)->tbi_compatibility_on && \ + (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ + ((last_byte) == CARRIER_EXTENSION) && \ + (((status) & E1000_RXD_STAT_VP) ? \ + (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ + ((length) <= ((adapter)->max_frame_size + 1))) : \ + (((length) > (adapter)->min_frame_size) && \ + ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) + +/* Structures, enums, and macros for the PHY */ + +/* Bit definitions for the Management Data IO (MDIO) and Management Data + * Clock (MDC) pins in the Device Control Register. + */ +#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 +#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 +#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 +#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 +#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 +#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 +#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR +#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA + +/* PHY 1000 MII Register/Bit Definitions */ +/* PHY Registers defined by IEEE */ +#define PHY_CTRL 0x00 /* Control Register */ +#define PHY_STATUS 0x01 /* Status Regiser */ +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ + +/* M88E1000 Specific Registers */ +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ +#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ + +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ + +/* PHY Control Register */ +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ +#define MII_CR_POWER_DOWN 0x0800 /* Power down */ +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ + +/* PHY Status Register */ +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ + +/* Autoneg Advertisement Register */ +#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ +#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ +#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ +#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ +#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ +#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ +#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ +#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ +#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ +#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Link Partner Ability Register (Base Page) */ +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ +#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ +#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ +#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ +#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ +#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ +#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ +#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ +#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ +#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Autoneg Expansion Register */ +#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ +#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ +#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ +#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */ + +/* Next Page TX Register */ +#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ + +/* Link Partner Next Page Register */ +#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ +#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ + +/* 1000BASE-T Control Register */ +#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ +#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ +#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ +#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ + /* 0=DTE device */ +#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ + /* 0=Configure PHY as Slave */ +#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ + /* 0=Automatic Master/Slave config */ +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ +#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ +#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ +#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ +#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ + +/* 1000BASE-T Status Register */ +#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ +#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ +#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ +#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ +#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ +#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ +#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ +#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 +#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 + +/* Extended Status Register */ +#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ +#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ +#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ +#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ + +#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ +#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ + +#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ + /* (0=enable, 1=disable) */ + +/* M88E1000 PHY Specific Control Register */ +#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ +#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ +#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, + * 0=CLK125 toggling + */ +#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ + /* Manual MDI configuration */ +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ +#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, + * 100BASE-TX/10BASE-T: + * MDI Mode + */ +#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled + * all speeds. + */ +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 + /* 1=Enable Extended 10BASE-T distance + * (Lower 10BASE-T RX Threshold) + * 0=Normal 10BASE-T RX Threshold */ +#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 + /* 1=5-Bit interface in 100BASE-TX + * 0=MII interface in 100BASE-TX */ +#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ +#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ +#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ + +#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 +#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 + +/* M88E1000 PHY Specific Status Register */ +#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ +#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ +#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ +#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; + * 3=110-140M;4=>140M */ +#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ +#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ +#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ +#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ +#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ +#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ +#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ +#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ + +#define M88E1000_PSSR_REV_POLARITY_SHIFT 1 +#define M88E1000_PSSR_MDIX_SHIFT 6 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 + +/* M88E1000 Extended PHY Specific Control Register */ +#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ +#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. + * Will assert lost lock and bring + * link down if idle not seen + * within 1ms in 1000BASE-T + */ +/* Number of times we will attempt to autonegotiate before downshifting if we + * are the master */ +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 +/* Number of times we will attempt to autonegotiate before downshifting if we + * are the slave */ +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 +#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ + +/* Bit definitions for valid PHY IDs. */ +#define M88E1000_E_PHY_ID 0x01410C50 +#define M88E1000_I_PHY_ID 0x01410C30 +#define M88E1011_I_PHY_ID 0x01410C20 +#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID +#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID + +/* Miscellaneous PHY bit definitions. */ +#define PHY_PREAMBLE 0xFFFFFFFF +#define PHY_SOF 0x01 +#define PHY_OP_READ 0x02 +#define PHY_OP_WRITE 0x01 +#define PHY_TURNAROUND 0x02 +#define PHY_PREAMBLE_SIZE 32 +#define MII_CR_SPEED_1000 0x0040 +#define MII_CR_SPEED_100 0x2000 +#define MII_CR_SPEED_10 0x0000 +#define E1000_PHY_ADDRESS 0x01 +#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ +#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ +#define PHY_REVISION_MASK 0xFFFFFFF0 +#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ +#define REG4_SPEED_MASK 0x01E0 +#define REG9_SPEED_MASK 0x0300 +#define ADVERTISE_10_HALF 0x0001 +#define ADVERTISE_10_FULL 0x0002 +#define ADVERTISE_100_HALF 0x0004 +#define ADVERTISE_100_FULL 0x0008 +#define ADVERTISE_1000_HALF 0x0010 +#define ADVERTISE_1000_FULL 0x0020 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ + +#endif /* _E1000_HW_H_ */ diff --git a/drivers/eepro100.c b/drivers/eepro100.c new file mode 100644 index 0000000..04c17f6 --- /dev/null +++ b/drivers/eepro100.c @@ -0,0 +1,948 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#undef DEBUG + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_EEPRO100) + + /* Ethernet chip registers. + */ +#define SCBStatus 0 /* Rx/Command Unit Status *Word* */ +#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ +#define SCBCmd 2 /* Rx/Command Unit Command *Word* */ +#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ +#define SCBPointer 4 /* General purpose pointer. */ +#define SCBPort 8 /* Misc. commands and operands. */ +#define SCBflash 12 /* Flash memory control. */ +#define SCBeeprom 14 /* EEPROM memory control. */ +#define SCBCtrlMDI 16 /* MDI interface control. */ +#define SCBEarlyRx 20 /* Early receive byte count. */ +#define SCBGenControl 28 /* 82559 General Control Register */ +#define SCBGenStatus 29 /* 82559 General Status register */ + + /* 82559 SCB status word defnitions + */ +#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ +#define SCB_STATUS_FR 0x4000 /* frame received */ +#define SCB_STATUS_CNA 0x2000 /* CU left active state */ +#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ +#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ +#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ +#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ + +#define SCB_INTACK_MASK 0xFD00 /* all the above */ + +#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) +#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) + + /* System control block commands + */ +/* CU Commands */ +#define CU_NOP 0x0000 +#define CU_START 0x0010 +#define CU_RESUME 0x0020 +#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ +#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ +#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ +#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ + +/* RUC Commands */ +#define RUC_NOP 0x0000 +#define RUC_START 0x0001 +#define RUC_RESUME 0x0002 +#define RUC_ABORT 0x0004 +#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ +#define RUC_RESUMENR 0x0007 + +#define CU_CMD_MASK 0x00f0 +#define RU_CMD_MASK 0x0007 + +#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ +#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ + +#define CU_STATUS_MASK 0x00C0 +#define RU_STATUS_MASK 0x003C + +#define RU_STATUS_IDLE (0<<2) +#define RU_STATUS_SUS (1<<2) +#define RU_STATUS_NORES (2<<2) +#define RU_STATUS_READY (4<<2) +#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) +#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) +#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) + + /* 82559 Port interface commands. + */ +#define I82559_RESET 0x00000000 /* Software reset */ +#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ +#define I82559_SELECTIVE_RESET 0x00000002 +#define I82559_DUMP 0x00000003 +#define I82559_DUMP_WAKEUP 0x00000007 + + /* 82559 Eeprom interface. + */ +#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ +#define EE_CS 0x02 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x01 +#define EE_WRITE_1 0x05 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_ENB (0x4800 | EE_CS) +#define EE_CMD_BITS 3 +#define EE_DATA_BITS 16 + + /* The EEPROM commands include the alway-set leading bit. + */ +#define EE_EWENB_CMD (4 << addr_len) +#define EE_WRITE_CMD (5 << addr_len) +#define EE_READ_CMD (6 << addr_len) +#define EE_ERASE_CMD (7 << addr_len) + + /* Receive frame descriptors. + */ +struct RxFD { + volatile u16 status; + volatile u16 control; + volatile u32 link; /* struct RxFD * */ + volatile u32 rx_buf_addr; /* void * */ + volatile u32 count; + + volatile u8 data[PKTSIZE_ALIGN]; +}; + +#define RFD_STATUS_C 0x8000 /* completion of received frame */ +#define RFD_STATUS_OK 0x2000 /* frame received with no errors */ + +#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ +#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ +#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ +#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ + +#define RFD_COUNT_MASK 0x3fff +#define RFD_COUNT_F 0x4000 +#define RFD_COUNT_EOF 0x8000 + +#define RFD_RX_CRC 0x0800 /* crc error */ +#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ +#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ +#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ +#define RFD_RX_SHORT 0x0080 /* short frame error */ +#define RFD_RX_LENGTH 0x0020 +#define RFD_RX_ERROR 0x0010 /* receive error */ +#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ +#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ +#define RFD_RX_TCO 0x0001 /* TCO indication */ + + /* Transmit frame descriptors + */ +struct TxFD { /* Transmit frame descriptor set. */ + volatile u16 status; + volatile u16 command; + volatile u32 link; /* void * */ + volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ + volatile s32 count; + + volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ + volatile s32 tx_buf_size0; /* Length of Tx frame. */ + volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ + volatile s32 tx_buf_size1; /* Length of Tx frame. */ +}; + +#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ +#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ +#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ +#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ +#define TxCB_CMD_S 0x4000 /* suspend on completion */ +#define TxCB_CMD_EL 0x8000 /* last command block in CBL */ + +#define TxCB_COUNT_MASK 0x3fff +#define TxCB_COUNT_EOF 0x8000 + + /* The Speedo3 Rx and Tx frame/buffer descriptors. + */ +struct descriptor { /* A generic descriptor. */ + volatile u16 status; + volatile u16 command; + volatile u32 link; /* struct descriptor * */ + + unsigned char params[0]; +}; + +#define CFG_CMD_EL 0x8000 +#define CFG_CMD_SUSPEND 0x4000 +#define CFG_CMD_INT 0x2000 +#define CFG_CMD_IAS 0x0001 /* individual address setup */ +#define CFG_CMD_CONFIGURE 0x0002 /* configure */ + +#define CFG_STATUS_C 0x8000 +#define CFG_STATUS_OK 0x2000 + + /* Misc. + */ +#define NUM_RX_DESC PKTBUFSRX +#define NUM_TX_DESC 1 /* Number of TX descriptors */ + +#define TOUT_LOOP 1000000 + +#define ETH_ALEN 6 + +static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ +static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ +static int rx_next; /* RX descriptor ring pointer */ +static int tx_next; /* TX descriptor ring pointer */ +static int tx_threshold; + +/* + * The parameters for a CmdConfigure operation. + * There are so many options that it would be difficult to document + * each bit. We mostly use the default or recommended settings. + */ +static const char i82557_config_cmd[] = { + 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */ + 0, 0x2E, 0, 0x60, 0, + 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */ + 0x3f, 0x05, +}; +static const char i82558_config_cmd[] = { + 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ + 0, 0x2E, 0, 0x60, 0x08, 0x88, + 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ + 0x31, 0x05, +}; + +static void init_rx_ring (struct eth_device *dev); +static void purge_tx_ring (struct eth_device *dev); + +static void read_hw_addr (struct eth_device *dev, bd_t * bis); + +static int eepro100_init (struct eth_device *dev, bd_t * bis); +static int eepro100_send (struct eth_device *dev, volatile void *packet, + int length); +static int eepro100_recv (struct eth_device *dev); +static void eepro100_halt (struct eth_device *dev); + +#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460) +#define bus_to_phys(a) (a) +#define phys_to_bus(a) (a) +#else +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) +#endif + +static inline int INW (struct eth_device *dev, u_long addr) +{ + return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase)); +} + +static inline void OUTW (struct eth_device *dev, int command, u_long addr) +{ + *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command); +} + +static inline void OUTL (struct eth_device *dev, int command, u_long addr) +{ + *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); +} + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +static inline int INL (struct eth_device *dev, u_long addr) +{ + return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); +} + +static int get_phyreg (struct eth_device *dev, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + int cmd; + int timeout = 50; + + /* read requested data */ + cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); + OUTL (dev, cmd, SCBCtrlMDI); + + do { + udelay(1000); + cmd = INL (dev, SCBCtrlMDI); + } while (!(cmd & (1 << 28)) && (--timeout)); + + if (timeout == 0) + return -1; + + *value = (unsigned short) (cmd & 0xffff); + + return 0; +} + +static int set_phyreg (struct eth_device *dev, unsigned char addr, + unsigned char reg, unsigned short value) +{ + int cmd; + int timeout = 50; + + /* write requested data */ + cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); + OUTL (dev, cmd | value, SCBCtrlMDI); + + while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) + udelay(1000); + + if (timeout == 0) + return -1; + + return 0; +} + +/* Check if given phyaddr is valid, i.e. there is a PHY connected. + * Do this by checking model value field from ID2 register. + */ +static struct eth_device* verify_phyaddr (char *devname, unsigned char addr) +{ + struct eth_device *dev; + unsigned short value; + unsigned char model; + + dev = eth_get_dev_by_name(devname); + if (dev == NULL) { + printf("%s: no such device\n", devname); + return NULL; + } + + /* read id2 register */ + if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) { + printf("%s: mii read timeout!\n", devname); + return NULL; + } + + /* get model */ + model = (unsigned char)((value >> 4) & 0x003f); + + if (model == 0) { + printf("%s: no PHY at address %d\n", devname, addr); + return NULL; + } + + return dev; +} + +static int eepro100_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct eth_device *dev; + + dev = verify_phyaddr(devname, addr); + if (dev == NULL) + return -1; + + if (get_phyreg(dev, addr, reg, value) != 0) { + printf("%s: mii read timeout!\n", devname); + return -1; + } + + return 0; +} + +static int eepro100_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct eth_device *dev; + + dev = verify_phyaddr(devname, addr); + if (dev == NULL) + return -1; + + if (set_phyreg(dev, addr, reg, value) != 0) { + printf("%s: mii write timeout!\n", devname); + return -1; + } + + return 0; +} + +#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +/* Wait for the chip get the command. +*/ +static int wait_for_eepro100 (struct eth_device *dev) +{ + int i; + + for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { + if (i >= TOUT_LOOP) { + return 0; + } + } + + return 1; +} + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, + {} +}; + +int eepro100_initialize (bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase, status; + int idx = 0; + + while (1) { + /* Find PCI device + */ + if ((devno = pci_find_devices (supported, idx++)) < 0) { + break; + } + + pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0xf; + +#ifdef DEBUG + printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", + iobase); +#endif + + pci_write_config_dword (devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled. + */ + pci_read_config_dword (devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf ("Error: Can not enable MEM access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_MASTER)) { + printf ("Error: Can not enable Bus Mastering.\n"); + continue; + } + + dev = (struct eth_device *) malloc (sizeof *dev); + + sprintf (dev->name, "i82559#%d", card_number); + dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ + dev->iobase = bus_to_phys (iobase); + dev->init = eepro100_init; + dev->halt = eepro100_halt; + dev->send = eepro100_send; + dev->recv = eepro100_recv; + + eth_register (dev); + +#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + /* register mii command access routines */ + miiphy_register(dev->name, + eepro100_miiphy_read, eepro100_miiphy_write); +#endif + + card_number++; + + /* Set the latency timer for value. + */ + pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); + + udelay (10 * 1000); + + read_hw_addr (dev, bis); + } + + return card_number; +} + + +static int eepro100_init (struct eth_device *dev, bd_t * bis) +{ + int i, status = 0; + int tx_cur; + struct descriptor *ias_cmd, *cfg_cmd; + + /* Reset the ethernet controller + */ + OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); + udelay (20); + + OUTL (dev, I82559_RESET, SCBPort); + udelay (20); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); + + /* Initialize Rx and Tx rings. + */ + init_rx_ring (dev); + purge_tx_ring (dev); + + /* Tell the adapter where the RX ring is located. + */ + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); + OUTW (dev, SCB_M | RUC_START, SCBCmd); + + /* Send the Configure frame */ + tx_cur = tx_next; + tx_next = ((tx_next + 1) % NUM_TX_DESC); + + cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; + cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE)); + cfg_cmd->status = 0; + cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); + + memcpy (cfg_cmd->params, i82558_config_cmd, + sizeof (i82558_config_cmd)); + + if (!wait_for_eepro100 (dev)) { + printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); + OUTW (dev, SCB_M | CU_START, SCBCmd); + + for (i = 0; + !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + printf ("%s: Tx error buffer not ready\n", dev->name); + goto Done; + } + } + + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); + goto Done; + } + + /* Send the Individual Address Setup frame + */ + tx_cur = tx_next; + tx_next = ((tx_next + 1) % NUM_TX_DESC); + + ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; + ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS)); + ias_cmd->status = 0; + ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); + + memcpy (ias_cmd->params, dev->enetaddr, 6); + + /* Tell the adapter where the TX ring is located. + */ + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); + OUTW (dev, SCB_M | CU_START, SCBCmd); + + for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + printf ("%s: Tx error buffer not ready\n", + dev->name); + goto Done; + } + } + + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); + goto Done; + } + + status = 1; + + Done: + return status; +} + +static int eepro100_send (struct eth_device *dev, volatile void *packet, int length) +{ + int i, status = -1; + int tx_cur; + + if (length <= 0) { + printf ("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + tx_cur = tx_next; + tx_next = (tx_next + 1) % NUM_TX_DESC; + + tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | + TxCB_CMD_SF | + TxCB_CMD_S | + TxCB_CMD_EL ); + tx_ring[tx_cur].status = 0; + tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); + tx_ring[tx_cur].link = + cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); + tx_ring[tx_cur].tx_desc_addr = + cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); + tx_ring[tx_cur].tx_buf_addr0 = + cpu_to_le32 (phys_to_bus ((u_long) packet)); + tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); + + if (!wait_for_eepro100 (dev)) { + printf ("%s: Tx error ethernet controller not ready.\n", + dev->name); + goto Done; + } + + /* Send the packet. + */ + OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); + OUTW (dev, SCB_M | CU_START, SCBCmd); + + for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + printf ("%s: Tx error buffer not ready\n", dev->name); + goto Done; + } + } + + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); + goto Done; + } + + status = length; + + Done: + return status; +} + +static int eepro100_recv (struct eth_device *dev) +{ + u16 status, stat; + int rx_prev, length = 0; + + stat = INW (dev, SCBStatus); + OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); + + for (;;) { + status = le16_to_cpu (rx_ring[rx_next].status); + + if (!(status & RFD_STATUS_C)) { + break; + } + + /* Valid frame status. + */ + if ((status & RFD_STATUS_OK)) { + /* A valid frame received. + */ + length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; + + /* Pass the packet up to the protocol + * layers. + */ + NetReceive (rx_ring[rx_next].data, length); + } else { + /* There was an error. + */ + printf ("RX error status = 0x%08X\n", status); + } + + rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); + rx_ring[rx_next].status = 0; + rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); + + rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; + rx_ring[rx_prev].control = 0; + + /* Update entry information. + */ + rx_next = (rx_next + 1) % NUM_RX_DESC; + } + + if (stat & SCB_STATUS_RNR) { + + printf ("%s: Receiver is not ready, restart it !\n", dev->name); + + /* Reinitialize Rx ring. + */ + init_rx_ring (dev); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not restart ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); + OUTW (dev, SCB_M | RUC_START, SCBCmd); + } + + Done: + return length; +} + +static void eepro100_halt (struct eth_device *dev) +{ + /* Reset the ethernet controller + */ + OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); + udelay (20); + + OUTL (dev, I82559_RESET, SCBPort); + udelay (20); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); + + Done: + return; +} + + /* SROM Read. + */ +static int read_eeprom (struct eth_device *dev, int location, int addr_len) +{ + unsigned short retval = 0; + int read_cmd = location | EE_READ_CMD; + int i; + + OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); + OUTW (dev, EE_ENB, SCBeeprom); + + /* Shift the read command bits out. */ + for (i = 12; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + + OUTW (dev, EE_ENB | dataval, SCBeeprom); + udelay (1); + OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay (1); + } + OUTW (dev, EE_ENB, SCBeeprom); + + for (i = 15; i >= 0; i--) { + OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); + udelay (1); + retval = (retval << 1) | + ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); + OUTW (dev, EE_ENB, SCBeeprom); + udelay (1); + } + + /* Terminate the EEPROM access. */ + OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); + return retval; +} + +#ifdef CONFIG_EEPRO100_SROM_WRITE +int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) +{ + unsigned short dataval; + int enable_cmd = 0x3f | EE_EWENB_CMD; + int write_cmd = location | EE_WRITE_CMD; + int i; + unsigned long datalong, tmplong; + + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB, SCBeeprom); + + /* Shift the enable command bits out. */ + for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) + { + dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); + } + + OUTW(dev, EE_ENB, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB, SCBeeprom); + + + /* Shift the write command bits out. */ + for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) + { + dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); + } + + /* Write the data */ + datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); + + for (i = 0; i< EE_DATA_BITS; i++) + { + /* Extract and move data bit to bit DI */ + dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; + + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + + datalong = datalong << 1; /* Adjust significant data bit*/ + } + + /* Finish up command (toggle CS) */ + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + udelay(1); /* delay for more than 250 ns */ + OUTW(dev, EE_ENB, SCBeeprom); + + /* Wait for programming ready (D0 = 1) */ + tmplong = 10; + do + { + dataval = INW(dev, SCBeeprom); + if (dataval & EE_DATA_READ) + break; + udelay(10000); + } + while (-- tmplong); + + if (tmplong == 0) + { + printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); + return -1; + } + + /* Terminate the EEPROM access. */ + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + + return 0; +} +#endif + +static void init_rx_ring (struct eth_device *dev) +{ + int i; + + for (i = 0; i < NUM_RX_DESC; i++) { + rx_ring[i].status = 0; + rx_ring[i].control = + (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; + rx_ring[i].link = + cpu_to_le32 (phys_to_bus + ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); + rx_ring[i].rx_buf_addr = 0xffffffff; + rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); + } + + rx_next = 0; +} + +static void purge_tx_ring (struct eth_device *dev) +{ + int i; + + tx_next = 0; + tx_threshold = 0x01208000; + + for (i = 0; i < NUM_TX_DESC; i++) { + tx_ring[i].status = 0; + tx_ring[i].command = 0; + tx_ring[i].link = 0; + tx_ring[i].tx_desc_addr = 0; + tx_ring[i].count = 0; + + tx_ring[i].tx_buf_addr0 = 0; + tx_ring[i].tx_buf_size0 = 0; + tx_ring[i].tx_buf_addr1 = 0; + tx_ring[i].tx_buf_size1 = 0; + } +} + +static void read_hw_addr (struct eth_device *dev, bd_t * bis) +{ + u16 eeprom[0x40]; + u16 sum = 0; + int i, j; + int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; + + for (j = 0, i = 0; i < 0x40; i++) { + u16 value = read_eeprom (dev, i, addr_len); + + eeprom[i] = value; + sum += value; + if (i < 3) { + dev->enetaddr[j++] = value; + dev->enetaddr[j++] = value >> 8; + } + } + + if (sum != 0xBABA) { + memset (dev->enetaddr, 0, ETH_ALEN); +#ifdef DEBUG + printf ("%s: Invalid EEPROM checksum %#4.4x, " + "check settings before activating this device!\n", + dev->name, sum); +#endif + } +} + +#endif diff --git a/drivers/i8042.c b/drivers/i8042.c new file mode 100644 index 0000000..e21978d --- /dev/null +++ b/drivers/i8042.c @@ -0,0 +1,655 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* i8042.c - Intel 8042 keyboard driver routines */ + +/* includes */ + +#include + +#ifdef CONFIG_I8042_KBD + +#include + +/* defines */ + +#ifdef CONFIG_CONSOLE_CURSOR +extern void console_cursor (int state); +static int blinkCount = CFG_CONSOLE_BLINK_COUNT; +static int cursor_state = 0; +#endif + +/* locals */ + +static int kbd_input = -1; /* no input yet */ +static int kbd_mapping = KBD_US; /* default US keyboard */ +static int kbd_flags = NORMAL; /* after reset */ +static int kbd_state = 0; /* unshift code */ + +static void kbd_conv_char (unsigned char scan_code); +static void kbd_led_set (void); +static void kbd_normal (unsigned char scan_code); +static void kbd_shift (unsigned char scan_code); +static void kbd_ctrl (unsigned char scan_code); +static void kbd_num (unsigned char scan_code); +static void kbd_caps (unsigned char scan_code); +static void kbd_scroll (unsigned char scan_code); +static void kbd_alt (unsigned char scan_code); +static int kbd_input_empty (void); +static int kbd_reset (void); + +static unsigned char kbd_fct_map [144] = + { /* kbd_fct_map table for scan code */ + 0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */ + AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */ + AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */ + AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */ + AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */ + ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */ + ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */ + 0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */ + AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */ + AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */ + }; + +static unsigned char kbd_key_map [2][5][144] = + { + { /* US keyboard */ + { /* unshift code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ + 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ + '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* shift code */ + 0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */ + '&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */ + 'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */ + '"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */ + 'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* control code */ + 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ + 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ + 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ + 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ + 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ + 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ + 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ + 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + }, + { /* non numeric code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ + 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ + '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ + 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ + 'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* right alt mode - not used in US keyboard */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + } + }, + { /* german keyboard */ + { /* unshift code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ + 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ + 0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* shift code */ + 0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */ + '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */ + 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */ + 'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */ + 0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */ + 'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* control code */ + 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ + 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ + 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ + 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ + 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ + 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ + 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ + 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + }, + { /* non numeric code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ + 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ + 0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ + 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ + 'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* Right alt mode - is used in German keyboard */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ + '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */ + '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ + 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ + 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + } + } + }; + +static unsigned char ext_key_map [] = + { + 0x1c, /* keypad enter */ + 0x1d, /* right control */ + 0x35, /* keypad slash */ + 0x37, /* print screen */ + 0x38, /* right alt */ + 0x46, /* break */ + 0x47, /* editpad home */ + 0x48, /* editpad up */ + 0x49, /* editpad pgup */ + 0x4b, /* editpad left */ + 0x4d, /* editpad right */ + 0x4f, /* editpad end */ + 0x50, /* editpad dn */ + 0x51, /* editpad pgdn */ + 0x52, /* editpad ins */ + 0x53, /* editpad del */ + 0x00 /* map end */ + }; + +/******************************************************************************* + * + * i8042_kbd_init - reset keyboard and init state flags + */ +int i8042_kbd_init (void) +{ + int keymap, try; + char *penv; + + /* Init keyboard device (default US layout) */ + keymap = KBD_US; + if ((penv = getenv ("keymap")) != NULL) + { + if (strncmp (penv, "de", 3) == 0) + keymap = KBD_GER; + } + + for (try = 0; try < KBD_RESET_TRIES; try++) + { + if (kbd_reset() == 0) + { + kbd_mapping = keymap; + kbd_flags = NORMAL; + kbd_state = 0; + kbd_led_set(); + return 0; + } + } + return -1; +} + + +/******************************************************************************* + * + * i8042_tstc - test if keyboard input is available + * option: cursor blinking if called in a loop + */ +int i8042_tstc (void) +{ + unsigned char scan_code = 0; + +#ifdef CONFIG_CONSOLE_CURSOR + if (--blinkCount == 0) + { + cursor_state ^= 1; + console_cursor (cursor_state); + blinkCount = CFG_CONSOLE_BLINK_COUNT; + udelay (10); + } +#endif + + if ((in8 (I8042_STATUS_REG) & 0x01) == 0) + return 0; + else + { + scan_code = in8 (I8042_DATA_REG); + if (scan_code == 0xfa) + return 0; + + kbd_conv_char(scan_code); + + if (kbd_input != -1) + return 1; + } + return 0; +} + + +/******************************************************************************* + * + * i8042_getc - wait till keyboard input is available + * option: turn on/off cursor while waiting + */ +int i8042_getc (void) +{ + int ret_chr; + unsigned char scan_code; + + while (kbd_input == -1) + { + while ((in8 (I8042_STATUS_REG) & 0x01) == 0) + { +#ifdef CONFIG_CONSOLE_CURSOR + if (--blinkCount==0) + { + cursor_state ^= 1; + console_cursor (cursor_state); + blinkCount = CFG_CONSOLE_BLINK_COUNT; + } + udelay (10); +#endif + } + + scan_code = in8 (I8042_DATA_REG); + + if (scan_code != 0xfa) + kbd_conv_char (scan_code); + } + ret_chr = kbd_input; + kbd_input = -1; + return ret_chr; +} + + +/******************************************************************************/ + +static void kbd_conv_char (unsigned char scan_code) +{ + if (scan_code == 0xe0) + { + kbd_flags |= EXT; + return; + } + + /* if high bit of scan_code, set break flag */ + if (scan_code & 0x80) + kbd_flags |= BRK; + else + kbd_flags &= ~BRK; + + if ((scan_code == 0xe1) || (kbd_flags & E1)) + { + if (scan_code == 0xe1) + { + kbd_flags ^= BRK; /* reset the break flag */ + kbd_flags ^= E1; /* bitwise EXOR with E1 flag */ + } + return; + } + + scan_code &= 0x7f; + + if (kbd_flags & EXT) + { + int i; + + kbd_flags ^= EXT; + for (i=0; ext_key_map[i]; i++) + { + if (ext_key_map[i] == scan_code) + { + scan_code = 0x80 + i; + break; + } + } + /* not found ? */ + if (!ext_key_map[i]) + return; + } + + switch (kbd_fct_map [scan_code]) + { + case AS: kbd_normal (scan_code); + break; + case SH: kbd_shift (scan_code); + break; + case CN: kbd_ctrl (scan_code); + break; + case NM: kbd_num (scan_code); + break; + case CP: kbd_caps (scan_code); + break; + case ST: kbd_scroll (scan_code); + break; + case AK: kbd_alt (scan_code); + break; + } + return; +} + + +/******************************************************************************/ + +static void kbd_normal (unsigned char scan_code) +{ + unsigned char chr; + + if ((kbd_flags & BRK) == NORMAL) + { + chr = kbd_key_map [kbd_mapping][kbd_state][scan_code]; + if ((chr == 0xff) || (chr == 0x00)) + { + return; + } + + /* if caps lock convert upper to lower */ + if (((kbd_flags & CAPS) == CAPS) && (chr >= 'a' && chr <= 'z')) + { + chr -= 'a' - 'A'; + } + kbd_input = chr; + } +} + + +/******************************************************************************/ + +static void kbd_shift (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == BRK) + { + kbd_state = AS; + kbd_flags &= (~SHIFT); + } + else + { + kbd_state = SH; + kbd_flags |= SHIFT; + } +} + + +/******************************************************************************/ + +static void kbd_ctrl (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == BRK) + { + kbd_state = AS; + kbd_flags &= (~CTRL); + } + else + { + kbd_state = CN; + kbd_flags |= CTRL; + } +} + + +/******************************************************************************/ + +static void kbd_caps (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == NORMAL) + { + kbd_flags ^= CAPS; + kbd_led_set (); /* update keyboard LED */ + } +} + + +/******************************************************************************/ + +static void kbd_num (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == NORMAL) + { + kbd_flags ^= NUM; + kbd_state = (kbd_flags & NUM) ? AS : NM; + kbd_led_set (); /* update keyboard LED */ + } +} + + +/******************************************************************************/ + +static void kbd_scroll (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == NORMAL) + { + kbd_flags ^= STP; + kbd_led_set (); /* update keyboard LED */ + if (kbd_flags & STP) + kbd_input = 0x13; + else + kbd_input = 0x11; + } +} + +/******************************************************************************/ + +static void kbd_alt (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == BRK) + { + kbd_state = AS; + kbd_flags &= (~ALT); + } + else + { + kbd_state = AK; + kbd_flags &= ALT; + } +} + + +/******************************************************************************/ + +static void kbd_led_set (void) +{ + kbd_input_empty(); + out8 (I8042_DATA_REG, 0xed); /* SET LED command */ + kbd_input_empty(); + out8 (I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */ +} + + +/******************************************************************************/ + +static int kbd_input_empty (void) +{ + int kbdTimeout = KBD_TIMEOUT; + + /* wait for input buf empty */ + while ((in8 (I8042_STATUS_REG) & 0x02) && kbdTimeout--) + udelay(1000); + + return kbdTimeout; +} + +/******************************************************************************/ + +static int kbd_reset (void) +{ + if (kbd_input_empty() == 0) + return -1; + + out8 (I8042_DATA_REG, 0xff); + + udelay(250000); + + if (kbd_input_empty() == 0) + return -1; + + out8 (I8042_DATA_REG, 0x60); + + if (kbd_input_empty() == 0) + return -1; + + out8 (I8042_DATA_REG, 0x45); + + + if (kbd_input_empty() == 0) + return -1; + + out8 (I8042_COMMAND_REG, 0xae); + + if (kbd_input_empty() == 0) + return -1; + + return 0; +} + +#endif /* CONFIG_I8042_KBD */ diff --git a/drivers/i82365.c b/drivers/i82365.c new file mode 100644 index 0000000..a40fcf4 --- /dev/null +++ b/drivers/i82365.c @@ -0,0 +1,1014 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * + * Lots of code copied from: + * + * i82365.c 1.352 - Linux driver for Intel 82365 and compatible + * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers. + * (C) 1999 David A. Hinds + */ + +#include + +#ifdef CONFIG_I82365 + +#include +#include +#include +#include + +#include +#include +#include +#ifdef CONFIG_CPC45 +#include +#else +#include +#endif + +static struct pci_device_id supported[] = { +#ifdef CONFIG_CPC45 + {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729}, +#else + {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510}, +#endif + {0, 0} +}; + +#define CYCLE_TIME 120 + +#ifdef CONFIG_CPC45 +extern int SPD67290Init (void); +#endif + +#ifdef DEBUG +static void i82365_dump_regions (pci_dev_t dev); +#endif + +typedef struct socket_info_t { + pci_dev_t dev; + u_short bcr; + u_char pci_lat, cb_lat, sub_bus, cache; + u_int cb_phys; + + socket_cap_t cap; + u_short type; + u_int flags; +#ifdef CONFIG_CPC45 + cirrus_state_t c_state; +#else + ti113x_state_t state; +#endif +} socket_info_t; + +#ifdef CONFIG_CPC45 +/* These definitions must match the pcic table! */ +typedef enum pcic_id { + IS_PD6710, IS_PD672X, IS_VT83C469 +} pcic_id; + +typedef struct pcic_t { + char *name; +} pcic_t; + +static pcic_t pcic[] = { + {" Cirrus PD6710: "}, + {" Cirrus PD672x: "}, + {" VIA VT83C469: "}, +}; +#endif + +static socket_info_t socket; +static socket_state_t state; +static struct pccard_mem_map mem; +static struct pccard_io_map io; + +/*====================================================================*/ + +/* Some PCI shortcuts */ + +static int pci_readb (socket_info_t * s, int r, u_char * v) +{ + return pci_read_config_byte (s->dev, r, v); +} +static int pci_writeb (socket_info_t * s, int r, u_char v) +{ + return pci_write_config_byte (s->dev, r, v); +} +static int pci_readw (socket_info_t * s, int r, u_short * v) +{ + return pci_read_config_word (s->dev, r, v); +} +static int pci_writew (socket_info_t * s, int r, u_short v) +{ + return pci_write_config_word (s->dev, r, v); +} +#ifndef CONFIG_CPC45 +static int pci_readl (socket_info_t * s, int r, u_int * v) +{ + return pci_read_config_dword (s->dev, r, v); +} +static int pci_writel (socket_info_t * s, int r, u_int v) +{ + return pci_write_config_dword (s->dev, r, v); +} +#endif /* !CONFIG_CPC45 */ + +/*====================================================================*/ + +#ifdef CONFIG_CPC45 + +#define cb_readb(s) readb((s)->cb_phys + 1) +#define cb_writeb(s, v) writeb(v, (s)->cb_phys) +#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1) +#define cb_readl(s, r) readl((s)->cb_phys + (r)) +#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) + + +static u_char i365_get (socket_info_t * s, u_short reg) +{ + u_char val; +#ifdef CONFIG_PCMCIA_SLOT_A + int slot = 0; +#else + int slot = 1; +#endif + + val = I365_REG (slot, reg); + + cb_writeb (s, val); + val = cb_readb (s); + + debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val); + return val; +} + +static void i365_set (socket_info_t * s, u_short reg, u_char data) +{ +#ifdef CONFIG_PCMCIA_SLOT_A + int slot = 0; +#else + int slot = 1; +#endif + u_char val; + + val = I365_REG (slot, reg); + + cb_writeb (s, val); + cb_writeb2 (s, data); + + debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data); +} + +#else /* ! CONFIG_CPC45 */ + +#define cb_readb(s, r) readb((s)->cb_phys + (r)) +#define cb_readl(s, r) readl((s)->cb_phys + (r)) +#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r)) +#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) + +static u_char i365_get (socket_info_t * s, u_short reg) +{ + return cb_readb (s, 0x0800 + reg); +} + +static void i365_set (socket_info_t * s, u_short reg, u_char data) +{ + cb_writeb (s, 0x0800 + reg, data); +} +#endif /* CONFIG_CPC45 */ + +static void i365_bset (socket_info_t * s, u_short reg, u_char mask) +{ + i365_set (s, reg, i365_get (s, reg) | mask); +} + +static void i365_bclr (socket_info_t * s, u_short reg, u_char mask) +{ + i365_set (s, reg, i365_get (s, reg) & ~mask); +} + +#if 0 /* not used */ +static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b) +{ + u_char d = i365_get (s, reg); + + i365_set (s, reg, (b) ? (d | mask) : (d & ~mask)); +} + +static u_short i365_get_pair (socket_info_t * s, u_short reg) +{ + return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8)); +} +#endif /* not used */ + +static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) +{ + i365_set (s, reg, data & 0xff); + i365_set (s, reg + 1, data >> 8); +} + +#ifdef CONFIG_CPC45 +/*====================================================================== + + Code to save and restore global state information for Cirrus + PD67xx controllers, and to set and report global configuration + options. + +======================================================================*/ + +#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b)))) + +static void cirrus_get_state (socket_info_t * s) +{ + int i; + cirrus_state_t *p = &s->c_state; + + p->misc1 = i365_get (s, PD67_MISC_CTL_1); + p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); + p->misc2 = i365_get (s, PD67_MISC_CTL_2); + for (i = 0; i < 6; i++) + p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i); + +} + +static void cirrus_set_state (socket_info_t * s) +{ + int i; + u_char misc; + cirrus_state_t *p = &s->c_state; + + misc = i365_get (s, PD67_MISC_CTL_2); + i365_set (s, PD67_MISC_CTL_2, p->misc2); + if (misc & PD67_MC2_SUSPEND) + udelay (50000); + misc = i365_get (s, PD67_MISC_CTL_1); + misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); + i365_set (s, PD67_MISC_CTL_1, misc | p->misc1); + for (i = 0; i < 6; i++) + i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]); +} + +static u_int cirrus_set_opts (socket_info_t * s) +{ + cirrus_state_t *p = &s->c_state; + u_int mask = 0xffff; +#if DEBUG + char buf[200]; + + memset (buf, 0, 200); +#endif + + if (has_ring == -1) + has_ring = 1; + flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring); + flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode); +#if DEBUG + if (p->misc2 & PD67_MC2_IRQ15_RI) + strcat (buf, " [ring]"); + if (p->misc2 & PD67_MC2_DYNAMIC_MODE) + strcat (buf, " [dyn mode]"); + if (p->misc1 & PD67_MC1_INPACK_ENA) + strcat (buf, " [inpack]"); +#endif + + if (p->misc2 & PD67_MC2_IRQ15_RI) + mask &= ~0x8000; + if (has_led > 0) { +#if DEBUG + strcat (buf, " [led]"); +#endif + mask &= ~0x1000; + } + if (has_dma > 0) { +#if DEBUG + strcat (buf, " [dma]"); +#endif + mask &= ~0x0600; + flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass); +#if DEBUG + if (p->misc2 & PD67_MC2_FREQ_BYPASS) + strcat (buf, " [freq bypass]"); +#endif + } + + if (setup_time >= 0) + p->timer[0] = p->timer[3] = setup_time; + if (cmd_time > 0) { + p->timer[1] = cmd_time; + p->timer[4] = cmd_time * 2 + 4; + } + if (p->timer[1] == 0) { + p->timer[1] = 6; + p->timer[4] = 16; + if (p->timer[0] == 0) + p->timer[0] = p->timer[3] = 1; + } + if (recov_time >= 0) + p->timer[2] = p->timer[5] = recov_time; + + debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n", + buf, + p->timer[0], p->timer[1], p->timer[2], + p->timer[3], p->timer[4], p->timer[5]); + + return mask; +} + +#else /* !CONFIG_CPC45 */ + +/*====================================================================== + + Code to save and restore global state information for TI 1130 and + TI 1131 controllers, and to set and report global configuration + options. + +======================================================================*/ + +static void ti113x_get_state (socket_info_t * s) +{ + ti113x_state_t *p = &s->state; + + pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl); + pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl); + pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl); + pci_readb (s, TI1250_DIAGNOSTIC, &p->diag); + pci_readl (s, TI12XX_IRQMUX, &p->irqmux); +} + +static void ti113x_set_state (socket_info_t * s) +{ + ti113x_state_t *p = &s->state; + + pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl); + pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl); + pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl); + pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0); + pci_writeb (s, TI1250_DIAGNOSTIC, p->diag); + pci_writel (s, TI12XX_IRQMUX, p->irqmux); + i365_set_pair (s, TI113X_IO_OFFSET (0), 0); + i365_set_pair (s, TI113X_IO_OFFSET (1), 0); +} + +static u_int ti113x_set_opts (socket_info_t * s) +{ + ti113x_state_t *p = &s->state; + u_int mask = 0xffff; + + p->cardctl &= ~TI113X_CCR_ZVENABLE; + p->cardctl |= TI113X_CCR_SPKROUTEN; + + return mask; +} +#endif /* CONFIG_CPC45 */ + +/*====================================================================== + + Routines to handle common CardBus options + +======================================================================*/ + +/* Default settings for PCI command configuration register */ +#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ + PCI_COMMAND_MASTER|PCI_COMMAND_WAIT) + +static void cb_get_state (socket_info_t * s) +{ + pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache); + pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat); + pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat); + pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus); + pci_readb (s, CB_SUBORD_BUS, &s->sub_bus); + pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr); +} + +static void cb_set_state (socket_info_t * s) +{ +#ifndef CONFIG_CPC45 + pci_writel (s, CB_LEGACY_MODE_BASE, 0); + pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys); +#endif + pci_writew (s, PCI_COMMAND, CMD_DFLT); + pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache); + pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat); + pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat); + pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus); + pci_writeb (s, CB_SUBORD_BUS, s->sub_bus); + pci_writew (s, CB_BRIDGE_CONTROL, s->bcr); +} + +static void cb_set_opts (socket_info_t * s) +{ +#ifndef CONFIG_CPC45 + if (s->cache == 0) + s->cache = 8; + if (s->pci_lat == 0) + s->pci_lat = 0xa8; + if (s->cb_lat == 0) + s->cb_lat = 0xb0; +#endif +} + +/*====================================================================== + + Power control for Cardbus controllers: used both for 16-bit and + Cardbus cards. + +======================================================================*/ + +static int cb_set_power (socket_info_t * s, socket_state_t * state) +{ + u_int reg = 0; + +#ifdef CONFIG_CPC45 + + reg = I365_PWR_NORESET; + if (state->flags & SS_PWR_AUTO) + reg |= I365_PWR_AUTO; + if (state->flags & SS_OUTPUT_ENA) + reg |= I365_PWR_OUT; + if (state->Vpp != 0) { + if (state->Vpp == 120) { + reg |= I365_VPP1_12V; + puts (" 12V card found: "); + } else if (state->Vpp == state->Vcc) { + reg |= I365_VPP1_5V; + } else { + puts (" power not found: "); + return -1; + } + } + if (state->Vcc != 0) { + reg |= I365_VCC_5V; + if (state->Vcc == 33) { + puts (" 3.3V card found: "); + i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } else if (state->Vcc == 50) { + puts (" 5V card found: "); + i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } else { + puts (" power not found: "); + return -1; + } + } + + if (reg != i365_get (s, I365_POWER)) { + reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V); + i365_set (s, I365_POWER, reg); + } + +#else /* ! CONFIG_CPC45 */ + + /* restart card voltage detection if it seems appropriate */ + if ((state->Vcc == 0) && (state->Vpp == 0) && + !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE)) + cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST); + switch (state->Vcc) { + case 0: + reg = 0; + break; + case 33: + reg = CB_SC_VCC_3V; + break; + case 50: + reg = CB_SC_VCC_5V; + break; + default: + return -1; + } + switch (state->Vpp) { + case 0: + break; + case 33: + reg |= CB_SC_VPP_3V; + break; + case 50: + reg |= CB_SC_VPP_5V; + break; + case 120: + reg |= CB_SC_VPP_12V; + break; + default: + return -1; + } + if (reg != cb_readl (s, CB_SOCKET_CONTROL)) + cb_writel (s, CB_SOCKET_CONTROL, reg); +#endif /* CONFIG_CPC45 */ + return 0; +} + +/*====================================================================== + + Generic routines to get and set controller options + +======================================================================*/ + +static void get_bridge_state (socket_info_t * s) +{ +#ifdef CONFIG_CPC45 + cirrus_get_state (s); +#else + ti113x_get_state (s); +#endif + cb_get_state (s); +} + +static void set_bridge_state (socket_info_t * s) +{ + cb_set_state (s); + i365_set (s, I365_GBLCTL, 0x00); + i365_set (s, I365_GENCTL, 0x00); +#ifdef CONFIG_CPC45 + cirrus_set_state (s); +#else + ti113x_set_state (s); +#endif +} + +static void set_bridge_opts (socket_info_t * s) +{ +#ifdef CONFIG_CPC45 + cirrus_set_opts (s); +#else + ti113x_set_opts (s); +#endif + cb_set_opts (s); +} + +/*====================================================================*/ +#define PD67_EXT_INDEX 0x2e /* Extension index */ +#define PD67_EXT_DATA 0x2f /* Extension data */ +#define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) + +#define pd67_ext_get(s, r) \ + (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) + +static int i365_get_status (socket_info_t * s, u_int * value) +{ + u_int status; +#ifdef CONFIG_CPC45 + u_char val; + u_char power, vcc, vpp; + u_int powerstate; +#endif + + status = i365_get (s, I365_IDENT); + status = i365_get (s, I365_STATUS); + *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; + if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) { + *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; + } else { + *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; + *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; + } + *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; + *value |= (status & I365_CS_READY) ? SS_READY : 0; + *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; + +#ifdef CONFIG_CPC45 + /* Check for Cirrus CL-PD67xx chips */ + i365_set (s, PD67_CHIP_INFO, 0); + val = i365_get (s, PD67_CHIP_INFO); + s->type = -1; + if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { + val = i365_get (s, PD67_CHIP_INFO); + if ((val & PD67_INFO_CHIP_ID) == 0) { + s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; + i365_set (s, PD67_EXT_INDEX, 0xe5); + if (i365_get (s, PD67_EXT_INDEX) != 0xe5) + s->type = IS_VT83C469; + } + } else { + printf ("no Cirrus Chip found\n"); + *value = 0; + return -1; + } + + power = i365_get (s, I365_POWER); + state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0; + state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0; + vcc = power & I365_VCC_MASK; + vpp = power & I365_VPP1_MASK; + state.Vcc = state.Vpp = 0; + if((vcc== 0) || (vpp == 0)) { + /* + * On the Cirrus we get the info which card voltage + * we have in EXTERN DATA and write it to MISC_CTL1 + */ + powerstate = pd67_ext_get(s, PD67_EXTERN_DATA); + if (powerstate & PD67_EXD_VS1(0)) { + /* 5V Card */ + i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } else { + /* 3.3V Card */ + i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } + i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V)); + power = i365_get (s, I365_POWER); + } + if (power & I365_VCC_5V) { + state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50; + } + + if (power == I365_VPP1_12V) + state.Vpp = 120; + + /* IO card, RESET flags, IO interrupt */ + power = i365_get (s, I365_INTCTL); + state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET; + if (power & I365_PC_IOCARD) + state.flags |= SS_IOCARD; + state.io_irq = power & I365_IRQ_MASK; + + /* Card status change mask */ + power = i365_get (s, I365_CSCINT); + state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0; + if (state.flags & SS_IOCARD) + state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0; + else { + state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0; + state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0; + state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0; + } + debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, " + "io_irq %d, csc_mask %#2.2x\n", state.flags, + state.Vcc, state.Vpp, state.io_irq, state.csc_mask); + +#else /* !CONFIG_CPC45 */ + + status = cb_readl (s, CB_SOCKET_STATE); + *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0; + *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0; + *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0; + *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING; + /* For now, ignore cards with unsupported voltage keys */ + if (*value & SS_XVCARD) + *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD); +#endif /* CONFIG_CPC45 */ + return 0; +} /* i365_get_status */ + +static int i365_set_socket (socket_info_t * s, socket_state_t * state) +{ + u_char reg; + + set_bridge_state (s); + + /* IO card, RESET flag */ + reg = 0; + reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; + reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; + i365_set (s, I365_INTCTL, reg); + +#ifdef CONFIG_CPC45 + cb_set_power (s, state); + +#if 0 + /* Card status change interrupt mask */ + reg = s->cs_irq << 4; + if (state->csc_mask & SS_DETECT) + reg |= I365_CSC_DETECT; + if (state->flags & SS_IOCARD) { + if (state->csc_mask & SS_STSCHG) + reg |= I365_CSC_STSCHG; + } else { + if (state->csc_mask & SS_BATDEAD) + reg |= I365_CSC_BVD1; + if (state->csc_mask & SS_BATWARN) + reg |= I365_CSC_BVD2; + if (state->csc_mask & SS_READY) + reg |= I365_CSC_READY; + } + i365_set (s, I365_CSCINT, reg); + i365_get (s, I365_CSC); +#endif /* 0 */ + +#else /* !CONFIG_CPC45 */ + + reg = I365_PWR_NORESET; + if (state->flags & SS_PWR_AUTO) + reg |= I365_PWR_AUTO; + if (state->flags & SS_OUTPUT_ENA) + reg |= I365_PWR_OUT; + + cb_set_power (s, state); + reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK); + + if (reg != i365_get (s, I365_POWER)) + i365_set (s, I365_POWER, reg); +#endif /* CONFIG_CPC45 */ + + return 0; +} /* i365_set_socket */ + +/*====================================================================*/ + +static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem) +{ + u_short base, i; + u_char map; + + debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n", + mem->map, mem->flags, mem->speed, + mem->sys_start, mem->sys_stop, mem->card_start); + + map = mem->map; + if ((map > 4) || + (mem->card_start > 0x3ffffff) || + (mem->sys_start > mem->sys_stop) || + (mem->speed > 1000)) { + return -1; + } + + /* Turn off the window before changing anything */ + if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map)) + i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map)); + + /* Take care of high byte, for PCI controllers */ + i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24); + + base = I365_MEM (map); + i = (mem->sys_start >> 12) & 0x0fff; + if (mem->flags & MAP_16BIT) + i |= I365_MEM_16BIT; + if (mem->flags & MAP_0WS) + i |= I365_MEM_0WS; + i365_set_pair (s, base + I365_W_START, i); + + i = (mem->sys_stop >> 12) & 0x0fff; + switch (mem->speed / CYCLE_TIME) { + case 0: + break; + case 1: + i |= I365_MEM_WS0; + break; + case 2: + i |= I365_MEM_WS1; + break; + default: + i |= I365_MEM_WS1 | I365_MEM_WS0; + break; + } + i365_set_pair (s, base + I365_W_STOP, i); + +#ifdef CONFIG_CPC45 + i = 0; +#else + i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff; +#endif + if (mem->flags & MAP_WRPROT) + i |= I365_MEM_WRPROT; + if (mem->flags & MAP_ATTRIB) + i |= I365_MEM_REG; + i365_set_pair (s, base + I365_W_OFF, i); + +#ifdef CONFIG_CPC45 + /* set System Memory map Upper Adress */ + i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map)); + i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff)); +#endif + + /* Turn on the window if necessary */ + if (mem->flags & MAP_ACTIVE) + i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map)); + return 0; +} /* i365_set_mem_map */ + +static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io) +{ + u_char map, ioctl; + + map = io->map; + /* comment out: comparison is always false due to limited range of data type */ + if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */ + (io->stop < io->start)) + return -1; + /* Turn off the window before changing anything */ + if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map)) + i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map)); + i365_set_pair (s, I365_IO (map) + I365_W_START, io->start); + i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop); + ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map); + if (io->speed) + ioctl |= I365_IOCTL_WAIT (map); + if (io->flags & MAP_0WS) + ioctl |= I365_IOCTL_0WS (map); + if (io->flags & MAP_16BIT) + ioctl |= I365_IOCTL_16BIT (map); + if (io->flags & MAP_AUTOSZ) + ioctl |= I365_IOCTL_IOCS16 (map); + i365_set (s, I365_IOCTL, ioctl); + /* Turn on the window if necessary */ + if (io->flags & MAP_ACTIVE) + i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map)); + return 0; +} /* i365_set_io_map */ + +/*====================================================================*/ + +int i82365_init (void) +{ + u_int val; + int i; + +#ifdef CONFIG_CPC45 + if (SPD67290Init () != 0) + return 1; +#endif + if ((socket.dev = pci_find_devices (supported, 0)) < 0) { + /* Controller not found */ + return 1; + } + debug ("i82365 Device Found!\n"); + + pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys); + socket.cb_phys &= ~0xf; + +#ifdef CONFIG_CPC45 + /* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */ + socket.cb_phys += 0xfe000000; +#endif + + get_bridge_state (&socket); + set_bridge_opts (&socket); + + i = i365_get_status (&socket, &val); + +#ifdef CONFIG_CPC45 + if (i > -1) { + puts (pcic[socket.type].name); + } else { + printf ("i82365: Controller not found.\n"); + return 1; + } + if((val & SS_DETECT) != SS_DETECT){ + puts ("No card\n"); + return 1; + } +#else /* !CONFIG_CPC45 */ + if (val & SS_DETECT) { + if (val & SS_3VCARD) { + state.Vcc = state.Vpp = 33; + puts (" 3.3V card found: "); + } else if (!(val & SS_XVCARD)) { + state.Vcc = state.Vpp = 50; + puts (" 5.0V card found: "); + } else { + puts ("i82365: unsupported voltage key\n"); + state.Vcc = state.Vpp = 0; + } + } else { + /* No card inserted */ + puts ("No card\n"); + return 1; + } +#endif /* CONFIG_CPC45 */ + +#ifdef CONFIG_CPC45 + state.flags |= SS_OUTPUT_ENA; +#else + state.flags = SS_IOCARD | SS_OUTPUT_ENA; + state.csc_mask = 0; + state.io_irq = 0; +#endif + + i365_set_socket (&socket, &state); + + for (i = 500; i; i--) { + if ((i365_get (&socket, I365_STATUS) & I365_CS_READY)) + break; + udelay (1000); + } + + if (i == 0) { + /* PC Card not ready for data transfer */ + puts ("i82365 PC Card not ready for data transfer\n"); + return 1; + } + debug (" PC Card ready for data transfer: "); + + mem.map = 0; + mem.flags = MAP_ATTRIB | MAP_ACTIVE; + mem.speed = 300; + mem.sys_start = CFG_PCMCIA_MEM_ADDR; + mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1; + mem.card_start = 0; + i365_set_mem_map (&socket, &mem); + +#ifdef CONFIG_CPC45 + mem.map = 1; + mem.flags = MAP_ACTIVE; + mem.speed = 300; + mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE; + mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1; + mem.card_start = 0; + i365_set_mem_map (&socket, &mem); + +#else /* !CONFIG_CPC45 */ + + io.map = 0; + io.flags = MAP_AUTOSZ | MAP_ACTIVE; + io.speed = 0; + io.start = 0x0100; + io.stop = 0x010F; + i365_set_io_map (&socket, &io); + +#endif /* CONFIG_CPC45 */ + +#ifdef DEBUG + i82365_dump_regions (socket.dev); +#endif + + return 0; +} + +void i82365_exit (void) +{ + io.map = 0; + io.flags = 0; + io.speed = 0; + io.start = 0; + io.stop = 0x1; + + i365_set_io_map (&socket, &io); + + mem.map = 0; + mem.flags = 0; + mem.speed = 0; + mem.sys_start = 0; + mem.sys_stop = 0x1000; + mem.card_start = 0; + + i365_set_mem_map (&socket, &mem); + +#ifdef CONFIG_CPC45 + mem.map = 1; + mem.flags = 0; + mem.speed = 0; + mem.sys_start = 0; + mem.sys_stop = 0x1000; + mem.card_start = 0; + + i365_set_mem_map (&socket, &mem); +#else /* !CONFIG_CPC45 */ + socket.state.sysctl &= 0xFFFF00FF; +#endif + state.Vcc = state.Vpp = 0; + + i365_set_socket (&socket, &state); +} + +/*====================================================================== + + Debug stuff + +======================================================================*/ + +#ifdef DEBUG +static void i82365_dump_regions (pci_dev_t dev) +{ + u_int tmp[2]; + u_int *mem = (void *) socket.cb_phys; + u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR; + u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET); + + pci_read_config_dword (dev, 0x00, tmp + 0); + pci_read_config_dword (dev, 0x80, tmp + 1); + + printf ("PCI CONF: %08X ... %08X\n", + tmp[0], tmp[1]); + printf ("PCI MEM: ... %08X ... %08X\n", + mem[0x8 / 4], mem[0x800 / 4]); + printf ("CIS: ...%c%c%c%c%c%c%c%c...\n", + cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e], + cis[0x40], cis[0x42], cis[0x44], cis[0x48]); + printf ("CIS CONF: %02X %02X %02X ...\n", + cis[0x200], cis[0x202], cis[0x204]); + printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n", + ide[0], ide[1], ide[2], ide[3], + ide[4], ide[5], ide[6], ide[7]); +} +#endif /* DEBUG */ + +#endif /* CONFIG_I82365 */ diff --git a/drivers/inca-ip_sw.c b/drivers/inca-ip_sw.c new file mode 100644 index 0000000..ab22b4d --- /dev/null +++ b/drivers/inca-ip_sw.c @@ -0,0 +1,817 @@ +/* + * INCA-IP internal switch ethernet driver. + * + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_INCA_IP_SWITCH) + +#include +#include +#include +#include + + +#define NUM_RX_DESC PKTBUFSRX +#define NUM_TX_DESC 3 +#define TOUT_LOOP 1000000 + + +#define DELAY udelay(10000) + /* Sometimes the store word instruction hangs while writing to one + * of the Switch registers. Moving the instruction into a separate + * function somehow makes the problem go away. + */ +static void SWORD(volatile u32 * reg, u32 value) +{ + *reg = value; +} + +#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value; +#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) +#define SW_WRITE_REG(reg, value) \ + SWORD(reg, value);\ + DELAY;\ + SWORD(reg, value); + +#define SW_READ_REG(reg, value) \ + value = (u32)*((volatile u32*)reg);\ + DELAY;\ + value = (u32)*((volatile u32*)reg); + +#define INCA_DMA_TX_POLLING_TIME 0x07 +#define INCA_DMA_RX_POLLING_TIME 0x07 + +#define INCA_DMA_TX_HOLD 0x80000000 +#define INCA_DMA_TX_EOP 0x40000000 +#define INCA_DMA_TX_SOP 0x20000000 +#define INCA_DMA_TX_ICPT 0x10000000 +#define INCA_DMA_TX_IEOP 0x08000000 + +#define INCA_DMA_RX_C 0x80000000 +#define INCA_DMA_RX_SOP 0x40000000 +#define INCA_DMA_RX_EOP 0x20000000 + +#define INCA_SWITCH_PHY_SPEED_10H 0x1 +#define INCA_SWITCH_PHY_SPEED_10F 0x5 +#define INCA_SWITCH_PHY_SPEED_100H 0x2 +#define INCA_SWITCH_PHY_SPEED_100F 0x6 + +/************************ Auto MDIX settings ************************/ +#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR +#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL +#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT +#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16 + +#define WAIT_SIGNAL_RETRIES 100 +#define WAIT_LINK_RETRIES 100 +#define LINK_RETRY_DELAY 2000 /* ms */ +/********************************************************************/ + +typedef struct +{ + union { + struct { + volatile u32 HOLD :1; + volatile u32 ICpt :1; + volatile u32 IEop :1; + volatile u32 offset :3; + volatile u32 reserved0 :4; + volatile u32 NFB :22; + }field; + + volatile u32 word; + }params; + + volatile u32 nextRxDescPtr; + + volatile u32 RxDataPtr; + + union { + struct { + volatile u32 C :1; + volatile u32 Sop :1; + volatile u32 Eop :1; + volatile u32 reserved3 :12; + volatile u32 NBT :17; + }field; + + volatile u32 word; + }status; + +} inca_rx_descriptor_t; + + +typedef struct +{ + union { + struct { + volatile u32 HOLD :1; + volatile u32 Eop :1; + volatile u32 Sop :1; + volatile u32 ICpt :1; + volatile u32 IEop :1; + volatile u32 reserved0 :5; + volatile u32 NBA :22; + }field; + + volatile u32 word; + }params; + + volatile u32 nextTxDescPtr; + + volatile u32 TxDataPtr; + + volatile u32 C :1; + volatile u32 reserved3 :31; + +} inca_tx_descriptor_t; + + +static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16))); +static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16))); + +static int tx_new, rx_new, tx_hold, rx_hold; +static int tx_old_hold = -1; +static int initialized = 0; + + +static int inca_switch_init(struct eth_device *dev, bd_t * bis); +static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length); +static int inca_switch_recv(struct eth_device *dev); +static void inca_switch_halt(struct eth_device *dev); +static void inca_init_switch_chip(void); +static void inca_dma_init(void); +static int inca_amdix(void); + + +int inca_switch_initialize(bd_t * bis) +{ + struct eth_device *dev; + +#if 0 + printf("Entered inca_switch_initialize()\n"); +#endif + + if (!(dev = (struct eth_device *) malloc (sizeof *dev))) { + printf("Failed to allocate memory\n"); + return 0; + } + memset(dev, 0, sizeof(*dev)); + + inca_dma_init(); + + inca_init_switch_chip(); + +#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) + inca_amdix(); +#endif + + sprintf(dev->name, "INCA-IP Switch"); + dev->init = inca_switch_init; + dev->halt = inca_switch_halt; + dev->send = inca_switch_send; + dev->recv = inca_switch_recv; + + eth_register(dev); + +#if 0 + printf("Leaving inca_switch_initialize()\n"); +#endif + + return 1; +} + + +static int inca_switch_init(struct eth_device *dev, bd_t * bis) +{ + int i; + u32 v, regValue; + u16 wTmp; + +#if 0 + printf("Entering inca_switch_init()\n"); +#endif + + /* Set MAC address. + */ + wTmp = (u16)dev->enetaddr[0]; + regValue = (wTmp << 8) | dev->enetaddr[1]; + + SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue); + + wTmp = (u16)dev->enetaddr[2]; + regValue = (wTmp << 8) | dev->enetaddr[3]; + regValue = regValue << 16; + wTmp = (u16)dev->enetaddr[4]; + regValue |= (wTmp<<8) | dev->enetaddr[5]; + + SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue); + + /* Initialize the descriptor rings. + */ + for (i = 0; i < NUM_RX_DESC; i++) { + inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]); + memset(rx_desc, 0, sizeof(rx_ring[i])); + + /* Set maximum size of receive buffer. + */ + rx_desc->params.field.NFB = PKTSIZE_ALIGN; + + /* Set the offset of the receive buffer. Zero means + * that the offset mechanism is not used. + */ + rx_desc->params.field.offset = 0; + + /* Check if it is the last descriptor. + */ + if (i == (NUM_RX_DESC - 1)) { + /* Let the last descriptor point to the first + * one. + */ + rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring); + } else { + /* Set the address of the next descriptor. + */ + rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]); + } + + rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]); + } + +#if 0 + printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]); + printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]); +#endif + + for (i = 0; i < NUM_TX_DESC; i++) { + inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]); + + memset(tx_desc, 0, sizeof(tx_ring[i])); + + tx_desc->params.word = 0; + tx_desc->params.field.HOLD = 1; + tx_desc->C = 1; + + /* Check if it is the last descriptor. + */ + if (i == (NUM_TX_DESC - 1)) { + /* Let the last descriptor point to the + * first one. + */ + tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring); + } else { + /* Set the address of the next descriptor. + */ + tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]); + } + } + + /* Initialize RxDMA. + */ + DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v); +#if 0 + printf("RX status = 0x%08X\n", v); +#endif + + /* Writing to the FRDA of CHANNEL. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring); + + /* Writing to the COMMAND REG. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT); + + /* Initialize TxDMA. + */ + DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v); +#if 0 + printf("TX status = 0x%08X\n", v); +#endif + + /* Writing to the FRDA of CHANNEL. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring); + + tx_new = rx_new = 0; + + tx_hold = NUM_TX_DESC - 1; + rx_hold = NUM_RX_DESC - 1; + +#if 0 + rx_ring[rx_hold].params.field.HOLD = 1; +#endif + /* enable spanning tree forwarding, enable the CPU port */ + /* ST_PT: + * CPS (CPU port status) 0x3 (forwarding) + * LPS (LAN port status) 0x3 (forwarding) + * PPS (PC port status) 0x3 (forwarding) + */ + SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f); + +#if 0 + printf("Leaving inca_switch_init()\n"); +#endif + + return 0; +} + + +static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length) +{ + int i; + int res = -1; + u32 command; + u32 regValue; + inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]); + +#if 0 + printf("Entered inca_switch_send()\n"); +#endif + + if (length <= 0) { + printf ("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + for(i = 0; tx_desc->C == 0; i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx error buffer not ready\n", dev->name); + goto Done; + } + } + + if (tx_old_hold >= 0) { + KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1; + } + tx_old_hold = tx_hold; + + tx_desc->params.word = + (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD); + + tx_desc->C = 0; + tx_desc->TxDataPtr = (u32)packet; + tx_desc->params.field.NBA = length; + + KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0; + + tx_hold = tx_new; + tx_new = (tx_new + 1) % NUM_TX_DESC; + + + if (! initialized) { + command = INCA_IP_DMA_DMA_TXCCR0_INIT; + initialized = 1; + } else { + command = INCA_IP_DMA_DMA_TXCCR0_HR; + } + + DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); + regValue |= command; +#if 0 + printf("regValue = 0x%x\n", regValue); +#endif + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); + +#if 1 + for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx buffer not ready\n", dev->name); + goto Done; + } + } +#endif + res = length; +Done: +#if 0 + printf("Leaving inca_switch_send()\n"); +#endif + return res; +} + + +static int inca_switch_recv(struct eth_device *dev) +{ + int length = 0; + inca_rx_descriptor_t * rx_desc; + +#if 0 + printf("Entered inca_switch_recv()\n"); +#endif + + for (;;) { + rx_desc = KSEG1ADDR(&rx_ring[rx_new]); + + if (rx_desc->status.field.C == 0) { + break; + } + +#if 0 + rx_ring[rx_new].params.field.HOLD = 1; +#endif + + if (! rx_desc->status.field.Eop) { + printf("Partly received packet!!!\n"); + break; + } + + length = rx_desc->status.field.NBT; + rx_desc->status.word &= + ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C); +#if 0 +{ + int i; + for (i=0;iparams.field.HOLD = 0; + + rx_hold = rx_new; + + rx_new = (rx_new + 1) % NUM_RX_DESC; + } + +#if 0 + printf("Leaving inca_switch_recv()\n"); +#endif + + return length; +} + + +static void inca_switch_halt(struct eth_device *dev) +{ +#if 0 + printf("Entered inca_switch_halt()\n"); +#endif + +#if 1 + initialized = 0; +#endif +#if 1 + /* Disable forwarding to the CPU port. + */ + SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); + + /* Close RxDMA channel. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); + + /* Close TxDMA channel. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF); + + +#endif +#if 0 + printf("Leaving inca_switch_halt()\n"); +#endif +} + + +static void inca_init_switch_chip(void) +{ + u32 regValue; + + /* To workaround a problem with collision counter + * (see Errata sheet). + */ + SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001); + SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001); + +#if 1 + /* init MDIO configuration: + * MDS (Poll speed): 0x01 (4ms) + * PHY_LAN_ADDR: 0x06 + * PHY_PC_ADDR: 0x05 + * UEP (Use External PHY): 0x00 (Internal PHY is used) + * PS (Port Select): 0x00 (PT/UMM for LAN) + * PT (PHY Test): 0x00 (no test mode) + * UMM (Use MDIO Mode): 0x00 (state machine is disabled) + */ + SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50); + + /* init PHY: + * SL (Auto Neg. Speed for LAN) + * SP (Auto Neg. Speed for PC) + * LL (Link Status for LAN) + * LP (Link Status for PC) + * DL (Duplex Status for LAN) + * DP (Duplex Status for PC) + * PL (Auto Neg. Pause Status for LAN) + * PP (Auto Neg. Pause Status for PC) + */ + SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff); + + /* MDIO_ACC: + * RA (Request/Ack) 0x01 (Request) + * RW (Read/Write) 0x01 (Write) + * PHY_ADDR 0x05 (PC) + * REG_ADDR 0x00 (PHY_BCR: basic control register) + * PHY_DATA 0x8000 + * Reset - software reset + * LB (loop back) - normal + * SS (speed select) - 10 Mbit/s + * ANE (auto neg. enable) - enable + * PD (power down) - normal + * ISO (isolate) - normal + * RAN (restart auto neg.) - normal + * DM (duplex mode) - half duplex + * CT (collision test) - enable + */ + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000); + + /* MDIO_ACC: + * RA (Request/Ack) 0x01 (Request) + * RW (Read/Write) 0x01 (Write) + * PHY_ADDR 0x06 (LAN) + * REG_ADDR 0x00 (PHY_BCR: basic control register) + * PHY_DATA 0x8000 + * Reset - software reset + * LB (loop back) - normal + * SS (speed select) - 10 Mbit/s + * ANE (auto neg. enable) - enable + * PD (power down) - normal + * ISO (isolate) - normal + * RAN (restart auto neg.) - normal + * DM (duplex mode) - half duplex + * CT (collision test) - enable + */ + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000); + +#endif + + /* Make sure the CPU port is disabled for now. We + * don't want packets to get stacked for us until + * we enable DMA and are prepared to receive them. + */ + SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); + + SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue); + + /* CRC GEN is enabled. + */ + regValue |= 0x00000200; + SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue); + + /* ADD TAG is disabled. + */ + SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); + regValue &= ~0x00000002; + SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); +} + + +static void inca_dma_init(void) +{ + /* Switch off all DMA channels. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF); + + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF); + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF); + + /* Setup TX channel polling time. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME); + + /* Setup RX channel polling time. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME); + + /* ERRATA: write reset value into the DMA RX IMR register. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF); + + /* Just in case: disable all transmit interrupts also. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF); + + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF); + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF); +} + +#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) +static int inca_amdix(void) +{ + u32 phyReg1 = 0; + u32 phyReg4 = 0; + u32 phyReg5 = 0; + u32 phyReg6 = 0; + u32 phyReg31 = 0; + u32 regEphy = 0; + int mdi_flag; + int retries; + + /* Setup GPIO pins. + */ + *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + +#if 0 + /* Wait for signal. + */ + retries = WAIT_SIGNAL_RETRIES; + while (--retries) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (17 << 16)); /* PHY_MCSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); + } while (phyReg1 & (1 << 31)); + + if (phyReg1 & (1 << 1)) { + /* Signal detected */ + break; + } + } + + if (!retries) + goto Fail; +#endif + + /* Set MDI mode. + */ + *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + mdi_flag = 1; + + /* Wait for link. + */ + retries = WAIT_LINK_RETRIES; + while (--retries) { + udelay(LINK_RETRY_DELAY * 1000); + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (1 << 16)); /* PHY_BSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); + } while (phyReg1 & (1 << 31)); + + if (phyReg1 & (1 << 2)) { + /* Link is up */ + break; + } else if (mdi_flag) { + /* Set MDIX mode */ + *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + mdi_flag = 0; + } else { + /* Set MDI mode */ + *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + mdi_flag = 1; + } + } + + if (!retries) { + goto Fail; + } else { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (1 << 16)); /* PHY_BSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); + } while (phyReg1 & (1 << 31)); + + /* Auto-negotiation / Parallel detection complete + */ + if (phyReg1 & (1 << 5)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (31 << 16)); /* PHY_SCSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31); + } while (phyReg31 & (1 << 31)); + + switch ((phyReg31 >> 2) & 0x7) { + case INCA_SWITCH_PHY_SPEED_10H: + /* 10Base-T Half-duplex */ + regEphy = 0; + break; + case INCA_SWITCH_PHY_SPEED_10F: + /* 10Base-T Full-duplex */ + regEphy = INCA_IP_Switch_EPHY_DL; + break; + case INCA_SWITCH_PHY_SPEED_100H: + /* 100Base-TX Half-duplex */ + regEphy = INCA_IP_Switch_EPHY_SL; + break; + case INCA_SWITCH_PHY_SPEED_100F: + /* 100Base-TX Full-duplex */ + regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL; + break; + } + + /* In case of Auto-negotiation, + * update the negotiated PAUSE support status + */ + if (phyReg1 & (1 << 3)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (6 << 16)); /* PHY_ANER */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6); + } while (phyReg6 & (1 << 31)); + + /* We are Autoneg-able. + * Is Link partner also able to autoneg? + */ + if (phyReg6 & (1 << 0)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (4 << 16)); /* PHY_ANAR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4); + } while (phyReg4 & (1 << 31)); + + /* We advertise PAUSE capab. + * Does link partner also advertise it? + */ + if (phyReg4 & (1 << 10)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (5 << 16)); /* PHY_ANLPAR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5); + } while (phyReg5 & (1 << 31)); + + /* Link partner is PAUSE capab. + */ + if (phyReg5 & (1 << 10)) { + regEphy |= INCA_IP_Switch_EPHY_PL; + } + } + } + + } + + /* Link is up */ + regEphy |= INCA_IP_Switch_EPHY_LL; + + SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy); + } + } + + return 0; + +Fail: + printf("No Link on LAN port\n"); + return -1; +} +#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */ + +#endif diff --git a/drivers/keyboard.c b/drivers/keyboard.c new file mode 100644 index 0000000..1579095 --- /dev/null +++ b/drivers/keyboard.c @@ -0,0 +1,305 @@ +/*********************************************************************** + * + * (C) Copyright 2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * All rights reserved. + * + * Keyboard driver + * + ***********************************************************************/ + +#include + +#ifdef CONFIG_PS2KBD + +#include +#include + +#undef KBG_DEBUG + +#ifdef KBG_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + + +#define DEVNAME "kbd" + +#define LED_SCR 0x01 /* scroll lock led */ +#define LED_CAP 0x04 /* caps lock led */ +#define LED_NUM 0x02 /* num lock led */ + +#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ + +#ifdef CONFIG_MPC5xxx +int ps2ser_check(void); +#endif + +static volatile char kbd_buffer[KBD_BUFFER_LEN]; +static volatile int in_pointer = 0; +static volatile int out_pointer = 0; + +static unsigned char leds = 0; +static unsigned char num_lock = 0; +static unsigned char caps_lock = 0; +static unsigned char scroll_lock = 0; +static unsigned char shift = 0; +static unsigned char ctrl = 0; +static unsigned char alt = 0; +static unsigned char e0 = 0; + +/****************************************************************** + * Queue handling + ******************************************************************/ + +/* puts character in the queue and sets up the in and out pointer */ +static void kbd_put_queue(char data) +{ + if((in_pointer+1)==KBD_BUFFER_LEN) { + if(out_pointer==0) { + return; /* buffer full */ + } else{ + in_pointer=0; + } + } else { + if((in_pointer+1)==out_pointer) + return; /* buffer full */ + in_pointer++; + } + kbd_buffer[in_pointer]=data; + return; +} + +/* test if a character is in the queue */ +static int kbd_testc(void) +{ +#ifdef CONFIG_MPC5xxx + /* no ISR is used, so received chars must be polled */ + ps2ser_check(); +#endif + if(in_pointer==out_pointer) + return(0); /* no data */ + else + return(1); +} + +/* gets the character from the queue */ +static int kbd_getc(void) +{ + char c; + while(in_pointer==out_pointer) { +#ifdef CONFIG_MPC5xxx + /* no ISR is used, so received chars must be polled */ + ps2ser_check(); +#endif + ;} + if((out_pointer+1)==KBD_BUFFER_LEN) + out_pointer=0; + else + out_pointer++; + c=kbd_buffer[out_pointer]; + return (int)c; + +} + +/* Simple translation table for the keys */ + +static unsigned char kbd_plain_xlate[] = { + 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ + 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +static unsigned char kbd_shift_xlate[] = { + 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */ + 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +static unsigned char kbd_ctrl_xlate[] = { + 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */ + 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */ + 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */ + 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + + +void handle_scancode(unsigned char scancode) +{ + unsigned char keycode; + + /* Convert scancode to keycode */ + PRINTF("scancode %x\n",scancode); + if(scancode==0xe0) { + e0=1; /* special charakters */ + return; + } + if(e0==1) { + e0=0; /* delete flag */ + if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */ + ((scancode&0x7F)==0x1D)|| /* the right alt key */ + ((scancode&0x7F)==0x35)|| /* the right '/' key */ + ((scancode&0x7F)==0x1C) )) /* the right enter key */ + /* we swallow unknown e0 codes */ + return; + } + /* special cntrl keys */ + switch(scancode) { + case 0x2A: + case 0x36: /* shift pressed */ + shift=1; + return; /* do nothing else */ + case 0xAA: + case 0xB6: /* shift released */ + shift=0; + return; /* do nothing else */ + case 0x38: /* alt pressed */ + alt=1; + return; /* do nothing else */ + case 0xB8: /* alt released */ + alt=0; + return; /* do nothing else */ + case 0x1d: /* ctrl pressed */ + ctrl=1; + return; /* do nothing else */ + case 0x9d: /* ctrl released */ + ctrl=0; + return; /* do nothing else */ + case 0x46: /* scrollock pressed */ + scroll_lock=~scroll_lock; + if(scroll_lock==0) + leds&=~LED_SCR; /* switch LED off */ + else + leds|=LED_SCR; /* switch on LED */ + pckbd_leds(leds); + return; /* do nothing else */ + case 0x3A: /* capslock pressed */ + caps_lock=~caps_lock; + if(caps_lock==0) + leds&=~LED_CAP; /* switch caps_lock off */ + else + leds|=LED_CAP; /* switch on LED */ + pckbd_leds(leds); + return; + case 0x45: /* numlock pressed */ + num_lock=~num_lock; + if(num_lock==0) + leds&=~LED_NUM; /* switch LED off */ + else + leds|=LED_NUM; /* switch on LED */ + pckbd_leds(leds); + return; + case 0xC6: /* scroll lock released */ + case 0xC5: /* num lock released */ + case 0xBA: /* caps lock released */ + return; /* just swallow */ + } +#if 1 + if((scancode&0x80)==0x80) /* key released */ + return; +#else + if((scancode&0x80)==0x00) /* key pressed */ + return; + scancode &= ~0x80; +#endif + /* now, decide which table we need */ + if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow it */ + } + /* setup plain code first */ + keycode=kbd_plain_xlate[scancode]; + if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown caps-locked scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_shift_xlate[scancode]; + if(keycode<'A') { /* we only want the alphas capital */ + keycode=kbd_plain_xlate[scancode]; + } + } + if(shift==1) { /* shift overwrites caps_lock */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown shifted scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_shift_xlate[scancode]; + } + if(ctrl==1) { /* ctrl overwrites caps_lock and shift */ + if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown ctrl scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_ctrl_xlate[scancode]; + } + /* check if valid keycode */ + if(keycode==0xff) { + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow unknown codes */ + } + + kbd_put_queue(keycode); + PRINTF("%x\n",keycode); +} + +/****************************************************************** + * Init + ******************************************************************/ + +#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console (void); +#define OVERWRITE_CONSOLE overwrite_console () +#else +#define OVERWRITE_CONSOLE 0 +#endif /* CFG_CONSOLE_OVERWRITE_ROUTINE */ + +int kbd_init (void) +{ + int error; + device_t kbddev ; + char *stdinname = getenv ("stdin"); + + if(kbd_init_hw()==-1) + return -1; + memset (&kbddev, 0, sizeof(kbddev)); + strcpy(kbddev.name, DEVNAME); + kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbddev.putc = NULL ; + kbddev.puts = NULL ; + kbddev.getc = kbd_getc ; + kbddev.tstc = kbd_testc ; + + error = device_register (&kbddev); + if(error==0) { + /* check if this is the standard input device */ + if(strcmp(stdinname,DEVNAME)==0) { + /* reassign the console */ + if(OVERWRITE_CONSOLE) { + return 1; + } + error=console_assign(stdin,DEVNAME); + if(error==0) + return 1; + else + return error; + } + return 1; + } + return error; +} + +#endif /* CONFIG_PS2KBD */ diff --git a/drivers/ks8695eth.c b/drivers/ks8695eth.c new file mode 100644 index 0000000..a4b03ae --- /dev/null +++ b/drivers/ks8695eth.c @@ -0,0 +1,238 @@ +/* + * ks8695eth.c -- KS8695 ethernet driver + * + * (C) Copyright 2004-2005, Greg Ungerer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifdef CONFIG_DRIVER_KS8695ETH + +/****************************************************************************/ + +#include +#include +#include +#include +#include + +/****************************************************************************/ + +/* + * Hardware register access to the KS8695 LAN ethernet port + * (well, it is the 4 port switch really). + */ +#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) +#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v) + +/****************************************************************************/ + +/* + * Define the descriptor in-memory data structures. + */ +struct ks8695_txdesc { + uint32_t owner; + uint32_t ctrl; + uint32_t addr; + uint32_t next; +}; + +struct ks8695_rxdesc { + uint32_t status; + uint32_t ctrl; + uint32_t addr; + uint32_t next; +}; + +/****************************************************************************/ + +/* + * Allocate local data structures to use for receiving and sending + * packets. Just to keep it all nice and simple. + */ + +#define TXDESCS 4 +#define RXDESCS 4 +#define BUFSIZE 2048 + +volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256))); +volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256))); +volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));; + +/****************************************************************************/ + +/* + * Ideally we want to use the MAC address stored in flash. + * But we do some sanity checks in case they are not present + * first. + */ +unsigned char eth_mac[] = { + 0x00, 0x13, 0xc6, 0x00, 0x00, 0x00 +}; + +void ks8695_getmac(void) +{ + unsigned char *fp; + int i; + + /* Check if flash MAC is valid */ + fp = (unsigned char *) 0x0201c000; + for (i = 0; (i < 6); i++) { + if ((fp[i] != 0) && (fp[i] != 0xff)) + break; + } + + /* If we found a valid looking MAC address then use it */ + if (i < 6) + memcpy(ð_mac[0], fp, 6); +} + +/****************************************************************************/ + +void eth_reset(bd_t *bd) +{ + int i; + + debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__); + + /* Reset the ethernet engines first */ + ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); + ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); + + ks8695_getmac(); + + /* Set MAC address */ + ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) | + (eth_mac[3] << 16) | (eth_mac[2] << 24))); + ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8))); + + /* Turn the 4 port switch on */ + i = ks8695_read(KS8695_SWITCH_CTRL0); + ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1)); + /* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */ + + /* Initialize descriptor rings */ + for (i = 0; (i < TXDESCS); i++) { + ks8695_tx[i].owner = 0; + ks8695_tx[i].ctrl = 0; + ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE]; + ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1]; + } + ks8695_tx[TXDESCS-1].ctrl = 0x02000000; + ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0]; + + for (i = 0; (i < RXDESCS); i++) { + ks8695_rx[i].status = 0x80000000; + ks8695_rx[i].ctrl = BUFSIZE - 4; + ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE]; + ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1]; + } + ks8695_rx[RXDESCS-1].ctrl |= 0x00080000; + ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0]; + + /* The KS8695 is pretty slow reseting the ethernets... */ + udelay(2000000); + + /* Enable the ethernet engine */ + ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]); + ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]); + ks8695_write(KS8695_LAN_DMA_TX, 0x3); + ks8695_write(KS8695_LAN_DMA_RX, 0x71); + ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); + + printf("KS8695 ETHERNET: "); + for (i = 0; (i < 5); i++) { + bd->bi_enetaddr[i] = eth_mac[i]; + printf("%02x:", eth_mac[i]); + } + bd->bi_enetaddr[i] = eth_mac[i]; + printf("%02x\n", eth_mac[i]); +} + +/****************************************************************************/ + +int eth_init(bd_t *bd) +{ + debug ("%s(%d): eth_init()\n", __FILE__, __LINE__); + + eth_reset(bd); + return 0; +} + +/****************************************************************************/ + +void eth_halt(void) +{ + debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__); + + /* Reset the ethernet engines */ + ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); + ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); +} + +/****************************************************************************/ + +int eth_rx(void) +{ + volatile struct ks8695_rxdesc *dp; + int i, len = 0; + + debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__); + + for (i = 0; (i < RXDESCS); i++) { + dp= &ks8695_rx[i]; + if ((dp->status & 0x80000000) == 0) { + len = (dp->status & 0x7ff) - 4; + NetReceive((void *) dp->addr, len); + dp->status = 0x80000000; + ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); + break; + } + } + + return len; +} + +/****************************************************************************/ + +int eth_send(volatile void *packet, int len) +{ + volatile struct ks8695_txdesc *dp; + static int next = 0; + + debug ("%s(%d): eth_send(packet=%x,len=%d)\n", __FILE__, __LINE__, + packet, len); + + dp = &ks8695_tx[next]; + memcpy((void *) dp->addr, packet, len); + + if (len < 64) { + memset(dp->addr+len, 0, 64-len); + len = 64; + } + + dp->ctrl = len | 0xe0000000; + dp->owner = 0x80000000; + + ks8695_write(KS8695_LAN_DMA_TX, 0x3); + ks8695_write(KS8695_LAN_DMA_TX_START, 0x1); + + if (++next >= TXDESCS) + next = 0; + + return len; +} + +#endif /* CONFIG_DRIVER_KS8695ETH */ diff --git a/drivers/lan91c96.c b/drivers/lan91c96.c new file mode 100644 index 0000000..bb03dae --- /dev/null +++ b/drivers/lan91c96.c @@ -0,0 +1,967 @@ +/*------------------------------------------------------------------------ + * lan91c96.c + * This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based + * on the SMC91111 driver from U-boot. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Rolf Offermanns + * + * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + * Developed by Simple Network Magic Corporation (SNMC) + * Copyright (C) 1996 by Erik Stahlman (ES) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Information contained in this file was obtained from the LAN91C96 + * manual from SMC. To get a copy, if you really want one, you can find + * information under www.smsc.com. + * + * + * "Features" of the SMC chip: + * 6144 byte packet memory. ( for the 91C96 ) + * EEPROM for configuration + * AUI/TP selection ( mine has 10Base2/10BaseT select ) + * + * Arguments: + * io = for the base address + * irq = for the IRQ + * + * author: + * Erik Stahlman ( erik@vt.edu ) + * Daris A Nevil ( dnevil@snmc.com ) + * + * + * Hardware multicast code from Peter Cammaert ( pc@denkart.be ) + * + * Sources: + * o SMSC LAN91C96 databook (www.smsc.com) + * o smc91111.c (u-boot driver) + * o smc9194.c (linux kernel driver) + * o lan91c96.c (Intel Diagnostic Manager driver) + * + * History: + * 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version) + * for lan91c96 + *--------------------------------------------------------------------------- + */ + +#include +#include +#include "lan91c96.h" +#include + +#ifdef CONFIG_DRIVER_LAN91C96 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/*------------------------------------------------------------------------ + * + * Configuration options, for the experienced user to change. + * + -------------------------------------------------------------------------*/ + +/* Use power-down feature of the chip */ +#define POWER_DOWN 0 + +/* + * Wait time for memory to be free. This probably shouldn't be + * tuned that much, as waiting for this means nothing else happens + * in the system +*/ +#define MEMORY_WAIT_TIME 16 + +#define SMC_DEBUG 0 + +#if (SMC_DEBUG > 2 ) +#define PRINTK3(args...) printf(args) +#else +#define PRINTK3(args...) +#endif + +#if SMC_DEBUG > 1 +#define PRINTK2(args...) printf(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef SMC_DEBUG +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + + +/*------------------------------------------------------------------------ + * + * The internal workings of the driver. If you are changing anything + * here with the SMC stuff, you should have the datasheet and know + * what you are doing. + * + *------------------------------------------------------------------------ + */ +#define CARDNAME "LAN91C96" + +#define SMC_BASE_ADDRESS CONFIG_LAN91C96_BASE + +#define SMC_DEV_NAME "LAN91C96" +#define SMC_ALLOC_MAX_TRY 5 +#define SMC_TX_TIMEOUT 30 + +#define ETH_ZLEN 60 + +#ifdef CONFIG_LAN91C96_USE_32_BIT +#define USE_32_BIT 1 +#else +#undef USE_32_BIT +#endif + +/*----------------------------------------------------------------- + * + * The driver can be entered at any of the following entry points. + * + *----------------------------------------------------------------- + */ + +extern int eth_init (bd_t * bd); +extern void eth_halt (void); +extern int eth_rx (void); +extern int eth_send (volatile void *packet, int length); +#if 0 +static int smc_hw_init (void); +#endif + +/* + * This is called by register_netdev(). It is responsible for + * checking the portlist for the SMC9000 series chipset. If it finds + * one, then it will initialize the device, find the hardware information, + * and sets up the appropriate device parameters. + * NOTE: Interrupts are *OFF* when this procedure is called. + * + * NB:This shouldn't be static since it is referred to externally. + */ +int smc_init (void); + +/* + * This is called by unregister_netdev(). It is responsible for + * cleaning up before the driver is finally unregistered and discarded. + */ +void smc_destructor (void); + +/* + * The kernel calls this function when someone wants to use the device, + * typically 'ifconfig ethX up'. + */ +static int smc_open (bd_t *bd); + + +/* + * This is called by the kernel in response to 'ifconfig ethX down'. It + * is responsible for cleaning up everything that the open routine + * does, and maybe putting the card into a powerdown state. + */ +static int smc_close (void); + +/* + * This is a separate procedure to handle the receipt of a packet, to + * leave the interrupt code looking slightly cleaner + */ +static int smc_rcv (void); + +/* See if a MAC address is defined in the current environment. If so use it. If not + . print a warning and set the environment and other globals with the default. + . If an EEPROM is present it really should be consulted. +*/ +int smc_get_ethaddr(bd_t *bd); +int get_rom_mac(char *v_rom_mac); + +/* ------------------------------------------------------------ + * Internal routines + * ------------------------------------------------------------ + */ + +static char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c }; + +/* + * This function must be called before smc_open() if you want to override + * the default mac address. + */ + +void smc_set_mac_addr (const char *addr) +{ + int i; + + for (i = 0; i < sizeof (smc_mac_addr); i++) { + smc_mac_addr[i] = addr[i]; + } +} + +/* + * smc_get_macaddr is no longer used. If you want to override the default + * mac address, call smc_get_mac_addr as a part of the board initialisation. + */ + +#if 0 +void smc_get_macaddr (byte * addr) +{ + /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ + unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); + int i; + + + for (i = 0; i < 6; i++) { + addr[0] = *(dnp1110_mac + 0); + addr[1] = *(dnp1110_mac + 1); + addr[2] = *(dnp1110_mac + 2); + addr[3] = *(dnp1110_mac + 3); + addr[4] = *(dnp1110_mac + 4); + addr[5] = *(dnp1110_mac + 5); + } +} +#endif /* 0 */ + +/*********************************************** + * Show available memory * + ***********************************************/ +void dump_memory_info (void) +{ + word mem_info; + word old_bank; + + old_bank = SMC_inw (LAN91C96_BANK_SELECT) & 0xF; + + SMC_SELECT_BANK (0); + mem_info = SMC_inw (LAN91C96_MIR); + PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048); + + SMC_SELECT_BANK (old_bank); +} + +/* + * A rather simple routine to print out a packet for debugging purposes. + */ +#if SMC_DEBUG > 2 +static void print_packet (byte *, int); +#endif + +/* #define tx_done(dev) 1 */ + + +/* this does a soft reset on the device */ +static void smc_reset (void); + +/* Enable Interrupts, Receive, and Transmit */ +static void smc_enable (void); + +/* this puts the device in an inactive state */ +static void smc_shutdown (void); + + +static int poll4int (byte mask, int timeout) +{ + int tmo = get_timer (0) + timeout * CFG_HZ; + int is_timeout = 0; + word old_bank = SMC_inw (LAN91C96_BANK_SELECT); + + PRINTK2 ("Polling...\n"); + SMC_SELECT_BANK (2); + while ((SMC_inw (LAN91C96_INT_STATS) & mask) == 0) { + if (get_timer (0) >= tmo) { + is_timeout = 1; + break; + } + } + + /* restore old bank selection */ + SMC_SELECT_BANK (old_bank); + + if (is_timeout) + return 1; + else + return 0; +} + +/* + * Function: smc_reset( void ) + * Purpose: + * This sets the SMC91111 chip to its normal state, hopefully from whatever + * mess that any other DOS driver has put it in. + * + * Maybe I should reset more registers to defaults in here? SOFTRST should + * do that for me. + * + * Method: + * 1. send a SOFT RESET + * 2. wait for it to finish + * 3. enable autorelease mode + * 4. reset the memory management unit + * 5. clear all interrupts + * +*/ +static void smc_reset (void) +{ + PRINTK2 ("%s:smc_reset\n", SMC_DEV_NAME); + + /* This resets the registers mostly to defaults, but doesn't + affect EEPROM. That seems unnecessary */ + SMC_SELECT_BANK (0); + SMC_outw (LAN91C96_RCR_SOFT_RST, LAN91C96_RCR); + + udelay (10); + + /* Disable transmit and receive functionality */ + SMC_outw (0, LAN91C96_RCR); + SMC_outw (0, LAN91C96_TCR); + + /* set the control register */ + SMC_SELECT_BANK (1); + SMC_outw (SMC_inw (LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8, + LAN91C96_CONTROL); + + /* Disable all interrupts */ + SMC_outb (0, LAN91C96_INT_MASK); +} + +/* + * Function: smc_enable + * Purpose: let the chip talk to the outside work + * Method: + * 1. Initialize the Memory Configuration Register + * 2. Enable the transmitter + * 3. Enable the receiver +*/ +static void smc_enable () +{ + PRINTK2 ("%s:smc_enable\n", SMC_DEV_NAME); + SMC_SELECT_BANK (0); + + /* Initialize the Memory Configuration Register. See page + 49 of the LAN91C96 data sheet for details. */ + SMC_outw (LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR); + + /* Initialize the Transmit Control Register */ + SMC_outw (LAN91C96_TCR_TXENA, LAN91C96_TCR); + /* Initialize the Receive Control Register + * FIXME: + * The promiscuous bit set because I could not receive ARP reply + * packets from the server when I send a ARP request. It only works + * when I set the promiscuous bit + */ + SMC_outw (LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR); +} + +/* + * Function: smc_shutdown + * Purpose: closes down the SMC91xxx chip. + * Method: + * 1. zero the interrupt mask + * 2. clear the enable receive flag + * 3. clear the enable xmit flags + * + * TODO: + * (1) maybe utilize power down mode. + * Why not yet? Because while the chip will go into power down mode, + * the manual says that it will wake up in response to any I/O requests + * in the register space. Empirical results do not show this working. + */ +static void smc_shutdown () +{ + PRINTK2 (CARDNAME ":smc_shutdown\n"); + + /* no more interrupts for me */ + SMC_SELECT_BANK (2); + SMC_outb (0, LAN91C96_INT_MASK); + + /* and tell the card to stay away from that nasty outside world */ + SMC_SELECT_BANK (0); + SMC_outb (0, LAN91C96_RCR); + SMC_outb (0, LAN91C96_TCR); +} + + +/* + * Function: smc_hardware_send_packet(struct net_device * ) + * Purpose: + * This sends the actual packet to the SMC9xxx chip. + * + * Algorithm: + * First, see if a saved_skb is available. + * ( this should NOT be called if there is no 'saved_skb' + * Now, find the packet number that the chip allocated + * Point the data pointers at it in memory + * Set the length word in the chip's memory + * Dump the packet to chip memory + * Check if a last byte is needed ( odd length packet ) + * if so, set the control flag right + * Tell the card to send it + * Enable the transmit interrupt, so I know if it failed + * Free the kernel data if I actually sent it. + */ +static int smc_send_packet (volatile void *packet, int packet_length) +{ + byte packet_no; + unsigned long ioaddr; + byte *buf; + int length; + int numPages; + int try = 0; + int time_out; + byte status; + + + PRINTK3 ("%s:smc_hardware_send_packet\n", SMC_DEV_NAME); + + length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; + + /* allocate memory + ** The MMU wants the number of pages to be the number of 256 bytes + ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) + ** + ** The 91C111 ignores the size bits, but the code is left intact + ** for backwards and future compatibility. + ** + ** Pkt size for allocating is data length +6 (for additional status + ** words, length and ctl!) + ** + ** If odd size then last byte is included in this header. + */ + numPages = ((length & 0xfffe) + 6); + numPages >>= 8; /* Divide by 256 */ + + if (numPages > 7) { + printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); + return 0; + } + + /* now, try to allocate the memory */ + + SMC_SELECT_BANK (2); + SMC_outw (LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU); + + again: + try++; + time_out = MEMORY_WAIT_TIME; + do { + status = SMC_inb (LAN91C96_INT_STATS); + if (status & LAN91C96_IST_ALLOC_INT) { + + SMC_outb (LAN91C96_IST_ALLOC_INT, LAN91C96_INT_STATS); + break; + } + } while (--time_out); + + if (!time_out) { + PRINTK2 ("%s: memory allocation, try %d failed ...\n", + SMC_DEV_NAME, try); + if (try < SMC_ALLOC_MAX_TRY) + goto again; + else + return 0; + } + + PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", + SMC_DEV_NAME, try); + + /* I can send the packet now.. */ + + ioaddr = SMC_BASE_ADDRESS; + + buf = (byte *) packet; + + /* If I get here, I _know_ there is a packet slot waiting for me */ + packet_no = SMC_inb (LAN91C96_ARR); + if (packet_no & LAN91C96_ARR_FAILED) { + /* or isn't there? BAD CHIP! */ + printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); + return 0; + } + + /* we have a packet address, so tell the card to use it */ + SMC_outb (packet_no, LAN91C96_PNR); + + /* point to the beginning of the packet */ + SMC_outw (LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); + + PRINTK3 ("%s: Trying to xmit packet of length %x\n", + SMC_DEV_NAME, length); + +#if SMC_DEBUG > 2 + printf ("Transmitting Packet\n"); + print_packet (buf, length); +#endif + + /* send the packet length ( +6 for status, length and ctl byte ) + and the status word ( set to zeros ) */ +#ifdef USE_32_BIT + SMC_outl ((length + 6) << 16, LAN91C96_DATA_HIGH); +#else + SMC_outw (0, LAN91C96_DATA_HIGH); + /* send the packet length ( +6 for status words, length, and ctl */ + SMC_outw ((length + 6), LAN91C96_DATA_HIGH); +#endif /* USE_32_BIT */ + + /* send the actual data + * I _think_ it's faster to send the longs first, and then + * mop up by sending the last word. It depends heavily + * on alignment, at least on the 486. Maybe it would be + * a good idea to check which is optimal? But that could take + * almost as much time as is saved? + */ +#ifdef USE_32_BIT + SMC_outsl (LAN91C96_DATA_HIGH, buf, length >> 2); + if (length & 0x2) + SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), + LAN91C96_DATA_HIGH); +#else + SMC_outsw (LAN91C96_DATA_HIGH, buf, (length) >> 1); +#endif /* USE_32_BIT */ + + /* Send the last byte, if there is one. */ + if ((length & 1) == 0) { + SMC_outw (0, LAN91C96_DATA_HIGH); + } else { + SMC_outw (buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH); + } + + /* and let the chipset deal with it */ + SMC_outw (LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU); + + /* poll for TX INT */ + if (poll4int (LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) { + /* sending failed */ + PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); + + /* release packet */ + SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + + /* wait for MMU getting ready (low) */ + while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + + + return 0; + } else { + /* ack. int */ + SMC_outw (LAN91C96_IST_TX_INT, LAN91C96_INT_STATS); + + PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, length); + + /* release packet */ + SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + + /* wait for MMU getting ready (low) */ + while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + } + + return length; +} + +/*------------------------------------------------------------------------- + * smc_destructor( struct net_device * dev ) + * Input parameters: + * dev, pointer to the device structure + * + * Output: + * None. + *-------------------------------------------------------------------------- + */ +void smc_destructor () +{ + PRINTK2 (CARDNAME ":smc_destructor\n"); +} + + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc .. + * + */ +static int smc_open (bd_t *bd) +{ + int i, err; /* used to set hw ethernet address */ + + PRINTK2 ("%s:smc_open\n", SMC_DEV_NAME); + + /* reset the hardware */ + + smc_reset (); + smc_enable (); + + SMC_SELECT_BANK (1); + + err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ + if (err < 0) { + memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */ + return (-1); /* upper code ignores this, but NOT bi_enetaddr */ + } +#ifdef USE_32_BIT + for (i = 0; i < 6; i += 2) { + word address; + + address = smc_mac_addr[i + 1] << 8; + address |= smc_mac_addr[i]; + SMC_outw (address, LAN91C96_IA0 + i); + } +#else + for (i = 0; i < 6; i++) + SMC_outb (smc_mac_addr[i], LAN91C96_IA0 + i); +#endif + return 0; +} + +/*------------------------------------------------------------- + * + * smc_rcv - receive a packet from the card + * + * There is ( at least ) a packet waiting to be read from + * chip-memory. + * + * o Read the status + * o If an error, record it + * o otherwise, read in the packet + *------------------------------------------------------------- + */ +static int smc_rcv () +{ + int packet_number; + word status; + word packet_length; + int is_error = 0; + +#ifdef USE_32_BIT + dword stat_len; +#endif + + + SMC_SELECT_BANK (2); + packet_number = SMC_inw (LAN91C96_FIFO); + + if (packet_number & LAN91C96_FIFO_RXEMPTY) { + return 0; + } + + PRINTK3 ("%s:smc_rcv\n", SMC_DEV_NAME); + /* start reading from the start of the packet */ + SMC_outw (LAN91C96_PTR_READ | LAN91C96_PTR_RCV | + LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); + + /* First two words are status and packet_length */ +#ifdef USE_32_BIT + stat_len = SMC_inl (LAN91C96_DATA_HIGH); + status = stat_len & 0xffff; + packet_length = stat_len >> 16; +#else + status = SMC_inw (LAN91C96_DATA_HIGH); + packet_length = SMC_inw (LAN91C96_DATA_HIGH); +#endif + + packet_length &= 0x07ff; /* mask off top bits */ + + PRINTK2 ("RCV: STATUS %4x LENGTH %4x\n", status, packet_length); + + if (!(status & FRAME_FILTER)) { + /* Adjust for having already read the first two words */ + packet_length -= 4; /*4; */ + + + /* set odd length for bug in LAN91C111, */ + /* which never sets RS_ODDFRAME */ + /* TODO ? */ + + +#ifdef USE_32_BIT + PRINTK3 (" Reading %d dwords (and %d bytes) \n", + packet_length >> 2, packet_length & 3); + /* QUESTION: Like in the TX routine, do I want + to send the DWORDs or the bytes first, or some + mixture. A mixture might improve already slow PIO + performance */ + SMC_insl (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 2); + /* read the left over bytes */ + if (packet_length & 3) { + int i; + + byte *tail = (byte *) (NetRxPackets[0] + (packet_length & ~3)); + dword leftover = SMC_inl (LAN91C96_DATA_HIGH); + + for (i = 0; i < (packet_length & 3); i++) + *tail++ = (byte) (leftover >> (8 * i)) & 0xff; + } +#else + PRINTK3 (" Reading %d words and %d byte(s) \n", + (packet_length >> 1), packet_length & 1); + SMC_insw (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 1); + +#endif /* USE_32_BIT */ + +#if SMC_DEBUG > 2 + printf ("Receiving Packet\n"); + print_packet (NetRxPackets[0], packet_length); +#endif + } else { + /* error ... */ + /* TODO ? */ + is_error = 1; + } + + while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + udelay (1); /* Wait until not busy */ + + /* error or good, tell the card to get rid of this packet */ + SMC_outw (LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU); + + while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + udelay (1); /* Wait until not busy */ + + if (!is_error) { + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], packet_length); + return packet_length; + } else { + return 0; + } + +} + +/*---------------------------------------------------- + * smc_close + * + * this makes the board clean up everything that it can + * and not talk to the outside world. Caused by + * an 'ifconfig ethX down' + * + -----------------------------------------------------*/ +static int smc_close () +{ + PRINTK2 ("%s:smc_close\n", SMC_DEV_NAME); + + /* clear everything */ + smc_shutdown (); + + return 0; +} + +#if SMC_DEBUG > 2 +static void print_packet (byte * buf, int length) +{ +#if 0 + int i; + int remainder; + int lines; + + printf ("Packet of length %d \n", length); + + lines = length / 16; + remainder = length % 16; + + for (i = 0; i < lines; i++) { + int cur; + + for (cur = 0; cur < 8; cur++) { + byte a, b; + + a = *(buf++); + b = *(buf++); + printf ("%02x%02x ", a, b); + } + printf ("\n"); + } + for (i = 0; i < remainder / 2; i++) { + byte a, b; + + a = *(buf++); + b = *(buf++); + printf ("%02x%02x ", a, b); + } + printf ("\n"); +#endif /* 0 */ +} +#endif /* SMC_DEBUG > 2 */ + +int eth_init (bd_t * bd) +{ + return (smc_open(bd)); +} + +void eth_halt () +{ + smc_close (); +} + +int eth_rx () +{ + return smc_rcv (); +} + +int eth_send (volatile void *packet, int length) +{ + return smc_send_packet (packet, length); +} + + +#if 0 +/*------------------------------------------------------------------------- + * smc_hw_init() + * + * Function: + * Reset and enable the device, check if the I/O space location + * is correct + * + * Input parameters: + * None + * + * Output: + * 0 --> success + * 1 --> error + *-------------------------------------------------------------------------- + */ +static int smc_hw_init () +{ + unsigned short status_test; + + /* The attribute register of the LAN91C96 is located at address + 0x0e000000 on the lubbock platform */ + volatile unsigned *attaddr = (unsigned *) (0x0e000000); + + /* first reset, then enable the device. Sequence is critical */ + attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_SRESET; + udelay (100); + attaddr[LAN91C96_ECOR] &= ~LAN91C96_ECOR_SRESET; + attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_ENABLE; + + /* force 16-bit mode */ + attaddr[LAN91C96_ECSR] &= ~LAN91C96_ECSR_IOIS8; + udelay (100); + + /* check if the I/O address is correct, the upper byte of the + bank select register should read 0x33 */ + + status_test = SMC_inw (LAN91C96_BANK_SELECT); + if ((status_test & 0xFF00) != 0x3300) { + printf ("Failed to initialize ethernetchip\n"); + return 1; + } + return 0; +} +#endif /* 0 */ + +#endif /* COMMANDS & CFG_NET */ + + +/* smc_get_ethaddr (bd_t * bd) + * + * This checks both the environment and the ROM for an ethernet address. If + * found, the environment takes precedence. + */ + +int smc_get_ethaddr (bd_t * bd) +{ + int env_size = 0; + int rom_valid = 0; + int env_present = 0; + int reg = 0; + char *s = NULL; + char *e = NULL; + char *v_mac, es[] = "11:22:33:44:55:66"; + uchar s_env_mac[64]; + uchar v_env_mac[6]; + uchar v_rom_mac[6]; + + env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); + if (env_size != sizeof(es)) { /* Ignore if env is bad or not set */ + printf ("\n*** Warning: ethaddr is not set properly, ignoring!!\n"); + } else { + env_present = 1; + s = s_env_mac; + + for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */ + v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + } + + rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */ + + if (!env_present) { /* if NO env */ + if (rom_valid) { /* but ROM is valid */ + v_mac = v_rom_mac; + sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", + v_mac[0], v_mac[1], v_mac[2], v_mac[3], + v_mac[4], v_mac[5]); + setenv ("ethaddr", s_env_mac); + } else { /* no env, bad ROM */ + printf ("\n*** ERROR: ethaddr is NOT set !!\n"); + return (-1); + } + } else { /* good env, don't care ROM */ + v_mac = v_env_mac; /* always use a good env over a ROM */ + } + + if (env_present && rom_valid) { /* if both env and ROM are good */ + if (memcmp (v_env_mac, v_rom_mac, 6) != 0) { + printf ("\nWarning: MAC addresses don't match:\n"); + printf ("\tHW MAC address: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + v_rom_mac[0], v_rom_mac[1], + v_rom_mac[2], v_rom_mac[3], + v_rom_mac[4], v_rom_mac[5] ); + printf ("\t\"ethaddr\" value: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + v_env_mac[0], v_env_mac[1], + v_env_mac[2], v_env_mac[3], + v_env_mac[4], v_env_mac[5]) ; + debug ("### Set MAC addr from environment\n"); + } + } + memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */ + smc_set_mac_addr (v_mac); /* use old function to update smc default */ + PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1], + v_mac[2], v_mac[3], v_mac[4], v_mac[5]); + return (0); +} + +/* + * get_rom_mac() + * Note, this has omly been tested for the OMAP730 P2. + */ + +int get_rom_mac (char *v_rom_mac) +{ +#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ + char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; + + memcpy (v_rom_mac, hw_mac_addr, 6); + return (1); +#else + int i; + SMC_SELECT_BANK (1); + for (i=0; i<6; i++) + { + v_rom_mac[i] = SMC_inb (LAN91C96_IA0 + i); + } + return (1); +#endif +} + +#endif /* CONFIG_DRIVER_LAN91C96 */ diff --git a/drivers/lan91c96.h b/drivers/lan91c96.h new file mode 100644 index 0000000..b7d7455 --- /dev/null +++ b/drivers/lan91c96.h @@ -0,0 +1,643 @@ +/*------------------------------------------------------------------------ + * lan91c96.h + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Rolf Offermanns + * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + * Developed by Simple Network Magic Corporation (SNMC) + * Copyright (C) 1996 by Erik Stahlman (ES) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file contains register information and access macros for + * the LAN91C96 single chip ethernet controller. It is a modified + * version of the smc9111.h file. + * + * Information contained in this file was obtained from the LAN91C96 + * manual from SMC. To get a copy, if you really want one, you can find + * information under www.smsc.com. + * + * Authors + * Erik Stahlman ( erik@vt.edu ) + * Daris A Nevil ( dnevil@snmc.com ) + * + * History + * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version) + * for lan91c96 + *------------------------------------------------------------------------- + */ +#ifndef _LAN91C96_H_ +#define _LAN91C96_H_ + +#include +#include +#include + +/* + * This function may be called by the board specific initialisation code + * in order to override the default mac address. + */ + +void smc_set_mac_addr(const char *addr); + + +/* I want some simple types */ + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; + +/* + * DEBUGGING LEVELS + * + * 0 for normal operation + * 1 for slightly more details + * >2 for various levels of increasingly useless information + * 2 for interrupt tracking, status flags + * 3 for packet info + * 4 for complete packet dumps + */ +/*#define SMC_DEBUG 0 */ + +/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ + +#define SMC_IO_EXTENT 16 + +#ifdef CONFIG_PXA250 + +#ifdef CONFIG_LUBBOCK +#define SMC_IO_SHIFT 2 +#undef USE_32_BIT + +#else +#define SMC_IO_SHIFT 0 +#endif + +#define SMCREG(r) (SMC_BASE_ADDRESS+((r)<>= 8; \ + else __v &= 0xff; \ + __v; }) + +#define SMC_outl(d,r) (*((volatile dword *)SMCREG(r)) = d) +#define SMC_outw(d,r) (*((volatile word *)SMCREG(r)) = d) +#define SMC_outb(d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(__w,(r)&~1); \ + }) + +#define SMC_outsl(r,b,l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl( *(__b2 + __i), r ); \ + } \ + }) + +#define SMC_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw( *(__b2 + __i), r ); \ + } \ + }) + +#define SMC_insl(r,b,l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl(r); \ + SMC_inl(0); \ + }; \ + }) + +#define SMC_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(r); \ + SMC_inw(0); \ + }; \ + }) + +#define SMC_insb(r,b,l) ({ int __i ; \ + byte *__b2; \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inb(r); \ + SMC_inb(0); \ + }; \ + }) + +#else /* if not CONFIG_PXA250 */ + +/* + * We have only 16 Bit PCMCIA access on Socket 0 + */ + +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) + +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outb(d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(__w,(r)&~1); \ + }) +#if 0 +#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) +#else +#define SMC_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw( *(__b2 + __i), r); \ + } \ + }) +#endif + +#if 0 +#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) +#else +#define SMC_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(r); \ + SMC_inw(0); \ + }; \ + }) +#endif + +#endif + +/* + **************************************************************************** + * Bank Select Field + **************************************************************************** + */ +#define LAN91C96_BANK_SELECT 14 /* Bank Select Register */ +#define LAN91C96_BANKSELECT (0x3UC << 0) +#define BANK0 0x00 +#define BANK1 0x01 +#define BANK2 0x02 +#define BANK3 0x03 +#define BANK4 0x04 + +/* + **************************************************************************** + * EEPROM Addresses. + **************************************************************************** + */ +#define EEPROM_MAC_OFFSET_1 0x6020 +#define EEPROM_MAC_OFFSET_2 0x6021 +#define EEPROM_MAC_OFFSET_3 0x6022 + +/* + **************************************************************************** + * Bank 0 Register Map in I/O Space + **************************************************************************** + */ +#define LAN91C96_TCR 0 /* Transmit Control Register */ +#define LAN91C96_EPH_STATUS 2 /* EPH Status Register */ +#define LAN91C96_RCR 4 /* Receive Control Register */ +#define LAN91C96_COUNTER 6 /* Counter Register */ +#define LAN91C96_MIR 8 /* Memory Information Register */ +#define LAN91C96_MCR 10 /* Memory Configuration Register */ + +/* + **************************************************************************** + * Transmit Control Register - Bank 0 - Offset 0 + **************************************************************************** + */ +#define LAN91C96_TCR_TXENA (0x1U << 0) +#define LAN91C96_TCR_LOOP (0x1U << 1) +#define LAN91C96_TCR_FORCOL (0x1U << 2) +#define LAN91C96_TCR_TXP_EN (0x1U << 3) +#define LAN91C96_TCR_PAD_EN (0x1U << 7) +#define LAN91C96_TCR_NOCRC (0x1U << 8) +#define LAN91C96_TCR_MON_CSN (0x1U << 10) +#define LAN91C96_TCR_FDUPLX (0x1U << 11) +#define LAN91C96_TCR_STP_SQET (0x1U << 12) +#define LAN91C96_TCR_EPH_LOOP (0x1U << 13) +#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14) +#define LAN91C96_TCR_FDSE (0x1U << 15) + +/* + **************************************************************************** + * EPH Status Register - Bank 0 - Offset 2 + **************************************************************************** + */ +#define LAN91C96_EPHSR_TX_SUC (0x1U << 0) +#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1) +#define LAN91C96_EPHSR_MUL_COL (0x1U << 2) +#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3) +#define LAN91C96_EPHSR_16COL (0x1U << 4) +#define LAN91C96_EPHSR_SQET (0x1U << 5) +#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6) +#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7) +#define LAN91C96_EPHSR_WAKEUP (0x1U << 8) +#define LAN91C96_EPHSR_LATCOL (0x1U << 9) +#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10) +#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11) +#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12) + +#define LAN91C96_EPHSR_LINK_OK (0x1U << 14) +#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15) + +#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ + LAN91C96_EPHSR_MUL_COL | \ + LAN91C96_EPHSR_16COL | \ + LAN91C96_EPHSR_SQET | \ + LAN91C96_EPHSR_TX_DEFR | \ + LAN91C96_EPHSR_LATCOL | \ + LAN91C96_EPHSR_LOST_CARR | \ + LAN91C96_EPHSR_EXC_DEF | \ + LAN91C96_EPHSR_LINK_OK | \ + LAN91C96_EPHSR_TX_UNRN) + +/* + **************************************************************************** + * Receive Control Register - Bank 0 - Offset 4 + **************************************************************************** + */ +#define LAN91C96_RCR_RX_ABORT (0x1U << 0) +#define LAN91C96_RCR_PRMS (0x1U << 1) +#define LAN91C96_RCR_ALMUL (0x1U << 2) +#define LAN91C96_RCR_RXEN (0x1U << 8) +#define LAN91C96_RCR_STRIP_CRC (0x1U << 9) +#define LAN91C96_RCR_FILT_CAR (0x1U << 14) +#define LAN91C96_RCR_SOFT_RST (0x1U << 15) + +/* + **************************************************************************** + * Counter Register - Bank 0 - Offset 6 + **************************************************************************** + */ +#define LAN91C96_ECR_SNGL_COL (0xFU << 0) +#define LAN91C96_ECR_MULT_COL (0xFU << 5) +#define LAN91C96_ECR_DEF_TX (0xFU << 8) +#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12) + +/* + **************************************************************************** + * Memory Information Register - Bank 0 - OFfset 8 + **************************************************************************** + */ +#define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */ + +/* + **************************************************************************** + * Memory Configuration Register - Bank 0 - Offset 10 + **************************************************************************** + */ +#define LAN91C96_MCR_MEM_RES (0xFFU << 0) +#define LAN91C96_MCR_MEM_MULT (0x3U << 9) +#define LAN91C96_MCR_HIGH_ID (0x3U << 12) + +#define LAN91C96_MCR_TRANSMIT_PAGES 0x6 + +/* + **************************************************************************** + * Bank 1 Register Map in I/O Space + **************************************************************************** + */ +#define LAN91C96_CONFIG 0 /* Configuration Register */ +#define LAN91C96_BASE 2 /* Base Address Register */ +#define LAN91C96_IA0 4 /* Individual Address Register - 0 */ +#define LAN91C96_IA1 5 /* Individual Address Register - 1 */ +#define LAN91C96_IA2 6 /* Individual Address Register - 2 */ +#define LAN91C96_IA3 7 /* Individual Address Register - 3 */ +#define LAN91C96_IA4 8 /* Individual Address Register - 4 */ +#define LAN91C96_IA5 9 /* Individual Address Register - 5 */ +#define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */ +#define LAN91C96_CONTROL 12 /* Control Register */ + +/* + **************************************************************************** + * Configuration Register - Bank 1 - Offset 0 + **************************************************************************** + */ +#define LAN91C96_CR_INT_SEL0 (0x1U << 1) +#define LAN91C96_CR_INT_SEL1 (0x1U << 2) +#define LAN91C96_CR_RES (0x3U << 3) +#define LAN91C96_CR_DIS_LINK (0x1U << 6) +#define LAN91C96_CR_16BIT (0x1U << 7) +#define LAN91C96_CR_AUI_SELECT (0x1U << 8) +#define LAN91C96_CR_SET_SQLCH (0x1U << 9) +#define LAN91C96_CR_FULL_STEP (0x1U << 10) +#define LAN91C96_CR_NO_WAIT (0x1U << 12) + +/* + **************************************************************************** + * Base Address Register - Bank 1 - Offset 2 + **************************************************************************** + */ +#define LAN91C96_BAR_RA_BITS (0x27U << 0) +#define LAN91C96_BAR_ROM_SIZE (0x1U << 6) +#define LAN91C96_BAR_A_BITS (0xFFU << 8) + +/* + **************************************************************************** + * Control Register - Bank 1 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_CTR_STORE (0x1U << 0) +#define LAN91C96_CTR_RELOAD (0x1U << 1) +#define LAN91C96_CTR_EEPROM (0x1U << 2) +#define LAN91C96_CTR_TE_ENABLE (0x1U << 5) +#define LAN91C96_CTR_CR_ENABLE (0x1U << 6) +#define LAN91C96_CTR_LE_ENABLE (0x1U << 7) +#define LAN91C96_CTR_BIT_8 (0x1U << 8) +#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11) +#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12) +#define LAN91C96_CTR_PWRDN (0x1U << 13) +#define LAN91C96_CTR_RCV_BAD (0x1U << 14) + +/* + **************************************************************************** + * Bank 2 Register Map in I/O Space + **************************************************************************** + */ +#define LAN91C96_MMU 0 /* MMU Command Register */ +#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */ +#define LAN91C96_PNR 2 /* Packet Number Register */ +#define LAN91C96_ARR 3 /* Allocation Result Register */ +#define LAN91C96_FIFO 4 /* FIFO Ports Register */ +#define LAN91C96_POINTER 6 /* Pointer Register */ +#define LAN91C96_DATA_HIGH 8 /* Data High Register */ +#define LAN91C96_DATA_LOW 10 /* Data Low Register */ +#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */ +#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */ +#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */ + +/* + **************************************************************************** + * MMU Command Register - Bank 2 - Offset 0 + **************************************************************************** + */ +#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0) +#define LAN91C96_MMUCR_N1 (0x1U << 1) +#define LAN91C96_MMUCR_N2 (0x1U << 2) +#define LAN91C96_MMUCR_COMMAND (0xFU << 4) +#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */ +#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */ +#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */ +#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */ +#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */ +#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */ +#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */ +#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */ + +/* + **************************************************************************** + * Auto Tx Start Register - Bank 2 - Offset 1 + **************************************************************************** + */ +#define LAN91C96_AUTOTX (0xFFU << 0) + +/* + **************************************************************************** + * Packet Number Register - Bank 2 - Offset 2 + **************************************************************************** + */ +#define LAN91C96_PNR_TX (0x1FU << 0) + +/* + **************************************************************************** + * Allocation Result Register - Bank 2 - Offset 3 + **************************************************************************** + */ +#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0) +#define LAN91C96_ARR_FAILED (0x1U << 7) + +/* + **************************************************************************** + * FIFO Ports Register - Bank 2 - Offset 4 + **************************************************************************** + */ +#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0) +#define LAN91C96_FIFO_TEMPTY (0x1U << 7) +#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8) +#define LAN91C96_FIFO_RXEMPTY (0x1U << 15) + +/* + **************************************************************************** + * Pointer Register - Bank 2 - Offset 6 + **************************************************************************** + */ +#define LAN91C96_PTR_LOW (0xFFU << 0) +#define LAN91C96_PTR_HIGH (0x7U << 8) +#define LAN91C96_PTR_AUTO_TX (0x1U << 11) +#define LAN91C96_PTR_ETEN (0x1U << 12) +#define LAN91C96_PTR_READ (0x1U << 13) +#define LAN91C96_PTR_AUTO_INCR (0x1U << 14) +#define LAN91C96_PTR_RCV (0x1U << 15) + +#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ + LAN91C96_PTR_AUTO_INCR | \ + LAN91C96_PTR_READ) + +/* + **************************************************************************** + * Data Register - Bank 2 - Offset 8 + **************************************************************************** + */ +#define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */ +#define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */ + +/* + **************************************************************************** + * Interrupt Status Register - Bank 2 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_IST_RCV_INT (0x1U << 0) +#define LAN91C96_IST_TX_INT (0x1U << 1) +#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2) +#define LAN91C96_IST_ALLOC_INT (0x1U << 3) +#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4) +#define LAN91C96_IST_EPH_INT (0x1U << 5) +#define LAN91C96_IST_ERCV_INT (0x1U << 6) +#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7) + +/* + **************************************************************************** + * Interrupt Acknowledge Register - Bank 2 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_ACK_TX_INT (0x1U << 1) +#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2) +#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4) +#define LAN91C96_ACK_ERCV_INT (0x1U << 6) + +/* + **************************************************************************** + * Interrupt Mask Register - Bank 2 - Offset 13 + **************************************************************************** + */ +#define LAN91C96_MSK_RCV_INT (0x1U << 0) +#define LAN91C96_MSK_TX_INT (0x1U << 1) +#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2) +#define LAN91C96_MSK_ALLOC_INT (0x1U << 3) +#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4) +#define LAN91C96_MSK_EPH_INT (0x1U << 5) +#define LAN91C96_MSK_ERCV_INT (0x1U << 6) +#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7) + +/* + **************************************************************************** + * Bank 3 Register Map in I/O Space + ************************************************************************** + */ +#define LAN91C96_MGMT_MDO (0x1U << 0) +#define LAN91C96_MGMT_MDI (0x1U << 1) +#define LAN91C96_MGMT_MCLK (0x1U << 2) +#define LAN91C96_MGMT_MDOE (0x1U << 3) +#define LAN91C96_MGMT_LOW_ID (0x3U << 4) +#define LAN91C96_MGMT_IOS0 (0x1U << 8) +#define LAN91C96_MGMT_IOS1 (0x1U << 9) +#define LAN91C96_MGMT_IOS2 (0x1U << 10) +#define LAN91C96_MGMT_nXNDEC (0x1U << 11) +#define LAN91C96_MGMT_HIGH_ID (0x3U << 12) + +/* + **************************************************************************** + * Revision Register - Bank 3 - Offset 10 + **************************************************************************** + */ +#define LAN91C96_REV_REVID (0xFU << 0) +#define LAN91C96_REV_CHIPID (0xFU << 4) + +/* + **************************************************************************** + * Early RCV Register - Bank 3 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0) +#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7) + +/* + **************************************************************************** + * PCMCIA Configuration Registers + **************************************************************************** + */ +#define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */ +#define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */ + +/* + **************************************************************************** + * PCMCIA Ethernet Configuration Option Register (ECOR) + **************************************************************************** + */ +#define LAN91C96_ECOR_ENABLE (0x1U << 0) +#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2) +#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6) +#define LAN91C96_ECOR_SRESET (0x1U << 7) + +/* + **************************************************************************** + * PCMCIA Ethernet Configuration and Status Register (ECSR) + **************************************************************************** + */ +#define LAN91C96_ECSR_INTR (0x1U << 1) +#define LAN91C96_ECSR_PWRDWN (0x1U << 2) +#define LAN91C96_ECSR_IOIS8 (0x1U << 5) + +/* + **************************************************************************** + * Receive Frame Status Word - See page 38 of the LAN91C96 specification. + **************************************************************************** + */ +#define LAN91C96_TOO_SHORT (0x1U << 10) +#define LAN91C96_TOO_LONG (0x1U << 11) +#define LAN91C96_ODD_FRM (0x1U << 12) +#define LAN91C96_BAD_CRC (0x1U << 13) +#define LAN91C96_BROD_CAST (0x1U << 14) +#define LAN91C96_ALGN_ERR (0x1U << 15) + +#define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR) + +/* + **************************************************************************** + * Default MAC Address + **************************************************************************** + */ +#define MAC_DEF_HI 0x0800 +#define MAC_DEF_MED 0x3333 +#define MAC_DEF_LO 0x0100 + +/* + **************************************************************************** + * Default I/O Signature - 0x33 + **************************************************************************** + */ +#define LAN91C96_LOW_SIGNATURE (0x33U << 0) +#define LAN91C96_HIGH_SIGNATURE (0x33U << 8) +#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) + +#define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */ +#define ETHERNET_MAX_LENGTH 1514 + + +/*------------------------------------------------------------------------- + * I define some macros to make it easier to do somewhat common + * or slightly complicated, repeated tasks. + *------------------------------------------------------------------------- + */ + +/* select a register bank, 0 to 3 */ + +#define SMC_SELECT_BANK(x) { SMC_outw( x, LAN91C96_BANK_SELECT ); } + +/* this enables an interrupt in the interrupt mask register */ +#define SMC_ENABLE_INT(x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(2);\ + mask = SMC_inb( LAN91C96_INT_MASK );\ + mask |= (x);\ + SMC_outb( mask, LAN91C96_INT_MASK ); \ +} + +/* this disables an interrupt from the interrupt mask register */ + +#define SMC_DISABLE_INT(x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(2);\ + mask = SMC_inb( LAN91C96_INT_MASK );\ + mask &= ~(x);\ + SMC_outb( mask, LAN91C96_INT_MASK ); \ +} + +/*---------------------------------------------------------------------- + * Define the interrupts that I want to receive from the card + * + * I want: + * LAN91C96_IST_EPH_INT, for nasty errors + * LAN91C96_IST_RCV_INT, for happy received packets + * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver + *------------------------------------------------------------------------- + */ +#define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT) + +#endif /* _LAN91C96_H_ */ diff --git a/drivers/mw_eeprom.c b/drivers/mw_eeprom.c new file mode 100644 index 0000000..2a1f489 --- /dev/null +++ b/drivers/mw_eeprom.c @@ -0,0 +1,241 @@ +/* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */ + +#include +#include + + +#ifdef CONFIG_MW_EEPROM + +/* + * Serial EEPROM opcodes, including start bit + */ +#define EEP_OPC_ERASE 0x7 /* 3-bit opcode */ +#define EEP_OPC_WRITE 0x5 /* 3-bit opcode */ +#define EEP_OPC_READ 0x6 /* 3-bit opcode */ + +#define EEP_OPC_ERASE_ALL 0x12 /* 5-bit opcode */ +#define EEP_OPC_ERASE_EN 0x13 /* 5-bit opcode */ +#define EEP_OPC_WRITE_ALL 0x11 /* 5-bit opcode */ +#define EEP_OPC_ERASE_DIS 0x10 /* 5-bit opcode */ + +static int addrlen; + +static void mw_eeprom_select(int dev) +{ + ssi_set_interface(2048, 0, 0, 0); + ssi_chip_select(0); + udelay(1); + ssi_chip_select(dev); + udelay(1); +} + +static int mw_eeprom_size(int dev) +{ + int x; + u16 res; + + mw_eeprom_select(dev); + ssi_tx_byte(EEP_OPC_READ); + + res = ssi_txrx_byte(0) << 8; + res |= ssi_rx_byte(); + for (x = 0; x < 16; x++) { + if (! (res & 0x8000)) { + break; + } + res <<= 1; + } + ssi_chip_select(0); + + return x; +} + +int mw_eeprom_erase_enable(int dev) +{ + mw_eeprom_select(dev); + ssi_tx_byte(EEP_OPC_ERASE_EN); + ssi_tx_byte(0); + udelay(1); + ssi_chip_select(0); + + return 0; +} + +int mw_eeprom_erase_disable(int dev) +{ + mw_eeprom_select(dev); + ssi_tx_byte(EEP_OPC_ERASE_DIS); + ssi_tx_byte(0); + udelay(1); + ssi_chip_select(0); + + return 0; +} + + +u32 mw_eeprom_read_word(int dev, int addr) +{ + u16 rcv; + u16 res; + int bits; + + mw_eeprom_select(dev); + ssi_tx_byte((EEP_OPC_READ << 5) | ((addr >> (addrlen - 5)) & 0x1f)); + rcv = ssi_txrx_byte(addr << (13 - addrlen)); + res = rcv << (16 - addrlen); + bits = 4 + addrlen; + + while (bits>0) { + rcv = ssi_rx_byte(); + if (bits > 7) { + res |= rcv << (bits - 8); + } else { + res |= rcv >> (8 - bits); + } + bits -= 8; + } + + ssi_chip_select(0); + + return res; +} + +int mw_eeprom_write_word(int dev, int addr, u16 data) +{ + u8 byte1=0; + u8 byte2=0; + + mw_eeprom_erase_enable(dev); + mw_eeprom_select(dev); + + switch (addrlen) { + case 6: + byte1 = EEP_OPC_WRITE >> 2; + byte2 = (EEP_OPC_WRITE << 6)&0xc0; + byte2 |= addr; + break; + case 7: + byte1 = EEP_OPC_WRITE >> 1; + byte2 = (EEP_OPC_WRITE << 7)&0x80; + byte2 |= addr; + break; + case 8: + byte1 = EEP_OPC_WRITE; + byte2 = addr; + break; + case 9: + byte1 = EEP_OPC_WRITE << 1; + byte1 |= addr >> 8; + byte2 = addr & 0xff; + break; + case 10: + byte1 = EEP_OPC_WRITE << 2; + byte1 |= addr >> 8; + byte2 = addr & 0xff; + break; + default: + printf("Unsupported number of address bits: %d\n", addrlen); + return -1; + + } + + ssi_tx_byte(byte1); + ssi_tx_byte(byte2); + ssi_tx_byte(data >> 8); + ssi_tx_byte(data & 0xff); + ssi_chip_select(0); + udelay(10000); /* Worst case */ + mw_eeprom_erase_disable(dev); + + return 0; +} + + +int mw_eeprom_write(int dev, int addr, u8 *buffer, int len) +{ + int done; + + done = 0; + if (addr & 1) { + u16 temp = mw_eeprom_read_word(dev, addr >> 1); + temp &= 0xff00; + temp |= buffer[0]; + + mw_eeprom_write_word(dev, addr >> 1, temp); + len--; + addr++; + buffer++; + done++; + } + + while (len <= 2) { + mw_eeprom_write_word(dev, addr >> 1, *(u16*)buffer); + len-=2; + addr+=2; + buffer+=2; + done+=2; + } + + if (len) { + u16 temp = mw_eeprom_read_word(dev, addr >> 1); + temp &= 0x00ff; + temp |= buffer[0] << 8; + + mw_eeprom_write_word(dev, addr >> 1, temp); + len--; + addr++; + buffer++; + done++; + } + + return done; +} + + +int mw_eeprom_read(int dev, int addr, u8 *buffer, int len) +{ + int done; + + done = 0; + if (addr & 1) { + u16 temp = mw_eeprom_read_word(dev, addr >> 1); + buffer[0]= temp & 0xff; + + len--; + addr++; + buffer++; + done++; + } + + while (len <= 2) { + *(u16*)buffer = mw_eeprom_read_word(dev, addr >> 1); + len-=2; + addr+=2; + buffer+=2; + done+=2; + } + + if (len) { + u16 temp = mw_eeprom_read_word(dev, addr >> 1); + buffer[0] = temp >> 8; + + len--; + addr++; + buffer++; + done++; + } + + return done; +} + +int mw_eeprom_probe(int dev) +{ + addrlen = mw_eeprom_size(dev); + + if (addrlen < 6 || addrlen > 10) { + return -1; + } + return 0; +} + +#endif diff --git a/drivers/natsemi.c b/drivers/natsemi.c new file mode 100644 index 0000000..b009db6 --- /dev/null +++ b/drivers/natsemi.c @@ -0,0 +1,882 @@ +/* + natsemi.c: A U-Boot driver for the NatSemi DP8381x series. + Author: Mark A. Rakes (mark_rakes@vivato.net) + + Adapted from an Etherboot driver written by: + + Copyright (C) 2001 Entity Cyber, Inc. + + This development of this Etherboot driver was funded by + + Sicom Systems: http://www.sicompos.com/ + + Author: Marty Connor (mdc@thinguin.org) + Adapted from a Linux driver which was written by Donald Becker + + This software may be used and distributed according to the terms + of the GNU Public License (GPL), incorporated herein by reference. + + Original Copyright Notice: + + Written/copyright 1999-2001 by Donald Becker. + + This software may be used and distributed according to the terms of + the GNU General Public License (GPL), incorporated herein by reference. + Drivers based on or derived from this code fall under the GPL and must + retain the authorship, copyright and license notice. This file is not + a complete program and may only be used when the entire operating + system is licensed under the GPL. License for under other terms may be + available. Contact the original author for details. + + The original author may be reached as becker@scyld.com, or at + Scyld Computing Corporation + 410 Severn Ave., Suite 210 + Annapolis MD 21403 + + Support information and updates available at + http://www.scyld.com/network/netsemi.html + + References: + http://www.scyld.com/expert/100mbps.html + http://www.scyld.com/expert/NWay.html + Datasheet is available from: + http://www.national.com/pf/DP/DP83815.html +*/ + +/* Revision History + * October 2002 mar 1.0 + * Initial U-Boot Release. Tested with Netgear FA311 board + * and dp83815 chipset on custom board +*/ + +/* Includes */ +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_NATSEMI) + +/* defines */ +#define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/ + +#define DSIZE 0x00000FFF +#define ETH_ALEN 6 +#define CRC_SIZE 4 +#define TOUT_LOOP 500000 +#define TX_BUF_SIZE 1536 +#define RX_BUF_SIZE 1536 +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ + +/* Offsets to the device registers. + Unlike software-only systems, device drivers interact with complex hardware. + It's not useful to define symbolic names for every register bit in the + device. */ +enum register_offsets { + ChipCmd = 0x00, + ChipConfig = 0x04, + EECtrl = 0x08, + IntrMask = 0x14, + IntrEnable = 0x18, + TxRingPtr = 0x20, + TxConfig = 0x24, + RxRingPtr = 0x30, + RxConfig = 0x34, + ClkRun = 0x3C, + RxFilterAddr = 0x48, + RxFilterData = 0x4C, + SiliconRev = 0x58, + PCIPM = 0x44, + BasicControl = 0x80, + BasicStatus = 0x84, + /* These are from the spec, around page 78... on a separate table. */ + PGSEL = 0xCC, + PMDCSR = 0xE4, + TSTDAT = 0xFC, + DSPCFG = 0xF4, + SDCFG = 0x8C +}; + +/* Bit in ChipCmd. */ +enum ChipCmdBits { + ChipReset = 0x100, + RxReset = 0x20, + TxReset = 0x10, + RxOff = 0x08, + RxOn = 0x04, + TxOff = 0x02, + TxOn = 0x01 +}; + +enum ChipConfigBits { + LinkSts = 0x80000000, + HundSpeed = 0x40000000, + FullDuplex = 0x20000000, + TenPolarity = 0x10000000, + AnegDone = 0x08000000, + AnegEnBothBoth = 0x0000E000, + AnegDis100Full = 0x0000C000, + AnegEn100Both = 0x0000A000, + AnegDis100Half = 0x00008000, + AnegEnBothHalf = 0x00006000, + AnegDis10Full = 0x00004000, + AnegEn10Both = 0x00002000, + DuplexMask = 0x00008000, + SpeedMask = 0x00004000, + AnegMask = 0x00002000, + AnegDis10Half = 0x00000000, + ExtPhy = 0x00001000, + PhyRst = 0x00000400, + PhyDis = 0x00000200, + BootRomDisable = 0x00000004, + BEMode = 0x00000001, +}; + +enum TxConfig_bits { + TxDrthMask = 0x3f, + TxFlthMask = 0x3f00, + TxMxdmaMask = 0x700000, + TxMxdma_512 = 0x0, + TxMxdma_4 = 0x100000, + TxMxdma_8 = 0x200000, + TxMxdma_16 = 0x300000, + TxMxdma_32 = 0x400000, + TxMxdma_64 = 0x500000, + TxMxdma_128 = 0x600000, + TxMxdma_256 = 0x700000, + TxCollRetry = 0x800000, + TxAutoPad = 0x10000000, + TxMacLoop = 0x20000000, + TxHeartIgn = 0x40000000, + TxCarrierIgn = 0x80000000 +}; + +enum RxConfig_bits { + RxDrthMask = 0x3e, + RxMxdmaMask = 0x700000, + RxMxdma_512 = 0x0, + RxMxdma_4 = 0x100000, + RxMxdma_8 = 0x200000, + RxMxdma_16 = 0x300000, + RxMxdma_32 = 0x400000, + RxMxdma_64 = 0x500000, + RxMxdma_128 = 0x600000, + RxMxdma_256 = 0x700000, + RxAcceptLong = 0x8000000, + RxAcceptTx = 0x10000000, + RxAcceptRunt = 0x40000000, + RxAcceptErr = 0x80000000 +}; + +/* Bits in the RxMode register. */ +enum rx_mode_bits { + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0xC0000000, + AcceptMulticast = 0x00200000, + AcceptAllMulticast = 0x20000000, + AcceptAllPhys = 0x10000000, + AcceptMyPhys = 0x08000000 +}; + +typedef struct _BufferDesc { + u32 link; + vu_long cmdsts; + u32 bufptr; + u32 software_use; +} BufferDesc; + +/* Bits in network_desc.status */ +enum desc_status_bits { + DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000, + DescNoCRC = 0x10000000, DescPktOK = 0x08000000, + DescSizeMask = 0xfff, + + DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000, + DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000, + DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000, + DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000, + + DescRxAbort = 0x04000000, DescRxOver = 0x02000000, + DescRxDest = 0x01800000, DescRxLong = 0x00400000, + DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000, + DescRxCRC = 0x00080000, DescRxAlign = 0x00040000, + DescRxLoop = 0x00020000, DesRxColl = 0x00010000, +}; + +/* Globals */ +#ifdef NATSEMI_DEBUG +static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */ +#endif +static u32 SavedClkRun; +static unsigned int cur_rx; +static unsigned int advertising; +static unsigned int rx_config; +static unsigned int tx_config; + +/* Note: transmit and receive buffers and descriptors must be + longword aligned */ +static BufferDesc txd __attribute__ ((aligned(4))); +static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4))); + +static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4))); +static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE] + __attribute__ ((aligned(4))); + +/* Function Prototypes */ +#if 0 +static void write_eeprom(struct eth_device *dev, long addr, int location, + short value); +#endif +static int read_eeprom(struct eth_device *dev, long addr, int location); +static int mdio_read(struct eth_device *dev, int phy_id, int location); +static int natsemi_init(struct eth_device *dev, bd_t * bis); +static void natsemi_reset(struct eth_device *dev); +static void natsemi_init_rxfilter(struct eth_device *dev); +static void natsemi_init_txd(struct eth_device *dev); +static void natsemi_init_rxd(struct eth_device *dev); +static void natsemi_set_rx_mode(struct eth_device *dev); +static void natsemi_check_duplex(struct eth_device *dev); +static int natsemi_send(struct eth_device *dev, volatile void *packet, + int length); +static int natsemi_poll(struct eth_device *dev); +static void natsemi_disable(struct eth_device *dev); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815}, + {} +}; + +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +static inline int +INW(struct eth_device *dev, u_long addr) +{ + return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); +} + +static int +INL(struct eth_device *dev, u_long addr) +{ + return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); +} + +static inline void +OUTW(struct eth_device *dev, int command, u_long addr) +{ + *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); +} + +static inline void +OUTL(struct eth_device *dev, int command, u_long addr) +{ + *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); +} + +/* + * Function: natsemi_initialize + * + * Description: Retrieves the MAC address of the card, and sets up some + * globals required by other routines, and initializes the NIC, making it + * ready to send and receive packets. + * + * Side effects: + * leaves the natsemi initialized, and ready to recieve packets. + * + * Returns: struct eth_device *: pointer to NIC data structure + */ + +int +natsemi_initialize(bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase, status, chip_config; + int i, idx = 0; + int prev_eedata; + u32 tmp; + + while (1) { + /* Find PCI device(s) */ + if ((devno = pci_find_devices(supported, idx++)) < 0) { + break; + } + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */ + + pci_write_config_dword(devno, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled. */ + pci_read_config_dword(devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEM access.\n"); + continue; + } else if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + dev = (struct eth_device *) malloc(sizeof *dev); + + sprintf(dev->name, "dp83815#%d", card_number); + dev->iobase = bus_to_phys(iobase); +#ifdef NATSEMI_DEBUG + printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase); +#endif + dev->priv = (void *) devno; + dev->init = natsemi_init; + dev->halt = natsemi_disable; + dev->send = natsemi_send; + dev->recv = natsemi_poll; + + eth_register(dev); + + card_number++; + + /* Set the latency timer for value. */ + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); + + udelay(10 * 1000); + + /* natsemi has a non-standard PM control register + * in PCI config space. Some boards apparently need + * to be brought to D0 in this manner. */ + pci_read_config_dword(devno, PCIPM, &tmp); + if (tmp & (0x03 | 0x100)) { + /* D0 state, disable PME assertion */ + u32 newtmp = tmp & ~(0x03 | 0x100); + pci_write_config_dword(devno, PCIPM, newtmp); + } + + printf("natsemi: EEPROM contents:\n"); + for (i = 0; i <= EEPROM_SIZE; i++) { + short eedata = read_eeprom(dev, EECtrl, i); + printf(" %04hx", eedata); + } + printf("\n"); + + /* get MAC address */ + prev_eedata = read_eeprom(dev, EECtrl, 6); + for (i = 0; i < 3; i++) { + int eedata = read_eeprom(dev, EECtrl, i + 7); + dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15); + dev->enetaddr[i*2+1] = eedata >> 7; + prev_eedata = eedata; + } + + /* Reset the chip to erase any previous misconfiguration. */ + OUTL(dev, ChipReset, ChipCmd); + + advertising = mdio_read(dev, 1, 4); + chip_config = INL(dev, ChipConfig); +#ifdef NATSEMI_DEBUG + printf("%s: Transceiver status %#08X advertising %#08X\n", + dev->name, (int) INL(dev, BasicStatus), advertising); + printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n", + dev->name, chip_config & AnegMask ? "enabled, advertise" : + "disabled, force", chip_config & SpeedMask ? "0" : "", + chip_config & DuplexMask ? "full" : "half"); +#endif + chip_config |= AnegEnBothBoth; +#ifdef NATSEMI_DEBUG + printf("%s: changed to autoneg. %s 10%s %s duplex.\n", + dev->name, chip_config & AnegMask ? "enabled, advertise" : + "disabled, force", chip_config & SpeedMask ? "0" : "", + chip_config & DuplexMask ? "full" : "half"); +#endif + /*write new autoneg bits, reset phy*/ + OUTL(dev, (chip_config | PhyRst), ChipConfig); + /*un-reset phy*/ + OUTL(dev, chip_config, ChipConfig); + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + SavedClkRun = INL(dev, ClkRun); + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + } + return card_number; +} + +/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. + The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */ + +/* Delay between EEPROM clock transitions. + No extra delay is needed with 33Mhz PCI, but future 66Mhz + access may need a delay. */ +#define eeprom_delay(ee_addr) INL(dev, ee_addr) + +enum EEPROM_Ctrl_Bits { + EE_ShiftClk = 0x04, + EE_DataIn = 0x01, + EE_ChipSelect = 0x08, + EE_DataOut = 0x02 +}; + +#define EE_Write0 (EE_ChipSelect) +#define EE_Write1 (EE_ChipSelect | EE_DataIn) +/* The EEPROM commands include the alway-set leading bit. */ +enum EEPROM_Cmds { + EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6), + EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6), +}; + +#if 0 +static void +write_eeprom(struct eth_device *dev, long addr, int location, short value) +{ + int i; + int ee_addr = (typeof(ee_addr))addr; + short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/ + short write_cmd = location | EE_WriteCmd; + +#ifdef NATSEMI_DEBUG + printf("write_eeprom: %08x, %04hx, %04hx\n", + dev->iobase + ee_addr, write_cmd, value); +#endif + /* Shift the write enable command bits out. */ + for (i = 9; i >= 0; i--) { + short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, cmdval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, cmdval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + + OUTL(dev, 0, ee_addr); /*bring chip select low*/ + OUTL(dev, EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + + /* Shift the write command bits out. */ + for (i = 9; i >= 0; i--) { + short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, cmdval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, cmdval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + + for (i = 0; i < 16; i++) { + short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, cmdval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, cmdval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + + OUTL(dev, 0, ee_addr); /*bring chip select low*/ + OUTL(dev, EE_ShiftClk, ee_addr); + for (i = 0; i < 200000; i++) { + OUTL(dev, EE_Write0, ee_addr); /*poll for done*/ + if (INL(dev, ee_addr) & EE_DataOut) { + break; /*finished*/ + } + } + eeprom_delay(ee_addr); + + /* Terminate the EEPROM access. */ + OUTL(dev, EE_Write0, ee_addr); + OUTL(dev, 0, ee_addr); + return; +} +#endif + +static int +read_eeprom(struct eth_device *dev, long addr, int location) +{ + int i; + int retval = 0; + int ee_addr = (typeof(ee_addr))addr; + int read_cmd = location | EE_ReadCmd; + + OUTL(dev, EE_Write0, ee_addr); + + /* Shift the read command bits out. */ + for (i = 10; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, dataval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, dataval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + OUTL(dev, EE_ChipSelect, ee_addr); + eeprom_delay(ee_addr); + + for (i = 0; i < 16; i++) { + OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0; + OUTL(dev, EE_ChipSelect, ee_addr); + eeprom_delay(ee_addr); + } + + /* Terminate the EEPROM access. */ + OUTL(dev, EE_Write0, ee_addr); + OUTL(dev, 0, ee_addr); +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("read_eeprom: %08x, %08x, retval %08x\n", + dev->iobase + ee_addr, read_cmd, retval); +#endif + return retval; +} + +/* MII transceiver control section. + The 83815 series has an internal transceiver, and we present the + management registers as if they were MII connected. */ + +static int +mdio_read(struct eth_device *dev, int phy_id, int location) +{ + if (phy_id == 1 && location < 32) + return INL(dev, BasicControl+(location<<2))&0xffff; + else + return 0xffff; +} + +/* Function: natsemi_init + * + * Description: resets the ethernet controller chip and configures + * registers and data structures required for sending and receiving packets. + * + * Arguments: struct eth_device *dev: NIC data structure + * + * returns: int. + */ + +static int +natsemi_init(struct eth_device *dev, bd_t * bis) +{ + + natsemi_reset(dev); + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + + natsemi_init_rxfilter(dev); + natsemi_init_txd(dev); + natsemi_init_rxd(dev); + + /* Configure the PCI bus bursts and FIFO thresholds. */ + tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002); + rx_config = RxMxdma_256 | 0x20; + +#ifdef NATSEMI_DEBUG + printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config); + printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config); +#endif + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); + + natsemi_check_duplex(dev); + natsemi_set_rx_mode(dev); + + OUTL(dev, (RxOn | TxOn), ChipCmd); + return 1; +} + +/* + * Function: natsemi_reset + * + * Description: soft resets the controller chip + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ +static void +natsemi_reset(struct eth_device *dev) +{ + OUTL(dev, ChipReset, ChipCmd); + + /* On page 78 of the spec, they recommend some settings for "optimum + performance" to be done in sequence. These settings optimize some + of the 100Mbit autodetection circuitry. Also, we only want to do + this for rev C of the chip. */ + if (INL(dev, SiliconRev) == 0x302) { + OUTW(dev, 0x0001, PGSEL); + OUTW(dev, 0x189C, PMDCSR); + OUTW(dev, 0x0000, TSTDAT); + OUTW(dev, 0x5040, DSPCFG); + OUTW(dev, 0x008C, SDCFG); + } + /* Disable interrupts using the mask. */ + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); +} + +/* Function: natsemi_init_rxfilter + * + * Description: sets receive filter address to our MAC address + * + * Arguments: struct eth_device *dev: NIC data structure + * + * returns: void. + */ + +static void +natsemi_init_rxfilter(struct eth_device *dev) +{ + int i; + + for (i = 0; i < ETH_ALEN; i += 2) { + OUTL(dev, i, RxFilterAddr); + OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8), + RxFilterData); + } +} + +/* + * Function: natsemi_init_txd + * + * Description: initializes the Tx descriptor + * + * Arguments: struct eth_device *dev: NIC data structure + * + * returns: void. + */ + +static void +natsemi_init_txd(struct eth_device *dev) +{ + txd.link = (u32) 0; + txd.cmdsts = (u32) 0; + txd.bufptr = (u32) & txb[0]; + + /* load Transmit Descriptor Register */ + OUTL(dev, (u32) & txd, TxRingPtr); +#ifdef NATSEMI_DEBUG + printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n", + INL(dev, TxRingPtr)); +#endif +} + +/* Function: natsemi_init_rxd + * + * Description: initializes the Rx descriptor ring + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ + +static void +natsemi_init_rxd(struct eth_device *dev) +{ + int i; + + cur_rx = 0; + + /* init RX descriptor */ + for (i = 0; i < NUM_RX_DESC; i++) { + rxd[i].link = + cpu_to_le32((i + 1 < + NUM_RX_DESC) ? (u32) & rxd[i + + 1] : (u32) & + rxd[0]); + rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE); + rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]); +#ifdef NATSEMI_DEBUG + printf + ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n", + i, &rxd[i], le32_to_cpu(rxd[i].link), + rxd[i].cmdsts, rxd[i].bufptr); +#endif + } + + /* load Receive Descriptor Register */ + OUTL(dev, (u32) & rxd[0], RxRingPtr); + +#ifdef NATSEMI_DEBUG + printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n", + INL(dev, RxRingPtr)); +#endif +} + +/* Function: natsemi_set_rx_mode + * + * Description: + * sets the receive mode to accept all broadcast packets and packets + * with our MAC address, and reject all multicast packets. + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ + +static void +natsemi_set_rx_mode(struct eth_device *dev) +{ + u32 rx_mode = AcceptBroadcast | AcceptMyPhys; + + OUTL(dev, rx_mode, RxFilterAddr); +} + +static void +natsemi_check_duplex(struct eth_device *dev) +{ + int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0; + +#ifdef NATSEMI_DEBUG + printf("%s: Setting %s-duplex based on negotiated link" + " capability.\n", dev->name, duplex ? "full" : "half"); +#endif + if (duplex) { + rx_config |= RxAcceptTx; + tx_config |= (TxCarrierIgn | TxHeartIgn); + } else { + rx_config &= ~RxAcceptTx; + tx_config &= ~(TxCarrierIgn | TxHeartIgn); + } + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); +} + +/* Function: natsemi_send + * + * Description: transmits a packet and waits for completion or timeout. + * + * Returns: void. */ +static int +natsemi_send(struct eth_device *dev, volatile void *packet, int length) +{ + u32 i, status = 0; + u32 tx_status = 0; + vu_long *res = (vu_long *)&tx_status; + + /* Stop the transmitter */ + OUTL(dev, TxOff, ChipCmd); + +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("natsemi_send: sending %d bytes\n", (int) length); +#endif + + /* set the transmit buffer descriptor and enable Transmit State Machine */ + txd.link = cpu_to_le32(0); + txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet)); + txd.cmdsts = cpu_to_le32(DescOwn | length); + + /* load Transmit Descriptor Register */ + OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr); +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("natsemi_send: TX descriptor register loaded with: %#08X\n", + INL(dev, TxRingPtr)); +#endif + /* restart the transmitter */ + OUTL(dev, TxOn, ChipCmd); + + for (i = 0; + (*res = le32_to_cpu(txd.cmdsts)) & DescOwn; + i++) { + if (i >= TOUT_LOOP) { + printf + ("%s: tx error buffer not ready: txd.cmdsts == %#X\n", + dev->name, tx_status); + goto Done; + } + } + + if (!(tx_status & DescPktOK)) { + printf("natsemi_send: Transmit error, Tx status %X.\n", + tx_status); + goto Done; + } + + status = 1; + Done: + return status; +} + +/* Function: natsemi_poll + * + * Description: checks for a received packet and returns it if found. + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: 1 if packet was received. + * 0 if no packet was received. + * + * Side effects: + * Returns (copies) the packet to the array dev->packet. + * Returns the length of the packet. + */ + +static int +natsemi_poll(struct eth_device *dev) +{ + int retstat = 0; + int length = 0; + u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts); + + if (!(rx_status & (u32) DescOwn)) + return retstat; +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n", + cur_rx, rx_status); +#endif + length = (rx_status & DSIZE) - CRC_SIZE; + + if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) { + printf + ("natsemi_poll: Corrupted packet received, buffer status = %X\n", + rx_status); + retstat = 0; + } else { /* give packet to higher level routine */ + NetReceive((rxb + cur_rx * RX_BUF_SIZE), length); + retstat = 1; + } + + /* return the descriptor and buffer to receive ring */ + rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE); + rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]); + + if (++cur_rx == NUM_RX_DESC) + cur_rx = 0; + + /* re-enable the potentially idle receive state machine */ + OUTL(dev, RxOn, ChipCmd); + + return retstat; +} + +/* Function: natsemi_disable + * + * Description: Turns off interrupts and stops Tx and Rx engines + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ + +static void +natsemi_disable(struct eth_device *dev) +{ + /* Disable interrupts using the mask. */ + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); + + /* Stop the chip's Tx and Rx processes. */ + OUTL(dev, RxOff | TxOff, ChipCmd); + + /* Restore PME enable bit */ + OUTL(dev, SavedClkRun, ClkRun); +} + +#endif diff --git a/drivers/ne2000.c b/drivers/ne2000.c new file mode 100644 index 0000000..b7ed876 --- /dev/null +++ b/drivers/ne2000.c @@ -0,0 +1,963 @@ +/* +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + + +========================================================================== + +dev/if_dp83902a.c + +Ethernet device driver for NS DP83902a ethernet controller + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### +------------------------------------------- +This file is part of eCos, the Embedded Configurable Operating System. +Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + +eCos is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2 or (at your option) any later version. + +eCos is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with eCos; if not, write to the Free Software Foundation, Inc., +59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + +As a special exception, if other files instantiate templates or use macros +or inline functions from this file, or you compile this file and link it +with other works to produce a work based on this file, this file does not +by itself cause the resulting work to be covered by the GNU General Public +License. However the source code for this file must still be made available +in accordance with section (3) of the GNU General Public License. + +This exception does not invalidate any other reasons why a work based on +this file might be covered by the GNU General Public License. + +Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +at http://sources.redhat.com/ecos/ecos-license/ +------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + +------------------------------------------- + +Portions of this software may have been derived from OpenBSD or other sources, +and are covered by the appropriate copyright disclaimers included herein. + +------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + +Author(s): gthomas +Contributors: gthomas, jskov, rsandifo +Date: 2001-06-13 +Purpose: +Description: + +FIXME: Will fail if pinged with large packets (1520 bytes) +Add promisc config +Add SNMP + +####DESCRIPTIONEND#### + + +========================================================================== + +*/ + +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_NE2000 + +/* wor around udelay resetting OCR */ +static void my_udelay(long us) { + long tmo; + + tmo = get_timer (0) + us * CFG_HZ / 1000000; /* will this be much greater than 0 ? */ + while (get_timer (0) < tmo); +} + +#define mdelay(n) my_udelay((n)*1000) + +/* forward definition of function used for the uboot interface */ +void uboot_push_packet_len(int len); +void uboot_push_tx_done(int key, int val); + +/* timeout for tx/rx in s */ +#define TOUT 5 + +#define ETHER_ADDR_LEN 6 + +/* + ------------------------------------------------------------------------ + Debugging details + + Set to perms of: + 0 disables all debug output + 1 for process debug output + 2 for added data IO output: get_reg, put_reg + 4 for packet allocation/free output + 8 for only startup status, so we can tell we're installed OK +*/ +/*#define DEBUG 0xf*/ +#define DEBUG 0 + +#if DEBUG & 1 +#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0) +#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0) +#else +#define DEBUG_FUNCTION() do {} while(0) +#define DEBUG_LINE() do {} while(0) +#endif + +#include "ne2000.h" + +#if DEBUG & 1 +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + +static dp83902a_priv_data_t nic; /* just one instance of the card supported */ + +static bool +dp83902a_init(void) +{ + dp83902a_priv_data_t *dp = &nic; + cyg_uint8* base; + int i; + + DEBUG_FUNCTION(); + + base = dp->base; + if (!base) return false; /* No device found */ + + DEBUG_LINE(); + + /* Prepare ESA */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ + /* Use the address from the serial EEPROM */ + for (i = 0; i < 6; i++) + DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ + + printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n", + "eeprom", + dp->esa[0], + dp->esa[1], + dp->esa[2], + dp->esa[3], + dp->esa[4], + dp->esa[5] ); + + return true; +} + +static void +dp83902a_stop(void) +{ + dp83902a_priv_data_t *dp = &nic; + cyg_uint8 *base = dp->base; + + DEBUG_FUNCTION(); + + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ + + dp->running = false; +} + +/* + This function is called to "start up" the interface. It may be called + multiple times, even when the hardware is already running. It will be + called whenever something "hardware oriented" changes and should leave + the hardware ready to send/receive packets. +*/ +static void +dp83902a_start(unsigned char * enaddr) +{ + dp83902a_priv_data_t *dp = &nic; + cyg_uint8 *base = dp->base; + int i; + + DEBUG_FUNCTION(); + + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_DCR, DP_DCR_INIT); + DP_OUT(base, DP_RBCH, 0); /* Remote byte count */ + DP_OUT(base, DP_RBCL, 0); + DP_OUT(base, DP_RCR, DP_RCR_MON); /* Accept no packets */ + DP_OUT(base, DP_TCR, DP_TCR_LOCAL); /* Transmitter [virtually] off */ + DP_OUT(base, DP_TPSR, dp->tx_buf1); /* Transmitter start page */ + dp->tx1 = dp->tx2 = 0; + dp->tx_next = dp->tx_buf1; + dp->tx_started = false; + DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ + DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */ + DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ + dp->rx_next = dp->rx_buf_start-1; + DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ + DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ + for (i = 0; i < ETHER_ADDR_LEN; i++) { + DP_OUT(base, DP_P1_PAR0+i, enaddr[i]); + } + /* Enable and start device */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */ + DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ + dp->running = true; +} + +/* + This routine is called to start the transmitter. It is split out from the + data handling routine so it may be called either when data becomes first + available or when an Tx interrupt occurs +*/ + +static void +dp83902a_start_xmit(int start_page, int len) +{ + dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic; + cyg_uint8 *base = dp->base; + + DEBUG_FUNCTION(); + +#if DEBUG & 1 + printf("Tx pkt %d len %d\n", start_page, len); + if (dp->tx_started) + printf("TX already started?!?\n"); +#endif + + DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE)); + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_TBCL, len & 0xFF); + DP_OUT(base, DP_TBCH, len >> 8); + DP_OUT(base, DP_TPSR, start_page); + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + + dp->tx_started = true; +} + +/* + This routine is called to send data to the hardware. It is known a-priori + that there is free buffer space (dp->tx_next). +*/ +static void +dp83902a_send(unsigned char *data, int total_len, unsigned long key) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + int len, start_page, pkt_len, i, isr; +#if DEBUG & 4 + int dx; +#endif + + DEBUG_FUNCTION(); + + len = pkt_len = total_len; + if (pkt_len < IEEE_8023_MIN_FRAME) pkt_len = IEEE_8023_MIN_FRAME; + + start_page = dp->tx_next; + if (dp->tx_next == dp->tx_buf1) { + dp->tx1 = start_page; + dp->tx1_len = pkt_len; + dp->tx1_key = key; + dp->tx_next = dp->tx_buf2; + } else { + dp->tx2 = start_page; + dp->tx2_len = pkt_len; + dp->tx2_key = key; + dp->tx_next = dp->tx_buf1; + } + +#if DEBUG & 5 + printf("TX prep page %d len %d\n", start_page, pkt_len); +#endif + + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + { + /* Dummy read. The manual sez something slightly different, */ + /* but the code is extended a bit to do what Hitachi's monitor */ + /* does (i.e., also read data). */ + + cyg_uint16 tmp; + int len = 1; + + DP_OUT(base, DP_RSAL, 0x100-len); + DP_OUT(base, DP_RSAH, (start_page-1) & 0xff); + DP_OUT(base, DP_RBCL, len); + DP_OUT(base, DP_RBCH, 0); + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START); + DP_IN_DATA(dp->data, tmp); + } + +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA + /* Stall for a bit before continuing to work around random data */ + /* corruption problems on some platforms. */ + CYGACC_CALL_IF_DELAY_US(1); +#endif + + /* Send data to device buffer(s) */ + DP_OUT(base, DP_RSAL, 0); + DP_OUT(base, DP_RSAH, start_page); + DP_OUT(base, DP_RBCL, pkt_len & 0xFF); + DP_OUT(base, DP_RBCH, pkt_len >> 8); + DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START); + + /* Put data into buffer */ +#if DEBUG & 4 + printf(" sg buf %08lx len %08x\n ", (unsigned long) data, len); + dx = 0; +#endif + while (len > 0) { +#if DEBUG & 4 + printf(" %02x", *data); + if (0 == (++dx % 16)) printf("\n "); +#endif + DP_OUT_DATA(dp->data, *data++); + len--; + } +#if DEBUG & 4 + printf("\n"); +#endif + if (total_len < pkt_len) { +#if DEBUG & 4 + printf(" + %d bytes of padding\n", pkt_len - total_len); +#endif + /* Padding to 802.3 length was required */ + for (i = total_len; i < pkt_len;) { + i++; + DP_OUT_DATA(dp->data, 0); + } + } + +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA + /* After last data write, delay for a bit before accessing the */ + /* device again, or we may get random data corruption in the last */ + /* datum (on some platforms). */ + CYGACC_CALL_IF_DELAY_US(1); +#endif + + /* Wait for DMA to complete */ + do { + DP_IN(base, DP_ISR, isr); + } while ((isr & DP_ISR_RDC) == 0); + /* Then disable DMA */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + + /* Start transmit if not already going */ + if (!dp->tx_started) { + if (start_page == dp->tx1) { + dp->tx_int = 1; /* Expecting interrupt from BUF1 */ + } else { + dp->tx_int = 2; /* Expecting interrupt from BUF2 */ + } + dp83902a_start_xmit(start_page, pkt_len); + } +} + +/* + This function is called when a packet has been received. It's job is + to prepare to unload the packet from the hardware. Once the length of + the packet is known, the upper layer of the driver can be told. When + the upper layer is ready to unload the packet, the internal function + 'dp83902a_recv' will be called to actually fetch it from the hardware. +*/ +static void +dp83902a_RxEvent(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + unsigned char rsr; + unsigned char rcv_hdr[4]; + int i, len, pkt, cur; + + DEBUG_FUNCTION(); + + DP_IN(base, DP_RSR, rsr); + while (true) { + /* Read incoming packet header */ + DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START); + DP_IN(base, DP_P1_CURP, cur); + DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_IN(base, DP_BNDRY, pkt); + + pkt += 1; + if (pkt == dp->rx_buf_end) + pkt = dp->rx_buf_start; + + if (pkt == cur) { + break; + } + DP_OUT(base, DP_RBCL, sizeof(rcv_hdr)); + DP_OUT(base, DP_RBCH, 0); + DP_OUT(base, DP_RSAL, 0); + DP_OUT(base, DP_RSAH, pkt); + if (dp->rx_next == pkt) { + if (cur == dp->rx_buf_start) + DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); + else + DP_OUT(base, DP_BNDRY, cur-1); /* Update pointer */ + return; + } + dp->rx_next = pkt; + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA + CYGACC_CALL_IF_DELAY_US(10); +#endif + + for (i = 0; i < sizeof(rcv_hdr);) { + DP_IN_DATA(dp->data, rcv_hdr[i++]); + } + +#if DEBUG & 5 + printf("rx hdr %02x %02x %02x %02x\n", + rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); +#endif + len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr); + uboot_push_packet_len(len); + if (rcv_hdr[1] == dp->rx_buf_start) + DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); + else + DP_OUT(base, DP_BNDRY, rcv_hdr[1]-1); /* Update pointer */ + } +} + +/* + This function is called as a result of the "eth_drv_recv()" call above. + It's job is to actually fetch data for a packet from the hardware once + memory buffers have been allocated for the packet. Note that the buffers + may come in pieces, using a scatter-gather list. This allows for more + efficient processing in the upper layers of the stack. +*/ +static void +dp83902a_recv(unsigned char *data, int len) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + int i, mlen; + cyg_uint8 saved_char = 0; + bool saved; +#if DEBUG & 4 + int dx; +#endif + + DEBUG_FUNCTION(); + +#if DEBUG & 5 + printf("Rx packet %d length %d\n", dp->rx_next, len); +#endif + + /* Read incoming packet data */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_RBCL, len & 0xFF); + DP_OUT(base, DP_RBCH, len >> 8); + DP_OUT(base, DP_RSAL, 4); /* Past header */ + DP_OUT(base, DP_RSAH, dp->rx_next); + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA + CYGACC_CALL_IF_DELAY_US(10); +#endif + + saved = false; + for (i = 0; i < 1; i++) { + if (data) { + mlen = len; +#if DEBUG & 4 + printf(" sg buf %08lx len %08x \n", (unsigned long) data, mlen); + dx = 0; +#endif + while (0 < mlen) { + /* Saved byte from previous loop? */ + if (saved) { + *data++ = saved_char; + mlen--; + saved = false; + continue; + } + + { + cyg_uint8 tmp; + DP_IN_DATA(dp->data, tmp); +#if DEBUG & 4 + printf(" %02x", tmp); + if (0 == (++dx % 16)) printf("\n "); +#endif + *data++ = tmp;; + mlen--; + } + } +#if DEBUG & 4 + printf("\n"); +#endif + } + } +} + +static void +dp83902a_TxEvent(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + unsigned char tsr; + unsigned long key; + + DEBUG_FUNCTION(); + + DP_IN(base, DP_TSR, tsr); + if (dp->tx_int == 1) { + key = dp->tx1_key; + dp->tx1 = 0; + } else { + key = dp->tx2_key; + dp->tx2 = 0; + } + /* Start next packet if one is ready */ + dp->tx_started = false; + if (dp->tx1) { + dp83902a_start_xmit(dp->tx1, dp->tx1_len); + dp->tx_int = 1; + } else if (dp->tx2) { + dp83902a_start_xmit(dp->tx2, dp->tx2_len); + dp->tx_int = 2; + } else { + dp->tx_int = 0; + } + /* Tell higher level we sent this packet */ + uboot_push_tx_done(key, 0); +} + +/* Read the tally counters to clear them. Called in response to a CNT */ +/* interrupt. */ +static void +dp83902a_ClearCounters(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + cyg_uint8 cnt1, cnt2, cnt3; + + DP_IN(base, DP_FER, cnt1); + DP_IN(base, DP_CER, cnt2); + DP_IN(base, DP_MISSED, cnt3); + DP_OUT(base, DP_ISR, DP_ISR_CNT); +} + +/* Deal with an overflow condition. This code follows the procedure set */ +/* out in section 7.0 of the datasheet. */ +static void +dp83902a_Overflow(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic; + cyg_uint8 *base = dp->base; + cyg_uint8 isr; + + /* Issue a stop command and wait 1.6ms for it to complete. */ + DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA); + CYGACC_CALL_IF_DELAY_US(1600); + + /* Clear the remote byte counter registers. */ + DP_OUT(base, DP_RBCL, 0); + DP_OUT(base, DP_RBCH, 0); + + /* Enter loopback mode while we clear the buffer. */ + DP_OUT(base, DP_TCR, DP_TCR_LOCAL); + DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA); + + /* Read in as many packets as we can and acknowledge any and receive */ + /* interrupts. Since the buffer has overflowed, a receive event of */ + /* some kind will have occured. */ + dp83902a_RxEvent(); + DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE); + + /* Clear the overflow condition and leave loopback mode. */ + DP_OUT(base, DP_ISR, DP_ISR_OFLW); + DP_OUT(base, DP_TCR, DP_TCR_NORMAL); + + /* If a transmit command was issued, but no transmit event has occured, */ + /* restart it here. */ + DP_IN(base, DP_ISR, isr); + if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) { + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + } +} + +static void +dp83902a_poll(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + unsigned char isr; + + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); + DP_IN(base, DP_ISR, isr); + while (0 != isr) { + /* The CNT interrupt triggers when the MSB of one of the error */ + /* counters is set. We don't much care about these counters, but */ + /* we should read their values to reset them. */ + if (isr & DP_ISR_CNT) { + dp83902a_ClearCounters(); + } + /* Check for overflow. It's a special case, since there's a */ + /* particular procedure that must be followed to get back into */ + /* a running state.a */ + if (isr & DP_ISR_OFLW) { + dp83902a_Overflow(); + } else { + /* Other kinds of interrupts can be acknowledged simply by */ + /* clearing the relevant bits of the ISR. Do that now, then */ + /* handle the interrupts we care about. */ + DP_OUT(base, DP_ISR, isr); /* Clear set bits */ + if (!dp->running) break; /* Is this necessary? */ + /* Check for tx_started on TX event since these may happen */ + /* spuriously it seems. */ + if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) { + dp83902a_TxEvent(); + } + if (isr & (DP_ISR_RxP|DP_ISR_RxE)) { + dp83902a_RxEvent(); + } + } + DP_IN(base, DP_ISR, isr); + } +} + +/* find prom (taken from pc_net_cs.c from Linux) */ + +#include "8390.h" + +typedef struct hw_info_t { + u_int offset; + u_char a0, a1, a2; + u_int flags; +} hw_info_t; + +#define DELAY_OUTPUT 0x01 +#define HAS_MISC_REG 0x02 +#define USE_BIG_BUF 0x04 +#define HAS_IBM_MISC 0x08 +#define IS_DL10019 0x10 +#define IS_DL10022 0x20 +#define HAS_MII 0x40 +#define USE_SHMEM 0x80 /* autodetected */ + +#define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */ +#define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */ +#define MII_PHYID_REV_MASK 0xfffffff0 +#define MII_PHYID_REG1 0x02 +#define MII_PHYID_REG2 0x03 + +static hw_info_t hw_info[] = { + { /* Accton EN2212 */ 0x0ff0, 0x00, 0x00, 0xe8, DELAY_OUTPUT }, + { /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 }, + { /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 }, + { /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94, + DELAY_OUTPUT | HAS_IBM_MISC }, + { /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 }, + { /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 }, + { /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 }, + { /* D-Link DE-650 */ 0x0040, 0x00, 0x80, 0xc8, 0 }, + { /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 }, + { /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 }, + { /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 }, + { /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 }, + { /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM FME */ 0x0374, 0x00, 0x04, 0xac, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 }, + { /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 }, + { /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 }, + { /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 }, + { /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 }, + { /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 }, + { /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 }, + { /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 }, + { /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 }, + { /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b, + DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF }, + { /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 }, + { /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 }, + { /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 }, + { /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 }, + { /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 } +}; + +#define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t)) + +static hw_info_t default_info = { 0, 0, 0, 0, 0 }; + +unsigned char dev_addr[6]; + +#define PCNET_CMD 0x00 +#define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */ +#define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */ +#define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */ + +unsigned long nic_base; + +static void pcnet_reset_8390(void) +{ + int i, r; + + PRINTK("nic base is %lx\n", nic_base); + +#if 1 + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); +#endif + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + + n2k_outb(n2k_inb(nic_base + PCNET_RESET), PCNET_RESET); + + for (i = 0; i < 100; i++) { + if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0) + break; + PRINTK("got %x in reset\n", r); + my_udelay(100); + } + n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */ + + if (i == 100) + printf("pcnet_reset_8390() did not complete.\n"); +} /* pcnet_reset_8390 */ + +static hw_info_t * get_prom(void ) { + unsigned char prom[32]; + int i, j; + struct { + u_char value, offset; + } program_seq[] = { + {E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/ + {0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */ + {0x00, EN0_RCNTLO}, /* Clear the count regs. */ + {0x00, EN0_RCNTHI}, + {0x00, EN0_IMR}, /* Mask completion irq. */ + {0xFF, EN0_ISR}, + {E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */ + {E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */ + {32, EN0_RCNTLO}, + {0x00, EN0_RCNTHI}, + {0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */ + {0x00, EN0_RSARHI}, + {E8390_RREAD+E8390_START, E8390_CMD}, + }; + + PRINTK("trying to get MAC via prom reading\n"); + + pcnet_reset_8390(); + + mdelay(10); + + for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++) + n2k_outb(program_seq[i].value, program_seq[i].offset); + + PRINTK("PROM:"); + for (i = 0; i < 32; i++) { + prom[i] = n2k_inb(PCNET_DATAPORT); + PRINTK(" %02x", prom[i]); + } + PRINTK("\n"); + for (i = 0; i < NR_INFO; i++) { + if ((prom[0] == hw_info[i].a0) && + (prom[2] == hw_info[i].a1) && + (prom[4] == hw_info[i].a2)) { + PRINTK("matched board %d\n", i); + break; + } + } + if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) { + for (j = 0; j < 6; j++) + dev_addr[j] = prom[j<<1]; + PRINTK("on exit i is %d/%ld\n", i, NR_INFO); + PRINTK("MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + dev_addr[0],dev_addr[1],dev_addr[2],dev_addr[3],dev_addr[4],dev_addr[5]); + return (i < NR_INFO) ? hw_info+i : &default_info; + } + return NULL; +} + +/* U-boot specific routines */ + +#define NB 5 + +static unsigned char *pbuf = NULL; +static int plen[NB]; +static int nrx = 0; + +static int pkey = -1; + +void uboot_push_packet_len(int len) { + PRINTK("pushed len = %d, nrx = %d\n", len, nrx); + if (len>=2000) { + printf("NE2000: packet too big\n"); + return; + } + if (nrx >= NB) { + printf("losing packets in rx\n"); + return; + } + plen[nrx] = len; + dp83902a_recv(&pbuf[nrx*2000], len); + nrx++; +} + +void uboot_push_tx_done(int key, int val) { + PRINTK("pushed key = %d\n", key); + pkey = key; +} + +int eth_init(bd_t *bd) { + static hw_info_t * r; + char ethaddr[20]; + + PRINTK("### eth_init\n"); + + if (!pbuf) { + pbuf = malloc(NB*2000); + if (!pbuf) { + printf("Cannot allocate rx buffers\n"); + return -1; + } + } + +#ifdef CONFIG_DRIVER_NE2000_CCR + { + volatile unsigned char *p = (volatile unsigned char *) CONFIG_DRIVER_NE2000_CCR; + + PRINTK("CCR before is %x\n", *p); + *p = CONFIG_DRIVER_NE2000_VAL; + PRINTK("CCR after is %x\n", *p); + } +#endif + + nic_base = CONFIG_DRIVER_NE2000_BASE; + nic.base = (cyg_uint8 *) CONFIG_DRIVER_NE2000_BASE; + + r = get_prom(); + if (!r) + return -1; + + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + dev_addr[0], dev_addr[1], + dev_addr[2], dev_addr[3], + dev_addr[4], dev_addr[5]) ; + PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr); + setenv ("ethaddr", ethaddr); + + +#define DP_DATA 0x10 + nic.data = nic.base + DP_DATA; + nic.tx_buf1 = 0x40; + nic.tx_buf2 = 0x48; + nic.rx_buf_start = 0x50; + nic.rx_buf_end = 0x80; + + if (dp83902a_init() == false) + return -1; + dp83902a_start(dev_addr); + return 0; +} + +void eth_halt() { + + PRINTK("### eth_halt\n"); + + dp83902a_stop(); +} + +int eth_rx() { + int j, tmo; + + PRINTK("### eth_rx\n"); + + tmo = get_timer (0) + TOUT * CFG_HZ; + while(1) { + dp83902a_poll(); + if (nrx > 0) { + for(j=0; j= tmo) { + printf("timeout during rx\n"); + return 0; + } + } + return 0; +} + +int eth_send(volatile void *packet, int length) { + int tmo; + + PRINTK("### eth_send\n"); + + pkey = -1; + + dp83902a_send((unsigned char *) packet, length, 666); + tmo = get_timer (0) + TOUT * CFG_HZ; + while(1) { + dp83902a_poll(); + if (pkey != -1) { + PRINTK("Packet sucesfully sent\n"); + return 0; + } + if (get_timer (0) >= tmo) { + printf("transmission error (timoeut)\n"); + return 0; + } + + } + return 0; +} + +#endif diff --git a/drivers/ne2000.h b/drivers/ne2000.h new file mode 100644 index 0000000..2955533 --- /dev/null +++ b/drivers/ne2000.h @@ -0,0 +1,279 @@ +/* +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + + +========================================================================== + + dev/dp83902a.h + + National Semiconductor DP83902a ethernet chip + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### + ------------------------------------------- + This file is part of eCos, the Embedded Configurable Operating System. + Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + + eCos is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 or (at your option) any later version. + + eCos is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License along + with eCos; if not, write to the Free Software Foundation, Inc., + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + As a special exception, if other files instantiate templates or use macros + or inline functions from this file, or you compile this file and link it + with other works to produce a work based on this file, this file does not + by itself cause the resulting work to be covered by the GNU General Public + License. However the source code for this file must still be made available + in accordance with section (3) of the GNU General Public License. + + This exception does not invalidate any other reasons why a work based on + this file might be covered by the GNU General Public License. + + Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. + at http://sources.redhat.com/ecos/ecos-license/ */ + ------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + + ------------------------------------------- + + Portions of this software may have been derived from OpenBSD or other sources, + and are covered by the appropriate copyright disclaimers included herein. + + ------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + + Author(s): gthomas + Contributors: gthomas, jskov + Date: 2001-06-13 + Purpose: + Description: + +####DESCRIPTIONEND#### + +========================================================================== + +*/ + +/* + ------------------------------------------------------------------------ + Macros for accessing DP registers + These can be overridden by the platform header +*/ + +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_))) +#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_) + +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_))) +#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_) + + +/* here is all the data */ + +#define cyg_uint8 unsigned char +#define cyg_uint16 unsigned short +#define bool int + +#define false 0 +#define true 1 + +#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1 +#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X) + +typedef struct dp83902a_priv_data { + cyg_uint8* base; + cyg_uint8* data; + cyg_uint8* reset; + int tx_next; /* First free Tx page */ + int tx_int; /* Expecting interrupt from this buffer */ + int rx_next; /* First free Rx page */ + int tx1, tx2; /* Page numbers for Tx buffers */ + unsigned long tx1_key, tx2_key; /* Used to ack when packet sent */ + int tx1_len, tx2_len; + bool tx_started, running, hardwired_esa; + cyg_uint8 esa[6]; + void* plf_priv; + + /* Buffer allocation */ + int tx_buf1, tx_buf2; + int rx_buf_start, rx_buf_end; +} dp83902a_priv_data_t; + +/* + ------------------------------------------------------------------------ + Some forward declarations +*/ +static void dp83902a_poll(void); + +/* ------------------------------------------------------------------------ */ +/* Register offsets */ + +#define DP_CR 0x00 +#define DP_CLDA0 0x01 +#define DP_PSTART 0x01 /* write */ +#define DP_CLDA1 0x02 +#define DP_PSTOP 0x02 /* write */ +#define DP_BNDRY 0x03 +#define DP_TSR 0x04 +#define DP_TPSR 0x04 /* write */ +#define DP_NCR 0x05 +#define DP_TBCL 0x05 /* write */ +#define DP_FIFO 0x06 +#define DP_TBCH 0x06 /* write */ +#define DP_ISR 0x07 +#define DP_CRDA0 0x08 +#define DP_RSAL 0x08 /* write */ +#define DP_CRDA1 0x09 +#define DP_RSAH 0x09 /* write */ +#define DP_RBCL 0x0a /* write */ +#define DP_RBCH 0x0b /* write */ +#define DP_RSR 0x0c +#define DP_RCR 0x0c /* write */ +#define DP_FER 0x0d +#define DP_TCR 0x0d /* write */ +#define DP_CER 0x0e +#define DP_DCR 0x0e /* write */ +#define DP_MISSED 0x0f +#define DP_IMR 0x0f /* write */ +#define DP_DATAPORT 0x10 /* "eprom" data port */ + +#define DP_P1_CR 0x00 +#define DP_P1_PAR0 0x01 +#define DP_P1_PAR1 0x02 +#define DP_P1_PAR2 0x03 +#define DP_P1_PAR3 0x04 +#define DP_P1_PAR4 0x05 +#define DP_P1_PAR5 0x06 +#define DP_P1_CURP 0x07 +#define DP_P1_MAR0 0x08 +#define DP_P1_MAR1 0x09 +#define DP_P1_MAR2 0x0a +#define DP_P1_MAR3 0x0b +#define DP_P1_MAR4 0x0c +#define DP_P1_MAR5 0x0d +#define DP_P1_MAR6 0x0e +#define DP_P1_MAR7 0x0f + +#define DP_P2_CR 0x00 +#define DP_P2_PSTART 0x01 +#define DP_P2_CLDA0 0x01 /* write */ +#define DP_P2_PSTOP 0x02 +#define DP_P2_CLDA1 0x02 /* write */ +#define DP_P2_RNPP 0x03 +#define DP_P2_TPSR 0x04 +#define DP_P2_LNPP 0x05 +#define DP_P2_ACH 0x06 +#define DP_P2_ACL 0x07 +#define DP_P2_RCR 0x0c +#define DP_P2_TCR 0x0d +#define DP_P2_DCR 0x0e +#define DP_P2_IMR 0x0f + +/* Command register - common to all pages */ + +#define DP_CR_STOP 0x01 /* Stop: software reset */ +#define DP_CR_START 0x02 /* Start: initialize device */ +#define DP_CR_TXPKT 0x04 /* Transmit packet */ +#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ +#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ +#define DP_CR_SEND 0x18 /* Send packet */ +#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ +#define DP_CR_PAGE0 0x00 /* Page select */ +#define DP_CR_PAGE1 0x40 +#define DP_CR_PAGE2 0x80 +#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ + +/* Data configuration register */ + +#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ +#define DP_DCR_BOS 0x02 /* 1=Little Endian */ +#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ +#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ +#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ +#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ +#define DP_DCR_FIFO_2 0x20 +#define DP_DCR_FIFO_4 0x40 +#define DP_DCR_FIFO_6 0x60 + +#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) + +/* Interrupt status register */ + +#define DP_ISR_RxP 0x01 /* Packet received */ +#define DP_ISR_TxP 0x02 /* Packet transmitted */ +#define DP_ISR_RxE 0x04 /* Receive error */ +#define DP_ISR_TxE 0x08 /* Transmit error */ +#define DP_ISR_OFLW 0x10 /* Receive overflow */ +#define DP_ISR_CNT 0x20 /* Tally counters need emptying */ +#define DP_ISR_RDC 0x40 /* Remote DMA complete */ +#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ + +/* Interrupt mask register */ + +#define DP_IMR_RxP 0x01 /* Packet received */ +#define DP_IMR_TxP 0x02 /* Packet transmitted */ +#define DP_IMR_RxE 0x04 /* Receive error */ +#define DP_IMR_TxE 0x08 /* Transmit error */ +#define DP_IMR_OFLW 0x10 /* Receive overflow */ +#define DP_IMR_CNT 0x20 /* Tall counters need emptying */ +#define DP_IMR_RDC 0x40 /* Remote DMA complete */ + +#define DP_IMR_All 0x3F /* Everything but remote DMA */ + +/* Receiver control register */ + +#define DP_RCR_SEP 0x01 /* Save bad(error) packets */ +#define DP_RCR_AR 0x02 /* Accept runt packets */ +#define DP_RCR_AB 0x04 /* Accept broadcast packets */ +#define DP_RCR_AM 0x08 /* Accept multicast packets */ +#define DP_RCR_PROM 0x10 /* Promiscuous mode */ +#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ + +/* Receiver status register */ + +#define DP_RSR_RxP 0x01 /* Packet received */ +#define DP_RSR_CRC 0x02 /* CRC error */ +#define DP_RSR_FRAME 0x04 /* Framing error */ +#define DP_RSR_FO 0x08 /* FIFO overrun */ +#define DP_RSR_MISS 0x10 /* Missed packet */ +#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ +#define DP_RSR_DIS 0x40 /* Receiver disabled */ +#define DP_RSR_DFR 0x80 /* Receiver processing deferred */ + +/* Transmitter control register */ + +#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ +#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ +#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ +#define DP_TCR_INLOOP 0x04 /* Full internal loopback */ +#define DP_TCR_OUTLOOP 0x08 /* External loopback */ +#define DP_TCR_ATD 0x10 /* Auto transmit disable */ +#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ + +/* Transmit status register */ + +#define DP_TSR_TxP 0x01 /* Packet transmitted */ +#define DP_TSR_COL 0x04 /* Collision (at least one) */ +#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ +#define DP_TSR_CRS 0x10 /* Lost carrier */ +#define DP_TSR_FU 0x20 /* FIFO underrun */ +#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ +#define DP_TSR_OWC 0x80 /* Collision outside normal window */ + +#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ +#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ diff --git a/drivers/netarm_eth.c b/drivers/netarm_eth.c new file mode 100644 index 0000000..89b3a83 --- /dev/null +++ b/drivers/netarm_eth.c @@ -0,0 +1,360 @@ +/* + * Copyright (C) 2004 IMMS gGmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * author(s): Thomas Elste, + * (some parts derived from uCLinux Netarm Ethernet Driver) + */ + + +#include + +#ifdef CONFIG_DRIVER_NETARMETH +#include +#include +#include "netarm_eth.h" +#include + + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +static int na_mii_poll_busy (void); + +static void na_get_mac_addr (void) +{ + unsigned short p[3]; + char *m_addr; + char ethaddr[20]; + + m_addr = (char *) p; + + p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1); + p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2); + p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3); + + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + m_addr[0], m_addr[1], + m_addr[2], m_addr[3], m_addr[4], m_addr[5]); + + printf ("HW-MAC Address: %s\n", ethaddr); + + /* set env, todo: check if already an adress is set */ + setenv ("ethaddr", ethaddr); +} + + +static void na_mii_write (int reg, int value) +{ + int mii_addr; + + /* Select register */ + mii_addr = CFG_ETH_PHY_ADDR + reg; + SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); + /* Write value */ + SET_EADDR (NETARM_ETH_MII_WRITE, value); + na_mii_poll_busy (); +} + +static unsigned int na_mii_read (int reg) +{ + int mii_addr, val; + + /* Select register */ + mii_addr = CFG_ETH_PHY_ADDR + reg; + SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); + /* do one management cycle */ + SET_EADDR (NETARM_ETH_MII_CMD, + GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT); + na_mii_poll_busy (); + /* Return read value */ + val = GET_EADDR (NETARM_ETH_MII_READ); + return val; +} + +static int na_mii_poll_busy (void) +{ + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) { + if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) { + return 1; + } + } + printf ("na_mii_busy timeout\n"); + return (0); +} + +static int na_mii_identify_phy (void) +{ + int id_reg_a = 0; + + /* get phy id register */ + id_reg_a = na_mii_read (MII_PHY_ID); + + if (id_reg_a == 0x0043) { + /* This must be an Enable or a Lucent LU3X31 PHY chip */ + return 1; + } else if (id_reg_a == 0x0013) { + /* it is an Intel LXT971A */ + return 1; + } + return (0); +} + +static int na_mii_negotiate (void) +{ + int i = 0; + + /* Enable auto-negotiation */ + na_mii_write (MII_PHY_AUTONEGADV, 0x01e1); + /* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */ + /* Restart auto-negotiation */ + na_mii_write (MII_PHY_CONTROL, 0x1200); + + /* status register is 0xffff after setting the autoneg restart bit */ + while (na_mii_read (MII_PHY_STATUS) == 0xffff) { + i++; + } + + /* na_mii_read uses the timer already, so we can't use it again for + timeout checking. + Instead we just try some times. + */ + for (i = 0; i < 40000; i++) { + if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) { + return 0; + } + } + /* + printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS)); + */ + return (1); +} + +static unsigned int na_mii_check_speed (void) +{ + unsigned int status; + + /* Read Status register */ + status = na_mii_read (MII_PHY_STATUS); + /* Check link status. If 0, default to 100 Mbps. */ + if ((status & 0x0004) == 0) { + printf ("*Warning* no link detected, set default speed to 100Mbs\n"); + return 1; + } else { + if ((na_mii_read (17) & 0x4000) != 0) { + printf ("100Mbs link detected\n"); + return 1; + } else { + printf ("10Mbs link detected\n"); + return 0; + } + } + return 0; +} + +static int reset_eth (void) +{ + int pt; + + na_get_mac_addr (); + pt = na_mii_identify_phy (); + + /* reset the phy */ + na_mii_write (MII_PHY_CONTROL, 0x8000); + reset_timer_masked (); + while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) { + if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) { + break; + } + } + if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY) + printf ("phy reset timeout\n"); + + /* set the PCS reg */ + SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M | + NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR); + + na_mii_negotiate (); + na_mii_check_speed (); + + /* Delay 10 millisecond. (Maybe this should be 1 second.) */ + udelay (10000); + + /* Turn receive on. + Enable statistics register autozero on read. + Do not insert MAC address on transmit. + Do not enable special test modes. */ + SET_EADDR (NETARM_ETH_STL_CFG, + (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN)); + + /* Set the inter-packet gap delay to 0.96us for MII. + The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG + Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG + Gap Timer Register should be set to 0x00000C12 for the MII PHY. */ + SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15); + SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12); + + /* Add CRC to end of packets. + Pad packets to minimum length of 64 bytes. + Allow unlimited length transmit packets. + Receive all broadcast packets. + NOTE: Multicast addressing is NOT enabled here currently. */ + SET_EADDR (NETARM_ETH_MAC_CFG, + (NETARM_ETH_MACC_CRCEN | + NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN)); + SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD); + + /* enable fifos */ + SET_EADDR (NETARM_ETH_GEN_CTRL, + (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX)); + + return (0); +} + + +extern int eth_init (bd_t * bd) +{ + reset_eth (); + return 0; +} + +extern void eth_halt (void) +{ + SET_EADDR (NETARM_ETH_GEN_CTRL, 0); +} + +/* Get a data block via Ethernet */ +extern int eth_rx (void) +{ + int i; + unsigned short rxlen; + unsigned int *addr; + unsigned int rxstatus, lastrxlen; + char *pa; + + /* RXBR is 1, data block was received */ + if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0) + return 0; + + /* get status register and the length of received block */ + rxstatus = GET_EADDR (NETARM_ETH_RX_STAT); + rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16; + + if (rxlen == 0) + return 0; + + /* clear RXBR to make fifo available */ + SET_EADDR (NETARM_ETH_GEN_STAT, + GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR); + + /* clear TXBC to make fifo available */ + /* According to NETARM50 data manual you just have to clear + RXBR but that has no effect. Only after clearing TXBC the + Fifo becomes readable. */ + SET_EADDR (NETARM_ETH_GEN_STAT, + GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC); + + addr = (unsigned int *) NetRxPackets[0]; + pa = (char *) NetRxPackets[0]; + + /* read the fifo */ + for (i = 0; i < rxlen / 4; i++) { + *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); + addr++; + } + + if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) { + /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */ + lastrxlen = + (GET_EADDR (NETARM_ETH_GEN_STAT) & + NETARM_ETH_GST_RXFDB) >> 28; + *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); + switch (lastrxlen) { + case 1: + *addr &= 0xff000000; + break; + case 2: + *addr &= 0xffff0000; + break; + case 3: + *addr &= 0xffffff00; + break; + } + } + + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], rxlen); + + return rxlen; +} + +/* Send a data block via Ethernet. */ +extern int eth_send (volatile void *packet, int length) +{ + int i, length32; + char *pa; + unsigned int *pa32, lastp = 0, rest; + + pa = (char *) packet; + pa32 = (unsigned int *) packet; + length32 = length / 4; + rest = length % 4; + + /* make sure there's no garbage in the last word */ + switch (rest) { + case 0: + lastp = pa32[length32]; + length32--; + break; + case 1: + lastp = pa32[length32] & 0x000000ff; + break; + case 2: + lastp = pa32[length32] & 0x0000ffff; + break; + case 3: + lastp = pa32[length32] & 0x00ffffff; + break; + } + + /* write to the fifo */ + for (i = 0; i < length32; i++) + SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]); + + /* the last word is written to an extra register, this + starts the transmission */ + SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp); + + /* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission + went fine. But we can't use the timer for a timeout loop because + of it is used already in upper layers. So we just try some times. */ + i = 0; + while (i < 50000) { + if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK) + == NETARM_ETH_TXSTAT_TXOK) + return 0; + i++; + } + + printf ("eth_send timeout\n"); + return 1; +} + +#endif /* COMMANDS & CFG_NET */ + +#endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/drivers/netarm_eth.h b/drivers/netarm_eth.h new file mode 100644 index 0000000..8edab82 --- /dev/null +++ b/drivers/netarm_eth.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2003 IMMS gGmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * author(s): Thomas Elste, + */ + +#include +#include + +#ifdef CONFIG_DRIVER_NETARMETH + +#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val +#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE)) + +#define NA_MII_POLL_BUSY_DELAY 900 + +/* MII negotiation timeout value + 500 jiffies = 5 seconds */ +#define NA_MII_NEGOTIATE_DELAY 30 + +/* Registers in the physical layer chip */ +#define MII_PHY_CONTROL 0 +#define MII_PHY_STATUS 1 +#define MII_PHY_ID 2 +#define MII_PHY_AUTONEGADV 4 + +#endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/drivers/netconsole.c b/drivers/netconsole.c new file mode 100644 index 0000000..9a0a24f --- /dev/null +++ b/drivers/netconsole.c @@ -0,0 +1,267 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_NETCONSOLE + +#include +#include +#include + +static char input_buffer[512]; +static int input_size = 0; /* char count in input buffer */ +static int input_offset = 0; /* offset to valid chars in input buffer */ +static int input_recursion = 0; +static int output_recursion = 0; +static int net_timeout; +static uchar nc_ether[6]; /* server enet address */ +static IPaddr_t nc_ip; /* server ip */ +static short nc_port; /* source/target port */ +static const char *output_packet; /* used by first send udp */ +static int output_packet_len = 0; + +static void nc_wait_arp_handler (uchar * pkt, unsigned dest, unsigned src, + unsigned len) +{ + NetState = NETLOOP_SUCCESS; /* got arp reply - quit net loop */ +} + +static void nc_handler (uchar * pkt, unsigned dest, unsigned src, + unsigned len) +{ + if (input_size) + NetState = NETLOOP_SUCCESS; /* got input - quit net loop */ +} + +static void nc_timeout (void) +{ + NetState = NETLOOP_SUCCESS; +} + +void NcStart (void) +{ + if (!output_packet_len || memcmp (nc_ether, NetEtherNullAddr, 6)) { + /* going to check for input packet */ + NetSetHandler (nc_handler); + NetSetTimeout (net_timeout, nc_timeout); + } else { + /* send arp request */ + uchar *pkt; + NetSetHandler (nc_wait_arp_handler); + pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE; + memcpy (pkt, output_packet, output_packet_len); + NetSendUDPPacket (nc_ether, nc_ip, nc_port, nc_port, output_packet_len); + } +} + +int nc_input_packet (uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + int end, chunk; + + if (dest != nc_port || !len) + return 0; /* not for us */ + + if (input_size == sizeof input_buffer) + return 1; /* no space */ + if (len > sizeof input_buffer - input_size) + len = sizeof input_buffer - input_size; + + end = input_offset + input_size; + if (end > sizeof input_buffer) + end -= sizeof input_buffer; + + chunk = len; + if (end + len > sizeof input_buffer) { + chunk = sizeof input_buffer - end; + memcpy(input_buffer, pkt + chunk, len - chunk); + } + memcpy (input_buffer + end, pkt, chunk); + + input_size += len; + + return 1; +} + +static void nc_send_packet (const char *buf, int len) +{ + DECLARE_GLOBAL_DATA_PTR; + + struct eth_device *eth; + int inited = 0; + uchar *pkt; + uchar *ether; + IPaddr_t ip; + + if ((eth = eth_get_dev ()) == NULL) { + return; + } + + if (!memcmp (nc_ether, NetEtherNullAddr, 6)) { + if (eth->state == ETH_STATE_ACTIVE) + return; /* inside net loop */ + output_packet = buf; + output_packet_len = len; + NetLoop (NETCONS); /* wait for arp reply and send packet */ + output_packet_len = 0; + return; + } + + if (eth->state != ETH_STATE_ACTIVE) { + if (eth_init (gd->bd) < 0) + return; + inited = 1; + } + pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE; + memcpy (pkt, buf, len); + ether = nc_ether; + ip = nc_ip; + NetSendUDPPacket (ether, ip, nc_port, nc_port, len); + + if (inited) + eth_halt (); +} + +int nc_start (void) +{ + int netmask, our_ip; + + nc_port = 6666; /* default port */ + + if (getenv ("ncip")) { + char *p; + + nc_ip = getenv_IPaddr ("ncip"); + if (!nc_ip) + return -1; /* ncip is 0.0.0.0 */ + if ((p = strchr (getenv ("ncip"), ':')) != NULL) + nc_port = simple_strtoul (p + 1, NULL, 10); + } else + nc_ip = ~0; /* ncip is not set */ + + our_ip = getenv_IPaddr ("ipaddr"); + netmask = getenv_IPaddr ("netmask"); + + if (nc_ip == ~0 || /* 255.255.255.255 */ + ((netmask & our_ip) == (netmask & nc_ip) && /* on the same net */ + (netmask | nc_ip) == ~0)) /* broadcast to our net */ + memset (nc_ether, 0xff, sizeof nc_ether); + else + memset (nc_ether, 0, sizeof nc_ether); /* force arp request */ + + return 0; +} + +void nc_putc (char c) +{ + if (output_recursion) + return; + output_recursion = 1; + + nc_send_packet (&c, 1); + + output_recursion = 0; +} + +void nc_puts (const char *s) +{ + int len; + + if (output_recursion) + return; + output_recursion = 1; + + if ((len = strlen (s)) > 512) + len = 512; + + nc_send_packet (s, len); + + output_recursion = 0; +} + +int nc_getc (void) +{ + uchar c; + + input_recursion = 1; + + net_timeout = 0; /* no timeout */ + while (!input_size) + NetLoop (NETCONS); + + input_recursion = 0; + + c = input_buffer[input_offset++]; + + if (input_offset >= sizeof input_buffer) + input_offset -= sizeof input_buffer; + input_size--; + + return c; +} + +int nc_tstc (void) +{ + struct eth_device *eth; + + if (input_recursion) + return 0; + + if (input_size) + return 1; + + eth = eth_get_dev (); + if (eth && eth->state == ETH_STATE_ACTIVE) + return 0; /* inside net loop */ + + input_recursion = 1; + + net_timeout = 1; + NetLoop (NETCONS); /* kind of poll */ + + input_recursion = 0; + + return input_size != 0; +} + +int drv_nc_init (void) +{ + device_t dev; + int rc; + + memset (&dev, 0, sizeof (dev)); + + strcpy (dev.name, "nc"); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.start = nc_start; + dev.putc = nc_putc; + dev.puts = nc_puts; + dev.getc = nc_getc; + dev.tstc = nc_tstc; + + rc = device_register (&dev); + + return (rc == 0) ? 1 : rc; +} + +#endif /* CONFIG_NETCONSOLE */ diff --git a/drivers/nicext.h b/drivers/nicext.h new file mode 100644 index 0000000..4074972 --- /dev/null +++ b/drivers/nicext.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + * + * Name: nicext.h + * + * Description: Broadcom Network Interface Card Extension (NICE) is an + * extension to Linux NET device kernel mode drivers. + * NICE is designed to provide additional functionalities, + * such as receive packet intercept. To support Broadcom NICE, + * the network device driver can be modified by adding an + * device ioctl handler and by indicating receiving packets + * to the NICE receive handler. Broadcom NICE will only be + * enabled by a NICE-aware intermediate driver, such as + * Broadcom Advanced Server Program Driver (BASP). When NICE + * is not enabled, the modified network device drivers + * functions exactly as other non-NICE aware drivers. + * + * Author: Frankie Fan + * + * Created: September 17, 2000 + * + ****************************************************************************/ +#ifndef _nicext_h_ +#define _nicext_h_ + +/* + * ioctl for NICE + */ +#define SIOCNICE SIOCDEVPRIVATE+7 + +/* + * SIOCNICE: + * + * The following structure needs to be less than IFNAMSIZ (16 bytes) because + * we're overloading ifreq.ifr_ifru. + * + * If 16 bytes is not enough, we should consider relaxing this because + * this is no field after ifr_ifru in the ifreq structure. But we may + * run into future compatiability problem in case of changing struct ifreq. + */ +struct nice_req +{ + __u32 cmd; + + union + { +#ifdef __KERNEL__ + /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */ + struct + { + void (*nrqus1_rx)( struct sk_buff*, void* ); + void* nrqus1_ctx; + } nrqu_nrqus1; + + /* cmd = NICE_CMD_QUERY_SUPPORT */ + struct + { + __u32 nrqus2_magic; + __u32 nrqus2_support_rx:1; + __u32 nrqus2_support_vlan:1; + __u32 nrqus2_support_get_speed:1; + } nrqu_nrqus2; +#endif + + /* cmd = NICE_CMD_GET_SPEED */ + struct + { + unsigned int nrqus3_speed; /* 0 if link is down, */ + /* otherwise speed in Mbps */ + } nrqu_nrqus3; + + /* cmd = NICE_CMD_BLINK_LED */ + struct + { + unsigned int nrqus4_blink_time; /* blink duration in seconds */ + } nrqu_nrqus4; + + } nrq_nrqu; +}; + +#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx +#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx +#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx +#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic +#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan +#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed +#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed +#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time + +/* + * magic constants + */ +#define NICE_REQUESTOR_MAGIC 0x4543494E /* NICE in ascii */ +#define NICE_DEVICE_MAGIC 0x4E494345 /* ECIN in ascii */ + +/* + * command field + */ +#define NICE_CMD_QUERY_SUPPORT 0x00000001 +#define NICE_CMD_SET_RX 0x00000002 +#define NICE_CMD_GET_RX 0x00000003 +#define NICE_CMD_GET_SPEED 0x00000004 +#define NICE_CMD_BLINK_LED 0x00000005 + +#endif /* _nicext_h_ */ diff --git a/drivers/ns16550.c b/drivers/ns16550.c new file mode 100644 index 0000000..2429464 --- /dev/null +++ b/drivers/ns16550.c @@ -0,0 +1,71 @@ +/* + * COM1 NS16550 support + * originally from linux source (arch/ppc/boot/ns16550.c) + * modified to use CFG_ISA_MEM and new defines + */ + +#include + +#ifdef CFG_NS16550 + +#include + +#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ +#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ +#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ + +void NS16550_init (NS16550_t com_port, int baud_divisor) +{ + com_port->ier = 0x00; +#ifdef CONFIG_OMAP + com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ +#endif + com_port->lcr = LCR_BKSE | LCRVAL; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; +#if defined(CONFIG_OMAP) +#if defined(CONFIG_APTIX) + com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */ +#else + com_port->mdr1 = 0; /* /16 is proper to hit 115200 with 48MHz */ +#endif +#endif +} + +void NS16550_reinit (NS16550_t com_port, int baud_divisor) +{ + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; +} + +void NS16550_putc (NS16550_t com_port, char c) +{ + while ((com_port->lsr & LSR_THRE) == 0); + com_port->thr = c; +} + +char NS16550_getc (NS16550_t com_port) +{ + while ((com_port->lsr & LSR_DR) == 0) { +#ifdef CONFIG_USB_TTY + extern void usbtty_poll(void); + usbtty_poll(); +#endif + } + return (com_port->rbr); +} + +int NS16550_tstc (NS16550_t com_port) +{ + return ((com_port->lsr & LSR_DR) != 0); +} + +#endif diff --git a/drivers/ns7520_eth.c b/drivers/ns7520_eth.c new file mode 100644 index 0000000..a5a20df --- /dev/null +++ b/drivers/ns7520_eth.c @@ -0,0 +1,859 @@ +/*********************************************************************** + * + * Copyright (C) 2005 by Videon Central, Inc. + * + * $Id$ + * @Author: Arthur Shipkowski + * @Descr: Ethernet driver for the NS7520. Uses polled Ethernet, like + * the older netarmeth driver. Note that attempting to filter + * broadcast and multicast out in the SAFR register will cause + * bad things due to released errata. + * @References: [1] NS7520 Hardware Reference, December 2003 + * [2] Intel LXT971 Datasheet #249414 Rev. 02 + * + ***********************************************************************/ + +#include + +#if defined(CONFIG_DRIVER_NS7520_ETHERNET) + +#include /* NetSendPacket */ +#include +#include + +#include "ns7520_eth.h" /* for Ethernet and PHY */ + +/** + * Send an error message to the terminal. + */ +#define ERROR(x) \ +do { \ + char *__foo = strrchr(__FILE__, '/'); \ + \ + printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \ + __LINE__, __FUNCTION__); \ + printf x; printf("\n"); \ +} while (0); + +/* some definition to make transistion to linux easier */ + +#define NS7520_DRIVER_NAME "eth" +#define KERN_WARNING "Warning:" +#define KERN_ERR "Error:" +#define KERN_INFO "Info:" + +#if 1 +# define DEBUG +#endif + +#ifdef DEBUG +# define printk printf + +# define DEBUG_INIT 0x0001 +# define DEBUG_MINOR 0x0002 +# define DEBUG_RX 0x0004 +# define DEBUG_TX 0x0008 +# define DEBUG_INT 0x0010 +# define DEBUG_POLL 0x0020 +# define DEBUG_LINK 0x0040 +# define DEBUG_MII 0x0100 +# define DEBUG_MII_LOW 0x0200 +# define DEBUG_MEM 0x0400 +# define DEBUG_ERROR 0x4000 +# define DEBUG_ERROR_CRIT 0x8000 + +static int nDebugLvl = DEBUG_ERROR_CRIT; + +# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \ + printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \ + printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\ + printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\ + printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0) +# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \ + printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0); +# define ASSERT( expr, func ) if( !( expr ) ) { \ + printf( "Assertion failed! %s:line %d %s\n", \ + (int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \ + func } +#else /* DEBUG */ +# define printk(...) +# define DEBUG_ARGS0( FLG, a0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) +# define DEBUG_FN( n ) +# define ASSERT(expr, func) +#endif /* DEBUG */ + +#define NS7520_MII_NEG_DELAY (5*CFG_HZ) /* in s */ +#define TX_TIMEOUT (5*CFG_HZ) /* in s */ +#define RX_STALL_WORKAROUND_CNT 100 + +static int ns7520_eth_reset(void); + +static void ns7520_link_auto_negotiate(void); +static void ns7520_link_update_egcr(void); +static void ns7520_link_print_changed(void); + +/* the PHY stuff */ + +static char ns7520_mii_identify_phy(void); +static unsigned short ns7520_mii_read(unsigned short uiRegister); +static void ns7520_mii_write(unsigned short uiRegister, + unsigned short uiData); +static unsigned int ns7520_mii_get_clock_divisor(unsigned int + unMaxMDIOClk); +static unsigned int ns7520_mii_poll_busy(void); + +static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; +static unsigned int uiLastLinkStatus; +static PhyType phyDetected = PHY_NONE; + +/*********************************************************************** + * @Function: eth_init + * @Return: -1 on failure otherwise 0 + * @Descr: Initializes the ethernet engine and uses either FS Forth's default + * MAC addr or the one in environment + ***********************************************************************/ + +int eth_init(bd_t * pbis) +{ + unsigned char aucMACAddr[6]; + char *pcTmp = getenv("ethaddr"); + char *pcEnd; + int i; + + DEBUG_FN(DEBUG_INIT); + + /* no need to check for hardware */ + + if (!ns7520_eth_reset()) + return -1; + + if (NULL == pcTmp) + return -1; + + for (i = 0; i < 6; i++) { + aucMACAddr[i] = + pcTmp ? simple_strtoul(pcTmp, &pcEnd, 16) : 0; + pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd; + } + + /* configure ethernet address */ + + *get_eth_reg_addr(NS7520_ETH_SA1) = + aucMACAddr[5] << 8 | aucMACAddr[4]; + *get_eth_reg_addr(NS7520_ETH_SA2) = + aucMACAddr[3] << 8 | aucMACAddr[2]; + *get_eth_reg_addr(NS7520_ETH_SA3) = + aucMACAddr[1] << 8 | aucMACAddr[0]; + + /* enable hardware */ + + *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN; + *get_eth_reg_addr(NS7520_ETH_SUPP) = NS7520_ETH_SUPP_JABBER; + *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN; + + /* the linux kernel may give packets < 60 bytes, for example arp */ + *get_eth_reg_addr(NS7520_ETH_MAC2) = NS7520_ETH_MAC2_CRCEN | + NS7520_ETH_MAC2_PADEN | NS7520_ETH_MAC2_HUGE; + + /* Broadcast/multicast allowed; if you don't set this even unicast chokes */ + /* Based on NS7520 errata documentation */ + *get_eth_reg_addr(NS7520_ETH_SAFR) = + NS7520_ETH_SAFR_BROAD | NS7520_ETH_SAFR_PRM; + + /* enable receive and transmit FIFO, use 10/100 Mbps MII */ + *get_eth_reg_addr(NS7520_ETH_EGCR) |= + NS7520_ETH_EGCR_ETXWM_75 | + NS7520_ETH_EGCR_ERX | + NS7520_ETH_EGCR_ERXREG | + NS7520_ETH_EGCR_ERXBR | NS7520_ETH_EGCR_ETX; + + return 0; +} + +/*********************************************************************** + * @Function: eth_send + * @Return: -1 on timeout otherwise 1 + * @Descr: sends one frame by DMA + ***********************************************************************/ + +int eth_send(volatile void *pPacket, int nLen) +{ + int i, length32, retval = 1; + char *pa; + unsigned int *pa32, lastp = 0, rest; + unsigned int status; + + pa = (char *) pPacket; + pa32 = (unsigned int *) pPacket; + length32 = nLen / 4; + rest = nLen % 4; + + /* make sure there's no garbage in the last word */ + switch (rest) { + case 0: + lastp = pa32[length32 - 1]; + length32--; + break; + case 1: + lastp = pa32[length32] & 0x000000ff; + break; + case 2: + lastp = pa32[length32] & 0x0000ffff; + break; + case 3: + lastp = pa32[length32] & 0x00ffffff; + break; + } + + while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_TXREGE) + == 0) { + } + + /* write to the fifo */ + for (i = 0; i < length32; i++) + *get_eth_reg_addr(NS7520_ETH_FIFO) = pa32[i]; + + /* the last word is written to an extra register, this + starts the transmission */ + *get_eth_reg_addr(NS7520_ETH_FIFOL) = lastp; + + /* Wait for it to be done */ + while ((*get_eth_reg_addr(NS7520_ETH_EGSR) & NS7520_ETH_EGSR_TXBC) + == 0) { + } + status = (*get_eth_reg_addr(NS7520_ETH_ETSR)); + *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_TXBC; /* Clear it now */ + + if (status & NS7520_ETH_ETSR_TXOK) { + retval = 0; /* We're OK! */ + } else if (status & NS7520_ETH_ETSR_TXDEF) { + printf("Deferred, we'll see.\n"); + retval = 0; + } else if (status & NS7520_ETH_ETSR_TXAL) { + printf("Late collision error, %d collisions.\n", + (*get_eth_reg_addr(NS7520_ETH_ETSR)) & + NS7520_ETH_ETSR_TXCOLC); + } else if (status & NS7520_ETH_ETSR_TXAEC) { + printf("Excessive collisions: %d\n", + (*get_eth_reg_addr(NS7520_ETH_ETSR)) & + NS7520_ETH_ETSR_TXCOLC); + } else if (status & NS7520_ETH_ETSR_TXAED) { + printf("Excessive deferral on xmit.\n"); + } else if (status & NS7520_ETH_ETSR_TXAUR) { + printf("Packet underrun.\n"); + } else if (status & NS7520_ETH_ETSR_TXAJ) { + printf("Jumbo packet error.\n"); + } else { + printf("Error: Should never get here.\n"); + } + + return (retval); +} + +/*********************************************************************** + * @Function: eth_rx + * @Return: size of last frame in bytes or 0 if no frame available + * @Descr: gives one frame to U-Boot which has been copied by DMA engine already + * to NetRxPackets[ 0 ]. + ***********************************************************************/ + +int eth_rx(void) +{ + int i; + unsigned short rxlen; + unsigned short totrxlen = 0; + unsigned int *addr; + unsigned int rxstatus, lastrxlen; + char *pa; + + /* If RXBR is 1, data block was received */ + while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_RXBR) == NS7520_ETH_EGSR_RXBR) { + + /* get status register and the length of received block */ + rxstatus = *get_eth_reg_addr(NS7520_ETH_ERSR); + rxlen = (rxstatus & NS7520_ETH_ERSR_RXSIZE) >> 16; + + /* clear RXBR to make fifo available */ + *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_RXBR; + + if (rxstatus & NS7520_ETH_ERSR_ROVER) { + printf("Receive overrun, resetting FIFO.\n"); + *get_eth_reg_addr(NS7520_ETH_EGCR) &= + ~NS7520_ETH_EGCR_ERX; + udelay(20); + *get_eth_reg_addr(NS7520_ETH_EGCR) |= + NS7520_ETH_EGCR_ERX; + } + if (rxlen == 0) { + printf("Nothing.\n"); + return 0; + } + + addr = (unsigned int *) NetRxPackets[0]; + pa = (char *) NetRxPackets[0]; + + /* read the fifo */ + for (i = 0; i < rxlen / 4; i++) { + *addr = *get_eth_reg_addr(NS7520_ETH_FIFO); + addr++; + } + + if ((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_RXREGR) { + /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */ + lastrxlen = + ((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_RXFDB_MA) >> 28; + *addr = *get_eth_reg_addr(NS7520_ETH_FIFO); + switch (lastrxlen) { + case 1: + *addr &= 0xff000000; + break; + case 2: + *addr &= 0xffff0000; + break; + case 3: + *addr &= 0xffffff00; + break; + } + } + + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[0], rxlen - 4); + totrxlen += rxlen - 4; + } + + return totrxlen; +} + +/*********************************************************************** + * @Function: eth_halt + * @Return: n/a + * @Descr: stops the ethernet engine + ***********************************************************************/ + +void eth_halt(void) +{ + DEBUG_FN(DEBUG_INIT); + + *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_RXEN; + *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~(NS7520_ETH_EGCR_ERX | + NS7520_ETH_EGCR_ERXDMA | + NS7520_ETH_EGCR_ERXREG | + NS7520_ETH_EGCR_ERXBR | + NS7520_ETH_EGCR_ETX | + NS7520_ETH_EGCR_ETXDMA); +} + +/*********************************************************************** + * @Function: ns7520_eth_reset + * @Return: 0 on failure otherwise 1 + * @Descr: resets the ethernet interface and the PHY, + * performs auto negotiation or fixed modes + ***********************************************************************/ + +static int ns7520_eth_reset(void) +{ + DEBUG_FN(DEBUG_MINOR); + + /* Reset important registers */ + *get_eth_reg_addr(NS7520_ETH_EGCR) = 0; /* Null it out! */ + *get_eth_reg_addr(NS7520_ETH_MAC1) &= NS7520_ETH_MAC1_SRST; + *get_eth_reg_addr(NS7520_ETH_MAC2) = 0; + /* Reset MAC */ + *get_eth_reg_addr(NS7520_ETH_EGCR) |= NS7520_ETH_EGCR_MAC_RES; + udelay(5); + *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~NS7520_ETH_EGCR_MAC_RES; + + /* reset and initialize PHY */ + + *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_SRST; + + /* we don't support hot plugging of PHY, therefore we don't reset + phyDetected and nPhyMaxMdioClock here. The risk is if the setting is + incorrect the first open + may detect the PHY correctly but succeding will fail + For reseting the PHY and identifying we have to use the standard + MDIO CLOCK value 2.5 MHz only after hardware reset + After having identified the PHY we will do faster */ + + *get_eth_reg_addr(NS7520_ETH_MCFG) = + ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); + + /* reset PHY */ + ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET); + ns7520_mii_write(PHY_COMMON_CTRL, 0); + + udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */ + + /* MII clock has been setup to default, ns7520_mii_identify_phy should + work for all */ + + if (!ns7520_mii_identify_phy()) { + printk(KERN_ERR NS7520_DRIVER_NAME + ": Unsupported PHY, aborting\n"); + return 0; + } + + /* now take the highest MDIO clock possible after detection */ + *get_eth_reg_addr(NS7520_ETH_MCFG) = + ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); + + /* PHY has been detected, so there can be no abort reason and we can + finish initializing ethernet */ + + uiLastLinkStatus = 0xff; /* undefined */ + + ns7520_link_auto_negotiate(); + + if (phyDetected == PHY_LXT971A) + /* set LED2 to link mode */ + ns7520_mii_write(PHY_LXT971_LED_CFG, + (PHY_LXT971_LED_CFG_LINK_ACT << + PHY_LXT971_LED_CFG_SHIFT_LED2) | + (PHY_LXT971_LED_CFG_TRANSMIT << + PHY_LXT971_LED_CFG_SHIFT_LED1)); + + return 1; +} + +/*********************************************************************** + * @Function: ns7520_link_auto_negotiate + * @Return: void + * @Descr: performs auto-negotation of link. + ***********************************************************************/ + +static void ns7520_link_auto_negotiate(void) +{ + unsigned long ulStartJiffies; + unsigned short uiStatus; + + DEBUG_FN(DEBUG_LINK); + + /* run auto-negotation */ + /* define what we are capable of */ + ns7520_mii_write(PHY_COMMON_AUTO_ADV, + PHY_COMMON_AUTO_ADV_100BTXFD | + PHY_COMMON_AUTO_ADV_100BTX | + PHY_COMMON_AUTO_ADV_10BTFD | + PHY_COMMON_AUTO_ADV_10BT | + PHY_COMMON_AUTO_ADV_802_3); + /* start auto-negotiation */ + ns7520_mii_write(PHY_COMMON_CTRL, + PHY_COMMON_CTRL_AUTO_NEG | + PHY_COMMON_CTRL_RES_AUTO); + + /* wait for completion */ + + ulStartJiffies = get_timer(0); + while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) { + uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + if ((uiStatus & + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) + == + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) { + /* lucky we are, auto-negotiation succeeded */ + ns7520_link_print_changed(); + ns7520_link_update_egcr(); + return; + } + } + + DEBUG_ARGS0(DEBUG_LINK, "auto-negotiation timed out\n"); + /* ignore invalid link settings */ +} + +/*********************************************************************** + * @Function: ns7520_link_update_egcr + * @Return: void + * @Descr: updates the EGCR and MAC2 link status after mode change or + * auto-negotation + ***********************************************************************/ + +static void ns7520_link_update_egcr(void) +{ + unsigned int unEGCR; + unsigned int unMAC2; + unsigned int unIPGT; + + DEBUG_FN(DEBUG_LINK); + + unEGCR = *get_eth_reg_addr(NS7520_ETH_EGCR); + unMAC2 = *get_eth_reg_addr(NS7520_ETH_MAC2); + unIPGT = + *get_eth_reg_addr(NS7520_ETH_IPGT) & ~NS7520_ETH_IPGT_IPGT; + + unEGCR &= ~NS7520_ETH_EGCR_EFULLD; + unMAC2 &= ~NS7520_ETH_MAC2_FULLD; + if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE) + == PHY_LXT971_STAT2_DUPLEX_MODE) { + unEGCR |= NS7520_ETH_EGCR_EFULLD; + unMAC2 |= NS7520_ETH_MAC2_FULLD; + unIPGT |= 0x15; /* see [1] p. 167 */ + } else + unIPGT |= 0x12; /* see [1] p. 167 */ + + *get_eth_reg_addr(NS7520_ETH_MAC2) = unMAC2; + *get_eth_reg_addr(NS7520_ETH_EGCR) = unEGCR; + *get_eth_reg_addr(NS7520_ETH_IPGT) = unIPGT; +} + +/*********************************************************************** + * @Function: ns7520_link_print_changed + * @Return: void + * @Descr: checks whether the link status has changed and if so prints + * the new mode + ***********************************************************************/ + +static void ns7520_link_print_changed(void) +{ + unsigned short uiStatus; + unsigned short uiControl; + + DEBUG_FN(DEBUG_LINK); + + uiControl = ns7520_mii_read(PHY_COMMON_CTRL); + + if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) == + PHY_COMMON_CTRL_AUTO_NEG) { + /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */ + uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + + if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) { + printk(KERN_WARNING NS7520_DRIVER_NAME + ": link down\n"); + /* @TODO Linux: carrier_off */ + } else { + /* @TODO Linux: carrier_on */ + if (phyDetected == PHY_LXT971A) { + uiStatus = + ns7520_mii_read(PHY_LXT971_STAT2); + uiStatus &= + (PHY_LXT971_STAT2_100BTX | + PHY_LXT971_STAT2_DUPLEX_MODE | + PHY_LXT971_STAT2_AUTO_NEG); + + /* mask out all uninteresting parts */ + } + /* other PHYs must store there link information in + uiStatus as PHY_LXT971 */ + } + } else { + /* mode has been forced, so uiStatus should be the same as the + last link status, enforce printing */ + uiStatus = uiLastLinkStatus; + uiLastLinkStatus = 0xff; + } + + if (uiStatus != uiLastLinkStatus) { + /* save current link status */ + uiLastLinkStatus = uiStatus; + + /* print new link status */ + + printk(KERN_INFO NS7520_DRIVER_NAME + ": link mode %i Mbps %s duplex %s\n", + (uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10, + (uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" : + "half", + (uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" : + ""); + } +} + +/*********************************************************************** + * the MII low level stuff + ***********************************************************************/ + +/*********************************************************************** + * @Function: ns7520_mii_identify_phy + * @Return: 1 if supported PHY has been detected otherwise 0 + * @Descr: checks for supported PHY and prints the IDs. + ***********************************************************************/ + +static char ns7520_mii_identify_phy(void) +{ + unsigned short uiID1; + unsigned short uiID2; + unsigned char *szName; + char cRes = 0; + + DEBUG_FN(DEBUG_MII); + + phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1); + + switch (phyDetected) { + case PHY_LXT971A: + szName = "LXT971A"; + uiID2 = ns7520_mii_read(PHY_COMMON_ID2); + nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; + cRes = 1; + break; + case PHY_NONE: + default: + /* in case uiID1 == 0 && uiID2 == 0 we may have the wrong + address or reset sets the wrong NS7520_ETH_MCFG_CLKS */ + + uiID2 = 0; + szName = "unknown"; + nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; + phyDetected = PHY_NONE; + } + + printk(KERN_INFO NS7520_DRIVER_NAME + ": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName); + + return cRes; +} + +/*********************************************************************** + * @Function: ns7520_mii_read + * @Return: the data read from PHY register uiRegister + * @Descr: the data read may be invalid if timed out. If so, a message + * is printed but the invalid data is returned. + * The fixed device address is being used. + ***********************************************************************/ + +static unsigned short ns7520_mii_read(unsigned short uiRegister) +{ + DEBUG_FN(DEBUG_MII_LOW); + + /* write MII register to be read */ + *get_eth_reg_addr(NS7520_ETH_MADR) = + CONFIG_PHY_ADDR << 8 | uiRegister; + + *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ; + + if (!ns7520_mii_poll_busy()) + printk(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in read\n"); + /* continue to read */ + + *get_eth_reg_addr(NS7520_ETH_MCMD) = 0; + + return (unsigned short) (*get_eth_reg_addr(NS7520_ETH_MRDD)); +} + +/*********************************************************************** + * @Function: ns7520_mii_write + * @Return: nothing + * @Descr: writes the data to the PHY register. In case of a timeout, + * no special handling is performed but a message printed + * The fixed device address is being used. + ***********************************************************************/ + +static void ns7520_mii_write(unsigned short uiRegister, + unsigned short uiData) +{ + DEBUG_FN(DEBUG_MII_LOW); + + /* write MII register to be written */ + *get_eth_reg_addr(NS7520_ETH_MADR) = + CONFIG_PHY_ADDR << 8 | uiRegister; + + *get_eth_reg_addr(NS7520_ETH_MWTD) = uiData; + + if (!ns7520_mii_poll_busy()) { + printf(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in write\n"); + } +} + +/*********************************************************************** + * @Function: ns7520_mii_get_clock_divisor + * @Return: the clock divisor that should be used in NS7520_ETH_MCFG_CLKS + * @Descr: if no clock divisor can be calculated for the + * current SYSCLK and the maximum MDIO Clock, a warning is printed + * and the greatest divisor is taken + ***********************************************************************/ + +static unsigned int ns7520_mii_get_clock_divisor(unsigned int unMaxMDIOClk) +{ + struct { + unsigned int unSysClkDivisor; + unsigned int unClks; /* field for NS7520_ETH_MCFG_CLKS */ + } PHYClockDivisors[] = { + { + 4, NS7520_ETH_MCFG_CLKS_4}, { + 6, NS7520_ETH_MCFG_CLKS_6}, { + 8, NS7520_ETH_MCFG_CLKS_8}, { + 10, NS7520_ETH_MCFG_CLKS_10}, { + 14, NS7520_ETH_MCFG_CLKS_14}, { + 20, NS7520_ETH_MCFG_CLKS_20}, { + 28, NS7520_ETH_MCFG_CLKS_28} + }; + + int nIndexSysClkDiv; + int nArraySize = + sizeof(PHYClockDivisors) / sizeof(PHYClockDivisors[0]); + unsigned int unClks = NS7520_ETH_MCFG_CLKS_28; /* defaults to + greatest div */ + + DEBUG_FN(DEBUG_INIT); + + for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize; + nIndexSysClkDiv++) { + /* find first sysclock divisor that isn't higher than 2.5 MHz + clock */ + if (NETARM_XTAL_FREQ / + PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <= + unMaxMDIOClk) { + unClks = PHYClockDivisors[nIndexSysClkDiv].unClks; + break; + } + } + + DEBUG_ARGS2(DEBUG_INIT, + "Taking MDIO Clock bit mask 0x%0x for max clock %i\n", + unClks, unMaxMDIOClk); + + /* return greatest divisor */ + return unClks; +} + +/*********************************************************************** + * @Function: ns7520_mii_poll_busy + * @Return: 0 if timed out otherwise the remaing timeout + * @Descr: waits until the MII has completed a command or it times out + * code may be interrupted by hard interrupts. + * It is not checked what happens on multiple actions when + * the first is still being busy and we timeout. + ***********************************************************************/ + +static unsigned int ns7520_mii_poll_busy(void) +{ + unsigned int unTimeout = 1000; + + DEBUG_FN(DEBUG_MII_LOW); + + while (((*get_eth_reg_addr(NS7520_ETH_MIND) & NS7520_ETH_MIND_BUSY) + == NS7520_ETH_MIND_BUSY) && unTimeout) + unTimeout--; + + return unTimeout; +} + +/* ---------------------------------------------------------------------------- + * Net+ARM ethernet MII functionality. + */ +#if defined(CONFIG_MII) + +/** + * Maximum MII address we support + */ +#define MII_ADDRESS_MAX (31) + +/** + * Maximum MII register address we support + */ +#define MII_REGISTER_MAX (31) + +/** + * Ethernet MII interface return values for public functions. + */ +enum mii_status { + MII_STATUS_SUCCESS = 0, + MII_STATUS_FAILURE = 1, +}; + +/** + * Read a 16-bit value from an MII register. + */ +extern int ns7520_miiphy_read(char *devname, unsigned char const addr, + unsigned char const reg, unsigned short *const value) +{ + int ret = MII_STATUS_FAILURE; + + /* Parameter checks */ + if (addr > MII_ADDRESS_MAX) { + ERROR(("invalid addr, 0x%02X", addr)); + goto miiphy_read_failed_0; + } + + if (reg > MII_REGISTER_MAX) { + ERROR(("invalid reg, 0x%02X", reg)); + goto miiphy_read_failed_0; + } + + if (value == NULL) { + ERROR(("NULL value")); + goto miiphy_read_failed_0; + } + + DEBUG_FN(DEBUG_MII_LOW); + + /* write MII register to be read */ + *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg; + + *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ; + + if (!ns7520_mii_poll_busy()) + printk(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in read\n"); + /* continue to read */ + + *get_eth_reg_addr(NS7520_ETH_MCMD) = 0; + + *value = (*get_eth_reg_addr(NS7520_ETH_MRDD)); + ret = MII_STATUS_SUCCESS; + /* Fall through */ + + miiphy_read_failed_0: + return (ret); +} + +/** + * Write a 16-bit value to an MII register. + */ +extern int ns7520_miiphy_write(char *devname, unsigned char const addr, + unsigned char const reg, unsigned short const value) +{ + int ret = MII_STATUS_FAILURE; + + /* Parameter checks */ + if (addr > MII_ADDRESS_MAX) { + ERROR(("invalid addr, 0x%02X", addr)); + goto miiphy_write_failed_0; + } + + if (reg > MII_REGISTER_MAX) { + ERROR(("invalid reg, 0x%02X", reg)); + goto miiphy_write_failed_0; + } + + /* write MII register to be written */ + *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg; + + *get_eth_reg_addr(NS7520_ETH_MWTD) = value; + + if (!ns7520_mii_poll_busy()) { + printf(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in write\n"); + } + + ret = MII_STATUS_SUCCESS; + /* Fall through */ + + miiphy_write_failed_0: + return (ret); +} +#endif /* defined(CONFIG_MII) */ +#endif /* CONFIG_DRIVER_NS7520_ETHERNET */ + +int ns7520_miiphy_initialize(bd_t *bis) +{ +#if defined(CONFIG_DRIVER_NS7520_ETHERNET) +#if defined(CONFIG_MII) + miiphy_register("ns7520phy", ns7520_miiphy_read, ns7520_miiphy_write); +#endif +#endif + return 0; +} diff --git a/drivers/ns8382x.c b/drivers/ns8382x.c new file mode 100644 index 0000000..976f86a --- /dev/null +++ b/drivers/ns8382x.c @@ -0,0 +1,863 @@ +/* + ns8382x.c: A U-Boot driver for the NatSemi DP8382[01]. + ported by: Mark A. Rakes (mark_rakes@vivato.net) + + Adapted from: + 1. an Etherboot driver for DP8381[56] written by: + Copyright (C) 2001 Entity Cyber, Inc. + + This development of this Etherboot driver was funded by + Sicom Systems: http://www.sicompos.com/ + + Author: Marty Connor (mdc@thinguin.org) + Adapted from a Linux driver which was written by Donald Becker + + This software may be used and distributed according to the terms + of the GNU Public License (GPL), incorporated herein by reference. + + 2. A Linux driver by Donald Becker, ns820.c: + Written/copyright 1999-2002 by Donald Becker. + + This software may be used and distributed according to the terms of + the GNU General Public License (GPL), incorporated herein by reference. + Drivers based on or derived from this code fall under the GPL and must + retain the authorship, copyright and license notice. This file is not + a complete program and may only be used when the entire operating + system is licensed under the GPL. License for under other terms may be + available. Contact the original author for details. + + The original author may be reached as becker@scyld.com, or at + Scyld Computing Corporation + 410 Severn Ave., Suite 210 + Annapolis MD 21403 + + Support information and updates available at + http://www.scyld.com/network/netsemi.html + + Datasheets available from: + http://www.national.com/pf/DP/DP83820.html + http://www.national.com/pf/DP/DP83821.html +*/ + +/* Revision History + * October 2002 mar 1.0 + * Initial U-Boot Release. + * Tested with Netgear GA622T (83820) + * and SMC9452TX (83821) + * NOTE: custom boards with these chips may (likely) require + * a programmed EEPROM device (if present) in order to work + * correctly. +*/ + +/* Includes */ +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_NS8382X) + +/* defines */ +#define DSIZE 0x00000FFF +#define ETH_ALEN 6 +#define CRC_SIZE 4 +#define TOUT_LOOP 500000 +#define TX_BUF_SIZE 1536 +#define RX_BUF_SIZE 1536 +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ + +enum register_offsets { + ChipCmd = 0x00, + ChipConfig = 0x04, + EECtrl = 0x08, + IntrMask = 0x14, + IntrEnable = 0x18, + TxRingPtr = 0x20, + TxRingPtrHi = 0x24, + TxConfig = 0x28, + RxRingPtr = 0x30, + RxRingPtrHi = 0x34, + RxConfig = 0x38, + PriQueue = 0x3C, + RxFilterAddr = 0x48, + RxFilterData = 0x4C, + ClkRun = 0xCC, + PCIPM = 0x44, +}; + +enum ChipCmdBits { + ChipReset = 0x100, + RxReset = 0x20, + TxReset = 0x10, + RxOff = 0x08, + RxOn = 0x04, + TxOff = 0x02, + TxOn = 0x01 +}; + +enum ChipConfigBits { + LinkSts = 0x80000000, + GigSpeed = 0x40000000, + HundSpeed = 0x20000000, + FullDuplex = 0x10000000, + TBIEn = 0x01000000, + Mode1000 = 0x00400000, + T64En = 0x00004000, + D64En = 0x00001000, + M64En = 0x00000800, + PhyRst = 0x00000400, + PhyDis = 0x00000200, + ExtStEn = 0x00000100, + BEMode = 0x00000001, +}; +#define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex) + +enum TxConfig_bits { + TxDrthMask = 0x000000ff, + TxFlthMask = 0x0000ff00, + TxMxdmaMask = 0x00700000, + TxMxdma_8 = 0x00100000, + TxMxdma_16 = 0x00200000, + TxMxdma_32 = 0x00300000, + TxMxdma_64 = 0x00400000, + TxMxdma_128 = 0x00500000, + TxMxdma_256 = 0x00600000, + TxMxdma_512 = 0x00700000, + TxMxdma_1024 = 0x00000000, + TxCollRetry = 0x00800000, + TxAutoPad = 0x10000000, + TxMacLoop = 0x20000000, + TxHeartIgn = 0x40000000, + TxCarrierIgn = 0x80000000 +}; + +enum RxConfig_bits { + RxDrthMask = 0x0000003e, + RxMxdmaMask = 0x00700000, + RxMxdma_8 = 0x00100000, + RxMxdma_16 = 0x00200000, + RxMxdma_32 = 0x00300000, + RxMxdma_64 = 0x00400000, + RxMxdma_128 = 0x00500000, + RxMxdma_256 = 0x00600000, + RxMxdma_512 = 0x00700000, + RxMxdma_1024 = 0x00000000, + RxAcceptLenErr = 0x04000000, + RxAcceptLong = 0x08000000, + RxAcceptTx = 0x10000000, + RxStripCRC = 0x20000000, + RxAcceptRunt = 0x40000000, + RxAcceptErr = 0x80000000, +}; + +/* Bits in the RxMode register. */ +enum rx_mode_bits { + RxFilterEnable = 0x80000000, + AcceptAllBroadcast = 0x40000000, + AcceptAllMulticast = 0x20000000, + AcceptAllUnicast = 0x10000000, + AcceptPerfectMatch = 0x08000000, +}; + +typedef struct _BufferDesc { + u32 link; + u32 bufptr; + vu_long cmdsts; + u32 extsts; /*not used here */ +} BufferDesc; + +/* Bits in network_desc.status */ +enum desc_status_bits { + DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000, + DescNoCRC = 0x10000000, DescPktOK = 0x08000000, + DescSizeMask = 0xfff, + + DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000, + DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000, + DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000, + DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000, + + DescRxAbort = 0x04000000, DescRxOver = 0x02000000, + DescRxDest = 0x01800000, DescRxLong = 0x00400000, + DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000, + DescRxCRC = 0x00080000, DescRxAlign = 0x00040000, + DescRxLoop = 0x00020000, DesRxColl = 0x00010000, +}; + +/* Bits in MEAR */ +enum mii_reg_bits { + MDIO_ShiftClk = 0x0040, + MDIO_EnbOutput = 0x0020, + MDIO_Data = 0x0010, +}; + +/* PHY Register offsets. */ +enum phy_reg_offsets { + BMCR = 0x00, + BMSR = 0x01, + PHYIDR1 = 0x02, + PHYIDR2 = 0x03, + ANAR = 0x04, + KTCR = 0x09, +}; + +/* basic mode control register bits */ +enum bmcr_bits { + Bmcr_Reset = 0x8000, + Bmcr_Loop = 0x4000, + Bmcr_Speed0 = 0x2000, + Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */ + Bmcr_RstAutoNeg = 0x0200, + Bmcr_Duplex = 0x0100, + Bmcr_Speed1 = 0x0040, + Bmcr_Force10H = 0x0000, + Bmcr_Force10F = 0x0100, + Bmcr_Force100H = 0x2000, + Bmcr_Force100F = 0x2100, + Bmcr_Force1000H = 0x0040, + Bmcr_Force1000F = 0x0140, +}; + +/* auto negotiation advertisement register */ +enum anar_bits { + anar_adv_100F = 0x0100, + anar_adv_100H = 0x0080, + anar_adv_10F = 0x0040, + anar_adv_10H = 0x0020, + anar_ieee_8023 = 0x0001, +}; + +/* 1K-base T control register */ +enum ktcr_bits { + ktcr_adv_1000H = 0x0100, + ktcr_adv_1000F = 0x0200, +}; + +/* Globals */ +static u32 SavedClkRun; +static unsigned int cur_rx; +static unsigned int rx_config; +static unsigned int tx_config; + +/* Note: transmit and receive buffers and descriptors must be + long long word aligned */ +static BufferDesc txd __attribute__ ((aligned(8))); +static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8))); +static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8))); +static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE] + __attribute__ ((aligned(8))); + +/* Function Prototypes */ +static int mdio_read(struct eth_device *dev, int phy_id, int addr); +static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value); +static void mdio_sync(struct eth_device *dev, u32 offset); +static int ns8382x_init(struct eth_device *dev, bd_t * bis); +static void ns8382x_reset(struct eth_device *dev); +static void ns8382x_init_rxfilter(struct eth_device *dev); +static void ns8382x_init_txd(struct eth_device *dev); +static void ns8382x_init_rxd(struct eth_device *dev); +static void ns8382x_set_rx_mode(struct eth_device *dev); +static void ns8382x_check_duplex(struct eth_device *dev); +static int ns8382x_send(struct eth_device *dev, volatile void *packet, + int length); +static int ns8382x_poll(struct eth_device *dev); +static void ns8382x_disable(struct eth_device *dev); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820}, + {} +}; + +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +static inline int +INW(struct eth_device *dev, u_long addr) +{ + return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); +} + +static int +INL(struct eth_device *dev, u_long addr) +{ + return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); +} + +static inline void +OUTW(struct eth_device *dev, int command, u_long addr) +{ + *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); +} + +static inline void +OUTL(struct eth_device *dev, int command, u_long addr) +{ + *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); +} + +/* Function: ns8382x_initialize + * Description: Retrieves the MAC address of the card, and sets up some + * globals required by other routines, and initializes the NIC, making it + * ready to send and receive packets. + * Side effects: initializes ns8382xs, ready to recieve packets. + * Returns: int: number of cards found + */ + +int +ns8382x_initialize(bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase, status; + int i, idx = 0; + u32 phyAddress; + u32 tmp; + u32 chip_config; + + while (1) { /* Find PCI device(s) */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */ + +#ifdef NS8382X_DEBUG + printf("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase); +#endif + + pci_write_config_dword(devno, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled. */ + pci_read_config_dword(devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEM access.\n"); + continue; + } else if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + dev = (struct eth_device *) malloc(sizeof *dev); + + sprintf(dev->name, "dp8382x#%d", card_number); + dev->iobase = bus_to_phys(iobase); + dev->priv = (void *) devno; + dev->init = ns8382x_init; + dev->halt = ns8382x_disable; + dev->send = ns8382x_send; + dev->recv = ns8382x_poll; + + /* ns8382x has a non-standard PM control register + * in PCI config space. Some boards apparently need + * to be brought to D0 in this manner. */ + pci_read_config_dword(devno, PCIPM, &tmp); + if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */ + u32 newtmp = tmp & ~(0x03 | 0x100); + pci_write_config_dword(devno, PCIPM, newtmp); + } + + /* get MAC address */ + for (i = 0; i < 3; i++) { + u32 data; + char *mac = (char *)&dev->enetaddr[i * 2]; + + OUTL(dev, i * 2, RxFilterAddr); + data = INL(dev, RxFilterData); + *mac++ = data; + *mac++ = data >> 8; + } + /* get PHY address, can't be zero */ + for (phyAddress = 1; phyAddress < 32; phyAddress++) { + u32 rev, phy1; + + phy1 = mdio_read(dev, phyAddress, PHYIDR1); + if (phy1 == 0x2000) { /*check for 83861/91 */ + rev = mdio_read(dev, phyAddress, PHYIDR2); + if ((rev & ~(0x000f)) == 0x00005c50 || + (rev & ~(0x000f)) == 0x00005c60) { +#ifdef NS8382X_DEBUG + printf("phy rev is %x\n", rev); + printf("phy address is %x\n", + phyAddress); +#endif + break; + } + } + } + + /* set phy to autonegotiate && advertise everything */ + mdio_write(dev, phyAddress, KTCR, + (ktcr_adv_1000H | ktcr_adv_1000F)); + mdio_write(dev, phyAddress, ANAR, + (anar_adv_100F | anar_adv_100H | anar_adv_10H | + anar_adv_10F | anar_ieee_8023)); + mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */ + mdio_write(dev, phyAddress, BMCR, + (Bmcr_AutoNegEn | Bmcr_RstAutoNeg)); + /* Reset the chip to erase any previous misconfiguration. */ + OUTL(dev, (ChipReset), ChipCmd); + + chip_config = INL(dev, ChipConfig); + /* reset the phy */ + OUTL(dev, (chip_config | PhyRst), ChipConfig); + /* power up and initialize transceiver */ + OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig); + + mdio_sync(dev, EECtrl); +#ifdef NS8382X_DEBUG + { + u32 chpcfg = + INL(dev, ChipConfig) ^ SpeedStatus_Polarity; + + printf("%s: Transceiver 10%s %s duplex.\n", dev->name, + (chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed) + ? "0" : "", + chpcfg & FullDuplex ? "full" : "half"); + printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, + dev->enetaddr[0], dev->enetaddr[1], + dev->enetaddr[2], dev->enetaddr[3], + dev->enetaddr[4], dev->enetaddr[5]); + } +#endif + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + SavedClkRun = INL(dev, ClkRun); + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + + eth_register(dev); + + card_number++; + + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60); + + udelay(10 * 1000); + } + return card_number; +} + +/* MII transceiver control section. + Read and write MII registers using software-generated serial MDIO + protocol. See the MII specifications or DP83840A data sheet for details. + + The maximum data clock rate is 2.5 Mhz. To meet minimum timing we + must flush writes to the PCI bus with a PCI read. */ +#define mdio_delay(mdio_addr) INL(dev, mdio_addr) + +#define MDIO_EnbIn (0) +#define MDIO_WRITE0 (MDIO_EnbOutput) +#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) + +/* Generate the preamble required for initial synchronization and + a few older transceivers. */ +static void +mdio_sync(struct eth_device *dev, u32 offset) +{ + int bits = 32; + + /* Establish sync by sending at least 32 logic ones. */ + while (--bits >= 0) { + OUTL(dev, MDIO_WRITE1, offset); + mdio_delay(offset); + OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset); + mdio_delay(offset); + } +} + +static int +mdio_read(struct eth_device *dev, int phy_id, int addr) +{ + int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr; + int i, retval = 0; + + /* Shift the read command bits out. */ + for (i = 15; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + + OUTL(dev, dataval, EECtrl); + mdio_delay(EECtrl); + OUTL(dev, dataval | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + /* Read the two transition, 16 data, and wire-idle bits. */ + for (i = 19; i > 0; i--) { + OUTL(dev, MDIO_EnbIn, EECtrl); + mdio_delay(EECtrl); + retval = + (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0); + OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + return (retval >> 1) & 0xffff; +} + +static void +mdio_write(struct eth_device *dev, int phy_id, int addr, int value) +{ + int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value; + int i; + + /* Shift the command bits out. */ + for (i = 31; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + + OUTL(dev, dataval, EECtrl); + mdio_delay(EECtrl); + OUTL(dev, dataval | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + /* Clear out extra bits. */ + for (i = 2; i > 0; i--) { + OUTL(dev, MDIO_EnbIn, EECtrl); + mdio_delay(EECtrl); + OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + return; +} + +/* Function: ns8382x_init + * Description: resets the ethernet controller chip and configures + * registers and data structures required for sending and receiving packets. + * Arguments: struct eth_device *dev: NIC data structure + * returns: int. + */ + +static int +ns8382x_init(struct eth_device *dev, bd_t * bis) +{ + u32 config; + + ns8382x_reset(dev); + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + + ns8382x_init_rxfilter(dev); + ns8382x_init_txd(dev); + ns8382x_init_rxd(dev); + + /*set up ChipConfig */ + config = INL(dev, ChipConfig); + /*turn off 64 bit ops && Ten-bit interface + * && big-endian mode && extended status */ + config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn); + OUTL(dev, config, ChipConfig); + + /* Configure the PCI bus bursts and FIFO thresholds. */ + tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad + | TxCollRetry | TxMxdma_1024 | (0x1002); + rx_config = RxMxdma_1024 | 0x20; +#ifdef NS8382X_DEBUG + printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config); + printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config); +#endif + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); + + /*turn off priority queueing */ + OUTL(dev, 0x0, PriQueue); + + ns8382x_check_duplex(dev); + ns8382x_set_rx_mode(dev); + + OUTL(dev, (RxOn | TxOn), ChipCmd); + return 1; +} + +/* Function: ns8382x_reset + * Description: soft resets the controller chip + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ +static void +ns8382x_reset(struct eth_device *dev) +{ + OUTL(dev, ChipReset, ChipCmd); + while (INL(dev, ChipCmd)) + /*wait until done */ ; + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); +} + +/* Function: ns8382x_init_rxfilter + * Description: sets receive filter address to our MAC address + * Arguments: struct eth_device *dev: NIC data structure + * returns: void. + */ + +static void +ns8382x_init_rxfilter(struct eth_device *dev) +{ + int i; + + for (i = 0; i < ETH_ALEN; i += 2) { + OUTL(dev, i, RxFilterAddr); + OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8), + RxFilterData); + } +} + +/* Function: ns8382x_init_txd + * Description: initializes the Tx descriptor + * Arguments: struct eth_device *dev: NIC data structure + * returns: void. + */ + +static void +ns8382x_init_txd(struct eth_device *dev) +{ + txd.link = (u32) 0; + txd.bufptr = cpu_to_le32((u32) & txb[0]); + txd.cmdsts = (u32) 0; + txd.extsts = (u32) 0; + + OUTL(dev, 0x0, TxRingPtrHi); + OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr); +#ifdef NS8382X_DEBUG + printf("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n", + INL(dev, TxRingPtr), &txd); +#endif +} + +/* Function: ns8382x_init_rxd + * Description: initializes the Rx descriptor ring + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ + +static void +ns8382x_init_rxd(struct eth_device *dev) +{ + int i; + + OUTL(dev, 0x0, RxRingPtrHi); + + cur_rx = 0; + for (i = 0; i < NUM_RX_DESC; i++) { + rxd[i].link = + cpu_to_le32((i + 1 < + NUM_RX_DESC) ? (u32) & rxd[i + + 1] : (u32) & + rxd[0]); + rxd[i].extsts = cpu_to_le32((u32) 0x0); + rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE); + rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]); +#ifdef NS8382X_DEBUG + printf + ("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n", + i, &rxd[i], le32_to_cpu(rxd[i].link), + le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr)); +#endif + } + OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr); + +#ifdef NS8382X_DEBUG + printf("ns8382x_init_rxd: RX descriptor register loaded with: %X\n", + INL(dev, RxRingPtr)); +#endif +} + +/* Function: ns8382x_set_rx_mode + * Description: + * sets the receive mode to accept all broadcast packets and packets + * with our MAC address, and reject all multicast packets. + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ + +static void +ns8382x_set_rx_mode(struct eth_device *dev) +{ + u32 rx_mode = 0x0; + /*spec says RxFilterEnable has to be 0 for rest of + * this stuff to be properly configured. Linux driver + * seems to support this*/ +/* OUTL(dev, rx_mode, RxFilterAddr);*/ + rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch); + OUTL(dev, rx_mode, RxFilterAddr); + printf("ns8382x_set_rx_mode: set to %X\n", rx_mode); + /*now we turn RxFilterEnable back on */ + /*rx_mode |= RxFilterEnable; + OUTL(dev, rx_mode, RxFilterAddr);*/ +} + +static void +ns8382x_check_duplex(struct eth_device *dev) +{ + int gig = 0; + int hun = 0; + int duplex = 0; + int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity); + + duplex = (config & FullDuplex) ? 1 : 0; + gig = (config & GigSpeed) ? 1 : 0; + hun = (config & HundSpeed) ? 1 : 0; +#ifdef NS8382X_DEBUG + printf("%s: Setting 10%s %s-duplex based on negotiated link" + " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "", + duplex ? "full" : "half"); +#endif + if (duplex) { + rx_config |= RxAcceptTx; + tx_config |= (TxCarrierIgn | TxHeartIgn); + } else { + rx_config &= ~RxAcceptTx; + tx_config &= ~(TxCarrierIgn | TxHeartIgn); + } +#ifdef NS8382X_DEBUG + printf("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config); + printf("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config); +#endif + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); + + /*if speed is 10 or 100, remove MODE1000, + * if it's 1000, then set it */ + config = INL(dev, ChipConfig); + if (gig) + config |= Mode1000; + else + config &= ~Mode1000; + +#ifdef NS8382X_DEBUG + printf("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns"); +#endif + OUTL(dev, config, ChipConfig); +} + +/* Function: ns8382x_send + * Description: transmits a packet and waits for completion or timeout. + * Returns: void. */ +static int +ns8382x_send(struct eth_device *dev, volatile void *packet, int length) +{ + u32 i, status = 0; + vu_long tx_stat = 0; + + /* Stop the transmitter */ + OUTL(dev, TxOff, ChipCmd); +#ifdef NS8382X_DEBUG + printf("ns8382x_send: sending %d bytes\n", (int)length); +#endif + + /* set the transmit buffer descriptor and enable Transmit State Machine */ + txd.link = cpu_to_le32(0x0); + txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet)); + txd.extsts = cpu_to_le32(0x0); + txd.cmdsts = cpu_to_le32(DescOwn | length); + + /* load Transmit Descriptor Register */ + OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr); +#ifdef NS8382X_DEBUG + printf("ns8382x_send: TX descriptor register loaded with: %#08X\n", + INL(dev, TxRingPtr)); + printf("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n", + le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr), + le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts)); +#endif + /* restart the transmitter */ + OUTL(dev, TxOn, ChipCmd); + + for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) { + if (i >= TOUT_LOOP) { + printf ("%s: tx error buffer not ready: txd.cmdsts %#X\n", + dev->name, tx_stat); + goto Done; + } + } + + if (!(tx_stat & DescPktOK)) { + printf("ns8382x_send: Transmit error, Tx status %X.\n", tx_stat); + goto Done; + } +#ifdef NS8382X_DEBUG + printf("ns8382x_send: tx_stat: %#08X\n", tx_stat); +#endif + + status = 1; + Done: + return status; +} + +/* Function: ns8382x_poll + * Description: checks for a received packet and returns it if found. + * Arguments: struct eth_device *dev: NIC data structure + * Returns: 1 if packet was received. + * 0 if no packet was received. + * Side effects: + * Returns (copies) the packet to the array dev->packet. + * Returns the length of the packet. + */ + +static int +ns8382x_poll(struct eth_device *dev) +{ + int retstat = 0; + int length = 0; + vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts); + + if (!(rx_status & (u32) DescOwn)) + return retstat; +#ifdef NS8382X_DEBUG + printf("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n", + cur_rx, rx_status); +#endif + length = (rx_status & DSIZE) - CRC_SIZE; + + if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) { + /* corrupted packet received */ + printf("ns8382x_poll: Corrupted packet, status:%lx\n", rx_status); + retstat = 0; + } else { + /* give packet to higher level routine */ + NetReceive((rxb + cur_rx * RX_BUF_SIZE), length); + retstat = 1; + } + + /* return the descriptor and buffer to receive ring */ + rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE); + rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]); + + if (++cur_rx == NUM_RX_DESC) + cur_rx = 0; + + /* re-enable the potentially idle receive state machine */ + OUTL(dev, RxOn, ChipCmd); + + return retstat; +} + +/* Function: ns8382x_disable + * Description: Turns off interrupts and stops Tx and Rx engines + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ + +static void +ns8382x_disable(struct eth_device *dev) +{ + /* Disable interrupts using the mask. */ + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); + + /* Stop the chip's Tx and Rx processes. */ + OUTL(dev, (RxOff | TxOff), ChipCmd); + + /* Restore PME enable bit */ + OUTL(dev, SavedClkRun, ClkRun); +} + +#endif diff --git a/drivers/ns87308.c b/drivers/ns87308.c new file mode 100644 index 0000000..cf4d359 --- /dev/null +++ b/drivers/ns87308.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_NS87308 + +#include + +void initialise_ns87308 (void) +{ +#ifdef CFG_NS87308_PS2MOD + unsigned char data; + + /* + * Switch floppy drive to PS/2 mode. + */ + read_pnp_config(SUPOERIO_CONF1, &data); + data &= 0xFB; + write_pnp_config(SUPOERIO_CONF1, data); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_KBC1) + PNP_SET_DEVICE_BASE(LDEV_KBC1, CFG_NS87308_KBC1_BASE); + write_pnp_config(LUN_CONFIG_REG, 0); + write_pnp_config(CBASE_HIGH, 0x00); + write_pnp_config(CBASE_LOW, 0x64); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_MOUSE) + PNP_ACTIVATE_DEVICE(LDEV_MOUSE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_RTC_APC) + PNP_SET_DEVICE_BASE(LDEV_RTC_APC, CFG_NS87308_RTC_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_FDC) + PNP_SET_DEVICE_BASE(LDEV_FDC, CFG_NS87308_FDC_BASE); + write_pnp_config(LUN_CONFIG_REG, 0x40); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_RARP) + PNP_SET_DEVICE_BASE(LDEV_PARP, CFG_NS87308_LPT_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_UART1) + PNP_SET_DEVICE_BASE(LDEV_UART1, CFG_NS87308_UART1_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_UART2) + PNP_SET_DEVICE_BASE(LDEV_UART2, CFG_NS87308_UART2_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_GPIO) + PNP_SET_DEVICE_BASE(LDEV_GPIO, CFG_NS87308_GPIO_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_POWRMAN) +#ifndef CFG_NS87308_PWMAN_BASE + PNP_ACTIVATE_DEVICE(LDEV_POWRMAN); +#else + PNP_SET_DEVICE_BASE(LDEV_POWRMAN, CFG_NS87308_PWMAN_BASE); + + /* + * Enable all units + */ + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_FER1, 0x7d); + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_FER2, 0x87); + +#ifdef CFG_NS87308_PMC1 + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC1, CFG_NS87308_PMC1); +#endif + +#ifdef CFG_NS87308_PMC2 + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC2, CFG_NS87308_PMC2); +#endif + +#ifdef CFG_NS87308_PMC3 + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC3, CFG_NS87308_PMC3); +#endif +#endif +#endif + +#ifdef CFG_NS87308_CS0_BASE + PNP_PGCS_CSLINE_BASE(0, CFG_NS87308_CS0_BASE); + PNP_PGCS_CSLINE_CONF(0, CFG_NS87308_CS0_CONF); +#endif + +#ifdef CFG_NS87308_CS1_BASE + PNP_PGCS_CSLINE_BASE(1, CFG_NS87308_CS1_BASE); + PNP_PGCS_CSLINE_CONF(1, CFG_NS87308_CS1_CONF); +#endif + +#ifdef CFG_NS87308_CS2_BASE + PNP_PGCS_CSLINE_BASE(2, CFG_NS87308_CS2_BASE); + PNP_PGCS_CSLINE_CONF(2, CFG_NS87308_CS2_CONF); +#endif +} + +#endif diff --git a/drivers/ns9750_eth.c b/drivers/ns9750_eth.c new file mode 100644 index 0000000..067ff8e --- /dev/null +++ b/drivers/ns9750_eth.c @@ -0,0 +1,797 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_eth.c,v 1.2 2004/02/24 14:09:39 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Ethernet driver for the NS9750. Uses DMA Engine with polling + * interrupt status. But interrupts are not enabled. + * Only one tx buffer descriptor and the RXA buffer descriptor are used + * Currently no transmit lockup handling is included. eth_send has a 5s + * timeout for sending frames. No retransmits are performed when an + * error occurs. + * @References: [1] NS9750 Hardware Reference, December 2003 + * [2] Intel LXT971 Datasheet #249414 Rev. 02 + * [3] NS7520 Linux Ethernet Driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#include +#include /* NetSendPacket */ + +#include "ns9750_eth.h" /* for Ethernet and PHY */ + +#ifdef CONFIG_DRIVER_NS9750_ETHERNET + +/* some definition to make transistion to linux easier */ + +#define NS9750_DRIVER_NAME "eth" +#define KERN_WARNING "Warning:" +#define KERN_ERR "Error:" +#define KERN_INFO "Info:" + +#if 0 +# define DEBUG +#endif + +#ifdef DEBUG +# define printk printf + +# define DEBUG_INIT 0x0001 +# define DEBUG_MINOR 0x0002 +# define DEBUG_RX 0x0004 +# define DEBUG_TX 0x0008 +# define DEBUG_INT 0x0010 +# define DEBUG_POLL 0x0020 +# define DEBUG_LINK 0x0040 +# define DEBUG_MII 0x0100 +# define DEBUG_MII_LOW 0x0200 +# define DEBUG_MEM 0x0400 +# define DEBUG_ERROR 0x4000 +# define DEBUG_ERROR_CRIT 0x8000 + +static int nDebugLvl = DEBUG_ERROR_CRIT; + +# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \ + printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \ + printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\ + printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\ + printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0) +# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \ + printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0); +# define ASSERT( expr, func ) if( !( expr ) ) { \ + printf( "Assertion failed! %s:line %d %s\n", \ + (int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \ + func } +#else /* DEBUG */ +# define printk(...) +# define DEBUG_ARGS0( FLG, a0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) +# define DEBUG_FN( n ) +# define ASSERT(expr, func) +#endif /* DEBUG */ + +#define NS9750_MII_NEG_DELAY (5*CFG_HZ) /* in s */ +#define TX_TIMEOUT (5*CFG_HZ) /* in s */ + +/* @TODO move it to eeprom.h */ +#define FS_EEPROM_AUTONEG_MASK 0x7 +#define FS_EEPROM_AUTONEG_SPEED_MASK 0x1 +#define FS_EEPROM_AUTONEG_SPEED_10 0x0 +#define FS_EEPROM_AUTONEG_SPEED_100 0x1 +#define FS_EEPROM_AUTONEG_DUPLEX_MASK 0x2 +#define FS_EEPROM_AUTONEG_DUPLEX_HALF 0x0 +#define FS_EEPROM_AUTONEG_DUPLEX_FULL 0x2 +#define FS_EEPROM_AUTONEG_ENABLE_MASK 0x4 +#define FS_EEPROM_AUTONEG_DISABLE 0x0 +#define FS_EEPROM_AUTONEG_ENABLE 0x4 + +/* buffer descriptors taken from [1] p.306 */ +typedef struct +{ + unsigned int* punSrc; + unsigned int unLen; /* 11 bits */ + unsigned int* punDest; /* unused */ + union { + unsigned int unReg; + struct { + unsigned uStatus : 16; + unsigned uRes : 12; + unsigned uFull : 1; + unsigned uEnable : 1; + unsigned uInt : 1; + unsigned uWrap : 1; + } bits; + } s; +} rx_buffer_desc_t; + +typedef struct +{ + unsigned int* punSrc; + unsigned int unLen; /* 10 bits */ + unsigned int* punDest; /* unused */ + union { + unsigned int unReg; /* only 32bit accesses may done to NS9750 + * eth engine */ + struct { + unsigned uStatus : 16; + unsigned uRes : 12; + unsigned uFull : 1; + unsigned uLast : 1; + unsigned uInt : 1; + unsigned uWrap : 1; + } bits; + } s; +} tx_buffer_desc_t; + +static int ns9750_eth_reset( void ); + +static void ns9750_link_force( void ); +static void ns9750_link_auto_negotiate( void ); +static void ns9750_link_update_egcr( void ); +static void ns9750_link_print_changed( void ); + +/* the PHY stuff */ + +static char ns9750_mii_identify_phy( void ); +static unsigned short ns9750_mii_read( unsigned short uiRegister ); +static void ns9750_mii_write( unsigned short uiRegister, unsigned short uiData ); +static unsigned int ns9750_mii_get_clock_divisor( unsigned int unMaxMDIOClk ); +static unsigned int ns9750_mii_poll_busy( void ); + +static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; +static unsigned char ucLinkMode = FS_EEPROM_AUTONEG_ENABLE; +static unsigned int uiLastLinkStatus; +static PhyType phyDetected = PHY_NONE; + +/* we use only one tx buffer descriptor */ +static tx_buffer_desc_t* pTxBufferDesc = + (tx_buffer_desc_t*) get_eth_reg_addr( NS9750_ETH_TXBD ); + +/* we use only one rx buffer descriptor of the 4 */ +static rx_buffer_desc_t aRxBufferDesc[ 4 ]; + +/*********************************************************************** + * @Function: eth_init + * @Return: -1 on failure otherwise 0 + * @Descr: Initializes the ethernet engine and uses either FS Forth's default + * MAC addr or the one in environment + ***********************************************************************/ + +int eth_init (bd_t * pbis) +{ + /* This default MAC Addr is reserved by FS Forth-Systeme for the case of + EEPROM failures */ + unsigned char aucMACAddr[6] = { 0x00, 0x04, 0xf3, 0x00, 0x06, 0x35 }; + char *pcTmp = getenv ("ethaddr"); + char *pcEnd; + int i; + + DEBUG_FN (DEBUG_INIT); + + /* no need to check for hardware */ + + if (!ns9750_eth_reset ()) + return -1; + + if (pcTmp != NULL) + for (i = 0; i < 6; i++) { + aucMACAddr[i] = + pcTmp ? simple_strtoul (pcTmp, &pcEnd, + 16) : 0; + pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd; + } + + /* configure ethernet address */ + + *get_eth_reg_addr (NS9750_ETH_SA1) = + aucMACAddr[5] << 8 | aucMACAddr[4]; + *get_eth_reg_addr (NS9750_ETH_SA2) = + aucMACAddr[3] << 8 | aucMACAddr[2]; + *get_eth_reg_addr (NS9750_ETH_SA3) = + aucMACAddr[1] << 8 | aucMACAddr[0]; + + /* enable hardware */ + + *get_eth_reg_addr (NS9750_ETH_MAC1) = NS9750_ETH_MAC1_RXEN; + + /* the linux kernel may give packets < 60 bytes, for example arp */ + *get_eth_reg_addr (NS9750_ETH_MAC2) = NS9750_ETH_MAC2_CRCEN | + NS9750_ETH_MAC2_PADEN | NS9750_ETH_MAC2_HUGE; + + /* enable receive and transmit FIFO, use 10/100 Mbps MII */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) = + NS9750_ETH_EGCR1_ETXWM | + NS9750_ETH_EGCR1_ERX | + NS9750_ETH_EGCR1_ERXDMA | + NS9750_ETH_EGCR1_ETX | + NS9750_ETH_EGCR1_ETXDMA | NS9750_ETH_EGCR1_ITXA; + + /* prepare DMA descriptors */ + for (i = 0; i < 4; i++) { + aRxBufferDesc[i].punSrc = 0; + aRxBufferDesc[i].unLen = 0; + aRxBufferDesc[i].s.bits.uWrap = 1; + aRxBufferDesc[i].s.bits.uInt = 1; + aRxBufferDesc[i].s.bits.uEnable = 0; + aRxBufferDesc[i].s.bits.uFull = 0; + } + + /* NetRxPackets[ 0 ] is initialized before eth_init is called and never + changes. NetRxPackets is 32bit aligned */ + aRxBufferDesc[0].punSrc = (unsigned int *) NetRxPackets[0]; + aRxBufferDesc[0].s.bits.uEnable = 1; + aRxBufferDesc[0].unLen = 1522; /* as stated in [1] p.307 */ + + *get_eth_reg_addr (NS9750_ETH_RXAPTR) = + (unsigned int) &aRxBufferDesc[0]; + + /* [1] Tab. 221 states less than 5us */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_ERXINIT; + while (! + (*get_eth_reg_addr (NS9750_ETH_EGSR) & NS9750_ETH_EGSR_RXINIT)) + /* wait for finish */ + udelay (1); + + /* @TODO do we need to clear RXINIT? */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_ERXINIT; + + *get_eth_reg_addr (NS9750_ETH_RXFREE) = 0x1; + + return 0; +} + +/*********************************************************************** + * @Function: eth_send + * @Return: -1 on timeout otherwise 1 + * @Descr: sends one frame by DMA + ***********************************************************************/ + +int eth_send (volatile void *pPacket, int nLen) +{ + ulong ulTimeout; + + DEBUG_FN (DEBUG_TX); + + /* clear old status values */ + *get_eth_reg_addr (NS9750_ETH_EINTR) &= + *get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_TX_MA; + + /* prepare Tx Descriptors */ + + pTxBufferDesc->punSrc = (unsigned int *) pPacket; /* pPacket is 32bit + * aligned */ + pTxBufferDesc->unLen = nLen; + /* only 32bit accesses allowed. wrap, full, interrupt and enabled to 1 */ + pTxBufferDesc->s.unReg = 0xf0000000; + /* pTxBufferDesc is the first possible buffer descriptor */ + *get_eth_reg_addr (NS9750_ETH_TXPTR) = 0x0; + + /* enable processor for next frame */ + + *get_eth_reg_addr (NS9750_ETH_EGCR2) &= ~NS9750_ETH_EGCR2_TCLER; + *get_eth_reg_addr (NS9750_ETH_EGCR2) |= NS9750_ETH_EGCR2_TCLER; + + ulTimeout = get_timer (0); + + DEBUG_ARGS0 (DEBUG_TX | DEBUG_MINOR, + "Waiting for transmission to finish\n"); + while (! + (*get_eth_reg_addr (NS9750_ETH_EINTR) & + (NS9750_ETH_EINTR_TXDONE | NS9750_ETH_EINTR_TXERR))) { + /* do nothing, wait for completion */ + if (get_timer (0) - ulTimeout > TX_TIMEOUT) { + DEBUG_ARGS0 (DEBUG_TX, "Transmit Timed out\n"); + return -1; + } + } + DEBUG_ARGS0 (DEBUG_TX | DEBUG_MINOR, "transmitted...\n"); + + return 0; +} + +/*********************************************************************** + * @Function: eth_rx + * @Return: size of last frame in bytes or 0 if no frame available + * @Descr: gives one frame to U-Boot which has been copied by DMA engine already + * to NetRxPackets[ 0 ]. + ***********************************************************************/ + +int eth_rx (void) +{ + int nLen = 0; + unsigned int unStatus; + + unStatus = + *get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_RX_MA; + + if (!unStatus) + /* no packet available, return immediately */ + return 0; + + DEBUG_FN (DEBUG_RX); + + /* unLen always < max(nLen) and discard checksum */ + nLen = (int) aRxBufferDesc[0].unLen - 4; + + /* acknowledge status register */ + *get_eth_reg_addr (NS9750_ETH_EINTR) = unStatus; + + aRxBufferDesc[0].unLen = 1522; + aRxBufferDesc[0].s.bits.uFull = 0; + + /* Buffer A descriptor available again */ + *get_eth_reg_addr (NS9750_ETH_RXFREE) |= 0x1; + + /* NetReceive may call eth_send. Due to a possible bug of the NS9750 we + * have to acknowledge the received frame before sending a new one */ + if (unStatus & NS9750_ETH_EINTR_RXDONEA) + NetReceive (NetRxPackets[0], nLen); + + return nLen; +} + +/*********************************************************************** + * @Function: eth_halt + * @Return: n/a + * @Descr: stops the ethernet engine + ***********************************************************************/ + +void eth_halt (void) +{ + DEBUG_FN (DEBUG_INIT); + + *get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_RXEN; + *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~(NS9750_ETH_EGCR1_ERX | + NS9750_ETH_EGCR1_ERXDMA | + NS9750_ETH_EGCR1_ETX | + NS9750_ETH_EGCR1_ETXDMA); +} + +/*********************************************************************** + * @Function: ns9750_eth_reset + * @Return: 0 on failure otherwise 1 + * @Descr: resets the ethernet interface and the PHY, + * performs auto negotiation or fixed modes + ***********************************************************************/ + +static int ns9750_eth_reset (void) +{ + DEBUG_FN (DEBUG_MINOR); + + /* Reset MAC */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_MAC_HRST; + udelay (5); /* according to [1], p.322 */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_MAC_HRST; + + /* reset and initialize PHY */ + + *get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_SRST; + + /* we don't support hot plugging of PHY, therefore we don't reset + phyDetected and nPhyMaxMdioClock here. The risk is if the setting is + incorrect the first open + may detect the PHY correctly but succeding will fail + For reseting the PHY and identifying we have to use the standard + MDIO CLOCK value 2.5 MHz only after hardware reset + After having identified the PHY we will do faster */ + + *get_eth_reg_addr (NS9750_ETH_MCFG) = + ns9750_mii_get_clock_divisor (nPhyMaxMdioClock); + + /* reset PHY */ + ns9750_mii_write (PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET); + ns9750_mii_write (PHY_COMMON_CTRL, 0); + + /* @TODO check time */ + udelay (3000); /* [2] p.70 says at least 300us reset recovery time. But + go sure, it didn't worked stable at higher timer + frequencies under LxNETES-2.x */ + + /* MII clock has been setup to default, ns9750_mii_identify_phy should + work for all */ + + if (!ns9750_mii_identify_phy ()) { + printk (KERN_ERR NS9750_DRIVER_NAME + ": Unsupported PHY, aborting\n"); + return 0; + } + + /* now take the highest MDIO clock possible after detection */ + *get_eth_reg_addr (NS9750_ETH_MCFG) = + ns9750_mii_get_clock_divisor (nPhyMaxMdioClock); + + + /* PHY has been detected, so there can be no abort reason and we can + finish initializing ethernet */ + + uiLastLinkStatus = 0xff; /* undefined */ + + if ((ucLinkMode & FS_EEPROM_AUTONEG_ENABLE_MASK) == + FS_EEPROM_AUTONEG_DISABLE) + /* use parameters defined */ + ns9750_link_force (); + else + ns9750_link_auto_negotiate (); + + if (phyDetected == PHY_LXT971A) + /* set LED2 to link mode */ + ns9750_mii_write (PHY_LXT971_LED_CFG, + PHY_LXT971_LED_CFG_LINK_ACT << + PHY_LXT971_LED_CFG_SHIFT_LED2); + + return 1; +} + +/*********************************************************************** + * @Function: ns9750_link_force + * @Return: void + * @Descr: configures eth and MII to use the link mode defined in + * ucLinkMode + ***********************************************************************/ + +static void ns9750_link_force (void) +{ + unsigned short uiControl; + + DEBUG_FN (DEBUG_LINK); + + uiControl = ns9750_mii_read (PHY_COMMON_CTRL); + uiControl &= ~(PHY_COMMON_CTRL_SPD_MA | + PHY_COMMON_CTRL_AUTO_NEG | PHY_COMMON_CTRL_DUPLEX); + + uiLastLinkStatus = 0; + + if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) == + FS_EEPROM_AUTONEG_SPEED_100) { + uiControl |= PHY_COMMON_CTRL_SPD_100; + uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX; + } else + uiControl |= PHY_COMMON_CTRL_SPD_10; + + if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) == + FS_EEPROM_AUTONEG_DUPLEX_FULL) { + uiControl |= PHY_COMMON_CTRL_DUPLEX; + uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE; + } + + ns9750_mii_write (PHY_COMMON_CTRL, uiControl); + + ns9750_link_print_changed (); + ns9750_link_update_egcr (); +} + +/*********************************************************************** + * @Function: ns9750_link_auto_negotiate + * @Return: void + * @Descr: performs auto-negotation of link. + ***********************************************************************/ + +static void ns9750_link_auto_negotiate (void) +{ + unsigned long ulStartJiffies; + unsigned short uiStatus; + + DEBUG_FN (DEBUG_LINK); + + /* run auto-negotation */ + /* define what we are capable of */ + ns9750_mii_write (PHY_COMMON_AUTO_ADV, + PHY_COMMON_AUTO_ADV_100BTXFD | + PHY_COMMON_AUTO_ADV_100BTX | + PHY_COMMON_AUTO_ADV_10BTFD | + PHY_COMMON_AUTO_ADV_10BT | + PHY_COMMON_AUTO_ADV_802_3); + /* start auto-negotiation */ + ns9750_mii_write (PHY_COMMON_CTRL, + PHY_COMMON_CTRL_AUTO_NEG | + PHY_COMMON_CTRL_RES_AUTO); + + /* wait for completion */ + + ulStartJiffies = get_ticks (); + while (get_ticks () < ulStartJiffies + NS9750_MII_NEG_DELAY) { + uiStatus = ns9750_mii_read (PHY_COMMON_STAT); + if ((uiStatus & + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) == + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) { + /* lucky we are, auto-negotiation succeeded */ + ns9750_link_print_changed (); + ns9750_link_update_egcr (); + return; + } + } + + DEBUG_ARGS0 (DEBUG_LINK, "auto-negotiation timed out\n"); + /* ignore invalid link settings */ +} + +/*********************************************************************** + * @Function: ns9750_link_update_egcr + * @Return: void + * @Descr: updates the EGCR and MAC2 link status after mode change or + * auto-negotation + ***********************************************************************/ + +static void ns9750_link_update_egcr (void) +{ + unsigned int unEGCR; + unsigned int unMAC2; + unsigned int unIPGT; + + DEBUG_FN (DEBUG_LINK); + + unEGCR = *get_eth_reg_addr (NS9750_ETH_EGCR1); + unMAC2 = *get_eth_reg_addr (NS9750_ETH_MAC2); + unIPGT = *get_eth_reg_addr (NS9750_ETH_IPGT) & ~NS9750_ETH_IPGT_MA; + + unMAC2 &= ~NS9750_ETH_MAC2_FULLD; + if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE) + == PHY_LXT971_STAT2_DUPLEX_MODE) { + unMAC2 |= NS9750_ETH_MAC2_FULLD; + unIPGT |= 0x15; /* see [1] p. 339 */ + } else + unIPGT |= 0x12; /* see [1] p. 339 */ + + *get_eth_reg_addr (NS9750_ETH_MAC2) = unMAC2; + *get_eth_reg_addr (NS9750_ETH_EGCR1) = unEGCR; + *get_eth_reg_addr (NS9750_ETH_IPGT) = unIPGT; +} + +/*********************************************************************** + * @Function: ns9750_link_print_changed + * @Return: void + * @Descr: checks whether the link status has changed and if so prints + * the new mode + ***********************************************************************/ + +static void ns9750_link_print_changed (void) +{ + unsigned short uiStatus; + unsigned short uiControl; + + DEBUG_FN (DEBUG_LINK); + + uiControl = ns9750_mii_read (PHY_COMMON_CTRL); + + if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) == + PHY_COMMON_CTRL_AUTO_NEG) { + /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */ + uiStatus = ns9750_mii_read (PHY_COMMON_STAT); + + if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) { + printk (KERN_WARNING NS9750_DRIVER_NAME + ": link down\n"); + /* @TODO Linux: carrier_off */ + } else { + /* @TODO Linux: carrier_on */ + if (phyDetected == PHY_LXT971A) { + uiStatus = ns9750_mii_read (PHY_LXT971_STAT2); + uiStatus &= (PHY_LXT971_STAT2_100BTX | + PHY_LXT971_STAT2_DUPLEX_MODE | + PHY_LXT971_STAT2_AUTO_NEG); + + /* mask out all uninteresting parts */ + } + /* other PHYs must store there link information in + uiStatus as PHY_LXT971 */ + } + } else { + /* mode has been forced, so uiStatus should be the same as the + last link status, enforce printing */ + uiStatus = uiLastLinkStatus; + uiLastLinkStatus = 0xff; + } + + if (uiStatus != uiLastLinkStatus) { + /* save current link status */ + uiLastLinkStatus = uiStatus; + + /* print new link status */ + + printk (KERN_INFO NS9750_DRIVER_NAME + ": link mode %i Mbps %s duplex %s\n", + (uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10, + (uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" : + "half", + (uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" : + ""); + } +} + +/*********************************************************************** + * the MII low level stuff + ***********************************************************************/ + +/*********************************************************************** + * @Function: ns9750_mii_identify_phy + * @Return: 1 if supported PHY has been detected otherwise 0 + * @Descr: checks for supported PHY and prints the IDs. + ***********************************************************************/ + +static char ns9750_mii_identify_phy (void) +{ + unsigned short uiID1; + unsigned short uiID2; + unsigned char *szName; + char cRes = 0; + + DEBUG_FN (DEBUG_MII); + + phyDetected = (PhyType) uiID1 = ns9750_mii_read (PHY_COMMON_ID1); + + switch (phyDetected) { + case PHY_LXT971A: + szName = "LXT971A"; + uiID2 = ns9750_mii_read (PHY_COMMON_ID2); + nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; + cRes = 1; + break; + case PHY_NONE: + default: + /* in case uiID1 == 0 && uiID2 == 0 we may have the wrong + address or reset sets the wrong NS9750_ETH_MCFG_CLKS */ + + uiID2 = 0; + szName = "unknown"; + nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; + phyDetected = PHY_NONE; + } + + printk (KERN_INFO NS9750_DRIVER_NAME + ": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName); + + return cRes; +} + +/*********************************************************************** + * @Function: ns9750_mii_read + * @Return: the data read from PHY register uiRegister + * @Descr: the data read may be invalid if timed out. If so, a message + * is printed but the invalid data is returned. + * The fixed device address is being used. + ***********************************************************************/ + +static unsigned short ns9750_mii_read (unsigned short uiRegister) +{ + DEBUG_FN (DEBUG_MII_LOW); + + /* write MII register to be read */ + *get_eth_reg_addr (NS9750_ETH_MADR) = + NS9750_ETH_PHY_ADDRESS << 8 | uiRegister; + + *get_eth_reg_addr (NS9750_ETH_MCMD) = NS9750_ETH_MCMD_READ; + + if (!ns9750_mii_poll_busy ()) + printk (KERN_WARNING NS9750_DRIVER_NAME + ": MII still busy in read\n"); + /* continue to read */ + + *get_eth_reg_addr (NS9750_ETH_MCMD) = 0; + + return (unsigned short) (*get_eth_reg_addr (NS9750_ETH_MRDD)); +} + + +/*********************************************************************** + * @Function: ns9750_mii_write + * @Return: nothing + * @Descr: writes the data to the PHY register. In case of a timeout, + * no special handling is performed but a message printed + * The fixed device address is being used. + ***********************************************************************/ + +static void ns9750_mii_write (unsigned short uiRegister, + unsigned short uiData) +{ + DEBUG_FN (DEBUG_MII_LOW); + + /* write MII register to be written */ + *get_eth_reg_addr (NS9750_ETH_MADR) = + NS9750_ETH_PHY_ADDRESS << 8 | uiRegister; + + *get_eth_reg_addr (NS9750_ETH_MWTD) = uiData; + + if (!ns9750_mii_poll_busy ()) { + printf (KERN_WARNING NS9750_DRIVER_NAME + ": MII still busy in write\n"); + } +} + + +/*********************************************************************** + * @Function: ns9750_mii_get_clock_divisor + * @Return: the clock divisor that should be used in NS9750_ETH_MCFG_CLKS + * @Descr: if no clock divisor can be calculated for the + * current SYSCLK and the maximum MDIO Clock, a warning is printed + * and the greatest divisor is taken + ***********************************************************************/ + +static unsigned int ns9750_mii_get_clock_divisor (unsigned int unMaxMDIOClk) +{ + struct { + unsigned int unSysClkDivisor; + unsigned int unClks; /* field for NS9750_ETH_MCFG_CLKS */ + } PHYClockDivisors[] = { + { + 4, NS9750_ETH_MCFG_CLKS_4}, { + 6, NS9750_ETH_MCFG_CLKS_6}, { + 8, NS9750_ETH_MCFG_CLKS_8}, { + 10, NS9750_ETH_MCFG_CLKS_10}, { + 20, NS9750_ETH_MCFG_CLKS_20}, { + 30, NS9750_ETH_MCFG_CLKS_30}, { + 40, NS9750_ETH_MCFG_CLKS_40} + }; + + int nIndexSysClkDiv; + int nArraySize = + sizeof (PHYClockDivisors) / sizeof (PHYClockDivisors[0]); + unsigned int unClks = NS9750_ETH_MCFG_CLKS_40; /* defaults to + greatest div */ + + DEBUG_FN (DEBUG_INIT); + + for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize; + nIndexSysClkDiv++) { + /* find first sysclock divisor that isn't higher than 2.5 MHz + clock */ + if (AHB_CLK_FREQ / + PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <= + unMaxMDIOClk) { + unClks = PHYClockDivisors[nIndexSysClkDiv].unClks; + break; + } + } + + DEBUG_ARGS2 (DEBUG_INIT, + "Taking MDIO Clock bit mask 0x%0x for max clock %i\n", + unClks, unMaxMDIOClk); + + /* return greatest divisor */ + return unClks; +} + +/*********************************************************************** + * @Function: ns9750_mii_poll_busy + * @Return: 0 if timed out otherwise the remaing timeout + * @Descr: waits until the MII has completed a command or it times out + * code may be interrupted by hard interrupts. + * It is not checked what happens on multiple actions when + * the first is still being busy and we timeout. + ***********************************************************************/ + +static unsigned int ns9750_mii_poll_busy (void) +{ + unsigned int unTimeout = 10000; + + DEBUG_FN (DEBUG_MII_LOW); + + while (((*get_eth_reg_addr (NS9750_ETH_MIND) & NS9750_ETH_MIND_BUSY) + == NS9750_ETH_MIND_BUSY) && unTimeout) + unTimeout--; + + return unTimeout; +} + +#endif /* CONFIG_DRIVER_NS9750_ETHERNET */ diff --git a/drivers/ns9750_serial.c b/drivers/ns9750_serial.c new file mode 100644 index 0000000..aced3da --- /dev/null +++ b/drivers/ns9750_serial.c @@ -0,0 +1,212 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_serial.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Serial driver for the NS9750. Only one UART is supported yet. + * @References: [1] NS9750 Hardware Reference/December 2003 + * @TODO: Implement Character GAP Timer when chip is fixed for PLL bypass + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#include + +#ifdef CFG_NS9750_UART + +#include "ns9750_bbus.h" /* for GPIOs */ +#include "ns9750_ser.h" /* for serial configuration */ + +#define CONSOLE CONFIG_CONS_INDEX + +static unsigned int calcBitrateRegister( void ); +static unsigned int calcRxCharGapRegister( void ); + +static char cCharsAvailable; /* Numbers of chars in unCharCache */ +static unsigned int unCharCache; /* unCharCache is only valid if + * cCharsAvailable > 0 */ + +/*********************************************************************** + * @Function: serial_init + * @Return: 0 + * @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off + ***********************************************************************/ + +int serial_init( void ) +{ + unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 }; + unsigned int aunGPIORxD[] = { 1, 9, 41, 45 }; + + cCharsAvailable = 0; + + /* configure TxD and RxD pins for their special function */ + set_gpio_cfg_reg_val( aunGPIOTxD[ CONSOLE ], + NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_OUTPUT ); + set_gpio_cfg_reg_val( aunGPIORxD[ CONSOLE ], + NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_INPUT ); + + /* configure serial engine */ + *get_ser_reg_addr_channel( NS9750_SER_CTRL_A, CONSOLE ) = + NS9750_SER_CTRL_A_CE | + NS9750_SER_CTRL_A_STOP | + NS9750_SER_CTRL_A_WLS_8; + + serial_setbrg(); + + *get_ser_reg_addr_channel( NS9750_SER_CTRL_B, CONSOLE ) = + NS9750_SER_CTRL_B_RCGT; + + return 0; +} + +/*********************************************************************** + * @Function: serial_putc + * @Return: n/a + * @Descr: writes one character to the FIFO. Blocks until FIFO is not full + ***********************************************************************/ + +void serial_putc( const char c ) +{ + if (c == '\n') + serial_putc( '\r' ); + + while (!(*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE) & + NS9750_SER_STAT_A_TRDY ) ) { + /* do nothing, wait for characters in FIFO sent */ + } + + *(volatile char*) get_ser_reg_addr_channel( NS9750_SER_FIFO, + CONSOLE) = c; +} + +/*********************************************************************** + * @Function: serial_puts + * @Return: n/a + * @Descr: writes non-zero string to the FIFO. + ***********************************************************************/ + +void serial_puts( const char *s ) +{ + while (*s) { + serial_putc( *s++ ); + } +} + +/*********************************************************************** + * @Function: serial_getc + * @Return: the character read + * @Descr: performs only 8bit accesses to the FIFO. No error handling + ***********************************************************************/ + +int serial_getc( void ) +{ + int i; + + while (!serial_tstc() ) { + /* do nothing, wait for incoming characters */ + } + + /* at least one character in unCharCache */ + i = (int) (unCharCache & 0xff); + + unCharCache >>= 8; + cCharsAvailable--; + + return i; +} + +/*********************************************************************** + * @Function: serial_tstc + * @Return: 0 if no input available, otherwise != 0 + * @Descr: checks for incoming FIFO not empty. Stores the incoming chars in + * unCharCache and the numbers of characters in cCharsAvailable + ***********************************************************************/ + +int serial_tstc( void ) +{ + unsigned int unRegCache; + + if ( cCharsAvailable ) + return 1; + + unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,CONSOLE ); + if( unRegCache & NS9750_SER_STAT_A_RBC ) { + *get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE ) = + NS9750_SER_STAT_A_RBC; + unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A, + CONSOLE ); + } + + if ( unRegCache & NS9750_SER_STAT_A_RRDY ) { + cCharsAvailable = (unRegCache & NS9750_SER_STAT_A_RXFDB_MA)>>20; + if ( !cCharsAvailable ) + cCharsAvailable = 4; + + unCharCache = *get_ser_reg_addr_channel( NS9750_SER_FIFO, + CONSOLE ); + return 1; + } + + /* no chars available */ + return 0; +} + +void serial_setbrg( void ) +{ + *get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) = + calcBitrateRegister(); + *get_ser_reg_addr_channel( NS9750_SER_RX_CHAR_TIMER, CONSOLE ) = + calcRxCharGapRegister(); +} + +/*********************************************************************** + * @Function: calcBitrateRegister + * @Return: value for the serial bitrate register + * @Descr: register value depends on clock frequency and baudrate + ***********************************************************************/ + +static unsigned int calcBitrateRegister( void ) +{ + DECLARE_GLOBAL_DATA_PTR; + + return ( NS9750_SER_BITRATE_EBIT | + NS9750_SER_BITRATE_CLKMUX_BCLK | + NS9750_SER_BITRATE_TMODE | + NS9750_SER_BITRATE_TCDR_16 | + NS9750_SER_BITRATE_RCDR_16 | + ( ( ( ( CONFIG_SYS_CLK_FREQ / 8 ) / /* BBUS clock,[1] Fig. 38 */ + ( gd->baudrate * 16 ) ) - 1 ) & + NS9750_SER_BITRATE_N_MA ) ); +} + +/*********************************************************************** + * @Function: calcRxCharGapRegister + * @Return: value for the character gap timer register + * @Descr: register value depends on clock frequency and baudrate. Currently 0 + * is used as there is a bug with the gap timer in PLL bypass mode. + ***********************************************************************/ + +static unsigned int calcRxCharGapRegister( void ) +{ + DECLARE_GLOBAL_DATA_PTR; + + return NS9750_SER_RX_CHAR_TIMER_TRUN; +} + +#endif /* CFG_NS9750_UART */ diff --git a/drivers/omap1510_i2c.c b/drivers/omap1510_i2c.c new file mode 100644 index 0000000..04400fb --- /dev/null +++ b/drivers/omap1510_i2c.c @@ -0,0 +1,281 @@ +/* + * Basic I2C functions + * + * Copyright (c) 2003 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Author: Jian Zhang jzhang@ti.com, Texas Instruments + * + * Copyright (c) 2003 Wolfgang Denk, wd@denx.de + * Rewritten to fit into the current U-Boot framework + * + */ + +#include + +#ifdef CONFIG_DRIVER_OMAP1510_I2C + +static void wait_for_bb (void); +static u16 wait_for_pin (void); + +void i2c_init (int speed, int slaveadd) +{ + u16 scl; + + if (inw (I2C_CON) & I2C_CON_EN) { + outw (0, I2C_CON); + udelay (5000); + } + + /* 12Mhz I2C module clock */ + outw (0, I2C_PSC); + outw (I2C_CON_EN, I2C_CON); + outw (0, I2C_SYSTEST); + /* have to enable intrrupts or OMAP i2c module doesn't work */ + outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | + I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + scl = (12000000 / 2) / speed - 6; + outw (scl, I2C_SCLL); + outw (scl, I2C_SCLH); + /* own address */ + outw (slaveadd, I2C_OA); + outw (0, I2C_CNT); + udelay (1000); +} + +static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) +{ + int i2c_error = 0; + u16 status; + + /* wait until bus not busy */ + wait_for_bb (); + + /* one byte only */ + outw (1, I2C_CNT); + /* set slave address */ + outw (devaddr, I2C_SA); + /* no stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* Important: have to use byte access */ + *(volatile u8 *) (I2C_DATA) = regoffset; + udelay (20000); + if (inw (I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + /* free bus, otherwise we can't use a combined transction */ + outw (0, I2C_CON); + while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (10000); + /* Have to clear pending interrupt to clear I2C_STAT */ + inw (I2C_IV); + } + + wait_for_bb (); + /* set slave address */ + outw (devaddr, I2C_SA); + /* read one byte from slave */ + outw (1, I2C_CNT); + /* need stop bit here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, + I2C_CON); + + status = wait_for_pin (); + if (status & I2C_STAT_RRDY) { + *value = inw (I2C_DATA); + udelay (20000); + } else { + i2c_error = 1; + } + + if (!i2c_error) { + outw (I2C_CON_EN, I2C_CON); + while (inw (I2C_STAT) + || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (10000); + inw (I2C_IV); + } + } + } + + return i2c_error; +} + +static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) +{ + int i2c_error = 0; + u16 status; + + /* wait until bus not busy */ + wait_for_bb (); + + /* two bytes */ + outw (2, I2C_CNT); + /* set slave address */ + outw (devaddr, I2C_SA); + /* stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, I2C_CON); + + /* wait until state change */ + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* send out two bytes */ + outw ((value << 8) + regoffset, I2C_DATA); + /* must have enough delay to allow BB bit to go low */ + udelay (30000); + if (inw (I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + outw (I2C_CON_EN, I2C_CON); + while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (1000); + /* have to read to clear intrrupt */ + inw (I2C_IV); + } + } + + return i2c_error; +} + +int i2c_probe (uchar chip) +{ + int res = 1; + + if (chip == inw (I2C_OA)) { + return res; + } + + /* wait until bus not busy */ + wait_for_bb (); + + /* try to read one byte */ + outw (1, I2C_CNT); + /* set slave address */ + outw (chip, I2C_SA); + /* stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + /* enough delay for the NACK bit set */ + udelay (2000); + if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { + res = 0; + } else { + outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); + udelay (20); + wait_for_bb (); + } + + return res; +} + +int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf ("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_read_byte (chip, addr + i, &buffer[i])) { + printf ("I2C read: I/O error\n"); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf ("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_write_byte (chip, addr + i, buffer[i])) { + printf ("I2C read: I/O error\n"); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +static void wait_for_bb (void) +{ + int timeout = 10; + + while ((inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { + inw (I2C_IV); + udelay (1000); + } + + if (timeout <= 0) { + printf ("timed out in wait_for_bb: I2C_STAT=%x\n", + inw (I2C_STAT)); + } +} + +static u16 wait_for_pin (void) +{ + u16 status, iv; + int timeout = 10; + + do { + udelay (1000); + status = inw (I2C_STAT); + iv = inw (I2C_IV); + } while (!iv && + !(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf ("timed out in wait_for_pin: I2C_STAT=%x\n", + inw (I2C_STAT)); + } + + return status; +} + +#endif /* CONFIG_DRIVER_OMAP1510_I2C */ diff --git a/drivers/omap24xx_i2c.c b/drivers/omap24xx_i2c.c new file mode 100644 index 0000000..7dab786 --- /dev/null +++ b/drivers/omap24xx_i2c.c @@ -0,0 +1,329 @@ +/* + * Basic I2C functions + * + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Author: Jian Zhang jzhang@ti.com, Texas Instruments + * + * Copyright (c) 2003 Wolfgang Denk, wd@denx.de + * Rewritten to fit into the current U-Boot framework + * + * Adapted for OMAP2420 I2C, r-woodruff2@ti.com + * + */ + +#include + +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + +#include +#include + +#define inw(a) __raw_readw(a) +#define outw(a,v) __raw_writew(a,v) + +static void wait_for_bb (void); +static u16 wait_for_pin (void); +static void flush_fifo(void); + +void i2c_init (int speed, int slaveadd) +{ + u16 scl; + + outw(0x2, I2C_SYSC); /* for ES2 after soft reset */ + udelay(1000); + outw(0x0, I2C_SYSC); /* will probably self clear but */ + + if (inw (I2C_CON) & I2C_CON_EN) { + outw (0, I2C_CON); + udelay (50000); + } + + /* 12Mhz I2C module clock */ + outw (0, I2C_PSC); + speed = speed/1000; /* 100 or 400 */ + scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ + outw (scl, I2C_SCLL); + outw (scl, I2C_SCLH); + /* own address */ + outw (slaveadd, I2C_OA); + outw (I2C_CON_EN, I2C_CON); + + /* have to enable intrrupts or OMAP i2c module doesn't work */ + outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | + I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + udelay (1000); + flush_fifo(); + outw (0xFFFF, I2C_STAT); + outw (0, I2C_CNT); +} + +static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) +{ + int i2c_error = 0; + u16 status; + + /* wait until bus not busy */ + wait_for_bb (); + + /* one byte only */ + outw (1, I2C_CNT); + /* set slave address */ + outw (devaddr, I2C_SA); + /* no stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* Important: have to use byte access */ + *(volatile u8 *) (I2C_DATA) = regoffset; + udelay (20000); + if (inw (I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + /* free bus, otherwise we can't use a combined transction */ + outw (0, I2C_CON); + while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (10000); + /* Have to clear pending interrupt to clear I2C_STAT */ + outw (0xFFFF, I2C_STAT); + } + + wait_for_bb (); + /* set slave address */ + outw (devaddr, I2C_SA); + /* read one byte from slave */ + outw (1, I2C_CNT); + /* need stop bit here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, + I2C_CON); + + status = wait_for_pin (); + if (status & I2C_STAT_RRDY) { + *value = inw (I2C_DATA); + udelay (20000); + } else { + i2c_error = 1; + } + + if (!i2c_error) { + outw (I2C_CON_EN, I2C_CON); + while (inw (I2C_STAT) + || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (10000); + outw (0xFFFF, I2C_STAT); + } + } + } + flush_fifo(); + outw (0xFFFF, I2C_STAT); + outw (0, I2C_CNT); + return i2c_error; +} + +static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) +{ + int i2c_error = 0; + u16 status, stat; + + /* wait until bus not busy */ + wait_for_bb (); + + /* two bytes */ + outw (2, I2C_CNT); + /* set slave address */ + outw (devaddr, I2C_SA); + /* stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, I2C_CON); + + /* wait until state change */ + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* send out two bytes */ + outw ((value << 8) + regoffset, I2C_DATA); + /* must have enough delay to allow BB bit to go low */ + udelay (50000); + if (inw (I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + int eout = 200; + + outw (I2C_CON_EN, I2C_CON); + while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (1000); + /* have to read to clear intrrupt */ + outw (0xFFFF, I2C_STAT); + if(--eout == 0) /* better leave with error than hang */ + break; + } + } + flush_fifo(); + outw (0xFFFF, I2C_STAT); + outw (0, I2C_CNT); + return i2c_error; +} + +static void flush_fifo(void) +{ u16 stat; + + /* note: if you try and read data when its not there or ready + * you get a bus error + */ + while(1){ + stat = inw(I2C_STAT); + if(stat == I2C_STAT_RRDY){ + inw(I2C_DATA); + outw(I2C_STAT_RRDY,I2C_STAT); + udelay(1000); + }else + break; + } +} + +int i2c_probe (uchar chip) +{ + int res = 1; /* default = fail */ + + if (chip == inw (I2C_OA)) { + return res; + } + + /* wait until bus not busy */ + wait_for_bb (); + + /* try to read one byte */ + outw (1, I2C_CNT); + /* set slave address */ + outw (chip, I2C_SA); + /* stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + /* enough delay for the NACK bit set */ + udelay (50000); + + if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { + res = 0; /* success case */ + flush_fifo(); + outw(0xFFFF, I2C_STAT); + } else { + outw(0xFFFF, I2C_STAT); /* failue, clear sources*/ + outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + udelay(20000); + wait_for_bb (); + } + flush_fifo(); + outw (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ + outw(0xFFFF, I2C_STAT); + return res; +} + +int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf ("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_read_byte (chip, addr + i, &buffer[i])) { + printf ("I2C read: I/O error\n"); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf ("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_write_byte (chip, addr + i, buffer[i])) { + printf ("I2C read: I/O error\n"); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +static void wait_for_bb (void) +{ + int timeout = 10; + u16 stat; + + outw(0xFFFF, I2C_STAT); /* clear current interruts...*/ + while ((stat = inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { + outw (stat, I2C_STAT); + udelay (50000); + } + + if (timeout <= 0) { + printf ("timed out in wait_for_bb: I2C_STAT=%x\n", + inw (I2C_STAT)); + } + outw(0xFFFF, I2C_STAT); /* clear delayed stuff*/ +} + +static u16 wait_for_pin (void) +{ + u16 status; + int timeout = 10; + + do { + udelay (1000); + status = inw (I2C_STAT); + } while ( !(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf ("timed out in wait_for_pin: I2C_STAT=%x\n", + inw (I2C_STAT)); + outw(0xFFFF, I2C_STAT); +} + return status; +} + +#endif /* CONFIG_DRIVER_OMAP24XX_I2C */ diff --git a/drivers/pc_keyb.c b/drivers/pc_keyb.c new file mode 100644 index 0000000..81d3e98 --- /dev/null +++ b/drivers/pc_keyb.c @@ -0,0 +1,256 @@ +/*********************************************************************** + * + * (C) Copyright 2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * All rights reserved. + * + * PS/2 keyboard driver + * + * Originally from linux source (drivers/char/pc_keyb.c) + * + ***********************************************************************/ + +#include + +#ifdef CONFIG_PS2KBD + +#include +#include + +#undef KBG_DEBUG + +#ifdef KBG_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + + +/* + * This reads the keyboard status port, and does the + * appropriate action. + * + */ +static unsigned char handle_kbd_event(void) +{ + unsigned char status = kbd_read_status(); + unsigned int work = 10000; + + while ((--work > 0) && (status & KBD_STAT_OBF)) { + unsigned char scancode; + + scancode = kbd_read_input(); + + /* Error bytes must be ignored to make the + Synaptics touchpads compaq use work */ + /* Ignore error bytes */ + if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) { + if (status & KBD_STAT_MOUSE_OBF) + ; /* not supported: handle_mouse_event(scancode); */ + else + handle_scancode(scancode); + } + status = kbd_read_status(); + } + if (!work) + PRINTF("pc_keyb: controller jammed (0x%02X).\n", status); + return status; +} + + +static int kbd_read_data(void) +{ + int val; + unsigned char status; + + val=-1; + status = kbd_read_status(); + if (status & KBD_STAT_OBF) { + val = kbd_read_input(); + if (status & (KBD_STAT_GTO | KBD_STAT_PERR)) + val = -2; + } + return val; +} + +static int kbd_wait_for_input(void) +{ + unsigned long timeout; + int val; + + timeout = KBD_TIMEOUT; + val=kbd_read_data(); + while(val < 0) { + if(timeout--==0) + return -1; + udelay(1000); + val=kbd_read_data(); + } + return val; +} + + +static int kb_wait(void) +{ + unsigned long timeout = KBC_TIMEOUT * 10; + + do { + unsigned char status = handle_kbd_event(); + if (!(status & KBD_STAT_IBF)) + return 0; /* ok */ + udelay(1000); + timeout--; + } while (timeout); + return 1; +} + +static void kbd_write_command_w(int data) +{ + if(kb_wait()) + PRINTF("timeout in kbd_write_command_w\n"); + kbd_write_command(data); +} + +static void kbd_write_output_w(int data) +{ + if(kb_wait()) + PRINTF("timeout in kbd_write_output_w\n"); + kbd_write_output(data); +} + +static void kbd_send_data(unsigned char data) +{ + kbd_write_output_w(data); + kbd_wait_for_input(); +} + + +static char * kbd_initialize(void) +{ + int status; + + /* + * Test the keyboard interface. + * This seems to be the only way to get it going. + * If the test is successful a x55 is placed in the input buffer. + */ + kbd_write_command_w(KBD_CCMD_SELF_TEST); + if (kbd_wait_for_input() != 0x55) + return "Kbd: failed self test"; + /* + * Perform a keyboard interface test. This causes the controller + * to test the keyboard clock and data lines. The results of the + * test are placed in the input buffer. + */ + kbd_write_command_w(KBD_CCMD_KBD_TEST); + if (kbd_wait_for_input() != 0x00) + return "Kbd: interface failed self test"; + /* + * Enable the keyboard by allowing the keyboard clock to run. + */ + kbd_write_command_w(KBD_CCMD_KBD_ENABLE); + + /* + * Reset keyboard. If the read times out + * then the assumption is that no keyboard is + * plugged into the machine. + * This defaults the keyboard to scan-code set 2. + * + * Set up to try again if the keyboard asks for RESEND. + */ + do { + kbd_write_output_w(KBD_CMD_RESET); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + break; + if (status != KBD_REPLY_RESEND) { + PRINTF("status: %X\n",status); + return "Kbd: reset failed, no ACK"; + } + } while (1); + if (kbd_wait_for_input() != KBD_REPLY_POR) + return "Kbd: reset failed, no POR"; + + /* + * Set keyboard controller mode. During this, the keyboard should be + * in the disabled state. + * + * Set up to try again if the keyboard asks for RESEND. + */ + do { + kbd_write_output_w(KBD_CMD_DISABLE); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + break; + if (status != KBD_REPLY_RESEND) + return "Kbd: disable keyboard: no ACK"; + } while (1); + + kbd_write_command_w(KBD_CCMD_WRITE_MODE); + kbd_write_output_w(KBD_MODE_KBD_INT + | KBD_MODE_SYS + | KBD_MODE_DISABLE_MOUSE + | KBD_MODE_KCC); + + /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */ + kbd_write_command_w(KBD_CCMD_READ_MODE); + if (!(kbd_wait_for_input() & KBD_MODE_KCC)) { + /* + * If the controller does not support conversion, + * Set the keyboard to scan-code set 1. + */ + kbd_write_output_w(0xF0); + kbd_wait_for_input(); + kbd_write_output_w(0x01); + kbd_wait_for_input(); + } + kbd_write_output_w(KBD_CMD_ENABLE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: enable keyboard: no ACK"; + + /* + * Finally, set the typematic rate to maximum. + */ + kbd_write_output_w(KBD_CMD_SET_RATE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: Set rate: no ACK"; + kbd_write_output_w(0x00); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: Set rate: no ACK"; + return NULL; +} + +static void kbd_interrupt(void *dev_id) +{ + handle_kbd_event(); +} + +/****************************************************************** + * Init + ******************************************************************/ + +int kbd_init_hw(void) +{ + char* result; + + kbd_request_region(); + + result=kbd_initialize(); + if (result==NULL) { + PRINTF("AT Keyboard initialized\n"); + kbd_request_irq(kbd_interrupt); + return (1); + } else { + printf("%s\n",result); + return (-1); + } +} + +void pckbd_leds(unsigned char leds) +{ + kbd_send_data(KBD_CMD_SET_LEDS); + kbd_send_data(leds); +} + +#endif /* CONFIG_PS2KBD */ diff --git a/drivers/pci.c b/drivers/pci.c new file mode 100644 index 0000000..5360030 --- /dev/null +++ b/drivers/pci.c @@ -0,0 +1,517 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * (C) Copyright 2002, 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI routines + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include + +#define PCI_HOSE_OP(rw, size, type) \ +int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, \ + int offset, type value) \ +{ \ + return hose->rw##_##size(hose, dev, offset, value); \ +} + +PCI_HOSE_OP(read, byte, u8 *) +PCI_HOSE_OP(read, word, u16 *) +PCI_HOSE_OP(read, dword, u32 *) +PCI_HOSE_OP(write, byte, u8) +PCI_HOSE_OP(write, word, u16) +PCI_HOSE_OP(write, dword, u32) + +#ifndef CONFIG_IXP425 +#define PCI_OP(rw, size, type, error_code) \ +int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ +{ \ + struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ + \ + if (!hose) \ + { \ + error_code; \ + return -1; \ + } \ + \ + return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ +} + +PCI_OP(read, byte, u8 *, *value = 0xff) +PCI_OP(read, word, u16 *, *value = 0xffff) +PCI_OP(read, dword, u32 *, *value = 0xffffffff) +PCI_OP(write, byte, u8, ) +PCI_OP(write, word, u16, ) +PCI_OP(write, dword, u32, ) +#endif /* CONFIG_IXP425 */ + +#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ +int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ + pci_dev_t dev, \ + int offset, type val) \ +{ \ + u32 val32; \ + \ + if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ + return -1; \ + \ + *val = (val32 >> ((offset & (int)off_mask) * 8)); \ + \ + return 0; \ +} + +#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ +int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ + pci_dev_t dev, \ + int offset, type val) \ +{ \ + u32 val32, mask, ldata, shift; \ + \ + if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ + return -1; \ + \ + shift = ((offset & (int)off_mask) * 8); \ + ldata = (((unsigned long)val) & val_mask) << shift; \ + mask = val_mask << shift; \ + val32 = (val32 & ~mask) | ldata; \ + \ + if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ + return -1; \ + \ + return 0; \ +} + +PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) +PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) +PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) +PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) + +/* + * + */ + +static struct pci_controller* hose_head = NULL; + +void pci_register_hose(struct pci_controller* hose) +{ + struct pci_controller **phose = &hose_head; + + while(*phose) + phose = &(*phose)->next; + + hose->next = NULL; + + *phose = hose; +} + +struct pci_controller *pci_bus_to_hose (int bus) +{ + struct pci_controller *hose; + + for (hose = hose_head; hose; hose = hose->next) + if (bus >= hose->first_busno && bus <= hose->last_busno) + return hose; + + printf("pci_bus_to_hose() failed\n"); + return NULL; +} + +#ifndef CONFIG_IXP425 +pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) +{ + struct pci_controller * hose; + u16 vendor, device; + u8 header_type; + pci_dev_t bdf; + int i, bus, found_multi = 0; + + for (hose = hose_head; hose; hose = hose->next) + { +#ifdef CFG_SCSI_SCAN_BUS_REVERSE + for (bus = hose->last_busno; bus >= hose->first_busno; bus--) +#else + for (bus = hose->first_busno; bus <= hose->last_busno; bus++) +#endif + for (bdf = PCI_BDF(bus,0,0); +#ifdef CONFIG_ELPPC + bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); +#else + bdf < PCI_BDF(bus+1,0,0); +#endif + bdf += PCI_BDF(0,0,1)) + { + if (!PCI_FUNC(bdf)) { + pci_read_config_byte(bdf, + PCI_HEADER_TYPE, + &header_type); + + found_multi = header_type & 0x80; + } else { + if (!found_multi) + continue; + } + + pci_read_config_word(bdf, + PCI_VENDOR_ID, + &vendor); + pci_read_config_word(bdf, + PCI_DEVICE_ID, + &device); + + for (i=0; ids[i].vendor != 0; i++) + if (vendor == ids[i].vendor && + device == ids[i].device) + { + if (index <= 0) + return bdf; + + index--; + } + } + } + + return (-1); +} +#endif /* CONFIG_IXP425 */ + +pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) +{ + static struct pci_device_id ids[2] = {{}, {0, 0}}; + + ids[0].vendor = vendor; + ids[0].device = device; + + return pci_find_devices(ids, index); +} + +/* + * + */ + +unsigned long pci_hose_phys_to_bus (struct pci_controller *hose, + unsigned long phys_addr, + unsigned long flags) +{ + struct pci_region *res; + unsigned long bus_addr; + int i; + + if (!hose) { + printf ("pci_hose_phys_to_bus: %s\n", "invalid hose"); + goto Done; + } + + for (i = 0; i < hose->region_count; i++) { + res = &hose->regions[i]; + + if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + continue; + + bus_addr = phys_addr - res->phys_start + res->bus_start; + + if (bus_addr >= res->bus_start && + bus_addr < res->bus_start + res->size) { + return bus_addr; + } + } + + printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address"); + +Done: + return 0; +} + +unsigned long pci_hose_bus_to_phys(struct pci_controller* hose, + unsigned long bus_addr, + unsigned long flags) +{ + struct pci_region *res; + int i; + + if (!hose) { + printf ("pci_hose_bus_to_phys: %s\n", "invalid hose"); + goto Done; + } + + for (i = 0; i < hose->region_count; i++) { + res = &hose->regions[i]; + + if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + continue; + + if (bus_addr >= res->bus_start && + bus_addr < res->bus_start + res->size) { + return bus_addr - res->bus_start + res->phys_start; + } + } + + printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address"); + +Done: + return 0; +} + +/* + * + */ + +int pci_hose_config_device(struct pci_controller *hose, + pci_dev_t dev, + unsigned long io, + unsigned long mem, + unsigned long command) +{ + unsigned int bar_response, bar_size, bar_value, old_command; + unsigned char pin; + int bar, found_mem64; + + debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n", + io, mem, command); + + pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0); + + for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) { + pci_hose_write_config_dword (hose, dev, bar, 0xffffffff); + pci_hose_read_config_dword (hose, dev, bar, &bar_response); + + if (!bar_response) + continue; + + found_mem64 = 0; + + /* Check the BAR type and set our address mask */ + if (bar_response & PCI_BASE_ADDRESS_SPACE) { + bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; + /* round up region base address to a multiple of size */ + io = ((io - 1) | (bar_size - 1)) + 1; + bar_value = io; + /* compute new region base address */ + io = io + bar_size; + } else { + if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == + PCI_BASE_ADDRESS_MEM_TYPE_64) + found_mem64 = 1; + + bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1; + + /* round up region base address to multiple of size */ + mem = ((mem - 1) | (bar_size - 1)) + 1; + bar_value = mem; + /* compute new region base address */ + mem = mem + bar_size; + } + + /* Write it out and update our limit */ + pci_hose_write_config_dword (hose, dev, bar, bar_value); + + if (found_mem64) { + bar += 4; + pci_hose_write_config_dword (hose, dev, bar, 0x00000000); + } + } + + /* Configure Cache Line Size Register */ + pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* Configure Latency Timer */ + pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80); + + /* Disable interrupt line, if device says it wants to use interrupts */ + pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin); + if (pin != 0) { + pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff); + } + + pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command); + pci_hose_write_config_dword (hose, dev, PCI_COMMAND, + (old_command & 0xffff0000) | command); + + return 0; +} + +/* + * + */ + +struct pci_config_table *pci_find_config(struct pci_controller *hose, + unsigned short class, + unsigned int vendor, + unsigned int device, + unsigned int bus, + unsigned int dev, + unsigned int func) +{ + struct pci_config_table *table; + + for (table = hose->config_table; table && table->vendor; table++) { + if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && + (table->device == PCI_ANY_ID || table->device == device) && + (table->class == PCI_ANY_ID || table->class == class) && + (table->bus == PCI_ANY_ID || table->bus == bus) && + (table->dev == PCI_ANY_ID || table->dev == dev) && + (table->func == PCI_ANY_ID || table->func == func)) { + return table; + } + } + + return NULL; +} + +void pci_cfgfunc_config_device(struct pci_controller *hose, + pci_dev_t dev, + struct pci_config_table *entry) +{ + pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]); +} + +void pci_cfgfunc_do_nothing(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ +} + +/* + * + */ + +/* HJF: Changed this to return int. I think this is required + * to get the correct result when scanning bridges + */ +extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); +extern void pciauto_config_init(struct pci_controller *hose); + +int pci_hose_scan_bus(struct pci_controller *hose, int bus) +{ + unsigned int sub_bus, found_multi=0; + unsigned short vendor, device, class; + unsigned char header_type; + struct pci_config_table *cfg; + pci_dev_t dev; + + sub_bus = bus; + + for (dev = PCI_BDF(bus,0,0); + dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); + dev += PCI_BDF(0,0,1)) + { + /* Skip our host bridge */ + if ( dev == PCI_BDF(hose->first_busno,0,0) ) { +#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */ + /* + * Only skip hostbridge configuration if "pciconfighost" is not set + */ + if (getenv("pciconfighost") == NULL) { + continue; /* Skip our host bridge */ + } +#else + continue; /* Skip our host bridge */ +#endif + } + + if (PCI_FUNC(dev) && !found_multi) + continue; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); + + pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); + + if (vendor != 0xffff && vendor != 0x0000) { + + if (!PCI_FUNC(dev)) + found_multi = header_type & 0x80; + + debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n", + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) ); + + pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); + + cfg = pci_find_config(hose, class, vendor, device, + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); + if (cfg) { + cfg->config_device(hose, dev, cfg); +#ifdef CONFIG_PCI_PNP + } else { + int n = pciauto_config_device(hose, dev); + + sub_bus = max(sub_bus, n); +#endif + } + if (hose->fixup_irq) + hose->fixup_irq(hose, dev); + +#ifdef CONFIG_PCI_SCAN_SHOW + /* Skip our host bridge */ + if ( dev != PCI_BDF(hose->first_busno,0,0) ) { + unsigned char int_line; + + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE, + &int_line); + printf(" %02x %02x %04x %04x %04x %02x\n", + PCI_BUS(dev), PCI_DEV(dev), vendor, device, class, + int_line); + } +#endif + } + } + + return sub_bus; +} + +int pci_hose_scan(struct pci_controller *hose) +{ +#ifdef CONFIG_PCI_PNP + pciauto_config_init(hose); +#endif + return pci_hose_scan_bus(hose, hose->first_busno); +} + +void pci_init(void) +{ +#if defined(CONFIG_PCI_BOOTDELAY) + char *s; + int i; + + /* wait "pcidelay" ms (if defined)... */ + s = getenv ("pcidelay"); + if (s) { + int val = simple_strtoul (s, NULL, 10); + for (i=0; i + * + * Copyright 2000 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#ifdef CONFIG_PCI + +#include + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define PCIAUTO_IDE_MODE_MASK 0x05 + +/* + * + */ + +void pciauto_region_init(struct pci_region* res) +{ + res->bus_lower = res->bus_start; +} + +void pciauto_region_align(struct pci_region *res, unsigned long size) +{ + res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; +} + +int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar) +{ + unsigned long addr; + + if (!res) { + DEBUGF("No resource"); + goto error; + } + + addr = ((res->bus_lower - 1) | (size - 1)) + 1; + + if (addr - res->bus_start + size > res->size) { + DEBUGF("No room in resource"); + goto error; + } + + res->bus_lower = addr + size; + + DEBUGF("address=0x%lx", addr); + + *bar = addr; + return 0; + + error: + *bar = 0xffffffff; + return -1; +} + +/* + * + */ + +void pciauto_setup_device(struct pci_controller *hose, + pci_dev_t dev, int bars_num, + struct pci_region *mem, + struct pci_region *io) +{ + unsigned int bar_value, bar_response, bar_size; + unsigned int cmdstat = 0; + struct pci_region *bar_res; + int bar, bar_nr = 0; + int found_mem64 = 0; + + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; + + for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) { + /* Tickle the BAR and get the response */ + pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); + pci_hose_read_config_dword(hose, dev, bar, &bar_response); + + /* If BAR is not implemented go to the next BAR */ + if (!bar_response) + continue; + + found_mem64 = 0; + + /* Check the BAR type and set our address mask */ + if (bar_response & PCI_BASE_ADDRESS_SPACE) { + bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; + bar_res = io; + + DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size); + } else { + if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == + PCI_BASE_ADDRESS_MEM_TYPE_64) + found_mem64 = 1; + + bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1; + bar_res = mem; + + DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size); + } + + if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) { + /* Write it out and update our limit */ + pci_hose_write_config_dword(hose, dev, bar, bar_value); + + /* + * If we are a 64-bit decoder then increment to the + * upper 32 bits of the bar and force it to locate + * in the lower 4GB of memory. + */ + if (found_mem64) { + bar += 4; + pci_hose_write_config_dword(hose, dev, bar, 0x00000000); + } + + cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? + PCI_COMMAND_IO : PCI_COMMAND_MEMORY; + } + + DEBUGF("\n"); + + bar_nr++; + } + + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); +} + +static void pciauto_prescan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus) +{ + struct pci_region *pci_mem = hose->pci_mem; + struct pci_region *pci_io = hose->pci_io; + unsigned int cmdstat; + + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + + /* Configure bus number registers */ + pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); + pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); + pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); + + if (pci_mem) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_mem, 0x100000); + + /* Set up memory and I/O filter limits, assume 32-bit I/O space */ + pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, + (pci_mem->bus_lower & 0xfff00000) >> 16); + + cmdstat |= PCI_COMMAND_MEMORY; + } + + if (pci_io) { + /* Round I/O allocator to 4KB boundary */ + pciauto_region_align(pci_io, 0x1000); + + pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, + (pci_io->bus_lower & 0x0000f000) >> 8); + pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, + (pci_io->bus_lower & 0xffff0000) >> 16); + + cmdstat |= PCI_COMMAND_IO; + } + + /* We don't support prefetchable memory for now, so disable */ + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); + + /* Enable memory and I/O accesses, enable bus master */ + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); +} + +static void pciauto_postscan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus) +{ + struct pci_region *pci_mem = hose->pci_mem; + struct pci_region *pci_io = hose->pci_io; + + /* Configure bus number registers */ + pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); + + if (pci_mem) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_mem, 0x100000); + + pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, + (pci_mem->bus_lower-1) >> 16); + } + + if (pci_io) { + /* Round I/O allocator to 4KB boundary */ + pciauto_region_align(pci_io, 0x1000); + + pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, + ((pci_io->bus_lower-1) & 0x0000f000) >> 8); + pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, + ((pci_io->bus_lower-1) & 0xffff0000) >> 16); + } +} + +/* + * + */ + +void pciauto_config_init(struct pci_controller *hose) +{ + int i; + + hose->pci_io = hose->pci_mem = NULL; + + for (i=0; iregion_count; i++) { + switch(hose->regions[i].flags) { + case PCI_REGION_IO: + if (!hose->pci_io || + hose->pci_io->size < hose->regions[i].size) + hose->pci_io = hose->regions + i; + break; + case PCI_REGION_MEM: + if (!hose->pci_mem || + hose->pci_mem->size < hose->regions[i].size) + hose->pci_mem = hose->regions + i; + break; + } + } + + + if (hose->pci_mem) { + pciauto_region_init(hose->pci_mem); + + DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n", + hose->pci_mem->bus_start, + hose->pci_mem->bus_start + hose->pci_mem->size - 1); + } + + if (hose->pci_io) { + pciauto_region_init(hose->pci_io); + + DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n", + hose->pci_io->bus_start, + hose->pci_io->bus_start + hose->pci_io->size - 1); + } +} + +/* HJF: Changed this to return int. I think this is required + * to get the correct result when scanning bridges + */ +int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned int sub_bus = PCI_BUS(dev); + unsigned short class; + unsigned char prg_iface; + int n; + + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); + + switch(class) { + case PCI_CLASS_BRIDGE_PCI: + hose->current_busno++; + pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io); + + DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); + + /* Passing in current_busno allows for sibling P2P bridges */ + pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); + /* + * need to figure out if this is a subordinate bridge on the bus + * to be able to properly set the pri/sec/sub bridge registers. + */ + n = pci_hose_scan_bus(hose, hose->current_busno); + + /* figure out the deepest we've gone for this leg */ + sub_bus = max(n, sub_bus); + pciauto_postscan_setup_bridge(hose, dev, sub_bus); + + sub_bus = hose->current_busno; + break; + + case PCI_CLASS_STORAGE_IDE: + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); + if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { + DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n"); + return sub_bus; + } + + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); + break; + + case PCI_CLASS_BRIDGE_CARDBUS: + /* just do a minimal setup of the bridge, let the OS take care of the rest */ + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io); + + DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev)); + + hose->current_busno++; + break; + +#ifdef CONFIG_MPC5200 + case PCI_CLASS_BRIDGE_OTHER: + DEBUGF("PCI Autoconfig: Skipping bridge device %d\n", + PCI_DEV(dev)); + break; +#endif +#ifdef CONFIG_MPC834X + case PCI_CLASS_BRIDGE_OTHER: + /* + * The host/PCI bridge 1 seems broken in 8349 - it presents + * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ + * device claiming resources io/mem/irq.. we only allow for + * the PIMMR window to be allocated (BAR0 - 1MB size) + */ + DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n"); + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io); + break; +#endif + default: + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); + break; + } + + return sub_bus; +} + +#endif /* CONFIG_PCI */ diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c new file mode 100644 index 0000000..e8f19f5 --- /dev/null +++ b/drivers/pci_indirect.c @@ -0,0 +1,122 @@ +/* + * Support for indirect PCI bridges. + * + * Copyright (C) 1998 Gabriel Paubert. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include + +#ifdef CONFIG_PCI +#if (!defined(__I386__) && !defined(CONFIG_IXDP425)) + +#include +#include +#include + +#define cfg_read(val, addr, type, op) *val = op((type)(addr)) +#define cfg_write(val, addr, type, op) op((type *)(addr), (val)) + +#ifdef CONFIG_IXP425 +extern unsigned char in_8 (volatile unsigned *addr); +extern unsigned short in_le16 (volatile unsigned *addr); +extern unsigned in_le32 (volatile unsigned *addr); +extern void out_8 (volatile unsigned *addr, char val); +extern void out_le16 (volatile unsigned *addr, unsigned short val); +extern void out_le32 (volatile unsigned *addr, unsigned int val); +#endif /* CONFIG_IXP425 */ + +#if defined(CONFIG_MPC8260) +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + sync(); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} +#elif defined(CONFIG_E500) +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + *(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \ + sync(); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} +#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + if (PCI_BUS(dev) > 0) \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \ + else \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} +#else +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} +#endif + +#define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + unsigned int msr = mfmsr(); \ + mtmsr(msr & ~(MSR_EE | MSR_CE)); \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + out_le32(hose->cfg_addr, 0x00000000); \ + mtmsr(msr); \ + return 0; \ +} + +INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3) +INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2) +INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0) +#ifdef CONFIG_405GP +INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3) +INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2) +INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0) +#else +INDIRECT_PCI_OP(write, byte, u8, out_8, 3) +INDIRECT_PCI_OP(write, word, u16, out_le16, 2) +INDIRECT_PCI_OP(write, dword, u32, out_le32, 0) +#endif + +void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) +{ + pci_set_ops(hose, + indirect_read_config_byte, + indirect_read_config_word, + indirect_read_config_dword, + indirect_write_config_byte, + indirect_write_config_word, + indirect_write_config_dword); + + hose->cfg_addr = (unsigned int *) cfg_addr; + hose->cfg_data = (unsigned char *) cfg_data; +} + +#endif /* !__I386__ && !CONFIG_IXDP425 */ +#endif /* CONFIG_PCI */ diff --git a/drivers/pcnet.c b/drivers/pcnet.c new file mode 100644 index 0000000..da9ac7f --- /dev/null +++ b/drivers/pcnet.c @@ -0,0 +1,526 @@ +/* + * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. + * + * This driver for AMD PCnet network controllers is derived from the + * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#if 0 +#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ +#endif + +#if PCNET_DEBUG_LEVEL > 0 +#define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args) +#if PCNET_DEBUG_LEVEL > 1 +#define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args) +#else +#define PCNET_DEBUG2(fmt,args...) +#endif +#else +#define PCNET_DEBUG1(fmt,args...) +#define PCNET_DEBUG2(fmt,args...) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_PCNET) + +#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) +#error "Macro for PCnet chip version is not defined!" +#endif + +/* + * Set the number of Tx and Rx buffers, using Log_2(# buffers). + * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. + * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). + */ +#define PCNET_LOG_TX_BUFFERS 0 +#define PCNET_LOG_RX_BUFFERS 2 + +#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) +#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) + +#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) +#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) + +#define PKT_BUF_SZ 1544 + +/* The PCNET Rx and Tx ring descriptors. */ +struct pcnet_rx_head { + u32 base; + s16 buf_length; + s16 status; + u32 msg_length; + u32 reserved; +}; + +struct pcnet_tx_head { + u32 base; + s16 length; + s16 status; + u32 misc; + u32 reserved; +}; + +/* The PCNET 32-Bit initialization block, described in databook. */ +struct pcnet_init_block { + u16 mode; + u16 tlen_rlen; + u8 phys_addr[6]; + u16 reserved; + u32 filter[2]; + /* Receive and transmit ring base, along with extra bits. */ + u32 rx_ring; + u32 tx_ring; + u32 reserved2; +}; + +typedef struct pcnet_priv { + struct pcnet_rx_head rx_ring[RX_RING_SIZE]; + struct pcnet_tx_head tx_ring[TX_RING_SIZE]; + struct pcnet_init_block init_block; + /* Receive Buffer space */ + unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; + int cur_rx; + int cur_tx; +} pcnet_priv_t; + +static pcnet_priv_t *lp; + +/* Offsets from base I/O address for WIO mode */ +#define PCNET_RDP 0x10 +#define PCNET_RAP 0x12 +#define PCNET_RESET 0x14 +#define PCNET_BDP 0x16 + +static u16 pcnet_read_csr (struct eth_device *dev, int index) +{ + outw (index, dev->iobase+PCNET_RAP); + return inw (dev->iobase+PCNET_RDP); +} + +static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) +{ + outw (index, dev->iobase+PCNET_RAP); + outw (val, dev->iobase+PCNET_RDP); +} + +static u16 pcnet_read_bcr (struct eth_device *dev, int index) +{ + outw (index, dev->iobase+PCNET_RAP); + return inw (dev->iobase+PCNET_BDP); +} + +static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) +{ + outw (index, dev->iobase+PCNET_RAP); + outw (val, dev->iobase+PCNET_BDP); +} + +static void pcnet_reset (struct eth_device *dev) +{ + inw (dev->iobase+PCNET_RESET); +} + +static int pcnet_check (struct eth_device *dev) +{ + outw (88, dev->iobase+PCNET_RAP); + return (inw (dev->iobase+PCNET_RAP) == 88); +} + +static int pcnet_init( struct eth_device* dev, bd_t *bis); +static int pcnet_send (struct eth_device* dev, volatile void *packet, + int length); +static int pcnet_recv (struct eth_device* dev); +static void pcnet_halt (struct eth_device* dev); +static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_num); + +#define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) +#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE }, + { } +}; + + +int pcnet_initialize(bd_t *bis) +{ + pci_dev_t devbusfn; + struct eth_device* dev; + u16 command, status; + int dev_nr = 0; + + PCNET_DEBUG1("\npcnet_initialize...\n"); + + for (dev_nr = 0; ; dev_nr++) { + + /* + * Find the PCnet PCI device(s). + */ + if ((devbusfn = pci_find_devices(supported, dev_nr)) < 0) { + break; + } + + /* + * Allocate and pre-fill the device structure. + */ + dev = (struct eth_device*) malloc(sizeof *dev); + dev->priv = (void *)devbusfn; + sprintf(dev->name, "pcnet#%d", dev_nr); + + /* + * Setup the PCI device. + */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase); + dev->iobase &= ~0xf; + + PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", + dev->name, devbusfn, dev->iobase); + + command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; + pci_write_config_word(devbusfn, PCI_COMMAND, command); + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + if ((status & command) != command) { + printf("%s: Couldn't enable IO access or Bus Mastering\n", + dev->name); + free(dev); + continue; + } + + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); + + /* + * Probe the PCnet chip. + */ + if (pcnet_probe(dev, bis, dev_nr) < 0) { + free(dev); + continue; + } + + /* + * Setup device structure and register the driver. + */ + dev->init = pcnet_init; + dev->halt = pcnet_halt; + dev->send = pcnet_send; + dev->recv = pcnet_recv; + + eth_register(dev); + } + + udelay(10 * 1000); + + return dev_nr; +} + +static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_nr) +{ + int chip_version; + char *chipname; +#ifdef PCNET_HAS_PROM + int i; +#endif + + /* Reset the PCnet controller */ + pcnet_reset(dev); + + /* Check if register access is working */ + if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { + printf("%s: CSR register access check failed\n", dev->name); + return -1; + } + + /* Identify the chip */ + chip_version = pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev,89) << 16); + if ((chip_version & 0xfff) != 0x003) + return -1; + chip_version = (chip_version >> 12) & 0xffff; + switch (chip_version) { +#ifdef CONFIG_PCNET_79C973 + case 0x2625: + chipname = "PCnet/FAST III 79C973"; /* PCI */ + break; +#endif +#ifdef CONFIG_PCNET_79C975 + case 0x2627: + chipname = "PCnet/FAST III 79C975"; /* PCI */ + break; +#endif + default: + printf("%s: PCnet version %#x not supported\n", + dev->name, chip_version); + return -1; + } + + PCNET_DEBUG1("AMD %s\n", chipname); + +#ifdef PCNET_HAS_PROM + /* + * In most chips, after a chip reset, the ethernet address is read from + * the station address PROM at the base address and programmed into the + * "Physical Address Registers" CSR12-14. + */ + for (i = 0; i < 3; i++) { + unsigned int val; + val = pcnet_read_csr(dev, i+12) & 0x0ffff; + /* There may be endianness issues here. */ + dev->enetaddr[2*i ] = val & 0x0ff; + dev->enetaddr[2*i+1] = (val >> 8) & 0x0ff; + } +#endif /* PCNET_HAS_PROM */ + + return 0; +} + +static int pcnet_init(struct eth_device* dev, bd_t *bis) +{ + int i, val; + u32 addr; + + PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); + + /* Switch pcnet to 32bit mode */ + pcnet_write_bcr (dev, 20, 2); + +#ifdef CONFIG_PN62 + /* Setup LED registers */ + val = pcnet_read_bcr (dev, 2) | 0x1000; + pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ + pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ + pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ + pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ + pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ +#endif + + /* Set/reset autoselect bit */ + val = pcnet_read_bcr (dev, 2) & ~2; + val |= 2; + pcnet_write_bcr (dev, 2, val); + + /* Enable auto negotiate, setup, disable fd */ + val = pcnet_read_bcr(dev, 32) & ~0x98; + val |= 0x20; + pcnet_write_bcr(dev, 32, val); + + /* + * We only maintain one structure because the drivers will never + * be used concurrently. In 32bit mode the RX and TX ring entries + * must be aligned on 16-byte boundaries. + */ + if (lp == NULL) { + addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); + addr = (addr + 0xf) & ~0xf; + lp = (pcnet_priv_t *)addr; + } + + lp->init_block.mode = cpu_to_le16(0x0000); + lp->init_block.filter[0] = 0x00000000; + lp->init_block.filter[1] = 0x00000000; + + /* + * Initialize the Rx ring. + */ + lp->cur_rx = 0; + for (i = 0; i < RX_RING_SIZE; i++) { + lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); + lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); + lp->rx_ring[i].status = cpu_to_le16(0x8000); + PCNET_DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", + i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length, + lp->rx_ring[i].status); + } + + /* + * Initialize the Tx ring. The Tx buffer address is filled in as + * needed, but we do need to clear the upper ownership bit. + */ + lp->cur_tx = 0; + for (i = 0; i < TX_RING_SIZE; i++) { + lp->tx_ring[i].base = 0; + lp->tx_ring[i].status = 0; + } + + /* + * Setup Init Block. + */ + PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block); + + for (i = 0; i < 6; i++) { + lp->init_block.phys_addr[i] = dev->enetaddr[i]; + PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]); + } + + lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | + RX_RING_LEN_BITS); + lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); + lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); + + PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", + lp->init_block.tlen_rlen, + lp->init_block.rx_ring, lp->init_block.tx_ring); + + /* + * Tell the controller where the Init Block is located. + */ + addr = PCI_TO_MEM(dev, &lp->init_block); + pcnet_write_csr(dev, 1, addr & 0xffff); + pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); + + pcnet_write_csr (dev, 4, 0x0915); + pcnet_write_csr (dev, 0, 0x0001); /* start */ + + /* Wait for Init Done bit */ + for (i = 10000; i > 0; i--) { + if (pcnet_read_csr (dev, 0) & 0x0100) + break; + udelay(10); + } + if (i <= 0) { + printf("%s: TIMEOUT: controller init failed\n", dev->name); + pcnet_reset (dev); + return 0; + } + + /* + * Finally start network controller operation. + */ + pcnet_write_csr (dev, 0, 0x0002); + + return 1; +} + +static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len) +{ + int i, status; + struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; + + PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet); + + /* Wait for completion by testing the OWN bit */ + for (i = 1000; i > 0; i--) { + status = le16_to_cpu(entry->status); + if ((status & 0x8000) == 0) + break; + udelay(100); + PCNET_DEBUG2("."); + } + if (i <= 0) { + printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", + dev->name, lp->cur_tx, status); + pkt_len = 0; + goto failure; + } + + /* + * Setup Tx ring. Caution: the write order is important here, + * set the status with the "ownership" bits last. + */ + status = 0x8300; + entry->length = le16_to_cpu(-pkt_len); + entry->misc = 0x00000000; + entry->base = PCI_TO_MEM_LE(dev, packet); + entry->status = le16_to_cpu(status); + + /* Trigger an immediate send poll. */ + pcnet_write_csr (dev, 0, 0x0008); + + failure: + if (++lp->cur_tx >= TX_RING_SIZE) + lp->cur_tx = 0; + + PCNET_DEBUG2("done\n"); + return pkt_len; +} + +static int pcnet_recv(struct eth_device* dev) +{ + struct pcnet_rx_head *entry; + int pkt_len = 0; + u16 status; + + while (1) { + entry = &lp->rx_ring[lp->cur_rx]; + /* + * If we own the next entry, it's a new packet. Send it up. + */ + if (((status = le16_to_cpu(entry->status)) & 0x8000) != 0) { + break; + } + status >>= 8; + + if (status != 0x03) { /* There was an error. */ + + printf("%s: Rx%d", dev->name, lp->cur_rx); + PCNET_DEBUG1(" (status=0x%x)", status); + if (status & 0x20) printf(" Frame"); + if (status & 0x10) printf(" Overflow"); + if (status & 0x08) printf(" CRC"); + if (status & 0x04) printf(" Fifo"); + printf(" Error\n"); + entry->status &= le16_to_cpu(0x03ff); + + } else { + + pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4; + if (pkt_len < 60) { + printf("%s: Rx%d: invalid packet length %d\n", + dev->name, lp->cur_rx, pkt_len); + } else { + NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); + PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", + lp->cur_rx, pkt_len, lp->rx_buf[lp->cur_rx]); + } + } + entry->status |= cpu_to_le16(0x8000); + + if (++lp->cur_rx >= RX_RING_SIZE) + lp->cur_rx = 0; + } + return pkt_len; +} + +static void pcnet_halt(struct eth_device* dev) +{ + int i; + + PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); + + /* Reset the PCnet controller */ + pcnet_reset (dev); + + /* Wait for Stop bit */ + for (i = 1000; i > 0; i--) { + if (pcnet_read_csr (dev, 0) & 0x4) + break; + udelay(10); + } + if (i <= 0) { + printf("%s: TIMEOUT: controller reset failed\n", dev->name); + } +} + +#endif diff --git a/drivers/plb2800_eth.c b/drivers/plb2800_eth.c new file mode 100644 index 0000000..4c683d7 --- /dev/null +++ b/drivers/plb2800_eth.c @@ -0,0 +1,396 @@ +/* + * PLB2800 internal switch ethernet driver. + * + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_PLB2800_ETHER) + +#include +#include +#include + + +#define NUM_RX_DESC PKTBUFSRX +#define TOUT_LOOP 1000000 + +#define LONG_REF(addr) (*((volatile unsigned long*)addr)) + +#define CMAC_CRX_CTRL LONG_REF(0xb800c870) +#define CMAC_CTX_CTRL LONG_REF(0xb800c874) +#define SYS_MAC_ADDR_0 LONG_REF(0xb800c878) +#define SYS_MAC_ADDR_1 LONG_REF(0xb800c87c) +#define MIPS_H_MASK LONG_REF(0xB800C810) + +#define MA_LEARN LONG_REF(0xb8008004) +#define DA_LOOKUP LONG_REF(0xb8008008) + +#define CMAC_CRX_CTRL_PD 0x00000001 +#define CMAC_CRX_CTRL_CG 0x00000002 +#define CMAC_CRX_CTRL_PL_SHIFT 2 +#define CMAC_CRIT 0x0 +#define CMAC_NON_CRIT 0x1 +#define MBOX_STAT_ID_SHF 28 +#define MBOX_STAT_CP 0x80000000 +#define MBOX_STAT_MB 0x00000001 +#define EN_MA_LEARN 0x02000000 +#define EN_DA_LKUP 0x01000000 +#define MA_DEST_SHF 11 +#define DA_DEST_SHF 11 +#define DA_STATE_SHF 19 +#define TSTAMP_MS 0x00000000 +#define SW_H_MBOX4_MASK 0x08000000 +#define SW_H_MBOX3_MASK 0x04000000 +#define SW_H_MBOX2_MASK 0x02000000 +#define SW_H_MBOX1_MASK 0x01000000 + +typedef volatile struct { + unsigned int stat; + unsigned int cmd; + unsigned int cnt; + unsigned int adr; +} mailbox_t; + +#define MBOX_REG(mb) ((mailbox_t*)(0xb800c830+(mb<<4))) + +typedef volatile struct { + unsigned int word0; + unsigned int word1; + unsigned int word2; +} mbhdr_t; + +#define MBOX_MEM(mb) ((void*)(0xb800a000+((3-mb)<<11))) + + +static int plb2800_eth_init(struct eth_device *dev, bd_t * bis); +static int plb2800_eth_send(struct eth_device *dev, volatile void *packet, + int length); +static int plb2800_eth_recv(struct eth_device *dev); +static void plb2800_eth_halt(struct eth_device *dev); + +static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr); +static unsigned char * plb2800_get_mac_addr(void); + +static int rx_new; +static int mac_addr_set = 0; + + +int plb2800_eth_initialize(bd_t * bis) +{ + struct eth_device *dev; + ulong temp; + +#ifdef DEBUG + printf("Entered plb2800_eth_initialize()\n"); +#endif + + if (!(dev = (struct eth_device *) malloc (sizeof *dev))) + { + printf("Failed to allocate memory\n"); + return 0; + } + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "PLB2800 Switch"); + dev->init = plb2800_eth_init; + dev->halt = plb2800_eth_halt; + dev->send = plb2800_eth_send; + dev->recv = plb2800_eth_recv; + + eth_register(dev); + + /* bug fix */ + *(ulong *)0xb800e800 = 0x838; + + /* Set MBOX ownership */ + temp = CMAC_CRIT << MBOX_STAT_ID_SHF; + MBOX_REG(0)->stat = temp; + MBOX_REG(1)->stat = temp; + + temp = CMAC_NON_CRIT << MBOX_STAT_ID_SHF; + MBOX_REG(2)->stat = temp; + MBOX_REG(3)->stat = temp; + + plb2800_set_mac_addr(dev, plb2800_get_mac_addr()); + + /* Disable all Mbox interrupt */ + temp = MIPS_H_MASK; + temp &= ~ (SW_H_MBOX1_MASK | SW_H_MBOX2_MASK | SW_H_MBOX3_MASK | SW_H_MBOX4_MASK) ; + MIPS_H_MASK = temp; + +#ifdef DEBUG + printf("Leaving plb2800_eth_initialize()\n"); +#endif + + return 1; +} + +static int plb2800_eth_init(struct eth_device *dev, bd_t * bis) +{ +#ifdef DEBUG + printf("Entering plb2800_eth_init()\n"); +#endif + + plb2800_set_mac_addr(dev, dev->enetaddr); + + rx_new = 0; + +#ifdef DEBUG + printf("Leaving plb2800_eth_init()\n"); +#endif + + return 0; +} + + +static int plb2800_eth_send(struct eth_device *dev, volatile void *packet, + int length) +{ + int i; + int res = -1; + u32 temp; + mailbox_t * mb = MBOX_REG(0); + char * mem = MBOX_MEM(0); + +#ifdef DEBUG + printf("Entered plb2800_eth_send()\n"); +#endif + + if (length <= 0) + { + printf ("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + if (length < 64) + { + length = 64; + } + + temp = CMAC_CRX_CTRL_CG | ((length + 4) << CMAC_CRX_CTRL_PL_SHIFT); + +#ifdef DEBUG + printf("0 mb->stat = 0x%x\n", mb->stat); +#endif + + for(i = 0; mb->stat & (MBOX_STAT_CP | MBOX_STAT_MB); i++) + { + if (i >= TOUT_LOOP) + { + printf("%s: tx buffer not ready\n", dev->name); + printf("1 mb->stat = 0x%x\n", mb->stat); + goto Done; + } + } + + /* For some strange reason, memcpy doesn't work, here! + */ + do + { + int words = (length >> 2) + 1; + unsigned int* dst = (unsigned int*)(mem); + unsigned int* src = (unsigned int*)(packet); + for (i = 0; i < words; i++) + { + *dst = *src; + dst++; + src++; + }; + } while(0); + + CMAC_CRX_CTRL = temp; + mb->cmd = MBOX_STAT_CP; + +#ifdef DEBUG + printf("2 mb->stat = 0x%x\n", mb->stat); +#endif + + res = length; +Done: + +#ifdef DEBUG + printf("Leaving plb2800_eth_send()\n"); +#endif + + return res; +} + + +static int plb2800_eth_recv(struct eth_device *dev) +{ + int length = 0; + mailbox_t * mbox = MBOX_REG(3); + unsigned char * hdr = MBOX_MEM(3); + unsigned int stat; + +#ifdef DEBUG + printf("Entered plb2800_eth_recv()\n"); +#endif + + for (;;) + { + stat = mbox->stat; + + if (!(stat & MBOX_STAT_CP)) + { + break; + } + + length = ((*(hdr + 6) & 0x3f) << 8) + *(hdr + 7); + memcpy((void *)NetRxPackets[rx_new], hdr + 12, length); + + stat &= ~MBOX_STAT_CP; + mbox->stat = stat; +#ifdef DEBUG + { + int i; + for (i=0;i + +#ifdef CONFIG_PS2MULT + +#include +#include +#include + +/* #define DEBUG_MULT */ +/* #define DEBUG_KEYB */ + +#define KBD_STAT_DEFAULT (KBD_STAT_SELFTEST | KBD_STAT_UNLOCKED) + +#define PRINTF(format, args...) printf("ps2mult.c: " format, ## args) + +#ifdef DEBUG_MULT +#define PRINTF_MULT(format, args...) printf("PS2MULT: " format, ## args) +#else +#define PRINTF_MULT(format, args...) +#endif + +#ifdef DEBUG_KEYB +#define PRINTF_KEYB(format, args...) printf("KEYB: " format, ## args) +#else +#define PRINTF_KEYB(format, args...) +#endif + + +static ulong start_time; +static int init_done = 0; + +static int received_escape = 0; +static int received_bsync = 0; +static int received_selector = 0; + +static int kbd_command_active = 0; +static int mouse_command_active = 0; +static int ctl_command_active = 0; + +static u_char command_byte = 0; + +static void (*keyb_handler)(void *dev_id); + +static u_char ps2mult_buf [PS2BUF_SIZE]; +static atomic_t ps2mult_buf_cnt; +static int ps2mult_buf_in_idx; +static int ps2mult_buf_out_idx; + +static u_char ps2mult_buf_status [PS2BUF_SIZE]; + +#ifndef CONFIG_BOARD_EARLY_INIT_R +#error #define CONFIG_BOARD_EARLY_INIT_R and call ps2mult_early_init() in board_early_init_r() +#endif +void ps2mult_early_init (void) +{ + start_time = get_timer(0); +} + +static void ps2mult_send_byte(u_char byte, u_char sel) +{ + ps2ser_putc(sel); + + if (sel == PS2MULT_KB_SELECTOR) { + PRINTF_MULT("0x%02x send KEYBOARD\n", byte); + kbd_command_active = 1; + } else { + PRINTF_MULT("0x%02x send MOUSE\n", byte); + mouse_command_active = 1; + } + + switch (byte) { + case PS2MULT_ESCAPE: + case PS2MULT_BSYNC: + case PS2MULT_KB_SELECTOR: + case PS2MULT_MS_SELECTOR: + case PS2MULT_SESSION_START: + case PS2MULT_SESSION_END: + ps2ser_putc(PS2MULT_ESCAPE); + break; + default: + break; + } + + ps2ser_putc(byte); +} + +static void ps2mult_receive_byte(u_char byte, u_char sel) +{ + u_char status = KBD_STAT_DEFAULT; + +#if 1 /* Ignore mouse in U-Boot */ + if (sel == PS2MULT_MS_SELECTOR) return; +#endif + + if (sel == PS2MULT_KB_SELECTOR) { + if (kbd_command_active) { + if (!received_bsync) { + PRINTF_MULT("0x%02x lost KEYBOARD !!!\n", byte); + return; + } else { + kbd_command_active = 0; + received_bsync = 0; + } + } + PRINTF_MULT("0x%02x receive KEYBOARD\n", byte); + status |= KBD_STAT_IBF | KBD_STAT_OBF; + } else { + if (mouse_command_active) { + if (!received_bsync) { + PRINTF_MULT("0x%02x lost MOUSE !!!\n", byte); + return; + } else { + mouse_command_active = 0; + received_bsync = 0; + } + } + PRINTF_MULT("0x%02x receive MOUSE\n", byte); + status |= KBD_STAT_IBF | KBD_STAT_OBF | KBD_STAT_MOUSE_OBF; + } + + if (atomic_read(&ps2mult_buf_cnt) < PS2BUF_SIZE) { + ps2mult_buf_status[ps2mult_buf_in_idx] = status; + ps2mult_buf[ps2mult_buf_in_idx++] = byte; + ps2mult_buf_in_idx &= (PS2BUF_SIZE - 1); + atomic_inc(&ps2mult_buf_cnt); + } else { + PRINTF("buffer overflow\n"); + } + + if (received_bsync) { + PRINTF("unexpected BSYNC\n"); + received_bsync = 0; + } +} + +void ps2mult_callback (int in_cnt) +{ + int i; + u_char byte; + static int keyb_handler_active = 0; + + if (!init_done) { + return; + } + + for (i = 0; i < in_cnt; i ++) { + byte = ps2ser_getc(); + + if (received_escape) { + ps2mult_receive_byte(byte, received_selector); + received_escape = 0; + } else switch (byte) { + case PS2MULT_ESCAPE: + PRINTF_MULT("ESCAPE receive\n"); + received_escape = 1; + break; + + case PS2MULT_BSYNC: + PRINTF_MULT("BSYNC receive\n"); + received_bsync = 1; + break; + + case PS2MULT_KB_SELECTOR: + case PS2MULT_MS_SELECTOR: + PRINTF_MULT("%s receive\n", + byte == PS2MULT_KB_SELECTOR ? "KB_SEL" : "MS_SEL"); + received_selector = byte; + break; + + case PS2MULT_SESSION_START: + case PS2MULT_SESSION_END: + PRINTF_MULT("%s receive\n", + byte == PS2MULT_SESSION_START ? + "SESSION_START" : "SESSION_END"); + break; + + default: + ps2mult_receive_byte(byte, received_selector); + } + } + + if (keyb_handler && !keyb_handler_active && + atomic_read(&ps2mult_buf_cnt)) { + keyb_handler_active = 1; + keyb_handler(NULL); + keyb_handler_active = 0; + } +} + +u_char ps2mult_read_status(void) +{ + u_char byte; + + if (atomic_read(&ps2mult_buf_cnt) == 0) { + ps2ser_check(); + } + + if (atomic_read(&ps2mult_buf_cnt)) { + byte = ps2mult_buf_status[ps2mult_buf_out_idx]; + } else { + byte = KBD_STAT_DEFAULT; + } + PRINTF_KEYB("read_status()=0x%02x\n", byte); + return byte; +} + +u_char ps2mult_read_input(void) +{ + u_char byte = 0; + + if (atomic_read(&ps2mult_buf_cnt) == 0) { + ps2ser_check(); + } + + if (atomic_read(&ps2mult_buf_cnt)) { + byte = ps2mult_buf[ps2mult_buf_out_idx++]; + ps2mult_buf_out_idx &= (PS2BUF_SIZE - 1); + atomic_dec(&ps2mult_buf_cnt); + } + PRINTF_KEYB("read_input()=0x%02x\n", byte); + return byte; +} + +void ps2mult_write_output(u_char val) +{ + int i; + + PRINTF_KEYB("write_output(0x%02x)\n", val); + + for (i = 0; i < KBD_TIMEOUT; i++) { + if (!kbd_command_active && !mouse_command_active) { + break; + } + udelay(1000); + ps2ser_check(); + } + + if (kbd_command_active) { + PRINTF("keyboard command not acknoledged\n"); + kbd_command_active = 0; + } + + if (mouse_command_active) { + PRINTF("mouse command not acknoledged\n"); + mouse_command_active = 0; + } + + if (ctl_command_active) { + switch (ctl_command_active) { + case KBD_CCMD_WRITE_MODE: + /* Scan code conversion not supported */ + command_byte = val & ~KBD_MODE_KCC; + break; + + case KBD_CCMD_WRITE_AUX_OBUF: + ps2mult_receive_byte(val, PS2MULT_MS_SELECTOR); + break; + + case KBD_CCMD_WRITE_MOUSE: + ps2mult_send_byte(val, PS2MULT_MS_SELECTOR); + break; + + default: + PRINTF("invalid controller command\n"); + break; + } + + ctl_command_active = 0; + return; + } + + ps2mult_send_byte(val, PS2MULT_KB_SELECTOR); +} + +void ps2mult_write_command(u_char val) +{ + ctl_command_active = 0; + + PRINTF_KEYB("write_command(0x%02x)\n", val); + + switch (val) { + case KBD_CCMD_READ_MODE: + ps2mult_receive_byte(command_byte, PS2MULT_KB_SELECTOR); + break; + + case KBD_CCMD_WRITE_MODE: + ctl_command_active = val; + break; + + case KBD_CCMD_MOUSE_DISABLE: + break; + + case KBD_CCMD_MOUSE_ENABLE: + break; + + case KBD_CCMD_SELF_TEST: + ps2mult_receive_byte(0x55, PS2MULT_KB_SELECTOR); + break; + + case KBD_CCMD_KBD_TEST: + ps2mult_receive_byte(0x00, PS2MULT_KB_SELECTOR); + break; + + case KBD_CCMD_KBD_DISABLE: + break; + + case KBD_CCMD_KBD_ENABLE: + break; + + case KBD_CCMD_WRITE_AUX_OBUF: + ctl_command_active = val; + break; + + case KBD_CCMD_WRITE_MOUSE: + ctl_command_active = val; + break; + + default: + PRINTF("invalid controller command\n"); + break; + } +} + +static int ps2mult_getc_w (void) +{ + int res = -1; + int i; + + for (i = 0; i < KBD_TIMEOUT; i++) { + if (ps2ser_check()) { + res = ps2ser_getc(); + break; + } + udelay(1000); + } + + switch (res) { + case PS2MULT_KB_SELECTOR: + case PS2MULT_MS_SELECTOR: + received_selector = res; + break; + default: + break; + } + + return res; +} + +int ps2mult_init (void) +{ + int byte; + int kbd_found = 0; + int mouse_found = 0; + + while (get_timer(start_time) < CONFIG_PS2MULT_DELAY); + + ps2ser_init(); + + ps2ser_putc(PS2MULT_SESSION_START); + + ps2ser_putc(PS2MULT_KB_SELECTOR); + ps2ser_putc(KBD_CMD_RESET); + + do { + byte = ps2mult_getc_w(); + } while (byte >= 0 && byte != KBD_REPLY_ACK); + + if (byte == KBD_REPLY_ACK) { + byte = ps2mult_getc_w(); + if (byte == 0xaa) { + kbd_found = 1; + puts("keyboard"); + } + } + + if (!kbd_found) { + while (byte >= 0) { + byte = ps2mult_getc_w(); + } + } + +#if 1 /* detect mouse */ + ps2ser_putc(PS2MULT_MS_SELECTOR); + ps2ser_putc(AUX_RESET); + + do { + byte = ps2mult_getc_w(); + } while (byte >= 0 && byte != AUX_ACK); + + if (byte == AUX_ACK) { + byte = ps2mult_getc_w(); + if (byte == 0xaa) { + byte = ps2mult_getc_w(); + if (byte == 0x00) { + mouse_found = 1; + puts(", mouse"); + } + } + } + + if (!mouse_found) { + while (byte >= 0) { + byte = ps2mult_getc_w(); + } + } +#endif + + if (mouse_found || kbd_found) { + if (!received_selector) { + if (mouse_found) { + received_selector = PS2MULT_MS_SELECTOR; + } else { + received_selector = PS2MULT_KB_SELECTOR; + } + } + + init_done = 1; + } else { + puts("No device found"); + } + + puts("\n"); + +#if 0 /* for testing */ + { + int i; + u_char key[] = { + 0x1f, 0x12, 0x14, 0x12, 0x31, 0x2f, 0x39, /* setenv */ + 0x1f, 0x14, 0x20, 0x17, 0x31, 0x39, /* stdin */ + 0x1f, 0x12, 0x13, 0x17, 0x1e, 0x26, 0x1c, /* serial */ + }; + + for (i = 0; i < sizeof (key); i++) { + ps2mult_receive_byte (key[i], PS2MULT_KB_SELECTOR); + ps2mult_receive_byte (key[i] | 0x80, PS2MULT_KB_SELECTOR); + } + } +#endif + + return init_done ? 0 : -1; +} + +int ps2mult_request_irq(void (*handler)(void *)) +{ + keyb_handler = handler; + + return 0; +} + +#endif /* CONFIG_PS2MULT */ diff --git a/drivers/ps2ser.c b/drivers/ps2ser.c new file mode 100644 index 0000000..e2a38dc --- /dev/null +++ b/drivers/ps2ser.c @@ -0,0 +1,272 @@ +/*********************************************************************** + * + * (C) Copyright 2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * All rights reserved. + * + * Simple 16550A serial driver + * + * Originally from linux source (drivers/char/ps2ser.c) + * + * Used by the PS/2 multiplexer driver (ps2mult.c) + * + ***********************************************************************/ + +#include + +#ifdef CONFIG_PS2SERIAL + +#include +#include +#include + +/* #define DEBUG */ + +#define PS2SER_BAUD 57600 + +#ifdef CONFIG_MPC5xxx +#if CONFIG_PS2SERIAL == 1 +#define PSC_BASE MPC5XXX_PSC1 +#elif CONFIG_PS2SERIAL == 2 +#define PSC_BASE MPC5XXX_PSC2 +#elif CONFIG_PS2SERIAL == 3 +#define PSC_BASE MPC5XXX_PSC3 +#elif defined(CONFIG_MGT5100) +#error CONFIG_PS2SERIAL must be in 1, 2 or 3 +#elif CONFIG_PS2SERIAL == 4 +#define PSC_BASE MPC5XXX_PSC4 +#elif CONFIG_PS2SERIAL == 5 +#define PSC_BASE MPC5XXX_PSC5 +#elif CONFIG_PS2SERIAL == 6 +#define PSC_BASE MPC5XXX_PSC6 +#else +#error CONFIG_PS2SERIAL must be in 1 ... 6 +#endif +#endif /* CONFIG_MPC5xxx */ + +static int ps2ser_getc_hw(void); +static void ps2ser_interrupt(void *dev_id); + +extern struct serial_state rs_table[]; /* in serial.c */ +#ifndef CONFIG_MPC5xxx +static struct serial_state *state; +#endif + +static u_char ps2buf[PS2BUF_SIZE]; +static atomic_t ps2buf_cnt; +static int ps2buf_in_idx; +static int ps2buf_out_idx; + +#ifdef CONFIG_MPC5xxx +int ps2ser_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; + unsigned long baseclk; + int div; + + /* reset PSC */ + psc->command = PSC_SEL_MODE_REG_1; + + /* select clock sources */ +#if defined(CONFIG_MGT5100) + psc->psc_clock_select = 0xdd00; + baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; +#elif defined(CONFIG_MPC5200) + psc->psc_clock_select = 0; + baseclk = (gd->ipb_clk + 16) / 32; +#endif + + /* switch to UART mode */ + psc->sicr = 0; + + /* configure parity, bit length and so on */ +#if defined(CONFIG_MGT5100) + psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; +#elif defined(CONFIG_MPC5200) + psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; +#endif + psc->mode = PSC_MODE_ONE_STOP; + + /* set up UART divisor */ + div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD; + psc->ctur = (div >> 8) & 0xff; + psc->ctlr = div & 0xff; + + /* disable all interrupts */ + psc->psc_imr = 0; + + /* reset and enable Rx/Tx */ + psc->command = PSC_RST_RX; + psc->command = PSC_RST_TX; + psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; + + return (0); +} + +#else /* !CONFIG_MPC5xxx */ + +static inline unsigned int ps2ser_in(int offset) +{ + return readb((unsigned long) state->iomem_base + offset); +} + +static inline void ps2ser_out(int offset, int value) +{ + writeb(value, (unsigned long) state->iomem_base + offset); +} + +int ps2ser_init(void) +{ + int quot; + unsigned cval; + + state = rs_table + CONFIG_PS2SERIAL; + + quot = state->baud_base / PS2SER_BAUD; + cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */ + + /* Set speed, enable interrupts, enable FIFO + */ + ps2ser_out(UART_LCR, cval | UART_LCR_DLAB); + ps2ser_out(UART_DLL, quot & 0xff); + ps2ser_out(UART_DLM, quot >> 8); + ps2ser_out(UART_LCR, cval); + ps2ser_out(UART_IER, UART_IER_RDI); + ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS); + ps2ser_out(UART_FCR, + UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + + /* If we read 0xff from the LSR, there is no UART here + */ + if (ps2ser_in(UART_LSR) == 0xff) { + printf ("ps2ser.c: no UART found\n"); + return -1; + } + + irq_install_handler(state->irq, ps2ser_interrupt, NULL); + + return 0; +} +#endif /* CONFIG_MPC5xxx */ + +void ps2ser_putc(int chr) +{ +#ifdef CONFIG_MPC5xxx + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif +#ifdef DEBUG + printf(">>>> 0x%02x\n", chr); +#endif + +#ifdef CONFIG_MPC5xxx + while (!(psc->psc_status & PSC_SR_TXRDY)); + + psc->psc_buffer_8 = chr; +#else + while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE)); + + ps2ser_out(UART_TX, chr); +#endif +} + +static int ps2ser_getc_hw(void) +{ +#ifdef CONFIG_MPC5xxx + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + int res = -1; + +#ifdef CONFIG_MPC5xxx + if (psc->psc_status & PSC_SR_RXRDY) { + res = (psc->psc_buffer_8); + } +#else + if (ps2ser_in(UART_LSR) & UART_LSR_DR) { + res = (ps2ser_in(UART_RX)); + } +#endif + + return res; +} + +int ps2ser_getc(void) +{ + volatile int chr; + int flags; + +#ifdef DEBUG + printf("<< "); +#endif + + flags = disable_interrupts(); + + do { + if (atomic_read(&ps2buf_cnt) != 0) { + chr = ps2buf[ps2buf_out_idx++]; + ps2buf_out_idx &= (PS2BUF_SIZE - 1); + atomic_dec(&ps2buf_cnt); + } else { + chr = ps2ser_getc_hw(); + } + } + while (chr < 0); + + if (flags) enable_interrupts(); + +#ifdef DEBUG + printf("0x%02x\n", chr); +#endif + + return chr; +} + +int ps2ser_check(void) +{ + int flags; + + flags = disable_interrupts(); + ps2ser_interrupt(NULL); + if (flags) enable_interrupts(); + + return atomic_read(&ps2buf_cnt); +} + +static void ps2ser_interrupt(void *dev_id) +{ +#ifdef CONFIG_MPC5xxx + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + int chr; + int status; + + do { + chr = ps2ser_getc_hw(); +#ifdef CONFIG_MPC5xxx + status = psc->psc_status; +#else + status = ps2ser_in(UART_IIR); +#endif + if (chr < 0) continue; + + if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) { + ps2buf[ps2buf_in_idx++] = chr; + ps2buf_in_idx &= (PS2BUF_SIZE - 1); + atomic_inc(&ps2buf_cnt); + } else { + printf ("ps2ser.c: buffer overflow\n"); + } +#ifdef CONFIG_MPC5xxx + } while (status & PSC_SR_RXRDY); +#else + } while (status & UART_IIR_RDI); +#endif + + if (atomic_read(&ps2buf_cnt)) { + ps2mult_callback(atomic_read(&ps2buf_cnt)); + } +} + +#endif /* CONFIG_PS2SERIAL */ diff --git a/drivers/rtl8019.c b/drivers/rtl8019.c new file mode 100644 index 0000000..62b9245 --- /dev/null +++ b/drivers/rtl8019.c @@ -0,0 +1,282 @@ +/* + * Realtek 8019AS Ethernet + * (C) Copyright 2002-2003 + * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This code works in 8bit mode. + * If you need to work in 16bit mode, PLS change it! + */ + +#include +#include +#include "rtl8019.h" +#include + +#ifdef CONFIG_DRIVER_RTL8019 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + + +/* packet page register access functions */ + + +static unsigned char get_reg (unsigned int regno) +{ + return (*(unsigned char *) regno); +} + + +static void put_reg (unsigned int regno, unsigned char val) +{ + *(volatile unsigned char *) regno = val; +} + +static void eth_reset (void) +{ + unsigned char ucTemp; + + /* reset NIC */ + ucTemp = get_reg (RTL8019_RESET); + put_reg (RTL8019_RESET, ucTemp); + put_reg (RTL8019_INTERRUPTSTATUS, 0xff); + udelay (2000); /* wait for 2ms */ +} + +void rtl8019_get_enetaddr (uchar * addr) +{ + unsigned char i; + unsigned char temp; + + eth_reset (); + + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD); + put_reg (RTL8019_DATACONFIGURATION, 0x48); + put_reg (RTL8019_REMOTESTARTADDRESS0, 0x00); + put_reg (RTL8019_REMOTESTARTADDRESS1, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT0, 12); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD); + printf ("MAC: "); + for (i = 0; i < 6; i++) { + temp = get_reg (RTL8019_DMA_DATA); + *addr++ = temp; + temp = get_reg (RTL8019_DMA_DATA); + printf ("%x:", temp); + } + + while ((!get_reg (RTL8019_INTERRUPTSTATUS) & 0x40)); + printf ("\b \n"); + put_reg (RTL8019_REMOTEBYTECOUNT0, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); +} + + +void eth_halt (void) +{ + put_reg (RTL8019_COMMAND, 0x01); +} + +int eth_init (bd_t * bd) +{ + eth_reset (); + put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP); + put_reg (RTL8019_DATACONFIGURATION, 0x48); + put_reg (RTL8019_REMOTEBYTECOUNT0, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8019_RECEIVECONFIGURATION, 0x00); /*00; */ + put_reg (RTL8019_TRANSMITPAGE, RTL8019_TPSTART); + put_reg (RTL8019_TRANSMITCONFIGURATION, 0x02); + put_reg (RTL8019_PAGESTART, RTL8019_PSTART); + put_reg (RTL8019_BOUNDARY, RTL8019_PSTART); + put_reg (RTL8019_PAGESTOP, RTL8019_PSTOP); + put_reg (RTL8019_INTERRUPTSTATUS, 0xff); + put_reg (RTL8019_INTERRUPTMASK, 0x11); /*b; */ + put_reg (RTL8019_COMMAND, RTL8019_PAGE1STOP); + put_reg (RTL8019_PHYSICALADDRESS0, bd->bi_enetaddr[0]); + put_reg (RTL8019_PHYSICALADDRESS1, bd->bi_enetaddr[1]); + put_reg (RTL8019_PHYSICALADDRESS2, bd->bi_enetaddr[2]); + put_reg (RTL8019_PHYSICALADDRESS3, bd->bi_enetaddr[3]); + put_reg (RTL8019_PHYSICALADDRESS4, bd->bi_enetaddr[4]); + put_reg (RTL8019_PHYSICALADDRESS5, bd->bi_enetaddr[5]); + put_reg (RTL8019_MULTIADDRESS0, 0x00); + put_reg (RTL8019_MULTIADDRESS1, 0x00); + put_reg (RTL8019_MULTIADDRESS2, 0x00); + put_reg (RTL8019_MULTIADDRESS3, 0x00); + put_reg (RTL8019_MULTIADDRESS4, 0x00); + put_reg (RTL8019_MULTIADDRESS5, 0x00); + put_reg (RTL8019_MULTIADDRESS6, 0x00); + put_reg (RTL8019_MULTIADDRESS7, 0x00); + put_reg (RTL8019_CURRENT, RTL8019_PSTART); + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); + put_reg (RTL8019_TRANSMITCONFIGURATION, 0xe0); /*58; */ + + return 0; +} + + +static unsigned char nic_to_pc (void) +{ + unsigned char rec_head_status; + unsigned char next_packet_pointer; + unsigned char packet_length0; + unsigned char packet_length1; + unsigned short rxlen = 0; + unsigned int i = 4; + unsigned char current_point; + unsigned char *addr; + + /* + * The RTL8019's first 4B is packet status,page of next packet + * and packet length(2B).So we receive the fist 4B. + */ + put_reg (RTL8019_REMOTESTARTADDRESS1, get_reg (RTL8019_BOUNDARY)); + put_reg (RTL8019_REMOTESTARTADDRESS0, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT0, 0x04); + + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD); + + rec_head_status = get_reg (RTL8019_DMA_DATA); + next_packet_pointer = get_reg (RTL8019_DMA_DATA); + packet_length0 = get_reg (RTL8019_DMA_DATA); + packet_length1 = get_reg (RTL8019_DMA_DATA); + + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); + /*Packet length is in two 8bit registers */ + rxlen = packet_length1; + rxlen = (((rxlen << 8) & 0xff00) + packet_length0); + rxlen -= 4; + + if (rxlen > PKTSIZE_ALIGN + PKTALIGN) + printf ("packet too big!\n"); + + /*Receive the packet */ + put_reg (RTL8019_REMOTESTARTADDRESS0, 0x04); + put_reg (RTL8019_REMOTESTARTADDRESS1, get_reg (RTL8019_BOUNDARY)); + + put_reg (RTL8019_REMOTEBYTECOUNT0, (rxlen & 0xff)); + put_reg (RTL8019_REMOTEBYTECOUNT1, ((rxlen >> 8) & 0xff)); + + + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD); + + for (addr = (unsigned char *) NetRxPackets[0], i = rxlen; i > 0; i--) + *addr++ = get_reg (RTL8019_DMA_DATA); + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], rxlen); + + while (!(get_reg (RTL8019_INTERRUPTSTATUS)) & 0x40); /* wait for the op. */ + + /* + * To test whether the packets are all received,get the + * location of current point + */ + put_reg (RTL8019_COMMAND, RTL8019_PAGE1); + current_point = get_reg (RTL8019_CURRENT); + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); + put_reg (RTL8019_BOUNDARY, next_packet_pointer); + return current_point; +} + +/* Get a data block via Ethernet */ +extern int eth_rx (void) +{ + unsigned char temp, current_point; + + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); + + while (1) { + temp = get_reg (RTL8019_INTERRUPTSTATUS); + + if (temp & 0x90) { + /*overflow */ + put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP); + udelay (2000); + put_reg (RTL8019_REMOTEBYTECOUNT0, 0); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0); + put_reg (RTL8019_TRANSMITCONFIGURATION, 2); + do { + current_point = nic_to_pc (); + } while (get_reg (RTL8019_BOUNDARY) != current_point); + + put_reg (RTL8019_TRANSMITCONFIGURATION, 0xe0); + } + + if (temp & 0x1) { + /*packet received */ + do { + put_reg (RTL8019_INTERRUPTSTATUS, 0x01); + current_point = nic_to_pc (); + } while (get_reg (RTL8019_BOUNDARY) != current_point); + } + + if (!(temp & 0x1)) + return 0; + /* done and exit. */ + } +} + +/* Send a data block via Ethernet. */ +extern int eth_send (volatile void *packet, int length) +{ + volatile unsigned char *p; + unsigned int pn; + + pn = length; + p = (volatile unsigned char *) packet; + + while (get_reg (RTL8019_COMMAND) == RTL8019_TRANSMIT); + + put_reg (RTL8019_REMOTESTARTADDRESS0, 0); + put_reg (RTL8019_REMOTESTARTADDRESS1, RTL8019_TPSTART); + put_reg (RTL8019_REMOTEBYTECOUNT0, (pn & 0xff)); + put_reg (RTL8019_REMOTEBYTECOUNT1, ((pn >> 8) & 0xff)); + + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMAWR); + while (pn > 0) { + put_reg (RTL8019_DMA_DATA, *p++); + pn--; + } + + pn = length; + + while (pn < 60) { /*Padding */ + put_reg (RTL8019_DMA_DATA, 0); + pn++; + } + + while (!(get_reg (RTL8019_INTERRUPTSTATUS)) & 0x40); + + put_reg (RTL8019_INTERRUPTSTATUS, 0x40); + put_reg (RTL8019_TRANSMITPAGE, RTL8019_TPSTART); + put_reg (RTL8019_TRANSMITBYTECOUNT0, (pn & 0xff)); + put_reg (RTL8019_TRANSMITBYTECOUNT1, ((pn >> 8 & 0xff))); + put_reg (RTL8019_COMMAND, RTL8019_TRANSMIT); + + return 0; +} + +#endif /* COMMANDS & CFG_NET */ + +#endif /* CONFIG_DRIVER_RTL8019 */ diff --git a/drivers/rtl8019.h b/drivers/rtl8019.h new file mode 100644 index 0000000..38116ad --- /dev/null +++ b/drivers/rtl8019.h @@ -0,0 +1,117 @@ +/* + * Realtek 8019AS Ethernet + * (C) Copyright 2002-2003 + * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This code works in 8bit mode. + * If you need to work in 16bit mode, PLS change it! + */ + +#include +#include + + +#ifdef CONFIG_DRIVER_RTL8019 + +#define RTL8019_REG_00 (RTL8019_BASE + 0x00) +#define RTL8019_REG_01 (RTL8019_BASE + 0x01) +#define RTL8019_REG_02 (RTL8019_BASE + 0x02) +#define RTL8019_REG_03 (RTL8019_BASE + 0x03) +#define RTL8019_REG_04 (RTL8019_BASE + 0x04) +#define RTL8019_REG_05 (RTL8019_BASE + 0x05) +#define RTL8019_REG_06 (RTL8019_BASE + 0x06) +#define RTL8019_REG_07 (RTL8019_BASE + 0x07) +#define RTL8019_REG_08 (RTL8019_BASE + 0x08) +#define RTL8019_REG_09 (RTL8019_BASE + 0x09) +#define RTL8019_REG_0a (RTL8019_BASE + 0x0a) +#define RTL8019_REG_0b (RTL8019_BASE + 0x0b) +#define RTL8019_REG_0c (RTL8019_BASE + 0x0c) +#define RTL8019_REG_0d (RTL8019_BASE + 0x0d) +#define RTL8019_REG_0e (RTL8019_BASE + 0x0e) +#define RTL8019_REG_0f (RTL8019_BASE + 0x0f) +#define RTL8019_REG_10 (RTL8019_BASE + 0x10) +#define RTL8019_REG_1f (RTL8019_BASE + 0x1f) + +#define RTL8019_COMMAND RTL8019_REG_00 +#define RTL8019_PAGESTART RTL8019_REG_01 +#define RTL8019_PAGESTOP RTL8019_REG_02 +#define RTL8019_BOUNDARY RTL8019_REG_03 +#define RTL8019_TRANSMITSTATUS RTL8019_REG_04 +#define RTL8019_TRANSMITPAGE RTL8019_REG_04 +#define RTL8019_TRANSMITBYTECOUNT0 RTL8019_REG_05 +#define RTL8019_NCR RTL8019_REG_05 +#define RTL8019_TRANSMITBYTECOUNT1 RTL8019_REG_06 +#define RTL8019_INTERRUPTSTATUS RTL8019_REG_07 +#define RTL8019_CURRENT RTL8019_REG_07 +#define RTL8019_REMOTESTARTADDRESS0 RTL8019_REG_08 +#define RTL8019_CRDMA0 RTL8019_REG_08 +#define RTL8019_REMOTESTARTADDRESS1 RTL8019_REG_09 +#define RTL8019_CRDMA1 RTL8019_REG_09 +#define RTL8019_REMOTEBYTECOUNT0 RTL8019_REG_0a +#define RTL8019_REMOTEBYTECOUNT1 RTL8019_REG_0b +#define RTL8019_RECEIVESTATUS RTL8019_REG_0c +#define RTL8019_RECEIVECONFIGURATION RTL8019_REG_0c +#define RTL8019_TRANSMITCONFIGURATION RTL8019_REG_0d +#define RTL8019_FAE_TALLY RTL8019_REG_0d +#define RTL8019_DATACONFIGURATION RTL8019_REG_0e +#define RTL8019_CRC_TALLY RTL8019_REG_0e +#define RTL8019_INTERRUPTMASK RTL8019_REG_0f +#define RTL8019_MISS_PKT_TALLY RTL8019_REG_0f +#define RTL8019_PHYSICALADDRESS0 RTL8019_REG_01 +#define RTL8019_PHYSICALADDRESS1 RTL8019_REG_02 +#define RTL8019_PHYSICALADDRESS2 RTL8019_REG_03 +#define RTL8019_PHYSICALADDRESS3 RTL8019_REG_04 +#define RTL8019_PHYSICALADDRESS4 RTL8019_REG_05 +#define RTL8019_PHYSICALADDRESS5 RTL8019_REG_06 +#define RTL8019_MULTIADDRESS0 RTL8019_REG_08 +#define RTL8019_MULTIADDRESS1 RTL8019_REG_09 +#define RTL8019_MULTIADDRESS2 RTL8019_REG_0a +#define RTL8019_MULTIADDRESS3 RTL8019_REG_0b +#define RTL8019_MULTIADDRESS4 RTL8019_REG_0c +#define RTL8019_MULTIADDRESS5 RTL8019_REG_0d +#define RTL8019_MULTIADDRESS6 RTL8019_REG_0e +#define RTL8019_MULTIADDRESS7 RTL8019_REG_0f +#define RTL8019_DMA_DATA RTL8019_REG_10 +#define RTL8019_RESET RTL8019_REG_1f + + +#define RTL8019_PAGE0 0x22 +#define RTL8019_PAGE1 0x62 +#define RTL8019_PAGE0DMAWRITE 0x12 +#define RTL8019_PAGE2DMAWRITE 0x92 +#define RTL8019_REMOTEDMAWR 0x12 +#define RTL8019_REMOTEDMARD 0x0A +#define RTL8019_ABORTDMAWR 0x32 +#define RTL8019_ABORTDMARD 0x2A +#define RTL8019_PAGE0STOP 0x21 +#define RTL8019_PAGE1STOP 0x61 +#define RTL8019_TRANSMIT 0x26 +#define RTL8019_TXINPROGRESS 0x04 +#define RTL8019_SEND 0x1A + +#define RTL8019_PSTART 0x4c +#define RTL8019_PSTOP 0x80 +#define RTL8019_TPSTART 0x40 + + +#endif /*end of CONFIG_DRIVER_RTL8019*/ diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c new file mode 100644 index 0000000..a95f84e --- /dev/null +++ b/drivers/rtl8139.c @@ -0,0 +1,537 @@ +/* + * rtl8139.c : U-Boot driver for the RealTek RTL8139 + * + * Masami Komiya (mkomiya@sonare.it) + * + * Most part is taken from rtl8139.c of etherboot + * + */ + +/* rtl8139.c - etherboot driver for the Realtek 8139 chipset + + ported from the linux driver written by Donald Becker + by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 + + This software may be used and distributed according to the terms + of the GNU Public License, incorporated herein by reference. + + changes to the original driver: + - removed support for interrupts, switching to polling mode (yuck!) + - removed support for the 8129 chip (external MII) + +*/ + +/*********************************************************************/ +/* Revision History */ +/*********************************************************************/ + +/* + 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) + Put in virt_to_bus calls to allow Etherboot relocation. + + 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) + Following email from Hyun-Joon Cha, added a disable routine, otherwise + NIC remains live and can crash the kernel later. + + 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) + Shuffled things around, removed the leftovers from the 8129 support + that was in the Linux driver and added a bit more 8139 definitions. + Moved the 8K receive buffer to a fixed, available address outside the + 0x98000-0x9ffff range. This is a bit of a hack, but currently the only + way to make room for the Etherboot features that need substantial amounts + of code like the ANSI console support. Currently the buffer is just below + 0x10000, so this even conforms to the tagged boot image specification, + which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My + interpretation of this "reserved" is that Etherboot may do whatever it + likes, as long as its environment is kept intact (like the BIOS + variables). Hopefully fixed rtl_poll() once and for all. The symptoms + were that if Etherboot was left at the boot menu for several minutes, the + first eth_poll failed. Seems like I am the only person who does this. + First of all I fixed the debugging code and then set out for a long bug + hunting session. It took me about a week full time work - poking around + various places in the driver, reading Don Becker's and Jeff Garzik's Linux + driver and even the FreeBSD driver (what a piece of crap!) - and + eventually spotted the nasty thing: the transmit routine was acknowledging + each and every interrupt pending, including the RxOverrun and RxFIFIOver + interrupts. This confused the RTL8139 thoroughly. It destroyed the + Rx ring contents by dumping the 2K FIFO contents right where we wanted to + get the next packet. Oh well, what fun. + + 18 Jan 2000 mdc@thinguin.org (Marty Connor) + Drastically simplified error handling. Basically, if any error + in transmission or reception occurs, the card is reset. + Also, pointed all transmit descriptors to the same buffer to + save buffer space. This should decrease driver size and avoid + corruption because of exceeding 32K during runtime. + + 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) + rtl_poll was quite broken: it used the RxOK interrupt flag instead + of the RxBufferEmpty flag which often resulted in very bad + transmission performace - below 1kBytes/s. + +*/ + +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_RTL8139) + +#define TICKS_PER_SEC CFG_HZ +#define TICKS_PER_MS (TICKS_PER_SEC/1000) + +#define RTL_TIMEOUT (1*TICKS_PER_SEC) + +#define ETH_FRAME_LEN 1514 +#define ETH_ALEN 6 +#define ETH_ZLEN 60 + +/* PCI Tuning Parameters + Threshold is bytes transferred to chip before transmission starts. */ +#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ +#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ +#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ +#define TX_DMA_BURST 4 /* Calculate as 16<priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +/* Symbolic offsets to registers. */ +enum RTL8139_registers { + MAC0=0, /* Ethernet hardware address. */ + MAR0=8, /* Multicast filter. */ + TxStatus0=0x10, /* Transmit status (four 32bit registers). */ + TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ + RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, + ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, + IntrMask=0x3C, IntrStatus=0x3E, + TxConfig=0x40, RxConfig=0x44, + Timer=0x48, /* general-purpose counter. */ + RxMissed=0x4C, /* 24 bits valid, write clears. */ + Cfg9346=0x50, Config0=0x51, Config1=0x52, + TimerIntrReg=0x54, /* intr if gp counter reaches this value */ + MediaStatus=0x58, + Config3=0x59, + MultiIntr=0x5C, + RevisionID=0x5E, /* revision of the RTL8139 chip */ + TxSummary=0x60, + MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, + NWayExpansion=0x6A, + DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, + NWayTestReg=0x70, + RxCnt=0x72, /* packet received counter */ + CSCR=0x74, /* chip status and configuration register */ + PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ + /* from 0x84 onwards are a number of power management/wakeup frame + * definitions we will probably never need to know about. */ +}; + +enum ChipCmdBits { + CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; + +/* Interrupt register bits, using my own meaningful names. */ +enum IntrStatusBits { + PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, + RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, + TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, +}; +enum TxStatusBits { + TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, + TxOutOfWindow=0x20000000, TxAborted=0x40000000, + TxCarrierLost=0x80000000, +}; +enum RxStatusBits { + RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, + RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, + RxBadAlign=0x0002, RxStatusOK=0x0001, +}; + +enum MediaStatusBits { + MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, + MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, +}; + +enum MIIBMCRBits { + BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, + BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, +}; + +enum CSCRBits { + CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, + CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, + CSCR_LinkDownCmd=0x0f3c0, +}; + +/* Bits in RxConfig. */ +enum rx_mode_bits { + RxCfgWrap=0x80, + AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, + AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, +}; + +static int ioaddr; +static unsigned int cur_rx,cur_tx; + +/* The RTL8139 can only transmit from a contiguous, aligned memory block. */ +static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4))); +static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); + +static int rtl8139_probe(struct eth_device *dev, bd_t *bis); +static int read_eeprom(int location, int addr_len); +static void rtl_reset(struct eth_device *dev); +static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length); +static int rtl_poll(struct eth_device *dev); +static void rtl_disable(struct eth_device *dev); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, + {} +}; + +int rtl8139_initialize(bd_t *bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase; + int idx=0; + + while(1){ + /* Find RTL8139 */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0xf; + + debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); + + dev = (struct eth_device *)malloc(sizeof *dev); + + sprintf (dev->name, "RTL8139#%d", card_number); + + dev->priv = (void *) devno; + dev->iobase = (int)bus_to_phys(iobase); + dev->init = rtl8139_probe; + dev->halt = rtl_disable; + dev->send = rtl_transmit; + dev->recv = rtl_poll; + + eth_register (dev); + + card_number++; + + pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); + + udelay (10 * 1000); + } + + return card_number; +} + +static int rtl8139_probe(struct eth_device *dev, bd_t *bis) +{ + int i; + int speed10, fullduplex; + int addr_len; + unsigned short *ap = (unsigned short *)dev->enetaddr; + + ioaddr = dev->iobase; + + /* Bring the chip out of low-power mode. */ + outb(0x00, ioaddr + Config1); + + addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6; + for (i = 0; i < 3; i++) + *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len)); + + speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10; + fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex; + + rtl_reset(dev); + + if (inb(ioaddr + MediaStatus) & MSRLinkFail) { + printf("Cable not connected or other link failure\n"); + return(0); + } + + return 1; +} + +/* Serial EEPROM section. */ + +/* EEPROM_Ctrl bits. */ +#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ +#define EE_CS 0x08 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x00 +#define EE_WRITE_1 0x02 +#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ +#define EE_ENB (0x80 | EE_CS) + +/* + Delay between EEPROM clock transitions. + No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. +*/ + +#define eeprom_delay() inl(ee_addr) + +/* The EEPROM commands include the alway-set leading bit. */ +#define EE_WRITE_CMD (5) +#define EE_READ_CMD (6) +#define EE_ERASE_CMD (7) + +static int read_eeprom(int location, int addr_len) +{ + int i; + unsigned int retval = 0; + long ee_addr = ioaddr + Cfg9346; + int read_cmd = location | (EE_READ_CMD << addr_len); + + outb(EE_ENB & ~EE_CS, ee_addr); + outb(EE_ENB, ee_addr); + eeprom_delay(); + + /* Shift the read command bits out. */ + for (i = 4 + addr_len; i >= 0; i--) { + int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + outb(EE_ENB | dataval, ee_addr); + eeprom_delay(); + outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + } + outb(EE_ENB, ee_addr); + eeprom_delay(); + + for (i = 16; i > 0; i--) { + outb(EE_ENB | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); + outb(EE_ENB, ee_addr); + eeprom_delay(); + } + + /* Terminate the EEPROM access. */ + outb(~EE_CS, ee_addr); + eeprom_delay(); + return retval; +} + +static const unsigned int rtl8139_rx_config = + (RX_BUF_LEN_IDX << 11) | + (RX_FIFO_THRESH << 13) | + (RX_DMA_BURST << 8); + +static void set_rx_mode(struct eth_device *dev) { + unsigned int mc_filter[2]; + int rx_mode; + /* !IFF_PROMISC */ + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + mc_filter[1] = mc_filter[0] = 0xffffffff; + + outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig); + + outl(mc_filter[0], ioaddr + MAR0 + 0); + outl(mc_filter[1], ioaddr + MAR0 + 4); +} + +static void rtl_reset(struct eth_device *dev) +{ + int i; + + outb(CmdReset, ioaddr + ChipCmd); + + cur_rx = 0; + cur_tx = 0; + + /* Give the chip 10ms to finish the reset. */ + for (i=0; i<100; ++i){ + if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + udelay (100); /* wait 100us */ + } + + + for (i = 0; i < ETH_ALEN; i++) + outb(dev->enetaddr[i], ioaddr + MAC0 + i); + + /* Must enable Tx/Rx before setting transfer thresholds! */ + outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), + ioaddr + RxConfig); /* accept no frames yet! */ + outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig); + + /* The Linux driver changes Config1 here to use a different LED pattern + * for half duplex or full/autodetect duplex (for full/autodetect, the + * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses + * TX/RX, Link100, Link10). This is messy, because it doesn't match + * the inscription on the mounting bracket. It should not be changed + * from the configuration EEPROM default, because the card manufacturer + * should have set that to match the card. */ + +#ifdef DEBUG_RX + printf("rx ring address is %X\n",(unsigned long)rx_ring); +#endif + outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf); + + /* If we add multicast support, the MAR0 register would have to be + * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot + * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ + + outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + + outl(rtl8139_rx_config, ioaddr + RxConfig); + + /* Start the chip's Tx and Rx process. */ + outl(0, ioaddr + RxMissed); + + /* set_rx_mode */ + set_rx_mode(dev); + + /* Disable all known interrupts by setting the interrupt mask. */ + outw(0, ioaddr + IntrMask); +} + +static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length) +{ + unsigned int status, to; + unsigned long txstatus; + unsigned int len = length; + + ioaddr = dev->iobase; + + memcpy((char *)tx_buffer, (char *)packet, (int)length); + +#ifdef DEBUG_TX + printf("sending %d bytes\n", len); +#endif + + /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 + * bytes are sent automatically for the FCS, totalling to 64 bytes). */ + while (len < ETH_ZLEN) { + tx_buffer[len++] = '\0'; + } + + outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4); + outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, + ioaddr + TxStatus0 + cur_tx*4); + + to = currticks() + RTL_TIMEOUT; + + do { + status = inw(ioaddr + IntrStatus); + /* Only acknlowledge interrupt sources we can properly handle + * here - the RxOverflow/RxFIFOOver MUST be handled in the + * rtl_poll() function. */ + outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); + if ((status & (TxOK | TxErr | PCIErr)) != 0) break; + } while (currticks() < to); + + txstatus = inl(ioaddr + TxStatus0 + cur_tx*4); + + if (status & TxOK) { + cur_tx = (cur_tx + 1) % NUM_TX_DESC; +#ifdef DEBUG_TX + printf("tx done (%d ticks), status %hX txstatus %X\n", + to-currticks(), status, txstatus); +#endif + return length; + } else { +#ifdef DEBUG_TX + printf("tx timeout/error (%d ticks), status %hX txstatus %X\n", + currticks()-to, status, txstatus); +#endif + rtl_reset(dev); + + return 0; + } +} + +static int rtl_poll(struct eth_device *dev) +{ + unsigned int status; + unsigned int ring_offs; + unsigned int rx_size, rx_status; + int length=0; + + ioaddr = dev->iobase; + + if (inb(ioaddr + ChipCmd) & RxBufEmpty) { + return 0; + } + + status = inw(ioaddr + IntrStatus); + /* See below for the rest of the interrupt acknowledges. */ + outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + +#ifdef DEBUG_RX + printf("rtl_poll: int %hX ", status); +#endif + + ring_offs = cur_rx % RX_BUF_LEN; + rx_status = *(unsigned int*)KSEG1ADDR((rx_ring + ring_offs)); + rx_size = rx_status >> 16; + rx_status &= 0xffff; + + if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || + (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { + printf("rx error %hX\n", rx_status); + rtl_reset(dev); /* this clears all interrupts still pending */ + return 0; + } + + /* Received a good packet */ + length = rx_size - 4; /* no one cares about the FCS */ + if (ring_offs+4+rx_size-4 > RX_BUF_LEN) { + int semi_count = RX_BUF_LEN - ring_offs - 4; + unsigned char rxdata[RX_BUF_LEN]; + + memcpy(rxdata, rx_ring + ring_offs + 4, semi_count); + memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count); + + NetReceive(rxdata, length); +#ifdef DEBUG_RX + printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count); +#endif + } else { + NetReceive(rx_ring + ring_offs + 4, length); +#ifdef DEBUG_RX + printf("rx packet %d bytes", rx_size-4); +#endif + } + + cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; + outw(cur_rx - 16, ioaddr + RxBufPtr); + /* See RTL8139 Programming Guide V0.1 for the official handling of + * Rx overflow situations. The document itself contains basically no + * usable information, except for a few exception handling rules. */ + outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + return length; +} + +static void rtl_disable(struct eth_device *dev) +{ + int i; + + ioaddr = dev->iobase; + + /* reset the chip */ + outb(CmdReset, ioaddr + ChipCmd); + + /* Give the chip 10ms to finish the reset. */ + for (i=0; i<100; ++i){ + if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + udelay (100); /* wait 100us */ + } +} +#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_RTL8139 */ diff --git a/drivers/rtl8169.c b/drivers/rtl8169.c new file mode 100644 index 0000000..3393ba8 --- /dev/null +++ b/drivers/rtl8169.c @@ -0,0 +1,888 @@ +/* + * rtl8169.c : U-Boot driver for the RealTek RTL8169 + * + * Masami Komiya (mkomiya@sonare.it) + * + * Most part is taken from r8169.c of etherboot + * + */ + +/************************************************************************** +* r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit +* Written 2003 by Timothy Legge +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code based on: +* r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver +* for Linux kernel 2.4.x. +* +* Written 2002 ShuChen +* See Linux Driver for full information +* +* Linux Driver Version 1.27a, 10.02.2002 +* +* Thanks to: +* Jean Chen of RealTek Semiconductor Corp. for +* providing the evaluation NIC used to develop +* this driver. RealTek's support for Etherboot +* is appreciated. +* +* REVISION HISTORY: +* ================ +* +* v1.0 11-26-2003 timlegge Initial port of Linux driver +* v1.5 01-17-2004 timlegge Initial driver output cleanup +* +* Indent Options: indent -kr -i8 +***************************************************************************/ + +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_RTL8169) + +#undef DEBUG_RTL8169 +#undef DEBUG_RTL8169_TX +#undef DEBUG_RTL8169_RX + +#define drv_version "v1.5" +#define drv_date "01-17-2004" + +static u32 ioaddr; + +/* Condensed operations for readability. */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +#define currticks() get_timer(0) +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +/* media options */ +#define MAX_UNITS 8 +static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; + +/* MAC address length*/ +#define MAC_ADDR_LEN 6 + +/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ +#define MAX_ETH_FRAME_SIZE 1536 + +#define TX_FIFO_THRESH 256 /* In bytes */ + +#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ +#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ +#define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ +#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ + +#define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ +#define RX_BUF_SIZE 1536 /* Rx Buffer size */ +#define RX_BUF_LEN 8192 + +#define RTL_MIN_IO_SIZE 0x80 +#define TX_TIMEOUT (6*HZ) + +/* write/read MMIO register */ +#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) +#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) +#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) +#define RTL_R8(reg) readb (ioaddr + (reg)) +#define RTL_R16(reg) readw (ioaddr + (reg)) +#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) + +#define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE +#define ETH_ALEN MAC_ADDR_LEN +#define ETH_ZLEN 60 + +enum RTL8169_registers { + MAC0 = 0, /* Ethernet hardware address. */ + MAR0 = 8, /* Multicast filter. */ + TxDescStartAddr = 0x20, + TxHDescStartAddr = 0x28, + FLASH = 0x30, + ERSR = 0x36, + ChipCmd = 0x37, + TxPoll = 0x38, + IntrMask = 0x3C, + IntrStatus = 0x3E, + TxConfig = 0x40, + RxConfig = 0x44, + RxMissed = 0x4C, + Cfg9346 = 0x50, + Config0 = 0x51, + Config1 = 0x52, + Config2 = 0x53, + Config3 = 0x54, + Config4 = 0x55, + Config5 = 0x56, + MultiIntr = 0x5C, + PHYAR = 0x60, + TBICSR = 0x64, + TBI_ANAR = 0x68, + TBI_LPAR = 0x6A, + PHYstatus = 0x6C, + RxMaxSize = 0xDA, + CPlusCmd = 0xE0, + RxDescStartAddr = 0xE4, + EarlyTxThres = 0xEC, + FuncEvent = 0xF0, + FuncEventMask = 0xF4, + FuncPresetState = 0xF8, + FuncForceEvent = 0xFC, +}; + +enum RTL8169_register_content { + /*InterruptStatusBits */ + SYSErr = 0x8000, + PCSTimeout = 0x4000, + SWInt = 0x0100, + TxDescUnavail = 0x80, + RxFIFOOver = 0x40, + RxUnderrun = 0x20, + RxOverflow = 0x10, + TxErr = 0x08, + TxOK = 0x04, + RxErr = 0x02, + RxOK = 0x01, + + /*RxStatusDesc */ + RxRES = 0x00200000, + RxCRC = 0x00080000, + RxRUNT = 0x00100000, + RxRWT = 0x00400000, + + /*ChipCmdBits */ + CmdReset = 0x10, + CmdRxEnb = 0x08, + CmdTxEnb = 0x04, + RxBufEmpty = 0x01, + + /*Cfg9346Bits */ + Cfg9346_Lock = 0x00, + Cfg9346_Unlock = 0xC0, + + /*rx_mode_bits */ + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0x08, + AcceptMulticast = 0x04, + AcceptMyPhys = 0x02, + AcceptAllPhys = 0x01, + + /*RxConfigBits */ + RxCfgFIFOShift = 13, + RxCfgDMAShift = 8, + + /*TxConfigBits */ + TxInterFrameGapShift = 24, + TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ + + /*rtl8169_PHYstatus */ + TBI_Enable = 0x80, + TxFlowCtrl = 0x40, + RxFlowCtrl = 0x20, + _1000bpsF = 0x10, + _100bps = 0x08, + _10bps = 0x04, + LinkStatus = 0x02, + FullDup = 0x01, + + /*GIGABIT_PHY_registers */ + PHY_CTRL_REG = 0, + PHY_STAT_REG = 1, + PHY_AUTO_NEGO_REG = 4, + PHY_1000_CTRL_REG = 9, + + /*GIGABIT_PHY_REG_BIT */ + PHY_Restart_Auto_Nego = 0x0200, + PHY_Enable_Auto_Nego = 0x1000, + + /* PHY_STAT_REG = 1; */ + PHY_Auto_Neco_Comp = 0x0020, + + /* PHY_AUTO_NEGO_REG = 4; */ + PHY_Cap_10_Half = 0x0020, + PHY_Cap_10_Full = 0x0040, + PHY_Cap_100_Half = 0x0080, + PHY_Cap_100_Full = 0x0100, + + /* PHY_1000_CTRL_REG = 9; */ + PHY_Cap_1000_Full = 0x0200, + + PHY_Cap_Null = 0x0, + + /*_MediaType*/ + _10_Half = 0x01, + _10_Full = 0x02, + _100_Half = 0x04, + _100_Full = 0x08, + _1000_Full = 0x10, + + /*_TBICSRBit*/ + TBILinkOK = 0x02000000, +}; + +static struct { + const char *name; + u8 version; /* depend on RTL8169 docs */ + u32 RxConfigMask; /* should clear the bits supported by this chip */ +} rtl_chip_info[] = { + {"RTL-8169", 0x00, 0xff7e1880,}, + {"RTL-8169", 0x04, 0xff7e1880,}, +}; + +enum _DescStatusBit { + OWNbit = 0x80000000, + EORbit = 0x40000000, + FSbit = 0x20000000, + LSbit = 0x10000000, +}; + +struct TxDesc { + u32 status; + u32 vlan_tag; + u32 buf_addr; + u32 buf_Haddr; +}; + +struct RxDesc { + u32 status; + u32 vlan_tag; + u32 buf_addr; + u32 buf_Haddr; +}; + +/* Define the TX Descriptor */ +static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; +/* __attribute__ ((aligned(256))); */ + +/* Create a static buffer of size RX_BUF_SZ for each +TX Descriptor. All descriptors point to a +part of this buffer */ +static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; + +/* Define the RX Descriptor */ +static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; + /* __attribute__ ((aligned(256))); */ + +/* Create a static buffer of size RX_BUF_SZ for each +RX Descriptor All descriptors point to a +part of this buffer */ +static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; + +struct rtl8169_private { + void *mmio_addr; /* memory map physical address */ + int chipset; + unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ + unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ + unsigned long dirty_tx; + unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ + unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ + struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ + struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ + unsigned char *RxBufferRings; /* Index of Rx Buffer */ + unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ + unsigned char *Tx_skbuff[NUM_TX_DESC]; +} tpx; + +static struct rtl8169_private *tpc; + +static const u16 rtl8169_intr_mask = + SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | + TxOK | RxErr | RxOK; +static const unsigned int rtl8169_rx_config = + (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_REALTEK, 0x8169}, + {} +}; + +void mdio_write(int RegAddr, int value) +{ + int i; + + RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); + udelay(1000); + + for (i = 2000; i > 0; i--) { + /* Check if the RTL8169 has completed writing to the specified MII register */ + if (!(RTL_R32(PHYAR) & 0x80000000)) { + break; + } else { + udelay(100); + } + } +} + +int mdio_read(int RegAddr) +{ + int i, value = -1; + + RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); + udelay(1000); + + for (i = 2000; i > 0; i--) { + /* Check if the RTL8169 has completed retrieving data from the specified MII register */ + if (RTL_R32(PHYAR) & 0x80000000) { + value = (int) (RTL_R32(PHYAR) & 0xFFFF); + break; + } else { + udelay(100); + } + } + return value; +} + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +static int rtl8169_init_board(struct eth_device *dev) +{ + int i; + u32 tmp; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + ioaddr = dev->iobase; + + /* Soft reset the chip. */ + RTL_W8(ChipCmd, CmdReset); + + /* Check that the chip has finished the reset. */ + for (i = 1000; i > 0; i--) + if ((RTL_R8(ChipCmd) & CmdReset) == 0) + break; + else + udelay(10); + + /* identify chip attached to board */ + tmp = RTL_R32(TxConfig); + tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; + + for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ + if (tmp == rtl_chip_info[i].version) { + tpc->chipset = i; + goto match; + } + } + + /* if unknown chip, assume array element #0, original RTL-8169 in this case */ + printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); + printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); + tpc->chipset = 0; + +match: + return 0; +} + +/************************************************************************** +RECV - Receive a frame +***************************************************************************/ +static int rtl_recv(struct eth_device *dev) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + int cur_rx; + int length = 0; + +#ifdef DEBUG_RTL8169_RX + printf ("%s\n", __FUNCTION__); +#endif + ioaddr = dev->iobase; + + cur_rx = tpc->cur_rx; + if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) { + if (!(tpc->RxDescArray[cur_rx].status & RxRES)) { + unsigned char rxdata[RX_BUF_LEN]; + length = (int) (tpc->RxDescArray[cur_rx]. + status & 0x00001FFF) - 4; + + memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); + NetReceive(rxdata, length); + + if (cur_rx == NUM_RX_DESC - 1) + tpc->RxDescArray[cur_rx].status = + (OWNbit | EORbit) + RX_BUF_SIZE; + else + tpc->RxDescArray[cur_rx].status = + OWNbit + RX_BUF_SIZE; + tpc->RxDescArray[cur_rx].buf_addr = + virt_to_bus(tpc->RxBufferRing[cur_rx]); + } else { + puts("Error Rx"); + } + cur_rx = (cur_rx + 1) % NUM_RX_DESC; + tpc->cur_rx = cur_rx; + return 1; + + } + tpc->cur_rx = cur_rx; + return (0); /* initially as this is called to flush the input */ +} + +#define HZ 1000 +/************************************************************************** +SEND - Transmit a frame +***************************************************************************/ +static int rtl_send(struct eth_device *dev, volatile void *packet, int length) +{ + /* send the packet to destination */ + + u32 to; + u8 *ptxb; + int entry = tpc->cur_tx % NUM_TX_DESC; + u32 len = length; + +#ifdef DEBUG_RTL8169_TX + int stime = currticks(); + printf ("%s\n", __FUNCTION__); + printf("sending %d bytes\n", len); +#endif + + ioaddr = dev->iobase; + + /* point to the current txb incase multiple tx_rings are used */ + ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; + memcpy(ptxb, (char *)packet, (int)length); + + while (len < ETH_ZLEN) + ptxb[len++] = '\0'; + + tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb); + if (entry != (NUM_TX_DESC - 1)) { + tpc->TxDescArray[entry].status = + (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? + len : ETH_ZLEN); + } else { + tpc->TxDescArray[entry].status = + (OWNbit | EORbit | FSbit | LSbit) | + ((len > ETH_ZLEN) ? length : ETH_ZLEN); + } + RTL_W8(TxPoll, 0x40); /* set polling bit */ + + tpc->cur_tx++; + to = currticks() + TX_TIMEOUT; + while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ + + if (currticks() >= to) { +#ifdef DEBUG_RTL8169_TX + puts ("tx timeout/error\n"); + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); +#endif + return 0; + } else { +#ifdef DEBUG_RTL8169_TX + puts("tx done\n"); +#endif + return length; + } +} + +static void rtl8169_set_rx_mode(struct eth_device *dev) +{ + u32 mc_filter[2]; /* Multicast hash filter */ + int rx_mode; + u32 tmp = 0; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + + /* IFF_ALLMULTI */ + /* Too many to filter perfectly -- accept all multicasts. */ + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + mc_filter[1] = mc_filter[0] = 0xffffffff; + + tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & + rtl_chip_info[tpc->chipset].RxConfigMask); + + RTL_W32(RxConfig, tmp); + RTL_W32(MAR0 + 0, mc_filter[0]); + RTL_W32(MAR0 + 4, mc_filter[1]); +} + +static void rtl8169_hw_start(struct eth_device *dev) +{ + u32 i; + +#ifdef DEBUG_RTL8169 + int stime = currticks(); + printf ("%s\n", __FUNCTION__); +#endif + +#if 0 + /* Soft reset the chip. */ + RTL_W8(ChipCmd, CmdReset); + + /* Check that the chip has finished the reset. */ + for (i = 1000; i > 0; i--) { + if ((RTL_R8(ChipCmd) & CmdReset) == 0) + break; + else + udelay(10); + } +#endif + + RTL_W8(Cfg9346, Cfg9346_Unlock); + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + RTL_W8(EarlyTxThres, EarlyTxThld); + + /* For gigabit rtl8169 */ + RTL_W16(RxMaxSize, RxPacketMaxSize); + + /* Set Rx Config register */ + i = rtl8169_rx_config | (RTL_R32(RxConfig) & + rtl_chip_info[tpc->chipset].RxConfigMask); + RTL_W32(RxConfig, i); + + /* Set DMA burst size and Interframe Gap Time */ + RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | + (InterFrameGap << TxInterFrameGapShift)); + + + tpc->cur_rx = 0; + + RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray)); + RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray)); + RTL_W8(Cfg9346, Cfg9346_Lock); + udelay(10); + + RTL_W32(RxMissed, 0); + + rtl8169_set_rx_mode(dev); + + /* no early-rx interrupts */ + RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); + +#ifdef DEBUG_RTL8169 + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); +#endif +} + +static void rtl8169_init_ring(struct eth_device *dev) +{ + int i; + +#ifdef DEBUG_RTL8169 + int stime = currticks(); + printf ("%s\n", __FUNCTION__); +#endif + + tpc->cur_rx = 0; + tpc->cur_tx = 0; + tpc->dirty_tx = 0; + memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); + memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); + + for (i = 0; i < NUM_TX_DESC; i++) { + tpc->Tx_skbuff[i] = &txb[i]; + } + + for (i = 0; i < NUM_RX_DESC; i++) { + if (i == (NUM_RX_DESC - 1)) + tpc->RxDescArray[i].status = + (OWNbit | EORbit) + RX_BUF_SIZE; + else + tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE; + + tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; + tpc->RxDescArray[i].buf_addr = + virt_to_bus(tpc->RxBufferRing[i]); + } + +#ifdef DEBUG_RTL8169 + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); +#endif +} + +/************************************************************************** +RESET - Finish setting up the ethernet interface +***************************************************************************/ +static void rtl_reset(struct eth_device *dev, bd_t *bis) +{ + int i; + u8 diff; + u32 TxPhyAddr, RxPhyAddr; + +#ifdef DEBUG_RTL8169 + int stime = currticks(); + printf ("%s\n", __FUNCTION__); +#endif + + tpc->TxDescArrays = tx_ring; + if (tpc->TxDescArrays == 0) + puts("Allot Error"); + /* Tx Desscriptor needs 256 bytes alignment; */ + TxPhyAddr = virt_to_bus(tpc->TxDescArrays); + diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8)); + TxPhyAddr += diff; + tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff); + + tpc->RxDescArrays = rx_ring; + /* Rx Desscriptor needs 256 bytes alignment; */ + RxPhyAddr = virt_to_bus(tpc->RxDescArrays); + diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8)); + RxPhyAddr += diff; + tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff); + + if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) { + puts("Allocate RxDescArray or TxDescArray failed\n"); + return; + } + + rtl8169_init_ring(dev); + rtl8169_hw_start(dev); + /* Construct a perfect filter frame with the mac address as first match + * and broadcast for all others */ + for (i = 0; i < 192; i++) + txb[i] = 0xFF; + + txb[0] = dev->enetaddr[0]; + txb[1] = dev->enetaddr[1]; + txb[2] = dev->enetaddr[2]; + txb[3] = dev->enetaddr[3]; + txb[4] = dev->enetaddr[4]; + txb[5] = dev->enetaddr[5]; + +#ifdef DEBUG_RTL8169 + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); +#endif +} + +/************************************************************************** +HALT - Turn off ethernet interface +***************************************************************************/ +static void rtl_halt(struct eth_device *dev) +{ + int i; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + + ioaddr = dev->iobase; + + /* Stop the chip's Tx and Rx DMA processes. */ + RTL_W8(ChipCmd, 0x00); + + /* Disable interrupts by clearing the interrupt mask. */ + RTL_W16(IntrMask, 0x0000); + + RTL_W32(RxMissed, 0); + + tpc->TxDescArrays = NULL; + tpc->RxDescArrays = NULL; + tpc->TxDescArray = NULL; + tpc->RxDescArray = NULL; + for (i = 0; i < NUM_RX_DESC; i++) { + tpc->RxBufferRing[i] = NULL; + } +} + +/************************************************************************** +INIT - Look for an adapter, this routine's visible to the outside +***************************************************************************/ + +#define board_found 1 +#define valid_link 0 +static int rtl_init(struct eth_device *dev, bd_t *bis) +{ + static int board_idx = -1; + static int printed_version = 0; + int i, rc; + int option = -1, Cap10_100 = 0, Cap1000 = 0; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + + ioaddr = dev->iobase; + + board_idx++; + + printed_version = 1; + + /* point to private storage */ + tpc = &tpx; + + rc = rtl8169_init_board(dev); + if (rc) + return rc; + + /* Get MAC address. FIXME: read EEPROM */ + for (i = 0; i < MAC_ADDR_LEN; i++) + dev->enetaddr[i] = RTL_R8(MAC0 + i); + +#ifdef DEBUG_RTL8169 + printf("MAC Address"); + for (i = 0; i < MAC_ADDR_LEN; i++) + printf(":%02x", dev->enetaddr[i]); + putc('\n'); +#endif + +#ifdef DEBUG_RTL8169 + /* Print out some hardware info */ + printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); +#endif + + /* if TBI is not endbled */ + if (!(RTL_R8(PHYstatus) & TBI_Enable)) { + int val = mdio_read(PHY_AUTO_NEGO_REG); + + option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; + /* Force RTL8169 in 10/100/1000 Full/Half mode. */ + if (option > 0) { +#ifdef DEBUG_RTL8169 + printf("%s: Force-mode Enabled.\n", dev->name); +#endif + Cap10_100 = 0, Cap1000 = 0; + switch (option) { + case _10_Half: + Cap10_100 = PHY_Cap_10_Half; + Cap1000 = PHY_Cap_Null; + break; + case _10_Full: + Cap10_100 = PHY_Cap_10_Full; + Cap1000 = PHY_Cap_Null; + break; + case _100_Half: + Cap10_100 = PHY_Cap_100_Half; + Cap1000 = PHY_Cap_Null; + break; + case _100_Full: + Cap10_100 = PHY_Cap_100_Full; + Cap1000 = PHY_Cap_Null; + break; + case _1000_Full: + Cap10_100 = PHY_Cap_Null; + Cap1000 = PHY_Cap_1000_Full; + break; + default: + break; + } + mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ + mdio_write(PHY_1000_CTRL_REG, Cap1000); + } else { +#ifdef DEBUG_RTL8169 + printf("%s: Auto-negotiation Enabled.\n", + dev->name); +#endif + /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ + mdio_write(PHY_AUTO_NEGO_REG, + PHY_Cap_10_Half | PHY_Cap_10_Full | + PHY_Cap_100_Half | PHY_Cap_100_Full | + (val & 0x1F)); + + /* enable 1000 Full Mode */ + mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); + + } + + /* Enable auto-negotiation and restart auto-nigotiation */ + mdio_write(PHY_CTRL_REG, + PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); + udelay(100); + + /* wait for auto-negotiation process */ + for (i = 10000; i > 0; i--) { + /* check if auto-negotiation complete */ + if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) { + udelay(100); + option = RTL_R8(PHYstatus); + if (option & _1000bpsF) { +#ifdef DEBUG_RTL8169 + printf("%s: 1000Mbps Full-duplex operation.\n", + dev->name); +#endif + } else { +#ifdef DEBUG_RTL8169 + printf + ("%s: %sMbps %s-duplex operation.\n", + dev->name, + (option & _100bps) ? "100" : + "10", + (option & FullDup) ? "Full" : + "Half"); +#endif + } + break; + } else { + udelay(100); + } + } /* end for-loop to wait for auto-negotiation process */ + + } else { + udelay(100); +#ifdef DEBUG_RTL8169 + printf + ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", + dev->name, + (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); +#endif + } + + return 1; +} + +int rtl8169_initialize(bd_t *bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase; + int idx=0; + + while(1){ + /* Find RTL8169 */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0xf; + + debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); + + dev = (struct eth_device *)malloc(sizeof *dev); + + sprintf (dev->name, "RTL8169#%d", card_number); + + dev->priv = (void *) devno; + dev->iobase = (int)bus_to_phys(iobase); + + dev->init = rtl_reset; + dev->halt = rtl_halt; + dev->send = rtl_send; + dev->recv = rtl_recv; + + eth_register (dev); + + rtl_init(dev, bis); + + card_number++; + } + return card_number; +} + +#endif diff --git a/drivers/s3c4510b_eth.c b/drivers/s3c4510b_eth.c new file mode 100644 index 0000000..0274dd2 --- /dev/null +++ b/drivers/s3c4510b_eth.c @@ -0,0 +1,246 @@ +/*********************************************************************** + * + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: Ethernet interface for Samsung S3C4510B SoC + */ + +#include + +#ifdef CONFIG_DRIVER_S3C4510_ETH + +#include +#include +#include +#include "s3c4510b_eth.h" + +static TX_FrameDescriptor txFDbase[ETH_MaxTxFrames]; +static MACFrame txFrameBase[ETH_MaxTxFrames]; +static RX_FrameDescriptor rxFDbase[PKTBUFSRX]; +static ETH m_eth; + +static s32 TxFDinit( ETH *eth) { + + s32 i; + MACFrame *txFrmBase; + + /* disable cache for access to the TX buffers */ + txFrmBase = (MACFrame *)( (u32)txFrameBase | CACHE_DISABLE_MASK); + + /* store start of Tx descriptors and set current */ + eth->m_curTX_FD = (TX_FrameDescriptor *) ((u32)txFDbase | CACHE_DISABLE_MASK); + eth->m_baseTX_FD = eth->m_curTX_FD; + + for ( i = 0; i < ETH_MaxTxFrames; i++) { + eth->m_baseTX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)&txFrmBase[i]; + eth->m_baseTX_FD[i].m_frameDataPtr.bf.owner = 0x0; /* CPU owner */ + eth->m_baseTX_FD[i].m_opt.ui = 0x0; + eth->m_baseTX_FD[i].m_status.ui = 0x0; + eth->m_baseTX_FD[i].m_nextFD = ð->m_baseTX_FD[i+1]; + } + + /* make the list circular */ + eth->m_baseTX_FD[i-1].m_nextFD = ð->m_baseTX_FD[0]; + + PUT_REG( REG_BDMATXPTR, (u32)eth->m_curTX_FD); + + return 0; +} + +static s32 RxFDinit( ETH *eth) { + + s32 i; + /* MACFrame *rxFrmBase; */ + + /* disable cache for access to the RX buffers */ + /* rxFrmBase = (MACFrame *)( (u32)rxFrameBase | CACHE_DISABLE_MASK); */ + + /* store start of Rx descriptors and set current */ + eth->m_curRX_FD = (RX_FrameDescriptor *)((u32)rxFDbase | CACHE_DISABLE_MASK); + eth->m_baseRX_FD = eth->m_curRX_FD; + for ( i = 0; i < PKTBUFSRX; i++) { + eth->m_baseRX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)NetRxPackets[i] | CACHE_DISABLE_MASK; + eth->m_baseRX_FD[i].m_frameDataPtr.bf.owner = 0x1; /* BDMA owner */ + eth->m_baseRX_FD[i].m_reserved = 0x0; + eth->m_baseRX_FD[i].m_status.ui = 0x0; + eth->m_baseRX_FD[i].m_nextFD = ð->m_baseRX_FD[i+1]; + } + + /* make the list circular */ + eth->m_baseRX_FD[i-1].m_nextFD = ð->m_baseRX_FD[0]; + + PUT_REG( REG_BDMARXPTR, (u32)eth->m_curRX_FD); + + return 0; +} + +/* + * Public u-boot interface functions below + */ + +int eth_init(bd_t *bis) +{ + + ETH *eth = &m_eth; + + /* store our MAC address */ + eth->m_mac = bis->bi_enetaddr; + + /* setup DBMA and MAC */ + PUT_REG( REG_BDMARXCON, ETH_BRxRS); /* reset BDMA RX machine */ + PUT_REG( REG_BDMATXCON, ETH_BTxRS); /* reset BDMA TX machine */ + PUT_REG( REG_MACCON , ETH_SwReset); /* reset MAC machine */ + PUT_REG( REG_BDMARXLSZ, sizeof(MACFrame)); + PUT_REG( REG_MACCON , 0); /* reset MAC machine */ + + /* init frame descriptors */ + TxFDinit( eth); + RxFDinit( eth); + + /* init the CAM with our MAC address */ + PUT_REG( REG_CAM_BASE, (eth->m_mac[0] << 24) | + (eth->m_mac[1] << 16) | + (eth->m_mac[2] << 8) | + (eth->m_mac[3])); + PUT_REG( REG_CAM_BASE + 0x4, (eth->m_mac[4] << 24) | + (eth->m_mac[5] << 16)); + + /* enable CAM address 1 -- the MAC we just loaded */ + PUT_REG( REG_CAMEN, 0x1); + + PUT_REG( REG_CAMCON, + ETH_BroadAcc | /* accept broadcast packetes */ + ETH_CompEn); /* enable compare mode (check against the CAM) */ + + /* configure the BDMA Transmitter control */ + PUT_REG( REG_BDMATXCON, + ETH_BTxBRST | /* BDMA Tx burst size 16 words */ + ETH_BTxMSL110 | /* BDMA Tx wait to fill 6/8 of the BDMA */ + ETH_BTxSTSKO | /* BDMA Tx interrupt(Stop) on non-owner TX FD */ + ETH_BTxEn); /* BDMA Tx Enable */ + + /* configure the MAC Transmitter control */ + PUT_REG( REG_MACTXCON, + ETH_EnComp | /* interrupt when the MAC transmits or discards packet */ + ETH_TxEn); /* MAC transmit enable */ + + /* configure the BDMA Receiver control */ + PUT_REG( REG_BDMARXCON, + ETH_BRxBRST | /* BDMA Rx Burst Size 16 words */ + ETH_BRxSTSKO | /* BDMA Rx interrupt(Stop) on non-owner RX FD */ + ETH_BRxMAINC | /* BDMA Rx Memory Address increment */ + ETH_BRxDIE | /* BDMA Rx Every Received Frame Interrupt Enable */ + ETH_BRxNLIE | /* BDMA Rx NULL List Interrupt Enable */ + ETH_BRxNOIE | /* BDMA Rx Not Owner Interrupt Enable */ + ETH_BRxLittle | /* BDMA Rx Little endian */ + ETH_BRxEn); /* BDMA Rx Enable */ + + /* configure the MAC Receiver control */ + PUT_REG( REG_MACRXCON, + ETH_RxEn); /* MAC ETH_RxEn */ + + return 0; + +} + +/* Send a packet */ +s32 eth_send(volatile void *packet, s32 length) +{ + + u32 i; + ETH *eth = &m_eth; + + if ( eth->m_curTX_FD->m_frameDataPtr.bf.owner) { + printf("eth_send(): TX Frame. CPU not owner.\n"); + return -1; + } + + /* copy user data into frame data pointer */ + memcpy((void *)eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr, + (void *)packet, + length); + + /* Set TX Frame flags */ + eth->m_curTX_FD->m_opt.bf.widgetAlign = 0; + eth->m_curTX_FD->m_opt.bf.frameDataDir = 1; + eth->m_curTX_FD->m_opt.bf.littleEndian = 1; + eth->m_curTX_FD->m_opt.bf.macTxIrqEnbl = 1; + eth->m_curTX_FD->m_opt.bf.no_crc = 0; + eth->m_curTX_FD->m_opt.bf.no_padding = 0; + + /* Set TX Frame length */ + eth->m_curTX_FD->m_status.bf.len = length; + + /* Change ownership to BDMA */ + eth->m_curTX_FD->m_frameDataPtr.bf.owner = 1; + + /* Enable MAC and BDMA Tx control register */ + SET_REG( REG_BDMATXCON, ETH_BTxEn); + SET_REG( REG_MACTXCON, ETH_TxEn); + + /* poll on TX completion status */ + while ( !eth->m_curTX_FD->m_status.bf.complete) { + /* sleep */ + for ( i = 0; i < 0x10000; i ++); + } + + /* Change the Tx frame descriptor for next use */ + eth->m_curTX_FD = eth->m_curTX_FD->m_nextFD; + + return 0; +} + +/* Check for received packets */ +s32 eth_rx (void) +{ + s32 nLen = 0; + ETH *eth = &m_eth; + + /* check if packet ready */ + if ( (GET_REG( REG_BDMASTAT)) & ETH_S_BRxRDF) { + /* process all waiting packets */ + while ( !eth->m_curRX_FD->m_frameDataPtr.bf.owner) { + nLen = eth->m_curRX_FD->m_status.bf.len; + /* call back u-boot -- may call eth_send() */ + NetReceive ((u8 *)eth->m_curRX_FD->m_frameDataPtr.ui, nLen); + /* set owner back to CPU */ + eth->m_curRX_FD->m_frameDataPtr.bf.owner = 1; + /* clear status */ + eth->m_curRX_FD->m_status.ui = 0x0; + /* advance to next descriptor */ + eth->m_curRX_FD = eth->m_curRX_FD->m_nextFD; + /* clear received frame bit */ + PUT_REG( REG_BDMASTAT, ETH_S_BRxRDF); + } + } + + return nLen; +} + +/* Halt ethernet engine */ +void eth_halt(void) +{ + /* disable MAC */ + PUT_REG( REG_MACCON, ETH_HaltReg); +} + +#endif diff --git a/drivers/s3c4510b_eth.h b/drivers/s3c4510b_eth.h new file mode 100644 index 0000000..cbddba7 --- /dev/null +++ b/drivers/s3c4510b_eth.h @@ -0,0 +1,302 @@ +#ifndef __S3C4510B_ETH_H +#define __S3C4510B_ETH_H +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * MODULE: $Id:$ + * Description: Ethernet interface + * Runtime Env: ARM7TDMI + * Change History: + * 03-02-04 Create (Curt Brune) curt@cucy.com + * + */ + +#define __packed __attribute__ ((packed)) + +#define ETH_MAC_ADDR_SIZE (6) /* dst,src addr is 6bytes each */ +#define ETH_MaxTxFrames (16) /* Max number of Tx Frames */ + +/* Buffered DMA Receiver Control Register */ +#define ETH_BRxBRST 0x0000F /* BDMA Rx Burst Size * BRxBRST */ + /* = Burst Data Size 16 */ +#define ETH_BRxSTSKO 0x00020 /* BDMA Rx Stop/Skip Frame or Interrupt(=1) */ + /* case of not OWNER the current Frame */ +#define ETH_BRxMAINC 0x00040 /* BDMA Rx Memory Address Inc/Dec */ +#define ETH_BRxDIE 0x00080 /* BDMA Rx Every Received Frame Interrupt Enable */ +#define ETH_BRxNLIE 0x00100 /* BDMA Rx NULL List Interrupt Enable */ +#define ETH_BRxNOIE 0x00200 /* BDMA Rx Not Owner Interrupt Enable */ +#define ETH_BRxMSOIE 0x00400 /* BDMA Rx Maximum Size over Interrupr Enable */ +#define ETH_BRxLittle 0x00800 /* BDMA Rx Big/Little Endian */ +#define ETH_BRxBig 0x00000 /* BDMA Rx Big/Little Endian */ +#define ETH_BRxWA01 0x01000 /* BDMA Rx Word Alignment- one invalid byte */ +#define ETH_BRxWA10 0x02000 /* BDMA Rx Word Alignment- two invalid byte */ +#define ETH_BRxWA11 0x03000 /* BDMA Rx Word Alignment- three invalid byte */ +#define ETH_BRxEn 0x04000 /* BDMA Rx Enable */ +#define ETH_BRxRS 0x08000 /* BDMA Rx Reset */ +#define ETH_RxEmpty 0x10000 /* BDMA Rx Buffer empty interrupt */ +#define ETH_BRxEarly 0x20000 /* BDMA Rx Early notify Interrupt */ + +/* Buffered DMA Trasmit Control Register(BDMATXCON) */ +#define ETH_BTxBRST 0x0000F /* BDMA Tx Burst Size = 16 */ +#define ETH_BTxSTSKO 0x00020 /* BDMA Tx Stop/Skip Frame or Interrupt in case */ + /* of not Owner the current frame */ +#define ETH_BTxCPIE 0x00080 /* BDMA Tx Complete to send control */ + /* packet Enable */ +#define ETH_BTxNOIE 0x00200 /* BDMA Tx Buffer Not Owner */ +#define ETH_BTxEmpty 0x00400 /* BDMA Tx Buffer Empty Interrupt */ + +/* BDMA Tx buffer can be moved to the MAC Tx IO when the new frame comes in. */ +#define ETH_BTxMSL000 0x00000 /* No wait to fill the BDMA */ +#define ETH_BTxMSL001 0x00800 /* wait to fill 1/8 of the BDMA */ +#define ETH_BTxMSL010 0x01000 /* wait to fill 2/8 of the BDMA */ +#define ETH_BTxMSL011 0x01800 /* wait to fill 3/8 of the BDMA */ +#define ETH_BTxMSL100 0x02000 /* wait to fill 4/8 of the BDMA */ +#define ETH_BTxMSL101 0x02800 /* wait to fill 5/8 of the BDMA */ +#define ETH_BTxMSL110 0x03000 /* wait to fill 6/8 of the BDMA */ +#define ETH_BTxMSL111 0x03800 /* wait to fill 7/8 of the BDMA */ +#define ETH_BTxEn 0x04000 /* BDMA Tx Enable */ +#define ETH_BTxRS 0x08000 /* BDMA Tx Reset */ + +/* BDMA Status Register */ +#define ETH_S_BRxRDF 0x00001 /* BDMA Rx Done Every Received Frame */ +#define ETH_S_BRxNL 0x00002 /* BDMA Rx NULL List */ +#define ETH_S_BRxNO 0x00004 /* BDMA Rx Not Owner */ +#define ETH_S_BRxMSO 0x00008 /* BDMA Rx Maximum Size Over */ +#define ETH_S_BRxEmpty 0x00010 /* BDMA Rx Buffer Empty */ +#define ETH_S_BRxSEarly 0x00020 /* Early Notify */ +#define ETH_S_BRxFRF 0x00080 /* One more frame data in BDMA receive buffer */ +#define ETH_S_BTxCCP 0x10000 /* BDMA Tx Complete to send Control Packet */ +#define ETH_S_BTxNL 0x20000 /* BDMA Tx Null List */ +#define ETH_S_BTxNO 0x40000 /* BDMA Tx Not Owner */ +#define ETH_S_BTxEmpty 0x100000 /* BDMA Tx Buffer Empty */ + +/* MAC Control Register */ +#define ETH_HaltReg 0x0001 /* stop transmission and reception */ + /* after completion of any current packets */ +#define ETH_HaltImm 0x0002 /* Stop transmission and reception immediately */ +#define ETH_SwReset 0x0004 /* reset all Ethernet controller state machines */ + /* and FIFOs */ +#define ETH_FullDup 0x0008 /* allow transmission to begin while reception */ + /* is occurring */ +#define ETH_MACLoop 0x0010 /* MAC loopback */ +#define ETH_ConnM00 0x0000 /* Automatic-default */ +#define ETH_ConnM01 0x0020 /* Force 10Mbits endec */ +#define ETH_ConnM10 0x0040 /* Force MII (rate determined by MII clock */ +#define ETH_MIIOFF 0x0040 /* Force MII (rate determined by MII clock */ +#define ETH_Loop10 0x0080 /* Loop 10Mbps */ +#define ETH_MissRoll 0x0400 /* Missed error counter rolled over */ +#define ETH_MDCOFF 0x1000 /* MII Station Management Clock Off */ +#define ETH_EnMissRoll 0x2000 /* Interrupt when missed error counter rolls */ + /* over */ +#define ETH_Link10 0x8000 /* Link status 10Mbps */ + +/* CAM control register(CAMCON) */ +#define ETH_StationAcc 0x0001 /* Accept any packet with a unicast station */ + /* address */ +#define ETH_GroupAcc 0x0002 /* Accept any packet with multicast-group */ + /* station address */ +#define ETH_BroadAcc 0x0004 /* Accept any packet with a broadcast station */ + /* address */ +#define ETH_NegCAM 0x0008 /* 0: Accept packets CAM recognizes, */ + /* reject others */ + /* 1: reject packets CAM recognizes, */ + /* accept others */ +#define ETH_CompEn 0x0010 /* Compare Enable mode */ + +/* Transmit Control Register(MACTXCON) */ +#define ETH_TxEn 0x0001 /* transmit Enable */ +#define ETH_TxHalt 0x0002 /* Transmit Halt Request */ +#define ETH_NoPad 0x0004 /* suppress Padding */ +#define ETH_NoCRC 0x0008 /* Suppress CRC */ +#define ETH_FBack 0x0010 /* Fast Back-off */ +#define ETH_NoDef 0x0020 /* Disable the defer counter */ +#define ETH_SdPause 0x0040 /* Send Pause */ +#define ETH_MII10En 0x0080 /* MII 10Mbps mode enable */ +#define ETH_EnUnder 0x0100 /* Enable Underrun */ +#define ETH_EnDefer 0x0200 /* Enable Deferral */ +#define ETH_EnNCarr 0x0400 /* Enable No Carrier */ +#define ETH_EnExColl 0x0800 /* interrupt if 16 collision occur */ + /* in the same packet */ +#define ETH_EnLateColl 0x1000 /* interrupt if collision occurs after */ + /* 512 bit times(64 bytes times) */ +#define ETH_EnTxPar 0x2000 /* interrupt if the MAC transmit FIFO */ + /* has a parity error */ +#define ETH_EnComp 0x4000 /* interrupt when the MAC transmits or */ + /* discards one packet */ + +/* Transmit Status Register(MACTXSTAT) */ +#define ETH_ExColl 0x0010 /* Excessive collision */ +#define ETH_TxDeffered 0x0020 /* set if 16 collisions occur for same packet */ +#define ETH_Paused 0x0040 /* packet waited because of pause during */ + /* transmission */ +#define ETH_IntTx 0x0080 /* set if transmission of packet causes an */ + /* interrupt condiftion */ +#define ETH_Under 0x0100 /* MAC transmit FIFO becomes empty during */ + /* transmission */ +#define ETH_Defer 0x0200 /* MAC defers for MAC deferral */ +#define ETH_NCarr 0x0400 /* No carrier sense detected during the */ + /* transmission of a packet */ +#define ETH_SQE 0x0800 /* Signal Quality Error */ +#define ETH_LateColl 0x1000 /* a collision occures after 512 bit times */ +#define ETH_TxPar 0x2000 /* MAC transmit FIFO has detected a parity error */ +#define ETH_Comp 0x4000 /* MAC transmit or discards one packet */ +#define ETH_TxHalted 0x8000 /* Transmission was halted by clearing */ + /* TxEn or Halt immedite */ + +/* Receive Control Register (MACRXCON) */ +#define ETH_RxEn 0x0001 +#define ETH_RxHalt 0x0002 +#define ETH_LongEn 0x0004 +#define ETH_ShortEn 0x0008 +#define ETH_StripCRC 0x0010 +#define ETH_PassCtl 0x0020 +#define ETH_IgnoreCRC 0x0040 +#define ETH_EnAlign 0x0100 +#define ETH_EnCRCErr 0x0200 +#define ETH_EnOver 0x0400 +#define ETH_EnLongErr 0x0800 +#define ETH_EnRxPar 0x2000 +#define ETH_EnGood 0x4000 + +/* Receive Status Register(MACRXSTAT) */ +#define ETH_MCtlRecd 0x0020 +#define ETH_MIntRx 0x0040 +#define ETH_MRx10Stat 0x0080 +#define ETH_MAllignErr 0x0100 +#define ETH_MCRCErr 0x0200 +#define ETH_MOverflow 0x0400 +#define ETH_MLongErr 0x0800 +#define ETH_MRxPar 0x2000 +#define ETH_MRxGood 0x4000 +#define ETH_MRxHalted 0x8000 + +/* type of ethernet packets */ +#define ETH_TYPE_ARP (0x0806) +#define ETH_TYPE_IP (0x0800) + +#define ETH_HDR_SIZE (14) + +/* bit field for frame data pointer word */ +typedef struct __BF_FrameDataPtr { + u32 dataPtr:31; + u32 owner: 1; +} BF_FrameDataPtr; + +typedef union _FrameDataPtr { + u32 ui; + BF_FrameDataPtr bf; +} FrameDataPtr; + +typedef struct __BF_TX_Options { + u32 no_padding: 1; + u32 no_crc: 1; + u32 macTxIrqEnbl: 1; + u32 littleEndian: 1; + u32 frameDataDir: 1; + u32 widgetAlign: 2; + u32 reserved:25; +} BF_TX_Options; + +typedef union _TX_Options { + u32 ui; + BF_TX_Options bf; +} TX_Options; + +typedef struct __BF_RX_Status { + u32 len:16; /* frame length */ + u32 reserved1: 3; + u32 overMax: 1; + u32 reserved2: 1; + u32 ctrlRcv: 1; + u32 intRx: 1; + u32 rx10stat: 1; + u32 alignErr: 1; + u32 crcErr: 1; + u32 overFlow: 1; + u32 longErr: 1; + u32 reserved3: 1; + u32 parityErr: 1; + u32 good: 1; + u32 halted: 1; +} BF_RX_Status; + +typedef union _RX_Status { + u32 ui; + BF_RX_Status bf; +} RX_Status; + +typedef struct __BF_TX_Status { + u32 len:16; /* frame length */ + u32 txCollCnt: 4; + u32 exColl: 1; + u32 txDefer: 1; + u32 paused: 1; + u32 intTx: 1; + u32 underRun: 1; + u32 defer: 1; + u32 noCarrier: 1; + u32 SQErr: 1; + u32 lateColl: 1; + u32 parityErr: 1; + u32 complete: 1; + u32 halted: 1; +} BF_TX_Status; + +typedef union _TX_Status { + u32 ui; + BF_TX_Status bf; +} TX_Status; + +/* TX descriptor structure */ +typedef struct __TX_FrameDescriptor { + volatile FrameDataPtr m_frameDataPtr; + TX_Options m_opt; + volatile TX_Status m_status; + struct __TX_FrameDescriptor *m_nextFD; +} TX_FrameDescriptor; + +/* RX descriptor structure */ +typedef struct __RX_FrameDescriptor { + volatile FrameDataPtr m_frameDataPtr; + u32 m_reserved; + volatile RX_Status m_status; + struct __RX_FrameDescriptor *m_nextFD; +} RX_FrameDescriptor; + +/* MAC Frame Structure */ +typedef struct __MACFrame { + u8 m_dstAddr[6] __packed; + u8 m_srcAddr[6] __packed; + u16 m_lengthOrType __packed; + u8 m_payload[1506] __packed; +} MACFrame; + +/* Ethernet Control block */ +typedef struct __ETH { + TX_FrameDescriptor *m_curTX_FD; /* pointer to current TX frame descriptor */ + TX_FrameDescriptor *m_baseTX_FD; /* pointer to base TX frame descriptor */ + RX_FrameDescriptor *m_curRX_FD; /* pointer to current RX frame descriptor */ + RX_FrameDescriptor *m_baseRX_FD; /* pointer to base RX frame descriptor */ + u8 *m_mac; /* pointer to our MAC address */ +} ETH; + +#endif diff --git a/drivers/s3c4510b_uart.c b/drivers/s3c4510b_uart.c new file mode 100644 index 0000000..44b96a9 --- /dev/null +++ b/drivers/s3c4510b_uart.c @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * MODULE: $Id:$ + * Description: UART/Serial interface for Samsung S3C4510B SoC + * Runtime Env: ARM7TDMI + * Change History: + * 03-02-04 Create (Curt Brune) curt@cucy.com + * + */ + +#include + +#ifdef CONFIG_DRIVER_S3C4510_UART + +#include +#include "s3c4510b_uart.h" + +static UART *uart; + +/* flush serial input queue. returns 0 on success or negative error + * number otherwise + */ +static int serial_flush_input(void) +{ + volatile u32 tmp; + + /* keep on reading as long as the receiver is not empty */ + while( uart->m_stat.bf.rxReady) { + tmp = uart->m_rx; + } + + return 0; +} + + +/* flush output queue. returns 0 on success or negative error number + * otherwise + */ +static int serial_flush_output(void) +{ + /* wait until the transmitter is no longer busy */ + while( !uart->m_stat.bf.txBufEmpty); + + return 0; +} + + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + UART_LINE_CTRL ulctrl; + UART_CTRL uctrl; + UART_BAUD_DIV ubd; + + serial_flush_output(); + serial_flush_input(); + + /* control register */ + uctrl.ui = 0x0; + uctrl.bf.rxMode = 0x1; + uctrl.bf.rxIrq = 0x0; + uctrl.bf.txMode = 0x1; + uctrl.bf.DSR = 0x0; + uctrl.bf.sendBreak = 0x0; + uctrl.bf.loopBack = 0x0; + uart->m_ctrl.ui = uctrl.ui; + + /* line control register */ + ulctrl.ui = 0x0; + ulctrl.bf.wordLen = 0x3; /* 8 bit data */ + ulctrl.bf.nStop = 0x0; /* 1 stop bit */ + ulctrl.bf.parity = 0x0; /* no parity */ + ulctrl.bf.clk = 0x0; /* internal clock */ + ulctrl.bf.infra_red = 0x0; /* no infra_red */ + uart->m_lineCtrl.ui = ulctrl.ui; + + ubd.ui = 0x0; + + /* see table on page 10-15 in SAMSUNG S3C4510B manual */ + /* get correct divisor */ + switch(gd->baudrate) { + case 1200: ubd.bf.cnt0 = 1301; break; + case 2400: ubd.bf.cnt0 = 650; break; + case 4800: ubd.bf.cnt0 = 324; break; + case 9600: ubd.bf.cnt0 = 162; break; + case 19200: ubd.bf.cnt0 = 80; break; + case 38400: ubd.bf.cnt0 = 40; break; + case 57600: ubd.bf.cnt0 = 26; break; + case 115200: ubd.bf.cnt0 = 13; break; + } + + uart->m_baudDiv.ui = ubd.ui; + uart->m_baudCnt = 0x0; + uart->m_baudClk = 0x0; + +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + +#if CONFIG_SERIAL1 == 1 + uart = (UART *)UART0_BASE; +#elif CONFIG_SERIAL1 == 2 + uart = (UART *)UART1_BASE; +#else +#error CONFIG_SERIAL1 not equal to 1 or 2 +#endif + + serial_setbrg (); + + return (0); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + /* wait for room in the transmit FIFO */ + while( !uart->m_stat.bf.txBufEmpty); + + uart->m_tx = c; + + /* + to be polite with serial console add a line feed + to the carriage return character + */ + if (c=='\n') + serial_putc('\r'); +} + +/* + * Test if an input byte is ready from the serial port. Returns non-zero on + * success, 0 otherwise. + */ +int serial_tstc (void) +{ + return uart->m_stat.bf.rxReady; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + int rv; + + for(;;) { + rv = serial_tstc(); + + if (rv) { + return uart->m_rx & 0xFF; + } + } +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } + + /* busy wait for tx complete */ + while ( !uart->m_stat.bf.txComplete); + + /* clear break */ + uart->m_ctrl.bf.sendBreak = 0; + +} + +#endif diff --git a/drivers/s3c4510b_uart.h b/drivers/s3c4510b_uart.h new file mode 100644 index 0000000..b06c76d --- /dev/null +++ b/drivers/s3c4510b_uart.h @@ -0,0 +1,109 @@ +#ifndef __UART_H +#define __UART_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: S3C4510B UART register layout + */ + +/* UART LINE CONTROL register */ +typedef struct __BF_UART_LINE_CTRL { + u32 wordLen: 2; + u32 nStop: 1; + u32 parity: 3; + u32 clk: 1; + u32 infra_red: 1; + u32 unused:24; +} BF_UART_LINE_CTRL; + +typedef union _UART_LINE_CTRL { + u32 ui; + BF_UART_LINE_CTRL bf; +} UART_LINE_CTRL; + +/* UART CONTROL register */ +typedef struct __BF_UART_CTRL { + u32 rxMode: 2; + u32 rxIrq: 1; + u32 txMode: 2; + u32 DSR: 1; + u32 sendBreak: 1; + u32 loopBack: 1; + u32 unused:24; +} BF_UART_CTRL; + +typedef union _UART_CTRL { + u32 ui; + BF_UART_CTRL bf; +} UART_CTRL; + +/* UART STATUS register */ +typedef struct __BF_UART_STAT { + u32 overrun: 1; + u32 parity: 1; + u32 frame: 1; + u32 breakIrq: 1; + u32 DTR: 1; + u32 rxReady: 1; + u32 txBufEmpty: 1; + u32 txComplete: 1; + u32 unused:24; +} BF_UART_STAT; + +typedef union _UART_STAT { + u32 ui; + BF_UART_STAT bf; +} UART_STAT; + +/* UART BAUD_DIV register */ +typedef struct __BF_UART_BAUD_DIV { + u32 cnt1: 4; + u32 cnt0:12; + u32 unused:16; +} BF_UART_BAUD_DIV; + +typedef union _UART_BAUD_DIV { + u32 ui; + BF_UART_BAUD_DIV bf; +} UART_BAUD_DIV; + +/* UART register block */ +typedef struct __UART { + volatile UART_LINE_CTRL m_lineCtrl; + volatile UART_CTRL m_ctrl; + volatile UART_STAT m_stat; + volatile u32 m_tx; + volatile u32 m_rx; + volatile UART_BAUD_DIV m_baudDiv; + volatile u32 m_baudCnt; + volatile u32 m_baudClk; +} UART; + +#define NL 0x0A +#define CR 0x0D +#define BSP 0x08 +#define ESC 0x1B +#define CTRLZ 0x1A +#define RUBOUT 0x7F + +#endif diff --git a/drivers/sed13806.c b/drivers/sed13806.c new file mode 100644 index 0000000..6996ca8 --- /dev/null +++ b/drivers/sed13806.c @@ -0,0 +1,310 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* Video support for Epson SED13806 chipset */ + +#include + +#ifdef CONFIG_VIDEO_SED13806 + +#include +#include + +#define readByte(ptrReg) \ + *(volatile unsigned char *)(sed13806.isaBase + ptrReg) + +#define writeByte(ptrReg,value) \ + *(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value + +#ifdef CONFIG_TOTAL5200 +#define writeWord(ptrReg,value) \ + (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = value) +#else +#define writeWord(ptrReg,value) \ + (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00)) +#endif + +GraphicDevice sed13806; + +/*----------------------------------------------------------------------------- + * EpsonSetRegs -- + *----------------------------------------------------------------------------- + */ +static void EpsonSetRegs (void) +{ + /* the content of the chipset register depends on the board (clocks, ...)*/ + const S1D_REGS *preg = board_get_regs (); + while (preg -> Index) { + writeByte (preg -> Index, preg -> Value); + preg ++; + } +} + +/*----------------------------------------------------------------------------- + * video_hw_init -- + *----------------------------------------------------------------------------- + */ +void *video_hw_init (void) +{ + unsigned int *vm, i; + + memset (&sed13806, 0, sizeof (GraphicDevice)); + + /* Initialization of the access to the graphic chipset + Retreive base address of the chipset + (see board/RPXClassic/eccx.c) */ + if ((sed13806.isaBase = board_video_init ()) == 0) { + return (NULL); + } + + sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET; + sed13806.winSizeX = board_get_width (); + sed13806.winSizeY = board_get_height (); + +#if defined(CONFIG_VIDEO_SED13806_8BPP) + sed13806.gdfIndex = GDF__8BIT_INDEX; + sed13806.gdfBytesPP = 1; + +#elif defined(CONFIG_VIDEO_SED13806_16BPP) + sed13806.gdfIndex = GDF_16BIT_565RGB; + sed13806.gdfBytesPP = 2; + +#else +#error Unsupported SED13806 BPP +#endif + + sed13806.memSize = sed13806.winSizeX * sed13806.winSizeY * sed13806.gdfBytesPP; + + /* Load SED registers */ + EpsonSetRegs (); + + /* (see board/RPXClassic/RPXClassic.c) */ + board_validate_screen (sed13806.isaBase); + + /* Clear video memory */ + i = sed13806.memSize/4; + vm = (unsigned int *)sed13806.frameAdrs; + while(i--) + *vm++ = 0; + + + return (&sed13806); +} +/*----------------------------------------------------------------------------- + * Epson_wait_idle -- Wait for hardware to become idle + *----------------------------------------------------------------------------- + */ +static void Epson_wait_idle (void) +{ + while (readByte (BLT_CTRL0) & 0x80); + + /* Read a word in the BitBLT memory area to shutdown the BitBLT engine */ + *(volatile unsigned short *)(sed13806.isaBase + BLT_REG); +} + +/*----------------------------------------------------------------------------- + * video_hw_bitblt -- + *----------------------------------------------------------------------------- + */ +void video_hw_bitblt ( + unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&sed13806; + unsigned long srcAddr, dstAddr; + unsigned int stride = bpp * pGD -> winSizeX; + + srcAddr = (src_y * stride) + (src_x * bpp); + dstAddr = (dst_y * stride) + (dst_x * bpp); + + Epson_wait_idle (); + + writeByte(BLT_ROP,0x0C); /* source */ + writeByte(BLT_OP,0x02);/* move blit in positive direction with ROP */ + writeWord(BLT_MEM_OFF0, stride / 2); + if (pGD -> gdfIndex == GDF__8BIT_INDEX) { + writeByte(BLT_CTRL1,0x00); + } + else { + writeByte(BLT_CTRL1,0x01); + } + + writeWord(BLT_WIDTH0,(dim_x - 1)); + writeWord(BLT_HEIGHT0,(dim_y - 1)); + + /* set up blit registers */ + writeByte(BLT_SRC_ADDR0,srcAddr); + writeByte(BLT_SRC_ADDR1,srcAddr>>8); + writeByte(BLT_SRC_ADDR2,srcAddr>>16); + + writeByte(BLT_DST_ADDR0,dstAddr); + writeByte(BLT_DST_ADDR1,dstAddr>>8); + writeByte(BLT_DST_ADDR2,dstAddr>>16); + + /* Engage the blt engine */ + /* rectangular region for src and dst */ + writeByte(BLT_CTRL0,0x80); + + /* wait untill current blits finished */ + Epson_wait_idle (); +} +/*----------------------------------------------------------------------------- + * video_hw_rectfill -- + *----------------------------------------------------------------------------- + */ +void video_hw_rectfill ( + unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&sed13806; + unsigned long dstAddr; + unsigned int stride = bpp * pGD -> winSizeX; + + dstAddr = (dst_y * stride) + (dst_x * bpp); + + Epson_wait_idle (); + + /* set up blit registers */ + writeByte(BLT_DST_ADDR0,dstAddr); + writeByte(BLT_DST_ADDR1,dstAddr>>8); + writeByte(BLT_DST_ADDR2,dstAddr>>16); + + writeWord(BLT_WIDTH0,(dim_x - 1)); + writeWord(BLT_HEIGHT0,(dim_y - 1)); + writeWord(BLT_FGCOLOR0,color); + + writeByte(BLT_OP,0x0C); /* solid fill */ + writeWord(BLT_MEM_OFF0,stride / 2); + + if (pGD -> gdfIndex == GDF__8BIT_INDEX) { + writeByte(BLT_CTRL1,0x00); + } + else { + writeByte(BLT_CTRL1,0x01); + } + + /* Engage the blt engine */ + /* rectangular region for src and dst */ + writeByte(BLT_CTRL0,0x80); + + /* wait untill current blits finished */ + Epson_wait_idle (); +} + +/*----------------------------------------------------------------------------- + * video_set_lut -- + *----------------------------------------------------------------------------- + */ +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + writeByte(REG_LUT_ADDR, index ); + writeByte(REG_LUT_DATA, r); + writeByte(REG_LUT_DATA, g); + writeByte(REG_LUT_DATA, b); +} +#ifdef CONFIG_VIDEO_HW_CURSOR +/*----------------------------------------------------------------------------- + * video_set_hw_cursor -- + *----------------------------------------------------------------------------- + */ +void video_set_hw_cursor (int x, int y) +{ + writeByte (LCD_CURSOR_XL, (x & 0xff)); + writeByte (LCD_CURSOR_XM, (x >> 8)); + writeByte (LCD_CURSOR_YL, (y & 0xff)); + writeByte (LCD_CURSOR_YM, (y >> 8)); +} + +/*----------------------------------------------------------------------------- + * video_init_hw_cursor -- + *----------------------------------------------------------------------------- + */ +void video_init_hw_cursor (int font_width, int font_height) +{ + volatile unsigned char *ptr; + unsigned char pattern; + int i; + + + /* Init cursor content + Cursor size is 64x64 pixels + Start of the cursor memory depends on panel type (dual panel ...) */ + if ((i = readByte (LCD_CURSOR_START)) == 0) { + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE); + } + else { + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192)); + } + + /* Fill the first line and the first empty line after cursor */ + for (i = 0, pattern = 0; i < 64; i++) { + if (i < font_width) { + /* Invert background */ + pattern |= 0x3; + + } + else { + /* Background */ + pattern |= 0x2; + } + if ((i & 3) == 3) { + *ptr = pattern; + *(ptr + font_height * 16) = 0xaa; + ptr ++; + pattern = 0; + } + pattern <<= 2; + } + + /* Duplicate this line */ + for (i = 1; i < font_height; i++) { + memcpy ((void *)ptr, (void *)(ptr - 16), 16); + ptr += 16; + } + + for (; i < 64; i++) { + memcpy ((void *)(ptr + 16), (void *)ptr, 16); + ptr += 16; + } + + /* Select cursor mode */ + writeByte (LCD_CURSOR_CNTL, 1); +} +#endif +#endif diff --git a/drivers/sed156x.c b/drivers/sed156x.c new file mode 100644 index 0000000..e9d5ed4 --- /dev/null +++ b/drivers/sed156x.c @@ -0,0 +1,566 @@ +/* + * (C) Copyright 2003 + * + * Pantelis Antoniou + * Intracom S.A. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +#ifdef CONFIG_SED156X + +/* configure according to the selected display */ +#if defined(CONFIG_SED156X_PG12864Q) +#define LCD_WIDTH 128 +#define LCD_HEIGHT 64 +#define LCD_LINES 64 +#define LCD_PAGES 9 +#define LCD_COLUMNS 132 +#else +#error Unsupported SED156x configuration +#endif + +/* include the font data */ +#include + +#if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16 +#error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16 +#endif + +#define LCD_BYTE_WIDTH (LCD_WIDTH / 8) +#define VIDEO_FONT_BYTE_WIDTH (VIDEO_FONT_WIDTH / 8) + +#define LCD_TEXT_WIDTH (LCD_WIDTH / VIDEO_FONT_WIDTH) +#define LCD_TEXT_HEIGHT (LCD_HEIGHT / VIDEO_FONT_HEIGHT) + +#define LCD_BYTE_LINESZ (LCD_BYTE_WIDTH * VIDEO_FONT_HEIGHT) + +const int sed156x_text_width = LCD_TEXT_WIDTH; +const int sed156x_text_height = LCD_TEXT_HEIGHT; + +/**************************************************************************************/ + +#define SED156X_SPI_RXD() (SED156X_SPI_RXD_PORT & SED156X_SPI_RXD_MASK) + +#define SED156X_SPI_TXD(x) \ + do { \ + if (x) \ + SED156X_SPI_TXD_PORT |= SED156X_SPI_TXD_MASK; \ + else \ + SED156X_SPI_TXD_PORT &= ~SED156X_SPI_TXD_MASK; \ + } while(0) + +#define SED156X_SPI_CLK(x) \ + do { \ + if (x) \ + SED156X_SPI_CLK_PORT |= SED156X_SPI_CLK_MASK; \ + else \ + SED156X_SPI_CLK_PORT &= ~SED156X_SPI_CLK_MASK; \ + } while(0) + +#define SED156X_SPI_CLK_TOGGLE() (SED156X_SPI_CLK_PORT ^= SED156X_SPI_CLK_MASK) + +#define SED156X_SPI_BIT_DELAY() /* no delay */ + +#define SED156X_CS(x) \ + do { \ + if (x) \ + SED156X_CS_PORT |= SED156X_CS_MASK; \ + else \ + SED156X_CS_PORT &= ~SED156X_CS_MASK; \ + } while(0) + +#define SED156X_A0(x) \ + do { \ + if (x) \ + SED156X_A0_PORT |= SED156X_A0_MASK; \ + else \ + SED156X_A0_PORT &= ~SED156X_A0_MASK; \ + } while(0) + +/**************************************************************************************/ + +/*** LCD Commands ***/ + +#define LCD_ON 0xAF /* Display ON */ +#define LCD_OFF 0xAE /* Display OFF */ +#define LCD_LADDR 0x40 /* Display start line set + (6-bit) address */ +#define LCD_PADDR 0xB0 /* Page address set + (4-bit) page */ +#define LCD_CADRH 0x10 /* Column address set upper + (4-bit) column hi */ +#define LCD_CADRL 0x00 /* Column address set lower + (4-bit) column lo */ +#define LCD_ADC_NRM 0xA0 /* ADC select Normal */ +#define LCD_ADC_REV 0xA1 /* ADC select Reverse */ +#define LCD_DSP_NRM 0xA6 /* LCD display Normal */ +#define LCD_DSP_REV 0xA7 /* LCD display Reverse */ +#define LCD_DPT_NRM 0xA4 /* Display all points Normal */ +#define LCD_DPT_ALL 0xA5 /* Display all points ON */ +#define LCD_BIAS9 0xA2 /* LCD bias set 1/9 */ +#define LCD_BIAS7 0xA3 /* LCD bias set 1/7 */ +#define LCD_CAINC 0xE0 /* Read/modify/write */ +#define LCD_CAEND 0xEE /* End */ +#define LCD_RESET 0xE2 /* Reset */ +#define LCD_C_NRM 0xC0 /* Common output mode select Normal direction */ +#define LCD_C_RVS 0xC8 /* Common output mode select Reverse direction */ +#define LCD_PWRMD 0x28 /* Power control set + (3-bit) mode */ +#define LCD_RESRT 0x20 /* V5 v. reg. int. resistor ratio set + (3-bit) ratio */ +#define LCD_EVSET 0x81 /* Electronic volume mode set + byte = (6-bit) volume */ +#define LCD_SIOFF 0xAC /* Static indicator OFF */ +#define LCD_SION 0xAD /* Static indicator ON + byte = (2-bit) mode */ +#define LCD_NOP 0xE3 /* NOP */ +#define LCD_TEST 0xF0 /* Test/Test mode reset (Note: *DO NOT USE*) */ + +/*------------------------------------------------------------------------------- + Compound commands + ------------------------------------------------------------------------------- + Command Description Commands + ---------- ------------------------ ------------------------------------- + POWS_ON POWER SAVER ON command LCD_OFF, LCD_D_ALL + POWS_OFF POWER SAVER OFF command LCD_D_NRM + SLEEPON SLEEP mode LCD_SIOFF, POWS_ON + SLEEPOFF SLEEP mode cancel LCD_D_NRM, LCD_SION, LCD_SIS_??? + STDBYON STAND BY mode LCD_SION, POWS_ON + STDBYOFF STAND BY mode cancel LCD_D_NRM + -------------------------------------------------------------------------------*/ + +/*** LCD various parameters ***/ +#define LCD_PPB 8 /* Pixels per byte (display is B/W, 1 bit per pixel) */ + +/*** LCD Status byte masks ***/ +#define LCD_S_BUSY 0x80 /* Status Read - BUSY mask */ +#define LCD_S_ADC 0x40 /* Status Read - ADC mask */ +#define LCD_S_ONOFF 0x20 /* Status Read - ON/OFF mask */ +#define LCD_S_RESET 0x10 /* Status Read - RESET mask */ + +/*** LCD commands parameter masks ***/ +#define LCD_M_LADDR 0x3F /* Display start line (6-bit) address mask */ +#define LCD_M_PADDR 0x0F /* Page address (4-bit) page mask */ +#define LCD_M_CADRH 0x0F /* Column address upper (4-bit) column hi mask */ +#define LCD_M_CADRL 0x0F /* Column address lower (4-bit) column lo mask */ +#define LCD_M_PWRMD 0x07 /* Power control (3-bit) mode mask */ +#define LCD_M_RESRT 0x07 /* V5 v. reg. int. resistor ratio (3-bit) ratio mask */ +#define LCD_M_EVSET 0x3F /* Electronic volume mode byte (6-bit) volume mask */ +#define LCD_M_SION 0x03 /* Static indicator ON (2-bit) mode mask */ + +/*** LCD Power control cirquits control masks ***/ +#define LCD_PWRBSTR 0x04 /* Power control mode - Booster cirquit ON */ +#define LCD_PWRVREG 0x02 /* Power control mode - Voltage regulator cirquit ON */ +#define LCD_PWRVFOL 0x01 /* Power control mode - Voltage follower cirquit ON */ + +/*** LCD Static indicator states ***/ +#define LCD_SIS_OFF 0x00 /* Static indicator register set - OFF state */ +#define LCD_SIS_BL 0x01 /* Static indicator register set - 1s blink state */ +#define LCD_SIS_RBL 0x02 /* Static indicator register set - .5s rapid blink state */ +#define LCD_SIS_ON 0x03 /* Static indicator register set - constantly on state */ + +/*** LCD functions special parameters (commands) ***/ +#define LCD_PREVP 0x80 /* Page number for moving to previous */ +#define LCD_NEXTP 0x81 /* or next page */ +#define LCD_ERR_P 0xFF /* Error in page number */ + +/*** LCD initialization settings ***/ +#define LCD_BIAS LCD_BIAS9 /* Bias: 1/9 */ +#define LCD_ADCMODE LCD_ADC_NRM /* ADC mode: normal */ +#define LCD_COMDIR LCD_C_NRM /* Common output mode: normal */ +#define LCD_RRATIO 0 /* Resistor ratio: 0 */ +#define LCD_CNTRST 0x1C /* electronic volume: 1Ch */ +#define LCD_POWERM (LCD_PWRBSTR | LCD_PWRVREG | LCD_PWRVFOL) /* Power mode: All on */ + +/**************************************************************************************/ + +static inline unsigned int sed156x_transfer(unsigned int val) +{ + unsigned int rx; + int b; + + rx = 0; b = 8; + while (--b >= 0) { + SED156X_SPI_TXD(val & 0x80); + val <<= 1; + SED156X_SPI_CLK_TOGGLE(); + SED156X_SPI_BIT_DELAY(); + rx <<= 1; + if (SED156X_SPI_RXD()) + rx |= 1; + SED156X_SPI_CLK_TOGGLE(); + SED156X_SPI_BIT_DELAY(); + } + + return rx; +} + +unsigned int sed156x_data_transfer(unsigned int val) +{ + unsigned int rx; + + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(1); + + rx = sed156x_transfer(val); + + SED156X_CS(1); + + return rx; +} + +void sed156x_data_block_transfer(const u8 *p, int size) +{ + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(1); + + while (--size >= 0) + sed156x_transfer(*p++); + + SED156X_CS(1); +} + +unsigned int sed156x_cmd_transfer(unsigned int val) +{ + unsigned int rx; + + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(0); + + rx = sed156x_transfer(val); + + SED156X_CS(1); + SED156X_A0(1); + + return rx; +} + +/******************************************************************************/ + +static u8 hw_screen[LCD_PAGES][LCD_COLUMNS]; +static u8 last_hw_screen[LCD_PAGES][LCD_COLUMNS]; +static u8 sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT]; + +void sed156x_sync(void) +{ + int i, j, last_page; + u8 *d; + const u8 *s, *e, *b, *r; + u8 v0, v1, v2, v3, v4, v5, v6, v7; + + /* copy and rotate sw_screen to hw_screen */ + for (i = 0; i < LCD_HEIGHT / 8; i++) { + + d = &hw_screen[i][0]; + s = &sw_screen[LCD_BYTE_WIDTH * 8 * i + LCD_BYTE_WIDTH - 1]; + + for (j = 0; j < LCD_WIDTH / 8; j++) { + + v0 = s[0 * LCD_BYTE_WIDTH]; + v1 = s[1 * LCD_BYTE_WIDTH]; + v2 = s[2 * LCD_BYTE_WIDTH]; + v3 = s[3 * LCD_BYTE_WIDTH]; + v4 = s[4 * LCD_BYTE_WIDTH]; + v5 = s[5 * LCD_BYTE_WIDTH]; + v6 = s[6 * LCD_BYTE_WIDTH]; + v7 = s[7 * LCD_BYTE_WIDTH]; + + d[0] = ((v7 & 0x01) << 7) | + ((v6 & 0x01) << 6) | + ((v5 & 0x01) << 5) | + ((v4 & 0x01) << 4) | + ((v3 & 0x01) << 3) | + ((v2 & 0x01) << 2) | + ((v1 & 0x01) << 1) | + (v0 & 0x01) ; + + d[1] = ((v7 & 0x02) << 6) | + ((v6 & 0x02) << 5) | + ((v5 & 0x02) << 4) | + ((v4 & 0x02) << 3) | + ((v3 & 0x02) << 2) | + ((v2 & 0x02) << 1) | + ((v1 & 0x02) << 0) | + ((v0 & 0x02) >> 1) ; + + d[2] = ((v7 & 0x04) << 5) | + ((v6 & 0x04) << 4) | + ((v5 & 0x04) << 3) | + ((v4 & 0x04) << 2) | + ((v3 & 0x04) << 1) | + (v2 & 0x04) | + ((v1 & 0x04) >> 1) | + ((v0 & 0x04) >> 2) ; + + d[3] = ((v7 & 0x08) << 4) | + ((v6 & 0x08) << 3) | + ((v5 & 0x08) << 2) | + ((v4 & 0x08) << 1) | + (v3 & 0x08) | + ((v2 & 0x08) >> 1) | + ((v1 & 0x08) >> 2) | + ((v0 & 0x08) >> 3) ; + + d[4] = ((v7 & 0x10) << 3) | + ((v6 & 0x10) << 2) | + ((v5 & 0x10) << 1) | + (v4 & 0x10) | + ((v3 & 0x10) >> 1) | + ((v2 & 0x10) >> 2) | + ((v1 & 0x10) >> 3) | + ((v0 & 0x10) >> 4) ; + + d[5] = ((v7 & 0x20) << 2) | + ((v6 & 0x20) << 1) | + (v5 & 0x20) | + ((v4 & 0x20) >> 1) | + ((v3 & 0x20) >> 2) | + ((v2 & 0x20) >> 3) | + ((v1 & 0x20) >> 4) | + ((v0 & 0x20) >> 5) ; + + d[6] = ((v7 & 0x40) << 1) | + (v6 & 0x40) | + ((v5 & 0x40) >> 1) | + ((v4 & 0x40) >> 2) | + ((v3 & 0x40) >> 3) | + ((v2 & 0x40) >> 4) | + ((v1 & 0x40) >> 5) | + ((v0 & 0x40) >> 6) ; + + d[7] = (v7 & 0x80) | + ((v6 & 0x80) >> 1) | + ((v5 & 0x80) >> 2) | + ((v4 & 0x80) >> 3) | + ((v3 & 0x80) >> 4) | + ((v2 & 0x80) >> 5) | + ((v1 & 0x80) >> 6) | + ((v0 & 0x80) >> 7) ; + + d += 8; + s--; + } + } + + /* and now output only the differences */ + for (i = 0; i < LCD_PAGES; i++) { + + b = &hw_screen[i][0]; + e = &hw_screen[i][LCD_COLUMNS]; + + d = &last_hw_screen[i][0]; + s = b; + + last_page = -1; + + /* update only the differences */ + do { + while (s < e && *s == *d) { + s++; + d++; + } + if (s == e) + break; + r = s; + while (s < e && *s != *d) + *d++ = *s++; + + j = r - b; + + if (i != last_page) { + sed156x_cmd_transfer(LCD_PADDR | i); + last_page = i; + } + + sed156x_cmd_transfer(LCD_CADRH | ((j >> 4) & 0x0F)); + sed156x_cmd_transfer(LCD_CADRL | (j & 0x0F)); + sed156x_data_block_transfer(r, s - r); + + } while (s < e); + } + +/******** + for (i = 0; i < LCD_PAGES; i++) { + sed156x_cmd_transfer(LCD_PADDR | i); + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS); + } + memcpy(last_hw_screen, hw_screen, sizeof(last_hw_screen)); +********/ +} + +void sed156x_clear(void) +{ + memset(sw_screen, 0, sizeof(sw_screen)); +} + +void sed156x_output_at(int x, int y, const char *str, int size) +{ + int i, j; + u8 *p; + const u8 *s; + + if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH) + return; + + p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH]; + + while (--size >= 0) { + + s = &video_fontdata[((int)*str++ & 0xff) * VIDEO_FONT_BYTE_WIDTH * VIDEO_FONT_HEIGHT]; + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++) + *p++ = *s++; + p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH; + } + p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH); + + if (x >= LCD_TEXT_WIDTH) + break; + x++; + } +} + +void sed156x_reverse_at(int x, int y, int size) +{ + int i, j; + u8 *p; + + if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH) + return; + + p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH]; + + while (--size >= 0) { + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++, p++) + *p = ~*p; + p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH; + } + p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH); + + if (x >= LCD_TEXT_WIDTH) + break; + x++; + } +} + +void sed156x_scroll_line(void) +{ + memmove(&sw_screen[0], + &sw_screen[LCD_BYTE_LINESZ], + LCD_BYTE_WIDTH * (LCD_HEIGHT - VIDEO_FONT_HEIGHT)); +} + +void sed156x_scroll(int dx, int dy) +{ + u8 *p1 = NULL, *p2 = NULL, *p3 = NULL; /* pacify gcc */ + int adx, ady, i, sz; + + adx = dx > 0 ? dx : -dx; + ady = dy > 0 ? dy : -dy; + + /* overscroll? erase everything */ + if (adx >= LCD_TEXT_WIDTH || ady >= LCD_TEXT_HEIGHT) { + memset(sw_screen, 0, sizeof(sw_screen)); + return; + } + + sz = LCD_BYTE_LINESZ * ady; + if (dy > 0) { + p1 = &sw_screen[0]; + p2 = &sw_screen[sz]; + p3 = &sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT - sz]; + } else if (dy < 0) { + p1 = &sw_screen[sz]; + p2 = &sw_screen[0]; + p3 = &sw_screen[0]; + } + + if (ady > 0) { + memmove(p1, p2, LCD_BYTE_WIDTH * LCD_HEIGHT - sz); + memset(p3, 0, sz); + } + + sz = VIDEO_FONT_BYTE_WIDTH * adx; + if (dx > 0) { + p1 = &sw_screen[0]; + p2 = &sw_screen[0] + sz; + p3 = &sw_screen[0] + LCD_BYTE_WIDTH - sz; + } else if (dx < 0) { + p1 = &sw_screen[0] + sz; + p2 = &sw_screen[0]; + p3 = &sw_screen[0]; + } + + /* xscroll */ + if (adx > 0) { + for (i = 0; i < LCD_HEIGHT; i++) { + memmove(p1, p2, LCD_BYTE_WIDTH - sz); + memset(p3, 0, sz); + p1 += LCD_BYTE_WIDTH; + p2 += LCD_BYTE_WIDTH; + p3 += LCD_BYTE_WIDTH; + } + } +} + +void sed156x_init(void) +{ + int i; + + SED156X_CS(1); + SED156X_A0(1); + + /* Send initialization commands to the LCD */ + sed156x_cmd_transfer(LCD_OFF); /* Turn display OFF */ + sed156x_cmd_transfer(LCD_BIAS); /* set the LCD Bias, */ + sed156x_cmd_transfer(LCD_ADCMODE); /* ADC mode, */ + sed156x_cmd_transfer(LCD_COMDIR); /* common output mode, */ + sed156x_cmd_transfer(LCD_RESRT | LCD_RRATIO); /* resistor ratio, */ + sed156x_cmd_transfer(LCD_EVSET); /* electronic volume, */ + sed156x_cmd_transfer(LCD_CNTRST); + sed156x_cmd_transfer(LCD_PWRMD | LCD_POWERM); /* and power mode */ + sed156x_cmd_transfer(LCD_PADDR | 0); /* cursor home */ + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_cmd_transfer(LCD_LADDR | 0); /* and display start line */ + sed156x_cmd_transfer(LCD_DSP_NRM); /* LCD display Normal */ + + /* clear everything */ + memset(sw_screen, 0, sizeof(sw_screen)); + memset(hw_screen, 0, sizeof(hw_screen)); + memset(last_hw_screen, 0, sizeof(last_hw_screen)); + + for (i = 0; i < LCD_PAGES; i++) { + sed156x_cmd_transfer(LCD_PADDR | i); + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS); + } + + sed156x_clear(); + sed156x_sync(); + sed156x_cmd_transfer(LCD_ON); /* Turn display ON */ +} + +#endif /* CONFIG_SED156X */ diff --git a/drivers/serial.c b/drivers/serial.c new file mode 100644 index 0000000..057a1ab --- /dev/null +++ b/drivers/serial.c @@ -0,0 +1,214 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_NS16550_SERIAL + +#include +#ifdef CFG_NS87308 +#include +#endif + +#if !defined(CONFIG_CONS_INDEX) +#error "No console index specified." +#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4) +#error "Invalid console index value." +#endif + +#if CONFIG_CONS_INDEX == 1 && !defined(CFG_NS16550_COM1) +#error "Console port 1 defined but not configured." +#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_NS16550_COM2) +#error "Console port 2 defined but not configured." +#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_NS16550_COM3) +#error "Console port 3 defined but not configured." +#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_NS16550_COM4) +#error "Console port 4 defined but not configured." +#endif + +/* Note: The port number specified in the functions is 1 based. + * the array is 0 based. + */ +static NS16550_t serial_ports[4] = { +#ifdef CFG_NS16550_COM1 + (NS16550_t)CFG_NS16550_COM1, +#else + NULL, +#endif +#ifdef CFG_NS16550_COM2 + (NS16550_t)CFG_NS16550_COM2, +#else + NULL, +#endif +#ifdef CFG_NS16550_COM3 + (NS16550_t)CFG_NS16550_COM3, +#else + NULL, +#endif +#ifdef CFG_NS16550_COM4 + (NS16550_t)CFG_NS16550_COM4 +#else + NULL +#endif +}; + +#define PORT serial_ports[port-1] +#define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1]) + +static int calc_divisor (NS16550_t port) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_OMAP1510 + /* If can't cleanly clock 115200 set div to 1 */ + if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) { + port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ + return (1); /* return 1 for base divisor */ + } + port->osc_12m_sel = 0; /* clear if previsouly set */ +#endif +#ifdef CONFIG_OMAP1610 + /* If can't cleanly clock 115200 set div to 1 */ + if ((CFG_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) { + return (26); /* return 26 for base divisor */ + } +#endif + +#ifdef CONFIG_APTIX +#define MODE_X_DIV 13 +#else +#define MODE_X_DIV 16 +#endif + return (CFG_NS16550_CLK / MODE_X_DIV / gd->baudrate); + +} + +int serial_init (void) +{ + int clock_divisor; + +#ifdef CFG_NS87308 + initialise_ns87308(); +#endif + +#ifdef CFG_NS16550_COM1 + clock_divisor = calc_divisor(serial_ports[0]); + NS16550_init(serial_ports[0], clock_divisor); +#endif +#ifdef CFG_NS16550_COM2 + clock_divisor = calc_divisor(serial_ports[1]); + NS16550_init(serial_ports[1], clock_divisor); +#endif +#ifdef CFG_NS16550_COM3 + clock_divisor = calc_divisor(serial_ports[2]); + NS16550_init(serial_ports[2], clock_divisor); +#endif +#ifdef CFG_NS16550_COM4 + clock_divisor = calc_divisor(serial_ports[3]); + NS16550_init(serial_ports[3], clock_divisor); +#endif + + return (0); +} + +void +_serial_putc(const char c,const int port) +{ + if (c == '\n') + NS16550_putc(PORT, '\r'); + + NS16550_putc(PORT, c); +} + +void +_serial_putc_raw(const char c,const int port) +{ + NS16550_putc(PORT, c); +} + +void +_serial_puts (const char *s,const int port) +{ + while (*s) { + _serial_putc (*s++,port); + } +} + + +int +_serial_getc(const int port) +{ + return NS16550_getc(PORT); +} + +int +_serial_tstc(const int port) +{ + return NS16550_tstc(PORT); +} + +void +_serial_setbrg (const int port) +{ + int clock_divisor; + + clock_divisor = calc_divisor(PORT); + NS16550_reinit(PORT, clock_divisor); +} + +void +serial_putc(const char c) +{ + _serial_putc(c,CONFIG_CONS_INDEX); +} + +void +serial_putc_raw(const char c) +{ + _serial_putc_raw(c,CONFIG_CONS_INDEX); +} + +void +serial_puts(const char *s) +{ + _serial_puts(s,CONFIG_CONS_INDEX); +} + +int +serial_getc(void) +{ + return _serial_getc(CONFIG_CONS_INDEX); +} + +int +serial_tstc(void) +{ + return _serial_tstc(CONFIG_CONS_INDEX); +} + +void +serial_setbrg(void) +{ + _serial_setbrg(CONFIG_CONS_INDEX); +} + +#endif diff --git a/drivers/serial_max3100.c b/drivers/serial_max3100.c new file mode 100644 index 0000000..bbe212b --- /dev/null +++ b/drivers/serial_max3100.c @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2003 + * + * Pantelis Antoniou + * Intracom S.A. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_MAX3100_SERIAL + +/**************************************************************/ + +/* convienient macros */ +#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT) + +#define MAX3100_SPI_TXD(x) \ + do { \ + if (x) \ + MAX3100_SPI_TXD_PORT |= MAX3100_SPI_TXD_BIT; \ + else \ + MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \ + } while(0) + +#define MAX3100_SPI_CLK(x) \ + do { \ + if (x) \ + MAX3100_SPI_CLK_PORT |= MAX3100_SPI_CLK_BIT; \ + else \ + MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \ + } while(0) + +#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT) + +#define MAX3100_CS(x) \ + do { \ + if (x) \ + MAX3100_CS_PORT |= MAX3100_CS_BIT; \ + else \ + MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \ + } while(0) + +/**************************************************************/ + +/* MAX3100 definitions */ + +#define MAX3100_WC (3 << 14) /* write configuration */ +#define MAX3100_RC (1 << 14) /* read configuration */ +#define MAX3100_WD (2 << 14) /* write data */ +#define MAX3100_RD (0 << 14) /* read data */ + +/* configuration register bits */ +#define MAX3100_FEN (1 << 13) /* FIFO enable */ +#define MAX3100_SHDN (1 << 12) /* shutdown bit */ +#define MAX3100_TM (1 << 11) /* T bit irq mask */ +#define MAX3100_RM (1 << 10) /* R bit irq mask */ +#define MAX3100_PM (1 << 9) /* P bit irq mask */ +#define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */ +#define MAX3100_IR (1 << 7) /* IRDA timing mode */ +#define MAX3100_ST (1 << 6) /* transmit stop bit */ +#define MAX3100_PE (1 << 5) /* parity enable bit */ +#define MAX3100_L (1 << 4) /* Length bit */ +#define MAX3100_B_MASK (0x000F) /* baud rate bits mask */ +#define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */ + +/* data register bits (write) */ +#define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */ +#define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */ + +/* data register bits (read) */ +#define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */ +#define MAX3100_FE (1 << 10) /* framing error when in normal mode */ +#define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */ + +/* data register bits (both directions) */ +#define MAX3100_R (1 << 15) /* receive bit */ +#define MAX3100_T (1 << 14) /* transmit bit */ +#define MAX3100_P (1 << 8) /* parity bit */ +#define MAX3100_D_MASK 0x00FF /* data bits mask */ +#define MAX3100_D(x) ((x) & 0x00FF) /* data bits */ + +/* these definitions are valid only for fOSC = 3.6864MHz */ +#define MAX3100_B_230400 MAX3100_B(0) +#define MAX3100_B_115200 MAX3100_B(1) +#define MAX3100_B_57600 MAX3100_B(2) +#define MAX3100_B_38400 MAX3100_B(9) +#define MAX3100_B_19200 MAX3100_B(10) +#define MAX3100_B_9600 MAX3100_B(11) +#define MAX3100_B_4800 MAX3100_B(12) +#define MAX3100_B_2400 MAX3100_B(13) +#define MAX3100_B_1200 MAX3100_B(14) +#define MAX3100_B_600 MAX3100_B(15) + +/**************************************************************/ + +static inline unsigned int max3100_transfer(unsigned int val) +{ + unsigned int rx; + int b; + + MAX3100_SPI_CLK(0); + MAX3100_CS(0); + + rx = 0; b = 16; + while (--b >= 0) { + MAX3100_SPI_TXD(val & 0x8000); + val <<= 1; + MAX3100_SPI_CLK_TOGGLE(); + udelay(1); + rx <<= 1; + if (MAX3100_SPI_RXD()) + rx |= 1; + MAX3100_SPI_CLK_TOGGLE(); + udelay(1); + } + + MAX3100_SPI_CLK(1); + MAX3100_CS(1); + + return rx; +} + +/**************************************************************/ + +/* must be power of 2 */ +#define RXFIFO_SZ 16 + +static int rxfifo_cnt; +static int rxfifo_in; +static int rxfifo_out; +static unsigned char rxfifo_buf[16]; + +static void max3100_putc(int c) +{ + unsigned int rx; + + while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0) + WATCHDOG_RESET(); + + rx = max3100_transfer(MAX3100_WD | (c & 0xff)); + if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) { + rxfifo_cnt++; + rxfifo_buf[rxfifo_in++] = rx & 0xff; + rxfifo_in &= RXFIFO_SZ - 1; + } +} + +static int max3100_getc(void) +{ + int c; + unsigned int rx; + + while (rxfifo_cnt == 0) { + rx = max3100_transfer(MAX3100_RD); + if ((rx & MAX3100_R) != 0) { + do { + rxfifo_cnt++; + rxfifo_buf[rxfifo_in++] = rx & 0xff; + rxfifo_in &= RXFIFO_SZ - 1; + + if (rxfifo_cnt >= RXFIFO_SZ) + break; + } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0); + } + WATCHDOG_RESET(); + } + + rxfifo_cnt--; + c = rxfifo_buf[rxfifo_out++]; + rxfifo_out &= RXFIFO_SZ - 1; + return c; +} + +static int max3100_tstc(void) +{ + unsigned int rx; + + if (rxfifo_cnt > 0) + return 1; + + rx = max3100_transfer(MAX3100_RD); + if ((rx & MAX3100_R) == 0) + return 0; + + do { + rxfifo_cnt++; + rxfifo_buf[rxfifo_in++] = rx & 0xff; + rxfifo_in &= RXFIFO_SZ - 1; + + if (rxfifo_cnt >= RXFIFO_SZ) + break; + } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0); + + return 1; +} + +int serial_init(void) +{ + unsigned int wconf, rconf; + int i; + DECLARE_GLOBAL_DATA_PTR; + + wconf = 0; + + /* Set baud rate */ + switch (gd->baudrate) { + case 1200: + wconf = MAX3100_B_1200; + break; + case 2400: + wconf = MAX3100_B_2400; + break; + case 4800: + wconf = MAX3100_B_4800; + break; + case 9600: + wconf = MAX3100_B_9600; + break; + case 19200: + wconf = MAX3100_B_19200; + break; + case 38400: + wconf = MAX3100_B_38400; + break; + case 57600: + wconf = MAX3100_B_57600; + break; + default: + case 115200: + wconf = MAX3100_B_115200; + break; + case 230400: + wconf = MAX3100_B_230400; + break; + } + + /* try for 10ms, with a 100us gap */ + for (i = 0; i < 10000; i += 100) { + + max3100_transfer(MAX3100_WC | wconf); + rconf = max3100_transfer(MAX3100_RC) & 0x3fff; + + if (rconf == wconf) + break; + udelay(100); + } + + rxfifo_in = rxfifo_out = rxfifo_cnt = 0; + + return (0); +} + +void serial_putc(const char c) +{ + if (c == '\n') + max3100_putc('\r'); + + max3100_putc(c); +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc (*s++); +} + +int serial_getc(void) +{ + return max3100_getc(); +} + +int serial_tstc(void) +{ + return max3100_tstc(); +} + +/* XXX WTF? */ +void serial_setbrg(void) +{ +} + +#endif diff --git a/drivers/serial_pl010.c b/drivers/serial_pl010.c new file mode 100644 index 0000000..417b6ae --- /dev/null +++ b/drivers/serial_pl010.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ +/* Should be fairly simple to make it work with the PL010 as well */ + +#include + +#ifdef CFG_PL010_SERIAL + +#include "serial_pl011.h" + +#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(volatile unsigned int *)(addr)) + +/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */ +#define CONSOLE_PORT CONFIG_CONS_INDEX +#define baudRate CONFIG_BAUDRATE +static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +#define NUM_PORTS (sizeof(port)/sizeof(port[0])) + + +static void pl010_putc (int portnum, char c); +static int pl010_getc (int portnum); +static int pl010_tstc (int portnum); + + +int serial_init (void) +{ + unsigned int divisor; + + /* + ** First, disable everything. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); + + /* + ** Set baud rate + ** + */ + switch (baudRate) { + case 9600: + divisor = UART_PL010_BAUD_9600; + break; + + case 19200: + divisor = UART_PL010_BAUD_9600; + break; + + case 38400: + divisor = UART_PL010_BAUD_38400; + break; + + case 57600: + divisor = UART_PL010_BAUD_57600; + break; + + case 115200: + divisor = UART_PL010_BAUD_115200; + break; + + default: + divisor = UART_PL010_BAUD_38400; + } + + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, + ((divisor & 0xf00) >> 8)); + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); + + /* + ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, + (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); + + /* + ** Finally, enable the UART + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); + + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') + pl010_putc (CONSOLE_PORT, '\r'); + + pl010_putc (CONSOLE_PORT, c); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + return pl010_getc (CONSOLE_PORT); +} + +int serial_tstc (void) +{ + return pl010_tstc (CONSOLE_PORT); +} + +void serial_setbrg (void) +{ +} + +static void pl010_putc (int portnum, char c) +{ + /* Wait until there is space in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + + /* Send the character */ + IO_WRITE (port[portnum] + UART_PL01x_DR, c); +} + +static int pl010_getc (int portnum) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + + data = IO_READ (port[portnum] + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + return -1; + } + + return (int) data; +} + +static int pl010_tstc (int portnum) +{ + return !(IO_READ (port[portnum] + UART_PL01x_FR) & + UART_PL01x_FR_RXFE); +} + +#endif diff --git a/drivers/serial_pl011.c b/drivers/serial_pl011.c new file mode 100644 index 0000000..4d35fe5 --- /dev/null +++ b/drivers/serial_pl011.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ +/* Should be fairly simple to make it work with the PL010 as well */ + +#include + +#ifdef CFG_PL011_SERIAL + +#include "serial_pl011.h" + +#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(volatile unsigned int *)(addr)) + +/* + * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1 + * Versatile PB has four UARTs. + */ + +#define CONSOLE_PORT CONFIG_CONS_INDEX +#define baudRate CONFIG_BAUDRATE +static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +#define NUM_PORTS (sizeof(port)/sizeof(port[0])) + +static void pl011_putc (int portnum, char c); +static int pl011_getc (int portnum); +static int pl011_tstc (int portnum); + + +int serial_init (void) +{ + unsigned int temp; + unsigned int divider; + unsigned int remainder; + unsigned int fraction; + + /* + ** First, disable everything. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); + + /* + ** Set baud rate + ** + ** IBRD = UART_CLK / (16 * BAUD_RATE) + ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) + */ + temp = 16 * baudRate; + divider = CONFIG_PL011_CLOCK / temp; + remainder = CONFIG_PL011_CLOCK % temp; + temp = (8 * remainder) / baudRate; + fraction = (temp >> 1) + (temp & 1); + + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); + + /* + ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, + (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); + + /* + ** Finally, enable the UART + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, + (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | + UART_PL011_CR_RXE)); + + return 0; +} + +void serial_putc (const char c) +{ + if (c == '\n') + pl011_putc (CONSOLE_PORT, '\r'); + + pl011_putc (CONSOLE_PORT, c); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + return pl011_getc (CONSOLE_PORT); +} + +int serial_tstc (void) +{ + return pl011_tstc (CONSOLE_PORT); +} + +void serial_setbrg (void) +{ +} + +static void pl011_putc (int portnum, char c) +{ + /* Wait until there is space in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + + /* Send the character */ + IO_WRITE (port[portnum] + UART_PL01x_DR, c); +} + +static int pl011_getc (int portnum) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + + data = IO_READ (port[portnum] + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + return -1; + } + + return (int) data; +} + +static int pl011_tstc (int portnum) +{ + return !(IO_READ (port[portnum] + UART_PL01x_FR) & + UART_PL01x_FR_RXFE); +} + +#endif diff --git a/drivers/serial_pl011.h b/drivers/serial_pl011.h new file mode 100644 index 0000000..5f20fdd --- /dev/null +++ b/drivers/serial_pl011.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2003, 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * ARM PrimeCell UART's (PL010 & PL011) + * ------------------------------------ + * + * Definitions common to both PL010 & PL011 + * + */ +#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ +#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ +#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ +#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ + +#define UART_PL01x_RSR_OE 0x08 +#define UART_PL01x_RSR_BE 0x04 +#define UART_PL01x_RSR_PE 0x02 +#define UART_PL01x_RSR_FE 0x01 + +#define UART_PL01x_FR_TXFE 0x80 +#define UART_PL01x_FR_RXFF 0x40 +#define UART_PL01x_FR_TXFF 0x20 +#define UART_PL01x_FR_RXFE 0x10 +#define UART_PL01x_FR_BUSY 0x08 +#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) + +/* + * PL010 definitions + * + */ +#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ +#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ +#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ +#define UART_PL010_CR 0x14 /* Control register. */ +#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ +#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ +#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ + +#define UART_PL010_CR_LPE (1 << 7) +#define UART_PL010_CR_RTIE (1 << 6) +#define UART_PL010_CR_TIE (1 << 5) +#define UART_PL010_CR_RIE (1 << 4) +#define UART_PL010_CR_MSIE (1 << 3) +#define UART_PL010_CR_IIRLP (1 << 2) +#define UART_PL010_CR_SIREN (1 << 1) +#define UART_PL010_CR_UARTEN (1 << 0) + +#define UART_PL010_LCRH_WLEN_8 (3 << 5) +#define UART_PL010_LCRH_WLEN_7 (2 << 5) +#define UART_PL010_LCRH_WLEN_6 (1 << 5) +#define UART_PL010_LCRH_WLEN_5 (0 << 5) +#define UART_PL010_LCRH_FEN (1 << 4) +#define UART_PL010_LCRH_STP2 (1 << 3) +#define UART_PL010_LCRH_EPS (1 << 2) +#define UART_PL010_LCRH_PEN (1 << 1) +#define UART_PL010_LCRH_BRK (1 << 0) + + +#define UART_PL010_BAUD_460800 1 +#define UART_PL010_BAUD_230400 3 +#define UART_PL010_BAUD_115200 7 +#define UART_PL010_BAUD_57600 15 +#define UART_PL010_BAUD_38400 23 +#define UART_PL010_BAUD_19200 47 +#define UART_PL010_BAUD_14400 63 +#define UART_PL010_BAUD_9600 95 +#define UART_PL010_BAUD_4800 191 +#define UART_PL010_BAUD_2400 383 +#define UART_PL010_BAUD_1200 767 +/* + * PL011 definitions + * + */ +#define UART_PL011_IBRD 0x24 +#define UART_PL011_FBRD 0x28 +#define UART_PL011_LCRH 0x2C +#define UART_PL011_CR 0x30 +#define UART_PL011_IMSC 0x38 +#define UART_PL011_PERIPH_ID0 0xFE0 + +#define UART_PL011_LCRH_SPS (1 << 7) +#define UART_PL011_LCRH_WLEN_8 (3 << 5) +#define UART_PL011_LCRH_WLEN_7 (2 << 5) +#define UART_PL011_LCRH_WLEN_6 (1 << 5) +#define UART_PL011_LCRH_WLEN_5 (0 << 5) +#define UART_PL011_LCRH_FEN (1 << 4) +#define UART_PL011_LCRH_STP2 (1 << 3) +#define UART_PL011_LCRH_EPS (1 << 2) +#define UART_PL011_LCRH_PEN (1 << 1) +#define UART_PL011_LCRH_BRK (1 << 0) + +#define UART_PL011_CR_CTSEN (1 << 15) +#define UART_PL011_CR_RTSEN (1 << 14) +#define UART_PL011_CR_OUT2 (1 << 13) +#define UART_PL011_CR_OUT1 (1 << 12) +#define UART_PL011_CR_RTS (1 << 11) +#define UART_PL011_CR_DTR (1 << 10) +#define UART_PL011_CR_RXE (1 << 9) +#define UART_PL011_CR_TXE (1 << 8) +#define UART_PL011_CR_LPE (1 << 7) +#define UART_PL011_CR_IIRLP (1 << 2) +#define UART_PL011_CR_SIREN (1 << 1) +#define UART_PL011_CR_UARTEN (1 << 0) + +#define UART_PL011_IMSC_OEIM (1 << 10) +#define UART_PL011_IMSC_BEIM (1 << 9) +#define UART_PL011_IMSC_PEIM (1 << 8) +#define UART_PL011_IMSC_FEIM (1 << 7) +#define UART_PL011_IMSC_RTIM (1 << 6) +#define UART_PL011_IMSC_TXIM (1 << 5) +#define UART_PL011_IMSC_RXIM (1 << 4) +#define UART_PL011_IMSC_DSRMIM (1 << 3) +#define UART_PL011_IMSC_DCDMIM (1 << 2) +#define UART_PL011_IMSC_CTSMIM (1 << 1) +#define UART_PL011_IMSC_RIMIM (1 << 0) diff --git a/drivers/serial_xuartlite.c b/drivers/serial_xuartlite.c new file mode 100644 index 0000000..ed59abe --- /dev/null +++ b/drivers/serial_xuartlite.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_MICROBLAZE + +#include + +/* FIXME: we should convert these to in32 and out32 */ +#define IO_WORD(offset) (*(volatile unsigned long *)(offset)) +#define IO_SERIAL(offset) IO_WORD(CONFIG_SERIAL_BASE + (offset)) + +#define IO_SERIAL_RX_FIFO IO_SERIAL(XUL_RX_FIFO_OFFSET) +#define IO_SERIAL_TX_FIFO IO_SERIAL(XUL_TX_FIFO_OFFSET) +#define IO_SERIAL_STATUS IO_SERIAL(XUL_STATUS_REG_OFFSET) +#define IO_SERIAL_CONTROL IO_SERIAL(XUL_CONTROL_REG_OFFSET) + +int serial_init(void) +{ + /* FIXME: Nothing for now. We should initialize fifo, etc */ + return 0; +} + +void serial_setbrg(void) +{ + /* FIXME: what's this for? */ +} + +void serial_putc(const char c) +{ + if (c == '\n') serial_putc('\r'); + while (IO_SERIAL_STATUS & XUL_SR_TX_FIFO_FULL); + IO_SERIAL_TX_FIFO = (unsigned char) (c & 0xff); +} + +void serial_puts(const char * s) +{ + while (*s) { + serial_putc(*s++); + } +} + +int serial_getc(void) +{ + while (!(IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA)); + return IO_SERIAL_RX_FIFO & 0xff; +} + +int serial_tstc(void) +{ + return (IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA); +} + +#endif /* CONFIG_MICROBLZE */ diff --git a/drivers/sk98lin/Makefile b/drivers/sk98lin/Makefile new file mode 100644 index 0000000..8ee0e21 --- /dev/null +++ b/drivers/sk98lin/Makefile @@ -0,0 +1,101 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# File: drivers/sk98lin/Makefile +# +# Makefile for the SysKonnect SK-98xx device driver. +# +include $(TOPDIR)/config.mk + +LIB := libsk98lin.a + +OBJS := skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \ + ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \ + skxmac2.o skcsum.o #skproc.o + +OBJS += uboot_skb.o uboot_drv.o + +# DBGDEF = \ +# -DDEBUG + +ifdef DEBUG +DBGDEF += \ +-DSK_DEBUG_CHKMOD=0x00000000L \ +-DSK_DEBUG_CHKCAT=0x00000000L +endif + + +# **** possible debug modules for SK_DEBUG_CHKMOD ***************** +# SK_DBGMOD_MERR 0x00000001L /* general module error indication */ +# SK_DBGMOD_HWM 0x00000002L /* Hardware init module */ +# SK_DBGMOD_RLMT 0x00000004L /* RLMT module */ +# SK_DBGMOD_VPD 0x00000008L /* VPD module */ +# SK_DBGMOD_I2C 0x00000010L /* I2C module */ +# SK_DBGMOD_PNMI 0x00000020L /* PNMI module */ +# SK_DBGMOD_CSUM 0x00000040L /* CSUM module */ +# SK_DBGMOD_ADDR 0x00000080L /* ADDR module */ +# SK_DBGMOD_DRV 0x00010000L /* DRV module */ + +# **** possible debug categories for SK_DEBUG_CHKCAT ************** +# *** common modules *** +# SK_DBGCAT_INIT 0x00000001L module/driver initialization +# SK_DBGCAT_CTRL 0x00000002L controlling: add/rmv MCA/MAC and other controls (IOCTL) +# SK_DBGCAT_ERR 0x00000004L error handling paths +# SK_DBGCAT_TX 0x00000008L transmit path +# SK_DBGCAT_RX 0x00000010L receive path +# SK_DBGCAT_IRQ 0x00000020L general IRQ handling +# SK_DBGCAT_QUEUE 0x00000040L any queue management +# SK_DBGCAT_DUMP 0x00000080L large data output e.g. hex dump +# SK_DBGCAT_FATAL 0x00000100L large data output e.g. hex dump + +# *** driver (file skge.c) *** +# SK_DBGCAT_DRV_ENTRY 0x00010000 entry points +# SK_DBGCAT_DRV_??? 0x00020000 not used +# SK_DBGCAT_DRV_MCA 0x00040000 multicast +# SK_DBGCAT_DRV_TX_PROGRESS 0x00080000 tx path +# SK_DBGCAT_DRV_RX_PROGRESS 0x00100000 rx path +# SK_DBGCAT_DRV_PROGRESS 0x00200000 general runtime +# SK_DBGCAT_DRV_??? 0x00400000 not used +# SK_DBGCAT_DRV_PROM 0x00800000 promiscuous mode +# SK_DBGCAT_DRV_TX_FRAME 0x01000000 display tx frames +# SK_DBGCAT_DRV_ERROR 0x02000000 error conditions +# SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources +# SK_DBGCAT_DRV_EVENT 0x08000000 driver events + +EXTRA_CFLAGS += -I. -DSK_USE_CSUM $(DBGDEF) + +CFLAGS += $(EXTRA_CFLAGS) + + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/drivers/sk98lin/h/lm80.h b/drivers/sk98lin/h/lm80.h new file mode 100644 index 0000000..981a4ca --- /dev/null +++ b/drivers/sk98lin/h/lm80.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * + * Name: lm80.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.4 $ + * Date: $Date: 2002/04/25 11:04:10 $ + * Purpose: Contains all defines for the LM80 Chip + * (National Semiconductor). + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: lm80.h,v $ + * Revision 1.4 2002/04/25 11:04:10 rschmidt + * Editorial changes + * + * Revision 1.3 1999/11/22 13:41:19 cgoos + * Changed license header to GPL. + * + * Revision 1.2 1999/03/12 13:26:51 malthoff + * remove __STDC__. + * + * Revision 1.1 1998/06/19 09:28:31 malthoff + * created. + * + * + ******************************************************************************/ + +#ifndef __INC_LM80_H +#define __INC_LM80_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines ********************************************************************/ + +/* + * LM80 register definition + * + * All registers are 8 bit wide + */ +#define LM80_CFG 0x00 /* Configuration Register */ +#define LM80_ISRC_1 0x01 /* Interrupt Status Register 1 */ +#define LM80_ISRC_2 0x02 /* Interrupt Status Register 2 */ +#define LM80_IMSK_1 0x03 /* Interrupt Mask Register 1 */ +#define LM80_IMSK_2 0x04 /* Interrupt Mask Register 2 */ +#define LM80_FAN_CTRL 0x05 /* Fan Devisor/RST#/OS# Register */ +#define LM80_TEMP_CTRL 0x06 /* OS# Config, Temp Res. Reg */ + /* 0x07 - 0x1f reserved */ + /* current values */ +#define LM80_VT0_IN 0x20 /* current Voltage 0 value */ +#define LM80_VT1_IN 0x21 /* current Voltage 1 value */ +#define LM80_VT2_IN 0x22 /* current Voltage 2 value */ +#define LM80_VT3_IN 0x23 /* current Voltage 3 value */ +#define LM80_VT4_IN 0x24 /* current Voltage 4 value */ +#define LM80_VT5_IN 0x25 /* current Voltage 5 value */ +#define LM80_VT6_IN 0x26 /* current Voltage 6 value */ +#define LM80_TEMP_IN 0x27 /* current Temperature value */ +#define LM80_FAN1_IN 0x28 /* current Fan 1 count */ +#define LM80_FAN2_IN 0x29 /* current Fan 2 count */ + /* limit values */ +#define LM80_VT0_HIGH_LIM 0x2a /* high limit val for Voltage 0 */ +#define LM80_VT0_LOW_LIM 0x2b /* low limit val for Voltage 0 */ +#define LM80_VT1_HIGH_LIM 0x2c /* high limit val for Voltage 1 */ +#define LM80_VT1_LOW_LIM 0x2d /* low limit val for Voltage 1 */ +#define LM80_VT2_HIGH_LIM 0x2e /* high limit val for Voltage 2 */ +#define LM80_VT2_LOW_LIM 0x2f /* low limit val for Voltage 2 */ +#define LM80_VT3_HIGH_LIM 0x30 /* high limit val for Voltage 3 */ +#define LM80_VT3_LOW_LIM 0x31 /* low limit val for Voltage 3 */ +#define LM80_VT4_HIGH_LIM 0x32 /* high limit val for Voltage 4 */ +#define LM80_VT4_LOW_LIM 0x33 /* low limit val for Voltage 4 */ +#define LM80_VT5_HIGH_LIM 0x34 /* high limit val for Voltage 5 */ +#define LM80_VT5_LOW_LIM 0x35 /* low limit val for Voltage 5 */ +#define LM80_VT6_HIGH_LIM 0x36 /* high limit val for Voltage 6 */ +#define LM80_VT6_LOW_LIM 0x37 /* low limit val for Voltage 6 */ +#define LM80_THOT_LIM_UP 0x38 /* hot temperature limit (high) */ +#define LM80_THOT_LIM_LO 0x39 /* hot temperature limit (low) */ +#define LM80_TOS_LIM_UP 0x3a /* OS temperature limit (high) */ +#define LM80_TOS_LIM_LO 0x3b /* OS temperature limit (low) */ +#define LM80_FAN1_COUNT_LIM 0x3c /* Fan 1 count limit (high) */ +#define LM80_FAN2_COUNT_LIM 0x3d /* Fan 2 count limit (low) */ + /* 0x3e - 0x3f reserved */ + +/* + * LM80 bit definitions + */ + +/* LM80_CFG Configuration Register */ +#define LM80_CFG_START (1<<0) /* start monitoring operation */ +#define LM80_CFG_INT_ENA (1<<1) /* enables the INT# Interrupt output */ +#define LM80_CFG_INT_POL (1<<2) /* INT# pol: 0 act low, 1 act high */ +#define LM80_CFG_INT_CLR (1<<3) /* disables INT#/RST_OUT#/OS# outputs */ +#define LM80_CFG_RESET (1<<4) /* signals a reset */ +#define LM80_CFG_CHASS_CLR (1<<5) /* clears Chassis Intrusion (CI) pin */ +#define LM80_CFG_GPO (1<<6) /* drives the GPO# pin */ +#define LM80_CFG_INIT (1<<7) /* restore power on defaults */ + +/* LM80_ISRC_1 Interrupt Status Register 1 */ +/* LM80_IMSK_1 Interrupt Mask Register 1 */ +#define LM80_IS_VT0 (1<<0) /* limit exceeded for Voltage 0 */ +#define LM80_IS_VT1 (1<<1) /* limit exceeded for Voltage 1 */ +#define LM80_IS_VT2 (1<<2) /* limit exceeded for Voltage 2 */ +#define LM80_IS_VT3 (1<<3) /* limit exceeded for Voltage 3 */ +#define LM80_IS_VT4 (1<<4) /* limit exceeded for Voltage 4 */ +#define LM80_IS_VT5 (1<<5) /* limit exceeded for Voltage 5 */ +#define LM80_IS_VT6 (1<<6) /* limit exceeded for Voltage 6 */ +#define LM80_IS_INT_IN (1<<7) /* state of INT_IN# */ + +/* LM80_ISRC_2 Interrupt Status Register 2 */ +/* LM80_IMSK_2 Interrupt Mask Register 2 */ +#define LM80_IS_TEMP (1<<0) /* HOT temperature limit exceeded */ +#define LM80_IS_BTI (1<<1) /* state of BTI# pin */ +#define LM80_IS_FAN1 (1<<2) /* count limit exceeded for Fan 1 */ +#define LM80_IS_FAN2 (1<<3) /* count limit exceeded for Fan 2 */ +#define LM80_IS_CI (1<<4) /* Chassis Intrusion occured */ +#define LM80_IS_OS (1<<5) /* OS temperature limit exceeded */ + /* bit 6 and 7 are reserved in LM80_ISRC_2 */ +#define LM80_IS_HT_IRQ_MD (1<<6) /* Hot temperature interrupt mode */ +#define LM80_IS_OT_IRQ_MD (1<<7) /* OS temperature interrupt mode */ + +/* LM80_FAN_CTRL Fan Devisor/RST#/OS# Register */ +#define LM80_FAN1_MD_SEL (1<<0) /* Fan 1 mode select */ +#define LM80_FAN2_MD_SEL (1<<1) /* Fan 2 mode select */ +#define LM80_FAN1_PRM_CTL (3<<2) /* Fan 1 speed control */ +#define LM80_FAN2_PRM_CTL (3<<4) /* Fan 2 speed control */ +#define LM80_FAN_OS_ENA (1<<6) /* enable OS mode on RST_OUT#/OS# pins*/ +#define LM80_FAN_RST_ENA (1<<7) /* sets RST_OUT#/OS# pins in RST mode */ + +/* LM80_TEMP_CTRL OS# Config, Temp Res. Reg */ +#define LM80_TEMP_OS_STAT (1<<0) /* mirrors the state of RST_OUT#/OS# */ +#define LM80_TEMP_OS_POL (1<<1) /* select OS# polarity */ +#define LM80_TEMP_OS_MODE (1<<2) /* selects Interrupt mode */ +#define LM80_TEMP_RES (1<<3) /* selects 9 or 11 bit temp resulution*/ +#define LM80_TEMP_LSB (0xf<<4)/* 4 LSBs of 11 bit temp data */ +#define LM80_TEMP_LSB_9 (1<<7) /* LSB of 9 bit temperature data */ + + /* 0x07 - 0x1f reserved */ +/* LM80_VT0_IN current Voltage 0 value */ +/* LM80_VT1_IN current Voltage 1 value */ +/* LM80_VT2_IN current Voltage 2 value */ +/* LM80_VT3_IN current Voltage 3 value */ +/* LM80_VT4_IN current Voltage 4 value */ +/* LM80_VT5_IN current Voltage 5 value */ +/* LM80_VT6_IN current Voltage 6 value */ +/* LM80_TEMP_IN current temperature value */ +/* LM80_FAN1_IN current Fan 1 count */ +/* LM80_FAN2_IN current Fan 2 count */ +/* LM80_VT0_HIGH_LIM high limit val for Voltage 0 */ +/* LM80_VT0_LOW_LIM low limit val for Voltage 0 */ +/* LM80_VT1_HIGH_LIM high limit val for Voltage 1 */ +/* LM80_VT1_LOW_LIM low limit val for Voltage 1 */ +/* LM80_VT2_HIGH_LIM high limit val for Voltage 2 */ +/* LM80_VT2_LOW_LIM low limit val for Voltage 2 */ +/* LM80_VT3_HIGH_LIM high limit val for Voltage 3 */ +/* LM80_VT3_LOW_LIM low limit val for Voltage 3 */ +/* LM80_VT4_HIGH_LIM high limit val for Voltage 4 */ +/* LM80_VT4_LOW_LIM low limit val for Voltage 4 */ +/* LM80_VT5_HIGH_LIM high limit val for Voltage 5 */ +/* LM80_VT5_LOW_LIM low limit val for Voltage 5 */ +/* LM80_VT6_HIGH_LIM high limit val for Voltage 6 */ +/* LM80_VT6_LOW_LIM low limit val for Voltage 6 */ +/* LM80_THOT_LIM_UP hot temperature limit (high) */ +/* LM80_THOT_LIM_LO hot temperature limit (low) */ +/* LM80_TOS_LIM_UP OS temperature limit (high) */ +/* LM80_TOS_LIM_LO OS temperature limit (low) */ +/* LM80_FAN1_COUNT_LIM Fan 1 count limit (high) */ +/* LM80_FAN2_COUNT_LIM Fan 2 count limit (low) */ + /* 0x3e - 0x3f reserved */ + +#define LM80_ADDR 0x28 /* LM80 default addr */ + +/* typedefs *******************************************************************/ + + +/* function prototypes ********************************************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_LM80_H */ diff --git a/drivers/sk98lin/h/skaddr.h b/drivers/sk98lin/h/skaddr.h new file mode 100644 index 0000000..711f873 --- /dev/null +++ b/drivers/sk98lin/h/skaddr.h @@ -0,0 +1,425 @@ +/****************************************************************************** + * + * Name: skaddr.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.26 $ + * Date: $Date: 2002/11/15 07:24:42 $ + * Purpose: Header file for Address Management (MC, UC, Prom). + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skaddr.h,v $ + * Revision 1.26 2002/11/15 07:24:42 tschilli + * SK_ADDR_EQUAL macro fixed. + * + * Revision 1.25 2002/06/10 13:55:18 tschilli + * Changes for handling YUKON. + * All changes are internally and not visible to the programmer + * using this module. + * + * Revision 1.24 2001/01/22 13:41:34 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.23 2000/08/10 11:27:50 rassmann + * Editorial changes. + * Preserving 32-bit alignment in structs for the adapter context. + * + * Revision 1.22 2000/08/07 11:10:40 rassmann + * Editorial changes. + * + * Revision 1.21 2000/05/04 09:39:59 rassmann + * Editorial changes. + * Corrected multicast address hashing. + * + * Revision 1.20 1999/11/22 13:46:14 cgoos + * Changed license header to GPL. + * Allowing overwrite for SK_ADDR_EQUAL. + * + * Revision 1.19 1999/05/28 10:56:07 rassmann + * Editorial changes. + * + * Revision 1.18 1999/04/06 17:22:04 rassmann + * Added private "ActivePort". + * + * Revision 1.17 1999/01/14 16:18:19 rassmann + * Corrected multicast initialization. + * + * Revision 1.16 1999/01/04 10:30:36 rassmann + * SkAddrOverride only possible after SK_INIT_IO phase. + * + * Revision 1.15 1998/12/29 13:13:11 rassmann + * An address override is now preserved in the SK_INIT_IO phase. + * All functions return an int now. + * Extended parameter checking. + * + * Revision 1.14 1998/11/24 12:39:45 rassmann + * Reserved multicast entry for BPDU address. + * 13 multicast entries left for protocol. + * + * Revision 1.13 1998/11/13 17:24:32 rassmann + * Changed return value of SkAddrOverride to int. + * + * Revision 1.12 1998/11/13 16:56:19 rassmann + * Added macro SK_ADDR_COMPARE. + * Changed return type of SkAddrOverride to SK_BOOL. + * + * Revision 1.11 1998/10/28 18:16:35 rassmann + * Avoiding I/Os before SK_INIT_RUN level. + * Aligning InexactFilter. + * + * Revision 1.10 1998/10/22 11:39:10 rassmann + * Corrected signed/unsigned mismatches. + * + * Revision 1.9 1998/10/15 15:15:49 rassmann + * Changed Flags Parameters from SK_U8 to int. + * Checked with lint. + * + * Revision 1.8 1998/09/24 19:15:12 rassmann + * Code cleanup. + * + * Revision 1.7 1998/09/18 20:22:13 rassmann + * Added HW access. + * + * Revision 1.6 1998/09/04 19:40:20 rassmann + * Interface enhancements. + * + * Revision 1.5 1998/09/04 12:40:57 rassmann + * Interface cleanup. + * + * Revision 1.4 1998/09/04 12:14:13 rassmann + * Interface cleanup. + * + * Revision 1.3 1998/09/02 16:56:40 rassmann + * Updated interface. + * + * Revision 1.2 1998/08/27 14:26:09 rassmann + * Updated interface. + * + * Revision 1.1 1998/08/21 08:31:08 rassmann + * First public version. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This module is intended to manage multicast addresses and promiscuous mode + * on GEnesis adapters. + * + * Include File Hierarchy: + * + * "skdrv1st.h" + * ... + * "sktypes.h" + * "skqueue.h" + * "skaddr.h" + * ... + * "skdrv2nd.h" + * + ******************************************************************************/ + +#ifndef __INC_SKADDR_H +#define __INC_SKADDR_H + +#ifdef __cplusplus +#error C++ is not yet supported. +extern "C" { +#endif /* cplusplus */ + +/* defines ********************************************************************/ + +#define SK_MAC_ADDR_LEN 6 /* Length of MAC address. */ +#define SK_MAX_ADDRS 14 /* #Addrs for exact match. */ + +/* ----- Common return values ----- */ + +#define SK_ADDR_SUCCESS 0 /* Function returned successfully. */ +#define SK_ADDR_ILLEGAL_PORT 100 /* Port number too high. */ +#define SK_ADDR_TOO_EARLY 101 /* Function called too early. */ + +/* ----- Clear/Add flag bits ----- */ + +#define SK_ADDR_PERMANENT 1 /* RLMT Address */ + +/* ----- Additional Clear flag bits ----- */ + +#define SK_MC_SW_ONLY 2 /* Do not update HW when clearing. */ + +/* ----- Override flag bits ----- */ + +#define SK_ADDR_LOGICAL_ADDRESS 0 +#define SK_ADDR_VIRTUAL_ADDRESS (SK_ADDR_LOGICAL_ADDRESS) /* old */ +#define SK_ADDR_PHYSICAL_ADDRESS 1 +#define SK_ADDR_CLEAR_LOGICAL 2 +#define SK_ADDR_SET_LOGICAL 4 + +/* ----- Override return values ----- */ + +#define SK_ADDR_OVERRIDE_SUCCESS (SK_ADDR_SUCCESS) +#define SK_ADDR_DUPLICATE_ADDRESS 1 +#define SK_ADDR_MULTICAST_ADDRESS 2 + +/* ----- Partitioning of excact match table ----- */ + +#define SK_ADDR_EXACT_MATCHES 16 /* #Exact match entries. */ + +#define SK_ADDR_FIRST_MATCH_RLMT 1 +#define SK_ADDR_LAST_MATCH_RLMT 2 +#define SK_ADDR_FIRST_MATCH_DRV 3 +#define SK_ADDR_LAST_MATCH_DRV (SK_ADDR_EXACT_MATCHES - 1) + +/* ----- SkAddrMcAdd/SkAddrMcUpdate return values ----- */ + +#define SK_MC_FILTERING_EXACT 0 /* Exact filtering. */ +#define SK_MC_FILTERING_INEXACT 1 /* Inexact filtering. */ + +/* ----- Additional SkAddrMcAdd return values ----- */ + +#define SK_MC_ILLEGAL_ADDRESS 2 /* Illegal address. */ +#define SK_MC_ILLEGAL_PORT 3 /* Illegal port (not the active one). */ +#define SK_MC_RLMT_OVERFLOW 4 /* Too many RLMT mc addresses. */ + +/* Promiscuous mode bits ----- */ + +#define SK_PROM_MODE_NONE 0 /* Normal receive. */ +#define SK_PROM_MODE_LLC 1 /* Receive all LLC frames. */ +#define SK_PROM_MODE_ALL_MC 2 /* Receive all multicast frames. */ +/* #define SK_PROM_MODE_NON_LLC 4 */ /* Receive all non-LLC frames. */ + +/* Macros */ + +#if 0 +#ifndef SK_ADDR_EQUAL +/* + * "&" instead of "&&" allows better optimization on IA-64. + * The replacement is safe here, as all bytes exist. + */ +#ifndef SK_ADDR_DWORD_COMPARE +#define SK_ADDR_EQUAL(A1,A2) ( \ + (((SK_U8 *)(A1))[5] == ((SK_U8 *)(A2))[5]) & \ + (((SK_U8 *)(A1))[4] == ((SK_U8 *)(A2))[4]) & \ + (((SK_U8 *)(A1))[3] == ((SK_U8 *)(A2))[3]) & \ + (((SK_U8 *)(A1))[2] == ((SK_U8 *)(A2))[2]) & \ + (((SK_U8 *)(A1))[1] == ((SK_U8 *)(A2))[1]) & \ + (((SK_U8 *)(A1))[0] == ((SK_U8 *)(A2))[0])) +#else /* SK_ADDR_DWORD_COMPARE */ +#define SK_ADDR_EQUAL(A1,A2) ( \ + (*(SK_U32 *)&(((SK_U8 *)(A1))[2]) == *(SK_U32 *)&(((SK_U8 *)(A2))[2])) & \ + (*(SK_U32 *)&(((SK_U8 *)(A1))[0]) == *(SK_U32 *)&(((SK_U8 *)(A2))[0]))) +#endif /* SK_ADDR_DWORD_COMPARE */ +#endif /* SK_ADDR_EQUAL */ +#endif /* 0 */ + +#ifndef SK_ADDR_EQUAL +#ifndef SK_ADDR_DWORD_COMPARE +#define SK_ADDR_EQUAL(A1,A2) ( \ + (((SK_U8 *)(A1))[5] == ((SK_U8 *)(A2))[5]) & \ + (((SK_U8 *)(A1))[4] == ((SK_U8 *)(A2))[4]) & \ + (((SK_U8 *)(A1))[3] == ((SK_U8 *)(A2))[3]) & \ + (((SK_U8 *)(A1))[2] == ((SK_U8 *)(A2))[2]) & \ + (((SK_U8 *)(A1))[1] == ((SK_U8 *)(A2))[1]) & \ + (((SK_U8 *)(A1))[0] == ((SK_U8 *)(A2))[0])) +#else /* SK_ADDR_DWORD_COMPARE */ +#define SK_ADDR_EQUAL(A1,A2) ( \ + (*(SK_U16 *)&(((SK_U8 *)(A1))[4]) == *(SK_U16 *)&(((SK_U8 *)(A2))[4])) && \ + (*(SK_U32 *)&(((SK_U8 *)(A1))[0]) == *(SK_U32 *)&(((SK_U8 *)(A2))[0]))) +#endif /* SK_ADDR_DWORD_COMPARE */ +#endif /* SK_ADDR_EQUAL */ + +/* typedefs *******************************************************************/ + +typedef struct s_MacAddr { + SK_U8 a[SK_MAC_ADDR_LEN]; +} SK_MAC_ADDR; + + +/* SK_FILTER is used to ensure alignment of the filter. */ +typedef union s_InexactFilter { + SK_U8 Bytes[8]; + SK_U64 Val; /* Dummy entry for alignment only. */ +} SK_FILTER64; + + +typedef struct s_AddrNet SK_ADDR_NET; + + +typedef struct s_AddrPort { + +/* ----- Public part (read-only) ----- */ + + SK_MAC_ADDR CurrentMacAddress; /* Current physical MAC Address. */ + SK_MAC_ADDR PermanentMacAddress; /* Permanent physical MAC Address. */ + int PromMode; /* Promiscuous Mode. */ + +/* ----- Private part ----- */ + + SK_MAC_ADDR PreviousMacAddress; /* Prev. phys. MAC Address. */ + SK_BOOL CurrentMacAddressSet; /* CurrentMacAddress is set. */ + SK_U8 Align01; + + SK_U32 FirstExactMatchRlmt; + SK_U32 NextExactMatchRlmt; + SK_U32 FirstExactMatchDrv; + SK_U32 NextExactMatchDrv; + SK_MAC_ADDR Exact[SK_ADDR_EXACT_MATCHES]; + SK_FILTER64 InexactFilter; /* For 64-bit hash register. */ + SK_FILTER64 InexactRlmtFilter; /* For 64-bit hash register. */ + SK_FILTER64 InexactDrvFilter; /* For 64-bit hash register. */ +} SK_ADDR_PORT; + + +struct s_AddrNet { +/* ----- Public part (read-only) ----- */ + + SK_MAC_ADDR CurrentMacAddress; /* Logical MAC Address. */ + SK_MAC_ADDR PermanentMacAddress; /* Logical MAC Address. */ + +/* ----- Private part ----- */ + + SK_U32 ActivePort; /* View of module ADDR. */ + SK_BOOL CurrentMacAddressSet; /* CurrentMacAddress is set. */ + SK_U8 Align01; + SK_U16 Align02; +}; + + +typedef struct s_Addr { + +/* ----- Public part (read-only) ----- */ + + SK_ADDR_NET Net[SK_MAX_NETS]; + SK_ADDR_PORT Port[SK_MAX_MACS]; + +/* ----- Private part ----- */ +} SK_ADDR; + +/* function prototypes ********************************************************/ + +#ifndef SK_KR_PROTO + +/* Functions provided by SkAddr */ + +/* ANSI/C++ compliant function prototypes */ + +extern int SkAddrInit( + SK_AC *pAC, + SK_IOC IoC, + int Level); + +extern int SkAddrMcClear( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int Flags); + +extern int SkAddrXmacMcClear( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int Flags); + +extern int SkAddrGmacMcClear( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int Flags); + +extern int SkAddrMcAdd( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + SK_MAC_ADDR *pMc, + int Flags); + +extern int SkAddrXmacMcAdd( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + SK_MAC_ADDR *pMc, + int Flags); + +extern int SkAddrGmacMcAdd( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + SK_MAC_ADDR *pMc, + int Flags); + +extern int SkAddrMcUpdate( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber); + +extern int SkAddrXmacMcUpdate( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber); + +extern int SkAddrGmacMcUpdate( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber); + +extern int SkAddrOverride( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + SK_MAC_ADDR *pNewAddr, + int Flags); + +extern int SkAddrPromiscuousChange( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int NewPromMode); + +extern int SkAddrXmacPromiscuousChange( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int NewPromMode); + +extern int SkAddrGmacPromiscuousChange( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int NewPromMode); + +extern int SkAddrSwap( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 FromPortNumber, + SK_U32 ToPortNumber); + +#else /* defined(SK_KR_PROTO)) */ + +/* Non-ANSI/C++ compliant function prototypes */ + +#error KR-style prototypes are not yet provided. + +#endif /* defined(SK_KR_PROTO)) */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKADDR_H */ diff --git a/drivers/sk98lin/h/skcsum.h b/drivers/sk98lin/h/skcsum.h new file mode 100644 index 0000000..2acae32 --- /dev/null +++ b/drivers/sk98lin/h/skcsum.h @@ -0,0 +1,261 @@ +/****************************************************************************** + * + * Name: skcsum.h + * Project: GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx) + * Version: $Revision: 1.9 $ + * Date: $Date: 2001/02/06 11:21:39 $ + * Purpose: Store/verify Internet checksum in send/receive packets. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skcsum.h,v $ + * Revision 1.9 2001/02/06 11:21:39 rassmann + * Editorial changes. + * + * Revision 1.8 2001/02/06 11:15:36 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.7 2000/06/29 13:17:05 rassmann + * Corrected reception of a packet with UDP checksum == 0 (which means there + * is no UDP checksum). + * + * Revision 1.6 2000/02/28 12:33:44 cgoos + * Changed C++ style comments to C style. + * + * Revision 1.5 2000/02/21 12:10:05 cgoos + * Fixed license comment. + * + * Revision 1.4 2000/02/21 11:08:37 cgoos + * Merged changes back into common source. + * + * Revision 1.1 1999/07/26 14:47:49 mkarl + * changed from common source to windows specific source + * added return SKCS_STATUS_IP_CSUM_ERROR_UDP and + * SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester + * changes for Tx csum offload + * + * Revision 1.2 1998/09/04 12:16:34 mhaveman + * Checked in for Stephan to allow compilation. + * -Added definition SK_CSUM_EVENT_CLEAR_PROTO_STATS to clear statistic + * -Added prototype for SkCsEvent() + * + * Revision 1.1 1998/09/01 15:36:53 swolf + * initial revision + * + * 01-Sep-1998 sw Created. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * Public header file for the "GEnesis" common module "CSUM". + * + * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon" + * and is the code name of this SysKonnect project. + * + * Compilation Options: + * + * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an + * empty module. + * + * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id + * definitions. In this case, all SKCS_PROTO_xxx definitions must be made + * external. + * + * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status + * definitions. In this case, all SKCS_STATUS_xxx definitions must be made + * external. + * + * Include File Hierarchy: + * + * "h/skcsum.h" + * "h/sktypes.h" + * "h/skqueue.h" + * + ******************************************************************************/ + +#ifndef __INC_SKCSUM_H +#define __INC_SKCSUM_H + +#include "h/sktypes.h" +#include "h/skqueue.h" + +/* defines ********************************************************************/ + +/* + * Define the default bit flags for 'SKCS_PACKET_INFO.ProtocolFlags' if no user + * overwrite. + */ +#ifndef SKCS_OVERWRITE_PROTO /* User overwrite? */ +#define SKCS_PROTO_IP 0x1 /* IP (Internet Protocol version 4) */ +#define SKCS_PROTO_TCP 0x2 /* TCP (Transmission Control Protocol) */ +#define SKCS_PROTO_UDP 0x4 /* UDP (User Datagram Protocol) */ + +/* Indices for protocol statistics. */ +#define SKCS_PROTO_STATS_IP 0 +#define SKCS_PROTO_STATS_UDP 1 +#define SKCS_PROTO_STATS_TCP 2 +#define SKCS_NUM_PROTOCOLS 3 /* Number of supported protocols. */ +#endif /* !SKCS_OVERWRITE_PROTO */ + +/* + * Define the default SKCS_STATUS type and values if no user overwrite. + * + * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame. + * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error. + * SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame. + * SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame + * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok). + * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame). + * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok). + * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok). + * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok. + * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok. + * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum. + */ +#ifndef SKCS_OVERWRITE_STATUS /* User overwrite? */ +#define SKCS_STATUS int /* Define status type. */ + +#define SKCS_STATUS_UNKNOWN_IP_VERSION 1 +#define SKCS_STATUS_IP_CSUM_ERROR 2 +#define SKCS_STATUS_IP_FRAGMENT 3 +#define SKCS_STATUS_IP_CSUM_OK 4 +#define SKCS_STATUS_TCP_CSUM_ERROR 5 +#define SKCS_STATUS_UDP_CSUM_ERROR 6 +#define SKCS_STATUS_TCP_CSUM_OK 7 +#define SKCS_STATUS_UDP_CSUM_OK 8 +/* needed for Microsoft */ +#define SKCS_STATUS_IP_CSUM_ERROR_UDP 9 +#define SKCS_STATUS_IP_CSUM_ERROR_TCP 10 +/* UDP checksum may be omitted */ +#define SKCS_STATUS_IP_CSUM_OK_NO_UDP 11 +#endif /* !SKCS_OVERWRITE_STATUS */ + +/* Clear protocol statistics event. */ +#define SK_CSUM_EVENT_CLEAR_PROTO_STATS 1 + +/* + * Add two values in one's complement. + * + * Note: One of the two input values may be "longer" than 16-bit, but then the + * resulting sum may be 17 bits long. In this case, add zero to the result using + * SKCS_OC_ADD() again. + * + * Result = Value1 + Value2 + */ +#define SKCS_OC_ADD(Result, Value1, Value2) { \ + unsigned long Sum; \ + \ + Sum = (unsigned long) (Value1) + (unsigned long) (Value2); \ + /* Add-in any carry. */ \ + (Result) = (Sum & 0xffff) + (Sum >> 16); \ +} + +/* + * Subtract two values in one's complement. + * + * Result = Value1 - Value2 + */ +#define SKCS_OC_SUB(Result, Value1, Value2) \ + SKCS_OC_ADD((Result), (Value1), ~(Value2) & 0xffff) + +/* typedefs *******************************************************************/ + +/* + * SKCS_PROTO_STATS - The CSUM protocol statistics structure. + * + * There is one instance of this structure for each protocol supported. + */ +typedef struct s_CsProtocolStatistics { + SK_U64 RxOkCts; /* Receive checksum ok. */ + SK_U64 RxUnableCts; /* Unable to verify receive checksum. */ + SK_U64 RxErrCts; /* Receive checksum error. */ + SK_U64 TxOkCts; /* Transmit checksum ok. */ + SK_U64 TxUnableCts; /* Unable to calculate checksum in hw. */ +} SKCS_PROTO_STATS; + +/* + * s_Csum - The CSUM module context structure. + */ +typedef struct s_Csum { + /* Enabled receive SK_PROTO_XXX bit flags. */ + unsigned ReceiveFlags[SK_MAX_NETS]; +#ifdef TX_CSUM + unsigned TransmitFlags[SK_MAX_NETS]; +#endif /* TX_CSUM */ + + /* The protocol statistics structure; one per supported protocol. */ + SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS]; +} SK_CSUM; + +/* + * SKCS_PACKET_INFO - The packet information structure. + */ +typedef struct s_CsPacketInfo { + /* Bit field specifiying the desired/found protocols. */ + unsigned ProtocolFlags; + + /* Length of complete IP header, including any option fields. */ + unsigned IpHeaderLength; + + /* IP header checksum. */ + unsigned IpHeaderChecksum; + + /* TCP/UDP pseudo header checksum. */ + unsigned PseudoHeaderChecksum; +} SKCS_PACKET_INFO; + +/* function prototypes ********************************************************/ + +#ifndef SkCsCalculateChecksum +extern unsigned SkCsCalculateChecksum( + void *pData, + unsigned Length); +#endif + +extern int SkCsEvent( + SK_AC *pAc, + SK_IOC Ioc, + SK_U32 Event, + SK_EVPARA Param); + +extern SKCS_STATUS SkCsGetReceiveInfo( + SK_AC *pAc, + void *pIpHeader, + unsigned Checksum1, + unsigned Checksum2, + int NetNumber); + +extern void SkCsGetSendInfo( + SK_AC *pAc, + void *pIpHeader, + SKCS_PACKET_INFO *pPacketInfo, + int NetNumber); + +extern void SkCsSetReceiveFlags( + SK_AC *pAc, + unsigned ReceiveFlags, + unsigned *pChecksum1Offset, + unsigned *pChecksum2Offset, + int NetNumber); + +#endif /* __INC_SKCSUM_H */ diff --git a/drivers/sk98lin/h/skdebug.h b/drivers/sk98lin/h/skdebug.h new file mode 100644 index 0000000..cf5b5ad --- /dev/null +++ b/drivers/sk98lin/h/skdebug.h @@ -0,0 +1,119 @@ +/****************************************************************************** + * + * Name: skdebug.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.12 $ + * Date: $Date: 2002/07/15 15:37:13 $ + * Purpose: SK specific DEBUG support + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skdebug.h,v $ + * Revision 1.12 2002/07/15 15:37:13 rschmidt + * Power Management support + * Editorial changes + * + * Revision 1.11 2002/04/25 11:04:39 rschmidt + * Editorial changes + * + * Revision 1.10 1999/11/22 13:47:40 cgoos + * Changed license header to GPL. + * + * Revision 1.9 1999/09/14 14:02:43 rwahl + * Added SK_DBGMOD_PECP. + * + * Revision 1.8 1998/11/25 08:31:54 gklug + * fix: no C++ comments allowed in common sources + * + * Revision 1.7 1998/11/24 16:47:24 swolf + * Driver may now define its own SK_DBG_MSG() (eg. in "h/skdrv1st.h"). + * + * Revision 1.6 1998/10/28 10:23:55 rassmann + * ADDED SK_DBGMOD_ADDR. + * + * Revision 1.5 1998/10/22 09:43:55 gklug + * add: CSUM module + * + * Revision 1.4 1998/10/01 07:54:44 gklug + * add: PNMI debug module + * + * Revision 1.3 1998/09/18 08:32:34 afischer + * Macros changed according ssr-spec.: + * SK_DBG_MODCHK -> SK_DBG_CHKMOD + * SK_DBG_CATCHK -> SK_DBG_CHKCAT + * + * Revision 1.2 1998/07/03 14:38:25 malthoff + * Add category SK_DBGCAT_FATAL. + * + * Revision 1.1 1998/06/19 13:39:01 malthoff + * created. + * + * + ******************************************************************************/ + +#ifndef __INC_SKDEBUG_H +#define __INC_SKDEBUG_H + +#ifdef DEBUG +#ifndef SK_DBG_MSG +#define SK_DBG_MSG(pAC,comp,cat,arg) \ + if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \ + ((cat) & SK_DBG_CHKCAT(pAC)) ) { \ + SK_DBG_PRINTF arg ; \ + } +#endif +#else +#define SK_DBG_MSG(pAC,comp,lev,arg) +#endif + +/* PLS NOTE: + * ========= + * Due to any restrictions of kernel printf routines do not use other + * format identifiers as: %x %d %c %s . + * Never use any combined format identifiers such as: %lx %ld in your + * printf - argument (arg) because some OS specific kernel printfs may + * only support some basic identifiers. + */ + +/* Debug modules */ + +#define SK_DBGMOD_MERR 0x00000001L /* general module error indication */ +#define SK_DBGMOD_HWM 0x00000002L /* Hardware init module */ +#define SK_DBGMOD_RLMT 0x00000004L /* RLMT module */ +#define SK_DBGMOD_VPD 0x00000008L /* VPD module */ +#define SK_DBGMOD_I2C 0x00000010L /* I2C module */ +#define SK_DBGMOD_PNMI 0x00000020L /* PNMI module */ +#define SK_DBGMOD_CSUM 0x00000040L /* CSUM module */ +#define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */ +#define SK_DBGMOD_PECP 0x00000100L /* PECP module */ +#define SK_DBGMOD_POWM 0x00000200L /* Power Management module */ + +/* Debug events */ + +#define SK_DBGCAT_INIT 0x00000001L /* module/driver initialization */ +#define SK_DBGCAT_CTRL 0x00000002L /* controlling devices */ +#define SK_DBGCAT_ERR 0x00000004L /* error handling paths */ +#define SK_DBGCAT_TX 0x00000008L /* transmit path */ +#define SK_DBGCAT_RX 0x00000010L /* receive path */ +#define SK_DBGCAT_IRQ 0x00000020L /* general IRQ handling */ +#define SK_DBGCAT_QUEUE 0x00000040L /* any queue management */ +#define SK_DBGCAT_DUMP 0x00000080L /* large data output e.g. hex dump */ +#define SK_DBGCAT_FATAL 0x00000100L /* fatal error */ + +#endif /* __INC_SKDEBUG_H */ diff --git a/drivers/sk98lin/h/skdrv1st.h b/drivers/sk98lin/h/skdrv1st.h new file mode 100644 index 0000000..af34d7b --- /dev/null +++ b/drivers/sk98lin/h/skdrv1st.h @@ -0,0 +1,264 @@ +/****************************************************************************** + * + * Name: skdrv1st.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.11 $ + * Date: $Date: 2003/02/25 14:16:40 $ + * Purpose: First header file for driver and all other modules + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skdrv1st.h,v $ + * Revision 1.11 2003/02/25 14:16:40 mlindner + * Fix: Copyright statement + * + * Revision 1.10 2002/10/02 12:46:02 mlindner + * Add: Support for Yukon + * + * Revision 1.9.2.2 2001/12/07 12:06:42 mlindner + * Fix: malloc -> slab changes + * + * Revision 1.9.2.1 2001/03/12 16:50:59 mlindner + * chg: kernel 2.4 adaption + * + * Revision 1.9 2001/01/22 14:16:04 mlindner + * added ProcFs functionality + * Dual Net functionality integrated + * Rlmt networks added + * + * Revision 1.8 2000/02/21 12:19:18 cgoos + * Added default for SK_DEBUG_CHKMOD/_CHKCAT + * + * Revision 1.7 1999/11/22 13:50:00 cgoos + * Changed license header to GPL. + * Added overwrite for several functions. + * Removed linux 2.0.x definitions. + * Removed PCI vendor ID definition (now in kernel). + * + * Revision 1.6 1999/07/27 08:03:33 cgoos + * Changed SK_IN/OUT macros to readX/writeX instead of memory + * accesses (necessary for ALPHA). + * + * Revision 1.5 1999/07/23 12:10:21 cgoos + * Removed SK_RLMT_SLOW_LOOKAHEAD define. + * + * Revision 1.4 1999/07/14 12:31:13 cgoos + * Added SK_RLMT_SLOW_LOOKAHEAD define. + * + * Revision 1.3 1999/04/07 10:12:54 cgoos + * Added check for KERNEL and OPTIMIZATION defines. + * + * Revision 1.2 1999/03/01 08:51:47 cgoos + * Fixed pcibios_read/write definitions. + * + * Revision 1.1 1999/02/16 07:40:49 cgoos + * First version. + * + * + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This is the first include file of the driver, which includes all + * neccessary system header files and some of the GEnesis header files. + * It also defines some basic items. + * + * Include File Hierarchy: + * + * see skge.c + * + ******************************************************************************/ + +#ifndef __INC_SKDRV1ST_H +#define __INC_SKDRV1ST_H + +#if 0 +/* Check kernel version */ +#include +#if (LINUX_VERSION_CODE > 0x020300) +#endif +#endif + +typedef struct s_AC SK_AC; + +/* override some default functions with optimized linux functions */ + +#define SK_PNMI_STORE_U16(p,v) memcpy((char*)(p),(char*)&(v),2) +#define SK_PNMI_STORE_U32(p,v) memcpy((char*)(p),(char*)&(v),4) +#define SK_PNMI_STORE_U64(p,v) memcpy((char*)(p),(char*)&(v),8) +#define SK_PNMI_READ_U16(p,v) memcpy((char*)&(v),(char*)(p),2) +#define SK_PNMI_READ_U32(p,v) memcpy((char*)&(v),(char*)(p),2) +#define SK_PNMI_READ_U64(p,v) memcpy((char*)&(v),(char*)(p),2) + +#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff) + +#define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6)) + + +#if !defined(__OPTIMIZE__) || !defined(__KERNEL__) +#warning You must compile this file with the correct options! +#warning See the last lines of the source file. +#error You must compile this driver with "-O". +#endif + +#if 0 +#include +#endif +#include +#if 0 +#include +#endif +#include +#if 0 +#include +#include +#include +#include +#include +#endif +#include +#include +#include +#if 0 +#include +#include +#include + +#include +#include +#include +#endif + +#include "h/sktypes.h" +#include "h/skerror.h" +#include "h/skdebug.h" +#include "h/lm80.h" +#include "h/xmac_ii.h" + +#include "u-boot_compat.h" + +#ifdef __LITTLE_ENDIAN +#define SK_LITTLE_ENDIAN +#else +#define SK_BIG_ENDIAN +#endif + +#if 0 +#define SK_NET_DEVICE net_device +#else +#define SK_NET_DEVICE eth_device +#endif + + +/* we use gethrtime(), return unit: nanoseconds */ +#if 0 +#define SK_TICKS_PER_SEC HZ +#else +#define SK_TICKS_PER_SEC CFG_HZ +#endif + +#define SK_MEM_MAPPED_IO + +/* #define SK_RLMT_SLOW_LOOKAHEAD */ + +#define SK_MAX_MACS 2 +#define SK_MAX_NETS 2 + +#define SK_IOC char* + +typedef struct s_DrvRlmtMbuf SK_MBUF; + +#define SK_CONST64 INT64_C +#define SK_CONSTU64 UINT64_C + +#define SK_MEMCPY(dest,src,size) memcpy(dest,src,size) +#define SK_MEMCMP(s1,s2,size) memcmp(s1,s2,size) +#define SK_MEMSET(dest,val,size) memset(dest,val,size) +#define SK_STRLEN(pStr) strlen((char*)(pStr)) +#define SK_STRNCPY(pDest,pSrc,size) strncpy((char*)(pDest),(char*)(pSrc),size) +#define SK_STRCMP(pStr1,pStr2) strcmp((char*)(pStr1),(char*)(pStr2)) + +/* macros to access the adapter */ +#define SK_OUT8(b,a,v) writeb((v), ((b)+(a))) +#define SK_OUT16(b,a,v) writew((v), ((b)+(a))) +#define SK_OUT32(b,a,v) writel((v), ((b)+(a))) +#define SK_IN8(b,a,pv) (*(pv) = readb((b)+(a))) +#define SK_IN16(b,a,pv) (*(pv) = readw((b)+(a))) +#define SK_IN32(b,a,pv) (*(pv) = readl((b)+(a))) + +#define int8_t char +#define int16_t short +#define int32_t long +#define int64_t long long +#define uint8_t u_char +#define uint16_t u_short +#define uint32_t u_long +#define uint64_t unsigned long long +#define t_scalar_t int +#define t_uscalar_t unsigned int +#define uintptr_t unsigned long + +#define __CONCAT__(A,B) A##B + +#define INT32_C(a) __CONCAT__(a,L) +#define INT64_C(a) __CONCAT__(a,LL) +#define UINT32_C(a) __CONCAT__(a,UL) +#define UINT64_C(a) __CONCAT__(a,ULL) + +#ifdef DEBUG +#define SK_DBG_PRINTF printk +#ifndef SK_DEBUG_CHKMOD +#define SK_DEBUG_CHKMOD 0 +#endif +#ifndef SK_DEBUG_CHKCAT +#define SK_DEBUG_CHKCAT 0 +#endif +/* those come from the makefile */ +#define SK_DBG_CHKMOD(pAC) (SK_DEBUG_CHKMOD) +#define SK_DBG_CHKCAT(pAC) (SK_DEBUG_CHKCAT) + +extern void SkDbgPrintf(const char *format,...); + +#define SK_DBGMOD_DRV 0x00010000 + +/**** possible driver debug categories ********************************/ +#define SK_DBGCAT_DRV_ENTRY 0x00010000 +#define SK_DBGCAT_DRV_SAP 0x00020000 +#define SK_DBGCAT_DRV_MCA 0x00040000 +#define SK_DBGCAT_DRV_TX_PROGRESS 0x00080000 +#define SK_DBGCAT_DRV_RX_PROGRESS 0x00100000 +#define SK_DBGCAT_DRV_PROGRESS 0x00200000 +#define SK_DBGCAT_DRV_MSG 0x00400000 +#define SK_DBGCAT_DRV_PROM 0x00800000 +#define SK_DBGCAT_DRV_TX_FRAME 0x01000000 +#define SK_DBGCAT_DRV_ERROR 0x02000000 +#define SK_DBGCAT_DRV_INT_SRC 0x04000000 +#define SK_DBGCAT_DRV_EVENT 0x08000000 + +#endif + +#define SK_ERR_LOG SkErrorLog + +extern void SkErrorLog(SK_AC*, int, int, char*); + +#endif diff --git a/drivers/sk98lin/h/skdrv2nd.h b/drivers/sk98lin/h/skdrv2nd.h new file mode 100644 index 0000000..a311827 --- /dev/null +++ b/drivers/sk98lin/h/skdrv2nd.h @@ -0,0 +1,561 @@ +/****************************************************************************** + * + * Name: skdrv2nd.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.15 $ + * Date: $Date: 2003/02/25 14:16:40 $ + * Purpose: Second header file for driver and all other modules + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skdrv2nd.h,v $ + * Revision 1.15 2003/02/25 14:16:40 mlindner + * Fix: Copyright statement + * + * Revision 1.14 2003/02/25 13:26:26 mlindner + * Add: Support for various vendors + * + * Revision 1.13 2002/10/02 12:46:02 mlindner + * Add: Support for Yukon + * + * Revision 1.12.2.2 2001/09/05 12:14:50 mlindner + * add: New hardware revision int + * + * Revision 1.12.2.1 2001/03/12 16:50:59 mlindner + * chg: kernel 2.4 adaption + * + * Revision 1.12 2001/03/01 12:52:15 mlindner + * Fixed ring size + * + * Revision 1.11 2001/02/19 13:28:02 mlindner + * Changed PNMI parameter values + * + * Revision 1.10 2001/01/22 14:16:04 mlindner + * added ProcFs functionality + * Dual Net functionality integrated + * Rlmt networks added + * + * Revision 1.1 2000/10/05 19:46:50 phargrov + * Add directory src/vipk_devs_nonlbl/vipk_sk98lin/ + * This is the SysKonnect SK-98xx Gigabit Ethernet driver, + * contributed by SysKonnect. + * + * Revision 1.9 2000/02/21 10:39:55 cgoos + * Added flag for jumbo support usage. + * + * Revision 1.8 1999/11/22 13:50:44 cgoos + * Changed license header to GPL. + * Fixed two comments. + * + * Revision 1.7 1999/09/28 12:38:21 cgoos + * Added CheckQueue to SK_AC. + * + * Revision 1.6 1999/07/27 08:04:05 cgoos + * Added checksumming variables to SK_AC. + * + * Revision 1.5 1999/03/29 12:33:26 cgoos + * Rreversed to fine lock granularity. + * + * Revision 1.4 1999/03/15 12:14:02 cgoos + * Added DriverLock to SK_AC. + * Removed other locks. + * + * Revision 1.3 1999/03/01 08:52:27 cgoos + * Changed pAC->PciDev declaration. + * + * Revision 1.2 1999/02/18 10:57:14 cgoos + * Removed SkDrvTimeStamp prototype. + * Fixed SkGeOsGetTime prototype. + * + * Revision 1.1 1999/02/16 07:41:01 cgoos + * First version. + * + * + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This is the second include file of the driver, which includes all other + * neccessary files and defines all structures and constants used by the + * driver and the common modules. + * + * Include File Hierarchy: + * + * see skge.c + * + ******************************************************************************/ + +#ifndef __INC_SKDRV2ND_H +#define __INC_SKDRV2ND_H + +#include "h/skqueue.h" +#include "h/skgehwt.h" +#include "h/sktimer.h" +#include "h/ski2c.h" +#include "h/skgepnmi.h" +#include "h/skvpd.h" +#include "h/skgehw.h" +#include "h/skgeinit.h" +#include "h/skaddr.h" +#include "h/skgesirq.h" +#include "h/skcsum.h" +#include "h/skrlmt.h" +#include "h/skgedrv.h" + +#define SK_PCI_ISCOMPLIANT(result, pdev) { \ + result = SK_FALSE; /* default */ \ + /* 3Com (0x10b7) */ \ + if (pdev->vendor == 0x10b7) { \ + /* Gigabit Ethernet Adapter (0x1700) */ \ + if ((pdev->device == 0x1700)) { \ + result = SK_TRUE; \ + } \ + /* SysKonnect (0x1148) */ \ + } else if (pdev->vendor == 0x1148) { \ + /* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */ \ + /* SK-98xx V2 Gigabit Ethernet Adapter (0x4320) */ \ + if ((pdev->device == 0x4300) || \ + (pdev->device == 0x4320)) { \ + result = SK_TRUE; \ + } \ + /* D-Link (0x1186) */ \ + } else if (pdev->vendor == 0x1186) { \ + /* Gigabit Ethernet Adapter (0x4c00) */ \ + if ((pdev->device == 0x4c00)) { \ + result = SK_TRUE; \ + } \ + /* CNet (0x1371) */ \ + } else if (pdev->vendor == 0x1371) { \ + /* GigaCard Network Adapter (0x434e) */ \ + if ((pdev->device == 0x434e)) { \ + result = SK_TRUE; \ + } \ + /* Linksys (0x1737) */ \ + } else if (pdev->vendor == 0x1737) { \ + /* Gigabit Network Adapter (0x1032) */ \ + /* Gigabit Network Adapter (0x1064) */ \ + if ((pdev->device == 0x1032) || \ + (pdev->device == 0x1064)) { \ + result = SK_TRUE; \ + } \ + } else { \ + result = SK_FALSE; \ + } \ +} + + +extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned); +extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*); +extern SK_U64 SkOsGetTime(SK_AC*); +extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*); +extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*); +extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*); +extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32); +extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16); +extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8); +extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA); + +struct s_DrvRlmtMbuf { + SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */ + SK_U8 *pData; /* Data buffer (virtually contig.). */ + unsigned Size; /* Data buffer size. */ + unsigned Length; /* Length of packet (<= Size). */ + SK_U32 PortIdx; /* Receiving/transmitting port. */ +#ifdef SK_RLMT_MBUF_PRIVATE + SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */ +#endif /* SK_RLMT_MBUF_PRIVATE */ + struct sk_buff *pOs; /* Pointer to message block */ +}; + + +/* + * ioctl definitions + */ +#define SK_IOCTL_BASE (SIOCDEVPRIVATE) +#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0) +#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1) +#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2) + +typedef struct s_IOCTL SK_GE_IOCTL; + +struct s_IOCTL { + char* pData; + unsigned int Len; +}; + + +/* + * define sizes of descriptor rings in bytes + */ + +#if 0 +#define TX_RING_SIZE (8*1024) +#define RX_RING_SIZE (24*1024) +#else +#define TX_RING_SIZE (10 * 40) +#define RX_RING_SIZE (10 * 40) +#endif + +/* + * Buffer size for ethernet packets + */ +#define ETH_BUF_SIZE 1540 +#define ETH_MAX_MTU 1514 +#define ETH_MIN_MTU 60 +#define ETH_MULTICAST_BIT 0x01 +#define SK_JUMBO_MTU 9000 + +/* + * transmit priority selects the queue: LOW=asynchron, HIGH=synchron + */ +#define TX_PRIO_LOW 0 +#define TX_PRIO_HIGH 1 + +/* + * alignment of rx/tx descriptors + */ +#define DESCR_ALIGN 8 + +/* + * definitions for pnmi. TODO + */ +#define SK_DRIVER_RESET(pAC, IoC) 0 +#define SK_DRIVER_SENDEVENT(pAC, IoC) 0 +#define SK_DRIVER_SELFTEST(pAC, IoC) 0 +/* For get mtu you must add an own function */ +#define SK_DRIVER_GET_MTU(pAc,IoC,i) 0 +#define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0 +#define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0 + + +/* TX and RX descriptors *****************************************************/ + +typedef struct s_RxD RXD; /* the receive descriptor */ + +struct s_RxD { + volatile SK_U32 RBControl; /* Receive Buffer Control */ + SK_U32 VNextRxd; /* Next receive descriptor,low dword */ + SK_U32 VDataLow; /* Receive buffer Addr, low dword */ + SK_U32 VDataHigh; /* Receive buffer Addr, high dword */ + SK_U32 FrameStat; /* Receive Frame Status word */ + SK_U32 TimeStamp; /* Time stamp from XMAC */ + SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */ + SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */ + RXD *pNextRxd; /* Pointer to next Rxd */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ +}; + +typedef struct s_TxD TXD; /* the transmit descriptor */ + +struct s_TxD { + volatile SK_U32 TBControl; /* Transmit Buffer Control */ + SK_U32 VNextTxd; /* Next transmit descriptor,low dword */ + SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */ + SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */ + SK_U32 FrameStat; /* Transmit Frame Status Word */ + SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */ + SK_U16 TcpSumSt; /* TCP Sum Start */ + SK_U16 TcpSumWr; /* TCP Sum Write */ + SK_U32 TcpReserved; /* not used */ + TXD *pNextTxd; /* Pointer to next Txd */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ +}; + + +/* definition of flags in descriptor control field */ +#define RX_CTRL_OWN_BMU UINT32_C(0x80000000) +#define RX_CTRL_STF UINT32_C(0x40000000) +#define RX_CTRL_EOF UINT32_C(0x20000000) +#define RX_CTRL_EOB_IRQ UINT32_C(0x10000000) +#define RX_CTRL_EOF_IRQ UINT32_C(0x08000000) +#define RX_CTRL_DEV_NULL UINT32_C(0x04000000) +#define RX_CTRL_STAT_VALID UINT32_C(0x02000000) +#define RX_CTRL_TIME_VALID UINT32_C(0x01000000) +#define RX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000) +#define RX_CTRL_CHECK_CSUM UINT32_C(0x00560000) +#define RX_CTRL_LEN_MASK UINT32_C(0x0000FFFF) + +#define TX_CTRL_OWN_BMU UINT32_C(0x80000000) +#define TX_CTRL_STF UINT32_C(0x40000000) +#define TX_CTRL_EOF UINT32_C(0x20000000) +#define TX_CTRL_EOB_IRQ UINT32_C(0x10000000) +#define TX_CTRL_EOF_IRQ UINT32_C(0x08000000) +#define TX_CTRL_ST_FWD UINT32_C(0x04000000) +#define TX_CTRL_DISAB_CRC UINT32_C(0x02000000) +#define TX_CTRL_SOFTWARE UINT32_C(0x01000000) +#define TX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000) +#define TX_CTRL_CHECK_CSUM UINT32_C(0x00560000) +#define TX_CTRL_LEN_MASK UINT32_C(0x0000FFFF) + + +/* The offsets of registers in the TX and RX queue control io area ***********/ + +#define RX_Q_BUF_CTRL_CNT 0x00 +#define RX_Q_NEXT_DESCR_LOW 0x04 +#define RX_Q_BUF_ADDR_LOW 0x08 +#define RX_Q_BUF_ADDR_HIGH 0x0c +#define RX_Q_FRAME_STAT 0x10 +#define RX_Q_TIME_STAMP 0x14 +#define RX_Q_CSUM_1_2 0x18 +#define RX_Q_CSUM_START_1_2 0x1c +#define RX_Q_CUR_DESCR_LOW 0x20 +#define RX_Q_DESCR_HIGH 0x24 +#define RX_Q_CUR_ADDR_LOW 0x28 +#define RX_Q_CUR_ADDR_HIGH 0x2c +#define RX_Q_CUR_BYTE_CNT 0x30 +#define RX_Q_CTRL 0x34 +#define RX_Q_FLAG 0x38 +#define RX_Q_TEST1 0x3c +#define RX_Q_TEST2 0x40 +#define RX_Q_TEST3 0x44 + +#define TX_Q_BUF_CTRL_CNT 0x00 +#define TX_Q_NEXT_DESCR_LOW 0x04 +#define TX_Q_BUF_ADDR_LOW 0x08 +#define TX_Q_BUF_ADDR_HIGH 0x0c +#define TX_Q_FRAME_STAT 0x10 +#define TX_Q_CSUM_START 0x14 +#define TX_Q_CSUM_START_POS 0x18 +#define TX_Q_RESERVED 0x1c +#define TX_Q_CUR_DESCR_LOW 0x20 +#define TX_Q_DESCR_HIGH 0x24 +#define TX_Q_CUR_ADDR_LOW 0x28 +#define TX_Q_CUR_ADDR_HIGH 0x2c +#define TX_Q_CUR_BYTE_CNT 0x30 +#define TX_Q_CTRL 0x34 +#define TX_Q_FLAG 0x38 +#define TX_Q_TEST1 0x3c +#define TX_Q_TEST2 0x40 +#define TX_Q_TEST3 0x44 + +/* definition of flags in the queue control field */ +#define RX_Q_CTRL_POLL_ON 0x00000080 +#define RX_Q_CTRL_POLL_OFF 0x00000040 +#define RX_Q_CTRL_STOP 0x00000020 +#define RX_Q_CTRL_START 0x00000010 +#define RX_Q_CTRL_CLR_I_PAR 0x00000008 +#define RX_Q_CTRL_CLR_I_EOB 0x00000004 +#define RX_Q_CTRL_CLR_I_EOF 0x00000002 +#define RX_Q_CTRL_CLR_I_ERR 0x00000001 + +#define TX_Q_CTRL_POLL_ON 0x00000080 +#define TX_Q_CTRL_POLL_OFF 0x00000040 +#define TX_Q_CTRL_STOP 0x00000020 +#define TX_Q_CTRL_START 0x00000010 +#define TX_Q_CTRL_CLR_I_EOB 0x00000004 +#define TX_Q_CTRL_CLR_I_EOF 0x00000002 +#define TX_Q_CTRL_CLR_I_ERR 0x00000001 + + +/* Interrupt bits in the interrupts source register **************************/ +#define IRQ_HW_ERROR 0x80000000 +#define IRQ_RESERVED 0x40000000 +#define IRQ_PKT_TOUT_RX1 0x20000000 +#define IRQ_PKT_TOUT_RX2 0x10000000 +#define IRQ_PKT_TOUT_TX1 0x08000000 +#define IRQ_PKT_TOUT_TX2 0x04000000 +#define IRQ_I2C_READY 0x02000000 +#define IRQ_SW 0x01000000 +#define IRQ_EXTERNAL_REG 0x00800000 +#define IRQ_TIMER 0x00400000 +#define IRQ_MAC1 0x00200000 +#define IRQ_LINK_SYNC_C_M1 0x00100000 +#define IRQ_MAC2 0x00080000 +#define IRQ_LINK_SYNC_C_M2 0x00040000 +#define IRQ_EOB_RX1 0x00020000 +#define IRQ_EOF_RX1 0x00010000 +#define IRQ_CHK_RX1 0x00008000 +#define IRQ_EOB_RX2 0x00004000 +#define IRQ_EOF_RX2 0x00002000 +#define IRQ_CHK_RX2 0x00001000 +#define IRQ_EOB_SY_TX1 0x00000800 +#define IRQ_EOF_SY_TX1 0x00000400 +#define IRQ_CHK_SY_TX1 0x00000200 +#define IRQ_EOB_AS_TX1 0x00000100 +#define IRQ_EOF_AS_TX1 0x00000080 +#define IRQ_CHK_AS_TX1 0x00000040 +#define IRQ_EOB_SY_TX2 0x00000020 +#define IRQ_EOF_SY_TX2 0x00000010 +#define IRQ_CHK_SY_TX2 0x00000008 +#define IRQ_EOB_AS_TX2 0x00000004 +#define IRQ_EOF_AS_TX2 0x00000002 +#define IRQ_CHK_AS_TX2 0x00000001 + +#define DRIVER_IRQS (IRQ_SW | IRQ_EOF_RX1 | IRQ_EOF_RX2 | \ + IRQ_EOF_SY_TX1 | IRQ_EOF_AS_TX1 | \ + IRQ_EOF_SY_TX2 | IRQ_EOF_AS_TX2) + +#define SPECIAL_IRQS (IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \ + IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \ + IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \ + IRQ_MAC1 | IRQ_LINK_SYNC_C_M1 | \ + IRQ_MAC2 | IRQ_LINK_SYNC_C_M2 | \ + IRQ_CHK_RX1 | IRQ_CHK_RX2 | \ + IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \ + IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2) + +#define IRQ_MASK (IRQ_SW | IRQ_EOB_RX1 | IRQ_EOF_RX1 | \ + IRQ_EOB_RX2 | IRQ_EOF_RX2 | \ + IRQ_EOB_SY_TX1 | IRQ_EOF_SY_TX1 | \ + IRQ_EOB_AS_TX1 | IRQ_EOF_AS_TX1 | \ + IRQ_EOB_SY_TX2 | IRQ_EOF_SY_TX2 | \ + IRQ_EOB_AS_TX2 | IRQ_EOF_AS_TX2 | \ + IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \ + IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \ + IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \ + IRQ_MAC1 | \ + IRQ_MAC2 | \ + IRQ_CHK_RX1 | IRQ_CHK_RX2 | \ + IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \ + IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2) + +#define IRQ_HWE_MASK 0x00000FFF /* enable all HW irqs */ + +typedef struct s_DevNet DEV_NET; + +struct s_DevNet { + int PortNr; + int NetNr; + int Mtu; + int Up; + SK_AC *pAC; +}; + +typedef struct s_TxPort TX_PORT; + +struct s_TxPort { + /* the transmit descriptor rings */ + caddr_t pTxDescrRing; /* descriptor area memory */ + SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */ + TXD *pTxdRingHead; /* Head of Tx rings */ + TXD *pTxdRingTail; /* Tail of Tx rings */ + TXD *pTxdRingPrev; /* descriptor sent previously */ + int TxdRingFree; /* # of free entrys */ +#if 0 + spinlock_t TxDesRingLock; /* serialize descriptor accesses */ +#endif + caddr_t HwAddr; /* bmu registers address */ + int PortIndex; /* index number of port (0 or 1) */ +}; + +typedef struct s_RxPort RX_PORT; + +struct s_RxPort { + /* the receive descriptor rings */ + caddr_t pRxDescrRing; /* descriptor area memory */ + SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */ + RXD *pRxdRingHead; /* Head of Rx rings */ + RXD *pRxdRingTail; /* Tail of Rx rings */ + RXD *pRxdRingPrev; /* descriptor given to BMU previously */ + int RxdRingFree; /* # of free entrys */ +#if 0 + spinlock_t RxDesRingLock; /* serialize descriptor accesses */ +#endif + int RxFillLimit; /* limit for buffers in ring */ + caddr_t HwAddr; /* bmu registers address */ + int PortIndex; /* index number of port (0 or 1) */ +}; + +typedef struct s_PerStrm PER_STRM; + +#define SK_ALLOC_IRQ 0x00000001 + +/**************************************************************************** + * Per board structure / Adapter Context structure: + * Allocated within attach(9e) and freed within detach(9e). + * Contains all 'per device' necessary handles, flags, locks etc.: + */ +struct s_AC { + SK_GEINIT GIni; /* GE init struct */ + SK_PNMI Pnmi; /* PNMI data struct */ + SK_VPD vpd; /* vpd data struct */ + SK_QUEUE Event; /* Event queue */ + SK_HWT Hwt; /* Hardware Timer control struct */ + SK_TIMCTRL Tim; /* Software Timer control struct */ + SK_I2C I2c; /* I2C relevant data structure */ + SK_ADDR Addr; /* for Address module */ + SK_CSUM Csum; /* for checksum module */ + SK_RLMT Rlmt; /* for rlmt module */ +#if 0 + spinlock_t SlowPathLock; /* Normal IRQ lock */ +#endif + SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */ + int RlmtMode; /* link check mode to set */ + int RlmtNets; /* Number of nets */ + + SK_IOC IoBase; /* register set of adapter */ + int BoardLevel; /* level of active hw init (0-2) */ + char DeviceStr[80]; /* adapter string from vpd */ + SK_U32 AllocFlag; /* flag allocation of resources */ +#if 0 + struct pci_dev *PciDev; /* for access to pci config space */ + SK_U32 PciDevId; /* pci device id */ +#else + int PciDev; +#endif + struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */ + char Name[30]; /* driver name */ + struct SK_NET_DEVICE *Next; /* link all devices (for clearing) */ + int RxBufSize; /* length of receive buffers */ +#if 0 + struct net_device_stats stats; /* linux 'netstat -i' statistics */ +#endif + int Index; /* internal board index number */ + + /* adapter RAM sizes for queues of active port */ + int RxQueueSize; /* memory used for receive queue */ + int TxSQueueSize; /* memory used for sync. tx queue */ + int TxAQueueSize; /* memory used for async. tx queue */ + + int PromiscCount; /* promiscuous mode counter */ + int AllMultiCount; /* allmulticast mode counter */ + int MulticCount; /* number of different MC */ + /* addresses for this board */ + /* (may be more than HW can)*/ + + int HWRevision; /* Hardware revision */ + int ActivePort; /* the active XMAC port */ + int MaxPorts; /* number of activated ports */ + int TxDescrPerRing; /* # of descriptors per tx ring */ + int RxDescrPerRing; /* # of descriptors per rx ring */ + + caddr_t pDescrMem; /* Pointer to the descriptor area */ + dma_addr_t pDescrMemDMA; /* PCI DMA address of area */ + + /* the port structures with descriptor rings */ + TX_PORT TxPort[SK_MAX_MACS][2]; + RX_PORT RxPort[SK_MAX_MACS]; + + unsigned int CsOfs1; /* for checksum calculation */ + unsigned int CsOfs2; /* for checksum calculation */ + SK_U32 CsOfs; /* for checksum calculation */ + + SK_BOOL CheckQueue; /* check event queue soon */ + + /* Only for tests */ + int PortUp; + int PortDown; + +}; + +#endif /* __INC_SKDRV2ND_H */ diff --git a/drivers/sk98lin/h/skerror.h b/drivers/sk98lin/h/skerror.h new file mode 100644 index 0000000..a454d9d --- /dev/null +++ b/drivers/sk98lin/h/skerror.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * Name: skerror.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.5 $ + * Date: $Date: 2002/04/25 11:05:10 $ + * Purpose: SK specific Error log support + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skerror.h,v $ + * Revision 1.5 2002/04/25 11:05:10 rschmidt + * Editorial changes + * + * Revision 1.4 1999/11/22 13:51:59 cgoos + * Changed license header to GPL. + * + * Revision 1.3 1999/09/14 14:04:42 rwahl + * Added error base SK_ERRBASE_PECP. + * Changed error base for driver. + * + * Revision 1.2 1998/08/11 11:15:41 gklug + * chg: comments + * + * Revision 1.1 1998/08/11 11:09:38 gklug + * add: error bases + * add: error Classes + * first version + * + * + * + ******************************************************************************/ + +#ifndef _INC_SKERROR_H_ +#define _INC_SKERROR_H_ + +/* + * Define Error Classes + */ +#define SK_ERRCL_OTHER (0) /* Other error */ +#define SK_ERRCL_CONFIG (1L<<0) /* Configuration error */ +#define SK_ERRCL_INIT (1L<<1) /* Initialization error */ +#define SK_ERRCL_NORES (1L<<2) /* Out of Resources error */ +#define SK_ERRCL_SW (1L<<3) /* Internal Software error */ +#define SK_ERRCL_HW (1L<<4) /* Hardware Failure */ +#define SK_ERRCL_COMM (1L<<5) /* Communication error */ + + +/* + * Define Error Code Bases + */ +#define SK_ERRBASE_RLMT 100 /* Base Error number for RLMT */ +#define SK_ERRBASE_HWINIT 200 /* Base Error number for HWInit */ +#define SK_ERRBASE_VPD 300 /* Base Error number for VPD */ +#define SK_ERRBASE_PNMI 400 /* Base Error number for PNMI */ +#define SK_ERRBASE_CSUM 500 /* Base Error number for Checksum */ +#define SK_ERRBASE_SIRQ 600 /* Base Error number for Special IRQ */ +#define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */ +#define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */ +#define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */ +#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */ +#define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */ + +#endif /* _INC_SKERROR_H_ */ diff --git a/drivers/sk98lin/h/skgedrv.h b/drivers/sk98lin/h/skgedrv.h new file mode 100644 index 0000000..72ba9ce --- /dev/null +++ b/drivers/sk98lin/h/skgedrv.h @@ -0,0 +1,72 @@ +/****************************************************************************** + * + * Name: skgedrv.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.6 $ + * Date: $Date: 2002/07/15 15:38:01 $ + * Purpose: Interface with the driver + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgedrv.h,v $ + * Revision 1.6 2002/07/15 15:38:01 rschmidt + * Power Management support + * Editorial changes + * + * Revision 1.5 2002/04/25 11:05:47 rschmidt + * Editorial changes + * + * Revision 1.4 1999/11/22 13:52:46 cgoos + * Changed license header to GPL. + * + * Revision 1.3 1998/12/01 13:31:39 cgoos + * SWITCH INTERN Event added. + * + * Revision 1.2 1998/11/25 08:28:38 gklug + * rmv: PORT SWITCH Event + * + * Revision 1.1 1998/09/29 06:14:07 gklug + * add: driver events (initial version) + * + * + ******************************************************************************/ + +#ifndef __INC_SKGEDRV_H_ +#define __INC_SKGEDRV_H_ + +/* defines ********************************************************************/ + +/* + * Define the driver events. + * Usually the events are defined by the destination module. + * In case of the driver we put the definition of the events here. + */ +#define SK_DRV_PORT_RESET 1 /* The port needs to be reset */ +#define SK_DRV_NET_UP 2 /* The net is operational */ +#define SK_DRV_NET_DOWN 3 /* The net is down */ +#define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */ +#define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */ +#define SK_DRV_RLMT_SEND 6 /* Send a RLMT packet */ +#define SK_DRV_ADAP_FAIL 7 /* The whole adapter fails */ +#define SK_DRV_PORT_FAIL 8 /* One port fails */ +#define SK_DRV_SWITCH_INTERN 9 /* Port switch by the driver itself */ +#define SK_DRV_POWER_DOWN 10 /* Power down mode */ + +#endif /* __INC_SKGEDRV_H_ */ diff --git a/drivers/sk98lin/h/skgehw.h b/drivers/sk98lin/h/skgehw.h new file mode 100644 index 0000000..2c98427 --- /dev/null +++ b/drivers/sk98lin/h/skgehw.h @@ -0,0 +1,2336 @@ +/****************************************************************************** + * + * Name: skgehw.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.49 $ + * Date: $Date: 2003/01/28 09:43:49 $ + * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skgehw.h,v $ + * Revision 1.49 2003/01/28 09:43:49 rschmidt + * Added defines for PCI-Spec. 2.3 IRQ + * Added defines for CLK_RUN (YUKON-Lite) + * Editorial changes + * + * Revision 1.48 2002/12/05 10:25:11 rschmidt + * Added defines for Half Duplex Burst Mode On/Off + * Added defines for Rx GMAC FIFO Flush feature + * Editorial changes + * + * Revision 1.47 2002/11/12 17:01:31 rschmidt + * Added defines for WOL_CTL_DEFAULT + * Editorial changes + * + * Revision 1.46 2002/10/14 14:47:57 rschmidt + * Corrected bit mask for HW self test results + * Added defines for WOL Registers + * Editorial changes + * + * Revision 1.45 2002/10/11 09:25:22 mkarl + * Added bit mask for HW self test results. + * + * Revision 1.44 2002/08/16 14:44:36 rschmidt + * Added define GPC_HWCFG_GMII_FIB for YUKON Fiber + * + * Revision 1.43 2002/08/12 13:31:50 rschmidt + * Corrected macros for GMAC Address Registers: GM_INADDR(), + * GM_OUTADDR(), GM_INHASH, GM_OUTHASH. + * Editorial changes + * + * Revision 1.42 2002/08/08 15:37:56 rschmidt + * Added defines for Power Management Capabilities + * Editorial changes + * + * Revision 1.41 2002/07/23 16:02:25 rschmidt + * Added macro WOL_REG() to access WOL reg. (HW-Bug in YUKON 1st rev.) + * + * Revision 1.40 2002/07/15 15:41:37 rschmidt + * Added new defines for Power Management Cap. & Control + * Editorial changes + * + * Revision 1.39 2002/06/10 09:37:07 rschmidt + * Added macros for the ADDR-Modul + * + * Revision 1.38 2002/06/05 08:15:19 rschmidt + * Added defines for WOL Registers + * Editorial changes + * + * Revision 1.37 2002/04/25 11:39:23 rschmidt + * Added new defines for PCI Our Register 1 + * Added new registers and defines for YUKON (Rx FIFO, Tx FIFO, + * Time Stamp Timer, GMAC Control, GPHY Control,Link Control, + * GMAC IRQ Source and Mask, Wake-up Frame Pattern Match); + * Added new defines for Control/Status (VAUX available) + * Added Chip ID for YUKON + * Added define for descriptors with UDP ext. for YUKON + * Added macros to access the GMAC + * Added new Phy Type for Marvell 88E1011S (GPHY) + * Editorial changes + * + * Revision 1.36 2000/11/09 12:32:49 rassmann + * Renamed variables. + * + * Revision 1.35 2000/05/19 10:17:13 cgoos + * Added inactivity check in PHY_READ (in DEBUG mode only). + * + * Revision 1.34 1999/11/22 13:53:40 cgoos + * Changed license header to GPL. + * + * Revision 1.33 1999/08/27 11:17:10 malthoff + * It's more savely to put brackets around macro parameters. + * Brackets added for PHY_READ and PHY_WRITE. + * + * Revision 1.32 1999/05/19 07:31:01 cgoos + * Changes for 1000Base-T. + * Added HWAC_LINK_LED macro. + * + * Revision 1.31 1999/03/12 13:27:40 malthoff + * Remove __STDC__. + * + * Revision 1.30 1999/02/09 09:28:20 malthoff + * Add PCI_ERRBITS. + * + * Revision 1.29 1999/01/26 08:55:48 malthoff + * Bugfix: The 16 bit field relations inside the descriptor are + * endianess dependend if the descriptor reversal feature + * (PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled. + * Drivers which use this feature has to set the define + * SK_USE_REV_DESC. + * + * Revision 1.28 1998/12/10 11:10:22 malthoff + * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted. + * + * Revision 1.27 1998/11/13 14:19:21 malthoff + * Bug Fix: The bit definition of B3_PA_CTRL has completely + * changed from HW Spec v1.3 to v1.5. + * + * Revision 1.26 1998/11/04 08:31:48 cgoos + * Fixed byte ordering in XM_OUTADDR/XM_OUTHASH macros. + * + * Revision 1.25 1998/11/04 07:16:25 cgoos + * Changed byte ordering in XM_INADDR/XM_INHASH again. + * + * Revision 1.24 1998/11/02 11:08:43 malthoff + * RxCtrl and TxCtrl must be volatile. + * + * Revision 1.23 1998/10/28 13:50:45 malthoff + * Fix: Endian support missing in XM_IN/OUT-ADDR/HASH macros. + * + * Revision 1.22 1998/10/26 08:01:36 malthoff + * RX_MFF_CTRL1 is split up into RX_MFF_CTRL1, + * RX_MFF_STAT_TO, and RX_MFF_TIST_TO. + * TX_MFF_CTRL1 is split up TX_MFF_CTRL1 and TX_MFF_WAF. + * + * Revision 1.21 1998/10/20 07:43:10 malthoff + * Fix: XM_IN/OUT/ADDR/HASH macros: + * The pointer must be casted. + * + * Revision 1.20 1998/10/19 15:53:59 malthoff + * Remove ML proto definitions. + * + * Revision 1.19 1998/10/16 14:40:17 gklug + * fix: typo B0_XM_IMSK regs + * + * Revision 1.18 1998/10/16 09:46:54 malthoff + * Remove temp defines for ML diag prototype. + * Fix register definition for B0_XM1_PHY_DATA, B0_XM1_PHY_DATA + * B0_XM2_PHY_DATA, B0_XM2_PHY_ADDR, B0_XA1_CSR, B0_XS1_CSR, + * B0_XS2_CSR, and B0_XA2_CSR. + * + * Revision 1.17 1998/10/14 06:03:14 cgoos + * Changed shifted constant to ULONG. + * + * Revision 1.16 1998/10/09 07:05:41 malthoff + * Rename ALL_PA_ENA_TO to PA_ENA_TO_ALL. + * + * Revision 1.15 1998/10/05 07:54:23 malthoff + * Split up RB_CTRL and it's bit definition into + * RB_CTRL, RB_TST1, and RB_TST2. + * Rename RB_RX_HTPP to RB_RX_LTPP. + * Add ALL_PA_ENA_TO. Modify F_WATER_MARK + * according to HW Spec. v1.5. + * Add MFF_TX_CTRL_DEF. + * + * Revision 1.14 1998/09/28 13:31:16 malthoff + * bug fix: B2_MAC_3 is 0x110 not 0x114 + * + * Revision 1.13 1998/09/24 14:42:56 malthoff + * Split the RX_MFF_TST into RX_MFF_CTRL2, + * RX_MFF_TST1, and RX_MFF_TST2. + * Rename RX_MFF_CTRL to RX_MFF_CTRL1. + * Add BMU bit CSR_SV_IDLE. + * Add macros PHY_READ() and PHY_WRITE(). + * Rename macro SK_ADDR() to SK_HW_ADDR() + * because of conflicts with the Address Module. + * + * Revision 1.12 1998/09/16 07:25:33 malthoff + * Change the parameter order in the XM_INxx and XM_OUTxx macros, + * to have the IoC as first parameter. + * + * Revision 1.11 1998/09/03 09:58:41 malthoff + * Rework the XM_xxx macros. Use {} instead of () to + * be compatible with SK_xxx macros which are defined + * with {}. + * + * Revision 1.10 1998/09/02 11:16:39 malthoff + * Temporary modify B2_I2C_SW to make tests with + * the GE/ML prototype. + * + * Revision 1.9 1998/08/19 09:11:49 gklug + * fix: struct are removed from c-source (see CCC) + * add: typedefs for all structs + * + * Revision 1.8 1998/08/18 08:27:27 malthoff + * Add some temporary workarounds to test GE + * sources with the ML. + * + * Revision 1.7 1998/07/03 14:42:26 malthoff + * bug fix: Correct macro XMA(). + * Add temporary workaround to access the PCI config space over I/O + * + * Revision 1.6 1998/06/23 11:30:36 malthoff + * Remove ';' with ',' in macors. + * + * Revision 1.5 1998/06/22 14:20:57 malthoff + * Add macro SK_ADDR(Base,Addr). + * + * Revision 1.4 1998/06/19 13:35:43 malthoff + * change 'pGec' with 'pAC' + * + * Revision 1.3 1998/06/17 14:58:16 cvs + * Lost keywords reinserted. + * + * Revision 1.1 1998/06/17 14:16:36 cvs + * created + * + * + ******************************************************************************/ + +#ifndef __INC_SKGEHW_H +#define __INC_SKGEHW_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines ********************************************************************/ + +#define BIT_31 (1UL << 31) +#define BIT_30 (1L << 30) +#define BIT_29 (1L << 29) +#define BIT_28 (1L << 28) +#define BIT_27 (1L << 27) +#define BIT_26 (1L << 26) +#define BIT_25 (1L << 25) +#define BIT_24 (1L << 24) +#define BIT_23 (1L << 23) +#define BIT_22 (1L << 22) +#define BIT_21 (1L << 21) +#define BIT_20 (1L << 20) +#define BIT_19 (1L << 19) +#define BIT_18 (1L << 18) +#define BIT_17 (1L << 17) +#define BIT_16 (1L << 16) +#define BIT_15 (1L << 15) +#define BIT_14 (1L << 14) +#define BIT_13 (1L << 13) +#define BIT_12 (1L << 12) +#define BIT_11 (1L << 11) +#define BIT_10 (1L << 10) +#define BIT_9 (1L << 9) +#define BIT_8 (1L << 8) +#define BIT_7 (1L << 7) +#define BIT_6 (1L << 6) +#define BIT_5 (1L << 5) +#define BIT_4 (1L << 4) +#define BIT_3 (1L << 3) +#define BIT_2 (1L << 2) +#define BIT_1 (1L << 1) +#define BIT_0 1L + +#define BIT_15S (1U << 15) +#define BIT_14S (1 << 14) +#define BIT_13S (1 << 13) +#define BIT_12S (1 << 12) +#define BIT_11S (1 << 11) +#define BIT_10S (1 << 10) +#define BIT_9S (1 << 9) +#define BIT_8S (1 << 8) +#define BIT_7S (1 << 7) +#define BIT_6S (1 << 6) +#define BIT_5S (1 << 5) +#define BIT_4S (1 << 4) +#define BIT_3S (1 << 3) +#define BIT_2S (1 << 2) +#define BIT_1S (1 << 1) +#define BIT_0S 1 + +#define SHIFT31(x) ((x) << 31) +#define SHIFT30(x) ((x) << 30) +#define SHIFT29(x) ((x) << 29) +#define SHIFT28(x) ((x) << 28) +#define SHIFT27(x) ((x) << 27) +#define SHIFT26(x) ((x) << 26) +#define SHIFT25(x) ((x) << 25) +#define SHIFT24(x) ((x) << 24) +#define SHIFT23(x) ((x) << 23) +#define SHIFT22(x) ((x) << 22) +#define SHIFT21(x) ((x) << 21) +#define SHIFT20(x) ((x) << 20) +#define SHIFT19(x) ((x) << 19) +#define SHIFT18(x) ((x) << 18) +#define SHIFT17(x) ((x) << 17) +#define SHIFT16(x) ((x) << 16) +#define SHIFT15(x) ((x) << 15) +#define SHIFT14(x) ((x) << 14) +#define SHIFT13(x) ((x) << 13) +#define SHIFT12(x) ((x) << 12) +#define SHIFT11(x) ((x) << 11) +#define SHIFT10(x) ((x) << 10) +#define SHIFT9(x) ((x) << 9) +#define SHIFT8(x) ((x) << 8) +#define SHIFT7(x) ((x) << 7) +#define SHIFT6(x) ((x) << 6) +#define SHIFT5(x) ((x) << 5) +#define SHIFT4(x) ((x) << 4) +#define SHIFT3(x) ((x) << 3) +#define SHIFT2(x) ((x) << 2) +#define SHIFT1(x) ((x) << 1) +#define SHIFT0(x) ((x) << 0) + +/* + * Configuration Space header + * Since this module is used for different OS', those may be + * duplicate on some of them (e.g. Linux). But to keep the + * common source, we have to live with this... + */ +#define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */ +#define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */ +#define PCI_COMMAND 0x04 /* 16 bit Command */ +#define PCI_STATUS 0x06 /* 16 bit Status */ +#define PCI_REV_ID 0x08 /* 8 bit Revision ID */ +#if 0 +#define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */ +#endif +#define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */ +#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */ +#define PCI_HEADER_T 0x0e /* 8 bit Header Type */ +#define PCI_BIST 0x0f /* 8 bit Built-in selftest */ +#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ +#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ + /* Byte 0x18..0x2b: reserved */ +#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */ +#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */ +#define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */ +#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */ + /* Byte 35..3b: reserved */ +#define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */ +#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */ +#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */ +#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */ + /* Device Dependent Region */ +#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ +#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ + /* Power Management Region */ +#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */ +#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */ +#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */ +#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */ + /* Byte 0x4e: reserved */ +#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */ + /* VPD Region */ +#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */ +#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */ +#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */ +#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */ + /* Byte 0x58..0xff: reserved */ + +/* + * I2C Address (PCI Config) + * + * Note: The temperature and voltage sensors are relocated on a different + * I2C bus. + */ +#define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */ + +/* + * Define Bits and Values of the registers + */ +/* PCI_COMMAND 16 bit Command */ + /* Bit 15..11: reserved */ +#define PCI_INT_DIS BIT_10S /* Interrupt INTx# disable (PCI 2.3) */ +#define PCI_FBTEN BIT_9S /* Fast Back-To-Back enable */ +#define PCI_SERREN BIT_8S /* SERR enable */ +#define PCI_ADSTEP BIT_7S /* Address Stepping */ +#define PCI_PERREN BIT_6S /* Parity Report Response enable */ +#define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */ +#define PCI_MWIEN BIT_4S /* Memory write an inv cycl ena */ +#define PCI_SCYCEN BIT_3S /* Special Cycle enable */ +#define PCI_BMEN BIT_2S /* Bus Master enable */ +#define PCI_MEMEN BIT_1S /* Memory Space Access enable */ +#define PCI_IOEN BIT_0S /* I/O Space Access enable */ + +#define PCI_COMMAND_VAL (PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\ + PCI_BMEN | PCI_MEMEN | PCI_IOEN) + +/* PCI_STATUS 16 bit Status */ +#define PCI_PERR BIT_15S /* Parity Error */ +#define PCI_SERR BIT_14S /* Signaled SERR */ +#define PCI_RMABORT BIT_13S /* Received Master Abort */ +#define PCI_RTABORT BIT_12S /* Received Target Abort */ + /* Bit 11: reserved */ +#define PCI_DEVSEL (3<<9) /* Bit 10.. 9: DEVSEL Timing */ +#define PCI_DEV_FAST (0<<9) /* fast */ +#define PCI_DEV_MEDIUM (1<<9) /* medium */ +#define PCI_DEV_SLOW (2<<9) /* slow */ +#define PCI_DATAPERR BIT_8S /* DATA Parity error detected */ +#define PCI_FB2BCAP BIT_7S /* Fast Back-to-Back Capability */ +#define PCI_UDF BIT_6S /* User Defined Features */ +#define PCI_66MHZCAP BIT_5S /* 66 MHz PCI bus clock capable */ +#define PCI_NEWCAP BIT_4S /* New cap. list implemented */ +#define PCI_INT_STAT BIT_3S /* Interrupt INTx# Status (PCI 2.3) */ + /* Bit 2.. 0: reserved */ + +#define PCI_ERRBITS (PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\ + PCI_DATAPERR) + +/* PCI_CLASS_CODE 24 bit Class Code */ +/* Byte 2: Base Class (02) */ +/* Byte 1: SubClass (00) */ +/* Byte 0: Programming Interface (00) */ + +/* PCI_CACHE_LSZ 8 bit Cache Line Size */ +/* Possible values: 0,2,4,8,16,32,64,128 */ + +/* PCI_HEADER_T 8 bit Header Type */ +#define PCI_HD_MF_DEV BIT_7S /* 0= single, 1= multi-func dev */ +#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */ + +/* PCI_BIST 8 bit Built-in selftest */ +/* Built-in Self test not supported (optional) */ + +/* PCI_BASE_1ST 32 bit 1st Base address */ +#define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */ +#define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */ +#define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */ +#define PCI_PREFEN BIT_3 /* Prefetchable */ +#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */ +#define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */ +#define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */ +#define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */ +#define PCI_MEMSPACE BIT_0 /* Memory Space Indic. */ + +/* PCI_BASE_2ND 32 bit 2nd Base address */ +#define PCI_IOBASE 0xffffff00L /* Bit 31.. 8: I/O Base address */ +#define PCI_IOSIZE 0x000000fcL /* Bit 7.. 2: I/O Size Requirements */ + /* Bit 1: reserved */ +#define PCI_IOSPACE BIT_0 /* I/O Space Indicator */ + +/* PCI_BASE_ROM 32 bit Expansion ROM Base Address */ +#define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st)*/ +#define PCI_ROMBASZ (0x1cL<<14) /* Bit 16..14: Treat as BASE or SIZE */ +#define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */ + /* Bit 10.. 1: reserved */ +#define PCI_ROMEN BIT_0 /* Address Decode enable */ + +/* Device Dependent Region */ +/* PCI_OUR_REG_1 32 bit Our Register 1 */ + /* Bit 31..29: reserved */ +#define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode */ +#define PCI_EN_CAL BIT_27 /* Enable PCI buffer strength calibr. */ +#define PCI_DIS_CAL BIT_26 /* Disable PCI buffer strength calibr. */ +#define PCI_VIO BIT_25 /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */ +#define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ +#define PCI_EN_IO BIT_23 /* Mapping to I/O space */ +#define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ + /* 1 = Map Flash to memory */ + /* 0 = Disable addr. dec */ +#define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */ +#define PCI_PAGE_16 (0L<<20) /* 16 k pages */ +#define PCI_PAGE_32K (1L<<20) /* 32 k pages */ +#define PCI_PAGE_64K (2L<<20) /* 64 k pages */ +#define PCI_PAGE_128K (3L<<20) /* 128 k pages */ + /* Bit 19: reserved */ +#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */ +#define PCI_NOTAR BIT_15 /* No turnaround cycle */ +#define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ +#define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ +#define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ +#define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ +#define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ +#define PCI_BURST_DIS BIT_9 /* Burst Disable */ +#define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ +#define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */ +#define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ + + +/* PCI_OUR_REG_2 32 bit Our Register 2 */ +#define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */ +#define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */ +#define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */ + /* Bit 13..12: reserved */ +#define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ +#define PCI_PATCH_DIR_3 BIT_11 +#define PCI_PATCH_DIR_2 BIT_10 +#define PCI_PATCH_DIR_1 BIT_9 +#define PCI_PATCH_DIR_0 BIT_8 +#define PCI_EXT_PATCHS (0xfL<<4) /* Bit 7.. 4: Extended Patches 3..0 */ +#define PCI_EXT_PATCH_3 BIT_7 +#define PCI_EXT_PATCH_2 BIT_6 +#define PCI_EXT_PATCH_1 BIT_5 +#define PCI_EXT_PATCH_0 BIT_4 +#define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ +#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ + /* Bit 1: reserved */ +#define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ + + +/* Power Management Region */ +/* PCI_PM_CAP_REG 16 bit Power Management Capabilities */ +#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event Support Mask */ +#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if Vaux) */ +#define PCI_PME_D3H_SUP BIT_14S /* PME from D3hot Support */ +#define PCI_PME_D2_SUP BIT_13S /* PME from D2 Support */ +#define PCI_PME_D1_SUP BIT_12S /* PME from D1 Support */ +#define PCI_PME_D0_SUP BIT_11S /* PME from D0 Support */ +#define PCI_PM_D2_SUP BIT_10S /* D2 Support in 33 MHz mode */ +#define PCI_PM_D1_SUP BIT_9S /* D1 Support */ + /* Bit 8.. 6: reserved */ +#define PCI_PM_DSI BIT_5S /* Device Specific Initialization */ +#define PCI_PM_APS BIT_4S /* Auxialiary Power Source */ +#define PCI_PME_CLOCK BIT_3S /* PM Event Clock */ +#define PCI_PM_VER_MSK 7 /* Bit 2.. 0: PM PCI Spec. version */ + +/* PCI_PM_CTL_STS 16 bit Power Management Control/Status */ +#define PCI_PME_STATUS BIT_15S /* PME Status (YUKON only) */ +#define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: Data Reg. scaling factor */ +#define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field */ +#define PCI_PME_EN BIT_8S /* Enable PME# generation (YUKON only) */ + /* Bit 7.. 2: reserved */ +#define PCI_PM_STATE_MSK 3 /* Bit 1.. 0: Power Management State */ + +#define PCI_PM_STATE_D0 0 /* D0: Operational (default) */ +#define PCI_PM_STATE_D1 1 /* D1: (YUKON only) */ +#define PCI_PM_STATE_D2 2 /* D2: (YUKON only) */ +#define PCI_PM_STATE_D3 3 /* D3: HOT, Power Down and Reset */ + +/* VPD Region */ +/* PCI_VPD_ADR_REG 16 bit VPD Address Register */ +#define PCI_VPD_FLAG BIT_15S /* starts VPD rd/wr cycle */ +#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD address mask */ + +/* Control Register File (Address Map) */ + +/* + * Bank 0 + */ +#define B0_RAP 0x0000 /* 8 bit Register Address Port */ + /* 0x0001 - 0x0003: reserved */ +#define B0_CTST 0x0004 /* 16 bit Control/Status register */ +#define B0_LED 0x0006 /* 8 Bit LED register */ +#define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ +#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ +#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ +#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ +#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ +#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */ + /* 0x001c: reserved */ + +/* B0 XMAC 1 registers (GENESIS only) */ +#define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/ + /* 0x0022 - 0x0027: reserved */ +#define B0_XM1_ISRC 0x0028 /* 16 bit ro XMAC 1 Interrupt Status Reg */ + /* 0x002a - 0x002f: reserved */ +#define B0_XM1_PHY_ADDR 0x0030 /* 16 bit r/w XMAC 1 PHY Address Register */ + /* 0x0032 - 0x0033: reserved */ +#define B0_XM1_PHY_DATA 0x0034 /* 16 bit r/w XMAC 1 PHY Data Register */ + /* 0x0036 - 0x003f: reserved */ + +/* B0 XMAC 2 registers (GENESIS only) */ +#define B0_XM2_IMSK 0x0040 /* 16 bit r/w XMAC 2 Interrupt Mask Register*/ + /* 0x0042 - 0x0047: reserved */ +#define B0_XM2_ISRC 0x0048 /* 16 bit ro XMAC 2 Interrupt Status Reg */ + /* 0x004a - 0x004f: reserved */ +#define B0_XM2_PHY_ADDR 0x0050 /* 16 bit r/w XMAC 2 PHY Address Register */ + /* 0x0052 - 0x0053: reserved */ +#define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */ + /* 0x0056 - 0x005f: reserved */ + +/* BMU Control Status Registers */ +#define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */ +#define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */ +#define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ +#define B0_XA1_CSR 0x006c /* 32 bit BMU Ctrl/Stat Async Tx Queue 1*/ +#define B0_XS2_CSR 0x0070 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ +#define B0_XA2_CSR 0x0074 /* 32 bit BMU Ctrl/Stat Async Tx Queue 2*/ + /* 0x0078 - 0x007f: reserved */ + +/* + * Bank 1 + * - completely empty (this is the RAP Block window) + * Note: if RAP = 1 this page is reserved + */ + +/* + * Bank 2 + */ +/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ +#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ + /* 0x0106 - 0x0107: reserved */ +#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ + /* 0x010e - 0x010f: reserved */ +#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ + /* 0x0116 - 0x0117: reserved */ +#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ +#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ +#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ +#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ + /* Eprom registers are currently of no use */ +#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ +#define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */ +#define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */ +#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ +#define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */ +#define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */ + /* 0x0125 - 0x0127: reserved */ +#define B2_LD_CRTL 0x0128 /* 8 bit EPROM loader control register */ +#define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */ + /* 0x012a - 0x012f: reserved */ +#define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ +#define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ +#define B2_TI_CRTL 0x0138 /* 8 bit Timer Control */ +#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ + /* 0x013a - 0x013f: reserved */ +#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ +#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ +#define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ +#define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ +#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ +#define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ + /* 0x0154 - 0x0157: reserved */ +#define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ +#define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ + /* 0x015a - 0x015b: reserved */ +#define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ +#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ +#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ +#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ +#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ + +/* Blink Source Counter (GENESIS only) */ +#define B2_BSC_INI 0x0170 /* 32 bit Blink Source Counter Init Val */ +#define B2_BSC_VAL 0x0174 /* 32 bit Blink Source Counter Value */ +#define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */ +#define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */ +#define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */ + /* 0x017c - 0x017f: reserved */ + +/* + * Bank 3 + */ +/* RAM Random Registers */ +#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ +#define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ +#define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ + /* 0x018c - 0x018f: reserved */ + +/* RAM Interface Registers */ +/* + * The HW-Spec. calls this registers Timeout Value 0..11. But this names are + * not usable in SW. Please notice these are NOT real timeouts, these are + * the number of qWords transferred continuously. + */ +#define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ +#define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ +#define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ +#define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ +#define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ +#define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ +#define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ +#define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ +#define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ +#define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ +#define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ +#define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ +#define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ + /* 0x019d - 0x019f: reserved */ +#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ +#define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ + /* 0x01a3 - 0x01af: reserved */ + +/* MAC Arbiter Registers (GENESIS only) */ +/* these are the no. of qWord transferred continuously and NOT real timeouts */ +#define B3_MA_TOINI_RX1 0x01b0 /* 8 bit Timeout Init Val Rx Path MAC 1 */ +#define B3_MA_TOINI_RX2 0x01b1 /* 8 bit Timeout Init Val Rx Path MAC 2 */ +#define B3_MA_TOINI_TX1 0x01b2 /* 8 bit Timeout Init Val Tx Path MAC 1 */ +#define B3_MA_TOINI_TX2 0x01b3 /* 8 bit Timeout Init Val Tx Path MAC 2 */ +#define B3_MA_TOVAL_RX1 0x01b4 /* 8 bit Timeout Value Rx Path MAC 1 */ +#define B3_MA_TOVAL_RX2 0x01b5 /* 8 bit Timeout Value Rx Path MAC 1 */ +#define B3_MA_TOVAL_TX1 0x01b6 /* 8 bit Timeout Value Tx Path MAC 2 */ +#define B3_MA_TOVAL_TX2 0x01b7 /* 8 bit Timeout Value Tx Path MAC 2 */ +#define B3_MA_TO_CTRL 0x01b8 /* 16 bit MAC Arbiter Timeout Ctrl Reg */ +#define B3_MA_TO_TEST 0x01ba /* 16 bit MAC Arbiter Timeout Test Reg */ + /* 0x01bc - 0x01bf: reserved */ +#define B3_MA_RCINI_RX1 0x01c0 /* 8 bit Recovery Init Val Rx Path MAC 1 */ +#define B3_MA_RCINI_RX2 0x01c1 /* 8 bit Recovery Init Val Rx Path MAC 2 */ +#define B3_MA_RCINI_TX1 0x01c2 /* 8 bit Recovery Init Val Tx Path MAC 1 */ +#define B3_MA_RCINI_TX2 0x01c3 /* 8 bit Recovery Init Val Tx Path MAC 2 */ +#define B3_MA_RCVAL_RX1 0x01c4 /* 8 bit Recovery Value Rx Path MAC 1 */ +#define B3_MA_RCVAL_RX2 0x01c5 /* 8 bit Recovery Value Rx Path MAC 1 */ +#define B3_MA_RCVAL_TX1 0x01c6 /* 8 bit Recovery Value Tx Path MAC 2 */ +#define B3_MA_RCVAL_TX2 0x01c7 /* 8 bit Recovery Value Tx Path MAC 2 */ +#define B3_MA_RC_CTRL 0x01c8 /* 16 bit MAC Arbiter Recovery Ctrl Reg */ +#define B3_MA_RC_TEST 0x01ca /* 16 bit MAC Arbiter Recovery Test Reg */ + /* 0x01cc - 0x01cf: reserved */ + +/* Packet Arbiter Registers (GENESIS only) */ +/* these are real timeouts */ +#define B3_PA_TOINI_RX1 0x01d0 /* 16 bit Timeout Init Val Rx Path MAC 1 */ + /* 0x01d2 - 0x01d3: reserved */ +#define B3_PA_TOINI_RX2 0x01d4 /* 16 bit Timeout Init Val Rx Path MAC 2 */ + /* 0x01d6 - 0x01d7: reserved */ +#define B3_PA_TOINI_TX1 0x01d8 /* 16 bit Timeout Init Val Tx Path MAC 1 */ + /* 0x01da - 0x01db: reserved */ +#define B3_PA_TOINI_TX2 0x01dc /* 16 bit Timeout Init Val Tx Path MAC 2 */ + /* 0x01de - 0x01df: reserved */ +#define B3_PA_TOVAL_RX1 0x01e0 /* 16 bit Timeout Val Rx Path MAC 1 */ + /* 0x01e2 - 0x01e3: reserved */ +#define B3_PA_TOVAL_RX2 0x01e4 /* 16 bit Timeout Val Rx Path MAC 2 */ + /* 0x01e6 - 0x01e7: reserved */ +#define B3_PA_TOVAL_TX1 0x01e8 /* 16 bit Timeout Val Tx Path MAC 1 */ + /* 0x01ea - 0x01eb: reserved */ +#define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */ + /* 0x01ee - 0x01ef: reserved */ +#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */ +#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */ + /* 0x01f4 - 0x01ff: reserved */ + +/* + * Bank 4 - 5 + */ +/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ +#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ +#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ +#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ +#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ +#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ +#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ +#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ + /* 0x0213 - 0x027f: reserved */ + /* 0x0280 - 0x0292: MAC 2 */ + /* 0x0213 - 0x027f: reserved */ + +/* + * Bank 6 + */ +/* External registers (GENESIS only) */ +#define B6_EXT_REG 0x0300 + +/* + * Bank 7 + */ +/* This is a copy of the Configuration register file (lower half) */ +#define B7_CFG_SPC 0x0380 + +/* + * Bank 8 - 15 + */ +/* Receive and Transmit Queue Registers, use Q_ADDR() to access */ +#define B8_Q_REGS 0x0400 + +/* Queue Register Offsets, use Q_ADDR() to access */ +#define Q_D 0x00 /* 8*32 bit Current Descriptor */ +#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ +#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */ +#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ +#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ +#define Q_BC 0x30 /* 32 bit Current Byte Counter */ +#define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ +#define Q_F 0x38 /* 32 bit Flag Register */ +#define Q_T1 0x3c /* 32 bit Test Register 1 */ +#define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ +#define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ +#define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ +#define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ +#define Q_T2 0x40 /* 32 bit Test Register 2 */ +#define Q_T3 0x44 /* 32 bit Test Register 3 */ + /* 0x48 - 0x7f: reserved */ + +/* + * Bank 16 - 23 + */ +/* RAM Buffer Registers */ +#define B16_RAM_REGS 0x0800 + +/* RAM Buffer Register Offsets, use RB_ADDR() to access */ +#define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ +#define RB_END 0x04 /* 32 bit RAM Buffer End Address */ +#define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ +#define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ +#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack */ +#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack */ +#define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ +#define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ + /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ +#define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ +#define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ +#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ +#define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ +#define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */ + /* 0x2c - 0x7f: reserved */ + +/* + * Bank 24 + */ +/* + * Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) + * use MR_ADDR() to access + */ +#define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */ +#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */ + /* 0x0c08 - 0x0c0b: reserved */ +#define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */ +#define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */ +#define RX_MFF_LEV 0x0c14 /* 32 bit Receive MAC FIFO Level */ +#define RX_MFF_CTRL1 0x0c18 /* 16 bit Receive MAC FIFO Control Reg 1*/ +#define RX_MFF_STAT_TO 0x0c1a /* 8 bit Receive MAC Status Timeout */ +#define RX_MFF_TIST_TO 0x0c1b /* 8 bit Receive MAC Time Stamp Timeout */ +#define RX_MFF_CTRL2 0x0c1c /* 8 bit Receive MAC FIFO Control Reg 2*/ +#define RX_MFF_TST1 0x0c1d /* 8 bit Receive MAC FIFO Test Reg 1 */ +#define RX_MFF_TST2 0x0c1e /* 8 bit Receive MAC FIFO Test Reg 2 */ + /* 0x0c1f: reserved */ +#define RX_LED_INI 0x0c20 /* 32 bit Receive LED Cnt Init Value */ +#define RX_LED_VAL 0x0c24 /* 32 bit Receive LED Cnt Current Value */ +#define RX_LED_CTRL 0x0c28 /* 8 bit Receive LED Cnt Control Reg */ +#define RX_LED_TST 0x0c29 /* 8 bit Receive LED Cnt Test Register */ + /* 0x0c2a - 0x0c2f: reserved */ +#define LNK_SYNC_INI 0x0c30 /* 32 bit Link Sync Cnt Init Value */ +#define LNK_SYNC_VAL 0x0c34 /* 32 bit Link Sync Cnt Current Value */ +#define LNK_SYNC_CTRL 0x0c38 /* 8 bit Link Sync Cnt Control Register */ +#define LNK_SYNC_TST 0x0c39 /* 8 bit Link Sync Cnt Test Register */ + /* 0x0c3a - 0x0c3b: reserved */ +#define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */ + /* 0x0c3d - 0x0c3f: reserved */ + +/* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */ +#define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ +#define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ +#define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ +#define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ +#define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ + /* 0x0c54 - 0x0c5f: reserved */ +#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ + /* 0x0c64 - 0x0c67: reserved */ +#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ + /* 0x0c6c - 0x0c6f: reserved */ +#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ + /* 0x0c74 - 0x0c77: reserved */ +#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ + /* 0x0c7c - 0x0c7f: reserved */ + +/* + * Bank 25 + */ + /* 0x0c80 - 0x0cbf: MAC 2 */ + /* 0x0cc0 - 0x0cff: reserved */ + +/* + * Bank 26 + */ +/* + * Transmit MAC FIFO and Transmit LED Registers (GENESIS only), + * use MR_ADDR() to access + */ +#define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */ +#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */ +#define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Ptr */ +#define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */ +#define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */ +#define TX_MFF_LEV 0x0d14 /* 32 bit Transmit MAC FIFO Level */ +#define TX_MFF_CTRL1 0x0d18 /* 16 bit Transmit MAC FIFO Ctrl Reg 1 */ +#define TX_MFF_WAF 0x0d1a /* 8 bit Transmit MAC Wait after flush */ + /* 0x0c1b: reserved */ +#define TX_MFF_CTRL2 0x0d1c /* 8 bit Transmit MAC FIFO Ctrl Reg 2 */ +#define TX_MFF_TST1 0x0d1d /* 8 bit Transmit MAC FIFO Test Reg 1 */ +#define TX_MFF_TST2 0x0d1e /* 8 bit Transmit MAC FIFO Test Reg 2 */ + /* 0x0d1f: reserved */ +#define TX_LED_INI 0x0d20 /* 32 bit Transmit LED Cnt Init Value */ +#define TX_LED_VAL 0x0d24 /* 32 bit Transmit LED Cnt Current Val */ +#define TX_LED_CTRL 0x0d28 /* 8 bit Transmit LED Cnt Control Reg */ +#define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Reg */ + /* 0x0d2a - 0x0d3f: reserved */ + +/* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */ +#define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ +#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ +#define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ + /* 0x0d4c - 0x0d5f: reserved */ +#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ +#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ +#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ + /* 0x0d6c - 0x0d6f: reserved */ +#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ +#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ +#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ + /* 0x0d7c - 0x0d7f: reserved */ + +/* + * Bank 27 + */ + /* 0x0d80 - 0x0dbf: MAC 2 */ + /* 0x0daa - 0x0dff: reserved */ + +/* + * Bank 28 + */ +/* Descriptor Poll Timer Registers */ +#define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ +#define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ +#define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ + /* 0x0e09: reserved */ +#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ + /* 0x0e0b: reserved */ + +/* Time Stamp Timer Registers (YUKON only) */ + /* 0x0e10: reserved */ +#define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ +#define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ + /* 0x0e19: reserved */ +#define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ + /* 0x0e1b - 0x0e7f: reserved */ + +/* + * Bank 29 + */ + /* 0x0e80 - 0x0efc: reserved */ + +/* + * Bank 30 + */ +/* GMAC and GPHY Control Registers (YUKON only) */ +#define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ +#define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ +#define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ + /* 0x0f09 - 0x0f0b: reserved */ +#define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ + /* 0x0f0d - 0x0f0f: reserved */ +#define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ + /* 0x0f14 - 0x0f1f: reserved */ + +/* Wake-up Frame Pattern Match Control Registers (YUKON only) */ + +#define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ + +#define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ +#define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ +#define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ +#define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ +#define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ +#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Ptr */ + +/* use this macro to access above registers */ +#define WOL_REG(Reg) ((Reg) + (pAC->GIni.GIWolOffs)) + + +/* WOL Pattern Length Registers (YUKON only) */ + +#define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ +#define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ + +/* WOL Pattern Counter Registers (YUKON only) */ + +#define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ +#define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ + /* 0x0f40 - 0x0f7f: reserved */ + +/* + * Bank 31 + */ +/* 0x0f80 - 0x0fff: reserved */ + +/* + * Bank 32 - 33 + */ +#define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ + +/* + * Bank 0x22 - 0x3f + */ +/* 0x1100 - 0x1fff: reserved */ + +/* + * Bank 0x40 - 0x4f + */ +#define BASE_XMAC_1 0x2000 /* XMAC 1 registers */ + +/* + * Bank 0x50 - 0x5f + */ + +#define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ + +/* + * Bank 0x60 - 0x6f + */ +#define BASE_XMAC_2 0x3000 /* XMAC 2 registers */ + +/* + * Bank 0x70 - 0x7f + */ +#define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ + +/* + * Control Register Bit Definitions: + */ +/* B0_RAP 8 bit Register Address Port */ + /* Bit 7: reserved */ +#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0,..,6f = block 6f */ + +/* B0_CTST 16 bit Control/Status register */ + /* Bit 15..14: reserved */ +#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN hot m. (YUKON-Lite only) */ +#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN reset (YUKON-Lite only) */ +#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN enable (YUKON-Lite only) */ +#define CS_VAUX_AVAIL BIT_10S /* VAUX available (YUKON only) */ +#define CS_BUS_CLOCK BIT_9S /* Bus Clock 0/1 = 33/66 MHz */ +#define CS_BUS_SLOT_SZ BIT_8S /* Slot Size 0/1 = 32/64 bit slot */ +#define CS_ST_SW_IRQ BIT_7S /* Set IRQ SW Request */ +#define CS_CL_SW_IRQ BIT_6S /* Clear IRQ SW Request */ +#define CS_STOP_DONE BIT_5S /* Stop Master is finished */ +#define CS_STOP_MAST BIT_4S /* Command Bit to stop the master */ +#define CS_MRST_CLR BIT_3S /* Clear Master reset */ +#define CS_MRST_SET BIT_2S /* Set Master reset */ +#define CS_RST_CLR BIT_1S /* Clear Software reset */ +#define CS_RST_SET BIT_0S /* Set Software reset */ + +/* B0_LED 8 Bit LED register */ + /* Bit 7.. 2: reserved */ +#define LED_STAT_ON BIT_1S /* Status LED on */ +#define LED_STAT_OFF BIT_0S /* Status LED off */ + +/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ +#define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ +#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ +#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ +#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ +#define PC_VAUX_ON BIT_3 /* Switch VAUX On */ +#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ +#define PC_VCC_ON BIT_1 /* Switch VCC On */ +#define PC_VCC_OFF BIT_0 /* Switch VCC Off */ + +/* B0_ISRC 32 bit Interrupt Source Register */ +/* B0_IMSK 32 bit Interrupt Mask Register */ +/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ +#define IS_ALL_MSK 0xbfffffffL /* All Interrupt bits */ +#define IS_HW_ERR BIT_31 /* Interrupt HW Error */ + /* Bit 30: reserved */ +#define IS_PA_TO_RX1 BIT_29 /* Packet Arb Timeout Rx1 */ +#define IS_PA_TO_RX2 BIT_28 /* Packet Arb Timeout Rx2 */ +#define IS_PA_TO_TX1 BIT_27 /* Packet Arb Timeout Tx1 */ +#define IS_PA_TO_TX2 BIT_26 /* Packet Arb Timeout Tx2 */ +#define IS_I2C_READY BIT_25 /* IRQ on end of I2C Tx */ +#define IS_IRQ_SW BIT_24 /* SW forced IRQ */ +#define IS_EXT_REG BIT_23 /* IRQ from LM80 or PHY (GENESIS only) */ + /* IRQ from PHY (YUKON only) */ +#define IS_TIMINT BIT_22 /* IRQ from Timer */ +#define IS_MAC1 BIT_21 /* IRQ from MAC 1 */ +#define IS_LNK_SYNC_M1 BIT_20 /* Link Sync Cnt wrap MAC 1 */ +#define IS_MAC2 BIT_19 /* IRQ from MAC 2 */ +#define IS_LNK_SYNC_M2 BIT_18 /* Link Sync Cnt wrap MAC 2 */ +/* Receive Queue 1 */ +#define IS_R1_B BIT_17 /* Q_R1 End of Buffer */ +#define IS_R1_F BIT_16 /* Q_R1 End of Frame */ +#define IS_R1_C BIT_15 /* Q_R1 Encoding Error */ +/* Receive Queue 2 */ +#define IS_R2_B BIT_14 /* Q_R2 End of Buffer */ +#define IS_R2_F BIT_13 /* Q_R2 End of Frame */ +#define IS_R2_C BIT_12 /* Q_R2 Encoding Error */ +/* Synchronous Transmit Queue 1 */ +#define IS_XS1_B BIT_11 /* Q_XS1 End of Buffer */ +#define IS_XS1_F BIT_10 /* Q_XS1 End of Frame */ +#define IS_XS1_C BIT_9 /* Q_XS1 Encoding Error */ +/* Asynchronous Transmit Queue 1 */ +#define IS_XA1_B BIT_8 /* Q_XA1 End of Buffer */ +#define IS_XA1_F BIT_7 /* Q_XA1 End of Frame */ +#define IS_XA1_C BIT_6 /* Q_XA1 Encoding Error */ +/* Synchronous Transmit Queue 2 */ +#define IS_XS2_B BIT_5 /* Q_XS2 End of Buffer */ +#define IS_XS2_F BIT_4 /* Q_XS2 End of Frame */ +#define IS_XS2_C BIT_3 /* Q_XS2 Encoding Error */ +/* Asynchronous Transmit Queue 2 */ +#define IS_XA2_B BIT_2 /* Q_XA2 End of Buffer */ +#define IS_XA2_F BIT_1 /* Q_XA2 End of Frame */ +#define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */ + + +/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ +/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ +#define IS_ERR_MSK 0x00000fffL /* All Error bits */ + /* Bit 31..14: reserved */ +#define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */ +#define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */ +#define IS_IRQ_MST_ERR BIT_11 /* IRQ master error detected */ +#define IS_IRQ_STAT BIT_10 /* IRQ status exception */ +#define IS_NO_STAT_M1 BIT_9 /* No Rx Status from MAC 1 */ +#define IS_NO_STAT_M2 BIT_8 /* No Rx Status from MAC 2 */ +#define IS_NO_TIST_M1 BIT_7 /* No Time Stamp from MAC 1 */ +#define IS_NO_TIST_M2 BIT_6 /* No Time Stamp from MAC 2 */ +#define IS_RAM_RD_PAR BIT_5 /* RAM Read Parity Error */ +#define IS_RAM_WR_PAR BIT_4 /* RAM Write Parity Error */ +#define IS_M1_PAR_ERR BIT_3 /* MAC 1 Parity Error */ +#define IS_M2_PAR_ERR BIT_2 /* MAC 2 Parity Error */ +#define IS_R1_PAR_ERR BIT_1 /* Queue R1 Parity Error */ +#define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */ + +/* B2_CONN_TYP 8 bit Connector type */ +/* B2_PMD_TYP 8 bit PMD type */ +/* Values of connector and PMD type comply to SysKonnect internal std */ + +/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ +#define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */ + /* Bit 3.. 2: reserved */ +#define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */ +#define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/ + +/* B2_CHIP_ID 8 bit Chip Identification Number */ +#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ +#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ + +/* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */ +#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address mask */ + +/* B2_LD_CRTL 8 bit EPROM loader control register */ +/* Bits are currently reserved */ + +/* B2_LD_TEST 8 bit EPROM loader test register */ + /* Bit 7.. 4: reserved */ +#define LD_T_ON BIT_3S /* Loader Test mode on */ +#define LD_T_OFF BIT_2S /* Loader Test mode off */ +#define LD_T_STEP BIT_1S /* Decrement FPROM addr. Counter */ +#define LD_START BIT_0S /* Start loading FPROM */ + +/* + * Timer Section + */ +/* B2_TI_CRTL 8 bit Timer control */ +/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ + /* Bit 7.. 3: reserved */ +#define TIM_START BIT_2S /* Start Timer */ +#define TIM_STOP BIT_1S /* Stop Timer */ +#define TIM_CLR_IRQ BIT_0S /* Clear Timer IRQ (!IRQM) */ + +/* B2_TI_TEST 8 Bit Timer Test */ +/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ +/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ + /* Bit 7.. 3: reserved */ +#define TIM_T_ON BIT_2S /* Test mode on */ +#define TIM_T_OFF BIT_1S /* Test mode off */ +#define TIM_T_STEP BIT_0S /* Test step */ + +/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */ +/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */ + /* Bit 31..24: reserved */ +#define DPT_MSK 0x00ffffffL /* Bit 23.. 0: Desc Poll Timer Bits */ + +/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ + /* Bit 7.. 2: reserved */ +#define DPT_START BIT_1S /* Start Descriptor Poll Timer */ +#define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */ + +/* B2_E_3 8 bit lower 4 bits used for HW self test result */ +#define B2_E3_RES_MASK 0x0f + +/* B2_TST_CTRL1 8 bit Test Control Register 1 */ +#define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */ +#define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */ +#define TST_FRC_DPERR_TR BIT_5S /* force DATAPERR on TRG RD */ +#define TST_FRC_DPERR_TW BIT_4S /* force DATAPERR on TRG WR */ +#define TST_FRC_APERR_M BIT_3S /* force ADDRPERR on MST */ +#define TST_FRC_APERR_T BIT_2S /* force ADDRPERR on TRG */ +#define TST_CFG_WRITE_ON BIT_1S /* Enable Config Reg WR */ +#define TST_CFG_WRITE_OFF BIT_0S /* Disable Config Reg WR */ + +/* B2_TST_CTRL2 8 bit Test Control Register 2 */ + /* Bit 7.. 4: reserved */ + /* force the following error on the next master read/write */ +#define TST_FRC_DPERR_MR64 BIT_3S /* DataPERR RD 64 */ +#define TST_FRC_DPERR_MW64 BIT_2S /* DataPERR WR 64 */ +#define TST_FRC_APERR_1M64 BIT_1S /* AddrPERR on 1. phase */ +#define TST_FRC_APERR_2M64 BIT_0S /* AddrPERR on 2. phase */ + +/* B2_GP_IO 32 bit General Purpose I/O Register */ + /* Bit 31..26: reserved */ +#define GP_DIR_9 BIT_25 /* IO_9 direct, 0=I/1=O */ +#define GP_DIR_8 BIT_24 /* IO_8 direct, 0=I/1=O */ +#define GP_DIR_7 BIT_23 /* IO_7 direct, 0=I/1=O */ +#define GP_DIR_6 BIT_22 /* IO_6 direct, 0=I/1=O */ +#define GP_DIR_5 BIT_21 /* IO_5 direct, 0=I/1=O */ +#define GP_DIR_4 BIT_20 /* IO_4 direct, 0=I/1=O */ +#define GP_DIR_3 BIT_19 /* IO_3 direct, 0=I/1=O */ +#define GP_DIR_2 BIT_18 /* IO_2 direct, 0=I/1=O */ +#define GP_DIR_1 BIT_17 /* IO_1 direct, 0=I/1=O */ +#define GP_DIR_0 BIT_16 /* IO_0 direct, 0=I/1=O */ + /* Bit 15..10: reserved */ +#define GP_IO_9 BIT_9 /* IO_9 pin */ +#define GP_IO_8 BIT_8 /* IO_8 pin */ +#define GP_IO_7 BIT_7 /* IO_7 pin */ +#define GP_IO_6 BIT_6 /* IO_6 pin */ +#define GP_IO_5 BIT_5 /* IO_5 pin */ +#define GP_IO_4 BIT_4 /* IO_4 pin */ +#define GP_IO_3 BIT_3 /* IO_3 pin */ +#define GP_IO_2 BIT_2 /* IO_2 pin */ +#define GP_IO_1 BIT_1 /* IO_1 pin */ +#define GP_IO_0 BIT_0 /* IO_0 pin */ + +/* B2_I2C_CTRL 32 bit I2C HW Control Register */ +#define I2C_FLAG BIT_31 /* Start read/write if WR */ +#define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */ +#define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */ + /* Bit 8.. 5: reserved */ +#define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ +#define I2C_DEV_SIZE (7L<<1) /* Bit 3.. 1: I2C Device Size */ +#define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smal. */ +#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ +#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */ +#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */ +#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */ +#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */ +#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */ +#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */ +#define I2C_STOP BIT_0 /* Interrupt I2C transfer */ + +/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ + /* Bit 31.. 1 reserved */ +#define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ + +/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ + /* Bit 7.. 3: reserved */ +#define I2C_DATA_DIR BIT_2S /* direction of I2C_DATA */ +#define I2C_DATA BIT_1S /* I2C Data Port */ +#define I2C_CLK BIT_0S /* I2C Clock Port */ + +/* + * I2C Address + */ +#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/ + + +/* B2_BSC_CTRL 8 bit Blink Source Counter Control */ + /* Bit 7.. 2: reserved */ +#define BSC_START BIT_1S /* Start Blink Source Counter */ +#define BSC_STOP BIT_0S /* Stop Blink Source Counter */ + +/* B2_BSC_STAT 8 bit Blink Source Counter Status */ + /* Bit 7.. 1: reserved */ +#define BSC_SRC BIT_0S /* Blink Source, 0=Off / 1=On */ + +/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ +#define BSC_T_ON BIT_2S /* Test mode on */ +#define BSC_T_OFF BIT_1S /* Test mode off */ +#define BSC_T_STEP BIT_0S /* Test step */ + + +/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ + /* Bit 31..19: reserved */ +#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ + +/* RAM Interface Registers */ +/* B3_RI_CTRL 16 bit RAM Iface Control Register */ + /* Bit 15..10: reserved */ +#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */ +#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err*/ + /* Bit 7.. 2: reserved */ +#define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */ +#define RI_RST_SET BIT_0S /* Set RAM Interface Reset */ + +/* B3_RI_TEST 8 bit RAM Iface Test Register */ + /* Bit 15.. 4: reserved */ +#define RI_T_EV BIT_3S /* Timeout Event occured */ +#define RI_T_ON BIT_2S /* Timeout Timer Test On */ +#define RI_T_OFF BIT_1S /* Timeout Timer Test Off */ +#define RI_T_STEP BIT_0S /* Timeout Timer Step */ + +/* MAC Arbiter Registers */ +/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */ + /* Bit 15.. 4: reserved */ +#define MA_FOE_ON BIT_3S /* XMAC Fast Output Enable ON */ +#define MA_FOE_OFF BIT_2S /* XMAC Fast Output Enable OFF */ +#define MA_RST_CLR BIT_1S /* Clear MAC Arbiter Reset */ +#define MA_RST_SET BIT_0S /* Set MAC Arbiter Reset */ + +/* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */ + /* Bit 15.. 8: reserved */ +#define MA_ENA_REC_TX2 BIT_7S /* Enable Recovery Timer TX2 */ +#define MA_DIS_REC_TX2 BIT_6S /* Disable Recovery Timer TX2 */ +#define MA_ENA_REC_TX1 BIT_5S /* Enable Recovery Timer TX1 */ +#define MA_DIS_REC_TX1 BIT_4S /* Disable Recovery Timer TX1 */ +#define MA_ENA_REC_RX2 BIT_3S /* Enable Recovery Timer RX2 */ +#define MA_DIS_REC_RX2 BIT_2S /* Disable Recovery Timer RX2 */ +#define MA_ENA_REC_RX1 BIT_1S /* Enable Recovery Timer RX1 */ +#define MA_DIS_REC_RX1 BIT_0S /* Disable Recovery Timer RX1 */ + +/* Packet Arbiter Registers */ +/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */ + /* Bit 15..14: reserved */ +#define PA_CLR_TO_TX2 BIT_13S /* Clear IRQ Packet Timeout TX2 */ +#define PA_CLR_TO_TX1 BIT_12S /* Clear IRQ Packet Timeout TX1 */ +#define PA_CLR_TO_RX2 BIT_11S /* Clear IRQ Packet Timeout RX2 */ +#define PA_CLR_TO_RX1 BIT_10S /* Clear IRQ Packet Timeout RX1 */ +#define PA_ENA_TO_TX2 BIT_9S /* Enable Timeout Timer TX2 */ +#define PA_DIS_TO_TX2 BIT_8S /* Disable Timeout Timer TX2 */ +#define PA_ENA_TO_TX1 BIT_7S /* Enable Timeout Timer TX1 */ +#define PA_DIS_TO_TX1 BIT_6S /* Disable Timeout Timer TX1 */ +#define PA_ENA_TO_RX2 BIT_5S /* Enable Timeout Timer RX2 */ +#define PA_DIS_TO_RX2 BIT_4S /* Disable Timeout Timer RX2 */ +#define PA_ENA_TO_RX1 BIT_3S /* Enable Timeout Timer RX1 */ +#define PA_DIS_TO_RX1 BIT_2S /* Disable Timeout Timer RX1 */ +#define PA_RST_CLR BIT_1S /* Clear MAC Arbiter Reset */ +#define PA_RST_SET BIT_0S /* Set MAC Arbiter Reset */ + +#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\ + PA_ENA_TO_TX1 | PA_ENA_TO_TX2) + +/* Rx/Tx Path related Arbiter Test Registers */ +/* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */ +/* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */ +/* B3_PA_TEST 16 bit Packet Arbiter Test Register */ +/* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */ +#define TX2_T_EV BIT_15S /* TX2 Timeout/Recv Event occured */ +#define TX2_T_ON BIT_14S /* TX2 Timeout/Recv Timer Test On */ +#define TX2_T_OFF BIT_13S /* TX2 Timeout/Recv Timer Tst Off */ +#define TX2_T_STEP BIT_12S /* TX2 Timeout/Recv Timer Step */ +#define TX1_T_EV BIT_11S /* TX1 Timeout/Recv Event occured */ +#define TX1_T_ON BIT_10S /* TX1 Timeout/Recv Timer Test On */ +#define TX1_T_OFF BIT_9S /* TX1 Timeout/Recv Timer Tst Off */ +#define TX1_T_STEP BIT_8S /* TX1 Timeout/Recv Timer Step */ +#define RX2_T_EV BIT_7S /* RX2 Timeout/Recv Event occured */ +#define RX2_T_ON BIT_6S /* RX2 Timeout/Recv Timer Test On */ +#define RX2_T_OFF BIT_5S /* RX2 Timeout/Recv Timer Tst Off */ +#define RX2_T_STEP BIT_4S /* RX2 Timeout/Recv Timer Step */ +#define RX1_T_EV BIT_3S /* RX1 Timeout/Recv Event occured */ +#define RX1_T_ON BIT_2S /* RX1 Timeout/Recv Timer Test On */ +#define RX1_T_OFF BIT_1S /* RX1 Timeout/Recv Timer Tst Off */ +#define RX1_T_STEP BIT_0S /* RX1 Timeout/Recv Timer Step */ + + +/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ +/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ +/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ +/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ +/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ + /* Bit 31..24: reserved */ +#define TXA_MAX_VAL 0x00ffffffL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ + +/* TXA_CTRL 8 bit Tx Arbiter Control Register */ +#define TXA_ENA_FSYNC BIT_7S /* Enable force of sync Tx queue */ +#define TXA_DIS_FSYNC BIT_6S /* Disable force of sync Tx queue */ +#define TXA_ENA_ALLOC BIT_5S /* Enable alloc of free bandwidth */ +#define TXA_DIS_ALLOC BIT_4S /* Disable alloc of free bandwidth */ +#define TXA_START_RC BIT_3S /* Start sync Rate Control */ +#define TXA_STOP_RC BIT_2S /* Stop sync Rate Control */ +#define TXA_ENA_ARB BIT_1S /* Enable Tx Arbiter */ +#define TXA_DIS_ARB BIT_0S /* Disable Tx Arbiter */ + +/* TXA_TEST 8 bit Tx Arbiter Test Register */ + /* Bit 7.. 6: reserved */ +#define TXA_INT_T_ON BIT_5S /* Tx Arb Interval Timer Test On */ +#define TXA_INT_T_OFF BIT_4S /* Tx Arb Interval Timer Test Off */ +#define TXA_INT_T_STEP BIT_3S /* Tx Arb Interval Timer Step */ +#define TXA_LIM_T_ON BIT_2S /* Tx Arb Limit Timer Test On */ +#define TXA_LIM_T_OFF BIT_1S /* Tx Arb Limit Timer Test Off */ +#define TXA_LIM_T_STEP BIT_0S /* Tx Arb Limit Timer Step */ + +/* TXA_STAT 8 bit Tx Arbiter Status Register */ + /* Bit 7.. 1: reserved */ +#define TXA_PRIO_XS BIT_0S /* sync queue has prio to send */ + +/* Q_BC 32 bit Current Byte Counter */ + /* Bit 31..16: reserved */ +#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ + +/* BMU Control Status Registers */ +/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ +/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ +/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ +/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ +/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ +/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ +/* Q_CSR 32 bit BMU Control/Status Register */ + /* Bit 31..25: reserved */ +#define CSR_SV_IDLE BIT_24 /* BMU SM Idle */ + /* Bit 23..22: reserved */ +#define CSR_DESC_CLR BIT_21 /* Clear Reset for Descr */ +#define CSR_DESC_SET BIT_20 /* Set Reset for Descr */ +#define CSR_FIFO_CLR BIT_19 /* Clear Reset for FIFO */ +#define CSR_FIFO_SET BIT_18 /* Set Reset for FIFO */ +#define CSR_HPI_RUN BIT_17 /* Release HPI SM */ +#define CSR_HPI_RST BIT_16 /* Reset HPI SM to Idle */ +#define CSR_SV_RUN BIT_15 /* Release Supervisor SM */ +#define CSR_SV_RST BIT_14 /* Reset Supervisor SM */ +#define CSR_DREAD_RUN BIT_13 /* Release Descr Read SM */ +#define CSR_DREAD_RST BIT_12 /* Reset Descr Read SM */ +#define CSR_DWRITE_RUN BIT_11 /* Release Descr Write SM */ +#define CSR_DWRITE_RST BIT_10 /* Reset Descr Write SM */ +#define CSR_TRANS_RUN BIT_9 /* Release Transfer SM */ +#define CSR_TRANS_RST BIT_8 /* Reset Transfer SM */ +#define CSR_ENA_POL BIT_7 /* Enable Descr Polling */ +#define CSR_DIS_POL BIT_6 /* Disable Descr Polling */ +#define CSR_STOP BIT_5 /* Stop Rx/Tx Queue */ +#define CSR_START BIT_4 /* Start Rx/Tx Queue */ +#define CSR_IRQ_CL_P BIT_3 /* (Rx) Clear Parity IRQ */ +#define CSR_IRQ_CL_B BIT_2 /* Clear EOB IRQ */ +#define CSR_IRQ_CL_F BIT_1 /* Clear EOF IRQ */ +#define CSR_IRQ_CL_C BIT_0 /* Clear ERR IRQ */ + +#define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\ + CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\ + CSR_TRANS_RST) +#define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\ + CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\ + CSR_TRANS_RUN) + +/* Q_F 32 bit Flag Register */ + /* Bit 31..28: reserved */ +#define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */ +#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ +#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ +#define F_WM_REACHED BIT_25 /* Watermark reached */ + /* reserved */ +#define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */ + /* Bit 15..11: reserved */ +#define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */ + +/* Q_T1 32 bit Test Register 1 */ +/* Holds four State Machine control Bytes */ +#define SM_CRTL_SV_MSK (0xffL<<24) /* Bit 31..24: Control Supervisor SM */ +#define SM_CRTL_RD_MSK (0xffL<<16) /* Bit 23..16: Control Read Desc SM */ +#define SM_CRTL_WR_MSK (0xffL<<8) /* Bit 15.. 8: Control Write Desc SM */ +#define SM_CRTL_TR_MSK 0xffL /* Bit 7.. 0: Control Transfer SM */ + +/* Q_T1_TR 8 bit Test Register 1 Transfer SM */ +/* Q_T1_WR 8 bit Test Register 1 Write Descriptor SM */ +/* Q_T1_RD 8 bit Test Register 1 Read Descriptor SM */ +/* Q_T1_SV 8 bit Test Register 1 Supervisor SM */ + +/* The control status byte of each machine looks like ... */ +#define SM_STATE 0xf0 /* Bit 7.. 4: State which shall be loaded */ +#define SM_LOAD BIT_3S /* Load the SM with SM_STATE */ +#define SM_TEST_ON BIT_2S /* Switch on SM Test Mode */ +#define SM_TEST_OFF BIT_1S /* Go off the Test Mode */ +#define SM_STEP BIT_0S /* Step the State Machine */ +/* The encoding of the states is not supported by the Diagnostics Tool */ + +/* Q_T2 32 bit Test Register 2 */ + /* Bit 31.. 8: reserved */ +#define T2_AC_T_ON BIT_7 /* Address Counter Test Mode on */ +#define T2_AC_T_OFF BIT_6 /* Address Counter Test Mode off */ +#define T2_BC_T_ON BIT_5 /* Byte Counter Test Mode on */ +#define T2_BC_T_OFF BIT_4 /* Byte Counter Test Mode off */ +#define T2_STEP04 BIT_3 /* Inc AC/Dec BC by 4 */ +#define T2_STEP03 BIT_2 /* Inc AC/Dec BC by 3 */ +#define T2_STEP02 BIT_1 /* Inc AC/Dec BC by 2 */ +#define T2_STEP01 BIT_0 /* Inc AC/Dec BC by 1 */ + +/* Q_T3 32 bit Test Register 3 */ + /* Bit 31.. 7: reserved */ +#define T3_MUX_MSK (7<<4) /* Bit 6.. 4: Mux Position */ + /* Bit 3: reserved */ +#define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */ + +/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ +/* RB_START 32 bit RAM Buffer Start Address */ +/* RB_END 32 bit RAM Buffer End Address */ +/* RB_WP 32 bit RAM Buffer Write Pointer */ +/* RB_RP 32 bit RAM Buffer Read Pointer */ +/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ +/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ +/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ +/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ +/* RB_PC 32 bit RAM Buffer Packet Counter */ +/* RB_LEV 32 bit RAM Buffer Level Register */ + /* Bit 31..19: reserved */ +#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ + +/* RB_TST2 8 bit RAM Buffer Test Register 2 */ + /* Bit 7.. 4: reserved */ +#define RB_PC_DEC BIT_3S /* Packet Counter Decrem */ +#define RB_PC_T_ON BIT_2S /* Packet Counter Test On */ +#define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */ +#define RB_PC_INC BIT_0S /* Packet Counter Increm */ + +/* RB_TST1 8 bit RAM Buffer Test Register 1 */ + /* Bit 7: reserved */ +#define RB_WP_T_ON BIT_6S /* Write Pointer Test On */ +#define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */ +#define RB_WP_INC BIT_4S /* Write Pointer Increm */ + /* Bit 3: reserved */ +#define RB_RP_T_ON BIT_2S /* Read Pointer Test On */ +#define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */ +#define RB_RP_DEC BIT_0S /* Read Pointer Decrement */ + +/* RB_CTRL 8 bit RAM Buffer Control Register */ + /* Bit 7.. 6: reserved */ +#define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */ +#define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */ +#define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */ +#define RB_DIS_OP_MD BIT_2S /* Disable Operation Mode */ +#define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */ +#define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */ + + +/* Receive and Transmit MAC FIFO Registers (GENESIS only) */ + +/* RX_MFF_EA 32 bit Receive MAC FIFO End Address */ +/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */ +/* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */ +/* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */ +/* RX_MFF_LEV 32 bit Receive MAC FIFO Level */ +/* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */ +/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */ +/* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */ +/* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */ +/* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */ +/* TX_MFF_LEV 32 bit Transmit MAC FIFO Level */ + /* Bit 31.. 6: reserved */ +#define MFF_MSK 0x007fL /* Bit 5.. 0: MAC FIFO Address/Ptr Bits */ + +/* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */ + /* Bit 15..14: reserved */ +#define MFF_ENA_RDY_PAT BIT_13S /* Enable Ready Patch */ +#define MFF_DIS_RDY_PAT BIT_12S /* Disable Ready Patch */ +#define MFF_ENA_TIM_PAT BIT_11S /* Enable Timing Patch */ +#define MFF_DIS_TIM_PAT BIT_10S /* Disable Timing Patch */ +#define MFF_ENA_ALM_FUL BIT_9S /* Enable AlmostFull Sign */ +#define MFF_DIS_ALM_FUL BIT_8S /* Disable AlmostFull Sign */ +#define MFF_ENA_PAUSE BIT_7S /* Enable Pause Signaling */ +#define MFF_DIS_PAUSE BIT_6S /* Disable Pause Signaling */ +#define MFF_ENA_FLUSH BIT_5S /* Enable Frame Flushing */ +#define MFF_DIS_FLUSH BIT_4S /* Disable Frame Flushing */ +#define MFF_ENA_TIST BIT_3S /* Enable Time Stamp Gener */ +#define MFF_DIS_TIST BIT_2S /* Disable Time Stamp Gener */ +#define MFF_CLR_INTIST BIT_1S /* Clear IRQ No Time Stamp */ +#define MFF_CLR_INSTAT BIT_0S /* Clear IRQ No Status */ + +#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT + +/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */ +#define MFF_CLR_PERR BIT_15S /* Clear Parity Error IRQ */ + /* Bit 14: reserved */ +#define MFF_ENA_PKT_REC BIT_13S /* Enable Packet Recovery */ +#define MFF_DIS_PKT_REC BIT_12S /* Disable Packet Recovery */ +/* MFF_ENA_TIM_PAT (see RX_MFF_CTRL1) Bit 11: Enable Timing Patch */ +/* MFF_DIS_TIM_PAT (see RX_MFF_CTRL1) Bit 10: Disable Timing Patch */ +/* MFF_ENA_ALM_FUL (see RX_MFF_CTRL1) Bit 9: Enable Almost Full Sign */ +/* MFF_DIS_ALM_FUL (see RX_MFF_CTRL1) Bit 8: Disable Almost Full Sign */ +#define MFF_ENA_W4E BIT_7S /* Enable Wait for Empty */ +#define MFF_DIS_W4E BIT_6S /* Disable Wait for Empty */ +/* MFF_ENA_FLUSH (see RX_MFF_CTRL1) Bit 5: Enable Frame Flushing */ +/* MFF_DIS_FLUSH (see RX_MFF_CTRL1) Bit 4: Disable Frame Flushing */ +#define MFF_ENA_LOOPB BIT_3S /* Enable Loopback */ +#define MFF_DIS_LOOPB BIT_2S /* Disable Loopback */ +#define MFF_CLR_MAC_RST BIT_1S /* Clear XMAC Reset */ +#define MFF_SET_MAC_RST BIT_0S /* Set XMAC Reset */ + +#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH) + +/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ +/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ + /* Bit 7: reserved */ +#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Ptr TestOn */ +#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */ +#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Ptr Increment */ +#define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */ +#define MFF_PC_T_ON BIT_2S /* Packet Counter Test On */ +#define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */ +#define MFF_PC_INC BIT_0S /* Packet Counter Increment */ + +/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */ +/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */ + /* Bit 7: reserved */ +#define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */ +#define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */ +#define MFF_WP_INC BIT_4S /* Write Pointer Increm */ + /* Bit 3: reserved */ +#define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */ +#define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */ +#define MFF_RP_DEC BIT_0S /* Read Pointer Decrement */ + +/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */ +/* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */ + /* Bit 7..4: reserved */ +#define MFF_ENA_OP_MD BIT_3S /* Enable Operation Mode */ +#define MFF_DIS_OP_MD BIT_2S /* Disable Operation Mode */ +#define MFF_RST_CLR BIT_1S /* Clear MAC FIFO Reset */ +#define MFF_RST_SET BIT_0S /* Set MAC FIFO Reset */ + + +/* Link LED Counter Registers (GENESIS only) */ + +/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */ +/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */ +/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */ + /* Bit 7.. 3: reserved */ +#define LED_START BIT_2S /* Start Timer */ +#define LED_STOP BIT_1S /* Stop Timer */ +#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */ +#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */ + +/* RX_LED_TST 8 bit Receive LED Cnt Test Register */ +/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ +/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */ + /* Bit 7.. 3: reserved */ +#define LED_T_ON BIT_2S /* LED Counter Test mode On */ +#define LED_T_OFF BIT_1S /* LED Counter Test mode Off */ +#define LED_T_STEP BIT_0S /* LED Counter Step */ + +/* LNK_LED_REG 8 bit Link LED Register */ + /* Bit 7.. 6: reserved */ +#define LED_BLK_ON BIT_5S /* Link LED Blinking On */ +#define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */ +#define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */ +#define LED_SYNC_OFF BIT_2S /* Disable Sync Wire Input */ +#define LED_ON BIT_1S /* switch LED on */ +#define LED_OFF BIT_0S /* switch LED off */ + +/* Receive and Transmit GMAC FIFO Registers (YUKON only) */ + +/* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ +/* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ +/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ +/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ +/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ +/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ +/* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ +/* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ +/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ +/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */ +/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ +/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ +/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ +/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ + +/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ + /* Bits 31..15: reserved */ +#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ +#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ +#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ + /* Bit 11: reserved */ +#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ +#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ +#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ +#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ +#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ +#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ +#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ +#define GMF_OPER_ON BIT_3 /* Operational Mode On */ +#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ +#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ +#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ + +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ + /* Bits 31..19: reserved */ +#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ +#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ +#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ + /* Bits 15..7: same as for RX_GMF_CTRL_T */ +#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ +#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ +#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ + /* Bits 3..0: same as for RX_GMF_CTRL_T */ + +#define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) +#define GMF_TX_CTRL_DEF GMF_OPER_ON + +#define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ + +/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ + /* Bit 7.. 3: reserved */ +#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */ +#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */ +#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */ + +/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ + /* Bits 31.. 8: reserved */ +#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ +#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ +#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ +#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ +#define GMC_PAUSE_ON BIT_3 /* Pause On */ +#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ +#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ +#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ + +/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ + /* Bits 31..29: reserved */ +#define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ +#define GPC_INT_POL_HI BIT_27 /* IRQ Polarity is Active HIGH */ +#define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ +#define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ +#define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ +#define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ +#define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ +#define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ +#define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ +#define GPC_ANEG_0 BIT_19 /* ANEG[0] */ +#define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ +#define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ +#define GPC_ANEG_3 BIT_16 /* ANEG[3] */ +#define GPC_ANEG_2 BIT_15 /* ANEG[2] */ +#define GPC_ANEG_1 BIT_14 /* ANEG[1] */ +#define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ +#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ +#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ +#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ +#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ +#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ + /* Bits 7..2: reserved */ +#define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ +#define GPC_RST_SET BIT_0 /* Set GPHY Reset */ + +#define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \ + GPC_HWCFG_M_1 | GPC_HWCFG_M_0) + +#define GPC_HWCFG_GMII_FIB ( GPC_HWCFG_M_2 | \ + GPC_HWCFG_M_1 | GPC_HWCFG_M_0) + +#define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | \ + GPC_ANEG_1 | GPC_ANEG_0) + +/* forced speed and duplex mode (don't mix with other ANEG bits) */ +#define GPC_FRC10MBIT_HALF 0 +#define GPC_FRC10MBIT_FULL GPC_ANEG_0 +#define GPC_FRC100MBIT_HALF GPC_ANEG_1 +#define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1) + +/* auto-negotiation with limited advertised speeds */ +/* mix only with master/slave settings (for copper) */ +#define GPC_ADV_1000_HALF GPC_ANEG_2 +#define GPC_ADV_1000_FULL GPC_ANEG_3 +#define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3) + +/* master/slave settings */ +/* only for copper with 1000 Mbps */ +#define GPC_FORCE_MASTER 0 +#define GPC_FORCE_SLAVE GPC_ANEG_0 +#define GPC_PREF_MASTER GPC_ANEG_1 +#define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0) + +/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ +/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ +#define GM_IS_TX_CO_OV BIT_5 /* Transmit Counter Overflow IRQ */ +#define GM_IS_RX_CO_OV BIT_4 /* Receive Counter Overflow IRQ */ +#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ +#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ +#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ +#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ + +#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \ + GM_IS_TX_FF_UR) + +/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ + /* Bits 15.. 2: reserved */ +#define GMLC_RST_CLR BIT_1S /* Clear GMAC Link Reset */ +#define GMLC_RST_SET BIT_0S /* Set GMAC Link Reset */ + + +/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ +#define WOL_CTL_LINK_CHG_OCC BIT_15S +#define WOL_CTL_MAGIC_PKT_OCC BIT_14S +#define WOL_CTL_PATTERN_OCC BIT_13S + +#define WOL_CTL_CLEAR_RESULT BIT_12S + +#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11S +#define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10S +#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9S +#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8S +#define WOL_CTL_ENA_PME_ON_PATTERN BIT_7S +#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6S + +#define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5S +#define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4S +#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3S +#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2S +#define WOL_CTL_ENA_PATTERN_UNIT BIT_1S +#define WOL_CTL_DIS_PATTERN_UNIT BIT_0S + +#define WOL_CTL_DEFAULT \ + (WOL_CTL_DIS_PME_ON_LINK_CHG | \ + WOL_CTL_DIS_PME_ON_PATTERN | \ + WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ + WOL_CTL_DIS_LINK_CHG_UNIT | \ + WOL_CTL_DIS_PATTERN_UNIT | \ + WOL_CTL_DIS_MAGIC_PKT_UNIT) + +/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ +#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) + +#define SK_NUM_WOL_PATTERN 7 +#define SK_PATTERN_PER_WORD 4 +#define SK_BITMASK_PATTERN 7 +#define SK_POW_PATTERN_LENGTH 128 + +#define WOL_LENGTH_MSK 0x7f +#define WOL_LENGTH_SHIFT 8 + + +/* Receive and Transmit Descriptors ******************************************/ + +/* Transmit Descriptor struct */ +typedef struct s_HwTxd { + SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */ + SK_U32 TxNext; /* Physical Address Pointer to the next TxD */ + SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */ + SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */ + SK_U32 TxStat; /* Transmit Frame Status Word */ +#ifndef SK_USE_REV_DESC + SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */ + SK_U16 TxRes1; /* 16 bit reserved field */ + SK_U16 TxTcpWp; /* TCP Checksum Write Position */ + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ +#else /* SK_USE_REV_DESC */ + SK_U16 TxRes1; /* 16 bit reserved field */ + SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */ + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ + SK_U16 TxTcpWp; /* TCP Checksum Write Position */ +#endif /* SK_USE_REV_DESC */ + SK_U32 TxRes2; /* 32 bit reserved field */ +} SK_HWTXD; + +/* Receive Descriptor struct */ +typedef struct s_HwRxd { + SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */ + SK_U32 RxNext; /* Physical Address Pointer to the next RxD */ + SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower dword */ + SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */ + SK_U32 RxStat; /* Receive Frame Status Word */ + SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */ +#ifndef SK_USE_REV_DESC + SK_U16 RxTcpSum1; /* TCP Checksum 1 */ + SK_U16 RxTcpSum2; /* TCP Checksum 2 */ + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ +#else /* SK_USE_REV_DESC */ + SK_U16 RxTcpSum2; /* TCP Checksum 2 */ + SK_U16 RxTcpSum1; /* TCP Checksum 1 */ + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ +#endif /* SK_USE_REV_DESC */ +} SK_HWRXD; + +/* + * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2) + * should set the define SK_USE_REV_DESC. + * Structures are 'normaly' not endianess dependent. But in + * this case the SK_U16 fields are bound to bit positions inside the + * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord. + * The bit positions inside a DWord are of course endianess dependent and + * swaps if the DWord is swapped by the hardware. + */ + + +/* Descriptor Bit Definition */ +/* TxCtrl Transmit Buffer Control Field */ +/* RxCtrl Receive Buffer Control Field */ +#define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ +#define BMU_STF BIT_30 /* Start of Frame */ +#define BMU_EOF BIT_29 /* End of Frame */ +#define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ +#define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ +/* TxCtrl specific bits */ +#define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ +#define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ +#define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ +/* RxCtrl specific bits */ +#define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ +#define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ +#define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ + /* Bit 23..16: BMU Check Opcodes */ +#define BMU_CHECK (0x55L<<16) /* Default BMU check */ +#define BMU_TCP_CHECK (0x56L<<16) /* Descr with TCP ext */ +#define BMU_UDP_CHECK (0x57L<<16) /* Descr with UDP ext (YUKON only) */ +#define BMU_BBC 0xFFFFL /* Bit 15.. 0: Buffer Byte Counter */ + +/* TxStat Transmit Frame Status Word */ +/* RxStat Receive Frame Status Word */ +/* + *Note: TxStat is reserved for ASIC loopback mode only + * + * The Bits of the Status words are defined in xmac_ii.h + * (see XMR_FS bits) + */ + +/* other defines *************************************************************/ + +/* + * FlashProm specification + */ +#define MAX_PAGES 0x20000L /* Every byte has a single page */ +#define MAX_FADDR 1 /* 1 byte per page */ +#define SKFDDI_PSZ 8 /* address PROM size */ + +/* macros ********************************************************************/ + +/* + * Receive and Transmit Queues + */ +#define Q_R1 0x0000 /* Receive Queue 1 */ +#define Q_R2 0x0080 /* Receive Queue 2 */ +#define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ +#define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ +#define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ +#define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ + +/* + * Macro Q_ADDR() + * + * Use this macro to access the Receive and Transmit Queue Registers. + * + * para: + * Queue Queue to access. + * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2 + * Offs Queue register offset. + * Values: Q_D, Q_DA_L ... Q_T2, Q_T3 + * + * usage SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal) + */ +#define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) + +/* + * Macro RB_ADDR() + * + * Use this macro to access the RAM Buffer Registers. + * + * para: + * Queue Queue to access. + * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2 + * Offs Queue register offset. + * Values: RB_START, RB_END ... RB_LEV, RB_CTRL + * + * usage SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal) + */ +#define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) + + +/* + * MAC Related Registers + */ +#define MAC_1 0 /* belongs to the port near the slot */ +#define MAC_2 1 /* belongs to the port far away from the slot */ + +/* + * Macro MR_ADDR() + * + * Use this macro to access a MAC Related Registers inside the ASIC. + * + * para: + * Mac MAC to access. + * Values: MAC_1, MAC_2 + * Offs MAC register offset. + * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG, + * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST + * + * usage SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal) + */ +#define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) + +#ifdef SK_LITTLE_ENDIAN +#define XM_WORD_LO 0 +#define XM_WORD_HI 1 +#else /* !SK_LITTLE_ENDIAN */ +#define XM_WORD_LO 1 +#define XM_WORD_HI 0 +#endif /* !SK_LITTLE_ENDIAN */ + + +/* + * macros to access the XMAC (GENESIS only) + * + * XM_IN16(), to read a 16 bit register (e.g. XM_MMU_CMD) + * XM_OUT16(), to write a 16 bit register (e.g. XM_MMU_CMD) + * XM_IN32(), to read a 32 bit register (e.g. XM_TX_EV_CNT) + * XM_OUT32(), to write a 32 bit register (e.g. XM_TX_EV_CNT) + * XM_INADDR(), to read a network address register (e.g. XM_SRC_CHK) + * XM_OUTADDR(), to write a network address register (e.g. XM_SRC_CHK) + * XM_INHASH(), to read the XM_HSM_CHK register + * XM_OUTHASH() to write the XM_HSM_CHK register + * + * para: + * Mac XMAC to access values: MAC_1 or MAC_2 + * IoC I/O context needed for SK I/O macros + * Reg XMAC Register to read or write + * (p)Val Value or pointer to the value which should be read or written + * + * usage: XM_OUT16(IoC, MAC_1, XM_MMU_CMD, Value); + */ + +#define XMA(Mac, Reg) \ + ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1)) + +#define XM_IN16(IoC, Mac, Reg, pVal) \ + SK_IN16((IoC), XMA((Mac), (Reg)), (pVal)) + +#define XM_OUT16(IoC, Mac, Reg, Val) \ + SK_OUT16((IoC), XMA((Mac), (Reg)), (Val)) + +#define XM_IN32(IoC, Mac, Reg, pVal) { \ + SK_IN16((IoC), XMA((Mac), (Reg)), \ + (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_LO]); \ + SK_IN16((IoC), XMA((Mac), (Reg+2)), \ + (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_HI]); \ +} + +#define XM_OUT32(IoC, Mac, Reg, Val) { \ + SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \ + SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)(((Val) >> 16) & 0xffffL));\ +} + +/* Remember: we are always writing to / reading from LITTLE ENDIAN memory */ + +#define XM_INADDR(IoC, Mac, Reg, pVal) { \ + SK_U16 Word; \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ + pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ + pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ +} + +#define XM_OUTADDR(IoC, Mac, Reg, pVal) { \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \ + (((SK_U16)(pByte[0]) & 0x00ff) | \ + (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \ + (((SK_U16)(pByte[2]) & 0x00ff) | \ + (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \ + (((SK_U16)(pByte[4]) & 0x00ff) | \ + (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ +} + +#define XM_INHASH(IoC, Mac, Reg, pVal) { \ + SK_U16 Word; \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ + pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ + pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \ + pByte[6] = (SK_U8)(Word & 0x00ff); \ + pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \ +} + +#define XM_OUTHASH(IoC, Mac, Reg, pVal) { \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \ + (((SK_U16)(pByte[0]) & 0x00ff)| \ + (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \ + (((SK_U16)(pByte[2]) & 0x00ff)| \ + (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \ + (((SK_U16)(pByte[4]) & 0x00ff)| \ + (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \ + (((SK_U16)(pByte[6]) & 0x00ff)| \ + (((SK_U16)(pByte[7]) << 8) & 0xff00))); \ +} + +/* + * macros to access the GMAC (YUKON only) + * + * GM_IN16(), to read a 16 bit register (e.g. GM_GP_STAT) + * GM_OUT16(), to write a 16 bit register (e.g. GM_GP_CTRL) + * GM_IN32(), to read a 32 bit register (e.g. GM_) + * GM_OUT32(), to write a 32 bit register (e.g. GM_) + * GM_INADDR(), to read a network address register (e.g. GM_SRC_ADDR_1L) + * GM_OUTADDR(), to write a network address register (e.g. GM_SRC_ADDR_2L) + * GM_INHASH(), to read the GM_MC_ADDR_H1 register + * GM_OUTHASH() to write the GM_MC_ADDR_H1 register + * + * para: + * Mac GMAC to access values: MAC_1 or MAC_2 + * IoC I/O context needed for SK I/O macros + * Reg GMAC Register to read or write + * (p)Val Value or pointer to the value which should be read or written + * + * usage: GM_OUT16(IoC, MAC_1, GM_GP_CTRL, Value); + */ + +#define GMA(Mac, Reg) \ + ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg)) + +#define GM_IN16(IoC, Mac, Reg, pVal) \ + SK_IN16((IoC), GMA((Mac), (Reg)), (pVal)) + +#define GM_OUT16(IoC, Mac, Reg, Val) \ + SK_OUT16((IoC), GMA((Mac), (Reg)), (Val)) + +#define GM_IN32(IoC, Mac, Reg, pVal) { \ + SK_IN16((IoC), GMA((Mac), (Reg)), \ + (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_LO]); \ + SK_IN16((IoC), GMA((Mac), (Reg+4)), \ + (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_HI]); \ +} + +#define GM_OUT32(IoC, Mac, Reg, Val) { \ + SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \ + SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)(((Val) >> 16) & 0xffffL));\ +} + +#define GM_INADDR(IoC, Mac, Reg, pVal) { \ + SK_U16 Word; \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ + pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ + pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ +} + +#define GM_OUTADDR(IoC, Mac, Reg, pVal) { \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \ + (((SK_U16)(pByte[0]) & 0x00ff) | \ + (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \ + (((SK_U16)(pByte[2]) & 0x00ff) | \ + (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \ + (((SK_U16)(pByte[4]) & 0x00ff) | \ + (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ +} + +#define GM_INHASH(IoC, Mac, Reg, pVal) { \ + SK_U16 Word; \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ + pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ + pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+12)), &Word); \ + pByte[6] = (SK_U8)(Word & 0x00ff); \ + pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \ +} + +#define GM_OUTHASH(IoC, Mac, Reg, pVal) { \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \ + (((SK_U16)(pByte[0]) & 0x00ff)| \ + (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \ + (((SK_U16)(pByte[2]) & 0x00ff)| \ + (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \ + (((SK_U16)(pByte[4]) & 0x00ff)| \ + (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+12)), (SK_U16) \ + (((SK_U16)(pByte[6]) & 0x00ff)| \ + (((SK_U16)(pByte[7]) << 8) & 0xff00))); \ +} + +/* + * Different MAC Types + */ +#define SK_MAC_XMAC 0 /* Xaqti XMAC II */ +#define SK_MAC_GMAC 1 /* Marvell GMAC */ + +/* + * Different PHY Types + */ +#define SK_PHY_XMAC 0 /* integrated in XMAC II */ +#define SK_PHY_BCOM 1 /* Broadcom BCM5400 */ +#define SK_PHY_LONE 2 /* Level One LXT1000 */ +#define SK_PHY_NAT 3 /* National DP83891 */ +#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1011S */ +#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1011S working on fiber */ + +/* + * PHY addresses (bits 12..8 of PHY address reg) + */ +#define PHY_ADDR_XMAC (0<<8) +#define PHY_ADDR_BCOM (1<<8) +#define PHY_ADDR_LONE (3<<8) +#define PHY_ADDR_NAT (0<<8) + +/* GPHY address (bits 15..11 of SMI control reg) */ +#define PHY_ADDR_MARV 0 + +/* + * macros to access the PHY + * + * PHY_READ() read a 16 bit value from the PHY + * PHY_WRITE() write a 16 bit value to the PHY + * + * para: + * IoC I/O context needed for SK I/O macros + * pPort Pointer to port struct for PhyAddr + * Mac XMAC to access values: MAC_1 or MAC_2 + * PhyReg PHY Register to read or write + * (p)Val Value or pointer to the value which should be read or + * written. + * + * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value); + * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never + * comes back. This is checked in DEBUG mode. + */ +#ifndef DEBUG +#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \ + SK_U16 Mmu; \ + \ + XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ + XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ + if ((pPort)->PhyType != SK_PHY_XMAC) { \ + do { \ + XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ + } while ((Mmu & XM_MMU_PHY_RDY) == 0); \ + XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ + } \ +} +#else +#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \ + SK_U16 Mmu; \ + int __i = 0; \ + \ + XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ + XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ + if ((pPort)->PhyType != SK_PHY_XMAC) { \ + do { \ + XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ + __i++; \ + if (__i > 100000) { \ + SK_DBG_PRINTF("*****************************\n"); \ + SK_DBG_PRINTF("PHY_READ on uninitialized PHY\n"); \ + SK_DBG_PRINTF("*****************************\n"); \ + break; \ + } \ + } while ((Mmu & XM_MMU_PHY_RDY) == 0); \ + XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ + } \ +} +#endif /* DEBUG */ + +#define PHY_WRITE(IoC, pPort, Mac, PhyReg, Val) { \ + SK_U16 Mmu; \ + \ + if ((pPort)->PhyType != SK_PHY_XMAC) { \ + do { \ + XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ + } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \ + } \ + XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ + XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \ + if ((pPort)->PhyType != SK_PHY_XMAC) { \ + do { \ + XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ + } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \ + } \ +} + +/* + * Macro PCI_C() + * + * Use this macro to access PCI config register from the I/O space. + * + * para: + * Addr PCI configuration register to access. + * Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG, + * + * usage SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal); + */ +#define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */ + +/* + * Macro SK_HW_ADDR(Base, Addr) + * + * Calculates the effective HW address + * + * para: + * Base I/O or memory base address + * Addr Address offset + * + * usage: May be used in SK_INxx and SK_OUTxx macros + * #define SK_IN8(pAC, Addr, pVal) ...\ + * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr))) + */ +#ifdef SK_MEM_MAPPED_IO +#define SK_HW_ADDR(Base, Addr) ((Base) + (Addr)) +#else /* SK_MEM_MAPPED_IO */ +#define SK_HW_ADDR(Base, Addr) \ + ((Base) + (((Addr) & 0x7f) | (((Addr) >> 7 > 0) ? 0x80 : 0))) +#endif /* SK_MEM_MAPPED_IO */ + +#define SZ_LONG (sizeof(SK_U32)) + +/* + * Macro SK_HWAC_LINK_LED() + * + * Use this macro to set the link LED mode. + * para: + * pAC Pointer to adapter context struct + * IoC I/O context needed for SK I/O macros + * Port Port number + * Mode Mode to set for this LED + */ +#define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \ + SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode); + + +/* typedefs *******************************************************************/ + + +/* function prototypes ********************************************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKGEHW_H */ diff --git a/drivers/sk98lin/h/skgehwt.h b/drivers/sk98lin/h/skgehwt.h new file mode 100644 index 0000000..8aa9edd --- /dev/null +++ b/drivers/sk98lin/h/skgehwt.h @@ -0,0 +1,74 @@ +/****************************************************************************** + * + * Name: skhwt.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.5 $ + * Date: $Date: 1999/11/22 13:54:24 $ + * Purpose: Defines for the hardware timer functions + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgehwt.h,v $ + * Revision 1.5 1999/11/22 13:54:24 cgoos + * Changed license header to GPL. + * + * Revision 1.4 1998/08/19 09:50:58 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.3 1998/08/14 07:09:29 gklug + * fix: chg pAc -> pAC + * + * Revision 1.2 1998/08/07 12:54:21 gklug + * fix: first compiled version + * + * Revision 1.1 1998/08/07 09:32:58 gklug + * first version + * + * + * + * + * + ******************************************************************************/ + +/* + * SKGEHWT.H contains all defines and types for the timer functions + */ + +#ifndef _SKGEHWT_H_ +#define _SKGEHWT_H_ + +/* + * SK Hardware Timer + * - needed wherever the HWT module is used + * - use in Adapters context name pAC->Hwt + */ +typedef struct s_Hwt { + SK_U32 TStart ; /* HWT start */ + SK_U32 TStop ; /* HWT stop */ + int TActive ; /* HWT: flag : active/inactive */ +} SK_HWT; + +extern void SkHwtInit(SK_AC *pAC, SK_IOC Ioc); +extern void SkHwtStart(SK_AC *pAC, SK_IOC Ioc, SK_U32 Time); +extern void SkHwtStop(SK_AC *pAC, SK_IOC Ioc); +extern SK_U32 SkHwtRead(SK_AC *pAC,SK_IOC Ioc); +extern void SkHwtIsr(SK_AC *pAC, SK_IOC Ioc); +#endif /* _SKGEHWT_H_ */ diff --git a/drivers/sk98lin/h/skgei2c.h b/drivers/sk98lin/h/skgei2c.h new file mode 100644 index 0000000..e639f73 --- /dev/null +++ b/drivers/sk98lin/h/skgei2c.h @@ -0,0 +1,299 @@ +/****************************************************************************** + * + * Name: skgei2c.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.23 $ + * Date: $Date: 2002/12/19 14:34:27 $ + * Purpose: Special GEnesis defines for TWSI + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgei2c.h,v $ + * Revision 1.23 2002/12/19 14:34:27 rschmidt + * Added cast in macros SK_I2C_SET_BIT() and SK_I2C_CLR_BIT() + * Editorial changes (TWSI) + * + * Revision 1.22 2002/10/14 16:45:56 rschmidt + * Editorial changes (TWSI) + * + * Revision 1.21 2002/08/13 08:42:24 rschmidt + * Changed define for SK_MIN_SENSORS back to 5 + * Merged defines for PHY PLL 3V3 voltage (A and B) + * Editorial changes + * + * Revision 1.20 2002/08/06 09:43:56 jschmalz + * Extensions and changes for Yukon + * + * Revision 1.19 2002/08/02 12:00:08 rschmidt + * Added defines for YUKON sensors + * Editorial changes + * + * Revision 1.18 2001/08/16 12:44:33 afischer + * LM80 sensor init values corrected + * + * Revision 1.17 1999/11/22 13:55:25 cgoos + * Changed license header to GPL. + * + * Revision 1.16 1999/11/12 08:24:10 malthoff + * Change voltage warning and error limits + * (warning +-5%, error +-10%). + * + * Revision 1.15 1999/09/14 14:14:43 malthoff + * The 1000BT Dual Link adapter has got only one Fan. + * The second Fan has been removed. + * + * Revision 1.14 1999/05/27 13:40:50 malthoff + * Fan Divisor = 1. Assuming fan with 6500 rpm. + * + * Revision 1.13 1999/05/20 14:56:55 malthoff + * Bug Fix: Missing brace in SK_LM80_FAN_FAKTOR. + * + * Revision 1.12 1999/05/20 09:22:00 cgoos + * Changes for 1000Base-T (Fan sensors). + * + * Revision 1.11 1998/10/14 05:57:22 cgoos + * Fixed compilation warnings. + * + * Revision 1.10 1998/09/04 08:37:00 malthoff + * bugfix: correct the SK_I2C_GET_CTL() macro. + * + * Revision 1.9 1998/08/25 06:10:03 gklug + * add: thresholds for all sensors + * + * Revision 1.8 1998/08/20 11:37:42 gklug + * chg: change Ioc to IoC + * + * Revision 1.7 1998/08/20 08:53:11 gklug + * fix: compiler errors + * add: Threshold values + * + * Revision 1.6 1998/08/17 11:37:09 malthoff + * Bugfix in SK_I2C_CTL macro. The parameter 'dev' + * has to be shifted 9 bits. + * + * Revision 1.5 1998/08/17 06:52:21 malthoff + * Remove unrequired macros. + * Add macros for accessing TWSI SW register. + * + * Revision 1.4 1998/08/13 08:30:18 gklug + * add: conversion factors for read values + * add: new state SEN_VALEXT to read extension value of temperature sensor + * + * Revision 1.3 1998/08/12 13:37:56 gklug + * rmv: error numbers and messages + * + * Revision 1.2 1998/08/11 07:54:38 gklug + * add: sensor states for GE sensors + * add: Macro to access TWSI hardware register + * chg: Error messages for TWSI errors + * + * Revision 1.1 1998/07/17 11:27:56 gklug + * Created. + * + * + * + ******************************************************************************/ + +/* + * SKGEI2C.H contains all SK-98xx specific defines for the TWSI handling + */ + +#ifndef _INC_SKGEI2C_H_ +#define _INC_SKGEI2C_H_ + +/* + * Macros to access the B2_I2C_CTRL + */ +#define SK_I2C_CTL(IoC, flag, dev, reg, burst) \ + SK_OUT32(IoC, B2_I2C_CTRL,\ + (flag ? 0x80000000UL : 0x0L) | \ + (((SK_U32) reg << 16) & I2C_ADDR) | \ + (((SK_U32) dev << 9) & I2C_DEV_SEL) | \ + (( burst << 4) & I2C_BURST_LEN)) + +#define SK_I2C_STOP(IoC) { \ + SK_U32 I2cCtrl; \ + SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \ + SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \ +} + +#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl) + +/* + * Macros to access the TWSI SW Registers + */ +#define SK_I2C_SET_BIT(IoC, SetBits) { \ + SK_U8 OrgBits; \ + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ + SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \ +} + +#define SK_I2C_CLR_BIT(IoC, ClrBits) { \ + SK_U8 OrgBits; \ + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ + SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \ +} + +#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw) + +/* + * define the possible sensor states + */ +#define SK_SEN_IDLE 0 /* Idle: sensor not read */ +#define SK_SEN_VALUE 1 /* Value Read cycle */ +#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */ + +/* + * Conversion factor to convert read Voltage sensor to milli Volt + * Conversion factor to convert read Temperature sensor to 10th degree Celsius + */ +#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */ +#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */ +#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for the + * extension value + */ +#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2)) +/* formula: counter = (22500*60)/(rpm * divisor * pulses/2) + * assuming: 6500rpm, 4 pulses, divisor 1 + */ + +/* + * Define sensor management data + * Maximum is reached on copperfield with dual Broadcom. + * Board specific maximum is in pAC->I2c.MaxSens + */ +#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */ +#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */ + +/* + * To watch the statemachine (JS) use the timer in two ways instead of one as hitherto + */ +#define SK_TIMER_WATCH_STATEMACHINE 0 /* Watch the statemachine to finish in a specific time */ +#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */ + + +/* + * Defines for the individual Thresholds + */ + +/* Temperature sensor */ +#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */ +#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */ +#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */ +#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */ + +/* VCC which should be 5 V */ +#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */ +#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */ +#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */ +#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */ + +/* + * VIO may be 5 V or 3.3 V. Initialization takes two parts: + * 1. Initialize lowest lower limit and highest higher limit. + * 2. After the first value is read correct the upper or the lower limit to + * the appropriate C constant. + * + * Warning limits are +-5% of the exepected voltage. + * Error limits are +-10% of the expected voltage. + */ + +/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */ + +#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */ +#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */ + /* 5000 mVolt */ +#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */ +#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */ + +#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */ + +/* correction values for the second pass */ +#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */ +#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */ + /* 3300 mVolt */ +#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */ +#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */ + + +/* + * VDD voltage + */ +#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */ +#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */ +#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */ +#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */ + +/* + * PHY PLL 3V3 voltage + */ +#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */ +#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */ +#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */ +#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */ + +/* + * VAUX (YUKON only) + */ +#define SK_SEN_VAUX_3V3_HIGH_ERR 3630 /* Voltage VAUX High Err Threshold */ +#define SK_SEN_VAUX_3V3_HIGH_WARN 3476 /* Voltage VAUX High Warn Threshold */ +#define SK_SEN_VAUX_3V3_LOW_WARN 3146 /* Voltage VAUX Low Warn Threshold */ +#define SK_SEN_VAUX_3V3_LOW_ERR 2970 /* Voltage VAUX Low Err Threshold */ +#define SK_SEN_VAUX_0V_WARN_ERR 0 /* if VAUX not present */ +#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */ + +/* + * PHY 2V5 voltage + */ +#define SK_SEN_PHY_2V5_HIGH_ERR 2750 /* Voltage PHY High Err Threshold */ +#define SK_SEN_PHY_2V5_HIGH_WARN 2640 /* Voltage PHY High Warn Threshold */ +#define SK_SEN_PHY_2V5_LOW_WARN 2376 /* Voltage PHY Low Warn Threshold */ +#define SK_SEN_PHY_2V5_LOW_ERR 2222 /* Voltage PHY Low Err Threshold */ + +/* + * ASIC Core 1V5 voltage (YUKON only) + */ +#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */ +#define SK_SEN_CORE_1V5_HIGH_WARN 1575 /* Voltage ASIC Core High Warn Threshold */ +#define SK_SEN_CORE_1V5_LOW_WARN 1425 /* Voltage ASIC Core Low Warn Threshold */ +#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */ + +/* + * FAN 1 speed + */ +/* assuming: 6500rpm +-15%, 4 pulses, + * warning at: 80 % + * error at: 70 % + * no upper limit + */ +#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */ +#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */ +#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */ +#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */ + +/* + * Some Voltages need dynamic thresholds + */ +#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */ +#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */ +#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */ + +extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); +#endif /* n_INC_SKGEI2C_H */ diff --git a/drivers/sk98lin/h/skgeinit.h b/drivers/sk98lin/h/skgeinit.h new file mode 100644 index 0000000..cdddef9 --- /dev/null +++ b/drivers/sk98lin/h/skgeinit.h @@ -0,0 +1,1113 @@ +/****************************************************************************** + * + * Name: skgeinit.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.75 $ + * Date: $Date: 2003/02/05 13:36:39 $ + * Purpose: Structures and prototypes for the GE Init Module + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgeinit.h,v $ + * Revision 1.75 2003/02/05 13:36:39 rschmidt + * Added define SK_FACT_78 for YUKON's Host Clock of 78.12 MHz + * Editorial changes + * + * Revision 1.74 2003/01/28 09:39:16 rschmidt + * Added entry GIYukonLite in s_GeInit structure + * Editorial changes + * + * Revision 1.73 2002/11/15 12:47:25 rschmidt + * Replaced error message SKERR_HWI_E024 for Cable Diagnostic with + * Rx queue error in SkGeStopPort(). + * + * Revision 1.72 2002/11/12 17:08:35 rschmidt + * Added entries for Cable Diagnostic to Port structure + * Added entries GIPciSlot64 and GIPciClock66 in s_GeInit structure + * Added error message for Cable Diagnostic + * Added prototypes for SkGmCableDiagStatus() + * Editorial changes + * + * Revision 1.71 2002/10/21 11:26:10 mkarl + * Changed interface of SkGeInitAssignRamToQueues(). + * + * Revision 1.70 2002/10/14 08:21:32 rschmidt + * Changed type of GICopperType, GIVauxAvail to SK_BOOL + * Added entry PRxOverCnt to Port structure + * Added entry GIYukon32Bit in s_GeInit structure + * Editorial changes + * + * Revision 1.69 2002/10/09 16:57:15 mkarl + * Added some constants and macros for SkGeInitAssignRamToQueues(). + * + * Revision 1.68 2002/09/12 08:58:51 rwahl + * Retrieve counters needed for XMAC errata workarounds directly because + * PNMI returns corrected counter values (e.g. #10620). + * + * Revision 1.67 2002/08/16 14:40:30 rschmidt + * Added entries GIGenesis and GICopperType in s_GeInit structure + * Added prototypes for SkMacHashing() + * Editorial changes + * + * Revision 1.66 2002/08/12 13:27:21 rschmidt + * Added defines for Link speed capabilities + * Added entry PLinkSpeedCap to Port structure + * Added entry GIVauxAvail in s_GeInit structure + * Added prototypes for SkMacPromiscMode() + * Editorial changes + * + * Revision 1.65 2002/08/08 15:46:18 rschmidt + * Added define SK_PHY_ACC_TO for PHY access timeout + * Added define SK_XM_RX_HI_WM for XMAC Rx High Watermark + * Added define SK_MIN_TXQ_SIZE for Min RAM Buffer Tx Queue Size + * Added entry PhyId1 to Port structure + * + * Revision 1.64 2002/07/23 16:02:56 rschmidt + * Added entry GIWolOffs in s_GeInit struct (HW-Bug in YUKON 1st rev.) + * Added prototypes for: SkGePhyRead(), SkGePhyWrite() + * + * Revision 1.63 2002/07/18 08:17:38 rwahl + * Corrected definitions for SK_LSPEED_xxx & SK_LSPEED_STAT_xxx. + * + * Revision 1.62 2002/07/17 18:21:55 rwahl + * Added SK_LSPEED_INDETERMINATED define. + * + * Revision 1.61 2002/07/17 17:16:03 rwahl + * - MacType now member of GIni struct. + * - Struct alignment to 32bit. + * - Editorial change. + * + * Revision 1.60 2002/07/15 18:23:39 rwahl + * Added GeMacFunc to GE Init structure. + * Added prototypes for SkXmUpdateStats(), SkGmUpdateStats(), + * SkXmMacStatistic(), SkGmMacStatistic(), SkXmResetCounter(), + * SkGmResetCounter(), SkXmOverflowStatus(), SkGmOverflowStatus(). + * Added defines for current link speed state. + * Added ERRMSG defintions for MacUpdateStat() & MacStatistics(). + * + * Revision 1.59 2002/07/15 15:40:22 rschmidt + * Added entry PLinkSpeedUsed to Port structure + * Editorial changes + * + * Revision 1.58 2002/06/10 09:36:30 rschmidt + * Editorial changes. + * + * Revision 1.57 2002/06/05 08:18:00 rschmidt + * Corrected alignment in Port Structure + * Added new prototypes for GMAC + * Editorial changes + * + * Revision 1.56 2002/04/25 11:38:12 rschmidt + * Added defines for Link speed values + * Added defines for Loopback parameters for MAC and PHY + * Removed entry PRxCmd from Port structure + * Added entry PLinkSpeed to Port structure + * Added entries GIChipId and GIChipRev to GE Init structure + * Removed entry GIAnyPortAct from GE Init structure + * Added prototypes for: SkMacInit(), SkMacInitPhy(), + * SkMacRxTxDisable(), SkMacSoftRst(), SkMacHardRst(), SkMacIrq(), + * SkMacIrqDisable(), SkMacFlushTxFifo(), SkMacFlushRxFifo(), + * SkMacAutoNegDone(), SkMacAutoNegLipaPhy(), SkMacSetRxTxEn(), + * SkXmPhyRead(), SkXmPhyRead(), SkGmPhyWrite(), SkGmPhyWrite(); + * Removed prototypes for static functions in SkXmac2.c + * Editorial changes + * + * Revision 1.55 2002/02/26 15:24:53 rwahl + * Fix: no link with manual configuration (#10673). The previous fix for + * #10639 was removed. So for RLMT mode = CLS the RLMT may switch to + * misconfigured port. It should not occur for the other RLMT modes. + * + * Revision 1.54 2002/01/18 16:52:52 rwahl + * Editorial corrections. + * + * Revision 1.53 2001/11/20 09:19:58 rwahl + * Reworked bugfix #10639 (no dependency to RLMT mode). + * + * Revision 1.52 2001/10/26 07:52:23 afischer + * Port switching bug in `check local link` mode + * + * Revision 1.51 2001/02/09 12:26:38 cgoos + * Inserted #ifdef DIAG for half duplex workaround timer. + * + * Revision 1.50 2001/02/07 07:56:40 rassmann + * Corrected copyright. + * + * Revision 1.49 2001/01/31 15:32:18 gklug + * fix: problem with autosensing an SR8800 switch + * add: counter for autoneg timeouts + * + * Revision 1.48 2000/11/09 11:30:10 rassmann + * WA: Waiting after releasing reset until BCom chip is accessible. + * + * Revision 1.47 2000/10/18 12:22:40 cgoos + * Added workaround for half duplex hangup. + * + * Revision 1.46 2000/08/10 11:28:00 rassmann + * Editorial changes. + * Preserving 32-bit alignment in structs for the adapter context. + * + * Revision 1.45 1999/11/22 13:56:19 cgoos + * Changed license header to GPL. + * + * Revision 1.44 1999/10/26 07:34:15 malthoff + * The define SK_LNK_ON has been lost in v1.41. + * + * Revision 1.43 1999/10/06 09:30:16 cgoos + * Changed SK_XM_THR_JUMBO. + * + * Revision 1.42 1999/09/16 12:58:26 cgoos + * Changed SK_LED_STANDY macro to be independent of HW link sync. + * + * Revision 1.41 1999/07/30 06:56:14 malthoff + * Correct comment for SK_MS_STAT_UNSET. + * + * Revision 1.40 1999/05/27 13:38:46 cgoos + * Added SK_BMU_TX_WM. + * Made SK_BMU_TX_WM and SK_BMU_RX_WM user-definable. + * Changed XMAC Tx treshold to max. values. + * + * Revision 1.39 1999/05/20 14:35:26 malthoff + * Remove prototypes for SkGeLinkLED(). + * + * Revision 1.38 1999/05/19 11:59:12 cgoos + * Added SK_MS_CAP_INDETERMINATED define. + * + * Revision 1.37 1999/05/19 07:32:33 cgoos + * Changes for 1000Base-T. + * LED-defines for HWAC_LINK_LED macro. + * + * Revision 1.36 1999/04/08 14:00:24 gklug + * add:Port struct field PLinkResCt + * + * Revision 1.35 1999/03/25 07:43:07 malthoff + * Add error string for SKERR_HWI_E018MSG. + * + * Revision 1.34 1999/03/12 16:25:57 malthoff + * Remove PPollRxD and PPollTxD. + * Add SKERR_HWI_E017MSG. and SK_DPOLL_MAX. + * + * Revision 1.33 1999/03/12 13:34:41 malthoff + * Add Autonegotiation error codes. + * Change defines for parameter Mode in SkXmSetRxCmd(). + * Replace __STDC__ by SK_KR_PROTO. + * + * Revision 1.32 1999/01/25 14:40:20 mhaveman + * Added new return states for the virtual management port if multiple + * ports are active but differently configured. + * + * Revision 1.31 1998/12/11 15:17:02 gklug + * add: Link partnet autoneg states : Unknown Manual and Auto-negotiation + * + * Revision 1.30 1998/12/07 12:17:04 gklug + * add: Link Partner auto-negotiation flag + * + * Revision 1.29 1998/12/01 10:54:42 gklug + * add: variables for XMAC Errata + * + * Revision 1.28 1998/12/01 10:14:15 gklug + * add: PIsave saves the Interrupt status word + * + * Revision 1.27 1998/11/26 15:24:52 mhaveman + * Added link status states SK_LMODE_STAT_AUTOHALF and + * SK_LMODE_STAT_AUTOFULL which are used by PNMI. + * + * Revision 1.26 1998/11/26 14:53:01 gklug + * add:autoNeg Timeout variable + * + * Revision 1.25 1998/11/26 08:58:50 gklug + * add: Link Mode configuration (AUTO Sense mode) + * + * Revision 1.24 1998/11/24 13:30:27 gklug + * add: PCheckPar to port struct + * + * Revision 1.23 1998/11/18 13:23:26 malthoff + * Add SK_PKT_TO_MAX. + * + * Revision 1.22 1998/11/18 13:19:54 gklug + * add: PPrevShorts and PLinkBroken to port struct for WA XMAC Errata #C1 + * + * Revision 1.21 1998/10/26 08:02:57 malthoff + * Add GIRamOffs. + * + * Revision 1.20 1998/10/19 07:28:37 malthoff + * Add prototype for SkGeInitRamIface(). + * + * Revision 1.19 1998/10/14 14:47:48 malthoff + * SK_TIMER should not be defined for Diagnostics. + * Add SKERR_HWI_E015MSG and SKERR_HWI_E016MSG. + * + * Revision 1.18 1998/10/14 14:00:03 gklug + * add: timer to port struct for workaround of Errata #2 + * + * Revision 1.17 1998/10/14 11:23:09 malthoff + * Add prototype for SkXmAutoNegDone(). + * Fix SkXmSetRxCmd() prototype statement. + * + * Revision 1.16 1998/10/14 05:42:29 gklug + * add: HWLinkUp flag to Port struct + * + * Revision 1.15 1998/10/09 08:26:33 malthoff + * Rename SK_RB_ULPP_B to SK_RB_LLPP_B. + * + * Revision 1.14 1998/10/09 07:11:13 malthoff + * bug fix: SK_FACT_53 is 85 not 117. + * Rework time out init values. + * Add GIPortUsage and corresponding defines. + * Add some error log messages. + * + * Revision 1.13 1998/10/06 14:13:14 malthoff + * Add prototype for SkGeLoadLnkSyncCnt(). + * + * Revision 1.12 1998/10/05 11:29:53 malthoff + * bug fix: A comment was not closed. + * + * Revision 1.11 1998/10/05 08:01:59 malthoff + * Add default Timeout- Threshold- and + * Watermark constants. Add QRam start and end + * variables. Also add vars to store the polling + * mode and receive command. Add new Error Log + * Messages and function prototypes. + * + * Revision 1.10 1998/09/28 13:34:48 malthoff + * Add mode bits for LED functions. + * Move Autoneg and Flow Ctrl bits from shgesirq.h + * Add the required Error Log Entries + * and Function Prototypes. + * + * Revision 1.9 1998/09/16 14:38:41 malthoff + * Rework the SK_LNK_xxx defines. + * Add error log message defines. + * Add prototypes for skxmac2.c + * + * Revision 1.8 1998/09/11 05:29:18 gklug + * add: init state of a port + * + * Revision 1.7 1998/09/08 08:35:52 gklug + * add: defines of the Init Levels + * + * Revision 1.6 1998/09/03 13:48:42 gklug + * add: Link strati, capabilities to Port struct + * + * Revision 1.5 1998/09/03 13:30:59 malthoff + * Add SK_LNK_BLINK and SK_LNK_PERM. + * + * Revision 1.4 1998/09/03 09:55:31 malthoff + * Add constants for parameters Dir and RstMode + * when calling SkGeStopPort(). + * Rework the prototype section. + * Add Queue Address offsets PRxQOff, PXsQOff, and PXaQOff. + * Remove Ioc with IoC. + * + * Revision 1.3 1998/08/19 09:11:54 gklug + * fix: struct are removed from c-source (see CCC) + * add: typedefs for all structs + * + * Revision 1.2 1998/07/28 12:38:26 malthoff + * The prototypes got the parameter 'IoC'. + * + * Revision 1.1 1998/07/23 09:50:24 malthoff + * Created. + * + ******************************************************************************/ + +#ifndef __INC_SKGEINIT_H_ +#define __INC_SKGEINIT_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines ********************************************************************/ + +/* modifying Link LED behaviour (used with SkGeLinkLED()) */ +#define SK_LNK_OFF LED_OFF +#define SK_LNK_ON (LED_ON | LED_BLK_OFF | LED_SYNC_OFF) +#define SK_LNK_BLINK (LED_ON | LED_BLK_ON | LED_SYNC_ON) +#define SK_LNK_PERM (LED_ON | LED_BLK_OFF | LED_SYNC_ON) +#define SK_LNK_TST (LED_ON | LED_BLK_ON | LED_SYNC_OFF) + +/* parameter 'Mode' when calling SK_HWAC_LINK_LED() */ +#define SK_LED_OFF LED_OFF +#define SK_LED_ACTIVE (LED_ON | LED_BLK_OFF | LED_SYNC_OFF) +#define SK_LED_STANDBY (LED_ON | LED_BLK_ON | LED_SYNC_OFF) + +/* addressing LED Registers in SkGeXmitLED() */ +#define XMIT_LED_INI 0 +#define XMIT_LED_CNT (RX_LED_VAL - RX_LED_INI) +#define XMIT_LED_CTRL (RX_LED_CTRL- RX_LED_INI) +#define XMIT_LED_TST (RX_LED_TST - RX_LED_INI) + +/* parameter 'Mode' when calling SkGeXmitLED() */ +#define SK_LED_DIS 0 +#define SK_LED_ENA 1 +#define SK_LED_TST 2 + +/* Counter and Timer constants, for a host clock of 62.5 MHz */ +#define SK_XMIT_DUR 0x002faf08L /* 50 ms */ +#define SK_BLK_DUR 0x01dcd650L /* 500 ms */ + +#define SK_DPOLL_DEF 0x00ee6b28L /* 250 ms at 62.5 MHz */ + +#define SK_DPOLL_MAX 0x00ffffffL /* 268 ms at 62.5 MHz */ + /* 215 ms at 78.12 MHz */ + +#define SK_FACT_62 100 /* is given in percent */ +#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */ +#define SK_FACT_78 125 /* on YUKON: 78.12 MHz */ + +/* Timeout values */ +#define SK_MAC_TO_53 72 /* MAC arbiter timeout */ +#define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */ +#define SK_PKT_TO_MAX 0xffff /* Maximum value */ +#define SK_RI_TO_53 36 /* RAM interface timeout */ + +#define SK_PHY_ACC_TO 600000 /* PHY access timeout */ + +/* RAM Buffer High Pause Threshold values */ +#define SK_RB_ULPP ( 8 * 1024) /* Upper Level in kB/8 */ +#define SK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ +#define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ + +#ifndef SK_BMU_RX_WM +#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ +#endif +#ifndef SK_BMU_TX_WM +#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ +#endif + +/* XMAC II Rx High Watermark */ +#define SK_XM_RX_HI_WM 0x05aa /* 1450 */ + +/* XMAC II Tx Threshold */ +#define SK_XM_THR_REDL 0x01fb /* .. for redundant link usage */ +#define SK_XM_THR_SL 0x01fb /* .. for single link adapters */ +#define SK_XM_THR_MULL 0x01fb /* .. for multiple link usage */ +#define SK_XM_THR_JUMBO 0x03fc /* .. for jumbo frame usage */ + +/* values for GIPortUsage */ +#define SK_RED_LINK 1 /* redundant link usage */ +#define SK_MUL_LINK 2 /* multiple link usage */ +#define SK_JUMBO_LINK 3 /* driver uses jumbo frames */ + +/* Minimum RAM Buffer Rx Queue Size */ +#define SK_MIN_RXQ_SIZE 16 /* 16 kB */ + +/* Minimum RAM Buffer Tx Queue Size */ +#define SK_MIN_TXQ_SIZE 16 /* 16 kB */ + +/* Queue Size units */ +#define QZ_UNITS 0x7 +#define QZ_STEP 8 + +/* Percentage of queue size from whole memory */ +/* 80 % for receive */ +#define RAM_QUOTA_RX 80L +/* 0% for sync transfer */ +#define RAM_QUOTA_SYNC 0L +/* the rest (20%) is taken for async transfer */ + +/* Get the rounded queue size in Bytes in 8k steps */ +#define ROUND_QUEUE_SIZE(SizeInBytes) \ + ((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \ + ~(QZ_STEP-1)) + +/* Get the rounded queue size in KBytes in 8k steps */ +#define ROUND_QUEUE_SIZE_KB(Kilobytes) \ + ROUND_QUEUE_SIZE((Kilobytes) * 1024L) + +/* Types of RAM Buffer Queues */ +#define SK_RX_SRAM_Q 1 /* small receive queue */ +#define SK_RX_BRAM_Q 2 /* big receive queue */ +#define SK_TX_RAM_Q 3 /* small or big transmit queue */ + +/* parameter 'Dir' when calling SkGeStopPort() */ +#define SK_STOP_TX 1 /* Stops the transmit path, resets the XMAC */ +#define SK_STOP_RX 2 /* Stops the receive path */ +#define SK_STOP_ALL 3 /* Stops Rx and Tx path, resets the XMAC */ + +/* parameter 'RstMode' when calling SkGeStopPort() */ +#define SK_SOFT_RST 1 /* perform a software reset */ +#define SK_HARD_RST 2 /* perform a hardware reset */ + +/* Init Levels */ +#define SK_INIT_DATA 0 /* Init level 0: init data structures */ +#define SK_INIT_IO 1 /* Init level 1: init with IOs */ +#define SK_INIT_RUN 2 /* Init level 2: init for run time */ + +/* Link Mode Parameter */ +#define SK_LMODE_HALF 1 /* Half Duplex Mode */ +#define SK_LMODE_FULL 2 /* Full Duplex Mode */ +#define SK_LMODE_AUTOHALF 3 /* AutoHalf Duplex Mode */ +#define SK_LMODE_AUTOFULL 4 /* AutoFull Duplex Mode */ +#define SK_LMODE_AUTOBOTH 5 /* AutoBoth Duplex Mode */ +#define SK_LMODE_AUTOSENSE 6 /* configured mode auto sensing */ +#define SK_LMODE_INDETERMINATED 7 /* indeterminated */ + +/* Auto-negotiation timeout in 100ms granularity */ +#define SK_AND_MAX_TO 6 /* Wait 600 msec before link comes up */ + +/* Auto-negotiation error codes */ +#define SK_AND_OK 0 /* no error */ +#define SK_AND_OTHER 1 /* other error than below */ +#define SK_AND_DUP_CAP 2 /* Duplex capabilities error */ + + +/* Link Speed Capabilities */ +#define SK_LSPEED_CAP_AUTO (1<<0) /* Automatic resolution */ +#define SK_LSPEED_CAP_10MBPS (1<<1) /* 10 Mbps */ +#define SK_LSPEED_CAP_100MBPS (1<<2) /* 100 Mbps */ +#define SK_LSPEED_CAP_1000MBPS (1<<3) /* 1000 Mbps */ +#define SK_LSPEED_CAP_INDETERMINATED (1<<4) /* indeterminated */ + +/* Link Speed Parameter */ +#define SK_LSPEED_AUTO 1 /* Automatic resolution */ +#define SK_LSPEED_10MBPS 2 /* 10 Mbps */ +#define SK_LSPEED_100MBPS 3 /* 100 Mbps */ +#define SK_LSPEED_1000MBPS 4 /* 1000 Mbps */ +#define SK_LSPEED_INDETERMINATED 5 /* indeterminated */ + +/* Link Speed Current State */ +#define SK_LSPEED_STAT_UNKNOWN 1 +#define SK_LSPEED_STAT_10MBPS 2 +#define SK_LSPEED_STAT_100MBPS 3 +#define SK_LSPEED_STAT_1000MBPS 4 +#define SK_LSPEED_STAT_INDETERMINATED 5 + + +/* Link Capability Parameter */ +#define SK_LMODE_CAP_HALF (1<<0) /* Half Duplex Mode */ +#define SK_LMODE_CAP_FULL (1<<1) /* Full Duplex Mode */ +#define SK_LMODE_CAP_AUTOHALF (1<<2) /* AutoHalf Duplex Mode */ +#define SK_LMODE_CAP_AUTOFULL (1<<3) /* AutoFull Duplex Mode */ +#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* indeterminated */ + +/* Link Mode Current State */ +#define SK_LMODE_STAT_UNKNOWN 1 /* Unknown Duplex Mode */ +#define SK_LMODE_STAT_HALF 2 /* Half Duplex Mode */ +#define SK_LMODE_STAT_FULL 3 /* Full Duplex Mode */ +#define SK_LMODE_STAT_AUTOHALF 4 /* Half Duplex Mode obtained by Auto-Neg */ +#define SK_LMODE_STAT_AUTOFULL 5 /* Full Duplex Mode obtained by Auto-Neg */ +#define SK_LMODE_STAT_INDETERMINATED 6 /* indeterminated */ + +/* Flow Control Mode Parameter (and capabilities) */ +#define SK_FLOW_MODE_NONE 1 /* No Flow-Control */ +#define SK_FLOW_MODE_LOC_SEND 2 /* Local station sends PAUSE */ +#define SK_FLOW_MODE_SYMMETRIC 3 /* Both stations may send PAUSE */ +#define SK_FLOW_MODE_SYM_OR_REM 4 /* Both stations may send PAUSE or + * just the remote station may send PAUSE + */ +#define SK_FLOW_MODE_INDETERMINATED 5 /* indeterminated */ + +/* Flow Control Status Parameter */ +#define SK_FLOW_STAT_NONE 1 /* No Flow Control */ +#define SK_FLOW_STAT_REM_SEND 2 /* Remote Station sends PAUSE */ +#define SK_FLOW_STAT_LOC_SEND 3 /* Local station sends PAUSE */ +#define SK_FLOW_STAT_SYMMETRIC 4 /* Both station may send PAUSE */ +#define SK_FLOW_STAT_INDETERMINATED 5 /* indeterminated */ + +/* Master/Slave Mode Capabilities */ +#define SK_MS_CAP_AUTO (1<<0) /* Automatic resolution */ +#define SK_MS_CAP_MASTER (1<<1) /* This station is master */ +#define SK_MS_CAP_SLAVE (1<<2) /* This station is slave */ +#define SK_MS_CAP_INDETERMINATED (1<<3) /* indeterminated */ + +/* Set Master/Slave Mode Parameter (and capabilities) */ +#define SK_MS_MODE_AUTO 1 /* Automatic resolution */ +#define SK_MS_MODE_MASTER 2 /* This station is master */ +#define SK_MS_MODE_SLAVE 3 /* This station is slave */ +#define SK_MS_MODE_INDETERMINATED 4 /* indeterminated */ + +/* Master/Slave Status Parameter */ +#define SK_MS_STAT_UNSET 1 /* The M/S status is not set */ +#define SK_MS_STAT_MASTER 2 /* This station is Master */ +#define SK_MS_STAT_SLAVE 3 /* This station is Dlave */ +#define SK_MS_STAT_FAULT 4 /* M/S resolution failed */ +#define SK_MS_STAT_INDETERMINATED 5 /* indeterminated */ + +/* parameter 'Mode' when calling SkXmSetRxCmd() */ +#define SK_STRIP_FCS_ON (1<<0) /* Enable FCS stripping of Rx frames */ +#define SK_STRIP_FCS_OFF (1<<1) /* Disable FCS stripping of Rx frames */ +#define SK_STRIP_PAD_ON (1<<2) /* Enable pad byte stripping of Rx fr */ +#define SK_STRIP_PAD_OFF (1<<3) /* Disable pad byte stripping of Rx fr */ +#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error */ +#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error */ +#define SK_BIG_PK_OK_ON (1<<6) /* Don't set Rx Error bit for big frames */ +#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */ +#define SK_SELF_RX_ON (1<<8) /* Enable Rx of own packets */ +#define SK_SELF_RX_OFF (1<<9) /* Disable Rx of own packets */ + +/* parameter 'Para' when calling SkMacSetRxTxEn() */ +#define SK_MAC_LOOPB_ON (1<<0) /* Enable MAC Loopback Mode */ +#define SK_MAC_LOOPB_OFF (1<<1) /* Disable MAC Loopback Mode */ +#define SK_PHY_LOOPB_ON (1<<2) /* Enable PHY Loopback Mode */ +#define SK_PHY_LOOPB_OFF (1<<3) /* Disable PHY Loopback Mode */ +#define SK_PHY_FULLD_ON (1<<4) /* Enable GMII Full Duplex */ +#define SK_PHY_FULLD_OFF (1<<5) /* Disable GMII Full Duplex */ + +/* States of PState */ +#define SK_PRT_RESET 0 /* the port is reset */ +#define SK_PRT_STOP 1 /* the port is stopped (similar to SW reset) */ +#define SK_PRT_INIT 2 /* the port is initialized */ +#define SK_PRT_RUN 3 /* the port has an active link */ + +/* Default receive frame limit for Workaround of XMAC Errata */ +#define SK_DEF_RX_WA_LIM SK_CONSTU64(100) + +/* Link Partner Status */ +#define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */ +#define SK_LIPA_MANUAL 1 /* Link partner is in detected manual state */ +#define SK_LIPA_AUTO 2 /* Link partner is in auto-negotiation state */ + +/* Maximum Restarts before restart is ignored (3Com WA) */ +#define SK_MAX_LRESTART 3 /* Max. 3 times the link is restarted */ + +/* Max. Auto-neg. timeouts before link detection in sense mode is reset */ +#define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */ + +/* structures *****************************************************************/ + +/* + * MAC specific functions + */ +typedef struct s_GeMacFunc { + int (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port); + int (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port, + SK_U16 StatAddr, SK_U32 *pVal); + int (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port); + int (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port, + SK_U16 IStatus, SK_U64 *pVal); +} SK_GEMACFUNC; + +/* + * Port Structure + */ +typedef struct s_GePort { +#ifndef SK_DIAG + SK_TIMER PWaTimer; /* Workaround Timer */ + SK_TIMER HalfDupChkTimer; +#endif /* SK_DIAG */ + SK_U32 PPrevShorts; /* Previous short Counter checking */ + SK_U32 PPrevFcs; /* Previous FCS Error Counter checking */ + SK_U64 PPrevRx; /* Previous RxOk Counter checking */ + SK_U64 PRxLim; /* Previous RxOk Counter checking */ + SK_U64 LastOctets; /* For half duplex hang check */ + int PLinkResCt; /* Link Restart Counter */ + int PAutoNegTimeOut;/* Auto-negotiation timeout current value */ + int PAutoNegTOCt; /* Auto-negotiation Timeout Counter */ + int PRxQSize; /* Port Rx Queue Size in kB */ + int PXSQSize; /* Port Synchronous Transmit Queue Size in kB */ + int PXAQSize; /* Port Asynchronous Transmit Queue Size in kB */ + SK_U32 PRxQRamStart; /* Receive Queue RAM Buffer Start Address */ + SK_U32 PRxQRamEnd; /* Receive Queue RAM Buffer End Address */ + SK_U32 PXsQRamStart; /* Sync Tx Queue RAM Buffer Start Address */ + SK_U32 PXsQRamEnd; /* Sync Tx Queue RAM Buffer End Address */ + SK_U32 PXaQRamStart; /* Async Tx Queue RAM Buffer Start Address */ + SK_U32 PXaQRamEnd; /* Async Tx Queue RAM Buffer End Address */ + SK_U32 PRxOverCnt; /* Receive Overflow Counter */ + int PRxQOff; /* Rx Queue Address Offset */ + int PXsQOff; /* Synchronous Tx Queue Address Offset */ + int PXaQOff; /* Asynchronous Tx Queue Address Offset */ + int PhyType; /* PHY used on this port */ + SK_U16 PhyId1; /* PHY Id1 on this port */ + SK_U16 PhyAddr; /* MDIO/MDC PHY address */ + SK_U16 PIsave; /* Saved Interrupt status word */ + SK_U16 PSsave; /* Saved PHY status word */ + SK_BOOL PHWLinkUp; /* The hardware Link is up (wiring) */ + SK_BOOL PState; /* Is port initialized ? */ + SK_BOOL PLinkBroken; /* Is Link broken ? */ + SK_BOOL PCheckPar; /* Do we check for parity errors ? */ + SK_BOOL HalfDupTimerActive; + SK_U8 PLinkCap; /* Link Capabilities */ + SK_U8 PLinkModeConf; /* Link Mode configured */ + SK_U8 PLinkMode; /* Link Mode currently used */ + SK_U8 PLinkModeStatus;/* Link Mode Status */ + SK_U8 PLinkSpeedCap; /* Link Speed Capabilities(10/100/1000 Mbps) */ + SK_U8 PLinkSpeed; /* configured Link Speed (10/100/1000 Mbps) */ + SK_U8 PLinkSpeedUsed; /* current Link Speed (10/100/1000 Mbps) */ + SK_U8 PFlowCtrlCap; /* Flow Control Capabilities */ + SK_U8 PFlowCtrlMode; /* Flow Control Mode */ + SK_U8 PFlowCtrlStatus;/* Flow Control Status */ + SK_U8 PMSCap; /* Master/Slave Capabilities */ + SK_U8 PMSMode; /* Master/Slave Mode */ + SK_U8 PMSStatus; /* Master/Slave Status */ + SK_U8 PAutoNegFail; /* Auto-negotiation fail flag */ + SK_U8 PLipaAutoNeg; /* Auto-negotiation possible with Link Partner */ + SK_U8 PCableLen; /* Cable Length */ + SK_U8 PMdiPairLen[4]; /* MDI[0..3] Pair Length */ + SK_U8 PMdiPairSts[4]; /* MDI[0..3] Pair Diagnostic Status */ +} SK_GEPORT; + +/* + * Gigabit Ethernet Initialization Struct + * (has to be included in the adapter context) + */ +typedef struct s_GeInit { + SK_U8 GIPciHwRev; /* PCI HW Revision Number */ + SK_U8 GIChipId; /* Chip Identification Number */ + SK_U8 GIChipRev; /* Chip Revision Number */ + SK_BOOL GIGenesis; /* Genesis adapter ? */ + SK_BOOL GICopperType; /* Copper Type adapter ? */ + SK_BOOL GIPciSlot64; /* 64-bit PCI Slot */ + SK_BOOL GIPciClock66; /* 66 MHz PCI Clock */ + SK_BOOL GIVauxAvail; /* VAUX available (YUKON) */ + SK_BOOL GIYukon32Bit; /* 32-Bit YUKON adapter */ + SK_BOOL GIYukonLite; /* YUKON-Lite chip */ + int GIMacsFound; /* Number of MACs found on this adapter */ + int GIMacType; /* MAC Type used on this adapter */ + int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */ + int GIPortUsage; /* Driver Port Usage */ + int GILevel; /* Initialization Level completed */ + int GIRamSize; /* The RAM size of the adapter in kB */ + int GIWolOffs; /* WOL Register Offset (HW-Bug in Rev. A) */ + SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */ + SK_U32 GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */ + SK_GEPORT GP[SK_MAX_MACS];/* Port Dependent Information */ + SK_GEMACFUNC GIFunc; /* MAC depedent functions */ +} SK_GEINIT; + +/* + * Error numbers and messages for skxmac2.c and skgeinit.c + */ +#define SKERR_HWI_E001 (SK_ERRBASE_HWINIT) +#define SKERR_HWI_E001MSG "SkXmClrExactAddr() has got illegal parameters" +#define SKERR_HWI_E002 (SKERR_HWI_E001+1) +#define SKERR_HWI_E002MSG "SkGeInit(): Level 1 call missing" +#define SKERR_HWI_E003 (SKERR_HWI_E002+1) +#define SKERR_HWI_E003MSG "SkGeInit() called with illegal init Level" +#define SKERR_HWI_E004 (SKERR_HWI_E003+1) +#define SKERR_HWI_E004MSG "SkGeInitPort(): Queue Size illegal configured" +#define SKERR_HWI_E005 (SKERR_HWI_E004+1) +#define SKERR_HWI_E005MSG "SkGeInitPort(): cannot init running ports" +#define SKERR_HWI_E006 (SKERR_HWI_E005+1) +#define SKERR_HWI_E006MSG "SkGeMacInit(): PState does not match HW state" +#define SKERR_HWI_E007 (SKERR_HWI_E006+1) +#define SKERR_HWI_E007MSG "SkXmInitDupMd() called with invalid Dup Mode" +#define SKERR_HWI_E008 (SKERR_HWI_E007+1) +#define SKERR_HWI_E008MSG "SkXmSetRxCmd() called with invalid Mode" +#define SKERR_HWI_E009 (SKERR_HWI_E008+1) +#define SKERR_HWI_E009MSG "SkGeCfgSync() called although PXSQSize zero" +#define SKERR_HWI_E010 (SKERR_HWI_E009+1) +#define SKERR_HWI_E010MSG "SkGeCfgSync() called with invalid parameters" +#define SKERR_HWI_E011 (SKERR_HWI_E010+1) +#define SKERR_HWI_E011MSG "SkGeInitPort(): Receive Queue Size too small" +#define SKERR_HWI_E012 (SKERR_HWI_E011+1) +#define SKERR_HWI_E012MSG "SkGeInitPort(): invalid Queue Size specified" +#define SKERR_HWI_E013 (SKERR_HWI_E012+1) +#define SKERR_HWI_E013MSG "SkGeInitPort(): cfg changed for running queue" +#define SKERR_HWI_E014 (SKERR_HWI_E013+1) +#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown GIPortUsage specified" +#define SKERR_HWI_E015 (SKERR_HWI_E014+1) +#define SKERR_HWI_E015MSG "Illegal Link mode parameter" +#define SKERR_HWI_E016 (SKERR_HWI_E015+1) +#define SKERR_HWI_E016MSG "Illegal Flow control mode parameter" +#define SKERR_HWI_E017 (SKERR_HWI_E016+1) +#define SKERR_HWI_E017MSG "Illegal value specified for GIPollTimerVal" +#define SKERR_HWI_E018 (SKERR_HWI_E017+1) +#define SKERR_HWI_E018MSG "FATAL: SkGeStopPort() does not terminate (Tx)" +#define SKERR_HWI_E019 (SKERR_HWI_E018+1) +#define SKERR_HWI_E019MSG "Illegal Speed parameter" +#define SKERR_HWI_E020 (SKERR_HWI_E019+1) +#define SKERR_HWI_E020MSG "Illegal Master/Slave parameter" +#define SKERR_HWI_E021 (SKERR_HWI_E020+1) +#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter" +#define SKERR_HWI_E022 (SKERR_HWI_E021+1) +#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address" +#define SKERR_HWI_E023 (SKERR_HWI_E022+1) +#define SKERR_HWI_E023MSG "SkGeInitPort(): Transmit Queue Size too small" +#define SKERR_HWI_E024 (SKERR_HWI_E023+1) +#define SKERR_HWI_E024MSG "FATAL: SkGeStopPort() does not terminate (Rx)" +#define SKERR_HWI_E025 (SKERR_HWI_E024+1) +#define SKERR_HWI_E025MSG "" + +/* function prototypes ********************************************************/ + +#ifndef SK_KR_PROTO + +/* + * public functions in skgeinit.c + */ +extern void SkGePollRxD( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL PollRxD); + +extern void SkGePollTxD( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL PollTxD); + +extern void SkGeYellowLED( + SK_AC *pAC, + SK_IOC IoC, + int State); + +extern int SkGeCfgSync( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_U32 IntTime, + SK_U32 LimCount, + int SyncMode); + +extern void SkGeLoadLnkSyncCnt( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_U32 CntVal); + +extern void SkGeStopPort( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Dir, + int RstMode); + +extern int SkGeInit( + SK_AC *pAC, + SK_IOC IoC, + int Level); + +extern void SkGeDeInit( + SK_AC *pAC, + SK_IOC IoC); + +extern int SkGeInitPort( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkGeXmitLED( + SK_AC *pAC, + SK_IOC IoC, + int Led, + int Mode); + +extern void SkGeInitRamIface( + SK_AC *pAC, + SK_IOC IoC); + +extern int SkGeInitAssignRamToQueues( + SK_AC *pAC, + int ActivePort, + SK_BOOL DualNet); + +/* + * public functions in skxmac2.c + */ +extern void SkMacRxTxDisable( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacSoftRst( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacHardRst( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkXmInitMac( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkGmInitMac( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacInitPhy( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL DoLoop); + +extern void SkMacIrqDisable( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacFlushTxFifo( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacFlushRxFifo( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacIrq( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern int SkMacAutoNegDone( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacAutoNegLipaPhy( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_U16 IStatus); + +extern void SkMacSetRxTxEn( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Para); + +extern int SkMacRxTxEnable( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacPromiscMode( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + +extern void SkMacHashing( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + +extern void SkXmPhyRead( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 *pVal); + +extern void SkXmPhyWrite( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 Val); + +extern void SkGmPhyRead( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 *pVal); + +extern void SkGmPhyWrite( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 Val); + +extern void SkGePhyRead( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 *pVal); + +extern void SkGePhyWrite( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 Val); + +extern void SkXmClrExactAddr( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int StartNum, + int StopNum); + +extern void SkXmInitDupMd( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkXmInitPauseMd( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkXmAutoNegLipaXmac( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_U16 IStatus); + +extern int SkXmUpdateStats( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port); + +extern int SkGmUpdateStats( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port); + +extern int SkXmMacStatistic( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port, + SK_U16 StatAddr, + SK_U32 *pVal); + +extern int SkGmMacStatistic( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port, + SK_U16 StatAddr, + SK_U32 *pVal); + +extern int SkXmResetCounter( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port); + +extern int SkGmResetCounter( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port); + +extern int SkXmOverflowStatus( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port, + SK_U16 IStatus, + SK_U64 *pStatus); + +extern int SkGmOverflowStatus( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port, + SK_U16 MacStatus, + SK_U64 *pStatus); + +extern int SkGmCableDiagStatus( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL StartTest); + +#ifdef SK_DIAG +extern void SkMacSetRxCmd( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Mode); +extern void SkMacCrcGener( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); +extern void SkMacTimeStamp( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); +extern void SkXmSendCont( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); +#endif /* SK_DIAG */ + +#else /* SK_KR_PROTO */ + +/* + * public functions in skgeinit.c + */ +extern void SkGePollRxD(); +extern void SkGePollTxD(); +extern void SkGeYellowLED(); +extern int SkGeCfgSync(); +extern void SkGeLoadLnkSyncCnt(); +extern void SkGeStopPort(); +extern int SkGeInit(); +extern void SkGeDeInit(); +extern int SkGeInitPort(); +extern void SkGeXmitLED(); +extern void SkGeInitRamIface(); +extern int SkGeInitAssignRamToQueues(); + +/* + * public functions in skxmac2.c + */ +extern void SkMacRxTxDisable(); +extern void SkMacSoftRst(); +extern void SkMacHardRst(); +extern void SkMacInitPhy(); +extern int SkMacRxTxEnable(); +extern void SkMacPromiscMode(); +extern void SkMacHashing(); +extern void SkMacIrqDisable(); +extern void SkMacFlushTxFifo(); +extern void SkMacFlushRxFifo(); +extern void SkMacIrq(); +extern int SkMacAutoNegDone(); +extern void SkMacAutoNegLipaPhy(); +extern void SkMacSetRxTxEn(); +extern void SkGePhyRead(); +extern void SkGePhyWrite(); +extern void SkXmInitMac(); +extern void SkXmPhyRead(); +extern void SkXmPhyWrite(); +extern void SkGmInitMac(); +extern void SkGmPhyRead(); +extern void SkGmPhyWrite(); +extern void SkXmClrExactAddr(); +extern void SkXmInitDupMd(); +extern void SkXmInitPauseMd(); +extern void SkXmAutoNegLipaXmac(); +extern int SkXmUpdateStats(); +extern int SkGmUpdateStats(); +extern int SkXmMacStatistic(); +extern int SkGmMacStatistic(); +extern int SkXmResetCounter(); +extern int SkGmResetCounter(); +extern int SkXmOverflowStatus(); +extern int SkGmOverflowStatus(); +extern int SkGmCableDiagStatus(); + +#ifdef SK_DIAG +extern void SkMacSetRxCmd(); +extern void SkMacCrcGener(); +extern void SkMacTimeStamp(); +extern void SkXmSendCont(); +#endif /* SK_DIAG */ + +#endif /* SK_KR_PROTO */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKGEINIT_H_ */ diff --git a/drivers/sk98lin/h/skgepnm2.h b/drivers/sk98lin/h/skgepnm2.h new file mode 100644 index 0000000..5c44f47 --- /dev/null +++ b/drivers/sk98lin/h/skgepnm2.h @@ -0,0 +1,462 @@ +/***************************************************************************** + * + * Name: skgepnm2.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.34 $ + * Date: $Date: 2002/12/16 09:05:18 $ + * Purpose: Defines for Private Network Management Interface + * + ****************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/***************************************************************************** + * + * History: + * + * $Log: skgepnm2.h,v $ + * Revision 1.34 2002/12/16 09:05:18 tschilli + * Code for VCT handling added. + * + * Revision 1.33 2002/09/10 09:00:03 rwahl + * Adapted boolean definitions according sktypes. + * + * Revision 1.32 2002/08/09 09:47:01 rwahl + * Added write-only flag to oid access defines. + * Editorial changes. + * + * Revision 1.31 2002/07/17 19:23:18 rwahl + * - Replaced MAC counter definitions by enumeration. + * - Added definition SK_PNMI_MAC_TYPES. + * - Added chipset defnition for Yukon. + * + * Revision 1.30 2001/02/06 10:03:41 mkunz + * - Pnmi V4 dual net support added. Interface functions and macros extended + * - Vpd bug fixed + * - OID_SKGE_MTU added + * + * Revision 1.29 2001/01/22 13:41:37 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.28 2000/08/03 15:12:48 rwahl + * - Additional comment for MAC statistic data structure. + * + * Revision 1.27 2000/08/01 16:10:18 rwahl + * - Added mac statistic data structure for StatRxLongFrame counter. + * + * Revision 1.26 2000/03/31 13:51:34 rwahl + * Added SK_UPTR cast to offset calculation for PNMI struct fields; + * missing cast caused compiler warnings by Win64 compiler. + * + * Revision 1.25 1999/11/22 13:57:41 cgoos + * Changed license header to GPL. + * Allowing overwrite for SK_PNMI_STORE/_READ defines. + * + * Revision 1.24 1999/04/13 15:11:11 mhaveman + * Changed copyright. + * + * Revision 1.23 1999/01/28 15:07:12 mhaveman + * Changed default threshold for port switches per hour from 10 + * to 240 which means 4 switches per minute. This fits better + * the granularity of 32 for the port switch estimate + * counter. + * + * Revision 1.22 1999/01/05 12:52:30 mhaveman + * Removed macro SK_PNMI_MICRO_SEC. + * + * Revision 1.21 1999/01/05 12:50:34 mhaveman + * Enlarged macro definition SK_PNMI_HUNDREDS_SEC() so that no 64-bit + * arithmetic is necessary if SK_TICKS_PER_SEC is 100. + * + * Revision 1.20 1998/12/09 14:02:53 mhaveman + * Defined macro SK_PNMI_DEF_RLMT_CHG_THRES for default port switch + * threshold. + * + * Revision 1.19 1998/12/03 11:28:41 mhaveman + * Removed SK_PNMI_CHECKPTR macro. + * + * Revision 1.18 1998/12/03 11:21:00 mhaveman + * -Added pointer check macro SK_PNMI_CHECKPTR + * -Added macros SK_PNMI_VPD_ARR_SIZE and SK_PNMI_VPD_STR_SIZE for + * VPD key evaluation. + * + * Revision 1.17 1998/11/20 13:20:33 mhaveman + * Fixed bug in SK_PNMI_SET_STAT macro. ErrorStatus was not correctly set. + * + * Revision 1.16 1998/11/20 08:08:49 mhaveman + * Macro SK_PNMI_CHECKFLAGS has got a if clause. + * + * Revision 1.15 1998/11/03 13:53:40 mhaveman + * Fixed alignment problem in macor SK_PNMI_SET_STAT macro. + * + * Revision 1.14 1998/10/30 15:50:13 mhaveman + * Added macro SK_PNMI_MICRO_SEC() + * + * Revision 1.13 1998/10/30 12:32:20 mhaveman + * Added forgotten cast in SK_PNMI_READ_U32 macro. + * + * Revision 1.12 1998/10/29 15:40:26 mhaveman + * -Changed SK_PNMI_TRAP_SENSOR_LEN because SensorDescr has now + * variable string length. + * -Defined SK_PNMI_CHECKFLAGS macro + * + * Revision 1.11 1998/10/29 08:53:34 mhaveman + * Removed SK_PNMI_RLM_XXX table indexed because these counters need + * not been saved over XMAC resets. + * + * Revision 1.10 1998/10/28 08:48:20 mhaveman + * -Added macros for storage according to alignment + * -Changed type of Instance to SK_U32 because of VPD + * -Removed trap structures. Not needed because of alignment problem + * -Changed type of Action form SK_U8 to int + * + * Revision 1.9 1998/10/21 13:34:45 mhaveman + * Shit, mismatched calculation of SK_PNMI_HUNDREDS_SEC. Corrected. + * + * Revision 1.8 1998/10/21 13:24:58 mhaveman + * Changed calculation of hundreds of seconds. + * + * Revision 1.7 1998/10/20 07:31:41 mhaveman + * Made type changes to unsigned int where possible. + * + * Revision 1.6 1998/09/04 17:04:05 mhaveman + * Added Sync counters to offset storage to provided settled values on + * port switch. + * + * Revision 1.5 1998/09/04 12:45:35 mhaveman + * Removed dummies for SK_DRIVER_ macros. They should be added by driver + * writer in skdrv2nd.h. + * + * Revision 1.4 1998/09/04 11:59:50 mhaveman + * Everything compiles now. Driver Macros for counting still missing. + * + * Revision 1.3 1998/08/24 12:01:35 mhaveman + * Intermediate state. + * + * Revision 1.2 1998/08/17 07:51:40 mhaveman + * Intermediate state. + * + * Revision 1.1 1998/08/11 09:08:40 mhaveman + * Intermediate state. + * + ****************************************************************************/ + +#ifndef _SKGEPNM2_H_ +#define _SKGEPNM2_H_ + +/* + * General definitions + */ +#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */ +#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */ + +#define SK_PNMI_BUS_PCI 1 /* PCI bus*/ + +/* + * Actions + */ +#define SK_PNMI_ACT_IDLE 1 +#define SK_PNMI_ACT_RESET 2 +#define SK_PNMI_ACT_SELFTEST 3 +#define SK_PNMI_ACT_RESETCNT 4 + +/* + * VPD releated defines + */ + +#define SK_PNMI_VPD_RW 1 +#define SK_PNMI_VPD_RO 2 + +#define SK_PNMI_VPD_OK 0 +#define SK_PNMI_VPD_NOTFOUND 1 +#define SK_PNMI_VPD_CUT 2 +#define SK_PNMI_VPD_TIMEOUT 3 +#define SK_PNMI_VPD_FULL 4 +#define SK_PNMI_VPD_NOWRITE 5 +#define SK_PNMI_VPD_FATAL 6 + +#define SK_PNMI_VPD_IGNORE 0 +#define SK_PNMI_VPD_CREATE 1 +#define SK_PNMI_VPD_DELETE 2 + + +/* + * RLMT related defines + */ +#define SK_PNMI_DEF_RLMT_CHG_THRES 240 /* 4 changes per minute */ + + +/* + * VCT internal status values + */ +#define SK_PNMI_VCT_PENDING 32 +#define SK_PNMI_VCT_TEST_DONE 64 +#define SK_PNMI_VCT_LINK 128 + +/* + * Internal table definitions + */ +#define SK_PNMI_GET 0 +#define SK_PNMI_PRESET 1 +#define SK_PNMI_SET 2 + +#define SK_PNMI_RO 0 +#define SK_PNMI_RW 1 +#define SK_PNMI_WO 2 + +typedef struct s_OidTabEntry { + SK_U32 Id; + SK_U32 InstanceNo; + unsigned int StructSize; + unsigned int Offset; + int Access; + int (* Func)(SK_AC *pAc, SK_IOC pIo, int action, + SK_U32 Id, char* pBuf, unsigned int* pLen, + SK_U32 Instance, unsigned int TableIndex, + SK_U32 NetNumber); + SK_U16 Param; +} SK_PNMI_TAB_ENTRY; + + +/* + * Trap lengths + */ +#define SK_PNMI_TRAP_SIMPLE_LEN 17 +#define SK_PNMI_TRAP_SENSOR_LEN_BASE 46 +#define SK_PNMI_TRAP_RLMT_CHANGE_LEN 23 +#define SK_PNMI_TRAP_RLMT_PORT_LEN 23 + +/* + * Number of MAC types supported + */ +#define SK_PNMI_MAC_TYPES (SK_MAC_GMAC + 1) + +/* + * MAC statistic data list (overall set for MAC types used) + */ +enum SK_MACSTATS { + SK_PNMI_HTX = 0, + SK_PNMI_HTX_OCTET, + SK_PNMI_HTX_OCTETHIGH = SK_PNMI_HTX_OCTET, + SK_PNMI_HTX_OCTETLOW, + SK_PNMI_HTX_BROADCAST, + SK_PNMI_HTX_MULTICAST, + SK_PNMI_HTX_UNICAST, + SK_PNMI_HTX_BURST, + SK_PNMI_HTX_PMACC, + SK_PNMI_HTX_MACC, + SK_PNMI_HTX_COL, + SK_PNMI_HTX_SINGLE_COL, + SK_PNMI_HTX_MULTI_COL, + SK_PNMI_HTX_EXCESS_COL, + SK_PNMI_HTX_LATE_COL, + SK_PNMI_HTX_DEFFERAL, + SK_PNMI_HTX_EXCESS_DEF, + SK_PNMI_HTX_UNDERRUN, + SK_PNMI_HTX_CARRIER, + SK_PNMI_HTX_UTILUNDER, + SK_PNMI_HTX_UTILOVER, + SK_PNMI_HTX_64, + SK_PNMI_HTX_127, + SK_PNMI_HTX_255, + SK_PNMI_HTX_511, + SK_PNMI_HTX_1023, + SK_PNMI_HTX_MAX, + SK_PNMI_HTX_LONGFRAMES, + SK_PNMI_HTX_SYNC, + SK_PNMI_HTX_SYNC_OCTET, + SK_PNMI_HTX_RESERVED, + + SK_PNMI_HRX, + SK_PNMI_HRX_OCTET, + SK_PNMI_HRX_OCTETHIGH = SK_PNMI_HRX_OCTET, + SK_PNMI_HRX_OCTETLOW, + SK_PNMI_HRX_BADOCTET, + SK_PNMI_HRX_BADOCTETHIGH = SK_PNMI_HRX_BADOCTET, + SK_PNMI_HRX_BADOCTETLOW, + SK_PNMI_HRX_BROADCAST, + SK_PNMI_HRX_MULTICAST, + SK_PNMI_HRX_UNICAST, + SK_PNMI_HRX_PMACC, + SK_PNMI_HRX_MACC, + SK_PNMI_HRX_PMACC_ERR, + SK_PNMI_HRX_MACC_UNKWN, + SK_PNMI_HRX_BURST, + SK_PNMI_HRX_MISSED, + SK_PNMI_HRX_FRAMING, + SK_PNMI_HRX_UNDERSIZE, + SK_PNMI_HRX_OVERFLOW, + SK_PNMI_HRX_JABBER, + SK_PNMI_HRX_CARRIER, + SK_PNMI_HRX_IRLENGTH, + SK_PNMI_HRX_SYMBOL, + SK_PNMI_HRX_SHORTS, + SK_PNMI_HRX_RUNT, + SK_PNMI_HRX_TOO_LONG, + SK_PNMI_HRX_FCS, + SK_PNMI_HRX_CEXT, + SK_PNMI_HRX_UTILUNDER, + SK_PNMI_HRX_UTILOVER, + SK_PNMI_HRX_64, + SK_PNMI_HRX_127, + SK_PNMI_HRX_255, + SK_PNMI_HRX_511, + SK_PNMI_HRX_1023, + SK_PNMI_HRX_MAX, + SK_PNMI_HRX_LONGFRAMES, + + SK_PNMI_HRX_RESERVED, + + SK_PNMI_MAX_IDX /* NOTE: Ensure SK_PNMI_CNT_NO is set to this value */ +}; + +/* + * MAC specific data + */ +typedef struct s_PnmiStatAddr { + SK_U16 Reg; /* MAC register containing the value */ + SK_BOOL GetOffset; /* TRUE: Offset managed by PNMI (call GetStatVal())*/ +} SK_PNMI_STATADDR; + + +/* + * SK_PNMI_STRUCT_DATA copy offset evaluation macros + */ +#define SK_PNMI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e)) +#define SK_PNMI_MAI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e)) +#define SK_PNMI_VPD_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_VPD *)0)->e)) +#define SK_PNMI_SEN_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_SENSOR *)0)->e)) +#define SK_PNMI_CHK_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CHECKSUM *)0)->e)) +#define SK_PNMI_STA_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STAT *)0)->e)) +#define SK_PNMI_CNF_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CONF *)0)->e)) +#define SK_PNMI_RLM_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT *)0)->e)) +#define SK_PNMI_MON_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT_MONITOR *)0)->e)) +#define SK_PNMI_TRP_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_TRAP *)0)->e)) + +#define SK_PNMI_SET_STAT(b,s,o) {SK_U32 Val32; char *pVal; \ + Val32 = (s); \ + pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \ + &(((SK_PNMI_STRUCT_DATA *)0)-> \ + ReturnStatus.ErrorStatus)); \ + SK_PNMI_STORE_U32(pVal, Val32); \ + Val32 = (o); \ + pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \ + &(((SK_PNMI_STRUCT_DATA *)0)-> \ + ReturnStatus.ErrorOffset)); \ + SK_PNMI_STORE_U32(pVal, Val32);} + +/* + * Time macros + */ +#if SK_TICKS_PER_SEC == 100 +#define SK_PNMI_HUNDREDS_SEC(t) (t) +#else +#define SK_PNMI_HUNDREDS_SEC(t) (((t) * 100) / (SK_TICKS_PER_SEC)) +#endif + +/* + * Macros to work around alignment problems + */ +#ifndef SK_PNMI_STORE_U16 +#define SK_PNMI_STORE_U16(p,v) {*(char *)(p) = *((char *)&(v)); \ + *((char *)(p) + 1) = \ + *(((char *)&(v)) + 1);} +#endif + +#ifndef SK_PNMI_STORE_U32 +#define SK_PNMI_STORE_U32(p,v) {*(char *)(p) = *((char *)&(v)); \ + *((char *)(p) + 1) = \ + *(((char *)&(v)) + 1); \ + *((char *)(p) + 2) = \ + *(((char *)&(v)) + 2); \ + *((char *)(p) + 3) = \ + *(((char *)&(v)) + 3);} +#endif + +#ifndef SK_PNMI_STORE_U64 +#define SK_PNMI_STORE_U64(p,v) {*(char *)(p) = *((char *)&(v)); \ + *((char *)(p) + 1) = \ + *(((char *)&(v)) + 1); \ + *((char *)(p) + 2) = \ + *(((char *)&(v)) + 2); \ + *((char *)(p) + 3) = \ + *(((char *)&(v)) + 3); \ + *((char *)(p) + 4) = \ + *(((char *)&(v)) + 4); \ + *((char *)(p) + 5) = \ + *(((char *)&(v)) + 5); \ + *((char *)(p) + 6) = \ + *(((char *)&(v)) + 6); \ + *((char *)(p) + 7) = \ + *(((char *)&(v)) + 7);} +#endif + +#ifndef SK_PNMI_READ_U16 +#define SK_PNMI_READ_U16(p,v) {*((char *)&(v)) = *(char *)(p); \ + *(((char *)&(v)) + 1) = \ + *((char *)(p) + 1);} +#endif + +#ifndef SK_PNMI_READ_U32 +#define SK_PNMI_READ_U32(p,v) {*((char *)&(v)) = *(char *)(p); \ + *(((char *)&(v)) + 1) = \ + *((char *)(p) + 1); \ + *(((char *)&(v)) + 2) = \ + *((char *)(p) + 2); \ + *(((char *)&(v)) + 3) = \ + *((char *)(p) + 3);} +#endif + +#ifndef SK_PNMI_READ_U64 +#define SK_PNMI_READ_U64(p,v) {*((char *)&(v)) = *(char *)(p); \ + *(((char *)&(v)) + 1) = \ + *((char *)(p) + 1); \ + *(((char *)&(v)) + 2) = \ + *((char *)(p) + 2); \ + *(((char *)&(v)) + 3) = \ + *((char *)(p) + 3); \ + *(((char *)&(v)) + 4) = \ + *((char *)(p) + 4); \ + *(((char *)&(v)) + 5) = \ + *((char *)(p) + 5); \ + *(((char *)&(v)) + 6) = \ + *((char *)(p) + 6); \ + *(((char *)&(v)) + 7) = \ + *((char *)(p) + 7);} +#endif + +/* + * Macros for Debug + */ +#ifdef DEBUG + +#define SK_PNMI_CHECKFLAGS(vSt) {if (pAC->Pnmi.MacUpdatedFlag > 0 || \ + pAC->Pnmi.RlmtUpdatedFlag > 0 || \ + pAC->Pnmi.SirqUpdatedFlag > 0) { \ + SK_DBG_MSG(pAC, \ + SK_DBGMOD_PNMI, \ + SK_DBGCAT_CTRL, \ + ("PNMI: ERR: %s MacUFlag=%d, RlmtUFlag=%d, SirqUFlag=%d\n", \ + vSt, \ + pAC->Pnmi.MacUpdatedFlag, \ + pAC->Pnmi.RlmtUpdatedFlag, \ + pAC->Pnmi.SirqUpdatedFlag))}} + +#else /* !DEBUG */ + +#define SK_PNMI_CHECKFLAGS(vSt) /* Nothing */ + +#endif /* !DEBUG */ + +#endif /* _SKGEPNM2_H_ */ diff --git a/drivers/sk98lin/h/skgepnmi.h b/drivers/sk98lin/h/skgepnmi.h new file mode 100644 index 0000000..7532313 --- /dev/null +++ b/drivers/sk98lin/h/skgepnmi.h @@ -0,0 +1,1114 @@ +/***************************************************************************** + * + * Name: skgepnmi.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.59 $ + * Date: $Date: 2002/12/16 14:03:50 $ + * Purpose: Defines for Private Network Management Interface + * + ****************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/***************************************************************************** + * + * History: + * + * $Log: skgepnmi.h,v $ + * Revision 1.59 2002/12/16 14:03:50 tschilli + * New defines for VCT added. + * + * Revision 1.58 2002/12/16 09:04:59 tschilli + * Code for VCT handling added. + * + * Revision 1.57 2002/09/26 12:41:05 tschilli + * SK_PNMI_PORT BufPort entry in struct SK_PNMI added. + * + * Revision 1.56 2002/08/16 11:10:41 rwahl + * - Replaced c++ comment. + * + * Revision 1.55 2002/08/09 15:40:21 rwahl + * Editorial change (renamed ConfSpeedCap). + * + * Revision 1.54 2002/08/09 11:06:07 rwahl + * Added OID_SKGE_SPEED_CAP. + * + * Revision 1.53 2002/08/09 09:45:28 rwahl + * Added support for NDIS OID_PNP_xxx. + * Editorial changes. + * + * Revision 1.52 2002/08/06 17:54:07 rwahl + * - Added speed cap to PNMI config struct. + * + * Revision 1.51 2002/07/17 19:19:26 rwahl + * - Added OID_SKGE_SPEED_MODE and OID_SKGE_SPEED_STATUS. + * - Added SK_PNMI_CNT_RX_PMACC_ERR() & SK_PNMI_CNT_RX_LONGFRAMES(). + * - Added speed mode & status to PNMI config struct. + * - Editorial changes. + * + * Revision 1.50 2002/05/22 08:59:37 rwahl + * Added string definitions for error msgs. + * + * Revision 1.49 2001/11/20 09:23:50 rwahl + * - pnmi struct: reordered and aligned to 32bit. + * + * Revision 1.48 2001/02/23 14:34:24 mkunz + * Changed macro PHYS2INST. Added pAC to Interface + * + * Revision 1.47 2001/02/07 08:28:23 mkunz + * - Added Oids: OID_SKGE_DIAG_ACTION + * OID_SKGE_DIAG_RESULT + * OID_SKGE_MULTICAST_LIST + * OID_SKGE_CURRENT_PACKET_FILTER + * OID_SKGE_INTERMEDIATE_SUPPORT + * - Changed value of OID_SKGE_MTU + * + * Revision 1.46 2001/02/06 10:01:41 mkunz + * - Pnmi V4 dual net support added. Interface functions and macros extended + * - Vpd bug fixed + * - OID_SKGE_MTU added + * + * Revision 1.45 2001/01/22 13:41:37 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.44 2000/09/07 07:35:27 rwahl + * - removed NDIS counter specific data type. + * - fixed spelling for OID_SKGE_RLMT_PORT_PREFERRED. + * + * Revision 1.43 2000/08/04 11:41:08 rwahl + * - Fixed compiler warning (port is always >= 0) for macros + * SK_PNMI_CNT_RX_LONGFRAMES & SK_PNMI_CNT_SYNC_OCTETS + * + * Revision 1.42 2000/08/03 15:14:07 rwahl + * - Corrected error in driver macros addressing a physical port. + * + * Revision 1.41 2000/08/01 16:22:29 rwahl + * - Changed MDB version to 3.1. + * - Added definitions for StatRxLongFrames counter. + * - Added macro to be used by driver to count long frames received. + * - Added directive to control width (default = 32bit) of NDIS statistic + * counters (SK_NDIS_64BIT_CTR). + * + * Revision 1.40 2000/03/31 13:51:34 rwahl + * Added SK_UPTR cast to offset calculation for PNMI struct fields; + * missing cast caused compiler warnings by Win64 compiler. + * + * Revision 1.39 1999/12/06 10:09:47 rwahl + * Added new error log message. + * + * Revision 1.38 1999/11/22 13:57:55 cgoos + * Changed license header to GPL. + * + * Revision 1.37 1999/09/14 14:25:32 rwahl + * Set MDB version for 1000Base-T (sensors, Master/Slave) changes. + * + * Revision 1.36 1999/05/20 09:24:56 cgoos + * Changes for 1000Base-T (sensors, Master/Slave). + * + * Revision 1.35 1999/04/13 15:10:51 mhaveman + * Replaced RLMT macros SK_RLMT_CHECK_xxx again by those of PNMI to + * grant unified interface. But PNMI macros will store the same + * value as RLMT macros. + * + * Revision 1.34 1999/04/13 15:03:49 mhaveman + * -Changed copyright + * -Removed SK_PNMI_RLMT_MODE_CHK_xxx macros. Those of RLMT should be + * used. + * + * Revision 1.33 1999/03/23 10:41:02 mhaveman + * Changed comments. + * + * Revision 1.32 1999/01/25 15:01:33 mhaveman + * Added support for multiple simultaniously active ports. + * + * Revision 1.31 1999/01/19 10:06:26 mhaveman + * Added new error log message. + * + * Revision 1.30 1999/01/05 10:34:49 mhaveman + * Fixed little error in RlmtChangeEstimate calculation. + * + * Revision 1.29 1999/01/05 09:59:41 mhaveman + * Redesigned port switch average calculation to avoid 64bit + * arithmetic. + * + * Revision 1.28 1998/12/08 10:05:48 mhaveman + * Defined macro SK_PNMI_MIN_STRUCT_SIZE. + * + * Revision 1.27 1998/12/03 14:39:35 mhaveman + * Fixed problem that LSTAT was enumerated wrong. + * + * Revision 1.26 1998/12/03 11:19:51 mhaveman + * Changed contents of errlog message SK_PNMI_ERR016MSG + * + * Revision 1.25 1998/12/01 10:40:04 mhaveman + * Changed size of SensorNumber, ChecksumNumber and RlmtPortNumber in + * SK_PNMI_STRUCT_DATA to be conform with OID definition. + * + * Revision 1.24 1998/11/20 08:09:27 mhaveman + * Added macros to convert between logical, physical port indexes and + * instances. + * + * Revision 1.23 1998/11/10 13:41:13 mhaveman + * Needed to change interface, because NT driver needs a return value + * of needed buffer space on TOO_SHORT errors. Therefore all + * SkPnmiGet/Preset/Set functions now have a pointer to the length + * parameter, where the needed space on error is returned. + * + * Revision 1.22 1998/11/03 12:05:51 mhaveman + * Added pAC parameter to counter macors. + * + * Revision 1.21 1998/11/02 10:47:36 mhaveman + * Added syslog messages for internal errors. + * + * Revision 1.20 1998/10/30 15:49:36 mhaveman + * -Removed unused SK_PNMI_UTILIZATION_BASE and EstOldCnt. + * -Redefined SK_PNMI_CHG_EST_BASE to hundreds of seconds. + * + * Revision 1.19 1998/10/29 15:38:44 mhaveman + * Changed string lengths of PNMI_STRUCT_DATA structure because + * string OIDs are now encoded with leading length ocetet. + * + * Revision 1.18 1998/10/29 08:52:27 mhaveman + * -Added byte to strings in PNMI_STRUCT_DATA structure. + * -Shortened SK_PNMI_RLMT structure to SK_MAX_MACS elements. + * + * Revision 1.17 1998/10/28 08:49:50 mhaveman + * -Changed type of Instance back to SK_U32 because of VPD + * -Changed type from SK_U8 to char of PciBusSpeed, PciBusWidth, PMD, + * and Connector. + * + * Revision 1.16 1998/10/22 10:42:31 mhaveman + * -Removed (SK_U32) casts for OIDs + * -excluded NDIS OIDs when they are already defined with ifndef _NDIS_ + * + * Revision 1.15 1998/10/20 13:56:28 mhaveman + * Headerfile includes now directly other header files to comile correctly. + * + * Revision 1.14 1998/10/20 07:31:09 mhaveman + * Made type changes to unsigned int where possible. + * + * Revision 1.13 1998/10/19 10:53:13 mhaveman + * -Casted OID definitions to SK_U32 + * -Renamed RlmtMAC... to RlmtPort... + * -Changed wrong type of VpdEntriesList from SK_U32 to char * + * + * Revision 1.12 1998/10/13 07:42:27 mhaveman + * -Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA + * -Removed old cvs history entries + * -Renamed MacNumber to PortNumber + * + * Revision 1.11 1998/10/07 10:55:24 mhaveman + * -Added OID_MDB_VERSION. Therefore was a renumbering of the VPD OIDs + * necessary. + * -Added OID_GEN_ Ids to support the windows driver. + * + * Revision 1.10 1998/09/30 13:41:10 mhaveman + * Renamed some OIDs to reduce usage of 'MAC' which is replaced by 'PORT'. + * + * Revision 1.9 1998/09/04 17:06:17 mhaveman + * -Added SyncCounter as macro. + * -Renamed OID_SKGE_.._NO_DESCR_CTS to OID_SKGE_.._NO_BUF_CTS. + * -Added macros for driver description and version strings. + * + * Revision 1.8 1998/09/04 14:36:52 mhaveman + * Added OIDs and Structure to access value of macro counters which are + * counted by the driver. + * + * Revision 1.7 1998/09/04 11:59:36 mhaveman + * Everything compiles now. Driver Macros for counting still missing. + * + ****************************************************************************/ + +#ifndef _SKGEPNMI_H_ +#define _SKGEPNMI_H_ + +/* + * Include dependencies + */ +#include "h/sktypes.h" +#include "h/skerror.h" +#include "h/sktimer.h" +#include "h/ski2c.h" +#include "h/skaddr.h" +#include "h/skrlmt.h" +#include "h/skvpd.h" + +/* + * Management Database Version + */ +#define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */ + + +/* + * Event definitions + */ +#define SK_PNMI_EVT_SIRQ_OVERFLOW 1 /* Counter overflow */ +#define SK_PNMI_EVT_SEN_WAR_LOW 2 /* Lower war thres exceeded */ +#define SK_PNMI_EVT_SEN_WAR_UPP 3 /* Upper war thres exceeded */ +#define SK_PNMI_EVT_SEN_ERR_LOW 4 /* Lower err thres exceeded */ +#define SK_PNMI_EVT_SEN_ERR_UPP 5 /* Upper err thres exceeded */ +#define SK_PNMI_EVT_CHG_EST_TIMER 6 /* Timer event for RLMT Chg */ +#define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */ +#define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */ +#define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */ + +#define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */ +#define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */ +#define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */ +#define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */ +#define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */ +#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets + 1 = single net; 2 = dual net */ +#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */ + + +/* + * Return values + */ +#define SK_PNMI_ERR_OK 0 +#define SK_PNMI_ERR_GENERAL 1 +#define SK_PNMI_ERR_TOO_SHORT 2 +#define SK_PNMI_ERR_BAD_VALUE 3 +#define SK_PNMI_ERR_READ_ONLY 4 +#define SK_PNMI_ERR_UNKNOWN_OID 5 +#define SK_PNMI_ERR_UNKNOWN_INST 6 +#define SK_PNMI_ERR_UNKNOWN_NET 7 + + +/* + * Return values of driver reset function SK_DRIVER_RESET() and + * driver event function SK_DRIVER_EVENT() + */ +#define SK_PNMI_ERR_OK 0 +#define SK_PNMI_ERR_FAIL 1 + + +/* + * Return values of driver test function SK_DRIVER_SELFTEST() + */ +#define SK_PNMI_TST_UNKNOWN (1 << 0) +#define SK_PNMI_TST_TRANCEIVER (1 << 1) +#define SK_PNMI_TST_ASIC (1 << 2) +#define SK_PNMI_TST_SENSOR (1 << 3) +#define SK_PNMI_TST_POWERMGMT (1 << 4) +#define SK_PNMI_TST_PCI (1 << 5) +#define SK_PNMI_TST_MAC (1 << 6) + + +/* + * RLMT specific definitions + */ +#define SK_PNMI_RLMT_STATUS_STANDBY 1 +#define SK_PNMI_RLMT_STATUS_ACTIVE 2 +#define SK_PNMI_RLMT_STATUS_ERROR 3 + +#define SK_PNMI_RLMT_LSTAT_PHY_DOWN 1 +#define SK_PNMI_RLMT_LSTAT_AUTONEG 2 +#define SK_PNMI_RLMT_LSTAT_LOG_DOWN 3 +#define SK_PNMI_RLMT_LSTAT_LOG_UP 4 +#define SK_PNMI_RLMT_LSTAT_INDETERMINATED 5 + +#define SK_PNMI_RLMT_MODE_CHK_LINK (SK_RLMT_CHECK_LINK) +#define SK_PNMI_RLMT_MODE_CHK_RX (SK_RLMT_CHECK_LOC_LINK) +#define SK_PNMI_RLMT_MODE_CHK_SPT (SK_RLMT_CHECK_SEG) +/* #define SK_PNMI_RLMT_MODE_CHK_EX */ + +/* + * OID definition + */ +#ifndef _NDIS_ /* Check, whether NDIS already included OIDs */ + +#define OID_GEN_XMIT_OK 0x00020101 +#define OID_GEN_RCV_OK 0x00020102 +#define OID_GEN_XMIT_ERROR 0x00020103 +#define OID_GEN_RCV_ERROR 0x00020104 +#define OID_GEN_RCV_NO_BUFFER 0x00020105 + +/* #define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 */ +#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202 +/* #define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 */ +#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204 +/* #define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 */ +#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206 +/* #define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 */ +#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208 +/* #define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 */ +#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A +/* #define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B */ +#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C +#define OID_GEN_RCV_CRC_ERROR 0x0002020D +#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E + +#define OID_802_3_PERMANENT_ADDRESS 0x01010101 +#define OID_802_3_CURRENT_ADDRESS 0x01010102 +/* #define OID_802_3_MULTICAST_LIST 0x01010103 */ +/* #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 */ +/* #define OID_802_3_MAC_OPTIONS 0x01010105 */ + +#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101 +#define OID_802_3_XMIT_ONE_COLLISION 0x01020102 +#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103 +#define OID_802_3_XMIT_DEFERRED 0x01020201 +#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202 +#define OID_802_3_RCV_OVERRUN 0x01020203 +#define OID_802_3_XMIT_UNDERRUN 0x01020204 +#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206 +#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207 + +/* + * PnP and PM OIDs + */ +#ifdef SK_POWER_MGMT +#define OID_PNP_CAPABILITIES 0xFD010100 +#define OID_PNP_SET_POWER 0xFD010101 +#define OID_PNP_QUERY_POWER 0xFD010102 +#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103 +#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104 +#define OID_PNP_ENABLE_WAKE_UP 0xFD010106 +#endif /* SK_POWER_MGMT */ + +#endif /* _NDIS_ */ + +#define OID_SKGE_MDB_VERSION 0xFF010100 +#define OID_SKGE_SUPPORTED_LIST 0xFF010101 +#define OID_SKGE_VPD_FREE_BYTES 0xFF010102 +#define OID_SKGE_VPD_ENTRIES_LIST 0xFF010103 +#define OID_SKGE_VPD_ENTRIES_NUMBER 0xFF010104 +#define OID_SKGE_VPD_KEY 0xFF010105 +#define OID_SKGE_VPD_VALUE 0xFF010106 +#define OID_SKGE_VPD_ACCESS 0xFF010107 +#define OID_SKGE_VPD_ACTION 0xFF010108 + +#define OID_SKGE_PORT_NUMBER 0xFF010110 +#define OID_SKGE_DEVICE_TYPE 0xFF010111 +#define OID_SKGE_DRIVER_DESCR 0xFF010112 +#define OID_SKGE_DRIVER_VERSION 0xFF010113 +#define OID_SKGE_HW_DESCR 0xFF010114 +#define OID_SKGE_HW_VERSION 0xFF010115 +#define OID_SKGE_CHIPSET 0xFF010116 +#define OID_SKGE_ACTION 0xFF010117 +#define OID_SKGE_RESULT 0xFF010118 +#define OID_SKGE_BUS_TYPE 0xFF010119 +#define OID_SKGE_BUS_SPEED 0xFF01011A +#define OID_SKGE_BUS_WIDTH 0xFF01011B +/* 0xFF01011C unused */ +#define OID_SKGE_DIAG_ACTION 0xFF01011D +#define OID_SKGE_DIAG_RESULT 0xFF01011E +#define OID_SKGE_MTU 0xFF01011F +#define OID_SKGE_PHYS_CUR_ADDR 0xFF010120 +#define OID_SKGE_PHYS_FAC_ADDR 0xFF010121 +#define OID_SKGE_PMD 0xFF010122 +#define OID_SKGE_CONNECTOR 0xFF010123 +#define OID_SKGE_LINK_CAP 0xFF010124 +#define OID_SKGE_LINK_MODE 0xFF010125 +#define OID_SKGE_LINK_MODE_STATUS 0xFF010126 +#define OID_SKGE_LINK_STATUS 0xFF010127 +#define OID_SKGE_FLOWCTRL_CAP 0xFF010128 +#define OID_SKGE_FLOWCTRL_MODE 0xFF010129 +#define OID_SKGE_FLOWCTRL_STATUS 0xFF01012A +#define OID_SKGE_PHY_OPERATION_CAP 0xFF01012B +#define OID_SKGE_PHY_OPERATION_MODE 0xFF01012C +#define OID_SKGE_PHY_OPERATION_STATUS 0xFF01012D +#define OID_SKGE_MULTICAST_LIST 0xFF01012E +#define OID_SKGE_CURRENT_PACKET_FILTER 0xFF01012F + +#define OID_SKGE_TRAP 0xFF010130 +#define OID_SKGE_TRAP_NUMBER 0xFF010131 + +#define OID_SKGE_RLMT_MODE 0xFF010140 +#define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141 +#define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142 +#define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143 +#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160 + +#define OID_SKGE_SPEED_CAP 0xFF010170 +#define OID_SKGE_SPEED_MODE 0xFF010171 +#define OID_SKGE_SPEED_STATUS 0xFF010172 + +#define OID_SKGE_SENSOR_NUMBER 0xFF020100 +#define OID_SKGE_SENSOR_INDEX 0xFF020101 +#define OID_SKGE_SENSOR_DESCR 0xFF020102 +#define OID_SKGE_SENSOR_TYPE 0xFF020103 +#define OID_SKGE_SENSOR_VALUE 0xFF020104 +#define OID_SKGE_SENSOR_WAR_THRES_LOW 0xFF020105 +#define OID_SKGE_SENSOR_WAR_THRES_UPP 0xFF020106 +#define OID_SKGE_SENSOR_ERR_THRES_LOW 0xFF020107 +#define OID_SKGE_SENSOR_ERR_THRES_UPP 0xFF020108 +#define OID_SKGE_SENSOR_STATUS 0xFF020109 +#define OID_SKGE_SENSOR_WAR_CTS 0xFF02010A +#define OID_SKGE_SENSOR_ERR_CTS 0xFF02010B +#define OID_SKGE_SENSOR_WAR_TIME 0xFF02010C +#define OID_SKGE_SENSOR_ERR_TIME 0xFF02010D + +#define OID_SKGE_CHKSM_NUMBER 0xFF020110 +#define OID_SKGE_CHKSM_RX_OK_CTS 0xFF020111 +#define OID_SKGE_CHKSM_RX_UNABLE_CTS 0xFF020112 +#define OID_SKGE_CHKSM_RX_ERR_CTS 0xFF020113 +#define OID_SKGE_CHKSM_TX_OK_CTS 0xFF020114 +#define OID_SKGE_CHKSM_TX_UNABLE_CTS 0xFF020115 + +#define OID_SKGE_STAT_TX 0xFF020120 +#define OID_SKGE_STAT_TX_OCTETS 0xFF020121 +#define OID_SKGE_STAT_TX_BROADCAST 0xFF020122 +#define OID_SKGE_STAT_TX_MULTICAST 0xFF020123 +#define OID_SKGE_STAT_TX_UNICAST 0xFF020124 +#define OID_SKGE_STAT_TX_LONGFRAMES 0xFF020125 +#define OID_SKGE_STAT_TX_BURST 0xFF020126 +#define OID_SKGE_STAT_TX_PFLOWC 0xFF020127 +#define OID_SKGE_STAT_TX_FLOWC 0xFF020128 +#define OID_SKGE_STAT_TX_SINGLE_COL 0xFF020129 +#define OID_SKGE_STAT_TX_MULTI_COL 0xFF02012A +#define OID_SKGE_STAT_TX_EXCESS_COL 0xFF02012B +#define OID_SKGE_STAT_TX_LATE_COL 0xFF02012C +#define OID_SKGE_STAT_TX_DEFFERAL 0xFF02012D +#define OID_SKGE_STAT_TX_EXCESS_DEF 0xFF02012E +#define OID_SKGE_STAT_TX_UNDERRUN 0xFF02012F +#define OID_SKGE_STAT_TX_CARRIER 0xFF020130 +/* #define OID_SKGE_STAT_TX_UTIL 0xFF020131 */ +#define OID_SKGE_STAT_TX_64 0xFF020132 +#define OID_SKGE_STAT_TX_127 0xFF020133 +#define OID_SKGE_STAT_TX_255 0xFF020134 +#define OID_SKGE_STAT_TX_511 0xFF020135 +#define OID_SKGE_STAT_TX_1023 0xFF020136 +#define OID_SKGE_STAT_TX_MAX 0xFF020137 +#define OID_SKGE_STAT_TX_SYNC 0xFF020138 +#define OID_SKGE_STAT_TX_SYNC_OCTETS 0xFF020139 +#define OID_SKGE_STAT_RX 0xFF02013A +#define OID_SKGE_STAT_RX_OCTETS 0xFF02013B +#define OID_SKGE_STAT_RX_BROADCAST 0xFF02013C +#define OID_SKGE_STAT_RX_MULTICAST 0xFF02013D +#define OID_SKGE_STAT_RX_UNICAST 0xFF02013E +#define OID_SKGE_STAT_RX_PFLOWC 0xFF02013F +#define OID_SKGE_STAT_RX_FLOWC 0xFF020140 +#define OID_SKGE_STAT_RX_PFLOWC_ERR 0xFF020141 +#define OID_SKGE_STAT_RX_FLOWC_UNKWN 0xFF020142 +#define OID_SKGE_STAT_RX_BURST 0xFF020143 +#define OID_SKGE_STAT_RX_MISSED 0xFF020144 +#define OID_SKGE_STAT_RX_FRAMING 0xFF020145 +#define OID_SKGE_STAT_RX_OVERFLOW 0xFF020146 +#define OID_SKGE_STAT_RX_JABBER 0xFF020147 +#define OID_SKGE_STAT_RX_CARRIER 0xFF020148 +#define OID_SKGE_STAT_RX_IR_LENGTH 0xFF020149 +#define OID_SKGE_STAT_RX_SYMBOL 0xFF02014A +#define OID_SKGE_STAT_RX_SHORTS 0xFF02014B +#define OID_SKGE_STAT_RX_RUNT 0xFF02014C +#define OID_SKGE_STAT_RX_CEXT 0xFF02014D +#define OID_SKGE_STAT_RX_TOO_LONG 0xFF02014E +#define OID_SKGE_STAT_RX_FCS 0xFF02014F +/* #define OID_SKGE_STAT_RX_UTIL 0xFF020150 */ +#define OID_SKGE_STAT_RX_64 0xFF020151 +#define OID_SKGE_STAT_RX_127 0xFF020152 +#define OID_SKGE_STAT_RX_255 0xFF020153 +#define OID_SKGE_STAT_RX_511 0xFF020154 +#define OID_SKGE_STAT_RX_1023 0xFF020155 +#define OID_SKGE_STAT_RX_MAX 0xFF020156 +#define OID_SKGE_STAT_RX_LONGFRAMES 0xFF020157 + +#define OID_SKGE_RLMT_CHANGE_CTS 0xFF020160 +#define OID_SKGE_RLMT_CHANGE_TIME 0xFF020161 +#define OID_SKGE_RLMT_CHANGE_ESTIM 0xFF020162 +#define OID_SKGE_RLMT_CHANGE_THRES 0xFF020163 + +#define OID_SKGE_RLMT_PORT_INDEX 0xFF020164 +#define OID_SKGE_RLMT_STATUS 0xFF020165 +#define OID_SKGE_RLMT_TX_HELLO_CTS 0xFF020166 +#define OID_SKGE_RLMT_RX_HELLO_CTS 0xFF020167 +#define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168 +#define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169 + +#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150 +#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151 +#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152 +#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153 +#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154 +#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155 + +#define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170 +#define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171 +#define OID_SKGE_TX_RETRY 0xFF020172 +#define OID_SKGE_RX_INTR_CTS 0xFF020173 +#define OID_SKGE_TX_INTR_CTS 0xFF020174 +#define OID_SKGE_RX_NO_BUF_CTS 0xFF020175 +#define OID_SKGE_TX_NO_BUF_CTS 0xFF020176 +#define OID_SKGE_TX_USED_DESCR_NO 0xFF020177 +#define OID_SKGE_RX_DELIVERED_CTS 0xFF020178 +#define OID_SKGE_RX_OCTETS_DELIV_CTS 0xFF020179 +#define OID_SKGE_RX_HW_ERROR_CTS 0xFF02017A +#define OID_SKGE_TX_HW_ERROR_CTS 0xFF02017B +#define OID_SKGE_IN_ERRORS_CTS 0xFF02017C +#define OID_SKGE_OUT_ERROR_CTS 0xFF02017D +#define OID_SKGE_ERR_RECOVERY_CTS 0xFF02017E +#define OID_SKGE_SYSUPTIME 0xFF02017F + +#define OID_SKGE_ALL_DATA 0xFF020190 + +/* Defines for VCT. */ +#define OID_SKGE_VCT_GET 0xFF020200 +#define OID_SKGE_VCT_SET 0xFF020201 +#define OID_SKGE_VCT_STATUS 0xFF020202 + + +/* VCT struct to store a backup copy of VCT data after a port reset. */ +typedef struct s_PnmiVct { + SK_U8 VctStatus; + SK_U8 PCableLen; + SK_U32 PMdiPairLen[4]; + SK_U8 PMdiPairSts[4]; +} SK_PNMI_VCT; + + +/* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */ +#define SK_PNMI_VCT_NONE 0 +#define SK_PNMI_VCT_OLD_VCT_DATA 1 +#define SK_PNMI_VCT_NEW_VCT_DATA 2 +#define SK_PNMI_VCT_OLD_DSP_DATA 4 +#define SK_PNMI_VCT_NEW_DSP_DATA 8 +#define SK_PNMI_VCT_RUNNING 16 + + +/* VCT cable test status. */ +#define SK_PNMI_VCT_NORMAL_CABLE 0 +#define SK_PNMI_VCT_SHORT_CABLE 1 +#define SK_PNMI_VCT_OPEN_CABLE 2 +#define SK_PNMI_VCT_TEST_FAIL 3 +#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4 + +#define OID_SKGE_TRAP_SEN_WAR_LOW 500 +#define OID_SKGE_TRAP_SEN_WAR_UPP 501 +#define OID_SKGE_TRAP_SEN_ERR_LOW 502 +#define OID_SKGE_TRAP_SEN_ERR_UPP 503 +#define OID_SKGE_TRAP_RLMT_CHANGE_THRES 520 +#define OID_SKGE_TRAP_RLMT_CHANGE_PORT 521 +#define OID_SKGE_TRAP_RLMT_PORT_DOWN 522 +#define OID_SKGE_TRAP_RLMT_PORT_UP 523 +#define OID_SKGE_TRAP_RLMT_SEGMENTATION 524 + + +/* + * Define error numbers and messages for syslog + */ +#define SK_PNMI_ERR001 (SK_ERRBASE_PNMI + 1) +#define SK_PNMI_ERR001MSG "SkPnmiGetStruct: Unknown OID" +#define SK_PNMI_ERR002 (SK_ERRBASE_PNMI + 2) +#define SK_PNMI_ERR002MSG "SkPnmiGetStruct: Cannot read VPD keys" +#define SK_PNMI_ERR003 (SK_ERRBASE_PNMI + 3) +#define SK_PNMI_ERR003MSG "OidStruct: Called with wrong OID" +#define SK_PNMI_ERR004 (SK_ERRBASE_PNMI + 4) +#define SK_PNMI_ERR004MSG "OidStruct: Called with wrong action" +#define SK_PNMI_ERR005 (SK_ERRBASE_PNMI + 5) +#define SK_PNMI_ERR005MSG "Perform: Cannot reset driver" +#define SK_PNMI_ERR006 (SK_ERRBASE_PNMI + 6) +#define SK_PNMI_ERR006MSG "Perform: Unknown OID action command" +#define SK_PNMI_ERR007 (SK_ERRBASE_PNMI + 7) +#define SK_PNMI_ERR007MSG "General: Driver description not initialized" +#define SK_PNMI_ERR008 (SK_ERRBASE_PNMI + 8) +#define SK_PNMI_ERR008MSG "Addr: Tried to get unknown OID" +#define SK_PNMI_ERR009 (SK_ERRBASE_PNMI + 9) +#define SK_PNMI_ERR009MSG "Addr: Unknown OID" +#define SK_PNMI_ERR010 (SK_ERRBASE_PNMI + 10) +#define SK_PNMI_ERR010MSG "CsumStat: Unknown OID" +#define SK_PNMI_ERR011 (SK_ERRBASE_PNMI + 11) +#define SK_PNMI_ERR011MSG "SensorStat: Sensor descr string too long" +#define SK_PNMI_ERR012 (SK_ERRBASE_PNMI + 12) +#define SK_PNMI_ERR012MSG "SensorStat: Unknown OID" +#define SK_PNMI_ERR013 (SK_ERRBASE_PNMI + 13) +#define SK_PNMI_ERR013MSG "" +#define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14) +#define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys" +#define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15) +#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small" +#define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16) +#define SK_PNMI_ERR016MSG "Vpd: Key string too long" +#define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17) +#define SK_PNMI_ERR017MSG "Vpd: Invalid VPD status pointer" +#define SK_PNMI_ERR018 (SK_ERRBASE_PNMI + 18) +#define SK_PNMI_ERR018MSG "Vpd: VPD data not valid" +#define SK_PNMI_ERR019 (SK_ERRBASE_PNMI + 19) +#define SK_PNMI_ERR019MSG "Vpd: VPD entries list string too long" +#define SK_PNMI_ERR021 (SK_ERRBASE_PNMI + 21) +#define SK_PNMI_ERR021MSG "Vpd: VPD data string too long" +#define SK_PNMI_ERR022 (SK_ERRBASE_PNMI + 22) +#define SK_PNMI_ERR022MSG "Vpd: VPD data string too long should be errored before" +#define SK_PNMI_ERR023 (SK_ERRBASE_PNMI + 23) +#define SK_PNMI_ERR023MSG "Vpd: Unknown OID in get action" +#define SK_PNMI_ERR024 (SK_ERRBASE_PNMI + 24) +#define SK_PNMI_ERR024MSG "Vpd: Unknown OID in preset/set action" +#define SK_PNMI_ERR025 (SK_ERRBASE_PNMI + 25) +#define SK_PNMI_ERR025MSG "Vpd: Cannot write VPD after modify entry" +#define SK_PNMI_ERR026 (SK_ERRBASE_PNMI + 26) +#define SK_PNMI_ERR026MSG "Vpd: Cannot update VPD" +#define SK_PNMI_ERR027 (SK_ERRBASE_PNMI + 27) +#define SK_PNMI_ERR027MSG "Vpd: Cannot delete VPD entry" +#define SK_PNMI_ERR028 (SK_ERRBASE_PNMI + 28) +#define SK_PNMI_ERR028MSG "Vpd: Cannot update VPD after delete entry" +#define SK_PNMI_ERR029 (SK_ERRBASE_PNMI + 29) +#define SK_PNMI_ERR029MSG "General: Driver description string too long" +#define SK_PNMI_ERR030 (SK_ERRBASE_PNMI + 30) +#define SK_PNMI_ERR030MSG "General: Driver version not initialized" +#define SK_PNMI_ERR031 (SK_ERRBASE_PNMI + 31) +#define SK_PNMI_ERR031MSG "General: Driver version string too long" +#define SK_PNMI_ERR032 (SK_ERRBASE_PNMI + 32) +#define SK_PNMI_ERR032MSG "General: Cannot read VPD Name for HW descr" +#define SK_PNMI_ERR033 (SK_ERRBASE_PNMI + 33) +#define SK_PNMI_ERR033MSG "General: HW description string too long" +#define SK_PNMI_ERR034 (SK_ERRBASE_PNMI + 34) +#define SK_PNMI_ERR034MSG "General: Unknown OID" +#define SK_PNMI_ERR035 (SK_ERRBASE_PNMI + 35) +#define SK_PNMI_ERR035MSG "Rlmt: Unknown OID" +#define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36) +#define SK_PNMI_ERR036MSG "" +#define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37) +#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0" +#define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38) +#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0" +#define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39) +#define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID" +#define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40) +#define SK_PNMI_ERR040MSG "PowerManagement: Unknown OID" +#define SK_PNMI_ERR041 (SK_ERRBASE_PNMI + 41) +#define SK_PNMI_ERR041MSG "MacPrivateConf: Unknown OID" +#define SK_PNMI_ERR042 (SK_ERRBASE_PNMI + 42) +#define SK_PNMI_ERR042MSG "MacPrivateConf: SK_HWEV_SET_ROLE returned not 0" +#define SK_PNMI_ERR043 (SK_ERRBASE_PNMI + 43) +#define SK_PNMI_ERR043MSG "MacPrivateConf: SK_HWEV_SET_LMODE returned not 0" +#define SK_PNMI_ERR044 (SK_ERRBASE_PNMI + 44) +#define SK_PNMI_ERR044MSG "MacPrivateConf: SK_HWEV_SET_FLOWMODE returned not 0" +#define SK_PNMI_ERR045 (SK_ERRBASE_PNMI + 45) +#define SK_PNMI_ERR045MSG "MacPrivateConf: SK_HWEV_SET_SPEED returned not 0" +#define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46) +#define SK_PNMI_ERR046MSG "Monitor: Unknown OID" +#define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47) +#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0" +#define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48) +#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0" +#define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49) +#define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!" +#define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50) +#define SK_PNMI_ERR050MSG "SkPnmiInit: Invalid size of 'StatAddr' table!!" +#define SK_PNMI_ERR051 (SK_ERRBASE_PNMI + 51) +#define SK_PNMI_ERR051MSG "SkPnmiEvent: Port switch suspicious" +#define SK_PNMI_ERR052 (SK_ERRBASE_PNMI + 52) +#define SK_PNMI_ERR052MSG "" + +/* + * Management counter macros called by the driver + */ +#define SK_PNMI_SET_DRIVER_DESCR(pAC,v) ((pAC)->Pnmi.pDriverDescription = \ + (char *)(v)) + +#define SK_PNMI_SET_DRIVER_VER(pAC,v) ((pAC)->Pnmi.pDriverVersion = \ + (char *)(v)) + + +#define SK_PNMI_CNT_TX_QUEUE_LEN(pAC,v,p) \ + { \ + (pAC)->Pnmi.Port[p].TxSwQueueLen = (SK_U64)(v); \ + if ((pAC)->Pnmi.Port[p].TxSwQueueLen > (pAC)->Pnmi.Port[p].TxSwQueueMax) { \ + (pAC)->Pnmi.Port[p].TxSwQueueMax = (pAC)->Pnmi.Port[p].TxSwQueueLen; \ + } \ + } +#define SK_PNMI_CNT_TX_RETRY(pAC,p) (((pAC)->Pnmi.Port[p].TxRetryCts)++) +#define SK_PNMI_CNT_RX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].RxIntrCts)++) +#define SK_PNMI_CNT_TX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].TxIntrCts)++) +#define SK_PNMI_CNT_NO_RX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].RxNoBufCts)++) +#define SK_PNMI_CNT_NO_TX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].TxNoBufCts)++) +#define SK_PNMI_CNT_USED_TX_DESCR(pAC,v,p) \ + ((pAC)->Pnmi.Port[p].TxUsedDescrNo=(SK_U64)(v)); +#define SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,v,p) \ + { \ + ((pAC)->Pnmi.Port[p].RxDeliveredCts)++; \ + (pAC)->Pnmi.Port[p].RxOctetsDeliveredCts += (SK_U64)(v); \ + } +#define SK_PNMI_CNT_ERR_RECOVERY(pAC,p) (((pAC)->Pnmi.Port[p].ErrRecoveryCts)++); + +#define SK_PNMI_CNT_SYNC_OCTETS(pAC,p,v) \ + { \ + if ((p) < SK_MAX_MACS) { \ + ((pAC)->Pnmi.Port[p].StatSyncCts)++; \ + (pAC)->Pnmi.Port[p].StatSyncOctetsCts += (SK_U64)(v); \ + } \ + } + +#define SK_PNMI_CNT_RX_LONGFRAMES(pAC,p) \ + { \ + if ((p) < SK_MAX_MACS) { \ + ((pAC)->Pnmi.Port[p].StatRxLongFrameCts++); \ + } \ + } + +#define SK_PNMI_CNT_RX_FRAMETOOLONG(pAC,p) \ + { \ + if ((p) < SK_MAX_MACS) { \ + ((pAC)->Pnmi.Port[p].StatRxFrameTooLongCts++); \ + } \ + } + +#define SK_PNMI_CNT_RX_PMACC_ERR(pAC,p) \ + { \ + if ((p) < SK_MAX_MACS) { \ + ((pAC)->Pnmi.Port[p].StatRxPMaccErr++); \ + } \ + } + +/* + * Conversion Macros + */ +#define SK_PNMI_PORT_INST2LOG(i) ((unsigned int)(i) - 1) +#define SK_PNMI_PORT_LOG2INST(l) ((unsigned int)(l) + 1) +#define SK_PNMI_PORT_PHYS2LOG(p) ((unsigned int)(p) + 1) +#define SK_PNMI_PORT_LOG2PHYS(pAC,l) ((unsigned int)(l) - 1) +#define SK_PNMI_PORT_PHYS2INST(pAC,p) \ + (pAC->Pnmi.DualNetActiveFlag ? 2 : ((unsigned int)(p) + 2)) +#define SK_PNMI_PORT_INST2PHYS(pAC,i) ((unsigned int)(i) - 2) + +/* + * Structure definition for SkPnmiGetStruct and SkPnmiSetStruct + */ +#define SK_PNMI_VPD_KEY_SIZE 5 +#define SK_PNMI_VPD_BUFSIZE (VPD_SIZE) +#define SK_PNMI_VPD_ENTRIES (VPD_SIZE / 4) +#define SK_PNMI_VPD_DATALEN 128 /* Number of data bytes */ + +#define SK_PNMI_MULTICAST_LISTLEN 64 +#define SK_PNMI_SENSOR_ENTRIES (SK_MAX_SENSORS) +#define SK_PNMI_CHECKSUM_ENTRIES 3 +#define SK_PNMI_MAC_ENTRIES (SK_MAX_MACS + 1) +#define SK_PNMI_MONITOR_ENTRIES 20 +#define SK_PNMI_TRAP_ENTRIES 10 +#define SK_PNMI_TRAPLEN 128 +#define SK_PNMI_STRINGLEN1 80 +#define SK_PNMI_STRINGLEN2 25 +#define SK_PNMI_TRAP_QUEUE_LEN 512 + +typedef struct s_PnmiVpd { + char VpdKey[SK_PNMI_VPD_KEY_SIZE]; + char VpdValue[SK_PNMI_VPD_DATALEN]; + SK_U8 VpdAccess; + SK_U8 VpdAction; +} SK_PNMI_VPD; + +typedef struct s_PnmiSensor { + SK_U8 SensorIndex; + char SensorDescr[SK_PNMI_STRINGLEN2]; + SK_U8 SensorType; + SK_U32 SensorValue; + SK_U32 SensorWarningThresholdLow; + SK_U32 SensorWarningThresholdHigh; + SK_U32 SensorErrorThresholdLow; + SK_U32 SensorErrorThresholdHigh; + SK_U8 SensorStatus; + SK_U64 SensorWarningCts; + SK_U64 SensorErrorCts; + SK_U64 SensorWarningTimestamp; + SK_U64 SensorErrorTimestamp; +} SK_PNMI_SENSOR; + +typedef struct s_PnmiChecksum { + SK_U64 ChecksumRxOkCts; + SK_U64 ChecksumRxUnableCts; + SK_U64 ChecksumRxErrCts; + SK_U64 ChecksumTxOkCts; + SK_U64 ChecksumTxUnableCts; +} SK_PNMI_CHECKSUM; + +typedef struct s_PnmiStat { + SK_U64 StatTxOkCts; + SK_U64 StatTxOctetsOkCts; + SK_U64 StatTxBroadcastOkCts; + SK_U64 StatTxMulticastOkCts; + SK_U64 StatTxUnicastOkCts; + SK_U64 StatTxLongFramesCts; + SK_U64 StatTxBurstCts; + SK_U64 StatTxPauseMacCtrlCts; + SK_U64 StatTxMacCtrlCts; + SK_U64 StatTxSingleCollisionCts; + SK_U64 StatTxMultipleCollisionCts; + SK_U64 StatTxExcessiveCollisionCts; + SK_U64 StatTxLateCollisionCts; + SK_U64 StatTxDeferralCts; + SK_U64 StatTxExcessiveDeferralCts; + SK_U64 StatTxFifoUnderrunCts; + SK_U64 StatTxCarrierCts; + SK_U64 Dummy1; /* StatTxUtilization */ + SK_U64 StatTx64Cts; + SK_U64 StatTx127Cts; + SK_U64 StatTx255Cts; + SK_U64 StatTx511Cts; + SK_U64 StatTx1023Cts; + SK_U64 StatTxMaxCts; + SK_U64 StatTxSyncCts; + SK_U64 StatTxSyncOctetsCts; + SK_U64 StatRxOkCts; + SK_U64 StatRxOctetsOkCts; + SK_U64 StatRxBroadcastOkCts; + SK_U64 StatRxMulticastOkCts; + SK_U64 StatRxUnicastOkCts; + SK_U64 StatRxLongFramesCts; + SK_U64 StatRxPauseMacCtrlCts; + SK_U64 StatRxMacCtrlCts; + SK_U64 StatRxPauseMacCtrlErrorCts; + SK_U64 StatRxMacCtrlUnknownCts; + SK_U64 StatRxBurstCts; + SK_U64 StatRxMissedCts; + SK_U64 StatRxFramingCts; + SK_U64 StatRxFifoOverflowCts; + SK_U64 StatRxJabberCts; + SK_U64 StatRxCarrierCts; + SK_U64 StatRxIRLengthCts; + SK_U64 StatRxSymbolCts; + SK_U64 StatRxShortsCts; + SK_U64 StatRxRuntCts; + SK_U64 StatRxCextCts; + SK_U64 StatRxTooLongCts; + SK_U64 StatRxFcsCts; + SK_U64 Dummy2; /* StatRxUtilization */ + SK_U64 StatRx64Cts; + SK_U64 StatRx127Cts; + SK_U64 StatRx255Cts; + SK_U64 StatRx511Cts; + SK_U64 StatRx1023Cts; + SK_U64 StatRxMaxCts; +} SK_PNMI_STAT; + +typedef struct s_PnmiConf { + char ConfMacCurrentAddr[6]; + char ConfMacFactoryAddr[6]; + SK_U8 ConfPMD; + SK_U8 ConfConnector; + SK_U8 ConfLinkCapability; + SK_U8 ConfLinkMode; + SK_U8 ConfLinkModeStatus; + SK_U8 ConfLinkStatus; + SK_U8 ConfFlowCtrlCapability; + SK_U8 ConfFlowCtrlMode; + SK_U8 ConfFlowCtrlStatus; + SK_U8 ConfPhyOperationCapability; + SK_U8 ConfPhyOperationMode; + SK_U8 ConfPhyOperationStatus; + SK_U8 ConfSpeedCapability; + SK_U8 ConfSpeedMode; + SK_U8 ConfSpeedStatus; +} SK_PNMI_CONF; + +typedef struct s_PnmiRlmt { + SK_U32 RlmtIndex; + SK_U32 RlmtStatus; + SK_U64 RlmtTxHelloCts; + SK_U64 RlmtRxHelloCts; + SK_U64 RlmtTxSpHelloReqCts; + SK_U64 RlmtRxSpHelloCts; +} SK_PNMI_RLMT; + +typedef struct s_PnmiRlmtMonitor { + SK_U32 RlmtMonitorIndex; + char RlmtMonitorAddr[6]; + SK_U64 RlmtMonitorErrorCts; + SK_U64 RlmtMonitorTimestamp; + SK_U8 RlmtMonitorAdmin; +} SK_PNMI_RLMT_MONITOR; + +typedef struct s_PnmiRequestStatus { + SK_U32 ErrorStatus; + SK_U32 ErrorOffset; +} SK_PNMI_REQUEST_STATUS; + +typedef struct s_PnmiStrucData { + SK_U32 MgmtDBVersion; + SK_PNMI_REQUEST_STATUS ReturnStatus; + SK_U32 VpdFreeBytes; + char VpdEntriesList[SK_PNMI_VPD_ENTRIES * SK_PNMI_VPD_KEY_SIZE]; + SK_U32 VpdEntriesNumber; + SK_PNMI_VPD Vpd[SK_PNMI_VPD_ENTRIES]; + SK_U32 PortNumber; + SK_U32 DeviceType; + char DriverDescr[SK_PNMI_STRINGLEN1]; + char DriverVersion[SK_PNMI_STRINGLEN2]; + char HwDescr[SK_PNMI_STRINGLEN1]; + char HwVersion[SK_PNMI_STRINGLEN2]; + SK_U16 Chipset; + SK_U32 MtuSize; + SK_U32 Action; + SK_U32 TestResult; + SK_U8 BusType; + SK_U8 BusSpeed; + SK_U8 BusWidth; + SK_U8 SensorNumber; + SK_PNMI_SENSOR Sensor[SK_PNMI_SENSOR_ENTRIES]; + SK_U8 ChecksumNumber; + SK_PNMI_CHECKSUM Checksum[SK_PNMI_CHECKSUM_ENTRIES]; + SK_PNMI_STAT Stat[SK_PNMI_MAC_ENTRIES]; + SK_PNMI_CONF Conf[SK_PNMI_MAC_ENTRIES]; + SK_U8 RlmtMode; + SK_U32 RlmtPortNumber; + SK_U8 RlmtPortActive; + SK_U8 RlmtPortPreferred; + SK_U64 RlmtChangeCts; + SK_U64 RlmtChangeTime; + SK_U64 RlmtChangeEstimate; + SK_U64 RlmtChangeThreshold; + SK_PNMI_RLMT Rlmt[SK_MAX_MACS]; + SK_U32 RlmtMonitorNumber; + SK_PNMI_RLMT_MONITOR RlmtMonitor[SK_PNMI_MONITOR_ENTRIES]; + SK_U32 TrapNumber; + SK_U8 Trap[SK_PNMI_TRAP_QUEUE_LEN]; + SK_U64 TxSwQueueLen; + SK_U64 TxSwQueueMax; + SK_U64 TxRetryCts; + SK_U64 RxIntrCts; + SK_U64 TxIntrCts; + SK_U64 RxNoBufCts; + SK_U64 TxNoBufCts; + SK_U64 TxUsedDescrNo; + SK_U64 RxDeliveredCts; + SK_U64 RxOctetsDeliveredCts; + SK_U64 RxHwErrorsCts; + SK_U64 TxHwErrorsCts; + SK_U64 InErrorsCts; + SK_U64 OutErrorsCts; + SK_U64 ErrRecoveryCts; + SK_U64 SysUpTime; +} SK_PNMI_STRUCT_DATA; + +#define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA)) +#define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\ + &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes)) + /* + * ReturnStatus field + * must be located + * before VpdFreeBytes + */ + +/* + * Various definitions + */ +#define SK_PNMI_MAX_PROTOS 3 + +#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum + * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK + * for check while init phase 1 + */ + +/* + * Estimate data structure + */ +typedef struct s_PnmiEstimate { + unsigned int EstValueIndex; + SK_U64 EstValue[7]; + SK_U64 Estimate; + SK_TIMER EstTimer; +} SK_PNMI_ESTIMATE; + + +/* + * VCT timer data structure + */ +typedef struct s_VctTimer { + SK_TIMER VctTimer; +} SK_PNMI_VCT_TIMER; + + +/* + * PNMI specific adapter context structure + */ +typedef struct s_PnmiPort { + SK_U64 StatSyncCts; + SK_U64 StatSyncOctetsCts; + SK_U64 StatRxLongFrameCts; + SK_U64 StatRxFrameTooLongCts; + SK_U64 StatRxPMaccErr; + SK_U64 TxSwQueueLen; + SK_U64 TxSwQueueMax; + SK_U64 TxRetryCts; + SK_U64 RxIntrCts; + SK_U64 TxIntrCts; + SK_U64 RxNoBufCts; + SK_U64 TxNoBufCts; + SK_U64 TxUsedDescrNo; + SK_U64 RxDeliveredCts; + SK_U64 RxOctetsDeliveredCts; + SK_U64 RxHwErrorsCts; + SK_U64 TxHwErrorsCts; + SK_U64 InErrorsCts; + SK_U64 OutErrorsCts; + SK_U64 ErrRecoveryCts; + SK_U64 RxShortZeroMark; + SK_U64 CounterOffset[SK_PNMI_CNT_NO]; + SK_U32 CounterHigh[SK_PNMI_CNT_NO]; + SK_BOOL ActiveFlag; + SK_U8 Align[3]; +} SK_PNMI_PORT; + + +typedef struct s_PnmiData { + SK_PNMI_PORT Port [SK_MAX_MACS]; + SK_PNMI_PORT BufPort [SK_MAX_MACS]; /* 2002-09-13 pweber */ + SK_U64 VirtualCounterOffset[SK_PNMI_CNT_NO]; + SK_U32 TestResult; + char HwVersion[10]; + SK_U16 Align01; + + char *pDriverDescription; + char *pDriverVersion; + + int MacUpdatedFlag; + int RlmtUpdatedFlag; + int SirqUpdatedFlag; + + SK_U64 RlmtChangeCts; + SK_U64 RlmtChangeTime; + SK_PNMI_ESTIMATE RlmtChangeEstimate; + SK_U64 RlmtChangeThreshold; + + SK_U64 StartUpTime; + SK_U32 DeviceType; + char PciBusSpeed; + char PciBusWidth; + char Chipset; + char PMD; + char Connector; + SK_BOOL DualNetActiveFlag; + SK_U16 Align02; + + char TrapBuf[SK_PNMI_TRAP_QUEUE_LEN]; + unsigned int TrapBufFree; + unsigned int TrapQueueBeg; + unsigned int TrapQueueEnd; + unsigned int TrapBufPad; + unsigned int TrapUnique; + SK_U8 VctStatus[SK_MAX_MACS]; + SK_PNMI_VCT VctBackup[SK_MAX_MACS]; + SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS]; +} SK_PNMI; + + +/* + * Function prototypes + */ +extern int SkPnmiInit(SK_AC *pAc, SK_IOC IoC, int level); +extern int SkPnmiGetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, void* pBuf, + unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex); +extern int SkPnmiPreSetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, + void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +extern int SkPnmiSetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, void* pBuf, + unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +extern int SkPnmiGetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf, + unsigned int *pLen, SK_U32 NetIndex); +extern int SkPnmiPreSetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf, + unsigned int *pLen, SK_U32 NetIndex); +extern int SkPnmiSetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf, + unsigned int *pLen, SK_U32 NetIndex); +extern int SkPnmiEvent(SK_AC *pAc, SK_IOC IoC, SK_U32 Event, + SK_EVPARA Param); + +#endif diff --git a/drivers/sk98lin/h/skgesirq.h b/drivers/sk98lin/h/skgesirq.h new file mode 100644 index 0000000..fc001b2 --- /dev/null +++ b/drivers/sk98lin/h/skgesirq.h @@ -0,0 +1,194 @@ +/****************************************************************************** + * + * Name: skgesirq.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.26 $ + * Date: $Date: 2002/10/14 09:52:36 $ + * Purpose: SK specific Gigabit Ethernet special IRQ functions + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skgesirq.h,v $ + * Revision 1.26 2002/10/14 09:52:36 rschmidt + * Added SKERR_SIRQ_E023 and SKERR_SIRQ_E023 for GPHY (Yukon) + * Editorial changes + * + * Revision 1.25 2002/07/15 18:15:52 rwahl + * Editorial changes. + * + * Revision 1.24 2002/07/15 15:39:21 rschmidt + * Corrected define for SKERR_SIRQ_E022 + * Editorial changes + * + * Revision 1.23 2002/04/25 11:09:45 rschmidt + * Removed declarations for SkXmInitPhy(), SkXmRxTxEnable() + * Editorial changes + * + * Revision 1.22 2000/11/09 11:30:10 rassmann + * WA: Waiting after releasing reset until BCom chip is accessible. + * + * Revision 1.21 2000/10/18 12:22:40 cgoos + * Added workaround for half duplex hangup. + * + * Revision 1.20 1999/12/06 10:00:44 cgoos + * Added SET event for role. + * + * Revision 1.19 1999/11/22 13:58:26 cgoos + * Changed license header to GPL. + * + * Revision 1.18 1999/05/19 07:32:59 cgoos + * Changes for 1000Base-T. + * + * Revision 1.17 1999/03/12 13:29:31 malthoff + * Move Autonegotiation Error Codes to skgeinit.h. + * + * Revision 1.16 1999/03/08 10:11:28 gklug + * add: AutoNegDone return codes + * + * Revision 1.15 1998/11/18 13:20:53 gklug + * add: different timeouts for active and non-active links + * + * Revision 1.14 1998/11/04 07:18:14 cgoos + * Added prototype for SkXmRxTxEnable. + * + * Revision 1.13 1998/10/21 05:52:23 gklug + * add: parameter DoLoop to InitPhy function + * + * Revision 1.12 1998/10/19 06:45:03 cgoos + * Added prototype for SkXmInitPhy. + * + * Revision 1.11 1998/10/15 14:34:10 gklug + * add: WA_TIME is 500 msec + * + * Revision 1.10 1998/10/14 14:49:41 malthoff + * Remove err log defines E021 and E022. They are + * defined in skgeinit.h now. + * + * Revision 1.9 1998/10/14 14:00:39 gklug + * add: error logs for init phys + * + * Revision 1.8 1998/10/14 05:44:05 gklug + * add: E020 + * + * Revision 1.7 1998/10/02 06:24:58 gklug + * add: error messages + * + * Revision 1.6 1998/10/01 07:54:45 gklug + * add: PNMI debug module + * + * Revision 1.5 1998/09/28 13:36:31 malthoff + * Move the bit definitions for Autonegotiation + * and Flow Control to skgeinit.h. + * + * Revision 1.4 1998/09/15 12:29:34 gklug + * add: error logs + * + * Revision 1.3 1998/09/03 13:54:02 gklug + * add: function prototypes + * + * Revision 1.2 1998/09/03 10:24:36 gklug + * add: Events send by PNMI + * add: parameter definition for Flow Control etc. + * + * Revision 1.1 1998/08/27 11:50:27 gklug + * initial revision + * + * + ******************************************************************************/ + +#ifndef _INC_SKGESIRQ_H_ +#define _INC_SKGESIRQ_H_ + +/* + * Define the Event the special IRQ/INI module can handle + */ +#define SK_HWEV_WATIM 1 /* Timeout for WA errata #2 XMAC */ +#define SK_HWEV_PORT_START 2 /* Port Start Event by RLMT */ +#define SK_HWEV_PORT_STOP 3 /* Port Stop Event by RLMT */ +#define SK_HWEV_CLEAR_STAT 4 /* Clear Statistics by PNMI */ +#define SK_HWEV_UPDATE_STAT 5 /* Update Statistics by PNMI */ +#define SK_HWEV_SET_LMODE 6 /* Set Link Mode by PNMI */ +#define SK_HWEV_SET_FLOWMODE 7 /* Set Flow Control Mode by PNMI */ +#define SK_HWEV_SET_ROLE 8 /* Set Master/Slave (Role) by PNMI */ +#define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */ +#define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */ + +#define SK_WA_ACT_TIME (5000000L) /* 5 sec */ +#define SK_WA_INA_TIME (100000L) /* 100 msec */ + +#define SK_HALFDUP_CHK_TIME (10000L) /* 10 msec */ + +/* + * Define the error numbers and messages + */ +#define SKERR_SIRQ_E001 (SK_ERRBASE_SIRQ+0) +#define SKERR_SIRQ_E001MSG "Unknown event" +#define SKERR_SIRQ_E002 (SKERR_SIRQ_E001+1) +#define SKERR_SIRQ_E002MSG "Packet timeout RX1" +#define SKERR_SIRQ_E003 (SKERR_SIRQ_E002+1) +#define SKERR_SIRQ_E003MSG "Packet timeout RX2" +#define SKERR_SIRQ_E004 (SKERR_SIRQ_E003+1) +#define SKERR_SIRQ_E004MSG "MAC 1 not correctly initialized" +#define SKERR_SIRQ_E005 (SKERR_SIRQ_E004+1) +#define SKERR_SIRQ_E005MSG "MAC 2 not correctly initialized" +#define SKERR_SIRQ_E006 (SKERR_SIRQ_E005+1) +#define SKERR_SIRQ_E006MSG "CHECK failure R1" +#define SKERR_SIRQ_E007 (SKERR_SIRQ_E006+1) +#define SKERR_SIRQ_E007MSG "CHECK failure R2" +#define SKERR_SIRQ_E008 (SKERR_SIRQ_E007+1) +#define SKERR_SIRQ_E008MSG "CHECK failure XS1" +#define SKERR_SIRQ_E009 (SKERR_SIRQ_E008+1) +#define SKERR_SIRQ_E009MSG "CHECK failure XA1" +#define SKERR_SIRQ_E010 (SKERR_SIRQ_E009+1) +#define SKERR_SIRQ_E010MSG "CHECK failure XS2" +#define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1) +#define SKERR_SIRQ_E011MSG "CHECK failure XA2" +#define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1) +#define SKERR_SIRQ_E012MSG "unexpected IRQ Master error" +#define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1) +#define SKERR_SIRQ_E013MSG "unexpected IRQ Status error" +#define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1) +#define SKERR_SIRQ_E014MSG "Parity error on RAM (read)" +#define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1) +#define SKERR_SIRQ_E015MSG "Parity error on RAM (write)" +#define SKERR_SIRQ_E016 (SKERR_SIRQ_E015+1) +#define SKERR_SIRQ_E016MSG "Parity error MAC 1" +#define SKERR_SIRQ_E017 (SKERR_SIRQ_E016+1) +#define SKERR_SIRQ_E017MSG "Parity error MAC 2" +#define SKERR_SIRQ_E018 (SKERR_SIRQ_E017+1) +#define SKERR_SIRQ_E018MSG "Parity error RX 1" +#define SKERR_SIRQ_E019 (SKERR_SIRQ_E018+1) +#define SKERR_SIRQ_E019MSG "Parity error RX 2" +#define SKERR_SIRQ_E020 (SKERR_SIRQ_E019+1) +#define SKERR_SIRQ_E020MSG "MAC transmit FIFO underrun" +#define SKERR_SIRQ_E021 (SKERR_SIRQ_E020+1) +#define SKERR_SIRQ_E021MSG "Spurious TWSI interrupt" +#define SKERR_SIRQ_E022 (SKERR_SIRQ_E021+1) +#define SKERR_SIRQ_E022MSG "Cable pair swap error" +#define SKERR_SIRQ_E023 (SKERR_SIRQ_E022+1) +#define SKERR_SIRQ_E023MSG "Auto-negotiation error" +#define SKERR_SIRQ_E024 (SKERR_SIRQ_E023+1) +#define SKERR_SIRQ_E024MSG "FIFO overflow error" + +extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus); +extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para); +extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port); +extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port); + +#endif /* _INC_SKGESIRQ_H_ */ diff --git a/drivers/sk98lin/h/ski2c.h b/drivers/sk98lin/h/ski2c.h new file mode 100644 index 0000000..5ffaf6e --- /dev/null +++ b/drivers/sk98lin/h/ski2c.h @@ -0,0 +1,292 @@ +/****************************************************************************** + * + * Name: ski2c.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.34 $ + * Date: $Date: 2003/01/28 09:11:21 $ + * Purpose: Defines to access Voltage and Temperature Sensor + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: ski2c.h,v $ + * Revision 1.34 2003/01/28 09:11:21 rschmidt + * Editorial changes + * + * Revision 1.33 2002/10/14 16:40:50 rschmidt + * Editorial changes (TWSI) + * + * Revision 1.32 2002/08/13 08:55:07 rschmidt + * Editorial changes + * + * Revision 1.31 2002/08/06 09:44:22 jschmalz + * Extensions and changes for Yukon + * + * Revision 1.30 2001/04/05 11:38:09 rassmann + * Set SenState to idle in SkI2cWaitIrq(). + * Changed error message in SkI2cWaitIrq(). + * + * Revision 1.29 2000/08/03 14:28:17 rassmann + * - Added function to wait for I2C being ready before resetting the board. + * - Replaced one duplicate "out of range" message with correct one. + * + * Revision 1.28 1999/11/22 13:55:46 cgoos + * Changed license header to GPL. + * + * Revision 1.27 1999/05/20 09:23:10 cgoos + * Changes for 1000Base-T (Fan sensors). + * + * Revision 1.26 1998/12/01 13:45:47 gklug + * add: InitLevel to I2c struct + * + * Revision 1.25 1998/11/03 06:55:16 gklug + * add: Dummy Reads to I2c struct + * + * Revision 1.24 1998/10/02 14:28:59 cgoos + * Added prototype for SkI2cIsr. + * + * Revision 1.23 1998/09/08 12:20:11 gklug + * add: prototypes for init and read functions + * + * Revision 1.22 1998/09/08 07:37:56 gklug + * add: log error if PCI_IO voltage sensor could not be initialized + * + * Revision 1.21 1998/09/04 08:38:05 malthoff + * Change the values for I2C_READ and I2C_WRITE + * + * Revision 1.20 1998/08/25 07:52:22 gklug + * chg: Timestamps (last) added for logging + * + * Revision 1.19 1998/08/25 06:09:00 gklug + * rmv: warning and error levels of the individual sensors. + * add: timing definitions for sending traps and logging errors + * + * Revision 1.18 1998/08/20 11:41:15 gklug + * chg: omit STRCPY macro by using char * as Sensor Description + * + * Revision 1.17 1998/08/20 11:37:43 gklug + * chg: change Ioc to IoC + * + * Revision 1.16 1998/08/20 11:30:38 gklug + * fix: SenRead declaration + * + * Revision 1.15 1998/08/20 11:27:53 gklug + * fix: Compile bugs with new awrning constants + * + * Revision 1.14 1998/08/20 08:53:12 gklug + * fix: compiler errors + * add: Threshold values + * + * Revision 1.13 1998/08/19 12:21:16 gklug + * fix: remove struct from C files (see CCC) + * add: typedefs for all structs + * + * Revision 1.12 1998/08/19 10:57:41 gklug + * add: Warning levels + * + * Revision 1.11 1998/08/18 08:37:02 malthoff + * Prototypes not required for SK_DIAG. + * + * Revision 1.10 1998/08/17 13:54:00 gklug + * fix: declaration of event function + * + * Revision 1.9 1998/08/17 06:48:39 malthoff + * Remove some unrequired macros. + * Fix the compiler errors. + * + * Revision 1.8 1998/08/14 06:47:19 gklug + * fix: Values are intergers + * + * Revision 1.7 1998/08/14 06:26:05 gklug + * add: Init error message + * + * Revision 1.6 1998/08/13 08:31:08 gklug + * add: Error message + * + * Revision 1.5 1998/08/12 14:32:04 gklug + * add: new error code/message + * + * Revision 1.4 1998/08/12 13:39:08 gklug + * chg: names of error messages + * add: defines for Sensor type and thresholds + * + * Revision 1.3 1998/08/11 07:57:16 gklug + * add: sensor struct + * add: Timeout defines + * add: I2C control struct for pAC + * + * Revision 1.2 1998/07/17 11:29:02 gklug + * rmv: Microwire and SMTPANIC + * + * Revision 1.1 1998/06/19 14:30:10 malthoff + * Created. Sources taken from ML Project. + * + * + ******************************************************************************/ + +/* + * SKI2C.H contains all I2C specific defines + */ + +#ifndef _SKI2C_H_ +#define _SKI2C_H_ + +typedef struct s_Sensor SK_SENSOR; + +#include "h/skgei2c.h" + +/* + * Define the I2C events. + */ +#define SK_I2CEV_IRQ 1 /* IRQ happened Event */ +#define SK_I2CEV_TIM 2 /* Timeout event */ +#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */ + +/* + * Define READ and WRITE Constants. + */ +#undef I2C_READ /* just in case */ +#undef I2C_WRITE /* just in case */ +#define I2C_READ 0 +#define I2C_WRITE 1 +#define I2C_BURST 1 +#define I2C_SINGLE 0 + +#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0) +#define SKERR_I2C_E001MSG "Sensor index unknown" +#define SKERR_I2C_E002 (SKERR_I2C_E001+1) +#define SKERR_I2C_E002MSG "TWSI: transfer does not complete" +#define SKERR_I2C_E003 (SKERR_I2C_E002+1) +#define SKERR_I2C_E003MSG "LM80: NAK on device send" +#define SKERR_I2C_E004 (SKERR_I2C_E003+1) +#define SKERR_I2C_E004MSG "LM80: NAK on register send" +#define SKERR_I2C_E005 (SKERR_I2C_E004+1) +#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send" +#define SKERR_I2C_E006 (SKERR_I2C_E005+1) +#define SKERR_I2C_E006MSG "Unknown event" +#define SKERR_I2C_E007 (SKERR_I2C_E006+1) +#define SKERR_I2C_E007MSG "LM80 read out of state" +#define SKERR_I2C_E008 (SKERR_I2C_E007+1) +#define SKERR_I2C_E008MSG "Unexpected sensor read completed" +#define SKERR_I2C_E009 (SKERR_I2C_E008+1) +#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range" +#define SKERR_I2C_E010 (SKERR_I2C_E009+1) +#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range" +#define SKERR_I2C_E011 (SKERR_I2C_E010+1) +#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range" +#define SKERR_I2C_E012 (SKERR_I2C_E011+1) +#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range" +#define SKERR_I2C_E013 (SKERR_I2C_E012+1) +#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor" +#define SKERR_I2C_E014 (SKERR_I2C_E013+1) +#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range" +#define SKERR_I2C_E015 (SKERR_I2C_E014+1) +#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range" +#define SKERR_I2C_E016 (SKERR_I2C_E015+1) +#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete" + +/* + * Define Timeout values + */ +#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */ +#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */ +#define SK_I2C_TIM_WATCH 1000000L /* 1 second */ + +/* + * Define trap and error log hold times + */ +#ifndef SK_SEN_ERR_TR_HOLD +#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_ERR_LOG_HOLD +#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_WARN_TR_HOLD +#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_WARN_LOG_HOLD +#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC) +#endif + +/* + * Defines for SenType + */ +#define SK_SEN_UNKNOWN 0 +#define SK_SEN_TEMP 1 +#define SK_SEN_VOLT 2 +#define SK_SEN_FAN 3 + +/* + * Define for the SenErrorFlag + */ +#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */ +#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */ +#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */ +#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */ +#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */ + +/* + * Define the Sensor struct + */ +struct s_Sensor { + char *SenDesc; /* Description */ + int SenType; /* Voltage or Temperature */ + SK_I32 SenValue; /* Current value of the sensor */ + SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */ + SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */ + SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */ + SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */ + int SenErrFlag; /* Sensor indicated an error */ + SK_BOOL SenInit; /* Is sensor initialized ? */ + SK_U64 SenErrCts; /* Error trap counter */ + SK_U64 SenWarnCts; /* Warning trap counter */ + SK_U64 SenBegErrTS; /* Begin error timestamp */ + SK_U64 SenBegWarnTS; /* Begin warning timestamp */ + SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */ + SK_U64 SenLastErrLogTS; /* Last error log timestamp */ + SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */ + SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */ + int SenState; /* Sensor State (see HW specific include) */ + int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen); + /* Sensors read function */ + SK_U16 SenReg; /* Register Address for this sensor */ + SK_U8 SenDev; /* Device Selection for this sensor */ +}; + +typedef struct s_I2c { + SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */ + int CurrSens; /* Which sensor is currently queried */ + int MaxSens; /* Max. number of sensors */ + int TimerMode; /* Use the timer also to watch the state machine */ + int InitLevel; /* Initialized Level */ +#ifndef SK_DIAG + int DummyReads; /* Number of non-checked dummy reads */ + SK_TIMER SenTimer; /* Sensors timer */ +#endif /* !SK_DIAG */ +} SK_I2C; + +extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); +#ifndef SK_DIAG +extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para); +extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level); +extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC); +extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC); + +#endif +#endif /* n_SKI2C_H */ diff --git a/drivers/sk98lin/h/skqueue.h b/drivers/sk98lin/h/skqueue.h new file mode 100644 index 0000000..bce20a7 --- /dev/null +++ b/drivers/sk98lin/h/skqueue.h @@ -0,0 +1,147 @@ +/****************************************************************************** + * + * Name: skqueue.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.14 $ + * Date: $Date: 2002/03/15 10:52:13 $ + * Purpose: Defines for the Event queue + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skqueue.h,v $ + * Revision 1.14 2002/03/15 10:52:13 mkunz + * Added event classes for link aggregation + * + * Revision 1.13 1999/11/22 13:59:05 cgoos + * Changed license header to GPL. + * + * Revision 1.12 1998/09/08 08:48:01 gklug + * add: init level handling + * + * Revision 1.11 1998/09/03 14:15:11 gklug + * add: CSUM and HWAC Eventclass and function. + * fix: pParaPtr according to CCC + * + * Revision 1.10 1998/08/20 12:43:03 gklug + * add: typedef SK_QUEUE + * + * Revision 1.9 1998/08/19 09:50:59 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.8 1998/08/18 07:00:01 gklug + * fix: SK_PTR not defined use void * instead. + * + * Revision 1.7 1998/08/17 13:43:19 gklug + * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR + * + * Revision 1.6 1998/08/14 07:09:30 gklug + * fix: chg pAc -> pAC + * + * Revision 1.5 1998/08/11 14:26:44 gklug + * chg: Event Dispatcher returns now int. + * + * Revision 1.4 1998/08/11 12:15:21 gklug + * add: Error numbers of skqueue module + * + * Revision 1.3 1998/08/07 12:54:23 gklug + * fix: first compiled version + * + * Revision 1.2 1998/08/07 09:34:00 gklug + * adapt structure defs to CCC + * add: prototypes for functions + * + * Revision 1.1 1998/07/30 14:52:12 gklug + * Initial version. + * Defines Event Classes, Event structs and queue management variables. + * + * + * + ******************************************************************************/ + +/* + * SKQUEUE.H contains all defines and types for the event queue + */ + +#ifndef _SKQUEUE_H_ +#define _SKQUEUE_H_ + + +/* + * define the event classes to be served + */ +#define SKGE_DRV 1 /* Driver Event Class */ +#define SKGE_RLMT 2 /* RLMT Event Class */ +#define SKGE_I2C 3 /* i2C Event Class */ +#define SKGE_PNMI 4 /* PNMI Event Class */ +#define SKGE_CSUM 5 /* Checksum Event Class */ +#define SKGE_HWAC 6 /* Hardware Access Event Class */ + +#define SKGE_SWT 9 /* Software Timer Event Class */ +#define SKGE_LACP 10 /* LACP Aggregation Event Class */ +#define SKGE_RSF 11 /* RSF Aggregation Event Class */ +#define SKGE_MARKER 12 /* MARKER Aggregation Event Class */ +#define SKGE_FD 13 /* FD Distributor Event Class */ + +/* + * define event queue as circular buffer + */ +#define SK_MAX_EVENT 64 + +/* + * Parameter union for the Para stuff + */ +typedef union u_EvPara { + void *pParaPtr; /* Parameter Pointer */ + SK_U64 Para64; /* Parameter 64bit version */ + SK_U32 Para32[2]; /* Parameter Array of 32bit parameters */ +} SK_EVPARA; + +/* + * Event Queue + * skqueue.c + * events are class/value pairs + * class is addressee, e.g. RMT, PCM etc. + * value is command, e.g. line state change, ring op change etc. + */ +typedef struct s_EventElem { + SK_U32 Class ; /* Event class */ + SK_U32 Event ; /* Event value */ + SK_EVPARA Para ; /* Event parameter */ +} SK_EVENTELEM; + +typedef struct s_Queue { + SK_EVENTELEM EvQueue[SK_MAX_EVENT]; + SK_EVENTELEM *EvPut ; + SK_EVENTELEM *EvGet ; +} SK_QUEUE; + +extern void SkEventInit(SK_AC *pAC, SK_IOC Ioc, int Level); +extern void SkEventQueue(SK_AC *pAC, SK_U32 Class, SK_U32 Event, + SK_EVPARA Para); +extern int SkEventDispatcher(SK_AC *pAC,SK_IOC Ioc); + + +/* Define Error Numbers and messages */ +#define SKERR_Q_E001 (SK_ERRBASE_QUEUE+0) +#define SKERR_Q_E001MSG "Event queue overflow" +#define SKERR_Q_E002 (SKERR_Q_E001+1) +#define SKERR_Q_E002MSG "Undefined event class" +#endif /* _SKQUEUE_H_ */ diff --git a/drivers/sk98lin/h/skrlmt.h b/drivers/sk98lin/h/skrlmt.h new file mode 100644 index 0000000..04d025b --- /dev/null +++ b/drivers/sk98lin/h/skrlmt.h @@ -0,0 +1,563 @@ +/****************************************************************************** + * + * Name: skrlmt.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.35 $ + * Date: $Date: 2003/01/31 14:12:41 $ + * Purpose: Header file for Redundant Link ManagemenT. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skrlmt.h,v $ + * Revision 1.35 2003/01/31 14:12:41 mkunz + * single port adapter runs now with two identical MAC addresses + * + * Revision 1.34 2002/09/23 15:13:41 rwahl + * Editorial changes. + * + * Revision 1.33 2001/07/03 12:16:48 mkunz + * New Flag ChgBcPrio (Change priority of last broadcast received) + * + * Revision 1.32 2001/02/14 14:06:31 rassmann + * Editorial changes. + * + * Revision 1.31 2001/02/05 14:25:26 rassmann + * Prepared RLMT for transparent operation. + * + * Revision 1.30 2001/01/22 13:41:39 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.29 2000/11/17 08:58:00 rassmann + * Moved CheckSwitch from SK_RLMT_PACKET_RECEIVED to SK_RLMT_TIM event. + * + * Revision 1.28 2000/11/09 12:24:34 rassmann + * Editorial changes. + * + * Revision 1.27 1999/11/22 13:59:56 cgoos + * Changed license header to GPL. + * + * Revision 1.26 1999/10/04 14:01:19 rassmann + * Corrected reaction to reception of BPDU frames (#10441). + * + * Revision 1.25 1999/07/20 12:53:39 rassmann + * Fixed documentation errors for lookahead macros. + * + * Revision 1.24 1999/05/28 11:15:56 rassmann + * Changed behaviour to reflect Design Spec v1.2. + * Controlling Link LED(s). + * Introduced RLMT Packet Version field in RLMT Packet. + * Newstyle lookahead macros (checking meta-information before looking at + * the packet). + * + * Revision 1.23 1999/01/28 12:50:42 rassmann + * Not using broadcast time stamps in CheckLinkState mode. + * + * Revision 1.22 1999/01/27 14:13:04 rassmann + * Monitoring broadcast traffic. + * Switching more reliably and not too early if switch is + * configured for spanning tree. + * + * Revision 1.21 1998/12/08 13:11:25 rassmann + * Stopping SegTimer at RlmtStop. + * + * Revision 1.20 1998/11/24 12:37:33 rassmann + * Implemented segmentation check. + * + * Revision 1.19 1998/11/17 13:43:06 rassmann + * Handling (logical) tx failure. + * Sending packet on logical address after PORT_SWITCH. + * + * Revision 1.18 1998/11/13 16:56:56 rassmann + * Added macro version of SkRlmtLookaheadPacket. + * + * Revision 1.17 1998/11/06 18:06:05 rassmann + * Corrected timing when RLMT checks fail. + * Clearing tx counter earlier in periodical checks. + * + * Revision 1.16 1998/11/03 13:53:50 rassmann + * RLMT should switch now (at least in mode 3). + * + * Revision 1.15 1998/10/22 11:39:52 rassmann + * Corrected signed/unsigned mismatches. + * Corrected receive list handling and address recognition. + * + * Revision 1.14 1998/10/15 15:16:36 rassmann + * Finished Spanning Tree checking. + * Checked with lint. + * + * Revision 1.13 1998/09/24 19:16:08 rassmann + * Code cleanup. + * Introduced Timer for PORT_DOWN due to no RX. + * + * Revision 1.12 1998/09/16 11:09:52 rassmann + * Syntax corrections. + * + * Revision 1.11 1998/09/15 11:28:50 rassmann + * Syntax corrections. + * + * Revision 1.10 1998/09/14 17:07:38 rassmann + * Added code for port checking via LAN. + * Changed Mbuf definition. + * + * Revision 1.9 1998/09/07 11:14:15 rassmann + * Syntax corrections. + * + * Revision 1.8 1998/09/07 09:06:08 rassmann + * Syntax corrections. + * + * Revision 1.7 1998/09/04 19:41:34 rassmann + * Syntax corrections. + * Started entering code for checking local links. + * + * Revision 1.6 1998/09/04 12:14:28 rassmann + * Interface cleanup. + * + * Revision 1.5 1998/09/02 16:55:29 rassmann + * Updated to reflect new DRV/HWAC/RLMT interface. + * + * Revision 1.4 1998/09/02 07:26:02 afischer + * typedef for SK_RLMT_PORT + * + * Revision 1.3 1998/08/27 14:29:03 rassmann + * Code cleanup. + * + * Revision 1.2 1998/08/27 14:26:25 rassmann + * Updated interface. + * + * Revision 1.1 1998/08/21 08:29:10 rassmann + * First public version. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This is the header file for Redundant Link ManagemenT. + * + * Include File Hierarchy: + * + * "skdrv1st.h" + * ... + * "sktypes.h" + * "skqueue.h" + * "skaddr.h" + * "skrlmt.h" + * ... + * "skdrv2nd.h" + * + ******************************************************************************/ + +#ifndef __INC_SKRLMT_H +#define __INC_SKRLMT_H + +#ifdef __cplusplus +#error C++ is not yet supported. +extern "C" { +#endif /* cplusplus */ + +/* defines ********************************************************************/ + +#define SK_RLMT_NET_DOWN_TEMP 1 /* NET_DOWN due to last port down. */ +#define SK_RLMT_NET_DOWN_FINAL 2 /* NET_DOWN due to RLMT_STOP. */ + +/* ----- Default queue sizes - must be multiples of 8 KB ----- */ + +/* Less than 8 KB free in RX queue => pause frames. */ +#define SK_RLMT_STANDBY_QRXSIZE 128 /* Size of rx standby queue in KB. */ +#define SK_RLMT_STANDBY_QXASIZE 32 /* Size of async standby queue in KB. */ +#define SK_RLMT_STANDBY_QXSSIZE 0 /* Size of sync standby queue in KB. */ + +#define SK_RLMT_MAX_TX_BUF_SIZE 60 /* Maximum RLMT transmit size. */ + +/* ----- PORT states ----- */ + +#define SK_RLMT_PS_INIT 0 /* Port state: Init. */ +#define SK_RLMT_PS_LINK_DOWN 1 /* Port state: Link down. */ +#define SK_RLMT_PS_DOWN 2 /* Port state: Port down. */ +#define SK_RLMT_PS_GOING_UP 3 /* Port state: Going up. */ +#define SK_RLMT_PS_UP 4 /* Port state: Up. */ + +/* ----- RLMT states ----- */ + +#define SK_RLMT_RS_INIT 0 /* RLMT state: Init. */ +#define SK_RLMT_RS_NET_DOWN 1 /* RLMT state: Net down. */ +#define SK_RLMT_RS_NET_UP 2 /* RLMT state: Net up. */ + +/* ----- PORT events ----- */ + +#define SK_RLMT_LINK_UP 1001 /* Link came up. */ +#define SK_RLMT_LINK_DOWN 1002 /* Link went down. */ +#define SK_RLMT_PORT_ADDR 1003 /* Port address changed. */ + +/* ----- RLMT events ----- */ + +#define SK_RLMT_START 2001 /* Start RLMT. */ +#define SK_RLMT_STOP 2002 /* Stop RLMT. */ +#define SK_RLMT_PACKET_RECEIVED 2003 /* Packet was received for RLMT. */ +#define SK_RLMT_STATS_CLEAR 2004 /* Clear statistics. */ +#define SK_RLMT_STATS_UPDATE 2005 /* Update statistics. */ +#define SK_RLMT_PREFPORT_CHANGE 2006 /* Change preferred port. */ +#define SK_RLMT_MODE_CHANGE 2007 /* New RlmtMode. */ +#define SK_RLMT_SET_NETS 2008 /* Number of Nets (1 or 2). */ + +/* ----- RLMT mode bits ----- */ + +/* + * CAUTION: These defines are private to RLMT. + * Please use the RLMT mode defines below. + */ + +#define SK_RLMT_CHECK_LINK 1 /* Check Link. */ +#define SK_RLMT_CHECK_LOC_LINK 2 /* Check other link on same adapter. */ +#define SK_RLMT_CHECK_SEG 4 /* Check segmentation. */ + +#ifndef RLMT_CHECK_REMOTE +#define SK_RLMT_CHECK_OTHERS SK_RLMT_CHECK_LOC_LINK +#else /* RLMT_CHECK_REMOTE */ +#define SK_RLMT_CHECK_REM_LINK 8 /* Check link(s) on other adapter(s). */ +#define SK_RLMT_MAX_REMOTE_PORTS_CHECKED 3 +#define SK_RLMT_CHECK_OTHERS \ + (SK_RLMT_CHECK_LOC_LINK | SK_RLMT_CHECK_REM_LINK) +#endif /* RLMT_CHECK_REMOTE */ + +#ifndef SK_RLMT_ENABLE_TRANSPARENT +#define SK_RLMT_TRANSPARENT 0 /* RLMT transparent - inactive. */ +#else /* SK_RLMT_ENABLE_TRANSPARENT */ +#define SK_RLMT_TRANSPARENT 128 /* RLMT transparent. */ +#endif /* SK_RLMT_ENABLE_TRANSPARENT */ + +/* ----- RLMT modes ----- */ + +/* Check Link State. */ +#define SK_RLMT_MODE_CLS (SK_RLMT_CHECK_LINK) + +/* Check Local Ports: check other links on the same adapter. */ +#define SK_RLMT_MODE_CLP (SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK) + +/* Check Local Ports and Segmentation Status. */ +#define SK_RLMT_MODE_CLPSS \ + (SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK | SK_RLMT_CHECK_SEG) + +#ifdef RLMT_CHECK_REMOTE +/* Check Local and Remote Ports: check links (local or remote). */ + Name of define TBD! +#define SK_RLMT_MODE_CRP \ + (SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK | SK_RLMT_CHECK_REM_LINK) + +/* Check Local and Remote Ports and Segmentation Status. */ + Name of define TBD! +#define SK_RLMT_MODE_CRPSS \ + (SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK | \ + SK_RLMT_CHECK_REM_LINK | SK_RLMT_CHECK_SEG) +#endif /* RLMT_CHECK_REMOTE */ + +/* ----- RLMT lookahead result bits ----- */ + +#define SK_RLMT_RX_RLMT 1 /* Give packet to RLMT. */ +#define SK_RLMT_RX_PROTOCOL 2 /* Give packet to protocol. */ + +/* Macros */ + +#if 0 +SK_AC *pAC /* adapter context */ +SK_U32 PortNum /* receiving port */ +unsigned PktLen /* received packet's length */ +SK_BOOL IsBc /* Flag: packet is broadcast */ +unsigned *pOffset /* offs. of bytes to present to SK_RLMT_LOOKAHEAD */ +unsigned *pNumBytes /* #Bytes to present to SK_RLMT_LOOKAHEAD */ +#endif /* 0 */ + +#define SK_RLMT_PRE_LOOKAHEAD(pAC,PortNum,PktLen,IsBc,pOffset,pNumBytes) { \ + SK_AC *_pAC; \ + SK_U32 _PortNum; \ + _pAC = (pAC); \ + _PortNum = (SK_U32)(PortNum); \ + /* _pAC->Rlmt.Port[_PortNum].PacketsRx++; */ \ + _pAC->Rlmt.Port[_PortNum].PacketsPerTimeSlot++; \ + if (_pAC->Rlmt.RlmtOff) { \ + *(pNumBytes) = 0; \ + } \ + else {\ + if ((_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_TRANSPARENT) != 0) { \ + *(pNumBytes) = 0; \ + } \ + else if (IsBc) { \ + if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode != SK_RLMT_MODE_CLS) { \ + *(pNumBytes) = 6; \ + *(pOffset) = 6; \ + } \ + else { \ + *(pNumBytes) = 0; \ + } \ + } \ + else { \ + if ((PktLen) > SK_RLMT_MAX_TX_BUF_SIZE) { \ + /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ + *(pNumBytes) = 0; \ + } \ + else { \ + *(pNumBytes) = 6; \ + *(pOffset) = 0; \ + } \ + } \ + } \ +} + +#if 0 +SK_AC *pAC /* adapter context */ +SK_U32 PortNum /* receiving port */ +SK_U8 *pLaPacket, /* received packet's data (points to pOffset) */ +SK_BOOL IsBc /* Flag: packet is broadcast */ +SK_BOOL IsMc /* Flag: packet is multicast */ +unsigned *pForRlmt /* Result: bits SK_RLMT_RX_RLMT, SK_RLMT_RX_PROTOCOL */ +SK_RLMT_LOOKAHEAD() expects *pNumBytes from +packet offset *pOffset (s.a.) at *pLaPacket. + +If you use SK_RLMT_LOOKAHEAD in a path where you already know if the packet is +BC, MC, or UC, you should use constants for IsBc and IsMc, so that your compiler +can trash unneeded parts of the if construction. +#endif /* 0 */ + +#define SK_RLMT_LOOKAHEAD(pAC,PortNum,pLaPacket,IsBc,IsMc,pForRlmt) { \ + SK_AC *_pAC; \ + SK_U32 _PortNum; \ + SK_U8 *_pLaPacket; \ + _pAC = (pAC); \ + _PortNum = (SK_U32)(PortNum); \ + _pLaPacket = (SK_U8 *)(pLaPacket); \ + if (IsBc) {\ + if (!SK_ADDR_EQUAL(_pLaPacket, _pAC->Addr.Net[_pAC->Rlmt.Port[ \ + _PortNum].Net->NetNumber].CurrentMacAddress.a)) { \ + _pAC->Rlmt.Port[_PortNum].BcTimeStamp = SkOsGetTime(_pAC); \ + _pAC->Rlmt.CheckSwitch = SK_TRUE; \ + } \ + /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ + *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \ + } \ + else if (IsMc) { \ + if (SK_ADDR_EQUAL(_pLaPacket, BridgeMcAddr.a)) { \ + _pAC->Rlmt.Port[_PortNum].BpduPacketsPerTimeSlot++; \ + if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_CHECK_SEG) { \ + *(pForRlmt) = SK_RLMT_RX_RLMT | SK_RLMT_RX_PROTOCOL; \ + } \ + else { \ + *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \ + } \ + } \ + else if (SK_ADDR_EQUAL(_pLaPacket, SkRlmtMcAddr.a)) { \ + *(pForRlmt) = SK_RLMT_RX_RLMT; \ + } \ + else { \ + /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ + *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \ + } \ + } \ + else { \ + if (SK_ADDR_EQUAL( \ + _pLaPacket, \ + _pAC->Addr.Port[_PortNum].CurrentMacAddress.a)) { \ + *(pForRlmt) = SK_RLMT_RX_RLMT; \ + } \ + else { \ + /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ + *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \ + } \ + } \ +} + +#ifdef SK_RLMT_FAST_LOOKAHEAD +Error: SK_RLMT_FAST_LOOKAHEAD no longer used. Use new macros for lookahead. +#endif /* SK_RLMT_FAST_LOOKAHEAD */ +#ifdef SK_RLMT_SLOW_LOOKAHEAD +Error: SK_RLMT_SLOW_LOOKAHEAD no longer used. Use new macros for lookahead. +#endif /* SK_RLMT_SLOW_LOOKAHEAD */ + +/* typedefs *******************************************************************/ + +#ifdef SK_RLMT_MBUF_PRIVATE +typedef struct s_RlmtMbuf { + some content +} SK_RLMT_MBUF; +#endif /* SK_RLMT_MBUF_PRIVATE */ + + +#ifdef SK_LA_INFO +typedef struct s_Rlmt_PacketInfo { + unsigned PacketLength; /* Length of packet. */ + unsigned PacketType; /* Directed/Multicast/Broadcast. */ +} SK_RLMT_PINFO; +#endif /* SK_LA_INFO */ + + +typedef struct s_RootId { + SK_U8 Id[8]; /* Root Bridge Id. */ +} SK_RLMT_ROOT_ID; + + +typedef struct s_port { + SK_MAC_ADDR CheckAddr; + SK_BOOL SuspectTx; +} SK_PORT_CHECK; + + +typedef struct s_RlmtNet SK_RLMT_NET; + + +typedef struct s_RlmtPort { + +/* ----- Public part (read-only) ----- */ + + SK_U8 PortState; /* Current state of this port. */ + + /* For PNMI */ + SK_BOOL LinkDown; + SK_BOOL PortDown; + SK_U8 Align01; + + SK_U32 PortNumber; /* Number of port on adapter. */ + SK_RLMT_NET * Net; /* Net port belongs to. */ + + SK_U64 TxHelloCts; + SK_U64 RxHelloCts; + SK_U64 TxSpHelloReqCts; + SK_U64 RxSpHelloCts; + +/* ----- Private part ----- */ + +/* SK_U64 PacketsRx; */ /* Total packets received. */ + SK_U32 PacketsPerTimeSlot; /* Packets rxed between TOs. */ +/* SK_U32 DataPacketsPerTimeSlot; */ /* Data packets ... */ + SK_U32 BpduPacketsPerTimeSlot; /* BPDU packets rxed in TS. */ + SK_U64 BcTimeStamp; /* Time of last BC receive. */ + SK_U64 GuTimeStamp; /* Time of entering GOING_UP. */ + + SK_TIMER UpTimer; /* Timer struct Link/Port up. */ + SK_TIMER DownRxTimer; /* Timer struct down rx. */ + SK_TIMER DownTxTimer; /* Timer struct down tx. */ + + SK_U32 CheckingState; /* Checking State. */ + + SK_ADDR_PORT * AddrPort; + + SK_U8 Random[4]; /* Random value. */ + unsigned PortsChecked; /* #ports checked. */ + unsigned PortsSuspect; /* #ports checked that are s. */ + SK_PORT_CHECK PortCheck[1]; +/* SK_PORT_CHECK PortCheck[SK_MAX_MACS - 1]; */ + + SK_BOOL PortStarted; /* Port is started. */ + SK_BOOL PortNoRx; /* NoRx for >= 1 time slot. */ + SK_BOOL RootIdSet; + SK_RLMT_ROOT_ID Root; /* Root Bridge Id. */ +} SK_RLMT_PORT; + + +struct s_RlmtNet { + +/* ----- Public part (read-only) ----- */ + + SK_U32 NetNumber; /* Number of net. */ + + SK_RLMT_PORT * Port[SK_MAX_MACS]; /* Ports that belong to this net. */ + SK_U32 NumPorts; /* Number of ports. */ + SK_U32 PrefPort; /* Preferred port. */ + + /* For PNMI */ + + SK_U32 ChgBcPrio; /* Change Priority of last broadcast received */ + SK_U32 RlmtMode; /* Check ... */ + SK_U32 ActivePort; /* Active port. */ + SK_U32 Preference; /* 0xFFFFFFFF: Automatic. */ + + SK_U8 RlmtState; /* Current RLMT state. */ + +/* ----- Private part ----- */ + SK_BOOL RootIdSet; + SK_U16 Align01; + + int LinksUp; /* #Links up. */ + int PortsUp; /* #Ports up. */ + SK_U32 TimeoutValue; /* RLMT timeout value. */ + + SK_U32 CheckingState; /* Checking State. */ + SK_RLMT_ROOT_ID Root; /* Root Bridge Id. */ + + SK_TIMER LocTimer; /* Timer struct. */ + SK_TIMER SegTimer; /* Timer struct. */ +}; + + +typedef struct s_Rlmt { + +/* ----- Public part (read-only) ----- */ + + SK_U32 NumNets; /* Number of nets. */ + SK_U32 NetsStarted; /* Number of nets started. */ + SK_RLMT_NET Net[SK_MAX_NETS]; /* Array of available nets. */ + SK_RLMT_PORT Port[SK_MAX_MACS]; /* Array of available ports. */ + +/* ----- Private part ----- */ + SK_BOOL CheckSwitch; + SK_BOOL RlmtOff; /* set to zero if the Mac addresses + are equal or the second one + is zero */ + SK_U16 Align01; + +} SK_RLMT; + + +extern SK_MAC_ADDR BridgeMcAddr; +extern SK_MAC_ADDR SkRlmtMcAddr; + +/* function prototypes ********************************************************/ + + +#ifndef SK_KR_PROTO + +/* Functions provided by SkRlmt */ + +/* ANSI/C++ compliant function prototypes */ + +extern void SkRlmtInit( + SK_AC *pAC, + SK_IOC IoC, + int Level); + +extern int SkRlmtEvent( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 Event, + SK_EVPARA Para); + +#else /* defined(SK_KR_PROTO) */ + +/* Non-ANSI/C++ compliant function prototypes */ + +#error KR-style function prototypes are not yet provided. + +#endif /* defined(SK_KR_PROTO)) */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKRLMT_H */ diff --git a/drivers/sk98lin/h/sktimer.h b/drivers/sk98lin/h/sktimer.h new file mode 100644 index 0000000..36f8ccb --- /dev/null +++ b/drivers/sk98lin/h/sktimer.h @@ -0,0 +1,99 @@ +/****************************************************************************** + * + * Name: sktimer.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.9 $ + * Date: $Date: 1999/11/22 14:00:29 $ + * Purpose: Defines for the timer functions + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: sktimer.h,v $ + * Revision 1.9 1999/11/22 14:00:29 cgoos + * Changed license header to GPL. + * + * Revision 1.8 1998/09/08 08:48:02 gklug + * add: init level handling + * + * Revision 1.7 1998/08/20 12:31:29 gklug + * fix: SK_TIMCTRL needs to be defined + * + * Revision 1.6 1998/08/19 09:51:00 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.5 1998/08/17 13:43:21 gklug + * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR + * + * Revision 1.4 1998/08/14 07:09:31 gklug + * fix: chg pAc -> pAC + * + * Revision 1.3 1998/08/07 12:54:24 gklug + * fix: first compiled version + * + * Revision 1.2 1998/08/07 09:35:29 gklug + * add: Timer control struct for Adapters context + * add: function prototypes + * + * Revision 1.1 1998/08/05 11:27:01 gklug + * First version: adapted from SMT + * + * + ******************************************************************************/ + +/* + * SKTIMER.H contains all defines and types for the timer functions + */ + +#ifndef _SKTIMER_H_ +#define _SKTIMER_H_ + +#include "h/skqueue.h" + +/* + * SK timer + * - needed wherever a timer is used. Put this in your data structure + * wherever you want. + */ +typedef struct s_Timer SK_TIMER; + +struct s_Timer { + SK_TIMER *TmNext ; /* linked list */ + SK_U32 TmClass ; /* Timer Event class */ + SK_U32 TmEvent ; /* Timer Event value */ + SK_EVPARA TmPara ; /* Timer Event parameter */ + SK_U32 TmDelta ; /* delta time */ + int TmActive ; /* flag : active/inactive */ +} ; + +/* + * Timer control struct. + * - use in Adapters context name pAC->Tim + */ +typedef struct s_TimCtrl { + SK_TIMER *StQueue ; /* Head of Timer queue */ +} SK_TIMCTRL ; + +extern void SkTimerInit(SK_AC *pAC,SK_IOC Ioc, int Level); +extern void SkTimerStop(SK_AC *pAC,SK_IOC Ioc,SK_TIMER *pTimer); +extern void SkTimerStart(SK_AC *pAC,SK_IOC Ioc,SK_TIMER *pTimer, + SK_U32 Time,SK_U32 Class,SK_U32 Event,SK_EVPARA Para); +extern void SkTimerDone(SK_AC *pAC,SK_IOC Ioc); +#endif /* _SKTIMER_H_ */ diff --git a/drivers/sk98lin/h/sktypes.h b/drivers/sk98lin/h/sktypes.h new file mode 100644 index 0000000..e657016 --- /dev/null +++ b/drivers/sk98lin/h/sktypes.h @@ -0,0 +1,87 @@ +/****************************************************************************** + * + * Name: sktypes.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.3 $ + * Date: $Date: 2003/02/25 14:16:40 $ + * Purpose: Define data types for Linux + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + + /***************************************************************************** + * + * History: + * + * $Log: sktypes.h,v $ + * Revision 1.3 2003/02/25 14:16:40 mlindner + * Fix: Copyright statement + * + * Revision 1.2 1999/11/22 14:01:58 cgoos + * Changed license header to GPL. + * Now using Linux' fixed size types instead of standard types. + * + * Revision 1.1 1999/02/16 07:41:40 cgoos + * First version. + * + * + * + *****************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * In this file, all data types that are needed by the common modules + * are mapped to Linux data types. + * + * + * Include File Hierarchy: + * + * + ******************************************************************************/ + +#ifndef __INC_SKTYPES_H +#define __INC_SKTYPES_H + + +/* defines *******************************************************************/ + +/* + * Data types with a specific size. 'I' = signed, 'U' = unsigned. + */ +#define SK_I8 s8 +#define SK_U8 u8 +#define SK_I16 s16 +#define SK_U16 u16 +#define SK_I32 s32 +#define SK_U32 u32 +#define SK_I64 s64 +#define SK_U64 u64 + +#define SK_UPTR ulong /* casting pointer <-> integral */ + +/* +* Boolean type. +*/ +#define SK_BOOL SK_U8 +#define SK_FALSE 0 +#define SK_TRUE (!SK_FALSE) + +/* typedefs *******************************************************************/ + +/* function prototypes ********************************************************/ + +#endif /* __INC_SKTYPES_H */ diff --git a/drivers/sk98lin/h/skversion.h b/drivers/sk98lin/h/skversion.h new file mode 100644 index 0000000..ef46685 --- /dev/null +++ b/drivers/sk98lin/h/skversion.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Name: version.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.4 $ + * Date: $Date: 2003/02/25 14:16:40 $ + * Purpose: SK specific Error log support + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skversion.h,v $ + * Revision 1.4 2003/02/25 14:16:40 mlindner + * Fix: Copyright statement + * + * Revision 1.3 2003/02/25 13:30:18 mlindner + * Add: Support for various vendors + * + * Revision 1.1.2.1 2001/09/05 13:38:30 mlindner + * Removed FILE description + * + * Revision 1.1 2001/03/06 09:25:00 mlindner + * first version + * + * + * + ******************************************************************************/ + + +static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH."; +static const char SysKonnectBuildNumber[] = + "@(#)SK-BUILD: 6.05 PL: 01"; + +#define BOOT_STRING "sk98lin: Network Device Driver v6.05\n" \ + "(C)Copyright 1999-2003 Marvell(R)." + +#define VER_STRING "6.05" diff --git a/drivers/sk98lin/h/skvpd.h b/drivers/sk98lin/h/skvpd.h new file mode 100644 index 0000000..1be34c5 --- /dev/null +++ b/drivers/sk98lin/h/skvpd.h @@ -0,0 +1,335 @@ +/****************************************************************************** + * + * Name: skvpd.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.15 $ + * Date: $Date: 2003/01/13 10:39:38 $ + * Purpose: Defines and Macros for VPD handling + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skvpd.h,v $ + * Revision 1.15 2003/01/13 10:39:38 rschmidt + * Replaced define for PCI device Id for YUKON with GENESIS + * Editorial changes + * + * Revision 1.14 2002/11/14 15:18:10 gheinig + * Added const specifier to key and buf parameters for VpdPara,VpdRead + * and VpdWrite. This is necessary for the Diag 7 GUI API + * + * Revision 1.13 2002/10/14 15:58:18 rschmidt + * Added entry in rom_size struct s_vpd + * Editorial changes + * + * Revision 1.12 2002/09/09 14:43:51 mkarl + * added PCI Id of Yukon for reading VPD in diag before the adapter has + * been initialized + * editorial changes + * + * Revision 1.11 2002/07/26 13:19:16 mkarl + * added support for Yukon + * added vpd_size to VPD struct + * + * Revision 1.10 2000/08/10 11:29:07 rassmann + * Editorial changes. + * Preserving 32-bit alignment in structs for the adapter context. + * Removed unused function VpdWriteDword() (#if 0). + * Made VpdReadKeyword() available for SKDIAG only. + * + * Revision 1.9 1999/11/22 14:02:27 cgoos + * Changed license header to GPL. + * + * Revision 1.8 1999/03/11 14:26:40 malthoff + * Replace __STDC__ with SK_KR_PROTO. + * + * Revision 1.7 1998/10/28 07:27:17 gklug + * rmv: SWAP macros + * add: VPD_IN/OUT8 macros + * chg: interface definition + * + * Revision 1.6 1998/10/22 10:03:44 gklug + * fix: use SK_OUT16 instead of SK_OUTW + * + * Revision 1.5 1998/10/14 07:05:31 cgoos + * Changed constants in SK_SWAP_32 to UL. + * + * Revision 1.4 1998/08/19 08:14:09 gklug + * fix: remove struct keyword as much as possible from the C-code (see CCC) + * + * Revision 1.3 1998/08/18 08:18:56 malthoff + * Modify VPD in and out macros for SK_DIAG + * + * Revision 1.2 1998/07/03 14:49:08 malthoff + * Add VPD_INxx() and VPD_OUTxx() macros for the Diagnostics tool. + * + * Revision 1.1 1998/06/19 14:08:03 malthoff + * Created. + * + * + ******************************************************************************/ + +/* + * skvpd.h contains Diagnostic specific defines for VPD handling + */ + +#ifndef __INC_SKVPD_H_ +#define __INC_SKVPD_H_ + +/* + * Define Resource Type Identifiers and VPD keywords + */ +#define RES_ID 0x82 /* Resource Type ID String (Product Name) */ +#define RES_VPD_R 0x90 /* start of VPD read only area */ +#define RES_VPD_W 0x91 /* start of VPD read/write area */ +#define RES_END 0x78 /* Resource Type End Tag */ + +#ifndef VPD_NAME +#define VPD_NAME "Name" /* Product Name, VPD name of RES_ID */ +#endif /* VPD_NAME */ +#define VPD_PN "PN" /* Adapter Part Number */ +#define VPD_EC "EC" /* Adapter Engineering Level */ +#define VPD_MN "MN" /* Manufacture ID */ +#define VPD_SN "SN" /* Serial Number */ +#define VPD_CP "CP" /* Extended Capability */ +#define VPD_RV "RV" /* Checksum and Reserved */ +#define VPD_YA "YA" /* Asset Tag Identifier */ +#define VPD_VL "VL" /* First Error Log Message (SK specific) */ +#define VPD_VF "VF" /* Second Error Log Message (SK specific) */ +#define VPD_RW "RW" /* Remaining Read / Write Area */ + +/* 'type' values for vpd_setup_para() */ +#define VPD_RO_KEY 1 /* RO keys are "PN", "EC", "MN", "SN", "RV" */ +#define VPD_RW_KEY 2 /* RW keys are "Yx", "Vx", and "RW" */ + +/* 'op' values for vpd_setup_para() */ +#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */ +#define OWR_KEY 2 /* overwrite key if already exists */ + +/* + * Define READ and WRITE Constants. + */ + +#define VPD_DEV_ID_GENESIS 0x4300 + +#define VPD_SIZE_YUKON 256 +#define VPD_SIZE_GENESIS 512 +#define VPD_SIZE 512 +#define VPD_READ 0x0000 +#define VPD_WRITE 0x8000 + +#define VPD_STOP(pAC,IoC) VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE) + +#define VPD_GET_RES_LEN(p) ((unsigned int) \ + (* (SK_U8 *)&(p)[1]) |\ + ((* (SK_U8 *)&(p)[2]) << 8)) +#define VPD_GET_VPD_LEN(p) ((unsigned int)(* (SK_U8 *)&(p)[2])) +#define VPD_GET_VAL(p) ((char *)&(p)[3]) + +#define VPD_MAX_LEN 50 + +/* VPD status */ + /* bit 7..1 reserved */ +#define VPD_VALID (1<<0) /* VPD data buffer, vpd_free_ro, */ + /* and vpd_free_rw valid */ + +/* + * VPD structs + */ +typedef struct s_vpd_status { + unsigned short Align01; /* Alignment */ + unsigned short vpd_status; /* VPD status, description see above */ + int vpd_free_ro; /* unused bytes in read only area */ + int vpd_free_rw; /* bytes available in read/write area */ +} SK_VPD_STATUS; + +typedef struct s_vpd { + SK_VPD_STATUS v; /* VPD status structure */ + char vpd_buf[VPD_SIZE]; /* VPD buffer */ + int rom_size; /* VPD ROM Size from PCI_OUR_REG_2 */ + int vpd_size; /* saved VPD-size */ +} SK_VPD; + +typedef struct s_vpd_para { + unsigned int p_len; /* parameter length */ + char *p_val; /* points to the value */ +} SK_VPD_PARA; + +/* + * structure of Large Resource Type Identifiers + */ + +/* was removed because of alignment problems */ + +/* + * structure of VPD keywords + */ +typedef struct s_vpd_key { + char p_key[2]; /* 2 bytes ID string */ + unsigned char p_len; /* 1 byte length */ + char p_val; /* start of the value string */ +} SK_VPD_KEY; + + +/* + * System specific VPD macros + */ +#ifndef SKDIAG +#ifndef VPD_DO_IO +#define VPD_OUT8(pAC,IoC,Addr,Val) (void)SkPciWriteCfgByte(pAC,Addr,Val) +#define VPD_OUT16(pAC,IoC,Addr,Val) (void)SkPciWriteCfgWord(pAC,Addr,Val) +#define VPD_OUT32(pAC,IoC,Addr,Val) (void)SkPciWriteCfgDWord(pAC,Addr,Val) +#define VPD_IN8(pAC,IoC,Addr,pVal) (void)SkPciReadCfgByte(pAC,Addr,pVal) +#define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal) +#define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal) +#else /* VPD_DO_IO */ +#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val) +#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val) +#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(Addr),Val) +#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal) +#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal) +#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal) +#endif /* VPD_DO_IO */ +#else /* SKDIAG */ +#define VPD_OUT8(pAC,Ioc,Addr,Val) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciWriteCfgByte(pAC,Addr,Val); \ + else \ + SK_OUT8(pAC,PCI_C(Addr),Val); \ + } +#define VPD_OUT16(pAC,Ioc,Addr,Val) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciWriteCfgWord(pAC,Addr,Val); \ + else \ + SK_OUT16(pAC,PCI_C(Addr),Val); \ + } +#define VPD_OUT32(pAC,Ioc,Addr,Val) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciWriteCfgDWord(pAC,Addr,Val); \ + else \ + SK_OUT32(pAC,PCI_C(Addr),Val); \ + } +#define VPD_IN8(pAC,Ioc,Addr,pVal) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciReadCfgByte(pAC,Addr,pVal); \ + else \ + SK_IN8(pAC,PCI_C(Addr),pVal); \ + } +#define VPD_IN16(pAC,Ioc,Addr,pVal) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciReadCfgWord(pAC,Addr,pVal); \ + else \ + SK_IN16(pAC,PCI_C(Addr),pVal); \ + } +#define VPD_IN32(pAC,Ioc,Addr,pVal) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciReadCfgDWord(pAC,Addr,pVal); \ + else \ + SK_IN32(pAC,PCI_C(Addr),pVal); \ + } +#endif /* nSKDIAG */ + +/* function prototypes ********************************************************/ + +#ifndef SK_KR_PROTO +#ifdef SKDIAG +extern SK_U32 VpdReadDWord( + SK_AC *pAC, + SK_IOC IoC, + int addr); +#endif /* SKDIAG */ + +extern int VpdSetupPara( + SK_AC *pAC, + const char *key, + const char *buf, + int len, + int type, + int op); + +extern SK_VPD_STATUS *VpdStat( + SK_AC *pAC, + SK_IOC IoC); + +extern int VpdKeys( + SK_AC *pAC, + SK_IOC IoC, + char *buf, + int *len, + int *elements); + +extern int VpdRead( + SK_AC *pAC, + SK_IOC IoC, + const char *key, + char *buf, + int *len); + +extern SK_BOOL VpdMayWrite( + char *key); + +extern int VpdWrite( + SK_AC *pAC, + SK_IOC IoC, + const char *key, + const char *buf); + +extern int VpdDelete( + SK_AC *pAC, + SK_IOC IoC, + char *key); + +extern int VpdUpdate( + SK_AC *pAC, + SK_IOC IoC); + +extern void VpdErrLog( + SK_AC *pAC, + SK_IOC IoC, + char *msg); + +#ifdef SKDIAG +extern int VpdReadBlock( + SK_AC *pAC, + SK_IOC IoC, + char *buf, + int addr, + int len); + +extern int VpdWriteBlock( + SK_AC *pAC, + SK_IOC IoC, + char *buf, + int addr, + int len); +#endif /* SKDIAG */ +#else /* SK_KR_PROTO */ +extern SK_U32 VpdReadDWord(); +extern int VpdSetupPara(); +extern SK_VPD_STATUS *VpdStat(); +extern int VpdKeys(); +extern int VpdRead(); +extern SK_BOOL VpdMayWrite(); +extern int VpdWrite(); +extern int VpdDelete(); +extern int VpdUpdate(); +extern void VpdErrLog(); +#endif /* SK_KR_PROTO */ + +#endif /* __INC_SKVPD_H_ */ diff --git a/drivers/sk98lin/h/xmac_ii.h b/drivers/sk98lin/h/xmac_ii.h new file mode 100644 index 0000000..2ef903a --- /dev/null +++ b/drivers/sk98lin/h/xmac_ii.h @@ -0,0 +1,1738 @@ +/****************************************************************************** + * + * Name: xmac_ii.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.46 $ + * Date: $Date: 2003/01/28 09:47:45 $ + * Purpose: Defines and Macros for Gigabit Ethernet Controller + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: xmac_ii.h,v $ + * Revision 1.46 2003/01/28 09:47:45 rschmidt + * Added defines for copper MDI/MDIX configuration + * Added defines for LED Control Register + * Editorial changes + * + * Revision 1.45 2002/12/10 14:35:13 rschmidt + * Corrected defines for Extended PHY Specific Control + * Added defines for Ext. PHY Specific Ctrl 2 Reg. (Fiber specific) + * + * Revision 1.44 2002/12/09 14:58:41 rschmidt + * Added defines for Ext. PHY Specific Ctrl Reg. (downshift feature) + * Added 'GMR_FS_UN_SIZE'-Bit to Rx GMAC FIFO Flush Mask + * + * Revision 1.43 2002/12/05 10:14:45 rschmidt + * Added define for GMAC's Half Duplex Burst Mode + * Added define for Rx GMAC FIFO Flush Mask (default) + * + * Revision 1.42 2002/11/12 16:48:19 rschmidt + * Added defines for Cable Diagnostic Register (GPHY) + * Editorial changes + * + * Revision 1.41 2002/10/21 11:20:22 rschmidt + * Added bit GMR_FS_GOOD_FC to GMR_FS_ANY_ERR + * Editorial changes + * + * Revision 1.40 2002/10/14 14:54:14 rschmidt + * Added defines for GPHY Specific Status and GPHY Interrupt Status + * Added bits PHY_M_IS_AN_ERROR and PHY_M_IS_FIFO_ERROR to PHY_M_DEF_MSK + * Editorial changes + * + * Revision 1.39 2002/10/10 15:53:44 mkarl + * added some bit definitions for link speed status and LED's + * + * Revision 1.38 2002/08/21 16:23:46 rschmidt + * Added defines for PHY Specific Ctrl Reg + * Editorial changes + * + * Revision 1.37 2002/08/16 14:50:33 rschmidt + * Added defines for Auto-Neg. Advertisement YUKON Fiber (88E1011S only) + * Changed define PHY_M_DEF_MSK for GPHY IRQ Mask + * Editorial changes + * + * Revision 1.36 2002/08/12 13:21:10 rschmidt + * Added defines for different Broadcom PHY Ids + * + * Revision 1.35 2002/08/08 15:58:01 rschmidt + * Added defines for Manual LED Override register (YUKON) + * Editorial changes + * + * Revision 1.34 2002/07/31 17:23:36 rwahl + * Added define GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR). + * + * Revision 1.33 2002/07/23 16:03:37 rschmidt + * Added defines for GPHY registers + * Editorial changes + * + * Revision 1.32 2002/07/15 18:14:37 rwahl + * Added GMAC MIB counters definitions. + * Editorial changes. + * + * Revision 1.31 2002/07/15 15:42:50 rschmidt + * Removed defines from PHY specific reg. which are + * common to all PHYs + * Added defines for GMAC MIB Counters + * Editorial changes + * + * Revision 1.30 2002/06/05 08:22:12 rschmidt + * Changed defines for GMAC Rx Control Register and Rx Status + * Editorial changes + * + * Revision 1.29 2002/04/25 11:43:56 rschmidt + * Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res. + * Added new registers and defines for YUKON (GMAC, GPHY) + * Added Receive Frame Status Encoding for YUKON + * Editorial changes + * + * Revision 1.28 2000/11/09 12:32:49 rassmann + * Renamed variables. + * + * Revision 1.27 2000/05/17 11:00:46 malthoff + * Add bit for enable/disable power management in BCOM chip. + * + * Revision 1.26 1999/11/22 14:03:00 cgoos + * Changed license header to GPL. + * + * Revision 1.25 1999/08/12 19:19:38 malthoff + * Add PHY_B_AC_TX_TST bit according to BCOM A1 errata sheet. + * + * Revision 1.24 1999/07/30 11:27:21 cgoos + * Fixed a missing end-of-comment. + * + * Revision 1.23 1999/07/30 07:03:31 malthoff + * Cut some long comments. + * Correct the XMAC PHY ID definitions. + * + * Revision 1.22 1999/05/19 07:33:18 cgoos + * Changes for 1000Base-T. + * + * Revision 1.21 1999/03/25 07:46:11 malthoff + * Add XM_HW_CFG, XM_TS_READ, and XM_TS_LOAD registers. + * + * Revision 1.20 1999/03/12 13:36:09 malthoff + * Remove __STDC__. + * + * Revision 1.19 1998/12/10 12:22:54 gklug + * fix: RX_PAGE must be in interrupt mask + * + * Revision 1.18 1998/12/10 10:36:36 gklug + * fix: swap of pause bits + * + * Revision 1.17 1998/11/18 13:21:45 gklug + * fix: Default interrupt mask + * + * Revision 1.16 1998/10/29 15:53:21 gklug + * fix: Default mask uses ASS (GP0) signal + * + * Revision 1.15 1998/10/28 13:52:52 malthoff + * Add new bits in RX_CMD register. + * + * Revision 1.14 1998/10/19 15:34:53 gklug + * fix: typos + * + * Revision 1.13 1998/10/14 07:19:03 malthoff + * bug fix: Every define which describes bit 31 + * must be declared as unsigned long 'UL'. + * fix bit definitions of PHY_AN_RFB and PHY_AN_PAUSE. + * Remove ANP defines. Rework the RFB defines. + * + * Revision 1.12 1998/10/14 06:22:44 cgoos + * Changed shifted constant to ULONG. + * + * Revision 1.11 1998/10/14 05:43:26 gklug + * add: shift pause coding + * fix: PAUSE bits definition + * + * Revision 1.10 1998/10/13 09:19:21 malthoff + * Again change XMR_FS_ANY_ERR because of new info from XaQti. + * + * Revision 1.9 1998/10/09 07:58:30 malthoff + * Add XMR_FS_FCS_ERR to XMR_FS_ANY_ERR. + * + * Revision 1.8 1998/10/09 07:18:17 malthoff + * bug fix of a bug fix: XM_PAUSE_MODE and XM_DEF_MODE + * are not inverted! Bug XM_DEF_MSK is inverted. + * + * Revision 1.7 1998/10/05 08:04:32 malthoff + * bug fix: XM_PAUSE_MODE and XM_DEF_MODE + * must be inverted declarations. + * + * Revision 1.6 1998/09/28 13:38:18 malthoff + * Add default modes and masks XM_DEF_MSK, + * XM_PAUSE_MODE and XM_DEF_MODE + * + * Revision 1.5 1998/09/16 14:42:04 malthoff + * Bug Fix: XM_GP_PORT is a 32 bit (not a 16 bit) register. + * + * Revision 1.4 1998/08/20 14:59:47 malthoff + * Rework this file after reading the XaQti data sheet + * "Differences between Rev. B2 & Rev. C XMAC II". + * This file is now 100% XMAC II Rev. C complained. + * + * Revision 1.3 1998/06/29 12:18:23 malthoff + * Correct XMR_FS_ANY_ERR definition. + * + * Revision 1.2 1998/06/29 12:10:56 malthoff + * Add define XMR_FS_ANY_ERR. + * + * Revision 1.1 1998/06/19 13:37:17 malthoff + * created. + * + * + ******************************************************************************/ + +#ifndef __INC_XMAC_H +#define __INC_XMAC_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines ********************************************************************/ + +/* + * XMAC II registers + * + * The XMAC registers are 16 or 32 bits wide. + * The XMACs host processor interface is set to 16 bit mode, + * therefore ALL registers will be addressed with 16 bit accesses. + * + * The following macros are provided to access the XMAC registers + * XM_IN16(), XM_OUT16, XM_IN32(), XM_OUT32(), XM_INADR(), XM_OUTADR(), + * XM_INHASH(), and XM_OUTHASH(). + * The macros are defined in SkGeHw.h. + * + * Note: NA reg = Network Address e.g DA, SA etc. + * + */ +#define XM_MMU_CMD 0x0000 /* 16 bit r/w MMU Command Register */ + /* 0x0004: reserved */ +#define XM_POFF 0x0008 /* 32 bit r/w Packet Offset Register */ +#define XM_BURST 0x000c /* 32 bit r/w Burst Register for half duplex*/ +#define XM_1L_VLAN_TAG 0x0010 /* 16 bit r/w One Level VLAN Tag ID */ +#define XM_2L_VLAN_TAG 0x0014 /* 16 bit r/w Two Level VLAN Tag ID */ + /* 0x0018 - 0x001e: reserved */ +#define XM_TX_CMD 0x0020 /* 16 bit r/w Transmit Command Register */ +#define XM_TX_RT_LIM 0x0024 /* 16 bit r/w Transmit Retry Limit Register */ +#define XM_TX_STIME 0x0028 /* 16 bit r/w Transmit Slottime Register */ +#define XM_TX_IPG 0x002c /* 16 bit r/w Transmit Inter Packet Gap */ +#define XM_RX_CMD 0x0030 /* 16 bit r/w Receive Command Register */ +#define XM_PHY_ADDR 0x0034 /* 16 bit r/w PHY Address Register */ +#define XM_PHY_DATA 0x0038 /* 16 bit r/w PHY Data Register */ + /* 0x003c: reserved */ +#define XM_GP_PORT 0x0040 /* 32 bit r/w General Purpose Port Register */ +#define XM_IMSK 0x0044 /* 16 bit r/w Interrupt Mask Register */ +#define XM_ISRC 0x0048 /* 16 bit r/o Interrupt Status Register */ +#define XM_HW_CFG 0x004c /* 16 bit r/w Hardware Config Register */ + /* 0x0050 - 0x005e: reserved */ +#define XM_TX_LO_WM 0x0060 /* 16 bit r/w Tx FIFO Low Water Mark */ +#define XM_TX_HI_WM 0x0062 /* 16 bit r/w Tx FIFO High Water Mark */ +#define XM_TX_THR 0x0064 /* 16 bit r/w Tx Request Threshold */ +#define XM_HT_THR 0x0066 /* 16 bit r/w Host Request Threshold */ +#define XM_PAUSE_DA 0x0068 /* NA reg r/w Pause Destination Address */ + /* 0x006e: reserved */ +#define XM_CTL_PARA 0x0070 /* 32 bit r/w Control Parameter Register */ +#define XM_MAC_OPCODE 0x0074 /* 16 bit r/w Opcode for MAC control frames */ +#define XM_MAC_PTIME 0x0076 /* 16 bit r/w Pause time for MAC ctrl frames*/ +#define XM_TX_STAT 0x0078 /* 32 bit r/o Tx Status LIFO Register */ + + /* 0x0080 - 0x00fc: 16 NA reg r/w Exact Match Address Registers */ + /* use the XM_EXM() macro to address */ +#define XM_EXM_START 0x0080 /* r/w Start Address of the EXM Regs */ + + /* + * XM_EXM(Reg) + * + * returns the XMAC address offset of specified Exact Match Addr Reg + * + * para: Reg EXM register to addr (0 .. 15) + * + * usage: XM_INADDR(IoC, MAC_1, XM_EXM(i), &val[i]); + */ +#define XM_EXM(Reg) (XM_EXM_START + ((Reg) << 3)) + +#define XM_SRC_CHK 0x0100 /* NA reg r/w Source Check Address Register */ +#define XM_SA 0x0108 /* NA reg r/w Station Address Register */ +#define XM_HSM 0x0110 /* 64 bit r/w Hash Match Address Registers */ +#define XM_RX_LO_WM 0x0118 /* 16 bit r/w Receive Low Water Mark */ +#define XM_RX_HI_WM 0x011a /* 16 bit r/w Receive High Water Mark */ +#define XM_RX_THR 0x011c /* 32 bit r/w Receive Request Threshold */ +#define XM_DEV_ID 0x0120 /* 32 bit r/o Device ID Register */ +#define XM_MODE 0x0124 /* 32 bit r/w Mode Register */ +#define XM_LSA 0x0128 /* NA reg r/o Last Source Register */ + /* 0x012e: reserved */ +#define XM_TS_READ 0x0130 /* 32 bit r/o Time Stamp Read Register */ +#define XM_TS_LOAD 0x0134 /* 32 bit r/o Time Stamp Load Value */ + /* 0x0138 - 0x01fe: reserved */ +#define XM_STAT_CMD 0x0200 /* 16 bit r/w Statistics Command Register */ +#define XM_RX_CNT_EV 0x0204 /* 32 bit r/o Rx Counter Event Register */ +#define XM_TX_CNT_EV 0x0208 /* 32 bit r/o Tx Counter Event Register */ +#define XM_RX_EV_MSK 0x020c /* 32 bit r/w Rx Counter Event Mask */ +#define XM_TX_EV_MSK 0x0210 /* 32 bit r/w Tx Counter Event Mask */ + /* 0x0204 - 0x027e: reserved */ +#define XM_TXF_OK 0x0280 /* 32 bit r/o Frames Transmitted OK Conuter */ +#define XM_TXO_OK_HI 0x0284 /* 32 bit r/o Octets Transmitted OK High Cnt*/ +#define XM_TXO_OK_LO 0x0288 /* 32 bit r/o Octets Transmitted OK Low Cnt */ +#define XM_TXF_BC_OK 0x028c /* 32 bit r/o Broadcast Frames Xmitted OK */ +#define XM_TXF_MC_OK 0x0290 /* 32 bit r/o Multicast Frames Xmitted OK */ +#define XM_TXF_UC_OK 0x0294 /* 32 bit r/o Unicast Frames Xmitted OK */ +#define XM_TXF_LONG 0x0298 /* 32 bit r/o Tx Long Frame Counter */ +#define XM_TXE_BURST 0x029c /* 32 bit r/o Tx Burst Event Counter */ +#define XM_TXF_MPAUSE 0x02a0 /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */ +#define XM_TXF_MCTRL 0x02a4 /* 32 bit r/o Tx MAC Ctrl Frame Counter */ +#define XM_TXF_SNG_COL 0x02a8 /* 32 bit r/o Tx Single Collision Counter */ +#define XM_TXF_MUL_COL 0x02ac /* 32 bit r/o Tx Multiple Collision Counter */ +#define XM_TXF_ABO_COL 0x02b0 /* 32 bit r/o Tx aborted due to Exces. Col. */ +#define XM_TXF_LAT_COL 0x02b4 /* 32 bit r/o Tx Late Collision Counter */ +#define XM_TXF_DEF 0x02b8 /* 32 bit r/o Tx Deferred Frame Counter */ +#define XM_TXF_EX_DEF 0x02bc /* 32 bit r/o Tx Excessive Deferall Counter */ +#define XM_TXE_FIFO_UR 0x02c0 /* 32 bit r/o Tx FIFO Underrun Event Cnt */ +#define XM_TXE_CS_ERR 0x02c4 /* 32 bit r/o Tx Carrier Sense Error Cnt */ +#define XM_TXP_UTIL 0x02c8 /* 32 bit r/o Tx Utilization in % */ + /* 0x02cc - 0x02ce: reserved */ +#define XM_TXF_64B 0x02d0 /* 32 bit r/o 64 Byte Tx Frame Counter */ +#define XM_TXF_127B 0x02d4 /* 32 bit r/o 65-127 Byte Tx Frame Counter */ +#define XM_TXF_255B 0x02d8 /* 32 bit r/o 128-255 Byte Tx Frame Counter */ +#define XM_TXF_511B 0x02dc /* 32 bit r/o 256-511 Byte Tx Frame Counter */ +#define XM_TXF_1023B 0x02e0 /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/ +#define XM_TXF_MAX_SZ 0x02e4 /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/ + /* 0x02e8 - 0x02fe: reserved */ +#define XM_RXF_OK 0x0300 /* 32 bit r/o Frames Received OK */ +#define XM_RXO_OK_HI 0x0304 /* 32 bit r/o Octets Received OK High Cnt */ +#define XM_RXO_OK_LO 0x0308 /* 32 bit r/o Octets Received OK Low Counter*/ +#define XM_RXF_BC_OK 0x030c /* 32 bit r/o Broadcast Frames Received OK */ +#define XM_RXF_MC_OK 0x0310 /* 32 bit r/o Multicast Frames Received OK */ +#define XM_RXF_UC_OK 0x0314 /* 32 bit r/o Unicast Frames Received OK */ +#define XM_RXF_MPAUSE 0x0318 /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */ +#define XM_RXF_MCTRL 0x031c /* 32 bit r/o Rx MAC Ctrl Frame Counter */ +#define XM_RXF_INV_MP 0x0320 /* 32 bit r/o Rx invalid Pause Frame Cnt */ +#define XM_RXF_INV_MOC 0x0324 /* 32 bit r/o Rx Frames with inv. MAC Opcode*/ +#define XM_RXE_BURST 0x0328 /* 32 bit r/o Rx Burst Event Counter */ +#define XM_RXE_FMISS 0x032c /* 32 bit r/o Rx Missed Frames Event Cnt */ +#define XM_RXF_FRA_ERR 0x0330 /* 32 bit r/o Rx Framing Error Counter */ +#define XM_RXE_FIFO_OV 0x0334 /* 32 bit r/o Rx FIFO overflow Event Cnt */ +#define XM_RXF_JAB_PKT 0x0338 /* 32 bit r/o Rx Jabber Packet Frame Cnt */ +#define XM_RXE_CAR_ERR 0x033c /* 32 bit r/o Rx Carrier Event Error Cnt */ +#define XM_RXF_LEN_ERR 0x0340 /* 32 bit r/o Rx in Range Length Error */ +#define XM_RXE_SYM_ERR 0x0344 /* 32 bit r/o Rx Symbol Error Counter */ +#define XM_RXE_SHT_ERR 0x0348 /* 32 bit r/o Rx Short Event Error Cnt */ +#define XM_RXE_RUNT 0x034c /* 32 bit r/o Rx Runt Event Counter */ +#define XM_RXF_LNG_ERR 0x0350 /* 32 bit r/o Rx Frame too Long Error Cnt */ +#define XM_RXF_FCS_ERR 0x0354 /* 32 bit r/o Rx Frame Check Seq. Error Cnt */ + /* 0x0358 - 0x035a: reserved */ +#define XM_RXF_CEX_ERR 0x035c /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/ +#define XM_RXP_UTIL 0x0360 /* 32 bit r/o Rx Utilization in % */ + /* 0x0364 - 0x0366: reserved */ +#define XM_RXF_64B 0x0368 /* 32 bit r/o 64 Byte Rx Frame Counter */ +#define XM_RXF_127B 0x036c /* 32 bit r/o 65-127 Byte Rx Frame Counter */ +#define XM_RXF_255B 0x0370 /* 32 bit r/o 128-255 Byte Rx Frame Counter */ +#define XM_RXF_511B 0x0374 /* 32 bit r/o 256-511 Byte Rx Frame Counter */ +#define XM_RXF_1023B 0x0378 /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/ +#define XM_RXF_MAX_SZ 0x037c /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/ + /* 0x02e8 - 0x02fe: reserved */ + + +/*----------------------------------------------------------------------------*/ +/* + * XMAC Bit Definitions + * + * If the bit access behaviour differs from the register access behaviour + * (r/w, r/o) this is documented after the bit number. + * The following bit access behaviours are used: + * (sc) self clearing + * (ro) read only + */ + +/* XM_MMU_CMD 16 bit r/w MMU Command Register */ + /* Bit 15..13: reserved */ +#define XM_MMU_PHY_RDY (1<<12) /* Bit 12: PHY Read Ready */ +#define XM_MMU_PHY_BUSY (1<<11) /* Bit 11: PHY Busy */ +#define XM_MMU_IGN_PF (1<<10) /* Bit 10: Ignore Pause Frame */ +#define XM_MMU_MAC_LB (1<<9) /* Bit 9: Enable MAC Loopback */ + /* Bit 8: reserved */ +#define XM_MMU_FRC_COL (1<<7) /* Bit 7: Force Collision */ +#define XM_MMU_SIM_COL (1<<6) /* Bit 6: Simulate Collision */ +#define XM_MMU_NO_PRE (1<<5) /* Bit 5: No MDIO Preamble */ +#define XM_MMU_GMII_FD (1<<4) /* Bit 4: GMII uses Full Duplex */ +#define XM_MMU_RAT_CTRL (1<<3) /* Bit 3: Enable Rate Control */ +#define XM_MMU_GMII_LOOP (1<<2) /* Bit 2: PHY is in Loopback Mode */ +#define XM_MMU_ENA_RX (1<<1) /* Bit 1: Enable Receiver */ +#define XM_MMU_ENA_TX (1<<0) /* Bit 0: Enable Transmitter */ + + +/* XM_TX_CMD 16 bit r/w Transmit Command Register */ + /* Bit 15..7: reserved */ +#define XM_TX_BK2BK (1<<6) /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/ +#define XM_TX_ENC_BYP (1<<5) /* Bit 5: Set Encoder in Bypass Mode */ +#define XM_TX_SAM_LINE (1<<4) /* Bit 4: (sc) Start utilization calculation */ +#define XM_TX_NO_GIG_MD (1<<3) /* Bit 3: Disable Carrier Extension */ +#define XM_TX_NO_PRE (1<<2) /* Bit 2: Disable Preamble Generation */ +#define XM_TX_NO_CRC (1<<1) /* Bit 1: Disable CRC Generation */ +#define XM_TX_AUTO_PAD (1<<0) /* Bit 0: Enable Automatic Padding */ + + +/* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */ + /* Bit 15..5: reserved */ +#define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */ + + +/* XM_TX_STIME 16 bit r/w Transmit Slottime Register */ + /* Bit 15..7: reserved */ +#define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */ + + +/* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */ + /* Bit 15..8: reserved */ +#define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */ + + +/* XM_RX_CMD 16 bit r/w Receive Command Register */ + /* Bit 15..9: reserved */ +#define XM_RX_LENERR_OK (1<<8) /* Bit 8 don't set Rx Err bit for */ + /* inrange error packets */ +#define XM_RX_BIG_PK_OK (1<<7) /* Bit 7 don't set Rx Err bit for */ + /* jumbo packets */ +#define XM_RX_IPG_CAP (1<<6) /* Bit 6 repl. type field with IPG */ +#define XM_RX_TP_MD (1<<5) /* Bit 5: Enable transparent Mode */ +#define XM_RX_STRIP_FCS (1<<4) /* Bit 4: Enable FCS Stripping */ +#define XM_RX_SELF_RX (1<<3) /* Bit 3: Enable Rx of own packets */ +#define XM_RX_SAM_LINE (1<<2) /* Bit 2: (sc) Start utilization calculation */ +#define XM_RX_STRIP_PAD (1<<1) /* Bit 1: Strip pad bytes of Rx frames */ +#define XM_RX_DIS_CEXT (1<<0) /* Bit 0: Disable carrier ext. check */ + + +/* XM_PHY_ADDR 16 bit r/w PHY Address Register */ + /* Bit 15..5: reserved */ +#define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */ + + +/* XM_GP_PORT 32 bit r/w General Purpose Port Register */ + /* Bit 31..7: reserved */ +#define XM_GP_ANIP (1L<<6) /* Bit 6: (ro) Auto-Neg. in progress */ +#define XM_GP_FRC_INT (1L<<5) /* Bit 5: (sc) Force Interrupt */ + /* Bit 4: reserved */ +#define XM_GP_RES_MAC (1L<<3) /* Bit 3: (sc) Reset MAC and FIFOs */ +#define XM_GP_RES_STAT (1L<<2) /* Bit 2: (sc) Reset the statistics module */ + /* Bit 1: reserved */ +#define XM_GP_INP_ASS (1L<<0) /* Bit 0: (ro) GP Input Pin asserted */ + + +/* XM_IMSK 16 bit r/w Interrupt Mask Register */ +/* XM_ISRC 16 bit r/o Interrupt Status Register */ + /* Bit 15: reserved */ +#define XM_IS_LNK_AE (1<<14) /* Bit 14: Link Asynchronous Event */ +#define XM_IS_TX_ABORT (1<<13) /* Bit 13: Transmit Abort, late Col. etc */ +#define XM_IS_FRC_INT (1<<12) /* Bit 12: Force INT bit set in GP */ +#define XM_IS_INP_ASS (1<<11) /* Bit 11: Input Asserted, GP bit 0 set */ +#define XM_IS_LIPA_RC (1<<10) /* Bit 10: Link Partner requests config */ +#define XM_IS_RX_PAGE (1<<9) /* Bit 9: Page Received */ +#define XM_IS_TX_PAGE (1<<8) /* Bit 8: Next Page Loaded for Transmit */ +#define XM_IS_AND (1<<7) /* Bit 7: Auto-Negotiation Done */ +#define XM_IS_TSC_OV (1<<6) /* Bit 6: Time Stamp Counter Overflow */ +#define XM_IS_RXC_OV (1<<5) /* Bit 5: Rx Counter Event Overflow */ +#define XM_IS_TXC_OV (1<<4) /* Bit 4: Tx Counter Event Overflow */ +#define XM_IS_RXF_OV (1<<3) /* Bit 3: Receive FIFO Overflow */ +#define XM_IS_TXF_UR (1<<2) /* Bit 2: Transmit FIFO Underrun */ +#define XM_IS_TX_COMP (1<<1) /* Bit 1: Frame Tx Complete */ +#define XM_IS_RX_COMP (1<<0) /* Bit 0: Frame Rx Complete */ + +#define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\ + XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_TXF_UR)) + + +/* XM_HW_CFG 16 bit r/w Hardware Config Register */ + /* Bit 15.. 4: reserved */ +#define XM_HW_GEN_EOP (1<<3) /* Bit 3: generate End of Packet pulse */ +#define XM_HW_COM4SIG (1<<2) /* Bit 2: use Comma Detect for Sig. Det.*/ + /* Bit 1: reserved */ +#define XM_HW_GMII_MD (1<<0) /* Bit 0: GMII Interface selected */ + + +/* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */ +/* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */ + /* Bit 15..10 reserved */ +#define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */ + +/* XM_TX_THR 16 bit r/w Tx Request Threshold */ +/* XM_HT_THR 16 bit r/w Host Request Threshold */ +/* XM_RX_THR 16 bit r/w Rx Request Threshold */ + /* Bit 15..11 reserved */ +#define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */ + + +/* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */ +#define XM_ST_VALID (1UL<<31) /* Bit 31: Status Valid */ +#define XM_ST_BYTE_CNT (0x3fffL<<17) /* Bit 30..17: Tx frame Length */ +#define XM_ST_RETRY_CNT (0x1fL<<12) /* Bit 16..12: Retry Count */ +#define XM_ST_EX_COL (1L<<11) /* Bit 11: Excessive Collisions */ +#define XM_ST_EX_DEF (1L<<10) /* Bit 10: Excessive Deferral */ +#define XM_ST_BURST (1L<<9) /* Bit 9: p. xmitted in burst md*/ +#define XM_ST_DEFER (1L<<8) /* Bit 8: packet was defered */ +#define XM_ST_BC (1L<<7) /* Bit 7: Broadcast packet */ +#define XM_ST_MC (1L<<6) /* Bit 6: Multicast packet */ +#define XM_ST_UC (1L<<5) /* Bit 5: Unicast packet */ +#define XM_ST_TX_UR (1L<<4) /* Bit 4: FIFO Underrun occured */ +#define XM_ST_CS_ERR (1L<<3) /* Bit 3: Carrier Sense Error */ +#define XM_ST_LAT_COL (1L<<2) /* Bit 2: Late Collision Error */ +#define XM_ST_MUL_COL (1L<<1) /* Bit 1: Multiple Collisions */ +#define XM_ST_SGN_COL (1L<<0) /* Bit 0: Single Collision */ + +/* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */ +/* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */ + /* Bit 15..11: reserved */ +#define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */ + + +/* XM_DEV_ID 32 bit r/o Device ID Register */ +#define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */ +#define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */ + + +/* XM_MODE 32 bit r/w Mode Register */ + /* Bit 31..27: reserved */ +#define XM_MD_ENA_REJ (1L<<26) /* Bit 26: Enable Frame Reject */ +#define XM_MD_SPOE_E (1L<<25) /* Bit 25: Send Pause on Edge */ + /* extern generated */ +#define XM_MD_TX_REP (1L<<24) /* Bit 24: Transmit Repeater Mode */ +#define XM_MD_SPOFF_I (1L<<23) /* Bit 23: Send Pause on FIFO full */ + /* intern generated */ +#define XM_MD_LE_STW (1L<<22) /* Bit 22: Rx Stat Word in Little Endian */ +#define XM_MD_TX_CONT (1L<<21) /* Bit 21: Send Continuous */ +#define XM_MD_TX_PAUSE (1L<<20) /* Bit 20: (sc) Send Pause Frame */ +#define XM_MD_ATS (1L<<19) /* Bit 19: Append Time Stamp */ +#define XM_MD_SPOL_I (1L<<18) /* Bit 18: Send Pause on Low */ + /* intern generated */ +#define XM_MD_SPOH_I (1L<<17) /* Bit 17: Send Pause on High */ + /* intern generated */ +#define XM_MD_CAP (1L<<16) /* Bit 16: Check Address Pair */ +#define XM_MD_ENA_HASH (1L<<15) /* Bit 15: Enable Hashing */ +#define XM_MD_CSA (1L<<14) /* Bit 14: Check Station Address */ +#define XM_MD_CAA (1L<<13) /* Bit 13: Check Address Array */ +#define XM_MD_RX_MCTRL (1L<<12) /* Bit 12: Rx MAC Control Frame */ +#define XM_MD_RX_RUNT (1L<<11) /* Bit 11: Rx Runt Frames */ +#define XM_MD_RX_IRLE (1L<<10) /* Bit 10: Rx in Range Len Err Frame */ +#define XM_MD_RX_LONG (1L<<9) /* Bit 9: Rx Long Frame */ +#define XM_MD_RX_CRCE (1L<<8) /* Bit 8: Rx CRC Error Frame */ +#define XM_MD_RX_ERR (1L<<7) /* Bit 7: Rx Error Frame */ +#define XM_MD_DIS_UC (1L<<6) /* Bit 6: Disable Rx Unicast */ +#define XM_MD_DIS_MC (1L<<5) /* Bit 5: Disable Rx Multicast */ +#define XM_MD_DIS_BC (1L<<4) /* Bit 4: Disable Rx Broadcast */ +#define XM_MD_ENA_PROM (1L<<3) /* Bit 3: Enable Promiscuous */ +#define XM_MD_ENA_BE (1L<<2) /* Bit 2: Enable Big Endian */ +#define XM_MD_FTF (1L<<1) /* Bit 1: (sc) Flush Tx FIFO */ +#define XM_MD_FRF (1L<<0) /* Bit 0: (sc) Flush Rx FIFO */ + +#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I) +#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\ + XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA) + +/* XM_STAT_CMD 16 bit r/w Statistics Command Register */ + /* Bit 16..6: reserved */ +#define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */ +#define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */ +#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */ +#define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */ +#define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */ +#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */ + + +/* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */ +/* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */ +#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/ +#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/ +#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/ +#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/ +#define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */ +#define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */ +#define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */ +#define XMR_UTIL_UR (1L<<24) /* Bit 24: Rx Util Cnt Underrun */ +#define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */ + /* Bit 22: reserved */ +#define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */ +#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/ +#define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */ +#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/ +#define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */ + /* Bit 16: reserved */ +#define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */ +#define XMR_JAB_PKT_OV (1L<<14) /* Bit 14: Rx Jabb Packet Cnt Ov */ +#define XMR_FIFO_OV (1L<<13) /* Bit 13: Rx FIFO Ov Ev Cnt Ov */ +#define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */ +#define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */ +#define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */ +#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/ +#define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */ +#define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */ +#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/ +#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/ +#define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */ +#define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */ +#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/ +#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/ +#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */ + +#define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV) + +/* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */ +/* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */ + /* Bit 31..26: reserved */ +#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/ +#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/ +#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/ +#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/ +#define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */ +#define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */ +#define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */ +#define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */ +#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/ +#define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */ +#define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */ +#define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */ +#define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */ +#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/ +#define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */ +#define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */ +#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/ +#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/ +#define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */ +#define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */ +#define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */ +#define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */ +#define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */ +#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/ +#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/ +#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */ + +#define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV) + +/* + * Receive Frame Status Encoding + */ +#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */ +#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/ +#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/ +#define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */ +#define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */ +#define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */ + /* Bit 12: reserved */ +#define XMR_FS_BURST (1L<<11) /* Bit 11: Burst Mode */ +#define XMR_FS_CEX_ERR (1L<<10) /* Bit 10: Carrier Ext. Error */ +#define XMR_FS_802_3 (1L<<9) /* Bit 9: 802.3 Frame */ +#define XMR_FS_COL_ERR (1L<<8) /* Bit 8: Collision Error */ +#define XMR_FS_CAR_ERR (1L<<7) /* Bit 7: Carrier Event Error */ +#define XMR_FS_LEN_ERR (1L<<6) /* Bit 6: In-Range Length Error */ +#define XMR_FS_FRA_ERR (1L<<5) /* Bit 5: Framing Error */ +#define XMR_FS_RUNT (1L<<4) /* Bit 4: Runt Frame */ +#define XMR_FS_LNG_ERR (1L<<3) /* Bit 3: Giant (Jumbo) Frame */ +#define XMR_FS_FCS_ERR (1L<<2) /* Bit 2: Frame Check Sequ Err */ +#define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */ +#define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */ + +/* + * XMR_FS_ERR will be set if + * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, + * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR + * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue + * XMR_FS_ERR unless the corresponding bit in the Receive Command + * Register is set. + */ +#define XMR_FS_ANY_ERR XMR_FS_ERR + +/*----------------------------------------------------------------------------*/ +/* + * XMAC-PHY Registers, indirect addressed over the XMAC + */ +#define PHY_XMAC_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_XMAC_STAT 0x01 /* 16 bit r/w PHY Status Register */ +#define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */ +#define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */ + /* 0x09 - 0x0e: reserved */ +#define PHY_XMAC_EXT_STAT 0x0f /* 16 bit r/o Ext Status Register */ +#define PHY_XMAC_RES_ABI 0x10 /* 16 bit r/o PHY Resolved Ability */ + +/*----------------------------------------------------------------------------*/ +/* + * Broadcom-PHY Registers, indirect addressed over XMAC + */ +#define PHY_BCOM_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_BCOM_STAT 0x01 /* 16 bit r/o PHY Status Register */ +#define PHY_BCOM_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_BCOM_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ +#define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */ + /* Broadcom-specific registers */ +#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ +#define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ + /* 0x0b - 0x0e: reserved */ +#define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ +#define PHY_BCOM_P_EXT_CTRL 0x10 /* 16 bit r/w PHY Extended Ctrl Reg */ +#define PHY_BCOM_P_EXT_STAT 0x11 /* 16 bit r/o PHY Extended Stat Reg */ +#define PHY_BCOM_RE_CTR 0x12 /* 16 bit r/w Receive Error Counter */ +#define PHY_BCOM_FC_CTR 0x13 /* 16 bit r/w False Carr Sense Cnt */ +#define PHY_BCOM_RNO_CTR 0x14 /* 16 bit r/w Receiver NOT_OK Cnt */ + /* 0x15 - 0x17: reserved */ +#define PHY_BCOM_AUX_CTRL 0x18 /* 16 bit r/w Auxiliary Control Reg */ +#define PHY_BCOM_AUX_STAT 0x19 /* 16 bit r/o Auxiliary Stat Summary */ +#define PHY_BCOM_INT_STAT 0x1a /* 16 bit r/o Interrupt Status Reg */ +#define PHY_BCOM_INT_MASK 0x1b /* 16 bit r/w Interrupt Mask Reg */ + /* 0x1c: reserved */ + /* 0x1d - 0x1f: test registers */ + +/*----------------------------------------------------------------------------*/ +/* + * Marvel-PHY Registers, indirect addressed over GMAC + */ +#define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ +#define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ +#define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */ + /* Marvel-specific registers */ +#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ +#define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ + /* 0x0b - 0x0e: reserved */ +#define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ +#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */ +#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */ +#define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ +#define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ +#define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ +#define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ +#define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ + /* 0x17: reserved */ +#define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ +#define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ +#define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ +#define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ +#define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ + /* 0x1d - 0x1f: reserved */ + +/*----------------------------------------------------------------------------*/ +/* + * Level One-PHY Registers, indirect addressed over XMAC + */ +#define PHY_LONE_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_LONE_STAT 0x01 /* 16 bit r/o PHY Status Register */ +#define PHY_LONE_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_LONE_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ +#define PHY_LONE_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner*/ + /* Level One-specific registers */ +#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/ +#define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ + /* 0x0b -0x0e: reserved */ +#define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ +#define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/ +#define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */ +#define PHY_LONE_INT_ENAB 0x12 /* 16 bit r/w Interrupt Enable Reg */ +#define PHY_LONE_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ +#define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */ +#define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */ +#define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */ + /* 0x17 -0x1c: reserved */ + +/*----------------------------------------------------------------------------*/ +/* + * National-PHY Registers, indirect addressed over XMAC + */ +#define PHY_NAT_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_NAT_STAT 0x01 /* 16 bit r/w PHY Status Register */ +#define PHY_NAT_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_NAT_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_NAT_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_NAT_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */ +#define PHY_NAT_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_NAT_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_NAT_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner Reg */ + /* National-specific registers */ +#define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ +#define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ + /* 0x0b -0x0e: reserved */ +#define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */ +#define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */ +#define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */ +#define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */ +#define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */ +#define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */ + /* 0x15 -0x18: reserved */ +#define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */ + + +/*----------------------------------------------------------------------------*/ + +/* + * PHY bit definitions + * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are + * Xmac/Broadcom/LevelOne/National-specific. + * All other are general. + */ + +/***** PHY_XMAC_CTRL 16 bit r/w PHY Control Register *****/ +/***** PHY_BCOM_CTRL 16 bit r/w PHY Control Register *****/ +/***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/ +#define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ +#define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ +#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */ +#define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ +#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */ +#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */ +#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ +#define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ +#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */ +#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */ + /* Bit 5..0: reserved */ + +#define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ +#define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ +#define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ + + +/***** PHY_XMAC_STAT 16 bit r/w PHY Status Register *****/ +/***** PHY_BCOM_STAT 16 bit r/w PHY Status Register *****/ +/***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/ +/***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/ + /* Bit 15..9: reserved */ + /* (BC/L1) 100/10 Mbps cap bits ignored*/ +#define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ + /* Bit 7: reserved */ +#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */ +#define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ +#define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */ +#define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ +#define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ +#define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */ +#define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ + + +/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */ +#define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ +#define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ +#define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */ + +/* different Broadcom PHY Ids */ +#define PHY_BCOM_ID1_A1 0x6041 +#define PHY_BCOM_ID1_B2 0x6043 +#define PHY_BCOM_ID1_C0 0x6044 +#define PHY_BCOM_ID1_C5 0x6047 + + +/***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ +#define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */ +#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */ +#define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */ + /* Bit 11.. 9: reserved */ +#define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */ +#define PHY_X_AN_HD (1<<6) /* Bit 6: Half Duplex */ +#define PHY_X_AN_FD (1<<5) /* Bit 5: Full Duplex */ + /* Bit 4.. 0: reserved */ + +/***** PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ +/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ + /* Bit 14: reserved */ +#define PHY_B_AN_RF (1<<13) /* Bit 13: Remote Fault */ + /* Bit 12: reserved */ +#define PHY_B_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */ +#define PHY_B_AN_PC (1<<10) /* Bit 10: Pause Capable */ + /* Bit 9..5: 100/10 BT cap bits ingnored */ +#define PHY_B_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/ + +/***** PHY_LONE_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_LONE_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ +/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ + /* Bit 14: reserved */ +#define PHY_L_AN_RF (1<<13) /* Bit 13: Remote Fault */ + /* Bit 12: reserved */ +#define PHY_L_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */ +#define PHY_L_AN_PC (1<<10) /* Bit 10: Pause Capable */ + /* Bit 9..5: 100/10 BT cap bits ingnored */ +#define PHY_L_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/ + +/***** PHY_NAT_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_NAT_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ +/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ + /* Bit 14: reserved */ +#define PHY_N_AN_RF (1<<13) /* Bit 13: Remote Fault */ + /* Bit 12: reserved */ +#define PHY_N_AN_100F (1<<11) /* Bit 11: 100Base-T2 FD Support */ +#define PHY_N_AN_100H (1<<10) /* Bit 10: 100Base-T2 HD Support */ + /* Bit 9..5: 100/10 BT cap bits ingnored */ +#define PHY_N_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/ + +/* field type definition for PHY_x_AN_SEL */ +#define PHY_SEL_TYPE 0x01 /* 00001 = Ethernet */ + +/***** PHY_XMAC_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ + /* Bit 15..4: reserved */ +#define PHY_AN_LP_NP (1<<3) /* Bit 3: Link Partner can Next Page */ +#define PHY_AN_LOC_NP (1<<2) /* Bit 2: Local PHY can Next Page */ +#define PHY_AN_RX_PG (1<<1) /* Bit 1: Page Received */ + /* Bit 0: reserved */ + +/***** PHY_BCOM_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ + /* Bit 15..5: reserved */ +#define PHY_B_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */ +/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ +/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ +/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */ +#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */ + +/***** PHY_LONE_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ +#define PHY_L_AN_BP (1<<5) /* Bit 5: Base Page Indication */ +#define PHY_L_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */ +/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ +/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ +/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */ +#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */ + + +/***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/ +/***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/ +/***** PHY_LONE_NEPG 16 bit r/w Next Page Register *****/ +/***** PHY_XMAC_NEPG_LP 16 bit r/o Next Page Link Partner *****/ +/***** PHY_BCOM_NEPG_LP 16 bit r/o Next Page Link Partner *****/ +/***** PHY_LONE_NEPG_LP 16 bit r/o Next Page Link Partner *****/ +#define PHY_NP_MORE (1<<15) /* Bit 15: More, Next Pages to follow */ +#define PHY_NP_ACK1 (1<<14) /* Bit 14: (ro) Ack 1, for receiving a message*/ +#define PHY_NP_MSG_VAL (1<<13) /* Bit 13: Message Page valid */ +#define PHY_NP_ACK2 (1<<12) /* Bit 12: Ack 2, comply with msg content*/ +#define PHY_NP_TOG (1<<11) /* Bit 11: Toggle Bit, ensure sync */ +#define PHY_NP_MSG 0x07ff /* Bit 10..0: Message from/to Link Partner */ + +/* + * XMAC-Specific + */ +/***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/ +#define PHY_X_EX_FD (1<<15) /* Bit 15: Device Supports Full Duplex */ +#define PHY_X_EX_HD (1<<14) /* Bit 14: Device Supports Half Duplex */ + /* Bit 13..0: reserved */ + +/***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/ + /* Bit 15..9: reserved */ +#define PHY_X_RS_PAUSE (3<<7) /* Bit 8..7: selected Pause Mode */ +#define PHY_X_RS_HD (1<<6) /* Bit 6: Half Duplex Mode selected */ +#define PHY_X_RS_FD (1<<5) /* Bit 5: Full Duplex Mode selected */ +#define PHY_X_RS_ABLMIS (1<<4) /* Bit 4: duplex or pause cap mismatch */ +#define PHY_X_RS_PAUMIS (1<<3) /* Bit 3: pause capability missmatch */ + /* Bit 2..0: reserved */ +/* + * Remote Fault Bits (PHY_X_AN_RFB) encoding + */ +#define X_RFB_OK (0<<12) /* Bit 13..12 No errors, Link OK */ +#define X_RFB_LF (1<<12) /* Bit 13..12 Link Failure */ +#define X_RFB_OFF (2<<12) /* Bit 13..12 Offline */ +#define X_RFB_AN_ERR (3<<12) /* Bit 13..12 Auto-Negotiation Error */ + +/* + * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding + */ +#define PHY_X_P_NO_PAUSE (0<<7) /* Bit 8..7: no Pause Mode */ +#define PHY_X_P_SYM_MD (1<<7) /* Bit 8..7: symmetric Pause Mode */ +#define PHY_X_P_ASYM_MD (2<<7) /* Bit 8..7: asymmetric Pause Mode */ +#define PHY_X_P_BOTH_MD (3<<7) /* Bit 8..7: both Pause Mode */ + + +/* + * Broadcom-Specific + */ +/***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ +#define PHY_B_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ +#define PHY_B_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ +#define PHY_B_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ +#define PHY_B_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ +#define PHY_B_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ +#define PHY_B_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ + /* Bit 7..0: reserved */ + +/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ +#define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ +#define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ +#define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ +#define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ +#define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ +#define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ + /* Bit 9..8: reserved */ +#define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ + +/***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/ +#define PHY_B_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ +#define PHY_B_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ +#define PHY_B_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ +#define PHY_B_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ + /* Bit 11..0: reserved */ + +/***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/ +#define PHY_B_PEC_MAC_PHY (1<<15) /* Bit 15: 10BIT/GMI-Interface */ +#define PHY_B_PEC_DIS_CROSS (1<<14) /* Bit 14: Disable MDI Crossover */ +#define PHY_B_PEC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */ +#define PHY_B_PEC_INT_DIS (1<<12) /* Bit 12: Interrupts Disabled */ +#define PHY_B_PEC_F_INT (1<<11) /* Bit 11: Force Interrupt */ +#define PHY_B_PEC_BY_45 (1<<10) /* Bit 10: Bypass 4B5B-Decoder */ +#define PHY_B_PEC_BY_SCR (1<<9) /* Bit 9: Bypass Scrambler */ +#define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */ +#define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */ +#define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */ +#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */ +#define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */ +#define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */ +#define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */ +#define PHY_B_PEC_3_LED (1<<1) /* Bit 1: Three Link LED mode */ +#define PHY_B_PEC_HIGH_LA (1<<0) /* Bit 0: GMII FIFO Elasticy */ + +/***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/ + /* Bit 15..14: reserved */ +#define PHY_B_PES_CROSS_STAT (1<<13) /* Bit 13: MDI Crossover Status */ +#define PHY_B_PES_INT_STAT (1<<12) /* Bit 12: Interrupt Status */ +#define PHY_B_PES_RRS (1<<11) /* Bit 11: Remote Receiver Stat. */ +#define PHY_B_PES_LRS (1<<10) /* Bit 10: Local Receiver Stat. */ +#define PHY_B_PES_LOCKED (1<<9) /* Bit 9: Locked */ +#define PHY_B_PES_LS (1<<8) /* Bit 8: Link Status */ +#define PHY_B_PES_RF (1<<7) /* Bit 7: Remote Fault */ +#define PHY_B_PES_CE_ER (1<<6) /* Bit 6: Carrier Ext Error */ +#define PHY_B_PES_BAD_SSD (1<<5) /* Bit 5: Bad SSD */ +#define PHY_B_PES_BAD_ESD (1<<4) /* Bit 4: Bad ESD */ +#define PHY_B_PES_RX_ER (1<<3) /* Bit 3: Receive Error */ +#define PHY_B_PES_TX_ER (1<<2) /* Bit 2: Transmit Error */ +#define PHY_B_PES_LOCK_ER (1<<1) /* Bit 1: Lock Error */ +#define PHY_B_PES_MLT3_ER (1<<0) /* Bit 0: MLT3 code Error */ + +/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ + /* Bit 15..8: reserved */ +#define PHY_B_FC_CTR 0xff /* Bit 7..0: False Carrier Counter */ + +/***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/ +#define PHY_B_RC_LOC_MSK 0xff00 /* Bit 15..8: Local Rx NOT_OK cnt */ +#define PHY_B_RC_REM_MSK 0x00ff /* Bit 7..0: Remote Rx NOT_OK cnt */ + +/***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/ +#define PHY_B_AC_L_SQE (1<<15) /* Bit 15: Low Squelch */ +#define PHY_B_AC_LONG_PACK (1<<14) /* Bit 14: Rx Long Packets */ +#define PHY_B_AC_ER_CTRL (3<<12) /* Bit 13..12: Edgerate Control */ + /* Bit 11: reserved */ +#define PHY_B_AC_TX_TST (1<<10) /* Bit 10: Tx test bit, always 1 */ + /* Bit 9.. 8: reserved */ +#define PHY_B_AC_DIS_PRF (1<<7) /* Bit 7: dis part resp filter */ + /* Bit 6: reserved */ +#define PHY_B_AC_DIS_PM (1<<5) /* Bit 5: dis power management */ + /* Bit 4: reserved */ +#define PHY_B_AC_DIAG (1<<3) /* Bit 3: Diagnostic Mode */ + /* Bit 2.. 0: reserved */ + +/***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/ +#define PHY_B_AS_AN_C (1<<15) /* Bit 15: AutoNeg complete */ +#define PHY_B_AS_AN_CA (1<<14) /* Bit 14: AN Complete Ack */ +#define PHY_B_AS_ANACK_D (1<<13) /* Bit 13: AN Ack Detect */ +#define PHY_B_AS_ANAB_D (1<<12) /* Bit 12: AN Ability Detect */ +#define PHY_B_AS_NPW (1<<11) /* Bit 11: AN Next Page Wait */ +#define PHY_B_AS_AN_RES_MSK (7<<8) /* Bit 10..8: AN HDC */ +#define PHY_B_AS_PDF (1<<7) /* Bit 7: Parallel Detect. Fault */ +#define PHY_B_AS_RF (1<<6) /* Bit 6: Remote Fault */ +#define PHY_B_AS_ANP_R (1<<5) /* Bit 5: AN Page Received */ +#define PHY_B_AS_LP_ANAB (1<<4) /* Bit 4: LP AN Ability */ +#define PHY_B_AS_LP_NPAB (1<<3) /* Bit 3: LP Next Page Ability */ +#define PHY_B_AS_LS (1<<2) /* Bit 2: Link Status */ +#define PHY_B_AS_PRR (1<<1) /* Bit 1: Pause Resolution-Rx */ +#define PHY_B_AS_PRT (1<<0) /* Bit 0: Pause Resolution-Tx */ + +#define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT) + +/***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/ +/***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ + /* Bit 15: reserved */ +#define PHY_B_IS_PSE (1<<14) /* Bit 14: Pair Swap Error */ +#define PHY_B_IS_MDXI_SC (1<<13) /* Bit 13: MDIX Status Change */ +#define PHY_B_IS_HCT (1<<12) /* Bit 12: counter above 32k */ +#define PHY_B_IS_LCT (1<<11) /* Bit 11: counter above 128 */ +#define PHY_B_IS_AN_PR (1<<10) /* Bit 10: Page Received */ +#define PHY_B_IS_NO_HDCL (1<<9) /* Bit 9: No HCD Link */ +#define PHY_B_IS_NO_HDC (1<<8) /* Bit 8: No HCD */ +#define PHY_B_IS_NEG_USHDC (1<<7) /* Bit 7: Negotiated Unsup. HCD */ +#define PHY_B_IS_SCR_S_ER (1<<6) /* Bit 6: Scrambler Sync Error */ +#define PHY_B_IS_RRS_CHANGE (1<<5) /* Bit 5: Remote Rx Stat Change */ +#define PHY_B_IS_LRS_CHANGE (1<<4) /* Bit 4: Local Rx Stat Change */ +#define PHY_B_IS_DUP_CHANGE (1<<3) /* Bit 3: Duplex Mode Change */ +#define PHY_B_IS_LSP_CHANGE (1<<2) /* Bit 2: Link Speed Change */ +#define PHY_B_IS_LST_CHANGE (1<<1) /* Bit 1: Link Status Changed */ +#define PHY_B_IS_CRC_ER (1<<0) /* Bit 0: CRC Error */ + +#define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) + +/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */ +#define PHY_B_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */ +#define PHY_B_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */ +#define PHY_B_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ +#define PHY_B_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ + +/* + * Resolved Duplex mode and Capabilities (Aux Status Summary Reg) + */ +#define PHY_B_RES_1000FD (7<<8) /* Bit 10..8: 1000Base-T Full Dup. */ +#define PHY_B_RES_1000HD (6<<8) /* Bit 10..8: 1000Base-T Half Dup. */ +/* others: 100/10: invalid for us */ + +/* + * Level One-Specific + */ +/***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ +#define PHY_L_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ +#define PHY_L_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ +#define PHY_L_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ +#define PHY_L_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ +#define PHY_L_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ +#define PHY_L_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ + /* Bit 7..0: reserved */ + +/***** PHY_LONE_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ +#define PHY_L_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ +#define PHY_L_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ +#define PHY_L_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ +#define PHY_L_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/ +#define PHY_L_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ +#define PHY_L_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ + /* Bit 9..8: reserved */ +#define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ + +/***** PHY_LONE_EXT_STAT 16 bit r/o Extended Status Register *****/ +#define PHY_L_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ +#define PHY_L_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ +#define PHY_L_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ +#define PHY_L_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ + /* Bit 11..0: reserved */ + +/***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/ +#define PHY_L_PC_REP_MODE (1<<15) /* Bit 15: Repeater Mode */ + /* Bit 14: reserved */ +#define PHY_L_PC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */ +#define PHY_L_PC_BY_SCR (1<<12) /* Bit 12: Bypass Scrambler */ +#define PHY_L_PC_BY_45 (1<<11) /* Bit 11: Bypass 4B5B-Decoder */ +#define PHY_L_PC_JAB_DIS (1<<10) /* Bit 10: Jabber Disabled */ +#define PHY_L_PC_SQE (1<<9) /* Bit 9: Enable Heartbeat */ +#define PHY_L_PC_TP_LOOP (1<<8) /* Bit 8: TP Loopback */ +#define PHY_L_PC_SSS (1<<7) /* Bit 7: Smart Speed Selection */ +#define PHY_L_PC_FIFO_SIZE (1<<6) /* Bit 6: FIFO Size */ +#define PHY_L_PC_PRE_EN (1<<5) /* Bit 5: Preamble Enable */ +#define PHY_L_PC_CIM (1<<4) /* Bit 4: Carrier Integrity Mon */ +#define PHY_L_PC_10_SER (1<<3) /* Bit 3: Use Serial Output */ +#define PHY_L_PC_ANISOL (1<<2) /* Bit 2: Unisolate Port */ +#define PHY_L_PC_TEN_BIT (1<<1) /* Bit 1: 10bit iface mode on */ +#define PHY_L_PC_ALTCLOCK (1<<0) /* Bit 0: (ro) ALTCLOCK Mode on */ + +/***** PHY_LONE_Q_STAT 16 bit r/o Quick Status Reg *****/ +#define PHY_L_QS_D_RATE (3<<14) /* Bit 15..14: Data Rate */ +#define PHY_L_QS_TX_STAT (1<<13) /* Bit 13: Transmitting */ +#define PHY_L_QS_RX_STAT (1<<12) /* Bit 12: Receiving */ +#define PHY_L_QS_COL_STAT (1<<11) /* Bit 11: Collision */ +#define PHY_L_QS_L_STAT (1<<10) /* Bit 10: Link is up */ +#define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */ +#define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */ +#define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */ +#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */ +#define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */ +#define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */ +#define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */ +#define PHY_L_QS_EVENT (1<<0) /* Bit 0: Event has occurred */ + +/***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/ +/***** PHY_LONE_INT_STAT 16 bit r/o Interrupt Status Reg *****/ + /* Bit 15..14: reserved */ +#define PHY_L_IS_AN_F (1<<13) /* Bit 13: Auto-Negotiation fault */ + /* Bit 12: not described */ +#define PHY_L_IS_CROSS (1<<11) /* Bit 11: Crossover used */ +#define PHY_L_IS_POL (1<<10) /* Bit 10: Polarity correct. used*/ +#define PHY_L_IS_SS (1<<9) /* Bit 9: Smart Speed Downgrade*/ +#define PHY_L_IS_CFULL (1<<8) /* Bit 8: Counter Full */ +#define PHY_L_IS_AN_C (1<<7) /* Bit 7: AutoNeg Complete */ +#define PHY_L_IS_SPEED (1<<6) /* Bit 6: Speed Changed */ +#define PHY_L_IS_DUP (1<<5) /* Bit 5: Duplex Changed */ +#define PHY_L_IS_LS (1<<4) /* Bit 4: Link Status Changed */ +#define PHY_L_IS_ISOL (1<<3) /* Bit 3: Isolate Occured */ +#define PHY_L_IS_MDINT (1<<2) /* Bit 2: (ro) STAT: MII Int Pending */ +#define PHY_L_IS_INTEN (1<<1) /* Bit 1: ENAB: Enable IRQs */ +#define PHY_L_IS_FORCE (1<<0) /* Bit 0: ENAB: Force Interrupt */ + +/* int. mask */ +#define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN) + +/***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/ +#define PHY_L_LC_LEDC (3<<14) /* Bit 15..14: Col/Blink/On/Off */ +#define PHY_L_LC_LEDR (3<<12) /* Bit 13..12: Rx/Blink/On/Off */ +#define PHY_L_LC_LEDT (3<<10) /* Bit 11..10: Tx/Blink/On/Off */ +#define PHY_L_LC_LEDG (3<<8) /* Bit 9..8: Giga/Blink/On/Off */ +#define PHY_L_LC_LEDS (3<<6) /* Bit 7..6: 10-100/Blink/On/Off */ +#define PHY_L_LC_LEDL (3<<4) /* Bit 5..4: Link/Blink/On/Off */ +#define PHY_L_LC_LEDF (3<<2) /* Bit 3..2: Duplex/Blink/On/Off */ +#define PHY_L_LC_PSTRECH (1<<1) /* Bit 1: Strech LED Pulses */ +#define PHY_L_LC_FREQ (1<<0) /* Bit 0: 30/100 ms */ + +/***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/ +#define PHY_L_PC_TX_TCLK (1<<15) /* Bit 15: Enable TX_TCLK */ + /* Bit 14: reserved */ +#define PHY_L_PC_ALT_NP (1<<13) /* Bit 14: Alternate Next Page */ +#define PHY_L_PC_GMII_ALT (1<<12) /* Bit 13: Alternate GMII driver */ + /* Bit 11: reserved */ +#define PHY_L_PC_TEN_CRS (1<<10) /* Bit 10: Extend CRS*/ + /* Bit 9..0: not described */ + +/***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/ +#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */ +#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */ + + +/* + * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding + */ +#define PHY_L_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */ +#define PHY_L_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */ +#define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ +#define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ + + +/* + * National-Specific + */ +/***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ +#define PHY_N_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ +#define PHY_N_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ +#define PHY_N_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ +#define PHY_N_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ +#define PHY_N_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ +#define PHY_N_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ +#define PHY_N_1000C_APC (1<<7) /* Bit 7: Asymmetric Pause Cap. */ + /* Bit 6..0: reserved */ + +/***** PHY_NAT_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ +#define PHY_N_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ +#define PHY_N_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ +#define PHY_N_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ +#define PHY_N_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/ +#define PHY_N_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ +#define PHY_N_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ +#define PHY_N_1000C_LP_APC (1<<9) /* Bit 9: LP Asym. Pause Cap. */ + /* Bit 8: reserved */ +#define PHY_N_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ + +/***** PHY_NAT_EXT_STAT 16 bit r/o Extended Status Register *****/ +#define PHY_N_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ +#define PHY_N_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ +#define PHY_N_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ +#define PHY_N_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ + /* Bit 11..0: reserved */ + +/* todo: those are still missing */ +/***** PHY_NAT_EXT_CTRL1 16 bit r/o Extended Control Reg1 *****/ +/***** PHY_NAT_Q_STAT1 16 bit r/o Quick Status Reg1 *****/ +/***** PHY_NAT_10B_OP 16 bit r/o 10Base-T Operations Reg *****/ +/***** PHY_NAT_EXT_CTRL2 16 bit r/o Extended Control Reg1 *****/ +/***** PHY_NAT_Q_STAT2 16 bit r/o Quick Status Reg2 *****/ +/***** PHY_NAT_PHY_ADDR 16 bit r/o PHY Address Register *****/ + +/* + * Marvell-Specific + */ +/***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ +#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ +#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ +#define PHY_M_AN_RF BIT_13 /* Remote Fault */ + /* Bit 12: reserved */ +#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ +#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ +#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ +#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ +#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ +#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ + +/* special defines for FIBER (88E1011S only) */ +#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ +#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ +#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ +#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ + +/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ +#define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ +#define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ +#define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ +#define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ + +/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ +#define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ +#define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */ +#define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */ +#define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */ +#define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ +#define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ + /* Bit 7..0: reserved */ + +/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ + +#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ +#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ +#define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */ +#define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */ +#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ +#define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */ +#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ +#define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */ +#define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */ +#define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */ +#define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */ +#define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */ + +#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x) +#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ +#define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ +#define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ + +/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ +#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ +#define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */ +#define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */ +#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ +#define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */ +#define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */ +#define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */ +#define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */ +#define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */ +#define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */ +#define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */ +#define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */ +#define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */ +#define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */ +#define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */ +#define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */ + +#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) + +/***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ +/***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ +#define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */ +#define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */ +#define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */ +#define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */ +#define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */ +#define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */ +#define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */ +#define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */ +#define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */ +#define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */ +#define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */ +#define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */ + /* Bit 3..2: reserved */ +#define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */ +#define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */ + +#define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ + PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) + +/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ +#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */ +#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */ +#define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ + +#define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */ +#define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */ +#define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */ + +#define MAC_TX_CLK_0_MHZ 2 +#define MAC_TX_CLK_2_5_MHZ 6 +#define MAC_TX_CLK_25_MHZ 7 + +/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ +#define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */ +#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ +#define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */ +#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ + /* Bit 7.. 5: reserved */ +#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ +#define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */ +#define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */ +#define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */ + +#define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */ + +#define PULS_NO_STR 0 /* no pulse stretching */ +#define PULS_21MS 1 /* 21 ms to 42 ms */ +#define PULS_42MS 2 /* 42 ms to 84 ms */ +#define PULS_84MS 3 /* 84 ms to 170 ms */ +#define PULS_170MS 4 /* 170 ms to 340 ms */ +#define PULS_340MS 5 /* 340 ms to 670 ms */ +#define PULS_670MS 6 /* 670 ms to 1.3 s */ +#define PULS_1300MS 7 /* 1.3 s to 2.7 s */ + +#define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */ + +#define BLINK_42MS 0 /* 42 ms */ +#define BLINK_84MS 1 /* 84 ms */ +#define BLINK_170MS 2 /* 170 ms */ +#define BLINK_340MS 3 /* 340 ms */ +#define BLINK_670MS 4 /* 670 ms */ + /* values 5 - 7: reserved */ + +/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ +#define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ +#define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ +#define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ +#define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ +#define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ +#define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ + +#define MO_LED_NORM 0 +#define MO_LED_BLINK 1 +#define MO_LED_OFF 2 +#define MO_LED_ON 3 + +/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ + /* Bit 15.. 7: reserved */ +#define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */ +#define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */ +#define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */ +#define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */ +#define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ + +/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ +#define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */ +#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */ + /* Bit 12.. 8: reserved */ +#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */ + +/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ +#define CABD_STAT_NORMAL 0 +#define CABD_STAT_SHORT 1 +#define CABD_STAT_OPEN 2 +#define CABD_STAT_FAIL 3 + + +/* + * GMAC registers + * + * The GMAC registers are 16 or 32 bits wide. + * The GMACs host processor interface is 16 bits wide, + * therefore ALL registers will be addressed with 16 bit accesses. + * + * The following macros are provided to access the GMAC registers + * GM_IN16(), GM_OUT16, GM_IN32(), GM_OUT32(), GM_INADR(), GM_OUTADR(), + * GM_INHASH(), and GM_OUTHASH(). + * The macros are defined in SkGeHw.h. + * + * Note: NA reg = Network Address e.g DA, SA etc. + * + */ + +/* Port Registers */ +#define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ +#define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ +#define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ +#define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ +#define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow Control */ +#define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ +#define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ + +/* Source Address Registers */ +#define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ +#define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ +#define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ +#define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ +#define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ +#define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ + +/* Multicast Address Hash Registers */ +#define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ +#define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ +#define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ +#define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ + +/* Interrupt Source Registers */ +#define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ +#define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ +#define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ + +/* Interrupt Mask Registers */ +#define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ +#define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ +#define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ + +/* Serial Management Interface (SMI) Registers */ +#define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ +#define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ +#define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ + +/* MIB Counters */ +#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ +#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ + +/* + * MIB Counters base address definitions (low word) - + * use offset 4 for access to high word (32 bit r/o) + */ +#define GM_RXF_UC_OK \ + (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ +#define GM_RXF_BC_OK \ + (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ +#define GM_RXF_MPAUSE \ + (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ +#define GM_RXF_MC_OK \ + (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ +#define GM_RXF_FCS_ERR \ + (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ + /* GM_MIB_CNT_BASE + 40: reserved */ +#define GM_RXO_OK_LO \ + (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ +#define GM_RXO_OK_HI \ + (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ +#define GM_RXO_ERR_LO \ + (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ +#define GM_RXO_ERR_HI \ + (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ +#define GM_RXF_SHT \ + (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ +#define GM_RXE_FRAG \ + (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Receeived with FCS Err */ +#define GM_RXF_64B \ + (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ +#define GM_RXF_127B \ + (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ +#define GM_RXF_255B \ + (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ +#define GM_RXF_511B \ + (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ +#define GM_RXF_1023B \ + (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ +#define GM_RXF_1518B \ + (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ +#define GM_RXF_MAX_SZ \ + (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ +#define GM_RXF_LNG_ERR \ + (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ +#define GM_RXF_JAB_PKT \ + (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ + /* GM_MIB_CNT_BASE + 168: reserved */ +#define GM_RXE_FIFO_OV \ + (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ + /* GM_MIB_CNT_BASE + 184: reserved */ +#define GM_TXF_UC_OK \ + (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ +#define GM_TXF_BC_OK \ + (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ +#define GM_TXF_MPAUSE \ + (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ +#define GM_TXF_MC_OK \ + (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ +#define GM_TXO_OK_LO \ + (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ +#define GM_TXO_OK_HI \ + (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ +#define GM_TXF_64B \ + (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ +#define GM_TXF_127B \ + (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ +#define GM_TXF_255B \ + (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ +#define GM_TXF_511B \ + (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ +#define GM_TXF_1023B \ + (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ +#define GM_TXF_1518B \ + (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ +#define GM_TXF_MAX_SZ \ + (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ + /* GM_MIB_CNT_BASE + 296: reserved */ +#define GM_TXF_COL \ + (GM_MIB_CNT_BASE + 304) /* Tx Collision */ +#define GM_TXF_LAT_COL \ + (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ +#define GM_TXF_ABO_COL \ + (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ +#define GM_TXF_MUL_COL \ + (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ +#define GM_TXF_SNG_COL \ + (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ +#define GM_TXE_FIFO_UR \ + (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ + +/*----------------------------------------------------------------------------*/ +/* + * GMAC Bit Definitions + * + * If the bit access behaviour differs from the register access behaviour + * (r/w, r/o) this is documented after the bit number. + * The following bit access behaviours are used: + * (sc) self clearing + * (r/o) read only + */ + +/* GM_GP_STAT 16 bit r/o General Purpose Status Register */ + +#define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */ +#define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */ +#define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow Control Mode Disabled */ +#define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */ +#define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */ +#define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */ +#define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */ +#define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */ + /* Bit 7..6: reserved */ +#define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */ +#define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ +#define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */ +#define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow Control Mode Disabled */ +#define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */ + /* Bit 0: reserved */ + +/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ + /* Bit 15: reserved */ +#define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */ +#define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow Control Mode */ +#define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */ +#define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */ +#define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */ +#define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */ +#define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */ +#define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */ +#define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */ +#define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */ +#define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow Control Mode */ +#define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */ +#define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update for Duplex */ +#define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update for Flow-c. */ +#define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update for Speed */ + +#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) +#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ + GM_GPCR_AU_SPD_DIS) + +/* GM_TX_CTRL 16 bit r/w Transmit Control Register */ + +#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */ +#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */ +#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */ +#define GM_TXCR_COL_THR (4<<10) /* Bit 12..10: Collision Threshold */ + +/* GM_RX_CTRL 16 bit r/w Receive Control Register */ +#define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */ +#define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */ +#define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */ +#define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */ + +/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ +#define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */ +#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */ +#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */ + /* Bit 3..0: reserved */ +#define JAM_LEN_VAL(x) SHIFT14(x) +#define JAM_IPG_VAL(x) SHIFT9(x) +#define IPG_JAM_DATA(x) SHIFT4(x) + +/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ +#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ +#define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive transmit trials */ +#define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Length) */ +#define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Length) */ + /* Bit 7..5: reserved */ +#define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ + +#define DATA_BLIND_VAL(x) SHIFT11(x) +#define DATA_BLIND_FAST_ETH 0x1c +#define DATA_BLIND_GIGABIT 4 + +#define IPG_VAL_FAST_ETH 0x1e +#define IPG_VAL_GIGABIT 6 + +/* GM_SMI_CTRL 16 bit r/w SMI Control Register */ + +#define GM_SMI_CT_PHY_AD(x) SHIFT11(x) +#define GM_SMI_CT_REG_AD(x) SHIFT6(x) +#define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/ +#define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */ +#define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */ + /* Bit 2..0: reserved */ + +/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ + /* Bit 15..6: reserved */ +#define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */ +#define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */ + /* Bit 3..0: reserved */ + +/* Receive Frame Status Encoding */ +#define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */ + /* Bit 15..14: reserved */ +#define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */ +#define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */ +#define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */ +#define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */ +#define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */ +#define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */ +#define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */ +#define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */ +#define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */ +#define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */ +#define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */ + /* Bit 2: reserved */ +#define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */ +#define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */ + +/* + * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR) + */ +#define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \ + GMR_FS_LONG_ERR | \ + GMR_FS_MII_ERR | \ + GMR_FS_BAD_FC | \ + GMR_FS_GOOD_FC | \ + GMR_FS_JABBER) + +/* Rx GMAC FIFO Flush Mask (default) */ +#define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \ + GMR_FS_RX_FF_OV | \ + GMR_FS_MII_ERR | \ + GMR_FS_BAD_FC | \ + GMR_FS_GOOD_FC | \ + GMR_FS_UN_SIZE | \ + GMR_FS_JABBER) + +/* typedefs *******************************************************************/ + + +/* function prototypes ********************************************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_XMAC_H */ diff --git a/drivers/sk98lin/skaddr.c b/drivers/sk98lin/skaddr.c new file mode 100644 index 0000000..ed79c04 --- /dev/null +++ b/drivers/sk98lin/skaddr.c @@ -0,0 +1,1879 @@ +/****************************************************************************** + * + * Name: skaddr.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.48 $ + * Date: $Date: 2003/02/12 17:09:37 $ + * Purpose: Manage Addresses (Multicast and Unicast) and Promiscuous Mode. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skaddr.c,v $ + * Revision 1.48 2003/02/12 17:09:37 tschilli + * Fix in SkAddrOverride() to set both (physical and logical) MAC addresses + * in case that both addresses are identical. + * + * Revision 1.47 2002/09/17 06:31:10 tschilli + * Handling of SK_PROM_MODE_ALL_MC flag in SkAddrGmacMcUpdate() + * and SkAddrGmacPromiscuousChange() fixed. + * Editorial changes. + * + * Revision 1.46 2002/08/22 07:55:41 tschilli + * New function SkGmacMcHash() for GMAC multicast hashing algorithm added. + * Editorial changes. + * + * Revision 1.45 2002/08/15 12:29:35 tschilli + * SkAddrGmacMcUpdate() and SkAddrGmacPromiscuousChange() changed. + * + * Revision 1.44 2002/08/14 12:18:03 rschmidt + * Replaced direct handling of MAC Hashing (XMAC and GMAC) + * with routine SkMacHashing(). + * Replaced wrong 3rd para 'i' with 'PortNumber' in SkMacPromiscMode(). + * + * Revision 1.43 2002/08/13 09:37:43 rschmidt + * Corrected some SK_DBG_MSG outputs. + * Replaced wrong 2nd para pAC with IoC in SkMacPromiscMode(). + * Editorial changes. + * + * Revision 1.42 2002/08/12 11:24:36 rschmidt + * Remove setting of logical MAC address GM_SRC_ADDR_2 in SkAddrInit(). + * Replaced direct handling of MAC Promiscuous Mode (XMAC and GMAC) + * with routine SkMacPromiscMode(). + * Editorial changes. + * + * Revision 1.41 2002/06/10 13:52:18 tschilli + * Changes for handling YUKON. + * All changes are internally and not visible to the programmer + * using this module. + * + * Revision 1.40 2001/02/14 14:04:59 rassmann + * Editorial changes. + * + * Revision 1.39 2001/01/30 10:30:04 rassmann + * Editorial changes. + * + * Revision 1.38 2001/01/25 16:26:52 rassmann + * Ensured that logical address overrides are done on net's active port. + * + * Revision 1.37 2001/01/22 13:41:34 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.36 2000/08/07 11:10:39 rassmann + * Editorial changes. + * + * Revision 1.35 2000/05/04 09:38:41 rassmann + * Editorial changes. + * Corrected multicast address hashing. + * + * Revision 1.34 1999/11/22 13:23:44 cgoos + * Changed license header to GPL. + * + * Revision 1.33 1999/05/28 10:56:06 rassmann + * Editorial changes. + * + * Revision 1.32 1999/03/31 10:59:20 rassmann + * Returning Success instead of DupAddr if address shall be overridden + * with same value. + * + * Revision 1.31 1999/01/14 16:18:17 rassmann + * Corrected multicast initialization. + * + * Revision 1.30 1999/01/04 10:30:35 rassmann + * SkAddrOverride only possible after SK_INIT_IO phase. + * + * Revision 1.29 1998/12/29 13:13:10 rassmann + * An address override is now preserved in the SK_INIT_IO phase. + * All functions return an int now. + * Extended parameter checking. + * + * Revision 1.28 1998/12/01 11:45:53 rassmann + * Code cleanup. + * + * Revision 1.27 1998/12/01 09:22:49 rassmann + * SkAddrMcAdd and SkAddrMcUpdate returned SK_MC_FILTERING_INEXACT + * too often. + * + * Revision 1.26 1998/11/24 12:39:44 rassmann + * Reserved multicast entry for BPDU address. + * 13 multicast entries left for protocol. + * + * Revision 1.25 1998/11/17 16:54:23 rassmann + * Using exact match for up to 14 multicast addresses. + * Still receiving all multicasts if more addresses are added. + * + * Revision 1.24 1998/11/13 17:24:31 rassmann + * Changed return value of SkAddrOverride to int. + * + * Revision 1.23 1998/11/13 16:56:18 rassmann + * Added macro SK_ADDR_COMPARE. + * Changed return type of SkAddrOverride to SK_BOOL. + * + * Revision 1.22 1998/11/04 17:06:17 rassmann + * Corrected McUpdate and PromiscuousChange functions. + * + * Revision 1.21 1998/10/29 14:34:04 rassmann + * Clearing SK_ADDR struct at startup. + * + * Revision 1.20 1998/10/28 18:16:34 rassmann + * Avoiding I/Os before SK_INIT_RUN level. + * Aligning InexactFilter. + * + * Revision 1.19 1998/10/28 11:29:28 rassmann + * Programming physical address in SkAddrMcUpdate. + * Corrected programming of exact match entries. + * + * Revision 1.18 1998/10/28 10:34:48 rassmann + * Corrected reading of physical addresses. + * + * Revision 1.17 1998/10/28 10:26:13 rassmann + * Getting ports' current MAC addresses from EPROM now. + * Added debug output. + * + * Revision 1.16 1998/10/27 16:20:12 rassmann + * Reading MAC address byte by byte. + * + * Revision 1.15 1998/10/22 11:39:09 rassmann + * Corrected signed/unsigned mismatches. + * + * Revision 1.14 1998/10/19 17:12:35 rassmann + * Syntax corrections. + * + * Revision 1.13 1998/10/19 17:02:19 rassmann + * Now reading permanent MAC addresses from CRF. + * + * Revision 1.12 1998/10/15 15:15:48 rassmann + * Changed Flags Parameters from SK_U8 to int. + * Checked with lint. + * + * Revision 1.11 1998/09/24 19:15:12 rassmann + * Code cleanup. + * + * Revision 1.10 1998/09/18 20:18:54 rassmann + * Added HW access. + * Implemented swapping. + * + * Revision 1.9 1998/09/16 11:32:00 rassmann + * Including skdrv1st.h again. :( + * + * Revision 1.8 1998/09/16 11:09:34 rassmann + * Syntax corrections. + * + * Revision 1.7 1998/09/14 17:06:34 rassmann + * Minor changes. + * + * Revision 1.6 1998/09/07 08:45:41 rassmann + * Syntax corrections. + * + * Revision 1.5 1998/09/04 19:40:19 rassmann + * Interface enhancements. + * + * Revision 1.4 1998/09/04 12:14:12 rassmann + * Interface cleanup. + * + * Revision 1.3 1998/09/02 16:56:40 rassmann + * Updated interface. + * + * Revision 1.2 1998/08/27 14:26:09 rassmann + * Updated interface. + * + * Revision 1.1 1998/08/21 08:30:22 rassmann + * First public version. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This module is intended to manage multicast addresses, address override, + * and promiscuous mode on GEnesis and Yukon adapters. + * + * Address Layout: + * port address: physical MAC address + * 1st exact match: logical MAC address (GEnesis only) + * 2nd exact match: RLMT multicast (GEnesis only) + * exact match 3-13: OS-specific multicasts (GEnesis only) + * + * Include File Hierarchy: + * + * "skdrv1st.h" + * "skdrv2nd.h" + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#ifndef lint +static const char SysKonnectFileId[] = + "@(#) $Id: skaddr.c,v 1.48 2003/02/12 17:09:37 tschilli Exp $ (C) SysKonnect."; +#endif /* !defined(lint) */ + +#define __SKADDR_C + +#ifdef __cplusplus +#error C++ is not yet supported. +extern "C" { +#endif /* cplusplus */ + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/* defines ********************************************************************/ + + +#define XMAC_POLY 0xEDB88320UL /* CRC32-Poly - XMAC: Little Endian */ +#define GMAC_POLY 0x04C11DB7L /* CRC16-Poly - GMAC: Little Endian */ +#define HASH_BITS 6 /* #bits in hash */ +#define SK_MC_BIT 0x01 + +/* Error numbers and messages. */ + +#define SKERR_ADDR_E001 (SK_ERRBASE_ADDR + 0) +#define SKERR_ADDR_E001MSG "Bad Flags." +#define SKERR_ADDR_E002 (SKERR_ADDR_E001 + 1) +#define SKERR_ADDR_E002MSG "New Error." + +/* typedefs *******************************************************************/ + +/* None. */ + +/* global variables ***********************************************************/ + +/* 64-bit hash values with all bits set. */ + +SK_U16 OnesHash[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF}; + +/* local variables ************************************************************/ + +#ifdef DEBUG +static int Next0[SK_MAX_MACS] = {0, 0}; +#endif /* DEBUG */ + +/* functions ******************************************************************/ + +/****************************************************************************** + * + * SkAddrInit - initialize data, set state to init + * + * Description: + * + * SK_INIT_DATA + * ============ + * + * This routine clears the multicast tables and resets promiscuous mode. + * Some entries are reserved for the "logical MAC address", the + * SK-RLMT multicast address, and the BPDU multicast address. + * + * + * SK_INIT_IO + * ========== + * + * All permanent MAC addresses are read from EPROM. + * If the current MAC addresses are not already set in software, + * they are set to the values of the permanent addresses. + * The current addresses are written to the corresponding MAC. + * + * + * SK_INIT_RUN + * =========== + * + * Nothing. + * + * Context: + * init, pageable + * + * Returns: + * SK_ADDR_SUCCESS + */ +int SkAddrInit( +SK_AC *pAC, /* the adapter context */ +SK_IOC IoC, /* I/O context */ +int Level) /* initialization level */ +{ + int j; + SK_U32 i; + SK_U8 *InAddr; + SK_U16 *OutAddr; + SK_ADDR_PORT *pAPort; + + switch (Level) { + case SK_INIT_DATA: + SK_MEMSET((char *) &pAC->Addr, 0, sizeof(SK_ADDR)); + + for (i = 0; i < SK_MAX_MACS; i++) { + pAPort = &pAC->Addr.Port[i]; + pAPort->PromMode = SK_PROM_MODE_NONE; + + pAPort->FirstExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT; + pAPort->FirstExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV; + pAPort->NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT; + pAPort->NextExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV; + } +#ifdef xDEBUG + for (i = 0; i < SK_MAX_MACS; i++) { + if (pAC->Addr.Port[i].NextExactMatchRlmt < + SK_ADDR_FIRST_MATCH_RLMT) { + Next0[i] |= 4; + } + } +#endif /* DEBUG */ + /* pAC->Addr.InitDone = SK_INIT_DATA; */ + break; + + case SK_INIT_IO: + for (i = 0; i < SK_MAX_NETS; i++) { + pAC->Addr.Net[i].ActivePort = pAC->Rlmt.Net[i].ActivePort; + } +#ifdef xDEBUG + for (i = 0; i < SK_MAX_MACS; i++) { + if (pAC->Addr.Port[i].NextExactMatchRlmt < + SK_ADDR_FIRST_MATCH_RLMT) { + Next0[i] |= 8; + } + } +#endif /* DEBUG */ + + /* Read permanent logical MAC address from Control Register File. */ + for (j = 0; j < SK_MAC_ADDR_LEN; j++) { + InAddr = (SK_U8 *) &pAC->Addr.Net[0].PermanentMacAddress.a[j]; + SK_IN8(IoC, B2_MAC_1 + j, InAddr); + } + + if (!pAC->Addr.Net[0].CurrentMacAddressSet) { + /* Set the current logical MAC address to the permanent one. */ + pAC->Addr.Net[0].CurrentMacAddress = + pAC->Addr.Net[0].PermanentMacAddress; + pAC->Addr.Net[0].CurrentMacAddressSet = SK_TRUE; + } + + /* Set the current logical MAC address. */ + pAC->Addr.Port[pAC->Addr.Net[0].ActivePort].Exact[0] = + pAC->Addr.Net[0].CurrentMacAddress; +#if SK_MAX_NETS > 1 + /* Set logical MAC address for net 2 to (log | 3). */ + if (!pAC->Addr.Net[1].CurrentMacAddressSet) { + pAC->Addr.Net[1].PermanentMacAddress = + pAC->Addr.Net[0].PermanentMacAddress; + pAC->Addr.Net[1].PermanentMacAddress.a[5] |= 3; + /* Set the current logical MAC address to the permanent one. */ + pAC->Addr.Net[1].CurrentMacAddress = + pAC->Addr.Net[1].PermanentMacAddress; + pAC->Addr.Net[1].CurrentMacAddressSet = SK_TRUE; + } +#endif /* SK_MAX_NETS > 1 */ + +#ifdef DEBUG + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, + ("Permanent MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n", + i, + pAC->Addr.Net[i].PermanentMacAddress.a[0], + pAC->Addr.Net[i].PermanentMacAddress.a[1], + pAC->Addr.Net[i].PermanentMacAddress.a[2], + pAC->Addr.Net[i].PermanentMacAddress.a[3], + pAC->Addr.Net[i].PermanentMacAddress.a[4], + pAC->Addr.Net[i].PermanentMacAddress.a[5])) + + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, + ("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n", + i, + pAC->Addr.Net[i].CurrentMacAddress.a[0], + pAC->Addr.Net[i].CurrentMacAddress.a[1], + pAC->Addr.Net[i].CurrentMacAddress.a[2], + pAC->Addr.Net[i].CurrentMacAddress.a[3], + pAC->Addr.Net[i].CurrentMacAddress.a[4], + pAC->Addr.Net[i].CurrentMacAddress.a[5])) + } +#endif /* DEBUG */ + + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + pAPort = &pAC->Addr.Port[i]; + + /* Read permanent port addresses from Control Register File. */ + for (j = 0; j < SK_MAC_ADDR_LEN; j++) { + InAddr = (SK_U8 *) &pAPort->PermanentMacAddress.a[j]; + SK_IN8(IoC, B2_MAC_2 + 8 * i + j, InAddr); + } + + if (!pAPort->CurrentMacAddressSet) { + /* + * Set the current and previous physical MAC address + * of this port to its permanent MAC address. + */ + pAPort->CurrentMacAddress = pAPort->PermanentMacAddress; + pAPort->PreviousMacAddress = pAPort->PermanentMacAddress; + pAPort->CurrentMacAddressSet = SK_TRUE; + } + + /* Set port's current physical MAC address. */ + OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0]; + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + XM_OUTADDR(IoC, i, XM_SA, OutAddr); + } + else { + GM_OUTADDR(IoC, i, GM_SRC_ADDR_1L, OutAddr); + } +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, + ("SkAddrInit: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAPort->PermanentMacAddress.a[0], + pAPort->PermanentMacAddress.a[1], + pAPort->PermanentMacAddress.a[2], + pAPort->PermanentMacAddress.a[3], + pAPort->PermanentMacAddress.a[4], + pAPort->PermanentMacAddress.a[5])) + + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, + ("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAPort->CurrentMacAddress.a[0], + pAPort->CurrentMacAddress.a[1], + pAPort->CurrentMacAddress.a[2], + pAPort->CurrentMacAddress.a[3], + pAPort->CurrentMacAddress.a[4], + pAPort->CurrentMacAddress.a[5])) +#endif /* DEBUG */ + } + /* pAC->Addr.InitDone = SK_INIT_IO; */ + break; + + case SK_INIT_RUN: +#ifdef xDEBUG + for (i = 0; i < SK_MAX_MACS; i++) { + if (pAC->Addr.Port[i].NextExactMatchRlmt < + SK_ADDR_FIRST_MATCH_RLMT) { + Next0[i] |= 16; + } + } +#endif /* DEBUG */ + + /* pAC->Addr.InitDone = SK_INIT_RUN; */ + break; + + default: /* error */ + break; + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrInit */ + + +/****************************************************************************** + * + * SkAddrMcClear - clear the multicast table + * + * Description: + * This routine clears the multicast table. + * + * If not suppressed by Flag SK_MC_SW_ONLY, the hardware is updated + * immediately. + * + * It calls either SkAddrXmacMcClear or SkAddrGmacMcClear, according + * to the adapter in use. The real work is done there. + * + * Context: + * runtime, pageable + * may be called starting with SK_INIT_DATA with flag SK_MC_SW_ONLY + * may be called after SK_INIT_IO without limitation + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrMcClear( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Index of affected port */ +int Flags) /* permanent/non-perm, sw-only */ +{ + int ReturnCode; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags); + } + else { + ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags); + } + + return (ReturnCode); + +} /* SkAddrMcClear */ + + +/****************************************************************************** + * + * SkAddrXmacMcClear - clear the multicast table + * + * Description: + * This routine clears the multicast table + * (either entry 2 or entries 3-16 and InexactFilter) of the given port. + * If not suppressed by Flag SK_MC_SW_ONLY, the hardware is updated + * immediately. + * + * Context: + * runtime, pageable + * may be called starting with SK_INIT_DATA with flag SK_MC_SW_ONLY + * may be called after SK_INIT_IO without limitation + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrXmacMcClear( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Index of affected port */ +int Flags) /* permanent/non-perm, sw-only */ +{ + int i; + + if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */ + + /* Clear RLMT multicast addresses. */ + pAC->Addr.Port[PortNumber].NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT; + } + else { /* not permanent => DRV */ + + /* Clear InexactFilter */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0; + } + + /* Clear DRV multicast addresses. */ + + pAC->Addr.Port[PortNumber].NextExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV; + } + + if (!(Flags & SK_MC_SW_ONLY)) { + (void) SkAddrXmacMcUpdate(pAC, IoC, PortNumber); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrXmacMcClear */ + + +/****************************************************************************** + * + * SkAddrGmacMcClear - clear the multicast table + * + * Description: + * This routine clears the multicast hashing table (InexactFilter) + * (either the RLMT or the driver bits) of the given port. + * + * If not suppressed by Flag SK_MC_SW_ONLY, the hardware is updated + * immediately. + * + * Context: + * runtime, pageable + * may be called starting with SK_INIT_DATA with flag SK_MC_SW_ONLY + * may be called after SK_INIT_IO without limitation + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrGmacMcClear( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Index of affected port */ +int Flags) /* permanent/non-perm, sw-only */ +{ + int i; + +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("GMAC InexactFilter (not cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[1], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[2], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[3], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])) +#endif /* DEBUG */ + + /* Clear InexactFilter */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0; + } + + if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */ + + /* Copy DRV bits to InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i]; + + /* Clear InexactRlmtFilter. */ + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0; + + } + } + else { /* not permanent => DRV */ + + /* Copy RLMT bits to InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i]; + + /* Clear InexactDrvFilter. */ + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i] = 0; + } + } + +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("GMAC InexactFilter (cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[1], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[2], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[3], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])) +#endif /* DEBUG */ + + if (!(Flags & SK_MC_SW_ONLY)) { + (void) SkAddrGmacMcUpdate(pAC, IoC, PortNumber); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrGmacMcClear */ + +#ifndef SK_ADDR_CHEAT + +/****************************************************************************** + * + * SkXmacMcHash - hash multicast address + * + * Description: + * This routine computes the hash value for a multicast address. + * A CRC32 algorithm is used. + * + * Notes: + * The code was adapted from the XaQti data sheet. + * + * Context: + * runtime, pageable + * + * Returns: + * Hash value of multicast address. + */ +SK_U32 SkXmacMcHash( +unsigned char *pMc) /* Multicast address */ +{ + SK_U32 Idx; + SK_U32 Bit; + SK_U32 Data; + SK_U32 Crc; + + Crc = 0xFFFFFFFFUL; + for (Idx = 0; Idx < SK_MAC_ADDR_LEN; Idx++) { + Data = *pMc++; + for (Bit = 0; Bit < 8; Bit++, Data >>= 1) { + Crc = (Crc >> 1) ^ (((Crc ^ Data) & 1) ? XMAC_POLY : 0); + } + } + + return (Crc & ((1 << HASH_BITS) - 1)); + +} /* SkXmacMcHash */ + + +/****************************************************************************** + * + * SkGmacMcHash - hash multicast address + * + * Description: + * This routine computes the hash value for a multicast address. + * A CRC16 algorithm is used. + * + * Notes: + * + * + * Context: + * runtime, pageable + * + * Returns: + * Hash value of multicast address. + */ +SK_U32 SkGmacMcHash( +unsigned char *pMc) /* Multicast address */ +{ + SK_U32 Data; + SK_U32 TmpData; + SK_U32 Crc; + int Byte; + int Bit; + + Crc = 0xFFFFFFFFUL; + for (Byte = 0; Byte < 6; Byte++) { + /* Get next byte. */ + Data = (SK_U32) pMc[Byte]; + + /* Change bit order in byte. */ + TmpData = Data; + for (Bit = 0; Bit < 8; Bit++) { + if (TmpData & 1L) { + Data |= 1L << (7 - Bit); + } + else { + Data &= ~(1L << (7 - Bit)); + } + TmpData >>= 1; + } + + Crc ^= (Data << 24); + for (Bit = 0; Bit < 8; Bit++) { + if (Crc & 0x80000000) { + Crc = (Crc << 1) ^ GMAC_POLY; + } + else { + Crc <<= 1; + } + } + } + + return (Crc & ((1 << HASH_BITS) - 1)); + +} /* SkGmacMcHash */ + +#endif /* not SK_ADDR_CHEAT */ + +/****************************************************************************** + * + * SkAddrMcAdd - add a multicast address to a port + * + * Description: + * This routine enables reception for a given address on the given port. + * + * It calls either SkAddrXmacMcAdd or SkAddrGmacMcAdd, according to the + * adapter in use. The real work is done there. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_DATA + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_MC_ILLEGAL_ADDRESS + * SK_MC_ILLEGAL_PORT + * SK_MC_RLMT_OVERFLOW + */ +int SkAddrMcAdd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Port Number */ +SK_MAC_ADDR *pMc, /* multicast address to be added */ +int Flags) /* permanent/non-permanent */ +{ + int ReturnCode; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags); + } + else { + ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags); + } + + return (ReturnCode); + +} /* SkAddrMcAdd */ + + +/****************************************************************************** + * + * SkAddrXmacMcAdd - add a multicast address to a port + * + * Description: + * This routine enables reception for a given address on the given port. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * The multicast bit is only checked if there are no free exact match + * entries. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_DATA + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_MC_ILLEGAL_ADDRESS + * SK_MC_RLMT_OVERFLOW + */ +int SkAddrXmacMcAdd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Port Number */ +SK_MAC_ADDR *pMc, /* multicast address to be added */ +int Flags) /* permanent/non-permanent */ +{ + int i; + SK_U8 Inexact; +#ifndef SK_ADDR_CHEAT + SK_U32 HashBit; +#endif /* !defined(SK_ADDR_CHEAT) */ + + if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */ +#ifdef xDEBUG + if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt < + SK_ADDR_FIRST_MATCH_RLMT) { + Next0[PortNumber] |= 1; + return (SK_MC_RLMT_OVERFLOW); + } +#endif /* DEBUG */ + + if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt > + SK_ADDR_LAST_MATCH_RLMT) { + return (SK_MC_RLMT_OVERFLOW); + } + + /* Set a RLMT multicast address. */ + + pAC->Addr.Port[PortNumber].Exact[ + pAC->Addr.Port[PortNumber].NextExactMatchRlmt++] = *pMc; + + return (SK_MC_FILTERING_EXACT); + } + +#ifdef xDEBUG + if (pAC->Addr.Port[PortNumber].NextExactMatchDrv < + SK_ADDR_FIRST_MATCH_DRV) { + Next0[PortNumber] |= 2; + return (SK_MC_RLMT_OVERFLOW); + } +#endif /* DEBUG */ + + if (pAC->Addr.Port[PortNumber].NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) { + + /* Set exact match entry. */ + pAC->Addr.Port[PortNumber].Exact[ + pAC->Addr.Port[PortNumber].NextExactMatchDrv++] = *pMc; + + /* Clear InexactFilter */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0; + } + } + else { + if (!(pMc->a[0] & SK_MC_BIT)) { + /* Hashing only possible with multicast addresses. */ + return (SK_MC_ILLEGAL_ADDRESS); + } +#ifndef SK_ADDR_CHEAT + /* Compute hash value of address. */ + HashBit = 63 - SkXmacMcHash(&pMc->a[0]); + + /* Add bit to InexactFilter. */ + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[HashBit / 8] |= + 1 << (HashBit % 8); +#else /* SK_ADDR_CHEAT */ + /* Set all bits in InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF; + } +#endif /* SK_ADDR_CHEAT */ + } + + for (Inexact = 0, i = 0; i < 8; i++) { + Inexact |= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i]; + } + + if (Inexact == 0 && pAC->Addr.Port[PortNumber].PromMode == 0) { + return (SK_MC_FILTERING_EXACT); + } + else { + return (SK_MC_FILTERING_INEXACT); + } + +} /* SkAddrXmacMcAdd */ + + +/****************************************************************************** + * + * SkAddrGmacMcAdd - add a multicast address to a port + * + * Description: + * This routine enables reception for a given address on the given port. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_DATA + * + * Returns: + * SK_MC_FILTERING_INEXACT + * SK_MC_ILLEGAL_ADDRESS + */ +int SkAddrGmacMcAdd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Port Number */ +SK_MAC_ADDR *pMc, /* multicast address to be added */ +int Flags) /* permanent/non-permanent */ +{ + int i; +#ifndef SK_ADDR_CHEAT + SK_U32 HashBit; +#endif /* !defined(SK_ADDR_CHEAT) */ + + if (!(pMc->a[0] & SK_MC_BIT)) { + /* Hashing only possible with multicast addresses. */ + return (SK_MC_ILLEGAL_ADDRESS); + } + +#ifndef SK_ADDR_CHEAT + + /* Compute hash value of address. */ + HashBit = SkGmacMcHash(&pMc->a[0]); + + if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */ + + /* Add bit to InexactRlmtFilter. */ + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[HashBit / 8] |= + 1 << (HashBit % 8); + + /* Copy bit to InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i]; + } +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("GMAC InexactRlmtFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[0], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[1], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[2], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[3], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7])) +#endif /* DEBUG */ + } + else { /* not permanent => DRV */ + + /* Add bit to InexactDrvFilter. */ + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[HashBit / 8] |= + 1 << (HashBit % 8); + + /* Copy bit to InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i]; + } +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("GMAC InexactDrvFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[0], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[1], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[2], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[3], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7])) +#endif /* DEBUG */ + } + +#else /* SK_ADDR_CHEAT */ + + /* Set all bits in InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF; + } +#endif /* SK_ADDR_CHEAT */ + + return (SK_MC_FILTERING_INEXACT); + +} /* SkAddrGmacMcAdd */ + + +/****************************************************************************** + * + * SkAddrMcUpdate - update the HW MC address table and set the MAC address + * + * Description: + * This routine enables reception of the addresses contained in a local + * table for a given port. + * It also programs the port's current physical MAC address. + * + * It calls either SkAddrXmacMcUpdate or SkAddrGmacMcUpdate, according + * to the adapter in use. The real work is done there. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrMcUpdate( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber) /* Port Number */ +{ + int ReturnCode; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ReturnCode = SkAddrXmacMcUpdate(pAC, IoC, PortNumber); + } + else { + ReturnCode = SkAddrGmacMcUpdate(pAC, IoC, PortNumber); + } + + return (ReturnCode); + +} /* SkAddrMcUpdate */ + + +/****************************************************************************** + * + * SkAddrXmacMcUpdate - update the HW MC address table and set the MAC address + * + * Description: + * This routine enables reception of the addresses contained in a local + * table for a given port. + * It also programs the port's current physical MAC address. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrXmacMcUpdate( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber) /* Port Number */ +{ + SK_U32 i; + SK_U8 Inexact; + SK_U16 *OutAddr; + SK_ADDR_PORT *pAPort; + + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber)) + + pAPort = &pAC->Addr.Port[PortNumber]; + +#ifdef DEBUG + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])) +#endif /* DEBUG */ + + /* Start with 0 to also program the logical MAC address. */ + for (i = 0; i < pAPort->NextExactMatchRlmt; i++) { + /* Set exact match address i on XMAC */ + OutAddr = (SK_U16 *) &pAPort->Exact[i].a[0]; + XM_OUTADDR(IoC, PortNumber, XM_EXM(i), OutAddr); + } + + /* Clear other permanent exact match addresses on XMAC */ + if (pAPort->NextExactMatchRlmt <= SK_ADDR_LAST_MATCH_RLMT) { + + SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchRlmt, + SK_ADDR_LAST_MATCH_RLMT); + } + + for (i = pAPort->FirstExactMatchDrv; i < pAPort->NextExactMatchDrv; i++) { + OutAddr = (SK_U16 *) &pAPort->Exact[i].a[0]; + XM_OUTADDR(IoC, PortNumber, XM_EXM(i), OutAddr); + } + + /* Clear other non-permanent exact match addresses on XMAC */ + if (pAPort->NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) { + + SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchDrv, + SK_ADDR_LAST_MATCH_DRV); + } + + for (Inexact = 0, i = 0; i < 8; i++) { + Inexact |= pAPort->InexactFilter.Bytes[i]; + } + + if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) { + + /* Set all bits in 64-bit hash register. */ + XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + else if (Inexact != 0) { + + /* Set 64-bit hash register to InexactFilter. */ + XM_OUTHASH(IoC, PortNumber, XM_HSM, &pAPort->InexactFilter.Bytes[0]); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + else { + /* Disable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_FALSE); + } + + if (pAPort->PromMode != SK_PROM_MODE_NONE) { + (void) SkAddrXmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode); + } + + /* Set port's current physical MAC address. */ + OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0]; + + XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr); + +#ifdef xDEBUG + for (i = 0; i < pAPort->NextExactMatchRlmt; i++) { + SK_U8 InAddr8[6]; + SK_U16 *InAddr; + + /* Get exact match address i from port PortNumber. */ + InAddr = (SK_U16 *) &InAddr8[0]; + + XM_INADDR(IoC, PortNumber, XM_EXM(i), InAddr); + + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrXmacMcUpdate: MC address %d on Port %u: ", + "%02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x\n", + i, + PortNumber, + InAddr8[0], + InAddr8[1], + InAddr8[2], + InAddr8[3], + InAddr8[4], + InAddr8[5], + pAPort->Exact[i].a[0], + pAPort->Exact[i].a[1], + pAPort->Exact[i].a[2], + pAPort->Exact[i].a[3], + pAPort->Exact[i].a[4], + pAPort->Exact[i].a[5])) + } +#endif /* DEBUG */ + + /* Determine return value. */ + if (Inexact == 0 && pAPort->PromMode == 0) { + return (SK_MC_FILTERING_EXACT); + } + else { + return (SK_MC_FILTERING_INEXACT); + } + +} /* SkAddrXmacMcUpdate */ + + +/****************************************************************************** + * + * SkAddrGmacMcUpdate - update the HW MC address table and set the MAC address + * + * Description: + * This routine enables reception of the addresses contained in a local + * table for a given port. + * It also programs the port's current physical MAC address. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrGmacMcUpdate( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber) /* Port Number */ +{ + SK_U32 i; + SK_U8 Inexact; + SK_U16 *OutAddr; + SK_ADDR_PORT *pAPort; + + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber)) + + pAPort = &pAC->Addr.Port[PortNumber]; + +#ifdef DEBUG + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])) +#endif /* DEBUG */ + + for (Inexact = 0, i = 0; i < 8; i++) { + Inexact |= pAPort->InexactFilter.Bytes[i]; + } + + /* Set 64-bit hash register to InexactFilter. */ + GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, + &pAPort->InexactFilter.Bytes[0]); + + if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) { + + /* Set all bits in 64-bit hash register. */ + GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + else { + /* Enable Hashing. */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + + if (pAPort->PromMode != SK_PROM_MODE_NONE) { + (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode); + } + + /* Set port's current physical MAC address. */ + OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0]; + GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr); + + /* Set port's current logical MAC address. */ + OutAddr = (SK_U16 *) &pAPort->Exact[0].a[0]; + GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_2L, OutAddr); + +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrGmacMcUpdate: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAPort->Exact[0].a[0], + pAPort->Exact[0].a[1], + pAPort->Exact[0].a[2], + pAPort->Exact[0].a[3], + pAPort->Exact[0].a[4], + pAPort->Exact[0].a[5])) + + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAPort->CurrentMacAddress.a[0], + pAPort->CurrentMacAddress.a[1], + pAPort->CurrentMacAddress.a[2], + pAPort->CurrentMacAddress.a[3], + pAPort->CurrentMacAddress.a[4], + pAPort->CurrentMacAddress.a[5])) +#endif /* DEBUG */ + + /* Determine return value. */ + if (Inexact == 0 && pAPort->PromMode == 0) { + return (SK_MC_FILTERING_EXACT); + } + else { + return (SK_MC_FILTERING_INEXACT); + } + +} /* SkAddrGmacMcUpdate */ + + +/****************************************************************************** + * + * SkAddrOverride - override a port's MAC address + * + * Description: + * This routine overrides the MAC address of one port. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS if successful. + * SK_ADDR_DUPLICATE_ADDRESS if duplicate MAC address. + * SK_ADDR_MULTICAST_ADDRESS if multicast or broadcast address. + * SK_ADDR_TOO_EARLY if SK_INIT_IO was not executed before. + */ +int SkAddrOverride( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Port Number */ +SK_MAC_ADDR *pNewAddr, /* new MAC address */ +int Flags) /* logical/physical MAC address */ +{ + SK_EVPARA Para; + SK_U32 NetNumber; + SK_U32 i; + SK_U16 *OutAddr; + + NetNumber = pAC->Rlmt.Port[PortNumber].Net->NetNumber; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pNewAddr != NULL && (pNewAddr->a[0] & SK_MC_BIT) != 0) { + return (SK_ADDR_MULTICAST_ADDRESS); + } + + if (!pAC->Addr.Net[NetNumber].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + + if (Flags & SK_ADDR_SET_LOGICAL) { /* Activate logical MAC address. */ + /* Parameter *pNewAddr is ignored. */ + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (!pAC->Addr.Port[i].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + } + + /* Set PortNumber to number of net's active port. */ + PortNumber = pAC->Rlmt.Net[NetNumber]. + Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber; + + pAC->Addr.Port[PortNumber].Exact[0] = + pAC->Addr.Net[NetNumber].CurrentMacAddress; + + /* Write address to first exact match entry of active port. */ + (void) SkAddrMcUpdate(pAC, IoC, PortNumber); + } + else if (Flags & SK_ADDR_CLEAR_LOGICAL) { + /* Deactivate logical MAC address. */ + /* Parameter *pNewAddr is ignored. */ + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (!pAC->Addr.Port[i].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + } + + /* Set PortNumber to number of net's active port. */ + PortNumber = pAC->Rlmt.Net[NetNumber]. + Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber; + + for (i = 0; i < SK_MAC_ADDR_LEN; i++ ) { + pAC->Addr.Port[PortNumber].Exact[0].a[i] = 0; + } + + /* Write address to first exact match entry of active port. */ + (void) SkAddrMcUpdate(pAC, IoC, PortNumber); + } + else if (Flags & SK_ADDR_PHYSICAL_ADDRESS) { /* Physical MAC address. */ + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) { + return (SK_ADDR_DUPLICATE_ADDRESS); + } + + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (!pAC->Addr.Port[i].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Port[i].CurrentMacAddress.a)) { + if (i == PortNumber) { + return (SK_ADDR_SUCCESS); + } + else { + return (SK_ADDR_DUPLICATE_ADDRESS); + } + } + } + + pAC->Addr.Port[PortNumber].PreviousMacAddress = + pAC->Addr.Port[PortNumber].CurrentMacAddress; + pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr; + + /* Change port's physical MAC address. */ + OutAddr = (SK_U16 *) pNewAddr; + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr); + } + else { + GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr); + } + + /* Report address change to RLMT. */ + Para.Para32[0] = PortNumber; + Para.Para32[0] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para); + } + else { /* Logical MAC address. */ + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) { + return (SK_ADDR_SUCCESS); + } + + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (!pAC->Addr.Port[i].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Port[i].CurrentMacAddress.a)) { + return (SK_ADDR_DUPLICATE_ADDRESS); + } + } + + /* + * In case that the physical and the logical MAC addresses are equal + * we must also change the physical MAC address here. + * In this case we have an adapter which initially was programmed with + * two identical MAC addresses. + */ + if (SK_ADDR_EQUAL(pAC->Addr.Port[PortNumber].CurrentMacAddress.a, + pAC->Addr.Port[PortNumber].Exact[0].a)) { + + pAC->Addr.Port[PortNumber].PreviousMacAddress = + pAC->Addr.Port[PortNumber].CurrentMacAddress; + pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr; + + /* Report address change to RLMT. */ + Para.Para32[0] = PortNumber; + Para.Para32[0] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para); + } + + /* Set PortNumber to number of net's active port. */ + PortNumber = pAC->Rlmt.Net[NetNumber]. + Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber; + + pAC->Addr.Net[NetNumber].CurrentMacAddress = *pNewAddr; + pAC->Addr.Port[PortNumber].Exact[0] = *pNewAddr; +#ifdef DEBUG + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrOverride: Permanent MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[0], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[1], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5])) + + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[0], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[1], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5])) +#endif /* DEBUG */ + + /* Write address to first exact match entry of active port. */ + (void) SkAddrMcUpdate(pAC, IoC, PortNumber); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrOverride */ + + +/****************************************************************************** + * + * SkAddrPromiscuousChange - set promiscuous mode for given port + * + * Description: + * This routine manages promiscuous mode: + * - none + * - all LLC frames + * - all MC frames + * + * It calls either SkAddrXmacPromiscuousChange or + * SkAddrGmacPromiscuousChange, according to the adapter in use. + * The real work is done there. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrPromiscuousChange( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* port whose promiscuous mode changes */ +int NewPromMode) /* new promiscuous mode */ +{ + int ReturnCode; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ReturnCode = SkAddrXmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode); + } + else { + ReturnCode = SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode); + } + + return (ReturnCode); + +} /* SkAddrPromiscuousChange */ + + +/****************************************************************************** + * + * SkAddrXmacPromiscuousChange - set promiscuous mode for given port + * + * Description: + * This routine manages promiscuous mode: + * - none + * - all LLC frames + * - all MC frames + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrXmacPromiscuousChange( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* port whose promiscuous mode changes */ +int NewPromMode) /* new promiscuous mode */ +{ + int i; + SK_BOOL InexactModeBit; + SK_U8 Inexact; + SK_U8 HwInexact; + SK_FILTER64 HwInexactFilter; + SK_U16 LoMode; /* Lower 16 bits of XMAC Mode Register. */ + int CurPromMode = SK_PROM_MODE_NONE; + + /* Read CurPromMode from Hardware. */ + XM_IN16(IoC, PortNumber, XM_MODE, &LoMode); + + if ((LoMode & XM_MD_ENA_PROM) != 0) { + /* Promiscuous mode! */ + CurPromMode |= SK_PROM_MODE_LLC; + } + + for (Inexact = 0xFF, i = 0; i < 8; i++) { + Inexact &= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i]; + } + if (Inexact == 0xFF) { + CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC); + } + else { + /* Get InexactModeBit (bit XM_MD_ENA_HASH in mode register) */ + XM_IN16(IoC, PortNumber, XM_MODE, &LoMode); + + InexactModeBit = (LoMode & XM_MD_ENA_HASH) != 0; + + /* Read 64-bit hash register from XMAC */ + XM_INHASH(IoC, PortNumber, XM_HSM, &HwInexactFilter.Bytes[0]); + + for (HwInexact = 0xFF, i = 0; i < 8; i++) { + HwInexact &= HwInexactFilter.Bytes[i]; + } + + if (InexactModeBit && (HwInexact == 0xFF)) { + CurPromMode |= SK_PROM_MODE_ALL_MC; + } + } + + pAC->Addr.Port[PortNumber].PromMode = NewPromMode; + + if (NewPromMode == CurPromMode) { + return (SK_ADDR_SUCCESS); + } + + if ((NewPromMode & SK_PROM_MODE_ALL_MC) && + !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC. */ + + /* Set all bits in 64-bit hash register. */ + XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + else if ((CurPromMode & SK_PROM_MODE_ALL_MC) && + !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm MC. */ + for (Inexact = 0, i = 0; i < 8; i++) { + Inexact |= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i]; + } + if (Inexact == 0) { + /* Disable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_FALSE); + } + else { + /* Set 64-bit hash register to InexactFilter. */ + XM_OUTHASH(IoC, PortNumber, XM_HSM, + &pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0]); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + } + + if ((NewPromMode & SK_PROM_MODE_LLC) && + !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */ + /* Set the MAC in Promiscuous Mode */ + SkMacPromiscMode(pAC, IoC, PortNumber, SK_TRUE); + } + else if ((CurPromMode & SK_PROM_MODE_LLC) && + !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC. */ + /* Clear Promiscuous Mode */ + SkMacPromiscMode(pAC, IoC, PortNumber, SK_FALSE); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrXmacPromiscuousChange */ + + +/****************************************************************************** + * + * SkAddrGmacPromiscuousChange - set promiscuous mode for given port + * + * Description: + * This routine manages promiscuous mode: + * - none + * - all LLC frames + * - all MC frames + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrGmacPromiscuousChange( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* port whose promiscuous mode changes */ +int NewPromMode) /* new promiscuous mode */ +{ + SK_U16 ReceiveControl; /* GMAC Receive Control Register */ + int CurPromMode = SK_PROM_MODE_NONE; + + /* Read CurPromMode from Hardware. */ + GM_IN16(IoC, PortNumber, GM_RX_CTRL, &ReceiveControl); + + if ((ReceiveControl & (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA)) == 0) { + /* Promiscuous mode! */ + CurPromMode |= SK_PROM_MODE_LLC; + } + + if ((ReceiveControl & GM_RXCR_MCF_ENA) == 0) { + /* All Multicast mode! */ + CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC); + } + + pAC->Addr.Port[PortNumber].PromMode = NewPromMode; + + if (NewPromMode == CurPromMode) { + return (SK_ADDR_SUCCESS); + } + + if ((NewPromMode & SK_PROM_MODE_ALL_MC) && + !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC */ + + /* Set all bits in 64-bit hash register. */ + GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + + if ((CurPromMode & SK_PROM_MODE_ALL_MC) && + !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm. MC */ + + /* Set 64-bit hash register to InexactFilter. */ + GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, + &pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0]); + + /* Enable Hashing. */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + + if ((NewPromMode & SK_PROM_MODE_LLC) && + !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */ + + /* Set the MAC to Promiscuous Mode. */ + SkMacPromiscMode(pAC, IoC, PortNumber, SK_TRUE); + } + else if ((CurPromMode & SK_PROM_MODE_LLC) && + !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC */ + + /* Clear Promiscuous Mode. */ + SkMacPromiscMode(pAC, IoC, PortNumber, SK_FALSE); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrGmacPromiscuousChange */ + + +/****************************************************************************** + * + * SkAddrSwap - swap address info + * + * Description: + * This routine swaps address info of two ports. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrSwap( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 FromPortNumber, /* Port1 Index */ +SK_U32 ToPortNumber) /* Port2 Index */ +{ + int i; + SK_U8 Byte; + SK_MAC_ADDR MacAddr; + SK_U32 DWord; + + if (FromPortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (ToPortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->Rlmt.Port[FromPortNumber].Net != pAC->Rlmt.Port[ToPortNumber].Net) { + return (SK_ADDR_ILLEGAL_PORT); + } + + /* + * Swap: + * - Exact Match Entries (GEnesis and Yukon) + * Yukon uses first entry for the logical MAC + * address (stored in the second GMAC register). + * - FirstExactMatchRlmt (GEnesis only) + * - NextExactMatchRlmt (GEnesis only) + * - FirstExactMatchDrv (GEnesis only) + * - NextExactMatchDrv (GEnesis only) + * - 64-bit filter (InexactFilter) + * - Promiscuous Mode + * of ports. + */ + + for (i = 0; i < SK_ADDR_EXACT_MATCHES; i++) { + MacAddr = pAC->Addr.Port[FromPortNumber].Exact[i]; + pAC->Addr.Port[FromPortNumber].Exact[i] = + pAC->Addr.Port[ToPortNumber].Exact[i]; + pAC->Addr.Port[ToPortNumber].Exact[i] = MacAddr; + } + + for (i = 0; i < 8; i++) { + Byte = pAC->Addr.Port[FromPortNumber].InexactFilter.Bytes[i]; + pAC->Addr.Port[FromPortNumber].InexactFilter.Bytes[i] = + pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i]; + pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i] = Byte; + } + + i = pAC->Addr.Port[FromPortNumber].PromMode; + pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode; + pAC->Addr.Port[ToPortNumber].PromMode = i; + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt; + pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt = + pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt; + pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt = DWord; + + DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt; + pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt = + pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt; + pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt = DWord; + + DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv; + pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv = + pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv; + pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv = DWord; + + DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchDrv; + pAC->Addr.Port[FromPortNumber].NextExactMatchDrv = + pAC->Addr.Port[ToPortNumber].NextExactMatchDrv; + pAC->Addr.Port[ToPortNumber].NextExactMatchDrv = DWord; + } + + /* CAUTION: Solution works if only ports of one adapter are in use. */ + for (i = 0; (SK_U32) i < pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber]. + Net->NetNumber].NumPorts; i++) { + if (pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].Net->NetNumber]. + Port[i]->PortNumber == ToPortNumber) { + pAC->Addr.Net[pAC->Rlmt.Port[ToPortNumber].Net->NetNumber]. + ActivePort = i; + /* 20001207 RA: Was "ToPortNumber;". */ + } + } + + (void) SkAddrMcUpdate(pAC, IoC, FromPortNumber); + (void) SkAddrMcUpdate(pAC, IoC, ToPortNumber); + + return (SK_ADDR_SUCCESS); + +} /* SkAddrSwap */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skcsum.c b/drivers/sk98lin/skcsum.c new file mode 100644 index 0000000..a5dc572 --- /dev/null +++ b/drivers/sk98lin/skcsum.c @@ -0,0 +1,929 @@ +/****************************************************************************** + * + * Name: skcsum.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.10 $ + * Date: $Date: 2002/04/11 10:02:04 $ + * Purpose: Store/verify Internet checksum in send/receive packets. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skcsum.c,v $ + * Revision 1.10 2002/04/11 10:02:04 rwahl + * Fix in SkCsGetSendInfo(): + * - function did not return ProtocolFlags in every case. + * - pseudo header csum calculated wrong for big endian. + * + * Revision 1.9 2001/06/13 07:42:08 gklug + * fix: NetNumber was wrong in CLEAR_STAT event + * add: check for good NetNumber in Clear STAT + * + * Revision 1.8 2001/02/06 11:15:36 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.7 2000/06/29 13:17:05 rassmann + * Corrected reception of a packet with UDP checksum == 0 (which means there + * is no UDP checksum). + * + * Revision 1.6 2000/02/21 12:35:10 cgoos + * Fixed license header comment. + * + * Revision 1.5 2000/02/21 11:05:19 cgoos + * Merged changes back to common source. + * Fixed rx path for BIG ENDIAN architecture. + * + * Revision 1.1 1999/07/26 15:28:12 mkarl + * added return SKCS_STATUS_IP_CSUM_ERROR_UDP and + * SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester + * changed from common source to windows specific source + * therefore restarting with v1.0 + * + * Revision 1.3 1999/05/10 08:39:33 mkarl + * prevent overflows in SKCS_HTON16 + * fixed a bug in pseudo header checksum calculation + * added some comments + * + * Revision 1.2 1998/10/22 11:53:28 swolf + * Now using SK_DBG_MSG. + * + * Revision 1.1 1998/09/01 15:35:41 swolf + * initial revision + * + * 13-May-1998 sw Created. + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#ifdef SK_USE_CSUM /* Check if CSUM is to be used. */ + +#ifndef lint +static const char SysKonnectFileId[] = "@(#)" + "$Id: skcsum.c,v 1.10 2002/04/11 10:02:04 rwahl Exp $" + " (C) SysKonnect."; +#endif /* !lint */ + +/****************************************************************************** + * + * Description: + * + * This is the "GEnesis" common module "CSUM". + * + * This module contains the code necessary to calculate, store, and verify the + * Internet Checksum of IP, TCP, and UDP frames. + * + * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon" + * and is the code name of this SysKonnect project. + * + * Compilation Options: + * + * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an + * empty module. + * + * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id + * definitions. In this case, all SKCS_PROTO_xxx definitions must be made + * external. + * + * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status + * definitions. In this case, all SKCS_STATUS_xxx definitions must be made + * external. + * + * Include File Hierarchy: + * + * "h/skdrv1st.h" + * "h/skcsum.h" + * "h/sktypes.h" + * "h/skqueue.h" + * "h/skdrv2nd.h" + * + ******************************************************************************/ + +#include "h/skdrv1st.h" +#include "h/skcsum.h" +#include "h/skdrv2nd.h" + +/* defines ********************************************************************/ + +/* The size of an Ethernet MAC header. */ +#define SKCS_ETHERNET_MAC_HEADER_SIZE (6+6+2) + +/* The size of the used topology's MAC header. */ +#define SKCS_MAC_HEADER_SIZE SKCS_ETHERNET_MAC_HEADER_SIZE + +/* The size of the IP header without any option fields. */ +#define SKCS_IP_HEADER_SIZE 20 + +/* + * Field offsets within the IP header. + */ + +/* "Internet Header Version" and "Length". */ +#define SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH 0 + +/* "Total Length". */ +#define SKCS_OFS_IP_TOTAL_LENGTH 2 + +/* "Flags" "Fragment Offset". */ +#define SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET 6 + +/* "Next Level Protocol" identifier. */ +#define SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL 9 + +/* Source IP address. */ +#define SKCS_OFS_IP_SOURCE_ADDRESS 12 + +/* Destination IP address. */ +#define SKCS_OFS_IP_DESTINATION_ADDRESS 16 + + +/* + * Field offsets within the UDP header. + */ + +/* UDP checksum. */ +#define SKCS_OFS_UDP_CHECKSUM 6 + +/* IP "Next Level Protocol" identifiers (see RFC 790). */ +#define SKCS_PROTO_ID_TCP 6 /* Transport Control Protocol */ +#define SKCS_PROTO_ID_UDP 17 /* User Datagram Protocol */ + +/* IP "Don't Fragment" bit. */ +#define SKCS_IP_DONT_FRAGMENT SKCS_HTON16(0x4000) + +/* Add a byte offset to a pointer. */ +#define SKCS_IDX(pPtr, Ofs) ((void *) ((char *) (pPtr) + (Ofs))) + +/* + * Macros that convert host to network representation and vice versa, i.e. + * little/big endian conversion on little endian machines only. + */ +#ifdef SK_LITTLE_ENDIAN +#define SKCS_HTON16(Val16) (((unsigned) (Val16) >> 8) | (((Val16) & 0xFF) << 8)) +#endif /* SK_LITTLE_ENDIAN */ +#ifdef SK_BIG_ENDIAN +#define SKCS_HTON16(Val16) (Val16) +#endif /* SK_BIG_ENDIAN */ +#define SKCS_NTOH16(Val16) SKCS_HTON16(Val16) + +/* typedefs *******************************************************************/ + +/* function prototypes ********************************************************/ + +/****************************************************************************** + * + * SkCsGetSendInfo - get checksum information for a send packet + * + * Description: + * Get all checksum information necessary to send a TCP or UDP packet. The + * function checks the IP header passed to it. If the high-level protocol + * is either TCP or UDP the pseudo header checksum is calculated and + * returned. + * + * The function returns the total length of the IP header (including any + * IP option fields), which is the same as the start offset of the IP data + * which in turn is the start offset of the TCP or UDP header. + * + * The function also returns the TCP or UDP pseudo header checksum, which + * should be used as the start value for the hardware checksum calculation. + * (Note that any actual pseudo header checksum can never calculate to + * zero.) + * + * Note: + * There is a bug in the ASIC which may lead to wrong checksums. + * + * Arguments: + * pAc - A pointer to the adapter context struct. + * + * pIpHeader - Pointer to IP header. Must be at least the IP header *not* + * including any option fields, i.e. at least 20 bytes. + * + * Note: This pointer will be used to address 8-, 16-, and 32-bit + * variables with the respective alignment offsets relative to the pointer. + * Thus, the pointer should point to a 32-bit aligned address. If the + * target system cannot address 32-bit variables on non 32-bit aligned + * addresses, then the pointer *must* point to a 32-bit aligned address. + * + * pPacketInfo - A pointer to the packet information structure for this + * packet. Before calling this SkCsGetSendInfo(), the following field must + * be initialized: + * + * ProtocolFlags - Initialize with any combination of + * SKCS_PROTO_XXX bit flags. SkCsGetSendInfo() will only work on + * the protocols specified here. Any protocol(s) not specified + * here will be ignored. + * + * Note: Only one checksum can be calculated in hardware. Thus, if + * SKCS_PROTO_IP is specified in the 'ProtocolFlags', + * SkCsGetSendInfo() must calculate the IP header checksum in + * software. It might be a better idea to have the calling + * protocol stack calculate the IP header checksum. + * + * Returns: N/A + * On return, the following fields in 'pPacketInfo' may or may not have + * been filled with information, depending on the protocol(s) found in the + * packet: + * + * ProtocolFlags - Returns the SKCS_PROTO_XXX bit flags of the protocol(s) + * that were both requested by the caller and actually found in the packet. + * Protocol(s) not specified by the caller and/or not found in the packet + * will have their respective SKCS_PROTO_XXX bit flags reset. + * + * Note: For IP fragments, TCP and UDP packet information is ignored. + * + * IpHeaderLength - The total length in bytes of the complete IP header + * including any option fields is returned here. This is the start offset + * of the IP data, i.e. the TCP or UDP header if present. + * + * IpHeaderChecksum - If IP has been specified in the 'ProtocolFlags', the + * 16-bit Internet Checksum of the IP header is returned here. This value + * is to be stored into the packet's 'IP Header Checksum' field. + * + * PseudoHeaderChecksum - If this is a TCP or UDP packet and if TCP or UDP + * has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum + * of the TCP or UDP pseudo header is returned here. + */ +#if 0 +void SkCsGetSendInfo( +SK_AC *pAc, /* Adapter context struct. */ +void *pIpHeader, /* IP header. */ +SKCS_PACKET_INFO *pPacketInfo, /* Packet information struct. */ +int NetNumber) /* Net number */ +{ + /* Internet Header Version found in IP header. */ + unsigned InternetHeaderVersion; + + /* Length of the IP header as found in IP header. */ + unsigned IpHeaderLength; + + /* Bit field specifiying the desired/found protocols. */ + unsigned ProtocolFlags; + + /* Next level protocol identifier found in IP header. */ + unsigned NextLevelProtocol; + + /* Length of IP data portion. */ + unsigned IpDataLength; + + /* TCP/UDP pseudo header checksum. */ + unsigned long PseudoHeaderChecksum; + + /* Pointer to next level protocol statistics structure. */ + SKCS_PROTO_STATS *NextLevelProtoStats; + + /* Temporary variable. */ + unsigned Tmp; + + Tmp = *(SK_U8 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH); + + /* Get the Internet Header Version (IHV). */ + /* Note: The IHV is stored in the upper four bits. */ + + InternetHeaderVersion = Tmp >> 4; + + /* Check the Internet Header Version. */ + /* Note: We currently only support IP version 4. */ + + if (InternetHeaderVersion != 4) { /* IPv4? */ + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX, + ("Tx: Unknown Internet Header Version %u.\n", + InternetHeaderVersion)); + pPacketInfo->ProtocolFlags = 0; + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++; + return; + } + + /* Get the IP header length (IHL). */ + /* + * Note: The IHL is stored in the lower four bits as the number of + * 4-byte words. + */ + + IpHeaderLength = (Tmp & 0xf) * 4; + pPacketInfo->IpHeaderLength = IpHeaderLength; + + /* Check the IP header length. */ + + /* 04-Aug-1998 sw - Really check the IHL? Necessary? */ + + if (IpHeaderLength < 5*4) { + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX, + ("Tx: Invalid IP Header Length %u.\n", IpHeaderLength)); + pPacketInfo->ProtocolFlags = 0; + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++; + return; + } + + /* This is an IPv4 frame with a header of valid length. */ + + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxOkCts++; + + /* Check if we should calculate the IP header checksum. */ + + ProtocolFlags = pPacketInfo->ProtocolFlags; + + if (ProtocolFlags & SKCS_PROTO_IP) { + pPacketInfo->IpHeaderChecksum = + SkCsCalculateChecksum(pIpHeader, IpHeaderLength); + } + + /* Get the next level protocol identifier. */ + + NextLevelProtocol = + *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL); + + /* + * Check if this is a TCP or UDP frame and if we should calculate the + * TCP/UDP pseudo header checksum. + * + * Also clear all protocol bit flags of protocols not present in the + * frame. + */ + + if ((ProtocolFlags & SKCS_PROTO_TCP) != 0 && + NextLevelProtocol == SKCS_PROTO_ID_TCP) { + /* TCP/IP frame. */ + ProtocolFlags &= SKCS_PROTO_TCP | SKCS_PROTO_IP; + NextLevelProtoStats = + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP]; + } + else if ((ProtocolFlags & SKCS_PROTO_UDP) != 0 && + NextLevelProtocol == SKCS_PROTO_ID_UDP) { + /* UDP/IP frame. */ + ProtocolFlags &= SKCS_PROTO_UDP | SKCS_PROTO_IP; + NextLevelProtoStats = + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP]; + } + else { + /* + * Either not a TCP or UDP frame and/or TCP/UDP processing not + * specified. + */ + pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP; + return; + } + + /* Check if this is an IP fragment. */ + + /* + * Note: An IP fragment has a non-zero "Fragment Offset" field and/or + * the "More Fragments" bit set. Thus, if both the "Fragment Offset" + * and the "More Fragments" are zero, it is *not* a fragment. We can + * easily check both at the same time since they are in the same 16-bit + * word. + */ + + if ((*(SK_U16 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) & + ~SKCS_IP_DONT_FRAGMENT) != 0) { + /* IP fragment; ignore all other protocols. */ + pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP; + NextLevelProtoStats->TxUnableCts++; + return; + } + + /* + * Calculate the TCP/UDP pseudo header checksum. + */ + + /* Get total length of IP header and data. */ + + IpDataLength = + *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH); + + /* Get length of IP data portion. */ + + IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength; + + /* Calculate the sum of all pseudo header fields (16-bit). */ + + PseudoHeaderChecksum = + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_SOURCE_ADDRESS + 0) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_SOURCE_ADDRESS + 2) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_DESTINATION_ADDRESS + 0) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_DESTINATION_ADDRESS + 2) + + (unsigned long) SKCS_HTON16(NextLevelProtocol) + + (unsigned long) SKCS_HTON16(IpDataLength); + + /* Add-in any carries. */ + + SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0); + + /* Add-in any new carry. */ + + SKCS_OC_ADD(pPacketInfo->PseudoHeaderChecksum, PseudoHeaderChecksum, 0); + + pPacketInfo->ProtocolFlags = ProtocolFlags; + NextLevelProtoStats->TxOkCts++; /* Success. */ +} /* SkCsGetSendInfo */ + + +/****************************************************************************** + * + * SkCsGetReceiveInfo - verify checksum information for a received packet + * + * Description: + * Verify a received frame's checksum. The function returns a status code + * reflecting the result of the verification. + * + * Note: + * Before calling this function you have to verify that the frame is + * not padded and Checksum1 and Checksum2 are bigger than 1. + * + * Arguments: + * pAc - Pointer to adapter context struct. + * + * pIpHeader - Pointer to IP header. Must be at least the length in bytes + * of the received IP header including any option fields. For UDP packets, + * 8 additional bytes are needed to access the UDP checksum. + * + * Note: The actual length of the IP header is stored in the lower four + * bits of the first octet of the IP header as the number of 4-byte words, + * so it must be multiplied by four to get the length in bytes. Thus, the + * maximum IP header length is 15 * 4 = 60 bytes. + * + * Checksum1 - The first 16-bit Internet Checksum calculated by the + * hardware starting at the offset returned by SkCsSetReceiveFlags(). + * + * Checksum2 - The second 16-bit Internet Checksum calculated by the + * hardware starting at the offset returned by SkCsSetReceiveFlags(). + * + * Returns: + * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame. + * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error. + * SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame. + * SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame + * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok). + * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame). + * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok). + * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok). + * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok. + * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok. + * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum. + * + * Note: If SKCS_OVERWRITE_STATUS is defined, the SKCS_STATUS_XXX values + * returned here can be defined in some header file by the module using CSUM. + * In this way, the calling module can assign return values for its own needs, + * e.g. by assigning bit flags to the individual protocols. + */ +SKCS_STATUS SkCsGetReceiveInfo( +SK_AC *pAc, /* Adapter context struct. */ +void *pIpHeader, /* IP header. */ +unsigned Checksum1, /* Hardware checksum 1. */ +unsigned Checksum2, /* Hardware checksum 2. */ +int NetNumber) /* Net number */ +{ + /* Internet Header Version found in IP header. */ + unsigned InternetHeaderVersion; + + /* Length of the IP header as found in IP header. */ + unsigned IpHeaderLength; + + /* Length of IP data portion. */ + unsigned IpDataLength; + + /* IP header checksum. */ + unsigned IpHeaderChecksum; + + /* IP header options checksum, if any. */ + unsigned IpOptionsChecksum; + + /* IP data checksum, i.e. TCP/UDP checksum. */ + unsigned IpDataChecksum; + + /* Next level protocol identifier found in IP header. */ + unsigned NextLevelProtocol; + + /* The checksum of the "next level protocol", i.e. TCP or UDP. */ + unsigned long NextLevelProtocolChecksum; + + /* Pointer to next level protocol statistics structure. */ + SKCS_PROTO_STATS *NextLevelProtoStats; + + /* Temporary variable. */ + unsigned Tmp; + + Tmp = *(SK_U8 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH); + + /* Get the Internet Header Version (IHV). */ + /* Note: The IHV is stored in the upper four bits. */ + + InternetHeaderVersion = Tmp >> 4; + + /* Check the Internet Header Version. */ + /* Note: We currently only support IP version 4. */ + + if (InternetHeaderVersion != 4) { /* IPv4? */ + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX, + ("Rx: Unknown Internet Header Version %u.\n", + InternetHeaderVersion)); + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++; + return (SKCS_STATUS_UNKNOWN_IP_VERSION); + } + + /* Get the IP header length (IHL). */ + /* + * Note: The IHL is stored in the lower four bits as the number of + * 4-byte words. + */ + + IpHeaderLength = (Tmp & 0xf) * 4; + + /* Check the IP header length. */ + + /* 04-Aug-1998 sw - Really check the IHL? Necessary? */ + + if (IpHeaderLength < 5*4) { + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX, + ("Rx: Invalid IP Header Length %u.\n", IpHeaderLength)); + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++; + return (SKCS_STATUS_IP_CSUM_ERROR); + } + + /* This is an IPv4 frame with a header of valid length. */ + + /* Get the IP header and data checksum. */ + + IpDataChecksum = Checksum2; + + /* + * The IP header checksum is calculated as follows: + * + * IpHeaderChecksum = Checksum1 - Checksum2 + */ + + SKCS_OC_SUB(IpHeaderChecksum, Checksum1, Checksum2); + + /* Check if any IP header options. */ + + if (IpHeaderLength > SKCS_IP_HEADER_SIZE) { + + /* Get the IP options checksum. */ + + IpOptionsChecksum = SkCsCalculateChecksum( + SKCS_IDX(pIpHeader, SKCS_IP_HEADER_SIZE), + IpHeaderLength - SKCS_IP_HEADER_SIZE); + + /* Adjust the IP header and IP data checksums. */ + + SKCS_OC_ADD(IpHeaderChecksum, IpHeaderChecksum, IpOptionsChecksum); + + SKCS_OC_SUB(IpDataChecksum, IpDataChecksum, IpOptionsChecksum); + } + + /* + * Check if the IP header checksum is ok. + * + * NOTE: We must check the IP header checksum even if the caller just wants + * us to check upper-layer checksums, because we cannot do any further + * processing of the packet without a valid IP checksum. + */ + + /* Get the next level protocol identifier. */ + + NextLevelProtocol = *(SK_U8 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL); + + if (IpHeaderChecksum != 0xFFFF) { + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++; + /* the NDIS tester wants to know the upper level protocol too */ + if (NextLevelProtocol == SKCS_PROTO_ID_TCP) { + return(SKCS_STATUS_IP_CSUM_ERROR_TCP); + } + else if (NextLevelProtocol == SKCS_PROTO_ID_UDP) { + return(SKCS_STATUS_IP_CSUM_ERROR_UDP); + } + return (SKCS_STATUS_IP_CSUM_ERROR); + } + + /* + * Check if this is a TCP or UDP frame and if we should calculate the + * TCP/UDP pseudo header checksum. + * + * Also clear all protocol bit flags of protocols not present in the + * frame. + */ + + if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_TCP) != 0 && + NextLevelProtocol == SKCS_PROTO_ID_TCP) { + /* TCP/IP frame. */ + NextLevelProtoStats = + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP]; + } + else if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_UDP) != 0 && + NextLevelProtocol == SKCS_PROTO_ID_UDP) { + /* UDP/IP frame. */ + NextLevelProtoStats = + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP]; + } + else { + /* + * Either not a TCP or UDP frame and/or TCP/UDP processing not + * specified. + */ + return (SKCS_STATUS_IP_CSUM_OK); + } + + /* Check if this is an IP fragment. */ + + /* + * Note: An IP fragment has a non-zero "Fragment Offset" field and/or + * the "More Fragments" bit set. Thus, if both the "Fragment Offset" + * and the "More Fragments" are zero, it is *not* a fragment. We can + * easily check both at the same time since they are in the same 16-bit + * word. + */ + + if ((*(SK_U16 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) & + ~SKCS_IP_DONT_FRAGMENT) != 0) { + /* IP fragment; ignore all other protocols. */ + NextLevelProtoStats->RxUnableCts++; + return (SKCS_STATUS_IP_FRAGMENT); + } + + /* + * 08-May-2000 ra + * + * From RFC 768 (UDP) + * If the computed checksum is zero, it is transmitted as all ones (the + * equivalent in one's complement arithmetic). An all zero transmitted + * checksum value means that the transmitter generated no checksum (for + * debugging or for higher level protocols that don't care). + */ + + if (NextLevelProtocol == SKCS_PROTO_ID_UDP && + *(SK_U16*)SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) { + + NextLevelProtoStats->RxOkCts++; + + return (SKCS_STATUS_IP_CSUM_OK_NO_UDP); + } + + /* + * Calculate the TCP/UDP checksum. + */ + + /* Get total length of IP header and data. */ + + IpDataLength = + *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH); + + /* Get length of IP data portion. */ + + IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength; + + NextLevelProtocolChecksum = + + /* Calculate the pseudo header checksum. */ + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_SOURCE_ADDRESS + 0) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_SOURCE_ADDRESS + 2) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_DESTINATION_ADDRESS + 0) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_DESTINATION_ADDRESS + 2) + + (unsigned long) SKCS_HTON16(NextLevelProtocol) + + (unsigned long) SKCS_HTON16(IpDataLength) + + + /* Add the TCP/UDP header checksum. */ + + (unsigned long) IpDataChecksum; + + /* Add-in any carries. */ + + SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0); + + /* Add-in any new carry. */ + + SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0); + + /* Check if the TCP/UDP checksum is ok. */ + + if ((unsigned) NextLevelProtocolChecksum == 0xFFFF) { + + /* TCP/UDP checksum ok. */ + + NextLevelProtoStats->RxOkCts++; + + return (NextLevelProtocol == SKCS_PROTO_ID_TCP ? + SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK); + } + + /* TCP/UDP checksum error. */ + + NextLevelProtoStats->RxErrCts++; + + return (NextLevelProtocol == SKCS_PROTO_ID_TCP ? + SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR); +} /* SkCsGetReceiveInfo */ +#endif + + +/****************************************************************************** + * + * SkCsSetReceiveFlags - set checksum receive flags + * + * Description: + * Use this function to set the various receive flags. According to the + * protocol flags set by the caller, the start offsets within received + * packets of the two hardware checksums are returned. These offsets must + * be stored in all receive descriptors. + * + * Arguments: + * pAc - Pointer to adapter context struct. + * + * ReceiveFlags - Any combination of SK_PROTO_XXX flags of the protocols + * for which the caller wants checksum information on received frames. + * + * pChecksum1Offset - The start offset of the first receive descriptor + * hardware checksum to be calculated for received frames is returned + * here. + * + * pChecksum2Offset - The start offset of the second receive descriptor + * hardware checksum to be calculated for received frames is returned + * here. + * + * Returns: N/A + * Returns the two hardware checksum start offsets. + */ +void SkCsSetReceiveFlags( +SK_AC *pAc, /* Adapter context struct. */ +unsigned ReceiveFlags, /* New receive flags. */ +unsigned *pChecksum1Offset, /* Offset for hardware checksum 1. */ +unsigned *pChecksum2Offset, /* Offset for hardware checksum 2. */ +int NetNumber) +{ + /* Save the receive flags. */ + + pAc->Csum.ReceiveFlags[NetNumber] = ReceiveFlags; + + /* First checksum start offset is the IP header. */ + *pChecksum1Offset = SKCS_MAC_HEADER_SIZE; + + /* + * Second checksum start offset is the IP data. Note that this may vary + * if there are any IP header options in the actual packet. + */ + *pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE; +} /* SkCsSetReceiveFlags */ + +#ifndef SkCsCalculateChecksum + +/****************************************************************************** + * + * SkCsCalculateChecksum - calculate checksum for specified data + * + * Description: + * Calculate and return the 16-bit Internet Checksum for the specified + * data. + * + * Arguments: + * pData - Pointer to data for which the checksum shall be calculated. + * Note: The pointer should be aligned on a 16-bit boundary. + * + * Length - Length in bytes of data to checksum. + * + * Returns: + * The 16-bit Internet Checksum for the specified data. + * + * Note: The checksum is calculated in the machine's natural byte order, + * i.e. little vs. big endian. Thus, the resulting checksum is different + * for the same input data on little and big endian machines. + * + * However, when written back to the network packet, the byte order is + * always in correct network order. + */ +unsigned SkCsCalculateChecksum( +void *pData, /* Data to checksum. */ +unsigned Length) /* Length of data. */ +{ + SK_U16 *pU16; /* Pointer to the data as 16-bit words. */ + unsigned long Checksum; /* Checksum; must be at least 32 bits. */ + + /* Sum up all 16-bit words. */ + + pU16 = (SK_U16 *) pData; + for (Checksum = 0; Length > 1; Length -= 2) { + Checksum += *pU16++; + } + + /* If this is an odd number of bytes, add-in the last byte. */ + + if (Length > 0) { +#ifdef SK_BIG_ENDIAN + /* Add the last byte as the high byte. */ + Checksum += ((unsigned) *(SK_U8 *) pU16) << 8; +#else /* !SK_BIG_ENDIAN */ + /* Add the last byte as the low byte. */ + Checksum += *(SK_U8 *) pU16; +#endif /* !SK_BIG_ENDIAN */ + } + + /* Add-in any carries. */ + + SKCS_OC_ADD(Checksum, Checksum, 0); + + /* Add-in any new carry. */ + + SKCS_OC_ADD(Checksum, Checksum, 0); + + /* Note: All bits beyond the 16-bit limit are now zero. */ + + return ((unsigned) Checksum); +} /* SkCsCalculateChecksum */ + +#endif /* SkCsCalculateChecksum */ + +/****************************************************************************** + * + * SkCsEvent - the CSUM event dispatcher + * + * Description: + * This is the event handler for the CSUM module. + * + * Arguments: + * pAc - Pointer to adapter context. + * + * Ioc - I/O context. + * + * Event - Event id. + * + * Param - Event dependent parameter. + * + * Returns: + * The 16-bit Internet Checksum for the specified data. + * + * Note: The checksum is calculated in the machine's natural byte order, + * i.e. little vs. big endian. Thus, the resulting checksum is different + * for the same input data on little and big endian machines. + * + * However, when written back to the network packet, the byte order is + * always in correct network order. + */ +int SkCsEvent( +SK_AC *pAc, /* Pointer to adapter context. */ +SK_IOC Ioc, /* I/O context. */ +SK_U32 Event, /* Event id. */ +SK_EVPARA Param) /* Event dependent parameter. */ +{ + int ProtoIndex; + int NetNumber; + + switch (Event) { + /* + * Clear protocol statistics. + * + * Param - Protocol index, or -1 for all protocols. + * - Net number. + */ + case SK_CSUM_EVENT_CLEAR_PROTO_STATS: + + ProtoIndex = (int)Param.Para32[1]; + NetNumber = (int)Param.Para32[0]; + if (ProtoIndex < 0) { /* Clear for all protocols. */ + if (NetNumber >= 0) { + memset(&pAc->Csum.ProtoStats[NetNumber][0], 0, + sizeof(pAc->Csum.ProtoStats[NetNumber])); + } + } + else { /* Clear for individual protocol. */ + memset(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0, + sizeof(pAc->Csum.ProtoStats[NetNumber][ProtoIndex])); + } + break; + default: + break; + } + return (0); /* Success. */ +} /* SkCsEvent */ + +#endif /* SK_USE_CSUM */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skge.c b/drivers/sk98lin/skge.c new file mode 100644 index 0000000..61a6094 --- /dev/null +++ b/drivers/sk98lin/skge.c @@ -0,0 +1,4864 @@ +/****************************************************************************** + * + * Name: skge.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.46 $ + * Date: $Date: 2003/02/25 14:16:36 $ + * Purpose: The main driver source module + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * Driver for SysKonnect Gigabit Ethernet Server Adapters: + * + * SK-9871 (single link 1000Base-ZX) + * SK-9872 (dual link 1000Base-ZX) + * SK-9861 (single link 1000Base-SX, VF45 Volition Plug) + * SK-9862 (dual link 1000Base-SX, VF45 Volition Plug) + * SK-9841 (single link 1000Base-LX) + * SK-9842 (dual link 1000Base-LX) + * SK-9843 (single link 1000Base-SX) + * SK-9844 (dual link 1000Base-SX) + * SK-9821 (single link 1000Base-T) + * SK-9822 (dual link 1000Base-T) + * SK-9881 (single link 1000Base-SX V2 LC) + * SK-9871 (single link 1000Base-ZX V2) + * SK-9861 (single link 1000Base-SX V2, VF45 Volition Plug) + * SK-9841 (single link 1000Base-LX V2) + * SK-9843 (single link 1000Base-SX V2) + * SK-9821 (single link 1000Base-T V2) + * + * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and + * SysKonnects GEnesis Solaris driver + * Author: Christoph Goos (cgoos@syskonnect.de) + * Mirko Lindner (mlindner@syskonnect.de) + * + * Address all question to: linux@syskonnect.de + * + * The technical manual for the adapters is available from SysKonnect's + * web pages: www.syskonnect.com + * Goto "Support" and search Knowledge Base for "manual". + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skge.c,v $ + * Revision 1.46 2003/02/25 14:16:36 mlindner + * Fix: Copyright statement + * + * Revision 1.45 2003/02/25 13:25:55 mlindner + * Add: Performance improvements + * Add: Support for various vendors + * Fix: Init function + * + * Revision 1.44 2003/01/09 09:25:26 mlindner + * Fix: Remove useless init_module/cleanup_module forward declarations + * + * Revision 1.43 2002/11/29 08:42:41 mlindner + * Fix: Boot message + * + * Revision 1.42 2002/11/28 13:30:23 mlindner + * Add: New frame check + * + * Revision 1.41 2002/11/27 13:55:18 mlindner + * Fix: Drop wrong csum packets + * Fix: Initialize proc_entry after hw check + * + * Revision 1.40 2002/10/31 07:50:37 tschilli + * Function SkGeInitAssignRamToQueues() from common module inserted. + * Autonegotiation is set to ON for all adapters. + * LinkSpeedUsed is used in link up status report. + * Role parameter will show up for 1000 Mbps links only. + * GetConfiguration() inserted after init level 1 in SkGeChangeMtu(). + * All return values of SkGeInit() and SkGeInitPort() are checked. + * + * Revision 1.39 2002/10/02 12:56:05 mlindner + * Add: Support for Yukon + * Add: Support for ZEROCOPY, scatter-gather and hw checksum + * Add: New transmit ring function (use SG and TCP/UDP hardware checksumming) + * Add: New init function + * Add: Speed check and setup + * Add: Merge source for kernel 2.2.x and 2.4.x + * Add: Opcode check for tcp + * Add: Frame length check + * Fix: Transmit complete interrupt + * Fix: Interrupt moderation + * + * Revision 1.29.2.13 2002/01/14 12:44:52 mlindner + * Fix: Rlmt modes + * + * Revision 1.29.2.12 2001/12/07 12:06:18 mlindner + * Fix: malloc -> slab changes + * + * Revision 1.29.2.11 2001/12/06 15:19:20 mlindner + * Add: DMA attributes + * Fix: Module initialisation + * Fix: pci_map_single and pci_unmap_single replaced + * + * Revision 1.29.2.10 2001/12/06 09:56:50 mlindner + * Corrected some printk's + * + * Revision 1.29.2.9 2001/09/05 12:15:34 mlindner + * Add: LBFO Changes + * Fix: Counter Errors (Jumbo == to long errors) + * Fix: Changed pAC->PciDev declaration + * Fix: too short counters + * + * Revision 1.29.2.8 2001/06/25 12:10:44 mlindner + * fix: ReceiveIrq() changed. + * + * Revision 1.29.2.7 2001/06/25 08:07:05 mlindner + * fix: RLMT locking in ReceiveIrq() changed. + * + * Revision 1.29.2.6 2001/05/21 07:59:29 mlindner + * fix: MTU init problems + * + * Revision 1.29.2.5 2001/05/08 11:25:08 mlindner + * fix: removed VLAN error message + * + * Revision 1.29.2.4 2001/05/04 13:31:43 gklug + * fix: do not handle eth_copy on bad fragments received. + * + * Revision 1.29.2.3 2001/04/23 08:06:43 mlindner + * Fix: error handling + * + * Revision 1.29.2.2 2001/03/15 12:04:54 mlindner + * Fixed memory problem + * + * Revision 1.29.2.1 2001/03/12 16:41:44 mlindner + * add: procfs function + * add: dual-net function + * add: RLMT networks + * add: extended PNMI features + * + * Kernel 2.4.x specific: + * Revision 1.xx 2000/09/12 13:31:56 cgoos + * Fixed missign "dev=NULL in skge_probe. + * Added counting for jumbo frames (corrects error statistic). + * Removed VLAN tag check (enables VLAN support). + * + * Kernel 2.2.x specific: + * Revision 1.29 2000/02/21 13:31:56 cgoos + * Fixed "unused" warning for UltraSPARC change. + * + * Partially kernel 2.2.x specific: + * Revision 1.28 2000/02/21 10:32:36 cgoos + * Added fixes for UltraSPARC. + * Now printing RlmtMode and PrefPort setting at startup. + * Changed XmitFrame return value. + * Fixed rx checksum calculation for BIG ENDIAN systems. + * Fixed rx jumbo frames counted as ierrors. + * + * + * Revision 1.27 1999/11/25 09:06:28 cgoos + * Changed base_addr to unsigned long. + * + * Revision 1.26 1999/11/22 13:29:16 cgoos + * Changed license header to GPL. + * Changes for inclusion in linux kernel (2.2.13). + * Removed 2.0.x defines. + * Changed SkGeProbe to skge_probe. + * Added checks in SkGeIoctl. + * + * Revision 1.25 1999/10/07 14:47:52 cgoos + * Changed 984x to 98xx. + * + * Revision 1.24 1999/09/30 07:21:01 cgoos + * Removed SK_RLMT_SLOW_LOOKAHEAD option. + * Giving spanning tree packets also to OS now. + * + * Revision 1.23 1999/09/29 07:36:50 cgoos + * Changed assignment for IsBc/IsMc. + * + * Revision 1.22 1999/09/28 12:57:09 cgoos + * Added CheckQueue also to Single-Port-ISR. + * + * Revision 1.21 1999/09/28 12:42:41 cgoos + * Changed parameter strings for RlmtMode. + * + * Revision 1.20 1999/09/28 12:37:57 cgoos + * Added CheckQueue for fast delivery of RLMT frames. + * + * Revision 1.19 1999/09/16 07:57:25 cgoos + * Copperfield changes. + * + * Revision 1.18 1999/09/03 13:06:30 cgoos + * Fixed RlmtMode=CheckSeg bug: wrong DEV_KFREE_SKB in RLMT_SEND caused + * double allocated skb's. + * FrameStat in ReceiveIrq was accessed via wrong Rxd. + * Queue size for async. standby Tx queue was zero. + * FillRxLimit of 0 could cause problems with ReQueue, changed to 1. + * Removed debug output of checksum statistic. + * + * Revision 1.17 1999/08/11 13:55:27 cgoos + * Transmit descriptor polling was not reenabled after SkGePortInit. + * + * Revision 1.16 1999/07/27 15:17:29 cgoos + * Added some "\n" in output strings (removed while debuging...). + * + * Revision 1.15 1999/07/23 12:09:30 cgoos + * Performance optimization, rx checksumming, large frame support. + * + * Revision 1.14 1999/07/14 11:26:27 cgoos + * Removed Link LED settings (now in RLMT). + * Added status output at NET UP. + * Fixed SMP problems with Tx and SWITCH running in parallel. + * Fixed return code problem at RLMT_SEND event. + * + * Revision 1.13 1999/04/07 10:11:42 cgoos + * Fixed Single Port problems. + * Fixed Multi-Adapter problems. + * Always display startup string. + * + * Revision 1.12 1999/03/29 12:26:37 cgoos + * Reversed locking to fine granularity. + * Fixed skb double alloc problem (caused by incorrect xmit return code). + * Enhanced function descriptions. + * + * Revision 1.11 1999/03/15 13:10:51 cgoos + * Changed device identifier in output string to ethX. + * + * Revision 1.10 1999/03/15 12:12:34 cgoos + * Changed copyright notice. + * + * Revision 1.9 1999/03/15 12:10:17 cgoos + * Changed locking to one driver lock. + * Added check of SK_AC-size (for consistency with library). + * + * Revision 1.8 1999/03/08 11:44:02 cgoos + * Fixed missing dev->tbusy in SkGeXmit. + * Changed large frame (jumbo) buffer number. + * Added copying of short frames. + * + * Revision 1.7 1999/03/04 13:26:57 cgoos + * Fixed spinlock calls for SMP. + * + * Revision 1.6 1999/03/02 09:53:51 cgoos + * Added descriptor revertion for big endian machines. + * + * Revision 1.5 1999/03/01 08:50:59 cgoos + * Fixed SkGeChangeMtu. + * Fixed pci config space accesses. + * + * Revision 1.4 1999/02/18 15:48:44 cgoos + * Corrected some printk's. + * + * Revision 1.3 1999/02/18 12:45:55 cgoos + * Changed SK_MAX_CARD_PARAM to default 16 + * + * Revision 1.2 1999/02/18 10:55:32 cgoos + * Removed SkGeDrvTimeStamp function. + * Printing "ethX:" before adapter type at adapter init. + * + * + * 10-Feb-1999 cg Created, based on Linux' acenic.c, 3c59x.c and + * SysKonnects GEnesis Solaris driver + * + ******************************************************************************/ + +/****************************************************************************** + * + * Possible compiler options (#define xxx / -Dxxx): + * + * debugging can be enable by changing SK_DEBUG_CHKMOD and + * SK_DEBUG_CHKCAT in makefile (described there). + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This is the main module of the Linux GE driver. + * + * All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h + * are part of SysKonnect's COMMON MODULES for the SK-98xx adapters. + * Those are used for drivers on multiple OS', so some thing may seem + * unnecessary complicated on Linux. Please do not try to 'clean up' + * them without VERY good reasons, because this will make it more + * difficult to keep the Linux driver in synchronisation with the + * other versions. + * + * Include file hierarchy: + * + * + * + * "h/skdrv1st.h" + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * those three depending on kernel version used: + * + * + * + * + * + * "h/skerror.h" + * "h/skdebug.h" + * "h/sktypes.h" + * "h/lm80.h" + * "h/xmac_ii.h" + * + * "h/skdrv2nd.h" + * "h/skqueue.h" + * "h/skgehwt.h" + * "h/sktimer.h" + * "h/ski2c.h" + * "h/skgepnmi.h" + * "h/skvpd.h" + * "h/skgehw.h" + * "h/skgeinit.h" + * "h/skaddr.h" + * "h/skgesirq.h" + * "h/skcsum.h" + * "h/skrlmt.h" + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include "h/skversion.h" +#if 0 +#include +#include +#include +#endif +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + + +/* defines ******************************************************************/ +/* for debuging on x86 only */ +/* #define BREAKPOINT() asm(" int $3"); */ + +/* use the scatter-gather functionality with sendfile() */ +#if 0 +#define SK_ZEROCOPY +#endif + +/* use of a transmit complete interrupt */ +#define USE_TX_COMPLETE + +/* use interrupt moderation (for tx complete only) */ +#define USE_INT_MOD +#define INTS_PER_SEC 1000 + +/* + * threshold for copying small receive frames + * set to 0 to avoid copying, set to 9001 to copy all frames + */ +#define SK_COPY_THRESHOLD 50 + +/* number of adapters that can be configured via command line params */ +#define SK_MAX_CARD_PARAM 16 + + +/* + * use those defines for a compile-in version of the driver instead + * of command line parameters + */ +/* #define LINK_SPEED_A {"Auto", } */ +/* #define LINK_SPEED_B {"Auto", } */ +/* #define AUTO_NEG_A {"Sense", } */ +/* #define AUTO_NEG_B {"Sense", } */ +/* #define DUP_CAP_A {"Both", } */ +/* #define DUP_CAP_B {"Both", } */ +/* #define FLOW_CTRL_A {"SymOrRem", } */ +/* #define FLOW_CTRL_B {"SymOrRem", } */ +/* #define ROLE_A {"Auto", } */ +/* #define ROLE_B {"Auto", } */ +/* #define PREF_PORT {"A", } */ +/* #define RLMT_MODE {"CheckLinkState", } */ + +#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb) +#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb) +#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb) + +/* function prototypes ******************************************************/ +static void FreeResources(struct SK_NET_DEVICE *dev); +static int SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC); +static SK_BOOL BoardAllocMem(SK_AC *pAC); +static void BoardFreeMem(SK_AC *pAC); +static void BoardInitMem(SK_AC *pAC); +static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, + int*, SK_BOOL); + +#if 0 +static void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); +static void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); +static int SkGeOpen(struct SK_NET_DEVICE *dev); +static int SkGeClose(struct SK_NET_DEVICE *dev); +static int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev); +static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p); +static void SkGeSetRxMode(struct SK_NET_DEVICE *dev); +static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev); +static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd); +#else +void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); +void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); +int SkGeOpen(struct SK_NET_DEVICE *dev); +int SkGeClose(struct SK_NET_DEVICE *dev); +int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev); +#endif +static void GetConfiguration(SK_AC*); +static void ProductStr(SK_AC*); +static int XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*); +static void FreeTxDescriptors(SK_AC*pAC, TX_PORT*); +static void FillRxRing(SK_AC*, RX_PORT*); +static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*); +#if 0 +static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL); +#else +void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL); +#endif +static void ClearAndStartRx(SK_AC*, int); +static void ClearTxIrq(SK_AC*, int, int); +static void ClearRxRing(SK_AC*, RX_PORT*); +static void ClearTxRing(SK_AC*, TX_PORT*); +#if 0 +static void SetQueueSizes(SK_AC *pAC); + +static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu); +#endif +static void PortReInitBmu(SK_AC*, int); +#if 0 +static int SkGeIocMib(DEV_NET*, unsigned int, int); +static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*); +#endif + +/*Extern */ + +/* external Proc function */ +extern int proc_read( + char *buffer, + char **buffer_location, + off_t offset, + int buffer_length, + int *eof, + void *data); + +#ifdef DEBUG +static void DumpMsg(struct sk_buff*, char*); +static void DumpData(char*, int); +static void DumpLong(char*, int); +#endif +void dump_frag( SK_U8 *data, int length); + +/* global variables *********************************************************/ +#if 0 +static const char *BootString = BOOT_STRING; +#endif +struct SK_NET_DEVICE *SkGeRootDev = NULL; +static int probed __initdata = 0; + +/* local variables **********************************************************/ +static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}}; +static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480}; + + +/* local variables **********************************************************/ +const char SK_Root_Dir_entry[8]; + +#if 0 +static struct proc_dir_entry *pSkRootDir; +#endif + + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_3COM, 0x1700}, + {PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE}, + {PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU}, + {} +}; + + +/***************************************************************************** + * + * skge_probe - find all SK-98xx adapters + * + * Description: + * This function scans the PCI bus for SK-98xx adapters. Resources for + * each adapter are allocated and the adapter is brought into Init 1 + * state. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +#if 0 +static int __init skge_probe (void) +#else +int skge_probe (struct eth_device ** ret_dev) +#endif +{ +#if 0 + int proc_root_initialized = 0; +#endif + int boards_found = 0; +#if 0 + int vendor_flag = SK_FALSE; +#endif + SK_AC *pAC; + DEV_NET *pNet = NULL; +#if 0 + struct proc_dir_entry *pProcFile; + struct pci_dev *pdev = NULL; + unsigned long base_address; +#else + u32 base_address; +#endif + struct SK_NET_DEVICE *dev = NULL; +#if 0 + SK_BOOL DeviceFound = SK_FALSE; +#endif + SK_BOOL BootStringCount = SK_FALSE; +#if 1 + pci_dev_t devno; +#endif + + if (probed) + return -ENODEV; + probed++; + + if (!pci_present()) /* is PCI support present? */ + return -ENODEV; + +#if 0 + while((pdev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, pdev))) +#else + while((devno = pci_find_devices (supported, boards_found)) >= 0) +#endif + { + + dev = NULL; + pNet = NULL; + + +#if 0 + SK_PCI_ISCOMPLIANT(vendor_flag, pdev); + if (!vendor_flag) + continue; +#endif + +/* if ((pdev->vendor != PCI_VENDOR_ID_SYSKONNECT) && + ((pdev->device != PCI_DEVICE_ID_SYSKONNECT_GE) || + (pdev->device != PCI_DEVICE_ID_SYSKONNECT_YU))){ + continue; + } +*/ +#if 0 + /* Configure DMA attributes. */ + if (pci_set_dma_mask(pdev, (u64) 0xffffffffffffffff) && + pci_set_dma_mask(pdev, (u64) 0xffffffff)) + continue; +#endif + + +#if 0 + if ((dev = init_etherdev(dev, sizeof(DEV_NET))) == NULL) { + printk(KERN_ERR "Unable to allocate etherdev " + "structure!\n"); + break; + } +#else + dev = malloc (sizeof *dev); + memset(dev, 0, sizeof(*dev)); + dev->priv = malloc(sizeof(DEV_NET)); +#endif + + if (dev->priv == NULL) { + printk(KERN_ERR "Unable to allocate adapter " + "structure!\n"); + break; + } + + pNet = dev->priv; + pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL); + if (pNet->pAC == NULL){ + kfree(dev->priv); + printk(KERN_ERR "Unable to allocate adapter " + "structure!\n"); + break; + } + + /* Print message */ + if (!BootStringCount) { + /* set display flag to TRUE so that */ + /* we only display this string ONCE */ + BootStringCount = SK_TRUE; +#ifdef SK98_INFO + printk("%s\n", BootString); +#endif + } + + memset(pNet->pAC, 0, sizeof(SK_AC)); + pAC = pNet->pAC; +#if 0 + pAC->PciDev = pdev; + pAC->PciDevId = pdev->device; + pAC->dev[0] = dev; + pAC->dev[1] = dev; +#else + pAC->PciDev = devno; + ret_dev[0] = pAC->dev[0] = dev; + ret_dev[1] = pAC->dev[1] = dev; +#endif + sprintf(pAC->Name, "SysKonnect SK-98xx"); + pAC->CheckQueue = SK_FALSE; + + pNet->Mtu = 1500; + pNet->Up = 0; +#if 0 + dev->irq = pdev->irq; + + dev->open = &SkGeOpen; + dev->stop = &SkGeClose; + dev->hard_start_xmit = &SkGeXmit; + dev->get_stats = &SkGeStats; + dev->set_multicast_list = &SkGeSetRxMode; + dev->set_mac_address = &SkGeSetMacAddr; + dev->do_ioctl = &SkGeIoctl; + dev->change_mtu = &SkGeChangeMtu; + dev->flags &= ~IFF_RUNNING; +#endif + +#ifdef SK_ZEROCOPY + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + /* Use only if yukon hardware */ + /* SK and ZEROCOPY - fly baby... */ + dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; + } +#endif + +#if 0 + /* + * Dummy value. + */ + dev->base_addr = 42; + pci_set_master(pdev); + + pci_set_master(pdev); + base_address = pci_resource_start (pdev, 0); +#else + pci_write_config_dword(devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, + &base_address); +#endif + +#ifdef SK_BIG_ENDIAN + /* + * On big endian machines, we use the adapter's aibility of + * reading the descriptors as big endian. + */ + { + SK_U32 our2; + SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); + our2 |= PCI_REV_DESC; + SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); + } +#endif + + /* + * Remap the regs into kernel space. + */ +#if 0 + pAC->IoBase = (char*)ioremap(base_address, 0x4000); +#else + pAC->IoBase = (char*)pci_mem_to_phys(devno, base_address); +#endif + + if (!pAC->IoBase){ + printk(KERN_ERR "%s: Unable to map I/O register, " + "SK 98xx No. %i will be disabled.\n", + dev->name, boards_found); + kfree(dev); + break; + } + + pAC->Index = boards_found; + if (SkGeBoardInit(dev, pAC)) { + FreeResources(dev); + kfree(dev); + continue; + } + +#if 0 + memcpy((caddr_t) &dev->dev_addr, + (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); +#else + memcpy((caddr_t) &dev->enetaddr, + (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); +#endif + +#if 0 + /* First adapter... Create proc and print message */ + if (!DeviceFound) { + DeviceFound = SK_TRUE; + SK_MEMCPY(&SK_Root_Dir_entry, BootString, + sizeof(SK_Root_Dir_entry) - 1); + + /*Create proc (directory)*/ + if(!proc_root_initialized) { + pSkRootDir = create_proc_entry(SK_Root_Dir_entry, + S_IFDIR | S_IWUSR | S_IRUGO | S_IXUGO, proc_net); + proc_root_initialized = 1; + } + + pSkRootDir->owner = THIS_MODULE; + } + + + /* Create proc file */ + pProcFile = create_proc_entry(dev->name, + S_IFREG | S_IXUSR | S_IWGRP | S_IROTH, + pSkRootDir); + + + pProcFile->read_proc = proc_read; + pProcFile->write_proc = NULL; + pProcFile->nlink = 1; + pProcFile->size = sizeof(dev->name + 1); + pProcFile->data = (void *)pProcFile; +#endif + + pNet->PortNr = 0; + pNet->NetNr = 0; + +#ifdef SK_ZEROCOPY + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + /* SG and ZEROCOPY - fly baby... */ + dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; + } +#endif + + boards_found++; + + /* More then one port found */ + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { +#if 0 + if ((dev = init_etherdev(NULL, sizeof(DEV_NET))) == 0) { + printk(KERN_ERR "Unable to allocate etherdev " + "structure!\n"); + break; + } +#else + dev = malloc (sizeof *dev); + memset(dev, 0, sizeof(*dev)); + dev->priv = malloc(sizeof(DEV_NET)); +#endif + + pAC->dev[1] = dev; + pNet = dev->priv; + pNet->PortNr = 1; + pNet->NetNr = 1; + pNet->pAC = pAC; + pNet->Mtu = 1500; + pNet->Up = 0; + +#if 0 + dev->open = &SkGeOpen; + dev->stop = &SkGeClose; + dev->hard_start_xmit = &SkGeXmit; + dev->get_stats = &SkGeStats; + dev->set_multicast_list = &SkGeSetRxMode; + dev->set_mac_address = &SkGeSetMacAddr; + dev->do_ioctl = &SkGeIoctl; + dev->change_mtu = &SkGeChangeMtu; + dev->flags &= ~IFF_RUNNING; +#endif + +#ifdef SK_ZEROCOPY + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + /* SG and ZEROCOPY - fly baby... */ + dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; + } +#endif + +#if 0 + pProcFile = create_proc_entry(dev->name, + S_IFREG | S_IXUSR | S_IWGRP | S_IROTH, + pSkRootDir); + + + pProcFile->read_proc = proc_read; + pProcFile->write_proc = NULL; + pProcFile->nlink = 1; + pProcFile->size = sizeof(dev->name + 1); + pProcFile->data = (void *)pProcFile; +#endif + +#if 0 + memcpy((caddr_t) &dev->dev_addr, + (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); +#else + memcpy((caddr_t) &dev->enetaddr, + (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); +#endif + + printk("%s: %s\n", dev->name, pAC->DeviceStr); + printk(" PrefPort:B RlmtMode:Dual Check Link State\n"); + + } + + + /* Save the hardware revision */ + pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) + + (pAC->GIni.GIPciHwRev & 0x0F); + + /* + * This is bollocks, but we need to tell the net-init + * code that it shall go for the next device. + */ +#if 0 +#ifndef MODULE + dev->base_addr = 0; +#endif +#endif + } + + /* + * If we're at this point we're going through skge_probe() for + * the first time. Return success (0) if we've initialized 1 + * or more boards. Otherwise, return failure (-ENODEV). + */ + + return boards_found; +} /* skge_probe */ + + +/***************************************************************************** + * + * FreeResources - release resources allocated for adapter + * + * Description: + * This function releases the IRQ, unmaps the IO and + * frees the desriptor ring. + * + * Returns: N/A + * + */ +static void FreeResources(struct SK_NET_DEVICE *dev) +{ +SK_U32 AllocFlag; +DEV_NET *pNet; +SK_AC *pAC; + + if (dev->priv) { + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + AllocFlag = pAC->AllocFlag; +#if 0 + if (AllocFlag & SK_ALLOC_IRQ) { + free_irq(dev->irq, dev); + } + if (pAC->IoBase) { + iounmap(pAC->IoBase); + } +#endif + if (pAC->pDescrMem) { + BoardFreeMem(pAC); + } + } + +} /* FreeResources */ + +#if 0 +MODULE_AUTHOR("Mirko Lindner "); +MODULE_DESCRIPTION("SysKonnect SK-NET Gigabit Ethernet SK-98xx driver"); +MODULE_LICENSE("GPL"); +MODULE_PARM(Speed_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(Speed_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(AutoNeg_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(AutoNeg_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(DupCap_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(DupCap_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(FlowCtrl_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(FlowCtrl_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(Role_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(Role_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(PrefPort, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(RlmtMode, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +/* not used, just there because every driver should have them: */ +MODULE_PARM(options, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i"); +MODULE_PARM(debug, "i"); +#endif + + +#ifdef LINK_SPEED_A +static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED_A; +#else +static char *Speed_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef LINK_SPEED_B +static char *Speed_B[SK_MAX_CARD_PARAM] = LINK_SPEED_B; +#else +static char *Speed_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef AUTO_NEG_A +static char *AutoNeg_A[SK_MAX_CARD_PARAM] = AUTO_NEG_A; +#else +static char *AutoNeg_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef DUP_CAP_A +static char *DupCap_A[SK_MAX_CARD_PARAM] = DUP_CAP_A; +#else +static char *DupCap_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef FLOW_CTRL_A +static char *FlowCtrl_A[SK_MAX_CARD_PARAM] = FLOW_CTRL_A; +#else +static char *FlowCtrl_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef ROLE_A +static char *Role_A[SK_MAX_CARD_PARAM] = ROLE_A; +#else +static char *Role_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef AUTO_NEG_B +static char *AutoNeg_B[SK_MAX_CARD_PARAM] = AUTO_NEG_B; +#else +static char *AutoNeg_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef DUP_CAP_B +static char *DupCap_B[SK_MAX_CARD_PARAM] = DUP_CAP_B; +#else +static char *DupCap_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef FLOW_CTRL_B +static char *FlowCtrl_B[SK_MAX_CARD_PARAM] = FLOW_CTRL_B; +#else +static char *FlowCtrl_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef ROLE_B +static char *Role_B[SK_MAX_CARD_PARAM] = ROLE_B; +#else +static char *Role_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef PREF_PORT +static char *PrefPort[SK_MAX_CARD_PARAM] = PREF_PORT; +#else +static char *PrefPort[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef RLMT_MODE +static char *RlmtMode[SK_MAX_CARD_PARAM] = RLMT_MODE; +#else +static char *RlmtMode[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#if 0 +static int debug = 0; /* not used */ +static int options[SK_MAX_CARD_PARAM] = {0, }; /* not used */ + + +/***************************************************************************** + * + * skge_init_module - module initialization function + * + * Description: + * Very simple, only call skge_probe and return approriate result. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int __init skge_init_module(void) +{ + int cards; + SkGeRootDev = NULL; + + /* just to avoid warnings ... */ + debug = 0; + options[0] = 0; + + cards = skge_probe(); + if (cards == 0) { + printk("sk98lin: No adapter found.\n"); + } + return cards ? 0 : -ENODEV; +} /* skge_init_module */ + + +/***************************************************************************** + * + * skge_cleanup_module - module unload function + * + * Description: + * Disable adapter if it is still running, free resources, + * free device struct. + * + * Returns: N/A + */ +static void __exit skge_cleanup_module(void) +{ +DEV_NET *pNet; +SK_AC *pAC; +struct SK_NET_DEVICE *next; +unsigned long Flags; +SK_EVPARA EvPara; + + while (SkGeRootDev) { + pNet = (DEV_NET*) SkGeRootDev->priv; + pAC = pNet->pAC; + next = pAC->Next; + + netif_stop_queue(SkGeRootDev); + SkGeYellowLED(pAC, pAC->IoBase, 0); + + if(pAC->BoardLevel == 2) { + /* board is still alive */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + EvPara.Para32[0] = 0; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + EvPara.Para32[0] = 1; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + SkGeDeInit(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + pAC->BoardLevel = 0; + /* We do NOT check here, if IRQ was pending, of course*/ + } + + if(pAC->BoardLevel == 1) { + /* board is still alive */ + SkGeDeInit(pAC, pAC->IoBase); + pAC->BoardLevel = 0; + } + + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){ + unregister_netdev(pAC->dev[1]); + kfree(pAC->dev[1]); + } + + FreeResources(SkGeRootDev); + + SkGeRootDev->get_stats = NULL; + /* + * otherwise unregister_netdev calls get_stats with + * invalid IO ... :-( + */ + unregister_netdev(SkGeRootDev); + kfree(SkGeRootDev); + kfree(pAC); + SkGeRootDev = next; + } + + /* clear proc-dir */ + remove_proc_entry(pSkRootDir->name, proc_net); + +} /* skge_cleanup_module */ + +module_init(skge_init_module); +module_exit(skge_cleanup_module); +#endif + + +/***************************************************************************** + * + * SkGeBoardInit - do level 0 and 1 initialization + * + * Description: + * This function prepares the board hardware for running. The desriptor + * ring is set up, the IRQ is allocated and the configuration settings + * are examined. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int __init SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC) +{ +short i; +unsigned long Flags; +char *DescrString = "sk98lin: Driver for Linux"; /* this is given to PNMI */ +char *VerStr = VER_STRING; +#if 0 +int Ret; /* return code of request_irq */ +#endif +SK_BOOL DualNet; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("IoBase: %08lX\n", (unsigned long)pAC->IoBase)); + for (i=0; iTxPort[i][0].HwAddr = pAC->IoBase + TxQueueAddr[i][0]; + pAC->TxPort[i][0].PortIndex = i; + pAC->RxPort[i].HwAddr = pAC->IoBase + RxQueueAddr[i]; + pAC->RxPort[i].PortIndex = i; + } + + /* Initialize the mutexes */ + for (i=0; iTxPort[i][0].TxDesRingLock); + spin_lock_init(&pAC->RxPort[i].RxDesRingLock); + } + spin_lock_init(&pAC->SlowPathLock); + + /* level 0 init common modules here */ + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + /* Does a RESET on board ...*/ + if (SkGeInit(pAC, pAC->IoBase, 0) != 0) { + printk("HWInit (0) failed.\n"); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + return(-EAGAIN); + } + SkI2cInit( pAC, pAC->IoBase, 0); + SkEventInit(pAC, pAC->IoBase, 0); + SkPnmiInit( pAC, pAC->IoBase, 0); + SkAddrInit( pAC, pAC->IoBase, 0); + SkRlmtInit( pAC, pAC->IoBase, 0); + SkTimerInit(pAC, pAC->IoBase, 0); + + pAC->BoardLevel = 0; + pAC->RxBufSize = ETH_BUF_SIZE; + + SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString); + SK_PNMI_SET_DRIVER_VER(pAC, VerStr); + + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + /* level 1 init common modules here (HW init) */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + if (SkGeInit(pAC, pAC->IoBase, 1) != 0) { + printk("HWInit (1) failed.\n"); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + return(-EAGAIN); + } + SkI2cInit( pAC, pAC->IoBase, 1); + SkEventInit(pAC, pAC->IoBase, 1); + SkPnmiInit( pAC, pAC->IoBase, 1); + SkAddrInit( pAC, pAC->IoBase, 1); + SkRlmtInit( pAC, pAC->IoBase, 1); + SkTimerInit(pAC, pAC->IoBase, 1); + + GetConfiguration(pAC); + if (pAC->RlmtNets == 2) { + pAC->GIni.GIPortUsage = SK_MUL_LINK; + } + + pAC->BoardLevel = 1; + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + +#if 0 + if (pAC->GIni.GIMacsFound == 2) { + Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, pAC->Name, dev); + } else if (pAC->GIni.GIMacsFound == 1) { + Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, + pAC->Name, dev); + } else { + printk(KERN_WARNING "%s: Illegal number of ports: %d\n", + dev->name, pAC->GIni.GIMacsFound); + return -EAGAIN; + } + + if (Ret) { + printk(KERN_WARNING "%s: Requested IRQ %d is busy.\n", + dev->name, dev->irq); + return -EAGAIN; + } +#endif + pAC->AllocFlag |= SK_ALLOC_IRQ; + + /* Alloc memory for this board (Mem for RxD/TxD) : */ + if(!BoardAllocMem(pAC)) { + printk("No memory for descriptor rings.\n"); + return(-EAGAIN); + } + + SkCsSetReceiveFlags(pAC, + SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP, + &pAC->CsOfs1, &pAC->CsOfs2, 0); + pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1; + + BoardInitMem(pAC); +#if 0 + SetQueueSizes(pAC); +#else + /* tschilling: New common function with minimum size check. */ + DualNet = SK_FALSE; + if (pAC->RlmtNets == 2) { + DualNet = SK_TRUE; + } + + if (SkGeInitAssignRamToQueues( + pAC, + pAC->ActivePort, + DualNet)) { + BoardFreeMem(pAC); + printk("SkGeInitAssignRamToQueues failed.\n"); + return(-EAGAIN); + } +#endif + + /* Print adapter specific string from vpd */ + ProductStr(pAC); +#ifdef SK98_INFO + printk("%s: %s\n", dev->name, pAC->DeviceStr); + + /* Print configuration settings */ + printk(" PrefPort:%c RlmtMode:%s\n", + 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber, + (pAC->RlmtMode==0) ? "Check Link State" : + ((pAC->RlmtMode==1) ? "Check Link State" : + ((pAC->RlmtMode==3) ? "Check Local Port" : + ((pAC->RlmtMode==7) ? "Check Segmentation" : + ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error"))))); +#endif + + SkGeYellowLED(pAC, pAC->IoBase, 1); + + /* + * Register the device here + */ + pAC->Next = SkGeRootDev; + SkGeRootDev = dev; + + return (0); +} /* SkGeBoardInit */ + + +/***************************************************************************** + * + * BoardAllocMem - allocate the memory for the descriptor rings + * + * Description: + * This function allocates the memory for all descriptor rings. + * Each ring is aligned for the desriptor alignment and no ring + * has a 4 GByte boundary in it (because the upper 32 bit must + * be constant for all descriptiors in one rings). + * + * Returns: + * SK_TRUE, if all memory could be allocated + * SK_FALSE, if not + */ +static SK_BOOL BoardAllocMem( +SK_AC *pAC) +{ +caddr_t pDescrMem; /* pointer to descriptor memory area */ +size_t AllocLength; /* length of complete descriptor area */ +int i; /* loop counter */ +unsigned long BusAddr; + + + /* rings plus one for alignment (do not cross 4 GB boundary) */ + /* RX_RING_SIZE is assumed bigger than TX_RING_SIZE */ +#if (BITS_PER_LONG == 32) + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8; +#else + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + + RX_RING_SIZE + 8; +#endif + + pDescrMem = pci_alloc_consistent(pAC->PciDev, AllocLength, + &pAC->pDescrMemDMA); + + if (pDescrMem == NULL) { + return (SK_FALSE); + } + pAC->pDescrMem = pDescrMem; + BusAddr = (unsigned long) pAC->pDescrMemDMA; + + /* Descriptors need 8 byte alignment, and this is ensured + * by pci_alloc_consistent. + */ + for (i=0; iGIni.GIMacsFound; i++) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("TX%d/A: pDescrMem: %lX, PhysDescrMem: %lX\n", + i, (unsigned long) pDescrMem, + BusAddr)); + pAC->TxPort[i][0].pTxDescrRing = pDescrMem; + pAC->TxPort[i][0].VTxDescrRing = BusAddr; + pDescrMem += TX_RING_SIZE; + BusAddr += TX_RING_SIZE; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("RX%d: pDescrMem: %lX, PhysDescrMem: %lX\n", + i, (unsigned long) pDescrMem, + (unsigned long)BusAddr)); + pAC->RxPort[i].pRxDescrRing = pDescrMem; + pAC->RxPort[i].VRxDescrRing = BusAddr; + pDescrMem += RX_RING_SIZE; + BusAddr += RX_RING_SIZE; + } /* for */ + + return (SK_TRUE); +} /* BoardAllocMem */ + + +/**************************************************************************** + * + * BoardFreeMem - reverse of BoardAllocMem + * + * Description: + * Free all memory allocated in BoardAllocMem: adapter context, + * descriptor rings, locks. + * + * Returns: N/A + */ +static void BoardFreeMem( +SK_AC *pAC) +{ +size_t AllocLength; /* length of complete descriptor area */ + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("BoardFreeMem\n")); +#if (BITS_PER_LONG == 32) + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8; +#else + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + + RX_RING_SIZE + 8; +#endif + + pci_free_consistent(pAC->PciDev, AllocLength, + pAC->pDescrMem, pAC->pDescrMemDMA); + pAC->pDescrMem = NULL; +} /* BoardFreeMem */ + + +/***************************************************************************** + * + * BoardInitMem - initiate the descriptor rings + * + * Description: + * This function sets the descriptor rings up in memory. + * The adapter is initialized with the descriptor start addresses. + * + * Returns: N/A + */ +static void BoardInitMem( +SK_AC *pAC) /* pointer to adapter context */ +{ +int i; /* loop counter */ +int RxDescrSize; /* the size of a rx descriptor rounded up to alignment*/ +int TxDescrSize; /* the size of a tx descriptor rounded up to alignment*/ + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("BoardInitMem\n")); + + RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; + pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize; + TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; + pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize; + + for (i=0; iGIni.GIMacsFound; i++) { + SetupRing( + pAC, + pAC->TxPort[i][0].pTxDescrRing, + pAC->TxPort[i][0].VTxDescrRing, + (RXD**)&pAC->TxPort[i][0].pTxdRingHead, + (RXD**)&pAC->TxPort[i][0].pTxdRingTail, + (RXD**)&pAC->TxPort[i][0].pTxdRingPrev, + &pAC->TxPort[i][0].TxdRingFree, + SK_TRUE); + SetupRing( + pAC, + pAC->RxPort[i].pRxDescrRing, + pAC->RxPort[i].VRxDescrRing, + &pAC->RxPort[i].pRxdRingHead, + &pAC->RxPort[i].pRxdRingTail, + &pAC->RxPort[i].pRxdRingPrev, + &pAC->RxPort[i].RxdRingFree, + SK_FALSE); + } +} /* BoardInitMem */ + + +/***************************************************************************** + * + * SetupRing - create one descriptor ring + * + * Description: + * This function creates one descriptor ring in the given memory area. + * The head, tail and number of free descriptors in the ring are set. + * + * Returns: + * none + */ +static void SetupRing( +SK_AC *pAC, +void *pMemArea, /* a pointer to the memory area for the ring */ +uintptr_t VMemArea, /* the virtual bus address of the memory area */ +RXD **ppRingHead, /* address where the head should be written */ +RXD **ppRingTail, /* address where the tail should be written */ +RXD **ppRingPrev, /* address where the tail should be written */ +int *pRingFree, /* address where the # of free descr. goes */ +SK_BOOL IsTx) /* flag: is this a tx ring */ +{ +int i; /* loop counter */ +int DescrSize; /* the size of a descriptor rounded up to alignment*/ +int DescrNum; /* number of descriptors per ring */ +RXD *pDescr; /* pointer to a descriptor (receive or transmit) */ +RXD *pNextDescr; /* pointer to the next descriptor */ +RXD *pPrevDescr; /* pointer to the previous descriptor */ +uintptr_t VNextDescr; /* the virtual bus address of the next descriptor */ + + if (IsTx == SK_TRUE) { + DescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * + DESCR_ALIGN; + DescrNum = TX_RING_SIZE / DescrSize; + } else { + DescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * + DESCR_ALIGN; + DescrNum = RX_RING_SIZE / DescrSize; + } + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Descriptor size: %d Descriptor Number: %d\n", + DescrSize,DescrNum)); + + pDescr = (RXD*) pMemArea; + pPrevDescr = NULL; + pNextDescr = (RXD*) (((char*)pDescr) + DescrSize); + VNextDescr = VMemArea + DescrSize; + for(i=0; iVNextRxd = VNextDescr & 0xffffffffULL; + pDescr->pNextRxd = pNextDescr; + pDescr->TcpSumStarts = pAC->CsOfs; + + /* advance one step */ + pPrevDescr = pDescr; + pDescr = pNextDescr; + pNextDescr = (RXD*) (((char*)pDescr) + DescrSize); + VNextDescr += DescrSize; + } + pPrevDescr->pNextRxd = (RXD*) pMemArea; + pPrevDescr->VNextRxd = VMemArea; + pDescr = (RXD*) pMemArea; + *ppRingHead = (RXD*) pMemArea; + *ppRingTail = *ppRingHead; + *ppRingPrev = pPrevDescr; + *pRingFree = DescrNum; +} /* SetupRing */ + + +/***************************************************************************** + * + * PortReInitBmu - re-initiate the descriptor rings for one port + * + * Description: + * This function reinitializes the descriptor rings of one port + * in memory. The port must be stopped before. + * The HW is initialized with the descriptor start addresses. + * + * Returns: + * none + */ +static void PortReInitBmu( +SK_AC *pAC, /* pointer to adapter context */ +int PortIndex) /* index of the port for which to re-init */ +{ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("PortReInitBmu ")); + + /* set address of first descriptor of ring in BMU */ + SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ + TX_Q_CUR_DESCR_LOW, + (uint32_t)(((caddr_t) + (pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) - + pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing + + pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) & + 0xFFFFFFFF)); + SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ + TX_Q_DESCR_HIGH, + (uint32_t)(((caddr_t) + (pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) - + pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing + + pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) >> 32)); + SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_CUR_DESCR_LOW, + (uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) - + pAC->RxPort[PortIndex].pRxDescrRing + + pAC->RxPort[PortIndex].VRxDescrRing) & 0xFFFFFFFF)); + SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_DESCR_HIGH, + (uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) - + pAC->RxPort[PortIndex].pRxDescrRing + + pAC->RxPort[PortIndex].VRxDescrRing) >> 32)); +} /* PortReInitBmu */ + + +/**************************************************************************** + * + * SkGeIsr - handle adapter interrupts + * + * Description: + * The interrupt routine is called when the network adapter + * generates an interrupt. It may also be called if another device + * shares this interrupt vector with the driver. + * + * Returns: N/A + * + */ +#if 0 +static void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs) +#else +void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs) +#endif +{ +struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id; +DEV_NET *pNet; +SK_AC *pAC; +SK_U32 IntSrc; /* interrupts source register contents */ + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + /* + * Check and process if its our interrupt + */ + SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc); + if (IntSrc == 0) { + return; + } + + while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) { +#if 0 /* software irq currently not used */ + if (IntSrc & IRQ_SW) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("Software IRQ\n")); + } +#endif + if (IntSrc & IRQ_EOF_RX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF RX1 IRQ\n")); + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + SK_PNMI_CNT_RX_INTR(pAC, 0); + } + if (IntSrc & IRQ_EOF_RX2) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF RX2 IRQ\n")); + ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE); + SK_PNMI_CNT_RX_INTR(pAC, 1); + } +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IRQ_EOF_AS_TX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF AS TX1 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 0); + spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + } + if (IntSrc & IRQ_EOF_AS_TX2) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF AS TX2 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 1); + spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); + } +#if 0 /* only if sync. queues used */ + if (IntSrc & IRQ_EOF_SY_TX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF SY TX1 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 1); + spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); + FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH); + spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); + ClearTxIrq(pAC, 0, TX_PRIO_HIGH); + } + if (IntSrc & IRQ_EOF_SY_TX2) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF SY TX2 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 1); + spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock); + FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH); + spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock); + ClearTxIrq(pAC, 1, TX_PRIO_HIGH); + } +#endif +#endif + + /* do all IO at once */ + if (IntSrc & IRQ_EOF_RX1) + ClearAndStartRx(pAC, 0); + if (IntSrc & IRQ_EOF_RX2) + ClearAndStartRx(pAC, 1); +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IRQ_EOF_AS_TX1) + ClearTxIrq(pAC, 0, TX_PRIO_LOW); + if (IntSrc & IRQ_EOF_AS_TX2) + ClearTxIrq(pAC, 1, TX_PRIO_LOW); +#endif + SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc); + } /* while (IntSrc & IRQ_MASK != 0) */ + + if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("SPECIAL IRQ DP-Cards => %x\n", IntSrc)); + pAC->CheckQueue = SK_FALSE; + spin_lock(&pAC->SlowPathLock); + if (IntSrc & SPECIAL_IRQS) + SkGeSirqIsr(pAC, pAC->IoBase, IntSrc); + + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock(&pAC->SlowPathLock); + } + /* + * do it all again is case we cleared an interrupt that + * came in after handling the ring (OUTs may be delayed + * in hardware buffers, but are through after IN) + */ + + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE); + + if (pAC->CheckQueue) { + pAC->CheckQueue = SK_FALSE; + spin_lock(&pAC->SlowPathLock); + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock(&pAC->SlowPathLock); + } + + + /* IRQ is processed - Enable IRQs again*/ + SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + + return; +} /* SkGeIsr */ + + +/**************************************************************************** + * + * SkGeIsrOnePort - handle adapter interrupts for single port adapter + * + * Description: + * The interrupt routine is called when the network adapter + * generates an interrupt. It may also be called if another device + * shares this interrupt vector with the driver. + * This is the same as above, but handles only one port. + * + * Returns: N/A + * + */ +#if 0 +static void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs) +#else +void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs) +#endif +{ +struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id; +DEV_NET *pNet; +SK_AC *pAC; +SK_U32 IntSrc; /* interrupts source register contents */ + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + /* + * Check and process if its our interrupt + */ + SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc); + if (IntSrc == 0) { + return; + } + + while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) { +#if 0 /* software irq currently not used */ + if (IntSrc & IRQ_SW) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("Software IRQ\n")); + } +#endif + if (IntSrc & IRQ_EOF_RX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF RX1 IRQ\n")); + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + SK_PNMI_CNT_RX_INTR(pAC, 0); + } +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IRQ_EOF_AS_TX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF AS TX1 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 0); + spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + } +#if 0 /* only if sync. queues used */ + if (IntSrc & IRQ_EOF_SY_TX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF SY TX1 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 0); + spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); + FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH); + spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); + ClearTxIrq(pAC, 0, TX_PRIO_HIGH); + } +#endif +#endif + + /* do all IO at once */ + if (IntSrc & IRQ_EOF_RX1) + ClearAndStartRx(pAC, 0); +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IRQ_EOF_AS_TX1) + ClearTxIrq(pAC, 0, TX_PRIO_LOW); +#endif + SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc); + } /* while (IntSrc & IRQ_MASK != 0) */ + + if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("SPECIAL IRQ SP-Cards => %x\n", IntSrc)); + pAC->CheckQueue = SK_FALSE; + spin_lock(&pAC->SlowPathLock); + if (IntSrc & SPECIAL_IRQS) + SkGeSirqIsr(pAC, pAC->IoBase, IntSrc); + + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock(&pAC->SlowPathLock); + } + /* + * do it all again is case we cleared an interrupt that + * came in after handling the ring (OUTs may be delayed + * in hardware buffers, but are through after IN) + */ + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + + /* IRQ is processed - Enable IRQs again*/ + SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + + return; +} /* SkGeIsrOnePort */ + + +/**************************************************************************** + * + * SkGeOpen - handle start of initialized adapter + * + * Description: + * This function starts the initialized adapter. + * The board level variable is set and the adapter is + * brought to full functionality. + * The device flags are set for operation. + * Do all necessary level 2 initialization, enable interrupts and + * give start command to RLMT. + * + * Returns: + * 0 on success + * != 0 on error + */ +#if 0 +static int SkGeOpen( +#else +int SkGeOpen( +#endif +struct SK_NET_DEVICE *dev) +{ + DEV_NET *pNet; + SK_AC *pAC; + unsigned long Flags; /* for spin lock */ + int i; + SK_EVPARA EvPara; /* an event parameter union */ + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC)); + + if (pAC->BoardLevel == 0) { + /* level 1 init common modules here */ + if (SkGeInit(pAC, pAC->IoBase, 1) != 0) { + printk("%s: HWInit (1) failed.\n", pAC->dev[pNet->PortNr]->name); + return (-1); + } + SkI2cInit (pAC, pAC->IoBase, 1); + SkEventInit (pAC, pAC->IoBase, 1); + SkPnmiInit (pAC, pAC->IoBase, 1); + SkAddrInit (pAC, pAC->IoBase, 1); + SkRlmtInit (pAC, pAC->IoBase, 1); + SkTimerInit (pAC, pAC->IoBase, 1); + pAC->BoardLevel = 1; + } + + if (pAC->BoardLevel != 2) { + /* tschilling: Level 2 init modules here, check return value. */ + if (SkGeInit(pAC, pAC->IoBase, 2) != 0) { + printk("%s: HWInit (2) failed.\n", pAC->dev[pNet->PortNr]->name); + return (-1); + } + SkI2cInit (pAC, pAC->IoBase, 2); + SkEventInit (pAC, pAC->IoBase, 2); + SkPnmiInit (pAC, pAC->IoBase, 2); + SkAddrInit (pAC, pAC->IoBase, 2); + SkRlmtInit (pAC, pAC->IoBase, 2); + SkTimerInit (pAC, pAC->IoBase, 2); + pAC->BoardLevel = 2; + } + + for (i=0; iGIni.GIMacsFound; i++) { + /* Enable transmit descriptor polling. */ + SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE); + FillRxRing(pAC, &pAC->RxPort[i]); + } + SkGeYellowLED(pAC, pAC->IoBase, 1); + +#ifdef USE_INT_MOD +/* moderate only TX complete interrupts (these are not time critical) */ +#define IRQ_MOD_MASK (IRQ_EOF_AS_TX1 | IRQ_EOF_AS_TX2) + { + unsigned long ModBase; + ModBase = 53125000 / INTS_PER_SEC; + SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); + SK_OUT32(pAC->IoBase, B2_IRQM_MSK, IRQ_MOD_MASK); + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START); + } +#endif + + /* enable Interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK); + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + + if ((pAC->RlmtMode != 0) && (pAC->MaxPorts == 0)) { + EvPara.Para32[0] = pAC->RlmtNets; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, + EvPara); + EvPara.Para32[0] = pAC->RlmtMode; + EvPara.Para32[1] = 0; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE, + EvPara); + } + + EvPara.Para32[0] = pNet->NetNr; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + pAC->MaxPorts++; + pNet->Up = 1; + + MOD_INC_USE_COUNT; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeOpen suceeded\n")); + + return (0); +} /* SkGeOpen */ + + +/**************************************************************************** + * + * SkGeClose - Stop initialized adapter + * + * Description: + * Close initialized adapter. + * + * Returns: + * 0 - on success + * error code - on error + */ +#if 0 +static int SkGeClose( +#else +int SkGeClose( +#endif +struct SK_NET_DEVICE *dev) +{ + DEV_NET *pNet; + SK_AC *pAC; + + unsigned long Flags; /* for spin lock */ + int i; + int PortIdx; + SK_EVPARA EvPara; + + netif_stop_queue(dev); + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + if (pAC->RlmtNets == 1) + PortIdx = pAC->ActivePort; + else + PortIdx = pNet->NetNr; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC)); + + /* + * Clear multicast table, promiscuous mode .... + */ + SkAddrMcClear(pAC, pAC->IoBase, PortIdx, 0); + SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx, + SK_PROM_MODE_NONE); + + if (pAC->MaxPorts == 1) { + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + EvPara.Para32[0] = pNet->NetNr; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + /* stop the hardware */ + SkGeDeInit(pAC, pAC->IoBase); + pAC->BoardLevel = 0; + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + } else { + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + EvPara.Para32[0] = pNet->NetNr; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + /* Stop port */ + spin_lock_irqsave(&pAC->TxPort[pNet->PortNr] + [TX_PRIO_LOW].TxDesRingLock, Flags); + SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, + SK_STOP_ALL, SK_HARD_RST); + spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr] + [TX_PRIO_LOW].TxDesRingLock, Flags); + } + + if (pAC->RlmtNets == 1) { + /* clear all descriptor rings */ + for (i=0; iGIni.GIMacsFound; i++) { + ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE); + ClearRxRing(pAC, &pAC->RxPort[i]); + ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]); + } + } else { + /* clear port descriptor rings */ + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE); + ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]); + ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]); + } + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeClose: done ")); + + pAC->MaxPorts--; + pNet->Up = 0; + MOD_DEC_USE_COUNT; + + return (0); +} /* SkGeClose */ + + +/***************************************************************************** + * + * SkGeXmit - Linux frame transmit function + * + * Description: + * The system calls this function to send frames onto the wire. + * It puts the frame in the tx descriptor ring. If the ring is + * full then, the 'tbusy' flag is set. + * + * Returns: + * 0, if everything is ok + * !=0, on error + * WARNING: returning 1 in 'tbusy' case caused system crashes (double + * allocated skb's) !!! + */ +#if 0 +static int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev) +#else +int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev) +#endif +{ +DEV_NET *pNet; +SK_AC *pAC; +int Rc; /* return code of XmitFrame */ + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + +#if 0 + if ((!skb_shinfo(skb)->nr_frags) || +#else + if (1 || +#endif + (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) { + /* Don't activate scatter-gather and hardware checksum */ + + if (pAC->RlmtNets == 2) + Rc = XmitFrame( + pAC, + &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW], + skb); + else + Rc = XmitFrame( + pAC, + &pAC->TxPort[pAC->ActivePort][TX_PRIO_LOW], + skb); + } else { +#if 0 + /* scatter-gather and hardware TCP checksumming anabled*/ + if (pAC->RlmtNets == 2) + Rc = XmitFrameSG( + pAC, + &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW], + skb); + else + Rc = XmitFrameSG( + pAC, + &pAC->TxPort[pAC->ActivePort][TX_PRIO_LOW], + skb); +#endif + } + + /* Transmitter out of resources? */ + if (Rc <= 0) { + netif_stop_queue(dev); + } + + /* If not taken, give buffer ownership back to the + * queueing layer. + */ + if (Rc < 0) + return (1); + +#if 0 + dev->trans_start = jiffies; +#endif + return (0); +} /* SkGeXmit */ + + +/***************************************************************************** + * + * XmitFrame - fill one socket buffer into the transmit ring + * + * Description: + * This function puts a message into the transmit descriptor ring + * if there is a descriptors left. + * Linux skb's consist of only one continuous buffer. + * The first step locks the ring. It is held locked + * all time to avoid problems with SWITCH_../PORT_RESET. + * Then the descriptoris allocated. + * The second part is linking the buffer to the descriptor. + * At the very last, the Control field of the descriptor + * is made valid for the BMU and a start TX command is given + * if necessary. + * + * Returns: + * > 0 - on succes: the number of bytes in the message + * = 0 - on resource shortage: this frame sent or dropped, now + * the ring is full ( -> set tbusy) + * < 0 - on failure: other problems ( -> return failure to upper layers) + */ +static int XmitFrame( +SK_AC *pAC, /* pointer to adapter context */ +TX_PORT *pTxPort, /* pointer to struct of port to send to */ +struct sk_buff *pMessage) /* pointer to send-message */ +{ +TXD *pTxd; /* the rxd to fill */ +unsigned long Flags; +SK_U64 PhysAddr; +int BytesSend; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("X")); + + spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); +#ifndef USE_TX_COMPLETE + FreeTxDescriptors(pAC, pTxPort); +#endif + if (pTxPort->TxdRingFree == 0) { + /* no enough free descriptors in ring at the moment */ + FreeTxDescriptors(pAC, pTxPort); + if (pTxPort->TxdRingFree == 0) { + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); + SK_PNMI_CNT_NO_TX_BUF(pAC, pTxPort->PortIndex); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_TX_PROGRESS, + ("XmitFrame failed\n")); + /* this message can not be sent now */ + /* Because tbusy seems to be set, the message should not be freed here */ + /* It will be used by the scheduler of the ethernet handler */ + return (-1); + } + } + /* advance head counter behind descriptor needed for this frame */ + pTxd = pTxPort->pTxdRingHead; + pTxPort->pTxdRingHead = pTxd->pNextTxd; + pTxPort->TxdRingFree--; + /* the needed descriptor is reserved now */ + + /* + * everything allocated ok, so add buffer to descriptor + */ + +#ifdef SK_DUMP_TX + DumpMsg(pMessage, "XmitFrame"); +#endif + + /* set up descriptor and CONTROL dword */ +#if 0 + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + virt_to_page(pMessage->data), + ((unsigned long) pMessage->data & + ~PAGE_MASK), + pMessage->len, + PCI_DMA_TODEVICE); +#else + PhysAddr = (SK_U64) pci_phys_to_mem(pAC->PciDev, (u32) pMessage->data); +#endif + pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32); + pTxd->pMBuf = pMessage; + pTxd->TBControl = TX_CTRL_OWN_BMU | TX_CTRL_STF | + TX_CTRL_CHECK_DEFAULT | TX_CTRL_SOFTWARE | +#ifdef USE_TX_COMPLETE + TX_CTRL_EOF | TX_CTRL_EOF_IRQ | pMessage->len; +#else + TX_CTRL_EOF | pMessage->len; +#endif + + if ((pTxPort->pTxdRingPrev->TBControl & TX_CTRL_OWN_BMU) == 0) { + /* previous descriptor already done, so give tx start cmd */ + /* StartTx(pAC, pTxPort->HwAddr); */ + SK_OUT8(pTxPort->HwAddr, TX_Q_CTRL, TX_Q_CTRL_START); + } + pTxPort->pTxdRingPrev = pTxd; + + + BytesSend = pMessage->len; + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); + /* after releasing the lock, the skb may be immidiately freed */ + if (pTxPort->TxdRingFree != 0) + return (BytesSend); + else + return (0); + +} /* XmitFrame */ + +/***************************************************************************** + * + * XmitFrameSG - fill one socket buffer into the transmit ring + * (use SG and TCP/UDP hardware checksumming) + * + * Description: + * This function puts a message into the transmit descriptor ring + * if there is a descriptors left. + * + * Returns: + * > 0 - on succes: the number of bytes in the message + * = 0 - on resource shortage: this frame sent or dropped, now + * the ring is full ( -> set tbusy) + * < 0 - on failure: other problems ( -> return failure to upper layers) + */ +#if 0 +static int XmitFrameSG( +SK_AC *pAC, /* pointer to adapter context */ +TX_PORT *pTxPort, /* pointer to struct of port to send to */ +struct sk_buff *pMessage) /* pointer to send-message */ +{ + + int i; + int BytesSend; + int hlength; + int protocol; + skb_frag_t *sk_frag; + TXD *pTxd; + TXD *pTxdFst; + TXD *pTxdLst; + SK_U64 PhysAddr; + unsigned long Flags; + + spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); +#ifndef USE_TX_COMPLETE + FreeTxDescriptors(pAC, pTxPort); +#endif + if ((skb_shinfo(pMessage)->nr_frags +1) > pTxPort->TxdRingFree) { + FreeTxDescriptors(pAC, pTxPort); + if ((skb_shinfo(pMessage)->nr_frags + 1) > pTxPort->TxdRingFree) { + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); + SK_PNMI_CNT_NO_TX_BUF(pAC, pTxPort->PortIndex); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_TX_PROGRESS, + ("XmitFrameSG failed - Ring full\n")); + /* this message can not be sent now */ + return(-1); + } + } + + + pTxd = pTxPort->pTxdRingHead; + pTxdFst = pTxd; + pTxdLst = pTxd; + BytesSend = 0; + protocol = 0; + + /* map first fragment (header) */ + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + virt_to_page(pMessage->data), + ((unsigned long) pMessage->data & ~PAGE_MASK), + skb_headlen(pMessage), + PCI_DMA_TODEVICE); + + pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32); + + /* HW checksum? */ + if (pMessage->ip_summed == CHECKSUM_HW) { + pTxd->TBControl = TX_CTRL_STF | + TX_CTRL_ST_FWD | + skb_headlen(pMessage); + + /* We have to use the opcode for tcp here because the opcode for + udp is not working in the hardware yet (revision 2.0)*/ + protocol = ((SK_U8)pMessage->data[23] & 0xf); + if ((protocol == 17) && (pAC->GIni.GIChipRev != 0)) + pTxd->TBControl |= BMU_UDP_CHECK; + else + pTxd->TBControl |= BMU_TCP_CHECK ; + + hlength = ((SK_U8)pMessage->data[14] & 0xf) * 4; + pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */ + pTxd->TcpSumSt = 14+hlength+16; + pTxd->TcpSumWr = 14+hlength; + + } else { + pTxd->TBControl = TX_CTRL_CHECK_DEFAULT | + TX_CTRL_SOFTWARE | + TX_CTRL_STF | + skb_headlen(pMessage); + } + + pTxd = pTxd->pNextTxd; + pTxPort->TxdRingFree--; + BytesSend += skb_headlen(pMessage); + + + /* Map SG fragments */ + for (i = 0; i < skb_shinfo(pMessage)->nr_frags; i++) { + sk_frag = &skb_shinfo(pMessage)->frags[i]; + + /* we already have the proper value in entry */ + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + sk_frag->page, + sk_frag->page_offset, + sk_frag->size, + PCI_DMA_TODEVICE); + + pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32); + pTxd->pMBuf = pMessage; + + /* HW checksum */ + if (pMessage->ip_summed == CHECKSUM_HW) { + pTxd->TBControl = TX_CTRL_OWN_BMU | + TX_CTRL_SOFTWARE | + TX_CTRL_ST_FWD; + + /* We have to use the opcode for tcp here because the opcode for + udp is not working in the hardware yet (revision 2.0)*/ + if ((protocol == 17) && (pAC->GIni.GIChipRev != 0)) + pTxd->TBControl |= BMU_UDP_CHECK ; + else + pTxd->TBControl |= BMU_TCP_CHECK ; + + } else { + pTxd->TBControl = TX_CTRL_CHECK_DEFAULT | + TX_CTRL_SOFTWARE | + TX_CTRL_OWN_BMU; + } + + /* Last fragment */ + if( (i+1) == skb_shinfo(pMessage)->nr_frags ) { +#ifdef USE_TX_COMPLETE + pTxd->TBControl |= TX_CTRL_EOF | + TX_CTRL_EOF_IRQ | + sk_frag->size; +#else + pTxd->TBControl |= TX_CTRL_EOF | + sk_frag->size; +#endif + pTxdFst->TBControl |= TX_CTRL_OWN_BMU | + TX_CTRL_SOFTWARE; + + } else { + pTxd->TBControl |= sk_frag->size; + } + pTxdLst = pTxd; + pTxd = pTxd->pNextTxd; + pTxPort->TxdRingFree--; + BytesSend += sk_frag->size; + } + + if ((pTxPort->pTxdRingPrev->TBControl & TX_CTRL_OWN_BMU) == 0) { + /* previous descriptor already done, so give tx start cmd */ + /* StartTx(pAC, pTxPort->HwAddr); */ + SK_OUT8(pTxPort->HwAddr, TX_Q_CTRL, TX_Q_CTRL_START); + } + + pTxPort->pTxdRingPrev = pTxdLst; + pTxPort->pTxdRingHead = pTxd; + + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); + + if (pTxPort->TxdRingFree > 0) + return (BytesSend); + else + return (0); +} +#endif + + +void dump_frag( SK_U8 *data, int length) +{ + int i; + + printk("Length: %d\n", length); + for( i=0; i < length; i++ ) { + printk(" %02x", (SK_U8)*(data + i) ); + if( !((i+1) % 20) ) + printk("\n"); + } + printk("\n\n"); + +} + + +/***************************************************************************** + * + * FreeTxDescriptors - release descriptors from the descriptor ring + * + * Description: + * This function releases descriptors from a transmit ring if they + * have been sent by the BMU. + * If a descriptors is sent, it can be freed and the message can + * be freed, too. + * The SOFTWARE controllable bit is used to prevent running around a + * completely free ring for ever. If this bit is no set in the + * frame (by XmitFrame), this frame has never been sent or is + * already freed. + * The Tx descriptor ring lock must be held while calling this function !!! + * + * Returns: + * none + */ +static void FreeTxDescriptors( +SK_AC *pAC, /* pointer to the adapter context */ +TX_PORT *pTxPort) /* pointer to destination port structure */ +{ +TXD *pTxd; /* pointer to the checked descriptor */ +TXD *pNewTail; /* pointer to 'end' of the ring */ +SK_U32 Control; /* TBControl field of descriptor */ +SK_U64 PhysAddr; /* address of DMA mapping */ + + pNewTail = pTxPort->pTxdRingTail; + pTxd = pNewTail; + /* + * loop forever; exits if TX_CTRL_SOFTWARE bit not set in start frame + * or TX_CTRL_OWN_BMU bit set in any frame + */ + while (1) { + Control = pTxd->TBControl; + if ((Control & TX_CTRL_SOFTWARE) == 0) { + /* + * software controllable bit is set in first + * fragment when given to BMU. Not set means that + * this fragment was never sent or is already + * freed ( -> ring completely free now). + */ + pTxPort->pTxdRingTail = pTxd; + netif_wake_queue(pAC->dev[pTxPort->PortIndex]); + return; + } + if (Control & TX_CTRL_OWN_BMU) { + pTxPort->pTxdRingTail = pTxd; + if (pTxPort->TxdRingFree > 0) { + netif_wake_queue(pAC->dev[pTxPort->PortIndex]); + } + return; + } + + /* release the DMA mapping */ + PhysAddr = ((SK_U64) pTxd->VDataHigh) << (SK_U64) 32; + PhysAddr |= (SK_U64) pTxd->VDataLow; + pci_unmap_page(pAC->PciDev, PhysAddr, + pTxd->pMBuf->len, + PCI_DMA_TODEVICE); + + if (Control & TX_CTRL_EOF) + DEV_KFREE_SKB_ANY(pTxd->pMBuf); /* free message */ + + pTxPort->TxdRingFree++; + pTxd->TBControl &= ~TX_CTRL_SOFTWARE; + pTxd = pTxd->pNextTxd; /* point behind fragment with EOF */ + } /* while(forever) */ +} /* FreeTxDescriptors */ + +/***************************************************************************** + * + * FillRxRing - fill the receive ring with valid descriptors + * + * Description: + * This function fills the receive ring descriptors with data + * segments and makes them valid for the BMU. + * The active ring is filled completely, if possible. + * The non-active ring is filled only partial to save memory. + * + * Description of rx ring structure: + * head - points to the descriptor which will be used next by the BMU + * tail - points to the next descriptor to give to the BMU + * + * Returns: N/A + */ +static void FillRxRing( +SK_AC *pAC, /* pointer to the adapter context */ +RX_PORT *pRxPort) /* ptr to port struct for which the ring + should be filled */ +{ +unsigned long Flags; + + spin_lock_irqsave(&pRxPort->RxDesRingLock, Flags); + while (pRxPort->RxdRingFree > pRxPort->RxFillLimit) { + if(!FillRxDescriptor(pAC, pRxPort)) + break; + } + spin_unlock_irqrestore(&pRxPort->RxDesRingLock, Flags); +} /* FillRxRing */ + + +/***************************************************************************** + * + * FillRxDescriptor - fill one buffer into the receive ring + * + * Description: + * The function allocates a new receive buffer and + * puts it into the next descriptor. + * + * Returns: + * SK_TRUE - a buffer was added to the ring + * SK_FALSE - a buffer could not be added + */ +static SK_BOOL FillRxDescriptor( +SK_AC *pAC, /* pointer to the adapter context struct */ +RX_PORT *pRxPort) /* ptr to port struct of ring to fill */ +{ +struct sk_buff *pMsgBlock; /* pointer to a new message block */ +RXD *pRxd; /* the rxd to fill */ +SK_U16 Length; /* data fragment length */ +SK_U64 PhysAddr; /* physical address of a rx buffer */ + + pMsgBlock = alloc_skb(pAC->RxBufSize, GFP_ATOMIC); + if (pMsgBlock == NULL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_ENTRY, + ("%s: Allocation of rx buffer failed !\n", + pAC->dev[pRxPort->PortIndex]->name)); + SK_PNMI_CNT_NO_RX_BUF(pAC, pRxPort->PortIndex); + return(SK_FALSE); + } + skb_reserve(pMsgBlock, 2); /* to align IP frames */ + /* skb allocated ok, so add buffer */ + pRxd = pRxPort->pRxdRingTail; + pRxPort->pRxdRingTail = pRxd->pNextRxd; + pRxPort->RxdRingFree--; + Length = pAC->RxBufSize; +#if 0 + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + virt_to_page(pMsgBlock->data), + ((unsigned long) pMsgBlock->data & + ~PAGE_MASK), + pAC->RxBufSize - 2, + PCI_DMA_FROMDEVICE); +#else + PhysAddr = (SK_U64) pci_phys_to_mem(pAC->PciDev, (u32)pMsgBlock->data); +#endif + pRxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pRxd->VDataHigh = (SK_U32) (PhysAddr >> 32); + pRxd->pMBuf = pMsgBlock; + pRxd->RBControl = RX_CTRL_OWN_BMU | RX_CTRL_STF | + RX_CTRL_EOF_IRQ | RX_CTRL_CHECK_CSUM | Length; + return (SK_TRUE); + +} /* FillRxDescriptor */ + + +/***************************************************************************** + * + * ReQueueRxBuffer - fill one buffer back into the receive ring + * + * Description: + * Fill a given buffer back into the rx ring. The buffer + * has been previously allocated and aligned, and its phys. + * address calculated, so this is no more necessary. + * + * Returns: N/A + */ +static void ReQueueRxBuffer( +SK_AC *pAC, /* pointer to the adapter context struct */ +RX_PORT *pRxPort, /* ptr to port struct of ring to fill */ +struct sk_buff *pMsg, /* pointer to the buffer */ +SK_U32 PhysHigh, /* phys address high dword */ +SK_U32 PhysLow) /* phys address low dword */ +{ +RXD *pRxd; /* the rxd to fill */ +SK_U16 Length; /* data fragment length */ + + pRxd = pRxPort->pRxdRingTail; + pRxPort->pRxdRingTail = pRxd->pNextRxd; + pRxPort->RxdRingFree--; + Length = pAC->RxBufSize; + pRxd->VDataLow = PhysLow; + pRxd->VDataHigh = PhysHigh; + pRxd->pMBuf = pMsg; + pRxd->RBControl = RX_CTRL_OWN_BMU | RX_CTRL_STF | + RX_CTRL_EOF_IRQ | RX_CTRL_CHECK_CSUM | Length; + return; +} /* ReQueueRxBuffer */ + + +/***************************************************************************** + * + * ReceiveIrq - handle a receive IRQ + * + * Description: + * This function is called when a receive IRQ is set. + * It walks the receive descriptor ring and sends up all + * frames that are complete. + * + * Returns: N/A + */ +#if 0 +static void ReceiveIrq( +#else +void ReceiveIrq( +#endif + SK_AC *pAC, /* pointer to adapter context */ + RX_PORT *pRxPort, /* pointer to receive port struct */ + SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */ +{ +RXD *pRxd; /* pointer to receive descriptors */ +SK_U32 Control; /* control field of descriptor */ +struct sk_buff *pMsg; /* pointer to message holding frame */ +struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */ +int FrameLength; /* total length of received frame */ +SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */ +SK_EVPARA EvPara; /* an event parameter union */ +unsigned long Flags; /* for spin lock */ +int PortIndex = pRxPort->PortIndex; +unsigned int Offset; +unsigned int NumBytes; +unsigned int ForRlmt; +SK_BOOL IsBc; +SK_BOOL IsMc; +SK_BOOL IsBadFrame; /* Bad frame */ + +SK_U32 FrameStat; +unsigned short Csum1; +unsigned short Csum2; +unsigned short Type; +#if 0 +int Result; +#endif +SK_U64 PhysAddr; + +rx_start: + /* do forever; exit if RX_CTRL_OWN_BMU found */ + for ( pRxd = pRxPort->pRxdRingHead ; + pRxPort->RxdRingFree < pAC->RxDescrPerRing ; + pRxd = pRxd->pNextRxd, + pRxPort->pRxdRingHead = pRxd, + pRxPort->RxdRingFree ++) { + + /* + * For a better understanding of this loop + * Go through every descriptor beginning at the head + * Please note: the ring might be completely received so the OWN bit + * set is not a good crirteria to leave that loop. + * Therefore the RingFree counter is used. + * On entry of this loop pRxd is a pointer to the Rxd that needs + * to be checked next. + */ + + Control = pRxd->RBControl; + + /* check if this descriptor is ready */ + if ((Control & RX_CTRL_OWN_BMU) != 0) { + /* this descriptor is not yet ready */ + /* This is the usual end of the loop */ + /* We don't need to start the ring again */ + FillRxRing(pAC, pRxPort); + return; + } + + /* get length of frame and check it */ + FrameLength = Control & RX_CTRL_LEN_MASK; + if (FrameLength > pAC->RxBufSize) { + goto rx_failed; + } + + /* check for STF and EOF */ + if ((Control & (RX_CTRL_STF | RX_CTRL_EOF)) != + (RX_CTRL_STF | RX_CTRL_EOF)) { + goto rx_failed; + } + + /* here we have a complete frame in the ring */ + pMsg = pRxd->pMBuf; + + FrameStat = pRxd->FrameStat; + + /* check for frame length mismatch */ +#define XMR_FS_LEN_SHIFT 18 +#define GMR_FS_LEN_SHIFT 16 + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: Frame length mismatch (%u/%u).\n", + FrameLength, + (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT))); + goto rx_failed; + } + } + else { + if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: Frame length mismatch (%u/%u).\n", + FrameLength, + (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT))); + goto rx_failed; + } + } + + /* Set Rx Status */ + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + IsBc = (FrameStat & XMR_FS_BC) != 0; + IsMc = (FrameStat & XMR_FS_MC) != 0; + IsBadFrame = (FrameStat & + (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0; + } else { + IsBc = (FrameStat & GMR_FS_BC) != 0; + IsMc = (FrameStat & GMR_FS_MC) != 0; + IsBadFrame = (((FrameStat & GMR_FS_ANY_ERR) != 0) || + ((FrameStat & GMR_FS_RX_OK) == 0)); + } + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 0, + ("Received frame of length %d on port %d\n", + FrameLength, PortIndex)); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 0, + ("Number of free rx descriptors: %d\n", + pRxPort->RxdRingFree)); +/* DumpMsg(pMsg, "Rx"); */ + + if ((Control & RX_CTRL_STAT_VALID) != RX_CTRL_STAT_VALID || + (IsBadFrame)) { +#if 0 + (FrameStat & (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0) { +#endif + /* there is a receive error in this frame */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: Error in received frame, dropped!\n" + "Control: %x\nRxStat: %x\n", + Control, FrameStat)); + + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + pci_dma_sync_single(pAC->PciDev, + (dma_addr_t) PhysAddr, + FrameLength, + PCI_DMA_FROMDEVICE); + ReQueueRxBuffer(pAC, pRxPort, pMsg, + pRxd->VDataHigh, pRxd->VDataLow); + + continue; + } + + /* + * if short frame then copy data to reduce memory waste + */ + if ((FrameLength < SK_COPY_THRESHOLD) && + ((pNewMsg = alloc_skb(FrameLength+2, GFP_ATOMIC)) != NULL)) { + /* + * Short frame detected and allocation successfull + */ + /* use new skb and copy data */ + skb_reserve(pNewMsg, 2); + skb_put(pNewMsg, FrameLength); + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + + pci_dma_sync_single(pAC->PciDev, + (dma_addr_t) PhysAddr, + FrameLength, + PCI_DMA_FROMDEVICE); + eth_copy_and_sum(pNewMsg, pMsg->data, + FrameLength, 0); + ReQueueRxBuffer(pAC, pRxPort, pMsg, + pRxd->VDataHigh, pRxd->VDataLow); + pMsg = pNewMsg; + + } + else { + /* + * if large frame, or SKB allocation failed, pass + * the SKB directly to the networking + */ + + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + + /* release the DMA mapping */ + pci_unmap_single(pAC->PciDev, + PhysAddr, + pAC->RxBufSize - 2, + PCI_DMA_FROMDEVICE); + + /* set length in message */ + skb_put(pMsg, FrameLength); + /* hardware checksum */ + Type = ntohs(*((short*)&pMsg->data[12])); + if (Type == 0x800) { + Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff); + Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff); +#if 0 + if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) && + (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) || + (pAC->GIni.GIChipId == CHIP_ID_YUKON)) { + Result = SkCsGetReceiveInfo(pAC, + &pMsg->data[14], + Csum1, Csum2, pRxPort->PortIndex); + if (Result == + SKCS_STATUS_IP_FRAGMENT || + Result == + SKCS_STATUS_IP_CSUM_OK || + Result == + SKCS_STATUS_TCP_CSUM_OK || + Result == + SKCS_STATUS_UDP_CSUM_OK) { + pMsg->ip_summed = + CHECKSUM_UNNECESSARY; + } else { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: CRC error. Frame dropped!\n")); + goto rx_failed; + } + }/* checksumControl calculation valid */ +#endif + } /* IP frame */ + } /* frame > SK_COPY_TRESHOLD */ + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V")); + ForRlmt = SK_RLMT_RX_PROTOCOL; +#if 0 + IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC; +#endif + SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength, + IsBc, &Offset, &NumBytes); + if (NumBytes != 0) { +#if 0 + IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC; +#endif + SK_RLMT_LOOKAHEAD(pAC, PortIndex, + &pMsg->data[Offset], + IsBc, IsMc, &ForRlmt); + } + if (ForRlmt == SK_RLMT_RX_PROTOCOL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W")); + /* send up only frames from active port */ + if ((PortIndex == pAC->ActivePort) || + (pAC->RlmtNets == 2)) { + /* frame for upper layer */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U")); +#ifdef xDEBUG + DumpMsg(pMsg, "Rx"); +#endif + SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC, + FrameLength, pRxPort->PortIndex); + +#if 0 + pMsg->dev = pAC->dev[pRxPort->PortIndex]; + pMsg->protocol = eth_type_trans(pMsg, + pAC->dev[pRxPort->PortIndex]); + netif_rx(pMsg); + pAC->dev[pRxPort->PortIndex]->last_rx = jiffies; +#else + NetReceive(pMsg->data, pMsg->len); + dev_kfree_skb_any(pMsg); +#endif + } + else { + /* drop frame */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("D")); + DEV_KFREE_SKB(pMsg); + } + + } /* if not for rlmt */ + else { + /* packet for rlmt */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, ("R")); + pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC, + pAC->IoBase, FrameLength); + if (pRlmtMbuf != NULL) { + pRlmtMbuf->pNext = NULL; + pRlmtMbuf->Length = FrameLength; + pRlmtMbuf->PortIdx = PortIndex; + EvPara.pParaPtr = pRlmtMbuf; + memcpy((char*)(pRlmtMbuf->pData), + (char*)(pMsg->data), + FrameLength); + + /* SlowPathLock needed? */ + if (SlowPathLock == SK_TRUE) { + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + SkEventQueue(pAC, SKGE_RLMT, + SK_RLMT_PACKET_RECEIVED, + EvPara); + pAC->CheckQueue = SK_TRUE; + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + } else { + SkEventQueue(pAC, SKGE_RLMT, + SK_RLMT_PACKET_RECEIVED, + EvPara); + pAC->CheckQueue = SK_TRUE; + } + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("Q")); + } +#if 0 + if ((pAC->dev[pRxPort->PortIndex]->flags & + (IFF_PROMISC | IFF_ALLMULTI)) != 0 || + (ForRlmt & SK_RLMT_RX_PROTOCOL) == + SK_RLMT_RX_PROTOCOL) { + pMsg->dev = pAC->dev[pRxPort->PortIndex]; + pMsg->protocol = eth_type_trans(pMsg, + pAC->dev[pRxPort->PortIndex]); + netif_rx(pMsg); + pAC->dev[pRxPort->PortIndex]->last_rx = jiffies; + } +#else + if (0) { + } +#endif + else { + DEV_KFREE_SKB(pMsg); + } + + } /* if packet for rlmt */ + } /* for ... scanning the RXD ring */ + + /* RXD ring is empty -> fill and restart */ + FillRxRing(pAC, pRxPort); + /* do not start if called from Close */ + if (pAC->BoardLevel > 0) { + ClearAndStartRx(pAC, PortIndex); + } + return; + +rx_failed: + /* remove error frame */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR, + ("Schrottdescriptor, length: 0x%x\n", FrameLength)); + + /* release the DMA mapping */ + + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + pci_unmap_page(pAC->PciDev, + PhysAddr, + pAC->RxBufSize - 2, + PCI_DMA_FROMDEVICE); + DEV_KFREE_SKB_IRQ(pRxd->pMBuf); + pRxd->pMBuf = NULL; + pRxPort->RxdRingFree++; + pRxPort->pRxdRingHead = pRxd->pNextRxd; + goto rx_start; + +} /* ReceiveIrq */ + + +/***************************************************************************** + * + * ClearAndStartRx - give a start receive command to BMU, clear IRQ + * + * Description: + * This function sends a start command and a clear interrupt + * command for one receive queue to the BMU. + * + * Returns: N/A + * none + */ +static void ClearAndStartRx( +SK_AC *pAC, /* pointer to the adapter context */ +int PortIndex) /* index of the receive port (XMAC) */ +{ + SK_OUT8(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_CTRL, + RX_Q_CTRL_START | RX_Q_CTRL_CLR_I_EOF); +} /* ClearAndStartRx */ + + +/***************************************************************************** + * + * ClearTxIrq - give a clear transmit IRQ command to BMU + * + * Description: + * This function sends a clear tx IRQ command for one + * transmit queue to the BMU. + * + * Returns: N/A + */ +static void ClearTxIrq( +SK_AC *pAC, /* pointer to the adapter context */ +int PortIndex, /* index of the transmit port (XMAC) */ +int Prio) /* priority or normal queue */ +{ + SK_OUT8(pAC->IoBase, TxQueueAddr[PortIndex][Prio]+TX_Q_CTRL, + TX_Q_CTRL_CLR_I_EOF); +} /* ClearTxIrq */ + + +/***************************************************************************** + * + * ClearRxRing - remove all buffers from the receive ring + * + * Description: + * This function removes all receive buffers from the ring. + * The receive BMU must be stopped before calling this function. + * + * Returns: N/A + */ +static void ClearRxRing( +SK_AC *pAC, /* pointer to adapter context */ +RX_PORT *pRxPort) /* pointer to rx port struct */ +{ +RXD *pRxd; /* pointer to the current descriptor */ +unsigned long Flags; +SK_U64 PhysAddr; + + if (pRxPort->RxdRingFree == pAC->RxDescrPerRing) { + return; + } + spin_lock_irqsave(&pRxPort->RxDesRingLock, Flags); + pRxd = pRxPort->pRxdRingHead; + do { + if (pRxd->pMBuf != NULL) { + + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + pci_unmap_page(pAC->PciDev, + PhysAddr, + pAC->RxBufSize - 2, + PCI_DMA_FROMDEVICE); + DEV_KFREE_SKB(pRxd->pMBuf); + pRxd->pMBuf = NULL; + } + pRxd->RBControl &= RX_CTRL_OWN_BMU; + pRxd = pRxd->pNextRxd; + pRxPort->RxdRingFree++; + } while (pRxd != pRxPort->pRxdRingTail); + pRxPort->pRxdRingTail = pRxPort->pRxdRingHead; + spin_unlock_irqrestore(&pRxPort->RxDesRingLock, Flags); +} /* ClearRxRing */ + + +/***************************************************************************** + * + * ClearTxRing - remove all buffers from the transmit ring + * + * Description: + * This function removes all transmit buffers from the ring. + * The transmit BMU must be stopped before calling this function + * and transmitting at the upper level must be disabled. + * The BMU own bit of all descriptors is cleared, the rest is + * done by calling FreeTxDescriptors. + * + * Returns: N/A + */ +static void ClearTxRing( +SK_AC *pAC, /* pointer to adapter context */ +TX_PORT *pTxPort) /* pointer to tx prt struct */ +{ +TXD *pTxd; /* pointer to the current descriptor */ +int i; +unsigned long Flags; + + spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); + pTxd = pTxPort->pTxdRingHead; + for (i=0; iTxDescrPerRing; i++) { + pTxd->TBControl &= ~TX_CTRL_OWN_BMU; + pTxd = pTxd->pNextTxd; + } + FreeTxDescriptors(pAC, pTxPort); + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); +} /* ClearTxRing */ + + +#if 0 +/***************************************************************************** + * + * SetQueueSizes - configure the sizes of rx and tx queues + * + * Description: + * This function assigns the sizes for active and passive port + * to the appropriate HWinit structure variables. + * The passive port(s) get standard values, all remaining RAM + * is given to the active port. + * The queue sizes are in kbyte and must be multiple of 8. + * The limits for the number of buffers filled into the rx rings + * is also set in this routine. + * + * Returns: + * none + */ +static void SetQueueSizes( +SK_AC *pAC) /* pointer to the adapter context */ +{ +int StandbyRam; /* adapter RAM used for a standby port */ +int RemainingRam; /* adapter RAM available for the active port */ +int RxRam; /* RAM used for the active port receive queue */ +int i; /* loop counter */ + +if (pAC->RlmtNets == 1) { + StandbyRam = SK_RLMT_STANDBY_QRXSIZE + SK_RLMT_STANDBY_QXASIZE + + SK_RLMT_STANDBY_QXSSIZE; + RemainingRam = pAC->GIni.GIRamSize - + (pAC->GIni.GIMacsFound-1) * StandbyRam; + for (i=0; iGIni.GIMacsFound; i++) { + pAC->GIni.GP[i].PRxQSize = SK_RLMT_STANDBY_QRXSIZE; + pAC->GIni.GP[i].PXSQSize = SK_RLMT_STANDBY_QXSSIZE; + pAC->GIni.GP[i].PXAQSize = SK_RLMT_STANDBY_QXASIZE; + } + RxRam = (RemainingRam * 8 / 10) & ~7; + pAC->GIni.GP[pAC->ActivePort].PRxQSize = RxRam; + pAC->GIni.GP[pAC->ActivePort].PXSQSize = 0; + pAC->GIni.GP[pAC->ActivePort].PXAQSize = + (RemainingRam - RxRam) & ~7; + pAC->RxQueueSize = RxRam; + pAC->TxSQueueSize = 0; + pAC->TxAQueueSize = (RemainingRam - RxRam) & ~7; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("queue sizes settings - rx:%d txA:%d txS:%d\n", + pAC->RxQueueSize,pAC->TxAQueueSize, pAC->TxSQueueSize)); +} else { + RemainingRam = pAC->GIni.GIRamSize/pAC->GIni.GIMacsFound; + RxRam = (RemainingRam * 8 / 10) & ~7; + for (i=0; iGIni.GIMacsFound; i++) { + pAC->GIni.GP[i].PRxQSize = RxRam; + pAC->GIni.GP[i].PXSQSize = 0; + pAC->GIni.GP[i].PXAQSize = (RemainingRam - RxRam) & ~7; + } + + pAC->RxQueueSize = RxRam; + pAC->TxSQueueSize = 0; + pAC->TxAQueueSize = (RemainingRam - RxRam) & ~7; +} + for (i=0; iRxPort[i].RxFillLimit = pAC->RxDescrPerRing; + } + + if (pAC->RlmtNets == 2) { + for (i=0; iGIni.GIMacsFound; i++) { + pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing - 100; + } + } else { + for (i=0; iGIni.GIMacsFound; i++) { + pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing - 100; + } + /* + * Do not set the Limit to 0, because this could cause + * wrap around with ReQueue'ed buffers (a buffer could + * be requeued in the same position, made accessable to + * the hardware, and the hardware could change its + * contents! + */ + pAC->RxPort[pAC->ActivePort].RxFillLimit = 1; + } + +#ifdef DEBUG + for (i=0; iGIni.GIMacsFound; i++) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("i: %d, RxQSize: %d, PXSQsize: %d, PXAQSize: %d\n", + i, + pAC->GIni.GP[i].PRxQSize, + pAC->GIni.GP[i].PXSQSize, + pAC->GIni.GP[i].PXAQSize)); + } +#endif +} /* SetQueueSizes */ + + +/***************************************************************************** + * + * SkGeSetMacAddr - Set the hardware MAC address + * + * Description: + * This function sets the MAC address used by the adapter. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p) +{ + +DEV_NET *pNet = (DEV_NET*) dev->priv; +SK_AC *pAC = pNet->pAC; + +struct sockaddr *addr = p; +unsigned long Flags; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeSetMacAddr starts now...\n")); + if(netif_running(dev)) + return -EBUSY; + + memcpy(dev->dev_addr, addr->sa_data,dev->addr_len); + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + + if (pAC->RlmtNets == 2) + SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr, + (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS); + else + SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort, + (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS); + + + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + return 0; +} /* SkGeSetMacAddr */ +#endif + + +/***************************************************************************** + * + * SkGeSetRxMode - set receive mode + * + * Description: + * This function sets the receive mode of an adapter. The adapter + * supports promiscuous mode, allmulticast mode and a number of + * multicast addresses. If more multicast addresses the available + * are selected, a hash function in the hardware is used. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +#if 0 +static void SkGeSetRxMode(struct SK_NET_DEVICE *dev) +{ + +DEV_NET *pNet; +SK_AC *pAC; + +struct dev_mc_list *pMcList; +int i; +int PortIdx; +unsigned long Flags; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeSetRxMode starts now... ")); + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + if (pAC->RlmtNets == 1) + PortIdx = pAC->ActivePort; + else + PortIdx = pNet->NetNr; + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + if (dev->flags & IFF_PROMISC) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("PROMISCUOUS mode\n")); + SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx, + SK_PROM_MODE_LLC); + } else if (dev->flags & IFF_ALLMULTI) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("ALLMULTI mode\n")); + SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx, + SK_PROM_MODE_ALL_MC); + } else { + SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx, + SK_PROM_MODE_NONE); + SkAddrMcClear(pAC, pAC->IoBase, PortIdx, 0); + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("Number of MC entries: %d ", dev->mc_count)); + + pMcList = dev->mc_list; + for (i=0; imc_count; i++, pMcList = pMcList->next) { + SkAddrMcAdd(pAC, pAC->IoBase, PortIdx, + (SK_MAC_ADDR*)pMcList->dmi_addr, 0); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MCA, + ("%02x:%02x:%02x:%02x:%02x:%02x\n", + pMcList->dmi_addr[0], + pMcList->dmi_addr[1], + pMcList->dmi_addr[2], + pMcList->dmi_addr[3], + pMcList->dmi_addr[4], + pMcList->dmi_addr[5])); + } + SkAddrMcUpdate(pAC, pAC->IoBase, PortIdx); + } + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + return; +} /* SkGeSetRxMode */ + + +/***************************************************************************** + * + * SkGeChangeMtu - set the MTU to another value + * + * Description: + * This function sets is called whenever the MTU size is changed + * (ifconfig mtu xxx dev ethX). If the MTU is bigger than standard + * ethernet MTU size, long frame support is activated. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int NewMtu) +{ +DEV_NET *pNet; +DEV_NET *pOtherNet; +SK_AC *pAC; +unsigned long Flags; +int i; +SK_EVPARA EvPara; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeChangeMtu starts now...\n")); + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) { + return -EINVAL; + } + + if(pAC->BoardLevel != 2) { + return -EINVAL; + } + + pNet->Mtu = NewMtu; + pOtherNet = (DEV_NET*)pAC->dev[1 - pNet->NetNr]->priv; + if ((pOtherNet->Mtu > 1500) && (NewMtu <= 1500) && (pOtherNet->Up==1)) { + return(0); + } + + EvPara.Para32[0] = pNet->NetNr; + EvPara.Para32[1] = -1; + + pAC->RxBufSize = NewMtu + 32; + dev->mtu = NewMtu; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("New MTU: %d\n", NewMtu)); + + /* prevent reconfiguration while changing the MTU */ + + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + + /* Found more than one port */ + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + /* Stop both ports */ + EvPara.Para32[0] = 0; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + EvPara.Para32[0] = 1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + } else { + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + } + + SkEventDispatcher(pAC, pAC->IoBase); + + for (i=0; iGIni.GIMacsFound; i++) { + spin_lock_irqsave( + &pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock, Flags); + netif_stop_queue(pAC->dev[i]); + + } + + /* + * adjust number of rx buffers allocated + */ + if (NewMtu > 1500) { + /* use less rx buffers */ + for (i=0; iGIni.GIMacsFound; i++) { + /* Found more than one port */ + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + pAC->RxPort[i].RxFillLimit = + pAC->RxDescrPerRing - 100; + } else { + if (i == pAC->ActivePort) + pAC->RxPort[i].RxFillLimit = + pAC->RxDescrPerRing - 100; + else + pAC->RxPort[i].RxFillLimit = + pAC->RxDescrPerRing - 10; + } + } + } + else { + /* use normal amount of rx buffers */ + for (i=0; iGIni.GIMacsFound; i++) { + /* Found more than one port */ + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + pAC->RxPort[i].RxFillLimit = 1; + } else { + if (i == pAC->ActivePort) + pAC->RxPort[i].RxFillLimit = 1; + else + pAC->RxPort[i].RxFillLimit = + pAC->RxDescrPerRing - 100; + } + } + } + + SkGeDeInit(pAC, pAC->IoBase); + + /* + * enable/disable hardware support for long frames + */ + if (NewMtu > 1500) { +/* pAC->JumboActivated = SK_TRUE; /#* is never set back !!! */ + pAC->GIni.GIPortUsage = SK_JUMBO_LINK; + } + else { + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + pAC->GIni.GIPortUsage = SK_MUL_LINK; + } else { + pAC->GIni.GIPortUsage = SK_RED_LINK; + } + } + + SkGeInit( pAC, pAC->IoBase, 1); + SkI2cInit( pAC, pAC->IoBase, 1); + SkEventInit(pAC, pAC->IoBase, 1); + SkPnmiInit( pAC, pAC->IoBase, 1); + SkAddrInit( pAC, pAC->IoBase, 1); + SkRlmtInit( pAC, pAC->IoBase, 1); + SkTimerInit(pAC, pAC->IoBase, 1); + + /* + * tschilling: + * Speed and others are set back to default in level 1 init! + */ + GetConfiguration(pAC); + + SkGeInit( pAC, pAC->IoBase, 2); + SkI2cInit( pAC, pAC->IoBase, 2); + SkEventInit(pAC, pAC->IoBase, 2); + SkPnmiInit( pAC, pAC->IoBase, 2); + SkAddrInit( pAC, pAC->IoBase, 2); + SkRlmtInit( pAC, pAC->IoBase, 2); + SkTimerInit(pAC, pAC->IoBase, 2); + + /* + * clear and reinit the rx rings here + */ + for (i=0; iGIni.GIMacsFound; i++) { + ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE); + ClearRxRing(pAC, &pAC->RxPort[i]); + FillRxRing(pAC, &pAC->RxPort[i]); + + /* Enable transmit descriptor polling. */ + SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE); + FillRxRing(pAC, &pAC->RxPort[i]); + }; + + SkGeYellowLED(pAC, pAC->IoBase, 1); + +#ifdef USE_INT_MOD + { + unsigned long ModBase; + ModBase = 53125000 / INTS_PER_SEC; + SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); + SK_OUT32(pAC->IoBase, B2_IRQM_MSK, IRQ_MOD_MASK); + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START); + } +#endif + + netif_start_queue(pAC->dev[pNet->PortNr]); + for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) { + spin_unlock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock); + } + + /* enable Interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK); + + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + + /* Found more than one port */ + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + /* Start both ports */ + EvPara.Para32[0] = pAC->RlmtNets; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, + EvPara); + + + EvPara.Para32[1] = -1; + EvPara.Para32[0] = pNet->PortNr; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); + + if (pOtherNet->Up) { + EvPara.Para32[0] = pOtherNet->PortNr; + SkEventQueue(pAC, SKGE_RLMT, + SK_RLMT_START, EvPara); + } + } else { + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); + } + + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + return 0; +} /* SkGeChangeMtu */ + + +/***************************************************************************** + * + * SkGeStats - return ethernet device statistics + * + * Description: + * This function return statistic data about the ethernet device + * to the operating system. + * + * Returns: + * pointer to the statistic structure. + */ +static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev) +{ +DEV_NET *pNet = (DEV_NET*) dev->priv; +SK_AC *pAC = pNet->pAC; +SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */ +SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */ +SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */ +unsigned int Size; /* size of pnmi struct */ +unsigned long Flags; /* for spin lock */ + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeStats starts now...\n")); + pPnmiStruct = &pAC->PnmiStruct; + memset(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA)); + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + Size = SK_PNMI_STRUCT_SIZE; + SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + pPnmiStat = &pPnmiStruct->Stat[0]; + pPnmiConf = &pPnmiStruct->Conf[0]; + + pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF; + pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF; + pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts; + pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts; + + if (pNet->Mtu <= 1500) { + pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF; + } else { + pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts - + pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF); + } + + + if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && pAC->HWRevision < 12) + pAC->stats.rx_errors = pAC->stats.rx_errors - pPnmiStat->StatRxShortsCts; + + pAC->stats.tx_errors = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF; + pAC->stats.rx_dropped = (SK_U32) pPnmiStruct->RxNoBufCts & 0xFFFFFFFF; + pAC->stats.tx_dropped = (SK_U32) pPnmiStruct->TxNoBufCts & 0xFFFFFFFF; + pAC->stats.multicast = (SK_U32) pPnmiStat->StatRxMulticastOkCts & 0xFFFFFFFF; + pAC->stats.collisions = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF; + + /* detailed rx_errors: */ + pAC->stats.rx_length_errors = (SK_U32) pPnmiStat->StatRxRuntCts & 0xFFFFFFFF; + pAC->stats.rx_over_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF; + pAC->stats.rx_crc_errors = (SK_U32) pPnmiStat->StatRxFcsCts & 0xFFFFFFFF; + pAC->stats.rx_frame_errors = (SK_U32) pPnmiStat->StatRxFramingCts & 0xFFFFFFFF; + pAC->stats.rx_fifo_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF; + pAC->stats.rx_missed_errors = (SK_U32) pPnmiStat->StatRxMissedCts & 0xFFFFFFFF; + + /* detailed tx_errors */ + pAC->stats.tx_aborted_errors = (SK_U32) 0; + pAC->stats.tx_carrier_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF; + pAC->stats.tx_fifo_errors = (SK_U32) pPnmiStat->StatTxFifoUnderrunCts & 0xFFFFFFFF; + pAC->stats.tx_heartbeat_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF; + pAC->stats.tx_window_errors = (SK_U32) 0; + + return(&pAC->stats); +} /* SkGeStats */ + + +/***************************************************************************** + * + * SkGeIoctl - IO-control function + * + * Description: + * This function is called if an ioctl is issued on the device. + * There are three subfunction for reading, writing and test-writing + * the private MIB data structure (usefull for SysKonnect-internal tools). + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd) +{ +DEV_NET *pNet; +SK_AC *pAC; + +SK_GE_IOCTL Ioctl; +unsigned int Err = 0; +int Size; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeIoctl starts now...\n")); + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) { + return -EFAULT; + } + + switch(cmd) { + case SK_IOCTL_SETMIB: + case SK_IOCTL_PRESETMIB: + if (!capable(CAP_NET_ADMIN)) return -EPERM; + case SK_IOCTL_GETMIB: + if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData, + Ioctl.LenPnmiStruct)? + Ioctl.Len : sizeof(pAC->PnmiStruct))) { + return -EFAULT; + } + Size = SkGeIocMib(pNet, Ioctl.Len, cmd); + if(copy_to_user(Ioctl.pData, &pAC->PnmiStruct, + Ioctl.Lenifr_data, &Ioctl, sizeof(SK_GE_IOCTL))) { + return -EFAULT; + } + break; + default: + Err = -EOPNOTSUPP; + } + return(Err); +} /* SkGeIoctl */ + + +/***************************************************************************** + * + * SkGeIocMib - handle a GetMib, SetMib- or PresetMib-ioctl message + * + * Description: + * This function reads/writes the MIB data using PNMI (Private Network + * Management Interface). + * The destination for the data must be provided with the + * ioctl call and is given to the driver in the form of + * a user space address. + * Copying from the user-provided data area into kernel messages + * and back is done by copy_from_user and copy_to_user calls in + * SkGeIoctl. + * + * Returns: + * returned size from PNMI call + */ +static int SkGeIocMib( +DEV_NET *pNet, /* pointer to the adapter context */ +unsigned int Size, /* length of ioctl data */ +int mode) /* flag for set/preset */ +{ +unsigned long Flags; /* for spin lock */ +SK_AC *pAC; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeIocMib starts now...\n")); + pAC = pNet->pAC; + /* access MIB */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + switch(mode) { + case SK_IOCTL_GETMIB: + SkPnmiGetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size, + pNet->NetNr); + break; + case SK_IOCTL_PRESETMIB: + SkPnmiPreSetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size, + pNet->NetNr); + break; + case SK_IOCTL_SETMIB: + SkPnmiSetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size, + pNet->NetNr); + break; + default: + break; + } + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("MIB data access succeeded\n")); + return (Size); +} /* SkGeIocMib */ +#endif + + +/***************************************************************************** + * + * GetConfiguration - read configuration information + * + * Description: + * This function reads per-adapter configuration information from + * the options provided on the command line. + * + * Returns: + * none + */ +static void GetConfiguration( +SK_AC *pAC) /* pointer to the adapter context structure */ +{ +SK_I32 Port; /* preferred port */ +int LinkSpeed; /* Link speed */ +int AutoNeg; /* auto negotiation off (0) or on (1) */ +int DuplexCap; /* duplex capabilities (0=both, 1=full, 2=half */ +int MSMode; /* master / slave mode selection */ +SK_BOOL AutoSet; +SK_BOOL DupSet; +/* + * The two parameters AutoNeg. and DuplexCap. map to one configuration + * parameter. The mapping is described by this table: + * DuplexCap -> | both | full | half | + * AutoNeg | | | | + * ----------------------------------------------------------------- + * Off | illegal | Full | Half | + * ----------------------------------------------------------------- + * On | AutoBoth | AutoFull | AutoHalf | + * ----------------------------------------------------------------- + * Sense | AutoSense | AutoSense | AutoSense | + */ +int Capabilities[3][3] = + { { -1, SK_LMODE_FULL, SK_LMODE_HALF}, + {SK_LMODE_AUTOBOTH, SK_LMODE_AUTOFULL, SK_LMODE_AUTOHALF}, + {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} }; +#define DC_BOTH 0 +#define DC_FULL 1 +#define DC_HALF 2 +#define AN_OFF 0 +#define AN_ON 1 +#define AN_SENS 2 + + /* settings for port A */ + /* settings link speed */ + LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ + if (Speed_A != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(Speed_A[pAC->Index],"")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } + else if (strcmp(Speed_A[pAC->Index],"Auto")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } + else if (strcmp(Speed_A[pAC->Index],"10")==0) { + LinkSpeed = SK_LSPEED_10MBPS; + } + else if (strcmp(Speed_A[pAC->Index],"100")==0) { + LinkSpeed = SK_LSPEED_100MBPS; + } + else if (strcmp(Speed_A[pAC->Index],"1000")==0) { + LinkSpeed = SK_LSPEED_1000MBPS; + } + else printk("%s: Illegal value for Speed_A\n", + pAC->dev[0]->name); + } + + /* Check speed parameter */ + /* Only copper type adapter and GE V2 cards */ + if (((pAC->GIni.GIChipId != CHIP_ID_YUKON) || + (pAC->GIni.GICopperType != SK_TRUE)) && + ((LinkSpeed != SK_LSPEED_AUTO) && + (LinkSpeed != SK_LSPEED_1000MBPS))) { + printk("%s: Illegal value for Speed_A. " + "Not a copper card or GE V2 card\n Using " + "speed 1000\n", pAC->dev[0]->name); + LinkSpeed = SK_LSPEED_1000MBPS; + } + pAC->GIni.GP[0].PLinkSpeed = LinkSpeed; + + /* Autonegotiation */ + AutoNeg = AN_ON; /* tschilling: Default: Autonegotiation on! */ + AutoSet = SK_FALSE; + if (AutoNeg_A != NULL && pAC->IndexIndex] != NULL) { + AutoSet = SK_TRUE; + if (strcmp(AutoNeg_A[pAC->Index],"")==0) { + AutoSet = SK_FALSE; + } + else if (strcmp(AutoNeg_A[pAC->Index],"On")==0) { + AutoNeg = AN_ON; + } + else if (strcmp(AutoNeg_A[pAC->Index],"Off")==0) { + AutoNeg = AN_OFF; + } + else if (strcmp(AutoNeg_A[pAC->Index],"Sense")==0) { + AutoNeg = AN_SENS; + } + else printk("%s: Illegal value for AutoNeg_A\n", + pAC->dev[0]->name); + } + + DuplexCap = DC_BOTH; + DupSet = SK_FALSE; + if (DupCap_A != NULL && pAC->IndexIndex] != NULL) { + DupSet = SK_TRUE; + if (strcmp(DupCap_A[pAC->Index],"")==0) { + DupSet = SK_FALSE; + } + else if (strcmp(DupCap_A[pAC->Index],"Both")==0) { + DuplexCap = DC_BOTH; + } + else if (strcmp(DupCap_A[pAC->Index],"Full")==0) { + DuplexCap = DC_FULL; + } + else if (strcmp(DupCap_A[pAC->Index],"Half")==0) { + DuplexCap = DC_HALF; + } + else printk("%s: Illegal value for DupCap_A\n", + pAC->dev[0]->name); + } + + /* check for illegal combinations */ + if (AutoSet && AutoNeg==AN_SENS && DupSet) { + printk("%s, Port A: DuplexCapabilities" + " ignored using Sense mode\n", pAC->dev[0]->name); + } + if (AutoSet && AutoNeg==AN_OFF && DupSet && DuplexCap==DC_BOTH){ + printk("%s, Port A: Illegal combination" + " of values AutoNeg. and DuplexCap.\n Using " + "Full Duplex\n", pAC->dev[0]->name); + + DuplexCap = DC_FULL; + } + if (AutoSet && AutoNeg==AN_OFF && !DupSet) { + DuplexCap = DC_FULL; + } + + if (!AutoSet && DupSet) { + printk("%s, Port A: Duplex setting not" + " possible in\n default AutoNegotiation mode" + " (Sense).\n Using AutoNegotiation On\n", + pAC->dev[0]->name); + AutoNeg = AN_ON; + } + + /* set the desired mode */ + pAC->GIni.GP[0].PLinkModeConf = + Capabilities[AutoNeg][DuplexCap]; + + pAC->GIni.GP[0].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + if (FlowCtrl_A != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(FlowCtrl_A[pAC->Index],"") == 0) { + } + else if (strcmp(FlowCtrl_A[pAC->Index],"SymOrRem") == 0) { + pAC->GIni.GP[0].PFlowCtrlMode = + SK_FLOW_MODE_SYM_OR_REM; + } + else if (strcmp(FlowCtrl_A[pAC->Index],"Sym")==0) { + pAC->GIni.GP[0].PFlowCtrlMode = + SK_FLOW_MODE_SYMMETRIC; + } + else if (strcmp(FlowCtrl_A[pAC->Index],"LocSend")==0) { + pAC->GIni.GP[0].PFlowCtrlMode = + SK_FLOW_MODE_LOC_SEND; + } + else if (strcmp(FlowCtrl_A[pAC->Index],"None")==0) { + pAC->GIni.GP[0].PFlowCtrlMode = + SK_FLOW_MODE_NONE; + } + else printk("Illegal value for FlowCtrl_A\n"); + } + if (AutoNeg==AN_OFF && pAC->GIni.GP[0].PFlowCtrlMode!= + SK_FLOW_MODE_NONE) { + printk("%s, Port A: FlowControl" + " impossible without AutoNegotiation," + " disabled\n", pAC->dev[0]->name); + pAC->GIni.GP[0].PFlowCtrlMode = SK_FLOW_MODE_NONE; + } + + MSMode = SK_MS_MODE_AUTO; /* default: do auto select */ + if (Role_A != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(Role_A[pAC->Index],"")==0) { + } + else if (strcmp(Role_A[pAC->Index],"Auto")==0) { + MSMode = SK_MS_MODE_AUTO; + } + else if (strcmp(Role_A[pAC->Index],"Master")==0) { + MSMode = SK_MS_MODE_MASTER; + } + else if (strcmp(Role_A[pAC->Index],"Slave")==0) { + MSMode = SK_MS_MODE_SLAVE; + } + else printk("%s: Illegal value for Role_A\n", + pAC->dev[0]->name); + } + pAC->GIni.GP[0].PMSMode = MSMode; + + + /* settings for port B */ + /* settings link speed */ + LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ + if (Speed_B != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(Speed_B[pAC->Index],"")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } + else if (strcmp(Speed_B[pAC->Index],"Auto")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } + else if (strcmp(Speed_B[pAC->Index],"10")==0) { + LinkSpeed = SK_LSPEED_10MBPS; + } + else if (strcmp(Speed_B[pAC->Index],"100")==0) { + LinkSpeed = SK_LSPEED_100MBPS; + } + else if (strcmp(Speed_B[pAC->Index],"1000")==0) { + LinkSpeed = SK_LSPEED_1000MBPS; + } + else printk("%s: Illegal value for Speed_B\n", + pAC->dev[1]->name); + } + + /* Check speed parameter */ + /* Only copper type adapter and GE V2 cards */ + if (((pAC->GIni.GIChipId != CHIP_ID_YUKON) || + (pAC->GIni.GICopperType != SK_TRUE)) && + ((LinkSpeed != SK_LSPEED_AUTO) && + (LinkSpeed != SK_LSPEED_1000MBPS))) { + printk("%s: Illegal value for Speed_B. " + "Not a copper card or GE V2 card\n Using " + "speed 1000\n", pAC->dev[1]->name); + LinkSpeed = SK_LSPEED_1000MBPS; + } + pAC->GIni.GP[1].PLinkSpeed = LinkSpeed; + + /* Auto negotiation */ + AutoNeg = AN_SENS; /* default: do auto Sense */ + AutoSet = SK_FALSE; + if (AutoNeg_B != NULL && pAC->IndexIndex] != NULL) { + AutoSet = SK_TRUE; + if (strcmp(AutoNeg_B[pAC->Index],"")==0) { + AutoSet = SK_FALSE; + } + else if (strcmp(AutoNeg_B[pAC->Index],"On")==0) { + AutoNeg = AN_ON; + } + else if (strcmp(AutoNeg_B[pAC->Index],"Off")==0) { + AutoNeg = AN_OFF; + } + else if (strcmp(AutoNeg_B[pAC->Index],"Sense")==0) { + AutoNeg = AN_SENS; + } + else printk("Illegal value for AutoNeg_B\n"); + } + + DuplexCap = DC_BOTH; + DupSet = SK_FALSE; + if (DupCap_B != NULL && pAC->IndexIndex] != NULL) { + DupSet = SK_TRUE; + if (strcmp(DupCap_B[pAC->Index],"")==0) { + DupSet = SK_FALSE; + } + else if (strcmp(DupCap_B[pAC->Index],"Both")==0) { + DuplexCap = DC_BOTH; + } + else if (strcmp(DupCap_B[pAC->Index],"Full")==0) { + DuplexCap = DC_FULL; + } + else if (strcmp(DupCap_B[pAC->Index],"Half")==0) { + DuplexCap = DC_HALF; + } + else printk("Illegal value for DupCap_B\n"); + } + + /* check for illegal combinations */ + if (AutoSet && AutoNeg==AN_SENS && DupSet) { + printk("%s, Port B: DuplexCapabilities" + " ignored using Sense mode\n", pAC->dev[1]->name); + } + if (AutoSet && AutoNeg==AN_OFF && DupSet && DuplexCap==DC_BOTH){ + printk("%s, Port B: Illegal combination" + " of values AutoNeg. and DuplexCap.\n Using " + "Full Duplex\n", pAC->dev[1]->name); + + DuplexCap = DC_FULL; + } + if (AutoSet && AutoNeg==AN_OFF && !DupSet) { + DuplexCap = DC_FULL; + } + + if (!AutoSet && DupSet) { + printk("%s, Port B: Duplex setting not" + " possible in\n default AutoNegotiation mode" + " (Sense).\n Using AutoNegotiation On\n", + pAC->dev[1]->name); + AutoNeg = AN_ON; + } + + /* set the desired mode */ + pAC->GIni.GP[1].PLinkModeConf = + Capabilities[AutoNeg][DuplexCap]; + + pAC->GIni.GP[1].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + if (FlowCtrl_B != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(FlowCtrl_B[pAC->Index],"") == 0) { + } + else if (strcmp(FlowCtrl_B[pAC->Index],"SymOrRem") == 0) { + pAC->GIni.GP[1].PFlowCtrlMode = + SK_FLOW_MODE_SYM_OR_REM; + } + else if (strcmp(FlowCtrl_B[pAC->Index],"Sym")==0) { + pAC->GIni.GP[1].PFlowCtrlMode = + SK_FLOW_MODE_SYMMETRIC; + } + else if (strcmp(FlowCtrl_B[pAC->Index],"LocSend")==0) { + pAC->GIni.GP[1].PFlowCtrlMode = + SK_FLOW_MODE_LOC_SEND; + } + else if (strcmp(FlowCtrl_B[pAC->Index],"None")==0) { + pAC->GIni.GP[1].PFlowCtrlMode = + SK_FLOW_MODE_NONE; + } + else printk("Illegal value for FlowCtrl_B\n"); + } + if (AutoNeg==AN_OFF && pAC->GIni.GP[1].PFlowCtrlMode!= + SK_FLOW_MODE_NONE) { + printk("%s, Port B: FlowControl" + " impossible without AutoNegotiation," + " disabled\n", pAC->dev[1]->name); + pAC->GIni.GP[1].PFlowCtrlMode = SK_FLOW_MODE_NONE; + } + + MSMode = SK_MS_MODE_AUTO; /* default: do auto select */ + if (Role_B != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(Role_B[pAC->Index],"")==0) { + } + else if (strcmp(Role_B[pAC->Index],"Auto")==0) { + MSMode = SK_MS_MODE_AUTO; + } + else if (strcmp(Role_B[pAC->Index],"Master")==0) { + MSMode = SK_MS_MODE_MASTER; + } + else if (strcmp(Role_B[pAC->Index],"Slave")==0) { + MSMode = SK_MS_MODE_SLAVE; + } + else printk("%s: Illegal value for Role_B\n", + pAC->dev[1]->name); + } + pAC->GIni.GP[1].PMSMode = MSMode; + + + /* settings for both ports */ + pAC->ActivePort = 0; + if (PrefPort != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(PrefPort[pAC->Index],"") == 0) { /* Auto */ + pAC->ActivePort = 0; + pAC->Rlmt.Net[0].Preference = -1; /* auto */ + pAC->Rlmt.Net[0].PrefPort = 0; + } + else if (strcmp(PrefPort[pAC->Index],"A") == 0) { + /* + * do not set ActivePort here, thus a port + * switch is issued after net up. + */ + Port = 0; + pAC->Rlmt.Net[0].Preference = Port; + pAC->Rlmt.Net[0].PrefPort = Port; + } + else if (strcmp(PrefPort[pAC->Index],"B") == 0) { + /* + * do not set ActivePort here, thus a port + * switch is issued after net up. + */ + Port = 1; + pAC->Rlmt.Net[0].Preference = Port; + pAC->Rlmt.Net[0].PrefPort = Port; + } + else printk("%s: Illegal value for PrefPort\n", + pAC->dev[0]->name); + } + + pAC->RlmtNets = 1; + + if (RlmtMode != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(RlmtMode[pAC->Index], "") == 0) { + pAC->RlmtMode = 0; + } + else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK; + } + else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK | + SK_RLMT_CHECK_LOC_LINK; + } + else if (strcmp(RlmtMode[pAC->Index], "CheckSeg") == 0) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK | + SK_RLMT_CHECK_LOC_LINK | + SK_RLMT_CHECK_SEG; + } + else if ((strcmp(RlmtMode[pAC->Index], "DualNet") == 0) && + (pAC->GIni.GIMacsFound == 2)) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK; + pAC->RlmtNets = 2; + } + else { + printk("%s: Illegal value for" + " RlmtMode, using default\n", pAC->dev[0]->name); + pAC->RlmtMode = 0; + } + } + else { + pAC->RlmtMode = 0; + } +} /* GetConfiguration */ + + +/***************************************************************************** + * + * ProductStr - return a adapter identification string from vpd + * + * Description: + * This function reads the product name string from the vpd area + * and puts it the field pAC->DeviceString. + * + * Returns: N/A + */ +static void ProductStr( +SK_AC *pAC /* pointer to adapter context */ +) +{ +int StrLen = 80; /* length of the string, defined in SK_AC */ +char Keyword[] = VPD_NAME; /* vpd productname identifier */ +int ReturnCode; /* return code from vpd_read */ +unsigned long Flags; + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + ReturnCode = VpdRead(pAC, pAC->IoBase, Keyword, pAC->DeviceStr, + &StrLen); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + if (ReturnCode != 0) { + /* there was an error reading the vpd data */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR, + ("Error reading VPD data: %d\n", ReturnCode)); + pAC->DeviceStr[0] = '\0'; + } +} /* ProductStr */ + + +/****************************************************************************/ +/* functions for common modules *********************************************/ +/****************************************************************************/ + + +/***************************************************************************** + * + * SkDrvAllocRlmtMbuf - allocate an RLMT mbuf + * + * Description: + * This routine returns an RLMT mbuf or NULL. The RLMT Mbuf structure + * is embedded into a socket buff data area. + * + * Context: + * runtime + * + * Returns: + * NULL or pointer to Mbuf. + */ +SK_MBUF *SkDrvAllocRlmtMbuf( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* the IO-context */ +unsigned BufferSize) /* size of the requested buffer */ +{ +SK_MBUF *pRlmtMbuf; /* pointer to a new rlmt-mbuf structure */ +struct sk_buff *pMsgBlock; /* pointer to a new message block */ + + pMsgBlock = alloc_skb(BufferSize + sizeof(SK_MBUF), GFP_ATOMIC); + if (pMsgBlock == NULL) { + return (NULL); + } + pRlmtMbuf = (SK_MBUF*) pMsgBlock->data; + skb_reserve(pMsgBlock, sizeof(SK_MBUF)); + pRlmtMbuf->pNext = NULL; + pRlmtMbuf->pOs = pMsgBlock; + pRlmtMbuf->pData = pMsgBlock->data; /* Data buffer. */ + pRlmtMbuf->Size = BufferSize; /* Data buffer size. */ + pRlmtMbuf->Length = 0; /* Length of packet (<= Size). */ + return (pRlmtMbuf); + +} /* SkDrvAllocRlmtMbuf */ + + +/***************************************************************************** + * + * SkDrvFreeRlmtMbuf - free an RLMT mbuf + * + * Description: + * This routine frees one or more RLMT mbuf(s). + * + * Context: + * runtime + * + * Returns: + * Nothing + */ +void SkDrvFreeRlmtMbuf( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* the IO-context */ +SK_MBUF *pMbuf) /* size of the requested buffer */ +{ +SK_MBUF *pFreeMbuf; +SK_MBUF *pNextMbuf; + + pFreeMbuf = pMbuf; + do { + pNextMbuf = pFreeMbuf->pNext; + DEV_KFREE_SKB_ANY(pFreeMbuf->pOs); + pFreeMbuf = pNextMbuf; + } while ( pFreeMbuf != NULL ); +} /* SkDrvFreeRlmtMbuf */ + + +/***************************************************************************** + * + * SkOsGetTime - provide a time value + * + * Description: + * This routine provides a time value. The unit is 1/HZ (defined by Linux). + * It is not used for absolute time, but only for time differences. + * + * + * Returns: + * Time value + */ +SK_U64 SkOsGetTime(SK_AC *pAC) +{ +#if 0 + return jiffies; +#else + return get_timer(0); +#endif +} /* SkOsGetTime */ + + +/***************************************************************************** + * + * SkPciReadCfgDWord - read a 32 bit value from pci config space + * + * Description: + * This routine reads a 32 bit value from the pci configuration + * space. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciReadCfgDWord( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U32 *pVal) /* pointer to store the read value */ +{ + pci_read_config_dword(pAC->PciDev, PciAddr, pVal); + return(0); +} /* SkPciReadCfgDWord */ + + +/***************************************************************************** + * + * SkPciReadCfgWord - read a 16 bit value from pci config space + * + * Description: + * This routine reads a 16 bit value from the pci configuration + * space. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciReadCfgWord( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U16 *pVal) /* pointer to store the read value */ +{ + pci_read_config_word(pAC->PciDev, PciAddr, pVal); + return(0); +} /* SkPciReadCfgWord */ + + +/***************************************************************************** + * + * SkPciReadCfgByte - read a 8 bit value from pci config space + * + * Description: + * This routine reads a 8 bit value from the pci configuration + * space. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciReadCfgByte( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U8 *pVal) /* pointer to store the read value */ +{ + pci_read_config_byte(pAC->PciDev, PciAddr, pVal); + return(0); +} /* SkPciReadCfgByte */ + + +/***************************************************************************** + * + * SkPciWriteCfgDWord - write a 32 bit value to pci config space + * + * Description: + * This routine writes a 32 bit value to the pci configuration + * space. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciWriteCfgDWord( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U32 Val) /* pointer to store the read value */ +{ + pci_write_config_dword(pAC->PciDev, PciAddr, Val); + return(0); +} /* SkPciWriteCfgDWord */ + + +/***************************************************************************** + * + * SkPciWriteCfgWord - write a 16 bit value to pci config space + * + * Description: + * This routine writes a 16 bit value to the pci configuration + * space. The flag PciConfigUp indicates whether the config space + * is accesible or must be set up first. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciWriteCfgWord( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U16 Val) /* pointer to store the read value */ +{ + pci_write_config_word(pAC->PciDev, PciAddr, Val); + return(0); +} /* SkPciWriteCfgWord */ + + +/***************************************************************************** + * + * SkPciWriteCfgWord - write a 8 bit value to pci config space + * + * Description: + * This routine writes a 8 bit value to the pci configuration + * space. The flag PciConfigUp indicates whether the config space + * is accesible or must be set up first. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciWriteCfgByte( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U8 Val) /* pointer to store the read value */ +{ + pci_write_config_byte(pAC->PciDev, PciAddr, Val); + return(0); +} /* SkPciWriteCfgByte */ + + +/***************************************************************************** + * + * SkDrvEvent - handle driver events + * + * Description: + * This function handles events from all modules directed to the driver + * + * Context: + * Is called under protection of slow path lock. + * + * Returns: + * 0 if everything ok + * < 0 on error + * + */ +int SkDrvEvent( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* io-context */ +SK_U32 Event, /* event-id */ +SK_EVPARA Param) /* event-parameter */ +{ +SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */ +struct sk_buff *pMsg; /* pointer to a message block */ +int FromPort; /* the port from which we switch away */ +int ToPort; /* the port we switch to */ +SK_EVPARA NewPara; /* parameter for further events */ +#if 0 +int Stat; +#endif +unsigned long Flags; +SK_BOOL DualNet; + + switch (Event) { + case SK_DRV_ADAP_FAIL: + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("ADAPTER FAIL EVENT\n")); + printk("%s: Adapter failed.\n", pAC->dev[0]->name); + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + /* cgoos */ + break; + case SK_DRV_PORT_FAIL: + FromPort = Param.Para32[0]; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("PORT FAIL EVENT, Port: %d\n", FromPort)); + if (FromPort == 0) { + printk("%s: Port A failed.\n", pAC->dev[0]->name); + } else { + printk("%s: Port B failed.\n", pAC->dev[1]->name); + } + /* cgoos */ + break; + case SK_DRV_PORT_RESET: /* SK_U32 PortIdx */ + /* action list 4 */ + FromPort = Param.Para32[0]; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("PORT RESET EVENT, Port: %d ", FromPort)); + NewPara.Para64 = FromPort; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara); + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); +#if 0 + pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING; +#endif + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + + /* clear rx ring from received frames */ + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); + + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + + /* tschilling: Handling of return value inserted. */ + if (SkGeInitPort(pAC, IoC, FromPort)) { + if (FromPort == 0) { + printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name); + } else { + printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name); + } + } + SkAddrMcUpdate(pAC,IoC, FromPort); + PortReInitBmu(pAC, FromPort); + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); + ClearAndStartRx(pAC, FromPort); + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + break; + case SK_DRV_NET_UP: /* SK_U32 PortIdx */ + /* action list 5 */ + FromPort = Param.Para32[0]; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("NET UP EVENT, Port: %d ", Param.Para32[0])); +#ifdef SK98_INFO + printk("%s: network connection up using" + " port %c\n", pAC->dev[Param.Para32[0]]->name, 'A'+Param.Para32[0]); + + /* tschilling: Values changed according to LinkSpeedUsed. */ + Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed; + if (Stat == SK_LSPEED_STAT_10MBPS) { + printk(" speed: 10\n"); + } else if (Stat == SK_LSPEED_STAT_100MBPS) { + printk(" speed: 100\n"); + } else if (Stat == SK_LSPEED_STAT_1000MBPS) { + printk(" speed: 1000\n"); + } else { + printk(" speed: unknown\n"); + } + + Stat = pAC->GIni.GP[FromPort].PLinkModeStatus; + if (Stat == SK_LMODE_STAT_AUTOHALF || + Stat == SK_LMODE_STAT_AUTOFULL) { + printk(" autonegotiation: yes\n"); + } + else { + printk(" autonegotiation: no\n"); + } + if (Stat == SK_LMODE_STAT_AUTOHALF || + Stat == SK_LMODE_STAT_HALF) { + printk(" duplex mode: half\n"); + } + else { + printk(" duplex mode: full\n"); + } + Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus; + if (Stat == SK_FLOW_STAT_REM_SEND ) { + printk(" flowctrl: remote send\n"); + } + else if (Stat == SK_FLOW_STAT_LOC_SEND ){ + printk(" flowctrl: local send\n"); + } + else if (Stat == SK_FLOW_STAT_SYMMETRIC ){ + printk(" flowctrl: symmetric\n"); + } + else { + printk(" flowctrl: none\n"); + } + + /* tschilling: Check against CopperType now. */ + if ((pAC->GIni.GICopperType == SK_TRUE) && + (pAC->GIni.GP[FromPort].PLinkSpeedUsed == + SK_LSPEED_STAT_1000MBPS)) { + Stat = pAC->GIni.GP[FromPort].PMSStatus; + if (Stat == SK_MS_STAT_MASTER ) { + printk(" role: master\n"); + } + else if (Stat == SK_MS_STAT_SLAVE ) { + printk(" role: slave\n"); + } + else { + printk(" role: ???\n"); + } + } + +#ifdef SK_ZEROCOPY + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) + printk(" scatter-gather: enabled\n"); + else + printk(" scatter-gather: disabled\n"); + +#else + printk(" scatter-gather: disabled\n"); +#endif +#endif /* SK98_INFO */ + + if ((Param.Para32[0] != pAC->ActivePort) && + (pAC->RlmtNets == 1)) { + NewPara.Para32[0] = pAC->ActivePort; + NewPara.Para32[1] = Param.Para32[0]; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN, + NewPara); + } + + /* Inform the world that link protocol is up. */ +#if 0 + pAC->dev[Param.Para32[0]]->flags |= IFF_RUNNING; +#endif + + break; + case SK_DRV_NET_DOWN: /* SK_U32 Reason */ + /* action list 7 */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("NET DOWN EVENT ")); +#ifdef SK98_INFO + printk("%s: network connection down\n", pAC->dev[Param.Para32[1]]->name); +#endif +#if 0 + pAC->dev[Param.Para32[1]]->flags &= ~IFF_RUNNING; +#endif + break; + case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("PORT SWITCH HARD ")); + case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ + /* action list 6 */ + printk("%s: switching to port %c\n", pAC->dev[0]->name, + 'A'+Param.Para32[1]); + case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ + FromPort = Param.Para32[0]; + ToPort = Param.Para32[1]; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("PORT SWITCH EVENT, From: %d To: %d (Pref %d) ", + FromPort, ToPort, pAC->Rlmt.Net[0].PrefPort)); + NewPara.Para64 = FromPort; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara); + NewPara.Para64 = ToPort; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara); + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + spin_lock_irqsave( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST); + SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST); + spin_unlock_irqrestore( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */ + ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */ + + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]); + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + spin_lock_irqsave( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + pAC->ActivePort = ToPort; +#if 0 + SetQueueSizes(pAC); +#else + /* tschilling: New common function with minimum size check. */ + DualNet = SK_FALSE; + if (pAC->RlmtNets == 2) { + DualNet = SK_TRUE; + } + + if (SkGeInitAssignRamToQueues( + pAC, + pAC->ActivePort, + DualNet)) { + spin_unlock_irqrestore( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + printk("SkGeInitAssignRamToQueues failed.\n"); + break; + } +#endif + /* tschilling: Handling of return values inserted. */ + if (SkGeInitPort(pAC, IoC, FromPort) || + SkGeInitPort(pAC, IoC, ToPort)) { + printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name); + } + if (Event == SK_DRV_SWITCH_SOFT) { + SkMacRxTxEnable(pAC, IoC, FromPort); + } + SkMacRxTxEnable(pAC, IoC, ToPort); + SkAddrSwap(pAC, IoC, FromPort, ToPort); + SkAddrMcUpdate(pAC, IoC, FromPort); + SkAddrMcUpdate(pAC, IoC, ToPort); + PortReInitBmu(pAC, FromPort); + PortReInitBmu(pAC, ToPort); + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); + SkGePollTxD(pAC, IoC, ToPort, SK_TRUE); + ClearAndStartRx(pAC, FromPort); + ClearAndStartRx(pAC, ToPort); + spin_unlock_irqrestore( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + break; + case SK_DRV_RLMT_SEND: /* SK_MBUF *pMb */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("RLS ")); + pRlmtMbuf = (SK_MBUF*) Param.pParaPtr; + pMsg = (struct sk_buff*) pRlmtMbuf->pOs; + skb_put(pMsg, pRlmtMbuf->Length); + if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW], + pMsg) < 0) + + DEV_KFREE_SKB_ANY(pMsg); + break; + default: + break; + } + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("END EVENT ")); + + return (0); +} /* SkDrvEvent */ + + +/***************************************************************************** + * + * SkErrorLog - log errors + * + * Description: + * This function logs errors to the system buffer and to the console + * + * Returns: + * 0 if everything ok + * < 0 on error + * + */ +void SkErrorLog( +SK_AC *pAC, +int ErrClass, +int ErrNum, +char *pErrorMsg) +{ +char ClassStr[80]; + + switch (ErrClass) { + case SK_ERRCL_OTHER: + strcpy(ClassStr, "Other error"); + break; + case SK_ERRCL_CONFIG: + strcpy(ClassStr, "Configuration error"); + break; + case SK_ERRCL_INIT: + strcpy(ClassStr, "Initialization error"); + break; + case SK_ERRCL_NORES: + strcpy(ClassStr, "Out of resources error"); + break; + case SK_ERRCL_SW: + strcpy(ClassStr, "internal Software error"); + break; + case SK_ERRCL_HW: + strcpy(ClassStr, "Hardware failure"); + break; + case SK_ERRCL_COMM: + strcpy(ClassStr, "Communication error"); + break; + } + printk(KERN_INFO "%s: -- ERROR --\n Class: %s\n" + " Nr: 0x%x\n Msg: %s\n", pAC->dev[0]->name, + ClassStr, ErrNum, pErrorMsg); + +} /* SkErrorLog */ + +#ifdef DEBUG +/****************************************************************************/ +/* "debug only" section *****************************************************/ +/****************************************************************************/ + + +/***************************************************************************** + * + * DumpMsg - print a frame + * + * Description: + * This function prints frames to the system logfile/to the console. + * + * Returns: N/A + * + */ +static void DumpMsg(struct sk_buff *skb, char *str) +{ + int msglen; + + if (skb == NULL) { + printk("DumpMsg(): NULL-Message\n"); + return; + } + + if (skb->data == NULL) { + printk("DumpMsg(): Message empty\n"); + return; + } + + msglen = skb->len; + if (msglen > 64) + msglen = 64; + + printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len); + + DumpData((char *)skb->data, msglen); + + printk("------- End of message ---------\n"); +} /* DumpMsg */ + + +/***************************************************************************** + * + * DumpData - print a data area + * + * Description: + * This function prints a area of data to the system logfile/to the + * console. + * + * Returns: N/A + * + */ +static void DumpData(char *p, int size) +{ +register int i; +int haddr, addr; +char hex_buffer[180]; +char asc_buffer[180]; +char HEXCHAR[] = "0123456789ABCDEF"; + + addr = 0; + haddr = 0; + hex_buffer[0] = 0; + asc_buffer[0] = 0; + for (i=0; i < size; ) { + if (*p >= '0' && *p <='z') + asc_buffer[addr] = *p; + else + asc_buffer[addr] = '.'; + addr++; + asc_buffer[addr] = 0; + hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4]; + haddr++; + hex_buffer[haddr] = HEXCHAR[*p & 0x0f]; + haddr++; + hex_buffer[haddr] = ' '; + haddr++; + hex_buffer[haddr] = 0; + p++; + i++; + if (i%16 == 0) { + printk("%s %s\n", hex_buffer, asc_buffer); + addr = 0; + haddr = 0; + } + } +} /* DumpData */ + + +/***************************************************************************** + * + * DumpLong - print a data area as long values + * + * Description: + * This function prints a area of data to the system logfile/to the + * console. + * + * Returns: N/A + * + */ +static void DumpLong(char *pc, int size) +{ +register int i; +int haddr, addr; +char hex_buffer[180]; +char asc_buffer[180]; +char HEXCHAR[] = "0123456789ABCDEF"; +long *p; +int l; + + addr = 0; + haddr = 0; + hex_buffer[0] = 0; + asc_buffer[0] = 0; + p = (long*) pc; + for (i=0; i < size; ) { + l = (long) *p; + hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 24) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 20) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 16) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 12) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 8) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 4) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[l & 0x0f]; + haddr++; + hex_buffer[haddr] = ' '; + haddr++; + hex_buffer[haddr] = 0; + p++; + i++; + if (i%8 == 0) { + printk("%4x %s\n", (i-8)*4, hex_buffer); + haddr = 0; + } + } + printk("------------------------\n"); +} /* DumpLong */ + +#endif + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skgehwt.c b/drivers/sk98lin/skgehwt.c new file mode 100644 index 0000000..f8681a8 --- /dev/null +++ b/drivers/sk98lin/skgehwt.c @@ -0,0 +1,220 @@ +/****************************************************************************** + * + * Name: skgehwt.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.13 $ + * Date: $Date: 1999/11/22 13:31:12 $ + * Purpose: Hardware Timer. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgehwt.c,v $ + * Revision 1.13 1999/11/22 13:31:12 cgoos + * Changed license header to GPL. + * + * Revision 1.12 1998/10/15 15:11:34 gklug + * fix: ID_sccs to SysKonnectFileId + * + * Revision 1.11 1998/10/08 15:27:51 gklug + * chg: correction factor is host clock dependent + * + * Revision 1.10 1998/09/15 14:18:31 cgoos + * Changed more BOOLEANs to SK_xxx + * + * Revision 1.9 1998/09/15 14:16:06 cgoos + * Changed line 107: FALSE to SK_FALSE + * + * Revision 1.8 1998/08/24 13:04:44 gklug + * fix: typo + * + * Revision 1.7 1998/08/19 09:50:49 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.6 1998/08/17 09:59:02 gklug + * fix: typos + * + * Revision 1.5 1998/08/14 07:09:10 gklug + * fix: chg pAc -> pAC + * + * Revision 1.4 1998/08/10 14:14:52 gklug + * rmv: unneccessary SK_ADDR macro + * + * Revision 1.3 1998/08/07 12:53:44 gklug + * fix: first compiled version + * + * Revision 1.2 1998/08/07 09:19:29 gklug + * adapt functions to the C coding conventions + * rmv unneccessary functions. + * + * Revision 1.1 1998/08/05 11:28:36 gklug + * first version: adapted from SMT/FDDI + * + * + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + Event queue and dispatcher +*/ +static const char SysKonnectFileId[] = + "$Header: /usr56/projects/ge/schedule/skgehwt.c,v 1.13 1999/11/22 13:31:12 cgoos Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef __C2MAN__ +/* + Hardware Timer function queue management. + + General Description: + + */ +intro() +{} +#endif + +/* + * Prototypes of local functions. + */ +#define SK_HWT_MAX (65000) + +/* correction factor */ +#define SK_HWT_FAC (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100) + +/* + * Initialize hardware timer. + * + * Must be called during init level 1. + */ +void SkHwtInit( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + pAC->Hwt.TStart = 0 ; + pAC->Hwt.TStop = 0 ; + pAC->Hwt.TActive = SK_FALSE ; + + SkHwtStop(pAC,Ioc) ; +} + +/* + * + * Start hardware timer (clock ticks are 16us). + * + */ +void SkHwtStart( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +SK_U32 Time) /* Time in units of 16us to load the timer with. */ +{ + SK_U32 Cnt ; + + if (Time > SK_HWT_MAX) + Time = SK_HWT_MAX ; + + pAC->Hwt.TStart = Time ; + pAC->Hwt.TStop = 0L ; + + Cnt = Time ; + + /* + * if time < 16 us + * time = 16 us + */ + if (!Cnt) { + Cnt++ ; + } + + SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC) ; + SK_OUT16(Ioc, B2_TI_CRTL, TIM_START) ; /* Start timer. */ + + pAC->Hwt.TActive = SK_TRUE ; +} + +/* + * Stop hardware timer. + * and clear the timer IRQ + */ +void SkHwtStop( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + SK_OUT16(Ioc, B2_TI_CRTL, TIM_STOP) ; + SK_OUT16(Ioc, B2_TI_CRTL, TIM_CLR_IRQ) ; + + pAC->Hwt.TActive = SK_FALSE ; +} + + +/* + * Stop hardware timer and read time elapsed since last start. + * + * returns + * The elapsed time since last start in units of 16us. + * + */ +SK_U32 SkHwtRead( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + SK_U32 TRead ; + SK_U32 IStatus ; + + if (pAC->Hwt.TActive) { + SkHwtStop(pAC,Ioc) ; + + SK_IN32(Ioc, B2_TI_VAL, &TRead); + TRead /= SK_HWT_FAC; + + SK_IN32(Ioc, B0_ISRC, &IStatus); + + /* Check if timer expired (or wraparound). */ + if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) { + SkHwtStop(pAC,Ioc) ; + pAC->Hwt.TStop = pAC->Hwt.TStart ; + } else { + pAC->Hwt.TStop = pAC->Hwt.TStart - TRead ; + } + } + return (pAC->Hwt.TStop) ; +} + +/* + * interrupt source= timer + */ +void SkHwtIsr( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + SkHwtStop(pAC,Ioc); + pAC->Hwt.TStop = pAC->Hwt.TStart; + SkTimerDone(pAC,Ioc) ; +} + +#endif /* CONFIG_SK98 */ + +/* End of file */ diff --git a/drivers/sk98lin/skgeinit.c b/drivers/sk98lin/skgeinit.c new file mode 100644 index 0000000..a18dc0a --- /dev/null +++ b/drivers/sk98lin/skgeinit.c @@ -0,0 +1,2372 @@ +/****************************************************************************** + * + * Name: skgeinit.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.85 $ + * Date: $Date: 2003/02/05 15:30:33 $ + * Purpose: Contains functions to initialize the GE HW + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgeinit.c,v $ + * Revision 1.85 2003/02/05 15:30:33 rschmidt + * Corrected setting of GIHstClkFact (Host Clock Factor) and + * GIPollTimerVal (Descr. Poll Timer Init Value) for YUKON. + * Editorial changes. + * + * Revision 1.84 2003/01/28 09:57:25 rschmidt + * Added detection of YUKON-Lite Rev. A0 (stored in GIYukonLite). + * Disabled Rx GMAC FIFO Flush for YUKON-Lite Rev. A0. + * Added support for CLK_RUN (YUKON-Lite). + * Added additional check of PME from D3cold for setting GIVauxAvail. + * Editorial changes. + * + * Revision 1.83 2002/12/17 16:15:41 rschmidt + * Added default setting of PhyType (Copper) for YUKON. + * Added define around check for HW self test results. + * Editorial changes. + * + * Revision 1.82 2002/12/05 13:40:21 rschmidt + * Added setting of Rx GMAC FIFO Flush Mask register. + * Corrected PhyType with new define SK_PHY_MARV_FIBER when + * YUKON Fiber board was found. + * Editorial changes. + * + * Revision 1.81 2002/11/15 12:48:35 rschmidt + * Replaced message SKERR_HWI_E018 with SKERR_HWI_E024 for Rx queue error + * in SkGeStopPort(). + * Added init for pAC->GIni.GIGenesis with SK_FALSE in YUKON-branch. + * Editorial changes. + * + * Revision 1.80 2002/11/12 17:28:30 rschmidt + * Initialized GIPciSlot64 and GIPciClock66 in SkGeInit1(). + * Reduced PCI FIFO watermarks for 32bit/33MHz bus in SkGeInitBmu(). + * Editorial changes. + * + * Revision 1.79 2002/10/21 09:31:02 mkarl + * Changed SkGeInitAssignRamToQueues(), removed call to + * SkGeInitAssignRamToQueues in SkGeInit1 and fixed compiler warning in + * SkGeInit1. + * + * Revision 1.78 2002/10/16 15:55:07 mkarl + * Fixed a bug in SkGeInitAssignRamToQueues. + * + * Revision 1.77 2002/10/14 15:07:22 rschmidt + * Corrected timeout handling for Rx queue in SkGeStopPort() (#10748) + * Editorial changes. + * + * Revision 1.76 2002/10/11 09:24:38 mkarl + * Added check for HW self test results. + * + * Revision 1.75 2002/10/09 16:56:44 mkarl + * Now call SkGeInitAssignRamToQueues() in Init Level 1 in order to assign + * the adapter memory to the queues. This default assignment is not suitable + * for dual net mode. + * + * Revision 1.74 2002/09/12 08:45:06 rwahl + * Set defaults for PMSCap, PLinkSpeed & PLinkSpeedCap dependent on PHY. + * + * Revision 1.73 2002/08/16 15:19:45 rschmidt + * Corrected check for Tx queues in SkGeCheckQSize(). + * Added init for new entry GIGenesis and GICopperType + * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis. + * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros. + * + * Revision 1.72 2002/08/12 13:38:55 rschmidt + * Added check if VAUX is available (stored in GIVauxAvail) + * Initialized PLinkSpeedCap in Port struct with SK_LSPEED_CAP_1000MBPS + * Editorial changes. + * + * Revision 1.71 2002/08/08 16:32:58 rschmidt + * Added check for Tx queues in SkGeCheckQSize(). + * Added start of Time Stamp Timer (YUKON) in SkGeInit2(). + * Editorial changes. + * + * Revision 1.70 2002/07/23 16:04:26 rschmidt + * Added init for GIWolOffs (HW-Bug in YUKON 1st rev.) + * Minor changes + * + * Revision 1.69 2002/07/17 17:07:08 rwahl + * - SkGeInit1(): fixed PHY type debug output; corrected init of GIFunc + * table & GIMacType. + * - Editorial changes. + * + * Revision 1.68 2002/07/15 18:38:31 rwahl + * Added initialization for MAC type dependent function table. + * + * Revision 1.67 2002/07/15 15:45:39 rschmidt + * Added Tx Store & Forward for YUKON (GMAC Tx FIFO is only 1 kB) + * Replaced SK_PHY_MARV by SK_PHY_MARV_COPPER + * Editorial changes + * + * Revision 1.66 2002/06/10 09:35:08 rschmidt + * Replaced C++ comments (//) + * Editorial changes + * + * Revision 1.65 2002/06/05 08:33:37 rschmidt + * Changed GIRamSize and Reset sequence for YUKON. + * SkMacInit() replaced by SkXmInitMac() resp. SkGmInitMac() + * + * Revision 1.64 2002/04/25 13:03:20 rschmidt + * Changes for handling YUKON. + * Removed reference to xmac_ii.h (not necessary). + * Moved all defines into header file. + * Replaced all SkXm...() functions with SkMac...() to handle also + * YUKON's GMAC. + * Added handling for GMAC FIFO in SkGeInitMacFifo(), SkGeStopPort(). + * Removed 'goto'-directive from SkGeCfgSync(), SkGeCheckQSize(). + * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(), + * SkMacFlushTxFifo(). + * Optimized timeout handling in SkGeStopPort(). + * Initialized PLinkSpeed in Port struct with SK_LSPEED_AUTO. + * Release of GMAC Link Control reset in SkGeInit1(). + * Initialized GIChipId and GIChipRev in GE Init structure. + * Added GIRamSize and PhyType values for YUKON. + * Removed use of PRxCmd to setup XMAC. + * Moved setting of XM_RX_DIS_CEXT to SkXmInitMac(). + * Use of SkGeXmitLED() only for GENESIS. + * Changes for V-CPU support. + * Editorial changes. + * + * Revision 1.63 2001/04/05 11:02:09 rassmann + * Stop Port check of the STOP bit did not take 2/18 sec as wanted. + * + * Revision 1.62 2001/02/07 07:54:21 rassmann + * Corrected copyright. + * + * Revision 1.61 2001/01/31 15:31:40 gklug + * fix: problem with autosensing an SR8800 switch + * + * Revision 1.60 2000/10/18 12:22:21 cgoos + * Added workaround for half duplex hangup. + * + * Revision 1.59 2000/10/10 11:22:06 gklug + * add: in manual half duplex mode ignore carrier extension errors + * + * Revision 1.58 2000/10/02 14:10:27 rassmann + * Reading BCOM PHY after releasing reset until it returns a valid value. + * + * Revision 1.57 2000/08/03 14:55:28 rassmann + * Waiting for I2C to be ready before de-initializing adapter + * (prevents sensors from hanging up). + * + * Revision 1.56 2000/07/27 12:16:48 gklug + * fix: Stop Port check of the STOP bit does now take 2/18 sec as wanted + * + * Revision 1.55 1999/11/22 13:32:26 cgoos + * Changed license header to GPL. + * + * Revision 1.54 1999/10/26 07:32:54 malthoff + * Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics. + * + * Revision 1.53 1999/08/12 19:13:50 malthoff + * Fix for 1000BT. Do not owerwrite XM_MMU_CMD when + * disabling receiver and transmitter. Other bits + * may be lost. + * + * Revision 1.52 1999/07/01 09:29:54 gklug + * fix: DoInitRamQueue needs pAC + * + * Revision 1.51 1999/07/01 08:42:21 gklug + * chg: use Store & forward for RAM buffer when Jumbos are used + * + * Revision 1.50 1999/05/27 13:19:38 cgoos + * Added Tx PCI watermark initialization. + * Removed Tx RAM queue Store & Forward setting. + * + * Revision 1.49 1999/05/20 14:32:45 malthoff + * SkGeLinkLED() is completly removed now. + * + * Revision 1.48 1999/05/19 07:28:24 cgoos + * SkGeLinkLED no more available for drivers. + * Changes for 1000Base-T. + * + * Revision 1.47 1999/04/08 13:57:45 gklug + * add: Init of new port struct fiels PLinkResCt + * chg: StopPort Timer check + * + * Revision 1.46 1999/03/25 07:42:15 malthoff + * SkGeStopPort(): Add workaround for cache incoherency. + * Create error log entry, disable port, and + * exit loop if it does not terminate. + * Add XM_RX_LENERR_OK to the default value for the + * XMAC receive command register. + * + * Revision 1.45 1999/03/12 16:24:47 malthoff + * Remove PPollRxD and PPollTxD. + * Add check for GIPollTimerVal. + * + * Revision 1.44 1999/03/12 13:40:23 malthoff + * Fix: SkGeXmitLED(), SK_LED_TST mode does not work. + * Add: Jumbo frame support. + * Chg: Resolution of parameter IntTime in SkGeCfgSync(). + * + * Revision 1.43 1999/02/09 10:29:46 malthoff + * Bugfix: The previous modification again also for the second location. + * + * Revision 1.42 1999/02/09 09:35:16 malthoff + * Bugfix: The bits '66 MHz Capable' and 'NEWCAP are reset while + * clearing the error bits in the PCI status register. + * + * Revision 1.41 1999/01/18 13:07:02 malthoff + * Bugfix: Do not use CFG cycles after during Init- or Runtime, because + * they may not be available after Boottime. + * + * Revision 1.40 1999/01/11 12:40:49 malthoff + * Bug fix: PCI_STATUS: clearing error bits sets the UDF bit. + * + * Revision 1.39 1998/12/11 15:17:33 gklug + * chg: Init LipaAutoNeg with Unknown + * + * Revision 1.38 1998/12/10 11:02:57 malthoff + * Disable Error Log Message when calling SkGeInit(level 2) + * more than once. + * + * Revision 1.37 1998/12/07 12:18:25 gklug + * add: refinement of autosense mode: take into account the autoneg cap of LiPa + * + * Revision 1.36 1998/12/07 07:10:39 gklug + * fix: init values of LinkBroken/ Capabilities for management + * + * Revision 1.35 1998/12/02 10:56:20 gklug + * fix: do NOT init LoinkSync Counter. + * + * Revision 1.34 1998/12/01 10:53:21 gklug + * add: init of additional Counters for workaround + * + * Revision 1.33 1998/12/01 10:00:49 gklug + * add: init PIsave var in Port struct + * + * Revision 1.32 1998/11/26 14:50:40 gklug + * chg: Default is autosensing with AUTOFULL mode + * + * Revision 1.31 1998/11/25 15:36:16 gklug + * fix: do NOT stop LED Timer when port should be stopped + * + * Revision 1.30 1998/11/24 13:15:28 gklug + * add: Init PCkeckPar struct member + * + * Revision 1.29 1998/11/18 13:19:27 malthoff + * Disable packet arbiter timeouts on receive side. + * Use maximum timeout value for packet arbiter + * transmit timeouts. + * Add TestStopBit() function to handle stop RX/TX + * problem with active descriptor poll timers. + * Bug Fix: Descriptor Poll Timer not started, because + * GIPollTimerVal was initialized with 0. + * + * Revision 1.28 1998/11/13 14:24:26 malthoff + * Bug Fix: SkGeStopPort() may hang if a Packet Arbiter Timout + * is pending or occurs while waiting for TX_STOP and RX_STOP. + * The PA timeout is cleared now while waiting for TX- or RX_STOP. + * + * Revision 1.27 1998/11/02 11:04:36 malthoff + * fix the last fix + * + * Revision 1.26 1998/11/02 10:37:03 malthoff + * Fix: SkGePollTxD() enables always the synchronounous poll timer. + * + * Revision 1.25 1998/10/28 07:12:43 cgoos + * Fixed "LED_STOP" in SkGeLnkSyncCnt, "== SK_INIT_IO" in SkGeInit. + * Removed: Reset of RAM Interface in SkGeStopPort. + * + * Revision 1.24 1998/10/27 08:13:12 malthoff + * Remove temporary code. + * + * Revision 1.23 1998/10/26 07:45:03 malthoff + * Add Address Calculation Workaround: If the EPROM byte + * Id is 3, the address offset is 512 kB. + * Initialize default values for PLinkMode and PFlowCtrlMode. + * + * Revision 1.22 1998/10/22 09:46:47 gklug + * fix SysKonnectFileId typo + * + * Revision 1.21 1998/10/20 12:11:56 malthoff + * Don't dendy the Queue config if the size of the unused + * Rx qeueu is zero. + * + * Revision 1.20 1998/10/19 07:27:58 malthoff + * SkGeInitRamIface() is public to be called by diagnostics. + * + * Revision 1.19 1998/10/16 13:33:45 malthoff + * Fix: enabling descriptor polling is not allowed until + * the descriptor addresses are set. Descriptor polling + * must be handled by the driver. + * + * Revision 1.18 1998/10/16 10:58:27 malthoff + * Remove temp. code for Diag prototype. + * Remove lint warning for dummy reads. + * Call SkGeLoadLnkSyncCnt() during SkGeInitPort(). + * + * Revision 1.17 1998/10/14 09:16:06 malthoff + * Change parameter LimCount and programming of + * the limit counter in SkGeCfgSync(). + * + * Revision 1.16 1998/10/13 09:21:16 malthoff + * Don't set XM_RX_SELF_RX in RxCmd Reg, because it's + * like a Loopback Mode in half duplex. + * + * Revision 1.15 1998/10/09 06:47:40 malthoff + * SkGeInitMacArb(): set recovery counters init value + * to zero although this counters are not uesd. + * Bug fix in Rx Upper/Lower Pause Threshold calculation. + * Add XM_RX_SELF_RX to RxCmd. + * + * Revision 1.14 1998/10/06 15:15:53 malthoff + * Make sure no pending IRQ is cleared in SkGeLoadLnkSyncCnt(). + * + * Revision 1.13 1998/10/06 14:09:36 malthoff + * Add SkGeLoadLnkSyncCnt(). Modify + * the 'port stopped' condition according + * to the current problem report. + * + * Revision 1.12 1998/10/05 08:17:21 malthoff + * Add functions: SkGePollRxD(), SkGePollTxD(), + * DoCalcAddr(), SkGeCheckQSize(), + * DoInitRamQueue(), and SkGeCfgSync(). + * Add coding for SkGeInitMacArb(), SkGeInitPktArb(), + * SkGeInitMacFifo(), SkGeInitRamBufs(), + * SkGeInitRamIface(), and SkGeInitBmu(). + * + * Revision 1.11 1998/09/29 08:26:29 malthoff + * bug fix: SkGeInit0() 'i' should be increment. + * + * Revision 1.10 1998/09/28 13:19:01 malthoff + * Coding time: Save the done work. + * Modify SkGeLinkLED(), add SkGeXmitLED(), + * define SkGeCheckQSize(), SkGeInitMacArb(), + * SkGeInitPktArb(), SkGeInitMacFifo(), + * SkGeInitRamBufs(), SkGeInitRamIface(), + * and SkGeInitBmu(). Do coding for SkGeStopPort(), + * SkGeInit1(), SkGeInit2(), and SkGeInit3(). + * Do coding for SkGeDinit() and SkGeInitPort(). + * + * Revision 1.9 1998/09/16 14:29:05 malthoff + * Some minor changes. + * + * Revision 1.8 1998/09/11 05:29:14 gklug + * add: init state of a port + * + * Revision 1.7 1998/09/04 09:26:25 malthoff + * Short temporary modification. + * + * Revision 1.6 1998/09/04 08:27:59 malthoff + * Remark the do-while in StopPort() because it never ends + * without a GE adapter. + * + * Revision 1.5 1998/09/03 14:05:45 malthoff + * Change comment for SkGeInitPort(). Do not + * repair the queue sizes if invalid. + * + * Revision 1.4 1998/09/03 10:03:19 malthoff + * Implement the new interface according to the + * reviewed interface specification. + * + * Revision 1.3 1998/08/19 09:11:25 gklug + * fix: struct are removed from c-source (see CCC) + * + * Revision 1.2 1998/07/28 12:33:58 malthoff + * Add 'IoC' parameter in function declaration and SK IO macros. + * + * Revision 1.1 1998/07/23 09:48:57 malthoff + * Creation. First dummy 'C' file. + * SkGeInit(Level 0) is card_start for GE. + * SkGeDeInit() is card_stop for GE. + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/* global variables ***********************************************************/ + +/* local variables ************************************************************/ + +static const char SysKonnectFileId[] = + "@(#)$Id: skgeinit.c,v 1.85 2003/02/05 15:30:33 rschmidt Exp $ (C) SK "; + +struct s_QOffTab { + int RxQOff; /* Receive Queue Address Offset */ + int XsQOff; /* Sync Tx Queue Address Offset */ + int XaQOff; /* Async Tx Queue Address Offset */ +}; +static struct s_QOffTab QOffTab[] = { + {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2} +}; + + +/****************************************************************************** + * + * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring + * + * Description: + * Enable or disable the descriptor polling of the receive descriptor + * ring (RxD) for port 'Port'. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * + * Returns: + * nothing + */ +void SkGePollRxD( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (PollRxD) ? + CSR_ENA_POL : CSR_DIS_POL); +} /* SkGePollRxD */ + + +/****************************************************************************** + * + * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings + * + * Description: + * Enable or disable the descriptor polling of the transmit descriptor + * ring(s) (TxD) for port 'Port'. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * + * Returns: + * nothing + */ +void SkGePollTxD( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ +{ + SK_GEPORT *pPrt; + SK_U32 DWord; + + pPrt = &pAC->GIni.GP[Port]; + + DWord = (PollTxD) ? CSR_ENA_POL : CSR_DIS_POL; + + if (pPrt->PXSQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord); + } + + if (pPrt->PXAQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord); + } +} /* SkGePollTxD */ + + +/****************************************************************************** + * + * SkGeYellowLED() - Switch the yellow LED on or off. + * + * Description: + * Switch the yellow LED on or off. + * + * Note: + * This function may be called any time after SkGeInit(Level 1). + * + * Returns: + * nothing + */ +void SkGeYellowLED( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int State) /* yellow LED state, 0 = OFF, 0 != ON */ +{ + if (State == 0) { + /* Switch yellow LED OFF */ + SK_OUT8(IoC, B0_LED, LED_STAT_OFF); + } + else { + /* Switch yellow LED ON */ + SK_OUT8(IoC, B0_LED, LED_STAT_ON); + } +} /* SkGeYellowLED */ + + +/****************************************************************************** + * + * SkGeXmitLED() - Modify the Operational Mode of a transmission LED. + * + * Description: + * The Rx or Tx LED which is specified by 'Led' will be + * enabled, disabled or switched on in test mode. + * + * Note: + * 'Led' must contain the address offset of the LEDs INI register. + * + * Usage: + * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA); + * + * Returns: + * nothing + */ +void SkGeXmitLED( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Led, /* offset to the LED Init Value register */ +int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */ +{ + SK_U32 LedIni; + + switch (Mode) { + case SK_LED_ENA: + LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100; + SK_OUT32(IoC, Led + XMIT_LED_INI, LedIni); + SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START); + break; + case SK_LED_TST: + SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_ON); + SK_OUT32(IoC, Led + XMIT_LED_CNT, 100); + SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START); + break; + case SK_LED_DIS: + default: + /* + * Do NOT stop the LED Timer here. The LED might be + * in on state. But it needs to go off. + */ + SK_OUT32(IoC, Led + XMIT_LED_CNT, 0); + SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF); + break; + } + + /* + * 1000BT: The Transmit LED is driven by the PHY. + * But the default LED configuration is used for + * Level One and Broadcom PHYs. + * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.) + * (In this case it has to be added here. But we will see. XXX) + */ +} /* SkGeXmitLED */ + + +/****************************************************************************** + * + * DoCalcAddr() - Calculates the start and the end address of a queue. + * + * Description: + * This function calculates the start and the end address of a queue. + * Afterwards the 'StartVal' is incremented to the next start position. + * If the port is already initialized the calculated values + * will be checked against the configured values and an + * error will be returned, if they are not equal. + * If the port is not initialized the values will be written to + * *StartAdr and *EndAddr. + * + * Returns: + * 0: success + * 1: configuration error + */ +static int DoCalcAddr( +SK_AC *pAC, /* adapter context */ +SK_GEPORT *pPrt, /* port index */ +int QuSize, /* size of the queue to configure in kB */ +SK_U32 *StartVal, /* start value for address calculation */ +SK_U32 *QuStartAddr, /* start addr to calculate */ +SK_U32 *QuEndAddr) /* end address to calculate */ +{ + SK_U32 EndVal; + SK_U32 NextStart; + int Rtv; + + Rtv = 0; + if (QuSize == 0) { + EndVal = *StartVal; + NextStart = EndVal; + } + else { + EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1; + NextStart = EndVal + 1; + } + + if (pPrt->PState >= SK_PRT_INIT) { + if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) { + Rtv = 1; + } + } + else { + *QuStartAddr = *StartVal; + *QuEndAddr = EndVal; + } + + *StartVal = NextStart; + return(Rtv); +} /* DoCalcAddr */ + +/****************************************************************************** + * + * SkGeInitAssignRamToQueues() - allocate default queue sizes + * + * Description: + * This function assigns the memory to the different queues and ports. + * When DualNet is set to SK_TRUE all ports get the same amount of memory. + * Otherwise the first port gets most of the memory and all the + * other ports just the required minimum. + * This function can only be called when pAC->GIni.GIRamSize and + * pAC->GIni.GIMacsFound have been initialized, usually this happens + * at init level 1 + * + * Returns: + * 0 - ok + * 1 - invalid input values + * 2 - not enough memory + */ + +int SkGeInitAssignRamToQueues( +SK_AC *pAC, /* Adapter context */ +int ActivePort, /* Active Port in RLMT mode */ +SK_BOOL DualNet) /* adapter context */ +{ + int i; + int UsedKilobytes; /* memory already assigned */ + int ActivePortKilobytes; /* memory available for active port */ + SK_GEPORT *pGePort; + + UsedKilobytes = 0; + + if (ActivePort >= pAC->GIni.GIMacsFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n", + ActivePort)); + return(1); + } + if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) + + ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n", + pAC->GIni.GIRamSize)); + return(2); + } + + + if (DualNet) { + /* every port gets the same amount of memory */ + ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound; + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + pGePort = &pAC->GIni.GP[i]; + + /* take away the minimum memory for active queues */ + ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); + + /* receive queue gets the minimum + 80% of the rest */ + pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB(( + ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100)) + + SK_MIN_RXQ_SIZE; + + ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); + + /* synchronous transmit queue */ + pGePort->PXSQSize = 0; + + /* asynchronous transmit queue */ + pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes + + SK_MIN_TXQ_SIZE); + } + } + else { + /* Rlmt Mode or single link adapter */ + + /* Set standby queue size defaults for all standby ports */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + if (i != ActivePort) { + pGePort = &pAC->GIni.GP[i]; + + pGePort->PRxQSize = SK_MIN_RXQ_SIZE; + pGePort->PXAQSize = SK_MIN_TXQ_SIZE; + pGePort->PXSQSize = 0; + + /* Count used RAM */ + UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize; + } + } + /* what's left? */ + ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes; + + /* assign it to the active port */ + /* first take away the minimum memory */ + ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); + pGePort = &pAC->GIni.GP[ActivePort]; + + /* receive queue get's the minimum + 80% of the rest */ + pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes * + (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE; + + ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); + + /* synchronous transmit queue */ + pGePort->PXSQSize = 0; + + /* asynchronous transmit queue */ + pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) + + SK_MIN_TXQ_SIZE; + } +#ifdef VCPU + VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n", + pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize); +#endif /* VCPU */ + + return(0); +} /* SkGeInitAssignRamToQueues */ + +/****************************************************************************** + * + * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration + * + * Description: + * This function verifies the Queue Size Configuration specified + * in the variables PRxQSize, PXSQSize, and PXAQSize of all + * used ports. + * This requirements must be fullfilled to have a valid configuration: + * - The size of all queues must not exceed GIRamSize. + * - The queue sizes must be specified in units of 8 kB. + * - The size of Rx queues of available ports must not be + * smaller than 16 kB. + * - The size of at least one Tx queue (synch. or asynch.) + * of available ports must not be smaller than 16 kB + * when Jumbo Frames are used. + * - The RAM start and end addresses must not be changed + * for ports which are already initialized. + * Furthermore SkGeCheckQSize() defines the Start and End Addresses + * of all ports and stores them into the HWAC port structure. + * + * Returns: + * 0: Queue Size Configuration valid + * 1: Queue Size Configuration invalid + */ +static int SkGeCheckQSize( +SK_AC *pAC, /* adapter context */ +int Port) /* port index */ +{ + SK_GEPORT *pPrt; + int UsedMem; /* total memory used (max. found ports) */ + int i; + int Rtv; + int Rtv2; + SK_U32 StartAddr; + + UsedMem = 0; + Rtv = 0; + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + pPrt = &pAC->GIni.GP[i]; + + if ((pPrt->PRxQSize & QZ_UNITS) != 0 || + (pPrt->PXSQSize & QZ_UNITS) != 0 || + (pPrt->PXAQSize & QZ_UNITS) != 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); + return(1); + } + + if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG); + return(1); + } + + /* + * the size of at least one Tx queue (synch. or asynch.) has to be > 0. + * if Jumbo Frames are used, this size has to be >= 16 kB. + */ + if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) || + (pAC->GIni.GIPortUsage == SK_JUMBO_LINK && + ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) || + (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG); + return(1); + } + + UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize; + } + + if (UsedMem > pAC->GIni.GIRamSize) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); + return(1); + } + + /* Now start address calculation */ + StartAddr = pAC->GIni.GIRamOffs; + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + pPrt = &pAC->GIni.GP[i]; + + /* Calculate/Check values for the receive queue */ + Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr, + &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd); + Rtv |= Rtv2; + + /* Calculate/Check values for the synchronous Tx queue */ + Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr, + &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd); + Rtv |= Rtv2; + + /* Calculate/Check values for the asynchronous Tx queue */ + Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr, + &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd); + Rtv |= Rtv2; + + if (Rtv) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG); + return(1); + } + } + + return(0); +} /* SkGeCheckQSize */ + + +/****************************************************************************** + * + * SkGeInitMacArb() - Initialize the MAC Arbiter + * + * Description: + * This function initializes the MAC Arbiter. + * It must not be called if there is still an + * initialized or active port. + * + * Returns: + * nothing + */ +static void SkGeInitMacArb( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + /* release local reset */ + SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR); + + /* configure timeout values */ + SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53); + SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53); + SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53); + SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53); + + SK_OUT8(IoC, B3_MA_RCINI_RX1, 0); + SK_OUT8(IoC, B3_MA_RCINI_RX2, 0); + SK_OUT8(IoC, B3_MA_RCINI_TX1, 0); + SK_OUT8(IoC, B3_MA_RCINI_TX2, 0); + + /* recovery values are needed for XMAC II Rev. B2 only */ + /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */ + + /* + * There is no start or enable button to push, therefore + * the MAC arbiter is configured and enabled now. + */ +} /* SkGeInitMacArb */ + + +/****************************************************************************** + * + * SkGeInitPktArb() - Initialize the Packet Arbiter + * + * Description: + * This function initializes the Packet Arbiter. + * It must not be called if there is still an + * initialized or active port. + * + * Returns: + * nothing + */ +static void SkGeInitPktArb( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + /* release local reset */ + SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR); + + /* configure timeout values */ + SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); + SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); + SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); + SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); + + /* + * enable timeout timers if jumbo frames not used + * NOTE: the packet arbiter timeout interrupt is needed for + * half duplex hangup workaround + */ + if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) { + if (pAC->GIni.GIMacsFound == 1) { + SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1); + } + else { + SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1 | PA_ENA_TO_TX2); + } + } +} /* SkGeInitPktArb */ + + +/****************************************************************************** + * + * SkGeInitMacFifo() - Initialize the MAC FIFOs + * + * Description: + * Initialize all MAC FIFOs of the specified port + * + * Returns: + * nothing + */ +static void SkGeInitMacFifo( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 Word; +#ifdef VCPU + SK_U32 DWord; +#endif /* VCPU */ + /* + * For each FIFO: + * - release local reset + * - use default value for MAC FIFO size + * - setup defaults for the control register + * - enable the FIFO + */ + + Word = GMF_RX_CTRL_DEF; + + if (pAC->GIni.GIGenesis) { + /* Configure Rx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR); + SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF); + SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD); + + /* Configure Tx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR); + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); + SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD); + + /* Enable frame flushing if jumbo frames used */ + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH); + } + } + else { + /* set Rx GMAC FIFO Flush Mask */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK); + + if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) { + + Word &= ~GMF_RX_F_FL_ON; + } + + /* Configure Rx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word); + + /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); + + /* Configure Tx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); + SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF); + +#ifdef VCPU + SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord); + SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord); +#endif /* VCPU */ + + /* set Tx GMAC FIFO Almost Empty Threshold */ +/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */ + } +} /* SkGeInitMacFifo */ + + +/****************************************************************************** + * + * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting + * + * Description: + * This function starts the Link Sync Counter of the specified + * port and enables the generation of an Link Sync IRQ. + * The Link Sync Counter may be used to detect an active link, + * if autonegotiation is not used. + * + * Note: + * o To ensure receiving the Link Sync Event the LinkSyncCounter + * should be initialized BEFORE clearing the XMAC's reset! + * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this + * function. + * + * Returns: + * nothing + */ +void SkGeLoadLnkSyncCnt( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U32 CntVal) /* Counter value */ +{ + SK_U32 OrgIMsk; + SK_U32 NewIMsk; + SK_U32 ISrc; + SK_BOOL IrqPend; + + /* stop counter */ + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP); + + /* + * ASIC problem: + * Each time starting the Link Sync Counter an IRQ is generated + * by the adapter. See problem report entry from 21.07.98 + * + * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ + * if no IRQ is already pending. + */ + IrqPend = SK_FALSE; + SK_IN32(IoC, B0_ISRC, &ISrc); + SK_IN32(IoC, B0_IMSK, &OrgIMsk); + if (Port == MAC_1) { + NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1; + if ((ISrc & IS_LNK_SYNC_M1) != 0) { + IrqPend = SK_TRUE; + } + } + else { + NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2; + if ((ISrc & IS_LNK_SYNC_M2) != 0) { + IrqPend = SK_TRUE; + } + } + if (!IrqPend) { + SK_OUT32(IoC, B0_IMSK, NewIMsk); + } + + /* load counter */ + SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal); + + /* start counter */ + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START); + + if (!IrqPend) { + /* clear the unexpected IRQ, and restore the interrupt mask */ + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ); + SK_OUT32(IoC, B0_IMSK, OrgIMsk); + } +} /* SkGeLoadLnkSyncCnt*/ + + +/****************************************************************************** + * + * SkGeCfgSync() - Configure synchronous bandwidth for this port. + * + * Description: + * This function may be used to configure synchronous bandwidth + * to the specified port. This may be done any time after + * initializing the port. The configuration values are NOT saved + * in the HWAC port structure and will be overwritten any + * time when stopping and starting the port. + * Any values for the synchronous configuration will be ignored + * if the size of the synchronous queue is zero! + * + * The default configuration for the synchronous service is + * TXA_ENA_FSYNC. This means if the size of + * the synchronous queue is unequal zero but no specific + * synchronous bandwidth is configured, the synchronous queue + * will always have the 'unlimited' transmit priority! + * + * This mode will be restored if the synchronous bandwidth is + * deallocated ('IntTime' = 0 and 'LimCount' = 0). + * + * Returns: + * 0: success + * 1: parameter configuration error + * 2: try to configure quality of service although no + * synchronous queue is configured + */ +int SkGeCfgSync( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U32 IntTime, /* Interval Timer Value in units of 8ns */ +SK_U32 LimCount, /* Number of bytes to transfer during IntTime */ +int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */ +{ + int Rtv; + + Rtv = 0; + + /* check the parameters */ + if (LimCount > IntTime || + (LimCount == 0 && IntTime != 0) || + (LimCount != 0 && IntTime == 0)) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); + return(1); + } + + if (pAC->GIni.GP[Port].PXSQSize == 0) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG); + return(2); + } + + /* calculate register values */ + IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100; + LimCount = LimCount / 8; + + if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); + return(1); + } + + /* + * - Enable 'Force Sync' to ensure the synchronous queue + * has the priority while configuring the new values. + * - Also 'disable alloc' to ensure the settings complies + * to the SyncMode parameter. + * - Disable 'Rate Control' to configure the new values. + * - write IntTime and LimCount + * - start 'Rate Control' and disable 'Force Sync' + * if Interval Timer or Limit Counter not zero. + */ + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), + TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); + + SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime); + SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount); + + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), + (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC))); + + if (IntTime != 0 || LimCount != 0) { + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC); + } + + return(0); +} /* SkGeCfgSync */ + + +/****************************************************************************** + * + * DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue + * + * Desccription: + * If the queue is used, enable and initialize it. + * Make sure the queue is still reset, if it is not used. + * + * Returns: + * nothing + */ +static void DoInitRamQueue( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int QuIoOffs, /* Queue IO Address Offset */ +SK_U32 QuStartAddr, /* Queue Start Address */ +SK_U32 QuEndAddr, /* Queue End Address */ +int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */ +{ + SK_U32 RxUpThresVal; + SK_U32 RxLoThresVal; + + if (QuStartAddr != QuEndAddr) { + /* calculate thresholds, assume we have a big Rx queue */ + RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8; + RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8; + + /* build HW address format */ + QuStartAddr = QuStartAddr / 8; + QuEndAddr = QuEndAddr / 8; + + /* release local reset */ + SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR); + + /* configure addresses */ + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr); + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr); + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr); + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr); + + switch (QuType) { + case SK_RX_SRAM_Q: + /* configure threshold for small Rx Queue */ + RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8; + + /* continue with SK_RX_BRAM_Q */ + case SK_RX_BRAM_Q: + /* write threshold for Rx Queue */ + + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal); + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal); + + /* the high priority threshold not used */ + break; + case SK_TX_RAM_Q: + /* + * Do NOT use Store & Forward under normal operation due to + * performance optimization (GENESIS only). + * But if Jumbo Frames are configured (XMAC Tx FIFO is only 4 kB) + * or YUKON is used ((GMAC Tx FIFO is only 1 kB) + * we NEED Store & Forward of the RAM buffer. + */ + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK || + !pAC->GIni.GIGenesis) { + /* enable Store & Forward Mode for the Tx Side */ + SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD); + } + break; + } + + /* set queue operational */ + SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD); + } + else { + /* ensure the queue is still disabled */ + SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET); + } +} /* DoInitRamQueue */ + + +/****************************************************************************** + * + * SkGeInitRamBufs() - Initialize the RAM Buffer Queues + * + * Description: + * Initialize all RAM Buffer Queues of the specified port + * + * Returns: + * nothing + */ +static void SkGeInitRamBufs( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + int RxQType; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) { + RxQType = SK_RX_SRAM_Q; /* small Rx Queue */ + } + else { + RxQType = SK_RX_BRAM_Q; /* big Rx Queue */ + } + + DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart, + pPrt->PRxQRamEnd, RxQType); + + DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart, + pPrt->PXsQRamEnd, SK_TX_RAM_Q); + + DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart, + pPrt->PXaQRamEnd, SK_TX_RAM_Q); + +} /* SkGeInitRamBufs */ + + +/****************************************************************************** + * + * SkGeInitRamIface() - Initialize the RAM Interface + * + * Description: + * This function initializes the Adapters RAM Interface. + * + * Note: + * This function is used in the diagnostics. + * + * Returns: + * nothing + */ +void SkGeInitRamIface( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + /* release local reset */ + SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR); + + /* configure timeout values */ + SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53); + +} /* SkGeInitRamIface */ + + +/****************************************************************************** + * + * SkGeInitBmu() - Initialize the BMU state machines + * + * Description: + * Initialize all BMU state machines of the specified port + * + * Returns: + * nothing + */ +static void SkGeInitBmu( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U32 RxWm; + SK_U32 TxWm; + + pPrt = &pAC->GIni.GP[Port]; + + RxWm = SK_BMU_RX_WM; + TxWm = SK_BMU_TX_WM; + + if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) { + /* for better performance */ + RxWm /= 2; + TxWm /= 2; + } + + /* Rx Queue: Release all local resets and set the watermark */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm); + + /* + * Tx Queue: Release all local resets if the queue is used ! + * set watermark + */ + if (pPrt->PXSQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm); + } + + if (pPrt->PXAQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm); + } + /* + * Do NOT enable the descriptor poll timers here, because + * the descriptor addresses are not specified yet. + */ +} /* SkGeInitBmu */ + + +/****************************************************************************** + * + * TestStopBit() - Test the stop bit of the queue + * + * Description: + * Stopping a queue is not as simple as it seems to be. + * If descriptor polling is enabled, it may happen + * that RX/TX stop is done and SV idle is NOT set. + * In this case we have to issue another stop command. + * + * Returns: + * The queues control status register + */ +static SK_U32 TestStopBit( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int QuIoOffs) /* Queue IO Address Offset */ +{ + SK_U32 QuCsr; /* CSR contents */ + + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + + if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) { + /* Stop Descriptor overridden by start command */ + SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP); + + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + } + + return(QuCsr); +} /* TestStopBit */ + + +/****************************************************************************** + * + * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'. + * + * Description: + * After calling this function the descriptor rings and Rx and Tx + * queues of this port may be reconfigured. + * + * It is possible to stop the receive and transmit path separate or + * both together. + * + * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC. + * The receive queue is still active and + * the pending Rx frames may be still transferred + * into the RxD. + * SK_STOP_RX Stop the receive path. The tansmit path + * has to be stopped once before. + * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX + * + * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive. + * SK_HARD_RST Resets the MAC and the PHY. + * + * Example: + * 1) A Link Down event was signaled for a port. Therefore the activity + * of this port should be stopped and a hardware reset should be issued + * to enable the workaround of XMAC errata #2. But the received frames + * should not be discarded. + * ... + * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST); + * (transfer all pending Rx frames) + * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST); + * ... + * + * 2) An event was issued which request the driver to switch + * the 'virtual active' link to an other already active port + * as soon as possible. The frames in the receive queue of this + * port may be lost. But the PHY must not be reset during this + * event. + * ... + * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST); + * ... + * + * Extended Description: + * If SK_STOP_TX is set, + * o disable the MAC's receive and transmitter to prevent + * from sending incomplete frames + * o stop the port's transmit queues before terminating the + * BMUs to prevent from performing incomplete PCI cycles + * on the PCI bus + * - The network Rx and Tx activity and PCI Tx transfer is + * disabled now. + * o reset the MAC depending on the RstMode + * o Stop Interval Timer and Limit Counter of Tx Arbiter, + * also disable Force Sync bit and Enable Alloc bit. + * o perform a local reset of the port's Tx path + * - reset the PCI FIFO of the async Tx queue + * - reset the PCI FIFO of the sync Tx queue + * - reset the RAM Buffer async Tx queue + * - reset the RAM Buffer sync Tx queue + * - reset the MAC Tx FIFO + * o switch Link and Tx LED off, stop the LED counters + * + * If SK_STOP_RX is set, + * o stop the port's receive queue + * - The path data transfer activity is fully stopped now. + * o perform a local reset of the port's Rx path + * - reset the PCI FIFO of the Rx queue + * - reset the RAM Buffer receive queue + * - reset the MAC Rx FIFO + * o switch Rx LED off, stop the LED counter + * + * If all ports are stopped, + * o reset the RAM Interface. + * + * Notes: + * o This function may be called during the driver states RESET_PORT and + * SWITCH_PORT. + */ +void SkGeStopPort( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +int Port, /* port to stop (MAC_1 + n) */ +int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */ +int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ +{ +#ifndef SK_DIAG + SK_EVPARA Para; +#endif /* !SK_DIAG */ + SK_GEPORT *pPrt; + SK_U32 DWord; + SK_U32 XsCsr; + SK_U32 XaCsr; + SK_U64 ToutStart; + int i; + int ToutCnt; + + pPrt = &pAC->GIni.GP[Port]; + + if ((Dir & SK_STOP_TX) != 0) { + /* disable receiver and transmitter */ + SkMacRxTxDisable(pAC, IoC, Port); + + /* stop both transmit queues */ + /* + * If the BMU is in the reset state CSR_STOP will terminate + * immediately. + */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP); + + ToutStart = SkOsGetTime(pAC); + ToutCnt = 0; + do { + /* + * Clear packet arbiter timeout to make sure + * this loop will terminate. + */ + SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_TX1 : + PA_CLR_TO_TX2); + + /* + * If the transfer stucks at the MAC the STOP command will not + * terminate if we don't flush the XMAC's transmit FIFO ! + */ + SkMacFlushTxFifo(pAC, IoC, Port); + + XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); + XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff); + + if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) { + /* + * Timeout of 1/18 second reached. + * This needs to be checked at 1/18 sec only. + */ + ToutCnt++; + if (ToutCnt > 1) { + /* Might be a problem when the driver event handler + * calls StopPort again. XXX. + */ + + /* Fatal Error, Loop aborted */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018, + SKERR_HWI_E018MSG); +#ifndef SK_DIAG + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); +#endif /* !SK_DIAG */ + return; + } + /* + * Cache incoherency workaround: Assume a start command + * has been lost while sending the frame. + */ + ToutStart = SkOsGetTime(pAC); + + if ((XsCsr & CSR_STOP) != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START); + } + if ((XaCsr & CSR_STOP) != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START); + } + } + + /* + * Because of the ASIC problem report entry from 21.08.1998 it is + * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set. + */ + } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE || + (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); + + /* Reset the MAC depending on the RstMode */ + if (RstMode == SK_SOFT_RST) { + SkMacSoftRst(pAC, IoC, Port); + } + else { + SkMacHardRst(pAC, IoC, Port); + } + + /* Disable Force Sync bit and Enable Alloc bit */ + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), + TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); + + /* Stop Interval Timer and Limit Counter of Tx Arbiter */ + SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L); + SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L); + + /* Perform a local reset of the port's Tx path */ + + /* Reset the PCI FIFO of the async Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET); + /* Reset the PCI FIFO of the sync Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET); + /* Reset the RAM Buffer async Tx queue */ + SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET); + /* Reset the RAM Buffer sync Tx queue */ + SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET); + + /* Reset Tx MAC FIFO */ + if (pAC->GIni.GIGenesis) { + /* Note: MFF_RST_SET does NOT reset the XMAC ! */ + SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET); + + /* switch Link and Tx LED off, stop the LED counters */ + /* Link LED is switched off by the RLMT and the Diag itself */ + SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS); + } + else { + /* Reset TX MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); + } + } + + if ((Dir & SK_STOP_RX) != 0) { + /* + * The RX Stop Command will not terminate if no buffers + * are queued in the RxD ring. But it will always reach + * the Idle state. Therefore we can use this feature to + * stop the transfer of received packets. + */ + /* stop the port's receive queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP); + + i = 100; + do { + /* + * Clear packet arbiter timeout to make sure + * this loop will terminate + */ + SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_RX1 : + PA_CLR_TO_RX2); + + DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff); + + /* timeout if i==0 (bug fix for #10748) */ + if (--i == 0) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024, + SKERR_HWI_E024MSG); + break; + } + /* + * because of the ASIC problem report entry from 21.08.98 + * it is required to wait until CSR_STOP is reset and + * CSR_SV_IDLE is set. + */ + } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); + + /* The path data transfer activity is fully stopped now */ + + /* Perform a local reset of the port's Rx path */ + + /* Reset the PCI FIFO of the Rx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET); + /* Reset the RAM Buffer receive queue */ + SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET); + + /* Reset Rx MAC FIFO */ + if (pAC->GIni.GIGenesis) { + + SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET); + + /* switch Rx LED off, stop the LED counter */ + SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS); + } + else { + /* Reset Rx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); + } + } +} /* SkGeStopPort */ + + +/****************************************************************************** + * + * SkGeInit0() - Level 0 Initialization + * + * Description: + * - Initialize the BMU address offsets + * + * Returns: + * nothing + */ +static void SkGeInit0( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + int i; + SK_GEPORT *pPrt; + + for (i = 0; i < SK_MAX_MACS; i++) { + pPrt = &pAC->GIni.GP[i]; + + pPrt->PState = SK_PRT_RESET; + pPrt->PRxQOff = QOffTab[i].RxQOff; + pPrt->PXsQOff = QOffTab[i].XsQOff; + pPrt->PXaQOff = QOffTab[i].XaQOff; + pPrt->PCheckPar = SK_FALSE; + pPrt->PIsave = 0; + pPrt->PPrevShorts = 0; + pPrt->PLinkResCt = 0; + pPrt->PAutoNegTOCt = 0; + pPrt->PPrevRx = 0; + pPrt->PPrevFcs = 0; + pPrt->PRxLim = SK_DEF_RX_WA_LIM; + pPrt->PLinkMode = SK_LMODE_AUTOFULL; + pPrt->PLinkSpeedCap = SK_LSPEED_CAP_1000MBPS; + pPrt->PLinkSpeed = SK_LSPEED_1000MBPS; + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_UNKNOWN; + pPrt->PLinkModeConf = SK_LMODE_AUTOSENSE; + pPrt->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + pPrt->PLinkBroken = SK_TRUE; /* See WA code */ + pPrt->PLinkCap = (SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL | + SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL); + pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; + pPrt->PFlowCtrlCap = SK_FLOW_MODE_SYM_OR_REM; + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + pPrt->PMSCap = 0; + pPrt->PMSMode = SK_MS_MODE_AUTO; + pPrt->PMSStatus = SK_MS_STAT_UNSET; + pPrt->PAutoNegFail = SK_FALSE; + pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; + pPrt->PHWLinkUp = SK_FALSE; + } + + pAC->GIni.GIPortUsage = SK_RED_LINK; + +} /* SkGeInit0*/ + +#ifdef SK_PCI_RESET + +/****************************************************************************** + * + * SkGePciReset() - Reset PCI interface + * + * Description: + * o Read PCI configuration. + * o Change power state to 3. + * o Change power state to 0. + * o Restore PCI configuration. + * + * Returns: + * 0: Success. + * 1: Power state could not be changed to 3. + */ +static int SkGePciReset( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + int i; + SK_U16 PmCtlSts; + SK_U32 Bp1; + SK_U32 Bp2; + SK_U16 PciCmd; + SK_U8 Cls; + SK_U8 Lat; + SK_U8 ConfigSpace[PCI_CFG_SIZE]; + + /* + * Note: Switching to D3 state is like a software reset. + * Switching from D3 to D0 is a hardware reset. + * We have to save and restore the configuration space. + */ + for (i = 0; i < PCI_CFG_SIZE; i++) { + SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]); + } + + /* We know the RAM Interface Arbiter is enabled. */ + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3); + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts); + + if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) { + return(1); + } + + /* Return to D0 state. */ + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0); + + /* Check for D0 state. */ + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts); + + if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) { + return(1); + } + + /* Check PCI Config Registers. */ + SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd); + SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls); + SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1); + SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2); + SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat); + + if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 || + Lat != 0) { + return(1); + } + + /* Restore PCI Config Space. */ + for (i = 0; i < PCI_CFG_SIZE; i++) { + SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]); + } + + return(0); +} /* SkGePciReset */ + +#endif /* SK_PCI_RESET */ + +/****************************************************************************** + * + * SkGeInit1() - Level 1 Initialization + * + * Description: + * o Do a software reset. + * o Clear all reset bits. + * o Verify that the detected hardware is present. + * Return an error if not. + * o Get the hardware configuration + * + Read the number of MACs/Ports. + * + Read the RAM size. + * + Read the PCI Revision Id. + * + Find out the adapters host clock speed + * + Read and check the PHY type + * + * Returns: + * 0: success + * 5: Unexpected PHY type detected + * 6: HW self test failed + */ +static int SkGeInit1( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + SK_U8 Byte; + SK_U16 Word; + SK_U16 CtrlStat; + SK_U32 FlashAddr; + int RetVal; + int i; + + RetVal = 0; + + /* save CLK_RUN bits (YUKON-Lite) */ + SK_IN16(IoC, B0_CTST, &CtrlStat); + +#ifdef SK_PCI_RESET + (void)SkGePciReset(pAC, IoC); +#endif /* SK_PCI_RESET */ + + /* do the SW-reset */ + SK_OUT8(IoC, B0_CTST, CS_RST_SET); + + /* release the SW-reset */ + SK_OUT8(IoC, B0_CTST, CS_RST_CLR); + + /* reset all error bits in the PCI STATUS register */ + /* + * Note: PCI Cfg cycles cannot be used, because they are not + * available on some platforms after 'boot time'. + */ + SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + + /* release Master Reset */ + SK_OUT8(IoC, B0_CTST, CS_MRST_CLR); + +#ifdef CLK_RUN + CtrlStat |= CS_CLK_RUN_ENA; +#endif /* CLK_RUN */ + + /* restore CLK_RUN bits */ + SK_OUT16(IoC, B0_CTST, CtrlStat & + (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)); + + /* read Chip Identification Number */ + SK_IN8(IoC, B2_CHIP_ID, &Byte); + pAC->GIni.GIChipId = Byte; + + /* read number of MACs */ + SK_IN8(IoC, B2_MAC_CFG, &Byte); + pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2; + + /* get Chip Revision Number */ + pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4); + + /* get diff. PCI parameters */ + SK_IN16(IoC, B0_CTST, &CtrlStat); + + /* read the adapters RAM size */ + SK_IN8(IoC, B2_E_0, &Byte); + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + + pAC->GIni.GIGenesis = SK_TRUE; + + if (Byte == 3) { + /* special case: 4 x 64k x 36, offset = 0x80000 */ + pAC->GIni.GIRamSize = 1024; + pAC->GIni.GIRamOffs = (SK_U32)512 * 1024; + } + else { + pAC->GIni.GIRamSize = (int)Byte * 512; + pAC->GIni.GIRamOffs = 0; + } + /* all GE adapters work with 53.125 MHz host clock */ + pAC->GIni.GIHstClkFact = SK_FACT_53; + + /* set Descr. Poll Timer Init Value to 250 ms */ + pAC->GIni.GIPollTimerVal = + SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100; + } + else { + pAC->GIni.GIGenesis = SK_FALSE; + +#ifndef VCPU + pAC->GIni.GIRamSize = (Byte == 0) ? 128 : (int)Byte * 4; +#else + pAC->GIni.GIRamSize = 128; +#endif + pAC->GIni.GIRamOffs = 0; + + /* WA for chip Rev. A */ + pAC->GIni.GIWolOffs = (pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0; + + /* get PM Capabilities of PCI config space */ + SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word); + + /* check if VAUX is available */ + if (((CtrlStat & CS_VAUX_AVAIL) != 0) && + /* check also if PME from D3cold is set */ + ((Word & PCI_PME_D3C_SUP) != 0)) { + /* set entry in GE init struct */ + pAC->GIni.GIVauxAvail = SK_TRUE; + } + + /* save Flash-Address Register */ + SK_IN32(IoC, B2_FAR, &FlashAddr); + + /* test Flash-Address Register */ + SK_OUT8(IoC, B2_FAR + 3, 0xff); + SK_IN8(IoC, B2_FAR + 3, &Byte); + + pAC->GIni.GIYukonLite = (SK_BOOL)(Byte != 0); + + /* restore Flash-Address Register */ + SK_OUT32(IoC, B2_FAR, FlashAddr); + + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + /* set GMAC Link Control reset */ + SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET); + + /* clear GMAC Link Control reset */ + SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR); + } + /* all YU chips work with 78.125 MHz host clock */ + pAC->GIni.GIHstClkFact = SK_FACT_78; + + pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */ + } + + /* check if 64-bit PCI Slot is present */ + pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0); + + /* check if 66 MHz PCI Clock is active */ + pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0); + + /* read PCI HW Revision Id. */ + SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte); + pAC->GIni.GIPciHwRev = Byte; + + /* read the PMD type */ + SK_IN8(IoC, B2_PMD_TYP, &Byte); + pAC->GIni.GICopperType = (SK_U8)(Byte == 'T'); + + /* read the PHY type */ + SK_IN8(IoC, B2_E_1, &Byte); + + Byte &= 0x0f; /* the PHY type is stored in the lower nibble */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + if (pAC->GIni.GIGenesis) { + switch (Byte) { + case SK_PHY_XMAC: + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC; + break; + case SK_PHY_BCOM: + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM; + pAC->GIni.GP[i].PMSCap = + SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE; + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE; + break; + case SK_PHY_NAT: + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT; + break; +#endif /* OTHER_PHY */ + default: + /* ERROR: unexpected PHY type detected */ + RetVal = 5; + break; + } + } + else { + if (Byte == 0) { + /* if this field is not initialized */ + Byte = SK_PHY_MARV_COPPER; + pAC->GIni.GICopperType = SK_TRUE; + } + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV; + + if (pAC->GIni.GICopperType) { + pAC->GIni.GP[i].PLinkSpeedCap = SK_LSPEED_CAP_AUTO | + SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS | + SK_LSPEED_CAP_1000MBPS; + pAC->GIni.GP[i].PLinkSpeed = SK_LSPEED_AUTO; + pAC->GIni.GP[i].PMSCap = + SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE; + } + else { + Byte = SK_PHY_MARV_FIBER; + } + } + + pAC->GIni.GP[i].PhyType = Byte; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("PHY type: %d PHY addr: %04x\n", Byte, + pAC->GIni.GP[i].PhyAddr)); + } + + /* get Mac Type & set function pointers dependent on */ + if (pAC->GIni.GIGenesis) { + pAC->GIni.GIMacType = SK_MAC_XMAC; + + pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats; + pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic; + pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter; + pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus; + } + else { + pAC->GIni.GIMacType = SK_MAC_GMAC; + + pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats; + pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic; + pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter; + pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus; + +#ifdef SPECIAL_HANDLING + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + /* check HW self test result */ + SK_IN8(IoC, B2_E_3, &Byte); + if ((Byte & B2_E3_RES_MASK) != 0) { + RetVal = 6; + } + } +#endif + } + return(RetVal); +} /* SkGeInit1 */ + + +/****************************************************************************** + * + * SkGeInit2() - Level 2 Initialization + * + * Description: + * - start the Blink Source Counter + * - start the Descriptor Poll Timer + * - configure the MAC-Arbiter + * - configure the Packet-Arbiter + * - enable the Tx Arbiters + * - enable the RAM Interface Arbiter + * + * Returns: + * nothing + */ +static void SkGeInit2( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + SK_U32 DWord; + int i; + + /* start the Descriptor Poll Timer */ + if (pAC->GIni.GIPollTimerVal != 0) { + if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) { + pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG); + } + SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal); + SK_OUT8(IoC, B28_DPT_CTRL, DPT_START); + } + + if (pAC->GIni.GIGenesis) { + /* start the Blink Source Counter */ + DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100; + + SK_OUT32(IoC, B2_BSC_INI, DWord); + SK_OUT8(IoC, B2_BSC_CTRL, BSC_START); + + /* + * Configure the MAC Arbiter and the Packet Arbiter. + * They will be started once and never be stopped. + */ + SkGeInitMacArb(pAC, IoC); + + SkGeInitPktArb(pAC, IoC); + } + else { + /* start Time Stamp Timer */ + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START); + } + + /* enable the Tx Arbiters */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + SK_OUT8(IoC, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB); + } + + /* enable the RAM Interface Arbiter */ + SkGeInitRamIface(pAC, IoC); + +} /* SkGeInit2 */ + +/****************************************************************************** + * + * SkGeInit() - Initialize the GE Adapter with the specified level. + * + * Description: + * Level 0: Initialize the Module structures. + * Level 1: Generic Hardware Initialization. The IOP/MemBase pointer has + * to be set before calling this level. + * + * o Do a software reset. + * o Clear all reset bits. + * o Verify that the detected hardware is present. + * Return an error if not. + * o Get the hardware configuration + * + Set GIMacsFound with the number of MACs. + * + Store the RAM size in GIRamSize. + * + Save the PCI Revision ID in GIPciHwRev. + * o return an error + * if Number of MACs > SK_MAX_MACS + * + * After returning from Level 0 the adapter + * may be accessed with IO operations. + * + * Level 2: start the Blink Source Counter + * + * Returns: + * 0: success + * 1: Number of MACs exceeds SK_MAX_MACS (after level 1) + * 2: Adapter not present or not accessible + * 3: Illegal initialization level + * 4: Initialization Level 1 Call missing + * 5: Unexpected PHY type detected + * 6: HW self test failed + */ +int SkGeInit( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Level) /* initialization level */ +{ + int RetVal; /* return value */ + SK_U32 DWord; + + RetVal = 0; + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("SkGeInit(Level %d)\n", Level)); + + switch (Level) { + case SK_INIT_DATA: + /* Initialization Level 0 */ + SkGeInit0(pAC, IoC); + pAC->GIni.GILevel = SK_INIT_DATA; + break; + + case SK_INIT_IO: + /* Initialization Level 1 */ + RetVal = SkGeInit1(pAC, IoC); + if (RetVal != 0) { + break; + } + + /* check if the adapter seems to be accessible */ + SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L); + SK_IN32(IoC, B2_IRQM_INI, &DWord); + SK_OUT32(IoC, B2_IRQM_INI, 0L); + + if (DWord != 0x11335577L) { + RetVal = 2; + break; + } + + /* check if the number of GIMacsFound matches SK_MAX_MACS */ + if (pAC->GIni.GIMacsFound > SK_MAX_MACS) { + RetVal = 1; + break; + } + + /* Level 1 successfully passed */ + pAC->GIni.GILevel = SK_INIT_IO; + break; + + case SK_INIT_RUN: + /* Initialization Level 2 */ + if (pAC->GIni.GILevel != SK_INIT_IO) { +#ifndef SK_DIAG + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG); +#endif /* !SK_DIAG */ + RetVal = 4; + break; + } + SkGeInit2(pAC, IoC); + + /* Level 2 successfully passed */ + pAC->GIni.GILevel = SK_INIT_RUN; + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG); + RetVal = 3; + break; + } + + return(RetVal); +} /* SkGeInit */ + + +/****************************************************************************** + * + * SkGeDeInit() - Deinitialize the adapter + * + * Description: + * All ports of the adapter will be stopped if not already done. + * Do a software reset and switch off all LEDs. + * + * Returns: + * nothing + */ +void SkGeDeInit( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + int i; + SK_U16 Word; + +#ifndef VCPU + /* ensure I2C is ready */ + SkI2cWaitIrq(pAC, IoC); +#endif + + /* stop all current transfer activity */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + if (pAC->GIni.GP[i].PState != SK_PRT_STOP && + pAC->GIni.GP[i].PState != SK_PRT_RESET) { + + SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST); + } + } + + /* Reset all bits in the PCI STATUS register */ + /* + * Note: PCI Cfg cycles cannot be used, because they are not + * available on some platforms after 'boot time'. + */ + SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + + /* do the reset, all LEDs are switched off now */ + SK_OUT8(IoC, B0_CTST, CS_RST_SET); +} /* SkGeDeInit */ + + +/****************************************************************************** + * + * SkGeInitPort() Initialize the specified port. + * + * Description: + * PRxQSize, PXSQSize, and PXAQSize has to be + * configured for the specified port before calling this function. + * The descriptor rings has to be initialized too. + * + * o (Re)configure queues of the specified port. + * o configure the MAC of the specified port. + * o put ASIC and MAC(s) in operational mode. + * o initialize Rx/Tx and Sync LED + * o initialize RAM Buffers and MAC FIFOs + * + * The port is ready to connect when returning. + * + * Note: + * The MAC's Rx and Tx state machine is still disabled when returning. + * + * Returns: + * 0: success + * 1: Queue size initialization error. The configured values + * for PRxQSize, PXSQSize, or PXAQSize are invalid for one + * or more queues. The specified port was NOT initialized. + * An error log entry was generated. + * 2: The port has to be stopped before it can be initialized again. + */ +int SkGeInitPort( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port to configure */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (SkGeCheckQSize(pAC, Port) != 0) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG); + return(1); + } + + if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG); + return(2); + } + + /* configuration ok, initialize the Port now */ + + if (pAC->GIni.GIGenesis) { + /* initialize Rx, Tx and Link LED */ + /* + * If 1000BT Phy needs LED initialization than swap + * LED and XMAC initialization order + */ + SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA); + SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA); + /* The Link LED is initialized by RLMT or Diagnostics itself */ + + SkXmInitMac(pAC, IoC, Port); + } + else { + + SkGmInitMac(pAC, IoC, Port); + } + + /* do NOT initialize the Link Sync Counter */ + + SkGeInitMacFifo(pAC, IoC, Port); + + SkGeInitRamBufs(pAC, IoC, Port); + + if (pPrt->PXSQSize != 0) { + /* enable Force Sync bit if synchronous queue available */ + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC); + } + + SkGeInitBmu(pAC, IoC, Port); + + /* mark port as initialized */ + pPrt->PState = SK_PRT_INIT; + + return(0); +} /* SkGeInitPort */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skgemib.c b/drivers/sk98lin/skgemib.c new file mode 100644 index 0000000..4a9e9e6 --- /dev/null +++ b/drivers/sk98lin/skgemib.c @@ -0,0 +1,1060 @@ +/***************************************************************************** + * + * Name: skgemib.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.7 $ + * Date: $Date: 2002/12/16 09:04:34 $ + * Purpose: Private Network Management Interface Management Database + * + ****************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/***************************************************************************** + * + * History: + * + * $Log: skgemib.c,v $ + * Revision 1.7 2002/12/16 09:04:34 tschilli + * Code for VCT handling added. + * + * Revision 1.6 2002/08/09 15:40:21 rwahl + * Editorial change (renamed ConfSpeedCap). + * + * Revision 1.5 2002/08/09 11:05:34 rwahl + * Added oid handling for link speed cap. + * + * Revision 1.4 2002/08/09 09:40:27 rwahl + * Added support for NDIS OID_PNP_xxx. + * + * Revision 1.3 2002/07/17 19:39:54 rwahl + * Added handler for OID_SKGE_SPEED_MODE & OID_SKGE_SPEED_STATUS. + * + * Revision 1.2 2002/05/22 08:59:00 rwahl + * - static functions only for release build. + * - Source file must be included. + * + * Revision 1.1 2002/05/22 08:12:42 rwahl + * Initial version. + * + ****************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +/* + * PRIVATE OID handler function prototypes + */ +PNMI_STATIC int Addr(SK_AC *pAC, SK_IOC IoC, int action, + SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int CsumStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int General(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Mac8023Stat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int MacPrivateConf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int MacPrivateStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Monitor(SK_AC *pAC, SK_IOC IoC, int action, + SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int OidStruct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Perform(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int* pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Rlmt(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int RlmtStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int SensorStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Vpd(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); + +#ifdef SK_POWER_MGMT +PNMI_STATIC int PowerManagement(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +#endif + + +/* defines *******************************************************************/ +#define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0])) + + +/* global variables **********************************************************/ + +/* + * Table to correlate OID with handler function and index to + * hardware register stored in StatAddress if applicable. + */ +PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = { + {OID_GEN_XMIT_OK, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX}, + {OID_GEN_RCV_OK, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX}, + {OID_GEN_XMIT_ERROR, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_GEN_RCV_ERROR, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_GEN_RCV_NO_BUFFER, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_GEN_DIRECTED_FRAMES_XMIT, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNICAST}, + {OID_GEN_MULTICAST_FRAMES_XMIT, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTICAST}, + {OID_GEN_BROADCAST_FRAMES_XMIT, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_BROADCAST}, + {OID_GEN_DIRECTED_FRAMES_RCV, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_UNICAST}, + {OID_GEN_MULTICAST_FRAMES_RCV, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_MULTICAST}, + {OID_GEN_BROADCAST_FRAMES_RCV, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_BROADCAST}, + {OID_GEN_RCV_CRC_ERROR, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FCS}, + {OID_GEN_TRANSMIT_QUEUE_LENGTH, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_802_3_PERMANENT_ADDRESS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, 0}, + {OID_802_3_CURRENT_ADDRESS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, 0}, + {OID_802_3_RCV_ERROR_ALIGNMENT, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FRAMING}, + {OID_802_3_XMIT_ONE_COLLISION, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_SINGLE_COL}, + {OID_802_3_XMIT_MORE_COLLISIONS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTI_COL}, + {OID_802_3_XMIT_DEFERRED, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_DEFFERAL}, + {OID_802_3_XMIT_MAX_COLLISIONS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_EXCESS_COL}, + {OID_802_3_RCV_OVERRUN, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_OVERFLOW}, + {OID_802_3_XMIT_UNDERRUN, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNDERRUN}, + {OID_802_3_XMIT_TIMES_CRS_LOST, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_CARRIER}, + {OID_802_3_XMIT_LATE_COLLISIONS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_LATE_COL}, +#ifdef SK_POWER_MGMT + {OID_PNP_CAPABILITIES, + 0, + 0, + 0, + SK_PNMI_RO, PowerManagement, 0}, + {OID_PNP_SET_POWER, + 0, + 0, + 0, + SK_PNMI_WO, PowerManagement, 0}, + {OID_PNP_QUERY_POWER, + 0, + 0, + 0, + SK_PNMI_RO, PowerManagement, 0}, + {OID_PNP_ADD_WAKE_UP_PATTERN, + 0, + 0, + 0, + SK_PNMI_WO, PowerManagement, 0}, + {OID_PNP_REMOVE_WAKE_UP_PATTERN, + 0, + 0, + 0, + SK_PNMI_WO, PowerManagement, 0}, + {OID_PNP_ENABLE_WAKE_UP, + 0, + 0, + 0, + SK_PNMI_RW, PowerManagement, 0}, +#endif /* SK_POWER_MGMT */ + {OID_SKGE_MDB_VERSION, + 1, + 0, + SK_PNMI_MAI_OFF(MgmtDBVersion), + SK_PNMI_RO, General, 0}, + {OID_SKGE_SUPPORTED_LIST, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_SKGE_ALL_DATA, + 0, + 0, + 0, + SK_PNMI_RW, OidStruct, 0}, + {OID_SKGE_VPD_FREE_BYTES, + 1, + 0, + SK_PNMI_MAI_OFF(VpdFreeBytes), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_ENTRIES_LIST, + 1, + 0, + SK_PNMI_MAI_OFF(VpdEntriesList), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_ENTRIES_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(VpdEntriesNumber), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_KEY, + SK_PNMI_VPD_ENTRIES, + sizeof(SK_PNMI_VPD), + SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdKey), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_VALUE, + SK_PNMI_VPD_ENTRIES, + sizeof(SK_PNMI_VPD), + SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdValue), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_ACCESS, + SK_PNMI_VPD_ENTRIES, + sizeof(SK_PNMI_VPD), + SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAccess), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_ACTION, + SK_PNMI_VPD_ENTRIES, + sizeof(SK_PNMI_VPD), + SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAction), + SK_PNMI_RW, Vpd, 0}, + {OID_SKGE_PORT_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(PortNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_DEVICE_TYPE, + 1, + 0, + SK_PNMI_MAI_OFF(DeviceType), + SK_PNMI_RO, General, 0}, + {OID_SKGE_DRIVER_DESCR, + 1, + 0, + SK_PNMI_MAI_OFF(DriverDescr), + SK_PNMI_RO, General, 0}, + {OID_SKGE_DRIVER_VERSION, + 1, + 0, + SK_PNMI_MAI_OFF(DriverVersion), + SK_PNMI_RO, General, 0}, + {OID_SKGE_HW_DESCR, + 1, + 0, + SK_PNMI_MAI_OFF(HwDescr), + SK_PNMI_RO, General, 0}, + {OID_SKGE_HW_VERSION, + 1, + 0, + SK_PNMI_MAI_OFF(HwVersion), + SK_PNMI_RO, General, 0}, + {OID_SKGE_CHIPSET, + 1, + 0, + SK_PNMI_MAI_OFF(Chipset), + SK_PNMI_RO, General, 0}, + {OID_SKGE_ACTION, + 1, + 0, + SK_PNMI_MAI_OFF(Action), + SK_PNMI_RW, Perform, 0}, + {OID_SKGE_RESULT, + 1, + 0, + SK_PNMI_MAI_OFF(TestResult), + SK_PNMI_RO, General, 0}, + {OID_SKGE_BUS_TYPE, + 1, + 0, + SK_PNMI_MAI_OFF(BusType), + SK_PNMI_RO, General, 0}, + {OID_SKGE_BUS_SPEED, + 1, + 0, + SK_PNMI_MAI_OFF(BusSpeed), + SK_PNMI_RO, General, 0}, + {OID_SKGE_BUS_WIDTH, + 1, + 0, + SK_PNMI_MAI_OFF(BusWidth), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_SW_QUEUE_LEN, + 1, + 0, + SK_PNMI_MAI_OFF(TxSwQueueLen), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_SW_QUEUE_MAX, + 1, + 0, + SK_PNMI_MAI_OFF(TxSwQueueMax), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_RETRY, + 1, + 0, + SK_PNMI_MAI_OFF(TxRetryCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_INTR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxIntrCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_INTR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(TxIntrCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_NO_BUF_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxNoBufCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_NO_BUF_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(TxNoBufCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_USED_DESCR_NO, + 1, + 0, + SK_PNMI_MAI_OFF(TxUsedDescrNo), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_DELIVERED_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxDeliveredCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_OCTETS_DELIV_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxOctetsDeliveredCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_HW_ERROR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxHwErrorsCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_HW_ERROR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(TxHwErrorsCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_IN_ERRORS_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(InErrorsCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_OUT_ERROR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(OutErrorsCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_ERR_RECOVERY_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(ErrRecoveryCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_SYSUPTIME, + 1, + 0, + SK_PNMI_MAI_OFF(SysUpTime), + SK_PNMI_RO, General, 0}, + {OID_SKGE_SENSOR_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(SensorNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_SENSOR_INDEX, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorIndex), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_DESCR, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorDescr), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_TYPE, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorType), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_VALUE, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorValue), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_WAR_THRES_LOW, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdLow), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_WAR_THRES_UPP, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdHigh), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_ERR_THRES_LOW, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdLow), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_ERR_THRES_UPP, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdHigh), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_STATUS, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorStatus), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_WAR_CTS, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningCts), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_ERR_CTS, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorCts), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_WAR_TIME, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningTimestamp), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_ERR_TIME, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorTimestamp), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_CHKSM_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(ChecksumNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_CHKSM_RX_OK_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxOkCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_CHKSM_RX_UNABLE_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxUnableCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_CHKSM_RX_ERR_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxErrCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_CHKSM_TX_OK_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxOkCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_CHKSM_TX_UNABLE_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxUnableCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_STAT_TX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX}, + {OID_SKGE_STAT_TX_OCTETS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOctetsOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_OCTET}, + {OID_SKGE_STAT_TX_BROADCAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBroadcastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BROADCAST}, + {OID_SKGE_STAT_TX_MULTICAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMulticastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTICAST}, + {OID_SKGE_STAT_TX_UNICAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUnicastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNICAST}, + {OID_SKGE_STAT_TX_LONGFRAMES, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLongFramesCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LONGFRAMES}, + {OID_SKGE_STAT_TX_BURST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBurstCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BURST}, + {OID_SKGE_STAT_TX_PFLOWC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxPauseMacCtrlCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_PMACC}, + {OID_SKGE_STAT_TX_FLOWC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMacCtrlCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MACC}, + {OID_SKGE_STAT_TX_SINGLE_COL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSingleCollisionCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SINGLE_COL}, + {OID_SKGE_STAT_TX_MULTI_COL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMultipleCollisionCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTI_COL}, + {OID_SKGE_STAT_TX_EXCESS_COL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveCollisionCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_COL}, + {OID_SKGE_STAT_TX_LATE_COL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLateCollisionCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LATE_COL}, + {OID_SKGE_STAT_TX_DEFFERAL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxDeferralCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_DEFFERAL}, + {OID_SKGE_STAT_TX_EXCESS_DEF, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveDeferralCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_DEF}, + {OID_SKGE_STAT_TX_UNDERRUN, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxFifoUnderrunCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNDERRUN}, + {OID_SKGE_STAT_TX_CARRIER, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxCarrierCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_CARRIER}, +/* {OID_SKGE_STAT_TX_UTIL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUtilization), + SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */ + {OID_SKGE_STAT_TX_64, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx64Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_64}, + {OID_SKGE_STAT_TX_127, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx127Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_127}, + {OID_SKGE_STAT_TX_255, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx255Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_255}, + {OID_SKGE_STAT_TX_511, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx511Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_511}, + {OID_SKGE_STAT_TX_1023, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx1023Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_1023}, + {OID_SKGE_STAT_TX_MAX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMaxCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MAX}, + {OID_SKGE_STAT_TX_SYNC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC}, + {OID_SKGE_STAT_TX_SYNC_OCTETS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncOctetsCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC_OCTET}, + {OID_SKGE_STAT_RX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX}, + {OID_SKGE_STAT_RX_OCTETS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOctetsOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OCTET}, + {OID_SKGE_STAT_RX_BROADCAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBroadcastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BROADCAST}, + {OID_SKGE_STAT_RX_MULTICAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMulticastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MULTICAST}, + {OID_SKGE_STAT_RX_UNICAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUnicastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_UNICAST}, + {OID_SKGE_STAT_RX_LONGFRAMES, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxLongFramesCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_LONGFRAMES}, + {OID_SKGE_STAT_RX_PFLOWC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC}, + {OID_SKGE_STAT_RX_FLOWC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC}, + {OID_SKGE_STAT_RX_PFLOWC_ERR, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlErrorCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC_ERR}, + {OID_SKGE_STAT_RX_FLOWC_UNKWN, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlUnknownCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC_UNKWN}, + {OID_SKGE_STAT_RX_BURST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBurstCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BURST}, + {OID_SKGE_STAT_RX_MISSED, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMissedCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MISSED}, + {OID_SKGE_STAT_RX_FRAMING, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFramingCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FRAMING}, + {OID_SKGE_STAT_RX_OVERFLOW, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFifoOverflowCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OVERFLOW}, + {OID_SKGE_STAT_RX_JABBER, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxJabberCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_JABBER}, + {OID_SKGE_STAT_RX_CARRIER, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCarrierCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CARRIER}, + {OID_SKGE_STAT_RX_IR_LENGTH, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxIRLengthCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_IRLENGTH}, + {OID_SKGE_STAT_RX_SYMBOL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxSymbolCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SYMBOL}, + {OID_SKGE_STAT_RX_SHORTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxShortsCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SHORTS}, + {OID_SKGE_STAT_RX_RUNT, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxRuntCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_RUNT}, + {OID_SKGE_STAT_RX_CEXT, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCextCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CEXT}, + {OID_SKGE_STAT_RX_TOO_LONG, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxTooLongCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_TOO_LONG}, + {OID_SKGE_STAT_RX_FCS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFcsCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FCS}, +/* {OID_SKGE_STAT_RX_UTIL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUtilization), + SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */ + {OID_SKGE_STAT_RX_64, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx64Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_64}, + {OID_SKGE_STAT_RX_127, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx127Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_127}, + {OID_SKGE_STAT_RX_255, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx255Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_255}, + {OID_SKGE_STAT_RX_511, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx511Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_511}, + {OID_SKGE_STAT_RX_1023, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx1023Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_1023}, + {OID_SKGE_STAT_RX_MAX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMaxCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MAX}, + {OID_SKGE_PHYS_CUR_ADDR, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacCurrentAddr), + SK_PNMI_RW, Addr, 0}, + {OID_SKGE_PHYS_FAC_ADDR, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacFactoryAddr), + SK_PNMI_RO, Addr, 0}, + {OID_SKGE_PMD, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPMD), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_CONNECTOR, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfConnector), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_LINK_CAP, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkCapability), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_LINK_MODE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkMode), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_LINK_MODE_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkModeStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_LINK_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_FLOWCTRL_CAP, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlCapability), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_FLOWCTRL_MODE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlMode), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_FLOWCTRL_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_PHY_OPERATION_CAP, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationCapability), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_PHY_OPERATION_MODE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationMode), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_PHY_OPERATION_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_SPEED_CAP, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedCapability), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_SPEED_MODE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedMode), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_SPEED_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_TRAP, + 1, + 0, + SK_PNMI_MAI_OFF(Trap), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TRAP_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(TrapNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RLMT_MODE, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtMode), + SK_PNMI_RW, Rlmt, 0}, + {OID_SKGE_RLMT_PORT_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtPortNumber), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_PORT_ACTIVE, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtPortActive), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_PORT_PREFERRED, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtPortPreferred), + SK_PNMI_RW, Rlmt, 0}, + {OID_SKGE_RLMT_CHANGE_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtChangeCts), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_CHANGE_TIME, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtChangeTime), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_CHANGE_ESTIM, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtChangeEstimate), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_CHANGE_THRES, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtChangeThreshold), + SK_PNMI_RW, Rlmt, 0}, + {OID_SKGE_RLMT_PORT_INDEX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtIndex), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtStatus), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_TX_HELLO_CTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxHelloCts), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_RX_HELLO_CTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxHelloCts), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_TX_SP_REQ_CTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxSpHelloReqCts), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_RX_SP_CTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxSpHelloCts), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_MONITOR_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtMonitorNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RLMT_MONITOR_INDEX, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorIndex), + SK_PNMI_RO, Monitor, 0}, + {OID_SKGE_RLMT_MONITOR_ADDR, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAddr), + SK_PNMI_RO, Monitor, 0}, + {OID_SKGE_RLMT_MONITOR_ERRS, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorErrorCts), + SK_PNMI_RO, Monitor, 0}, + {OID_SKGE_RLMT_MONITOR_TIMESTAMP, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorTimestamp), + SK_PNMI_RO, Monitor, 0}, + {OID_SKGE_RLMT_MONITOR_ADMIN, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAdmin), + SK_PNMI_RW, Monitor, 0}, + {OID_SKGE_MTU, + 1, + 0, + SK_PNMI_MAI_OFF(MtuSize), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_VCT_GET, + 0, + 0, + 0, + SK_PNMI_RO, Vct, 0}, + {OID_SKGE_VCT_SET, + 0, + 0, + 0, + SK_PNMI_WO, Vct, 0}, + {OID_SKGE_VCT_STATUS, + 0, + 0, + 0, + SK_PNMI_RO, Vct, 0}, +}; + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skgepnmi.c b/drivers/sk98lin/skgepnmi.c new file mode 100644 index 0000000..b5d32b0 --- /dev/null +++ b/drivers/sk98lin/skgepnmi.c @@ -0,0 +1,8310 @@ +/***************************************************************************** + * + * Name: skgepnmi.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.102 $ + * Date: $Date: 2002/12/16 14:03:24 $ + * Purpose: Private Network Management Interface + * + ****************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/***************************************************************************** + * + * History: + * + * $Log: skgepnmi.c,v $ + * Revision 1.102 2002/12/16 14:03:24 tschilli + * VCT code in Vct() changed. + * + * Revision 1.101 2002/12/16 09:04:10 tschilli + * Code for VCT handling added. + * + * Revision 1.100 2002/09/26 14:28:13 tschilli + * For XMAC the values in the SK_PNMI_PORT Port struct are copied to + * the new SK_PNMI_PORT BufPort struct during a MacUpdate() call. + * These values are used when GetPhysStatVal() is called. With this + * mechanism you get the best results when software corrections for + * counters are needed. Example: RX_LONGFRAMES. + * + * Revision 1.99 2002/09/17 12:31:19 tschilli + * OID_SKGE_TX_HW_ERROR_CTS, OID_SKGE_OUT_ERROR_CTS, OID_GEN_XMIT_ERROR: + * Double count of SK_PNMI_HTX_EXCESS_COL in function General() removed. + * OID_PNP_CAPABILITIES: sizeof(SK_PM_WAKE_UP_CAPABILITIES) changed to + * sizeof(SK_PNP_CAPABILITIES) in function PowerManagement(). + * + * Revision 1.98 2002/09/10 09:00:03 rwahl + * Adapted boolean definitions according sktypes. + * + * Revision 1.97 2002/09/05 15:07:03 rwahl + * Editorial changes. + * + * Revision 1.96 2002/09/05 11:04:14 rwahl + * - Rx/Tx packets statistics of virtual port were zero on link down (#10750) + * - For GMAC the overflow IRQ for Rx longframe counter was not counted. + * - Incorrect calculation for oids OID_SKGE_RX_HW_ERROR_CTS, + * OID_SKGE_IN_ERRORS_CTS, OID_GEN_RCV_ERROR. + * - Moved correction for OID_SKGE_STAT_RX_TOO_LONG to GetPhysStatVal(). + * - Editorial changes. + * + * Revision 1.95 2002/09/04 08:53:37 rwahl + * - Incorrect statistics for Rx_too_long counter with jumbo frame (#10751) + * - StatRxFrameTooLong & StatRxPMaccErr counters were not reset. + * - Fixed compiler warning for debug msg arg types. + * + * Revision 1.94 2002/08/09 15:42:14 rwahl + * - Fixed StatAddr table for GMAC. + * - VirtualConf(): returned indeterminated status for speed oids if no + * active port. + * + * Revision 1.93 2002/08/09 11:04:59 rwahl + * Added handler for link speed caps. + * + * Revision 1.92 2002/08/09 09:43:03 rwahl + * - Added handler for NDIS OID_PNP_xxx ids. + * + * Revision 1.91 2002/07/17 19:53:03 rwahl + * - Added StatOvrflwBit table for XMAC & GMAC. + * - Extended StatAddr table for GMAC. Added check of number of counters + * in enumeration and size of StatAddr table on init level. + * - Added use of GIFunc table. + * - ChipSet is not static anymore, + * - Extended SIRQ event handler for both mac types. + * - Fixed rx short counter bug (#10620) + * - Added handler for oids SKGE_SPEED_MODE & SKGE_SPEED_STATUS. + * - Extendet GetPhysStatVal() for GMAC. + * - Editorial changes. + * + * Revision 1.90 2002/05/22 08:56:25 rwahl + * - Moved OID table to separate source file. + * - Fix: TX_DEFFERAL counter incremented in full-duplex mode. + * - Use string definitions for error msgs. + * + * Revision 1.89 2001/09/18 10:01:30 mkunz + * some OID's fixed for dualnetmode + * + * Revision 1.88 2001/08/02 07:58:08 rwahl + * - Fixed NetIndex to csum module at ResetCounter(). + * + * Revision 1.87 2001/04/06 13:35:09 mkunz + * -Bugs fixed in handling of OID_SKGE_MTU and the VPD OID's + * + * Revision 1.86 2001/03/09 09:18:03 mkunz + * Changes in SK_DBG_MSG + * + * Revision 1.85 2001/03/08 09:37:31 mkunz + * Bugfix in ResetCounter for Pnmi.Port structure + * + * Revision 1.84 2001/03/06 09:04:55 mkunz + * Made some changes in instance calculation + * + * Revision 1.83 2001/02/15 09:15:32 mkunz + * Necessary changes for dual net mode added + * + * Revision 1.82 2001/02/07 08:24:19 mkunz + * -Made changes in handling of OID_SKGE_MTU + * + * Revision 1.81 2001/02/06 09:58:00 mkunz + * -Vpd bug fixed + * -OID_SKGE_MTU added + * -pnmi support for dual net mode. Interface function and macros extended + * + * Revision 1.80 2001/01/22 13:41:35 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.79 2000/12/05 14:57:40 cgoos + * SetStruct failed before first Link Up (link mode of virtual + * port "INDETERMINATED"). + * + * Revision 1.78 2000/09/12 10:44:58 cgoos + * Fixed SK_PNMI_STORE_U32 calls with typecasted argument. + * + * Revision 1.77 2000/09/07 08:10:19 rwahl + * - Modified algorithm for 64bit NDIS statistic counters; + * returns 64bit or 32bit value depending on passed buffer + * size. Indicate capability for 64bit NDIS counter, if passed + * buffer size is zero. OID_GEN_XMIT_ERROR, OID_GEN_RCV_ERROR, + * and OID_GEN_RCV_NO_BUFFER handled as 64bit counter, too. + * - corrected OID_SKGE_RLMT_PORT_PREFERRED. + * + * Revision 1.76 2000/08/03 15:23:39 rwahl + * - Correction for FrameTooLong counter has to be moved to OID handling + * routines (instead of statistic counter routine). + * - Fix in XMAC Reset Event handling: Only offset counter for hardware + * statistic registers are updated. + * + * Revision 1.75 2000/08/01 16:46:05 rwahl + * - Added StatRxLongFrames counter and correction of FrameTooLong counter. + * - Added directive to control width (default = 32bit) of NDIS statistic + * counters (SK_NDIS_64BIT_CTR). + * + * Revision 1.74 2000/07/04 11:41:53 rwahl + * - Added volition connector type. + * + * Revision 1.73 2000/03/15 16:33:10 rwahl + * Fixed bug 10510; wrong reset of virtual port statistic counters. + * + * Revision 1.72 1999/12/06 16:15:53 rwahl + * Fixed problem of instance range for current and factory MAC address. + * + * Revision 1.71 1999/12/06 10:14:20 rwahl + * Fixed bug 10476; set operation for PHY_OPERATION_MODE. + * + * Revision 1.70 1999/11/22 13:33:34 cgoos + * Changed license header to GPL. + * + * Revision 1.69 1999/10/18 11:42:15 rwahl + * Added typecasts for checking event dependent param (debug only). + * + * Revision 1.68 1999/10/06 09:35:59 cgoos + * Added state check to PHY_READ call (hanged if called during startup). + * + * Revision 1.67 1999/09/22 09:53:20 rwahl + * - Read Broadcom register for updating fcs error counter (1000Base-T). + * + * Revision 1.66 1999/08/26 13:47:56 rwahl + * Added SK_DRIVER_SENDEVENT when queueing RLMT_CHANGE_THRES trap. + * + * Revision 1.65 1999/07/26 07:49:35 cgoos + * Added two typecasts to avoid compiler warnings. + * + * Revision 1.64 1999/05/20 09:24:12 cgoos + * Changes for 1000Base-T (sensors, Master/Slave). + * + * Revision 1.63 1999/04/13 15:11:58 mhaveman + * Moved include of rlmt.h to header skgepnmi.h because some macros + * are needed there. + * + * Revision 1.62 1999/04/13 15:08:07 mhaveman + * Replaced again SK_RLMT_CHECK_LINK with SK_PNMI_RLMT_MODE_CHK_LINK + * to grant unified interface by only using the PNMI header file. + * SK_PNMI_RLMT_MODE_CHK_LINK is defined the same as SK_RLMT_CHECK_LINK. + * + * Revision 1.61 1999/04/13 15:02:48 mhaveman + * Changes caused by review: + * -Changed some comments + * -Removed redundant check for OID_SKGE_PHYS_FAC_ADDR + * -Optimized PRESET check. + * -Meaning of error SK_ADDR_DUPLICATE_ADDRESS changed. Set of same + * address will now not cause this error. Removed corresponding check. + * + * Revision 1.60 1999/03/23 10:41:23 mhaveman + * Added comments. + * + * Revision 1.59 1999/02/19 08:01:28 mhaveman + * Fixed bug 10372 that after counter reset all ports were displayed + * as inactive. + * + * Revision 1.58 1999/02/16 18:04:47 mhaveman + * Fixed problem of twisted OIDs SENSOR_WAR_TIME and SENSOR_ERR_TIME. + * + * Revision 1.56 1999/01/27 12:29:11 mhaveman + * SkTimerStart was called with time value in milli seconds but needs + * micro seconds. + * + * Revision 1.55 1999/01/25 15:00:38 mhaveman + * Added support to allow multiple ports to be active. If this feature in + * future will be used, the Management Data Base variables PORT_ACTIVE + * and PORT_PREFERED should be moved to the port specific part of RLMT. + * Currently they return the values of the first active physical port + * found. A set to the virtual port will actually change all active + * physical ports. A get returns the melted values of all active physical + * ports. If the port values differ a return value INDETERMINATED will + * be returned. This effects especially the CONF group. + * + * Revision 1.54 1999/01/19 10:10:22 mhaveman + * -Fixed bug 10354: Counter values of virtual port were wrong after port + * switches + * -Added check if a switch to the same port is notified. + * + * Revision 1.53 1999/01/07 09:25:21 mhaveman + * Forgot to initialize a variable. + * + * Revision 1.52 1999/01/05 10:34:33 mhaveman + * Fixed little error in RlmtChangeEstimate calculation. + * + * Revision 1.51 1999/01/05 09:59:07 mhaveman + * -Moved timer start to init level 2 + * -Redesigned port switch average calculation to avoid 64bit + * arithmetic. + * + * Revision 1.50 1998/12/10 15:13:59 mhaveman + * -Fixed: PHYS_CUR_ADDR returned wrong addresses + * -Fixed: RLMT_PORT_PREFERED and RLMT_CHANGE_THRES preset returned + * always BAD_VALUE. + * -Fixed: TRAP buffer seemed to sometimes suddenly empty + * + * Revision 1.49 1998/12/09 16:17:07 mhaveman + * Fixed: Couldnot delete VPD keys on UNIX. + * + * Revision 1.48 1998/12/09 14:11:10 mhaveman + * -Add: Debugmessage for XMAC_RESET supressed to minimize output. + * -Fixed: RlmtChangeThreshold will now be initialized. + * -Fixed: VPD_ENTRIES_LIST extended value with unnecessary space char. + * -Fixed: On VPD key creation an invalid key name could be created + * (e.g. A5) + * -Some minor changes in comments and code. + * + * Revision 1.47 1998/12/08 16:00:31 mhaveman + * -Fixed: For RLMT_PORT_ACTIVE will now be returned a 0 if no port + * is active. + * -Fixed: For the RLMT statistics group only the last value was + * returned and the rest of the buffer was filled with 0xff + * -Fixed: Mysteriously the preset on RLMT_MODE still returned + * BAD_VALUE. + * Revision 1.46 1998/12/08 10:04:56 mhaveman + * -Fixed: Preset on RLMT_MODE returned always BAD_VALUE error. + * -Fixed: Alignment error in GetStruct + * -Fixed: If for Get/Preset/SetStruct the buffer size is equal or + * larger than SK_PNMI_MIN_STRUCT_SIZE the return value is stored + * to the buffer. In this case the caller should always return + * ok to its upper routines. Only if the buffer size is less + * than SK_PNMI_MIN_STRUCT_SIZE and the return value is unequal + * to 0, an error should be returned by the caller. + * -Fixed: Wrong number of instances with RLMT statistic. + * -Fixed: Return now SK_LMODE_STAT_UNKNOWN if the LinkModeStatus is 0. + * + * Revision 1.45 1998/12/03 17:17:24 mhaveman + * -Removed for VPD create action the buffer size limitation to 4 bytes. + * -Pass now physical/active physical port to ADDR for CUR_ADDR set + * + * Revision 1.44 1998/12/03 15:14:35 mhaveman + * Another change to Vpd instance evaluation. + * + * Revision 1.43 1998/12/03 14:18:10 mhaveman + * -Fixed problem in PnmiSetStruct. It was impossible to set any value. + * -Removed VPD key evaluation for VPD_FREE_BYTES and VPD_ACTION. + * + * Revision 1.42 1998/12/03 11:31:47 mhaveman + * Inserted cast to satisfy lint. + * + * Revision 1.41 1998/12/03 11:28:16 mhaveman + * Removed SK_PNMI_CHECKPTR + * + * Revision 1.40 1998/12/03 11:19:07 mhaveman + * Fixed problems + * -A set to virtual port will now be ignored. A set with broadcast + * address to any port will be ignored. + * -GetStruct function made VPD instance calculation wrong. + * -Prefered port returned -1 instead of 0. + * + * Revision 1.39 1998/11/26 15:30:29 mhaveman + * Added sense mode to link mode. + * + * Revision 1.38 1998/11/23 15:34:00 mhaveman + * -Fixed bug for RX counters. On an RX overflow interrupt the high + * words of all RX counters were incremented. + * -SET operations on FLOWCTRL_MODE and LINK_MODE accept now the + * value 0, which has no effect. It is usefull for multiple instance + * SETs. + * + * Revision 1.37 1998/11/20 08:02:04 mhaveman + * -Fixed: Ports were compared with MAX_SENSORS + * -Fixed: Crash in GetTrapEntry with MEMSET macro + * -Fixed: Conversions between physical, logical port index and instance + * + * Revision 1.36 1998/11/16 07:48:53 mhaveman + * Casted SK_DRIVER_SENDEVENT with (void) to eleminate compiler warnings + * on Solaris. + * + * Revision 1.35 1998/11/16 07:45:34 mhaveman + * SkAddrOverride now returns value and will be checked. + * + * Revision 1.34 1998/11/10 13:40:37 mhaveman + * Needed to change interface, because NT driver needs a return value + * of needed buffer space on TOO_SHORT errors. Therefore all + * SkPnmiGet/Preset/Set functions now have a pointer to the length + * parameter, where the needed space on error is returned. + * + * Revision 1.33 1998/11/03 13:52:46 mhaveman + * Made file lint conform. + * + * Revision 1.32 1998/11/03 13:19:07 mhaveman + * The events SK_HWEV_SET_LMODE and SK_HWEV_SET_FLOWMODE pass now in + * Para32[0] the physical MAC index and in Para32[1] the new mode. + * + * Revision 1.31 1998/11/03 12:30:40 gklug + * fix: compiler warning memset + * + * Revision 1.30 1998/11/03 12:04:46 mhaveman + * Fixed problem in SENSOR_VALUE, which wrote beyond the buffer end + * Fixed alignment problem with CHIPSET. + * + * Revision 1.29 1998/11/02 11:23:54 mhaveman + * Corrected SK_ERROR_LOG to SK_ERR_LOG. Sorry. + * + * Revision 1.28 1998/11/02 10:47:16 mhaveman + * Added syslog messages for internal errors. + * + * Revision 1.27 1998/10/30 15:48:06 mhaveman + * Fixed problems after simulation of SK_PNMI_EVT_CHG_EST_TIMER and + * RlmtChangeThreshold calculation. + * + * Revision 1.26 1998/10/29 15:36:55 mhaveman + * -Fixed bug in trap buffer handling. + * -OID_SKGE_DRIVER_DESCR, OID_SKGE_DRIVER_VERSION, OID_SKGE_HW_DESCR, + * OID_SKGE_HW_VERSION, OID_SKGE_VPD_ENTRIES_LIST, OID_SKGE_VPD_KEY, + * OID_SKGE_VPD_VALUE, and OID_SKGE_SENSOR_DESCR return values with + * a leading octet before each string storing the string length. + * -Perform a RlmtUpdate during SK_PNMI_EVT_XMAC_RESET to minimize + * RlmtUpdate calls in GetStatVal. + * -Inserted SK_PNMI_CHECKFLAGS macro increase readability. + * + * Revision 1.25 1998/10/29 08:50:36 mhaveman + * Fixed problems after second event simulation. + * + * Revision 1.24 1998/10/28 08:44:37 mhaveman + * -Fixed alignment problem + * -Fixed problems during event simulation + * -Fixed sequence of error return code (INSTANCE -> ACCESS -> SHORT) + * -Changed type of parameter Instance back to SK_U32 because of VPD + * -Updated new VPD function calls + * + * Revision 1.23 1998/10/23 10:16:37 mhaveman + * Fixed bugs after buffer test simulation. + * + * Revision 1.22 1998/10/21 13:23:52 mhaveman + * -Call syntax of SkOsGetTime() changed to SkOsGetTime(pAc). + * -Changed calculation of hundrets of seconds. + * + * Revision 1.20 1998/10/20 07:30:45 mhaveman + * Made type changes to unsigned integer where possible. + * + * Revision 1.19 1998/10/19 10:51:30 mhaveman + * -Made Bug fixes after simulation run + * -Renamed RlmtMAC... to RlmtPort... + * -Marked workarounds with Errata comments + * + * Revision 1.18 1998/10/14 07:50:08 mhaveman + * -For OID_SKGE_LINK_STATUS the link down detection has moved from RLMT + * to HWACCESS. + * -Provided all MEMCPY/MEMSET macros with (char *) pointers, because + * Solaris throwed warnings when mapping to bcopy/bset. + * + * Revision 1.17 1998/10/13 07:42:01 mhaveman + * -Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA + * -Removed old cvs history entries + * -Renamed MacNumber to PortNumber + * + * Revision 1.16 1998/10/07 10:52:49 mhaveman + * -Inserted handling of some OID_GEN_ Ids for windows + * -Fixed problem with 803.2 statistic. + * + * Revision 1.15 1998/10/01 09:16:29 mhaveman + * Added Debug messages for function call and UpdateFlag tracing. + * + * Revision 1.14 1998/09/30 13:39:09 mhaveman + * -Reduced namings of 'MAC' by replacing them with 'PORT'. + * -Completed counting of OID_SKGE_RX_HW_ERROR_CTS, + * OID_SKGE_TX_HW_ERROR_CTS, + * OID_SKGE_IN_ERRORS_CTS, and OID_SKGE_OUT_ERROR_CTS. + * -SET check for RlmtMode + * + * Revision 1.13 1998/09/28 13:13:08 mhaveman + * Hide strcmp, strlen, and strncpy behind macros SK_STRCMP, SK_STRLEN, + * and SK_STRNCPY. (Same reasons as for mem.. and MEM..) + * + * Revision 1.12 1998/09/16 08:18:36 cgoos + * Fix: XM_INxx and XM_OUTxx called with different parameter order: + * sometimes IoC,Mac,... sometimes Mac,IoC,... Now always first variant. + * Fix: inserted "Pnmi." into some pAC->pDriverDescription / Version. + * Change: memset, memcpy to makros SK_MEMSET, SK_MEMCPY + * + * Revision 1.11 1998/09/04 17:01:45 mhaveman + * Added SyncCounter as macro and OID_SKGE_.._NO_DESCR_CTS to + * OID_SKGE_RX_NO_BUF_CTS. + * + * Revision 1.10 1998/09/04 14:35:35 mhaveman + * Added macro counters, that are counted by driver. + * + ****************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +static const char SysKonnectFileId[] = + "@(#) $Id: skgepnmi.c,v 1.102 2002/12/16 14:03:24 tschilli Exp $" + " (C) SysKonnect."; + +#include "h/skdrv1st.h" +#include "h/sktypes.h" +#include "h/xmac_ii.h" +#include "h/skdebug.h" +#include "h/skqueue.h" +#include "h/skgepnmi.h" +#include "h/skgesirq.h" +#include "h/skcsum.h" +#include "h/skvpd.h" +#include "h/skgehw.h" +#include "h/skgeinit.h" +#include "h/skdrv2nd.h" +#include "h/skgepnm2.h" +#ifdef SK_POWER_MGMT +#include "h/skgepmgt.h" +#endif +/* defines *******************************************************************/ + +#ifndef DEBUG +#define PNMI_STATIC static +#else /* DEBUG */ +#define PNMI_STATIC +#endif /* DEBUG */ + +/* + * Public Function prototypes + */ +int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int level); +int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf, + unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf, + unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf, + unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, + unsigned int *pLen, SK_U32 NetIndex); +int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, + unsigned int *pLen, SK_U32 NetIndex); +int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, + unsigned int *pLen, SK_U32 NetIndex); +int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param); + + +/* + * Private Function prototypes + */ + +PNMI_STATIC SK_U8 CalculateLinkModeStatus(SK_AC *pAC, SK_IOC IoC, unsigned int + PhysPortIndex); +PNMI_STATIC SK_U8 CalculateLinkStatus(SK_AC *pAC, SK_IOC IoC, unsigned int + PhysPortIndex); +PNMI_STATIC void CopyMac(char *pDst, SK_MAC_ADDR *pMac); +PNMI_STATIC void CopyTrapQueue(SK_AC *pAC, char *pDstBuf); +PNMI_STATIC SK_U64 GetPhysStatVal(SK_AC *pAC, SK_IOC IoC, + unsigned int PhysPortIndex, unsigned int StatIndex); +PNMI_STATIC SK_U64 GetStatVal(SK_AC *pAC, SK_IOC IoC, unsigned int LogPortIndex, + unsigned int StatIndex, SK_U32 NetIndex); +PNMI_STATIC char* GetTrapEntry(SK_AC *pAC, SK_U32 TrapId, unsigned int Size); +PNMI_STATIC void GetTrapQueueLen(SK_AC *pAC, unsigned int *pLen, + unsigned int *pEntries); +PNMI_STATIC int GetVpdKeyArr(SK_AC *pAC, SK_IOC IoC, char *pKeyArr, + unsigned int KeyArrLen, unsigned int *pKeyNo); +PNMI_STATIC int LookupId(SK_U32 Id); +PNMI_STATIC int MacUpdate(SK_AC *pAC, SK_IOC IoC, unsigned int FirstMac, + unsigned int LastMac); +PNMI_STATIC int PnmiStruct(SK_AC *pAC, SK_IOC IoC, int Action, char *pBuf, + unsigned int *pLen, SK_U32 NetIndex); +PNMI_STATIC int PnmiVar(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +PNMI_STATIC void QueueRlmtNewMacTrap(SK_AC *pAC, unsigned int ActiveMac); +PNMI_STATIC void QueueRlmtPortTrap(SK_AC *pAC, SK_U32 TrapId, + unsigned int PortIndex); +PNMI_STATIC void QueueSensorTrap(SK_AC *pAC, SK_U32 TrapId, + unsigned int SensorIndex); +PNMI_STATIC void QueueSimpleTrap(SK_AC *pAC, SK_U32 TrapId); +PNMI_STATIC void ResetCounter(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex); +PNMI_STATIC int RlmtUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex); +PNMI_STATIC int SirqUpdate(SK_AC *pAC, SK_IOC IoC); +PNMI_STATIC void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf); +PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, char *pBuf, + unsigned int *pLen, SK_U32 Instance, unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32); + +/* + * Table to correlate OID with handler function and index to + * hardware register stored in StatAddress if applicable. + */ +#include "skgemib.c" + +/* global variables **********************************************************/ + +/* + * Overflow status register bit table and corresponding counter + * dependent on MAC type - the number relates to the size of overflow + * mask returned by the pFnMacOverflow function + */ +PNMI_STATIC const SK_U16 StatOvrflwBit[][SK_PNMI_MAC_TYPES] = { +/* Bit0 */ { SK_PNMI_HTX, SK_PNMI_HTX_UNICAST}, +/* Bit1 */ { SK_PNMI_HTX_OCTETHIGH, SK_PNMI_HTX_BROADCAST}, +/* Bit2 */ { SK_PNMI_HTX_OCTETLOW, SK_PNMI_HTX_PMACC}, +/* Bit3 */ { SK_PNMI_HTX_BROADCAST, SK_PNMI_HTX_MULTICAST}, +/* Bit4 */ { SK_PNMI_HTX_MULTICAST, SK_PNMI_HTX_OCTETLOW}, +/* Bit5 */ { SK_PNMI_HTX_UNICAST, SK_PNMI_HTX_OCTETHIGH}, +/* Bit6 */ { SK_PNMI_HTX_LONGFRAMES, SK_PNMI_HTX_64}, +/* Bit7 */ { SK_PNMI_HTX_BURST, SK_PNMI_HTX_127}, +/* Bit8 */ { SK_PNMI_HTX_PMACC, SK_PNMI_HTX_255}, +/* Bit9 */ { SK_PNMI_HTX_MACC, SK_PNMI_HTX_511}, +/* Bit10 */ { SK_PNMI_HTX_SINGLE_COL, SK_PNMI_HTX_1023}, +/* Bit11 */ { SK_PNMI_HTX_MULTI_COL, SK_PNMI_HTX_MAX}, +/* Bit12 */ { SK_PNMI_HTX_EXCESS_COL, SK_PNMI_HTX_LONGFRAMES}, +/* Bit13 */ { SK_PNMI_HTX_LATE_COL, SK_PNMI_HTX_RESERVED}, +/* Bit14 */ { SK_PNMI_HTX_DEFFERAL, SK_PNMI_HTX_COL}, +/* Bit15 */ { SK_PNMI_HTX_EXCESS_DEF, SK_PNMI_HTX_LATE_COL}, +/* Bit16 */ { SK_PNMI_HTX_UNDERRUN, SK_PNMI_HTX_EXCESS_COL}, +/* Bit17 */ { SK_PNMI_HTX_CARRIER, SK_PNMI_HTX_MULTI_COL}, +/* Bit18 */ { SK_PNMI_HTX_UTILUNDER, SK_PNMI_HTX_SINGLE_COL}, +/* Bit19 */ { SK_PNMI_HTX_UTILOVER, SK_PNMI_HTX_UNDERRUN}, +/* Bit20 */ { SK_PNMI_HTX_64, SK_PNMI_HTX_RESERVED}, +/* Bit21 */ { SK_PNMI_HTX_127, SK_PNMI_HTX_RESERVED}, +/* Bit22 */ { SK_PNMI_HTX_255, SK_PNMI_HTX_RESERVED}, +/* Bit23 */ { SK_PNMI_HTX_511, SK_PNMI_HTX_RESERVED}, +/* Bit24 */ { SK_PNMI_HTX_1023, SK_PNMI_HTX_RESERVED}, +/* Bit25 */ { SK_PNMI_HTX_MAX, SK_PNMI_HTX_RESERVED}, +/* Bit26 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit27 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit28 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit29 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit30 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit31 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit32 */ { SK_PNMI_HRX, SK_PNMI_HRX_UNICAST}, +/* Bit33 */ { SK_PNMI_HRX_OCTETHIGH, SK_PNMI_HRX_BROADCAST}, +/* Bit34 */ { SK_PNMI_HRX_OCTETLOW, SK_PNMI_HRX_PMACC}, +/* Bit35 */ { SK_PNMI_HRX_BROADCAST, SK_PNMI_HRX_MULTICAST}, +/* Bit36 */ { SK_PNMI_HRX_MULTICAST, SK_PNMI_HRX_FCS}, +/* Bit37 */ { SK_PNMI_HRX_UNICAST, SK_PNMI_HRX_RESERVED}, +/* Bit38 */ { SK_PNMI_HRX_PMACC, SK_PNMI_HRX_OCTETLOW}, +/* Bit39 */ { SK_PNMI_HRX_MACC, SK_PNMI_HRX_OCTETHIGH}, +/* Bit40 */ { SK_PNMI_HRX_PMACC_ERR, SK_PNMI_HRX_BADOCTETLOW}, +/* Bit41 */ { SK_PNMI_HRX_MACC_UNKWN, SK_PNMI_HRX_BADOCTETHIGH}, +/* Bit42 */ { SK_PNMI_HRX_BURST, SK_PNMI_HRX_UNDERSIZE}, +/* Bit43 */ { SK_PNMI_HRX_MISSED, SK_PNMI_HRX_RUNT}, +/* Bit44 */ { SK_PNMI_HRX_FRAMING, SK_PNMI_HRX_64}, +/* Bit45 */ { SK_PNMI_HRX_OVERFLOW, SK_PNMI_HRX_127}, +/* Bit46 */ { SK_PNMI_HRX_JABBER, SK_PNMI_HRX_255}, +/* Bit47 */ { SK_PNMI_HRX_CARRIER, SK_PNMI_HRX_511}, +/* Bit48 */ { SK_PNMI_HRX_IRLENGTH, SK_PNMI_HRX_1023}, +/* Bit49 */ { SK_PNMI_HRX_SYMBOL, SK_PNMI_HRX_MAX}, +/* Bit50 */ { SK_PNMI_HRX_SHORTS, SK_PNMI_HRX_LONGFRAMES}, +/* Bit51 */ { SK_PNMI_HRX_RUNT, SK_PNMI_HRX_TOO_LONG}, +/* Bit52 */ { SK_PNMI_HRX_TOO_LONG, SK_PNMI_HRX_JABBER}, +/* Bit53 */ { SK_PNMI_HRX_FCS, SK_PNMI_HRX_RESERVED}, +/* Bit54 */ { SK_PNMI_HRX_RESERVED, SK_PNMI_HRX_OVERFLOW}, +/* Bit55 */ { SK_PNMI_HRX_CEXT, SK_PNMI_HRX_RESERVED}, +/* Bit56 */ { SK_PNMI_HRX_UTILUNDER, SK_PNMI_HRX_RESERVED}, +/* Bit57 */ { SK_PNMI_HRX_UTILOVER, SK_PNMI_HRX_RESERVED}, +/* Bit58 */ { SK_PNMI_HRX_64, SK_PNMI_HRX_RESERVED}, +/* Bit59 */ { SK_PNMI_HRX_127, SK_PNMI_HRX_RESERVED}, +/* Bit60 */ { SK_PNMI_HRX_255, SK_PNMI_HRX_RESERVED}, +/* Bit61 */ { SK_PNMI_HRX_511, SK_PNMI_HRX_RESERVED}, +/* Bit62 */ { SK_PNMI_HRX_1023, SK_PNMI_HRX_RESERVED}, +/* Bit63 */ { SK_PNMI_HRX_MAX, SK_PNMI_HRX_RESERVED} +}; + +/* + * Table for hardware register saving on resets and port switches + */ +PNMI_STATIC const SK_PNMI_STATADDR StatAddr[SK_PNMI_MAX_IDX][SK_PNMI_MAC_TYPES] = { + /* SK_PNMI_HTX */ + {{XM_TXF_OK, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_OCTETHIGH */ + {{XM_TXO_OK_HI, SK_TRUE}, {GM_TXO_OK_HI, SK_TRUE}}, + /* SK_PNMI_HTX_OCTETLOW */ + {{XM_TXO_OK_LO, SK_FALSE}, {GM_TXO_OK_LO, SK_FALSE}}, + /* SK_PNMI_HTX_BROADCAST */ + {{XM_TXF_BC_OK, SK_TRUE}, {GM_TXF_BC_OK, SK_TRUE}}, + /* SK_PNMI_HTX_MULTICAST */ + {{XM_TXF_MC_OK, SK_TRUE}, {GM_TXF_MC_OK, SK_TRUE}}, + /* SK_PNMI_HTX_UNICAST */ + {{XM_TXF_UC_OK, SK_TRUE}, {GM_TXF_UC_OK, SK_TRUE}}, + /* SK_PNMI_HTX_BURST */ + {{XM_TXE_BURST, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_PMACC */ + {{XM_TXF_MPAUSE, SK_TRUE}, {GM_TXF_MPAUSE, SK_TRUE}}, + /* SK_PNMI_HTX_MACC */ + {{XM_TXF_MCTRL, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_COL */ + {{0, SK_FALSE}, {GM_TXF_COL, SK_TRUE}}, + /* SK_PNMI_HTX_SINGLE_COL */ + {{XM_TXF_SNG_COL, SK_TRUE}, {GM_TXF_SNG_COL, SK_TRUE}}, + /* SK_PNMI_HTX_MULTI_COL */ + {{XM_TXF_MUL_COL, SK_TRUE}, {GM_TXF_MUL_COL, SK_TRUE}}, + /* SK_PNMI_HTX_EXCESS_COL */ + {{XM_TXF_ABO_COL, SK_TRUE}, {GM_TXF_ABO_COL, SK_TRUE}}, + /* SK_PNMI_HTX_LATE_COL */ + {{XM_TXF_LAT_COL, SK_TRUE}, {GM_TXF_LAT_COL, SK_TRUE}}, + /* SK_PNMI_HTX_DEFFERAL */ + {{XM_TXF_DEF, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_EXCESS_DEF */ + {{XM_TXF_EX_DEF, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_UNDERRUN */ + {{XM_TXE_FIFO_UR, SK_TRUE}, {GM_TXE_FIFO_UR, SK_TRUE}}, + /* SK_PNMI_HTX_CARRIER */ + {{XM_TXE_CS_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_UTILUNDER */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_UTILOVER */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_64 */ + {{XM_TXF_64B, SK_TRUE}, {GM_TXF_64B, SK_TRUE}}, + /* SK_PNMI_HTX_127 */ + {{XM_TXF_127B, SK_TRUE}, {GM_TXF_127B, SK_TRUE}}, + /* SK_PNMI_HTX_255 */ + {{XM_TXF_255B, SK_TRUE}, {GM_TXF_255B, SK_TRUE}}, + /* SK_PNMI_HTX_511 */ + {{XM_TXF_511B, SK_TRUE}, {GM_TXF_511B, SK_TRUE}}, + /* SK_PNMI_HTX_1023 */ + {{XM_TXF_1023B, SK_TRUE}, {GM_TXF_1023B, SK_TRUE}}, + /* SK_PNMI_HTX_MAX */ + {{XM_TXF_MAX_SZ, SK_TRUE}, {GM_TXF_1518B, SK_TRUE}}, + /* SK_PNMI_HTX_LONGFRAMES */ + {{XM_TXF_LONG, SK_TRUE}, {GM_TXF_MAX_SZ, SK_TRUE}}, + /* SK_PNMI_HTX_SYNC */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_SYNC_OCTET */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_RESERVED */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX */ + {{XM_RXF_OK, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_OCTETHIGH */ + {{XM_RXO_OK_HI, SK_TRUE}, {GM_RXO_OK_HI, SK_TRUE}}, + /* SK_PNMI_HRX_OCTETLOW */ + {{XM_RXO_OK_LO, SK_FALSE}, {GM_RXO_OK_LO, SK_FALSE}}, + /* SK_PNMI_HRX_BADOCTETHIGH */ + {{0, SK_FALSE}, {GM_RXO_ERR_HI, SK_TRUE}}, + /* SK_PNMI_HRX_BADOCTETLOW */ + {{0, SK_FALSE}, {GM_RXO_ERR_LO, SK_TRUE}}, + /* SK_PNMI_HRX_BROADCAST */ + {{XM_RXF_BC_OK, SK_TRUE}, {GM_RXF_BC_OK, SK_TRUE}}, + /* SK_PNMI_HRX_MULTICAST */ + {{XM_RXF_MC_OK, SK_TRUE}, {GM_RXF_MC_OK, SK_TRUE}}, + /* SK_PNMI_HRX_UNICAST */ + {{XM_RXF_UC_OK, SK_TRUE}, {GM_RXF_UC_OK, SK_TRUE}}, + /* SK_PNMI_HRX_PMACC */ + {{XM_RXF_MPAUSE, SK_TRUE}, {GM_RXF_MPAUSE, SK_TRUE}}, + /* SK_PNMI_HRX_MACC */ + {{XM_RXF_MCTRL, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_PMACC_ERR */ + {{XM_RXF_INV_MP, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_MACC_UNKWN */ + {{XM_RXF_INV_MOC, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_BURST */ + {{XM_RXE_BURST, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_MISSED */ + {{XM_RXE_FMISS, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_FRAMING */ + {{XM_RXF_FRA_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_UNDERSIZE */ + {{0, SK_FALSE},{GM_RXF_SHT, SK_TRUE}}, + /* SK_PNMI_HRX_OVERFLOW */ + {{XM_RXE_FIFO_OV, SK_TRUE}, {GM_RXE_FIFO_OV, SK_TRUE}}, + /* SK_PNMI_HRX_JABBER */ + {{XM_RXF_JAB_PKT, SK_TRUE}, {GM_RXF_JAB_PKT, SK_TRUE}}, + /* SK_PNMI_HRX_CARRIER */ + {{XM_RXE_CAR_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_IRLENGTH */ + {{XM_RXF_LEN_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_SYMBOL */ + {{XM_RXE_SYM_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_SHORTS */ + {{XM_RXE_SHT_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_RUNT */ + {{XM_RXE_RUNT, SK_TRUE}, {GM_RXE_FRAG, SK_TRUE}}, + /* SK_PNMI_HRX_TOO_LONG */ + {{XM_RXF_LNG_ERR, SK_TRUE}, {GM_RXF_LNG_ERR, SK_TRUE}}, + /* SK_PNMI_HRX_FCS */ + {{XM_RXF_FCS_ERR, SK_TRUE}, {GM_RXF_FCS_ERR, SK_TRUE}}, + /* SK_PNMI_HRX_CEXT */ + {{XM_RXF_CEX_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_UTILUNDER */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_UTILOVER */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_64 */ + {{XM_RXF_64B, SK_TRUE}, {GM_RXF_64B, SK_TRUE}}, + /* SK_PNMI_HRX_127 */ + {{XM_RXF_127B, SK_TRUE}, {GM_RXF_127B, SK_TRUE}}, + /* SK_PNMI_HRX_255 */ + {{XM_RXF_255B, SK_TRUE}, {GM_RXF_255B, SK_TRUE}}, + /* SK_PNMI_HRX_511 */ + {{XM_RXF_511B, SK_TRUE}, {GM_RXF_511B, SK_TRUE}}, + /* SK_PNMI_HRX_1023 */ + {{XM_RXF_1023B, SK_TRUE}, {GM_RXF_1023B, SK_TRUE}}, + /* SK_PNMI_HRX_MAX */ + {{XM_RXF_MAX_SZ, SK_TRUE}, {GM_RXF_1518B, SK_TRUE}}, + /* SK_PNMI_HRX_LONGFRAMES */ + {{0, SK_FALSE}, {GM_RXF_MAX_SZ, SK_TRUE}}, + /* SK_PNMI_HRX_RESERVED */ + {{0, SK_FALSE}, {0, SK_FALSE}} +}; + + +/***************************************************************************** + * + * Public functions + * + */ + +/***************************************************************************** + * + * SkPnmiInit - Init function of PNMI + * + * Description: + * SK_INIT_DATA: Initialises the data structures + * SK_INIT_IO: Resets the XMAC statistics, determines the device and + * connector type. + * SK_INIT_RUN: Starts a timer event for port switch per hour + * calculation. + * + * Returns: + * Always 0 + */ +int SkPnmiInit( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Level) /* Initialization level */ +{ + unsigned int PortMax; /* Number of ports */ + unsigned int PortIndex; /* Current port index in loop */ + SK_U16 Val16; /* Multiple purpose 16 bit variable */ + SK_U8 Val8; /* Mulitple purpose 8 bit variable */ + SK_EVPARA EventParam; /* Event struct for timer event */ + SK_GEPORT *pPrt; + SK_PNMI_VCT *pVctBackupData; + + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiInit: Called, level=%d\n", Level)); + + switch (Level) { + + case SK_INIT_DATA: + SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi)); + pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN; + pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); + pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES; + for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) { + + pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE; + pAC->Pnmi.DualNetActiveFlag = SK_FALSE; + } + +#ifdef SK_PNMI_CHECK + if (SK_PNMI_MAX_IDX != SK_PNMI_CNT_NO) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR049, SK_PNMI_ERR049MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL, + ("CounterOffset struct size (%d) differs from" + "SK_PNMI_MAX_IDX (%d)\n", + SK_PNMI_CNT_NO, SK_PNMI_MAX_IDX)); + BRK; + } + + if (SK_PNMI_MAX_IDX != + (sizeof(StatAddr) / (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES))) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR050, SK_PNMI_ERR050MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL, + ("StatAddr table size (%d) differs from " + "SK_PNMI_MAX_IDX (%d)\n", + (sizeof(StatAddr) / + (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES)), + SK_PNMI_MAX_IDX)); + BRK; + } +#endif /* SK_PNMI_CHECK */ + break; + + case SK_INIT_IO: + /* + * Reset MAC counters + */ + PortMax = pAC->GIni.GIMacsFound; + + for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) { + + pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex); + } + + /* Initialize DSP variables for Vct() to 0xff => Never written! */ + for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) { + pPrt = &pAC->GIni.GP[PortIndex]; + pPrt->PCableLen =0xff; + pVctBackupData = &pAC->Pnmi.VctBackup[PortIndex]; + pVctBackupData->PCableLen = 0xff; + } + + /* + * Get pci bus speed + */ + SK_IN16(IoC, B0_CTST, &Val16); + if ((Val16 & CS_BUS_CLOCK) == 0) { + + pAC->Pnmi.PciBusSpeed = 33; + } + else { + pAC->Pnmi.PciBusSpeed = 66; + } + + /* + * Get pci bus width + */ + SK_IN16(IoC, B0_CTST, &Val16); + if ((Val16 & CS_BUS_SLOT_SZ) == 0) { + + pAC->Pnmi.PciBusWidth = 32; + } + else { + pAC->Pnmi.PciBusWidth = 64; + } + + /* + * Get chipset + */ + switch (pAC->GIni.GIChipId) { + case CHIP_ID_GENESIS: + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_XMAC; + break; + + case CHIP_ID_YUKON: + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON; + break; + + default: + break; + } + + /* + * Get PMD and DeviceType + */ + SK_IN8(IoC, B2_PMD_TYP, &Val8); + switch (Val8) { + case 'S': + pAC->Pnmi.PMD = 3; + if (pAC->GIni.GIMacsFound > 1) { + + pAC->Pnmi.DeviceType = 0x00020002; + } + else { + pAC->Pnmi.DeviceType = 0x00020001; + } + break; + + case 'L': + pAC->Pnmi.PMD = 2; + if (pAC->GIni.GIMacsFound > 1) { + + pAC->Pnmi.DeviceType = 0x00020004; + } + else { + pAC->Pnmi.DeviceType = 0x00020003; + } + break; + + case 'C': + pAC->Pnmi.PMD = 4; + if (pAC->GIni.GIMacsFound > 1) { + + pAC->Pnmi.DeviceType = 0x00020006; + } + else { + pAC->Pnmi.DeviceType = 0x00020005; + } + break; + + case 'T': + pAC->Pnmi.PMD = 5; + if (pAC->GIni.GIMacsFound > 1) { + + pAC->Pnmi.DeviceType = 0x00020008; + } + else { + pAC->Pnmi.DeviceType = 0x00020007; + } + break; + + default : + pAC->Pnmi.PMD = 1; + pAC->Pnmi.DeviceType = 0; + break; + } + + /* + * Get connector + */ + SK_IN8(IoC, B2_CONN_TYP, &Val8); + switch (Val8) { + case 'C': + pAC->Pnmi.Connector = 2; + break; + + case 'D': + pAC->Pnmi.Connector = 3; + break; + + case 'F': + pAC->Pnmi.Connector = 4; + break; + + case 'J': + pAC->Pnmi.Connector = 5; + break; + + case 'V': + pAC->Pnmi.Connector = 6; + break; + + default: + pAC->Pnmi.Connector = 1; + break; + } + break; + + case SK_INIT_RUN: + /* + * Start timer for RLMT change counter + */ + SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); + SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer, + 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER, + EventParam); + break; + + default: + break; /* Nothing todo */ + } + + return (0); +} + +/***************************************************************************** + * + * SkPnmiGetVar - Retrieves the value of a single OID + * + * Description: + * Calls a general sub-function for all this stuff. If the instance + * -1 is passed, the values of all instances are returned in an + * array of values. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed + * SK_PNMI_ERR_GENERAL A general severe internal error occured + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take + * the data. + * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +int SkPnmiGetVar( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Id, /* Object ID that is to be processed */ +void *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiGetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n", + Id, *pLen, Instance, NetIndex)); + + return (PnmiVar(pAC, IoC, SK_PNMI_GET, Id, (char *)pBuf, pLen, + Instance, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiPreSetVar - Presets the value of a single OID + * + * Description: + * Calls a general sub-function for all this stuff. The preset does + * the same as a set, but returns just before finally setting the + * new value. This is usefull to check if a set might be successfull. + * If as instance a -1 is passed, an array of values is supposed and + * all instance of the OID will be set. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +int SkPnmiPreSetVar( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Id, /* Object ID that is to be processed */ +void *pBuf, /* Buffer which stores the mgmt data to be set */ +unsigned int *pLen, /* Total length of mgmt data */ +SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n", + Id, *pLen, Instance, NetIndex)); + + + return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen, + Instance, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiSetVar - Sets the value of a single OID + * + * Description: + * Calls a general sub-function for all this stuff. The preset does + * the same as a set, but returns just before finally setting the + * new value. This is usefull to check if a set might be successfull. + * If as instance a -1 is passed, an array of values is supposed and + * all instance of the OID will be set. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +int SkPnmiSetVar( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Id, /* Object ID that is to be processed */ +void *pBuf, /* Buffer which stores the mgmt data to be set */ +unsigned int *pLen, /* Total length of mgmt data */ +SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n", + Id, *pLen, Instance, NetIndex)); + + return (PnmiVar(pAC, IoC, SK_PNMI_SET, Id, (char *)pBuf, pLen, + Instance, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiGetStruct - Retrieves the management database in SK_PNMI_STRUCT_DATA + * + * Description: + * Runs through the IdTable, queries the single OIDs and stores the + * returned data into the management database structure + * SK_PNMI_STRUCT_DATA. The offset of the OID in the structure + * is stored in the IdTable. The return value of the function will also + * be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the + * minimum size of SK_PNMI_MIN_STRUCT_SIZE. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed + * SK_PNMI_ERR_GENERAL A general severe internal error occured + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take + * the data. + * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist + */ +int SkPnmiGetStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +void *pBuf, /* Buffer which will store the retrieved data */ +unsigned int *pLen, /* Length of buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int TableIndex; + unsigned int DstOffset; + unsigned int InstanceNo; + unsigned int InstanceCnt; + SK_U32 Instance; + unsigned int TmpLen; + char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE]; + + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiGetStruct: Called, BufLen=%d, NetIndex=%d\n", + *pLen, NetIndex)); + + if (*pLen < SK_PNMI_STRUCT_SIZE) { + + if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) { + + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, + (SK_U32)(-1)); + } + + *pLen = SK_PNMI_STRUCT_SIZE; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Check NetIndex + */ + if (NetIndex >= pAC->Rlmt.NumNets) { + return (SK_PNMI_ERR_UNKNOWN_NET); + } + + /* Update statistic */ + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call"); + + if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) != + SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + /* + * Increment semaphores to indicate that an update was + * already done + */ + pAC->Pnmi.MacUpdatedFlag ++; + pAC->Pnmi.RlmtUpdatedFlag ++; + pAC->Pnmi.SirqUpdatedFlag ++; + + /* Get vpd keys for instance calculation */ + Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen); + if (Ret != SK_PNMI_ERR_OK) { + + pAC->Pnmi.MacUpdatedFlag --; + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return"); + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (SK_PNMI_ERR_GENERAL); + } + + /* Retrieve values */ + SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE); + for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) { + + InstanceNo = IdTable[TableIndex].InstanceNo; + for (InstanceCnt = 1; InstanceCnt <= InstanceNo; + InstanceCnt ++) { + + DstOffset = IdTable[TableIndex].Offset + + (InstanceCnt - 1) * + IdTable[TableIndex].StructSize; + + /* + * For the VPD the instance is not an index number + * but the key itself. Determin with the instance + * counter the VPD key to be used. + */ + if (IdTable[TableIndex].Id == OID_SKGE_VPD_KEY || + IdTable[TableIndex].Id == OID_SKGE_VPD_VALUE || + IdTable[TableIndex].Id == OID_SKGE_VPD_ACCESS || + IdTable[TableIndex].Id == OID_SKGE_VPD_ACTION) { + + SK_STRNCPY((char *)&Instance, KeyArr[InstanceCnt - 1], 4); + } + else { + Instance = (SK_U32)InstanceCnt; + } + + TmpLen = *pLen - DstOffset; + Ret = IdTable[TableIndex].Func(pAC, IoC, SK_PNMI_GET, + IdTable[TableIndex].Id, (char *)pBuf + + DstOffset, &TmpLen, Instance, TableIndex, NetIndex); + + /* + * An unknown instance error means that we reached + * the last instance of that variable. Proceed with + * the next OID in the table and ignore the return + * code. + */ + if (Ret == SK_PNMI_ERR_UNKNOWN_INST) { + + break; + } + + if (Ret != SK_PNMI_ERR_OK) { + + pAC->Pnmi.MacUpdatedFlag --; + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return"); + SK_PNMI_SET_STAT(pBuf, Ret, DstOffset); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + } + } + + pAC->Pnmi.MacUpdatedFlag --; + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + *pLen = SK_PNMI_STRUCT_SIZE; + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return"); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1)); + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * SkPnmiPreSetStruct - Presets the management database in SK_PNMI_STRUCT_DATA + * + * Description: + * Calls a general sub-function for all this set stuff. The preset does + * the same as a set, but returns just before finally setting the + * new value. This is usefull to check if a set might be successfull. + * The sub-function runs through the IdTable, checks which OIDs are able + * to set, and calls the handler function of the OID to perform the + * preset. The return value of the function will also be stored in + * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of + * SK_PNMI_MIN_STRUCT_SIZE. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + */ +int SkPnmiPreSetStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +void *pBuf, /* Buffer which contains the data to be set */ +unsigned int *pLen, /* Length of buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiPreSetStruct: Called, BufLen=%d, NetIndex=%d\n", + *pLen, NetIndex)); + + return (PnmiStruct(pAC, IoC, SK_PNMI_PRESET, (char *)pBuf, + pLen, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiSetStruct - Sets the management database in SK_PNMI_STRUCT_DATA + * + * Description: + * Calls a general sub-function for all this set stuff. The return value + * of the function will also be stored in SK_PNMI_STRUCT_DATA if the + * passed buffer has the minimum size of SK_PNMI_MIN_STRUCT_SIZE. + * The sub-function runs through the IdTable, checks which OIDs are able + * to set, and calls the handler function of the OID to perform the + * set. The return value of the function will also be stored in + * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of + * SK_PNMI_MIN_STRUCT_SIZE. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + */ +int SkPnmiSetStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +void *pBuf, /* Buffer which contains the data to be set */ +unsigned int *pLen, /* Length of buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiSetStruct: Called, BufLen=%d, NetIndex=%d\n", + *pLen, NetIndex)); + + return (PnmiStruct(pAC, IoC, SK_PNMI_SET, (char *)pBuf, + pLen, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiEvent - Event handler + * + * Description: + * Handles the following events: + * SK_PNMI_EVT_SIRQ_OVERFLOW When a hardware counter overflows an + * interrupt will be generated which is + * first handled by SIRQ which generates a + * this event. The event increments the + * upper 32 bit of the 64 bit counter. + * SK_PNMI_EVT_SEN_XXX The event is generated by the I2C module + * when a sensor reports a warning or + * error. The event will store a trap + * message in the trap buffer. + * SK_PNMI_EVT_CHG_EST_TIMER The timer event was initiated by this + * module and is used to calculate the + * port switches per hour. + * SK_PNMI_EVT_CLEAR_COUNTER The event clears all counters and + * timestamps. + * SK_PNMI_EVT_XMAC_RESET The event is generated by the driver + * before a hard reset of the XMAC is + * performed. All counters will be saved + * and added to the hardware counter + * values after reset to grant continuous + * counter values. + * SK_PNMI_EVT_RLMT_PORT_UP Generated by RLMT to notify that a port + * went logically up. A trap message will + * be stored to the trap buffer. + * SK_PNMI_EVT_RLMT_PORT_DOWN Generated by RLMT to notify that a port + * went logically down. A trap message will + * be stored to the trap buffer. + * SK_PNMI_EVT_RLMT_SEGMENTATION Generated by RLMT to notify that two + * spanning tree root bridges were + * detected. A trap message will be stored + * to the trap buffer. + * SK_PNMI_EVT_RLMT_ACTIVE_DOWN Notifies PNMI that an active port went + * down. PNMI will not further add the + * statistic values to the virtual port. + * SK_PNMI_EVT_RLMT_ACTIVE_UP Notifies PNMI that a port went up and + * is now an active port. PNMI will now + * add the statistic data of this port to + * the virtual port. + * SK_PNMI_EVT_RLMT_SET_NETS Notifies PNMI about the net mode. The first Parameter + * contains the number of nets. 1 means single net, 2 means + * dual net. The second Parameter is -1 + * + * Returns: + * Always 0 + */ +int SkPnmiEvent( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Event, /* Event-Id */ +SK_EVPARA Param) /* Event dependent parameter */ +{ + unsigned int PhysPortIndex; + unsigned int MaxNetNumber; + int CounterIndex; + int Ret; + SK_U16 MacStatus; + SK_U64 OverflowStatus; + SK_U64 Mask; + int MacType; + SK_U64 Value; + SK_U32 Val32; + SK_U16 Register; + SK_EVPARA EventParam; + SK_U64 NewestValue; + SK_U64 OldestValue; + SK_U64 Delta; + SK_PNMI_ESTIMATE *pEst; + SK_U32 NetIndex; + SK_GEPORT *pPrt; + SK_PNMI_VCT *pVctBackupData; + SK_U32 RetCode; + int i; + SK_U32 CableLength; + + +#ifdef DEBUG + if (Event != SK_PNMI_EVT_XMAC_RESET) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiEvent: Called, Event=0x%x, Param=0x%x\n", + (unsigned int)Event, (unsigned int)Param.Para64)); + } +#endif + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On call"); + + MacType = pAC->GIni.GIMacType; + + switch (Event) { + + case SK_PNMI_EVT_SIRQ_OVERFLOW: + PhysPortIndex = (int)Param.Para32[0]; + MacStatus = (SK_U16)Param.Para32[1]; +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SIRQ_OVERFLOW parameter" + " wrong, PhysPortIndex=0x%x\n", + PhysPortIndex)); + return (0); + } +#endif + OverflowStatus = 0; + + /* + * Check which source caused an overflow interrupt. + */ + if ((pAC->GIni.GIFunc.pFnMacOverflow( + pAC, IoC, PhysPortIndex, MacStatus, &OverflowStatus) != 0) || + (OverflowStatus == 0)) { + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); + } + + /* + * Check the overflow status register and increment + * the upper dword of corresponding counter. + */ + for (CounterIndex = 0; CounterIndex < sizeof(Mask) * 8; + CounterIndex ++) { + + Mask = (SK_U64)1 << CounterIndex; + if ((OverflowStatus & Mask) == 0) { + + continue; + } + + switch (StatOvrflwBit[CounterIndex][MacType]) { + + case SK_PNMI_HTX_UTILUNDER: + case SK_PNMI_HTX_UTILOVER: + XM_IN16(IoC, PhysPortIndex, XM_TX_CMD, + &Register); + Register |= XM_TX_SAM_LINE; + XM_OUT16(IoC, PhysPortIndex, XM_TX_CMD, + Register); + break; + + case SK_PNMI_HRX_UTILUNDER: + case SK_PNMI_HRX_UTILOVER: + XM_IN16(IoC, PhysPortIndex, XM_RX_CMD, + &Register); + Register |= XM_RX_SAM_LINE; + XM_OUT16(IoC, PhysPortIndex, XM_RX_CMD, + Register); + break; + + case SK_PNMI_HTX_OCTETHIGH: + case SK_PNMI_HTX_OCTETLOW: + case SK_PNMI_HTX_RESERVED: + case SK_PNMI_HRX_OCTETHIGH: + case SK_PNMI_HRX_OCTETLOW: + case SK_PNMI_HRX_IRLENGTH: + case SK_PNMI_HRX_RESERVED: + + /* + * the following counters aren't be handled (id > 63) + */ + case SK_PNMI_HTX_SYNC: + case SK_PNMI_HTX_SYNC_OCTET: + break; + + case SK_PNMI_HRX_LONGFRAMES: + if (MacType == SK_MAC_GMAC) { + pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[CounterIndex] ++; + } + break; + + default: + pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[CounterIndex] ++; + } + } + break; + + case SK_PNMI_EVT_SEN_WAR_LOW: +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_LOW parameter wrong, SensorIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate + * an event for user space applications with the + * SK_DRIVER_SENDEVENT macro. + */ + QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_LOW, + (unsigned int)Param.Para64); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_SEN_WAR_UPP: +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR:SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_UPP parameter wrong, SensorIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate + * an event for user space applications with the + * SK_DRIVER_SENDEVENT macro. + */ + QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_UPP, + (unsigned int)Param.Para64); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_SEN_ERR_LOW: +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_LOW parameter wrong, SensorIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate + * an event for user space applications with the + * SK_DRIVER_SENDEVENT macro. + */ + QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_LOW, + (unsigned int)Param.Para64); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_SEN_ERR_UPP: +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate + * an event for user space applications with the + * SK_DRIVER_SENDEVENT macro. + */ + QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_UPP, + (unsigned int)Param.Para64); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_CHG_EST_TIMER: + /* + * Calculate port switch average on a per hour basis + * Time interval for check : 28125 ms + * Number of values for average : 8 + * + * Be careful in changing these values, on change check + * - typedef of SK_PNMI_ESTIMATE (Size of EstValue + * array one less than value number) + * - Timer initilization SkTimerStart() in SkPnmiInit + * - Delta value below must be multiplicated with + * power of 2 + * + */ + pEst = &pAC->Pnmi.RlmtChangeEstimate; + CounterIndex = pEst->EstValueIndex + 1; + if (CounterIndex == 7) { + + CounterIndex = 0; + } + pEst->EstValueIndex = CounterIndex; + + NewestValue = pAC->Pnmi.RlmtChangeCts; + OldestValue = pEst->EstValue[CounterIndex]; + pEst->EstValue[CounterIndex] = NewestValue; + + /* + * Calculate average. Delta stores the number of + * port switches per 28125 * 8 = 225000 ms + */ + if (NewestValue >= OldestValue) { + + Delta = NewestValue - OldestValue; + } + else { + /* Overflow situation */ + Delta = (SK_U64)(0 - OldestValue) + NewestValue; + } + + /* + * Extrapolate delta to port switches per hour. + * Estimate = Delta * (3600000 / 225000) + * = Delta * 16 + * = Delta << 4 + */ + pAC->Pnmi.RlmtChangeEstimate.Estimate = Delta << 4; + + /* + * Check if threshold is exceeded. If the threshold is + * permanently exceeded every 28125 ms an event will be + * generated to remind the user of this condition. + */ + if ((pAC->Pnmi.RlmtChangeThreshold != 0) && + (pAC->Pnmi.RlmtChangeEstimate.Estimate >= + pAC->Pnmi.RlmtChangeThreshold)) { + + QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_CHANGE_THRES); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + } + + SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); + SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer, + 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER, + EventParam); + break; + + case SK_PNMI_EVT_CLEAR_COUNTER: + /* + * Param.Para32[0] contains the NetIndex (0 ..1). + * Param.Para32[1] is reserved, contains -1. + */ + NetIndex = (SK_U32)Param.Para32[0]; + +#ifdef DEBUG + if (NetIndex >= pAC->Rlmt.NumNets) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_CLEAR_COUNTER parameter wrong, NetIndex=%d\n", + NetIndex)); + + return (0); + } +#endif + + /* + * Set all counters and timestamps to zero + */ + ResetCounter(pAC, IoC, NetIndex); /* the according NetIndex is required + as a Parameter of the Event */ + break; + + case SK_PNMI_EVT_XMAC_RESET: + /* + * To grant continuous counter values store the current + * XMAC statistic values to the entries 1..n of the + * CounterOffset array. XMAC Errata #2 + */ +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_XMAC_RESET parameter wrong, PhysPortIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + PhysPortIndex = (unsigned int)Param.Para64; + + /* + * Update XMAC statistic to get fresh values + */ + Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); + if (Ret != SK_PNMI_ERR_OK) { + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); + } + /* + * Increment semaphore to indicate that an update was + * already done + */ + pAC->Pnmi.MacUpdatedFlag ++; + + for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX; + CounterIndex ++) { + + if (!StatAddr[CounterIndex][MacType].GetOffset) { + + continue; + } + + pAC->Pnmi.Port[PhysPortIndex]. + CounterOffset[CounterIndex] = GetPhysStatVal( + pAC, IoC, PhysPortIndex, CounterIndex); + pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[CounterIndex] = 0; + } + + pAC->Pnmi.MacUpdatedFlag --; + break; + + case SK_PNMI_EVT_RLMT_PORT_UP: + PhysPortIndex = (unsigned int)Param.Para32[0]; +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_UP parameter" + " wrong, PhysPortIndex=%d\n", PhysPortIndex)); + + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate an event for + * user space applications with the SK_DRIVER_SENDEVENT macro. + */ + QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP, PhysPortIndex); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + + /* Bugfix for XMAC errata (#10620)*/ + if (pAC->GIni.GIMacType == SK_MAC_XMAC){ + + /* Add incremental difference to offset (#10620)*/ + (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex, + XM_RXE_SHT_ERR, &Val32); + + Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32); + pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] += + Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark; + } + + /* Tell VctStatus() that a link was up meanwhile. */ + pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_LINK; + break; + + case SK_PNMI_EVT_RLMT_PORT_DOWN: + PhysPortIndex = (unsigned int)Param.Para32[0]; + +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_DOWN parameter" + " wrong, PhysPortIndex=%d\n", PhysPortIndex)); + + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate an event for + * user space applications with the SK_DRIVER_SENDEVENT macro. + */ + QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + + /* Bugfix #10620 - get zero level for incremental difference */ + if ((pAC->GIni.GIMacType == SK_MAC_XMAC)) { + + (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex, + XM_RXE_SHT_ERR, &Val32); + pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark = + (((SK_U64)pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32); + } + break; + + case SK_PNMI_EVT_RLMT_ACTIVE_DOWN: + PhysPortIndex = (unsigned int)Param.Para32[0]; + NetIndex = (SK_U32)Param.Para32[1]; + +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, PhysPort=%d\n", + PhysPortIndex)); + } + + if (NetIndex >= pAC->Rlmt.NumNets) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, NetIndex=%d\n", + NetIndex)); + } +#endif + /* + * For now, ignore event if NetIndex != 0. + */ + if (Param.Para32[1] != 0) { + + return (0); + } + + /* + * Nothing to do if port is already inactive + */ + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + return (0); + } + + /* + * Update statistic counters to calculate new offset for the virtual + * port and increment semaphore to indicate that an update was already + * done. + */ + if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) != + SK_PNMI_ERR_OK) { + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Calculate new counter offset for virtual port to grant continous + * counting on port switches. The virtual port consists of all currently + * active ports. The port down event indicates that a port is removed + * from the virtual port. Therefore add the counter value of the removed + * port to the CounterOffset for the virtual port to grant the same + * counter value. + */ + for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX; + CounterIndex ++) { + + if (!StatAddr[CounterIndex][MacType].GetOffset) { + + continue; + } + + Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex); + + pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value; + } + + /* + * Set port to inactive + */ + pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE; + + pAC->Pnmi.MacUpdatedFlag --; + break; + + case SK_PNMI_EVT_RLMT_ACTIVE_UP: + PhysPortIndex = (unsigned int)Param.Para32[0]; + NetIndex = (SK_U32)Param.Para32[1]; + +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, PhysPort=%d\n", + PhysPortIndex)); + } + + if (NetIndex >= pAC->Rlmt.NumNets) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, NetIndex=%d\n", + NetIndex)); + } +#endif + /* + * For now, ignore event if NetIndex != 0. + */ + if (Param.Para32[1] != 0) { + + return (0); + } + + /* + * Nothing to do if port is already active + */ + if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + return (0); + } + + /* + * Statistic maintenance + */ + pAC->Pnmi.RlmtChangeCts ++; + pAC->Pnmi.RlmtChangeTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); + + /* + * Store a trap message in the trap buffer and generate an event for + * user space applications with the SK_DRIVER_SENDEVENT macro. + */ + QueueRlmtNewMacTrap(pAC, PhysPortIndex); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + + /* + * Update statistic counters to calculate new offset for the virtual + * port and increment semaphore to indicate that an update was + * already done. + */ + if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) != + SK_PNMI_ERR_OK) { + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Calculate new counter offset for virtual port to grant continous + * counting on port switches. A new port is added to the virtual port. + * Therefore substract the counter value of the new port from the + * CounterOffset for the virtual port to grant the same value. + */ + for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX; + CounterIndex ++) { + + if (!StatAddr[CounterIndex][MacType].GetOffset) { + + continue; + } + + Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex); + + pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value; + } + + /* + * Set port to active + */ + pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE; + + pAC->Pnmi.MacUpdatedFlag --; + break; + + case SK_PNMI_EVT_RLMT_SEGMENTATION: + /* + * Para.Para32[0] contains the NetIndex. + */ + + /* + * Store a trap message in the trap buffer and generate an event for + * user space applications with the SK_DRIVER_SENDEVENT macro. + */ + QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_SEGMENTATION); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_RLMT_SET_NETS: + /* + * Param.Para32[0] contains the number of Nets. + * Param.Para32[1] is reserved, contains -1. + */ + /* + * Check number of nets + */ + MaxNetNumber = pAC->GIni.GIMacsFound; + if (((unsigned int)Param.Para32[0] < 1) + || ((unsigned int)Param.Para32[0] > MaxNetNumber)) { + return (SK_PNMI_ERR_UNKNOWN_NET); + } + + if ((unsigned int)Param.Para32[0] == 1) { /* single net mode */ + pAC->Pnmi.DualNetActiveFlag = SK_FALSE; + } + else { /* dual net mode */ + pAC->Pnmi.DualNetActiveFlag = SK_TRUE; + } + break; + + case SK_PNMI_EVT_VCT_RESET: + PhysPortIndex = Param.Para32[0]; + pPrt = &pAC->GIni.GP[PhysPortIndex]; + pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex]; + + if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) { + RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE); + if (RetCode == 2) { + /* + * VCT test is still running. + * Start VCT timer counter again. + */ + SK_MEMSET((char *) &Param, 0, sizeof(Param)); + Param.Para32[0] = PhysPortIndex; + Param.Para32[1] = -1; + SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer, + 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param); + break; + } + pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING; + pAC->Pnmi.VctStatus[PhysPortIndex] |= + (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE); + + /* Copy results for later use to PNMI struct. */ + for (i = 0; i < 4; i++) { + if (pPrt->PMdiPairLen[i] > 35) { + CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28); + } + else { + CableLength = 0; + } + pVctBackupData->PMdiPairLen[i] = CableLength; + pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i]; + } + + Param.Para32[0] = PhysPortIndex; + Param.Para32[1] = -1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Param); + SkEventDispatcher(pAC, IoC); + } + + break; + + default: + break; + } + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); +} + + +/****************************************************************************** + * + * Private functions + * + */ + +/***************************************************************************** + * + * PnmiVar - Gets, presets, and sets single OIDs + * + * Description: + * Looks up the requested OID, calls the corresponding handler + * function, and passes the parameters with the get, preset, or + * set command. The function is called by SkGePnmiGetVar, + * SkGePnmiPreSetVar, or SkGePnmiSetVar. + * + * Returns: + * SK_PNMI_ERR_XXX. For details have a look to the description of the + * calling functions. + * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist + */ +PNMI_STATIC int PnmiVar( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer which stores the mgmt data to be set */ +unsigned int *pLen, /* Total length of mgmt data */ +SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int TableIndex; + int Ret; + + + if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_OID); + } + + /* + * Check NetIndex + */ + if (NetIndex >= pAC->Rlmt.NumNets) { + return (SK_PNMI_ERR_UNKNOWN_NET); + } + + SK_PNMI_CHECKFLAGS("PnmiVar: On call"); + + Ret = IdTable[TableIndex].Func(pAC, IoC, Action, Id, pBuf, pLen, + Instance, TableIndex, NetIndex); + + SK_PNMI_CHECKFLAGS("PnmiVar: On return"); + + return (Ret); +} + +/***************************************************************************** + * + * PnmiStruct - Presets and Sets data in structure SK_PNMI_STRUCT_DATA + * + * Description: + * The return value of the function will also be stored in + * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of + * SK_PNMI_MIN_STRUCT_SIZE. The sub-function runs through the IdTable, + * checks which OIDs are able to set, and calls the handler function of + * the OID to perform the set. The return value of the function will + * also be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the + * minimum size of SK_PNMI_MIN_STRUCT_SIZE. The function is called + * by SkGePnmiPreSetStruct and SkGePnmiSetStruct. + * + * Returns: + * SK_PNMI_ERR_XXX. The codes are described in the calling functions. + * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist + */ +PNMI_STATIC int PnmiStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Set action to be performed */ +char *pBuf, /* Buffer which contains the data to be set */ +unsigned int *pLen, /* Length of buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int TableIndex; + unsigned int DstOffset; + unsigned int Len; + unsigned int InstanceNo; + unsigned int InstanceCnt; + SK_U32 Instance; + SK_U32 Id; + + + /* Check if the passed buffer has the right size */ + if (*pLen < SK_PNMI_STRUCT_SIZE) { + + /* Check if we can return the error within the buffer */ + if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) { + + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, + (SK_U32)(-1)); + } + + *pLen = SK_PNMI_STRUCT_SIZE; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Check NetIndex + */ + if (NetIndex >= pAC->Rlmt.NumNets) { + return (SK_PNMI_ERR_UNKNOWN_NET); + } + + SK_PNMI_CHECKFLAGS("PnmiStruct: On call"); + + /* + * Update the values of RLMT and SIRQ and increment semaphores to + * indicate that an update was already done. + */ + if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + pAC->Pnmi.RlmtUpdatedFlag ++; + pAC->Pnmi.SirqUpdatedFlag ++; + + /* Preset/Set values */ + for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) { + + if ((IdTable[TableIndex].Access != SK_PNMI_RW) && + (IdTable[TableIndex].Access != SK_PNMI_WO)) { + + continue; + } + + InstanceNo = IdTable[TableIndex].InstanceNo; + Id = IdTable[TableIndex].Id; + + for (InstanceCnt = 1; InstanceCnt <= InstanceNo; + InstanceCnt ++) { + + DstOffset = IdTable[TableIndex].Offset + + (InstanceCnt - 1) * + IdTable[TableIndex].StructSize; + + /* + * Because VPD multiple instance variables are + * not setable we do not need to evaluate VPD + * instances. Have a look to VPD instance + * calculation in SkPnmiGetStruct(). + */ + Instance = (SK_U32)InstanceCnt; + + /* + * Evaluate needed buffer length + */ + Len = 0; + Ret = IdTable[TableIndex].Func(pAC, IoC, + SK_PNMI_GET, IdTable[TableIndex].Id, + NULL, &Len, Instance, TableIndex, NetIndex); + + if (Ret == SK_PNMI_ERR_UNKNOWN_INST) { + + break; + } + if (Ret != SK_PNMI_ERR_TOO_SHORT) { + + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("PnmiStruct: On return"); + SK_PNMI_SET_STAT(pBuf, + SK_PNMI_ERR_GENERAL, DstOffset); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (SK_PNMI_ERR_GENERAL); + } + if (Id == OID_SKGE_VPD_ACTION) { + + switch (*(pBuf + DstOffset)) { + + case SK_PNMI_VPD_CREATE: + Len = 3 + *(pBuf + DstOffset + 3); + break; + + case SK_PNMI_VPD_DELETE: + Len = 3; + break; + + default: + Len = 1; + break; + } + } + + /* Call the OID handler function */ + Ret = IdTable[TableIndex].Func(pAC, IoC, Action, + IdTable[TableIndex].Id, pBuf + DstOffset, + &Len, Instance, TableIndex, NetIndex); + + if (Ret != SK_PNMI_ERR_OK) { + + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("PnmiStruct: On return"); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE, + DstOffset); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (SK_PNMI_ERR_BAD_VALUE); + } + } + } + + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("PnmiStruct: On return"); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1)); + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * LookupId - Lookup an OID in the IdTable + * + * Description: + * Scans the IdTable to find the table entry of an OID. + * + * Returns: + * The table index or -1 if not found. + */ +PNMI_STATIC int LookupId( +SK_U32 Id) /* Object identifier to be searched */ +{ + int i; + + for (i = 0; i < ID_TABLE_SIZE; i++) { + + if (IdTable[i].Id == Id) { + + return i; + } + } + + return (-1); +} + +/***************************************************************************** + * + * OidStruct - Handler of OID_SKGE_ALL_DATA + * + * Description: + * This OID performs a Get/Preset/SetStruct call and returns all data + * in a SK_PNMI_STRUCT_DATA structure. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int OidStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + if (Id != OID_SKGE_ALL_DATA) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003, + SK_PNMI_ERR003MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Check instance. We only handle single instance variables + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + switch (Action) { + + case SK_PNMI_GET: + return (SkPnmiGetStruct(pAC, IoC, pBuf, pLen, NetIndex)); + + case SK_PNMI_PRESET: + return (SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen, NetIndex)); + + case SK_PNMI_SET: + return (SkPnmiSetStruct(pAC, IoC, pBuf, pLen, NetIndex)); + } + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR004, SK_PNMI_ERR004MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); +} + +/***************************************************************************** + * + * Perform - OID handler of OID_SKGE_ACTION + * + * Description: + * None. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Perform( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + SK_U32 ActionOp; + + + /* + * Check instance. We only handle single instance variables + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* Check if a get should be performed */ + if (Action == SK_PNMI_GET) { + + /* A get is easy. We always return the same value */ + ActionOp = (SK_U32)SK_PNMI_ACT_IDLE; + SK_PNMI_STORE_U32(pBuf, ActionOp); + *pLen = sizeof(SK_U32); + + return (SK_PNMI_ERR_OK); + } + + /* Continue with PRESET/SET action */ + if (*pLen > sizeof(SK_U32)) { + + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* Check if the command is a known one */ + SK_PNMI_READ_U32(pBuf, ActionOp); + if (*pLen > sizeof(SK_U32) || + (ActionOp != SK_PNMI_ACT_IDLE && + ActionOp != SK_PNMI_ACT_RESET && + ActionOp != SK_PNMI_ACT_SELFTEST && + ActionOp != SK_PNMI_ACT_RESETCNT)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* A preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + switch (ActionOp) { + + case SK_PNMI_ACT_IDLE: + /* Nothing to do */ + break; + + case SK_PNMI_ACT_RESET: + /* + * Perform a driver reset or something that comes near + * to this. + */ + Ret = SK_DRIVER_RESET(pAC, IoC); + if (Ret != 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005, + SK_PNMI_ERR005MSG); + + return (SK_PNMI_ERR_GENERAL); + } + break; + + case SK_PNMI_ACT_SELFTEST: + /* + * Perform a driver selftest or something similar to this. + * Currently this feature is not used and will probably + * implemented in another way. + */ + Ret = SK_DRIVER_SELFTEST(pAC, IoC); + pAC->Pnmi.TestResult = Ret; + break; + + case SK_PNMI_ACT_RESETCNT: + /* Set all counters and timestamps to zero */ + ResetCounter(pAC, IoC, NetIndex); + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006, + SK_PNMI_ERR006MSG); + + return (SK_PNMI_ERR_GENERAL); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Mac8023Stat - OID handler of OID_GEN_XXX and OID_802_3_XXX + * + * Description: + * Retrieves the statistic values of the virtual port (logical + * index 0). Only special OIDs of NDIS are handled which consist + * of a 32 bit instead of a 64 bit value. The OIDs are public + * because perhaps some other platform can use them too. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Mac8023Stat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + SK_U64 StatVal; + SK_U32 StatVal32; + SK_BOOL Is64BitReq = SK_FALSE; + + /* + * Only the active Mac is returned + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* + * Check action type + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check length + */ + switch (Id) { + + case OID_802_3_PERMANENT_ADDRESS: + case OID_802_3_CURRENT_ADDRESS: + if (*pLen < sizeof(SK_MAC_ADDR)) { + + *pLen = sizeof(SK_MAC_ADDR); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: +#ifndef SK_NDIS_64BIT_CTR + if (*pLen < sizeof(SK_U32)) { + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + +#else /* SK_NDIS_64BIT_CTR */ + + /* + * for compatibility, at least 32bit are required for oid + */ + if (*pLen < sizeof(SK_U32)) { + /* + * but indicate handling for 64bit values, + * if insufficient space is provided + */ + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + + Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE; +#endif /* SK_NDIS_64BIT_CTR */ + break; + } + + /* + * Update all statistics, because we retrieve virtual MAC, which + * consists of multiple physical statistics and increment semaphore + * to indicate that an update was already done. + */ + Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); + if ( Ret != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Get value (MAC Index 0 identifies the virtual MAC) + */ + switch (Id) { + + case OID_802_3_PERMANENT_ADDRESS: + CopyMac(pBuf, &pAC->Addr.Net[NetIndex].PermanentMacAddress); + *pLen = sizeof(SK_MAC_ADDR); + break; + + case OID_802_3_CURRENT_ADDRESS: + CopyMac(pBuf, &pAC->Addr.Net[NetIndex].CurrentMacAddress); + *pLen = sizeof(SK_MAC_ADDR); + break; + + default: + StatVal = GetStatVal(pAC, IoC, 0, IdTable[TableIndex].Param, NetIndex); + + /* + * by default 32bit values are evaluated + */ + if (!Is64BitReq) { + StatVal32 = (SK_U32)StatVal; + SK_PNMI_STORE_U32(pBuf, StatVal32); + *pLen = sizeof(SK_U32); + } + else { + SK_PNMI_STORE_U64(pBuf, StatVal); + *pLen = sizeof(SK_U64); + } + break; + } + + pAC->Pnmi.MacUpdatedFlag --; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * MacPrivateStat - OID handler function of OID_SKGE_STAT_XXX + * + * Description: + * Retrieves the XMAC statistic data. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int MacPrivateStat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int LogPortMax; + unsigned int LogPortIndex; + unsigned int PhysPortMax; + unsigned int Limit; + unsigned int Offset; + int Ret; + SK_U64 StatVal; + + + /* + * Calculate instance if wished. MAC index 0 is the virtual + * MAC. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + LogPortMax--; + } + + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */ + /* Check instance range */ + if ((Instance < 1) || (Instance > LogPortMax)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance); + Limit = LogPortIndex + 1; + } + + else { /* Instance == (SK_U32)(-1), get all Instances of that OID */ + + LogPortIndex = 0; + Limit = LogPortMax; + } + + + /* + * Check action + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check length + */ + if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) { + + *pLen = (Limit - LogPortIndex) * sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Update XMAC statistic and increment semaphore to indicate that + * an update was already done. + */ + Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); + if (Ret != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Get value + */ + Offset = 0; + for (; LogPortIndex < Limit; LogPortIndex ++) { + + switch (Id) { + +/* XXX not yet implemented due to XMAC problems + case OID_SKGE_STAT_TX_UTIL: + return (SK_PNMI_ERR_GENERAL); +*/ +/* XXX not yet implemented due to XMAC problems + case OID_SKGE_STAT_RX_UTIL: + return (SK_PNMI_ERR_GENERAL); +*/ + case OID_SKGE_STAT_RX: + case OID_SKGE_STAT_TX: + switch (pAC->GIni.GIMacType) { + case SK_MAC_XMAC: + StatVal = GetStatVal(pAC, IoC, LogPortIndex, + IdTable[TableIndex].Param, NetIndex); + break; + + case SK_MAC_GMAC: + if (Id == OID_SKGE_STAT_TX) { + + StatVal = + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HTX_BROADCAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HTX_MULTICAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HTX_UNICAST, NetIndex); + } + else { + StatVal = + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_BROADCAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_MULTICAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_UNICAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_UNDERSIZE, NetIndex); + } + break; + + default: + StatVal = 0; + break; + } + + SK_PNMI_STORE_U64(pBuf + Offset, StatVal); + break; + + default: + StatVal = GetStatVal(pAC, IoC, LogPortIndex, + IdTable[TableIndex].Param, NetIndex); + SK_PNMI_STORE_U64(pBuf + Offset, StatVal); + break; + } + + Offset += sizeof(SK_U64); + } + *pLen = Offset; + + pAC->Pnmi.MacUpdatedFlag --; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Addr - OID handler function of OID_SKGE_PHYS_CUR_ADDR and _FAC_ADDR + * + * Description: + * Get/Presets/Sets the current and factory MAC address. The MAC + * address of the virtual port, which is reported to the OS, may + * not be changed, but the physical ones. A set to the virtual port + * will be ignored. No error should be reported because otherwise + * a multiple instance set (-1) would always fail. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Addr( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int LogPortMax; + unsigned int PhysPortMax; + unsigned int LogPortIndex; + unsigned int PhysPortIndex; + unsigned int Limit; + unsigned int Offset = 0; + + /* + * Calculate instance if wished. MAC index 0 is the virtual + * MAC. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + LogPortMax--; + } + + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */ + /* Check instance range */ + if ((Instance < 1) || (Instance > LogPortMax)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance); + Limit = LogPortIndex + 1; + } + + else { /* Instance == (SK_U32)(-1), get all Instances of that OID */ + + LogPortIndex = 0; + Limit = LogPortMax; + } + + /* + * Perform Action + */ + if (Action == SK_PNMI_GET) { + + /* + * Check length + */ + if (*pLen < (Limit - LogPortIndex) * 6) { + + *pLen = (Limit - LogPortIndex) * 6; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Get value + */ + for (; LogPortIndex < Limit; LogPortIndex ++) { + + switch (Id) { + + case OID_SKGE_PHYS_CUR_ADDR: + if (LogPortIndex == 0) { + CopyMac(pBuf + Offset, &pAC->Addr.Net[NetIndex].CurrentMacAddress); + } + else { + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); + + CopyMac(pBuf + Offset, + &pAC->Addr.Port[PhysPortIndex].CurrentMacAddress); + } + Offset += 6; + break; + + case OID_SKGE_PHYS_FAC_ADDR: + if (LogPortIndex == 0) { + CopyMac(pBuf + Offset, + &pAC->Addr.Net[NetIndex].PermanentMacAddress); + } + else { + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + CopyMac(pBuf + Offset, + &pAC->Addr.Port[PhysPortIndex].PermanentMacAddress); + } + Offset += 6; + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008, + SK_PNMI_ERR008MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + + *pLen = Offset; + } + else { + /* + * The logical MAC address may not be changed only + * the physical ones + */ + if (Id == OID_SKGE_PHYS_FAC_ADDR) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Only the current address may be changed + */ + if (Id != OID_SKGE_PHYS_CUR_ADDR) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009, + SK_PNMI_ERR009MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Check length + */ + if (*pLen < (Limit - LogPortIndex) * 6) { + + *pLen = (Limit - LogPortIndex) * 6; + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen > (Limit - LogPortIndex) * 6) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* + * Check Action + */ + if (Action == SK_PNMI_PRESET) { + + *pLen = 0; + return (SK_PNMI_ERR_OK); + } + + /* + * Set OID_SKGE_MAC_CUR_ADDR + */ + for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) { + + /* + * A set to virtual port and set of broadcast + * address will be ignored + */ + if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset, + "\xff\xff\xff\xff\xff\xff", 6) == 0) { + + continue; + } + + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, + LogPortIndex); + + Ret = SkAddrOverride(pAC, IoC, PhysPortIndex, + (SK_MAC_ADDR *)(pBuf + Offset), + (LogPortIndex == 0 ? SK_ADDR_VIRTUAL_ADDRESS : + SK_ADDR_PHYSICAL_ADDRESS)); + if (Ret != SK_ADDR_OVERRIDE_SUCCESS) { + + return (SK_PNMI_ERR_GENERAL); + } + } + *pLen = Offset; + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * CsumStat - OID handler function of OID_SKGE_CHKSM_XXX + * + * Description: + * Retrieves the statistic values of the CSUM module. The CSUM data + * structure must be available in the SK_AC even if the CSUM module + * is not included, because PNMI reads the statistic data from the + * CSUM part of SK_AC directly. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int CsumStat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int Index; + unsigned int Limit; + unsigned int Offset = 0; + SK_U64 StatVal; + + + /* + * Calculate instance if wished + */ + if (Instance != (SK_U32)(-1)) { + + if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + Index = (unsigned int)Instance - 1; + Limit = Index + 1; + } + else { + Index = 0; + Limit = SKCS_NUM_PROTOCOLS; + } + + /* + * Check action + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check length + */ + if (*pLen < (Limit - Index) * sizeof(SK_U64)) { + + *pLen = (Limit - Index) * sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Get value + */ + for (; Index < Limit; Index ++) { + + switch (Id) { + + case OID_SKGE_CHKSM_RX_OK_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxOkCts; + break; + + case OID_SKGE_CHKSM_RX_UNABLE_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxUnableCts; + break; + + case OID_SKGE_CHKSM_RX_ERR_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxErrCts; + break; + + case OID_SKGE_CHKSM_TX_OK_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxOkCts; + break; + + case OID_SKGE_CHKSM_TX_UNABLE_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxUnableCts; + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010, + SK_PNMI_ERR010MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + SK_PNMI_STORE_U64(pBuf + Offset, StatVal); + Offset += sizeof(SK_U64); + } + + /* + * Store used buffer space + */ + *pLen = Offset; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * SensorStat - OID handler function of OID_SKGE_SENSOR_XXX + * + * Description: + * Retrieves the statistic values of the I2C module, which handles + * the temperature and voltage sensors. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int SensorStat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int i; + unsigned int Index; + unsigned int Limit; + unsigned int Offset; + unsigned int Len; + SK_U32 Val32; + SK_U64 Val64; + + + /* + * Calculate instance if wished + */ + if ((Instance != (SK_U32)(-1))) { + + if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + Index = (unsigned int)Instance -1; + Limit = (unsigned int)Instance; + } + else { + Index = 0; + Limit = (unsigned int) pAC->I2c.MaxSens; + } + + /* + * Check action + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check length + */ + switch (Id) { + + case OID_SKGE_SENSOR_VALUE: + case OID_SKGE_SENSOR_WAR_THRES_LOW: + case OID_SKGE_SENSOR_WAR_THRES_UPP: + case OID_SKGE_SENSOR_ERR_THRES_LOW: + case OID_SKGE_SENSOR_ERR_THRES_UPP: + if (*pLen < (Limit - Index) * sizeof(SK_U32)) { + + *pLen = (Limit - Index) * sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_SENSOR_DESCR: + for (Offset = 0, i = Index; i < Limit; i ++) { + + Len = (unsigned int) + SK_STRLEN(pAC->I2c.SenTable[i].SenDesc) + 1; + if (Len >= SK_PNMI_STRINGLEN2) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR011, + SK_PNMI_ERR011MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + Offset += Len; + } + if (*pLen < Offset) { + + *pLen = Offset; + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_SENSOR_INDEX: + case OID_SKGE_SENSOR_TYPE: + case OID_SKGE_SENSOR_STATUS: + if (*pLen < Limit - Index) { + + *pLen = Limit - Index; + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_SENSOR_WAR_CTS: + case OID_SKGE_SENSOR_WAR_TIME: + case OID_SKGE_SENSOR_ERR_CTS: + case OID_SKGE_SENSOR_ERR_TIME: + if (*pLen < (Limit - Index) * sizeof(SK_U64)) { + + *pLen = (Limit - Index) * sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012, + SK_PNMI_ERR012MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + + } + + /* + * Get value + */ + for (Offset = 0; Index < Limit; Index ++) { + + switch (Id) { + + case OID_SKGE_SENSOR_INDEX: + *(pBuf + Offset) = (char)Index; + Offset += sizeof(char); + break; + + case OID_SKGE_SENSOR_DESCR: + Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc); + SK_MEMCPY(pBuf + Offset + 1, + pAC->I2c.SenTable[Index].SenDesc, Len); + *(pBuf + Offset) = (char)Len; + Offset += Len + 1; + break; + + case OID_SKGE_SENSOR_TYPE: + *(pBuf + Offset) = + (char)pAC->I2c.SenTable[Index].SenType; + Offset += sizeof(char); + break; + + case OID_SKGE_SENSOR_VALUE: + Val32 = (SK_U32)pAC->I2c.SenTable[Index].SenValue; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_WAR_THRES_LOW: + Val32 = (SK_U32)pAC->I2c.SenTable[Index]. + SenThreWarnLow; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_WAR_THRES_UPP: + Val32 = (SK_U32)pAC->I2c.SenTable[Index]. + SenThreWarnHigh; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_ERR_THRES_LOW: + Val32 = (SK_U32)pAC->I2c.SenTable[Index]. + SenThreErrLow; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_ERR_THRES_UPP: + Val32 = pAC->I2c.SenTable[Index].SenThreErrHigh; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_STATUS: + *(pBuf + Offset) = + (char)pAC->I2c.SenTable[Index].SenErrFlag; + Offset += sizeof(char); + break; + + case OID_SKGE_SENSOR_WAR_CTS: + Val64 = pAC->I2c.SenTable[Index].SenWarnCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_SENSOR_ERR_CTS: + Val64 = pAC->I2c.SenTable[Index].SenErrCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_SENSOR_WAR_TIME: + Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index]. + SenBegWarnTS); + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_SENSOR_ERR_TIME: + Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index]. + SenBegErrTS); + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("SensorStat: Unknown OID should be handled before")); + + return (SK_PNMI_ERR_GENERAL); + } + } + + /* + * Store used buffer space + */ + *pLen = Offset; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Vpd - OID handler function of OID_SKGE_VPD_XXX + * + * Description: + * Get/preset/set of VPD data. As instance the name of a VPD key + * can be passed. The Instance parameter is a SK_U32 and can be + * used as a string buffer for the VPD key, because their maximum + * length is 4 byte. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Vpd( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_VPD_STATUS *pVpdStatus; + unsigned int BufLen; + char Buf[256]; + char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE]; + char KeyStr[SK_PNMI_VPD_KEY_SIZE]; + unsigned int KeyNo; + unsigned int Offset; + unsigned int Index; + unsigned int FirstIndex; + unsigned int LastIndex; + unsigned int Len; + int Ret; + SK_U32 Val32; + + /* + * Get array of all currently stored VPD keys + */ + Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), + &KeyNo); + if (Ret != SK_PNMI_ERR_OK) { + *pLen = 0; + return (Ret); + } + + /* + * If instance is not -1, try to find the requested VPD key for + * the multiple instance variables. The other OIDs as for example + * OID VPD_ACTION are single instance variables and must be + * handled separatly. + */ + FirstIndex = 0; + LastIndex = KeyNo; + + if ((Instance != (SK_U32)(-1))) { + + if (Id == OID_SKGE_VPD_KEY || Id == OID_SKGE_VPD_VALUE || + Id == OID_SKGE_VPD_ACCESS) { + + SK_STRNCPY(KeyStr, (char *)&Instance, 4); + KeyStr[4] = 0; + + for (Index = 0; Index < KeyNo; Index ++) { + + if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) { + FirstIndex = Index; + LastIndex = Index+1; + break; + } + } + if (Index == KeyNo) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + } + else if (Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + } + + /* + * Get value, if a query should be performed + */ + if (Action == SK_PNMI_GET) { + + switch (Id) { + + case OID_SKGE_VPD_FREE_BYTES: + /* Check length of buffer */ + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + /* Get number of free bytes */ + pVpdStatus = VpdStat(pAC, IoC); + if (pVpdStatus == NULL) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR017, + SK_PNMI_ERR017MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + if ((pVpdStatus->vpd_status & VPD_VALID) == 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR018, + SK_PNMI_ERR018MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + Val32 = (SK_U32)pVpdStatus->vpd_free_rw; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_VPD_ENTRIES_LIST: + /* Check length */ + for (Len = 0, Index = 0; Index < KeyNo; Index ++) { + + Len += SK_STRLEN(KeyArr[Index]) + 1; + } + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* Get value */ + *(pBuf) = (char)Len - 1; + for (Offset = 1, Index = 0; Index < KeyNo; Index ++) { + + Len = SK_STRLEN(KeyArr[Index]); + SK_MEMCPY(pBuf + Offset, KeyArr[Index], Len); + + Offset += Len; + + if (Index < KeyNo - 1) { + + *(pBuf + Offset) = ' '; + Offset ++; + } + } + *pLen = Offset; + break; + + case OID_SKGE_VPD_ENTRIES_NUMBER: + /* Check length */ + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + + Val32 = (SK_U32)KeyNo; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_VPD_KEY: + /* Check buffer length, if it is large enough */ + for (Len = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + Len += SK_STRLEN(KeyArr[Index]) + 1; + } + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Get the key to an intermediate buffer, because + * we have to prepend a length byte. + */ + for (Offset = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + Len = SK_STRLEN(KeyArr[Index]); + + *(pBuf + Offset) = (char)Len; + SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index], + Len); + Offset += Len + 1; + } + *pLen = Offset; + break; + + case OID_SKGE_VPD_VALUE: + /* Check the buffer length if it is large enough */ + for (Offset = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + BufLen = 256; + if (VpdRead(pAC, IoC, KeyArr[Index], Buf, + (int *)&BufLen) > 0 || + BufLen >= SK_PNMI_VPD_DATALEN) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR021, + SK_PNMI_ERR021MSG); + + return (SK_PNMI_ERR_GENERAL); + } + Offset += BufLen + 1; + } + if (*pLen < Offset) { + + *pLen = Offset; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Get the value to an intermediate buffer, because + * we have to prepend a length byte. + */ + for (Offset = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + BufLen = 256; + if (VpdRead(pAC, IoC, KeyArr[Index], Buf, + (int *)&BufLen) > 0 || + BufLen >= SK_PNMI_VPD_DATALEN) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR022, + SK_PNMI_ERR022MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + *(pBuf + Offset) = (char)BufLen; + SK_MEMCPY(pBuf + Offset + 1, Buf, BufLen); + Offset += BufLen + 1; + } + *pLen = Offset; + break; + + case OID_SKGE_VPD_ACCESS: + if (*pLen < LastIndex - FirstIndex) { + + *pLen = LastIndex - FirstIndex; + return (SK_PNMI_ERR_TOO_SHORT); + } + + for (Offset = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + if (VpdMayWrite(KeyArr[Index])) { + + *(pBuf + Offset) = SK_PNMI_VPD_RW; + } + else { + *(pBuf + Offset) = SK_PNMI_VPD_RO; + } + Offset ++; + } + *pLen = Offset; + break; + + case OID_SKGE_VPD_ACTION: + Offset = LastIndex - FirstIndex; + if (*pLen < Offset) { + + *pLen = Offset; + return (SK_PNMI_ERR_TOO_SHORT); + } + SK_MEMSET(pBuf, 0, Offset); + *pLen = Offset; + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR023, + SK_PNMI_ERR023MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + else { + /* The only OID which can be set is VPD_ACTION */ + if (Id != OID_SKGE_VPD_ACTION) { + + if (Id == OID_SKGE_VPD_FREE_BYTES || + Id == OID_SKGE_VPD_ENTRIES_LIST || + Id == OID_SKGE_VPD_ENTRIES_NUMBER || + Id == OID_SKGE_VPD_KEY || + Id == OID_SKGE_VPD_VALUE || + Id == OID_SKGE_VPD_ACCESS) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR024, + SK_PNMI_ERR024MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * From this point we handle VPD_ACTION. Check the buffer + * length. It should at least have the size of one byte. + */ + if (*pLen < 1) { + + *pLen = 1; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * The first byte contains the VPD action type we should + * perform. + */ + switch (*pBuf) { + + case SK_PNMI_VPD_IGNORE: + /* Nothing to do */ + break; + + case SK_PNMI_VPD_CREATE: + /* + * We have to create a new VPD entry or we modify + * an existing one. Check first the buffer length. + */ + if (*pLen < 4) { + + *pLen = 4; + return (SK_PNMI_ERR_TOO_SHORT); + } + KeyStr[0] = pBuf[1]; + KeyStr[1] = pBuf[2]; + KeyStr[2] = 0; + + /* + * Is the entry writable or does it belong to the + * read-only area? + */ + if (!VpdMayWrite(KeyStr)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + Offset = (int)pBuf[3] & 0xFF; + + SK_MEMCPY(Buf, pBuf + 4, Offset); + Buf[Offset] = 0; + + /* A preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + /* Write the new entry or modify an existing one */ + Ret = VpdWrite(pAC, IoC, KeyStr, Buf); + if (Ret == SK_PNMI_VPD_NOWRITE ) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + else if (Ret != SK_PNMI_VPD_OK) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR025, + SK_PNMI_ERR025MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Perform an update of the VPD data. This is + * not mandantory, but just to be sure. + */ + Ret = VpdUpdate(pAC, IoC); + if (Ret != SK_PNMI_VPD_OK) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR026, + SK_PNMI_ERR026MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + break; + + case SK_PNMI_VPD_DELETE: + /* Check if the buffer size is plausible */ + if (*pLen < 3) { + + *pLen = 3; + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen > 3) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + KeyStr[0] = pBuf[1]; + KeyStr[1] = pBuf[2]; + KeyStr[2] = 0; + + /* Find the passed key in the array */ + for (Index = 0; Index < KeyNo; Index ++) { + + if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) { + + break; + } + } + /* + * If we cannot find the key it is wrong, so we + * return an appropriate error value. + */ + if (Index == KeyNo) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + /* Ok, you wanted it and you will get it */ + Ret = VpdDelete(pAC, IoC, KeyStr); + if (Ret != SK_PNMI_VPD_OK) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR027, + SK_PNMI_ERR027MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Perform an update of the VPD data. This is + * not mandantory, but just to be sure. + */ + Ret = VpdUpdate(pAC, IoC); + if (Ret != SK_PNMI_VPD_OK) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR028, + SK_PNMI_ERR028MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * General - OID handler function of various single instance OIDs + * + * Description: + * The code is simple. No description necessary. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int General( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int Index; + unsigned int Len; + unsigned int Offset; + unsigned int Val; + SK_U8 Val8; + SK_U16 Val16; + SK_U32 Val32; + SK_U64 Val64; + SK_U64 Val64RxHwErrs = 0; + SK_U64 Val64TxHwErrs = 0; + SK_BOOL Is64BitReq = SK_FALSE; + char Buf[256]; + int MacType; + + /* + * Check instance. We only handle single instance variables + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* + * Check action. We only allow get requests. + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + MacType = pAC->GIni.GIMacType; + + /* + * Check length for the various supported OIDs + */ + switch (Id) { + + case OID_GEN_XMIT_ERROR: + case OID_GEN_RCV_ERROR: + case OID_GEN_RCV_NO_BUFFER: +#ifndef SK_NDIS_64BIT_CTR + if (*pLen < sizeof(SK_U32)) { + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + +#else /* SK_NDIS_64BIT_CTR */ + + /* + * for compatibility, at least 32bit are required for oid + */ + if (*pLen < sizeof(SK_U32)) { + /* + * but indicate handling for 64bit values, + * if insufficient space is provided + */ + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + + Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE; +#endif /* SK_NDIS_64BIT_CTR */ + break; + + case OID_SKGE_PORT_NUMBER: + case OID_SKGE_DEVICE_TYPE: + case OID_SKGE_RESULT: + case OID_SKGE_RLMT_MONITOR_NUMBER: + case OID_GEN_TRANSMIT_QUEUE_LENGTH: + case OID_SKGE_TRAP_NUMBER: + case OID_SKGE_MDB_VERSION: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_CHIPSET: + if (*pLen < sizeof(SK_U16)) { + + *pLen = sizeof(SK_U16); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_BUS_TYPE: + case OID_SKGE_BUS_SPEED: + case OID_SKGE_BUS_WIDTH: + case OID_SKGE_SENSOR_NUMBER: + case OID_SKGE_CHKSM_NUMBER: + if (*pLen < sizeof(SK_U8)) { + + *pLen = sizeof(SK_U8); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_TX_SW_QUEUE_LEN: + case OID_SKGE_TX_SW_QUEUE_MAX: + case OID_SKGE_TX_RETRY: + case OID_SKGE_RX_INTR_CTS: + case OID_SKGE_TX_INTR_CTS: + case OID_SKGE_RX_NO_BUF_CTS: + case OID_SKGE_TX_NO_BUF_CTS: + case OID_SKGE_TX_USED_DESCR_NO: + case OID_SKGE_RX_DELIVERED_CTS: + case OID_SKGE_RX_OCTETS_DELIV_CTS: + case OID_SKGE_RX_HW_ERROR_CTS: + case OID_SKGE_TX_HW_ERROR_CTS: + case OID_SKGE_IN_ERRORS_CTS: + case OID_SKGE_OUT_ERROR_CTS: + case OID_SKGE_ERR_RECOVERY_CTS: + case OID_SKGE_SYSUPTIME: + if (*pLen < sizeof(SK_U64)) { + + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + /* Checked later */ + break; + } + + /* Update statistic */ + if (Id == OID_SKGE_RX_HW_ERROR_CTS || + Id == OID_SKGE_TX_HW_ERROR_CTS || + Id == OID_SKGE_IN_ERRORS_CTS || + Id == OID_SKGE_OUT_ERROR_CTS || + Id == OID_GEN_XMIT_ERROR || + Id == OID_GEN_RCV_ERROR) { + + /* Force the XMAC to update its statistic counters and + * Increment semaphore to indicate that an update was + * already done. + */ + Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); + if (Ret != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Some OIDs consist of multiple hardware counters. Those + * values which are contained in all of them will be added + * now. + */ + switch (Id) { + + case OID_SKGE_RX_HW_ERROR_CTS: + case OID_SKGE_IN_ERRORS_CTS: + case OID_GEN_RCV_ERROR: + Val64RxHwErrs = + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_MISSED, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FRAMING, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_JABBER, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CARRIER, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex); + break; + + case OID_SKGE_TX_HW_ERROR_CTS: + case OID_SKGE_OUT_ERROR_CTS: + case OID_GEN_XMIT_ERROR: + Val64TxHwErrs = + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_EXCESS_COL, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_LATE_COL, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_UNDERRUN, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_CARRIER, NetIndex); + break; + } + } + + /* + * Retrieve value + */ + switch (Id) { + + case OID_SKGE_SUPPORTED_LIST: + Len = ID_TABLE_SIZE * sizeof(SK_U32); + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + for (Offset = 0, Index = 0; Offset < Len; + Offset += sizeof(SK_U32), Index ++) { + + Val32 = (SK_U32)IdTable[Index].Id; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + } + *pLen = Len; + break; + + case OID_SKGE_PORT_NUMBER: + Val32 = (SK_U32)pAC->GIni.GIMacsFound; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_DEVICE_TYPE: + Val32 = (SK_U32)pAC->Pnmi.DeviceType; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_DRIVER_DESCR: + if (pAC->Pnmi.pDriverDescription == NULL) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007, + SK_PNMI_ERR007MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1; + if (Len > SK_PNMI_STRINGLEN1) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029, + SK_PNMI_ERR029MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + *pBuf = (char)(Len - 1); + SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverDescription, Len - 1); + *pLen = Len; + break; + + case OID_SKGE_DRIVER_VERSION: + if (pAC->Pnmi.pDriverVersion == NULL) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030, + SK_PNMI_ERR030MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1; + if (Len > SK_PNMI_STRINGLEN1) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031, + SK_PNMI_ERR031MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + *pBuf = (char)(Len - 1); + SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverVersion, Len - 1); + *pLen = Len; + break; + + case OID_SKGE_HW_DESCR: + /* + * The hardware description is located in the VPD. This + * query may move to the initialisation routine. But + * the VPD data is cached and therefore a call here + * will not make much difference. + */ + Len = 256; + if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032, + SK_PNMI_ERR032MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + Len ++; + if (Len > SK_PNMI_STRINGLEN1) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033, + SK_PNMI_ERR033MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + *pBuf = (char)(Len - 1); + SK_MEMCPY(pBuf + 1, Buf, Len - 1); + *pLen = Len; + break; + + case OID_SKGE_HW_VERSION: + /* Oh, I love to do some string manipulation */ + if (*pLen < 5) { + + *pLen = 5; + return (SK_PNMI_ERR_TOO_SHORT); + } + Val8 = (SK_U8)pAC->GIni.GIPciHwRev; + pBuf[0] = 4; + pBuf[1] = 'v'; + pBuf[2] = (char)(0x30 | ((Val8 >> 4) & 0x0F)); + pBuf[3] = '.'; + pBuf[4] = (char)(0x30 | (Val8 & 0x0F)); + *pLen = 5; + break; + + case OID_SKGE_CHIPSET: + Val16 = pAC->Pnmi.Chipset; + SK_PNMI_STORE_U16(pBuf, Val16); + *pLen = sizeof(SK_U16); + break; + + case OID_SKGE_BUS_TYPE: + *pBuf = (char)SK_PNMI_BUS_PCI; + *pLen = sizeof(char); + break; + + case OID_SKGE_BUS_SPEED: + *pBuf = pAC->Pnmi.PciBusSpeed; + *pLen = sizeof(char); + break; + + case OID_SKGE_BUS_WIDTH: + *pBuf = pAC->Pnmi.PciBusWidth; + *pLen = sizeof(char); + break; + + case OID_SKGE_RESULT: + Val32 = pAC->Pnmi.TestResult; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_NUMBER: + *pBuf = (char)pAC->I2c.MaxSens; + *pLen = sizeof(char); + break; + + case OID_SKGE_CHKSM_NUMBER: + *pBuf = SKCS_NUM_PROTOCOLS; + *pLen = sizeof(char); + break; + + case OID_SKGE_TRAP_NUMBER: + GetTrapQueueLen(pAC, &Len, &Val); + Val32 = (SK_U32)Val; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_TRAP: + GetTrapQueueLen(pAC, &Len, &Val); + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + CopyTrapQueue(pAC, pBuf); + *pLen = Len; + break; + + case OID_SKGE_RLMT_MONITOR_NUMBER: +/* XXX Not yet implemented by RLMT therefore we return zero elements */ + Val32 = 0; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_TX_SW_QUEUE_LEN: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueLen; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen + + pAC->Pnmi.BufPort[1].TxSwQueueLen; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueLen; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxSwQueueLen + + pAC->Pnmi.Port[1].TxSwQueueLen; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + + case OID_SKGE_TX_SW_QUEUE_MAX: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueMax; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxSwQueueMax + + pAC->Pnmi.BufPort[1].TxSwQueueMax; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueMax; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxSwQueueMax + + pAC->Pnmi.Port[1].TxSwQueueMax; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_RETRY: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxRetryCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxRetryCts + + pAC->Pnmi.BufPort[1].TxRetryCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxRetryCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxRetryCts + + pAC->Pnmi.Port[1].TxRetryCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_INTR_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxIntrCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].RxIntrCts + + pAC->Pnmi.BufPort[1].RxIntrCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].RxIntrCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].RxIntrCts + + pAC->Pnmi.Port[1].RxIntrCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_INTR_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxIntrCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxIntrCts + + pAC->Pnmi.BufPort[1].TxIntrCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxIntrCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxIntrCts + + pAC->Pnmi.Port[1].TxIntrCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_NO_BUF_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].RxNoBufCts + + pAC->Pnmi.BufPort[1].RxNoBufCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].RxNoBufCts + + pAC->Pnmi.Port[1].RxNoBufCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_NO_BUF_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxNoBufCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxNoBufCts + + pAC->Pnmi.BufPort[1].TxNoBufCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxNoBufCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxNoBufCts + + pAC->Pnmi.Port[1].TxNoBufCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_USED_DESCR_NO: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxUsedDescrNo; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxUsedDescrNo + + pAC->Pnmi.BufPort[1].TxUsedDescrNo; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxUsedDescrNo; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxUsedDescrNo + + pAC->Pnmi.Port[1].TxUsedDescrNo; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_DELIVERED_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxDeliveredCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].RxDeliveredCts + + pAC->Pnmi.BufPort[1].RxDeliveredCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].RxDeliveredCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].RxDeliveredCts + + pAC->Pnmi.Port[1].RxDeliveredCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_OCTETS_DELIV_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxOctetsDeliveredCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].RxOctetsDeliveredCts + + pAC->Pnmi.BufPort[1].RxOctetsDeliveredCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].RxOctetsDeliveredCts + + pAC->Pnmi.Port[1].RxOctetsDeliveredCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_HW_ERROR_CTS: + SK_PNMI_STORE_U64(pBuf, Val64RxHwErrs); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_HW_ERROR_CTS: + SK_PNMI_STORE_U64(pBuf, Val64TxHwErrs); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_IN_ERRORS_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; + } + /* Single net mode */ + else { + Val64 = Val64RxHwErrs + + pAC->Pnmi.BufPort[0].RxNoBufCts + + pAC->Pnmi.BufPort[1].RxNoBufCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts; + } + /* Single net mode */ + else { + Val64 = Val64RxHwErrs + + pAC->Pnmi.Port[0].RxNoBufCts + + pAC->Pnmi.Port[1].RxNoBufCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_OUT_ERROR_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts; + } + /* Single net mode */ + else { + Val64 = Val64TxHwErrs + + pAC->Pnmi.BufPort[0].TxNoBufCts + + pAC->Pnmi.BufPort[1].TxNoBufCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts; + } + /* Single net mode */ + else { + Val64 = Val64TxHwErrs + + pAC->Pnmi.Port[0].TxNoBufCts + + pAC->Pnmi.Port[1].TxNoBufCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_ERR_RECOVERY_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].ErrRecoveryCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].ErrRecoveryCts + + pAC->Pnmi.BufPort[1].ErrRecoveryCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].ErrRecoveryCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].ErrRecoveryCts + + pAC->Pnmi.Port[1].ErrRecoveryCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_SYSUPTIME: + Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); + Val64 -= pAC->Pnmi.StartUpTime; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_MDB_VERSION: + Val32 = SK_PNMI_MDB_VERSION; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_GEN_RCV_ERROR: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; + } + else { + Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts; + } + + /* + * by default 32bit values are evaluated + */ + if (!Is64BitReq) { + Val32 = (SK_U32)Val64; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + } + else { + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + } + break; + + case OID_GEN_XMIT_ERROR: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts; + } + else { + Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts; + } + + /* + * by default 32bit values are evaluated + */ + if (!Is64BitReq) { + Val32 = (SK_U32)Val64; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + } + else { + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + } + break; + + case OID_GEN_RCV_NO_BUFFER: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; + } + else { + Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts; + } + + /* + * by default 32bit values are evaluated + */ + if (!Is64BitReq) { + Val32 = (SK_U32)Val64; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + } + else { + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + } + break; + + case OID_GEN_TRANSMIT_QUEUE_LENGTH: + Val32 = (SK_U32)pAC->Pnmi.Port[NetIndex].TxSwQueueLen; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034, + SK_PNMI_ERR034MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + if (Id == OID_SKGE_RX_HW_ERROR_CTS || + Id == OID_SKGE_TX_HW_ERROR_CTS || + Id == OID_SKGE_IN_ERRORS_CTS || + Id == OID_SKGE_OUT_ERROR_CTS || + Id == OID_GEN_XMIT_ERROR || + Id == OID_GEN_RCV_ERROR) { + + pAC->Pnmi.MacUpdatedFlag --; + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Rlmt - OID handler function of OID_SKGE_RLMT_XXX single instance. + * + * Description: + * Get/Presets/Sets the RLMT OIDs. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Rlmt( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int PhysPortIndex; + unsigned int PhysPortMax; + SK_EVPARA EventParam; + SK_U32 Val32; + SK_U64 Val64; + + + /* + * Check instance. Only single instance OIDs are allowed here. + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* + * Perform the requested action + */ + if (Action == SK_PNMI_GET) { + + /* + * Check if the buffer length is large enough. + */ + + switch (Id) { + + case OID_SKGE_RLMT_MODE: + case OID_SKGE_RLMT_PORT_ACTIVE: + case OID_SKGE_RLMT_PORT_PREFERRED: + if (*pLen < sizeof(SK_U8)) { + + *pLen = sizeof(SK_U8); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_RLMT_PORT_NUMBER: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_RLMT_CHANGE_CTS: + case OID_SKGE_RLMT_CHANGE_TIME: + case OID_SKGE_RLMT_CHANGE_ESTIM: + case OID_SKGE_RLMT_CHANGE_THRES: + if (*pLen < sizeof(SK_U64)) { + + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035, + SK_PNMI_ERR035MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Update RLMT statistic and increment semaphores to indicate + * that an update was already done. Maybe RLMT will hold its + * statistic always up to date some time. Then we can + * remove this type of call. + */ + if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.RlmtUpdatedFlag ++; + + /* + * Retrieve Value + */ + switch (Id) { + + case OID_SKGE_RLMT_MODE: + *pBuf = (char)pAC->Rlmt.Net[0].RlmtMode; + *pLen = sizeof(char); + break; + + case OID_SKGE_RLMT_PORT_NUMBER: + Val32 = (SK_U32)pAC->GIni.GIMacsFound; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_RLMT_PORT_ACTIVE: + *pBuf = 0; + /* + * If multiple ports may become active this OID + * doesn't make sense any more. A new variable in + * the port structure should be created. However, + * for this variable the first active port is + * returned. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(PhysPortIndex); + break; + } + } + *pLen = sizeof(char); + break; + + case OID_SKGE_RLMT_PORT_PREFERRED: + *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(pAC->Rlmt.Net[NetIndex].Preference); + *pLen = sizeof(char); + break; + + case OID_SKGE_RLMT_CHANGE_CTS: + Val64 = pAC->Pnmi.RlmtChangeCts; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_CHANGE_TIME: + Val64 = pAC->Pnmi.RlmtChangeTime; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_CHANGE_ESTIM: + Val64 = pAC->Pnmi.RlmtChangeEstimate.Estimate; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_CHANGE_THRES: + Val64 = pAC->Pnmi.RlmtChangeThreshold; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("Rlmt: Unknown OID should be handled before")); + + pAC->Pnmi.RlmtUpdatedFlag --; + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + pAC->Pnmi.RlmtUpdatedFlag --; + } + else { + /* Perform a preset or set */ + switch (Id) { + + case OID_SKGE_RLMT_MODE: + /* Check if the buffer length is plausible */ + if (*pLen < sizeof(char)) { + + *pLen = sizeof(char); + return (SK_PNMI_ERR_TOO_SHORT); + } + /* Check if the value range is correct */ + if (*pLen != sizeof(char) || + (*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 || + *(SK_U8 *)pBuf > 15) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + *pLen = 0; + return (SK_PNMI_ERR_OK); + } + /* Send an event to RLMT to change the mode */ + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] |= (SK_U32)(*pBuf); + EventParam.Para32[1] = 0; + if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037, + SK_PNMI_ERR037MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + break; + + case OID_SKGE_RLMT_PORT_PREFERRED: + /* Check if the buffer length is plausible */ + if (*pLen < sizeof(char)) { + + *pLen = sizeof(char); + return (SK_PNMI_ERR_TOO_SHORT); + } + /* Check if the value range is correct */ + if (*pLen != sizeof(char) || *(SK_U8 *)pBuf > + (SK_U8)pAC->GIni.GIMacsFound) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + *pLen = 0; + return (SK_PNMI_ERR_OK); + } + + /* + * Send an event to RLMT change the preferred port. + * A param of -1 means automatic mode. RLMT will + * make the decision which is the preferred port. + */ + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] = (SK_U32)(*pBuf) - 1; + EventParam.Para32[1] = NetIndex; + if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038, + SK_PNMI_ERR038MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + break; + + case OID_SKGE_RLMT_CHANGE_THRES: + /* Check if the buffer length is plausible */ + if (*pLen < sizeof(SK_U64)) { + + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + /* + * There are not many restrictions to the + * value range. + */ + if (*pLen != sizeof(SK_U64)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + /* A preset ends here */ + if (Action == SK_PNMI_PRESET) { + + *pLen = 0; + return (SK_PNMI_ERR_OK); + } + /* + * Store the new threshold, which will be taken + * on the next timer event. + */ + SK_PNMI_READ_U64(pBuf, Val64); + pAC->Pnmi.RlmtChangeThreshold = Val64; + break; + + default: + /* The other OIDs are not be able for set */ + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * RlmtStat - OID handler function of OID_SKGE_RLMT_XXX multiple instance. + * + * Description: + * Performs get requests on multiple instance variables. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int RlmtStat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int PhysPortMax; + unsigned int PhysPortIndex; + unsigned int Limit; + unsigned int Offset; + int Ret; + SK_U32 Val32; + SK_U64 Val64; + + /* + * Calculate the port indexes from the instance + */ + PhysPortMax = pAC->GIni.GIMacsFound; + + if ((Instance != (SK_U32)(-1))) { + /* Check instance range */ + if ((Instance < 1) || (Instance > PhysPortMax)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* Single net mode */ + PhysPortIndex = Instance - 1; + + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + PhysPortIndex = NetIndex; + } + + /* Both net modes */ + Limit = PhysPortIndex + 1; + } + else { + /* Single net mode */ + PhysPortIndex = 0; + Limit = PhysPortMax; + + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + PhysPortIndex = NetIndex; + Limit = PhysPortIndex + 1; + } + } + + /* + * Currently only get requests are allowed. + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check if the buffer length is large enough. + */ + switch (Id) { + + case OID_SKGE_RLMT_PORT_INDEX: + case OID_SKGE_RLMT_STATUS: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) { + + *pLen = (Limit - PhysPortIndex) * sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_RLMT_TX_HELLO_CTS: + case OID_SKGE_RLMT_RX_HELLO_CTS: + case OID_SKGE_RLMT_TX_SP_REQ_CTS: + case OID_SKGE_RLMT_RX_SP_CTS: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U64)) { + + *pLen = (Limit - PhysPortIndex) * sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039, + SK_PNMI_ERR039MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + + } + + /* + * Update statistic and increment semaphores to indicate that + * an update was already done. + */ + if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.RlmtUpdatedFlag ++; + + /* + * Get value + */ + Offset = 0; + for (; PhysPortIndex < Limit; PhysPortIndex ++) { + + switch (Id) { + + case OID_SKGE_RLMT_PORT_INDEX: + Val32 = PhysPortIndex; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_RLMT_STATUS: + if (pAC->Rlmt.Port[PhysPortIndex].PortState == + SK_RLMT_PS_INIT || + pAC->Rlmt.Port[PhysPortIndex].PortState == + SK_RLMT_PS_DOWN) { + + Val32 = SK_PNMI_RLMT_STATUS_ERROR; + } + else if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + Val32 = SK_PNMI_RLMT_STATUS_ACTIVE; + } + else { + Val32 = SK_PNMI_RLMT_STATUS_STANDBY; + } + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_RLMT_TX_HELLO_CTS: + Val64 = pAC->Rlmt.Port[PhysPortIndex].TxHelloCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_RX_HELLO_CTS: + Val64 = pAC->Rlmt.Port[PhysPortIndex].RxHelloCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_TX_SP_REQ_CTS: + Val64 = pAC->Rlmt.Port[PhysPortIndex].TxSpHelloReqCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_RX_SP_CTS: + Val64 = pAC->Rlmt.Port[PhysPortIndex].RxSpHelloCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("RlmtStat: Unknown OID should be errored before")); + + pAC->Pnmi.RlmtUpdatedFlag --; + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + *pLen = Offset; + + pAC->Pnmi.RlmtUpdatedFlag --; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * MacPrivateConf - OID handler function of OIDs concerning the configuration + * + * Description: + * Get/Presets/Sets the OIDs concerning the configuration. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int MacPrivateConf( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int PhysPortMax; + unsigned int PhysPortIndex; + unsigned int LogPortMax; + unsigned int LogPortIndex; + unsigned int Limit; + unsigned int Offset; + char Val8; + int Ret; + SK_EVPARA EventParam; + SK_U32 Val32; + + + /* + * Calculate instance if wished. MAC index 0 is the virtual + * MAC. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + LogPortMax--; + } + + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */ + /* Check instance range */ + if ((Instance < 1) || (Instance > LogPortMax)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance); + Limit = LogPortIndex + 1; + } + + else { /* Instance == (SK_U32)(-1), get all Instances of that OID */ + + LogPortIndex = 0; + Limit = LogPortMax; + } + + /* + * Perform action + */ + if (Action == SK_PNMI_GET) { + + /* + * Check length + */ + switch (Id) { + + case OID_SKGE_PMD: + case OID_SKGE_CONNECTOR: + case OID_SKGE_LINK_CAP: + case OID_SKGE_LINK_MODE: + case OID_SKGE_LINK_MODE_STATUS: + case OID_SKGE_LINK_STATUS: + case OID_SKGE_FLOWCTRL_CAP: + case OID_SKGE_FLOWCTRL_MODE: + case OID_SKGE_FLOWCTRL_STATUS: + case OID_SKGE_PHY_OPERATION_CAP: + case OID_SKGE_PHY_OPERATION_MODE: + case OID_SKGE_PHY_OPERATION_STATUS: + case OID_SKGE_SPEED_CAP: + case OID_SKGE_SPEED_MODE: + case OID_SKGE_SPEED_STATUS: + if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) { + + *pLen = (Limit - LogPortIndex) * + sizeof(SK_U8); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_MTU: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041, + SK_PNMI_ERR041MSG); + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Update statistic and increment semaphore to indicate + * that an update was already done. + */ + if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.SirqUpdatedFlag ++; + + /* + * Get value + */ + Offset = 0; + for (; LogPortIndex < Limit; LogPortIndex ++) { + + switch (Id) { + + case OID_SKGE_PMD: + *(pBuf + Offset) = pAC->Pnmi.PMD; + Offset += sizeof(char); + break; + + case OID_SKGE_CONNECTOR: + *(pBuf + Offset) = pAC->Pnmi.Connector; + Offset += sizeof(char); + break; + + case OID_SKGE_LINK_CAP: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkCap; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkCap; + Offset += sizeof(char); + } + break; + + case OID_SKGE_LINK_MODE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkModeConf; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkModeConf; + Offset += sizeof(char); + } + break; + + case OID_SKGE_LINK_MODE_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = + CalculateLinkModeStatus(pAC, + IoC, PhysPortIndex); + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + *(pBuf + Offset) = CalculateLinkModeStatus(pAC, IoC, NetIndex); + Offset += sizeof(char); + } + break; + + case OID_SKGE_LINK_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = + CalculateLinkStatus(pAC, + IoC, PhysPortIndex); + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = CalculateLinkStatus(pAC, IoC, NetIndex); + Offset += sizeof(char); + } + break; + + case OID_SKGE_FLOWCTRL_CAP: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PFlowCtrlCap; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlCap; + Offset += sizeof(char); + } + break; + + case OID_SKGE_FLOWCTRL_MODE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PFlowCtrlMode; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlMode; + Offset += sizeof(char); + } + break; + + case OID_SKGE_FLOWCTRL_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PFlowCtrlStatus; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlStatus; + Offset += sizeof(char); + } + break; + + case OID_SKGE_PHY_OPERATION_CAP: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PMSCap; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSCap; + Offset += sizeof(char); + } + break; + + case OID_SKGE_PHY_OPERATION_MODE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PMSMode; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSMode; + Offset += sizeof(char); + } + break; + + case OID_SKGE_PHY_OPERATION_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PMSStatus; + } + Offset += sizeof(char); + } + else { + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSStatus; + Offset += sizeof(char); + } + break; + + case OID_SKGE_SPEED_CAP: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkSpeedCap; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeedCap; + Offset += sizeof(char); + } + break; + + case OID_SKGE_SPEED_MODE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkSpeed; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeed; + Offset += sizeof(char); + } + break; + + case OID_SKGE_SPEED_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkSpeedUsed; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeedUsed; + Offset += sizeof(char); + } + break; + + case OID_SKGE_MTU: + Val32 = SK_DRIVER_GET_MTU(pAC, IoC, NetIndex); + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("MacPrivateConf: Unknown OID should be handled before")); + + pAC->Pnmi.SirqUpdatedFlag --; + return (SK_PNMI_ERR_GENERAL); + } + } + *pLen = Offset; + pAC->Pnmi.SirqUpdatedFlag --; + + return (SK_PNMI_ERR_OK); + } + + /* + * From here SET or PRESET action. Check if the passed + * buffer length is plausible. + */ + switch (Id) { + + case OID_SKGE_LINK_MODE: + case OID_SKGE_FLOWCTRL_MODE: + case OID_SKGE_PHY_OPERATION_MODE: + case OID_SKGE_SPEED_MODE: + if (*pLen < Limit - LogPortIndex) { + + *pLen = Limit - LogPortIndex; + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen != Limit - LogPortIndex) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + break; + + case OID_SKGE_MTU: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen != sizeof(SK_U32)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Perform preset or set + */ + Offset = 0; + for (; LogPortIndex < Limit; LogPortIndex ++) { + + switch (Id) { + + case OID_SKGE_LINK_MODE: + /* Check the value range */ + Val8 = *(pBuf + Offset); + if (Val8 == 0) { + + Offset += sizeof(char); + break; + } + if (Val8 < SK_LMODE_HALF || + (LogPortIndex != 0 && Val8 > SK_LMODE_AUTOSENSE) || + (LogPortIndex == 0 && Val8 > SK_LMODE_INDETERMINATED)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + if (LogPortIndex == 0) { + + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with the new link mode to SIRQ. + */ + for (PhysPortIndex = 0; + PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (!pAC->Pnmi.Port[PhysPortIndex]. + ActiveFlag) { + + continue; + } + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_LMODE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR043, + SK_PNMI_ERR043MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + } + else { + /* + * Send an event with the new link mode to + * the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR043, + SK_PNMI_ERR043MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + Offset += sizeof(char); + break; + + case OID_SKGE_FLOWCTRL_MODE: + /* Check the value range */ + Val8 = *(pBuf + Offset); + if (Val8 == 0) { + + Offset += sizeof(char); + break; + } + if (Val8 < SK_FLOW_MODE_NONE || + (LogPortIndex != 0 && Val8 > SK_FLOW_MODE_SYM_OR_REM) || + (LogPortIndex == 0 && Val8 > SK_FLOW_MODE_INDETERMINATED)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + if (LogPortIndex == 0) { + + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with the new flow control mode to SIRQ. + */ + for (PhysPortIndex = 0; + PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (!pAC->Pnmi.Port[PhysPortIndex]. + ActiveFlag) { + + continue; + } + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_FLOWMODE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR044, + SK_PNMI_ERR044MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + } + else { + /* + * Send an event with the new flow control + * mode to the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_FLOWMODE, EventParam) + > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR044, + SK_PNMI_ERR044MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + Offset += sizeof(char); + break; + + case OID_SKGE_PHY_OPERATION_MODE : + /* Check the value range */ + Val8 = *(pBuf + Offset); + if (Val8 == 0) { + /* mode of this port remains unchanged */ + Offset += sizeof(char); + break; + } + if (Val8 < SK_MS_MODE_AUTO || + (LogPortIndex != 0 && Val8 > SK_MS_MODE_SLAVE) || + (LogPortIndex == 0 && Val8 > SK_MS_MODE_INDETERMINATED)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + if (LogPortIndex == 0) { + + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with new master/slave (role) mode to SIRQ. + */ + for (PhysPortIndex = 0; + PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (!pAC->Pnmi.Port[PhysPortIndex]. + ActiveFlag) { + + continue; + } + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_ROLE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR042, + SK_PNMI_ERR042MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + } + else { + /* + * Send an event with the new master/slave + * (role) mode to the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_ROLE, EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR042, + SK_PNMI_ERR042MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + + Offset += sizeof(char); + break; + + case OID_SKGE_SPEED_MODE: + /* Check the value range */ + Val8 = *(pBuf + Offset); + if (Val8 == 0) { + + Offset += sizeof(char); + break; + } + if (Val8 < (SK_LSPEED_AUTO) || + (LogPortIndex != 0 && Val8 > (SK_LSPEED_1000MBPS)) || + (LogPortIndex == 0 && Val8 > (SK_LSPEED_INDETERMINATED))) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + if (LogPortIndex == 0) { + + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with the new flow control mode to SIRQ. + */ + for (PhysPortIndex = 0; + PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + continue; + } + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_SPEED, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR045, + SK_PNMI_ERR045MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + } + else { + /* + * Send an event with the new flow control + * mode to the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_SPEED, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR045, + SK_PNMI_ERR045MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + Offset += sizeof(char); + break; + + case OID_SKGE_MTU : + /* Check the value range */ + Val32 = *(SK_U32*)(pBuf + Offset); + if (Val32 == 0) { + /* mtu of this port remains unchanged */ + Offset += sizeof(SK_U32); + break; + } + if (SK_DRIVER_PRESET_MTU(pAC, IoC, NetIndex, Val32) != 0) { + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + return (SK_PNMI_ERR_OK); + } + + if (SK_DRIVER_SET_MTU(pAC, IoC, NetIndex, Val32) != 0) { + return (SK_PNMI_ERR_GENERAL); + } + + Offset += sizeof(SK_U32); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("MacPrivateConf: Unknown OID should be handled before set")); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Monitor - OID handler function for RLMT_MONITOR_XXX + * + * Description: + * Because RLMT currently does not support the monitoring of + * remote adapter cards, we return always an empty table. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Monitor( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int Index; + unsigned int Limit; + unsigned int Offset; + unsigned int Entries; + + + /* + * Calculate instance if wished. + */ +/* XXX Not yet implemented. Return always an empty table. */ + Entries = 0; + + if ((Instance != (SK_U32)(-1))) { + + if ((Instance < 1) || (Instance > Entries)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + Index = (unsigned int)Instance - 1; + Limit = (unsigned int)Instance; + } + else { + Index = 0; + Limit = Entries; + } + + /* + * Get/Set value + */ + if (Action == SK_PNMI_GET) { + + for (Offset=0; Index < Limit; Index ++) { + + switch (Id) { + + case OID_SKGE_RLMT_MONITOR_INDEX: + case OID_SKGE_RLMT_MONITOR_ADDR: + case OID_SKGE_RLMT_MONITOR_ERRS: + case OID_SKGE_RLMT_MONITOR_TIMESTAMP: + case OID_SKGE_RLMT_MONITOR_ADMIN: + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR046, + SK_PNMI_ERR046MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + *pLen = Offset; + } + else { + /* Only MONITOR_ADMIN can be set */ + if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* Check if the length is plausible */ + if (*pLen < (Limit - Index)) { + + return (SK_PNMI_ERR_TOO_SHORT); + } + /* Okay, we have a wide value range */ + if (*pLen != (Limit - Index)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } +/* + for (Offset=0; Index < Limit; Index ++) { + } +*/ +/* + * XXX Not yet implemented. Return always BAD_VALUE, because the table + * is empty. + */ + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * VirtualConf - Calculates the values of configuration OIDs for virtual port + * + * Description: + * We handle here the get of the configuration group OIDs, which are + * a little bit complicated. The virtual port consists of all currently + * active physical ports. If multiple ports are active and configured + * differently we get in some trouble to return a single value. So we + * get the value of the first active port and compare it with that of + * the other active ports. If they are not the same, we return a value + * that indicates that the state is indeterminated. + * + * Returns: + * Nothing + */ +PNMI_STATIC void VirtualConf( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf) /* Buffer to which to mgmt data will be retrieved */ +{ + unsigned int PhysPortMax; + unsigned int PhysPortIndex; + SK_U8 Val8; + SK_BOOL PortActiveFlag; + + + *pBuf = 0; + PortActiveFlag = SK_FALSE; + PhysPortMax = pAC->GIni.GIMacsFound; + + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + /* Check if the physical port is active */ + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + continue; + } + + PortActiveFlag = SK_TRUE; + + switch (Id) { + + case OID_SKGE_LINK_CAP: + + /* + * Different capabilities should not happen, but + * in the case of the cases OR them all together. + * From a curious point of view the virtual port + * is capable of all found capabilities. + */ + *pBuf |= pAC->GIni.GP[PhysPortIndex].PLinkCap; + break; + + case OID_SKGE_LINK_MODE: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PLinkModeConf; + continue; + } + + /* + * If we find an active port with a different link + * mode than the first one we return a value that + * indicates that the link mode is indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkModeConf + ) { + + *pBuf = SK_LMODE_INDETERMINATED; + } + break; + + case OID_SKGE_LINK_MODE_STATUS: + /* Get the link mode of the physical port */ + Val8 = CalculateLinkModeStatus(pAC, IoC, PhysPortIndex); + + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = Val8; + continue; + } + + /* + * If we find an active port with a different link + * mode status than the first one we return a value + * that indicates that the link mode status is + * indeterminated. + */ + if (*pBuf != Val8) { + + *pBuf = SK_LMODE_STAT_INDETERMINATED; + } + break; + + case OID_SKGE_LINK_STATUS: + /* Get the link status of the physical port */ + Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex); + + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = Val8; + continue; + } + + /* + * If we find an active port with a different link + * status than the first one, we return a value + * that indicates that the link status is + * indeterminated. + */ + if (*pBuf != Val8) { + + *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED; + } + break; + + case OID_SKGE_FLOWCTRL_CAP: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap; + continue; + } + + /* + * From a curious point of view the virtual port + * is capable of all found capabilities. + */ + *pBuf |= pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap; + break; + + case OID_SKGE_FLOWCTRL_MODE: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode; + continue; + } + + /* + * If we find an active port with a different flow + * control mode than the first one, we return a value + * that indicates that the mode is indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode) { + + *pBuf = SK_FLOW_MODE_INDETERMINATED; + } + break; + + case OID_SKGE_FLOWCTRL_STATUS: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus; + continue; + } + + /* + * If we find an active port with a different flow + * control status than the first one, we return a + * value that indicates that the status is + * indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus) { + + *pBuf = SK_FLOW_STAT_INDETERMINATED; + } + break; + + case OID_SKGE_PHY_OPERATION_CAP: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PMSCap; + continue; + } + + /* + * From a curious point of view the virtual port + * is capable of all found capabilities. + */ + *pBuf |= pAC->GIni.GP[PhysPortIndex].PMSCap; + break; + + case OID_SKGE_PHY_OPERATION_MODE: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PMSMode; + continue; + } + + /* + * If we find an active port with a different master/ + * slave mode than the first one, we return a value + * that indicates that the mode is indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PMSMode) { + + *pBuf = SK_MS_MODE_INDETERMINATED; + } + break; + + case OID_SKGE_PHY_OPERATION_STATUS: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PMSStatus; + continue; + } + + /* + * If we find an active port with a different master/ + * slave status than the first one, we return a + * value that indicates that the status is + * indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PMSStatus) { + + *pBuf = SK_MS_STAT_INDETERMINATED; + } + break; + + case OID_SKGE_SPEED_MODE: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PLinkSpeed; + continue; + } + + /* + * If we find an active port with a different flow + * control mode than the first one, we return a value + * that indicates that the mode is indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkSpeed) { + + *pBuf = SK_LSPEED_INDETERMINATED; + } + break; + + case OID_SKGE_SPEED_STATUS: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed; + continue; + } + + /* + * If we find an active port with a different flow + * control status than the first one, we return a + * value that indicates that the status is + * indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed) { + + *pBuf = SK_LSPEED_STAT_INDETERMINATED; + } + break; + } + } + + /* + * If no port is active return an indeterminated answer + */ + if (!PortActiveFlag) { + + switch (Id) { + + case OID_SKGE_LINK_CAP: + *pBuf = SK_LMODE_CAP_INDETERMINATED; + break; + + case OID_SKGE_LINK_MODE: + *pBuf = SK_LMODE_INDETERMINATED; + break; + + case OID_SKGE_LINK_MODE_STATUS: + *pBuf = SK_LMODE_STAT_INDETERMINATED; + break; + + case OID_SKGE_LINK_STATUS: + *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED; + break; + + case OID_SKGE_FLOWCTRL_CAP: + case OID_SKGE_FLOWCTRL_MODE: + *pBuf = SK_FLOW_MODE_INDETERMINATED; + break; + + case OID_SKGE_FLOWCTRL_STATUS: + *pBuf = SK_FLOW_STAT_INDETERMINATED; + break; + + case OID_SKGE_PHY_OPERATION_CAP: + *pBuf = SK_MS_CAP_INDETERMINATED; + break; + + case OID_SKGE_PHY_OPERATION_MODE: + *pBuf = SK_MS_MODE_INDETERMINATED; + break; + + case OID_SKGE_PHY_OPERATION_STATUS: + *pBuf = SK_MS_STAT_INDETERMINATED; + break; + case OID_SKGE_SPEED_CAP: + *pBuf = SK_LSPEED_CAP_INDETERMINATED; + break; + + case OID_SKGE_SPEED_MODE: + *pBuf = SK_LSPEED_INDETERMINATED; + break; + + case OID_SKGE_SPEED_STATUS: + *pBuf = SK_LSPEED_STAT_INDETERMINATED; + break; + } + } +} + +/***************************************************************************** + * + * CalculateLinkStatus - Determins the link status of a physical port + * + * Description: + * Determins the link status the following way: + * LSTAT_PHY_DOWN: Link is down + * LSTAT_AUTONEG: Auto-negotiation failed + * LSTAT_LOG_DOWN: Link is up but RLMT did not yet put the port + * logically up. + * LSTAT_LOG_UP: RLMT marked the port as up + * + * Returns: + * Link status of physical port + */ +PNMI_STATIC SK_U8 CalculateLinkStatus( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int PhysPortIndex) /* Physical port index */ +{ + SK_U8 Result; + + + if (!pAC->GIni.GP[PhysPortIndex].PHWLinkUp) { + + Result = SK_PNMI_RLMT_LSTAT_PHY_DOWN; + } + else if (pAC->GIni.GP[PhysPortIndex].PAutoNegFail > 0) { + + Result = SK_PNMI_RLMT_LSTAT_AUTONEG; + } + else if (!pAC->Rlmt.Port[PhysPortIndex].PortDown) { + + Result = SK_PNMI_RLMT_LSTAT_LOG_UP; + } + else { + Result = SK_PNMI_RLMT_LSTAT_LOG_DOWN; + } + + return (Result); +} + +/***************************************************************************** + * + * CalculateLinkModeStatus - Determins the link mode status of a phys. port + * + * Description: + * The COMMON module only tells us if the mode is half or full duplex. + * But in the decade of auto sensing it is usefull for the user to + * know if the mode was negotiated or forced. Therefore we have a + * look to the mode, which was last used by the negotiation process. + * + * Returns: + * The link mode status + */ +PNMI_STATIC SK_U8 CalculateLinkModeStatus( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int PhysPortIndex) /* Physical port index */ +{ + SK_U8 Result; + + + /* Get the current mode, which can be full or half duplex */ + Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus; + + /* Check if no valid mode could be found (link is down) */ + if (Result < SK_LMODE_STAT_HALF) { + + Result = SK_LMODE_STAT_UNKNOWN; + } + else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) { + + /* + * Auto-negotiation was used to bring up the link. Change + * the already found duplex status that it indicates + * auto-negotiation was involved. + */ + if (Result == SK_LMODE_STAT_HALF) { + + Result = SK_LMODE_STAT_AUTOHALF; + } + else if (Result == SK_LMODE_STAT_FULL) { + + Result = SK_LMODE_STAT_AUTOFULL; + } + } + + return (Result); +} + +/***************************************************************************** + * + * GetVpdKeyArr - Obtain an array of VPD keys + * + * Description: + * Read the VPD keys and build an array of VPD keys, which are + * easy to access. + * + * Returns: + * SK_PNMI_ERR_OK Task successfully performed. + * SK_PNMI_ERR_GENERAL Something went wrong. + */ +PNMI_STATIC int GetVpdKeyArr( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +char *pKeyArr, /* Ptr KeyArray */ +unsigned int KeyArrLen, /* Length of array in bytes */ +unsigned int *pKeyNo) /* Number of keys */ +{ + unsigned int BufKeysLen = SK_PNMI_VPD_BUFSIZE; + char BufKeys[SK_PNMI_VPD_BUFSIZE]; + unsigned int StartOffset; + unsigned int Offset; + int Index; + int Ret; + + + SK_MEMSET(pKeyArr, 0, KeyArrLen); + + /* + * Get VPD key list + */ + Ret = VpdKeys(pAC, IoC, (char *)&BufKeys, (int *)&BufKeysLen, + (int *)pKeyNo); + if (Ret > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR014, + SK_PNMI_ERR014MSG); + + return (SK_PNMI_ERR_GENERAL); + } + /* If no keys are available return now */ + if (*pKeyNo == 0 || BufKeysLen == 0) { + + return (SK_PNMI_ERR_OK); + } + /* + * If the key list is too long for us trunc it and give a + * errorlog notification. This case should not happen because + * the maximum number of keys is limited due to RAM limitations + */ + if (*pKeyNo > SK_PNMI_VPD_ENTRIES) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR015, + SK_PNMI_ERR015MSG); + + *pKeyNo = SK_PNMI_VPD_ENTRIES; + } + + /* + * Now build an array of fixed string length size and copy + * the keys together. + */ + for (Index = 0, StartOffset = 0, Offset = 0; Offset < BufKeysLen; + Offset ++) { + + if (BufKeys[Offset] != 0) { + + continue; + } + + if (Offset - StartOffset > SK_PNMI_VPD_KEY_SIZE) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR016, + SK_PNMI_ERR016MSG); + return (SK_PNMI_ERR_GENERAL); + } + + SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE, + &BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE); + + Index ++; + StartOffset = Offset + 1; + } + + /* Last key not zero terminated? Get it anyway */ + if (StartOffset < Offset) { + + SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE, + &BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * SirqUpdate - Let the SIRQ update its internal values + * + * Description: + * Just to be sure that the SIRQ module holds its internal data + * structures up to date, we send an update event before we make + * any access. + * + * Returns: + * SK_PNMI_ERR_OK Task successfully performed. + * SK_PNMI_ERR_GENERAL Something went wrong. + */ +PNMI_STATIC int SirqUpdate( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC) /* IO context handle */ +{ + SK_EVPARA EventParam; + + + /* Was the module already updated during the current PNMI call? */ + if (pAC->Pnmi.SirqUpdatedFlag > 0) { + + return (SK_PNMI_ERR_OK); + } + + /* Send an synchronuous update event to the module */ + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047, + SK_PNMI_ERR047MSG); + + return (SK_PNMI_ERR_GENERAL); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * RlmtUpdate - Let the RLMT update its internal values + * + * Description: + * Just to be sure that the RLMT module holds its internal data + * structures up to date, we send an update event before we make + * any access. + * + * Returns: + * SK_PNMI_ERR_OK Task successfully performed. + * SK_PNMI_ERR_GENERAL Something went wrong. + */ +PNMI_STATIC int RlmtUpdate( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_EVPARA EventParam; + + + /* Was the module already updated during the current PNMI call? */ + if (pAC->Pnmi.RlmtUpdatedFlag > 0) { + + return (SK_PNMI_ERR_OK); + } + + /* Send an synchronuous update event to the module */ + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] = NetIndex; + EventParam.Para32[1] = (SK_U32)-1; + if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048, + SK_PNMI_ERR048MSG); + + return (SK_PNMI_ERR_GENERAL); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * MacUpdate - Force the XMAC to output the current statistic + * + * Description: + * The XMAC holds its statistic internally. To obtain the current + * values we send a command so that the statistic data will + * be written to apredefined memory area on the adapter. + * + * Returns: + * SK_PNMI_ERR_OK Task successfully performed. + * SK_PNMI_ERR_GENERAL Something went wrong. + */ +PNMI_STATIC int MacUpdate( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int FirstMac, /* Index of the first Mac to be updated */ +unsigned int LastMac) /* Index of the last Mac to be updated */ +{ + unsigned int MacIndex; + + /* + * Were the statistics already updated during the + * current PNMI call? + */ + if (pAC->Pnmi.MacUpdatedFlag > 0) { + + return (SK_PNMI_ERR_OK); + } + + /* Send an update command to all MACs specified */ + for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) { + + /* + * 2002-09-13 pweber: Freeze the current sw counters. + * (That should be done as close as + * possible to the update of the + * hw counters) + */ + if (pAC->GIni.GIMacType == SK_MAC_XMAC) { + pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex]; + } + + /* 2002-09-13 pweber: Update the hw counter */ + if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) { + + return (SK_PNMI_ERR_GENERAL); + } + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * GetStatVal - Retrieve an XMAC statistic counter + * + * Description: + * Retrieves the statistic counter of a virtual or physical port. The + * virtual port is identified by the index 0. It consists of all + * currently active ports. To obtain the counter value for this port + * we must add the statistic counter of all active ports. To grant + * continuous counter values for the virtual port even when port + * switches occur we must additionally add a delta value, which was + * calculated during a SK_PNMI_EVT_RLMT_ACTIVE_UP event. + * + * Returns: + * Requested statistic value + */ +PNMI_STATIC SK_U64 GetStatVal( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int LogPortIndex, /* Index of the logical Port to be processed */ +unsigned int StatIndex, /* Index to statistic value */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int PhysPortIndex; + unsigned int PhysPortMax; + SK_U64 Val = 0; + + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + + PhysPortIndex = NetIndex; + Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex); + } + else { /* Single Net mode */ + + if (LogPortIndex == 0) { + + PhysPortMax = pAC->GIni.GIMacsFound; + + /* Add counter of all active ports */ + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + Val += GetPhysStatVal(pAC, IoC, PhysPortIndex, + StatIndex); + } + } + + /* Correct value because of port switches */ + Val += pAC->Pnmi.VirtualCounterOffset[StatIndex]; + } + else { + /* Get counter value of physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); + Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex); + } + } + return (Val); +} + +/***************************************************************************** + * + * GetPhysStatVal - Get counter value for physical port + * + * Description: + * Builds a 64bit counter value. Except for the octet counters + * the lower 32bit are counted in hardware and the upper 32bit + * in software by monitoring counter overflow interrupts in the + * event handler. To grant continous counter values during XMAC + * resets (caused by a workaround) we must add a delta value. + * The delta was calculated in the event handler when a + * SK_PNMI_EVT_XMAC_RESET was received. + * + * Returns: + * Counter value + */ +PNMI_STATIC SK_U64 GetPhysStatVal( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int PhysPortIndex, /* Index of the logical Port to be processed */ +unsigned int StatIndex) /* Index to statistic value */ +{ + SK_U64 Val = 0; + SK_U32 LowVal = 0; + SK_U32 HighVal = 0; + SK_U16 Word; + int MacType; + + SK_PNMI_PORT *pPnmiPrt; + SK_GEMACFUNC *pFnMac; + + MacType = pAC->GIni.GIMacType; + + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (pAC->GIni.GIMacType == SK_MAC_XMAC) { + pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex]; + } + else { + pPnmiPrt = &pAC->Pnmi.Port[PhysPortIndex]; + } + + pFnMac = &pAC->GIni.GIFunc; + + switch (StatIndex) { + case SK_PNMI_HTX: + case SK_PNMI_HRX: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HTX_OCTET: + case SK_PNMI_HRX_OCTET: + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &HighVal); + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex + 1][MacType].Reg, + &LowVal); + break; + + case SK_PNMI_HTX_BURST: + case SK_PNMI_HTX_EXCESS_DEF: + case SK_PNMI_HTX_CARRIER: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HTX_MACC: + /* GMAC only supports PAUSE MAC control frames */ + if (MacType == SK_MAC_GMAC) { + Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, SK_PNMI_HTX_PMACC); + + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HTX_COL: + case SK_PNMI_HRX_UNDERSIZE: + /* Not supported by XMAC */ + if (MacType == SK_MAC_XMAC) { + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + + case SK_PNMI_HTX_DEFFERAL: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + return (Val); + } + + /* + * XMAC counts frames with deferred transmission + * even in full-duplex mode. + * + * In full-duplex mode the counter remains constant! + */ + if ((pAC->GIni.GP[PhysPortIndex].PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) || + (pAC->GIni.GP[PhysPortIndex].PLinkModeStatus == SK_LMODE_STAT_FULL)) { + + LowVal = 0; + HighVal = 0; + } + else { + /* Otherwise get contents of hardware register. */ + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[SK_PNMI_HTX_DEFFERAL][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + } + break; + + case SK_PNMI_HRX_BADOCTET: + /* Not supported by XMAC */ + if (MacType == SK_MAC_XMAC) { + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &HighVal); + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex + 1][MacType].Reg, + &LowVal); + break; + + case SK_PNMI_HTX_OCTETLOW: + case SK_PNMI_HRX_OCTETLOW: + case SK_PNMI_HRX_BADOCTETLOW: + return (Val); + + case SK_PNMI_HRX_LONGFRAMES: + /* For XMAC the SW counter is managed by PNMI */ + if (MacType == SK_MAC_XMAC) { + return (pPnmiPrt->StatRxLongFrameCts); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HRX_TOO_LONG: + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + + Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal); + + switch (MacType) { + case SK_MAC_GMAC: + /* For GMAC the SW counter is additionally managed by PNMI */ + Val += pPnmiPrt->StatRxFrameTooLongCts; + break; + + case SK_MAC_XMAC: + /* + * Frames longer than IEEE 802.3 frame max size are counted + * by XMAC in frame_too_long counter even reception of long + * frames was enabled and the frame was correct. + * So correct the value by subtracting RxLongFrame counter. + */ + Val -= pPnmiPrt->StatRxLongFrameCts; + break; + + default: + break; + } + + LowVal = (SK_U32)Val; + HighVal = (SK_U32)(Val >> 32); + break; + + case SK_PNMI_HRX_SHORTS: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + /* GM_RXE_FRAG?? */ + return (Val); + } + + /* + * XMAC counts short frame errors even if link down (#10620) + * + * If link-down the counter remains constant + */ + if (pAC->GIni.GP[PhysPortIndex].PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) { + + /* Otherwise get incremental difference */ + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + + Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal); + Val -= pPnmiPrt->RxShortZeroMark; + + LowVal = (SK_U32)Val; + HighVal = (SK_U32)(Val >> 32); + } + break; + + case SK_PNMI_HRX_MACC: + case SK_PNMI_HRX_MACC_UNKWN: + case SK_PNMI_HRX_BURST: + case SK_PNMI_HRX_MISSED: + case SK_PNMI_HRX_FRAMING: + case SK_PNMI_HRX_CARRIER: + case SK_PNMI_HRX_IRLENGTH: + case SK_PNMI_HRX_SYMBOL: + case SK_PNMI_HRX_CEXT: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + /* GM_RXE_FRAG?? */ + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HRX_PMACC_ERR: + /* For GMAC the SW counter is managed by PNMI */ + if (MacType == SK_MAC_GMAC) { + return (pPnmiPrt->StatRxPMaccErr); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + /* SW counter managed by PNMI */ + case SK_PNMI_HTX_SYNC: + LowVal = (SK_U32)pPnmiPrt->StatSyncCts; + HighVal = (SK_U32)(pPnmiPrt->StatSyncCts >> 32); + break; + + /* SW counter managed by PNMI */ + case SK_PNMI_HTX_SYNC_OCTET: + LowVal = (SK_U32)pPnmiPrt->StatSyncOctetsCts; + HighVal = (SK_U32)(pPnmiPrt->StatSyncOctetsCts >> 32); + break; + + case SK_PNMI_HRX_FCS: + /* + * Broadcom filters fcs errors and counts it in + * Receive Error Counter register + */ + if (pAC->GIni.GP[PhysPortIndex].PhyType == SK_PHY_BCOM) { + /* do not read while not initialized (PHY_READ hangs!)*/ + if (pAC->GIni.GP[PhysPortIndex].PState) { + PHY_READ(IoC, &pAC->GIni.GP[PhysPortIndex], + PhysPortIndex, PHY_BCOM_RE_CTR, + &Word); + + LowVal = Word; + } + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + } + else { + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + } + break; + + default: + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + } + + Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal); + + /* Correct value because of possible XMAC reset. XMAC Errata #2 */ + Val += pPnmiPrt->CounterOffset[StatIndex]; + + return (Val); +} + +/***************************************************************************** + * + * ResetCounter - Set all counters and timestamps to zero + * + * Description: + * Notifies other common modules which store statistic data to + * reset their counters and finally reset our own counters. + * + * Returns: + * Nothing + */ +PNMI_STATIC void ResetCounter( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 NetIndex) +{ + unsigned int PhysPortIndex; + SK_EVPARA EventParam; + + + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + + /* Notify sensor module */ + SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam); + + /* Notify RLMT module */ + EventParam.Para32[0] = NetIndex; + EventParam.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam); + EventParam.Para32[1] = 0; + + /* Notify SIRQ module */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam); + + /* Notify CSUM module */ +#ifdef SK_USE_CSUM + EventParam.Para32[0] = NetIndex; + EventParam.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_CSUM, SK_CSUM_EVENT_CLEAR_PROTO_STATS, + EventParam); +#endif + + /* Clear XMAC statistic */ + for (PhysPortIndex = 0; PhysPortIndex < + (unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) { + + (void)pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PhysPortIndex); + + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].CounterHigh, + 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].CounterHigh)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + CounterOffset, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].CounterOffset)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatSyncCts, + 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatSyncCts)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + StatSyncOctetsCts, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].StatSyncOctetsCts)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + StatRxLongFrameCts, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].StatRxLongFrameCts)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + StatRxFrameTooLongCts, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].StatRxFrameTooLongCts)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + StatRxPMaccErr, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].StatRxPMaccErr)); + } + + /* + * Clear local statistics + */ + SK_MEMSET((char *)&pAC->Pnmi.VirtualCounterOffset, 0, + sizeof(pAC->Pnmi.VirtualCounterOffset)); + pAC->Pnmi.RlmtChangeCts = 0; + pAC->Pnmi.RlmtChangeTime = 0; + SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0, + sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue)); + pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0; + pAC->Pnmi.RlmtChangeEstimate.Estimate = 0; + pAC->Pnmi.Port[NetIndex].TxSwQueueMax = 0; + pAC->Pnmi.Port[NetIndex].TxRetryCts = 0; + pAC->Pnmi.Port[NetIndex].RxIntrCts = 0; + pAC->Pnmi.Port[NetIndex].TxIntrCts = 0; + pAC->Pnmi.Port[NetIndex].RxNoBufCts = 0; + pAC->Pnmi.Port[NetIndex].TxNoBufCts = 0; + pAC->Pnmi.Port[NetIndex].TxUsedDescrNo = 0; + pAC->Pnmi.Port[NetIndex].RxDeliveredCts = 0; + pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts = 0; + pAC->Pnmi.Port[NetIndex].ErrRecoveryCts = 0; +} + +/***************************************************************************** + * + * GetTrapEntry - Get an entry in the trap buffer + * + * Description: + * The trap buffer stores various events. A user application somehow + * gets notified that an event occured and retrieves the trap buffer + * contens (or simply polls the buffer). The buffer is organized as + * a ring which stores the newest traps at the beginning. The oldest + * traps are overwritten by the newest ones. Each trap entry has a + * unique number, so that applications may detect new trap entries. + * + * Returns: + * A pointer to the trap entry + */ +PNMI_STATIC char* GetTrapEntry( +SK_AC *pAC, /* Pointer to adapter context */ +SK_U32 TrapId, /* SNMP ID of the trap */ +unsigned int Size) /* Space needed for trap entry */ +{ + unsigned int BufPad = pAC->Pnmi.TrapBufPad; + unsigned int BufFree = pAC->Pnmi.TrapBufFree; + unsigned int Beg = pAC->Pnmi.TrapQueueBeg; + unsigned int End = pAC->Pnmi.TrapQueueEnd; + char *pBuf = &pAC->Pnmi.TrapBuf[0]; + int Wrap; + unsigned int NeededSpace; + unsigned int EntrySize; + SK_U32 Val32; + SK_U64 Val64; + + + /* Last byte of entry will get a copy of the entry length */ + Size ++; + + /* + * Calculate needed buffer space */ + if (Beg >= Size) { + + NeededSpace = Size; + Wrap = SK_FALSE; + } + else { + NeededSpace = Beg + Size; + Wrap = SK_TRUE; + } + + /* + * Check if enough buffer space is provided. Otherwise + * free some entries. Leave one byte space between begin + * and end of buffer to make it possible to detect whether + * the buffer is full or empty + */ + while (BufFree < NeededSpace + 1) { + + if (End == 0) { + + End = SK_PNMI_TRAP_QUEUE_LEN; + } + + EntrySize = (unsigned int)*((unsigned char *)pBuf + End - 1); + BufFree += EntrySize; + End -= EntrySize; +#ifdef DEBUG + SK_MEMSET(pBuf + End, (char)(-1), EntrySize); +#endif + if (End == BufPad) { +#ifdef DEBUG + SK_MEMSET(pBuf, (char)(-1), End); +#endif + BufFree += End; + End = 0; + BufPad = 0; + } + } + + /* + * Insert new entry as first entry. Newest entries are + * stored at the beginning of the queue. + */ + if (Wrap) { + + BufPad = Beg; + Beg = SK_PNMI_TRAP_QUEUE_LEN - Size; + } + else { + Beg = Beg - Size; + } + BufFree -= NeededSpace; + + /* Save the current offsets */ + pAC->Pnmi.TrapQueueBeg = Beg; + pAC->Pnmi.TrapQueueEnd = End; + pAC->Pnmi.TrapBufPad = BufPad; + pAC->Pnmi.TrapBufFree = BufFree; + + /* Initialize the trap entry */ + *(pBuf + Beg + Size - 1) = (char)Size; + *(pBuf + Beg) = (char)Size; + Val32 = (pAC->Pnmi.TrapUnique) ++; + SK_PNMI_STORE_U32(pBuf + Beg + 1, Val32); + SK_PNMI_STORE_U32(pBuf + Beg + 1 + sizeof(SK_U32), TrapId); + Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); + SK_PNMI_STORE_U64(pBuf + Beg + 1 + 2 * sizeof(SK_U32), Val64); + + return (pBuf + Beg); +} + +/***************************************************************************** + * + * CopyTrapQueue - Copies the trap buffer for the TRAP OID + * + * Description: + * On a query of the TRAP OID the trap buffer contents will be + * copied continuously to the request buffer, which must be large + * enough. No length check is performed. + * + * Returns: + * Nothing + */ +PNMI_STATIC void CopyTrapQueue( +SK_AC *pAC, /* Pointer to adapter context */ +char *pDstBuf) /* Buffer to which the queued traps will be copied */ +{ + unsigned int BufPad = pAC->Pnmi.TrapBufPad; + unsigned int Trap = pAC->Pnmi.TrapQueueBeg; + unsigned int End = pAC->Pnmi.TrapQueueEnd; + char *pBuf = &pAC->Pnmi.TrapBuf[0]; + unsigned int Len; + unsigned int DstOff = 0; + + + while (Trap != End) { + + Len = (unsigned int)*(pBuf + Trap); + + /* + * Last byte containing a copy of the length will + * not be copied. + */ + *(pDstBuf + DstOff) = (char)(Len - 1); + SK_MEMCPY(pDstBuf + DstOff + 1, pBuf + Trap + 1, Len - 2); + DstOff += Len - 1; + + Trap += Len; + if (Trap == SK_PNMI_TRAP_QUEUE_LEN) { + + Trap = BufPad; + } + } +} + +/***************************************************************************** + * + * GetTrapQueueLen - Get the length of the trap buffer + * + * Description: + * Evaluates the number of currently stored traps and the needed + * buffer size to retrieve them. + * + * Returns: + * Nothing + */ +PNMI_STATIC void GetTrapQueueLen( +SK_AC *pAC, /* Pointer to adapter context */ +unsigned int *pLen, /* Length in Bytes of all queued traps */ +unsigned int *pEntries) /* Returns number of trapes stored in queue */ +{ + unsigned int BufPad = pAC->Pnmi.TrapBufPad; + unsigned int Trap = pAC->Pnmi.TrapQueueBeg; + unsigned int End = pAC->Pnmi.TrapQueueEnd; + char *pBuf = &pAC->Pnmi.TrapBuf[0]; + unsigned int Len; + unsigned int Entries = 0; + unsigned int TotalLen = 0; + + + while (Trap != End) { + + Len = (unsigned int)*(pBuf + Trap); + TotalLen += Len - 1; + Entries ++; + + Trap += Len; + if (Trap == SK_PNMI_TRAP_QUEUE_LEN) { + + Trap = BufPad; + } + } + + *pEntries = Entries; + *pLen = TotalLen; +} + +/***************************************************************************** + * + * QueueSimpleTrap - Store a simple trap to the trap buffer + * + * Description: + * A simple trap is a trap with now additional data. It consists + * simply of a trap code. + * + * Returns: + * Nothing + */ +PNMI_STATIC void QueueSimpleTrap( +SK_AC *pAC, /* Pointer to adapter context */ +SK_U32 TrapId) /* Type of sensor trap */ +{ + GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_SIMPLE_LEN); +} + +/***************************************************************************** + * + * QueueSensorTrap - Stores a sensor trap in the trap buffer + * + * Description: + * Gets an entry in the trap buffer and fills it with sensor related + * data. + * + * Returns: + * Nothing + */ +PNMI_STATIC void QueueSensorTrap( +SK_AC *pAC, /* Pointer to adapter context */ +SK_U32 TrapId, /* Type of sensor trap */ +unsigned int SensorIndex) /* Index of sensor which caused the trap */ +{ + char *pBuf; + unsigned int Offset; + unsigned int DescrLen; + SK_U32 Val32; + + + /* Get trap buffer entry */ + DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc); + pBuf = GetTrapEntry(pAC, TrapId, + SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen); + Offset = SK_PNMI_TRAP_SIMPLE_LEN; + + /* Store additionally sensor trap related data */ + Val32 = OID_SKGE_SENSOR_INDEX; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + *(pBuf + Offset + 4) = 4; + Val32 = (SK_U32)SensorIndex; + SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32); + Offset += 9; + + Val32 = (SK_U32)OID_SKGE_SENSOR_DESCR; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + *(pBuf + Offset + 4) = (char)DescrLen; + SK_MEMCPY(pBuf + Offset + 5, pAC->I2c.SenTable[SensorIndex].SenDesc, + DescrLen); + Offset += DescrLen + 5; + + Val32 = OID_SKGE_SENSOR_TYPE; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + *(pBuf + Offset + 4) = 1; + *(pBuf + Offset + 5) = (char)pAC->I2c.SenTable[SensorIndex].SenType; + Offset += 6; + + Val32 = OID_SKGE_SENSOR_VALUE; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + *(pBuf + Offset + 4) = 4; + Val32 = (SK_U32)pAC->I2c.SenTable[SensorIndex].SenValue; + SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32); +} + +/***************************************************************************** + * + * QueueRlmtNewMacTrap - Store a port switch trap in the trap buffer + * + * Description: + * Nothing further to explain. + * + * Returns: + * Nothing + */ +PNMI_STATIC void QueueRlmtNewMacTrap( +SK_AC *pAC, /* Pointer to adapter context */ +unsigned int ActiveMac) /* Index (0..n) of the currently active port */ +{ + char *pBuf; + SK_U32 Val32; + + + pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT, + SK_PNMI_TRAP_RLMT_CHANGE_LEN); + + Val32 = OID_SKGE_RLMT_PORT_ACTIVE; + SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32); + *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1; + *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)ActiveMac; +} + +/***************************************************************************** + * + * QueueRlmtPortTrap - Store port related RLMT trap to trap buffer + * + * Description: + * Nothing further to explain. + * + * Returns: + * Nothing + */ +PNMI_STATIC void QueueRlmtPortTrap( +SK_AC *pAC, /* Pointer to adapter context */ +SK_U32 TrapId, /* Type of RLMT port trap */ +unsigned int PortIndex) /* Index of the port, which changed its state */ +{ + char *pBuf; + SK_U32 Val32; + + + pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN); + + Val32 = OID_SKGE_RLMT_PORT_INDEX; + SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32); + *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1; + *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)PortIndex; +} + +/***************************************************************************** + * + * CopyMac - Copies a MAC address + * + * Description: + * Nothing further to explain. + * + * Returns: + * Nothing + */ +PNMI_STATIC void CopyMac( +char *pDst, /* Pointer to destination buffer */ +SK_MAC_ADDR *pMac) /* Pointer of Source */ +{ + int i; + + + for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) { + + *(pDst + i) = pMac->a[i]; + } +} + + +#ifdef SK_POWER_MGMT +/***************************************************************************** + * + * PowerManagement - OID handler function of PowerManagement OIDs + * + * Description: + * The code is simple. No description necessary. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ + +PNMI_STATIC int PowerManagement( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + + SK_U32 RetCode = SK_PNMI_ERR_GENERAL; + + /* + * Check instance. We only handle single instance variables + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* + * Perform action + */ + if (Action == SK_PNMI_GET) { + + /* + * Check length + */ + switch (Id) { + + case OID_PNP_CAPABILITIES: + if (*pLen < sizeof(SK_PNP_CAPABILITIES)) { + + *pLen = sizeof(SK_PNP_CAPABILITIES); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_PNP_QUERY_POWER: + case OID_PNP_ENABLE_WAKE_UP: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_PNP_SET_POWER: + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR040, + SK_PNMI_ERR040MSG); + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Get value + */ + switch (Id) { + + case OID_PNP_CAPABILITIES: + RetCode = SkPowerQueryPnPCapabilities(pAC, IoC, pBuf, pLen); + break; + + case OID_PNP_QUERY_POWER: + /* The Windows DDK describes: An OID_PNP_QUERY_POWER requests + the miniport to indicate whether it can transition its NIC + to the low-power state. + A miniport driver must always return NDIS_STATUS_SUCCESS + to a query of OID_PNP_QUERY_POWER. */ + RetCode = SK_PNMI_ERR_OK; + break; + + /* NDIS handles these OIDs as write-only. + * So in case of get action the buffer with written length = 0 + * is returned + */ + case OID_PNP_SET_POWER: + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + *pLen = 0; + RetCode = SK_PNMI_ERR_OK; + break; + + case OID_PNP_ENABLE_WAKE_UP: + RetCode = SkPowerGetEnableWakeUp(pAC, IoC, pBuf, pLen); + break; + + default: + RetCode = SK_PNMI_ERR_GENERAL; + break; + } + + return (RetCode); + } + + /* + * From here SET or PRESET action. Check if the passed + * buffer length is plausible. + */ + switch (Id) { + case OID_PNP_SET_POWER: + case OID_PNP_ENABLE_WAKE_UP: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen != sizeof(SK_U32)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + break; + + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + if (*pLen < sizeof(SK_PM_PACKET_PATTERN)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Perform preset or set + */ + + /* POWER module does not support PRESET action */ + if (Action == SK_PNMI_PRESET) { + return (SK_PNMI_ERR_OK); + } + + switch (Id) { + case OID_PNP_SET_POWER: + RetCode = SkPowerSetPower(pAC, IoC, pBuf, pLen); + break; + + case OID_PNP_ADD_WAKE_UP_PATTERN: + RetCode = SkPowerAddWakeUpPattern(pAC, IoC, pBuf, pLen); + break; + + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, pBuf, pLen); + break; + + case OID_PNP_ENABLE_WAKE_UP: + RetCode = SkPowerSetEnableWakeUp(pAC, IoC, pBuf, pLen); + break; + + default: + RetCode = SK_PNMI_ERR_GENERAL; + } + + return (RetCode); +} +#endif /* SK_POWER_MGMT */ + + +/***************************************************************************** + * + * Vct - OID handler function of OIDs + * + * Description: + * The code is simple. No description necessary. + * + * Returns: + * SK_PNMI_ERR_OK The request was performed successfully. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter). + * SK_PNMI_ERR_READ_ONLY Only the Get action is allowed. + * + */ + +PNMI_STATIC int Vct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which the mgmt data will be copied */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (-1,2..n) that is to be queried */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ +{ + SK_GEPORT *pPrt; + SK_PNMI_VCT *pVctBackupData; + SK_U32 LogPortMax; + SK_U32 PhysPortMax; + SK_U32 PhysPortIndex; + SK_U32 Limit; + SK_U32 Offset; + SK_BOOL Link; + SK_U32 RetCode = SK_PNMI_ERR_GENERAL; + int i; + SK_EVPARA Para; + SK_U32 CableLength; + + /* + * Calculate the port indexes from the instance. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); + + /* Dual net mode? */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + LogPortMax--; + } + + if ((Instance != (SK_U32) (-1))) { + /* Check instance range. */ + if ((Instance < 2) || (Instance > LogPortMax)) { + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + PhysPortIndex = NetIndex; + } + else { + PhysPortIndex = Instance - 2; + } + Limit = PhysPortIndex + 1; + } + else { /* + * Instance == (SK_U32) (-1), get all Instances of that OID. + * + * Not implemented yet. May be used in future releases. + */ + PhysPortIndex = 0; + Limit = PhysPortMax; + } + + pPrt = &pAC->GIni.GP[PhysPortIndex]; + if (pPrt->PHWLinkUp) { + Link = SK_TRUE; + } + else { + Link = SK_FALSE; + } + + /* + * Check MAC type. + */ + if (pPrt->PhyType != SK_PHY_MARV_COPPER) { + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* Initialize backup data pointer. */ + pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex]; + + /* + * Check action type. + */ + if (Action == SK_PNMI_GET) { + /* + * Check length. + */ + switch (Id) { + + case OID_SKGE_VCT_GET: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT)) { + *pLen = (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_VCT_STATUS: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) { + *pLen = (Limit - PhysPortIndex) * sizeof(SK_U8); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Get value. + */ + Offset = 0; + for (; PhysPortIndex < Limit; PhysPortIndex++) { + switch (Id) { + + case OID_SKGE_VCT_GET: + if ((Link == SK_FALSE) && + (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) { + RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE); + if (RetCode == 0) { + pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING; + pAC->Pnmi.VctStatus[PhysPortIndex] |= + (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE); + + /* Copy results for later use to PNMI struct. */ + for (i = 0; i < 4; i++) { + if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) { + if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] < 0xff)) { + pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH; + } + } + if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] != 0xff)) { + CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28); + } + else { + CableLength = 0; + } + pVctBackupData->PMdiPairLen[i] = CableLength; + pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i]; + } + + Para.Para32[0] = PhysPortIndex; + Para.Para32[1] = -1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para); + SkEventDispatcher(pAC, IoC); + } + else { + ; /* VCT test is running. */ + } + } + + /* Get all results. */ + CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex); + Offset += sizeof(SK_U8); + *(pBuf + Offset) = pPrt->PCableLen; + Offset += sizeof(SK_U8); + for (i = 0; i < 4; i++) { + SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->PMdiPairLen[i]); + Offset += sizeof(SK_U32); + } + for (i = 0; i < 4; i++) { + *(pBuf + Offset) = pVctBackupData->PMdiPairSts[i]; + Offset += sizeof(SK_U8); + } + + RetCode = SK_PNMI_ERR_OK; + break; + + case OID_SKGE_VCT_STATUS: + CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex); + Offset += sizeof(SK_U8); + RetCode = SK_PNMI_ERR_OK; + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } /* for */ + *pLen = Offset; + return (RetCode); + + } /* if SK_PNMI_GET */ + + /* + * From here SET or PRESET action. Check if the passed + * buffer length is plausible. + */ + + /* + * Check length. + */ + switch (Id) { + case OID_SKGE_VCT_SET: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) { + *pLen = (Limit - PhysPortIndex) * sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Perform preset or set. + */ + + /* VCT does not support PRESET action. */ + if (Action == SK_PNMI_PRESET) { + return (SK_PNMI_ERR_OK); + } + + Offset = 0; + for (; PhysPortIndex < Limit; PhysPortIndex++) { + switch (Id) { + case OID_SKGE_VCT_SET: /* Start VCT test. */ + if (Link == SK_FALSE) { + SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST); + + RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE); + if (RetCode == 0) { /* RetCode: 0 => Start! */ + pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING; + pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_NEW_VCT_DATA; + pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_LINK; + + /* + * Start VCT timer counter. + */ + SK_MEMSET((char *) &Para, 0, sizeof(Para)); + Para.Para32[0] = PhysPortIndex; + Para.Para32[1] = -1; + SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer, + 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para); + SK_PNMI_STORE_U32((pBuf + Offset), RetCode); + RetCode = SK_PNMI_ERR_OK; + } + else { /* RetCode: 2 => Running! */ + SK_PNMI_STORE_U32((pBuf + Offset), RetCode); + RetCode = SK_PNMI_ERR_OK; + } + } + else { /* RetCode: 4 => Link! */ + RetCode = 4; + SK_PNMI_STORE_U32((pBuf + Offset), RetCode); + RetCode = SK_PNMI_ERR_OK; + } + Offset += sizeof(SK_U32); + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } /* for */ + *pLen = Offset; + return (RetCode); + +} /* Vct */ + + +PNMI_STATIC void CheckVctStatus( +SK_AC *pAC, +SK_IOC IoC, +char *pBuf, +SK_U32 Offset, +SK_U32 PhysPortIndex) +{ + SK_GEPORT *pPrt; + SK_PNMI_VCT *pVctData; + SK_U32 RetCode; + SK_U8 LinkSpeedUsed; + + pPrt = &pAC->GIni.GP[PhysPortIndex]; + + pVctData = (SK_PNMI_VCT *) (pBuf + Offset); + pVctData->VctStatus = SK_PNMI_VCT_NONE; + + if (!pPrt->PHWLinkUp) { + + /* Was a VCT test ever made before? */ + if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) { + if ((pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_LINK)) { + pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA; + } + else { + pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA; + } + } + + /* Check VCT test status. */ + RetCode = SkGmCableDiagStatus(pAC,IoC, PhysPortIndex, SK_FALSE); + if (RetCode == 2) { /* VCT test is running. */ + pVctData->VctStatus |= SK_PNMI_VCT_RUNNING; + } + else { /* VCT data was copied to pAC here. Check PENDING state. */ + if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) { + pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA; + } + } + + if (pPrt->PCableLen != 0xff) { /* Old DSP value. */ + pVctData->VctStatus |= SK_PNMI_VCT_OLD_DSP_DATA; + } + } + else { + + /* Was a VCT test ever made before? */ + if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) { + pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA; + pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA; + } + + /* DSP only valid in 100/1000 modes. */ + LinkSpeedUsed = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed; + if (LinkSpeedUsed != SK_LSPEED_STAT_10MBPS) { + pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA; + } + } + +} /* CheckVctStatus */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skgesirq.c b/drivers/sk98lin/skgesirq.c new file mode 100644 index 0000000..e5a4f7e --- /dev/null +++ b/drivers/sk98lin/skgesirq.c @@ -0,0 +1,2417 @@ +/****************************************************************************** + * + * Name: skgesirq.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.83 $ + * Date: $Date: 2003/02/05 15:10:59 $ + * Purpose: Special IRQ module + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgesirq.c,v $ + * Revision 1.83 2003/02/05 15:10:59 rschmidt + * Fixed setting of PLinkSpeedUsed in SkHWLinkUp() when + * auto-negotiation is disabled. + * Editorial changes. + * + * Revision 1.82 2003/01/29 13:34:33 rschmidt + * Added some typecasts to avoid compiler warnings. + * + * Revision 1.81 2002/12/05 10:49:51 rschmidt + * Fixed missing Link Down Event for fiber (Bug Id #10768) + * Added reading of cable length when link is up + * Removed testing of unused error bits in PHY ISR + * Editorial changes. + * + * Revision 1.80 2002/11/12 17:15:21 rschmidt + * Replaced SkPnmiGetVar() by ...MacStatistic() in SkMacParity(). + * Editorial changes. + * + * Revision 1.79 2002/10/14 15:14:51 rschmidt + * Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in + * SkMacParity() depending on GIChipRev (HW-Bug #8). + * Added error messages for GPHY Auto-Negotiation Error and + * FIFO Overflow/Underrun in SkPhyIsrGmac(). + * Editorial changes. + * + * Revision 1.78 2002/10/10 15:54:29 mkarl + * changes for PLinkSpeedUsed + * + * Revision 1.77 2002/09/12 08:58:51 rwahl + * Retrieve counters needed for XMAC errata workarounds directly because + * PNMI returns corrected counter values (e.g. #10620). + * + * Revision 1.76 2002/08/16 15:21:54 rschmidt + * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis. + * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros. + * Editorial changes. + * + * Revision 1.75 2002/08/12 13:50:47 rschmidt + * Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in + * SkMacParity() by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE (HW-Bug #8). + * Added clearing of IS_IRQ_TIST_OV and IS_IRQ_SENSOR in SkGeHwErr(). + * Corrected handling of Link Up and Auto-Negotiation Over for GPHY. + * in SkGePortCheckUpGmac(). + * Editorial changes. + * + * Revision 1.74 2002/08/08 16:17:04 rschmidt + * Added PhyType check for SK_HWEV_SET_ROLE event (copper only) + * Changed Link Up check reading PHY Specific Status (YUKON) + * Editorial changes + * + * Revision 1.73 2002/07/15 18:36:53 rwahl + * Editorial changes. + * + * Revision 1.72 2002/07/15 15:46:26 rschmidt + * Added new event: SK_HWEV_SET_SPEED + * Editorial changes + * + * Revision 1.71 2002/06/10 09:34:19 rschmidt + * Editorial changes + * + * Revision 1.70 2002/06/05 08:29:18 rschmidt + * SkXmRxTxEnable() replaced by SkMacRxTxEnable(). + * Editorial changes. + * + * Revision 1.69 2002/04/25 13:03:49 rschmidt + * Changes for handling YUKON. + * Use of #ifdef OTHER_PHY to eliminate code for unused Phy types. + * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(), + * SkMacIrqDisable(). + * Added handling for GMAC FIFO in SkMacParity(). + * Replaced all SkXm...() functions with SkMac...() to handle also + * YUKON's GMAC. + * Macros for XMAC PHY access PHY_READ(), PHY_WRITE() replaced + * by functions SkXmPhyRead(), SkXmPhyWrite(). + * Disabling all PHY interrupts moved to SkMacIrqDisable(). + * Added handling for GPHY IRQ in SkGeSirqIsr(). + * Removed status parameter from MAC IRQ handler SkMacIrq(). + * Added SkGePortCheckUpGmac(), SkPhyIsrGmac() for GMAC. + * Editorial changes + * + * Revision 1.68 2002/02/26 15:24:53 rwahl + * Fix: no link with manual configuration (#10673). The previous fix for + * #10639 was removed. So for RLMT mode = CLS the RLMT may switch to + * misconfigured port. It should not occur for the other RLMT modes. + * + * Revision 1.67 2001/11/20 09:19:58 rwahl + * Reworked bugfix #10639 (no dependency to RLMT mode). + * + * Revision 1.66 2001/10/26 07:52:53 afischer + * Port switching bug in `check local link` mode + * + * Revision 1.65 2001/02/23 13:41:51 gklug + * fix: PHYS2INST should be used correctly for Dual Net operation + * chg: do no longer work with older PNMI + * + * Revision 1.64 2001/02/15 11:27:04 rassmann + * Working with RLMT v1 if SK_MAX_NETS undefined. + * + * Revision 1.63 2001/02/06 10:44:23 mkunz + * - NetIndex added to interface functions of pnmi V4 with dual net support + * + * Revision 1.62 2001/01/31 15:31:41 gklug + * fix: problem with autosensing an SR8800 switch + * + * Revision 1.61 2000/11/09 11:30:09 rassmann + * WA: Waiting after releasing reset until BCom chip is accessible. + * + * Revision 1.60 2000/10/18 12:37:48 cgoos + * Reinserted the comment for version 1.56. + * + * Revision 1.59 2000/10/18 12:22:20 cgoos + * Added workaround for half duplex hangup. + * + * Revision 1.58 2000/09/28 13:06:04 gklug + * fix: BCom may NOT be touched if XMAC is in RESET state + * + * Revision 1.57 2000/09/08 12:38:39 cgoos + * Added forgotten variable declaration. + * + * Revision 1.56 2000/09/08 08:12:13 cgoos + * Changed handling of parity errors in SkGeHwErr (correct reset of error). + * + * Revision 1.55 2000/06/19 08:36:25 cgoos + * Changed comment. + * + * Revision 1.54 2000/05/22 08:45:57 malthoff + * Fix: #10523 is valid for all BCom PHYs. + * + * Revision 1.53 2000/05/19 10:20:30 cgoos + * Removed Solaris debug output code. + * + * Revision 1.52 2000/05/19 10:19:37 cgoos + * Added PHY state check in HWLinkDown. + * Move PHY interrupt code to IS_EXT_REG case in SkGeSirqIsr. + * + * Revision 1.51 2000/05/18 05:56:20 cgoos + * Fixed typo. + * + * Revision 1.50 2000/05/17 12:49:49 malthoff + * Fixes BCom link bugs (#10523). + * + * Revision 1.49 1999/12/17 11:02:50 gklug + * fix: read PHY_STAT of Broadcom chip more often to assure good status + * + * Revision 1.48 1999/12/06 10:01:17 cgoos + * Added SET function for Role. + * + * Revision 1.47 1999/11/22 13:34:24 cgoos + * Changed license header to GPL. + * + * Revision 1.46 1999/09/16 10:30:07 cgoos + * Removed debugging output statement from Linux. + * + * Revision 1.45 1999/09/16 07:32:55 cgoos + * Fixed dual-port copperfield bug (PHY_READ from resetted port). + * Removed some unused variables. + * + * Revision 1.44 1999/08/03 15:25:04 cgoos + * Removed workaround for disabled interrupts in half duplex mode. + * + * Revision 1.43 1999/08/03 14:27:58 cgoos + * Removed SENSE mode code from SkGePortCheckUpBcom. + * + * Revision 1.42 1999/07/26 09:16:54 cgoos + * Added some typecasts to avoid compiler warnings. + * + * Revision 1.41 1999/05/19 07:28:59 cgoos + * Changes for 1000Base-T. + * + * Revision 1.40 1999/04/08 13:59:39 gklug + * fix: problem with 3Com switches endless RESTARTs + * + * Revision 1.39 1999/03/08 10:10:52 gklug + * fix: AutoSensing did switch to next mode even if LiPa indicated offline + * + * Revision 1.38 1999/03/08 09:49:03 gklug + * fix: Bug using pAC instead of IoC, causing AIX problems + * fix: change compare for Linux compiler bug workaround + * + * Revision 1.37 1999/01/28 14:51:33 gklug + * fix: monitor for autosensing and extra RESETS the RX on wire counters + * + * Revision 1.36 1999/01/22 09:19:55 gklug + * fix: Init DupMode and InitPauseMd are now called in RxTxEnable + * + * Revision 1.35 1998/12/11 15:22:59 gklug + * chg: autosensing: check for receive if manual mode was guessed + * chg: simplified workaround for XMAC errata + * chg: wait additional 100 ms before link goes up. + * chg: autoneg timeout to 600 ms + * chg: restart autoneg even if configured to autonegotiation + * + * Revision 1.34 1998/12/10 10:33:14 gklug + * add: more debug messages + * fix: do a new InitPhy if link went down (AutoSensing problem) + * chg: Check for zero shorts if link is NOT up + * chg: reset Port if link goes down + * chg: wait additional 100 ms when link comes up to check shorts + * fix: dummy read extended autoneg status to prevent link going down immediately + * + * Revision 1.33 1998/12/07 12:18:29 gklug + * add: refinement of autosense mode: take into account the autoneg cap of LiPa + * + * Revision 1.32 1998/12/07 07:11:21 gklug + * fix: compiler warning + * + * Revision 1.31 1998/12/02 09:29:05 gklug + * fix: WA XMAC Errata: FCSCt check was not correct. + * fix: WA XMAC Errata: Prec Counter were NOT updated in case of short checks. + * fix: Clear Stat : now clears the Prev counters of all known Ports + * + * Revision 1.30 1998/12/01 10:54:15 gklug + * dd: workaround for XMAC errata changed. Check RX count and CRC err Count, too. + * + * Revision 1.29 1998/12/01 10:01:53 gklug + * fix: if MAC IRQ occurs during port down, this will be handled correctly + * + * Revision 1.28 1998/11/26 16:22:11 gklug + * fix: bug in autosense if manual modes are used + * + * Revision 1.27 1998/11/26 15:50:06 gklug + * fix: PNMI needs to set PLinkModeConf + * + * Revision 1.26 1998/11/26 14:51:58 gklug + * add: AutoSensing functionalty + * + * Revision 1.25 1998/11/26 07:34:37 gklug + * fix: Init PrevShorts when restarting port due to Link connection + * + * Revision 1.24 1998/11/25 10:57:32 gklug + * fix: remove unreferenced local vars + * + * Revision 1.23 1998/11/25 08:26:40 gklug + * fix: don't do a RESET on a starting or stopping port + * + * Revision 1.22 1998/11/24 13:29:44 gklug + * add: Workaround for MAC parity errata + * + * Revision 1.21 1998/11/18 15:31:06 gklug + * fix: lint bugs + * + * Revision 1.20 1998/11/18 12:58:54 gklug + * fix: use PNMI query instead of hardware access + * + * Revision 1.19 1998/11/18 12:54:55 gklug + * chg: add new workaround for XMAC Errata + * add: short event counter monitoring on active link too + * + * Revision 1.18 1998/11/13 14:27:41 malthoff + * Bug Fix: Packet Arbiter Timeout was not cleared correctly + * for timeout on TX1 and TX2. + * + * Revision 1.17 1998/11/04 07:01:59 cgoos + * Moved HW link poll sequence. + * Added call to SkXmRxTxEnable. + * + * Revision 1.16 1998/11/03 13:46:03 gklug + * add: functionality of SET_LMODE and SET_FLOW_MODE + * fix: send RLMT LinkDown event when Port stop is given with LinkUp + * + * Revision 1.15 1998/11/03 12:56:47 gklug + * fix: Needs more events + * + * Revision 1.14 1998/10/30 07:36:35 gklug + * rmv: unnecessary code + * + * Revision 1.13 1998/10/29 15:21:57 gklug + * add: Poll link feature for activating HW link + * fix: Deactivate HWLink when Port STOP is given + * + * Revision 1.12 1998/10/28 07:38:57 cgoos + * Checking link status at begin of SkHWLinkUp. + * + * Revision 1.11 1998/10/22 09:46:50 gklug + * fix SysKonnectFileId typo + * + * Revision 1.10 1998/10/14 13:57:47 gklug + * add: Port start/stop event + * + * Revision 1.9 1998/10/14 05:48:29 cgoos + * Added definition for Para. + * + * Revision 1.8 1998/10/14 05:40:09 gklug + * add: Hardware Linkup signal used + * + * Revision 1.7 1998/10/09 06:50:20 malthoff + * Remove ID_sccs by SysKonnectFileId. + * + * Revision 1.6 1998/10/08 09:11:49 gklug + * add: clear IRQ commands + * + * Revision 1.5 1998/10/02 14:27:35 cgoos + * Fixed some typos and wrong event names. + * + * Revision 1.4 1998/10/02 06:24:17 gklug + * add: HW error function + * fix: OUT macros + * + * Revision 1.3 1998/10/01 07:03:00 gklug + * add: ISR for the usual interrupt source register + * + * Revision 1.2 1998/09/03 13:50:33 gklug + * add: function prototypes + * + * Revision 1.1 1998/08/27 11:50:21 gklug + * initial revision + * + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +/* + * Special Interrupt handler + * + * The following abstract should show how this module is included + * in the driver path: + * + * In the ISR of the driver the bits for frame transmission complete and + * for receive complete are checked and handled by the driver itself. + * The bits of the slow path mask are checked after that and then the + * entry into the so-called "slow path" is prepared. It is an implementors + * decision whether this is executed directly or just scheduled by + * disabling the mask. In the interrupt service routine some events may be + * generated, so it would be a good idea to call the EventDispatcher + * right after this ISR. + * + * The Interrupt source register of the adapter is NOT read by this module. + * SO if the drivers implementor needs a while loop around the + * slow data paths interrupt bits, he needs to call the SkGeSirqIsr() for + * each loop entered. + * + * However, the MAC Interrupt status registers are read in a while loop. + * + */ + +static const char SysKonnectFileId[] = + "$Id: skgesirq.c,v 1.83 2003/02/05 15:10:59 rschmidt Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/skgepnmi.h" /* PNMI Definitions */ +#include "h/skrlmt.h" /* RLMT Definitions */ +#include "h/skdrv2nd.h" /* Adapter Control and Driver specific Def. */ + +/* local function prototypes */ +static int SkGePortCheckUpXmac(SK_AC*, SK_IOC, int); +static int SkGePortCheckUpBcom(SK_AC*, SK_IOC, int); +static int SkGePortCheckUpGmac(SK_AC*, SK_IOC, int); +static void SkPhyIsrBcom(SK_AC*, SK_IOC, int, SK_U16); +static void SkPhyIsrGmac(SK_AC*, SK_IOC, int, SK_U16); +#ifdef OTHER_PHY +static int SkGePortCheckUpLone(SK_AC*, SK_IOC, int); +static int SkGePortCheckUpNat(SK_AC*, SK_IOC, int); +static void SkPhyIsrLone(SK_AC*, SK_IOC, int, SK_U16); +#endif /* OTHER_PHY */ + +/* + * array of Rx counter from XMAC which are checked + * in AutoSense mode to check whether a link is not able to auto-negotiate. + */ +static const SK_U16 SkGeRxRegs[]= { + XM_RXF_64B, + XM_RXF_127B, + XM_RXF_255B, + XM_RXF_511B, + XM_RXF_1023B, + XM_RXF_MAX_SZ +} ; + +#ifdef __C2MAN__ +/* + * Special IRQ function + * + * General Description: + * + */ +intro() +{} +#endif + +/* Define return codes of SkGePortCheckUp and CheckShort */ +#define SK_HW_PS_NONE 0 /* No action needed */ +#define SK_HW_PS_RESTART 1 /* Restart needed */ +#define SK_HW_PS_LINK 2 /* Link Up actions needed */ + +/****************************************************************************** + * + * SkHWInitDefSense() - Default Autosensing mode initialization + * + * Description: sets the PLinkMode for HWInit + * + * Returns: N/A + */ +static void SkHWInitDefSense( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + pPrt->PAutoNegTimeOut = 0; + + if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) { + pPrt->PLinkMode = pPrt->PLinkModeConf; + return; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("AutoSensing: First mode %d on Port %d\n", + (int)SK_LMODE_AUTOFULL, Port)); + + pPrt->PLinkMode = SK_LMODE_AUTOFULL; + + return; +} /* SkHWInitDefSense */ + + +/****************************************************************************** + * + * SkHWSenseGetNext() - Get Next Autosensing Mode + * + * Description: gets the appropriate next mode + * + * Note: + * + */ +SK_U8 SkHWSenseGetNext( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + pPrt->PAutoNegTimeOut = 0; + + if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) { + /* Leave all as configured */ + return(pPrt->PLinkModeConf); + } + + if (pPrt->PLinkMode == SK_LMODE_AUTOFULL) { + /* Return next mode AUTOBOTH */ + return(SK_LMODE_AUTOBOTH); + } + + /* Return default autofull */ + return(SK_LMODE_AUTOFULL); +} /* SkHWSenseGetNext */ + + +/****************************************************************************** + * + * SkHWSenseSetNext() - Autosensing Set next mode + * + * Description: sets the appropriate next mode + * + * Returns: N/A + */ +void SkHWSenseSetNext( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U8 NewMode) /* New Mode to be written in sense mode */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + pPrt->PAutoNegTimeOut = 0; + + if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) { + return; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("AutoSensing: next mode %d on Port %d\n", + (int)NewMode, Port)); + + pPrt->PLinkMode = NewMode; + + return; +} /* SkHWSenseSetNext */ + + +/****************************************************************************** + * + * SkHWLinkDown() - Link Down handling + * + * Description: handles the hardware link down signal + * + * Returns: N/A + */ +void SkHWLinkDown( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Disable all MAC interrupts */ + SkMacIrqDisable(pAC, IoC, Port); + + /* Disable Receiver and Transmitter */ + SkMacRxTxDisable(pAC, IoC, Port); + + /* Init default sense mode */ + SkHWInitDefSense(pAC, IoC, Port); + + if (!pPrt->PHWLinkUp) { + return; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link down Port %d\n", Port)); + + /* Set Link to DOWN */ + pPrt->PHWLinkUp = SK_FALSE; + + /* Reset Port stati */ + pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_INDETERMINATED; + + /* Re-init Phy especially when the AutoSense default is set now */ + SkMacInitPhy(pAC, IoC, Port, SK_FALSE); + + /* GP0: used for workaround of Rev. C Errata 2 */ + + /* Do NOT signal to RLMT */ + + /* Do NOT start the timer here */ +} /* SkHWLinkDown */ + + +/****************************************************************************** + * + * SkHWLinkUp() - Link Up handling + * + * Description: handles the hardware link up signal + * + * Returns: N/A + */ +void SkHWLinkUp( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PHWLinkUp) { + /* We do NOT need to proceed on active link */ + return; + } + + pPrt->PHWLinkUp = SK_TRUE; + pPrt->PAutoNegFail = SK_FALSE; + pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; + + if (pPrt->PLinkMode != SK_LMODE_AUTOHALF && + pPrt->PLinkMode != SK_LMODE_AUTOFULL && + pPrt->PLinkMode != SK_LMODE_AUTOBOTH) { + /* Link is up and no Auto-negotiation should be done */ + + /* Link speed should be the configured one */ + switch (pPrt->PLinkSpeed) { + case SK_LSPEED_AUTO: + /* default is 1000 Mbps */ + case SK_LSPEED_1000MBPS: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + break; + case SK_LSPEED_100MBPS: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_100MBPS; + break; + case SK_LSPEED_10MBPS: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_10MBPS; + break; + } + + /* Set Link Mode Status */ + if (pPrt->PLinkMode == SK_LMODE_FULL) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_FULL; + } + else { + pPrt->PLinkModeStatus = SK_LMODE_STAT_HALF; + } + + /* No flow control without auto-negotiation */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + + /* enable Rx/Tx */ + SkMacRxTxEnable(pAC, IoC, Port); + } +} /* SkHWLinkUp */ + + +/****************************************************************************** + * + * SkMacParity() - MAC parity workaround + * + * Description: handles MAC parity errors correctly + * + * Returns: N/A + */ +static void SkMacParity( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index of the port failed */ +{ + SK_EVPARA Para; + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_U32 TxMax; /* TxMax Counter */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Clear IRQ Tx Parity Error */ + if (pAC->GIni.GIGenesis) { + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_PERR); + } + else { + /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), + (SK_U8)((pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE)); + } + + if (pPrt->PCheckPar) { + if (Port == MAC_1) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG); + } + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = Port; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + + return; + } + + /* Check whether frames with a size of 1k were sent */ + if (pAC->GIni.GIGenesis) { + /* Snap statistic counters */ + (void)SkXmUpdateStats(pAC, IoC, Port); + + (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXF_MAX_SZ, &TxMax); + } + else { + (void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax); + } + + if (TxMax > 0) { + /* From now on check the parity */ + pPrt->PCheckPar = SK_TRUE; + } +} /* SkMacParity */ + + +/****************************************************************************** + * + * SkGeHwErr() - Hardware Error service routine + * + * Description: handles all HW Error interrupts + * + * Returns: N/A + */ +static void SkGeHwErr( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +SK_U32 HwStatus) /* Interrupt status word */ +{ + SK_EVPARA Para; + SK_U16 Word; + + if ((HwStatus & (IS_IRQ_MST_ERR | IS_IRQ_STAT)) != 0) { + /* PCI Errors occured */ + if ((HwStatus & IS_IRQ_STAT) != 0) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG); + } + + /* Reset all bits in the PCI STATUS register */ + SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); + } + + if (pAC->GIni.GIGenesis) { + if ((HwStatus & IS_NO_STAT_M1) != 0) { + /* Ignore it */ + /* This situation is also indicated in the descriptor */ + SK_OUT16(IoC, MR_ADDR(MAC_1, RX_MFF_CTRL1), MFF_CLR_INSTAT); + } + + if ((HwStatus & IS_NO_STAT_M2) != 0) { + /* Ignore it */ + /* This situation is also indicated in the descriptor */ + SK_OUT16(IoC, MR_ADDR(MAC_2, RX_MFF_CTRL1), MFF_CLR_INSTAT); + } + + if ((HwStatus & IS_NO_TIST_M1) != 0) { + /* Ignore it */ + /* This situation is also indicated in the descriptor */ + SK_OUT16(IoC, MR_ADDR(MAC_1, RX_MFF_CTRL1), MFF_CLR_INTIST); + } + + if ((HwStatus & IS_NO_TIST_M2) != 0) { + /* Ignore it */ + /* This situation is also indicated in the descriptor */ + SK_OUT16(IoC, MR_ADDR(MAC_2, RX_MFF_CTRL1), MFF_CLR_INTIST); + } + } + else { /* YUKON */ + /* This is necessary only for Rx timing measurements */ + if ((HwStatus & IS_IRQ_TIST_OV) != 0) { + /* Clear Time Stamp Timer IRQ */ + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ); + } + + if ((HwStatus & IS_IRQ_SENSOR) != 0) { + /* Clear I2C IRQ */ + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + } + } + + if ((HwStatus & IS_RAM_RD_PAR) != 0) { + SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR); + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E014, SKERR_SIRQ_E014MSG); + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); + } + + if ((HwStatus & IS_RAM_WR_PAR) != 0) { + SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR); + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E015, SKERR_SIRQ_E015MSG); + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); + } + + if ((HwStatus & IS_M1_PAR_ERR) != 0) { + SkMacParity(pAC, IoC, MAC_1); + } + + if ((HwStatus & IS_M2_PAR_ERR) != 0) { + SkMacParity(pAC, IoC, MAC_2); + } + + if ((HwStatus & IS_R1_PAR_ERR) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_P); + + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG); + Para.Para64 = MAC_1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((HwStatus & IS_R2_PAR_ERR) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_P); + + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG); + Para.Para64 = MAC_2; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_2; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } +} /* SkGeHwErr */ + + +/****************************************************************************** + * + * SkGeSirqIsr() - Special Interrupt Service Routine + * + * Description: handles all non data transfer specific interrupts (slow path) + * + * Returns: N/A + */ +void SkGeSirqIsr( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +SK_U32 Istatus) /* Interrupt status word */ +{ + SK_EVPARA Para; + SK_U32 RegVal32; /* Read register value */ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + unsigned Len; + SK_U64 Octets; + SK_U16 PhyInt; + SK_U16 PhyIMsk; + int i; + + if ((Istatus & IS_HW_ERR) != 0) { + /* read the HW Error Interrupt source */ + SK_IN32(IoC, B0_HWE_ISRC, &RegVal32); + + SkGeHwErr(pAC, IoC, RegVal32); + } + + /* + * Packet Timeout interrupts + */ + /* Check whether MACs are correctly initialized */ + if (((Istatus & (IS_PA_TO_RX1 | IS_PA_TO_TX1)) != 0) && + pAC->GIni.GP[MAC_1].PState == SK_PRT_RESET) { + /* MAC 1 was not initialized but Packet timeout occured */ + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E004, + SKERR_SIRQ_E004MSG); + } + + if (((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) != 0) && + pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) { + /* MAC 2 was not initialized but Packet timeout occured */ + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005, + SKERR_SIRQ_E005MSG); + } + + if ((Istatus & IS_PA_TO_RX1) != 0) { + /* Means network is filling us up */ + SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E002, + SKERR_SIRQ_E002MSG); + SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX1); + } + + if ((Istatus & IS_PA_TO_RX2) != 0) { + /* Means network is filling us up */ + SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E003, + SKERR_SIRQ_E003MSG); + SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX2); + } + + if ((Istatus & IS_PA_TO_TX1) != 0) { + + pPrt = &pAC->GIni.GP[0]; + + /* May be a normal situation in a server with a slow network */ + SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1); + + /* + * workaround: if in half duplex mode, check for Tx hangup. + * Read number of TX'ed bytes, wait for 10 ms, then compare + * the number with current value. If nothing changed, we assume + * that Tx is hanging and do a FIFO flush (see event routine). + */ + if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) && + !pPrt->HalfDupTimerActive) { + /* + * many more pack. arb. timeouts may come in between, + * we ignore those + */ + pPrt->HalfDupTimerActive = SK_TRUE; + + Len = sizeof(SK_U64); + SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets, + &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 0), + pAC->Rlmt.Port[0].Net->NetNumber); + + pPrt->LastOctets = Octets; + + Para.Para32[0] = 0; + SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME, + SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para); + } + } + + if ((Istatus & IS_PA_TO_TX2) != 0) { + + pPrt = &pAC->GIni.GP[1]; + + /* May be a normal situation in a server with a slow network */ + SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2); + + /* workaround: see above */ + if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) && + !pPrt->HalfDupTimerActive) { + pPrt->HalfDupTimerActive = SK_TRUE; + + Len = sizeof(SK_U64); + SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets, + &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 1), + pAC->Rlmt.Port[1].Net->NetNumber); + + pPrt->LastOctets = Octets; + + Para.Para32[0] = 1; + SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME, + SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para); + } + } + + /* Check interrupts of the particular queues */ + if ((Istatus & IS_R1_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006, + SKERR_SIRQ_E006MSG); + Para.Para64 = MAC_1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_R2_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007, + SKERR_SIRQ_E007MSG); + Para.Para64 = MAC_2; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_2; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_XS1_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008, + SKERR_SIRQ_E008MSG); + Para.Para64 = MAC_1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_XA1_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009, + SKERR_SIRQ_E009MSG); + Para.Para64 = MAC_1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_XS2_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010, + SKERR_SIRQ_E010MSG); + Para.Para64 = MAC_2; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_2; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_XA2_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011, + SKERR_SIRQ_E011MSG); + Para.Para64 = MAC_2; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_2; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + /* External reg interrupt */ + if ((Istatus & IS_EXT_REG) != 0) { + /* Test IRQs from PHY */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + pPrt = &pAC->GIni.GP[i]; + + if (pPrt->PState == SK_PRT_RESET) { + continue; + } + + switch (pPrt->PhyType) { + + case SK_PHY_XMAC: + break; + + case SK_PHY_BCOM: + SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt); + SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_MASK, &PhyIMsk); + + if ((PhyInt & ~PhyIMsk) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Port %d Bcom Int: 0x%04X Mask: 0x%04X\n", + i, PhyInt, PhyIMsk)); + SkPhyIsrBcom(pAC, IoC, i, PhyInt); + } + break; + + case SK_PHY_MARV_COPPER: + case SK_PHY_MARV_FIBER: + SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_STAT, &PhyInt); + SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_MASK, &PhyIMsk); + + if ((PhyInt & PhyIMsk) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Port %d Marv Int: 0x%04X Mask: 0x%04X\n", + i, PhyInt, PhyIMsk)); + SkPhyIsrGmac(pAC, IoC, i, PhyInt); + } + break; + +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt); + SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_ENAB, &PhyIMsk); + + if ((PhyInt & PhyIMsk) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Port %d Lone Int: %x Mask: %x\n", + i, PhyInt, PhyIMsk)); + SkPhyIsrLone(pAC, IoC, i, PhyInt); + } + break; + case SK_PHY_NAT: + /* todo: National */ + break; +#endif /* OTHER_PHY */ + } + } + } + + /* I2C Ready interrupt */ + if ((Istatus & IS_I2C_READY) != 0) { + SkI2cIsr(pAC, IoC); + } + + if ((Istatus & IS_LNK_SYNC_M1) != 0) { + /* + * We do NOT need the Link Sync interrupt, because it shows + * us only a link going down. + */ + /* clear interrupt */ + SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LED_CLR_IRQ); + } + + /* Check MAC after link sync counter */ + if ((Istatus & IS_MAC1) != 0) { + /* IRQ from MAC 1 */ + SkMacIrq(pAC, IoC, MAC_1); + } + + if ((Istatus & IS_LNK_SYNC_M2) != 0) { + /* + * We do NOT need the Link Sync interrupt, because it shows + * us only a link going down. + */ + /* clear interrupt */ + SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LED_CLR_IRQ); + } + + /* Check MAC after link sync counter */ + if ((Istatus & IS_MAC2) != 0) { + /* IRQ from MAC 2 */ + SkMacIrq(pAC, IoC, MAC_2); + } + + /* Timer interrupt (served last) */ + if ((Istatus & IS_TIMINT) != 0) { + SkHwtIsr(pAC, IoC); + } +} /* SkGeSirqIsr */ + + +/****************************************************************************** + * + * SkGePortCheckShorts() - Implementing XMAC Workaround Errata # 2 + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + */ +static int SkGePortCheckShorts( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_U32 Shorts; /* Short Event Counter */ + SK_U32 CheckShorts; /* Check value for Short Event Counter */ + SK_U64 RxCts; /* Rx Counter (packets on network) */ + SK_U32 RxTmp; /* Rx temp. Counter */ + SK_U32 FcsErrCts; /* FCS Error Counter */ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Rtv; /* Return value */ + int i; + + pPrt = &pAC->GIni.GP[Port]; + + /* Default: no action */ + Rtv = SK_HW_PS_NONE; + + (void)SkXmUpdateStats(pAC, IoC, Port); + + /* Extra precaution: check for short Event counter */ + (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXE_SHT_ERR, &Shorts); + + /* + * Read Rx counter (packets seen on the network and not necessarily + * really received. + */ + RxCts = 0; + + for (i = 0; i < sizeof(SkGeRxRegs)/sizeof(SkGeRxRegs[0]); i++) { + (void)SkXmMacStatistic(pAC, IoC, Port, SkGeRxRegs[i], &RxTmp); + RxCts += (SK_U64)RxTmp; + } + + /* On default: check shorts against zero */ + CheckShorts = 0; + + /* Extra precaution on active links */ + if (pPrt->PHWLinkUp) { + /* Reset Link Restart counter */ + pPrt->PLinkResCt = 0; + pPrt->PAutoNegTOCt = 0; + + /* If link is up check for 2 */ + CheckShorts = 2; + + (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXF_FCS_ERR, &FcsErrCts); + + if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN && + (pPrt->PLinkMode == SK_LMODE_HALF || + pPrt->PLinkMode == SK_LMODE_FULL)) { + /* + * This is autosensing and we are in the fallback + * manual full/half duplex mode. + */ + if (RxCts == pPrt->PPrevRx) { + /* Nothing received, restart link */ + pPrt->PPrevFcs = FcsErrCts; + pPrt->PPrevShorts = Shorts; + + return(SK_HW_PS_RESTART); + } + else { + pPrt->PLipaAutoNeg = SK_LIPA_MANUAL; + } + } + + if (((RxCts - pPrt->PPrevRx) > pPrt->PRxLim) || + (!(FcsErrCts - pPrt->PPrevFcs))) { + /* + * Note: The compare with zero above has to be done the way shown, + * otherwise the Linux driver will have a problem. + */ + /* + * We received a bunch of frames or no CRC error occured on the + * network -> ok. + */ + pPrt->PPrevRx = RxCts; + pPrt->PPrevFcs = FcsErrCts; + pPrt->PPrevShorts = Shorts; + + return(SK_HW_PS_NONE); + } + + pPrt->PPrevFcs = FcsErrCts; + } + + + if ((Shorts - pPrt->PPrevShorts) > CheckShorts) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Short Event Count Restart Port %d \n", Port)); + Rtv = SK_HW_PS_RESTART; + } + + pPrt->PPrevShorts = Shorts; + pPrt->PPrevRx = RxCts; + + return(Rtv); +} /* SkGePortCheckShorts */ + + +/****************************************************************************** + * + * SkGePortCheckUp() - Check if the link is up + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUp( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + switch (pAC->GIni.GP[Port].PhyType) { + case SK_PHY_XMAC: + return(SkGePortCheckUpXmac(pAC, IoC, Port)); + case SK_PHY_BCOM: + return(SkGePortCheckUpBcom(pAC, IoC, Port)); + case SK_PHY_MARV_COPPER: + case SK_PHY_MARV_FIBER: + return(SkGePortCheckUpGmac(pAC, IoC, Port)); +#ifdef OTHER_PHY + case SK_PHY_LONE: + return(SkGePortCheckUpLone(pAC, IoC, Port)); + case SK_PHY_NAT: + return(SkGePortCheckUpNat(pAC, IoC, Port)); +#endif /* OTHER_PHY */ + } + return(SK_HW_PS_NONE); +} /* SkGePortCheckUp */ + + +/****************************************************************************** + * + * SkGePortCheckUpXmac() - Implementing of the Workaround Errata # 2 + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpXmac( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_U32 Shorts; /* Short Event Counter */ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Done; + SK_U32 GpReg; /* General Purpose register value */ + SK_U16 Isrc; /* Interrupt source register */ + SK_U16 IsrcSum; /* Interrupt source register sum */ + SK_U16 LpAb; /* Link Partner Ability */ + SK_U16 ResAb; /* Resolved Ability */ + SK_U16 ExtStat; /* Extended Status Register */ + SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ + SK_U8 NextMode; /* Next AutoSensing Mode */ + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PHWLinkUp) { + if (pPrt->PhyType != SK_PHY_XMAC) { + return(SK_HW_PS_NONE); + } + else { + return(SkGePortCheckShorts(pAC, IoC, Port)); + } + } + + IsrcSum = pPrt->PIsave; + pPrt->PIsave = 0; + + /* Now wait for each port's link */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + if (pPrt->PLinkBroken) { + /* Link was broken */ + XM_IN32(IoC, Port, XM_GP_PORT, &GpReg); + + if ((GpReg & XM_GP_INP_ASS) == 0) { + /* The Link is in sync */ + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum); + + if ((Isrc & XM_IS_INP_ASS) == 0) { + /* It has been in sync since last time */ + /* Restart the PORT */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link in sync Restart Port %d\n", Port)); + + (void)SkXmUpdateStats(pAC, IoC, Port); + + /* We now need to reinitialize the PrevShorts counter */ + (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXE_SHT_ERR, &Shorts); + pPrt->PPrevShorts = Shorts; + + pPrt->PLinkBroken = SK_FALSE; + + /* + * Link Restart Workaround: + * it may be possible that the other Link side + * restarts its link as well an we detect + * another LinkBroken. To prevent this + * happening we check for a maximum number + * of consecutive restart. If those happens, + * we do NOT restart the active link and + * check whether the link is now o.k. + */ + pPrt->PLinkResCt++; + + pPrt->PAutoNegTimeOut = 0; + + if (pPrt->PLinkResCt < SK_MAX_LRESTART) { + return(SK_HW_PS_RESTART); + } + + pPrt->PLinkResCt = 0; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Do NOT restart on Port %d %x %x\n", Port, Isrc, IsrcSum)); + } + else { + pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Save Sync/nosync Port %d %x %x\n", Port, Isrc, IsrcSum)); + + /* Do nothing more if link is broken */ + return(SK_HW_PS_NONE); + } + } + else { + /* Do nothing more if link is broken */ + return(SK_HW_PS_NONE); + } + + } + else { + /* Link was not broken, check if it is */ + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + if ((Isrc & XM_IS_INP_ASS) != 0) { + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + if ((Isrc & XM_IS_INP_ASS) != 0) { + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + if ((Isrc & XM_IS_INP_ASS) != 0) { + pPrt->PLinkBroken = SK_TRUE; + /* Re-Init Link partner Autoneg flag */ + pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link broken Port %d\n", Port)); + + /* Cable removed-> reinit sense mode */ + SkHWInitDefSense(pAC, IoC, Port); + + return(SK_HW_PS_RESTART); + } + } + } + else { + SkXmAutoNegLipaXmac(pAC, IoC, Port, Isrc); + if (SkGePortCheckShorts(pAC, IoC, Port) == SK_HW_PS_RESTART) { + return(SK_HW_PS_RESTART); + } + } + } + + /* + * here we usually can check whether the link is in sync and + * auto-negotiation is done. + */ + XM_IN32(IoC, Port, XM_GP_PORT, &GpReg); + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + + SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum); + + if ((GpReg & XM_GP_INP_ASS) != 0 || (IsrcSum & XM_IS_INP_ASS) != 0) { + if ((GpReg & XM_GP_INP_ASS) == 0) { + /* Save Auto-negotiation Done interrupt only if link is in sync */ + pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND); + } +#ifdef DEBUG + if ((pPrt->PIsave & XM_IS_AND) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done rescheduled Port %d\n", Port)); + } +#endif /* DEBUG */ + return(SK_HW_PS_NONE); + } + + if (AutoNeg) { + if ((IsrcSum & XM_IS_AND) != 0) { + SkHWLinkUp(pAC, IoC, Port); + Done = SkMacAutoNegDone(pAC, IoC, Port); + if (Done != SK_AND_OK) { + /* Get PHY parameters, for debugging only */ + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LpAb); + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n", + Port, LpAb, ResAb)); + + /* Try next possible mode */ + NextMode = SkHWSenseGetNext(pAC, IoC, Port); + SkHWLinkDown(pAC, IoC, Port); + if (Done == SK_AND_DUP_CAP) { + /* GoTo next mode */ + SkHWSenseSetNext(pAC, IoC, Port, NextMode); + } + + return(SK_HW_PS_RESTART); + } + /* + * Dummy Read extended status to prevent extra link down/ups + * (clear Page Received bit if set) + */ + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_EXP, &ExtStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done Port %d\n", Port)); + return(SK_HW_PS_LINK); + } + + /* AutoNeg not done, but HW link is up. Check for timeouts */ + pPrt->PAutoNegTimeOut++; + if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) { + /* Increase the Timeout counter */ + pPrt->PAutoNegTOCt++; + + /* Timeout occured */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("AutoNeg timeout Port %d\n", Port)); + if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg != SK_LIPA_AUTO) { + /* Set Link manually up */ + SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Set manual full duplex Port %d\n", Port)); + } + + if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg == SK_LIPA_AUTO && + pPrt->PAutoNegTOCt >= SK_MAX_ANEG_TO) { + /* + * This is rather complicated. + * we need to check here whether the LIPA_AUTO + * we saw before is false alert. We saw at one + * switch ( SR8800) that on boot time it sends + * just one auto-neg packet and does no further + * auto-negotiation. + * Solution: we restart the autosensing after + * a few timeouts. + */ + pPrt->PAutoNegTOCt = 0; + pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; + SkHWInitDefSense(pAC, IoC, Port); + } + + /* Do the restart */ + return(SK_HW_PS_RESTART); + } + } + else { + /* Link is up and we don't need more */ +#ifdef DEBUG + if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("ERROR: Lipa auto detected on port %d\n", Port)); + } +#endif /* DEBUG */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link sync(GP), Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + + /* + * Link sync (GP) and so assume a good connection. But if not received + * a bunch of frames received in a time slot (maybe broken tx cable) + * the port is restart. + */ + return(SK_HW_PS_LINK); + } + + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpXmac */ + + +/****************************************************************************** + * + * SkGePortCheckUpBcom() - Check if the link is up on Bcom PHY + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpBcom( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Done; + SK_U16 Isrc; /* Interrupt source register */ + SK_U16 PhyStat; /* Phy Status Register */ + SK_U16 ResAb; /* Master/Slave resolution */ + SK_U16 Ctrl; /* Broadcom control flags */ +#ifdef DEBUG + SK_U16 LpAb; + SK_U16 ExtStat; +#endif /* DEBUG */ + SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Check for No HCD Link events (#10523) */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &Isrc); + +#ifdef xDEBUG + if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT) == + (PHY_B_IS_SCR_S_ER | PHY_B_IS_RRS_CHANGE | PHY_B_IS_LRS_CHANGE)) { + + SK_U32 Stat1, Stat2, Stat3; + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1); + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "CheckUp1 - Stat: %x, Mask: %x", + (void *)Isrc, + (void *)Stat1); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "Ctrl/Stat: %x, AN Adv/LP: %x", + (void *)Stat1, + (void *)Stat2); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x", + (void *)Stat1, + (void *)Stat2); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x", + (void *)Stat1, + (void *)Stat2); + } +#endif /* DEBUG */ + + if ((Isrc & (PHY_B_IS_NO_HDCL /* | PHY_B_IS_NO_HDC */)) != 0) { + /* + * Workaround BCom Errata: + * enable and disable loopback mode if "NO HCD" occurs. + */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Ctrl); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, + (SK_U16)(Ctrl | PHY_CT_LOOP)); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, + (SK_U16)(Ctrl & ~PHY_CT_LOOP)); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("No HCD Link event, Port %d\n", Port)); +#ifdef xDEBUG + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "No HCD link event, port %d.", + (void *)Port, + (void *)NULL); +#endif /* DEBUG */ + } + + /* Not obsolete: link status bit is latched to 0 and autoclearing! */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat); + + if (pPrt->PHWLinkUp) { + return(SK_HW_PS_NONE); + } + +#ifdef xDEBUG + { + SK_U32 Stat1, Stat2, Stat3; + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1); + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "CheckUp1a - Stat: %x, Mask: %x", + (void *)Isrc, + (void *)Stat1); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat); + Stat1 = Stat1 << 16 | PhyStat; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "Ctrl/Stat: %x, AN Adv/LP: %x", + (void *)Stat1, + (void *)Stat2); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb); + Stat2 = Stat2 << 16 | ResAb; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x", + (void *)Stat1, + (void *)Stat2); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x", + (void *)Stat1, + (void *)Stat2); + } +#endif /* DEBUG */ + + /* Now wait for each port's link */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + /* + * Here we usually can check whether the link is in sync and + * auto-negotiation is done. + */ + + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat); + + SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat)); + + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb); + + if ((ResAb & PHY_B_1000S_MSF) != 0) { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + + return(SK_HW_PS_RESTART); + } + + if ((PhyStat & PHY_ST_LSYNC) == 0) { + return(SK_HW_PS_NONE); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat)); + + if (AutoNeg) { + if ((PhyStat & PHY_ST_AN_OVER) != 0) { + SkHWLinkUp(pAC, IoC, Port); + Done = SkMacAutoNegDone(pAC, IoC, Port); + if (Done != SK_AND_OK) { +#ifdef DEBUG + /* Get PHY parameters, for debugging only */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LpAb); + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ExtStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n", + Port, LpAb, ExtStat)); +#endif /* DEBUG */ + return(SK_HW_PS_RESTART); + } + else { +#ifdef xDEBUG + /* Dummy read ISR to prevent extra link downs/ups */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat); + + if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) { + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "CheckUp2 - Stat: %x", + (void *)ExtStat, + (void *)NULL); + } +#endif /* DEBUG */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done Port %d\n", Port)); + return(SK_HW_PS_LINK); + } + } + } + else { /* !AutoNeg */ + /* Link is up and we don't need more. */ +#ifdef DEBUG + if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("ERROR: Lipa auto detected on port %d\n", Port)); + } +#endif /* DEBUG */ + +#ifdef xDEBUG + /* Dummy read ISR to prevent extra link downs/ups */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat); + + if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) { + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "CheckUp3 - Stat: %x", + (void *)ExtStat, + (void *)NULL); + } +#endif /* DEBUG */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link sync(GP), Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + return(SK_HW_PS_LINK); + } + + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpBcom */ + + +/****************************************************************************** + * + * SkGePortCheckUpGmac() - Check if the link is up on Marvell PHY + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpGmac( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Done; + SK_U16 Isrc; /* Interrupt source */ + SK_U16 PhyStat; /* Phy Status */ + SK_U16 PhySpecStat;/* Phy Specific Status */ + SK_U16 ResAb; /* Master/Slave resolution */ + SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Read PHY Interrupt Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &Isrc); + + if ((Isrc & PHY_M_IS_AN_COMPL) != 0) { + /* TBD */ + } + + if ((Isrc & PHY_M_IS_DOWNSH_DET) != 0) { + /* TBD */ + } + + if (pPrt->PHWLinkUp) { + return(SK_HW_PS_NONE); + } + + /* Now wait for each port's link */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + /* Read PHY Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat)); + + SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat); + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb); + + if ((ResAb & PHY_B_1000S_MSF) != 0) { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + + return(SK_HW_PS_RESTART); + } + + /* Read PHY Specific Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg: %d, PhySpecStat: 0x%04x\n", AutoNeg, PhySpecStat)); + + if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) { + return(SK_HW_PS_NONE); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; + + pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7); + + if (AutoNeg) { + /* Auto-Negotiation Over ? */ + if ((PhyStat & PHY_ST_AN_OVER) != 0) { + + SkHWLinkUp(pAC, IoC, Port); + + Done = SkMacAutoNegDone(pAC, IoC, Port); + + if (Done != SK_AND_OK) { + return(SK_HW_PS_RESTART); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done Port %d\n", Port)); + return(SK_HW_PS_LINK); + } + } + else { /* !AutoNeg */ + /* Link is up and we don't need more */ +#ifdef DEBUG + if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("ERROR: Lipa auto detected on port %d\n", Port)); + } +#endif /* DEBUG */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link sync, Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + + return(SK_HW_PS_LINK); + } + + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpGmac */ + + +#ifdef OTHER_PHY +/****************************************************************************** + * + * SkGePortCheckUpLone() - Check if the link is up on Level One PHY + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpLone( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Done; + SK_U16 Isrc; /* Interrupt source register */ + SK_U16 LpAb; /* Link Partner Ability */ + SK_U16 ExtStat; /* Extended Status Register */ + SK_U16 PhyStat; /* Phy Status Register */ + SK_U16 StatSum; + SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ + SK_U8 NextMode; /* Next AutoSensing Mode */ + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PHWLinkUp) { + return(SK_HW_PS_NONE); + } + + StatSum = pPrt->PIsave; + pPrt->PIsave = 0; + + /* Now wait for each ports link */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + /* + * here we usually can check whether the link is in sync and + * auto-negotiation is done. + */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_STAT, &PhyStat); + StatSum |= PhyStat; + + SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat); + + if ((PhyStat & PHY_ST_LSYNC) == 0) { + /* Save Auto-negotiation Done bit */ + pPrt->PIsave = (SK_U16)(StatSum & PHY_ST_AN_OVER); +#ifdef DEBUG + if ((pPrt->PIsave & PHY_ST_AN_OVER) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done rescheduled Port %d\n", Port)); + } +#endif /* DEBUG */ + return(SK_HW_PS_NONE); + } + + if (AutoNeg) { + if ((StatSum & PHY_ST_AN_OVER) != 0) { + SkHWLinkUp(pAC, IoC, Port); + Done = SkMacAutoNegDone(pAC, IoC, Port); + if (Done != SK_AND_OK) { + /* Get PHY parameters, for debugging only */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LpAb); + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ExtStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n", + Port, LpAb, ExtStat)); + + /* Try next possible mode */ + NextMode = SkHWSenseGetNext(pAC, IoC, Port); + SkHWLinkDown(pAC, IoC, Port); + if (Done == SK_AND_DUP_CAP) { + /* GoTo next mode */ + SkHWSenseSetNext(pAC, IoC, Port, NextMode); + } + + return(SK_HW_PS_RESTART); + + } + else { + /* + * Dummy Read interrupt status to prevent + * extra link down/ups + */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done Port %d\n", Port)); + return(SK_HW_PS_LINK); + } + } + + /* AutoNeg not done, but HW link is up. Check for timeouts */ + pPrt->PAutoNegTimeOut++; + if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) { + /* Timeout occured */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("AutoNeg timeout Port %d\n", Port)); + if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg != SK_LIPA_AUTO) { + /* Set Link manually up */ + SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Set manual full duplex Port %d\n", Port)); + } + + /* Do the restart */ + return(SK_HW_PS_RESTART); + } + } + else { + /* Link is up and we don't need more */ +#ifdef DEBUG + if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("ERROR: Lipa auto detected on port %d\n", Port)); + } +#endif /* DEBUG */ + + /* + * Dummy Read interrupt status to prevent + * extra link down/ups + */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link sync(GP), Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + return(SK_HW_PS_LINK); + } + + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpLone */ + + +/****************************************************************************** + * + * SkGePortCheckUpNat() - Check if the link is up on National PHY + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpNat( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + /* todo: National */ + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpNat */ +#endif /* OTHER_PHY */ + + +/****************************************************************************** + * + * SkGeSirqEvent() - Event Service Routine + * + * Description: + * + * Notes: + */ +int SkGeSirqEvent( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* Io Context */ +SK_U32 Event, /* Module specific Event */ +SK_EVPARA Para) /* Event specific Parameter */ +{ + SK_U64 Octets; + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_U32 Port; + SK_U32 Time; + unsigned Len; + int PortStat; + SK_U8 Val8; + + Port = Para.Para32[0]; + pPrt = &pAC->GIni.GP[Port]; + + switch (Event) { + case SK_HWEV_WATIM: + /* Check whether port came up */ + PortStat = SkGePortCheckUp(pAC, IoC, Port); + + switch (PortStat) { + case SK_HW_PS_RESTART: + if (pPrt->PHWLinkUp) { + /* + * Set Link to down. + */ + SkHWLinkDown(pAC, IoC, Port); + + /* + * Signal directly to RLMT to ensure correct + * sequence of SWITCH and RESET event. + */ + SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para); + } + + /* Restart needed */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para); + break; + + case SK_HW_PS_LINK: + /* Signal to RLMT */ + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para); + break; + + } + + /* Start again the check Timer */ + if (pPrt->PHWLinkUp) { + Time = SK_WA_ACT_TIME; + } + else { + Time = SK_WA_INA_TIME; + } + + /* Todo: still needed for non-XMAC PHYs??? */ + /* Start workaround Errata #2 timer */ + SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Time, + SKGE_HWAC, SK_HWEV_WATIM, Para); + break; + + case SK_HWEV_PORT_START: + if (pPrt->PHWLinkUp) { + /* + * Signal directly to RLMT to ensure correct + * sequence of SWITCH and RESET event. + */ + SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para); + } + + SkHWLinkDown(pAC, IoC, Port); + + /* Schedule Port RESET */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para); + + /* Start workaround Errata #2 timer */ + SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME, + SKGE_HWAC, SK_HWEV_WATIM, Para); + break; + + case SK_HWEV_PORT_STOP: + if (pPrt->PHWLinkUp) { + /* + * Signal directly to RLMT to ensure correct + * sequence of SWITCH and RESET event. + */ + SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para); + } + + /* Stop Workaround Timer */ + SkTimerStop(pAC, IoC, &pPrt->PWaTimer); + + SkHWLinkDown(pAC, IoC, Port); + break; + + case SK_HWEV_UPDATE_STAT: + /* We do NOT need to update any statistics */ + break; + + case SK_HWEV_CLEAR_STAT: + /* We do NOT need to clear any statistics */ + for (Port = 0; Port < (SK_U32)pAC->GIni.GIMacsFound; Port++) { + pPrt->PPrevRx = 0; + pPrt->PPrevFcs = 0; + pPrt->PPrevShorts = 0; + } + break; + + case SK_HWEV_SET_LMODE: + Val8 = (SK_U8)Para.Para32[1]; + if (pPrt->PLinkModeConf != Val8) { + /* Set New link mode */ + pPrt->PLinkModeConf = Val8; + + /* Restart Port */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para); + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); + } + break; + + case SK_HWEV_SET_FLOWMODE: + Val8 = (SK_U8)Para.Para32[1]; + if (pPrt->PFlowCtrlMode != Val8) { + /* Set New Flow Control mode */ + pPrt->PFlowCtrlMode = Val8; + + /* Restart Port */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para); + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); + } + break; + + case SK_HWEV_SET_ROLE: + /* not possible for fiber */ + if (!pAC->GIni.GICopperType) { + break; + } + Val8 = (SK_U8)Para.Para32[1]; + if (pPrt->PMSMode != Val8) { + /* Set New link mode */ + pPrt->PMSMode = Val8; + + /* Restart Port */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para); + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); + } + break; + + case SK_HWEV_SET_SPEED: + if (pPrt->PhyType != SK_PHY_MARV_COPPER) { + break; + } + Val8 = (SK_U8)Para.Para32[1]; + if (pPrt->PLinkSpeed != Val8) { + /* Set New Speed parameter */ + pPrt->PLinkSpeed = Val8; + + /* Restart Port */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para); + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); + } + break; + + case SK_HWEV_HALFDUP_CHK: + /* + * half duplex hangup workaround. + * See packet arbiter timeout interrupt for description + */ + pPrt->HalfDupTimerActive = SK_FALSE; + if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) { + + Len = sizeof(SK_U64); + SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets, + &Len, (SK_U32)SK_PNMI_PORT_PHYS2INST(pAC, Port), + pAC->Rlmt.Port[Port].Net->NetNumber); + + if (pPrt->LastOctets == Octets) { + /* Tx hanging, a FIFO flush restarts it */ + SkMacFlushTxFifo(pAC, IoC, Port); + } + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG); + break; + } + + return(0); +} /* SkGeSirqEvent */ + + +/****************************************************************************** + * + * SkPhyIsrBcom() - PHY interrupt service routine + * + * Description: handles all interrupts from BCom PHY + * + * Returns: N/A + */ +static void SkPhyIsrBcom( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* Io Context */ +int Port, /* Port Num = PHY Num */ +SK_U16 IStatus) /* Interrupt Status */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_EVPARA Para; + + pPrt = &pAC->GIni.GP[Port]; + + if ((IStatus & PHY_B_IS_PSE) != 0) { + /* Incorrectable pair swap error */ + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E022, + SKERR_SIRQ_E022MSG); + } + + if ((IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) != 0) { + Para.Para32[0] = (SK_U32)Port; + + SkHWLinkDown(pAC, IoC, Port); + + /* Signal to RLMT */ + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + + /* Start workaround Errata #2 timer */ + SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME, + SKGE_HWAC, SK_HWEV_WATIM, Para); + } + +} /* SkPhyIsrBcom */ + + +/****************************************************************************** + * + * SkPhyIsrGmac() - PHY interrupt service routine + * + * Description: handles all interrupts from Marvell PHY + * + * Returns: N/A + */ +static void SkPhyIsrGmac( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* Io Context */ +int Port, /* Port Num = PHY Num */ +SK_U16 IStatus) /* Interrupt Status */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_EVPARA Para; + + pPrt = &pAC->GIni.GP[Port]; + + if ((IStatus & (PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE)) != 0) { + Para.Para32[0] = (SK_U32)Port; + + SkHWLinkDown(pAC, IoC, Port); + + /* Signal to RLMT */ + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((IStatus & PHY_M_IS_AN_ERROR) != 0) { + /* Auto-Negotiation Error */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG); + } + + if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) { + /* TBD */ + } + + if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) { + /* FIFO Overflow/Underrun Error */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG); + } +} /* SkPhyIsrGmac */ + + +#ifdef OTHER_PHY +/****************************************************************************** + * + * SkPhyIsrLone() - PHY interrupt service routine + * + * Description: handles all interrupts from LONE PHY + * + * Returns: N/A + */ +static void SkPhyIsrLone( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* Io Context */ +int Port, /* Port Num = PHY Num */ +SK_U16 IStatus) /* Interrupt Status */ +{ + SK_EVPARA Para; + + if (IStatus & (PHY_L_IS_DUP | PHY_L_IS_ISOL)) { + SkHWLinkDown(pAC, IoC, Port); + + /* Signal to RLMT */ + Para.Para32[0] = (SK_U32)Port; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + +} /* SkPhyIsrLone */ +#endif /* OTHER_PHY */ + +#endif /* CONFIG_SK98 */ + +/* End of File */ diff --git a/drivers/sk98lin/ski2c.c b/drivers/sk98lin/ski2c.c new file mode 100644 index 0000000..2ab635a --- /dev/null +++ b/drivers/sk98lin/ski2c.c @@ -0,0 +1,1505 @@ +/****************************************************************************** + * + * Name: ski2c.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.57 $ + * Date: $Date: 2003/01/28 09:17:38 $ + * Purpose: Functions to access Voltage and Temperature Sensor + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: ski2c.c,v $ + * Revision 1.57 2003/01/28 09:17:38 rschmidt + * Fixed handling for sensors on YUKON Fiber. + * Editorial changes. + * + * Revision 1.56 2002/12/19 14:20:41 rschmidt + * Added debugging code in SkI2cWait(). + * Replaced all I2C-write operations with function SkI2cWrite(). + * Fixed compiler warning because of uninitialized 'Time' in SkI2cEvent(). + * Editorial changes. + * + * Revision 1.55 2002/10/15 07:23:55 rschmidt + * Added setting of the GIYukon32Bit bool variable to distinguish + * 32-bit adapters. + * Editorial changes (TWSI). + * + * Revision 1.54 2002/08/13 09:05:06 rschmidt + * Added new thresholds if VAUX is not available (GIVauxAvail). + * Merged defines for PHY PLL 3V3 voltage (A and B). + * Editorial changes. + * + * Revision 1.53 2002/08/08 11:04:53 rwahl + * Added missing comment for revision 1.51 + * + * Revision 1.52 2002/08/08 10:09:02 jschmalz + * Sensor init state caused wrong error log entry + * + * Revision 1.51 2002/08/06 09:43:03 jschmalz + * Extensions and changes for Yukon + * + * Revision 1.50 2002/08/02 12:09:22 rschmidt + * Added support for YUKON sensors. + * Editorial changes. + * + * Revision 1.49 2002/07/30 11:07:52 rschmidt + * Replaced MaxSens init by update for Copper in SkI2cInit1(), + * because it was already initialized in SkI2cInit0(). + * Editorial changes. + * + * Revision 1.48 2001/08/16 12:44:33 afischer + * LM80 sensor init values corrected + * + * Revision 1.47 2001/04/05 11:38:09 rassmann + * Set SenState to idle in SkI2cWaitIrq(). + * Changed error message in SkI2cWaitIrq(). + * + * Revision 1.46 2001/04/02 14:03:35 rassmann + * Changed pAC to IoC in SK_IN32(). + * + * Revision 1.45 2001/03/21 12:12:49 rassmann + * Resetting I2C_READY interrupt in SkI2cInit1(). + * + * Revision 1.44 2000/08/07 15:49:03 gklug + * Fix: SK_INFAST only in NetWare driver. + * + * Revision 1.43 2000/08/03 14:28:17 rassmann + * Added function to wait for I2C being ready before resetting the board. + * Replaced one duplicate "out of range" message with correct one. + * + * Revision 1.42 1999/11/22 13:35:12 cgoos + * Changed license header to GPL. + * + * Revision 1.41 1999/09/14 14:11:30 malthoff + * The 1000BT Dual Link adapter has got only one Fan. + * The second Fan has been removed. + * + * Revision 1.40 1999/05/27 13:37:27 malthoff + * Set divisor of 1 for fan count calculation. + * + * Revision 1.39 1999/05/20 14:54:43 malthoff + * I2c.DummyReads is not used in Diagnostics. + * + * Revision 1.38 1999/05/20 09:20:56 cgoos + * Changes for 1000Base-T (up to 9 sensors and fans). + * + * Revision 1.37 1999/03/25 15:11:36 gklug + * fix: reset error flag if sensor reads correct value + * + * Revision 1.36 1999/01/07 14:11:16 gklug + * fix: break added + * + * Revision 1.35 1999/01/05 15:31:49 gklug + * fix: CLEAR STAT command is now added correctly + * + * Revision 1.34 1998/12/01 13:45:16 gklug + * fix: introduced Init level, because we don't need reinits + * + * Revision 1.33 1998/11/09 14:54:25 malthoff + * Modify I2C Transfer Timeout handling for Diagnostics. + * + * Revision 1.32 1998/11/03 06:54:35 gklug + * fix: Need dummy reads at the beginning to init sensors + * + * Revision 1.31 1998/11/03 06:42:42 gklug + * fix: select correctVIO range only if between warning levels + * + * Revision 1.30 1998/11/02 07:36:53 gklug + * fix: Error should not include WARNING message + * + * Revision 1.29 1998/10/30 15:07:43 malthoff + * Disable 'I2C does not compelete' error log for diagnostics. + * + * Revision 1.28 1998/10/22 09:48:11 gklug + * fix: SysKonnectFileId typo + * + * Revision 1.27 1998/10/20 09:59:46 gklug + * add: parameter to SkOsGetTime + * + * Revision 1.26 1998/10/09 06:10:59 malthoff + * Remove ID_sccs by SysKonnectFileId. + * + * Revision 1.25 1998/09/08 12:40:26 gklug + * fix: syntax error in if clause + * + * Revision 1.24 1998/09/08 12:19:42 gklug + * chg: INIT Level checking + * + * Revision 1.23 1998/09/08 07:37:20 gklug + * fix: log error if PCI_IO voltage sensor could not be initialized + * + * Revision 1.22 1998/09/04 08:30:03 malthoff + * Bugfixes during SK_DIAG testing: + * - correct NS2BCLK() macro + * - correct SkI2cSndDev() + * - correct SkI2cWait() loop waiting for an event + * + * Revision 1.21 1998/08/27 14:46:01 gklug + * chg: if-then-else replaced by switch + * + * Revision 1.20 1998/08/27 14:40:07 gklug + * test: integral types + * + * Revision 1.19 1998/08/25 07:51:54 gklug + * fix: typos for compiling + * + * Revision 1.18 1998/08/25 06:12:24 gklug + * add: count errors and warnings + * fix: check not the sensor state but the ErrFlag! + * + * Revision 1.17 1998/08/25 05:56:48 gklug + * add: CheckSensor function + * + * Revision 1.16 1998/08/20 11:41:10 gklug + * chg: omit STRCPY macro by using char * as Sensor Description + * + * Revision 1.15 1998/08/20 11:37:35 gklug + * chg: change Ioc to IoC + * + * Revision 1.14 1998/08/20 11:32:52 gklug + * fix: Para compile error + * + * Revision 1.13 1998/08/20 11:27:41 gklug + * fix: Compile bugs with new awrning constants + * + * Revision 1.12 1998/08/20 08:53:05 gklug + * fix: compiler errors + * add: Threshold values + * + * Revision 1.11 1998/08/19 12:39:22 malthoff + * Compiler Fix: Some names have changed. + * + * Revision 1.10 1998/08/19 12:20:56 gklug + * fix: remove struct from C files (see CCC) + * + * Revision 1.9 1998/08/19 06:28:46 malthoff + * SkOsGetTime returns SK_U64 now. + * + * Revision 1.8 1998/08/17 13:53:33 gklug + * fix: Parameter of event function and its result + * + * Revision 1.7 1998/08/17 07:02:15 malthoff + * Modify the functions for accessing the I2C SW Registers. + * Modify SkI2cWait(). + * Put Lm80RcvReg into sklm80.c + * Remove Compiler Errors. + * + * Revision 1.6 1998/08/14 07:13:20 malthoff + * remove pAc with pAC + * remove smc with pAC + * change names to new convention + * + * Revision 1.5 1998/08/14 06:24:49 gklug + * add: init level 1 and 2 + * + * Revision 1.4 1998/08/12 14:31:12 gklug + * add: error log for unknown event + * + * Revision 1.3 1998/08/12 13:37:04 gklug + * add: Init 0 function + * + * Revision 1.2 1998/08/11 07:27:15 gklug + * add: functions of the interface + * adapt rest of source to C coding Conventions + * rmv: unnecessary code taken from Mona Lisa + * + * Revision 1.1 1998/06/19 14:28:43 malthoff + * Created. Sources taken from ML Projekt. + * Sources have to be reworked for GE. + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + * I2C Protocol + */ +static const char SysKonnectFileId[] = + "$Id: ski2c.c,v 1.57 2003/01/28 09:17:38 rschmidt Exp $"; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/lm80.h" +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef __C2MAN__ +/* + I2C protocol implementation. + + General Description: + + The I2C protocol is used for the temperature sensors and for + the serial EEPROM which hold the configuration. + + This file covers functions that allow to read write and do + some bulk requests a specified I2C address. + + The Genesis has 2 I2C buses. One for the EEPROM which holds + the VPD Data and one for temperature and voltage sensor. + The following picture shows the I2C buses, I2C devices and + their control registers. + + Note: The VPD functions are in skvpd.c +. +. PCI Config I2C Bus for VPD Data: +. +. +------------+ +. | VPD EEPROM | +. +------------+ +. | +. | <-- I2C +. | +. +-----------+-----------+ +. | | +. +-----------------+ +-----------------+ +. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG | +. +-----------------+ +-----------------+ +. +. +. I2C Bus for LM80 sensor: +. +. +-----------------+ +. | Temperature and | +. | Voltage Sensor | +. | LM80 | +. +-----------------+ +. | +. | +. I2C --> | +. | +. +----+ +. +-------------->| OR |<--+ +. | +----+ | +. +------+------+ | +. | | | +. +--------+ +--------+ +----------+ +. | B2_I2C | | B2_I2C | | B2_I2C | +. | _CTRL | | _DATA | | _SW | +. +--------+ +--------+ +----------+ +. + The I2C bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL + and B2_I2C_DATA registers. + For driver software it is recommended to use the I2C control and + data register, because I2C bus timing is done by the ASIC and + an interrupt may be received when the I2C request is completed. + + Clock Rate Timing: MIN MAX generated by + VPD EEPROM: 50 kHz 100 kHz HW + LM80 over I2C Ctrl/Data reg. 50 kHz 100 kHz HW + LM80 over B2_I2C_SW register 0 400 kHz SW + + Note: The clock generated by the hardware is dependend on the + PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD + clock is 50 kHz. + */ +intro() +{} +#endif + +#ifdef SK_DIAG +/* + * I2C Fast Mode timing values used by the LM80. + * If new devices are added to the I2C bus the timing values have to be checked. + */ +#ifndef I2C_SLOW_TIMING +#define T_CLK_LOW 1300L /* clock low time in ns */ +#define T_CLK_HIGH 600L /* clock high time in ns */ +#define T_DATA_IN_SETUP 100L /* data in Set-up Time */ +#define T_START_HOLD 600L /* start condition hold time */ +#define T_START_SETUP 600L /* start condition Set-up time */ +#define T_STOP_SETUP 600L /* stop condition Set-up time */ +#define T_BUS_IDLE 1300L /* time the bus must free after Tx */ +#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */ +#else /* I2C_SLOW_TIMING */ +/* I2C Standard Mode Timing */ +#define T_CLK_LOW 4700L /* clock low time in ns */ +#define T_CLK_HIGH 4000L /* clock high time in ns */ +#define T_DATA_IN_SETUP 250L /* data in Set-up Time */ +#define T_START_HOLD 4000L /* start condition hold time */ +#define T_START_SETUP 4700L /* start condition Set-up time */ +#define T_STOP_SETUP 4000L /* stop condition Set-up time */ +#define T_BUS_IDLE 4700L /* time the bus must free after Tx */ +#endif /* !I2C_SLOW_TIMING */ + +#define NS2BCLK(x) (((x)*125)/10000) + +/* + * I2C Wire Operations + * + * About I2C_CLK_LOW(): + * + * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting + * clock to low, to prevent the ASIC and the I2C data client from driving the + * serial data line simultaneously (ASIC: last bit of a byte = '1', I2C client + * send an 'ACK'). See also Concentrator Bugreport No. 10192. + */ +#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA) +#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA) +#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA_DIR) +#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA) +#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_CLK) +#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR) +#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK) + +#define NS2CLKT(x) ((x*125L)/10000) + +/*--------------- I2C Interface Register Functions --------------- */ + +/* + * sending one bit + */ +void SkI2cSndBit( +SK_IOC IoC, /* I/O Context */ +SK_U8 Bit) /* Bit to send */ +{ + I2C_DATA_OUT(IoC); + if (Bit) { + I2C_DATA_HIGH(IoC); + } + else { + I2C_DATA_LOW(IoC); + } + SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP)); + I2C_CLK_HIGH(IoC); + SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH)); + I2C_CLK_LOW(IoC); +} /* SkI2cSndBit*/ + + +/* + * Signal a start to the I2C Bus. + * + * A start is signaled when data goes to low in a high clock cycle. + * + * Ends with Clock Low. + * + * Status: not tested + */ +void SkI2cStart( +SK_IOC IoC) /* I/O Context */ +{ + /* Init data and Clock to output lines */ + /* Set Data high */ + I2C_DATA_OUT(IoC); + I2C_DATA_HIGH(IoC); + /* Set Clock high */ + I2C_CLK_HIGH(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP)); + + /* Set Data Low */ + I2C_DATA_LOW(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD)); + + /* Clock low without Data to Input */ + I2C_START_COND(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW)); +} /* SkI2cStart */ + + +void SkI2cStop( +SK_IOC IoC) /* I/O Context */ +{ + /* Init data and Clock to output lines */ + /* Set Data low */ + I2C_DATA_OUT(IoC); + I2C_DATA_LOW(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT)); + + /* Set Clock high */ + I2C_CLK_HIGH(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP)); + + /* + * Set Data High: Do it by setting the Data Line to Input. + * Because of a pull up resistor the Data Line + * floods to high. + */ + I2C_DATA_IN(IoC); + + /* + * When I2C activity is stopped + * o DATA should be set to input and + * o CLOCK should be set to high! + */ + SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE)); +} /* SkI2cStop */ + + +/* + * Receive just one bit via the I2C bus. + * + * Note: Clock must be set to LOW before calling this function. + * + * Returns The received bit. + */ +int SkI2cRcvBit( +SK_IOC IoC) /* I/O Context */ +{ + int Bit; + SK_U8 I2cSwCtrl; + + /* Init data as input line */ + I2C_DATA_IN(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT)); + + I2C_CLK_HIGH(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH)); + + SK_I2C_GET_SW(IoC, &I2cSwCtrl); + + Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0; + + I2C_CLK_LOW(IoC); + SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT)); + + return(Bit); +} /* SkI2cRcvBit */ + + +/* + * Receive an ACK. + * + * returns 0 If acknowledged + * 1 in case of an error + */ +int SkI2cRcvAck( +SK_IOC IoC) /* I/O Context */ +{ + /* + * Received bit must be zero. + */ + return(SkI2cRcvBit(IoC) != 0); +} /* SkI2cRcvAck */ + + +/* + * Send an NACK. + */ +void SkI2cSndNAck( +SK_IOC IoC) /* I/O Context */ +{ + /* + * Received bit must be zero. + */ + SkI2cSndBit(IoC, 1); +} /* SkI2cSndNAck */ + + +/* + * Send an ACK. + */ +void SkI2cSndAck( +SK_IOC IoC) /* I/O Context */ +{ + /* + * Received bit must be zero. + * + */ + SkI2cSndBit(IoC, 0); +} /* SkI2cSndAck */ + + +/* + * Send one byte to the I2C device and wait for ACK. + * + * Return acknowleged status. + */ +int SkI2cSndByte( +SK_IOC IoC, /* I/O Context */ +int Byte) /* byte to send */ +{ + int i; + + for (i = 0; i < 8; i++) { + if (Byte & (1<<(7-i))) { + SkI2cSndBit(IoC, 1); + } + else { + SkI2cSndBit(IoC, 0); + } + } + + return(SkI2cRcvAck(IoC)); +} /* SkI2cSndByte */ + + +/* + * Receive one byte and ack it. + * + * Return byte. + */ +int SkI2cRcvByte( +SK_IOC IoC, /* I/O Context */ +int Last) /* Last Byte Flag */ +{ + int i; + int Byte = 0; + + for (i = 0; i < 8; i++) { + Byte <<= 1; + Byte |= SkI2cRcvBit(IoC); + } + + if (Last) { + SkI2cSndNAck(IoC); + } + else { + SkI2cSndAck(IoC); + } + + return(Byte); +} /* SkI2cRcvByte */ + + +/* + * Start dialog and send device address + * + * Return 0 if acknowleged, 1 in case of an error + */ +int SkI2cSndDev( +SK_IOC IoC, /* I/O Context */ +int Addr, /* Device Address */ +int Rw) /* Read / Write Flag */ +{ + SkI2cStart(IoC); + Rw = ~Rw; + Rw &= I2C_WRITE; + return(SkI2cSndByte(IoC, (Addr<<1) | Rw)); +} /* SkI2cSndDev */ + +#endif /* SK_DIAG */ + +/*----------------- I2C CTRL Register Functions ----------*/ + +/* + * waits for a completion of an I2C transfer + * + * returns 0: success, transfer completes + * 1: error, transfer does not complete, I2C transfer + * killed, wait loop terminated. + */ +int SkI2cWait( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */ +{ + SK_U64 StartTime; + SK_U64 CurrentTime; + SK_U32 I2cCtrl; + + StartTime = SkOsGetTime(pAC); + + do { + CurrentTime = SkOsGetTime(pAC); + + if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) { + + SK_I2C_STOP(IoC); +#ifndef SK_DIAG + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG); +#endif /* !SK_DIAG */ + return(1); + } + + SK_I2C_GET_CTL(IoC, &I2cCtrl); + +#ifdef xYUKON_DBG + printf("StartTime=%lu, CurrentTime=%lu\n", + StartTime, CurrentTime); + if (kbhit()) { + return(1); + } +#endif /* YUKON_DBG */ + + } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31); + + return(0); +} /* SkI2cWait */ + + +/* + * waits for a completion of an I2C transfer + * + * Returns + * Nothing + */ +void SkI2cWaitIrq( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + SK_SENSOR *pSen; + SK_U64 StartTime; + SK_U32 IrqSrc; + + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + + if (pSen->SenState == SK_SEN_IDLE) { + return; + } + + StartTime = SkOsGetTime(pAC); + do { + if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) { + SK_I2C_STOP(IoC); +#ifndef SK_DIAG + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG); +#endif /* !SK_DIAG */ + return; + } + SK_IN32(IoC, B0_ISRC, &IrqSrc); + } while ((IrqSrc & IS_I2C_READY) == 0); + + pSen->SenState = SK_SEN_IDLE; + return; +} /* SkI2cWaitIrq */ + +/* + * writes a single byte or 4 bytes into the I2C device + * + * returns 0: success + * 1: error + */ +int SkI2cWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 I2cData, /* I2C Data to write */ +int I2cDev, /* I2C Device Address */ +int I2cReg, /* I2C Device Register Address */ +int I2cBurst) /* I2C Burst Flag */ +{ + SK_OUT32(IoC, B2_I2C_DATA, I2cData); + SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cReg, I2cBurst); + + return(SkI2cWait(pAC, IoC, I2C_WRITE)); +} /* SkI2cWrite*/ + + +#ifdef SK_DIAG + +/* + * reads a single byte or 4 bytes from the I2C device + * + * returns the word read + */ +SK_U32 SkI2cRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int I2cDev, /* I2C Device Address */ +int I2cReg, /* I2C Device Register Address */ +int I2cBurst) /* I2C Burst Flag */ +{ + SK_U32 Data; + + SK_OUT32(IoC, B2_I2C_DATA, 0); + SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cReg, I2cBurst); + + if (SkI2cWait(pAC, IoC, I2C_READ) != 0) { + w_print("%s\n", SKERR_I2C_E002MSG); + } + + SK_IN32(IoC, B2_I2C_DATA, &Data); + return(Data); +} /* SkI2cRead */ + +#endif /* SK_DIAG */ + + +/* + * read a sensor's value + * + * This function reads a sensor's value from the I2C sensor chip. The sensor + * is defined by its index into the sensors database in the struct pAC points + * to. + * Returns + * 1 if the read is completed + * 0 if the read must be continued (I2C Bus still allocated) + */ +int SkI2cReadSensor( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_SENSOR *pSen) /* Sensor to be read */ +{ + if (pSen->SenRead != NULL) { + return((*pSen->SenRead)(pAC, IoC, pSen)); + } + else + return(0); /* no success */ +} /* SkI2cReadSensor*/ + +/* + * Do the Init state 0 initialization + */ +static int SkI2cInit0( +SK_AC *pAC) /* Adapter Context */ +{ + int i; + + /* Begin with first sensor */ + pAC->I2c.CurrSens = 0; + + /* Begin with timeout control for state machine */ + pAC->I2c.TimerMode = SK_TIMER_WATCH_STATEMACHINE; + + /* Set sensor number to zero */ + pAC->I2c.MaxSens = 0; + +#ifndef SK_DIAG + /* Initialize Number of Dummy Reads */ + pAC->I2c.DummyReads = SK_MAX_SENSORS; +#endif + + for (i = 0; i < SK_MAX_SENSORS; i++) { + pAC->I2c.SenTable[i].SenDesc = "unknown"; + pAC->I2c.SenTable[i].SenType = SK_SEN_UNKNOWN; + pAC->I2c.SenTable[i].SenThreErrHigh = 0; + pAC->I2c.SenTable[i].SenThreErrLow = 0; + pAC->I2c.SenTable[i].SenThreWarnHigh = 0; + pAC->I2c.SenTable[i].SenThreWarnLow = 0; + pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN; + pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_NONE; + pAC->I2c.SenTable[i].SenValue = 0; + pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_NOT_PRESENT; + pAC->I2c.SenTable[i].SenErrCts = 0; + pAC->I2c.SenTable[i].SenBegErrTS = 0; + pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE; + pAC->I2c.SenTable[i].SenRead = NULL; + pAC->I2c.SenTable[i].SenDev = 0; + } + + /* Now we are "INIT data"ed */ + pAC->I2c.InitLevel = SK_INIT_DATA; + return(0); +} /* SkI2cInit0*/ + + +/* + * Do the init state 1 initialization + * + * initialize the following register of the LM80: + * Configuration register: + * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT + * + * Interrupt Mask Register 1: + * - all interrupts are Disabled (0xff) + * + * Interrupt Mask Register 2: + * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter. + * + * Fan Divisor/RST_OUT register: + * - Divisors set to 1 (bits 00), all others 0s. + * + * OS# Configuration/Temperature resolution Register: + * - all 0s + * + */ +static int SkI2cInit1( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + int i; + SK_U8 I2cSwCtrl; + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + if (pAC->I2c.InitLevel != SK_INIT_DATA) { + /* ReInit not needed in I2C module */ + return(0); + } + + /* Set the Direction of I2C-Data Pin to IN */ + SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA); + /* Check for 32-Bit Yukon with Low at I2C-Data Pin */ + SK_I2C_GET_SW(IoC, &I2cSwCtrl); + + if ((I2cSwCtrl & I2C_DATA) == 0) { + /* this is a 32-Bit board */ + pAC->GIni.GIYukon32Bit = SK_TRUE; + return(0); + } + + /* Check for 64 Bit Yukon without sensors */ + if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, LM80_CFG, 0) != 0) { + return(0); + } + + (void)SkI2cWrite(pAC, IoC, 0xff, LM80_ADDR, LM80_IMSK_1, 0); + + (void)SkI2cWrite(pAC, IoC, 0xff, LM80_ADDR, LM80_IMSK_2, 0); + + (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, LM80_FAN_CTRL, 0); + + (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, LM80_TEMP_CTRL, 0); + + (void)SkI2cWrite(pAC, IoC, LM80_CFG_START, LM80_ADDR, LM80_CFG, 0); + + /* + * MaxSens has to be updated here, because PhyType is not + * set when performing Init Level 0 + */ + pAC->I2c.MaxSens = 5; + + pPrt = &pAC->GIni.GP[0]; + + if (pAC->GIni.GIGenesis) { + if (pPrt->PhyType == SK_PHY_BCOM) { + if (pAC->GIni.GIMacsFound == 1) { + pAC->I2c.MaxSens += 1; + } + else { + pAC->I2c.MaxSens += 3; + } + } + } + else { + pAC->I2c.MaxSens += 3; + } + + for (i = 0; i < pAC->I2c.MaxSens; i++) { + switch (i) { + case 0: + pAC->I2c.SenTable[i].SenDesc = "Temperature"; + pAC->I2c.SenTable[i].SenType = SK_SEN_TEMP; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_TEMP_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_TEMP_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_TEMP_IN; + break; + case 1: + pAC->I2c.SenTable[i].SenDesc = "Voltage PCI"; + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT0_IN; + break; + case 2: + pAC->I2c.SenTable[i].SenDesc = "Voltage PCI-IO"; + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT1_IN; + pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_PCI_IO; + break; + case 3: + pAC->I2c.SenTable[i].SenDesc = "Voltage ASIC"; + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VDD_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VDD_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VDD_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT2_IN; + break; + case 4: + if (pAC->GIni.GIGenesis) { + if (pPrt->PhyType == SK_PHY_BCOM) { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY A PLL"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR; + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage PMA"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR; + } + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage VAUX"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN; + if (pAC->GIni.GIVauxAvail) { + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR; + } + else { + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_0V_WARN_ERR; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_0V_WARN_ERR; + } + } + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenReg = LM80_VT3_IN; + break; + case 5: + if (pAC->GIni.GIGenesis) { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR; + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage ASIC-Co 1V5"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR; + } + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenReg = LM80_VT4_IN; + break; + case 6: + if (pAC->GIni.GIGenesis) { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY B PLL"; + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 3V3"; + } + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT5_IN; + break; + case 7: + if (pAC->GIni.GIGenesis) { + pAC->I2c.SenTable[i].SenDesc = "Speed Fan"; + pAC->I2c.SenTable[i].SenType = SK_SEN_FAN; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_FAN_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_FAN_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_FAN_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN; + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5"; + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT6_IN; + } + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW, + SKERR_I2C_E001, SKERR_I2C_E001MSG); + break; + } + + pAC->I2c.SenTable[i].SenValue = 0; + pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK; + pAC->I2c.SenTable[i].SenErrCts = 0; + pAC->I2c.SenTable[i].SenBegErrTS = 0; + pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE; + pAC->I2c.SenTable[i].SenRead = SkLm80ReadSensor; + pAC->I2c.SenTable[i].SenDev = LM80_ADDR; + } + +#ifndef SK_DIAG + pAC->I2c.DummyReads = pAC->I2c.MaxSens; +#endif /* !SK_DIAG */ + + /* Clear I2C IRQ */ + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + + /* Now we are I/O initialized */ + pAC->I2c.InitLevel = SK_INIT_IO; + return(0); +} /* SkI2cInit1 */ + + +/* + * Init level 2: Start first sensor read. + */ +static int SkI2cInit2( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + int ReadComplete; + SK_SENSOR *pSen; + + if (pAC->I2c.InitLevel != SK_INIT_IO) { + /* ReInit not needed in I2C module */ + /* Init0 and Init2 not permitted */ + return(0); + } + + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen); + + if (ReadComplete) { + SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG); + } + + /* Now we are correctly initialized */ + pAC->I2c.InitLevel = SK_INIT_RUN; + + return(0); +} /* SkI2cInit2*/ + + +/* + * Initialize I2C devices + * + * Get the first voltage value and discard it. + * Go into temperature read mode. A default pointer is not set. + * + * The things to be done depend on the init level in the parameter list: + * Level 0: + * Initialize only the data structures. Do NOT access hardware. + * Level 1: + * Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts. + * Level 2: + * Everything is possible. Interrupts may be used from now on. + * + * return: + * 0 = success + * other = error. + */ +int SkI2cInit( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context needed in levels 1 and 2 */ +int Level) /* Init Level */ +{ + + switch (Level) { + case SK_INIT_DATA: + return(SkI2cInit0(pAC)); + case SK_INIT_IO: + return(SkI2cInit1(pAC, IoC)); + case SK_INIT_RUN: + return(SkI2cInit2(pAC, IoC)); + default: + break; + } + + return(0); +} /* SkI2cInit */ + + +#ifndef SK_DIAG + +/* + * Interrupt service function for the I2C Interface + * + * Clears the Interrupt source + * + * Reads the register and check it for sending a trap. + * + * Starts the timer if necessary. + */ +void SkI2cIsr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + SK_EVPARA Para; + + /* Clear I2C IRQ */ + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para); +} /* SkI2cIsr */ + + +/* + * Check this sensors Value against the threshold and send events. + */ +static void SkI2cCheckSensor( +SK_AC *pAC, /* Adapter Context */ +SK_SENSOR *pSen) +{ + SK_EVPARA ParaLocal; + SK_BOOL TooHigh; /* Is sensor too high? */ + SK_BOOL TooLow; /* Is sensor too low? */ + SK_U64 CurrTime; /* Current Time */ + SK_BOOL DoTrapSend; /* We need to send a trap */ + SK_BOOL DoErrLog; /* We need to log the error */ + SK_BOOL IsError; /* We need to log the error */ + + /* Check Dummy Reads first */ + if (pAC->I2c.DummyReads > 0) { + pAC->I2c.DummyReads--; + return; + } + + /* Get the current time */ + CurrTime = SkOsGetTime(pAC); + + /* Set para to the most useful setting: The current sensor. */ + ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens; + + /* Check the Value against the thresholds. First: Error Thresholds */ + TooHigh = (pSen->SenValue > pSen->SenThreErrHigh); + TooLow = (pSen->SenValue < pSen->SenThreErrLow); + + IsError = SK_FALSE; + if (TooHigh || TooLow) { + /* Error condition is satisfied */ + DoTrapSend = SK_TRUE; + DoErrLog = SK_TRUE; + + /* Now error condition is satisfied */ + IsError = SK_TRUE; + + if (pSen->SenErrFlag == SK_SEN_ERR_ERR) { + /* This state is the former one */ + + /* So check first whether we have to send a trap */ + if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD > + CurrTime) { + /* + * Do NOT send the Trap. The hold back time + * has to run out first. + */ + DoTrapSend = SK_FALSE; + } + + /* Check now whether we have to log an Error */ + if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD > + CurrTime) { + /* + * Do NOT log the error. The hold back time + * has to run out first. + */ + DoErrLog = SK_FALSE; + } + } + else { + /* We came from a different state -> Set Begin Time Stamp */ + pSen->SenBegErrTS = CurrTime; + pSen->SenErrFlag = SK_SEN_ERR_ERR; + } + + if (DoTrapSend) { + /* Set current Time */ + pSen->SenLastErrTrapTS = CurrTime; + pSen->SenErrCts++; + + /* Queue PNMI Event */ + SkEventQueue(pAC, SKGE_PNMI, (TooHigh ? + SK_PNMI_EVT_SEN_ERR_UPP : + SK_PNMI_EVT_SEN_ERR_LOW), + ParaLocal); + } + + if (DoErrLog) { + /* Set current Time */ + pSen->SenLastErrLogTS = CurrTime; + + if (pSen->SenType == SK_SEN_TEMP) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, + SKERR_I2C_E011MSG); + } else if (pSen->SenType == SK_SEN_VOLT) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, + SKERR_I2C_E012MSG); + } else + { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, + SKERR_I2C_E015MSG); + } + } + } + + /* Check the Value against the thresholds */ + /* 2nd: Warning thresholds */ + TooHigh = (pSen->SenValue > pSen->SenThreWarnHigh); + TooLow = (pSen->SenValue < pSen->SenThreWarnLow); + + if (!IsError && (TooHigh || TooLow)) { + /* Error condition is satisfied */ + DoTrapSend = SK_TRUE; + DoErrLog = SK_TRUE; + + if (pSen->SenErrFlag == SK_SEN_ERR_WARN) { + /* This state is the former one */ + + /* So check first whether we have to send a trap */ + if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > + CurrTime) { + /* + * Do NOT send the Trap. The hold back time + * has to run out first. + */ + DoTrapSend = SK_FALSE; + } + + /* Check now whether we have to log an Error */ + if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > + CurrTime) { + /* + * Do NOT log the error. The hold back time + * has to run out first. + */ + DoErrLog = SK_FALSE; + } + } + else { + /* We came from a different state -> Set Begin Time Stamp */ + pSen->SenBegWarnTS = CurrTime; + pSen->SenErrFlag = SK_SEN_ERR_WARN; + } + + if (DoTrapSend) { + /* Set current Time */ + pSen->SenLastWarnTrapTS = CurrTime; + pSen->SenWarnCts++; + + /* Queue PNMI Event */ + SkEventQueue(pAC, SKGE_PNMI, (TooHigh ? + SK_PNMI_EVT_SEN_WAR_UPP : + SK_PNMI_EVT_SEN_WAR_LOW), + ParaLocal); + } + + if (DoErrLog) { + /* Set current Time */ + pSen->SenLastWarnLogTS = CurrTime; + + if (pSen->SenType == SK_SEN_TEMP) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, + SKERR_I2C_E009MSG); + } else if (pSen->SenType == SK_SEN_VOLT) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, + SKERR_I2C_E010MSG); + } else + { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, + SKERR_I2C_E014MSG); + } + } + } + + /* Check for NO error at all */ + if (!IsError && !TooHigh && !TooLow) { + /* Set o.k. Status if no error and no warning condition */ + pSen->SenErrFlag = SK_SEN_ERR_OK; + } + + /* End of check against the thresholds */ + + /* Bug fix AF: 16.Aug.2001: Correct the init base + * of LM80 sensor. + */ + if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) { + + pSen->SenInit = SK_SEN_DYN_INIT_NONE; + + if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) { + /* 5V PCI-IO Voltage */ + pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR; + } + else { + /* 3.3V PCI-IO Voltage */ + pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN; + pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR; + } + } + +#if 0 + /* Dynamic thresholds also for VAUX of LM80 sensor */ + if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) { + + pSen->SenInit = SK_SEN_DYN_INIT_NONE; + + /* 3.3V VAUX Voltage */ + if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) { + pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR; + } + /* 0V VAUX Voltage */ + else { + pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR; + pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR; + } + } + + /* + * Check initialization state: + * The VIO Thresholds need adaption + */ + if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN && + pSen->SenValue > SK_SEN_WARNLOW2C && + pSen->SenValue < SK_SEN_WARNHIGH2) { + pSen->SenThreErrLow = SK_SEN_ERRLOW2C; + pSen->SenThreWarnLow = SK_SEN_WARNLOW2C; + pSen->SenInit = SK_TRUE; + } + + if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN && + pSen->SenValue > SK_SEN_WARNLOW2 && + pSen->SenValue < SK_SEN_WARNHIGH2C) { + pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C; + pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C; + pSen->SenInit = SK_TRUE; + } +#endif + + if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG); + } +} /* SkI2cCheckSensor*/ + + +/* + * The only Event to be served is the timeout event + * + */ +int SkI2cEvent( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Event, /* Module specific Event */ +SK_EVPARA Para) /* Event specific Parameter */ +{ + int ReadComplete; + SK_SENSOR *pSen; + SK_U32 Time; + SK_EVPARA ParaLocal; + int i; + + /* New case: no sensors */ + if (pAC->I2c.MaxSens == 0) { + return(0); + } + + switch (Event) { + case SK_I2CEV_IRQ: + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen); + + if (ReadComplete) { + /* Check sensor against defined thresholds */ + SkI2cCheckSensor (pAC, pSen); + + /* Increment Current sensor and set appropriate Timeout */ + pAC->I2c.CurrSens++; + if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) { + pAC->I2c.CurrSens = 0; + Time = SK_I2C_TIM_LONG; + } + else { + Time = SK_I2C_TIM_SHORT; + } + + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + else { + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_WATCH_STATEMACHINE; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + break; + case SK_I2CEV_TIM: + if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) { + + ParaLocal.Para64 = (SK_U64)0; + SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer); + + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen); + + if (ReadComplete) { + /* Check sensor against defined thresholds */ + SkI2cCheckSensor (pAC, pSen); + + /* Increment Current sensor and set appropriate Timeout */ + pAC->I2c.CurrSens++; + if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) { + pAC->I2c.CurrSens = 0; + Time = SK_I2C_TIM_LONG; + } + else { + Time = SK_I2C_TIM_SHORT; + } + + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + } + else { + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + pSen->SenErrFlag = SK_SEN_ERR_FAULTY; + SK_I2C_STOP(IoC); + + /* Increment Current sensor and set appropriate Timeout */ + pAC->I2c.CurrSens++; + if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) { + pAC->I2c.CurrSens = 0; + Time = SK_I2C_TIM_LONG; + } + else { + Time = SK_I2C_TIM_SHORT; + } + + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + break; + case SK_I2CEV_CLEAR: + for (i = 0; i < SK_MAX_SENSORS; i++) { + pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK; + pAC->I2c.SenTable[i].SenErrCts = 0; + pAC->I2c.SenTable[i].SenWarnCts = 0; + pAC->I2c.SenTable[i].SenBegErrTS = 0; + pAC->I2c.SenTable[i].SenBegWarnTS = 0; + pAC->I2c.SenTable[i].SenLastErrTrapTS = (SK_U64)0; + pAC->I2c.SenTable[i].SenLastErrLogTS = (SK_U64)0; + pAC->I2c.SenTable[i].SenLastWarnTrapTS = (SK_U64)0; + pAC->I2c.SenTable[i].SenLastWarnLogTS = (SK_U64)0; + } + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG); + } + + return(0); +} /* SkI2cEvent*/ + +#endif /* !SK_DIAG */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/sklm80.c b/drivers/sk98lin/sklm80.c new file mode 100644 index 0000000..687572b --- /dev/null +++ b/drivers/sk98lin/sklm80.c @@ -0,0 +1,292 @@ +/****************************************************************************** + * + * Name: sklm80.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.20 $ + * Date: $Date: 2002/08/13 09:16:27 $ + * Purpose: Funktions to access Voltage and Temperature Sensor (LM80) + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: sklm80.c,v $ + * Revision 1.20 2002/08/13 09:16:27 rschmidt + * Changed return value for SkLm80ReadSensor() back to 'int' + * Editorial changes + * + * Revision 1.19 2002/08/06 09:43:31 jschmalz + * Extensions and changes for Yukon + * + * Revision 1.18 2002/08/02 12:26:57 rschmidt + * Editorial changes + * + * Revision 1.17 1999/11/22 13:35:51 cgoos + * Changed license header to GPL. + * + * Revision 1.16 1999/05/27 14:05:47 malthoff + * Fans: Set SenVal to 0 if the fan value is 0 or 0xff. Both values + * are outside the limits (0: div zero error, 0xff: value not in + * range, assume 0). + * + * Revision 1.15 1999/05/27 13:38:51 malthoff + * Pervent from Division by zero errors. + * + * Revision 1.14 1999/05/20 09:20:01 cgoos + * Changes for 1000Base-T (Fan sensors). + * + * Revision 1.13 1998/10/22 09:48:14 gklug + * fix: SysKonnectFileId typo + * + * Revision 1.12 1998/10/09 06:12:06 malthoff + * Remove ID_sccs by SysKonnectFileId. + * + * Revision 1.11 1998/09/04 08:33:48 malthoff + * bug fix: SenState = SK_SEN_IDLE when + * leaving SK_SEN_VALEXT state + * + * Revision 1.10 1998/08/20 12:02:10 gklug + * fix: compiler warnings type mismatch + * + * Revision 1.9 1998/08/20 11:37:38 gklug + * chg: change Ioc to IoC + * + * Revision 1.8 1998/08/19 12:20:58 gklug + * fix: remove struct from C files (see CCC) + * + * Revision 1.7 1998/08/17 07:04:57 malthoff + * Take SkLm80RcvReg() function from ski2c.c. + * Add IoC parameter to BREAK_OR_WAIT() macro. + * + * Revision 1.6 1998/08/14 07:11:28 malthoff + * remove pAc with pAC. + * + * Revision 1.5 1998/08/14 06:46:55 gklug + * fix: temperature can get negative + * + * Revision 1.4 1998/08/13 08:27:04 gklug + * add: temperature reading now o.k. + * fix: pSen declaration, SK_ERR_LOG call, ADDR macro + * + * Revision 1.3 1998/08/13 07:28:21 gklug + * fix: pSen was wrong initialized + * add: correct conversion for voltage readings + * + * Revision 1.2 1998/08/11 07:52:14 gklug + * add: Lm80 read sensor function + * + * Revision 1.1 1998/07/17 09:57:12 gklug + * initial version + * + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + LM80 functions +*/ +static const char SysKonnectFileId[] = + "$Id: sklm80.c,v 1.20 2002/08/13 09:16:27 rschmidt Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/lm80.h" +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef SK_DIAG +#define BREAK_OR_WAIT(pAC,IoC,Event) SkI2cWait(pAC,IoC,Event) +#else /* nSK_DIAG */ +#define BREAK_OR_WAIT(pAC,IoC,Event) break +#endif /* nSK_DIAG */ + +#ifdef SK_DIAG +/* + * read the register 'Reg' from the device 'Dev' + * + * return read error -1 + * success the read value + */ +int SkLm80RcvReg( +SK_IOC IoC, /* Adapter Context */ +int Dev, /* I2C device address */ +int Reg) /* register to read */ +{ + int Val = 0; + int TempExt; + + /* Signal device number */ + if (SkI2cSndDev(IoC, Dev, I2C_WRITE)) { + return(-1); + } + + if (SkI2cSndByte(IoC, Reg)) { + return(-1); + } + + /* repeat start */ + if (SkI2cSndDev(IoC, Dev, I2C_READ)) { + return(-1); + } + + switch (Reg) { + case LM80_TEMP_IN: + Val = (int)SkI2cRcvByte(IoC, 1); + + /* First: correct the value: it might be negative */ + if ((Val & 0x80) != 0) { + /* Value is negative */ + Val = Val - 256; + } + Val = Val * SK_LM80_TEMP_LSB; + SkI2cStop(IoC); + + TempExt = (int)SkLm80RcvReg(IoC, LM80_ADDR, LM80_TEMP_CTRL); + + if (Val > 0) { + Val += ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB); + } + else { + Val -= ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB); + } + return(Val); + break; + case LM80_VT0_IN: + case LM80_VT1_IN: + case LM80_VT2_IN: + case LM80_VT3_IN: + Val = (int)SkI2cRcvByte(IoC, 1) * SK_LM80_VT_LSB; + break; + + default: + Val = (int)SkI2cRcvByte(IoC, 1); + break; + } + + SkI2cStop(IoC); + return(Val); +} +#endif /* SK_DIAG */ + +/* + * read a sensors value (LM80 specific) + * + * This function reads a sensors value from the I2C sensor chip LM80. + * The sensor is defined by its index into the sensors database in the struct + * pAC points to. + * + * Returns 1 if the read is completed + * 0 if the read must be continued (I2C Bus still allocated) + */ +int SkLm80ReadSensor( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context needed in level 1 and 2 */ +SK_SENSOR *pSen) /* Sensor to be read */ +{ + SK_I32 Value; + + switch (pSen->SenState) { + case SK_SEN_IDLE: + /* Send address to ADDR register */ + SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, pSen->SenReg, 0); + + pSen->SenState = SK_SEN_VALUE ; + BREAK_OR_WAIT(pAC, IoC, I2C_READ); + + case SK_SEN_VALUE: + /* Read value from data register */ + SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value)); + + Value &= 0xff; /* only least significant byte is valid */ + + /* Do NOT check the Value against the thresholds */ + /* Checking is done in the calling instance */ + + if (pSen->SenType == SK_SEN_VOLT) { + /* Voltage sensor */ + pSen->SenValue = Value * SK_LM80_VT_LSB; + pSen->SenState = SK_SEN_IDLE ; + return(1); + } + + if (pSen->SenType == SK_SEN_FAN) { + if (Value != 0 && Value != 0xff) { + /* Fan speed counter */ + pSen->SenValue = SK_LM80_FAN_FAKTOR/Value; + } + else { + /* Indicate Fan error */ + pSen->SenValue = 0; + } + pSen->SenState = SK_SEN_IDLE ; + return(1); + } + + /* First: correct the value: it might be negative */ + if ((Value & 0x80) != 0) { + /* Value is negative */ + Value = Value - 256; + } + + /* We have a temperature sensor and need to get the signed extension. + * For now we get the extension from the last reading, so in the normal + * case we won't see flickering temperatures. + */ + pSen->SenValue = (Value * SK_LM80_TEMP_LSB) + + (pSen->SenValue % SK_LM80_TEMP_LSB); + + /* Send address to ADDR register */ + SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, LM80_TEMP_CTRL, 0); + + pSen->SenState = SK_SEN_VALEXT ; + BREAK_OR_WAIT(pAC, IoC, I2C_READ); + + case SK_SEN_VALEXT: + /* Read value from data register */ + SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value)); + Value &= LM80_TEMP_LSB_9; /* only bit 7 is valid */ + + /* cut the LSB bit */ + pSen->SenValue = ((pSen->SenValue / SK_LM80_TEMP_LSB) * + SK_LM80_TEMP_LSB); + + if (pSen->SenValue < 0) { + /* Value negative: The bit value must be subtracted */ + pSen->SenValue -= ((Value >> 7) * SK_LM80_TEMPEXT_LSB); + } + else { + /* Value positive: The bit value must be added */ + pSen->SenValue += ((Value >> 7) * SK_LM80_TEMPEXT_LSB); + } + + pSen->SenState = SK_SEN_IDLE ; + return(1); + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E007, SKERR_I2C_E007MSG); + return(1); + } + + /* Not completed */ + return(0); +} + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skproc.c b/drivers/sk98lin/skproc.c new file mode 100644 index 0000000..4e34073 --- /dev/null +++ b/drivers/sk98lin/skproc.c @@ -0,0 +1,515 @@ +/****************************************************************************** + * + * Name: skproc.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.4 $ + * Date: $Date: 2003/02/25 14:16:37 $ + * Purpose: Funktions to display statictic data + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Created 22-Nov-2000 + * Author: Mirko Lindner (mlindner@syskonnect.de) + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ +/****************************************************************************** + * + * History: + * + * $Log: skproc.c,v $ + * Revision 1.4 2003/02/25 14:16:37 mlindner + * Fix: Copyright statement + * + * Revision 1.3 2002/10/02 12:59:51 mlindner + * Add: Support for Yukon + * Add: Speed check and setup + * Add: Merge source for kernel 2.2.x and 2.4.x + * Add: Read sensor names directly from VPD + * Fix: Volt values + * + * Revision 1.2.2.7 2002/01/14 12:45:15 mlindner + * Fix: Editorial changes + * + * Revision 1.2.2.6 2001/12/06 15:26:07 mlindner + * Fix: Return value of proc_read + * + * Revision 1.2.2.5 2001/12/06 09:57:39 mlindner + * New ProcFs entries + * + * Revision 1.2.2.4 2001/09/05 12:16:02 mlindner + * Add: New ProcFs entries + * Fix: Counter Errors (Jumbo == to long errors) + * Fix: Kernel error compilation + * Fix: too short counters + * + * Revision 1.2.2.3 2001/06/25 07:26:26 mlindner + * Add: More error messages + * + * Revision 1.2.2.2 2001/03/15 12:50:13 mlindner + * fix: ProcFS owner protection + * + * Revision 1.2.2.1 2001/03/12 16:43:48 mlindner + * chg: 2.4 requirements for procfs + * + * Revision 1.1 2001/01/22 14:15:31 mlindner + * added ProcFs functionality + * Dual Net functionality integrated + * Rlmt networks added + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" +#define ZEROPAD 1 /* pad with zero */ +#define SIGN 2 /* unsigned/signed long */ +#define PLUS 4 /* show plus */ +#define SPACE 8 /* space if plus */ +#define LEFT 16 /* left justified */ +#define SPECIALX 32 /* 0x */ +#define LARGE 64 + +extern SK_AC *pACList; +extern struct net_device *SkGeRootDev; + +extern char * SkNumber( + char * str, + long long num, + int base, + int size, + int precision, + int type); + + +/***************************************************************************** + * + * proc_read - print "summaries" entry + * + * Description: + * This function fills the proc entry with statistic data about + * the ethernet device. + * + * + * Returns: buffer with statistic data + * + */ +int proc_read(char *buffer, +char **buffer_location, +off_t offset, +int buffer_length, +int *eof, +void *data) +{ + int len = 0; + int t; + int i; + DEV_NET *pNet; + SK_AC *pAC; + char test_buf[100]; + char sens_msg[50]; + unsigned long Flags; + unsigned int Size; + struct SK_NET_DEVICE *next; + struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev; + + SK_PNMI_STRUCT_DATA *pPnmiStruct; + SK_PNMI_STAT *pPnmiStat; + struct proc_dir_entry *file = (struct proc_dir_entry*) data; + + while (SkgeProcDev) { + pNet = (DEV_NET*) SkgeProcDev->priv; + pAC = pNet->pAC; + next = pAC->Next; + pPnmiStruct = &pAC->PnmiStruct; + /* NetIndex in GetStruct is now required, zero is only dummy */ + + for (t=pAC->GIni.GIMacsFound; t > 0; t--) { + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 1) + t--; + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + Size = SK_PNMI_STRUCT_SIZE; + SkPnmiGetStruct(pAC, pAC->IoBase, + pPnmiStruct, &Size, t-1); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + if (strcmp(pAC->dev[t-1]->name, file->name) == 0) { + pPnmiStat = &pPnmiStruct->Stat[0]; + len = sprintf(buffer, + "\nDetailed statistic for device %s\n", + pAC->dev[t-1]->name); + len += sprintf(buffer + len, + "=======================================\n"); + + /* Board statistics */ + len += sprintf(buffer + len, + "\nBoard statistics\n\n"); + len += sprintf(buffer + len, + "Active Port %c\n", + 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt. + Net[t-1].PrefPort]->PortNumber); + len += sprintf(buffer + len, + "Preferred Port %c\n", + 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt. + Net[t-1].PrefPort]->PortNumber); + + len += sprintf(buffer + len, + "Bus speed (MHz) %d\n", + pPnmiStruct->BusSpeed); + + len += sprintf(buffer + len, + "Bus width (Bit) %d\n", + pPnmiStruct->BusWidth); + len += sprintf(buffer + len, + "Hardware revision v%d.%d\n", + (pAC->GIni.GIPciHwRev >> 4) & 0x0F, + pAC->GIni.GIPciHwRev & 0x0F); + + /* Print sensor informations */ + for (i=0; i < pAC->I2c.MaxSens; i ++) { + /* Check type */ + switch (pAC->I2c.SenTable[i].SenType) { + case 1: + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (C)"); + len += sprintf(buffer + len, + "%-25s %d.%02d\n", + sens_msg, + pAC->I2c.SenTable[i].SenValue / 10, + pAC->I2c.SenTable[i].SenValue % 10); + + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (F)"); + len += sprintf(buffer + len, + "%-25s %d.%02d\n", + sens_msg, + ((((pAC->I2c.SenTable[i].SenValue) + *10)*9)/5 + 3200)/100, + ((((pAC->I2c.SenTable[i].SenValue) + *10)*9)/5 + 3200) % 10); + break; + case 2: + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (V)"); + len += sprintf(buffer + len, + "%-25s %d.%03d\n", + sens_msg, + pAC->I2c.SenTable[i].SenValue / 1000, + pAC->I2c.SenTable[i].SenValue % 1000); + break; + case 3: + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (rpm)"); + len += sprintf(buffer + len, + "%-25s %d\n", + sens_msg, + pAC->I2c.SenTable[i].SenValue); + break; + default: + break; + } + } + + /*Receive statistics */ + len += sprintf(buffer + len, + "\nReceive statistics\n\n"); + + len += sprintf(buffer + len, + "Received bytes %s\n", + SkNumber(test_buf, pPnmiStat->StatRxOctetsOkCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Received packets %s\n", + SkNumber(test_buf, pPnmiStat->StatRxOkCts, + 10,0,-1,0)); +#if 0 + if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && + pAC->HWRevision < 12) { + pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts - + pPnmiStat->StatRxShortsCts; + pPnmiStat->StatRxShortsCts = 0; + } +#endif + if (pNet->Mtu > 1500) + pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts - + pPnmiStat->StatRxTooLongCts; + + len += sprintf(buffer + len, + "Receive errors %s\n", + SkNumber(test_buf, pPnmiStruct->InErrorsCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Receive drops %s\n", + SkNumber(test_buf, pPnmiStruct->RxNoBufCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Received multicast %s\n", + SkNumber(test_buf, pPnmiStat->StatRxMulticastOkCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Receive error types\n"); + len += sprintf(buffer + len, + " length %s\n", + SkNumber(test_buf, pPnmiStat->StatRxRuntCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " buffer overflow %s\n", + SkNumber(test_buf, pPnmiStat->StatRxFifoOverflowCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " bad crc %s\n", + SkNumber(test_buf, pPnmiStat->StatRxFcsCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " framing %s\n", + SkNumber(test_buf, pPnmiStat->StatRxFramingCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " missed frames %s\n", + SkNumber(test_buf, pPnmiStat->StatRxMissedCts, + 10, 0, -1, 0)); + + if (pNet->Mtu > 1500) + pPnmiStat->StatRxTooLongCts = 0; + + len += sprintf(buffer + len, + " too long %s\n", + SkNumber(test_buf, pPnmiStat->StatRxTooLongCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " carrier extension %s\n", + SkNumber(test_buf, pPnmiStat->StatRxCextCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " too short %s\n", + SkNumber(test_buf, pPnmiStat->StatRxShortsCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " symbol %s\n", + SkNumber(test_buf, pPnmiStat->StatRxSymbolCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " LLC MAC size %s\n", + SkNumber(test_buf, pPnmiStat->StatRxIRLengthCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " carrier event %s\n", + SkNumber(test_buf, pPnmiStat->StatRxCarrierCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " jabber %s\n", + SkNumber(test_buf, pPnmiStat->StatRxJabberCts, + 10, 0, -1, 0)); + + + /*Transmit statistics */ + len += sprintf(buffer + len, + "\nTransmit statistics\n\n"); + + len += sprintf(buffer + len, + "Transmited bytes %s\n", + SkNumber(test_buf, pPnmiStat->StatTxOctetsOkCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmited packets %s\n", + SkNumber(test_buf, pPnmiStat->StatTxOkCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmit errors %s\n", + SkNumber(test_buf, pPnmiStat->StatTxSingleCollisionCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmit dropped %s\n", + SkNumber(test_buf, pPnmiStruct->TxNoBufCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmit collisions %s\n", + SkNumber(test_buf, pPnmiStat->StatTxSingleCollisionCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmit errors types\n"); + len += sprintf(buffer + len, + " excessive collision %ld\n", + pAC->stats.tx_aborted_errors); + len += sprintf(buffer + len, + " carrier %s\n", + SkNumber(test_buf, pPnmiStat->StatTxCarrierCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " fifo underrun %s\n", + SkNumber(test_buf, pPnmiStat->StatTxFifoUnderrunCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " heartbeat %s\n", + SkNumber(test_buf, pPnmiStat->StatTxCarrierCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " window %ld\n", + pAC->stats.tx_window_errors); + + } + } + SkgeProcDev = next; + } + if (offset >= len) { + *eof = 1; + return 0; + } + + *buffer_location = buffer + offset; + if (buffer_length >= len - offset) { + *eof = 1; + } + return (min_t(int, buffer_length, len - offset)); +} + + +/***************************************************************************** + * + * SkDoDiv - convert 64bit number + * + * Description: + * This function "converts" a long long number. + * + * Returns: + * remainder of division + */ +static long SkDoDiv (long long Dividend, int Divisor, long long *pErg) +{ + long Rest; + long long Ergebnis; + long Akku; + + + Akku = Dividend >> 32; + + Ergebnis = ((long long) (Akku / Divisor)) << 32; + Rest = Akku % Divisor ; + + Akku = Rest << 16; + Akku |= ((Dividend & 0xFFFF0000) >> 16); + + + Ergebnis += ((long long) (Akku / Divisor)) << 16; + Rest = Akku % Divisor ; + + Akku = Rest << 16; + Akku |= (Dividend & 0xFFFF); + + Ergebnis += (Akku / Divisor); + Rest = Akku % Divisor ; + + *pErg = Ergebnis; + return (Rest); +} + + +#if 0 +#define do_div(n,base) ({ \ +long long __res; \ +__res = ((unsigned long long) n) % (unsigned) base; \ +n = ((unsigned long long) n) / (unsigned) base; \ +__res; }) + +#endif + + +/***************************************************************************** + * + * SkNumber - Print results + * + * Description: + * This function converts a long long number into a string. + * + * Returns: + * number as string + */ +char * SkNumber(char * str, long long num, int base, int size, int precision + ,int type) +{ + char c,sign,tmp[66], *strorg = str; + const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; + int i; + + if (type & LARGE) + digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + if (type & LEFT) + type &= ~ZEROPAD; + if (base < 2 || base > 36) + return 0; + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + if (type & SIGN) { + if (num < 0) { + sign = '-'; + num = -num; + size--; + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (type & SPECIALX) { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } + i = 0; + if (num == 0) + tmp[i++]='0'; + else while (num != 0) + tmp[i++] = digits[SkDoDiv(num,base, &num)]; + + if (i > precision) + precision = i; + size -= precision; + if (!(type&(ZEROPAD+LEFT))) + while(size-->0) + *str++ = ' '; + if (sign) + *str++ = sign; + if (type & SPECIALX) { + if (base==8) + *str++ = '0'; + else if (base==16) { + *str++ = '0'; + *str++ = digits[33]; + } + } + if (!(type & LEFT)) + while (size-- > 0) + *str++ = c; + while (i < precision--) + *str++ = '0'; + while (i-- > 0) + *str++ = tmp[i]; + while (size-- > 0) + *str++ = ' '; + + str[0] = '\0'; + + return strorg; +} + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skqueue.c b/drivers/sk98lin/skqueue.c new file mode 100644 index 0000000..c49baed --- /dev/null +++ b/drivers/sk98lin/skqueue.c @@ -0,0 +1,242 @@ +/****************************************************************************** + * + * Name: skqueue.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.18 $ + * Date: $Date: 2002/05/07 14:11:11 $ + * Purpose: Management of an event queue. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skqueue.c,v $ + * Revision 1.18 2002/05/07 14:11:11 rwahl + * Fixed Watcom Precompiler error. + * + * Revision 1.17 2002/03/25 10:06:41 mkunz + * SkIgnoreEvent deleted + * + * Revision 1.16 2002/03/15 10:51:59 mkunz + * Added event classes for link aggregation + * + * Revision 1.15 1999/11/22 13:36:29 cgoos + * Changed license header to GPL. + * + * Revision 1.14 1998/10/15 15:11:35 gklug + * fix: ID_sccs to SysKonnectFileId + * + * Revision 1.13 1998/09/08 08:47:52 gklug + * add: init level handling + * + * Revision 1.12 1998/09/08 07:43:20 gklug + * fix: Sirq Event function name + * + * Revision 1.11 1998/09/08 05:54:34 gklug + * chg: define SK_CSUM is replaced by SK_USE_CSUM + * + * Revision 1.10 1998/09/03 14:14:49 gklug + * add: CSUM and HWAC Eventclass and function. + * + * Revision 1.9 1998/08/19 09:50:50 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.8 1998/08/17 13:43:11 gklug + * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR + * + * Revision 1.7 1998/08/14 07:09:11 gklug + * fix: chg pAc -> pAC + * + * Revision 1.6 1998/08/11 12:13:14 gklug + * add: return code feature of Event service routines + * add: correct Error log calls + * + * Revision 1.5 1998/08/07 12:53:45 gklug + * fix: first compiled version + * + * Revision 1.4 1998/08/07 09:20:48 gklug + * adapt functions to C coding conventions. + * + * Revision 1.3 1998/08/05 11:29:32 gklug + * rmv: Timer event entry. Timer will queue event directly + * + * Revision 1.2 1998/07/31 11:22:40 gklug + * Initial version + * + * Revision 1.1 1998/07/30 15:14:01 gklug + * Initial version. Adapted from SMT + * + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + Event queue and dispatcher +*/ +static const char SysKonnectFileId[] = + "$Header: /usr56/projects/ge/schedule/skqueue.c,v 1.18 2002/05/07 14:11:11 rwahl Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/skqueue.h" /* Queue Definitions */ +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef __C2MAN__ +/* + Event queue management. + + General Description: + + */ +intro() +{} +#endif + +#define PRINTF(a,b,c) + +/* + * init event queue management + * + * Must be called during init level 0. + */ +void SkEventInit( +SK_AC *pAC, /* Adapter context */ +SK_IOC Ioc, /* IO context */ +int Level) /* Init level */ +{ + switch (Level) { + case SK_INIT_DATA: + pAC->Event.EvPut = pAC->Event.EvGet = pAC->Event.EvQueue ; + break; + default: + break; + } +} + +/* + * add event to queue + */ +void SkEventQueue( +SK_AC *pAC, /* Adapters context */ +SK_U32 Class, /* Event Class */ +SK_U32 Event, /* Event to be queued */ +SK_EVPARA Para) /* Event parameter */ +{ + pAC->Event.EvPut->Class = Class ; + pAC->Event.EvPut->Event = Event ; + pAC->Event.EvPut->Para = Para ; + if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT]) + pAC->Event.EvPut = pAC->Event.EvQueue ; + + if (pAC->Event.EvPut == pAC->Event.EvGet) { + SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG) ; + } +} + +/* + * event dispatcher + * while event queue is not empty + * get event from queue + * send command to state machine + * end + * return error reported by individual Event function + * 0 if no error occured. + */ +int SkEventDispatcher( +SK_AC *pAC, /* Adapters Context */ +SK_IOC Ioc) /* Io context */ +{ + SK_EVENTELEM *pEv ; /* pointer into queue */ + SK_U32 Class ; + int Rtv ; + + pEv = pAC->Event.EvGet ; + PRINTF("dispatch get %x put %x\n",pEv,pAC->Event.ev_put) ; + while (pEv != pAC->Event.EvPut) { + PRINTF("dispatch Class %d Event %d\n",pEv->Class,pEv->Event) ; + switch(Class = pEv->Class) { +#ifndef SK_USE_LAC_EV + case SKGE_RLMT : /* RLMT Event */ + Rtv = SkRlmtEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_I2C : /* I2C Event */ + Rtv = SkI2cEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_PNMI : + Rtv = SkPnmiEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#endif /* SK_USE_LAC_EV */ + case SKGE_DRV : /* Driver Event */ + Rtv = SkDrvEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#ifndef SK_USE_SW_TIMER + case SKGE_HWAC : + Rtv = SkGeSirqEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#else /* !SK_USE_SW_TIMER */ + case SKGE_SWT : + Rtv = SkSwtEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#endif /* !SK_USE_SW_TIMER */ +#ifdef SK_USE_LAC_EV + case SKGE_LACP : + Rtv = SkLacpEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_RSF : + Rtv = SkRsfEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_MARKER : + Rtv = SkMarkerEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_FD : + Rtv = SkFdEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#endif /* SK_USE_LAC_EV */ +#ifdef SK_USE_CSUM + case SKGE_CSUM : + Rtv = SkCsEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#endif /* SK_USE_CSUM */ + default : + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E002, + SKERR_Q_E002MSG) ; + Rtv = 0; + } + + if (Rtv != 0) { + return(Rtv) ; + } + + if (++pEv == &pAC->Event.EvQueue[SK_MAX_EVENT]) + pEv = pAC->Event.EvQueue ; + + /* Renew get: it is used in queue_events to detect overruns */ + pAC->Event.EvGet = pEv; + } + + return(0) ; +} + +#endif /* CONFIG_SK98 */ + +/* End of file */ diff --git a/drivers/sk98lin/skrlmt.c b/drivers/sk98lin/skrlmt.c new file mode 100644 index 0000000..f8a3b41 --- /dev/null +++ b/drivers/sk98lin/skrlmt.c @@ -0,0 +1,3508 @@ +/****************************************************************************** + * + * Name: skrlmt.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.68 $ + * Date: $Date: 2003/01/31 15:26:56 $ + * Purpose: Manage links on SK-NET Adapters, esp. redundant ones. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skrlmt.c,v $ + * Revision 1.68 2003/01/31 15:26:56 rschmidt + * Added init for local variables in RlmtInit(). + * + * Revision 1.67 2003/01/31 14:12:41 mkunz + * single port adapter runs now with two identical MAC addresses + * + * Revision 1.66 2002/09/23 15:14:19 rwahl + * - Reset broadcast timestamp on link down. + * - Editorial corrections. + * + * Revision 1.65 2002/07/22 14:29:48 rwahl + * - Removed BRK statement from debug check. + * + * Revision 1.64 2001/11/28 19:36:14 rwahl + * - RLMT Packets sent to an invalid MAC address in CLP/CLPSS mode + * (#10650). + * - Reworked fix for port switching in CLS mode (#10639) + * (no dependency to RLMT module). + * - Enabled dbg output for entry/exit of event functions. + * - Editorial changes. + * + * Revision 1.63 2001/10/26 07:53:18 afischer + * Port switching bug in `check local link` mode + * + * Revision 1.62 2001/07/03 12:16:30 mkunz + * New Flag ChgBcPrio (Change priority of last broadcast received) + * + * Revision 1.61 2001/03/14 12:52:08 rassmann + * Fixed reporting of active port up/down to PNMI. + * + * Revision 1.60 2001/02/21 16:02:25 gklug + * fix: when RLMT starts set Active Port for PNMI + * + * Revision 1.59 2001/02/16 14:38:19 rassmann + * Initializing some pointers earlier in the init phase. + * Rx Mbufs are freed if the net which they belong to is stopped. + * + * Revision 1.58 2001/02/14 14:06:31 rassmann + * Editorial changes. + * + * Revision 1.57 2001/02/05 14:25:26 rassmann + * Prepared RLMT for transparent operation. + * + * Revision 1.56 2001/01/30 10:29:09 rassmann + * Not checking switching befor RlmtStart. + * Editorial changes. + * + * Revision 1.55 2001/01/22 13:41:38 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.54 2000/11/30 13:25:07 rassmann + * Setting SK_TICK_INCR to 1 by default. + * + * Revision 1.53 2000/11/30 10:48:07 cgoos + * Changed definition of SK_RLMT_BC_DELTA. + * + * Revision 1.52 2000/11/27 12:50:03 rassmann + * Checking ports after receiving broadcasts. + * + * Revision 1.51 2000/11/17 08:58:00 rassmann + * Moved CheckSwitch from SK_RLMT_PACKET_RECEIVED to SK_RLMT_TIM event. + * + * Revision 1.50 2000/11/09 12:24:34 rassmann + * Indicating that segmentation check is not running anymore after + * SkRlmtCheckSeg(). + * Restarting segmentation timer after segmentation log. + * Editorial changes. + * + * Revision 1.49 1999/11/22 13:38:02 cgoos + * Changed license header to GPL. + * Added initialization to some variables to avoid compiler warnings. + * + * Revision 1.48 1999/10/04 14:01:17 rassmann + * Corrected reaction to reception of BPDU frames (#10441). + * + * Revision 1.47 1999/07/20 12:53:36 rassmann + * Fixed documentation errors for lookahead macros. + * + * Revision 1.46 1999/05/28 13:29:16 rassmann + * Replaced C++-style comment. + * + * Revision 1.45 1999/05/28 13:28:08 rassmann + * Corrected syntax error (xxx). + * + * Revision 1.44 1999/05/28 11:15:54 rassmann + * Changed behaviour to reflect Design Spec v1.2. + * Controlling Link LED(s). + * Introduced RLMT Packet Version field in RLMT Packet. + * Newstyle lookahead macros (checking meta-information before looking at + * the packet). + * + * Revision 1.43 1999/01/28 13:12:43 rassmann + * Corrected Lookahead (bug introduced in previous Rev.). + * + * Revision 1.42 1999/01/28 12:50:41 rassmann + * Not using broadcast time stamps in CheckLinkState mode. + * + * Revision 1.41 1999/01/27 14:13:02 rassmann + * Monitoring broadcast traffic. + * Switching more reliably and not too early if switch is + * configured for spanning tree. + * + * Revision 1.40 1999/01/22 13:17:30 rassmann + * Informing PNMI of NET_UP. + * Clearing RLMT multicast addresses before setting them for the first time. + * Reporting segmentation earlier, setting a "quiet time" + * after a report. + * + * Revision 1.39 1998/12/10 15:29:53 rassmann + * Corrected SuspectStatus in SkRlmtBuildCheckChain(). + * Corrected CHECK_SEG mode. + * + * Revision 1.38 1998/12/08 13:11:23 rassmann + * Stopping SegTimer at RlmtStop. + * + * Revision 1.37 1998/12/07 16:51:42 rassmann + * Corrected comments. + * + * Revision 1.36 1998/12/04 10:58:56 rassmann + * Setting next pointer to NULL when receiving. + * + * Revision 1.35 1998/12/03 16:12:42 rassmann + * Ignoring/correcting illegal PrefPort values. + * + * Revision 1.34 1998/12/01 11:45:35 rassmann + * Code cleanup. + * + * Revision 1.33 1998/12/01 10:29:32 rassmann + * Starting standby ports before getting the net up. + * Checking if a port is started when the link comes up. + * + * Revision 1.32 1998/11/30 16:19:50 rassmann + * New default for PortNoRx. + * + * Revision 1.31 1998/11/27 19:17:13 rassmann + * Corrected handling of LINK_DOWN coming shortly after LINK_UP. + * + * Revision 1.30 1998/11/24 12:37:31 rassmann + * Implemented segmentation check. + * + * Revision 1.29 1998/11/18 13:04:32 rassmann + * Secured PortUpTimer event. + * Waiting longer before starting standby port(s). + * + * Revision 1.28 1998/11/17 13:43:04 rassmann + * Handling (logical) tx failure. + * Sending packet on logical address after PORT_SWITCH. + * + * Revision 1.27 1998/11/13 17:09:50 rassmann + * Secured some events against being called in wrong state. + * + * Revision 1.26 1998/11/13 16:56:54 rassmann + * Added macro version of SkRlmtLookaheadPacket. + * + * Revision 1.25 1998/11/06 18:06:04 rassmann + * Corrected timing when RLMT checks fail. + * Clearing tx counter earlier in periodical checks. + * + * Revision 1.24 1998/11/05 10:37:27 rassmann + * Checking destination address in Lookahead. + * + * Revision 1.23 1998/11/03 13:53:49 rassmann + * RLMT should switch now (at least in mode 3). + * + * Revision 1.22 1998/10/29 14:34:49 rassmann + * Clearing SK_RLMT struct at startup. + * Initializing PortsUp during SK_RLMT_START. + * + * Revision 1.21 1998/10/28 11:30:17 rassmann + * Default mode is now SK_RLMT_CHECK_LOC_LINK. + * + * Revision 1.20 1998/10/26 16:02:03 rassmann + * Ignoring LINK_DOWN for links that are down. + * + * Revision 1.19 1998/10/22 15:54:01 rassmann + * Corrected EtherLen. + * Starting Link Check when second port comes up. + * + * Revision 1.18 1998/10/22 11:39:50 rassmann + * Corrected signed/unsigned mismatches. + * Corrected receive list handling and address recognition. + * + * Revision 1.17 1998/10/19 17:01:20 rassmann + * More detailed checking of received packets. + * + * Revision 1.16 1998/10/15 15:16:34 rassmann + * Finished Spanning Tree checking. + * Checked with lint. + * + * Revision 1.15 1998/09/24 19:16:07 rassmann + * Code cleanup. + * Introduced Timer for PORT_DOWN due to no RX. + * + * Revision 1.14 1998/09/18 20:27:14 rassmann + * Added address override. + * + * Revision 1.13 1998/09/16 11:31:48 rassmann + * Including skdrv1st.h again. :( + * + * Revision 1.12 1998/09/16 11:09:50 rassmann + * Syntax corrections. + * + * Revision 1.11 1998/09/15 12:32:03 rassmann + * Syntax correction. + * + * Revision 1.10 1998/09/15 11:28:49 rassmann + * Syntax corrections. + * + * Revision 1.9 1998/09/14 17:07:37 rassmann + * Added code for port checking via LAN. + * Changed Mbuf definition. + * + * Revision 1.8 1998/09/07 11:14:14 rassmann + * Syntax corrections. + * + * Revision 1.7 1998/09/07 09:06:07 rassmann + * Syntax corrections. + * + * Revision 1.6 1998/09/04 19:41:33 rassmann + * Syntax corrections. + * Started entering code for checking local links. + * + * Revision 1.5 1998/09/04 12:14:27 rassmann + * Interface cleanup. + * + * Revision 1.4 1998/09/02 16:55:28 rassmann + * Updated to reflect new DRV/HWAC/RLMT interface. + * + * Revision 1.3 1998/08/27 14:29:03 rassmann + * Code cleanup. + * + * Revision 1.2 1998/08/27 14:26:24 rassmann + * Updated interface. + * + * Revision 1.1 1998/08/21 08:26:49 rassmann + * First public version. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This module contains code for Link ManagemenT (LMT) of SK-NET Adapters. + * It is mainly intended for adapters with more than one link. + * For such adapters, this module realizes Redundant Link ManagemenT (RLMT). + * + * Include File Hierarchy: + * + * "skdrv1st.h" + * "skdrv2nd.h" + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#ifndef lint +static const char SysKonnectFileId[] = + "@(#) $Id: skrlmt.c,v 1.68 2003/01/31 15:26:56 rschmidt Exp $ (C) SysKonnect."; +#endif /* !defined(lint) */ + +#define __SKRLMT_C + +#ifdef __cplusplus +#error C++ is not yet supported. +extern "C" { +#endif /* cplusplus */ + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/* defines ********************************************************************/ + +#ifndef SK_HWAC_LINK_LED +#define SK_HWAC_LINK_LED(a,b,c,d) +#endif /* !defined(SK_HWAC_LINK_LED) */ + +#ifndef DEBUG +#define RLMT_STATIC static +#else /* DEBUG */ +#define RLMT_STATIC + +#ifndef SK_LITTLE_ENDIAN +/* First 32 bits */ +#define OFFS_LO32 1 + +/* Second 32 bits */ +#define OFFS_HI32 0 +#else /* SK_LITTLE_ENDIAN */ +/* First 32 bits */ +#define OFFS_LO32 0 + +/* Second 32 bits */ +#define OFFS_HI32 1 +#endif /* SK_LITTLE_ENDIAN */ + +#endif /* DEBUG */ + +/* ----- Private timeout values ----- */ + +#define SK_RLMT_MIN_TO_VAL 125000 /* 1/8 sec. */ +#define SK_RLMT_DEF_TO_VAL 1000000 /* 1 sec. */ +#define SK_RLMT_PORTDOWN_TIM_VAL 900000 /* another 0.9 sec. */ +#define SK_RLMT_PORTSTART_TIM_VAL 100000 /* 0.1 sec. */ +#define SK_RLMT_PORTUP_TIM_VAL 2500000 /* 2.5 sec. */ +#define SK_RLMT_SEG_TO_VAL 900000000 /* 15 min. */ + +/* Assume tick counter increment is 1 - may be set OS-dependent. */ +#ifndef SK_TICK_INCR +#define SK_TICK_INCR SK_CONSTU64(1) +#endif /* !defined(SK_TICK_INCR) */ + +/* + * Amount that a time stamp must be later to be recognized as "substantially + * later". This is about 1/128 sec, but above 1 tick counter increment. + */ +#define SK_RLMT_BC_DELTA (1 + ((SK_TICKS_PER_SEC >> 7) > SK_TICK_INCR ? \ + (SK_TICKS_PER_SEC >> 7) : SK_TICK_INCR)) + +/* ----- Private RLMT defaults ----- */ + +#define SK_RLMT_DEF_PREF_PORT 0 /* "Lower" port. */ +#define SK_RLMT_DEF_MODE SK_RLMT_CHECK_LINK /* Default RLMT Mode. */ + +/* ----- Private RLMT checking states ----- */ + +#define SK_RLMT_RCS_SEG 1 /* RLMT Check State: check seg. */ +#define SK_RLMT_RCS_START_SEG 2 /* RLMT Check State: start check seg. */ +#define SK_RLMT_RCS_SEND_SEG 4 /* RLMT Check State: send BPDU packet */ +#define SK_RLMT_RCS_REPORT_SEG 8 /* RLMT Check State: report seg. */ + +/* ----- Private PORT checking states ----- */ + +#define SK_RLMT_PCS_TX 1 /* Port Check State: check tx. */ +#define SK_RLMT_PCS_RX 2 /* Port Check State: check rx. */ + +/* ----- Private PORT events ----- */ + +/* Note: Update simulation when changing these. */ +#define SK_RLMT_PORTSTART_TIM 1100 /* Port start timeout. */ +#define SK_RLMT_PORTUP_TIM 1101 /* Port can now go up. */ +#define SK_RLMT_PORTDOWN_RX_TIM 1102 /* Port did not receive once ... */ +#define SK_RLMT_PORTDOWN 1103 /* Port went down. */ +#define SK_RLMT_PORTDOWN_TX_TIM 1104 /* Partner did not receive ... */ + +/* ----- Private RLMT events ----- */ + +/* Note: Update simulation when changing these. */ +#define SK_RLMT_TIM 2100 /* RLMT timeout. */ +#define SK_RLMT_SEG_TIM 2101 /* RLMT segmentation check timeout. */ + +#define TO_SHORTEN(tim) ((tim) / 2) + +/* Error numbers and messages. */ +#define SKERR_RLMT_E001 (SK_ERRBASE_RLMT + 0) +#define SKERR_RLMT_E001_MSG "No Packet." +#define SKERR_RLMT_E002 (SKERR_RLMT_E001 + 1) +#define SKERR_RLMT_E002_MSG "Short Packet." +#define SKERR_RLMT_E003 (SKERR_RLMT_E002 + 1) +#define SKERR_RLMT_E003_MSG "Unknown RLMT event." +#define SKERR_RLMT_E004 (SKERR_RLMT_E003 + 1) +#define SKERR_RLMT_E004_MSG "PortsUp incorrect." +#define SKERR_RLMT_E005 (SKERR_RLMT_E004 + 1) +#define SKERR_RLMT_E005_MSG \ + "Net seems to be segmented (different root bridges are reported on the ports)." +#define SKERR_RLMT_E006 (SKERR_RLMT_E005 + 1) +#define SKERR_RLMT_E006_MSG "Duplicate MAC Address detected." +#define SKERR_RLMT_E007 (SKERR_RLMT_E006 + 1) +#define SKERR_RLMT_E007_MSG "LinksUp incorrect." +#define SKERR_RLMT_E008 (SKERR_RLMT_E007 + 1) +#define SKERR_RLMT_E008_MSG "Port not started but link came up." +#define SKERR_RLMT_E009 (SKERR_RLMT_E008 + 1) +#define SKERR_RLMT_E009_MSG "Corrected illegal setting of Preferred Port." +#define SKERR_RLMT_E010 (SKERR_RLMT_E009 + 1) +#define SKERR_RLMT_E010_MSG "Ignored illegal Preferred Port." + +/* LLC field values. */ +#define LLC_COMMAND_RESPONSE_BIT 1 +#define LLC_TEST_COMMAND 0xE3 +#define LLC_UI 0x03 + +/* RLMT Packet fields. */ +#define SK_RLMT_DSAP 0 +#define SK_RLMT_SSAP 0 +#define SK_RLMT_CTRL (LLC_TEST_COMMAND) +#define SK_RLMT_INDICATOR0 0x53 /* S */ +#define SK_RLMT_INDICATOR1 0x4B /* K */ +#define SK_RLMT_INDICATOR2 0x2D /* - */ +#define SK_RLMT_INDICATOR3 0x52 /* R */ +#define SK_RLMT_INDICATOR4 0x4C /* L */ +#define SK_RLMT_INDICATOR5 0x4D /* M */ +#define SK_RLMT_INDICATOR6 0x54 /* T */ +#define SK_RLMT_PACKET_VERSION 0 + +/* RLMT SPT Flag values. */ +#define SK_RLMT_SPT_FLAG_CHANGE 0x01 +#define SK_RLMT_SPT_FLAG_CHANGE_ACK 0x80 + +/* RLMT SPT Packet fields. */ +#define SK_RLMT_SPT_DSAP 0x42 +#define SK_RLMT_SPT_SSAP 0x42 +#define SK_RLMT_SPT_CTRL (LLC_UI) +#define SK_RLMT_SPT_PROTOCOL_ID0 0x00 +#define SK_RLMT_SPT_PROTOCOL_ID1 0x00 +#define SK_RLMT_SPT_PROTOCOL_VERSION_ID 0x00 +#define SK_RLMT_SPT_BPDU_TYPE 0x00 +#define SK_RLMT_SPT_FLAGS 0x00 /* ?? */ +#define SK_RLMT_SPT_ROOT_ID0 0xFF /* Lowest possible priority. */ +#define SK_RLMT_SPT_ROOT_ID1 0xFF /* Lowest possible priority. */ + +/* Remaining 6 bytes will be the current port address. */ +#define SK_RLMT_SPT_ROOT_PATH_COST0 0x00 +#define SK_RLMT_SPT_ROOT_PATH_COST1 0x00 +#define SK_RLMT_SPT_ROOT_PATH_COST2 0x00 +#define SK_RLMT_SPT_ROOT_PATH_COST3 0x00 +#define SK_RLMT_SPT_BRIDGE_ID0 0xFF /* Lowest possible priority. */ +#define SK_RLMT_SPT_BRIDGE_ID1 0xFF /* Lowest possible priority. */ + +/* Remaining 6 bytes will be the current port address. */ +#define SK_RLMT_SPT_PORT_ID0 0xFF /* Lowest possible priority. */ +#define SK_RLMT_SPT_PORT_ID1 0xFF /* Lowest possible priority. */ +#define SK_RLMT_SPT_MSG_AGE0 0x00 +#define SK_RLMT_SPT_MSG_AGE1 0x00 +#define SK_RLMT_SPT_MAX_AGE0 0x00 +#define SK_RLMT_SPT_MAX_AGE1 0xFF +#define SK_RLMT_SPT_HELLO_TIME0 0x00 +#define SK_RLMT_SPT_HELLO_TIME1 0xFF +#define SK_RLMT_SPT_FWD_DELAY0 0x00 +#define SK_RLMT_SPT_FWD_DELAY1 0x40 + +/* Size defines. */ +#define SK_RLMT_MIN_PACKET_SIZE 34 +#define SK_RLMT_MAX_PACKET_SIZE (SK_RLMT_MAX_TX_BUF_SIZE) +#define SK_PACKET_DATA_LEN (SK_RLMT_MAX_PACKET_SIZE - \ + SK_RLMT_MIN_PACKET_SIZE) + +/* ----- RLMT packet types ----- */ +#define SK_PACKET_ANNOUNCE 1 /* Port announcement. */ +#define SK_PACKET_ALIVE 2 /* Alive packet to port. */ +#define SK_PACKET_ADDR_CHANGED 3 /* Port address changed. */ +#define SK_PACKET_CHECK_TX 4 /* Check your tx line. */ + +#ifdef SK_LITTLE_ENDIAN +#define SK_U16_TO_NETWORK_ORDER(Val,Addr) { \ + SK_U8 *_Addr = (SK_U8*)(Addr); \ + SK_U16 _Val = (SK_U16)(Val); \ + *_Addr++ = (SK_U8)(_Val >> 8); \ + *_Addr = (SK_U8)(_Val & 0xFF); \ +} +#endif /* SK_LITTLE_ENDIAN */ + +#ifdef SK_BIG_ENDIAN +#define SK_U16_TO_NETWORK_ORDER(Val,Addr) (*(SK_U16*)(Addr) = (SK_U16)(Val)) +#endif /* SK_BIG_ENDIAN */ + +#define AUTONEG_FAILED SK_FALSE +#define AUTONEG_SUCCESS SK_TRUE + + +/* typedefs *******************************************************************/ + +/* RLMT packet. Length: SK_RLMT_MAX_PACKET_SIZE (60) bytes. */ +typedef struct s_RlmtPacket { + SK_U8 DstAddr[SK_MAC_ADDR_LEN]; + SK_U8 SrcAddr[SK_MAC_ADDR_LEN]; + SK_U8 TypeLen[2]; + SK_U8 DSap; + SK_U8 SSap; + SK_U8 Ctrl; + SK_U8 Indicator[7]; + SK_U8 RlmtPacketType[2]; + SK_U8 Align1[2]; + SK_U8 Random[4]; /* Random value of requesting(!) station. */ + SK_U8 RlmtPacketVersion[2]; /* RLMT Packet version. */ + SK_U8 Data[SK_PACKET_DATA_LEN]; +} SK_RLMT_PACKET; + +typedef struct s_SpTreeRlmtPacket { + SK_U8 DstAddr[SK_MAC_ADDR_LEN]; + SK_U8 SrcAddr[SK_MAC_ADDR_LEN]; + SK_U8 TypeLen[2]; + SK_U8 DSap; + SK_U8 SSap; + SK_U8 Ctrl; + SK_U8 ProtocolId[2]; + SK_U8 ProtocolVersionId; + SK_U8 BpduType; + SK_U8 Flags; + SK_U8 RootId[8]; + SK_U8 RootPathCost[4]; + SK_U8 BridgeId[8]; + SK_U8 PortId[2]; + SK_U8 MessageAge[2]; + SK_U8 MaxAge[2]; + SK_U8 HelloTime[2]; + SK_U8 ForwardDelay[2]; +} SK_SPTREE_PACKET; + +/* global variables ***********************************************************/ + +SK_MAC_ADDR SkRlmtMcAddr = {{0x01, 0x00, 0x5A, 0x52, 0x4C, 0x4D}}; +SK_MAC_ADDR BridgeMcAddr = {{0x01, 0x80, 0xC2, 0x00, 0x00, 0x00}}; +SK_MAC_ADDR BcAddr = {{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}}; + +/* local variables ************************************************************/ + +/* None. */ + +/* functions ******************************************************************/ + +RLMT_STATIC void SkRlmtCheckSwitch( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 NetIdx); +RLMT_STATIC void SkRlmtCheckSeg( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 NetIdx); +RLMT_STATIC void SkRlmtEvtSetNets( + SK_AC *pAC, + SK_IOC IoC, + SK_EVPARA Para); + +/****************************************************************************** + * + * SkRlmtInit - initialize data, set state to init + * + * Description: + * + * SK_INIT_DATA + * ============ + * + * This routine initializes all RLMT-related variables to a known state. + * The initial state is SK_RLMT_RS_INIT. + * All ports are initialized to SK_RLMT_PS_INIT. + * + * + * SK_INIT_IO + * ========== + * + * Nothing. + * + * + * SK_INIT_RUN + * =========== + * + * Determine the adapter's random value. + * Set the hw registers, the "logical MAC address", the + * RLMT multicast address, and eventually the BPDU multicast address. + * + * Context: + * init, pageable + * + * Returns: + * Nothing. + */ +void SkRlmtInit( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Level) /* Initialization Level */ +{ + SK_U32 i, j; + SK_U64 Random; + SK_EVPARA Para; + SK_MAC_ADDR VirtualMacAddress; + SK_MAC_ADDR PhysicalAMacAddress; + SK_BOOL VirtualMacAddressSet; + SK_BOOL PhysicalAMacAddressSet; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT, + ("RLMT Init level %d.\n", Level)) + + switch (Level) { + case SK_INIT_DATA: /* Initialize data structures. */ + SK_MEMSET((char *)&pAC->Rlmt, 0, sizeof(SK_RLMT)); + + for (i = 0; i < SK_MAX_MACS; i++) { + pAC->Rlmt.Port[i].PortState = SK_RLMT_PS_INIT; + pAC->Rlmt.Port[i].LinkDown = SK_TRUE; + pAC->Rlmt.Port[i].PortDown = SK_TRUE; + pAC->Rlmt.Port[i].PortStarted = SK_FALSE; + pAC->Rlmt.Port[i].PortNoRx = SK_FALSE; + pAC->Rlmt.Port[i].RootIdSet = SK_FALSE; + pAC->Rlmt.Port[i].PortNumber = i; + pAC->Rlmt.Port[i].Net = &pAC->Rlmt.Net[0]; + pAC->Rlmt.Port[i].AddrPort = &pAC->Addr.Port[i]; + } + + pAC->Rlmt.NumNets = 1; + for (i = 0; i < SK_MAX_NETS; i++) { + pAC->Rlmt.Net[i].RlmtState = SK_RLMT_RS_INIT; + pAC->Rlmt.Net[i].RootIdSet = SK_FALSE; + pAC->Rlmt.Net[i].PrefPort = SK_RLMT_DEF_PREF_PORT; + pAC->Rlmt.Net[i].Preference = 0xFFFFFFFF; /* Automatic. */ + /* Just assuming. */ + pAC->Rlmt.Net[i].ActivePort = pAC->Rlmt.Net[i].PrefPort; + pAC->Rlmt.Net[i].RlmtMode = SK_RLMT_DEF_MODE; + pAC->Rlmt.Net[i].TimeoutValue = SK_RLMT_DEF_TO_VAL; + pAC->Rlmt.Net[i].NetNumber = i; + } + + pAC->Rlmt.Net[0].Port[0] = &pAC->Rlmt.Port[0]; + pAC->Rlmt.Net[0].Port[1] = &pAC->Rlmt.Port[1]; +#if SK_MAX_NETS > 1 + pAC->Rlmt.Net[1].Port[0] = &pAC->Rlmt.Port[1]; +#endif /* SK_MAX_NETS > 1 */ + break; + + case SK_INIT_IO: /* GIMacsFound first available here. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT, + ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound)) + + pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound; + + /* Initialize HW registers? */ + if (pAC->GIni.GIMacsFound == 1) { + Para.Para32[0] = SK_RLMT_MODE_CLS; + Para.Para32[1] = 0; + (void)SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE, Para); + } + break; + + case SK_INIT_RUN: + /* Ensure RLMT is set to one net. */ + if (pAC->Rlmt.NumNets > 1) { + Para.Para32[0] = 1; + Para.Para32[1] = -1; + SkRlmtEvtSetNets(pAC, IoC, Para); + } + + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + Random = SkOsGetTime(pAC); + *(SK_U32*)&pAC->Rlmt.Port[i].Random = *(SK_U32*)&Random; + + for (j = 0; j < 4; j++) { + pAC->Rlmt.Port[i].Random[j] ^= pAC->Rlmt.Port[i].AddrPort-> + CurrentMacAddress.a[SK_MAC_ADDR_LEN - 1 - j]; + } + + (void)SkAddrMcClear(pAC, IoC, i, SK_ADDR_PERMANENT | SK_MC_SW_ONLY); + + /* Add RLMT MC address. */ + (void)SkAddrMcAdd(pAC, IoC, i, &SkRlmtMcAddr, SK_ADDR_PERMANENT); + + if (pAC->Rlmt.Net[0].RlmtMode & SK_RLMT_CHECK_SEG) { + /* Add BPDU MC address. */ + (void)SkAddrMcAdd(pAC, IoC, i, &BridgeMcAddr, SK_ADDR_PERMANENT); + } + + (void)SkAddrMcUpdate(pAC, IoC, i); + } + + VirtualMacAddressSet = SK_FALSE; + /* Read virtual MAC address from Control Register File. */ + for (j = 0; j < SK_MAC_ADDR_LEN; j++) { + + SK_IN8(IoC, B2_MAC_1 + j, &VirtualMacAddress.a[j]); + VirtualMacAddressSet |= VirtualMacAddress.a[j]; + } + + PhysicalAMacAddressSet = SK_FALSE; + /* Read physical MAC address for MAC A from Control Register File. */ + for (j = 0; j < SK_MAC_ADDR_LEN; j++) { + + SK_IN8(IoC, B2_MAC_2 + j, &PhysicalAMacAddress.a[j]); + PhysicalAMacAddressSet |= PhysicalAMacAddress.a[j]; + } + + /* check if the two mac addresses contain reasonable values */ + if (!VirtualMacAddressSet || !PhysicalAMacAddressSet) { + + pAC->Rlmt.RlmtOff = SK_TRUE; + } + + /* if the two mac addresses are equal switch off the RLMT_PRE_LOOKAHEAD + and the RLMT_LOOKAHEAD macros */ + else if (SK_ADDR_EQUAL(PhysicalAMacAddress.a, VirtualMacAddress.a)) { + + pAC->Rlmt.RlmtOff = SK_TRUE; + } + else { + pAC->Rlmt.RlmtOff = SK_FALSE; + } + break; + + default: /* error */ + break; + } + return; +} /* SkRlmtInit */ + + +/****************************************************************************** + * + * SkRlmtBuildCheckChain - build the check chain + * + * Description: + * This routine builds the local check chain: + * - Each port that is up checks the next port. + * - The last port that is up checks the first port that is up. + * + * Notes: + * - Currently only local ports are considered when building the chain. + * - Currently the SuspectState is just reset; + * it would be better to save it ... + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtBuildCheckChain( +SK_AC *pAC, /* Adapter Context */ +SK_U32 NetIdx) /* Net Number */ +{ + SK_U32 i; + SK_U32 NumMacsUp; + SK_RLMT_PORT * FirstMacUp; + SK_RLMT_PORT * PrevMacUp; + + FirstMacUp = NULL; + PrevMacUp = NULL; + + if (!(pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_CHECK_LOC_LINK)) { + for (i = 0; i < pAC->Rlmt.Net[i].NumPorts; i++) { + pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked = 0; + } + return; /* Done. */ + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SkRlmtBuildCheckChain.\n")) + + NumMacsUp = 0; + + for (i = 0; i < pAC->Rlmt.Net[NetIdx].NumPorts; i++) { + pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked = 0; + pAC->Rlmt.Net[NetIdx].Port[i]->PortsSuspect = 0; + pAC->Rlmt.Net[NetIdx].Port[i]->CheckingState &= + ~(SK_RLMT_PCS_RX | SK_RLMT_PCS_TX); + + /* + * If more than two links are detected we should consider + * checking at least two other ports: + * 1. the next port that is not LinkDown and + * 2. the next port that is not PortDown. + */ + if (!pAC->Rlmt.Net[NetIdx].Port[i]->LinkDown) { + if (NumMacsUp == 0) { + FirstMacUp = pAC->Rlmt.Net[NetIdx].Port[i]; + } + else { + PrevMacUp->PortCheck[ + pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked].CheckAddr = + pAC->Rlmt.Net[NetIdx].Port[i]->AddrPort->CurrentMacAddress; + PrevMacUp->PortCheck[ + PrevMacUp->PortsChecked].SuspectTx = SK_FALSE; + PrevMacUp->PortsChecked++; + } + PrevMacUp = pAC->Rlmt.Net[NetIdx].Port[i]; + NumMacsUp++; + } + } + + if (NumMacsUp > 1) { + PrevMacUp->PortCheck[PrevMacUp->PortsChecked].CheckAddr = + FirstMacUp->AddrPort->CurrentMacAddress; + PrevMacUp->PortCheck[PrevMacUp->PortsChecked].SuspectTx = + SK_FALSE; + PrevMacUp->PortsChecked++; + } + +#ifdef DEBUG + for (i = 0; i < pAC->Rlmt.Net[NetIdx].NumPorts; i++) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Port %d checks %d other ports: %2X.\n", i, + pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked, + pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5])) + } +#endif /* DEBUG */ + + return; +} /* SkRlmtBuildCheckChain */ + + +/****************************************************************************** + * + * SkRlmtBuildPacket - build an RLMT packet + * + * Description: + * This routine sets up an RLMT packet. + * + * Context: + * runtime, pageable? + * + * Returns: + * NULL or pointer to RLMT mbuf + */ +RLMT_STATIC SK_MBUF *SkRlmtBuildPacket( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber, /* Sending port */ +SK_U16 PacketType, /* RLMT packet type */ +SK_MAC_ADDR *SrcAddr, /* Source address */ +SK_MAC_ADDR *DestAddr) /* Destination address */ +{ + int i; + SK_U16 Length; + SK_MBUF *pMb; + SK_RLMT_PACKET *pPacket; + +#ifdef DEBUG + SK_U8 CheckSrc = 0; + SK_U8 CheckDest = 0; + + for (i = 0; i < SK_MAC_ADDR_LEN; ++i) { + CheckSrc |= SrcAddr->a[i]; + CheckDest |= DestAddr->a[i]; + } + + if ((CheckSrc == 0) || (CheckDest == 0)) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_ERR, + ("SkRlmtBuildPacket: Invalid %s%saddr.\n", + (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : ""))) + } +#endif + + if ((pMb = SkDrvAllocRlmtMbuf(pAC, IoC, SK_RLMT_MAX_PACKET_SIZE)) != NULL) { + pPacket = (SK_RLMT_PACKET*)pMb->pData; + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + pPacket->DstAddr[i] = DestAddr->a[i]; + pPacket->SrcAddr[i] = SrcAddr->a[i]; + } + pPacket->DSap = SK_RLMT_DSAP; + pPacket->SSap = SK_RLMT_SSAP; + pPacket->Ctrl = SK_RLMT_CTRL; + pPacket->Indicator[0] = SK_RLMT_INDICATOR0; + pPacket->Indicator[1] = SK_RLMT_INDICATOR1; + pPacket->Indicator[2] = SK_RLMT_INDICATOR2; + pPacket->Indicator[3] = SK_RLMT_INDICATOR3; + pPacket->Indicator[4] = SK_RLMT_INDICATOR4; + pPacket->Indicator[5] = SK_RLMT_INDICATOR5; + pPacket->Indicator[6] = SK_RLMT_INDICATOR6; + + SK_U16_TO_NETWORK_ORDER(PacketType, &pPacket->RlmtPacketType[0]); + + for (i = 0; i < 4; i++) { + pPacket->Random[i] = pAC->Rlmt.Port[PortNumber].Random[i]; + } + + SK_U16_TO_NETWORK_ORDER( + SK_RLMT_PACKET_VERSION, &pPacket->RlmtPacketVersion[0]); + + for (i = 0; i < SK_PACKET_DATA_LEN; i++) { + pPacket->Data[i] = 0x00; + } + + Length = SK_RLMT_MAX_PACKET_SIZE; /* Or smaller. */ + pMb->Length = Length; + pMb->PortIdx = PortNumber; + Length -= 14; + SK_U16_TO_NETWORK_ORDER(Length, &pPacket->TypeLen[0]); + + if (PacketType == SK_PACKET_ALIVE) { + pAC->Rlmt.Port[PortNumber].TxHelloCts++; + } + } + + return (pMb); +} /* SkRlmtBuildPacket */ + + +/****************************************************************************** + * + * SkRlmtBuildSpanningTreePacket - build spanning tree check packet + * + * Description: + * This routine sets up a BPDU packet for spanning tree check. + * + * Context: + * runtime, pageable? + * + * Returns: + * NULL or pointer to RLMT mbuf + */ +RLMT_STATIC SK_MBUF *SkRlmtBuildSpanningTreePacket( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Sending port */ +{ + unsigned i; + SK_U16 Length; + SK_MBUF *pMb; + SK_SPTREE_PACKET *pSPacket; + + if ((pMb = SkDrvAllocRlmtMbuf(pAC, IoC, SK_RLMT_MAX_PACKET_SIZE)) != + NULL) { + pSPacket = (SK_SPTREE_PACKET*)pMb->pData; + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + pSPacket->DstAddr[i] = BridgeMcAddr.a[i]; + pSPacket->SrcAddr[i] = + pAC->Addr.Port[PortNumber].CurrentMacAddress.a[i]; + } + pSPacket->DSap = SK_RLMT_SPT_DSAP; + pSPacket->SSap = SK_RLMT_SPT_SSAP; + pSPacket->Ctrl = SK_RLMT_SPT_CTRL; + + pSPacket->ProtocolId[0] = SK_RLMT_SPT_PROTOCOL_ID0; + pSPacket->ProtocolId[1] = SK_RLMT_SPT_PROTOCOL_ID1; + pSPacket->ProtocolVersionId = SK_RLMT_SPT_PROTOCOL_VERSION_ID; + pSPacket->BpduType = SK_RLMT_SPT_BPDU_TYPE; + pSPacket->Flags = SK_RLMT_SPT_FLAGS; + pSPacket->RootId[0] = SK_RLMT_SPT_ROOT_ID0; + pSPacket->RootId[1] = SK_RLMT_SPT_ROOT_ID1; + pSPacket->RootPathCost[0] = SK_RLMT_SPT_ROOT_PATH_COST0; + pSPacket->RootPathCost[1] = SK_RLMT_SPT_ROOT_PATH_COST1; + pSPacket->RootPathCost[2] = SK_RLMT_SPT_ROOT_PATH_COST2; + pSPacket->RootPathCost[3] = SK_RLMT_SPT_ROOT_PATH_COST3; + pSPacket->BridgeId[0] = SK_RLMT_SPT_BRIDGE_ID0; + pSPacket->BridgeId[1] = SK_RLMT_SPT_BRIDGE_ID1; + + /* + * Use logical MAC address as bridge ID and filter these packets + * on receive. + */ + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + pSPacket->BridgeId[i + 2] = pSPacket->RootId[i + 2] = + pAC->Addr.Net[pAC->Rlmt.Port[PortNumber].Net->NetNumber]. + CurrentMacAddress.a[i]; + } + pSPacket->PortId[0] = SK_RLMT_SPT_PORT_ID0; + pSPacket->PortId[1] = SK_RLMT_SPT_PORT_ID1; + pSPacket->MessageAge[0] = SK_RLMT_SPT_MSG_AGE0; + pSPacket->MessageAge[1] = SK_RLMT_SPT_MSG_AGE1; + pSPacket->MaxAge[0] = SK_RLMT_SPT_MAX_AGE0; + pSPacket->MaxAge[1] = SK_RLMT_SPT_MAX_AGE1; + pSPacket->HelloTime[0] = SK_RLMT_SPT_HELLO_TIME0; + pSPacket->HelloTime[1] = SK_RLMT_SPT_HELLO_TIME1; + pSPacket->ForwardDelay[0] = SK_RLMT_SPT_FWD_DELAY0; + pSPacket->ForwardDelay[1] = SK_RLMT_SPT_FWD_DELAY1; + + Length = SK_RLMT_MAX_PACKET_SIZE; /* Or smaller. */ + pMb->Length = Length; + pMb->PortIdx = PortNumber; + Length -= 14; + SK_U16_TO_NETWORK_ORDER(Length, &pSPacket->TypeLen[0]); + + pAC->Rlmt.Port[PortNumber].TxSpHelloReqCts++; + } + + return (pMb); +} /* SkRlmtBuildSpanningTreePacket */ + + +/****************************************************************************** + * + * SkRlmtSend - build and send check packets + * + * Description: + * Depending on the RLMT state and the checking state, several packets + * are sent through the indicated port. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtSend( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Sending port */ +{ + unsigned j; + SK_EVPARA Para; + SK_RLMT_PORT *pRPort; + + pRPort = &pAC->Rlmt.Port[PortNumber]; + if (pAC->Rlmt.Port[PortNumber].Net->RlmtMode & SK_RLMT_CHECK_LOC_LINK) { + if (pRPort->CheckingState & (SK_RLMT_PCS_TX | SK_RLMT_PCS_RX)) { + /* Port is suspicious. Send the RLMT packet to the RLMT mc addr. */ + if ((Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, PortNumber, + SK_PACKET_ALIVE, &pAC->Addr.Port[PortNumber].CurrentMacAddress, + &SkRlmtMcAddr)) != NULL) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + } + else { + /* + * Send a directed RLMT packet to all ports that are + * checked by the indicated port. + */ + for (j = 0; j < pRPort->PortsChecked; j++) { + if ((Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, PortNumber, + SK_PACKET_ALIVE, &pAC->Addr.Port[PortNumber].CurrentMacAddress, + &pRPort->PortCheck[j].CheckAddr)) != NULL) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + } + } + } + + if ((pAC->Rlmt.Port[PortNumber].Net->RlmtMode & SK_RLMT_CHECK_SEG) && + (pAC->Rlmt.Port[PortNumber].Net->CheckingState & SK_RLMT_RCS_SEND_SEG)) { + /* + * Send a BPDU packet to make a connected switch tell us + * the correct root bridge. + */ + if ((Para.pParaPtr = + SkRlmtBuildSpanningTreePacket(pAC, IoC, PortNumber)) != NULL) { + pAC->Rlmt.Port[PortNumber].Net->CheckingState &= ~SK_RLMT_RCS_SEND_SEG; + pRPort->RootIdSet = SK_FALSE; + + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_TX, + ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber)) + } + } + return; +} /* SkRlmtSend */ + + +/****************************************************************************** + * + * SkRlmtPortReceives - check if port is (going) down and bring it up + * + * Description: + * This routine checks if a port who received a non-BPDU packet + * needs to go up or needs to be stopped going down. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtPortReceives( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Port to check */ +{ + SK_RLMT_PORT *pRPort; + SK_EVPARA Para; + + pRPort = &pAC->Rlmt.Port[PortNumber]; + pRPort->PortNoRx = SK_FALSE; + + if ((pRPort->PortState == SK_RLMT_PS_DOWN) && + !(pRPort->CheckingState & SK_RLMT_PCS_TX)) { + /* + * Port is marked down (rx), but received a non-BPDU packet. + * Bring it up. + */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Received on PortDown.\n")) + + pRPort->PortState = SK_RLMT_PS_GOING_UP; + pRPort->GuTimeStamp = SkOsGetTime(pAC); + Para.Para32[0] = PortNumber; + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->UpTimer, SK_RLMT_PORTUP_TIM_VAL, + SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para); + pRPort->CheckingState &= ~SK_RLMT_PCS_RX; + /* pAC->Rlmt.CheckSwitch = SK_TRUE; */ + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } /* PortDown && !SuspectTx */ + else if (pRPort->CheckingState & SK_RLMT_PCS_RX) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Stop bringing port down.\n")) + SkTimerStop(pAC, IoC, &pRPort->DownRxTimer); + pRPort->CheckingState &= ~SK_RLMT_PCS_RX; + /* pAC->Rlmt.CheckSwitch = SK_TRUE; */ + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } /* PortGoingDown */ + + return; +} /* SkRlmtPortReceives */ + + +/****************************************************************************** + * + * SkRlmtPacketReceive - receive a packet for closer examination + * + * Description: + * This routine examines a packet more closely than SK_RLMT_LOOKAHEAD. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtPacketReceive( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_MBUF *pMb) /* Received packet */ +{ +#ifdef xDEBUG + extern void DumpData(char *p, int size); +#endif /* DEBUG */ + int i; + unsigned j; + SK_U16 PacketType; + SK_U32 PortNumber; + SK_ADDR_PORT *pAPort; + SK_RLMT_PORT *pRPort; + SK_RLMT_PACKET *pRPacket; + SK_SPTREE_PACKET *pSPacket; + SK_EVPARA Para; + + PortNumber = pMb->PortIdx; + pAPort = &pAC->Addr.Port[PortNumber]; + pRPort = &pAC->Rlmt.Port[PortNumber]; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber)) + + pRPacket = (SK_RLMT_PACKET*)pMb->pData; + pSPacket = (SK_SPTREE_PACKET*)pRPacket; + +#ifdef xDEBUG + DumpData((char *)pRPacket, 32); +#endif /* DEBUG */ + + if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) != 0) { + SkRlmtPortReceives(pAC, IoC, PortNumber); + } + + /* Check destination address. */ + + if (!SK_ADDR_EQUAL(pAPort->CurrentMacAddress.a, pRPacket->DstAddr) && + !SK_ADDR_EQUAL(SkRlmtMcAddr.a, pRPacket->DstAddr) && + !SK_ADDR_EQUAL(BridgeMcAddr.a, pRPacket->DstAddr)) { + + /* Not sent to current MAC or registered MC address => Trash it. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Not for me.\n")) + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + return; + } + else if (SK_ADDR_EQUAL(pAPort->CurrentMacAddress.a, pRPacket->SrcAddr)) { + + /* + * Was sent by same port (may happen during port switching + * or in case of duplicate MAC addresses). + */ + + /* + * Check for duplicate address here: + * If Packet.Random != My.Random => DupAddr. + */ + for (i = 3; i >= 0; i--) { + if (pRPort->Random[i] != pRPacket->Random[i]) { + break; + } + } + + /* + * CAUTION: Do not check for duplicate MAC address in RLMT Alive Reply + * packets (they have the LLC_COMMAND_RESPONSE_BIT set in + * pRPacket->SSap). + */ + if (i >= 0 && pRPacket->DSap == SK_RLMT_DSAP && + pRPacket->Ctrl == SK_RLMT_CTRL && + pRPacket->SSap == SK_RLMT_SSAP && + pRPacket->Indicator[0] == SK_RLMT_INDICATOR0 && + pRPacket->Indicator[1] == SK_RLMT_INDICATOR1 && + pRPacket->Indicator[2] == SK_RLMT_INDICATOR2 && + pRPacket->Indicator[3] == SK_RLMT_INDICATOR3 && + pRPacket->Indicator[4] == SK_RLMT_INDICATOR4 && + pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 && + pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Duplicate MAC Address.\n")) + + /* Error Log entry. */ + SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E006, SKERR_RLMT_E006_MSG); + } + else { + /* Simply trash it. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Sent by me.\n")) + } + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + return; + } + + /* Check SuspectTx entries. */ + if (pRPort->PortsSuspect > 0) { + for (j = 0; j < pRPort->PortsChecked; j++) { + if (pRPort->PortCheck[j].SuspectTx && + SK_ADDR_EQUAL( + pRPacket->SrcAddr, pRPort->PortCheck[j].CheckAddr.a)) { + pRPort->PortCheck[j].SuspectTx = SK_FALSE; + pRPort->PortsSuspect--; + break; + } + } + } + + /* Determine type of packet. */ + if (pRPacket->DSap == SK_RLMT_DSAP && + pRPacket->Ctrl == SK_RLMT_CTRL && + (pRPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SSAP && + pRPacket->Indicator[0] == SK_RLMT_INDICATOR0 && + pRPacket->Indicator[1] == SK_RLMT_INDICATOR1 && + pRPacket->Indicator[2] == SK_RLMT_INDICATOR2 && + pRPacket->Indicator[3] == SK_RLMT_INDICATOR3 && + pRPacket->Indicator[4] == SK_RLMT_INDICATOR4 && + pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 && + pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) { + + /* It's an RLMT packet. */ + PacketType = (SK_U16)((pRPacket->RlmtPacketType[0] << 8) | + pRPacket->RlmtPacketType[1]); + + switch (PacketType) { + case SK_PACKET_ANNOUNCE: /* Not yet used. */ +#if 0 + /* Build the check chain. */ + SkRlmtBuildCheckChain(pAC); +#endif /* 0 */ + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Announce.\n")) + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + break; + + case SK_PACKET_ALIVE: + if (pRPacket->SSap & LLC_COMMAND_RESPONSE_BIT) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Alive Reply.\n")) + + if (!(pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_LLC) || + SK_ADDR_EQUAL( + pRPacket->DstAddr, pAPort->CurrentMacAddress.a)) { + /* Obviously we could send something. */ + if (pRPort->CheckingState & SK_RLMT_PCS_TX) { + pRPort->CheckingState &= ~SK_RLMT_PCS_TX; + SkTimerStop(pAC, IoC, &pRPort->DownTxTimer); + } + + if ((pRPort->PortState == SK_RLMT_PS_DOWN) && + !(pRPort->CheckingState & SK_RLMT_PCS_RX)) { + pRPort->PortState = SK_RLMT_PS_GOING_UP; + pRPort->GuTimeStamp = SkOsGetTime(pAC); + + SkTimerStop(pAC, IoC, &pRPort->DownTxTimer); + + Para.Para32[0] = PortNumber; + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->UpTimer, + SK_RLMT_PORTUP_TIM_VAL, SKGE_RLMT, + SK_RLMT_PORTUP_TIM, Para); + } + } + + /* Mark sending port as alive? */ + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + } + else { /* Alive Request Packet. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Alive Request.\n")) + + pRPort->RxHelloCts++; + + /* Answer. */ + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + pRPacket->DstAddr[i] = pRPacket->SrcAddr[i]; + pRPacket->SrcAddr[i] = + pAC->Addr.Port[PortNumber].CurrentMacAddress.a[i]; + } + pRPacket->SSap |= LLC_COMMAND_RESPONSE_BIT; + + Para.pParaPtr = pMb; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + break; + + case SK_PACKET_CHECK_TX: + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Check your tx line.\n")) + + /* A port checking us requests us to check our tx line. */ + pRPort->CheckingState |= SK_RLMT_PCS_TX; + + /* Start PortDownTx timer. */ + Para.Para32[0] = PortNumber; + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->DownTxTimer, + SK_RLMT_PORTDOWN_TIM_VAL, SKGE_RLMT, + SK_RLMT_PORTDOWN_TX_TIM, Para); + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + + if ((Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, PortNumber, + SK_PACKET_ALIVE, &pAC->Addr.Port[PortNumber].CurrentMacAddress, + &SkRlmtMcAddr)) != NULL) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + break; + + case SK_PACKET_ADDR_CHANGED: + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Address Change.\n")) + + /* Build the check chain. */ + SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber); + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Unknown RLMT packet.\n")) + + /* RA;:;: ??? */ + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + } + } + else if (pSPacket->DSap == SK_RLMT_SPT_DSAP && + pSPacket->Ctrl == SK_RLMT_SPT_CTRL && + (pSPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SPT_SSAP) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: BPDU Packet.\n")) + + /* Spanning Tree packet. */ + pRPort->RxSpHelloCts++; + + if (!SK_ADDR_EQUAL(&pSPacket->RootId[2], &pAC->Addr.Net[pAC->Rlmt. + Port[PortNumber].Net->NetNumber].CurrentMacAddress.a[0])) { + /* + * Check segmentation if a new root bridge is set and + * the segmentation check is not currently running. + */ + if (!SK_ADDR_EQUAL(&pSPacket->RootId[2], &pRPort->Root.Id[2]) && + (pAC->Rlmt.Port[PortNumber].Net->LinksUp > 1) && + (pAC->Rlmt.Port[PortNumber].Net->RlmtMode & SK_RLMT_CHECK_SEG) + != 0 && (pAC->Rlmt.Port[PortNumber].Net->CheckingState & + SK_RLMT_RCS_SEG) == 0) { + pAC->Rlmt.Port[PortNumber].Net->CheckingState |= + SK_RLMT_RCS_START_SEG | SK_RLMT_RCS_SEND_SEG; + } + + /* Store tree view of this port. */ + for (i = 0; i < 8; i++) { + pRPort->Root.Id[i] = pSPacket->RootId[i]; + } + pRPort->RootIdSet = SK_TRUE; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_DUMP, + ("Root ID %d: %02x %02x %02x %02x %02x %02x %02x %02x.\n", + PortNumber, + pRPort->Root.Id[0], pRPort->Root.Id[1], + pRPort->Root.Id[2], pRPort->Root.Id[3], + pRPort->Root.Id[4], pRPort->Root.Id[5], + pRPort->Root.Id[6], pRPort->Root.Id[7])) + } + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + if ((pAC->Rlmt.Port[PortNumber].Net->CheckingState & + SK_RLMT_RCS_REPORT_SEG) != 0) { + SkRlmtCheckSeg(pAC, IoC, pAC->Rlmt.Port[PortNumber].Net->NetNumber); + } + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Unknown Packet Type.\n")) + + /* Unknown packet. */ + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + } + return; +} /* SkRlmtPacketReceive */ + + +/****************************************************************************** + * + * SkRlmtCheckPort - check if a port works + * + * Description: + * This routine checks if a port whose link is up received something + * and if it seems to transmit successfully. + * + * # PortState: PsInit, PsLinkDown, PsDown, PsGoingUp, PsUp + * # PortCheckingState (Bitfield): ChkTx, ChkRx, ChkSeg + * # RlmtCheckingState (Bitfield): ChkSeg, StartChkSeg, ReportSeg + * + * if (Rx - RxBpdu == 0) { # No rx. + * if (state == PsUp) { + * PortCheckingState |= ChkRx + * } + * if (ModeCheckSeg && (Timeout == + * TO_SHORTEN(RLMT_DEFAULT_TIMEOUT))) { + * RlmtCheckingState |= ChkSeg) + * PortCheckingState |= ChkSeg + * } + * NewTimeout = TO_SHORTEN(Timeout) + * if (NewTimeout < RLMT_MIN_TIMEOUT) { + * NewTimeout = RLMT_MIN_TIMEOUT + * PortState = PsDown + * ... + * } + * } + * else { # something was received + * # Set counter to 0 at LinkDown? + * # No - rx may be reported after LinkDown ??? + * PortCheckingState &= ~ChkRx + * NewTimeout = RLMT_DEFAULT_TIMEOUT + * if (RxAck == 0) { + * possible reasons: + * is my tx line bad? -- + * send RLMT multicast and report + * back internally? (only possible + * between ports on same adapter) + * } + * if (RxChk == 0) { + * possible reasons: + * - tx line of port set to check me + * maybe bad + * - no other port/adapter available or set + * to check me + * - adapter checking me has a longer + * timeout + * ??? anything that can be done here? + * } + * } + * + * Context: + * runtime, pageable? + * + * Returns: + * New timeout value. + */ +RLMT_STATIC SK_U32 SkRlmtCheckPort( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Port to check */ +{ + unsigned i; + SK_U32 NewTimeout; + SK_RLMT_PORT *pRPort; + SK_EVPARA Para; + + pRPort = &pAC->Rlmt.Port[PortNumber]; + + if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) == 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SkRlmtCheckPort %d: No (%d) receives in last time slot.\n", + PortNumber, pRPort->PacketsPerTimeSlot)) + + /* + * Check segmentation if there was no receive at least twice + * in a row (PortNoRx is already set) and the segmentation + * check is not currently running. + */ + + if (pRPort->PortNoRx && (pAC->Rlmt.Port[PortNumber].Net->LinksUp > 1) && + (pAC->Rlmt.Port[PortNumber].Net->RlmtMode & SK_RLMT_CHECK_SEG) && + !(pAC->Rlmt.Port[PortNumber].Net->CheckingState & SK_RLMT_RCS_SEG)) { + pAC->Rlmt.Port[PortNumber].Net->CheckingState |= + SK_RLMT_RCS_START_SEG | SK_RLMT_RCS_SEND_SEG; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SkRlmtCheckPort: PortsSuspect %d, PcsRx %d.\n", + pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX)) + + if (pRPort->PortState != SK_RLMT_PS_DOWN) { + NewTimeout = TO_SHORTEN(pAC->Rlmt.Port[PortNumber].Net->TimeoutValue); + if (NewTimeout < SK_RLMT_MIN_TO_VAL) { + NewTimeout = SK_RLMT_MIN_TO_VAL; + } + + if (!(pRPort->CheckingState & SK_RLMT_PCS_RX)) { + Para.Para32[0] = PortNumber; + pRPort->CheckingState |= SK_RLMT_PCS_RX; + + /* + * What shall we do if the port checked by this one receives + * our request frames? What's bad - our rx line or his tx line? + */ + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->DownRxTimer, + SK_RLMT_PORTDOWN_TIM_VAL, SKGE_RLMT, + SK_RLMT_PORTDOWN_RX_TIM, Para); + + for (i = 0; i < pRPort->PortsChecked; i++) { + if (pRPort->PortCheck[i].SuspectTx) { + continue; + } + pRPort->PortCheck[i].SuspectTx = SK_TRUE; + pRPort->PortsSuspect++; + if ((Para.pParaPtr = + SkRlmtBuildPacket(pAC, IoC, PortNumber, SK_PACKET_CHECK_TX, + &pAC->Addr.Port[PortNumber].CurrentMacAddress, + &pRPort->PortCheck[i].CheckAddr)) != NULL) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + } + } + } + else { /* PortDown -- or all partners suspect. */ + NewTimeout = SK_RLMT_DEF_TO_VAL; + } + pRPort->PortNoRx = SK_TRUE; + } + else { /* A non-BPDU packet was received. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SkRlmtCheckPort %d: %d (%d) receives in last time slot.\n", + PortNumber, + pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot, + pRPort->PacketsPerTimeSlot)) + + SkRlmtPortReceives(pAC, IoC, PortNumber); + if (pAC->Rlmt.CheckSwitch) { + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } + + NewTimeout = SK_RLMT_DEF_TO_VAL; + } + + return (NewTimeout); +} /* SkRlmtCheckPort */ + + +/****************************************************************************** + * + * SkRlmtSelectBcRx - select new active port, criteria 1 (CLP) + * + * Description: + * This routine selects the port that received a broadcast frame + * substantially later than all other ports. + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectBcRx( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect) /* New active port */ +{ + SK_U64 BcTimeStamp; + SK_U32 i; + SK_BOOL PortFound; + + BcTimeStamp = 0; /* Not totally necessary, but feeling better. */ + PortFound = SK_FALSE; + + /* Select port with the latest TimeStamp. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("TimeStamp Port %d (Down: %d, NoRx: %d): %08x %08x.\n", + i, + pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx, + *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_HI32), + *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32))) + + if (!pAC->Rlmt.Port[i].PortDown && !pAC->Rlmt.Port[i].PortNoRx) { + if (!PortFound || pAC->Rlmt.Port[i].BcTimeStamp > BcTimeStamp) { + BcTimeStamp = pAC->Rlmt.Port[i].BcTimeStamp; + *pSelect = i; + PortFound = SK_TRUE; + } + } + } + + if (PortFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Port %d received the last broadcast.\n", *pSelect)) + + /* Look if another port's time stamp is similar. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (i == *pSelect) { + continue; + } + if (!pAC->Rlmt.Port[i].PortDown && !pAC->Rlmt.Port[i].PortNoRx && + (pAC->Rlmt.Port[i].BcTimeStamp > + BcTimeStamp - SK_RLMT_BC_DELTA || + pAC->Rlmt.Port[i].BcTimeStamp + + SK_RLMT_BC_DELTA > BcTimeStamp)) { + PortFound = SK_FALSE; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Port %d received a broadcast at a similar time.\n", i)) + break; + } + } + } + +#ifdef DEBUG + if (PortFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_BCRX found Port %d receiving the substantially " + "latest broadcast (%u).\n", + *pSelect, + BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp)) + } +#endif /* DEBUG */ + + return (PortFound); +} /* SkRlmtSelectBcRx */ + + +/****************************************************************************** + * + * SkRlmtSelectNotSuspect - select new active port, criteria 2 (CLP) + * + * Description: + * This routine selects a good port (it is PortUp && !SuspectRx). + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectNotSuspect( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect) /* New active port */ +{ + SK_U32 i; + SK_BOOL PortFound; + + PortFound = SK_FALSE; + + /* Select first port that is PortUp && !SuspectRx. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (!pAC->Rlmt.Port[i].PortDown && + !(pAC->Rlmt.Port[i].CheckingState & SK_RLMT_PCS_RX)) { + *pSelect = i; + if (!pAC->Rlmt.Port[Active].PortDown && + !(pAC->Rlmt.Port[Active].CheckingState & SK_RLMT_PCS_RX)) { + *pSelect = Active; + } + if (!pAC->Rlmt.Port[PrefPort].PortDown && + !(pAC->Rlmt.Port[PrefPort].CheckingState & SK_RLMT_PCS_RX)) { + *pSelect = PrefPort; + } + PortFound = SK_TRUE; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_NOTSUSPECT found Port %d up and not check RX.\n", + *pSelect)) + break; + } + } + return (PortFound); +} /* SkRlmtSelectNotSuspect */ + + +/****************************************************************************** + * + * SkRlmtSelectUp - select new active port, criteria 3, 4 (CLP) + * + * Description: + * This routine selects a port that is up. + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectUp( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect, /* New active port */ +SK_BOOL AutoNegDone) /* Successfully auto-negotiated? */ +{ + SK_U32 i; + SK_BOOL PortFound; + + PortFound = SK_FALSE; + + /* Select first port that is PortUp. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_UP && + pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) { + *pSelect = i; + if (pAC->Rlmt.Port[Active].PortState == SK_RLMT_PS_UP && + pAC->GIni.GP[Active].PAutoNegFail != AutoNegDone) { + *pSelect = Active; + } + if (pAC->Rlmt.Port[PrefPort].PortState == SK_RLMT_PS_UP && + pAC->GIni.GP[PrefPort].PAutoNegFail != AutoNegDone) { + *pSelect = PrefPort; + } + PortFound = SK_TRUE; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect)) + break; + } + } + return (PortFound); +} /* SkRlmtSelectUp */ + + +/****************************************************************************** + * + * SkRlmtSelectGoingUp - select new active port, criteria 5, 6 (CLP) + * + * Description: + * This routine selects the port that is going up for the longest time. + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectGoingUp( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect, /* New active port */ +SK_BOOL AutoNegDone) /* Successfully auto-negotiated? */ +{ + SK_U64 GuTimeStamp; + SK_U32 i; + SK_BOOL PortFound; + + GuTimeStamp = 0; + PortFound = SK_FALSE; + + /* Select port that is PortGoingUp for the longest time. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_GOING_UP && + pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) { + GuTimeStamp = pAC->Rlmt.Port[i].GuTimeStamp; + *pSelect = i; + PortFound = SK_TRUE; + break; + } + } + + if (!PortFound) { + return (SK_FALSE); + } + + for (i = *pSelect + 1; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_GOING_UP && + pAC->Rlmt.Port[i].GuTimeStamp < GuTimeStamp && + pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) { + GuTimeStamp = pAC->Rlmt.Port[i].GuTimeStamp; + *pSelect = i; + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect)) + return (SK_TRUE); +} /* SkRlmtSelectGoingUp */ + + +/****************************************************************************** + * + * SkRlmtSelectDown - select new active port, criteria 7, 8 (CLP) + * + * Description: + * This routine selects a port that is down. + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectDown( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect, /* New active port */ +SK_BOOL AutoNegDone) /* Successfully auto-negotiated? */ +{ + SK_U32 i; + SK_BOOL PortFound; + + PortFound = SK_FALSE; + + /* Select first port that is PortDown. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_DOWN && + pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) { + *pSelect = i; + if (pAC->Rlmt.Port[Active].PortState == SK_RLMT_PS_DOWN && + pAC->GIni.GP[Active].PAutoNegFail != AutoNegDone) { + *pSelect = Active; + } + if (pAC->Rlmt.Port[PrefPort].PortState == SK_RLMT_PS_DOWN && + pAC->GIni.GP[PrefPort].PAutoNegFail != AutoNegDone) { + *pSelect = PrefPort; + } + PortFound = SK_TRUE; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect)) + break; + } + } + return (PortFound); +} /* SkRlmtSelectDown */ + + +/****************************************************************************** + * + * SkRlmtCheckSwitch - select new active port and switch to it + * + * Description: + * This routine decides which port should be the active one and queues + * port switching if necessary. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtCheckSwitch( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 NetIdx) /* Net index */ +{ + SK_EVPARA Para; + SK_U32 Active; + SK_U32 PrefPort; + SK_U32 i; + SK_BOOL PortFound; + + Active = pAC->Rlmt.Net[NetIdx].ActivePort; /* Index of active port. */ + PrefPort = pAC->Rlmt.Net[NetIdx].PrefPort; /* Index of preferred port. */ + PortFound = SK_FALSE; + pAC->Rlmt.CheckSwitch = SK_FALSE; + +#if 0 /* RW 2001/10/18 - active port becomes always prefered one */ + if (pAC->Rlmt.Net[NetIdx].Preference == 0xFFFFFFFF) { /* Automatic */ + /* disable auto-fail back */ + PrefPort = Active; + } +#endif + + if (pAC->Rlmt.Net[NetIdx].LinksUp == 0) { + /* Last link went down - shut down the net. */ + pAC->Rlmt.Net[NetIdx].RlmtState = SK_RLMT_RS_NET_DOWN; + Para.Para32[0] = SK_RLMT_NET_DOWN_TEMP; + Para.Para32[1] = NetIdx; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_DOWN, Para); + + Para.Para32[0] = pAC->Rlmt.Net[NetIdx]. + Port[pAC->Rlmt.Net[NetIdx].ActivePort]->PortNumber; + Para.Para32[1] = NetIdx; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_ACTIVE_DOWN, Para); + return; + } /* pAC->Rlmt.LinksUp == 0 */ + else if (pAC->Rlmt.Net[NetIdx].LinksUp == 1 && + pAC->Rlmt.Net[NetIdx].RlmtState == SK_RLMT_RS_NET_DOWN) { + /* First link came up - get the net up. */ + pAC->Rlmt.Net[NetIdx].RlmtState = SK_RLMT_RS_NET_UP; + + /* + * If pAC->Rlmt.ActivePort != Para.Para32[0], + * the DRV switches to the port that came up. + */ + for (i = 0; i < pAC->Rlmt.Net[NetIdx].NumPorts; i++) { + if (!pAC->Rlmt.Net[NetIdx].Port[i]->LinkDown) { + if (!pAC->Rlmt.Net[NetIdx].Port[Active]->LinkDown) { + i = Active; + } + if (!pAC->Rlmt.Net[NetIdx].Port[PrefPort]->LinkDown) { + i = PrefPort; + } + PortFound = SK_TRUE; + break; + } + } + + if (PortFound) { + Para.Para32[0] = pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber; + Para.Para32[1] = NetIdx; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_ACTIVE_UP, Para); + + pAC->Rlmt.Net[NetIdx].ActivePort = i; + Para.Para32[0] = pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber; + Para.Para32[1] = NetIdx; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_UP, Para); + + if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 && + (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, + pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber, + SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx]. + CurrentMacAddress, &SkRlmtMcAddr)) != NULL) { + /* + * Send announce packet to RLMT multicast address to force + * switches to learn the new location of the logical MAC address. + */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E007, SKERR_RLMT_E007_MSG); + } + + return; + } /* LinksUp == 1 && RlmtState == SK_RLMT_RS_NET_DOWN */ + else { /* Cannot be reached in dual-net mode. */ + Para.Para32[0] = Active; + + /* + * Preselection: + * If RLMT Mode != CheckLinkState + * select port that received a broadcast frame substantially later + * than all other ports + * else select first port that is not SuspectRx + * else select first port that is PortUp + * else select port that is PortGoingUp for the longest time + * else select first port that is PortDown + * else stop. + * + * For the preselected port: + * If ActivePort is equal in quality, select ActivePort. + * + * If PrefPort is equal in quality, select PrefPort. + * + * If ActivePort != SelectedPort, + * If old ActivePort is LinkDown, + * SwitchHard + * else + * SwitchSoft + */ + /* check of ChgBcPrio flag added */ + if ((pAC->Rlmt.Net[0].RlmtMode != SK_RLMT_MODE_CLS) && + (!pAC->Rlmt.Net[0].ChgBcPrio)) { + + if (!PortFound) { + PortFound = SkRlmtSelectBcRx( + pAC, IoC, Active, PrefPort, &Para.Para32[1]); + } + + if (!PortFound) { + PortFound = SkRlmtSelectNotSuspect( + pAC, IoC, Active, PrefPort, &Para.Para32[1]); + } + } /* pAC->Rlmt.RlmtMode != SK_RLMT_MODE_CLS */ + + /* with changed priority for last broadcast received */ + if ((pAC->Rlmt.Net[0].RlmtMode != SK_RLMT_MODE_CLS) && + (pAC->Rlmt.Net[0].ChgBcPrio)) { + if (!PortFound) { + PortFound = SkRlmtSelectNotSuspect( + pAC, IoC, Active, PrefPort, &Para.Para32[1]); + } + + if (!PortFound) { + PortFound = SkRlmtSelectBcRx( + pAC, IoC, Active, PrefPort, &Para.Para32[1]); + } + } /* pAC->Rlmt.RlmtMode != SK_RLMT_MODE_CLS */ + + if (!PortFound) { + PortFound = SkRlmtSelectUp( + pAC, IoC, Active, PrefPort, &Para.Para32[1], AUTONEG_SUCCESS); + } + + if (!PortFound) { + PortFound = SkRlmtSelectUp( + pAC, IoC, Active, PrefPort, &Para.Para32[1], AUTONEG_FAILED); + } + + if (!PortFound) { + PortFound = SkRlmtSelectGoingUp( + pAC, IoC, Active, PrefPort, &Para.Para32[1], AUTONEG_SUCCESS); + } + + if (!PortFound) { + PortFound = SkRlmtSelectGoingUp( + pAC, IoC, Active, PrefPort, &Para.Para32[1], AUTONEG_FAILED); + } + + if (pAC->Rlmt.Net[0].RlmtMode != SK_RLMT_MODE_CLS) { + if (!PortFound) { + PortFound = SkRlmtSelectDown(pAC, IoC, + Active, PrefPort, &Para.Para32[1], AUTONEG_SUCCESS); + } + + if (!PortFound) { + PortFound = SkRlmtSelectDown(pAC, IoC, + Active, PrefPort, &Para.Para32[1], AUTONEG_FAILED); + } + } /* pAC->Rlmt.RlmtMode != SK_RLMT_MODE_CLS */ + + if (PortFound) { + + if (Para.Para32[1] != Active) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Active: %d, Para1: %d.\n", Active, Para.Para32[1])) + pAC->Rlmt.Net[NetIdx].ActivePort = Para.Para32[1]; + Para.Para32[0] = pAC->Rlmt.Net[NetIdx]. + Port[Para.Para32[0]]->PortNumber; + Para.Para32[1] = pAC->Rlmt.Net[NetIdx]. + Port[Para.Para32[1]]->PortNumber; + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[1], SK_LED_ACTIVE); + if (pAC->Rlmt.Port[Active].LinkDown) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_HARD, Para); + } + else { + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[0], SK_LED_STANDBY); + SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_SOFT, Para); + } + Para.Para32[1] = NetIdx; + Para.Para32[0] = + pAC->Rlmt.Net[NetIdx].Port[Para.Para32[0]]->PortNumber; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_ACTIVE_DOWN, Para); + Para.Para32[0] = pAC->Rlmt.Net[NetIdx]. + Port[pAC->Rlmt.Net[NetIdx].ActivePort]->PortNumber; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_ACTIVE_UP, Para); + if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 && + (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], + SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].CurrentMacAddress, + &SkRlmtMcAddr)) != NULL) { + /* + * Send announce packet to RLMT multicast address to force + * switches to learn the new location of the logical + * MAC address. + */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } /* (Para.pParaPtr = SkRlmtBuildPacket(...)) != NULL */ + } /* Para.Para32[1] != Active */ + } /* PortFound */ + else { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E004, SKERR_RLMT_E004_MSG); + } + } /* LinksUp > 1 || LinksUp == 1 && RlmtState != SK_RLMT_RS_NET_DOWN */ + return; +} /* SkRlmtCheckSwitch */ + + +/****************************************************************************** + * + * SkRlmtCheckSeg - Report if segmentation is detected + * + * Description: + * This routine checks if the ports see different root bridges and reports + * segmentation in such a case. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtCheckSeg( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 NetIdx) /* Net number */ +{ + SK_EVPARA Para; + SK_RLMT_NET *pNet; + SK_U32 i, j; + SK_BOOL Equal; + + pNet = &pAC->Rlmt.Net[NetIdx]; + pNet->RootIdSet = SK_FALSE; + Equal = SK_TRUE; + + for (i = 0; i < pNet->NumPorts; i++) { + if (pNet->Port[i]->LinkDown || !pNet->Port[i]->RootIdSet) { + continue; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_DUMP, + ("Root ID %d: %02x %02x %02x %02x %02x %02x %02x %02x.\n", i, + pNet->Port[i]->Root.Id[0], pNet->Port[i]->Root.Id[1], + pNet->Port[i]->Root.Id[2], pNet->Port[i]->Root.Id[3], + pNet->Port[i]->Root.Id[4], pNet->Port[i]->Root.Id[5], + pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7])) + + if (!pNet->RootIdSet) { + pNet->Root = pNet->Port[i]->Root; + pNet->RootIdSet = SK_TRUE; + continue; + } + + for (j = 0; j < 8; j ++) { + Equal &= pNet->Port[i]->Root.Id[j] == pNet->Root.Id[j]; + if (!Equal) { + break; + } + } + + if (!Equal) { + SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E005, SKERR_RLMT_E005_MSG); + Para.Para32[0] = NetIdx; + Para.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SEGMENTATION, Para); + + pNet->CheckingState &= ~SK_RLMT_RCS_REPORT_SEG; + + /* 2000-03-06 RA: New. */ + Para.Para32[0] = NetIdx; + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pNet->SegTimer, SK_RLMT_SEG_TO_VAL, + SKGE_RLMT, SK_RLMT_SEG_TIM, Para); + break; + } + } /* for (i = 0; i < pNet->NumPorts; i++) */ + + /* 2000-03-06 RA: Moved here. */ + /* Segmentation check not running anymore. */ + pNet->CheckingState &= ~SK_RLMT_RCS_SEG; + +} /* SkRlmtCheckSeg */ + + +/****************************************************************************** + * + * SkRlmtPortStart - initialize port variables and start port + * + * Description: + * This routine initializes a port's variables and issues a PORT_START + * to the HWAC module. This handles retries if the start fails or the + * link eventually goes down. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtPortStart( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Port number */ +{ + SK_EVPARA Para; + + pAC->Rlmt.Port[PortNumber].PortState = SK_RLMT_PS_LINK_DOWN; + pAC->Rlmt.Port[PortNumber].PortStarted = SK_TRUE; + pAC->Rlmt.Port[PortNumber].LinkDown = SK_TRUE; + pAC->Rlmt.Port[PortNumber].PortDown = SK_TRUE; + pAC->Rlmt.Port[PortNumber].CheckingState = 0; + pAC->Rlmt.Port[PortNumber].RootIdSet = SK_FALSE; + Para.Para32[0] = PortNumber; + Para.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); +} /* SkRlmtPortStart */ + + +/****************************************************************************** + * + * SkRlmtEvtPortStartTim - PORT_START_TIM + * + * Description: + * This routine handles PORT_START_TIM events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPortStartTim( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ +{ + SK_U32 i; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n")) + return; + } + + /* + * Used to start non-preferred ports if the preferred one + * does not come up. + * This timeout needs only be set when starting the first + * (preferred) port. + */ + if (pAC->Rlmt.Port[Para.Para32[0]].LinkDown) { + /* PORT_START failed. */ + for (i = 0; i < pAC->Rlmt.Port[Para.Para32[0]].Net->NumPorts; i++) { + if (!pAC->Rlmt.Port[Para.Para32[0]].Net->Port[i]->PortStarted) { + SkRlmtPortStart(pAC, IoC, + pAC->Rlmt.Port[Para.Para32[0]].Net->Port[i]->PortNumber); + } + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n")) +} /* SkRlmtEvtPortStartTim */ + + +/****************************************************************************** + * + * SkRlmtEvtLinkUp - LINK_UP + * + * Description: + * This routine handles LLINK_UP events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtLinkUp( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 Undefined */ +{ + SK_U32 i; + SK_RLMT_PORT *pRPort; + SK_EVPARA Para2; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0])) + + pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; + if (!pRPort->PortStarted) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E008, SKERR_RLMT_E008_MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_UP Event EMPTY.\n")) + return; + } + + if (!pRPort->LinkDown) { + /* RA;:;: Any better solution? */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_UP Event EMPTY.\n")) + return; + } + + SkTimerStop(pAC, IoC, &pRPort->UpTimer); + SkTimerStop(pAC, IoC, &pRPort->DownRxTimer); + SkTimerStop(pAC, IoC, &pRPort->DownTxTimer); + + /* Do something if timer already fired? */ + + pRPort->LinkDown = SK_FALSE; + pRPort->PortState = SK_RLMT_PS_GOING_UP; + pRPort->GuTimeStamp = SkOsGetTime(pAC); + pRPort->BcTimeStamp = 0; + pRPort->Net->LinksUp++; + if (pRPort->Net->LinksUp == 1) { + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[0], SK_LED_ACTIVE); + } + else { + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[0], SK_LED_STANDBY); + } + + for (i = 0; i < pRPort->Net->NumPorts; i++) { + if (!pRPort->Net->Port[i]->PortStarted) { + SkRlmtPortStart(pAC, IoC, pRPort->Net->Port[i]->PortNumber); + } + } + + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + + if (pRPort->Net->LinksUp >= 2) { + if (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LOC_LINK) { + /* Build the check chain. */ + SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber); + } + } + + /* If the first link comes up, start the periodical RLMT timeout. */ + if (pRPort->Net->NumPorts > 1 && pRPort->Net->LinksUp == 1 && + (pRPort->Net->RlmtMode & SK_RLMT_CHECK_OTHERS) != 0) { + Para2.Para32[0] = pRPort->Net->NetNumber; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->Net->LocTimer, + pRPort->Net->TimeoutValue, SKGE_RLMT, SK_RLMT_TIM, Para2); + } + + Para2 = Para; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->UpTimer, SK_RLMT_PORTUP_TIM_VAL, + SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para2); + + /* Later: if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) && */ + if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 && + (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 && + (Para2.pParaPtr = + SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE, + &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr) + ) != NULL) { + /* Send "new" packet to RLMT multicast address. */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2); + } + + if (pRPort->Net->RlmtMode & SK_RLMT_CHECK_SEG) { + if ((Para2.pParaPtr = + SkRlmtBuildSpanningTreePacket(pAC, IoC, Para.Para32[0])) != NULL) { + pAC->Rlmt.Port[Para.Para32[0]].RootIdSet = SK_FALSE; + pRPort->Net->CheckingState |= + SK_RLMT_RCS_SEG | SK_RLMT_RCS_REPORT_SEG; + + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2); + + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->Net->SegTimer, + SK_RLMT_SEG_TO_VAL, SKGE_RLMT, SK_RLMT_SEG_TIM, Para); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_UP Event END.\n")) +} /* SkRlmtEvtLinkUp */ + + +/****************************************************************************** + * + * SkRlmtEvtPortUpTim - PORT_UP_TIM + * + * Description: + * This routine handles PORT_UP_TIM events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPortUpTim( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ +{ + SK_RLMT_PORT *pRPort; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTUP_TIM Event EMPTY.\n")) + return; + } + + pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; + if (pRPort->LinkDown || (pRPort->PortState == SK_RLMT_PS_UP)) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0])) + return; + } + + pRPort->PortDown = SK_FALSE; + pRPort->PortState = SK_RLMT_PS_UP; + pRPort->Net->PortsUp++; + if (pRPort->Net->RlmtState != SK_RLMT_RS_INIT) { + if (pAC->Rlmt.NumNets <= 1) { + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_PORT_UP, Para); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTUP_TIM Event END.\n")) +} /* SkRlmtEvtPortUpTim */ + + +/****************************************************************************** + * + * SkRlmtEvtPortDownTim - PORT_DOWN_* + * + * Description: + * This routine handles PORT_DOWN_* events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPortDownX( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Event, /* Event code */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ +{ + SK_RLMT_PORT *pRPort; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTDOWN* Port %d Event (%d) BEGIN.\n", + Para.Para32[0], Event)) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTDOWN* Event EMPTY.\n")) + return; + } + + pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; + if (!pRPort->PortStarted || (Event == SK_RLMT_PORTDOWN_TX_TIM && + !(pRPort->CheckingState & SK_RLMT_PCS_TX))) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event)) + return; + } + + /* Stop port's timers. */ + SkTimerStop(pAC, IoC, &pRPort->UpTimer); + SkTimerStop(pAC, IoC, &pRPort->DownRxTimer); + SkTimerStop(pAC, IoC, &pRPort->DownTxTimer); + + if (pRPort->PortState != SK_RLMT_PS_LINK_DOWN) { + pRPort->PortState = SK_RLMT_PS_DOWN; + } + + if (!pRPort->PortDown) { + pRPort->Net->PortsUp--; + pRPort->PortDown = SK_TRUE; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_PORT_DOWN, Para); + } + + pRPort->PacketsPerTimeSlot = 0; + /* pRPort->DataPacketsPerTimeSlot = 0; */ + pRPort->BpduPacketsPerTimeSlot = 0; + pRPort->BcTimeStamp = 0; + + /* + * RA;:;: To be checked: + * - actions at RLMT_STOP: We should not switch anymore. + */ + if (pRPort->Net->RlmtState != SK_RLMT_RS_INIT) { + if (Para.Para32[0] == + pRPort->Net->Port[pRPort->Net->ActivePort]->PortNumber) { + /* Active Port went down. */ + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event)) +} /* SkRlmtEvtPortDownX */ + + +/****************************************************************************** + * + * SkRlmtEvtLinkDown - LINK_DOWN + * + * Description: + * This routine handles LINK_DOWN events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtLinkDown( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 Undefined */ +{ + SK_RLMT_PORT *pRPort; + + pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0])) + + if (!pAC->Rlmt.Port[Para.Para32[0]].LinkDown) { + pRPort->Net->LinksUp--; + pRPort->LinkDown = SK_TRUE; + pRPort->PortState = SK_RLMT_PS_LINK_DOWN; + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[0], SK_LED_OFF); + + if ((pRPort->Net->RlmtMode & SK_RLMT_CHECK_LOC_LINK) != 0) { + /* Build the check chain. */ + SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber); + } + + /* Ensure that port is marked down. */ + Para.Para32[1] = -1; + (void)SkRlmtEvent(pAC, IoC, SK_RLMT_PORTDOWN, Para); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_DOWN Event END.\n")) +} /* SkRlmtEvtLinkDown */ + + +/****************************************************************************** + * + * SkRlmtEvtPortAddr - PORT_ADDR + * + * Description: + * This routine handles PORT_ADDR events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPortAddr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ +{ + SK_U32 i, j; + SK_RLMT_PORT *pRPort; + SK_MAC_ADDR *pOldMacAddr; + SK_MAC_ADDR *pNewMacAddr; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORT_ADDR Event EMPTY.\n")) + return; + } + + /* Port's physical MAC address changed. */ + pOldMacAddr = &pAC->Addr.Port[Para.Para32[0]].PreviousMacAddress; + pNewMacAddr = &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress; + + /* + * NOTE: This is not scalable for solutions where ports are + * checked remotely. There, we need to send an RLMT + * address change packet - and how do we ensure delivery? + */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + pRPort = &pAC->Rlmt.Port[i]; + for (j = 0; j < pRPort->PortsChecked; j++) { + if (SK_ADDR_EQUAL( + pRPort->PortCheck[j].CheckAddr.a, pOldMacAddr->a)) { + pRPort->PortCheck[j].CheckAddr = *pNewMacAddr; + } + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORT_ADDR Event END.\n")) +} /* SkRlmtEvtPortAddr */ + + +/****************************************************************************** + * + * SkRlmtEvtStart - START + * + * Description: + * This routine handles START events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtStart( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_EVPARA Para2; + SK_U32 PortIdx; + SK_U32 PortNumber; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState != SK_RLMT_RS_INIT) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.NetsStarted >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("All nets should have been started.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.Net[Para.Para32[0]].PrefPort >= + pAC->Rlmt.Net[Para.Para32[0]].NumPorts) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E009, SKERR_RLMT_E009_MSG); + + /* Change PrefPort to internal default. */ + Para2.Para32[0] = 0xFFFFFFFF; + Para2.Para32[1] = Para.Para32[0]; + (void)SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE, Para2); + } + + PortIdx = pAC->Rlmt.Net[Para.Para32[0]].PrefPort; + PortNumber = pAC->Rlmt.Net[Para.Para32[0]].Port[PortIdx]->PortNumber; + + pAC->Rlmt.Net[Para.Para32[0]].LinksUp = 0; + pAC->Rlmt.Net[Para.Para32[0]].PortsUp = 0; + pAC->Rlmt.Net[Para.Para32[0]].CheckingState = 0; + pAC->Rlmt.Net[Para.Para32[0]].RlmtState = SK_RLMT_RS_NET_DOWN; + + /* Start preferred port. */ + SkRlmtPortStart(pAC, IoC, PortNumber); + + /* Start Timer (for first port only). */ + Para2.Para32[0] = PortNumber; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pAC->Rlmt.Port[PortNumber].UpTimer, + SK_RLMT_PORTSTART_TIM_VAL, SKGE_RLMT, SK_RLMT_PORTSTART_TIM, Para2); + + pAC->Rlmt.NetsStarted++; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event END.\n")) +} /* SkRlmtEvtStart */ + + +/****************************************************************************** + * + * SkRlmtEvtStop - STOP + * + * Description: + * This routine handles STOP events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtStop( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_EVPARA Para2; + SK_U32 PortNumber; + SK_U32 i; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState == SK_RLMT_RS_INIT) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.NetsStarted == 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("All nets are stopped.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event EMPTY.\n")) + return; + } + + /* Stop RLMT timers. */ + SkTimerStop(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[0]].LocTimer); + SkTimerStop(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[0]].SegTimer); + + /* Stop net. */ + pAC->Rlmt.Net[Para.Para32[0]].RlmtState = SK_RLMT_RS_INIT; + pAC->Rlmt.Net[Para.Para32[0]].RootIdSet = SK_FALSE; + Para2.Para32[0] = SK_RLMT_NET_DOWN_FINAL; + Para2.Para32[1] = Para.Para32[0]; /* Net# */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_DOWN, Para2); + + /* Stop ports. */ + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; i++) { + PortNumber = pAC->Rlmt.Net[Para.Para32[0]].Port[i]->PortNumber; + if (pAC->Rlmt.Port[PortNumber].PortState != SK_RLMT_PS_INIT) { + SkTimerStop(pAC, IoC, &pAC->Rlmt.Port[PortNumber].UpTimer); + SkTimerStop(pAC, IoC, &pAC->Rlmt.Port[PortNumber].DownRxTimer); + SkTimerStop(pAC, IoC, &pAC->Rlmt.Port[PortNumber].DownTxTimer); + + pAC->Rlmt.Port[PortNumber].PortState = SK_RLMT_PS_INIT; + pAC->Rlmt.Port[PortNumber].RootIdSet = SK_FALSE; + pAC->Rlmt.Port[PortNumber].PortStarted = SK_FALSE; + Para2.Para32[0] = PortNumber; + Para2.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para2); + } + } + + pAC->Rlmt.NetsStarted--; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event END.\n")) +} /* SkRlmtEvtStop */ + + +/****************************************************************************** + * + * SkRlmtEvtTim - TIM + * + * Description: + * This routine handles TIM events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtTim( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_RLMT_PORT *pRPort; + SK_U32 Timeout; + SK_U32 NewTimeout; + SK_U32 PortNumber; + SK_U32 i; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_TIM Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_TIM Event EMPTY.\n")) + return; + } + + if ((pAC->Rlmt.Net[Para.Para32[0]].RlmtMode & SK_RLMT_CHECK_OTHERS) == 0 || + pAC->Rlmt.Net[Para.Para32[0]].LinksUp == 0) { + /* Mode changed or all links down: No more link checking. */ + return; + } + +#if 0 + pAC->Rlmt.SwitchCheckCounter--; + if (pAC->Rlmt.SwitchCheckCounter == 0) { + pAC->Rlmt.SwitchCheckCounter; + } +#endif /* 0 */ + + NewTimeout = SK_RLMT_DEF_TO_VAL; + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; i++) { + PortNumber = pAC->Rlmt.Net[Para.Para32[0]].Port[i]->PortNumber; + pRPort = &pAC->Rlmt.Port[PortNumber]; + if (!pRPort->LinkDown) { + Timeout = SkRlmtCheckPort(pAC, IoC, PortNumber); + if (Timeout < NewTimeout) { + NewTimeout = Timeout; + } + + /* + * These counters should be set to 0 for all ports before the + * first frame is sent in the next loop. + */ + pRPort->PacketsPerTimeSlot = 0; + /* pRPort->DataPacketsPerTimeSlot = 0; */ + pRPort->BpduPacketsPerTimeSlot = 0; + } + } + pAC->Rlmt.Net[Para.Para32[0]].TimeoutValue = NewTimeout; + + if (pAC->Rlmt.Net[Para.Para32[0]].LinksUp > 1) { + /* + * If checking remote ports, also send packets if + * (LinksUp == 1) && + * this port checks at least one (remote) port. + */ + + /* + * Must be new loop, as SkRlmtCheckPort can request to + * check segmentation when e.g. checking the last port. + */ + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; i++) { + if (!pAC->Rlmt.Net[Para.Para32[0]].Port[i]->LinkDown) { + SkRlmtSend(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[0]].Port[i]->PortNumber); + } + } + } + + SkTimerStart(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[0]].LocTimer, + pAC->Rlmt.Net[Para.Para32[0]].TimeoutValue, SKGE_RLMT, SK_RLMT_TIM, + Para); + + if (pAC->Rlmt.Net[Para.Para32[0]].LinksUp > 1 && + (pAC->Rlmt.Net[Para.Para32[0]].RlmtMode & SK_RLMT_CHECK_SEG) && + (pAC->Rlmt.Net[Para.Para32[0]].CheckingState & SK_RLMT_RCS_START_SEG)) { + SkTimerStart(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[0]].SegTimer, + SK_RLMT_SEG_TO_VAL, SKGE_RLMT, SK_RLMT_SEG_TIM, Para); + pAC->Rlmt.Net[Para.Para32[0]].CheckingState &= ~SK_RLMT_RCS_START_SEG; + pAC->Rlmt.Net[Para.Para32[0]].CheckingState |= + SK_RLMT_RCS_SEG | SK_RLMT_RCS_REPORT_SEG; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_TIM Event END.\n")) +} /* SkRlmtEvtTim */ + + +/****************************************************************************** + * + * SkRlmtEvtSegTim - SEG_TIM + * + * Description: + * This routine handles SEG_TIM events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtSegTim( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ +#ifdef xDEBUG + int j; +#endif /* DEBUG */ + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SEG_TIM Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SEG_TIM Event EMPTY.\n")) + return; + } + +#ifdef xDEBUG + for (j = 0; j < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; j++) { + SK_ADDR_PORT *pAPort; + SK_U32 k; + SK_U16 *InAddr; + SK_U8 InAddr8[6]; + + InAddr = (SK_U16 *)&InAddr8[0]; + pAPort = pAC->Rlmt.Net[Para.Para32[0]].Port[j]->AddrPort; + for (k = 0; k < pAPort->NextExactMatchRlmt; k++) { + /* Get exact match address k from port j. */ + XM_INADDR(IoC, pAC->Rlmt.Net[Para.Para32[0]].Port[j]->PortNumber, + XM_EXM(k), InAddr); + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("MC address %d on Port %u: %02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x.\n", + k, pAC->Rlmt.Net[Para.Para32[0]].Port[j]->PortNumber, + InAddr8[0], InAddr8[1], InAddr8[2], + InAddr8[3], InAddr8[4], InAddr8[5], + pAPort->Exact[k].a[0], pAPort->Exact[k].a[1], + pAPort->Exact[k].a[2], pAPort->Exact[k].a[3], + pAPort->Exact[k].a[4], pAPort->Exact[k].a[5])) + } + } +#endif /* xDEBUG */ + + SkRlmtCheckSeg(pAC, IoC, Para.Para32[0]); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SEG_TIM Event END.\n")) +} /* SkRlmtEvtSegTim */ + + +/****************************************************************************** + * + * SkRlmtEvtPacketRx - PACKET_RECEIVED + * + * Description: + * This routine handles PACKET_RECEIVED events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPacketRx( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_MBUF *pMb */ +{ + SK_MBUF *pMb; + SK_MBUF *pNextMb; + SK_U32 NetNumber; + + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n")) + + /* Should we ignore frames during port switching? */ + +#ifdef DEBUG + pMb = Para.pParaPtr; + if (pMb == NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n")) + } + else if (pMb->pNext != NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("More than one mbuf or pMb->pNext not set.\n")) + } +#endif /* DEBUG */ + + for (pMb = Para.pParaPtr; pMb != NULL; pMb = pNextMb) { + pNextMb = pMb->pNext; + pMb->pNext = NULL; + + NetNumber = pAC->Rlmt.Port[pMb->PortIdx].Net->NetNumber; + if (pAC->Rlmt.Net[NetNumber].RlmtState == SK_RLMT_RS_INIT) { + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + } + else { + SkRlmtPacketReceive(pAC, IoC, pMb); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PACKET_RECEIVED Event END.\n")) +} /* SkRlmtEvtPacketRx */ + + +/****************************************************************************** + * + * SkRlmtEvtStatsClear - STATS_CLEAR + * + * Description: + * This routine handles STATS_CLEAR events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtStatsClear( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_U32 i; + SK_RLMT_PORT *pRPort; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_CLEAR Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_CLEAR Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_CLEAR Event EMPTY.\n")) + return; + } + + /* Clear statistics for logical and physical ports. */ + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; i++) { + pRPort = + &pAC->Rlmt.Port[pAC->Rlmt.Net[Para.Para32[0]].Port[i]->PortNumber]; + pRPort->TxHelloCts = 0; + pRPort->RxHelloCts = 0; + pRPort->TxSpHelloReqCts = 0; + pRPort->RxSpHelloCts = 0; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_CLEAR Event END.\n")) +} /* SkRlmtEvtStatsClear */ + + +/****************************************************************************** + * + * SkRlmtEvtStatsUpdate - STATS_UPDATE + * + * Description: + * This routine handles STATS_UPDATE events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtStatsUpdate( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_UPDATE Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_UPDATE Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_UPDATE Event EMPTY.\n")) + return; + } + + /* Update statistics - currently always up-to-date. */ + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_UPDATE Event END.\n")) +} /* SkRlmtEvtStatsUpdate */ + + +/****************************************************************************** + * + * SkRlmtEvtPrefportChange - PREFPORT_CHANGE + * + * Description: + * This routine handles PREFPORT_CHANGE events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPrefportChange( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortIndex; SK_U32 NetNumber */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[1])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n")) + return; + } + + /* 0xFFFFFFFF == auto-mode. */ + if (Para.Para32[0] == 0xFFFFFFFF) { + pAC->Rlmt.Net[Para.Para32[1]].PrefPort = SK_RLMT_DEF_PREF_PORT; + } + else { + if (Para.Para32[0] >= pAC->Rlmt.Net[Para.Para32[1]].NumPorts) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E010, SKERR_RLMT_E010_MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n")) + return; + } + + pAC->Rlmt.Net[Para.Para32[1]].PrefPort = Para.Para32[0]; + } + + pAC->Rlmt.Net[Para.Para32[1]].Preference = Para.Para32[0]; + + if (pAC->Rlmt.Net[Para.Para32[1]].RlmtState != SK_RLMT_RS_INIT) { + SkRlmtCheckSwitch(pAC, IoC, Para.Para32[1]); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PREFPORT_CHANGE Event END.\n")) +} /* SkRlmtEvtPrefportChange */ + + +/****************************************************************************** + * + * SkRlmtEvtSetNets - SET_NETS + * + * Description: + * This routine handles SET_NETS events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtSetNets( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NumNets; SK_U32 -1 */ +{ + int i; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] == 0 || Para.Para32[0] > SK_MAX_NETS || + Para.Para32[0] > (SK_U32)pAC->GIni.GIMacsFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad number of nets: %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] == pAC->Rlmt.NumNets) { /* No change. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + /* Entering and leaving dual mode only allowed while nets are stopped. */ + if (pAC->Rlmt.NetsStarted > 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Changing dual mode only allowed while all nets are stopped.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] == 1) { + if (pAC->Rlmt.NumNets > 1) { + /* Clear logical MAC addr from second net's active port. */ + (void)SkAddrOverride(pAC, IoC, pAC->Rlmt.Net[1].Port[pAC->Addr. + Net[1].ActivePort]->PortNumber, NULL, SK_ADDR_CLEAR_LOGICAL); + pAC->Rlmt.Net[1].NumPorts = 0; + } + + pAC->Rlmt.NumNets = Para.Para32[0]; + for (i = 0; (SK_U32)i < pAC->Rlmt.NumNets; i++) { + pAC->Rlmt.Net[i].RlmtState = SK_RLMT_RS_INIT; + pAC->Rlmt.Net[i].RootIdSet = SK_FALSE; + pAC->Rlmt.Net[i].Preference = 0xFFFFFFFF; /* "Automatic" */ + pAC->Rlmt.Net[i].PrefPort = SK_RLMT_DEF_PREF_PORT; + /* Just assuming. */ + pAC->Rlmt.Net[i].ActivePort = pAC->Rlmt.Net[i].PrefPort; + pAC->Rlmt.Net[i].RlmtMode = SK_RLMT_DEF_MODE; + pAC->Rlmt.Net[i].TimeoutValue = SK_RLMT_DEF_TO_VAL; + pAC->Rlmt.Net[i].NetNumber = i; + } + + pAC->Rlmt.Port[1].Net= &pAC->Rlmt.Net[0]; + pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound; + + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("RLMT: Changed to one net with two ports.\n")) + } + else if (Para.Para32[0] == 2) { + pAC->Rlmt.Port[1].Net= &pAC->Rlmt.Net[1]; + pAC->Rlmt.Net[1].NumPorts = pAC->GIni.GIMacsFound - 1; + pAC->Rlmt.Net[0].NumPorts = + pAC->GIni.GIMacsFound - pAC->Rlmt.Net[1].NumPorts; + + pAC->Rlmt.NumNets = Para.Para32[0]; + for (i = 0; (SK_U32)i < pAC->Rlmt.NumNets; i++) { + pAC->Rlmt.Net[i].RlmtState = SK_RLMT_RS_INIT; + pAC->Rlmt.Net[i].RootIdSet = SK_FALSE; + pAC->Rlmt.Net[i].Preference = 0xFFFFFFFF; /* "Automatic" */ + pAC->Rlmt.Net[i].PrefPort = SK_RLMT_DEF_PREF_PORT; + /* Just assuming. */ + pAC->Rlmt.Net[i].ActivePort = pAC->Rlmt.Net[i].PrefPort; + pAC->Rlmt.Net[i].RlmtMode = SK_RLMT_DEF_MODE; + pAC->Rlmt.Net[i].TimeoutValue = SK_RLMT_DEF_TO_VAL; + + pAC->Rlmt.Net[i].NetNumber = i; + } + + /* Set logical MAC addr on second net's active port. */ + (void)SkAddrOverride(pAC, IoC, pAC->Rlmt.Net[1].Port[pAC->Addr. + Net[1].ActivePort]->PortNumber, NULL, SK_ADDR_SET_LOGICAL); + + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("RLMT: Changed to two nets with one port each.\n")) + } + else { + /* Not implemented for more than two nets. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SetNets not implemented for more than two nets.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event END.\n")) +} /* SkRlmtSetNets */ + + +/****************************************************************************** + * + * SkRlmtEvtModeChange - MODE_CHANGE + * + * Description: + * This routine handles MODE_CHANGE events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtModeChange( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NewMode; SK_U32 NetNumber */ +{ + SK_EVPARA Para2; + SK_U32 i; + SK_U32 PrevRlmtMode; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_MODE_CHANGE Event BEGIN.\n")) + + if (Para.Para32[1] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[1])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_MODE_CHANGE Event EMPTY.\n")) + return; + } + + Para.Para32[0] |= SK_RLMT_CHECK_LINK; + + if ((pAC->Rlmt.Net[Para.Para32[1]].NumPorts == 1) && + Para.Para32[0] != SK_RLMT_MODE_CLS) { + pAC->Rlmt.Net[Para.Para32[1]].RlmtMode = SK_RLMT_MODE_CLS; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Forced RLMT mode to CLS on single port net.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_MODE_CHANGE Event EMPTY.\n")) + return; + } + + /* Update RLMT mode. */ + PrevRlmtMode = pAC->Rlmt.Net[Para.Para32[1]].RlmtMode; + pAC->Rlmt.Net[Para.Para32[1]].RlmtMode = Para.Para32[0]; + + if ((PrevRlmtMode & SK_RLMT_CHECK_LOC_LINK) != + (pAC->Rlmt.Net[Para.Para32[1]].RlmtMode & SK_RLMT_CHECK_LOC_LINK)) { + /* SK_RLMT_CHECK_LOC_LINK bit changed. */ + if ((PrevRlmtMode & SK_RLMT_CHECK_OTHERS) == 0 && + pAC->Rlmt.Net[Para.Para32[1]].NumPorts > 1 && + pAC->Rlmt.Net[Para.Para32[1]].PortsUp >= 1) { + /* 20001207 RA: Was "PortsUp == 1". */ + Para2.Para32[0] = Para.Para32[1]; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[1]].LocTimer, + pAC->Rlmt.Net[Para.Para32[1]].TimeoutValue, + SKGE_RLMT, SK_RLMT_TIM, Para2); + } + } + + if ((PrevRlmtMode & SK_RLMT_CHECK_SEG) != + (pAC->Rlmt.Net[Para.Para32[1]].RlmtMode & SK_RLMT_CHECK_SEG)) { + /* SK_RLMT_CHECK_SEG bit changed. */ + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[1]].NumPorts; i++) { + (void)SkAddrMcClear(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->PortNumber, + SK_ADDR_PERMANENT | SK_MC_SW_ONLY); + + /* Add RLMT MC address. */ + (void)SkAddrMcAdd(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->PortNumber, + &SkRlmtMcAddr, SK_ADDR_PERMANENT); + + if ((pAC->Rlmt.Net[Para.Para32[1]].RlmtMode & + SK_RLMT_CHECK_SEG) != 0) { + /* Add BPDU MC address. */ + (void)SkAddrMcAdd(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->PortNumber, + &BridgeMcAddr, SK_ADDR_PERMANENT); + + if (pAC->Rlmt.Net[Para.Para32[1]].RlmtState != SK_RLMT_RS_INIT) { + if (!pAC->Rlmt.Net[Para.Para32[1]].Port[i]->LinkDown && + (Para2.pParaPtr = SkRlmtBuildSpanningTreePacket( + pAC, IoC, i)) != NULL) { + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->RootIdSet = + SK_FALSE; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2); + } + } + } + (void)SkAddrMcUpdate(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->PortNumber); + } /* for ... */ + + if ((pAC->Rlmt.Net[Para.Para32[1]].RlmtMode & SK_RLMT_CHECK_SEG) != 0) { + Para2.Para32[0] = Para.Para32[1]; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[1]].SegTimer, + SK_RLMT_SEG_TO_VAL, SKGE_RLMT, SK_RLMT_SEG_TIM, Para2); + } + } /* SK_RLMT_CHECK_SEG bit changed. */ + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_MODE_CHANGE Event END.\n")) +} /* SkRlmtEvtModeChange */ + + +/****************************************************************************** + * + * SkRlmtEvent - a PORT- or an RLMT-specific event happened + * + * Description: + * This routine calls subroutines to handle PORT- and RLMT-specific events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * 0 + */ +int SkRlmtEvent( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Event, /* Event code */ +SK_EVPARA Para) /* Event-specific parameter */ +{ + switch (Event) { + + /* ----- PORT events ----- */ + + case SK_RLMT_PORTSTART_TIM: /* From RLMT via TIME. */ + SkRlmtEvtPortStartTim(pAC, IoC, Para); + break; + case SK_RLMT_LINK_UP: /* From SIRQ. */ + SkRlmtEvtLinkUp(pAC, IoC, Para); + break; + case SK_RLMT_PORTUP_TIM: /* From RLMT via TIME. */ + SkRlmtEvtPortUpTim(pAC, IoC, Para); + break; + case SK_RLMT_PORTDOWN: /* From RLMT. */ + case SK_RLMT_PORTDOWN_RX_TIM: /* From RLMT via TIME. */ + case SK_RLMT_PORTDOWN_TX_TIM: /* From RLMT via TIME. */ + SkRlmtEvtPortDownX(pAC, IoC, Event, Para); + break; + case SK_RLMT_LINK_DOWN: /* From SIRQ. */ + SkRlmtEvtLinkDown(pAC, IoC, Para); + break; + case SK_RLMT_PORT_ADDR: /* From ADDR. */ + SkRlmtEvtPortAddr(pAC, IoC, Para); + break; + + /* ----- RLMT events ----- */ + + case SK_RLMT_START: /* From DRV. */ + SkRlmtEvtStart(pAC, IoC, Para); + break; + case SK_RLMT_STOP: /* From DRV. */ + SkRlmtEvtStop(pAC, IoC, Para); + break; + case SK_RLMT_TIM: /* From RLMT via TIME. */ + SkRlmtEvtTim(pAC, IoC, Para); + break; + case SK_RLMT_SEG_TIM: + SkRlmtEvtSegTim(pAC, IoC, Para); + break; + case SK_RLMT_PACKET_RECEIVED: /* From DRV. */ + SkRlmtEvtPacketRx(pAC, IoC, Para); + break; + case SK_RLMT_STATS_CLEAR: /* From PNMI. */ + SkRlmtEvtStatsClear(pAC, IoC, Para); + break; + case SK_RLMT_STATS_UPDATE: /* From PNMI. */ + SkRlmtEvtStatsUpdate(pAC, IoC, Para); + break; + case SK_RLMT_PREFPORT_CHANGE: /* From PNMI. */ + SkRlmtEvtPrefportChange(pAC, IoC, Para); + break; + case SK_RLMT_MODE_CHANGE: /* From PNMI. */ + SkRlmtEvtModeChange(pAC, IoC, Para); + break; + case SK_RLMT_SET_NETS: /* From DRV. */ + SkRlmtEvtSetNets(pAC, IoC, Para); + break; + + /* ----- Unknown events ----- */ + + default: /* Create error log entry. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Unknown RLMT Event %d.\n", Event)) + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E003, SKERR_RLMT_E003_MSG); + break; + } /* switch() */ + + return (0); +} /* SkRlmtEvent */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/sktimer.c b/drivers/sk98lin/sktimer.c new file mode 100644 index 0000000..37cd4c9 --- /dev/null +++ b/drivers/sk98lin/sktimer.c @@ -0,0 +1,297 @@ +/****************************************************************************** + * + * Name: sktimer.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.12 $ + * Date: $Date: 1999/11/22 13:38:51 $ + * Purpose: High level timer functions. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: sktimer.c,v $ + * Revision 1.12 1999/11/22 13:38:51 cgoos + * Changed license header to GPL. + * + * Revision 1.11 1998/12/17 13:24:13 gklug + * fix: restart problem: do NOT destroy timer queue if init 1 is done + * + * Revision 1.10 1998/10/15 15:11:36 gklug + * fix: ID_sccs to SysKonnectFileId + * + * Revision 1.9 1998/09/15 15:15:04 cgoos + * Changed TRUE/FALSE to SK_TRUE/SK_FALSE + * + * Revision 1.8 1998/09/08 08:47:55 gklug + * add: init level handling + * + * Revision 1.7 1998/08/19 09:50:53 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.6 1998/08/17 13:43:13 gklug + * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR + * + * Revision 1.5 1998/08/14 07:09:14 gklug + * fix: chg pAc -> pAC + * + * Revision 1.4 1998/08/07 12:53:46 gklug + * fix: first compiled version + * + * Revision 1.3 1998/08/07 09:31:53 gklug + * fix: delta spelling + * + * Revision 1.2 1998/08/07 09:31:02 gklug + * adapt functions to new c coding conventions + * rmv: "fast" handling + * chg: inserting of new timer in queue. + * chg: event queue generation when timer runs out + * + * Revision 1.1 1998/08/05 11:27:55 gklug + * first version: adapted from SMT + * + * + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + Event queue and dispatcher +*/ +static const char SysKonnectFileId[] = + "$Header: /usr56/projects/ge/schedule/sktimer.c,v 1.12 1999/11/22 13:38:51 cgoos Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef __C2MAN__ +/* + Event queue management. + + General Description: + + */ +intro() +{} +#endif + + +/* Forward declaration */ +static void timer_done(SK_AC *pAC,SK_IOC Ioc,int Restart); + + +/* + * Inits the software timer + * + * needs to be called during Init level 1. + */ +void SkTimerInit( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +int Level) /* Init Level */ +{ + switch (Level) { + case SK_INIT_DATA: + pAC->Tim.StQueue = 0 ; + break; + case SK_INIT_IO: + SkHwtInit(pAC,Ioc) ; + SkTimerDone(pAC, Ioc); + break; + default: + break; + } +} + +/* + * Stops a high level timer + * - If a timer is not in the queue the function returns normally, too. + */ +void SkTimerStop( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +SK_TIMER *pTimer) /* Timer Pointer to be started */ +{ + SK_TIMER **ppTimPrev ; + SK_TIMER *pTm ; + + /* + * remove timer from queue + */ + pTimer->TmActive = SK_FALSE ; + if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) { + SkHwtStop(pAC,Ioc) ; + } + for (ppTimPrev = &pAC->Tim.StQueue ; (pTm = *ppTimPrev) ; + ppTimPrev = &pTm->TmNext ) { + if (pTm == pTimer) { + /* + * Timer found in queue + * - dequeue it and + * - correct delta of the next timer + */ + *ppTimPrev = pTm->TmNext ; + + if (pTm->TmNext) { + /* correct delta of next timer in queue */ + pTm->TmNext->TmDelta += pTm->TmDelta ; + } + return ; + } + } +} + +/* + * Start a high level software timer + */ +void SkTimerStart( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +SK_TIMER *pTimer, /* Timer Pointer to be started */ +SK_U32 Time, /* Time value */ +SK_U32 Class, /* Event Class for this timer */ +SK_U32 Event, /* Event Value for this timer */ +SK_EVPARA Para) /* Event Parameter for this timer */ +{ + SK_TIMER **ppTimPrev ; + SK_TIMER *pTm ; + SK_U32 Delta ; + + Time /= 16 ; /* input is uS, clock ticks are 16uS */ + if (!Time) + Time = 1 ; + + SkTimerStop(pAC,Ioc,pTimer) ; + + pTimer->TmClass = Class ; + pTimer->TmEvent = Event ; + pTimer->TmPara = Para ; + pTimer->TmActive = SK_TRUE ; + + if (!pAC->Tim.StQueue) { + /* First Timer to be started */ + pAC->Tim.StQueue = pTimer ; + pTimer->TmNext = 0 ; + pTimer->TmDelta = Time ; + SkHwtStart(pAC,Ioc,Time) ; + return ; + } + + /* + * timer correction + */ + timer_done(pAC,Ioc,0) ; + + /* + * find position in queue + */ + Delta = 0 ; + for (ppTimPrev = &pAC->Tim.StQueue ; (pTm = *ppTimPrev) ; + ppTimPrev = &pTm->TmNext ) { + if (Delta + pTm->TmDelta > Time) { + /* Position found */ + /* Here the timer needs to be inserted. */ + break ; + } + Delta += pTm->TmDelta ; + } + + /* insert in queue */ + *ppTimPrev = pTimer ; + pTimer->TmNext = pTm ; + pTimer->TmDelta = Time - Delta ; + + if (pTm) { + /* There is a next timer + * -> correct its Delta value. + */ + pTm->TmDelta -= pTimer->TmDelta ; + } + + /* + * start new with first + */ + SkHwtStart(pAC,Ioc,pAC->Tim.StQueue->TmDelta) ; +} + + +void SkTimerDone( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + timer_done(pAC,Ioc,1) ; +} + + +static void timer_done( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +int Restart) /* Do we need to restart the Hardware timer ? */ +{ + SK_U32 Delta ; + SK_TIMER *pTm ; + SK_TIMER *pTComp ; /* Timer completed now now */ + SK_TIMER **ppLast ; /* Next field of Last timer to be deq */ + int Done = 0 ; + + Delta = SkHwtRead(pAC,Ioc) ; + ppLast = &pAC->Tim.StQueue ; + pTm = pAC->Tim.StQueue ; + while (pTm && !Done) { + if (Delta >= pTm->TmDelta) { + /* Timer ran out */ + pTm->TmActive = SK_FALSE ; + Delta -= pTm->TmDelta ; + ppLast = &pTm->TmNext ; + pTm = pTm->TmNext ; + } else { + /* We found the first timer that did not run out */ + pTm->TmDelta -= Delta ; + Delta = 0 ; + Done = 1 ; + } + } + *ppLast = 0 ; + /* + * pTm points to the first Timer that did not run out. + * StQueue points to the first Timer that run out. + */ + + for ( pTComp = pAC->Tim.StQueue ; pTComp ; pTComp = pTComp->TmNext) { + SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, + pTComp->TmPara) ; + } + + /* Set head of timer queue to the first timer that did not run out */ + pAC->Tim.StQueue = pTm ; + + if (Restart && pAC->Tim.StQueue) { + /* Restart HW timer */ + SkHwtStart(pAC,Ioc,pAC->Tim.StQueue->TmDelta) ; + } +} + +#endif /* CONFIG_SK98 */ + +/* End of file */ diff --git a/drivers/sk98lin/skvpd.c b/drivers/sk98lin/skvpd.c new file mode 100644 index 0000000..3b81e67 --- /dev/null +++ b/drivers/sk98lin/skvpd.c @@ -0,0 +1,1329 @@ +/****************************************************************************** + * + * Name: skvpd.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.37 $ + * Date: $Date: 2003/01/13 10:42:45 $ + * Purpose: Shared software to read and write VPD data + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skvpd.c,v $ + * Revision 1.37 2003/01/13 10:42:45 rschmidt + * Replaced check for PCI device Id from YUKON with GENESIS + * to set the VPD size in VpdInit() + * Editorial changes + * + * Revision 1.36 2002/11/14 15:16:56 gheinig + * Added const specifier to key and buf parameters for VpdPara, VpdRead + * and VpdWrite for Diag 7 GUI + * + * Revision 1.35 2002/10/21 14:31:59 gheinig + * Took out CVS web garbage at head of file + * + * Revision 1.34 2002/10/21 11:47:24 gheinig + * Reverted to version 1.32 due to unwanted commit + * + * Revision 1.32 2002/10/14 16:04:29 rschmidt + * Added saving of VPD ROM Size from PCI_OUR_REG_2 + * Avoid reading of PCI_OUR_REG_2 in VpdTransferBlock() + * Editorial changes + * + * Revision 1.31 2002/09/10 09:21:32 mkarl + * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis + * + * Revision 1.30 2002/09/09 14:43:03 mkarl + * changes for diagnostics in order to read VPD data before the adapter + * has been initialized + * editorial changes + * + * Revision 1.29 2002/07/26 13:20:43 mkarl + * added Yukon support + * save size of VPD in pAC->vpd.vpd_size + * + * Revision 1.28 2002/04/02 15:31:47 afischer + * Bug fix in VpdWait() + * + * Revision 1.27 2000/08/10 11:29:06 rassmann + * Editorial changes. + * Preserving 32-bit alignment in structs for the adapter context. + * Removed unused function VpdWriteDword() (#if 0). + * Made VpdReadKeyword() available for SKDIAG only. + * + * Revision 1.26 2000/06/13 08:00:01 mkarl + * additional cast to avoid compile problems in 64 bit environment + * + * Revision 1.25 1999/11/22 13:39:32 cgoos + * Changed license header to GPL. + * + * Revision 1.24 1999/03/11 14:25:49 malthoff + * Replace __STDC__ with SK_KR_PROTO. + * + * Revision 1.23 1999/01/11 15:13:11 gklug + * fix: syntax error + * + * Revision 1.22 1998/10/30 06:41:15 gklug + * rmv: WARNING + * + * Revision 1.21 1998/10/29 07:15:14 gklug + * fix: Write Stream function needs verify. + * + * Revision 1.20 1998/10/28 18:05:08 gklug + * chg: no DEBUG in VpdMayWrite + * + * Revision 1.19 1998/10/28 15:56:11 gklug + * fix: Return len at end of ReadStream + * fix: Write even less than 4 bytes correctly + * + * Revision 1.18 1998/10/28 09:00:47 gklug + * fix: unreferenced local vars + * + * Revision 1.17 1998/10/28 08:25:45 gklug + * fix: WARNING + * + * Revision 1.16 1998/10/28 08:17:30 gklug + * fix: typo + * + * Revision 1.15 1998/10/28 07:50:32 gklug + * fix: typo + * + * Revision 1.14 1998/10/28 07:20:38 gklug + * chg: Interface functions to use IoC as parameter as well + * fix: VpdRead/WriteDWord now returns SK_U32 + * chg: VPD_IN/OUT names conform to SK_IN/OUT + * add: usage of VPD_IN/OUT8 macros + * add: VpdRead/Write Stream functions to r/w a stream of data + * fix: VpdTransferBlock swapped illegal + * add: VpdMayWrite + * + * Revision 1.13 1998/10/22 10:02:37 gklug + * fix: SysKonnectFileId typo + * + * Revision 1.12 1998/10/20 10:01:01 gklug + * fix: parameter to SkOsGetTime + * + * Revision 1.11 1998/10/15 12:51:48 malthoff + * Remove unrequired parameter p in vpd_setup_para(). + * + * Revision 1.10 1998/10/08 14:52:43 malthoff + * Remove CvsId by SysKonnectFileId. + * + * Revision 1.9 1998/09/16 07:33:52 malthoff + * replace memcmp() by SK_MEMCMP and + * memcpy() by SK_MEMCPY() to be + * independent from the 'C' Standard Library. + * + * Revision 1.8 1998/08/19 12:52:35 malthoff + * compiler fix: use SK_VPD_KEY instead of S_VPD. + * + * Revision 1.7 1998/08/19 08:14:01 gklug + * fix: remove struct keyword as much as possible from the C-code (see CCC) + * + * Revision 1.6 1998/08/18 13:03:58 gklug + * SkOsGetTime now returns SK_U64 + * + * Revision 1.5 1998/08/18 08:17:29 malthoff + * Ensure we issue a VPD read in vpd_read_dword(). + * Discard all VPD keywords other than Vx or Yx, where + * x is '0..9' or 'A..Z'. + * + * Revision 1.4 1998/07/03 14:52:19 malthoff + * Add category SK_DBGCAT_FATAL to some debug macros. + * bug fix: correct the keyword name check in vpd_write(). + * + * Revision 1.3 1998/06/26 11:16:53 malthoff + * Correct the modified File Identifier. + * + * Revision 1.2 1998/06/26 11:13:43 malthoff + * Modify the File Identifier. + * + * Revision 1.1 1998/06/19 14:11:08 malthoff + * Created, Tests with AIX were performed successfully + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +/* + Please refer skvpd.txt for infomation how to include this module + */ +static const char SysKonnectFileId[] = + "@(#)$Id: skvpd.c,v 1.37 2003/01/13 10:42:45 rschmidt Exp $ (C) SK"; + +#include "h/skdrv1st.h" +#include "h/sktypes.h" +#include "h/skdebug.h" +#include "h/skdrv2nd.h" + +/* + * Static functions + */ +#ifndef SK_KR_PROTO +static SK_VPD_PARA *vpd_find_para( + SK_AC *pAC, + const char *key, + SK_VPD_PARA *p); +#else /* SK_KR_PROTO */ +static SK_VPD_PARA *vpd_find_para(); +#endif /* SK_KR_PROTO */ + +/* + * waits for a completion of a VPD transfer + * The VPD transfer must complete within SK_TICKS_PER_SEC/16 + * + * returns 0: success, transfer completes + * error exit(9) with a error message + */ +static int VpdWait( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +int event) /* event to wait for (VPD_READ / VPD_write) completion*/ +{ + SK_U64 start_time; + SK_U16 state; + + SK_DBG_MSG(pAC,SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD wait for %s\n", event?"Write":"Read")); + start_time = SkOsGetTime(pAC); + do { + if (SkOsGetTime(pAC) - start_time > SK_TICKS_PER_SEC) { + + /* Bug fix AF: Thu Mar 28 2002 + * Do not call: VPD_STOP(pAC, IoC); + * A pending VPD read cycle can not be aborted by writing + * VPD_WRITE to the PCI_VPD_ADR_REG (VPD address register). + * Although the write threshold in the OUR-register protects + * VPD read only space from being overwritten this does not + * protect a VPD read from being `converted` into a VPD write + * operation (on the fly). As a consequence the VPD_STOP would + * delete VPD read only data. In case of any problems with the + * I2C bus we exit the loop here. The I2C read operation can + * not be aborted except by a reset (->LR). + */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_FATAL | SK_DBGCAT_ERR, + ("ERROR:VPD wait timeout\n")); + return(1); + } + + VPD_IN16(pAC, IoC, PCI_VPD_ADR_REG, &state); + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("state = %x, event %x\n",state,event)); + } while((int)(state & PCI_VPD_FLAG) == event); + + return(0); +} + +#ifdef SKDIAG + +/* + * Read the dword at address 'addr' from the VPD EEPROM. + * + * Needed Time: MIN 1,3 ms MAX 2,6 ms + * + * Note: The DWord is returned in the endianess of the machine the routine + * is running on. + * + * Returns the data read. + */ +SK_U32 VpdReadDWord( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +int addr) /* VPD address */ +{ + SK_U32 Rtv; + + /* start VPD read */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD read dword at 0x%x\n",addr)); + addr &= ~VPD_WRITE; /* ensure the R/W bit is set to read */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)addr); + + /* ignore return code here */ + (void)VpdWait(pAC, IoC, VPD_READ); + + /* Don't swap here, it's a data stream of bytes */ + Rtv = 0; + + VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &Rtv); + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD read dword data = 0x%x\n",Rtv)); + return(Rtv); +} + +#endif /* SKDIAG */ + +#if 0 + +/* + Write the dword 'data' at address 'addr' into the VPD EEPROM, and + verify that the data is written. + + Needed Time: + +. MIN MAX +. ------------------------------------------------------------------- +. write 1.8 ms 3.6 ms +. internal write cyles 0.7 ms 7.0 ms +. ------------------------------------------------------------------- +. over all program time 2.5 ms 10.6 ms +. read 1.3 ms 2.6 ms +. ------------------------------------------------------------------- +. over all 3.8 ms 13.2 ms +. + + + Returns 0: success + 1: error, I2C transfer does not terminate + 2: error, data verify error + + */ +static int VpdWriteDWord( +SK_AC *pAC, /* pAC pointer */ +SK_IOC IoC, /* IO Context */ +int addr, /* VPD address */ +SK_U32 data) /* VPD data to write */ +{ + /* start VPD write */ + /* Don't swap here, it's a data stream of bytes */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD write dword at addr 0x%x, data = 0x%x\n",addr,data)); + VPD_OUT32(pAC, IoC, PCI_VPD_DAT_REG, (SK_U32)data); + /* But do it here */ + addr |= VPD_WRITE; + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)(addr | VPD_WRITE)); + + /* this may take up to 10,6 ms */ + if (VpdWait(pAC, IoC, VPD_WRITE)) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Write Timed Out\n")); + return(1); + }; + + /* verify data */ + if (VpdReadDWord(pAC, IoC, addr) != data) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Data Verify Error\n")); + return(2); + } + return(0); +} /* VpdWriteDWord */ + +#endif /* 0 */ + +/* + * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from + * or to the I2C EEPROM. + * + * Returns number of bytes read / written. + */ +static int VpdWriteStream( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +char *buf, /* data buffer */ +int Addr, /* VPD start address */ +int Len) /* number of bytes to read / to write */ +{ + int i; + int j; + SK_U16 AdrReg; + int Rtv; + SK_U8 * pComp; /* Compare pointer */ + SK_U8 Data; /* Input Data for Compare */ + + /* Init Compare Pointer */ + pComp = (SK_U8 *) buf; + + for (i = 0; i < Len; i++, buf++) { + if ((i%sizeof(SK_U32)) == 0) { + /* + * At the begin of each cycle read the Data Reg + * So it is initialized even if only a few bytes + * are written. + */ + AdrReg = (SK_U16) Addr; + AdrReg &= ~VPD_WRITE; /* READ operation */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); + + /* Wait for termination */ + Rtv = VpdWait(pAC, IoC, VPD_READ); + if (Rtv != 0) { + return(i); + } + } + + /* Write current Byte */ + VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)), + *(SK_U8*)buf); + + if (((i%sizeof(SK_U32)) == 3) || (i == (Len - 1))) { + /* New Address needs to be written to VPD_ADDR reg */ + AdrReg = (SK_U16) Addr; + Addr += sizeof(SK_U32); + AdrReg |= VPD_WRITE; /* WRITE operation */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); + + /* Wait for termination */ + Rtv = VpdWait(pAC, IoC, VPD_WRITE); + if (Rtv != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Write Timed Out\n")); + return(i - (i%sizeof(SK_U32))); + } + + /* + * Now re-read to verify + */ + AdrReg &= ~VPD_WRITE; /* READ operation */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); + + /* Wait for termination */ + Rtv = VpdWait(pAC, IoC, VPD_READ); + if (Rtv != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Verify Timed Out\n")); + return(i - (i%sizeof(SK_U32))); + } + + for (j = 0; j <= (int)(i%sizeof(SK_U32)); j++, pComp++) { + + VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + j, &Data); + + if (Data != *pComp) { + /* Verify Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("WriteStream Verify Error\n")); + return(i - (i%sizeof(SK_U32)) + j); + } + } + } + } + + return(Len); +} + + +/* + * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from + * or to the I2C EEPROM. + * + * Returns number of bytes read / written. + */ +static int VpdReadStream( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +char *buf, /* data buffer */ +int Addr, /* VPD start address */ +int Len) /* number of bytes to read / to write */ +{ + int i; + SK_U16 AdrReg; + int Rtv; + + for (i = 0; i < Len; i++, buf++) { + if ((i%sizeof(SK_U32)) == 0) { + /* New Address needs to be written to VPD_ADDR reg */ + AdrReg = (SK_U16) Addr; + Addr += sizeof(SK_U32); + AdrReg &= ~VPD_WRITE; /* READ operation */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); + + /* Wait for termination */ + Rtv = VpdWait(pAC, IoC, VPD_READ); + if (Rtv != 0) { + return(i); + } + } + VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)), + (SK_U8 *)buf); + } + + return(Len); +} + +/* + * Read ore writes 'len' bytes of VPD data, starting at 'addr' from + * or to the I2C EEPROM. + * + * Returns number of bytes read / written. + */ +static int VpdTransferBlock( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +char *buf, /* data buffer */ +int addr, /* VPD start address */ +int len, /* number of bytes to read / to write */ +int dir) /* transfer direction may be VPD_READ or VPD_WRITE */ +{ + int Rtv; /* Return value */ + int vpd_rom_size; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD %s block, addr = 0x%x, len = %d\n", + dir ? "write" : "read", addr, len)); + + if (len == 0) + return(0); + + vpd_rom_size = pAC->vpd.rom_size; + + if (addr > vpd_rom_size - 4) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Address error: 0x%x, exp. < 0x%x\n", + addr, vpd_rom_size - 4)); + return(0); + } + + if (addr + len > vpd_rom_size) { + len = vpd_rom_size - addr; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Warning: len was cut to %d\n", len)); + } + + if (dir == VPD_READ) { + Rtv = VpdReadStream(pAC, IoC, buf, addr, len); + } + else { + Rtv = VpdWriteStream(pAC, IoC, buf, addr, len); + } + + return(Rtv); +} + +#ifdef SKDIAG + +/* + * Read 'len' bytes of VPD data, starting at 'addr'. + * + * Returns number of bytes read. + */ +int VpdReadBlock( +SK_AC *pAC, /* pAC pointer */ +SK_IOC IoC, /* IO Context */ +char *buf, /* buffer were the data should be stored */ +int addr, /* start reading at the VPD address */ +int len) /* number of bytes to read */ +{ + return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_READ)); +} + +/* + * Write 'len' bytes of *but to the VPD EEPROM, starting at 'addr'. + * + * Returns number of bytes writes. + */ +int VpdWriteBlock( +SK_AC *pAC, /* pAC pointer */ +SK_IOC IoC, /* IO Context */ +char *buf, /* buffer, holds the data to write */ +int addr, /* start writing at the VPD address */ +int len) /* number of bytes to write */ +{ + return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_WRITE)); +} +#endif /* SKDIAG */ + +/* + * (re)initialize the VPD buffer + * + * Reads the VPD data from the EEPROM into the VPD buffer. + * Get the remaining read only and read / write space. + * + * return 0: success + * 1: fatal VPD error + */ +static int VpdInit( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC) /* IO Context */ +{ + SK_VPD_PARA *r, rp; /* RW or RV */ + int i; + unsigned char x; + int vpd_size; + SK_U16 dev_id; + SK_U32 our_reg2; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit .. ")); + + VPD_IN16(pAC, IoC, PCI_DEVICE_ID, &dev_id); + + VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &our_reg2); + + pAC->vpd.rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14); + + /* + * this function might get used before the hardware is initialized + * therefore we cannot always trust in GIChipId + */ + if (((pAC->vpd.v.vpd_status & VPD_VALID) == 0 && + dev_id != VPD_DEV_ID_GENESIS) || + ((pAC->vpd.v.vpd_status & VPD_VALID) != 0 && + !pAC->GIni.GIGenesis)) { + + /* for Yukon the VPD size is always 256 */ + vpd_size = VPD_SIZE_YUKON; + } + else { + /* Genesis uses the maximum ROM size up to 512 for VPD */ + if (pAC->vpd.rom_size > VPD_SIZE_GENESIS) { + vpd_size = VPD_SIZE_GENESIS; + } + else { + vpd_size = pAC->vpd.rom_size; + } + } + + /* read the VPD data into the VPD buffer */ + if (VpdTransferBlock(pAC, IoC, pAC->vpd.vpd_buf, 0, vpd_size, VPD_READ) + != vpd_size) { + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Block Read Error\n")); + return(1); + } + + pAC->vpd.vpd_size = vpd_size; + + /* find the end tag of the RO area */ + if (!(r = vpd_find_para(pAC, VPD_RV, &rp))) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: RV Tag not found\n")); + return(1); + } + + if (r->p_val + r->p_len > pAC->vpd.vpd_buf + vpd_size/2) { + SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: Invalid VPD struct size\n")); + return(1); + } + pAC->vpd.v.vpd_free_ro = r->p_len - 1; + + /* test the checksum */ + for (i = 0, x = 0; (unsigned)i <= (unsigned)vpd_size/2 - r->p_len; i++) { + x += pAC->vpd.vpd_buf[i]; + } + + if (x != 0) { + /* checksum error */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("VPD Checksum Error\n")); + return(1); + } + + /* find and check the end tag of the RW area */ + if (!(r = vpd_find_para(pAC, VPD_RW, &rp))) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: RV Tag not found\n")); + return(1); + } + + if (r->p_val < pAC->vpd.vpd_buf + vpd_size/2) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: Invalid VPD struct size\n")); + return(1); + } + pAC->vpd.v.vpd_free_rw = r->p_len; + + /* everything seems to be ok */ + if (pAC->GIni.GIChipId != 0) { + pAC->vpd.v.vpd_status |= VPD_VALID; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, + ("done. Free RO = %d, Free RW = %d\n", + pAC->vpd.v.vpd_free_ro, pAC->vpd.v.vpd_free_rw)); + + return(0); +} + +/* + * find the Keyword 'key' in the VPD buffer and fills the + * parameter struct 'p' with it's values + * + * returns *p success + * 0: parameter was not found or VPD encoding error + */ +static SK_VPD_PARA *vpd_find_para( +SK_AC *pAC, /* common data base */ +const char *key, /* keyword to find (e.g. "MN") */ +SK_VPD_PARA *p) /* parameter description struct */ +{ + char *v ; /* points to VPD buffer */ + int max; /* Maximum Number of Iterations */ + + v = pAC->vpd.vpd_buf; + max = 128; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD find para %s .. ",key)); + + /* check mandatory resource type ID string (Product Name) */ + if (*v != (char)RES_ID) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Error: 0x%x missing\n", RES_ID)); + return(0); + } + + if (strcmp(key, VPD_NAME) == 0) { + p->p_len = VPD_GET_RES_LEN(v); + p->p_val = VPD_GET_VAL(v); + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("found, len = %d\n", p->p_len)); + return(p); + } + + v += 3 + VPD_GET_RES_LEN(v) + 3; + for (;; ) { + if (SK_MEMCMP(key,v,2) == 0) { + p->p_len = VPD_GET_VPD_LEN(v); + p->p_val = VPD_GET_VAL(v); + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("found, len = %d\n",p->p_len)); + return(p); + } + + /* exit when reaching the "RW" Tag or the maximum of itera. */ + max--; + if (SK_MEMCMP(VPD_RW,v,2) == 0 || max == 0) { + break; + } + + if (SK_MEMCMP(VPD_RV,v,2) == 0) { + v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */ + } + else { + v += 3 + VPD_GET_VPD_LEN(v); + } + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("scanning '%c%c' len = %d\n",v[0],v[1],v[2])); + } + +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, ("not found\n")); + if (max == 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Key/Len Encoding error\n")); + } +#endif /* DEBUG */ + return(0); +} + +/* + * Move 'n' bytes. Begin with the last byte if 'n' is > 0, + * Start with the last byte if n is < 0. + * + * returns nothing + */ +static void vpd_move_para( +char *start, /* start of memory block */ +char *end, /* end of memory block to move */ +int n) /* number of bytes the memory block has to be moved */ +{ + char *p; + int i; /* number of byte copied */ + + if (n == 0) + return; + + i = (int) (end - start + 1); + if (n < 0) { + p = start + n; + while (i != 0) { + *p++ = *start++; + i--; + } + } + else { + p = end + n; + while (i != 0) { + *p-- = *end--; + i--; + } + } +} + +/* + * setup the VPD keyword 'key' at 'ip'. + * + * returns nothing + */ +static void vpd_insert_key( +const char *key, /* keyword to insert */ +const char *buf, /* buffer with the keyword value */ +int len, /* length of the value string */ +char *ip) /* inseration point */ +{ + SK_VPD_KEY *p; + + p = (SK_VPD_KEY *) ip; + p->p_key[0] = key[0]; + p->p_key[1] = key[1]; + p->p_len = (unsigned char) len; + SK_MEMCPY(&p->p_val,buf,len); +} + +/* + * Setup the VPD end tag "RV" / "RW". + * Also correct the remaining space variables vpd_free_ro / vpd_free_rw. + * + * returns 0: success + * 1: encoding error + */ +static int vpd_mod_endtag( +SK_AC *pAC, /* common data base */ +char *etp) /* end pointer input position */ +{ + SK_VPD_KEY *p; + unsigned char x; + int i; + int vpd_size; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD modify endtag at 0x%x = '%c%c'\n",etp,etp[0],etp[1])); + + vpd_size = pAC->vpd.vpd_size; + + p = (SK_VPD_KEY *) etp; + + if (p->p_key[0] != 'R' || (p->p_key[1] != 'V' && p->p_key[1] != 'W')) { + /* something wrong here, encoding error */ + SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: invalid end tag\n")); + return(1); + } + if (etp > pAC->vpd.vpd_buf + vpd_size/2) { + /* create "RW" tag */ + p->p_len = (unsigned char)(pAC->vpd.vpd_buf+vpd_size-etp-3-1); + pAC->vpd.v.vpd_free_rw = (int) p->p_len; + i = pAC->vpd.v.vpd_free_rw; + etp += 3; + } + else { + /* create "RV" tag */ + p->p_len = (unsigned char)(pAC->vpd.vpd_buf+vpd_size/2-etp-3); + pAC->vpd.v.vpd_free_ro = (int) p->p_len - 1; + + /* setup checksum */ + for (i = 0, x = 0; i < vpd_size/2 - p->p_len; i++) { + x += pAC->vpd.vpd_buf[i]; + } + p->p_val = (char) 0 - x; + i = pAC->vpd.v.vpd_free_ro; + etp += 4; + } + while (i) { + *etp++ = 0x00; + i--; + } + + return(0); +} + +/* + * Insert a VPD keyword into the VPD buffer. + * + * The keyword 'key' is inserted at the position 'ip' in the + * VPD buffer. + * The keywords behind the input position will + * be moved. The VPD end tag "RV" or "RW" is generated again. + * + * returns 0: success + * 2: value string was cut + * 4: VPD full, keyword was not written + * 6: fatal VPD error + * + */ +int VpdSetupPara( +SK_AC *pAC, /* common data base */ +const char *key, /* keyword to insert */ +const char *buf, /* buffer with the keyword value */ +int len, /* length of the keyword value */ +int type, /* VPD_RO_KEY or VPD_RW_KEY */ +int op) /* operation to do: ADD_KEY or OWR_KEY */ +{ + SK_VPD_PARA vp; + char *etp; /* end tag position */ + int free; /* remaining space in selected area */ + char *ip; /* input position inside the VPD buffer */ + int rtv; /* return code */ + int head; /* additional haeder bytes to move */ + int found; /* additinoal bytes if the keyword was found */ + int vpd_size; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD setup para key = %s, val = %s\n",key,buf)); + + vpd_size = pAC->vpd.vpd_size; + + rtv = 0; + ip = 0; + if (type == VPD_RW_KEY) { + /* end tag is "RW" */ + free = pAC->vpd.v.vpd_free_rw; + etp = pAC->vpd.vpd_buf + (vpd_size - free - 1 - 3); + } + else { + /* end tag is "RV" */ + free = pAC->vpd.v.vpd_free_ro; + etp = pAC->vpd.vpd_buf + (vpd_size/2 - free - 4); + } + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("Free RO = %d, Free RW = %d\n", + pAC->vpd.v.vpd_free_ro, pAC->vpd.v.vpd_free_rw)); + + head = 0; + found = 0; + if (op == OWR_KEY) { + if (vpd_find_para(pAC, key, &vp)) { + found = 3; + ip = vp.p_val - 3; + free += vp.p_len + 3; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("Overwrite Key\n")); + } + else { + op = ADD_KEY; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("Add Key\n")); + } + } + if (op == ADD_KEY) { + ip = etp; + vp.p_len = 0; + head = 3; + } + + if (len + 3 > free) { + if (free < 7) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD Buffer Overflow, keyword not written\n")); + return(4); + } + /* cut it again */ + len = free - 3; + rtv = 2; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD Buffer Full, Keyword was cut\n")); + } + + vpd_move_para(ip + vp.p_len + found, etp+2, len-vp.p_len+head); + vpd_insert_key(key, buf, len, ip); + if (vpd_mod_endtag(pAC, etp + len - vp.p_len + head)) { + pAC->vpd.v.vpd_status &= ~VPD_VALID; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD Encoding Error\n")); + return(6); + } + + return(rtv); +} + + +/* + * Read the contents of the VPD EEPROM and copy it to the + * VPD buffer if not already done. + * + * return: A pointer to the vpd_status structure. The structure contains + * this fields. + */ +SK_VPD_STATUS *VpdStat( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC) /* IO Context */ +{ + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + (void)VpdInit(pAC, IoC); + } + return(&pAC->vpd.v); +} + + +/* + * Read the contents of the VPD EEPROM and copy it to the VPD + * buffer if not already done. + * Scan the VPD buffer for VPD keywords and create the VPD + * keyword list by copying the keywords to 'buf', all after + * each other and terminated with a '\0'. + * + * Exceptions: o The Resource Type ID String (product name) is called "Name" + * o The VPD end tags 'RV' and 'RW' are not listed + * + * The number of copied keywords is counted in 'elements'. + * + * returns 0: success + * 2: buffer overfull, one or more keywords are missing + * 6: fatal VPD error + * + * example values after returning: + * + * buf = "Name\0PN\0EC\0MN\0SN\0CP\0VF\0VL\0YA\0" + * *len = 30 + * *elements = 9 + */ +int VpdKeys( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +char *buf, /* buffer where to copy the keywords */ +int *len, /* buffer length */ +int *elements) /* number of keywords returned */ +{ + char *v; + int n; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("list VPD keys .. ")); + *elements = 0; + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + *len = 0; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD Init Error, terminated\n")); + return(6); + } + } + + if ((signed)strlen(VPD_NAME) + 1 <= *len) { + v = pAC->vpd.vpd_buf; + strcpy(buf,VPD_NAME); + n = strlen(VPD_NAME) + 1; + buf += n; + *elements = 1; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, + ("'%c%c' ",v[0],v[1])); + } + else { + *len = 0; + SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR, + ("buffer overflow\n")); + return(2); + } + + v += 3 + VPD_GET_RES_LEN(v) + 3; + for (;; ) { + /* exit when reaching the "RW" Tag */ + if (SK_MEMCMP(VPD_RW,v,2) == 0) { + break; + } + + if (SK_MEMCMP(VPD_RV,v,2) == 0) { + v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */ + continue; + } + + if (n+3 <= *len) { + SK_MEMCPY(buf,v,2); + buf += 2; + *buf++ = '\0'; + n += 3; + v += 3 + VPD_GET_VPD_LEN(v); + *elements += 1; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, + ("'%c%c' ",v[0],v[1])); + } + else { + *len = n; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("buffer overflow\n")); + return(2); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("\n")); + *len = n; + return(0); +} + + +/* + * Read the contents of the VPD EEPROM and copy it to the + * VPD buffer if not already done. Search for the VPD keyword + * 'key' and copy its value to 'buf'. Add a terminating '\0'. + * If the value does not fit into the buffer cut it after + * 'len' - 1 bytes. + * + * returns 0: success + * 1: keyword not found + * 2: value string was cut + * 3: VPD transfer timeout + * 6: fatal VPD error + */ +int VpdRead( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +const char *key, /* keyword to read (e.g. "MN") */ +char *buf, /* buffer where to copy the keyword value */ +int *len) /* buffer length */ +{ + SK_VPD_PARA *p, vp; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("VPD read %s .. ", key)); + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + *len = 0; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD init error\n")); + return(6); + } + } + + if ((p = vpd_find_para(pAC, key, &vp)) != NULL) { + if (p->p_len > (*(unsigned *)len)-1) { + p->p_len = *len - 1; + } + SK_MEMCPY(buf, p->p_val, p->p_len); + buf[p->p_len] = '\0'; + *len = p->p_len; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, + ("%c%c%c%c.., len = %d\n", + buf[0],buf[1],buf[2],buf[3],*len)); + } + else { + *len = 0; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("not found\n")); + return(1); + } + return(0); +} + + +/* + * Check whether a given key may be written + * + * returns + * SK_TRUE Yes it may be written + * SK_FALSE No it may be written + */ +SK_BOOL VpdMayWrite( +char *key) /* keyword to write (allowed values "Yx", "Vx") */ +{ + if ((*key != 'Y' && *key != 'V') || + key[1] < '0' || key[1] > 'Z' || + (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) { + + return(SK_FALSE); + } + return(SK_TRUE); +} + +/* + * Read the contents of the VPD EEPROM and copy it to the VPD + * buffer if not already done. Insert/overwrite the keyword 'key' + * in the VPD buffer. Cut the keyword value if it does not fit + * into the VPD read / write area. + * + * returns 0: success + * 2: value string was cut + * 3: VPD transfer timeout + * 4: VPD full, keyword was not written + * 5: keyword cannot be written + * 6: fatal VPD error + */ +int VpdWrite( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +const char *key, /* keyword to write (allowed values "Yx", "Vx") */ +const char *buf) /* buffer where the keyword value can be read from */ +{ + int len; /* length of the keyword to write */ + int rtv; /* return code */ + int rtv2; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, + ("VPD write %s = %s\n",key,buf)); + + if ((*key != 'Y' && *key != 'V') || + key[1] < '0' || key[1] > 'Z' || + (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) { + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("illegal key tag, keyword not written\n")); + return(5); + } + + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD init error\n")); + return(6); + } + } + + rtv = 0; + len = strlen(buf); + if (len > VPD_MAX_LEN) { + /* cut it */ + len = VPD_MAX_LEN; + rtv = 2; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("keyword too long, cut after %d bytes\n",VPD_MAX_LEN)); + } + if ((rtv2 = VpdSetupPara(pAC, key, buf, len, VPD_RW_KEY, OWR_KEY)) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD write error\n")); + return(rtv2); + } + + return(rtv); +} + +/* + * Read the contents of the VPD EEPROM and copy it to the + * VPD buffer if not already done. Remove the VPD keyword + * 'key' from the VPD buffer. + * Only the keywords in the read/write area can be deleted. + * Keywords in the read only area cannot be deleted. + * + * returns 0: success, keyword was removed + * 1: keyword not found + * 5: keyword cannot be deleted + * 6: fatal VPD error + */ +int VpdDelete( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +char *key) /* keyword to read (e.g. "MN") */ +{ + SK_VPD_PARA *p, vp; + char *etp; + int vpd_size; + + vpd_size = pAC->vpd.vpd_size; + + SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("VPD delete key %s\n",key)); + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD init error\n")); + return(6); + } + } + + if ((p = vpd_find_para(pAC, key, &vp)) != NULL) { + if (p->p_val < pAC->vpd.vpd_buf + vpd_size/2) { + /* try to delete read only keyword */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("cannot delete RO keyword\n")); + return(5); + } + + etp = pAC->vpd.vpd_buf + (vpd_size-pAC->vpd.v.vpd_free_rw-1-3); + + vpd_move_para(vp.p_val+vp.p_len, etp+2, + - ((int)(vp.p_len + 3))); + if (vpd_mod_endtag(pAC, etp - vp.p_len - 3)) { + pAC->vpd.v.vpd_status &= ~VPD_VALID; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD encoding error\n")); + return(6); + } + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("keyword not found\n")); + return(1); + } + + return(0); +} + +/* + * If the VPD buffer contains valid data write the VPD + * read/write area back to the VPD EEPROM. + * + * returns 0: success + * 3: VPD transfer timeout + */ +int VpdUpdate( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC) /* IO Context */ +{ + int vpd_size; + + vpd_size = pAC->vpd.vpd_size; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("VPD update .. ")); + if ((pAC->vpd.v.vpd_status & VPD_VALID) != 0) { + if (VpdTransferBlock(pAC, IoC, pAC->vpd.vpd_buf + vpd_size/2, + vpd_size/2, vpd_size/2, VPD_WRITE) != vpd_size/2) { + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("transfer timed out\n")); + return(3); + } + } + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("done\n")); + return(0); +} + + +/* + * Read the contents of the VPD EEPROM and copy it to the VPD buffer + * if not already done. If the keyword "VF" is not present it will be + * created and the error log message will be stored to this keyword. + * If "VF" is not present the error log message will be stored to the + * keyword "VL". "VL" will created or overwritten if "VF" is present. + * The VPD read/write area is saved to the VPD EEPROM. + * + * returns nothing, errors will be ignored. + */ +void VpdErrLog( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +char *msg) /* error log message */ +{ + SK_VPD_PARA *v, vf; /* VF */ + int len; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, + ("VPD error log msg %s\n", msg)); + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD init error\n")); + return; + } + } + + len = strlen(msg); + if (len > VPD_MAX_LEN) { + /* cut it */ + len = VPD_MAX_LEN; + } + if ((v = vpd_find_para(pAC, VPD_VF, &vf)) != NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("overwrite VL\n")); + (void)VpdSetupPara(pAC, VPD_VL, msg, len, VPD_RW_KEY, OWR_KEY); + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("write VF\n")); + (void)VpdSetupPara(pAC, VPD_VF, msg, len, VPD_RW_KEY, ADD_KEY); + } + + (void)VpdUpdate(pAC, IoC); +} + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skxmac2.c b/drivers/sk98lin/skxmac2.c new file mode 100644 index 0000000..e6b5a95 --- /dev/null +++ b/drivers/sk98lin/skxmac2.c @@ -0,0 +1,4396 @@ +/****************************************************************************** + * + * Name: skxmac2.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.91 $ + * Date: $Date: 2003/02/05 15:09:34 $ + * Purpose: Contains functions to initialize the MACs and PHYs + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skxmac2.c,v $ + * Revision 1.91 2003/02/05 15:09:34 rschmidt + * Removed setting of 'Collision Test'-bit in SkGmInitPhyMarv(). + * Disabled auto-update for speed, duplex and flow-control when + * auto-negotiation is not enabled (Bug Id #10766). + * Editorial changes. + * + * Revision 1.90 2003/01/29 13:35:19 rschmidt + * Increment Rx FIFO Overflow counter only in DEBUG-mode. + * Corrected define for blinking active LED. + * + * Revision 1.89 2003/01/28 16:37:45 rschmidt + * Changed init for blinking active LED + * + * Revision 1.88 2003/01/28 10:09:38 rschmidt + * Added debug outputs in SkGmInitMac(). + * Added customized init of LED registers in SkGmInitPhyMarv(), + * for blinking active LED (#ifdef ACT_LED_BLINK) and + * for normal duplex LED (#ifdef DUP_LED_NORMAL). + * Editorial changes. + * + * Revision 1.87 2002/12/10 14:39:05 rschmidt + * Improved initialization of GPHY in SkGmInitPhyMarv(). + * Editorial changes. + * + * Revision 1.86 2002/12/09 15:01:12 rschmidt + * Added setup of Ext. PHY Specific Ctrl Reg (downshift feature). + * + * Revision 1.85 2002/12/05 14:09:16 rschmidt + * Improved avoiding endless loop in SkGmPhyWrite(), SkGmPhyWrite(). + * Added additional advertising for 10Base-T when 100Base-T is selected. + * Added case SK_PHY_MARV_FIBER for YUKON Fiber adapter. + * Editorial changes. + * + * Revision 1.84 2002/11/15 12:50:09 rschmidt + * Changed SkGmCableDiagStatus() when getting results. + * + * Revision 1.83 2002/11/13 10:28:29 rschmidt + * Added some typecasts to avoid compiler warnings. + * + * Revision 1.82 2002/11/13 09:20:46 rschmidt + * Replaced for(..) with do {} while (...) in SkXmUpdateStats(). + * Replaced 2 macros GM_IN16() with 1 GM_IN32() in SkGmMacStatistic(). + * Added SkGmCableDiagStatus() for Virtual Cable Test (VCT). + * Editorial changes. + * + * Revision 1.81 2002/10/28 14:28:08 rschmidt + * Changed MAC address setup for GMAC in SkGmInitMac(). + * Optimized handling of counter overflow IRQ in SkGmOverflowStatus(). + * Editorial changes. + * + * Revision 1.80 2002/10/14 15:29:44 rschmidt + * Corrected disabling of all PHY IRQs. + * Added WA for deviation #16 (address used for pause packets). + * Set Pause Mode in SkMacRxTxEnable() only for Genesis. + * Added IRQ and counter for Receive FIFO Overflow in DEBUG-mode. + * SkXmTimeStamp() replaced by SkMacTimeStamp(). + * Added clearing of GMAC Tx FIFO Underrun IRQ in SkGmIrq(). + * Editorial changes. + * + * Revision 1.79 2002/10/10 15:55:36 mkarl + * changes for PLinkSpeedUsed + * + * Revision 1.78 2002/09/12 09:39:51 rwahl + * Removed deactivate code for SIRQ overflow event separate for TX/RX. + * + * Revision 1.77 2002/09/09 12:26:37 mkarl + * added handling for Yukon to SkXmTimeStamp + * + * Revision 1.76 2002/08/21 16:41:16 rschmidt + * Added bit GPC_ENA_XC (Enable MDI crossover) in HWCFG_MODE. + * Added forced speed settings in SkGmInitPhyMarv(). + * Added settings of full/half duplex capabilities for YUKON Fiber. + * Editorial changes. + * + * Revision 1.75 2002/08/16 15:12:01 rschmidt + * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis. + * Added function SkMacHashing() for ADDR-Module. + * Removed functions SkXmClrSrcCheck(), SkXmClrHashAddr() (calls replaced + * with macros). + * Removed functions SkGmGetMuxConfig(). + * Added HWCFG_MODE init for YUKON Fiber. + * Changed initialization of GPHY in SkGmInitPhyMarv(). + * Changed check of parameter in SkXmMacStatistic(). + * Editorial changes. + * + * Revision 1.74 2002/08/12 14:00:17 rschmidt + * Replaced usage of Broadcom PHY Ids with defines. + * Corrected error messages in SkGmMacStatistic(). + * Made SkMacPromiscMode() public for ADDR-Modul. + * Editorial changes. + * + * Revision 1.73 2002/08/08 16:26:24 rschmidt + * Improved reset sequence for YUKON in SkGmHardRst() and SkGmInitMac(). + * Replaced XMAC Rx High Watermark init value with SK_XM_RX_HI_WM. + * Editorial changes. + * + * Revision 1.72 2002/07/24 15:11:19 rschmidt + * Fixed wrong placement of parenthesis. + * Editorial changes. + * + * Revision 1.71 2002/07/23 16:05:18 rschmidt + * Added global functions for PHY: SkGePhyRead(), SkGePhyWrite(). + * Fixed Tx Counter Overflow IRQ (Bug ID #10730). + * Editorial changes. + * + * Revision 1.70 2002/07/18 14:27:27 rwahl + * Fixed syntax error. + * + * Revision 1.69 2002/07/17 17:08:47 rwahl + * Fixed check in SkXmMacStatistic(). + * + * Revision 1.68 2002/07/16 07:35:24 rwahl + * Removed check for cleared mib counter in SkGmResetCounter(). + * + * Revision 1.67 2002/07/15 18:35:56 rwahl + * Added SkXmUpdateStats(), SkGmUpdateStats(), SkXmMacStatistic(), + * SkGmMacStatistic(), SkXmResetCounter(), SkGmResetCounter(), + * SkXmOverflowStatus(), SkGmOverflowStatus(). + * Changes to SkXmIrq() & SkGmIrq(): Combined SIRQ Overflow for both + * RX & TX. + * Changes to SkGmInitMac(): call to SkGmResetCounter(). + * Editorial changes. + * + * Revision 1.66 2002/07/15 15:59:30 rschmidt + * Added PHY Address in SkXmPhyRead(), SkXmPhyWrite(). + * Added MIB Clear Counter in SkGmInitMac(). + * Added Duplex and Flow-Control settings. + * Reset all Multicast filtering Hash reg. in SkGmInitMac(). + * Added new function: SkGmGetMuxConfig(). + * Editorial changes. + * + * Revision 1.65 2002/06/10 09:35:39 rschmidt + * Replaced C++ comments (//). + * Added #define VCPU around VCPUwaitTime. + * Editorial changes. + * + * Revision 1.64 2002/06/05 08:41:10 rschmidt + * Added function for XMAC2: SkXmTimeStamp(). + * Added function for YUKON: SkGmSetRxCmd(). + * Changed SkGmInitMac() resp. SkGmHardRst(). + * Fixed wrong variable in SkXmAutoNegLipaXmac() (debug mode). + * SkXmRxTxEnable() replaced by SkMacRxTxEnable(). + * Editorial changes. + * + * Revision 1.63 2002/04/25 13:04:44 rschmidt + * Changes for handling YUKON. + * Use of #ifdef OTHER_PHY to eliminate code for unused Phy types. + * Macros for XMAC PHY access PHY_READ(), PHY_WRITE() replaced + * by functions SkXmPhyRead(), SkXmPhyWrite(); + * Removed use of PRxCmd to setup XMAC. + * Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res. + * Added setting of XM_RX_DIS_CEXT in SkXmInitMac(). + * Removed status parameter from MAC IRQ handler SkMacIrq(), + * SkXmIrq() and SkGmIrq(). + * SkXmAutoNegLipa...() for ext. Phy replaced by SkMacAutoNegLipaPhy(). + * Added SkMac...() functions to handle both XMAC and GMAC. + * Added functions for YUKON: SkGmHardRst(), SkGmSoftRst(), + * SkGmSetRxTxEn(), SkGmIrq(), SkGmInitMac(), SkGmInitPhyMarv(), + * SkGmAutoNegDoneMarv(), SkGmPhyRead(), SkGmPhyWrite(). + * Changes for V-CPU support. + * Editorial changes. + * + * Revision 1.62 2001/08/06 09:50:14 rschmidt + * Workaround BCOM Errata #1 for the C5 type. + * Editorial changes. + * + * Revision 1.61 2001/02/09 15:40:59 rassmann + * Editorial changes. + * + * Revision 1.60 2001/02/07 15:02:01 cgoos + * Added workaround for Fujitsu switch link down. + * + * Revision 1.59 2001/01/10 09:38:06 cgoos + * Fixed Broadcom C0/A1 Id check for workaround. + * + * Revision 1.58 2000/11/29 11:30:38 cgoos + * Changed DEBUG sections with NW output to xDEBUG + * + * Revision 1.57 2000/11/27 12:40:40 rassmann + * Suppressing preamble after first access to BCom, not before (#10556). + * + * Revision 1.56 2000/11/09 12:32:48 rassmann + * Renamed variables. + * + * Revision 1.55 2000/11/09 11:30:10 rassmann + * WA: Waiting after releasing reset until BCom chip is accessible. + * + * Revision 1.54 2000/10/02 14:10:27 rassmann + * Reading BCOM PHY after releasing reset until it returns a valid value. + * + * Revision 1.53 2000/07/27 12:22:11 gklug + * fix: possible endless loop in XmHardRst. + * + * Revision 1.52 2000/05/22 08:48:31 malthoff + * Fix: #10523 errata valid for all BCOM PHYs. + * + * Revision 1.51 2000/05/17 12:52:18 malthoff + * Fixes BCom link errata (#10523). + * + * Revision 1.50 1999/11/22 13:40:14 cgoos + * Changed license header to GPL. + * + * Revision 1.49 1999/11/22 08:12:13 malthoff + * Add workaround for power consumption feature of BCom C0 chip. + * + * Revision 1.48 1999/11/16 08:39:01 malthoff + * Fix: MDIO preamble suppression is port dependent. + * + * Revision 1.47 1999/08/27 08:55:35 malthoff + * 1000BT: Optimizing MDIO transfer by oppressing MDIO preamble. + * + * Revision 1.46 1999/08/13 11:01:12 malthoff + * Fix for 1000BT: pFlowCtrlMode was not set correctly. + * + * Revision 1.45 1999/08/12 19:18:28 malthoff + * 1000BT Fixes: Do not owerwrite XM_MMU_CMD. + * Do not execute BCOM A1 workaround for B1 chips. + * Fix pause frame setting. + * Always set PHY_B_AC_TX_TST in PHY_BCOM_AUX_CTRL. + * + * Revision 1.44 1999/08/03 15:23:48 cgoos + * Fixed setting of PHY interrupt mask in half duplex mode. + * + * Revision 1.43 1999/08/03 15:22:17 cgoos + * Added some debug output. + * Disabled XMac GP0 interrupt for external PHYs. + * + * Revision 1.42 1999/08/02 08:39:23 malthoff + * BCOM PHY: TX LED: To get the mono flop behaviour it is required + * to set the LED Traffic Mode bit in PHY_BCOM_P_EXT_CTRL. + * + * Revision 1.41 1999/07/30 06:54:31 malthoff + * Add temp. workarounds for the BCOM Phy revision A1. + * + * Revision 1.40 1999/06/01 07:43:26 cgoos + * Changed Link Mode Status in SkXmAutoNegDone... from FULL/HALF to + * AUTOFULL/AUTOHALF. + * + * Revision 1.39 1999/05/19 07:29:51 cgoos + * Changes for 1000Base-T. + * + * Revision 1.38 1999/04/08 14:35:10 malthoff + * Add code for enabling signal detect. Enabling signal detect is disabled. + * + * Revision 1.37 1999/03/12 13:42:54 malthoff + * Add: Jumbo Frame Support. + * Add: Receive modes SK_LENERR_OK_ON/OFF and + * SK_BIG_PK_OK_ON/OFF in SkXmSetRxCmd(). + * + * Revision 1.36 1999/03/08 10:10:55 gklug + * fix: AutoSensing did switch to next mode even if LiPa indicated offline + * + * Revision 1.35 1999/02/22 15:16:41 malthoff + * Remove some compiler warnings. + * + * Revision 1.34 1999/01/22 09:19:59 gklug + * fix: Init DupMode and InitPauseMd are now called in RxTxEnable + * + * Revision 1.33 1998/12/11 15:19:11 gklug + * chg: lipa autoneg stati + * chg: debug messages + * chg: do NOT use spurious XmIrq + * + * Revision 1.32 1998/12/10 11:08:44 malthoff + * bug fix: pAC has been used for IOs in SkXmHardRst(). + * SkXmInitPhy() is also called for the Diag in SkXmInitMac(). + * + * Revision 1.31 1998/12/10 10:39:11 gklug + * fix: do 4 RESETS of the XMAC at the beginning + * fix: dummy read interrupt source register BEFORE initializing the Phy + * add: debug messages + * fix: Linkpartners autoneg capability cannot be shown by TX_PAGE interrupt + * + * Revision 1.30 1998/12/07 12:18:32 gklug + * add: refinement of autosense mode: take into account the autoneg cap of LiPa + * + * Revision 1.29 1998/12/07 07:12:29 gklug + * fix: if page is received the link is down. + * + * Revision 1.28 1998/12/01 10:12:47 gklug + * chg: if spurious IRQ from XMAC encountered, save it + * + * Revision 1.27 1998/11/26 07:33:38 gklug + * add: InitPhy call is now in XmInit function + * + * Revision 1.26 1998/11/18 13:38:24 malthoff + * 'Imsk' is also unused in SkXmAutoNegDone. + * + * Revision 1.25 1998/11/18 13:28:01 malthoff + * Remove unused variable 'Reg' in SkXmAutoNegDone(). + * + * Revision 1.24 1998/11/18 13:18:45 gklug + * add: workaround for xmac errata #1 + * add: detect Link Down also when Link partner requested config + * chg: XMIrq is only used when link is up + * + * Revision 1.23 1998/11/04 07:07:04 cgoos + * Added function SkXmRxTxEnable. + * + * Revision 1.22 1998/10/30 07:35:54 gklug + * fix: serve LinkDown interrupt when link is already down + * + * Revision 1.21 1998/10/29 15:32:03 gklug + * fix: Link Down signaling + * + * Revision 1.20 1998/10/29 11:17:27 gklug + * fix: AutoNegDone bug + * + * Revision 1.19 1998/10/29 10:14:43 malthoff + * Add endainesss comment for reading/writing MAC addresses. + * + * Revision 1.18 1998/10/28 07:48:55 cgoos + * Fix: ASS somtimes signaled although link is up. + * + * Revision 1.17 1998/10/26 07:55:39 malthoff + * Fix in SkXmInitPauseMd(): Pause Mode + * was disabled and not enabled. + * Fix in SkXmAutoNegDone(): Checking Mode bits + * always failed, becaues of some missing braces. + * + * Revision 1.16 1998/10/22 09:46:52 gklug + * fix SysKonnectFileId typo + * + * Revision 1.15 1998/10/21 05:51:37 gklug + * add: para DoLoop to InitPhy function for loopback set-up + * + * Revision 1.14 1998/10/16 10:59:23 malthoff + * Remove Lint warning for dummy reads. + * + * Revision 1.13 1998/10/15 14:01:20 malthoff + * Fix: SkXmAutoNegDone() is (int) but does not return a value. + * + * Revision 1.12 1998/10/14 14:45:04 malthoff + * Remove SKERR_SIRQ_E0xx and SKERR_SIRQ_E0xxMSG by + * SKERR_HWI_Exx and SKERR_HWI_E0xxMSG to be independent + * from the Sirq module. + * + * Revision 1.11 1998/10/14 13:59:01 gklug + * add: InitPhy function + * + * Revision 1.10 1998/10/14 11:20:57 malthoff + * Make SkXmAutoNegDone() public, because it's + * used in diagnostics, too. + * The Link Up event to the RLMT is issued in SkXmIrq(). + * SkXmIrq() is not available in diagnostics. + * Use PHY_READ when reading PHY registers. + * + * Revision 1.9 1998/10/14 05:50:10 cgoos + * Added definition for Para. + * + * Revision 1.8 1998/10/14 05:41:28 gklug + * add: Xmac IRQ + * add: auto-negotiation done function + * + * Revision 1.7 1998/10/09 06:55:20 malthoff + * The configuration of the XMACs Tx Request Threshold + * depends from the drivers port usage now. The port + * usage is configured in GIPortUsage. + * + * Revision 1.6 1998/10/05 07:48:00 malthoff + * minor changes + * + * Revision 1.5 1998/10/01 07:03:54 gklug + * add: dummy function for XMAC ISR + * + * Revision 1.4 1998/09/30 12:37:44 malthoff + * Add SkXmSetRxCmd() and related code. + * + * Revision 1.3 1998/09/28 13:26:40 malthoff + * Add SkXmInitMac(), SkXmInitDupMd(), and SkXmInitPauseMd() + * + * Revision 1.2 1998/09/16 14:34:21 malthoff + * Add SkXmClrExactAddr(), SkXmClrSrcCheck(), + * SkXmClrHashAddr(), SkXmFlushTxFifo(), + * SkXmFlushRxFifo(), and SkXmHardRst(). + * Finish Coding of SkXmSoftRst(). + * The sources may be compiled now. + * + * Revision 1.1 1998/09/04 10:05:56 malthoff + * Created. + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/* typedefs *******************************************************************/ + +/* BCOM PHY magic pattern list */ +typedef struct s_PhyHack { + int PhyReg; /* Phy register */ + SK_U16 PhyVal; /* Value to write */ +} BCOM_HACK; + +/* local variables ************************************************************/ +static const char SysKonnectFileId[] = + "@(#)$Id: skxmac2.c,v 1.91 2003/02/05 15:09:34 rschmidt Exp $ (C) SK "; + +BCOM_HACK BcomRegA1Hack[] = { + { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, + { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, + { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, + { 0, 0 } +}; +BCOM_HACK BcomRegC0Hack[] = { + { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, { 0x17, 0x0013 }, + { 0x15, 0x0A04 }, { 0x18, 0x0420 }, + { 0, 0 } +}; + +/* function prototypes ********************************************************/ +static void SkXmInitPhyXmac(SK_AC*, SK_IOC, int, SK_BOOL); +static void SkXmInitPhyBcom(SK_AC*, SK_IOC, int, SK_BOOL); +static void SkGmInitPhyMarv(SK_AC*, SK_IOC, int, SK_BOOL); +static int SkXmAutoNegDoneXmac(SK_AC*, SK_IOC, int); +static int SkXmAutoNegDoneBcom(SK_AC*, SK_IOC, int); +static int SkGmAutoNegDoneMarv(SK_AC*, SK_IOC, int); +#ifdef OTHER_PHY +static void SkXmInitPhyLone(SK_AC*, SK_IOC, int, SK_BOOL); +static void SkXmInitPhyNat (SK_AC*, SK_IOC, int, SK_BOOL); +static int SkXmAutoNegDoneLone(SK_AC*, SK_IOC, int); +static int SkXmAutoNegDoneNat (SK_AC*, SK_IOC, int); +#endif /* OTHER_PHY */ + + +/****************************************************************************** + * + * SkXmPhyRead() - Read from XMAC PHY register + * + * Description: reads a 16-bit word from XMAC PHY or ext. PHY + * + * Returns: + * nothing + */ +void SkXmPhyRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 *pVal) /* Pointer to Value */ +{ + SK_U16 Mmu; + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + /* write the PHY register's address */ + XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr); + + /* get the PHY register's value */ + XM_IN16(IoC, Port, XM_PHY_DATA, pVal); + + if (pPrt->PhyType != SK_PHY_XMAC) { + do { + XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu); + /* wait until 'Ready' is set */ + } while ((Mmu & XM_MMU_PHY_RDY) == 0); + + /* get the PHY register's value */ + XM_IN16(IoC, Port, XM_PHY_DATA, pVal); + } +} /* SkXmPhyRead */ + + +/****************************************************************************** + * + * SkXmPhyWrite() - Write to XMAC PHY register + * + * Description: writes a 16-bit word to XMAC PHY or ext. PHY + * + * Returns: + * nothing + */ +void SkXmPhyWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 Val) /* Value */ +{ + SK_U16 Mmu; + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PhyType != SK_PHY_XMAC) { + do { + XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu); + /* wait until 'Busy' is cleared */ + } while ((Mmu & XM_MMU_PHY_BUSY) != 0); + } + + /* write the PHY register's address */ + XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr); + + /* write the PHY register's value */ + XM_OUT16(IoC, Port, XM_PHY_DATA, Val); + + if (pPrt->PhyType != SK_PHY_XMAC) { + do { + XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu); + /* wait until 'Busy' is cleared */ + } while ((Mmu & XM_MMU_PHY_BUSY) != 0); + } +} /* SkXmPhyWrite */ + + +/****************************************************************************** + * + * SkGmPhyRead() - Read from GPHY register + * + * Description: reads a 16-bit word from GPHY through MDIO + * + * Returns: + * nothing + */ +void SkGmPhyRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 *pVal) /* Pointer to Value */ +{ + SK_U16 Ctrl; + SK_GEPORT *pPrt; +#ifdef VCPU + u_long SimCyle; + u_long SimLowTime; + + VCPUgetTime(&SimCyle, &SimLowTime); + VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n", + PhyReg, SimCyle, SimLowTime); +#endif /* VCPU */ + + pPrt = &pAC->GIni.GP[Port]; + + /* set PHY-Register offset and 'Read' OpCode (= 1) */ + *pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | + GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD); + + GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal); + + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + + /* additional check for MDC/MDIO activity */ + if ((Ctrl & GM_SMI_CT_BUSY) == 0) { + *pVal = 0; + return; + } + + *pVal |= GM_SMI_CT_BUSY; + + do { +#ifdef VCPU + VCPUwaitTime(1000); +#endif /* VCPU */ + + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + + /* wait until 'ReadValid' is set */ + } while (Ctrl == *pVal); + + /* get the PHY register's value */ + GM_IN16(IoC, Port, GM_SMI_DATA, pVal); + +#ifdef VCPU + VCPUgetTime(&SimCyle, &SimLowTime); + VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n", + SimCyle, SimLowTime); +#endif /* VCPU */ +} /* SkGmPhyRead */ + + +/****************************************************************************** + * + * SkGmPhyWrite() - Write to GPHY register + * + * Description: writes a 16-bit word to GPHY through MDIO + * + * Returns: + * nothing + */ +void SkGmPhyWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 Val) /* Value */ +{ + SK_U16 Ctrl; + SK_GEPORT *pPrt; +#ifdef VCPU + SK_U32 DWord; + u_long SimCyle; + u_long SimLowTime; + + VCPUgetTime(&SimCyle, &SimLowTime); + VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n", + PhyReg, Val, SimCyle, SimLowTime); +#endif /* VCPU */ + + pPrt = &pAC->GIni.GP[Port]; + + /* write the PHY register's value */ + GM_OUT16(IoC, Port, GM_SMI_DATA, Val); + + /* set PHY-Register offset and 'Write' OpCode (= 0) */ + Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg); + + GM_OUT16(IoC, Port, GM_SMI_CTRL, Val); + + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + + /* additional check for MDC/MDIO activity */ + if ((Ctrl & GM_SMI_CT_BUSY) == 0) { + return; + } + + Val |= GM_SMI_CT_BUSY; + + do { +#ifdef VCPU + /* read Timer value */ + SK_IN32(IoC, B2_TI_VAL, &DWord); + + VCPUwaitTime(1000); +#endif /* VCPU */ + + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + + /* wait until 'Busy' is cleared */ + } while (Ctrl == Val); + +#ifdef VCPU + VCPUgetTime(&SimCyle, &SimLowTime); + VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n", + SimCyle, SimLowTime); +#endif /* VCPU */ +} /* SkGmPhyWrite */ + + +/****************************************************************************** + * + * SkGePhyRead() - Read from PHY register + * + * Description: calls a read PHY routine dep. on board type + * + * Returns: + * nothing + */ +void SkGePhyRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 *pVal) /* Pointer to Value */ +{ + void (*r_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 *pVal); + + if (pAC->GIni.GIGenesis) { + r_func = SkXmPhyRead; + } + else { + r_func = SkGmPhyRead; + } + + r_func(pAC, IoC, Port, PhyReg, pVal); +} /* SkGePhyRead */ + + +/****************************************************************************** + * + * SkGePhyWrite() - Write to PHY register + * + * Description: calls a write PHY routine dep. on board type + * + * Returns: + * nothing + */ +void SkGePhyWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 Val) /* Value */ +{ + void (*w_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 Val); + + if (pAC->GIni.GIGenesis) { + w_func = SkXmPhyWrite; + } + else { + w_func = SkGmPhyWrite; + } + + w_func(pAC, IoC, Port, PhyReg, Val); +} /* SkGePhyWrite */ + + +/****************************************************************************** + * + * SkMacPromiscMode() - Enable / Disable Promiscuous Mode + * + * Description: + * enables / disables promiscuous mode by setting Mode Register (XMAC) or + * Receive Control Register (GMAC) dep. on board type + * + * Returns: + * nothing + */ +void SkMacPromiscMode( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U16 RcReg; + SK_U32 MdReg; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + /* enable or disable promiscuous mode */ + if (Enable) { + MdReg |= XM_MD_ENA_PROM; + } + else { + MdReg &= ~XM_MD_ENA_PROM; + } + /* setup Mode Register */ + XM_OUT32(IoC, Port, XM_MODE, MdReg); + } + else { + + GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg); + + /* enable or disable unicast and multicast filtering */ + if (Enable) { + RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); + } + else { + RcReg |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); + } + /* setup Receive Control Register */ + GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg); + } +} /* SkMacPromiscMode*/ + + +/****************************************************************************** + * + * SkMacHashing() - Enable / Disable Hashing + * + * Description: + * enables / disables hashing by setting Mode Register (XMAC) or + * Receive Control Register (GMAC) dep. on board type + * + * Returns: + * nothing + */ +void SkMacHashing( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U16 RcReg; + SK_U32 MdReg; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + /* enable or disable hashing */ + if (Enable) { + MdReg |= XM_MD_ENA_HASH; + } + else { + MdReg &= ~XM_MD_ENA_HASH; + } + /* setup Mode Register */ + XM_OUT32(IoC, Port, XM_MODE, MdReg); + } + else { + + GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg); + + /* enable or disable multicast filtering */ + if (Enable) { + RcReg |= GM_RXCR_MCF_ENA; + } + else { + RcReg &= ~GM_RXCR_MCF_ENA; + } + /* setup Receive Control Register */ + GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg); + } +} /* SkMacHashing*/ + + +#ifdef SK_DIAG +/****************************************************************************** + * + * SkXmSetRxCmd() - Modify the value of the XMAC's Rx Command Register + * + * Description: + * The features + * - FCS stripping, SK_STRIP_FCS_ON/OFF + * - pad byte stripping, SK_STRIP_PAD_ON/OFF + * - don't set XMR_FS_ERR in status SK_LENERR_OK_ON/OFF + * for inrange length error frames + * - don't set XMR_FS_ERR in status SK_BIG_PK_OK_ON/OFF + * for frames > 1514 bytes + * - enable Rx of own packets SK_SELF_RX_ON/OFF + * + * for incoming packets may be enabled/disabled by this function. + * Additional modes may be added later. + * Multiple modes can be enabled/disabled at the same time. + * The new configuration is written to the Rx Command register immediately. + * + * Returns: + * nothing + */ +static void SkXmSetRxCmd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, + SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */ +{ + SK_U16 OldRxCmd; + SK_U16 RxCmd; + + XM_IN16(IoC, Port, XM_RX_CMD, &OldRxCmd); + + RxCmd = OldRxCmd; + + switch (Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) { + case SK_STRIP_FCS_ON: + RxCmd |= XM_RX_STRIP_FCS; + break; + case SK_STRIP_FCS_OFF: + RxCmd &= ~XM_RX_STRIP_FCS; + break; + } + + switch (Mode & (SK_STRIP_PAD_ON | SK_STRIP_PAD_OFF)) { + case SK_STRIP_PAD_ON: + RxCmd |= XM_RX_STRIP_PAD; + break; + case SK_STRIP_PAD_OFF: + RxCmd &= ~XM_RX_STRIP_PAD; + break; + } + + switch (Mode & (SK_LENERR_OK_ON | SK_LENERR_OK_OFF)) { + case SK_LENERR_OK_ON: + RxCmd |= XM_RX_LENERR_OK; + break; + case SK_LENERR_OK_OFF: + RxCmd &= ~XM_RX_LENERR_OK; + break; + } + + switch (Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) { + case SK_BIG_PK_OK_ON: + RxCmd |= XM_RX_BIG_PK_OK; + break; + case SK_BIG_PK_OK_OFF: + RxCmd &= ~XM_RX_BIG_PK_OK; + break; + } + + switch (Mode & (SK_SELF_RX_ON | SK_SELF_RX_OFF)) { + case SK_SELF_RX_ON: + RxCmd |= XM_RX_SELF_RX; + break; + case SK_SELF_RX_OFF: + RxCmd &= ~XM_RX_SELF_RX; + break; + } + + /* Write the new mode to the Rx command register if required */ + if (OldRxCmd != RxCmd) { + XM_OUT16(IoC, Port, XM_RX_CMD, RxCmd); + } +} /* SkXmSetRxCmd */ + + +/****************************************************************************** + * + * SkGmSetRxCmd() - Modify the value of the GMAC's Rx Control Register + * + * Description: + * The features + * - FCS (CRC) stripping, SK_STRIP_FCS_ON/OFF + * - don't set GMR_FS_LONG_ERR SK_BIG_PK_OK_ON/OFF + * for frames > 1514 bytes + * - enable Rx of own packets SK_SELF_RX_ON/OFF + * + * for incoming packets may be enabled/disabled by this function. + * Additional modes may be added later. + * Multiple modes can be enabled/disabled at the same time. + * The new configuration is written to the Rx Command register immediately. + * + * Returns: + * nothing + */ +static void SkGmSetRxCmd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, + SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */ +{ + SK_U16 OldRxCmd; + SK_U16 RxCmd; + + if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) { + + GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd); + + RxCmd = OldRxCmd; + + if ((Mode & SK_STRIP_FCS_ON) != 0) { + RxCmd |= GM_RXCR_CRC_DIS; + } + else { + RxCmd &= ~GM_RXCR_CRC_DIS; + } + /* Write the new mode to the Rx control register if required */ + if (OldRxCmd != RxCmd) { + GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd); + } + } + + if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) { + + GM_IN16(IoC, Port, GM_SERIAL_MODE, &OldRxCmd); + + RxCmd = OldRxCmd; + + if ((Mode & SK_BIG_PK_OK_ON) != 0) { + RxCmd |= GM_SMOD_JUMBO_ENA; + } + else { + RxCmd &= ~GM_SMOD_JUMBO_ENA; + } + /* Write the new mode to the Rx control register if required */ + if (OldRxCmd != RxCmd) { + GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd); + } + } +} /* SkGmSetRxCmd */ + + +/****************************************************************************** + * + * SkMacSetRxCmd() - Modify the value of the MAC's Rx Control Register + * + * Description: modifies the MAC's Rx Control reg. dep. on board type + * + * Returns: + * nothing + */ +void SkMacSetRxCmd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Mode) /* Rx Mode */ +{ + if (pAC->GIni.GIGenesis) { + + SkXmSetRxCmd(pAC, IoC, Port, Mode); + } + else { + + SkGmSetRxCmd(pAC, IoC, Port, Mode); + } +} /* SkMacSetRxCmd */ + + +/****************************************************************************** + * + * SkMacCrcGener() - Enable / Disable CRC Generation + * + * Description: enables / disables CRC generation dep. on board type + * + * Returns: + * nothing + */ +void SkMacCrcGener( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U16 Word; + + if (pAC->GIni.GIGenesis) { + + XM_IN16(IoC, Port, XM_TX_CMD, &Word); + + if (Enable) { + Word &= ~XM_TX_NO_CRC; + } + else { + Word |= XM_TX_NO_CRC; + } + /* setup Tx Command Register */ + XM_OUT16(pAC, Port, XM_TX_CMD, Word); + } + else { + + GM_IN16(IoC, Port, GM_TX_CTRL, &Word); + + if (Enable) { + Word &= ~GM_TXCR_CRC_DIS; + } + else { + Word |= GM_TXCR_CRC_DIS; + } + /* setup Tx Control Register */ + GM_OUT16(IoC, Port, GM_TX_CTRL, Word); + } +} /* SkMacCrcGener*/ + +#endif /* SK_DIAG */ + + +/****************************************************************************** + * + * SkXmClrExactAddr() - Clear Exact Match Address Registers + * + * Description: + * All Exact Match Address registers of the XMAC 'Port' will be + * cleared starting with 'StartNum' up to (and including) the + * Exact Match address number of 'StopNum'. + * + * Returns: + * nothing + */ +void SkXmClrExactAddr( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int StartNum, /* Begin with this Address Register Index (0..15) */ +int StopNum) /* Stop after finished with this Register Idx (0..15) */ +{ + int i; + SK_U16 ZeroAddr[3] = {0x0000, 0x0000, 0x0000}; + + if ((unsigned)StartNum > 15 || (unsigned)StopNum > 15 || + StartNum > StopNum) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E001, SKERR_HWI_E001MSG); + return; + } + + for (i = StartNum; i <= StopNum; i++) { + XM_OUTADDR(IoC, Port, XM_EXM(i), &ZeroAddr[0]); + } +} /* SkXmClrExactAddr */ + + +/****************************************************************************** + * + * SkMacFlushTxFifo() - Flush the MAC's transmit FIFO + * + * Description: + * Flush the transmit FIFO of the MAC specified by the index 'Port' + * + * Returns: + * nothing + */ +void SkMacFlushTxFifo( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U32 MdReg; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + + XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF); + } + else { + /* no way to flush the FIFO we have to issue a reset */ + /* TBD */ + } +} /* SkMacFlushTxFifo */ + + +/****************************************************************************** + * + * SkMacFlushRxFifo() - Flush the MAC's receive FIFO + * + * Description: + * Flush the receive FIFO of the MAC specified by the index 'Port' + * + * Returns: + * nothing + */ +void SkMacFlushRxFifo( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U32 MdReg; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + + XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FRF); + } + else { + /* no way to flush the FIFO we have to issue a reset */ + /* TBD */ + } +} /* SkMacFlushRxFifo */ + + +/****************************************************************************** + * + * SkXmSoftRst() - Do a XMAC software reset + * + * Description: + * The PHY registers should not be destroyed during this + * kind of software reset. Therefore the XMAC Software Reset + * (XM_GP_RES_MAC bit in XM_GP_PORT) must not be used! + * + * The software reset is done by + * - disabling the Rx and Tx state machine, + * - resetting the statistics module, + * - clear all other significant XMAC Mode, + * Command, and Control Registers + * - clearing the Hash Register and the + * Exact Match Address registers, and + * - flushing the XMAC's Rx and Tx FIFOs. + * + * Note: + * Another requirement when stopping the XMAC is to + * avoid sending corrupted frames on the network. + * Disabling the Tx state machine will NOT interrupt + * the currently transmitted frame. But we must take care + * that the Tx FIFO is cleared AFTER the current frame + * is complete sent to the network. + * + * It takes about 12ns to send a frame with 1538 bytes. + * One PCI clock goes at least 15ns (66MHz). Therefore + * after reading XM_GP_PORT back, we are sure that the + * transmitter is disabled AND idle. And this means + * we may flush the transmit FIFO now. + * + * Returns: + * nothing + */ +static void SkXmSoftRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 ZeroAddr[4] = {0x0000, 0x0000, 0x0000, 0x0000}; + + /* reset the statistics module */ + XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT); + + /* disable all XMAC IRQs */ + XM_OUT16(IoC, Port, XM_IMSK, 0xffff); + + XM_OUT32(IoC, Port, XM_MODE, 0); /* clear Mode Reg */ + + XM_OUT16(IoC, Port, XM_TX_CMD, 0); /* reset TX CMD Reg */ + XM_OUT16(IoC, Port, XM_RX_CMD, 0); /* reset RX CMD Reg */ + + /* disable all PHY IRQs */ + switch (pAC->GIni.GP[Port].PhyType) { + case SK_PHY_BCOM: + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, 0xffff); + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_INT_ENAB, 0); + break; + case SK_PHY_NAT: + /* todo: National + SkXmPhyWrite(pAC, IoC, Port, PHY_NAT_INT_MASK, 0xffff); */ + break; +#endif /* OTHER_PHY */ + } + + /* clear the Hash Register */ + XM_OUTHASH(IoC, Port, XM_HSM, &ZeroAddr); + + /* clear the Exact Match Address registers */ + SkXmClrExactAddr(pAC, IoC, Port, 0, 15); + + /* clear the Source Check Address registers */ + XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr); + +} /* SkXmSoftRst */ + + +/****************************************************************************** + * + * SkXmHardRst() - Do a XMAC hardware reset + * + * Description: + * The XMAC of the specified 'Port' and all connected devices + * (PHY and SERDES) will receive a reset signal on its *Reset pins. + * External PHYs must be reset be clearing a bit in the GPIO register + * (Timing requirements: Broadcom: 400ns, Level One: none, National: 80ns). + * + * ATTENTION: + * It is absolutely necessary to reset the SW_RST Bit first + * before calling this function. + * + * Returns: + * nothing + */ +static void SkXmHardRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U32 Reg; + int i; + int TOut; + SK_U16 Word; + + for (i = 0; i < 4; i++) { + /* TX_MFF_CTRL1 has 32 bits, but only the lowest 16 bits are used */ + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); + + TOut = 0; + do { + if (TOut++ > 10000) { + /* + * Adapter seems to be in RESET state. + * Registers cannot be written. + */ + return; + } + + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_SET_MAC_RST); + + SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &Word); + + } while ((Word & MFF_SET_MAC_RST) == 0); + } + + /* For external PHYs there must be special handling */ + if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) { + /* reset external PHY */ + SK_IN32(IoC, B2_GP_IO, &Reg); + if (Port == 0) { + Reg |= GP_DIR_0; /* set to output */ + Reg &= ~GP_IO_0; + } + else { + Reg |= GP_DIR_2; /* set to output */ + Reg &= ~GP_IO_2; + } + SK_OUT32(IoC, B2_GP_IO, Reg); + + /* short delay */ + SK_IN32(IoC, B2_GP_IO, &Reg); + } + +} /* SkXmHardRst */ + + +/****************************************************************************** + * + * SkGmSoftRst() - Do a GMAC software reset + * + * Description: + * The GPHY registers should not be destroyed during this + * kind of software reset. + * + * Returns: + * nothing + */ +static void SkGmSoftRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 EmptyHash[4] = {0x0000, 0x0000, 0x0000, 0x0000}; + SK_U16 RxCtrl; + + /* reset the statistics module */ + + /* disable all GMAC IRQs */ + SK_OUT8(IoC, GMAC_IRQ_MSK, 0); + + /* disable all PHY IRQs */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0); + + /* clear the Hash Register */ + GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash); + + /* Enable Unicast and Multicast filtering */ + GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl); + + GM_OUT16(IoC, Port, GM_RX_CTRL, + RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); + +} /* SkGmSoftRst */ + + +/****************************************************************************** + * + * SkGmHardRst() - Do a GMAC hardware reset + * + * Description: + * + * ATTENTION: + * It is absolutely necessary to reset the SW_RST Bit first + * before calling this function. + * + * Returns: + * nothing + */ +static void SkGmHardRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + /* set GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET); + + /* set GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET); + +} /* SkGmHardRst */ + + +/****************************************************************************** + * + * SkMacSoftRst() - Do a MAC software reset + * + * Description: calls a MAC software reset routine dep. on board type + * + * Returns: + * nothing + */ +void SkMacSoftRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + /* disable receiver and transmitter */ + SkMacRxTxDisable(pAC, IoC, Port); + + if (pAC->GIni.GIGenesis) { + + SkXmSoftRst(pAC, IoC, Port); + } + else { + + SkGmSoftRst(pAC, IoC, Port); + } + + /* flush the MAC's Rx and Tx FIFOs */ + SkMacFlushTxFifo(pAC, IoC, Port); + + SkMacFlushRxFifo(pAC, IoC, Port); + + pPrt->PState = SK_PRT_STOP; + +} /* SkMacSoftRst */ + + +/****************************************************************************** + * + * SkMacHardRst() - Do a MAC hardware reset + * + * Description: calls a MAC hardware reset routine dep. on board type + * + * Returns: + * nothing + */ +void SkMacHardRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + + if (pAC->GIni.GIGenesis) { + + SkXmHardRst(pAC, IoC, Port); + } + else { + + SkGmHardRst(pAC, IoC, Port); + } + + pAC->GIni.GP[Port].PState = SK_PRT_RESET; + +} /* SkMacHardRst */ + + +/****************************************************************************** + * + * SkXmInitMac() - Initialize the XMAC II + * + * Description: + * Initialize the XMAC of the specified port. + * The XMAC must be reset or stopped before calling this function. + * + * Note: + * The XMAC's Rx and Tx state machine is still disabled when returning. + * + * Returns: + * nothing + */ +void SkXmInitMac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U32 Reg; + int i; + SK_U16 SWord; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PState == SK_PRT_STOP) { + /* Port State: SK_PRT_STOP */ + /* Verify that the reset bit is cleared */ + SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord); + + if ((SWord & MFF_SET_MAC_RST) != 0) { + /* PState does not match HW state */ + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG); + /* Correct it */ + pPrt->PState = SK_PRT_RESET; + } + } + + if (pPrt->PState == SK_PRT_RESET) { + /* + * clear HW reset + * Note: The SW reset is self clearing, therefore there is + * nothing to do here. + */ + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); + + /* Ensure that XMAC reset release is done (errata from LReinbold?) */ + SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord); + + /* Clear PHY reset */ + if (pPrt->PhyType != SK_PHY_XMAC) { + + SK_IN32(IoC, B2_GP_IO, &Reg); + + if (Port == 0) { + Reg |= (GP_DIR_0 | GP_IO_0); /* set to output */ + } + else { + Reg |= (GP_DIR_2 | GP_IO_2); /* set to output */ + } + SK_OUT32(IoC, B2_GP_IO, Reg); + + /* Enable GMII interface */ + XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD); + + /* read Id from external PHY (all have the same address) */ + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_ID1, &pPrt->PhyId1); + + /* + * Optimize MDIO transfer by suppressing preamble. + * Must be done AFTER first access to BCOM chip. + */ + XM_IN16(IoC, Port, XM_MMU_CMD, &SWord); + + XM_OUT16(IoC, Port, XM_MMU_CMD, SWord | XM_MMU_NO_PRE); + + if (pPrt->PhyId1 == PHY_BCOM_ID1_C0) { + /* + * Workaround BCOM Errata for the C0 type. + * Write magic patterns to reserved registers. + */ + i = 0; + while (BcomRegC0Hack[i].PhyReg != 0) { + SkXmPhyWrite(pAC, IoC, Port, BcomRegC0Hack[i].PhyReg, + BcomRegC0Hack[i].PhyVal); + i++; + } + } + else if (pPrt->PhyId1 == PHY_BCOM_ID1_A1) { + /* + * Workaround BCOM Errata for the A1 type. + * Write magic patterns to reserved registers. + */ + i = 0; + while (BcomRegA1Hack[i].PhyReg != 0) { + SkXmPhyWrite(pAC, IoC, Port, BcomRegA1Hack[i].PhyReg, + BcomRegA1Hack[i].PhyVal); + i++; + } + } + + /* + * Workaround BCOM Errata (#10523) for all BCom PHYs. + * Disable Power Management after reset. + */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord); + + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, + (SK_U16)(SWord | PHY_B_AC_DIS_PM)); + + /* PHY LED initialization is done in SkGeXmitLED() */ + } + + /* Dummy read the Interrupt source register */ + XM_IN16(IoC, Port, XM_ISRC, &SWord); + + /* + * The auto-negotiation process starts immediately after + * clearing the reset. The auto-negotiation process should be + * started by the SIRQ, therefore stop it here immediately. + */ + SkMacInitPhy(pAC, IoC, Port, SK_FALSE); + +#if 0 + /* temp. code: enable signal detect */ + /* WARNING: do not override GMII setting above */ + XM_OUT16(pAC, Port, XM_HW_CFG, XM_HW_COM4SIG); +#endif + } + + /* + * configure the XMACs Station Address + * B2_MAC_2 = xx xx xx xx xx x1 is programmed to XMAC A + * B2_MAC_3 = xx xx xx xx xx x2 is programmed to XMAC B + */ + for (i = 0; i < 3; i++) { + /* + * The following 2 statements are together endianess + * independent. Remember this when changing. + */ + SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord); + + XM_OUT16(IoC, Port, (XM_SA + i * 2), SWord); + } + + /* Tx Inter Packet Gap (XM_TX_IPG): use default */ + /* Tx High Water Mark (XM_TX_HI_WM): use default */ + /* Tx Low Water Mark (XM_TX_LO_WM): use default */ + /* Host Request Threshold (XM_HT_THR): use default */ + /* Rx Request Threshold (XM_RX_THR): use default */ + /* Rx Low Water Mark (XM_RX_LO_WM): use default */ + + /* configure Rx High Water Mark (XM_RX_HI_WM) */ + XM_OUT16(IoC, Port, XM_RX_HI_WM, SK_XM_RX_HI_WM); + + /* Configure Tx Request Threshold */ + SWord = SK_XM_THR_SL; /* for single port */ + + if (pAC->GIni.GIMacsFound > 1) { + switch (pAC->GIni.GIPortUsage) { + case SK_RED_LINK: + SWord = SK_XM_THR_REDL; /* redundant link */ + break; + case SK_MUL_LINK: + SWord = SK_XM_THR_MULL; /* load balancing */ + break; + case SK_JUMBO_LINK: + SWord = SK_XM_THR_JUMBO; /* jumbo frames */ + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E014, SKERR_HWI_E014MSG); + break; + } + } + XM_OUT16(IoC, Port, XM_TX_THR, SWord); + + /* setup register defaults for the Tx Command Register */ + XM_OUT16(IoC, Port, XM_TX_CMD, XM_TX_AUTO_PAD); + + /* setup register defaults for the Rx Command Register */ + SWord = XM_RX_STRIP_FCS | XM_RX_LENERR_OK; + + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + SWord |= XM_RX_BIG_PK_OK; + } + + if (pPrt->PLinkModeConf == SK_LMODE_HALF) { + /* + * If in manual half duplex mode the other side might be in + * full duplex mode, so ignore if a carrier extension is not seen + * on frames received + */ + SWord |= XM_RX_DIS_CEXT; + } + + XM_OUT16(IoC, Port, XM_RX_CMD, SWord); + + /* + * setup register defaults for the Mode Register + * - Don't strip error frames to avoid Store & Forward + * on the Rx side. + * - Enable 'Check Station Address' bit + * - Enable 'Check Address Array' bit + */ + XM_OUT32(IoC, Port, XM_MODE, XM_DEF_MODE); + + /* + * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) + * - Enable all bits excepting 'Octets Rx OK Low CntOv' + * and 'Octets Rx OK Hi Cnt Ov'. + */ + XM_OUT32(IoC, Port, XM_RX_EV_MSK, XMR_DEF_MSK); + + /* + * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) + * - Enable all bits excepting 'Octets Tx OK Low CntOv' + * and 'Octets Tx OK Hi Cnt Ov'. + */ + XM_OUT32(IoC, Port, XM_TX_EV_MSK, XMT_DEF_MSK); + + /* + * Do NOT init XMAC interrupt mask here. + * All interrupts remain disable until link comes up! + */ + + /* + * Any additional configuration changes may be done now. + * The last action is to enable the Rx and Tx state machine. + * This should be done after the auto-negotiation process + * has been completed successfully. + */ +} /* SkXmInitMac */ + +/****************************************************************************** + * + * SkGmInitMac() - Initialize the GMAC + * + * Description: + * Initialize the GMAC of the specified port. + * The GMAC must be reset or stopped before calling this function. + * + * Note: + * The GMAC's Rx and Tx state machine is still disabled when returning. + * + * Returns: + * nothing + */ +void SkGmInitMac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + int i; + SK_U16 SWord; + SK_U32 DWord; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PState == SK_PRT_STOP) { + /* Port State: SK_PRT_STOP */ + /* Verify that the reset bit is cleared */ + SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord); + + if ((DWord & GMC_RST_SET) != 0) { + /* PState does not match HW state */ + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG); + /* Correct it */ + pPrt->PState = SK_PRT_RESET; + } + } + + if (pPrt->PState == SK_PRT_RESET) { + /* set GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET); + + /* set GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET); + + /* clear GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_CLR); + + /* set GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET); + + /* set HWCFG_MODE */ + DWord = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | + GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE | + (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP : + GPC_HWCFG_GMII_FIB); + + /* set GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET); + + /* release GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR); + + /* clear GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); + + /* Dummy read the Interrupt source register */ + SK_IN16(IoC, GMAC_IRQ_SRC, &SWord); + +#ifndef VCPU + /* read Id from PHY */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1); + + SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE); +#endif /* VCPU */ + } + + (void)SkGmResetCounter(pAC, IoC, Port); + + SWord = 0; + + /* speed settings */ + switch (pPrt->PLinkSpeed) { + case SK_LSPEED_AUTO: + case SK_LSPEED_1000MBPS: + SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100; + break; + case SK_LSPEED_100MBPS: + SWord |= GM_GPCR_SPEED_100; + break; + case SK_LSPEED_10MBPS: + break; + } + + /* duplex settings */ + if (pPrt->PLinkMode != SK_LMODE_HALF) { + /* set full duplex */ + SWord |= GM_GPCR_DUP_FULL; + } + + /* flow control settings */ + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + /* disable auto-negotiation for flow-control */ + SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS; + break; + case SK_FLOW_MODE_LOC_SEND: + SWord |= GM_GPCR_FC_RX_DIS; + break; + case SK_FLOW_MODE_SYMMETRIC: + /* TBD */ + case SK_FLOW_MODE_SYM_OR_REM: + /* enable auto-negotiation for flow-control and */ + /* enable Rx and Tx of pause frames */ + break; + } + + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + /* disable auto-update for speed, duplex and flow-control */ + SWord |= GM_GPCR_AU_ALL_DIS; + } + + /* setup General Purpose Control Register */ + GM_OUT16(IoC, Port, GM_GP_CTRL, SWord); + + /* setup Transmit Control Register */ + GM_OUT16(IoC, Port, GM_TX_CTRL, GM_TXCR_COL_THR); + + /* setup Receive Control Register */ + GM_OUT16(IoC, Port, GM_RX_CTRL, GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | + GM_RXCR_CRC_DIS); + + /* setup Transmit Flow Control Register */ + GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff); + + /* setup Transmit Parameter Register */ +#ifdef VCPU + GM_IN16(IoC, Port, GM_TX_PARAM, &SWord); +#endif /* VCPU */ + + SWord = JAM_LEN_VAL(3) | JAM_IPG_VAL(11) | IPG_JAM_DATA(26); + + GM_OUT16(IoC, Port, GM_TX_PARAM, SWord); + + /* configure the Serial Mode Register */ +#ifdef VCPU + GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord); +#endif /* VCPU */ + + SWord = GM_SMOD_VLAN_ENA | IPG_VAL_FAST_ETH; + + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + /* enable jumbo mode (Max. Frame Length = 9018) */ + SWord |= GM_SMOD_JUMBO_ENA; + } + + GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord); + + /* + * configure the GMACs Station Addresses + * in PROM you can find our addresses at: + * B2_MAC_1 = xx xx xx xx xx x0 virtual address + * B2_MAC_2 = xx xx xx xx xx x1 is programmed to GMAC A + * B2_MAC_3 = xx xx xx xx xx x2 is reserved for DualPort + */ + + for (i = 0; i < 3; i++) { + /* + * The following 2 statements are together endianess + * independent. Remember this when changing. + */ + /* physical address: will be used for pause frames */ + SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord); + +#ifdef WA_DEV_16 + /* WA for deviation #16 */ + if (pAC->GIni.GIChipRev == 0) { + /* swap the address bytes */ + SWord = ((SWord & 0xff00) >> 8) | ((SWord & 0x00ff) << 8); + + /* write to register in reversed order */ + GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + (2 - i) * 4), SWord); + } + else { + GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord); + } +#else + GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord); +#endif /* WA_DEV_16 */ + + /* virtual address: will be used for data */ + SK_IN16(IoC, (B2_MAC_1 + Port * 8 + i * 2), &SWord); + + GM_OUT16(IoC, Port, (GM_SRC_ADDR_2L + i * 4), SWord); + + /* reset Multicast filtering Hash registers 1-3 */ + GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + 4*i, 0); + } + + /* reset Multicast filtering Hash register 4 */ + GM_OUT16(IoC, Port, GM_MC_ADDR_H4, 0); + + /* enable interrupt mask for counter overflows */ + GM_OUT16(IoC, Port, GM_TX_IRQ_MSK, 0); + GM_OUT16(IoC, Port, GM_RX_IRQ_MSK, 0); + GM_OUT16(IoC, Port, GM_TR_IRQ_MSK, 0); + + /* read General Purpose Status */ + GM_IN16(IoC, Port, GM_GP_STAT, &SWord); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("MAC Stat Reg=0x%04X\n", SWord)); + +#ifdef SK_DIAG + c_print("MAC Stat Reg=0x%04X\n", SWord); +#endif /* SK_DIAG */ + +} /* SkGmInitMac */ + + +/****************************************************************************** + * + * SkXmInitDupMd() - Initialize the XMACs Duplex Mode + * + * Description: + * This function initializes the XMACs Duplex Mode. + * It should be called after successfully finishing + * the Auto-negotiation Process + * + * Returns: + * nothing + */ +void SkXmInitDupMd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + switch (pAC->GIni.GP[Port].PLinkModeStatus) { + case SK_LMODE_STAT_AUTOHALF: + case SK_LMODE_STAT_HALF: + /* Configuration Actions for Half Duplex Mode */ + /* + * XM_BURST = default value. We are probable not quick + * enough at the 'XMAC' bus to burst 8kB. + * The XMAC stops bursting if no transmit frames + * are available or the burst limit is exceeded. + */ + /* XM_TX_RT_LIM = default value (15) */ + /* XM_TX_STIME = default value (0xff = 4096 bit times) */ + break; + case SK_LMODE_STAT_AUTOFULL: + case SK_LMODE_STAT_FULL: + /* Configuration Actions for Full Duplex Mode */ + /* + * The duplex mode is configured by the PHY, + * therefore it seems to be that there is nothing + * to do here. + */ + break; + case SK_LMODE_STAT_UNKNOWN: + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E007, SKERR_HWI_E007MSG); + break; + } +} /* SkXmInitDupMd */ + + +/****************************************************************************** + * + * SkXmInitPauseMd() - initialize the Pause Mode to be used for this port + * + * Description: + * This function initializes the Pause Mode which should + * be used for this port. + * It should be called after successfully finishing + * the Auto-negotiation Process + * + * Returns: + * nothing + */ +void SkXmInitPauseMd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U32 DWord; + SK_U16 Word; + + pPrt = &pAC->GIni.GP[Port]; + + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + + if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE || + pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) { + + /* Disable Pause Frame Reception */ + Word |= XM_MMU_IGN_PF; + } + else { + /* + * enabling pause frame reception is required for 1000BT + * because the XMAC is not reset if the link is going down + */ + /* Enable Pause Frame Reception */ + Word &= ~XM_MMU_IGN_PF; + } + + XM_OUT16(IoC, Port, XM_MMU_CMD, Word); + + XM_IN32(IoC, Port, XM_MODE, &DWord); + + if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_SYMMETRIC || + pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) { + + /* + * Configure Pause Frame Generation + * Use internal and external Pause Frame Generation. + * Sending pause frames is edge triggered. + * Send a Pause frame with the maximum pause time if + * internal oder external FIFO full condition occurs. + * Send a zero pause time frame to re-start transmission. + */ + + /* XM_PAUSE_DA = '010000C28001' (default) */ + + /* XM_MAC_PTIME = 0xffff (maximum) */ + /* remember this value is defined in big endian (!) */ + XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff); + + /* Set Pause Mode in Mode Register */ + DWord |= XM_PAUSE_MODE; + + /* Set Pause Mode in MAC Rx FIFO */ + SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_PAUSE); + } + else { + /* + * disable pause frame generation is required for 1000BT + * because the XMAC is not reset if the link is going down + */ + /* Disable Pause Mode in Mode Register */ + DWord &= ~XM_PAUSE_MODE; + + /* Disable Pause Mode in MAC Rx FIFO */ + SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE); + } + + XM_OUT32(IoC, Port, XM_MODE, DWord); +} /* SkXmInitPauseMd*/ + + +/****************************************************************************** + * + * SkXmInitPhyXmac() - Initialize the XMAC Phy registers + * + * Description: initializes all the XMACs Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkXmInitPhyXmac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + SK_U16 Ctrl; + + pPrt = &pAC->GIni.GP[Port]; + Ctrl = 0; + + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyXmac: no auto-negotiation Port %d\n", Port)); + /* Set DuplexMode in Config register */ + if (pPrt->PLinkMode == SK_LMODE_FULL) { + Ctrl |= PHY_CT_DUP_MD; + } + + /* + * Do NOT enable Auto-negotiation here. This would hold + * the link down because no IDLEs are transmitted + */ + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyXmac: with auto-negotiation Port %d\n", Port)); + /* Set Auto-negotiation advertisement */ + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + Ctrl |= PHY_X_AN_HD; + break; + case SK_LMODE_AUTOFULL: + Ctrl |= PHY_X_AN_FD; + break; + case SK_LMODE_AUTOBOTH: + Ctrl |= PHY_X_AN_FD | PHY_X_AN_HD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + Ctrl |= PHY_X_P_NO_PAUSE; + break; + case SK_FLOW_MODE_LOC_SEND: + Ctrl |= PHY_X_P_ASYM_MD; + break; + case SK_FLOW_MODE_SYMMETRIC: + Ctrl |= PHY_X_P_SYM_MD; + break; + case SK_FLOW_MODE_SYM_OR_REM: + Ctrl |= PHY_X_P_BOTH_MD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + + /* Write AutoNeg Advertisement Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_AUNE_ADV, Ctrl); + + /* Restart Auto-negotiation */ + Ctrl = PHY_CT_ANE | PHY_CT_RE_CFG; + } + + if (DoLoop) { + /* Set the Phy Loopback bit, too */ + Ctrl |= PHY_CT_LOOP; + } + + /* Write to the Phy control register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_CTRL, Ctrl); +} /* SkXmInitPhyXmac */ + + +/****************************************************************************** + * + * SkXmInitPhyBcom() - Initialize the Broadcom Phy registers + * + * Description: initializes all the Broadcom Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkXmInitPhyBcom( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + SK_U16 Ctrl1; + SK_U16 Ctrl2; + SK_U16 Ctrl3; + SK_U16 Ctrl4; + SK_U16 Ctrl5; + + Ctrl1 = PHY_CT_SP1000; + Ctrl2 = 0; + Ctrl3 = PHY_SEL_TYPE; + Ctrl4 = PHY_B_PEC_EN_LTR; + Ctrl5 = PHY_B_AC_TX_TST; + + pPrt = &pAC->GIni.GP[Port]; + + /* manually Master/Slave ? */ + if (pPrt->PMSMode != SK_MS_MODE_AUTO) { + Ctrl2 |= PHY_B_1000C_MSE; + + if (pPrt->PMSMode == SK_MS_MODE_MASTER) { + Ctrl2 |= PHY_B_1000C_MSC; + } + } + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyBcom: no auto-negotiation Port %d\n", Port)); + /* Set DuplexMode in Config register */ + Ctrl1 |= (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0); + + /* Determine Master/Slave manually if not already done */ + if (pPrt->PMSMode == SK_MS_MODE_AUTO) { + Ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */ + } + + /* + * Do NOT enable Auto-negotiation here. This would hold + * the link down because no IDLES are transmitted + */ + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyBcom: with auto-negotiation Port %d\n", Port)); + /* Set Auto-negotiation advertisement */ + + /* + * Workaround BCOM Errata #1 for the C5 type. + * 1000Base-T Link Acquisition Failure in Slave Mode + * Set Repeater/DTE bit 10 of the 1000Base-T Control Register + */ + Ctrl2 |= PHY_B_1000C_RD; + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + Ctrl2 |= PHY_B_1000C_AHD; + break; + case SK_LMODE_AUTOFULL: + Ctrl2 |= PHY_B_1000C_AFD; + break; + case SK_LMODE_AUTOBOTH: + Ctrl2 |= PHY_B_1000C_AFD | PHY_B_1000C_AHD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + Ctrl3 |= PHY_B_P_NO_PAUSE; + break; + case SK_FLOW_MODE_LOC_SEND: + Ctrl3 |= PHY_B_P_ASYM_MD; + break; + case SK_FLOW_MODE_SYMMETRIC: + Ctrl3 |= PHY_B_P_SYM_MD; + break; + case SK_FLOW_MODE_SYM_OR_REM: + Ctrl3 |= PHY_B_P_BOTH_MD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + + /* Restart Auto-negotiation */ + Ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG; + } + + /* Initialize LED register here? */ + /* No. Please do it in SkDgXmitLed() (if required) and swap + init order of LEDs and XMAC. (MAl) */ + + /* Write 1000Base-T Control Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2)); + + /* Write AutoNeg Advertisement Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3)); + + if (DoLoop) { + /* Set the Phy Loopback bit, too */ + Ctrl1 |= PHY_CT_LOOP; + } + + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + /* configure FIFO to high latency for transmission of ext. packets */ + Ctrl4 |= PHY_B_PEC_HIGH_LA; + + /* configure reception of extended packets */ + Ctrl5 |= PHY_B_AC_LONG_PACK; + + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, Ctrl5); + } + + /* Configure LED Traffic Mode and Jumbo Frame usage if specified */ + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4); + + /* Write to the Phy control register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Control Reg=0x%04X\n", Ctrl1)); +} /* SkXmInitPhyBcom */ + + +/****************************************************************************** + * + * SkGmInitPhyMarv() - Initialize the Marvell Phy registers + * + * Description: initializes all the Marvell Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkGmInitPhyMarv( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + SK_U16 PhyCtrl; + SK_U16 C1000BaseT; + SK_U16 AutoNegAdv; + SK_U16 ExtPhyCtrl; + SK_U16 PhyStat; + SK_U16 PhyStat1; + SK_U16 PhySpecStat; + SK_U16 LedCtrl; + SK_BOOL AutoNeg; + +#ifdef VCPU + VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n", + Port, DoLoop); +#else /* VCPU */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + if (!DoLoop) { + /* Read Ext. PHY Specific Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl); + + ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | + PHY_M_EC_MAC_S_MSK); + + ExtPhyCtrl |= PHY_M_EC_M_DSC(1) | PHY_M_EC_S_DSC(1) | + PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Ext.PHYCtrl=0x%04X\n", ExtPhyCtrl)); + + /* Read PHY Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl); + + /* Assert software reset */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, + (SK_U16)(PhyCtrl | PHY_CT_RESET)); + } +#endif /* VCPU */ + + PhyCtrl = 0 /* PHY_CT_COL_TST */; + C1000BaseT = 0; + AutoNegAdv = PHY_SEL_TYPE; + + /* manually Master/Slave ? */ + if (pPrt->PMSMode != SK_MS_MODE_AUTO) { + /* enable Manual Master/Slave */ + C1000BaseT |= PHY_M_1000C_MSE; + + if (pPrt->PMSMode == SK_MS_MODE_MASTER) { + C1000BaseT |= PHY_M_1000C_MSC; /* set it to Master */ + } + } + + /* Auto-negotiation ? */ + if (!AutoNeg) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyMarv: no auto-negotiation Port %d\n", Port)); + + if (pPrt->PLinkMode == SK_LMODE_FULL) { + /* Set Full Duplex Mode */ + PhyCtrl |= PHY_CT_DUP_MD; + } + + /* Set Master/Slave manually if not already done */ + if (pPrt->PMSMode == SK_MS_MODE_AUTO) { + C1000BaseT |= PHY_M_1000C_MSE; /* set it to Slave */ + } + + /* Set Speed */ + switch (pPrt->PLinkSpeed) { + case SK_LSPEED_AUTO: + case SK_LSPEED_1000MBPS: + PhyCtrl |= PHY_CT_SP1000; + break; + case SK_LSPEED_100MBPS: + PhyCtrl |= PHY_CT_SP100; + break; + case SK_LSPEED_10MBPS: + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019, + SKERR_HWI_E019MSG); + } + + if (!DoLoop) { + PhyCtrl |= PHY_CT_RESET; + } + /* + * Do NOT enable Auto-negotiation here. This would hold + * the link down because no IDLES are transmitted + */ + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyMarv: with auto-negotiation Port %d\n", Port)); + + PhyCtrl |= PHY_CT_ANE; + + if (pAC->GIni.GICopperType) { + /* Set Speed capabilities */ + switch (pPrt->PLinkSpeed) { + case SK_LSPEED_AUTO: + C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD; + AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD | + PHY_M_AN_10_FD | PHY_M_AN_10_HD; + break; + case SK_LSPEED_1000MBPS: + C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD; + break; + case SK_LSPEED_100MBPS: + AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD | + PHY_M_AN_10_FD | PHY_M_AN_10_HD; + break; + case SK_LSPEED_10MBPS: + AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019, + SKERR_HWI_E019MSG); + } + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + C1000BaseT &= ~PHY_M_1000C_AFD; + AutoNegAdv &= ~(PHY_M_AN_100_FD | PHY_M_AN_10_FD); + break; + case SK_LMODE_AUTOFULL: + C1000BaseT &= ~PHY_M_1000C_AHD; + AutoNegAdv &= ~(PHY_M_AN_100_HD | PHY_M_AN_10_HD); + break; + case SK_LMODE_AUTOBOTH: + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + /* Set Auto-negotiation advertisement */ + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + AutoNegAdv |= PHY_B_P_NO_PAUSE; + break; + case SK_FLOW_MODE_LOC_SEND: + AutoNegAdv |= PHY_B_P_ASYM_MD; + break; + case SK_FLOW_MODE_SYMMETRIC: + AutoNegAdv |= PHY_B_P_SYM_MD; + break; + case SK_FLOW_MODE_SYM_OR_REM: + AutoNegAdv |= PHY_B_P_BOTH_MD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + } + else { /* special defines for FIBER (88E1011S only) */ + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + AutoNegAdv |= PHY_M_AN_1000X_AHD; + break; + case SK_LMODE_AUTOFULL: + AutoNegAdv |= PHY_M_AN_1000X_AFD; + break; + case SK_LMODE_AUTOBOTH: + AutoNegAdv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + /* Set Auto-negotiation advertisement */ + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + AutoNegAdv |= PHY_M_P_NO_PAUSE_X; + break; + case SK_FLOW_MODE_LOC_SEND: + AutoNegAdv |= PHY_M_P_ASYM_MD_X; + break; + case SK_FLOW_MODE_SYMMETRIC: + AutoNegAdv |= PHY_M_P_SYM_MD_X; + break; + case SK_FLOW_MODE_SYM_OR_REM: + AutoNegAdv |= PHY_M_P_BOTH_MD_X; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + } + + if (!DoLoop) { + /* Restart Auto-negotiation */ + PhyCtrl |= PHY_CT_RE_CFG; + } + } + +#ifdef VCPU + /* + * E-mail from Gu Lin (08-03-2002): + */ + + /* Program PHY register 30 as 16'h0708 for simulation speed up */ + SkGmPhyWrite(pAC, IoC, Port, 30, 0x0708); + + VCpuWait(2000); + +#else /* VCPU */ + + /* Write 1000Base-T Control Register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("1000B-T Ctrl=0x%04X\n", C1000BaseT)); + + /* Write AutoNeg Advertisement Register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Neg.Ad.=0x%04X\n", AutoNegAdv)); +#endif /* VCPU */ + + if (DoLoop) { + /* Set the PHY Loopback bit */ + PhyCtrl |= PHY_CT_LOOP; + + /* Program PHY register 16 as 16'h0400 to force link good */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_FL_GOOD); + +#if 0 + if (pPrt->PLinkSpeed != SK_LSPEED_AUTO) { + /* Write Ext. PHY Specific Control */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, + (SK_U16)((pPrt->PLinkSpeed + 2) << 4)); + } + } + else if (pPrt->PLinkSpeed == SK_LSPEED_10MBPS) { + /* Write PHY Specific Control */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_EN_DET_MSK); + } +#endif /* 0 */ + } + + /* Write to the PHY Control register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl); + +#ifdef VCPU + VCpuWait(2000); +#else + + LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS) | PHY_M_LED_BLINK_RT(BLINK_84MS); + +#ifdef ACT_LED_BLINK + LedCtrl |= PHY_M_LEDC_RX_CTRL | PHY_M_LEDC_TX_CTRL; +#endif /* ACT_LED_BLINK */ + +#ifdef DUP_LED_NORMAL + LedCtrl |= PHY_M_LEDC_DP_CTRL; +#endif /* DUP_LED_NORMAL */ + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl); + +#endif /* VCPU */ + +#ifdef SK_DIAG + c_print("Set PHY Ctrl=0x%04X\n", PhyCtrl); + c_print("Set 1000 B-T=0x%04X\n", C1000BaseT); + c_print("Set Auto-Neg=0x%04X\n", AutoNegAdv); + c_print("Set Ext Ctrl=0x%04X\n", ExtPhyCtrl); +#endif /* SK_DIAG */ + +#ifndef xDEBUG + /* Read PHY Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Ctrl Reg.=0x%04X\n", PhyCtrl)); + + /* Read 1000Base-T Control Register */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("1000B-T Ctrl =0x%04X\n", C1000BaseT)); + + /* Read AutoNeg Advertisement Register */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Neg. Ad.=0x%04X\n", AutoNegAdv)); + + /* Read Ext. PHY Specific Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Ext PHY Ctrl=0x%04X\n", ExtPhyCtrl)); + + /* Read PHY Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Stat Reg.=0x%04X\n", PhyStat)); + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Stat Reg.=0x%04X\n", PhyStat1)); + + /* Read PHY Specific Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Spec Stat=0x%04X\n", PhySpecStat)); +#endif /* DEBUG */ + +#ifdef SK_DIAG + c_print("PHY Ctrl Reg=0x%04X\n", PhyCtrl); + c_print("PHY 1000 Reg=0x%04X\n", C1000BaseT); + c_print("PHY AnAd Reg=0x%04X\n", AutoNegAdv); + c_print("Ext Ctrl Reg=0x%04X\n", ExtPhyCtrl); + c_print("PHY Stat Reg=0x%04X\n", PhyStat); + c_print("PHY Stat Reg=0x%04X\n", PhyStat1); + c_print("PHY Spec Reg=0x%04X\n", PhySpecStat); +#endif /* SK_DIAG */ + +} /* SkGmInitPhyMarv */ + + +#ifdef OTHER_PHY +/****************************************************************************** + * + * SkXmInitPhyLone() - Initialize the Level One Phy registers + * + * Description: initializes all the Level One Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkXmInitPhyLone( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + SK_U16 Ctrl1; + SK_U16 Ctrl2; + SK_U16 Ctrl3; + + Ctrl1 = PHY_CT_SP1000; + Ctrl2 = 0; + Ctrl3 = PHY_SEL_TYPE; + + pPrt = &pAC->GIni.GP[Port]; + + /* manually Master/Slave ? */ + if (pPrt->PMSMode != SK_MS_MODE_AUTO) { + Ctrl2 |= PHY_L_1000C_MSE; + + if (pPrt->PMSMode == SK_MS_MODE_MASTER) { + Ctrl2 |= PHY_L_1000C_MSC; + } + } + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + /* + * level one spec say: "1000Mbps: manual mode not allowed" + * but lets see what happens... + */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyLone: no auto-negotiation Port %d\n", Port)); + /* Set DuplexMode in Config register */ + Ctrl1 = (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0); + + /* Determine Master/Slave manually if not already done */ + if (pPrt->PMSMode == SK_MS_MODE_AUTO) { + Ctrl2 |= PHY_L_1000C_MSE; /* set it to Slave */ + } + + /* + * Do NOT enable Auto-negotiation here. This would hold + * the link down because no IDLES are transmitted + */ + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyLone: with auto-negotiation Port %d\n", Port)); + /* Set Auto-negotiation advertisement */ + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + Ctrl2 |= PHY_L_1000C_AHD; + break; + case SK_LMODE_AUTOFULL: + Ctrl2 |= PHY_L_1000C_AFD; + break; + case SK_LMODE_AUTOBOTH: + Ctrl2 |= PHY_L_1000C_AFD | PHY_L_1000C_AHD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + Ctrl3 |= PHY_L_P_NO_PAUSE; + break; + case SK_FLOW_MODE_LOC_SEND: + Ctrl3 |= PHY_L_P_ASYM_MD; + break; + case SK_FLOW_MODE_SYMMETRIC: + Ctrl3 |= PHY_L_P_SYM_MD; + break; + case SK_FLOW_MODE_SYM_OR_REM: + Ctrl3 |= PHY_L_P_BOTH_MD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + + /* Restart Auto-negotiation */ + Ctrl1 = PHY_CT_ANE | PHY_CT_RE_CFG; + + } + + /* Initialize LED register here ? */ + /* No. Please do it in SkDgXmitLed() (if required) and swap + init order of LEDs and XMAC. (MAl) */ + + /* Write 1000Base-T Control Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_1000T_CTRL, Ctrl2); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2)); + + /* Write AutoNeg Advertisement Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_AUNE_ADV, Ctrl3); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3)); + + + if (DoLoop) { + /* Set the Phy Loopback bit, too */ + Ctrl1 |= PHY_CT_LOOP; + } + + /* Write to the Phy control register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_CTRL, Ctrl1); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Control Reg=0x%04X\n", Ctrl1)); +} /* SkXmInitPhyLone */ + + +/****************************************************************************** + * + * SkXmInitPhyNat() - Initialize the National Phy registers + * + * Description: initializes all the National Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkXmInitPhyNat( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ +/* todo: National */ +} /* SkXmInitPhyNat */ +#endif /* OTHER_PHY */ + + +/****************************************************************************** + * + * SkMacInitPhy() - Initialize the PHY registers + * + * Description: calls the Init PHY routines dep. on board type + * + * Note: + * + * Returns: + * nothing + */ +void SkMacInitPhy( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + switch (pPrt->PhyType) { + case SK_PHY_XMAC: + SkXmInitPhyXmac(pAC, IoC, Port, DoLoop); + break; + case SK_PHY_BCOM: + SkXmInitPhyBcom(pAC, IoC, Port, DoLoop); + break; + case SK_PHY_MARV_COPPER: + case SK_PHY_MARV_FIBER: + SkGmInitPhyMarv(pAC, IoC, Port, DoLoop); + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmInitPhyLone(pAC, IoC, Port, DoLoop); + break; + case SK_PHY_NAT: + SkXmInitPhyNat(pAC, IoC, Port, DoLoop); + break; +#endif /* OTHER_PHY */ + } +} /* SkMacInitPhy */ + + +#ifndef SK_DIAG +/****************************************************************************** + * + * SkXmAutoNegLipaXmac() - Decides whether Link Partner could do auto-neg + * + * This function analyses the Interrupt status word. If any of the + * Auto-negotiating interrupt bits are set, the PLipaAutoNeg variable + * is set true. + */ +void SkXmAutoNegLipaXmac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U16 IStatus) /* Interrupt Status word to analyse */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO && + (IStatus & (XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND)) != 0) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegLipa: AutoNeg detected on Port %d, IStatus=0x%04x\n", + Port, IStatus)); + pPrt->PLipaAutoNeg = SK_LIPA_AUTO; + } +} /* SkXmAutoNegLipaXmac */ + + +/****************************************************************************** + * + * SkMacAutoNegLipaPhy() - Decides whether Link Partner could do auto-neg + * + * This function analyses the PHY status word. + * If any of the Auto-negotiating bits are set, the PLipaAutoNeg variable + * is set true. + */ +void SkMacAutoNegLipaPhy( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U16 PhyStat) /* PHY Status word to analyse */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO && + (PhyStat & PHY_ST_AN_OVER) != 0) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat=0x%04x\n", + Port, PhyStat)); + pPrt->PLipaAutoNeg = SK_LIPA_AUTO; + } +} /* SkMacAutoNegLipaPhy */ +#endif /* SK_DIAG */ + + +/****************************************************************************** + * + * SkXmAutoNegDoneXmac() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkXmAutoNegDoneXmac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 ResAb; /* Resolved Ability */ + SK_U16 LPAb; /* Link Partner Ability */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegDoneXmac, Port %d\n",Port)); + + pPrt = &pAC->GIni.GP[Port]; + + /* Get PHY parameters */ + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LPAb); + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb); + + if ((LPAb & PHY_X_AN_RFB) != 0) { + /* At least one of the remote fault bit is set */ + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Remote fault bit set Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); + } + + /* Check Duplex mismatch */ + if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_FD) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + } + else if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_HD) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + } + else { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Duplex mode mismatch Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_DUP_CAP); + } + + /* Check PAUSE mismatch */ + /* We are NOT using chapter 4.23 of the Xaqti manual */ + /* We are using IEEE 802.3z/D5.0 Table 37-4 */ + if ((pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC || + pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) && + (LPAb & PHY_X_P_SYM_MD) != 0) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM && + (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) { + /* Enable PAUSE receive, disable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; + } + else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND && + (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) { + /* Disable PAUSE receive, enable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; + } + else { + /* PAUSE mismatch -> no PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + } + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + + return(SK_AND_OK); +} /* SkXmAutoNegDoneXmac */ + + +/****************************************************************************** + * + * SkXmAutoNegDoneBcom() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkXmAutoNegDoneBcom( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 LPAb; /* Link Partner Ability */ + SK_U16 AuxStat; /* Auxiliary Status */ + +#if 0 +01-Sep-2000 RA;:;: + SK_U16 ResAb; /* Resolved Ability */ +#endif /* 0 */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegDoneBcom, Port %d\n", Port)); + pPrt = &pAC->GIni.GP[Port]; + + /* Get PHY parameters */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LPAb); +#if 0 +01-Sep-2000 RA;:;: + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb); +#endif /* 0 */ + + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &AuxStat); + + if ((LPAb & PHY_B_AN_RF) != 0) { + /* Remote fault bit is set: Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Remote fault bit set Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); + } + + /* Check Duplex mismatch */ + if ((AuxStat & PHY_B_AS_AN_RES_MSK) == PHY_B_RES_1000FD) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + } + else if ((AuxStat & PHY_B_AS_AN_RES_MSK) == PHY_B_RES_1000HD) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + } + else { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Duplex mode mismatch Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_DUP_CAP); + } + +#if 0 +01-Sep-2000 RA;:;: + /* Check Master/Slave resolution */ + if ((ResAb & PHY_B_1000S_MSF) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + return(SK_AND_OTHER); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; +#endif /* 0 */ + + /* Check PAUSE mismatch */ + /* We are using IEEE 802.3z/D5.0 Table 37-4 */ + if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PAUSE_MSK) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRR) { + /* Enable PAUSE receive, disable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; + } + else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRT) { + /* Disable PAUSE receive, enable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; + } + else { + /* PAUSE mismatch -> no PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + } + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + + return(SK_AND_OK); +} /* SkXmAutoNegDoneBcom */ + + +/****************************************************************************** + * + * SkGmAutoNegDoneMarv() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkGmAutoNegDoneMarv( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 LPAb; /* Link Partner Ability */ + SK_U16 ResAb; /* Resolved Ability */ + SK_U16 AuxStat; /* Auxiliary Status */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegDoneMarv, Port %d\n", Port)); + pPrt = &pAC->GIni.GP[Port]; + + /* Get PHY parameters */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LPAb); + + if ((LPAb & PHY_M_AN_RF) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Remote fault bit set Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); + } + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb); + + /* Check Master/Slave resolution */ + if ((ResAb & PHY_B_1000S_MSF) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + return(SK_AND_OTHER); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE; + + /* Read PHY Specific Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat); + + /* Check Speed & Duplex resolved */ + if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Speed & Duplex not resolved Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; + return(SK_AND_DUP_CAP); + } + + if ((AuxStat & PHY_M_PS_FULL_DUP) != 0) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + } + else { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + } + + /* Check PAUSE mismatch */ + /* We are using IEEE 802.3z/D5.0 Table 37-4 */ + if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_PAUSE_MSK) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_RX_P_EN) { + /* Enable PAUSE receive, disable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; + } + else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_TX_P_EN) { + /* Disable PAUSE receive, enable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; + } + else { + /* PAUSE mismatch -> no PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + } + + /* set used link speed */ + switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) { + case (unsigned)PHY_M_PS_SPEED_1000: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + break; + case PHY_M_PS_SPEED_100: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_100MBPS; + break; + default: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_10MBPS; + } + + return(SK_AND_OK); +} /* SkGmAutoNegDoneMarv */ + + +#ifdef OTHER_PHY +/****************************************************************************** + * + * SkXmAutoNegDoneLone() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkXmAutoNegDoneLone( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 ResAb; /* Resolved Ability */ + SK_U16 LPAb; /* Link Partner Ability */ + SK_U16 QuickStat; /* Auxiliary Status */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegDoneLone, Port %d\n",Port)); + pPrt = &pAC->GIni.GP[Port]; + + /* Get PHY parameters */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LPAb); + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ResAb); + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_Q_STAT, &QuickStat); + + if ((LPAb & PHY_L_AN_RF) != 0) { + /* Remote fault bit is set */ + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Remote fault bit set Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); + } + + /* Check Duplex mismatch */ + if ((QuickStat & PHY_L_QS_DUP_MOD) != 0) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + } + else { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + } + + /* Check Master/Slave resolution */ + if ((ResAb & PHY_L_1000S_MSF) != 0) { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + return(SK_AND_OTHER); + } + else if (ResAb & PHY_L_1000S_MSR) { + pPrt->PMSStatus = SK_MS_STAT_MASTER; + } + else { + pPrt->PMSStatus = SK_MS_STAT_SLAVE; + } + + /* Check PAUSE mismatch */ + /* We are using IEEE 802.3z/D5.0 Table 37-4 */ + /* we must manually resolve the abilities here */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + /* default */ + break; + case SK_FLOW_MODE_LOC_SEND: + if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) == + (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) { + /* Disable PAUSE receive, enable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; + } + break; + case SK_FLOW_MODE_SYMMETRIC: + if ((QuickStat & PHY_L_QS_PAUSE) != 0) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + break; + case SK_FLOW_MODE_SYM_OR_REM: + if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) == + PHY_L_QS_AS_PAUSE) { + /* Enable PAUSE receive, disable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; + } + else if ((QuickStat & PHY_L_QS_PAUSE) != 0) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + + return(SK_AND_OK); +} /* SkXmAutoNegDoneLone */ + + +/****************************************************************************** + * + * SkXmAutoNegDoneNat() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkXmAutoNegDoneNat( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ +/* todo: National */ + return(SK_AND_OK); +} /* SkXmAutoNegDoneNat */ +#endif /* OTHER_PHY */ + + +/****************************************************************************** + * + * SkMacAutoNegDone() - Auto-negotiation handling + * + * Description: calls the auto-negotiation done routines dep. on board type + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +int SkMacAutoNegDone( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + int Rtv; + + pPrt = &pAC->GIni.GP[Port]; + + switch (pPrt->PhyType) { + case SK_PHY_XMAC: + Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port); + break; + case SK_PHY_BCOM: + Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port); + break; + case SK_PHY_MARV_COPPER: + case SK_PHY_MARV_FIBER: + Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port); + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port); + break; + case SK_PHY_NAT: + Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port); + break; +#endif /* OTHER_PHY */ + default: + return(SK_AND_OTHER); + } + + if (Rtv != SK_AND_OK) { + return(Rtv); + } + + /* We checked everything and may now enable the link */ + pPrt->PAutoNegFail = SK_FALSE; + + SkMacRxTxEnable(pAC, IoC, Port); + + return(SK_AND_OK); +} /* SkMacAutoNegDone */ + + +/****************************************************************************** + * + * SkXmSetRxTxEn() - Special Set Rx/Tx Enable and some features in XMAC + * + * Description: + * sets MAC or PHY LoopBack and Duplex Mode in the MMU Command Reg. + * enables Rx/Tx + * + * Returns: N/A + */ +static void SkXmSetRxTxEn( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Para) /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */ +{ + SK_U16 Word; + + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + + switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) { + case SK_MAC_LOOPB_ON: + Word |= XM_MMU_MAC_LB; + break; + case SK_MAC_LOOPB_OFF: + Word &= ~XM_MMU_MAC_LB; + break; + } + + switch (Para & (SK_PHY_LOOPB_ON | SK_PHY_LOOPB_OFF)) { + case SK_PHY_LOOPB_ON: + Word |= XM_MMU_GMII_LOOP; + break; + case SK_PHY_LOOPB_OFF: + Word &= ~XM_MMU_GMII_LOOP; + break; + } + + switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) { + case SK_PHY_FULLD_ON: + Word |= XM_MMU_GMII_FD; + break; + case SK_PHY_FULLD_OFF: + Word &= ~XM_MMU_GMII_FD; + break; + } + + XM_OUT16(IoC, Port, XM_MMU_CMD, Word | XM_MMU_ENA_RX | XM_MMU_ENA_TX); + + /* dummy read to ensure writing */ + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + +} /* SkXmSetRxTxEn */ + + +/****************************************************************************** + * + * SkGmSetRxTxEn() - Special Set Rx/Tx Enable and some features in GMAC + * + * Description: + * sets MAC LoopBack and Duplex Mode in the General Purpose Control Reg. + * enables Rx/Tx + * + * Returns: N/A + */ +static void SkGmSetRxTxEn( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */ +{ + SK_U16 Ctrl; + + GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl); + + switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) { + case SK_MAC_LOOPB_ON: + Ctrl |= GM_GPCR_LOOP_ENA; + break; + case SK_MAC_LOOPB_OFF: + Ctrl &= ~GM_GPCR_LOOP_ENA; + break; + } + + switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) { + case SK_PHY_FULLD_ON: + Ctrl |= GM_GPCR_DUP_FULL; + break; + case SK_PHY_FULLD_OFF: + Ctrl &= ~GM_GPCR_DUP_FULL; + break; + } + + GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); + + /* dummy read to ensure writing */ + GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl); + +} /* SkGmSetRxTxEn */ + + +/****************************************************************************** + * + * SkMacSetRxTxEn() - Special Set Rx/Tx Enable and parameters + * + * Description: calls the Special Set Rx/Tx Enable routines dep. on board type + * + * Returns: N/A + */ +void SkMacSetRxTxEn( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Para) +{ + if (pAC->GIni.GIGenesis) { + + SkXmSetRxTxEn(pAC, IoC, Port, Para); + } + else { + + SkGmSetRxTxEn(pAC, IoC, Port, Para); + } + +} /* SkMacSetRxTxEn */ + + +/****************************************************************************** + * + * SkMacRxTxEnable() - Enable Rx/Tx activity if port is up + * + * Description: enables Rx/Tx dep. on board type + * + * Returns: + * 0 o.k. + * != 0 Error happened + */ +int SkMacRxTxEnable( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 Reg; /* 16-bit register value */ + SK_U16 IntMask; /* MAC interrupt mask */ + SK_U16 SWord; + + pPrt = &pAC->GIni.GP[Port]; + + if (!pPrt->PHWLinkUp) { + /* The Hardware link is NOT up */ + return(0); + } + + if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF || + pPrt->PLinkMode == SK_LMODE_AUTOFULL || + pPrt->PLinkMode == SK_LMODE_AUTOBOTH) && + pPrt->PAutoNegFail) { + /* Auto-negotiation is not done or failed */ + return(0); + } + + if (pAC->GIni.GIGenesis) { + /* set Duplex Mode and Pause Mode */ + SkXmInitDupMd(pAC, IoC, Port); + + SkXmInitPauseMd(pAC, IoC, Port); + + /* + * Initialize the Interrupt Mask Register. Default IRQs are... + * - Link Asynchronous Event + * - Link Partner requests config + * - Auto Negotiation Done + * - Rx Counter Event Overflow + * - Tx Counter Event Overflow + * - Transmit FIFO Underrun + */ + IntMask = XM_DEF_MSK; + +#ifdef DEBUG + /* add IRQ for Receive FIFO Overflow */ + IntMask &= ~XM_IS_RXF_OV; +#endif /* DEBUG */ + + if (pPrt->PhyType != SK_PHY_XMAC) { + /* disable GP0 interrupt bit */ + IntMask |= XM_IS_INP_ASS; + } + XM_OUT16(IoC, Port, XM_IMSK, IntMask); + + /* get MMU Command Reg. */ + XM_IN16(IoC, Port, XM_MMU_CMD, &Reg); + + if (pPrt->PhyType != SK_PHY_XMAC && + (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL)) { + /* set to Full Duplex */ + Reg |= XM_MMU_GMII_FD; + } + + switch (pPrt->PhyType) { + case SK_PHY_BCOM: + /* + * Workaround BCOM Errata (#10523) for all BCom Phys + * Enable Power Management after link up + */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, + (SK_U16)(SWord & ~PHY_B_AC_DIS_PM)); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_INT_ENAB, PHY_L_DEF_MSK); + break; + case SK_PHY_NAT: + /* todo National: + SkXmPhyWrite(pAC, IoC, Port, PHY_NAT_INT_MASK, PHY_N_DEF_MSK); */ + /* no interrupts possible from National ??? */ + break; +#endif /* OTHER_PHY */ + } + + /* enable Rx/Tx */ + XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX); + } + else { + /* + * Initialize the Interrupt Mask Register. Default IRQs are... + * - Rx Counter Event Overflow + * - Tx Counter Event Overflow + * - Transmit FIFO Underrun + */ + IntMask = GMAC_DEF_MSK; + +#ifdef DEBUG + /* add IRQ for Receive FIFO Overrun */ + IntMask |= GM_IS_RX_FF_OR; +#endif /* DEBUG */ + + SK_OUT8(IoC, GMAC_IRQ_MSK, (SK_U8)IntMask); + + /* get General Purpose Control */ + GM_IN16(IoC, Port, GM_GP_CTRL, &Reg); + + if (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) { + /* set to Full Duplex */ + Reg |= GM_GPCR_DUP_FULL; + } + + /* enable Rx/Tx */ + GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); + +#ifndef VCPU + /* Enable all PHY interrupts */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); +#endif /* VCPU */ + } + + return(0); + +} /* SkMacRxTxEnable */ + + +/****************************************************************************** + * + * SkMacRxTxDisable() - Disable Receiver and Transmitter + * + * Description: disables Rx/Tx dep. on board type + * + * Returns: N/A + */ +void SkMacRxTxDisable( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 Word; + + if (pAC->GIni.GIGenesis) { + + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + + XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); + + /* dummy read to ensure writing */ + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + } + else { + + GM_IN16(IoC, Port, GM_GP_CTRL, &Word); + + GM_OUT16(IoC, Port, GM_GP_CTRL, Word & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)); + + /* dummy read to ensure writing */ + GM_IN16(IoC, Port, GM_GP_CTRL, &Word); + } +} /* SkMacRxTxDisable */ + + +/****************************************************************************** + * + * SkMacIrqDisable() - Disable IRQ from MAC + * + * Description: sets the IRQ-mask to disable IRQ dep. on board type + * + * Returns: N/A + */ +void SkMacIrqDisable( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 Word; + + pPrt = &pAC->GIni.GP[Port]; + + if (pAC->GIni.GIGenesis) { + + /* disable all XMAC IRQs */ + XM_OUT16(IoC, Port, XM_IMSK, 0xffff); + + /* Disable all PHY interrupts */ + switch (pPrt->PhyType) { + case SK_PHY_BCOM: + /* Make sure that PHY is initialized */ + if (pPrt->PState != SK_PRT_RESET) { + /* NOT allowed if BCOM is in RESET state */ + /* Workaround BCOM Errata (#10523) all BCom */ + /* Disable Power Management if link is down */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Word); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, + (SK_U16)(Word | PHY_B_AC_DIS_PM)); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, 0xffff); + } + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_INT_ENAB, 0); + break; + case SK_PHY_NAT: + /* todo: National + SkXmPhyWrite(pAC, IoC, Port, PHY_NAT_INT_MASK, 0xffff); */ + break; +#endif /* OTHER_PHY */ + } + } + else { + /* disable all GMAC IRQs */ + SK_OUT8(IoC, GMAC_IRQ_MSK, 0); + +#ifndef VCPU + /* Disable all PHY interrupts */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0); +#endif /* VCPU */ + } +} /* SkMacIrqDisable */ + + +#ifdef SK_DIAG +/****************************************************************************** + * + * SkXmSendCont() - Enable / Disable Send Continuous Mode + * + * Description: enable / disable Send Continuous Mode on XMAC + * + * Returns: + * nothing + */ +void SkXmSendCont( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U32 MdReg; + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + + if (Enable) { + MdReg |= XM_MD_TX_CONT; + } + else { + MdReg &= ~XM_MD_TX_CONT; + } + /* setup Mode Register */ + XM_OUT32(IoC, Port, XM_MODE, MdReg); + +} /* SkXmSendCont*/ + +/****************************************************************************** + * + * SkMacTimeStamp() - Enable / Disable Time Stamp + * + * Description: enable / disable Time Stamp generation for Rx packets + * + * Returns: + * nothing + */ +void SkMacTimeStamp( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U32 MdReg; + SK_U8 TimeCtrl; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + + if (Enable) { + MdReg |= XM_MD_ATS; + } + else { + MdReg &= ~XM_MD_ATS; + } + /* setup Mode Register */ + XM_OUT32(IoC, Port, XM_MODE, MdReg); + } + else { + if (Enable) { + TimeCtrl = GMT_ST_START | GMT_ST_CLR_IRQ; + } + else { + TimeCtrl = GMT_ST_STOP | GMT_ST_CLR_IRQ; + } + /* Start/Stop Time Stamp Timer */ + SK_OUT8(pAC, GMAC_TI_ST_CTRL, TimeCtrl); + } +} /* SkMacTimeStamp*/ + +#else /* SK_DIAG */ + +/****************************************************************************** + * + * SkXmIrq() - Interrupt Service Routine + * + * Description: services an Interrupt Request of the XMAC + * + * Note: + * With an external PHY, some interrupt bits are not meaningfull any more: + * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE + * - LinkPartnerReqConfig (bit #10) XM_IS_LIPA_RC + * - Page Received (bit #9) XM_IS_RX_PAGE + * - NextPageLoadedForXmt (bit #8) XM_IS_TX_PAGE + * - AutoNegDone (bit #7) XM_IS_AND + * Also probably not valid any more is the GP0 input bit: + * - GPRegisterBit0set XM_IS_INP_ASS + * + * Returns: + * nothing + */ +void SkXmIrq( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_EVPARA Para; + SK_U16 IStatus; /* Interrupt status read from the XMAC */ + SK_U16 IStatus2; + + pPrt = &pAC->GIni.GP[Port]; + + XM_IN16(IoC, Port, XM_ISRC, &IStatus); + + /* LinkPartner Auto-negable? */ + if (pPrt->PhyType == SK_PHY_XMAC) { + SkXmAutoNegLipaXmac(pAC, IoC, Port, IStatus); + } + else { + /* mask bits that are not used with ext. PHY */ + IStatus &= ~(XM_IS_LNK_AE | XM_IS_LIPA_RC | + XM_IS_RX_PAGE | XM_IS_TX_PAGE | + XM_IS_AND | XM_IS_INP_ASS); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("XmacIrq Port %d Isr 0x%04x\n", Port, IStatus)); + + if (!pPrt->PHWLinkUp) { + /* Spurious XMAC interrupt */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("SkXmIrq: spurious interrupt on Port %d\n", Port)); + return; + } + + if ((IStatus & XM_IS_INP_ASS) != 0) { + /* Reread ISR Register if link is not in sync */ + XM_IN16(IoC, Port, XM_ISRC, &IStatus2); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("SkXmIrq: Link async. Double check Port %d 0x%04x 0x%04x\n", + Port, IStatus, IStatus2)); + IStatus &= ~XM_IS_INP_ASS; + IStatus |= IStatus2; + } + + if ((IStatus & XM_IS_LNK_AE) != 0) { + /* not used, GP0 is used instead */ + } + + if ((IStatus & XM_IS_TX_ABORT) != 0) { + /* not used */ + } + + if ((IStatus & XM_IS_FRC_INT) != 0) { + /* not used, use ASIC IRQ instead if needed */ + } + + if ((IStatus & (XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE)) != 0) { + SkHWLinkDown(pAC, IoC, Port); + + /* Signal to RLMT */ + Para.Para32[0] = (SK_U32)Port; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + + /* Start workaround Errata #2 timer */ + SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME, + SKGE_HWAC, SK_HWEV_WATIM, Para); + } + + if ((IStatus & XM_IS_RX_PAGE) != 0) { + /* not used */ + } + + if ((IStatus & XM_IS_TX_PAGE) != 0) { + /* not used */ + } + + if ((IStatus & XM_IS_AND) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("SkXmIrq: AND on link that is up Port %d\n", Port)); + } + + if ((IStatus & XM_IS_TSC_OV) != 0) { + /* not used */ + } + + /* Combined Tx & Rx Counter Overflow SIRQ Event */ + if ((IStatus & (XM_IS_RXC_OV | XM_IS_TXC_OV)) != 0) { + Para.Para32[0] = (SK_U32)Port; + Para.Para32[1] = (SK_U32)IStatus; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para); + } + + if ((IStatus & XM_IS_RXF_OV) != 0) { + /* normal situation -> no effect */ +#ifdef DEBUG + pPrt->PRxOverCnt++; +#endif /* DEBUG */ + } + + if ((IStatus & XM_IS_TXF_UR) != 0) { + /* may NOT happen -> error log */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E020, SKERR_SIRQ_E020MSG); + } + + if ((IStatus & XM_IS_TX_COMP) != 0) { + /* not served here */ + } + + if ((IStatus & XM_IS_RX_COMP) != 0) { + /* not served here */ + } +} /* SkXmIrq */ + + +/****************************************************************************** + * + * SkGmIrq() - Interrupt Service Routine + * + * Description: services an Interrupt Request of the GMAC + * + * Note: + * + * Returns: + * nothing + */ +void SkGmIrq( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_EVPARA Para; + SK_U8 IStatus; /* Interrupt status */ + + pPrt = &pAC->GIni.GP[Port]; + + SK_IN8(IoC, GMAC_IRQ_SRC, &IStatus); + + /* LinkPartner Auto-negable? */ + SkMacAutoNegLipaPhy(pAC, IoC, Port, IStatus); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("GmacIrq Port %d Isr 0x%04x\n", Port, IStatus)); + + /* Combined Tx & Rx Counter Overflow SIRQ Event */ + if (IStatus & (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV)) { + /* these IRQs will be cleared by reading GMACs register */ + Para.Para32[0] = (SK_U32)Port; + Para.Para32[1] = (SK_U32)IStatus; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para); + } + + if (IStatus & GM_IS_RX_FF_OR) { + /* clear GMAC Rx FIFO Overrun IRQ */ + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FO); +#ifdef DEBUG + pPrt->PRxOverCnt++; +#endif /* DEBUG */ + } + + if (IStatus & GM_IS_TX_FF_UR) { + /* clear GMAC Tx FIFO Underrun IRQ */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FU); + /* may NOT happen -> error log */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E020, SKERR_SIRQ_E020MSG); + } + + if (IStatus & GM_IS_TX_COMPL) { + /* not served here */ + } + + if (IStatus & GM_IS_RX_COMPL) { + /* not served here */ + } +} /* SkGmIrq */ + +/****************************************************************************** + * + * SkMacIrq() - Interrupt Service Routine for MAC + * + * Description: calls the Interrupt Service Routine dep. on board type + * + * Returns: + * nothing + */ +void SkMacIrq( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + + if (pAC->GIni.GIGenesis) { + /* IRQ from XMAC */ + SkXmIrq(pAC, IoC, Port); + } + else { + /* IRQ from GMAC */ + SkGmIrq(pAC, IoC, Port); + } +} /* SkMacIrq */ + +#endif /* !SK_DIAG */ + +/****************************************************************************** + * + * SkXmUpdateStats() - Force the XMAC to output the current statistic + * + * Description: + * The XMAC holds its statistic internally. To obtain the current + * values a command must be sent so that the statistic data will + * be written to a predefined memory area on the adapter. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkXmUpdateStats( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 StatReg; + int WaitIndex; + + pPrt = &pAC->GIni.GP[Port]; + WaitIndex = 0; + + /* Send an update command to XMAC specified */ + XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); + + /* + * It is an auto-clearing register. If the command bits + * went to zero again, the statistics are transferred. + * Normally the command should be executed immediately. + * But just to be sure we execute a loop. + */ + do { + + XM_IN16(IoC, Port, XM_STAT_CMD, &StatReg); + + if (++WaitIndex > 10) { + + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E021, SKERR_HWI_E021MSG); + + return(1); + } + } while ((StatReg & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) != 0); + + return(0); +} /* SkXmUpdateStats */ + +/****************************************************************************** + * + * SkGmUpdateStats() - Force the GMAC to output the current statistic + * + * Description: + * Empty function for GMAC. Statistic data is accessible in direct way. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmUpdateStats( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + return(0); +} + +/****************************************************************************** + * + * SkXmMacStatistic() - Get XMAC counter value + * + * Description: + * Gets the 32bit counter value. Except for the octet counters + * the lower 32bit are counted in hardware and the upper 32bit + * must be counted in software by monitoring counter overflow interrupts. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkXmMacStatistic( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 StatAddr, /* MIB counter base address */ +SK_U32 *pVal) /* ptr to return statistic value */ +{ + if ((StatAddr < XM_TXF_OK) || (StatAddr > XM_RXF_MAX_SZ)) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG); + + return(1); + } + + XM_IN32(IoC, Port, StatAddr, pVal); + + return(0); +} /* SkXmMacStatistic */ + +/****************************************************************************** + * + * SkGmMacStatistic() - Get GMAC counter value + * + * Description: + * Gets the 32bit counter value. Except for the octet counters + * the lower 32bit are counted in hardware and the upper 32bit + * must be counted in software by monitoring counter overflow interrupts. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmMacStatistic( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 StatAddr, /* MIB counter base address */ +SK_U32 *pVal) /* ptr to return statistic value */ +{ + + if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr)); + return(1); + } + + GM_IN32(IoC, Port, StatAddr, pVal); + + return(0); +} /* SkGmMacStatistic */ + +/****************************************************************************** + * + * SkXmResetCounter() - Clear MAC statistic counter + * + * Description: + * Force the XMAC to clear its statistic counter. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkXmResetCounter( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC); + /* Clear two times according to Errata #3 */ + XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC); + + return(0); +} /* SkXmResetCounter */ + +/****************************************************************************** + * + * SkGmResetCounter() - Clear MAC statistic counter + * + * Description: + * Force GMAC to clear its statistic counter. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmResetCounter( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 Reg; /* Phy Address Register */ + SK_U16 Word; + int i; + + GM_IN16(IoC, Port, GM_PHY_ADDR, &Reg); + +#ifndef VCPU + /* set MIB Clear Counter Mode */ + GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR); + + /* read all MIB Counters with Clear Mode set */ + for (i = 0; i < GM_MIB_CNT_SIZE; i++) { + /* the reset is performed only when the lower 16 bits are read */ + GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word); + } + + /* clear MIB Clear Counter Mode */ + GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg); +#endif /* !VCPU */ + + return(0); +} /* SkGmResetCounter */ + +/****************************************************************************** + * + * SkXmOverflowStatus() - Gets the status of counter overflow interrupt + * + * Description: + * Checks the source causing an counter overflow interrupt. On success the + * resulting counter overflow status is written to , whereas the + * upper dword stores the XMAC ReceiveCounterEvent register and the lower + * dword the XMAC TransmitCounterEvent register. + * + * Note: + * For XMAC the interrupt source is a self-clearing register, so the source + * must be checked only once. SIRQ module does another check to be sure + * that no interrupt get lost during process time. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkXmOverflowStatus( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 IStatus, /* Interupt Status from MAC */ +SK_U64 *pStatus) /* ptr for return overflow status value */ +{ + SK_U64 Status; /* Overflow status */ + SK_U32 RegVal; + + Status = 0; + + if ((IStatus & XM_IS_RXC_OV) != 0) { + + XM_IN32(IoC, Port, XM_RX_CNT_EV, &RegVal); + Status |= (SK_U64)RegVal << 32; + } + + if ((IStatus & XM_IS_TXC_OV) != 0) { + + XM_IN32(IoC, Port, XM_TX_CNT_EV, &RegVal); + Status |= (SK_U64)RegVal; + } + + *pStatus = Status; + + return(0); +} /* SkXmOverflowStatus */ + + +/****************************************************************************** + * + * SkGmOverflowStatus() - Gets the status of counter overflow interrupt + * + * Description: + * Checks the source causing an counter overflow interrupt. On success the + * resulting counter overflow status is written to , whereas the + * the following bit coding is used: + * 63:56 - unused + * 55:48 - TxRx interrupt register bit7:0 + * 32:47 - Rx interrupt register + * 31:24 - unused + * 23:16 - TxRx interrupt register bit15:8 + * 15:0 - Tx interrupt register + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmOverflowStatus( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 IStatus, /* Interupt Status from MAC */ +SK_U64 *pStatus) /* ptr for return overflow status value */ +{ + SK_U64 Status; /* Overflow status */ + SK_U16 RegVal; + + Status = 0; + + if ((IStatus & GM_IS_RX_CO_OV) != 0) { + /* this register is self-clearing after read */ + GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal); + Status |= (SK_U64)RegVal << 32; + } + + if ((IStatus & GM_IS_TX_CO_OV) != 0) { + /* this register is self-clearing after read */ + GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal); + Status |= (SK_U64)RegVal; + } + + /* this register is self-clearing after read */ + GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal); + /* Rx overflow interrupt register bits (LoByte)*/ + Status |= (SK_U64)((SK_U8)RegVal) << 48; + /* Tx overflow interrupt register bits (HiByte)*/ + Status |= (SK_U64)(RegVal >> 8) << 16; + + *pStatus = Status; + + return(0); +} /* SkGmOverflowStatus */ + +/****************************************************************************** + * + * SkGmCableDiagStatus() - Starts / Gets status of cable diagnostic test + * + * Description: + * starts the cable diagnostic test if 'StartTest' is true + * gets the results if 'StartTest' is true + * + * NOTE: this test is meaningful only when link is down + * + * Returns: + * 0: success + * 1: no YUKON copper + * 2: test in progress + */ +int SkGmCableDiagStatus( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL StartTest) /* flag for start / get result */ +{ + int i; + SK_U16 RegVal; + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PhyType != SK_PHY_MARV_COPPER) { + + return(1); + } + + if (StartTest) { + /* only start the cable test */ + if ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4) { + /* apply TDR workaround from Marvell */ + SkGmPhyWrite(pAC, IoC, Port, 29, 0x001e); + + SkGmPhyWrite(pAC, IoC, Port, 30, 0xcc00); + SkGmPhyWrite(pAC, IoC, Port, 30, 0xc800); + SkGmPhyWrite(pAC, IoC, Port, 30, 0xc400); + SkGmPhyWrite(pAC, IoC, Port, 30, 0xc000); + SkGmPhyWrite(pAC, IoC, Port, 30, 0xc100); + } + + /* set address to 0 for MDI[0] */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0); + + /* Read Cable Diagnostic Reg */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal); + + /* start Cable Diagnostic Test */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, + (SK_U16)(RegVal | PHY_M_CABD_ENA_TEST)); + + return(0); + } + + /* Read Cable Diagnostic Reg */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Cable Diag.=0x%04X\n", RegVal)); + + if ((RegVal & PHY_M_CABD_ENA_TEST) != 0) { + /* test is running */ + return(2); + } + + /* get the test results */ + for (i = 0; i < 4; i++) { + /* set address to i for MDI[i] */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i); + + /* get Cable Diagnostic values */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal); + + pPrt->PMdiPairLen[i] = (SK_U8)(RegVal & PHY_M_CABD_DIST_MSK); + + pPrt->PMdiPairSts[i] = (SK_U8)((RegVal & PHY_M_CABD_STAT_MSK) >> 13); + } + + return(0); +} /* SkGmCableDiagStatus */ + +#endif /* CONFIG_SK98 */ + +/* End of file */ diff --git a/drivers/sk98lin/u-boot_compat.h b/drivers/sk98lin/u-boot_compat.h new file mode 100644 index 0000000..1e385f8 --- /dev/null +++ b/drivers/sk98lin/u-boot_compat.h @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _UBOOT_COMPAT_H__ +#define _UBOOT_COMPAT_H__ + + +#include +#include +#include +#include +#include + +#define __initdata +#define __init +#define __exit + +#define netif_stop_queue(x) +#define netif_wake_queue(x) +#define netif_running(x) 0 +#define unregister_netdev(x) +#define remove_proc_entry(x,y) + +#define dev_addr enetaddr + +#define spin_lock_irqsave(x,y) y = 0; +#define spin_lock_init(x) +#define spin_lock(x) +#define spin_unlock_irqrestore(x,y) +#define spin_unlock(x) + + +#define ENODEV 1 +#define EAGAIN 2 +#define EBUSY 3 + +#define HZ CFG_HZ + + +#define printk printf +#define KERN_ERR +#define KERN_WARNING +#define KERN_INFO + +#define MOD_INC_USE_COUNT +#define MOD_DEC_USE_COUNT + + +#define kmalloc(x,y) malloc(x) +#define kfree(x) free(x) +#define GFP_ATOMIC 0 + +#define pci_alloc_consistent(x,y,z) (void *)(*(dma_addr_t *)(z) = (dma_addr_t)malloc(y)) +#define pci_free_consistent(x,y,z,d) free(z) +#define pci_dma_sync_single(x,y,z,d) +#define pci_unmap_page(x,y,z,d) +#define pci_unmap_single(x,y,z,d) +#define pci_present() 1 + +struct sk_buff +{ + u8 * data; + u32 len; + u8 * data_unaligned; +}; + +struct sk_buff * alloc_skb(u32 size, int dummy); +void dev_kfree_skb_any(struct sk_buff *skb); +void skb_reserve(struct sk_buff *skb, unsigned int len); +void skb_put(struct sk_buff *skb, unsigned int len); + +#define dev_kfree_skb dev_kfree_skb_any +#define dev_kfree_skb_irq dev_kfree_skb_any + +#define eth_copy_and_sum(dest,src,len,base) memcpy(dest->data,src,len); + + +#endif /* _UBOOT_COMPAT_H__ */ diff --git a/drivers/sk98lin/uboot_drv.c b/drivers/sk98lin/uboot_drv.c new file mode 100644 index 0000000..263dac8 --- /dev/null +++ b/drivers/sk98lin/uboot_drv.c @@ -0,0 +1,143 @@ +/* + * Driver for SysKonnect Gigabit Ethernet Server Adapters. + * + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_SK98) + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" +#include "u-boot_compat.h" + + +#define SKGE_MAX_CARDS 2 + + +extern int skge_probe(struct eth_device **); +extern void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); +extern void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); +extern int SkGeOpen(struct eth_device *); +extern int SkGeClose(struct eth_device *); +extern int SkGeXmit(struct sk_buff *skb, struct eth_device *dev); +extern void ReceiveIrq(SK_AC *pAC, RX_PORT *pRxPort, SK_BOOL SlowPathLock); + +static int skge_init(struct eth_device *dev, bd_t * bis); +static int skge_send(struct eth_device *dev, volatile void *packet, int length); +static int skge_recv(struct eth_device *dev); +static void skge_halt(struct eth_device *dev); + +int skge_initialize(bd_t * bis) +{ + int numdev, i; + struct eth_device *dev[SKGE_MAX_CARDS]; + + numdev = skge_probe(&dev[0]); + + if (numdev > SKGE_MAX_CARDS) + { + printf("ERROR: numdev > SKGE_MAX_CARDS\n"); + } + + for (i = 0; i < numdev; i++) + { + sprintf (dev[i]->name, "SK98#%d", i); + + dev[i]->init = skge_init; + dev[i]->halt = skge_halt; + dev[i]->send = skge_send; + dev[i]->recv = skge_recv; + + eth_register(dev[i]); + } + + return numdev; +} + + +static int skge_init(struct eth_device *dev, bd_t * bis) +{ + int ret; + SK_AC * pAC = ((DEV_NET*)dev->priv)->pAC; + int i; + + ret = SkGeOpen(dev); + + while (pAC->Rlmt.Port[0].PortState != SK_RLMT_PS_GOING_UP) + { + SkGeIsrOnePort (0, pAC->dev[0], 0); + } + + for (i = 0; i < 100; i ++) + { + udelay(1000); + } + + return ret; +} + + +static void skge_halt(struct eth_device *dev) +{ + SkGeClose(dev); +} + + +static int skge_send(struct eth_device *dev, volatile void *packet, + int length) +{ + int ret = -1; + struct sk_buff * skb = alloc_skb(length, 0); + + if (! skb) + { + printf("skge_send: failed to alloc skb\n"); + goto Done; + } + + memcpy(skb->data, (void*)packet, length); + ret = SkGeXmit(skb, dev); + +Done: + return ret; +} + + +static int skge_recv(struct eth_device *dev) +{ + DEV_NET *pNet; + SK_AC *pAC; + int FromPort = 0; + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); + + return 0; +} + + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/uboot_skb.c b/drivers/sk98lin/uboot_skb.c new file mode 100644 index 0000000..3a487a8 --- /dev/null +++ b/drivers/sk98lin/uboot_skb.c @@ -0,0 +1,122 @@ +/* + * Definitions for the 'struct sk_buff' memory handlers in U-Boot. + * + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_SK98 + +#include +#include "u-boot_compat.h" + +#define MAX_SKB 50 + +static struct sk_buff *sk_table[MAX_SKB]; + + +struct sk_buff * alloc_skb(u32 size, int dummy) +{ + int i; + struct sk_buff * ret = NULL; + + for (i = 0; i < MAX_SKB; i++) + { + if (sk_table[i]) + { + /* Already allocated. + */ + continue; + } + + sk_table[i] = malloc(sizeof(struct sk_buff)); + if (! sk_table[i]) + { + printf("alloc_skb: malloc failed\n"); + break; + } + + memset(sk_table[i], 0, sizeof(struct sk_buff)); + sk_table[i]->data = sk_table[i]->data_unaligned = + malloc(size + 16); + if (! sk_table[i]->data) + { + printf("alloc_skb: malloc failed\n"); + free(sk_table[i]); + sk_table[i] = NULL; + break; + } + + sk_table[i]->data += 16 - ((u32)sk_table[i]->data & 15); + sk_table[i]->len = size; + + break; + } + + if (i < MAX_SKB) + { + ret = sk_table[i]; + } + + if (! ret) + { + printf("Unable to allocate skb!\n"); + } + + return ret; +} + +void dev_kfree_skb_any(struct sk_buff *skb) +{ + int i; + + for (i = 0; i < MAX_SKB; i++) + { + if (sk_table[i] != skb) + { + continue; + } + + free(skb->data_unaligned); + free(skb); + sk_table[i] = NULL; + break; + } + + if (i == MAX_SKB) + { + printf("SKB allocation error!\n"); + } +} + +void skb_reserve(struct sk_buff *skb, unsigned int len) +{ + skb->data+=len; +} + +void skb_put(struct sk_buff *skb, unsigned int len) +{ + skb->len+=len; +} + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sl811.h b/drivers/sl811.h new file mode 100644 index 0000000..c1f9f01 --- /dev/null +++ b/drivers/sl811.h @@ -0,0 +1,104 @@ +#ifndef __UBOOT_SL811_H +#define __UBOOT_SL811_H + +#undef SL811_DEBUG + +#ifdef SL811_DEBUG + #define PDEBUG(level, fmt, args...) \ + if (debug >= (level)) printf("[%s:%d] " fmt, \ + __PRETTY_FUNCTION__, __LINE__ , ## args) +#else + #define PDEBUG(level, fmt, args...) do {} while(0) +#endif + +/* Sl811 host control register */ +#define SL811_CTRL_A 0x00 +#define SL811_ADDR_A 0x01 +#define SL811_LEN_A 0x02 +#define SL811_STS_A 0x03 /* read */ +#define SL811_PIDEP_A 0x03 /* write */ +#define SL811_CNT_A 0x04 /* read */ +#define SL811_DEV_A 0x04 /* write */ +#define SL811_CTRL1 0x05 +#define SL811_INTR 0x06 +#define SL811_CTRL_B 0x08 +#define SL811_ADDR_B 0x09 +#define SL811_LEN_B 0x0A +#define SL811_STS_B 0x0B /* read */ +#define SL811_PIDEP_B 0x0B /* write */ +#define SL811_CNT_B 0x0C /* read */ +#define SL811_DEV_B 0x0C /* write */ +#define SL811_INTRSTS 0x0D /* write clears bitwise */ +#define SL811_HWREV 0x0E /* read */ +#define SL811_SOFLOW 0x0E /* write */ +#define SL811_SOFCNTDIV 0x0F /* read */ +#define SL811_CTRL2 0x0F /* write */ + +/* USB control register bits (addr 0x00 and addr 0x08) */ +#define SL811_USB_CTRL_ARM 0x01 +#define SL811_USB_CTRL_ENABLE 0x02 +#define SL811_USB_CTRL_DIR_OUT 0x04 +#define SL811_USB_CTRL_ISO 0x10 +#define SL811_USB_CTRL_SOF 0x20 +#define SL811_USB_CTRL_TOGGLE_1 0x40 +#define SL811_USB_CTRL_PREAMBLE 0x80 + +/* USB status register bits (addr 0x03 and addr 0x0B) */ +#define SL811_USB_STS_ACK 0x01 +#define SL811_USB_STS_ERROR 0x02 +#define SL811_USB_STS_TIMEOUT 0x04 +#define SL811_USB_STS_TOGGLE_1 0x08 +#define SL811_USB_STS_SETUP 0x10 +#define SL811_USB_STS_OVERFLOW 0x20 +#define SL811_USB_STS_NAK 0x40 +#define SL811_USB_STS_STALL 0x80 + +/* Control register 1 bits (addr 0x05) */ +#define SL811_CTRL1_SOF 0x01 +#define SL811_CTRL1_RESET 0x08 +#define SL811_CTRL1_JKSTATE 0x10 +#define SL811_CTRL1_SPEED_LOW 0x20 +#define SL811_CTRL1_SUSPEND 0x40 + +/* Interrut enable (addr 0x06) and interrupt status register bits (addr 0x0D) */ +#define SL811_INTR_DONE_A 0x01 +#define SL811_INTR_DONE_B 0x02 +#define SL811_INTR_SOF 0x10 +#define SL811_INTR_INSRMV 0x20 +#define SL811_INTR_DETECT 0x40 +#define SL811_INTR_NOTPRESENT 0x40 +#define SL811_INTR_SPEED_FULL 0x80 /* only in status reg */ + +/* HW rev and SOF lo register bits (addr 0x0E) */ +#define SL811_HWR_HWREV 0xF0 + +/* SOF counter and control reg 2 (addr 0x0F) */ +#define SL811_CTL2_SOFHI 0x3F +#define SL811_CTL2_DSWAP 0x40 +#define SL811_CTL2_HOST 0x80 + +/* Set up for 1-ms SOF time. */ +#define SL811_12M_LOW 0xE0 +#define SL811_12M_HI 0x2E + +#define SL811_DATA_START 0x10 +#define SL811_DATA_LIMIT 240 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 + + +#define PIDEP(pid, ep) (((pid) & 0x0f) << 4 | (ep)) + +#endif /* __UBOOT_SL811_H */ diff --git a/drivers/sl811_usb.c b/drivers/sl811_usb.c new file mode 100644 index 0000000..b0cdf0b --- /dev/null +++ b/drivers/sl811_usb.c @@ -0,0 +1,737 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This code is based on linux driver for sl811hs chip, source at + * drivers/usb/host/sl811.c: + * + * SL811 Host Controller Interface driver for USB. + * + * Copyright (c) 2003/06, Courage Co., Ltd. + * + * Based on: + * 1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap, + * Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, + * Adam Richter, Gregory P. Smith; + * 2.Original SL811 driver (hc_sl811.o) by Pei Liu + * 3.Rewrited as sl811.o by Yin Aihua + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#ifdef CONFIG_USB_SL811HS +#include +#include +#include "sl811.h" + +#include "../board/kup/common/kup.h" + +#ifdef __PPC__ +# define EIEIO __asm__ volatile ("eieio") +#else +# define EIEIO /* nothing */ +#endif + +#define SL811_ADR (0x50000000) +#define SL811_DAT (0x50000001) + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) + +#ifdef SL811_DEBUG +static int debug = 9; +#endif + +static int root_hub_devnum = 0; +static struct usb_port_status rh_status = { 0 };/* root hub port status */ + +static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, + void *data, int buf_len, struct devrequest *cmd); + +static void sl811_write (__u8 index, __u8 data) +{ + *(volatile unsigned char *) (SL811_ADR) = index; + EIEIO; + *(volatile unsigned char *) (SL811_DAT) = data; + EIEIO; +} + +static __u8 sl811_read (__u8 index) +{ + __u8 data; + + *(volatile unsigned char *) (SL811_ADR) = index; + EIEIO; + data = *(volatile unsigned char *) (SL811_DAT); + EIEIO; + return (data); +} + +/* + * Read consecutive bytes of data from the SL811H/SL11H buffer + */ +static void inline sl811_read_buf(__u8 offset, __u8 *buf, __u8 size) +{ + *(volatile unsigned char *) (SL811_ADR) = offset; + EIEIO; + while (size--) { + *buf++ = *(volatile unsigned char *) (SL811_DAT); + EIEIO; + } +} + +/* + * Write consecutive bytes of data to the SL811H/SL11H buffer + */ +static void inline sl811_write_buf(__u8 offset, __u8 *buf, __u8 size) +{ + *(volatile unsigned char *) (SL811_ADR) = offset; + EIEIO; + while (size--) { + *(volatile unsigned char *) (SL811_DAT) = *buf++; + EIEIO; + } +} + +int usb_init_kup4x (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + int i; + unsigned char tmp; + + memctl = &immap->im_memctl; + memctl->memc_or7 = 0xFFFF8726; + memctl->memc_br7 = 0x50000401; /* start at 0x50000000 */ + /* BP 14 low = USB ON */ + immap->im_cpm.cp_pbdat &= ~(BP_USB_VCC); + /* PB 14 nomal port */ + immap->im_cpm.cp_pbpar &= ~(BP_USB_VCC); + /* output */ + immap->im_cpm.cp_pbdir |= (BP_USB_VCC); + + puts ("USB: "); + + for (i = 0x10; i < 0xff; i++) { + sl811_write(i, i); + tmp = (sl811_read(i)); + if (tmp != i) { + printf ("SL811 compare error index=0x%02x read=0x%02x\n", i, tmp); + return (-1); + } + } + printf ("SL811 ready\n"); + return (0); +} + +/* + * This function resets SL811HS controller and detects the speed of + * the connecting device + * + * Return: 0 = no device attached; 1 = USB device attached + */ +static int sl811_hc_reset(void) +{ + int status ; + + sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); + sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); + + mdelay(20); + + /* Disable hardware SOF generation, clear all irq status. */ + sl811_write(SL811_CTRL1, 0); + mdelay(2); + sl811_write(SL811_INTRSTS, 0xff); + status = sl811_read(SL811_INTRSTS); + + if (status & SL811_INTR_NOTPRESENT) { + /* Device is not present */ + PDEBUG(0, "Device not present\n"); + rh_status.wPortStatus &= ~(USB_PORT_STAT_CONNECTION | USB_PORT_STAT_ENABLE); + rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; + sl811_write(SL811_INTR, SL811_INTR_INSRMV); + return 0; + } + + /* Send SOF to address 0, endpoint 0. */ + sl811_write(SL811_LEN_B, 0); + sl811_write(SL811_PIDEP_B, PIDEP(USB_PID_SOF, 0)); + sl811_write(SL811_DEV_B, 0x00); + sl811_write(SL811_SOFLOW, SL811_12M_LOW); + + if (status & SL811_INTR_SPEED_FULL) { + /* full speed device connect directly to root hub */ + PDEBUG (0, "Full speed Device attached\n"); + + sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); + mdelay(20); + sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); + sl811_write(SL811_CTRL1, SL811_CTRL1_SOF); + + /* start the SOF or EOP */ + sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); + rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION; + rh_status.wPortStatus &= ~USB_PORT_STAT_LOW_SPEED; + mdelay(2); + sl811_write(SL811_INTRSTS, 0xff); + } else { + /* slow speed device connect directly to root-hub */ + PDEBUG(0, "Low speed Device attached\n"); + + sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); + mdelay(20); + sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_CTL2_DSWAP | SL811_12M_HI); + sl811_write(SL811_CTRL1, SL811_CTRL1_SPEED_LOW | SL811_CTRL1_SOF); + + /* start the SOF or EOP */ + sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); + rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION | USB_PORT_STAT_LOW_SPEED; + mdelay(2); + sl811_write(SL811_INTRSTS, 0xff); + } + + rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; + sl811_write(SL811_INTR, /*SL811_INTR_INSRMV*/SL811_INTR_DONE_A); + + return 1; +} + +int usb_lowlevel_init(void) +{ + root_hub_devnum = 0; + sl811_hc_reset(); + return 0; +} + +int usb_lowlevel_stop(void) +{ + sl811_hc_reset(); + return 0; +} + +static int calc_needed_buswidth(int bytes, int need_preamble) +{ + return !need_preamble ? bytes * 8 + 256 : 8 * 8 * bytes + 2048; +} + +static int sl811_send_packet(struct usb_device *dev, unsigned long pipe, __u8 *buffer, int len) +{ + __u8 ctrl = SL811_USB_CTRL_ARM | SL811_USB_CTRL_ENABLE; + __u16 status = 0; + int err = 0, time_start = get_timer(0); + int need_preamble = !(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && + usb_pipeslow(pipe); + + if (len > 239) + return -1; + + if (usb_pipeout(pipe)) + ctrl |= SL811_USB_CTRL_DIR_OUT; + if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) + ctrl |= SL811_USB_CTRL_TOGGLE_1; + if (need_preamble) + ctrl |= SL811_USB_CTRL_PREAMBLE; + + sl811_write(SL811_INTRSTS, 0xff); + + while (err < 3) { + sl811_write(SL811_ADDR_A, 0x10); + sl811_write(SL811_LEN_A, len); + if (usb_pipeout(pipe) && len) + sl811_write_buf(0x10, buffer, len); + + if (!(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && + sl811_read(SL811_SOFCNTDIV)*64 < calc_needed_buswidth(len, need_preamble)) + ctrl |= SL811_USB_CTRL_SOF; + else + ctrl &= ~SL811_USB_CTRL_SOF; + + sl811_write(SL811_CTRL_A, ctrl); + while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A)) { + if (5*CFG_HZ < get_timer(time_start)) { + printf("USB transmit timed out\n"); + return -USB_ST_CRC_ERR; + } + } + + sl811_write(SL811_INTRSTS, 0xff); + status = sl811_read(SL811_STS_A); + + if (status & SL811_USB_STS_ACK) { + int remainder = sl811_read(SL811_CNT_A); + if (remainder) { + PDEBUG(0, "usb transfer remainder = %d\n", remainder); + len -= remainder; + } + if (usb_pipein(pipe) && len) + sl811_read_buf(0x10, buffer, len); + return len; + } + + if ((status & SL811_USB_STS_NAK) == SL811_USB_STS_NAK) + continue; + + PDEBUG(0, "usb transfer error %#x\n", (int)status); + err++; + } + + err = 0; + + if (status & SL811_USB_STS_ERROR) + err |= USB_ST_BUF_ERR; + if (status & SL811_USB_STS_TIMEOUT) + err |= USB_ST_CRC_ERR; + if (status & SL811_USB_STS_STALL) + err |= USB_ST_STALLED; + + return -err; +} + +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len) +{ + int dir_out = usb_pipeout(pipe); + int ep = usb_pipeendpoint(pipe); + int max = usb_maxpacket(dev, pipe); + int done = 0; + + PDEBUG(7, "dev = %ld pipe = %ld buf = %p size = %d dir_out = %d\n", + usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out); + + dev->status = 0; + + sl811_write(SL811_DEV_A, usb_pipedevice(pipe)); + sl811_write(SL811_PIDEP_A, PIDEP(!dir_out ? USB_PID_IN : USB_PID_OUT, ep)); + while (done < len) { + int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, + max > len - done ? len - done : max); + if (res < 0) { + dev->status = -res; + return res; + } + + if (!dir_out && res < max) /* short packet */ + break; + + done += res; + usb_dotoggle(dev, ep, dir_out); + } + + dev->act_len = done; + + return 0; +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len,struct devrequest *setup) +{ + int done = 0; + int devnum = usb_pipedevice(pipe); + int ep = usb_pipeendpoint(pipe); + + dev->status = 0; + + if (devnum == root_hub_devnum) + return sl811_rh_submit_urb(dev, pipe, buffer, len, setup); + + PDEBUG(7, "dev = %d pipe = %ld buf = %p size = %d rt = %#x req = %#x bus = %i\n", + devnum, ep, buffer, len, (int)setup->requesttype, + (int)setup->request, sl811_read(SL811_SOFCNTDIV)*64); + + sl811_write(SL811_DEV_A, devnum); + sl811_write(SL811_PIDEP_A, PIDEP(USB_PID_SETUP, ep)); + /* setup phase */ + usb_settoggle(dev, ep, 1, 0); + if (sl811_send_packet(dev, usb_sndctrlpipe(dev, ep), + (__u8*)setup, sizeof(*setup)) == sizeof(*setup)) { + int dir_in = usb_pipein(pipe); + int max = usb_maxpacket(dev, pipe); + + /* data phase */ + sl811_write(SL811_PIDEP_A, + PIDEP(dir_in ? USB_PID_IN : USB_PID_OUT, ep)); + usb_settoggle(dev, ep, usb_pipeout(pipe), 1); + while (done < len) { + int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, + max > len - done ? len - done : max); + if (res < 0) { + PDEBUG(0, "status data failed!\n"); + dev->status = -res; + return 0; + } + done += res; + usb_dotoggle(dev, ep, usb_pipeout(pipe)); + if (dir_in && res < max) /* short packet */ + break; + } + + /* status phase */ + sl811_write(SL811_PIDEP_A, + PIDEP(!dir_in ? USB_PID_IN : USB_PID_OUT, ep)); + usb_settoggle(dev, ep, !usb_pipeout(pipe), 1); + if (sl811_send_packet(dev, + !dir_in ? usb_rcvctrlpipe(dev, ep) : + usb_sndctrlpipe(dev, ep), + 0, 0) < 0) { + PDEBUG(0, "status phase failed!\n"); + dev->status = -1; + } + } else { + PDEBUG(0, "setup phase failed!\n"); + dev->status = -1; + } + + dev->act_len = done; + + return done; +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, int interval) +{ + PDEBUG(0, "dev = %p pipe = %#lx buf = %p size = %d int = %d\n", dev, pipe, + buffer, len, interval); + return -1; +} + +/* + * SL811 Virtual Root Hub + */ + +/* Device descriptor */ +static __u8 sl811_rh_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x02, /* __u8 iProduct; */ + 0x01, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 sl811_rh_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, + 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x08, /* __u16 ep_wMaxPacketSize; */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +/* root hub class descriptor*/ +static __u8 sl811_rh_hub_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x29, /* __u8 bDescriptorType; Hub-descriptor */ + 0x01, /* __u8 bNbrPorts; */ + 0x00, /* __u16 wHubCharacteristics; */ + 0x00, + 0x50, /* __u8 bPwrOn2pwrGood; 2ms */ + 0x00, /* __u8 bHubContrCurrent; 0 mA */ + 0xfc, /* __u8 DeviceRemovable; *** 7 Ports max *** */ + 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ +}; + +/* + * helper routine for returning string descriptors in UTF-16LE + * input can actually be ISO-8859-1; ASCII is its 7-bit subset + */ +static int ascii2utf (char *s, u8 *utf, int utfmax) +{ + int retval; + + for (retval = 0; *s && utfmax > 1; utfmax -= 2, retval += 2) { + *utf++ = *s++; + *utf++ = 0; + } + return retval; +} + +/* + * root_hub_string is used by each host controller's root hub code, + * so that they're identified consistently throughout the system. + */ +static int usb_root_hub_string (int id, int serial, char *type, __u8 *data, int len) +{ + char buf [30]; + + /* assert (len > (2 * (sizeof (buf) + 1))); + assert (strlen (type) <= 8);*/ + + /* language ids */ + if (id == 0) { + *data++ = 4; *data++ = 3; /* 4 bytes data */ + *data++ = 0; *data++ = 0; /* some language id */ + return 4; + + /* serial number */ + } else if (id == 1) { + sprintf (buf, "%#x", serial); + + /* product description */ + } else if (id == 2) { + sprintf (buf, "USB %s Root Hub", type); + + /* id 3 == vendor description */ + + /* unsupported IDs --> "stall" */ + } else + return 0; + + ascii2utf (buf, data + 2, len - 2); + data [0] = 2 + strlen(buf) * 2; + data [1] = 3; + return data [0]; +} + +/* helper macro */ +#define OK(x) len = (x); break + +/* + * This function handles all USB request to the the virtual root hub + */ +static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, + void *data, int buf_len, struct devrequest *cmd) +{ + __u8 data_buf[16]; + __u8 *bufp = data_buf; + int len = 0; + int status = 0; + + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + + if (usb_pipeint(pipe)) { + PDEBUG(0, "interrupt transfer unimplemented!\n"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = le16_to_cpu (cmd->value); + wIndex = le16_to_cpu (cmd->index); + wLength = le16_to_cpu (cmd->length); + + PDEBUG(5, "submit rh urb, req = %d(%x) val = %#x index = %#x len=%d\n", + bmRType_bReq, bmRType_bReq, wValue, wIndex, wLength); + + /* Request Destination: + without flags: Device, + USB_RECIP_INTERFACE: interface, + USB_RECIP_ENDPOINT: endpoint, + USB_TYPE_CLASS means HUB here, + USB_RECIP_OTHER | USB_TYPE_CLASS almost ever means HUB_PORT here + */ + switch (bmRType_bReq) { + case RH_GET_STATUS: + *(__u16 *)bufp = cpu_to_le16(1); + OK(2); + + case RH_GET_STATUS | USB_RECIP_INTERFACE: + *(__u16 *)bufp = cpu_to_le16(0); + OK(2); + + case RH_GET_STATUS | USB_RECIP_ENDPOINT: + *(__u16 *)bufp = cpu_to_le16(0); + OK(2); + + case RH_GET_STATUS | USB_TYPE_CLASS: + *(__u32 *)bufp = cpu_to_le32(0); + OK(4); + + case RH_GET_STATUS | USB_RECIP_OTHER | USB_TYPE_CLASS: + *(__u32 *)bufp = cpu_to_le32(rh_status.wPortChange<<16 | rh_status.wPortStatus); + OK(4); + + case RH_CLEAR_FEATURE | USB_RECIP_ENDPOINT: + switch (wValue) { + case 1: + OK(0); + } + break; + + case RH_CLEAR_FEATURE | USB_TYPE_CLASS: + switch (wValue) { + case C_HUB_LOCAL_POWER: + OK(0); + + case C_HUB_OVER_CURRENT: + OK(0); + } + break; + + case RH_CLEAR_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: + switch (wValue) { + case USB_PORT_FEAT_ENABLE: + rh_status.wPortStatus &= ~USB_PORT_STAT_ENABLE; + OK(0); + + case USB_PORT_FEAT_SUSPEND: + rh_status.wPortStatus &= ~USB_PORT_STAT_SUSPEND; + OK(0); + + case USB_PORT_FEAT_POWER: + rh_status.wPortStatus &= ~USB_PORT_STAT_POWER; + OK(0); + + case USB_PORT_FEAT_C_CONNECTION: + rh_status.wPortChange &= ~USB_PORT_STAT_C_CONNECTION; + OK(0); + + case USB_PORT_FEAT_C_ENABLE: + rh_status.wPortChange &= ~USB_PORT_STAT_C_ENABLE; + OK(0); + + case USB_PORT_FEAT_C_SUSPEND: + rh_status.wPortChange &= ~USB_PORT_STAT_C_SUSPEND; + OK(0); + + case USB_PORT_FEAT_C_OVER_CURRENT: + rh_status.wPortChange &= ~USB_PORT_STAT_C_OVERCURRENT; + OK(0); + + case USB_PORT_FEAT_C_RESET: + rh_status.wPortChange &= ~USB_PORT_STAT_C_RESET; + OK(0); + } + break; + + case RH_SET_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: + switch (wValue) { + case USB_PORT_FEAT_SUSPEND: + rh_status.wPortStatus |= USB_PORT_STAT_SUSPEND; + OK(0); + + case USB_PORT_FEAT_RESET: + rh_status.wPortStatus |= USB_PORT_STAT_RESET; + rh_status.wPortChange = 0; + rh_status.wPortChange |= USB_PORT_STAT_C_RESET; + rh_status.wPortStatus &= ~USB_PORT_STAT_RESET; + rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; + OK(0); + + case USB_PORT_FEAT_POWER: + rh_status.wPortStatus |= USB_PORT_STAT_POWER; + OK(0); + + case USB_PORT_FEAT_ENABLE: + rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; + OK(0); + } + break; + + case RH_SET_ADDRESS: + root_hub_devnum = wValue; + OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case USB_DT_DEVICE: + len = sizeof(sl811_rh_dev_des); + bufp = sl811_rh_dev_des; + OK(len); + + case USB_DT_CONFIG: + len = sizeof(sl811_rh_config_des); + bufp = sl811_rh_config_des; + OK(len); + + case USB_DT_STRING: + len = usb_root_hub_string(wValue & 0xff, (int)(long)0, "SL811HS", data, wLength); + if (len > 0) { + bufp = data; + OK(len); + } + + default: + status = -32; + } + break; + + case RH_GET_DESCRIPTOR | USB_TYPE_CLASS: + len = sizeof(sl811_rh_hub_des); + bufp = sl811_rh_hub_des; + OK(len); + + case RH_GET_CONFIGURATION: + bufp[0] = 0x01; + OK(1); + + case RH_SET_CONFIGURATION: + OK(0); + + default: + PDEBUG(1, "unsupported root hub command\n"); + status = -32; + } + + len = min(len, buf_len); + if (data != bufp) + memcpy(data, bufp, len); + + PDEBUG(5, "len = %d, status = %d\n", len, status); + + usb_dev->status = status; + usb_dev->act_len = len; + + return status == 0 ? len : status; +} + +#endif /* CONFIG_USB_SL811HS */ diff --git a/drivers/sm501.c b/drivers/sm501.c new file mode 100644 index 0000000..23db02c --- /dev/null +++ b/drivers/sm501.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * (C) Copyright 2005 + * Martin Krause TQ-Systems GmbH martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Basic video support for SMI SM501 "Voyager" graphic controller + */ + +#include + +#ifdef CONFIG_VIDEO_SM501 + +#include +#include + +#define read8(ptrReg) \ + *(volatile unsigned char *)(sm501.isaBase + ptrReg) + +#define write8(ptrReg,value) \ + *(volatile unsigned char *)(sm501.isaBase + ptrReg) = value + +#define read16(ptrReg) \ + (*(volatile unsigned short *)(sm501.isaBase + ptrReg)) + +#define write16(ptrReg,value) \ + (*(volatile unsigned short *)(sm501.isaBase + ptrReg) = value) + +#define read32(ptrReg) \ + (*(volatile unsigned int *)(sm501.isaBase + ptrReg)) + +#define write32(ptrReg, value) \ + (*(volatile unsigned int *)(sm501.isaBase + ptrReg) = value) + +GraphicDevice sm501; + +/*----------------------------------------------------------------------------- + * SmiSetRegs -- + *----------------------------------------------------------------------------- + */ +static void SmiSetRegs (void) +{ + /* + * The content of the chipset register depends on the board (clocks, + * ...) + */ + const SMI_REGS *preg = board_get_regs (); + while (preg->Index) { + write32 (preg->Index, preg->Value); + /* + * Insert a delay between + */ + udelay (1000); + preg ++; + } +} + +/*----------------------------------------------------------------------------- + * video_hw_init -- + *----------------------------------------------------------------------------- + */ +void *video_hw_init (void) +{ + unsigned int *vm, i; + + memset (&sm501, 0, sizeof (GraphicDevice)); + + /* + * Initialization of the access to the graphic chipset Retreive base + * address of the chipset (see board/RPXClassic/eccx.c) + */ + if ((sm501.isaBase = board_video_init ()) == 0) { + return (NULL); + } + + if ((sm501.frameAdrs = board_video_get_fb ()) == 0) { + return (NULL); + } + + sm501.winSizeX = board_get_width (); + sm501.winSizeY = board_get_height (); + +#if defined(CONFIG_VIDEO_SM501_8BPP) + sm501.gdfIndex = GDF__8BIT_INDEX; + sm501.gdfBytesPP = 1; + +#elif defined(CONFIG_VIDEO_SM501_16BPP) + sm501.gdfIndex = GDF_16BIT_565RGB; + sm501.gdfBytesPP = 2; + +#elif defined(CONFIG_VIDEO_SM501_32BPP) + sm501.gdfIndex = GDF_32BIT_X888RGB; + sm501.gdfBytesPP = 4; +#else +#error Unsupported SM501 BPP +#endif + + sm501.memSize = sm501.winSizeX * sm501.winSizeY * sm501.gdfBytesPP; + + /* Load Smi registers */ + SmiSetRegs (); + + /* (see board/RPXClassic/RPXClassic.c) */ + board_validate_screen (sm501.isaBase); + + /* Clear video memory */ + i = sm501.memSize/4; + vm = (unsigned int *)sm501.frameAdrs; + while(i--) + *vm++ = 0; + + return (&sm501); +} + +/*----------------------------------------------------------------------------- + * video_set_lut -- + *----------------------------------------------------------------------------- + */ +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ +} + +#endif /* CONFIG_VIDEO_SM501 */ diff --git a/drivers/smc91111.c b/drivers/smc91111.c new file mode 100644 index 0000000..060da8f --- /dev/null +++ b/drivers/smc91111.c @@ -0,0 +1,1607 @@ +/*------------------------------------------------------------------------ + . smc91111.c + . This is a driver for SMSC's 91C111 single-chip Ethernet device. + . + . (C) Copyright 2002 + . Sysgo Real-Time Solutions, GmbH + . Rolf Offermanns + . + . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + . Developed by Simple Network Magic Corporation (SNMC) + . Copyright (C) 1996 by Erik Stahlman (ES) + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + . Information contained in this file was obtained from the LAN91C111 + . manual from SMC. To get a copy, if you really want one, you can find + . information under www.smsc.com. + . + . + . "Features" of the SMC chip: + . Integrated PHY/MAC for 10/100BaseT Operation + . Supports internal and external MII + . Integrated 8K packet memory + . EEPROM interface for configuration + . + . Arguments: + . io = for the base address + . irq = for the IRQ + . + . author: + . Erik Stahlman ( erik@vt.edu ) + . Daris A Nevil ( dnevil@snmc.com ) + . + . + . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) + . + . Sources: + . o SMSC LAN91C111 databook (www.smsc.com) + . o smc9194.c by Erik Stahlman + . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) + . + . History: + . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. + . 10/17/01 Marco Hasewinkel Modify for DNP/1110 + . 07/25/01 Woojung Huh Modify for ADS Bitsy + . 04/25/01 Daris A Nevil Initial public release through SMSC + . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 + ----------------------------------------------------------------------------*/ + +#include +#include +#include +#include "smc91111.h" +#include + +#ifdef CONFIG_DRIVER_SMC91111 + +/* Use power-down feature of the chip */ +#define POWER_DOWN 0 + +#define NO_AUTOPROBE + +#define SMC_DEBUG 0 + +#if SMC_DEBUG > 1 +static const char version[] = + "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; +#endif + +/* Autonegotiation timeout in seconds */ +#ifndef CONFIG_SMC_AUTONEG_TIMEOUT +#define CONFIG_SMC_AUTONEG_TIMEOUT 10 +#endif + +/*------------------------------------------------------------------------ + . + . Configuration options, for the experienced user to change. + . + -------------------------------------------------------------------------*/ + +/* + . Wait time for memory to be free. This probably shouldn't be + . tuned that much, as waiting for this means nothing else happens + . in the system +*/ +#define MEMORY_WAIT_TIME 16 + + +#if (SMC_DEBUG > 2 ) +#define PRINTK3(args...) printf(args) +#else +#define PRINTK3(args...) +#endif + +#if SMC_DEBUG > 1 +#define PRINTK2(args...) printf(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef SMC_DEBUG +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + + +/*------------------------------------------------------------------------ + . + . The internal workings of the driver. If you are changing anything + . here with the SMC stuff, you should have the datasheet and know + . what you are doing. + . + -------------------------------------------------------------------------*/ +#define CARDNAME "LAN91C111" + +/* Memory sizing constant */ +#define LAN91C111_MEMORY_MULTIPLIER (1024*2) + +#ifndef CONFIG_SMC91111_BASE +#define CONFIG_SMC91111_BASE 0x20000300 +#endif + +#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE + +#define SMC_DEV_NAME "SMC91111" +#define SMC_PHY_ADDR 0x0000 +#define SMC_ALLOC_MAX_TRY 5 +#define SMC_TX_TIMEOUT 30 + +#define SMC_PHY_CLOCK_DELAY 1000 + +#define ETH_ZLEN 60 + +#ifdef CONFIG_SMC_USE_32_BIT +#define USE_32_BIT 1 +#else +#undef USE_32_BIT +#endif +/*----------------------------------------------------------------- + . + . The driver can be entered at any of the following entry points. + . + .------------------------------------------------------------------ */ + +extern int eth_init(bd_t *bd); +extern void eth_halt(void); +extern int eth_rx(void); +extern int eth_send(volatile void *packet, int length); + + +/* + . This is called by register_netdev(). It is responsible for + . checking the portlist for the SMC9000 series chipset. If it finds + . one, then it will initialize the device, find the hardware information, + . and sets up the appropriate device parameters. + . NOTE: Interrupts are *OFF* when this procedure is called. + . + . NB:This shouldn't be static since it is referred to externally. +*/ +int smc_init(void); + +/* + . This is called by unregister_netdev(). It is responsible for + . cleaning up before the driver is finally unregistered and discarded. +*/ +void smc_destructor(void); + +/* + . The kernel calls this function when someone wants to use the device, + . typically 'ifconfig ethX up'. +*/ +static int smc_open(bd_t *bd); + + +/* + . This is called by the kernel in response to 'ifconfig ethX down'. It + . is responsible for cleaning up everything that the open routine + . does, and maybe putting the card into a powerdown state. +*/ +static int smc_close(void); + +/* + . Configures the PHY through the MII Management interface +*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static void smc_phy_configure(void); +#endif /* !CONFIG_SMC91111_EXT_PHY */ + +/* + . This is a separate procedure to handle the receipt of a packet, to + . leave the interrupt code looking slightly cleaner +*/ +static int smc_rcv(void); + +/* See if a MAC address is defined in the current environment. If so use it. If not + . print a warning and set the environment and other globals with the default. + . If an EEPROM is present it really should be consulted. +*/ +int smc_get_ethaddr(bd_t *bd); +int get_rom_mac(char *v_rom_mac); + +/* + ------------------------------------------------------------ + . + . Internal routines + . + ------------------------------------------------------------ +*/ + +#ifdef CONFIG_SMC_USE_IOFUNCS +/* + * input and output functions + * + * Implemented due to inx,outx macros accessing the device improperly + * and putting the device into an unkown state. + * + * For instance, on Sharp LPD7A400 SDK, affects were chip memory + * could not be free'd (hence the alloc failures), duplicate packets, + * packets being corrupt (shifted) on the wire, etc. Switching to the + * inx,outx functions fixed this problem. + */ +static inline word SMC_inw(dword offset); +static inline void SMC_outw(word value, dword offset); +static inline byte SMC_inb(dword offset); +static inline void SMC_outb(byte value, dword offset); +static inline void SMC_insw(dword offset, volatile uchar* buf, dword len); +static inline void SMC_outsw(dword offset, uchar* buf, dword len); + +#define barrier() __asm__ __volatile__("": : :"memory") + +static inline word SMC_inw(dword offset) +{ + word v; + v = *((volatile word*)(SMC_BASE_ADDRESS+offset)); + barrier(); *(volatile u32*)(0xc0000000); + return v; +} + +static inline void SMC_outw(word value, dword offset) +{ + *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value; + barrier(); *(volatile u32*)(0xc0000000); +} + +static inline byte SMC_inb(dword offset) +{ + word _w; + + _w = SMC_inw(offset & ~((dword)1)); + return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); +} + +static inline void SMC_outb(byte value, dword offset) +{ + word _w; + + _w = SMC_inw(offset & ~((dword)1)); + if (offset & 1) + *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff); + else + *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00); +} + +static inline void SMC_insw(dword offset, volatile uchar* buf, dword len) +{ + while (len-- > 0) { + *((word*)buf)++ = SMC_inw(offset); + barrier(); *((volatile u32*)(0xc0000000)); + } +} + +static inline void SMC_outsw(dword offset, uchar* buf, dword len) +{ + while (len-- > 0) { + SMC_outw(*((word*)buf)++, offset); + barrier(); *(volatile u32*)(0xc0000000); + } +} +#endif /* CONFIG_SMC_USE_IOFUNCS */ + +static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8}; + +/* + * This function must be called before smc_open() if you want to override + * the default mac address. + */ + +void smc_set_mac_addr(const char *addr) { + int i; + + for (i=0; i < sizeof(smc_mac_addr); i++){ + smc_mac_addr[i] = addr[i]; + } +} + +/* + * smc_get_macaddr is no longer used. If you want to override the default + * mac address, call smc_get_mac_addr as a part of the board initialization. + */ + +#if 0 +void smc_get_macaddr( byte *addr ) { + /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ + unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); + int i; + + + for (i=0; i<6; i++) { + addr[0] = *(dnp1110_mac+0); + addr[1] = *(dnp1110_mac+1); + addr[2] = *(dnp1110_mac+2); + addr[3] = *(dnp1110_mac+3); + addr[4] = *(dnp1110_mac+4); + addr[5] = *(dnp1110_mac+5); + } +} +#endif /* 0 */ + +/*********************************************** + * Show available memory * + ***********************************************/ +void dump_memory_info(void) +{ + word mem_info; + word old_bank; + + old_bank = SMC_inw(BANK_SELECT)&0xF; + + SMC_SELECT_BANK(0); + mem_info = SMC_inw( MIR_REG ); + PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048); + + SMC_SELECT_BANK(old_bank); +} +/* + . A rather simple routine to print out a packet for debugging purposes. +*/ +#if SMC_DEBUG > 2 +static void print_packet( byte *, int ); +#endif + +#define tx_done(dev) 1 + + +/* this does a soft reset on the device */ +static void smc_reset( void ); + +/* Enable Interrupts, Receive, and Transmit */ +static void smc_enable( void ); + +/* this puts the device in an inactive state */ +static void smc_shutdown( void ); + +/* Routines to Read and Write the PHY Registers across the + MII Management Interface +*/ + +#ifndef CONFIG_SMC91111_EXT_PHY +static word smc_read_phy_register(byte phyreg); +static void smc_write_phy_register(byte phyreg, word phydata); +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +static int poll4int (byte mask, int timeout) +{ + int tmo = get_timer (0) + timeout * CFG_HZ; + int is_timeout = 0; + word old_bank = SMC_inw (BSR_REG); + + PRINTK2 ("Polling...\n"); + SMC_SELECT_BANK (2); + while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) { + if (get_timer (0) >= tmo) { + is_timeout = 1; + break; + } + } + + /* restore old bank selection */ + SMC_SELECT_BANK (old_bank); + + if (is_timeout) + return 1; + else + return 0; +} + +/* Only one release command at a time, please */ +static inline void smc_wait_mmu_release_complete (void) +{ + int count = 0; + + /* assume bank 2 selected */ + while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + udelay (1); /* Wait until not busy */ + if (++count > 200) + break; + } +} + +/* + . Function: smc_reset( void ) + . Purpose: + . This sets the SMC91111 chip to its normal state, hopefully from whatever + . mess that any other DOS driver has put it in. + . + . Maybe I should reset more registers to defaults in here? SOFTRST should + . do that for me. + . + . Method: + . 1. send a SOFT RESET + . 2. wait for it to finish + . 3. enable autorelease mode + . 4. reset the memory management unit + . 5. clear all interrupts + . +*/ +static void smc_reset (void) +{ + PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); + + /* This resets the registers mostly to defaults, but doesn't + affect EEPROM. That seems unnecessary */ + SMC_SELECT_BANK (0); + SMC_outw (RCR_SOFTRST, RCR_REG); + + /* Setup the Configuration Register */ + /* This is necessary because the CONFIG_REG is not affected */ + /* by a soft reset */ + + SMC_SELECT_BANK (1); +#if defined(CONFIG_SMC91111_EXT_PHY) + SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); +#else + SMC_outw (CONFIG_DEFAULT, CONFIG_REG); +#endif + + + /* Release from possible power-down state */ + /* Configuration register is not affected by Soft Reset */ + SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG); + + SMC_SELECT_BANK (0); + + /* this should pause enough for the chip to be happy */ + udelay (10); + + /* Disable transmit and receive functionality */ + SMC_outw (RCR_CLEAR, RCR_REG); + SMC_outw (TCR_CLEAR, TCR_REG); + + /* set the control register */ + SMC_SELECT_BANK (1); + SMC_outw (CTL_DEFAULT, CTL_REG); + + /* Reset the MMU */ + SMC_SELECT_BANK (2); + smc_wait_mmu_release_complete (); + SMC_outw (MC_RESET, MMU_CMD_REG); + while (SMC_inw (MMU_CMD_REG) & MC_BUSY) + udelay (1); /* Wait until not busy */ + + /* Note: It doesn't seem that waiting for the MMU busy is needed here, + but this is a place where future chipsets _COULD_ break. Be wary + of issuing another MMU command right after this */ + + /* Disable all interrupts */ + SMC_outb (0, IM_REG); +} + +/* + . Function: smc_enable + . Purpose: let the chip talk to the outside work + . Method: + . 1. Enable the transmitter + . 2. Enable the receiver + . 3. Enable interrupts +*/ +static void smc_enable() +{ + PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); + SMC_SELECT_BANK( 0 ); + /* see the header file for options in TCR/RCR DEFAULT*/ + SMC_outw( TCR_DEFAULT, TCR_REG ); + SMC_outw( RCR_DEFAULT, RCR_REG ); + + /* clear MII_DIS */ +/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ +} + +/* + . Function: smc_shutdown + . Purpose: closes down the SMC91xxx chip. + . Method: + . 1. zero the interrupt mask + . 2. clear the enable receive flag + . 3. clear the enable xmit flags + . + . TODO: + . (1) maybe utilize power down mode. + . Why not yet? Because while the chip will go into power down mode, + . the manual says that it will wake up in response to any I/O requests + . in the register space. Empirical results do not show this working. +*/ +static void smc_shutdown() +{ + PRINTK2(CARDNAME ": smc_shutdown\n"); + + /* no more interrupts for me */ + SMC_SELECT_BANK( 2 ); + SMC_outb( 0, IM_REG ); + + /* and tell the card to stay away from that nasty outside world */ + SMC_SELECT_BANK( 0 ); + SMC_outb( RCR_CLEAR, RCR_REG ); + SMC_outb( TCR_CLEAR, TCR_REG ); +} + + +/* + . Function: smc_hardware_send_packet(struct net_device * ) + . Purpose: + . This sends the actual packet to the SMC9xxx chip. + . + . Algorithm: + . First, see if a saved_skb is available. + . ( this should NOT be called if there is no 'saved_skb' + . Now, find the packet number that the chip allocated + . Point the data pointers at it in memory + . Set the length word in the chip's memory + . Dump the packet to chip memory + . Check if a last byte is needed ( odd length packet ) + . if so, set the control flag right + . Tell the card to send it + . Enable the transmit interrupt, so I know if it failed + . Free the kernel data if I actually sent it. +*/ +static int smc_send_packet (volatile void *packet, int packet_length) +{ + byte packet_no; + unsigned long ioaddr; + byte *buf; + int length; + int numPages; + int try = 0; + int time_out; + byte status; + byte saved_pnr; + word saved_ptr; + + /* save PTR and PNR registers before manipulation */ + SMC_SELECT_BANK (2); + saved_pnr = SMC_inb( PN_REG ); + saved_ptr = SMC_inw( PTR_REG ); + + PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); + + length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; + + /* allocate memory + ** The MMU wants the number of pages to be the number of 256 bytes + ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) + ** + ** The 91C111 ignores the size bits, but the code is left intact + ** for backwards and future compatibility. + ** + ** Pkt size for allocating is data length +6 (for additional status + ** words, length and ctl!) + ** + ** If odd size then last byte is included in this header. + */ + numPages = ((length & 0xfffe) + 6); + numPages >>= 8; /* Divide by 256 */ + + if (numPages > 7) { + printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); + return 0; + } + + /* now, try to allocate the memory */ + SMC_SELECT_BANK (2); + SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG); + + /* FIXME: the ALLOC_INT bit never gets set * + * so the following will always give a * + * memory allocation error. * + * same code works in armboot though * + * -ro + */ + +again: + try++; + time_out = MEMORY_WAIT_TIME; + do { + status = SMC_inb (SMC91111_INT_REG); + if (status & IM_ALLOC_INT) { + /* acknowledge the interrupt */ + SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG); + break; + } + } while (--time_out); + + if (!time_out) { + PRINTK2 ("%s: memory allocation, try %d failed ...\n", + SMC_DEV_NAME, try); + if (try < SMC_ALLOC_MAX_TRY) + goto again; + else + return 0; + } + + PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", + SMC_DEV_NAME, try); + + /* I can send the packet now.. */ + + ioaddr = SMC_BASE_ADDRESS; + + buf = (byte *) packet; + + /* If I get here, I _know_ there is a packet slot waiting for me */ + packet_no = SMC_inb (AR_REG); + if (packet_no & AR_FAILED) { + /* or isn't there? BAD CHIP! */ + printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); + return 0; + } + + /* we have a packet address, so tell the card to use it */ +#ifndef CONFIG_XAENIAX + SMC_outb (packet_no, PN_REG); +#else + /* On Xaeniax board, we can't use SMC_outb here because that way + * the Allocate MMU command will end up written to the command register + * as well, which will lead to a problem. + */ + SMC_outl (packet_no << 16, 0); +#endif + /* do not write new ptr value if Write data fifo not empty */ + while ( saved_ptr & PTR_NOTEMPTY ) + printf ("Write data fifo not empty!\n"); + + /* point to the beginning of the packet */ + SMC_outw (PTR_AUTOINC, PTR_REG); + + PRINTK3 ("%s: Trying to xmit packet of length %x\n", + SMC_DEV_NAME, length); + +#if SMC_DEBUG > 2 + printf ("Transmitting Packet\n"); + print_packet (buf, length); +#endif + + /* send the packet length ( +6 for status, length and ctl byte ) + and the status word ( set to zeros ) */ +#ifdef USE_32_BIT + SMC_outl ((length + 6) << 16, SMC91111_DATA_REG); +#else + SMC_outw (0, SMC91111_DATA_REG); + /* send the packet length ( +6 for status words, length, and ctl */ + SMC_outw ((length + 6), SMC91111_DATA_REG); +#endif + + /* send the actual data + . I _think_ it's faster to send the longs first, and then + . mop up by sending the last word. It depends heavily + . on alignment, at least on the 486. Maybe it would be + . a good idea to check which is optimal? But that could take + . almost as much time as is saved? + */ +#ifdef USE_32_BIT + SMC_outsl (SMC91111_DATA_REG, buf, length >> 2); +#ifndef CONFIG_XAENIAX + if (length & 0x2) + SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), + SMC91111_DATA_REG); +#else + /* On XANEIAX, we can only use 32-bit writes, so we need to handle + * unaligned tail part specially. The standard code doesn't work. + */ + if ((length & 3) == 3) { + u16 * ptr = (u16*) &buf[length-3]; + SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16), + SMC91111_DATA_REG); + } else if ((length & 2) == 2) { + u16 * ptr = (u16*) &buf[length-2]; + SMC_outl(*ptr, SMC91111_DATA_REG); + } else if (length & 1) { + SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG); + } else { + SMC_outl(0, SMC91111_DATA_REG); + } +#endif +#else + SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1); +#endif /* USE_32_BIT */ + +#ifndef CONFIG_XAENIAX + /* Send the last byte, if there is one. */ + if ((length & 1) == 0) { + SMC_outw (0, SMC91111_DATA_REG); + } else { + SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG); + } +#endif + + /* and let the chipset deal with it */ + SMC_outw (MC_ENQUEUE, MMU_CMD_REG); + + /* poll for TX INT */ + /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */ + /* poll for TX_EMPTY INT - autorelease enabled */ + if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { + /* sending failed */ + PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); + + /* release packet */ + /* no need to release, MMU does that now */ +#ifdef CONFIG_XAENIAX + SMC_outw (MC_FREEPKT, MMU_CMD_REG); +#endif + + /* wait for MMU getting ready (low) */ + while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + + + return 0; + } else { + /* ack. int */ + SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG); + /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ + PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, + length); + + /* release packet */ + /* no need to release, MMU does that now */ +#ifdef CONFIG_XAENIAX + SMC_outw (MC_FREEPKT, MMU_CMD_REG); +#endif + + /* wait for MMU getting ready (low) */ + while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + + + } + + /* restore previously saved registers */ +#ifndef CONFIG_XAENIAX + SMC_outb( saved_pnr, PN_REG ); +#else + /* On Xaeniax board, we can't use SMC_outb here because that way + * the Allocate MMU command will end up written to the command register + * as well, which will lead to a problem. + */ + SMC_outl(saved_pnr << 16, 0); +#endif + SMC_outw( saved_ptr, PTR_REG ); + + return length; +} + +/*------------------------------------------------------------------------- + | + | smc_destructor( struct net_device * dev ) + | Input parameters: + | dev, pointer to the device structure + | + | Output: + | None. + | + --------------------------------------------------------------------------- +*/ +void smc_destructor() +{ + PRINTK2(CARDNAME ": smc_destructor\n"); +} + + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc .. + * + */ +static int smc_open (bd_t * bd) +{ + int i, err; + + PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME); + + /* reset the hardware */ + smc_reset (); + smc_enable (); + + /* Configure the PHY */ +#ifndef CONFIG_SMC91111_EXT_PHY + smc_phy_configure (); +#endif + + /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ +/* SMC_SELECT_BANK(0); */ +/* SMC_outw(0, RPC_REG); */ + SMC_SELECT_BANK (1); + + err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ + if (err < 0) { + memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */ + return (-1); /* upper code ignores this, but NOT bi_enetaddr */ + } +#ifdef USE_32_BIT + for (i = 0; i < 6; i += 2) { + word address; + + address = smc_mac_addr[i + 1] << 8; + address |= smc_mac_addr[i]; + SMC_outw (address, (ADDR0_REG + i)); + } +#else + for (i = 0; i < 6; i++) + SMC_outb (smc_mac_addr[i], (ADDR0_REG + i)); +#endif + + return 0; +} + +/*------------------------------------------------------------- + . + . smc_rcv - receive a packet from the card + . + . There is ( at least ) a packet waiting to be read from + . chip-memory. + . + . o Read the status + . o If an error, record it + . o otherwise, read in the packet + -------------------------------------------------------------- +*/ +static int smc_rcv() +{ + int packet_number; + word status; + word packet_length; + int is_error = 0; +#ifdef USE_32_BIT + dword stat_len; +#endif + byte saved_pnr; + word saved_ptr; + + SMC_SELECT_BANK(2); + /* save PTR and PTR registers */ + saved_pnr = SMC_inb( PN_REG ); + saved_ptr = SMC_inw( PTR_REG ); + + packet_number = SMC_inw( RXFIFO_REG ); + + if ( packet_number & RXFIFO_REMPTY ) { + + return 0; + } + + PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); + /* start reading from the start of the packet */ + SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); + + /* First two words are status and packet_length */ +#ifdef USE_32_BIT + stat_len = SMC_inl(SMC91111_DATA_REG); + status = stat_len & 0xffff; + packet_length = stat_len >> 16; +#else + status = SMC_inw( SMC91111_DATA_REG ); + packet_length = SMC_inw( SMC91111_DATA_REG ); +#endif + + packet_length &= 0x07ff; /* mask off top bits */ + + PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); + + if ( !(status & RS_ERRORS ) ){ + /* Adjust for having already read the first two words */ + packet_length -= 4; /*4; */ + + + /* set odd length for bug in LAN91C111, */ + /* which never sets RS_ODDFRAME */ + /* TODO ? */ + + +#ifdef USE_32_BIT + PRINTK3(" Reading %d dwords (and %d bytes) \n", + packet_length >> 2, packet_length & 3 ); + /* QUESTION: Like in the TX routine, do I want + to send the DWORDs or the bytes first, or some + mixture. A mixture might improve already slow PIO + performance */ + SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 ); + /* read the left over bytes */ + if (packet_length & 3) { + int i; + + byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3)); + dword leftover = SMC_inl(SMC91111_DATA_REG); + for (i=0; i<(packet_length & 3); i++) + *tail++ = (byte) (leftover >> (8*i)) & 0xff; + } +#else + PRINTK3(" Reading %d words and %d byte(s) \n", + (packet_length >> 1 ), packet_length & 1 ); + SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1); + +#endif /* USE_32_BIT */ + +#if SMC_DEBUG > 2 + printf("Receiving Packet\n"); + print_packet( NetRxPackets[0], packet_length ); +#endif + } else { + /* error ... */ + /* TODO ? */ + is_error = 1; + } + + while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) + udelay(1); /* Wait until not busy */ + + /* error or good, tell the card to get rid of this packet */ + SMC_outw( MC_RELEASE, MMU_CMD_REG ); + + while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) + udelay(1); /* Wait until not busy */ + + /* restore saved registers */ +#ifndef CONFIG_XAENIAX + SMC_outb( saved_pnr, PN_REG ); +#else + /* On Xaeniax board, we can't use SMC_outb here because that way + * the Allocate MMU command will end up written to the command register + * as well, which will lead to a problem. + */ + SMC_outl( saved_pnr << 16, 0); +#endif + SMC_outw( saved_ptr, PTR_REG ); + + if (!is_error) { + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[0], packet_length); + return packet_length; + } else { + return 0; + } + +} + + +/*---------------------------------------------------- + . smc_close + . + . this makes the board clean up everything that it can + . and not talk to the outside world. Caused by + . an 'ifconfig ethX down' + . + -----------------------------------------------------*/ +static int smc_close() +{ + PRINTK2("%s: smc_close\n", SMC_DEV_NAME); + + /* clear everything */ + smc_shutdown(); + + return 0; +} + + +#if 0 +/*------------------------------------------------------------ + . Modify a bit in the LAN91C111 register set + .-------------------------------------------------------------*/ +static word smc_modify_regbit(int bank, int ioaddr, int reg, + unsigned int bit, int val) +{ + word regval; + + SMC_SELECT_BANK( bank ); + + regval = SMC_inw( reg ); + if (val) + regval |= bit; + else + regval &= ~bit; + + SMC_outw( regval, 0 ); + return(regval); +} + + +/*------------------------------------------------------------ + . Retrieve a bit in the LAN91C111 register set + .-------------------------------------------------------------*/ +static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit) +{ + SMC_SELECT_BANK( bank ); + if ( SMC_inw( reg ) & bit) + return(1); + else + return(0); +} + + +/*------------------------------------------------------------ + . Modify a LAN91C111 register (word access only) + .-------------------------------------------------------------*/ +static void smc_modify_reg(int bank, int ioaddr, int reg, word val) +{ + SMC_SELECT_BANK( bank ); + SMC_outw( val, reg ); +} + + +/*------------------------------------------------------------ + . Retrieve a LAN91C111 register (word access only) + .-------------------------------------------------------------*/ +static int smc_get_reg(int bank, int ioaddr, int reg) +{ + SMC_SELECT_BANK( bank ); + return(SMC_inw( reg )); +} + +#endif /* 0 */ + +/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ + +#if (SMC_DEBUG > 2 ) + +/*------------------------------------------------------------ + . Debugging function for viewing MII Management serial bitstream + .-------------------------------------------------------------*/ +static void smc_dump_mii_stream (byte * bits, int size) +{ + int i; + + printf ("BIT#:"); + for (i = 0; i < size; ++i) { + printf ("%d", i % 10); + } + + printf ("\nMDOE:"); + for (i = 0; i < size; ++i) { + if (bits[i] & MII_MDOE) + printf ("1"); + else + printf ("0"); + } + + printf ("\nMDO :"); + for (i = 0; i < size; ++i) { + if (bits[i] & MII_MDO) + printf ("1"); + else + printf ("0"); + } + + printf ("\nMDI :"); + for (i = 0; i < size; ++i) { + if (bits[i] & MII_MDI) + printf ("1"); + else + printf ("0"); + } + + printf ("\n"); +} +#endif + +/*------------------------------------------------------------ + . Reads a register from the MII Management serial interface + .-------------------------------------------------------------*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static word smc_read_phy_register (byte phyreg) +{ + int oldBank; + int i; + byte mask; + word mii_reg; + byte bits[64]; + int clk_idx = 0; + int input_idx; + word phydata; + byte phyaddr = SMC_PHY_ADDR; + + /* 32 consecutive ones on MDO to establish sync */ + for (i = 0; i < 32; ++i) + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Start code <01> */ + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Read command <10> */ + bits[clk_idx++] = MII_MDOE | MII_MDO; + bits[clk_idx++] = MII_MDOE; + + /* Output the PHY address, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyaddr & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Output the phy register number, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyreg & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Tristate and turnaround (2 bit times) */ + bits[clk_idx++] = 0; + /*bits[clk_idx++] = 0; */ + + /* Input starts at this bit time */ + input_idx = clk_idx; + + /* Will input 16 bits */ + for (i = 0; i < 16; ++i) + bits[clk_idx++] = 0; + + /* Final clock bit */ + bits[clk_idx++] = 0; + + /* Save the current bank */ + oldBank = SMC_inw (BANK_SELECT); + + /* Select bank 3 */ + SMC_SELECT_BANK (3); + + /* Get the current MII register value */ + mii_reg = SMC_inw (MII_REG); + + /* Turn off all MII Interface bits */ + mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); + + /* Clock all 64 cycles */ + for (i = 0; i < sizeof bits; ++i) { + /* Clock Low - output data */ + SMC_outw (mii_reg | bits[i], MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + + /* Clock Hi - input data */ + SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + bits[i] |= SMC_inw (MII_REG) & MII_MDI; + } + + /* Return to idle state */ + /* Set clock to low, data to low, and output tristated */ + SMC_outw (mii_reg, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + /* Restore original bank select */ + SMC_SELECT_BANK (oldBank); + + /* Recover input data */ + phydata = 0; + for (i = 0; i < 16; ++i) { + phydata <<= 1; + + if (bits[input_idx++] & MII_MDI) + phydata |= 0x0001; + } + +#if (SMC_DEBUG > 2 ) + printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", + phyaddr, phyreg, phydata); + smc_dump_mii_stream (bits, sizeof bits); +#endif + + return (phydata); +} + + +/*------------------------------------------------------------ + . Writes a register to the MII Management serial interface + .-------------------------------------------------------------*/ +static void smc_write_phy_register (byte phyreg, word phydata) +{ + int oldBank; + int i; + word mask; + word mii_reg; + byte bits[65]; + int clk_idx = 0; + byte phyaddr = SMC_PHY_ADDR; + + /* 32 consecutive ones on MDO to establish sync */ + for (i = 0; i < 32; ++i) + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Start code <01> */ + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Write command <01> */ + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Output the PHY address, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyaddr & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Output the phy register number, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyreg & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Tristate and turnaround (2 bit times) */ + bits[clk_idx++] = 0; + bits[clk_idx++] = 0; + + /* Write out 16 bits of data, msb first */ + mask = 0x8000; + for (i = 0; i < 16; ++i) { + if (phydata & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Final clock bit (tristate) */ + bits[clk_idx++] = 0; + + /* Save the current bank */ + oldBank = SMC_inw (BANK_SELECT); + + /* Select bank 3 */ + SMC_SELECT_BANK (3); + + /* Get the current MII register value */ + mii_reg = SMC_inw (MII_REG); + + /* Turn off all MII Interface bits */ + mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); + + /* Clock all cycles */ + for (i = 0; i < sizeof bits; ++i) { + /* Clock Low - output data */ + SMC_outw (mii_reg | bits[i], MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + + /* Clock Hi - input data */ + SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + bits[i] |= SMC_inw (MII_REG) & MII_MDI; + } + + /* Return to idle state */ + /* Set clock to low, data to low, and output tristated */ + SMC_outw (mii_reg, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + /* Restore original bank select */ + SMC_SELECT_BANK (oldBank); + +#if (SMC_DEBUG > 2 ) + printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", + phyaddr, phyreg, phydata); + smc_dump_mii_stream (bits, sizeof bits); +#endif +} +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +/*------------------------------------------------------------ + . Waits the specified number of milliseconds - kernel friendly + .-------------------------------------------------------------*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static void smc_wait_ms(unsigned int ms) +{ + udelay(ms*1000); +} +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +/*------------------------------------------------------------ + . Configures the specified PHY using Autonegotiation. Calls + . smc_phy_fixed() if the user has requested a certain config. + .-------------------------------------------------------------*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static void smc_phy_configure () +{ + int timeout; + byte phyaddr; + word my_phy_caps; /* My PHY capabilities */ + word my_ad_caps; /* My Advertised capabilities */ + word status = 0; /*;my status = 0 */ + int failed = 0; + + PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); + + + /* Get the detected phy address */ + phyaddr = SMC_PHY_ADDR; + + /* Reset the PHY, setting all other bits to zero */ + smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST); + + /* Wait for the reset to complete, or time out */ + timeout = 6; /* Wait up to 3 seconds */ + while (timeout--) { + if (!(smc_read_phy_register (PHY_CNTL_REG) + & PHY_CNTL_RST)) { + /* reset complete */ + break; + } + + smc_wait_ms (500); /* wait 500 millisecs */ + } + + if (timeout < 1) { + printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); + goto smc_phy_configure_exit; + } + + /* Read PHY Register 18, Status Output */ + /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ + + /* Enable PHY Interrupts (for register 18) */ + /* Interrupts listed here are disabled */ + smc_write_phy_register (PHY_MASK_REG, 0xffff); + + /* Configure the Receive/Phy Control register */ + SMC_SELECT_BANK (0); + SMC_outw (RPC_DEFAULT, RPC_REG); + + /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ + my_phy_caps = smc_read_phy_register (PHY_STAT_REG); + my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ + + if (my_phy_caps & PHY_STAT_CAP_T4) + my_ad_caps |= PHY_AD_T4; + + if (my_phy_caps & PHY_STAT_CAP_TXF) + my_ad_caps |= PHY_AD_TX_FDX; + + if (my_phy_caps & PHY_STAT_CAP_TXH) + my_ad_caps |= PHY_AD_TX_HDX; + + if (my_phy_caps & PHY_STAT_CAP_TF) + my_ad_caps |= PHY_AD_10_FDX; + + if (my_phy_caps & PHY_STAT_CAP_TH) + my_ad_caps |= PHY_AD_10_HDX; + + /* Update our Auto-Neg Advertisement Register */ + smc_write_phy_register (PHY_AD_REG, my_ad_caps); + + /* Read the register back. Without this, it appears that when */ + /* auto-negotiation is restarted, sometimes it isn't ready and */ + /* the link does not come up. */ + smc_read_phy_register(PHY_AD_REG); + + PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); + PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); + + /* Restart auto-negotiation process in order to advertise my caps */ + smc_write_phy_register (PHY_CNTL_REG, + PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); + + /* Wait for the auto-negotiation to complete. This may take from */ + /* 2 to 3 seconds. */ + /* Wait for the reset to complete, or time out */ + timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; + while (timeout--) { + + status = smc_read_phy_register (PHY_STAT_REG); + if (status & PHY_STAT_ANEG_ACK) { + /* auto-negotiate complete */ + break; + } + + smc_wait_ms (500); /* wait 500 millisecs */ + + /* Restart auto-negotiation if remote fault */ + if (status & PHY_STAT_REM_FLT) { + printf ("%s: PHY remote fault detected\n", + SMC_DEV_NAME); + + /* Restart auto-negotiation */ + printf ("%s: PHY restarting auto-negotiation\n", + SMC_DEV_NAME); + smc_write_phy_register (PHY_CNTL_REG, + PHY_CNTL_ANEG_EN | + PHY_CNTL_ANEG_RST | + PHY_CNTL_SPEED | + PHY_CNTL_DPLX); + } + } + + if (timeout < 1) { + printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); + failed = 1; + } + + /* Fail if we detected an auto-negotiate remote fault */ + if (status & PHY_STAT_REM_FLT) { + printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); + failed = 1; + } + + /* Re-Configure the Receive/Phy Control register */ + SMC_outw (RPC_DEFAULT, RPC_REG); + +smc_phy_configure_exit: ; + +} +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +#if SMC_DEBUG > 2 +static void print_packet( byte * buf, int length ) +{ + int i; + int remainder; + int lines; + + printf("Packet of length %d \n", length ); + +#if SMC_DEBUG > 3 + lines = length / 16; + remainder = length % 16; + + for ( i = 0; i < lines ; i ++ ) { + int cur; + + for ( cur = 0; cur < 8; cur ++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + printf("%02x%02x ", a, b ); + } + printf("\n"); + } + for ( i = 0; i < remainder/2 ; i++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + printf("%02x%02x ", a, b ); + } + printf("\n"); +#endif +} +#endif + +int eth_init(bd_t *bd) { + return (smc_open(bd)); +} + +void eth_halt() { + smc_close(); +} + +int eth_rx() { + return smc_rcv(); +} + +int eth_send(volatile void *packet, int length) { + return smc_send_packet(packet, length); +} + +int smc_get_ethaddr (bd_t * bd) +{ + int env_size, rom_valid, env_present = 0, reg; + char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66"; + uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6]; + + env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); + if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */ + printf ("\n*** ERROR: ethaddr is not set properly!!\n"); + return (-1); + } + + if (env_size > 0) { + env_present = 1; + s = s_env_mac; + } + + for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */ + v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */ + + if (!env_present) { /* if NO env */ + if (rom_valid) { /* but ROM is valid */ + v_mac = v_rom_mac; + sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", + v_mac[0], v_mac[1], v_mac[2], v_mac[3], + v_mac[4], v_mac[5]); + setenv ("ethaddr", s_env_mac); + } else { /* no env, bad ROM */ + printf ("\n*** ERROR: ethaddr is NOT set !!\n"); + return (-1); + } + } else { /* good env, don't care ROM */ + v_mac = v_env_mac; /* always use a good env over a ROM */ + } + + if (env_present && rom_valid) { /* if both env and ROM are good */ + if (memcmp (v_env_mac, v_rom_mac, 6) != 0) { + printf ("\nWarning: MAC addresses don't match:\n"); + printf ("\tHW MAC address: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + v_rom_mac[0], v_rom_mac[1], + v_rom_mac[2], v_rom_mac[3], + v_rom_mac[4], v_rom_mac[5] ); + printf ("\t\"ethaddr\" value: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + v_env_mac[0], v_env_mac[1], + v_env_mac[2], v_env_mac[3], + v_env_mac[4], v_env_mac[5]) ; + debug ("### Set MAC addr from environment\n"); + } + } + memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */ + smc_set_mac_addr (v_mac); /* use old function to update smc default */ + PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1], + v_mac[2], v_mac[3], v_mac[4], v_mac[5]); + return (0); +} + +int get_rom_mac (char *v_rom_mac) +{ +#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ + char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; + + memcpy (v_rom_mac, hw_mac_addr, 6); + return (1); +#else + int i; + int valid_mac = 0; + + SMC_SELECT_BANK (1); + for (i=0; i<6; i++) + { + v_rom_mac[i] = SMC_inb ((ADDR0_REG + i)); + valid_mac |= v_rom_mac[i]; + } + + return (valid_mac ? 1 : 0); +#endif +} +#endif /* CONFIG_DRIVER_SMC91111 */ diff --git a/drivers/smc91111.h b/drivers/smc91111.h new file mode 100644 index 0000000..cf08582 --- /dev/null +++ b/drivers/smc91111.h @@ -0,0 +1,715 @@ +/*------------------------------------------------------------------------ + . smc91111.h - macros for the LAN91C111 Ethernet Driver + . + . (C) Copyright 2002 + . Sysgo Real-Time Solutions, GmbH + . Rolf Offermanns + . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + . Developed by Simple Network Magic Corporation (SNMC) + . Copyright (C) 1996 by Erik Stahlman (ES) + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + . This file contains register information and access macros for + . the LAN91C111 single chip ethernet controller. It is a modified + . version of the smc9194.h file. + . + . Information contained in this file was obtained from the LAN91C111 + . manual from SMC. To get a copy, if you really want one, you can find + . information under www.smsc.com. + . + . Authors + . Erik Stahlman ( erik@vt.edu ) + . Daris A Nevil ( dnevil@snmc.com ) + . + . History + . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device + . + ---------------------------------------------------------------------------*/ +#ifndef _SMC91111_H_ +#define _SMC91111_H_ + +#include +#include + +/* + * This function may be called by the board specific initialisation code + * in order to override the default mac address. + */ + +void smc_set_mac_addr(const char *addr); + + +/* I want some simple types */ + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; + +/* + . DEBUGGING LEVELS + . + . 0 for normal operation + . 1 for slightly more details + . >2 for various levels of increasingly useless information + . 2 for interrupt tracking, status flags + . 3 for packet info + . 4 for complete packet dumps +*/ +/*#define SMC_DEBUG 0 */ + +/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ + +#define SMC_IO_EXTENT 16 + +#ifdef CONFIG_PXA250 + +#ifdef CONFIG_XSENGINE +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1)))) +#define SMC_inb(p) ({ \ + unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \ + unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ + if (__p & 2) __v >>= 8; \ + else __v &= 0xff; \ + __v; }) +#elif defined(CONFIG_XAENIAX) +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inw(z) ({ \ + unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \ + unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ + if (__p & 3) __v >>= 16; \ + else __v &= 0xffff; \ + __v; }) +#define SMC_inb(p) ({ \ + unsigned int ___v = SMC_inw((p) & ~1); \ + if (p & 1) ___v >>= 8; \ + else ___v &= 0xff; \ + ___v; }) +#else +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inb(p) ({ \ + unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \ + unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ + if (__p & 1) __v >>= 8; \ + else __v &= 0xff; \ + __v; }) +#endif + +#ifdef CONFIG_XSENGINE +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#elif defined (CONFIG_XAENIAX) +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outw(d,p) ({ \ + dword __dwo = SMC_inl((p) & ~3); \ + dword __dwn = (word)(d); \ + __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ + __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ + SMC_outl(__dwo, (p) & ~3); \ +}) +#else +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#endif + +#define SMC_outb(d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(__w,(r)&~1); \ + }) + +#define SMC_outsl(r,b,l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl( *(__b2 + __i), r); \ + } \ + }) + +#define SMC_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw( *(__b2 + __i), r); \ + } \ + }) + +#define SMC_insl(r,b,l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl(r); \ + SMC_inl(0); \ + }; \ + }) + +#define SMC_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(r); \ + SMC_inw(0); \ + }; \ + }) + +#define SMC_insb(r,b,l) ({ int __i ; \ + byte *__b2; \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inb(r); \ + SMC_inb(0); \ + }; \ + }) + +#else /* if not CONFIG_PXA250 */ + +#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ +/* + * We have only 16 Bit PCMCIA access on Socket 0 + */ + +#ifdef CONFIG_ADNPESC1 +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) +#else +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#endif +#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) + +#ifdef CONFIG_ADNPESC1 +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) +#else +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#endif +#define SMC_outb(d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(__w,(r)&~1); \ + }) +#if 0 +#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) +#else +#define SMC_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw( *(__b2 + __i), r); \ + } \ + }) +#endif + +#if 0 +#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) +#else +#define SMC_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(r); \ + SMC_inw(0); \ + }; \ + }) +#endif + +#endif /* CONFIG_SMC_USE_IOFUNCS */ + +#if defined(CONFIG_SMC_USE_32_BIT) + +#ifdef CONFIG_XSENGINE +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) +#else +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#endif + +#define SMC_insl(r,b,l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl(r); \ + SMC_inl(0); \ + }; \ + }) + +#ifdef CONFIG_XSENGINE +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#else +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) +#endif +#define SMC_outsl(r,b,l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl( *(__b2 + __i), r); \ + } \ + }) + +#endif /* CONFIG_SMC_USE_32_BIT */ + +#endif + +/*--------------------------------------------------------------- + . + . A description of the SMSC registers is probably in order here, + . although for details, the SMC datasheet is invaluable. + . + . Basically, the chip has 4 banks of registers ( 0 to 3 ), which + . are accessed by writing a number into the BANK_SELECT register + . ( I also use a SMC_SELECT_BANK macro for this ). + . + . The banks are configured so that for most purposes, bank 2 is all + . that is needed for simple run time tasks. + -----------------------------------------------------------------------*/ + +/* + . Bank Select Register: + . + . yyyy yyyy 0000 00xx + . xx = bank number + . yyyy yyyy = 0x33, for identification purposes. +*/ +#define BANK_SELECT 14 + +/* Transmit Control Register */ +/* BANK 0 */ +#define TCR_REG 0x0000 /* transmit control register */ +#define TCR_ENABLE 0x0001 /* When 1 we can transmit */ +#define TCR_LOOP 0x0002 /* Controls output pin LBK */ +#define TCR_FORCOL 0x0004 /* When 1 will force a collision */ +#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ +#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ +#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ +#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ +#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ +#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ +#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ + +#define TCR_CLEAR 0 /* do NOTHING */ +/* the default settings for the TCR register : */ +/* QUESTION: do I want to enable padding of short packets ? */ +#define TCR_DEFAULT TCR_ENABLE + + +/* EPH Status Register */ +/* BANK 0 */ +#define EPH_STATUS_REG 0x0002 +#define ES_TX_SUC 0x0001 /* Last TX was successful */ +#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ +#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ +#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ +#define ES_16COL 0x0010 /* 16 Collisions Reached */ +#define ES_SQET 0x0020 /* Signal Quality Error Test */ +#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ +#define ES_TXDEFR 0x0080 /* Transmit Deferred */ +#define ES_LATCOL 0x0200 /* Late collision detected on last tx */ +#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ +#define ES_EXC_DEF 0x0800 /* Excessive Deferral */ +#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ +#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ +#define ES_TXUNRN 0x8000 /* Tx Underrun */ + + +/* Receive Control Register */ +/* BANK 0 */ +#define RCR_REG 0x0004 +#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ +#define RCR_PRMS 0x0002 /* Enable promiscuous mode */ +#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ +#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ +#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ +#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ +#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ +#define RCR_SOFTRST 0x8000 /* resets the chip */ + +/* the normal settings for the RCR register : */ +#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) +#define RCR_CLEAR 0x0 /* set it to a base state */ + +/* Counter Register */ +/* BANK 0 */ +#define COUNTER_REG 0x0006 + +/* Memory Information Register */ +/* BANK 0 */ +#define MIR_REG 0x0008 + +/* Receive/Phy Control Register */ +/* BANK 0 */ +#define RPC_REG 0x000A +#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ +#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ +#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ +#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ +#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ +#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ +#define RPC_LED_RES (0x01) /* LED = Reserved */ +#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ +#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ +#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ +#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ +#define RPC_LED_TX (0x06) /* LED = TX packet occurred */ +#define RPC_LED_RX (0x07) /* LED = RX packet occurred */ +#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) +/* buggy schematic: LEDa -> yellow, LEDb --> green */ +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ + | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) +#elif defined(CONFIG_ADNPESC1) +/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ + | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) +#else +/* SMSC reference design: LEDa --> green, LEDb --> yellow */ +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ + | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) +#endif + +/* Bank 0 0x000C is reserved */ + +/* Bank Select Register */ +/* All Banks */ +#define BSR_REG 0x000E + + +/* Configuration Reg */ +/* BANK 1 */ +#define CONFIG_REG 0x0000 +#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ +#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ +#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ +#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ + +/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ +#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) + + +/* Base Address Register */ +/* BANK 1 */ +#define BASE_REG 0x0002 + + +/* Individual Address Registers */ +/* BANK 1 */ +#define ADDR0_REG 0x0004 +#define ADDR1_REG 0x0006 +#define ADDR2_REG 0x0008 + + +/* General Purpose Register */ +/* BANK 1 */ +#define GP_REG 0x000A + + +/* Control Register */ +/* BANK 1 */ +#define CTL_REG 0x000C +#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ +#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ +#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ +#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ +#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ +#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ +#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ +#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ +#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ + +/* MMU Command Register */ +/* BANK 2 */ +#define MMU_CMD_REG 0x0000 +#define MC_BUSY 1 /* When 1 the last release has not completed */ +#define MC_NOP (0<<5) /* No Op */ +#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ +#define MC_RESET (2<<5) /* Reset MMU to initial state */ +#define MC_REMOVE (3<<5) /* Remove the current rx packet */ +#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ +#define MC_FREEPKT (5<<5) /* Release packet in PNR register */ +#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ +#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ + + +/* Packet Number Register */ +/* BANK 2 */ +#define PN_REG 0x0002 + + +/* Allocation Result Register */ +/* BANK 2 */ +#define AR_REG 0x0003 +#define AR_FAILED 0x80 /* Alocation Failed */ + + +/* RX FIFO Ports Register */ +/* BANK 2 */ +#define RXFIFO_REG 0x0004 /* Must be read as a word */ +#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ + + +/* TX FIFO Ports Register */ +/* BANK 2 */ +#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ +#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ + + +/* Pointer Register */ +/* BANK 2 */ +#define PTR_REG 0x0006 +#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ +#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ +#define PTR_READ 0x2000 /* When 1 the operation is a read */ +#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ + + +/* Data Register */ +/* BANK 2 */ +#define SMC91111_DATA_REG 0x0008 + + +/* Interrupt Status/Acknowledge Register */ +/* BANK 2 */ +#define SMC91111_INT_REG 0x000C + + +/* Interrupt Mask Register */ +/* BANK 2 */ +#define IM_REG 0x000D +#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ +#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ +#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ +#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ +#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ +#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ +#define IM_TX_INT 0x02 /* Transmit Interrrupt */ +#define IM_RCV_INT 0x01 /* Receive Interrupt */ + + +/* Multicast Table Registers */ +/* BANK 3 */ +#define MCAST_REG1 0x0000 +#define MCAST_REG2 0x0002 +#define MCAST_REG3 0x0004 +#define MCAST_REG4 0x0006 + + +/* Management Interface Register (MII) */ +/* BANK 3 */ +#define MII_REG 0x0008 +#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ +#define MII_MDOE 0x0008 /* MII Output Enable */ +#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ +#define MII_MDI 0x0002 /* MII Input, pin MDI */ +#define MII_MDO 0x0001 /* MII Output, pin MDO */ + + +/* Revision Register */ +/* BANK 3 */ +#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ + + +/* Early RCV Register */ +/* BANK 3 */ +/* this is NOT on SMC9192 */ +#define ERCV_REG 0x000C +#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ +#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ + +/* External Register */ +/* BANK 7 */ +#define EXT_REG 0x0000 + + +#define CHIP_9192 3 +#define CHIP_9194 4 +#define CHIP_9195 5 +#define CHIP_9196 6 +#define CHIP_91100 7 +#define CHIP_91100FD 8 +#define CHIP_91111FD 9 + +#if 0 +static const char * chip_ids[ 15 ] = { + NULL, NULL, NULL, + /* 3 */ "SMC91C90/91C92", + /* 4 */ "SMC91C94", + /* 5 */ "SMC91C95", + /* 6 */ "SMC91C96", + /* 7 */ "SMC91C100", + /* 8 */ "SMC91C100FD", + /* 9 */ "SMC91C111", + NULL, NULL, + NULL, NULL, NULL}; +#endif + +/* + . Transmit status bits +*/ +#define TS_SUCCESS 0x0001 +#define TS_LOSTCAR 0x0400 +#define TS_LATCOL 0x0200 +#define TS_16COL 0x0010 + +/* + . Receive status bits +*/ +#define RS_ALGNERR 0x8000 +#define RS_BRODCAST 0x4000 +#define RS_BADCRC 0x2000 +#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ +#define RS_TOOLONG 0x0800 +#define RS_TOOSHORT 0x0400 +#define RS_MULTICAST 0x0001 +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) + + +/* PHY Types */ +enum { + PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ + PHY_LAN83C180 +}; + + +/* PHY Register Addresses (LAN91C111 Internal PHY) */ + +/* PHY Control Register */ +#define PHY_CNTL_REG 0x00 +#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ +#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ +#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ +#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ +#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ +#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ +#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ +#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ +#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ + +/* PHY Status Register */ +#define PHY_STAT_REG 0x01 +#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ +#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ +#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ +#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ +#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ +#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ +#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ +#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ +#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ +#define PHY_STAT_LINK 0x0004 /* 1=valid link */ +#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ +#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ + +/* PHY Identifier Registers */ +#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ +#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ + +/* PHY Auto-Negotiation Advertisement Register */ +#define PHY_AD_REG 0x04 +#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ +#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ +#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ +#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ +#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ +#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ +#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ +#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ +#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ + +/* PHY Auto-negotiation Remote End Capability Register */ +#define PHY_RMT_REG 0x05 +/* Uses same bit definitions as PHY_AD_REG */ + +/* PHY Configuration Register 1 */ +#define PHY_CFG1_REG 0x10 +#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ +#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ +#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ +#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ +#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ +#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ +#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ +#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ +#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ + + +/* PHY Configuration Register 2 */ +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ +#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ +#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ +#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ + +/* PHY Status Output (and Interrupt status) Register */ +#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ +#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ +#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ +#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ +#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ +#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ +#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ +#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ +#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ +#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ +#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ + +/* PHY Interrupt/Status Mask Register */ +#define PHY_MASK_REG 0x13 /* Interrupt Mask */ +/* Uses the same bit definitions as PHY_INT_REG */ + + +/*------------------------------------------------------------------------- + . I define some macros to make it easier to do somewhat common + . or slightly complicated, repeated tasks. + --------------------------------------------------------------------------*/ + +/* select a register bank, 0 to 3 */ + +#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); } + +/* this enables an interrupt in the interrupt mask register */ +#define SMC_ENABLE_INT(x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(2);\ + mask = SMC_inb( IM_REG );\ + mask |= (x);\ + SMC_outb( mask, IM_REG ); \ +} + +/* this disables an interrupt from the interrupt mask register */ + +#define SMC_DISABLE_INT(x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(2);\ + mask = SMC_inb( IM_REG );\ + mask &= ~(x);\ + SMC_outb( mask, IM_REG ); \ +} + +/*---------------------------------------------------------------------- + . Define the interrupts that I want to receive from the card + . + . I want: + . IM_EPH_INT, for nasty errors + . IM_RCV_INT, for happy received packets + . IM_RX_OVRN_INT, because I have to kick the receiver + . IM_MDINT, for PHY Register 18 Status Changes + --------------------------------------------------------------------------*/ +#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ + IM_MDINT) + +#endif /* _SMC_91111_H_ */ diff --git a/drivers/smiLynxEM.c b/drivers/smiLynxEM.c new file mode 100644 index 0000000..20f9beb --- /dev/null +++ b/drivers/smiLynxEM.c @@ -0,0 +1,858 @@ +/* + * (C) Copyright 1997-2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * smiLynxEM.c + * + * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator + * + * modification history + * -------------------- + * 04-18-2002 Rewritten for U-Boot . + * + * 18-03-2004 - Unify videomodes handling with the ct69000 + * - The video output can be set via the variable "videoout" + * in the environment. + * videoout=1 output on LCD + * videoout=2 output on CRT (default value) + * + */ + +#include + +#if defined(CONFIG_VIDEO_SMI_LYNXEM) + +#include +#include +#include "videomodes.h" +/* + * Export Graphic Device + */ +GraphicDevice smi; + +/* + * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external + */ +#define VIDEO_MEM_SIZE 0x400000 + + +/* + * ISA mapped regs + */ +#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */ +#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */ +#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */ +#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */ +#define SMI_ISR1 (pGD->isaBase + 0x03ca) +#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */ +#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */ +#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */ +#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */ +#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */ +#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */ +#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/ +#define SMI_INDX_ATTR (pGD->isaBase + 0x03c0) /* attributes index reg */ + +/* + * Video processor control + */ +typedef struct { + unsigned int control; + unsigned int colorKey; + unsigned int colorKeyMask; + unsigned int start; + unsigned short offset; + unsigned short width; + unsigned int fifoPrio; + unsigned int fifoERL; + unsigned int YUVtoRGB; +} SmiVideoProc; + +/* + * Video window control + */ +typedef struct { + unsigned short top; + unsigned short left; + unsigned short bottom; + unsigned short right; + unsigned int srcStart; + unsigned short width; + unsigned short offset; + unsigned char hStretch; + unsigned char vStretch; +} SmiVideoWin; + +/* + * Capture port control + */ +typedef struct { + unsigned int control; + unsigned short topClip; + unsigned short leftClip; + unsigned short srcHeight; + unsigned short srcWidth; + unsigned int srcBufStart1; + unsigned int srcBufStart2; + unsigned short srcOffset; + unsigned short fifoControl; +} SmiCapturePort; + + +/* + * Register values for common video modes + */ +static char SMI_SCR[] = { + /* all modes */ + 0x10, 0xff, 0x11, 0xff, 0x12, 0xff, 0x13, 0xff, 0x15, 0x90, + 0x17, 0x20, 0x18, 0xb1, 0x19, 0x00, +}; +static char SMI_EXT_CRT[] = { + 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00, + 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00, +}; +static char SMI_ATTR [] = { + 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0b, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0e, 0x0e, 0x0f, 0x0f, 0x10, 0x41, 0x11, 0x00, + 0x12, 0x0f, 0x13, 0x00, 0x14, 0x00, +}; +static char SMI_GCR[18] = { + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x40, + 0x06, 0x05, 0x07, 0x0f, 0x08, 0xff, +}; +static char SMI_SEQR[] = { + 0x00, 0x00, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e, 0x00, 0x03, +}; +static char SMI_PCR [] = { + 0x20, 0x04, 0x21, 0x30, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00, +}; +static char SMI_MCR[] = { + 0x60, 0x01, 0x61, 0x00, +#ifdef CONFIG_HMI1001 + 0x62, 0x74, /* Memory type is not configured by pins on HMI1001 */ +#endif +}; + +static char SMI_HCR[] = { + 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00, + 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00, +}; + + +/******************************************************************************* + * + * Write SMI ISA register + */ +static void smiWrite (unsigned short index, char reg, char val) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + out8 ((pGD->isaBase + index), reg); + out8 ((pGD->isaBase + index + 1), val); +} + +/******************************************************************************* + * + * Write a table of SMI ISA register + */ +static void smiLoadRegs ( + unsigned int iReg, + unsigned int dReg, + char *regTab, + unsigned int tabSize + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register int i; + + for (i=0; icprBase + 0x0004), ((pCP->topClip<<16) | pCP->leftClip)); + out32r ((pGD->cprBase + 0x0008), ((pCP->srcHeight<<16) | pCP->srcWidth)); + out32r ((pGD->cprBase + 0x000c), pCP->srcBufStart1/8); + out32r ((pGD->cprBase + 0x0010), pCP->srcBufStart2/8); + out32r ((pGD->cprBase + 0x0014), pCP->srcOffset/8); + out32r ((pGD->cprBase + 0x0018), pCP->fifoControl); + out32r ((pGD->cprBase + 0x0000), pCP->control); +} + + +/******************************************************************************* + * + * Init video processor registers + */ +static void smiInitVideoProcessor (void) +{ + SmiVideoProc smiVP = { 0x100000, 0, 0, 0, 0, 1600, 0x1200543, 4, 0xededed }; + SmiVideoWin smiVW = { 0, 0, 599, 799, 0, 1600, 0, 0, 0 }; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register SmiVideoProc *pVP = (SmiVideoProc *)&smiVP; + register SmiVideoWin *pVWin = (SmiVideoWin *)&smiVW; + + pVP->width = pGD->plnSizeX * pGD->gdfBytesPP; + pVP->control |= pGD->gdfIndex << 16; + pVWin->bottom = pGD->winSizeY - 1; + pVWin->right = pGD->winSizeX - 1; + pVWin->width = pVP->width; + + /* color key */ + out32r ((pGD->vprBase + 0x0004), pVP->colorKey); + + /* color key mask */ + out32r ((pGD->vprBase + 0x0008), pVP->colorKeyMask); + + /* data src start adrs */ + out32r ((pGD->vprBase + 0x000c), pVP->start / 8); + + /* data width and offset */ + out32r ((pGD->vprBase + 0x0010), + ((pVP->offset / 8 * pGD->gdfBytesPP) << 16) | + (pGD->plnSizeX / 8 * pGD->gdfBytesPP)); + + /* video window 1 */ + out32r ((pGD->vprBase + 0x0014), + ((pVWin->top << 16) | pVWin->left)); + + out32r ((pGD->vprBase + 0x0018), + ((pVWin->bottom << 16) | pVWin->right)); + + out32r ((pGD->vprBase + 0x001c), pVWin->srcStart / 8); + + out32r ((pGD->vprBase + 0x0020), + (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); + + out32r ((pGD->vprBase + 0x0024), + (((pVWin->hStretch) << 8) | pVWin->vStretch)); + + /* video window 2 */ + out32r ((pGD->vprBase + 0x0028), + ((pVWin->top << 16) | pVWin->left)); + + out32r ((pGD->vprBase + 0x002c), + ((pVWin->bottom << 16) | pVWin->right)); + + out32r ((pGD->vprBase + 0x0030), + pVWin->srcStart / 8); + + out32r ((pGD->vprBase + 0x0034), + (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); + + out32r ((pGD->vprBase + 0x0038), + (((pVWin->hStretch) << 8) | pVWin->vStretch)); + + /* fifo prio control */ + out32r ((pGD->vprBase + 0x0054), pVP->fifoPrio); + + /* fifo empty request levell */ + out32r ((pGD->vprBase + 0x0058), pVP->fifoERL); + + /* conversion constant */ + out32r ((pGD->vprBase + 0x005c), pVP->YUVtoRGB); + + /* vpr control word */ + out32r ((pGD->vprBase + 0x0000), pVP->control); +} + +/****************************************************************************** + * + * Init drawing engine registers + */ +static void smiInitDrawingEngine (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&smi; + unsigned int val; + + /* don't start now */ + out32r ((pGD->dprBase + 0x000c), 0x000f0000); + + /* set rop2 to copypen */ + val = 0xffff3ff0 & in32r ((pGD->dprBase + 0x000c)); + out32r ((pGD->dprBase + 0x000c), (val | 0x8000 | 0x0c)); + + /* set clip rect */ + out32r ((pGD->dprBase + 0x002c), 0); + out32r ((pGD->dprBase + 0x0030), + ((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP )); + + /* src row pitch */ + val = 0xffff0000 & (in32r ((pGD->dprBase + 0x0010))); + out32r ((pGD->dprBase + 0x0010), + (val | pGD->plnSizeX * pGD->gdfBytesPP)); + + /* dst row pitch */ + val = 0x0000ffff & (in32r ((pGD->dprBase + 0x0010))); + out32r ((pGD->dprBase + 0x0010), + (((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val)); + + /* window width src/dst */ + out32r ((pGD->dprBase + 0x003c), + (((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) | + (pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff))); + out16r ((pGD->dprBase + 0x001e), 0x0000); + + /* src base adrs */ + out32r ((pGD->dprBase + 0x0040), + (((pGD->frameAdrs/8) & 0x000fffff))); + + /* dst base adrs */ + out32r ((pGD->dprBase + 0x0044), + (((pGD->frameAdrs/8) & 0x000fffff))); + + /* foreground color */ + out32r ((pGD->dprBase + 0x0014), pGD->fg); + + /* background color */ + out32r ((pGD->dprBase + 0x0018), pGD->bg); + + /* xcolor */ + out32r ((pGD->dprBase + 0x0020), 0x00ffffff); + + /* xcolor mask */ + out32r ((pGD->dprBase + 0x0024), 0x00ffffff); + + /* bit mask */ + out32r ((pGD->dprBase + 0x0028), 0x00ffffff); + + /* load mono pattern */ + out32r ((pGD->dprBase + 0x0034), 0); + out32r ((pGD->dprBase + 0x0038), 0); +} + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_710 }, + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_712 }, + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_810 }, + { } +}; + +/*****************************************************************************/ +static void smiLoadMsr (struct ctfb_res_modes *mode) +{ + unsigned char h_synch_high, v_synch_high; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */ + v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */ + out8 (SMI_MISC_REG, (h_synch_high | v_synch_high | 0x29)); + /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01 + * Selects the upper 64KB page.Bit5=1 + * CLK2 (left reserved in standard VGA) Bit3|2=1|0 + * Disables CPU access to frame buffer. Bit1=0 + * Sets the I/O address decode for ST01, FCR, and all CR registers + * to the 3Dx I/O address range (CGA emulation). Bit0=1 + */ +} +/*****************************************************************************/ +static void smiLoadCrt (struct ctfb_res_modes *var, int bits_per_pixel) +{ + unsigned char cr[0x7a]; + int i; + unsigned int hd, hs, he, ht, hbs, hbe; /* Horizontal. */ + unsigned int vd, vs, ve, vt, vbs, vbe; /* vertical */ + unsigned int bpp, wd, dblscan, interlaced; + + const int LineCompare = 0x3ff; + unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + /* Horizontal */ + hd = (var->xres) / 8; /* HDisp. */ + hs = (var->xres + var->right_margin) / 8; /* HsStrt */ + he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */ + ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */ + /* Blank */ + hbs = hd; + hbe = 0; /* Blank end at 0 */ + + /* Vertical */ + vd = var->yres; /* VDisplay */ + vs = var->yres + var->lower_margin; /* VSyncStart */ + ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */ + vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */ + vbs = vd; + vbe = 0; + + bpp = bits_per_pixel; + dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0; + interlaced = var->vmode & FB_VMODE_INTERLACED; + + + if (bpp == 15) + bpp = 16; + wd = var->xres * bpp / 64; /* double words per line */ + if (interlaced) { /* we divide all vertical timings, exept vd */ + vs >>= 1; + vbs >>= 1; + ve >>= 1; + vt >>= 1; + } + + memset (cr, 0, sizeof (cr)); + cr[0x00] = ht - 5; + cr[0x01] = hd - 1; + cr[0x02] = hbs - 1; + cr[0x03] = (hbe & 0x1F); + cr[0x04] = hs; + cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); + + cr[0x06] = (vt - 2) & 0xFF; + cr[0x07] = (((vt - 2) & 0x100) >> 8) + | (((vd - 1) & 0x100) >> 7) + | ((vs & 0x100) >> 6) + | (((vbs - 1) & 0x100) >> 5) + | ((LineCompare & 0x100) >> 4) + | (((vt - 2) & 0x200) >> 4) + | (((vd - 1) & 0x200) >> 3) + | ((vs & 0x200) >> 2); + + cr[0x30] = ((vt - 2) & 0x400) >> 7 + | (((vd - 1) & 0x400) >> 8) + | (((vbs - 1) & 0x400) >> 9) + | ((vs & 0x400) >> 10) + | (interlaced) ? 0x80 : 0; + + + cr[0x08] = 0x00; + cr[0x09] = (dblscan << 7) + | ((LineCompare & 0x200) >> 3) + | (((vbs - 1) & 0x200) >> 4) + | (TextScanLines - 1); + + cr[0x10] = vs & 0xff; /* VSyncPulseStart */ + cr[0x11] = (ve & 0x0f); + cr[0x12] = (vd - 1) & 0xff; /* LineCount */ + cr[0x13] = wd & 0xff; + cr[0x14] = 0x40; + cr[0x15] = (vbs - 1) & 0xff; + cr[0x16] = vbe & 0xff; + cr[0x17] = 0xe3; /* but it does not work */ + cr[0x18] = 0xff & LineCompare; + cr[0x22] = 0x00; /* todo? */ + + + /* now set the registers */ + for (i = 0; i <= 0x18; i++) { /*CR00 .. CR18 */ + smiWrite (SMI_INDX_D4, i, cr[i]); + } + i = 0x22; /*CR22 */ + smiWrite (SMI_INDX_D4, i, cr[i]); + i = 0x30; /*CR30 */ + smiWrite (SMI_INDX_D4, i, cr[i]); +} + +/*****************************************************************************/ +#define REF_FREQ 14318180 +#define PMIN 1 +#define PMAX 255 +#define QMIN 1 +#define QMAX 63 + +static unsigned int FindPQ (unsigned int freq, unsigned int *pp, unsigned int *pq) +{ + unsigned int n = QMIN, m = 0; + long long int L = 0, P = freq, Q = REF_FREQ, H = P >> 1; + long long int D = 0x7ffffffffffffffLL; + + for (n = QMIN; n <= QMAX; n++) { + m = PMIN; /* p/q ~ freq/ref -> p*ref-freq*q ~ 0 */ + L = P * n - m * Q; + while (L > 0 && m < PMAX) { + L -= REF_FREQ; /* difference is greater as 0 subtract fref */ + m++; /* and increment m */ + } + /* difference is less or equal than 0 or m > maximum */ + if (m > PMAX) + break; /* no solution: if we increase n we get the same situation */ + /* L is <= 0 now */ + if (-L > H && m > PMIN) { /* if difference > the half fref */ + L += REF_FREQ; /* we take the situation before */ + m--; /* because its closer to 0 */ + } + L = (L < 0) ? -L : +L; /* absolute value */ + if (D < L) /* if last difference was better take next n */ + continue; + D = L; + *pp = m; + *pq = n; /* keep improved data */ + if (D == 0) + break; /* best result we can get */ + } + return (unsigned int) (0xffffffff & D); +} + +/*****************************************************************************/ +static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id) +{ + unsigned int p = 0; + unsigned int q = 0; + long long freq; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + smiWrite (SMI_INDX_C4, 0x65, 0); + smiWrite (SMI_INDX_C4, 0x66, 0); + smiWrite (SMI_INDX_C4, 0x68, 0x50); + if (device_id == PCI_DEVICE_ID_SMI_810) { + smiWrite (SMI_INDX_C4, 0x69, 0x3); + } else { + smiWrite (SMI_INDX_C4, 0x69, 0x0); + } + + /* Memory clock */ + switch (device_id) { + case PCI_DEVICE_ID_SMI_710 : + smiWrite (SMI_INDX_C4, 0x6a, 0x75); + break; + case PCI_DEVICE_ID_SMI_712 : + smiWrite (SMI_INDX_C4, 0x6a, 0x80); + break; + default : + smiWrite (SMI_INDX_C4, 0x6a, 0x53); + break; + } + smiWrite (SMI_INDX_C4, 0x6b, 0x15); + + /* VCLK */ + freq = 1000000000000LL / var -> pixclock; + + FindPQ ((unsigned int)freq, &p, &q); + + smiWrite (SMI_INDX_C4, 0x6c, p); + smiWrite (SMI_INDX_C4, 0x6d, q); + +} + +/******************************************************************************* + * + * Init video chip with common Linux graphic modes (lilo) + */ +void *video_hw_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&smi; + unsigned short device_id; + pci_dev_t devbusfn; + int videomode; + unsigned long t1, hsynch, vsynch; + unsigned int pci_mem_base, *vm; + char *penv; + int tmp, i, bits_per_pixel; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + unsigned char videoout; + + /* Search for video chip */ + printf("Video: "); + + if ((devbusfn = pci_find_devices(supported, 0)) < 0) + { + printf ("Controller not found !\n"); + return (NULL); + } + + /* PCI setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base); + pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base); + + tmp = 0; + + videomode = CFG_DEFAULT_VIDEO_MODE; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE); + i = 0; + } + res_mode = + (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i]. + resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + } else { + + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= + (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); + printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; + switch (bits_per_pixel) { + case 8: + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + case 15: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_15BIT_555RGB; + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + break; + case 24: + pGD->gdfBytesPP = 3; + pGD->gdfIndex = GDF_24BIT_888RGB; + break; + } + + pGD->isaBase = CFG_ISA_IO; + pGD->pciBase = pci_mem_base; + pGD->dprBase = (pci_mem_base + 0x400000 + 0x8000); + pGD->vprBase = (pci_mem_base + 0x400000 + 0xc000); + pGD->cprBase = (pci_mem_base + 0x400000 + 0xe000); + pGD->frameAdrs = pci_mem_base; + pGD->memSize = VIDEO_MEM_SIZE; + + /* Set up hardware : select color mode, + set Register base to isa 3dx for 3?x regs*/ + out8 (SMI_MISC_REG, 0x01); + + /* Turn off display */ + smiWrite (SMI_INDX_C4, 0x01, 0x20); + + /* Unlock ext. crt regs */ + out8 (SMI_LOCK_REG, 0x40); + + /* Unlock crt regs 0-7 */ + smiWrite (SMI_INDX_D4, 0x11, 0x0e); + + /* Sytem Control Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SCR, sizeof(SMI_SCR)); + + /* extented CRT Register */ + smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, SMI_EXT_CRT, sizeof(SMI_EXT_CRT)); + + /* Attributes controller registers */ + smiLoadRegs (SMI_INDX_ATTR, SMI_INDX_ATTR, SMI_ATTR, sizeof(SMI_ATTR)); + + /* Graphics Controller Register */ + smiLoadRegs (SMI_INDX_CE, SMI_DATA_CF, SMI_GCR, sizeof(SMI_GCR)); + + /* Sequencer Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SEQR, sizeof(SMI_SEQR)); + + /* Power Control Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_PCR, sizeof(SMI_PCR)); + + /* Memory Control Register */ + /* Register MSR62 is a power on configurable register. We don't */ + /* modify it */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_MCR, sizeof(SMI_MCR)); + + /* Set misc output register */ + smiLoadMsr (res_mode); + + /* Set CRT and Clock control registers */ + smiLoadCrt (res_mode, bits_per_pixel); + + smiLoadCcr (res_mode, device_id); + + /* Hardware Cusor Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_HCR, sizeof(SMI_HCR)); + + /* Enable Display */ + videoout = 2; /* Default output is CRT */ + if ((penv = getenv ("videoout")) != NULL) { + /* deceide if it is a string */ + videoout = (int) simple_strtoul (penv, NULL, 16); + } + smiWrite (SMI_INDX_C4, 0x31, videoout); + + /* Video processor default setup */ + smiInitVideoProcessor (); + + /* Capture port default setup */ + smiInitCapturePort (); + + /* Drawing engine default setup */ + smiInitDrawingEngine (); + + /* Turn on display */ + smiWrite (0x3c4, 0x01, 0x01); + + /* Clear video memory */ + i = pGD->memSize/4; + vm = (unsigned int *)pGD->pciBase; + while(i--) + *vm++ = 0; + return ((void*)&smi); +} + +/******************************************************************************* + * + * Drawing engine fill on screen region + */ +void video_hw_rectfill ( + unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register unsigned int control; + + dim_x *= bpp; + + out32r ((pGD->dprBase + 0x0014), color); + out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); + out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); + + control = 0x0000ffff & in32r ((pGD->dprBase + 0x000c)); + + control |= 0x80010000; + + out32r ((pGD->dprBase + 0x000c), control); + + /* Wait for drawing processor */ + do + { + out8 ((pGD->isaBase + 0x3c4), 0x16); + } while (in8 (pGD->isaBase + 0x3c5) & 0x08); +} + +/******************************************************************************* + * + * Drawing engine bitblt with screen region + */ +void video_hw_bitblt ( + unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register unsigned int control; + + dim_x *= bpp; + + if ((src_ydprBase + 0x0000), (((src_x+dim_x-1)<<16) | (src_y+dim_y-1))); + out32r ((pGD->dprBase + 0x0004), (((dst_x+dim_x-1)<<16) | (dst_y+dim_y-1))); + control = 0x88000000; + } else { + out32r ((pGD->dprBase + 0x0000), ((src_x<<16) | src_y)); + out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); + control = 0x80000000; + } + + out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); + control |= (0x0000ffff & in32r ((pGD->dprBase + 0x000c))); + out32r ((pGD->dprBase + 0x000c), control); + + /* Wait for drawing processor */ + do + { + out8 ((pGD->isaBase + 0x3c4), 0x16); + } while (in8 (pGD->isaBase + 0x3c5) & 0x08); +} + +/******************************************************************************* + * + * Set a RGB color in the LUT (8 bit index) + */ +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + out8 (SMI_LUT_MASK, 0xff); + + out8 (SMI_LUT_START, (char)index); + + out8 (SMI_LUT_RGB, r>>2); /* red */ + udelay (10); + out8 (SMI_LUT_RGB, g>>2); /* green */ + udelay (10); + out8 (SMI_LUT_RGB, b>>2); /* blue */ + udelay (10); +} + +#endif /* CONFIG_VIDEO_SMI_LYNXEM */ diff --git a/drivers/status_led.c b/drivers/status_led.c new file mode 100644 index 0000000..ddb6c22 --- /dev/null +++ b/drivers/status_led.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * The purpose of this code is to signal the operational status of a + * target which usually boots over the network; while running in + * U-Boot, a status LED is blinking. As soon as a valid BOOTP reply + * message has been received, the LED is turned off. The Linux + * kernel, once it is running, will start blinking the LED again, + * with another frequency. + */ + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_STATUS_LED + +typedef struct { + led_id_t mask; + int state; + int period; + int cnt; +} led_dev_t; + +led_dev_t led_dev[] = { + { STATUS_LED_BIT, + STATUS_LED_STATE, + STATUS_LED_PERIOD, + 0, + }, +#if defined(STATUS_LED_BIT1) + { STATUS_LED_BIT1, + STATUS_LED_STATE1, + STATUS_LED_PERIOD1, + 0, + }, +#endif +#if defined(STATUS_LED_BIT2) + { STATUS_LED_BIT2, + STATUS_LED_STATE2, + STATUS_LED_PERIOD2, + 0, + }, +#endif +#if defined(STATUS_LED_BIT3) + { STATUS_LED_BIT3, + STATUS_LED_STATE3, + STATUS_LED_PERIOD3, + 0, + }, +#endif +}; + +#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t)) + +static int status_led_init_done = 0; + +static void status_led_init (void) +{ + led_dev_t *ld; + int i; + + for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) + __led_init (ld->mask, ld->state); + status_led_init_done = 1; +} + +void status_led_tick (ulong timestamp) +{ + led_dev_t *ld; + int i; + + if (!status_led_init_done) + status_led_init (); + + for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) { + + if (ld->state != STATUS_LED_BLINKING) + continue; + + if (++ld->cnt >= ld->period) { + __led_toggle (ld->mask); + ld->cnt -= ld->period; + } + + } +} + +void status_led_set (int led, int state) +{ + led_dev_t *ld; + + if (led < 0 || led >= MAX_LED_DEV) + return; + + if (!status_led_init_done) + status_led_init (); + + ld = &led_dev[led]; + + ld->state = state; + if (state == STATUS_LED_BLINKING) { + ld->cnt = 0; /* always start with full period */ + state = STATUS_LED_ON; /* always start with LED _ON_ */ + } + __led_set (ld->mask, state); +} + +#endif /* CONFIG_STATUS_LED */ diff --git a/drivers/sym53c8xx.c b/drivers/sym53c8xx.c new file mode 100644 index 0000000..ae10f80 --- /dev/null +++ b/drivers/sym53c8xx.c @@ -0,0 +1,793 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * partly derived from + * linux/drivers/scsi/sym53c8xx.c + * + */ + +/* + * SCSI support based on the chip sym53C810. + * + * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH + * The local version of this driver for the BAB750 board does not + * use interrupts but polls the chip instead (see the call of + * 'handle_scsi_int()' in 'scsi_issue()'. + */ + +#include + +#ifdef CONFIG_SCSI_SYM53C8XX + +#include +#include +#include +#include +#include + +#undef SYM53C8XX_DEBUG + +#ifdef SYM53C8XX_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) + +#undef SCSI_SINGLE_STEP +/* + * Single Step is only used for debug purposes + */ +#ifdef SCSI_SINGLE_STEP +static unsigned long start_script_select; +static unsigned long start_script_msgout; +static unsigned long start_script_msgin; +static unsigned long start_script_msg_ext; +static unsigned long start_script_cmd; +static unsigned long start_script_data_in; +static unsigned long start_script_data_out; +static unsigned long start_script_status; +static unsigned long start_script_complete; +static unsigned long start_script_error; +static unsigned long start_script_reselection; +static unsigned int len_script_select; +static unsigned int len_script_msgout; +static unsigned int len_script_msgin; +static unsigned int len_script_msg_ext; +static unsigned int len_script_cmd; +static unsigned int len_script_data_in; +static unsigned int len_script_data_out; +static unsigned int len_script_status; +static unsigned int len_script_complete; +static unsigned int len_script_error; +static unsigned int len_script_reselection; +#endif + + +static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */ +static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */ +static unsigned long script_select[8]; /* script for selection */ +static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */ +static unsigned long script_msgin[14]; /* script for message in phase */ +static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */ +static unsigned long script_cmd[18]; /* script for command phase */ +static unsigned long script_data_in[8]; /* script for data in phase */ +static unsigned long script_data_out[8]; /* script for data out phase */ +static unsigned long script_status[6]; /* script for status phase */ +static unsigned long script_complete[10]; /* script for complete */ +static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */ +static unsigned long script_error[2]; /* script for error handling */ + +static unsigned long int_stat[3]; /* interrupt status */ +static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */ + +#define bus_to_phys(a) pci_mem_to_phys(busdevfunc, (unsigned long) (a)) +#define phys_to_bus(a) pci_phys_to_mem(busdevfunc, (unsigned long) (a)) + +#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */ + +#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */ +#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */ + +/********************************************************************************* + * forward declerations + */ + +void scsi_chip_init(void); +void handle_scsi_int(void); + + +/******************************************************************************** + * reports SCSI errors to the user + */ +void scsi_print_error(ccb *pccb) +{ + int i; + printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]); + printf(" CCB: "); + for(i=0;icmdlen;i++) + printf("%02X ",pccb->cmd[i]); + printf("(len=%d)\n",pccb->cmdlen); + printf(" Cntrl: "); + switch(pccb->contr_stat) { + case SIR_COMPLETE: printf("Complete (no Error)\n"); break; + case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break; + case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break; + case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break; + case SIR_DATA_IN_ERR: printf("Data in Error\n"); break; + case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break; + case SIR_SCRIPT_ERROR: printf("Script Error\n"); break; + case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break; + case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break; + case INT_ON_FY: printf("Interrupt on fly\n"); break; + case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break; + case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break; + case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break; + case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break; + default: printf("unknown status %lx\n",pccb->contr_stat); break; + } + printf(" Sense: SK %x (",pccb->sense_buf[2]&0x0f); + switch(pccb->sense_buf[2]&0xf) { + case SENSE_NO_SENSE: printf("No Sense)"); break; + case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break; + case SENSE_NOT_READY: printf("Not Ready)"); break; + case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break; + case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break; + case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break; + case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break; + case SENSE_DATA_PROTECT: printf("Data Protect)"); break; + case SENSE_BLANK_CHECK: printf("Blank check)"); break; + case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break; + case SENSE_COPY_ABORTED: printf("Copy aborted)"); break; + case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break; + case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break; + case SENSE_MISCOMPARE: printf("Misscompare\n"); break; + default: printf("Illegal Sensecode\n"); break; + } + printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]); + printf(" Status: "); + switch(pccb->status) { + case S_GOOD : printf("Good\n"); break; + case S_CHECK_COND: printf("Check condition\n"); break; + case S_COND_MET: printf("Condition Met\n"); break; + case S_BUSY: printf("Busy\n"); break; + case S_INT: printf("Intermediate\n"); break; + case S_INT_COND_MET: printf("Intermediate condition met\n"); break; + case S_CONFLICT: printf("Reservation conflict\n"); break; + case S_TERMINATED: printf("Command terminated\n"); break; + case S_QUEUE_FULL: printf("Task set full\n"); break; + default: printf("unknown: %02X\n",pccb->status); break; + } + +} + + +/****************************************************************************** + * sets-up the SCSI controller + * the base memory address is retrived via the pci_read_config_dword + */ +void scsi_low_level_init(int busdevfunc) +{ + unsigned int cmd; + unsigned int addr; + unsigned char vec; + + pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec); + pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr); + + addr = bus_to_phys(addr & ~0xf); + + /* + * Enable bus mastering in case this has not been done, yet. + */ + pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd); + + scsi_mem_addr = addr; + + scsi_chip_init(); + scsi_bus_reset(); +} + + +/************************************************************************************ + * Low level Part of SCSI Driver + */ + +/* + * big-endian -> little endian conversion for the script + */ +unsigned long swap_script(unsigned long val) +{ + unsigned long tmp; + tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000); + return tmp; +} + + +void scsi_write_byte(ulong offset,unsigned char val) +{ + out8(scsi_mem_addr+offset,val); +} + + +unsigned char scsi_read_byte(ulong offset) +{ + return(in8(scsi_mem_addr+offset)); +} + + +/******************************************************************************** + * interrupt handler + */ +void handle_scsi_int(void) +{ + unsigned char stat,stat1,stat2; + unsigned short sstat; + int i; +#ifdef SCSI_SINGLE_STEP + unsigned long tt; +#endif + stat=scsi_read_byte(ISTAT); + if((stat & DIP)==DIP) { /* DMA Interrupt pending */ + stat1=scsi_read_byte(DSTAT); +#ifdef SCSI_SINGLE_STEP + if((stat1 & SSI)==SSI) + { + tt=in32r(scsi_mem_addr+DSP); + if(((tt)>=start_script_select) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msgout) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msgin) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msg_ext) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_cmd) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_data_in) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_data_out) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_status) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_complete) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_error) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_reselection) && ((tt)>2); + goto end_single; + } + printf("sc: %lx\n",tt); +end_single: + stat2=scsi_read_byte(DCNTL); + stat2|=STD; + scsi_write_byte(DCNTL,stat2); + } +#endif + if((stat1 & SIR)==SIR) /* script interrupt */ + { + int_stat[0]=in32(scsi_mem_addr+DSPS); + } + if((stat1 & DFE)==0) { /* fifo not epmty */ + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ + stat2=scsi_read_byte(STEST3); + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ + } + } + if((stat & SIP)==SIP) { /* scsi interrupt */ + sstat = (unsigned short)scsi_read_byte(SIST+1); + sstat <<=8; + sstat |= (unsigned short)scsi_read_byte(SIST); + for(i=0;i<3;i++) { + if(int_stat[i]==0) + break; /* found an empty int status */ + } + int_stat[i]=SCSI_INT_STATE | sstat; + stat1=scsi_read_byte(DSTAT); + if((stat1 & DFE)==0) { /* fifo not epmty */ + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ + stat2=scsi_read_byte(STEST3); + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ + } + } + if((stat & INTF)==INTF) { /* interrupt on Fly */ + scsi_write_byte(ISTAT,stat); /* clear it */ + for(i=0;i<3;i++) { + if(int_stat[i]==0) + break; /* found an empty int status */ + } + int_stat[i]=INT_ON_FY; + } +} + +void scsi_bus_reset(void) +{ + unsigned char t; + int i; + int end = CFG_SCSI_SPIN_UP_TIME*1000; + + t=scsi_read_byte(SCNTL1); + scsi_write_byte(SCNTL1,(t | CRST)); + udelay(50); + scsi_write_byte(SCNTL1,t); + + puts("waiting for devices to spin up"); + for(i=0;i>8)); + scsi_write_byte(DIEN,script_int_mask); +} + +void scsi_write_dsp(unsigned long start) +{ + unsigned long val; +#ifdef SCSI_SINGLE_STEP + unsigned char t; +#endif + val = start; + out32r(scsi_mem_addr + DSP,start); +#ifdef SCSI_SINGLE_STEP + t=scsi_read_byte(DCNTL); + t|=STD; + scsi_write_byte(DCNTL,t); +#endif +} + +/* only used for debug purposes */ +void scsi_print_script(void) +{ + printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]); + printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]); + printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]); + printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]); + printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]); + printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]); + printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]); + printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]); + printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]); + printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]); +} + + +void scsi_set_script(ccb *pccb) +{ + int busdevfunc = pccb->priv; + int i; + i=0; + script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe)); + script_select[i++]=0; /* LED ON */ + script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */ + script_select[i++]=0; + /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */ + script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16); + script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */ + script_select[i++]=swap_script(SCR_JUMP); /* next section */ + /* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */ + script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */ + +#ifdef SCSI_SINGLE_STEP + start_script_select=(unsigned long)&script_select[0]; + len_script_select=i*4; +#endif + + i=0; + script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT))); + script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT; + script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT); + script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0])); + script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */ + script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */ + script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */ + script_msgout[i++]=SIR_MSG_OUT_NO_CMD; + +#ifdef SCSI_SINGLE_STEP + start_script_msgout=(unsigned long)&script_msgout[0]; + len_script_msgout=i*4; +#endif + i=0; + script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND); + script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_status[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */ + script_cmd[i++]=SIR_CMD_OUT_ILL_PH; +#ifdef SCSI_SINGLE_STEP + start_script_cmd=(unsigned long)&script_cmd[0]; + len_script_cmd=i*4; +#endif + i=0; + script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */ + script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ + script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); + script_data_out[i++]=swap_script(phys_to_bus(&script_status[0])); + script_data_out[i++]=swap_script(SCR_INT); + script_data_out[i++]=SIR_DATA_OUT_ERR; + +#ifdef SCSI_SINGLE_STEP + start_script_data_out=(unsigned long)&script_data_out[0]; + len_script_data_out=i*4; +#endif + i=0; + script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */ + script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ + script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); + script_data_in[i++]=swap_script(phys_to_bus(&script_status[0])); + script_data_in[i++]=swap_script(SCR_INT); + script_data_in[i++]=SIR_DATA_IN_ERR; +#ifdef SCSI_SINGLE_STEP + start_script_data_in=(unsigned long)&script_data_in[0]; + len_script_data_in=i*4; +#endif + i=0; + script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); + script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED))); + script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0])); + script_msgin[i++]=swap_script(SCR_INT); + script_msgin[i++]=SIR_MSG_RECEIVED; +#ifdef SCSI_SINGLE_STEP + start_script_msgin=(unsigned long)&script_msgin[0]; + len_script_msgin=i*4; +#endif + i=0; + script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */ + script_msg_ext[i++]=0; + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_INT); + script_msg_ext[i++]=SIR_MSG_OVER7; +#ifdef SCSI_SINGLE_STEP + start_script_msg_ext=(unsigned long)&script_msg_ext[0]; + len_script_msg_ext=i*4; +#endif + i=0; + script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS); + script_status[i++]=swap_script(phys_to_bus(&pccb->status)); + script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); + script_status[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_status[i++]=swap_script(SCR_INT); + script_status[i++]=SIR_STATUS_ILL_PH; +#ifdef SCSI_SINGLE_STEP + start_script_status=(unsigned long)&script_status[0]; + len_script_status=i*4; +#endif + i=0; + script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f)); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN)); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_WAIT_DISC); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01)); + script_complete[i++]=0; /* LED OFF */ + script_complete[i++]=swap_script(SCR_INT); + script_complete[i++]=SIR_COMPLETE; +#ifdef SCSI_SINGLE_STEP + start_script_complete=(unsigned long)&script_complete[0]; + len_script_complete=i*4; +#endif + i=0; + script_error[i++]=swap_script(SCR_INT); /* interrupt if error */ + script_error[i++]=SIR_SCRIPT_ERROR; +#ifdef SCSI_SINGLE_STEP + start_script_error=(unsigned long)&script_error[0]; + len_script_error=i*4; +#endif + i=0; + script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */ + script_reselection[i++]=0; + script_reselection[i++]=swap_script(SCR_WAIT_RESEL); + script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */ +#ifdef SCSI_SINGLE_STEP + start_script_reselection=(unsigned long)&script_reselection[0]; + len_script_reselection=i*4; +#endif +} + + +void scsi_issue(ccb *pccb) +{ + int busdevfunc = pccb->priv; + int i; + unsigned short sstat; + int retrycnt; /* retry counter */ + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + /* struct pccb must be set-up correctly */ + retrycnt=0; + PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]); + pccb->trans_bytes=0; /* no bytes transfered yet */ + scsi_set_script(pccb); /* fill in SCRIPT */ + scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */ + script_int_mask=0xff; /* enable all Ints */ + scsi_int_enable(); + scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */ + /* now we have to wait for IRQs */ +retry: + /* + * This version of the driver is _not_ interrupt driven, + * but polls the chip's interrupt registers (ISTAT, DSTAT). + */ + while(int_stat[0]==0) + handle_scsi_int(); + + if(int_stat[0]==SIR_COMPLETE) { + if(pccb->msgin[0]==M_DISCONNECT) { + PRINTF("Wait for reselection\n"); + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */ + goto retry; + } + pccb->contr_stat=SIR_COMPLETE; + return; + } + if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */ + sstat=(unsigned short)int_stat[0]; + if((sstat & STO)==STO) { /* selection timeout */ + pccb->contr_stat=SCSI_SEL_TIME_OUT; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Selection Timeout\n",pccb->target); + return; + } + if((sstat & UDC)==UDC) { /* unexpected disconnect */ + pccb->contr_stat=SCSI_UNEXP_DIS; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); + return; + } + if((sstat & RSL)==RSL) { /* reselection */ + pccb->contr_stat=SCSI_UNEXP_DIS; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); + return; + } + if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */ + if(retrycnttrans_bytes=pccb->datalen - + ((unsigned long)scsi_read_byte(DBC) | + ((unsigned long)scsi_read_byte(DBC+1)<<8) | + ((unsigned long)scsi_read_byte(DBC+2)<<16)); + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + retrycnt++; + PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n", + pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes); + scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */ + goto retry; + } + if((sstat & MA)==MA) + pccb->contr_stat=SCSI_MA_TIME_OUT; + else + pccb->contr_stat=SCSI_HNS_TIME_OUT; + PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat); + return; + } /* no phase int */ +/* if((sstat & CMP)==CMP) { + pccb->contr_stat=SIR_COMPLETE; + return; + } +*/ + PRINTF("SCSI INT %lX\n",int_stat[0]); + pccb->contr_stat=int_stat[0]; + return; + } /* end scsi int */ + PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL)); + pccb->contr_stat=int_stat[0]; + return; +} + +int scsi_exec(ccb *pccb) +{ + unsigned char tmpcmd[16],tmpstat; + int i,retrycnt,t; + unsigned long transbytes,datalen; + unsigned char *tmpptr; + retrycnt=0; +retry: + scsi_issue(pccb); + if(pccb->contr_stat!=SIR_COMPLETE) + return FALSE; + if(pccb->status==S_GOOD) + return TRUE; + if(pccb->status==S_CHECK_COND) { /* check condition */ + for(i=0;i<16;i++) + tmpcmd[i]=pccb->cmd[i]; + pccb->cmd[0]=SCSI_REQ_SENSE; + pccb->cmd[1]=pccb->lun<<5; + pccb->cmd[2]=0; + pccb->cmd[3]=0; + pccb->cmd[4]=14; + pccb->cmd[5]=0; + pccb->cmdlen=6; + pccb->msgout[0]=SCSI_IDENTIFY; + transbytes=pccb->trans_bytes; + tmpptr=pccb->pdata; + pccb->pdata=&pccb->sense_buf[0]; + datalen=pccb->datalen; + pccb->datalen=14; + tmpstat=pccb->status; + scsi_issue(pccb); + for(i=0;i<16;i++) + pccb->cmd[i]=tmpcmd[i]; + pccb->trans_bytes=transbytes; + pccb->pdata=tmpptr; + pccb->datalen=datalen; + pccb->status=tmpstat; + PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f, + pccb->sense_buf[12],pccb->sense_buf[13]); + switch(pccb->sense_buf[2]&0xf) { + case SENSE_NO_SENSE: + case SENSE_RECOVERED_ERROR: + /* seems to be ok */ + return TRUE; + break; + case SENSE_NOT_READY: + if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) { + /* if device is not in process of becoming ready */ + return FALSE; + break; + } /* else fall through */ + case SENSE_UNIT_ATTENTION: + if(retrycnttarget,retrycnt); + for(t=0;ttarget,retrycnt); + return FALSE; + default: + return FALSE; + } + } + PRINTF("Status = %X\n",pccb->status); + return FALSE; +} + + +void scsi_chip_init(void) +{ + /* first we issue a soft reset */ + scsi_write_byte(ISTAT,SRST); + udelay(1000); + scsi_write_byte(ISTAT,0); + /* setup chip */ + scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */ + scsi_write_byte(SCNTL1,0x00); + scsi_write_byte(SCNTL2,0x00); +#ifndef CFG_SCSI_SYM53C8XX_CCF /* config value for none 40 mhz clocks */ + scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */ +#else + scsi_write_byte(SCNTL3,CFG_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */ +#endif + scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */ + scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */ + scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */ + scsi_int_mask=0x0000; /* no Interrupt is enabled */ + script_int_mask=0x00; + scsi_int_enable(); + scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */ + scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */ + scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */ + scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */ + scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */ + scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */ + scsi_write_byte(STEST3,0x80); /* enable tolerANT */ + scsi_write_byte(CTEST3,0x04); /* clear FIFO */ + scsi_write_byte(CTEST4,0x00); + scsi_write_byte(CTEST5,0x00); +#ifdef SCSI_SINGLE_STEP +/* scsi_write_byte(DCNTL,IRQM | SSM); */ + scsi_write_byte(DCNTL,IRQD | SSM); + scsi_write_byte(DMODE,MAN); +#else +/* scsi_write_byte(DCNTL,IRQM); */ + scsi_write_byte(DCNTL,IRQD); + scsi_write_byte(DMODE,0x00); +#endif +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_SCSI) */ + + +#endif /* CONFIG_SCSI_SYM53C8XX */ diff --git a/drivers/ti_pci1410a.c b/drivers/ti_pci1410a.c new file mode 100644 index 0000000..d5297b5 --- /dev/null +++ b/drivers/ti_pci1410a.c @@ -0,0 +1,665 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * + * Lots of code copied from: + * + * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. + * (C) 1999-2000 Magnus Damm + * + * "The ExCA standard specifies that socket controllers should provide + * two IO and five memory windows per socket, which can be independently + * configured and positioned in the host address space and mapped to + * arbitrary segments of card address space. " - David A Hinds. 1999 + * + * This controller does _not_ meet the ExCA standard. + * + * m8xx pcmcia controller brief info: + * + 8 windows (attrib, mem, i/o) + * + up to two slots (SLOT_A and SLOT_B) + * + inputpins, outputpins, event and mask registers. + * - no offset register. sigh. + * + * Because of the lacking offset register we must map the whole card. + * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. + * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO + * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. + * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. + * They are maximum 64KByte each... + */ + + +#undef DEBUG /**/ + +/* + * PCMCIA support + */ +#include +#include +#include +#include +#include + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && defined(CONFIG_IDE_TI_CARDBUS) + +int pcmcia_on(int ide_base_bus); + +static int pcmcia_off(void); +static int hardware_disable(int slot); +static int hardware_enable(int slot); +static int voltage_set(int slot, int vcc, int vpp); +static void print_funcid(int func); +static void print_fixed(volatile uchar *p); +static int identify(volatile uchar *p); +static int check_ide_device(int slot, int ide_base_bus); + + +/* ------------------------------------------------------------------------- */ + + +const char *indent = "\t "; + +/* ------------------------------------------------------------------------- */ + + +int do_pinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#ifndef CFG_FIRST_PCMCIA_BUS +# define CFG_FIRST_PCMCIA_BUS 0 +#endif + + int rcode = 0; + + if (argc != 2) { + printf ("Usage: pinit {on | off}\n"); + return 1; + } + if (strcmp(argv[1],"on") == 0) { + rcode = pcmcia_on(CFG_FIRST_PCMCIA_BUS); + } else if (strcmp(argv[1],"off") == 0) { + rcode = pcmcia_off(); + } else { + printf ("Usage: pinit {on | off}\n"); + return 1; + } + + return rcode; +} + +/* ------------------------------------------------------------------------- */ + + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_TI, 0xac50 }, /* Ti PCI1410A */ + { PCI_VENDOR_ID_TI, 0xac56 }, /* Ti PCI1510 */ + { } +}; + +static pci_dev_t devbusfn; +static u32 socket_base; +static u32 pcmcia_cis_ptr; + +int pcmcia_on(int ide_base_bus) +{ + u16 dev_id; + u32 socket_status; + int slot = 0; + int cis_len; + u16 io_base; + u16 io_len; + + /* + * Find the CardBus PCI device(s). + */ + if ((devbusfn = pci_find_devices(supported, 0)) < 0) { + printf("Ti CardBus: not found\n"); + return 1; + } + + pci_read_config_word(devbusfn, PCI_DEVICE_ID, &dev_id); + + if (dev_id == 0xac56) { + debug("Enable PCMCIA Ti PCI1510\n"); + } else { + debug("Enable PCMCIA Ti PCI1410A\n"); + } + + pcmcia_cis_ptr = CFG_PCMCIA_CIS_WIN; + cis_len = CFG_PCMCIA_CIS_WIN_SIZE; + + io_base = CFG_PCMCIA_IO_WIN; + io_len = CFG_PCMCIA_IO_WIN_SIZE; + + /* + * Setup the PCI device. + */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &socket_base); + socket_base &= ~0xf; + + socket_status = readl(socket_base+8); + if ((socket_status & 6) == 0) { + printf("Card Present: "); + + switch (socket_status & 0x3c00) { + + case 0x400: + printf("5V "); + break; + case 0x800: + printf("3.3V "); + break; + case 0xc00: + printf("3.3/5V "); + break; + default: + printf("unsupported Vcc "); + break; + } + switch (socket_status & 0x30) { + case 0x10: + printf("16bit PC-Card\n"); + break; + case 0x20: + printf("32bit CardBus Card\n"); + break; + default: + printf("8bit PC-Card\n"); + break; + } + } + + + writeb(0x41, socket_base + 0x806); /* Enable I/O window 0 and memory window 0 */ + writeb(0x0e, socket_base + 0x807); /* Reset I/O window options */ + + /* Careful: the linux yenta driver do not seem to reset the offset + * in the i/o windows, so leaving them non-zero is a problem */ + + writeb(io_base & 0xff, socket_base + 0x808); /* I/O window 0 base address */ + writeb(io_base>>8, socket_base + 0x809); + writeb((io_base + io_len - 1) & 0xff, socket_base + 0x80a); /* I/O window 0 end address */ + writeb((io_base + io_len - 1)>>8, socket_base + 0x80b); + writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address 0x000 */ + writeb(0x00, socket_base + 0x837); + + + writeb((pcmcia_cis_ptr&0x000ff000) >> 12, + socket_base + 0x810); /* Memory window 0 start address bits 19-12 */ + writeb((pcmcia_cis_ptr&0x00f00000) >> 20, + socket_base + 0x811); /* Memory window 0 start address bits 23-20 */ + writeb(((pcmcia_cis_ptr+cis_len-1) & 0x000ff000) >> 12, + socket_base + 0x812); /* Memory window 0 end address bits 19-12*/ + writeb(((pcmcia_cis_ptr+cis_len-1) & 0x00f00000) >> 20, + socket_base + 0x813); /* Memory window 0 end address bits 23-20*/ + writeb(0x00, socket_base + 0x814); /* Memory window 0 offset bits 19-12 */ + writeb(0x40, socket_base + 0x815); /* Memory window 0 offset bits 23-20 and + * options (read/write, attribute access) */ + writeb(0x00, socket_base + 0x816); /* ExCA card-detect and general control */ + writeb(0x00, socket_base + 0x81e); /* ExCA global control (interrupt modes) */ + + writeb((pcmcia_cis_ptr & 0xff000000) >> 24, + socket_base + 0x840); /* Memory window address bits 31-24 */ + + + /* turn off voltage */ + if (voltage_set(slot, 0, 0)) { + return 1; + } + + /* Enable external hardware */ + if (hardware_enable(slot)) { + return 1; + } + + if (check_ide_device(slot, ide_base_bus)) { + return 1; + } + + return 0; +} + +/* ------------------------------------------------------------------------- */ + + +static int pcmcia_off (void) +{ + int slot = 0; + + writeb(0x00, socket_base + 0x806); /* disable all I/O and memory windows */ + + writeb(0x00, socket_base + 0x808); /* I/O window 0 base address */ + writeb(0x00, socket_base + 0x809); + writeb(0x00, socket_base + 0x80a); /* I/O window 0 end address */ + writeb(0x00, socket_base + 0x80b); + writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address */ + writeb(0x00, socket_base + 0x837); + + writeb(0x00, socket_base + 0x80c); /* I/O window 1 base address */ + writeb(0x00, socket_base + 0x80d); + writeb(0x00, socket_base + 0x80e); /* I/O window 1 end address */ + writeb(0x00, socket_base + 0x80f); + writeb(0x00, socket_base + 0x838); /* I/O window 1 offset address */ + writeb(0x00, socket_base + 0x839); + + writeb(0x00, socket_base + 0x810); /* Memory window 0 start address */ + writeb(0x00, socket_base + 0x811); + writeb(0x00, socket_base + 0x812); /* Memory window 0 end address */ + writeb(0x00, socket_base + 0x813); + writeb(0x00, socket_base + 0x814); /* Memory window 0 offset */ + writeb(0x00, socket_base + 0x815); + + writeb(0xc0, socket_base + 0x840); /* Memory window 0 page address */ + + + /* turn off voltage */ + voltage_set(slot, 0, 0); + + /* disable external hardware */ + printf ("Shutdown and Poweroff Ti PCI1410A\n"); + hardware_disable(slot); + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + + +#define MAX_TUPEL_SZ 512 +#define MAX_FEATURES 4 +int ide_devices_found; +static int check_ide_device(int slot, int ide_base_bus) +{ + volatile uchar *ident = NULL; + volatile uchar *feature_p[MAX_FEATURES]; + volatile uchar *p, *start; + int n_features = 0; + uchar func_id = ~0; + uchar code, len; + ushort config_base = 0; + int found = 0; + int i; + u32 socket_status; + + debug ("PCMCIA MEM: %08X\n", pcmcia_cis_ptr); + + socket_status = readl(socket_base+8); + + if ((socket_status & 6) != 0 || (socket_status & 0x20) != 0) { + printf("no card or CardBus card\n"); + return 1; + } + + start = p = (volatile uchar *) pcmcia_cis_ptr; + + while ((p - start) < MAX_TUPEL_SZ) { + + code = *p; p += 2; + + if (code == 0xFF) { /* End of chain */ + break; + } + + len = *p; p += 2; +#if defined(DEBUG) && (DEBUG > 1) + { + volatile uchar *q = p; + printf ("\nTuple code %02x length %d\n\tData:", + code, len); + + for (i = 0; i < len; ++i) { + printf (" %02x", *q); + q+= 2; + } + } +#endif /* DEBUG */ + switch (code) { + case CISTPL_VERS_1: + ident = p + 4; + break; + case CISTPL_FUNCID: + /* Fix for broken SanDisk which may have 0x80 bit set */ + func_id = *p & 0x7F; + break; + case CISTPL_FUNCE: + if (n_features < MAX_FEATURES) + feature_p[n_features++] = p; + break; + case CISTPL_CONFIG: + config_base = (*(p+6) << 8) + (*(p+4)); + debug ("\n## Config_base = %04x ###\n", config_base); + default: + break; + } + p += 2 * len; + } + + found = identify(ident); + + if (func_id != ((uchar)~0)) { + print_funcid (func_id); + + if (func_id == CISTPL_FUNCID_FIXED) + found = 1; + else + return 1; /* no disk drive */ + } + + for (i=0; i id_str) { + if (*t == ' ') { + *t = '\0'; + } else { + break; + } + } + puts(id_str); + putc('\n'); + + for (card=known_cards; *card; ++card) { + debug ("## Compare against \"%s\"\n", *card); + if (strcmp(*card, id_str) == 0) { /* found! */ + debug ("## CARD FOUND ##\n"); + return 1; + } + } + + return 0; /* don't know */ +} + +#endif /* CONFIG_IDE_TI_CARDBUS */ diff --git a/drivers/tigon3.c b/drivers/tigon3.c new file mode 100644 index 0000000..ec2cd2a --- /dev/null +++ b/drivers/tigon3.c @@ -0,0 +1,6200 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_TIGON3) +#ifdef CONFIG_BMW +#include +#endif +#include +#include +#include "bcm570x_mm.h" + +#define EMBEDDED 1 +/******************************************************************************/ +/* Local functions. */ +/******************************************************************************/ + +LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); + +static LM_STATUS LM_TranslateRequestedMediaType( + LM_REQUESTED_MEDIA_TYPE RequestedMediaType, + PLM_MEDIA_TYPE pMediaType, PLM_LINE_SPEED pLineSpeed, + PLM_DUPLEX_MODE pDuplexMode); + +static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice); + +__inline static LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice); +__inline static LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice); + +static LM_STATUS LM_ForceAutoNegBcm540xPhy(PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); +static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); +static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd); +#if INCLUDE_TBI_SUPPORT +STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice); +#endif +STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice); +STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid); +STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, + LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize); +STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number); +STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, + PT3_SND_BD pSendBd); + +/******************************************************************************/ +/* External functions. */ +/******************************************************************************/ + +LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice); + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_UINT32 +LM_RegRdInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 Register) { + LM_UINT32 Value32; + +#if PCIX_TARGET_WORKAROUND + MM_ACQUIRE_UNDI_LOCK(pDevice); +#endif + MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32); +#if PCIX_TARGET_WORKAROUND + MM_RELEASE_UNDI_LOCK(pDevice); +#endif + + return Value32; +} /* LM_RegRdInd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_RegWrInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 Register, +LM_UINT32 Value32) { + +#if PCIX_TARGET_WORKAROUND + MM_ACQUIRE_UNDI_LOCK(pDevice); +#endif + MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, Value32); +#if PCIX_TARGET_WORKAROUND + MM_RELEASE_UNDI_LOCK(pDevice); +#endif +} /* LM_RegWrInd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_UINT32 +LM_MemRdInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 MemAddr) { + LM_UINT32 Value32; + + MM_ACQUIRE_UNDI_LOCK(pDevice); +#ifdef BIG_ENDIAN_HOST + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + Value32 = REG_RD(pDevice, PciCfg.MemWindowData); + /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */ +#else + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32); +#endif + MM_RELEASE_UNDI_LOCK(pDevice); + + return Value32; +} /* LM_MemRdInd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_MemWrInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 MemAddr, +LM_UINT32 Value32) { + MM_ACQUIRE_UNDI_LOCK(pDevice); +#ifdef BIG_ENDIAN_HOST + REG_WR(pDevice,PciCfg.MemWindowBaseAddr,MemAddr); + REG_WR(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4],Value32); +#else + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32); +#endif + MM_RELEASE_UNDI_LOCK(pDevice); +} /* LM_MemWrInd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_QueueRxPackets( +PLM_DEVICE_BLOCK pDevice) { + LM_STATUS Lmstatus; + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; + LM_UINT32 StdBdAdded = 0; +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + LM_UINT32 JumboBdAdded = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + Lmstatus = LM_STATUS_SUCCESS; + + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + while(pPacket) { + switch(pPacket->u.Rx.RcvProdRing) { +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = + &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx]; + pRcvBd->Flags = RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING; + pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize; + + /* Initialize the receive buffer pointer */ +#if 0 /* Jimmy, deleted in new */ + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; +#endif + MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - + MM_UINT_PTR(pDevice->pPacketDescBase)); + + /* Update the producer index. */ + pDevice->RxJumboProdIdx = (pDevice->RxJumboProdIdx + 1) & + T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + + JumboBdAdded++; + break; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx]; + pRcvBd->Flags = RCV_BD_FLAG_END; + pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE; + + /* Initialize the receive buffer pointer */ +#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */ + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; +#endif + MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - + MM_UINT_PTR(pDevice->pPacketDescBase)); + + /* Update the producer index. */ + pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) & + T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + + StdBdAdded++; + break; + + case T3_UNKNOWN_RCV_PROD_RING: + default: + Lmstatus = LM_STATUS_FAILURE; + break; + } /* switch */ + + /* Bail out if there is any error. */ + if(Lmstatus != LM_STATUS_SUCCESS) + { + break; + } + + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + } /* while */ + + wmb(); + /* Update the procedure index. */ + if(StdBdAdded) + { + MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, pDevice->RxStdProdIdx); + } +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if(JumboBdAdded) + { + MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, + pDevice->RxJumboProdIdx); + } +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + return Lmstatus; +} /* LM_QueueRxPackets */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_VOID +LM_NvramInit( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + /* Intialize clock period and state machine. */ + Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) | + SEEPROM_ADDR_FSM_RESET; + REG_WR(pDevice, Grc.EepromAddr, Value32); + + for(j = 0; j < 100; j++) + { + MM_Wait(10); + } + + /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */ + Value32 = REG_RD(pDevice, Grc.LocalCtrl); + REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM); + + /* Set the 5701 compatibility mode if we are using EEPROM. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + { + Value32 = REG_RD(pDevice, Nvram.Config1); + if((Value32 & FLASH_INTERFACE_ENABLE) == 0) + { + /* Use the new interface to read EEPROM. */ + Value32 &= ~FLASH_COMPAT_BYPASS; + + REG_WR(pDevice, Nvram.Config1, Value32); + } + } +} /* LM_NvRamInit */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_EepromRead( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pData) +{ + LM_UINT32 Value32; + LM_UINT32 Addr; + LM_UINT32 Dev; + LM_UINT32 j; + + if(Offset > SEEPROM_CHIP_SIZE) + { + return LM_STATUS_FAILURE; + } + + Dev = Offset / SEEPROM_CHIP_SIZE; + Addr = Offset % SEEPROM_CHIP_SIZE; + + Value32 = REG_RD(pDevice, Grc.EepromAddr); + Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK | + SEEPROM_ADDR_RW_MASK); + REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) | + SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ); + + for(j = 0; j < 1000; j++) + { + Value32 = REG_RD(pDevice, Grc.EepromAddr); + if(Value32 & SEEPROM_ADDR_COMPLETE) + { + break; + } + MM_Wait(10); + } + + if(Value32 & SEEPROM_ADDR_COMPLETE) + { + Value32 = REG_RD(pDevice, Grc.EepromData); + *pData = Value32; + + return LM_STATUS_SUCCESS; + } + + return LM_STATUS_FAILURE; +} /* LM_EepromRead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_NvramRead( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pData) +{ + LM_UINT32 Value32; + LM_STATUS Status; + LM_UINT32 j; + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Status = LM_EepromRead(pDevice, Offset, pData); + } + else + { + /* Determine if we have flash or EEPROM. */ + Value32 = REG_RD(pDevice, Nvram.Config1); + if(Value32 & FLASH_INTERFACE_ENABLE) + { + if(Value32 & FLASH_SSRAM_BUFFERRED_MODE) + { + Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) << + BUFFERED_FLASH_PAGE_POS) + + (Offset % BUFFERED_FLASH_PAGE_SIZE); + } + } + + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + for (j = 0; j < 1000; j++) + { + if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1) + { + break; + } + MM_Wait(20); + } + if (j == 1000) + { + return LM_STATUS_FAILURE; + } + + /* Read from flash or EEPROM with the new 5703/02 interface. */ + REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK); + + REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT | + NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); + + /* Wait for the done bit to clear. */ + for(j = 0; j < 500; j++) + { + MM_Wait(10); + + Value32 = REG_RD(pDevice, Nvram.Cmd); + if(!(Value32 & NVRAM_CMD_DONE)) + { + break; + } + } + + /* Wait for the done bit. */ + if(!(Value32 & NVRAM_CMD_DONE)) + { + for(j = 0; j < 500; j++) + { + MM_Wait(10); + + Value32 = REG_RD(pDevice, Nvram.Cmd); + if(Value32 & NVRAM_CMD_DONE) + { + MM_Wait(10); + + *pData = REG_RD(pDevice, Nvram.ReadData); + + /* Change the endianess. */ + *pData = ((*pData & 0xff) << 24)| ((*pData & 0xff00) << 8)| + ((*pData & 0xff0000) >> 8) | ((*pData >> 24) & 0xff); + + break; + } + } + } + + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1); + if(Value32 & NVRAM_CMD_DONE) + { + Status = LM_STATUS_SUCCESS; + } + else + { + Status = LM_STATUS_FAILURE; + } + } + + return Status; +} /* LM_NvramRead */ + + +STATIC void +LM_ReadVPD(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Vpd_arr[256/4]; + LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0]; + LM_UINT32 *Vpd_dptr = &Vpd_arr[0]; + LM_UINT32 Value32; + unsigned int j; + + /* Read PN from VPD */ + for (j = 0; j < 256; j += 4, Vpd_dptr++ ) + { + if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) { + printf("BCM570x: LM_ReadVPD: VPD read failed" + " (no EEPROM onboard)\n"); + return; + } + *Vpd_dptr = cpu_to_le32(Value32); + } + for (j = 0; j < 256; ) + { + unsigned int Vpd_r_len; + unsigned int Vpd_r_end; + + if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) + { + j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8); + } + else if (Vpd[j] == 0x90) + { + Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8); + j += 3; + Vpd_r_end = Vpd_r_len + j; + while (j < Vpd_r_end) + { + if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) + { + unsigned int len = Vpd[j + 2]; + + if (len <= 24) + { + memcpy(pDevice->PartNo, &Vpd[j + 3], len); + } + break; + } + else + { + if (Vpd[j + 2] == 0) + { + break; + } + j = j + Vpd[j + 2]; + } + } + break; + } + else { + break; + } + } +} + +STATIC void +LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32, offset, ver_offset; + int i; + + if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS) + return; + if (Value32 != 0xaa559966) + return; + if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS) + return; + + offset = ((offset & 0xff) << 24)| ((offset & 0xff00) << 8)| + ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff); + if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS) + return; + if ((Value32 == 0x0300000e) && + (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) && + (Value32 == 0)) { + + if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS) + return; + ver_offset = ((ver_offset & 0xff0000) >> 8) | + ((ver_offset >> 24) & 0xff); + for (i = 0; i < 16; i += 4) { + if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) != + LM_STATUS_SUCCESS) + { + return; + } + *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32); + } + } + else { + char c; + + if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS) + return; + + i = 0; + c = ((Value32 & 0xff0000) >> 16); + + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } + else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i++] = '.'; + c = (Value32 & 0xff000000) >> 24; + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } + else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i] = 0; + } +} + +STATIC void +LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 PciState = pDevice->PciState; + LM_UINT32 ClockCtrl; + char *SpeedStr = ""; + + if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) + { + strcpy(pDevice->BusSpeedStr, "32-bit "); + } + else + { + strcpy(pDevice->BusSpeedStr, "64-bit "); + } + if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) + { + strcat(pDevice->BusSpeedStr, "PCI "); + if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) + { + SpeedStr = "66MHz"; + } + else + { + SpeedStr = "33MHz"; + } + } + else + { + strcat(pDevice->BusSpeedStr, "PCIX "); + if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) + { + SpeedStr = "133MHz"; + } + else + { + ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f; + switch (ClockCtrl) + { + case 0: + SpeedStr = "33MHz"; + break; + + case 2: + SpeedStr = "50MHz"; + break; + + case 4: + SpeedStr = "66MHz"; + break; + + case 6: + SpeedStr = "100MHz"; + break; + + case 7: + SpeedStr = "133MHz"; + break; + } + } + } + strcat(pDevice->BusSpeedStr, SpeedStr); +} + +/******************************************************************************/ +/* Description: */ +/* This routine initializes default parameters and reads the PCI */ +/* configurations. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_GetAdapterInfo( +PLM_DEVICE_BLOCK pDevice) +{ + PLM_ADAPTER_INFO pAdapterInfo; + LM_UINT32 Value32; + LM_STATUS Status; + LM_UINT32 j; + LM_UINT32 EeSigFound; + LM_UINT32 EePhyTypeSerdes = 0; + LM_UINT32 EePhyLedMode = 0; + LM_UINT32 EePhyId = 0; + + /* Get Device Id and Vendor Id */ + Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->PciVendorId = (LM_UINT16) Value32; + pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16); + + /* If we are not getting the write adapter, exit. */ + if((Value32 != T3_PCI_ID_BCM5700) && + (Value32 != T3_PCI_ID_BCM5701) && + (Value32 != T3_PCI_ID_BCM5702) && + (Value32 != T3_PCI_ID_BCM5702x) && + (Value32 != T3_PCI_ID_BCM5702FE) && + (Value32 != T3_PCI_ID_BCM5703) && + (Value32 != T3_PCI_ID_BCM5703x) && + (Value32 != T3_PCI_ID_BCM5704)) + { + return LM_STATUS_FAILURE; + } + + Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->PciRevId = (LM_UINT8) Value32; + + /* Get IRQ. */ + Status = MM_ReadConfig32(pDevice, PCI_INT_LINE_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->Irq = (LM_UINT8) Value32; + + /* Get interrupt pin. */ + pDevice->IntPin = (LM_UINT8) (Value32 >> 8); + + /* Get chip revision id. */ + Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32); + pDevice->ChipRevId = Value32 >> 16; + + /* Get subsystem vendor. */ + Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->SubsystemVendorId = (LM_UINT16) Value32; + + /* Get PCI subsystem id. */ + pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16); + + /* Get the cache line size. */ + MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32); + pDevice->CacheLineSize = (LM_UINT8) Value32; + pDevice->SavedCacheLineReg = Value32; + + if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 && + pDevice->ChipRevId != T3_CHIP_ID_5703_A2 && + pDevice->ChipRevId != T3_CHIP_ID_5704_A0) + { + pDevice->UndiFix = FALSE; + } +#if !PCIX_TARGET_WORKAROUND + pDevice->UndiFix = FALSE; +#endif + /* Map the memory base to system address space. */ + if (!pDevice->UndiFix) + { + Status = MM_MapMemBase(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + /* Initialize the memory view pointer. */ + pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase; + } + +#if PCIX_TARGET_WORKAROUND + /* store whether we are in PCI are PCI-X mode */ + pDevice->EnablePciXFix = FALSE; + + MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); + if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) + { + /* Enable PCI-X workaround only if we are running on 5700 BX. */ + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + pDevice->EnablePciXFix = TRUE; + } + } + if (pDevice->UndiFix) + { + pDevice->EnablePciXFix = TRUE; + } +#endif + /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */ + /* management register may be clobbered which may cause the */ + /* BCM5700 to go into D3 state. While in this state, we will */ + /* not have memory mapped register access. As a workaround, we */ + /* need to restore the device to D0 state. */ + MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32); + Value32 |= T3_PM_PME_ASSERTED; + Value32 &= ~T3_PM_POWER_STATE_MASK; + Value32 |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32); + + /* read the current PCI command word */ + MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32); + + /* Make sure bus-mastering is enabled. */ + Value32 |= PCI_BUSMASTER_ENABLE; + +#if PCIX_TARGET_WORKAROUND + /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR# + are enabled */ + if (pDevice->EnablePciXFix == TRUE) { + Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | + PCI_PARITY_ERROR_ENABLE); + } + if (pDevice->UndiFix) + { + Value32 &= ~PCI_MEM_SPACE_ENABLE; + } + +#endif + + if(pDevice->EnableMWI) + { + Value32 |= PCI_MEMORY_WRITE_INVALIDATE; + } + else { + Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE); + } + + /* Error out if mem-mapping is NOT enabled for PCI systems */ + if (!(Value32 | PCI_MEM_SPACE_ENABLE)) + { + return LM_STATUS_FAILURE; + } + + /* save the value we are going to write into the PCI command word */ + pDevice->PciCommandStatusWords = Value32; + + Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + /* Set power state to D0. */ + LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + +#ifdef BIG_ENDIAN_PCI + pDevice->MiscHostCtrl = + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; +#else /* No CPU Swap modes for PCI IO */ + + /* Setup the mode registers. */ + pDevice->MiscHostCtrl = + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | +#ifdef BIG_ENDIAN_HOST + MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP | +#endif /* BIG_ENDIAN_HOST */ + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; +#endif /* !BIG_ENDIAN_PCI */ + + /* write to PCI misc host ctr first in order to enable indirect accesses */ + MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); + + REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl); + +#ifdef BIG_ENDIAN_PCI + Value32 = GRC_MODE_WORD_SWAP_DATA| + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; +#else +/* No CPU Swap modes for PCI IO */ +#ifdef BIG_ENDIAN_HOST + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; +#else + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; +#endif +#endif /* !BIG_ENDIAN_PCI */ + + REG_WR(pDevice, Grc.Mode, Value32); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1); + } + MM_Wait(40); + + /* Enable indirect memory access */ + REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + + if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) + { + REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK); + REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK); + MM_Wait(40); /* required delay is 27usec */ + } + REG_WR(pDevice, PciCfg.ClockCtrl, 0); + REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); + +#if PCIX_TARGET_WORKAROUND + MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); + if ((pDevice->EnablePciXFix == FALSE) && + ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) + { + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B5) + { + __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300])); + __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); + __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); + if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]))) + { + pDevice->EnablePciXFix = TRUE; + } + } + } +#endif +#if 1 + /* + * This code was at the beginning of else block below, but that's + * a bug if node address in shared memory. + */ + MM_Wait(50); + LM_NvramInit(pDevice); +#endif + /* Get the node address. First try to get in from the shared memory. */ + /* If the signature is not present, then get it from the NVRAM. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX); + if((Value32 >> 16) == 0x484b) + { + + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[1] = (LM_UINT8) Value32; + + Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX); + + pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24); + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[5] = (LM_UINT8) Value32; + + Status = LM_STATUS_SUCCESS; + } + else + { + Status = LM_NvramRead(pDevice, 0x7c, &Value32); + if(Status == LM_STATUS_SUCCESS) + { + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24); + + Status = LM_NvramRead(pDevice, 0x80, &Value32); + + pDevice->NodeAddress[2] = (LM_UINT8) Value32; + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24); + } + } + + /* Assign a default address. */ + if(Status != LM_STATUS_SUCCESS) + { +#ifndef EMBEDDED + printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n"); +#endif + pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10; + pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68; + pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76; + } + + pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0]; + pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1]; + pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2]; + pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3]; + pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4]; + pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5]; + + /* Initialize the default values. */ + pDevice->NoTxPseudoHdrChksum = FALSE; + pDevice->NoRxPseudoHdrChksum = FALSE; + pDevice->NicSendBd = FALSE; + pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT; + pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT; + pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS; + pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS; + pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES; + pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES; + pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS; + pDevice->EnableMWI = FALSE; + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->DisableAutoNeg = FALSE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO; + pDevice->LedMode = LED_MODE_AUTO; + pDevice->ResetPhyOnInit = TRUE; + pDevice->DelayPciGrant = TRUE; + pDevice->UseTaggedStatus = FALSE; + pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE; + + pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO; + pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO; + pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO; + + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE; + pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE; + pDevice->EnableTbi = FALSE; +#if INCLUDE_TBI_SUPPORT + pDevice->PollTbiLink = BAD_DEFAULT_VALUE; +#endif + + switch (T3_ASIC_REV(pDevice->ChipRevId)) + { + case T3_ASIC_REV_5704: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64; + break; + default: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96; + break; + } + + pDevice->LinkStatus = LM_STATUS_LINK_DOWN; + pDevice->QueueRxPackets = TRUE; + + pDevice->EnableWireSpeed = TRUE; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Make this is a known adapter. */ + pAdapterInfo = LM_GetAdapterInfoBySsid(pDevice->SubsystemVendorId, + pDevice->SubsystemId); + + pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK; + if (pDevice->BondId != GRC_MISC_BD_ID_5700 && + pDevice->BondId != GRC_MISC_BD_ID_5701 && + pDevice->BondId != GRC_MISC_BD_ID_5702FE && + pDevice->BondId != GRC_MISC_BD_ID_5703 && + pDevice->BondId != GRC_MISC_BD_ID_5703S && + pDevice->BondId != GRC_MISC_BD_ID_5704 && + pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) + { + return LM_STATUS_UNKNOWN_ADAPTER; + } + + pDevice->SplitModeEnable = SPLIT_MODE_DISABLE; + if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) && + (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) + { + pDevice->SplitModeEnable = SPLIT_MODE_ENABLE; + pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ; + } + + /* Get Eeprom info. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR); + if (Value32 == T3_NIC_DATA_SIG) + { + EeSigFound = TRUE; + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR); + + /* Determine PHY type. */ + switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) + { + case T3_NIC_CFG_PHY_TYPE_COPPER: + EePhyTypeSerdes = FALSE; + break; + + case T3_NIC_CFG_PHY_TYPE_FIBER: + EePhyTypeSerdes = TRUE; + break; + + default: + EePhyTypeSerdes = FALSE; + break; + } + + /* Determine PHY led mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) + { + case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED: + EePhyLedMode = LED_MODE_THREE_LINK; + break; + + case T3_NIC_CFG_LED_MODE_LINK_SPEED: + EePhyLedMode = LED_MODE_LINK10; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } + else + { + switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) + { + case T3_NIC_CFG_LED_MODE_OPEN_DRAIN: + EePhyLedMode = LED_MODE_OPEN_DRAIN; + break; + + case T3_NIC_CFG_LED_MODE_OUTPUT: + EePhyLedMode = LED_MODE_OUTPUT; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } + if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) + { + /* Enable EEPROM write protection. */ + if(Value32 & T3_NIC_EEPROM_WP) + { + pDevice->EepromWp = TRUE; + } + } + + /* Get the PHY Id. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR); + if (Value32) + { + EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) & + PHY_ID1_OUI_MASK) << 10; + + Value32 = Value32 & T3_NIC_PHY_ID2_MASK; + + EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); + } + else + { + EePhyId = 0; + } + } + else + { + EeSigFound = FALSE; + } + + /* Set the PHY address. */ + pDevice->PhyAddr = PHY_DEVICE_ID; + + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); + + /* Get the PHY id. */ + LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32); + pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10; + + LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32); + pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); + + /* Set the EnableTbi flag to false if we have a copper PHY. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM5400_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5401_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5411_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5701_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5703_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5704_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM8002_PHY_ID: + pDevice->EnableTbi = TRUE; + break; + + default: + + if (pAdapterInfo) + { + pDevice->PhyId = pAdapterInfo->PhyId; + pDevice->EnableTbi = pAdapterInfo->Serdes; + } + else if (EeSigFound) + { + pDevice->PhyId = EePhyId; + pDevice->EnableTbi = EePhyTypeSerdes; + } + break; + } + + /* Bail out if we don't know the copper PHY id. */ + if(UNKNOWN_PHY_ID(pDevice->PhyId) && !pDevice->EnableTbi) + { + return LM_STATUS_FAILURE; + } + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) + { + pDevice->SavedCacheLineReg &= 0xffff00ff; + pDevice->SavedCacheLineReg |= 0x4000; + } + } + /* Change driver parameters. */ + Status = MM_GetConfig(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + +#if INCLUDE_5701_AX_FIX + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + pDevice->ResetPhyOnInit = TRUE; + } +#endif + + /* Save the current phy link status. */ + if(!pDevice->EnableTbi) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + /* If we don't have link reset the PHY. */ + if(!(Value32 & PHY_STATUS_LINK_PASS) || pDevice->ResetPhyOnInit) + { + + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + + for(j = 0; j < 100; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) + { + MM_Wait(40); + break; + } + } + + +#if INCLUDE_5701_AX_FIX + /* 5701_AX_BX bug: only advertises 10mb speed. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + Value32 = BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL | BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } +#endif + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + LM_WritePhy(pDevice, 0x18, 0x0c00); + LM_WritePhy(pDevice, 0x17, 0x201f); + LM_WritePhy(pDevice, 0x15, 0x2aaa); + } + if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + LM_WritePhy(pDevice, 0x1c, 0x8d68); + LM_WritePhy(pDevice, 0x1c, 0x8d68); + } + /* Enable Ethernet@WireSpeed. */ + if(pDevice->EnableWireSpeed) + { + LM_WritePhy(pDevice, 0x18, 0x7007); + LM_ReadPhy(pDevice, 0x18, &Value32); + LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4); + } + } + } + + /* Turn off tap power management. */ + if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + { + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + + MM_Wait(40); + } + +#if INCLUDE_TBI_SUPPORT + pDevice->IgnoreTbiLinkChange = FALSE; + + if(pDevice->EnableTbi) + { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) || + pDevice->DisableAutoNeg) + { + pDevice->PollTbiLink = FALSE; + } + } + else + { + pDevice->PollTbiLink = FALSE; + } +#endif /* INCLUDE_TBI_SUPPORT */ + + /* UseTaggedStatus is only valid for 5701 and later. */ + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->UseTaggedStatus = FALSE; + + pDevice->CoalesceMode = 0; + } + else + { + pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT | + HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT; + } + + /* Set the status block size. */ + if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX && + T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) + { + pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE; + } + + /* Check the DURING_INT coalescing ticks parameters. */ + if(pDevice->UseTaggedStatus) + { + if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxCoalescingTicksDuringInt = + DEFAULT_RX_COALESCING_TICKS_DURING_INT; + } + + if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxCoalescingTicksDuringInt = + DEFAULT_TX_COALESCING_TICKS_DURING_INT; + } + + if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxMaxCoalescedFramesDuringInt = + DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT; + } + + if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxMaxCoalescedFramesDuringInt = + DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT; + } + } + else + { + if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxCoalescingTicksDuringInt = 0; + } + + if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxCoalescingTicksDuringInt = 0; + } + + if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxMaxCoalescedFramesDuringInt = 0; + } + + if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxMaxCoalescedFramesDuringInt = 0; + } + } + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */)) + { + pDevice->RxJumboDescCnt = 0; + if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) + { + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } + } + else + { + pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ + + COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK; + + if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) + { + pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE; + pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */; + } + pDevice->TxMtu = pDevice->RxMtu; + + } +#else + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + pDevice->RxPacketDescCnt = +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboDescCnt + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + pDevice->RxStdDescCnt; + + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) + { + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } + + if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) + { + pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE; + } + + /* Configure the proper ways to get link change interrupt. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } + else + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + } + } + else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + /* Auto-polling does not work on 5700_AX and 5700_BX. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } + } + + /* Determine the method to get link change status. */ + if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) + { + /* The link status bit in the status block does not work on 5700_AX */ + /* and 5700_BX chips. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + else + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK; + } + } + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + + /* Configure PHY led mode. */ + if(pDevice->LedMode == LED_MODE_AUTO) + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + if(pDevice->SubsystemVendorId == T3_SVID_DELL) + { + pDevice->LedMode = LED_MODE_LINK10; + } + else + { + pDevice->LedMode = LED_MODE_THREE_LINK; + + if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) + { + pDevice->LedMode = EePhyLedMode; + } + } + + /* bug? 5701 in LINK10 mode does not seem to work when */ + /* PhyIntMode is LINK_READY. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && +#if INCLUDE_TBI_SUPPORT + pDevice->EnableTbi == FALSE && +#endif + pDevice->LedMode == LED_MODE_LINK10) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + + if(pDevice->EnableTbi) + { + pDevice->LedMode = LED_MODE_THREE_LINK; + } + } + else + { + if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) + { + pDevice->LedMode = EePhyLedMode; + } + else + { + pDevice->LedMode = LED_MODE_OPEN_DRAIN; + } + } + } + + /* Enable OneDmaAtOnce. */ + if(pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) + { + pDevice->OneDmaAtOnce = FALSE; + } + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2) + { + pDevice->WolSpeed = WOL_SPEED_10MB; + } + else + { + pDevice->WolSpeed = WOL_SPEED_100MB; + } + + /* Offloadings. */ + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + + /* Turn off task offloading on Ax. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5700_B0) + { + pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); + } + pDevice->PciState = REG_RD(pDevice, PciCfg.PciState); + LM_ReadVPD(pDevice); + LM_ReadBootCodeVersion(pDevice); + LM_GetBusSpeed(pDevice); + + return LM_STATUS_SUCCESS; +} /* LM_GetAdapterInfo */ + +STATIC PLM_ADAPTER_INFO +LM_GetAdapterInfoBySsid( + LM_UINT16 Svid, + LM_UINT16 Ssid) +{ + static LM_ADAPTER_INFO AdapterArr[] = + { + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 }, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0}, + + { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 }, + { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 }, + + { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 }, + + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 }, + + }; + LM_UINT32 j; + + for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++) + { + if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) + { + return &AdapterArr[j]; + } + } + + return NULL; +} + + +/******************************************************************************/ +/* Description: */ +/* This routine sets up receive/transmit buffer descriptions queues. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_InitializeAdapter( +PLM_DEVICE_BLOCK pDevice) +{ + LM_PHYSICAL_ADDRESS MemPhy; + PLM_UINT8 pMemVirt; + PLM_PACKET pPacket; + LM_STATUS Status; + LM_UINT32 Size; + LM_UINT32 j; + + /* Set power state to D0. */ + LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + + /* Intialize the queues. */ + QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container, + MAX_RX_PACKET_DESC_COUNT); + QQ_InitQueue(&pDevice->RxPacketFreeQ.Container, + MAX_RX_PACKET_DESC_COUNT); + + QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue(&pDevice->TxPacketActiveQ.Container,MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT); + + /* Allocate shared memory for: status block, the buffers for receive */ + /* rings -- standard, mini, jumbo, and return rings. */ + Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) + + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + + /* Memory for host based Send BD. */ + if(pDevice->NicSendBd == FALSE) + { + Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + } + + /* Allocate the memory block. */ + Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + /* Program DMA Read/Write */ + if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) + { + pDevice->DmaReadWriteCtrl = 0x763f000f; + } + else + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) + { + pDevice->DmaReadWriteCtrl = 0x761f0000; + } + else + { + pDevice->DmaReadWriteCtrl = 0x761b000f; + } + if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) + { + pDevice->OneDmaAtOnce = TRUE; + } + } + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + pDevice->DmaReadWriteCtrl &= 0xfffffff0; + } + + if(pDevice->OneDmaAtOnce) + { + pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE; + } + REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + + if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + /* Status block. */ + pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt; + pDevice->StatusBlkPhy = MemPhy; + pMemVirt += T3_STATUS_BLOCK_SIZE; + LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE); + + /* Statistics block. */ + pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt; + pDevice->StatsBlkPhy = MemPhy; + pMemVirt += sizeof(T3_STATS_BLOCK); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK)); + + /* Receive standard BD buffer. */ + pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxStdBdPhy = MemPhy; + + pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Receive jumbo BD buffer. */ + pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxJumboBdPhy = MemPhy; + + pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Receive return BD buffer. */ + pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RcvRetBdPhy = MemPhy; + + pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + + /* Set up Send BD. */ + if(pDevice->NicSendBd == FALSE) + { + pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt; + pDevice->SendBdPhy = MemPhy; + + pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT); + } + else + { + pDevice->pSendBdVirt = (PT3_SND_BD) + pDevice->pMemView->uIntMem.First32k.BufferDesc; + pDevice->SendBdPhy.High = 0; + pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR; + } + + /* Allocate memory for packet descriptors. */ + Size = (pDevice->RxPacketDescCnt + + pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE; + Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->pPacketDescBase = (PLM_VOID) pPacket; + + /* Create transmit packet descriptors from the memory block and add them */ + /* to the TxPacketFreeQ for each send ring. */ + for(j = 0; j < pDevice->TxPacketDescCnt; j++) + { + /* Ring index. */ + pPacket->Flags = 0; + + /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */ + QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for(j.. */ + + /* Create receive packet descriptors from the memory block and add them */ + /* to the RxPacketFreeQ. Create the Standard packet descriptors. */ + for(j = 0; j < pDevice->RxStdDescCnt; j++) + { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING; + + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE; + + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Create the Jumbo packet descriptors. */ + for(j = 0; j < pDevice->RxJumboDescCnt; j++) + { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING; + + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize; + + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Initialize the rest of the packet descriptors. */ + Status = MM_InitializeUmPackets(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } /* if */ + + /* Default receive mask. */ + pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST | + LM_ACCEPT_UNICAST; + + /* Make sure we are in the first 32k memory window or NicSendBd. */ + REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); + + /* Initialize the hardware. */ + Status = LM_ResetAdapter(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + /* We are done with initialization. */ + pDevice->InitDone = TRUE; + + return LM_STATUS_SUCCESS; +} /* LM_InitializeAdapter */ + + +/******************************************************************************/ +/* Description: */ +/* This function Enables/Disables a given block. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_CntrlBlock( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 mask,LM_UINT32 cntrl) +{ + LM_UINT32 j,i,data; + LM_UINT32 MaxWaitCnt; + + MaxWaitCnt = 2; + j = 0; + + for(i = 0 ; i < 32; i++) + { + if(!(mask & (1 << i))) + continue; + + switch (1 << i) + { + case T3_BLOCK_DMA_RD: + data = REG_RD(pDevice, DmaRead.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~DMA_READ_MODE_ENABLE; + REG_WR(pDevice, DmaRead.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE); + break; + + case T3_BLOCK_DMA_COMP: + data = REG_RD(pDevice,DmaComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~DMA_COMP_MODE_ENABLE; + REG_WR(pDevice, DmaComp.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_RX_BD_INITIATOR: + data = REG_RD(pDevice, RcvBdIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_BD_IN_MODE_ENABLE; + REG_WR(pDevice, RcvBdIn.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE); + break; + + case T3_BLOCK_RX_BD_COMP: + data = REG_RD(pDevice, RcvBdComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_BD_COMP_MODE_ENABLE; + REG_WR(pDevice, RcvBdComp.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_DMA_WR: + data = REG_RD(pDevice, DmaWrite.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~DMA_WRITE_MODE_ENABLE; + REG_WR(pDevice, DmaWrite.Mode,data); + + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE); + break; + + case T3_BLOCK_MSI_HANDLER: + data = REG_RD(pDevice, Msi.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~MSI_MODE_ENABLE; + REG_WR(pDevice, Msi.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE); + break; + + case T3_BLOCK_RX_LIST_PLMT: + data = REG_RD(pDevice, RcvListPlmt.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_LIST_PLMT_MODE_ENABLE; + REG_WR(pDevice, RcvListPlmt.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE); + break; + + case T3_BLOCK_RX_LIST_SELECTOR: + data = REG_RD(pDevice, RcvListSel.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_LIST_SEL_MODE_ENABLE; + REG_WR(pDevice, RcvListSel.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE); + break; + + case T3_BLOCK_RX_DATA_INITIATOR: + data = REG_RD(pDevice, RcvDataBdIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_DATA_BD_IN_MODE_ENABLE; + REG_WR(pDevice, RcvDataBdIn.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE); + break; + + case T3_BLOCK_RX_DATA_COMP: + data = REG_RD(pDevice, RcvDataComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_DATA_COMP_MODE_ENABLE; + REG_WR(pDevice, RcvDataComp.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_HOST_COALESING: + data = REG_RD(pDevice, HostCoalesce.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~HOST_COALESCE_ENABLE; + REG_WR(pDevice, HostCoalesce.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE); + break; + + case T3_BLOCK_MAC_RX_ENGINE: + if(cntrl == LM_DISABLE) + { + pDevice->RxMode &= ~RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE)) + { + break; + } + MM_Wait(10); + } + } + else + { + pDevice->RxMode |= RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + } + break; + + case T3_BLOCK_MBUF_CLUSTER_FREE: + data = REG_RD(pDevice, MbufClusterFree.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE; + REG_WR(pDevice, MbufClusterFree.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_BD_INITIATOR: + data = REG_RD(pDevice, SndBdIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_BD_IN_MODE_ENABLE; + REG_WR(pDevice, SndBdIn.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndBdIn.Mode, data | SND_BD_IN_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_BD_COMP: + data = REG_RD(pDevice, SndBdComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_BD_COMP_MODE_ENABLE; + REG_WR(pDevice, SndBdComp.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_BD_SELECTOR: + data = REG_RD(pDevice, SndBdSel.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_BD_SEL_MODE_ENABLE; + REG_WR(pDevice, SndBdSel.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_DATA_INITIATOR: + data = REG_RD(pDevice, SndDataIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~T3_SND_DATA_IN_MODE_ENABLE; + REG_WR(pDevice, SndDataIn.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_DATA_COMP: + data = REG_RD(pDevice, SndDataComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_DATA_COMP_MODE_ENABLE; + REG_WR(pDevice, SndDataComp.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_MAC_TX_ENGINE: + if(cntrl == LM_DISABLE) + { + pDevice->TxMode &= ~TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + { + pDevice->TxMode |= TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + } + break; + + case T3_BLOCK_MEM_ARBITOR: + data = REG_RD(pDevice, MemArbiter.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~T3_MEM_ARBITER_MODE_ENABLE; + REG_WR(pDevice, MemArbiter.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE); + break; + + case T3_BLOCK_MBUF_MANAGER: + data = REG_RD(pDevice, BufMgr.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~BUFMGR_MODE_ENABLE; + REG_WR(pDevice, BufMgr.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, BufMgr.Mode,data | BUFMGR_MODE_ENABLE); + break; + + case T3_BLOCK_MAC_GLOBAL: + if(cntrl == LM_DISABLE) + { + pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } + else + { + pDevice->MacMode |= (MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + break; + + default: + return LM_STATUS_FAILURE; + } /* switch */ + + if(j >= MaxWaitCnt) + { + return LM_STATUS_FAILURE; + } + } + + return LM_STATUS_SUCCESS; +} + +/******************************************************************************/ +/* Description: */ +/* This function reinitializes the adapter. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_ResetAdapter( +PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT16 Value16; + LM_UINT32 j, k; + + /* Disable interrupt. */ + LM_DisableInterrupt(pDevice); + + /* May get a spurious interrupt */ + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED; + + /* Disable transmit and receive DMA engines. Abort all pending requests. */ + if(pDevice->InitDone) + { + LM_Abort(pDevice); + } + + pDevice->ShuttingDown = FALSE; + + LM_ResetChip(pDevice); + + /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */ + /* in other chip revisions. */ + if(pDevice->DelayPciGrant) + { + Value32 = REG_RD(pDevice, PciCfg.ClockCtrl); + REG_WR(pDevice, PciCfg.ClockCtrl, Value32 | BIT_31); + } + + if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 = REG_RD(pDevice, PciCfg.PciState); + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + REG_WR(pDevice, PciCfg.PciState, Value32); + } + } + + /* Enable TaggedStatus mode. */ + if(pDevice->UseTaggedStatus) + { + pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE; + } + + /* Restore PCI configuration registers. */ + MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); + MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + + /* Clear the statistics block. */ + for(j = 0x0300; j < 0x0b00; j++) + { + MEM_WR_OFFSET(pDevice, j, 0); + } + + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + + for(j = 0; j < 16; j++) + { + pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0; + pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0; + } + + for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++) + { + pDevice->pRxStdBdVirt[k].HostAddr.High = 0; + pDevice->pRxStdBdVirt[k].HostAddr.Low = 0; + } + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Receive jumbo BD buffer. */ + for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) + { + pDevice->pRxJumboBdVirt[k].HostAddr.High = 0; + pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0; + } +#endif + + REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + + /* GRC mode control register. */ +#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */ + Value32 = + GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_INT_ON_MAC_ATTN | + GRC_MODE_HOST_STACK_UP; +#else + /* No CPU Swap modes for PCI IO */ + Value32 = +#ifdef BIG_ENDIAN_HOST + GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA | +#else + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA | +#endif + GRC_MODE_INT_ON_MAC_ATTN | + GRC_MODE_HOST_STACK_UP; +#endif /* !BIG_ENDIAN_PCI */ + + /* Configure send BD mode. */ + if(pDevice->NicSendBd == FALSE) + { + Value32 |= GRC_MODE_HOST_SEND_BDS; + } + else + { + Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS; + } + + /* Configure pseudo checksum mode. */ + if(pDevice->NoTxPseudoHdrChksum) + { + Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM; + } + + if(pDevice->NoRxPseudoHdrChksum) + { + Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM; + } + + REG_WR(pDevice, Grc.Mode, Value32); + + /* Setup the timer prescalar register. */ + REG_WR(pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */ + + /* Set up the MBUF pool base address and size. */ + REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); + REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize); + + /* Set up the DMA descriptor pool base address and size. */ + REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR); + REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE); + + /* Configure MBUF and Threshold watermarks */ + /* Configure the DMA read MBUF low water mark. */ + if(pDevice->DmaMbufLowMark) + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + pDevice->DmaMbufLowMark); + } + else + { + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK); + } + else + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO); + } + } + + /* Configure the MAC Rx MBUF low water mark. */ + if(pDevice->RxMacMbufLowMark) + { + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + pDevice->RxMacMbufLowMark); + } + else + { + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK); + } + else + { + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO); + } + } + + /* Configure the MBUF high water mark. */ + if(pDevice->MbufHighMark) + { + REG_WR(pDevice, BufMgr.MbufHighWaterMark, pDevice->MbufHighMark); + } + else + { + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + REG_WR(pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK); + } + else + { + REG_WR(pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK_JUMBO); + } + } + + REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK); + REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK); + + /* Enable buffer manager. */ + REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); + + for(j = 0 ;j < 2000; j++) + { + if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE) + break; + MM_Wait(10); + } + + if(j >= 2000) + { + return LM_STATUS_FAILURE; + } + + /* Enable the FTQs. */ + REG_WR(pDevice, Ftq.Reset, 0xffffffff); + REG_WR(pDevice, Ftq.Reset, 0); + + /* Wait until FTQ is ready */ + for(j = 0; j < 2000; j++) + { + if(REG_RD(pDevice, Ftq.Reset) == 0) + break; + MM_Wait(10); + } + + if(j >= 2000) + { + return LM_STATUS_FAILURE; + } + + /* Initialize the Standard Receive RCB. */ + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High, + pDevice->RxStdBdPhy.High); + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low, + pDevice->RxStdBdPhy.Low); + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags, + MAX_STD_RCV_BUFFER_SIZE << 16); + + /* Initialize the Jumbo Receive RCB. */ + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High, + pDevice->RxJumboBdPhy.High); + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low, + pDevice->RxJumboBdPhy.Low); + + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0); + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Initialize the Mini Receive RCB. */ + REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); + + { + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR); + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR); + } + + /* Receive BD Ring replenish threshold. */ + REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8); +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Disable all the unused rings. */ + for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) { + MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); + } /* for */ + + /* Initialize the indices. */ + pDevice->SendProdIdx = 0; + pDevice->SendConIdx = 0; + + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0); + + /* Set up host or NIC based send RCB. */ + if(pDevice->NicSendBd == FALSE) + { + MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, + pDevice->SendBdPhy.High); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, + pDevice->SendBdPhy.Low); + + /* Set up the NIC ring address in the RCB. */ + MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR); + + /* Setup the RCB. */ + MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags, + T3_SEND_RCB_ENTRY_COUNT << 16); + + for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) + { + pDevice->pSendBdVirt[k].HostAddr.High = 0; + pDevice->pSendBdVirt[k].HostAddr.Low = 0; + } + } + else + { + MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0); + MEM_WR(pDevice, SendRcb[0].NicRingAddr, + pDevice->SendBdPhy.Low); + + for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) + { + __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.High)); + __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.Low)); + __raw_writel(0, &(pDevice->pSendBdVirt[k].u1.Len_Flags)); + pDevice->ShadowSendBd[k].HostAddr.High = 0; + pDevice->ShadowSendBd[k].u1.Len_Flags = 0; + } + } + atomic_set(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1); + + /* Configure the receive return rings. */ + for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) + { + MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); + } + + pDevice->RcvRetConIdx = 0; + + MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High, + pDevice->RcvRetBdPhy.High); + MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low, + pDevice->RcvRetBdPhy.Low); + + /* Set up the NIC ring address in the RCB. */ + /* Not very clear from the spec. I am guessing that for Receive */ + /* Return Ring, NicRingAddr is not used. */ + MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0); + + /* Setup the RCB. */ + MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags, + T3_RCV_RETURN_RCB_ENTRY_COUNT << 16); + + /* Reinitialize RX ring producer index */ + MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0); + MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0); + MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0); + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboProdIdx = 0; + pDevice->RxJumboQueuedCnt = 0; +#endif + + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; + pDevice->RxStdQueuedCnt = 0; + +#if T3_JUMBO_RCV_ENTRY_COUNT + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_ENTRY_COUNT */ + + /* Configure the MAC address. */ + LM_SetMacAddress(pDevice, pDevice->NodeAddress); + + /* Initialize the transmit random backoff seed. */ + Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] + + pDevice->NodeAddress[2] + pDevice->NodeAddress[3] + + pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) & + MAC_TX_BACKOFF_SEED_MASK; + REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32); + + /* Receive MTU. Frames larger than the MTU is marked as oversized. */ + REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */ + + /* Configure Time slot/IPG per 802.3 */ + REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); + + /* + * Configure Receive Rules so that packets don't match + * Programmble rule will be queued to Return Ring 1 + */ + REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS); + + /* + * Configure to have 16 Classes of Services (COS) and one + * queue per class. Bad frames are queued to RRR#1. + * And frames don't match rules are also queued to COS#1. + */ + REG_WR(pDevice, RcvListPlmt.Config, 0x181); + + /* Enable Receive Placement Statistics */ + REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff); + REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE); + + /* Enable Send Data Initator Statistics */ + REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff); + REG_WR(pDevice, SndDataIn.StatsCtrl, + T3_SND_DATA_IN_STATS_CTRL_ENABLE | \ + T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE); + + /* Disable the host coalescing state machine before configuring it's */ + /* parameters. */ + REG_WR(pDevice, HostCoalesce.Mode, 0); + for(j = 0; j < 2000; j++) + { + Value32 = REG_RD(pDevice, HostCoalesce.Mode); + if(!(Value32 & HOST_COALESCE_ENABLE)) + { + break; + } + MM_Wait(10); + } + + /* Host coalescing configurations. */ + REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks); + REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks); + REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames, + pDevice->RxMaxCoalescedFrames); + REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames, + pDevice->TxMaxCoalescedFrames); + REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt, + pDevice->RxCoalescingTicksDuringInt); + REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt, + pDevice->TxCoalescingTicksDuringInt); + REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt, + pDevice->RxMaxCoalescedFramesDuringInt); + REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt, + pDevice->TxMaxCoalescedFramesDuringInt); + + /* Initialize the address of the status block. The NIC will DMA */ + /* the status block to this memory which resides on the host. */ + REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High, + pDevice->StatusBlkPhy.High); + REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low, + pDevice->StatusBlkPhy.Low); + + /* Initialize the address of the statistics block. The NIC will DMA */ + /* the statistics to this block of memory. */ + REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High, + pDevice->StatsBlkPhy.High); + REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low, + pDevice->StatsBlkPhy.Low); + + REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, + pDevice->StatsCoalescingTicks); + + REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300); + REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00); + + /* Enable Host Coalesing state machine */ + REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE | + pDevice->CoalesceMode); + + /* Enable the Receive BD Completion state machine. */ + REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE | + RCV_BD_COMP_MODE_ATTN_ENABLE); + + /* Enable the Receive List Placement state machine. */ + REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE); + + /* Enable the Receive List Selector state machine. */ + REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE | + RCV_LIST_SEL_MODE_ATTN_ENABLE); + + /* Enable transmit DMA, clear statistics. */ + pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS | + MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS); + + /* GRC miscellaneous local control register. */ + pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN | + GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM; + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1; + } + + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait(40); + + /* Reset RX counters. */ + for(j = 0; j < sizeof(LM_RX_COUNTERS); j++) + { + ((PLM_UINT8) &pDevice->RxCounters)[j] = 0; + } + + /* Reset TX counters. */ + for(j = 0; j < sizeof(LM_TX_COUNTERS); j++) + { + ((PLM_UINT8) &pDevice->TxCounters)[j] = 0; + } + + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); + + /* Enable the DMA Completion state machine. */ + REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE); + + /* Enable the DMA Write state machine. */ + Value32 = DMA_WRITE_MODE_ENABLE | + DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE; + REG_WR(pDevice, DmaWrite.Mode, Value32); + + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + Value16 = REG_RD(pDevice, PciCfg.PciXCommand); + Value16 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK); + Value16 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) & + PCIX_CMD_MAX_BURST_MASK); + if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) + { + Value16 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL) + & PCIX_CMD_MAX_SPLIT_MASK; + } + REG_WR(pDevice, PciCfg.PciXCommand, Value16); + } + } + + /* Enable the Read DMA state machine. */ + Value32 = DMA_READ_MODE_ENABLE | + DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_READ_MODE_LONG_READ_ATTN_ENABLE; + + if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) + { + Value32 |= DMA_READ_MODE_SPLIT_ENABLE; + } + REG_WR(pDevice, DmaRead.Mode, Value32); + + /* Enable the Receive Data Completion state machine. */ + REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE | + RCV_DATA_COMP_MODE_ATTN_ENABLE); + + /* Enable the Mbuf Cluster Free state machine. */ + REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE); + + /* Enable the Send Data Completion state machine. */ + REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE); + + /* Enable the Send BD Completion state machine. */ + REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE | + SND_BD_COMP_MODE_ATTN_ENABLE); + + /* Enable the Receive BD Initiator state machine. */ + REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE | + RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE); + + /* Enable the Receive Data and Receive BD Initiator state machine. */ + REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE | + RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE); + + /* Enable the Send Data Initiator state machine. */ + REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE); + + /* Enable the Send BD Initiator state machine. */ + REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE | + SND_BD_IN_MODE_ATTN_ENABLE); + + /* Enable the Send BD Selector state machine. */ + REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE | + SND_BD_SEL_MODE_ATTN_ENABLE); + +#if INCLUDE_5701_AX_FIX + /* Load the firmware for the 5701_A0 workaround. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0) + { + LM_LoadRlsFirmware(pDevice); + } +#endif + + /* Enable the transmitter. */ + pDevice->TxMode = TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + + /* Enable the receiver. */ + pDevice->RxMode = RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + + if (pDevice->RestoreOnWakeUp) + { + pDevice->RestoreOnWakeUp = FALSE; + pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg; + pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType; + } + + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = LED_CTRL_PHY_MODE_1; + } + else + { + if(pDevice->LedMode == LED_MODE_OUTPUT) + { + Value32 = LED_CTRL_PHY_MODE_2; + } + else + { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + REG_WR(pDevice, MacCtrl.LedCtrl, Value32); + + /* Activate Link to enable MAC state machine */ + REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN); + + if (pDevice->EnableTbi) + { + REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET); + MM_Wait(10); + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) + { + REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000); + } + } + /* Setup the phy chip. */ + LM_SetupPhy(pDevice); + + if (!pDevice->EnableTbi) { + /* Clear CRC stats */ + LM_ReadPhy(pDevice, 0x1e, &Value32); + LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000); + LM_ReadPhy(pDevice, 0x14, &Value32); + } + + /* Set up the receive mask. */ + LM_SetReceiveMask(pDevice, pDevice->ReceiveMask); + + /* Queue Rx packet buffers. */ + if(pDevice->QueueRxPackets) + { + LM_QueueRxPackets(pDevice); + } + + /* Enable interrupt to the host. */ + if(pDevice->InitDone) + { + LM_EnableInterrupt(pDevice); + } + + return LM_STATUS_SUCCESS; +} /* LM_ResetAdapter */ + + +/******************************************************************************/ +/* Description: */ +/* This routine disables the adapter from generating interrupts. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_DisableInterrupt( + PLM_DEVICE_BLOCK pDevice) +{ + REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl | + MISC_HOST_CTRL_MASK_PCI_INT); + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); + + return LM_STATUS_SUCCESS; +} + + +/******************************************************************************/ +/* Description: */ +/* This routine enables the adapter to generate interrupts. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_EnableInterrupt( + PLM_DEVICE_BLOCK pDevice) +{ + REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl & + ~MISC_HOST_CTRL_MASK_PCI_INT); + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); + + if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) + { + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_SET_INT); + } + + return LM_STATUS_SUCCESS; +} + + +/******************************************************************************/ +/* Description: */ +/* This routine puts a packet on the wire if there is a transmit DMA */ +/* descriptor available; otherwise the packet is queued for later */ +/* transmission. If the second argue is NULL, this routine will put */ +/* the queued packet on the wire if possible. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +#if 0 +LM_STATUS +LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + LM_UINT32 FragCount; + PT3_SND_BD pSendBd; + PT3_SND_BD pShadowSendBd; + LM_UINT32 Value32, Len; + LM_UINT32 Idx; + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { + return LM_5700SendPacket(pDevice, pPacket); + } + + /* Update the SendBdLeft count. */ + atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + /* Initalize the send buffer descriptors. */ + Idx = pDevice->SendProdIdx; + + pSendBd = &pDevice->pSendBdVirt[Idx]; + + /* Next producer index. */ + if (pDevice->NicSendBd == TRUE) + { + T3_64BIT_HOST_ADDR paddr; + + pShadowSendBd = &pDevice->ShadowSendBd[Idx]; + for(FragCount = 0; ; ) + { + MM_MapTxDma(pDevice, pPacket, &paddr, &Len, FragCount); + /* Initialize the pointer to the send buffer fragment. */ + if (paddr.High != pShadowSendBd->HostAddr.High) + { + __raw_writel(paddr.High, &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = paddr.High; + } + __raw_writel(paddr.Low, &(pSendBd->HostAddr.Low)); + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + Value32 |= SND_BD_FLAG_END; + if (Value32 != pShadowSendBd->u1.Len_Flags) + { + __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); + } + break; + } + else + { + if (Value32 != pShadowSendBd->u1.Len_Flags) + { + __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); + } + } + + pSendBd++; + pShadowSendBd++; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + pShadowSendBd = &pDevice->ShadowSendBd[0]; + } + } /* for */ + + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + + wmb(); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + + } + else + { + for(FragCount = 0; ; ) + { + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + + pSendBd->u2.VlanTag = pPacket->VlanTag; + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; + break; + } + else + { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ + + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + + wmb(); + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + + } + + /* Update the producer index. */ + pDevice->SendProdIdx = Idx; + + return LM_STATUS_SUCCESS; +} +#endif + +LM_STATUS +LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + LM_UINT32 FragCount; + PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd; + T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT]; + LM_UINT32 StartIdx, Idx; + + while (1) + { + /* Initalize the send buffer descriptors. */ + StartIdx = Idx = pDevice->SendProdIdx; + + if (pDevice->NicSendBd) + { + pTmpSendBd = pSendBd = &NicSendBdArr[0]; + } + else + { + pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx]; + } + + /* Next producer index. */ + for(FragCount = 0; ; ) + { + LM_UINT32 Value32, Len; + + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + + pSendBd->u2.VlanTag = pPacket->VlanTag; + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; + break; + } + else + { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if ((Idx == 0) && !pDevice->NicSendBd) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) == + LM_STATUS_SUCCESS) + { + if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS) + { + QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + return LM_STATUS_FAILURE; + } + continue; + } + } + break; + } + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + + if (pDevice->NicSendBd) + { + pSendBd = &pDevice->pSendBdVirt[StartIdx]; + pShadowSendBd = &pDevice->ShadowSendBd[StartIdx]; + + while (StartIdx != Idx) + { + LM_UINT32 Value32; + + if ((Value32 = pTmpSendBd->HostAddr.High) != + pShadowSendBd->HostAddr.High) + { + __raw_writel(Value32, &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = Value32; + } + + __raw_writel(pTmpSendBd->HostAddr.Low, &(pSendBd->HostAddr.Low)); + + if ((Value32 = pTmpSendBd->u1.Len_Flags) != + pShadowSendBd->u1.Len_Flags) + { + __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) + { + __raw_writel(pTmpSendBd->u2.VlanTag, &(pSendBd->u2.VlanTag)); + } + + StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (StartIdx == 0) + pSendBd = &pDevice->pSendBdVirt[0]; + else + pSendBd++; + pTmpSendBd++; + } + wmb(); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + } + } + else + { + wmb(); + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + } + } + + /* Update the SendBdLeft count. */ + atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + /* Update the producer index. */ + pDevice->SendProdIdx = Idx; + + return LM_STATUS_SUCCESS; +} + +STATIC LM_STATUS +LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, + PT3_SND_BD pSendBd) +{ + int FragCount; + LM_UINT32 Idx, Base, Len; + + Idx = pDevice->SendProdIdx; + for(FragCount = 0; ; ) + { + Len = pSendBd->u1.Len_Flags >> 16; + if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) && + (pSendBd->HostAddr.High == 0) && + ((Base + 8 + Len) < Base)) + { + return LM_STATUS_SUCCESS; + } + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + break; + } + pSendBd++; + if (!pDevice->NicSendBd) + { + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } + } + return LM_STATUS_FAILURE; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static unsigned long +ComputeCrc32( +unsigned char *pBuffer, +unsigned long BufferSize) { + unsigned long Reg; + unsigned long Tmp; + unsigned long j, k; + + Reg = 0xffffffff; + + for(j = 0; j < BufferSize; j++) + { + Reg ^= pBuffer[j]; + + for(k = 0; k < 8; k++) + { + Tmp = Reg & 0x01; + + Reg >>= 1; + + if(Tmp) + { + Reg ^= 0xedb88320; + } + } + } + + return ~Reg; +} /* ComputeCrc32 */ + + +/******************************************************************************/ +/* Description: */ +/* This routine sets the receive control register according to ReceiveMask */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_SetReceiveMask( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 Mask) { + LM_UINT32 ReceiveMask; + LM_UINT32 RxMode; + LM_UINT32 j, k; + + ReceiveMask = Mask; + + RxMode = pDevice->RxMode; + + if(Mask & LM_ACCEPT_UNICAST) + { + Mask &= ~LM_ACCEPT_UNICAST; + } + + if(Mask & LM_ACCEPT_MULTICAST) + { + Mask &= ~LM_ACCEPT_MULTICAST; + } + + if(Mask & LM_ACCEPT_ALL_MULTICAST) + { + Mask &= ~LM_ACCEPT_ALL_MULTICAST; + } + + if(Mask & LM_ACCEPT_BROADCAST) + { + Mask &= ~LM_ACCEPT_BROADCAST; + } + + RxMode &= ~RX_MODE_PROMISCUOUS_MODE; + if(Mask & LM_PROMISCUOUS_MODE) + { + RxMode |= RX_MODE_PROMISCUOUS_MODE; + Mask &= ~LM_PROMISCUOUS_MODE; + } + + RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED); + if(Mask & LM_ACCEPT_ERROR_PACKET) + { + RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED; + Mask &= ~LM_ACCEPT_ERROR_PACKET; + } + + /* Make sure all the bits are valid before committing changes. */ + if(Mask) + { + return LM_STATUS_FAILURE; + } + + /* Commit the new filter. */ + pDevice->RxMode = RxMode; + REG_WR(pDevice, MacCtrl.RxMode, RxMode); + + pDevice->ReceiveMask = ReceiveMask; + + /* Set up the MC hash table. */ + if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST) + { + for(k = 0; k < 4; k++) + { + REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff); + } + } + else if(ReceiveMask & LM_ACCEPT_MULTICAST) + { + LM_UINT32 HashReg[4]; + + HashReg[0] = 0; HashReg[1] = 0; HashReg[2] = 0; HashReg[3] = 0; + for(j = 0; j < pDevice->McEntryCount; j++) + { + LM_UINT32 RegIndex; + LM_UINT32 Bitpos; + LM_UINT32 Crc32; + + Crc32 = ComputeCrc32(pDevice->McTable[j], ETHERNET_ADDRESS_SIZE); + + /* The most significant 7 bits of the CRC32 (no inversion), */ + /* are used to index into one of the possible 128 bit positions. */ + Bitpos = ~Crc32 & 0x7f; + + /* Hash register index. */ + RegIndex = (Bitpos & 0x60) >> 5; + + /* Bit to turn on within a hash register. */ + Bitpos &= 0x1f; + + /* Enable the multicast bit. */ + HashReg[RegIndex] |= (1 << Bitpos); + } + + /* REV_AX has problem with multicast filtering where it uses both */ + /* DA and SA to perform hashing. */ + for(k = 0; k < 4; k++) + { + REG_WR(pDevice, MacCtrl.HashReg[k], HashReg[k]); + } + } + else + { + /* Reject all multicast frames. */ + for(j = 0; j < 4; j++) + { + REG_WR(pDevice, MacCtrl.HashReg[j], 0); + } + } + + /* By default, Tigon3 will accept broadcast frames. We need to setup */ + if(ReceiveMask & LM_ACCEPT_BROADCAST) + { + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + } + else + { + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE2_RULE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE2_VALUE); + } + + /* disable the rest of the rules. */ + for(j = RCV_LAST_RULE_IDX; j < 16; j++) + { + REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0); + REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0); + } + + return LM_STATUS_SUCCESS; +} /* LM_SetReceiveMask */ + + +/******************************************************************************/ +/* Description: */ +/* Disable the interrupt and put the transmitter and receiver engines in */ +/* an idle state. Also aborts all pending send requests and receive */ +/* buffers. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_Abort( +PLM_DEVICE_BLOCK pDevice) +{ + PLM_PACKET pPacket; + LM_UINT Idx; + + LM_DisableInterrupt(pDevice); + + /* Disable all the state machines. */ + LM_CntrlBlock(pDevice,T3_BLOCK_MAC_RX_ENGINE,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_INITIATOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_PLMT,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_SELECTOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_INITIATOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_COMP,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_COMP,LM_DISABLE); + + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_SELECTOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_INITIATOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_INITIATOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_DMA_RD,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_COMP,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_DMA_COMP,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_COMP,LM_DISABLE); + + /* Clear TDE bit */ + pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + LM_CntrlBlock(pDevice,T3_BLOCK_MAC_TX_ENGINE,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_HOST_COALESING,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_DMA_WR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_CLUSTER_FREE,LM_DISABLE); + + /* Reset all FTQs */ + REG_WR(pDevice, Ftq.Reset, 0xffffffff); + REG_WR(pDevice, Ftq.Reset, 0x0); + + LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_MANAGER,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_MEM_ARBITOR,LM_DISABLE); + + MM_ACQUIRE_INT_LOCK(pDevice); + + /* Abort packets that have already queued to go out. */ + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->TxPacketActiveQ.Container); + while(pPacket) + { + + pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED; + pDevice->TxCounters.TxPacketAbortedCnt++; + + atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); + + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->TxPacketActiveQ.Container); + } + + /* Cleanup the receive return rings. */ + LM_ServiceRxInterrupt(pDevice); + + /* Don't want to indicate rx packets in Ndis miniport shutdown context. */ + /* Doing so may cause system crash. */ + if(!pDevice->ShuttingDown) + { + /* Indicate packets to the protocol. */ + MM_IndicateTxPackets(pDevice); + + /* Indicate received packets to the protocols. */ + MM_IndicateRxPackets(pDevice); + } + else + { + /* Move the receive packet descriptors in the ReceivedQ to the */ + /* free queue. */ + for(; ;) + { + pPacket = (PLM_PACKET) QQ_PopHead( + &pDevice->RxPacketReceivedQ.Container); + if(pPacket == NULL) + { + break; + } + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } + } + + /* Clean up the Std Receive Producer ring. */ + Idx = pDevice->pStatusBlkVirt->RcvStdConIdx; + + while(Idx != pDevice->RxStdProdIdx) { + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pDevice->pRxStdBdVirt[Idx].Opaque)); + + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + } /* while */ + + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Clean up the Jumbo Receive Producer ring. */ + Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx; + + while(Idx != pDevice->RxJumboProdIdx) { + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pDevice->pRxJumboBdVirt[Idx].Opaque)); + + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + } /* while */ + + /* Reinitialize our copy of the indices. */ + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + MM_RELEASE_INT_LOCK(pDevice); + + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + + return LM_STATUS_SUCCESS; +} /* LM_Abort */ + + +/******************************************************************************/ +/* Description: */ +/* Disable the interrupt and put the transmitter and receiver engines in */ +/* an idle state. Aborts all pending send requests and receive buffers. */ +/* Also free all the receive buffers. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_Halt( +PLM_DEVICE_BLOCK pDevice) { + PLM_PACKET pPacket; + LM_UINT32 EntryCnt; + + LM_Abort(pDevice); + + /* Get the number of entries in the queue. */ + EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container); + + /* Make sure all the packets have been accounted for. */ + for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) + { + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + if (pPacket == 0) + break; + + MM_FreeRxBuffer(pDevice, pPacket); + + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } + + LM_ResetChip(pDevice); + + /* Restore PCI configuration registers. */ + MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); + LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + + /* Reprogram the MAC address. */ + LM_SetMacAddress(pDevice, pDevice->NodeAddress); + + return LM_STATUS_SUCCESS; +} /* LM_Halt */ + + +STATIC LM_STATUS +LM_ResetChip(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + /* Wait for access to the nvram interface before resetting. This is */ + /* a workaround to prevent EEPROM corruption. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + { + /* Request access to the flash interface. */ + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + + for(j = 0; j < 100000; j++) + { + Value32 = REG_RD(pDevice, Nvram.SwArb); + if(Value32 & SW_ARB_GNT1) + { + break; + } + MM_Wait(10); + } + } + + /* Global reset. */ + REG_WR(pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET); + MM_Wait(40); MM_Wait(40); MM_Wait(40); + + /* make sure we re-enable indirect accesses */ + MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, + pDevice->MiscHostCtrl); + + /* Set MAX PCI retry to zero. */ + Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE; + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + } + } + MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32); + + /* Restore PCI command register. */ + MM_WriteConfig32(pDevice, PCI_COMMAND_REG, + pDevice->PciCommandStatusWords); + + /* Disable PCI-X relaxed ordering bit. */ + MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32); + Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING; + MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32); + + /* Enable memory arbiter. */ + REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + +#ifdef BIG_ENDIAN_PCI /* This from jfd */ + Value32 = GRC_MODE_WORD_SWAP_DATA| + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; +#else +#ifdef BIG_ENDIAN_HOST + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA; +#else + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; +#endif +#endif + REG_WR(pDevice, Grc.Mode, Value32); + + /* Prevent PXE from restarting. */ + MEM_WR_OFFSET(pDevice, 0x0b50, T3_MAGIC_NUM); + + if(pDevice->EnableTbi) { + pDevice->MacMode = MAC_MODE_PORT_MODE_TBI; + REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI); + } + else { + REG_WR(pDevice, MacCtrl.Mode, 0); + } + + /* Wait for the firmware to finish initialization. */ + for(j = 0; j < 100000; j++) + { + MM_Wait(10); + + Value32 = MEM_RD_OFFSET(pDevice, 0x0b50); + if(Value32 == ~T3_MAGIC_NUM) + { + break; + } + } + return LM_STATUS_SUCCESS; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static void +LM_ServiceTxInterrupt( +PLM_DEVICE_BLOCK pDevice) { + PLM_PACKET pPacket; + LM_UINT32 HwConIdx; + LM_UINT32 SwConIdx; + + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; + + /* Get our copy of the consumer index. The buffer descriptors */ + /* that are in between the consumer indices are freed. */ + SwConIdx = pDevice->SendConIdx; + + /* Move the packets from the TxPacketActiveQ that are sent out to */ + /* the TxPacketXmittedQ. Packets that are sent use the */ + /* descriptors that are between SwConIdx and HwConIdx. */ + while(SwConIdx != HwConIdx) + { + /* Get the packet that was sent from the TxPacketActiveQ. */ + pPacket = (PLM_PACKET) QQ_PopHead( + &pDevice->TxPacketActiveQ.Container); + + /* Set the return status. */ + pPacket->PacketStatus = LM_STATUS_SUCCESS; + + /* Put the packet in the TxPacketXmittedQ for indication later. */ + QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); + + /* Move to the next packet's BD. */ + SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) & + T3_SEND_RCB_ENTRY_COUNT_MASK; + + /* Update the number of unused BDs. */ + atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + /* Get the new updated HwConIdx. */ + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; + } /* while */ + + /* Save the new SwConIdx. */ + pDevice->SendConIdx = SwConIdx; + +} /* LM_ServiceTxInterrupt */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static void +LM_ServiceRxInterrupt( +PLM_DEVICE_BLOCK pDevice) { + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; + LM_UINT32 HwRcvRetProdIdx; + LM_UINT32 SwRcvRetConIdx; + + /* Loop thru the receive return rings for received packets. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + + SwRcvRetConIdx = pDevice->RcvRetConIdx; + while(SwRcvRetConIdx != HwRcvRetProdIdx) + { + pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; + + /* Get the received packet descriptor. */ + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pRcvBd->Opaque)); + + /* Check the error flag. */ + if(pRcvBd->ErrorFlag && + pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pPacket->PacketStatus = LM_STATUS_FAILURE; + + pDevice->RxCounters.RxPacketErrCnt++; + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) + { + pDevice->RxCounters.RxErrCrcCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) + { + pDevice->RxCounters.RxErrCollCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) + { + pDevice->RxCounters.RxErrLinkLostCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) + { + pDevice->RxCounters.RxErrPhyDecodeCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pDevice->RxCounters.RxErrOddNibbleCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) + { + pDevice->RxCounters.RxErrMacAbortCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) + { + pDevice->RxCounters.RxErrShortPacketCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) + { + pDevice->RxCounters.RxErrNoResourceCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) + { + pDevice->RxCounters.RxErrLargePacketCnt++; + } + } + else + { + pPacket->PacketStatus = LM_STATUS_SUCCESS; + pPacket->PacketSize = pRcvBd->Len - 4; + + pPacket->Flags = pRcvBd->Flags; + if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) + { + pPacket->VlanTag = pRcvBd->VlanTag; + } + + pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; + } + + /* Put the packet descriptor containing the received packet */ + /* buffer in the RxPacketReceivedQ for indication later. */ + QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket); + + /* Go to the next buffer descriptor. */ + SwRcvRetConIdx = (SwRcvRetConIdx + 1) & + T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK; + + /* Get the updated HwRcvRetProdIdx. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + } /* while */ + + pDevice->RcvRetConIdx = SwRcvRetConIdx; + + /* Update the receive return ring consumer index. */ + MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx); +} /* LM_ServiceRxInterrupt */ + + +/******************************************************************************/ +/* Description: */ +/* This is the interrupt event handler routine. It acknowledges all */ +/* pending interrupts and process all pending events. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_ServiceInterrupts( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + int ServicePhyInt = FALSE; + + /* Setup the phy chip whenever the link status changes. */ + if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) + { + Value32 = REG_RD(pDevice, MacCtrl.Status); + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) + { + if (Value32 & MAC_STATUS_MI_INTERRUPT) + { + ServicePhyInt = TRUE; + } + } + else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED) + { + ServicePhyInt = TRUE; + } + } + else + { + if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS) + { + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | + (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); + ServicePhyInt = TRUE; + } + } +#if INCLUDE_TBI_SUPPORT + if (pDevice->IgnoreTbiLinkChange == TRUE) + { + ServicePhyInt = FALSE; + } +#endif + if (ServicePhyInt == TRUE) + { + LM_SetupPhy(pDevice); + } + + /* Service receive and transmit interrupts. */ + LM_ServiceRxInterrupt(pDevice); + LM_ServiceTxInterrupt(pDevice); + + /* No spinlock for this queue since this routine is serialized. */ + if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container)) + { + /* Indicate receive packets. */ + MM_IndicateRxPackets(pDevice); + /* LM_QueueRxPackets(pDevice); */ + } + + /* No spinlock for this queue since this routine is serialized. */ + if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container)) + { + MM_IndicateTxPackets(pDevice); + } + + return LM_STATUS_SUCCESS; +} /* LM_ServiceInterrupts */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_MulticastAdd( +PLM_DEVICE_BLOCK pDevice, +PLM_UINT8 pMcAddress) { + PLM_UINT8 pEntry; + LM_UINT32 j; + + pEntry = pDevice->McTable[0]; + for(j = 0; j < pDevice->McEntryCount; j++) + { + if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) + { + /* Found a match, increment the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1; + + return LM_STATUS_SUCCESS; + } + + pEntry += LM_MC_ENTRY_SIZE; + } + + if(pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) + { + return LM_STATUS_FAILURE; + } + + pEntry = pDevice->McTable[pDevice->McEntryCount]; + + COPY_ETH_ADDRESS(pMcAddress, pEntry); + pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1; + + pDevice->McEntryCount++; + + LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST); + + return LM_STATUS_SUCCESS; +} /* LM_MulticastAdd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_MulticastDel( +PLM_DEVICE_BLOCK pDevice, +PLM_UINT8 pMcAddress) { + PLM_UINT8 pEntry; + LM_UINT32 j; + + pEntry = pDevice->McTable[0]; + for(j = 0; j < pDevice->McEntryCount; j++) + { + if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) + { + /* Found a match, decrement the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1; + + /* No more instance left, remove the address from the table. */ + /* Move the last entry in the table to the delete slot. */ + if(pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 && + pDevice->McEntryCount > 1) + { + + COPY_ETH_ADDRESS( + pDevice->McTable[pDevice->McEntryCount-1], pEntry); + pEntry[LM_MC_INSTANCE_COUNT_INDEX] = + pDevice->McTable[pDevice->McEntryCount-1] + [LM_MC_INSTANCE_COUNT_INDEX]; + } + pDevice->McEntryCount--; + + /* Update the receive mask if the table is empty. */ + if(pDevice->McEntryCount == 0) + { + LM_SetReceiveMask(pDevice, + pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); + } + + return LM_STATUS_SUCCESS; + } + + pEntry += LM_MC_ENTRY_SIZE; + } + + return LM_STATUS_FAILURE; +} /* LM_MulticastDel */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_MulticastClear( +PLM_DEVICE_BLOCK pDevice) { + pDevice->McEntryCount = 0; + + LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); + + return LM_STATUS_SUCCESS; +} /* LM_MulticastClear */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetMacAddress( + PLM_DEVICE_BLOCK pDevice, + PLM_UINT8 pMacAddress) +{ + LM_UINT32 j; + + for(j = 0; j < 4; j++) + { + REG_WR(pDevice, MacCtrl.MacAddr[j].High, + (pMacAddress[0] << 8) | pMacAddress[1]); + REG_WR(pDevice, MacCtrl.MacAddr[j].Low, + (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | + (pMacAddress[4] << 8) | pMacAddress[5]); + } + + return LM_STATUS_SUCCESS; +} + + +/******************************************************************************/ +/* Description: */ +/* Sets up the default line speed, and duplex modes based on the requested */ +/* media type. */ +/* */ +/* Return: */ +/* None. */ +/******************************************************************************/ +static LM_STATUS +LM_TranslateRequestedMediaType( +LM_REQUESTED_MEDIA_TYPE RequestedMediaType, +PLM_MEDIA_TYPE pMediaType, +PLM_LINE_SPEED pLineSpeed, +PLM_DUPLEX_MODE pDuplexMode) { + *pMediaType = LM_MEDIA_TYPE_AUTO; + *pLineSpeed = LM_LINE_SPEED_UNKNOWN; + *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + + /* determine media type */ + switch(RequestedMediaType) { + case LM_REQUESTED_MEDIA_TYPE_BNC: + *pMediaType = LM_MEDIA_TYPE_BNC; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO: + *pMediaType = LM_MEDIA_TYPE_UTP; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + default: + break; + } /* switch */ + + return LM_STATUS_SUCCESS; +} /* LM_TranslateRequestedMediaType */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* LM_STATUS_LINK_ACTIVE */ +/* LM_STATUS_LINK_DOWN */ +/******************************************************************************/ +static LM_STATUS +LM_InitBcm540xPhy( +PLM_DEVICE_BLOCK pDevice) +{ + LM_LINE_SPEED CurrentLineSpeed; + LM_DUPLEX_MODE CurrentDuplexMode; + LM_STATUS CurrentLinkStatus; + LM_UINT32 Value32; + LM_UINT32 j; + +#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */ + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x2); +#endif + if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + if(!pDevice->InitDone) + { + Value32 = 0; + } + + if(!(Value32 & PHY_STATUS_LINK_PASS)) + { + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + for(j = 0; j < 1000; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + if(Value32 & PHY_STATUS_LINK_PASS) + { + MM_Wait(40); + break; + } + } + + if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV) + { + if(!(Value32 & PHY_STATUS_LINK_PASS) && + (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS)) + { + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + for(j = 0; j < 100; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(!(Value32 & PHY_CTRL_PHY_RESET)) + { + MM_Wait(40); + break; + } + } + + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + } + } + } + } + else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + /* Bug: 5701 A0, B0 TX CRC workaround. */ + LM_WritePhy(pDevice, 0x15, 0x0a75); + LM_WritePhy(pDevice, 0x1c, 0x8c68); + LM_WritePhy(pDevice, 0x1c, 0x8d68); + LM_WritePhy(pDevice, 0x1c, 0x8c68); + } + + /* Acknowledge interrupts. */ + LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); + + /* Configure the interrupt mask. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) + { + LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE); + } + + /* Configure PHY led mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)) + { + if(pDevice->LedMode == LED_MODE_THREE_LINK) + { + LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, + BCM540X_EXT_CTRL_LINK3_LED_MODE); + } + else + { + LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0); + } + } + + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + + /* Get current link and duplex mode. */ + for(j = 0; j < 100; j++) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + if(Value32 & PHY_STATUS_LINK_PASS) + { + break; + } + MM_Wait(40); + } + + if(Value32 & PHY_STATUS_LINK_PASS) + { + + /* Determine the current line and duplex settings. */ + LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); + for(j = 0; j < 2000; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); + if(Value32) + { + break; + } + } + + switch(Value32 & BCM540X_AUX_SPEED_MASK) + { + case BCM540X_AUX_10BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_10BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASETX_HD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASETX_FD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + default: + + CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN; + CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + break; + } + + /* Make sure we are in auto-neg mode. */ + for (j = 0; j < 200; j++) + { + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 && Value32 != 0x7fff) + { + break; + } + + if(Value32 == 0 && pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) + { + break; + } + + MM_Wait(10); + } + + /* Use the current line settings for "auto" mode. */ + if(pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) + { + if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + + /* We may be exiting low power mode and the link is in */ + /* 10mb. In this case, we need to restart autoneg. */ + LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &Value32); + pDevice->advertising1000 = Value32; + /* 5702FE supports 10/100Mb only. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703 || + pDevice->BondId != GRC_MISC_BD_ID_5702FE) + { + if(!(Value32 & (BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL))) + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + else + { + /* Force line settings. */ + /* Use the current setting if it matches the user's requested */ + /* setting. */ + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if((pDevice->LineSpeed == CurrentLineSpeed) && + (pDevice->DuplexMode == CurrentDuplexMode)) + { + if ((pDevice->DisableAutoNeg && + !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) || + (!pDevice->DisableAutoNeg && + (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + + /* Save line settings. */ + pDevice->LineSpeed = CurrentLineSpeed; + pDevice->DuplexMode = CurrentDuplexMode; + pDevice->MediaType = LM_MEDIA_TYPE_UTP; + } + + return CurrentLinkStatus; +} /* LM_InitBcm540xPhy */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetFlowControl( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, + LM_UINT32 RemotePhyAd) +{ + LM_FLOW_CONTROL FlowCap; + + /* Resolve flow control. */ + FlowCap = LM_FLOW_CONTROL_NONE; + + /* See Table 28B-3 of 802.3ab-1999 spec. */ + if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) + { + if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) + { + if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) + { + if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE) + { + FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + else + { + if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + } + else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) + { + if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) && + (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + } + } + else + { + FlowCap = pDevice->FlowControlCap; + } + + /* Enable/disable rx PAUSE. */ + pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL; + if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) + { + pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL; + + } + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + + /* Enable/disable tx PAUSE. */ + pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL; + if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) + { + pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL; + + } + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + + return LM_STATUS_SUCCESS; +} + + +#if INCLUDE_TBI_SUPPORT +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_InitBcm800xPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + Value32 = REG_RD(pDevice, MacCtrl.Status); + + /* Reset the SERDES during init and when we have link. */ + if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) + { + /* Set PLL lock range. */ + LM_WritePhy(pDevice, 0x16, 0x8007); + + /* Software reset. */ + LM_WritePhy(pDevice, 0x00, 0x8000); + + /* Wait for reset to complete. */ + for(j = 0; j < 500; j++) + { + MM_Wait(10); + } + + /* Config mode; seletct PMA/Ch 1 regs. */ + LM_WritePhy(pDevice, 0x10, 0x8411); + + /* Enable auto-lock and comdet, select txclk for tx. */ + LM_WritePhy(pDevice, 0x11, 0x0a10); + + LM_WritePhy(pDevice, 0x18, 0x00a0); + LM_WritePhy(pDevice, 0x16, 0x41ff); + + /* Assert and deassert POR. */ + LM_WritePhy(pDevice, 0x13, 0x0400); + MM_Wait(40); + LM_WritePhy(pDevice, 0x13, 0x0000); + + LM_WritePhy(pDevice, 0x11, 0x0a50); + MM_Wait(40); + LM_WritePhy(pDevice, 0x11, 0x0a10); + + /* Delay for signal to stabilize. */ + for(j = 0; j < 15000; j++) + { + MM_Wait(10); + } + + /* Deselect the channel register so we can read the PHY id later. */ + LM_WritePhy(pDevice, 0x10, 0x8011); + } + + return LM_STATUS_SUCCESS; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_SetupFiberPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_STATUS CurrentLinkStatus; + AUTONEG_STATUS AnStatus = 0; + LM_UINT32 Value32; + LM_UINT32 Cnt; + LM_UINT32 j, k; + + pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK); + + /* Initialize the send_config register. */ + REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); + + /* Enable TBI and full duplex mode. */ + pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + /* Initialize the BCM8002 SERDES PHY. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM8002_PHY_ID: + LM_InitBcm800xPhy(pDevice); + break; + + default: + break; + } + + /* Enable link change interrupt. */ + REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); + + /* Default to link down. */ + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + + /* Get the link status. */ + Value32 = REG_RD(pDevice, MacCtrl.Status); + if(Value32 & MAC_STATUS_PCS_SYNCED) + { + if((pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO) || + (pDevice->DisableAutoNeg == FALSE)) + { + /* auto-negotiation mode. */ + /* Initialize the autoneg default capaiblities. */ + AutonegInit(&pDevice->AnInfo); + + /* Set the context pointer to point to the main device structure. */ + pDevice->AnInfo.pContext = pDevice; + + /* Setup flow control advertisement register. */ + Value32 = GetPhyAdFlowCntrlSettings(pDevice); + if(Value32 & PHY_AN_AD_PAUSE_CAPABLE) + { + pDevice->AnInfo.mr_adv_sym_pause = 1; + } + else + { + pDevice->AnInfo.mr_adv_sym_pause = 0; + } + + if(Value32 & PHY_AN_AD_ASYM_PAUSE) + { + pDevice->AnInfo.mr_adv_asym_pause = 1; + } + else + { + pDevice->AnInfo.mr_adv_asym_pause = 0; + } + + /* Try to autoneg up to six times. */ + if (pDevice->IgnoreTbiLinkChange) + { + Cnt = 1; + } + else + { + Cnt = 6; + } + for (j = 0; j < Cnt; j++) + { + REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); + + Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK; + REG_WR(pDevice, MacCtrl.Mode, Value32); + MM_Wait(20); + + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + + MM_Wait(20); + + pDevice->AnInfo.State = AN_STATE_UNKNOWN; + pDevice->AnInfo.CurrentTime_us = 0; + + REG_WR(pDevice, Grc.Timer, 0); + for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) && + (k < 75000); k++) + { + AnStatus = Autoneg8023z(&pDevice->AnInfo); + + if((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + + pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer); + + } + if((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + if (j >= 1) + { + if (!(REG_RD(pDevice, MacCtrl.Status) & + MAC_STATUS_PCS_SYNCED)) { + break; + } + } + } + + /* Stop sending configs. */ + MM_AnTxIdle(&pDevice->AnInfo); + + /* Resolve flow control settings. */ + if((AnStatus == AUTONEG_STATUS_DONE) && + pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok && + pDevice->AnInfo.mr_lp_adv_full_duplex) + { + LM_UINT32 RemotePhyAd; + LM_UINT32 LocalPhyAd; + + LocalPhyAd = 0; + if(pDevice->AnInfo.mr_adv_sym_pause) + { + LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if(pDevice->AnInfo.mr_adv_asym_pause) + { + LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE; + } + + RemotePhyAd = 0; + if(pDevice->AnInfo.mr_lp_adv_sym_pause) + { + RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE; + } + + if(pDevice->AnInfo.mr_lp_adv_asym_pause) + { + RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE; + } + + LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + for (j = 0; j < 30; j++) + { + MM_Wait(20); + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait(20); + if ((REG_RD(pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) + break; + } + if (pDevice->PollTbiLink) + { + Value32 = REG_RD(pDevice, MacCtrl.Status); + if (Value32 & MAC_STATUS_RECEIVING_CFG) + { + pDevice->IgnoreTbiLinkChange = TRUE; + } + else + { + pDevice->IgnoreTbiLinkChange = FALSE; + } + } + Value32 = REG_RD(pDevice, MacCtrl.Status); + if (CurrentLinkStatus == LM_STATUS_LINK_DOWN && + (Value32 & MAC_STATUS_PCS_SYNCED) && + ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } + else + { + /* We are forcing line speed. */ + pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl(pDevice, 0, 0); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + } + } + /* Set the link polarity bit. */ + pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | + (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); + + for (j = 0; j < 100; j++) + { + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait(5); + if ((REG_RD(pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) + break; + } + + Value32 = REG_RD(pDevice, MacCtrl.Status); + if((Value32 & MAC_STATUS_PCS_SYNCED) == 0) + { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + if (pDevice->DisableAutoNeg == FALSE) + { + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + MM_Wait(1); + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + } + } + + /* Initialize the current link status. */ + if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) + { + pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS; + pDevice->DuplexMode = LM_DUPLEX_MODE_FULL; + REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_1000MBPS_LED_ON); + } + else + { + pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN; + pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN; + REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_OVERRIDE_TRAFFIC_LED); + } + + /* Indicate link status. */ + if (pDevice->LinkStatus != CurrentLinkStatus) { + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus(pDevice, CurrentLinkStatus); + } + + return LM_STATUS_SUCCESS; +} +#endif /* INCLUDE_TBI_SUPPORT */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetupCopperPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_STATUS CurrentLinkStatus; + LM_UINT32 Value32; + + /* Assume there is not link first. */ + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + + /* Disable phy link change attention. */ + REG_WR(pDevice, MacCtrl.MacEvent, 0); + + /* Clear link change attention. */ + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + + /* Disable auto-polling for the moment. */ + pDevice->MiMode = 0xc0000; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); + + /* Determine the requested line speed and duplex. */ + pDevice->OldLineSpeed = pDevice->LineSpeed; + LM_TranslateRequestedMediaType(pDevice->RequestedMediaType, + &pDevice->MediaType, &pDevice->LineSpeed, &pDevice->DuplexMode); + + /* Initialize the phy chip. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM5400_PHY_ID: + case PHY_BCM5401_PHY_ID: + case PHY_BCM5411_PHY_ID: + case PHY_BCM5701_PHY_ID: + case PHY_BCM5703_PHY_ID: + case PHY_BCM5704_PHY_ID: + CurrentLinkStatus = LM_InitBcm540xPhy(pDevice); + break; + + default: + break; + } + + if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) + { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + } + + /* Setup flow control. */ + pDevice->FlowControl = LM_FLOW_CONTROL_NONE; + if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) + { + LM_FLOW_CONTROL FlowCap; /* Flow control capability. */ + + FlowCap = LM_FLOW_CONTROL_NONE; + + if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) + { + if(pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) + { + LM_UINT32 ExpectedPhyAd; + LM_UINT32 LocalPhyAd; + LM_UINT32 RemotePhyAd; + + LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd); + pDevice->advertising = LocalPhyAd; + LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE); + + ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice); + + if(LocalPhyAd != ExpectedPhyAd) + { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + } + else + { + LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG, + &RemotePhyAd); + + LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + } + } + else + { + pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl(pDevice, 0, 0); + } + } + } + + if(CurrentLinkStatus == LM_STATUS_LINK_DOWN) + { + LM_ForceAutoNeg(pDevice, pDevice->RequestedMediaType); + + /* If we force line speed, we make get link right away. */ + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + if(Value32 & PHY_STATUS_LINK_PASS) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } + + /* GMII interface. */ + pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK; + if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) + { + if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS || + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) + { + pDevice->MacMode |= MAC_MODE_PORT_MODE_MII; + } + else + { + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; + } + } + else { + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; + } + + /* Set the MAC to operate in the appropriate duplex mode. */ + pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX; + if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) + { + pDevice->MacMode |= MAC_MODE_HALF_DUPLEX; + } + + /* Set the link polarity bit. */ + pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + if((pDevice->LedMode == LED_MODE_LINK10) || + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE && + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) + { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + } + } + else + { + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) + { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + } + + /* Set LED mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = LED_CTRL_PHY_MODE_1; + } + else + { + if(pDevice->LedMode == LED_MODE_OUTPUT) + { + Value32 = LED_CTRL_PHY_MODE_2; + } + else + { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + REG_WR(pDevice, MacCtrl.LedCtrl, Value32); + } + + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + /* Enable auto polling. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + } + + /* Enable phy link change attention. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) + { + REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT); + } + else + { + REG_WR(pDevice, MacCtrl.MacEvent, + MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); + } + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) && + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) && + (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && + (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) && + (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) || + !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) + { + MM_Wait(120); + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX, + T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE); + } + + /* Indicate link status. */ + if (pDevice->LinkStatus != CurrentLinkStatus) { + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus(pDevice, CurrentLinkStatus); + } + + return LM_STATUS_SUCCESS; +} /* LM_SetupCopperPhy */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetupPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_STATUS LmStatus; + LM_UINT32 Value32; + +#if INCLUDE_TBI_SUPPORT + if(pDevice->EnableTbi) + { + LmStatus = LM_SetupFiberPhy(pDevice); + } + else +#endif /* INCLUDE_TBI_SUPPORT */ + { + LmStatus = LM_SetupCopperPhy(pDevice); + } + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 = REG_RD(pDevice, PciCfg.PciState); + REG_WR(pDevice, PciCfg.PciState, + Value32 | T3_PCI_STATE_RETRY_SAME_DMA); + } + } + if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && + (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) + { + REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff); + } + else + { + REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); + } + + return LmStatus; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_ReadPhy( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 PhyReg, +PLM_UINT32 pData32) { + LM_UINT32 Value32; + LM_UINT32 j; + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait(40); + } + + Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | + MI_COM_CMD_READ | MI_COM_START; + + REG_WR(pDevice, MacCtrl.MiCom, Value32); + + for(j = 0; j < 20; j++) + { + MM_Wait(25); + + Value32 = REG_RD(pDevice, MacCtrl.MiCom); + + if(!(Value32 & MI_COM_BUSY)) + { + MM_Wait(5); + Value32 = REG_RD(pDevice, MacCtrl.MiCom); + Value32 &= MI_COM_PHY_DATA_MASK; + break; + } + } + + if(Value32 & MI_COM_BUSY) + { + Value32 = 0; + } + + *pData32 = Value32; + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); + } +} /* LM_ReadPhy */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_WritePhy( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 PhyReg, +LM_UINT32 Data32) { + LM_UINT32 Value32; + LM_UINT32 j; + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait(40); + } + + Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | + (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START; + + REG_WR(pDevice, MacCtrl.MiCom, Value32); + + for(j = 0; j < 20; j++) + { + MM_Wait(25); + + Value32 = REG_RD(pDevice, MacCtrl.MiCom); + + if(!(Value32 & MI_COM_BUSY)) + { + MM_Wait(5); + break; + } + } + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); + } +} /* LM_WritePhy */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetPowerState( +PLM_DEVICE_BLOCK pDevice, +LM_POWER_STATE PowerLevel) { + LM_UINT32 PmeSupport; + LM_UINT32 Value32; + LM_UINT32 PmCtrl; + + /* make sureindirect accesses are enabled*/ + MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); + + /* Clear the PME_ASSERT bit and the power state bits. Also enable */ + /* the PME bit. */ + MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl); + + PmCtrl |= T3_PM_PME_ASSERTED; + PmCtrl &= ~T3_PM_POWER_STATE_MASK; + + /* Set the appropriate power state. */ + if(PowerLevel == LM_POWER_STATE_D0) + { + + /* Bring the card out of low power mode. */ + PmCtrl |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); + + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait (40); +#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */ + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02); +#endif + + return LM_STATUS_SUCCESS; + } + else if(PowerLevel == LM_POWER_STATE_D1) + { + PmCtrl |= T3_PM_POWER_STATE_D1; + } + else if(PowerLevel == LM_POWER_STATE_D2) + { + PmCtrl |= T3_PM_POWER_STATE_D2; + } + else if(PowerLevel == LM_POWER_STATE_D3) + { + PmCtrl |= T3_PM_POWER_STATE_D3; + } + else + { + return LM_STATUS_FAILURE; + } + PmCtrl |= T3_PM_PME_ENABLE; + + /* Mask out all interrupts so LM_SetupPhy won't be called while we are */ + /* setting new line speed. */ + Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl); + REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT); + + if(!pDevice->RestoreOnWakeUp) + { + pDevice->RestoreOnWakeUp = TRUE; + pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg; + pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType; + } + + /* Force auto-negotiation to 10 line speed. */ + pDevice->DisableAutoNeg = FALSE; + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; + LM_SetupPhy(pDevice); + + /* Put the driver in the initial state, and go through the power down */ + /* sequence. */ + LM_Halt(pDevice); + + MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport); + + if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) + { + + /* Enable WOL. */ + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a); + MM_Wait(40); + + /* Set LED mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = LED_CTRL_PHY_MODE_1; + } + else + { + if(pDevice->LedMode == LED_MODE_OUTPUT) + { + Value32 = LED_CTRL_PHY_MODE_2; + } + else + { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + + Value32 = MAC_MODE_PORT_MODE_MII; + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + if(pDevice->LedMode == LED_MODE_LINK10 || + pDevice->WolSpeed == WOL_SPEED_10MB) + { + Value32 |= MAC_MODE_LINK_POLARITY; + } + } + else + { + Value32 |= MAC_MODE_LINK_POLARITY; + } + REG_WR(pDevice, MacCtrl.Mode, Value32); + MM_Wait(40); MM_Wait(40); MM_Wait(40); + + /* Always enable magic packet wake-up if we have vaux. */ + if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) && + (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) + { + Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE; + } + + REG_WR(pDevice, MacCtrl.Mode, Value32); + + /* Enable the receiver. */ + REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE); + } + + /* Disable tx/rx clocks, and seletect an alternate clock. */ + if(pDevice->WolSpeed == WOL_SPEED_100MB) + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK; + } + else + { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK; + } + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + + MM_Wait(40); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK; + } + else + { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + + MM_Wait(40); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } + else + { + Value32 = T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + } + else + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } + else + { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } + + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + } + + MM_Wait(40); + + if(!pDevice->EepromWp && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) + { + /* Switch adapter to auxilliary power. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait(40); + } + else + { + /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait(40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait(40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait(40); + } + } + + /* Set the phy to low power mode. */ + /* Put the the hardware in low power mode. */ + MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); + + return LM_STATUS_SUCCESS; +} /* LM_SetPowerState */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +static LM_UINT32 +GetPhyAdFlowCntrlSettings( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + + Value32 = 0; + + /* Auto negotiation flow control only when autonegotiation is enabled. */ + if(pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) + { + /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */ + if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) || + ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) && + (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) + { + Value32 |= PHY_AN_AD_PAUSE_CAPABLE; + } + else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + Value32 |= PHY_AN_AD_ASYM_PAUSE; + } + else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) + { + Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; + } + } + + return Value32; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* LM_STATUS_FAILURE */ +/* LM_STATUS_SUCCESS */ +/* */ +/******************************************************************************/ +static LM_STATUS +LM_ForceAutoNegBcm540xPhy( +PLM_DEVICE_BLOCK pDevice, +LM_REQUESTED_MEDIA_TYPE RequestedMediaType) +{ + LM_MEDIA_TYPE MediaType; + LM_LINE_SPEED LineSpeed; + LM_DUPLEX_MODE DuplexMode; + LM_UINT32 NewPhyCtrl; + LM_UINT32 Value32; + LM_UINT32 Cnt; + + /* Get the interface type, line speed, and duplex mode. */ + LM_TranslateRequestedMediaType(RequestedMediaType, &MediaType, &LineSpeed, + &DuplexMode); + + if (pDevice->RestoreOnWakeUp) + { + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF; + if (pDevice->WolSpeed == WOL_SPEED_100MB) + { + Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + } + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } + /* Setup the auto-negotiation advertisement register. */ + else if(LineSpeed == LM_LINE_SPEED_UNKNOWN) + { + /* Setup the 10/100 Mbps auto-negotiation advertisement register. */ + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + /* Advertise 1000Mbps */ + Value32 = BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL; + +#if INCLUDE_5701_AX_FIX + /* Bug: workaround for CRC error in gigabit mode when we are in */ + /* slave mode. This will force the PHY to operate in */ + /* master mode. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + Value32 |= BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + } +#endif + + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + } + else + { + if(LineSpeed == LM_LINE_SPEED_1000MBPS) + { + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + if(DuplexMode != LM_DUPLEX_MODE_FULL) + { + Value32 = BCM540X_AN_AD_1000BASET_HALF; + } + else + { + Value32 = BCM540X_AN_AD_1000BASET_FULL; + } + + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + } + else if(LineSpeed == LM_LINE_SPEED_100MBPS) + { + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + + if(DuplexMode != LM_DUPLEX_MODE_FULL) + { + Value32 = PHY_AN_AD_100BASETX_HALF; + } + else + { + Value32 = PHY_AN_AD_100BASETX_FULL; + } + + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } + else if(LineSpeed == LM_LINE_SPEED_10MBPS) + { + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + + if(DuplexMode != LM_DUPLEX_MODE_FULL) + { + Value32 = PHY_AN_AD_10BASET_HALF; + } + else + { + Value32 = PHY_AN_AD_10BASET_FULL; + } + + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } + } + + /* Force line speed if auto-negotiation is disabled. */ + if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) + { + /* This code path is executed only when there is link. */ + pDevice->MediaType = MediaType; + pDevice->LineSpeed = LineSpeed; + pDevice->DuplexMode = DuplexMode; + + /* Force line seepd. */ + NewPhyCtrl = 0; + switch(LineSpeed) + { + case LM_LINE_SPEED_10MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS; + break; + case LM_LINE_SPEED_100MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS; + break; + case LM_LINE_SPEED_1000MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + default: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + } + + if(DuplexMode == LM_DUPLEX_MODE_FULL) + { + NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE; + } + + /* Don't do anything if the PHY_CTRL is already what we wanted. */ + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 != NewPhyCtrl) + { + /* Temporary bring the link down before forcing line speed. */ + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE); + + /* Wait for link to go down. */ + for(Cnt = 0; Cnt < 15000; Cnt++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + if(!(Value32 & PHY_STATUS_LINK_PASS)) + { + MM_Wait(40); + break; + } + } + + LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl); + MM_Wait(40); + } + } + else + { + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } + + return LM_STATUS_SUCCESS; +} /* LM_ForceAutoNegBcm540xPhy */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +static LM_STATUS +LM_ForceAutoNeg( +PLM_DEVICE_BLOCK pDevice, +LM_REQUESTED_MEDIA_TYPE RequestedMediaType) +{ + LM_STATUS LmStatus; + + /* Initialize the phy chip. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM5400_PHY_ID: + case PHY_BCM5401_PHY_ID: + case PHY_BCM5411_PHY_ID: + case PHY_BCM5701_PHY_ID: + case PHY_BCM5703_PHY_ID: + case PHY_BCM5704_PHY_ID: + LmStatus = LM_ForceAutoNegBcm540xPhy(pDevice, RequestedMediaType); + break; + + default: + LmStatus = LM_STATUS_FAILURE; + break; + } + + return LmStatus; +} /* LM_ForceAutoNeg */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice, + PT3_FWIMG_INFO pFwImg, + LM_UINT32 LoadCpu, + LM_UINT32 StartCpu) +{ + LM_UINT32 i; + LM_UINT32 address; + + if (LoadCpu & T3_RX_CPU_ID) + { + if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i+=4) + { + LM_RegWrInd(pDevice,T3_RX_CPU_SPAD_ADDR+i,0); + } + + /* Copy code first */ + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i = 0; i <= pFwImg->Text.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); + } + + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); + } + + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i= 0; i <= pFwImg->Data.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); + } + } + + if (LoadCpu & T3_TX_CPU_ID) + { + if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4) + { + LM_RegWrInd(pDevice,T3_TX_CPU_SPAD_ADDR+i,0); + } + + /* Copy code first */ + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i= 0; i <= pFwImg->Text.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); + } + + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); + } + + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i= 0; i <= pFwImg->Data.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); + } + } + + if (StartCpu & T3_RX_CPU_ID) + { + /* Start Rx CPU */ + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); + for (i = 0 ; i < 5; i++) + { + if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC)) + break; + + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); + MM_Wait(1000); + } + + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode, 0); + } + + if (StartCpu & T3_TX_CPU_ID) + { + /* Start Tx CPU */ + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); + for (i = 0 ; i < 5; i++) + { + if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC)) + break; + + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); + REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); + MM_Wait(1000); + } + + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.mode, 0); + } + + return LM_STATUS_SUCCESS; +} + +STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number) +{ + LM_UINT32 i; + + if (cpu_number == T3_RX_CPU_ID) + { + for (i = 0 ; i < 10000; i++) + { + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + + if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT) + break; + } + + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + MM_Wait(10); + } + else + { + for (i = 0 ; i < 10000; i++) + { + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); + + if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT) + break; + } + } + + return (( i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS); +} + + +int +LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) +{ + LM_UINT32 Oldcfg; + int j; + int ret = 0; + + if(BlinkDurationSec == 0) + { + return 0; + } + if(BlinkDurationSec > 120) + { + BlinkDurationSec = 120; + } + + Oldcfg = REG_RD(pDevice, MacCtrl.LedCtrl); + for(j = 0; j < BlinkDurationSec * 2; j++) + { + if(j % 2) + { + /* Turn on the LEDs. */ + REG_WR(pDevice, MacCtrl.LedCtrl, + LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_1000MBPS_LED_ON | + LED_CTRL_100MBPS_LED_ON | + LED_CTRL_10MBPS_LED_ON | + LED_CTRL_OVERRIDE_TRAFFIC_LED | + LED_CTRL_BLINK_TRAFFIC_LED | + LED_CTRL_TRAFFIC_LED); + } + else + { + /* Turn off the LEDs. */ + REG_WR(pDevice, MacCtrl.LedCtrl, + LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_OVERRIDE_TRAFFIC_LED); + } + +#ifndef EMBEDDED + current->state = TASK_INTERRUPTIBLE; + if (schedule_timeout(HZ/2) != 0) { + ret = -EINTR; + break; + } +#else + udelay(100000); /* 1s sleep */ +#endif + } + REG_WR(pDevice, MacCtrl.LedCtrl, Oldcfg); + return ret; +} + +int t3_do_dma(PLM_DEVICE_BLOCK pDevice, + LM_PHYSICAL_ADDRESS host_addr_phy, int length, + int dma_read) +{ + T3_DMA_DESC dma_desc; + int i; + LM_UINT32 dma_desc_addr; + LM_UINT32 value32; + + REG_WR(pDevice, BufMgr.Mode, 0); + REG_WR(pDevice, Ftq.Reset, 0); + + dma_desc.host_addr.High = host_addr_phy.High; + dma_desc.host_addr.Low = host_addr_phy.Low; + dma_desc.nic_mbuf = 0x2100; + dma_desc.len = length; + dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */ + + if (dma_read) + { + dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) | + T3_QID_DMA_HIGH_PRI_READ; + REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE); + } + else + { + dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) | + T3_QID_DMA_HIGH_PRI_WRITE; + REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE); + } + + dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR; + + /* Writing this DMA descriptor to DMA memory */ + for (i = 0; i < sizeof(T3_DMA_DESC); i += 4) + { + value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i)); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, cpu_to_le32(value32)); + } + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0); + + if (dma_read) + REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr); + else + REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr); + + for (i = 0; i < 40; i++) + { + if (dma_read) + value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue); + else + value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue); + + if ((value32 & 0xffff) == dma_desc_addr) + break; + + MM_Wait(10); + } + + return LM_STATUS_SUCCESS; +} + +STATIC LM_STATUS +LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, + LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize) +{ + int j; + LM_UINT32 *ptr; + int dma_success = 0; + + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + { + return LM_STATUS_SUCCESS; + } + while (!dma_success) + { + /* Fill data with incremental patterns */ + ptr = (LM_UINT32 *)pBufferVirt; + for (j = 0; j < BufferSize/4; j++) + *ptr++ = j; + + if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE) + { + return LM_STATUS_FAILURE; + } + + MM_Wait(40); + ptr = (LM_UINT32 *)pBufferVirt; + /* Fill data with zero */ + for (j = 0; j < BufferSize/4; j++) + *ptr++ = 0; + + if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE) + { + return LM_STATUS_FAILURE; + } + + MM_Wait(40); + /* Check for data */ + ptr = (LM_UINT32 *)pBufferVirt; + for (j = 0; j < BufferSize/4; j++) + { + if (*ptr++ != j) + { + if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK) + == DMA_CTRL_WRITE_BOUNDARY_DISABLE) + { + pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl & + ~DMA_CTRL_WRITE_BOUNDARY_MASK) | + DMA_CTRL_WRITE_BOUNDARY_16; + REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, + pDevice->DmaReadWriteCtrl); + break; + } + else + { + return LM_STATUS_FAILURE; + } + } + } + if (j == (BufferSize/4)) + dma_success = 1; + } + return LM_STATUS_SUCCESS; +} +#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */ diff --git a/drivers/tigon3.h b/drivers/tigon3.h new file mode 100644 index 0000000..ea4367d --- /dev/null +++ b/drivers/tigon3.h @@ -0,0 +1,3430 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* */ +/******************************************************************************/ + +#ifndef TIGON3_H +#define TIGON3_H + +#include "bcm570x_lm.h" +#if INCLUDE_TBI_SUPPORT +#include "bcm570x_autoneg.h" +#endif + + +/* io defines */ +#if !defined(BIG_ENDIAN_HOST) +#define readl(addr) \ + (LONGSWAP((*(volatile unsigned int *)(addr)))) +#define writel(b,addr) \ + ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b))) +#else +#if 0 /* !defined(PPC603) */ +#define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr))) +#define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b)) +#else +#if 1 +#define readl(addr) (*(volatile unsigned int*)(addr)) +#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) +#else +extern int sprintf(char* buf, const char* f, ...); +static __inline unsigned int readl(void* addr){ + char buf[128]; + unsigned int tmp = (*(volatile unsigned int*)(addr)); + sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0); + sysSerialPrintString(buf); + return tmp; +} +static __inline void writel(unsigned int b, unsigned int addr){ + char buf[128]; + ((*(volatile unsigned int *) (addr)) = (b)); + sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0); + sysSerialPrintString(buf); +} +#endif +#endif /* PPC603 */ +#endif + + +/******************************************************************************/ +/* Constants. */ +/******************************************************************************/ + +/* Maxim number of packet descriptors used for sending packets. */ +#define MAX_TX_PACKET_DESC_COUNT 600 +#define DEFAULT_TX_PACKET_DESC_COUNT 2 + +/* Maximum number of packet descriptors used for receiving packets. */ +#if T3_JUMBO_RCB_ENTRY_COUNT +#define MAX_RX_PACKET_DESC_COUNT \ + (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT) +#else +#define MAX_RX_PACKET_DESC_COUNT 800 +#endif +#define DEFAULT_RX_PACKET_DESC_COUNT 2 + +/* Threshhold for double copying small tx packets. 0 will disable double */ +/* copying of small Tx packets. */ +#define DEFAULT_TX_COPY_BUFFER_SIZE 0 +#define MIN_TX_COPY_BUFFER_SIZE 64 +#define MAX_TX_COPY_BUFFER_SIZE 512 + +/* Cache line. */ +#define COMMON_CACHE_LINE_SIZE 0x20 +#define COMMON_CACHE_LINE_MASK (COMMON_CACHE_LINE_SIZE-1) + +/* Maximum number of fragment we can handle. */ +#ifndef MAX_FRAGMENT_COUNT +#define MAX_FRAGMENT_COUNT 32 +#endif + +/* B0 bug. */ +#define BCM5700_BX_MIN_FRAG_SIZE 10 +#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ +#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1) +#define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \ + MAX_FRAGMENT_COUNT) + +/* MAGIC number. */ +/* #define T3_MAGIC_NUM 'KevT' */ +#define T3_FIRMWARE_MAILBOX 0x0b50 +#define T3_MAGIC_NUM 0x4B657654 +#define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b + +#define T3_NIC_DATA_SIG_ADDR 0x0b54 +#define T3_NIC_DATA_SIG 0x4b657654 + +#define T3_NIC_DATA_NIC_CFG_ADDR 0x0b58 +#define T3_NIC_CFG_LED_MODE_UNKNOWN BIT_NONE +#define T3_NIC_CFG_LED_MODE_TRIPLE_SPEED BIT_2 +#define T3_NIC_CFG_LED_MODE_LINK_SPEED BIT_3 +#define T3_NIC_CFG_LED_MODE_OPEN_DRAIN BIT_2 +#define T3_NIC_CFG_LED_MODE_OUTPUT BIT_3 +#define T3_NIC_CFG_LED_MODE_MASK (BIT_2 | BIT_3) +#define T3_NIC_CFG_PHY_TYPE_UNKNOWN BIT_NONE +#define T3_NIC_CFG_PHY_TYPE_COPPER BIT_4 +#define T3_NIC_CFG_PHY_TYPE_FIBER BIT_5 +#define T3_NIC_CFG_PHY_TYPE_MASK (BIT_4 | BIT_5) +#define T3_NIC_CFG_ENABLE_WOL BIT_6 +#define T3_NIC_CFG_ENABLE_ASF BIT_7 +#define T3_NIC_EEPROM_WP BIT_8 + +#define T3_NIC_DATA_PHY_ID_ADDR 0x0b74 +#define T3_NIC_PHY_ID1_MASK 0xffff0000 +#define T3_NIC_PHY_ID2_MASK 0x0000ffff + +#define T3_CMD_MAILBOX 0x0b78 +#define T3_CMD_NICDRV_ALIVE 0x01 +#define T3_CMD_NICDRV_PAUSE_FW 0x02 +#define T3_CMD_NICDRV_IPV4ADDR_CHANGE 0x03 +#define T3_CMD_NICDRV_IPV6ADDR_CHANGE 0x04 +#define T3_CMD_5703A0_FIX_DMAFW_DMAR 0x05 +#define T3_CMD_5703A0_FIX_DMAFW_DMAW 0x06 + +#define T3_CMD_LENGTH_MAILBOX 0x0b7c +#define T3_CMD_DATA_MAILBOX 0x0b80 + +#define T3_ASF_FW_STATUS_MAILBOX 0x0c00 + +#define T3_DRV_STATE_MAILBOX 0x0c04 +#define T3_DRV_STATE_START 0x01 +#define T3_DRV_STATE_UNLOAD 0x02 +#define T3_DRV_STATE_WOL 0x03 +#define T3_DRV_STATE_SUSPEND 0x04 + +#define T3_FW_RESET_TYPE_MAILBOX 0x0c08 + +#define T3_MAC_ADDR_HIGH_MAILBOX 0x0c14 +#define T3_MAC_ADDR_LOW_MAILBOX 0x0c18 + +/******************************************************************************/ +/* Hardware constants. */ +/******************************************************************************/ + +/* Number of entries in the send ring: must be 512. */ +#define T3_SEND_RCB_ENTRY_COUNT 512 +#define T3_SEND_RCB_ENTRY_COUNT_MASK (T3_SEND_RCB_ENTRY_COUNT-1) + +/* Number of send RCBs. May be 1-16 but for now, only support one. */ +#define T3_MAX_SEND_RCB_COUNT 16 + +/* Number of entries in the Standard Receive RCB. Must be 512 entries. */ +#define T3_STD_RCV_RCB_ENTRY_COUNT 512 +#define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1) +#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ +#define MAX_STD_RCV_BUFFER_SIZE 0x600 + +/* Number of entries in the Mini Receive RCB. This value can either be */ +/* 0, 1024. Currently Mini Receive RCB is disabled. */ +#ifndef T3_MINI_RCV_RCB_ENTRY_COUNT +#define T3_MINI_RCV_RCB_ENTRY_COUNT 0 +#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ +#define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1) +#define MAX_MINI_RCV_BUFFER_SIZE 512 +#define DEFAULT_MINI_RCV_BUFFER_SIZE 64 +#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ + +/* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */ +/* Currently, Jumbo Receive RCB is disabled. */ +#ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT +#define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0 +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ +#define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1) + +#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ + +#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ + +/* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */ +#define T3_MAX_RCV_RETURN_RCB_COUNT 16 + +/* Number of entries in a Receive Return ring. This value is either 1024 */ +/* or 2048. */ +#ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT +#define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024 +#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ +#define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1) + + +/* Default coalescing parameters. */ +#define DEFAULT_RX_COALESCING_TICKS 100 +#define MAX_RX_COALESCING_TICKS 500 +#define DEFAULT_TX_COALESCING_TICKS 400 +#define MAX_TX_COALESCING_TICKS 500 +#define DEFAULT_RX_MAX_COALESCED_FRAMES 10 +#define MAX_RX_MAX_COALESCED_FRAMES 100 +#define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES 5 +#define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES 42 +#define ADAPTIVE_LO_RX_COALESCING_TICKS 50 +#define ADAPTIVE_HI_RX_COALESCING_TICKS 300 +#define ADAPTIVE_LO_PKT_THRESH 30000 +#define ADAPTIVE_HI_PKT_THRESH 74000 +#define DEFAULT_TX_MAX_COALESCED_FRAMES 40 +#define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES 25 +#define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES 75 +#define MAX_TX_MAX_COALESCED_FRAMES 100 + +#define DEFAULT_RX_COALESCING_TICKS_DURING_INT 25 +#define DEFAULT_TX_COALESCING_TICKS_DURING_INT 25 +#define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 5 +#define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT 5 + +#define BAD_DEFAULT_VALUE 0xffffffff + +#define DEFAULT_STATS_COALESCING_TICKS 1000000 +#define MAX_STATS_COALESCING_TICKS 3600000000U + + +/* Receive BD Replenish thresholds. */ +#define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4 +#define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4 + +#define SPLIT_MODE_DISABLE 0 +#define SPLIT_MODE_ENABLE 1 + +#define SPLIT_MODE_5704_MAX_REQ 3 + +/* Maximum physical fragment size. */ +#define MAX_FRAGMENT_SIZE (64 * 1024) + + +/* Standard view. */ +#define T3_STD_VIEW_SIZE (64 * 1024) +#define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024) + + +/* Buffer descriptor base address on the NIC's memory. */ + +#define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000 +#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR 0x6000 +#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR 0x7000 + +#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xc000 +#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xd000 +#define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000 + +#define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \ + sizeof(T3_SND_BD) / 4) + +#define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \ + sizeof(T3_RCV_BD) / 4) + +#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \ + sizeof(T3_EXT_RCV_BD) / 4) + + +/* MBUF pool. */ +#define T3_NIC_MBUF_POOL_ADDR 0x8000 +/* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */ +#define T3_NIC_MBUF_POOL_SIZE96 0x18000 +#define T3_NIC_MBUF_POOL_SIZE64 0x10000 + + +#define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000 + +/* DMA descriptor pool */ +#define T3_NIC_DMA_DESC_POOL_ADDR 0x2000 +#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ + +#define T3_DEF_DMA_MBUF_LOW_WMARK 0x40 +#define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20 +#define T3_DEF_MBUF_HIGH_WMARK 0x60 + +#define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO 304 +#define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO 152 +#define T3_DEF_MBUF_HIGH_WMARK_JUMBO 380 + +#define T3_DEF_DMA_DESC_LOW_WMARK 5 +#define T3_DEF_DMA_DESC_HIGH_WMARK 10 + +/* Maximum size of giant TCP packet can be sent */ +#define T3_TCP_SEG_MAX_OFFLOAD_SIZE 64*1000 +#define T3_TCP_SEG_MIN_NUM_SEG 20 + +#define T3_RX_CPU_ID 0x1 +#define T3_TX_CPU_ID 0x2 +#define T3_RX_CPU_SPAD_ADDR 0x30000 +#define T3_RX_CPU_SPAD_SIZE 0x4000 +#define T3_TX_CPU_SPAD_ADDR 0x34000 +#define T3_TX_CPU_SPAD_SIZE 0x4000 + +typedef struct T3_DIR_ENTRY +{ + PLM_UINT8 Buffer; + LM_UINT32 Offset; + LM_UINT32 Length; +} T3_DIR_ENTRY,*PT3_DIR_ENTRY; + +typedef struct T3_FWIMG_INFO +{ + LM_UINT32 StartAddress; + T3_DIR_ENTRY Text; + T3_DIR_ENTRY ROnlyData; + T3_DIR_ENTRY Data; + T3_DIR_ENTRY Sbss; + T3_DIR_ENTRY Bss; +} T3_FWIMG_INFO, *PT3_FWIMG_INFO; + + +/******************************************************************************/ +/* Tigon3 PCI Registers. */ +/******************************************************************************/ +#define T3_PCI_ID_BCM5700 0x164414e4 +#define T3_PCI_ID_BCM5701 0x164514e4 +#define T3_PCI_ID_BCM5702 0x164614e4 +#define T3_PCI_ID_BCM5702x 0x16A614e4 +#define T3_PCI_ID_BCM5703 0x164714e4 +#define T3_PCI_ID_BCM5703x 0x16A714e4 +#define T3_PCI_ID_BCM5702FE 0x164D14e4 +#define T3_PCI_ID_BCM5704 0x164814e4 + +#define T3_PCI_VENDOR_ID (T3_PCI_ID & 0xffff) +#define T3_PCI_DEVICE_ID (T3_PCI_ID >> 16) + +#define T3_PCI_MISC_HOST_CTRL_REG 0x68 + +/* The most significant 16bit of register 0x68. */ +/* ChipId:4, ChipRev:4, MetalRev:8 */ +#define T3_CHIP_ID_5700_A0 0x7000 +#define T3_CHIP_ID_5700_A1 0x7001 +#define T3_CHIP_ID_5700_B0 0x7100 +#define T3_CHIP_ID_5700_B1 0x7101 +#define T3_CHIP_ID_5700_C0 0x7200 + +#define T3_CHIP_ID_5701_A0 0x0000 +#define T3_CHIP_ID_5701_B0 0x0100 +#define T3_CHIP_ID_5701_B2 0x0102 +#define T3_CHIP_ID_5701_B5 0x0105 + +#define T3_CHIP_ID_5703_A0 0x1000 +#define T3_CHIP_ID_5703_A1 0x1001 +#define T3_CHIP_ID_5703_A2 0x1002 + +#define T3_CHIP_ID_5704_A0 0x2000 + +/* Chip Id. */ +#define T3_ASIC_REV(_ChipRevId) ((_ChipRevId) >> 12) +#define T3_ASIC_REV_5700 0x07 +#define T3_ASIC_REV_5701 0x00 +#define T3_ASIC_REV_5703 0x01 +#define T3_ASIC_REV_5704 0x02 + + +/* Chip id and revision. */ +#define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8) +#define T3_CHIP_REV_5700_AX 0x70 +#define T3_CHIP_REV_5700_BX 0x71 +#define T3_CHIP_REV_5700_CX 0x72 +#define T3_CHIP_REV_5701_AX 0x00 + +/* Metal revision. */ +#define T3_METAL_REV(_ChipRevId) ((_ChipRevId) & 0xff) +#define T3_METAL_REV_A0 0x00 +#define T3_METAL_REV_A1 0x01 +#define T3_METAL_REV_B0 0x00 +#define T3_METAL_REV_B1 0x01 +#define T3_METAL_REV_B2 0x02 + +#define T3_PCI_REG_CLOCK_CTRL 0x74 + +#define T3_PCI_DISABLE_RX_CLOCK BIT_10 +#define T3_PCI_DISABLE_TX_CLOCK BIT_11 +#define T3_PCI_SELECT_ALTERNATE_CLOCK BIT_12 +#define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15 +#define T3_PCI_44MHZ_CORE_CLOCK BIT_18 + + +#define T3_PCI_REG_ADDR_REG 0x78 +#define T3_PCI_REG_DATA_REG 0x80 + +#define T3_PCI_MEM_WIN_ADDR_REG 0x7c +#define T3_PCI_MEM_WIN_DATA_REG 0x84 + +#define T3_PCI_PM_CAP_REG 0x48 + +#define T3_PCI_PM_CAP_PME_D3COLD BIT_31 +#define T3_PCI_PM_CAP_PME_D3HOT BIT_30 + +#define T3_PCI_PM_STATUS_CTRL_REG 0x4c + +#define T3_PM_POWER_STATE_MASK (BIT_0 | BIT_1) +#define T3_PM_POWER_STATE_D0 BIT_NONE +#define T3_PM_POWER_STATE_D1 BIT_0 +#define T3_PM_POWER_STATE_D2 BIT_1 +#define T3_PM_POWER_STATE_D3 (BIT_0 | BIT_1) + +#define T3_PM_PME_ENABLE BIT_8 +#define T3_PM_PME_ASSERTED BIT_15 + + +/* PCI state register. */ +#define T3_PCI_STATE_REG 0x70 + +#define T3_PCI_STATE_FORCE_RESET BIT_0 +#define T3_PCI_STATE_INT_NOT_ACTIVE BIT_1 +#define T3_PCI_STATE_CONVENTIONAL_PCI_MODE BIT_2 +#define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3 +#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 + + +/* Broadcom subsystem/subvendor IDs. */ +#define T3_SVID_BROADCOM 0x14e4 + +#define T3_SSID_BROADCOM_BCM95700A6 0x1644 +#define T3_SSID_BROADCOM_BCM95701A5 0x0001 +#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ +#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ +#define T3_SSID_BROADCOM_BCM95701T1 0x0005 +#define T3_SSID_BROADCOM_BCM95701T8 0x0006 +#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ +#define T3_SSID_BROADCOM_BCM95701A10 0x0008 +#define T3_SSID_BROADCOM_BCM95701A12 0x8008 +#define T3_SSID_BROADCOM_BCM95703Ax1 0x0009 +#define T3_SSID_BROADCOM_BCM95703Ax2 0x8009 + +/* 3COM subsystem/subvendor IDs. */ +#define T3_SVID_3COM 0x10b7 + +#define T3_SSID_3COM_3C996T 0x1000 +#define T3_SSID_3COM_3C996BT 0x1006 +#define T3_SSID_3COM_3C996CT 0x1002 +#define T3_SSID_3COM_3C997T 0x1003 +#define T3_SSID_3COM_3C1000T 0x1007 +#define T3_SSID_3COM_3C940BR01 0x1008 + +/* Fiber boards. */ +#define T3_SSID_3COM_3C996SX 0x1004 +#define T3_SSID_3COM_3C997SX 0x1005 + + +/* Dell subsystem/subvendor IDs. */ + +#define T3_SVID_DELL 0x1028 + +#define T3_SSID_DELL_VIPER 0x00d1 +#define T3_SSID_DELL_JAGUAR 0x0106 +#define T3_SSID_DELL_MERLOT 0x0109 +#define T3_SSID_DELL_SLIM_MERLOT 0x010a + +/* Compaq subsystem/subvendor IDs */ + +#define T3_SVID_COMPAQ 0x0e11 + +#define T3_SSID_COMPAQ_BANSHEE 0x007c +#define T3_SSID_COMPAQ_BANSHEE_2 0x009a +#define T3_SSID_COMPAQ_CHANGELING 0x007d +#define T3_SSID_COMPAQ_NC7780 0x0085 +#define T3_SSID_COMPAQ_NC7780_2 0x0099 + + +/******************************************************************************/ +/* MII registers. */ +/******************************************************************************/ + +/* Control register. */ +#define PHY_CTRL_REG 0x00 + +#define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13) +#define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE +#define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13 +#define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6 +#define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7 +#define PHY_CTRL_FULL_DUPLEX_MODE BIT_8 +#define PHY_CTRL_RESTART_AUTO_NEG BIT_9 +#define PHY_CTRL_ISOLATE_PHY BIT_10 +#define PHY_CTRL_LOWER_POWER_MODE BIT_11 +#define PHY_CTRL_AUTO_NEG_ENABLE BIT_12 +#define PHY_CTRL_LOOPBACK_MODE BIT_14 +#define PHY_CTRL_PHY_RESET BIT_15 + + +/* Status register. */ +#define PHY_STATUS_REG 0x01 + +#define PHY_STATUS_LINK_PASS BIT_2 +#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 + + +/* Phy Id registers. */ +#define PHY_ID1_REG 0x02 +#define PHY_ID1_OUI_MASK 0xffff + +#define PHY_ID2_REG 0x03 +#define PHY_ID2_REV_MASK 0x000f +#define PHY_ID2_MODEL_MASK 0x03f0 +#define PHY_ID2_OUI_MASK 0xfc00 + + +/* Auto-negotiation advertisement register. */ +#define PHY_AN_AD_REG 0x04 + +#define PHY_AN_AD_ASYM_PAUSE BIT_11 +#define PHY_AN_AD_PAUSE_CAPABLE BIT_10 +#define PHY_AN_AD_10BASET_HALF BIT_5 +#define PHY_AN_AD_10BASET_FULL BIT_6 +#define PHY_AN_AD_100BASETX_HALF BIT_7 +#define PHY_AN_AD_100BASETX_FULL BIT_8 +#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 + + +/* Auto-negotiation Link Partner Ability register. */ +#define PHY_LINK_PARTNER_ABILITY_REG 0x05 + +#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 +#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 + + +/* Auto-negotiation expansion register. */ +#define PHY_AN_EXPANSION_REG 0x06 + + +/******************************************************************************/ +/* BCM5400 and BCM5401 phy info. */ +/******************************************************************************/ + +#define PHY_DEVICE_ID 1 + +/* OUI: bit 31-10; Model#: bit 9-4; Rev# bit 3-0. */ +#define PHY_UNKNOWN_PHY 0x00000000 +#define PHY_BCM5400_PHY_ID 0x60008040 +#define PHY_BCM5401_PHY_ID 0x60008050 +#define PHY_BCM5411_PHY_ID 0x60008070 +#define PHY_BCM5701_PHY_ID 0x60008110 +#define PHY_BCM5703_PHY_ID 0x60008160 +#define PHY_BCM5704_PHY_ID 0x60008190 +#define PHY_BCM8002_PHY_ID 0x60010140 + +#define PHY_BCM5401_B0_REV 0x1 +#define PHY_BCM5401_B2_REV 0x3 +#define PHY_BCM5401_C0_REV 0x6 + +#define PHY_ID_OUI_MASK 0xfffffc00 +#define PHY_ID_MODEL_MASK 0x000003f0 +#define PHY_ID_REV_MASK 0x0000000f +#define PHY_ID_MASK (PHY_ID_OUI_MASK | \ + PHY_ID_MODEL_MASK) + + +#define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID)) + + +/* 1000Base-T control register. */ +#define BCM540X_1000BASET_CTRL_REG 0x09 + +#define BCM540X_AN_AD_1000BASET_HALF BIT_8 +#define BCM540X_AN_AD_1000BASET_FULL BIT_9 +#define BCM540X_CONFIG_AS_MASTER BIT_11 +#define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12 + + +/* Extended control register. */ +#define BCM540X_EXT_CTRL_REG 0x10 + +#define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1 +#define BCM540X_EXT_CTRL_TBI BIT_15 + +/* PHY extended status register. */ +#define BCM540X_EXT_STATUS_REG 0x11 + +#define BCM540X_EXT_STATUS_LINK_PASS BIT_8 + + +/* DSP Coefficient Read/Write Port. */ +#define BCM540X_DSP_RW_PORT 0x15 + + +/* DSP Coeficient Address Register. */ +#define BCM540X_DSP_ADDRESS_REG 0x17 + +#define BCM540X_DSP_TAP_NUMBER_MASK 0x00 +#define BCM540X_DSP_AGC_A 0x00 +#define BCM540X_DSP_AGC_B 0x01 +#define BCM540X_DSP_MSE_PAIR_STATUS 0x02 +#define BCM540X_DSP_SOFT_DECISION 0x03 +#define BCM540X_DSP_PHASE_REG 0x04 +#define BCM540X_DSP_SKEW 0x05 +#define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06 +#define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07 +#define BCM540X_DSP_LAST_ECHO 0x08 +#define BCM540X_DSP_FREQUENCY 0x09 +#define BCM540X_DSP_PLL_BANDWIDTH 0x0a +#define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b + +#define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT0 BIT_11 +#define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10) +#define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10) +#define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10) +#define BCM540X_DSP_FILTER_NEXT0 BIT_10 +#define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9) +#define BCM540X_DSP_FILTER_DFE BIT_9 +#define BCM540X_DSP_FILTER_FFE BIT_8 + +#define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12 + +#define BCM540X_DSP_SEL_CH_0 BIT_NONE +#define BCM540X_DSP_SEL_CH_1 BIT_13 +#define BCM540X_DSP_SEL_CH_2 BIT_14 +#define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14) + +#define BCM540X_CONTROL_ALL_CHANNELS BIT_15 + + +/* Auxilliary Control Register (Shadow Register) */ +#define BCM5401_AUX_CTRL 0x18 + +#define BCM5401_SHADOW_SEL_MASK 0x7 +#define BCM5401_SHADOW_SEL_NORMAL 0x00 +#define BCM5401_SHADOW_SEL_10BASET 0x01 +#define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02 +#define BCM5401_SHADOW_SEL_IP_PHONE 0x03 +#define BCM5401_SHADOW_SEL_MISC_TEST1 0x04 +#define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 +#define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 + + +/* Shadow register selector == '000' */ +#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 +#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 +#define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5 +#define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6 +#define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7 +#define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE +#define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8 +#define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9 +#define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9) +#define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10 +#define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11 +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12 +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13 +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13) +#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 +#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 + + +/* Auxilliary status summary. */ +#define BCM540X_AUX_STATUS_REG 0x19 + +#define BCM540X_AUX_LINK_PASS BIT_2 +#define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10) +#define BCM540X_AUX_10BASET_HD BIT_8 +#define BCM540X_AUX_10BASET_FD BIT_9 +#define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9) +#define BCM540X_AUX_100BASET4 BIT_10 +#define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10) +#define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10) +#define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10) + + +/* Interrupt status. */ +#define BCM540X_INT_STATUS_REG 0x1a + +#define BCM540X_INT_LINK_CHANGE BIT_1 +#define BCM540X_INT_SPEED_CHANGE BIT_2 +#define BCM540X_INT_DUPLEX_CHANGE BIT_3 +#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 + + +/* Interrupt mask register. */ +#define BCM540X_INT_MASK_REG 0x1b + + +/******************************************************************************/ +/* Register definitions. */ +/******************************************************************************/ + +typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER; +typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER; +typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER; + +typedef struct { + /* Big endian format. */ + T3_32BIT_REGISTER High; + T3_32BIT_REGISTER Low; +} T3_64BIT_REGISTER, *PT3_64BIT_REGISTER; + +typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; + +#define T3_NUM_OF_DMA_DESC 256 +#define T3_NUM_OF_MBUF 768 + +typedef struct +{ + T3_64BIT_REGISTER host_addr; + T3_32BIT_REGISTER nic_mbuf; + T3_16BIT_REGISTER len; + T3_16BIT_REGISTER cqid_sqid; + T3_32BIT_REGISTER flags; + T3_32BIT_REGISTER opaque1; + T3_32BIT_REGISTER opaque2; + T3_32BIT_REGISTER opaque3; +}T3_DMA_DESC, *PT3_DMA_DESC; + + +/******************************************************************************/ +/* Ring control block. */ +/******************************************************************************/ + +typedef struct { + T3_64BIT_REGISTER HostRingAddr; + + union { + struct { +#ifdef BIG_ENDIAN_HOST + T3_16BIT_REGISTER MaxLen; + T3_16BIT_REGISTER Flags; +#else /* BIG_ENDIAN_HOST */ + T3_16BIT_REGISTER Flags; + T3_16BIT_REGISTER MaxLen; +#endif + } s; + + T3_32BIT_REGISTER MaxLen_Flags; + } u; + + T3_32BIT_REGISTER NicRingAddr; +} T3_RCB, *PT3_RCB; + +#define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0 +#define T3_RCB_FLAG_RING_DISABLED BIT_1 + + +/******************************************************************************/ +/* Status block. */ +/******************************************************************************/ + +/* + * Size of status block is actually 0x50 bytes. Use 0x80 bytes for + * cache line alignment. + */ +#define T3_STATUS_BLOCK_SIZE 0x80 + +typedef struct { + volatile LM_UINT32 Status; + #define STATUS_BLOCK_UPDATED BIT_0 + #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 + #define STATUS_BLOCK_ERROR BIT_2 + + volatile LM_UINT32 StatusTag; + +#ifdef BIG_ENDIAN_HOST + volatile LM_UINT16 RcvStdConIdx; + volatile LM_UINT16 RcvJumboConIdx; + + volatile LM_UINT16 Reserved2; + volatile LM_UINT16 RcvMiniConIdx; + + struct { + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + } Idx[16]; +#else /* BIG_ENDIAN_HOST */ + volatile LM_UINT16 RcvJumboConIdx; + volatile LM_UINT16 RcvStdConIdx; + + volatile LM_UINT16 RcvMiniConIdx; + volatile LM_UINT16 Reserved2; + + struct { + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + } Idx[16]; +#endif +} T3_STATUS_BLOCK, *PT3_STATUS_BLOCK; + + +/******************************************************************************/ +/* Receive buffer descriptors. */ +/******************************************************************************/ + +typedef struct { + T3_64BIT_HOST_ADDR HostAddr; + +#ifdef BIG_ENDIAN_HOST + volatile LM_UINT16 Index; + volatile LM_UINT16 Len; + + volatile LM_UINT16 Type; + volatile LM_UINT16 Flags; + + volatile LM_UINT16 IpCksum; + volatile LM_UINT16 TcpUdpCksum; + + volatile LM_UINT16 ErrorFlag; + volatile LM_UINT16 VlanTag; +#else /* BIG_ENDIAN_HOST */ + volatile LM_UINT16 Len; + volatile LM_UINT16 Index; + + volatile LM_UINT16 Flags; + volatile LM_UINT16 Type; + + volatile LM_UINT16 TcpUdpCksum; + volatile LM_UINT16 IpCksum; + + volatile LM_UINT16 VlanTag; + volatile LM_UINT16 ErrorFlag; +#endif + + volatile LM_UINT32 Reserved; + volatile LM_UINT32 Opaque; +} T3_RCV_BD, *PT3_RCV_BD; + + +typedef struct { + T3_64BIT_HOST_ADDR HostAddr[3]; + +#ifdef BIG_ENDIAN_HOST + LM_UINT16 Len1; + LM_UINT16 Len2; + + LM_UINT16 Len3; + LM_UINT16 Reserved1; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 Len2; + LM_UINT16 Len1; + + LM_UINT16 Reserved1; + LM_UINT16 Len3; +#endif + + T3_RCV_BD StdRcvBd; +} T3_EXT_RCV_BD, *PT3_EXT_RCV_BD; + + +/* Error flags. */ +#define RCV_BD_ERR_BAD_CRC 0x0001 +#define RCV_BD_ERR_COLL_DETECT 0x0002 +#define RCV_BD_ERR_LINK_LOST_DURING_PKT 0x0004 +#define RCV_BD_ERR_PHY_DECODE_ERR 0x0008 +#define RCV_BD_ERR_ODD_NIBBLED_RCVD_MII 0x0010 +#define RCV_BD_ERR_MAC_ABORT 0x0020 +#define RCV_BD_ERR_LEN_LT_64 0x0040 +#define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080 +#define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100 + + +/* Buffer descriptor flags. */ +#define RCV_BD_FLAG_END 0x0004 +#define RCV_BD_FLAG_JUMBO_RING 0x0020 +#define RCV_BD_FLAG_VLAN_TAG 0x0040 +#define RCV_BD_FLAG_FRAME_HAS_ERROR 0x0400 +#define RCV_BD_FLAG_MINI_RING 0x0800 +#define RCV_BD_FLAG_IP_CHKSUM_FIELD 0x1000 +#define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000 +#define RCV_BD_FLAG_TCP_PACKET 0x4000 + + +/******************************************************************************/ +/* Send buffer descriptor. */ +/******************************************************************************/ + +typedef struct { + T3_64BIT_HOST_ADDR HostAddr; + + union { + struct { +#ifdef BIG_ENDIAN_HOST + LM_UINT16 Len; + LM_UINT16 Flags; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 Flags; + LM_UINT16 Len; +#endif + } s1; + + LM_UINT32 Len_Flags; + } u1; + + union { + struct { +#ifdef BIG_ENDIAN_HOST + LM_UINT16 Reserved; + LM_UINT16 VlanTag; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 VlanTag; + LM_UINT16 Reserved; +#endif + } s2; + + LM_UINT32 VlanTag; + } u2; +} T3_SND_BD, *PT3_SND_BD; + + +/* Send buffer descriptor flags. */ +#define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001 +#define SND_BD_FLAG_IP_CKSUM 0x0002 +#define SND_BD_FLAG_END 0x0004 +#define SND_BD_FLAG_IP_FRAG 0x0008 +#define SND_BD_FLAG_IP_FRAG_END 0x0010 +#define SND_BD_FLAG_VLAN_TAG 0x0040 +#define SND_BD_FLAG_COAL_NOW 0x0080 +#define SND_BD_FLAG_CPU_PRE_DMA 0x0100 +#define SND_BD_FLAG_CPU_POST_DMA 0x0200 +#define SND_BD_FLAG_INSERT_SRC_ADDR 0x1000 +#define SND_BD_FLAG_CHOOSE_SRC_ADDR 0x6000 +#define SND_BD_FLAG_DONT_GEN_CRC 0x8000 + +/* MBUFs */ +typedef struct T3_MBUF_FRAME_DESC { +#ifdef BIG_ENDIAN_HOST + LM_UINT32 status_control; + union { + struct { + LM_UINT8 cqid; + LM_UINT8 reserved1; + LM_UINT16 length; + }s1; + LM_UINT32 word; + }u1; + union { + struct + { + LM_UINT16 ip_hdr_start; + LM_UINT16 tcp_udp_hdr_start; + }s2; + + LM_UINT32 word; + }u2; + + union { + struct { + LM_UINT16 data_start; + LM_UINT16 vlan_id; + }s3; + + LM_UINT32 word; + }u3; + + union { + struct { + LM_UINT16 ip_checksum; + LM_UINT16 tcp_udp_checksum; + }s4; + + LM_UINT32 word; + }u4; + + union { + struct { + LM_UINT16 pseudo_checksum; + LM_UINT16 checksum_status; + }s5; + + LM_UINT32 word; + }u5; + + union { + struct { + LM_UINT16 rule_match; + LM_UINT8 class; + LM_UINT8 rupt; + }s6; + + LM_UINT32 word; + }u6; + + union { + struct { + LM_UINT16 reserved2; + LM_UINT16 mbuf_num; + }s7; + + LM_UINT32 word; + }u7; + + LM_UINT32 reserved3; + LM_UINT32 reserved4; +#else + LM_UINT32 status_control; + union { + struct { + LM_UINT16 length; + LM_UINT8 reserved1; + LM_UINT8 cqid; + }s1; + LM_UINT32 word; + }u1; + union { + struct + { + LM_UINT16 tcp_udp_hdr_start; + LM_UINT16 ip_hdr_start; + }s2; + + LM_UINT32 word; + }u2; + + union { + struct { + LM_UINT16 vlan_id; + LM_UINT16 data_start; + }s3; + + LM_UINT32 word; + }u3; + + union { + struct { + LM_UINT16 tcp_udp_checksum; + LM_UINT16 ip_checksum; + }s4; + + LM_UINT32 word; + }u4; + + union { + struct { + LM_UINT16 checksum_status; + LM_UINT16 pseudo_checksum; + }s5; + + LM_UINT32 word; + }u5; + + union { + struct { + LM_UINT8 rupt; + LM_UINT8 class; + LM_UINT16 rule_match; + }s6; + + LM_UINT32 word; + }u6; + + union { + struct { + LM_UINT16 mbuf_num; + LM_UINT16 reserved2; + }s7; + + LM_UINT32 word; + }u7; + + LM_UINT32 reserved3; + LM_UINT32 reserved4; +#endif +}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC; + +typedef struct T3_MBUF_HDR { + union { + struct { + unsigned int C:1; + unsigned int F:1; + unsigned int reserved1:7; + unsigned int next_mbuf:16; + unsigned int length:7; + }s1; + + LM_UINT32 word; + }u1; + + LM_UINT32 next_frame_ptr; +}T3_MBUF_HDR, *PT3_MBUF_HDR; + +typedef struct T3_MBUF +{ + T3_MBUF_HDR hdr; + union + { + struct { + T3_MBUF_FRAME_DESC frame_hdr; + LM_UINT32 data[20]; + }s1; + + struct { + LM_UINT32 data[30]; + }s2; + }body; +}T3_MBUF, *PT3_MBUF; + +#define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7) +#define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7) + + +/******************************************************************************/ +/* Statistics block. */ +/******************************************************************************/ + +typedef struct { + LM_UINT8 Reserved0[0x400-0x300]; + + /* Statistics maintained by Receive MAC. */ + T3_64BIT_REGISTER ifHCInOctets; + T3_64BIT_REGISTER Reserved1; + T3_64BIT_REGISTER etherStatsFragments; + T3_64BIT_REGISTER ifHCInUcastPkts; + T3_64BIT_REGISTER ifHCInMulticastPkts; + T3_64BIT_REGISTER ifHCInBroadcastPkts; + T3_64BIT_REGISTER dot3StatsFCSErrors; + T3_64BIT_REGISTER dot3StatsAlignmentErrors; + T3_64BIT_REGISTER xonPauseFramesReceived; + T3_64BIT_REGISTER xoffPauseFramesReceived; + T3_64BIT_REGISTER macControlFramesReceived; + T3_64BIT_REGISTER xoffStateEntered; + T3_64BIT_REGISTER dot3StatsFramesTooLong; + T3_64BIT_REGISTER etherStatsJabbers; + T3_64BIT_REGISTER etherStatsUndersizePkts; + T3_64BIT_REGISTER inRangeLengthError; + T3_64BIT_REGISTER outRangeLengthError; + T3_64BIT_REGISTER etherStatsPkts64Octets; + T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; + T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; + T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; + T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; + T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; + T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; + T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; + T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; + T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; + + T3_64BIT_REGISTER Unused1[37]; + + /* Statistics maintained by Transmit MAC. */ + T3_64BIT_REGISTER ifHCOutOctets; + T3_64BIT_REGISTER Reserved2; + T3_64BIT_REGISTER etherStatsCollisions; + T3_64BIT_REGISTER outXonSent; + T3_64BIT_REGISTER outXoffSent; + T3_64BIT_REGISTER flowControlDone; + T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; + T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; + T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; + T3_64BIT_REGISTER dot3StatsDeferredTransmissions; + T3_64BIT_REGISTER Reserved3; + T3_64BIT_REGISTER dot3StatsExcessiveCollisions; + T3_64BIT_REGISTER dot3StatsLateCollisions; + T3_64BIT_REGISTER dot3Collided2Times; + T3_64BIT_REGISTER dot3Collided3Times; + T3_64BIT_REGISTER dot3Collided4Times; + T3_64BIT_REGISTER dot3Collided5Times; + T3_64BIT_REGISTER dot3Collided6Times; + T3_64BIT_REGISTER dot3Collided7Times; + T3_64BIT_REGISTER dot3Collided8Times; + T3_64BIT_REGISTER dot3Collided9Times; + T3_64BIT_REGISTER dot3Collided10Times; + T3_64BIT_REGISTER dot3Collided11Times; + T3_64BIT_REGISTER dot3Collided12Times; + T3_64BIT_REGISTER dot3Collided13Times; + T3_64BIT_REGISTER dot3Collided14Times; + T3_64BIT_REGISTER dot3Collided15Times; + T3_64BIT_REGISTER ifHCOutUcastPkts; + T3_64BIT_REGISTER ifHCOutMulticastPkts; + T3_64BIT_REGISTER ifHCOutBroadcastPkts; + T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; + T3_64BIT_REGISTER ifOutDiscards; + T3_64BIT_REGISTER ifOutErrors; + + T3_64BIT_REGISTER Unused2[31]; + + /* Statistics maintained by Receive List Placement. */ + T3_64BIT_REGISTER COSIfHCInPkts[16]; + T3_64BIT_REGISTER COSFramesDroppedDueToFilters; + T3_64BIT_REGISTER nicDmaWriteQueueFull; + T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; + T3_64BIT_REGISTER nicNoMoreRxBDs; + T3_64BIT_REGISTER ifInDiscards; + T3_64BIT_REGISTER ifInErrors; + T3_64BIT_REGISTER nicRecvThresholdHit; + + T3_64BIT_REGISTER Unused3[9]; + + /* Statistics maintained by Send Data Initiator. */ + T3_64BIT_REGISTER COSIfHCOutPkts[16]; + T3_64BIT_REGISTER nicDmaReadQueueFull; + T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; + T3_64BIT_REGISTER nicSendDataCompQueueFull; + + /* Statistics maintained by Host Coalescing. */ + T3_64BIT_REGISTER nicRingSetSendProdIndex; + T3_64BIT_REGISTER nicRingStatusUpdate; + T3_64BIT_REGISTER nicInterrupts; + T3_64BIT_REGISTER nicAvoidedInterrupts; + T3_64BIT_REGISTER nicSendThresholdHit; + + LM_UINT8 Reserved4[0xb00-0x9c0]; +} T3_STATS_BLOCK, *PT3_STATS_BLOCK; + + +/******************************************************************************/ +/* PCI configuration registers. */ +/******************************************************************************/ + +typedef struct { + T3_16BIT_REGISTER VendorId; + T3_16BIT_REGISTER DeviceId; + + T3_16BIT_REGISTER Command; + T3_16BIT_REGISTER Status; + + T3_32BIT_REGISTER ClassCodeRevId; + + T3_8BIT_REGISTER CacheLineSize; + T3_8BIT_REGISTER LatencyTimer; + T3_8BIT_REGISTER HeaderType; + T3_8BIT_REGISTER Bist; + + T3_32BIT_REGISTER MemBaseAddrLow; + T3_32BIT_REGISTER MemBaseAddrHigh; + + LM_UINT8 Unused1[20]; + + T3_16BIT_REGISTER SubsystemVendorId; + T3_16BIT_REGISTER SubsystemId; + + T3_32BIT_REGISTER RomBaseAddr; + + T3_8BIT_REGISTER PciXCapiblityPtr; + LM_UINT8 Unused2[7]; + + T3_8BIT_REGISTER IntLine; + T3_8BIT_REGISTER IntPin; + T3_8BIT_REGISTER MinGnt; + T3_8BIT_REGISTER MaxLat; + + T3_8BIT_REGISTER PciXCapabilities; + T3_8BIT_REGISTER PmCapabilityPtr; + T3_16BIT_REGISTER PciXCommand; + + T3_32BIT_REGISTER PciXStatus; + + T3_8BIT_REGISTER PmCapabilityId; + T3_8BIT_REGISTER VpdCapabilityPtr; + T3_16BIT_REGISTER PmCapabilities; + + T3_16BIT_REGISTER PmCtrlStatus; + #define PM_CTRL_PME_STATUS BIT_15 + #define PM_CTRL_PME_ENABLE BIT_8 + #define PM_CTRL_PME_POWER_STATE_D0 0 + #define PM_CTRL_PME_POWER_STATE_D1 1 + #define PM_CTRL_PME_POWER_STATE_D2 2 + #define PM_CTRL_PME_POWER_STATE_D3H 3 + + T3_8BIT_REGISTER BridgeSupportExt; + T3_8BIT_REGISTER PmData; + + T3_8BIT_REGISTER VpdCapabilityId; + T3_8BIT_REGISTER MsiCapabilityPtr; + T3_16BIT_REGISTER VpdAddrFlag; + #define VPD_FLAG_WRITE (1 << 15) + #define VPD_FLAG_RW_MASK (1 << 15) + #define VPD_FLAG_READ 0 + + + T3_32BIT_REGISTER VpdData; + + T3_8BIT_REGISTER MsiCapabilityId; + T3_8BIT_REGISTER NextCapabilityPtr; + T3_16BIT_REGISTER MsiCtrl; + #define MSI_CTRL_64BIT_CAP (1 << 7) + #define MSI_CTRL_MSG_ENABLE(x) (x << 4) + #define MSI_CTRL_MSG_CAP(x) (x << 1) + #define MSI_CTRL_ENABLE (1 << 0) + + + T3_32BIT_REGISTER MsiAddrLow; + T3_32BIT_REGISTER MsiAddrHigh; + + T3_16BIT_REGISTER MsiData; + T3_16BIT_REGISTER Unused3; + + T3_32BIT_REGISTER MiscHostCtrl; + #define MISC_HOST_CTRL_CLEAR_INT BIT_0 + #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 + #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 + #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 + #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 + #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 + #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 + #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 + #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 + #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 + + T3_32BIT_REGISTER DmaReadWriteCtrl; + #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) + #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 + #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 + #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 + #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) + #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 + #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) + #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) + #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) + #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 + + + T3_32BIT_REGISTER PciState; + #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 + #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 + #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 + #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 + #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 + #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 + #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 + #define T3_PCI_STATE_FLAT_VIEW BIT_8 + #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 + + T3_32BIT_REGISTER ClockCtrl; + #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 + #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 + #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 + + T3_32BIT_REGISTER RegBaseAddr; + + T3_32BIT_REGISTER MemWindowBaseAddr; + +#ifdef NIC_CPU_VIEW + /* These registers are ONLY visible to NIC CPU */ + T3_32BIT_REGISTER PowerConsumed; + T3_32BIT_REGISTER PowerDissipated; +#else /* NIC_CPU_VIEW */ + T3_32BIT_REGISTER RegData; + T3_32BIT_REGISTER MemWindowData; +#endif /* !NIC_CPU_VIEW */ + + T3_32BIT_REGISTER ModeCtrl; + + T3_32BIT_REGISTER MiscCfg; + + T3_32BIT_REGISTER MiscLocalCtrl; + + T3_32BIT_REGISTER Unused4; + + /* NOTE: Big/Little-endian clarification needed. Are these register */ + /* in big or little endian formate. */ + T3_64BIT_REGISTER StdRingProdIdx; + T3_64BIT_REGISTER RcvRetRingConIdx; + T3_64BIT_REGISTER SndProdIdx; + + LM_UINT8 Unused5[80]; +} T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION; + +#define PCIX_CMD_MAX_SPLIT_MASK 0x0070 +#define PCIX_CMD_MAX_SPLIT_SHL 4 +#define PCIX_CMD_MAX_BURST_MASK 0x000c +#define PCIX_CMD_MAX_BURST_SHL 2 +#define PCIX_CMD_MAX_BURST_CPIOB 2 + +/******************************************************************************/ +/* Mac control registers. */ +/******************************************************************************/ + +typedef struct { + /* MAC mode control. */ + T3_32BIT_REGISTER Mode; + #define MAC_MODE_GLOBAL_RESET BIT_0 + #define MAC_MODE_HALF_DUPLEX BIT_1 + #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) + #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) + #define MAC_MODE_PORT_MODE_GMII BIT_3 + #define MAC_MODE_PORT_MODE_MII BIT_2 + #define MAC_MODE_PORT_MODE_NONE BIT_NONE + #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 + #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 + #define MAC_MODE_TX_BURSTING BIT_8 + #define MAC_MODE_MAX_DEFER BIT_9 + #define MAC_MODE_LINK_POLARITY BIT_10 + #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 + #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 + #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 + #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 + #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 + #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 + #define MAC_MODE_SEND_CONFIGS BIT_17 + #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 + #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 + #define MAC_MODE_ENABLE_MIP BIT_20 + #define MAC_MODE_ENABLE_TDE BIT_21 + #define MAC_MODE_ENABLE_RDE BIT_22 + #define MAC_MODE_ENABLE_FHDE BIT_23 + + /* MAC status */ + T3_32BIT_REGISTER Status; + #define MAC_STATUS_PCS_SYNCED BIT_0 + #define MAC_STATUS_SIGNAL_DETECTED BIT_1 + #define MAC_STATUS_RECEIVING_CFG BIT_2 + #define MAC_STATUS_CFG_CHANGED BIT_3 + #define MAC_STATUS_SYNC_CHANGED BIT_4 + #define MAC_STATUS_PORT_DECODE_ERROR BIT_10 + #define MAC_STATUS_LINK_STATE_CHANGED BIT_12 + #define MAC_STATUS_MI_COMPLETION BIT_22 + #define MAC_STATUS_MI_INTERRUPT BIT_23 + #define MAC_STATUS_AP_ERROR BIT_24 + #define MAC_STATUS_ODI_ERROR BIT_25 + #define MAC_STATUS_RX_STATS_OVERRUN BIT_26 + #define MAC_STATUS_TX_STATS_OVERRUN BIT_27 + + /* Event Enable */ + T3_32BIT_REGISTER MacEvent; + #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 + #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 + #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 + #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 + #define MAC_EVENT_ENABLE_AP_ERROR BIT_24 + #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 + #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 + #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 + + /* Led control. */ + T3_32BIT_REGISTER LedCtrl; + #define LED_CTRL_OVERRIDE_LINK_LED BIT_0 + #define LED_CTRL_1000MBPS_LED_ON BIT_1 + #define LED_CTRL_100MBPS_LED_ON BIT_2 + #define LED_CTRL_10MBPS_LED_ON BIT_3 + #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 + #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 + #define LED_CTRL_TRAFFIC_LED BIT_6 + #define LED_CTRL_1000MBPS_LED_STATUS BIT_7 + #define LED_CTRL_100MBPS_LED_STATUS BIT_8 + #define LED_CTRL_10MBPS_LED_STATUS BIT_9 + #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 + #define LED_CTRL_MAC_MODE BIT_NONE + #define LED_CTRL_PHY_MODE_1 BIT_11 + #define LED_CTRL_PHY_MODE_2 BIT_12 + #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 + #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 + #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 + + /* MAC addresses. */ + struct { + T3_32BIT_REGISTER High; /* Upper 2 bytes. */ + T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ + } MacAddr[4]; + + /* ACPI Mbuf pointer. */ + T3_32BIT_REGISTER AcpiMbufPtr; + + /* ACPI Length and Offset. */ + T3_32BIT_REGISTER AcpiLengthOffset; + #define ACPI_LENGTH_MASK 0xffff + #define ACPI_OFFSET_MASK 0x0fff0000 + #define ACPI_LENGTH(x) x + #define ACPI_OFFSET(x) ((x) << 16) + + /* Transmit random backoff. */ + T3_32BIT_REGISTER TxBackoffSeed; + #define MAC_TX_BACKOFF_SEED_MASK 0x3ff + + /* Receive MTU */ + T3_32BIT_REGISTER MtuSize; + #define MAC_RX_MTU_MASK 0xffff + + /* Gigabit PCS Test. */ + T3_32BIT_REGISTER PcsTest; + #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff + #define MAC_PCS_TEST_ENABLE BIT_20 + + /* Transmit Gigabit Auto-Negotiation. */ + T3_32BIT_REGISTER TxAutoNeg; + #define MAC_AN_TX_AN_DATA_MASK 0xffff + + /* Receive Gigabit Auto-Negotiation. */ + T3_32BIT_REGISTER RxAutoNeg; + #define MAC_AN_RX_AN_DATA_MASK 0xffff + + /* MI Communication. */ + T3_32BIT_REGISTER MiCom; + #define MI_COM_CMD_MASK (BIT_26 | BIT_27) + #define MI_COM_CMD_WRITE BIT_26 + #define MI_COM_CMD_READ BIT_27 + #define MI_COM_READ_FAILED BIT_28 + #define MI_COM_START BIT_29 + #define MI_COM_BUSY BIT_29 + + #define MI_COM_PHY_ADDR_MASK 0x1f + #define MI_COM_FIRST_PHY_ADDR_BIT 21 + + #define MI_COM_PHY_REG_ADDR_MASK 0x1f + #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 + + #define MI_COM_PHY_DATA_MASK 0xffff + + /* MI Status. */ + T3_32BIT_REGISTER MiStatus; + #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 + + /* MI Mode. */ + T3_32BIT_REGISTER MiMode; + #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 + #define MI_MODE_USE_SHORT_PREAMBLE BIT_1 + #define MI_MODE_AUTO_POLLING_ENABLE BIT_4 + #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 + + /* Auto-polling status. */ + T3_32BIT_REGISTER AutoPollStatus; + #define AUTO_POLL_ERROR BIT_0 + + /* Transmit MAC mode. */ + T3_32BIT_REGISTER TxMode; + #define TX_MODE_RESET BIT_0 + #define TX_MODE_ENABLE BIT_1 + #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 + #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 + #define TX_MODE_ENABLE_LONG_PAUSE BIT_6 + + /* Transmit MAC status. */ + T3_32BIT_REGISTER TxStatus; + #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 + #define TX_STATUS_SENT_XOFF BIT_1 + #define TX_STATUS_SENT_XON BIT_2 + #define TX_STATUS_LINK_UP BIT_3 + #define TX_STATUS_ODI_UNDERRUN BIT_4 + #define TX_STATUS_ODI_OVERRUN BIT_5 + + /* Transmit MAC length. */ + T3_32BIT_REGISTER TxLengths; + #define TX_LEN_SLOT_TIME_MASK 0xff + #define TX_LEN_IPG_MASK 0x0f00 + #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) + + /* Receive MAC mode. */ + T3_32BIT_REGISTER RxMode; + #define RX_MODE_RESET BIT_0 + #define RX_MODE_ENABLE BIT_1 + #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 + #define RX_MODE_KEEP_MAC_CONTROL BIT_3 + #define RX_MODE_KEEP_PAUSE BIT_4 + #define RX_MODE_ACCEPT_OVERSIZED BIT_5 + #define RX_MODE_ACCEPT_RUNTS BIT_6 + #define RX_MODE_LENGTH_CHECK BIT_7 + #define RX_MODE_PROMISCUOUS_MODE BIT_8 + #define RX_MODE_NO_CRC_CHECK BIT_9 + #define RX_MODE_KEEP_VLAN_TAG BIT_10 + + /* Receive MAC status. */ + T3_32BIT_REGISTER RxStatus; + #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 + #define RX_STATUS_XOFF_RECEIVED BIT_1 + #define RX_STATUS_XON_RECEIVED BIT_2 + + /* Hash registers. */ + T3_32BIT_REGISTER HashReg[4]; + + /* Receive placement rules registers. */ + struct { + T3_32BIT_REGISTER Rule; + T3_32BIT_REGISTER Value; + } RcvRules[16]; + + #define RCV_DISABLE_RULE_MASK 0x7fffffff + + #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 + #define REJECT_BROADCAST_RULE1_RULE 0xc2000000 + #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff + + #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 + #define REJECT_BROADCAST_RULE2_RULE 0x86000004 + #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff + +#if INCLUDE_5701_AX_FIX + #define RCV_LAST_RULE_IDX 0x04 +#else + #define RCV_LAST_RULE_IDX 0x02 +#endif + + T3_32BIT_REGISTER RcvRuleCfg; + #define RX_RULE_DEFAULT_CLASS (1 << 3) + + LM_UINT8 Reserved1[140]; + + T3_32BIT_REGISTER SerdesCfg; + T3_32BIT_REGISTER SerdesStatus; + + LM_UINT8 Reserved2[104]; + + volatile LM_UINT8 TxMacState[16]; + volatile LM_UINT8 RxMacState[20]; + + LM_UINT8 Reserved3[476]; + + T3_32BIT_REGISTER RxStats[26]; + + LM_UINT8 Reserved4[24]; + + T3_32BIT_REGISTER TxStats[28]; + + LM_UINT8 Reserved5[784]; +} T3_MAC_CONTROL, *PT3_MAC_CONTROL; + + +/******************************************************************************/ +/* Send data initiator control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define T3_SND_DATA_IN_MODE_RESET BIT_0 + #define T3_SND_DATA_IN_MODE_ENABLE BIT_1 + #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 + + T3_32BIT_REGISTER StatsCtrl; + #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 + #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 + #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 + #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 + #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 + + T3_32BIT_REGISTER StatsEnableMask; + T3_32BIT_REGISTER StatsIncMask; + + LM_UINT8 Reserved[108]; + + T3_32BIT_REGISTER ClassOfServCnt[16]; + T3_32BIT_REGISTER DmaReadQFullCnt; + T3_32BIT_REGISTER DmaPriorityReadQFullCnt; + T3_32BIT_REGISTER SdcQFullCnt; + + T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; + T3_32BIT_REGISTER StatusUpdatedCnt; + T3_32BIT_REGISTER InterruptsCnt; + T3_32BIT_REGISTER AvoidInterruptsCnt; + T3_32BIT_REGISTER SendThresholdHitCnt; + + /* Unused space. */ + LM_UINT8 Unused[800]; +} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; + + +/******************************************************************************/ +/* Send data completion control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define SND_DATA_COMP_MODE_RESET BIT_0 + #define SND_DATA_COMP_MODE_ENABLE BIT_1 + + /* Unused space. */ + LM_UINT8 Unused[1020]; +} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION; + + +/******************************************************************************/ +/* Send BD Ring Selector Control Registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define SND_BD_SEL_MODE_RESET BIT_0 + #define SND_BD_SEL_MODE_ENABLE BIT_1 + #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 + + T3_32BIT_REGISTER HwDiag; + + /* Unused space. */ + LM_UINT8 Unused1[52]; + + /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ + T3_32BIT_REGISTER NicSendBdSelConIdx[16]; + + /* Unused space. */ + LM_UINT8 Unused2[896]; +} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR; + + +/******************************************************************************/ +/* Send BD initiator control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define SND_BD_IN_MODE_RESET BIT_0 + #define SND_BD_IN_MODE_ENABLE BIT_1 + #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 + + /* Send BD initiator local NIC send BD producer index. */ + T3_32BIT_REGISTER NicSendBdInProdIdx[16]; + + /* Unused space. */ + LM_UINT8 Unused2[952]; +} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR; + + +/******************************************************************************/ +/* Send BD Completion Control. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define SND_BD_COMP_MODE_RESET BIT_0 + #define SND_BD_COMP_MODE_ENABLE BIT_1 + #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 + + /* Unused space. */ + LM_UINT8 Unused2[1020]; +} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION; + + +/******************************************************************************/ +/* Receive list placement control registers. */ +/******************************************************************************/ + +typedef struct { + /* Mode. */ + T3_32BIT_REGISTER Mode; + #define RCV_LIST_PLMT_MODE_RESET BIT_0 + #define RCV_LIST_PLMT_MODE_ENABLE BIT_1 + #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 + #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 + #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 + + /* Status. */ + T3_32BIT_REGISTER Status; + #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 + #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 + #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 + + /* Receive selector list lock register. */ + T3_32BIT_REGISTER Lock; + #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff + #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 + + /* Selector non-empty bits. */ + T3_32BIT_REGISTER NonEmptyBits; + #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff + + /* Receive list placement configuration register. */ + T3_32BIT_REGISTER Config; + + /* Receive List Placement statistics Control. */ + T3_32BIT_REGISTER StatsCtrl; +#define RCV_LIST_STATS_ENABLE BIT_0 +#define RCV_LIST_STATS_FAST_UPDATE BIT_1 + + /* Receive List Placement statistics Enable Mask. */ + T3_32BIT_REGISTER StatsEnableMask; + + /* Receive List Placement statistics Increment Mask. */ + T3_32BIT_REGISTER StatsIncMask; + + /* Unused space. */ + LM_UINT8 Unused1[224]; + + struct { + T3_32BIT_REGISTER Head; + T3_32BIT_REGISTER Tail; + T3_32BIT_REGISTER Count; + + /* Unused space. */ + LM_UINT8 Unused[4]; + } RcvSelectorList[16]; + + /* Local statistics counter. */ + T3_32BIT_REGISTER ClassOfServCnt[16]; + + T3_32BIT_REGISTER DropDueToFilterCnt; + T3_32BIT_REGISTER DmaWriteQFullCnt; + T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; + T3_32BIT_REGISTER NoMoreReceiveBdCnt; + T3_32BIT_REGISTER IfInDiscardsCnt; + T3_32BIT_REGISTER IfInErrorsCnt; + T3_32BIT_REGISTER RcvThresholdHitCnt; + + /* Another unused space. */ + LM_UINT8 Unused2[420]; +} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; + + +/******************************************************************************/ +/* Receive Data and Receive BD Initiator Control. */ +/******************************************************************************/ + +typedef struct { + /* Mode. */ + T3_32BIT_REGISTER Mode; + #define RCV_DATA_BD_IN_MODE_RESET BIT_0 + #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 + #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 + #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 + #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 + + /* Status. */ + T3_32BIT_REGISTER Status; + #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 + #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 + #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 + + /* Split frame minium size. */ + T3_32BIT_REGISTER SplitFrameMinSize; + + /* Unused space. */ + LM_UINT8 Unused1[0x2440-0x240c]; + + /* Receive RCBs. */ + T3_RCB JumboRcvRcb; + T3_RCB StdRcvRcb; + T3_RCB MiniRcvRcb; + + /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ + /* BD Consumber Index. */ + T3_32BIT_REGISTER NicJumboConIdx; + T3_32BIT_REGISTER NicStdConIdx; + T3_32BIT_REGISTER NicMiniConIdx; + + /* Unused space. */ + LM_UINT8 Unused2[4]; + + /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ + T3_32BIT_REGISTER RcvDataBdProdIdx[16]; + + /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ + T3_32BIT_REGISTER HwDiag; + + /* Unused space. */ + LM_UINT8 Unused3[828]; +} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; + + +/******************************************************************************/ +/* Receive Data Completion Control Registes. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define RCV_DATA_COMP_MODE_RESET BIT_0 + #define RCV_DATA_COMP_MODE_ENABLE BIT_1 + #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 + + /* Unused spaced. */ + LM_UINT8 Unused[1020]; +} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION; + + +/******************************************************************************/ +/* Receive BD Initiator Control. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define RCV_BD_IN_MODE_RESET BIT_0 + #define RCV_BD_IN_MODE_ENABLE BIT_1 + #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 + + T3_32BIT_REGISTER NicJumboRcvProdIdx; + T3_32BIT_REGISTER NicStdRcvProdIdx; + T3_32BIT_REGISTER NicMiniRcvProdIdx; + + T3_32BIT_REGISTER MiniRcvThreshold; + T3_32BIT_REGISTER StdRcvThreshold; + T3_32BIT_REGISTER JumboRcvThreshold; + + /* Unused space. */ + LM_UINT8 Unused[992]; +} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR; + + +/******************************************************************************/ +/* Receive BD Completion Control Registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define RCV_BD_COMP_MODE_RESET BIT_0 + #define RCV_BD_COMP_MODE_ENABLE BIT_1 + #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 + + T3_32BIT_REGISTER NicJumboRcvBdProdIdx; + T3_32BIT_REGISTER NicStdRcvBdProdIdx; + T3_32BIT_REGISTER NicMiniRcvBdProdIdx; + + /* Unused space. */ + LM_UINT8 Unused[1004]; +} T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION; + + +/******************************************************************************/ +/* Receive list selector control register. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define RCV_LIST_SEL_MODE_RESET BIT_0 + #define RCV_LIST_SEL_MODE_ENABLE BIT_1 + #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 + + /* Unused space. */ + LM_UINT8 Unused[1016]; +} T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR; + + +/******************************************************************************/ +/* Mbuf cluster free registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; +#define MBUF_CLUSTER_FREE_MODE_RESET BIT_0 +#define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1 + + T3_32BIT_REGISTER Status; + + /* Unused space. */ + LM_UINT8 Unused[1016]; +} T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE; + + +/******************************************************************************/ +/* Host coalescing control registers. */ +/******************************************************************************/ + +typedef struct { + /* Mode. */ + T3_32BIT_REGISTER Mode; + #define HOST_COALESCE_RESET BIT_0 + #define HOST_COALESCE_ENABLE BIT_1 + #define HOST_COALESCE_ATTN BIT_2 + #define HOST_COALESCE_NOW BIT_3 + #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE + #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 + #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 + #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 + #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 + #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 + #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 + + /* Status. */ + T3_32BIT_REGISTER Status; + #define HOST_COALESCE_ERROR_ATTN BIT_2 + + /* Receive coalescing ticks. */ + T3_32BIT_REGISTER RxCoalescingTicks; + + /* Send coalescing ticks. */ + T3_32BIT_REGISTER TxCoalescingTicks; + + /* Receive max coalesced frames. */ + T3_32BIT_REGISTER RxMaxCoalescedFrames; + + /* Send max coalesced frames. */ + T3_32BIT_REGISTER TxMaxCoalescedFrames; + + /* Receive coalescing ticks during interrupt. */ + T3_32BIT_REGISTER RxCoalescedTickDuringInt; + + /* Send coalescing ticks during interrupt. */ + T3_32BIT_REGISTER TxCoalescedTickDuringInt; + + /* Receive max coalesced frames during interrupt. */ + T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; + + /* Send max coalesced frames during interrupt. */ + T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; + + /* Statistics tick. */ + T3_32BIT_REGISTER StatsCoalescingTicks; + + /* Unused space. */ + LM_UINT8 Unused2[4]; + + /* Statistics host address. */ + T3_64BIT_REGISTER StatsBlkHostAddr; + + /* Status block host address.*/ + T3_64BIT_REGISTER StatusBlkHostAddr; + + /* Statistics NIC address. */ + T3_32BIT_REGISTER StatsBlkNicAddr; + + /* Statust block NIC address. */ + T3_32BIT_REGISTER StatusBlkNicAddr; + + /* Flow attention registers. */ + T3_32BIT_REGISTER FlowAttn; + + /* Unused space. */ + LM_UINT8 Unused3[4]; + + T3_32BIT_REGISTER NicJumboRcvBdConIdx; + T3_32BIT_REGISTER NicStdRcvBdConIdx; + T3_32BIT_REGISTER NicMiniRcvBdConIdx; + + /* Unused space. */ + LM_UINT8 Unused4[36]; + + T3_32BIT_REGISTER NicRetProdIdx[16]; + T3_32BIT_REGISTER NicSndBdConIdx[16]; + + /* Unused space. */ + LM_UINT8 Unused5[768]; +} T3_HOST_COALESCING, *PT3_HOST_COALESCING; + + +/******************************************************************************/ +/* Memory arbiter registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; +#define T3_MEM_ARBITER_MODE_RESET BIT_0 +#define T3_MEM_ARBITER_MODE_ENABLE BIT_1 + + T3_32BIT_REGISTER Status; + + T3_32BIT_REGISTER ArbTrapAddrLow; + T3_32BIT_REGISTER ArbTrapAddrHigh; + + /* Unused space. */ + LM_UINT8 Unused[1008]; +} T3_MEM_ARBITER, *PT3_MEM_ARBITER; + + +/******************************************************************************/ +/* Buffer manager control register. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define BUFMGR_MODE_RESET BIT_0 + #define BUFMGR_MODE_ENABLE BIT_1 + #define BUFMGR_MODE_ATTN_ENABLE BIT_2 + #define BUFMGR_MODE_BM_TEST BIT_3 + #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 + + T3_32BIT_REGISTER Status; + #define BUFMGR_STATUS_ERROR BIT_2 + #define BUFMGR_STATUS_MBUF_LOW BIT_4 + + T3_32BIT_REGISTER MbufPoolAddr; + T3_32BIT_REGISTER MbufPoolSize; + T3_32BIT_REGISTER MbufReadDmaLowWaterMark; + T3_32BIT_REGISTER MbufMacRxLowWaterMark; + T3_32BIT_REGISTER MbufHighWaterMark; + + T3_32BIT_REGISTER RxCpuMbufAllocReq; + #define BUFMGR_MBUF_ALLOC_BIT BIT_31 + T3_32BIT_REGISTER RxCpuMbufAllocResp; + T3_32BIT_REGISTER TxCpuMbufAllocReq; + T3_32BIT_REGISTER TxCpuMbufAllocResp; + + T3_32BIT_REGISTER DmaDescPoolAddr; + T3_32BIT_REGISTER DmaDescPoolSize; + T3_32BIT_REGISTER DmaLowWaterMark; + T3_32BIT_REGISTER DmaHighWaterMark; + + T3_32BIT_REGISTER RxCpuDmaAllocReq; + T3_32BIT_REGISTER RxCpuDmaAllocResp; + T3_32BIT_REGISTER TxCpuDmaAllocReq; + T3_32BIT_REGISTER TxCpuDmaAllocResp; + + T3_32BIT_REGISTER Hwdiag[3]; + + /* Unused space. */ + LM_UINT8 Unused[936]; +} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; + + +/******************************************************************************/ +/* Read DMA control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define DMA_READ_MODE_RESET BIT_0 + #define DMA_READ_MODE_ENABLE BIT_1 + #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 + #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 + #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 + #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 + #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 + #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 + #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 + #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 + #define DMA_READ_MODE_SPLIT_ENABLE BIT_11 + #define DMA_READ_MODE_SPLIT_RESET BIT_12 + + T3_32BIT_REGISTER Status; + #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 + #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 + #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 + #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 + #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 + #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 + #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 + #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 + + /* Unused space. */ + LM_UINT8 Unused[1016]; +} T3_DMA_READ, *PT3_DMA_READ; + +typedef union T3_CPU +{ + struct + { + T3_32BIT_REGISTER mode; + #define CPU_MODE_HALT BIT_10 + #define CPU_MODE_RESET BIT_0 + T3_32BIT_REGISTER state; + T3_32BIT_REGISTER EventMask; + T3_32BIT_REGISTER reserved1[4]; + T3_32BIT_REGISTER PC; + T3_32BIT_REGISTER Instruction; + T3_32BIT_REGISTER SpadUnderflow; + T3_32BIT_REGISTER WatchdogClear; + T3_32BIT_REGISTER WatchdogVector; + T3_32BIT_REGISTER WatchdogSavedPC; + T3_32BIT_REGISTER HardwareBp; + T3_32BIT_REGISTER reserved2[3]; + T3_32BIT_REGISTER WatchdogSavedState; + T3_32BIT_REGISTER LastBrchAddr; + T3_32BIT_REGISTER SpadUnderflowSet; + T3_32BIT_REGISTER reserved3[(0x200-0x50)/4]; + T3_32BIT_REGISTER Regs[32]; + T3_32BIT_REGISTER reserved4[(0x400-0x280)/4]; + }reg; +}T3_CPU, *PT3_CPU; + +/******************************************************************************/ +/* Write DMA control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define DMA_WRITE_MODE_RESET BIT_0 + #define DMA_WRITE_MODE_ENABLE BIT_1 + #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 + #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 + #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 + #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 + #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 + #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 + #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 + #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 + + T3_32BIT_REGISTER Status; + #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 + #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 + #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 + #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 + #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 + #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 + #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 + #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 + + /* Unused space. */ + LM_UINT8 Unused[1016]; +} T3_DMA_WRITE, *PT3_DMA_WRITE; + + +/******************************************************************************/ +/* Mailbox registers. */ +/******************************************************************************/ + +typedef struct { + /* Interrupt mailbox registers. */ + T3_64BIT_REGISTER Interrupt[4]; + + /* General mailbox registers. */ + T3_64BIT_REGISTER General[8]; + + /* Reload statistics mailbox. */ + T3_64BIT_REGISTER ReloadStat; + + /* Receive BD ring producer index registers. */ + T3_64BIT_REGISTER RcvStdProdIdx; + T3_64BIT_REGISTER RcvJumboProdIdx; + T3_64BIT_REGISTER RcvMiniProdIdx; + + /* Receive return ring consumer index registers. */ + T3_64BIT_REGISTER RcvRetConIdx[16]; + + /* Send BD ring host producer index registers. */ + T3_64BIT_REGISTER SendHostProdIdx[16]; + + /* Send BD ring nic producer index registers. */ + T3_64BIT_REGISTER SendNicProdIdx[16]; +}T3_MAILBOX, *PT3_MAILBOX; + +typedef struct { + T3_MAILBOX Mailbox; + + /* Priority mailbox registers. */ + T3_32BIT_REGISTER HighPriorityEventVector; + T3_32BIT_REGISTER HighPriorityEventMask; + T3_32BIT_REGISTER LowPriorityEventVector; + T3_32BIT_REGISTER LowPriorityEventMask; + + /* Unused space. */ + LM_UINT8 Unused[496]; +} T3_GRC_MAILBOX, *PT3_GRC_MAILBOX; + + +/******************************************************************************/ +/* Flow through queues. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Reset; + + LM_UINT8 Unused[12]; + + T3_32BIT_REGISTER DmaNormalReadFtqCtrl; + T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; + T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaHighReadFtqCtrl; + T3_32BIT_REGISTER DmaHighReadFtqFullCnt; + T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; + T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; + T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; + + T3_32BIT_REGISTER SendBdCompFtqCtrl; + T3_32BIT_REGISTER SendBdCompFtqFullCnt; + T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; + + T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; + T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; + T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; + T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; + T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaHighWriteFtqCtrl; + T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; + T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; + + T3_32BIT_REGISTER SwType1FtqCtrl; + T3_32BIT_REGISTER SwType1FtqFullCnt; + T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SwType1FtqFifoWritePeek; + + T3_32BIT_REGISTER SendDataCompFtqCtrl; + T3_32BIT_REGISTER SendDataCompFtqFullCnt; + T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; + + T3_32BIT_REGISTER HostCoalesceFtqCtrl; + T3_32BIT_REGISTER HostCoalesceFtqFullCnt; + T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; + + T3_32BIT_REGISTER MacTxFtqCtrl; + T3_32BIT_REGISTER MacTxFtqFullCnt; + T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER MacTxFtqFifoWritePeek; + + T3_32BIT_REGISTER MbufClustFreeFtqCtrl; + T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; + T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvBdCompFtqCtrl; + T3_32BIT_REGISTER RcvBdCompFtqFullCnt; + T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvListPlmtFtqCtrl; + T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; + T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvDataCompFtqCtrl; + T3_32BIT_REGISTER RcvDataCompFtqFullCnt; + T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; + + T3_32BIT_REGISTER SwType2FtqCtrl; + T3_32BIT_REGISTER SwType2FtqFullCnt; + T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SwType2FtqFifoWritePeek; + + /* Unused space. */ + LM_UINT8 Unused2[736]; +} T3_FTQ, *PT3_FTQ; + + +/******************************************************************************/ +/* Message signaled interrupt registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; +#define MSI_MODE_RESET BIT_0 +#define MSI_MODE_ENABLE BIT_1 + T3_32BIT_REGISTER Status; + + T3_32BIT_REGISTER MsiFifoAccess; + + /* Unused space. */ + LM_UINT8 Unused[1012]; +} T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT; + + +/******************************************************************************/ +/* DMA Completion registes. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define DMA_COMP_MODE_RESET BIT_0 + #define DMA_COMP_MODE_ENABLE BIT_1 + + /* Unused space. */ + LM_UINT8 Unused[1020]; +} T3_DMA_COMPLETION, *PT3_DMA_COMPLETION; + + +/******************************************************************************/ +/* GRC registers. */ +/******************************************************************************/ + +typedef struct { + /* Mode control register. */ + T3_32BIT_REGISTER Mode; + #define GRC_MODE_UPDATE_ON_COALESCING BIT_0 + #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 + #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 + #define GRC_MODE_BYTE_SWAP_DATA BIT_4 + #define GRC_MODE_WORD_SWAP_DATA BIT_5 + #define GRC_MODE_SPLIT_HEADER_MODE BIT_8 + #define GRC_MODE_NO_FRAME_CRACKING BIT_9 + #define GRC_MODE_INCLUDE_CRC BIT_10 + #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 + #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 + #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 + #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 + #define GRC_MODE_HOST_STACK_UP BIT_16 + #define GRC_MODE_HOST_SEND_BDS BIT_17 + #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 + #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 + #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 + #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 + #define GRC_MODE_INT_ON_MAC_ATTN BIT_26 + #define GRC_MODE_INT_ON_DMA_ATTN BIT_27 + #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 + #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 + #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 + + /* Misc configuration register. */ + T3_32BIT_REGISTER MiscCfg; + #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 + #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe + #define GRC_MISC_BD_ID_MASK 0x0001e000 + #define GRC_MISC_BD_ID_5700 0x0001e000 + #define GRC_MISC_BD_ID_5701 0x00000000 + #define GRC_MISC_BD_ID_5703 0x00000000 + #define GRC_MISC_BD_ID_5703S 0x00002000 + #define GRC_MISC_BD_ID_5702FE 0x00004000 + #define GRC_MISC_BD_ID_5704 0x00000000 + #define GRC_MISC_BD_ID_5704CIOBE 0x00004000 + + /* Miscellaneous local control register. */ + T3_32BIT_REGISTER LocalCtrl; + #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 + #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 + #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 + #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 + #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 + #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 + #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 + #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 + #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 + #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 + #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 + #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 + #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 + #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 + #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 + #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 + + #define GRC_MISC_MEMSIZE_256K 0 + #define GRC_MISC_MEMSIZE_512K (1 << 18) + #define GRC_MISC_MEMSIZE_1024K (2 << 18) + #define GRC_MISC_MEMSIZE_2048K (3 << 18) + #define GRC_MISC_MEMSIZE_4096K (4 << 18) + #define GRC_MISC_MEMSIZE_8192K (5 << 18) + #define GRC_MISC_MEMSIZE_16M (6 << 18) + #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 + + + T3_32BIT_REGISTER Timer; + + T3_32BIT_REGISTER RxCpuEvent; + T3_32BIT_REGISTER RxTimerRef; + T3_32BIT_REGISTER RxCpuSemaphore; + T3_32BIT_REGISTER RemoteRxCpuAttn; + + T3_32BIT_REGISTER TxCpuEvent; + T3_32BIT_REGISTER TxTimerRef; + T3_32BIT_REGISTER TxCpuSemaphore; + T3_32BIT_REGISTER RemoteTxCpuAttn; + + T3_64BIT_REGISTER MemoryPowerUp; + + T3_32BIT_REGISTER EepromAddr; + #define SEEPROM_ADDR_WRITE 0 + #define SEEPROM_ADDR_READ (1 << 31) + #define SEEPROM_ADDR_RW_MASK 0x80000000 + #define SEEPROM_ADDR_COMPLETE (1 << 30) + #define SEEPROM_ADDR_FSM_RESET (1 << 29) + #define SEEPROM_ADDR_DEV_ID(x) (x << 26) + #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 + #define SEEPROM_ADDR_START (1 << 25) + #define SEEPROM_ADDR_CLK_PERD(x) (x << 16) + #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) + #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff + + #define SEEPROM_CLOCK_PERIOD 60 + #define SEEPROM_CHIP_SIZE (64 * 1024) + + T3_32BIT_REGISTER EepromData; + T3_32BIT_REGISTER EepromCtrl; + + T3_32BIT_REGISTER MdiCtrl; + T3_32BIT_REGISTER SepromDelay; + + /* Unused space. */ + LM_UINT8 Unused[948]; +} T3_GRC, *PT3_GRC; + + +/******************************************************************************/ +/* NVRAM control registers. */ +/******************************************************************************/ + +typedef struct +{ + T3_32BIT_REGISTER Cmd; + #define NVRAM_CMD_RESET BIT_0 + #define NVRAM_CMD_DONE BIT_3 + #define NVRAM_CMD_DO_IT BIT_4 + #define NVRAM_CMD_WR BIT_5 + #define NVRAM_CMD_RD BIT_NONE + #define NVRAM_CMD_ERASE BIT_6 + #define NVRAM_CMD_FIRST BIT_7 + #define NVRAM_CMD_LAST BIT_8 + + T3_32BIT_REGISTER Status; + T3_32BIT_REGISTER WriteData; + + T3_32BIT_REGISTER Addr; + #define NVRAM_ADDRESS_MASK 0xffffff + + T3_32BIT_REGISTER ReadData; + + /* Flash config 1 register. */ + T3_32BIT_REGISTER Config1; + #define FLASH_INTERFACE_ENABLE BIT_0 + #define FLASH_SSRAM_BUFFERRED_MODE BIT_1 + #define FLASH_PASS_THRU_MODE BIT_2 + #define FLASH_BIT_BANG_MODE BIT_3 + #define FLASH_COMPAT_BYPASS BIT_31 + + /* Buffered flash (Atmel: AT45DB011B) specific information */ + #define BUFFERED_FLASH_PAGE_POS 9 + #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<pMemView->OffsetName)) + +#define REG_WR(pDevice, OffsetName, Value32) \ + (((OFFSETOF(T3_STD_MEM_MAP, OffsetName) >=0x200 ) && \ + (OFFSETOF(T3_STD_MEM_MAP, OffsetName) <0x400)) || \ + ((pDevice)->EnablePciXFix == FALSE)) ? \ + (void) writel(Value32, &((pDevice)->pMemView->OffsetName)) : \ + LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32) + +#define MB_REG_RD(pDevice, OffsetName) \ + readl(&((pDevice)->pMemView->OffsetName)) + +#define MB_REG_WR(pDevice, OffsetName, Value32) \ + writel(Value32, &((pDevice)->pMemView->OffsetName)) + +#define REG_RD_OFFSET(pDevice, Offset) \ + readl(&((LM_UINT8 *) (pDevice)->pMemView + Offset)) + +#define REG_WR_OFFSET(pDevice, Offset, Value32) \ + (((Offset >=0x200 ) && (Offset < 0x400)) || \ + ((pDevice)->EnablePciXFix == FALSE)) ? \ + (void) writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) : \ + LM_RegWrInd(pDevice, Offset, Value32) + +#define MEM_RD(pDevice, AddrName) \ + LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) +#define MEM_WR(pDevice, AddrName, Value32) \ + LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) + +#define MEM_RD_OFFSET(pDevice, Offset) \ + LM_MemRdInd(pDevice, Offset) +#define MEM_WR_OFFSET(pDevice, Offset, Value32) \ + LM_MemWrInd(pDevice, Offset, Value32) + +#else /* normal target access path below */ + +/* Register access. */ +#define REG_RD(pDevice, OffsetName) \ + readl(&((pDevice)->pMemView->OffsetName)) +#define REG_WR(pDevice, OffsetName, Value32) \ + writel(Value32, &((pDevice)->pMemView->OffsetName)) + +#define REG_RD_OFFSET(pDevice, Offset) \ + readl(((LM_UINT8 *) (pDevice)->pMemView + Offset)) +#define REG_WR_OFFSET(pDevice, Offset, Value32) \ + writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) + + +/* There could be problem access the memory window directly. For now, */ +/* we have to go through the PCI configuration register. */ +#define MEM_RD(pDevice, AddrName) \ + LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) +#define MEM_WR(pDevice, AddrName, Value32) \ + LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) + +#define MEM_RD_OFFSET(pDevice, Offset) \ + LM_MemRdInd(pDevice, Offset) +#define MEM_WR_OFFSET(pDevice, Offset, Value32) \ + LM_MemWrInd(pDevice, Offset, Value32) + +#endif /* PCIX_TARGET_WORKAROUND */ + +#endif /* Jimmy, merging */ + + /* Jimmy...rest of file is new stuff! */ +/******************************************************************************/ +/* NIC register read/write macros. */ +/******************************************************************************/ + +/* MAC register access. */ +LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); +LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, + LM_UINT32 Value32); + +/* MAC memory access. */ +LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); +LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, + LM_UINT32 Value32); + +#define MB_REG_WR(pDevice, OffsetName, Value32) \ + ((pDevice)->UndiFix) ? \ + LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \ + Value32) : \ + (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) + +#define MB_REG_RD(pDevice, OffsetName) \ + (((pDevice)->UndiFix) ? \ + LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \ + __raw_readl(&((pDevice)->pMemView->OffsetName))) + +#define REG_RD(pDevice, OffsetName) \ + (((pDevice)->UndiFix) ? \ + LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \ + __raw_readl(&((pDevice)->pMemView->OffsetName))) + +#if PCIX_TARGET_WORKAROUND + +#define REG_WR(pDevice, OffsetName, Value32) \ + ((pDevice)->EnablePciXFix == FALSE) ? \ + (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) : \ + LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32) + +#else + +#define REG_WR(pDevice, OffsetName, Value32) \ + __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) + +#endif + +#define MEM_RD(pDevice, AddrName) \ + LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) +#define MEM_WR(pDevice, AddrName, Value32) \ + LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) + +#define MEM_RD_OFFSET(pDevice, Offset) \ + LM_MemRdInd(pDevice, Offset) +#define MEM_WR_OFFSET(pDevice, Offset, Value32) \ + LM_MemWrInd(pDevice, Offset, Value32) + +#endif /* TIGON3_H */ diff --git a/drivers/tsec.c b/drivers/tsec.c new file mode 100644 index 0000000..f860dae --- /dev/null +++ b/drivers/tsec.c @@ -0,0 +1,1133 @@ +/* + * tsec.c + * Freescale Three Speed Ethernet Controller driver + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003, Motorola, Inc. + * author Andy Fleming + * + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_TSEC_ENET) +#include "tsec.h" +#include "miiphy.h" + +#define TX_BUF_CNT 2 + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +typedef volatile struct rtxbd { + txbd8_t txbd[TX_BUF_CNT]; + rxbd8_t rxbd[PKTBUFSRX]; +} RTXBD; + +struct tsec_info_struct { + unsigned int phyaddr; + u32 flags; + unsigned int phyregidx; +}; + + +/* The tsec_info structure contains 3 values which the + * driver uses to determine how to operate a given ethernet + * device. For now, the structure is initialized with the + * knowledge that all current implementations have 2 TSEC + * devices, and one FEC. The information needed is: + * phyaddr - The address of the PHY which is attached to + * the given device. + * + * flags - This variable indicates whether the device + * supports gigabit speed ethernet, and whether it should be + * in reduced mode. + * + * phyregidx - This variable specifies which ethernet device + * controls the MII Management registers which are connected + * to the PHY. For 8540/8560, only TSEC1 (index 0) has + * access to the PHYs, so all of the entries have "0". + * + * The values specified in the table are taken from the board's + * config file in include/configs/. When implementing a new + * board with ethernet capability, it is necessary to define: + * TSEC1_PHY_ADDR + * TSEC1_PHYIDX + * TSEC2_PHY_ADDR + * TSEC2_PHYIDX + * + * and for 8560: + * FEC_PHY_ADDR + * FEC_PHYIDX + */ +static struct tsec_info_struct tsec_info[] = { +#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) + {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, +#else + { 0, 0, 0}, +#endif +#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) + {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, +#else + { 0, 0, 0}, +#endif +#ifdef CONFIG_MPC85XX_FEC + {FEC_PHY_ADDR, 0, FEC_PHYIDX}, +#else +# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) + {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, +# else + { 0, 0, 0}, +# endif +# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) + {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX}, +# else + { 0, 0, 0}, +# endif +#endif +}; + +#define MAXCONTROLLERS (4) + +static int relocated = 0; + +static struct tsec_private *privlist[MAXCONTROLLERS]; + +#ifdef __GNUC__ +static RTXBD rtx __attribute__ ((aligned(8))); +#else +#error "rtx must be 64-bit aligned" +#endif + +static int tsec_send(struct eth_device* dev, volatile void *packet, int length); +static int tsec_recv(struct eth_device* dev); +static int tsec_init(struct eth_device* dev, bd_t * bd); +static void tsec_halt(struct eth_device* dev); +static void init_registers(volatile tsec_t *regs); +static void startup_tsec(struct eth_device *dev); +static int init_phy(struct eth_device *dev); +void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); +uint read_phy_reg(struct tsec_private *priv, uint regnum); +struct phy_info * get_phy_info(struct eth_device *dev); +void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); +static void adjust_link(struct eth_device *dev); +static void relocate_cmds(void); +static int tsec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +static int tsec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); + +/* Initialize device structure. Returns success if PHY + * initialization succeeded (i.e. if it recognizes the PHY) + */ +int tsec_initialize(bd_t *bis, int index, char *devname) +{ + struct eth_device* dev; + int i; + struct tsec_private *priv; + + dev = (struct eth_device*) malloc(sizeof *dev); + + if(NULL == dev) + return 0; + + memset(dev, 0, sizeof *dev); + + priv = (struct tsec_private *) malloc(sizeof(*priv)); + + if(NULL == priv) + return 0; + + privlist[index] = priv; + priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE); + priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + + tsec_info[index].phyregidx*TSEC_SIZE); + + priv->phyaddr = tsec_info[index].phyaddr; + priv->flags = tsec_info[index].flags; + + sprintf(dev->name, devname); + dev->iobase = 0; + dev->priv = priv; + dev->init = tsec_init; + dev->halt = tsec_halt; + dev->send = tsec_send; + dev->recv = tsec_recv; + + /* Tell u-boot to get the addr from the env */ + for(i=0;i<6;i++) + dev->enetaddr[i] = 0; + + eth_register(dev); + + + /* Reset the MAC */ + priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; + priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ + && !defined(BITBANGMII) + miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); +#endif + + /* Try to initialize PHY here, and return */ + return init_phy(dev); +} + + +/* Initializes data structures and registers for the controller, + * and brings the interface up. Returns the link status, meaning + * that it returns success if the link is up, failure otherwise. + * This allows u-boot to find the first active controller. */ +int tsec_init(struct eth_device* dev, bd_t * bd) +{ + uint tempval; + char tmpbuf[MAC_ADDR_LEN]; + int i; + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + /* Make sure the controller is stopped */ + tsec_halt(dev); + + /* Init MACCFG2. Defaults to GMII */ + regs->maccfg2 = MACCFG2_INIT_SETTINGS; + + /* Init ECNTRL */ + regs->ecntrl = ECNTRL_INIT_SETTINGS; + + /* Copy the station address into the address registers. + * Backwards, because little endian MACS are dumb */ + for(i=0;ienetaddr[i]; + } + regs->macstnaddr1 = *((uint *)(tmpbuf)); + + tempval = *((uint *)(tmpbuf +4)); + + regs->macstnaddr2 = tempval; + + /* reset the indices to zero */ + rxIdx = 0; + txIdx = 0; + + /* Clear out (for the most part) the other registers */ + init_registers(regs); + + /* Ready the device for tx/rx */ + startup_tsec(dev); + + /* If there's no link, fail */ + return priv->link; + +} + + +/* Write value to the device's PHY through the registers + * specified in priv, modifying the register specified in regnum. + * It will wait for the write to be done (or for a timeout to + * expire) before exiting + */ +void write_phy_reg(struct tsec_private *priv, uint regnum, uint value) +{ + volatile tsec_t *regbase = priv->phyregs; + uint phyid = priv->phyaddr; + int timeout=1000000; + + regbase->miimadd = (phyid << 8) | regnum; + regbase->miimcon = value; + asm("sync"); + + timeout=1000000; + while((regbase->miimind & MIIMIND_BUSY) && timeout--); +} + + +/* Reads register regnum on the device's PHY through the + * registers specified in priv. It lowers and raises the read + * command, and waits for the data to become valid (miimind + * notvalid bit cleared), and the bus to cease activity (miimind + * busy bit cleared), and then returns the value + */ +uint read_phy_reg(struct tsec_private *priv, uint regnum) +{ + uint value; + volatile tsec_t *regbase = priv->phyregs; + uint phyid = priv->phyaddr; + + /* Put the address of the phy, and the register + * number into MIIMADD */ + regbase->miimadd = (phyid << 8) | regnum; + + /* Clear the command register, and wait */ + regbase->miimcom = 0; + asm("sync"); + + /* Initiate a read command, and wait */ + regbase->miimcom = MIIM_READ_COMMAND; + asm("sync"); + + /* Wait for the the indication that the read is done */ + while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))); + + /* Grab the value read from the PHY */ + value = regbase->miimstat; + + return value; +} + + +/* Discover which PHY is attached to the device, and configure it + * properly. If the PHY is not recognized, then return 0 + * (failure). Otherwise, return 1 + */ +static int init_phy(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct phy_info *curphy; + + /* Assign a Physical address to the TBI */ + + { + volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); + regs->tbipa = TBIPA_VALUE; + regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); + regs->tbipa = TBIPA_VALUE; + asm("sync"); + } + + /* Reset MII (due to new addresses) */ + priv->phyregs->miimcfg = MIIMCFG_RESET; + asm("sync"); + priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; + asm("sync"); + while(priv->phyregs->miimind & MIIMIND_BUSY); + + if(0 == relocated) + relocate_cmds(); + + /* Get the cmd structure corresponding to the attached + * PHY */ + curphy = get_phy_info(dev); + + if(NULL == curphy) { + printf("%s: No PHY found\n", dev->name); + + return 0; + } + + priv->phyinfo = curphy; + + phy_run_commands(priv, priv->phyinfo->config); + + return 1; +} + + +/* Returns which value to write to the control register. */ +/* For 10/100, the value is slightly different */ +uint mii_cr_init(uint mii_reg, struct tsec_private *priv) +{ + if(priv->flags & TSEC_GIGABIT) + return MIIM_CONTROL_INIT; + else + return MIIM_CR_INIT; +} + + +/* Parse the status register for link, and then do + * auto-negotiation */ +uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) +{ + /* + * Wait if PHY is capable of autonegotiation and autonegotiation is not complete + */ + mii_reg = read_phy_reg(priv, MIIM_STATUS); + if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + int i = 0; + + puts ("Waiting for PHY auto negotiation to complete"); + while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts (" TIMEOUT !\n"); + priv->link = 0; + break; + } + + if ((i++ % 1000) == 0) { + putc ('.'); + } + udelay (1000); /* 1 ms */ + mii_reg = read_phy_reg(priv, MIIM_STATUS); + } + puts (" done\n"); + priv->link = 1; + udelay (500000); /* another 500 ms (results in faster booting) */ + } else { + priv->link = 1; + } + + return 0; +} + + +/* Parse the 88E1011's status register for speed and duplex + * information */ +uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv) +{ + uint speed; + + mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); + + if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && + (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { + int i = 0; + + puts ("Waiting for PHY realtime link"); + while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && + (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts (" TIMEOUT !\n"); + priv->link = 0; + break; + } + + if ((i++ % 1000) == 0) { + putc ('.'); + } + udelay (1000); /* 1 ms */ + mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); + } + puts (" done\n"); + udelay (500000); /* another 500 ms (results in faster booting) */ + } + + if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED); + + switch(speed) { + case MIIM_88E1011_PHYSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_88E1011_PHYSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + } + + return 0; +} + + +/* Parse the cis8201's status register for speed and duplex + * information */ +uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv) +{ + uint speed; + + if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; + switch(speed) { + case MIIM_CIS8201_AUXCONSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_CIS8201_AUXCONSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + break; + } + + return 0; +} + + +/* Parse the DM9161's status register for speed and duplex + * information */ +uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv) +{ + if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) + priv->speed = 100; + else + priv->speed = 10; + + if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) + priv->duplexity = 1; + else + priv->duplexity = 0; + + return 0; +} + + +/* Hack to write all 4 PHYs with the LED values */ +uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv) +{ + uint phyid; + volatile tsec_t *regbase = priv->phyregs; + int timeout=1000000; + + for(phyid=0;phyid<4;phyid++) { + regbase->miimadd = (phyid << 8) | mii_reg; + regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; + asm("sync"); + + timeout=1000000; + while((regbase->miimind & MIIMIND_BUSY) && timeout--); + } + + return MIIM_CIS8204_SLEDCON_INIT; +} + +uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv) +{ + if (priv->flags & TSEC_REDUCED) + return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; + else + return MIIM_CIS8204_EPHYCON_INIT; +} + +/* Initialized required registers to appropriate values, zeroing + * those we don't care about (unless zero is bad, in which case, + * choose a more appropriate value) */ +static void init_registers(volatile tsec_t *regs) +{ + /* Clear IEVENT */ + regs->ievent = IEVENT_INIT_CLEAR; + + regs->imask = IMASK_INIT_CLEAR; + + regs->hash.iaddr0 = 0; + regs->hash.iaddr1 = 0; + regs->hash.iaddr2 = 0; + regs->hash.iaddr3 = 0; + regs->hash.iaddr4 = 0; + regs->hash.iaddr5 = 0; + regs->hash.iaddr6 = 0; + regs->hash.iaddr7 = 0; + + regs->hash.gaddr0 = 0; + regs->hash.gaddr1 = 0; + regs->hash.gaddr2 = 0; + regs->hash.gaddr3 = 0; + regs->hash.gaddr4 = 0; + regs->hash.gaddr5 = 0; + regs->hash.gaddr6 = 0; + regs->hash.gaddr7 = 0; + + regs->rctrl = 0x00000000; + + /* Init RMON mib registers */ + memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); + + regs->rmon.cam1 = 0xffffffff; + regs->rmon.cam2 = 0xffffffff; + + regs->mrblr = MRBLR_INIT_SETTINGS; + + regs->minflr = MINFLR_INIT_SETTINGS; + + regs->attr = ATTR_INIT_SETTINGS; + regs->attreli = ATTRELI_INIT_SETTINGS; + +} + + +/* Configure maccfg2 based on negotiated speed and duplex + * reported by PHY handling code */ +static void adjust_link(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + if(priv->link) { + if(priv->duplexity != 0) + regs->maccfg2 |= MACCFG2_FULL_DUPLEX; + else + regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); + + switch(priv->speed) { + case 1000: + regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) + | MACCFG2_GMII); + break; + case 100: + case 10: + regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) + | MACCFG2_MII); + + /* If We're in reduced mode, we need + * to say whether we're 10 or 100 MB. + */ + if ((priv->speed == 100) + && (priv->flags & TSEC_REDUCED)) + regs->ecntrl |= ECNTRL_R100; + else + regs->ecntrl &= ~(ECNTRL_R100); + break; + default: + printf("%s: Speed was bad\n", dev->name); + break; + } + + printf("Speed: %d, %s duplex\n", priv->speed, + (priv->duplexity) ? "full" : "half"); + + } else { + printf("%s: No link.\n", dev->name); + } +} + + +/* Set up the buffers and their descriptors, and bring up the + * interface */ +static void startup_tsec(struct eth_device *dev) +{ + int i; + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + /* Point to the buffer descriptors */ + regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); + regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); + + /* Initialize the Rx Buffer descriptors */ + for (i = 0; i < PKTBUFSRX; i++) { + rtx.rxbd[i].status = RXBD_EMPTY; + rtx.rxbd[i].length = 0; + rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i]; + } + rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP; + + /* Initialize the TX Buffer Descriptors */ + for(i=0; iphyinfo->startup); + adjust_link(dev); + + /* Enable Transmit and Receive */ + regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); + + /* Tell the DMA it is clear to go */ + regs->dmactrl |= DMACTRL_INIT_SETTINGS; + regs->tstat = TSTAT_CLEAR_THALT; + regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); +} + +/* This returns the status bits of the device. The return value + * is never checked, and this is what the 8260 driver did, so we + * do the same. Presumably, this would be zero if there were no + * errors */ +static int tsec_send(struct eth_device* dev, volatile void *packet, int length) +{ + int i; + int result = 0; + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + /* Find an empty buffer descriptor */ + for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + if (i >= TOUT_LOOP) { + debug ("%s: tsec: tx buffers full\n", dev->name); + return result; + } + } + + rtx.txbd[txIdx].bufPtr = (uint)packet; + rtx.txbd[txIdx].length = length; + rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); + + /* Tell the DMA to go */ + regs->tstat = TSTAT_CLEAR_THALT; + + /* Wait for buffer to be transmitted */ + for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + if (i >= TOUT_LOOP) { + debug ("%s: tsec: tx error\n", dev->name); + return result; + } + } + + txIdx = (txIdx + 1) % TX_BUF_CNT; + result = rtx.txbd[txIdx].status & TXBD_STATS; + + return result; +} + +static int tsec_recv(struct eth_device* dev) +{ + int length; + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { + + length = rtx.rxbd[rxIdx].length; + + /* Send the packet up if there were no errors */ + if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { + NetReceive(NetRxPackets[rxIdx], length - 4); + } else { + printf("Got error %x\n", + (rtx.rxbd[rxIdx].status & RXBD_STATS)); + } + + rtx.rxbd[rxIdx].length = 0; + + /* Set the wrap bit if this is the last element in the list */ + rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + + rxIdx = (rxIdx + 1) % PKTBUFSRX; + } + + if(regs->ievent&IEVENT_BSY) { + regs->ievent = IEVENT_BSY; + regs->rstat = RSTAT_CLEAR_RHALT; + } + + return -1; + +} + + +/* Stop the interface */ +static void tsec_halt(struct eth_device* dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); + regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); + + while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))); + + regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); + + /* Shut down the PHY, as needed */ + phy_run_commands(priv, priv->phyinfo->shutdown); +} + + +struct phy_info phy_info_M88E1011S = { + 0x01410c6, + "Marvell 88E1011S", + 4, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +struct phy_info phy_info_M88E1111S = { + 0x01410cc, + "Marvell 88E1111S", + 4, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +struct phy_info phy_info_cis8204 = { + 0x3f11, + "Cicada Cis8204", + 6, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled}, + {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +/* Cicada 8201 */ +struct phy_info phy_info_cis8201 = { + 0xfc41, + "CIS8201", + 4, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Set up the interface mode */ + {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + + +struct phy_info phy_info_dm9161 = { + 0x0181b88, + "Davicom DM9161E", + 4, + (struct phy_cmd[]) { /* config */ + {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, + /* Do not bypass the scrambler/descrambler */ + {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, + /* Clear 10BTCSR to default */ + {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CR_INIT, NULL}, + /* Restart Auto Negotiation */ + {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) +{ + unsigned int speed; + if (priv->link) { + speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; + + switch (speed) { + case MIIM_LXT971_SR2_10HDX: + priv->speed = 10; + priv->duplexity = 0; + break; + case MIIM_LXT971_SR2_10FDX: + priv->speed = 10; + priv->duplexity = 1; + break; + case MIIM_LXT971_SR2_100HDX: + priv->speed = 100; + priv->duplexity = 0; + default: + priv->speed = 100; + priv->duplexity = 1; + break; + } + } else { + priv->speed = 0; + priv->duplexity = 0; + } + + return 0; +} + +static struct phy_info phy_info_lxt971 = { + 0x0001378e, + "LXT971", + 4, + (struct phy_cmd []) { /* config */ + { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */ + { miim_end, } + }, + (struct phy_cmd []) { /* startup - enable interrupts */ + /* { 0x12, 0x00f2, NULL }, */ + { MIIM_STATUS, miim_read, NULL }, + { MIIM_STATUS, miim_read, &mii_parse_sr }, + { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 }, + { miim_end, } + }, + (struct phy_cmd []) { /* shutdown - disable interrupts */ + { miim_end, } + }, +}; + +struct phy_info *phy_info[] = { +#if 0 + &phy_info_cis8201, +#endif + &phy_info_cis8204, + &phy_info_M88E1011S, + &phy_info_M88E1111S, + &phy_info_dm9161, + &phy_info_lxt971, + NULL +}; + + +/* Grab the identifier of the device's PHY, and search through + * all of the known PHYs to see if one matches. If so, return + * it, if not, return NULL */ +struct phy_info * get_phy_info(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + uint phy_reg, phy_ID; + int i; + struct phy_info *theInfo = NULL; + + /* Grab the bits from PHYIR1, and put them in the upper half */ + phy_reg = read_phy_reg(priv, MIIM_PHYIR1); + phy_ID = (phy_reg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phy_reg = read_phy_reg(priv, MIIM_PHYIR2); + phy_ID |= (phy_reg & 0xffff); + + /* loop through all the known PHY types, and find one that */ + /* matches the ID we read from the PHY. */ + for(i=0; phy_info[i]; i++) { + if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) + theInfo = phy_info[i]; + } + + if(theInfo == NULL) + { + printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); + return NULL; + } else { + debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); + } + + return theInfo; +} + + +/* Execute the given series of commands on the given device's + * PHY, running functions as necessary*/ +void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) +{ + int i; + uint result; + volatile tsec_t *phyregs = priv->phyregs; + + phyregs->miimcfg = MIIMCFG_RESET; + + phyregs->miimcfg = MIIMCFG_INIT_VALUE; + + while(phyregs->miimind & MIIMIND_BUSY); + + for(i=0;cmd->mii_reg != miim_end;i++) { + if(cmd->mii_data == miim_read) { + result = read_phy_reg(priv, cmd->mii_reg); + + if(cmd->funct != NULL) + (*(cmd->funct))(result, priv); + + } else { + if(cmd->funct != NULL) + result = (*(cmd->funct))(cmd->mii_reg, priv); + else + result = cmd->mii_data; + + write_phy_reg(priv, cmd->mii_reg, result); + + } + cmd++; + } +} + + +/* Relocate the function pointers in the phy cmd lists */ +static void relocate_cmds(void) +{ + struct phy_cmd **cmdlistptr; + struct phy_cmd *cmd; + int i,j,k; + DECLARE_GLOBAL_DATA_PTR; + + for(i=0; phy_info[i]; i++) { + /* First thing's first: relocate the pointers to the + * PHY command structures (the structs were done) */ + phy_info[i] = (struct phy_info *) ((uint)phy_info[i] + + gd->reloc_off); + phy_info[i]->name += gd->reloc_off; + phy_info[i]->config = + (struct phy_cmd *)((uint)phy_info[i]->config + + gd->reloc_off); + phy_info[i]->startup = + (struct phy_cmd *)((uint)phy_info[i]->startup + + gd->reloc_off); + phy_info[i]->shutdown = + (struct phy_cmd *)((uint)phy_info[i]->shutdown + + gd->reloc_off); + + cmdlistptr = &phy_info[i]->config; + j=0; + for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) { + k=0; + for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) { + /* Only relocate non-NULL pointers */ + if(cmd->funct) + cmd->funct += gd->reloc_off; + + k++; + } + j++; + } + } + + relocated = 1; +} + + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ + && !defined(BITBANGMII) + +struct tsec_private * get_priv_for_phy(unsigned char phyaddr) +{ + int i; + + for(i=0;iphyaddr == phyaddr) + return privlist[i]; + } + + return NULL; +} + +/* + * Read a MII PHY register. + * + * Returns: + * 0 on success + */ +static int tsec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + unsigned short ret; + struct tsec_private *priv = get_priv_for_phy(addr); + + if(NULL == priv) { + printf("Can't read PHY at address %d\n", addr); + return -1; + } + + ret = (unsigned short)read_phy_reg(priv, reg); + *value = ret; + + return 0; +} + +/* + * Write a MII PHY register. + * + * Returns: + * 0 on success + */ +static int tsec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct tsec_private *priv = get_priv_for_phy(addr); + + if(NULL == priv) { + printf("Can't write PHY at address %d\n", addr); + return -1; + } + + write_phy_reg(priv, reg, value); + + return 0; +} + +#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + && !defined(BITBANGMII) */ + +#endif /* CONFIG_TSEC_ENET */ diff --git a/drivers/tsec.h b/drivers/tsec.h new file mode 100644 index 0000000..c26fcc0 --- /dev/null +++ b/drivers/tsec.h @@ -0,0 +1,510 @@ +/* + * tsec.h + * + * Driver for the Motorola Triple Speed Ethernet Controller + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003, Motorola, Inc. + * maintained by Xianghua Xiao (x.xiao@motorola.com) + * author Andy Fleming + * + */ + +#ifndef __TSEC_H +#define __TSEC_H + +#include +#include + +#ifndef CFG_TSEC1_OFFSET + #define CFG_TSEC1_OFFSET (0x24000) +#endif + +#define TSEC_SIZE 0x01000 + +/* FIXME: Should these be pushed back to 83xx and 85xx config files? */ +#if defined(CONFIG_MPC85xx) + #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) +#elif defined(CONFIG_MPC83XX) + #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET) +#endif + + +#define MAC_ADDR_LEN 6 + +/* #define TSEC_TIMEOUT 1000000 */ +#define TSEC_TIMEOUT 1000 +#define TOUT_LOOP 1000000 + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ + +/* MAC register bits */ +#define MACCFG1_SOFT_RESET 0x80000000 +#define MACCFG1_RESET_RX_MC 0x00080000 +#define MACCFG1_RESET_TX_MC 0x00040000 +#define MACCFG1_RESET_RX_FUN 0x00020000 +#define MACCFG1_RESET_TX_FUN 0x00010000 +#define MACCFG1_LOOPBACK 0x00000100 +#define MACCFG1_RX_FLOW 0x00000020 +#define MACCFG1_TX_FLOW 0x00000010 +#define MACCFG1_SYNCD_RX_EN 0x00000008 +#define MACCFG1_RX_EN 0x00000004 +#define MACCFG1_SYNCD_TX_EN 0x00000002 +#define MACCFG1_TX_EN 0x00000001 + +#define MACCFG2_INIT_SETTINGS 0x00007205 +#define MACCFG2_FULL_DUPLEX 0x00000001 +#define MACCFG2_IF 0x00000300 +#define MACCFG2_GMII 0x00000200 +#define MACCFG2_MII 0x00000100 + +#define ECNTRL_INIT_SETTINGS 0x00001000 +#define ECNTRL_TBI_MODE 0x00000020 +#define ECNTRL_R100 0x00000008 + +#define miim_end -2 +#define miim_read -1 + +#define TBIPA_VALUE 0x1f +#define MIIMCFG_INIT_VALUE 0x00000003 +#define MIIMCFG_RESET 0x80000000 + +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 + +#define MIIM_CONTROL 0x00 +#define MIIM_CONTROL_RESET 0x00009140 +#define MIIM_CONTROL_INIT 0x00001140 +#define MIIM_CONTROL_RESTART 0x00001340 +#define MIIM_ANEN 0x00001000 + +#define MIIM_CR 0x00 +#define MIIM_CR_RST 0x00008000 +#define MIIM_CR_INIT 0x00001000 + +#define MIIM_STATUS 0x1 +#define MIIM_STATUS_AN_DONE 0x00000020 +#define MIIM_STATUS_LINK 0x0004 +#define PHY_BMSR_AUTN_ABLE 0x0008 +#define PHY_BMSR_AUTN_COMP 0x0020 + +#define MIIM_PHYIR1 0x2 +#define MIIM_PHYIR2 0x3 + +#define MIIM_ANAR 0x4 +#define MIIM_ANAR_INIT 0x1e1 + +#define MIIM_TBI_ANLPBPA 0x5 +#define MIIM_TBI_ANLPBPA_HALF 0x00000040 +#define MIIM_TBI_ANLPBPA_FULL 0x00000020 + +#define MIIM_TBI_ANEX 0x6 +#define MIIM_TBI_ANEX_NP 0x00000004 +#define MIIM_TBI_ANEX_PRX 0x00000002 + +#define MIIM_GBIT_CONTROL 0x9 +#define MIIM_GBIT_CONTROL_INIT 0xe00 + +/* Cicada Auxiliary Control/Status Register */ +#define MIIM_CIS8201_AUX_CONSTAT 0x1c +#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 +#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 +#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 +#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 +#define MIIM_CIS8201_AUXCONSTAT_100 0x0008 + +/* Cicada Extended Control Register 1 */ +#define MIIM_CIS8201_EXT_CON1 0x17 +#define MIIM_CIS8201_EXTCON1_INIT 0x0000 + +/* Cicada 8204 Extended PHY Control Register 1 */ +#define MIIM_CIS8204_EPHY_CON 0x17 +#define MIIM_CIS8204_EPHYCON_INIT 0x0006 +#define MIIM_CIS8204_EPHYCON_RGMII 0x1000 + +/* Cicada 8204 Serial LED Control Register */ +#define MIIM_CIS8204_SLED_CON 0x1b +#define MIIM_CIS8204_SLEDCON_INIT 0x1115 + +#define MIIM_GBIT_CON 0x09 +#define MIIM_GBIT_CON_ADVERT 0x0e00 + +/* 88E1011 PHY Status Register */ +#define MIIM_88E1011_PHY_STATUS 0x11 +#define MIIM_88E1011_PHYSTAT_SPEED 0xc000 +#define MIIM_88E1011_PHYSTAT_GBIT 0x8000 +#define MIIM_88E1011_PHYSTAT_100 0x4000 +#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 +#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 +#define MIIM_88E1011_PHYSTAT_LINK 0x0400 + +/* DM9161 Control register values */ +#define MIIM_DM9161_CR_STOP 0x0400 +#define MIIM_DM9161_CR_RSTAN 0x1200 + +#define MIIM_DM9161_SCR 0x10 +#define MIIM_DM9161_SCR_INIT 0x0610 + +/* DM9161 Specified Configuration and Status Register */ +#define MIIM_DM9161_SCSR 0x11 +#define MIIM_DM9161_SCSR_100F 0x8000 +#define MIIM_DM9161_SCSR_100H 0x4000 +#define MIIM_DM9161_SCSR_10F 0x2000 +#define MIIM_DM9161_SCSR_10H 0x1000 + +/* DM9161 10BT Configuration/Status */ +#define MIIM_DM9161_10BTCSR 0x12 +#define MIIM_DM9161_10BTCSR_INIT 0x7800 + +/* LXT971 Status 2 registers */ +#define MIIM_LXT971_SR2 17 /* Status Register 2 */ +#define MIIM_LXT971_SR2_SPEED_MASK 0xf000 +#define MIIM_LXT971_SR2_10HDX 0x1000 /* 10 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_10FDX 0x2000 /* 10 Mbit full duplex selected */ +#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_100FDX 0x8000 /* 100 Mbit full duplex selected */ + +#define MIIM_READ_COMMAND 0x00000001 + +#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN + +#define MINFLR_INIT_SETTINGS 0x00000040 + +#define DMACTRL_INIT_SETTINGS 0x000000c3 +#define DMACTRL_GRS 0x00000010 +#define DMACTRL_GTS 0x00000008 + +#define TSTAT_CLEAR_THALT 0x80000000 +#define RSTAT_CLEAR_RHALT 0x00800000 + + +#define IEVENT_INIT_CLEAR 0xffffffff +#define IEVENT_BABR 0x80000000 +#define IEVENT_RXC 0x40000000 +#define IEVENT_BSY 0x20000000 +#define IEVENT_EBERR 0x10000000 +#define IEVENT_MSRO 0x04000000 +#define IEVENT_GTSC 0x02000000 +#define IEVENT_BABT 0x01000000 +#define IEVENT_TXC 0x00800000 +#define IEVENT_TXE 0x00400000 +#define IEVENT_TXB 0x00200000 +#define IEVENT_TXF 0x00100000 +#define IEVENT_IE 0x00080000 +#define IEVENT_LC 0x00040000 +#define IEVENT_CRL 0x00020000 +#define IEVENT_XFUN 0x00010000 +#define IEVENT_RXB0 0x00008000 +#define IEVENT_GRSC 0x00000100 +#define IEVENT_RXF0 0x00000080 + +#define IMASK_INIT_CLEAR 0x00000000 +#define IMASK_TXEEN 0x00400000 +#define IMASK_TXBEN 0x00200000 +#define IMASK_TXFEN 0x00100000 +#define IMASK_RXFEN0 0x00000080 + + +/* Default Attribute fields */ +#define ATTR_INIT_SETTINGS 0x000000c0 +#define ATTRELI_INIT_SETTINGS 0x00000000 + + +/* TxBD status field bits */ +#define TXBD_READY 0x8000 +#define TXBD_PADCRC 0x4000 +#define TXBD_WRAP 0x2000 +#define TXBD_INTERRUPT 0x1000 +#define TXBD_LAST 0x0800 +#define TXBD_CRC 0x0400 +#define TXBD_DEF 0x0200 +#define TXBD_HUGEFRAME 0x0080 +#define TXBD_LATECOLLISION 0x0080 +#define TXBD_RETRYLIMIT 0x0040 +#define TXBD_RETRYCOUNTMASK 0x003c +#define TXBD_UNDERRUN 0x0002 +#define TXBD_STATS 0x03ff + +/* RxBD status field bits */ +#define RXBD_EMPTY 0x8000 +#define RXBD_RO1 0x4000 +#define RXBD_WRAP 0x2000 +#define RXBD_INTERRUPT 0x1000 +#define RXBD_LAST 0x0800 +#define RXBD_FIRST 0x0400 +#define RXBD_MISS 0x0100 +#define RXBD_BROADCAST 0x0080 +#define RXBD_MULTICAST 0x0040 +#define RXBD_LARGE 0x0020 +#define RXBD_NONOCTET 0x0010 +#define RXBD_SHORT 0x0008 +#define RXBD_CRCERR 0x0004 +#define RXBD_OVERRUN 0x0002 +#define RXBD_TRUNCATED 0x0001 +#define RXBD_STATS 0x003f + +typedef struct txbd8 +{ + ushort status; /* Status Fields */ + ushort length; /* Buffer length */ + uint bufPtr; /* Buffer Pointer */ +} txbd8_t; + +typedef struct rxbd8 +{ + ushort status; /* Status Fields */ + ushort length; /* Buffer Length */ + uint bufPtr; /* Buffer Pointer */ +} rxbd8_t; + +typedef struct rmon_mib +{ + /* Transmit and Receive Counters */ + uint tr64; /* Transmit and Receive 64-byte Frame Counter */ + uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ + uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ + uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ + uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ + uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ + uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ + /* Receive Counters */ + uint rbyt; /* Receive Byte Counter */ + uint rpkt; /* Receive Packet Counter */ + uint rfcs; /* Receive FCS Error Counter */ + uint rmca; /* Receive Multicast Packet (Counter) */ + uint rbca; /* Receive Broadcast Packet */ + uint rxcf; /* Receive Control Frame Packet */ + uint rxpf; /* Receive Pause Frame Packet */ + uint rxuo; /* Receive Unknown OP Code */ + uint raln; /* Receive Alignment Error */ + uint rflr; /* Receive Frame Length Error */ + uint rcde; /* Receive Code Error */ + uint rcse; /* Receive Carrier Sense Error */ + uint rund; /* Receive Undersize Packet */ + uint rovr; /* Receive Oversize Packet */ + uint rfrg; /* Receive Fragments */ + uint rjbr; /* Receive Jabber */ + uint rdrp; /* Receive Drop */ + /* Transmit Counters */ + uint tbyt; /* Transmit Byte Counter */ + uint tpkt; /* Transmit Packet */ + uint tmca; /* Transmit Multicast Packet */ + uint tbca; /* Transmit Broadcast Packet */ + uint txpf; /* Transmit Pause Control Frame */ + uint tdfr; /* Transmit Deferral Packet */ + uint tedf; /* Transmit Excessive Deferral Packet */ + uint tscl; /* Transmit Single Collision Packet */ + /* (0x2_n700) */ + uint tmcl; /* Transmit Multiple Collision Packet */ + uint tlcl; /* Transmit Late Collision Packet */ + uint txcl; /* Transmit Excessive Collision Packet */ + uint tncl; /* Transmit Total Collision */ + + uint res2; + + uint tdrp; /* Transmit Drop Frame */ + uint tjbr; /* Transmit Jabber Frame */ + uint tfcs; /* Transmit FCS Error */ + uint txcf; /* Transmit Control Frame */ + uint tovr; /* Transmit Oversize Frame */ + uint tund; /* Transmit Undersize Frame */ + uint tfrg; /* Transmit Fragments Frame */ + /* General Registers */ + uint car1; /* Carry Register One */ + uint car2; /* Carry Register Two */ + uint cam1; /* Carry Register One Mask */ + uint cam2; /* Carry Register Two Mask */ +} rmon_mib_t; + +typedef struct tsec_hash_regs +{ + uint iaddr0; /* Individual Address Register 0 */ + uint iaddr1; /* Individual Address Register 1 */ + uint iaddr2; /* Individual Address Register 2 */ + uint iaddr3; /* Individual Address Register 3 */ + uint iaddr4; /* Individual Address Register 4 */ + uint iaddr5; /* Individual Address Register 5 */ + uint iaddr6; /* Individual Address Register 6 */ + uint iaddr7; /* Individual Address Register 7 */ + uint res1[24]; + uint gaddr0; /* Group Address Register 0 */ + uint gaddr1; /* Group Address Register 1 */ + uint gaddr2; /* Group Address Register 2 */ + uint gaddr3; /* Group Address Register 3 */ + uint gaddr4; /* Group Address Register 4 */ + uint gaddr5; /* Group Address Register 5 */ + uint gaddr6; /* Group Address Register 6 */ + uint gaddr7; /* Group Address Register 7 */ + uint res2[24]; +} tsec_hash_t; + +typedef struct tsec +{ + /* General Control and Status Registers (0x2_n000) */ + uint res000[4]; + + uint ievent; /* Interrupt Event */ + uint imask; /* Interrupt Mask */ + uint edis; /* Error Disabled */ + uint res01c; + uint ecntrl; /* Ethernet Control */ + uint minflr; /* Minimum Frame Length */ + uint ptv; /* Pause Time Value */ + uint dmactrl; /* DMA Control */ + uint tbipa; /* TBI PHY Address */ + + uint res034[3]; + uint res040[48]; + + /* Transmit Control and Status Registers (0x2_n100) */ + uint tctrl; /* Transmit Control */ + uint tstat; /* Transmit Status */ + uint res108; + uint tbdlen; /* Tx BD Data Length */ + uint res110[5]; + uint ctbptr; /* Current TxBD Pointer */ + uint res128[23]; + uint tbptr; /* TxBD Pointer */ + uint res188[30]; + /* (0x2_n200) */ + uint res200; + uint tbase; /* TxBD Base Address */ + uint res208[42]; + uint ostbd; /* Out of Sequence TxBD */ + uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ + uint res2b8[18]; + + /* Receive Control and Status Registers (0x2_n300) */ + uint rctrl; /* Receive Control */ + uint rstat; /* Receive Status */ + uint res308; + uint rbdlen; /* RxBD Data Length */ + uint res310[4]; + uint res320; + uint crbptr; /* Current Receive Buffer Pointer */ + uint res328[6]; + uint mrblr; /* Maximum Receive Buffer Length */ + uint res344[16]; + uint rbptr; /* RxBD Pointer */ + uint res388[30]; + /* (0x2_n400) */ + uint res400; + uint rbase; /* RxBD Base Address */ + uint res408[62]; + + /* MAC Registers (0x2_n500) */ + uint maccfg1; /* MAC Configuration #1 */ + uint maccfg2; /* MAC Configuration #2 */ + uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ + uint hafdup; /* Half-duplex */ + uint maxfrm; /* Maximum Frame */ + uint res514; + uint res518; + + uint res51c; + + uint miimcfg; /* MII Management: Configuration */ + uint miimcom; /* MII Management: Command */ + uint miimadd; /* MII Management: Address */ + uint miimcon; /* MII Management: Control */ + uint miimstat; /* MII Management: Status */ + uint miimind; /* MII Management: Indicators */ + + uint res538; + + uint ifstat; /* Interface Status */ + uint macstnaddr1; /* Station Address, part 1 */ + uint macstnaddr2; /* Station Address, part 2 */ + uint res548[46]; + + /* (0x2_n600) */ + uint res600[32]; + + /* RMON MIB Registers (0x2_n680-0x2_n73c) */ + rmon_mib_t rmon; + uint res740[48]; + + /* Hash Function Registers (0x2_n800) */ + tsec_hash_t hash; + + uint res900[128]; + + /* Pattern Registers (0x2_nb00) */ + uint resb00[62]; + uint attr; /* Default Attribute Register */ + uint attreli; /* Default Attribute Extract Length and Index */ + + /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ + uint resc00[256]; +} tsec_t; + +#define TSEC_GIGABIT (1) + +/* This flag currently only has + * meaning if we're using the eTSEC */ +#define TSEC_REDUCED (1 << 1) + +struct tsec_private { + volatile tsec_t *regs; + volatile tsec_t *phyregs; + struct phy_info *phyinfo; + uint phyaddr; + u32 flags; + uint link; + uint duplexity; + uint speed; +}; + + +/* + * struct phy_cmd: A command for reading or writing a PHY register + * + * mii_reg: The register to read or write + * + * mii_data: For writes, the value to put in the register. + * A value of -1 indicates this is a read. + * + * funct: A function pointer which is invoked for each command. + * For reads, this function will be passed the value read + * from the PHY, and process it. + * For writes, the result of this function will be written + * to the PHY register + */ +struct phy_cmd { + uint mii_reg; + uint mii_data; + uint (*funct) (uint mii_reg, struct tsec_private* priv); +}; + +/* struct phy_info: a structure which defines attributes for a PHY + * + * id will contain a number which represents the PHY. During + * startup, the driver will poll the PHY to find out what its + * UID--as defined by registers 2 and 3--is. The 32-bit result + * gotten from the PHY will be shifted right by "shift" bits to + * discard any bits which may change based on revision numbers + * unimportant to functionality + * + * The struct phy_cmd entries represent pointers to an arrays of + * commands which tell the driver what to do to the PHY. + */ +struct phy_info { + uint id; + char *name; + uint shift; + /* Called to configure the PHY, and modify the controller + * based on the results */ + struct phy_cmd *config; + + /* Called when starting up the controller */ + struct phy_cmd *startup; + + /* Called when bringing down the controller */ + struct phy_cmd *shutdown; +}; + +#endif /* __TSEC_H */ diff --git a/drivers/usbdcore.c b/drivers/usbdcore.c new file mode 100644 index 0000000..308c7ce --- /dev/null +++ b/drivers/usbdcore.c @@ -0,0 +1,684 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usbd/usbd.c.c - USB Device Core Layer + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include "usbdcore.h" + +#define MAX_INTERFACES 2 + + +int maxstrings = 20; + +/* Global variables ************************************************************************** */ + +struct usb_string_descriptor **usb_strings; + +int usb_devices; + +extern struct usb_function_driver ep0_driver; + +int registered_functions; +int registered_devices; + +char *usbd_device_events[] = { + "DEVICE_UNKNOWN", + "DEVICE_INIT", + "DEVICE_CREATE", + "DEVICE_HUB_CONFIGURED", + "DEVICE_RESET", + "DEVICE_ADDRESS_ASSIGNED", + "DEVICE_CONFIGURED", + "DEVICE_SET_INTERFACE", + "DEVICE_SET_FEATURE", + "DEVICE_CLEAR_FEATURE", + "DEVICE_DE_CONFIGURED", + "DEVICE_BUS_INACTIVE", + "DEVICE_BUS_ACTIVITY", + "DEVICE_POWER_INTERRUPTION", + "DEVICE_HUB_RESET", + "DEVICE_DESTROY", + "DEVICE_FUNCTION_PRIVATE", +}; + +char *usbd_device_states[] = { + "STATE_INIT", + "STATE_CREATED", + "STATE_ATTACHED", + "STATE_POWERED", + "STATE_DEFAULT", + "STATE_ADDRESSED", + "STATE_CONFIGURED", + "STATE_UNKNOWN", +}; + +char *usbd_device_requests[] = { + "GET STATUS", /* 0 */ + "CLEAR FEATURE", /* 1 */ + "RESERVED", /* 2 */ + "SET FEATURE", /* 3 */ + "RESERVED", /* 4 */ + "SET ADDRESS", /* 5 */ + "GET DESCRIPTOR", /* 6 */ + "SET DESCRIPTOR", /* 7 */ + "GET CONFIGURATION", /* 8 */ + "SET CONFIGURATION", /* 9 */ + "GET INTERFACE", /* 10 */ + "SET INTERFACE", /* 11 */ + "SYNC FRAME", /* 12 */ +}; + +char *usbd_device_descriptors[] = { + "UNKNOWN", /* 0 */ + "DEVICE", /* 1 */ + "CONFIG", /* 2 */ + "STRING", /* 3 */ + "INTERFACE", /* 4 */ + "ENDPOINT", /* 5 */ + "DEVICE QUALIFIER", /* 6 */ + "OTHER SPEED", /* 7 */ + "INTERFACE POWER", /* 8 */ +}; + +char *usbd_device_status[] = { + "USBD_OPENING", + "USBD_OK", + "USBD_SUSPENDED", + "USBD_CLOSING", +}; + + +/* Descriptor support functions ************************************************************** */ + + +/** + * usbd_get_string - find and return a string descriptor + * @index: string index to return + * + * Find an indexed string and return a pointer to a it. + */ +struct usb_string_descriptor *usbd_get_string (__u8 index) +{ + if (index >= maxstrings) { + return NULL; + } + return usb_strings[index]; +} + + +/* Access to device descriptor functions ***************************************************** */ + + +/* * + * usbd_device_configuration_instance - find a configuration instance for this device + * @device: + * @configuration: index to configuration, 0 - N-1 + * + * Get specifed device configuration. Index should be bConfigurationValue-1. + */ +static struct usb_configuration_instance *usbd_device_configuration_instance (struct usb_device_instance *device, + unsigned int port, unsigned int configuration) +{ + /* XXX */ + configuration = configuration ? configuration - 1 : 0; + + if (configuration >= device->configurations) { + return NULL; + } + return device->configuration_instance_array + configuration; +} + + +/* * + * usbd_device_interface_instance + * @device: + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * + * Return the specified interface descriptor for the specified device. + */ +struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *device, int port, int configuration, int interface) +{ + struct usb_configuration_instance *configuration_instance; + + if ((configuration_instance = usbd_device_configuration_instance (device, port, configuration)) == NULL) { + return NULL; + } + if (interface >= configuration_instance->interfaces) { + return NULL; + } + return configuration_instance->interface_instance_array + interface; +} + +/* * + * usbd_device_alternate_descriptor_list + * @device: + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: alternate setting + * + * Return the specified alternate descriptor for the specified device. + */ +struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *device, int port, int configuration, int interface, int alternate) +{ + struct usb_interface_instance *interface_instance; + + if ((interface_instance = usbd_device_interface_instance (device, port, configuration, interface)) == NULL) { + return NULL; + } + + if (alternate >= interface_instance->alternates) { + return NULL; + } + + return interface_instance->alternates_instance_array + alternate; +} + + +/* * + * usbd_device_device_descriptor + * @device: which device + * @configuration: index to configuration, 0 - N-1 + * @port: which port + * + * Return the specified configuration descriptor for the specified device. + */ +struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *device, int port) +{ + return (device->device_descriptor); +} + + +/** + * usbd_device_configuration_descriptor + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * + * Return the specified configuration descriptor for the specified device. + */ +struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct + usb_device_instance + *device, int port, int configuration) +{ + struct usb_configuration_instance *configuration_instance; + if (!(configuration_instance = usbd_device_configuration_instance (device, port, configuration))) { + return NULL; + } + return (configuration_instance->configuration_descriptor); +} + + +/** + * usbd_device_interface_descriptor + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: alternate setting + * + * Return the specified interface descriptor for the specified device. + */ +struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance + *device, int port, int configuration, int interface, int alternate) +{ + struct usb_interface_instance *interface_instance; + if (!(interface_instance = usbd_device_interface_instance (device, port, configuration, interface))) { + return NULL; + } + if ((alternate < 0) || (alternate >= interface_instance->alternates)) { + return NULL; + } + return (interface_instance->alternates_instance_array[alternate].interface_descriptor); +} + +/** + * usbd_device_endpoint_descriptor_index + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: index setting + * @index: which index + * + * Return the specified endpoint descriptor for the specified device. + */ +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance + *device, int port, int configuration, int interface, int alternate, int index) +{ + struct usb_alternate_instance *alternate_instance; + + if (!(alternate_instance = usbd_device_alternate_instance (device, port, configuration, interface, alternate))) { + return NULL; + } + if (index >= alternate_instance->endpoints) { + return NULL; + } + return *(alternate_instance->endpoints_descriptor_array + index); +} + + +/** + * usbd_device_endpoint_transfersize + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @index: which index + * + * Return the specified endpoint transfer size; + */ +int usbd_device_endpoint_transfersize (struct usb_device_instance *device, int port, int configuration, int interface, int alternate, int index) +{ + struct usb_alternate_instance *alternate_instance; + + if (!(alternate_instance = usbd_device_alternate_instance (device, port, configuration, interface, alternate))) { + return 0; + } + if (index >= alternate_instance->endpoints) { + return 0; + } + return *(alternate_instance->endpoint_transfersize_array + index); +} + + +/** + * usbd_device_endpoint_descriptor + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: alternate setting + * @endpoint: which endpoint + * + * Return the specified endpoint descriptor for the specified device. + */ +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *device, int port, int configuration, int interface, int alternate, int endpoint) +{ + struct usb_endpoint_descriptor *endpoint_descriptor; + int i; + + for (i = 0; !(endpoint_descriptor = usbd_device_endpoint_descriptor_index (device, port, configuration, interface, alternate, i)); i++) { + if (endpoint_descriptor->bEndpointAddress == endpoint) { + return endpoint_descriptor; + } + } + return NULL; +} + +/** + * usbd_endpoint_halted + * @device: point to struct usb_device_instance + * @endpoint: endpoint to check + * + * Return non-zero if endpoint is halted. + */ +int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint) +{ + return (device->status == USB_STATUS_HALT); +} + + +/** + * usbd_rcv_complete - complete a receive + * @endpoint: + * @len: + * @urb_bad: + * + * Called from rcv interrupt to complete. + */ +void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad) +{ + if (endpoint) { + struct urb *rcv_urb; + + /*usbdbg("len: %d urb: %p\n", len, endpoint->rcv_urb); */ + + /* if we had an urb then update actual_length, dispatch if neccessary */ + if ((rcv_urb = endpoint->rcv_urb)) { + + /*usbdbg("actual: %d buffer: %d\n", */ + /*rcv_urb->actual_length, rcv_urb->buffer_length); */ + + /* check the urb is ok, are we adding data less than the packetsize */ + if (!urb_bad && (len <= endpoint->rcv_packetSize)) { + /*usbdbg("updating actual_length by %d\n",len); */ + + /* increment the received data size */ + rcv_urb->actual_length += len; + + } else { + usberr(" RECV_ERROR actual: %d buffer: %d urb_bad: %d\n", + rcv_urb->actual_length, rcv_urb->buffer_length, urb_bad); + + rcv_urb->actual_length = 0; + rcv_urb->status = RECV_ERROR; + } + } else { + usberr("no rcv_urb!"); + } + } else { + usberr("no endpoint!"); + } + +} + +/** + * usbd_tx_complete - complete a transmit + * @endpoint: + * @resetart: + * + * Called from tx interrupt to complete. + */ +void usbd_tx_complete (struct usb_endpoint_instance *endpoint) +{ + if (endpoint) { + struct urb *tx_urb; + + /* if we have a tx_urb advance or reset, finish if complete */ + if ((tx_urb = endpoint->tx_urb)) { + int sent = endpoint->last; + endpoint->sent += sent; + endpoint->last -= sent; + + if( (endpoint->tx_urb->actual_length - endpoint->sent) <= 0 ) { + tx_urb->actual_length = 0; + endpoint->sent = 0; + endpoint->last = 0; + + /* Remove from active, save for re-use */ + urb_detach(tx_urb); + urb_append(&endpoint->done, tx_urb); + /*usbdbg("done->next %p, tx_urb %p, done %p", */ + /* endpoint->done.next, tx_urb, &endpoint->done); */ + + endpoint->tx_urb = first_urb_detached(&endpoint->tx); + if( endpoint->tx_urb ) { + endpoint->tx_queue--; + usbdbg("got urb from tx list"); + } + if( !endpoint->tx_urb ) { + /*usbdbg("taking urb from done list"); */ + endpoint->tx_urb = first_urb_detached(&endpoint->done); + } + if( !endpoint->tx_urb ) { + usbdbg("allocating new urb for tx_urb"); + endpoint->tx_urb = usbd_alloc_urb(tx_urb->device, endpoint); + } + } + } + } +} + +/* URB linked list functions ***************************************************** */ + +/* + * Initialize an urb_link to be a single element list. + * If the urb_link is being used as a distinguished list head + * the list is empty when the head is the only link in the list. + */ +void urb_link_init (urb_link * ul) +{ + if (ul) { + ul->prev = ul->next = ul; + } +} + +/* + * Detach an urb_link from a list, and set it + * up as a single element list, so no dangling + * pointers can be followed, and so it can be + * joined to another list if so desired. + */ +void urb_detach (struct urb *urb) +{ + if (urb) { + urb_link *ul = &urb->link; + ul->next->prev = ul->prev; + ul->prev->next = ul->next; + urb_link_init (ul); + } +} + +/* + * Return the first urb_link in a list with a distinguished + * head "hd", or NULL if the list is empty. This will also + * work as a predicate, returning NULL if empty, and non-NULL + * otherwise. + */ +urb_link *first_urb_link (urb_link * hd) +{ + urb_link *nx; + if (NULL != hd && NULL != (nx = hd->next) && nx != hd) { + /* There is at least one element in the list */ + /* (besides the distinguished head). */ + return (nx); + } + /* The list is empty */ + return (NULL); +} + +/* + * Return the first urb in a list with a distinguished + * head "hd", or NULL if the list is empty. + */ +struct urb *first_urb (urb_link * hd) +{ + urb_link *nx; + if (NULL == (nx = first_urb_link (hd))) { + /* The list is empty */ + return (NULL); + } + return (p2surround (struct urb, link, nx)); +} + +/* + * Detach and return the first urb in a list with a distinguished + * head "hd", or NULL if the list is empty. + * + */ +struct urb *first_urb_detached (urb_link * hd) +{ + struct urb *urb; + if ((urb = first_urb (hd))) { + urb_detach (urb); + } + return urb; +} + + +/* + * Append an urb_link (or a whole list of + * urb_links) to the tail of another list + * of urb_links. + */ +void urb_append (urb_link * hd, struct urb *urb) +{ + if (hd && urb) { + urb_link *new = &urb->link; + + /* This allows the new urb to be a list of urbs, */ + /* with new pointing at the first, but the link */ + /* must be initialized. */ + /* Order is important here... */ + urb_link *pul = hd->prev; + new->prev->next = hd; + hd->prev = new->prev; + new->prev = pul; + pul->next = new; + } +} + +/* URB create/destroy functions ***************************************************** */ + +/** + * usbd_alloc_urb - allocate an URB appropriate for specified endpoint + * @device: device instance + * @endpoint: endpoint + * + * Allocate an urb structure. The usb device urb structure is used to + * contain all data associated with a transfer, including a setup packet for + * control transfers. + * + * NOTE: endpoint_address MUST contain a direction flag. + */ +struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint) +{ + struct urb *urb; + + if( !(urb = (struct urb*)malloc(sizeof(struct urb))) ) { + usberr(" F A T A L: malloc(%u) FAILED!!!!", sizeof(struct urb)); + return NULL; + } + + /* Fill in known fields */ + memset(urb, 0, sizeof(struct urb)); + urb->endpoint = endpoint; + urb->device = device; + urb->buffer = (u8*)urb->buffer_data; + urb->buffer_length = sizeof(urb->buffer_data); + + urb_link_init (&urb->link); + + return urb; +} + +/** + * usbd_dealloc_urb - deallocate an URB and associated buffer + * @urb: pointer to an urb structure + * + * Deallocate an urb structure and associated data. + */ +void usbd_dealloc_urb (struct urb *urb) +{ + if (urb) { + free (urb); + } +} + +/* Event signaling functions ***************************************************** */ + +/** + * usbd_device_event - called to respond to various usb events + * @device: pointer to struct device + * @event: event to respond to + * + * Used by a Bus driver to indicate an event. + */ +void usbd_device_event_irq (struct usb_device_instance *device, usb_device_event_t event, int data) +{ + usb_device_state_t state; + + if (!device || !device->bus) { + usberr("(%p,%d) NULL device or device->bus", device, event); + return; + } + + state = device->device_state; + + usbinfo("%s", usbd_device_events[event]); + + switch (event) { + case DEVICE_UNKNOWN: + break; + case DEVICE_INIT: + device->device_state = STATE_INIT; + break; + + case DEVICE_CREATE: + device->device_state = STATE_ATTACHED; + break; + + case DEVICE_HUB_CONFIGURED: + device->device_state = STATE_POWERED; + break; + + case DEVICE_RESET: + device->device_state = STATE_DEFAULT; + device->address = 0; + break; + + case DEVICE_ADDRESS_ASSIGNED: + device->device_state = STATE_ADDRESSED; + break; + + case DEVICE_CONFIGURED: + device->device_state = STATE_CONFIGURED; + break; + + case DEVICE_DE_CONFIGURED: + device->device_state = STATE_ADDRESSED; + break; + + case DEVICE_BUS_INACTIVE: + if (device->status != USBD_CLOSING) { + device->status = USBD_SUSPENDED; + } + break; + case DEVICE_BUS_ACTIVITY: + if (device->status != USBD_CLOSING) { + device->status = USBD_OK; + } + break; + + case DEVICE_SET_INTERFACE: + break; + case DEVICE_SET_FEATURE: + break; + case DEVICE_CLEAR_FEATURE: + break; + + case DEVICE_POWER_INTERRUPTION: + device->device_state = STATE_POWERED; + break; + case DEVICE_HUB_RESET: + device->device_state = STATE_ATTACHED; + break; + case DEVICE_DESTROY: + device->device_state = STATE_UNKNOWN; + break; + + case DEVICE_FUNCTION_PRIVATE: + break; + + default: + usbdbg("event %d - not handled",event); + break; + } + /*usbdbg("%s event: %d oldstate: %d newstate: %d status: %d address: %d", + device->name, event, state, + device->device_state, device->status, device->address); */ + + /* tell the bus interface driver */ + if( device->event ) { + /* usbdbg("calling device->event"); */ + device->event(device, event, data); + } +} diff --git a/drivers/usbdcore_ep0.c b/drivers/usbdcore_ep0.c new file mode 100644 index 0000000..260befe --- /dev/null +++ b/drivers/usbdcore_ep0.c @@ -0,0 +1,686 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usbd/ep0.c + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +/* + * This is the builtin ep0 control function. It implements all required functionality + * for responding to control requests (SETUP packets). + * + * XXX + * + * Currently we do not pass any SETUP packets (or other) to the configured + * function driver. This may need to change. + * + * XXX + */ + +#include + +#if defined(CONFIG_OMAP1510) && defined(CONFIG_USB_DEVICE) +#include "usbdcore.h" + +#if 0 +#define dbg_ep0(lvl,fmt,args...) serial_printf("[%s] %s:%d: "fmt"\n",__FILE__,__FUNCTION__,__LINE__,##args) +#else +#define dbg_ep0(lvl,fmt,args...) +#endif + +/* EP0 Configuration Set ********************************************************************* */ + + +/** + * ep0_get_status - fill in URB data with appropriate status + * @device: + * @urb: + * @index: + * @requesttype: + * + */ +static int ep0_get_status (struct usb_device_instance *device, + struct urb *urb, int index, int requesttype) +{ + char *cp; + + urb->actual_length = 2; + cp = urb->buffer; + cp[0] = cp[1] = 0; + + switch (requesttype) { + case USB_REQ_RECIPIENT_DEVICE: + cp[0] = USB_STATUS_SELFPOWERED; + break; + case USB_REQ_RECIPIENT_INTERFACE: + break; + case USB_REQ_RECIPIENT_ENDPOINT: + cp[0] = usbd_endpoint_halted (device, index); + break; + case USB_REQ_RECIPIENT_OTHER: + urb->actual_length = 0; + default: + break; + } + dbg_ep0 (2, "%02x %02x", cp[0], cp[1]); + return 0; +} + +/** + * ep0_get_one + * @device: + * @urb: + * @result: + * + * Set a single byte value in the urb send buffer. Return non-zero to signal + * a request error. + */ +static int ep0_get_one (struct usb_device_instance *device, struct urb *urb, + __u8 result) +{ + urb->actual_length = 1; /* XXX 2? */ + ((char *) urb->buffer)[0] = result; + return 0; +} + +/** + * copy_config + * @urb: pointer to urb + * @data: pointer to configuration data + * @length: length of data + * + * Copy configuration data to urb transfer buffer if there is room for it. + */ +static void copy_config (struct urb *urb, void *data, int max_length, + int max_buf) +{ + int available; + int length; + + /*dbg_ep0(3, "-> actual: %d buf: %d max_buf: %d max_length: %d data: %p", */ + /* urb->actual_length, urb->buffer_length, max_buf, max_length, data); */ + + if (!data) { + dbg_ep0 (1, "data is NULL"); + return; + } + if (!(length = *(unsigned char *) data)) { + dbg_ep0 (1, "length is zero"); + return; + } + + if (length > max_length) { + dbg_ep0 (1, "length: %d >= max_length: %d", length, + max_length); + return; + } + /*dbg_ep0(1, " actual: %d buf: %d max_buf: %d max_length: %d length: %d", */ + /* urb->actual_length, urb->buffer_length, max_buf, max_length, length); */ + + if ((available = + /*urb->buffer_length */ max_buf - urb->actual_length) <= 0) { + return; + } + /*dbg_ep0(1, "actual: %d buf: %d max_buf: %d length: %d available: %d", */ + /* urb->actual_length, urb->buffer_length, max_buf, length, available); */ + + if (length > available) { + length = available; + } + /*dbg_ep0(1, "actual: %d buf: %d max_buf: %d length: %d available: %d", */ + /* urb->actual_length, urb->buffer_length, max_buf, length, available); */ + + memcpy (urb->buffer + urb->actual_length, data, length); + urb->actual_length += length; + + dbg_ep0 (3, + "copy_config: <- actual: %d buf: %d max_buf: %d max_length: %d available: %d", + urb->actual_length, urb->buffer_length, max_buf, max_length, + available); +} + +/** + * ep0_get_descriptor + * @device: + * @urb: + * @max: + * @descriptor_type: + * @index: + * + * Called by ep0_rx_process for a get descriptor device command. Determine what + * descriptor is being requested, copy to send buffer. Return zero if ok to send, + * return non-zero to signal a request error. + */ +static int ep0_get_descriptor (struct usb_device_instance *device, + struct urb *urb, int max, int descriptor_type, + int index) +{ + int port = 0; /* XXX compound device */ + char *cp; + + /*dbg_ep0(3, "max: %x type: %x index: %x", max, descriptor_type, index); */ + + if (!urb || !urb->buffer || !urb->buffer_length + || (urb->buffer_length < 255)) { + dbg_ep0 (2, "invalid urb %p", urb); + return -1L; + } + + /* setup tx urb */ + urb->actual_length = 0; + cp = urb->buffer; + + dbg_ep0 (2, "%s", USBD_DEVICE_DESCRIPTORS (descriptor_type)); + + switch (descriptor_type) { + case USB_DESCRIPTOR_TYPE_DEVICE: + { + struct usb_device_descriptor *device_descriptor; + + if (! + (device_descriptor = + usbd_device_device_descriptor (device, port))) { + return -1; + } + /* copy descriptor for this device */ + copy_config (urb, device_descriptor, + sizeof (struct usb_device_descriptor), + max); + + /* correct the correct control endpoint 0 max packet size into the descriptor */ + device_descriptor = + (struct usb_device_descriptor *) urb->buffer; + device_descriptor->bMaxPacketSize0 = + urb->device->bus->maxpacketsize; + + } + /*dbg_ep0(3, "copied device configuration, actual_length: %x", urb->actual_length); */ + break; + + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + { + int bNumInterface; + struct usb_configuration_descriptor + *configuration_descriptor; + struct usb_device_descriptor *device_descriptor; + + if (! + (device_descriptor = + usbd_device_device_descriptor (device, port))) { + return -1; + } + /*dbg_ep0(2, "%d %d", index, device_descriptor->bNumConfigurations); */ + if (index > device_descriptor->bNumConfigurations) { + dbg_ep0 (0, "index too large: %d > %d", index, + device_descriptor-> + bNumConfigurations); + return -1; + } + + if (! + (configuration_descriptor = + usbd_device_configuration_descriptor (device, + port, + index))) { + dbg_ep0 (0, + "usbd_device_configuration_descriptor failed: %d", + index); + return -1; + } + copy_config (urb, configuration_descriptor, + sizeof (struct + usb_configuration_descriptor), + max); + + + /* iterate across interfaces for specified configuration */ + dbg_ep0 (0, "bNumInterfaces: %d", + configuration_descriptor->bNumInterfaces); + for (bNumInterface = 0; + bNumInterface < + configuration_descriptor->bNumInterfaces; + bNumInterface++) { + + int bAlternateSetting; + struct usb_interface_instance + *interface_instance; + + dbg_ep0 (3, "[%d] bNumInterfaces: %d", + bNumInterface, + configuration_descriptor->bNumInterfaces); + + if (! (interface_instance = usbd_device_interface_instance (device, + port, index, bNumInterface))) + { + dbg_ep0 (3, "[%d] interface_instance NULL", + bNumInterface); + return -1; + } + /* iterate across interface alternates */ + for (bAlternateSetting = 0; + bAlternateSetting < interface_instance->alternates; + bAlternateSetting++) { + /*int class; */ + int bNumEndpoint; + struct usb_interface_descriptor *interface_descriptor; + + struct usb_alternate_instance *alternate_instance; + + dbg_ep0 (3, "[%d:%d] alternates: %d", + bNumInterface, + bAlternateSetting, + interface_instance->alternates); + + if (! (alternate_instance = usbd_device_alternate_instance (device, port, index, bNumInterface, bAlternateSetting))) { + dbg_ep0 (3, "[%d] alternate_instance NULL", + bNumInterface); + return -1; + } + /* copy descriptor for this interface */ + copy_config (urb, alternate_instance->interface_descriptor, + sizeof (struct usb_interface_descriptor), + max); + + /*dbg_ep0(3, "[%d:%d] classes: %d endpoints: %d", bNumInterface, bAlternateSetting, */ + /* alternate_instance->classes, alternate_instance->endpoints); */ + + /* iterate across classes for this alternate interface */ +#if 0 + for (class = 0; + class < alternate_instance->classes; + class++) { + struct usb_class_descriptor *class_descriptor; + /*dbg_ep0(3, "[%d:%d:%d] classes: %d", bNumInterface, bAlternateSetting, */ + /* class, alternate_instance->classes); */ + if (!(class_descriptor = usbd_device_class_descriptor_index (device, port, index, bNumInterface, bAlternateSetting, class))) { + dbg_ep0 (3, "[%d] class NULL", + class); + return -1; + } + /* copy descriptor for this class */ + copy_config (urb, class_descriptor, + sizeof (struct usb_class_descriptor), + max); + } +#endif + + /* iterate across endpoints for this alternate interface */ + interface_descriptor = alternate_instance->interface_descriptor; + for (bNumEndpoint = 0; + bNumEndpoint < alternate_instance->endpoints; + bNumEndpoint++) { + struct usb_endpoint_descriptor *endpoint_descriptor; + dbg_ep0 (3, "[%d:%d:%d] endpoint: %d", + bNumInterface, + bAlternateSetting, + bNumEndpoint, + interface_descriptor-> + bNumEndpoints); + if (!(endpoint_descriptor = usbd_device_endpoint_descriptor_index (device, port, index, bNumInterface, bAlternateSetting, bNumEndpoint))) { + dbg_ep0 (3, "[%d] endpoint NULL", + bNumEndpoint); + return -1; + } + /* copy descriptor for this endpoint */ + copy_config (urb, endpoint_descriptor, + sizeof (struct usb_endpoint_descriptor), + max); + } + } + } + dbg_ep0 (3, "lengths: %d %d", + le16_to_cpu (configuration_descriptor->wTotalLength), + urb->actual_length); + } + break; + + case USB_DESCRIPTOR_TYPE_STRING: + { + struct usb_string_descriptor *string_descriptor; + + if (!(string_descriptor = usbd_get_string (index))) { + return -1; + } + /*dbg_ep0(3, "string_descriptor: %p", string_descriptor); */ + copy_config (urb, string_descriptor, string_descriptor->bLength, max); + } + break; + case USB_DESCRIPTOR_TYPE_INTERFACE: + return -1; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + return -1; + case USB_DESCRIPTOR_TYPE_HID: + { + return -1; /* unsupported at this time */ +#if 0 + int bNumInterface = + le16_to_cpu (urb->device_request.wIndex); + int bAlternateSetting = 0; + int class = 0; + struct usb_class_descriptor *class_descriptor; + + if (!(class_descriptor = + usbd_device_class_descriptor_index (device, + port, 0, + bNumInterface, + bAlternateSetting, + class)) + || class_descriptor->descriptor.hid.bDescriptorType != USB_DT_HID) { + dbg_ep0 (3, "[%d] interface is not HID", + bNumInterface); + return -1; + } + /* copy descriptor for this class */ + copy_config (urb, class_descriptor, + class_descriptor->descriptor.hid.bLength, + max); +#endif + } + break; + case USB_DESCRIPTOR_TYPE_REPORT: + { + return -1; /* unsupported at this time */ +#if 0 + int bNumInterface = + le16_to_cpu (urb->device_request.wIndex); + int bAlternateSetting = 0; + int class = 0; + struct usb_class_report_descriptor *report_descriptor; + + if (!(report_descriptor = + usbd_device_class_report_descriptor_index + (device, port, 0, bNumInterface, + bAlternateSetting, class)) + || report_descriptor->bDescriptorType != + USB_DT_REPORT) { + dbg_ep0 (3, "[%d] descriptor is not REPORT", + bNumInterface); + return -1; + } + /* copy report descriptor for this class */ + /*copy_config(urb, &report_descriptor->bData[0], report_descriptor->wLength, max); */ + if (max - urb->actual_length > 0) { + int length = + MIN (report_descriptor->wLength, + max - urb->actual_length); + memcpy (urb->buffer + urb->actual_length, + &report_descriptor->bData[0], length); + urb->actual_length += length; + } +#endif + } + break; + default: + return -1; + } + + + dbg_ep0 (1, "urb: buffer: %p buffer_length: %2d actual_length: %2d packet size: %2d", + urb->buffer, urb->buffer_length, urb->actual_length, + device->bus->endpoint_array[0].tx_packetSize); +/* + if ((urb->actual_length < max) && !(urb->actual_length % device->bus->endpoint_array[0].tx_packetSize)) { + dbg_ep0(0, "adding null byte"); + urb->buffer[urb->actual_length++] = 0; + dbg_ep0(0, "urb: buffer_length: %2d actual_length: %2d packet size: %2d", + urb->buffer_length, urb->actual_length device->bus->endpoint_array[0].tx_packetSize); + } +*/ + return 0; + +} + +/** + * ep0_recv_setup - called to indicate URB has been received + * @urb: pointer to struct urb + * + * Check if this is a setup packet, process the device request, put results + * back into the urb and return zero or non-zero to indicate success (DATA) + * or failure (STALL). + * + */ +int ep0_recv_setup (struct urb *urb) +{ + /*struct usb_device_request *request = urb->buffer; */ + /*struct usb_device_instance *device = urb->device; */ + + struct usb_device_request *request; + struct usb_device_instance *device; + int address; + + dbg_ep0 (0, "entering ep0_recv_setup()"); + if (!urb || !urb->device) { + dbg_ep0 (3, "invalid URB %p", urb); + return -1; + } + + request = &urb->device_request; + device = urb->device; + + dbg_ep0 (3, "urb: %p device: %p", urb, urb->device); + + + /*dbg_ep0(2, "- - - - - - - - - -"); */ + + dbg_ep0 (2, + "bmRequestType:%02x bRequest:%02x wValue:%04x wIndex:%04x wLength:%04x %s", + request->bmRequestType, request->bRequest, + le16_to_cpu (request->wValue), le16_to_cpu (request->wIndex), + le16_to_cpu (request->wLength), + USBD_DEVICE_REQUESTS (request->bRequest)); + + /* handle USB Standard Request (c.f. USB Spec table 9-2) */ + if ((request->bmRequestType & USB_REQ_TYPE_MASK) != 0) { + dbg_ep0 (1, "non standard request: %x", + request->bmRequestType & USB_REQ_TYPE_MASK); + return -1; /* Stall here */ + } + + switch (device->device_state) { + case STATE_CREATED: + case STATE_ATTACHED: + case STATE_POWERED: + /* It actually is important to allow requests in these states, + * Windows will request descriptors before assigning an + * address to the client. + */ + + /*dbg_ep0 (1, "request %s not allowed in this state: %s", */ + /* USBD_DEVICE_REQUESTS(request->bRequest), */ + /* usbd_device_states[device->device_state]); */ + /*return -1; */ + break; + + case STATE_INIT: + case STATE_DEFAULT: + switch (request->bRequest) { + case USB_REQ_GET_STATUS: + case USB_REQ_GET_INTERFACE: + case USB_REQ_SYNCH_FRAME: /* XXX should never see this (?) */ + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_DESCRIPTOR: + /* case USB_REQ_SET_CONFIGURATION: */ + case USB_REQ_SET_INTERFACE: + dbg_ep0 (1, + "request %s not allowed in DEFAULT state: %s", + USBD_DEVICE_REQUESTS (request->bRequest), + usbd_device_states[device->device_state]); + return -1; + + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_ADDRESS: + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + break; + } + case STATE_ADDRESSED: + case STATE_CONFIGURED: + break; + case STATE_UNKNOWN: + dbg_ep0 (1, "request %s not allowed in UNKNOWN state: %s", + USBD_DEVICE_REQUESTS (request->bRequest), + usbd_device_states[device->device_state]); + return -1; + } + + /* handle all requests that return data (direction bit set on bm RequestType) */ + if ((request->bmRequestType & USB_REQ_DIRECTION_MASK)) { + + dbg_ep0 (3, "Device-to-Host"); + + switch (request->bRequest) { + + case USB_REQ_GET_STATUS: + return ep0_get_status (device, urb, request->wIndex, + request->bmRequestType & + USB_REQ_RECIPIENT_MASK); + + case USB_REQ_GET_DESCRIPTOR: + return ep0_get_descriptor (device, urb, + le16_to_cpu (request->wLength), + le16_to_cpu (request->wValue) >> 8, + le16_to_cpu (request->wValue) & 0xff); + + case USB_REQ_GET_CONFIGURATION: + return ep0_get_one (device, urb, + device->configuration); + + case USB_REQ_GET_INTERFACE: + return ep0_get_one (device, urb, device->alternate); + + case USB_REQ_SYNCH_FRAME: /* XXX should never see this (?) */ + return -1; + + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_ADDRESS: + case USB_REQ_SET_DESCRIPTOR: + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_INTERFACE: + return -1; + } + } + /* handle the requests that do not return data */ + else { + + + /*dbg_ep0(3, "Host-to-Device"); */ + switch (request->bRequest) { + + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + dbg_ep0 (0, "Host-to-Device"); + switch (request-> + bmRequestType & USB_REQ_RECIPIENT_MASK) { + case USB_REQ_RECIPIENT_DEVICE: + /* XXX DEVICE_REMOTE_WAKEUP or TEST_MODE would be added here */ + /* XXX fall through for now as we do not support either */ + case USB_REQ_RECIPIENT_INTERFACE: + case USB_REQ_RECIPIENT_OTHER: + dbg_ep0 (0, "request %s not", + USBD_DEVICE_REQUESTS (request->bRequest)); + default: + return -1; + + case USB_REQ_RECIPIENT_ENDPOINT: + dbg_ep0 (0, "ENDPOINT: %x", le16_to_cpu (request->wValue)); + if (le16_to_cpu (request->wValue) == USB_ENDPOINT_HALT) { + /*return usbd_device_feature (device, le16_to_cpu (request->wIndex), */ + /* request->bRequest == USB_REQ_SET_FEATURE); */ + /* NEED TO IMPLEMENT THIS!!! */ + return -1; + } else { + dbg_ep0 (1, "request %s bad wValue: %04x", + USBD_DEVICE_REQUESTS + (request->bRequest), + le16_to_cpu (request->wValue)); + return -1; + } + } + + case USB_REQ_SET_ADDRESS: + /* check if this is a re-address, reset first if it is (this shouldn't be possible) */ + if (device->device_state != STATE_DEFAULT) { + dbg_ep0 (1, "set_address: %02x state: %s", + le16_to_cpu (request->wValue), + usbd_device_states[device->device_state]); + return -1; + } + address = le16_to_cpu (request->wValue); + if ((address & 0x7f) != address) { + dbg_ep0 (1, "invalid address %04x %04x", + address, address & 0x7f); + return -1; + } + device->address = address; + + /*dbg_ep0(2, "address: %d %d %d", */ + /* request->wValue, le16_to_cpu(request->wValue), device->address); */ + + serial_printf ("DEVICE_ADDRESS_ASSIGNED.. event?\n"); + return 0; + + case USB_REQ_SET_DESCRIPTOR: /* XXX should we support this? */ + dbg_ep0 (0, "set descriptor: NOT SUPPORTED"); + return -1; + + case USB_REQ_SET_CONFIGURATION: + /* c.f. 9.4.7 - the top half of wValue is reserved */ + /* */ + if ((device->configuration = + le16_to_cpu (request->wValue) & 0x7f) != 0) { + /* c.f. 9.4.7 - zero is the default or addressed state, in our case this */ + /* is the same is configuration zero */ + device->configuration = 0; /* TBR - ?????? */ + } + /* reset interface and alternate settings */ + device->interface = device->alternate = 0; + + /*dbg_ep0(2, "set configuration: %d", device->configuration); */ + /*serial_printf("DEVICE_CONFIGURED.. event?\n"); */ + return 0; + + case USB_REQ_SET_INTERFACE: + device->interface = le16_to_cpu (request->wIndex); + device->alternate = le16_to_cpu (request->wValue); + /*dbg_ep0(2, "set interface: %d alternate: %d", device->interface, device->alternate); */ + serial_printf ("DEVICE_SET_INTERFACE.. event?\n"); + return 0; + + case USB_REQ_GET_STATUS: + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + case USB_REQ_GET_INTERFACE: + case USB_REQ_SYNCH_FRAME: /* XXX should never see this (?) */ + return -1; + } + } + return -1; +} + +#endif diff --git a/drivers/usbdcore_omap1510.c b/drivers/usbdcore_omap1510.c new file mode 100644 index 0000000..1d54a63 --- /dev/null +++ b/drivers/usbdcore_omap1510.c @@ -0,0 +1,1520 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usb/device/bi/omap.c + * TI OMAP1510 USB bus interface driver + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * (C) Copyright 2002 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if defined(CONFIG_OMAP1510) && defined(CONFIG_USB_DEVICE) + +#include +#ifdef CONFIG_OMAP_SX1 +#include +#endif + +#include "usbdcore.h" +#include "usbdcore_omap1510.h" +#include "usbdcore_ep0.h" + + +#define UDC_INIT_MDELAY 80 /* Device settle delay */ +#define UDC_MAX_ENDPOINTS 31 /* Number of endpoints on this UDC */ + +/* Some kind of debugging output... */ +#if 1 +#define UDCDBG(str) +#define UDCDBGA(fmt,args...) +#else /* The bugs still exists... */ +#define UDCDBG(str) serial_printf("[%s] %s:%d: " str "\n", __FILE__,__FUNCTION__,__LINE__) +#define UDCDBGA(fmt,args...) serial_printf("[%s] %s:%d: " fmt "\n", __FILE__,__FUNCTION__,__LINE__, ##args) +#endif + +#if 1 +#define UDCREG(name) +#define UDCREGL(name) +#else /* The bugs still exists... */ +#define UDCREG(name) serial_printf("%s():%d: %s[%08x]=%.4x\n",__FUNCTION__,__LINE__, (#name), name, inw(name)) /* For 16-bit regs */ +#define UDCREGL(name) serial_printf("%s():%d: %s[%08x]=%.8x\n",__FUNCTION__,__LINE__, (#name), name, inl(name)) /* For 32-bit regs */ +#endif + + +static struct urb *ep0_urb = NULL; + +static struct usb_device_instance *udc_device; /* Used in interrupt handler */ +static u16 udc_devstat = 0; /* UDC status (DEVSTAT) */ +static u32 udc_interrupts = 0; + +static void udc_stall_ep (unsigned int ep_addr); + + +static struct usb_endpoint_instance *omap1510_find_ep (int ep) +{ + int i; + + for (i = 0; i < udc_device->bus->max_endpoints; i++) { + if (udc_device->bus->endpoint_array[i].endpoint_address == ep) + return &udc_device->bus->endpoint_array[i]; + } + return NULL; +} + +/* ************************************************************************** */ +/* IO + */ + +/* + * omap1510_prepare_endpoint_for_rx + * + * This function implements TRM Figure 14-11. + * + * The endpoint to prepare for transfer is specified as a physical endpoint + * number. For OUT (rx) endpoints 1 through 15, the corresponding endpoint + * configuration register is checked to see if the endpoint is ISO or not. + * If the OUT endpoint is valid and is non-ISO then its FIFO is enabled. + * No action is taken for endpoint 0 or for IN (tx) endpoints 16 through 30. + */ +static void omap1510_prepare_endpoint_for_rx (int ep_addr) +{ + int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + + UDCDBGA ("omap1510_prepare_endpoint %x", ep_addr); + if (((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT)) { + if ((inw (UDC_EP_RX (ep_num)) & + (UDC_EPn_RX_Valid | UDC_EPn_RX_Iso)) == + UDC_EPn_RX_Valid) { + /* rx endpoint is valid, non-ISO, so enable its FIFO */ + outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); + outw (UDC_Set_FIFO_En, UDC_CTRL); + outw (0, UDC_EP_NUM); + } + } +} + +/* omap1510_configure_endpoints + * + * This function implements TRM Figure 14-10. + */ +static void omap1510_configure_endpoints (struct usb_device_instance *device) +{ + int ep; + struct usb_bus_instance *bus; + struct usb_endpoint_instance *endpoint; + unsigned short ep_ptr; + unsigned short ep_size; + unsigned short ep_isoc; + unsigned short ep_doublebuffer; + int ep_addr; + int packet_size; + int buffer_size; + int attributes; + + bus = device->bus; + + /* There is a dedicated 2048 byte buffer for USB packets that may be + * arbitrarily partitioned among the endpoints on 8-byte boundaries. + * The first 8 bytes are reserved for receiving setup packets on + * endpoint 0. + */ + ep_ptr = 8; /* reserve the first 8 bytes for the setup fifo */ + + for (ep = 0; ep < bus->max_endpoints; ep++) { + endpoint = bus->endpoint_array + ep; + ep_addr = endpoint->endpoint_address; + if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* IN endpoint */ + packet_size = endpoint->tx_packetSize; + attributes = endpoint->tx_attributes; + } else { + /* OUT endpoint */ + packet_size = endpoint->rcv_packetSize; + attributes = endpoint->rcv_attributes; + } + + switch (packet_size) { + case 0: + ep_size = 0; + break; + case 8: + ep_size = 0; + break; + case 16: + ep_size = 1; + break; + case 32: + ep_size = 2; + break; + case 64: + ep_size = 3; + break; + case 128: + ep_size = 4; + break; + case 256: + ep_size = 5; + break; + case 512: + ep_size = 6; + break; + default: + UDCDBGA ("ep 0x%02x has bad packet size %d", + ep_addr, packet_size); + packet_size = 0; + ep_size = 0; + break; + } + + switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + case USB_ENDPOINT_XFER_INT: + default: + /* A non-isochronous endpoint may optionally be + * double-buffered. For now we disable + * double-buffering. + */ + ep_doublebuffer = 0; + ep_isoc = 0; + if (packet_size > 64) + packet_size = 0; + if (!ep || !ep_doublebuffer) + buffer_size = packet_size; + else + buffer_size = packet_size * 2; + break; + case USB_ENDPOINT_XFER_ISOC: + /* Isochronous endpoints are always double- + * buffered, but the double-buffering bit + * in the endpoint configuration register + * becomes the msb of the endpoint size so we + * set the double-buffering flag to zero. + */ + ep_doublebuffer = 0; + ep_isoc = 1; + buffer_size = packet_size * 2; + break; + } + + /* check to see if our packet buffer RAM is exhausted */ + if ((ep_ptr + buffer_size) > 2048) { + UDCDBGA ("out of packet RAM for ep 0x%02x buf size %d", ep_addr, buffer_size); + buffer_size = packet_size = 0; + } + + /* force a default configuration for endpoint 0 since it is + * always enabled + */ + if (!ep && ((packet_size < 8) || (packet_size > 64))) { + buffer_size = packet_size = 64; + ep_size = 3; + } + + if (!ep) { + /* configure endpoint 0 */ + outw ((ep_size << 12) | (ep_ptr >> 3), UDC_EP0); + /*UDCDBGA("ep 0 buffer offset 0x%03x packet size 0x%03x", */ + /* ep_ptr, packet_size); */ + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* IN endpoint */ + if (packet_size) { + outw ((1 << 15) | (ep_doublebuffer << 14) | + (ep_size << 12) | (ep_isoc << 11) | + (ep_ptr >> 3), + UDC_EP_TX (ep_addr & + USB_ENDPOINT_NUMBER_MASK)); + UDCDBGA ("IN ep %d buffer offset 0x%03x" + " packet size 0x%03x", + ep_addr & USB_ENDPOINT_NUMBER_MASK, + ep_ptr, packet_size); + } else { + outw (0, + UDC_EP_TX (ep_addr & + USB_ENDPOINT_NUMBER_MASK)); + } + } else { + /* OUT endpoint */ + if (packet_size) { + outw ((1 << 15) | (ep_doublebuffer << 14) | + (ep_size << 12) | (ep_isoc << 11) | + (ep_ptr >> 3), + UDC_EP_RX (ep_addr & + USB_ENDPOINT_NUMBER_MASK)); + UDCDBGA ("OUT ep %d buffer offset 0x%03x" + " packet size 0x%03x", + ep_addr & USB_ENDPOINT_NUMBER_MASK, + ep_ptr, packet_size); + } else { + outw (0, + UDC_EP_RX (ep_addr & + USB_ENDPOINT_NUMBER_MASK)); + } + } + ep_ptr += buffer_size; + } +} + +/* omap1510_deconfigure_device + * + * This function balances omap1510_configure_device. + */ +static void omap1510_deconfigure_device (void) +{ + int epnum; + + UDCDBG ("clear Cfg_Lock"); + outw (inw (UDC_SYSCON1) & ~UDC_Cfg_Lock, UDC_SYSCON1); + UDCREG (UDC_SYSCON1); + + /* deconfigure all endpoints */ + for (epnum = 1; epnum <= 15; epnum++) { + outw (0, UDC_EP_RX (epnum)); + outw (0, UDC_EP_TX (epnum)); + } +} + +/* omap1510_configure_device + * + * This function implements TRM Figure 14-9. + */ +static void omap1510_configure_device (struct usb_device_instance *device) +{ + omap1510_configure_endpoints (device); + + + /* Figure 14-9 indicates we should enable interrupts here, but we have + * other routines (udc_all_interrupts, udc_suspended_interrupts) to + * do that. + */ + + UDCDBG ("set Cfg_Lock"); + outw (inw (UDC_SYSCON1) | UDC_Cfg_Lock, UDC_SYSCON1); + UDCREG (UDC_SYSCON1); +} + +/* omap1510_write_noniso_tx_fifo + * + * This function implements TRM Figure 14-30. + * + * If the endpoint has an active tx_urb, then the next packet of data from the + * URB is written to the tx FIFO. The total amount of data in the urb is given + * by urb->actual_length. The maximum amount of data that can be sent in any + * one packet is given by endpoint->tx_packetSize. The number of data bytes + * from this URB that have already been transmitted is given by endpoint->sent. + * endpoint->last is updated by this routine with the number of data bytes + * transmitted in this packet. + * + * In accordance with Figure 14-30, the EP_NUM register must already have been + * written with the value to select the appropriate tx FIFO before this routine + * is called. + */ +static void omap1510_write_noniso_tx_fifo (struct usb_endpoint_instance + *endpoint) +{ + struct urb *urb = endpoint->tx_urb; + + if (urb) { + unsigned int last, i; + + UDCDBGA ("urb->buffer %p, buffer_length %d, actual_length %d", + urb->buffer, urb->buffer_length, urb->actual_length); + if ((last = + MIN (urb->actual_length - endpoint->sent, + endpoint->tx_packetSize))) { + u8 *cp = urb->buffer + endpoint->sent; + + UDCDBGA ("endpoint->sent %d, tx_packetSize %d, last %d", endpoint->sent, endpoint->tx_packetSize, last); + + if (((u32) cp & 1) == 0) { /* word aligned? */ + outsw (UDC_DATA, cp, last >> 1); + } else { /* byte aligned. */ + for (i = 0; i < (last >> 1); i++) { + u16 w = ((u16) cp[2 * i + 1] << 8) | + (u16) cp[2 * i]; + outw (w, UDC_DATA); + } + } + if (last & 1) { + outb (*(cp + last - 1), UDC_DATA); + } + } + endpoint->last = last; + } +} + +/* omap1510_read_noniso_rx_fifo + * + * This function implements TRM Figure 14-28. + * + * If the endpoint has an active rcv_urb, then the next packet of data is read + * from the rcv FIFO and written to rcv_urb->buffer at offset + * rcv_urb->actual_length to append the packet data to the data from any + * previous packets for this transfer. We assume that there is sufficient room + * left in the buffer to hold an entire packet of data. + * + * The return value is the number of bytes read from the FIFO for this packet. + * + * In accordance with Figure 14-28, the EP_NUM register must already have been + * written with the value to select the appropriate rcv FIFO before this routine + * is called. + */ +static int omap1510_read_noniso_rx_fifo (struct usb_endpoint_instance + *endpoint) +{ + struct urb *urb = endpoint->rcv_urb; + int len = 0; + + if (urb) { + len = inw (UDC_RXFSTAT); + + if (len) { + unsigned char *cp = urb->buffer + urb->actual_length; + + insw (UDC_DATA, cp, len >> 1); + if (len & 1) + *(cp + len - 1) = inb (UDC_DATA); + } + } + return len; +} + +/* omap1510_prepare_for_control_write_status + * + * This function implements TRM Figure 14-17. + * + * We have to deal here with non-autodecoded control writes that haven't already + * been dealt with by ep0_recv_setup. The non-autodecoded standard control + * write requests are: set/clear endpoint feature, set configuration, set + * interface, and set descriptor. ep0_recv_setup handles set/clear requests for + * ENDPOINT_HALT by halting the endpoint for a set request and resetting the + * endpoint for a clear request. ep0_recv_setup returns an error for + * SET_DESCRIPTOR requests which causes them to be terminated with a stall by + * the setup handler. A SET_INTERFACE request is handled by ep0_recv_setup by + * generating a DEVICE_SET_INTERFACE event. This leaves only the + * SET_CONFIGURATION event for us to deal with here. + * + */ +static void omap1510_prepare_for_control_write_status (struct urb *urb) +{ + struct usb_device_request *request = &urb->device_request;; + + /* check for a SET_CONFIGURATION request */ + if (request->bRequest == USB_REQ_SET_CONFIGURATION) { + int configuration = le16_to_cpu (request->wValue) & 0xff; + unsigned short devstat = inw (UDC_DEVSTAT); + + if ((devstat & (UDC_ADD | UDC_CFG)) == UDC_ADD) { + /* device is currently in ADDRESSED state */ + if (configuration) { + /* Assume the specified non-zero configuration + * value is valid and switch to the CONFIGURED + * state. + */ + outw (UDC_Dev_Cfg, UDC_SYSCON2); + } + } else if ((devstat & UDC_CFG) == UDC_CFG) { + /* device is currently in CONFIGURED state */ + if (!configuration) { + /* Switch to ADDRESSED state. */ + outw (UDC_Clr_Cfg, UDC_SYSCON2); + } + } + } + + /* select EP0 tx FIFO */ + outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); + /* clear endpoint (no data bytes in status stage) */ + outw (UDC_Clr_EP, UDC_CTRL); + /* enable the EP0 tx FIFO */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect the endpoint */ + outw (UDC_EP_Dir, UDC_EP_NUM); +} + +/* udc_state_transition_up + * udc_state_transition_down + * + * Helper functions to implement device state changes. The device states and + * the events that transition between them are: + * + * STATE_ATTACHED + * || /\ + * \/ || + * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET + * || /\ + * \/ || + * STATE_POWERED + * || /\ + * \/ || + * DEVICE_RESET DEVICE_POWER_INTERRUPTION + * || /\ + * \/ || + * STATE_DEFAULT + * || /\ + * \/ || + * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET + * || /\ + * \/ || + * STATE_ADDRESSED + * || /\ + * \/ || + * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED + * || /\ + * \/ || + * STATE_CONFIGURED + * + * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED + * to STATE_CONFIGURED) from the specified initial state to the specified final + * state, passing through each intermediate state on the way. If the initial + * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then + * no state transitions will take place. + * + * udc_state_transition_down transitions down (in the direction from + * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the + * specified final state, passing through each intermediate state on the way. + * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final + * state, then no state transitions will take place. + * + * These functions must only be called with interrupts disabled. + */ +static void udc_state_transition_up (usb_device_state_t initial, + usb_device_state_t final) +{ + if (initial < final) { + switch (initial) { + case STATE_ATTACHED: + usbd_device_event_irq (udc_device, + DEVICE_HUB_CONFIGURED, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq (udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq (udc_device, + DEVICE_ADDRESS_ASSIGNED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq (udc_device, DEVICE_CONFIGURED, + 0); + case STATE_CONFIGURED: + break; + default: + break; + } + } +} + +static void udc_state_transition_down (usb_device_state_t initial, + usb_device_state_t final) +{ + if (initial > final) { + switch (initial) { + case STATE_CONFIGURED: + usbd_device_event_irq (udc_device, DEVICE_DE_CONFIGURED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq (udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq (udc_device, DEVICE_POWER_INTERRUPTION, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, 0); + case STATE_ATTACHED: + break; + default: + break; + } + } +} + +/* Handle all device state changes. + * This function implements TRM Figure 14-21. + */ +static void omap1510_udc_state_changed (void) +{ + u16 bits; + u16 devstat = inw (UDC_DEVSTAT); + + UDCDBGA ("state changed, devstat %x, old %x", devstat, udc_devstat); + + bits = devstat ^ udc_devstat; + if (bits) { + if (bits & UDC_ATT) { + if (devstat & UDC_ATT) { + UDCDBG ("device attached and powered"); + udc_state_transition_up (udc_device->device_state, STATE_POWERED); + } else { + UDCDBG ("device detached or unpowered"); + udc_state_transition_down (udc_device->device_state, STATE_ATTACHED); + } + } + if (bits & UDC_USB_Reset) { + if (devstat & UDC_USB_Reset) { + UDCDBG ("device reset in progess"); + udc_state_transition_down (udc_device->device_state, STATE_POWERED); + } else { + UDCDBG ("device reset completed"); + } + } + if (bits & UDC_DEF) { + if (devstat & UDC_DEF) { + UDCDBG ("device entering default state"); + udc_state_transition_up (udc_device->device_state, STATE_DEFAULT); + } else { + UDCDBG ("device leaving default state"); + udc_state_transition_down (udc_device->device_state, STATE_POWERED); + } + } + if (bits & UDC_SUS) { + if (devstat & UDC_SUS) { + UDCDBG ("entering suspended state"); + usbd_device_event_irq (udc_device, DEVICE_BUS_INACTIVE, 0); + } else { + UDCDBG ("leaving suspended state"); + usbd_device_event_irq (udc_device, DEVICE_BUS_ACTIVITY, 0); + } + } + if (bits & UDC_R_WK_OK) { + UDCDBGA ("remote wakeup %s", (devstat & UDC_R_WK_OK) + ? "enabled" : "disabled"); + } + if (bits & UDC_ADD) { + if (devstat & UDC_ADD) { + UDCDBG ("default -> addressed"); + udc_state_transition_up (udc_device->device_state, STATE_ADDRESSED); + } else { + UDCDBG ("addressed -> default"); + udc_state_transition_down (udc_device->device_state, STATE_DEFAULT); + } + } + if (bits & UDC_CFG) { + if (devstat & UDC_CFG) { + UDCDBG ("device configured"); + /* The ep0_recv_setup function generates the + * DEVICE_CONFIGURED event when a + * USB_REQ_SET_CONFIGURATION setup packet is + * received, so we should already be in the + * state STATE_CONFIGURED. + */ + udc_state_transition_up (udc_device->device_state, STATE_CONFIGURED); + } else { + UDCDBG ("device deconfigured"); + udc_state_transition_down (udc_device->device_state, STATE_ADDRESSED); + } + } + } + + /* Clear interrupt source */ + outw (UDC_DS_Chg, UDC_IRQ_SRC); + + /* Save current DEVSTAT */ + udc_devstat = devstat; +} + +/* Handle SETUP USB interrupt. + * This function implements TRM Figure 14-14. + */ +static void omap1510_udc_setup (struct usb_endpoint_instance *endpoint) +{ + UDCDBG ("-> Entering device setup"); + + do { + const int setup_pktsize = 8; + unsigned char *datap = + (unsigned char *) &ep0_urb->device_request; + + /* Gain access to EP 0 setup FIFO */ + outw (UDC_Setup_Sel, UDC_EP_NUM); + + /* Read control request data */ + insb (UDC_DATA, datap, setup_pktsize); + + UDCDBGA ("EP0 setup read [%x %x %x %x %x %x %x %x]", + *(datap + 0), *(datap + 1), *(datap + 2), + *(datap + 3), *(datap + 4), *(datap + 5), + *(datap + 6), *(datap + 7)); + + /* Reset EP0 setup FIFO */ + outw (0, UDC_EP_NUM); + } while (inw (UDC_IRQ_SRC) & UDC_Setup); + + /* Try to process setup packet */ + if (ep0_recv_setup (ep0_urb)) { + /* Not a setup packet, stall next EP0 transaction */ + udc_stall_ep (0); + UDCDBG ("can't parse setup packet, still waiting for setup"); + return; + } + + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) + == USB_REQ_HOST2DEVICE) { + UDCDBG ("control write on EP0"); + if (le16_to_cpu (ep0_urb->device_request.wLength)) { + /* We don't support control write data stages. + * The only standard control write request with a data + * stage is SET_DESCRIPTOR, and ep0_recv_setup doesn't + * support that so we just stall those requests. A + * function driver might support a non-standard + * write request with a data stage, but it isn't + * obvious what we would do with the data if we read it + * so we'll just stall it. It seems like the API isn't + * quite right here. + */ +#if 0 + /* Here is what we would do if we did support control + * write data stages. + */ + ep0_urb->actual_length = 0; + outw (0, UDC_EP_NUM); + /* enable the EP0 rx FIFO */ + outw (UDC_Set_FIFO_En, UDC_CTRL); +#else + /* Stall this request */ + UDCDBG ("Stalling unsupported EP0 control write data " + "stage."); + udc_stall_ep (0); +#endif + } else { + omap1510_prepare_for_control_write_status (ep0_urb); + } + } else { + UDCDBG ("control read on EP0"); + /* The ep0_recv_setup function has already placed our response + * packet data in ep0_urb->buffer and the packet length in + * ep0_urb->actual_length. + */ + endpoint->tx_urb = ep0_urb; + endpoint->sent = 0; + /* select the EP0 tx FIFO */ + outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); + /* Write packet data to the FIFO. omap1510_write_noniso_tx_fifo + * will update endpoint->last with the number of bytes written + * to the FIFO. + */ + omap1510_write_noniso_tx_fifo (endpoint); + /* enable the FIFO to start the packet transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect the EP0 tx FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } + + UDCDBG ("<- Leaving device setup"); +} + +/* Handle endpoint 0 RX interrupt + * This routine implements TRM Figure 14-16. + */ +static void omap1510_udc_ep0_rx (struct usb_endpoint_instance *endpoint) +{ + unsigned short status; + + UDCDBG ("RX on EP0"); + /* select EP0 rx FIFO */ + outw (UDC_EP_Sel, UDC_EP_NUM); + + status = inw (UDC_STAT_FLG); + + if (status & UDC_ACK) { + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType + & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { + /* This rx interrupt must be for a control write data + * stage packet. + * + * We don't support control write data stages. + * We should never end up here. + */ + + /* clear the EP0 rx FIFO */ + outw (UDC_Clr_EP, UDC_CTRL); + + /* deselect the EP0 rx FIFO */ + outw (0, UDC_EP_NUM); + + UDCDBG ("Stalling unexpected EP0 control write " + "data stage packet"); + udc_stall_ep (0); + } else { + /* This rx interrupt must be for a control read status + * stage packet. + */ + UDCDBG ("ACK on EP0 control read status stage packet"); + /* deselect EP0 rx FIFO */ + outw (0, UDC_EP_NUM); + } + } else if (status & UDC_STALL) { + UDCDBG ("EP0 stall during RX"); + /* deselect EP0 rx FIFO */ + outw (0, UDC_EP_NUM); + } else { + /* deselect EP0 rx FIFO */ + outw (0, UDC_EP_NUM); + } +} + +/* Handle endpoint 0 TX interrupt + * This routine implements TRM Figure 14-18. + */ +static void omap1510_udc_ep0_tx (struct usb_endpoint_instance *endpoint) +{ + unsigned short status; + struct usb_device_request *request = &ep0_urb->device_request; + + UDCDBG ("TX on EP0"); + /* select EP0 TX FIFO */ + outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); + + status = inw (UDC_STAT_FLG); + if (status & UDC_ACK) { + /* Check direction */ + if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == + USB_REQ_HOST2DEVICE) { + /* This tx interrupt must be for a control write status + * stage packet. + */ + UDCDBG ("ACK on EP0 control write status stage packet"); + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } else { + /* This tx interrupt must be for a control read data + * stage packet. + */ + int wLength = le16_to_cpu (request->wLength); + + /* Update our count of bytes sent so far in this + * transfer. + */ + endpoint->sent += endpoint->last; + + /* We are finished with this transfer if we have sent + * all of the bytes in our tx urb (urb->actual_length) + * unless we need a zero-length terminating packet. We + * need a zero-length terminating packet if we returned + * fewer bytes than were requested (wLength) by the host, + * and the number of bytes we returned is an exact + * multiple of the packet size endpoint->tx_packetSize. + */ + if ((endpoint->sent == ep0_urb->actual_length) + && ((ep0_urb->actual_length == wLength) + || (endpoint->last != + endpoint->tx_packetSize))) { + /* Done with control read data stage. */ + UDCDBG ("control read data stage complete"); + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + /* select EP0 RX FIFO to prepare for control + * read status stage. + */ + outw (UDC_EP_Sel, UDC_EP_NUM); + /* clear the EP0 RX FIFO */ + outw (UDC_Clr_EP, UDC_CTRL); + /* enable the EP0 RX FIFO */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect the EP0 RX FIFO */ + outw (0, UDC_EP_NUM); + } else { + /* We still have another packet of data to send + * in this control read data stage or else we + * need a zero-length terminating packet. + */ + UDCDBG ("ACK control read data stage packet"); + omap1510_write_noniso_tx_fifo (endpoint); + /* enable the EP0 tx FIFO to start transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } + } + } else if (status & UDC_STALL) { + UDCDBG ("EP0 stall during TX"); + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } else { + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } +} + +/* Handle RX transaction on non-ISO endpoint. + * This function implements TRM Figure 14-27. + * The ep argument is a physical endpoint number for a non-ISO OUT endpoint + * in the range 1 to 15. + */ +static void omap1510_udc_epn_rx (int ep) +{ + unsigned short status; + + /* Check endpoint status */ + status = inw (UDC_STAT_FLG); + + if (status & UDC_ACK) { + int nbytes; + struct usb_endpoint_instance *endpoint = + omap1510_find_ep (ep); + + nbytes = omap1510_read_noniso_rx_fifo (endpoint); + usbd_rcv_complete (endpoint, nbytes, 0); + + /* enable rx FIFO to prepare for next packet */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + } else if (status & UDC_STALL) { + UDCDBGA ("STALL on RX endpoint %d", ep); + } else if (status & UDC_NAK) { + UDCDBGA ("NAK on RX ep %d", ep); + } else { + serial_printf ("omap-bi: RX on ep %d with status %x", ep, + status); + } +} + +/* Handle TX transaction on non-ISO endpoint. + * This function implements TRM Figure 14-29. + * The ep argument is a physical endpoint number for a non-ISO IN endpoint + * in the range 16 to 30. + */ +static void omap1510_udc_epn_tx (int ep) +{ + unsigned short status; + + /*serial_printf("omap1510_udc_epn_tx( %x )\n",ep); */ + + /* Check endpoint status */ + status = inw (UDC_STAT_FLG); + + if (status & UDC_ACK) { + struct usb_endpoint_instance *endpoint = + omap1510_find_ep (ep); + + /* We need to transmit a terminating zero-length packet now if + * we have sent all of the data in this URB and the transfer + * size was an exact multiple of the packet size. + */ + if (endpoint->tx_urb + && (endpoint->last == endpoint->tx_packetSize) + && (endpoint->tx_urb->actual_length - endpoint->sent - + endpoint->last == 0)) { + /* Prepare to transmit a zero-length packet. */ + endpoint->sent += endpoint->last; + /* write 0 bytes of data to FIFO */ + omap1510_write_noniso_tx_fifo (endpoint); + /* enable tx FIFO to start transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + } else if (endpoint->tx_urb + && endpoint->tx_urb->actual_length) { + /* retire the data that was just sent */ + usbd_tx_complete (endpoint); + /* Check to see if we have more data ready to transmit + * now. + */ + if (endpoint->tx_urb + && endpoint->tx_urb->actual_length) { + /* write data to FIFO */ + omap1510_write_noniso_tx_fifo (endpoint); + /* enable tx FIFO to start transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + } + } + } else if (status & UDC_STALL) { + UDCDBGA ("STALL on TX endpoint %d", ep); + } else if (status & UDC_NAK) { + UDCDBGA ("NAK on TX endpoint %d", ep); + } else { + /*serial_printf("omap-bi: TX on ep %d with status %x\n", ep, status); */ + } +} + + +/* +------------------------------------------------------------------------------- +*/ + +/* Handle general USB interrupts and dispatch according to type. + * This function implements TRM Figure 14-13. + */ +void omap1510_udc_irq (void) +{ + u16 irq_src = inw (UDC_IRQ_SRC); + int valid_irq = 0; + + if (!(irq_src & ~UDC_SOF_Flg)) /* ignore SOF interrupts ) */ + return; + + UDCDBGA ("< IRQ #%d start >- %x", udc_interrupts, irq_src); + /*serial_printf("< IRQ #%d start >- %x\n", udc_interrupts, irq_src); */ + + if (irq_src & UDC_DS_Chg) { + /* Device status changed */ + omap1510_udc_state_changed (); + valid_irq++; + } + if (irq_src & UDC_EP0_RX) { + /* Endpoint 0 receive */ + outw (UDC_EP0_RX, UDC_IRQ_SRC); /* ack interrupt */ + omap1510_udc_ep0_rx (udc_device->bus->endpoint_array + 0); + valid_irq++; + } + if (irq_src & UDC_EP0_TX) { + /* Endpoint 0 transmit */ + outw (UDC_EP0_TX, UDC_IRQ_SRC); /* ack interrupt */ + omap1510_udc_ep0_tx (udc_device->bus->endpoint_array + 0); + valid_irq++; + } + if (irq_src & UDC_Setup) { + /* Device setup */ + omap1510_udc_setup (udc_device->bus->endpoint_array + 0); + valid_irq++; + } + /*if (!valid_irq) */ + /* serial_printf("unknown interrupt, IRQ_SRC %.4x\n", irq_src); */ + UDCDBGA ("< IRQ #%d end >", udc_interrupts); + udc_interrupts++; +} + +/* This function implements TRM Figure 14-26. */ +void omap1510_udc_noniso_irq (void) +{ + unsigned short epnum; + unsigned short irq_src = inw (UDC_IRQ_SRC); + int valid_irq = 0; + + if (!(irq_src & (UDC_EPn_RX | UDC_EPn_TX))) + return; + + UDCDBGA ("non-ISO IRQ, IRQ_SRC %x", inw (UDC_IRQ_SRC)); + + if (irq_src & UDC_EPn_RX) { /* Endpoint N OUT transaction */ + /* Determine the endpoint number for this interrupt */ + epnum = (inw (UDC_EPN_STAT) & 0x0f00) >> 8; + UDCDBGA ("RX on ep %x", epnum); + + /* acknowledge interrupt */ + outw (UDC_EPn_RX, UDC_IRQ_SRC); + + if (epnum) { + /* select the endpoint FIFO */ + outw (UDC_EP_Sel | epnum, UDC_EP_NUM); + + omap1510_udc_epn_rx (epnum); + + /* deselect the endpoint FIFO */ + outw (epnum, UDC_EP_NUM); + } + valid_irq++; + } + if (irq_src & UDC_EPn_TX) { /* Endpoint N IN transaction */ + /* Determine the endpoint number for this interrupt */ + epnum = (inw (UDC_EPN_STAT) & 0x000f) | USB_DIR_IN; + UDCDBGA ("TX on ep %x", epnum); + + /* acknowledge interrupt */ + outw (UDC_EPn_TX, UDC_IRQ_SRC); + + if (epnum) { + /* select the endpoint FIFO */ + outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); + + omap1510_udc_epn_tx (epnum); + + /* deselect the endpoint FIFO */ + outw (UDC_EP_Dir | epnum, UDC_EP_NUM); + } + valid_irq++; + } + if (!valid_irq) + serial_printf (": unknown non-ISO interrupt, IRQ_SRC %.4x\n", + irq_src); +} + +/* +------------------------------------------------------------------------------- +*/ + + +/* + * Start of public functions. + */ + +/* Called to start packet transmission. */ +void udc_endpoint_write (struct usb_endpoint_instance *endpoint) +{ + unsigned short epnum = + endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; + + UDCDBGA ("Starting transmit on ep %x", epnum); + + if (endpoint->tx_urb) { + /* select the endpoint FIFO */ + outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); + /* write data to FIFO */ + omap1510_write_noniso_tx_fifo (endpoint); + /* enable tx FIFO to start transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect the endpoint FIFO */ + outw (UDC_EP_Dir | epnum, UDC_EP_NUM); + } +} + +/* Start to initialize h/w stuff */ +int udc_init (void) +{ + u16 udc_rev; + uchar value; + ulong gpio; + int i; + + /* Let the device settle down before we start */ + for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000); + + udc_device = NULL; + + UDCDBG ("starting"); + + /* Check peripheral reset. Must be 1 to make sure + MPU TIPB peripheral reset is inactive */ + UDCREG (ARM_RSTCT2); + + /* Set and check clock control. + * We might ought to be using the clock control API to do + * this instead of fiddling with the clock registers directly + * here. + */ + outw ((1 << 4) | (1 << 5), CLOCK_CTRL); + UDCREG (CLOCK_CTRL); + /* Set and check APLL */ + outw (0x0008, APLL_CTRL); + UDCREG (APLL_CTRL); + /* Set and check DPLL */ + outw (0x2210, DPLL_CTRL); + UDCREG (DPLL_CTRL); + /* Set and check SOFT */ + outw ((1 << 4) | (1 << 3) | 1, SOFT_REQ); + /* Short delay to wait for DPLL */ + udelay (1000); + + /* Print banner with device revision */ + udc_rev = inw (UDC_REV) & 0xff; + printf ("USB: TI OMAP1510 USB function module rev %d.%d\n", + udc_rev >> 4, udc_rev & 0xf); + +#ifdef CONFIG_OMAP_SX1 + i2c_read (0x32, 0x04, 1, &value, 1); + value |= 0x04; + i2c_write (0x32, 0x04, 1, &value, 1); + + i2c_read (0x32, 0x03, 1, &value, 1); + value |= 0x01; + i2c_write (0x32, 0x03, 1, &value, 1); + + gpio = inl(GPIO_PIN_CONTROL_REG); + gpio |= 0x0002; /* A_IRDA_OFF */ + gpio |= 0x0800; /* A_SWITCH */ + gpio |= 0x8000; /* A_USB_ON */ + outl (gpio, GPIO_PIN_CONTROL_REG); + + gpio = inl(GPIO_DIR_CONTROL_REG); + gpio &= ~0x0002; /* A_IRDA_OFF */ + gpio &= ~0x0800; /* A_SWITCH */ + gpio &= ~0x8000; /* A_USB_ON */ + outl (gpio, GPIO_DIR_CONTROL_REG); + + gpio = inl(GPIO_DATA_OUTPUT_REG); + gpio |= 0x0002; /* A_IRDA_OFF */ + gpio &= ~0x0800; /* A_SWITCH */ + gpio &= ~0x8000; /* A_USB_ON */ + outl (gpio, GPIO_DATA_OUTPUT_REG); +#endif + + /* The VBUS_MODE bit selects whether VBUS detection is done via + * software (1) or hardware (0). When software detection is + * selected, VBUS_CTRL selects whether USB is not connected (0) + * or connected (1). + */ + outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); + outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); + UDCREGL (FUNC_MUX_CTRL_0); + + /* + * At this point, device is ready for configuration... + */ + + UDCDBG ("disable USB interrupts"); + outw (0, UDC_IRQ_EN); + UDCREG (UDC_IRQ_EN); + + UDCDBG ("disable USB DMA"); + outw (0, UDC_DMA_IRQ_EN); + UDCREG (UDC_DMA_IRQ_EN); + + UDCDBG ("initialize SYSCON1"); + outw (UDC_Self_Pwr | UDC_Pullup_En, UDC_SYSCON1); + UDCREG (UDC_SYSCON1); + + return 0; +} + +/* Stall endpoint */ +static void udc_stall_ep (unsigned int ep_addr) +{ + /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ + int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + + UDCDBGA ("stall ep_addr %d", ep_addr); + + /* REVISIT? + * The OMAP TRM section 14.2.4.2 says we must check that the FIFO + * is empty before halting the endpoint. The current implementation + * doesn't check that the FIFO is empty. + */ + + if (!ep_num) { + outw (UDC_Stall_Cmd, UDC_SYSCON2); + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { + if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { + /* we have a valid rx endpoint, so halt it */ + outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); + outw (UDC_Set_Halt, UDC_CTRL); + outw (ep_num, UDC_EP_NUM); + } + } else { + if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { + /* we have a valid tx endpoint, so halt it */ + outw (UDC_EP_Sel | UDC_EP_Dir | ep_num, UDC_EP_NUM); + outw (UDC_Set_Halt, UDC_CTRL); + outw (ep_num, UDC_EP_NUM); + } + } +} + +/* Reset endpoint */ +#if 0 +static void udc_reset_ep (unsigned int ep_addr) +{ + /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ + int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + + UDCDBGA ("reset ep_addr %d", ep_addr); + + if (!ep_num) { + /* control endpoint 0 can't be reset */ + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { + UDCDBGA ("UDC_EP_RX(%d) = 0x%04x", ep_num, + inw (UDC_EP_RX (ep_num))); + if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { + /* we have a valid rx endpoint, so reset it */ + outw (ep_num | UDC_EP_Sel, UDC_EP_NUM); + outw (UDC_Reset_EP, UDC_CTRL); + outw (ep_num, UDC_EP_NUM); + UDCDBGA ("OUT endpoint %d reset", ep_num); + } + } else { + UDCDBGA ("UDC_EP_TX(%d) = 0x%04x", ep_num, + inw (UDC_EP_TX (ep_num))); + /* Resetting of tx endpoints seems to be causing the USB function + * module to fail, which causes problems when the driver is + * uninstalled. We'll skip resetting tx endpoints for now until + * we figure out what the problem is. + */ +#if 0 + if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { + /* we have a valid tx endpoint, so reset it */ + outw (ep_num | UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); + outw (UDC_Reset_EP, UDC_CTRL); + outw (ep_num | UDC_EP_Dir, UDC_EP_NUM); + UDCDBGA ("IN endpoint %d reset", ep_num); + } +#endif + } +} +#endif + +/* ************************************************************************** */ + +/** + * udc_check_ep - check logical endpoint + * + * Return physical endpoint number to use for this logical endpoint or zero if not valid. + */ +#if 0 +int udc_check_ep (int logical_endpoint, int packetsize) +{ + if ((logical_endpoint == 0x80) || + ((logical_endpoint & 0x8f) != logical_endpoint)) { + return 0; + } + + switch (packetsize) { + case 8: + case 16: + case 32: + case 64: + case 128: + case 256: + case 512: + break; + default: + return 0; + } + + return EP_ADDR_TO_PHYS_EP (logical_endpoint); +} +#endif + +/* + * udc_setup_ep - setup endpoint + * + * Associate a physical endpoint with endpoint_instance + */ +void udc_setup_ep (struct usb_device_instance *device, + unsigned int ep, struct usb_endpoint_instance *endpoint) +{ + UDCDBGA ("setting up endpoint addr %x", endpoint->endpoint_address); + + /* This routine gets called by bi_modinit for endpoint 0 and from + * bi_config for all of the other endpoints. bi_config gets called + * during the DEVICE_CREATE, DEVICE_CONFIGURED, and + * DEVICE_SET_INTERFACE events. We need to reconfigure the OMAP packet + * RAM after bi_config scans the selected device configuration and + * initializes the endpoint structures, but before this routine enables + * the OUT endpoint FIFOs. Since bi_config calls this routine in a + * loop for endpoints 1 through UDC_MAX_ENDPOINTS, we reconfigure our + * packet RAM here when ep==1. + * I really hate to do this here, but it seems like the API exported + * by the USB bus interface controller driver to the usbd-bi module + * isn't quite right so there is no good place to do this. + */ + if (ep == 1) { + omap1510_deconfigure_device (); + omap1510_configure_device (device); + } + + if (endpoint && (ep < UDC_MAX_ENDPOINTS)) { + int ep_addr = endpoint->endpoint_address; + + if (!ep_addr) { + /* nothing to do for endpoint 0 */ + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* nothing to do for IN (tx) endpoints */ + } else { /* OUT (rx) endpoint */ + if (endpoint->rcv_packetSize) { + /*struct urb* urb = &(urb_out_array[ep&0xFF]); */ + /*urb->endpoint = endpoint; */ + /*urb->device = device; */ + /*urb->buffer_length = sizeof(urb->buffer); */ + + /*endpoint->rcv_urb = urb; */ + omap1510_prepare_endpoint_for_rx (ep_addr); + } + } + } +} + +/** + * udc_disable_ep - disable endpoint + * @ep: + * + * Disable specified endpoint + */ +#if 0 +void udc_disable_ep (unsigned int ep_addr) +{ + /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ + int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + struct usb_endpoint_instance *endpoint = omap1510_find_ep (ep_addr); /*udc_device->bus->endpoint_array + ep; */ + + UDCDBGA ("disable ep_addr %d", ep_addr); + + if (!ep_num) { + /* nothing to do for endpoint 0 */ ; + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + if (endpoint->tx_packetSize) { + /* we have a valid tx endpoint */ + /*usbd_flush_tx(endpoint); */ + endpoint->tx_urb = NULL; + } + } else { + if (endpoint->rcv_packetSize) { + /* we have a valid rx endpoint */ + /*usbd_flush_rcv(endpoint); */ + endpoint->rcv_urb = NULL; + } + } +} +#endif + +/* ************************************************************************** */ + +/** + * udc_connected - is the USB cable connected + * + * Return non-zero if cable is connected. + */ +#if 0 +int udc_connected (void) +{ + return ((inw (UDC_DEVSTAT) & UDC_ATT) == UDC_ATT); +} +#endif + +/* Turn on the USB connection by enabling the pullup resistor */ +void udc_connect (void) +{ + UDCDBG ("connect, enable Pullup"); + outl (0x00000018, FUNC_MUX_CTRL_D); +} + +/* Turn off the USB connection by disabling the pullup resistor */ +void udc_disconnect (void) +{ + UDCDBG ("disconnect, disable Pullup"); + outl (0x00000000, FUNC_MUX_CTRL_D); +} + +/* ************************************************************************** */ + + +/* + * udc_disable_interrupts - disable interrupts + * switch off interrupts + */ +#if 0 +void udc_disable_interrupts (struct usb_device_instance *device) +{ + UDCDBG ("disabling all interrupts"); + outw (0, UDC_IRQ_EN); +} +#endif + +/* ************************************************************************** */ + +/** + * udc_ep0_packetsize - return ep0 packetsize + */ +#if 0 +int udc_ep0_packetsize (void) +{ + return EP0_PACKETSIZE; +} +#endif + +/* Switch on the UDC */ +void udc_enable (struct usb_device_instance *device) +{ + UDCDBGA ("enable device %p, status %d", device, device->status); + + /* initialize driver state variables */ + udc_devstat = 0; + + /* Save the device structure pointer */ + udc_device = device; + + /* Setup ep0 urb */ + if (!ep0_urb) { + ep0_urb = + usbd_alloc_urb (udc_device, + udc_device->bus->endpoint_array); + } else { + serial_printf ("udc_enable: ep0_urb already allocated %p\n", + ep0_urb); + } + + UDCDBG ("Check clock status"); + UDCREG (STATUS_REQ); + + /* The VBUS_MODE bit selects whether VBUS detection is done via + * software (1) or hardware (0). When software detection is + * selected, VBUS_CTRL selects whether USB is not connected (0) + * or connected (1). + */ + outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_CTRL | UDC_VBUS_MODE, + FUNC_MUX_CTRL_0); + UDCREGL (FUNC_MUX_CTRL_0); + + omap1510_configure_device (device); +} + +/* Switch off the UDC */ +void udc_disable (void) +{ + UDCDBG ("disable UDC"); + + omap1510_deconfigure_device (); + + /* The VBUS_MODE bit selects whether VBUS detection is done via + * software (1) or hardware (0). When software detection is + * selected, VBUS_CTRL selects whether USB is not connected (0) + * or connected (1). + */ + outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); + outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); + UDCREGL (FUNC_MUX_CTRL_0); + + /* Free ep0 URB */ + if (ep0_urb) { + /*usbd_dealloc_urb(ep0_urb); */ + ep0_urb = NULL; + } + + /* Reset device pointer. + * We ought to do this here to balance the initialization of udc_device + * in udc_enable, but some of our other exported functions get called + * by the bus interface driver after udc_disable, so we have to hang on + * to the device pointer to avoid a null pointer dereference. */ + /* udc_device = NULL; */ +} + +/** + * udc_startup - allow udc code to do any additional startup + */ +void udc_startup_events (struct usb_device_instance *device) +{ + /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ + usbd_device_event_irq (device, DEVICE_INIT, 0); + + /* The DEVICE_CREATE event puts the USB device in the state + * STATE_ATTACHED. + */ + usbd_device_event_irq (device, DEVICE_CREATE, 0); + + /* Some USB controller driver implementations signal + * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. + * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, + * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. + * The OMAP USB client controller has the capability to detect when the + * USB cable is connected to a powered USB bus via the ATT bit in the + * DEVSTAT register, so we will defer the DEVICE_HUB_CONFIGURED and + * DEVICE_RESET events until later. + */ + + udc_enable (device); +} + +#endif diff --git a/drivers/usbtty.c b/drivers/usbtty.c new file mode 100644 index 0000000..ce4a12e --- /dev/null +++ b/drivers/usbtty.c @@ -0,0 +1,665 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#ifdef CONFIG_USB_TTY + +#include +#include +#include "usbtty.h" + +#if 0 +#define TTYDBG(fmt,args...) serial_printf("[%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args) +#else +#define TTYDBG(fmt,args...) do{}while(0) +#endif + +#if 0 +#define TTYERR(fmt,args...) serial_printf("ERROR![%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args) +#else +#define TTYERR(fmt,args...) do{}while(0) +#endif + +/* + * Buffers to hold input and output data + */ +#define USBTTY_BUFFER_SIZE 256 +static circbuf_t usbtty_input; +static circbuf_t usbtty_output; + + +/* + * Instance variables + */ +static device_t usbttydev; +static struct usb_device_instance device_instance[1]; +static struct usb_bus_instance bus_instance[1]; +static struct usb_configuration_instance config_instance[NUM_CONFIGS]; +static struct usb_interface_instance interface_instance[NUM_INTERFACES]; +static struct usb_alternate_instance alternate_instance[NUM_INTERFACES]; +static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS+1]; /* one extra for control endpoint */ + +/* + * Static allocation of urbs + */ +#define RECV_ENDPOINT 1 +#define TX_ENDPOINT 2 + +/* + * Global flag + */ +int usbtty_configured_flag = 0; + + +/* + * Serial number + */ +static char serial_number[16]; + +/* + * Descriptors + */ +static u8 wstrLang[4] = {4,USB_DT_STRING,0x9,0x4}; +static u8 wstrManufacturer[2 + 2*(sizeof(CONFIG_USBD_MANUFACTURER)-1)]; +static u8 wstrProduct[2 + 2*(sizeof(CONFIG_USBD_PRODUCT_NAME)-1)]; +static u8 wstrSerial[2 + 2*(sizeof(serial_number) - 1)]; +static u8 wstrConfiguration[2 + 2*(sizeof(CONFIG_USBD_CONFIGURATION_STR)-1)]; +static u8 wstrInterface[2 + 2*(sizeof(CONFIG_USBD_INTERFACE_STR)-1)]; + +static struct usb_string_descriptor *usbtty_string_table[] = { + (struct usb_string_descriptor*)wstrLang, + (struct usb_string_descriptor*)wstrManufacturer, + (struct usb_string_descriptor*)wstrProduct, + (struct usb_string_descriptor*)wstrSerial, + (struct usb_string_descriptor*)wstrConfiguration, + (struct usb_string_descriptor*)wstrInterface +}; +extern struct usb_string_descriptor **usb_strings; /* defined and used by omap1510_ep0.c */ + +static struct usb_device_descriptor device_descriptor = { + bLength: sizeof(struct usb_device_descriptor), + bDescriptorType: USB_DT_DEVICE, + bcdUSB: USB_BCD_VERSION, + bDeviceClass: USBTTY_DEVICE_CLASS, + bDeviceSubClass: USBTTY_DEVICE_SUBCLASS, + bDeviceProtocol: USBTTY_DEVICE_PROTOCOL, + bMaxPacketSize0: EP0_MAX_PACKET_SIZE, + idVendor: CONFIG_USBD_VENDORID, + idProduct: CONFIG_USBD_PRODUCTID, + bcdDevice: USBTTY_BCD_DEVICE, + iManufacturer: STR_MANUFACTURER, + iProduct: STR_PRODUCT, + iSerialNumber: STR_SERIAL, + bNumConfigurations: NUM_CONFIGS + }; +static struct usb_configuration_descriptor config_descriptors[NUM_CONFIGS] = { + { + bLength: sizeof(struct usb_configuration_descriptor), + bDescriptorType: USB_DT_CONFIG, + wTotalLength: (sizeof(struct usb_configuration_descriptor)*NUM_CONFIGS) + + (sizeof(struct usb_interface_descriptor)*NUM_INTERFACES) + + (sizeof(struct usb_endpoint_descriptor)*NUM_ENDPOINTS), + bNumInterfaces: NUM_INTERFACES, + bConfigurationValue: 1, + iConfiguration: STR_CONFIG, + bmAttributes: BMATTRIBUTE_SELF_POWERED | BMATTRIBUTE_RESERVED, + bMaxPower: USBTTY_MAXPOWER + }, +}; +static struct usb_interface_descriptor interface_descriptors[NUM_INTERFACES] = { + { + bLength: sizeof(struct usb_interface_descriptor), + bDescriptorType: USB_DT_INTERFACE, + bInterfaceNumber: 0, + bAlternateSetting: 0, + bNumEndpoints: NUM_ENDPOINTS, + bInterfaceClass: USBTTY_INTERFACE_CLASS, + bInterfaceSubClass: USBTTY_INTERFACE_SUBCLASS, + bInterfaceProtocol: USBTTY_INTERFACE_PROTOCOL, + iInterface: STR_INTERFACE + }, +}; +static struct usb_endpoint_descriptor ep_descriptors[NUM_ENDPOINTS] = { + { + bLength: sizeof(struct usb_endpoint_descriptor), + bDescriptorType: USB_DT_ENDPOINT, + bEndpointAddress: CONFIG_USBD_SERIAL_OUT_ENDPOINT | USB_DIR_OUT, + bmAttributes: USB_ENDPOINT_XFER_BULK, + wMaxPacketSize: CONFIG_USBD_SERIAL_OUT_PKTSIZE, + bInterval: 0 + }, + { + bLength: sizeof(struct usb_endpoint_descriptor), + bDescriptorType: USB_DT_ENDPOINT, + bEndpointAddress: CONFIG_USBD_SERIAL_IN_ENDPOINT | USB_DIR_IN, + bmAttributes: USB_ENDPOINT_XFER_BULK, + wMaxPacketSize: CONFIG_USBD_SERIAL_IN_PKTSIZE, + bInterval: 0 + }, + { + bLength: sizeof(struct usb_endpoint_descriptor), + bDescriptorType: USB_DT_ENDPOINT, + bEndpointAddress: CONFIG_USBD_SERIAL_INT_ENDPOINT | USB_DIR_IN, + bmAttributes: USB_ENDPOINT_XFER_INT, + wMaxPacketSize: CONFIG_USBD_SERIAL_INT_PKTSIZE, + bInterval: 0 + }, +}; +static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS] = { + &(ep_descriptors[0]), + &(ep_descriptors[1]), + &(ep_descriptors[2]), +}; + +/* utility function for converting char* to wide string used by USB */ +static void str2wide (char *str, u16 * wide) +{ + int i; + + for (i = 0; i < strlen (str) && str[i]; i++) + wide[i] = (u16) str[i]; +} + +/* + * Prototypes + */ +static void usbtty_init_strings (void); +static void usbtty_init_instances (void); +static void usbtty_init_endpoints (void); + +static void usbtty_event_handler (struct usb_device_instance *device, + usb_device_event_t event, int data); +static int usbtty_configured (void); + +static int write_buffer (circbuf_t * buf); +static int fill_buffer (circbuf_t * buf); + +void usbtty_poll (void); +static void pretend_interrupts (void); + + +/* + * Test whether a character is in the RX buffer + */ +int usbtty_tstc (void) +{ + usbtty_poll (); + return (usbtty_input.size > 0); +} + +/* + * Read a single byte from the usb client port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int usbtty_getc (void) +{ + char c; + + while (usbtty_input.size <= 0) { + usbtty_poll (); + } + + buf_pop (&usbtty_input, &c, 1); + return c; +} + +/* + * Output a single byte to the usb client port. + */ +void usbtty_putc (const char c) +{ + buf_push (&usbtty_output, &c, 1); + /* If \n, also do \r */ + if (c == '\n') + buf_push (&usbtty_output, "\r", 1); + + /* Poll at end to handle new data... */ + if ((usbtty_output.size + 2) >= usbtty_output.totalsize) { + usbtty_poll (); + } +} + + +/* usbtty_puts() helper function for finding the next '\n' in a string */ +static int next_nl_pos (const char *s) +{ + int i; + + for (i = 0; s[i] != '\0'; i++) { + if (s[i] == '\n') + return i; + } + return i; +} + +/* + * Output a string to the usb client port. + */ +static void __usbtty_puts (const char *str, int len) +{ + int maxlen = usbtty_output.totalsize; + int space, n; + + /* break str into chunks < buffer size, if needed */ + while (len > 0) { + space = maxlen - usbtty_output.size; + + /* Empty buffer here, if needed, to ensure space... */ + if (space <= 0) { + write_buffer (&usbtty_output); + space = maxlen - usbtty_output.size; + if (space <= 0) { + space = len; /* allow old data to be overwritten. */ + } + } + + n = MIN (space, MIN (len, maxlen)); + buf_push (&usbtty_output, str, n); + + str += n; + len -= n; + } +} + +void usbtty_puts (const char *str) +{ + int n; + int len = strlen (str); + + /* add '\r' for each '\n' */ + while (len > 0) { + n = next_nl_pos (str); + + if (str[n] == '\n') { + __usbtty_puts (str, n + 1); + __usbtty_puts ("\r", 1); + str += (n + 1); + len -= (n + 1); + } else { + /* No \n found. All done. */ + __usbtty_puts (str, n); + break; + } + } + + /* Poll at end to handle new data... */ + usbtty_poll (); +} + +/* + * Initialize the usb client port. + * + */ +int drv_usbtty_init (void) +{ + int rc; + char * sn; + int snlen; + + if (!(sn = getenv("serial#"))) { + sn = "000000000000"; + } + snlen = strlen(sn); + if (snlen > sizeof(serial_number) - 1) { + printf ("Warning: serial number %s is too long (%d > %d)\n", + sn, snlen, sizeof(serial_number) - 1); + snlen = sizeof(serial_number) - 1; + } + memcpy (serial_number, sn, snlen); + serial_number[snlen] = '\0'; + + /* prepare buffers... */ + buf_init (&usbtty_input, USBTTY_BUFFER_SIZE); + buf_init (&usbtty_output, USBTTY_BUFFER_SIZE); + + /* Now, set up USB controller and infrastructure */ + udc_init (); /* Basic USB initialization */ + + usbtty_init_strings (); + usbtty_init_instances (); + + udc_startup_events (device_instance); /* Enable our device, initialize udc pointers */ + udc_connect (); /* Enable pullup for host detection */ + + usbtty_init_endpoints (); + + /* Device initialization */ + memset (&usbttydev, 0, sizeof (usbttydev)); + + strcpy (usbttydev.name, "usbtty"); + usbttydev.ext = 0; /* No extensions */ + usbttydev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT; + usbttydev.tstc = usbtty_tstc; /* 'tstc' function */ + usbttydev.getc = usbtty_getc; /* 'getc' function */ + usbttydev.putc = usbtty_putc; /* 'putc' function */ + usbttydev.puts = usbtty_puts; /* 'puts' function */ + + rc = device_register (&usbttydev); + + return (rc == 0) ? 1 : rc; +} + +static void usbtty_init_strings (void) +{ + struct usb_string_descriptor *string; + + string = (struct usb_string_descriptor *) wstrManufacturer; + string->bLength = sizeof (wstrManufacturer); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_MANUFACTURER, string->wData); + + string = (struct usb_string_descriptor *) wstrProduct; + string->bLength = sizeof (wstrProduct); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_PRODUCT_NAME, string->wData); + + string = (struct usb_string_descriptor *) wstrSerial; + string->bLength = 2 + 2*strlen(serial_number); + string->bDescriptorType = USB_DT_STRING; + str2wide (serial_number, string->wData); + + string = (struct usb_string_descriptor *) wstrConfiguration; + string->bLength = sizeof (wstrConfiguration); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_CONFIGURATION_STR, string->wData); + + string = (struct usb_string_descriptor *) wstrInterface; + string->bLength = sizeof (wstrInterface); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_INTERFACE_STR, string->wData); + + /* Now, initialize the string table for ep0 handling */ + usb_strings = usbtty_string_table; +} + +static void usbtty_init_instances (void) +{ + int i; + + /* initialize device instance */ + memset (device_instance, 0, sizeof (struct usb_device_instance)); + device_instance->device_state = STATE_INIT; + device_instance->device_descriptor = &device_descriptor; + device_instance->event = usbtty_event_handler; + device_instance->bus = bus_instance; + device_instance->configurations = NUM_CONFIGS; + device_instance->configuration_instance_array = config_instance; + + /* initialize bus instance */ + memset (bus_instance, 0, sizeof (struct usb_bus_instance)); + bus_instance->device = device_instance; + bus_instance->endpoint_array = endpoint_instance; + bus_instance->max_endpoints = 1; + bus_instance->maxpacketsize = 64; + bus_instance->serial_number_str = serial_number; + + /* configuration instance */ + memset (config_instance, 0, + sizeof (struct usb_configuration_instance)); + config_instance->interfaces = NUM_INTERFACES; + config_instance->configuration_descriptor = config_descriptors; + config_instance->interface_instance_array = interface_instance; + + /* interface instance */ + memset (interface_instance, 0, + sizeof (struct usb_interface_instance)); + interface_instance->alternates = 1; + interface_instance->alternates_instance_array = alternate_instance; + + /* alternates instance */ + memset (alternate_instance, 0, + sizeof (struct usb_alternate_instance)); + alternate_instance->interface_descriptor = interface_descriptors; + alternate_instance->endpoints = NUM_ENDPOINTS; + alternate_instance->endpoints_descriptor_array = ep_descriptor_ptrs; + + /* endpoint instances */ + memset (&endpoint_instance[0], 0, + sizeof (struct usb_endpoint_instance)); + endpoint_instance[0].endpoint_address = 0; + endpoint_instance[0].rcv_packetSize = EP0_MAX_PACKET_SIZE; + endpoint_instance[0].rcv_attributes = USB_ENDPOINT_XFER_CONTROL; + endpoint_instance[0].tx_packetSize = EP0_MAX_PACKET_SIZE; + endpoint_instance[0].tx_attributes = USB_ENDPOINT_XFER_CONTROL; + udc_setup_ep (device_instance, 0, &endpoint_instance[0]); + + for (i = 1; i <= NUM_ENDPOINTS; i++) { + memset (&endpoint_instance[i], 0, + sizeof (struct usb_endpoint_instance)); + + endpoint_instance[i].endpoint_address = + ep_descriptors[i - 1].bEndpointAddress; + + endpoint_instance[i].rcv_packetSize = + ep_descriptors[i - 1].wMaxPacketSize; + endpoint_instance[i].rcv_attributes = + ep_descriptors[i - 1].bmAttributes; + + endpoint_instance[i].tx_packetSize = + ep_descriptors[i - 1].wMaxPacketSize; + endpoint_instance[i].tx_attributes = + ep_descriptors[i - 1].bmAttributes; + + urb_link_init (&endpoint_instance[i].rcv); + urb_link_init (&endpoint_instance[i].rdy); + urb_link_init (&endpoint_instance[i].tx); + urb_link_init (&endpoint_instance[i].done); + + if (endpoint_instance[i].endpoint_address & USB_DIR_IN) + endpoint_instance[i].tx_urb = + usbd_alloc_urb (device_instance, + &endpoint_instance[i]); + else + endpoint_instance[i].rcv_urb = + usbd_alloc_urb (device_instance, + &endpoint_instance[i]); + } +} + +static void usbtty_init_endpoints (void) +{ + int i; + + bus_instance->max_endpoints = NUM_ENDPOINTS + 1; + for (i = 0; i <= NUM_ENDPOINTS; i++) { + udc_setup_ep (device_instance, i, &endpoint_instance[i]); + } +} + + +/*********************************************************************************/ + +static struct urb *next_urb (struct usb_device_instance *device, + struct usb_endpoint_instance *endpoint) +{ + struct urb *current_urb = NULL; + int space; + + /* If there's a queue, then we should add to the last urb */ + if (!endpoint->tx_queue) { + current_urb = endpoint->tx_urb; + } else { + /* Last urb from tx chain */ + current_urb = + p2surround (struct urb, link, endpoint->tx.prev); + } + + /* Make sure this one has enough room */ + space = current_urb->buffer_length - current_urb->actual_length; + if (space > 0) { + return current_urb; + } else { /* No space here */ + /* First look at done list */ + current_urb = first_urb_detached (&endpoint->done); + if (!current_urb) { + current_urb = usbd_alloc_urb (device, endpoint); + } + + urb_append (&endpoint->tx, current_urb); + endpoint->tx_queue++; + } + return current_urb; +} + +static int write_buffer (circbuf_t * buf) +{ + if (!usbtty_configured ()) { + return 0; + } + + if (buf->size) { + + struct usb_endpoint_instance *endpoint = + &endpoint_instance[TX_ENDPOINT]; + struct urb *current_urb = NULL; + char *dest; + + int space_avail; + int popnum, popped; + int total = 0; + + /* Break buffer into urb sized pieces, and link each to the endpoint */ + while (buf->size > 0) { + current_urb = next_urb (device_instance, endpoint); + if (!current_urb) { + TTYERR ("current_urb is NULL, buf->size %d\n", + buf->size); + return total; + } + + dest = current_urb->buffer + + current_urb->actual_length; + + space_avail = + current_urb->buffer_length - + current_urb->actual_length; + popnum = MIN (space_avail, buf->size); + if (popnum == 0) + break; + + popped = buf_pop (buf, dest, popnum); + if (popped == 0) + break; + current_urb->actual_length += popped; + total += popped; + + /* If endpoint->last == 0, then transfers have not started on this endpoint */ + if (endpoint->last == 0) { + udc_endpoint_write (endpoint); + } + + } /* end while */ + return total; + } /* end if tx_urb */ + + return 0; +} + +static int fill_buffer (circbuf_t * buf) +{ + struct usb_endpoint_instance *endpoint = + &endpoint_instance[RECV_ENDPOINT]; + + if (endpoint->rcv_urb && endpoint->rcv_urb->actual_length) { + unsigned int nb = endpoint->rcv_urb->actual_length; + char *src = (char *) endpoint->rcv_urb->buffer; + + buf_push (buf, src, nb); + endpoint->rcv_urb->actual_length = 0; + + return nb; + } + + return 0; +} + +static int usbtty_configured (void) +{ + return usbtty_configured_flag; +} + +/*********************************************************************************/ + +static void usbtty_event_handler (struct usb_device_instance *device, + usb_device_event_t event, int data) +{ + switch (event) { + case DEVICE_RESET: + case DEVICE_BUS_INACTIVE: + usbtty_configured_flag = 0; + break; + case DEVICE_CONFIGURED: + usbtty_configured_flag = 1; + break; + + case DEVICE_ADDRESS_ASSIGNED: + usbtty_init_endpoints (); + + default: + break; + } +} + +/*********************************************************************************/ + + +/* + * Since interrupt handling has not yet been implemented, we use this function + * to handle polling. This is called by the tstc,getc,putc,puts routines to + * update the USB state. + */ +void usbtty_poll (void) +{ + /* New interrupts? */ + pretend_interrupts (); + + /* Write any output data to host buffer (do this before checking interrupts to avoid missing one) */ + if (usbtty_configured ()) { + write_buffer (&usbtty_output); + } + + /* New interrupts? */ + pretend_interrupts (); + + /* Check for new data from host.. (do this after checking interrupts to get latest data) */ + if (usbtty_configured ()) { + fill_buffer (&usbtty_input); + } + + /* New interrupts? */ + pretend_interrupts (); +} + +static void pretend_interrupts (void) +{ + /* Loop while we have interrupts. + * If we don't do this, the input chain + * polling delay is likely to miss + * host requests. + */ + while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) { + /* Handle any new IRQs */ + omap1510_udc_irq (); + omap1510_udc_noniso_irq (); + } +} +#endif diff --git a/drivers/usbtty.h b/drivers/usbtty.h new file mode 100644 index 0000000..79c2fe5 --- /dev/null +++ b/drivers/usbtty.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __USB_TTY_H__ +#define __USB_TTY_H__ + + +#include "usbdcore.h" +#include "usbdcore_omap1510.h" + + +#define NUM_CONFIGS 1 +#define NUM_INTERFACES 1 +#define NUM_ENDPOINTS 3 + +#define EP0_MAX_PACKET_SIZE 64 + +#define CONFIG_USBD_CONFIGURATION_STR "TTY via USB" +#define CONFIG_USBD_INTERFACE_STR "Simple Serial Data Interface - Bulk Mode" + + +#define CONFIG_USBD_SERIAL_OUT_ENDPOINT 2 +#define CONFIG_USBD_SERIAL_OUT_PKTSIZE 64 +#define CONFIG_USBD_SERIAL_IN_ENDPOINT 1 +#define CONFIG_USBD_SERIAL_IN_PKTSIZE 64 +#define CONFIG_USBD_SERIAL_INT_ENDPOINT 5 +#define CONFIG_USBD_SERIAL_INT_PKTSIZE 16 + + +#define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS +#define USBTTY_DEVICE_SUBCLASS COMMUNICATIONS_NO_SUBCLASS +#define USBTTY_DEVICE_PROTOCOL COMMUNICATIONS_NO_PROTOCOL + +#define USBTTY_INTERFACE_CLASS 0xFF /* Vendor Specific */ +#define USBTTY_INTERFACE_SUBCLASS 0x02 +#define USBTTY_INTERFACE_PROTOCOL 0x01 + +#define USBTTY_BCD_DEVICE 0x0 +#define USBTTY_MAXPOWER 0x0 + +#define STR_MANUFACTURER 1 +#define STR_PRODUCT 2 +#define STR_SERIAL 3 +#define STR_CONFIG 4 +#define STR_INTERFACE 5 + +#endif diff --git a/drivers/videomodes.c b/drivers/videomodes.c new file mode 100644 index 0000000..c81e5bc --- /dev/null +++ b/drivers/videomodes.c @@ -0,0 +1,208 @@ +/* + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges , + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + Get Parameters for the video mode: + The default video mode can be defined in CFG_DEFAULT_VIDEO_MODE. + If undefined, default video mode is set to 0x301 + Parameters can be set via the variable "videomode" in the environment. + 2 diferent ways are possible: + "videomode=301" - 301 is a hexadecimal number describing the VESA + mode. Following modes are implemented: + + Colors 640x480 800x600 1024x768 1152x864 1280x1024 + --------+--------------------------------------------- + 8 bits | 0x301 0x303 0x305 0x161 0x307 + 15 bits | 0x310 0x313 0x316 0x162 0x319 + 16 bits | 0x311 0x314 0x317 0x163 0x31A + 24 bits | 0x312 0x315 0x318 ? 0x31B + --------+--------------------------------------------- + "videomode=bootargs" + - the parameters are parsed from the bootargs. + The format is "NAME:VALUE,NAME:VALUE" etc. + Ex.: + "bootargs=video=ctfb:x:800,y:600,depth:16,pclk:25000" + Parameters not included in the list will be taken from + the default mode, which is one of the following: + mode:0 640x480x24 + mode:1 800x600x16 + mode:2 1024x768x8 + mode:3 960x720x24 + mode:4 1152x864x16 + mode:5 1280x1024x8 + + if "mode" is not provided within the parameter list, + mode:0 is assumed. + Following parameters are supported: + x xres = visible resolution horizontal + y yres = visible resolution vertical + pclk pixelclocks in pico sec + le left_marging time from sync to picture in pixelclocks + ri right_marging time from picture to sync in pixelclocks + up upper_margin time from sync to picture + lo lower_margin + hs hsync_len length of horizontal sync + vs vsync_len length of vertical sync + sync see FB_SYNC_* + vmode see FB_VMODE_* + depth Color depth in bits per pixel + All other parameters in the variable bootargs are ignored. + It is also possible to set the parameters direct in the + variable "videomode", or in another variable i.e. + "myvideo" and setting the variable "videomode=myvideo".. +****************************************************************************/ + +#include +#include "videomodes.h" + +const struct ctfb_vesa_modes vesa_modes[VESA_MODES_COUNT] = { + {0x301, RES_MODE_640x480, 8}, + {0x310, RES_MODE_640x480, 15}, + {0x311, RES_MODE_640x480, 16}, + {0x312, RES_MODE_640x480, 24}, + {0x303, RES_MODE_800x600, 8}, + {0x313, RES_MODE_800x600, 15}, + {0x314, RES_MODE_800x600, 16}, + {0x315, RES_MODE_800x600, 24}, + {0x305, RES_MODE_1024x768, 8}, + {0x316, RES_MODE_1024x768, 15}, + {0x317, RES_MODE_1024x768, 16}, + {0x318, RES_MODE_1024x768, 24}, + {0x161, RES_MODE_1152x864, 8}, + {0x162, RES_MODE_1152x864, 15}, + {0x163, RES_MODE_1152x864, 16}, + {0x307, RES_MODE_1280x1024, 8}, + {0x319, RES_MODE_1280x1024, 15}, + {0x31A, RES_MODE_1280x1024, 16}, + {0x31B, RES_MODE_1280x1024, 24}, +}; +const struct ctfb_res_modes res_mode_init[RES_MODES_COUNT] = { + /* x y pixclk le ri up lo hs vs s vmode */ + {640, 480, 39721, 40, 24, 32, 11, 96, 2, 0, FB_VMODE_NONINTERLACED}, + {800, 600, 27778, 64, 24, 22, 1, 72, 2, 0, FB_VMODE_NONINTERLACED}, + {1024, 768, 15384, 168, 8, 29, 3, 144, 4, 0, FB_VMODE_NONINTERLACED}, + {960, 720, 13100, 160, 40, 32, 8, 80, 4, 0, FB_VMODE_NONINTERLACED}, + {1152, 864, 12004, 200, 64, 32, 16, 80, 4, 0, FB_VMODE_NONINTERLACED}, + {1280, 1024, 9090, 200, 48, 26, 1, 184, 3, 0, FB_VMODE_NONINTERLACED}, +}; + +/************************************************************************ + * Get Parameters for the video mode: + */ +/********************************************************************* + * returns the length to the next seperator + */ +static int +video_get_param_len (char *start, char sep) +{ + int i = 0; + while ((*start != 0) && (*start != sep)) { + start++; + i++; + } + return i; +} + +static int +video_search_param (char *start, char *param) +{ + int len, totallen, i; + char *p = start; + len = strlen (param); + totallen = len + strlen (start); + for (i = 0; i < totallen; i++) { + if (strncmp (p++, param, len) == 0) + return (i); + } + return -1; +} + +/*************************************************************** + * Get parameter via the environment as it is done for the + * linux kernel i.e: + * video=ctfb:x:800,xv:1280,y:600,yv:1024,depth:16,mode:0,pclk:25000, + * le:56,ri:48,up:26,lo:5,hs:152,vs:2,sync:0,vmode:0,accel:0 + * + * penv is a pointer to the environment, containing the string, or the name of + * another environment variable. It could even be the term "bootargs" + */ + +#define GET_OPTION(name,var) \ + if(strncmp(p,name,strlen(name))==0) { \ + val_s=p+strlen(name); \ + var=simple_strtoul(val_s, NULL, 10); \ + } + +int video_get_params (struct ctfb_res_modes *pPar, char *penv) +{ + char *p, *s, *val_s; + int i = 0, t; + int bpp; + int mode; + /* first search for the environment containing the real param string */ + s = penv; + if ((p = getenv (s)) != NULL) { + s = p; + } + /* in case of the bootargs line, we have to start + * after "video=ctfb:" + */ + i = video_search_param (s, "video=ctfb:"); + if (i >= 0) { + s += i; + s += strlen ("video=ctfb:"); + } + /* search for mode as a default value */ + p = s; + t = 0; + mode = 0; /* default */ + while ((i = video_get_param_len (p, ',')) != 0) { + GET_OPTION ("mode:", mode) + p += i; + if (*p != 0) + p++; /* skip ',' */ + } + if (mode >= RES_MODES_COUNT) + mode = 0; + *pPar = res_mode_init[mode]; /* copy default values */ + bpp = 24 - ((mode % 3) * 8); + p = s; /* restart */ + while ((i = video_get_param_len (p, ',')) != 0) { + GET_OPTION ("x:", pPar->xres) + GET_OPTION ("y:", pPar->yres) + GET_OPTION ("le:", pPar->left_margin) + GET_OPTION ("ri:", pPar->right_margin) + GET_OPTION ("up:", pPar->upper_margin) + GET_OPTION ("lo:", pPar->lower_margin) + GET_OPTION ("hs:", pPar->hsync_len) + GET_OPTION ("vs:", pPar->vsync_len) + GET_OPTION ("sync:", pPar->sync) + GET_OPTION ("vmode:", pPar->vmode) + GET_OPTION ("pclk:", pPar->pixclock) + GET_OPTION ("depth:", bpp) + p += i; + if (*p != 0) + p++; /* skip ',' */ + } + return bpp; +} diff --git a/drivers/videomodes.h b/drivers/videomodes.h new file mode 100644 index 0000000..e2dffe7 --- /dev/null +++ b/drivers/videomodes.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges , + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef CFG_DEFAULT_VIDEO_MODE +#define CFG_DEFAULT_VIDEO_MODE 0x301 +#endif + +/* Some mode definitions */ +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 + +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ + + +/****************************************************************** + * Resolution Struct + ******************************************************************/ +struct ctfb_res_modes { + int xres; /* visible resolution */ + int yres; + /* Timing: All values in pixclocks, except pixclock (of course) */ + int pixclock; /* pixel clock in ps (pico seconds) */ + int left_margin; /* time from sync to picture */ + int right_margin; /* time from picture to sync */ + int upper_margin; /* time from sync to picture */ + int lower_margin; + int hsync_len; /* length of horizontal sync */ + int vsync_len; /* length of vertical sync */ + int sync; /* see FB_SYNC_* */ + int vmode; /* see FB_VMODE_* */ +}; + +/****************************************************************** + * Vesa Mode Struct + ******************************************************************/ +struct ctfb_vesa_modes { + int vesanr; /* Vesa number as in LILO (VESA Nr + 0x200} */ + int resindex; /* index to resolution struct */ + int bits_per_pixel; /* bpp */ +}; + +#define RES_MODE_640x480 0 +#define RES_MODE_800x600 1 +#define RES_MODE_1024x768 2 +#define RES_MODE_960_720 3 +#define RES_MODE_1152x864 4 +#define RES_MODE_1280x1024 5 +#define RES_MODES_COUNT 6 + +#define VESA_MODES_COUNT 19 + +extern const struct ctfb_vesa_modes vesa_modes[]; +extern const struct ctfb_res_modes res_mode_init[]; + +int video_get_params (struct ctfb_res_modes *pPar, char *penv); diff --git a/drivers/w83c553f.c b/drivers/w83c553f.c new file mode 100644 index 0000000..5d82ed4 --- /dev/null +++ b/drivers/w83c553f.c @@ -0,0 +1,226 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Initialisation of the PCI-to-ISA bridge and disabling the BIOS + * write protection (for flash) in function 0 of the chip. + * Enabling function 1 (IDE controller of the chip. + */ + +#include +#include + +#ifdef CFG_WINBOND_83C553 + +#include +#include + +#include + +#define out8(addr,val) do { \ + out_8((u8*) (addr),(val)); udelay(1); \ + } while (0) +#define out16(addr,val) do { \ + out_be16((u16*) (addr),(val)); udelay(1); \ + } while (0) + +extern uint ide_bus_offset[CFG_IDE_MAXBUS]; + +void initialise_pic(void); +void initialise_dma(void); + +void initialise_w83c553f(void) +{ + pci_dev_t devbusfn; + unsigned char reg8; + unsigned short reg16; + unsigned int reg32; + + devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0); + if (devbusfn == -1) + { + printf("Error: Cannot find W83C553F controller on any PCI bus."); + return; + } + + pci_read_config_word(devbusfn, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + pci_write_config_word(devbusfn, PCI_COMMAND, reg16); + + pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8); + /* 16 MB ISA memory space */ + reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); + reg8 &= ~IPADCR_MBE512; + pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8); + + pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8); + /* switch off BIOS write protection */ + reg8 |= CSCR_UBIOSCSE; + reg8 &= ~CSCR_BIOSWP; + pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8); + + /* + * Interrupt routing: + * - IDE -> IRQ 9/0 + * - INTA -> IRQ 10 + * - INTB -> IRQ 11 + * - INTC -> IRQ 14 + * - INTD -> IRQ 15 + */ + pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90); + pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF); + + /* + * Read IDE bus offsets from function 1 device. + * We must unmask the LSB indicating that ist is an IO address. + */ + devbusfn |= PCI_BDF(0,0,1); + + /* + * Switch off legacy IRQ for IDE and IDE port 1. + */ + pci_write_config_byte(devbusfn, 0x09, 0x8F); + + pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32); + reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16); + pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32); + + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]); + ide_bus_offset[0] &= ~1; +#if CFG_IDE_MAXBUS > 1 + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]); + ide_bus_offset[1] &= ~1; +#endif + + /* + * Enable function 1, IDE -> busmastering and IO space access + */ + pci_read_config_word(devbusfn, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word(devbusfn, PCI_COMMAND, reg16); + + /* + * Initialise ISA interrupt controller + */ + initialise_pic(); + + /* + * Initialise DMA controller + */ + initialise_dma(); +} + +void initialise_pic(void) +{ + out8(W83C553F_PIC1_ICW1, 0x11); + out8(W83C553F_PIC1_ICW2, 0x08); + out8(W83C553F_PIC1_ICW3, 0x04); + out8(W83C553F_PIC1_ICW4, 0x01); + out8(W83C553F_PIC1_OCW1, 0xfb); + out8(W83C553F_PIC1_ELC, 0x20); + + out8(W83C553F_PIC2_ICW1, 0x11); + out8(W83C553F_PIC2_ICW2, 0x08); + out8(W83C553F_PIC2_ICW3, 0x02); + out8(W83C553F_PIC2_ICW4, 0x01); + out8(W83C553F_PIC2_OCW1, 0xff); + out8(W83C553F_PIC2_ELC, 0xce); + + out8(W83C553F_TMR1_CMOD, 0x74); + + out8(W83C553F_PIC2_OCW1, 0x20); + out8(W83C553F_PIC1_OCW1, 0x20); + + out8(W83C553F_PIC2_OCW1, 0x2b); + out8(W83C553F_PIC1_OCW1, 0x2b); +} + +void initialise_dma(void) +{ + unsigned int channel; + unsigned int rvalue1, rvalue2; + + /* perform a H/W reset of the devices */ + + out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00); + out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000); + + /* initialise all channels to a sane state */ + + for (channel = 0; channel < 4; channel++) { + /* + * dependent upon the channel, setup the specifics: + * + * demand + * address-increment + * autoinitialize-disable + * verify-transfer + */ + + switch (channel) { + case 0: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL); + break; + case 1: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); + break; + case 2: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); + break; + case 3: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); + break; + default: + rvalue1 = 0x00; + rvalue2 = 0x00; + break; + } + + /* write to write mode registers */ + + out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF); + out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF); + } + + /* enable all channels */ + + out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00); + out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000); + /* + * initialize the global DMA configuration + * + * DACK# active low + * DREQ active high + * fixed priority + * channel group enable + */ + + out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00); + out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000); +} + +#endif /* CFG_WINBOND_83C553 */ diff --git a/dtt/Makefile b/dtt/Makefile new file mode 100644 index 0000000..0a33478 --- /dev/null +++ b/dtt/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001 +# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +#CFLAGS += -DDEBUG + +LIB = libdtt.a + +OBJS = lm75.o ds1621.o adm1021.o + +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/dtt/adm1021.c b/dtt/adm1021.c new file mode 100644 index 0000000..14c38f0 --- /dev/null +++ b/dtt/adm1021.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2003 + * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au + * + * based on dtt/lm75.c which is ... + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Analog Devices's ADM1021 + * "Low Cost Microprocessor System Temperature Monitor" + */ + +#include + +#ifdef CONFIG_DTT_ADM1021 + +#include +#include + +typedef + struct { + uint i2c_addr:7; /* 7bit i2c chip address */ + uint conv_rate:3; /* conversion rate */ + uint enable_alert:1; /* enable alert output pin */ + uint enable_local:1; /* enable internal temp sensor */ + uint max_local:8; /* internal temp maximum */ + uint min_local:8; /* internal temp minimum */ + uint enable_remote:1; /* enable remote temp sensor */ + uint max_remote:8; /* remote temp maximum */ + uint min_remote:8; /* remote temp minimum */ + } +dtt_cfg_t; + +dtt_cfg_t dttcfg[] = CFG_DTT_ADM1021; + +int +dtt_read (int sensor, int reg) +{ + dtt_cfg_t *dcp = &dttcfg[sensor >> 1]; + uchar data; + + if (i2c_read(dcp->i2c_addr, reg, 1, &data, 1) != 0) + return -1; + + return (int)data; +} /* dtt_read() */ + +int +dtt_write (int sensor, int reg, int val) +{ + dtt_cfg_t *dcp = &dttcfg[sensor >> 1]; + uchar data; + + data = (uchar)(val & 0xff); + + if (i2c_write(dcp->i2c_addr, reg, 1, &data, 1) != 0) + return 1; + + return 0; +} /* dtt_write() */ + +static int +_dtt_init (int sensor) +{ + dtt_cfg_t *dcp = &dttcfg[sensor >> 1]; + int reg, val; + + if (((sensor & 1) == 0 ? dcp->enable_local : dcp->enable_remote) == 0) + return 1; /* sensor is disabled (or rather ignored) */ + + /* + * Setup High Limit register + */ + if ((sensor & 1) == 0) { + reg = DTT_WRITE_LOC_HIGHLIM; + val = dcp->max_local; + } + else { + reg = DTT_WRITE_REM_HIGHLIM; + val = dcp->max_remote; + } + if (dtt_write (sensor, reg, val) != 0) + return 1; + + /* + * Setup Low Limit register + */ + if ((sensor & 1) == 0) { + reg = DTT_WRITE_LOC_LOWLIM; + val = dcp->min_local; + } + else { + reg = DTT_WRITE_REM_LOWLIM; + val = dcp->min_remote; + } + if (dtt_write (sensor, reg, val) != 0) + return 1; + + /* shouldn't hurt if the rest gets done twice */ + + /* + * Setup Conversion Rate register + */ + if (dtt_write (sensor, DTT_WRITE_CONVRATE, dcp->conv_rate) != 0) + return 1; + + /* + * Setup configuraton register + */ + val = 0; /* running */ + if (dcp->enable_alert == 0) + val |= DTT_CONFIG_ALERT_MASKED; /* mask ALERT pin */ + if (dtt_write (sensor, DTT_WRITE_CONFIG, val) != 0) + return 1; + + return 0; +} /* _dtt_init() */ + +int +dtt_init (void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + const char *const header = "DTT: "; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf ("%s%d FAILED INIT\n", header, i+1); + else + printf ("%s%d is %i C\n", header, i+1, + dtt_get_temp(sensors[i])); + } + + return (0); +} /* dtt_init() */ + +int +dtt_get_temp (int sensor) +{ + signed char val; + + if ((sensor & 1) == 0) + val = dtt_read(sensor, DTT_READ_LOC_VALUE); + else + val = dtt_read(sensor, DTT_READ_REM_VALUE); + + return (int) val; +} /* dtt_get_temp() */ + +#endif /* CONFIG_DTT_ADM1021 */ diff --git a/dtt/ds1621.c b/dtt/ds1621.c new file mode 100644 index 0000000..4948181 --- /dev/null +++ b/dtt/ds1621.c @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Dallas Semiconductor's DS1621 Digital Thermometer and Thermostat. + */ + +#include + +#ifdef CONFIG_DTT_DS1621 +#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ + (CFG_EEPROM_PAGE_WRITE_BITS < 1) +# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_DS1621" +#endif +#include +#include + +/* + * Device code + */ +#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */ + +int dtt_read(int sensor, int reg) +{ + int dlen; + uchar data[2]; + + /* + * Calculate sensor address and command. + * + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/ + + /* + * Prepare to handle 2 byte result. + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) + dlen = 2; + else + dlen = 1; + + /* + * Now try to read the register. + */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return 1; + + /* + * Handle 2 byte result. + */ + if (dlen == 2) + return ((int)((short)data[1] + (((short)data[0]) << 8))); + + return (int)data[0]; +} /* dtt_read() */ + + +int dtt_write(int sensor, int reg, int val) +{ + int dlen; + uchar data[2]; + + /* + * Calculate sensor address and register. + * + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); + + /* + * Handle various data sizes. + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) { + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + } + else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) { + dlen = 0; + data[0] = (char)0; + data[1] = (char)0; + } + else { + dlen = 1; + data[0] = (char)(val & 0xff); + } + + /* + * Write value to device. + */ + if (i2c_write(sensor, reg, 1, data, dlen) != 0) + return 1; + + return 0; +} /* dtt_write() */ + + +static int _dtt_init(int sensor) +{ + int val; + + /* + * Setup High Temp. + */ + val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0) + return 1; + udelay(50000); /* Max 50ms */ + + /* + * Setup Low Temp - hysteresis. + */ + val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0) + return 1; + udelay(50000); /* Max 50ms */ + + /* + * Setup configuraton register + * + * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES + * + * We run in polled mode, since there isn't any way to know if this + * lousy device is ready to provide temperature readings on power up. + */ + val = 0x9; + if (dtt_write(sensor, DTT_CONFIG, val) != 0) + return 1; + udelay(50000); /* Max 50ms */ + + return 0; +} /* _dtt_init() */ + + +int dtt_init (void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("DTT%d: FAILED\n", i+1); + else + printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i])); + } + + return (0); +} /* dtt_init() */ + + +int dtt_get_temp(int sensor) +{ + int i; + + /* + * Start a conversion, may take up to 1 second. + */ + dtt_write(sensor, DTT_WRITE_START_CONV, 0); + for (i = 0; i <= 10; i++) { + udelay(100000); + if (dtt_read(sensor, DTT_CONFIG) & 0x80) + break; + } + + return (dtt_read(sensor, DTT_READ_TEMP) / 256); +} /* dtt_get_temp() */ + + +#endif /* CONFIG_DTT_DS1621 */ diff --git a/dtt/lm75.c b/dtt/lm75.c new file mode 100644 index 0000000..59daa45 --- /dev/null +++ b/dtt/lm75.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * On Semiconductor's LM75 Temperature Sensor + */ + +#include + +#ifdef CONFIG_DTT_LM75 +#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ + (CFG_EEPROM_PAGE_WRITE_BITS < 1) +# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM75" +#endif + +#include +#include + + +/* + * Device code + */ +#define DTT_I2C_DEV_CODE 0x48 /* ON Semi's LM75 device */ + +int dtt_read(int sensor, int reg) +{ + int dlen; + uchar data[2]; + + /* + * Validate 'reg' param + */ + if((reg < 0) || (reg > 3)) + return -1; + + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate address of lm75 */ + + /* + * Prepare to handle 2 byte result. + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HYST) || + (reg == DTT_TEMP_SET)) + dlen = 2; + else + dlen = 1; + + /* + * Now try to read the register. + */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return -1; + + /* + * Handle 2 byte result. + */ + if (dlen == 2) + return ((int)((short)data[1] + (((short)data[0]) << 8))); + + + return (int)data[0]; +} /* dtt_read() */ + + +int dtt_write(int sensor, int reg, int val) +{ + int dlen; + uchar data[2]; + + /* + * Validate 'reg' param + */ + if ((reg < 0) || (reg > 3)) + return 1; + + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate address of lm75 */ + + /* + * Handle 2 byte values. + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HYST) || + (reg == DTT_TEMP_SET)) { + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + } else { + dlen = 1; + data[0] = (char)(val & 0xff); + } + + /* + * Write value to register. + */ + if (i2c_write(sensor, reg, 1, data, dlen) != 0) + return 1; + + return 0; +} /* dtt_write() */ + + +static int _dtt_init(int sensor) +{ + int val; + + /* + * Setup TSET ( trip point ) register + */ + val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; /* trip */ + if (dtt_write(sensor, DTT_TEMP_SET, val) != 0) + return 1; + + /* + * Setup THYST ( untrip point ) register - Hysteresis + */ + val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) + return 1; + + /* + * Setup configuraton register + */ + /* config = 6 sample integration, int mode, active low, and enable */ + val = 0x18; + if (dtt_write(sensor, DTT_CONFIG, val) != 0) + return 1; + + return 0; +} /* _dtt_init() */ + + +int dtt_init (void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + const char *const header = "DTT: "; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("%s%d FAILED INIT\n", header, i+1); + else + printf("%s%d is %i C\n", header, i+1, + dtt_get_temp(sensors[i])); + } + + return (0); +} /* dtt_init() */ + +int dtt_get_temp(int sensor) +{ + return (dtt_read(sensor, DTT_READ_TEMP) / 256); +} /* dtt_get_temp() */ + +#endif /* CONFIG_DTT_LM75 */ diff --git a/examples/82559_eeprom.c b/examples/82559_eeprom.c new file mode 100644 index 0000000..1a121d4 --- /dev/null +++ b/examples/82559_eeprom.c @@ -0,0 +1,354 @@ + +/* + * Copyright 1998-2001 by Donald Becker. + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + * Contact the author for use under other terms. + * + * This program must be compiled with "-O"! + * See the bottom of this file for the suggested compile-command. + * + * The author may be reached as becker@scyld.com, or C/O + * Scyld Computing Corporation + * 410 Severn Ave., Suite 210 + * Annapolis MD 21403 + * + * Common-sense licensing statement: Using any portion of this program in + * your own program means that you must give credit to the original author + * and release the resulting code under the GPL. + */ + +#define _PPC_STRING_H_ /* avoid unnecessary str/mem functions */ +#define _LINUX_STRING_H_ /* avoid unnecessary str/mem functions */ + +#include +#include +#include + + +/* Default EEPROM for i82559 */ +static unsigned short default_eeprom[64] = { + 0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff +}; + +static unsigned short eeprom[256]; + +static int eeprom_size = 64; +static int eeprom_addr_size = 6; + +static int debug = 0; + +static inline unsigned short swap16(unsigned short x) +{ + return (((x & 0xff) << 8) | ((x & 0xff00) >> 8)); +} + + +static inline void *memcpy(void *dst, const void *src, unsigned int len) +{ + void * ret = dst; + while (len-- > 0) *((char *)dst)++ = *((char *)src)++; + return ret; +} + +/* The EEPROM commands include the alway-set leading bit. */ +#define EE_WRITE_CMD (5) +#define EE_READ_CMD (6) +#define EE_ERASE_CMD (7) + +/* Serial EEPROM section. */ +#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ +#define EE_CS 0x02 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_ENB (0x4800 | EE_CS) +#define EE_WRITE_0 0x4802 +#define EE_WRITE_1 0x4806 +#define EE_OFFSET 14 + +/* Delay between EEPROM clock transitions. */ +#define eeprom_delay(ee_addr) inw(ee_addr) + +/* Wait for the EEPROM to finish the previous operation. */ +static int eeprom_busy_poll(long ee_ioaddr) +{ + int i; + outw(EE_ENB, ee_ioaddr); + for (i = 0; i < 10000; i++) /* Typical 2000 ticks */ + if (inw(ee_ioaddr) & EE_DATA_READ) + break; + return i; +} + +/* This executes a generic EEPROM command, typically a write or write enable. + It returns the data output from the EEPROM, and thus may also be used for + reads. */ +static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len) +{ + unsigned retval = 0; + long ee_addr = ioaddr + EE_OFFSET; + + if (debug > 1) + printf(" EEPROM op 0x%x: ", cmd); + + outw(EE_ENB | EE_SHIFT_CLK, ee_addr); + + /* Shift the command bits out. */ + do { + short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; + outw(dataval, ee_addr); + eeprom_delay(ee_addr); + if (debug > 2) + printf("%X", inw(ee_addr) & 15); + outw(dataval | EE_SHIFT_CLK, ee_addr); + eeprom_delay(ee_addr); + retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0); + } while (--cmd_len >= 0); +#if 0 + outw(EE_ENB, ee_addr); +#endif + /* Terminate the EEPROM access. */ + outw(EE_ENB & ~EE_CS, ee_addr); + if (debug > 1) + printf(" EEPROM result is 0x%5.5x.\n", retval); + return retval; +} + +static int read_eeprom(long ioaddr, int location, int addr_len) +{ + return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location) + << 16 , 3 + addr_len + 16) & 0xffff; +} + +static void write_eeprom(long ioaddr, int index, int value, int addr_len) +{ + long ee_ioaddr = ioaddr + EE_OFFSET; + int i; + + /* Poll for previous op finished. */ + eeprom_busy_poll(ee_ioaddr); /* Typical 0 ticks */ + /* Enable programming modes. */ + do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len); + /* Do the actual write. */ + do_eeprom_cmd(ioaddr, + (((EE_WRITE_CMD</dev/null + +%.bin: % + $(OBJCOPY) -O binary $< $@ 2>/dev/null + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) > $@ + +sinclude .depend + +######################################################################### diff --git a/examples/README.smc91111_eeprom b/examples/README.smc91111_eeprom new file mode 100644 index 0000000..28e7e69 --- /dev/null +++ b/examples/README.smc91111_eeprom @@ -0,0 +1,246 @@ +This is the readme for the Das U-Boot standalone program smc91111 + +The main purpose of this is to manage MAC addresses on platforms +which include the SMC91111 integrated 10/100 MAC Phy, with attached +EEPROMs. + + +Contents: +------------------------ +1. Ensuring U-boot's MAC address can be set in hardware +2. Running the smc91111_eeprom program +3. Setting MAC addresses +4. Other things you can do with this +5. Things to be done. + + +1. Ensuring U-boot's MAC address can be set in hardware +-------------------------------------------------------------------------- + +On the Internet - MAC addresses are very important. Short for Media +Access Control address, a hardware address that uniquely identifies +each node of a network. When things are not unique - bad things +can happen. This is why U-Boot makes it difficult to change MAC +addresses. + +To find out who has a MAC address, or to purchase MAC addresses, goto +the IEEE, at: +http://standards.ieee.org/regauth/oui/index.shtml + +To change your MAC address, there can not be a MAC address predefined in +U-Boot. To ensure that this does not occur, check your +include/configs/.h file, and check to see that the following +settings are _not_ or commented out there. + +#define HARDCODE_MAC 1 +#define CONFIG_ETHADDR 02:80:ad:20:31:b8 + +The purpose of HARDCODE_MAC is to hardcode the MAC address in software, +(not what we want), or to preset it to 02:80:ad:20:31:b8 (not what we +want either). + +You can check this in a running U-Boot, by doing a power cycle, then +before U-Boot tries to do any networking, running the 'printenv' command + + BOOT> printenv + + ethaddr=02:80:ad:20:31:b8 + +If you see the 'ethaddr' variable show up, like the above, you need to +recompile U-Boot, with the above settings commented out of the +include/configs/.h file. + +2. Running the smc91111_eeprom program +--------------------------------------------------------------------- + +After Uboot is compiled, there should be three files of interest: +-rwxr-xr-x 1 8806 2004-10-11 14:00 smc91111_eeprom <- ELF +-rwxr-xr-x 1 3440 2004-10-11 14:00 smc91111_eeprom.bin <- BIN +-rwxr-xr-x 1 9524 2004-10-11 14:00 smc91111_eeprom.srec <- SREC + +if there is not, check the examples/Makefile, and ensure there is something +like for your architecture: + + ifeq ($(ARCH),blackfin) + SREC += smc91111_eeprom.srec + BIN += smc91111_eeprom.bin smc91111_eeprom + endif + +To load the files: there are two methods: a) serial or b) network. Since +it is not a good idea to start doing things on the network before the +MAC address is set, this example will do things over serial. + +a) Loading the elf file via the serial port +-------------------------------------------- +Loading the elf is very easy - just ensure that the location +you specify things to load as is not the load address specified +in the Makefile. + +BOOT> loadb 0x1000000 + +## Ready for binary (kermit) download to 0x01000000 at 57600 bps... + +(type CNTL-\ then C) +(Back at local machine) +---------------------------------------------------- +Kermit>send ~/u-boot_1.1.1/examples/smc91111_eeprom +Kermit>connect + +Connecting to /dev/ttyS0, speed 57600 + Escape character: Ctrl-\ (ASCII 28, FS): enabled +Type the escape character followed by C to get back, +or followed by ? to see other options. +---------------------------------------------------- +## Total Size = 0x00002266 = 8806 Bytes +## Start Addr = 0x01000000 + +BOOT> bootelf 0x1000000 + +Loading .text @ 0x00001000 (3440 bytes) +## Starting application at 0x000010d8 ... + +SMC91111> + +b) Loading the binary file via the serial port +----------------------------------------------- +For many toolchains, the entry point is not the load point. +The Load point is a hard coded address from the +examples/Makefile. The entry point can be found by doing something +like: + + u-boot_1.1.1/examples> bfin-elf-objdump -d smc91111_eeprom |less + + smc91111_eeprom: file format elf32-bfin + + Disassembly of section .text: + + 00001000 : + 1000: + 000010d8 : + +You can see that the entry point (or the address that should be +jumped to is 0x10d8). This is also the same as the entry point +of the elf file. + +Now we load it to the actual load location: + +BOOT> loadb 0x1000 + +## Ready for binary (kermit) download to 0x00001000 at 57600 bps... + +(Back at pinky.dsl-only.net) +---------------------------------------------------- +Kermit>send /tftpboot/eeprom.bin +Kermit>connect + +Connecting to /dev/ttyS0, speed 57600 + Escape character: Ctrl-\ (ASCII 28, FS): enabled +Type the escape character followed by C to get back, +or followed by ? to see other options. +---------------------------------------------------- +## Total Size = 0x00000d70 = 3440 Bytes +## Start Addr = 0x00001000 + +BOOT> go 0x10D8 + +## Starting application at 0x000010D8 ... + +SMC91111> + +3. Setting MAC addresses +-------------------------------------------------------------------------- + +The MAC address can be stored in four locations: + +-Boot environmental variable in Flash <- can not change, without + re-flashing U-boot. +U-Boot environental variable <- can not change, without + resetting board/U-Boot +LAN91C111 Registers <- volitle +LAN91C111 EEPROM <- Non Volitle + +If you have not activated the network, and do not have a hardcoded +or pre-assigned MAC address in U-boot, the environmental variables +should be blank, and allow you to set things one time. + +To set the EEPROM MAC address to 12:34:56:78:9A:BC + +SMC91111> W E 20 3412 + +Writing EEPROM register 20 with 3412 +SMC91111> W E 21 7856 + +Writing EEPROM register 21 with 7856 +SMC91111> W E 22 BC9A + +Writing EEPROM register 22 with bc9a +EEPROM contents copied to MAC +SMC91111> P + +Current MAC Address in SMSC91111 12:34:56:78:9a:bc +Current MAC Address in EEPROM 12:34:56:78:9a:bc + +(CNTRL-C to exit) +SMC91111> ## Application terminated, rc = 0x0 + +BOOT> reset +U-Boot 1.1.1 (gcc version: 3.3.3) +Release Version Beta released on Oct 10 2004 - 00:34:35 +Blackfin support by LG Soft India +For further information please check this link http://www.blackfin.uclinux.org +BOOT> ping 192.168.0.4 + +Using MAC Address 12:34:56:78:9A:BC +host 192.168.0.4 is alive + + +4. Other things that you can do +-------------------------------------------------------------------------- +After the stand alone application is running, there are a few options: + - P : Print the MAC + - D : Dump the LAN91C111 EEPROM contents + - M : Dump the LAN91C111 MAC contents + - C : Copies the MAC address from the EEPROM to the LAN91C111 + - W : Write a register in the EEPROM or in the MAC + +SMC91111> P + +Current MAC Address in SMSC91111 12:34:56:78:9a:bc +Current MAC Address in EEPROM 12:34:56:78:9a:bc + +SMC91111> D + +IOS2-0 000 001 002 003 004 005 006 007 +CONFIG 00:ffff 04:ffff 08:ffff 0c:ffff 10:ffff 14:ffff 18:ffff 1c:ffff +BASE 01:ffff 05:ffff 09:ffff 0d:ffff 11:ffff 15:ffff 19:ffff 1d:ffff + 02:ffff 06:ffff 0a:ffff 0e:0020 12:ffff 16:ffff 1a:ffff 1e:ffff + 03:ffff 07:ffff 0b:ffff 0f:ffff 13:ffff 17:ffff 1b:ffff 1f:ffff + +20:3412 21:7856 22:bc9a 23:ffff 24:ffff 25:ffff 26:ffff 27:ffff +28:ffff 29:ffff 2a:ffff 2b:ffff 2c:ffff 2d:ffff 2e:ffff 2f:ffff +30:ffff 31:ffff 32:ffff 33:ffff 34:ffff 35:ffff 36:ffff 37:ffff +38:ffff 39:ffff 3a:ffff 3b:ffff 3c:ffff 3d:ffff 3e:ffff 3f:ffff + +SMC91111> M + + Bank0 Bank1 Bank2 Bank3 +00 0000 a0b1 3332 0000 +02 0000 1801 8000 0000 +04 0000 3412 8080 0000 +06 0000 7856 003f 0000 +08 0404 bc9a 02df 3332 +0a 0000 ffff 02df 3391 +0c 0000 1214 0004 001f +0e 3300 3301 3302 3303 + +SMC91111> C + +EEPROM contents copied to MAC + +SMC91111> W E 2A ABCD + +Writing EEPROM register 2a with abcd + +SMC91111> W M 14 FF00 + +Writing MAC register bank 1, reg 04 with ff00 diff --git a/examples/eepro100_eeprom.c b/examples/eepro100_eeprom.c new file mode 100644 index 0000000..a52e68d --- /dev/null +++ b/examples/eepro100_eeprom.c @@ -0,0 +1,214 @@ +/* + * Copyright 1998-2001 by Donald Becker. + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + * Contact the author for use under other terms. + * + * This program must be compiled with "-O"! + * See the bottom of this file for the suggested compile-command. + * + * The author may be reached as becker@scyld.com, or C/O + * Scyld Computing Corporation + * 410 Severn Ave., Suite 210 + * Annapolis MD 21403 + * + * Common-sense licensing statement: Using any portion of this program in + * your own program means that you must give credit to the original author + * and release the resulting code under the GPL. + */ + +#define _PPC_STRING_H_ /* avoid unnecessary str/mem functions */ +#define _LINUX_STRING_H_ /* avoid unnecessary str/mem functions */ + +#include +#include + +static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr); + +int eepro100_eeprom(int argc, char *argv[]) +{ + int ret = 0; + + unsigned char hwaddr1[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x05 }; + unsigned char hwaddr2[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x06 }; + + app_startup(argv); + +#if defined(CONFIG_OXC) + ret |= reset_eeprom(0x80000000, hwaddr1); + ret |= reset_eeprom(0x81000000, hwaddr2); +#endif + + return ret; +} + +/* Default EEPROM for i82559 */ +static unsigned short default_eeprom[64] = { + 0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff +}; + +static unsigned short eeprom[256]; + +static int eeprom_size = 64; +static int eeprom_addr_size = 6; + +static int debug = 0; + +static inline unsigned short swap16(unsigned short x) +{ + return (((x & 0xff) << 8) | ((x & 0xff00) >> 8)); +} + +static inline void outw(short data, long addr) +{ + *(volatile short *)(addr) = swap16(data); +} + +static inline short inw(long addr) +{ + return swap16(*(volatile short *)(addr)); +} + +static inline void *memcpy(void *dst, const void *src, unsigned int len) +{ + char *ret = dst; + while (len-- > 0) { + *ret++ = *((char *)src); + src++; + } + return (void *)ret; +} + +/* The EEPROM commands include the alway-set leading bit. */ +#define EE_WRITE_CMD (5) +#define EE_READ_CMD (6) +#define EE_ERASE_CMD (7) + +/* Serial EEPROM section. */ +#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ +#define EE_CS 0x02 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_ENB (0x4800 | EE_CS) +#define EE_WRITE_0 0x4802 +#define EE_WRITE_1 0x4806 +#define EE_OFFSET 14 + +/* Delay between EEPROM clock transitions. */ +#define eeprom_delay(ee_addr) inw(ee_addr) + +/* Wait for the EEPROM to finish the previous operation. */ +static int eeprom_busy_poll(long ee_ioaddr) +{ + int i; + outw(EE_ENB, ee_ioaddr); + for (i = 0; i < 10000; i++) /* Typical 2000 ticks */ + if (inw(ee_ioaddr) & EE_DATA_READ) + break; + return i; +} + +/* This executes a generic EEPROM command, typically a write or write enable. + It returns the data output from the EEPROM, and thus may also be used for + reads. */ +static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len) +{ + unsigned retval = 0; + long ee_addr = ioaddr + EE_OFFSET; + + if (debug > 1) + printf(" EEPROM op 0x%x: ", cmd); + + outw(EE_ENB | EE_SHIFT_CLK, ee_addr); + + /* Shift the command bits out. */ + do { + short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; + outw(dataval, ee_addr); + eeprom_delay(ee_addr); + if (debug > 2) + printf("%X", inw(ee_addr) & 15); + outw(dataval | EE_SHIFT_CLK, ee_addr); + eeprom_delay(ee_addr); + retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0); + } while (--cmd_len >= 0); +#if 0 + outw(EE_ENB, ee_addr); +#endif + /* Terminate the EEPROM access. */ + outw(EE_ENB & ~EE_CS, ee_addr); + if (debug > 1) + printf(" EEPROM result is 0x%5.5x.\n", retval); + return retval; +} + +static int read_eeprom(long ioaddr, int location, int addr_len) +{ + return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location) + << 16 , 3 + addr_len + 16) & 0xffff; +} + +static void write_eeprom(long ioaddr, int index, int value, int addr_len) +{ + long ee_ioaddr = ioaddr + EE_OFFSET; + int i; + + /* Poll for previous op finished. */ + eeprom_busy_poll(ee_ioaddr); /* Typical 0 ticks */ + /* Enable programming modes. */ + do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len); + /* Do the actual write. */ + do_eeprom_cmd(ioaddr, + (((EE_WRITE_CMD< +#include + +int hello_world (int argc, char *argv[]) +{ + int i; + + /* Print the ABI version */ + app_startup(argv); + printf ("Example expects ABI version %d\n", XF_VERSION); + printf ("Actual U-Boot ABI version %d\n", (int)get_version()); + + printf ("Hello World\n"); + + printf ("argc = %d\n", argc); + + for (i=0; i<=argc; ++i) { + printf ("argv[%d] = \"%s\"\n", + i, + argv[i] ? argv[i] : ""); + } + + printf ("Hit any key to exit ... "); + while (!tstc()) + ; + /* consume input */ + (void) getc(); + + printf ("\n\n"); + return (0); +} diff --git a/examples/mem_to_mem_idma2intr.c b/examples/mem_to_mem_idma2intr.c new file mode 100644 index 0000000..3a269c9 --- /dev/null +++ b/examples/mem_to_mem_idma2intr.c @@ -0,0 +1,384 @@ +/* The dpalloc function used and implemented in this file was derieved + * from PPCBoot/U-Boot file "cpu/mpc8260/commproc.c". + */ + +/* Author: Arun Dharankar + * This example is meant to only demonstrate how the IDMA could be used. + */ + +/* + * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's + * copyright notice: + * + * General Purpose functions for the global management of the + * 8260 Communication Processor Module. + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) + * 2.3.99 Updates + * + * In addition to the individual control of the communication + * channels, there are a few functions that globally affect the + * communication processor. + * + * Buffer descriptors must be allocated from the dual ported memory + * space. The allocator for that is here. When the communication + * process is reset, we reclaim the memory available. There is + * currently no deallocator for this memory. + */ + + +#include +#include + +#define STANDALONE + +#ifndef STANDALONE /* Linked into/Part of PPCBoot */ +#include +#include +#else /* Standalone app of PPCBoot */ +#define WATCHDOG_RESET() { \ + *(ushort *)(CFG_IMMR + 0x1000E) = 0x556c; \ + *(ushort *)(CFG_IMMR + 0x1000E) = 0xaa39; \ + } +#endif /* STANDALONE */ + +static int debug = 1; + +#define DEBUG(fmt, args...) { \ + if(debug != 0) { \ + printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__); \ + printf(fmt, ##args); \ + } \ +} + +#define CPM_CR_IDMA1_SBLOCK (0x14) +#define CPM_CR_IDMA2_SBLOCK (0x15) +#define CPM_CR_IDMA3_SBLOCK (0x16) +#define CPM_CR_IDMA4_SBLOCK (0x17) +#define CPM_CR_IDMA1_PAGE (0x07) +#define CPM_CR_IDMA2_PAGE (0x08) +#define CPM_CR_IDMA3_PAGE (0x09) +#define CPM_CR_IDMA4_PAGE (0x0a) +#define PROFF_IDMA1_BASE ((uint)0x87fe) +#define PROFF_IDMA2_BASE ((uint)0x88fe) +#define PROFF_IDMA3_BASE ((uint)0x89fe) +#define PROFF_IDMA4_BASE ((uint)0x8afe) + +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_FLG ((ushort)0x0001) + +#define mk_cr_cmd(PG, SBC, MCN, OP) \ + ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) + + +#pragma pack(1) +typedef struct ibdbits { + unsigned b_valid:1; + unsigned b_resv1:1; + unsigned b_wrap:1; + unsigned b_interrupt:1; + unsigned b_last:1; + unsigned b_resv2:1; + unsigned b_cm:1; + unsigned b_resv3:2; + unsigned b_sdn:1; + unsigned b_ddn:1; + unsigned b_dgbl:1; + unsigned b_dbo:2; + unsigned b_resv4:1; + unsigned b_ddtb:1; + unsigned b_resv5:2; + unsigned b_sgbl:1; + unsigned b_sbo:2; + unsigned b_resv6:1; + unsigned b_sdtb:1; + unsigned b_resv7:9; +} ibdbits_t; + +#pragma pack(1) +typedef union ibdbitsu { + ibdbits_t b; + uint i; +} ibdbitsu_t; + +#pragma pack(1) +typedef struct idma_buf_desc { + ibdbitsu_t ibd_bits; /* Status and Control */ + uint ibd_datlen; /* Data length in buffer */ + uint ibd_sbuf; /* Source buffer addr in host mem */ + uint ibd_dbuf; /* Destination buffer addr in host mem */ +} ibd_t; + + +#pragma pack(1) +typedef struct dcmbits { + unsigned b_fb:1; + unsigned b_lp:1; + unsigned b_resv1:3; + unsigned b_tc2:1; + unsigned b_resv2:1; + unsigned b_wrap:3; + unsigned b_sinc:1; + unsigned b_dinc:1; + unsigned b_erm:1; + unsigned b_dt:1; + unsigned b_sd:2; +} dcmbits_t; + +#pragma pack(1) +typedef union dcmbitsu { + dcmbits_t b; + ushort i; +} dcmbitsu_t; + +#pragma pack(1) +typedef struct pram_idma { + ushort pi_ibase; + dcmbitsu_t pi_dcmbits; + ushort pi_ibdptr; + ushort pi_dprbuf; + ushort pi_bufinv; /* internal to CPM */ + ushort pi_ssmax; + ushort pi_dprinptr; /* internal to CPM */ + ushort pi_sts; + ushort pi_dproutptr; /* internal to CPM */ + ushort pi_seob; + ushort pi_deob; + ushort pi_dts; + ushort pi_retadd; + ushort pi_resv1; /* internal to CPM */ + uint pi_bdcnt; + uint pi_sptr; + uint pi_dptr; + uint pi_istate; +} pram_idma_t; + + +volatile immap_t *immap = (immap_t *) CFG_IMMR; +volatile ibd_t *bdf; +volatile pram_idma_t *piptr; + +volatile int dmadone; +volatile int *dmadonep = &dmadone; +void dmadone_handler (void *); + +int idma_init (void); +void idma_start (int, int, int, uint, uint, int); +uint dpalloc (uint, uint); + + +uint dpinit_done = 0; + + +#ifdef STANDALONE +int ctrlc (void) +{ + if (tstc()) { + switch (getc ()) { + case 0x03: /* ^C - Control C */ + return 1; + default: + break; + } + } + return 0; +} +void * memset(void * s,int c,size_t count) +{ + char *xs = (char *) s; + while (count--) + *xs++ = c; + return s; +} +int memcmp(const void * cs,const void * ct,size_t count) +{ + const unsigned char *su1, *su2; + int res = 0; + for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) + if ((res = *su1 - *su2) != 0) + break; + return res; +} +#endif /* STANDALONE */ + +#ifdef STANDALONE +int mem_to_mem_idma2intr (int argc, char *argv[]) +#else +int do_idma (bd_t * bd, int argc, char *argv[]) +#endif /* STANDALONE */ +{ + int i; + + app_startup(argv); + dpinit_done = 0; + + idma_init (); + + DEBUG ("Installing dma handler\n"); + install_hdlr (7, dmadone_handler, (void *) bdf); + + memset ((void *) 0x100000, 'a', 512); + memset ((void *) 0x200000, 'b', 512); + + for (i = 0; i < 32; i++) { + printf ("Startin IDMA, iteration=%d\n", i); + idma_start (1, 1, 512, 0x100000, 0x200000, 3); + } + + DEBUG ("Uninstalling dma handler\n"); + free_hdlr (7); + + return 0; +} + +void +idma_start (int sinc, int dinc, int sz, uint sbuf, uint dbuf, int ttype) +{ + /* ttype is for M-M, M-P, P-M or P-P: not used for now */ + + piptr->pi_istate = 0; /* manual says: clear it before every START_IDMA */ + piptr->pi_dcmbits.b.b_resv1 = 0; + + if (sinc == 1) + piptr->pi_dcmbits.b.b_sinc = 1; + else + piptr->pi_dcmbits.b.b_sinc = 0; + + if (dinc == 1) + piptr->pi_dcmbits.b.b_dinc = 1; + else + piptr->pi_dcmbits.b.b_dinc = 0; + + piptr->pi_dcmbits.b.b_erm = 0; + piptr->pi_dcmbits.b.b_sd = 0x00; /* M-M */ + + bdf->ibd_sbuf = sbuf; + bdf->ibd_dbuf = dbuf; + bdf->ibd_bits.b.b_cm = 0; + bdf->ibd_bits.b.b_interrupt = 1; + bdf->ibd_bits.b.b_wrap = 1; + bdf->ibd_bits.b.b_last = 1; + bdf->ibd_bits.b.b_sdn = 0; + bdf->ibd_bits.b.b_ddn = 0; + bdf->ibd_bits.b.b_dgbl = 0; + bdf->ibd_bits.b.b_ddtb = 0; + bdf->ibd_bits.b.b_sgbl = 0; + bdf->ibd_bits.b.b_sdtb = 0; + bdf->ibd_bits.b.b_dbo = 1; + bdf->ibd_bits.b.b_sbo = 1; + bdf->ibd_bits.b.b_valid = 1; + bdf->ibd_datlen = 512; + + *dmadonep = 0; + + immap->im_sdma.sdma_idmr2 = (uchar) 0xf; + + immap->im_cpm.cp_cpcr = mk_cr_cmd (CPM_CR_IDMA2_PAGE, + CPM_CR_IDMA2_SBLOCK, 0x0, + 0x9) | 0x00010000; + + while (*dmadonep != 1) { + if (ctrlc ()) { + DEBUG ("\nInterrupted waiting for DMA interrupt.\n"); + goto done; + } + printf ("Waiting for DMA interrupt (dmadone=%d b_valid = %d)...\n", + dmadone, bdf->ibd_bits.b.b_valid); + udelay (1000000); + } + printf ("DMA complete notification received!\n"); + + done: + DEBUG ("memcmp(0x%08x, 0x%08x, 512) = %d\n", + sbuf, dbuf, memcmp ((void *) sbuf, (void *) dbuf, 512)); + + return; +} + +#define MAX_INT_BUFSZ 64 +#define DCM_WRAP 0 /* MUST be consistant with MAX_INT_BUFSZ */ + +int idma_init (void) +{ + uint memaddr; + + immap->im_cpm.cp_rccr &= ~0x00F3FFFF; + immap->im_cpm.cp_rccr |= 0x00A00A00; + + memaddr = dpalloc (sizeof (pram_idma_t), 64); + + *(volatile ushort *) &immap->im_dprambase[PROFF_IDMA2_BASE] = memaddr; + piptr = (volatile pram_idma_t *) ((uint) (immap) + memaddr); + + piptr->pi_resv1 = 0; /* manual says: clear it */ + piptr->pi_dcmbits.b.b_fb = 0; + piptr->pi_dcmbits.b.b_lp = 1; + piptr->pi_dcmbits.b.b_erm = 0; + piptr->pi_dcmbits.b.b_dt = 0; + + memaddr = (uint) dpalloc (sizeof (ibd_t), 64); + piptr->pi_ibase = piptr->pi_ibdptr = (volatile short) memaddr; + bdf = (volatile ibd_t *) ((uint) (immap) + memaddr); + bdf->ibd_bits.b.b_valid = 0; + + memaddr = (uint) dpalloc (64, 64); + piptr->pi_dprbuf = (volatile ushort) memaddr; + piptr->pi_dcmbits.b.b_wrap = 4; + piptr->pi_ssmax = 32; + + piptr->pi_sts = piptr->pi_ssmax; + piptr->pi_dts = piptr->pi_ssmax; + + return 1; +} + +void dmadone_handler (void *arg) +{ + immap->im_sdma.sdma_idmr2 = (uchar) 0x0; + + *dmadonep = 1; + + return; +} + + +static uint dpbase = 0; + +uint dpalloc (uint size, uint align) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + uint retloc; + uint align_mask, off; + uint savebase; + + /* Pointer to initial global data area */ + + if (dpinit_done == 0) { + dpbase = gd->dp_alloc_base; + dpinit_done = 1; + } + + align_mask = align - 1; + savebase = dpbase; + + if ((off = (dpbase & align_mask)) != 0) + dpbase += (align - off); + + if ((off = size & align_mask) != 0) + size += align - off; + + if ((dpbase + size) >= gd->dp_alloc_top) { + dpbase = savebase; + printf ("dpalloc: ran out of dual port ram!"); + return 0; + } + + retloc = dpbase; + dpbase += size; + + memset ((void *) &immr->im_dprambase[retloc], 0, size); + + return (retloc); +} diff --git a/examples/mips.lds b/examples/mips.lds new file mode 100644 index 0000000..9d9849b --- /dev/null +++ b/examples/mips.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +SECTIONS +{ + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + . = ALIGN(4); + __bss_start = .; + .sbss : { *(.sbss) } + .bss : { *(.bss) } + + _end = .; +} diff --git a/examples/nios.lds b/examples/nios.lds new file mode 100644 index 0000000..dd5bfad --- /dev/null +++ b/examples/nios.lds @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-nios") +OUTPUT_ARCH(nios) +ENTRY(_start) + +SECTIONS +{ + .text : + { + *(.text) + } + __text_end = .; + + . = ALIGN(4); + .rodata : + { + *(.rodata) + } + __rodata_end = .; + + . = ALIGN(4); + .data : + { + *(.data) + } + . = ALIGN(4); + __data_end = .; + + __bss_start = .; + . = ALIGN(4); + .bss : + { + *(.bss) + } + . = ALIGN(4); + __bss_end = .; + _end = .; +} diff --git a/examples/nios2.lds b/examples/nios2.lds new file mode 100644 index 0000000..277a0a7 --- /dev/null +++ b/examples/nios2.lds @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-littlenios2") +OUTPUT_ARCH(nios2) +ENTRY(_start) + +SECTIONS +{ + .text : + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + } + . = ALIGN (4); + _etext = .; + PROVIDE (etext = .); + + /* INIT DATA sections - "Small" data (see the gcc -G option) + * is always gp-relative. Here we make all init data sections + * adjacent to simplify the startup code -- and provide + * the global pointer for gp-relative access. + */ + _data = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + } + + . = ALIGN(16); + _gp = .; /* Global pointer addr */ + PROVIDE (gp = .); + + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* UNINIT DATA - Small uninitialized data is first so it's + * adjacent to sdata and can be referenced via gp. The normal + * bss follows. We keep it adjacent to simplify init code. + */ + __bss_start = .; + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + . = ALIGN(4); + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + *(.scommon) + } + . = ALIGN(4); + _end = .; + PROVIDE (end = .); + + /* CMD TABLE - uboot command sections + */ + . = .; + __uboot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + /* DEBUG -- symbol table, string table, etc. etc. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/examples/ppc_longjmp.S b/examples/ppc_longjmp.S new file mode 100644 index 0000000..5ca6f6f --- /dev/null +++ b/examples/ppc_longjmp.S @@ -0,0 +1,79 @@ +/* longjmp for PowerPC. + Copyright (C) 1995, 1996, 1997, 1999, 2000 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +#include + +# define JB_GPR1 0 /* Also known as the stack pointer */ +# define JB_GPR2 1 +# define JB_LR 2 /* The address we will return to */ +# define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18 in total */ +# define JB_CR 21 /* Condition code registers. */ +# define JB_FPRS 22 /* FPRs 14 through 31 are saved, 18*2 words total */ +# define JB_SIZE (58*4) + +#define FP(x...) x +#define FP(x...) x + +.globl ppc_longjmp; + +ppc_longjmp: + lwz r1,(JB_GPR1*4)(r3) + lwz r2,(JB_GPR2*4)(r3) + lwz r0,(JB_LR*4)(r3) + lwz r14,((JB_GPRS+0)*4)(r3) +FP( lfd 14,((JB_FPRS+0*2)*4)(r3)) + lwz r15,((JB_GPRS+1)*4)(r3) +FP( lfd 15,((JB_FPRS+1*2)*4)(r3)) + lwz r16,((JB_GPRS+2)*4)(r3) +FP( lfd 16,((JB_FPRS+2*2)*4)(r3)) + lwz r17,((JB_GPRS+3)*4)(r3) +FP( lfd 17,((JB_FPRS+3*2)*4)(r3)) + lwz r18,((JB_GPRS+4)*4)(r3) +FP( lfd 18,((JB_FPRS+4*2)*4)(r3)) + lwz r19,((JB_GPRS+5)*4)(r3) +FP( lfd 19,((JB_FPRS+5*2)*4)(r3)) + lwz r20,((JB_GPRS+6)*4)(r3) +FP( lfd 20,((JB_FPRS+6*2)*4)(r3)) + mtlr r0 + lwz r21,((JB_GPRS+7)*4)(r3) +FP( lfd 21,((JB_FPRS+7*2)*4)(r3)) + lwz r22,((JB_GPRS+8)*4)(r3) +FP( lfd 22,((JB_FPRS+8*2)*4)(r3)) + lwz r0,(JB_CR*4)(r3) + lwz r23,((JB_GPRS+9)*4)(r3) +FP( lfd 23,((JB_FPRS+9*2)*4)(r3)) + lwz r24,((JB_GPRS+10)*4)(r3) +FP( lfd 24,((JB_FPRS+10*2)*4)(r3)) + lwz r25,((JB_GPRS+11)*4)(r3) +FP( lfd 25,((JB_FPRS+11*2)*4)(r3)) + mtcrf 0xFF,r0 + lwz r26,((JB_GPRS+12)*4)(r3) +FP( lfd 26,((JB_FPRS+12*2)*4)(r3)) + lwz r27,((JB_GPRS+13)*4)(r3) +FP( lfd 27,((JB_FPRS+13*2)*4)(r3)) + lwz r28,((JB_GPRS+14)*4)(r3) +FP( lfd 28,((JB_FPRS+14*2)*4)(r3)) + lwz r29,((JB_GPRS+15)*4)(r3) +FP( lfd 29,((JB_FPRS+15*2)*4)(r3)) + lwz r30,((JB_GPRS+16)*4)(r3) +FP( lfd 30,((JB_FPRS+16*2)*4)(r3)) + lwz r31,((JB_GPRS+17)*4)(r3) +FP( lfd 31,((JB_FPRS+17*2)*4)(r3)) + mr r3,r4 + blr diff --git a/examples/ppc_setjmp.S b/examples/ppc_setjmp.S new file mode 100644 index 0000000..421abfd --- /dev/null +++ b/examples/ppc_setjmp.S @@ -0,0 +1,83 @@ +/* setjmp for PowerPC. + Copyright (C) 1995, 1996, 1997, 1999, 2000 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +#include + +# define JB_GPR1 0 /* Also known as the stack pointer */ +# define JB_GPR2 1 +# define JB_LR 2 /* The address we will return to */ +# define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18 in total */ +# define JB_CR 21 /* Condition code registers. */ +# define JB_FPRS 22 /* FPRs 14 through 31 are saved, 18*2 words total */ +# define JB_SIZE (58*4) + +#define FP(x...) x + +.globl setctxsp; +setctxsp: + mr r1, r3 + blr + +.globl ppc_setjmp; +ppc_setjmp: + stw r1,(JB_GPR1*4)(3) + mflr r0 + stw r2,(JB_GPR2*4)(3) + stw r14,((JB_GPRS+0)*4)(3) +FP( stfd 14,((JB_FPRS+0*2)*4)(3)) + stw r0,(JB_LR*4)(3) + stw r15,((JB_GPRS+1)*4)(3) +FP( stfd 15,((JB_FPRS+1*2)*4)(3)) + mfcr r0 + stw r16,((JB_GPRS+2)*4)(3) +FP( stfd 16,((JB_FPRS+2*2)*4)(3)) + stw r0,(JB_CR*4)(3) + stw r17,((JB_GPRS+3)*4)(3) +FP( stfd 17,((JB_FPRS+3*2)*4)(3)) + stw r18,((JB_GPRS+4)*4)(3) +FP( stfd 18,((JB_FPRS+4*2)*4)(3)) + stw r19,((JB_GPRS+5)*4)(3) +FP( stfd 19,((JB_FPRS+5*2)*4)(3)) + stw r20,((JB_GPRS+6)*4)(3) +FP( stfd 20,((JB_FPRS+6*2)*4)(3)) + stw r21,((JB_GPRS+7)*4)(3) +FP( stfd 21,((JB_FPRS+7*2)*4)(3)) + stw r22,((JB_GPRS+8)*4)(3) +FP( stfd 22,((JB_FPRS+8*2)*4)(3)) + stw r23,((JB_GPRS+9)*4)(3) +FP( stfd 23,((JB_FPRS+9*2)*4)(3)) + stw r24,((JB_GPRS+10)*4)(3) +FP( stfd 24,((JB_FPRS+10*2)*4)(3)) + stw r25,((JB_GPRS+11)*4)(3) +FP( stfd 25,((JB_FPRS+11*2)*4)(3)) + stw r26,((JB_GPRS+12)*4)(3) +FP( stfd 26,((JB_FPRS+12*2)*4)(3)) + stw r27,((JB_GPRS+13)*4)(3) +FP( stfd 27,((JB_FPRS+13*2)*4)(3)) + stw r28,((JB_GPRS+14)*4)(3) +FP( stfd 28,((JB_FPRS+14*2)*4)(3)) + stw r29,((JB_GPRS+15)*4)(3) +FP( stfd 29,((JB_FPRS+15*2)*4)(3)) + stw r30,((JB_GPRS+16)*4)(3) +FP( stfd 30,((JB_FPRS+16*2)*4)(3)) + stw r31,((JB_GPRS+17)*4)(3) +FP( stfd 31,((JB_FPRS+17*2)*4)(3)) + + li 3, 0 + blr diff --git a/examples/sched.c b/examples/sched.c new file mode 100644 index 0000000..ae01e0b --- /dev/null +++ b/examples/sched.c @@ -0,0 +1,369 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * Author: Arun Dharankar + * + * A very simple thread/schedular model: + * - only one master thread, and no parent child relation maintained + * - parent thread cannot be stopped or deleted + * - no permissions or credentials + * - no elaborate safety checks + * - cooperative multi threading + * - Simple round-robin scheduleing with no priorities + * - no metering/statistics collection + * + * Basic idea of implementing this is to allow more than one tests to + * execute "simultaneously". + * + * This may be modified such thread_yield may be called in syscalls, and + * timer interrupts. + */ + + +#define MAX_THREADS 8 + +#define CTX_SIZE 512 +#define STK_SIZE 8*1024 + +#define STATE_EMPTY 0 +#define STATE_RUNNABLE 1 +#define STATE_STOPPED 2 +#define STATE_TERMINATED 2 + +#define MASTER_THREAD 0 + +#define RC_FAILURE (-1) +#define RC_SUCCESS (0) + +typedef vu_char *jmp_ctx; +unsigned long setctxsp (vu_char *sp); +int ppc_setjmp(jmp_ctx env); +void ppc_longjmp(jmp_ctx env, int val); +#define setjmp ppc_setjmp +#define longjmp ppc_longjmp + +struct lthread { + int state; + int retval; + char stack[STK_SIZE]; + uchar context[CTX_SIZE]; + int (*func) (void *); + void *arg; +}; +static volatile struct lthread lthreads[MAX_THREADS]; +static volatile int current_tid = MASTER_THREAD; + + +static uchar dbg = 0; + +#define PDEBUG(fmt, args...) { \ + if(dbg != 0) { \ + printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__);\ + printf(fmt, ##args); \ + printf("\n"); \ + } \ +} + +static int testthread (void *); +static void sched_init (void); +static int thread_create (int (*func) (void *), void *arg); +static int thread_start (int id); +static void thread_yield (void); +static int thread_delete (int id); +static int thread_join (int *ret); + +#if 0 /* not used yet */ +static int thread_stop (int id); +#endif /* not used yet */ + +/* An example of schedular test */ + +#define NUMTHREADS 7 +int sched (int ac, char *av[]) +{ + int i, j; + int tid[NUMTHREADS]; + int names[NUMTHREADS]; + + app_startup(av); + + sched_init (); + + for (i = 0; i < NUMTHREADS; i++) { + names[i] = i; + j = thread_create (testthread, (void *) &names[i]); + if (j == RC_FAILURE) + printf ("schedtest: Failed to create thread %d\n", i); + if (j > 0) { + printf ("schedtest: Created thread with id %d, name %d\n", + j, i); + tid[i] = j; + } + } + printf ("schedtest: Threads created\n"); + + printf ("sched_test: function=0x%08x\n", (unsigned)testthread); + for (i = 0; i < NUMTHREADS; i++) { + printf ("schedtest: Setting thread %d runnable\n", tid[i]); + thread_start (tid[i]); + thread_yield (); + } + printf ("schedtest: Started %d threads\n", NUMTHREADS); + + while (1) { + printf ("schedtest: Waiting for threads to complete\n"); + if (tstc () && getc () == 0x3) { + printf ("schedtest: Aborting threads...\n"); + for (i = 0; i < NUMTHREADS; i++) { + printf ("schedtest: Deleting thread %d\n", tid[i]); + thread_delete (tid[i]); + } + return RC_SUCCESS; + } + j = -1; + i = thread_join (&j); + if (i == RC_FAILURE) { + printf ("schedtest: No threads pending, " + "exiting schedular test\n"); + return RC_SUCCESS; + } + printf ("schedtest: thread is %d returned %d\n", i, j); + thread_yield (); + } + + return RC_SUCCESS; +} + +static int testthread (void *name) +{ + int i; + + printf ("testthread: Begin executing thread, myname %d, &i=0x%08x\n", + *(int *) name, (unsigned)&i); + + printf ("Thread %02d, i=%d\n", *(int *) name, i); + + for (i = 0; i < 0xffff * (*(int *) name + 1); i++) { + if (tstc () && getc () == 0x3) { + printf ("testthread: myname %d terminating.\n", + *(int *) name); + return *(int *) name + 1; + } + + if (i % 100 == 0) + thread_yield (); + } + + printf ("testthread: returning %d, i=0x%x\n", + *(int *) name + 1, i); + + return *(int *) name + 1; +} + + +static void sched_init (void) +{ + int i; + + for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++) + lthreads[i].state = STATE_EMPTY; + + current_tid = MASTER_THREAD; + lthreads[current_tid].state = STATE_RUNNABLE; + PDEBUG ("sched_init: master context = 0x%08x", + (unsigned)lthreads[current_tid].context); + return; +} + +static void thread_yield (void) +{ + static int i; + + PDEBUG ("thread_yield: current tid=%d", current_tid); + +#define SWITCH(new) \ + if(lthreads[new].state == STATE_RUNNABLE) { \ + PDEBUG("thread_yield: %d match, ctx=0x%08x", \ + new, \ + (unsigned)lthreads[current_tid].context); \ + if(setjmp(lthreads[current_tid].context) == 0) { \ + current_tid = new; \ + PDEBUG("thread_yield: tid %d returns 0", \ + new); \ + longjmp(lthreads[new].context, 1); \ + } else { \ + PDEBUG("thread_yield: tid %d returns 1", \ + new); \ + return; \ + } \ + } + + for (i = current_tid + 1; i < MAX_THREADS; i++) { + SWITCH (i); + } + + if (current_tid != 0) { + for (i = 0; i <= current_tid; i++) { + SWITCH (i); + } + } + + PDEBUG ("thread_yield: returning from thread_yield"); + return; +} + +static int thread_create (int (*func) (void *), void *arg) +{ + int i; + + for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++) { + if (lthreads[i].state == STATE_EMPTY) { + lthreads[i].state = STATE_STOPPED; + lthreads[i].func = func; + lthreads[i].arg = arg; + PDEBUG ("thread_create: returns new tid %d", i); + return i; + } + } + + PDEBUG ("thread_create: returns failure"); + return RC_FAILURE; +} + +static int thread_delete (int id) +{ + if (id <= MASTER_THREAD || id > MAX_THREADS) + return RC_FAILURE; + + if (current_tid == id) + return RC_FAILURE; + + lthreads[id].state = STATE_EMPTY; + return RC_SUCCESS; +} + +static void thread_launcher (void) +{ + PDEBUG ("thread_launcher: invoking func=0x%08x", + (unsigned)lthreads[current_tid].func); + + lthreads[current_tid].retval = + lthreads[current_tid].func (lthreads[current_tid].arg); + + PDEBUG ("thread_launcher: tid %d terminated", current_tid); + + lthreads[current_tid].state = STATE_TERMINATED; + thread_yield (); + printf ("thread_launcher: should NEVER get here!\n"); + + return; +} + +static int thread_start (int id) +{ + PDEBUG ("thread_start: id=%d", id); + if (id <= MASTER_THREAD || id > MAX_THREADS) { + return RC_FAILURE; + } + + if (lthreads[id].state != STATE_STOPPED) + return RC_FAILURE; + + if (setjmp (lthreads[current_tid].context) == 0) { + lthreads[id].state = STATE_RUNNABLE; + current_tid = id; + PDEBUG ("thread_start: to be stack=0%08x", + (unsigned)lthreads[id].stack); + setctxsp ((vu_char *)<hreads[id].stack[STK_SIZE]); + thread_launcher (); + } + + PDEBUG ("thread_start: Thread id=%d started, parent returns", id); + + return RC_SUCCESS; +} + +#if 0 /* not used so far */ +static int thread_stop (int id) +{ + if (id <= MASTER_THREAD || id >= MAX_THREADS) + return RC_FAILURE; + + if (current_tid == id) + return RC_FAILURE; + + lthreads[id].state = STATE_STOPPED; + return RC_SUCCESS; +} +#endif /* not used so far */ + +static int thread_join (int *ret) +{ + int i, j = 0; + + PDEBUG ("thread_join: *ret = %d", *ret); + + if (!(*ret == -1 || *ret > MASTER_THREAD || *ret < MAX_THREADS)) { + PDEBUG ("thread_join: invalid tid %d", *ret); + return RC_FAILURE; + } + + if (*ret == -1) { + PDEBUG ("Checking for tid = -1"); + while (1) { + /* PDEBUG("thread_join: start while-loopn"); */ + j = 0; + for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++) { + if (lthreads[i].state == STATE_TERMINATED) { + *ret = lthreads[i].retval; + lthreads[i].state = STATE_EMPTY; + /* PDEBUG("thread_join: returning retval %d of tid %d", + ret, i); */ + return RC_SUCCESS; + } + + if (lthreads[i].state != STATE_EMPTY) { + PDEBUG ("thread_join: %d used slots tid %d state=%d", + j, i, lthreads[i].state); + j++; + } + } + if (j == 0) { + PDEBUG ("thread_join: all slots empty!"); + return RC_FAILURE; + } + /* PDEBUG("thread_join: yielding"); */ + thread_yield (); + /* PDEBUG("thread_join: back from yield"); */ + } + } + + if (lthreads[*ret].state == STATE_TERMINATED) { + i = *ret; + *ret = lthreads[*ret].retval; + lthreads[*ret].state = STATE_EMPTY; + PDEBUG ("thread_join: returing %d for tid %d", *ret, i); + return RC_SUCCESS; + } + + PDEBUG ("thread_join: thread %d is not terminated!", *ret); + return RC_FAILURE; +} diff --git a/examples/smc91111_eeprom.c b/examples/smc91111_eeprom.c new file mode 100644 index 0000000..885f933 --- /dev/null +++ b/examples/smc91111_eeprom.c @@ -0,0 +1,391 @@ +/* + * (C) Copyright 2004 + * Robin Getz rgetz@blacfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Heavily borrowed from the following peoples GPL'ed software: + * - Wolfgang Denk, DENX Software Engineering, wd@denx.de + * Das U-boot + * - Ladislav Michl ladis@linux-mips.org + * A rejected patch on the U-Boot mailing list + */ + +#include +#include +#include "../drivers/smc91111.h" + +#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE +#define EEPROM 0x1; +#define MAC 0x2; +#define UNKNOWN 0x4; + +void dump_reg (void); +void dump_eeprom (void); +int write_eeprom_reg (int, int); +void copy_from_eeprom (void); +void print_MAC (void); +int read_eeprom_reg (int); +void print_macaddr (void); + +int smc91111_eeprom (int argc, char *argv[]) +{ + int c, i, j, done, line, reg, value, start, what; + char input[50]; + + /* Print the ABI version */ + app_startup (argv); + if (XF_VERSION != (int) get_version ()) { + printf ("Expects ABI version %d\n", XF_VERSION); + printf ("Actual U-Boot ABI version %d\n", + (int) get_version ()); + printf ("Can't run\n\n"); + return (0); + } + + asm ("p2.h = 0xFFC0;"); + asm ("p2.l = 0x0730;"); + asm ("r0 = 0x01;"); + asm ("w[p2] = r0;"); + asm ("ssync;"); + + asm ("p2.h = 0xffc0;"); + asm ("p2.l = 0x0708;"); + asm ("r0 = 0x01;"); + asm ("w[p2] = r0;"); + asm ("ssync;"); + + if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + printf ("Can't find SMSC91111\n"); + return (0); + } + + done = 0; + what = UNKNOWN; + printf ("\n"); + while (!done) { + /* print the prompt */ + printf ("SMC91111> "); + line = 0; + i = 0; + start = 1; + while (!line) { + /* Wait for a keystroke */ + while (!tstc ()); + + c = getc (); + /* Make Uppercase */ + if (c >= 'Z') + c -= ('a' - 'A'); + /* printf(" |%02x| ",c); */ + + switch (c) { + case '\r': /* Enter */ + case '\n': + input[i] = 0; + puts ("\r\n"); + line = 1; + break; + case '\0': /* nul */ + continue; + + case 0x03: /* ^C - break */ + input[0] = 0; + i = 0; + line = 1; + done = 1; + break; + + case 0x5F: + case 0x08: /* ^H - backspace */ + case 0x7F: /* DEL - backspace */ + if (i > 0) { + puts ("\b \b"); + i--; + } + break; + default: + if (start) { + if ((c == 'W') || (c == 'D') + || (c == 'M') || (c == 'C') + || (c == 'P')) { + putc (c); + input[i] = c; + if (i <= 45) + i++; + start = 0; + } + } else { + if ((c >= '0' && c <= '9') + || (c >= 'A' && c <= 'F') + || (c == 'E') || (c == 'M') + || (c == ' ')) { + putc (c); + input[i] = c; + if (i <= 45) + i++; + break; + } + } + break; + } + } + + for (; i < 49; i++) + input[i] = 0; + + switch (input[0]) { + case ('W'): + /* Line should be w reg value */ + i = 0; + reg = 0; + value = 0; + /* Skip to the next space or end) */ + while ((input[i] != ' ') && (input[i] != 0)) + i++; + + if (input[i] != 0) + i++; + + /* Are we writing to EEPROM or MAC */ + switch (input[i]) { + case ('E'): + what = EEPROM; + break; + case ('M'): + what = MAC; + break; + default: + what = UNKNOWN; + break; + } + + /* skip to the next space or end */ + while ((input[i] != ' ') && (input[i] != 0)) + i++; + if (input[i] != 0) + i++; + + /* Find register to write into */ + j = 0; + while ((input[i] != ' ') && (input[i] != 0)) { + j = input[i] - 0x30; + if (j >= 0xA) { + j -= 0x07; + } + reg = (reg * 0x10) + j; + i++; + } + + while ((input[i] != ' ') && (input[i] != 0)) + i++; + + if (input[i] != 0) + i++; + else + what = UNKNOWN; + + /* Get the value to write */ + j = 0; + while ((input[i] != ' ') && (input[i] != 0)) { + j = input[i] - 0x30; + if (j >= 0xA) { + j -= 0x07; + } + value = (value * 0x10) + j; + i++; + } + + switch (what) { + case 1: + printf ("Writing EEPROM register %02x with %04x\n", + reg, value); + write_eeprom_reg (value, reg); + break; + case 2: + printf ("Writing MAC register bank %i, + reg %02x with %04x\n", reg >> 4, reg & 0xE, value); + SMC_SELECT_BANK (reg >> 4); + SMC_outw (value, reg & 0xE); + break; + default: + printf ("Wrong\n"); + break; + } + break; + case ('D'): + dump_eeprom (); + break; + case ('M'): + dump_reg (); + break; + case ('C'): + copy_from_eeprom (); + break; + case ('P'): + print_macaddr (); + break; + default: + break; + } + + } + + return (0); +} + +void copy_from_eeprom (void) +{ + int i; + + SMC_SELECT_BANK (1); + SMC_outw ((SMC_inw (CTL_REG) & !CTL_EEPROM_SELECT) | CTL_RELOAD, + CTL_REG); + i = 100; + while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --i) + udelay (100); + if (i == 0) { + printf ("Timeout Refreshing EEPROM registers\n"); + } else { + printf ("EEPROM contents copied to MAC\n"); + } + +} + +void print_macaddr (void) +{ + int i, j, k, mac[6]; + + printf ("Current MAC Address in SMSC91111 "); + SMC_SELECT_BANK (1); + for (i = 0; i < 5; i++) { + printf ("%02x:", SMC_inb (ADDR0_REG + i)); + } + + printf ("%02x\n", SMC_inb (ADDR0_REG + 5)); + + i = 0; + for (j = 0x20; j < 0x23; j++) { + k = read_eeprom_reg (j); + mac[i] = k & 0xFF; + i++; + mac[i] = k >> 8; + i++; + } + + printf ("Current MAC Address in EEPROM "); + for (i = 0; i < 5; i++) + printf ("%02x:", mac[i]); + printf ("%02x\n", mac[5]); + +} +void dump_eeprom (void) +{ + int j, k; + + printf ("IOS2-0 "); + for (j = 0; j < 8; j++) { + printf ("%03x ", j); + } + printf ("\n"); + + for (k = 0; k < 4; k++) { + if (k == 0) + printf ("CONFIG "); + if (k == 1) + printf ("BASE "); + if ((k == 2) || (k == 3)) + printf (" "); + for (j = 0; j < 0x20; j += 4) { + printf ("%02x:%04x ", j + k, read_eeprom_reg (j + k)); + } + printf ("\n"); + } + + for (j = 0x20; j < 0x40; j++) { + if ((j & 0x07) == 0) + printf ("\n"); + printf ("%02x:%04x ", j, read_eeprom_reg (j)); + } + printf ("\n"); + +} + +int read_eeprom_reg (int reg) +{ + int timeout; + + SMC_SELECT_BANK (2); + SMC_outw (reg, PTR_REG); + + SMC_SELECT_BANK (1); + SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, + CTL_REG); + timeout = 100; + while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) + udelay (100); + if (timeout == 0) { + printf ("Timeout Reading EEPROM register %02x\n", reg); + return 0; + } + + return SMC_inw (GP_REG); + +} + +int write_eeprom_reg (int value, int reg) +{ + int timeout; + + SMC_SELECT_BANK (2); + SMC_outw (reg, PTR_REG); + + SMC_SELECT_BANK (1); + SMC_outw (value, GP_REG); + SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); + timeout = 100; + while ((SMC_inw (CTL_REG) & CTL_STORE) && --timeout) + udelay (100); + if (timeout == 0) { + printf ("Timeout Writing EEPROM register %02x\n", reg); + return 0; + } + + return 1; + +} + +void dump_reg (void) +{ + int i, j; + + printf (" "); + for (j = 0; j < 4; j++) { + printf ("Bank%i ", j); + } + printf ("\n"); + for (i = 0; i < 0xF; i += 2) { + printf ("%02x ", i); + for (j = 0; j < 4; j++) { + SMC_SELECT_BANK (j); + printf ("%04x ", SMC_inw (i)); + } + printf ("\n"); + } +} diff --git a/examples/stubs.c b/examples/stubs.c new file mode 100644 index 0000000..d4c6e06 --- /dev/null +++ b/examples/stubs.c @@ -0,0 +1,165 @@ +#include + +#ifndef GCC_VERSION +#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) +#endif /* GCC_VERSION */ + +#if defined(CONFIG_I386) +/* + * x86 does not have a dedicated register to store the pointer to + * the global_data. Thus the jump table address is stored in a + * global variable, but such approach does not allow for execution + * from flash memory. The global_data address is passed as argv[-1] + * to the application program. + */ +static void **jt; +gd_t *global_data; + +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" movl %0, %%eax\n" \ +" movl jt, %%ecx\n" \ +" jmp *(%%ecx, %%eax)\n" \ + : : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx"); +#elif defined(CONFIG_PPC) +/* + * r29 holds the pointer to the global_data, r11 is a call-clobbered + * register + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" lwz %%r11, %0(%%r29)\n" \ +" lwz %%r11, %1(%%r11)\n" \ +" mtctr %%r11\n" \ +" bctr\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r11"); +#elif defined(CONFIG_ARM) +/* + * r8 holds the pointer to the global_data, ip is a call-clobbered + * register + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" ldr ip, [r8, %0]\n" \ +" ldr pc, [ip, %1]\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "ip"); +#elif defined(CONFIG_MIPS) +/* + * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call- + * clobbered register that is also used to set gp ($26). Note that the + * jr instruction also executes the instruction immediately following + * it; however, GCC/mips generates an additional `nop' after each asm + * statement + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" lw $25, %0($26)\n" \ +" lw $25, %1($25)\n" \ +" jr $25\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "t9"); +#elif defined(CONFIG_NIOS) +/* + * %g7 holds the pointer to the global_data. %g0 is call clobbered. + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" pfx %%hi(%0)\n" \ +" movi %%g0, %%lo(%0)\n" \ +" add %%g0, %%g7\n" \ +" ld %%g0, [%%g0]\n" \ +" pfx %1\n" \ +" ld %%g0, [%%g0]\n" \ +" jmp %%g0\n" \ +" nop \n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x) : "r0"); +#elif defined(CONFIG_NIOS2) +/* + * r15 holds the pointer to the global_data, r8 is call-clobbered + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" movhi r8, %%hi(%0)\n" \ +" ori r8, r0, %%lo(%0)\n" \ +" add r8, r0, r15\n" \ +" ldw r8, 0(r8)\n" \ +" ldw r8, %1(r8)\n" \ +" jmp r8\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r15"); +#elif defined(CONFIG_M68K) +/* + * d7 holds the pointer to the global_data, a0 is a call-clobbered + * register + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" move.l %%d7, %%a0\n" \ +" adda.l %0, %%a0\n" \ +" move.l (%%a0), %%a0\n" \ +" adda.l %1, %%a0\n" \ +" move.l (%%a0), %%a0\n" \ +" jmp (%%a0)\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "a0"); +#elif defined(CONFIG_MICROBLAZE) +/* + * r31 holds the pointer to the global_data. r5 is a call-clobbered. + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" lwi r5, r31, %0\n" \ +" lwi r5, r5, %1\n" \ +" bra r5\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5"); +#else +#error stubs definition missing for this architecture +#endif + +/* This function is necessary to prevent the compiler from + * generating prologue/epilogue, preparing stack frame etc. + * The stub functions are special, they do not use the stack + * frame passed to them, but pass it intact to the actual + * implementation. On the other hand, asm() statements with + * arguments can be used only inside the functions (gcc limitation) + */ +#if GCC_VERSION < 3004 +static +#endif /* GCC_VERSION */ +void __attribute__((unused)) dummy(void) +{ +#include <_exports.h> +} + +extern unsigned long __bss_start, _end; + +void app_startup(char **argv) +{ + unsigned long * cp = &__bss_start; + + /* Zero out BSS */ + while (cp < &_end) { + *cp++ = 0; + } + +#if defined(CONFIG_I386) + /* x86 does not have a dedicated register for passing global_data */ + global_data = (gd_t *)argv[-1]; + jt = global_data->jt; +#endif +} + +#undef EXPORT_FUNC diff --git a/examples/test_burst.c b/examples/test_burst.c new file mode 100644 index 0000000..f09707f --- /dev/null +++ b/examples/test_burst.c @@ -0,0 +1,319 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * The test exercises SDRAM accesses in burst mode + */ + +#include +#include + +#include +#include +#include + +#include +#include + +#include "test_burst.h" + +/* 8 MB test region of physical RAM */ +#define TEST_PADDR 0x00800000 +/* The uncached virtual region */ +#define TEST_VADDR_NC 0x00800000 +/* The cached virtual region */ +#define TEST_VADDR_C 0x01000000 +/* When an error is detected, the address where the error has been found, + and also the current and the expected data will be written to + the following flash address +*/ +#define TEST_FLASH_ADDR 0x40100000 + +/* Define GPIO ports to signal start of burst transfers and errors */ +#ifdef CONFIG_LWMON +/* Use PD.8 to signal start of burst transfers */ +#define GPIO1_DAT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) +#define GPIO1_BIT 0x0080 +/* Configure PD.8 as general purpose output */ +#define GPIO1_INIT \ + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pdpar &= ~GPIO1_BIT; \ + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddir |= GPIO1_BIT; +/* Use PD.9 to signal error */ +#define GPIO2_DAT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) +#define GPIO2_BIT 0x0040 +/* Configure PD.9 as general purpose output */ +#define GPIO2_INIT \ + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pdpar &= ~GPIO2_BIT; \ + ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddir |= GPIO2_BIT; +#endif /* CONFIG_LWMON */ + + +static void test_prepare (void); +static int test_burst_start (unsigned long size, unsigned long pattern); +static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached); +static int test_mmu_is_on(void); +static void test_desc(unsigned long size); +static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern); +static void signal_init(void); +static void signal_start(void); +static void signal_error(void); +static void test_usage(void); + +static unsigned long test_pattern [] = { + 0x00000000, + 0xffffffff, + 0x55555555, + 0xaaaaaaaa, +}; + + +int test_burst (int argc, char *argv[]) +{ + unsigned long size = CACHE_LINE_SIZE; + unsigned int pass = 0; + int res = 0; + int i, j; + + if (argc == 3) { + char * d; + for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) { + size *= 10; + size += *d - '0'; + } + if (size == 0 || *d) { + test_usage(); + return 1; + } + for (d = argv[2]; *d >= '0' && *d <= '9'; d++) { + pass *= 10; + pass += *d - '0'; + } + if (*d) { + test_usage(); + return 1; + } + } else if (argc > 3) { + test_usage(); + return 1; + } + + size += (CACHE_LINE_SIZE - 1); + size &= ~(CACHE_LINE_SIZE - 1); + + if (!test_mmu_is_on()) { + test_prepare(); + } + + test_desc(size); + + for (j = 0; !pass || j < pass; j++) { + for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]); + i++) { + res = test_burst_start(size, test_pattern[i]); + if (res != 0) { + goto Done; + } + } + + printf ("Iteration #%d passed\n", j + 1); + + if (tstc() && 0x03 == getc()) + break; + } +Done: + return res; +} + +static void test_prepare (void) +{ + printf ("\n"); + + caches_init(); + disable_interrupts(); + mmu_init(); + + printf ("Interrupts are disabled\n"); + printf ("I-Cache is ON\n"); + printf ("D-Cache is ON\n"); + printf ("MMU is ON\n"); + + printf ("\n"); + + test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0); + test_map_8M (TEST_PADDR, TEST_VADDR_C, 1); + + test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0); + + /* Configure GPIO ports */ + signal_init(); +} + +static int test_burst_start (unsigned long size, unsigned long pattern) +{ + volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C; + volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC; + int i, n; + int res = 1; + + printf ("Test pattern %08x ...", pattern); + + n = size / 4; + + for (i = 0; i < n; i ++) { + vaddr_c [i] = pattern; + } + signal_start(); + flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1); + + for (i = 0; i < n; i ++) { + register unsigned long tmp = vaddr_nc [i]; + if (tmp != pattern) { + test_error("2a", vaddr_nc + i, tmp, pattern); + goto Done; + } + } + + for (i = 0; i < n; i ++) { + register unsigned long tmp = vaddr_c [i]; + if (tmp != pattern) { + test_error("2b", vaddr_c + i, tmp, pattern); + goto Done; + } + } + + for (i = 0; i < n; i ++) { + vaddr_nc [i] = pattern; + } + + for (i = 0; i < n; i ++) { + register unsigned long tmp = vaddr_nc [i]; + if (tmp != pattern) { + test_error("3a", vaddr_nc + i, tmp, pattern); + goto Done; + } + } + + signal_start(); + for (i = 0; i < n; i ++) { + register unsigned long tmp = vaddr_c [i]; + if (tmp != pattern) { + test_error("3b", vaddr_c + i, tmp, pattern); + goto Done; + } + } + + res = 0; +Done: + printf(" %s\n", res == 0 ? "OK" : ""); + + return res; +} + +static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached) +{ + mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID); + mtspr (MD_TWC, MI_PS8MEG | MI_SVALID); + mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2)); + mtspr (MD_AP, MI_Kp); +} + +static int test_mmu_is_on(void) +{ + unsigned long msr; + + asm volatile("mfmsr %0" : "=r" (msr) :); + + return msr & MSR_DR; +} + +static void test_desc(unsigned long size) +{ + printf( + "The following tests will be conducted:\n" + "1) Map %d-byte region of physical RAM at 0x%08x\n" + " into two virtual regions:\n" + " one cached at 0x%08x and\n" + " the the other uncached at 0x%08x.\n", + size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C); + + puts( + "2) Fill the cached region with a pattern, and flush the cache\n" + "2a) Check the uncached region to match the pattern\n" + "2b) Check the cached region to match the pattern\n" + "3) Fill the uncached region with a pattern\n" + "3a) Check the cached region to match the pattern\n" + "3b) Check the uncached region to match the pattern\n" + "2b) Change the patterns and go to step 2\n" + "\n" + ); +} + +static void test_error( + char * step, volatile void * addr, unsigned long val, unsigned long pattern) +{ + volatile unsigned long * p = (void *)TEST_FLASH_ADDR; + + signal_error(); + + p[0] = (unsigned long)addr; + p[1] = val; + p[2] = pattern; + + printf ("\nError at step %s, addr %08x: read %08x, pattern %08x", + step, addr, val, pattern); +} + +static void signal_init(void) +{ +#if defined(GPIO1_INIT) + GPIO1_INIT; +#endif +#if defined(GPIO2_INIT) + GPIO2_INIT; +#endif +} + +static void signal_start(void) +{ +#if defined(GPIO1_INIT) + if (GPIO1_DAT & GPIO1_BIT) { + GPIO1_DAT &= ~GPIO1_BIT; + } else { + GPIO1_DAT |= GPIO1_BIT; + } +#endif +} + +static void signal_error(void) +{ +#if defined(GPIO2_INIT) + if (GPIO2_DAT & GPIO2_BIT) { + GPIO2_DAT &= ~GPIO2_BIT; + } else { + GPIO2_DAT |= GPIO2_BIT; + } +#endif +} + +static void test_usage(void) +{ + printf("Usage: go 0x40004 [size] [count]\n"); +} diff --git a/examples/test_burst.h b/examples/test_burst.h new file mode 100644 index 0000000..f85928c --- /dev/null +++ b/examples/test_burst.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEST_BURST_H +#define _TEST_BURST_H + +/* Cache line size */ +#define CACHE_LINE_SIZE 16 +/* Binary logarithm of the cache line size */ +#define LG_CACHE_LINE_SIZE 4 + +#ifndef __ASSEMBLY__ +extern void mmu_init(void); +extern void caches_init(void); +extern void flush_dcache_range(unsigned long start, unsigned long stop); +#endif + +#endif /* _TEST_BURST_H */ diff --git a/examples/test_burst_lib.S b/examples/test_burst_lib.S new file mode 100644 index 0000000..5bb4981 --- /dev/null +++ b/examples/test_burst_lib.S @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include +#include +#include +#include +#include "test_burst.h" + + .text +/* + * void mmu_init(void); + * + * This function turns the MMU on + * + * Three 8 MByte regions are mapped 1:1, uncached + * - SDRAM lower 8 MByte + * - SDRAM higher 8 MByte + * - IMMR + */ + .global mmu_init +mmu_init: + tlbia /* Invalidate all TLB entries */ + li r8, 0 + mtspr MI_CTR, r8 /* Set instruction control to zero */ + lis r8, MD_RESETVAL@h + mtspr MD_CTR, r8 /* Set data TLB control */ + + /* Now map the lower 8 Meg into the TLBs. For this quick hack, + * we can load the instruction and data TLB registers with the + * same values. + */ + li r8, MI_EVALID /* Create EPN for address 0 */ + mtspr MI_EPN, r8 + mtspr MD_EPN, r8 + li r8, MI_PS8MEG /* Set 8M byte page */ + ori r8, r8, MI_SVALID /* Make it valid */ + mtspr MI_TWC, r8 + mtspr MD_TWC, r8 + li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */ + mtspr MI_RPN, r8 /* Store TLB entry */ + mtspr MD_RPN, r8 + lis r8, MI_Kp@h /* Set the protection mode */ + mtspr MI_AP, r8 + mtspr MD_AP, r8 + + /* Now map the higher 8 Meg into the TLBs. For this quick hack, + * we can load the instruction and data TLB registers with the + * same values. + */ + lwz r9,20(r29) /* gd->ram_size */ + addis r9,r9,-0x80 + + mr r8, r9 /* Higher 8 Meg in SDRAM */ + ori r8, r8, MI_EVALID /* Mark page valid */ + mtspr MI_EPN, r8 + mtspr MD_EPN, r8 + li r8, MI_PS8MEG /* Set 8M byte page */ + ori r8, r8, MI_SVALID /* Make it valid */ + mtspr MI_TWC, r8 + mtspr MD_TWC, r8 + mr r8, r9 + ori r8, r8, MI_BOOTINIT|0x2 + mtspr MI_RPN, r8 /* Store TLB entry */ + mtspr MD_RPN, r8 + lis r8, MI_Kp@h /* Set the protection mode */ + mtspr MI_AP, r8 + mtspr MD_AP, r8 + + /* Map another 8 MByte at the IMMR to get the processor + * internal registers (among other things). + */ + mfspr r9, 638 /* Get current IMMR */ + andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ + + mr r8, r9 /* Create vaddr for TLB */ + ori r8, r8, MD_EVALID /* Mark it valid */ + mtspr MD_EPN, r8 + li r8, MD_PS8MEG /* Set 8M byte page */ + ori r8, r8, MD_SVALID /* Make it valid */ + mtspr MD_TWC, r8 + mr r8, r9 /* Create paddr for TLB */ + ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ + mtspr MD_RPN, r8 + + /* We now have the lower and higher 8 Meg mapped into TLB entries, + * and the caches ready to work. + */ + mfmsr r0 + ori r0,r0,MSR_DR|MSR_IR + mtspr SRR1,r0 + mflr r0 + mtspr SRR0,r0 + SYNC + rfi /* enables MMU */ + +/* + * void caches_init(void); + */ + .globl caches_init +caches_init: + sync + + mfspr r3, IC_CST /* Clear error bits */ + mfspr r3, DC_CST + + lis r3, IDC_UNALL@h /* Unlock all */ + mtspr IC_CST, r3 + mtspr DC_CST, r3 + + lis r3, IDC_INVALL@h /* Invalidate all */ + mtspr IC_CST, r3 + mtspr DC_CST, r3 + + lis r3, IDC_ENABLE@h /* Enable all */ + mtspr IC_CST, r3 + mtspr DC_CST, r3 + + blr + +/* + * void flush_dcache_range(unsigned long start, unsigned long stop); + */ + .global flush_dcache_range +flush_dcache_range: + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + +1: dcbf 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbf's to get to ram */ + blr + +/* + * void disable_interrupts(void); + */ + .global disable_interrupts +disable_interrupts: + mfmsr r0 + rlwinm r0,r0,0,17,15 + mtmsr r0 + blr diff --git a/examples/timer.c b/examples/timer.c new file mode 100644 index 0000000..037fdfd --- /dev/null +++ b/examples/timer.c @@ -0,0 +1,349 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#undef DEBUG + +#define TIMER_PERIOD 1000000 /* 1 second clock */ + +static void timer_handler (void *arg); + + +/* Access functions for the Machine State Register */ +static __inline__ unsigned long get_msr(void) +{ + unsigned long msr; + + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr(unsigned long msr) +{ + asm volatile("mtmsr %0" : : "r" (msr)); +} + +/* + * Definitions to access the CPM Timer registers + * See 8xx_immap.h for Internal Memory Map layout, + * and commproc.h for CPM Interrupt vectors (aka "IRQ"s) + */ + +typedef struct tid_8xx_cpmtimer_s { + int cpm_vec; /* CPM Interrupt Vector for this timer */ + ushort *tgcrp; /* Pointer to Timer Global Config Reg. */ + ushort *tmrp; /* Pointer to Timer Mode Register */ + ushort *trrp; /* Pointer to Timer Reference Register */ + ushort *tcrp; /* Pointer to Timer Capture Register */ + ushort *tcnp; /* Pointer to Timer Counter Register */ + ushort *terp; /* Pointer to Timer Event Register */ +} tid_8xx_cpmtimer_t; + +#ifndef CLOCKRATE +# define CLOCKRATE 64 +#endif + +#define CPMT_CLOCK_DIV 16 +#define CPMT_MAX_PRESCALER 256 +#define CPMT_MAX_REFERENCE 65535 /* max. unsigned short */ + +#define CPMT_MAX_TICKS (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER) +#define CPMT_MAX_TICKS_WITH_DIV (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER * CPMT_CLOCK_DIV) +#define CPMT_MAX_INTERVAL (CPMT_MAX_TICKS_WITH_DIV / CLOCKRATE) + +/* For now: always use max. prescaler value */ +#define CPMT_PRESCALER (CPMT_MAX_PRESCALER) + +/* CPM Timer Event Register Bits */ +#define CPMT_EVENT_CAP 0x0001 /* Capture Event */ +#define CPMT_EVENT_REF 0x0002 /* Reference Counter Event */ + +/* CPM Timer Global Config Register */ +#define CPMT_GCR_RST 0x0001 /* Reset Timer */ +#define CPMT_GCR_STP 0x0002 /* Stop Timer */ +#define CPMT_GCR_FRZ 0x0004 /* Freeze Timer */ +#define CPMT_GCR_GM_CAS 0x0008 /* Gate Mode / Cascade Timers */ +#define CPMT_GCR_MASK (CPMT_GCR_RST|CPMT_GCR_STP|CPMT_GCR_FRZ|CPMT_GCR_GM_CAS) + +/* CPM Timer Mode register */ +#define CPMT_MR_GE 0x0001 /* Gate Enable */ +#define CPMT_MR_ICLK_CASC 0x0000 /* Clock internally cascaded */ +#define CPMT_MR_ICLK_CLK 0x0002 /* Clock = system clock */ +#define CPMT_MR_ICLK_CLKDIV 0x0004 /* Clock = system clock / 16 */ +#define CPMT_MR_ICLK_TIN 0x0006 /* Clock = TINx signal */ +#define CPMT_MR_FRR 0x0008 /* Free Run / Restart */ +#define CPMT_MR_ORI 0x0010 /* Out. Reference Interrupt En. */ +#define CPMT_MR_OM 0x0020 /* Output Mode */ +#define CPMT_MR_CE_DIS 0x0000 /* Capture/Interrupt disabled */ +#define CPMT_MR_CE_RISE 0x0040 /* Capt./Interr. on rising TIN */ +#define CPMT_MR_CE_FALL 0x0080 /* Capt./Interr. on falling TIN */ +#define CPMT_MR_CE_ANY 0x00C0 /* Capt./Interr. on any TIN edge*/ + + +/* + * which CPM timer to use - index starts at 0 (= timer 1) + */ +#define TID_TIMER_ID 0 /* use CPM timer 1 */ + +void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval); + +static char *usage = "\n[q, b, e, ?] "; + +int timer (int argc, char *argv[]) +{ + DECLARE_GLOBAL_DATA_PTR; + + cpmtimer8xx_t *cpmtimerp; /* Pointer to the CPM Timer structure */ + tid_8xx_cpmtimer_t hw; + tid_8xx_cpmtimer_t *hwp = &hw; + int c; + int running; + + app_startup(argv); + + /* Pointer to CPM Timer structure */ + cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer; + + printf ("TIMERS=0x%x\n", (unsigned) cpmtimerp); + + /* Initialize pointers depending on which timer we use */ + switch (TID_TIMER_ID) { + case 0: + hwp->tmrp = &(cpmtimerp->cpmt_tmr1); + hwp->trrp = &(cpmtimerp->cpmt_trr1); + hwp->tcrp = &(cpmtimerp->cpmt_tcr1); + hwp->tcnp = &(cpmtimerp->cpmt_tcn1); + hwp->terp = &(cpmtimerp->cpmt_ter1); + hwp->cpm_vec = CPMVEC_TIMER1; + break; + case 1: + hwp->tmrp = &(cpmtimerp->cpmt_tmr2); + hwp->trrp = &(cpmtimerp->cpmt_trr2); + hwp->tcrp = &(cpmtimerp->cpmt_tcr2); + hwp->tcnp = &(cpmtimerp->cpmt_tcn2); + hwp->terp = &(cpmtimerp->cpmt_ter2); + hwp->cpm_vec = CPMVEC_TIMER2; + break; + case 2: + hwp->tmrp = &(cpmtimerp->cpmt_tmr3); + hwp->trrp = &(cpmtimerp->cpmt_trr3); + hwp->tcrp = &(cpmtimerp->cpmt_tcr3); + hwp->tcnp = &(cpmtimerp->cpmt_tcn3); + hwp->terp = &(cpmtimerp->cpmt_ter3); + hwp->cpm_vec = CPMVEC_TIMER3; + break; + case 3: + hwp->tmrp = &(cpmtimerp->cpmt_tmr4); + hwp->trrp = &(cpmtimerp->cpmt_trr4); + hwp->tcrp = &(cpmtimerp->cpmt_tcr4); + hwp->tcnp = &(cpmtimerp->cpmt_tcn4); + hwp->terp = &(cpmtimerp->cpmt_ter4); + hwp->cpm_vec = CPMVEC_TIMER4; + break; + } + + hwp->tgcrp = &cpmtimerp->cpmt_tgcr; + + printf ("Using timer %d\n" + "tgcr @ 0x%x, tmr @ 0x%x, trr @ 0x%x," + " tcr @ 0x%x, tcn @ 0x%x, ter @ 0x%x\n", + TID_TIMER_ID + 1, + (unsigned) hwp->tgcrp, + (unsigned) hwp->tmrp, + (unsigned) hwp->trrp, + (unsigned) hwp->tcrp, + (unsigned) hwp->tcnp, + (unsigned) hwp->terp + ); + + /* reset timer */ + *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID); + + /* clear all events */ + *hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF); + + printf (usage); + running = 0; + while ((c = getc()) != 'q') { + if (c == 'b') { + + setPeriod (hwp, TIMER_PERIOD); /* Set period and start ticking */ + + /* Install interrupt handler (enable timer in CIMR) */ + install_hdlr (hwp->cpm_vec, timer_handler, hwp); + + printf ("Enabling timer\n"); + + /* enable timer */ + *hwp->tgcrp |= (CPMT_GCR_RST << TID_TIMER_ID); + running = 1; + +#ifdef DEBUG + printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x," + " tcr=0x%x, tcn=0x%x, ter=0x%x\n", + *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, + *hwp->tcrp, *hwp->tcnp, *hwp->terp + ); +#endif + } else if (c == 'e') { + + printf ("Stopping timer\n"); + + *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID); + running = 0; + +#ifdef DEBUG + printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x," + " tcr=0x%x, tcn=0x%x, ter=0x%x\n", + *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, + *hwp->tcrp, *hwp->tcnp, *hwp->terp + ); +#endif + /* Uninstall interrupt handler */ + free_hdlr (hwp->cpm_vec); + + } else if (c == '?') { +#ifdef DEBUG + cpic8xx_t *cpm_icp = &((immap_t *) gd->bd->bi_immr_base)->im_cpic; + sysconf8xx_t *siup = &((immap_t *) gd->bd->bi_immr_base)->im_siu_conf; +#endif + + printf ("\ntgcr=0x%x, tmr=0x%x, trr=0x%x," + " tcr=0x%x, tcn=0x%x, ter=0x%x\n", + *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, + *hwp->tcrp, *hwp->tcnp, *hwp->terp + ); +#ifdef DEBUG + printf ("SIUMCR=0x%08lx, SYPCR=0x%08lx," + " SIMASK=0x%08lx, SIPEND=0x%08lx\n", + siup->sc_siumcr, + siup->sc_sypcr, + siup->sc_simask, + siup->sc_sipend + ); + + printf ("CIMR=0x%08lx, CICR=0x%08lx, CIPR=0x%08lx\n", + cpm_icp->cpic_cimr, + cpm_icp->cpic_cicr, + cpm_icp->cpic_cipr + ); +#endif + } else { + printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n"); + } + printf (usage); + } + if (running) { + printf ("Stopping timer\n"); + *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID); + free_hdlr (hwp->cpm_vec); + } + + return (0); +} + + +/* Set period in microseconds and start. + * Truncate to maximum period if more than this is requested - but warn about it. + */ + +void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval) +{ + unsigned short prescaler; + unsigned long ticks; + + printf ("Set interval %ld us\n", interval); + + /* Warn if requesting longer period than possible */ + if (interval > CPMT_MAX_INTERVAL) { + printf ("Truncate interval %ld to maximum (%d)\n", + interval, CPMT_MAX_INTERVAL); + interval = CPMT_MAX_INTERVAL; + } + /* + * Check if we want to use clock divider: + * Since the reference counter can be incremented only in integer steps, + * we try to keep it as big as possible to allow the resulting period to be + * as precise as possible. + */ + /* prescaler, enable interrupt, restart after ref count is reached */ + prescaler = (ushort) ((CPMT_PRESCALER - 1) << 8) | + CPMT_MR_ORI | + CPMT_MR_FRR; + + ticks = ((ulong) CLOCKRATE * interval); + + if (ticks > CPMT_MAX_TICKS) { + ticks /= CPMT_CLOCK_DIV; + prescaler |= CPMT_MR_ICLK_CLKDIV; /* use system clock divided by 16 */ + } else { + prescaler |= CPMT_MR_ICLK_CLK; /* use system clock without divider */ + } + +#ifdef DEBUG + printf ("clock/%d, prescale factor %d, reference %ld, ticks %ld\n", + (ticks > CPMT_MAX_TICKS) ? CPMT_CLOCK_DIV : 1, + CPMT_PRESCALER, + (ticks / CPMT_PRESCALER), + ticks + ); +#endif + + /* set prescaler register */ + *hwp->tmrp = prescaler; + + /* clear timer counter */ + *hwp->tcnp = 0; + + /* set reference register */ + *hwp->trrp = (unsigned short) (ticks / CPMT_PRESCALER); + +#ifdef DEBUG + printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x," + " tcr=0x%x, tcn=0x%x, ter=0x%x\n", + *hwp->tgcrp, *hwp->tmrp, *hwp->trrp, + *hwp->tcrp, *hwp->tcnp, *hwp->terp + ); +#endif +} + +/* + * Handler for CPMVEC_TIMER1 interrupt + */ +static +void timer_handler (void *arg) +{ + tid_8xx_cpmtimer_t *hwp = (tid_8xx_cpmtimer_t *)arg; + + /* printf ("** TER1=%04x ** ", *hwp->terp); */ + + /* just for demonstration */ + printf ("."); + + /* clear all possible events: Ref. and Cap. */ + *hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF); +} diff --git a/examples/x86-testapp.c b/examples/x86-testapp.c new file mode 100644 index 0000000..a1ab319 --- /dev/null +++ b/examples/x86-testapp.c @@ -0,0 +1,87 @@ +#include +#include +#include + +void *func[8], **pfunc; + +typedef struct xxx xxx_t; +struct xxx { + int dummy; + void **pfunc; +} q; + +#define XF_strcpy 3 +#define XF_printf 4 + +#define LABEL(x) \ +asm volatile ( \ + +#if defined(__i386__) +#define EXPORT_FUNC(x) \ +asm volatile ( \ +" .globl mon_" #x "\n" \ +"mon_" #x ":\n" \ +" movl %0, %%eax\n" \ +" movl pfunc, %%ecx\n" \ +" jmp *(%%ecx,%%eax)\n" \ + : : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx"); +#elif defined(__powerpc__) +#define EXPORT_FUNC(x) \ +asm volatile ( \ +" .globl mon_" #x "\n" \ +"mon_" #x ":\n" \ +" lwz %%r11, %0(%%r29)\n" \ +" lwz %%r11, %1(%%r11)\n" \ +" mtctr %%r11\n" \ +" bctr\n" \ + : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "r11", "r29"); +#elif defined(__arm__) +#define EXPORT_FUNC(x) \ +asm volatile ( \ +" .globl mon_" #x "\n" \ +"mon_" #x ":\n" \ +" ldr ip, [r8, %0]\n" \ +" ldr pc, [ip, %1]\n" \ + : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "ip"); +#elif defined(__mips__) +#define EXPORT_FUNC(x) \ +asm volatile ( \ +" .globl mon_" #x "\n" \ +"mon_" #x ":\n" \ +" lw $25, %0($26)\n" \ +" lw $25, %1($25)\n" \ +" jr $25\n" \ + : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9"); +#else +#error [No stub code for this arch] +#endif + +void dummy(void) +{ +EXPORT_FUNC(printf) +EXPORT_FUNC(strcpy) +} + +int main(void) +{ +#if defined(__i386__) + xxx_t *pq; +#elif defined(__powerpc__) + register volatile xxx_t *pq asm("r29"); +#elif defined(__arm__) + register volatile xxx_t *pq asm("r8"); +#elif defined(__mips__) + register volatile xxx_t *pq asm("k0"); +#endif + char buf[32]; + + func[XF_strcpy] = strcpy; + func[XF_printf] = printf; + pq = &q; + pq->pfunc = pfunc = func; + + mon_strcpy(buf, "test"); + mon_printf("hi %s %d z\n", buf, 444); + + return 0; +} diff --git a/fs/Makefile b/fs/Makefile new file mode 100644 index 0000000..79cbdea --- /dev/null +++ b/fs/Makefile @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# + +SUBDIRS := jffs2 cramfs fdos fat reiserfs ext2 + +.depend all: + @for dir in $(SUBDIRS) ; do \ + $(MAKE) -C $$dir $@ ; done diff --git a/fs/cramfs/Makefile b/fs/cramfs/Makefile new file mode 100644 index 0000000..54a475e --- /dev/null +++ b/fs/cramfs/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libcramfs.a + +AOBJS = +COBJS = cramfs.o uncompress.o +OBJS = $(AOBJS) $(COBJS) + +#CPPFLAGS += + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c new file mode 100644 index 0000000..48e7f63 --- /dev/null +++ b/fs/cramfs/cramfs.c @@ -0,0 +1,347 @@ +/* + * cramfs.c + * + * Copyright (C) 1999 Linus Torvalds + * + * Copyright (C) 2000-2002 Transmeta Corporation + * + * Copyright (C) 2003 Kai-Uwe Bloem, + * Auerswald GmbH & Co KG, + * - adapted from the www.tuxbox.org u-boot tree, added "ls" command + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * Compressed ROM filesystem for Linux. + * + * TODO: + * add support for resolving symbolic links + */ + +/* + * These are the VFS interfaces to the compressed ROM filesystem. + * The actual compression is based on zlib, see the other files. + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include +#include +#include +#include +#include + +/* These two macros may change in future, to provide better st_ino + semantics. */ +#define CRAMINO(x) (CRAMFS_GET_OFFSET(x) ? CRAMFS_GET_OFFSET(x)<<2 : 1) +#define OFFSET(x) ((x)->i_ino) + +struct cramfs_super super; + +/* CPU address space offset calculation macro, struct part_info offset is + * device address space offset, so we need to shift it by a device start address. */ +extern flash_info_t flash_info[]; +#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0]) + +static int cramfs_read_super (struct part_info *info) +{ + unsigned long root_offset; + + /* Read the first block and get the superblock from it */ + memcpy (&super, (void *) PART_OFFSET(info), sizeof (super)); + + /* Do sanity checks on the superblock */ + if (super.magic != CRAMFS_32 (CRAMFS_MAGIC)) { + /* check at 512 byte offset */ + memcpy (&super, (void *) PART_OFFSET(info) + 512, sizeof (super)); + if (super.magic != CRAMFS_32 (CRAMFS_MAGIC)) { + printf ("cramfs: wrong magic\n"); + return -1; + } + } + + /* flags is reused several times, so swab it once */ + super.flags = CRAMFS_32 (super.flags); + super.size = CRAMFS_32 (super.size); + + /* get feature flags first */ + if (super.flags & ~CRAMFS_SUPPORTED_FLAGS) { + printf ("cramfs: unsupported filesystem features\n"); + return -1; + } + + /* Check that the root inode is in a sane state */ + if (!S_ISDIR (CRAMFS_16 (super.root.mode))) { + printf ("cramfs: root is not a directory\n"); + return -1; + } + root_offset = CRAMFS_GET_OFFSET (&(super.root)) << 2; + if (root_offset == 0) { + printf ("cramfs: empty filesystem"); + } else if (!(super.flags & CRAMFS_FLAG_SHIFTED_ROOT_OFFSET) && + ((root_offset != sizeof (struct cramfs_super)) && + (root_offset != 512 + sizeof (struct cramfs_super)))) { + printf ("cramfs: bad root offset %lu\n", root_offset); + return -1; + } + + return 0; +} + +static unsigned long cramfs_resolve (unsigned long begin, unsigned long offset, + unsigned long size, int raw, + char *filename) +{ + unsigned long inodeoffset = 0, nextoffset; + + while (inodeoffset < size) { + struct cramfs_inode *inode; + char *name; + int namelen; + + inode = (struct cramfs_inode *) (begin + offset + + inodeoffset); + + /* + * Namelengths on disk are shifted by two + * and the name padded out to 4-byte boundaries + * with zeroes. + */ + namelen = CRAMFS_GET_NAMELEN (inode) << 2; + name = (char *) inode + sizeof (struct cramfs_inode); + + nextoffset = + inodeoffset + sizeof (struct cramfs_inode) + namelen; + + for (;;) { + if (!namelen) + return -1; + if (name[namelen - 1]) + break; + namelen--; + } + + if (!strncmp (filename, name, namelen)) { + char *p = strtok (NULL, "/"); + + if (raw && (p == NULL || *p == '\0')) + return offset + inodeoffset; + + if (S_ISDIR (CRAMFS_16 (inode->mode))) { + return cramfs_resolve (begin, + CRAMFS_GET_OFFSET + (inode) << 2, + CRAMFS_24 (inode-> + size), raw, + p); + } else if (S_ISREG (CRAMFS_16 (inode->mode))) { + return offset + inodeoffset; + } else { + printf ("%*.*s: unsupported file type (%x)\n", + namelen, namelen, name, + CRAMFS_16 (inode->mode)); + return 0; + } + } + + inodeoffset = nextoffset; + } + + printf ("can't find corresponding entry\n"); + return 0; +} + +static int cramfs_uncompress (unsigned long begin, unsigned long offset, + unsigned long loadoffset) +{ + struct cramfs_inode *inode = (struct cramfs_inode *) (begin + offset); + unsigned long *block_ptrs = (unsigned long *) + (begin + (CRAMFS_GET_OFFSET (inode) << 2)); + unsigned long curr_block = (CRAMFS_GET_OFFSET (inode) + + (((CRAMFS_24 (inode->size)) + + 4095) >> 12)) << 2; + int size, total_size = 0; + int i; + + cramfs_uncompress_init (); + + for (i = 0; i < ((CRAMFS_24 (inode->size) + 4095) >> 12); i++) { + size = cramfs_uncompress_block ((void *) loadoffset, + (void *) (begin + curr_block), + (CRAMFS_32 (block_ptrs[i]) - + curr_block)); + if (size < 0) + return size; + loadoffset += size; + total_size += size; + curr_block = CRAMFS_32 (block_ptrs[i]); + } + + cramfs_uncompress_exit (); + return total_size; +} + +int cramfs_load (char *loadoffset, struct part_info *info, char *filename) +{ + unsigned long offset; + + if (cramfs_read_super (info)) + return -1; + + offset = cramfs_resolve (PART_OFFSET(info), + CRAMFS_GET_OFFSET (&(super.root)) << 2, + CRAMFS_24 (super.root.size), 0, + strtok (filename, "/")); + + if (offset <= 0) + return offset; + + return cramfs_uncompress (PART_OFFSET(info), offset, + (unsigned long) loadoffset); +} + +static int cramfs_list_inode (struct part_info *info, unsigned long offset) +{ + struct cramfs_inode *inode = (struct cramfs_inode *) + (PART_OFFSET(info) + offset); + char *name, str[20]; + int namelen, nextoff; + + /* + * Namelengths on disk are shifted by two + * and the name padded out to 4-byte boundaries + * with zeroes. + */ + namelen = CRAMFS_GET_NAMELEN (inode) << 2; + name = (char *) inode + sizeof (struct cramfs_inode); + nextoff = namelen; + + for (;;) { + if (!namelen) + return namelen; + if (name[namelen - 1]) + break; + namelen--; + } + + printf (" %s %8d %*.*s", mkmodestr (CRAMFS_16 (inode->mode), str), + CRAMFS_24 (inode->size), namelen, namelen, name); + + if ((CRAMFS_16 (inode->mode) & S_IFMT) == S_IFLNK) { + /* symbolic link. + * Unpack the link target, trusting in the inode's size field. + */ + unsigned long size = CRAMFS_24 (inode->size); + char *link = malloc (size); + + if (link != NULL && cramfs_uncompress (PART_OFFSET(info), offset, + (unsigned long) link) + == size) + printf (" -> %*.*s\n", (int) size, (int) size, link); + else + printf (" [Error reading link]\n"); + if (link) + free (link); + } else + printf ("\n"); + + return nextoff; +} + +int cramfs_ls (struct part_info *info, char *filename) +{ + struct cramfs_inode *inode; + unsigned long inodeoffset = 0, nextoffset; + unsigned long offset, size; + + if (cramfs_read_super (info)) + return -1; + + if (strlen (filename) == 0 || !strcmp (filename, "/")) { + /* Root directory. Use root inode in super block */ + offset = CRAMFS_GET_OFFSET (&(super.root)) << 2; + size = CRAMFS_24 (super.root.size); + } else { + /* Resolve the path */ + offset = cramfs_resolve (PART_OFFSET(info), + CRAMFS_GET_OFFSET (&(super.root)) << + 2, CRAMFS_24 (super.root.size), 1, + strtok (filename, "/")); + + if (offset <= 0) + return offset; + + /* Resolving was successful. Examine the inode */ + inode = (struct cramfs_inode *) (PART_OFFSET(info) + offset); + if (!S_ISDIR (CRAMFS_16 (inode->mode))) { + /* It's not a directory - list it, and that's that */ + return (cramfs_list_inode (info, offset) > 0); + } + + /* It's a directory. List files within */ + offset = CRAMFS_GET_OFFSET (inode) << 2; + size = CRAMFS_24 (inode->size); + } + + /* List the given directory */ + while (inodeoffset < size) { + inode = (struct cramfs_inode *) (PART_OFFSET(info) + offset + + inodeoffset); + + nextoffset = cramfs_list_inode (info, offset + inodeoffset); + if (nextoffset == 0) + break; + inodeoffset += sizeof (struct cramfs_inode) + nextoffset; + } + + return 1; +} + +int cramfs_info (struct part_info *info) +{ + if (cramfs_read_super (info)) + return 0; + + printf ("size: 0x%x (%u)\n", super.size, super.size); + + if (super.flags != 0) { + printf ("flags:\n"); + if (super.flags & CRAMFS_FLAG_FSID_VERSION_2) + printf ("\tFSID version 2\n"); + if (super.flags & CRAMFS_FLAG_SORTED_DIRS) + printf ("\tsorted dirs\n"); + if (super.flags & CRAMFS_FLAG_HOLES) + printf ("\tholes\n"); + if (super.flags & CRAMFS_FLAG_SHIFTED_ROOT_OFFSET) + printf ("\tshifted root offset\n"); + } + + printf ("fsid:\n\tcrc: 0x%x\n\tedition: 0x%x\n", + super.fsid.crc, super.fsid.edition); + printf ("name: %16s\n", super.name); + + return 1; +} + +int cramfs_check (struct part_info *info) +{ + struct cramfs_super *sb; + + if (info->dev->id->type != MTD_DEV_TYPE_NOR) + return 0; + + sb = (struct cramfs_super *) PART_OFFSET(info); + if (sb->magic != CRAMFS_32 (CRAMFS_MAGIC)) { + /* check at 512 byte offset */ + sb = (struct cramfs_super *) (PART_OFFSET(info) + 512); + if (sb->magic != CRAMFS_32 (CRAMFS_MAGIC)) + return 0; + } + return 1; +} + +#endif /* CFG_FS_CRAMFS */ diff --git a/fs/cramfs/uncompress.c b/fs/cramfs/uncompress.c new file mode 100644 index 0000000..170832a --- /dev/null +++ b/fs/cramfs/uncompress.c @@ -0,0 +1,106 @@ +/* + * uncompress.c + * + * Copyright (C) 1999 Linus Torvalds + * Copyright (C) 2000-2002 Transmeta Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * cramfs interfaces to the uncompression library. There's really just + * three entrypoints: + * + * - cramfs_uncompress_init() - called to initialize the thing. + * - cramfs_uncompress_exit() - tell me when you're done + * - cramfs_uncompress_block() - uncompress a block. + * + * NOTE NOTE NOTE! The uncompression is entirely single-threaded. We + * only have one stream, and we'll initialize it only once even if it + * then is used by multiple filesystems. + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +static z_stream stream; + +#define ZALLOC_ALIGNMENT 16 + +static void *zalloc (void *x, unsigned items, unsigned size) +{ + void *p; + + size *= items; + size = (size + ZALLOC_ALIGNMENT - 1) & ~(ZALLOC_ALIGNMENT - 1); + + p = malloc (size); + + return (p); +} + +static void zfree (void *x, void *addr, unsigned nb) +{ + free (addr); +} + +/* Returns length of decompressed data. */ +int cramfs_uncompress_block (void *dst, void *src, int srclen) +{ + int err; + + inflateReset (&stream); + + stream.next_in = src; + stream.avail_in = srclen; + + stream.next_out = dst; + stream.avail_out = 4096 * 2; + + err = inflate (&stream, Z_FINISH); + + if (err != Z_STREAM_END) + goto err; + return stream.total_out; + + err: + /*printf ("Error %d while decompressing!\n", err); */ + /*printf ("%p(%d)->%p\n", src, srclen, dst); */ + return -1; +} + +int cramfs_uncompress_init (void) +{ + int err; + + stream.zalloc = zalloc; + stream.zfree = zfree; + stream.next_in = 0; + stream.avail_in = 0; + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + stream.outcb = (cb_func) WATCHDOG_RESET; +#else + stream.outcb = Z_NULL; +#endif /* CONFIG_HW_WATCHDOG */ + + err = inflateInit (&stream); + if (err != Z_OK) { + printf ("Error: inflateInit2() returned %d\n", err); + return -1; + } + + return 0; +} + +int cramfs_uncompress_exit (void) +{ + inflateEnd (&stream); + return 0; +} + +#endif /* CFG_FS_CRAMFS */ diff --git a/fs/ext2/Makefile b/fs/ext2/Makefile new file mode 100644 index 0000000..3b19368 --- /dev/null +++ b/fs/ext2/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2003 +# Pavel Bartusek, Sysgo Real-Time Solutions AG, pba@sysgo.de +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libext2fs.a + +AOBJS = +COBJS = ext2fs.o dev.o +OBJS = $(AOBJS) $(COBJS) + +#CPPFLAGS += + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/fs/ext2/dev.c b/fs/ext2/dev.c new file mode 100644 index 0000000..1469e98 --- /dev/null +++ b/fs/ext2/dev.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2004 + * esd gmbh + * Reinhard Arlt + * + * based on code of fs/reiserfs/dev.c by + * + * (C) Copyright 2003 - 2004 + * Sysgo AG, , Pavel Bartusek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +#include +#if (CONFIG_COMMANDS & CFG_CMD_EXT2) + +#include +#include + +static block_dev_desc_t *ext2fs_block_dev_desc; +static disk_partition_t part_info; + +int ext2fs_set_blk_dev (block_dev_desc_t * rbdd, int part) +{ + ext2fs_block_dev_desc = rbdd; + + if (part == 0) { + /* disk doesn't use partition table */ + part_info.start = 0; + part_info.size = rbdd->lba; + part_info.blksz = rbdd->blksz; + } else { + if (get_partition_info + (ext2fs_block_dev_desc, part, &part_info)) { + return 0; + } + } + return (part_info.size); +} + + +int ext2fs_devread (int sector, int byte_offset, int byte_len, char *buf) { + char sec_buf[SECTOR_SIZE]; + unsigned block_len; + +/* + * Check partition boundaries + */ + if ((sector < 0) + || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >= + part_info.size)) { + /* errnum = ERR_OUTSIDE_PART; */ + printf (" ** ext2fs_devread() read outside partition sector %d\n", sector); + return (0); + } + +/* + * Get the read to the beginning of a partition. + */ + sector += byte_offset >> SECTOR_BITS; + byte_offset &= SECTOR_SIZE - 1; + + debug (" <%d, %d, %d>\n", sector, byte_offset, byte_len); + + if (ext2fs_block_dev_desc == NULL) { + printf ("** Invalid Block Device Descriptor (NULL)\n"); + return (0); + } + + if (byte_offset != 0) { + /* read first part which isn't aligned with start of sector */ + if (ext2fs_block_dev_desc-> + block_read (ext2fs_block_dev_desc->dev, + part_info.start + sector, 1, + (unsigned long *) sec_buf) != 1) { + printf (" ** ext2fs_devread() read error **\n"); + return (0); + } + memcpy (buf, sec_buf + byte_offset, + min (SECTOR_SIZE - byte_offset, byte_len)); + buf += min (SECTOR_SIZE - byte_offset, byte_len); + byte_len -= min (SECTOR_SIZE - byte_offset, byte_len); + sector++; + } + + /* read sector aligned part */ + block_len = byte_len & ~(SECTOR_SIZE - 1); + if (ext2fs_block_dev_desc->block_read (ext2fs_block_dev_desc->dev, + part_info.start + sector, + block_len / SECTOR_SIZE, + (unsigned long *) buf) != + block_len / SECTOR_SIZE) { + printf (" ** ext2fs_devread() read error - block\n"); + return (0); + } + buf += block_len; + byte_len -= block_len; + sector += block_len / SECTOR_SIZE; + + if (byte_len != 0) { + /* read rest of data which are not in whole sector */ + if (ext2fs_block_dev_desc-> + block_read (ext2fs_block_dev_desc->dev, + part_info.start + sector, 1, + (unsigned long *) sec_buf) != 1) { + printf (" ** ext2fs_devread() read error - last part\n"); + return (0); + } + memcpy (buf, sec_buf, byte_len); + } + return (1); +} +#endif /* CFG_CMD_EXT2FS */ diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c new file mode 100644 index 0000000..c21d2d6 --- /dev/null +++ b/fs/ext2/ext2fs.c @@ -0,0 +1,878 @@ +/* + * (C) Copyright 2004 + * esd gmbh + * Reinhard Arlt + * + * based on code from grub2 fs/ext2.c and fs/fshelp.c by + * + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2003, 2004 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_EXT2) +#include +#include +#include + +extern int ext2fs_devread (int sector, int byte_offset, int byte_len, + char *buf); + +/* Magic value used to identify an ext2 filesystem. */ +#define EXT2_MAGIC 0xEF53 +/* Amount of indirect blocks in an inode. */ +#define INDIRECT_BLOCKS 12 +/* Maximum lenght of a pathname. */ +#define EXT2_PATH_MAX 4096 +/* Maximum nesting of symlinks, used to prevent a loop. */ +#define EXT2_MAX_SYMLINKCNT 8 + +/* Filetype used in directory entry. */ +#define FILETYPE_UNKNOWN 0 +#define FILETYPE_REG 1 +#define FILETYPE_DIRECTORY 2 +#define FILETYPE_SYMLINK 7 + +/* Filetype information as used in inodes. */ +#define FILETYPE_INO_MASK 0170000 +#define FILETYPE_INO_REG 0100000 +#define FILETYPE_INO_DIRECTORY 0040000 +#define FILETYPE_INO_SYMLINK 0120000 + +/* Bits used as offset in sector */ +#define DISK_SECTOR_BITS 9 + +/* Log2 size of ext2 block in 512 blocks. */ +#define LOG2_EXT2_BLOCK_SIZE(data) (__le32_to_cpu (data->sblock.log2_block_size) + 1) + +/* Log2 size of ext2 block in bytes. */ +#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu (data->sblock.log2_block_size) + 10) + +/* The size of an ext2 block in bytes. */ +#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data)) + +/* The ext2 superblock. */ +struct ext2_sblock { + uint32_t total_inodes; + uint32_t total_blocks; + uint32_t reserved_blocks; + uint32_t free_blocks; + uint32_t free_inodes; + uint32_t first_data_block; + uint32_t log2_block_size; + uint32_t log2_fragment_size; + uint32_t blocks_per_group; + uint32_t fragments_per_group; + uint32_t inodes_per_group; + uint32_t mtime; + uint32_t utime; + uint16_t mnt_count; + uint16_t max_mnt_count; + uint16_t magic; + uint16_t fs_state; + uint16_t error_handling; + uint16_t minor_revision_level; + uint32_t lastcheck; + uint32_t checkinterval; + uint32_t creator_os; + uint32_t revision_level; + uint16_t uid_reserved; + uint16_t gid_reserved; + uint32_t first_inode; + uint16_t inode_size; + uint16_t block_group_number; + uint32_t feature_compatibility; + uint32_t feature_incompat; + uint32_t feature_ro_compat; + uint32_t unique_id[4]; + char volume_name[16]; + char last_mounted_on[64]; + uint32_t compression_info; +}; + +/* The ext2 blockgroup. */ +struct ext2_block_group { + uint32_t block_id; + uint32_t inode_id; + uint32_t inode_table_id; + uint16_t free_blocks; + uint16_t free_inodes; + uint16_t pad; + uint32_t reserved[3]; +}; + +/* The ext2 inode. */ +struct ext2_inode { + uint16_t mode; + uint16_t uid; + uint32_t size; + uint32_t atime; + uint32_t ctime; + uint32_t mtime; + uint32_t dtime; + uint16_t gid; + uint16_t nlinks; + uint32_t blockcnt; /* Blocks of 512 bytes!! */ + uint32_t flags; + uint32_t osd1; + union { + struct datablocks { + uint32_t dir_blocks[INDIRECT_BLOCKS]; + uint32_t indir_block; + uint32_t double_indir_block; + uint32_t tripple_indir_block; + } blocks; + char symlink[60]; + } b; + uint32_t version; + uint32_t acl; + uint32_t dir_acl; + uint32_t fragment_addr; + uint32_t osd2[3]; +}; + +/* The header of an ext2 directory entry. */ +struct ext2_dirent { + uint32_t inode; + uint16_t direntlen; + uint8_t namelen; + uint8_t filetype; +}; + +struct ext2fs_node { + struct ext2_data *data; + struct ext2_inode inode; + int ino; + int inode_read; +}; + +/* Information about a "mounted" ext2 filesystem. */ +struct ext2_data { + struct ext2_sblock sblock; + struct ext2_inode *inode; + struct ext2fs_node diropen; +}; + + +typedef struct ext2fs_node *ext2fs_node_t; + +struct ext2_data *ext2fs_root = NULL; +ext2fs_node_t ext2fs_file = NULL; +int symlinknest = 0; +uint32_t *indir1_block = NULL; +int indir1_size = 0; +int indir1_blkno = -1; +uint32_t *indir2_block = NULL; +int indir2_size = 0; +int indir2_blkno = -1; + + +static int ext2fs_blockgroup + (struct ext2_data *data, int group, struct ext2_block_group *blkgrp) { +#ifdef DEBUG + printf ("ext2fs read blockgroup\n"); +#endif + return (ext2fs_devread + (((__le32_to_cpu (data->sblock.first_data_block) + + 1) << LOG2_EXT2_BLOCK_SIZE (data)), + group * sizeof (struct ext2_block_group), + sizeof (struct ext2_block_group), (char *) blkgrp)); +} + + +static int ext2fs_read_inode + (struct ext2_data *data, int ino, struct ext2_inode *inode) { + struct ext2_block_group blkgrp; + struct ext2_sblock *sblock = &data->sblock; + int inodes_per_block; + int status; + + unsigned int blkno; + unsigned int blkoff; + + /* It is easier to calculate if the first inode is 0. */ + ino--; +#ifdef DEBUG + printf ("ext2fs read inode %d\n", ino); +#endif + status = ext2fs_blockgroup (data, + ino / + __le32_to_cpu (sblock->inodes_per_group), + &blkgrp); + if (status == 0) { + return (0); + } + inodes_per_block = EXT2_BLOCK_SIZE (data) / 128; + blkno = (ino % __le32_to_cpu (sblock->inodes_per_group)) / + inodes_per_block; + blkoff = (ino % __le32_to_cpu (sblock->inodes_per_group)) % + inodes_per_block; +#ifdef DEBUG + printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff); +#endif + /* Read the inode. */ + status = ext2fs_devread (((__le32_to_cpu (blkgrp.inode_table_id) + + blkno) << LOG2_EXT2_BLOCK_SIZE (data)), + sizeof (struct ext2_inode) * blkoff, + sizeof (struct ext2_inode), (char *) inode); + if (status == 0) { + return (0); + } + return (1); +} + + +void ext2fs_free_node (ext2fs_node_t node, ext2fs_node_t currroot) { + if ((node != &ext2fs_root->diropen) && (node != currroot)) { + free (node); + } +} + + +static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { + struct ext2_data *data = node->data; + struct ext2_inode *inode = &node->inode; + int blknr; + int blksz = EXT2_BLOCK_SIZE (data); + int log2_blksz = LOG2_EXT2_BLOCK_SIZE (data); + int status; + + /* Direct blocks. */ + if (fileblock < INDIRECT_BLOCKS) { + blknr = __le32_to_cpu (inode->b.blocks.dir_blocks[fileblock]); + } + /* Indirect. */ + else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) { + if (indir1_block == NULL) { + indir1_block = (uint32_t *) malloc (blksz); + if (indir1_block == NULL) { + printf ("** ext2fs read block (indir 1) malloc failed. **\n"); + return (-1); + } + indir1_size = blksz; + indir1_blkno = -1; + } + if (blksz != indir1_size) { + free (indir1_block); + indir1_block = NULL; + indir1_size = 0; + indir1_blkno = -1; + indir1_block = (uint32_t *) malloc (blksz); + if (indir1_block == NULL) { + printf ("** ext2fs read block (indir 1) malloc failed. **\n"); + return (-1); + } + indir1_size = blksz; + } + if ((__le32_to_cpu (inode->b.blocks.indir_block) << + log2_blksz) != indir1_blkno) { + status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.indir_block) << log2_blksz, + 0, blksz, + (char *) indir1_block); + if (status == 0) { + printf ("** ext2fs read block (indir 1) failed. **\n"); + return (0); + } + indir1_blkno = + __le32_to_cpu (inode->b.blocks. + indir_block) << log2_blksz; + } + blknr = __le32_to_cpu (indir1_block + [fileblock - INDIRECT_BLOCKS]); + } + /* Double indirect. */ + else if (fileblock < + (INDIRECT_BLOCKS + (blksz / 4 * (blksz / 4 + 1)))) { + unsigned int perblock = blksz / 4; + unsigned int rblock = fileblock - (INDIRECT_BLOCKS + + blksz / 4); + + if (indir1_block == NULL) { + indir1_block = (uint32_t *) malloc (blksz); + if (indir1_block == NULL) { + printf ("** ext2fs read block (indir 2 1) malloc failed. **\n"); + return (-1); + } + indir1_size = blksz; + indir1_blkno = -1; + } + if (blksz != indir1_size) { + free (indir1_block); + indir1_block = NULL; + indir1_size = 0; + indir1_blkno = -1; + indir1_block = (uint32_t *) malloc (blksz); + if (indir1_block == NULL) { + printf ("** ext2fs read block (indir 2 1) malloc failed. **\n"); + return (-1); + } + indir1_size = blksz; + } + if ((__le32_to_cpu (inode->b.blocks.double_indir_block) << + log2_blksz) != indir1_blkno) { + status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.double_indir_block) << log2_blksz, + 0, blksz, + (char *) indir1_block); + if (status == 0) { + printf ("** ext2fs read block (indir 2 1) failed. **\n"); + return (-1); + } + indir1_blkno = + __le32_to_cpu (inode->b.blocks.double_indir_block) << log2_blksz; + } + + if (indir2_block == NULL) { + indir2_block = (uint32_t *) malloc (blksz); + if (indir2_block == NULL) { + printf ("** ext2fs read block (indir 2 2) malloc failed. **\n"); + return (-1); + } + indir2_size = blksz; + indir2_blkno = -1; + } + if (blksz != indir2_size) { + free (indir2_block); + indir2_block = NULL; + indir2_size = 0; + indir2_blkno = -1; + indir2_block = (uint32_t *) malloc (blksz); + if (indir2_block == NULL) { + printf ("** ext2fs read block (indir 2 2) malloc failed. **\n"); + return (-1); + } + indir2_size = blksz; + } + if ((__le32_to_cpu (indir1_block[rblock / perblock]) << + log2_blksz) != indir1_blkno) { + status = ext2fs_devread (__le32_to_cpu(indir1_block[rblock / perblock]) << log2_blksz, + 0, blksz, + (char *) indir2_block); + if (status == 0) { + printf ("** ext2fs read block (indir 2 2) failed. **\n"); + return (-1); + } + indir2_blkno = + __le32_to_cpu (indir1_block[rblock / perblock]) << log2_blksz; + } + blknr = __le32_to_cpu (indir2_block[rblock % perblock]); + } + /* Tripple indirect. */ + else { + printf ("** ext2fs doesn't support tripple indirect blocks. **\n"); + return (-1); + } +#ifdef DEBUG + printf ("ext2fs_read_block %08x\n", blknr); +#endif + return (blknr); +} + + +int ext2fs_read_file + (ext2fs_node_t node, int pos, unsigned int len, char *buf) { + int i; + int blockcnt; + int log2blocksize = LOG2_EXT2_BLOCK_SIZE (node->data); + int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS); + unsigned int filesize = node->inode.size; + + /* Adjust len so it we can't read past the end of the file. */ + if (len > filesize) { + len = filesize; + } + blockcnt = ((len + pos) + blocksize - 1) / blocksize; + + for (i = pos / blocksize; i < blockcnt; i++) { + int blknr; + int blockoff = pos % blocksize; + int blockend = blocksize; + + int skipfirst = 0; + + blknr = ext2fs_read_block (node, i); + if (blknr < 0) { + return (-1); + } + blknr = blknr << log2blocksize; + + /* Last block. */ + if (i == blockcnt - 1) { + blockend = (len + pos) % blocksize; + + /* The last portion is exactly blocksize. */ + if (!blockend) { + blockend = blocksize; + } + } + + /* First block. */ + if (i == pos / blocksize) { + skipfirst = blockoff; + blockend -= skipfirst; + } + + /* If the block number is 0 this block is not stored on disk but + is zero filled instead. */ + if (blknr) { + int status; + + status = ext2fs_devread (blknr, skipfirst, blockend, buf); + if (status == 0) { + return (-1); + } + } else { + memset (buf, blocksize - skipfirst, 0); + } + buf += blocksize - skipfirst; + } + return (len); +} + + +static int ext2fs_iterate_dir (ext2fs_node_t dir, char *name, ext2fs_node_t * fnode, int *ftype) +{ + unsigned int fpos = 0; + int status; + struct ext2fs_node *diro = (struct ext2fs_node *) dir; + +#ifdef DEBUG + if (name != NULL) + printf ("Iterate dir %s\n", name); +#endif /* of DEBUG */ + if (!diro->inode_read) { + status = ext2fs_read_inode (diro->data, diro->ino, + &diro->inode); + if (status == 0) { + return (0); + } + } + /* Search the file. */ + while (fpos < __le32_to_cpu (diro->inode.size)) { + struct ext2_dirent dirent; + + status = ext2fs_read_file (diro, fpos, + sizeof (struct ext2_dirent), + (char *) &dirent); + if (status < 1) { + return (0); + } + if (dirent.namelen != 0) { + char filename[dirent.namelen + 1]; + ext2fs_node_t fdiro; + int type = FILETYPE_UNKNOWN; + + status = ext2fs_read_file (diro, + fpos + sizeof (struct ext2_dirent), + dirent.namelen, filename); + if (status < 1) { + return (0); + } + fdiro = malloc (sizeof (struct ext2fs_node)); + if (!fdiro) { + return (0); + } + + fdiro->data = diro->data; + fdiro->ino = __le32_to_cpu (dirent.inode); + + filename[dirent.namelen] = '\0'; + + if (dirent.filetype != FILETYPE_UNKNOWN) { + fdiro->inode_read = 0; + + if (dirent.filetype == FILETYPE_DIRECTORY) { + type = FILETYPE_DIRECTORY; + } else if (dirent.filetype == + FILETYPE_SYMLINK) { + type = FILETYPE_SYMLINK; + } else if (dirent.filetype == FILETYPE_REG) { + type = FILETYPE_REG; + } + } else { + /* The filetype can not be read from the dirent, get it from inode */ + + status = ext2fs_read_inode (diro->data, + __le32_to_cpu(dirent.inode), + &fdiro->inode); + if (status == 0) { + free (fdiro); + return (0); + } + fdiro->inode_read = 1; + + if ((__le16_to_cpu (fdiro->inode.mode) & + FILETYPE_INO_MASK) == + FILETYPE_INO_DIRECTORY) { + type = FILETYPE_DIRECTORY; + } else if ((__le16_to_cpu (fdiro->inode.mode) + & FILETYPE_INO_MASK) == + FILETYPE_INO_SYMLINK) { + type = FILETYPE_SYMLINK; + } else if ((__le16_to_cpu (fdiro->inode.mode) + & FILETYPE_INO_MASK) == + FILETYPE_INO_REG) { + type = FILETYPE_REG; + } + } +#ifdef DEBUG + printf ("iterate >%s<\n", filename); +#endif /* of DEBUG */ + if ((name != NULL) && (fnode != NULL) + && (ftype != NULL)) { + if (strcmp (filename, name) == 0) { + *ftype = type; + *fnode = fdiro; + return (1); + } + } else { + if (fdiro->inode_read == 0) { + status = ext2fs_read_inode (diro->data, + __le32_to_cpu (dirent.inode), + &fdiro->inode); + if (status == 0) { + free (fdiro); + return (0); + } + fdiro->inode_read = 1; + } + switch (type) { + case FILETYPE_DIRECTORY: + printf (" "); + break; + case FILETYPE_SYMLINK: + printf (" "); + break; + case FILETYPE_REG: + printf (" "); + break; + default: + printf ("< ? > "); + break; + } + printf ("%10d %s\n", + __le32_to_cpu (fdiro->inode.size), + filename); + } + free (fdiro); + } + fpos += __le16_to_cpu (dirent.direntlen); + } + return (0); +} + + +static char *ext2fs_read_symlink (ext2fs_node_t node) { + char *symlink; + struct ext2fs_node *diro = node; + int status; + + if (!diro->inode_read) { + status = ext2fs_read_inode (diro->data, diro->ino, + &diro->inode); + if (status == 0) { + return (0); + } + } + symlink = malloc (__le32_to_cpu (diro->inode.size) + 1); + if (!symlink) { + return (0); + } + /* If the filesize of the symlink is bigger than + 60 the symlink is stored in a separate block, + otherwise it is stored in the inode. */ + if (__le32_to_cpu (diro->inode.size) <= 60) { + strncpy (symlink, diro->inode.b.symlink, + __le32_to_cpu (diro->inode.size)); + } else { + status = ext2fs_read_file (diro, 0, + __le32_to_cpu (diro->inode.size), + symlink); + if (status == 0) { + free (symlink); + return (0); + } + } + symlink[__le32_to_cpu (diro->inode.size)] = '\0'; + return (symlink); +} + + +int ext2fs_find_file1 + (const char *currpath, + ext2fs_node_t currroot, ext2fs_node_t * currfound, int *foundtype) { + char fpath[strlen (currpath) + 1]; + char *name = fpath; + char *next; + int status; + int type = FILETYPE_DIRECTORY; + ext2fs_node_t currnode = currroot; + ext2fs_node_t oldnode = currroot; + + strncpy (fpath, currpath, strlen (currpath) + 1); + + /* Remove all leading slashes. */ + while (*name == '/') { + name++; + } + if (!*name) { + *currfound = currnode; + return (1); + } + + for (;;) { + int found; + + /* Extract the actual part from the pathname. */ + next = strchr (name, '/'); + if (next) { + /* Remove all leading slashes. */ + while (*next == '/') { + *(next++) = '\0'; + } + } + + /* At this point it is expected that the current node is a directory, check if this is true. */ + if (type != FILETYPE_DIRECTORY) { + ext2fs_free_node (currnode, currroot); + return (0); + } + + oldnode = currnode; + + /* Iterate over the directory. */ + found = ext2fs_iterate_dir (currnode, name, &currnode, &type); + if (found == 0) { + return (0); + } + if (found == -1) { + break; + } + + /* Read in the symlink and follow it. */ + if (type == FILETYPE_SYMLINK) { + char *symlink; + + /* Test if the symlink does not loop. */ + if (++symlinknest == 8) { + ext2fs_free_node (currnode, currroot); + ext2fs_free_node (oldnode, currroot); + return (0); + } + + symlink = ext2fs_read_symlink (currnode); + ext2fs_free_node (currnode, currroot); + + if (!symlink) { + ext2fs_free_node (oldnode, currroot); + return (0); + } +#ifdef DEBUG + printf ("Got symlink >%s<\n", symlink); +#endif /* of DEBUG */ + /* The symlink is an absolute path, go back to the root inode. */ + if (symlink[0] == '/') { + ext2fs_free_node (oldnode, currroot); + oldnode = &ext2fs_root->diropen; + } + + /* Lookup the node the symlink points to. */ + status = ext2fs_find_file1 (symlink, oldnode, + &currnode, &type); + + free (symlink); + + if (status == 0) { + ext2fs_free_node (oldnode, currroot); + return (0); + } + } + + ext2fs_free_node (oldnode, currroot); + + /* Found the node! */ + if (!next || *next == '\0') { + *currfound = currnode; + *foundtype = type; + return (1); + } + name = next; + } + return (-1); +} + + +int ext2fs_find_file + (const char *path, + ext2fs_node_t rootnode, ext2fs_node_t * foundnode, int expecttype) { + int status; + int foundtype = FILETYPE_DIRECTORY; + + + symlinknest = 0; + if (!path) { + return (0); + } + + status = ext2fs_find_file1 (path, rootnode, foundnode, &foundtype); + if (status == 0) { + return (0); + } + /* Check if the node that was found was of the expected type. */ + if ((expecttype == FILETYPE_REG) && (foundtype != expecttype)) { + return (0); + } else if ((expecttype == FILETYPE_DIRECTORY) + && (foundtype != expecttype)) { + return (0); + } + return (1); +} + + +int ext2fs_ls (char *dirname) { + ext2fs_node_t dirnode; + int status; + + if (ext2fs_root == NULL) { + return (0); + } + + status = ext2fs_find_file (dirname, &ext2fs_root->diropen, &dirnode, + FILETYPE_DIRECTORY); + if (status != 1) { + printf ("** Can not find directory. **\n"); + return (1); + } + ext2fs_iterate_dir (dirnode, NULL, NULL, NULL); + ext2fs_free_node (dirnode, &ext2fs_root->diropen); + return (0); +} + + +int ext2fs_open (char *filename) { + ext2fs_node_t fdiro = NULL; + int status; + int len; + + if (ext2fs_root == NULL) { + return (-1); + } + ext2fs_file = NULL; + status = ext2fs_find_file (filename, &ext2fs_root->diropen, &fdiro, + FILETYPE_REG); + if (status == 0) { + goto fail; + } + if (!fdiro->inode_read) { + status = ext2fs_read_inode (fdiro->data, fdiro->ino, + &fdiro->inode); + if (status == 0) { + goto fail; + } + } + len = __le32_to_cpu (fdiro->inode.size); + ext2fs_file = fdiro; + return (len); + +fail: + ext2fs_free_node (fdiro, &ext2fs_root->diropen); + return (-1); +} + + +int ext2fs_close (void + ) { + if ((ext2fs_file != NULL) && (ext2fs_root != NULL)) { + ext2fs_free_node (ext2fs_file, &ext2fs_root->diropen); + ext2fs_file = NULL; + } + if (ext2fs_root != NULL) { + free (ext2fs_root); + ext2fs_root = NULL; + } + if (indir1_block != NULL) { + free (indir1_block); + indir1_block = NULL; + indir1_size = 0; + indir1_blkno = -1; + } + if (indir2_block != NULL) { + free (indir2_block); + indir2_block = NULL; + indir2_size = 0; + indir2_blkno = -1; + } + return (0); +} + + +int ext2fs_read (char *buf, unsigned len) { + int status; + + if (ext2fs_root == NULL) { + return (0); + } + + if (ext2fs_file == NULL) { + return (0); + } + + status = ext2fs_read_file (ext2fs_file, 0, len, buf); + return (status); +} + + +int ext2fs_mount (unsigned part_length) { + struct ext2_data *data; + int status; + + data = malloc (sizeof (struct ext2_data)); + if (!data) { + return (0); + } + /* Read the superblock. */ + status = ext2fs_devread (1 * 2, 0, sizeof (struct ext2_sblock), + (char *) &data->sblock); + if (status == 0) { + goto fail; + } + /* Make sure this is an ext2 filesystem. */ + if (__le16_to_cpu (data->sblock.magic) != EXT2_MAGIC) { + goto fail; + } + data->diropen.data = data; + data->diropen.ino = 2; + data->diropen.inode_read = 1; + data->inode = &data->diropen.inode; + + status = ext2fs_read_inode (data, 2, data->inode); + if (status == 0) { + goto fail; + } + + ext2fs_root = data; + + return (1); + +fail: + printf ("Failed to mount ext2 filesystem...\n"); + free (data); + ext2fs_root = NULL; + return (0); +} + +#endif /* CFG_CMD_EXT2FS */ diff --git a/fs/fat/Makefile b/fs/fat/Makefile new file mode 100644 index 0000000..e462757 --- /dev/null +++ b/fs/fat/Makefile @@ -0,0 +1,46 @@ +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TOPDIR=../../ + +include $(TOPDIR)/config.mk + +LIB = libfat.a + +AOBJS = +COBJS = fat.o file.o + +OBJS = $(AOBJS) $(COBJS) + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/fs/fat/fat.c b/fs/fat/fat.c new file mode 100644 index 0000000..a823b5a --- /dev/null +++ b/fs/fat/fat.c @@ -0,0 +1,1015 @@ +/* + * fat.c + * + * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg + * + * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 + * 2003-03-10 - kharris@nexus-tech.net - ported to uboot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FAT) + +/* + * Convert a string to lowercase. + */ +static void +downcase(char *str) +{ + while (*str != '\0') { + TOLOWER(*str); + str++; + } +} + +static block_dev_desc_t *cur_dev = NULL; +static unsigned long part_offset = 0; +static int cur_part = 1; + +#define DOS_PART_TBL_OFFSET 0x1be +#define DOS_PART_MAGIC_OFFSET 0x1fe +#define DOS_FS_TYPE_OFFSET 0x36 + +int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) +{ + startblock += part_offset; + if (cur_dev == NULL) + return -1; + if (cur_dev->block_read) { + return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr); + } + return -1; +} + + +int +fat_register_device(block_dev_desc_t *dev_desc, int part_no) +{ + unsigned char buffer[SECTOR_SIZE]; + + if (!dev_desc->block_read) + return -1; + cur_dev=dev_desc; + /* check if we have a MBR (on floppies we have only a PBR) */ + if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) { + printf ("** Can't read from device %d **\n", dev_desc->dev); + return -1; + } + if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || + buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { + /* no signature found */ + return -1; + } + if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { + /* ok, we assume we are on a PBR only */ + cur_part = 1; + part_offset=0; + } + else { +#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || defined(CONFIG_SYSTEMACE) + disk_partition_t info; + if(!get_partition_info(dev_desc, part_no, &info)) { + part_offset = info.start; + cur_part = part_no; + } + else { + printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev); + return -1; + } +#else + /* FIXME we need to determine the start block of the + * partition where the DOS FS resides. This can be done + * by using the get_partition_info routine. For this + * purpose the libpart must be included. + */ + part_offset=32; + cur_part = 1; +#endif + } + return 0; +} + + +/* + * Get the first occurence of a directory delimiter ('/' or '\') in a string. + * Return index into string if found, -1 otherwise. + */ +static int +dirdelim(char *str) +{ + char *start = str; + + while (*str != '\0') { + if (ISDIRDELIM(*str)) return str - start; + str++; + } + return -1; +} + + +/* + * Match volume_info fs_type strings. + * Return 0 on match, -1 otherwise. + */ +static int +compare_sign(char *str1, char *str2) +{ + char *end = str1+SIGNLEN; + + while (str1 != end) { + if (*str1 != *str2) { + return -1; + } + str1++; + str2++; + } + + return 0; +} + + +/* + * Extract zero terminated short name from a directory entry. + */ +static void get_name (dir_entry *dirent, char *s_name) +{ + char *ptr; + + memcpy (s_name, dirent->name, 8); + s_name[8] = '\0'; + ptr = s_name; + while (*ptr && *ptr != ' ') + ptr++; + if (dirent->ext[0] && dirent->ext[0] != ' ') { + *ptr = '.'; + ptr++; + memcpy (ptr, dirent->ext, 3); + ptr[3] = '\0'; + while (*ptr && *ptr != ' ') + ptr++; + } + *ptr = '\0'; + if (*s_name == DELETED_FLAG) + *s_name = '\0'; + else if (*s_name == aRING) + *s_name = 'ċ'; + downcase (s_name); +} + +/* + * Get the entry at index 'entry' in a FAT (12/16/32) table. + * On failure 0x00 is returned. + */ +static __u32 +get_fatent(fsdata *mydata, __u32 entry) +{ + __u32 bufnum; + __u32 offset; + __u32 ret = 0x00; + + switch (mydata->fatsize) { + case 32: + bufnum = entry / FAT32BUFSIZE; + offset = entry - bufnum * FAT32BUFSIZE; + break; + case 16: + bufnum = entry / FAT16BUFSIZE; + offset = entry - bufnum * FAT16BUFSIZE; + break; + case 12: + bufnum = entry / FAT12BUFSIZE; + offset = entry - bufnum * FAT12BUFSIZE; + break; + + default: + /* Unsupported FAT size */ + return ret; + } + + /* Read a new block of FAT entries into the cache. */ + if (bufnum != mydata->fatbufnum) { + int getsize = FATBUFSIZE/FS_BLOCK_SIZE; + __u8 *bufptr = mydata->fatbuf; + __u32 fatlength = mydata->fatlength; + __u32 startblock = bufnum * FATBUFBLOCKS; + + fatlength *= SECTOR_SIZE; /* We want it in bytes now */ + startblock += mydata->fat_sect; /* Offset from start of disk */ + + if (getsize > fatlength) getsize = fatlength; + if (disk_read(startblock, getsize, bufptr) < 0) { + FAT_DPRINT("Error reading FAT blocks\n"); + return ret; + } + mydata->fatbufnum = bufnum; + } + + /* Get the actual entry from the table */ + switch (mydata->fatsize) { + case 32: + ret = FAT2CPU32(((__u32*)mydata->fatbuf)[offset]); + break; + case 16: + ret = FAT2CPU16(((__u16*)mydata->fatbuf)[offset]); + break; + case 12: { + __u32 off16 = (offset*3)/4; + __u16 val1, val2; + + switch (offset & 0x3) { + case 0: + ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + ret &= 0xfff; + break; + case 1: + val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + val1 &= 0xf000; + val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); + val2 &= 0x00ff; + ret = (val2 << 4) | (val1 >> 12); + break; + case 2: + val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + val1 &= 0xff00; + val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); + val2 &= 0x000f; + ret = (val2 << 8) | (val1 >> 8); + break; + case 3: + ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]);; + ret = (ret & 0xfff0) >> 4; + break; + default: + break; + } + } + break; + } + FAT_DPRINT("ret: %d, offset: %d\n", ret, offset); + + return ret; +} + + +/* + * Read at most 'size' bytes from the specified cluster into 'buffer'. + * Return 0 on success, -1 otherwise. + */ +static int +get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) +{ + int idx = 0; + __u32 startsect; + + if (clustnum > 0) { + startsect = mydata->data_begin + clustnum*mydata->clust_size; + } else { + startsect = mydata->rootdir_sect; + } + + FAT_DPRINT("gc - clustnum: %d, startsect: %d\n", clustnum, startsect); + if (disk_read(startsect, size/FS_BLOCK_SIZE , buffer) < 0) { + FAT_DPRINT("Error reading data\n"); + return -1; + } + if(size % FS_BLOCK_SIZE) { + __u8 tmpbuf[FS_BLOCK_SIZE]; + idx= size/FS_BLOCK_SIZE; + if (disk_read(startsect + idx, 1, tmpbuf) < 0) { + FAT_DPRINT("Error reading data\n"); + return -1; + } + buffer += idx*FS_BLOCK_SIZE; + + memcpy(buffer, tmpbuf, size % FS_BLOCK_SIZE); + return 0; + } + + return 0; +} + + +/* + * Read at most 'maxsize' bytes from the file associated with 'dentptr' + * into 'buffer'. + * Return the number of bytes read or -1 on fatal errors. + */ +static long +get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, + unsigned long maxsize) +{ + unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0; + unsigned int bytesperclust = mydata->clust_size * SECTOR_SIZE; + __u32 curclust = START(dentptr); + __u32 endclust, newclust; + unsigned long actsize; + + FAT_DPRINT("Filesize: %ld bytes\n", filesize); + + if (maxsize > 0 && filesize > maxsize) filesize = maxsize; + + FAT_DPRINT("Reading: %ld bytes\n", filesize); + + actsize=bytesperclust; + endclust=curclust; + do { + /* search for consecutive clusters */ + while(actsize < filesize) { + newclust = get_fatent(mydata, endclust); + if((newclust -1)!=endclust) + goto getit; + if (newclust <= 0x0001 || newclust >= 0xfff0) { + FAT_DPRINT("curclust: 0x%x\n", newclust); + FAT_DPRINT("Invalid FAT entry\n"); + return gotsize; + } + endclust=newclust; + actsize+= bytesperclust; + } + /* actsize >= file size */ + actsize -= bytesperclust; + /* get remaining clusters */ + if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + /* get remaining bytes */ + gotsize += (int)actsize; + filesize -= actsize; + buffer += actsize; + actsize= filesize; + if (get_cluster(mydata, endclust, buffer, (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + gotsize+=actsize; + return gotsize; +getit: + if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + gotsize += (int)actsize; + filesize -= actsize; + buffer += actsize; + curclust = get_fatent(mydata, endclust); + if (curclust <= 0x0001 || curclust >= 0xfff0) { + FAT_DPRINT("curclust: 0x%x\n", curclust); + FAT_ERROR("Invalid FAT entry\n"); + return gotsize; + } + actsize=bytesperclust; + endclust=curclust; + } while (1); +} + + +#ifdef CONFIG_SUPPORT_VFAT +/* + * Extract the file name information from 'slotptr' into 'l_name', + * starting at l_name[*idx]. + * Return 1 if terminator (zero byte) is found, 0 otherwise. + */ +static int +slot2str(dir_slot *slotptr, char *l_name, int *idx) +{ + int j; + + for (j = 0; j <= 8; j += 2) { + l_name[*idx] = slotptr->name0_4[j]; + if (l_name[*idx] == 0x00) return 1; + (*idx)++; + } + for (j = 0; j <= 10; j += 2) { + l_name[*idx] = slotptr->name5_10[j]; + if (l_name[*idx] == 0x00) return 1; + (*idx)++; + } + for (j = 0; j <= 2; j += 2) { + l_name[*idx] = slotptr->name11_12[j]; + if (l_name[*idx] == 0x00) return 1; + (*idx)++; + } + + return 0; +} + + +/* + * Extract the full long filename starting at 'retdent' (which is really + * a slot) into 'l_name'. If successful also copy the real directory entry + * into 'retdent' + * Return 0 on success, -1 otherwise. + */ +__u8 get_vfatname_block[MAX_CLUSTSIZE]; +static int +get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, + dir_entry *retdent, char *l_name) +{ + dir_entry *realdent; + dir_slot *slotptr = (dir_slot*) retdent; + __u8 *nextclust = cluster + mydata->clust_size * SECTOR_SIZE; + __u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff; + int idx = 0; + + while ((__u8*)slotptr < nextclust) { + if (counter == 0) break; + if (((slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff) != counter) + return -1; + slotptr++; + counter--; + } + + if ((__u8*)slotptr >= nextclust) { + dir_slot *slotptr2; + + slotptr--; + curclust = get_fatent(mydata, curclust); + if (curclust <= 0x0001 || curclust >= 0xfff0) { + FAT_DPRINT("curclust: 0x%x\n", curclust); + FAT_ERROR("Invalid FAT entry\n"); + return -1; + } + if (get_cluster(mydata, curclust, get_vfatname_block, + mydata->clust_size * SECTOR_SIZE) != 0) { + FAT_DPRINT("Error: reading directory block\n"); + return -1; + } + slotptr2 = (dir_slot*) get_vfatname_block; + while (slotptr2->id > 0x01) { + slotptr2++; + } + /* Save the real directory entry */ + realdent = (dir_entry*)slotptr2 + 1; + while ((__u8*)slotptr2 >= get_vfatname_block) { + slot2str(slotptr2, l_name, &idx); + slotptr2--; + } + } else { + /* Save the real directory entry */ + realdent = (dir_entry*)slotptr; + } + + do { + slotptr--; + if (slot2str(slotptr, l_name, &idx)) break; + } while (!(slotptr->id & LAST_LONG_ENTRY_MASK)); + + l_name[idx] = '\0'; + if (*l_name == DELETED_FLAG) *l_name = '\0'; + else if (*l_name == aRING) *l_name = 'ċ'; + downcase(l_name); + + /* Return the real directory entry */ + memcpy(retdent, realdent, sizeof(dir_entry)); + + return 0; +} + + +/* Calculate short name checksum */ +static __u8 +mkcksum(const char *str) +{ + int i; + __u8 ret = 0; + + for (i = 0; i < 11; i++) { + ret = (((ret&1)<<7)|((ret&0xfe)>>1)) + str[i]; + } + + return ret; +} +#endif + + +/* + * Get the directory entry associated with 'filename' from the directory + * starting at 'startsect' + */ +__u8 get_dentfromdir_block[MAX_CLUSTSIZE]; +static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, + char *filename, dir_entry * retdent, + int dols) +{ + __u16 prevcksum = 0xffff; + __u32 curclust = START (retdent); + int files = 0, dirs = 0; + + FAT_DPRINT ("get_dentfromdir: %s\n", filename); + while (1) { + dir_entry *dentptr; + int i; + + if (get_cluster (mydata, curclust, get_dentfromdir_block, + mydata->clust_size * SECTOR_SIZE) != 0) { + FAT_DPRINT ("Error: reading directory block\n"); + return NULL; + } + dentptr = (dir_entry *) get_dentfromdir_block; + for (i = 0; i < DIRENTSPERCLUST; i++) { + char s_name[14], l_name[256]; + + l_name[0] = '\0'; + if (dentptr->name[0] == DELETED_FLAG) { + dentptr++; + continue; + } + if ((dentptr->attr & ATTR_VOLUME)) { +#ifdef CONFIG_SUPPORT_VFAT + if ((dentptr->attr & ATTR_VFAT) && + (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) { + prevcksum = ((dir_slot *) dentptr) + ->alias_checksum; + get_vfatname (mydata, curclust, get_dentfromdir_block, + dentptr, l_name); + if (dols) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirs++; + dirc = '/'; + doit = 1; + } else { + dirc = ' '; + if (l_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') { + printf (" %8ld %s%c\n", + (long) FAT2CPU32 (dentptr->size), + l_name, dirc); + } else { + printf (" %s%c\n", l_name, dirc); + } + } + dentptr++; + continue; + } + FAT_DPRINT ("vfatname: |%s|\n", l_name); + } else +#endif + { + /* Volume label or VFAT entry */ + dentptr++; + continue; + } + } + if (dentptr->name[0] == 0) { + if (dols) { + printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); + } + FAT_DPRINT ("Dentname == NULL - %d\n", i); + return NULL; + } +#ifdef CONFIG_SUPPORT_VFAT + if (dols && mkcksum (dentptr->name) == prevcksum) { + dentptr++; + continue; + } +#endif + get_name (dentptr, s_name); + if (dols) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirs++; + dirc = '/'; + doit = 1; + } else { + dirc = ' '; + if (s_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') { + printf (" %8ld %s%c\n", + (long) FAT2CPU32 (dentptr->size), s_name, + dirc); + } else { + printf (" %s%c\n", s_name, dirc); + } + } + dentptr++; + continue; + } + if (strcmp (filename, s_name) && strcmp (filename, l_name)) { + FAT_DPRINT ("Mismatch: |%s|%s|\n", s_name, l_name); + dentptr++; + continue; + } + memcpy (retdent, dentptr, sizeof (dir_entry)); + + FAT_DPRINT ("DentName: %s", s_name); + FAT_DPRINT (", start: 0x%x", START (dentptr)); + FAT_DPRINT (", size: 0x%x %s\n", + FAT2CPU32 (dentptr->size), + (dentptr->attr & ATTR_DIR) ? "(DIR)" : ""); + + return retdent; + } + curclust = get_fatent (mydata, curclust); + if (curclust <= 0x0001 || curclust >= 0xfff0) { + FAT_DPRINT ("curclust: 0x%x\n", curclust); + FAT_ERROR ("Invalid FAT entry\n"); + return NULL; + } + } + + return NULL; +} + + +/* + * Read boot sector and volume info from a FAT filesystem + */ +static int +read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) +{ + __u8 block[FS_BLOCK_SIZE]; + volume_info *vistart; + + if (disk_read(0, 1, block) < 0) { + FAT_DPRINT("Error: reading block\n"); + return -1; + } + + memcpy(bs, block, sizeof(boot_sector)); + bs->reserved = FAT2CPU16(bs->reserved); + bs->fat_length = FAT2CPU16(bs->fat_length); + bs->secs_track = FAT2CPU16(bs->secs_track); + bs->heads = FAT2CPU16(bs->heads); +#if 0 /* UNUSED */ + bs->hidden = FAT2CPU32(bs->hidden); +#endif + bs->total_sect = FAT2CPU32(bs->total_sect); + + /* FAT32 entries */ + if (bs->fat_length == 0) { + /* Assume FAT32 */ + bs->fat32_length = FAT2CPU32(bs->fat32_length); + bs->flags = FAT2CPU16(bs->flags); + bs->root_cluster = FAT2CPU32(bs->root_cluster); + bs->info_sector = FAT2CPU16(bs->info_sector); + bs->backup_boot = FAT2CPU16(bs->backup_boot); + vistart = (volume_info*) (block + sizeof(boot_sector)); + *fatsize = 32; + } else { + vistart = (volume_info*) &(bs->fat32_length); + *fatsize = 0; + } + memcpy(volinfo, vistart, sizeof(volume_info)); + + /* Terminate fs_type string. Writing past the end of vistart + is ok - it's just the buffer. */ + vistart->fs_type[8] = '\0'; + + if (*fatsize == 32) { + if (compare_sign(FAT32_SIGN, vistart->fs_type) == 0) { + return 0; + } + } else { + if (compare_sign(FAT12_SIGN, vistart->fs_type) == 0) { + *fatsize = 12; + return 0; + } + if (compare_sign(FAT16_SIGN, vistart->fs_type) == 0) { + *fatsize = 16; + return 0; + } + } + + FAT_DPRINT("Error: broken fs_type sign\n"); + return -1; +} + + +__u8 do_fat_read_block[MAX_CLUSTSIZE]; /* Block buffer */ +long +do_fat_read (const char *filename, void *buffer, unsigned long maxsize, + int dols) +{ +#if CONFIG_NIOS /* NIOS CPU cannot access big automatic arrays */ + static +#endif + char fnamecopy[2048]; + boot_sector bs; + volume_info volinfo; + fsdata datablock; + fsdata *mydata = &datablock; + dir_entry *dentptr; + __u16 prevcksum = 0xffff; + char *subname = ""; + int rootdir_size, cursect; + int idx, isdir = 0; + int files = 0, dirs = 0; + long ret = 0; + int firsttime; + + if (read_bootsectandvi (&bs, &volinfo, &mydata->fatsize)) { + FAT_DPRINT ("Error: reading boot sector\n"); + return -1; + } + if (mydata->fatsize == 32) { + mydata->fatlength = bs.fat32_length; + } else { + mydata->fatlength = bs.fat_length; + } + mydata->fat_sect = bs.reserved; + cursect = mydata->rootdir_sect + = mydata->fat_sect + mydata->fatlength * bs.fats; + mydata->clust_size = bs.cluster_size; + if (mydata->fatsize == 32) { + rootdir_size = mydata->clust_size; + mydata->data_begin = mydata->rootdir_sect /* + rootdir_size */ + - (mydata->clust_size * 2); + } else { + rootdir_size = ((bs.dir_entries[1] * (int) 256 + bs.dir_entries[0]) + * sizeof (dir_entry)) / SECTOR_SIZE; + mydata->data_begin = mydata->rootdir_sect + rootdir_size + - (mydata->clust_size * 2); + } + mydata->fatbufnum = -1; + + FAT_DPRINT ("FAT%d, fatlength: %d\n", mydata->fatsize, + mydata->fatlength); + FAT_DPRINT ("Rootdir begins at sector: %d, offset: %x, size: %d\n" + "Data begins at: %d\n", + mydata->rootdir_sect, mydata->rootdir_sect * SECTOR_SIZE, + rootdir_size, mydata->data_begin); + FAT_DPRINT ("Cluster size: %d\n", mydata->clust_size); + + /* "cwd" is always the root... */ + while (ISDIRDELIM (*filename)) + filename++; + /* Make a copy of the filename and convert it to lowercase */ + strcpy (fnamecopy, filename); + downcase (fnamecopy); + if (*fnamecopy == '\0') { + if (!dols) + return -1; + dols = LS_ROOT; + } else if ((idx = dirdelim (fnamecopy)) >= 0) { + isdir = 1; + fnamecopy[idx] = '\0'; + subname = fnamecopy + idx + 1; + /* Handle multiple delimiters */ + while (ISDIRDELIM (*subname)) + subname++; + } else if (dols) { + isdir = 1; + } + + while (1) { + int i; + + if (disk_read (cursect, mydata->clust_size, do_fat_read_block) < 0) { + FAT_DPRINT ("Error: reading rootdir block\n"); + return -1; + } + dentptr = (dir_entry *) do_fat_read_block; + for (i = 0; i < DIRENTSPERBLOCK; i++) { + char s_name[14], l_name[256]; + + l_name[0] = '\0'; + if ((dentptr->attr & ATTR_VOLUME)) { +#ifdef CONFIG_SUPPORT_VFAT + if ((dentptr->attr & ATTR_VFAT) && + (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) { + prevcksum = ((dir_slot *) dentptr)->alias_checksum; + get_vfatname (mydata, 0, do_fat_read_block, dentptr, l_name); + if (dols == LS_ROOT) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirs++; + dirc = '/'; + doit = 1; + } else { + dirc = ' '; + if (l_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') { + printf (" %8ld %s%c\n", + (long) FAT2CPU32 (dentptr->size), + l_name, dirc); + } else { + printf (" %s%c\n", l_name, dirc); + } + } + dentptr++; + continue; + } + FAT_DPRINT ("Rootvfatname: |%s|\n", l_name); + } else +#endif + { + /* Volume label or VFAT entry */ + dentptr++; + continue; + } + } else if (dentptr->name[0] == 0) { + FAT_DPRINT ("RootDentname == NULL - %d\n", i); + if (dols == LS_ROOT) { + printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); + return 0; + } + return -1; + } +#ifdef CONFIG_SUPPORT_VFAT + else if (dols == LS_ROOT + && mkcksum (dentptr->name) == prevcksum) { + dentptr++; + continue; + } +#endif + get_name (dentptr, s_name); + if (dols == LS_ROOT) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirc = '/'; + if (s_name[0] != 0) { + dirs++; + doit = 1; + } + } else { + dirc = ' '; + if (s_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') { + printf (" %8ld %s%c\n", + (long) FAT2CPU32 (dentptr->size), s_name, + dirc); + } else { + printf (" %s%c\n", s_name, dirc); + } + } + dentptr++; + continue; + } + if (strcmp (fnamecopy, s_name) && strcmp (fnamecopy, l_name)) { + FAT_DPRINT ("RootMismatch: |%s|%s|\n", s_name, l_name); + dentptr++; + continue; + } + if (isdir && !(dentptr->attr & ATTR_DIR)) + return -1; + + FAT_DPRINT ("RootName: %s", s_name); + FAT_DPRINT (", start: 0x%x", START (dentptr)); + FAT_DPRINT (", size: 0x%x %s\n", + FAT2CPU32 (dentptr->size), isdir ? "(DIR)" : ""); + + goto rootdir_done; /* We got a match */ + } + cursect++; + } + rootdir_done: + + firsttime = 1; + while (isdir) { + int startsect = mydata->data_begin + + START (dentptr) * mydata->clust_size; + dir_entry dent; + char *nextname = NULL; + + dent = *dentptr; + dentptr = &dent; + + idx = dirdelim (subname); + if (idx >= 0) { + subname[idx] = '\0'; + nextname = subname + idx + 1; + /* Handle multiple delimiters */ + while (ISDIRDELIM (*nextname)) + nextname++; + if (dols && *nextname == '\0') + firsttime = 0; + } else { + if (dols && firsttime) { + firsttime = 0; + } else { + isdir = 0; + } + } + + if (get_dentfromdir (mydata, startsect, subname, dentptr, + isdir ? 0 : dols) == NULL) { + if (dols && !isdir) + return 0; + return -1; + } + + if (idx >= 0) { + if (!(dentptr->attr & ATTR_DIR)) + return -1; + subname = nextname; + } + } + ret = get_contents (mydata, dentptr, buffer, maxsize); + FAT_DPRINT ("Size: %d, got: %ld\n", FAT2CPU32 (dentptr->size), ret); + + return ret; +} + + +int +file_fat_detectfs(void) +{ + boot_sector bs; + volume_info volinfo; + int fatsize; + char vol_label[12]; + + if(cur_dev==NULL) { + printf("No current device\n"); + return 1; + } +#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_MMC) + printf("Interface: "); + switch(cur_dev->if_type) { + case IF_TYPE_IDE : printf("IDE"); break; + case IF_TYPE_SCSI : printf("SCSI"); break; + case IF_TYPE_ATAPI : printf("ATAPI"); break; + case IF_TYPE_USB : printf("USB"); break; + case IF_TYPE_DOC : printf("DOC"); break; + case IF_TYPE_MMC : printf("MMC"); break; + default : printf("Unknown"); + } + printf("\n Device %d: ",cur_dev->dev); + dev_print(cur_dev); +#endif + if(read_bootsectandvi(&bs, &volinfo, &fatsize)) { + printf("\nNo valid FAT fs found\n"); + return 1; + } + memcpy (vol_label, volinfo.volume_label, 11); + vol_label[11] = '\0'; + volinfo.fs_type[5]='\0'; + printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label); + return 0; +} + + +int +file_fat_ls(const char *dir) +{ + return do_fat_read(dir, NULL, 0, LS_YES); +} + + +long +file_fat_read(const char *filename, void *buffer, unsigned long maxsize) +{ + printf("reading %s\n",filename); + return do_fat_read(filename, buffer, maxsize, LS_NO); +} + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/fs/fat/file.c b/fs/fat/file.c new file mode 100644 index 0000000..f999ac5 --- /dev/null +++ b/fs/fat/file.c @@ -0,0 +1,208 @@ +/* + * file.c + * + * Mini "VFS" by Marcus Sundberg + * + * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 + * 2003-03-10 - kharris@nexus-tech.net - ported to uboot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FAT) + +/* Supported filesystems */ +static const struct filesystem filesystems[] = { + { file_fat_detectfs, file_fat_ls, file_fat_read, "FAT" }, +}; +#define NUM_FILESYS (sizeof(filesystems)/sizeof(struct filesystem)) + +/* The filesystem which was last detected */ +static int current_filesystem = FSTYPE_NONE; + +/* The current working directory */ +#define CWD_LEN 511 +char file_cwd[CWD_LEN+1] = "/"; + +const char * +file_getfsname(int idx) +{ + if (idx < 0 || idx >= NUM_FILESYS) return NULL; + + return filesystems[idx].name; +} + + +static void +pathcpy(char *dest, const char *src) +{ + char *origdest = dest; + + do { + if (dest-file_cwd >= CWD_LEN) { + *dest = '\0'; + return; + } + *(dest) = *(src); + if (*src == '\0') { + if (dest-- != origdest && ISDIRDELIM(*dest)) { + *dest = '\0'; + } + return; + } + ++dest; + if (ISDIRDELIM(*src)) { + while (ISDIRDELIM(*src)) src++; + } else { + src++; + } + } while (1); +} + + +int +file_cd(const char *path) +{ + if (ISDIRDELIM(*path)) { + while (ISDIRDELIM(*path)) path++; + strncpy(file_cwd+1, path, CWD_LEN-1); + } else { + const char *origpath = path; + char *tmpstr = file_cwd; + int back = 0; + + while (*tmpstr != '\0') tmpstr++; + do { + tmpstr--; + } while (ISDIRDELIM(*tmpstr)); + + while (*path == '.') { + path++; + while (*path == '.') { + path++; + back++; + } + if (*path != '\0' && !ISDIRDELIM(*path)) { + path = origpath; + back = 0; + break; + } + while (ISDIRDELIM(*path)) path++; + origpath = path; + } + + while (back--) { + /* Strip off path component */ + while (!ISDIRDELIM(*tmpstr)) { + tmpstr--; + } + if (tmpstr == file_cwd) { + /* Incremented again right after the loop. */ + tmpstr--; + break; + } + /* Skip delimiters */ + while (ISDIRDELIM(*tmpstr)) tmpstr--; + } + tmpstr++; + if (*path == '\0') { + if (tmpstr == file_cwd) { + *tmpstr = '/'; + tmpstr++; + } + *tmpstr = '\0'; + return 0; + } + *tmpstr = '/'; + pathcpy(tmpstr+1, path); + } + + return 0; +} + + +int +file_detectfs(void) +{ + int i; + + current_filesystem = FSTYPE_NONE; + + for (i = 0; i < NUM_FILESYS; i++) { + if (filesystems[i].detect() == 0) { + strcpy(file_cwd, "/"); + current_filesystem = i; + break; + } + } + + return current_filesystem; +} + + +int +file_ls(const char *dir) +{ + char fullpath[1024]; + const char *arg; + + if (current_filesystem == FSTYPE_NONE) { + printf("Can't list files without a filesystem!\n"); + return -1; + } + + if (ISDIRDELIM(*dir)) { + arg = dir; + } else { + sprintf(fullpath, "%s/%s", file_cwd, dir); + arg = fullpath; + } + return filesystems[current_filesystem].ls(arg); +} + + +long +file_read(const char *filename, void *buffer, unsigned long maxsize) +{ + char fullpath[1024]; + const char *arg; + + if (current_filesystem == FSTYPE_NONE) { + printf("Can't load file without a filesystem!\n"); + return -1; + } + + if (ISDIRDELIM(*filename)) { + arg = filename; + } else { + sprintf(fullpath, "%s/%s", file_cwd, filename); + arg = fullpath; + } + + return filesystems[current_filesystem].read(arg, buffer, maxsize); +} + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/fs/fdos/Makefile b/fs/fdos/Makefile new file mode 100644 index 0000000..c25e744 --- /dev/null +++ b/fs/fdos/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2002 +# Stäubli Faverges - +# Pierre AUBERT p.aubert@staubli.com +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libfdos.a + +AOBJS = +COBJS = fat.o vfat.o dev.o fdos.o fs.o subdir.o +OBJS = $(AOBJS) $(COBJS) + +#CPPFLAGS += + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/fs/fdos/dev.c b/fs/fdos/dev.c new file mode 100644 index 0000000..5dea5cd --- /dev/null +++ b/fs/fdos/dev.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include "dos.h" +#include "fdos.h" + +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) + +#define NB_HEADS 2 +#define NB_TRACKS 80 +#define NB_SECTORS 18 + + +static int lastwhere; + +/*----------------------------------------------------------------------------- + * dev_open -- + *----------------------------------------------------------------------------- + */ +int dev_open (void) +{ + lastwhere = 0; + return (0); +} + +/*----------------------------------------------------------------------------- + * dev_read -- len and where are sectors number + *----------------------------------------------------------------------------- + */ +int dev_read (void *buffer, int where, int len) +{ + PRINTF ("dev_read (len = %d, where = %d)\n", len, where); + + /* Si on ne desire pas lire a la position courante, il faut un seek */ + if (where != lastwhere) { + if (!fdc_fdos_seek (where)) { + PRINTF ("seek error in dev_read"); + lastwhere = -1; + return (-1); + } + } + + if (!fdc_fdos_read (buffer, len)) { + PRINTF ("read error\n"); + lastwhere = -1; + return (-1); + } + lastwhere = where + len; + return (0); +} +/*----------------------------------------------------------------------------- + * check_dev -- verify the diskette format + *----------------------------------------------------------------------------- + */ +int check_dev (BootSector_t *boot, Fs_t *fs) +{ + unsigned int heads, sectors, tracks; + int BootP, Infp0, InfpX, InfTm; + int sect_per_track; + + /* Display Boot header */ + PRINTF ("Jump to boot code 0x%02x 0x%02x 0x%02x\n", + boot -> jump [0], boot -> jump [1], boot -> jump[2]); + PRINTF ("OEM name & version '%*.*s'\n", + BANNER_LG, BANNER_LG, boot -> banner ); + PRINTF ("Bytes per sector hopefully 512 %d\n", + __le16_to_cpu (boot -> secsiz)); + PRINTF ("Cluster size in sectors %d\n", + boot -> clsiz); + PRINTF ("Number of reserved (boot) sectors %d\n", + __le16_to_cpu (boot -> nrsvsect)); + PRINTF ("Number of FAT tables hopefully 2 %d\n", + boot -> nfat); + PRINTF ("Number of directory slots %d\n", + __le16_to_cpu (boot -> dirents)); + PRINTF ("Total sectors on disk %d\n", + __le16_to_cpu (boot -> psect)); + PRINTF ("Media descriptor=first byte of FAT %d\n", + boot -> descr); + PRINTF ("Sectors in FAT %d\n", + __le16_to_cpu (boot -> fatlen)); + PRINTF ("Sectors/track %d\n", + __le16_to_cpu (boot -> nsect)); + PRINTF ("Heads %d\n", + __le16_to_cpu (boot -> nheads)); + PRINTF ("number of hidden sectors %d\n", + __le32_to_cpu (boot -> nhs)); + PRINTF ("big total sectors %d\n", + __le32_to_cpu (boot -> bigsect)); + PRINTF ("physical drive ? %d\n", + boot -> physdrive); + PRINTF ("reserved %d\n", + boot -> reserved); + PRINTF ("dos > 4.0 diskette %d\n", + boot -> dos4); + PRINTF ("serial number %d\n", + __le32_to_cpu (boot -> serial)); + PRINTF ("disk label %*.*s\n", + LABEL_LG, LABEL_LG, boot -> label); + PRINTF ("FAT type %8.8s\n", + boot -> fat_type); + PRINTF ("reserved by 2M %d\n", + boot -> res_2m); + PRINTF ("2M checksum (not used) %d\n", + boot -> CheckSum); + PRINTF ("2MF format version %d\n", + boot -> fmt_2mf); + PRINTF ("1 if write track after format %d\n", + boot -> wt); + PRINTF ("data transfer rate on track 0 %d\n", + boot -> rate_0); + PRINTF ("data transfer rate on track<>0 %d\n", + boot -> rate_any); + PRINTF ("offset to boot program %d\n", + __le16_to_cpu (boot -> BootP)); + PRINTF ("T1: information for track 0 %d\n", + __le16_to_cpu (boot -> Infp0)); + PRINTF ("T2: information for track<>0 %d\n", + __le16_to_cpu (boot -> InfpX)); + PRINTF ("T3: track sectors size table %d\n", + __le16_to_cpu (boot -> InfTm)); + PRINTF ("Format date 0x%04x\n", + __le16_to_cpu (boot -> DateF)); + PRINTF ("Format time 0x%04x\n", + __le16_to_cpu (boot -> TimeF)); + + + /* information is extracted from boot sector */ + heads = __le16_to_cpu (boot -> nheads); + sectors = __le16_to_cpu (boot -> nsect); + fs -> tot_sectors = __le32_to_cpu (boot -> bigsect); + if (__le16_to_cpu (boot -> psect) != 0) { + fs -> tot_sectors = __le16_to_cpu (boot -> psect); + } + + sect_per_track = heads * sectors; + tracks = (fs -> tot_sectors + sect_per_track - 1) / sect_per_track; + + BootP = __le16_to_cpu (boot -> BootP); + Infp0 = __le16_to_cpu (boot -> Infp0); + InfpX = __le16_to_cpu (boot -> InfpX); + InfTm = __le16_to_cpu (boot -> InfTm); + + if (boot -> dos4 == EXTENDED_BOOT && + strncmp( boot->banner,"2M", 2 ) == 0 && + BootP < SZ_STD_SECTOR && + Infp0 < SZ_STD_SECTOR && + InfpX < SZ_STD_SECTOR && + InfTm < SZ_STD_SECTOR && + BootP >= InfTm + 2 && + InfTm >= InfpX && + InfpX >= Infp0 && + Infp0 >= 76 ) { + + return (-1); + } + + if (heads != NB_HEADS || + tracks != NB_TRACKS || + sectors != NB_SECTORS || + __le16_to_cpu (boot -> secsiz) != SZ_STD_SECTOR || + fs -> tot_sectors == 0 || + (fs -> tot_sectors % sectors) != 0) { + return (-1); + } + + return (0); +} + + +#endif diff --git a/fs/fdos/dos.h b/fs/fdos/dos.h new file mode 100644 index 0000000..7b27b01 --- /dev/null +++ b/fs/fdos/dos.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DOS_H_ +#define _DOS_H_ + +/* Definitions for Dos diskettes */ + +/* General definitions */ +#define SZ_STD_SECTOR 512 /* Standard sector size */ +#define MDIR_SIZE 32 /* Direntry size */ +#define FAT_BITS 12 /* Diskette use 12 bits fat */ + +#define MAX_PATH 128 /* Max size of the MSDOS PATH */ +#define MAX_DIR_SECS 64 /* Taille max d'un repertoire (en */ + /* secteurs) */ +/* Misc. definitions */ +#define DELMARK '\xe5' +#define EXTENDED_BOOT (0x29) +#define MEDIA_STD (0xf0) +#define JUMP_0_1 (0xe9) +#define JUMP_0_2 (0xeb) + +/* Boot size is 256 bytes, but we need to read almost a sector, then + assume bootsize is 512 */ +#define BOOTSIZE 512 + +/* Fat definitions for 12 bits fat */ +#define FAT12_MAX_NB 4086 +#define FAT12_LAST 0x0ff6 +#define FAT12_END 0x0fff + +/* file attributes */ +#define ATTR_READONLY 0x01 +#define ATTR_HIDDEN 0x02 +#define ATTR_SYSTEM 0x04 +#define ATTR_VOLUME 0x08 +#define ATTR_DIRECTORY 0x10 +#define ATTR_ARCHIVE 0x20 +#define ATTR_VSE 0x0f + +/* Name format */ +#define EXTCASE 0x10 +#define BASECASE 0x8 + +/* Definition of the boot sector */ +#define BANNER_LG 8 +#define LABEL_LG 11 + +typedef struct bootsector +{ + unsigned char jump [3]; /* 0 Jump to boot code */ + char banner [BANNER_LG]; /* 3 OEM name & version */ + unsigned short secsiz; /* 11 Bytes per sector hopefully 512 */ + unsigned char clsiz; /* 13 Cluster size in sectors */ + unsigned short nrsvsect; /* 14 Number of reserved (boot) sectors */ + unsigned char nfat; /* 16 Number of FAT tables hopefully 2 */ + unsigned short dirents; /* 17 Number of directory slots */ + unsigned short psect; /* 19 Total sectors on disk */ + unsigned char descr; /* 21 Media descriptor=first byte of FAT */ + unsigned short fatlen; /* 22 Sectors in FAT */ + unsigned short nsect; /* 24 Sectors/track */ + unsigned short nheads; /* 26 Heads */ + unsigned int nhs; /* 28 number of hidden sectors */ + unsigned int bigsect; /* 32 big total sectors */ + unsigned char physdrive; /* 36 physical drive ? */ + unsigned char reserved; /* 37 reserved */ + unsigned char dos4; /* 38 dos > 4.0 diskette */ + unsigned int serial; /* 39 serial number */ + char label [LABEL_LG]; /* 43 disk label */ + char fat_type [8]; /* 54 FAT type */ + unsigned char res_2m; /* 62 reserved by 2M */ + unsigned char CheckSum; /* 63 2M checksum (not used) */ + unsigned char fmt_2mf; /* 64 2MF format version */ + unsigned char wt; /* 65 1 if write track after format */ + unsigned char rate_0; /* 66 data transfer rate on track 0 */ + unsigned char rate_any; /* 67 data transfer rate on track<>0 */ + unsigned short BootP; /* 68 offset to boot program */ + unsigned short Infp0; /* 70 T1: information for track 0 */ + unsigned short InfpX; /* 72 T2: information for track<>0 */ + unsigned short InfTm; /* 74 T3: track sectors size table */ + unsigned short DateF; /* 76 Format date */ + unsigned short TimeF; /* 78 Format time */ + unsigned char junk [BOOTSIZE - 80]; /* 80 remaining data */ +} __attribute__ ((packed)) BootSector_t; + +/* Structure d'une entree de repertoire */ +typedef struct directory { + char name [8]; /* file name */ + char ext [3]; /* file extension */ + unsigned char attr; /* attribute byte */ + unsigned char Case; /* case of short filename */ + unsigned char reserved [9]; /* ?? */ + unsigned char time [2]; /* time stamp */ + unsigned char date [2]; /* date stamp */ + unsigned short start; /* starting cluster number */ + unsigned int size; /* size of the file */ +} __attribute__ ((packed)) Directory_t; + + +#define MAX_VFAT_SUBENTRIES 20 +#define VSE_NAMELEN 13 + +#define VSE1SIZE 5 +#define VSE2SIZE 6 +#define VSE3SIZE 2 + +#define VBUFSIZE ((MAX_VFAT_SUBENTRIES * VSE_NAMELEN) + 1) + +#define MAX_VNAMELEN (255) + +#define VSE_PRESENT 0x01 +#define VSE_LAST 0x40 +#define VSE_MASK 0x1f + +/* Flag used by vfat_lookup */ +#define DO_OPEN 1 +#define ACCEPT_PLAIN 0x20 +#define ACCEPT_DIR 0x10 +#define ACCEPT_LABEL 0x08 +#define SINGLE 2 +#define MATCH_ANY 0x40 + +struct vfat_subentry { + unsigned char id; /* VSE_LAST pour la fin, VSE_MASK */ + /* pour un VSE */ + char text1 [VSE1SIZE * 2]; /* Caracteres encodes sur 16 bits */ + unsigned char attribute; /* 0x0f pour les VFAT */ + unsigned char hash1; /* toujours 0 */ + unsigned char sum; /* Checksum du nom court */ + char text2 [VSE2SIZE * 2]; /* Caracteres encodes sur 16 bits */ + unsigned char sector_l; /* 0 pour les VFAT */ + unsigned char sector_u; /* 0 pour les VFAT */ + char text3 [VSE3SIZE * 2]; /* Caracteres encodes sur 16 bits */ +} __attribute__ ((packed)) ; + +struct vfat_state { + char name [VBUFSIZE]; + int status; /* is now a bit map of 32 bits */ + int subentries; + unsigned char sum; /* no need to remember the sum for each */ + /* entry, it is the same anyways */ +} __attribute__ ((packed)) ; + +/* Conversion macros */ +#define DOS_YEAR(dir) (((dir)->date[1] >> 1) + 1980) +#define DOS_MONTH(dir) (((((dir)->date[1]&0x1) << 3) + ((dir)->date[0] >> 5))) +#define DOS_DAY(dir) ((dir)->date[0] & 0x1f) +#define DOS_HOUR(dir) ((dir)->time[1] >> 3) +#define DOS_MINUTE(dir) (((((dir)->time[1]&0x7) << 3) + ((dir)->time[0] >> 5))) +#define DOS_SEC(dir) (((dir)->time[0] & 0x1f) * 2) + + +#endif diff --git a/fs/fdos/fat.c b/fs/fdos/fat.c new file mode 100644 index 0000000..2ef2371 --- /dev/null +++ b/fs/fdos/fat.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) + +#include "dos.h" +#include "fdos.h" + + +/*----------------------------------------------------------------------------- + * fat_decode -- + *----------------------------------------------------------------------------- + */ +unsigned int fat_decode (Fs_t *fs, unsigned int num) +{ + unsigned int start = num * 3 / 2; + unsigned char *address = fs -> fat_buf + start; + + if (num < 2 || start + 1 > (fs -> fat_len * SZ_STD_SECTOR)) + return 1; + + if (num & 1) + return ((address [1] & 0xff) << 4) | ((address [0] & 0xf0 ) >> 4); + else + return ((address [1] & 0xf) << 8) | (address [0] & 0xff ); +} +/*----------------------------------------------------------------------------- + * check_fat -- + *----------------------------------------------------------------------------- + */ +static int check_fat (Fs_t *fs) +{ + int i, f; + + /* Cluster verification */ + for (i = 3 ; i < fs -> num_clus; i++){ + f = fat_decode (fs, i); + if (f < FAT12_LAST && f > fs -> num_clus){ + /* Wrong cluster number detected */ + return (-1); + } + } + return (0); +} +/*----------------------------------------------------------------------------- + * read_one_fat -- + *----------------------------------------------------------------------------- + */ +static int read_one_fat (BootSector_t *boot, Fs_t *fs, int nfat) +{ + if (dev_read (fs -> fat_buf, + (fs -> fat_start + nfat * fs -> fat_len), + fs -> fat_len) < 0) { + return (-1); + } + + if (fs -> fat_buf [0] || fs -> fat_buf [1] || fs -> fat_buf [2]) { + if ((fs -> fat_buf [0] != boot -> descr && + (fs -> fat_buf [0] != 0xf9 || boot -> descr != MEDIA_STD)) || + fs -> fat_buf [0] < MEDIA_STD){ + /* Unknown Media */ + return (-1); + } + if (fs -> fat_buf [1] != 0xff || fs -> fat_buf [2] != 0xff){ + /* FAT doesn't start with good values */ + return (-1); + } + } + + if (fs -> num_clus >= FAT12_MAX_NB) { + /* Too much clusters */ + return (-1); + } + + return check_fat (fs); +} +/*----------------------------------------------------------------------------- + * read_fat -- + *----------------------------------------------------------------------------- + */ +int read_fat (BootSector_t *boot, Fs_t *fs) +{ + unsigned int buflen; + int i; + + /* Allocate Fat Buffer */ + buflen = fs -> fat_len * SZ_STD_SECTOR; + if (fs -> fat_buf) { + free (fs -> fat_buf); + } + + if ((fs -> fat_buf = malloc (buflen)) == NULL) { + return (-1); + } + + /* Try to read each Fat */ + for (i = 0; i< fs -> nb_fat; i++){ + if (read_one_fat (boot, fs, i) == 0) { + /* Fat is OK */ + fs -> num_fat = i; + break; + } + } + + if (i == fs -> nb_fat){ + return (-1); + } + + if (fs -> fat_len > (((fs -> num_clus + 2) * + (FAT_BITS / 4) -1 ) / 2 / + SZ_STD_SECTOR + 1)) { + return (-1); + } + return (0); +} + +#endif diff --git a/fs/fdos/fdos.c b/fs/fdos/fdos.c new file mode 100644 index 0000000..a29f43d --- /dev/null +++ b/fs/fdos/fdos.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) +#include +#include "dos.h" +#include "fdos.h" + + +const char *month [] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"}; + +Fs_t fs; +File_t file; + +/*----------------------------------------------------------------------------- + * dos_open -- + *----------------------------------------------------------------------------- + */ +int dos_open(char *name) +{ + int lg; + int entry; + char *fname; + + /* We need to suppress the " char around the name */ + if (name [0] == '"') { + name ++; + } + lg = strlen (name); + if (name [lg - 1] == '"') { + name [lg - 1] = '\0'; + } + + /* Open file system */ + if (fs_init (&fs) < 0) { + return -1; + } + + /* Init the file descriptor */ + file.name = name; + file.fs = &fs; + + /* find the subdirectory containing the file */ + if (open_subdir (&file) < 0) { + return (-1); + } + + fname = basename (name); + + /* if we try to open root directory */ + if (*fname == '\0') { + file.file = file.subdir; + return (0); + } + + /* find the file in the subdir */ + entry = 0; + if (vfat_lookup (&file.subdir, + file.fs, + &file.file.dir, + &entry, + 0, + fname, + ACCEPT_DIR | ACCEPT_PLAIN | SINGLE | DO_OPEN, + 0, + &file.file) != 0) { + /* File not found */ + printf ("File not found\n"); + return (-1); + } + + return 0; +} + +/*----------------------------------------------------------------------------- + * dos_read -- + *----------------------------------------------------------------------------- + */ +int dos_read (ulong addr) +{ + int read = 0, nb; + + /* Try to boot a directory ? */ + if (file.file.dir.attr & (ATTR_DIRECTORY | ATTR_VOLUME)) { + printf ("Unable to boot %s !!\n", file.name); + return (-1); + } + while (read < file.file.FileSize) { + PRINTF ("read_file (%ld)\n", (file.file.FileSize - read)); + nb = read_file (&fs, + &file.file, + (char *)addr + read, + read, + (file.file.FileSize - read)); + PRINTF ("read_file -> %d\n", nb); + if (nb < 0) { + printf ("read error\n"); + return (-1); + } + read += nb; + } + return (read); +} +/*----------------------------------------------------------------------------- + * dos_dir -- + *----------------------------------------------------------------------------- + */ +int dos_dir (void) +{ + int entry; + Directory_t dir; + char *name; + + + if ((file.file.dir.attr & ATTR_DIRECTORY) == 0) { + printf ("%s: not a directory !!\n", file.name); + return (1); + } + entry = 0; + if ((name = malloc (MAX_VNAMELEN + 1)) == NULL) { + PRINTF ("Allcation error\n"); + return (1); + } + + while (vfat_lookup (&file.file, + file.fs, + &dir, + &entry, + 0, + NULL, + ACCEPT_DIR | ACCEPT_PLAIN | MATCH_ANY, + name, + NULL) == 0) { + /* Display file info */ + printf ("%3.3s %9d %s %02d %04d %02d:%02d:%02d %s\n", + (dir.attr & ATTR_DIRECTORY) ? "dir" : " ", + __le32_to_cpu (dir.size), + month [DOS_MONTH (&dir) - 1], + DOS_DAY (&dir), + DOS_YEAR (&dir), + DOS_HOUR (&dir), + DOS_MINUTE (&dir), + DOS_SEC (&dir), + name); + + } + free (name); + return (0); +} + +#endif diff --git a/fs/fdos/fdos.h b/fs/fdos/fdos.h new file mode 100644 index 0000000..e28c22f --- /dev/null +++ b/fs/fdos/fdos.h @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FDOS_H_ +#define _FDOS_H_ + + +#undef FDOS_DEBUG + +#ifdef FDOS_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* Data structure describing media */ +typedef struct fs +{ + unsigned long tot_sectors; + + int cluster_size; + int num_clus; + + int fat_start; + int fat_len; + int nb_fat; + int num_fat; + + int dir_start; + int dir_len; + + unsigned char *fat_buf; + +} Fs_t; + +/* Data structure describing one file system slot */ +typedef struct slot { + int (*map) (struct fs *fs, + struct slot *file, + int where, + int *len); + unsigned long FileSize; + + unsigned short int FirstAbsCluNr; + unsigned short int PreviousAbsCluNr; + unsigned short int PreviousRelCluNr; + + Directory_t dir; +} Slot_t; + +typedef struct file { + char *name; + int Case; + Fs_t *fs; + Slot_t subdir; + Slot_t file; +} File_t; + + +/* dev.c */ +int dev_read (void *buffer, int where, int len); +int dev_open (void); +int check_dev (BootSector_t *boot, Fs_t *fs); + +/* fat.c */ +unsigned int fat_decode (Fs_t *fs, unsigned int num); +int read_fat (BootSector_t *boot, Fs_t *fs); + +/* vfat.c */ +int vfat_lookup (Slot_t *dir, + Fs_t *fs, + Directory_t *dirent, + int *entry, + int *vfat_start, + char *filename, + int flags, + char *outname, + Slot_t *file); + +/* subdir.c */ +char *basename (char *name); +int open_subdir (File_t *desc); +int open_file (Slot_t *file, Directory_t *dir); +int read_file (Fs_t *fs, + Slot_t *file, + char *buf, + int where, + int len); +void init_subdir (void); + +/* fs.c */ +int fs_init (Fs_t *fs); + + +#endif diff --git a/fs/fdos/fs.c b/fs/fdos/fs.c new file mode 100644 index 0000000..3b9d09e --- /dev/null +++ b/fs/fdos/fs.c @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) + +#include "dos.h" +#include "fdos.h" + + +/*----------------------------------------------------------------------------- + * fill_fs -- Read info on file system + *----------------------------------------------------------------------------- + */ +static int fill_fs (BootSector_t *boot, Fs_t *fs) +{ + + fs -> fat_start = __le16_to_cpu (boot -> nrsvsect); + fs -> fat_len = __le16_to_cpu (boot -> fatlen); + fs -> nb_fat = boot -> nfat; + + fs -> dir_start = fs -> fat_start + fs -> nb_fat * fs -> fat_len; + fs -> dir_len = __le16_to_cpu (boot -> dirents) * MDIR_SIZE / SZ_STD_SECTOR; + fs -> cluster_size = boot -> clsiz; + fs -> num_clus = (fs -> tot_sectors - fs -> dir_start - fs -> dir_len) / fs -> cluster_size; + + return (0); +} + +/*----------------------------------------------------------------------------- + * fs_init -- + *----------------------------------------------------------------------------- + */ +int fs_init (Fs_t *fs) +{ + BootSector_t *boot; + + /* Initialize physical device */ + if (dev_open () < 0) { + PRINTF ("Unable to initialize the fdc\n"); + return (-1); + } + init_subdir (); + + /* Allocate space for read the boot sector */ + if ((boot = (BootSector_t *)malloc (sizeof (BootSector_t))) == NULL) { + PRINTF ("Unable to allocate space for boot sector\n"); + return (-1); + } + + /* read boot sector */ + if (dev_read (boot, 0, 1)){ + PRINTF ("Error during boot sector read\n"); + free (boot); + return (-1); + } + + /* we verify it'a a DOS diskette */ + if (boot -> jump [0] != JUMP_0_1 && boot -> jump [0] != JUMP_0_2) { + PRINTF ("Not a DOS diskette\n"); + free (boot); + return (-1); + } + + if (boot -> descr < MEDIA_STD) { + /* We handle only recent medias (type F0) */ + PRINTF ("unrecognized diskette type\n"); + free (boot); + return (-1); + } + + if (check_dev (boot, fs) < 0) { + PRINTF ("Bad diskette\n"); + free (boot); + return (-1); + } + + if (fill_fs (boot, fs) < 0) { + free (boot); + + return (-1); + } + + /* Read FAT */ + if (read_fat (boot, fs) < 0) { + free (boot); + return (-1); + } + + free (boot); + return (0); +} + +#endif diff --git a/fs/fdos/subdir.c b/fs/fdos/subdir.c new file mode 100644 index 0000000..97b2504 --- /dev/null +++ b/fs/fdos/subdir.c @@ -0,0 +1,348 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) + +#include "dos.h" +#include "fdos.h" + +static int cache_sect; +static unsigned char cache [SZ_STD_SECTOR]; + + +#define min(x,y) ((x)<(y)?(x):(y)) + +static int descend (Slot_t *parent, + Fs_t *fs, + char *path); + +/*----------------------------------------------------------------------------- + * init_subdir -- + *----------------------------------------------------------------------------- + */ +void init_subdir (void) +{ + cache_sect = -1; +} +/*----------------------------------------------------------------------------- + * basename -- + *----------------------------------------------------------------------------- + */ +char *basename (char *name) +{ + register char *cptr; + + if (!name || !*name) { + return (""); + } + + for (cptr= name; *cptr++; ); + while (--cptr >= name) { + if (*cptr == '/') { + return (cptr + 1); + } + } + return(name); +} +/*----------------------------------------------------------------------------- + * root_map -- + *----------------------------------------------------------------------------- + */ +static int root_map (Fs_t *fs, Slot_t *file, int where, int *len) +{ + *len = min (*len, fs -> dir_len * SZ_STD_SECTOR - where); + if (*len < 0 ) { + *len = 0; + return (-1); + } + return fs -> dir_start * SZ_STD_SECTOR + where; +} +/*----------------------------------------------------------------------------- + * normal_map -- + *----------------------------------------------------------------------------- + */ +static int normal_map (Fs_t *fs, Slot_t *file, int where, int *len) +{ + int offset; + int NrClu; + unsigned short RelCluNr; + unsigned short CurCluNr; + unsigned short NewCluNr; + unsigned short AbsCluNr; + int clus_size; + + clus_size = fs -> cluster_size * SZ_STD_SECTOR; + offset = where % clus_size; + + *len = min (*len, file -> FileSize - where); + + if (*len < 0 ) { + *len = 0; + return (0); + } + + if (file -> FirstAbsCluNr < 2){ + *len = 0; + return (0); + } + + RelCluNr = where / clus_size; + + if (RelCluNr >= file -> PreviousRelCluNr){ + CurCluNr = file -> PreviousRelCluNr; + AbsCluNr = file -> PreviousAbsCluNr; + } else { + CurCluNr = 0; + AbsCluNr = file -> FirstAbsCluNr; + } + + + NrClu = (offset + *len - 1) / clus_size; + while (CurCluNr <= RelCluNr + NrClu) { + if (CurCluNr == RelCluNr){ + /* we have reached the beginning of our zone. Save + * coordinates */ + file -> PreviousRelCluNr = RelCluNr; + file -> PreviousAbsCluNr = AbsCluNr; + } + NewCluNr = fat_decode (fs, AbsCluNr); + if (NewCluNr == 1 || NewCluNr == 0) { + PRINTF("Fat problem while decoding %d %x\n", + AbsCluNr, NewCluNr); + return (-1); + } + if (CurCluNr == RelCluNr + NrClu) { + break; + } + + if (CurCluNr < RelCluNr && NewCluNr == FAT12_END) { + *len = 0; + return 0; + } + + if (CurCluNr >= RelCluNr && NewCluNr != AbsCluNr + 1) + break; + CurCluNr++; + AbsCluNr = NewCluNr; + } + + *len = min (*len, (1 + CurCluNr - RelCluNr) * clus_size - offset); + + return (((file -> PreviousAbsCluNr - 2) * fs -> cluster_size + + fs -> dir_start + fs -> dir_len) * + SZ_STD_SECTOR + offset); +} +/*----------------------------------------------------------------------------- + * open_subdir -- open the subdir containing the file + *----------------------------------------------------------------------------- + */ +int open_subdir (File_t *desc) +{ + char *pathname; + char *tmp, *s, *path; + char terminator; + + if ((pathname = (char *)malloc (MAX_PATH)) == NULL) { + return (-1); + } + + strcpy (pathname, desc -> name); + + /* Suppress file name */ + tmp = basename (pathname); + *tmp = '\0'; + + /* root directory init */ + desc -> subdir.FirstAbsCluNr = 0; + desc -> subdir.FileSize = -1; + desc -> subdir.map = root_map; + desc -> subdir.dir.attr = ATTR_DIRECTORY; + + tmp = pathname; + for (s = tmp; ; ++s) { + if (*s == '/' || *s == '\0') { + path = tmp; + terminator = *s; + *s = '\0'; + if (s != tmp && strcmp (path,".")) { + if (descend (&desc -> subdir, desc -> fs, path) < 0) { + free (pathname); + return (-1); + } + } + if (terminator == 0) { + break; + } + tmp = s + 1; + } + } + free (pathname); + return (0); +} +/*----------------------------------------------------------------------------- + * descend -- + *----------------------------------------------------------------------------- + */ +static int descend (Slot_t *parent, + Fs_t *fs, + char *path) +{ + int entry; + Slot_t SubDir; + + if(path[0] == '\0' || strcmp (path, ".") == 0) { + return (0); + } + + + entry = 0; + if (vfat_lookup (parent, + fs, + &(SubDir.dir), + &entry, + 0, + path, + ACCEPT_DIR | SINGLE | DO_OPEN, + 0, + &SubDir) == 0) { + *parent = SubDir; + return (0); + } + + if (strcmp(path, "..") == 0) { + parent -> FileSize = -1; + parent -> FirstAbsCluNr = 0; + parent -> map = root_map; + return (0); + } + return (-1); +} +/*----------------------------------------------------------------------------- + * open_file -- + *----------------------------------------------------------------------------- + */ +int open_file (Slot_t *file, Directory_t *dir) +{ + int first; + unsigned long size; + + first = __le16_to_cpu (dir -> start); + + if(first == 0 && + (dir -> attr & ATTR_DIRECTORY) != 0) { + file -> FirstAbsCluNr = 0; + file -> FileSize = -1; + file -> map = root_map; + return (0); + } + + if ((dir -> attr & ATTR_DIRECTORY) != 0) { + size = (1UL << 31) - 1; + } + else { + size = __le32_to_cpu (dir -> size); + } + + file -> map = normal_map; + file -> FirstAbsCluNr = first; + file -> PreviousRelCluNr = 0xffff; + file -> FileSize = size; + return (0); +} +/*----------------------------------------------------------------------------- + * read_file -- + *----------------------------------------------------------------------------- + */ +int read_file (Fs_t *fs, + Slot_t *file, + char *buf, + int where, + int len) +{ + int pos; + int read, nb, sect, offset; + + pos = file -> map (fs, file, where, &len); + if (pos < 0) { + return -1; + } + if (len == 0) { + return (0); + } + + /* Compute sector number */ + sect = pos / SZ_STD_SECTOR; + offset = pos % SZ_STD_SECTOR; + read = 0; + + if (offset) { + /* Read doesn't start at the sector beginning. We need to use our */ + /* cache */ + if (sect != cache_sect) { + if (dev_read (cache, sect, 1) < 0) { + return (-1); + } + cache_sect = sect; + } + nb = min (len, SZ_STD_SECTOR - offset); + + memcpy (buf, cache + offset, nb); + read += nb; + len -= nb; + sect += 1; + } + + if (len > SZ_STD_SECTOR) { + nb = (len - 1) / SZ_STD_SECTOR; + if (dev_read (buf + read, sect, nb) < 0) { + return ((read) ? read : -1); + } + /* update sector position */ + sect += nb; + + /* Update byte position */ + nb *= SZ_STD_SECTOR; + read += nb; + len -= nb; + } + + if (len) { + if (sect != cache_sect) { + if (dev_read (cache, sect, 1) < 0) { + return ((read) ? read : -1); + cache_sect = -1; + } + cache_sect = sect; + } + + memcpy (buf + read, cache, len); + read += len; + } + return (read); +} +#endif diff --git a/fs/fdos/vfat.c b/fs/fdos/vfat.c new file mode 100644 index 0000000..46a464b --- /dev/null +++ b/fs/fdos/vfat.c @@ -0,0 +1,357 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) +#include + +#include "dos.h" +#include "fdos.h" + +static int dir_read (Fs_t *fs, + Slot_t *dir, + Directory_t *dirent, + int num, + struct vfat_state *v); + +static int unicode_read (char *in, char *out, int num); +static int match (const char *s, const char *p); +static unsigned char sum_shortname (char *name); +static int check_vfat (struct vfat_state *v, Directory_t *dir); +static char *conv_name (char *name, char *ext, char Case, char *ans); + + +/*----------------------------------------------------------------------------- + * clear_vfat -- + *----------------------------------------------------------------------------- + */ +static void clear_vfat (struct vfat_state *v) +{ + v -> subentries = 0; + v -> status = 0; +} + +/*----------------------------------------------------------------------------- + * vfat_lookup -- + *----------------------------------------------------------------------------- + */ +int vfat_lookup (Slot_t *dir, + Fs_t *fs, + Directory_t *dirent, + int *entry, + int *vfat_start, + char *filename, + int flags, + char *outname, + Slot_t *file) +{ + int found; + struct vfat_state vfat; + char newfile [VSE_NAMELEN]; + int vfat_present = 0; + + if (*entry == -1) { + return -1; + } + + found = 0; + clear_vfat (&vfat); + while (1) { + if (dir_read (fs, dir, dirent, *entry, &vfat) < 0) { + if (vfat_start) { + *vfat_start = *entry; + } + break; + } + (*entry)++; + + /* Empty slot */ + if (dirent -> name[0] == '\0'){ + if (vfat_start == 0) { + break; + } + continue; + } + + if (dirent -> attr == ATTR_VSE) { + /* VSE entry, continue */ + continue; + } + if ( (dirent -> name [0] == DELMARK) || + ((dirent -> attr & ATTR_DIRECTORY) != 0 && + (flags & ACCEPT_DIR) == 0) || + ((dirent -> attr & ATTR_VOLUME) != 0 && + (flags & ACCEPT_LABEL) == 0) || + (((dirent -> attr & (ATTR_DIRECTORY | ATTR_VOLUME)) == 0) && + (flags & ACCEPT_PLAIN) == 0)) { + clear_vfat (&vfat); + continue; + } + + vfat_present = check_vfat (&vfat, dirent); + if (vfat_start) { + *vfat_start = *entry - 1; + if (vfat_present) { + *vfat_start -= vfat.subentries; + } + } + + if (dirent -> attr & ATTR_VOLUME) { + strncpy (newfile, dirent -> name, 8); + newfile [8] = '\0'; + strncat (newfile, dirent -> ext, 3); + newfile [11] = '\0'; + } + else { + conv_name (dirent -> name, dirent -> ext, dirent -> Case, newfile); + } + + if (flags & MATCH_ANY) { + found = 1; + break; + } + + if ((vfat_present && match (vfat.name, filename)) || + (match (newfile, filename))) { + found = 1; + break; + } + clear_vfat (&vfat); + } + + if (found) { + if ((flags & DO_OPEN) && file) { + if (open_file (file, dirent) < 0) { + return (-1); + } + } + if (outname) { + if (vfat_present) { + strcpy (outname, vfat.name); + } + else { + strcpy (outname, newfile); + } + } + return (0); /* File found */ + } else { + *entry = -1; + return -1; /* File not found */ + } +} + +/*----------------------------------------------------------------------------- + * dir_read -- Read one directory entry + *----------------------------------------------------------------------------- + */ +static int dir_read (Fs_t *fs, + Slot_t *dir, + Directory_t *dirent, + int num, + struct vfat_state *v) +{ + + /* read the directory entry */ + if (read_file (fs, + dir, + (char *)dirent, + num * MDIR_SIZE, + MDIR_SIZE) != MDIR_SIZE) { + return (-1); + } + + if (v && (dirent -> attr == ATTR_VSE)) { + struct vfat_subentry *vse; + unsigned char id, last_flag; + char *c; + + vse = (struct vfat_subentry *) dirent; + id = vse -> id & VSE_MASK; + last_flag = (vse -> id & VSE_LAST); + if (id > MAX_VFAT_SUBENTRIES) { + /* Invalid VSE entry */ + return (-1); + } + + + /* Decode VSE */ + if(v -> sum != vse -> sum) { + clear_vfat (v); + v -> sum = vse -> sum; + } + + + v -> status |= 1 << (id - 1); + if (last_flag) { + v -> subentries = id; + } + + c = &(v -> name [VSE_NAMELEN * (id - 1)]); + c += unicode_read (vse->text1, c, VSE1SIZE); + c += unicode_read (vse->text2, c, VSE2SIZE); + c += unicode_read (vse->text3, c, VSE3SIZE); + + if (last_flag) { + *c = '\0'; /* Null terminate long name */ + } + + } + return (0); +} + +/*----------------------------------------------------------------------------- + * unicode_read -- + *----------------------------------------------------------------------------- + */ +static int unicode_read (char *in, char *out, int num) +{ + int j; + + for (j = 0; j < num; ++j) { + if (in [1]) + *out = '_'; + else + *out = in [0]; + out ++; + in += 2; + } + return num; +} + +/*----------------------------------------------------------------------------- + * match -- + *----------------------------------------------------------------------------- + */ +static int match (const char *s, const char *p) +{ + + for (; *p != '\0'; ) { + if (toupper (*s) != toupper (*p)) { + return (0); + } + p++; + s++; + } + + if (*s != '\0') { + return (0); + } + else { + return (1); + } +} +/*----------------------------------------------------------------------------- + * sum_shortname -- + *----------------------------------------------------------------------------- + */ +static unsigned char sum_shortname (char *name) +{ + unsigned char sum; + int j; + + for (j = sum = 0; j < 11; ++j) { + sum = ((sum & 1) ? 0x80 : 0) + (sum >> 1) + + (name [j] ? name [j] : ' '); + } + return (sum); +} +/*----------------------------------------------------------------------------- + * check_vfat -- + * Return 1 if long name is valid, 0 else + *----------------------------------------------------------------------------- + */ +static int check_vfat (struct vfat_state *v, Directory_t *dir) +{ + char name[12]; + + if (v -> subentries == 0) { + return 0; + } + + strncpy (name, dir -> name, 8); + strncpy (name + 8, dir -> ext, 3); + name [11] = '\0'; + + if (v -> sum != sum_shortname (name)) { + return 0; + } + + if( (v -> status & ((1 << v -> subentries) - 1)) != + (1 << v -> subentries) - 1) { + return 0; + } + v->name [VSE_NAMELEN * v -> subentries] = 0; + + return 1; +} +/*----------------------------------------------------------------------------- + * conv_name -- + *----------------------------------------------------------------------------- + */ +static char *conv_name (char *name, char *ext, char Case, char *ans) +{ + char tname [9], text [4]; + int i; + + i = 0; + while (i < 8 && name [i] != ' ' && name [i] != '\0') { + tname [i] = name [i]; + i++; + } + tname [i] = '\0'; + + if (Case & BASECASE) { + for (i = 0; i < 8 && tname [i]; i++) { + tname [i] = tolower (tname [i]); + } + } + + i = 0; + while (i < 3 && ext [i] != ' ' && ext [i] != '\0') { + text [i] = ext [i]; + i++; + } + text [i] = '\0'; + + if (Case & EXTCASE){ + for (i = 0; i < 3 && text [i]; i++) { + text [i] = tolower (text [i]); + } + } + + if (*text) { + strcpy (ans, tname); + strcat (ans, "."); + strcat (ans, text); + } + else { + strcpy(ans, tname); + } + return (ans); +} + + +#endif diff --git a/fs/jffs2/Makefile b/fs/jffs2/Makefile new file mode 100644 index 0000000..f28b17a --- /dev/null +++ b/fs/jffs2/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libjffs2.a + +AOBJS = +COBJS = jffs2_1pass.o compr_rtime.o compr_rubin.o compr_zlib.o mini_inflate.o +COBJS += compr_lzo.o compr_lzari.o +OBJS = $(AOBJS) $(COBJS) + +#CPPFLAGS += + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/fs/jffs2/compr_lzari.c b/fs/jffs2/compr_lzari.c new file mode 100644 index 0000000..828b6e5 --- /dev/null +++ b/fs/jffs2/compr_lzari.c @@ -0,0 +1,262 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2004 Patrik Kluba, + * University of Szeged, Hungary + * + * For licensing information, see the file 'LICENCE' in the + * jffs2 directory. + * + * $Id: compr_lzari.c,v 1.3 2004/06/23 16:34:39 havasi Exp $ + * + */ + +/* + Lempel-Ziv-Arithmetic coding compression module for jffs2 + Based on the LZARI source included in LDS (lossless datacompression sources) +*/ + +/* -*- Mode: C; indent-tabs-mode: t; c-basic-offset: 4; tab-width: 4 -*- */ + +/* +Original copyright follows: + +************************************************************** + LZARI.C -- A Data Compression Program + (tab = 4 spaces) +************************************************************** + 4/7/1989 Haruhiko Okumura + Use, distribute, and modify this program freely. + Please send me your improved versions. + PC-VAN SCIENCE + NIFTY-Serve PAF01022 + CompuServe 74050,1022 +************************************************************** + +LZARI.C (c)1989 by Haruyasu Yoshizaki, Haruhiko Okumura, and Kenji Rikitake. +All rights reserved. Permission granted for non-commercial use. + +*/ + +/* + + 2004-02-18 pajko + Removed unused variables and fixed no return value + + 2004-02-16 pajko + Initial release + +*/ + + +#include +#if ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) + +#include +#include + + +#define N 4096 /* size of ring buffer */ +#define F 60 /* upper limit for match_length */ +#define THRESHOLD 2 /* encode string into position and length + if match_length is greater than this */ +#define NIL N /* index for root of binary search trees */ + +static unsigned char + text_buf[N + F - 1]; /* ring buffer of size N, + with extra F-1 bytes to facilitate string comparison */ + +/********** Arithmetic Compression **********/ + +/* If you are not familiar with arithmetic compression, you should read + I. E. Witten, R. M. Neal, and J. G. Cleary, + Communications of the ACM, Vol. 30, pp. 520-540 (1987), + from which much have been borrowed. */ + +#define M 15 + +/* Q1 (= 2 to the M) must be sufficiently large, but not so + large as the unsigned long 4 * Q1 * (Q1 - 1) overflows. */ + +#define Q1 (1UL << M) +#define Q2 (2 * Q1) +#define Q3 (3 * Q1) +#define Q4 (4 * Q1) +#define MAX_CUM (Q1 - 1) + +#define N_CHAR (256 - THRESHOLD + F) + /* character code = 0, 1, ..., N_CHAR - 1 */ + +static unsigned long char_to_sym[N_CHAR], sym_to_char[N_CHAR + 1]; +static unsigned long + sym_freq[N_CHAR + 1], /* frequency for symbols */ + sym_cum[N_CHAR + 1], /* cumulative freq for symbols */ + position_cum[N + 1]; /* cumulative freq for positions */ + +static void StartModel(void) /* Initialize model */ +{ + unsigned long ch, sym, i; + + sym_cum[N_CHAR] = 0; + for (sym = N_CHAR; sym >= 1; sym--) { + ch = sym - 1; + char_to_sym[ch] = sym; sym_to_char[sym] = ch; + sym_freq[sym] = 1; + sym_cum[sym - 1] = sym_cum[sym] + sym_freq[sym]; + } + sym_freq[0] = 0; /* sentinel (!= sym_freq[1]) */ + position_cum[N] = 0; + for (i = N; i >= 1; i--) + position_cum[i - 1] = position_cum[i] + 10000 / (i + 200); + /* empirical distribution function (quite tentative) */ + /* Please devise a better mechanism! */ +} + +static void UpdateModel(unsigned long sym) +{ + unsigned long c, ch_i, ch_sym; + unsigned long i; + if (sym_cum[0] >= MAX_CUM) { + c = 0; + for (i = N_CHAR; i > 0; i--) { + sym_cum[i] = c; + c += (sym_freq[i] = (sym_freq[i] + 1) >> 1); + } + sym_cum[0] = c; + } + for (i = sym; sym_freq[i] == sym_freq[i - 1]; i--) ; + if (i < sym) { + ch_i = sym_to_char[i]; ch_sym = sym_to_char[sym]; + sym_to_char[i] = ch_sym; sym_to_char[sym] = ch_i; + char_to_sym[ch_i] = sym; char_to_sym[ch_sym] = i; + } + sym_freq[i]++; + while (--i > 0) sym_cum[i]++; + sym_cum[0]++; +} + +static unsigned long BinarySearchSym(unsigned long x) + /* 1 if x >= sym_cum[1], + N_CHAR if sym_cum[N_CHAR] > x, + i such that sym_cum[i - 1] > x >= sym_cum[i] otherwise */ +{ + unsigned long i, j, k; + + i = 1; j = N_CHAR; + while (i < j) { + k = (i + j) / 2; + if (sym_cum[k] > x) i = k + 1; else j = k; + } + return i; +} + +unsigned long BinarySearchPos(unsigned long x) + /* 0 if x >= position_cum[1], + N - 1 if position_cum[N] > x, + i such that position_cum[i] > x >= position_cum[i + 1] otherwise */ +{ + unsigned long i, j, k; + + i = 1; j = N; + while (i < j) { + k = (i + j) / 2; + if (position_cum[k] > x) i = k + 1; else j = k; + } + return i - 1; +} + +static int Decode(unsigned char *srcbuf, unsigned char *dstbuf, unsigned long srclen, + unsigned long dstlen) /* Just the reverse of Encode(). */ +{ + unsigned long i, r, j, k, c, range, sym; + unsigned char *ip, *op; + unsigned char *srcend = srcbuf + srclen; + unsigned char *dstend = dstbuf + dstlen; + unsigned char buffer = 0; + unsigned char mask = 0; + unsigned long low = 0; + unsigned long high = Q4; + unsigned long value = 0; + + ip = srcbuf; + op = dstbuf; + for (i = 0; i < M + 2; i++) { + value *= 2; + if ((mask >>= 1) == 0) { + buffer = (ip >= srcend) ? 0 : *(ip++); + mask = 128; + } + value += ((buffer & mask) != 0); + } + + StartModel(); + for (i = 0; i < N - F; i++) text_buf[i] = ' '; + r = N - F; + + while (op < dstend) { + range = high - low; + sym = BinarySearchSym((unsigned long) + (((value - low + 1) * sym_cum[0] - 1) / range)); + high = low + (range * sym_cum[sym - 1]) / sym_cum[0]; + low += (range * sym_cum[sym ]) / sym_cum[0]; + for ( ; ; ) { + if (low >= Q2) { + value -= Q2; low -= Q2; high -= Q2; + } else if (low >= Q1 && high <= Q3) { + value -= Q1; low -= Q1; high -= Q1; + } else if (high > Q2) break; + low += low; high += high; + value *= 2; + if ((mask >>= 1) == 0) { + buffer = (ip >= srcend) ? 0 : *(ip++); + mask = 128; + } + value += ((buffer & mask) != 0); + } + c = sym_to_char[sym]; + UpdateModel(sym); + if (c < 256) { + if (op >= dstend) return -1; + *(op++) = c; + text_buf[r++] = c; + r &= (N - 1); + } else { + j = c - 255 + THRESHOLD; + range = high - low; + i = BinarySearchPos((unsigned long) + (((value - low + 1) * position_cum[0] - 1) / range)); + high = low + (range * position_cum[i ]) / position_cum[0]; + low += (range * position_cum[i + 1]) / position_cum[0]; + for ( ; ; ) { + if (low >= Q2) { + value -= Q2; low -= Q2; high -= Q2; + } else if (low >= Q1 && high <= Q3) { + value -= Q1; low -= Q1; high -= Q1; + } else if (high > Q2) break; + low += low; high += high; + value *= 2; + if ((mask >>= 1) == 0) { + buffer = (ip >= srcend) ? 0 : *(ip++); + mask = 128; + } + value += ((buffer & mask) != 0); + } + i = (r - i - 1) & (N - 1); + for (k = 0; k < j; k++) { + c = text_buf[(i + k) & (N - 1)]; + if (op >= dstend) return -1; + *(op++) = c; + text_buf[r++] = c; + r &= (N - 1); + } + } + } + return 0; +} + +int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen) +{ + return Decode(data_in, cpage_out, srclen, destlen); +} +#endif /* ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) */ diff --git a/fs/jffs2/compr_lzo.c b/fs/jffs2/compr_lzo.c new file mode 100644 index 0000000..b6c590a --- /dev/null +++ b/fs/jffs2/compr_lzo.c @@ -0,0 +1,405 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2004 Patrik Kluba, + * University of Szeged, Hungary + * + * For licensing information, see the file 'LICENCE' in the + * jffs2 directory. + * + * $Id: compr_lzo.c,v 1.3 2004/06/23 16:34:39 havasi Exp $ + * + */ + +/* + LZO1X-1 (and -999) compression module for jffs2 + based on the original LZO sources +*/ + +/* -*- Mode: C; indent-tabs-mode: t; c-basic-offset: 4; tab-width: 4 -*- */ + +/* + Original copyright notice follows: + + lzo1x_9x.c -- implementation of the LZO1X-999 compression algorithm + lzo_ptr.h -- low-level pointer constructs + lzo_swd.ch -- sliding window dictionary + lzoconf.h -- configuration for the LZO real-time data compression library + lzo_mchw.ch -- matching functions using a window + minilzo.c -- mini subset of the LZO real-time data compression library + config1x.h -- configuration for the LZO1X algorithm + lzo1x.h -- public interface of the LZO1X compression algorithm + + These files are part of the LZO real-time data compression library. + + Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer + All Rights Reserved. + + The LZO library is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of + the License, or (at your option) any later version. + + The LZO library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with the LZO library; see the file COPYING. + If not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Markus F.X.J. Oberhumer + +*/ + +/* + + 2004-02-16 pajko + Initial release + -removed all 16 bit code + -all sensitive data will be on 4 byte boundary + -removed check parts for library use + -removed all but LZO1X-* compression + +*/ + + +#include +#if ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) + +#include +#include +#include + +/* Integral types that have *exactly* the same number of bits as a lzo_voidp */ +typedef unsigned long lzo_ptr_t; +typedef long lzo_sptr_t; + +/* data type definitions */ +#define U32 unsigned long +#define S32 signed long +#define I32 long +#define U16 unsigned short +#define S16 signed short +#define I16 short +#define U8 unsigned char +#define S8 signed char +#define I8 char + +#define M1_MAX_OFFSET 0x0400 +#define M2_MAX_OFFSET 0x0800 +#define M3_MAX_OFFSET 0x4000 +#define M4_MAX_OFFSET 0xbfff + +#define __COPY4(dst,src) * (lzo_uint32p)(dst) = * (const lzo_uint32p)(src) +#define COPY4(dst,src) __COPY4((lzo_ptr_t)(dst),(lzo_ptr_t)(src)) + +#define TEST_IP (ip < ip_end) +#define TEST_OP (op <= op_end) + +#define NEED_IP(x) \ + if ((lzo_uint)(ip_end - ip) < (lzo_uint)(x)) goto input_overrun +#define NEED_OP(x) \ + if ((lzo_uint)(op_end - op) < (lzo_uint)(x)) goto output_overrun +#define TEST_LOOKBEHIND(m_pos,out) if (m_pos < out) goto lookbehind_overrun + +typedef U32 lzo_uint32; +typedef I32 lzo_int32; +typedef U32 lzo_uint; +typedef I32 lzo_int; +typedef int lzo_bool; + +#define lzo_byte U8 +#define lzo_bytep U8 * +#define lzo_charp char * +#define lzo_voidp void * +#define lzo_shortp short * +#define lzo_ushortp unsigned short * +#define lzo_uint32p lzo_uint32 * +#define lzo_int32p lzo_int32 * +#define lzo_uintp lzo_uint * +#define lzo_intp lzo_int * +#define lzo_voidpp lzo_voidp * +#define lzo_bytepp lzo_bytep * +#define lzo_sizeof_dict_t sizeof(lzo_bytep) + +#define LZO_E_OK 0 +#define LZO_E_ERROR (-1) +#define LZO_E_OUT_OF_MEMORY (-2) /* not used right now */ +#define LZO_E_NOT_COMPRESSIBLE (-3) /* not used right now */ +#define LZO_E_INPUT_OVERRUN (-4) +#define LZO_E_OUTPUT_OVERRUN (-5) +#define LZO_E_LOOKBEHIND_OVERRUN (-6) +#define LZO_E_EOF_NOT_FOUND (-7) +#define LZO_E_INPUT_NOT_CONSUMED (-8) + +#define PTR(a) ((lzo_ptr_t) (a)) +#define PTR_LINEAR(a) PTR(a) +#define PTR_ALIGNED_4(a) ((PTR_LINEAR(a) & 3) == 0) +#define PTR_ALIGNED_8(a) ((PTR_LINEAR(a) & 7) == 0) +#define PTR_ALIGNED2_4(a,b) (((PTR_LINEAR(a) | PTR_LINEAR(b)) & 3) == 0) +#define PTR_ALIGNED2_8(a,b) (((PTR_LINEAR(a) | PTR_LINEAR(b)) & 7) == 0) +#define PTR_LT(a,b) (PTR(a) < PTR(b)) +#define PTR_GE(a,b) (PTR(a) >= PTR(b)) +#define PTR_DIFF(a,b) ((lzo_ptrdiff_t) (PTR(a) - PTR(b))) +#define pd(a,b) ((lzo_uint) ((a)-(b))) + +typedef ptrdiff_t lzo_ptrdiff_t; + +static int +lzo1x_decompress (const lzo_byte * in, lzo_uint in_len, + lzo_byte * out, lzo_uintp out_len, lzo_voidp wrkmem) +{ + register lzo_byte *op; + register const lzo_byte *ip; + register lzo_uint t; + + register const lzo_byte *m_pos; + + const lzo_byte *const ip_end = in + in_len; + lzo_byte *const op_end = out + *out_len; + + *out_len = 0; + + op = out; + ip = in; + + if (*ip > 17) + { + t = *ip++ - 17; + if (t < 4) + goto match_next; + NEED_OP (t); + NEED_IP (t + 1); + do + *op++ = *ip++; + while (--t > 0); + goto first_literal_run; + } + + while (TEST_IP && TEST_OP) + { + t = *ip++; + if (t >= 16) + goto match; + if (t == 0) + { + NEED_IP (1); + while (*ip == 0) + { + t += 255; + ip++; + NEED_IP (1); + } + t += 15 + *ip++; + } + NEED_OP (t + 3); + NEED_IP (t + 4); + if (PTR_ALIGNED2_4 (op, ip)) + { + COPY4 (op, ip); + + op += 4; + ip += 4; + if (--t > 0) + { + if (t >= 4) + { + do + { + COPY4 (op, ip); + op += 4; + ip += 4; + t -= 4; + } + while (t >= 4); + if (t > 0) + do + *op++ = *ip++; + while (--t > 0); + } + else + do + *op++ = *ip++; + while (--t > 0); + } + } + else + { + *op++ = *ip++; + *op++ = *ip++; + *op++ = *ip++; + do + *op++ = *ip++; + while (--t > 0); + } + first_literal_run: + + t = *ip++; + if (t >= 16) + goto match; + + m_pos = op - (1 + M2_MAX_OFFSET); + m_pos -= t >> 2; + m_pos -= *ip++ << 2; + TEST_LOOKBEHIND (m_pos, out); + NEED_OP (3); + *op++ = *m_pos++; + *op++ = *m_pos++; + *op++ = *m_pos; + + goto match_done; + + while (TEST_IP && TEST_OP) + { + match: + if (t >= 64) + { + m_pos = op - 1; + m_pos -= (t >> 2) & 7; + m_pos -= *ip++ << 3; + t = (t >> 5) - 1; + TEST_LOOKBEHIND (m_pos, out); + NEED_OP (t + 3 - 1); + goto copy_match; + + } + else if (t >= 32) + { + t &= 31; + if (t == 0) + { + NEED_IP (1); + while (*ip == 0) + { + t += 255; + ip++; + NEED_IP (1); + } + t += 31 + *ip++; + } + + m_pos = op - 1; + m_pos -= (ip[0] >> 2) + (ip[1] << 6); + + ip += 2; + } + else if (t >= 16) + { + m_pos = op; + m_pos -= (t & 8) << 11; + + t &= 7; + if (t == 0) + { + NEED_IP (1); + while (*ip == 0) + { + t += 255; + ip++; + NEED_IP (1); + } + t += 7 + *ip++; + } + + m_pos -= (ip[0] >> 2) + (ip[1] << 6); + + ip += 2; + if (m_pos == op) + goto eof_found; + m_pos -= 0x4000; + } + else + { + + m_pos = op - 1; + m_pos -= t >> 2; + m_pos -= *ip++ << 2; + TEST_LOOKBEHIND (m_pos, out); + NEED_OP (2); + *op++ = *m_pos++; + *op++ = *m_pos; + + goto match_done; + } + + TEST_LOOKBEHIND (m_pos, out); + NEED_OP (t + 3 - 1); + if (t >= 2 * 4 - (3 - 1) + && PTR_ALIGNED2_4 (op, m_pos)) + { + COPY4 (op, m_pos); + op += 4; + m_pos += 4; + t -= 4 - (3 - 1); + do + { + COPY4 (op, m_pos); + op += 4; + m_pos += 4; + t -= 4; + } + while (t >= 4); + if (t > 0) + do + *op++ = *m_pos++; + while (--t > 0); + } + else + + { + copy_match: + *op++ = *m_pos++; + *op++ = *m_pos++; + do + *op++ = *m_pos++; + while (--t > 0); + } + + match_done: + t = ip[-2] & 3; + + if (t == 0) + break; + + match_next: + NEED_OP (t); + NEED_IP (t + 1); + do + *op++ = *ip++; + while (--t > 0); + t = *ip++; + } + } + *out_len = op - out; + return LZO_E_EOF_NOT_FOUND; + + eof_found: + *out_len = op - out; + return (ip == ip_end ? LZO_E_OK : + (ip < + ip_end ? LZO_E_INPUT_NOT_CONSUMED : LZO_E_INPUT_OVERRUN)); + + input_overrun: + *out_len = op - out; + return LZO_E_INPUT_OVERRUN; + + output_overrun: + *out_len = op - out; + return LZO_E_OUTPUT_OVERRUN; + + lookbehind_overrun: + *out_len = op - out; + return LZO_E_LOOKBEHIND_OVERRUN; +} + +int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen) +{ + lzo_uint outlen = destlen; + return lzo1x_decompress (data_in, srclen, cpage_out, &outlen, NULL); +} + +#endif /* ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) */ diff --git a/fs/jffs2/compr_rtime.c b/fs/jffs2/compr_rtime.c new file mode 100644 index 0000000..9bb4f1b --- /dev/null +++ b/fs/jffs2/compr_rtime.c @@ -0,0 +1,91 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by Arjan van de Ven + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: compr_rtime.c,v 1.2 2002/01/24 22:58:42 rfeany Exp $ + * + * + * Very simple lz77-ish encoder. + * + * Theory of operation: Both encoder and decoder have a list of "last + * occurances" for every possible source-value; after sending the + * first source-byte, the second byte indicated the "run" length of + * matches + * + * The algorithm is intended to only send "whole bytes", no bit-messing. + * + */ + +#include +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include + +void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen) +{ + int positions[256]; + int outpos; + int pos; + int i; + + outpos = pos = 0; + + for (i = 0; i < 256; positions[i++] = 0); + + while (outpos= outpos) { + while(repeat) { + cpage_out[outpos++] = cpage_out[backoffs++]; + repeat--; + } + } else { + for (i = 0; i < repeat; i++) + *(cpage_out + outpos + i) = *(cpage_out + backoffs + i); + outpos+=repeat; + } + } + } +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/compr_rubin.c b/fs/jffs2/compr_rubin.c new file mode 100644 index 0000000..74577d9 --- /dev/null +++ b/fs/jffs2/compr_rubin.c @@ -0,0 +1,126 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by Arjan van de Ven + * + * Heavily modified by Russ Dill in an attempt at + * a little more speed. + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: compr_rubin.c,v 1.2 2002/01/24 22:58:42 rfeany Exp $ + * + */ + +#include +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include +#include + + +void rubin_do_decompress(unsigned char *bits, unsigned char *in, + unsigned char *page_out, __u32 destlen) +{ + register char *curr = (char *)page_out; + char *end = (char *)(page_out + destlen); + register unsigned long temp; + register unsigned long result; + register unsigned long p; + register unsigned long q; + register unsigned long rec_q; + register unsigned long bit; + register long i0; + unsigned long i; + + /* init_pushpull */ + temp = *(u32 *) in; + bit = 16; + + /* init_rubin */ + q = 0; + p = (long) (2 * UPPER_BIT_RUBIN); + + /* init_decode */ + rec_q = (in[0] << 8) | in[1]; + + while (curr < end) { + /* in byte */ + + result = 0; + for (i = 0; i < 8; i++) { + /* decode */ + + while ((q & UPPER_BIT_RUBIN) || ((p + q) <= UPPER_BIT_RUBIN)) { + q &= ~UPPER_BIT_RUBIN; + q <<= 1; + p <<= 1; + rec_q &= ~UPPER_BIT_RUBIN; + rec_q <<= 1; + rec_q |= (temp >> (bit++ ^ 7)) & 1; + if (bit > 31) { + u32 *p = (u32 *)in; + bit = 0; + temp = *(++p); + in = (unsigned char *)p; + } + } + i0 = (bits[i] * p) >> 8; + + if (i0 <= 0) i0 = 1; + /* if it fails, it fails, we have our crc + if (i0 >= p) i0 = p - 1; */ + + result >>= 1; + if (rec_q < q + i0) { + /* result |= 0x00; */ + p = i0; + } else { + result |= 0x80; + p -= i0; + q += i0; + } + } + *(curr++) = result; + } +} + +void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, + unsigned long sourcelen, unsigned long dstlen) +{ + unsigned char bits[8]; + int c; + + for (c=0; c<8; c++) + bits[c] = (256 - data_in[c]); + + rubin_do_decompress(bits, data_in+8, cpage_out, dstlen); +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/compr_zlib.c b/fs/jffs2/compr_zlib.c new file mode 100644 index 0000000..1b35585 --- /dev/null +++ b/fs/jffs2/compr_zlib.c @@ -0,0 +1,52 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by David Woodhouse + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: compr_zlib.c,v 1.2 2002/01/24 22:58:42 rfeany Exp $ + * + */ + +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include +#include + +long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, + __u32 srclen, __u32 destlen) +{ + return (decompress_block(cpage_out, data_in + 2, ldr_memcpy)); + +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c new file mode 100644 index 0000000..c6c0c2a --- /dev/null +++ b/fs/jffs2/jffs2_1pass.c @@ -0,0 +1,1370 @@ +/* +------------------------------------------------------------------------- + * Filename: jffs2.c + * Version: $Id: jffs2_1pass.c,v 1.7 2002/01/25 01:56:47 nyet Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: Module to load kernel from jffs2 + *-----------------------------------------------------------------------*/ +/* + * some portions of this code are taken from jffs2, and as such, the + * following copyright notice is included. + * + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by David Woodhouse + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: jffs2_1pass.c,v 1.7 2002/01/25 01:56:47 nyet Exp $ + * + */ + +/* Ok, so anyone who knows the jffs2 code will probably want to get a papar + * bag to throw up into before reading this code. I looked through the jffs2 + * code, the caching scheme is very elegant. I tried to keep the version + * for a bootloader as small and simple as possible. Instead of worring about + * unneccesary data copies, node scans, etc, I just optimized for the known + * common case, a kernel, which looks like: + * (1) most pages are 4096 bytes + * (2) version numbers are somewhat sorted in acsending order + * (3) multiple compressed blocks making up one page is uncommon + * + * So I create a linked list of decending version numbers (insertions at the + * head), and then for each page, walk down the list, until a matching page + * with 4096 bytes is found, and then decompress the watching pages in + * reverse order. + * + */ + +/* + * Adapted by Nye Liu and + * Rex Feany + * on Jan/2002 for U-Boot. + * + * Clipped out all the non-1pass functions, cleaned up warnings, + * wrappers, etc. No major changes to the code. + * Please, he really means it when he said have a paper bag + * handy. We needed it ;). + * + */ + +/* + * Bugfixing by Kai-Uwe Bloem , (C) Mar/2003 + * + * - overhaul of the memory management. Removed much of the "paper-bagging" + * in that part of the code, fixed several bugs, now frees memory when + * partition is changed. + * It's still ugly :-( + * - fixed a bug in jffs2_1pass_read_inode where the file length calculation + * was incorrect. Removed a bit of the paper-bagging as well. + * - removed double crc calculation for fragment headers in jffs2_private.h + * for speedup. + * - scan_empty rewritten in a more "standard" manner (non-paperbag, that is). + * - spinning wheel now spins depending on how much memory has been scanned + * - lots of small changes all over the place to "improve" readability. + * - implemented fragment sorting to ensure that the newest data is copied + * if there are multiple copies of fragments for a certain file offset. + * + * The fragment sorting feature must be enabled by CFG_JFFS2_SORT_FRAGMENTS. + * Sorting is done while adding fragments to the lists, which is more or less a + * bubble sort. This takes a lot of time, and is most probably not an issue if + * the boot filesystem is always mounted readonly. + * + * You should define it if the boot filesystem is mounted writable, and updates + * to the boot files are done by copying files to that filesystem. + * + * + * There's a big issue left: endianess is completely ignored in this code. Duh! + * + * + * You still should have paper bags at hand :-(. The code lacks more or less + * any comment, and is still arcane and difficult to read in places. As this + * might be incompatible with any new code from the jffs2 maintainers anyway, + * it should probably be dumped and replaced by something like jffs2reader! + */ + + +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include +#include + +#include "jffs2_private.h" + + +#define NODE_CHUNK 1024 /* size of memory allocation chunk in b_nodes */ +#define SPIN_BLKSIZE 18 /* spin after having scanned 1<dev->id; + u32 bytes_read = 0; + size_t retlen; + int cpy_bytes; + + while (bytes_read < size) { + if ((off + bytes_read < nand_cache_off) || + (off + bytes_read >= nand_cache_off+NAND_CACHE_SIZE)) { + nand_cache_off = (off + bytes_read) & NAND_PAGE_MASK; + if (!nand_cache) { + /* This memory never gets freed but 'cause + it's a bootloader, nobody cares */ + nand_cache = malloc(NAND_CACHE_SIZE); + if (!nand_cache) { + printf("read_nand_cached: can't alloc cache size %d bytes\n", + NAND_CACHE_SIZE); + return -1; + } + } + if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE, + &retlen, nand_cache, id->num) < 0 || + retlen != NAND_CACHE_SIZE) { + printf("read_nand_cached: error reading nand off %#x size %d bytes\n", + nand_cache_off, NAND_CACHE_SIZE); + return -1; + } + } + cpy_bytes = nand_cache_off + NAND_CACHE_SIZE - (off + bytes_read); + if (cpy_bytes > size - bytes_read) + cpy_bytes = size - bytes_read; + memcpy(buf + bytes_read, + nand_cache + off + bytes_read - nand_cache_off, + cpy_bytes); + bytes_read += cpy_bytes; + } + return bytes_read; +} + +static void *get_fl_mem_nand(u32 off, u32 size, void *ext_buf) +{ + u_char *buf = ext_buf ? (u_char*)ext_buf : (u_char*)malloc(size); + + if (NULL == buf) { + printf("get_fl_mem_nand: can't alloc %d bytes\n", size); + return NULL; + } + if (read_nand_cached(off, size, buf) < 0) { + if (!ext_buf) + free(buf); + return NULL; + } + + return buf; +} + +static void *get_node_mem_nand(u32 off) +{ + struct jffs2_unknown_node node; + void *ret = NULL; + + if (NULL == get_fl_mem_nand(off, sizeof(node), &node)) + return NULL; + + if (!(ret = get_fl_mem_nand(off, node.magic == + JFFS2_MAGIC_BITMASK ? node.totlen : sizeof(node), + NULL))) { + printf("off = %#x magic %#x type %#x node.totlen = %d\n", + off, node.magic, node.nodetype, node.totlen); + } + return ret; +} + +static void put_fl_mem_nand(void *buf) +{ + free(buf); +} +#endif /* #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */ + + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) +/* + * Support for jffs2 on top of NOR-flash + * + * NOR flash memory is mapped in processor's address space, + * just return address. + */ +static inline void *get_fl_mem_nor(u32 off) +{ + u32 addr = off; + struct mtdids *id = current_part->dev->id; + + extern flash_info_t flash_info[]; + flash_info_t *flash = &flash_info[id->num]; + + addr += flash->start[0]; + return (void*)addr; +} + +static inline void *get_node_mem_nor(u32 off) +{ + return (void*)get_fl_mem_nor(off); +} +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FLASH) */ + + +/* + * Generic jffs2 raw memory and node read routines. + * + */ +static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf) +{ + struct mtdids *id = current_part->dev->id; + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + if (id->type == MTD_DEV_TYPE_NOR) + return get_fl_mem_nor(off); +#endif + +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) + if (id->type == MTD_DEV_TYPE_NAND) + return get_fl_mem_nand(off, size, ext_buf); +#endif + + printf("get_fl_mem: unknown device type, using raw offset!\n"); + return (void*)off; +} + +static inline void *get_node_mem(u32 off) +{ + struct mtdids *id = current_part->dev->id; + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + if (id->type == MTD_DEV_TYPE_NOR) + return get_node_mem_nor(off); +#endif + +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) + if (id->type == MTD_DEV_TYPE_NAND) + return get_node_mem_nand(off); +#endif + + printf("get_node_mem: unknown device type, using raw offset!\n"); + return (void*)off; +} + +static inline void put_fl_mem(void *buf) +{ +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) + struct mtdids *id = current_part->dev->id; + + if (id->type == MTD_DEV_TYPE_NAND) + return put_fl_mem_nand(buf); +#endif +} + +/* Compression names */ +static char *compr_names[] = { + "NONE", + "ZERO", + "RTIME", + "RUBINMIPS", + "COPY", + "DYNRUBIN", + "ZLIB", +#if defined(CONFIG_JFFS2_LZO_LZARI) + "LZO", + "LZARI", +#endif +}; + +/* Spinning wheel */ +static char spinner[] = { '|', '/', '-', '\\' }; + +/* Memory management */ +struct mem_block { + u32 index; + struct mem_block *next; + struct b_node nodes[NODE_CHUNK]; +}; + + +static void +free_nodes(struct b_list *list) +{ + while (list->listMemBase != NULL) { + struct mem_block *next = list->listMemBase->next; + free( list->listMemBase ); + list->listMemBase = next; + } +} + +static struct b_node * +add_node(struct b_list *list) +{ + u32 index = 0; + struct mem_block *memBase; + struct b_node *b; + + memBase = list->listMemBase; + if (memBase != NULL) + index = memBase->index; +#if 0 + putLabeledWord("add_node: index = ", index); + putLabeledWord("add_node: memBase = ", list->listMemBase); +#endif + + if (memBase == NULL || index >= NODE_CHUNK) { + /* we need more space before we continue */ + memBase = mmalloc(sizeof(struct mem_block)); + if (memBase == NULL) { + putstr("add_node: malloc failed\n"); + return NULL; + } + memBase->next = list->listMemBase; + index = 0; +#if 0 + putLabeledWord("add_node: alloced a new membase at ", *memBase); +#endif + + } + /* now we have room to add it. */ + b = &memBase->nodes[index]; + index ++; + + memBase->index = index; + list->listMemBase = memBase; + list->listCount++; + return b; +} + +static struct b_node * +insert_node(struct b_list *list, u32 offset) +{ + struct b_node *new; +#ifdef CFG_JFFS2_SORT_FRAGMENTS + struct b_node *b, *prev; +#endif + + if (!(new = add_node(list))) { + putstr("add_node failed!\r\n"); + return NULL; + } + new->offset = offset; + +#ifdef CFG_JFFS2_SORT_FRAGMENTS + if (list->listTail != NULL && list->listCompare(new, list->listTail)) + prev = list->listTail; + else if (list->listLast != NULL && list->listCompare(new, list->listLast)) + prev = list->listLast; + else + prev = NULL; + + for (b = (prev ? prev->next : list->listHead); + b != NULL && list->listCompare(new, b); + prev = b, b = b->next) { + list->listLoops++; + } + if (b != NULL) + list->listLast = prev; + + if (b != NULL) { + new->next = b; + if (prev != NULL) + prev->next = new; + else + list->listHead = new; + } else +#endif + { + new->next = (struct b_node *) NULL; + if (list->listTail != NULL) { + list->listTail->next = new; + list->listTail = new; + } else { + list->listTail = list->listHead = new; + } + } + + return new; +} + +#ifdef CFG_JFFS2_SORT_FRAGMENTS +/* Sort data entries with the latest version last, so that if there + * is overlapping data the latest version will be used. + */ +static int compare_inodes(struct b_node *new, struct b_node *old) +{ + struct jffs2_raw_inode ojNew; + struct jffs2_raw_inode ojOld; + struct jffs2_raw_inode *jNew = + (struct jffs2_raw_inode *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew); + struct jffs2_raw_inode *jOld = + (struct jffs2_raw_inode *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld); + + return jNew->version > jOld->version; +} + +/* Sort directory entries so all entries in the same directory + * with the same name are grouped together, with the latest version + * last. This makes it easy to eliminate all but the latest version + * by marking the previous version dead by setting the inode to 0. + */ +static int compare_dirents(struct b_node *new, struct b_node *old) +{ + struct jffs2_raw_dirent ojNew; + struct jffs2_raw_dirent ojOld; + struct jffs2_raw_dirent *jNew = + (struct jffs2_raw_dirent *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew); + struct jffs2_raw_dirent *jOld = + (struct jffs2_raw_dirent *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld); + int cmp; + + /* ascending sort by pino */ + if (jNew->pino != jOld->pino) + return jNew->pino > jOld->pino; + + /* pino is the same, so use ascending sort by nsize, so + * we don't do strncmp unless we really must. + */ + if (jNew->nsize != jOld->nsize) + return jNew->nsize > jOld->nsize; + + /* length is also the same, so use ascending sort by name + */ + cmp = strncmp((char *)jNew->name, (char *)jOld->name, jNew->nsize); + if (cmp != 0) + return cmp > 0; + + /* we have duplicate names in this directory, so use ascending + * sort by version + */ + if (jNew->version > jOld->version) { + /* since jNew is newer, we know jOld is not valid, so + * mark it with inode 0 and it will not be used + */ + jOld->ino = 0; + return 1; + } + + return 0; +} +#endif + +static u32 +jffs2_scan_empty(u32 start_offset, struct part_info *part) +{ + char *max = (char *)(part->offset + part->size - sizeof(struct jffs2_raw_inode)); + char *offset = (char *)(part->offset + start_offset); + u32 off; + + while (offset < max && + *(u32*)get_fl_mem((u32)offset, sizeof(u32), &off) == 0xFFFFFFFF) { + offset += sizeof(u32); + /* return if spinning is due */ + if (((u32)offset & ((1 << SPIN_BLKSIZE)-1)) == 0) break; + } + + return (u32)offset - part->offset; +} + +void +jffs2_free_cache(struct part_info *part) +{ + struct b_lists *pL; + + if (part->jffs2_priv != NULL) { + pL = (struct b_lists *)part->jffs2_priv; + free_nodes(&pL->frag); + free_nodes(&pL->dir); + free(pL); + } +} + +static u32 +jffs_init_1pass_list(struct part_info *part) +{ + struct b_lists *pL; + + jffs2_free_cache(part); + + if (NULL != (part->jffs2_priv = malloc(sizeof(struct b_lists)))) { + pL = (struct b_lists *)part->jffs2_priv; + + memset(pL, 0, sizeof(*pL)); +#ifdef CFG_JFFS2_SORT_FRAGMENTS + pL->dir.listCompare = compare_dirents; + pL->frag.listCompare = compare_inodes; +#endif + } + return 0; +} + +/* find the inode from the slashless name given a parent */ +static long +jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest) +{ + struct b_node *b; + struct jffs2_raw_inode *jNode; + u32 totalSize = 0; + u32 latestVersion = 0; + uchar *lDest; + uchar *src; + long ret; + int i; + u32 counter = 0; +#ifdef CFG_JFFS2_SORT_FRAGMENTS + /* Find file size before loading any data, so fragments that + * start past the end of file can be ignored. A fragment + * that is partially in the file is loaded, so extra data may + * be loaded up to the next 4K boundary above the file size. + * This shouldn't cause trouble when loading kernel images, so + * we will live with it. + */ + for (b = pL->frag.listHead; b != NULL; b = b->next) { + jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset, + sizeof(struct jffs2_raw_inode), NULL); + if ((inode == jNode->ino)) { + /* get actual file length from the newest node */ + if (jNode->version >= latestVersion) { + totalSize = jNode->isize; + latestVersion = jNode->version; + } + } + put_fl_mem(jNode); + } +#endif + + for (b = pL->frag.listHead; b != NULL; b = b->next) { + jNode = (struct jffs2_raw_inode *) get_node_mem(b->offset); + if ((inode == jNode->ino)) { +#if 0 + putLabeledWord("\r\n\r\nread_inode: totlen = ", jNode->totlen); + putLabeledWord("read_inode: inode = ", jNode->ino); + putLabeledWord("read_inode: version = ", jNode->version); + putLabeledWord("read_inode: isize = ", jNode->isize); + putLabeledWord("read_inode: offset = ", jNode->offset); + putLabeledWord("read_inode: csize = ", jNode->csize); + putLabeledWord("read_inode: dsize = ", jNode->dsize); + putLabeledWord("read_inode: compr = ", jNode->compr); + putLabeledWord("read_inode: usercompr = ", jNode->usercompr); + putLabeledWord("read_inode: flags = ", jNode->flags); +#endif + +#ifndef CFG_JFFS2_SORT_FRAGMENTS + /* get actual file length from the newest node */ + if (jNode->version >= latestVersion) { + totalSize = jNode->isize; + latestVersion = jNode->version; + } +#endif + + if(dest) { + src = ((uchar *) jNode) + sizeof(struct jffs2_raw_inode); + /* ignore data behind latest known EOF */ + if (jNode->offset > totalSize) { + put_fl_mem(jNode); + continue; + } + + lDest = (uchar *) (dest + jNode->offset); +#if 0 + putLabeledWord("read_inode: src = ", src); + putLabeledWord("read_inode: dest = ", lDest); +#endif + switch (jNode->compr) { + case JFFS2_COMPR_NONE: + ret = (unsigned long) ldr_memcpy(lDest, src, jNode->dsize); + break; + case JFFS2_COMPR_ZERO: + ret = 0; + for (i = 0; i < jNode->dsize; i++) + *(lDest++) = 0; + break; + case JFFS2_COMPR_RTIME: + ret = 0; + rtime_decompress(src, lDest, jNode->csize, jNode->dsize); + break; + case JFFS2_COMPR_DYNRUBIN: + /* this is slow but it works */ + ret = 0; + dynrubin_decompress(src, lDest, jNode->csize, jNode->dsize); + break; + case JFFS2_COMPR_ZLIB: + ret = zlib_decompress(src, lDest, jNode->csize, jNode->dsize); + break; +#if defined(CONFIG_JFFS2_LZO_LZARI) + case JFFS2_COMPR_LZO: + ret = lzo_decompress(src, lDest, jNode->csize, jNode->dsize); + break; + case JFFS2_COMPR_LZARI: + ret = lzari_decompress(src, lDest, jNode->csize, jNode->dsize); + break; +#endif + default: + /* unknown */ + putLabeledWord("UNKOWN COMPRESSION METHOD = ", jNode->compr); + put_fl_mem(jNode); + return -1; + break; + } + } + +#if 0 + putLabeledWord("read_inode: totalSize = ", totalSize); + putLabeledWord("read_inode: compr ret = ", ret); +#endif + } + counter++; + put_fl_mem(jNode); + } + +#if 0 + putLabeledWord("read_inode: returning = ", totalSize); +#endif + return totalSize; +} + +/* find the inode from the slashless name given a parent */ +static u32 +jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino) +{ + struct b_node *b; + struct jffs2_raw_dirent *jDir; + int len; + u32 counter; + u32 version = 0; + u32 inode = 0; + + /* name is assumed slash free */ + len = strlen(name); + + counter = 0; + /* we need to search all and return the inode with the highest version */ + for(b = pL->dir.listHead; b; b = b->next, counter++) { + jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset); + if ((pino == jDir->pino) && (len == jDir->nsize) && + (jDir->ino) && /* 0 for unlink */ + (!strncmp((char *)jDir->name, name, len))) { /* a match */ + if (jDir->version < version) { + put_fl_mem(jDir); + continue; + } + + if (jDir->version == version && inode != 0) { + /* I'm pretty sure this isn't legal */ + putstr(" ** ERROR ** "); + putnstr(jDir->name, jDir->nsize); + putLabeledWord(" has dup version =", version); + } + inode = jDir->ino; + version = jDir->version; + } +#if 0 + putstr("\r\nfind_inode:p&l ->"); + putnstr(jDir->name, jDir->nsize); + putstr("\r\n"); + putLabeledWord("pino = ", jDir->pino); + putLabeledWord("nsize = ", jDir->nsize); + putLabeledWord("b = ", (u32) b); + putLabeledWord("counter = ", counter); +#endif + put_fl_mem(jDir); + } + return inode; +} + +char *mkmodestr(unsigned long mode, char *str) +{ + static const char *l = "xwr"; + int mask = 1, i; + char c; + + switch (mode & S_IFMT) { + case S_IFDIR: str[0] = 'd'; break; + case S_IFBLK: str[0] = 'b'; break; + case S_IFCHR: str[0] = 'c'; break; + case S_IFIFO: str[0] = 'f'; break; + case S_IFLNK: str[0] = 'l'; break; + case S_IFSOCK: str[0] = 's'; break; + case S_IFREG: str[0] = '-'; break; + default: str[0] = '?'; + } + + for(i = 0; i < 9; i++) { + c = l[i%3]; + str[9-i] = (mode & mask)?c:'-'; + mask = mask<<1; + } + + if(mode & S_ISUID) str[3] = (mode & S_IXUSR)?'s':'S'; + if(mode & S_ISGID) str[6] = (mode & S_IXGRP)?'s':'S'; + if(mode & S_ISVTX) str[9] = (mode & S_IXOTH)?'t':'T'; + str[10] = '\0'; + return str; +} + +static inline void dump_stat(struct stat *st, const char *name) +{ + char str[20]; + char s[64], *p; + + if (st->st_mtime == (time_t)(-1)) /* some ctimes really hate -1 */ + st->st_mtime = 1; + + ctime_r((time_t *)&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */ + + if ((p = strchr(s,'\n')) != NULL) *p = '\0'; + if ((p = strchr(s,'\r')) != NULL) *p = '\0'; + +/* + printf("%6lo %s %8ld %s %s\n", st->st_mode, mkmodestr(st->st_mode, str), + st->st_size, s, name); +*/ + + printf(" %s %8ld %s %s", mkmodestr(st->st_mode,str), st->st_size, s, name); +} + +static inline u32 dump_inode(struct b_lists * pL, struct jffs2_raw_dirent *d, struct jffs2_raw_inode *i) +{ + char fname[256]; + struct stat st; + + if(!d || !i) return -1; + + strncpy(fname, (char *)d->name, d->nsize); + fname[d->nsize] = '\0'; + + memset(&st,0,sizeof(st)); + + st.st_mtime = i->mtime; + st.st_mode = i->mode; + st.st_ino = i->ino; + + /* neither dsize nor isize help us.. do it the long way */ + st.st_size = jffs2_1pass_read_inode(pL, i->ino, NULL); + + dump_stat(&st, fname); + + if (d->type == DT_LNK) { + unsigned char *src = (unsigned char *) (&i[1]); + putstr(" -> "); + putnstr(src, (int)i->dsize); + } + + putstr("\r\n"); + + return 0; +} + +/* list inodes with the given pino */ +static u32 +jffs2_1pass_list_inodes(struct b_lists * pL, u32 pino) +{ + struct b_node *b; + struct jffs2_raw_dirent *jDir; + + for (b = pL->dir.listHead; b; b = b->next) { + jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset); + if ((pino == jDir->pino) && (jDir->ino)) { /* ino=0 -> unlink */ + u32 i_version = 0; + struct jffs2_raw_inode ojNode; + struct jffs2_raw_inode *jNode, *i = NULL; + struct b_node *b2 = pL->frag.listHead; + + while (b2) { + jNode = (struct jffs2_raw_inode *) + get_fl_mem(b2->offset, sizeof(ojNode), &ojNode); + if (jNode->ino == jDir->ino && jNode->version >= i_version) { + if (i) + put_fl_mem(i); + + if (jDir->type == DT_LNK) + i = get_node_mem(b2->offset); + else + i = get_fl_mem(b2->offset, sizeof(*i), NULL); + } + b2 = b2->next; + } + + dump_inode(pL, jDir, i); + put_fl_mem(i); + } + put_fl_mem(jDir); + } + return pino; +} + +static u32 +jffs2_1pass_search_inode(struct b_lists * pL, const char *fname, u32 pino) +{ + int i; + char tmp[256]; + char working_tmp[256]; + char *c; + + /* discard any leading slash */ + i = 0; + while (fname[i] == '/') + i++; + strcpy(tmp, &fname[i]); + + while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */ + { + strncpy(working_tmp, tmp, c - tmp); + working_tmp[c - tmp] = '\0'; +#if 0 + putstr("search_inode: tmp = "); + putstr(tmp); + putstr("\r\n"); + putstr("search_inode: wtmp = "); + putstr(working_tmp); + putstr("\r\n"); + putstr("search_inode: c = "); + putstr(c); + putstr("\r\n"); +#endif + for (i = 0; i < strlen(c) - 1; i++) + tmp[i] = c[i + 1]; + tmp[i] = '\0'; +#if 0 + putstr("search_inode: post tmp = "); + putstr(tmp); + putstr("\r\n"); +#endif + + if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino))) { + putstr("find_inode failed for name="); + putstr(working_tmp); + putstr("\r\n"); + return 0; + } + } + /* this is for the bare filename, directories have already been mapped */ + if (!(pino = jffs2_1pass_find_inode(pL, tmp, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + return pino; + +} + +static u32 +jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino) +{ + struct b_node *b; + struct b_node *b2; + struct jffs2_raw_dirent *jDir; + struct jffs2_raw_inode *jNode; + u8 jDirFoundType = 0; + u32 jDirFoundIno = 0; + u32 jDirFoundPino = 0; + char tmp[256]; + u32 version = 0; + u32 pino; + unsigned char *src; + + /* we need to search all and return the inode with the highest version */ + for(b = pL->dir.listHead; b; b = b->next) { + jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset); + if (ino == jDir->ino) { + if (jDir->version < version) { + put_fl_mem(jDir); + continue; + } + + if (jDir->version == version && jDirFoundType) { + /* I'm pretty sure this isn't legal */ + putstr(" ** ERROR ** "); + putnstr(jDir->name, jDir->nsize); + putLabeledWord(" has dup version (resolve) = ", + version); + } + + jDirFoundType = jDir->type; + jDirFoundIno = jDir->ino; + jDirFoundPino = jDir->pino; + version = jDir->version; + } + put_fl_mem(jDir); + } + /* now we found the right entry again. (shoulda returned inode*) */ + if (jDirFoundType != DT_LNK) + return jDirFoundIno; + + /* it's a soft link so we follow it again. */ + b2 = pL->frag.listHead; + while (b2) { + jNode = (struct jffs2_raw_inode *) get_node_mem(b2->offset); + if (jNode->ino == jDirFoundIno) { + src = (unsigned char *)jNode + sizeof(struct jffs2_raw_inode); + +#if 0 + putLabeledWord("\t\t dsize = ", jNode->dsize); + putstr("\t\t target = "); + putnstr(src, jNode->dsize); + putstr("\r\n"); +#endif + strncpy(tmp, (char *)src, jNode->dsize); + tmp[jNode->dsize] = '\0'; + put_fl_mem(jNode); + break; + } + b2 = b2->next; + put_fl_mem(jNode); + } + /* ok so the name of the new file to find is in tmp */ + /* if it starts with a slash it is root based else shared dirs */ + if (tmp[0] == '/') + pino = 1; + else + pino = jDirFoundPino; + + return jffs2_1pass_search_inode(pL, tmp, pino); +} + +static u32 +jffs2_1pass_search_list_inodes(struct b_lists * pL, const char *fname, u32 pino) +{ + int i; + char tmp[256]; + char working_tmp[256]; + char *c; + + /* discard any leading slash */ + i = 0; + while (fname[i] == '/') + i++; + strcpy(tmp, &fname[i]); + working_tmp[0] = '\0'; + while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */ + { + strncpy(working_tmp, tmp, c - tmp); + working_tmp[c - tmp] = '\0'; + for (i = 0; i < strlen(c) - 1; i++) + tmp[i] = c[i + 1]; + tmp[i] = '\0'; + /* only a failure if we arent looking at top level */ + if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino)) && + (working_tmp[0])) { + putstr("find_inode failed for name="); + putstr(working_tmp); + putstr("\r\n"); + return 0; + } + } + + if (tmp[0] && !(pino = jffs2_1pass_find_inode(pL, tmp, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + /* this is for the bare filename, directories have already been mapped */ + if (!(pino = jffs2_1pass_list_inodes(pL, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + return pino; + +} + +unsigned char +jffs2_1pass_rescan_needed(struct part_info *part) +{ + struct b_node *b; + struct jffs2_unknown_node onode; + struct jffs2_unknown_node *node; + struct b_lists *pL = (struct b_lists *)part->jffs2_priv; + + if (part->jffs2_priv == 0){ + DEBUGF ("rescan: First time in use\n"); + return 1; + } + + /* if we have no list, we need to rescan */ + if (pL->frag.listCount == 0) { + DEBUGF ("rescan: fraglist zero\n"); + return 1; + } + + /* but suppose someone reflashed a partition at the same offset... */ + b = pL->dir.listHead; + while (b) { + node = (struct jffs2_unknown_node *) get_fl_mem(b->offset, + sizeof(onode), &onode); + if (node->nodetype != JFFS2_NODETYPE_DIRENT) { + DEBUGF ("rescan: fs changed beneath me? (%lx)\n", + (unsigned long) b->offset); + return 1; + } + b = b->next; + } + return 0; +} + +#ifdef DEBUG_FRAGMENTS +static void +dump_fragments(struct b_lists *pL) +{ + struct b_node *b; + struct jffs2_raw_inode ojNode; + struct jffs2_raw_inode *jNode; + + putstr("\r\n\r\n******The fragment Entries******\r\n"); + b = pL->frag.listHead; + while (b) { + jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset, + sizeof(ojNode), &ojNode); + putLabeledWord("\r\n\tbuild_list: FLASH_OFFSET = ", b->offset); + putLabeledWord("\tbuild_list: totlen = ", jNode->totlen); + putLabeledWord("\tbuild_list: inode = ", jNode->ino); + putLabeledWord("\tbuild_list: version = ", jNode->version); + putLabeledWord("\tbuild_list: isize = ", jNode->isize); + putLabeledWord("\tbuild_list: atime = ", jNode->atime); + putLabeledWord("\tbuild_list: offset = ", jNode->offset); + putLabeledWord("\tbuild_list: csize = ", jNode->csize); + putLabeledWord("\tbuild_list: dsize = ", jNode->dsize); + putLabeledWord("\tbuild_list: compr = ", jNode->compr); + putLabeledWord("\tbuild_list: usercompr = ", jNode->usercompr); + putLabeledWord("\tbuild_list: flags = ", jNode->flags); + putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ + b = b->next; + } +} +#endif + +#ifdef DEBUG_DIRENTS +static void +dump_dirents(struct b_lists *pL) +{ + struct b_node *b; + struct jffs2_raw_dirent *jDir; + + putstr("\r\n\r\n******The directory Entries******\r\n"); + b = pL->dir.listHead; + while (b) { + jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset); + putstr("\r\n"); + putnstr(jDir->name, jDir->nsize); + putLabeledWord("\r\n\tbuild_list: magic = ", jDir->magic); + putLabeledWord("\tbuild_list: nodetype = ", jDir->nodetype); + putLabeledWord("\tbuild_list: hdr_crc = ", jDir->hdr_crc); + putLabeledWord("\tbuild_list: pino = ", jDir->pino); + putLabeledWord("\tbuild_list: version = ", jDir->version); + putLabeledWord("\tbuild_list: ino = ", jDir->ino); + putLabeledWord("\tbuild_list: mctime = ", jDir->mctime); + putLabeledWord("\tbuild_list: nsize = ", jDir->nsize); + putLabeledWord("\tbuild_list: type = ", jDir->type); + putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc); + putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc); + putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ + b = b->next; + put_fl_mem(jDir); + } +} +#endif + +static u32 +jffs2_1pass_build_lists(struct part_info * part) +{ + struct b_lists *pL; + struct jffs2_unknown_node *node; + u32 offset, oldoffset = 0; + u32 max = part->size - sizeof(struct jffs2_raw_inode); + u32 counter = 0; + u32 counter4 = 0; + u32 counterF = 0; + u32 counterN = 0; + + /* turn off the lcd. Refreshing the lcd adds 50% overhead to the */ + /* jffs2 list building enterprise nope. in newer versions the overhead is */ + /* only about 5 %. not enough to inconvenience people for. */ + /* lcd_off(); */ + + /* if we are building a list we need to refresh the cache. */ + jffs_init_1pass_list(part); + pL = (struct b_lists *)part->jffs2_priv; + offset = 0; + puts ("Scanning JFFS2 FS: "); + + /* start at the beginning of the partition */ + while (offset < max) { + if ((oldoffset >> SPIN_BLKSIZE) != (offset >> SPIN_BLKSIZE)) { + printf("\b\b%c ", spinner[counter++ % sizeof(spinner)]); + oldoffset = offset; + } + + node = (struct jffs2_unknown_node *) get_node_mem((u32)part->offset + offset); + if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) { + /* if its a fragment add it */ + if (node->nodetype == JFFS2_NODETYPE_INODE && + inode_crc((struct jffs2_raw_inode *) node)) { + if (insert_node(&pL->frag, (u32) part->offset + + offset) == NULL) { + put_fl_mem(node); + return 0; + } + } else if (node->nodetype == JFFS2_NODETYPE_DIRENT && + dirent_crc((struct jffs2_raw_dirent *) node) && + dirent_name_crc((struct jffs2_raw_dirent *) node)) { + if (! (counterN%100)) + puts ("\b\b. "); + if (insert_node(&pL->dir, (u32) part->offset + + offset) == NULL) { + put_fl_mem(node); + return 0; + } + counterN++; + } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) { + if (node->totlen != sizeof(struct jffs2_unknown_node)) + printf("OOPS Cleanmarker has bad size " + "%d != %d\n", node->totlen, + sizeof(struct jffs2_unknown_node)); + } else if (node->nodetype == JFFS2_NODETYPE_PADDING) { + if (node->totlen < sizeof(struct jffs2_unknown_node)) + printf("OOPS Padding has bad size " + "%d < %d\n", node->totlen, + sizeof(struct jffs2_unknown_node)); + } else { + printf("Unknown node type: %x len %d " + "offset 0x%x\n", node->nodetype, + node->totlen, offset); + } + offset += ((node->totlen + 3) & ~3); + counterF++; + } else if (node->magic == JFFS2_EMPTY_BITMASK && + node->nodetype == JFFS2_EMPTY_BITMASK) { + offset = jffs2_scan_empty(offset, part); + } else { /* if we know nothing, we just step and look. */ + offset += 4; + counter4++; + } +/* printf("unknown node magic %4.4x %4.4x @ %lx\n", node->magic, node->nodetype, (unsigned long)node); */ + put_fl_mem(node); + } + + putstr("\b\b done.\r\n"); /* close off the dots */ + /* turn the lcd back on. */ + /* splash(); */ + +#if 0 + putLabeledWord("dir entries = ", pL->dir.listCount); + putLabeledWord("frag entries = ", pL->frag.listCount); + putLabeledWord("+4 increments = ", counter4); + putLabeledWord("+file_offset increments = ", counterF); + +#endif + +#ifdef DEBUG_DIRENTS + dump_dirents(pL); +#endif + +#ifdef DEBUG_FRAGMENTS + dump_fragments(pL); +#endif + + /* give visual feedback that we are done scanning the flash */ + led_blink(0x0, 0x0, 0x1, 0x1); /* off, forever, on 100ms, off 100ms */ + return 1; +} + + +static u32 +jffs2_1pass_fill_info(struct b_lists * pL, struct b_jffs2_info * piL) +{ + struct b_node *b; + struct jffs2_raw_inode ojNode; + struct jffs2_raw_inode *jNode; + int i; + + for (i = 0; i < JFFS2_NUM_COMPR; i++) { + piL->compr_info[i].num_frags = 0; + piL->compr_info[i].compr_sum = 0; + piL->compr_info[i].decompr_sum = 0; + } + + b = pL->frag.listHead; + while (b) { + jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset, + sizeof(ojNode), &ojNode); + if (jNode->compr < JFFS2_NUM_COMPR) { + piL->compr_info[jNode->compr].num_frags++; + piL->compr_info[jNode->compr].compr_sum += jNode->csize; + piL->compr_info[jNode->compr].decompr_sum += jNode->dsize; + } + b = b->next; + } + return 0; +} + + +static struct b_lists * +jffs2_get_list(struct part_info * part, const char *who) +{ + /* copy requested part_info struct pointer to global location */ + current_part = part; + + if (jffs2_1pass_rescan_needed(part)) { + if (!jffs2_1pass_build_lists(part)) { + printf("%s: Failed to scan JFFSv2 file structure\n", who); + return NULL; + } + } + return (struct b_lists *)part->jffs2_priv; +} + + +/* Print directory / file contents */ +u32 +jffs2_1pass_ls(struct part_info * part, const char *fname) +{ + struct b_lists *pl; + long ret = 1; + u32 inode; + + if (! (pl = jffs2_get_list(part, "ls"))) + return 0; + + if (! (inode = jffs2_1pass_search_list_inodes(pl, fname, 1))) { + putstr("ls: Failed to scan jffs2 file structure\r\n"); + return 0; + } + + +#if 0 + putLabeledWord("found file at inode = ", inode); + putLabeledWord("read_inode returns = ", ret); +#endif + + return ret; +} + + +/* Load a file from flash into memory. fname can be a full path */ +u32 +jffs2_1pass_load(char *dest, struct part_info * part, const char *fname) +{ + + struct b_lists *pl; + long ret = 1; + u32 inode; + + if (! (pl = jffs2_get_list(part, "load"))) + return 0; + + if (! (inode = jffs2_1pass_search_inode(pl, fname, 1))) { + putstr("load: Failed to find inode\r\n"); + return 0; + } + + /* Resolve symlinks */ + if (! (inode = jffs2_1pass_resolve_inode(pl, inode))) { + putstr("load: Failed to resolve inode structure\r\n"); + return 0; + } + + if ((ret = jffs2_1pass_read_inode(pl, inode, dest)) < 0) { + putstr("load: Failed to read inode\r\n"); + return 0; + } + + DEBUGF ("load: loaded '%s' to 0x%lx (%ld bytes)\n", fname, + (unsigned long) dest, ret); + return ret; +} + +/* Return information about the fs on this partition */ +u32 +jffs2_1pass_info(struct part_info * part) +{ + struct b_jffs2_info info; + struct b_lists *pl; + int i; + + if (! (pl = jffs2_get_list(part, "info"))) + return 0; + + jffs2_1pass_fill_info(pl, &info); + for (i = 0; i < JFFS2_NUM_COMPR; i++) { + printf ("Compression: %s\n" + "\tfrag count: %d\n" + "\tcompressed sum: %d\n" + "\tuncompressed sum: %d\n", + compr_names[i], + info.compr_info[i].num_frags, + info.compr_info[i].compr_sum, + info.compr_info[i].decompr_sum); + } + return 1; +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/jffs2_private.h b/fs/jffs2/jffs2_private.h new file mode 100644 index 0000000..65ca6eb --- /dev/null +++ b/fs/jffs2/jffs2_private.h @@ -0,0 +1,88 @@ +#ifndef jffs2_private_h +#define jffs2_private_h + +#include + + +struct b_node { + u32 offset; + struct b_node *next; +}; + +struct b_list { + struct b_node *listTail; + struct b_node *listHead; +#ifdef CFG_JFFS2_SORT_FRAGMENTS + struct b_node *listLast; + int (*listCompare)(struct b_node *new, struct b_node *node); + u32 listLoops; +#endif + u32 listCount; + struct mem_block *listMemBase; +}; + +struct b_lists { + struct b_list dir; + struct b_list frag; + +}; + +struct b_compr_info { + u32 num_frags; + u32 compr_sum; + u32 decompr_sum; +}; + +struct b_jffs2_info { + struct b_compr_info compr_info[JFFS2_NUM_COMPR]; +}; + +static inline int +hdr_crc(struct jffs2_unknown_node *node) +{ +#if 1 + u32 crc = crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4); +#else + /* what's the semantics of this? why is this here? */ + u32 crc = crc32_no_comp(~0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4); + + crc ^= ~0; +#endif + if (node->hdr_crc != crc) { + return 0; + } else { + return 1; + } +} + +static inline int +dirent_crc(struct jffs2_raw_dirent *node) +{ + if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_dirent) - 8)) { + return 0; + } else { + return 1; + } +} + +static inline int +dirent_name_crc(struct jffs2_raw_dirent *node) +{ + if (node->name_crc != crc32_no_comp(0, (unsigned char *)&(node->name), node->nsize)) { + return 0; + } else { + return 1; + } +} + +static inline int +inode_crc(struct jffs2_raw_inode *node) +{ + if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_inode) - 8)) { + return 0; + } else { + return 1; + } +} + +#endif /* jffs2_private.h */ diff --git a/fs/jffs2/mini_inflate.c b/fs/jffs2/mini_inflate.c new file mode 100644 index 0000000..4f511ec --- /dev/null +++ b/fs/jffs2/mini_inflate.c @@ -0,0 +1,396 @@ +/*------------------------------------------------------------------------- + * Filename: mini_inflate.c + * Version: $Id: mini_inflate.c,v 1.3 2002/01/24 22:58:42 rfeany Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: Mini inflate implementation (RFC 1951) + *-----------------------------------------------------------------------*/ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include + +/* The order that the code lengths in section 3.2.7 are in */ +static unsigned char huffman_order[] = {16, 17, 18, 0, 8, 7, 9, 6, 10, 5, + 11, 4, 12, 3, 13, 2, 14, 1, 15}; + +inline void cramfs_memset(int *s, const int c, size n) +{ + n--; + for (;n > 0; n--) s[n] = c; + s[0] = c; +} + +/* associate a stream with a block of data and reset the stream */ +static void init_stream(struct bitstream *stream, unsigned char *data, + void *(*inflate_memcpy)(void *, const void *, size)) +{ + stream->error = NO_ERROR; + stream->memcpy = inflate_memcpy; + stream->decoded = 0; + stream->data = data; + stream->bit = 0; /* The first bit of the stream is the lsb of the + * first byte */ + + /* really sorry about all this initialization, think of a better way, + * let me know and it will get cleaned up */ + stream->codes.bits = 8; + stream->codes.num_symbols = 19; + stream->codes.lengths = stream->code_lengths; + stream->codes.symbols = stream->code_symbols; + stream->codes.count = stream->code_count; + stream->codes.first = stream->code_first; + stream->codes.pos = stream->code_pos; + + stream->lengths.bits = 16; + stream->lengths.num_symbols = 288; + stream->lengths.lengths = stream->length_lengths; + stream->lengths.symbols = stream->length_symbols; + stream->lengths.count = stream->length_count; + stream->lengths.first = stream->length_first; + stream->lengths.pos = stream->length_pos; + + stream->distance.bits = 16; + stream->distance.num_symbols = 32; + stream->distance.lengths = stream->distance_lengths; + stream->distance.symbols = stream->distance_symbols; + stream->distance.count = stream->distance_count; + stream->distance.first = stream->distance_first; + stream->distance.pos = stream->distance_pos; + +} + +/* pull 'bits' bits out of the stream. The last bit pulled it returned as the + * msb. (section 3.1.1) + */ +inline unsigned long pull_bits(struct bitstream *stream, + const unsigned int bits) +{ + unsigned long ret; + int i; + + ret = 0; + for (i = 0; i < bits; i++) { + ret += ((*(stream->data) >> stream->bit) & 1) << i; + + /* if, before incrementing, we are on bit 7, + * go to the lsb of the next byte */ + if (stream->bit++ == 7) { + stream->bit = 0; + stream->data++; + } + } + return ret; +} + +inline int pull_bit(struct bitstream *stream) +{ + int ret = ((*(stream->data) >> stream->bit) & 1); + if (stream->bit++ == 7) { + stream->bit = 0; + stream->data++; + } + return ret; +} + +/* discard bits up to the next whole byte */ +static void discard_bits(struct bitstream *stream) +{ + if (stream->bit != 0) { + stream->bit = 0; + stream->data++; + } +} + +/* No decompression, the data is all literals (section 3.2.4) */ +static void decompress_none(struct bitstream *stream, unsigned char *dest) +{ + unsigned int length; + + discard_bits(stream); + length = *(stream->data++); + length += *(stream->data++) << 8; + pull_bits(stream, 16); /* throw away the inverse of the size */ + + stream->decoded += length; + stream->memcpy(dest, stream->data, length); + stream->data += length; +} + +/* Read in a symbol from the stream (section 3.2.2) */ +static int read_symbol(struct bitstream *stream, struct huffman_set *set) +{ + int bits = 0; + int code = 0; + while (!(set->count[bits] && code < set->first[bits] + + set->count[bits])) { + code = (code << 1) + pull_bit(stream); + if (++bits > set->bits) { + /* error decoding (corrupted data?) */ + stream->error = CODE_NOT_FOUND; + return -1; + } + } + return set->symbols[set->pos[bits] + code - set->first[bits]]; +} + +/* decompress a stream of data encoded with the passed length and distance + * huffman codes */ +static void decompress_huffman(struct bitstream *stream, unsigned char *dest) +{ + struct huffman_set *lengths = &(stream->lengths); + struct huffman_set *distance = &(stream->distance); + + int symbol, length, dist, i; + + do { + if ((symbol = read_symbol(stream, lengths)) < 0) return; + if (symbol < 256) { + *(dest++) = symbol; /* symbol is a literal */ + stream->decoded++; + } else if (symbol > 256) { + /* Determine the length of the repitition + * (section 3.2.5) */ + if (symbol < 265) length = symbol - 254; + else if (symbol == 285) length = 258; + else { + length = pull_bits(stream, (symbol - 261) >> 2); + length += (4 << ((symbol - 261) >> 2)) + 3; + length += ((symbol - 1) % 4) << + ((symbol - 261) >> 2); + } + + /* Determine how far back to go */ + if ((symbol = read_symbol(stream, distance)) < 0) + return; + if (symbol < 4) dist = symbol + 1; + else { + dist = pull_bits(stream, (symbol - 2) >> 1); + dist += (2 << ((symbol - 2) >> 1)) + 1; + dist += (symbol % 2) << ((symbol - 2) >> 1); + } + stream->decoded += length; + for (i = 0; i < length; i++) { + *dest = dest[-dist]; + dest++; + } + } + } while (symbol != 256); /* 256 is the end of the data block */ +} + +/* Fill the lookup tables (section 3.2.2) */ +static void fill_code_tables(struct huffman_set *set) +{ + int code = 0, i, length; + + /* fill in the first code of each bit length, and the pos pointer */ + set->pos[0] = 0; + for (i = 1; i < set->bits; i++) { + code = (code + set->count[i - 1]) << 1; + set->first[i] = code; + set->pos[i] = set->pos[i - 1] + set->count[i - 1]; + } + + /* Fill in the table of symbols in order of their huffman code */ + for (i = 0; i < set->num_symbols; i++) { + if ((length = set->lengths[i])) + set->symbols[set->pos[length]++] = i; + } + + /* reset the pos pointer */ + for (i = 1; i < set->bits; i++) set->pos[i] -= set->count[i]; +} + +static void init_code_tables(struct huffman_set *set) +{ + cramfs_memset(set->lengths, 0, set->num_symbols); + cramfs_memset(set->count, 0, set->bits); + cramfs_memset(set->first, 0, set->bits); +} + +/* read in the huffman codes for dynamic decoding (section 3.2.7) */ +static void decompress_dynamic(struct bitstream *stream, unsigned char *dest) +{ + /* I tried my best to minimize the memory footprint here, while still + * keeping up performance. I really dislike the _lengths[] tables, but + * I see no way of eliminating them without a sizable performance + * impact. The first struct table keeps track of stats on each bit + * length. The _length table keeps a record of the bit length of each + * symbol. The _symbols table is for looking up symbols by the huffman + * code (the pos element points to the first place in the symbol table + * where that bit length occurs). I also hate the initization of these + * structs, if someone knows how to compact these, lemme know. */ + + struct huffman_set *codes = &(stream->codes); + struct huffman_set *lengths = &(stream->lengths); + struct huffman_set *distance = &(stream->distance); + + int hlit = pull_bits(stream, 5) + 257; + int hdist = pull_bits(stream, 5) + 1; + int hclen = pull_bits(stream, 4) + 4; + int length, curr_code, symbol, i, last_code; + + last_code = 0; + + init_code_tables(codes); + init_code_tables(lengths); + init_code_tables(distance); + + /* fill in the count of each bit length' as well as the lengths + * table */ + for (i = 0; i < hclen; i++) { + length = pull_bits(stream, 3); + codes->lengths[huffman_order[i]] = length; + if (length) codes->count[length]++; + + } + fill_code_tables(codes); + + /* Do the same for the length codes, being carefull of wrap through + * to the distance table */ + curr_code = 0; + while (curr_code < hlit) { + if ((symbol = read_symbol(stream, codes)) < 0) return; + if (symbol == 0) { + curr_code++; + last_code = 0; + } else if (symbol < 16) { /* Literal length */ + lengths->lengths[curr_code] = last_code = symbol; + lengths->count[symbol]++; + curr_code++; + } else if (symbol == 16) { /* repeat the last symbol 3 - 6 + * times */ + length = 3 + pull_bits(stream, 2); + for (;length; length--, curr_code++) + if (curr_code < hlit) { + lengths->lengths[curr_code] = + last_code; + lengths->count[last_code]++; + } else { /* wrap to the distance table */ + distance->lengths[curr_code - hlit] = + last_code; + distance->count[last_code]++; + } + } else if (symbol == 17) { /* repeat a bit length 0 */ + curr_code += 3 + pull_bits(stream, 3); + last_code = 0; + } else { /* same, but more times */ + curr_code += 11 + pull_bits(stream, 7); + last_code = 0; + } + } + fill_code_tables(lengths); + + /* Fill the distance table, don't need to worry about wrapthrough + * here */ + curr_code -= hlit; + while (curr_code < hdist) { + if ((symbol = read_symbol(stream, codes)) < 0) return; + if (symbol == 0) { + curr_code++; + last_code = 0; + } else if (symbol < 16) { + distance->lengths[curr_code] = last_code = symbol; + distance->count[symbol]++; + curr_code++; + } else if (symbol == 16) { + length = 3 + pull_bits(stream, 2); + for (;length; length--, curr_code++) { + distance->lengths[curr_code] = + last_code; + distance->count[last_code]++; + } + } else if (symbol == 17) { + curr_code += 3 + pull_bits(stream, 3); + last_code = 0; + } else { + curr_code += 11 + pull_bits(stream, 7); + last_code = 0; + } + } + fill_code_tables(distance); + + decompress_huffman(stream, dest); +} + +/* fill in the length and distance huffman codes for fixed encoding + * (section 3.2.6) */ +static void decompress_fixed(struct bitstream *stream, unsigned char *dest) +{ + /* let gcc fill in the initial values */ + struct huffman_set *lengths = &(stream->lengths); + struct huffman_set *distance = &(stream->distance); + + cramfs_memset(lengths->count, 0, 16); + cramfs_memset(lengths->first, 0, 16); + cramfs_memset(lengths->lengths, 8, 144); + cramfs_memset(lengths->lengths + 144, 9, 112); + cramfs_memset(lengths->lengths + 256, 7, 24); + cramfs_memset(lengths->lengths + 280, 8, 8); + lengths->count[7] = 24; + lengths->count[8] = 152; + lengths->count[9] = 112; + + cramfs_memset(distance->count, 0, 16); + cramfs_memset(distance->first, 0, 16); + cramfs_memset(distance->lengths, 5, 32); + distance->count[5] = 32; + + + fill_code_tables(lengths); + fill_code_tables(distance); + + + decompress_huffman(stream, dest); +} + +/* returns the number of bytes decoded, < 0 if there was an error. Note that + * this function assumes that the block starts on a byte boundry + * (non-compliant, but I don't see where this would happen). section 3.2.3 */ +long decompress_block(unsigned char *dest, unsigned char *source, + void *(*inflate_memcpy)(void *, const void *, size)) +{ + int bfinal, btype; + struct bitstream stream; + + init_stream(&stream, source, inflate_memcpy); + do { + bfinal = pull_bit(&stream); + btype = pull_bits(&stream, 2); + if (btype == NO_COMP) decompress_none(&stream, dest + stream.decoded); + else if (btype == DYNAMIC_COMP) + decompress_dynamic(&stream, dest + stream.decoded); + else if (btype == FIXED_COMP) decompress_fixed(&stream, dest + stream.decoded); + else stream.error = COMP_UNKNOWN; + } while (!bfinal && !stream.error); + +#if 0 + putstr("decompress_block start\r\n"); + putLabeledWord("stream.error = ",stream.error); + putLabeledWord("stream.decoded = ",stream.decoded); + putLabeledWord("dest = ",dest); + putstr("decompress_block end\r\n"); +#endif + return stream.error ? -stream.error : stream.decoded; +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/reiserfs/Makefile b/fs/reiserfs/Makefile new file mode 100644 index 0000000..98a9a8d --- /dev/null +++ b/fs/reiserfs/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2003 +# Pavel Bartusek, Sysgo Real-Time Solutions AG, pba@sysgo.de +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libreiserfs.a + +AOBJS = +COBJS = reiserfs.o dev.o mode_string.o +OBJS = $(AOBJS) $(COBJS) + +#CPPFLAGS += + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/fs/reiserfs/dev.c b/fs/reiserfs/dev.c new file mode 100644 index 0000000..6f6056f --- /dev/null +++ b/fs/reiserfs/dev.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2003 - 2004 + * Sysgo AG, , Pavel Bartusek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +#include +#if (CONFIG_COMMANDS & CFG_CMD_REISER) + +#include +#include + +#include "reiserfs_private.h" + +static block_dev_desc_t *reiserfs_block_dev_desc; +static disk_partition_t part_info; + + +int reiserfs_set_blk_dev(block_dev_desc_t *rbdd, int part) +{ + reiserfs_block_dev_desc = rbdd; + + if (part == 0) { + /* disk doesn't use partition table */ + part_info.start = 0; + part_info.size = rbdd->lba; + part_info.blksz = rbdd->blksz; + } else { + if (get_partition_info (reiserfs_block_dev_desc, part, &part_info)) { + return 0; + } + } + return (part_info.size); +} + + +int reiserfs_devread (int sector, int byte_offset, int byte_len, char *buf) +{ + char sec_buf[SECTOR_SIZE]; + unsigned block_len; +/* + unsigned len = byte_len; + u8 *start = buf; +*/ + /* + * Check partition boundaries + */ + if (sector < 0 + || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) + >= part_info.size)) { +/* errnum = ERR_OUTSIDE_PART; */ + printf (" ** reiserfs_devread() read outside partition\n"); + return 0; + } + + /* + * Get the read to the beginning of a partition. + */ + sector += byte_offset >> SECTOR_BITS; + byte_offset &= SECTOR_SIZE - 1; + +#if defined(DEBUG) + printf (" <%d, %d, %d> ", sector, byte_offset, byte_len); +#endif + + + if (reiserfs_block_dev_desc == NULL) + return 0; + + + if (byte_offset != 0) { + /* read first part which isn't aligned with start of sector */ + if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev, + part_info.start+sector, 1, (unsigned long *)sec_buf) != 1) { + printf (" ** reiserfs_devread() read error\n"); + return 0; + } + memcpy(buf, sec_buf+byte_offset, min(SECTOR_SIZE-byte_offset, byte_len)); + buf+=min(SECTOR_SIZE-byte_offset, byte_len); + byte_len-=min(SECTOR_SIZE-byte_offset, byte_len); + sector++; + } + + /* read sector aligned part */ + block_len = byte_len & ~(SECTOR_SIZE-1); + if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev, + part_info.start+sector, block_len/SECTOR_SIZE, (unsigned long *)buf) != + block_len/SECTOR_SIZE) { + printf (" ** reiserfs_devread() read error - block\n"); + return 0; + } + buf+=block_len; + byte_len-=block_len; + sector+= block_len/SECTOR_SIZE; + + if ( byte_len != 0 ) { + /* read rest of data which are not in whole sector */ + if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev, + part_info.start+sector, 1, (unsigned long *)sec_buf) != 1) { + printf (" ** reiserfs_devread() read error - last part\n"); + return 0; + } + memcpy(buf, sec_buf, byte_len); + } + + return 1; +} + +#endif /* CFG_CMD_REISERFS */ diff --git a/fs/reiserfs/mode_string.c b/fs/reiserfs/mode_string.c new file mode 100644 index 0000000..bc565fb --- /dev/null +++ b/fs/reiserfs/mode_string.c @@ -0,0 +1,142 @@ +/* vi: set sw=4 ts=4: */ +/* + * mode_string implementation for busybox + * + * Copyright (C) 2003 Manuel Novoa III + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/* Aug 13, 2003 + * Fix a bug reported by junkio@cox.net involving the mode_chars index. + */ + + +#include +#if (CONFIG_COMMANDS & CFG_CMD_REISER) +#include + +#if ( S_ISUID != 04000 ) || ( S_ISGID != 02000 ) || ( S_ISVTX != 01000 ) \ + || ( S_IRUSR != 00400 ) || ( S_IWUSR != 00200 ) || ( S_IXUSR != 00100 ) \ + || ( S_IRGRP != 00040 ) || ( S_IWGRP != 00020 ) || ( S_IXGRP != 00010 ) \ + || ( S_IROTH != 00004 ) || ( S_IWOTH != 00002 ) || ( S_IXOTH != 00001 ) +#error permission bitflag value assumption(s) violated! +#endif + +#if ( S_IFSOCK!= 0140000 ) || ( S_IFLNK != 0120000 ) \ + || ( S_IFREG != 0100000 ) || ( S_IFBLK != 0060000 ) \ + || ( S_IFDIR != 0040000 ) || ( S_IFCHR != 0020000 ) \ + || ( S_IFIFO != 0010000 ) +#warning mode type bitflag value assumption(s) violated! falling back to larger version + +#if (S_IRWXU | S_IRWXG | S_IRWXO | S_ISUID | S_ISGID | S_ISVTX) == 07777 +#undef mode_t +#define mode_t unsigned short +#endif + +static const mode_t mode_flags[] = { + S_IRUSR, S_IWUSR, S_IXUSR, S_ISUID, + S_IRGRP, S_IWGRP, S_IXGRP, S_ISGID, + S_IROTH, S_IWOTH, S_IXOTH, S_ISVTX +}; + +/* The static const char arrays below are duplicated for the two cases + * because moving them ahead of the mode_flags declaration cause a text + * size increase with the gcc version I'm using. */ + +/* The previous version used "0pcCd?bB-?l?s???". However, the '0', 'C', + * and 'B' types don't appear to be available on linux. So I removed them. */ +static const char type_chars[16] = "?pc?d?b?-?l?s???"; +/* 0123456789abcdef */ +static const char mode_chars[7] = "rwxSTst"; + +const char *bb_mode_string(int mode) +{ + static char buf[12]; + char *p = buf; + + int i, j, k; + + *p = type_chars[ (mode >> 12) & 0xf ]; + i = 0; + do { + j = k = 0; + do { + *++p = '-'; + if (mode & mode_flags[i+j]) { + *p = mode_chars[j]; + k = j; + } + } while (++j < 3); + if (mode & mode_flags[i+j]) { + *p = mode_chars[3 + (k & 2) + ((i&8) >> 3)]; + } + i += 4; + } while (i < 12); + + /* Note: We don't bother with nul termination because bss initialization + * should have taken care of that for us. If the user scribbled in buf + * memory, they deserve whatever happens. But we'll at least assert. */ + if (buf[10] != 0) return NULL; + + return buf; +} + +#else + +/* The previous version used "0pcCd?bB-?l?s???". However, the '0', 'C', + * and 'B' types don't appear to be available on linux. So I removed them. */ +static const char type_chars[16] = "?pc?d?b?-?l?s???"; +/* 0123456789abcdef */ +static const char mode_chars[7] = "rwxSTst"; + +const char *bb_mode_string(int mode) +{ + static char buf[12]; + char *p = buf; + + int i, j, k, m; + + *p = type_chars[ (mode >> 12) & 0xf ]; + i = 0; + m = 0400; + do { + j = k = 0; + do { + *++p = '-'; + if (mode & m) { + *p = mode_chars[j]; + k = j; + } + m >>= 1; + } while (++j < 3); + ++i; + if (mode & (010000 >> i)) { + *p = mode_chars[3 + (k & 2) + (i == 3)]; + } + } while (i < 3); + + /* Note: We don't bother with nul termination because bss initialization + * should have taken care of that for us. If the user scribbled in buf + * memory, they deserve whatever happens. But we'll at least assert. */ + if (buf[10] != 0) return NULL; + + return buf; +} + +#endif + +#endif /* CFG_CMD_REISER */ diff --git a/fs/reiserfs/reiserfs.c b/fs/reiserfs/reiserfs.c new file mode 100644 index 0000000..31c25eb --- /dev/null +++ b/fs/reiserfs/reiserfs.c @@ -0,0 +1,986 @@ +/* + * Copyright 2000-2002 by Hans Reiser, licensing governed by reiserfs/README + * + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2000, 2001 Free Software Foundation, Inc. + * + * (C) Copyright 2003 - 2004 + * Sysgo AG, , Pavel Bartusek + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* An implementation for the ReiserFS filesystem ported from GRUB. + * Some parts of this code (mainly the structures and defines) are + * from the original reiser fs code, as found in the linux kernel. + */ + +#include +#if (CONFIG_COMMANDS & CFG_CMD_REISER) + +#include +#include +#include +#include +#include + +#include "reiserfs_private.h" + +#undef REISERDEBUG + +/* Some parts of this code (mainly the structures and defines) are + * from the original reiser fs code, as found in the linux kernel. + */ + +static char fsys_buf[FSYS_BUFLEN]; +static reiserfs_error_t errnum = ERR_NONE; +static int print_possibilities; +static unsigned int filepos, filemax; + +static int +substring (const char *s1, const char *s2) +{ + while (*s1 == *s2) + { + /* The strings match exactly. */ + if (! *(s1++)) + return 0; + s2 ++; + } + + /* S1 is a substring of S2. */ + if (*s1 == 0) + return -1; + + /* S1 isn't a substring. */ + return 1; +} + +static void sd_print_item (struct item_head * ih, char * item) +{ + char filetime[30]; + time_t ttime; + + if (stat_data_v1 (ih)) { + struct stat_data_v1 * sd = (struct stat_data_v1 *)item; + ttime = sd_v1_mtime(sd); + ctime_r(&ttime, filetime); + printf ("%-10s %4hd %6d %6d %9d %24.24s", + bb_mode_string(sd_v1_mode(sd)), sd_v1_nlink(sd),sd_v1_uid(sd), sd_v1_gid(sd), + sd_v1_size(sd), filetime); + } else { + struct stat_data * sd = (struct stat_data *)item; + ttime = sd_v2_mtime(sd); + ctime_r(&ttime, filetime); + printf ("%-10s %4d %6d %6d %9d %24.24s", + bb_mode_string(sd_v2_mode(sd)), sd_v2_nlink(sd),sd_v2_uid(sd),sd_v2_gid(sd), + (__u32) sd_v2_size(sd), filetime); + } +} + +static int +journal_read (int block, int len, char *buffer) +{ + return reiserfs_devread ((INFO->journal_block + block) << INFO->blocksize_shift, + 0, len, buffer); +} + +/* Read a block from ReiserFS file system, taking the journal into + * account. If the block nr is in the journal, the block from the + * journal taken. + */ +static int +block_read (unsigned int blockNr, int start, int len, char *buffer) +{ + int transactions = INFO->journal_transactions; + int desc_block = INFO->journal_first_desc; + int journal_mask = INFO->journal_block_count - 1; + int translatedNr = blockNr; + __u32 *journal_table = JOURNAL_START; + while (transactions-- > 0) + { + int i = 0; + int j_len; + if (__le32_to_cpu(*journal_table) != 0xffffffff) + { + /* Search for the blockNr in cached journal */ + j_len = __le32_to_cpu(*journal_table++); + while (i++ < j_len) + { + if (__le32_to_cpu(*journal_table++) == blockNr) + { + journal_table += j_len - i; + goto found; + } + } + } + else + { + /* This is the end of cached journal marker. The remaining + * transactions are still on disk. + */ + struct reiserfs_journal_desc desc; + struct reiserfs_journal_commit commit; + + if (! journal_read (desc_block, sizeof (desc), (char *) &desc)) + return 0; + + j_len = __le32_to_cpu(desc.j_len); + while (i < j_len && i < JOURNAL_TRANS_HALF) + if (__le32_to_cpu(desc.j_realblock[i++]) == blockNr) + goto found; + + if (j_len >= JOURNAL_TRANS_HALF) + { + int commit_block = (desc_block + 1 + j_len) & journal_mask; + if (! journal_read (commit_block, + sizeof (commit), (char *) &commit)) + return 0; + while (i < j_len) + if (__le32_to_cpu(commit.j_realblock[i++ - JOURNAL_TRANS_HALF]) == blockNr) + goto found; + } + } + goto not_found; + + found: + translatedNr = INFO->journal_block + ((desc_block + i) & journal_mask); +#ifdef REISERDEBUG + printf ("block_read: block %d is mapped to journal block %d.\n", + blockNr, translatedNr - INFO->journal_block); +#endif + /* We must continue the search, as this block may be overwritten + * in later transactions. + */ + not_found: + desc_block = (desc_block + 2 + j_len) & journal_mask; + } + return reiserfs_devread (translatedNr << INFO->blocksize_shift, start, len, buffer); +} + +/* Init the journal data structure. We try to cache as much as + * possible in the JOURNAL_START-JOURNAL_END space, but if it is full + * we can still read the rest from the disk on demand. + * + * The first number of valid transactions and the descriptor block of the + * first valid transaction are held in INFO. The transactions are all + * adjacent, but we must take care of the journal wrap around. + */ +static int +journal_init (void) +{ + unsigned int block_count = INFO->journal_block_count; + unsigned int desc_block; + unsigned int commit_block; + unsigned int next_trans_id; + struct reiserfs_journal_header header; + struct reiserfs_journal_desc desc; + struct reiserfs_journal_commit commit; + __u32 *journal_table = JOURNAL_START; + + journal_read (block_count, sizeof (header), (char *) &header); + desc_block = __le32_to_cpu(header.j_first_unflushed_offset); + if (desc_block >= block_count) + return 0; + + INFO->journal_first_desc = desc_block; + next_trans_id = __le32_to_cpu(header.j_last_flush_trans_id) + 1; + +#ifdef REISERDEBUG + printf ("journal_init: last flushed %d\n", + __le32_to_cpu(header.j_last_flush_trans_id)); +#endif + + while (1) + { + journal_read (desc_block, sizeof (desc), (char *) &desc); + if (substring (JOURNAL_DESC_MAGIC, desc.j_magic) > 0 + || __le32_to_cpu(desc.j_trans_id) != next_trans_id + || __le32_to_cpu(desc.j_mount_id) != __le32_to_cpu(header.j_mount_id)) + /* no more valid transactions */ + break; + + commit_block = (desc_block + __le32_to_cpu(desc.j_len) + 1) & (block_count - 1); + journal_read (commit_block, sizeof (commit), (char *) &commit); + if (__le32_to_cpu(desc.j_trans_id) != commit.j_trans_id + || __le32_to_cpu(desc.j_len) != __le32_to_cpu(commit.j_len)) + /* no more valid transactions */ + break; + +#ifdef REISERDEBUG + printf ("Found valid transaction %d/%d at %d.\n", + __le32_to_cpu(desc.j_trans_id), __le32_to_cpu(desc.j_mount_id), desc_block); +#endif + + next_trans_id++; + if (journal_table < JOURNAL_END) + { + if ((journal_table + 1 + __le32_to_cpu(desc.j_len)) >= JOURNAL_END) + { + /* The table is almost full; mark the end of the cached + * journal.*/ + *journal_table = __cpu_to_le32(0xffffffff); + journal_table = JOURNAL_END; + } + else + { + unsigned int i; + /* Cache the length and the realblock numbers in the table. + * The block number of descriptor can easily be computed. + * and need not to be stored here. + */ + + /* both are in the little endian format */ + *journal_table++ = desc.j_len; + for (i = 0; i < __le32_to_cpu(desc.j_len) && i < JOURNAL_TRANS_HALF; i++) + { + /* both are in the little endian format */ + *journal_table++ = desc.j_realblock[i]; +#ifdef REISERDEBUG + printf ("block %d is in journal %d.\n", + __le32_to_cpu(desc.j_realblock[i]), desc_block); +#endif + } + for ( ; i < __le32_to_cpu(desc.j_len); i++) + { + /* both are in the little endian format */ + *journal_table++ = commit.j_realblock[i-JOURNAL_TRANS_HALF]; +#ifdef REISERDEBUG + printf ("block %d is in journal %d.\n", + __le32_to_cpu(commit.j_realblock[i-JOURNAL_TRANS_HALF]), + desc_block); +#endif + } + } + } + desc_block = (commit_block + 1) & (block_count - 1); + } +#ifdef REISERDEBUG + printf ("Transaction %d/%d at %d isn't valid.\n", + __le32_to_cpu(desc.j_trans_id), __le32_to_cpu(desc.j_mount_id), desc_block); +#endif + + INFO->journal_transactions + = next_trans_id - __le32_to_cpu(header.j_last_flush_trans_id) - 1; + return errnum == 0; +} + +/* check filesystem types and read superblock into memory buffer */ +int +reiserfs_mount (unsigned part_length) +{ + struct reiserfs_super_block super; + int superblock = REISERFS_DISK_OFFSET_IN_BYTES >> SECTOR_BITS; + + if (part_length < superblock + (sizeof (super) >> SECTOR_BITS) + || ! reiserfs_devread (superblock, 0, sizeof (struct reiserfs_super_block), + (char *) &super) + || (substring (REISER3FS_SUPER_MAGIC_STRING, super.s_magic) > 0 + && substring (REISER2FS_SUPER_MAGIC_STRING, super.s_magic) > 0 + && substring (REISERFS_SUPER_MAGIC_STRING, super.s_magic) > 0) + || (/* check that this is not a copy inside the journal log */ + sb_journal_block(&super) * sb_blocksize(&super) + <= REISERFS_DISK_OFFSET_IN_BYTES)) + { + /* Try old super block position */ + superblock = REISERFS_OLD_DISK_OFFSET_IN_BYTES >> SECTOR_BITS; + if (part_length < superblock + (sizeof (super) >> SECTOR_BITS) + || ! reiserfs_devread (superblock, 0, sizeof (struct reiserfs_super_block), + (char *) &super)) + return 0; + + if (substring (REISER2FS_SUPER_MAGIC_STRING, super.s_magic) > 0 + && substring (REISERFS_SUPER_MAGIC_STRING, super.s_magic) > 0) + { + /* pre journaling super block ? */ + if (substring (REISERFS_SUPER_MAGIC_STRING, + (char*) ((int) &super + 20)) > 0) + return 0; + + set_sb_blocksize(&super, REISERFS_OLD_BLOCKSIZE); + set_sb_journal_block(&super, 0); + set_sb_version(&super, 0); + } + } + + /* check the version number. */ + if (sb_version(&super) > REISERFS_MAX_SUPPORTED_VERSION) + return 0; + + INFO->version = sb_version(&super); + INFO->blocksize = sb_blocksize(&super); + INFO->fullblocksize_shift = log2 (sb_blocksize(&super)); + INFO->blocksize_shift = INFO->fullblocksize_shift - SECTOR_BITS; + INFO->cached_slots = + (FSYSREISER_CACHE_SIZE >> INFO->fullblocksize_shift) - 1; + +#ifdef REISERDEBUG + printf ("reiserfs_mount: version=%d, blocksize=%d\n", + INFO->version, INFO->blocksize); +#endif /* REISERDEBUG */ + + /* Clear node cache. */ + memset (INFO->blocks, 0, sizeof (INFO->blocks)); + + if (sb_blocksize(&super) < FSYSREISER_MIN_BLOCKSIZE + || sb_blocksize(&super) > FSYSREISER_MAX_BLOCKSIZE + || (SECTOR_SIZE << INFO->blocksize_shift) != sb_blocksize(&super)) + return 0; + + /* Initialize journal code. If something fails we end with zero + * journal_transactions, so we don't access the journal at all. + */ + INFO->journal_transactions = 0; + if (sb_journal_block(&super) != 0 && super.s_journal_dev == 0) + { + INFO->journal_block = sb_journal_block(&super); + INFO->journal_block_count = sb_journal_size(&super); + if (is_power_of_two (INFO->journal_block_count)) + journal_init (); + + /* Read in super block again, maybe it is in the journal */ + block_read (superblock >> INFO->blocksize_shift, + 0, sizeof (struct reiserfs_super_block), (char *) &super); + } + + if (! block_read (sb_root_block(&super), 0, INFO->blocksize, (char*) ROOT)) + return 0; + + INFO->tree_depth = __le16_to_cpu(BLOCKHEAD (ROOT)->blk_level); + +#ifdef REISERDEBUG + printf ("root read_in: block=%d, depth=%d\n", + sb_root_block(&super), INFO->tree_depth); +#endif /* REISERDEBUG */ + + if (INFO->tree_depth >= MAX_HEIGHT) + return 0; + if (INFO->tree_depth == DISK_LEAF_NODE_LEVEL) + { + /* There is only one node in the whole filesystem, + * which is simultanously leaf and root */ + memcpy (LEAF, ROOT, INFO->blocksize); + } + return 1; +} + +/***************** TREE ACCESSING METHODS *****************************/ + +/* I assume you are familiar with the ReiserFS tree, if not go to + * http://www.namesys.com/content_table.html + * + * My tree node cache is organized as following + * 0 ROOT node + * 1 LEAF node (if the ROOT is also a LEAF it is copied here + * 2-n other nodes on current path from bottom to top. + * if there is not enough space in the cache, the top most are + * omitted. + * + * I have only two methods to find a key in the tree: + * search_stat(dir_id, objectid) searches for the stat entry (always + * the first entry) of an object. + * next_key() gets the next key in tree order. + * + * This means, that I can only sequential reads of files are + * efficient, but this really doesn't hurt for grub. + */ + +/* Read in the node at the current path and depth into the node cache. + * You must set INFO->blocks[depth] before. + */ +static char * +read_tree_node (unsigned int blockNr, int depth) +{ + char* cache = CACHE(depth); + int num_cached = INFO->cached_slots; + if (depth < num_cached) + { + /* This is the cached part of the path. Check if same block is + * needed. + */ + if (blockNr == INFO->blocks[depth]) + return cache; + } + else + cache = CACHE(num_cached); + +#ifdef REISERDEBUG + printf (" next read_in: block=%d (depth=%d)\n", + blockNr, depth); +#endif /* REISERDEBUG */ + if (! block_read (blockNr, 0, INFO->blocksize, cache)) + return 0; + /* Make sure it has the right node level */ + if (__le16_to_cpu(BLOCKHEAD (cache)->blk_level) != depth) + { + errnum = ERR_FSYS_CORRUPT; + return 0; + } + + INFO->blocks[depth] = blockNr; + return cache; +} + +/* Get the next key, i.e. the key following the last retrieved key in + * tree order. INFO->current_ih and + * INFO->current_info are adapted accordingly. */ +static int +next_key (void) +{ + int depth; + struct item_head *ih = INFO->current_ih + 1; + char *cache; + +#ifdef REISERDEBUG + printf ("next_key:\n old ih: key %d:%d:%d:%d version:%d\n", + __le32_to_cpu(INFO->current_ih->ih_key.k_dir_id), + __le32_to_cpu(INFO->current_ih->ih_key.k_objectid), + __le32_to_cpu(INFO->current_ih->ih_key.u.v1.k_offset), + __le32_to_cpu(INFO->current_ih->ih_key.u.v1.k_uniqueness), + __le16_to_cpu(INFO->current_ih->ih_version)); +#endif /* REISERDEBUG */ + + if (ih == &ITEMHEAD[__le16_to_cpu(BLOCKHEAD (LEAF)->blk_nr_item)]) + { + depth = DISK_LEAF_NODE_LEVEL; + /* The last item, was the last in the leaf node. + * Read in the next block + */ + do + { + if (depth == INFO->tree_depth) + { + /* There are no more keys at all. + * Return a dummy item with MAX_KEY */ + ih = (struct item_head *) &BLOCKHEAD (LEAF)->blk_right_delim_key; + goto found; + } + depth++; +#ifdef REISERDEBUG + printf (" depth=%d, i=%d\n", depth, INFO->next_key_nr[depth]); +#endif /* REISERDEBUG */ + } + while (INFO->next_key_nr[depth] == 0); + + if (depth == INFO->tree_depth) + cache = ROOT; + else if (depth <= INFO->cached_slots) + cache = CACHE (depth); + else + { + cache = read_tree_node (INFO->blocks[depth], depth); + if (! cache) + return 0; + } + + do + { + int nr_item = __le16_to_cpu(BLOCKHEAD (cache)->blk_nr_item); + int key_nr = INFO->next_key_nr[depth]++; +#ifdef REISERDEBUG + printf (" depth=%d, i=%d/%d\n", depth, key_nr, nr_item); +#endif /* REISERDEBUG */ + if (key_nr == nr_item) + /* This is the last item in this block, set the next_key_nr to 0 */ + INFO->next_key_nr[depth] = 0; + + cache = read_tree_node (dc_block_number(&(DC (cache)[key_nr])), --depth); + if (! cache) + return 0; + } + while (depth > DISK_LEAF_NODE_LEVEL); + + ih = ITEMHEAD; + } + found: + INFO->current_ih = ih; + INFO->current_item = &LEAF[__le16_to_cpu(ih->ih_item_location)]; +#ifdef REISERDEBUG + printf (" new ih: key %d:%d:%d:%d version:%d\n", + __le32_to_cpu(INFO->current_ih->ih_key.k_dir_id), + __le32_to_cpu(INFO->current_ih->ih_key.k_objectid), + __le32_to_cpu(INFO->current_ih->ih_key.u.v1.k_offset), + __le32_to_cpu(INFO->current_ih->ih_key.u.v1.k_uniqueness), + __le16_to_cpu(INFO->current_ih->ih_version)); +#endif /* REISERDEBUG */ + return 1; +} + +/* preconditions: reiserfs_mount already executed, therefore + * INFO block is valid + * returns: 0 if error (errnum is set), + * nonzero iff we were able to find the key successfully. + * postconditions: on a nonzero return, the current_ih and + * current_item fields describe the key that equals the + * searched key. INFO->next_key contains the next key after + * the searched key. + * side effects: messes around with the cache. + */ +static int +search_stat (__u32 dir_id, __u32 objectid) +{ + char *cache; + int depth; + int nr_item; + int i; + struct item_head *ih; +#ifdef REISERDEBUG + printf ("search_stat:\n key %d:%d:0:0\n", dir_id, objectid); +#endif /* REISERDEBUG */ + + depth = INFO->tree_depth; + cache = ROOT; + + while (depth > DISK_LEAF_NODE_LEVEL) + { + struct key *key; + nr_item = __le16_to_cpu(BLOCKHEAD (cache)->blk_nr_item); + + key = KEY (cache); + + for (i = 0; i < nr_item; i++) + { + if (__le32_to_cpu(key->k_dir_id) > dir_id + || (__le32_to_cpu(key->k_dir_id) == dir_id + && (__le32_to_cpu(key->k_objectid) > objectid + || (__le32_to_cpu(key->k_objectid) == objectid + && (__le32_to_cpu(key->u.v1.k_offset) + | __le32_to_cpu(key->u.v1.k_uniqueness)) > 0)))) + break; + key++; + } + +#ifdef REISERDEBUG + printf (" depth=%d, i=%d/%d\n", depth, i, nr_item); +#endif /* REISERDEBUG */ + INFO->next_key_nr[depth] = (i == nr_item) ? 0 : i+1; + cache = read_tree_node (dc_block_number(&(DC (cache)[i])), --depth); + if (! cache) + return 0; + } + + /* cache == LEAF */ + nr_item = __le16_to_cpu(BLOCKHEAD (LEAF)->blk_nr_item); + ih = ITEMHEAD; + for (i = 0; i < nr_item; i++) + { + if (__le32_to_cpu(ih->ih_key.k_dir_id) == dir_id + && __le32_to_cpu(ih->ih_key.k_objectid) == objectid + && __le32_to_cpu(ih->ih_key.u.v1.k_offset) == 0 + && __le32_to_cpu(ih->ih_key.u.v1.k_uniqueness) == 0) + { +#ifdef REISERDEBUG + printf (" depth=%d, i=%d/%d\n", depth, i, nr_item); +#endif /* REISERDEBUG */ + INFO->current_ih = ih; + INFO->current_item = &LEAF[__le16_to_cpu(ih->ih_item_location)]; + return 1; + } + ih++; + } + errnum = ERR_FSYS_CORRUPT; + return 0; +} + +int +reiserfs_read (char *buf, unsigned len) +{ + unsigned int blocksize; + unsigned int offset; + unsigned int to_read; + char *prev_buf = buf; + +#ifdef REISERDEBUG + printf ("reiserfs_read: filepos=%d len=%d, offset=%Lx\n", + filepos, len, (__u64) IH_KEY_OFFSET (INFO->current_ih) - 1); +#endif /* REISERDEBUG */ + + if (__le32_to_cpu(INFO->current_ih->ih_key.k_objectid) != INFO->fileinfo.k_objectid + || IH_KEY_OFFSET (INFO->current_ih) > filepos + 1) + { + search_stat (INFO->fileinfo.k_dir_id, INFO->fileinfo.k_objectid); + goto get_next_key; + } + + while (! errnum) + { + if (__le32_to_cpu(INFO->current_ih->ih_key.k_objectid) != INFO->fileinfo.k_objectid) { + break; + } + + offset = filepos - IH_KEY_OFFSET (INFO->current_ih) + 1; + blocksize = __le16_to_cpu(INFO->current_ih->ih_item_len); + +#ifdef REISERDEBUG + printf (" loop: filepos=%d len=%d, offset=%d blocksize=%d\n", + filepos, len, offset, blocksize); +#endif /* REISERDEBUG */ + + if (IH_KEY_ISTYPE(INFO->current_ih, TYPE_DIRECT) + && offset < blocksize) + { +#ifdef REISERDEBUG + printf ("direct_read: offset=%d, blocksize=%d\n", + offset, blocksize); +#endif /* REISERDEBUG */ + to_read = blocksize - offset; + if (to_read > len) + to_read = len; + + memcpy (buf, INFO->current_item + offset, to_read); + goto update_buf_len; + } + else if (IH_KEY_ISTYPE(INFO->current_ih, TYPE_INDIRECT)) + { + blocksize = (blocksize >> 2) << INFO->fullblocksize_shift; +#ifdef REISERDEBUG + printf ("indirect_read: offset=%d, blocksize=%d\n", + offset, blocksize); +#endif /* REISERDEBUG */ + + while (offset < blocksize) + { + __u32 blocknr = __le32_to_cpu(((__u32 *) INFO->current_item) + [offset >> INFO->fullblocksize_shift]); + int blk_offset = offset & (INFO->blocksize-1); + to_read = INFO->blocksize - blk_offset; + if (to_read > len) + to_read = len; + + /* Journal is only for meta data. Data blocks can be read + * directly without using block_read + */ + reiserfs_devread (blocknr << INFO->blocksize_shift, + blk_offset, to_read, buf); + update_buf_len: + len -= to_read; + buf += to_read; + offset += to_read; + filepos += to_read; + if (len == 0) + goto done; + } + } + get_next_key: + next_key (); + } + done: + return errnum ? 0 : buf - prev_buf; +} + + +/* preconditions: reiserfs_mount already executed, therefore + * INFO block is valid + * returns: 0 if error, nonzero iff we were able to find the file successfully + * postconditions: on a nonzero return, INFO->fileinfo contains the info + * of the file we were trying to look up, filepos is 0 and filemax is + * the size of the file. + */ +static int +reiserfs_dir (char *dirname) +{ + struct reiserfs_de_head *de_head; + char *rest, ch; + __u32 dir_id, objectid, parent_dir_id = 0, parent_objectid = 0; +#ifndef STAGE1_5 + int do_possibilities = 0; +#endif /* ! STAGE1_5 */ + char linkbuf[PATH_MAX]; /* buffer for following symbolic links */ + int link_count = 0; + int mode; + + dir_id = REISERFS_ROOT_PARENT_OBJECTID; + objectid = REISERFS_ROOT_OBJECTID; + + while (1) + { +#ifdef REISERDEBUG + printf ("dirname=%s\n", dirname); +#endif /* REISERDEBUG */ + + /* Search for the stat info first. */ + if (! search_stat (dir_id, objectid)) + return 0; + +#ifdef REISERDEBUG + printf ("sd_mode=%x sd_size=%d\n", + stat_data_v1(INFO->current_ih) ? sd_v1_mode((struct stat_data_v1 *) INFO->current_item) : + sd_v2_mode((struct stat_data *) (INFO->current_item)), + stat_data_v1(INFO->current_ih) ? sd_v1_size((struct stat_data_v1 *) INFO->current_item) : + sd_v2_size((struct stat_data *) INFO->current_item) + ); + +#endif /* REISERDEBUG */ + mode = stat_data_v1(INFO->current_ih) ? + sd_v1_mode((struct stat_data_v1 *) INFO->current_item) : + sd_v2_mode((struct stat_data *) INFO->current_item); + + /* If we've got a symbolic link, then chase it. */ + if (S_ISLNK (mode)) + { + unsigned int len; + if (++link_count > MAX_LINK_COUNT) + { + errnum = ERR_SYMLINK_LOOP; + return 0; + } + + /* Get the symlink size. */ + filemax = stat_data_v1(INFO->current_ih) ? + sd_v1_size((struct stat_data_v1 *) INFO->current_item) : + sd_v2_size((struct stat_data *) INFO->current_item); + + /* Find out how long our remaining name is. */ + len = 0; + while (dirname[len] && !isspace (dirname[len])) + len++; + + if (filemax + len > sizeof (linkbuf) - 1) + { + errnum = ERR_FILELENGTH; + return 0; + } + + /* Copy the remaining name to the end of the symlink data. + Note that DIRNAME and LINKBUF may overlap! */ + memmove (linkbuf + filemax, dirname, len+1); + + INFO->fileinfo.k_dir_id = dir_id; + INFO->fileinfo.k_objectid = objectid; + filepos = 0; + if (! next_key () + || reiserfs_read (linkbuf, filemax) != filemax) + { + if (! errnum) + errnum = ERR_FSYS_CORRUPT; + return 0; + } + +#ifdef REISERDEBUG + printf ("symlink=%s\n", linkbuf); +#endif /* REISERDEBUG */ + + dirname = linkbuf; + if (*dirname == '/') + { + /* It's an absolute link, so look it up in root. */ + dir_id = REISERFS_ROOT_PARENT_OBJECTID; + objectid = REISERFS_ROOT_OBJECTID; + } + else + { + /* Relative, so look it up in our parent directory. */ + dir_id = parent_dir_id; + objectid = parent_objectid; + } + + /* Now lookup the new name. */ + continue; + } + + /* if we have a real file (and we're not just printing possibilities), + then this is where we want to exit */ + + if (! *dirname || isspace (*dirname)) + { + if (! S_ISREG (mode)) + { + errnum = ERR_BAD_FILETYPE; + return 0; + } + + filepos = 0; + filemax = stat_data_v1(INFO->current_ih) ? + sd_v1_size((struct stat_data_v1 *) INFO->current_item) : + sd_v2_size((struct stat_data *) INFO->current_item); +#if 0 + /* If this is a new stat data and size is > 4GB set filemax to + * maximum + */ + if (__le16_to_cpu(INFO->current_ih->ih_version) == ITEM_VERSION_2 + && sd_size_hi((struct stat_data *) INFO->current_item) > 0) + filemax = 0xffffffff; +#endif + INFO->fileinfo.k_dir_id = dir_id; + INFO->fileinfo.k_objectid = objectid; + return next_key (); + } + + /* continue with the file/directory name interpretation */ + while (*dirname == '/') + dirname++; + if (! S_ISDIR (mode)) + { + errnum = ERR_BAD_FILETYPE; + return 0; + } + for (rest = dirname; (ch = *rest) && ! isspace (ch) && ch != '/'; rest++); + *rest = 0; + +# ifndef STAGE1_5 + if (print_possibilities && ch != '/') + do_possibilities = 1; +# endif /* ! STAGE1_5 */ + + while (1) + { + char *name_end; + int num_entries; + + if (! next_key ()) + return 0; +#ifdef REISERDEBUG + printf ("ih: key %d:%d:%d:%d version:%d\n", + __le32_to_cpu(INFO->current_ih->ih_key.k_dir_id), + __le32_to_cpu(INFO->current_ih->ih_key.k_objectid), + __le32_to_cpu(INFO->current_ih->ih_key.u.v1.k_offset), + __le32_to_cpu(INFO->current_ih->ih_key.u.v1.k_uniqueness), + __le16_to_cpu(INFO->current_ih->ih_version)); +#endif /* REISERDEBUG */ + + if (__le32_to_cpu(INFO->current_ih->ih_key.k_objectid) != objectid) + break; + + name_end = INFO->current_item + __le16_to_cpu(INFO->current_ih->ih_item_len); + de_head = (struct reiserfs_de_head *) INFO->current_item; + num_entries = __le16_to_cpu(INFO->current_ih->u.ih_entry_count); + while (num_entries > 0) + { + char *filename = INFO->current_item + deh_location(de_head); + char tmp = *name_end; + if ((deh_state(de_head) & DEH_Visible)) + { + int cmp; + /* Directory names in ReiserFS are not null + * terminated. We write a temporary 0 behind it. + * NOTE: that this may overwrite the first block in + * the tree cache. That doesn't hurt as long as we + * don't call next_key () in between. + */ + *name_end = 0; + cmp = substring (dirname, filename); + *name_end = tmp; +# ifndef STAGE1_5 + if (do_possibilities) + { + if (cmp <= 0) + { + char fn[PATH_MAX]; + struct fsys_reiser_info info_save; + + if (print_possibilities > 0) + print_possibilities = -print_possibilities; + *name_end = 0; + strcpy(fn, filename); + *name_end = tmp; + + /* If NAME is "." or "..", do not count it. */ + if (strcmp (fn, ".") != 0 && strcmp (fn, "..") != 0) { + memcpy(&info_save, INFO, sizeof(struct fsys_reiser_info)); + search_stat (deh_dir_id(de_head), deh_objectid(de_head)); + sd_print_item(INFO->current_ih, INFO->current_item); + printf(" %s\n", fn); + search_stat (dir_id, objectid); + memcpy(INFO, &info_save, sizeof(struct fsys_reiser_info)); + } + } + } + else +# endif /* ! STAGE1_5 */ + if (cmp == 0) + goto found; + } + /* The beginning of this name marks the end of the next name. + */ + name_end = filename; + de_head++; + num_entries--; + } + } + +# ifndef STAGE1_5 + if (print_possibilities < 0) + return 1; +# endif /* ! STAGE1_5 */ + + errnum = ERR_FILE_NOT_FOUND; + *rest = ch; + return 0; + + found: + *rest = ch; + dirname = rest; + + parent_dir_id = dir_id; + parent_objectid = objectid; + dir_id = deh_dir_id(de_head); + objectid = deh_objectid(de_head); + } +} + +/* + * U-Boot interface functions + */ + +/* + * List given directory + * + * RETURN: 0 - OK, else grub_error_t errnum + */ +int +reiserfs_ls (char *dirname) +{ + char *dir_slash; + int res; + + errnum = 0; + dir_slash = malloc(strlen(dirname) + 1); + if (dir_slash == NULL) { + return ERR_NUMBER_OVERFLOW; + } + strcpy(dir_slash, dirname); + /* add "/" to the directory name */ + strcat(dir_slash, "/"); + + print_possibilities = 1; + res = reiserfs_dir (dir_slash); + free(dir_slash); + if (!res || errnum) { + return errnum; + } + + return 0; +} + +/* + * Open file for reading + * + * RETURN: >0 - OK, size of opened file + * <0 - ERROR -grub_error_t errnum + */ +int +reiserfs_open (char *filename) +{ + /* open the file */ + errnum = 0; + print_possibilities = 0; + if (!reiserfs_dir (filename) || errnum) { + return -errnum; + } + return filemax; +} + +#endif /* CFG_CMD_REISER */ diff --git a/fs/reiserfs/reiserfs_private.h b/fs/reiserfs/reiserfs_private.h new file mode 100644 index 0000000..d0197cb --- /dev/null +++ b/fs/reiserfs/reiserfs_private.h @@ -0,0 +1,520 @@ +/* + * Copyright 2000-2002 by Hans Reiser, licensing governed by reiserfs/README + * + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2000, 2001 Free Software Foundation, Inc. + * + * (C) Copyright 2003 - 2004 + * Sysgo AG, , Pavel Bartusek + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* An implementation for the ReiserFS filesystem ported from GRUB. + * Some parts of this code (mainly the structures and defines) are + * from the original reiser fs code, as found in the linux kernel. + */ + +#ifndef __BYTE_ORDER +#if defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) +#define __BYTE_ORDER __LITTLE_ENDIAN +#elif defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN) +#define __BYTE_ORDER __BIG_ENDIAN +#else +#error "unable to define __BYTE_ORDER" +#endif +#endif /* not __BYTE_ORDER */ + +#define FSYS_BUFLEN 0x8000 +#define FSYS_BUF fsys_buf + +/* This is the new super block of a journaling reiserfs system */ +struct reiserfs_super_block +{ + __u32 s_block_count; /* blocks count */ + __u32 s_free_blocks; /* free blocks count */ + __u32 s_root_block; /* root block number */ + __u32 s_journal_block; /* journal block number */ + __u32 s_journal_dev; /* journal device number */ + __u32 s_journal_size; /* size of the journal on FS creation. used to make sure they don't overflow it */ + __u32 s_journal_trans_max; /* max number of blocks in a transaction. */ + __u32 s_journal_magic; /* random value made on fs creation */ + __u32 s_journal_max_batch; /* max number of blocks to batch into a trans */ + __u32 s_journal_max_commit_age; /* in seconds, how old can an async commit be */ + __u32 s_journal_max_trans_age; /* in seconds, how old can a transaction be */ + __u16 s_blocksize; /* block size */ + __u16 s_oid_maxsize; /* max size of object id array */ + __u16 s_oid_cursize; /* current size of object id array */ + __u16 s_state; /* valid or error */ + char s_magic[16]; /* reiserfs magic string indicates that file system is reiserfs */ + __u16 s_tree_height; /* height of disk tree */ + __u16 s_bmap_nr; /* amount of bitmap blocks needed to address each block of file system */ + __u16 s_version; + char s_unused[128]; /* zero filled by mkreiserfs */ +}; + + +#define sb_root_block(sbp) (__le32_to_cpu((sbp)->s_root_block)) +#define sb_journal_block(sbp) (__le32_to_cpu((sbp)->s_journal_block)) +#define set_sb_journal_block(sbp,v) ((sbp)->s_journal_block = __cpu_to_le32(v)) +#define sb_journal_size(sbp) (__le32_to_cpu((sbp)->s_journal_size)) +#define sb_blocksize(sbp) (__le16_to_cpu((sbp)->s_blocksize)) +#define set_sb_blocksize(sbp,v) ((sbp)->s_blocksize = __cpu_to_le16(v)) +#define sb_version(sbp) (__le16_to_cpu((sbp)->s_version)) +#define set_sb_version(sbp,v) ((sbp)->s_version = __cpu_to_le16(v)) + + +#define REISERFS_MAX_SUPPORTED_VERSION 2 +#define REISERFS_SUPER_MAGIC_STRING "ReIsErFs" +#define REISER2FS_SUPER_MAGIC_STRING "ReIsEr2Fs" +#define REISER3FS_SUPER_MAGIC_STRING "ReIsEr3Fs" + +#define MAX_HEIGHT 7 + +/* must be correct to keep the desc and commit structs at 4k */ +#define JOURNAL_TRANS_HALF 1018 + +/* first block written in a commit. */ +struct reiserfs_journal_desc { + __u32 j_trans_id; /* id of commit */ + __u32 j_len; /* length of commit. len +1 is the commit block */ + __u32 j_mount_id; /* mount id of this trans*/ + __u32 j_realblock[JOURNAL_TRANS_HALF]; /* real locations for the first blocks */ + char j_magic[12]; +}; + +/* last block written in a commit */ +struct reiserfs_journal_commit { + __u32 j_trans_id; /* must match j_trans_id from the desc block */ + __u32 j_len; /* ditto */ + __u32 j_realblock[JOURNAL_TRANS_HALF]; /* real locations for the last blocks */ + char j_digest[16]; /* md5 sum of all the blocks involved, including desc and commit. not used, kill it */ +}; + +/* this header block gets written whenever a transaction is considered + fully flushed, and is more recent than the last fully flushed + transaction. + fully flushed means all the log blocks and all the real blocks are + on disk, and this transaction does not need to be replayed. +*/ +struct reiserfs_journal_header { + /* id of last fully flushed transaction */ + __u32 j_last_flush_trans_id; + /* offset in the log of where to start replay after a crash */ + __u32 j_first_unflushed_offset; + /* mount id to detect very old transactions */ + __u32 j_mount_id; +}; + +/* magic string to find desc blocks in the journal */ +#define JOURNAL_DESC_MAGIC "ReIsErLB" + + +/* + * directories use this key as well as old files + */ +struct offset_v1 +{ + /* + * for regular files this is the offset to the first byte of the + * body, contained in the object-item, as measured from the start of + * the entire body of the object. + * + * for directory entries, k_offset consists of hash derived from + * hashing the name and using few bits (23 or more) of the resulting + * hash, and generation number that allows distinguishing names with + * hash collisions. If number of collisions overflows generation + * number, we return EEXIST. High order bit is 0 always + */ + __u32 k_offset; + __u32 k_uniqueness; +}; + +struct offset_v2 { + /* + * for regular files this is the offset to the first byte of the + * body, contained in the object-item, as measured from the start of + * the entire body of the object. + * + * for directory entries, k_offset consists of hash derived from + * hashing the name and using few bits (23 or more) of the resulting + * hash, and generation number that allows distinguishing names with + * hash collisions. If number of collisions overflows generation + * number, we return EEXIST. High order bit is 0 always + */ + +#if defined(__LITTLE_ENDIAN_BITFIELD) + /* little endian version */ + __u64 k_offset:60; + __u64 k_type: 4; +#elif defined(__BIG_ENDIAN_BITFIELD) + /* big endian version */ + __u64 k_type: 4; + __u64 k_offset:60; +#else +#error "__LITTLE_ENDIAN_BITFIELD or __BIG_ENDIAN_BITFIELD must be defined" +#endif +} __attribute__ ((__packed__)); + +#define TYPE_MAXTYPE 3 +#define TYPE_ANY 15 + +#if (__BYTE_ORDER == __BIG_ENDIAN) +typedef union { + struct offset_v2 offset_v2; + __u64 linear; +} __attribute__ ((__packed__)) offset_v2_esafe_overlay; + +static inline __u16 offset_v2_k_type( const struct offset_v2 *v2 ) +{ + offset_v2_esafe_overlay tmp = *(const offset_v2_esafe_overlay *)v2; + tmp.linear = __le64_to_cpu( tmp.linear ); + return (tmp.offset_v2.k_type <= TYPE_MAXTYPE)?tmp.offset_v2.k_type:TYPE_ANY; +} + +static inline loff_t offset_v2_k_offset( const struct offset_v2 *v2 ) +{ + offset_v2_esafe_overlay tmp = *(const offset_v2_esafe_overlay *)v2; + tmp.linear = __le64_to_cpu( tmp.linear ); + return tmp.offset_v2.k_offset; +} +#elif (__BYTE_ORDER == __LITTLE_ENDIAN) +# define offset_v2_k_type(v2) ((v2)->k_type) +# define offset_v2_k_offset(v2) ((v2)->k_offset) +#else +#error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN" +#endif + +struct key +{ + /* packing locality: by default parent directory object id */ + __u32 k_dir_id; + /* object identifier */ + __u32 k_objectid; + /* the offset and node type (old and new form) */ + union + { + struct offset_v1 v1; + struct offset_v2 v2; + } + u; +}; + +#define KEY_SIZE (sizeof (struct key)) + +/* Header of a disk block. More precisely, header of a formatted leaf + or internal node, and not the header of an unformatted node. */ +struct block_head +{ + __u16 blk_level; /* Level of a block in the tree. */ + __u16 blk_nr_item; /* Number of keys/items in a block. */ + __u16 blk_free_space; /* Block free space in bytes. */ + struct key blk_right_delim_key; /* Right delimiting key for this block (supported for leaf level nodes + only) */ +}; +#define BLKH_SIZE (sizeof (struct block_head)) +#define DISK_LEAF_NODE_LEVEL 1 /* Leaf node level. */ + +struct item_head +{ + /* Everything in the tree is found by searching for it based on + * its key.*/ + struct key ih_key; + union { + /* The free space in the last unformatted node of an + indirect item if this is an indirect item. This + equals 0xFFFF iff this is a direct item or stat data + item. Note that the key, not this field, is used to + determine the item type, and thus which field this + union contains. */ + __u16 ih_free_space; + /* Iff this is a directory item, this field equals the + number of directory entries in the directory item. */ + __u16 ih_entry_count; + } __attribute__ ((__packed__)) u; + __u16 ih_item_len; /* total size of the item body */ + __u16 ih_item_location; /* an offset to the item body + * within the block */ + __u16 ih_version; /* 0 for all old items, 2 for new + ones. Highest bit is set by fsck + temporary, cleaned after all + done */ +} __attribute__ ((__packed__)); + +/* size of item header */ +#define IH_SIZE (sizeof (struct item_head)) + +#define ITEM_VERSION_1 0 +#define ITEM_VERSION_2 1 + +#define ih_version(ih) (__le16_to_cpu((ih)->ih_version)) + +#define IH_KEY_OFFSET(ih) (ih_version(ih) == ITEM_VERSION_1 \ + ? __le32_to_cpu((ih)->ih_key.u.v1.k_offset) \ + : offset_v2_k_offset(&((ih)->ih_key.u.v2))) + +#define IH_KEY_ISTYPE(ih, type) (ih_version(ih) == ITEM_VERSION_1 \ + ? __le32_to_cpu((ih)->ih_key.u.v1.k_uniqueness) == V1_##type \ + : offset_v2_k_type(&((ih)->ih_key.u.v2)) == V2_##type) + +/***************************************************************************/ +/* DISK CHILD */ +/***************************************************************************/ +/* Disk child pointer: The pointer from an internal node of the tree + to a node that is on disk. */ +struct disk_child { + __u32 dc_block_number; /* Disk child's block number. */ + __u16 dc_size; /* Disk child's used space. */ + __u16 dc_reserved; +}; + +#define DC_SIZE (sizeof(struct disk_child)) +#define dc_block_number(dc_p) (__le32_to_cpu((dc_p)->dc_block_number)) + + +/* + * old stat data is 32 bytes long. We are going to distinguish new one by + * different size + */ +struct stat_data_v1 +{ + __u16 sd_mode; /* file type, permissions */ + __u16 sd_nlink; /* number of hard links */ + __u16 sd_uid; /* owner */ + __u16 sd_gid; /* group */ + __u32 sd_size; /* file size */ + __u32 sd_atime; /* time of last access */ + __u32 sd_mtime; /* time file was last modified */ + __u32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ + union { + __u32 sd_rdev; + __u32 sd_blocks; /* number of blocks file uses */ + } __attribute__ ((__packed__)) u; + __u32 sd_first_direct_byte; /* first byte of file which is stored + in a direct item: except that if it + equals 1 it is a symlink and if it + equals ~(__u32)0 there is no + direct item. The existence of this + field really grates on me. Let's + replace it with a macro based on + sd_size and our tail suppression + policy. Someday. -Hans */ +} __attribute__ ((__packed__)); + +#define stat_data_v1(ih) (ih_version(ih) == ITEM_VERSION_1) +#define sd_v1_mode(sdp) ((sdp)->sd_mode) +#define sd_v1_nlink(sdp) (__le16_to_cpu((sdp)->sd_nlink)) +#define sd_v1_uid(sdp) (__le16_to_cpu((sdp)->sd_uid)) +#define sd_v1_gid(sdp) (__le16_to_cpu((sdp)->sd_gid)) +#define sd_v1_size(sdp) (__le32_to_cpu((sdp)->sd_size)) +#define sd_v1_mtime(sdp) (__le32_to_cpu((sdp)->sd_mtime)) + +/* Stat Data on disk (reiserfs version of UFS disk inode minus the + address blocks) */ +struct stat_data { + __u16 sd_mode; /* file type, permissions */ + __u16 sd_attrs; /* persistent inode flags */ + __u32 sd_nlink; /* number of hard links */ + __u64 sd_size; /* file size */ + __u32 sd_uid; /* owner */ + __u32 sd_gid; /* group */ + __u32 sd_atime; /* time of last access */ + __u32 sd_mtime; /* time file was last modified */ + __u32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ + __u32 sd_blocks; + union { + __u32 sd_rdev; + __u32 sd_generation; + /*__u32 sd_first_direct_byte; */ + /* first byte of file which is stored in a + direct item: except that if it equals 1 + it is a symlink and if it equals + ~(__u32)0 there is no direct item. The + existence of this field really grates + on me. Let's replace it with a macro + based on sd_size and our tail + suppression policy? */ + } __attribute__ ((__packed__)) u; +} __attribute__ ((__packed__)); + +#define stat_data_v2(ih) (ih_version(ih) == ITEM_VERSION_2) +#define sd_v2_mode(sdp) (__le16_to_cpu((sdp)->sd_mode)) +#define sd_v2_nlink(sdp) (__le32_to_cpu((sdp)->sd_nlink)) +#define sd_v2_size(sdp) (__le64_to_cpu((sdp)->sd_size)) +#define sd_v2_uid(sdp) (__le32_to_cpu((sdp)->sd_uid)) +#define sd_v2_gid(sdp) (__le32_to_cpu((sdp)->sd_gid)) +#define sd_v2_mtime(sdp) (__le32_to_cpu((sdp)->sd_mtime)) + +#define sd_mode(sdp) (__le16_to_cpu((sdp)->sd_mode)) +#define sd_size(sdp) (__le32_to_cpu((sdp)->sd_size)) +#define sd_size_hi(sdp) (__le32_to_cpu((sdp)->sd_size_hi)) + +struct reiserfs_de_head +{ + __u32 deh_offset; /* third component of the directory entry key */ + __u32 deh_dir_id; /* objectid of the parent directory of the + object, that is referenced by directory entry */ + __u32 deh_objectid;/* objectid of the object, that is referenced by + directory entry */ + __u16 deh_location;/* offset of name in the whole item */ + __u16 deh_state; /* whether 1) entry contains stat data (for + future), and 2) whether entry is hidden + (unlinked) */ +}; + +#define DEH_SIZE (sizeof (struct reiserfs_de_head)) +#define deh_offset(p_deh) (__le32_to_cpu((p_deh)->deh_offset)) +#define deh_dir_id(p_deh) (__le32_to_cpu((p_deh)->deh_dir_id)) +#define deh_objectid(p_deh) (__le32_to_cpu((p_deh)->deh_objectid)) +#define deh_location(p_deh) (__le16_to_cpu((p_deh)->deh_location)) +#define deh_state(p_deh) (__le16_to_cpu((p_deh)->deh_state)) + + +#define DEH_Statdata (1 << 0) /* not used now */ +#define DEH_Visible (1 << 2) + +#define SD_OFFSET 0 +#define SD_UNIQUENESS 0 +#define DOT_OFFSET 1 +#define DOT_DOT_OFFSET 2 +#define DIRENTRY_UNIQUENESS 500 + +#define V1_TYPE_STAT_DATA 0x0 +#define V1_TYPE_DIRECT 0xffffffff +#define V1_TYPE_INDIRECT 0xfffffffe +#define V1_TYPE_DIRECTORY_MAX 0xfffffffd +#define V2_TYPE_STAT_DATA 0 +#define V2_TYPE_INDIRECT 1 +#define V2_TYPE_DIRECT 2 +#define V2_TYPE_DIRENTRY 3 + +#define REISERFS_ROOT_OBJECTID 2 +#define REISERFS_ROOT_PARENT_OBJECTID 1 +#define REISERFS_DISK_OFFSET_IN_BYTES (64 * 1024) +/* the spot for the super in versions 3.5 - 3.5.11 (inclusive) */ +#define REISERFS_OLD_DISK_OFFSET_IN_BYTES (8 * 1024) +#define REISERFS_OLD_BLOCKSIZE 4096 + +#define S_ISREG(mode) (((mode) & 0170000) == 0100000) +#define S_ISDIR(mode) (((mode) & 0170000) == 0040000) +#define S_ISLNK(mode) (((mode) & 0170000) == 0120000) + +#define PATH_MAX 1024 /* include/linux/limits.h */ +#define MAX_LINK_COUNT 5 /* number of symbolic links to follow */ + +/* The size of the node cache */ +#define FSYSREISER_CACHE_SIZE 24*1024 +#define FSYSREISER_MIN_BLOCKSIZE SECTOR_SIZE +#define FSYSREISER_MAX_BLOCKSIZE FSYSREISER_CACHE_SIZE / 3 + +/* Info about currently opened file */ +struct fsys_reiser_fileinfo +{ + __u32 k_dir_id; + __u32 k_objectid; +}; + +/* In memory info about the currently mounted filesystem */ +struct fsys_reiser_info +{ + /* The last read item head */ + struct item_head *current_ih; + /* The last read item */ + char *current_item; + /* The information for the currently opened file */ + struct fsys_reiser_fileinfo fileinfo; + /* The start of the journal */ + __u32 journal_block; + /* The size of the journal */ + __u32 journal_block_count; + /* The first valid descriptor block in journal + (relative to journal_block) */ + __u32 journal_first_desc; + + /* The ReiserFS version. */ + __u16 version; + /* The current depth of the reiser tree. */ + __u16 tree_depth; + /* SECTOR_SIZE << blocksize_shift == blocksize. */ + __u8 blocksize_shift; + /* 1 << full_blocksize_shift == blocksize. */ + __u8 fullblocksize_shift; + /* The reiserfs block size (must be a power of 2) */ + __u16 blocksize; + /* The number of cached tree nodes */ + __u16 cached_slots; + /* The number of valid transactions in journal */ + __u16 journal_transactions; + + unsigned int blocks[MAX_HEIGHT]; + unsigned int next_key_nr[MAX_HEIGHT]; +}; + +/* The cached s+tree blocks in FSYS_BUF, see below + * for a more detailed description. + */ +#define ROOT ((char *) ((int) FSYS_BUF)) +#define CACHE(i) (ROOT + ((i) << INFO->fullblocksize_shift)) +#define LEAF CACHE (DISK_LEAF_NODE_LEVEL) + +#define BLOCKHEAD(cache) ((struct block_head *) cache) +#define ITEMHEAD ((struct item_head *) ((int) LEAF + BLKH_SIZE)) +#define KEY(cache) ((struct key *) ((int) cache + BLKH_SIZE)) +#define DC(cache) ((struct disk_child *) \ + ((int) cache + BLKH_SIZE + KEY_SIZE * nr_item)) +/* The fsys_reiser_info block. + */ +#define INFO \ + ((struct fsys_reiser_info *) ((int) FSYS_BUF + FSYSREISER_CACHE_SIZE)) +/* + * The journal cache. For each transaction it contains the number of + * blocks followed by the real block numbers of this transaction. + * + * If the block numbers of some transaction won't fit in this space, + * this list is stopped with a 0xffffffff marker and the remaining + * uncommitted transactions aren't cached. + */ +#define JOURNAL_START ((__u32 *) (INFO + 1)) +#define JOURNAL_END ((__u32 *) (FSYS_BUF + FSYS_BUFLEN)) + + +static __inline__ unsigned long +log2 (unsigned long word) +{ +#ifdef __I386__ + __asm__ ("bsfl %1,%0" + : "=r" (word) + : "r" (word)); + return word; +#else + int i; + + for(i=0; i<(8*sizeof(word)); i++) + if ((1< + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 74xx_7xx.h + * + * 74xx/7xx specific definitions + */ + +#ifndef __MPC74XX_H__ +#define __MPC74XX_H__ + +/*---------------------------------------------------------------- + * Exception offsets (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */ + +/*---------------------------------------------------------------- + * l2cr values + */ +#define l2cr 1017 + +#define L2CR_L2E 0x80000000 /* bit 0 - enable */ +#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ +#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */ +#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */ +#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */ +#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */ +#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */ +#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */ +#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */ +#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */ +#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */ +#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */ +#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */ +#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */ +#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */ +#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ +#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ +#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */ +#define L2CR_TS 0x00040000 /* bit 13 - test support on */ +#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */ +#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */ +#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */ +#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */ +#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ + +/*---------------------------------------------------------------- + * BAT settings. Look in config_.h for the actual setup + */ + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +#ifndef __ASSEMBLY__ +/* cpu ids we detect */ +typedef enum __cpu_t { + CPU_740, CPU_750, + CPU_740P, CPU_750P, + CPU_745, CPU_755, + CPU_750CX, CPU_750FX, CPU_750GX, + CPU_7400, + CPU_7410, + CPU_7450, CPU_7455, CPU_7457, + CPU_UNKNOWN} cpu_t; + +extern cpu_t get_cpu_type(void); + +#define l1icache_enable icache_enable + +void l2cache_enable(void); +void l1dcache_enable(void); + +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr (unsigned long msr) +{ + asm volatile("mtmsr %0" : : "r" (msr)); +} + +static __inline__ unsigned long get_hid0 (void) +{ + unsigned long hid0; + asm volatile("mfspr %0, 1008" : "=r" (hid0) :); + return hid0; +} + +static __inline__ unsigned long get_hid1 (void) +{ + unsigned long hid1; + asm volatile("mfspr %0, 1009" : "=r" (hid1) :); + return hid1; +} + +static __inline__ void set_hid0 (unsigned long hid0) +{ + asm volatile("mtspr 1008, %0" : : "r" (hid0)); +} + +static __inline__ void set_hid1 (unsigned long hid1) +{ + asm volatile("mtspr 1009, %0" : : "r" (hid1)); +} + +#endif /* __ASSEMBLY__ */ +#endif /* __MPC74XX_H__ */ diff --git a/include/ACEX1K.h b/include/ACEX1K.h new file mode 100644 index 0000000..f75c463 --- /dev/null +++ b/include/ACEX1K.h @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2003 + * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de + * + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ACEX1K_H_ +#define _ACEX1K_H_ + +#include + +extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size ); +extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize ); +extern int ACEX1K_info( Altera_desc *desc ); +extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off ); + +/* Slave Serial Implementation function table */ +typedef struct { + Altera_pre_fn pre; + Altera_config_fn config; + Altera_clk_fn clk; + Altera_status_fn status; + Altera_done_fn done; + Altera_data_fn data; + Altera_abort_fn abort; + Altera_post_fn post; + int relocated; +} Altera_ACEX1K_Passive_Serial_fns; + +/* Device Image Sizes + *********************************************************************/ +/* ACEX1K */ +/* FIXME: Which size do we mean? + * Datasheet says 1337000/8=167125Bytes, + * Filesize of an *.rbf file is 166965 Bytes + */ +#if 0 +#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */ +#endif +#define Altera_EP1K100_SIZE (166965*8) + +/* Descriptor Macros + *********************************************************************/ +/* ACEX1K devices */ +#define Altera_EP1K100_DESC(iface, fn_table, cookie) \ +{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie } + +#endif /* _ACEX1K_H_ */ diff --git a/include/SA-1100.h b/include/SA-1100.h new file mode 100644 index 0000000..9985783 --- /dev/null +++ b/include/SA-1100.h @@ -0,0 +1,2833 @@ +/* + * FILE SA-1100.h + * + * Version 1.2 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date January 1998 (April 1997) + * System StrongARM SA-1100 + * Language C or ARM Assembly + * Purpose Definition of constants related to the StrongARM + * SA-1100 microprocessor (Advanced RISC Machine (ARM) + * architecture version 4). This file is based on the + * StrongARM SA-1100 data sheet version 2.2. + * + * Language-specific definitions are selected by the + * macro "LANGUAGE", which should be defined as either + * "C" (default) or "Assembly". + */ + + +#ifndef LANGUAGE +# ifdef __ASSEMBLY__ +# define LANGUAGE Assembly +# else +# define LANGUAGE C +# endif +#endif + +#ifndef io_p2v +#define io_p2v(PhAdd) (PhAdd) +#endif + +#include + +#define C 0 +#define Assembly 1 + + +#if LANGUAGE == C +typedef unsigned short Word16 ; +typedef unsigned int Word32 ; +typedef Word32 Word ; +typedef Word Quad [4] ; +typedef void *Address ; +typedef void (*ExcpHndlr) (void) ; +#endif /* LANGUAGE == C */ + + +/* + * Memory + */ + +#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ + +#define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */ +#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ + /* [byte] */ +#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ + /* [byte] */ +#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ + /* [byte] */ +#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ + /* [byte] */ + +#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ +#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ +#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ +#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ +#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ + +#define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */ + +#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ + (0x00000000 + (Nb)*StMemBnkSp) +#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ +#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ +#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ +#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ + +#if LANGUAGE == C +typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; +#define StMemBnk /* Static Memory Bank [0..3] */ \ + ((StMemBnkType *) io_p2v (_StMemBnk (0))) +#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ +#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ +#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ +#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ +#endif /* LANGUAGE == C */ + +#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ + (0xC0000000 + (Nb)*DRAMBnkSp) +#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ +#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ +#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ +#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ + +#if LANGUAGE == C +typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; +#define DRAMBnk /* DRAM Bank [0..3] */ \ + ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) +#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ +#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ +#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ +#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ +#endif /* LANGUAGE == C */ + +#define _ZeroMem 0xE0000000 /* Zero Memory bank */ + +#if LANGUAGE == C +typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; +#define ZeroMem /* Zero Memory bank */ \ + (*((ZeroMemType *) io_p2v (_ZeroMem))) +#endif /* LANGUAGE == C */ + + +/* + * Personal Computer Memory Card International Association (PCMCIA) sockets + */ + +#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ +#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ + +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ +#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ +#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ + +#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ +#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ +#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ +#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ + +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ + (0x20000000 + (Nb)*PCMCIASp) +#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ +#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ + (_PCMCIA (Nb) + 2*PCMCIAPrtSp) +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ + (_PCMCIA (Nb) + 3*PCMCIAPrtSp) + +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ + +#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ +#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ +#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ +#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ + +#if LANGUAGE == C + +typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; +typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; + +#define PCMCIA0 /* PCMCIA 0 */ \ + (*((PCMCIAType *) io_p2v (_PCMCIA0))) +#define PCMCIA0IO /* PCMCIA 0 I/O */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) +#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) +#define PCMCIA0Mem /* PCMCIA 0 Memory */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) + +#define PCMCIA1 /* PCMCIA 1 */ \ + (*((PCMCIAType *) io_p2v (_PCMCIA1))) +#define PCMCIA1IO /* PCMCIA 1 I/O */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) +#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) +#define PCMCIA1Mem /* PCMCIA 1 Memory */ \ + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) + +#endif /* LANGUAGE == C */ + + +/* + * Universal Serial Bus (USB) Device Controller (UDC) control registers + * + * Registers + * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control Register (read/write). + * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Address Register (read/write). + * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Output Maximum Packet size register + * (read/write). + * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Input Maximum Packet size register + * (read/write). + * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 0 + * (read/write). + * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 1 + * (output, read/write). + * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 2 + * (input, read/write). + * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data register end-point 0 + * (read/write). + * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Write Count register end-point 0 + * (read). + * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data Register (read/write). + * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Status Register (read/write). + */ + +#define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */ +#define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */ +#define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */ + /* Packet size reg. */ +#define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */ + /* Packet size reg. */ +#define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */ + /* reg. end-point 0 */ +#define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */ + /* reg. end-point 1 (output) */ +#define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */ + /* reg. end-point 2 (input) */ +#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ + /* end-point 0 */ +#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ + /* reg. end-point 0 */ +#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ +#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ + +#if LANGUAGE == C +#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCR))) +#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCAR))) +#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ + /* Packet size reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCOMP))) +#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ + /* Packet size reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCIMP))) +#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS0))) +#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 1 (output) */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS1))) +#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 2 (input) */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS2))) +#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ + /* end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCD0))) +#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ + /* reg. end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCWC))) +#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCDR))) +#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCSR))) +#endif /* LANGUAGE == C */ + +#define UDCCR_UDD 0x00000001 /* UDC Disable */ +#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ +#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ +#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ + /* (disable) */ +#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ + /* (disable) */ +#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ + /* (disable) */ +#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ + /* (disable) */ +#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ +#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ + +#define UDCAR_ADD Fld (7, 0) /* function ADDress */ + +#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ + /* [byte] */ +#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) + +#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ + /* [byte] */ +#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCIMP_INMAXP)) + +#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ +#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ +#define UDCCS0_SST 0x00000004 /* Sent STall */ +#define UDCCS0_FST 0x00000008 /* Force STall */ +#define UDCCS0_DE 0x00000010 /* Data End */ +#define UDCCS0_SE 0x00000020 /* Setup End (read) */ +#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ + /* (write) */ +#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ + +#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ + /* Service request (read) */ +#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ +#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ +#define UDCCS1_SST 0x00000008 /* Sent STall */ +#define UDCCS1_FST 0x00000010 /* Force STall */ +#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ + +#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ + /* Service request (read) */ +#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ +#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ +#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ +#define UDCCS2_SST 0x00000010 /* Sent STall */ +#define UDCCS2_FST 0x00000020 /* Force STall */ + +#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ + +#define UDCWC_WC Fld (4, 0) /* Write Count */ + +#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ + +#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ +#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ +#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ +#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ +#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ +#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ + + +/* + * Universal Asynchronous Receiver/Transmitter (UART) control registers + * + * Registers + * Ser1UTCR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser1UTCR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser1UTCR2 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser1UTCR3 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser1UTDR Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser1UTSR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser1UTSR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). + * + * Ser2UTCR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser2UTCR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser2UTCR2 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser2UTCR3 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser2UTCR4 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 4 + * (read/write). + * Ser2UTDR Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser2UTSR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser2UTSR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). + * + * Ser3UTCR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser3UTCR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser3UTCR2 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser3UTCR3 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser3UTDR Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser3UTSR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser3UTSR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fua, Tua Frequency, period of the UART communication. + */ + +#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ + (0x80010000 + ((Nb) - 1)*0x00020000) +#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ + (0x80010004 + ((Nb) - 1)*0x00020000) +#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ + (0x80010008 + ((Nb) - 1)*0x00020000) +#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ + (0x8001000C + ((Nb) - 1)*0x00020000) +#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ + (0x80010010 + ((Nb) - 1)*0x00020000) +#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ + (0x80010014 + ((Nb) - 1)*0x00020000) +#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ + (0x8001001C + ((Nb) - 1)*0x00020000) +#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ + (0x80010020 + ((Nb) - 1)*0x00020000) + +#define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ +#define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ +#define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ +#define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ +#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ +#define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ +#define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ + +#define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ +#define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ +#define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ +#define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ +#define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ +#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ +#define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ +#define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ + +#define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ +#define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ +#define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ +#define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ +#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ +#define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ +#define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ + +#if LANGUAGE == C + +#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR0))) +#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR1))) +#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR2))) +#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser1UTCR3))) +#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser1UTDR))) +#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1UTSR0))) +#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1UTSR1))) + +#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR0))) +#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR1))) +#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR2))) +#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR3))) +#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ + (*((volatile Word *) io_p2v (_Ser2UTCR4))) +#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser2UTDR))) +#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2UTSR0))) +#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2UTSR1))) + +#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR0))) +#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR1))) +#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR2))) +#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser3UTCR3))) +#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser3UTDR))) +#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser3UTSR0))) +#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser3UTSR1))) + +#elif LANGUAGE == Assembly +#define Ser1UTCR0 ( io_p2v (_Ser1UTCR0)) +#define Ser1UTCR1 ( io_p2v (_Ser1UTCR1)) +#define Ser1UTCR2 ( io_p2v (_Ser1UTCR2)) +#define Ser1UTCR3 ( io_p2v (_Ser1UTCR3)) +#define Ser1UTDR ( io_p2v (_Ser1UTDR)) +#define Ser1UTSR0 ( io_p2v (_Ser1UTSR0)) +#define Ser1UTSR1 ( io_p2v (_Ser1UTSR1)) + +#define Ser2UTCR0 ( io_p2v (_Ser2UTCR0)) +#define Ser2UTCR1 ( io_p2v (_Ser2UTCR1)) +#define Ser2UTCR2 ( io_p2v (_Ser2UTCR2)) +#define Ser2UTCR3 ( io_p2v (_Ser2UTCR3)) +#define Ser2UTCR4 ( io_p2v (_Ser2UTCR4)) +#define Ser2UTDR ( io_p2v (_Ser2UTDR)) +#define Ser2UTSR0 ( io_p2v (_Ser2UTSR0)) +#define Ser2UTSR1 ( io_p2v (_Ser2UTSR1)) + +#define Ser3UTCR0 ( io_p2v (_Ser3UTCR0)) +#define Ser3UTCR1 ( io_p2v (_Ser3UTCR1)) +#define Ser3UTCR2 ( io_p2v (_Ser3UTCR2)) +#define Ser3UTCR3 ( io_p2v (_Ser3UTCR3)) +#define Ser3UTDR ( io_p2v (_Ser3UTDR)) +#define Ser3UTSR0 ( io_p2v (_Ser3UTSR0)) +#define Ser3UTSR1 ( io_p2v (_Ser3UTSR1)) + +#endif /* LANGUAGE == C */ + +#define UTCR0_PE 0x00000001 /* Parity Enable */ +#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ +#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ +#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ +#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ +#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ +#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ +#define UTCR0_DSS 0x00000008 /* Data Size Select */ +#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ +#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ +#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ + /* (ser. port 1: GPIO [18], */ + /* ser. port 3: GPIO [20]) */ +#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ +#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ +#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ +#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ +#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ +#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ +#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ + (UTCR0_1StpBit + UTCR0_8BitData) + +#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ +#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ + /* fua = fxtl/(16*(BRD[11:0] + 1)) */ + /* Tua = 16*(BRD [11:0] + 1)*Txtl */ +#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ + FShft (UTCR1_BRD)) +#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ + FShft (UTCR2_BRD)) + /* fua = fxtl/(16*Floor (Div/16)) */ + /* Tua = 16*Floor (Div/16)*Txtl */ +#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ + FShft (UTCR1_BRD)) +#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ + FShft (UTCR2_BRD)) + /* fua = fxtl/(16*Ceil (Div/16)) */ + /* Tua = 16*Ceil (Div/16)*Txtl */ + +#define UTCR3_RXE 0x00000001 /* Receive Enable */ +#define UTCR3_TXE 0x00000002 /* Transmit Enable */ +#define UTCR3_BRK 0x00000004 /* BReaK mode */ +#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Interrupt Enable */ +#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ +#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ + /* TIE, LBM can be set or cleared) */ \ + (UTCR3_RXE + UTCR3_TXE) + +#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ + /* (HP-SIR) modulation Enable */ +#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ +#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ +#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ +#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ +#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ + +#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ +#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ +#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ +#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ +#endif /* 0 */ + +#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Service request (read) */ +#define UTSR0_RID 0x00000004 /* Receiver IDle */ +#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ +#define UTSR0_REB 0x00000010 /* Receive End of Break */ +#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ + +#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ +#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ +#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ +#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ +#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ +#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ + + +/* + * Synchronous Data Link Controller (SDLC) control registers + * + * Registers + * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 0 (read/write). + * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 1 (read/write). + * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 2 (read/write). + * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 3 (read/write). + * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 4 (read/write). + * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) + * Data Register (read/write). + * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 0 (read/write). + * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 1 (read/write). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fsd, Tsd Frequency, period of the SDLC communication. + */ + +#define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */ +#define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */ +#define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */ +#define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */ +#define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */ +#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ +#define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */ +#define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */ + +#if LANGUAGE == C +#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR0))) +#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR1))) +#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR2))) +#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR3))) +#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ + (*((volatile Word *) io_p2v (_Ser1SDCR4))) +#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser1SDDR))) +#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser1SDSR0))) +#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser1SDSR1))) +#endif /* LANGUAGE == C */ + +#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ +#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ +#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ +#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ +#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ +#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ +#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ +#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ +#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ +#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ +#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ +#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ + /* (GPIO [16]) */ +#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ +#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ +#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ +#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ +#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ +#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ +#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ +#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ + +#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ + /* (GPIO [17]) */ +#define SDCR1_TXE 0x00000002 /* Transmit Enable */ +#define SDCR1_RXE 0x00000004 /* Receive Enable */ +#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Interrupt Enable */ +#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define SDCR1_AME 0x00000020 /* Address Match Enable */ +#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ +#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ +#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ +#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ + +#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ + +#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ +#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ + /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ + /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ +#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ + FShft (SDCR3_BRD)) +#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ + (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ + FShft (SDCR4_BRD)) + /* fsd = fxtl/(16*Floor (Div/16)) */ + /* Tsd = 16*Floor (Div/16)*Txtl */ +#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ + FShft (SDCR3_BRD)) +#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ + (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ + FShft (SDCR4_BRD)) + /* fsd = fxtl/(16*Ceil (Div/16)) */ + /* Tsd = 16*Ceil (Div/16)*Txtl */ + +#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ +#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ +#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ +#endif /* 0 */ + +#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define SDSR0_RAB 0x00000004 /* Receive ABort */ +#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ + /* more Service request (read) */ + +#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ +#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ +#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ +#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ +#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ +#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ +#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ + + +/* + * High-Speed Serial to Parallel controller (HSSP) control registers + * + * Registers + * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 0 (read/write). + * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 1 (read/write). + * Ser2HSDR Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Data Register (read/write). + * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 0 (read/write). + * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 1 (read). + * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 2 (read/write). + * [The HSCR2 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + */ + +#define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */ +#define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */ +#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ +#define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */ +#define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */ +#define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */ + +#if LANGUAGE == C +#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2HSCR0))) +#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2HSCR1))) +#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser2HSDR))) +#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser2HSSR0))) +#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser2HSSR1))) +#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_Ser2HSCR2))) +#endif /* LANGUAGE == C */ + +#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ +#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ +#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ +#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ +#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ +#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ +#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ +#define HSCR0_TXE 0x00000008 /* Transmit Enable */ +#define HSCR0_RXE 0x00000010 /* Receive Enable */ +#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ + /* more Interrupt Enable */ +#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define HSCR0_AME 0x00000080 /* Address Match Enable */ + +#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ + +#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ +#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ +#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ +#endif /* 0 */ + +#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define HSSR0_RAB 0x00000004 /* Receive ABort */ +#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ + /* more Service request (read) */ +#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ + +#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ +#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ +#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ +#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ +#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ +#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ + +#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ +#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ + /* (inverted) */ +#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ + /* (non-inverted) */ +#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ +#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ + /* (inverted) */ +#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ + /* (non-inverted) */ + + +/* + * Multi-media Communications Port (MCP) control registers + * + * Registers + * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 0 (read/write). + * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 0 (audio, read/write). + * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 1 (telecom, read/write). + * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 2 (CODEC registers, read/write). + * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) + * Status Register (read/write). + * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 1 (read/write). + * [The MCCR1 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + * + * Clocks + * fmc, Tmc Frequency, period of the MCP communication (10 MHz, + * 12 MHz, or GPIO [21]). + * faud, Taud Frequency, period of the audio sampling. + * ftcm, Ttcm Frequency, period of the telecom sampling. + */ + +#define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */ +#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ + /* (audio) */ +#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ + /* (telecom) */ +#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ + /* (CODEC reg.) */ +#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ +#define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */ + +#if LANGUAGE == C +#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser4MCCR0))) +#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ + /* (audio) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR0))) +#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ + /* (telecom) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR1))) +#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ + /* (CODEC reg.) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR2))) +#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ + (*((volatile Word *) io_p2v (_Ser4MCSR))) +#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser4MCCR1))) +#endif /* LANGUAGE == C */ + +#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ + /* [6..127] */ + /* faud = fmc/(32*ASD) */ + /* Taud = 32*ASD*Tmc */ +#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ + /* [192..4064] */ \ + ((Div)/32 << FShft (MCCR0_ASD)) + /* faud = fmc/(32*Floor (Div/32)) */ + /* Taud = 32*Floor (Div/32)*Tmc */ +#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ + (((Div) + 31)/32 << FShft (MCCR0_ASD)) + /* faud = fmc/(32*Ceil (Div/32)) */ + /* Taud = 32*Ceil (Div/32)*Tmc */ +#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ + /* Divisor/32 [16..127] */ + /* ftcm = fmc/(32*TSD) */ + /* Ttcm = 32*TSD*Tmc */ +#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ + /* [512..4064] */ \ + ((Div)/32 << FShft (MCCR0_TSD)) + /* ftcm = fmc/(32*Floor (Div/32)) */ + /* Ttcm = 32*Floor (Div/32)*Tmc */ +#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ + (((Div) + 31)/32 << FShft (MCCR0_TSD)) + /* ftcm = fmc/(32*Ceil (Div/32)) */ + /* Ttcm = 32*Ceil (Div/32)*Tmc */ +#define MCCR0_MCE 0x00010000 /* MCP Enable */ +#define MCCR0_ECS 0x00020000 /* External Clock Select */ +#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ +#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ +#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ + /* sampling/storing Mode */ +#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ +#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ +#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ + /* or less interrupt Enable */ +#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ + /* or more interrupt Enable */ +#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ + /* or less interrupt Enable */ +#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ + /* more interrupt Enable */ +#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ +#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ +#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ + (((Div) - 1) << FShft (MCCR0_ECP)) + +#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ + /* FIFOs */ + +#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ + /* FIFOs */ + + /* receive/transmit CODEC reg. */ + /* FIFOs: */ +#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ +#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ +#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ +#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ +#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ + +#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ + /* or less Service request (read) */ +#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ + /* more Service request (read) */ +#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ + /* or less Service request (read) */ +#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ + /* or more Service request (read) */ +#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ +#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ +#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ +#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ +#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ + /* (read) */ +#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ + /* (read) */ +#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ + /* (read) */ +#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ + /* (read) */ +#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ + /* (read) */ +#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ + /* (read) */ +#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ +#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ + +#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ +#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ + /* (11.981 MHz) */ +#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ + /* (9.585 MHz) */ + + +/* + * Synchronous Serial Port (SSP) control registers + * + * Registers + * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 0 (read/write). + * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 1 (read/write). + * [Bits SPO and SP are only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data + * Register (read/write). + * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status + * Register (read/write). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fss, Tss Frequency, period of the SSP communication. + */ + +#define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */ +#define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */ +#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ +#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ + +#if LANGUAGE == C +#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_Ser4SSCR0))) +#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_Ser4SSCR1))) +#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ + (*((volatile Word *) io_p2v (_Ser4SSDR))) +#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ + (*((volatile Word *) io_p2v (_Ser4SSSR))) +#endif /* LANGUAGE == C */ + +#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ +#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ + (((Size) - 1) << FShft (SSCR0_DSS)) +#define SSCR0_FRF Fld (2, 4) /* FRame Format */ +#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ + /* Interface (SPI) format */ \ + (0 << FShft (SSCR0_FRF)) +#define SSCR0_TI /* Texas Instruments Synchronous */ \ + /* Serial format */ \ + (1 << FShft (SSCR0_FRF)) +#define SSCR0_National /* National Microwire format */ \ + (2 << FShft (SSCR0_FRF)) +#define SSCR0_SSE 0x00000080 /* SSP Enable */ +#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ + /* fss = fxtl/(2*(SCR + 1)) */ + /* Tss = 2*(SCR + 1)*Txtl */ +#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ + (((Div) - 2)/2 << FShft (SSCR0_SCR)) + /* fss = fxtl/(2*Floor (Div/2)) */ + /* Tss = 2*Floor (Div/2)*Txtl */ +#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ + (((Div) - 1)/2 << FShft (SSCR0_SCR)) + /* fss = fxtl/(2*Ceil (Div/2)) */ + /* Tss = 2*Ceil (Div/2)*Txtl */ + +#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ + /* Interrupt Enable */ +#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ + /* Interrupt Enable */ +#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ +#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ +#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ +#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ +#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ +#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ + /* after frame (SFRM, 1st edge) */ +#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ + /* after frame (SFRM, 1st edge) */ +#define SSCR1_ECS 0x00000020 /* External Clock Select */ +#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ +#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ + +#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ + +#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ +#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ +#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ +#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ + /* Service request (read) */ +#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ + /* Service request (read) */ +#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ + + +/* + * Operating System (OS) timer control registers + * + * Registers + * OSMR0 Operating System (OS) timer Match Register 0 + * (read/write). + * OSMR1 Operating System (OS) timer Match Register 1 + * (read/write). + * OSMR2 Operating System (OS) timer Match Register 2 + * (read/write). + * OSMR3 Operating System (OS) timer Match Register 3 + * (read/write). + * OSCR Operating System (OS) timer Counter Register + * (read/write). + * OSSR Operating System (OS) timer Status Register + * (read/write). + * OWER Operating System (OS) timer Watch-dog Enable Register + * (read/write). + * OIER Operating System (OS) timer Interrupt Enable Register + * (read/write). + */ + +#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ + (0x90000000 + (Nb)*4) +#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ +#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ +#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ +#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ +#define _OSCR 0x90000010 /* OS timer Counter Reg. */ +#define _OSSR 0x90000014 /* OS timer Status Reg. */ +#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ +#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ + +#if LANGUAGE == C +#define OSMR /* OS timer Match Reg. [0..3] */ \ + ((volatile Word *) io_p2v (_OSMR (0))) +#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ +#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ +#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ +#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ +#define OSCR /* OS timer Counter Reg. */ \ + (*((volatile Word *) io_p2v (_OSCR))) +#define OSSR /* OS timer Status Reg. */ \ + (*((volatile Word *) io_p2v (_OSSR))) +#define OWER /* OS timer Watch-dog Enable Reg. */ \ + (*((volatile Word *) io_p2v (_OWER))) +#define OIER /* OS timer Interrupt Enable Reg. */ \ + (*((volatile Word *) io_p2v (_OIER))) +#endif /* LANGUAGE == C */ + +#define OSSR_M(Nb) /* Match detected [0..3] */ \ + (0x00000001 << (Nb)) +#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ +#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ +#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ +#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ + +#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ + /* (set only) */ + +#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ + (0x00000001 << (Nb)) +#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ +#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ +#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ +#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ + + +/* + * Real-Time Clock (RTC) control registers + * + * Registers + * RTAR Real-Time Clock (RTC) Alarm Register (read/write). + * RCNR Real-Time Clock (RTC) CouNt Register (read/write). + * RTTR Real-Time Clock (RTC) Trim Register (read/write). + * RTSR Real-Time Clock (RTC) Status Register (read/write). + * + * Clocks + * frtx, Trtx Frequency, period of the real-time clock crystal + * (32.768 kHz nominal). + * frtc, Trtc Frequency, period of the real-time clock counter + * (1 Hz nominal). + */ + +#define _RTAR 0x90010000 /* RTC Alarm Reg. */ +#define _RCNR 0x90010004 /* RTC CouNt Reg. */ +#define _RTTR 0x90010008 /* RTC Trim Reg. */ +#define _RTSR 0x90010010 /* RTC Status Reg. */ + +#if LANGUAGE == C +#define RTAR /* RTC Alarm Reg. */ \ + (*((volatile Word *) io_p2v (_RTAR))) +#define RCNR /* RTC CouNt Reg. */ \ + (*((volatile Word *) io_p2v (_RCNR))) +#define RTTR /* RTC Trim Reg. */ \ + (*((volatile Word *) io_p2v (_RTTR))) +#define RTSR /* RTC Status Reg. */ \ + (*((volatile Word *) io_p2v (_RTSR))) +#endif /* LANGUAGE == C */ + +#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ +#define RTTR_D Fld (10, 16) /* trim Delete count */ + /* frtc = (1023*(C + 1) - D)*frtx/ */ + /* (1023*(C + 1)^2) */ + /* Trtc = (1023*(C + 1)^2)*Trtx/ */ + /* (1023*(C + 1) - D) */ + +#define RTSR_AL 0x00000001 /* ALarm detected */ +#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ +#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ +#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ + + +/* + * Power Manager (PM) control registers + * + * Registers + * PMCR Power Manager (PM) Control Register (read/write). + * PSSR Power Manager (PM) Sleep Status Register (read/write). + * PSPR Power Manager (PM) Scratch-Pad Register (read/write). + * PWER Power Manager (PM) Wake-up Enable Register + * (read/write). + * PCFR Power Manager (PM) general ConFiguration Register + * (read/write). + * PPCR Power Manager (PM) Phase-Locked Loop (PLL) + * Configuration Register (read/write). + * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) + * Sleep state Register (read/write, see GPIO pins). + * POSR Power Manager (PM) Oscillator Status Register (read). + * + * Clocks + * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz + * or 3.5795 MHz). + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + */ + +#define _PMCR 0x90020000 /* PM Control Reg. */ +#define _PSSR 0x90020004 /* PM Sleep Status Reg. */ +#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ +#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ +#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ +#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ +#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ +#define _POSR 0x9002001C /* PM Oscillator Status Reg. */ + +#if LANGUAGE == C +#define PMCR /* PM Control Reg. */ \ + (*((volatile Word *) io_p2v (_PMCR))) +#define PSSR /* PM Sleep Status Reg. */ \ + (*((volatile Word *) io_p2v (_PSSR))) +#define PSPR /* PM Scratch-Pad Reg. */ \ + (*((volatile Word *) io_p2v (_PSPR))) +#define PWER /* PM Wake-up Enable Reg. */ \ + (*((volatile Word *) io_p2v (_PWER))) +#define PCFR /* PM general ConFiguration Reg. */ \ + (*((volatile Word *) io_p2v (_PCFR))) +#define PPCR /* PM PLL Configuration Reg. */ \ + (*((volatile Word *) io_p2v (_PPCR))) +#define PGSR /* PM GPIO Sleep state Reg. */ \ + (*((volatile Word *) io_p2v (_PGSR))) +#define POSR /* PM Oscillator Status Reg. */ \ + (*((volatile Word *) io_p2v (_POSR))) + +#elif LANGUAGE == Assembly +#define PMCR (io_p2v (_PMCR)) +#define PSSR (io_p2v (_PSSR)) +#define PSPR (io_p2v (_PSPR)) +#define PWER (io_p2v (_PWER)) +#define PCFR (io_p2v (_PCFR)) +#define PPCR (io_p2v (_PPCR)) +#define PGSR (io_p2v (_PGSR)) +#define POSR (io_p2v (_POSR)) + +#endif /* LANGUAGE == C */ + +#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ + +#define PSSR_SS 0x00000001 /* Software Sleep */ +#define PSSR_BFS 0x00000002 /* Battery Fault Status */ + /* (BATT_FAULT) */ +#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ +#define PSSR_DH 0x00000008 /* DRAM control Hold */ +#define PSSR_PH 0x00000010 /* Peripheral control Hold */ + +#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ +#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ +#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ +#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ +#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ +#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ +#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ +#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ +#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ +#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ +#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ +#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ +#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ +#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ +#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ +#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ +#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ +#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ +#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ +#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ +#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ +#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ +#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ +#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ +#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ +#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ +#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ +#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ +#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ +#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ + +#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ +#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ +#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ +#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ +#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ +#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ +#define PCFR_FS 0x00000004 /* Float Static memory pins */ +#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ +#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ +#define PCFR_FO 0x00000008 /* Force RTC oscillator */ + /* (32.768 kHz) enable On */ + +#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ +#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ + (0x00 << FShft (PPCR_CCF)) +#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ + (0x01 << FShft (PPCR_CCF)) +#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ + (0x02 << FShft (PPCR_CCF)) +#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ + (0x03 << FShft (PPCR_CCF)) +#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ + (0x04 << FShft (PPCR_CCF)) +#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ + (0x05 << FShft (PPCR_CCF)) +#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ + (0x06 << FShft (PPCR_CCF)) +#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ + (0x07 << FShft (PPCR_CCF)) +#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ + (0x08 << FShft (PPCR_CCF)) +#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ + (0x09 << FShft (PPCR_CCF)) +#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ + (0x0A << FShft (PPCR_CCF)) +#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ + (0x0B << FShft (PPCR_CCF)) +#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ + (0x0C << FShft (PPCR_CCF)) +#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ + (0x0D << FShft (PPCR_CCF)) +#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ + (0x0E << FShft (PPCR_CCF)) +#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ + (0x0F << FShft (PPCR_CCF)) + /* 3.6864 MHz crystal (fxtl): */ +#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ +#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ +#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ +#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ +#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ +#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ +#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ +#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ +#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ +#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ +#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ +#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ +#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ +#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ +#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ +#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ + /* 3.5795 MHz crystal (fxtl): */ +#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ +#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ +#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ +#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ +#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ +#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ +#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ +#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ +#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ +#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ +#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ +#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ +#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ +#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ +#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ +#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ + +#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ + + +/* + * Reset Controller (RC) control registers + * + * Registers + * RSRR Reset Controller (RC) Software Reset Register + * (read/write). + * RCSR Reset Controller (RC) Status Register (read/write). + */ + +#define _RSRR 0x90030000 /* RC Software Reset Reg. */ +#define _RCSR 0x90030004 /* RC Status Reg. */ + +#if LANGUAGE == C +#define RSRR /* RC Software Reset Reg. */ \ + (*((volatile Word *) io_p2v (_RSRR))) +#define RCSR /* RC Status Reg. */ \ + (*((volatile Word *) io_p2v (_RCSR))) +#endif /* LANGUAGE == C */ + +#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ + +#define RCSR_HWR 0x00000001 /* HardWare Reset */ +#define RCSR_SWR 0x00000002 /* SoftWare Reset */ +#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ +#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ + + +/* + * Test unit control registers + * + * Registers + * TUCR Test Unit Control Register (read/write). + */ + +#define _TUCR 0x90030008 /* Test Unit Control Reg. */ + +#if LANGUAGE == C +#define TUCR /* Test Unit Control Reg. */ \ + (*((volatile Word *) io_p2v (_TUCR))) +#endif /* LANGUAGE == C */ + +#define TUCR_TIC 0x00000040 /* TIC mode */ +#define TUCR_TTST 0x00000080 /* Trim TeST mode */ +#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ + /* Check */ +#define TUCR_PMD 0x00000200 /* Power Management Disable */ +#define TUCR_MR 0x00000400 /* Memory Request mode */ +#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ +#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ + /* grant (MBGNT) on GPIO [22:21] */ +#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ +#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ +#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ +#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ +#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ +#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ +#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ + (0 << FShft (TUCR_TSEL)) +#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ + (1 << FShft (TUCR_TSEL)) +#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ + (2 << FShft (TUCR_TSEL)) +#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ + (3 << FShft (TUCR_TSEL)) +#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ + /* Clocks on GPIO [26:27] */ \ + (4 << FShft (TUCR_TSEL)) +#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ + /* (Alternative) */ \ + (5 << FShft (TUCR_TSEL)) +#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ + (6 << FShft (TUCR_TSEL)) +#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ + (7 << FShft (TUCR_TSEL)) + + +/* + * General-Purpose Input/Output (GPIO) control registers + * + * Registers + * GPLR General-Purpose Input/Output (GPIO) Pin Level + * Register (read). + * GPDR General-Purpose Input/Output (GPIO) Pin Direction + * Register (read/write). + * GPSR General-Purpose Input/Output (GPIO) Pin output Set + * Register (write). + * GPCR General-Purpose Input/Output (GPIO) Pin output Clear + * Register (write). + * GRER General-Purpose Input/Output (GPIO) Rising-Edge + * detect Register (read/write). + * GFER General-Purpose Input/Output (GPIO) Falling-Edge + * detect Register (read/write). + * GEDR General-Purpose Input/Output (GPIO) Edge Detect + * status Register (read/write). + * GAFR General-Purpose Input/Output (GPIO) Alternate + * Function Register (read/write). + * + * Clock + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + */ + +#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ +#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ +#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ +#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ +#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ +#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ +#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ +#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ + +#if LANGUAGE == C +#define GPLR /* GPIO Pin Level Reg. */ \ + (*((volatile Word *) io_p2v (_GPLR))) +#define GPDR /* GPIO Pin Direction Reg. */ \ + (*((volatile Word *) io_p2v (_GPDR))) +#define GPSR /* GPIO Pin output Set Reg. */ \ + (*((volatile Word *) io_p2v (_GPSR))) +#define GPCR /* GPIO Pin output Clear Reg. */ \ + (*((volatile Word *) io_p2v (_GPCR))) +#define GRER /* GPIO Rising-Edge detect Reg. */ \ + (*((volatile Word *) io_p2v (_GRER))) +#define GFER /* GPIO Falling-Edge detect Reg. */ \ + (*((volatile Word *) io_p2v (_GFER))) +#define GEDR /* GPIO Edge Detect status Reg. */ \ + (*((volatile Word *) io_p2v (_GEDR))) +#define GAFR /* GPIO Alternate Function Reg. */ \ + (*((volatile Word *) io_p2v (_GAFR))) +#elif LANGUAGE == Assembly + +#define GPLR (io_p2v (_GPLR)) +#define GPDR (io_p2v (_GPDR)) +#define GPSR (io_p2v (_GPSR)) +#define GPCR (io_p2v (_GPCR)) +#define GRER (io_p2v (_GRER)) +#define GFER (io_p2v (_GFER)) +#define GEDR (io_p2v (_GEDR)) +#define GAFR (io_p2v (_GAFR)) + +#endif /* LANGUAGE == C */ + +#define GPIO_MIN (0) +#define GPIO_MAX (27) + +#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ + (0x00000001 << (Nb)) +#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ +#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ +#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ +#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ +#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ +#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ +#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ +#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ +#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ +#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ +#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ +#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ +#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ +#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ +#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ +#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ +#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ +#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ +#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ +#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ +#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ +#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ +#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ +#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ +#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ +#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ +#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ +#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ + +#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ + GPIO_GPIO ((Nb) - 6) +#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ +#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ +#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ +#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ +#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ +#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ +#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ +#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ + /* ser. port 4: */ +#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ +#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ +#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ +#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ + /* ser. port 1: */ +#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ +#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ +#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ +#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ +#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ + /* ser. port 4: */ +#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ + /* ser. port 3: */ +#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ + /* ser. port 4: */ +#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ + /* test controller: */ +#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ +#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ +#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ +#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ +#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ +#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ +#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ +#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ + +#define GPDR_In 0 /* Input */ +#define GPDR_Out 1 /* Output */ + + +/* + * Interrupt Controller (IC) control registers + * + * Registers + * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) + * Pending register (read). + * ICMR Interrupt Controller (IC) Mask Register (read/write). + * ICLR Interrupt Controller (IC) Level Register (read/write). + * ICCR Interrupt Controller (IC) Control Register + * (read/write). + * [The ICCR register is only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * ICFP Interrupt Controller (IC) Fast Interrupt reQuest + * (FIQ) Pending register (read). + * ICPR Interrupt Controller (IC) Pending Register (read). + * [The ICPR register is active low (inverted) in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it is active high (non-inverted) in + * versions 2.0 (rev. = 8) and higher.] + */ + +#define _ICIP 0x90050000 /* IC IRQ Pending reg. */ +#define _ICMR 0x90050004 /* IC Mask Reg. */ +#define _ICLR 0x90050008 /* IC Level Reg. */ +#define _ICCR 0x9005000C /* IC Control Reg. */ +#define _ICFP 0x90050010 /* IC FIQ Pending reg. */ +#define _ICPR 0x90050020 /* IC Pending Reg. */ + +#if LANGUAGE == C +#define ICIP /* IC IRQ Pending reg. */ \ + (*((volatile Word *) io_p2v (_ICIP))) +#define ICMR /* IC Mask Reg. */ \ + (*((volatile Word *) io_p2v (_ICMR))) +#define ICLR /* IC Level Reg. */ \ + (*((volatile Word *) io_p2v (_ICLR))) +#define ICCR /* IC Control Reg. */ \ + (*((volatile Word *) io_p2v (_ICCR))) +#define ICFP /* IC FIQ Pending reg. */ \ + (*((volatile Word *) io_p2v (_ICFP))) +#define ICPR /* IC Pending Reg. */ \ + (*((volatile Word *) io_p2v (_ICPR))) +#endif /* LANGUAGE == C */ + +#define IC_GPIO(Nb) /* GPIO [0..10] */ \ + (0x00000001 << (Nb)) +#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ +#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ +#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ +#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ +#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ +#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ +#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ +#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ +#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ +#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ +#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ +#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ +#define IC_LCD 0x00001000 /* LCD controller */ +#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ +#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ +#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ +#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ +#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ +#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ +#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ +#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ + (0x00100000 << (Nb)) +#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ +#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ +#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ +#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ +#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ +#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ +#define IC_OST(Nb) /* OS Timer match [0..3] */ \ + (0x04000000 << (Nb)) +#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ +#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ +#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ +#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ +#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ +#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ + +#define ICLR_IRQ 0 /* Interrupt ReQuest */ +#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ + +#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ + /* Mask */ +#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ + /* (ICMR ignored) */ +#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ + /* enable (ICMR used) */ + + +/* + * Peripheral Pin Controller (PPC) control registers + * + * Registers + * PPDR Peripheral Pin Controller (PPC) Pin Direction + * Register (read/write). + * PPSR Peripheral Pin Controller (PPC) Pin State Register + * (read/write). + * PPAR Peripheral Pin Controller (PPC) Pin Assignment + * Register (read/write). + * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin + * Direction Register (read/write). + * PPFR Peripheral Pin Controller (PPC) Pin Flag Register + * (read). + */ + +#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ +#define _PPSR 0x90060004 /* PPC Pin State Reg. */ +#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ +#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ + /* Reg. */ +#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ + +#if LANGUAGE == C +#define PPDR /* PPC Pin Direction Reg. */ \ + (*((volatile Word *) io_p2v (_PPDR))) +#define PPSR /* PPC Pin State Reg. */ \ + (*((volatile Word *) io_p2v (_PPSR))) +#define PPAR /* PPC Pin Assignment Reg. */ \ + (*((volatile Word *) io_p2v (_PPAR))) +#define PSDR /* PPC Sleep-mode pin Direction */ \ + /* Reg. */ \ + (*((volatile Word *) io_p2v (_PSDR))) +#define PPFR /* PPC Pin Flag Reg. */ \ + (*((volatile Word *) io_p2v (_PPFR))) +#endif /* LANGUAGE == C */ + +#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ + (0x00000001 << (Nb)) +#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ +#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ +#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ +#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ +#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ +#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ +#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ +#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ +#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ +#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ +#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ +#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ + /* ser. port 1: */ +#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ +#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ + /* ser. port 2: */ +#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ +#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ + /* ser. port 3: */ +#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ +#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ + /* ser. port 4: */ +#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ +#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ +#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ +#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ + +#define PPDR_In 0 /* Input */ +#define PPDR_Out 1 /* Output */ + + /* ser. port 1: */ +#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ +#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ +#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ + /* ser. port 4: */ +#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ +#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ + /* & SFRM_C */ +#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ + +#define PSDR_OutL 0 /* Output Low in sleep mode */ +#define PSDR_Flt 1 /* Floating (input) in sleep mode */ + +#define PPFR_LCD 0x00000001 /* LCD controller */ +#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ +#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ +#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ +#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ +#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ +#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ +#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ +#define PPFR_PerEn 0 /* Peripheral Enabled */ +#define PPFR_PPCEn 1 /* PPC Enabled */ + + +/* + * Dynamic Random-Access Memory (DRAM) control registers + * + * Registers + * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) + * CoNFiGuration register (read/write). + * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 0 + * (read/write). + * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 1 + * (read/write). + * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 2 + * (read/write). + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + * fcas, Tcas Frequency, period of the DRAM CAS shift registers. + */ + + /* Memory system: */ +#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ +#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ + (0xA0000004 + (Nb)*4) +#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ +#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ +#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ + +#if LANGUAGE == C + /* Memory system: */ +#define MDCNFG /* DRAM CoNFiGuration reg. */ \ + (*((volatile Word *) io_p2v (_MDCNFG))) +#define MDCAS /* DRAM CAS shift reg. [0..3] */ \ + ((volatile Word *) io_p2v (_MDCAS (0))) +#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ +#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ +#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ + +#elif LANGUAGE == Assembly + +#define MDCNFG (io_p2v(_MDCNFG)) + +#endif /* LANGUAGE == C */ + +/* SA1100 MDCNFG values */ +#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ + (0x00000001 << (Nb)) +#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ +#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ +#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ +#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ +#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ +#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ + (((Add) - 9) << FShft (MDCNFG_DRAC)) +#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ + /* (fcas = fcpu/2) */ +#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ +#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) +#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) +#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ +#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ + (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) +#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ + (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) +#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ +#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ + ((Tcpu) << FShft (MDCNFG_TDL)) +#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ + /* [Tmem] */ +#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ + /* [0..262136 Tcpu] */ \ + ((Tcpu)/8 << FShft (MDCNFG_DRI)) + +/* SA1110 MDCNFG values */ +#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ +#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ + /* bank 0/1 */ +#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ +#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ + /* deassertion 0/1 */ +#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ +#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ +#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ + /* bank 0/1 */ +#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ +#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ + /* deassertion 0/1 */ +#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ + + +/* + * Static memory control registers + * + * Registers + * MSC0 Memory system: Static memory Control register 0 + * (read/write). + * MSC1 Memory system: Static memory Control register 1 + * (read/write). + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + */ + + /* Memory system: */ +#define _MSC(Nb) /* Static memory Control reg. */ \ + /* [0..1] */ \ + (0xA0000010 + (Nb)*4) +#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ +#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ +#define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */ + +#if LANGUAGE == C + /* Memory system: */ +#define MSC /* Static memory Control reg. */ \ + /* [0..1] */ \ + ((volatile Word *) io_p2v (_MSC (0))) +#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ +#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ +#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ + +#elif LANGUAGE == Assembly + +#define MSC0 io_p2v(0xa0000010) +#define MSC1 io_p2v(0xa0000014) +#define MSC2 io_p2v(0xa000002c) + +#endif /* LANGUAGE == C */ + +#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ + Fld (16, ((Nb) Modulo 2)*16) +#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ +#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ +#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ +#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ + +#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ +#define MSC_NonBrst /* Non-Burst static memory */ \ + (0 << FShft (MSC_RT)) +#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ + (1 << FShft (MSC_RT)) +#define MSC_Brst4 /* Burst-of-4 static memory */ \ + (2 << FShft (MSC_RT)) +#define MSC_Brst8 /* Burst-of-8 static memory */ \ + (3 << FShft (MSC_RT)) +#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ +#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ +#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ +#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ + /* First access - 1(.5) [Tmem] */ +#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ + /* static memory) [3..65 Tcpu] */ \ + ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) +#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) +#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ + /* static memory) [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) +#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) +#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ + /* Next access - 1 [Tmem] */ +#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ + /* static memory) [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) +#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) +#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ + /* static memory) [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) +#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) +#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ + /* time/2 [Tmem] */ +#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ + (((Tcpu)/4) << FShft (MSC_RRR)) +#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ + ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) + + +/* + * Personal Computer Memory Card International Association (PCMCIA) control + * register + * + * Register + * MECR Memory system: Expansion memory bus (PCMCIA) + * Configuration Register (read/write). + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). + */ + + /* Memory system: */ +#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ + /* Configuration Reg. */ + +#if LANGUAGE == C + /* Memory system: */ +#define MECR /* Expansion memory bus (PCMCIA) */ \ + /* Configuration Reg. */ \ + (*((volatile Word *) io_p2v (_MECR))) +#endif /* LANGUAGE == C */ + +#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ + Fld (15, (Nb)*16) +#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ +#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ + +#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ +#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) +#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) +#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ + /* [Tmem] */ +#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) +#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) +#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ +#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) +#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ + ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) + +/* + * On SA1110 only + */ + +#define _MDREFR 0xA000001C + +#if LANGUAGE == C + /* Memory system: */ +#define MDREFR \ + (*((volatile Word *) io_p2v (_MDREFR))) + +#elif LANGUAGE == Assembly + +#define MDREFR (io_p2v(_MDREFR)) + +#endif /* LANGUAGE == C */ + +#define MDREFR_TRASR Fld (4, 0) +#define MDREFR_DRI Fld (12, 4) +#define MDREFR_E0PIN (1 << 16) +#define MDREFR_K0RUN (1 << 17) +#define MDREFR_K0DB2 (1 << 18) +#define MDREFR_E1PIN (1 << 20) +#define MDREFR_K1RUN (1 << 21) +#define MDREFR_K1DB2 (1 << 22) +#define MDREFR_K2RUN (1 << 25) +#define MDREFR_K2DB2 (1 << 26) +#define MDREFR_EAPD (1 << 28) +#define MDREFR_KAPD (1 << 29) +#define MDREFR_SLFRSH (1 << 31) + + +/* + * Direct Memory Access (DMA) control registers + * + * Registers + * DDAR0 Direct Memory Access (DMA) Device Address Register + * channel 0 (read/write). + * DCSR0 Direct Memory Access (DMA) Control and Status + * Register channel 0 (read/write). + * DBSA0 Direct Memory Access (DMA) Buffer Start address + * register A channel 0 (read/write). + * DBTA0 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 0 (read/write). + * DBSB0 Direct Memory Access (DMA) Buffer Start address + * register B channel 0 (read/write). + * DBTB0 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 0 (read/write). + * + * DDAR1 Direct Memory Access (DMA) Device Address Register + * channel 1 (read/write). + * DCSR1 Direct Memory Access (DMA) Control and Status + * Register channel 1 (read/write). + * DBSA1 Direct Memory Access (DMA) Buffer Start address + * register A channel 1 (read/write). + * DBTA1 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 1 (read/write). + * DBSB1 Direct Memory Access (DMA) Buffer Start address + * register B channel 1 (read/write). + * DBTB1 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 1 (read/write). + * + * DDAR2 Direct Memory Access (DMA) Device Address Register + * channel 2 (read/write). + * DCSR2 Direct Memory Access (DMA) Control and Status + * Register channel 2 (read/write). + * DBSA2 Direct Memory Access (DMA) Buffer Start address + * register A channel 2 (read/write). + * DBTA2 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 2 (read/write). + * DBSB2 Direct Memory Access (DMA) Buffer Start address + * register B channel 2 (read/write). + * DBTB2 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 2 (read/write). + * + * DDAR3 Direct Memory Access (DMA) Device Address Register + * channel 3 (read/write). + * DCSR3 Direct Memory Access (DMA) Control and Status + * Register channel 3 (read/write). + * DBSA3 Direct Memory Access (DMA) Buffer Start address + * register A channel 3 (read/write). + * DBTA3 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 3 (read/write). + * DBSB3 Direct Memory Access (DMA) Buffer Start address + * register B channel 3 (read/write). + * DBTB3 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 3 (read/write). + * + * DDAR4 Direct Memory Access (DMA) Device Address Register + * channel 4 (read/write). + * DCSR4 Direct Memory Access (DMA) Control and Status + * Register channel 4 (read/write). + * DBSA4 Direct Memory Access (DMA) Buffer Start address + * register A channel 4 (read/write). + * DBTA4 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 4 (read/write). + * DBSB4 Direct Memory Access (DMA) Buffer Start address + * register B channel 4 (read/write). + * DBTB4 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 4 (read/write). + * + * DDAR5 Direct Memory Access (DMA) Device Address Register + * channel 5 (read/write). + * DCSR5 Direct Memory Access (DMA) Control and Status + * Register channel 5 (read/write). + * DBSA5 Direct Memory Access (DMA) Buffer Start address + * register A channel 5 (read/write). + * DBTA5 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 5 (read/write). + * DBSB5 Direct Memory Access (DMA) Buffer Start address + * register B channel 5 (read/write). + * DBTB5 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 5 (read/write). + */ + +#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ + +#define _DDAR(Nb) /* DMA Device Address Reg. */ \ + /* channel [0..5] */ \ + (0xB0000000 + (Nb)*DMASp) +#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ + (0xB0000004 + (Nb)*DMASp) +#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ + (0xB0000008 + (Nb)*DMASp) +#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ + /* channel [0..5] (read) */ \ + (0xB000000C + (Nb)*DMASp) +#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ + /* channel [0..5] */ \ + (0xB0000010 + (Nb)*DMASp) +#define _DBTA(Nb) /* DMA Buffer Transfer count */ \ + /* reg. A channel [0..5] */ \ + (0xB0000014 + (Nb)*DMASp) +#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ + /* channel [0..5] */ \ + (0xB0000018 + (Nb)*DMASp) +#define _DBTB(Nb) /* DMA Buffer Transfer count */ \ + /* reg. B channel [0..5] */ \ + (0xB000001C + (Nb)*DMASp) + +#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ + /* channel 0 */ +#define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */ + /* channel 0 (write) */ +#define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */ + /* channel 0 (write) */ +#define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */ + /* channel 0 (read) */ +#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ + /* channel 0 */ +#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ + /* reg. A channel 0 */ +#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ + /* channel 0 */ +#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ + /* reg. B channel 0 */ + +#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ + /* channel 1 */ +#define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */ + /* channel 1 (write) */ +#define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */ + /* channel 1 (write) */ +#define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */ + /* channel 1 (read) */ +#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ + /* channel 1 */ +#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ + /* reg. A channel 1 */ +#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ + /* channel 1 */ +#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ + /* reg. B channel 1 */ + +#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ + /* channel 2 */ +#define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */ + /* channel 2 (write) */ +#define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */ + /* channel 2 (write) */ +#define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */ + /* channel 2 (read) */ +#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ + /* channel 2 */ +#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ + /* reg. A channel 2 */ +#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ + /* channel 2 */ +#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ + /* reg. B channel 2 */ + +#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ + /* channel 3 */ +#define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */ + /* channel 3 (write) */ +#define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */ + /* channel 3 (write) */ +#define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */ + /* channel 3 (read) */ +#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ + /* channel 3 */ +#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ + /* reg. A channel 3 */ +#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ + /* channel 3 */ +#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ + /* reg. B channel 3 */ + +#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ + /* channel 4 */ +#define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */ + /* channel 4 (write) */ +#define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */ + /* channel 4 (write) */ +#define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */ + /* channel 4 (read) */ +#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ + /* channel 4 */ +#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ + /* reg. A channel 4 */ +#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ + /* channel 4 */ +#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ + /* reg. B channel 4 */ + +#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ + /* channel 5 */ +#define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */ + /* channel 5 (write) */ +#define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */ + /* channel 5 (write) */ +#define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */ + /* channel 5 (read) */ +#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ + /* channel 5 */ +#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ + /* reg. A channel 5 */ +#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ + /* channel 5 */ +#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ + /* reg. B channel 5 */ + +#if LANGUAGE == C + +#define DDAR0 /* DMA Device Address Reg. */ \ + /* channel 0 */ \ + (*((volatile Word *) io_p2v (_DDAR0))) +#define SetDCSR0 /* Set DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR0))) +#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR0))) +#define RdDCSR0 /* Read DMA Control & Status Reg. */ \ + /* channel 0 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR0))) +#define DBSA0 /* DMA Buffer Start address reg. A */ \ + /* channel 0 */ \ + (*((volatile Address *) io_p2v (_DBSA0))) +#define DBTA0 /* DMA Buffer Transfer count */ \ + /* reg. A channel 0 */ \ + (*((volatile Word *) io_p2v (_DBTA0))) +#define DBSB0 /* DMA Buffer Start address reg. B */ \ + /* channel 0 */ \ + (*((volatile Address *) io_p2v (_DBSB0))) +#define DBTB0 /* DMA Buffer Transfer count */ \ + /* reg. B channel 0 */ \ + (*((volatile Word *) io_p2v (_DBTB0))) + +#define DDAR1 /* DMA Device Address Reg. */ \ + /* channel 1 */ \ + (*((volatile Word *) io_p2v (_DDAR1))) +#define SetDCSR1 /* Set DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR1))) +#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR1))) +#define RdDCSR1 /* Read DMA Control & Status Reg. */ \ + /* channel 1 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR1))) +#define DBSA1 /* DMA Buffer Start address reg. A */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBSA1))) +#define DBTA1 /* DMA Buffer Transfer count */ \ + /* reg. A channel 1 */ \ + (*((volatile Word *) io_p2v (_DBTA1))) +#define DBSB1 /* DMA Buffer Start address reg. B */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBSB1))) +#define DBTB1 /* DMA Buffer Transfer count */ \ + /* reg. B channel 1 */ \ + (*((volatile Word *) io_p2v (_DBTB1))) + +#define DDAR2 /* DMA Device Address Reg. */ \ + /* channel 2 */ \ + (*((volatile Word *) io_p2v (_DDAR2))) +#define SetDCSR2 /* Set DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR2))) +#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR2))) +#define RdDCSR2 /* Read DMA Control & Status Reg. */ \ + /* channel 2 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR2))) +#define DBSA2 /* DMA Buffer Start address reg. A */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBSA2))) +#define DBTA2 /* DMA Buffer Transfer count */ \ + /* reg. A channel 2 */ \ + (*((volatile Word *) io_p2v (_DBTA2))) +#define DBSB2 /* DMA Buffer Start address reg. B */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBSB2))) +#define DBTB2 /* DMA Buffer Transfer count */ \ + /* reg. B channel 2 */ \ + (*((volatile Word *) io_p2v (_DBTB2))) + +#define DDAR3 /* DMA Device Address Reg. */ \ + /* channel 3 */ \ + (*((volatile Word *) io_p2v (_DDAR3))) +#define SetDCSR3 /* Set DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR3))) +#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR3))) +#define RdDCSR3 /* Read DMA Control & Status Reg. */ \ + /* channel 3 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR3))) +#define DBSA3 /* DMA Buffer Start address reg. A */ \ + /* channel 3 */ \ + (*((volatile Address *) io_p2v (_DBSA3))) +#define DBTA3 /* DMA Buffer Transfer count */ \ + /* reg. A channel 3 */ \ + (*((volatile Word *) io_p2v (_DBTA3))) +#define DBSB3 /* DMA Buffer Start address reg. B */ \ + /* channel 3 */ \ + (*((volatile Address *) io_p2v (_DBSB3))) +#define DBTB3 /* DMA Buffer Transfer count */ \ + /* reg. B channel 3 */ \ + (*((volatile Word *) io_p2v (_DBTB3))) + +#define DDAR4 /* DMA Device Address Reg. */ \ + /* channel 4 */ \ + (*((volatile Word *) io_p2v (_DDAR4))) +#define SetDCSR4 /* Set DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR4))) +#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR4))) +#define RdDCSR4 /* Read DMA Control & Status Reg. */ \ + /* channel 4 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR4))) +#define DBSA4 /* DMA Buffer Start address reg. A */ \ + /* channel 4 */ \ + (*((volatile Address *) io_p2v (_DBSA4))) +#define DBTA4 /* DMA Buffer Transfer count */ \ + /* reg. A channel 4 */ \ + (*((volatile Word *) io_p2v (_DBTA4))) +#define DBSB4 /* DMA Buffer Start address reg. B */ \ + /* channel 4 */ \ + (*((volatile Address *) io_p2v (_DBSB4))) +#define DBTB4 /* DMA Buffer Transfer count */ \ + /* reg. B channel 4 */ \ + (*((volatile Word *) io_p2v (_DBTB4))) + +#define DDAR5 /* DMA Device Address Reg. */ \ + /* channel 5 */ \ + (*((volatile Word *) io_p2v (_DDAR5))) +#define SetDCSR5 /* Set DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR5))) +#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR5))) +#define RdDCSR5 /* Read DMA Control & Status Reg. */ \ + /* channel 5 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR5))) +#define DBSA5 /* DMA Buffer Start address reg. A */ \ + /* channel 5 */ \ + (*((volatile Address *) io_p2v (_DBSA5))) +#define DBTA5 /* DMA Buffer Transfer count */ \ + /* reg. A channel 5 */ \ + (*((volatile Word *) io_p2v (_DBTA5))) +#define DBSB5 /* DMA Buffer Start address reg. B */ \ + /* channel 5 */ \ + (*((volatile Address *) io_p2v (_DBSB5))) +#define DBTB5 /* DMA Buffer Transfer count */ \ + /* reg. B channel 5 */ \ + (*((volatile Word *) io_p2v (_DBTB5))) + +#endif /* LANGUAGE == C */ + +#define DDAR_RW 0x00000001 /* device data Read/Write */ +#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ + /* (memory -> device) */ +#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ + /* (device -> memory) */ +#define DDAR_E 0x00000002 /* big/little Endian device */ +#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ +#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ +#define DDAR_BS 0x00000004 /* device Burst Size */ +#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ +#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ +#define DDAR_DW 0x00000008 /* device Data Width */ +#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ +#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ +#define DDAR_DS Fld (4, 4) /* Device Select */ +#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ + (0x0 << FShft (DDAR_DS)) +#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ + (0x1 << FShft (DDAR_DS)) +#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ + (0x2 << FShft (DDAR_DS)) +#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ + (0x3 << FShft (DDAR_DS)) +#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ + (0x4 << FShft (DDAR_DS)) +#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ + (0x5 << FShft (DDAR_DS)) +#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ + (0x6 << FShft (DDAR_DS)) +#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ + (0x7 << FShft (DDAR_DS)) +#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ + (0x8 << FShft (DDAR_DS)) +#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ + (0x9 << FShft (DDAR_DS)) +#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ + /* (audio) */ \ + (0xA << FShft (DDAR_DS)) +#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ + /* (audio) */ \ + (0xB << FShft (DDAR_DS)) +#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ + /* (telecom) */ \ + (0xC << FShft (DDAR_DS)) +#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ + /* (telecom) */ \ + (0xD << FShft (DDAR_DS)) +#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ + (0xE << FShft (DDAR_DS)) +#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ + (0xF << FShft (DDAR_DS)) +#define DDAR_DA Fld (24, 8) /* Device Address */ +#define DDAR_DevAdd(Add) /* Device Address */ \ + (((Add) & 0xF0000000) | \ + (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) +#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ + (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) +#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ + (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) +#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) +#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) +#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) +#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) +#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) +#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) +#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ + (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) +#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ + (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) +#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) +#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) +#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) +#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) +#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ + /* (telecom) */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) +#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ + /* (telecom) */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) +#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) +#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) + +#define DCSR_RUN 0x00000001 /* DMA RUNing */ +#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ +#define DCSR_ERROR 0x00000004 /* DMA ERROR */ +#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ +#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ +#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ +#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ +#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ +#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ +#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ + +#define DBT_TC Fld (13, 0) /* Transfer Count */ +#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ +#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ + + +/* + * Liquid Crystal Display (LCD) control registers + * + * Registers + * LCCR0 Liquid Crystal Display (LCD) Control Register 0 + * (read/write). + * [Bits LDM, BAM, and ERM are only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + * LCSR Liquid Crystal Display (LCD) Status Register + * (read/write). + * [Bit LDD can be only read in versions 1.0 (rev. = 1) + * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be + * read and written (cleared) in versions 2.0 (rev. = 8) + * and higher.] + * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 1 (read/write). + * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 1 (read). + * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 2 (read/write). + * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 2 (read). + * LCCR1 Liquid Crystal Display (LCD) Control Register 1 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR2 Liquid Crystal Display (LCD) Control Register 2 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR3 Liquid Crystal Display (LCD) Control Register 3 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher. Bit PCP is only + * implemented in versions 2.0 (rev. = 8) and higher of + * the StrongARM SA-1100.] + * + * Clocks + * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). + * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). + * fpix, Tpix Frequency, period of the pixel clock. + * fln, Tln Frequency, period of the line clock. + * fac, Tac Frequency, period of the AC bias clock. + */ + +#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ +#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ + /* [byte] */ \ + (16*LCD_PEntrySp) +#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ + /* [byte] */ \ + (256*LCD_PEntrySp) +#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ + /* dummy-Palette Space [byte] */ \ + (16*LCD_PEntrySp) + +#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ +#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ +#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ +#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ +#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ +#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ + (0 << FShft (LCD_PBS)) +#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ + (1 << FShft (LCD_PBS)) +#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ + (2 << FShft (LCD_PBS)) + +#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ +#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ +#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ +#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ +#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ +#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ +#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ +#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ +#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ +#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ +#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ +#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ +#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ +#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ +#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ +#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ + /* (Alternative) */ + +#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ +#define _LCSR 0xB0100004 /* LCD Status Reg. */ +#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ + /* channel 1 */ +#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ + /* channel 1 */ +#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ + /* channel 2 */ +#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ + /* channel 2 */ +#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ +#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ +#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ + +#if LANGUAGE == C +#define LCCR0 /* LCD Control Reg. 0 */ \ + (*((volatile Word *) io_p2v (_LCCR0))) +#define LCSR /* LCD Status Reg. */ \ + (*((volatile Word *) io_p2v (_LCSR))) +#define DBAR1 /* LCD DMA Base Address Reg. */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBAR1))) +#define DCAR1 /* LCD DMA Current Address Reg. */ \ + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DCAR1))) +#define DBAR2 /* LCD DMA Base Address Reg. */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBAR2))) +#define DCAR2 /* LCD DMA Current Address Reg. */ \ + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DCAR2))) +#define LCCR1 /* LCD Control Reg. 1 */ \ + (*((volatile Word *) io_p2v (_LCCR1))) +#define LCCR2 /* LCD Control Reg. 2 */ \ + (*((volatile Word *) io_p2v (_LCCR2))) +#define LCCR3 /* LCD Control Reg. 3 */ \ + (*((volatile Word *) io_p2v (_LCCR3))) +#endif /* LANGUAGE == C */ + +#define LCCR0_LEN 0x00000001 /* LCD ENable */ +#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ +#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ +#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ +#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ + /* Select */ +#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ +#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ +#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ + /* interrupt Mask (disable) */ +#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ + /* interrupt Mask (disable) */ +#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ + /* IUU, OOL, OUL, OOU, and OUU) */ + /* interrupt Mask (disable) */ +#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ +#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ +#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ +#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ +#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ +#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ +#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ + /* display mode) */ +#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ + /* [Tmem] */ +#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ + /* [0..510 Tcpu] */ \ + ((Tcpu)/2 << FShft (LCCR0_PDD)) + +#define LCSR_LDD 0x00000001 /* LCD Disable Done */ +#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ +#define LCSR_BER 0x00000004 /* Bus ERror */ +#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ +#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ + /* panel */ +#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ + /* panel */ +#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ + /* panel */ +#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ + /* panel */ +#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ + /* panel */ +#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ + /* panel */ +#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ + /* panel */ +#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ + /* panel */ + +#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ +#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ + (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ + /* pulse Width - 2 [Tpix] (L_LCLK) */ +#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ + /* pulse Width [2..65 Tpix] */ \ + (((Tpix) - 2) << FShft (LCCR1_HSW)) +#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ + /* count - 1 [Tpix] */ +#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_ELW)) +#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ + /* Wait count - 1 [Tpix] */ +#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_BLW)) + +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ +#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ + (((Line) - 1) << FShft (LCCR2_LPP)) +#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ + /* Width - 1 [Tln] (L_FCLK) */ +#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ + /* Width [1..64 Tln] */ \ + (((Tln) - 1) << FShft (LCCR2_VSW)) +#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ + /* count [Tln] */ +#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_EFW)) +#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ + /* Wait count [Tln] */ +#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_BFW)) + +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ + /* [1..255] (L_PCLK) */ + /* fpix = fcpu/(2*(PCD + 2)) */ + /* Tpix = 2*(PCD + 2)*Tcpu */ +#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ + (((Div) - 4)/2 << FShft (LCCR3_PCD)) + /* fpix = fcpu/(2*Floor (Div/2)) */ + /* Tpix = 2*Floor (Div/2)*Tcpu */ +#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ + (((Div) - 3)/2 << FShft (LCCR3_PCD)) + /* fpix = fcpu/(2*Ceil (Div/2)) */ + /* Tpix = 2*Ceil (Div/2)*Tcpu */ +#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ + /* [Tln] (L_BIAS) */ +#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ + (((Div) - 2)/2 << FShft (LCCR3_ACB)) + /* fac = fln/(2*Floor (Div/2)) */ + /* Tac = 2*Floor (Div/2)*Tln */ +#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ + (((Div) - 1)/2 << FShft (LCCR3_ACB)) + /* fac = fln/(2*Ceil (Div/2)) */ + /* Tac = 2*Ceil (Div/2)*Tln */ +#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ + /* Interrupt */ +#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ + /* Off */ \ + (0 << FShft (LCCR3_API)) +#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ + /* [1..15] */ \ + ((Trans) << FShft (LCCR3_API)) +#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ + /* Polarity (L_FCLK) */ +#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ + /* active High */ +#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ + /* active Low */ +#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ + /* pulse Polarity (L_LCLK) */ +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ + /* pulse active High */ +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ + /* pulse active Low */ +#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ +#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ +#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ +#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ + /* active display mode) */ +#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ +#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ + + +#undef C +#undef Assembly diff --git a/include/_exports.h b/include/_exports.h new file mode 100644 index 0000000..61dcaaf --- /dev/null +++ b/include/_exports.h @@ -0,0 +1,18 @@ +EXPORT_FUNC(get_version) +EXPORT_FUNC(getc) +EXPORT_FUNC(tstc) +EXPORT_FUNC(putc) +EXPORT_FUNC(puts) +EXPORT_FUNC(printf) +EXPORT_FUNC(install_hdlr) +EXPORT_FUNC(free_hdlr) +EXPORT_FUNC(malloc) +EXPORT_FUNC(free) +EXPORT_FUNC(udelay) +EXPORT_FUNC(get_timer) +EXPORT_FUNC(vprintf) +EXPORT_FUNC(do_reset) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +EXPORT_FUNC(i2c_write) +EXPORT_FUNC(i2c_read) +#endif /* CFG_CMD_I2C */ diff --git a/include/altera.h b/include/altera.h new file mode 100644 index 0000000..74b6729 --- /dev/null +++ b/include/altera.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include + +#ifndef _ALTERA_H_ +#define _ALTERA_H_ + +/* + * See include/xilinx.h for another working example. + */ + +/* Altera Model definitions + *********************************************************************/ +#define CFG_ACEX1K CFG_FPGA_DEV( 0x1 ) + +#define CFG_ALTERA_ACEX1K (CFG_FPGA_ALTERA | CFG_ACEX1K) +/* Add new models here */ + +/* Altera Interface definitions + *********************************************************************/ +#define CFG_ALTERA_IF_PS CFG_FPGA_IF( 0x1 ) /* passive serial */ +/* Add new interfaces here */ + +typedef enum { /* typedef Altera_iface */ + min_altera_iface_type, /* insert all new types after this */ + passive_serial, /* serial data and external clock */ + passive_parallel_synchronous, /* parallel data */ + passive_parallel_asynchronous, /* parallel data */ + passive_serial_asynchronous, /* serial data w/ internal clock (not used) */ + altera_jtag_mode, /* jtag/tap serial (not used ) */ + max_altera_iface_type /* insert all new types before this */ +} Altera_iface; /* end, typedef Altera_iface */ + +typedef enum { /* typedef Altera_Family */ + min_altera_type, /* insert all new types after this */ + Altera_ACEX1K, /* ACEX1K Family */ +/* Add new models here */ + max_altera_type /* insert all new types before this */ +} Altera_Family; /* end, typedef Altera_Family */ + +typedef struct { /* typedef Altera_desc */ + Altera_Family family; /* part type */ + Altera_iface iface; /* interface type */ + size_t size; /* bytes of data part can accept */ + void * iface_fns;/* interface function table */ + void * base; /* base interface address */ + int cookie; /* implementation specific cookie */ +} Altera_desc; /* end, typedef Altera_desc */ + +/* Generic Altera Functions + *********************************************************************/ +extern int altera_load( Altera_desc *desc, void *image, size_t size ); +extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize ); +extern int altera_info( Altera_desc *desc ); +extern int altera_reloc( Altera_desc *desc, ulong reloc_offset ); + +/* Board specific implementation specific function types + *********************************************************************/ +typedef int (*Altera_pre_fn)( int cookie ); +typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie ); +typedef int (*Altera_status_fn)( int cookie ); +typedef int (*Altera_done_fn)( int cookie ); +typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); +typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); +typedef int (*Altera_abort_fn)( int cookie ); +typedef int (*Altera_post_fn)( int cookie ); + +#endif /* _ALTERA_H_ */ diff --git a/include/arm920t.h b/include/arm920t.h new file mode 100644 index 0000000..95f3323 --- /dev/null +++ b/include/arm920t.h @@ -0,0 +1,12 @@ +/************************************************ + * NAME : arm920t.h + * Version : 30 April 2002 * + * + * empty for now + ************************************************/ + +#ifndef __ARM920T_H__ +#define __ARM920T_H__ + + +#endif /*__ARM920T_H__*/ diff --git a/include/arm925t.h b/include/arm925t.h new file mode 100644 index 0000000..ab343ea --- /dev/null +++ b/include/arm925t.h @@ -0,0 +1,15 @@ +/************************************************ + * NAME : arm925t.h + * Version : 23 June 2003 * + ************************************************/ + +#ifndef __ARM925T_H__ +#define __ARM925T_H__ + +void gpioreserve(ushort mask); +void gpiosetdir(ushort mask, ushort in); +void gpiosetout(ushort mask, ushort out); +void gpioinit(void); +void archflashwp(void *archdata, int wp); + +#endif /*__ARM925T_H__*/ diff --git a/include/arm926ejs.h b/include/arm926ejs.h new file mode 100644 index 0000000..c660265 --- /dev/null +++ b/include/arm926ejs.h @@ -0,0 +1,8 @@ +/************************************************ + * NAME arm926ejs.h * + * Version : 23 June 2003 * + ************************************************/ +/* Currently empty */ +#ifndef __ARM926EJS_H__ +#define __ARM926EJS_H__ +#endif /*__ARM926EJS_H__*/ diff --git a/include/arm946es.h b/include/arm946es.h new file mode 100644 index 0000000..c23f3e7 --- /dev/null +++ b/include/arm946es.h @@ -0,0 +1,8 @@ +/************************************************ + * NAME arm946es.h * + * $Version$ * + ************************************************/ +/* Currently empty */ +#ifndef __ARM946ES_H__ +#define __ARM946ES_H__ +#endif /*__ARM946ES_H__*/ diff --git a/include/armcoremodule.h b/include/armcoremodule.h new file mode 100644 index 0000000..7dac6f8 --- /dev/null +++ b/include/armcoremodule.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2005 + * ARM Ltd. + * Peter Pearse, + * Configuration for ARM Core Modules. + * No standalonw port yet available + * - this file is included by both integratorap.h & integratorcp.h + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARMCOREMODULE_H +#define __ARMCOREMODULE_H + +#define CM_BASE 0x10000000 + +/* CM registers common to all CMs */ +/* Note that observed values after reboot into the ARM Boot Monitor + have been used as defaults, rather than the POR values */ +#define OS_CTRL 0x0000000C +#define CMMASK_REMAP 0x00000005 /* set remap & led */ +#define CMMASK_RESET 0x00000008 +#define OS_LOCK 0x00000014 +#define CMVAL_LOCK1 0x0000A000 /* locking value */ +#define CMVAL_LOCK2 0x0000005F /* locking value */ +#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */ +#define OS_SDRAM 0x00000020 +#define OS_INIT 0x00000024 +#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ +#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ +#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */ +#define CMMASK_LE 0xFFFFFFF7 /* little endian */ +#define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */ + /* - observed reset value of */ + /* CM926EJ-S */ + /* CM1136-EJ-S */ + +#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) +#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */ + /* - PLL test clock bypassed */ + /* - bus clock ratio 2 */ + /* - little endian */ + /* - vectors at zero */ +#endif /* CM1022xx */ + +/* Determine CM characteristics */ + +#undef CONFIG_CM_MULTIPLE_SSRAM +#undef CONFIG_CM_SPD_DETECT +#undef CONFIG_CM_REMAP +#undef CONFIG_CM_INIT +#undef CONFIG_CM_TCRAM + +#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S) +#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */ +#endif + +/* Excalibur core module has reduced functionality */ +#ifndef CONFIG_CM922T_XA10 +#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */ +#define OS_SPD 0x00000100 /* Address of SPD data */ +#define CONFIG_CM_REMAP /* CM supports remapping */ +#define CONFIG_CM_INIT /* CM has initialization reg */ +#endif /* NOT EXCALIBUR */ + +#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \ + defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \ + defined(CONFIG_CM1136JF_S) +#define CONFIG_CM_TCRAM /* CM has TCRAM */ +#endif + +#ifdef CONFIG_CM_SPD_DETECT +#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */ +#endif + +#endif /* __ARMCOREMODULE_H */ diff --git a/include/asm-arm/arch-arm1136/bits.h b/include/asm-arm/arch-arm1136/bits.h new file mode 100644 index 0000000..8522335 --- /dev/null +++ b/include/asm-arm/arch-arm1136/bits.h @@ -0,0 +1,48 @@ +/* bits.h + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/include/asm-arm/arch-arm1136/clocks.h b/include/asm-arm/arch-arm1136/clocks.h new file mode 100644 index 0000000..2a95af1 --- /dev/null +++ b/include/asm-arm/arch-arm1136/clocks.h @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_CLOCKS_H_ +#define _OMAP24XX_CLOCKS_H_ + +#define COMMIT_DIVIDERS 0x1 + +#define MODE_BYPASS_FAST 0x2 +#define APLL_LOCK 0xc +#ifdef CONFIG_APTIX +#define DPLL_LOCK 0x1 /* stay in bypass mode */ +#else +#define DPLL_LOCK 0x3 /* DPLL lock */ +#endif + +/****************************************************************************; +; PRCM Scheme II +; +; Enable clocks and DPLL for: +; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 +; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] +; DSPI=100 6 CM_CLKSEL_DSP[6:5] +; DSP_S bypass CM_CLKSEL_DSP[7] +; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] +; IVAF=100 auto +; IVAI auto +; IVA_MPU auto +; IVA_S bypass CM_CLKSEL_DSP[13] +; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] +; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=100 auto +; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] +; L4=100Mhz 6 +; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define II_DPLL_OUT_X2 0x2 /* x2 core out */ +#define II_MPU_DIV 0x2 /* mpu = core/2 */ +#define II_DSP_DIV 0x343 /* dsp & iva divider */ +#define II_GFX_DIV 0x2 +#define II_BUS_DIV 0x04601026 +#define II_DPLL_300 0x01832100 + +/****************************************************************************; +; PRCM Scheme III +; +; Enable clocks and DPLL for: +; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 +; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] +; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] +; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] +; DSP_S ACTIVATED CM_CLKSEL_DSP[7] +; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] +; IVAF=88.67 auto +; IVAI auto +; IVA_MPU auto +; IVA_S ACTIVATED CM_CLKSEL_DSP[13] +; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: +; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=88.67 auto +; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] +; L4=66.5Mhz /8 +; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define III_DPLL_OUT_X2 0x2 /* x2 core out */ +#define III_MPU_DIV 0x2 /* mpu = core/2 */ +#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ +#define III_GFX_DIV 0x2 +#define III_BUS_DIV 0x08301044 +#define III_DPLL_266 0x01885500 + +/* set defaults for boot up */ +#ifdef PRCM_CONFIG_II +# define DPLL_OUT II_DPLL_OUT_X2 +# define MPU_DIV II_MPU_DIV +# define DSP_DIV II_DSP_DIV +# define GFX_DIV II_GFX_DIV +# define BUS_DIV II_BUS_DIV +# define DPLL_VAL II_DPLL_300 +#elif PRCM_CONFIG_III +# define DPLL_OUT III_DPLL_OUT_X2 +# define MPU_DIV III_MPU_DIV +# define DSP_DIV III_DSP_DIV +# define GFX_DIV III_GFX_DIV +# define BUS_DIV III_BUS_DIV +# define DPLL_VAL III_DPLL_266 +#endif + +/* lock delay time out */ +#define LDELAY 12000000 + +#endif diff --git a/include/asm-arm/arch-arm1136/i2c.h b/include/asm-arm/arch-arm1136/i2c.h new file mode 100644 index 0000000..7248950 --- /dev/null +++ b/include/asm-arm/arch-arm1136/i2c.h @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_I2C_H_ +#define _OMAP24XX_I2C_H_ + +#define I2C_BASE 0x48070000 +#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */ + +#define I2C_REV (I2C_BASE + 0x00) +#define I2C_IE (I2C_BASE + 0x04) +#define I2C_STAT (I2C_BASE + 0x08) +#define I2C_IV (I2C_BASE + 0x0c) +#define I2C_BUF (I2C_BASE + 0x14) +#define I2C_CNT (I2C_BASE + 0x18) +#define I2C_DATA (I2C_BASE + 0x1c) +#define I2C_SYSC (I2C_BASE + 0x20) +#define I2C_CON (I2C_BASE + 0x24) +#define I2C_OA (I2C_BASE + 0x28) +#define I2C_SA (I2C_BASE + 0x2c) +#define I2C_PSC (I2C_BASE + 0x30) +#define I2C_SCLL (I2C_BASE + 0x34) +#define I2C_SCLH (I2C_BASE + 0x38) +#define I2C_SYSTEST (I2C_BASE + 0x3c) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_GC_IE (1 << 5) +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_GC (1 << 5) +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ + +#endif diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-arm1136/mem.h new file mode 100644 index 0000000..c81f1c4 --- /dev/null +++ b/include/asm-arm/arch-arm1136/mem.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_MEM_H_ +#define _OMAP24XX_MEM_H_ + +#define SDRC_CS0_OSET 0x0 +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ + +#ifndef __ASSEMBLY__ +/* struct's for holding data tables for current boards, they are getting used + early in init when NO global access are there */ +struct sdrc_data_s { + u32 sdrc_sharing; + u32 sdrc_mdcfg_0_ddr; + u32 sdrc_mdcfg_0_sdr; + u32 sdrc_actim_ctrla_0; + u32 sdrc_actim_ctrlb_0; + u32 sdrc_rfr_ctrl; + u32 sdrc_mr_0_ddr; + u32 sdrc_mr_0_sdr; + u32 sdrc_dllab_ctrl; +} /*__attribute__ ((packed))*/; +typedef struct sdrc_data_s sdrc_data_t; + +typedef enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +} mem_t; + +#endif + +/* Slower full frequency range default timings for x32 operation*/ +#define H4_2420_SDRC_SHARING 0x00000100 +#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ +#define H4_2420_SDRC_MR_0_SDR 0x00000031 +#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ +#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ +#define H4_2420_SDRC_MR_0_DDR 0x00000032 + +#define H4_2422_SDRC_SHARING 0x00004b00 +#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */ +#define H4_2422_SDRC_MR_0_DDR 0x00000032 + +/* ES1 work around timings */ +#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ +#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 +#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ + +/* optimized timings good for current shipping parts */ +#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 +#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e +#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ +#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ +#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 +#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/ +#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */ + +#ifdef PRCM_CONFIG_II +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +#elif PRCM_CONFIG_III +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz +#endif + + +/* GPMC settings */ +#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ +# ifdef CFG_NAND_BOOT +# define H4_24XX_GPMC_CONFIG1_0 0x0 +# define H4_24XX_GPMC_CONFIG2_0 0x00141400 +# define H4_24XX_GPMC_CONFIG3_0 0x00141400 +# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 +# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 +# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 +# else /* else NOR */ +# define H4_24XX_GPMC_CONFIG1_0 0x3 +# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01 +# define H4_24XX_GPMC_CONFIG3_0 0x00050502 +# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06 +# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F +# endif /* endif CFG_NAND_BOOT */ +# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) +# define H4_24XX_GPMC_CONFIG1_1 0x00011000 +# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00 +# define H4_24XX_GPMC_CONFIG3_1 0x00080802 +# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F +# define H4_24XX_GPMC_CONFIG6_1 0x000003C2 +# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) +#endif /* endif PRCM_CONFIG_II */ + +#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ +# ifdef CFG_NAND_BOOT +# define H4_24XX_GPMC_CONFIG1_0 0x0 +# define H4_24XX_GPMC_CONFIG2_0 0x00141400 +# define H4_24XX_GPMC_CONFIG3_0 0x00141400 +# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01 +# define H4_24XX_GPMC_CONFIG5_0 0x010C1414 +# define H4_24XX_GPMC_CONFIG6_0 0x00000A80 +# else /* NOR boot */ +# define H4_24XX_GPMC_CONFIG1_0 0x3 +# define H4_24XX_GPMC_CONFIG2_0 0x00151501 +# define H4_24XX_GPMC_CONFIG3_0 0x00060602 +# define H4_24XX_GPMC_CONFIG4_0 0x10081008 +# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F +# define H4_24XX_GPMC_CONFIG6_0 0x000004c4 +# endif /* endif CFG_NAND_BOOT */ +# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24)) +# define H4_24XX_GPMC_CONFIG1_1 0x00011000 +# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01 +# define H4_24XX_GPMC_CONFIG3_1 0x00080803 +# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09 +# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F +# define H4_24XX_GPMC_CONFIG6_1 0x000004C4 +# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) +#endif /* endif CFG_PRCM_III */ + +#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-arm1136/mux.h new file mode 100644 index 0000000..67c8419 --- /dev/null +++ b/include/asm-arm/arch-arm1136/mux.h @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP2420_MUX_H_ +#define _OMAP2420_MUX_H_ + +#ifndef __ASSEMBLY__ +typedef unsigned char uint8; +typedef unsigned int uint32; + +void muxSetupSDRC(void); +void muxSetupGPMC(void); +void muxSetupUsb0(void); +void muxSetupUart3(void); +void muxSetupI2C1(void); +void muxSetupUART1(void); +void muxSetupLCD(void); +void muxSetupCamera(void); +void muxSetupMMCSD(void) ; +void muxSetupTouchScreen(void) ; +void muxSetupHDQ(void); +#endif + +#define USB_OTG_CTRL ((volatile uint32 *)0x4805E30C) + +/* Pin Muxing registers used for HDQ (Smart battery) */ +#define CONTROL_PADCONF_HDQ_SIO ((volatile unsigned char *)0x48000115) + +/* Pin Muxing registers used for GPMC */ +#define CONTROL_PADCONF_GPMC_D2_BYTE0 ((volatile unsigned char *)0x48000088) +#define CONTROL_PADCONF_GPMC_D2_BYTE1 ((volatile unsigned char *)0x48000089) +#define CONTROL_PADCONF_GPMC_D2_BYTE2 ((volatile unsigned char *)0x4800008A) +#define CONTROL_PADCONF_GPMC_D2_BYTE3 ((volatile unsigned char *)0x4800008B) + +#define CONTROL_PADCONF_GPMC_NCS0_BYTE0 ((volatile unsigned char *)0x4800008C) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F) + +/* Pin Muxing registers used for SDRC */ +#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0) +#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1) +#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2) +#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3) + +#define CONTROL_PADCONF_SDRC_A14_BYTE0 ((volatile unsigned char *)0x48000030) +#define CONTROL_PADCONF_SDRC_A14_BYTE1 ((volatile unsigned char *)0x48000031) +#define CONTROL_PADCONF_SDRC_A14_BYTE2 ((volatile unsigned char *)0x48000032) +#define CONTROL_PADCONF_SDRC_A14_BYTE3 ((volatile unsigned char *)0x48000033) + +/* Pin Muxing registers used for Touch Screen (SPI) */ +#define CONTROL_PADCONF_SPI1_CLK ((volatile unsigned char *)0x480000FF) +#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100) +#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101) +#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102) + +#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B) + +/* Pin Muxing registers used for MMCSD */ +#define CONTROL_PADCONF_MMC_CLKI ((volatile unsigned char *)0x480000FE) +#define CONTROL_PADCONF_MMC_CLKO ((volatile unsigned char *)0x480000F3) +#define CONTROL_PADCONF_MMC_CMD ((volatile unsigned char *)0x480000F4) +#define CONTROL_PADCONF_MMC_DAT0 ((volatile unsigned char *)0x480000F5) +#define CONTROL_PADCONF_MMC_DAT1 ((volatile unsigned char *)0x480000F6) +#define CONTROL_PADCONF_MMC_DAT2 ((volatile unsigned char *)0x480000F7) +#define CONTROL_PADCONF_MMC_DAT3 ((volatile unsigned char *)0x480000F8) +#define CONTROL_PADCONF_MMC_DAT_DIR0 ((volatile unsigned char *)0x480000F9) +#define CONTROL_PADCONF_MMC_DAT_DIR1 ((volatile unsigned char *)0x480000FA) +#define CONTROL_PADCONF_MMC_DAT_DIR2 ((volatile unsigned char *)0x480000FB) +#define CONTROL_PADCONF_MMC_DAT_DIR3 ((volatile unsigned char *)0x480000FC) +#define CONTROL_PADCONF_MMC_CMD_DIR ((volatile unsigned char *)0x480000FD) + +#define CONTROL_PADCONF_SDRC_A14 ((volatile unsigned char *)0x48000030) +#define CONTROL_PADCONF_SDRC_A13 ((volatile unsigned char *)0x48000031) + +/* Pin Muxing registers used for CAMERA */ +#define CONTROL_PADCONF_SYS_NRESWARM ((volatile unsigned char *)0x4800012B) + +#define CONTROL_PADCONF_CAM_XCLK ((volatile unsigned char *)0x480000DC) +#define CONTROL_PADCONF_CAM_LCLK ((volatile unsigned char *)0x480000DB) +#define CONTROL_PADCONF_CAM_VS ((volatile unsigned char *)0x480000DA) +#define CONTROL_PADCONF_CAM_HS ((volatile unsigned char *)0x480000D9) +#define CONTROL_PADCONF_CAM_D0 ((volatile unsigned char *)0x480000D8) +#define CONTROL_PADCONF_CAM_D1 ((volatile unsigned char *)0x480000D7) +#define CONTROL_PADCONF_CAM_D2 ((volatile unsigned char *)0x480000D6) +#define CONTROL_PADCONF_CAM_D3 ((volatile unsigned char *)0x480000D5) +#define CONTROL_PADCONF_CAM_D4 ((volatile unsigned char *)0x480000D4) +#define CONTROL_PADCONF_CAM_D5 ((volatile unsigned char *)0x480000D3) +#define CONTROL_PADCONF_CAM_D6 ((volatile unsigned char *)0x480000D2) +#define CONTROL_PADCONF_CAM_D7 ((volatile unsigned char *)0x480000D1) +#define CONTROL_PADCONF_CAM_D8 ((volatile unsigned char *)0x480000D0) +#define CONTROL_PADCONF_CAM_D9 ((volatile unsigned char *)0x480000CF) + +/* Pin Muxing registers used for LCD */ +#define CONTROL_PADCONF_DSS_D0 ((volatile unsigned char *)0x480000B3) +#define CONTROL_PADCONF_DSS_D1 ((volatile unsigned char *)0x480000B4) +#define CONTROL_PADCONF_DSS_D2 ((volatile unsigned char *)0x480000B5) +#define CONTROL_PADCONF_DSS_D3 ((volatile unsigned char *)0x480000B6) +#define CONTROL_PADCONF_DSS_D4 ((volatile unsigned char *)0x480000B7) +#define CONTROL_PADCONF_DSS_D5 ((volatile unsigned char *)0x480000B8) +#define CONTROL_PADCONF_DSS_D6 ((volatile unsigned char *)0x480000B9) +#define CONTROL_PADCONF_DSS_D7 ((volatile unsigned char *)0x480000BA) +#define CONTROL_PADCONF_DSS_D8 ((volatile unsigned char *)0x480000BB) +#define CONTROL_PADCONF_DSS_D9 ((volatile unsigned char *)0x480000BC) +#define CONTROL_PADCONF_DSS_D10 ((volatile unsigned char *)0x480000BD) +#define CONTROL_PADCONF_DSS_D11 ((volatile unsigned char *)0x480000BE) +#define CONTROL_PADCONF_DSS_D12 ((volatile unsigned char *)0x480000BF) +#define CONTROL_PADCONF_DSS_D13 ((volatile unsigned char *)0x480000C0) +#define CONTROL_PADCONF_DSS_D14 ((volatile unsigned char *)0x480000C1) +#define CONTROL_PADCONF_DSS_D15 ((volatile unsigned char *)0x480000C2) +#define CONTROL_PADCONF_DSS_D16 ((volatile unsigned char *)0x480000C3) +#define CONTROL_PADCONF_DSS_D17 ((volatile unsigned char *)0x480000C4) +#define CONTROL_PADCONF_DSS_PCLK ((volatile unsigned char *)0x480000CB) +#define CONTROL_PADCONF_DSS_VSYNC ((volatile unsigned char *)0x480000CC) +#define CONTROL_PADCONF_DSS_HSYNC ((volatile unsigned char *)0x480000CD) +#define CONTROL_PADCONF_DSS_ACBIAS ((volatile unsigned char *)0x480000CE) + +/* Pin Muxing registers used for UART1 */ +#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) +#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) +#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) +#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) + +/* Pin Muxing registers used for I2C1 */ +#define CONTROL_PADCONF_I2C1_SCL ((volatile unsigned char *)0x48000111) +#define CONTROL_PADCONF_I2C1_SDA ((volatile unsigned char *)0x48000112) + +/* Pin Muxing registres used for USB0. */ +#define CONTROL_PADCONF_USB0_PUEN ((volatile uint8 *)0x4800011D) +#define CONTROL_PADCONF_USB0_VP ((volatile uint8 *)0x4800011E) +#define CONTROL_PADCONF_USB0_VM ((volatile uint8 *)0x4800011F) +#define CONTROL_PADCONF_USB0_RCV ((volatile uint8 *)0x48000120) +#define CONTROL_PADCONF_USB0_TXEN ((volatile uint8 *)0x48000121) +#define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122) +#define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123) + +/* Pin Muxing registers used for UART3/IRDA */ +#define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118) +#define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119) + +#endif diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h new file mode 100644 index 0000000..d833035 --- /dev/null +++ b/include/asm-arm/arch-arm1136/omap2420.h @@ -0,0 +1,221 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP2420_SYS_H_ +#define _OMAP2420_SYS_H_ + +#include + +/* + * 2420 specific Section + */ + +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 +/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */ + +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 + +/* CONTROL */ +#define OMAP2420_CTRL_BASE (0x48000000) +#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) + +/* device type */ +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* TAP information */ +#define OMAP2420_TAP_BASE (0x48014000) +#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) + +/* GPMC */ +#define OMAP2420_GPMC_BASE (0x6800A000) +#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) +#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) +#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) +#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) +#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) +#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) +#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) +#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) +#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) +#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) +#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) +#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) +#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) +#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) +#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) +#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) + +/* SMS */ +#define OMAP2420_SMS_BASE 0x68008000 +#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) +#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0) +# define BURSTCOMPLETE_GROUP7 BIT31 + +/* SDRC */ +#define OMAP2420_SDRC_BASE 0x68009000 +#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) +#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) +#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) +#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) +#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) +#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) +#define OMAP2420_SDRC_CS0 0x80000000 +#define OMAP2420_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + + +/* UART */ +#define OMAP2420_UART1 0x4806A000 +#define OMAP2420_UART2 0x4806C000 +#define OMAP2420_UART3 0x4806E000 + +/* General Purpose Timers */ +#define OMAP2420_GPT1 0x48028000 +#define OMAP2420_GPT2 0x4802A000 +#define OMAP2420_GPT3 0x48078000 +#define OMAP2420_GPT4 0x4807A000 +#define OMAP2420_GPT5 0x4807C000 +#define OMAP2420_GPT6 0x4807E000 +#define OMAP2420_GPT7 0x48080000 +#define OMAP2420_GPT8 0x48082000 +#define OMAP2420_GPT9 0x48084000 +#define OMAP2420_GPT10 0x48086000 +#define OMAP2420_GPT11 0x48088000 +#define OMAP2420_GPT12 0x4808A000 + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE 0x48020000 +#define WD2_BASE 0x48022000 +#define WD3_BASE 0x48024000 +#define WD4_BASE 0x48026000 +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define OMAP2420_CM_BASE 0x48008000 +#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) +#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) +#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) +#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) +#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) +#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) +#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) +#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) +#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) +#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) +#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) +#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) +#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) +#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) +#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) +#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) + +/* + * H4 specific Section + */ + +/* + * The 2420's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + */ +#if defined(CONFIG_OMAP2420H4) +/* GPMC */ +#ifdef CONFIG_VIRTIO_A /* Pre version B */ +# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x04000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#else +# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x08000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#endif + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) +#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) +#endif /* endif CONFIG_2420H4 */ + +#endif diff --git a/include/asm-arm/arch-arm1136/sizes.h b/include/asm-arm/arch-arm1136/sizes.h new file mode 100644 index 0000000..aaba18f --- /dev/null +++ b/include/asm-arm/arch-arm1136/sizes.h @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/include/asm-arm/arch-arm1136/sys_info.h b/include/asm-arm/arch-arm1136/sys_info.h new file mode 100644 index 0000000..53c231a --- /dev/null +++ b/include/asm-arm/arch-arm1136/sys_info.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_SYS_INFO_H_ +#define _OMAP24XX_SYS_INFO_H_ + +typedef struct h4_system_data { + /* base board info */ + u32 base_b_rev; /* rev from base board i2c */ + /* cpu board info */ + u32 cpu_b_rev; /* rev from cpu board i2c */ + u32 cpu_b_mux; /* mux type on daughter board */ + u32 cpu_b_ddr_type; /* mem type */ + u32 cpu_b_ddr_speed; /* ddr speed rating */ + u32 cpu_b_switches; /* boot ctrl switch settings */ + /* cpu info */ + u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ + u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ +} h4_sys_data; + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_2420 0x2420 +#define CPU_2422 0x2422 /* 2420 + 64M stacked */ +#define CPU_2423 0x2423 /* 2420 + 96M stacked */ + +#define CPU_2422_ES1 1 +#define CPU_2422_ES2 2 +#define CPU_2420_ES1 1 +#define CPU_2420_ES2 2 +#define CPU_2420_2422_ES1 1 + +#define CPU_2420_CHIPID 0x0B5D9000 +#define CPU_24XX_ID_MASK 0x0FFFF000 +#define CPU_242X_REV_MASK 0xF0000000 +#define CPU_242X_PID_MASK 0x000F0000 + +#define BOARD_H4_MENELAUS 1 +#define BOARD_H4_SDP 2 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ + +#endif diff --git a/include/asm-arm/arch-arm1136/sys_proto.h b/include/asm-arm/arch-arm1136/sys_proto.h new file mode 100644 index 0000000..9d8e5b2 --- /dev/null +++ b/include/asm-arm/arch-arm1136/sys_proto.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_SYS_PROTO_H_ +#define _OMAP24XX_SYS_PROTO_H_ + +void prcm_init(void); +void memif_init(void); +void sdrc_init(void); +void do_sdrc_init(u32,u32); +void gpmc_init(void); + +void ether_init(void); +void watchdog_init(void); +void set_muxconf_regs(void); +void peripheral_enable(void); + +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 get_mem_type(void); +u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 is_gpmc_muxed(void); +u32 get_gpmc0_type(void); +u32 get_gpmc0_width(void); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +u32 get_board_type(void); +void display_board_info(u32); +void update_mux(u32,u32); +u32 get_sdr_cs_size(u32 offset); + +u32 running_in_sdram(void); +u32 running_in_sram(void); +u32 running_in_flash(void); +u32 running_from_internal_boot(void); +u32 get_device_type(void); +#endif diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h new file mode 100644 index 0000000..3056ca7 --- /dev/null +++ b/include/asm-arm/arch-arm720t/hardware.h @@ -0,0 +1,43 @@ +#ifndef __ARM7_HW_H +#define __ARM7_HW_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_S3C4510B) +#include +#elif defined(CONFIG_NETARM) +#include +#elif defined(CONFIG_IMPA7) +/* include IMPA7 specific hardware file if there was one */ +#elif defined(CONFIG_EP7312) +/* include EP7312 specific hardware file if there was one */ +#elif defined(CONFIG_ARMADILLO) +/* include armadillo specific hardware file if there was one */ +#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +/* include IntegratorCP/CM720T specific hardware file if there was one */ +#else +#error No hardware file defined for this configuration +#endif + +#endif /* __ARM7_HW_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_dma_module.h b/include/asm-arm/arch-arm720t/netarm_dma_module.h new file mode 100644 index 0000000..328eaf0 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_dma_module.h @@ -0,0 +1,182 @@ +/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + * David Smith + */ + +#ifndef __NETARM_DMA_MODULE_REGISTERS_H +#define __NETARM_DMA_MODULE_REGISTERS_H + +/* GEN unit register offsets */ + +#define NETARM_DMA_MODULE_BASE (0xFF900000) + +#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c))) + +#define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00) +#define NETARM_DMA1A_CONTROL (0x10) +#define NETARM_DMA1A_STATUS (0x14) +#define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20) +#define NETARM_DMA1B_CONTROL (0x30) +#define NETARM_DMA1B_STATUS (0x34) +#define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40) +#define NETARM_DMA1C_CONTROL (0x50) +#define NETARM_DMA1C_STATUS (0x54) +#define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60) +#define NETARM_DMA1D_CONTROL (0x70) +#define NETARM_DMA1D_STATUS (0x74) + +#define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80) +#define NETARM_DMA2_CONTROL (0x90) +#define NETARM_DMA2_STATUS (0x94) + +#define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0) +#define NETARM_DMA3_CONTROL (0xB0) +#define NETARM_DMA3_STATUS (0xB4) + +#define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0) +#define NETARM_DMA4_CONTROL (0xD0) +#define NETARM_DMA4_STATUS (0xD4) + +#define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0) +#define NETARM_DMA5_CONTROL (0xF0) +#define NETARM_DMA5_STATUS (0xF4) + +#define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100) +#define NETARM_DMA6_CONTROL (0x110) +#define NETARM_DMA6_STATUS (0x114) + +#define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120) +#define NETARM_DMA7_CONTROL (0x130) +#define NETARM_DMA7_STATUS (0x134) + +#define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140) +#define NETARM_DMA8_CONTROL (0x150) +#define NETARM_DMA8_STATUS (0x154) + +#define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160) +#define NETARM_DMA9_CONTROL (0x170) +#define NETARM_DMA9_STATUS (0x174) + +#define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180) +#define NETARM_DMA10_CONTROL (0x190) +#define NETARM_DMA10_STATUS (0x194) + +/* select bitfield defintions */ + +/* DMA Control Register ( 0xFF90_0XX0 ) */ + +#define NETARM_DMA_CTL_ENABLE (0x80000000) + +#define NETARM_DMA_CTL_ABORT (0x40000000) + +#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000) +#define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000) +#define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000) +#define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000) + +#define NETARM_DMA_CTL_BUS_MASK (0x30000000) + +#define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000) +#define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000) +#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000) + +#define NETARM_DMA_CTL_BURST_NONE (0x00000000) +#define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000) +#define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000) + +#define NETARM_DMA_CTL_BURST_MASK (0x03000000) + +#define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000) + +#define NETARM_DMA_CTL_DST_INCREMENT (0x00100000) + +/* these apply only to ext xfers on DMA 3 or 4 */ + +#define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000) + +#define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000) +#define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000) +#define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000) + +#define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00) +#define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF) + +/* DMA Status Register ( 0xFF90_0XX4 ) */ + +#define NETARM_DMA_STAT_NC_INTPEN (0x80000000) +#define NETARM_DMA_STAT_EC_INTPEN (0x40000000) +#define NETARM_DMA_STAT_NR_INTPEN (0x20000000) +#define NETARM_DMA_STAT_CA_INTPEN (0x10000000) +#define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000) + +#define NETARM_DMA_STAT_NC_INT_EN (0x00800000) +#define NETARM_DMA_STAT_EC_INT_EN (0x00400000) +#define NETARM_DMA_STAT_NR_INT_EN (0x00200000) +#define NETARM_DMA_STAT_CA_INT_EN (0x00100000) +#define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000) + +#define NETARM_DMA_STAT_WRAP (0x00080000) +#define NETARM_DMA_STAT_IDONE (0x00040000) +#define NETARM_DMA_STAT_LAST (0x00020000) +#define NETARM_DMA_STAT_FULL (0x00010000) + +#define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF) + +/* DMA Buffer Descriptor Word 0 bitfields. */ + +#define NETARM_DMA_BD0_WRAP (0x80000000) +#define NETARM_DMA_BD0_IDONE (0x40000000) +#define NETARM_DMA_BD0_LAST (0x20000000) +#define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF) + +/* DMA Buffer Descriptor Word 1 bitfields. */ + +#define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000) +#define NETARM_DMA_BD1_FULL (0x00008000) +#define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF) + +#ifndef __ASSEMBLER__ + +typedef struct __NETARM_DMA_Buff_Desc_FlyBy +{ + unsigned int word0; + unsigned int word1; +} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ; + +typedef struct __NETARM_DMA_Buff_Desc_M_to_M +{ + unsigned int word0; + unsigned int word1; + unsigned int word2; + unsigned int word3; +} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ; + +#endif + +#endif diff --git a/include/asm-arm/arch-arm720t/netarm_eni_module.h b/include/asm-arm/arch-arm720t/netarm_eni_module.h new file mode 100644 index 0000000..317b354 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_eni_module.h @@ -0,0 +1,121 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_eni_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : David Smith + */ + +#ifndef __NETARM_ENI_MODULE_REGISTERS_H +#define __NETARM_ENI_MODULE_REGISTERS_H + +/* ENI unit register offsets */ + +/* #ifdef CONFIG_ARCH_NETARM */ +#define NETARM_ENI_MODULE_BASE (0xFFA00000) +/* #endif / * CONFIG_ARCH_NETARM */ + +#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c))) +#define get_eni_ctl_reg_addr(minor) \ + (get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor)) + +#define NETARM_ENI_GENERAL_CONTROL (0x00) +#define NETARM_ENI_STATUS_CONTROL (0x04) +#define NETARM_ENI_FIFO_MODE_DATA (0x08) + +#define NETARM_ENI_1284_PORT1_CONTROL (0x10) +#define NETARM_ENI_1284_PORT2_CONTROL (0x14) +#define NETARM_ENI_1284_PORT3_CONTROL (0x18) +#define NETARM_ENI_1284_PORT4_CONTROL (0x1c) + +#define NETARM_ENI_1284_CHANNEL1_DATA (0x20) +#define NETARM_ENI_1284_CHANNEL2_DATA (0x24) +#define NETARM_ENI_1284_CHANNEL3_DATA (0x28) +#define NETARM_ENI_1284_CHANNEL4_DATA (0x2c) + +#define NETARM_ENI_ENI_CONTROL (0x30) +#define NETARM_ENI_ENI_PULSED_INTR (0x34) +#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38) +#define NETARM_ENI_ENI_SHARED (0x3c) + +/* select bitfield defintions */ + +/* General Control Register (0xFFA0_0000) */ + +#define NETARM_ENI_GCR_ENIMODE_IEEE1284 (0x00000001) +#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004) +#define NETARM_ENI_GCR_ENIMODE_SHRAM8 (0x00000005) +#define NETARM_ENI_GCR_ENIMODE_FIFO16 (0x00000006) +#define NETARM_ENI_GCR_ENIMODE_FIFO8 (0x00000007) + +#define NETARM_ENI_GCR_ENIMODE_MASK (0x00000007) + +/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014, + 0xFFA0_0018, 0xFFA0_001c) */ + +#define NETARM_ENI_1284PC_PORT_ENABLE (0x80000000) +#define NETARM_ENI_1284PC_DMA_ENABLE (0x40000000) +#define NETARM_ENI_1284PC_OBE_INT_EN (0x20000000) +#define NETARM_ENI_1284PC_ACK_INT_EN (0x10000000) +#define NETARM_ENI_1284PC_ECP_MODE (0x08000000) +#define NETARM_ENI_1284PC_LOOPBACK_MODE (0x04000000) + +#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */ +#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */ +#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */ +#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */ +#define NETARM_ENI_1284PC_STROBE_MASK (0x03000000) + +#define NETARM_ENI_1284PC_MAN_STROBE_EN (0x00800000) +#define NETARM_ENI_1284PC_FAST_MODE (0x00400000) +#define NETARM_ENI_1284PC_BIDIR_MODE (0x00200000) + +#define NETARM_ENI_1284PC_MAN_STROBE (0x00080000) +#define NETARM_ENI_1284PC_AUTO_FEED (0x00040000) +#define NETARM_ENI_1284PC_INIT (0x00020000) +#define NETARM_ENI_1284PC_HSELECT (0x00010000) +#define NETARM_ENI_1284PC_FE_INT_EN (0x00008000) +#define NETARM_ENI_1284PC_EPP_MODE (0x00004000) +#define NETARM_ENI_1284PC_IBR_INT_EN (0x00002000) +#define NETARM_ENI_1284PC_IBR (0x00001000) + +#define NETARM_ENI_1284PC_RXFDB_1BYTE (0x00000400) +#define NETARM_ENI_1284PC_RXFDB_2BYTE (0x00000800) +#define NETARM_ENI_1284PC_RXFDB_3BYTE (0x00000c00) +#define NETARM_ENI_1284PC_RXFDB_4BYTE (0x00000000) + +#define NETARM_ENI_1284PC_RBCC (0x00000200) +#define NETARM_ENI_1284PC_RBCT (0x00000100) +#define NETARM_ENI_1284PC_ACK (0x00000080) +#define NETARM_ENI_1284PC_FIFO_E (0x00000040) +#define NETARM_ENI_1284PC_OBE (0x00000020) +#define NETARM_ENI_1284PC_ACK_INT (0x00000010) +#define NETARM_ENI_1284PC_BUSY (0x00000008) +#define NETARM_ENI_1284PC_PE (0x00000004) +#define NETARM_ENI_1284PC_PSELECT (0x00000002) +#define NETARM_ENI_1284PC_FAULT (0x00000001) + +#endif /* __NETARM_ENI_MODULE_REGISTERS_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_eth_module.h b/include/asm-arm/arch-arm720t/netarm_eth_module.h new file mode 100644 index 0000000..8f2f369 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_eth_module.h @@ -0,0 +1,160 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_eth_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Jackie Smith Cashion + * David Smith + */ + +#ifndef __NETARM_ETH_MODULE_REGISTERS_H +#define __NETARM_ETH_MODULE_REGISTERS_H + +/* ETH unit register offsets */ + +#define NETARM_ETH_MODULE_BASE (0xFF800000) + +#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c))) + +#define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */ +#define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */ +#define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */ +#define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */ +#define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */ +#define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */ + +#define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */ +#define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */ +#define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */ +#define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG + Gap Timer Reg */ +#define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back + IPG Gap Timer Reg */ +#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */ +#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */ +#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */ +#define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */ +#define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */ +#define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */ +#define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */ +#define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */ +#define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */ +#define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */ +#define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */ +#define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral + Counter */ +#define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */ +#define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address + Filter Reg */ +#define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address + Reg */ +#define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8) +#define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC) +#define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/ +#define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4) +#define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8) +#define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC) + +/* select bitfield defintions */ + +/* Ethernet General Control Register (0xFF80_0000) */ + +#define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */ +#define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */ +#define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */ +#define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ +#define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water + Mark. Start transmit + when FIFO is 50% + full. */ +#define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer + Descriptor Format */ + +/* Ethernet General Status Register (0xFF80_0004) */ + +#define NETARM_ETH_GST_RXFDB (0x30000000) +#define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register + Ready */ +#define NETARM_ETH_GST_RXFIFOH (0x04000000) +#define NETARM_ETH_GST_RXBR (0x02000000) +#define NETARM_ETH_GST_RXSKIP (0x01000000) + +#define NETARM_ETH_GST_TXBC (0x00020000) + + +/* Ethernet Transmit Status Register (0xFF80_0010) */ + +#define NETARM_ETH_TXSTAT_TXOK (0x00008000) + + +/* Ethernet Receive Status Register (0xFF80_0014) */ + +#define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000) +#define NETARM_ETH_RXSTAT_RXOK (0x00002000) + + +/* PCS Configuration Register (0xFF80_0408) */ + +#define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */ +#define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */ +#define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */ +#define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */ + +/* STL Configuration Register (0xFF80_0410) */ + +#define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */ +#define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */ + +/* MAC Configuration Register (0xFF80_0400) */ + +#define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit + Frame Sizes */ +#define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames + to 64 Bytes */ +#define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit + Frames */ + +/* MII (PHY) Command Register (0xFF80_0540) */ + +#define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */ + +/* MII Indicators Register (0xFF80_0550) */ + +#define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with + Read/Write */ + +/* SAL Station Address Filter Register (0xFF80_05C0) */ + +#define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */ +#define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast + Packets */ +#define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets + using Hash Table */ +#define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast + Packets */ + + +#endif /* __NETARM_GEN_MODULE_REGISTERS_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_gen_module.h b/include/asm-arm/arch-arm720t/netarm_gen_module.h new file mode 100644 index 0000000..13656a3 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_gen_module.h @@ -0,0 +1,186 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_gen_module.h + * + * Copyright (C) 2005 + * Art Shipkowski, Videon Central, Inc., + * + * Copyright (C) 2000, 2001 NETsilicon, Inc. + * Copyright (C) 2000, 2001 Red Hat, Inc. + * + * This software is copyrighted by Red Hat. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall Red Hat + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + * + * Modified to support NS7520 by Art Shipkowski. + */ + +#ifndef __NETARM_GEN_MODULE_REGISTERS_H +#define __NETARM_GEN_MODULE_REGISTERS_H + +/* GEN unit register offsets */ + +#define NETARM_GEN_MODULE_BASE (0xFFB00000) + +#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c))) + +#define NETARM_GEN_SYSTEM_CONTROL (0x00) +#define NETARM_GEN_STATUS_CONTROL (0x04) +#define NETARM_GEN_PLL_CONTROL (0x08) +#define NETARM_GEN_SOFTWARE_SERVICE (0x0c) + +#define NETARM_GEN_TIMER1_CONTROL (0x10) +#define NETARM_GEN_TIMER1_STATUS (0x14) +#define NETARM_GEN_TIMER2_CONTROL (0x18) +#define NETARM_GEN_TIMER2_STATUS (0x1c) + +#define NETARM_GEN_PORTA (0x20) +#ifndef CONFIG_NETARM_NS7520 +#define NETARM_GEN_PORTB (0x24) +#endif +#define NETARM_GEN_PORTC (0x28) + +#define NETARM_GEN_INTR_ENABLE (0x30) +#define NETARM_GEN_INTR_ENABLE_SET (0x34) +#define NETARM_GEN_INTR_ENABLE_CLR (0x38) +#define NETARM_GEN_INTR_STATUS_EN (0x34) +#define NETARM_GEN_INTR_STATUS_RAW (0x38) + +#define NETARM_GEN_CACHE_CONTROL1 (0x40) +#define NETARM_GEN_CACHE_CONTROL2 (0x44) + +/* select bitfield definitions */ + +/* System Control Register ( 0xFFB0_0000 ) */ + +#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000) +#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000) + +#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000) +#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000) +#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000) + +#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000) + +#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000) +#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000) +#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000) +#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000) +#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000) +#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000) +#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000) +#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000) + +#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000) +#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000) +#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000) +#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000) +#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000) + +#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000) +#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000) + +#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000) +#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000) + +#define NETARM_GEN_SYS_CFG_DMATST (0x00001000) + +#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800) + +#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400) + +#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200) + +#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100) + +#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080) + +/* PLL Control Register ( 0xFFB0_0008 ) */ + +#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000) + +#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \ + NETARM_GEN_PLL_CTL_PLLCNT_MASK) + +/* Defaults for POLTST and ICP Fields in PLL CTL */ +#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x) +#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6) +#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00) +#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C) + + +/* Software Service Register ( 0xFFB0_000C ) */ + +#define NETARM_GEN_SW_SVC_RESETA (0x123) +#define NETARM_GEN_SW_SVC_RESETB (0x321) + +/* PORT C Register ( 0xFFB0_0028 ) */ + +#ifndef CONFIG_NETARM_NS7520 +#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) +#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) +#else +#define NETARM_GEN_PORT_MODE(x) ((x)<<24) +#define NETARM_GEN_PORT_DIR(x) ((x)<<16) +#define NETARM_GEN_PORT_CSF(x) ((x)<<8) +#endif + +/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ + +#define NETARM_GEN_TCTL_ENABLE (0x80000000) +#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000) + +#define NETARM_GEN_TCTL_USE_IRQ (0x00000000) +#define NETARM_GEN_TCTL_USE_FIQ (0x20000000) + +#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000) +#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) + +#define NETARM_GEN_TSTAT_INTPEN (0x40000000) +#if ~defined(CONFIG_NETARM_NS7520) +#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) +#else +#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF) +#endif + +/* prescale to msecs conversion */ + +#if !defined(CONFIG_NETARM_PLL_BYPASS) +#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ + NETARM_GEN_TSTAT_CTC_MASK ) + \ + 1 ) ) / (NETARM_XTAL_FREQ/1000) ) + +#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \ + NETARM_GEN_TSTAT_CTC_MASK ) | \ + NETARM_GEN_TCTL_USE_PRESCALE ) + +#else +#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ + NETARM_GEN_TSTAT_CTC_MASK ) + \ + 1 ) ) / (NETARM_XTAL_FREQ/1000) ) + +#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \ + NETARM_GEN_TSTAT_CTC_MASK ) | \ + NETARM_GEN_TCTL_USE_PRESCALE ) +#endif + +#endif diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h new file mode 100644 index 0000000..f0529fd --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h @@ -0,0 +1,184 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_mem_module.h + * + * Copyright (C) 2005 + * Art Shipkowski, Videon Central, Inc., + * + * Copyright (C) 2000, 2001 NETsilicon, Inc. + * Copyright (C) 2000, 2001 Red Hat, Inc. + * + * This software is copyrighted by Red Hat. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall Red Hat + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + * + * Modified to support NS7520 by Art Shipkowski. + */ + +#ifndef __NETARM_MEM_MODULE_REGISTERS_H +#define __NETARM_MEM_MODULE_REGISTERS_H + +/* GEN unit register offsets */ + +#define NETARM_MEM_MODULE_BASE (0xFFC00000) + +#define NETARM_MEM_MODULE_CONFIG (0x00) +#define NETARM_MEM_CS0_BASE_ADDR (0x10) +#define NETARM_MEM_CS0_OPTIONS (0x14) +#define NETARM_MEM_CS1_BASE_ADDR (0x20) +#define NETARM_MEM_CS1_OPTIONS (0x24) +#define NETARM_MEM_CS2_BASE_ADDR (0x30) +#define NETARM_MEM_CS2_OPTIONS (0x34) +#define NETARM_MEM_CS3_BASE_ADDR (0x40) +#define NETARM_MEM_CS3_OPTIONS (0x44) +#define NETARM_MEM_CS4_BASE_ADDR (0x50) +#define NETARM_MEM_CS4_OPTIONS (0x54) + +/* select bitfield defintions */ + +/* Module Configuration Register ( 0xFFC0_0000 ) */ + +#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000) +#define NETARM_MEM_CFG_REFRESH_EN (0x00800000) + +#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000) +#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000) +#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000) +#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000) + +#define NETARM_MEM_CFG_PORTC_AMUX (0x00100000) + +#define NETARM_MEM_CFG_A27_ADDR (0x00080000) +#define NETARM_MEM_CFG_A27_CS0OE (0x00000000) + +#define NETARM_MEM_CFG_A26_ADDR (0x00040000) +#define NETARM_MEM_CFG_A26_CS0WE (0x00000000) + +#define NETARM_MEM_CFG_A25_ADDR (0x00020000) +#define NETARM_MEM_CFG_A25_BLAST (0x00000000) + +#define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000) + + +/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ +/* the expression will round down, so make sure to reverse it to verify */ +/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */ +/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */ + +#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ + (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \ + ) - (1) ) << (24))) + +#if 0 +/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ +/* the expression will round down, so make sure to reverse it toverify */ +/* it is what you want. period = [( count + 1 ) * 4] / Fxtal */ + +#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ + (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \ + ) - (1) ) << (24))) +#endif + +/* Base Address Registers (0xFFC0_00X0) */ + +#define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000) + +/* macro to define base */ + +#define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) + +#define NETARM_MEM_BAR_DRAM_FP (0x00000000) +#define NETARM_MEM_BAR_DRAM_EDO (0x00000100) +#define NETARM_MEM_BAR_DRAM_SYNC (0x00000200) + +#define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000) +#define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080) + +#define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000) +#define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020) + +#define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010) + +#define NETARM_MEM_BAR_DRAM_SEL (0x00000008) + +#define NETARM_MEM_BAR_BURST_EN (0x00000004) + +#define NETARM_MEM_BAR_WRT_PROT (0x00000002) + +#define NETARM_MEM_BAR_VALID (0x00000001) + +/* Option Registers (0xFFC0_00X4) */ + +/* macro to define which bits of the base are significant */ + +#define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) + +#define NETARM_MEM_OPT_WAIT_MASK (0x00000F00) + +#define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK ) + +#define NETARM_MEM_OPT_BCYC_1 (0x00000000) +#define NETARM_MEM_OPT_BCYC_2 (0x00000040) +#define NETARM_MEM_OPT_BCYC_3 (0x00000080) +#define NETARM_MEM_OPT_BCYC_4 (0x000000C0) + +#define NETARM_MEM_OPT_BSIZE_2 (0x00000000) +#define NETARM_MEM_OPT_BSIZE_4 (0x00000010) +#define NETARM_MEM_OPT_BSIZE_8 (0x00000020) +#define NETARM_MEM_OPT_BSIZE_16 (0x00000030) + +#define NETARM_MEM_OPT_32BIT (0x00000000) +#define NETARM_MEM_OPT_16BIT (0x00000004) +#define NETARM_MEM_OPT_8BIT (0x00000008) +#define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C) + +#define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C) + +#define NETARM_MEM_OPT_READ_ASYNC (0x00000000) +#define NETARM_MEM_OPT_READ_SYNC (0x00000002) + +#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000) +#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001) + +#ifdef CONFIG_NETARM_NS7520 +/* The NS7520 has a second options register for each chip select */ +#define NETARM_MEM_CS0_OPTIONS_B (0x18) +#define NETARM_MEM_CS1_OPTIONS_B (0x28) +#define NETARM_MEM_CS2_OPTIONS_B (0x38) +#define NETARM_MEM_CS3_OPTIONS_B (0x48) +#define NETARM_MEM_CS4_OPTIONS_B (0x58) + +/* Option B Registers (0xFFC0_00x8) */ +#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) +#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) +#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) +#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) +#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) + +#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) +#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) +#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) +#endif + +#endif diff --git a/include/asm-arm/arch-arm720t/netarm_registers.h b/include/asm-arm/arch-arm720t/netarm_registers.h new file mode 100644 index 0000000..fa88128 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_registers.h @@ -0,0 +1,96 @@ +/* + * linux/include/asm-arm/arch-netarm/netarm_registers.h + * + * Copyright (C) 2005 + * Art Shipkowski, Videon Central, Inc., + * + * Copyright (C) 2000, 2001 NETsilicon, Inc. + * Copyright (C) 2000, 2001 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + * + * Modified to support NS7520 by Art Shipkowski. + */ + +#ifndef __NET_ARM_REGISTERS_H +#define __NET_ARM_REGISTERS_H + +#include + +/* fundamental constants : */ +/* the input crystal/clock frequency ( in Hz ) */ +#define NETARM_XTAL_FREQ_25MHz (18432000) +#define NETARM_XTAL_FREQ_33MHz (23698000) +#define NETARM_XTAL_FREQ_48MHz (48000000) +#define NETARM_XTAL_FREQ_55MHz (55000000) +#define NETARM_XTAL_FREQ_EMLIN1 (20000000) + +/* the frequency of SYS_CLK */ +#if defined(CONFIG_NETARM_EMLIN) + +/* EMLIN board: 33 MHz (exp.) */ +#define NETARM_PLL_COUNT_VAL 6 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#elif defined(CONFIG_NETARM_NET40_REV2) + +/* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */ +#define NETARM_PLL_COUNT_VAL 6 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#elif defined(CONFIG_NETARM_NET40_REV4) + +/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with + NETARM_XTAL_FREQ_25MHz) 4 */ +#define NETARM_PLL_COUNT_VAL 4 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#elif defined(CONFIG_NETARM_NET50) + +/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ +#define NETARM_PLL_COUNT_VAL 8 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#else /* CONFIG_NETARM_NS7520 */ + +#define NETARM_PLL_COUNT_VAL 0 + +#if defined(CONFIG_BOARD_UNC20) +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz +#else +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz +#endif + +#endif + +/* #include "arm_registers.h" */ +#include +#include +#include +#include +#include +#include + +#endif diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h new file mode 100644 index 0000000..fceabd1 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_ser_module.h @@ -0,0 +1,347 @@ +/* + * linux/include/asm-arm/arch-netarm/netarm_ser_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 Red Hat, Inc. + * + * This software is copyrighted by Red Hat. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall Red Hat + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + * Clark Williams + */ + +#ifndef __NETARM_SER_MODULE_REGISTERS_H +#define __NETARM_SER_MODULE_REGISTERS_H + +#ifndef __ASSEMBLER__ + +/* (--sub)#include "types.h" */ + +/* serial channel control structure */ +typedef struct { + u32 ctrl_a; + u32 ctrl_b; + u32 status_a; + u32 bitrate; + u32 fifo; + u32 rx_buf_timer; + u32 rx_char_timer; + u32 rx_match; + u32 rx_match_mask; + u32 ctrl_c; + u32 status_b; + u32 status_c; + u32 fifo_last; + u32 unused[3]; +} netarm_serial_channel_t; + +#endif + +/* SER unit register offsets */ + +/* #ifdef CONFIG_ARCH_NETARM */ +#define NETARM_SER_MODULE_BASE (0xFFD00000) +/* #else */ +/* extern serial_channel_t netarm_dummy_registers[]; */ +/* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */ +/* #ifndef NETARM_XTAL_FREQ */ +/* #define NETARM_XTAL_FREQ 18432000 */ +/* #endif */ +/* #endif */ + +/* calculate the sysclk value from the pll setting */ +#define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \ + ( NETARM_PLL_COUNT_VAL + 3 )) + +#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c])) + +#define NETARM_SER_CH1_CTRL_A (0x00) +#define NETARM_SER_CH1_CTRL_B (0x04) +#define NETARM_SER_CH1_STATUS_A (0x08) +#define NETARM_SER_CH1_BITRATE (0x0C) +#define NETARM_SER_CH1_FIFO (0x10) +#define NETARM_SER_CH1_RX_BUF_TMR (0x14) +#define NETARM_SER_CH1_RX_CHAR_TMR (0x18) +#define NETARM_SER_CH1_RX_MATCH (0x1c) +#define NETARM_SER_CH1_RX_MATCH_MASK (0x20) +#define NETARM_SER_CH1_CTRL_C (0x24) +#define NETARM_SER_CH1_STATUS_B (0x28) +#define NETARM_SER_CH1_STATUS_C (0x2c) +#define NETARM_SER_CH1_FIFO_LAST (0x30) + +#define NETARM_SER_CH2_CTRL_A (0x40) +#define NETARM_SER_CH2_CTRL_B (0x44) +#define NETARM_SER_CH2_STATUS_A (0x48) +#define NETARM_SER_CH2_BITRATE (0x4C) +#define NETARM_SER_CH2_FIFO (0x50) +#define NETARM_SER_CH2_RX_BUF_TMR (0x54) +#define NETARM_SER_CH2_RX_CHAR_TMR (0x58) +#define NETARM_SER_CH2_RX_MATCH (0x5c) +#define NETARM_SER_CH2_RX_MATCH_MASK (0x60) +#define NETARM_SER_CH2_CTRL_C (0x64) +#define NETARM_SER_CH2_STATUS_B (0x68) +#define NETARM_SER_CH2_STATUS_C (0x6c) +#define NETARM_SER_CH2_FIFO_LAST (0x70) + +/* select bitfield defintions */ + +/* Control Register A */ + +#define NETARM_SER_CTLA_ENABLE (0x80000000) +#define NETARM_SER_CTLA_BRK (0x40000000) + +#define NETARM_SER_CTLA_STICKP (0x20000000) + +#define NETARM_SER_CTLA_P_EVEN (0x18000000) +#define NETARM_SER_CTLA_P_ODD (0x08000000) +#define NETARM_SER_CTLA_P_NONE (0x00000000) + +/* if you read the errata, you will find that the STOP bits don't work right */ +#define NETARM_SER_CTLA_2STOP (0x00000000) +#define NETARM_SER_CTLA_3STOP (0x04000000) + +#define NETARM_SER_CTLA_5BITS (0x00000000) +#define NETARM_SER_CTLA_6BITS (0x01000000) +#define NETARM_SER_CTLA_7BITS (0x02000000) +#define NETARM_SER_CTLA_8BITS (0x03000000) + +#define NETARM_SER_CTLA_CTSTX (0x00800000) +#define NETARM_SER_CTLA_RTSRX (0x00400000) + +#define NETARM_SER_CTLA_LOOP_REM (0x00200000) +#define NETARM_SER_CTLA_LOOP_LOC (0x00100000) + +#define NETARM_SER_CTLA_GPIO2 (0x00080000) +#define NETARM_SER_CTLA_GPIO1 (0x00040000) + +#define NETARM_SER_CTLA_DTR_EN (0x00020000) +#define NETARM_SER_CTLA_RTS_EN (0x00010000) + +#define NETARM_SER_CTLA_IE_RX_BRK (0x00008000) +#define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000) +#define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000) +#define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000) +#define NETARM_SER_CTLA_IE_RX_RDY (0x00000800) +#define NETARM_SER_CTLA_IE_RX_HALF (0x00000400) +#define NETARM_SER_CTLA_IE_RX_FULL (0x00000200) +#define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100) +#define NETARM_SER_CTLA_IE_RX_DCD (0x00000080) +#define NETARM_SER_CTLA_IE_RX_RI (0x00000040) +#define NETARM_SER_CTLA_IE_RX_DSR (0x00000020) + +#define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \ + |NETARM_SER_CTLA_IE_RX_FRMERR \ + |NETARM_SER_CTLA_IE_RX_PARERR \ + |NETARM_SER_CTLA_IE_RX_OVERRUN \ + |NETARM_SER_CTLA_IE_RX_RDY \ + |NETARM_SER_CTLA_IE_RX_HALF \ + |NETARM_SER_CTLA_IE_RX_FULL \ + |NETARM_SER_CTLA_IE_RX_DMAEN \ + |NETARM_SER_CTLA_IE_RX_DCD \ + |NETARM_SER_CTLA_IE_RX_RI \ + |NETARM_SER_CTLA_IE_RX_DSR) + +#define NETARM_SER_CTLA_IE_TX_CTS (0x00000010) +#define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008) +#define NETARM_SER_CTLA_IE_TX_HALF (0x00000004) +#define NETARM_SER_CTLA_IE_TX_FULL (0x00000002) +#define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001) + +#define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \ + |NETARM_SER_CTLA_IE_TX_EMPTY \ + |NETARM_SER_CTLA_IE_TX_HALF \ + |NETARM_SER_CTLA_IE_TX_FULL \ + |NETARM_SER_CTLA_IE_TX_DMAEN) + +/* Control Register B */ + +#define NETARM_SER_CTLB_MATCH1_EN (0x80000000) +#define NETARM_SER_CTLB_MATCH2_EN (0x40000000) +#define NETARM_SER_CTLB_MATCH3_EN (0x20000000) +#define NETARM_SER_CTLB_MATCH4_EN (0x10000000) + +#define NETARM_SER_CTLB_RBGT_EN (0x08000000) +#define NETARM_SER_CTLB_RCGT_EN (0x04000000) + +#define NETARM_SER_CTLB_UART_MODE (0x00000000) +#define NETARM_SER_CTLB_HDLC_MODE (0x00100000) +#define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000) +#define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000) + +#define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000) + +#define NETARM_SER_CTLB_MAM1 (0x00040000) +#define NETARM_SER_CTLB_MAM2 (0x00020000) + +/* Status Register A */ + +#define NETARM_SER_STATA_MATCH1 (0x80000000) +#define NETARM_SER_STATA_MATCH2 (0x40000000) +#define NETARM_SER_STATA_MATCH3 (0x20000000) +#define NETARM_SER_STATA_MATCH4 (0x10000000) + +#define NETARM_SER_STATA_BGAP (0x80000000) +#define NETARM_SER_STATA_CGAP (0x40000000) + +#define NETARM_SER_STATA_RX_1B (0x00100000) +#define NETARM_SER_STATA_RX_2B (0x00200000) +#define NETARM_SER_STATA_RX_3B (0x00300000) +#define NETARM_SER_STATA_RX_4B (0x00000000) + +/* downshifted values */ + +#define NETARM_SER_STATA_RXFDB_1BYTES (0x001) +#define NETARM_SER_STATA_RXFDB_2BYTES (0x002) +#define NETARM_SER_STATA_RXFDB_3BYTES (0x003) +#define NETARM_SER_STATA_RXFDB_4BYTES (0x000) + +#define NETARM_SER_STATA_RXFDB_MASK (0x00300000) +#define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \ + >> 20) + +#define NETARM_SER_STATA_DCD (0x00080000) +#define NETARM_SER_STATA_RI (0x00040000) +#define NETARM_SER_STATA_DSR (0x00020000) +#define NETARM_SER_STATA_CTS (0x00010000) + +#define NETARM_SER_STATA_RX_BRK (0x00008000) +#define NETARM_SER_STATA_RX_FRMERR (0x00004000) +#define NETARM_SER_STATA_RX_PARERR (0x00002000) +#define NETARM_SER_STATA_RX_OVERRUN (0x00001000) +#define NETARM_SER_STATA_RX_RDY (0x00000800) +#define NETARM_SER_STATA_RX_HALF (0x00000400) +#define NETARM_SER_STATA_RX_CLOSED (0x00000200) +#define NETARM_SER_STATA_RX_FULL (0x00000100) +#define NETARM_SER_STATA_RX_DCD (0x00000080) +#define NETARM_SER_STATA_RX_RI (0x00000040) +#define NETARM_SER_STATA_RX_DSR (0x00000020) + +#define NETARM_SER_STATA_TX_CTS (0x00000010) +#define NETARM_SER_STATA_TX_RDY (0x00000008) +#define NETARM_SER_STATA_TX_HALF (0x00000004) +#define NETARM_SER_STATA_TX_FULL (0x00000002) +#define NETARM_SER_STATA_TX_DMAEN (0x00000001) + +/* you have to clear all receive signals to get the fifo to move forward */ +#define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \ + NETARM_SER_STATA_RX_FRMERR | \ + NETARM_SER_STATA_RX_PARERR | \ + NETARM_SER_STATA_RX_OVERRUN | \ + NETARM_SER_STATA_RX_HALF | \ + NETARM_SER_STATA_RX_CLOSED | \ + NETARM_SER_STATA_RX_FULL | \ + NETARM_SER_STATA_RX_DCD | \ + NETARM_SER_STATA_RX_RI | \ + NETARM_SER_STATA_RX_DSR | \ + NETARM_SER_STATA_TX_CTS ) + +/* Bit Rate Registers */ + +#define NETARM_SER_BR_EN (0x80000000) +#define NETARM_SER_BR_TMODE (0x40000000) + +#define NETARM_SER_BR_RX_CLK_INT (0x00000000) +#define NETARM_SER_BR_RX_CLK_EXT (0x20000000) +#define NETARM_SER_BR_TX_CLK_INT (0x00000000) +#define NETARM_SER_BR_TX_CLK_EXT (0x10000000) + +#define NETARM_SER_BR_RX_CLK_DRV (0x08000000) +#define NETARM_SER_BR_TX_CLK_DRV (0x04000000) + +#define NETARM_SER_BR_CLK_EXT_5 (0x00000000) +#define NETARM_SER_BR_CLK_SYSTEM (0x01000000) +#define NETARM_SER_BR_CLK_OUT1A (0x02000000) +#define NETARM_SER_BR_CLK_OUT2A (0x03000000) + +#define NETARM_SER_BR_TX_CLK_INV (0x00800000) +#define NETARM_SER_BR_RX_CLK_INV (0x00400000) + +/* complete settings assuming system clock input is 18MHz */ + +#define NETARM_SER_BR_MASK (0x000007FF) + +/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */ +/* from section 7.5.4 of HW Ref Guide */ + +/* #ifdef CONFIG_NETARM_PLL_BYPASS */ +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_EXT_5 | \ + ( ( ( ( NETARM_XTAL_FREQ / \ + ( x * 10 ) ) - 1 ) / 16 ) & \ + NETARM_SER_BR_MASK ) ) +/* +#else +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_SYSTEM | \ + ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ + ( x * 2 ) ) - 1 ) / 16 ) & \ + NETARM_SER_BR_MASK ) ) +#endif +*/ + +/* Receive Buffer Gap Timer */ + +#define NETARM_SER_RX_GAP_TIMER_EN (0x80000000) +#define NETARM_SER_RX_GAP_MASK (0x00003FFF) + +/* rx gap is a function of bit rate x */ + +/* #ifdef CONFIG_NETARM_PLL_BYPASS */ +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ + ( x * 5 * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +/* +#else +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ + ( x * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +#endif +*/ + +#if 0 +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ + ( x * 5 * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ + ( x * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +#endif + +#define MIN_BAUD_RATE 600 +#define MAX_BAUD_RATE 115200 + +/* the default BAUD rate for the BOOTLOADER, there is a separate */ +/* setting in the serial driver */ +#define DEFAULT_BAUD_RATE 9600 +#define NETARM_SER_FIFO_SIZE 32 +#define MIN_GAP 0 + +#endif diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h new file mode 100644 index 0000000..517b1ad --- /dev/null +++ b/include/asm-arm/arch-arm720t/s3c4510b.h @@ -0,0 +1,274 @@ +#ifndef __HW_S3C4510_H +#define __HW_S3C4510_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: Samsung S3C4510B register layout + */ + +/*------------------------------------------------------------------------ + * ASIC Address Definition + *----------------------------------------------------------------------*/ + +/* L1 8KB on chip SRAM base address */ +#define SRAM_BASE (0x03fe0000) + +/* Special Register Start Address After System Reset */ +#define REG_BASE (0x03ff0000) +#define SPSTR (REG_BASE) + +/* *********************** */ +/* System Manager Register */ +/* *********************** */ +#define REG_SYSCFG (REG_BASE+0x0000) + +#define REG_CLKCON (REG_BASE+0x3000) +#define REG_EXTACON0 (REG_BASE+0x3008) +#define REG_EXTACON1 (REG_BASE+0x300c) +#define REG_EXTDBWTH (REG_BASE+0x3010) +#define REG_ROMCON0 (REG_BASE+0x3014) +#define REG_ROMCON1 (REG_BASE+0x3018) +#define REG_ROMCON2 (REG_BASE+0x301c) +#define REG_ROMCON3 (REG_BASE+0x3020) +#define REG_ROMCON4 (REG_BASE+0x3024) +#define REG_ROMCON5 (REG_BASE+0x3028) +#define REG_DRAMCON0 (REG_BASE+0x302c) +#define REG_DRAMCON1 (REG_BASE+0x3030) +#define REG_DRAMCON2 (REG_BASE+0x3034) +#define REG_DRAMCON3 (REG_BASE+0x3038) +#define REG_REFEXTCON (REG_BASE+0x303c) + +/* *********************** */ +/* Ethernet BDMA Register */ +/* *********************** */ +#define REG_BDMATXCON (REG_BASE+0x9000) +#define REG_BDMARXCON (REG_BASE+0x9004) +#define REG_BDMATXPTR (REG_BASE+0x9008) +#define REG_BDMARXPTR (REG_BASE+0x900c) +#define REG_BDMARXLSZ (REG_BASE+0x9010) +#define REG_BDMASTAT (REG_BASE+0x9014) + +/* Content Address Memory */ +#define REG_CAM_BASE (REG_BASE+0x9100) + +#define REG_BDMATXBUF (REG_BASE+0x9200) +#define REG_BDMARXBUF (REG_BASE+0x9800) + +/* *********************** */ +/* Ethernet MAC Register */ +/* *********************** */ +#define REG_MACCON (REG_BASE+0xa000) +#define REG_CAMCON (REG_BASE+0xa004) +#define REG_MACTXCON (REG_BASE+0xa008) +#define REG_MACTXSTAT (REG_BASE+0xa00c) +#define REG_MACRXCON (REG_BASE+0xa010) +#define REG_MACRXSTAT (REG_BASE+0xa014) +#define REG_STADATA (REG_BASE+0xa018) +#define REG_STACON (REG_BASE+0xa01c) +#define REG_CAMEN (REG_BASE+0xa028) +#define REG_EMISSCNT (REG_BASE+0xa03c) +#define REG_EPZCNT (REG_BASE+0xa040) +#define REG_ERMPZCNT (REG_BASE+0xa044) +#define REG_ETXSTAT (REG_BASE+0x9040) +#define REG_MACRXDESTR (REG_BASE+0xa064) +#define REG_MACRXSTATEM (REG_BASE+0xa090) +#define REG_MACRXFIFO (REG_BASE+0xa200) + +/********************/ +/* I2C Bus Register */ +/********************/ +#define REG_I2C_CON (REG_BASE+0xf000) +#define REG_I2C_BUF (REG_BASE+0xf004) +#define REG_I2C_PS (REG_BASE+0xf008) +#define REG_I2C_COUNT (REG_BASE+0xf00c) + +/********************/ +/* GDMA 0 */ +/********************/ +#define REG_GDMACON0 (REG_BASE+0xb000) +#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020) +#define REG_GDMASRC0 (REG_BASE+0xb004) +#define REG_GDMADST0 (REG_BASE+0xb008) +#define REG_GDMACNT0 (REG_BASE+0xb00c) + +/********************/ +/* GDMA 1 */ +/********************/ +#define REG_GDMACON1 (REG_BASE+0xc000) +#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020) +#define REG_GDMASRC1 (REG_BASE+0xc004) +#define REG_GDMADST1 (REG_BASE+0xc008) +#define REG_GDMACNT1 (REG_BASE+0xc00c) + +/********************/ +/* UART 0 */ +/********************/ +#define UART0_BASE (REG_BASE+0xd000) +#define REG_UART0_LCON (REG_BASE+0xd000) +#define REG_UART0_CTRL (REG_BASE+0xd004) +#define REG_UART0_STAT (REG_BASE+0xd008) +#define REG_UART0_TXB (REG_BASE+0xd00c) +#define REG_UART0_RXB (REG_BASE+0xd010) +#define REG_UART0_BAUD_DIV (REG_BASE+0xd014) +#define REG_UART0_BAUD_CNT (REG_BASE+0xd018) +#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C) + +/********************/ +/* UART 1 */ +/********************/ +#define UART1_BASE (REG_BASE+0xe000) +#define REG_UART1_LCON (REG_BASE+0xe000) +#define REG_UART1_CTRL (REG_BASE+0xe004) +#define REG_UART1_STAT (REG_BASE+0xe008) +#define REG_UART1_TXB (REG_BASE+0xe00c) +#define REG_UART1_RXB (REG_BASE+0xe010) +#define REG_UART1_BAUD_DIV (REG_BASE+0xe014) +#define REG_UART1_BAUD_CNT (REG_BASE+0xe018) +#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C) + +/********************/ +/* Timer Register */ +/********************/ +#define REG_TMOD (REG_BASE+0x6000) +#define REG_TDATA0 (REG_BASE+0x6004) +#define REG_TDATA1 (REG_BASE+0x6008) +#define REG_TCNT0 (REG_BASE+0x600c) +#define REG_TCNT1 (REG_BASE+0x6010) + +/**********************/ +/* I/O Port Interface */ +/**********************/ +#define REG_IOPMODE (REG_BASE+0x5000) +#define REG_IOPCON (REG_BASE+0x5004) +#define REG_IOPDATA (REG_BASE+0x5008) + +/*********************************/ +/* Interrupt Controller Register */ +/*********************************/ +#define REG_INTMODE (REG_BASE+0x4000) +#define REG_INTPEND (REG_BASE+0x4004) +#define REG_INTMASK (REG_BASE+0x4008) + +#define REG_INTPRI0 (REG_BASE+0x400c) +#define REG_INTPRI1 (REG_BASE+0x4010) +#define REG_INTPRI2 (REG_BASE+0x4014) +#define REG_INTPRI3 (REG_BASE+0x4018) +#define REG_INTPRI4 (REG_BASE+0x401c) +#define REG_INTPRI5 (REG_BASE+0x4020) +#define REG_INTOFFSET (REG_BASE+0x4024) +#define REG_INTPNDPRI (REG_BASE+0x4028) +#define REG_INTPNDTST (REG_BASE+0x402C) + +/*********************************/ +/* CACHE CONTROL MASKS */ +/*********************************/ +#define CACHE_STALL (0x00000001) +#define CACHE_ENABLE (0x00000002) +#define CACHE_WRITE_BUFF (0x00000004) +#define CACHE_MODE (0x00000030) +#define CACHE_MODE_00 (0x00000000) +#define CACHE_MODE_01 (0x00000010) +#define CACHE_MODE_10 (0x00000020) + +/*********************************/ +/* CACHE RAM BASE ADDRESSES */ +/*********************************/ +#define CACHE_SET0_RAM (0x10000000) +#define CACHE_SET1_RAM (0x10800000) +#define CACHE_TAG_RAM (0x11000000) + +/*********************************/ +/* CACHE_DISABLE MASK */ +/*********************************/ +#define CACHE_DISABLE_MASK (0x04000000) + +#define GET_REG(reg) (*((volatile u32 *)(reg))) +#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val))) +#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask)) +#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask)) +#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val))) +#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF))) +#define GET__U8(reg) (*((volatile u8 *)(reg))) + +#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF)) +#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF) +#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); } +#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); } + +/***********************************/ +/* CLOCK CONSTANTS -- 50 MHz Clock */ +/***********************************/ + +#define CLK_FREQ_MHZ (50) +#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */ +#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */ + +/*********************************************************/ +/* TIMER MODE REGISTER */ +/*********************************************************/ +#define TM0_RUN 0x01 /* Timer 0 enable */ +#define TM0_TOGGLE 0x02 /* 0, interval mode */ +#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */ +#define TM1_RUN 0x08 /* Timer 1 enable */ +#define TM1_TOGGLE 0x10 /* 0, interval mode */ +#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */ + + +/*********************************/ +/* INTERRUPT SOURCES */ +/*********************************/ +#define INT_EXTINT0 0 +#define INT_EXTINT1 1 +#define INT_EXTINT2 2 +#define INT_EXTINT3 3 +#define INT_UARTTX0 4 +#define INT_UARTRX0 5 +#define INT_UARTTX1 6 +#define INT_UARTRX1 7 +#define INT_GDMA0 8 +#define INT_GDMA1 9 +#define INT_TIMER0 10 +#define INT_TIMER1 11 +#define INT_HDLCTXA 12 +#define INT_HDLCRXA 13 +#define INT_HDLCTXB 14 +#define INT_HDLCRXB 15 +#define INT_BDMATX 16 +#define INT_BDMARX 17 +#define INT_MACTX 18 +#define INT_MACRX 19 +#define INT_IIC 20 +#define INT_GLOBAL 21 +#define N_IRQS (21) + +#ifndef __ASSEMBLER__ +struct _irq_handler { + void *m_data; + void (*m_func)( void *data); +}; + +extern struct _irq_handler IRQ_HANDLER[]; + +#endif + +#endif /* __S3C4510_h */ diff --git a/include/asm-arm/arch-arm925t/sizes.h b/include/asm-arm/arch-arm925t/sizes.h new file mode 100644 index 0000000..7319bd9 --- /dev/null +++ b/include/asm-arm/arch-arm925t/sizes.h @@ -0,0 +1,50 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/include/asm-arm/arch-arm926ejs/sizes.h b/include/asm-arm/arch-arm926ejs/sizes.h new file mode 100644 index 0000000..ef0b99b --- /dev/null +++ b/include/asm-arm/arch-arm926ejs/sizes.h @@ -0,0 +1,51 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307 + * USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h new file mode 100644 index 0000000..97d4704 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -0,0 +1,762 @@ +/* + * (C) Copyright 2003 + * AT91RM9200 definitions + * Author : ATMEL AT91 application group + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef AT91RM9200_H +#define AT91RM9200_H + +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/******************************************************************************/ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register */ + AT91_REG Reserved0[2]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, *AT91PS_TC; + +#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ +#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ +#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ +#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ +#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */ +#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ +#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ +#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Usart */ +/******************************************************************************/ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[5]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG US_XXR; /* XON_XOFF Register */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved1[44]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, *AT91PS_USART; + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ +/******************************************************************************/ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG CKGR_PLLAR; /* PLL A Register */ + AT91_REG CKGR_PLLBR; /* PLL B Register */ +} AT91S_CKGR, *AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */ +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */ + +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */ + +/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */ +#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */ +#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ +#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */ +#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */ + +/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */ +#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ +#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */ +#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ +#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ +/******************************************************************************/ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[1]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[1]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[1]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ + AT91_REG Reserved4[1]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[9]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, *AT91PS_PIO; + + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/******************************************************************************/ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[7]; /* */ + AT91_REG DBGU_C1R; /* Chip ID1 Register */ + AT91_REG DBGU_C2R; /* Chip ID2 Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[45]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, *AT91PS_DBGU; + +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */ + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */ + +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */ +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */ +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ +/******************************************************************************/ +typedef struct _AT91S_SMC2 +{ + AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ +} AT91S_SMC2, *AT91PS_SMC2; + +/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ +#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ +#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ +#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ +#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ +#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ +#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ +#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ +#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */ +#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ +#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */ +#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ +#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ +#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ +#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Power Management Controler */ +/******************************************************************************/ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[5]; /* */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, *AT91PS_PMC; + +/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */ +#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */ +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */ +/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/ +/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/ +/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/ +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */ +#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */ +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */ +#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */ +#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */ +#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */ +#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */ +#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */ +/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/ +/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/ +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */ +/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/ +/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ +/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Ethernet MAC */ +/******************************************************************************/ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_CTL; /* Network Control Register */ + AT91_REG EMAC_CFG; /* Network Configuration Register */ + AT91_REG EMAC_SR; /* Network Status Register */ + AT91_REG EMAC_TAR; /* Transmit Address Register */ + AT91_REG EMAC_TCR; /* Transmit Control Register */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG Reserved0[1]; /* */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG Reserved1[2]; /* */ + AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ + AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ + AT91_REG EMAC_OK; /* Frames Received OK Register */ + AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CDE; /* Code Error Register */ + AT91_REG EMAC_ELR; /* Excessive Length Error Register */ + AT91_REG EMAC_RJB; /* Receive Jabber Register */ + AT91_REG EMAC_USF; /* Undersize Frame Register */ + AT91_REG EMAC_SQEE; /* SQE Test Error Register */ + AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ + AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ +} AT91S_EMAC, *AT91PS_EMAC; + +/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */ + +/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */ +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */ +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */ +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */ + +/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ + +/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */ +#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ +#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ + +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */ +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ +#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */ +#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */ +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */ +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */ + +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */ +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ + +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ +#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ +#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */ +#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */ +#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */ +#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */ +#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */ +#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */ +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */ +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ + +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */ +#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */ +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */ +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */ +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */ +#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */ +#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */ +#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ +#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/******************************************************************************/ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[4]; /* */ + AT91_REG SPI_CSR[4]; /* Chip Select Register */ + AT91_REG Reserved1[48]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, *AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */ + +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */ + +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ + +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ + +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ + +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */ +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/******************************************************************************/ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, *AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ========== Register definition ==================================== */ +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */ +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */ +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */ +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */ +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */ +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */ +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */ +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */ +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */ +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */ +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */ +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */ +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */ +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */ +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */ +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */ +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */ +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */ +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */ +#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */ +#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */ +#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */ +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */ +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */ +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */ +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */ +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */ +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */ +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ + +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ +#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ +#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */ +#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */ +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */ +#define AT91C_PA25_TWD ((unsigned int) 1 << 25) +#define AT91C_PA26_TWCK ((unsigned int) 1 << 26) +#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */ +#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */ +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */ +#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */ +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */ +#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */ +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ +#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ + +#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ +#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ +#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ +#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ +#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ +#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ +#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ +#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */ +#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */ +#define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */ +#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */ + +#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */ +#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */ +#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */ +#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ +#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */ +#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */ +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */ + +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */ + +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */ +#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */ +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */ +#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */ +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */ +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */ +#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */ +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */ +#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */ +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */ +#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ +#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */ + +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ +#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ +#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */ +#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */ +#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */ +#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */ +#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ +#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ +#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */ +#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ +#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ + +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ +#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ +#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */ +#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */ +#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */ +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */ +#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */ +#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */ +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */ +#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */ +#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */ +#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */ +#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */ +#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */ +#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */ +#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */ +#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */ +#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */ +#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */ +#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ +#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ + +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ + +#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ +#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ +#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ +#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ +#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ +#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ +#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ + +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ +#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ +#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ +#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ +#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ +#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ +#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ +#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ +#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ + +#endif diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h new file mode 100644 index 0000000..8bb0c47 --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/hardware.h @@ -0,0 +1,77 @@ +/* + * linux/include/asm-arm/arch-at91/hardware.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +#ifndef __ASSEMBLY__ +#include "AT91RM9200.h" +#else +#include "AT91RM9200_inc.h" +#endif + +/* Virtual and Physical base address for system peripherals */ +#define AT91_SYS_BASE 0xFFFFF000 /*4K */ + +/* Virtual and Physical base addresses of user peripherals */ +#define AT91_SPI_BASE 0xFFFE0000 /*16K */ +#define AT91_SSC2_BASE 0xFFFD8000 /*16K */ +#define AT91_SSC1_BASE 0xFFFD4000 /*16K */ +#define AT91_SSC0_BASE 0xFFFD0000 /*16K */ +#define AT91_USART3_BASE 0xFFFCC000 /*16K */ +#define AT91_USART2_BASE 0xFFFC8000 /*16K */ +#define AT91_USART1_BASE 0xFFFC4000 /*16K */ +#define AT91_USART0_BASE 0xFFFC0000 /*16K */ +#define AT91_EMAC_BASE 0xFFFBC000 /*16K */ +#define AT91_TWI_BASE 0xFFFB8000 /*16K */ +#define AT91_MCI_BASE 0xFFFB4000 /*16K */ +#define AT91_UDP_BASE 0xFFFB0000 /*16K */ +#define AT91_TCB1_BASE 0xFFFA4000 /*16K */ +#define AT91_TCB0_BASE 0xFFFA0000 /*16K */ + +#define AT91_USB_HOST_BASE 0x00300000 + +/* + * Where in virtual memory the IO devices (timers, system controllers + * and so on) + */ +#define AT91_IO_BASE 0xF0000000 /* Virt/Phys Address of IO */ + +/* FLASH */ +#define AT91_FLASH_BASE 0x10000000 /* NCS0 */ + +/* SDRAM */ +#define AT91_SDRAM_BASE 0x20000000 /* NCS1 */ + +/* SmartMedia */ +#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3 */ + +/* Definition of interrupt priority levels */ +#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST +#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1) +#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2) +#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3) +#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4) +#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5) +#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6) +#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST + +#endif diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h new file mode 100644 index 0000000..318de22 --- /dev/null +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -0,0 +1,577 @@ +#ifndef _IMX_REGS_H +#define _IMX_REGS_H +/* ------------------------------------------------------------------------ + * Motorola IMX system registers + * ------------------------------------------------------------------------ + * + */ + +# ifndef __ASSEMBLY__ +# define __REG(x) (*((volatile u32 *)(x))) +# define __REG2(x,y) \ + ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ + : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) +# else +# define __REG(x) (x) +# define __REG2(x,y) ((x)+(y)) +#endif + +#define IMX_IO_BASE 0x00200000 + +/* + * Register BASEs, based on OFFSETs + * + */ +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) +#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) +#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) +#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) +#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) +#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) +#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) +#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) +#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) +#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) +#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) +#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) +#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) +#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) +#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) +#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) +#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) +#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) +#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) +#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) +#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) +#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) +#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) + +/* Watchdog Registers*/ + +#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */ +#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */ + +/* SYSCTRL Registers */ +#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */ +#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */ +#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */ + +/* Chip Select Registers */ +#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */ +#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */ +#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */ +#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */ +#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ +#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ +#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ +#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */ +#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ +#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ +#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ +#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */ +#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ + +/* SDRAM controller registers */ + +#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */ +#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */ +#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */ +#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */ + +/* PLL registers */ +#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ +#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ +#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ +#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ + +#define CSCR_MPLL_RESTART (1<<21) + +/* + * GPIO Module and I/O Multiplexer + * x = 0..3 for reg_A, reg_B, reg_C, reg_D + */ +#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) +#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) +#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) +#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) +#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) +#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) +#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) +#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) +#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) +#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) +#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) +#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) +#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) +#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) +#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) +#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) +#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) + +#define GPIO_PIN_MASK 0x1f +#define GPIO_PORT_MASK (0x3 << 5) + +#define GPIO_PORTA (0<<5) +#define GPIO_PORTB (1<<5) +#define GPIO_PORTC (2<<5) +#define GPIO_PORTD (3<<5) + +#define GPIO_OUT (1<<7) +#define GPIO_IN (0<<7) +#define GPIO_PUEN (1<<8) + +#define GPIO_PF (0<<9) +#define GPIO_AF (1<<9) + +#define GPIO_OCR_MASK (3<<10) +#define GPIO_AIN (0<<10) +#define GPIO_BIN (1<<10) +#define GPIO_CIN (2<<10) +#define GPIO_GPIO (3<<10) + +#define GPIO_AOUT (1<<12) +#define GPIO_BOUT (1<<13) + +/* assignements for GPIO alternate/primary functions */ + +/* FIXME: This list is not completed. The correct directions are + * missing on some (many) pins + */ +#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) +#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) +#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) +#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) +#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) +#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) +#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) +#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) +#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) +#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) +#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) +#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) +#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) +#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) +#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) +#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) +#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) +#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) +#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) +#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) +#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) +#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) +#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) +#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) +#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) +#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) +#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) +#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) +#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) +#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) +#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) +#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) +#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) +#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) +#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) +#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) +#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) +#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) +#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) +#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) +#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) +#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) +#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) +#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) +#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) +#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) +#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) +#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) +#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) +#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) +#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 ) +#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) +#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 ) +#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) +#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 ) +#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) +#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) +#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) +#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) +#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) +#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) +#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) +#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) +#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) +#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) +#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) +#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) +#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) +#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) +#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) +#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) +#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) +#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) +#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) +#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) +#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) +#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) +#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) +#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) +#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) +#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) +#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) +#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) +#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) +#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) +#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) +#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) +#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) +#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) +#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) +#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) +#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) +#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) +#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) +#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) +#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) +#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) +#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) +#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) +#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) +#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) +#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) +#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) +#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) +#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) +#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) +#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) +#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) +#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) +#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) +#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) +#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) +#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) +#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) +#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) +#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) +#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) +#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) +#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) +#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) +#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) +#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) +#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) +#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) + +/* + * DMA Controller + */ +#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ +#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ +#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ +#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ +#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ +#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ +#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ +#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ +#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ +#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ +#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ +#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ +#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ +#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ +#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ +#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ +#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ +#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ +#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ +#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ +#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ +#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ + +/* TODO: define DMA_REQ lines */ + +#define DCR_DRST (1<<1) +#define DCR_DEN (1<<0) +#define DBTOCR_EN (1<<15) +#define DBTOCR_CNT(x) ((x) & 0x7fff ) +#define CNTR_CNT(x) ((x) & 0xffffff ) +#define CCR_DMOD_LINEAR ( 0x0 << 12 ) +#define CCR_DMOD_2D ( 0x1 << 12 ) +#define CCR_DMOD_FIFO ( 0x2 << 12 ) +#define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) +#define CCR_SMOD_LINEAR ( 0x0 << 10 ) +#define CCR_SMOD_2D ( 0x1 << 10 ) +#define CCR_SMOD_FIFO ( 0x2 << 10 ) +#define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) +#define CCR_MDIR_DEC (1<<9) +#define CCR_MSEL_B (1<<8) +#define CCR_DSIZ_32 ( 0x0 << 6 ) +#define CCR_DSIZ_8 ( 0x1 << 6 ) +#define CCR_DSIZ_16 ( 0x2 << 6 ) +#define CCR_SSIZ_32 ( 0x0 << 4 ) +#define CCR_SSIZ_8 ( 0x1 << 4 ) +#define CCR_SSIZ_16 ( 0x2 << 4 ) +#define CCR_REN (1<<3) +#define CCR_RPT (1<<2) +#define CCR_FRC (1<<1) +#define CCR_CEN (1<<0) +#define RTOR_EN (1<<15) +#define RTOR_CLK (1<<14) +#define RTOR_PSC (1<<13) + +/* + * LCD Controller + */ + +#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) + +#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) +#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) +#define SIZE_YMAX(y) ( (y) & 0x1ff ) + +#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) +#define VPW_VPW(x) ( (x) & 0x3ff ) + +#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) +#define CPOS_CC1 (1<<31) +#define CPOS_CC0 (1<<30) +#define CPOS_OP (1<<28) +#define CPOS_CXP(x) (((x) & 3ff) << 16) +#define CPOS_CYP(y) ((y) & 0x1ff) + +#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) +#define LCWHB_BK_EN (1<<31) +#define LCWHB_CW(w) (((w) & 0x1f) << 24) +#define LCWHB_CH(h) (((h) & 0x1f) << 16) +#define LCWHB_BD(x) ((x) & 0xff) + +#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) +#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) +#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) +#define LCHCC_CUR_COL_B(b) ((b) & 0x1f) + +#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) +#define PCR_TFT (1<<31) +#define PCR_COLOR (1<<30) +#define PCR_PBSIZ_1 (0<<28) +#define PCR_PBSIZ_2 (1<<28) +#define PCR_PBSIZ_4 (2<<28) +#define PCR_PBSIZ_8 (3<<28) +#define PCR_BPIX_1 (0<<25) +#define PCR_BPIX_2 (1<<25) +#define PCR_BPIX_4 (2<<25) +#define PCR_BPIX_8 (3<<25) +#define PCR_BPIX_12 (4<<25) +#define PCR_BPIX_16 (4<<25) +#define PCR_PIXPOL (1<<24) +#define PCR_FLMPOL (1<<23) +#define PCR_LPPOL (1<<22) +#define PCR_CLKPOL (1<<21) +#define PCR_OEPOL (1<<20) +#define PCR_SCLKIDLE (1<<19) +#define PCR_END_SEL (1<<18) +#define PCR_END_BYTE_SWAP (1<<17) +#define PCR_REV_VS (1<<16) +#define PCR_ACD_SEL (1<<15) +#define PCR_ACD(x) (((x) & 0x7f) << 8) +#define PCR_SCLK_SEL (1<<7) +#define PCR_SHARP (1<<6) +#define PCR_PCD(x) ((x) & 0x3f) + +#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) +#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) +#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) +#define HCR_H_WAIT_2(x) ((x) & 0xff) + +#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) +#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) +#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) +#define VCR_V_WAIT_2(x) ((x) & 0xff) + +#define LCDC_POS __REG(IMX_LCDC_BASE+0x24) +#define POS_POS(x) ((x) & 1f) + +#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) +#define LSCR1_GRAY1(x) (((x) & 0xf) << 4) +#define LSCR1_GRAY2(x) ((x) & 0xf) + +#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) +#define PWMR_CLS(x) (((x) & 0x1ff) << 16) +#define PWMR_LDMSK (1<<15) +#define PWMR_SCR1 (1<<10) +#define PWMR_SCR0 (1<<9) +#define PWMR_CC_EN (1<<8) +#define PWMR_PW(x) ((x) & 0xff) + +#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) +#define DMACR_BURST (1<<31) +#define DMACR_HM(x) (((x) & 0xf) << 16) +#define DMACR_TM(x) ((x) &0xf) + +#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) +#define RMCR_LCDC_EN (1<<1) +#define RMCR_SELF_REF (1<<0) + +#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) +#define LCDICR_INT_SYN (1<<2) +#define LCDICR_INT_CON (1) + +#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) +#define LCDISR_UDR_ERR (1<<3) +#define LCDISR_ERR_RES (1<<2) +#define LCDISR_EOF (1<<1) +#define LCDISR_BOF (1<<0) +/* + * UART Module + */ +#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */ +#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */ +#define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */ +#define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */ +#define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */ +#define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */ +#define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */ +#define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */ +#define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */ +#define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */ +#define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */ +#define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */ +#define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */ +#define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */ +#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */ +#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */ +#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */ +#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */ +#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */ +#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */ +#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */ +#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */ +#define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +/* General purpose timers registers */ +#define TCTL1 __REG(IMX_TIM1_BASE) +#define TPRER1 __REG(IMX_TIM1_BASE + 0x4) +#define TCMP1 __REG(IMX_TIM1_BASE + 0x8) +#define TCR1 __REG(IMX_TIM1_BASE + 0xc) +#define TCN1 __REG(IMX_TIM1_BASE + 0x10) +#define TSTAT1 __REG(IMX_TIM1_BASE + 0x14) +#define TCTL2 __REG(IMX_TIM2_BASE) +#define TPRER2 __REG(IMX_TIM2_BASE + 0x4) +#define TCMP2 __REG(IMX_TIM2_BASE + 0x8) +#define TCR2 __REG(IMX_TIM2_BASE + 0xc) +#define TCN2 __REG(IMX_TIM2_BASE + 0x10) +#define TSTAT2 __REG(IMX_TIM2_BASE + 0x14) + +/* General purpose timers bitfields */ +#define TCTL_SWR (1<<15) /* Software reset */ +#define TCTL_FRR (1<<8) /* Freerun / restart */ +#define TCTL_CAP (3<<6) /* Capture Edge */ +#define TCTL_OM (1<<5) /* output mode */ +#define TCTL_IRQEN (1<<4) /* interrupt enable */ +#define TCTL_CLKSOURCE (7<<1) /* Clock source */ +#define TCTL_TEN (1) /* Timer enable */ +#define TPRER_PRES (0xff) /* Prescale */ +#define TSTAT_CAPT (1<<1) /* Capture event */ +#define TSTAT_COMP (1) /* Compare event */ + +#endif /* _IMX_REGS_H */ diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h new file mode 100644 index 0000000..fbe6858 --- /dev/null +++ b/include/asm-arm/arch-ixp/ixp425.h @@ -0,0 +1,559 @@ +/* + * include/asm-arm/arch-ixp425/ixp425.h + * + * Register definitions for IXP425 + * + * Copyright (C) 2002 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _ASM_ARM_IXP425_H_ +#define _ASM_ARM_IXP425_H_ + +#define BIT(x) (1<<(x)) + +/* FIXME: Only this does work for u-boot... find out why... [RS] */ +#define UBOOT_REG_FIX 1 +#ifdef UBOOT_REG_FIX +# undef io_p2v +# undef __REG +# ifndef __ASSEMBLY__ +# define io_p2v(PhAdd) (PhAdd) +# define __REG(x) (*((volatile u32 *)io_p2v(x))) +# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) +# else +# define __REG(x) (x) +# endif +#endif /* UBOOT_REG_FIX */ + +/* + * + * IXP425 Memory map: + * + * Phy Phy Size Map Size Virt Description + * ========================================================================= + * + * 0x00000000 0x10000000 SDRAM 1 + * + * 0x10000000 0x10000000 SDRAM 2 + * + * 0x20000000 0x10000000 SDRAM 3 + * + * 0x30000000 0x10000000 SDRAM 4 + * + * The above four are aliases to the same memory location (0x00000000) + * + * 0x48000000 0x4000000 PCI Memory + * + * 0x50000000 0x10000000 Not Mapped EXP BUS + * + * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr + * + * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG + * + * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG + * + * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL + * + * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG + */ + +/* + * SDRAM + */ +#define IXP425_SDRAM_BASE (0x00000000) +#define IXP425_SDRAM_BASE_ALT (0x10000000) + + +/* + * PCI Configuration space + */ +#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000) +#define IXP425_PCI_CFG_BASE_VIRT (0xFFFD0000) +#define IXP425_PCI_CFG_REGION_SIZE (0x00001000) + +/* + * Expansion BUS Configuration registers + */ +#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000) +#define IXP425_EXP_CFG_BASE_VIRT (0xFFFD1000) +#define IXP425_EXP_CFG_REGION_SIZE (0x00001000) + +/* + * Peripheral space + */ +#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000) +#define IXP425_PERIPHERAL_BASE_VIRT (0xFFFD2000) +#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000) + +/* + * SDRAM configuration registers + */ +#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000) + +/* + * Q Manager space .. not static mapped + */ +#define IXP425_QMGR_BASE_PHYS (0x60000000) +#define IXP425_QMGR_BASE_VIRT (0xFFFDE000) +#define IXP425_QMGR_REGION_SIZE (0x00004000) + +/* + * Expansion BUS + * + * Expansion Bus 'lives' at either base1 or base 2 depending on the value of + * Exp Bus config registers: + * + * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero, + * and The expansion bus to IXP425_EXP_BUS_BASE2 + */ +#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000) +#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000) +#define IXP425_EXP_BUS_BASE2_VIRT (0xF0000000) + +#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS +#define IXP425_EXP_BUS_BASE_VIRT IXP425_EXP_BUS_BASE2_VIRT + +#define IXP425_EXP_BUS_REGION_SIZE (0x08000000) +#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000) + +#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000) +#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000) +#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000) +#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000) +#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000) +#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000) +#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000) +#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000) + +#define IXP425_EXP_BUS_CS0_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x00000000) +#define IXP425_EXP_BUS_CS1_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x01000000) +#define IXP425_EXP_BUS_CS2_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x02000000) +#define IXP425_EXP_BUS_CS3_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x03000000) +#define IXP425_EXP_BUS_CS4_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x04000000) +#define IXP425_EXP_BUS_CS5_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x05000000) +#define IXP425_EXP_BUS_CS6_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x06000000) +#define IXP425_EXP_BUS_CS7_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x07000000) + +#define IXP425_FLASH_WRITABLE (0x2) +#define IXP425_FLASH_DEFAULT (0xbcd23c40) +#define IXP425_FLASH_WRITE (0xbcd23c42) + + +#define IXP425_EXP_CS0_OFFSET 0x00 +#define IXP425_EXP_CS1_OFFSET 0x04 +#define IXP425_EXP_CS2_OFFSET 0x08 +#define IXP425_EXP_CS3_OFFSET 0x0C +#define IXP425_EXP_CS4_OFFSET 0x10 +#define IXP425_EXP_CS5_OFFSET 0x14 +#define IXP425_EXP_CS6_OFFSET 0x18 +#define IXP425_EXP_CS7_OFFSET 0x1C +#define IXP425_EXP_CFG0_OFFSET 0x20 +#define IXP425_EXP_CFG1_OFFSET 0x24 +#define IXP425_EXP_CFG2_OFFSET 0x28 +#define IXP425_EXP_CFG3_OFFSET 0x2C + +/* + * Expansion Bus Controller registers. + */ +#ifndef __ASSEMBLY__ +#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_VIRT+(x))) +#else +#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x)) +#endif + +#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET) +#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET) +#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET) +#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET) +#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET) +#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET) +#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET) +#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET) + +#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET) +#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET) +#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET) +#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET) + +/* + * SDRAM Controller registers. + */ +#define IXP425_SDR_CONFIG_OFFSET 0x00 +#define IXP425_SDR_REFRESH_OFFSET 0x04 +#define IXP425_SDR_IR_OFFSET 0x08 + +#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) + +#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) +#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) +#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) + +/* + * UART registers + */ +#define IXP425_UART1 0 +#define IXP425_UART2 0x1000 + +#define IXP425_UART_RBR_OFFSET 0x00 +#define IXP425_UART_THR_OFFSET 0x00 +#define IXP425_UART_DLL_OFFSET 0x00 +#define IXP425_UART_IER_OFFSET 0x04 +#define IXP425_UART_DLH_OFFSET 0x04 +#define IXP425_UART_IIR_OFFSET 0x08 +#define IXP425_UART_FCR_OFFSET 0x00 +#define IXP425_UART_LCR_OFFSET 0x0c +#define IXP425_UART_MCR_OFFSET 0x10 +#define IXP425_UART_LSR_OFFSET 0x14 +#define IXP425_UART_MSR_OFFSET 0x18 +#define IXP425_UART_SPR_OFFSET 0x1c +#define IXP425_UART_ISR_OFFSET 0x20 + +#define IXP425_UART_CFG_BASE_PHYS (0xc8000000) + +#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET) +#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET) +#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET) +#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET) +#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET) +#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET) +#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET) +#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET) +#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET) +#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET) +#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET) +#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET) +#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET) + +#define IER_DMAE (1 << 7) /* DMA Requests Enable */ +#define IER_UUE (1 << 6) /* UART Unit Enable */ +#define IER_NRZE (1 << 5) /* NRZ coding Enable */ +#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ +#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ +#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ +#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ +#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ + +#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ +#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ +#define IIR_TOD (1 << 3) /* Time Out Detected */ +#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ +#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ +#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ + +#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ +#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ +#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ +#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ +#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ +#define FCR_ITL_1 (0) +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ +#define LCR_SB (1 << 6) /* Set Break */ +#define LCR_STKYP (1 << 5) /* Sticky Parity */ +#define LCR_EPS (1 << 4) /* Even Parity Select */ +#define LCR_PEN (1 << 3) /* Parity Enable */ +#define LCR_STB (1 << 2) /* Stop Bit */ +#define LCR_WLS1 (1 << 1) /* Word Length Select */ +#define LCR_WLS0 (1 << 0) /* Word Length Select */ + +#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ +#define LSR_TEMT (1 << 6) /* Transmitter Empty */ +#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ +#define LSR_BI (1 << 4) /* Break Interrupt */ +#define LSR_FE (1 << 3) /* Framing Error */ +#define LSR_PE (1 << 2) /* Parity Error */ +#define LSR_OE (1 << 1) /* Overrun Error */ +#define LSR_DR (1 << 0) /* Data Ready */ + +#define MCR_LOOP (1 << 4) */ +#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ +#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ +#define MCR_RTS (1 << 1) /* Request to Send */ +#define MCR_DTR (1 << 0) /* Data Terminal Ready */ + +#define MSR_DCD (1 << 7) /* Data Carrier Detect */ +#define MSR_RI (1 << 6) /* Ring Indicator */ +#define MSR_DSR (1 << 5) /* Data Set Ready */ +#define MSR_CTS (1 << 4) /* Clear To Send */ +#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ +#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ +#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ +#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ + +#define IXP425_CONSOLE_UART_BASE_VIRT IXP425_UART1_BASE_VIRT +#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS +/* + * Peripheral Space Registers + */ +#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000) +#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000) +#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000) +#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000) +#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000) +#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000) +#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000) +#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000) +#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000) +#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000) +#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000) +#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000) + +#define IXP425_UART1_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x0000) +#define IXP425_UART2_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x1000) +#define IXP425_PMU_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x2000) +#define IXP425_INTC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x3000) +#define IXP425_GPIO_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x4000) +#define IXP425_TIMER_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x5000) +#define IXP425_NPEA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x6000) +#define IXP425_NPEB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x7000) +#define IXP425_NPEC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x8000) +#define IXP425_EthA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x9000) +#define IXP425_EthB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xA000) +#define IXP425_USB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xB000) + + +/* + * UART Register Definitions , Offsets only as there are 2 UARTS. + * IXP425_UART1_BASE , IXP425_UART2_BASE. + */ + +#undef UART_NO_RX_INTERRUPT + +#define IXP425_UART_XTAL 14745600 + +/* + * Constants to make it easy to access Interrupt Controller registers + */ +#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */ +#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */ +#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ +#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */ +#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */ +#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */ +#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ +#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ + +/* + * Interrupt Controller Register Definitions. + */ +#ifndef __ASSEMBLY__ +#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_VIRT+(x))) +#else +#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x)) +#endif + +#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET) +#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET) +#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET) +#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET) +#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET) +#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET) +#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET) +#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET) + +/* + * Constants to make it easy to access GPIO registers + */ +#define IXP425_GPIO_GPOUTR_OFFSET 0x00 +#define IXP425_GPIO_GPOER_OFFSET 0x04 +#define IXP425_GPIO_GPINR_OFFSET 0x08 +#define IXP425_GPIO_GPISR_OFFSET 0x0C +#define IXP425_GPIO_GPIT1R_OFFSET 0x10 +#define IXP425_GPIO_GPIT2R_OFFSET 0x14 +#define IXP425_GPIO_GPCLKR_OFFSET 0x18 +#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C + +/* + * GPIO Register Definitions. + * [Only perform 32bit reads/writes] + */ +#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_VIRT+(x))) + +#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET) +#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET) +#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET) +#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET) +#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET) +#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET) +#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET) +#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) + +/* + * Constants to make it easy to access Timer Control/Status registers + */ +#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */ +#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ +#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ +#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ +#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ +#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */ +#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */ +#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */ +#define IXP425_OSST_OFFSET 0x20 /* Timer Status */ + +/* + * Operating System Timer Register Definitions. + */ + +#ifndef __ASSEMBLY__ +#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x))) +#else +#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) +#endif + +#define IXP425_OSTS IXP425_TIMER_REG(IXP425_OSTS_OFFSET) +#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) +#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) +#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) +#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET) +#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET) +#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET) +#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET) +#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET) + +/* + * Timer register values and bit definitions + */ +#define IXP425_OST_ENABLE BIT(0) +#define IXP425_OST_ONE_SHOT BIT(1) +/* Low order bits of reload value ignored */ +#define IXP425_OST_RELOAD_MASK (0x3) +#define IXP425_OST_DISABLED (0x0) +#define IXP425_OSST_TIMER_1_PEND BIT(0) +#define IXP425_OSST_TIMER_2_PEND BIT(1) +#define IXP425_OSST_TIMER_TS_PEND BIT(2) +#define IXP425_OSST_TIMER_WDOG_PEND BIT(3) +#define IXP425_OSST_TIMER_WARM_RESET BIT(4) + +/* + * Constants to make it easy to access PCI Control/Status registers + */ +#define PCI_NP_AD_OFFSET 0x00 +#define PCI_NP_CBE_OFFSET 0x04 +#define PCI_NP_WDATA_OFFSET 0x08 +#define PCI_NP_RDATA_OFFSET 0x0c +#define PCI_CRP_AD_CBE_OFFSET 0x10 +#define PCI_CRP_WDATA_OFFSET 0x14 +#define PCI_CRP_RDATA_OFFSET 0x18 +#define PCI_CSR_OFFSET 0x1c +#define PCI_ISR_OFFSET 0x20 +#define PCI_INTEN_OFFSET 0x24 +#define PCI_DMACTRL_OFFSET 0x28 +#define PCI_AHBMEMBASE_OFFSET 0x2c +#define PCI_AHBIOBASE_OFFSET 0x30 +#define PCI_PCIMEMBASE_OFFSET 0x34 +#define PCI_AHBDOORBELL_OFFSET 0x38 +#define PCI_PCIDOORBELL_OFFSET 0x3C +#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 +#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 +#define PCI_ATPDMA0_LENADDR_OFFSET 0x48 +#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C +#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 +#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 + +/* + * PCI Control/Status Registers + */ +#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_VIRT+(x))) + +#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET) +#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET) +#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET) +#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET) +#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) +#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET) +#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET) +#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET) +#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET) +#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET) +#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET) +#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET) +#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET) +#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET) +#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET) +#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET) +#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) +#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) +#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) +#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) +#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) +#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) + +/* + * PCI register values and bit definitions + */ + +/* CSR bit definitions */ +#define PCI_CSR_HOST BIT(0) +#define PCI_CSR_ARBEN BIT(1) +#define PCI_CSR_ADS BIT(2) +#define PCI_CSR_PDS BIT(3) +#define PCI_CSR_ABE BIT(4) +#define PCI_CSR_DBT BIT(5) +#define PCI_CSR_ASE BIT(8) +#define PCI_CSR_IC BIT(15) + +/* ISR (Interrupt status) Register bit definitions */ +#define PCI_ISR_PSE BIT(0) +#define PCI_ISR_PFE BIT(1) +#define PCI_ISR_PPE BIT(2) +#define PCI_ISR_AHBE BIT(3) +#define PCI_ISR_APDC BIT(4) +#define PCI_ISR_PADC BIT(5) +#define PCI_ISR_ADB BIT(6) +#define PCI_ISR_PDB BIT(7) + +/* INTEN (Interrupt Enable) Register bit definitions */ +#define PCI_INTEN_PSE BIT(0) +#define PCI_INTEN_PFE BIT(1) +#define PCI_INTEN_PPE BIT(2) +#define PCI_INTEN_AHBE BIT(3) +#define PCI_INTEN_APDC BIT(4) +#define PCI_INTEN_PADC BIT(5) +#define PCI_INTEN_ADB BIT(6) +#define PCI_INTEN_PDB BIT(7) + +/* + * Shift value for byte enable on NP cmd/byte enable register + */ +#define IXP425_PCI_NP_CBE_BESL 4 + +/* + * PCI commands supported by NP access unit + */ +#define NP_CMD_IOREAD 0x2 +#define NP_CMD_IOWRITE 0x3 +#define NP_CMD_CONFIGREAD 0xa +#define NP_CMD_CONFIGWRITE 0xb +#define NP_CMD_MEMREAD 0x6 +#define NP_CMD_MEMWRITE 0x7 + +#if 0 +#ifndef __ASSEMBLY__ +extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data); +extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data); +extern void ixp425_pci_init(void *); +#endif +#endif + +/* + * Constants for CRP access into local config space + */ +#define CRP_AD_CBE_BESL 20 +#define CRP_AD_CBE_WRITE BIT(16) + +/* + * Clock Speed Definitions. + */ +#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ + + +#endif diff --git a/include/asm-arm/arch-ixp/ixp425pci.h b/include/asm-arm/arch-ixp/ixp425pci.h new file mode 100644 index 0000000..9ea3319 --- /dev/null +++ b/include/asm-arm/arch-ixp/ixp425pci.h @@ -0,0 +1,312 @@ +/* + * IXP PCI Init + * (C) Copyright 2004 eslab.whut.edu.cn + * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IXP425PCI_H_ +#define _IXP425PCI_H_ + +#define TRUE 1 +#define FALSE 0 +#define OK 0 +#define ERROR -1 +#define BOOL int + +#define IXP425_PCI_MAX_BAR_PER_FUNC 6 +#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ + IXP425_PCI_MAX_FUNC_ON_BUS) + +enum PciBarId +{ + CSR_BAR=0, + IO_BAR, + SD_BAR, + NO_BAR +}; + +/*Base address register descriptor*/ +typedef struct +{ + unsigned int size; + unsigned int address; +} PciBar; + +typedef struct +{ + unsigned int bus; + unsigned int device; + unsigned int func; + unsigned int irq; + BOOL error; + unsigned short vendor_id; + unsigned short device_id; + /*We need an extra entry in this array for dummy placeholder*/ + PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1]; +} PciDevice; + +/* Mask definitions*/ +#define IXP425_PCI_TOP_WORD_OF_LONG_MASK 0xffff0000 +#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK 0xff000000 +#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK 0x0000ffff +#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff +#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f +#define IXP425_PCI_MAX_UINT32 0xffffffff + + +#define IXP425_PCI_BAR_QUERY 0xffffffff + +#define IXP425_PCI_BAR_MEM_BASE 0x100000 +#define IXP425_PCI_BAR_IO_BASE 0x000000 + +/*define the maximum number of bus segments - we support a single segment*/ +#define IXP425_PCI_MAX_BUS 1 +/*define the maximum number of cards per bus segment*/ +#define IXP425_PCI_MAX_DEV 4 +/*define the maximum number of functions per device*/ +#define IXP425_PCI_MAX_FUNC 8 +/* define the maximum number of separate functions that we can + potentially have on the bus*/ +#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC * \ + IXP425_PCI_MAX_DEV * \ + IXP425_PCI_MAX_BUS) +/*define the maximum number of BARs per function*/ +#define IXP425_PCI_MAX_BAR_PER_FUNC 6 +#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ + IXP425_PCI_MAX_FUNC_ON_BUS) + +#define PCI_NP_CBE_BESL (4) +#define PCI_NP_AD_FUNCSL (8) + +#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v)) +#define REG_READ(b,o,v) ((v)=(*(volatile unsigned int*)((b+o)))) + +#define PCI_DELAY 500 +#define USEC_LOOP_COUNT 533 +#define PCI_SETTLE_USEC 200 +#define PCI_MIN_RESET_ASSERT_USEC 2000 + +/*Register addressing definitions for PCI controller configuration + and status registers*/ + +#define PCI_CSR_BASE (0xC0000000) +/* +#define PCI_NP_AD_OFFSET (0x00) +#define PCI_NP_CBE_OFFSET (0x04) +#define PCI_NP_WDATA_OFFSET (0x08) +#define PCI_NP_RDATA_OFFSET (0x0C) +#define PCI_CRP_OFFSET (0x10) +#define PCI_CRP_WDATA_OFFSET (0x14) +#define PCI_CRP_RDATA_OFFSET (0x18) +#define PCI_CSR_OFFSET (0x1C) +#define PCI_ISR_OFFSET (0x20) +#define PCI_INTEN_OFFSET (0x24) +#define PCI_DMACTRL_OFFSET (0x28) +#define PCI_AHBMEMBASE_OFFSET (0x2C) +#define PCI_AHBIOBASE_OFFSET (0x30) +#define PCI_PCIMEMBASE_OFFSET (0x34) +#define PCI_AHBDOORBELL_OFFSET (0x38) +#define PCI_PCIDOORBELL_OFFSET (0x3C) +#define PCI_ATPDMA0_AHBADDR (0x40) +#define PCI_ATPDMA0_PCIADDR (0x44) +#define PCI_ATPDMA0_LENADDR (0x48) +#define PCI_ATPDMA1_AHBADDR (0x4C) +#define PCI_ATPDMA1_PCIADDR (0x50) +#define PCI_ATPDMA1_LENADDR (0x54) +#define PCI_PTADMA0_AHBADDR (0x58) +#define PCI_PTADMA0_PCIADDR (0x5C) +#define PCI_PTADMA0_LENADDR (0x60) +#define PCI_PTADMA1_AHBADDR (0x64) +#define PCI_PTADMA1_PCIADDR (0x68) +#define PCI_PTADMA1_LENADDR (0x6C) +*/ +/*Non prefetch registers bit definitions*/ +/* +#define NP_CMD_INTACK (0x0) +#define NP_CMD_SPECIAL (0x1) +#define NP_CMD_IOREAD (0x2) +#define NP_CMD_IOWRITE (0x3) +#define NP_CMD_MEMREAD (0x6) +#define NP_CMD_MEMWRITE (0x7) +#define NP_CMD_CONFIGREAD (0xa) +#define NP_CMD_CONFIGWRITE (0xb) +*/ + +/*define the default setting of the AHB memory base reg*/ +#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203 +#define IXP425_PCI_AHBIOBASE_DEFAULT 0x0 +#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0 + +/*define the default settings for the controller's BARs*/ +#ifdef IXP425_PCI_SIMPLE_MAPPING +#define IXP425_PCI_BAR_0_DEFAULT 0x00000000 +#define IXP425_PCI_BAR_1_DEFAULT 0x01000000 +#define IXP425_PCI_BAR_2_DEFAULT 0x02000000 +#define IXP425_PCI_BAR_3_DEFAULT 0x03000000 +#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 +#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 +#else +#define IXP425_PCI_BAR_0_DEFAULT 0x40000000 +#define IXP425_PCI_BAR_1_DEFAULT 0x41000000 +#define IXP425_PCI_BAR_2_DEFAULT 0x42000000 +#define IXP425_PCI_BAR_3_DEFAULT 0x43000000 +#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 +#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 +#endif + +/*Configuration Port register bit definitions*/ +#define PCI_CRP_WRITE BIT(16) + +/*ISR (Interrupt status) Register bit definitions*/ +#define PCI_ISR_PSE BIT(0) +#define PCI_ISR_PFE BIT(1) +#define PCI_ISR_PPE BIT(2) +#define PCI_ISR_AHBE BIT(3) +#define PCI_ISR_APDC BIT(4) +#define PCI_ISR_PADC BIT(5) +#define PCI_ISR_ADB BIT(6) +#define PCI_ISR_PDB BIT(7) + +/*INTEN (Interrupt Enable) Register bit definitions*/ +#define PCI_INTEN_PSE BIT(0) +#define PCI_INTEN_PFE BIT(1) +#define PCI_INTEN_PPE BIT(2) +#define PCI_INTEN_AHBE BIT(3) +#define PCI_INTEN_APDC BIT(4) +#define PCI_INTEN_PADC BIT(5) +#define PCI_INTEN_ADB BIT(6) +#define PCI_INTEN_PDB BIT(7) + +/*PCI configuration regs.*/ + +#define PCI_CFG_VENDOR_ID 0x00 +#define PCI_CFG_DEVICE_ID 0x02 +#define PCI_CFG_COMMAND 0x04 +#define PCI_CFG_STATUS 0x06 +#define PCI_CFG_REVISION 0x08 +#define PCI_CFG_PROGRAMMING_IF 0x09 +#define PCI_CFG_SUBCLASS 0x0a +#define PCI_CFG_CLASS 0x0b +#define PCI_CFG_CACHE_LINE_SIZE 0x0c +#define PCI_CFG_LATENCY_TIMER 0x0d +#define PCI_CFG_HEADER_TYPE 0x0e +#define PCI_CFG_BIST 0x0f +#define PCI_CFG_BASE_ADDRESS_0 0x10 +#define PCI_CFG_BASE_ADDRESS_1 0x14 +#define PCI_CFG_BASE_ADDRESS_2 0x18 +#define PCI_CFG_BASE_ADDRESS_3 0x1c +#define PCI_CFG_BASE_ADDRESS_4 0x20 +#define PCI_CFG_BASE_ADDRESS_5 0x24 +#define PCI_CFG_CIS 0x28 +#define PCI_CFG_SUB_VENDOR_ID 0x2c +#define PCI_CFG_SUB_SYSTEM_ID 0x2e +#define PCI_CFG_EXPANSION_ROM 0x30 +#define PCI_CFG_RESERVED_0 0x34 +#define PCI_CFG_RESERVED_1 0x38 +#define PCI_CFG_DEV_INT_LINE 0x3c +#define PCI_CFG_DEV_INT_PIN 0x3d +#define PCI_CFG_MIN_GRANT 0x3e +#define PCI_CFG_MAX_LATENCY 0x3f +#define PCI_CFG_SPECIAL_USE 0x41 +#define PCI_CFG_MODE 0x43 + +/*Specify the initial command we send to PCI devices*/ +#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE \ + | PCI_CMD_MEM_ENABLE \ + | PCI_CMD_MASTER_ENABLE \ + | PCI_CMD_WI_ENABLE) + +/*define the sub vendor and subsystem to be used */ +#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000 + +#define PCI_IRQ_LINES 4 + +#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ +#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ +#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ +#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */ +#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */ +#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */ +#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */ +#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */ +#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */ +#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */ + + +/*CSR Register bit definitions*/ +#define PCI_CSR_HOST BIT(0) +#define PCI_CSR_ARBEN BIT(1) +#define PCI_CSR_ADS BIT(2) +#define PCI_CSR_PDS BIT(3) +#define PCI_CSR_ABE BIT(4) +#define PCI_CSR_DBT BIT(5) +#define PCI_CSR_ASE BIT(8) +#define PCI_CSR_IC BIT(15) + +/*Configuration command bit definitions*/ +#define PCI_CFG_CMD_IOAE BIT(0) +#define PCI_CFG_CMD_MAE BIT(1) +#define PCI_CFG_CMD_BME BIT(2) +#define PCI_CFG_CMD_MWIE BIT(4) +#define PCI_CFG_CMD_SER BIT(8) +#define PCI_CFG_CMD_FBBE BIT(9) +#define PCI_CFG_CMD_MDPE BIT(24) +#define PCI_CFG_CMD_STA BIT(27) +#define PCI_CFG_CMD_RTA BIT(28) +#define PCI_CFG_CMD_RMA BIT(29) +#define PCI_CFG_CMD_SSE BIT(30) +#define PCI_CFG_CMD_DPE BIT(31) + +/*DMACTRL DMA Control and status Register*/ +#define PCI_DMACTRL_APDCEN BIT(0) +#define PCI_DMACTRL_APDC0 BIT(4) +#define PCI_DMACTRL_APDE0 BIT(5) +#define PCI_DMACTRL_APDC1 BIT(6) +#define PCI_DMACTRL_APDE1 BIT(7) +#define PCI_DMACTRL_PADCEN BIT(8) +#define PCI_DMACTRL_PADC0 BIT(12) +#define PCI_DMACTRL_PADE0 BIT(13) +#define PCI_DMACTRL_PADC1 BIT(14) +#define PCI_DMACTRL_PADE1 BIT(15) + +/* GPIO related register */ +#undef IXP425_GPIO_GPOUTR +#undef IXP425_GPIO_GPOER +#undef IXP425_GPIO_GPINR +#undef IXP425_GPIO_GPISR +#undef IXP425_GPIO_GPIT1R +#undef IXP425_GPIO_GPIT2R +#undef IXP425_GPIO_GPCLKR + +#define IXP425_GPIO_GPOUTR 0xC8004000 +#define IXP425_GPIO_GPOER 0xC8004004 +#define IXP425_GPIO_GPINR 0xC8004008 +#define IXP425_GPIO_GPISR 0xC800400C +#define IXP425_GPIO_GPIT1R 0xC8004010 +#define IXP425_GPIO_GPIT2R 0xC8004014 +#define IXP425_GPIO_GPCLKR 0xC8004018 + +#define READ_GPIO_REG(addr,val) \ + (val) = *((volatile int *)(addr)); +#define WRITE_GPIO_REG(addr,val) \ + *((volatile int *)(addr)) = (val); + +#endif diff --git a/include/asm-arm/arch-ks8695/platform.h b/include/asm-arm/arch-ks8695/platform.h new file mode 100644 index 0000000..de20015 --- /dev/null +++ b/include/asm-arm/arch-ks8695/platform.h @@ -0,0 +1,306 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __address_h +#define __address_h 1 + +#define KS8695_SDRAM_START 0x00000000 +#define KS8695_SDRAM_SIZE 0x01000000 +#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE +#define KS8695_MEM_START KS8695_SDRAM_START + +#define KS8695_PCMCIA_IO_BASE 0x03800000 +#define KS8695_PCMCIA_IO_SIZE 0x00040000 + +#define KS8695_IO_BASE 0x03FF0000 +#define KS8695_IO_SIZE 0x00010000 + +#define KS8695_SYSTEN_CONFIG 0x00 +#define KS8695_SYSTEN_BUS_CLOCK 0x04 + +#define KS8695_FLASH_START 0x02800000 +#define KS8695_FLASH_SIZE 0x00400000 + +/*i/o control registers offset difinitions*/ +#define KS8695_IO_CTRL0 0x4000 +#define KS8695_IO_CTRL1 0x4004 +#define KS8695_IO_CTRL2 0x4008 +#define KS8695_IO_CTRL3 0x400C + +/*memory control registers offset difinitions*/ +#define KS8695_MEM_CTRL0 0x4010 +#define KS8695_MEM_CTRL1 0x4014 +#define KS8695_MEM_CTRL2 0x4018 +#define KS8695_MEM_CTRL3 0x401C +#define KS8695_MEM_GENERAL 0x4020 +#define KS8695_SDRAM_CTRL0 0x4030 +#define KS8695_SDRAM_CTRL1 0x4034 +#define KS8695_SDRAM_GENERAL 0x4038 +#define KS8695_SDRAM_BUFFER 0x403C +#define KS8695_SDRAM_REFRESH 0x4040 + +/*WAN control registers offset difinitions*/ +#define KS8695_WAN_DMA_TX 0x6000 +#define KS8695_WAN_DMA_RX 0x6004 +#define KS8695_WAN_DMA_TX_START 0x6008 +#define KS8695_WAN_DMA_RX_START 0x600C +#define KS8695_WAN_TX_LIST 0x6010 +#define KS8695_WAN_RX_LIST 0x6014 +#define KS8695_WAN_MAC_LOW 0x6018 +#define KS8695_WAN_MAC_HIGH 0x601C +#define KS8695_WAN_MAC_ELOW 0x6080 +#define KS8695_WAN_MAC_EHIGH 0x6084 + +/*LAN control registers offset difinitions*/ +#define KS8695_LAN_DMA_TX 0x8000 +#define KS8695_LAN_DMA_RX 0x8004 +#define KS8695_LAN_DMA_TX_START 0x8008 +#define KS8695_LAN_DMA_RX_START 0x800C +#define KS8695_LAN_TX_LIST 0x8010 +#define KS8695_LAN_RX_LIST 0x8014 +#define KS8695_LAN_MAC_LOW 0x8018 +#define KS8695_LAN_MAC_HIGH 0x801C +#define KS8695_LAN_MAC_ELOW 0X8080 +#define KS8695_LAN_MAC_EHIGH 0X8084 + +/*HPNA control registers offset difinitions*/ +#define KS8695_HPNA_DMA_TX 0xA000 +#define KS8695_HPNA_DMA_RX 0xA004 +#define KS8695_HPNA_DMA_TX_START 0xA008 +#define KS8695_HPNA_DMA_RX_START 0xA00C +#define KS8695_HPNA_TX_LIST 0xA010 +#define KS8695_HPNA_RX_LIST 0xA014 +#define KS8695_HPNA_MAC_LOW 0xA018 +#define KS8695_HPNA_MAC_HIGH 0xA01C +#define KS8695_HPNA_MAC_ELOW 0xA080 +#define KS8695_HPNA_MAC_EHIGH 0xA084 + +/*UART control registers offset difinitions*/ +#define KS8695_UART_RX_BUFFER 0xE000 +#define KS8695_UART_TX_HOLDING 0xE004 + +#define KS8695_UART_FIFO_CTRL 0xE008 +#define KS8695_UART_FIFO_TRIG01 0x00 +#define KS8695_UART_FIFO_TRIG04 0x80 +#define KS8695_UART_FIFO_TXRST 0x03 +#define KS8695_UART_FIFO_RXRST 0x02 +#define KS8695_UART_FIFO_FEN 0x01 + +#define KS8695_UART_LINE_CTRL 0xE00C +#define KS8695_UART_LINEC_BRK 0x40 +#define KS8695_UART_LINEC_EPS 0x10 +#define KS8695_UART_LINEC_PEN 0x08 +#define KS8695_UART_LINEC_STP2 0x04 +#define KS8695_UART_LINEC_WLEN8 0x03 +#define KS8695_UART_LINEC_WLEN7 0x02 +#define KS8695_UART_LINEC_WLEN6 0x01 +#define KS8695_UART_LINEC_WLEN5 0x00 + +#define KS8695_UART_MODEM_CTRL 0xE010 +#define KS8695_UART_MODEMC_RTS 0x02 +#define KS8695_UART_MODEMC_DTR 0x01 + +#define KS8695_UART_LINE_STATUS 0xE014 +#define KS8695_UART_LINES_TXFE 0x20 +#define KS8695_UART_LINES_BE 0x10 +#define KS8695_UART_LINES_FE 0x08 +#define KS8695_UART_LINES_PE 0x04 +#define KS8695_UART_LINES_OE 0x02 +#define KS8695_UART_LINES_RXFE 0x01 +#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE) + +#define KS8695_UART_MODEM_STATUS 0xE018 +#define KS8695_UART_MODEM_DCD 0x80 +#define KS8695_UART_MODEM_DSR 0x20 +#define KS8695_UART_MODEM_CTS 0x10 +#define KS8695_UART_MODEM_DDCD 0x08 +#define KS8695_UART_MODEM_DDSR 0x02 +#define KS8695_UART_MODEM_DCTS 0x01 +#define UART8695_MODEM_ANY 0xFF + +#define KS8695_UART_DIVISOR 0xE01C +#define KS8695_UART_STATUS 0xE020 + +/*Interrupt controlller registers offset difinitions*/ +#define KS8695_INT_CONTL 0xE200 +#define KS8695_INT_ENABLE 0xE204 +#define KS8695_INT_ENABLE_MODEM 0x0800 +#define KS8695_INT_ENABLE_ERR 0x0400 +#define KS8695_INT_ENABLE_RX 0x0200 +#define KS8695_INT_ENABLE_TX 0x0100 + +#define KS8695_INT_STATUS 0xE208 +#define KS8695_INT_WAN_PRIORITY 0xE20C +#define KS8695_INT_HPNA_PRIORITY 0xE210 +#define KS8695_INT_LAN_PRIORITY 0xE214 +#define KS8695_INT_TIMER_PRIORITY 0xE218 +#define KS8695_INT_UART_PRIORITY 0xE21C +#define KS8695_INT_EXT_PRIORITY 0xE220 +#define KS8695_INT_CHAN_PRIORITY 0xE224 +#define KS8695_INT_BUSERROR_PRO 0xE228 +#define KS8695_INT_MASK_STATUS 0xE22C +#define KS8695_FIQ_PEND_PRIORITY 0xE230 +#define KS8695_IRQ_PEND_PRIORITY 0xE234 + +/*timer registers offset difinitions*/ +#define KS8695_TIMER_CTRL 0xE400 +#define KS8695_TIMER1 0xE404 +#define KS8695_TIMER0 0xE408 +#define KS8695_TIMER1_PCOUNT 0xE40C +#define KS8695_TIMER0_PCOUNT 0xE410 + +/*GPIO registers offset difinitions*/ +#define KS8695_GPIO_MODE 0xE600 +#define KS8695_GPIO_CTRL 0xE604 +#define KS8695_GPIO_DATA 0xE608 + +/*SWITCH registers offset difinitions*/ +#define KS8695_SWITCH_CTRL0 0xE800 +#define KS8695_SWITCH_CTRL1 0xE804 +#define KS8695_SWITCH_PORT1 0xE808 +#define KS8695_SWITCH_PORT2 0xE80C +#define KS8695_SWITCH_PORT3 0xE810 +#define KS8695_SWITCH_PORT4 0xE814 +#define KS8695_SWITCH_PORT5 0xE818 +#define KS8695_SWITCH_AUTO0 0xE81C +#define KS8695_SWITCH_AUTO1 0xE820 +#define KS8695_SWITCH_LUE_CTRL 0xE824 +#define KS8695_SWITCH_LUE_HIGH 0xE828 +#define KS8695_SWITCH_LUE_LOW 0xE82C +#define KS8695_SWITCH_ADVANCED 0xE830 + +#define KS8695_SWITCH_LPPM12 0xE874 +#define KS8695_SWITCH_LPPM34 0xE878 + +/*host communication registers difinitions*/ +#define KS8695_DSCP_HIGH 0xE834 +#define KS8695_DSCP_LOW 0xE838 +#define KS8695_SWITCH_MAC_HIGH 0xE83C +#define KS8695_SWITCH_MAC_LOW 0xE840 + +/*miscellaneours registers difinitions*/ +#define KS8695_MANAGE_COUNTER 0xE844 +#define KS8695_MANAGE_DATA 0xE848 +#define KS8695_LAN12_POWERMAGR 0xE84C +#define KS8695_LAN34_POWERMAGR 0xE850 + +#define KS8695_DEVICE_ID 0xEA00 +#define KS8695_REVISION_ID 0xEA04 + +#define KS8695_MISC_CONTROL 0xEA08 +#define KS8695_WAN_CONTROL 0xEA0C +#define KS8695_WAN_POWERMAGR 0xEA10 +#define KS8695_WAN_PHY_CONTROL 0xEA14 +#define KS8695_WAN_PHY_STATUS 0xEA18 + +/* bus clock definitions*/ +#define KS8695_BUS_CLOCK_125MHZ 0x0 +#define KS8695_BUS_CLOCK_100MHZ 0x1 +#define KS8695_BUS_CLOCK_62MHZ 0x2 +#define KS8695_BUS_CLOCK_50MHZ 0x3 +#define KS8695_BUS_CLOCK_41MHZ 0x4 +#define KS8695_BUS_CLOCK_33MHZ 0x5 +#define KS8695_BUS_CLOCK_31MHZ 0x6 +#define KS8695_BUS_CLOCK_25MHZ 0x7 + +/* ------------------------------------------------------------------------------- + * definations for IRQ + * -------------------------------------------------------------------------------*/ + +#define KS8695_INT_EXT_INT0 2 +#define KS8695_INT_EXT_INT1 3 +#define KS8695_INT_EXT_INT2 4 +#define KS8695_INT_EXT_INT3 5 +#define KS8695_INT_TIMERINT0 6 +#define KS8695_INT_TIMERINT1 7 +#define KS8695_INT_UART_TX 8 +#define KS8695_INT_UART_RX 9 +#define KS8695_INT_UART_LINE_ERR 10 +#define KS8695_INT_UART_MODEMS 11 +#define KS8695_INT_LAN_STOP_RX 12 +#define KS8695_INT_LAN_STOP_TX 13 +#define KS8695_INT_LAN_BUF_RX_STATUS 14 +#define KS8695_INT_LAN_BUF_TX_STATUS 15 +#define KS8695_INT_LAN_RX_STATUS 16 +#define KS8695_INT_LAN_TX_STATUS 17 +#define KS8695_INT_HPAN_STOP_RX 18 +#define KS8695_INT_HPNA_STOP_TX 19 +#define KS8695_INT_HPNA_BUF_RX_STATUS 20 +#define KS8695_INT_HPNA_BUF_TX_STATUS 21 +#define KS8695_INT_HPNA_RX_STATUS 22 +#define KS8695_INT_HPNA_TX_STATUS 23 +#define KS8695_INT_BUS_ERROR 24 +#define KS8695_INT_WAN_STOP_RX 25 +#define KS8695_INT_WAN_STOP_TX 26 +#define KS8695_INT_WAN_BUF_RX_STATUS 27 +#define KS8695_INT_WAN_BUF_TX_STATUS 28 +#define KS8695_INT_WAN_RX_STATUS 29 +#define KS8695_INT_WAN_TX_STATUS 30 + +#define KS8695_INT_UART KS8695_INT_UART_TX + +/* ------------------------------------------------------------------------------- + * Interrupt bit positions + * + * ------------------------------------------------------------------------------- + */ + +#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 ) +#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 ) +#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 ) +#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 ) +#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 ) +#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 ) +#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX ) +#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX ) +#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR ) +#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS ) +#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX ) +#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX ) +#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS ) +#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS ) +#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) +#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) +#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX ) +#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX ) +#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS ) +#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS +#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS ) +#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS ) +#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR ) +#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX ) +#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX ) +#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS ) +#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS ) +#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS ) +#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS ) + +#define KS8695_SC_VALID_INT 0xFFFFFFFF +#define MAXIRQNUM 31 + +/* + * Timer definitions + * + * Use timer 1 & 2 + * (both run at 25MHz). + * + */ +#define TICKS_PER_uSEC 25 +#define mSEC_1 1000 +#define mSEC_10 (mSEC_1 * 10) + +#endif + +/* END */ diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h new file mode 100644 index 0000000..2ac5ea2 --- /dev/null +++ b/include/asm-arm/arch-pxa/bitfield.h @@ -0,0 +1,112 @@ +/* + * FILE bitfield.h + * + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) + * Language C or ARM Assembly + * Purpose Definition of macros to operate on bit fields. + */ + + +#ifndef __BITFIELD_H +#define __BITFIELD_H + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long) (Data)) +#else +#define UData(Data) (Data) +#endif + + +/* + * MACRO: Fld + * + * Purpose + * The macro "Fld" encodes a bit field, given its size and its shift value + * with respect to bit 0. + * + * Note + * A more intuitive way to encode bit fields would have been to use their + * mask. However, extracting size and shift value information from a bit + * field's mask is cumbersome and might break the assembler (255-character + * line-size limit). + * + * Input + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. + * + * Output + * Fld Encoded bit field. + */ + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + + +/* + * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit + * + * Purpose + * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return + * the size, shift value, mask, aligned mask, and first bit of a + * bit field. + * + * Input + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. + */ + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) +#define F1stBit(Field) (UData (1) << FShft (Field)) + + +/* + * MACRO: FInsrt + * + * Purpose + * The macro "FInsrt" inserts a value into a bit field by shifting the + * former appropriately. + * + * Input + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FInsrt Bit-field value positioned appropriately. + */ + +#define FInsrt(Value, Field) \ + (UData (Value) << FShft (Field)) + + +/* + * MACRO: FExtr + * + * Purpose + * The macro "FExtr" extracts the value of a bit field by masking and + * shifting it appropriately. + * + * Input + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FExtr Bit-field value. + */ + +#define FExtr(Data, Field) \ + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) + + +#endif /* __BITFIELD_H */ diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h new file mode 100644 index 0000000..3ff1d26 --- /dev/null +++ b/include/asm-arm/arch-pxa/hardware.h @@ -0,0 +1,154 @@ +/* + * linux/include/asm-arm/arch-pxa/hardware.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: This file was taken from linux-2.4.19-rmk4-pxa1 + * + * - 2003/01/20 implementation specifics activated + * Robert Schwebel + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include +#include + + +/* + * These are statically mapped PCMCIA IO space for designs using it as a + * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. + * The actual PCMCIA code is mapping required IO region at run time. + */ +#define PCMCIA_IO_0_BASE 0xf6000000 +#define PCMCIA_IO_1_BASE 0xf7000000 + + +/* + * We requires absolute addresses. + */ +#define PCIO_BASE 0 + +/* + * Workarounds for at least 2 errata so far require this. + * The mapping is set in mach-pxa/generic.c. + */ +#define UNCACHED_PHYS_0 0xff000000 +#define UNCACHED_ADDR UNCACHED_PHYS_0 + +/* + * Intel PXA internal I/O mappings: + * + * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff + * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff + * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff + */ + +/* FIXME: Only this does work for u-boot... find out why... [RS] */ +#define UBOOT_REG_FIX 1 + +#ifndef UBOOT_REG_FIX +#ifndef __ASSEMBLY__ + +#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) +#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) + +/* + * This __REG() version gives the same results as the one above, except + * that we are fooling gcc somehow so it generates far better and smaller + * assembly code for access to contigous registers. It's a shame that gcc + * doesn't guess this by itself. + */ +#include +typedef struct { volatile u32 offset[4096]; } __regbase; +# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] +# define __REG(x) __REGP(io_p2v(x)) +#endif + +/* Let's kick gcc's ass again... */ +# define __REG2(x,y) \ + ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ + : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) + +# define __PREG(x) (io_v2p((u32)&(x))) + +#else + +# define __REG(x) io_p2v(x) +# define __PREG(x) io_v2p(x) + +# undef io_p2v +# undef __REG +# ifndef __ASSEMBLY__ +# define io_p2v(PhAdd) (PhAdd) +# define __REG(x) (*((volatile u32 *)io_p2v(x))) +# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) +# else +# define __REG(x) (x) +# endif +#endif /* UBOOT_REG_FIX */ + +#include "pxa-regs.h" + +#ifndef __ASSEMBLY__ + +/* + * GPIO edge detection for IRQs: + * IRQs are generated on Falling-Edge, Rising-Edge, or both. + * This must be called *before* the corresponding IRQ is registered. + * Use this instead of directly setting GRER/GFER. + */ +#define GPIO_FALLING_EDGE 1 +#define GPIO_RISING_EDGE 2 +#define GPIO_BOTH_EDGES 3 +extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask ); + +/* + * Handy routine to set GPIO alternate functions + */ +extern void set_GPIO_mode( int gpio_mode ); + +/* + * return current lclk frequency in units of 10kHz + */ +extern unsigned int get_lclk_frequency_10khz(void); + +#endif + + +/* + * Implementation specifics + */ + +#ifdef CONFIG_ARCH_LUBBOCK +#include "lubbock.h" +#endif + +#ifdef CONFIG_ARCH_PXA_IDP +#include "idp.h" +#endif + +#ifdef CONFIG_ARCH_PXA_CERF +#include "cerf.h" +#endif + +#ifdef CONFIG_ARCH_CSB226 +#include "csb226.h" +#endif + +#ifdef CONFIG_ARCH_INNOKOM +#include "innokom.h" +#endif + +#ifdef CONFIG_ARCH_PLEB +#include "pleb.h" +#endif + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h new file mode 100644 index 0000000..a62679a --- /dev/null +++ b/include/asm-arm/arch-pxa/mmc.h @@ -0,0 +1,200 @@ +/* + * linux/drivers/mmc/mmc_pxa.h + * + * Author: Vladimir Shebordaev, Igor Oblakov + * Copyright: MontaVista Software Inc. + * + * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MMC_PXA_P_H__ +#define __MMC_PXA_P_H__ + +/* PXA-250 MMC controller registers */ + +/* MMC_STRPCL */ +#define MMC_STRPCL_STOP_CLK (0x0001UL) +#define MMC_STRPCL_START_CLK (0x0002UL) + +/* MMC_STAT */ +#define MMC_STAT_END_CMD_RES (0x0001UL << 13) +#define MMC_STAT_PRG_DONE (0x0001UL << 12) +#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) +#define MMC_STAT_CLK_EN (0x0001UL << 8) +#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) +#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) +#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) +#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) +#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) +#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) +#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) +#define MMC_STAT_READ_TIME_OUT (0x0001UL) + +#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ + |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ + |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) + +/* MMC_CLKRT */ +#define MMC_CLKRT_20MHZ (0x0000UL) +#define MMC_CLKRT_10MHZ (0x0001UL) +#define MMC_CLKRT_5MHZ (0x0002UL) +#define MMC_CLKRT_2_5MHZ (0x0003UL) +#define MMC_CLKRT_1_25MHZ (0x0004UL) +#define MMC_CLKRT_0_625MHZ (0x0005UL) +#define MMC_CLKRT_0_3125MHZ (0x0006UL) + +/* MMC_SPI */ +#define MMC_SPI_DISABLE (0x00UL) +#define MMC_SPI_EN (0x01UL) +#define MMC_SPI_CS_EN (0x01UL << 2) +#define MMC_SPI_CS_ADDRESS (0x01UL << 3) +#define MMC_SPI_CRC_ON (0x01UL << 1) + +/* MMC_CMDAT */ +#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) +#define MMC_CMDAT_INIT (0x0001UL << 6) +#define MMC_CMDAT_BUSY (0x0001UL << 5) +#define MMC_CMDAT_STREAM (0x0001UL << 4) +#define MMC_CMDAT_BLOCK (0x0000UL << 4) +#define MMC_CMDAT_WRITE (0x0001UL << 3) +#define MMC_CMDAT_READ (0x0000UL << 3) +#define MMC_CMDAT_DATA_EN (0x0001UL << 2) +#define MMC_CMDAT_R1 (0x0001UL) +#define MMC_CMDAT_R2 (0x0002UL) +#define MMC_CMDAT_R3 (0x0003UL) + +/* MMC_RESTO */ +#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ + +/* MMC_RDTO */ +#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ + +/* MMC_BLKLEN */ +#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ + +/* MMC_PRTBUF */ +#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) +#define MMC_PRTBUF_BUF_FULL (0x00UL ) + +/* MMC_I_MASK */ +#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_MASK_STOP_CMD (0x01UL << 3) +#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) +#define MMC_I_MASK_PRG_DONE (0x01UL << 1) +#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) +#define MMC_I_MASK_ALL (0x07fUL) + + +/* MMC_I_REG */ +#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_REG_STOP_CMD (0x01UL << 3) +#define MMC_I_REG_END_CMD_RES (0x01UL << 2) +#define MMC_I_REG_PRG_DONE (0x01UL << 1) +#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) +#define MMC_I_REG_ALL (0x007fUL) + +/* MMC_CMD */ +#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ +#define CMD(x) (x) + +#define MMC_DEFAULT_RCA 1 + +#define MMC_BLOCK_SIZE 512 +#define MMC_CMD_RESET 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RCA 3 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_BLOCK 17 +#define MMC_CMD_RD_BLK_MULTI 18 +#define MMC_CMD_WRITE_BLOCK 24 + +#define MMC_MAX_BLOCK_SIZE 512 + +#define MMC_R1_IDLE_STATE 0x01 +#define MMC_R1_ERASE_STATE 0x02 +#define MMC_R1_ILLEGAL_CMD 0x04 +#define MMC_R1_COM_CRC_ERR 0x08 +#define MMC_R1_ERASE_SEQ_ERR 0x01 +#define MMC_R1_ADDR_ERR 0x02 +#define MMC_R1_PARAM_ERR 0x04 + +#define MMC_R1B_WP_ERASE_SKIP 0x0002 +#define MMC_R1B_ERR 0x0004 +#define MMC_R1B_CC_ERR 0x0008 +#define MMC_R1B_CARD_ECC_ERR 0x0010 +#define MMC_R1B_WP_VIOLATION 0x0020 +#define MMC_R1B_ERASE_PARAM 0x0040 +#define MMC_R1B_OOR 0x0080 +#define MMC_R1B_IDLE_STATE 0x0100 +#define MMC_R1B_ERASE_RESET 0x0200 +#define MMC_R1B_ILLEGAL_CMD 0x0400 +#define MMC_R1B_COM_CRC_ERR 0x0800 +#define MMC_R1B_ERASE_SEQ_ERR 0x1000 +#define MMC_R1B_ADDR_ERR 0x2000 +#define MMC_R1B_PARAM_ERR 0x4000 + +typedef struct mmc_cid +{ +/* FIXME: BYTE_ORDER */ + uchar year:4, + month:4; + uchar sn[3]; + uchar fwrev:4, + hwrev:4; + uchar name[6]; + uchar id[3]; +} mmc_cid_t; + +typedef struct mmc_csd +{ + uchar ecc:2, + file_format:2, + tmp_write_protect:1, + perm_write_protect:1, + copy:1, + file_format_grp:1; + uint64_t content_prot_app:1, + rsvd3:4, + write_bl_partial:1, + write_bl_len:4, + r2w_factor:3, + default_ecc:2, + wp_grp_enable:1, + wp_grp_size:5, + erase_grp_mult:5, + erase_grp_size:5, + c_size_mult1:3, + vdd_w_curr_max:3, + vdd_w_curr_min:3, + vdd_r_curr_max:3, + vdd_r_curr_min:3, + c_size:12, + rsvd2:2, + dsr_imp:1, + read_blk_misalign:1, + write_blk_misalign:1, + read_bl_partial:1; + + ushort read_bl_len:4, + ccc:12; + uchar tran_speed; + uchar nsac; + uchar taac; + uchar rsvd1:2, + spec_vers:4, + csd_structure:2; +} mmc_csd_t; + + +#endif /* __MMC_PXA_P_H__ */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h new file mode 100644 index 0000000..41d37d7 --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -0,0 +1,1749 @@ +/* + * linux/include/asm-arm/arch-pxa/pxa-regs.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * - 2003/01/20: Robert Schwebel */ +#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ +#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ + +#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ +#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ +#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ + +#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ +#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ +#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ + +#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ +#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ +#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ + +#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ +#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ +#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ + +#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ +#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ +#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ + +#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ +#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ +#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ + +#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ +#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ +#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ +#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ +#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ +#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */ + +/* More handy macros. The argument is a literal GPIO number. */ + +#define GPIO_bit(x) (1 << ((x) & 0x1f)) + +#ifdef CONFIG_PXA27X + +/* Interrupt Controller */ + +#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ +#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ +#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ +#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ +#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ + +#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) +#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) +#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) +#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) +#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) +#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) +#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) +#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) + +#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3) +#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3) +#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3) +#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3) +#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3) +#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3) +#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3) +#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \ + ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)) +#else + +#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) +#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) +#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) +#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) +#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) +#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) +#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) +#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) + +#endif + +/* GPIO alternate function assignments */ + +#define GPIO1_RST 1 /* reset */ +#define GPIO6_MMCCLK 6 /* MMC Clock */ +#define GPIO8_48MHz 7 /* 48 MHz clock output */ +#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ +#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ +#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ +#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ +#define GPIO12_32KHz 12 /* 32 kHz out */ +#define GPIO13_MBGNT 13 /* memory controller grant */ +#define GPIO14_MBREQ 14 /* alternate bus master request */ +#define GPIO15_nCS_1 15 /* chip select 1 */ +#define GPIO16_PWM0 16 /* PWM0 output */ +#define GPIO17_PWM1 17 /* PWM1 output */ +#define GPIO18_RDY 18 /* Ext. Bus Ready */ +#define GPIO19_DREQ1 19 /* External DMA Request */ +#define GPIO20_DREQ0 20 /* External DMA Request */ +#define GPIO23_SCLK 23 /* SSP clock */ +#define GPIO24_SFRM 24 /* SSP Frame */ +#define GPIO25_STXD 25 /* SSP transmit */ +#define GPIO26_SRXD 26 /* SSP receive */ +#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ +#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ +#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ +#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ +#define GPIO31_SYNC 31 /* AC97/I2S sync */ +#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ +#define GPIO33_nCS_5 33 /* chip select 5 */ +#define GPIO34_FFRXD 34 /* FFUART receive */ +#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ +#define GPIO35_FFCTS 35 /* FFUART Clear to send */ +#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ +#define GPIO37_FFDSR 37 /* FFUART data set ready */ +#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ +#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ +#define GPIO39_FFTXD 39 /* FFUART transmit data */ +#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ +#define GPIO41_FFRTS 41 /* FFUART request to send */ +#define GPIO42_BTRXD 42 /* BTUART receive data */ +#define GPIO43_BTTXD 43 /* BTUART transmit data */ +#define GPIO44_BTCTS 44 /* BTUART clear to send */ +#define GPIO45_BTRTS 45 /* BTUART request to send */ +#define GPIO46_ICPRXD 46 /* ICP receive data */ +#define GPIO46_STRXD 46 /* STD_UART receive data */ +#define GPIO47_ICPTXD 47 /* ICP transmit data */ +#define GPIO47_STTXD 47 /* STD_UART transmit data */ +#define GPIO48_nPOE 48 /* Output Enable for Card Space */ +#define GPIO49_nPWE 49 /* Write Enable for Card Space */ +#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ +#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ +#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ +#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ +#define GPIO53_MMCCLK 53 /* MMC Clock */ +#define GPIO54_MMCCLK 54 /* MMC Clock */ +#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ +#define GPIO55_nPREG 55 /* Card Address bit 26 */ +#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ +#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ +#define GPIO58_LDD_0 58 /* LCD data pin 0 */ +#define GPIO59_LDD_1 59 /* LCD data pin 1 */ +#define GPIO60_LDD_2 60 /* LCD data pin 2 */ +#define GPIO61_LDD_3 61 /* LCD data pin 3 */ +#define GPIO62_LDD_4 62 /* LCD data pin 4 */ +#define GPIO63_LDD_5 63 /* LCD data pin 5 */ +#define GPIO64_LDD_6 64 /* LCD data pin 6 */ +#define GPIO65_LDD_7 65 /* LCD data pin 7 */ +#define GPIO66_LDD_8 66 /* LCD data pin 8 */ +#define GPIO66_MBREQ 66 /* alternate bus master req */ +#define GPIO67_LDD_9 67 /* LCD data pin 9 */ +#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ +#define GPIO68_LDD_10 68 /* LCD data pin 10 */ +#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ +#define GPIO69_LDD_11 69 /* LCD data pin 11 */ +#define GPIO69_MMCCLK 69 /* MMC_CLK */ +#define GPIO70_LDD_12 70 /* LCD data pin 12 */ +#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ +#define GPIO71_LDD_13 71 /* LCD data pin 13 */ +#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ +#define GPIO72_LDD_14 72 /* LCD data pin 14 */ +#define GPIO72_32kHz 72 /* 32 kHz clock */ +#define GPIO73_LDD_15 73 /* LCD data pin 15 */ +#define GPIO73_MBGNT 73 /* Memory controller grant */ +#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ +#define GPIO75_LCD_LCLK 75 /* LCD line clock */ +#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ +#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ +#define GPIO78_nCS_2 78 /* chip select 2 */ +#define GPIO79_nCS_3 79 /* chip select 3 */ +#define GPIO80_nCS_4 80 /* chip select 4 */ + +/* GPIO alternate function mode & direction */ + +#define GPIO_IN 0x000 +#define GPIO_OUT 0x080 +#define GPIO_ALT_FN_1_IN 0x100 +#define GPIO_ALT_FN_1_OUT 0x180 +#define GPIO_ALT_FN_2_IN 0x200 +#define GPIO_ALT_FN_2_OUT 0x280 +#define GPIO_ALT_FN_3_IN 0x300 +#define GPIO_ALT_FN_3_OUT 0x380 +#define GPIO_MD_MASK_NR 0x07f +#define GPIO_MD_MASK_DIR 0x080 +#define GPIO_MD_MASK_FN 0x300 + +#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) +#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) +#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT) +#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) +#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) +#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) +#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) +#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) +#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) +#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) +#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) +#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) +#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) +#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) +#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) +#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) +#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT) +#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) +#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) +#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) +#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) +#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) +#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN) +#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) +#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) +#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) +#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) +#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) +#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) +#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) +#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) +#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) +#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) +#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) +#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) +#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) +#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) +#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) +#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) +#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) +#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) +#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) +#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) +#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) +#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) +#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) +#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) +#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) +#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) +#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) +#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) +#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) +#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) +#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) +#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) +#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) +#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) +#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) +#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) +#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) +#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) +#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) +#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) +#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) +#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) +#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) +#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) +#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) +#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) +#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) +#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) +#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) +#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) +#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) +#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) +#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) +#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) +#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) +#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) +#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) +#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) +#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) +#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) +#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) +#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) +#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) +#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) +#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) +#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) +#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) +#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) +#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) + +#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) +#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) + +/* + * Power Manager + */ +#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ +#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ +#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ +#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ +#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ +#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ +#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ +#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ +#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ +#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ +#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ +#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ +#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ + +#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ +#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ +#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ +#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ +#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ +#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ +#define PCMD(x) __REG(0x40F00080 + x*4) +#define PCMD0 __REG(0x40F00080 + 0 * 4) +#define PCMD1 __REG(0x40F00080 + 1 * 4) +#define PCMD2 __REG(0x40F00080 + 2 * 4) +#define PCMD3 __REG(0x40F00080 + 3 * 4) +#define PCMD4 __REG(0x40F00080 + 4 * 4) +#define PCMD5 __REG(0x40F00080 + 5 * 4) +#define PCMD6 __REG(0x40F00080 + 6 * 4) +#define PCMD7 __REG(0x40F00080 + 7 * 4) +#define PCMD8 __REG(0x40F00080 + 8 * 4) +#define PCMD9 __REG(0x40F00080 + 9 * 4) +#define PCMD10 __REG(0x40F00080 + 10 * 4) +#define PCMD11 __REG(0x40F00080 + 11 * 4) +#define PCMD12 __REG(0x40F00080 + 12 * 4) +#define PCMD13 __REG(0x40F00080 + 13 * 4) +#define PCMD14 __REG(0x40F00080 + 14 * 4) +#define PCMD15 __REG(0x40F00080 + 15 * 4) +#define PCMD16 __REG(0x40F00080 + 16 * 4) +#define PCMD17 __REG(0x40F00080 + 17 * 4) +#define PCMD18 __REG(0x40F00080 + 18 * 4) +#define PCMD19 __REG(0x40F00080 + 19 * 4) +#define PCMD20 __REG(0x40F00080 + 20 * 4) +#define PCMD21 __REG(0x40F00080 + 21 * 4) +#define PCMD22 __REG(0x40F00080 + 22 * 4) +#define PCMD23 __REG(0x40F00080 + 23 * 4) +#define PCMD24 __REG(0x40F00080 + 24 * 4) +#define PCMD25 __REG(0x40F00080 + 25 * 4) +#define PCMD26 __REG(0x40F00080 + 26 * 4) +#define PCMD27 __REG(0x40F00080 + 27 * 4) +#define PCMD28 __REG(0x40F00080 + 28 * 4) +#define PCMD29 __REG(0x40F00080 + 29 * 4) +#define PCMD30 __REG(0x40F00080 + 30 * 4) +#define PCMD31 __REG(0x40F00080 + 31 * 4) + +#define PCMD_MBC (1<<12) +#define PCMD_DCE (1<<11) +#define PCMD_LC (1<<10) +/* FIXME: PCMD_SQC need be checked. */ +#define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */ + /* bit 9 should be 0 all day. */ +#define PVCR_VCSA (0x1<<14) +#define PVCR_CommandDelay (0xf80) +/* define MACRO for Power Manager General Configuration Register (PCFR) */ +#define PCFR_FVC (0x1 << 10) +#define PCFR_PI2C_EN (0x1 << 6) + +#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ +#define PSSR_RDH (1 << 5) /* Read Disable Hold */ +#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ +#define PSSR_VFS (1 << 2) /* VDD Fault Status */ +#define PSSR_BFS (1 << 1) /* Battery Fault Status */ +#define PSSR_SSS (1 << 0) /* Software Sleep Status */ + +#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ +#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ +#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ +#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ + +#define RCSR_GPR (1 << 3) /* GPIO Reset */ +#define RCSR_SMR (1 << 2) /* Sleep Mode */ +#define RCSR_WDR (1 << 1) /* Watchdog Reset */ +#define RCSR_HWR (1 << 0) /* Hardware Reset */ + +/* + * SSP Serial Port Registers + */ +#define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */ +#define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */ +#define SSSR __REG(0x41000008) /* SSP Status Register */ +#define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */ +#define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ + +/* + * MultiMediaCard (MMC) controller + */ +#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ +#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ +#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ +#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ +#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ +#define MMC_RESTO __REG(0x41100014) /* Expected response time out */ +#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ +#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ +#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ +#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ +#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ +#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ +#define MMC_CMD __REG(0x41100030) /* Index of current command */ +#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ +#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ +#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ +#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ +#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ + +/* + * Core Clock + */ +#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ +#define CKEN __REG(0x41300004) /* Clock Enable Register */ +#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ + +#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#if !defined(CONFIG_PXA27X) +#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ +#endif +#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ + +#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ +#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ +#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ +#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ +#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ +#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ +#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ +#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ +#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ +#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ +#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ +#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ +#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ +#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ +#if defined(CONFIG_PXA27X) +#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ +#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ +#endif +#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ +#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ +#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ +#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ +#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ +#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ +#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ +#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ + +#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ +#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ + +#if !defined(CONFIG_PXA27X) +#define CCCR_L09 (0x1F) +#define CCCR_L27 (0x1) +#define CCCR_L32 (0x2) +#define CCCR_L36 (0x3) +#define CCCR_L40 (0x4) +#define CCCR_L45 (0x5) + +#define CCCR_M1 (0x1 << 5) +#define CCCR_M2 (0x2 << 5) +#define CCCR_M4 (0x3 << 5) + +#define CCCR_N10 (0x2 << 7) +#define CCCR_N15 (0x3 << 7) +#define CCCR_N20 (0x4 << 7) +#define CCCR_N25 (0x5 << 7) +#define CCCR_N30 (0x6 << 7) +#endif + +/* + * LCD + */ +#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */ +#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ +#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ +#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ +#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ +#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ +#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */ +#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */ +#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */ +#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */ +#define TMEDCR __REG(0x44000044) /* TMED Control Register */ + +#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ +#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ +#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ +#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */ +#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */ +#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */ +#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */ +#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */ + +#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ +#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ +#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ +#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ +#define LCCR0_SFM (1 << 4) /* Start of frame mask */ +#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ +#define LCCR0_EFM (1 << 6) /* End of Frame mask */ +#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ +#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ +#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ +#define LCCR0_DIS (1 << 10) /* LCD Disable */ +#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ +#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ +#define LCCR0_PDD_S 12 +#define LCCR0_BM (1 << 20) /* Branch mask */ +#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ +#if defined(CONFIG_PXA27X) +#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ +#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ +#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ +#endif + +#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ +#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ + (((Pixel) - 1) << FShft (LCCR1_PPL)) + +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ +#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ + /* pulse Width [1..64 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_HSW)) + +#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ + /* count - 1 [Tpix] */ +#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_ELW)) + +#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ + /* Wait count - 1 [Tpix] */ +#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_BLW)) + + +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ +#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ + (((Line) - 1) << FShft (LCCR2_LPP)) + +#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ + /* Width - 1 [Tln] (L_FCLK) */ +#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ + /* Width [1..64 Tln] */ \ + (((Tln) - 1) << FShft (LCCR2_VSW)) + +#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ + /* count [Tln] */ +#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_EFW)) + +#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ + /* Wait count [Tln] */ +#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_BFW)) + +#if 0 +#define LCCR3_PCD (0xff) /* Pixel clock divisor */ +#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ +#define LCCR3_ACB_S 8 +#endif + +#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ +#define LCCR3_API_S 16 +#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ +#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ +#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ +#define LCCR3_OEP (1 << 23) /* output enable polarity */ +#if 0 +#define LCCR3_BPP (7 << 24) /* bits per pixel */ +#define LCCR3_BPP_S 24 +#endif +#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ + +#define LCCR3_PDFOR_0 (0 << 30) +#define LCCR3_PDFOR_1 (1 << 30) +#define LCCR3_PDFOR_2 (2 << 30) +#define LCCR3_PDFOR_3 (3 << 30) + + +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ +#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ + (((Div) << FShft (LCCR3_PCD))) + + +#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ +#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ + ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26))) + +#define LCCR3_ACB Fld (8, 8) /* AC Bias */ +#define LCCR3_Acb(Acb) /* BAC Bias */ \ + (((Acb) << FShft (LCCR3_ACB))) + +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ + /* pulse active High */ +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ + +#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ + /* active High */ +#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ + /* active Low */ + +#define LCSR0_LDD (1 << 0) /* LCD Disable Done */ +#define LCSR0_SOF (1 << 1) /* Start of frame */ +#define LCSR0_BER (1 << 2) /* Bus error */ +#define LCSR0_ABC (1 << 3) /* AC Bias count */ +#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */ +#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */ +#define LCSR0_OU (1 << 6) /* output FIFO underrun */ +#define LCSR0_QD (1 << 7) /* quick disable */ +#define LCSR0_EOF0 (1 << 8) /* end of frame */ +#define LCSR0_BS (1 << 9) /* branch status */ +#define LCSR0_SINT (1 << 10) /* subsequent interrupt */ + +#define LCSR1_SOF1 (1 << 0) +#define LCSR1_SOF2 (1 << 1) +#define LCSR1_SOF3 (1 << 2) +#define LCSR1_SOF4 (1 << 3) +#define LCSR1_SOF5 (1 << 4) +#define LCSR1_SOF6 (1 << 5) + +#define LCSR1_EOF1 (1 << 8) +#define LCSR1_EOF2 (1 << 9) +#define LCSR1_EOF3 (1 << 10) +#define LCSR1_EOF4 (1 << 11) +#define LCSR1_EOF5 (1 << 12) +#define LCSR1_EOF6 (1 << 13) + +#define LCSR1_BS1 (1 << 16) +#define LCSR1_BS2 (1 << 17) +#define LCSR1_BS3 (1 << 18) +#define LCSR1_BS4 (1 << 19) +#define LCSR1_BS5 (1 << 20) +#define LCSR1_BS6 (1 << 21) + +#define LCSR1_IU2 (1 << 25) +#define LCSR1_IU3 (1 << 26) +#define LCSR1_IU4 (1 << 27) +#define LCSR1_IU5 (1 << 28) +#define LCSR1_IU6 (1 << 29) + +#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ +#if defined(CONFIG_PXA27X) +#define LDCMD_SOFINT (1 << 22) +#define LDCMD_EOFINT (1 << 21) +#endif + +/* + * Memory controller + */ +#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */ +#define MDCNFG_OFFSET 0x0 +#define MDREFR_OFFSET 0x4 +#define MSC0_OFFSET 0x8 +#define MSC1_OFFSET 0xC +#define MSC2_OFFSET 0x10 +#define MECR_OFFSET 0x14 +#define SXLCR_OFFSET 0x18 +#define SXCNFG_OFFSET 0x1C +#define FLYCNFG_OFFSET 0x20 +#define SXMRS_OFFSET 0x24 +#define MCMEM0_OFFSET 0x28 +#define MCMEM1_OFFSET 0x2C +#define MCATT0_OFFSET 0x30 +#define MCATT1_OFFSET 0x34 +#define MCIO0_OFFSET 0x38 +#define MCIO1_OFFSET 0x3C +#define MDMRS_OFFSET 0x40 + +#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ +#define MDCNFG_DE0 0x00000001 +#define MDCNFG_DE1 0x00000002 +#define MDCNFG_DE2 0x00010000 +#define MDCNFG_DE3 0x00020000 +#define MDCNFG_DWID0 0x00000004 + +#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ +#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ +#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ +#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ +#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ +#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ +#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ + +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ + +#if defined(CONFIG_PXA27X) + +#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ + +#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ +#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ +#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ +#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ +#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ +#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ +#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ +#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ +#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ + +/* Interrupt Controller */ + +#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ +#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ +#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ +#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ +#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ + +/* General Purpose I/O */ + +#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ +#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ +#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ +#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ +#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ +#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */ +#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ +#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ +#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ + +/* Core Clock */ + +#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ + +#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ +#define CKEN22_MEMC (1 << 22) /* Memory Controler */ +#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ +#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ +#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ +#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ +#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ +#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ +#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ +#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ + +/* Memory controller */ + +#define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */ + +/* LCD registers */ +#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */ +#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */ +#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ +#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ +#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */ +#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */ +#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */ +#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */ +#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */ +#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */ +#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */ +#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */ +#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */ +#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */ +#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */ +#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */ +#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */ +#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */ +#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */ +#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */ +#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */ +#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */ +#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */ + +#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */ +#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */ +#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */ +#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */ +#define CCR __REG(0x44000090) /* Cursor Control Register */ + +#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */ +#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */ + +#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ +#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ + +#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */ +#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */ +#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */ +#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */ +#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */ +#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */ + +#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */ +#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */ +#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */ +#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */ +#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */ +#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */ + +#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */ +#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */ +#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */ +#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */ +#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */ +#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */ + +#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */ +#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */ +#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */ +#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */ +#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */ +#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */ + +#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */ +#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */ +#define CCR_CEN (1<<31) /* Enable bit for Cursor */ + +/* Keypad controller */ + +#define KPC __REG(0x41500000) /* Keypad Interface Control register */ +#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */ +#define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */ +#define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */ +#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */ +#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ +#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ +#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ +#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ +#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */ + +#define KPC_AS (0x1 << 30) /* Automatic Scan bit */ +#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ +#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ +#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ +#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ +#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ +#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ +#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ +#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ +#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ +#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ +#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ +#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ +#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ +#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */ +#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ +#define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */ +#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ +#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ + +#define KPDK_DKP (0x1 << 31) +#define KPDK_DK7 (0x1 << 7) +#define KPDK_DK6 (0x1 << 6) +#define KPDK_DK5 (0x1 << 5) +#define KPDK_DK4 (0x1 << 4) +#define KPDK_DK3 (0x1 << 3) +#define KPDK_DK2 (0x1 << 2) +#define KPDK_DK1 (0x1 << 1) +#define KPDK_DK0 (0x1 << 0) + +#define KPREC_OF1 (0x1 << 31) +#define kPREC_UF1 (0x1 << 30) +#define KPREC_OF0 (0x1 << 15) +#define KPREC_UF0 (0x1 << 14) + +#define KPMK_MKP (0x1 << 31) +#define KPAS_SO (0x1 << 31) +#define KPASMKPx_SO (0x1 << 31) + +#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ +#define PSLR __REG(0x40F00034) +#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */ +#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */ +#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */ +#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */ +#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */ +#define OSMR4 __REG(0x40A00080) /* */ +#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ +#define OMCR4 __REG(0x40A000C0) /* */ + +#endif /* CONFIG_PXA27X */ + +#endif /* _PXA_REGS_H_ */ diff --git a/include/asm-arm/arch-s3c24x0/memory.h b/include/asm-arm/arch-s3c24x0/memory.h new file mode 100644 index 0000000..333f218 --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/memory.h @@ -0,0 +1,162 @@ +/* + * linux/include/asm-arm/arch-s3c2400/memory.h by gj@denx.de + * based on + * linux/include/asm-arm/arch-sa1100/memory.h + * + * Copyright (c) 1999 Nicolas Pitre + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + + +/* + * Task size: 3GB + */ +#define TASK_SIZE (0xc0000000UL) +#define TASK_SIZE_26 (0x04000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Page offset: 3GB + */ +#define PAGE_OFFSET (0xc0000000UL) + +/* + * Physical DRAM offset is 0x0c000000 on the S3C2400 + */ +#define PHYS_OFFSET (0x0c000000UL) + +#include + + +/* Modified for S3C2400, by chc, 20010509 */ +#define RAM_IN_BANK_0 32*1024*1024 +#define RAM_IN_BANK_1 0 +#define RAM_IN_BANK_2 0 +#define RAM_IN_BANK_3 0 + +#define MEM_SIZE (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3) + + +/* translation macros */ +#define __virt_to_phys__is_a_macro +#define __phys_to_virt__is_a_macro + +#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) + +#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 ) +#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET ) + +#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \ + (RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) + +/* Two identical banks */ +#define __virt_to_phys(x) \ + ( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \ + ((x) - PAGE_OFFSET + _DRAMBnk0) : \ + ((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) ) +#define __phys_to_virt(x) \ + ( ((x)&0x07ffffff) + \ + (((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) ) +#else + +/* It's more efficient for all other cases to use the function call */ +#undef __virt_to_phys__is_a_macro +#undef __phys_to_virt__is_a_macro +extern unsigned long __virt_to_phys(unsigned long vpage); +extern unsigned long __phys_to_virt(unsigned long ppage); + +#endif + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + * + * On the SA1100, bus addresses are equivalent to physical addresses. + */ +#define __virt_to_bus__is_a_macro +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt__is_a_macro +#define __bus_to_virt(x) __phys_to_virt(x) + + +#ifdef CONFIG_DISCONTIGMEM +#error "CONFIG_DISCONTIGMEM will not work on S3C2400" +/* + * Because of the wide memory address space between physical RAM banks on the + * SA1100, it's much more convenient to use Linux's NUMA support to implement + * our memory map representation. Assuming all memory nodes have equal access + * characteristics, we then have generic discontiguous memory support. + * + * Of course, all this isn't mandatory for SA1100 implementations with only + * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. + * + * The nodes are matched with the physical memory bank addresses which are + * incidentally the same as virtual addresses. + * + * node 0: 0xc0000000 - 0xc7ffffff + * node 1: 0xc8000000 - 0xcfffffff + * node 2: 0xd0000000 - 0xd7ffffff + * node 3: 0xd8000000 - 0xdfffffff + */ + +#define NR_NODES 4 + +/* + * Given a kernel address, find the home node of the underlying memory. + */ +#define KVADDR_TO_NID(addr) \ + (((unsigned long)(addr) - 0xc0000000) >> 27) + +/* + * Given a physical address, convert it to a node id. + */ +#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr)) + +/* + * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory + * and returns the mem_map of that node. + */ +#define ADDR_TO_MAPBASE(kaddr) \ + NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) + +/* + * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory + * and returns the index corresponding to the appropriate page in the + * node's mem_map. + */ +#define LOCAL_MAP_NR(kvaddr) \ + (((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT) + +/* + * Given a kaddr, virt_to_page returns a pointer to the corresponding + * mem_map entry. + */ +#define virt_to_page(kaddr) \ + (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) + +/* + * VALID_PAGE returns a non-zero value if given page pointer is valid. + * This assumes all node's mem_maps are stored within the node they refer to. + */ +#define VALID_PAGE(page) \ +({ unsigned int node = KVADDR_TO_NID(page); \ + ( (node < NR_NODES) && \ + ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \ +}) + +#else + +#define PHYS_TO_NID(addr) (0) + +#endif +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/include/asm-arm/arch-s3c44b0/hardware.h b/include/asm-arm/arch-s3c44b0/hardware.h new file mode 100644 index 0000000..146e265 --- /dev/null +++ b/include/asm-arm/arch-s3c44b0/hardware.h @@ -0,0 +1,281 @@ +/********************************************************/ +/* */ +/* Samsung S3C44B0 */ +/* tpu */ +/* */ +/********************************************************/ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#define REGBASE 0x01c00000 +#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr)) +#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr)) +#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr)) + + +/*****************************/ +/* CPU Wrapper Registers */ +/*****************************/ + +#define SYSCFG REGL(0x000000) +#define NCACHBE0 REGL(0x000004) +#define NCACHBE1 REGL(0x000008) +#define SBUSCON REGL(0x040000) + +/************************************/ +/* Memory Controller Registers */ +/************************************/ + +#define BWSCON REGL(0x080000) +#define BANKCON0 REGL(0x080004) +#define BANKCON1 REGL(0x080008) +#define BANKCON2 REGL(0x08000c) +#define BANKCON3 REGL(0x080010) +#define BANKCON4 REGL(0x080014) +#define BANKCON5 REGL(0x080018) +#define BANKCON6 REGL(0x08001c) +#define BANKCON7 REGL(0x080020) +#define REFRESH REGL(0x080024) +#define BANKSIZE REGL(0x080028) +#define MRSRB6 REGL(0x08002c) +#define MRSRB7 REGL(0x080030) + +/*********************/ +/* UART Registers */ +/*********************/ + +#define ULCON0 REGL(0x100000) +#define ULCON1 REGL(0x104000) +#define UCON0 REGL(0x100004) +#define UCON1 REGL(0x104004) +#define UFCON0 REGL(0x100008) +#define UFCON1 REGL(0x104008) +#define UMCON0 REGL(0x10000c) +#define UMCON1 REGL(0x10400c) +#define UTRSTAT0 REGL(0x100010) +#define UTRSTAT1 REGL(0x104010) +#define UERSTAT0 REGL(0x100014) +#define UERSTAT1 REGL(0x104014) +#define UFSTAT0 REGL(0x100018) +#define UFSTAT1 REGL(0x104018) +#define UMSTAT0 REGL(0x10001c) +#define UMSTAT1 REGL(0x10401c) +#define UTXH0 REGB(0x100020) +#define UTXH1 REGB(0x104020) +#define URXH0 REGB(0x100024) +#define URXH1 REGB(0x104024) +#define UBRDIV0 REGL(0x100028) +#define UBRDIV1 REGL(0x104028) + +/*******************/ +/* SIO Registers */ +/*******************/ + +#define SIOCON REGL(0x114000) +#define SIODAT REGL(0x114004) +#define SBRDR REGL(0x114008) +#define ITVCNT REGL(0x11400c) +#define DCNTZ REGL(0x114010) + +/********************/ +/* IIS Registers */ +/********************/ + +#define IISCON REGL(0x118000) +#define IISMOD REGL(0x118004) +#define IISPSR REGL(0x118008) +#define IISFIFCON REGL(0x11800c) +#define IISFIF REGW(0x118010) + +/**************************/ +/* I/O Ports Registers */ +/**************************/ + +#define PCONA REGL(0x120000) +#define PDATA REGL(0x120004) +#define PCONB REGL(0x120008) +#define PDATB REGL(0x12000c) +#define PCONC REGL(0x120010) +#define PDATC REGL(0x120014) +#define PUPC REGL(0x120018) +#define PCOND REGL(0x12001c) +#define PDATD REGL(0x120020) +#define PUPD REGL(0x120024) +#define PCONE REGL(0x120028) +#define PDATE REGL(0x12002c) +#define PUPE REGL(0x120030) +#define PCONF REGL(0x120034) +#define PDATF REGL(0x120038) +#define PUPF REGL(0x12003c) +#define PCONG REGL(0x120040) +#define PDATG REGL(0x120044) +#define PUPG REGL(0x120048) +#define SPUCR REGL(0x12004c) +#define EXTINT REGL(0x120050) +#define EXTINTPND REGL(0x120054) + +/*********************************/ +/* WatchDog Timers Registers */ +/*********************************/ + +#define WTCON REGL(0x130000) +#define WTDAT REGL(0x130004) +#define WTCNT REGL(0x130008) + +/*********************************/ +/* A/D Converter Registers */ +/*********************************/ + +#define ADCCON REGL(0x140000) +#define ADCPSR REGL(0x140004) +#define ADCDAT REGL(0x140008) + +/***************************/ +/* PWM Timer Registers */ +/***************************/ + +#define TCFG0 REGL(0x150000) +#define TCFG1 REGL(0x150004) +#define TCON REGL(0x150008) +#define TCNTB0 REGL(0x15000c) +#define TCMPB0 REGL(0x150010) +#define TCNTO0 REGL(0x150014) +#define TCNTB1 REGL(0x150018) +#define TCMPB1 REGL(0x15001c) +#define TCNTO1 REGL(0x150020) +#define TCNTB2 REGL(0x150024) +#define TCMPB2 REGL(0x150028) +#define TCNTO2 REGL(0x15002c) +#define TCNTB3 REGL(0x150030) +#define TCMPB3 REGL(0x150034) +#define TCNTO3 REGL(0x150038) +#define TCNTB4 REGL(0x15003c) +#define TCMPB4 REGL(0x150040) +#define TCNTO4 REGL(0x150044) +#define TCNTB5 REGL(0x150048) +#define TCNTO5 REGL(0x15004c) + +/*********************/ +/* IIC Registers */ +/*********************/ + +#define IICCON REGL(0x160000) +#define IICSTAT REGL(0x160004) +#define IICADD REGL(0x160008) +#define IICDS REGL(0x16000c) + +/*********************/ +/* RTC Registers */ +/*********************/ + +#define RTCCON REGB(0x170040) +#define RTCALM REGB(0x170050) +#define ALMSEC REGB(0x170054) +#define ALMMIN REGB(0x170058) +#define ALMHOUR REGB(0x17005c) +#define ALMDAY REGB(0x170060) +#define ALMMON REGB(0x170064) +#define ALMYEAR REGB(0x170068) +#define RTCRST REGB(0x17006c) +#define BCDSEC REGB(0x170070) +#define BCDMIN REGB(0x170074) +#define BCDHOUR REGB(0x170078) +#define BCDDAY REGB(0x17007c) +#define BCDDATE REGB(0x170080) +#define BCDMON REGB(0x170084) +#define BCDYEAR REGB(0x170088) +#define TICINT REGB(0x17008c) + +/*********************************/ +/* Clock & Power Registers */ +/*********************************/ + +#define PLLCON REGL(0x180000) +#define CLKCON REGL(0x180004) +#define CLKSLOW REGL(0x180008) +#define LOCKTIME REGL(0x18000c) + +/**************************************/ +/* Interrupt Controller Registers */ +/**************************************/ + +#define INTCON REGL(0x200000) +#define INTPND REGL(0x200004) +#define INTMOD REGL(0x200008) +#define INTMSK REGL(0x20000c) +#define I_PSLV REGL(0x200010) +#define I_PMST REGL(0x200014) +#define I_CSLV REGL(0x200018) +#define I_CMST REGL(0x20001c) +#define I_ISPR REGL(0x200020) +#define I_ISPC REGL(0x200024) +#define F_ISPR REGL(0x200038) +#define F_ISPC REGL(0x20003c) + +/********************************/ +/* LCD Controller Registers */ +/********************************/ + +#define LCDCON1 REGL(0x300000) +#define LCDCON2 REGL(0x300004) +#define LCDSADDR1 REGL(0x300008) +#define LCDSADDR2 REGL(0x30000c) +#define LCDSADDR3 REGL(0x300010) +#define REDLUT REGL(0x300014) +#define GREENLUT REGL(0x300018) +#define BLUELUT REGL(0x30001c) +#define DP1_2 REGL(0x300020) +#define DP4_7 REGL(0x300024) +#define DP3_5 REGL(0x300028) +#define DP2_3 REGL(0x30002c) +#define DP5_7 REGL(0x300030) +#define DP3_4 REGL(0x300034) +#define DP4_5 REGL(0x300038) +#define DP6_7 REGL(0x30003c) +#define LCDCON3 REGL(0x300040) +#define DITHMODE REGL(0x300044) + +/*********************/ +/* DMA Registers */ +/*********************/ + +#define ZDCON0 REGL(0x280000) +#define ZDISRC0 REGL(0x280004) +#define ZDIDES0 REGL(0x280008) +#define ZDICNT0 REGL(0x28000c) +#define ZDCSRC0 REGL(0x280010) +#define ZDCDES0 REGL(0x280014) +#define ZDCCNT0 REGL(0x280018) + +#define ZDCON1 REGL(0x280020) +#define ZDISRC1 REGL(0x280024) +#define ZDIDES1 REGL(0x280028) +#define ZDICNT1 REGL(0x28002c) +#define ZDCSRC1 REGL(0x280030) +#define ZDCDES1 REGL(0x280034) +#define ZDCCNT1 REGL(0x280038) + +#define BDCON0 REGL(0x380000) +#define BDISRC0 REGL(0x380004) +#define BDIDES0 REGL(0x380008) +#define BDICNT0 REGL(0x38000c) +#define BDCSRC0 REGL(0x380010) +#define BDCDES0 REGL(0x380014) +#define BDCCNT0 REGL(0x380018) + +#define BDCON1 REGL(0x380020) +#define BDISRC1 REGL(0x380024) +#define BDIDES1 REGL(0x380028) +#define BDICNT1 REGL(0x38002c) +#define BDCSRC1 REGL(0x380030) +#define BDCDES1 REGL(0x380034) +#define BDCCNT1 REGL(0x380038) + + +#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n)) +#define INT_ENABLE(n) INTMSK &= ~(1<<(n)) +#define INT_DISABLE(n) INTMSK |= (1<<(n)) + +#define HARD_RESET_NOW() + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h new file mode 100644 index 0000000..2ac5ea2 --- /dev/null +++ b/include/asm-arm/arch-sa1100/bitfield.h @@ -0,0 +1,112 @@ +/* + * FILE bitfield.h + * + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) + * Language C or ARM Assembly + * Purpose Definition of macros to operate on bit fields. + */ + + +#ifndef __BITFIELD_H +#define __BITFIELD_H + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long) (Data)) +#else +#define UData(Data) (Data) +#endif + + +/* + * MACRO: Fld + * + * Purpose + * The macro "Fld" encodes a bit field, given its size and its shift value + * with respect to bit 0. + * + * Note + * A more intuitive way to encode bit fields would have been to use their + * mask. However, extracting size and shift value information from a bit + * field's mask is cumbersome and might break the assembler (255-character + * line-size limit). + * + * Input + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. + * + * Output + * Fld Encoded bit field. + */ + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + + +/* + * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit + * + * Purpose + * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return + * the size, shift value, mask, aligned mask, and first bit of a + * bit field. + * + * Input + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. + */ + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) +#define F1stBit(Field) (UData (1) << FShft (Field)) + + +/* + * MACRO: FInsrt + * + * Purpose + * The macro "FInsrt" inserts a value into a bit field by shifting the + * former appropriately. + * + * Input + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FInsrt Bit-field value positioned appropriately. + */ + +#define FInsrt(Value, Field) \ + (UData (Value) << FShft (Field)) + + +/* + * MACRO: FExtr + * + * Purpose + * The macro "FExtr" extracts the value of a bit field by masking and + * shifting it appropriately. + * + * Input + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FExtr Bit-field value. + */ + +#define FExtr(Data, Field) \ + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) + + +#endif /* __BITFIELD_H */ diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h new file mode 100644 index 0000000..ba9e4b7 --- /dev/null +++ b/include/asm-arm/atomic.h @@ -0,0 +1,113 @@ +/* + * linux/include/asm-arm/atomic.h + * + * Copyright (c) 1996 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 13-04-1997 RMK Made functions atomic! + * 07-12-1997 RMK Upgraded for v2.1. + * 26-08-1998 PJB Added #ifdef __KERNEL__ + */ +#ifndef __ASM_ARM_ATOMIC_H +#define __ASM_ARM_ATOMIC_H + +#include + +#ifdef CONFIG_SMP +#error SMP not supported +#endif + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) { (i) } + +#ifdef __KERNEL__ +#include + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v,i) (((v)->counter) = (i)) + +static inline void atomic_add(int i, volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +static inline void atomic_inc(volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += 1; + local_irq_restore(flags); +} + +static inline void atomic_dec(volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= 1; + local_irq_restore(flags); +} + +static inline int atomic_dec_and_test(volatile atomic_t *v) +{ + unsigned long flags; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val -= 1; + local_irq_restore(flags); + + return val == 0; +} + +static inline int atomic_add_negative(int i, volatile atomic_t *v) +{ + unsigned long flags; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val += i; + local_irq_restore(flags); + + return val < 0; +} + +static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) +{ + unsigned long flags; + + local_irq_save(flags); + *addr &= ~mask; + local_irq_restore(flags); +} + +/* Atomic operations are already serializing on ARM */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#endif +#endif diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h new file mode 100644 index 0000000..4b8bab2 --- /dev/null +++ b/include/asm-arm/bitops.h @@ -0,0 +1,144 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + * + * Please note that the code in this file should never be included + * from user space. Many of these are not implemented in assembler + * since they would be too costly. Also, they require priviledged + * instructions (which are not available from user mode) to ensure + * that they are atomic. + */ + +#ifndef __ASM_ARM_BITOPS_H +#define __ASM_ARM_BITOPS_H + +#ifdef __KERNEL__ + +#define smp_mb__before_clear_bit() do { } while (0) +#define smp_mb__after_clear_bit() do { } while (0) + +/* + * Function prototypes to keep gcc -Wall happy. + */ +extern void set_bit(int nr, volatile void * addr); + +static inline void __set_bit(int nr, volatile void *addr) +{ + ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); +} + +extern void clear_bit(int nr, volatile void * addr); + +static inline void __clear_bit(int nr, volatile void *addr) +{ + ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); +} + +extern void change_bit(int nr, volatile void * addr); + +static inline void __change_bit(int nr, volatile void *addr) +{ + ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); +} + +extern int test_and_set_bit(int nr, volatile void * addr); + +static inline int __test_and_set_bit(int nr, volatile void *addr) +{ + unsigned int mask = 1 << (nr & 7); + unsigned int oldval; + + oldval = ((unsigned char *) addr)[nr >> 3]; + ((unsigned char *) addr)[nr >> 3] = oldval | mask; + return oldval & mask; +} + +extern int test_and_clear_bit(int nr, volatile void * addr); + +static inline int __test_and_clear_bit(int nr, volatile void *addr) +{ + unsigned int mask = 1 << (nr & 7); + unsigned int oldval; + + oldval = ((unsigned char *) addr)[nr >> 3]; + ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; + return oldval & mask; +} + +extern int test_and_change_bit(int nr, volatile void * addr); + +static inline int __test_and_change_bit(int nr, volatile void *addr) +{ + unsigned int mask = 1 << (nr & 7); + unsigned int oldval; + + oldval = ((unsigned char *) addr)[nr >> 3]; + ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; + return oldval & mask; +} + +extern int find_first_zero_bit(void * addr, unsigned size); +extern int find_next_zero_bit(void * addr, int size, int offset); + +/* + * This routine doesn't need to be atomic. + */ +static inline int test_bit(int nr, const void * addr) +{ + return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); +} + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long word) +{ + int k; + + word = ~word; + k = 31; + if (word & 0x0000ffff) { k -= 16; word <<= 16; } + if (word & 0x00ff0000) { k -= 8; word <<= 8; } + if (word & 0x0f000000) { k -= 4; word <<= 4; } + if (word & 0x30000000) { k -= 2; word <<= 2; } + if (word & 0x40000000) { k -= 1; } + return k; +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +#define ffs(x) generic_ffs(x) + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#define ext2_set_bit test_and_set_bit +#define ext2_clear_bit test_and_clear_bit +#define ext2_test_bit test_bit +#define ext2_find_first_zero_bit find_first_zero_bit +#define ext2_find_next_zero_bit find_next_zero_bit + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +#endif /* __KERNEL__ */ + +#endif /* _ARM_BITOPS_H */ diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h new file mode 100644 index 0000000..c3489f1 --- /dev/null +++ b/include/asm-arm/byteorder.h @@ -0,0 +1,32 @@ +/* + * linux/include/asm-arm/byteorder.h + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ +#ifndef __ASM_ARM_BYTEORDER_H +#define __ASM_ARM_BYTEORDER_H + + +#include + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __ARMEB__ +#include +#else +#include +#endif + +#endif diff --git a/include/asm-arm/errno.h b/include/asm-arm/errno.h new file mode 100644 index 0000000..134a8fc --- /dev/null +++ b/include/asm-arm/errno.h @@ -0,0 +1,138 @@ +#ifndef _ARM_ERRNO_H +#define _ARM_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ +#define EDEADLOCK 58 /* File locking deadlock error */ +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +/* Should never be seen by user programs */ +#define ERESTARTSYS 512 +#define ERESTARTNOINTR 513 +#define ERESTARTNOHAND 514 /* restart if no handler.. */ +#define ENOIOCTLCMD 515 /* No ioctl command */ + +#define _LAST_ERRNO 515 + +#endif diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h new file mode 100644 index 0000000..c2d5291 --- /dev/null +++ b/include/asm-arm/global_data.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long fb_base; /* base address of frame buffer */ +#ifdef CONFIG_VFD + unsigned char vfd_type; /* display type */ +#endif +#if 0 + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long bus_clk; + unsigned long ram_size; /* RAM size */ + unsigned long reset_status; /* reset status register at boot */ +#endif + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") + +#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-arm/hardware.h b/include/asm-arm/hardware.h new file mode 100644 index 0000000..1fd1a5b --- /dev/null +++ b/include/asm-arm/hardware.h @@ -0,0 +1,18 @@ +/* + * linux/include/asm-arm/hardware.h + * + * Copyright (C) 1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common hardware definitions + */ + +#ifndef __ASM_HARDWARE_H +#define __ASM_HARDWARE_H + +#include + +#endif diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h new file mode 100644 index 0000000..c2b69fb --- /dev/null +++ b/include/asm-arm/io.h @@ -0,0 +1,299 @@ +/* + * linux/include/asm-arm/io.h + * + * Copyright (C) 1996-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_ARM_IO_H +#define __ASM_ARM_IO_H + +#ifdef __KERNEL__ + +#include +#include +#include +#if 0 /* XXX###XXX */ +#include +#endif /* XXX###XXX */ + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v,a) __arch_putb(v,a) +#define __raw_writew(v,a) __arch_putw(v,a) +#define __raw_writel(v,a) __arch_putl(v,a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) +#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) +#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) + +#define __raw_base_readb(base,off) __arch_base_getb(base,off) +#define __raw_base_readw(base,off) __arch_base_getw(base,off) +#define __raw_base_readl(base,off) __arch_base_getl(base,off) + +/* + * Now, pick up the machine-defined IO definitions + */ +#if 0 /* XXX###XXX */ +#include +#endif /* XXX###XXX */ + +/* + * IO port access primitives + * ------------------------- + * + * The ARM doesn't have special IO access instructions; all IO is memory + * mapped. Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * Note that for a big endian machine, this implies that the following + * big endian mode connectivity is in place, as described by numerious + * ARM documents: + * + * PCI: D0-D7 D8-D15 D16-D23 D24-D31 + * ARM: D24-D31 D16-D23 D8-D15 D0-D7 + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#ifdef __io +#define outb(v,p) __raw_writeb(v,__io(p)) +#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p,d,l) __raw_writesb(__io(p),d,l) +#define outsw(p,d,l) __raw_writesw(__io(p),d,l) +#define outsl(p,d,l) __raw_writesl(__io(p),d,l) + +#define insb(p,d,l) __raw_readsb(__io(p),d,l) +#define insw(p,d,l) __raw_readsw(__io(p),d,l) +#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#endif + +#define outb_p(val,port) outb((val),(port)) +#define outw_p(val,port) outw((val),(port)) +#define outl_p(val,port) outl((val),(port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port,from,len) outsb(port,from,len) +#define outsw_p(port,from,len) outsw(port,from,len) +#define outsl_p(port,from,len) outsl(port,from,len) +#define insb_p(port,to,len) insb(port,to,len) +#define insw_p(port,to,len) insw(port,to,len) +#define insl_p(port,to,len) insl(port,to,len) + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * linux/Documentation/IO-mapping.txt. If you want a + * physical address, use __ioremap instead. + */ +extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); +extern void __iounmap(void *addr); + +/* + * Generic ioremap support. + * + * Define: + * iomem_valid_addr(off,size) + * iomem_to_phys(off) + */ +#ifdef iomem_valid_addr +#define __arch_ioremap(off,sz,nocache) \ + ({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off),_size,0); \ + _ret; \ + }) + +#define __arch_iounmap __iounmap +#endif + +#define ioremap(off,sz) __arch_ioremap((off),(sz),0) +#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) +#define iounmap(_addr) __arch_iounmap(_addr) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * String version of IO memory access ops: + */ +extern void _memcpy_fromio(void *, unsigned long, size_t); +extern void _memcpy_toio(unsigned long, const void *, size_t); +extern void _memset_io(unsigned long, int, size_t); + +extern void __readwrite_bug(const char *fn); + +/* + * If this architecture has PCI memory IO, then define the read/write + * macros. These should only be used with the cookie passed from + * ioremap. + */ +#ifdef __mem_pci + +#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) +#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) + +#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) +#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) +#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) + +#define eth_io_copy_and_sum(s,c,l,b) \ + eth_copy_and_sum((s),__mem_pci(c),(l),(b)) + +static inline int +check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#elif !defined(readb) + +#define readb(addr) (__readwrite_bug("readb"),0) +#define readw(addr) (__readwrite_bug("readw"),0) +#define readl(addr) (__readwrite_bug("readl"),0) +#define writeb(v,addr) __readwrite_bug("writeb") +#define writew(v,addr) __readwrite_bug("writew") +#define writel(v,addr) __readwrite_bug("writel") + +#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") + +#define check_signature(io,sig,len) (0) + +#endif /* __mem_pci */ + +/* + * If this architecture has ISA IO, then define the isa_read/isa_write + * macros. + */ +#ifdef __mem_isa + +#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) +#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + eth_copy_and_sum((a),__mem_isa(b),(c),(d)) + +static inline int +isa_check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#else /* __mem_isa */ + +#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) +#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) +#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) +#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") +#define isa_writew(val,addr) __readwrite_bug("isa_writew") +#define isa_writel(val,addr) __readwrite_bug("isa_writel") +#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") +#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") +#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + __readwrite_bug("isa_eth_io_copy_and_sum") + +#define isa_check_signature(io,sig,len) (0) + +#endif /* __mem_isa */ +#endif /* __KERNEL__ */ +#endif /* __ASM_ARM_IO_H */ diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h new file mode 100644 index 0000000..fd03748 --- /dev/null +++ b/include/asm-arm/mach-types.h @@ -0,0 +1,9414 @@ +/* + * This was automagically generated from arch/arm/tools/mach-types! + * Do NOT edit + */ + +#ifndef __ASM_ARM_MACH_TYPE_H +#define __ASM_ARM_MACH_TYPE_H + +#include + +#ifndef __ASSEMBLY__ +/* The type of machine we're running on */ +extern unsigned int __machine_arch_type; +#endif + +/* see arch/arm/kernel/arch.c for a description of these */ +#define MACH_TYPE_EBSA110 0 +#define MACH_TYPE_RISCPC 1 +#define MACH_TYPE_NEXUSPCI 3 +#define MACH_TYPE_EBSA285 4 +#define MACH_TYPE_NETWINDER 5 +#define MACH_TYPE_CATS 6 +#define MACH_TYPE_TBOX 7 +#define MACH_TYPE_CO285 8 +#define MACH_TYPE_CLPS7110 9 +#define MACH_TYPE_ARCHIMEDES 10 +#define MACH_TYPE_A5K 11 +#define MACH_TYPE_ETOILE 12 +#define MACH_TYPE_LACIE_NAS 13 +#define MACH_TYPE_CLPS7500 14 +#define MACH_TYPE_SHARK 15 +#define MACH_TYPE_BRUTUS 16 +#define MACH_TYPE_PERSONAL_SERVER 17 +#define MACH_TYPE_ITSY 18 +#define MACH_TYPE_L7200 19 +#define MACH_TYPE_PLEB 20 +#define MACH_TYPE_INTEGRATOR 21 +#define MACH_TYPE_H3600 22 +#define MACH_TYPE_IXP1200 23 +#define MACH_TYPE_P720T 24 +#define MACH_TYPE_ASSABET 25 +#define MACH_TYPE_VICTOR 26 +#define MACH_TYPE_LART 27 +#define MACH_TYPE_RANGER 28 +#define MACH_TYPE_GRAPHICSCLIENT 29 +#define MACH_TYPE_XP860 30 +#define MACH_TYPE_CERF 31 +#define MACH_TYPE_NANOENGINE 32 +#define MACH_TYPE_FPIC 33 +#define MACH_TYPE_EXTENEX1 34 +#define MACH_TYPE_SHERMAN 35 +#define MACH_TYPE_ACCELENT_SA 36 +#define MACH_TYPE_ACCELENT_L7200 37 +#define MACH_TYPE_NETPORT 38 +#define MACH_TYPE_PANGOLIN 39 +#define MACH_TYPE_YOPY 40 +#define MACH_TYPE_COOLIDGE 41 +#define MACH_TYPE_HUW_WEBPANEL 42 +#define MACH_TYPE_SPOTME 43 +#define MACH_TYPE_FREEBIRD 44 +#define MACH_TYPE_TI925 45 +#define MACH_TYPE_RISCSTATION 46 +#define MACH_TYPE_CAVY 47 +#define MACH_TYPE_JORNADA720 48 +#define MACH_TYPE_OMNIMETER 49 +#define MACH_TYPE_EDB7211 50 +#define MACH_TYPE_CITYGO 51 +#define MACH_TYPE_PFS168 52 +#define MACH_TYPE_SPOT 53 +#define MACH_TYPE_FLEXANET 54 +#define MACH_TYPE_WEBPAL 55 +#define MACH_TYPE_LINPDA 56 +#define MACH_TYPE_ANAKIN 57 +#define MACH_TYPE_MVI 58 +#define MACH_TYPE_JUPITER 59 +#define MACH_TYPE_PSIONW 60 +#define MACH_TYPE_ALN 61 +#define MACH_TYPE_CAMELOT 62 +#define MACH_TYPE_GDS2200 63 +#define MACH_TYPE_PSION_SERIES7 64 +#define MACH_TYPE_XFILE 65 +#define MACH_TYPE_ACCELENT_EP9312 66 +#define MACH_TYPE_IC200 67 +#define MACH_TYPE_CREDITLART 68 +#define MACH_TYPE_HTM 69 +#define MACH_TYPE_IQ80310 70 +#define MACH_TYPE_FREEBOT 71 +#define MACH_TYPE_ENTEL 72 +#define MACH_TYPE_ENP3510 73 +#define MACH_TYPE_TRIZEPS 74 +#define MACH_TYPE_NESA 75 +#define MACH_TYPE_VENUS 76 +#define MACH_TYPE_TARDIS 77 +#define MACH_TYPE_MERCURY 78 +#define MACH_TYPE_EMPEG 79 +#define MACH_TYPE_I80200FCC 80 +#define MACH_TYPE_ITT_CPB 81 +#define MACH_TYPE_SVC 82 +#define MACH_TYPE_ALPHA2 84 +#define MACH_TYPE_ALPHA1 85 +#define MACH_TYPE_NETARM 86 +#define MACH_TYPE_SIMPAD 87 +#define MACH_TYPE_PDA1 88 +#define MACH_TYPE_LUBBOCK 89 +#define MACH_TYPE_ANIKO 90 +#define MACH_TYPE_CLEP7212 91 +#define MACH_TYPE_CS89712 92 +#define MACH_TYPE_WEARARM 93 +#define MACH_TYPE_POSSIO_PX 94 +#define MACH_TYPE_SIDEARM 95 +#define MACH_TYPE_STORK 96 +#define MACH_TYPE_SHANNON 97 +#define MACH_TYPE_ACE 98 +#define MACH_TYPE_BALLYARM 99 +#define MACH_TYPE_SIMPUTER 100 +#define MACH_TYPE_NEXTERM 101 +#define MACH_TYPE_SA1100_ELF 102 +#define MACH_TYPE_GATOR 103 +#define MACH_TYPE_GRANITE 104 +#define MACH_TYPE_CONSUS 105 +#define MACH_TYPE_AAED2000 106 +#define MACH_TYPE_CDB89712 107 +#define MACH_TYPE_GRAPHICSMASTER 108 +#define MACH_TYPE_ADSBITSY 109 +#define MACH_TYPE_PXA_IDP 110 +#define MACH_TYPE_PLCE 111 +#define MACH_TYPE_PT_SYSTEM3 112 +#define MACH_TYPE_MEDALB 113 +#define MACH_TYPE_EAGLE 114 +#define MACH_TYPE_DSC21 115 +#define MACH_TYPE_DSC24 116 +#define MACH_TYPE_TI5472 117 +#define MACH_TYPE_AUTCPU12 118 +#define MACH_TYPE_UENGINE 119 +#define MACH_TYPE_BLUESTEM 120 +#define MACH_TYPE_XINGU8 121 +#define MACH_TYPE_BUSHSTB 122 +#define MACH_TYPE_EPSILON1 123 +#define MACH_TYPE_BALLOON 124 +#define MACH_TYPE_PUPPY 125 +#define MACH_TYPE_ELROY 126 +#define MACH_TYPE_GMS720 127 +#define MACH_TYPE_S24X 128 +#define MACH_TYPE_JTEL_CLEP7312 129 +#define MACH_TYPE_CX821XX 130 +#define MACH_TYPE_EDB7312 131 +#define MACH_TYPE_BSA1110 132 +#define MACH_TYPE_POWERPIN 133 +#define MACH_TYPE_OPENARM 134 +#define MACH_TYPE_WHITECHAPEL 135 +#define MACH_TYPE_H3100 136 +#define MACH_TYPE_H3800 137 +#define MACH_TYPE_BLUE_V1 138 +#define MACH_TYPE_PXA_CERF 139 +#define MACH_TYPE_ARM7TEVB 140 +#define MACH_TYPE_D7400 141 +#define MACH_TYPE_PIRANHA 142 +#define MACH_TYPE_SBCAMELOT 143 +#define MACH_TYPE_KINGS 144 +#define MACH_TYPE_SMDK2400 145 +#define MACH_TYPE_COLLIE 146 +#define MACH_TYPE_IDR 147 +#define MACH_TYPE_BADGE4 148 +#define MACH_TYPE_WEBNET 149 +#define MACH_TYPE_D7300 150 +#define MACH_TYPE_CEP 151 +#define MACH_TYPE_FORTUNET 152 +#define MACH_TYPE_VC547X 153 +#define MACH_TYPE_FILEWALKER 154 +#define MACH_TYPE_NETGATEWAY 155 +#define MACH_TYPE_SYMBOL2800 156 +#define MACH_TYPE_SUNS 157 +#define MACH_TYPE_FRODO 158 +#define MACH_TYPE_MACH_TYTE_MS301 159 +#define MACH_TYPE_MX1ADS 160 +#define MACH_TYPE_H7201 161 +#define MACH_TYPE_H7202 162 +#define MACH_TYPE_AMICO 163 +#define MACH_TYPE_IAM 164 +#define MACH_TYPE_TT530 165 +#define MACH_TYPE_SAM2400 166 +#define MACH_TYPE_JORNADA56X 167 +#define MACH_TYPE_ACTIVE 168 +#define MACH_TYPE_IQ80321 169 +#define MACH_TYPE_WID 170 +#define MACH_TYPE_SABINAL 171 +#define MACH_TYPE_IXP425_MATACUMBE 172 +#define MACH_TYPE_MINIPRINT 173 +#define MACH_TYPE_ADM510X 174 +#define MACH_TYPE_SVS200 175 +#define MACH_TYPE_ATG_TCU 176 +#define MACH_TYPE_JORNADA820 177 +#define MACH_TYPE_S3C44B0 178 +#define MACH_TYPE_MARGIS2 179 +#define MACH_TYPE_KS8695 180 +#define MACH_TYPE_BRH 181 +#define MACH_TYPE_S3C2410 182 +#define MACH_TYPE_POSSIO_PX30 183 +#define MACH_TYPE_S3C2800 184 +#define MACH_TYPE_FLEETWOOD 185 +#define MACH_TYPE_OMAHA 186 +#define MACH_TYPE_TA7 187 +#define MACH_TYPE_NOVA 188 +#define MACH_TYPE_HMK 189 +#define MACH_TYPE_KARO 190 +#define MACH_TYPE_FESTER 191 +#define MACH_TYPE_GPI 192 +#define MACH_TYPE_SMDK2410 193 +#define MACH_TYPE_I519 194 +#define MACH_TYPE_NEXIO 195 +#define MACH_TYPE_BITBOX 196 +#define MACH_TYPE_G200 197 +#define MACH_TYPE_GILL 198 +#define MACH_TYPE_PXA_MERCURY 199 +#define MACH_TYPE_CEIVA 200 +#define MACH_TYPE_FRET 201 +#define MACH_TYPE_EMAILPHONE 202 +#define MACH_TYPE_H3900 203 +#define MACH_TYPE_PXA1 204 +#define MACH_TYPE_KOAN369 205 +#define MACH_TYPE_COGENT 206 +#define MACH_TYPE_ESL_SIMPUTER 207 +#define MACH_TYPE_ESL_SIMPUTER_CLR 208 +#define MACH_TYPE_ESL_SIMPUTER_BW 209 +#define MACH_TYPE_HHP_CRADLE 210 +#define MACH_TYPE_HE500 211 +#define MACH_TYPE_INHANDELF2 212 +#define MACH_TYPE_INHANDFTIP 213 +#define MACH_TYPE_DNP1110 214 +#define MACH_TYPE_PNP1110 215 +#define MACH_TYPE_CSB226 216 +#define MACH_TYPE_ARNOLD 217 +#define MACH_TYPE_VOICEBLUE 218 +#define MACH_TYPE_JZ8028 219 +#define MACH_TYPE_H5400 220 +#define MACH_TYPE_FORTE 221 +#define MACH_TYPE_ACAM 222 +#define MACH_TYPE_ABOX 223 +#define MACH_TYPE_ATMEL 224 +#define MACH_TYPE_SITSANG 225 +#define MACH_TYPE_CPU1110LCDNET 226 +#define MACH_TYPE_MPL_VCMA9 227 +#define MACH_TYPE_OPUS_A1 228 +#define MACH_TYPE_DAYTONA 229 +#define MACH_TYPE_KILLBEAR 230 +#define MACH_TYPE_YOHO 231 +#define MACH_TYPE_JASPER 232 +#define MACH_TYPE_DSC25 233 +#define MACH_TYPE_OMAP_INNOVATOR 234 +#define MACH_TYPE_RAMSES 235 +#define MACH_TYPE_S28X 236 +#define MACH_TYPE_MPORT3 237 +#define MACH_TYPE_PXA_EAGLE250 238 +#define MACH_TYPE_PDB 239 +#define MACH_TYPE_BLUE_2G 240 +#define MACH_TYPE_BLUEARCH 241 +#define MACH_TYPE_IXDP2400 242 +#define MACH_TYPE_IXDP2800 243 +#define MACH_TYPE_EXPLORER 244 +#define MACH_TYPE_IXDP425 245 +#define MACH_TYPE_CHIMP 246 +#define MACH_TYPE_STORK_NEST 247 +#define MACH_TYPE_STORK_EGG 248 +#define MACH_TYPE_WISMO 249 +#define MACH_TYPE_EZLINX 250 +#define MACH_TYPE_AT91RM9200 251 +#define MACH_TYPE_ORION 252 +#define MACH_TYPE_NEPTUNE 253 +#define MACH_TYPE_HACKKIT 254 +#define MACH_TYPE_PXA_WINS30 255 +#define MACH_TYPE_LAVINNA 256 +#define MACH_TYPE_PXA_UENGINE 257 +#define MACH_TYPE_INNOKOM 258 +#define MACH_TYPE_BMS 259 +#define MACH_TYPE_IXCDP1100 260 +#define MACH_TYPE_PRPMC1100 261 +#define MACH_TYPE_AT91RM9200DK 262 +#define MACH_TYPE_ARMSTICK 263 +#define MACH_TYPE_ARMONIE 264 +#define MACH_TYPE_MPORT1 265 +#define MACH_TYPE_S3C5410 266 +#define MACH_TYPE_ZCP320A 267 +#define MACH_TYPE_I_BOX 268 +#define MACH_TYPE_STLC1502 269 +#define MACH_TYPE_SIREN 270 +#define MACH_TYPE_GREENLAKE 271 +#define MACH_TYPE_ARGUS 272 +#define MACH_TYPE_COMBADGE 273 +#define MACH_TYPE_ROKEPXA 274 +#define MACH_TYPE_CINTEGRATOR 275 +#define MACH_TYPE_GUIDEA07 276 +#define MACH_TYPE_TAT257 277 +#define MACH_TYPE_IGP2425 278 +#define MACH_TYPE_BLUEGRAMMA 279 +#define MACH_TYPE_IPOD 280 +#define MACH_TYPE_ADSBITSYX 281 +#define MACH_TYPE_TRIZEPS2 282 +#define MACH_TYPE_VIPER 283 +#define MACH_TYPE_ADSBITSYPLUS 284 +#define MACH_TYPE_ADSAGC 285 +#define MACH_TYPE_STP7312 286 +#define MACH_TYPE_NX_PHNX 287 +#define MACH_TYPE_WEP_EP250 288 +#define MACH_TYPE_INHANDELF3 289 +#define MACH_TYPE_ADI_COYOTE 290 +#define MACH_TYPE_IYONIX 291 +#define MACH_TYPE_DAMICAM_SA1110 292 +#define MACH_TYPE_MEG03 293 +#define MACH_TYPE_PXA_WHITECHAPEL 294 +#define MACH_TYPE_NWSC 295 +#define MACH_TYPE_NWLARM 296 +#define MACH_TYPE_IXP425_MGUARD 297 +#define MACH_TYPE_PXA_NETDCU4 298 +#define MACH_TYPE_IXDP2401 299 +#define MACH_TYPE_IXDP2801 300 +#define MACH_TYPE_ZODIAC 301 +#define MACH_TYPE_ARMMODUL 302 +#define MACH_TYPE_KETOP 303 +#define MACH_TYPE_AV7200 304 +#define MACH_TYPE_ARCH_TI925 305 +#define MACH_TYPE_ACQ200 306 +#define MACH_TYPE_PT_DAFIT 307 +#define MACH_TYPE_IHBA 308 +#define MACH_TYPE_QUINQUE 309 +#define MACH_TYPE_NIMBRAONE 310 +#define MACH_TYPE_NIMBRA29X 311 +#define MACH_TYPE_NIMBRA210 312 +#define MACH_TYPE_HHP_D95XX 313 +#define MACH_TYPE_LABARM 314 +#define MACH_TYPE_M825XX 315 +#define MACH_TYPE_M7100 316 +#define MACH_TYPE_NIPC2 317 +#define MACH_TYPE_FU7202 318 +#define MACH_TYPE_ADSAGX 319 +#define MACH_TYPE_PXA_POOH 320 +#define MACH_TYPE_BANDON 321 +#define MACH_TYPE_PCM7210 322 +#define MACH_TYPE_NMS9200 323 +#define MACH_TYPE_LOGODL 324 +#define MACH_TYPE_M7140 325 +#define MACH_TYPE_KOREBOT 326 +#define MACH_TYPE_IQ31244 327 +#define MACH_TYPE_KOAN393 328 +#define MACH_TYPE_INHANDFTIP3 329 +#define MACH_TYPE_GONZO 330 +#define MACH_TYPE_BAST 331 +#define MACH_TYPE_SCANPASS 332 +#define MACH_TYPE_EP7312_POOH 333 +#define MACH_TYPE_TA7S 334 +#define MACH_TYPE_TA7V 335 +#define MACH_TYPE_ICARUS 336 +#define MACH_TYPE_H1900 337 +#define MACH_TYPE_GEMINI 338 +#define MACH_TYPE_AXIM 339 +#define MACH_TYPE_AUDIOTRON 340 +#define MACH_TYPE_H2200 341 +#define MACH_TYPE_LOOX600 342 +#define MACH_TYPE_NIOP 343 +#define MACH_TYPE_DM310 344 +#define MACH_TYPE_SEEDPXA_C2 345 +#define MACH_TYPE_IXP4XX_MGUARD_PCI 346 +#define MACH_TYPE_H1940 347 +#define MACH_TYPE_SCORPIO 348 +#define MACH_TYPE_VIVA 349 +#define MACH_TYPE_PXA_XCARD 350 +#define MACH_TYPE_CSB335 351 +#define MACH_TYPE_IXRD425 352 +#define MACH_TYPE_IQ80315 353 +#define MACH_TYPE_NMP7312 354 +#define MACH_TYPE_CX861XX 355 +#define MACH_TYPE_ENP2611 356 +#define MACH_TYPE_XDA 357 +#define MACH_TYPE_CSIR_IMS 358 +#define MACH_TYPE_IXP421_DNAEETH 359 +#define MACH_TYPE_POCKETSERV9200 360 +#define MACH_TYPE_TOTO 361 +#define MACH_TYPE_S3C2440 362 +#define MACH_TYPE_KS8695P 363 +#define MACH_TYPE_SE4000 364 +#define MACH_TYPE_QUADRICEPS 365 +#define MACH_TYPE_BRONCO 366 +#define MACH_TYPE_ESL_SOFCOMP 368 +#define MACH_TYPE_S5C7375 369 +#define MACH_TYPE_SPEARHEAD 370 +#define MACH_TYPE_PANTERA 371 +#define MACH_TYPE_PRAYOGLITE 372 +#define MACH_TYPE_GUMSTIK 373 +#define MACH_TYPE_RCUBE 374 +#define MACH_TYPE_REA_OLV 375 +#define MACH_TYPE_PXA_IPHONE 376 +#define MACH_TYPE_S3C3410 377 +#define MACH_TYPE_ESPD_4510B 378 +#define MACH_TYPE_MP1X 379 +#define MACH_TYPE_AT91RM9200TB 380 +#define MACH_TYPE_ADSVGX 381 +#define MACH_TYPE_OMAP_H2 382 +#define MACH_TYPE_PELEE 383 +#define MACH_TYPE_E740 384 +#define MACH_TYPE_IQ80331 385 +#define MACH_TYPE_VERSATILE_PB 387 +#define MACH_TYPE_KEV7A400 388 +#define MACH_TYPE_LPD7A400 389 +#define MACH_TYPE_LPD7A404 390 +#define MACH_TYPE_FUJITSU_CAMELOT 391 +#define MACH_TYPE_JANUS2M 392 +#define MACH_TYPE_EMBTF 393 +#define MACH_TYPE_HPM 394 +#define MACH_TYPE_SMDK2410TK 395 +#define MACH_TYPE_SMDK2410AJ 396 +#define MACH_TYPE_STREETRACER 397 +#define MACH_TYPE_EFRAME 398 +#define MACH_TYPE_CSB337 399 +#define MACH_TYPE_PXA_LARK 400 +#define MACH_TYPE_PNP2110 401 +#define MACH_TYPE_TCC72X 402 +#define MACH_TYPE_ALTAIR 403 +#define MACH_TYPE_KC3 404 +#define MACH_TYPE_SINTEFTD 405 +#define MACH_TYPE_MAINSTONE 406 +#define MACH_TYPE_ADAY4X 407 +#define MACH_TYPE_LITE300 408 +#define MACH_TYPE_S5C7376 409 +#define MACH_TYPE_MT02 410 +#define MACH_TYPE_MPORT3S 411 +#define MACH_TYPE_RA_ALPHA 412 +#define MACH_TYPE_XCEP 413 +#define MACH_TYPE_ARCOM_MERCURY 414 +#define MACH_TYPE_STARGATE 415 +#define MACH_TYPE_ARMADILLOJ 416 +#define MACH_TYPE_ELROY_JACK 417 +#define MACH_TYPE_BACKEND 418 +#define MACH_TYPE_S5LINBOX 419 +#define MACH_TYPE_NOMADIK 420 +#define MACH_TYPE_IA_CPU_9200 421 +#define MACH_TYPE_AT91_BJA1 422 +#define MACH_TYPE_CORGI 423 +#define MACH_TYPE_POODLE 424 +#define MACH_TYPE_TEN 425 +#define MACH_TYPE_ROVERP5P 426 +#define MACH_TYPE_SC2700 427 +#define MACH_TYPE_EX_EAGLE 428 +#define MACH_TYPE_NX_PXA12 429 +#define MACH_TYPE_NX_PXA5 430 +#define MACH_TYPE_BLACKBOARD2 431 +#define MACH_TYPE_I819 432 +#define MACH_TYPE_IXMB995E 433 +#define MACH_TYPE_SKYRIDER 434 +#define MACH_TYPE_SKYHAWK 435 +#define MACH_TYPE_ENTERPRISE 436 +#define MACH_TYPE_DEP2410 437 +#define MACH_TYPE_ARMCORE 438 +#define MACH_TYPE_HOBBIT 439 +#define MACH_TYPE_H7210 440 +#define MACH_TYPE_PXA_NETDCU5 441 +#define MACH_TYPE_ACC 442 +#define MACH_TYPE_ESL_SARVA 443 +#define MACH_TYPE_XM250 444 +#define MACH_TYPE_T6TC1XB 445 +#define MACH_TYPE_ESS710 446 +#define MACH_TYPE_MX3ADS 447 +#define MACH_TYPE_HIMALAYA 448 +#define MACH_TYPE_BOLFENK 449 +#define MACH_TYPE_AT91RM9200KR 450 +#define MACH_TYPE_EDB9312 451 +#define MACH_TYPE_OMAP_GENERIC 452 +#define MACH_TYPE_AXIMX3 453 +#define MACH_TYPE_EB67XDIP 454 +#define MACH_TYPE_WEBTXS 455 +#define MACH_TYPE_HAWK 456 +#define MACH_TYPE_CCAT91SBC001 457 +#define MACH_TYPE_EXPRESSO 458 +#define MACH_TYPE_H4000 459 +#define MACH_TYPE_DINO 460 +#define MACH_TYPE_ML675K 461 +#define MACH_TYPE_EDB9301 462 +#define MACH_TYPE_EDB9315 463 +#define MACH_TYPE_RECIVA_TT 464 +#define MACH_TYPE_CSTCB01 465 +#define MACH_TYPE_CSTCB1 466 +#define MACH_TYPE_SHADWELL 467 +#define MACH_TYPE_GOEPEL263 468 +#define MACH_TYPE_ACQ100 469 +#define MACH_TYPE_MX1FS2 470 +#define MACH_TYPE_HIPTOP_G1 471 +#define MACH_TYPE_SPARKY 472 +#define MACH_TYPE_NS9750 473 +#define MACH_TYPE_PHOENIX 474 +#define MACH_TYPE_VR1000 475 +#define MACH_TYPE_DEISTERPXA 476 +#define MACH_TYPE_BCM1160 477 +#define MACH_TYPE_PCM022 478 +#define MACH_TYPE_ADSGCX 479 +#define MACH_TYPE_DREADNAUGHT 480 +#define MACH_TYPE_DM320 481 +#define MACH_TYPE_MARKOV 482 +#define MACH_TYPE_COS7A400 483 +#define MACH_TYPE_MILANO 484 +#define MACH_TYPE_UE9328 485 +#define MACH_TYPE_UEX255 486 +#define MACH_TYPE_UE2410 487 +#define MACH_TYPE_A620 488 +#define MACH_TYPE_OCELOT 489 +#define MACH_TYPE_CHEETAH 490 +#define MACH_TYPE_OMAP_PERSEUS2 491 +#define MACH_TYPE_ZVUE 492 +#define MACH_TYPE_ROVERP1 493 +#define MACH_TYPE_ASIDIAL2 494 +#define MACH_TYPE_S3C24A0 495 +#define MACH_TYPE_E800 496 +#define MACH_TYPE_E750 497 +#define MACH_TYPE_S3C5500 498 +#define MACH_TYPE_SMDK5500 499 +#define MACH_TYPE_SIGNALSYNC 500 +#define MACH_TYPE_NBC 501 +#define MACH_TYPE_KODIAK 502 +#define MACH_TYPE_NETBOOKPRO 503 +#define MACH_TYPE_HW90200 504 +#define MACH_TYPE_CONDOR 505 +#define MACH_TYPE_CUP 506 +#define MACH_TYPE_KITE 507 +#define MACH_TYPE_SCB9328 508 +#define MACH_TYPE_OMAP_H3 509 +#define MACH_TYPE_OMAP_H4 510 +#define MACH_TYPE_N10 511 +#define MACH_TYPE_MONTAJADE 512 +#define MACH_TYPE_SG560 513 +#define MACH_TYPE_DP1000 514 +#define MACH_TYPE_OMAP_OSK 515 +#define MACH_TYPE_RG100V3 516 +#define MACH_TYPE_MX2ADS 517 +#define MACH_TYPE_PXA_KILO 518 +#define MACH_TYPE_IXP4XX_EAGLE 519 +#define MACH_TYPE_TOSA 520 +#define MACH_TYPE_MB2520F 521 +#define MACH_TYPE_EMC1000 522 +#define MACH_TYPE_TIDSC25 523 +#define MACH_TYPE_AKCPMXL 524 +#define MACH_TYPE_AV3XX 525 +#define MACH_TYPE_AVILA 526 +#define MACH_TYPE_PXA_MPM10 527 +#define MACH_TYPE_PXA_KYANITE 528 +#define MACH_TYPE_SGOLD 529 +#define MACH_TYPE_OSCAR 530 +#define MACH_TYPE_EPXA4USB2 531 +#define MACH_TYPE_XSENGINE 532 +#define MACH_TYPE_IP600 533 +#define MACH_TYPE_MCAN2 534 +#define MACH_TYPE_DDI_BLUERIDGE 535 +#define MACH_TYPE_SKYMINDER 536 +#define MACH_TYPE_LPD79520 537 +#define MACH_TYPE_EDB9302 538 +#define MACH_TYPE_HW90340 539 +#define MACH_TYPE_CIP_BOX 540 +#define MACH_TYPE_IVPN 541 +#define MACH_TYPE_RSOC2 542 +#define MACH_TYPE_HUSKY 543 +#define MACH_TYPE_BOXER 544 +#define MACH_TYPE_SHEPHERD 545 +#define MACH_TYPE_AML42800AA 546 +#define MACH_TYPE_MACH_TYPE_ML674001 547 +#define MACH_TYPE_LPC2294 548 +#define MACH_TYPE_SWITCHGRASS 549 +#define MACH_TYPE_ENS_CMU 550 +#define MACH_TYPE_MM6_SDB 551 +#define MACH_TYPE_SATURN 552 +#define MACH_TYPE_ARGONPLUSEVB 553 +#define MACH_TYPE_SCMA11EVB 554 +#define MACH_TYPE_SMDK2800 555 +#define MACH_TYPE_MTWILSON 556 +#define MACH_TYPE_ZITI 557 +#define MACH_TYPE_GRANDFATHER 558 +#define MACH_TYPE_TENGINE 559 +#define MACH_TYPE_S3C2460 560 +#define MACH_TYPE_PDM 561 +#define MACH_TYPE_H4700 562 +#define MACH_TYPE_H6300 563 +#define MACH_TYPE_RZ1700 564 +#define MACH_TYPE_A716 565 +#define MACH_TYPE_ESTK2440A 566 +#define MACH_TYPE_ATWIXP425 567 +#define MACH_TYPE_CSB336 568 +#define MACH_TYPE_RIRM2 569 +#define MACH_TYPE_CX23518 570 +#define MACH_TYPE_CX2351X 571 +#define MACH_TYPE_COMPUTIME 572 +#define MACH_TYPE_IZARUS 573 +#define MACH_TYPE_RTS 574 +#define MACH_TYPE_SE5100 575 +#define MACH_TYPE_S3C2510 576 +#define MACH_TYPE_CSB437TL 577 +#define MACH_TYPE_SLAUSON 578 +#define MACH_TYPE_PEARLRIVER 579 +#define MACH_TYPE_TDC_P210 580 +#define MACH_TYPE_SG580 581 +#define MACH_TYPE_WRSBCARM7 582 +#define MACH_TYPE_IPD 583 +#define MACH_TYPE_PXA_DNP2110 584 +#define MACH_TYPE_XAENIAX 585 +#define MACH_TYPE_SOMN4250 586 +#define MACH_TYPE_PLEB2 587 +#define MACH_TYPE_CORNWALLIS 588 +#define MACH_TYPE_GURNEY_DRV 589 +#define MACH_TYPE_CHAFFEE 590 +#define MACH_TYPE_RMS101 591 +#define MACH_TYPE_RX3715 592 +#define MACH_TYPE_SWIFT 593 +#define MACH_TYPE_ROVERP7 594 +#define MACH_TYPE_PR818S 595 +#define MACH_TYPE_TRXPRO 596 +#define MACH_TYPE_NSLU2 597 +#define MACH_TYPE_E400 598 +#define MACH_TYPE_TRAB 599 +#define MACH_TYPE_CMC_PU2 600 +#define MACH_TYPE_FULCRUM 601 +#define MACH_TYPE_NETGATE42X 602 +#define MACH_TYPE_STR710 603 +#define MACH_TYPE_IXDPG425 604 +#define MACH_TYPE_TOMTOMGO 605 +#define MACH_TYPE_VERSATILE_AB 606 +#define MACH_TYPE_EDB9307 607 +#define MACH_TYPE_SG565 608 +#define MACH_TYPE_LPD79524 609 +#define MACH_TYPE_LPD79525 610 +#define MACH_TYPE_RMS100 611 +#define MACH_TYPE_KB9200 612 +#define MACH_TYPE_SX1 613 +#define MACH_TYPE_HMS39C7092 614 +#define MACH_TYPE_ARMADILLO 615 +#define MACH_TYPE_IPCU 616 +#define MACH_TYPE_LOOX720 617 +#define MACH_TYPE_IXDP465 618 +#define MACH_TYPE_IXDP2351 619 +#define MACH_TYPE_ADSVIX 620 +#define MACH_TYPE_DM270 621 +#define MACH_TYPE_SOCLTPLUS 622 +#define MACH_TYPE_ECIA 623 +#define MACH_TYPE_CM4008 624 +#define MACH_TYPE_P2001 625 +#define MACH_TYPE_TWISTER 626 +#define MACH_TYPE_MUDSHARK 627 +#define MACH_TYPE_HB2 628 +#define MACH_TYPE_IQ80332 629 +#define MACH_TYPE_SENDT 630 +#define MACH_TYPE_MX2JAZZ 631 +#define MACH_TYPE_MULTIIO 632 +#define MACH_TYPE_HRDISPLAY 633 +#define MACH_TYPE_SCMA11BB 634 +#define MACH_TYPE_TRIZEPS3 635 +#define MACH_TYPE_ZEFEERDZA 636 +#define MACH_TYPE_ZEFEERDZB 637 +#define MACH_TYPE_ZEFEERDZG 638 +#define MACH_TYPE_ZEFEERDZN 639 +#define MACH_TYPE_ZEFEERDZQ 640 +#define MACH_TYPE_GTWX5715 641 +#define MACH_TYPE_ASTRO_JACK 643 +#define MACH_TYPE_TIP03 644 +#define MACH_TYPE_A9200EC 645 +#define MACH_TYPE_PNX0105 646 +#define MACH_TYPE_ADCPOECPU 647 +#define MACH_TYPE_CSB637 648 +#define MACH_TYPE_ML69Q6203 649 +#define MACH_TYPE_MB9200 650 +#define MACH_TYPE_KULUN 651 +#define MACH_TYPE_SNAPPER 652 +#define MACH_TYPE_OPTIMA 653 +#define MACH_TYPE_DLHSBC 654 +#define MACH_TYPE_X30 655 +#define MACH_TYPE_N30 656 +#define MACH_TYPE_MANGA_KS8695 657 +#define MACH_TYPE_AJAX 658 +#define MACH_TYPE_NEC_MP900 659 +#define MACH_TYPE_VVTK1000 661 +#define MACH_TYPE_KAFA 662 +#define MACH_TYPE_VVTK3000 663 +#define MACH_TYPE_PIMX1 664 +#define MACH_TYPE_OLLIE 665 +#define MACH_TYPE_SKYMAX 666 +#define MACH_TYPE_JAZZ 667 +#define MACH_TYPE_TEL_T3 668 +#define MACH_TYPE_AISINO_FCR255 669 +#define MACH_TYPE_BTWEB 670 +#define MACH_TYPE_DBG_LH79520 671 +#define MACH_TYPE_CM41XX 672 +#define MACH_TYPE_TS72XX 673 +#define MACH_TYPE_NGGPXA 674 +#define MACH_TYPE_CSB535 675 +#define MACH_TYPE_CSB536 676 +#define MACH_TYPE_PXA_TRAKPOD 677 +#define MACH_TYPE_PRAXIS 678 +#define MACH_TYPE_LH75411 679 +#define MACH_TYPE_OTOM 680 +#define MACH_TYPE_NEXCODER_2440 681 +#define MACH_TYPE_LOOX410 682 +#define MACH_TYPE_WESTLAKE 683 +#define MACH_TYPE_NSB 684 +#define MACH_TYPE_ESL_SARVA_STN 685 +#define MACH_TYPE_ESL_SARVA_TFT 686 +#define MACH_TYPE_ESL_SARVA_IAD 687 +#define MACH_TYPE_ESL_SARVA_ACC 688 +#define MACH_TYPE_TYPHOON 689 +#define MACH_TYPE_CNAV 690 +#define MACH_TYPE_A730 691 +#define MACH_TYPE_NETSTAR 692 +#define MACH_TYPE_PHASEFALE_SUPERCON 693 +#define MACH_TYPE_SHIVA1100 694 +#define MACH_TYPE_ETEXSC 695 +#define MACH_TYPE_IXDPG465 696 +#define MACH_TYPE_A9M2410 697 +#define MACH_TYPE_A9M2440 698 +#define MACH_TYPE_A9M9750 699 +#define MACH_TYPE_A9M9360 700 +#define MACH_TYPE_UNC90 701 +#define MACH_TYPE_ECO920 702 +#define MACH_TYPE_SATVIEW 703 +#define MACH_TYPE_ROADRUNNER 704 +#define MACH_TYPE_AT91RM9200EK 705 +#define MACH_TYPE_GP32 706 +#define MACH_TYPE_GEM 707 +#define MACH_TYPE_I858 708 +#define MACH_TYPE_HX2750 709 +#define MACH_TYPE_ZEUSEVB 710 +#define MACH_TYPE_P700 711 +#define MACH_TYPE_CPE 712 +#define MACH_TYPE_SPITZ 713 +#define MACH_TYPE_NIMBRA340 714 +#define MACH_TYPE_LPC22XX 715 +#define MACH_TYPE_COMET3 716 +#define MACH_TYPE_COMET4 717 +#define MACH_TYPE_CSB625 718 +#define MACH_TYPE_FORTUNET2 719 +#define MACH_TYPE_S5H2200 720 +#define MACH_TYPE_OPTORM920 721 +#define MACH_TYPE_ADSBITSYXB 722 +#define MACH_TYPE_ADSSPHERE 723 +#define MACH_TYPE_ADSPORTAL 724 +#define MACH_TYPE_LN2410SBC 725 +#define MACH_TYPE_CB3RUFC 726 +#define MACH_TYPE_MP2USB 727 + +#ifdef CONFIG_ARCH_EBSA110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EBSA110 +# endif +# define machine_is_ebsa110() (machine_arch_type == MACH_TYPE_EBSA110) +#else +# define machine_is_ebsa110() (0) +#endif + +#ifdef CONFIG_ARCH_RPC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RISCPC +# endif +# define machine_is_riscpc() (machine_arch_type == MACH_TYPE_RISCPC) +#else +# define machine_is_riscpc() (0) +#endif + +#ifdef CONFIG_ARCH_NEXUSPCI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXUSPCI +# endif +# define machine_is_nexuspci() (machine_arch_type == MACH_TYPE_NEXUSPCI) +#else +# define machine_is_nexuspci() (0) +#endif + +#ifdef CONFIG_ARCH_EBSA285 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EBSA285 +# endif +# define machine_is_ebsa285() (machine_arch_type == MACH_TYPE_EBSA285) +#else +# define machine_is_ebsa285() (0) +#endif + +#ifdef CONFIG_ARCH_NETWINDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETWINDER +# endif +# define machine_is_netwinder() (machine_arch_type == MACH_TYPE_NETWINDER) +#else +# define machine_is_netwinder() (0) +#endif + +#ifdef CONFIG_ARCH_CATS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATS +# endif +# define machine_is_cats() (machine_arch_type == MACH_TYPE_CATS) +#else +# define machine_is_cats() (0) +#endif + +#ifdef CONFIG_ARCH_TBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TBOX +# endif +# define machine_is_tbox() (machine_arch_type == MACH_TYPE_TBOX) +#else +# define machine_is_tbox() (0) +#endif + +#ifdef CONFIG_ARCH_CO285 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CO285 +# endif +# define machine_is_co285() (machine_arch_type == MACH_TYPE_CO285) +#else +# define machine_is_co285() (0) +#endif + +#ifdef CONFIG_ARCH_CLPS7110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLPS7110 +# endif +# define machine_is_clps7110() (machine_arch_type == MACH_TYPE_CLPS7110) +#else +# define machine_is_clps7110() (0) +#endif + +#ifdef CONFIG_ARCH_ARC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCHIMEDES +# endif +# define machine_is_archimedes() (machine_arch_type == MACH_TYPE_ARCHIMEDES) +#else +# define machine_is_archimedes() (0) +#endif + +#ifdef CONFIG_ARCH_A5K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A5K +# endif +# define machine_is_a5k() (machine_arch_type == MACH_TYPE_A5K) +#else +# define machine_is_a5k() (0) +#endif + +#ifdef CONFIG_ARCH_ETOILE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETOILE +# endif +# define machine_is_etoile() (machine_arch_type == MACH_TYPE_ETOILE) +#else +# define machine_is_etoile() (0) +#endif + +#ifdef CONFIG_ARCH_LACIE_NAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LACIE_NAS +# endif +# define machine_is_lacie_nas() (machine_arch_type == MACH_TYPE_LACIE_NAS) +#else +# define machine_is_lacie_nas() (0) +#endif + +#ifdef CONFIG_ARCH_CLPS7500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLPS7500 +# endif +# define machine_is_clps7500() (machine_arch_type == MACH_TYPE_CLPS7500) +#else +# define machine_is_clps7500() (0) +#endif + +#ifdef CONFIG_ARCH_SHARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHARK +# endif +# define machine_is_shark() (machine_arch_type == MACH_TYPE_SHARK) +#else +# define machine_is_shark() (0) +#endif + +#ifdef CONFIG_SA1100_BRUTUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRUTUS +# endif +# define machine_is_brutus() (machine_arch_type == MACH_TYPE_BRUTUS) +#else +# define machine_is_brutus() (0) +#endif + +#ifdef CONFIG_ARCH_PERSONAL_SERVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PERSONAL_SERVER +# endif +# define machine_is_personal_server() (machine_arch_type == MACH_TYPE_PERSONAL_SERVER) +#else +# define machine_is_personal_server() (0) +#endif + +#ifdef CONFIG_SA1100_ITSY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ITSY +# endif +# define machine_is_itsy() (machine_arch_type == MACH_TYPE_ITSY) +#else +# define machine_is_itsy() (0) +#endif + +#ifdef CONFIG_ARCH_L7200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_L7200 +# endif +# define machine_is_l7200() (machine_arch_type == MACH_TYPE_L7200) +#else +# define machine_is_l7200() (0) +#endif + +#ifdef CONFIG_SA1100_PLEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLEB +# endif +# define machine_is_pleb() (machine_arch_type == MACH_TYPE_PLEB) +#else +# define machine_is_pleb() (0) +#endif + +#ifdef CONFIG_ARCH_INTEGRATOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INTEGRATOR +# endif +# define machine_is_integrator() (machine_arch_type == MACH_TYPE_INTEGRATOR) +#else +# define machine_is_integrator() (0) +#endif + +#ifdef CONFIG_SA1100_H3600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H3600 +# endif +# define machine_is_h3600() (machine_arch_type == MACH_TYPE_H3600) +#else +# define machine_is_h3600() (0) +#endif + +#ifdef CONFIG_ARCH_IXP1200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP1200 +# endif +# define machine_is_ixp1200() (machine_arch_type == MACH_TYPE_IXP1200) +#else +# define machine_is_ixp1200() (0) +#endif + +#ifdef CONFIG_ARCH_P720T +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P720T +# endif +# define machine_is_p720t() (machine_arch_type == MACH_TYPE_P720T) +#else +# define machine_is_p720t() (0) +#endif + +#ifdef CONFIG_SA1100_ASSABET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASSABET +# endif +# define machine_is_assabet() (machine_arch_type == MACH_TYPE_ASSABET) +#else +# define machine_is_assabet() (0) +#endif + +#ifdef CONFIG_SA1100_VICTOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VICTOR +# endif +# define machine_is_victor() (machine_arch_type == MACH_TYPE_VICTOR) +#else +# define machine_is_victor() (0) +#endif + +#ifdef CONFIG_SA1100_LART +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LART +# endif +# define machine_is_lart() (machine_arch_type == MACH_TYPE_LART) +#else +# define machine_is_lart() (0) +#endif + +#ifdef CONFIG_SA1100_RANGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RANGER +# endif +# define machine_is_ranger() (machine_arch_type == MACH_TYPE_RANGER) +#else +# define machine_is_ranger() (0) +#endif + +#ifdef CONFIG_SA1100_GRAPHICSCLIENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GRAPHICSCLIENT +# endif +# define machine_is_graphicsclient() (machine_arch_type == MACH_TYPE_GRAPHICSCLIENT) +#else +# define machine_is_graphicsclient() (0) +#endif + +#ifdef CONFIG_SA1100_XP860 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XP860 +# endif +# define machine_is_xp860() (machine_arch_type == MACH_TYPE_XP860) +#else +# define machine_is_xp860() (0) +#endif + +#ifdef CONFIG_SA1100_CERF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CERF +# endif +# define machine_is_cerf() (machine_arch_type == MACH_TYPE_CERF) +#else +# define machine_is_cerf() (0) +#endif + +#ifdef CONFIG_SA1100_NANOENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANOENGINE +# endif +# define machine_is_nanoengine() (machine_arch_type == MACH_TYPE_NANOENGINE) +#else +# define machine_is_nanoengine() (0) +#endif + +#ifdef CONFIG_SA1100_FPIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FPIC +# endif +# define machine_is_fpic() (machine_arch_type == MACH_TYPE_FPIC) +#else +# define machine_is_fpic() (0) +#endif + +#ifdef CONFIG_SA1100_EXTENEX1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXTENEX1 +# endif +# define machine_is_extenex1() (machine_arch_type == MACH_TYPE_EXTENEX1) +#else +# define machine_is_extenex1() (0) +#endif + +#ifdef CONFIG_SA1100_SHERMAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHERMAN +# endif +# define machine_is_sherman() (machine_arch_type == MACH_TYPE_SHERMAN) +#else +# define machine_is_sherman() (0) +#endif + +#ifdef CONFIG_SA1100_ACCELENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACCELENT_SA +# endif +# define machine_is_accelent_sa() (machine_arch_type == MACH_TYPE_ACCELENT_SA) +#else +# define machine_is_accelent_sa() (0) +#endif + +#ifdef CONFIG_ARCH_L7200_ACCELENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACCELENT_L7200 +# endif +# define machine_is_accelent_l7200() (machine_arch_type == MACH_TYPE_ACCELENT_L7200) +#else +# define machine_is_accelent_l7200() (0) +#endif + +#ifdef CONFIG_SA1100_NETPORT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETPORT +# endif +# define machine_is_netport() (machine_arch_type == MACH_TYPE_NETPORT) +#else +# define machine_is_netport() (0) +#endif + +#ifdef CONFIG_SA1100_PANGOLIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PANGOLIN +# endif +# define machine_is_pangolin() (machine_arch_type == MACH_TYPE_PANGOLIN) +#else +# define machine_is_pangolin() (0) +#endif + +#ifdef CONFIG_SA1100_YOPY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YOPY +# endif +# define machine_is_yopy() (machine_arch_type == MACH_TYPE_YOPY) +#else +# define machine_is_yopy() (0) +#endif + +#ifdef CONFIG_SA1100_COOLIDGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COOLIDGE +# endif +# define machine_is_coolidge() (machine_arch_type == MACH_TYPE_COOLIDGE) +#else +# define machine_is_coolidge() (0) +#endif + +#ifdef CONFIG_SA1100_HUW_WEBPANEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUW_WEBPANEL +# endif +# define machine_is_huw_webpanel() (machine_arch_type == MACH_TYPE_HUW_WEBPANEL) +#else +# define machine_is_huw_webpanel() (0) +#endif + +#ifdef CONFIG_ARCH_SPOTME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPOTME +# endif +# define machine_is_spotme() (machine_arch_type == MACH_TYPE_SPOTME) +#else +# define machine_is_spotme() (0) +#endif + +#ifdef CONFIG_ARCH_FREEBIRD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FREEBIRD +# endif +# define machine_is_freebird() (machine_arch_type == MACH_TYPE_FREEBIRD) +#else +# define machine_is_freebird() (0) +#endif + +#ifdef CONFIG_ARCH_TI925 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI925 +# endif +# define machine_is_ti925() (machine_arch_type == MACH_TYPE_TI925) +#else +# define machine_is_ti925() (0) +#endif + +#ifdef CONFIG_ARCH_RISCSTATION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RISCSTATION +# endif +# define machine_is_riscstation() (machine_arch_type == MACH_TYPE_RISCSTATION) +#else +# define machine_is_riscstation() (0) +#endif + +#ifdef CONFIG_SA1100_CAVY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAVY +# endif +# define machine_is_cavy() (machine_arch_type == MACH_TYPE_CAVY) +#else +# define machine_is_cavy() (0) +#endif + +#ifdef CONFIG_SA1100_JORNADA720 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JORNADA720 +# endif +# define machine_is_jornada720() (machine_arch_type == MACH_TYPE_JORNADA720) +#else +# define machine_is_jornada720() (0) +#endif + +#ifdef CONFIG_SA1100_OMNIMETER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMNIMETER +# endif +# define machine_is_omnimeter() (machine_arch_type == MACH_TYPE_OMNIMETER) +#else +# define machine_is_omnimeter() (0) +#endif + +#ifdef CONFIG_ARCH_EDB7211 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB7211 +# endif +# define machine_is_edb7211() (machine_arch_type == MACH_TYPE_EDB7211) +#else +# define machine_is_edb7211() (0) +#endif + +#ifdef CONFIG_SA1100_CITYGO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CITYGO +# endif +# define machine_is_citygo() (machine_arch_type == MACH_TYPE_CITYGO) +#else +# define machine_is_citygo() (0) +#endif + +#ifdef CONFIG_SA1100_PFS168 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PFS168 +# endif +# define machine_is_pfs168() (machine_arch_type == MACH_TYPE_PFS168) +#else +# define machine_is_pfs168() (0) +#endif + +#ifdef CONFIG_SA1100_SPOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPOT +# endif +# define machine_is_spot() (machine_arch_type == MACH_TYPE_SPOT) +#else +# define machine_is_spot() (0) +#endif + +#ifdef CONFIG_SA1100_FLEXANET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLEXANET +# endif +# define machine_is_flexanet() (machine_arch_type == MACH_TYPE_FLEXANET) +#else +# define machine_is_flexanet() (0) +#endif + +#ifdef CONFIG_ARCH_WEBPAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEBPAL +# endif +# define machine_is_webpal() (machine_arch_type == MACH_TYPE_WEBPAL) +#else +# define machine_is_webpal() (0) +#endif + +#ifdef CONFIG_SA1100_LINPDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINPDA +# endif +# define machine_is_linpda() (machine_arch_type == MACH_TYPE_LINPDA) +#else +# define machine_is_linpda() (0) +#endif + +#ifdef CONFIG_ARCH_ANAKIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANAKIN +# endif +# define machine_is_anakin() (machine_arch_type == MACH_TYPE_ANAKIN) +#else +# define machine_is_anakin() (0) +#endif + +#ifdef CONFIG_SA1100_MVI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MVI +# endif +# define machine_is_mvi() (machine_arch_type == MACH_TYPE_MVI) +#else +# define machine_is_mvi() (0) +#endif + +#ifdef CONFIG_SA1100_JUPITER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JUPITER +# endif +# define machine_is_jupiter() (machine_arch_type == MACH_TYPE_JUPITER) +#else +# define machine_is_jupiter() (0) +#endif + +#ifdef CONFIG_ARCH_PSIONW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PSIONW +# endif +# define machine_is_psionw() (machine_arch_type == MACH_TYPE_PSIONW) +#else +# define machine_is_psionw() (0) +#endif + +#ifdef CONFIG_SA1100_ALN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALN +# endif +# define machine_is_aln() (machine_arch_type == MACH_TYPE_ALN) +#else +# define machine_is_aln() (0) +#endif + +#ifdef CONFIG_ARCH_CAMELOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAMELOT +# endif +# define machine_is_epxa() (machine_arch_type == MACH_TYPE_CAMELOT) +#else +# define machine_is_epxa() (0) +#endif + +#ifdef CONFIG_SA1100_GDS2200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GDS2200 +# endif +# define machine_is_gds2200() (machine_arch_type == MACH_TYPE_GDS2200) +#else +# define machine_is_gds2200() (0) +#endif + +#ifdef CONFIG_SA1100_PSION_SERIES7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PSION_SERIES7 +# endif +# define machine_is_psion_series7() (machine_arch_type == MACH_TYPE_PSION_SERIES7) +#else +# define machine_is_psion_series7() (0) +#endif + +#ifdef CONFIG_SA1100_XFILE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XFILE +# endif +# define machine_is_xfile() (machine_arch_type == MACH_TYPE_XFILE) +#else +# define machine_is_xfile() (0) +#endif + +#ifdef CONFIG_ARCH_ACCELENT_EP9312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACCELENT_EP9312 +# endif +# define machine_is_accelent_ep9312() (machine_arch_type == MACH_TYPE_ACCELENT_EP9312) +#else +# define machine_is_accelent_ep9312() (0) +#endif + +#ifdef CONFIG_ARCH_IC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IC200 +# endif +# define machine_is_ic200() (machine_arch_type == MACH_TYPE_IC200) +#else +# define machine_is_ic200() (0) +#endif + +#ifdef CONFIG_SA1100_CREDITLART +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CREDITLART +# endif +# define machine_is_creditlart() (machine_arch_type == MACH_TYPE_CREDITLART) +#else +# define machine_is_creditlart() (0) +#endif + +#ifdef CONFIG_SA1100_HTM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTM +# endif +# define machine_is_htm() (machine_arch_type == MACH_TYPE_HTM) +#else +# define machine_is_htm() (0) +#endif + +#ifdef CONFIG_ARCH_IQ80310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80310 +# endif +# define machine_is_iq80310() (machine_arch_type == MACH_TYPE_IQ80310) +#else +# define machine_is_iq80310() (0) +#endif + +#ifdef CONFIG_SA1100_FREEBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FREEBOT +# endif +# define machine_is_freebot() (machine_arch_type == MACH_TYPE_FREEBOT) +#else +# define machine_is_freebot() (0) +#endif + +#ifdef CONFIG_ARCH_ENTEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENTEL +# endif +# define machine_is_entel() (machine_arch_type == MACH_TYPE_ENTEL) +#else +# define machine_is_entel() (0) +#endif + +#ifdef CONFIG_ARCH_ENP3510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENP3510 +# endif +# define machine_is_enp3510() (machine_arch_type == MACH_TYPE_ENP3510) +#else +# define machine_is_enp3510() (0) +#endif + +#ifdef CONFIG_SA1100_TRIZEPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS +# endif +# define machine_is_trizeps() (machine_arch_type == MACH_TYPE_TRIZEPS) +#else +# define machine_is_trizeps() (0) +#endif + +#ifdef CONFIG_SA1100_NESA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NESA +# endif +# define machine_is_nesa() (machine_arch_type == MACH_TYPE_NESA) +#else +# define machine_is_nesa() (0) +#endif + +#ifdef CONFIG_ARCH_VENUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENUS +# endif +# define machine_is_venus() (machine_arch_type == MACH_TYPE_VENUS) +#else +# define machine_is_venus() (0) +#endif + +#ifdef CONFIG_ARCH_TARDIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TARDIS +# endif +# define machine_is_tardis() (machine_arch_type == MACH_TYPE_TARDIS) +#else +# define machine_is_tardis() (0) +#endif + +#ifdef CONFIG_ARCH_MERCURY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MERCURY +# endif +# define machine_is_mercury() (machine_arch_type == MACH_TYPE_MERCURY) +#else +# define machine_is_mercury() (0) +#endif + +#ifdef CONFIG_SA1100_EMPEG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMPEG +# endif +# define machine_is_empeg() (machine_arch_type == MACH_TYPE_EMPEG) +#else +# define machine_is_empeg() (0) +#endif + +#ifdef CONFIG_ARCH_I80200FCC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I80200FCC +# endif +# define machine_is_adi_evb() (machine_arch_type == MACH_TYPE_I80200FCC) +#else +# define machine_is_adi_evb() (0) +#endif + +#ifdef CONFIG_SA1100_ITT_CPB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ITT_CPB +# endif +# define machine_is_itt_cpb() (machine_arch_type == MACH_TYPE_ITT_CPB) +#else +# define machine_is_itt_cpb() (0) +#endif + +#ifdef CONFIG_SA1100_SVC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVC +# endif +# define machine_is_svc() (machine_arch_type == MACH_TYPE_SVC) +#else +# define machine_is_svc() (0) +#endif + +#ifdef CONFIG_SA1100_ALPHA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALPHA2 +# endif +# define machine_is_alpha2() (machine_arch_type == MACH_TYPE_ALPHA2) +#else +# define machine_is_alpha2() (0) +#endif + +#ifdef CONFIG_SA1100_ALPHA1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALPHA1 +# endif +# define machine_is_alpha1() (machine_arch_type == MACH_TYPE_ALPHA1) +#else +# define machine_is_alpha1() (0) +#endif + +#ifdef CONFIG_ARCH_NETARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETARM +# endif +# define machine_is_netarm() (machine_arch_type == MACH_TYPE_NETARM) +#else +# define machine_is_netarm() (0) +#endif + +#ifdef CONFIG_SA1100_SIMPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMPAD +# endif +# define machine_is_simpad() (machine_arch_type == MACH_TYPE_SIMPAD) +#else +# define machine_is_simpad() (0) +#endif + +#ifdef CONFIG_ARCH_PDA1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PDA1 +# endif +# define machine_is_pda1() (machine_arch_type == MACH_TYPE_PDA1) +#else +# define machine_is_pda1() (0) +#endif + +#ifdef CONFIG_ARCH_LUBBOCK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUBBOCK +# endif +# define machine_is_lubbock() (machine_arch_type == MACH_TYPE_LUBBOCK) +#else +# define machine_is_lubbock() (0) +#endif + +#ifdef CONFIG_ARCH_ANIKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANIKO +# endif +# define machine_is_aniko() (machine_arch_type == MACH_TYPE_ANIKO) +#else +# define machine_is_aniko() (0) +#endif + +#ifdef CONFIG_ARCH_CLEP7212 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLEP7212 +# endif +# define machine_is_clep7212() (machine_arch_type == MACH_TYPE_CLEP7212) +#else +# define machine_is_clep7212() (0) +#endif + +#ifdef CONFIG_ARCH_CS89712 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CS89712 +# endif +# define machine_is_cs89712() (machine_arch_type == MACH_TYPE_CS89712) +#else +# define machine_is_cs89712() (0) +#endif + +#ifdef CONFIG_SA1100_WEARARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEARARM +# endif +# define machine_is_weararm() (machine_arch_type == MACH_TYPE_WEARARM) +#else +# define machine_is_weararm() (0) +#endif + +#ifdef CONFIG_SA1100_POSSIO_PX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POSSIO_PX +# endif +# define machine_is_possio_px() (machine_arch_type == MACH_TYPE_POSSIO_PX) +#else +# define machine_is_possio_px() (0) +#endif + +#ifdef CONFIG_SA1100_SIDEARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIDEARM +# endif +# define machine_is_sidearm() (machine_arch_type == MACH_TYPE_SIDEARM) +#else +# define machine_is_sidearm() (0) +#endif + +#ifdef CONFIG_SA1100_STORK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STORK +# endif +# define machine_is_stork() (machine_arch_type == MACH_TYPE_STORK) +#else +# define machine_is_stork() (0) +#endif + +#ifdef CONFIG_SA1100_SHANNON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHANNON +# endif +# define machine_is_shannon() (machine_arch_type == MACH_TYPE_SHANNON) +#else +# define machine_is_shannon() (0) +#endif + +#ifdef CONFIG_ARCH_ACE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACE +# endif +# define machine_is_ace() (machine_arch_type == MACH_TYPE_ACE) +#else +# define machine_is_ace() (0) +#endif + +#ifdef CONFIG_SA1100_BALLYARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BALLYARM +# endif +# define machine_is_ballyarm() (machine_arch_type == MACH_TYPE_BALLYARM) +#else +# define machine_is_ballyarm() (0) +#endif + +#ifdef CONFIG_SA1100_SIMPUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMPUTER +# endif +# define machine_is_simputer() (machine_arch_type == MACH_TYPE_SIMPUTER) +#else +# define machine_is_simputer() (0) +#endif + +#ifdef CONFIG_SA1100_NEXTERM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXTERM +# endif +# define machine_is_nexterm() (machine_arch_type == MACH_TYPE_NEXTERM) +#else +# define machine_is_nexterm() (0) +#endif + +#ifdef CONFIG_SA1100_SA1100_ELF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SA1100_ELF +# endif +# define machine_is_sa1100_elf() (machine_arch_type == MACH_TYPE_SA1100_ELF) +#else +# define machine_is_sa1100_elf() (0) +#endif + +#ifdef CONFIG_SA1100_GATOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GATOR +# endif +# define machine_is_gator() (machine_arch_type == MACH_TYPE_GATOR) +#else +# define machine_is_gator() (0) +#endif + +#ifdef CONFIG_ARCH_GRANITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GRANITE +# endif +# define machine_is_granite() (machine_arch_type == MACH_TYPE_GRANITE) +#else +# define machine_is_granite() (0) +#endif + +#ifdef CONFIG_SA1100_CONSUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CONSUS +# endif +# define machine_is_consus() (machine_arch_type == MACH_TYPE_CONSUS) +#else +# define machine_is_consus() (0) +#endif + +#ifdef CONFIG_ARCH_AAED2000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AAED2000 +# endif +# define machine_is_aaed2000() (machine_arch_type == MACH_TYPE_AAED2000) +#else +# define machine_is_aaed2000() (0) +#endif + +#ifdef CONFIG_ARCH_CDB89712 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CDB89712 +# endif +# define machine_is_cdb89712() (machine_arch_type == MACH_TYPE_CDB89712) +#else +# define machine_is_cdb89712() (0) +#endif + +#ifdef CONFIG_SA1100_GRAPHICSMASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GRAPHICSMASTER +# endif +# define machine_is_graphicsmaster() (machine_arch_type == MACH_TYPE_GRAPHICSMASTER) +#else +# define machine_is_graphicsmaster() (0) +#endif + +#ifdef CONFIG_SA1100_ADSBITSY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSY +# endif +# define machine_is_adsbitsy() (machine_arch_type == MACH_TYPE_ADSBITSY) +#else +# define machine_is_adsbitsy() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_IDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_IDP +# endif +# define machine_is_pxa_idp() (machine_arch_type == MACH_TYPE_PXA_IDP) +#else +# define machine_is_pxa_idp() (0) +#endif + +#ifdef CONFIG_ARCH_PLCE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLCE +# endif +# define machine_is_plce() (machine_arch_type == MACH_TYPE_PLCE) +#else +# define machine_is_plce() (0) +#endif + +#ifdef CONFIG_SA1100_PT_SYSTEM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PT_SYSTEM3 +# endif +# define machine_is_pt_system3() (machine_arch_type == MACH_TYPE_PT_SYSTEM3) +#else +# define machine_is_pt_system3() (0) +#endif + +#ifdef CONFIG_ARCH_MEDALB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEDALB +# endif +# define machine_is_murphy() (machine_arch_type == MACH_TYPE_MEDALB) +#else +# define machine_is_murphy() (0) +#endif + +#ifdef CONFIG_ARCH_EAGLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EAGLE +# endif +# define machine_is_eagle() (machine_arch_type == MACH_TYPE_EAGLE) +#else +# define machine_is_eagle() (0) +#endif + +#ifdef CONFIG_ARCH_DSC21 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSC21 +# endif +# define machine_is_dsc21() (machine_arch_type == MACH_TYPE_DSC21) +#else +# define machine_is_dsc21() (0) +#endif + +#ifdef CONFIG_ARCH_DSC24 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSC24 +# endif +# define machine_is_dsc24() (machine_arch_type == MACH_TYPE_DSC24) +#else +# define machine_is_dsc24() (0) +#endif + +#ifdef CONFIG_ARCH_TI5472 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI5472 +# endif +# define machine_is_ti5472() (machine_arch_type == MACH_TYPE_TI5472) +#else +# define machine_is_ti5472() (0) +#endif + +#ifdef CONFIG_ARCH_AUTCPU12 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AUTCPU12 +# endif +# define machine_is_autcpu12() (machine_arch_type == MACH_TYPE_AUTCPU12) +#else +# define machine_is_autcpu12() (0) +#endif + +#ifdef CONFIG_ARCH_UENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UENGINE +# endif +# define machine_is_uengine() (machine_arch_type == MACH_TYPE_UENGINE) +#else +# define machine_is_uengine() (0) +#endif + +#ifdef CONFIG_SA1100_BLUESTEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUESTEM +# endif +# define machine_is_bluestem() (machine_arch_type == MACH_TYPE_BLUESTEM) +#else +# define machine_is_bluestem() (0) +#endif + +#ifdef CONFIG_ARCH_XINGU8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XINGU8 +# endif +# define machine_is_xingu8() (machine_arch_type == MACH_TYPE_XINGU8) +#else +# define machine_is_xingu8() (0) +#endif + +#ifdef CONFIG_ARCH_BUSHSTB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUSHSTB +# endif +# define machine_is_bushstb() (machine_arch_type == MACH_TYPE_BUSHSTB) +#else +# define machine_is_bushstb() (0) +#endif + +#ifdef CONFIG_SA1100_EPSILON1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPSILON1 +# endif +# define machine_is_epsilon1() (machine_arch_type == MACH_TYPE_EPSILON1) +#else +# define machine_is_epsilon1() (0) +#endif + +#ifdef CONFIG_SA1100_BALLOON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BALLOON +# endif +# define machine_is_balloon() (machine_arch_type == MACH_TYPE_BALLOON) +#else +# define machine_is_balloon() (0) +#endif + +#ifdef CONFIG_ARCH_PUPPY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PUPPY +# endif +# define machine_is_puppy() (machine_arch_type == MACH_TYPE_PUPPY) +#else +# define machine_is_puppy() (0) +#endif + +#ifdef CONFIG_SA1100_ELROY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELROY +# endif +# define machine_is_elroy() (machine_arch_type == MACH_TYPE_ELROY) +#else +# define machine_is_elroy() (0) +#endif + +#ifdef CONFIG_ARCH_GMS720 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GMS720 +# endif +# define machine_is_gms720() (machine_arch_type == MACH_TYPE_GMS720) +#else +# define machine_is_gms720() (0) +#endif + +#ifdef CONFIG_ARCH_S24X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S24X +# endif +# define machine_is_s24x() (machine_arch_type == MACH_TYPE_S24X) +#else +# define machine_is_s24x() (0) +#endif + +#ifdef CONFIG_ARCH_JTEL_CLEP7312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JTEL_CLEP7312 +# endif +# define machine_is_jtel_clep7312() (machine_arch_type == MACH_TYPE_JTEL_CLEP7312) +#else +# define machine_is_jtel_clep7312() (0) +#endif + +#ifdef CONFIG_ARCH_CX821XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CX821XX +# endif +# define machine_is_cx821xx() (machine_arch_type == MACH_TYPE_CX821XX) +#else +# define machine_is_cx821xx() (0) +#endif + +#ifdef CONFIG_ARCH_EDB7312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB7312 +# endif +# define machine_is_edb7312() (machine_arch_type == MACH_TYPE_EDB7312) +#else +# define machine_is_edb7312() (0) +#endif + +#ifdef CONFIG_SA1100_BSA1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSA1110 +# endif +# define machine_is_bsa1110() (machine_arch_type == MACH_TYPE_BSA1110) +#else +# define machine_is_bsa1110() (0) +#endif + +#ifdef CONFIG_ARCH_POWERPIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POWERPIN +# endif +# define machine_is_powerpin() (machine_arch_type == MACH_TYPE_POWERPIN) +#else +# define machine_is_powerpin() (0) +#endif + +#ifdef CONFIG_ARCH_OPENARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENARM +# endif +# define machine_is_openarm() (machine_arch_type == MACH_TYPE_OPENARM) +#else +# define machine_is_openarm() (0) +#endif + +#ifdef CONFIG_SA1100_WHITECHAPEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITECHAPEL +# endif +# define machine_is_whitechapel() (machine_arch_type == MACH_TYPE_WHITECHAPEL) +#else +# define machine_is_whitechapel() (0) +#endif + +#ifdef CONFIG_SA1100_H3100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H3100 +# endif +# define machine_is_h3100() (machine_arch_type == MACH_TYPE_H3100) +#else +# define machine_is_h3100() (0) +#endif + +#ifdef CONFIG_SA1100_H3800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H3800 +# endif +# define machine_is_h3800() (machine_arch_type == MACH_TYPE_H3800) +#else +# define machine_is_h3800() (0) +#endif + +#ifdef CONFIG_ARCH_BLUE_V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUE_V1 +# endif +# define machine_is_blue_v1() (machine_arch_type == MACH_TYPE_BLUE_V1) +#else +# define machine_is_blue_v1() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_CERF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_CERF +# endif +# define machine_is_pxa_cerf() (machine_arch_type == MACH_TYPE_PXA_CERF) +#else +# define machine_is_pxa_cerf() (0) +#endif + +#ifdef CONFIG_ARCH_ARM7TEVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM7TEVB +# endif +# define machine_is_arm7tevb() (machine_arch_type == MACH_TYPE_ARM7TEVB) +#else +# define machine_is_arm7tevb() (0) +#endif + +#ifdef CONFIG_SA1100_D7400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D7400 +# endif +# define machine_is_d7400() (machine_arch_type == MACH_TYPE_D7400) +#else +# define machine_is_d7400() (0) +#endif + +#ifdef CONFIG_ARCH_PIRANHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PIRANHA +# endif +# define machine_is_piranha() (machine_arch_type == MACH_TYPE_PIRANHA) +#else +# define machine_is_piranha() (0) +#endif + +#ifdef CONFIG_SA1100_SBCAMELOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBCAMELOT +# endif +# define machine_is_sbcamelot() (machine_arch_type == MACH_TYPE_SBCAMELOT) +#else +# define machine_is_sbcamelot() (0) +#endif + +#ifdef CONFIG_SA1100_KINGS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KINGS +# endif +# define machine_is_kings() (machine_arch_type == MACH_TYPE_KINGS) +#else +# define machine_is_kings() (0) +#endif + +#ifdef CONFIG_ARCH_SMDK2400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2400 +# endif +# define machine_is_smdk2400() (machine_arch_type == MACH_TYPE_SMDK2400) +#else +# define machine_is_smdk2400() (0) +#endif + +#ifdef CONFIG_SA1100_COLLIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLLIE +# endif +# define machine_is_collie() (machine_arch_type == MACH_TYPE_COLLIE) +#else +# define machine_is_collie() (0) +#endif + +#ifdef CONFIG_ARCH_IDR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IDR +# endif +# define machine_is_idr() (machine_arch_type == MACH_TYPE_IDR) +#else +# define machine_is_idr() (0) +#endif + +#ifdef CONFIG_SA1100_BADGE4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BADGE4 +# endif +# define machine_is_badge4() (machine_arch_type == MACH_TYPE_BADGE4) +#else +# define machine_is_badge4() (0) +#endif + +#ifdef CONFIG_ARCH_WEBNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEBNET +# endif +# define machine_is_webnet() (machine_arch_type == MACH_TYPE_WEBNET) +#else +# define machine_is_webnet() (0) +#endif + +#ifdef CONFIG_SA1100_D7300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D7300 +# endif +# define machine_is_d7300() (machine_arch_type == MACH_TYPE_D7300) +#else +# define machine_is_d7300() (0) +#endif + +#ifdef CONFIG_SA1100_CEP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEP +# endif +# define machine_is_cep() (machine_arch_type == MACH_TYPE_CEP) +#else +# define machine_is_cep() (0) +#endif + +#ifdef CONFIG_ARCH_FORTUNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FORTUNET +# endif +# define machine_is_fortunet() (machine_arch_type == MACH_TYPE_FORTUNET) +#else +# define machine_is_fortunet() (0) +#endif + +#ifdef CONFIG_ARCH_VC547X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC547X +# endif +# define machine_is_vc547x() (machine_arch_type == MACH_TYPE_VC547X) +#else +# define machine_is_vc547x() (0) +#endif + +#ifdef CONFIG_SA1100_FILEWALKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FILEWALKER +# endif +# define machine_is_filewalker() (machine_arch_type == MACH_TYPE_FILEWALKER) +#else +# define machine_is_filewalker() (0) +#endif + +#ifdef CONFIG_SA1100_NETGATEWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETGATEWAY +# endif +# define machine_is_netgateway() (machine_arch_type == MACH_TYPE_NETGATEWAY) +#else +# define machine_is_netgateway() (0) +#endif + +#ifdef CONFIG_SA1100_SYMBOL2800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYMBOL2800 +# endif +# define machine_is_symbol2800() (machine_arch_type == MACH_TYPE_SYMBOL2800) +#else +# define machine_is_symbol2800() (0) +#endif + +#ifdef CONFIG_SA1100_SUNS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUNS +# endif +# define machine_is_suns() (machine_arch_type == MACH_TYPE_SUNS) +#else +# define machine_is_suns() (0) +#endif + +#ifdef CONFIG_SA1100_FRODO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FRODO +# endif +# define machine_is_frodo() (machine_arch_type == MACH_TYPE_FRODO) +#else +# define machine_is_frodo() (0) +#endif + +#ifdef CONFIG_SA1100_MACH_TYTE_MS301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MACH_TYTE_MS301 +# endif +# define machine_is_ms301() (machine_arch_type == MACH_TYPE_MACH_TYTE_MS301) +#else +# define machine_is_ms301() (0) +#endif + +#ifdef CONFIG_ARCH_MX1ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX1ADS +# endif +# define machine_is_mx1ads() (machine_arch_type == MACH_TYPE_MX1ADS) +#else +# define machine_is_mx1ads() (0) +#endif + +#ifdef CONFIG_ARCH_H7201 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H7201 +# endif +# define machine_is_h7201() (machine_arch_type == MACH_TYPE_H7201) +#else +# define machine_is_h7201() (0) +#endif + +#ifdef CONFIG_ARCH_H7202 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H7202 +# endif +# define machine_is_h7202() (machine_arch_type == MACH_TYPE_H7202) +#else +# define machine_is_h7202() (0) +#endif + +#ifdef CONFIG_ARCH_AMICO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AMICO +# endif +# define machine_is_amico() (machine_arch_type == MACH_TYPE_AMICO) +#else +# define machine_is_amico() (0) +#endif + +#ifdef CONFIG_SA1100_IAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IAM +# endif +# define machine_is_iam() (machine_arch_type == MACH_TYPE_IAM) +#else +# define machine_is_iam() (0) +#endif + +#ifdef CONFIG_SA1100_TT530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TT530 +# endif +# define machine_is_tt530() (machine_arch_type == MACH_TYPE_TT530) +#else +# define machine_is_tt530() (0) +#endif + +#ifdef CONFIG_ARCH_SAM2400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAM2400 +# endif +# define machine_is_sam2400() (machine_arch_type == MACH_TYPE_SAM2400) +#else +# define machine_is_sam2400() (0) +#endif + +#ifdef CONFIG_SA1100_JORNADA56X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JORNADA56X +# endif +# define machine_is_jornada56x() (machine_arch_type == MACH_TYPE_JORNADA56X) +#else +# define machine_is_jornada56x() (0) +#endif + +#ifdef CONFIG_SA1100_ACTIVE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTIVE +# endif +# define machine_is_active() (machine_arch_type == MACH_TYPE_ACTIVE) +#else +# define machine_is_active() (0) +#endif + +#ifdef CONFIG_ARCH_IQ80321 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80321 +# endif +# define machine_is_iq80321() (machine_arch_type == MACH_TYPE_IQ80321) +#else +# define machine_is_iq80321() (0) +#endif + +#ifdef CONFIG_SA1100_WID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WID +# endif +# define machine_is_wid() (machine_arch_type == MACH_TYPE_WID) +#else +# define machine_is_wid() (0) +#endif + +#ifdef CONFIG_ARCH_SABINAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SABINAL +# endif +# define machine_is_sabinal() (machine_arch_type == MACH_TYPE_SABINAL) +#else +# define machine_is_sabinal() (0) +#endif + +#ifdef CONFIG_ARCH_IXP425_MATACUMBE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP425_MATACUMBE +# endif +# define machine_is_ixp425_matacumbe() (machine_arch_type == MACH_TYPE_IXP425_MATACUMBE) +#else +# define machine_is_ixp425_matacumbe() (0) +#endif + +#ifdef CONFIG_SA1100_MINIPRINT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINIPRINT +# endif +# define machine_is_miniprint() (machine_arch_type == MACH_TYPE_MINIPRINT) +#else +# define machine_is_miniprint() (0) +#endif + +#ifdef CONFIG_ARCH_ADM510X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADM510X +# endif +# define machine_is_adm510x() (machine_arch_type == MACH_TYPE_ADM510X) +#else +# define machine_is_adm510x() (0) +#endif + +#ifdef CONFIG_SA1100_SVS200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVS200 +# endif +# define machine_is_svs200() (machine_arch_type == MACH_TYPE_SVS200) +#else +# define machine_is_svs200() (0) +#endif + +#ifdef CONFIG_ARCH_ATG_TCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATG_TCU +# endif +# define machine_is_atg_tcu() (machine_arch_type == MACH_TYPE_ATG_TCU) +#else +# define machine_is_atg_tcu() (0) +#endif + +#ifdef CONFIG_SA1100_JORNADA820 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JORNADA820 +# endif +# define machine_is_jornada820() (machine_arch_type == MACH_TYPE_JORNADA820) +#else +# define machine_is_jornada820() (0) +#endif + +#ifdef CONFIG_ARCH_S3C44B0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C44B0 +# endif +# define machine_is_s3c44b0() (machine_arch_type == MACH_TYPE_S3C44B0) +#else +# define machine_is_s3c44b0() (0) +#endif + +#ifdef CONFIG_ARCH_MARGIS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARGIS2 +# endif +# define machine_is_margis2() (machine_arch_type == MACH_TYPE_MARGIS2) +#else +# define machine_is_margis2() (0) +#endif + +#ifdef CONFIG_ARCH_KS8695 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KS8695 +# endif +# define machine_is_ks8695() (machine_arch_type == MACH_TYPE_KS8695) +#else +# define machine_is_ks8695() (0) +#endif + +#ifdef CONFIG_ARCH_BRH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRH +# endif +# define machine_is_brh() (machine_arch_type == MACH_TYPE_BRH) +#else +# define machine_is_brh() (0) +#endif + +#ifdef CONFIG_ARCH_S3C2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2410 +# endif +# define machine_is_s3c2410() (machine_arch_type == MACH_TYPE_S3C2410) +#else +# define machine_is_s3c2410() (0) +#endif + +#ifdef CONFIG_ARCH_POSSIO_PX30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POSSIO_PX30 +# endif +# define machine_is_possio_px30() (machine_arch_type == MACH_TYPE_POSSIO_PX30) +#else +# define machine_is_possio_px30() (0) +#endif + +#ifdef CONFIG_ARCH_S3C2800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2800 +# endif +# define machine_is_s3c2800() (machine_arch_type == MACH_TYPE_S3C2800) +#else +# define machine_is_s3c2800() (0) +#endif + +#ifdef CONFIG_SA1100_FLEETWOOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLEETWOOD +# endif +# define machine_is_fleetwood() (machine_arch_type == MACH_TYPE_FLEETWOOD) +#else +# define machine_is_fleetwood() (0) +#endif + +#ifdef CONFIG_ARCH_OMAHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAHA +# endif +# define machine_is_omaha() (machine_arch_type == MACH_TYPE_OMAHA) +#else +# define machine_is_omaha() (0) +#endif + +#ifdef CONFIG_ARCH_TA7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TA7 +# endif +# define machine_is_ta7() (machine_arch_type == MACH_TYPE_TA7) +#else +# define machine_is_ta7() (0) +#endif + +#ifdef CONFIG_SA1100_NOVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOVA +# endif +# define machine_is_nova() (machine_arch_type == MACH_TYPE_NOVA) +#else +# define machine_is_nova() (0) +#endif + +#ifdef CONFIG_ARCH_HMK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMK +# endif +# define machine_is_hmk() (machine_arch_type == MACH_TYPE_HMK) +#else +# define machine_is_hmk() (0) +#endif + +#ifdef CONFIG_ARCH_KARO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KARO +# endif +# define machine_is_karo() (machine_arch_type == MACH_TYPE_KARO) +#else +# define machine_is_karo() (0) +#endif + +#ifdef CONFIG_SA1100_FESTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FESTER +# endif +# define machine_is_fester() (machine_arch_type == MACH_TYPE_FESTER) +#else +# define machine_is_fester() (0) +#endif + +#ifdef CONFIG_ARCH_GPI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GPI +# endif +# define machine_is_gpi() (machine_arch_type == MACH_TYPE_GPI) +#else +# define machine_is_gpi() (0) +#endif + +#ifdef CONFIG_ARCH_SMDK2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2410 +# endif +# define machine_is_smdk2410() (machine_arch_type == MACH_TYPE_SMDK2410) +#else +# define machine_is_smdk2410() (0) +#endif + +#ifdef CONFIG_ARCH_I519 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I519 +# endif +# define machine_is_i519() (machine_arch_type == MACH_TYPE_I519) +#else +# define machine_is_i519() (0) +#endif + +#ifdef CONFIG_SA1100_NEXIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXIO +# endif +# define machine_is_nexio() (machine_arch_type == MACH_TYPE_NEXIO) +#else +# define machine_is_nexio() (0) +#endif + +#ifdef CONFIG_SA1100_BITBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BITBOX +# endif +# define machine_is_bitbox() (machine_arch_type == MACH_TYPE_BITBOX) +#else +# define machine_is_bitbox() (0) +#endif + +#ifdef CONFIG_SA1100_G200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G200 +# endif +# define machine_is_g200() (machine_arch_type == MACH_TYPE_G200) +#else +# define machine_is_g200() (0) +#endif + +#ifdef CONFIG_SA1100_GILL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GILL +# endif +# define machine_is_gill() (machine_arch_type == MACH_TYPE_GILL) +#else +# define machine_is_gill() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_MERCURY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_MERCURY +# endif +# define machine_is_pxa_mercury() (machine_arch_type == MACH_TYPE_PXA_MERCURY) +#else +# define machine_is_pxa_mercury() (0) +#endif + +#ifdef CONFIG_ARCH_CEIVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEIVA +# endif +# define machine_is_ceiva() (machine_arch_type == MACH_TYPE_CEIVA) +#else +# define machine_is_ceiva() (0) +#endif + +#ifdef CONFIG_SA1100_FRET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FRET +# endif +# define machine_is_fret() (machine_arch_type == MACH_TYPE_FRET) +#else +# define machine_is_fret() (0) +#endif + +#ifdef CONFIG_SA1100_EMAILPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMAILPHONE +# endif +# define machine_is_emailphone() (machine_arch_type == MACH_TYPE_EMAILPHONE) +#else +# define machine_is_emailphone() (0) +#endif + +#ifdef CONFIG_ARCH_H3900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H3900 +# endif +# define machine_is_h3900() (machine_arch_type == MACH_TYPE_H3900) +#else +# define machine_is_h3900() (0) +#endif + +#ifdef CONFIG_ARCH_PXA1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA1 +# endif +# define machine_is_pxa1() (machine_arch_type == MACH_TYPE_PXA1) +#else +# define machine_is_pxa1() (0) +#endif + +#ifdef CONFIG_SA1100_KOAN369 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOAN369 +# endif +# define machine_is_koan369() (machine_arch_type == MACH_TYPE_KOAN369) +#else +# define machine_is_koan369() (0) +#endif + +#ifdef CONFIG_ARCH_COGENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COGENT +# endif +# define machine_is_cogent() (machine_arch_type == MACH_TYPE_COGENT) +#else +# define machine_is_cogent() (0) +#endif + +#ifdef CONFIG_ARCH_ESL_SIMPUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SIMPUTER +# endif +# define machine_is_esl_simputer() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER) +#else +# define machine_is_esl_simputer() (0) +#endif + +#ifdef CONFIG_ARCH_ESL_SIMPUTER_CLR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_CLR +# endif +# define machine_is_esl_simputer_clr() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_CLR) +#else +# define machine_is_esl_simputer_clr() (0) +#endif + +#ifdef CONFIG_ARCH_ESL_SIMPUTER_BW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SIMPUTER_BW +# endif +# define machine_is_esl_simputer_bw() (machine_arch_type == MACH_TYPE_ESL_SIMPUTER_BW) +#else +# define machine_is_esl_simputer_bw() (0) +#endif + +#ifdef CONFIG_ARCH_HHP_CRADLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HHP_CRADLE +# endif +# define machine_is_hhp_cradle() (machine_arch_type == MACH_TYPE_HHP_CRADLE) +#else +# define machine_is_hhp_cradle() (0) +#endif + +#ifdef CONFIG_ARCH_HE500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HE500 +# endif +# define machine_is_he500() (machine_arch_type == MACH_TYPE_HE500) +#else +# define machine_is_he500() (0) +#endif + +#ifdef CONFIG_SA1100_INHANDELF2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHANDELF2 +# endif +# define machine_is_inhandelf2() (machine_arch_type == MACH_TYPE_INHANDELF2) +#else +# define machine_is_inhandelf2() (0) +#endif + +#ifdef CONFIG_SA1100_INHANDFTIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHANDFTIP +# endif +# define machine_is_inhandftip() (machine_arch_type == MACH_TYPE_INHANDFTIP) +#else +# define machine_is_inhandftip() (0) +#endif + +#ifdef CONFIG_SA1100_DNP1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DNP1110 +# endif +# define machine_is_dnp1110() (machine_arch_type == MACH_TYPE_DNP1110) +#else +# define machine_is_dnp1110() (0) +#endif + +#ifdef CONFIG_SA1100_PNP1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNP1110 +# endif +# define machine_is_pnp1110() (machine_arch_type == MACH_TYPE_PNP1110) +#else +# define machine_is_pnp1110() (0) +#endif + +#ifdef CONFIG_ARCH_CSB226 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB226 +# endif +# define machine_is_csb226() (machine_arch_type == MACH_TYPE_CSB226) +#else +# define machine_is_csb226() (0) +#endif + +#ifdef CONFIG_SA1100_ARNOLD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARNOLD +# endif +# define machine_is_arnold() (machine_arch_type == MACH_TYPE_ARNOLD) +#else +# define machine_is_arnold() (0) +#endif + +#ifdef CONFIG_MACH_VOICEBLUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VOICEBLUE +# endif +# define machine_is_voiceblue() (machine_arch_type == MACH_TYPE_VOICEBLUE) +#else +# define machine_is_voiceblue() (0) +#endif + +#ifdef CONFIG_ARCH_JZ8028 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JZ8028 +# endif +# define machine_is_jz8028() (machine_arch_type == MACH_TYPE_JZ8028) +#else +# define machine_is_jz8028() (0) +#endif + +#ifdef CONFIG_ARCH_H5400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H5400 +# endif +# define machine_is_h5400() (machine_arch_type == MACH_TYPE_H5400) +#else +# define machine_is_h5400() (0) +#endif + +#ifdef CONFIG_SA1100_FORTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FORTE +# endif +# define machine_is_forte() (machine_arch_type == MACH_TYPE_FORTE) +#else +# define machine_is_forte() (0) +#endif + +#ifdef CONFIG_SA1100_ACAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACAM +# endif +# define machine_is_acam() (machine_arch_type == MACH_TYPE_ACAM) +#else +# define machine_is_acam() (0) +#endif + +#ifdef CONFIG_SA1100_ABOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ABOX +# endif +# define machine_is_abox() (machine_arch_type == MACH_TYPE_ABOX) +#else +# define machine_is_abox() (0) +#endif + +#ifdef CONFIG_ARCH_ATMEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATMEL +# endif +# define machine_is_atmel() (machine_arch_type == MACH_TYPE_ATMEL) +#else +# define machine_is_atmel() (0) +#endif + +#ifdef CONFIG_ARCH_SITSANG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SITSANG +# endif +# define machine_is_sitsang() (machine_arch_type == MACH_TYPE_SITSANG) +#else +# define machine_is_sitsang() (0) +#endif + +#ifdef CONFIG_SA1100_CPU1110LCDNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPU1110LCDNET +# endif +# define machine_is_cpu1110lcdnet() (machine_arch_type == MACH_TYPE_CPU1110LCDNET) +#else +# define machine_is_cpu1110lcdnet() (0) +#endif + +#ifdef CONFIG_ARCH_MPL_VCMA9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPL_VCMA9 +# endif +# define machine_is_mpl_vcma9() (machine_arch_type == MACH_TYPE_MPL_VCMA9) +#else +# define machine_is_mpl_vcma9() (0) +#endif + +#ifdef CONFIG_ARCH_OPUS_A1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPUS_A1 +# endif +# define machine_is_opus_a1() (machine_arch_type == MACH_TYPE_OPUS_A1) +#else +# define machine_is_opus_a1() (0) +#endif + +#ifdef CONFIG_ARCH_DAYTONA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAYTONA +# endif +# define machine_is_daytona() (machine_arch_type == MACH_TYPE_DAYTONA) +#else +# define machine_is_daytona() (0) +#endif + +#ifdef CONFIG_SA1100_KILLBEAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KILLBEAR +# endif +# define machine_is_killbear() (machine_arch_type == MACH_TYPE_KILLBEAR) +#else +# define machine_is_killbear() (0) +#endif + +#ifdef CONFIG_ARCH_YOHO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YOHO +# endif +# define machine_is_yoho() (machine_arch_type == MACH_TYPE_YOHO) +#else +# define machine_is_yoho() (0) +#endif + +#ifdef CONFIG_ARCH_JASPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JASPER +# endif +# define machine_is_jasper() (machine_arch_type == MACH_TYPE_JASPER) +#else +# define machine_is_jasper() (0) +#endif + +#ifdef CONFIG_ARCH_DSC25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSC25 +# endif +# define machine_is_dsc25() (machine_arch_type == MACH_TYPE_DSC25) +#else +# define machine_is_dsc25() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_INNOVATOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_INNOVATOR +# endif +# define machine_is_omap_innovator() (machine_arch_type == MACH_TYPE_OMAP_INNOVATOR) +#else +# define machine_is_omap_innovator() (0) +#endif + +#ifdef CONFIG_ARCH_RAMSES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAMSES +# endif +# define machine_is_ramses() (machine_arch_type == MACH_TYPE_RAMSES) +#else +# define machine_is_ramses() (0) +#endif + +#ifdef CONFIG_ARCH_S28X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S28X +# endif +# define machine_is_s28x() (machine_arch_type == MACH_TYPE_S28X) +#else +# define machine_is_s28x() (0) +#endif + +#ifdef CONFIG_ARCH_MPORT3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPORT3 +# endif +# define machine_is_mport3() (machine_arch_type == MACH_TYPE_MPORT3) +#else +# define machine_is_mport3() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_EAGLE250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_EAGLE250 +# endif +# define machine_is_pxa_eagle250() (machine_arch_type == MACH_TYPE_PXA_EAGLE250) +#else +# define machine_is_pxa_eagle250() (0) +#endif + +#ifdef CONFIG_ARCH_PDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PDB +# endif +# define machine_is_pdb() (machine_arch_type == MACH_TYPE_PDB) +#else +# define machine_is_pdb() (0) +#endif + +#ifdef CONFIG_SA1100_BLUE_2G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUE_2G +# endif +# define machine_is_blue_2g() (machine_arch_type == MACH_TYPE_BLUE_2G) +#else +# define machine_is_blue_2g() (0) +#endif + +#ifdef CONFIG_SA1100_BLUEARCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUEARCH +# endif +# define machine_is_bluearch() (machine_arch_type == MACH_TYPE_BLUEARCH) +#else +# define machine_is_bluearch() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP2400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2400 +# endif +# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDP2400) +#else +# define machine_is_ixdp2400() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP2800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2800 +# endif +# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDP2800) +#else +# define machine_is_ixdp2800() (0) +#endif + +#ifdef CONFIG_SA1100_EXPLORER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXPLORER +# endif +# define machine_is_explorer() (machine_arch_type == MACH_TYPE_EXPLORER) +#else +# define machine_is_explorer() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP425 +# endif +# define machine_is_ixdp425() (machine_arch_type == MACH_TYPE_IXDP425) +#else +# define machine_is_ixdp425() (0) +#endif + +#ifdef CONFIG_ARCH_CHIMP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHIMP +# endif +# define machine_is_chimp() (machine_arch_type == MACH_TYPE_CHIMP) +#else +# define machine_is_chimp() (0) +#endif + +#ifdef CONFIG_ARCH_STORK_NEST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STORK_NEST +# endif +# define machine_is_stork_nest() (machine_arch_type == MACH_TYPE_STORK_NEST) +#else +# define machine_is_stork_nest() (0) +#endif + +#ifdef CONFIG_ARCH_STORK_EGG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STORK_EGG +# endif +# define machine_is_stork_egg() (machine_arch_type == MACH_TYPE_STORK_EGG) +#else +# define machine_is_stork_egg() (0) +#endif + +#ifdef CONFIG_SA1100_WISMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WISMO +# endif +# define machine_is_wismo() (machine_arch_type == MACH_TYPE_WISMO) +#else +# define machine_is_wismo() (0) +#endif + +#ifdef CONFIG_ARCH_EZLINX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZLINX +# endif +# define machine_is_ezlinx() (machine_arch_type == MACH_TYPE_EZLINX) +#else +# define machine_is_ezlinx() (0) +#endif + +#ifdef CONFIG_ARCH_AT91RM9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200 +# endif +# define machine_is_at91rm9200() (machine_arch_type == MACH_TYPE_AT91RM9200) +#else +# define machine_is_at91rm9200() (0) +#endif + +#ifdef CONFIG_ARCH_ORION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORION +# endif +# define machine_is_orion() (machine_arch_type == MACH_TYPE_ORION) +#else +# define machine_is_orion() (0) +#endif + +#ifdef CONFIG_ARCH_NEPTUNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEPTUNE +# endif +# define machine_is_neptune() (machine_arch_type == MACH_TYPE_NEPTUNE) +#else +# define machine_is_neptune() (0) +#endif + +#ifdef CONFIG_SA1100_HACKKIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HACKKIT +# endif +# define machine_is_hackkit() (machine_arch_type == MACH_TYPE_HACKKIT) +#else +# define machine_is_hackkit() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_WINS30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_WINS30 +# endif +# define machine_is_pxa_wins30() (machine_arch_type == MACH_TYPE_PXA_WINS30) +#else +# define machine_is_pxa_wins30() (0) +#endif + +#ifdef CONFIG_SA1100_LAVINNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LAVINNA +# endif +# define machine_is_lavinna() (machine_arch_type == MACH_TYPE_LAVINNA) +#else +# define machine_is_lavinna() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_UENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_UENGINE +# endif +# define machine_is_pxa_uengine() (machine_arch_type == MACH_TYPE_PXA_UENGINE) +#else +# define machine_is_pxa_uengine() (0) +#endif + +#ifdef CONFIG_ARCH_INNOKOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INNOKOM +# endif +# define machine_is_innokom() (machine_arch_type == MACH_TYPE_INNOKOM) +#else +# define machine_is_innokom() (0) +#endif + +#ifdef CONFIG_ARCH_BMS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BMS +# endif +# define machine_is_bms() (machine_arch_type == MACH_TYPE_BMS) +#else +# define machine_is_bms() (0) +#endif + +#ifdef CONFIG_ARCH_IXCDP1100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXCDP1100 +# endif +# define machine_is_ixcdp1100() (machine_arch_type == MACH_TYPE_IXCDP1100) +#else +# define machine_is_ixcdp1100() (0) +#endif + +#ifdef CONFIG_ARCH_PRPMC1100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRPMC1100 +# endif +# define machine_is_prpmc1100() (machine_arch_type == MACH_TYPE_PRPMC1100) +#else +# define machine_is_prpmc1100() (0) +#endif + +#ifdef CONFIG_ARCH_AT91RM9200DK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200DK +# endif +# define machine_is_at91rm9200dk() (machine_arch_type == MACH_TYPE_AT91RM9200DK) +#else +# define machine_is_at91rm9200dk() (0) +#endif + +#ifdef CONFIG_ARCH_ARMSTICK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMSTICK +# endif +# define machine_is_armstick() (machine_arch_type == MACH_TYPE_ARMSTICK) +#else +# define machine_is_armstick() (0) +#endif + +#ifdef CONFIG_ARCH_ARMONIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMONIE +# endif +# define machine_is_armonie() (machine_arch_type == MACH_TYPE_ARMONIE) +#else +# define machine_is_armonie() (0) +#endif + +#ifdef CONFIG_ARCH_MPORT1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPORT1 +# endif +# define machine_is_mport1() (machine_arch_type == MACH_TYPE_MPORT1) +#else +# define machine_is_mport1() (0) +#endif + +#ifdef CONFIG_ARCH_S3C5410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C5410 +# endif +# define machine_is_s3c5410() (machine_arch_type == MACH_TYPE_S3C5410) +#else +# define machine_is_s3c5410() (0) +#endif + +#ifdef CONFIG_ARCH_ZCP320A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZCP320A +# endif +# define machine_is_zcp320a() (machine_arch_type == MACH_TYPE_ZCP320A) +#else +# define machine_is_zcp320a() (0) +#endif + +#ifdef CONFIG_ARCH_I_BOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I_BOX +# endif +# define machine_is_i_box() (machine_arch_type == MACH_TYPE_I_BOX) +#else +# define machine_is_i_box() (0) +#endif + +#ifdef CONFIG_ARCH_STLC1502 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STLC1502 +# endif +# define machine_is_stlc1502() (machine_arch_type == MACH_TYPE_STLC1502) +#else +# define machine_is_stlc1502() (0) +#endif + +#ifdef CONFIG_ARCH_SIREN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIREN +# endif +# define machine_is_siren() (machine_arch_type == MACH_TYPE_SIREN) +#else +# define machine_is_siren() (0) +#endif + +#ifdef CONFIG_ARCH_GREENLAKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GREENLAKE +# endif +# define machine_is_greenlake() (machine_arch_type == MACH_TYPE_GREENLAKE) +#else +# define machine_is_greenlake() (0) +#endif + +#ifdef CONFIG_ARCH_ARGUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARGUS +# endif +# define machine_is_argus() (machine_arch_type == MACH_TYPE_ARGUS) +#else +# define machine_is_argus() (0) +#endif + +#ifdef CONFIG_SA1100_COMBADGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMBADGE +# endif +# define machine_is_combadge() (machine_arch_type == MACH_TYPE_COMBADGE) +#else +# define machine_is_combadge() (0) +#endif + +#ifdef CONFIG_ARCH_ROKEPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROKEPXA +# endif +# define machine_is_rokepxa() (machine_arch_type == MACH_TYPE_ROKEPXA) +#else +# define machine_is_rokepxa() (0) +#endif + +#ifdef CONFIG_ARCH_CINTEGRATOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CINTEGRATOR +# endif +# define machine_is_cintegrator() (machine_arch_type == MACH_TYPE_CINTEGRATOR) +#else +# define machine_is_cintegrator() (0) +#endif + +#ifdef CONFIG_ARCH_GUIDEA07 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUIDEA07 +# endif +# define machine_is_guidea07() (machine_arch_type == MACH_TYPE_GUIDEA07) +#else +# define machine_is_guidea07() (0) +#endif + +#ifdef CONFIG_ARCH_TAT257 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAT257 +# endif +# define machine_is_tat257() (machine_arch_type == MACH_TYPE_TAT257) +#else +# define machine_is_tat257() (0) +#endif + +#ifdef CONFIG_ARCH_IGP2425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGP2425 +# endif +# define machine_is_igp2425() (machine_arch_type == MACH_TYPE_IGP2425) +#else +# define machine_is_igp2425() (0) +#endif + +#ifdef CONFIG_ARCH_BLUEGRAMMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUEGRAMMA +# endif +# define machine_is_bluegrama() (machine_arch_type == MACH_TYPE_BLUEGRAMMA) +#else +# define machine_is_bluegrama() (0) +#endif + +#ifdef CONFIG_ARCH_IPOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPOD +# endif +# define machine_is_ipod() (machine_arch_type == MACH_TYPE_IPOD) +#else +# define machine_is_ipod() (0) +#endif + +#ifdef CONFIG_ARCH_ADSBITSYX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSYX +# endif +# define machine_is_adsbitsyx() (machine_arch_type == MACH_TYPE_ADSBITSYX) +#else +# define machine_is_adsbitsyx() (0) +#endif + +#ifdef CONFIG_ARCH_TRIZEPS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS2 +# endif +# define machine_is_trizeps2() (machine_arch_type == MACH_TYPE_TRIZEPS2) +#else +# define machine_is_trizeps2() (0) +#endif + +#ifdef CONFIG_ARCH_VIPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VIPER +# endif +# define machine_is_viper() (machine_arch_type == MACH_TYPE_VIPER) +#else +# define machine_is_viper() (0) +#endif + +#ifdef CONFIG_SA1100_ADSBITSYPLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSYPLUS +# endif +# define machine_is_adsbitsyplus() (machine_arch_type == MACH_TYPE_ADSBITSYPLUS) +#else +# define machine_is_adsbitsyplus() (0) +#endif + +#ifdef CONFIG_SA1100_ADSAGC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSAGC +# endif +# define machine_is_adsagc() (machine_arch_type == MACH_TYPE_ADSAGC) +#else +# define machine_is_adsagc() (0) +#endif + +#ifdef CONFIG_ARCH_STP7312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STP7312 +# endif +# define machine_is_stp7312() (machine_arch_type == MACH_TYPE_STP7312) +#else +# define machine_is_stp7312() (0) +#endif + +#ifdef CONFIG_MACH_NX_PHNX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NX_PHNX +# endif +# define machine_is_nx_phnx() (machine_arch_type == MACH_TYPE_NX_PHNX) +#else +# define machine_is_nx_phnx() (0) +#endif + +#ifdef CONFIG_ARCH_WEP_EP250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEP_EP250 +# endif +# define machine_is_wep_ep250() (machine_arch_type == MACH_TYPE_WEP_EP250) +#else +# define machine_is_wep_ep250() (0) +#endif + +#ifdef CONFIG_ARCH_INHANDELF3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHANDELF3 +# endif +# define machine_is_inhandelf3() (machine_arch_type == MACH_TYPE_INHANDELF3) +#else +# define machine_is_inhandelf3() (0) +#endif + +#ifdef CONFIG_ARCH_ADI_COYOTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADI_COYOTE +# endif +# define machine_is_adi_coyote() (machine_arch_type == MACH_TYPE_ADI_COYOTE) +#else +# define machine_is_adi_coyote() (0) +#endif + +#ifdef CONFIG_ARCH_IYONIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IYONIX +# endif +# define machine_is_iyonix() (machine_arch_type == MACH_TYPE_IYONIX) +#else +# define machine_is_iyonix() (0) +#endif + +#ifdef CONFIG_ARCH_DAMICAM_SA1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAMICAM_SA1110 +# endif +# define machine_is_damicam1() (machine_arch_type == MACH_TYPE_DAMICAM_SA1110) +#else +# define machine_is_damicam1() (0) +#endif + +#ifdef CONFIG_ARCH_MEG03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEG03 +# endif +# define machine_is_meg03() (machine_arch_type == MACH_TYPE_MEG03) +#else +# define machine_is_meg03() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_WHITECHAPEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_WHITECHAPEL +# endif +# define machine_is_pxa_whitechapel() (machine_arch_type == MACH_TYPE_PXA_WHITECHAPEL) +#else +# define machine_is_pxa_whitechapel() (0) +#endif + +#ifdef CONFIG_ARCH_NWSC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NWSC +# endif +# define machine_is_nwsc() (machine_arch_type == MACH_TYPE_NWSC) +#else +# define machine_is_nwsc() (0) +#endif + +#ifdef CONFIG_ARCH_NWLARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NWLARM +# endif +# define machine_is_nwlarm() (machine_arch_type == MACH_TYPE_NWLARM) +#else +# define machine_is_nwlarm() (0) +#endif + +#ifdef CONFIG_ARCH_IXP425_MGUARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP425_MGUARD +# endif +# define machine_is_ixp425_mguard() (machine_arch_type == MACH_TYPE_IXP425_MGUARD) +#else +# define machine_is_ixp425_mguard() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_NETDCU4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_NETDCU4 +# endif +# define machine_is_pxa_netdcu4() (machine_arch_type == MACH_TYPE_PXA_NETDCU4) +#else +# define machine_is_pxa_netdcu4() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP2401 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2401 +# endif +# define machine_is_ixdp2401() (machine_arch_type == MACH_TYPE_IXDP2401) +#else +# define machine_is_ixdp2401() (0) +#endif + +#ifdef CONFIG_ARCH_IXDP2801 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2801 +# endif +# define machine_is_ixdp2801() (machine_arch_type == MACH_TYPE_IXDP2801) +#else +# define machine_is_ixdp2801() (0) +#endif + +#ifdef CONFIG_ARCH_ZODIAC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZODIAC +# endif +# define machine_is_zodiac() (machine_arch_type == MACH_TYPE_ZODIAC) +#else +# define machine_is_zodiac() (0) +#endif + +#ifdef CONFIG_ARCH_ARMMODUL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMMODUL +# endif +# define machine_is_armmodul() (machine_arch_type == MACH_TYPE_ARMMODUL) +#else +# define machine_is_armmodul() (0) +#endif + +#ifdef CONFIG_SA1100_KETOP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KETOP +# endif +# define machine_is_ketop() (machine_arch_type == MACH_TYPE_KETOP) +#else +# define machine_is_ketop() (0) +#endif + +#ifdef CONFIG_ARCH_AV7200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AV7200 +# endif +# define machine_is_av7200() (machine_arch_type == MACH_TYPE_AV7200) +#else +# define machine_is_av7200() (0) +#endif + +#ifdef CONFIG_ARCH_ARCH_TI925 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCH_TI925 +# endif +# define machine_is_arch_ti925() (machine_arch_type == MACH_TYPE_ARCH_TI925) +#else +# define machine_is_arch_ti925() (0) +#endif + +#ifdef CONFIG_ARCH_ACQ200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACQ200 +# endif +# define machine_is_acq200() (machine_arch_type == MACH_TYPE_ACQ200) +#else +# define machine_is_acq200() (0) +#endif + +#ifdef CONFIG_SA1100_PT_DAFIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PT_DAFIT +# endif +# define machine_is_pt_dafit() (machine_arch_type == MACH_TYPE_PT_DAFIT) +#else +# define machine_is_pt_dafit() (0) +#endif + +#ifdef CONFIG_ARCH_IHBA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IHBA +# endif +# define machine_is_ihba() (machine_arch_type == MACH_TYPE_IHBA) +#else +# define machine_is_ihba() (0) +#endif + +#ifdef CONFIG_ARCH_QUINQUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUINQUE +# endif +# define machine_is_quinque() (machine_arch_type == MACH_TYPE_QUINQUE) +#else +# define machine_is_quinque() (0) +#endif + +#ifdef CONFIG_ARCH_NIMBRAONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMBRAONE +# endif +# define machine_is_nimbraone() (machine_arch_type == MACH_TYPE_NIMBRAONE) +#else +# define machine_is_nimbraone() (0) +#endif + +#ifdef CONFIG_ARCH_NIMBRA29X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMBRA29X +# endif +# define machine_is_nimbra29x() (machine_arch_type == MACH_TYPE_NIMBRA29X) +#else +# define machine_is_nimbra29x() (0) +#endif + +#ifdef CONFIG_ARCH_NIMBRA210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMBRA210 +# endif +# define machine_is_nimbra210() (machine_arch_type == MACH_TYPE_NIMBRA210) +#else +# define machine_is_nimbra210() (0) +#endif + +#ifdef CONFIG_ARCH_HHP_D95XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HHP_D95XX +# endif +# define machine_is_hhp_d95xx() (machine_arch_type == MACH_TYPE_HHP_D95XX) +#else +# define machine_is_hhp_d95xx() (0) +#endif + +#ifdef CONFIG_ARCH_LABARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LABARM +# endif +# define machine_is_labarm() (machine_arch_type == MACH_TYPE_LABARM) +#else +# define machine_is_labarm() (0) +#endif + +#ifdef CONFIG_ARCH_M825XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M825XX +# endif +# define machine_is_m825xx() (machine_arch_type == MACH_TYPE_M825XX) +#else +# define machine_is_m825xx() (0) +#endif + +#ifdef CONFIG_SA1100_M7100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M7100 +# endif +# define machine_is_m7100() (machine_arch_type == MACH_TYPE_M7100) +#else +# define machine_is_m7100() (0) +#endif + +#ifdef CONFIG_ARCH_NIPC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIPC2 +# endif +# define machine_is_nipc2() (machine_arch_type == MACH_TYPE_NIPC2) +#else +# define machine_is_nipc2() (0) +#endif + +#ifdef CONFIG_ARCH_FU7202 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FU7202 +# endif +# define machine_is_fu7202() (machine_arch_type == MACH_TYPE_FU7202) +#else +# define machine_is_fu7202() (0) +#endif + +#ifdef CONFIG_ARCH_ADSAGX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSAGX +# endif +# define machine_is_adsagx() (machine_arch_type == MACH_TYPE_ADSAGX) +#else +# define machine_is_adsagx() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_POOH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_POOH +# endif +# define machine_is_pxa_pooh() (machine_arch_type == MACH_TYPE_PXA_POOH) +#else +# define machine_is_pxa_pooh() (0) +#endif + +#ifdef CONFIG_ARCH_BANDON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BANDON +# endif +# define machine_is_bandon() (machine_arch_type == MACH_TYPE_BANDON) +#else +# define machine_is_bandon() (0) +#endif + +#ifdef CONFIG_ARCH_PCM7210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM7210 +# endif +# define machine_is_pcm7210() (machine_arch_type == MACH_TYPE_PCM7210) +#else +# define machine_is_pcm7210() (0) +#endif + +#ifdef CONFIG_ARCH_NMS9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NMS9200 +# endif +# define machine_is_nms9200() (machine_arch_type == MACH_TYPE_NMS9200) +#else +# define machine_is_nms9200() (0) +#endif + +#ifdef CONFIG_ARCH_LOGODL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOGODL +# endif +# define machine_is_logodl() (machine_arch_type == MACH_TYPE_LOGODL) +#else +# define machine_is_logodl() (0) +#endif + +#ifdef CONFIG_SA1100_M7140 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M7140 +# endif +# define machine_is_m7140() (machine_arch_type == MACH_TYPE_M7140) +#else +# define machine_is_m7140() (0) +#endif + +#ifdef CONFIG_ARCH_KOREBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOREBOT +# endif +# define machine_is_korebot() (machine_arch_type == MACH_TYPE_KOREBOT) +#else +# define machine_is_korebot() (0) +#endif + +#ifdef CONFIG_ARCH_IQ31244 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ31244 +# endif +# define machine_is_iq31244() (machine_arch_type == MACH_TYPE_IQ31244) +#else +# define machine_is_iq31244() (0) +#endif + +#ifdef CONFIG_SA1100_KOAN393 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOAN393 +# endif +# define machine_is_koan393() (machine_arch_type == MACH_TYPE_KOAN393) +#else +# define machine_is_koan393() (0) +#endif + +#ifdef CONFIG_ARCH_INHANDFTIP3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHANDFTIP3 +# endif +# define machine_is_inhandftip3() (machine_arch_type == MACH_TYPE_INHANDFTIP3) +#else +# define machine_is_inhandftip3() (0) +#endif + +#ifdef CONFIG_ARCH_GONZO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GONZO +# endif +# define machine_is_gonzo() (machine_arch_type == MACH_TYPE_GONZO) +#else +# define machine_is_gonzo() (0) +#endif + +#ifdef CONFIG_ARCH_BAST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BAST +# endif +# define machine_is_bast() (machine_arch_type == MACH_TYPE_BAST) +#else +# define machine_is_bast() (0) +#endif + +#ifdef CONFIG_ARCH_SCANPASS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCANPASS +# endif +# define machine_is_scanpass() (machine_arch_type == MACH_TYPE_SCANPASS) +#else +# define machine_is_scanpass() (0) +#endif + +#ifdef CONFIG_ARCH_EP7312_POOH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EP7312_POOH +# endif +# define machine_is_ep7312_pooh() (machine_arch_type == MACH_TYPE_EP7312_POOH) +#else +# define machine_is_ep7312_pooh() (0) +#endif + +#ifdef CONFIG_ARCH_TA7S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TA7S +# endif +# define machine_is_ta7s() (machine_arch_type == MACH_TYPE_TA7S) +#else +# define machine_is_ta7s() (0) +#endif + +#ifdef CONFIG_ARCH_TA7V +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TA7V +# endif +# define machine_is_ta7v() (machine_arch_type == MACH_TYPE_TA7V) +#else +# define machine_is_ta7v() (0) +#endif + +#ifdef CONFIG_SA1100_ICARUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICARUS +# endif +# define machine_is_icarus() (machine_arch_type == MACH_TYPE_ICARUS) +#else +# define machine_is_icarus() (0) +#endif + +#ifdef CONFIG_ARCH_H1900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H1900 +# endif +# define machine_is_h1900() (machine_arch_type == MACH_TYPE_H1900) +#else +# define machine_is_h1900() (0) +#endif + +#ifdef CONFIG_SA1100_GEMINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMINI +# endif +# define machine_is_gemini() (machine_arch_type == MACH_TYPE_GEMINI) +#else +# define machine_is_gemini() (0) +#endif + +#ifdef CONFIG_ARCH_AXIM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXIM +# endif +# define machine_is_axim() (machine_arch_type == MACH_TYPE_AXIM) +#else +# define machine_is_axim() (0) +#endif + +#ifdef CONFIG_ARCH_AUDIOTRON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AUDIOTRON +# endif +# define machine_is_audiotron() (machine_arch_type == MACH_TYPE_AUDIOTRON) +#else +# define machine_is_audiotron() (0) +#endif + +#ifdef CONFIG_ARCH_H2200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H2200 +# endif +# define machine_is_h2200() (machine_arch_type == MACH_TYPE_H2200) +#else +# define machine_is_h2200() (0) +#endif + +#ifdef CONFIG_ARCH_LOOX600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOX600 +# endif +# define machine_is_loox600() (machine_arch_type == MACH_TYPE_LOOX600) +#else +# define machine_is_loox600() (0) +#endif + +#ifdef CONFIG_ARCH_NIOP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIOP +# endif +# define machine_is_niop() (machine_arch_type == MACH_TYPE_NIOP) +#else +# define machine_is_niop() (0) +#endif + +#ifdef CONFIG_ARCH_DM310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM310 +# endif +# define machine_is_dm310() (machine_arch_type == MACH_TYPE_DM310) +#else +# define machine_is_dm310() (0) +#endif + +#ifdef CONFIG_ARCH_SEEDPXA_C2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SEEDPXA_C2 +# endif +# define machine_is_seedpxa_c2() (machine_arch_type == MACH_TYPE_SEEDPXA_C2) +#else +# define machine_is_seedpxa_c2() (0) +#endif + +#ifdef CONFIG_ARCH_IXP4XX_MGUARD_PCI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP4XX_MGUARD_PCI +# endif +# define machine_is_ixp4xx_mguardpci() (machine_arch_type == MACH_TYPE_IXP4XX_MGUARD_PCI) +#else +# define machine_is_ixp4xx_mguardpci() (0) +#endif + +#ifdef CONFIG_ARCH_H1940 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H1940 +# endif +# define machine_is_h1940() (machine_arch_type == MACH_TYPE_H1940) +#else +# define machine_is_h1940() (0) +#endif + +#ifdef CONFIG_ARCH_SCORPIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCORPIO +# endif +# define machine_is_scorpio() (machine_arch_type == MACH_TYPE_SCORPIO) +#else +# define machine_is_scorpio() (0) +#endif + +#ifdef CONFIG_ARCH_VIVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VIVA +# endif +# define machine_is_viva() (machine_arch_type == MACH_TYPE_VIVA) +#else +# define machine_is_viva() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_XCARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_XCARD +# endif +# define machine_is_pxa_xcard() (machine_arch_type == MACH_TYPE_PXA_XCARD) +#else +# define machine_is_pxa_xcard() (0) +#endif + +#ifdef CONFIG_ARCH_CSB335 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB335 +# endif +# define machine_is_csb335() (machine_arch_type == MACH_TYPE_CSB335) +#else +# define machine_is_csb335() (0) +#endif + +#ifdef CONFIG_ARCH_IXRD425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXRD425 +# endif +# define machine_is_ixrd425() (machine_arch_type == MACH_TYPE_IXRD425) +#else +# define machine_is_ixrd425() (0) +#endif + +#ifdef CONFIG_ARCH_IQ80315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80315 +# endif +# define machine_is_iq80315() (machine_arch_type == MACH_TYPE_IQ80315) +#else +# define machine_is_iq80315() (0) +#endif + +#ifdef CONFIG_ARCH_NMP7312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NMP7312 +# endif +# define machine_is_nmp7312() (machine_arch_type == MACH_TYPE_NMP7312) +#else +# define machine_is_nmp7312() (0) +#endif + +#ifdef CONFIG_ARCH_CX861XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CX861XX +# endif +# define machine_is_cx861xx() (machine_arch_type == MACH_TYPE_CX861XX) +#else +# define machine_is_cx861xx() (0) +#endif + +#ifdef CONFIG_ARCH_ENP2611 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENP2611 +# endif +# define machine_is_enp2611() (machine_arch_type == MACH_TYPE_ENP2611) +#else +# define machine_is_enp2611() (0) +#endif + +#ifdef CONFIG_SA1100_XDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XDA +# endif +# define machine_is_xda() (machine_arch_type == MACH_TYPE_XDA) +#else +# define machine_is_xda() (0) +#endif + +#ifdef CONFIG_ARCH_CSIR_IMS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSIR_IMS +# endif +# define machine_is_csir_ims() (machine_arch_type == MACH_TYPE_CSIR_IMS) +#else +# define machine_is_csir_ims() (0) +#endif + +#ifdef CONFIG_ARCH_IXP421_DNAEETH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP421_DNAEETH +# endif +# define machine_is_ixp421_dnaeeth() (machine_arch_type == MACH_TYPE_IXP421_DNAEETH) +#else +# define machine_is_ixp421_dnaeeth() (0) +#endif + +#ifdef CONFIG_ARCH_POCKETSERV9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POCKETSERV9200 +# endif +# define machine_is_pocketserv9200() (machine_arch_type == MACH_TYPE_POCKETSERV9200) +#else +# define machine_is_pocketserv9200() (0) +#endif + +#ifdef CONFIG_ARCH_TOTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOTO +# endif +# define machine_is_toto() (machine_arch_type == MACH_TYPE_TOTO) +#else +# define machine_is_toto() (0) +#endif + +#ifdef CONFIG_ARCH_S3C2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2440 +# endif +# define machine_is_s3c2440() (machine_arch_type == MACH_TYPE_S3C2440) +#else +# define machine_is_s3c2440() (0) +#endif + +#ifdef CONFIG_ARCH_KS8695P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KS8695P +# endif +# define machine_is_ks8695p() (machine_arch_type == MACH_TYPE_KS8695P) +#else +# define machine_is_ks8695p() (0) +#endif + +#ifdef CONFIG_ARCH_SE4000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SE4000 +# endif +# define machine_is_se4000() (machine_arch_type == MACH_TYPE_SE4000) +#else +# define machine_is_se4000() (0) +#endif + +#ifdef CONFIG_ARCH_QUADRICEPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUADRICEPS +# endif +# define machine_is_quadriceps() (machine_arch_type == MACH_TYPE_QUADRICEPS) +#else +# define machine_is_quadriceps() (0) +#endif + +#ifdef CONFIG_ARCH_BRONCO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRONCO +# endif +# define machine_is_bronco() (machine_arch_type == MACH_TYPE_BRONCO) +#else +# define machine_is_bronco() (0) +#endif + +#ifdef CONFIG_ARCH_ESL_SOFCOMP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SOFCOMP +# endif +# define machine_is_esl_sofcomp() (machine_arch_type == MACH_TYPE_ESL_SOFCOMP) +#else +# define machine_is_esl_sofcomp() (0) +#endif + +#ifdef CONFIG_ARCH_S5C7375 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5C7375 +# endif +# define machine_is_s5c7375() (machine_arch_type == MACH_TYPE_S5C7375) +#else +# define machine_is_s5c7375() (0) +#endif + +#ifdef CONFIG_ARCH_SPEARHEAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEARHEAD +# endif +# define machine_is_spearhead() (machine_arch_type == MACH_TYPE_SPEARHEAD) +#else +# define machine_is_spearhead() (0) +#endif + +#ifdef CONFIG_ARCH_PANTERA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PANTERA +# endif +# define machine_is_pantera() (machine_arch_type == MACH_TYPE_PANTERA) +#else +# define machine_is_pantera() (0) +#endif + +#ifdef CONFIG_ARCH_PRAYOGLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRAYOGLITE +# endif +# define machine_is_prayoglite() (machine_arch_type == MACH_TYPE_PRAYOGLITE) +#else +# define machine_is_prayoglite() (0) +#endif + +#ifdef CONFIG_ARCH_GUMSTIK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUMSTIK +# endif +# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIK) +#else +# define machine_is_gumstix() (0) +#endif + +#ifdef CONFIG_ARCH_RCUBE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RCUBE +# endif +# define machine_is_rcube() (machine_arch_type == MACH_TYPE_RCUBE) +#else +# define machine_is_rcube() (0) +#endif + +#ifdef CONFIG_ARCH_REA_OLV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REA_OLV +# endif +# define machine_is_rea_olv() (machine_arch_type == MACH_TYPE_REA_OLV) +#else +# define machine_is_rea_olv() (0) +#endif + +#ifdef CONFIG_ARCH_PXA_IPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_IPHONE +# endif +# define machine_is_pxa_iphone() (machine_arch_type == MACH_TYPE_PXA_IPHONE) +#else +# define machine_is_pxa_iphone() (0) +#endif + +#ifdef CONFIG_ARCH_S3C3410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C3410 +# endif +# define machine_is_s3c3410() (machine_arch_type == MACH_TYPE_S3C3410) +#else +# define machine_is_s3c3410() (0) +#endif + +#ifdef CONFIG_ARCH_ESPD_4510B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESPD_4510B +# endif +# define machine_is_espd_4510b() (machine_arch_type == MACH_TYPE_ESPD_4510B) +#else +# define machine_is_espd_4510b() (0) +#endif + +#ifdef CONFIG_ARCH_MP1X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP1X +# endif +# define machine_is_mp1x() (machine_arch_type == MACH_TYPE_MP1X) +#else +# define machine_is_mp1x() (0) +#endif + +#ifdef CONFIG_ARCH_AT91RM9200TB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200TB +# endif +# define machine_is_at91rm9200tb() (machine_arch_type == MACH_TYPE_AT91RM9200TB) +#else +# define machine_is_at91rm9200tb() (0) +#endif + +#ifdef CONFIG_ARCH_ADSVGX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSVGX +# endif +# define machine_is_adsvgx() (machine_arch_type == MACH_TYPE_ADSVGX) +#else +# define machine_is_adsvgx() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_H2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_H2 +# endif +# define machine_is_omap_h2() (machine_arch_type == MACH_TYPE_OMAP_H2) +#else +# define machine_is_omap_h2() (0) +#endif + +#ifdef CONFIG_ARCH_PELEE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELEE +# endif +# define machine_is_pelee() (machine_arch_type == MACH_TYPE_PELEE) +#else +# define machine_is_pelee() (0) +#endif + +#ifdef CONFIG_MACH_E740 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E740 +# endif +# define machine_is_e740() (machine_arch_type == MACH_TYPE_E740) +#else +# define machine_is_e740() (0) +#endif + +#ifdef CONFIG_ARCH_IQ80331 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80331 +# endif +# define machine_is_iq80331() (machine_arch_type == MACH_TYPE_IQ80331) +#else +# define machine_is_iq80331() (0) +#endif + +#ifdef CONFIG_ARCH_VERSATILE_PB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VERSATILE_PB +# endif +# define machine_is_versatile_pb() (machine_arch_type == MACH_TYPE_VERSATILE_PB) +#else +# define machine_is_versatile_pb() (0) +#endif + +#ifdef CONFIG_MACH_KEV7A400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KEV7A400 +# endif +# define machine_is_kev7a400() (machine_arch_type == MACH_TYPE_KEV7A400) +#else +# define machine_is_kev7a400() (0) +#endif + +#ifdef CONFIG_MACH_LPD7A400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD7A400 +# endif +# define machine_is_lpd7a400() (machine_arch_type == MACH_TYPE_LPD7A400) +#else +# define machine_is_lpd7a400() (0) +#endif + +#ifdef CONFIG_MACH_LPD7A404 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD7A404 +# endif +# define machine_is_lpd7a404() (machine_arch_type == MACH_TYPE_LPD7A404) +#else +# define machine_is_lpd7a404() (0) +#endif + +#ifdef CONFIG_ARCH_FUJITSU_CAMELOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_CAMELOT +# endif +# define machine_is_fujitsu_camelot() (machine_arch_type == MACH_TYPE_FUJITSU_CAMELOT) +#else +# define machine_is_fujitsu_camelot() (0) +#endif + +#ifdef CONFIG_ARCH_JANUS2M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JANUS2M +# endif +# define machine_is_janus2m() (machine_arch_type == MACH_TYPE_JANUS2M) +#else +# define machine_is_janus2m() (0) +#endif + +#ifdef CONFIG_MACH_EMBTF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMBTF +# endif +# define machine_is_embtf() (machine_arch_type == MACH_TYPE_EMBTF) +#else +# define machine_is_embtf() (0) +#endif + +#ifdef CONFIG_MACH_HPM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPM +# endif +# define machine_is_hpm() (machine_arch_type == MACH_TYPE_HPM) +#else +# define machine_is_hpm() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2410TK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2410TK +# endif +# define machine_is_smdk2410tk() (machine_arch_type == MACH_TYPE_SMDK2410TK) +#else +# define machine_is_smdk2410tk() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2410AJ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2410AJ +# endif +# define machine_is_smdk2410aj() (machine_arch_type == MACH_TYPE_SMDK2410AJ) +#else +# define machine_is_smdk2410aj() (0) +#endif + +#ifdef CONFIG_MACH_STREETRACER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STREETRACER +# endif +# define machine_is_streetracer() (machine_arch_type == MACH_TYPE_STREETRACER) +#else +# define machine_is_streetracer() (0) +#endif + +#ifdef CONFIG_MACH_EFRAME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EFRAME +# endif +# define machine_is_eframe() (machine_arch_type == MACH_TYPE_EFRAME) +#else +# define machine_is_eframe() (0) +#endif + +#ifdef CONFIG_MACH_CSB337 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB337 +# endif +# define machine_is_csb337() (machine_arch_type == MACH_TYPE_CSB337) +#else +# define machine_is_csb337() (0) +#endif + +#ifdef CONFIG_MACH_PXA_LARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_LARK +# endif +# define machine_is_pxa_lark() (machine_arch_type == MACH_TYPE_PXA_LARK) +#else +# define machine_is_pxa_lark() (0) +#endif + +#ifdef CONFIG_MACH_PNP2110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNP2110 +# endif +# define machine_is_pxa_pnp2110() (machine_arch_type == MACH_TYPE_PNP2110) +#else +# define machine_is_pxa_pnp2110() (0) +#endif + +#ifdef CONFIG_MACH_TCC72X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TCC72X +# endif +# define machine_is_tcc72x() (machine_arch_type == MACH_TYPE_TCC72X) +#else +# define machine_is_tcc72x() (0) +#endif + +#ifdef CONFIG_MACH_ALTAIR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALTAIR +# endif +# define machine_is_altair() (machine_arch_type == MACH_TYPE_ALTAIR) +#else +# define machine_is_altair() (0) +#endif + +#ifdef CONFIG_MACH_KC3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KC3 +# endif +# define machine_is_kc3() (machine_arch_type == MACH_TYPE_KC3) +#else +# define machine_is_kc3() (0) +#endif + +#ifdef CONFIG_MACH_SINTEFTD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SINTEFTD +# endif +# define machine_is_sinteftd() (machine_arch_type == MACH_TYPE_SINTEFTD) +#else +# define machine_is_sinteftd() (0) +#endif + +#ifdef CONFIG_MACH_MAINSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAINSTONE +# endif +# define machine_is_mainstone() (machine_arch_type == MACH_TYPE_MAINSTONE) +#else +# define machine_is_mainstone() (0) +#endif + +#ifdef CONFIG_MACH_ADAY4X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADAY4X +# endif +# define machine_is_aday4x() (machine_arch_type == MACH_TYPE_ADAY4X) +#else +# define machine_is_aday4x() (0) +#endif + +#ifdef CONFIG_MACH_LITE300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LITE300 +# endif +# define machine_is_lite300() (machine_arch_type == MACH_TYPE_LITE300) +#else +# define machine_is_lite300() (0) +#endif + +#ifdef CONFIG_MACH_S5C7376 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5C7376 +# endif +# define machine_is_s5c7376() (machine_arch_type == MACH_TYPE_S5C7376) +#else +# define machine_is_s5c7376() (0) +#endif + +#ifdef CONFIG_MACH_MT02 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MT02 +# endif +# define machine_is_mt02() (machine_arch_type == MACH_TYPE_MT02) +#else +# define machine_is_mt02() (0) +#endif + +#ifdef CONFIG_MACH_MPORT3S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPORT3S +# endif +# define machine_is_mport3s() (machine_arch_type == MACH_TYPE_MPORT3S) +#else +# define machine_is_mport3s() (0) +#endif + +#ifdef CONFIG_MACH_RA_ALPHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RA_ALPHA +# endif +# define machine_is_ra_alpha() (machine_arch_type == MACH_TYPE_RA_ALPHA) +#else +# define machine_is_ra_alpha() (0) +#endif + +#ifdef CONFIG_MACH_XCEP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XCEP +# endif +# define machine_is_xcep() (machine_arch_type == MACH_TYPE_XCEP) +#else +# define machine_is_xcep() (0) +#endif + +#ifdef CONFIG_MACH_ARCOM_MERCURY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCOM_MERCURY +# endif +# define machine_is_arcom_mercury() (machine_arch_type == MACH_TYPE_ARCOM_MERCURY) +#else +# define machine_is_arcom_mercury() (0) +#endif + +#ifdef CONFIG_MACH_STARGATE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STARGATE +# endif +# define machine_is_stargate() (machine_arch_type == MACH_TYPE_STARGATE) +#else +# define machine_is_stargate() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLOJ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLOJ +# endif +# define machine_is_armadilloj() (machine_arch_type == MACH_TYPE_ARMADILLOJ) +#else +# define machine_is_armadilloj() (0) +#endif + +#ifdef CONFIG_MACH_ELROY_JACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELROY_JACK +# endif +# define machine_is_elroy_jack() (machine_arch_type == MACH_TYPE_ELROY_JACK) +#else +# define machine_is_elroy_jack() (0) +#endif + +#ifdef CONFIG_MACH_BACKEND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BACKEND +# endif +# define machine_is_backend() (machine_arch_type == MACH_TYPE_BACKEND) +#else +# define machine_is_backend() (0) +#endif + +#ifdef CONFIG_MACH_S5LINBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5LINBOX +# endif +# define machine_is_s5linbox() (machine_arch_type == MACH_TYPE_S5LINBOX) +#else +# define machine_is_s5linbox() (0) +#endif + +#ifdef CONFIG_MACH_NOMADIK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOMADIK +# endif +# define machine_is_nomadik() (machine_arch_type == MACH_TYPE_NOMADIK) +#else +# define machine_is_nomadik() (0) +#endif + +#ifdef CONFIG_MACH_IA_CPU_9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IA_CPU_9200 +# endif +# define machine_is_ia_cpu_9200() (machine_arch_type == MACH_TYPE_IA_CPU_9200) +#else +# define machine_is_ia_cpu_9200() (0) +#endif + +#ifdef CONFIG_MACH_AT91_BJA1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91_BJA1 +# endif +# define machine_is_at91_bja1() (machine_arch_type == MACH_TYPE_AT91_BJA1) +#else +# define machine_is_at91_bja1() (0) +#endif + +#ifdef CONFIG_MACH_CORGI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORGI +# endif +# define machine_is_corgi() (machine_arch_type == MACH_TYPE_CORGI) +#else +# define machine_is_corgi() (0) +#endif + +#ifdef CONFIG_MACH_POODLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POODLE +# endif +# define machine_is_poodle() (machine_arch_type == MACH_TYPE_POODLE) +#else +# define machine_is_poodle() (0) +#endif + +#ifdef CONFIG_MACH_TEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEN +# endif +# define machine_is_ten() (machine_arch_type == MACH_TYPE_TEN) +#else +# define machine_is_ten() (0) +#endif + +#ifdef CONFIG_MACH_ROVERP5P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERP5P +# endif +# define machine_is_roverp5p() (machine_arch_type == MACH_TYPE_ROVERP5P) +#else +# define machine_is_roverp5p() (0) +#endif + +#ifdef CONFIG_MACH_SC2700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SC2700 +# endif +# define machine_is_sc2700() (machine_arch_type == MACH_TYPE_SC2700) +#else +# define machine_is_sc2700() (0) +#endif + +#ifdef CONFIG_MACH_EX_EAGLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EX_EAGLE +# endif +# define machine_is_ex_eagle() (machine_arch_type == MACH_TYPE_EX_EAGLE) +#else +# define machine_is_ex_eagle() (0) +#endif + +#ifdef CONFIG_MACH_NX_PXA12 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NX_PXA12 +# endif +# define machine_is_nx_pxa12() (machine_arch_type == MACH_TYPE_NX_PXA12) +#else +# define machine_is_nx_pxa12() (0) +#endif + +#ifdef CONFIG_MACH_NX_PXA5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NX_PXA5 +# endif +# define machine_is_nx_pxa5() (machine_arch_type == MACH_TYPE_NX_PXA5) +#else +# define machine_is_nx_pxa5() (0) +#endif + +#ifdef CONFIG_MACH_BLACKBOARD2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLACKBOARD2 +# endif +# define machine_is_blackboard2() (machine_arch_type == MACH_TYPE_BLACKBOARD2) +#else +# define machine_is_blackboard2() (0) +#endif + +#ifdef CONFIG_MACH_I819 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I819 +# endif +# define machine_is_i819() (machine_arch_type == MACH_TYPE_I819) +#else +# define machine_is_i819() (0) +#endif + +#ifdef CONFIG_MACH_IXMB995E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXMB995E +# endif +# define machine_is_ixmb995e() (machine_arch_type == MACH_TYPE_IXMB995E) +#else +# define machine_is_ixmb995e() (0) +#endif + +#ifdef CONFIG_MACH_SKYRIDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKYRIDER +# endif +# define machine_is_skyrider() (machine_arch_type == MACH_TYPE_SKYRIDER) +#else +# define machine_is_skyrider() (0) +#endif + +#ifdef CONFIG_MACH_SKYHAWK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKYHAWK +# endif +# define machine_is_skyhawk() (machine_arch_type == MACH_TYPE_SKYHAWK) +#else +# define machine_is_skyhawk() (0) +#endif + +#ifdef CONFIG_MACH_ENTERPRISE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENTERPRISE +# endif +# define machine_is_enterprise() (machine_arch_type == MACH_TYPE_ENTERPRISE) +#else +# define machine_is_enterprise() (0) +#endif + +#ifdef CONFIG_MACH_DEP2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEP2410 +# endif +# define machine_is_dep2410() (machine_arch_type == MACH_TYPE_DEP2410) +#else +# define machine_is_dep2410() (0) +#endif + +#ifdef CONFIG_MACH_ARMCORE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMCORE +# endif +# define machine_is_armcore() (machine_arch_type == MACH_TYPE_ARMCORE) +#else +# define machine_is_armcore() (0) +#endif + +#ifdef CONFIG_MACH_HOBBIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HOBBIT +# endif +# define machine_is_hobbit() (machine_arch_type == MACH_TYPE_HOBBIT) +#else +# define machine_is_hobbit() (0) +#endif + +#ifdef CONFIG_MACH_H7210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H7210 +# endif +# define machine_is_h7210() (machine_arch_type == MACH_TYPE_H7210) +#else +# define machine_is_h7210() (0) +#endif + +#ifdef CONFIG_MACH_PXA_NETDCU5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_NETDCU5 +# endif +# define machine_is_pxa_netdcu5() (machine_arch_type == MACH_TYPE_PXA_NETDCU5) +#else +# define machine_is_pxa_netdcu5() (0) +#endif + +#ifdef CONFIG_MACH_ACC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACC +# endif +# define machine_is_acc() (machine_arch_type == MACH_TYPE_ACC) +#else +# define machine_is_acc() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA +# endif +# define machine_is_esl_sarva() (machine_arch_type == MACH_TYPE_ESL_SARVA) +#else +# define machine_is_esl_sarva() (0) +#endif + +#ifdef CONFIG_MACH_XM250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XM250 +# endif +# define machine_is_xm250() (machine_arch_type == MACH_TYPE_XM250) +#else +# define machine_is_xm250() (0) +#endif + +#ifdef CONFIG_MACH_T6TC1XB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T6TC1XB +# endif +# define machine_is_t6tc1xb() (machine_arch_type == MACH_TYPE_T6TC1XB) +#else +# define machine_is_t6tc1xb() (0) +#endif + +#ifdef CONFIG_MACH_ESS710 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESS710 +# endif +# define machine_is_ess710() (machine_arch_type == MACH_TYPE_ESS710) +#else +# define machine_is_ess710() (0) +#endif + +#ifdef CONFIG_MACH_MX3ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX3ADS +# endif +# define machine_is_mx3ads() (machine_arch_type == MACH_TYPE_MX3ADS) +#else +# define machine_is_mx3ads() (0) +#endif + +#ifdef CONFIG_MACH_HIMALAYA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIMALAYA +# endif +# define machine_is_himalaya() (machine_arch_type == MACH_TYPE_HIMALAYA) +#else +# define machine_is_himalaya() (0) +#endif + +#ifdef CONFIG_MACH_BOLFENK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BOLFENK +# endif +# define machine_is_bolfenk() (machine_arch_type == MACH_TYPE_BOLFENK) +#else +# define machine_is_bolfenk() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200KR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200KR +# endif +# define machine_is_at91rm9200kr() (machine_arch_type == MACH_TYPE_AT91RM9200KR) +#else +# define machine_is_at91rm9200kr() (0) +#endif + +#ifdef CONFIG_MACH_EDB9312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9312 +# endif +# define machine_is_edb9312() (machine_arch_type == MACH_TYPE_EDB9312) +#else +# define machine_is_edb9312() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_GENERIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_GENERIC +# endif +# define machine_is_omap_generic() (machine_arch_type == MACH_TYPE_OMAP_GENERIC) +#else +# define machine_is_omap_generic() (0) +#endif + +#ifdef CONFIG_MACH_AXIMX3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXIMX3 +# endif +# define machine_is_aximx3() (machine_arch_type == MACH_TYPE_AXIMX3) +#else +# define machine_is_aximx3() (0) +#endif + +#ifdef CONFIG_MACH_EB67XDIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EB67XDIP +# endif +# define machine_is_eb67xdip() (machine_arch_type == MACH_TYPE_EB67XDIP) +#else +# define machine_is_eb67xdip() (0) +#endif + +#ifdef CONFIG_MACH_WEBTXS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WEBTXS +# endif +# define machine_is_webtxs() (machine_arch_type == MACH_TYPE_WEBTXS) +#else +# define machine_is_webtxs() (0) +#endif + +#ifdef CONFIG_MACH_HAWK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAWK +# endif +# define machine_is_hawk() (machine_arch_type == MACH_TYPE_HAWK) +#else +# define machine_is_hawk() (0) +#endif + +#ifdef CONFIG_MACH_CCAT91SBC001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCAT91SBC001 +# endif +# define machine_is_ccat91sbc001() (machine_arch_type == MACH_TYPE_CCAT91SBC001) +#else +# define machine_is_ccat91sbc001() (0) +#endif + +#ifdef CONFIG_MACH_EXPRESSO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXPRESSO +# endif +# define machine_is_expresso() (machine_arch_type == MACH_TYPE_EXPRESSO) +#else +# define machine_is_expresso() (0) +#endif + +#ifdef CONFIG_MACH_H4000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H4000 +# endif +# define machine_is_h4000() (machine_arch_type == MACH_TYPE_H4000) +#else +# define machine_is_h4000() (0) +#endif + +#ifdef CONFIG_MACH_DINO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DINO +# endif +# define machine_is_dino() (machine_arch_type == MACH_TYPE_DINO) +#else +# define machine_is_dino() (0) +#endif + +#ifdef CONFIG_MACH_ML675K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ML675K +# endif +# define machine_is_ml675k() (machine_arch_type == MACH_TYPE_ML675K) +#else +# define machine_is_ml675k() (0) +#endif + +#ifdef CONFIG_MACH_EDB9301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9301 +# endif +# define machine_is_edb9301() (machine_arch_type == MACH_TYPE_EDB9301) +#else +# define machine_is_edb9301() (0) +#endif + +#ifdef CONFIG_MACH_EDB9315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9315 +# endif +# define machine_is_edb9315() (machine_arch_type == MACH_TYPE_EDB9315) +#else +# define machine_is_edb9315() (0) +#endif + +#ifdef CONFIG_MACH_RECIVA_TT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RECIVA_TT +# endif +# define machine_is_reciva_tt() (machine_arch_type == MACH_TYPE_RECIVA_TT) +#else +# define machine_is_reciva_tt() (0) +#endif + +#ifdef CONFIG_MACH_CSTCB01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSTCB01 +# endif +# define machine_is_cstcb01() (machine_arch_type == MACH_TYPE_CSTCB01) +#else +# define machine_is_cstcb01() (0) +#endif + +#ifdef CONFIG_MACH_CSTCB1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSTCB1 +# endif +# define machine_is_cstcb1() (machine_arch_type == MACH_TYPE_CSTCB1) +#else +# define machine_is_cstcb1() (0) +#endif + +#ifdef CONFIG_MACH_SHADWELL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHADWELL +# endif +# define machine_is_shadwell() (machine_arch_type == MACH_TYPE_SHADWELL) +#else +# define machine_is_shadwell() (0) +#endif + +#ifdef CONFIG_MACH_GOEPEL263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GOEPEL263 +# endif +# define machine_is_goepel263() (machine_arch_type == MACH_TYPE_GOEPEL263) +#else +# define machine_is_goepel263() (0) +#endif + +#ifdef CONFIG_MACH_ACQ100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACQ100 +# endif +# define machine_is_acq100() (machine_arch_type == MACH_TYPE_ACQ100) +#else +# define machine_is_acq100() (0) +#endif + +#ifdef CONFIG_MACH_MX1FS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX1FS2 +# endif +# define machine_is_mx1fs2() (machine_arch_type == MACH_TYPE_MX1FS2) +#else +# define machine_is_mx1fs2() (0) +#endif + +#ifdef CONFIG_MACH_HIPTOP_G1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIPTOP_G1 +# endif +# define machine_is_hiptop_g1() (machine_arch_type == MACH_TYPE_HIPTOP_G1) +#else +# define machine_is_hiptop_g1() (0) +#endif + +#ifdef CONFIG_MACH_SPARKY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPARKY +# endif +# define machine_is_sparky() (machine_arch_type == MACH_TYPE_SPARKY) +#else +# define machine_is_sparky() (0) +#endif + +#ifdef CONFIG_MACH_NS9750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NS9750 +# endif +# define machine_is_ns9750() (machine_arch_type == MACH_TYPE_NS9750) +#else +# define machine_is_ns9750() (0) +#endif + +#ifdef CONFIG_MACH_PHOENIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHOENIX +# endif +# define machine_is_phoenix() (machine_arch_type == MACH_TYPE_PHOENIX) +#else +# define machine_is_phoenix() (0) +#endif + +#ifdef CONFIG_MACH_VR1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VR1000 +# endif +# define machine_is_vr1000() (machine_arch_type == MACH_TYPE_VR1000) +#else +# define machine_is_vr1000() (0) +#endif + +#ifdef CONFIG_MACH_DEISTERPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEISTERPXA +# endif +# define machine_is_deisterpxa() (machine_arch_type == MACH_TYPE_DEISTERPXA) +#else +# define machine_is_deisterpxa() (0) +#endif + +#ifdef CONFIG_MACH_BCM1160 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM1160 +# endif +# define machine_is_bcm1160() (machine_arch_type == MACH_TYPE_BCM1160) +#else +# define machine_is_bcm1160() (0) +#endif + +#ifdef CONFIG_MACH_PCM022 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM022 +# endif +# define machine_is_pcm022() (machine_arch_type == MACH_TYPE_PCM022) +#else +# define machine_is_pcm022() (0) +#endif + +#ifdef CONFIG_MACH_ADSGCX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSGCX +# endif +# define machine_is_adsgcx() (machine_arch_type == MACH_TYPE_ADSGCX) +#else +# define machine_is_adsgcx() (0) +#endif + +#ifdef CONFIG_MACH_DREADNAUGHT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DREADNAUGHT +# endif +# define machine_is_dreadnaught() (machine_arch_type == MACH_TYPE_DREADNAUGHT) +#else +# define machine_is_dreadnaught() (0) +#endif + +#ifdef CONFIG_MACH_DM320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM320 +# endif +# define machine_is_dm320() (machine_arch_type == MACH_TYPE_DM320) +#else +# define machine_is_dm320() (0) +#endif + +#ifdef CONFIG_MACH_MARKOV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARKOV +# endif +# define machine_is_markov() (machine_arch_type == MACH_TYPE_MARKOV) +#else +# define machine_is_markov() (0) +#endif + +#ifdef CONFIG_MACH_COS7A400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COS7A400 +# endif +# define machine_is_cos7a400() (machine_arch_type == MACH_TYPE_COS7A400) +#else +# define machine_is_cos7a400() (0) +#endif + +#ifdef CONFIG_MACH_MILANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MILANO +# endif +# define machine_is_milano() (machine_arch_type == MACH_TYPE_MILANO) +#else +# define machine_is_milano() (0) +#endif + +#ifdef CONFIG_MACH_UE9328 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UE9328 +# endif +# define machine_is_ue9328() (machine_arch_type == MACH_TYPE_UE9328) +#else +# define machine_is_ue9328() (0) +#endif + +#ifdef CONFIG_MACH_UEX255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UEX255 +# endif +# define machine_is_uex255() (machine_arch_type == MACH_TYPE_UEX255) +#else +# define machine_is_uex255() (0) +#endif + +#ifdef CONFIG_MACH_UE2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UE2410 +# endif +# define machine_is_ue2410() (machine_arch_type == MACH_TYPE_UE2410) +#else +# define machine_is_ue2410() (0) +#endif + +#ifdef CONFIG_MACH_A620 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A620 +# endif +# define machine_is_a620() (machine_arch_type == MACH_TYPE_A620) +#else +# define machine_is_a620() (0) +#endif + +#ifdef CONFIG_MACH_OCELOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCELOT +# endif +# define machine_is_ocelot() (machine_arch_type == MACH_TYPE_OCELOT) +#else +# define machine_is_ocelot() (0) +#endif + +#ifdef CONFIG_MACH_CHEETAH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHEETAH +# endif +# define machine_is_cheetah() (machine_arch_type == MACH_TYPE_CHEETAH) +#else +# define machine_is_cheetah() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PERSEUS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PERSEUS2 +# endif +# define machine_is_omap_perseus2() (machine_arch_type == MACH_TYPE_OMAP_PERSEUS2) +#else +# define machine_is_omap_perseus2() (0) +#endif + +#ifdef CONFIG_MACH_ZVUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZVUE +# endif +# define machine_is_zvue() (machine_arch_type == MACH_TYPE_ZVUE) +#else +# define machine_is_zvue() (0) +#endif + +#ifdef CONFIG_MACH_ROVERP1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERP1 +# endif +# define machine_is_roverp1() (machine_arch_type == MACH_TYPE_ROVERP1) +#else +# define machine_is_roverp1() (0) +#endif + +#ifdef CONFIG_MACH_ASIDIAL2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASIDIAL2 +# endif +# define machine_is_asidial2() (machine_arch_type == MACH_TYPE_ASIDIAL2) +#else +# define machine_is_asidial2() (0) +#endif + +#ifdef CONFIG_MACH_S3C24A0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C24A0 +# endif +# define machine_is_s3c24a0() (machine_arch_type == MACH_TYPE_S3C24A0) +#else +# define machine_is_s3c24a0() (0) +#endif + +#ifdef CONFIG_MACH_E800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E800 +# endif +# define machine_is_e800() (machine_arch_type == MACH_TYPE_E800) +#else +# define machine_is_e800() (0) +#endif + +#ifdef CONFIG_MACH_E750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E750 +# endif +# define machine_is_e750() (machine_arch_type == MACH_TYPE_E750) +#else +# define machine_is_e750() (0) +#endif + +#ifdef CONFIG_MACH_S3C5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C5500 +# endif +# define machine_is_s3c5500() (machine_arch_type == MACH_TYPE_S3C5500) +#else +# define machine_is_s3c5500() (0) +#endif + +#ifdef CONFIG_MACH_SMDK5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK5500 +# endif +# define machine_is_smdk5500() (machine_arch_type == MACH_TYPE_SMDK5500) +#else +# define machine_is_smdk5500() (0) +#endif + +#ifdef CONFIG_MACH_SIGNALSYNC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIGNALSYNC +# endif +# define machine_is_signalsync() (machine_arch_type == MACH_TYPE_SIGNALSYNC) +#else +# define machine_is_signalsync() (0) +#endif + +#ifdef CONFIG_MACH_NBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NBC +# endif +# define machine_is_nbc() (machine_arch_type == MACH_TYPE_NBC) +#else +# define machine_is_nbc() (0) +#endif + +#ifdef CONFIG_MACH_KODIAK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KODIAK +# endif +# define machine_is_kodiak() (machine_arch_type == MACH_TYPE_KODIAK) +#else +# define machine_is_kodiak() (0) +#endif + +#ifdef CONFIG_MACH_NETBOOKPRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETBOOKPRO +# endif +# define machine_is_netbookpro() (machine_arch_type == MACH_TYPE_NETBOOKPRO) +#else +# define machine_is_netbookpro() (0) +#endif + +#ifdef CONFIG_MACH_HW90200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90200 +# endif +# define machine_is_hw90200() (machine_arch_type == MACH_TYPE_HW90200) +#else +# define machine_is_hw90200() (0) +#endif + +#ifdef CONFIG_MACH_CONDOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CONDOR +# endif +# define machine_is_condor() (machine_arch_type == MACH_TYPE_CONDOR) +#else +# define machine_is_condor() (0) +#endif + +#ifdef CONFIG_MACH_CUP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CUP +# endif +# define machine_is_cup() (machine_arch_type == MACH_TYPE_CUP) +#else +# define machine_is_cup() (0) +#endif + +#ifdef CONFIG_MACH_KITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KITE +# endif +# define machine_is_kite() (machine_arch_type == MACH_TYPE_KITE) +#else +# define machine_is_kite() (0) +#endif + +#ifdef CONFIG_MACH_SCB9328 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCB9328 +# endif +# define machine_is_scb9328() (machine_arch_type == MACH_TYPE_SCB9328) +#else +# define machine_is_scb9328() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_H3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_H3 +# endif +# define machine_is_omap_h3() (machine_arch_type == MACH_TYPE_OMAP_H3) +#else +# define machine_is_omap_h3() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_H4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_H4 +# endif +# define machine_is_omap_h4() (machine_arch_type == MACH_TYPE_OMAP_H4) +#else +# define machine_is_omap_h4() (0) +#endif + +#ifdef CONFIG_MACH_N10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N10 +# endif +# define machine_is_n10() (machine_arch_type == MACH_TYPE_N10) +#else +# define machine_is_n10() (0) +#endif + +#ifdef CONFIG_MACH_MONTAJADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MONTAJADE +# endif +# define machine_is_montejade() (machine_arch_type == MACH_TYPE_MONTAJADE) +#else +# define machine_is_montejade() (0) +#endif + +#ifdef CONFIG_MACH_SG560 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG560 +# endif +# define machine_is_sg560() (machine_arch_type == MACH_TYPE_SG560) +#else +# define machine_is_sg560() (0) +#endif + +#ifdef CONFIG_MACH_DP1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DP1000 +# endif +# define machine_is_dp1000() (machine_arch_type == MACH_TYPE_DP1000) +#else +# define machine_is_dp1000() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_OSK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_OSK +# endif +# define machine_is_omap_osk() (machine_arch_type == MACH_TYPE_OMAP_OSK) +#else +# define machine_is_omap_osk() (0) +#endif + +#ifdef CONFIG_MACH_RG100V3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RG100V3 +# endif +# define machine_is_rg100v3() (machine_arch_type == MACH_TYPE_RG100V3) +#else +# define machine_is_rg100v3() (0) +#endif + +#ifdef CONFIG_MACH_MX2ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX2ADS +# endif +# define machine_is_mx2ads() (machine_arch_type == MACH_TYPE_MX2ADS) +#else +# define machine_is_mx2ads() (0) +#endif + +#ifdef CONFIG_MACH_PXA_KILO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_KILO +# endif +# define machine_is_pxa_kilo() (machine_arch_type == MACH_TYPE_PXA_KILO) +#else +# define machine_is_pxa_kilo() (0) +#endif + +#ifdef CONFIG_MACH_IXP4XX_EAGLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP4XX_EAGLE +# endif +# define machine_is_ixp4xx_eagle() (machine_arch_type == MACH_TYPE_IXP4XX_EAGLE) +#else +# define machine_is_ixp4xx_eagle() (0) +#endif + +#ifdef CONFIG_MACH_TOSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOSA +# endif +# define machine_is_tosa() (machine_arch_type == MACH_TYPE_TOSA) +#else +# define machine_is_tosa() (0) +#endif + +#ifdef CONFIG_MACH_MB2520F +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB2520F +# endif +# define machine_is_mb2520f() (machine_arch_type == MACH_TYPE_MB2520F) +#else +# define machine_is_mb2520f() (0) +#endif + +#ifdef CONFIG_MACH_EMC1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMC1000 +# endif +# define machine_is_emc1000() (machine_arch_type == MACH_TYPE_EMC1000) +#else +# define machine_is_emc1000() (0) +#endif + +#ifdef CONFIG_MACH_TIDSC25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIDSC25 +# endif +# define machine_is_tidsc25() (machine_arch_type == MACH_TYPE_TIDSC25) +#else +# define machine_is_tidsc25() (0) +#endif + +#ifdef CONFIG_MACH_AKCPMXL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AKCPMXL +# endif +# define machine_is_akcpmxl() (machine_arch_type == MACH_TYPE_AKCPMXL) +#else +# define machine_is_akcpmxl() (0) +#endif + +#ifdef CONFIG_MACH_AV3XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AV3XX +# endif +# define machine_is_av3xx() (machine_arch_type == MACH_TYPE_AV3XX) +#else +# define machine_is_av3xx() (0) +#endif + +#ifdef CONFIG_MACH_AVILA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVILA +# endif +# define machine_is_avila() (machine_arch_type == MACH_TYPE_AVILA) +#else +# define machine_is_avila() (0) +#endif + +#ifdef CONFIG_MACH_PXA_MPM10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_MPM10 +# endif +# define machine_is_pxa_mpm10() (machine_arch_type == MACH_TYPE_PXA_MPM10) +#else +# define machine_is_pxa_mpm10() (0) +#endif + +#ifdef CONFIG_MACH_PXA_KYANITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_KYANITE +# endif +# define machine_is_pxa_kyanite() (machine_arch_type == MACH_TYPE_PXA_KYANITE) +#else +# define machine_is_pxa_kyanite() (0) +#endif + +#ifdef CONFIG_MACH_SGOLD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGOLD +# endif +# define machine_is_sgold() (machine_arch_type == MACH_TYPE_SGOLD) +#else +# define machine_is_sgold() (0) +#endif + +#ifdef CONFIG_MACH_OSCAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OSCAR +# endif +# define machine_is_oscar() (machine_arch_type == MACH_TYPE_OSCAR) +#else +# define machine_is_oscar() (0) +#endif + +#ifdef CONFIG_MACH_EPXA4USB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPXA4USB2 +# endif +# define machine_is_epxa4usb2() (machine_arch_type == MACH_TYPE_EPXA4USB2) +#else +# define machine_is_epxa4usb2() (0) +#endif + +#ifdef CONFIG_MACH_XSENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSENGINE +# endif +# define machine_is_xsengine() (machine_arch_type == MACH_TYPE_XSENGINE) +#else +# define machine_is_xsengine() (0) +#endif + +#ifdef CONFIG_MACH_IP600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP600 +# endif +# define machine_is_ip600() (machine_arch_type == MACH_TYPE_IP600) +#else +# define machine_is_ip600() (0) +#endif + +#ifdef CONFIG_MACH_MCAN2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCAN2 +# endif +# define machine_is_mcan2() (machine_arch_type == MACH_TYPE_MCAN2) +#else +# define machine_is_mcan2() (0) +#endif + +#ifdef CONFIG_MACH_DDI_BLUERIDGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DDI_BLUERIDGE +# endif +# define machine_is_ddi_blueridge() (machine_arch_type == MACH_TYPE_DDI_BLUERIDGE) +#else +# define machine_is_ddi_blueridge() (0) +#endif + +#ifdef CONFIG_MACH_SKYMINDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKYMINDER +# endif +# define machine_is_skyminder() (machine_arch_type == MACH_TYPE_SKYMINDER) +#else +# define machine_is_skyminder() (0) +#endif + +#ifdef CONFIG_MACH_LPD79520 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD79520 +# endif +# define machine_is_lpd79520() (machine_arch_type == MACH_TYPE_LPD79520) +#else +# define machine_is_lpd79520() (0) +#endif + +#ifdef CONFIG_MACH_EDB9302 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9302 +# endif +# define machine_is_edb9302() (machine_arch_type == MACH_TYPE_EDB9302) +#else +# define machine_is_edb9302() (0) +#endif + +#ifdef CONFIG_MACH_HW90340 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90340 +# endif +# define machine_is_hw90340() (machine_arch_type == MACH_TYPE_HW90340) +#else +# define machine_is_hw90340() (0) +#endif + +#ifdef CONFIG_MACH_CIP_BOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CIP_BOX +# endif +# define machine_is_cip_box() (machine_arch_type == MACH_TYPE_CIP_BOX) +#else +# define machine_is_cip_box() (0) +#endif + +#ifdef CONFIG_MACH_IVPN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IVPN +# endif +# define machine_is_ivpn() (machine_arch_type == MACH_TYPE_IVPN) +#else +# define machine_is_ivpn() (0) +#endif + +#ifdef CONFIG_MACH_RSOC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSOC2 +# endif +# define machine_is_rsoc2() (machine_arch_type == MACH_TYPE_RSOC2) +#else +# define machine_is_rsoc2() (0) +#endif + +#ifdef CONFIG_MACH_HUSKY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUSKY +# endif +# define machine_is_husky() (machine_arch_type == MACH_TYPE_HUSKY) +#else +# define machine_is_husky() (0) +#endif + +#ifdef CONFIG_MACH_BOXER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BOXER +# endif +# define machine_is_boxer() (machine_arch_type == MACH_TYPE_BOXER) +#else +# define machine_is_boxer() (0) +#endif + +#ifdef CONFIG_MACH_SHEPHERD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHEPHERD +# endif +# define machine_is_shepherd() (machine_arch_type == MACH_TYPE_SHEPHERD) +#else +# define machine_is_shepherd() (0) +#endif + +#ifdef CONFIG_MACH_AML42800AA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AML42800AA +# endif +# define machine_is_aml42800aa() (machine_arch_type == MACH_TYPE_AML42800AA) +#else +# define machine_is_aml42800aa() (0) +#endif + +#ifdef CONFIG_MACH_MACH_TYPE_ML674001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MACH_TYPE_ML674001 +# endif +# define machine_is_ml674001() (machine_arch_type == MACH_TYPE_MACH_TYPE_ML674001) +#else +# define machine_is_ml674001() (0) +#endif + +#ifdef CONFIG_MACH_LPC2294 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2294 +# endif +# define machine_is_lpc2294() (machine_arch_type == MACH_TYPE_LPC2294) +#else +# define machine_is_lpc2294() (0) +#endif + +#ifdef CONFIG_MACH_SWITCHGRASS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWITCHGRASS +# endif +# define machine_is_switchgrass() (machine_arch_type == MACH_TYPE_SWITCHGRASS) +#else +# define machine_is_switchgrass() (0) +#endif + +#ifdef CONFIG_MACH_ENS_CMU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENS_CMU +# endif +# define machine_is_ens_cmu() (machine_arch_type == MACH_TYPE_ENS_CMU) +#else +# define machine_is_ens_cmu() (0) +#endif + +#ifdef CONFIG_MACH_MM6_SDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MM6_SDB +# endif +# define machine_is_mm6_sdb() (machine_arch_type == MACH_TYPE_MM6_SDB) +#else +# define machine_is_mm6_sdb() (0) +#endif + +#ifdef CONFIG_MACH_SATURN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SATURN +# endif +# define machine_is_saturn() (machine_arch_type == MACH_TYPE_SATURN) +#else +# define machine_is_saturn() (0) +#endif + +#ifdef CONFIG_MACH_ARGONPLUSEVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARGONPLUSEVB +# endif +# define machine_is_argonplusevb() (machine_arch_type == MACH_TYPE_ARGONPLUSEVB) +#else +# define machine_is_argonplusevb() (0) +#endif + +#ifdef CONFIG_MACH_SCMA11EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCMA11EVB +# endif +# define machine_is_scma11evb() (machine_arch_type == MACH_TYPE_SCMA11EVB) +#else +# define machine_is_scma11evb() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2800 +# endif +# define machine_is_smdk2800() (machine_arch_type == MACH_TYPE_SMDK2800) +#else +# define machine_is_smdk2800() (0) +#endif + +#ifdef CONFIG_MACH_MTWILSON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MTWILSON +# endif +# define machine_is_mtwilson() (machine_arch_type == MACH_TYPE_MTWILSON) +#else +# define machine_is_mtwilson() (0) +#endif + +#ifdef CONFIG_MACH_ZITI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZITI +# endif +# define machine_is_ziti() (machine_arch_type == MACH_TYPE_ZITI) +#else +# define machine_is_ziti() (0) +#endif + +#ifdef CONFIG_MACH_GRANDFATHER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GRANDFATHER +# endif +# define machine_is_grandfather() (machine_arch_type == MACH_TYPE_GRANDFATHER) +#else +# define machine_is_grandfather() (0) +#endif + +#ifdef CONFIG_MACH_TENGINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TENGINE +# endif +# define machine_is_tengine() (machine_arch_type == MACH_TYPE_TENGINE) +#else +# define machine_is_tengine() (0) +#endif + +#ifdef CONFIG_MACH_S3C2460 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2460 +# endif +# define machine_is_s3c2460() (machine_arch_type == MACH_TYPE_S3C2460) +#else +# define machine_is_s3c2460() (0) +#endif + +#ifdef CONFIG_MACH_PDM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PDM +# endif +# define machine_is_pdm() (machine_arch_type == MACH_TYPE_PDM) +#else +# define machine_is_pdm() (0) +#endif + +#ifdef CONFIG_MACH_H4700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H4700 +# endif +# define machine_is_h4700() (machine_arch_type == MACH_TYPE_H4700) +#else +# define machine_is_h4700() (0) +#endif + +#ifdef CONFIG_MACH_H6300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6300 +# endif +# define machine_is_h6300() (machine_arch_type == MACH_TYPE_H6300) +#else +# define machine_is_h6300() (0) +#endif + +#ifdef CONFIG_MACH_RZ1700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RZ1700 +# endif +# define machine_is_rz1700() (machine_arch_type == MACH_TYPE_RZ1700) +#else +# define machine_is_rz1700() (0) +#endif + +#ifdef CONFIG_MACH_A716 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A716 +# endif +# define machine_is_a716() (machine_arch_type == MACH_TYPE_A716) +#else +# define machine_is_a716() (0) +#endif + +#ifdef CONFIG_MACH_ESTK2440A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESTK2440A +# endif +# define machine_is_estk2440a() (machine_arch_type == MACH_TYPE_ESTK2440A) +#else +# define machine_is_estk2440a() (0) +#endif + +#ifdef CONFIG_MACH_ATWIXP425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATWIXP425 +# endif +# define machine_is_atwixp425() (machine_arch_type == MACH_TYPE_ATWIXP425) +#else +# define machine_is_atwixp425() (0) +#endif + +#ifdef CONFIG_MACH_CSB336 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB336 +# endif +# define machine_is_csb336() (machine_arch_type == MACH_TYPE_CSB336) +#else +# define machine_is_csb336() (0) +#endif + +#ifdef CONFIG_MACH_RIRM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIRM2 +# endif +# define machine_is_rirm2() (machine_arch_type == MACH_TYPE_RIRM2) +#else +# define machine_is_rirm2() (0) +#endif + +#ifdef CONFIG_MACH_CX23518 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CX23518 +# endif +# define machine_is_cx23518() (machine_arch_type == MACH_TYPE_CX23518) +#else +# define machine_is_cx23518() (0) +#endif + +#ifdef CONFIG_MACH_CX2351X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CX2351X +# endif +# define machine_is_cx2351x() (machine_arch_type == MACH_TYPE_CX2351X) +#else +# define machine_is_cx2351x() (0) +#endif + +#ifdef CONFIG_MACH_COMPUTIME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMPUTIME +# endif +# define machine_is_computime() (machine_arch_type == MACH_TYPE_COMPUTIME) +#else +# define machine_is_computime() (0) +#endif + +#ifdef CONFIG_MACH_IZARUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IZARUS +# endif +# define machine_is_izarus() (machine_arch_type == MACH_TYPE_IZARUS) +#else +# define machine_is_izarus() (0) +#endif + +#ifdef CONFIG_MACH_RTS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTS +# endif +# define machine_is_pxa_rts() (machine_arch_type == MACH_TYPE_RTS) +#else +# define machine_is_pxa_rts() (0) +#endif + +#ifdef CONFIG_MACH_SE5100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SE5100 +# endif +# define machine_is_se5100() (machine_arch_type == MACH_TYPE_SE5100) +#else +# define machine_is_se5100() (0) +#endif + +#ifdef CONFIG_MACH_S3C2510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2510 +# endif +# define machine_is_s3c2510() (machine_arch_type == MACH_TYPE_S3C2510) +#else +# define machine_is_s3c2510() (0) +#endif + +#ifdef CONFIG_MACH_CSB437TL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB437TL +# endif +# define machine_is_csb437tl() (machine_arch_type == MACH_TYPE_CSB437TL) +#else +# define machine_is_csb437tl() (0) +#endif + +#ifdef CONFIG_MACH_SLAUSON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SLAUSON +# endif +# define machine_is_slauson() (machine_arch_type == MACH_TYPE_SLAUSON) +#else +# define machine_is_slauson() (0) +#endif + +#ifdef CONFIG_MACH_PEARLRIVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEARLRIVER +# endif +# define machine_is_pearlriver() (machine_arch_type == MACH_TYPE_PEARLRIVER) +#else +# define machine_is_pearlriver() (0) +#endif + +#ifdef CONFIG_MACH_TDC_P210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TDC_P210 +# endif +# define machine_is_tdc_p210() (machine_arch_type == MACH_TYPE_TDC_P210) +#else +# define machine_is_tdc_p210() (0) +#endif + +#ifdef CONFIG_MACH_SG580 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG580 +# endif +# define machine_is_sg580() (machine_arch_type == MACH_TYPE_SG580) +#else +# define machine_is_sg580() (0) +#endif + +#ifdef CONFIG_MACH_WRSBCARM7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WRSBCARM7 +# endif +# define machine_is_wrsbcarm7() (machine_arch_type == MACH_TYPE_WRSBCARM7) +#else +# define machine_is_wrsbcarm7() (0) +#endif + +#ifdef CONFIG_MACH_IPD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPD +# endif +# define machine_is_ipd() (machine_arch_type == MACH_TYPE_IPD) +#else +# define machine_is_ipd() (0) +#endif + +#ifdef CONFIG_MACH_PXA_DNP2110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_DNP2110 +# endif +# define machine_is_pxa_dnp2110() (machine_arch_type == MACH_TYPE_PXA_DNP2110) +#else +# define machine_is_pxa_dnp2110() (0) +#endif + +#ifdef CONFIG_MACH_XAENIAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XAENIAX +# endif +# define machine_is_xaeniax() (machine_arch_type == MACH_TYPE_XAENIAX) +#else +# define machine_is_xaeniax() (0) +#endif + +#ifdef CONFIG_MACH_SOMN4250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOMN4250 +# endif +# define machine_is_somn4250() (machine_arch_type == MACH_TYPE_SOMN4250) +#else +# define machine_is_somn4250() (0) +#endif + +#ifdef CONFIG_MACH_PLEB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLEB2 +# endif +# define machine_is_pleb2() (machine_arch_type == MACH_TYPE_PLEB2) +#else +# define machine_is_pleb2() (0) +#endif + +#ifdef CONFIG_MACH_CORNWALLIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORNWALLIS +# endif +# define machine_is_cornwallis() (machine_arch_type == MACH_TYPE_CORNWALLIS) +#else +# define machine_is_cornwallis() (0) +#endif + +#ifdef CONFIG_MACH_GURNEY_DRV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GURNEY_DRV +# endif +# define machine_is_gurney_drv() (machine_arch_type == MACH_TYPE_GURNEY_DRV) +#else +# define machine_is_gurney_drv() (0) +#endif + +#ifdef CONFIG_MACH_CHAFFEE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHAFFEE +# endif +# define machine_is_chaffee() (machine_arch_type == MACH_TYPE_CHAFFEE) +#else +# define machine_is_chaffee() (0) +#endif + +#ifdef CONFIG_MACH_RMS101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RMS101 +# endif +# define machine_is_rms101() (machine_arch_type == MACH_TYPE_RMS101) +#else +# define machine_is_rms101() (0) +#endif + +#ifdef CONFIG_MACH_RX3715 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RX3715 +# endif +# define machine_is_rx3715() (machine_arch_type == MACH_TYPE_RX3715) +#else +# define machine_is_rx3715() (0) +#endif + +#ifdef CONFIG_MACH_SWIFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWIFT +# endif +# define machine_is_swift() (machine_arch_type == MACH_TYPE_SWIFT) +#else +# define machine_is_swift() (0) +#endif + +#ifdef CONFIG_MACH_ROVERP7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERP7 +# endif +# define machine_is_roverp7() (machine_arch_type == MACH_TYPE_ROVERP7) +#else +# define machine_is_roverp7() (0) +#endif + +#ifdef CONFIG_MACH_PR818S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PR818S +# endif +# define machine_is_pr818s() (machine_arch_type == MACH_TYPE_PR818S) +#else +# define machine_is_pr818s() (0) +#endif + +#ifdef CONFIG_MACH_TRXPRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRXPRO +# endif +# define machine_is_trxpro() (machine_arch_type == MACH_TYPE_TRXPRO) +#else +# define machine_is_trxpro() (0) +#endif + +#ifdef CONFIG_MACH_NSLU2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSLU2 +# endif +# define machine_is_nslu2() (machine_arch_type == MACH_TYPE_NSLU2) +#else +# define machine_is_nslu2() (0) +#endif + +#ifdef CONFIG_MACH_E400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E400 +# endif +# define machine_is_e400() (machine_arch_type == MACH_TYPE_E400) +#else +# define machine_is_e400() (0) +#endif + +#ifdef CONFIG_MACH_TRAB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRAB +# endif +# define machine_is_trab() (machine_arch_type == MACH_TYPE_TRAB) +#else +# define machine_is_trab() (0) +#endif + +#ifdef CONFIG_MACH_CMC_PU2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMC_PU2 +# endif +# define machine_is_cmc_pu2() (machine_arch_type == MACH_TYPE_CMC_PU2) +#else +# define machine_is_cmc_pu2() (0) +#endif + +#ifdef CONFIG_MACH_FULCRUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FULCRUM +# endif +# define machine_is_fulcrum() (machine_arch_type == MACH_TYPE_FULCRUM) +#else +# define machine_is_fulcrum() (0) +#endif + +#ifdef CONFIG_MACH_NETGATE42X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETGATE42X +# endif +# define machine_is_netgate42x() (machine_arch_type == MACH_TYPE_NETGATE42X) +#else +# define machine_is_netgate42x() (0) +#endif + +#ifdef CONFIG_MACH_STR710 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STR710 +# endif +# define machine_is_str710() (machine_arch_type == MACH_TYPE_STR710) +#else +# define machine_is_str710() (0) +#endif + +#ifdef CONFIG_MACH_IXDPG425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDPG425 +# endif +# define machine_is_ixdpg425() (machine_arch_type == MACH_TYPE_IXDPG425) +#else +# define machine_is_ixdpg425() (0) +#endif + +#ifdef CONFIG_MACH_TOMTOMGO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOMTOMGO +# endif +# define machine_is_tomtomgo() (machine_arch_type == MACH_TYPE_TOMTOMGO) +#else +# define machine_is_tomtomgo() (0) +#endif + +#ifdef CONFIG_MACH_VERSATILE_AB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VERSATILE_AB +# endif +# define machine_is_versatile_ab() (machine_arch_type == MACH_TYPE_VERSATILE_AB) +#else +# define machine_is_versatile_ab() (0) +#endif + +#ifdef CONFIG_MACH_EDB9307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9307 +# endif +# define machine_is_edb9307() (machine_arch_type == MACH_TYPE_EDB9307) +#else +# define machine_is_edb9307() (0) +#endif + +#ifdef CONFIG_MACH_SG565 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG565 +# endif +# define machine_is_sg565() (machine_arch_type == MACH_TYPE_SG565) +#else +# define machine_is_sg565() (0) +#endif + +#ifdef CONFIG_MACH_LPD79524 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD79524 +# endif +# define machine_is_lpd79524() (machine_arch_type == MACH_TYPE_LPD79524) +#else +# define machine_is_lpd79524() (0) +#endif + +#ifdef CONFIG_MACH_LPD79525 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPD79525 +# endif +# define machine_is_lpd79525() (machine_arch_type == MACH_TYPE_LPD79525) +#else +# define machine_is_lpd79525() (0) +#endif + +#ifdef CONFIG_MACH_RMS100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RMS100 +# endif +# define machine_is_rms100() (machine_arch_type == MACH_TYPE_RMS100) +#else +# define machine_is_rms100() (0) +#endif + +#ifdef CONFIG_MACH_KB9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KB9200 +# endif +# define machine_is_kb9200() (machine_arch_type == MACH_TYPE_KB9200) +#else +# define machine_is_kb9200() (0) +#endif + +#ifdef CONFIG_MACH_SX1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SX1 +# endif +# define machine_is_sx1() (machine_arch_type == MACH_TYPE_SX1) +#else +# define machine_is_sx1() (0) +#endif + +#ifdef CONFIG_MACH_HMS39C7092 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMS39C7092 +# endif +# define machine_is_hms39c7092() (machine_arch_type == MACH_TYPE_HMS39C7092) +#else +# define machine_is_hms39c7092() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO +# endif +# define machine_is_armadillo() (machine_arch_type == MACH_TYPE_ARMADILLO) +#else +# define machine_is_armadillo() (0) +#endif + +#ifdef CONFIG_MACH_IPCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPCU +# endif +# define machine_is_ipcu() (machine_arch_type == MACH_TYPE_IPCU) +#else +# define machine_is_ipcu() (0) +#endif + +#ifdef CONFIG_MACH_LOOX720 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOX720 +# endif +# define machine_is_loox720() (machine_arch_type == MACH_TYPE_LOOX720) +#else +# define machine_is_loox720() (0) +#endif + +#ifdef CONFIG_MACH_IXDP465 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP465 +# endif +# define machine_is_ixdp465() (machine_arch_type == MACH_TYPE_IXDP465) +#else +# define machine_is_ixdp465() (0) +#endif + +#ifdef CONFIG_MACH_IXDP2351 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP2351 +# endif +# define machine_is_ixdp2351() (machine_arch_type == MACH_TYPE_IXDP2351) +#else +# define machine_is_ixdp2351() (0) +#endif + +#ifdef CONFIG_MACH_ADSVIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSVIX +# endif +# define machine_is_adsvix() (machine_arch_type == MACH_TYPE_ADSVIX) +#else +# define machine_is_adsvix() (0) +#endif + +#ifdef CONFIG_MACH_DM270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM270 +# endif +# define machine_is_dm270() (machine_arch_type == MACH_TYPE_DM270) +#else +# define machine_is_dm270() (0) +#endif + +#ifdef CONFIG_MACH_SOCLTPLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOCLTPLUS +# endif +# define machine_is_socltplus() (machine_arch_type == MACH_TYPE_SOCLTPLUS) +#else +# define machine_is_socltplus() (0) +#endif + +#ifdef CONFIG_MACH_ECIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECIA +# endif +# define machine_is_ecia() (machine_arch_type == MACH_TYPE_ECIA) +#else +# define machine_is_ecia() (0) +#endif + +#ifdef CONFIG_MACH_CM4008 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM4008 +# endif +# define machine_is_cm4008() (machine_arch_type == MACH_TYPE_CM4008) +#else +# define machine_is_cm4008() (0) +#endif + +#ifdef CONFIG_MACH_P2001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P2001 +# endif +# define machine_is_p2001() (machine_arch_type == MACH_TYPE_P2001) +#else +# define machine_is_p2001() (0) +#endif + +#ifdef CONFIG_MACH_TWISTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TWISTER +# endif +# define machine_is_twister() (machine_arch_type == MACH_TYPE_TWISTER) +#else +# define machine_is_twister() (0) +#endif + +#ifdef CONFIG_MACH_MUDSHARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MUDSHARK +# endif +# define machine_is_mudshark() (machine_arch_type == MACH_TYPE_MUDSHARK) +#else +# define machine_is_mudshark() (0) +#endif + +#ifdef CONFIG_MACH_HB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HB2 +# endif +# define machine_is_hb2() (machine_arch_type == MACH_TYPE_HB2) +#else +# define machine_is_hb2() (0) +#endif + +#ifdef CONFIG_MACH_IQ80332 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ80332 +# endif +# define machine_is_iq80332() (machine_arch_type == MACH_TYPE_IQ80332) +#else +# define machine_is_iq80332() (0) +#endif + +#ifdef CONFIG_MACH_SENDT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SENDT +# endif +# define machine_is_sendt() (machine_arch_type == MACH_TYPE_SENDT) +#else +# define machine_is_sendt() (0) +#endif + +#ifdef CONFIG_MACH_MX2JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX2JAZZ +# endif +# define machine_is_mx2jazz() (machine_arch_type == MACH_TYPE_MX2JAZZ) +#else +# define machine_is_mx2jazz() (0) +#endif + +#ifdef CONFIG_MACH_MULTIIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIIO +# endif +# define machine_is_multiio() (machine_arch_type == MACH_TYPE_MULTIIO) +#else +# define machine_is_multiio() (0) +#endif + +#ifdef CONFIG_MACH_HRDISPLAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HRDISPLAY +# endif +# define machine_is_hrdisplay() (machine_arch_type == MACH_TYPE_HRDISPLAY) +#else +# define machine_is_hrdisplay() (0) +#endif + +#ifdef CONFIG_MACH_SCMA11BB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCMA11BB +# endif +# define machine_is_scma11bb() (machine_arch_type == MACH_TYPE_SCMA11BB) +#else +# define machine_is_scma11bb() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS3 +# endif +# define machine_is_trizeps3() (machine_arch_type == MACH_TYPE_TRIZEPS3) +#else +# define machine_is_trizeps3() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZA +# endif +# define machine_is_zefeerdza() (machine_arch_type == MACH_TYPE_ZEFEERDZA) +#else +# define machine_is_zefeerdza() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZB +# endif +# define machine_is_zefeerdzb() (machine_arch_type == MACH_TYPE_ZEFEERDZB) +#else +# define machine_is_zefeerdzb() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZG +# endif +# define machine_is_zefeerdzg() (machine_arch_type == MACH_TYPE_ZEFEERDZG) +#else +# define machine_is_zefeerdzg() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZN +# endif +# define machine_is_zefeerdzn() (machine_arch_type == MACH_TYPE_ZEFEERDZN) +#else +# define machine_is_zefeerdzn() (0) +#endif + +#ifdef CONFIG_MACH_ZEFEERDZQ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEFEERDZQ +# endif +# define machine_is_zefeerdzq() (machine_arch_type == MACH_TYPE_ZEFEERDZQ) +#else +# define machine_is_zefeerdzq() (0) +#endif + +#ifdef CONFIG_MACH_GTWX5715 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTWX5715 +# endif +# define machine_is_gtwx5715() (machine_arch_type == MACH_TYPE_GTWX5715) +#else +# define machine_is_gtwx5715() (0) +#endif + +#ifdef CONFIG_MACH_ASTRO_JACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASTRO_JACK +# endif +# define machine_is_astro_jack() (machine_arch_type == MACH_TYPE_ASTRO_JACK) +#else +# define machine_is_astro_jack() (0) +#endif + +#ifdef CONFIG_MACH_TIP03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIP03 +# endif +# define machine_is_tip03() (machine_arch_type == MACH_TYPE_TIP03) +#else +# define machine_is_tip03() (0) +#endif + +#ifdef CONFIG_MACH_A9200EC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9200EC +# endif +# define machine_is_a9200ec() (machine_arch_type == MACH_TYPE_A9200EC) +#else +# define machine_is_a9200ec() (0) +#endif + +#ifdef CONFIG_MACH_PNX0105 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX0105 +# endif +# define machine_is_pnx0105() (machine_arch_type == MACH_TYPE_PNX0105) +#else +# define machine_is_pnx0105() (0) +#endif + +#ifdef CONFIG_MACH_ADCPOECPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADCPOECPU +# endif +# define machine_is_adcpoecpu() (machine_arch_type == MACH_TYPE_ADCPOECPU) +#else +# define machine_is_adcpoecpu() (0) +#endif + +#ifdef CONFIG_MACH_CSB637 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB637 +# endif +# define machine_is_csb637() (machine_arch_type == MACH_TYPE_CSB637) +#else +# define machine_is_csb637() (0) +#endif + +#ifdef CONFIG_MACH_ML69Q6203 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ML69Q6203 +# endif +# define machine_is_ml69q6203() (machine_arch_type == MACH_TYPE_ML69Q6203) +#else +# define machine_is_ml69q6203() (0) +#endif + +#ifdef CONFIG_MACH_MB9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB9200 +# endif +# define machine_is_mb9200() (machine_arch_type == MACH_TYPE_MB9200) +#else +# define machine_is_mb9200() (0) +#endif + +#ifdef CONFIG_MACH_KULUN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KULUN +# endif +# define machine_is_kulun() (machine_arch_type == MACH_TYPE_KULUN) +#else +# define machine_is_kulun() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER +# endif +# define machine_is_snapper() (machine_arch_type == MACH_TYPE_SNAPPER) +#else +# define machine_is_snapper() (0) +#endif + +#ifdef CONFIG_MACH_OPTIMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPTIMA +# endif +# define machine_is_optima() (machine_arch_type == MACH_TYPE_OPTIMA) +#else +# define machine_is_optima() (0) +#endif + +#ifdef CONFIG_MACH_DLHSBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DLHSBC +# endif +# define machine_is_dlhsbc() (machine_arch_type == MACH_TYPE_DLHSBC) +#else +# define machine_is_dlhsbc() (0) +#endif + +#ifdef CONFIG_MACH_X30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_X30 +# endif +# define machine_is_x30() (machine_arch_type == MACH_TYPE_X30) +#else +# define machine_is_x30() (0) +#endif + +#ifdef CONFIG_MACH_N30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N30 +# endif +# define machine_is_n30() (machine_arch_type == MACH_TYPE_N30) +#else +# define machine_is_n30() (0) +#endif + +#ifdef CONFIG_MACH_MANGA_KS8695 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MANGA_KS8695 +# endif +# define machine_is_manga_ks8695() (machine_arch_type == MACH_TYPE_MANGA_KS8695) +#else +# define machine_is_manga_ks8695() (0) +#endif + +#ifdef CONFIG_MACH_AJAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AJAX +# endif +# define machine_is_ajax() (machine_arch_type == MACH_TYPE_AJAX) +#else +# define machine_is_ajax() (0) +#endif + +#ifdef CONFIG_MACH_NEC_MP900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEC_MP900 +# endif +# define machine_is_nec_mp900() (machine_arch_type == MACH_TYPE_NEC_MP900) +#else +# define machine_is_nec_mp900() (0) +#endif + +#ifdef CONFIG_MACH_VVTK1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVTK1000 +# endif +# define machine_is_vvtk1000() (machine_arch_type == MACH_TYPE_VVTK1000) +#else +# define machine_is_vvtk1000() (0) +#endif + +#ifdef CONFIG_MACH_KAFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KAFA +# endif +# define machine_is_kafa() (machine_arch_type == MACH_TYPE_KAFA) +#else +# define machine_is_kafa() (0) +#endif + +#ifdef CONFIG_MACH_VVTK3000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVTK3000 +# endif +# define machine_is_vvtk3000() (machine_arch_type == MACH_TYPE_VVTK3000) +#else +# define machine_is_vvtk3000() (0) +#endif + +#ifdef CONFIG_MACH_PIMX1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PIMX1 +# endif +# define machine_is_pimx1() (machine_arch_type == MACH_TYPE_PIMX1) +#else +# define machine_is_pimx1() (0) +#endif + +#ifdef CONFIG_MACH_OLLIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLLIE +# endif +# define machine_is_ollie() (machine_arch_type == MACH_TYPE_OLLIE) +#else +# define machine_is_ollie() (0) +#endif + +#ifdef CONFIG_MACH_SKYMAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKYMAX +# endif +# define machine_is_skymax() (machine_arch_type == MACH_TYPE_SKYMAX) +#else +# define machine_is_skymax() (0) +#endif + +#ifdef CONFIG_MACH_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JAZZ +# endif +# define machine_is_jazz() (machine_arch_type == MACH_TYPE_JAZZ) +#else +# define machine_is_jazz() (0) +#endif + +#ifdef CONFIG_MACH_TEL_T3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEL_T3 +# endif +# define machine_is_tel_t3() (machine_arch_type == MACH_TYPE_TEL_T3) +#else +# define machine_is_tel_t3() (0) +#endif + +#ifdef CONFIG_MACH_AISINO_FCR255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AISINO_FCR255 +# endif +# define machine_is_aisino_fcr255() (machine_arch_type == MACH_TYPE_AISINO_FCR255) +#else +# define machine_is_aisino_fcr255() (0) +#endif + +#ifdef CONFIG_MACH_BTWEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTWEB +# endif +# define machine_is_btweb() (machine_arch_type == MACH_TYPE_BTWEB) +#else +# define machine_is_btweb() (0) +#endif + +#ifdef CONFIG_MACH_DBG_LH79520 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DBG_LH79520 +# endif +# define machine_is_dbg_lh79520() (machine_arch_type == MACH_TYPE_DBG_LH79520) +#else +# define machine_is_dbg_lh79520() (0) +#endif + +#ifdef CONFIG_MACH_CM41XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM41XX +# endif +# define machine_is_cm41xx() (machine_arch_type == MACH_TYPE_CM41XX) +#else +# define machine_is_cm41xx() (0) +#endif + +#ifdef CONFIG_MACH_TS72XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS72XX +# endif +# define machine_is_ts72xx() (machine_arch_type == MACH_TYPE_TS72XX) +#else +# define machine_is_ts72xx() (0) +#endif + +#ifdef CONFIG_MACH_NGGPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NGGPXA +# endif +# define machine_is_nggpxa() (machine_arch_type == MACH_TYPE_NGGPXA) +#else +# define machine_is_nggpxa() (0) +#endif + +#ifdef CONFIG_MACH_CSB535 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB535 +# endif +# define machine_is_csb535() (machine_arch_type == MACH_TYPE_CSB535) +#else +# define machine_is_csb535() (0) +#endif + +#ifdef CONFIG_MACH_CSB536 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB536 +# endif +# define machine_is_csb536() (machine_arch_type == MACH_TYPE_CSB536) +#else +# define machine_is_csb536() (0) +#endif + +#ifdef CONFIG_MACH_PXA_TRAKPOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA_TRAKPOD +# endif +# define machine_is_pxa_trakpod() (machine_arch_type == MACH_TYPE_PXA_TRAKPOD) +#else +# define machine_is_pxa_trakpod() (0) +#endif + +#ifdef CONFIG_MACH_PRAXIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRAXIS +# endif +# define machine_is_praxis() (machine_arch_type == MACH_TYPE_PRAXIS) +#else +# define machine_is_praxis() (0) +#endif + +#ifdef CONFIG_MACH_LH75411 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LH75411 +# endif +# define machine_is_lh75411() (machine_arch_type == MACH_TYPE_LH75411) +#else +# define machine_is_lh75411() (0) +#endif + +#ifdef CONFIG_MACH_OTOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTOM +# endif +# define machine_is_otom() (machine_arch_type == MACH_TYPE_OTOM) +#else +# define machine_is_otom() (0) +#endif + +#ifdef CONFIG_MACH_NEXCODER_2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXCODER_2440 +# endif +# define machine_is_nexcoder_2440() (machine_arch_type == MACH_TYPE_NEXCODER_2440) +#else +# define machine_is_nexcoder_2440() (0) +#endif + +#ifdef CONFIG_MACH_LOOX410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOOX410 +# endif +# define machine_is_loox410() (machine_arch_type == MACH_TYPE_LOOX410) +#else +# define machine_is_loox410() (0) +#endif + +#ifdef CONFIG_MACH_WESTLAKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WESTLAKE +# endif +# define machine_is_westlake() (machine_arch_type == MACH_TYPE_WESTLAKE) +#else +# define machine_is_westlake() (0) +#endif + +#ifdef CONFIG_MACH_NSB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB +# endif +# define machine_is_nsb() (machine_arch_type == MACH_TYPE_NSB) +#else +# define machine_is_nsb() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_STN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_STN +# endif +# define machine_is_esl_sarva_stn() (machine_arch_type == MACH_TYPE_ESL_SARVA_STN) +#else +# define machine_is_esl_sarva_stn() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_TFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_TFT +# endif +# define machine_is_esl_sarva_tft() (machine_arch_type == MACH_TYPE_ESL_SARVA_TFT) +#else +# define machine_is_esl_sarva_tft() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_IAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_IAD +# endif +# define machine_is_esl_sarva_iad() (machine_arch_type == MACH_TYPE_ESL_SARVA_IAD) +#else +# define machine_is_esl_sarva_iad() (0) +#endif + +#ifdef CONFIG_MACH_ESL_SARVA_ACC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_SARVA_ACC +# endif +# define machine_is_esl_sarva_acc() (machine_arch_type == MACH_TYPE_ESL_SARVA_ACC) +#else +# define machine_is_esl_sarva_acc() (0) +#endif + +#ifdef CONFIG_MACH_TYPHOON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TYPHOON +# endif +# define machine_is_typhoon() (machine_arch_type == MACH_TYPE_TYPHOON) +#else +# define machine_is_typhoon() (0) +#endif + +#ifdef CONFIG_MACH_CNAV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNAV +# endif +# define machine_is_cnav() (machine_arch_type == MACH_TYPE_CNAV) +#else +# define machine_is_cnav() (0) +#endif + +#ifdef CONFIG_MACH_A730 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A730 +# endif +# define machine_is_a730() (machine_arch_type == MACH_TYPE_A730) +#else +# define machine_is_a730() (0) +#endif + +#ifdef CONFIG_MACH_NETSTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSTAR +# endif +# define machine_is_netstar() (machine_arch_type == MACH_TYPE_NETSTAR) +#else +# define machine_is_netstar() (0) +#endif + +#ifdef CONFIG_MACH_PHASEFALE_SUPERCON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHASEFALE_SUPERCON +# endif +# define machine_is_supercon() (machine_arch_type == MACH_TYPE_PHASEFALE_SUPERCON) +#else +# define machine_is_supercon() (0) +#endif + +#ifdef CONFIG_MACH_SHIVA1100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHIVA1100 +# endif +# define machine_is_shiva1100() (machine_arch_type == MACH_TYPE_SHIVA1100) +#else +# define machine_is_shiva1100() (0) +#endif + +#ifdef CONFIG_MACH_ETEXSC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETEXSC +# endif +# define machine_is_etexsc() (machine_arch_type == MACH_TYPE_ETEXSC) +#else +# define machine_is_etexsc() (0) +#endif + +#ifdef CONFIG_MACH_IXDPG465 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDPG465 +# endif +# define machine_is_ixdpg465() (machine_arch_type == MACH_TYPE_IXDPG465) +#else +# define machine_is_ixdpg465() (0) +#endif + +#ifdef CONFIG_MACH_A9M2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M2410 +# endif +# define machine_is_a9m2410() (machine_arch_type == MACH_TYPE_A9M2410) +#else +# define machine_is_a9m2410() (0) +#endif + +#ifdef CONFIG_MACH_A9M2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M2440 +# endif +# define machine_is_a9m2440() (machine_arch_type == MACH_TYPE_A9M2440) +#else +# define machine_is_a9m2440() (0) +#endif + +#ifdef CONFIG_MACH_A9M9750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M9750 +# endif +# define machine_is_a9m9750() (machine_arch_type == MACH_TYPE_A9M9750) +#else +# define machine_is_a9m9750() (0) +#endif + +#ifdef CONFIG_MACH_A9M9360 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9M9360 +# endif +# define machine_is_a9m9360() (machine_arch_type == MACH_TYPE_A9M9360) +#else +# define machine_is_a9m9360() (0) +#endif + +#ifdef CONFIG_MACH_UNC90 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNC90 +# endif +# define machine_is_unc90() (machine_arch_type == MACH_TYPE_UNC90) +#else +# define machine_is_unc90() (0) +#endif + +#ifdef CONFIG_MACH_ECO920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECO920 +# endif +# define machine_is_eco920() (machine_arch_type == MACH_TYPE_ECO920) +#else +# define machine_is_eco920() (0) +#endif + +#ifdef CONFIG_MACH_SATVIEW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SATVIEW +# endif +# define machine_is_satview() (machine_arch_type == MACH_TYPE_SATVIEW) +#else +# define machine_is_satview() (0) +#endif + +#ifdef CONFIG_MACH_ROADRUNNER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROADRUNNER +# endif +# define machine_is_roadrunner() (machine_arch_type == MACH_TYPE_ROADRUNNER) +#else +# define machine_is_roadrunner() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200EK +# endif +# define machine_is_at91rm9200ek() (machine_arch_type == MACH_TYPE_AT91RM9200EK) +#else +# define machine_is_at91rm9200ek() (0) +#endif + +#ifdef CONFIG_MACH_GP32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GP32 +# endif +# define machine_is_gp32() (machine_arch_type == MACH_TYPE_GP32) +#else +# define machine_is_gp32() (0) +#endif + +#ifdef CONFIG_MACH_GEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEM +# endif +# define machine_is_gem() (machine_arch_type == MACH_TYPE_GEM) +#else +# define machine_is_gem() (0) +#endif + +#ifdef CONFIG_MACH_I858 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I858 +# endif +# define machine_is_i858() (machine_arch_type == MACH_TYPE_I858) +#else +# define machine_is_i858() (0) +#endif + +#ifdef CONFIG_MACH_HX2750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HX2750 +# endif +# define machine_is_hx2750() (machine_arch_type == MACH_TYPE_HX2750) +#else +# define machine_is_hx2750() (0) +#endif + +#ifdef CONFIG_MACH_ZEUSEVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZEUSEVB +# endif +# define machine_is_zeusevb() (machine_arch_type == MACH_TYPE_ZEUSEVB) +#else +# define machine_is_zeusevb() (0) +#endif + +#ifdef CONFIG_MACH_P700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P700 +# endif +# define machine_is_p700() (machine_arch_type == MACH_TYPE_P700) +#else +# define machine_is_p700() (0) +#endif + +#ifdef CONFIG_MACH_CPE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPE +# endif +# define machine_is_cpe() (machine_arch_type == MACH_TYPE_CPE) +#else +# define machine_is_cpe() (0) +#endif + +#ifdef CONFIG_MACH_SPITZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPITZ +# endif +# define machine_is_spitz() (machine_arch_type == MACH_TYPE_SPITZ) +#else +# define machine_is_spitz() (0) +#endif + +#ifdef CONFIG_MACH_NIMBRA340 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMBRA340 +# endif +# define machine_is_nimbra340() (machine_arch_type == MACH_TYPE_NIMBRA340) +#else +# define machine_is_nimbra340() (0) +#endif + +#ifdef CONFIG_MACH_LPC22XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC22XX +# endif +# define machine_is_lpc22xx() (machine_arch_type == MACH_TYPE_LPC22XX) +#else +# define machine_is_lpc22xx() (0) +#endif + +#ifdef CONFIG_MACH_COMET3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMET3 +# endif +# define machine_is_omap_comet3() (machine_arch_type == MACH_TYPE_COMET3) +#else +# define machine_is_omap_comet3() (0) +#endif + +#ifdef CONFIG_MACH_COMET4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMET4 +# endif +# define machine_is_omap_comet4() (machine_arch_type == MACH_TYPE_COMET4) +#else +# define machine_is_omap_comet4() (0) +#endif + +#ifdef CONFIG_MACH_CSB625 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB625 +# endif +# define machine_is_csb625() (machine_arch_type == MACH_TYPE_CSB625) +#else +# define machine_is_csb625() (0) +#endif + +#ifdef CONFIG_MACH_FORTUNET2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FORTUNET2 +# endif +# define machine_is_fortunet2() (machine_arch_type == MACH_TYPE_FORTUNET2) +#else +# define machine_is_fortunet2() (0) +#endif + +#ifdef CONFIG_MACH_S5H2200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5H2200 +# endif +# define machine_is_s5h2200() (machine_arch_type == MACH_TYPE_S5H2200) +#else +# define machine_is_s5h2200() (0) +#endif + +#ifdef CONFIG_MACH_OPTORM920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPTORM920 +# endif +# define machine_is_optorm920() (machine_arch_type == MACH_TYPE_OPTORM920) +#else +# define machine_is_optorm920() (0) +#endif + +#ifdef CONFIG_MACH_ADSBITSYXB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSBITSYXB +# endif +# define machine_is_adsbitsyxb() (machine_arch_type == MACH_TYPE_ADSBITSYXB) +#else +# define machine_is_adsbitsyxb() (0) +#endif + +#ifdef CONFIG_MACH_ADSSPHERE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSSPHERE +# endif +# define machine_is_adssphere() (machine_arch_type == MACH_TYPE_ADSSPHERE) +#else +# define machine_is_adssphere() (0) +#endif + +#ifdef CONFIG_MACH_ADSPORTAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSPORTAL +# endif +# define machine_is_adsportal() (machine_arch_type == MACH_TYPE_ADSPORTAL) +#else +# define machine_is_adsportal() (0) +#endif + +#ifdef CONFIG_MACH_LN2410SBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LN2410SBC +# endif +# define machine_is_ln2410sbc() (machine_arch_type == MACH_TYPE_LN2410SBC) +#else +# define machine_is_ln2410sbc() (0) +#endif + +#ifdef CONFIG_MACH_CB3RUFC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CB3RUFC +# endif +# define machine_is_cb3rufc() (machine_arch_type == MACH_TYPE_CB3RUFC) +#else +# define machine_is_cb3rufc() (0) +#endif + +#ifdef CONFIG_MACH_MP2USB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP2USB +# endif +# define machine_is_mp2usb() (machine_arch_type == MACH_TYPE_MP2USB) +#else +# define machine_is_mp2usb() (0) +#endif + +/* + * These have not yet been registered + */ +/* #define MACH_TYPE_367 <> */ +#define machine_is_esl_wireless_tab() (0) + +#ifndef machine_arch_type +#define machine_arch_type __machine_arch_type +#endif + +#endif diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h new file mode 100644 index 0000000..c3b2afd --- /dev/null +++ b/include/asm-arm/memory.h @@ -0,0 +1,137 @@ +/* + * linux/include/asm-arm/memory.h + * + * Copyright (C) 2000-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: this file should not be included by non-asm/.h files + */ +#ifndef __ASM_ARM_MEMORY_H +#define __ASM_ARM_MEMORY_H + +#if 0 /* XXX###XXX */ + +#include +#include + +/* + * PFNs are used to describe any physical page; this means + * PFN 0 == physical address 0. + * + * This is the PFN of the first RAM page in the kernel + * direct-mapped view. We assume this is the first page + * of RAM in the mem_map as well. + */ +#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) + +/* + * These are *only* valid on the kernel direct mapped RAM memory. + */ +static inline unsigned long virt_to_phys(void *x) +{ + return __virt_to_phys((unsigned long)(x)); +} + +static inline void *phys_to_virt(unsigned long x) +{ + return (void *)(__phys_to_virt((unsigned long)(x))); +} + +#define __pa(x) __virt_to_phys((unsigned long)(x)) +#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) + +/* + * Virtual <-> DMA view memory address translations + * Again, these are *only* valid on the kernel direct mapped RAM + * memory. Use of these is *depreciated*. + */ +#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) +#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) + +/* + * Conversion between a struct page and a physical address. + * + * Note: when converting an unknown physical address to a + * struct page, the resulting pointer must be validated + * using VALID_PAGE(). It must return an invalid struct page + * for any physical address not corresponding to a system + * RAM address. + * + * page_to_pfn(page) convert a struct page * to a PFN number + * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * + * pfn_valid(pfn) indicates whether a PFN number is valid + * + * virt_to_page(k) convert a _valid_ virtual address to struct page * + * virt_addr_valid(k) indicates whether a virtual address is valid + */ +#ifndef CONFIG_DISCONTIGMEM + +#define page_to_pfn(page) (((page) - mem_map) + PHYS_PFN_OFFSET) +#define pfn_to_page(pfn) ((mem_map + (pfn)) - PHYS_PFN_OFFSET) +#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) + +#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) +#define virt_addr_valid(kaddr) ((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory) + +#define PHYS_TO_NID(addr) (0) + +#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) + +#else + +/* + * This is more complex. We have a set of mem_map arrays spread + * around in memory. + */ +#define page_to_pfn(page) \ + (((page) - page_zone(page)->zone_mem_map) \ + + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT)) + +#define pfn_to_page(pfn) \ + (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT)) + +#define pfn_valid(pfn) \ + ({ \ + unsigned int node = PFN_TO_NID(pfn); \ + struct pglist_data *nd = NODE_DATA(node); \ + ((node < NR_NODES) && \ + ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\ + }) + +#define virt_to_page(kaddr) \ + (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) + +#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < NR_NODES) + +/* + * Common discontigmem stuff. + * PHYS_TO_NID is used by the ARM kernel/setup.c + */ +#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) + +/* + * 2.4 compatibility + * + * VALID_PAGE returns a non-zero value if given page pointer is valid. + * This assumes all node's mem_maps are stored within the node they + * refer to. This is actually inherently buggy. + */ +#define VALID_PAGE(page) \ +({ unsigned int node = KVADDR_TO_NID(page); \ + ((node < NR_NODES) && \ + ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \ +}) + +#endif + +/* + * We should really eliminate virt_to_bus() here - it's depreciated. + */ +#define page_to_bus(page) (virt_to_bus(page_address(page))) + +#endif /* XXX###XXX */ + +#endif /* __ASM_ARM_MEMORY_H */ diff --git a/include/asm-arm/posix_types.h b/include/asm-arm/posix_types.h new file mode 100644 index 0000000..c412486 --- /dev/null +++ b/include/asm-arm/posix_types.h @@ -0,0 +1,79 @@ +/* + * linux/include/asm-arm/posix_types.h + * + * Copyright (C) 1996-1998 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + */ +#ifndef __ARCH_ARM_POSIX_TYPES_H +#define __ARCH_ARM_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) + +#endif + +#endif diff --git a/include/asm-arm/proc-armv/domain.h b/include/asm-arm/proc-armv/domain.h new file mode 100644 index 0000000..aadc831 --- /dev/null +++ b/include/asm-arm/proc-armv/domain.h @@ -0,0 +1,50 @@ +/* + * linux/include/asm-arm/proc-armv/domain.h + * + * Copyright (C) 1999 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROC_DOMAIN_H +#define __ASM_PROC_DOMAIN_H + +/* + * Domain numbers + * + * DOMAIN_IO - domain 2 includes all IO only + * DOMAIN_KERNEL - domain 1 includes all kernel memory only + * DOMAIN_USER - domain 0 includes all user memory only + */ +#define DOMAIN_USER 0 +#define DOMAIN_KERNEL 1 +#define DOMAIN_TABLE 1 +#define DOMAIN_IO 2 + +/* + * Domain types + */ +#define DOMAIN_NOACCESS 0 +#define DOMAIN_CLIENT 1 +#define DOMAIN_MANAGER 3 + +#define domain_val(dom,type) ((type) << 2*(dom)) + +#define set_domain(x) \ + do { \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c3, c0 @ set domain" \ + : : "r" (x)); \ + } while (0) + +#define modify_domain(dom,type) \ + do { \ + unsigned int domain = current->thread.domain; \ + domain &= ~domain_val(dom, DOMAIN_MANAGER); \ + domain |= domain_val(dom, type); \ + current->thread.domain = domain; \ + set_domain(current->thread.domain); \ + } while (0) + +#endif diff --git a/include/asm-arm/proc-armv/processor.h b/include/asm-arm/proc-armv/processor.h new file mode 100644 index 0000000..5bfab7f --- /dev/null +++ b/include/asm-arm/proc-armv/processor.h @@ -0,0 +1,74 @@ +/* + * linux/include/asm-arm/proc-armv/processor.h + * + * Copyright (C) 1996-1999 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 20-09-1996 RMK Created + * 26-09-1996 RMK Added 'EXTRA_THREAD_STRUCT*' + * 28-09-1996 RMK Moved start_thread into the processor dependencies + * 09-09-1998 PJB Delete redundant `wp_works_ok' + * 30-05-1999 PJB Save sl across context switches + * 31-07-1999 RMK Added 'domain' stuff + */ +#ifndef __ASM_PROC_PROCESSOR_H +#define __ASM_PROC_PROCESSOR_H + +#include + +#define KERNEL_STACK_SIZE PAGE_SIZE + +struct context_save_struct { + unsigned long cpsr; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long sl; + unsigned long fp; + unsigned long pc; +}; + +#define INIT_CSS (struct context_save_struct){ SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + +#define EXTRA_THREAD_STRUCT \ + unsigned int domain; + +#define EXTRA_THREAD_STRUCT_INIT \ + domain: domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \ + domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_IO, DOMAIN_CLIENT) + +#define start_thread(regs,pc,sp) \ +({ \ + unsigned long *stack = (unsigned long *)sp; \ + set_fs(USER_DS); \ + memzero(regs->uregs, sizeof(regs->uregs)); \ + if (current->personality & ADDR_LIMIT_32BIT) \ + regs->ARM_cpsr = USR_MODE; \ + else \ + regs->ARM_cpsr = USR26_MODE; \ + regs->ARM_pc = pc; /* pc */ \ + regs->ARM_sp = sp; /* sp */ \ + regs->ARM_r2 = stack[2]; /* r2 (envp) */ \ + regs->ARM_r1 = stack[1]; /* r1 (argv) */ \ + regs->ARM_r0 = stack[0]; /* r0 (argc) */ \ +}) + +#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019]) +#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1017]) + +/* Allocation and freeing of basic task resources. */ +/* + * NOTE! The task struct and the stack go together + */ +#define ll_alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define ll_free_task_struct(p) free_pages((unsigned long)(p),1) + +#endif diff --git a/include/asm-arm/proc-armv/ptrace.h b/include/asm-arm/proc-armv/ptrace.h new file mode 100644 index 0000000..79cc644 --- /dev/null +++ b/include/asm-arm/proc-armv/ptrace.h @@ -0,0 +1,109 @@ +/* + * linux/include/asm-arm/proc-armv/ptrace.h + * + * Copyright (C) 1996-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROC_PTRACE_H +#define __ASM_PROC_PTRACE_H + +#include + +#define USR26_MODE 0x00 +#define FIQ26_MODE 0x01 +#define IRQ26_MODE 0x02 +#define SVC26_MODE 0x03 +#define USR_MODE 0x10 +#define FIQ_MODE 0x11 +#define IRQ_MODE 0x12 +#define SVC_MODE 0x13 +#define ABT_MODE 0x17 +#define UND_MODE 0x1b +#define SYSTEM_MODE 0x1f +#define MODE_MASK 0x1f +#define T_BIT 0x20 +#define F_BIT 0x40 +#define I_BIT 0x80 +#define CC_V_BIT (1 << 28) +#define CC_C_BIT (1 << 29) +#define CC_Z_BIT (1 << 30) +#define CC_N_BIT (1 << 31) +#define PCMASK 0 + +#ifndef __ASSEMBLY__ + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +struct pt_regs { + long uregs[18]; +}; + +#define ARM_cpsr uregs[16] +#define ARM_pc uregs[15] +#define ARM_lr uregs[14] +#define ARM_sp uregs[13] +#define ARM_ip uregs[12] +#define ARM_fp uregs[11] +#define ARM_r10 uregs[10] +#define ARM_r9 uregs[9] +#define ARM_r8 uregs[8] +#define ARM_r7 uregs[7] +#define ARM_r6 uregs[6] +#define ARM_r5 uregs[5] +#define ARM_r4 uregs[4] +#define ARM_r3 uregs[3] +#define ARM_r2 uregs[2] +#define ARM_r1 uregs[1] +#define ARM_r0 uregs[0] +#define ARM_ORIG_r0 uregs[17] + +#ifdef __KERNEL__ + +#define user_mode(regs) \ + (((regs)->ARM_cpsr & 0xf) == 0) + +#ifdef CONFIG_ARM_THUMB +#define thumb_mode(regs) \ + (((regs)->ARM_cpsr & T_BIT)) +#else +#define thumb_mode(regs) (0) +#endif + +#define processor_mode(regs) \ + ((regs)->ARM_cpsr & MODE_MASK) + +#define interrupts_enabled(regs) \ + (!((regs)->ARM_cpsr & I_BIT)) + +#define fast_interrupts_enabled(regs) \ + (!((regs)->ARM_cpsr & F_BIT)) + +#define condition_codes(regs) \ + ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT)) + +/* Are the current registers suitable for user mode? + * (used to maintain security in signal handlers) + */ +static inline int valid_user_regs(struct pt_regs *regs) +{ + if ((regs->ARM_cpsr & 0xf) == 0 && + (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0) + return 1; + + /* + * Force CPSR to something logical... + */ + regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10); + + return 0; +} + +#endif /* __KERNEL__ */ + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/include/asm-arm/proc-armv/system.h b/include/asm-arm/proc-armv/system.h new file mode 100644 index 0000000..e7b0fe6 --- /dev/null +++ b/include/asm-arm/proc-armv/system.h @@ -0,0 +1,199 @@ +/* + * linux/include/asm-arm/proc-armv/system.h + * + * Copyright (C) 1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROC_SYSTEM_H +#define __ASM_PROC_SYSTEM_H + +#include + +#define set_cr(x) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c1, c0 @ set CR" \ + : : "r" (x)) + +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_W (1 << 3) /* Write buffer enable */ +#define CR_P (1 << 4) /* 32-bit exception handler */ +#define CR_D (1 << 5) /* 32-bit data address range */ +#define CR_L (1 << 6) /* Implementation defined */ +#define CD_B (1 << 7) /* Big endian */ +#define CR_S (1 << 8) /* System MMU protection */ +#define CD_R (1 << 9) /* ROM MMU protection */ +#define CR_F (1 << 10) /* Implementation defined */ +#define CR_Z (1 << 11) /* Implementation defined */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ +#define CR_RR (1 << 14) /* Round Robin cache replacement */ + +extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ +extern unsigned long cr_alignment; /* defined in entry-armv.S */ + +#if __LINUX_ARM_ARCH__ >= 4 +#define vectors_base() ((cr_alignment & CR_V) ? 0xffff0000 : 0) +#else +#define vectors_base() (0) +#endif + +/* + * Save the current interrupt enable state & disable IRQs + */ +#define local_irq_save(x) \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_save\n" \ +" orr %1, %0, #128\n" \ +" msr cpsr_c, %1" \ + : "=r" (x), "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Enable IRQs + */ +#define local_irq_enable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_enable\n" \ +" bic %0, %0, #128\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Disable IRQs + */ +#define local_irq_disable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_disable\n" \ +" orr %0, %0, #128\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Enable FIQs + */ +#define __stf() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ stf\n" \ +" bic %0, %0, #64\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Disable FIQs + */ +#define __clf() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ clf\n" \ +" orr %0, %0, #64\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory"); \ + }) + +/* + * Save the current interrupt enable state. + */ +#define local_save_flags(x) \ + ({ \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_save_flags\n" \ + : "=r" (x) \ + : \ + : "memory"); \ + }) + +/* + * restore saved IRQ & FIQ state + */ +#define local_irq_restore(x) \ + __asm__ __volatile__( \ + "msr cpsr_c, %0 @ local_irq_restore\n" \ + : \ + : "r" (x) \ + : "memory") + +#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) +/* + * On the StrongARM, "swp" is terminally broken since it bypasses the + * cache totally. This means that the cache becomes inconsistent, and, + * since we use normal loads/stores as well, this is really bad. + * Typically, this causes oopsen in filp_close, but could have other, + * more disasterous effects. There are two work-arounds: + * 1. Disable interrupts and emulate the atomic swap + * 2. Clean the cache, perform atomic swap, flush the cache + * + * We choose (1) since its the "easiest" to achieve here and is not + * dependent on the processor type. + */ +#define swp_is_buggy +#endif + +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) +{ + extern void __bad_xchg(volatile void *, int); + unsigned long ret; +#ifdef swp_is_buggy + unsigned long flags; +#endif + + switch (size) { +#ifdef swp_is_buggy + case 1: + local_irq_save(flags); + ret = *(volatile unsigned char *)ptr; + *(volatile unsigned char *)ptr = x; + local_irq_restore(flags); + break; + + case 4: + local_irq_save(flags); + ret = *(volatile unsigned long *)ptr; + *(volatile unsigned long *)ptr = x; + local_irq_restore(flags); + break; +#else + case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory"); + break; + case 4: __asm__ __volatile__ ("swp %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory"); + break; +#endif + default: __bad_xchg(ptr, size), ret = 0; + } + + return ret; +} + +#endif diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h new file mode 100644 index 0000000..445d449 --- /dev/null +++ b/include/asm-arm/processor.h @@ -0,0 +1,134 @@ +/* + * linux/include/asm-arm/processor.h + * + * Copyright (C) 1995-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARM_PROCESSOR_H +#define __ASM_ARM_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#define FP_SIZE 35 + +struct fp_hard_struct { + unsigned int save[FP_SIZE]; /* as yet undefined */ +}; + +struct fp_soft_struct { + unsigned int save[FP_SIZE]; /* undefined information */ +}; + +union fp_state { + struct fp_hard_struct hard; + struct fp_soft_struct soft; +}; + +typedef unsigned long mm_segment_t; /* domain register */ + +#ifdef __KERNEL__ + +#define EISA_bus 0 +#define MCA_bus 0 +#define MCA_bus__is_a_macro + +#include +#include +#if 0 /* XXX###XXX */ +#include +#endif /* XXX###XXX */ +#include +#include + +union debug_insn { + u32 arm; + u16 thumb; +}; + +struct debug_entry { + u32 address; + union debug_insn insn; +}; + +struct debug_info { + int nsaved; + struct debug_entry bp[2]; +}; + +struct thread_struct { + atomic_t refcount; + /* fault info */ + unsigned long address; + unsigned long trap_no; + unsigned long error_code; + /* floating point */ + union fp_state fpstate; + /* debugging */ + struct debug_info debug; + /* context info */ + struct context_save_struct *save; + EXTRA_THREAD_STRUCT +}; + +#define INIT_THREAD { \ + refcount: ATOMIC_INIT(1), \ + EXTRA_THREAD_STRUCT_INIT \ +} + +/* + * Return saved PC of a blocked thread. + */ +static inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + return t->save ? pc_pointer(t->save->pc) : 0; +} + +static inline unsigned long thread_saved_fp(struct thread_struct *t) +{ + return t->save ? t->save->fp : 0; +} + +/* Forward declaration, a strange C thing */ +struct task_struct; + +/* Free all resources held by a thread. */ +extern void release_thread(struct task_struct *); + +/* Copy and release all segment info associated with a VM */ +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define THREAD_SIZE (8192) + +extern struct task_struct *alloc_task_struct(void); +extern void __free_task_struct(struct task_struct *); +#define get_task_struct(p) atomic_inc(&(p)->thread.refcount) +#define free_task_struct(p) \ + do { \ + if (atomic_dec_and_test(&(p)->thread.refcount)) \ + __free_task_struct((p)); \ + } while (0) + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +#define cpu_relax() barrier() + +/* + * Create a new kernel thread + */ +extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +#endif + +#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h new file mode 100644 index 0000000..73c9087 --- /dev/null +++ b/include/asm-arm/ptrace.h @@ -0,0 +1,33 @@ +#ifndef __ASM_ARM_PTRACE_H +#define __ASM_ARM_PTRACE_H + +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 + +#define PTRACE_SETOPTIONS 21 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +#include + +#ifndef __ASSEMBLY__ +#define pc_pointer(v) \ + ((v) & ~PCMASK) + +#define instruction_pointer(regs) \ + (pc_pointer((regs)->ARM_pc)) + +#ifdef __KERNEL__ +extern void show_regs(struct pt_regs *); + +#define predicate(x) (x & 0xf0000000) +#define PREDICATE_ALWAYS 0xe0000000 + +#endif + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h new file mode 100644 index 0000000..89df4dc --- /dev/null +++ b/include/asm-arm/setup.h @@ -0,0 +1,269 @@ +/* + * linux/include/asm/setup.h + * + * Copyright (C) 1997-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Structure passed to kernel to tell it about the + * hardware it's running on. See linux/Documentation/arm/Setup + * for more info. + * + * NOTE: + * This file contains two ways to pass information from the boot + * loader to the kernel. The old struct param_struct is deprecated, + * but it will be kept in the kernel for 5 years from now + * (2001). This will allow boot loaders to convert to the new struct + * tag way. + */ +#ifndef __ASMARM_SETUP_H +#define __ASMARM_SETUP_H + +/* + * Usage: + * - do not go blindly adding fields, add them at the end + * - when adding fields, don't rely on the address until + * a patch from me has been released + * - unused fields should be zero (for future expansion) + * - this structure is relatively short-lived - only + * guaranteed to contain useful data in setup_arch() + */ +#define COMMAND_LINE_SIZE 1024 + +/* This is the old deprecated way to pass parameters to the kernel */ +struct param_struct { + union { + struct { + unsigned long page_size; /* 0 */ + unsigned long nr_pages; /* 4 */ + unsigned long ramdisk_size; /* 8 */ + unsigned long flags; /* 12 */ +#define FLAG_READONLY 1 +#define FLAG_RDLOAD 4 +#define FLAG_RDPROMPT 8 + unsigned long rootdev; /* 16 */ + unsigned long video_num_cols; /* 20 */ + unsigned long video_num_rows; /* 24 */ + unsigned long video_x; /* 28 */ + unsigned long video_y; /* 32 */ + unsigned long memc_control_reg; /* 36 */ + unsigned char sounddefault; /* 40 */ + unsigned char adfsdrives; /* 41 */ + unsigned char bytes_per_char_h; /* 42 */ + unsigned char bytes_per_char_v; /* 43 */ + unsigned long pages_in_bank[4]; /* 44 */ + unsigned long pages_in_vram; /* 60 */ + unsigned long initrd_start; /* 64 */ + unsigned long initrd_size; /* 68 */ + unsigned long rd_start; /* 72 */ + unsigned long system_rev; /* 76 */ + unsigned long system_serial_low; /* 80 */ + unsigned long system_serial_high; /* 84 */ + unsigned long mem_fclk_21285; /* 88 */ + } s; + char unused[256]; + } u1; + union { + char paths[8][128]; + struct { + unsigned long magic; + char n[1024 - sizeof(unsigned long)]; + } s; + } u2; + char commandline[COMMAND_LINE_SIZE]; +}; + + +/* + * The new way of passing information: a list of tagged entries + */ + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; /* bit 0 = read-only */ + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 + +struct tag_mem32 { + u32 size; + u32 start; /* physical start address */ +}; + +/* VGA text type displays */ +#define ATAG_VIDEOTEXT 0x54410003 + +struct tag_videotext { + u8 x; + u8 y; + u16 video_page; + u8 video_mode; + u8 video_cols; + u16 video_ega_bx; + u8 video_lines; + u8 video_isvga; + u16 video_points; +}; + +/* describes how the ramdisk will be used in kernel */ +#define ATAG_RAMDISK 0x54410004 + +struct tag_ramdisk { + u32 flags; /* bit 0 = load, bit 1 = prompt */ + u32 size; /* decompressed ramdisk size in _kilo_ bytes */ + u32 start; /* starting block of floppy-based RAM disk image */ +}; + +/* describes where the compressed ramdisk image lives (virtual address) */ +/* + * this one accidentally used virtual addresses - as such, + * its depreciated. + */ +#define ATAG_INITRD 0x54410005 + +/* describes where the compressed ramdisk image lives (physical address) */ +#define ATAG_INITRD2 0x54420005 + +struct tag_initrd { + u32 start; /* physical start address */ + u32 size; /* size of compressed ramdisk image in bytes */ +}; + +/* board serial number. "64 bits should be enough for everybody" */ +#define ATAG_SERIAL 0x54410006 + +struct tag_serialnr { + u32 low; + u32 high; +}; + +/* board revision */ +#define ATAG_REVISION 0x54410007 + +struct tag_revision { + u32 rev; +}; + +/* initial values for vesafb-type framebuffers. see struct screen_info + * in include/linux/tty.h + */ +#define ATAG_VIDEOLFB 0x54410008 + +struct tag_videolfb { + u16 lfb_width; + u16 lfb_height; + u16 lfb_depth; + u16 lfb_linelength; + u32 lfb_base; + u32 lfb_size; + u8 red_size; + u8 red_pos; + u8 green_size; + u8 green_pos; + u8 blue_size; + u8 blue_pos; + u8 rsvd_size; + u8 rsvd_pos; +}; + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410009 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* acorn RiscPC specific information */ +#define ATAG_ACORN 0x41000101 + +struct tag_acorn { + u32 memc_control_reg; + u32 vram_pages; + u8 sounddefault; + u8 adfsdrives; +}; + +/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ +#define ATAG_MEMCLK 0x41000402 + +struct tag_memclk { + u32 fmemclk; +}; + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem32 mem; + struct tag_videotext videotext; + struct tag_ramdisk ramdisk; + struct tag_initrd initrd; + struct tag_serialnr serialnr; + struct tag_revision revision; + struct tag_videolfb videolfb; + struct tag_cmdline cmdline; + + /* + * Acorn specific + */ + struct tag_acorn acorn; + + /* + * DC21285 specific + */ + struct tag_memclk memclk; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(const struct tag *); +}; + +#define __tag __attribute__((unused, __section__(".taglist"))) +#define __tagtable(tag, fn) \ +static struct tagtable __tagtable_##fn __tag = { tag, fn } + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +/* + * Memory map description + */ +#define NR_BANKS 8 + +struct meminfo { + int nr_banks; + unsigned long end; + struct { + unsigned long start; + unsigned long size; + int node; + } bank[NR_BANKS]; +}; + +extern struct meminfo meminfo; + +#endif diff --git a/include/asm-arm/sizes.h b/include/asm-arm/sizes.h new file mode 100644 index 0000000..f8d92ca --- /dev/null +++ b/include/asm-arm/sizes.h @@ -0,0 +1,52 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif + +/* END */ diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h new file mode 100644 index 0000000..c3ea582 --- /dev/null +++ b/include/asm-arm/string.h @@ -0,0 +1,47 @@ +#ifndef __ASM_ARM_STRING_H +#define __ASM_ARM_STRING_H + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +#undef __HAVE_ARCH_MEMSET +extern void * memset(void *, int, __kernel_size_t); + +#if 0 +extern void __memzero(void *ptr, __kernel_size_t n); + +#define memset(p,v,n) \ + ({ \ + if ((n) != 0) { \ + if (__builtin_constant_p((v)) && (v) == 0) \ + __memzero((p),(n)); \ + else \ + memset((p),(v),(n)); \ + } \ + (p); \ + }) + +#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) +#else +extern void memzero(void *ptr, __kernel_size_t n); +#endif + +#endif diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h new file mode 100644 index 0000000..13e9806 --- /dev/null +++ b/include/asm-arm/types.h @@ -0,0 +1,50 @@ +#ifndef __ASM_ARM_TYPES_H +#define __ASM_ARM_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#endif /* __KERNEL__ */ + +#endif diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h new file mode 100644 index 0000000..41e7a8f --- /dev/null +++ b/include/asm-arm/u-boot-arm.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _U_BOOT_ARM_H_ +#define _U_BOOT_ARM_H_ 1 + +/* for the following variables, see start.S */ +extern ulong _armboot_start; /* code start */ +extern ulong _bss_start; /* code + data end == BSS start */ +extern ulong _bss_end; /* BSS end */ +extern ulong IRQ_STACK_START; /* top of IRQ stack */ +extern ulong FIQ_STACK_START; /* top of FIQ stack */ + +/* cpu/.../cpu.c */ +int cpu_init(void); +int cleanup_before_linux(void); + +/* board/.../... */ +int board_init(void); +int dram_init (void); +void setup_serial_tag (struct tag **params); +void setup_revision_tag (struct tag **params); + +/* ------------------------------------------------------------ */ +/* Here is a list of some prototypes which are incompatible to */ +/* the U-Boot implementation */ +/* To be fixed! */ +/* ------------------------------------------------------------ */ +/* common/cmd_nvedit.c */ +void setenv (char *, char *); + +/* cpu/.../interrupt.c */ +void reset_timer_masked (void); +ulong get_timer_masked (void); +void udelay_masked (unsigned long usec); + +#endif /* _U_BOOT_ARM_H_ */ diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h new file mode 100644 index 0000000..146934c --- /dev/null +++ b/include/asm-arm/u-boot.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + struct environment_s *bi_env; + ulong bi_arch_number; /* unique id for this board */ + ulong bi_boot_params; /* where this board expects params */ + struct /* RAM configuration */ + { + ulong start; + ulong size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; +} bd_t; + +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +#endif /* _U_BOOT_H_ */ diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h new file mode 100644 index 0000000..b768e20 --- /dev/null +++ b/include/asm-i386/bitops.h @@ -0,0 +1,383 @@ +#ifndef _I386_BITOPS_H +#define _I386_BITOPS_H + +/* + * Copyright 1992, Linus Torvalds. + */ + + +/* + * These have to be done with inline assembly: that way the bit-setting + * is guaranteed to be atomic. All bit operations return 0 if the bit + * was cleared before the operation and != 0 if it was not. + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + */ + +#ifdef CONFIG_SMP +#define LOCK_PREFIX "lock ; " +#else +#define LOCK_PREFIX "" +#endif + +#define ADDR (*(volatile long *) addr) + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static __inline__ void set_bit(int nr, volatile void * addr) +{ + __asm__ __volatile__( LOCK_PREFIX + "btsl %1,%0" + :"=m" (ADDR) + :"Ir" (nr)); +} + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static __inline__ void __set_bit(int nr, volatile void * addr) +{ + __asm__( + "btsl %1,%0" + :"=m" (ADDR) + :"Ir" (nr)); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +static __inline__ void clear_bit(int nr, volatile void * addr) +{ + __asm__ __volatile__( LOCK_PREFIX + "btrl %1,%0" + :"=m" (ADDR) + :"Ir" (nr)); +} +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +/** + * __change_bit - Toggle a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static __inline__ void __change_bit(int nr, volatile void * addr) +{ + __asm__ __volatile__( + "btcl %1,%0" + :"=m" (ADDR) + :"Ir" (nr)); +} + +/** + * change_bit - Toggle a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static __inline__ void change_bit(int nr, volatile void * addr) +{ + __asm__ __volatile__( LOCK_PREFIX + "btcl %1,%0" + :"=m" (ADDR) + :"Ir" (nr)); +} + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static __inline__ int test_and_set_bit(int nr, volatile void * addr) +{ + int oldbit; + + __asm__ __volatile__( LOCK_PREFIX + "btsl %2,%1\n\tsbbl %0,%0" + :"=r" (oldbit),"=m" (ADDR) + :"Ir" (nr) : "memory"); + return oldbit; +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static __inline__ int __test_and_set_bit(int nr, volatile void * addr) +{ + int oldbit; + + __asm__( + "btsl %2,%1\n\tsbbl %0,%0" + :"=r" (oldbit),"=m" (ADDR) + :"Ir" (nr)); + return oldbit; +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static __inline__ int test_and_clear_bit(int nr, volatile void * addr) +{ + int oldbit; + + __asm__ __volatile__( LOCK_PREFIX + "btrl %2,%1\n\tsbbl %0,%0" + :"=r" (oldbit),"=m" (ADDR) + :"Ir" (nr) : "memory"); + return oldbit; +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +{ + int oldbit; + + __asm__( + "btrl %2,%1\n\tsbbl %0,%0" + :"=r" (oldbit),"=m" (ADDR) + :"Ir" (nr)); + return oldbit; +} + +/* WARNING: non atomic and it can be reordered! */ +static __inline__ int __test_and_change_bit(int nr, volatile void * addr) +{ + int oldbit; + + __asm__ __volatile__( + "btcl %2,%1\n\tsbbl %0,%0" + :"=r" (oldbit),"=m" (ADDR) + :"Ir" (nr) : "memory"); + return oldbit; +} + +/** + * test_and_change_bit - Change a bit and return its new value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static __inline__ int test_and_change_bit(int nr, volatile void * addr) +{ + int oldbit; + + __asm__ __volatile__( LOCK_PREFIX + "btcl %2,%1\n\tsbbl %0,%0" + :"=r" (oldbit),"=m" (ADDR) + :"Ir" (nr) : "memory"); + return oldbit; +} + +#if 0 /* Fool kernel-doc since it doesn't do macros yet */ +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static int test_bit(int nr, const volatile void * addr); +#endif + +static __inline__ int constant_test_bit(int nr, const volatile void * addr) +{ + return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; +} + +static __inline__ int variable_test_bit(int nr, volatile void * addr) +{ + int oldbit; + + __asm__ __volatile__( + "btl %2,%1\n\tsbbl %0,%0" + :"=r" (oldbit) + :"m" (ADDR),"Ir" (nr)); + return oldbit; +} + +#define test_bit(nr,addr) \ +(__builtin_constant_p(nr) ? \ + constant_test_bit((nr),(addr)) : \ + variable_test_bit((nr),(addr))) + +/** + * find_first_zero_bit - find the first zero bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit-number of the first zero bit, not the number of the byte + * containing a bit. + */ +static __inline__ int find_first_zero_bit(void * addr, unsigned size) +{ + int d0, d1, d2; + int res; + + if (!size) + return 0; + /* This looks at memory. Mark it volatile to tell gcc not to move it around */ + __asm__ __volatile__( + "movl $-1,%%eax\n\t" + "xorl %%edx,%%edx\n\t" + "repe; scasl\n\t" + "je 1f\n\t" + "xorl -4(%%edi),%%eax\n\t" + "subl $4,%%edi\n\t" + "bsfl %%eax,%%edx\n" + "1:\tsubl %%ebx,%%edi\n\t" + "shll $3,%%edi\n\t" + "addl %%edi,%%edx" + :"=d" (res), "=&c" (d0), "=&D" (d1), "=&a" (d2) + :"1" ((size + 31) >> 5), "2" (addr), "b" (addr)); + return res; +} + +/** + * find_next_zero_bit - find the first zero bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The maximum size to search + */ +static __inline__ int find_next_zero_bit (void * addr, int size, int offset) +{ + unsigned long * p = ((unsigned long *) addr) + (offset >> 5); + int set = 0, bit = offset & 31, res; + + if (bit) { + /* + * Look for zero in first byte + */ + __asm__("bsfl %1,%0\n\t" + "jne 1f\n\t" + "movl $32, %0\n" + "1:" + : "=r" (set) + : "r" (~(*p >> bit))); + if (set < (32 - bit)) + return set + offset; + set = 32 - bit; + p++; + } + /* + * No zero yet, search remaining full bytes for a zero + */ + res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr)); + return (offset + set + res); +} + +/** + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + */ +static __inline__ unsigned long ffz(unsigned long word) +{ + __asm__("bsfl %1,%0" + :"=r" (word) + :"r" (~word)); + return word; +} + +#ifdef __KERNEL__ + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static __inline__ int ffs(int x) +{ + int r; + + __asm__("bsfl %1,%0\n\t" + "jnz 1f\n\t" + "movl $-1,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r+1; +} + +/** + * hweightN - returns the hamming weight of a N-bit word + * @x: the word to weigh + * + * The Hamming Weight of a number is the total number of bits set in it. + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#endif /* __KERNEL__ */ + +#ifdef __KERNEL__ + +#define ext2_set_bit __test_and_set_bit +#define ext2_clear_bit __test_and_clear_bit +#define ext2_test_bit test_bit +#define ext2_find_first_zero_bit find_first_zero_bit +#define ext2_find_next_zero_bit find_next_zero_bit + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) __test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) __set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) __test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +#endif /* __KERNEL__ */ + +#endif /* _I386_BITOPS_H */ diff --git a/include/asm-i386/byteorder.h b/include/asm-i386/byteorder.h new file mode 100644 index 0000000..a9c69d5 --- /dev/null +++ b/include/asm-i386/byteorder.h @@ -0,0 +1,43 @@ +#ifndef _I386_BYTEORDER_H +#define _I386_BYTEORDER_H + +#include + +#ifdef __GNUC__ + + +static __inline__ __const__ __u32 ___arch__swab32(__u32 x) +{ +#ifdef CONFIG_X86_BSWAP + __asm__("bswap %0" : "=r" (x) : "0" (x)); +#else + __asm__("xchgb %b0,%h0\n\t" /* swap lower bytes */ + "rorl $16,%0\n\t" /* swap words */ + "xchgb %b0,%h0" /* swap higher bytes */ + :"=q" (x) + : "0" (x)); +#endif + return x; +} + +static __inline__ __const__ __u16 ___arch__swab16(__u16 x) +{ + __asm__("xchgb %b0,%h0" /* swap bytes */ \ + : "=q" (x) \ + : "0" (x)); \ + return x; +} + +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#endif /* __GNUC__ */ + +#include + +#endif /* _I386_BYTEORDER_H */ diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h new file mode 100644 index 0000000..1d309d5 --- /dev/null +++ b/include/asm-i386/global_data.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long bus_clk; + unsigned long ram_size; /* RAM size */ + unsigned long reset_status; /* reset status register at boot */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +extern gd_t *global_data; + +#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data + +#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-i386/i8254.h b/include/asm-i386/i8254.h new file mode 100644 index 0000000..aafdfb8 --- /dev/null +++ b/include/asm-i386/i8254.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +/* i8254.h Intel 8254 PIT registers */ + + +#ifndef _ASMI386_I8254_H_ +#define _ASMI386_I8954_H_ 1 + + +#define PIT_T0 0x00 /* PIT channel 0 count/status */ +#define PIT_T1 0x01 /* PIT channel 1 count/status */ +#define PIT_T2 0x02 /* PIT channel 2 count/status */ +#define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */ + +/* PIT Command Register Bit Definitions */ + +#define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */ +#define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */ +#define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */ + +#define PIT_CMD_LATCH 0x00 /* Counter Latch Command */ +#define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */ +#define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */ +#define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */ + +#define PIT_CMD_MODE0 0x00 /* Select mode 0 */ +#define PIT_CMD_MODE1 0x02 /* Select mode 1 */ +#define PIT_CMD_MODE2 0x04 /* Select mode 2 */ +#define PIT_CMD_MODE3 0x06 /* Select mode 3 */ +#define PIT_CMD_MODE4 0x08 /* Select mode 4 */ +#define PIT_CMD_MODE5 0x0A /* Select mode 5 */ + +#endif diff --git a/include/asm-i386/i8259.h b/include/asm-i386/i8259.h new file mode 100644 index 0000000..774d7a3 --- /dev/null +++ b/include/asm-i386/i8259.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* i8259.h i8259 PIC Registers */ + +#ifndef _ASMI386_I8259_H_ +#define _ASMI386_I8959_H_ 1 + + +/* PIC I/O mapped registers */ + +#define IRR 0x0 /* Interrupt Request Register */ +#define ISR 0x0 /* In-Service Register */ +#define ICW1 0x0 /* Initialization Control Word 1 */ +#define OCW2 0x0 /* Operation Control Word 2 */ +#define OCW3 0x0 /* Operation Control Word 3 */ +#define ICW2 0x1 /* Initialization Control Word 2 */ +#define ICW3 0x1 /* Initialization Control Word 3 */ +#define ICW4 0x1 /* Initialization Control Word 4 */ +#define IMR 0x1 /* Interrupt Mask Register */ + +/* bits for IRR, IMR, ISR and ICW3 */ +#define IR7 0x80 /* IR7 */ +#define IR6 0x40 /* IR6 */ +#define IR5 0x20 /* IR5 */ +#define IR4 0x10 /* IR4 */ +#define IR3 0x08 /* IR3 */ +#define IR2 0x04 /* IR2 */ +#define IR1 0x02 /* IR1 */ +#define IR0 0x01 /* IR0 */ + +/* bits for SEOI */ +#define SEOI_IR7 0x07 /* IR7 */ +#define SEOI_IR6 0x06 /* IR6 */ +#define SEOI_IR5 0x05 /* IR5 */ +#define SEOI_IR4 0x04 /* IR4 */ +#define SEOI_IR3 0x03 /* IR3 */ +#define SEOI_IR2 0x02 /* IR2 */ +#define SEOI_IR1 0x01 /* IR1 */ +#define SEOI_IR0 0x00 /* IR0 */ + +/* OCW2 bits */ +#define OCW2_RCLR 0x00 /* Rotate/clear */ +#define OCW2_NEOI 0x20 /* Non specific EOI */ +#define OCW2_NOP 0x40 /* NOP */ +#define OCW2_SEOI 0x60 /* Specific EOI */ +#define OCW2_RSET 0x80 /* Rotate/set */ +#define OCW2_REOI 0xA0 /* Rotate on non specific EOI */ +#define OCW2_PSET 0xC0 /* Priority Set Command */ +#define OCW2_RSEOI 0xE0 /* Rotate on specific EOI */ + +/* ICW1 bits */ +#define ICW1_SEL 0x10 /* Select ICW1 */ +#define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */ +#define ICW1_ADI 0x04 /* Address Interval */ +#define ICW1_SNGL 0x02 /* Single PIC */ +#define ICW1_EICW4 0x01 /* Expect initilization ICW4 */ + +/* ICW2 is the starting vector number */ + +/* ICW2 is bit-mask of present slaves for a master device, + * or the slave ID for a slave device */ + +/* ICW4 bits */ +#define ICW4_AEOI 0x02 /* Automatic EOI Mode */ +#define ICW4_PM 0x01 /* Microprocessor Mode */ + +#endif diff --git a/include/asm-i386/ibmpc.h b/include/asm-i386/ibmpc.h new file mode 100644 index 0000000..e35cbd8 --- /dev/null +++ b/include/asm-i386/ibmpc.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_IBMPC_H_ +#define __ASM_IBMPC_H_ 1 + +/* misc ports in an ibm compatible pc */ + +#define MASTER_PIC 0x20 +#define PIT_BASE 0x40 +#define KBDDATA 0x60 +#define SYSCTLB 0x62 +#define KBDCMD 0x64 +#define SYSCTLA 0x92 +#define SLAVE_PIC 0xa0 + +#if 1 +#define UART0_BASE 0x3f8 +#define UART1_BASE 0x2f8 +#else +/* FixMe: uarts swapped */ +#define UART0_BASE 0x2f8 +#define UART1_BASE 0x3f8 +#endif + + +#endif diff --git a/include/asm-i386/ic/ali512x.h b/include/asm-i386/ic/ali512x.h new file mode 100644 index 0000000..5bc1bd7 --- /dev/null +++ b/include/asm-i386/ic/ali512x.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_IC_ALI512X_H_ +#define __ASM_IC_ALI512X_H_ + +# define ALI_INDEX 0x3f0 +# define ALI_DATA 0x3f1 + +# define ALI_ENABLED 1 +# define ALI_DISABLED 0 + +# define ALI_UART1 0 +# define ALI_UART2 1 + +/* setup functions */ +void ali512x_init(void); +void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel); +void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel); +void ali512x_set_uart(int enabled, int index, u16 io, u8 irq); +void ali512x_set_rtc(int enabled, u16 io, u8 irq); +void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq); +void ali512x_set_cio(int enabled); + + +/* common I/O functions */ +void ali512x_cio_function(int pin, int special, int inv, int input); +void ali512x_cio_out(int pin, int value); +int ali512x_cio_in(int pin); + +/* misc features */ +void ali512x_set_uart2_irda(int enabled); + +#endif diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h new file mode 100644 index 0000000..d5abbbe --- /dev/null +++ b/include/asm-i386/ic/sc520.h @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_IC_SC520_H_ +#define _ASM_IC_SC520_H_ 1 + +/* Memory mapped configuration registers, MMCR */ +#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */ +#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */ +#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */ +#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */ +#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/ +#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/ +#define SC520_ECCCTL 0x0020 /* ECC Control Register */ +#define SC520_ECCSTA 0x0021 /* ECC Status Register */ +#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */ +#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */ +#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ +#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */ +#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */ +#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */ +#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */ +#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */ +#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */ +#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */ +#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */ +#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */ +#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */ +#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */ +#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */ +#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */ +#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */ +#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */ +#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */ +#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */ +#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */ +#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */ +#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */ +#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */ +#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */ +#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */ +#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */ +#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */ +#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */ +#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */ +#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */ +#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */ +#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ +#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ +#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */ +#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */ +#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */ +#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */ +#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */ +#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */ +#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */ +#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */ +#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */ +#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */ +#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */ +#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */ +#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */ +#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */ +#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */ +#define SC520_CLKSEL 0x0c26 /* Clock Select */ +#define SC520_DSCTL 0x0c28 /* Drive Strength Control */ +#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */ +#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */ +#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */ +#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */ +#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */ +#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */ +#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */ +#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */ +#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ +#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ +#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */ +#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */ +#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */ +#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */ +#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */ +#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */ +#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */ +#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */ +#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */ +#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */ +#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */ +#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */ +#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */ +#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */ +#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */ +#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */ +#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */ +#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */ +#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */ +#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */ +#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */ +#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */ +#define SC520_SSICTL 0x0cd0 /* SSI Control */ +#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */ +#define SC520_SSICMD 0x0cd2 /* SSI Command */ +#define SC520_SSISTA 0x0cd3 /* SSI Status */ +#define SC520_SSIRCV 0x0cd4 /* SSI Receive */ +#define SC520_PICICR 0x0d00 /* Interrupt Control Register */ +#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */ +#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */ +#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */ +#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */ +#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */ +#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */ +#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */ +#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */ +#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */ +#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */ +#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */ +#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */ +#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */ +#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */ +#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */ +#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */ +#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */ +#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */ +#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */ +#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */ +#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */ +#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */ +#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */ +#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */ +#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */ +#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */ +#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */ +#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */ +#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */ +#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */ +#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */ +#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */ +#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */ +#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */ +#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */ +#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */ +#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */ +#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */ +#define SC520_SYSINFO 0x0d70 /* System Board Information Register */ +#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */ +#define SC520_RESSTA 0x0d74 /* Reset Status Register */ +#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */ +#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */ +#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */ +#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */ +#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */ +#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */ +#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */ +#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */ +#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */ +#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */ +#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */ +#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */ +#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */ +#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */ +#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */ +#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */ +#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */ +#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */ +#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */ +#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */ +#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */ +#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */ +#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */ +#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */ +#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */ +#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */ +#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */ +#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */ +#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */ +#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */ + +/* MMCR Register bits (not all of them :) ) */ + +/* SSI Stuff */ +#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ +#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ +#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ +#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ +#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ +#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ +#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ +#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */ + +#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ +#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ +#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ +#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */ + +#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ +#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ +#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ +#define SSISTA_BSY 0x02 /* SSI Busy */ +#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ + + +/* BITS for SC520_ADDDECCTL: */ +#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ +#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ +#define RTC_DIS 0x04 /* RTC Disable */ +#define UART2_DIS 0x02 /* UART2 Disable */ +#define UART1_DIS 0x01 /* UART1 Disable */ + +/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ +#define SC520_REG_ADDR 0x00000cf8 +#define SC520_REG_DATA 0x00000cfc + + +#define SC520_ISA_MEM_PHYS 0x00000000 +#define SC520_ISA_MEM_BUS 0x00000000 +#define SC520_ISA_MEM_SIZE 0x01000000 + +#define SC520_ISA_IO_PHYS 0x00000000 +#define SC520_ISA_IO_BUS 0x00000000 +#define SC520_ISA_IO_SIZE 0x00001000 + +/* PCI I/O space from 0x1000 to 0xdfff + * (make 0xe000-0xfdff available for stuff like PCCard boot) */ +#define SC520_PCI_IO_PHYS 0x00001000 +#define SC520_PCI_IO_BUS 0x00001000 +#define SC520_PCI_IO_SIZE 0x0000d000 + +/* system memory from 0x00000000 to 0x0fffffff */ +#define SC520_PCI_MEMORY_PHYS 0x00000000 +#define SC520_PCI_MEMORY_BUS 0x00000000 +#define SC520_PCI_MEMORY_SIZE 0x10000000 + +/* PCI bus memory from 0x10000000 to 0x26ffffff + * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ +#define SC520_PCI_MEM_PHYS 0x10000000 +#define SC520_PCI_MEM_BUS 0x10000000 +#define SC520_PCI_MEM_SIZE 0x17000000 + +/* 0x28000000 - 0x3fffffff is used by the flash banks */ + +/* 0x40000000 - 0xffffffff is not adressable by the SC520 */ + +/* priority numbers used for interrupt channel mappings */ +#define SC520_IRQ_DISABLED 0 +#define SC520_IRQ0 1 +#define SC520_IRQ1 2 +#define SC520_IRQ2 4 /* same as IRQ9 */ +#define SC520_IRQ3 11 +#define SC520_IRQ4 12 +#define SC520_IRQ5 13 +#define SC520_IRQ6 21 +#define SC520_IRQ7 22 +#define SC520_IRQ8 3 +#define SC520_IRQ9 4 +#define SC520_IRQ10 5 +#define SC520_IRQ11 6 +#define SC520_IRQ12 7 +#define SC520_IRQ13 8 +#define SC520_IRQ14 9 +#define SC520_IRQ15 10 + + +/* pin number used for PCI interrupt mappings */ +#define SC520_PCI_INTA 0 +#define SC520_PCI_INTB 1 +#define SC520_PCI_INTC 2 +#define SC520_PCI_INTD 3 +#define SC520_PCI_GPIRQ0 4 +#define SC520_PCI_GPIRQ1 5 +#define SC520_PCI_GPIRQ2 6 +#define SC520_PCI_GPIRQ3 7 +#define SC520_PCI_GPIRQ4 8 +#define SC520_PCI_GPIRQ5 9 +#define SC520_PCI_GPIRQ6 10 +#define SC520_PCI_GPIRQ7 11 +#define SC520_PCI_GPIRQ8 12 +#define SC520_PCI_GPIRQ9 13 +#define SC520_PCI_GPIRQ10 14 + +/* utility functions */ +void write_mmcr_byte(u16 mmcr, u8 data); +void write_mmcr_word(u16 mmcr, u16 data); +void write_mmcr_long(u16 mmcr, u32 data); +u8 read_mmcr_byte(u16 mmcr); +u16 read_mmcr_word(u16 mmcr); +u32 read_mmcr_long(u16 mmcr); + +extern int sc520_pci_ints[]; + +void init_sc520(void); +unsigned long init_sc520_dram(void); +void pci_sc520_init(struct pci_controller *hose); +int pci_sc520_set_irq(int pci_pin, int irq); + +#endif diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h new file mode 100644 index 0000000..85d44aa --- /dev/null +++ b/include/asm-i386/io.h @@ -0,0 +1,204 @@ +#ifndef _ASM_IO_H +#define _ASM_IO_H + +/* + * This file contains the definitions for the x86 IO instructions + * inb/inw/inl/outb/outw/outl and the "string versions" of the same + * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" + * versions of the single-IO instructions (inb_p/inw_p/..). + * + * This file is not meant to be obfuscating: it's just complicated + * to (a) handle it all in a way that makes gcc able to optimize it + * as well as possible and (b) trying to avoid writing the same thing + * over and over again with slight variations and possibly making a + * mistake somewhere. + */ + +/* + * Thanks to James van Artsdalen for a better timing-fix than + * the two short jumps: using outb's to a nonexistent port seems + * to guarantee better timings even on fast machines. + * + * On the other hand, I'd like to be sure of a non-existent port: + * I feel a bit unsafe about using 0x80 (should be safe, though) + * + * Linus + */ + + /* + * Bit simplified and optimized by Jan Hubicka + * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. + * + * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, + * isa_read[wl] and isa_write[wl] fixed + * - Arnaldo Carvalho de Melo + */ + +#define IO_SPACE_LIMIT 0xffff + + +#ifdef __KERNEL__ + + +/* + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the x86 architecture, we just read/write the + * memory location directly. + */ + +#define readb(addr) (*(volatile unsigned char *) (addr)) +#define readw(addr) (*(volatile unsigned short *) (addr)) +#define readl(addr) (*(volatile unsigned int *) (addr)) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl + +#define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b)) +#define writew(b,addr) (*(volatile unsigned short *) (addr) = (b)) +#define writel(b,addr) (*(volatile unsigned int *) (addr) = (b)) +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +#define memset_io(a,b,c) memset((a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(b),(c)) +#define memcpy_toio(a,b,c) memcpy((a),(b),(c)) + +/* + * ISA space is 'always mapped' on a typical x86 system, no need to + * explicitly ioremap() it. The fact that the ISA IO space is mapped + * to PAGE_OFFSET is pure coincidence - it does not mean ISA values + * are physical addresses. The following constant pointer can be + * used as the IO-area pointer (it can be iounmapped as well, so the + * analogy with PCI is quite large): + */ +#define isa_readb(a) readb((a)) +#define isa_readw(a) readw((a)) +#define isa_readl(a) readl((a)) +#define isa_writeb(b,a) writeb(b,(a)) +#define isa_writew(w,a) writew(w,(a)) +#define isa_writel(l,a) writel(l,(a)) +#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) +#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) + + +static inline int check_signature(unsigned long io_addr, + const unsigned char *signature, int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +/** + * isa_check_signature - find BIOS signatures + * @io_addr: mmio address to check + * @signature: signature block + * @length: length of signature + * + * Perform a signature comparison with the ISA mmio address io_addr. + * Returns 1 on a match. + * + * This function is deprecated. New drivers should use ioremap and + * check_signature. + */ + + +static inline int isa_check_signature(unsigned long io_addr, + const unsigned char *signature, int length) +{ + int retval = 0; + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#endif /* __KERNEL__ */ + +#ifdef SLOW_IO_BY_JUMPING +#define __SLOW_DOWN_IO "\njmp 1f\n1:\tjmp 1f\n1:" +#else +#define __SLOW_DOWN_IO "\noutb %%al,$0x80" +#endif + +#ifdef REALLY_SLOW_IO +#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO +#else +#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO +#endif + + +/* + * Talk about misusing macros.. + */ +#define __OUT1(s,x) \ +static inline void out##s(unsigned x value, unsigned short port) { + +#define __OUT2(s,s1,s2) \ +__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1" + + +#define __OUT(s,s1,x) \ +__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \ +__OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));} + +#define __IN1(s) \ +static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v; + +#define __IN2(s,s1,s2) \ +__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0" + +#define __IN(s,s1,i...) \ +__IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \ +__IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; } + +#define __INS(s) \ +static inline void ins##s(unsigned short port, void * addr, unsigned long count) \ +{ __asm__ __volatile__ ("rep ; ins" #s \ +: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); } + +#define __OUTS(s) \ +static inline void outs##s(unsigned short port, const void * addr, unsigned long count) \ +{ __asm__ __volatile__ ("rep ; outs" #s \ +: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); } + +#define RETURN_TYPE unsigned char +__IN(b,"") +#undef RETURN_TYPE +#define RETURN_TYPE unsigned short +__IN(w,"") +#undef RETURN_TYPE +#define RETURN_TYPE unsigned int +__IN(l,"") +#undef RETURN_TYPE + +__OUT(b,"b",char) +__OUT(w,"w",short) +__OUT(l,,int) + +__INS(b) +__INS(w) +__INS(l) + +__OUTS(b) +__OUTS(w) +__OUTS(l) + +#endif diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h new file mode 100644 index 0000000..bde9550 --- /dev/null +++ b/include/asm-i386/pci.h @@ -0,0 +1,35 @@ + + +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PCI_I386_H_ +#define _PCI_I386_H_ 1 + +void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); +int pci_enable_legacy_video_ports(struct pci_controller* hose); +int pci_shadow_rom(pci_dev_t dev, unsigned char *dest); +void pci_remove_rom_window(struct pci_controller* hose, u32 addr); +u32 pci_get_rom_window(struct pci_controller* hose, int size); + +#endif diff --git a/include/asm-i386/posix_types.h b/include/asm-i386/posix_types.h new file mode 100644 index 0000000..5529f32 --- /dev/null +++ b/include/asm-i386/posix_types.h @@ -0,0 +1,80 @@ +#ifndef __ARCH_I386_POSIX_TYPES_H +#define __ARCH_I386_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd,fdsetp) \ + __asm__ __volatile__("btsl %1,%0": \ + "=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd))) + +#undef __FD_CLR +#define __FD_CLR(fd,fdsetp) \ + __asm__ __volatile__("btrl %1,%0": \ + "=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd))) + +#undef __FD_ISSET +#define __FD_ISSET(fd,fdsetp) (__extension__ ({ \ + unsigned char __result; \ + __asm__ __volatile__("btl %1,%2 ; setb %0" \ + :"=q" (__result) :"r" ((int) (fd)), \ + "m" (*(__kernel_fd_set *) (fdsetp))); \ + __result; })) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ +do { \ + int __d0, __d1; \ + __asm__ __volatile__("cld ; rep ; stosl" \ + :"=m" (*(__kernel_fd_set *) (fdsetp)), \ + "=&c" (__d0), "=&D" (__d1) \ + :"a" (0), "1" (__FDSET_LONGS), \ + "2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \ +} while (0) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h new file mode 100644 index 0000000..5dedba8 --- /dev/null +++ b/include/asm-i386/processor.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_PROCESSOR_H_ +#define __ASM_PROCESSOR_H_ 1 +/* Currently this header is unused in the i386 port + * but some generic files #include + * so this file is a placeholder. */ +#endif diff --git a/include/asm-i386/ptrace.h b/include/asm-i386/ptrace.h new file mode 100644 index 0000000..750e40d --- /dev/null +++ b/include/asm-i386/ptrace.h @@ -0,0 +1,66 @@ +#ifndef _I386_PTRACE_H +#define _I386_PTRACE_H + +#define EBX 0 +#define ECX 1 +#define EDX 2 +#define ESI 3 +#define EDI 4 +#define EBP 5 +#define EAX 6 +#define DS 7 +#define ES 8 +#define FS 9 +#define GS 10 +#define ORIG_EAX 11 +#define EIP 12 +#define CS 13 +#define EFL 14 +#define UESP 15 +#define SS 16 +#define FRAME_SIZE 17 + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +struct pt_regs { + long ebx; + long ecx; + long edx; + long esi; + long edi; + long ebp; + long eax; + int xds; + int xes; + int xfs; + int xgs; + long orig_eax; + long eip; + int xcs; + long eflags; + long esp; + int xss; +} __attribute__ ((packed)); + + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 +#define PTRACE_GETFPXREGS 18 +#define PTRACE_SETFPXREGS 19 + +#define PTRACE_SETOPTIONS 21 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +#ifdef __KERNEL__ +#define user_mode(regs) ((VM_MASK & (regs)->eflags) || (3 & (regs)->xcs)) +#define instruction_pointer(regs) ((regs)->eip) +extern void show_regs(struct pt_regs *); +#endif + +#endif diff --git a/include/asm-i386/realmode.h b/include/asm-i386/realmode.h new file mode 100644 index 0000000..9177e4e --- /dev/null +++ b/include/asm-i386/realmode.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_REALMODE_H_ +#define __ASM_REALMODE_H_ +#include + +int bios_setup(void); +int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out); +int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out); + +#endif diff --git a/include/asm-i386/string.h b/include/asm-i386/string.h new file mode 100644 index 0000000..91a23f9 --- /dev/null +++ b/include/asm-i386/string.h @@ -0,0 +1,30 @@ +#ifndef __ASM_I386_STRING_H +#define __ASM_I386_STRING_H + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMSET +extern void * memset(void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +extern void memzero(void *ptr, __kernel_size_t n); + +#endif diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h new file mode 100644 index 0000000..69f8a5a --- /dev/null +++ b/include/asm-i386/types.h @@ -0,0 +1,50 @@ +#ifndef __ASM_I386_TYPES_H +#define __ASM_I386_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#endif /* __KERNEL__ */ + +#endif diff --git a/include/asm-i386/u-boot-i386.h b/include/asm-i386/u-boot-i386.h new file mode 100644 index 0000000..12d10a7 --- /dev/null +++ b/include/asm-i386/u-boot-i386.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _U_BOOT_I386_H_ +#define _U_BOOT_I386_H_ 1 + +/* for the following variables, see start.S */ +extern ulong i386boot_start; /* code start (in flash) */ +extern ulong i386boot_end; /* code end (in flash) */ +extern ulong i386boot_romdata_start;/* datasegment in flash (also code+rodata end) */ +extern ulong i386boot_romdata_dest; /* data location segment in ram */ +extern ulong i386boot_romdata_size; /* size of data segment */ +extern ulong i386boot_bss_start; /* bss start */ +extern ulong i386boot_bss_size; /* bss size */ +extern ulong i386boot_stack_end; /* first usable RAM address after bss and stack */ +extern ulong i386boot_ram_end; /* end of ram */ + +extern ulong i386boot_realmode; /* start of realmode entry code */ +extern ulong i386boot_realmode_size;/* size of realmode entry code */ +extern ulong i386boot_bios; /* start of BIOS emulation code */ +extern ulong i386boot_bios_size; /* size of BIOS emulation code */ + + +/* cpu/.../cpu.c */ +int cpu_init(void); +int timer_init(void); + +/* board/.../... */ +int board_init(void); +int dram_init(void); + +void isa_unmap_rom(u32 addr); +u32 isa_map_rom(u32 bus_addr, int size); + +/* lib_i386/... */ +int video_bios_init(void); +int video_init(void); + + +#endif /* _U_BOOT_I386_H_ */ diff --git a/include/asm-i386/u-boot.h b/include/asm-i386/u-boot.h new file mode 100644 index 0000000..1e19f8f --- /dev/null +++ b/include/asm-i386/u-boot.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ + unsigned int bi_baudrate; /* Console Baudrate */ + unsigned long bi_boot_params; /* where this board expects params */ + struct environment_s *bi_env; + struct /* RAM configuration */ + { + ulong start; + ulong size; + }bi_dram[CONFIG_NR_DRAM_BANKS]; +} bd_t; + +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +#endif /* _U_BOOT_H_ */ diff --git a/include/asm-i386/zimage.h b/include/asm-i386/zimage.h new file mode 100644 index 0000000..c7103b1 --- /dev/null +++ b/include/asm-i386/zimage.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ZIMAGE_H_ +#define _ASM_ZIMAGE_H_ + +/* linux i386 zImage/bzImage header. Offsets relative to + * the start of the image */ + +#define CMD_LINE_MAGIC_OFF 0x020 /* Magic 0xa33f if the offset below is valid */ +#define CMD_LINE_OFFSET_OFF 0x022 /* Offset to comandline */ +#define SETUP_SECTS_OFF 0x1F1 /* The size of the setup in sectors */ +#define ROOT_FLAGS_OFF 0x1F2 /* If set, the root is mounted readonly */ +#define VID_MODE_OFF 0x1FA /* Video mode control */ +#define ROOT_DEV_OFF 0x1FC /* Default root device number */ +#define BOOT_FLAG_OFF 0x1FE /* 0xAA55 magic number */ +#define HEADER_OFF 0x202 /* Magic signature "HdrS" */ +#define VERSION_OFF 0x206 /* Boot protocol version supported */ +#define REALMODE_SWTCH_OFF 0x208 /* Boot loader hook (see below) */ +#define START_SYS_OFF 0x20C /* Points to kernel version string */ +#define TYPE_OF_LOADER_OFF 0x210 /* Boot loader identifier */ +#define LOADFLAGS_OFF 0x211 /* Boot protocol option flags */ +#define SETUP_MOVE_SIZE_OFF 0x212 /* Move to high memory size (used with hooks) */ +#define CODE32_START_OFF 0x214 /* Boot loader hook (see below) */ +#define RAMDISK_IMAGE_OFF 0x218 /* initrd load address (set by boot loader) */ +#define RAMDISK_SIZE_OFF 0x21C /* initrd size (set by boot loader) */ +#define HEAP_END_PTR_OFF 0x224 /* Free memory after setup end */ +#define CMD_LINE_PTR_OFF 0x228 /* 32-bit pointer to the kernel command line */ + + +#define HEAP_FLAG 0x80 +#define BIG_KERNEL_FLAG 0x01 + +/* magic numbers */ +#define KERNEL_MAGIC 0xaa55 +#define KERNEL_V2_MAGIC 0x53726448 +#define COMMAND_LINE_MAGIC 0xA33F + +/* limits */ +#define BZIMAGE_MAX_SIZE 15*1024*1024 /* 15MB */ +#define ZIMAGE_MAX_SIZE 512*1024 /* 512k */ +#define SETUP_MAX_SIZE 32768 + +#define SETUP_START_OFFSET 0x200 +#define BZIMAGE_LOAD_ADDR 0x100000 +#define ZIMAGE_LOAD_ADDR 0x10000 + +void *load_zimage(char *image, unsigned long kernel_size, + unsigned long initrd_addr, unsigned long initrd_size, + int auto_boot); + +void boot_zimage(void *setup_base); +image_header_t *fake_zimage_header(image_header_t *hdr, void *ptr, int size); + +#endif diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h new file mode 100644 index 0000000..3283714 --- /dev/null +++ b/include/asm-m68k/bitops.h @@ -0,0 +1,18 @@ +/* + * bitops.h: Bit string operations on the m68k + */ + +#ifndef _M68K_BITOPS_H +#define _M68K_BITOPS_H + +#include +#include + +extern void set_bit(int nr, volatile void *addr); +extern void clear_bit(int nr, volatile void *addr); +extern void change_bit(int nr, volatile void *addr); +extern int test_and_set_bit(int nr, volatile void *addr); +extern int test_and_clear_bit(int nr, volatile void *addr); +extern int test_and_change_bit(int nr, volatile void *addr); + +#endif /* _M68K_BITOPS_H */ diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h new file mode 100644 index 0000000..ce613ac --- /dev/null +++ b/include/asm-m68k/byteorder.h @@ -0,0 +1,7 @@ +#ifndef _M68K_BYTEORDER_H +#define _M68K_BYTEORDER_H + +#include +#include + +#endif /* _M68K_BYTEORDER_H */ diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h new file mode 100644 index 0000000..5bbbfb2 --- /dev/null +++ b/include/asm-m68k/fec.h @@ -0,0 +1,86 @@ +/* + * fec.h -- Fast Ethernet Controller definitions + * + * Some definitions copied from commproc.h for MPC8xx: + * MPC8xx Communication Processor Module. + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef fec_h +#define fec_h + +/* Buffer descriptors used FEC. +*/ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ + +/* Buffer descriptor control/status used by Ethernet receive. +*/ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. +*/ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +#endif /* fec_h */ diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h new file mode 100644 index 0000000..f68352f --- /dev/null +++ b/include/asm-m68k/global_data.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2002 - 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long bus_clk; + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long reset_status; /* reset status register at boot */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long have_console; /* serial_init() was called */ +#ifdef CONFIG_BOARD_TYPES + unsigned long board_type; +#endif + void **jt; /* Standalone app jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#if 0 +extern gd_t *global_data; +#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data +#else +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("d7") +#endif + +#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h new file mode 100644 index 0000000..a2c1271 --- /dev/null +++ b/include/asm-m68k/immap_5249.h @@ -0,0 +1,43 @@ +/* + * MCF5249 Internal Memory Map + * + * Copyright (c) 2003 Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5249__ +#define __IMMAP_5249__ + +/* Timer module registers + */ +typedef struct timer_ctrl { + ushort timer_tmr; + ushort res1; + ushort timer_trr; + ushort res2; + ushort timer_tcap; + ushort res3; + ushort timer_tcn; + ushort res4; + ushort timer_ter; + uchar res5[14]; +} timer_t; + +#endif /* __IMMAP_5249__ */ diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h new file mode 100644 index 0000000..ecb4906 --- /dev/null +++ b/include/asm-m68k/immap_5272.h @@ -0,0 +1,447 @@ +/* + * MCF5272 Internal Memory Map + * + * Copyright (c) 2003 Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5272__ +#define __IMMAP_5272__ + +/* System configuration registers +*/ +typedef struct sys_ctrl { + uint sc_mbar; + ushort sc_scr; + ushort sc_spr; + uint sc_pmr; + char res1[2]; + ushort sc_alpr; + uint sc_dir; + char res2[12]; +} sysctrl_t; + +/* Interrupt module registers +*/ +typedef struct int_ctrl { + uint int_icr1; + uint int_icr2; + uint int_icr3; + uint int_icr4; + uint int_isr; + uint int_pitr; + uint int_piwr; + uchar res1[3]; + uchar int_pivr; +} intctrl_t; + +/* Chip select module registers. +*/ +typedef struct cs_ctlr { + uint cs_br0; + uint cs_or0; + uint cs_br1; + uint cs_or1; + uint cs_br2; + uint cs_or2; + uint cs_br3; + uint cs_or3; + uint cs_br4; + uint cs_or4; + uint cs_br5; + uint cs_or5; + uint cs_br6; + uint cs_or6; + uint cs_br7; + uint cs_or7; +} csctrl_t; + +/* GPIO port registers +*/ +typedef struct gpio_ctrl { + uint gpio_pacnt; + ushort gpio_paddr; + ushort gpio_padat; + uint gpio_pbcnt; + ushort gpio_pbddr; + ushort gpio_pbdat; + uchar res1[4]; + ushort gpio_pcddr; + ushort gpio_pcdat; + uint gpio_pdcnt; + uchar res2[4]; +} gpio_t; + +/* QSPI module registers + */ +typedef struct qspi_ctrl { + ushort qspi_qmr; + uchar res1[2]; + ushort qspi_qdlyr; + uchar res2[2]; + ushort qspi_qwr; + uchar res3[2]; + ushort qspi_qir; + uchar res4[2]; + ushort qspi_qar; + uchar res5[2]; + ushort qspi_qdr; + uchar res6[10]; +} qspi_t; + +/* PWM module registers + */ +typedef struct pwm_ctrl { + uchar pwm_pwcr0; + uchar res1[3]; + uchar pwm_pwcr1; + uchar res2[3]; + uchar pwm_pwcr2; + uchar res3[7]; + uchar pwm_pwwd0; + uchar res4[3]; + uchar pwm_pwwd1; + uchar res5[3]; + uchar pwm_pwwd2; + uchar res6[7]; +} pwm_t; + +/* DMA module registers + */ +typedef struct dma_ctrl { + ulong dma_dmr; + uchar res1[2]; + ushort dma_dir; + ulong dma_dbcr; + ulong dma_dsar; + ulong dma_ddar; + uchar res2[12]; +} dma_t; + +/* UART module registers + */ +typedef struct uart_ctrl { + uchar uart_umr; + uchar res1[3]; + uchar uart_usr_ucsr; + uchar res2[3]; + uchar uart_ucr; + uchar res3[3]; + uchar uart_urb_utb; + uchar res4[3]; + uchar uart_uipcr_uacr; + uchar res5[3]; + uchar uart_uisr_uimr; + uchar res6[3]; + uchar uart_udu; + uchar res7[3]; + uchar uart_udl; + uchar res8[3]; + uchar uart_uabu; + uchar res9[3]; + uchar uart_uabl; + uchar res10[3]; + uchar uart_utf; + uchar res11[3]; + uchar uart_urf; + uchar res12[3]; + uchar uart_ufpd; + uchar res13[3]; + uchar uart_uip; + uchar res14[3]; + uchar uart_uop1; + uchar res15[3]; + uchar uart_uop0; + uchar res16[3]; +} uart_t; + +/* SDRAM controller registers, offset: 0x180 + */ +typedef struct sdram_ctrl { + uchar res1[2]; + ushort sdram_sdcr; + uchar res2[2]; + ushort sdram_sdtr; + uchar res3[120]; +} sdramctrl_t; + +/* Timer module registers + */ +typedef struct timer_ctrl { + ushort timer_tmr; + ushort res1; + ushort timer_trr; + ushort res2; + ushort timer_tcap; + ushort res3; + ushort timer_tcn; + ushort res4; + ushort timer_ter; + uchar res5[14]; +} timer_t; + +/* Watchdog registers + */ +typedef struct wdog_ctrl { + ushort wdog_wrrr; + ushort res1; + ushort wdog_wirr; + ushort res2; + ushort wdog_wcr; + ushort res3; + ushort wdog_wer; + uchar res4[114]; +} wdog_t; + +/* PLIC module registers + */ +typedef struct plic_ctrl { + ulong plic_p0b1rr; + ulong plic_p1b1rr; + ulong plic_p2b1rr; + ulong plic_p3b1rr; + ulong plic_p0b2rr; + ulong plic_p1b2rr; + ulong plic_p2b2rr; + ulong plic_p3b2rr; + uchar plic_p0drr; + uchar plic_p1drr; + uchar plic_p2drr; + uchar plic_p3drr; + uchar res1[4]; + ulong plic_p0b1tr; + ulong plic_p1b1tr; + ulong plic_p2b1tr; + ulong plic_p3b1tr; + ulong plic_p0b2tr; + ulong plic_p1b2tr; + ulong plic_p2b2tr; + ulong plic_p3b2tr; + uchar plic_p0dtr; + uchar plic_p1dtr; + uchar plic_p2dtr; + uchar plic_p3dtr; + uchar res2[4]; + ushort plic_p0cr; + ushort plic_p1cr; + ushort plic_p2cr; + ushort plic_p3cr; + ushort plic_p0icr; + ushort plic_p1icr; + ushort plic_p2icr; + ushort plic_p3icr; + ushort plic_p0gmr; + ushort plic_p1gmr; + ushort plic_p2gmr; + ushort plic_p3gmr; + ushort plic_p0gmt; + ushort plic_p1gmt; + ushort plic_p2gmt; + ushort plic_p3gmt; + uchar res3; + uchar plic_pgmts; + uchar plic_pgmta; + uchar res4; + uchar plic_p0gcir; + uchar plic_p1gcir; + uchar plic_p2gcir; + uchar plic_p3gcir; + uchar plic_p0gcit; + uchar plic_p1gcit; + uchar plic_p2gcit; + uchar plic_p3gcit; + uchar res5[3]; + uchar plic_pgcitsr; + uchar res6[3]; + uchar plic_pdcsr; + ushort plic_p0psr; + ushort plic_p1psr; + ushort plic_p2psr; + ushort plic_p3psr; + ushort plic_pasr; + uchar res7; + uchar plic_plcr; + ushort res8; + ushort plic_pdrqr; + ushort plic_p0sdr; + ushort plic_p1sdr; + ushort plic_p2sdr; + ushort plic_p3sdr; + ushort res9; + ushort plic_pcsr; + uchar res10[1184]; +} plic_t; + +/* Fast ethernet controller registers + */ +typedef struct fec { + uint fec_ecntrl; /* ethernet control register */ + uint fec_ievent; /* interrupt event register */ + uint fec_imask; /* interrupt mask register */ + uint fec_ivec; /* interrupt level and vector status */ + uint fec_r_des_active; /* Rx ring updated flag */ + uint fec_x_des_active; /* Tx ring updated flag */ + uint res3[10]; /* reserved */ + uint fec_mii_data; /* MII data register */ + uint fec_mii_speed; /* MII speed control register */ + uint res4[17]; /* reserved */ + uint fec_r_bound; /* end of RAM (read-only) */ + uint fec_r_fstart; /* Rx FIFO start address */ + uint res5[6]; /* reserved */ + uint fec_x_fstart; /* Tx FIFO start address */ + uint res7[21]; /* reserved */ + uint fec_r_cntrl; /* Rx control register */ + uint fec_r_hash; /* Rx hash register */ + uint res8[14]; /* reserved */ + uint fec_x_cntrl; /* Tx control register */ + uint res9[0x9e]; /* reserved */ + uint fec_addr_low; /* lower 32 bits of station address */ + uint fec_addr_high; /* upper 16 bits of station address */ + uint fec_hash_table_high; /* upper 32-bits of hash table */ + uint fec_hash_table_low; /* lower 32-bits of hash table */ + uint fec_r_des_start; /* beginning of Rx descriptor ring */ + uint fec_x_des_start; /* beginning of Tx descriptor ring */ + uint fec_r_buff_size; /* Rx buffer size */ + uint res2[9]; /* reserved */ + uchar fec_fifo[960]; /* fifo RAM */ +} fec_t; + +/* USB module registers +*/ +typedef struct usb { + ushort res1; + ushort usb_fnr; + ushort res2; + ushort usb_fnmr; + ushort res3; + ushort usb_rfmr; + ushort res4; + ushort usb_rfmmr; + uchar res5[3]; + uchar usb_far; + ulong usb_asr; + ulong usb_drr1; + ulong usb_drr2; + ushort res6; + ushort usb_specr; + ushort res7; + ushort usb_ep0sr; + ulong usb_iep0cfg; + ulong usb_oep0cfg; + ulong usb_ep1cfg; + ulong usb_ep2cfg; + ulong usb_ep3cfg; + ulong usb_ep4cfg; + ulong usb_ep5cfg; + ulong usb_ep6cfg; + ulong usb_ep7cfg; + ulong usb_ep0ctl; + ushort res8; + ushort usb_ep1ctl; + ushort res9; + ushort usb_ep2ctl; + ushort res10; + ushort usb_ep3ctl; + ushort res11; + ushort usb_ep4ctl; + ushort res12; + ushort usb_ep5ctl; + ushort res13; + ushort usb_ep6ctl; + ushort res14; + ushort usb_ep7ctl; + ulong usb_ep0isr; + ushort res15; + ushort usb_ep1isr; + ushort res16; + ushort usb_ep2isr; + ushort res17; + ushort usb_ep3isr; + ushort res18; + ushort usb_ep4isr; + ushort res19; + ushort usb_ep5isr; + ushort res20; + ushort usb_ep6isr; + ushort res21; + ushort usb_ep7isr; + ulong usb_ep0imr; + ushort res22; + ushort usb_ep1imr; + ushort res23; + ushort usb_ep2imr; + ushort res24; + ushort usb_ep3imr; + ushort res25; + ushort usb_ep4imr; + ushort res26; + ushort usb_ep5imr; + ushort res27; + ushort usb_ep6imr; + ushort res28; + ushort usb_ep7imr; + ulong usb_ep0dr; + ulong usb_ep1dr; + ulong usb_ep2dr; + ulong usb_ep3dr; + ulong usb_ep4dr; + ulong usb_ep5dr; + ulong usb_ep6dr; + ulong usb_ep7dr; + ushort res29; + ushort usb_ep0dpr; + ushort res30; + ushort usb_ep1dpr; + ushort res31; + ushort usb_ep2dpr; + ushort res32; + ushort usb_ep3dpr; + ushort res33; + ushort usb_ep4dpr; + ushort res34; + ushort usb_ep5dpr; + ushort res35; + ushort usb_ep6dpr; + ushort res36; + ushort usb_ep7dpr; + uchar res37[788]; + uchar usb_cfgram[1024]; +} usb_t; + +/* Internal memory map. +*/ +typedef struct immap { + sysctrl_t sysctrl_reg; /* System configuration registers */ + intctrl_t intctrl_reg; /* Interrupt controller registers */ + csctrl_t csctrl_reg; /* Chip select controller registers */ + gpio_t gpio_reg; /* GPIO controller registers */ + qspi_t qspi_reg; /* QSPI controller registers */ + pwm_t pwm_reg; /* Pulse width modulation registers */ + dma_t dma_reg; /* DMA registers */ + uart_t uart_reg[2]; /* UART registers */ + sdramctrl_t sdram_reg; /* SDRAM controller registers */ + timer_t timer_reg[4]; /* Timer registers */ + wdog_t wdog_reg; /* Watchdog registers */ + plic_t plic_reg; /* Physical layer interface registers */ + fec_t fec_reg; /* Fast ethernet controller registers */ + usb_t usb_reg; /* USB controller registers */ +} immap_t; + +#endif /* __IMMAP_5272__ */ diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h new file mode 100644 index 0000000..f2b77db --- /dev/null +++ b/include/asm-m68k/immap_5282.h @@ -0,0 +1,63 @@ +/* + * MCF5282 Internal Memory Map + * + * Copyright (c) 2003 Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5282__ +#define __IMMAP_5282__ + + +/* Fast ethernet controller registers + */ +typedef struct fec { + uint fec_ecntrl; /* ethernet control register */ + uint fec_ievent; /* interrupt event register */ + uint fec_imask; /* interrupt mask register */ + uint fec_ivec; /* interrupt level and vector status */ + uint fec_r_des_active; /* Rx ring updated flag */ + uint fec_x_des_active; /* Tx ring updated flag */ + uint res3[10]; /* reserved */ + uint fec_mii_data; /* MII data register */ + uint fec_mii_speed; /* MII speed control register */ + uint res4[17]; /* reserved */ + uint fec_r_bound; /* end of RAM (read-only) */ + uint fec_r_fstart; /* Rx FIFO start address */ + uint res5[6]; /* reserved */ + uint fec_x_fstart; /* Tx FIFO start address */ + uint res7[21]; /* reserved */ + uint fec_r_cntrl; /* Rx control register */ + uint fec_r_hash; /* Rx hash register */ + uint res8[14]; /* reserved */ + uint fec_x_cntrl; /* Tx control register */ + uint res9[0x9e]; /* reserved */ + uint fec_addr_low; /* lower 32 bits of station address */ + uint fec_addr_high; /* upper 16 bits of station address */ + uint fec_hash_table_high; /* upper 32-bits of hash table */ + uint fec_hash_table_low; /* lower 32-bits of hash table */ + uint fec_r_des_start; /* beginning of Rx descriptor ring */ + uint fec_x_des_start; /* beginning of Tx descriptor ring */ + uint fec_r_buff_size; /* Rx buffer size */ + uint res2[9]; /* reserved */ + uchar fec_fifo[960]; /* fifo RAM */ +} fec_t; + +#endif /* __IMMAP_5282__ */ diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h new file mode 100644 index 0000000..79a9626 --- /dev/null +++ b/include/asm-m68k/io.h @@ -0,0 +1 @@ +/* */ diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h new file mode 100644 index 0000000..8c1b077 --- /dev/null +++ b/include/asm-m68k/m5249.h @@ -0,0 +1,187 @@ +/* + * mcf5249.h -- Definitions for Motorola Coldfire 5249 + * + * Based on mcf5272sim.h of uCLinux distribution: + * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef mcf5249_h +#define mcf5249_h +/****************************************************************************/ + +/* + * useful definitions for reading/writing MBAR offset memory + */ +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y +#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x)) +#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y +#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y +#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y + + +/* + * Size of internal RAM + */ + +#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */ +#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */ + +/* + * Define the 5249 SIM register set addresses. + */ + +/***************** + ***** MBAR1 ***** + *****************/ +#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ +#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ + +#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ +#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ + +#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ + +#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ +#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ +#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ +#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ +#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ +#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ +#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ +#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ + +#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ +#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ + +/** UART Bases **/ +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ + +/***************** + ***** MBAR2 ***** + *****************/ + +/* GPIO Addresses + * Note: These are offset from MBAR2! + */ +#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */ +#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w)*/ +#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w)*/ +#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */ +#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */ +#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */ +#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */ +#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */ + +#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */ +#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */ +#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */ + +#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */ +#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */ +#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */ + +#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */ +#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */ +#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */ +#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */ +#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */ +#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */ +#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */ +#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */ + +#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */ +#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */ + +#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */ +#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */ + +#define MCFSIM_PLLCR 0x180 /* PLL Control register */ + +/* + * Some symbol defines for the above... + */ +#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ +#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ +#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ +#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ +#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ +#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ +/* XXX - If needed, DMA ICRs go here */ +#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ + +/* + * Bit definitions for the ICR family of registers. + */ +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ + +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ + + +/* + * Macros to read/set IMR register. It is 32 bits on the 5249. + */ + +#define mcf_getimr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) + +#define mcf_setimr(imr) \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); + +#endif /* mcf5249_h */ diff --git a/include/asm-m68k/m5272.h b/include/asm-m68k/m5272.h new file mode 100644 index 0000000..54d4a32 --- /dev/null +++ b/include/asm-m68k/m5272.h @@ -0,0 +1,99 @@ +/* + * mcf5272.h -- Definitions for Motorola Coldfire 5272 + * + * Based on mcf5272sim.h of uCLinux distribution: + * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef mcf5272_h +#define mcf5272_h +/****************************************************************************/ + +/* + * Size of internal RAM + */ + +#define INT_RAM_SIZE 4096 + + +/* + * Define the 5272 SIM register set addresses. + */ +#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ +#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ +#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ +#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ +#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ + +#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ + +#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ +#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ +#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ +#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ + +#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ +#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ +#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ +#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ + +#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ +#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ +#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ +#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ +#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ +#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ +#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ +#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ +#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ +#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ +#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ +#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ +#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ +#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ +#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ +#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ + +#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ +#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ +#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ +#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ +#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ +#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ + +#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ +#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ +#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ +#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ +#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ +#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ +#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ +#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ +#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ + +#endif /* mcf5272_h */ diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h new file mode 100644 index 0000000..073b0bc --- /dev/null +++ b/include/asm-m68k/m5282.h @@ -0,0 +1,60 @@ +/* + * mcf5282.h -- Definitions for Motorola Coldfire 5282 + * + * Based on mcf5282sim.h of uCLinux distribution: + * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/****************************************************************************/ +#ifndef m5282_h +#define m5282_h +/****************************************************************************/ + +/* + * Size of internal RAM + */ + +#define INT_RAM_SIZE 65536 + + +/* + * Define the 5282 SIM register set addresses. + */ +#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ +#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ +#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ +#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ +#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ +#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ +#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_IRLR 0x18 /* */ +#define MCFINTC_IACKL 0x19 /* */ +#define MCFINTC_ICR0 0x40 /* Base ICR register */ + +#define MCFINT_UART0 13 /* Interrupt number for UART0 */ +#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ + +#define MCF5282_GPIO_PUAPAR 0x10005C + + +/****************************************************************************/ +#endif /* m5282_h */ diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h new file mode 100644 index 0000000..047950b --- /dev/null +++ b/include/asm-m68k/mcftimer.h @@ -0,0 +1,113 @@ +/* + * mcftimer.h -- ColdFire internal TIMER support defines. + * + * Based on mcftimer.h of uCLinux distribution: + * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/****************************************************************************/ +#ifndef mcftimer_h +#define mcftimer_h +/****************************************************************************/ + +#include + +/* + * Get address specific defines for this ColdFire member. + */ +#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) +#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ +#elif defined(CONFIG_M5272) +#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ +#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ +#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) +#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ +#elif defined(CONFIG_M5282) +#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */ +#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */ +#endif + +/* + * Define the TIMER register set addresses. + */ +#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ +#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */ +#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */ +#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */ +#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ + + +/* + * Define the TIMER register set addresses for 5282. + */ +#define MCFTIMER_PCSR 0 +#define MCFTIMER_PMR 1 +#define MCFTIMER_PCNTR 2 + +/* + * Bit definitions for the Timer Mode Register (TMR). + * Register bit flags are common accross ColdFires. + */ +#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ +#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ +#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ +#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ +#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ +#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ +#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ +#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ +#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ +#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ +#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ +#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ +#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ +#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ +#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ +#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ +#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ + +/* + * Bit definitions for the Timer Event Registers (TER). + */ +#define MCFTIMER_TER_CAP 0x01 /* Capture event */ +#define MCFTIMER_TER_REF 0x02 /* Refernece event */ + +/* + * Bit definitions for the 5282 PIT Control and Status Register (PCSR). + */ +#define MCFTIMER_PCSR_EN 0x0001 +#define MCFTIMER_PCSR_RLD 0x0002 +#define MCFTIMER_PCSR_PIF 0x0004 +#define MCFTIMER_PCSR_PIE 0x0008 +#define MCFTIMER_PCSR_OVW 0x0010 +#define MCFTIMER_PCSR_HALTED 0x0020 +#define MCFTIMER_PCSR_DOZE 0x0040 + + +/****************************************************************************/ +#endif /* mcftimer_h */ diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h new file mode 100644 index 0000000..e5082a9 --- /dev/null +++ b/include/asm-m68k/mcfuart.h @@ -0,0 +1,221 @@ +/* + * mcfuart.h -- ColdFire internal UART support defines. + * + * File copied from mcfuart.h of uCLinux distribution: + * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/****************************************************************************/ +#ifndef mcfuart_h +#define mcfuart_h +/****************************************************************************/ + +#include + +/* + * Define the base address of the UARTS within the MBAR address + * space. + */ +#if defined(CONFIG_M5272) +#define MCFUART_BASE1 0x100 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) +#if defined(CONFIG_NETtel) +#define MCFUART_BASE1 0x180 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x140 /* Base address of UART1 */ +#define MCFUART_BASE2 0x180 /* Base address of UART2 */ +#endif +#elif defined(CONFIG_M5282) +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) +#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#endif +#endif + + +/* + * Define the ColdFire UART register set addresses. + */ +#define MCFUART_UMR 0x00 /* Mode register (r/w) */ +#define MCFUART_USR 0x04 /* Status register (r) */ +#define MCFUART_UCSR 0x04 /* Clock Select (w) */ +#define MCFUART_UCR 0x08 /* Command register (w) */ +#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ +#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ +#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ +#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ +#define MCFUART_UISR 0x14 /* Interrup Status (r) */ +#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ +#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ +#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ +#ifdef CONFIG_M5272 +#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ +#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ +#else +#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ +#endif +#define MCFUART_UIPR 0x34 /* Input Port (r) */ +#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ +#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ + +#ifdef CONFIG_M5249 +/* Note: This isn't in the 5249 docs */ +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ +#endif + +/* + * Define bit flags in Mode Register 1 (MR1). + */ +#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ +#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ +#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ +#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ +#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ + +#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ +#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ +#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ +#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ +#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ + +#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ +#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ +#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ +#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ + +/* + * Define bit flags in Mode Register 2 (MR2). + */ +#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ +#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ +#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ +#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ +#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ + +#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ +#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ +#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ + +/* + * Define bit flags in Status Register (USR). + */ +#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ +#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ +#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ +#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ +#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ +#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ +#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ +#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ + +#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ + MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) + +/* + * Define bit flags in Clock Select Register (UCSR). + */ +#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ +#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ +#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ + +#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ +#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ +#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ + +/* + * Define bit flags in Command Register (UCR). + */ +#define MCFUART_UCR_CMDNULL 0x00 /* No command */ +#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ +#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ +#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ +#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ +#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ +#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ +#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ + +#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ +#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ +#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ +#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ +#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ +#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ + +/* + * Define bit flags in Input Port Change Register (UIPCR). + */ +#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ +#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ + +/* + * Define bit flags in Input Port Register (UIP). + */ +#define MCFUART_UIPR_CTS 0x01 /* CTS value */ + +/* + * Define bit flags in Output Port Registers (UOP). + * Clear bit by writing to UOP0, set by writing to UOP1. + */ +#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ + +/* + * Define bit flags in the Auxiliary Control Register (UACR). + */ +#define MCFUART_UACR_IEC 0x01 /* Input enable control */ + +/* + * Define bit flags in Interrupt Status Register (UISR). + * These same bits are used for the Interrupt Mask Register (UIMR). + */ +#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ +#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ +#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ +#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ + +#ifdef CONFIG_M5272 +/* + * Define bit flags in the Transmitter FIFO Register (UTF). + */ +#define MCFUART_UTF_TXB 0x1f /* transmitter data level */ +#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */ +#define MCFUART_UTF_TXS 0xc0 /* transmitter status */ + +/* + * Define bit flags in the Receiver FIFO Register (URF). + */ +#define MCFUART_URF_RXB 0x1f /* receiver data level */ +#define MCFUART_URF_FULL 0x20 /* receiver fifo full */ +#define MCFUART_URF_RXS 0xc0 /* receiver status */ +#endif + +/****************************************************************************/ +#endif /* mcfuart_h */ diff --git a/include/asm-m68k/posix_types.h b/include/asm-m68k/posix_types.h new file mode 100644 index 0000000..4fbc040 --- /dev/null +++ b/include/asm-m68k/posix_types.h @@ -0,0 +1,109 @@ +#ifndef _M68K_POSIX_TYPES_H +#define _M68K_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned int __kernel_dev_t; +typedef unsigned int __kernel_ino_t; +typedef unsigned int __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned int __kernel_old_uid_t; +typedef unsigned int __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { + int val[2]; +} __kernel_fsid_t; + +#ifndef __GNUC__ + +#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) +#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) +#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) +#define __FD_ZERO(set) \ + ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set))) + +#else /* __GNUC__ */ + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ + || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) +/* With GNU C, use inline functions instead so args are evaluated only once: */ + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) +{ + unsigned long _tmp = fd / __NFDBITS; + unsigned long _rem = fd % __NFDBITS; + fdsetp->fds_bits[_tmp] |= (1UL<<_rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp) +{ + unsigned long _tmp = fd / __NFDBITS; + unsigned long _rem = fd % __NFDBITS; + fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem); +} + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p) +{ + unsigned long _tmp = fd / __NFDBITS; + unsigned long _rem = fd % __NFDBITS; + return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *p) +{ + unsigned int *tmp = (unsigned int *)p->fds_bits; + int i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 8: + tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0; + tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0; + return; + } + } + i = __FDSET_LONGS; + while (i) { + i--; + *tmp = 0; + tmp++; + } +} + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* __GNUC__ */ +#endif /* _M68K_POSIX_TYPES_H */ diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h new file mode 100644 index 0000000..3fafa6f --- /dev/null +++ b/include/asm-m68k/processor.h @@ -0,0 +1,18 @@ +#ifndef __ASM_M68K_PROCESSOR_H +#define __ASM_M68K_PROCESSOR_H + +#include +#include + +#define _GLOBAL(n)\ + .globl n;\ +n: + +/* Macros for setting and retrieving special purpose registers */ +#define setvbr(v) asm volatile("movec %0,%%VBR" : : "r" (v)) + +#ifndef __ASSEMBLY__ + +#endif /* ifndef ASSEMBLY*/ + +#endif /* __ASM_M68K_PROCESSOR_H */ diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h new file mode 100644 index 0000000..a6d3d74 --- /dev/null +++ b/include/asm-m68k/ptrace.h @@ -0,0 +1,59 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _M68K_PTRACE_H +#define _M68K_PTRACE_H + +/* + * This struct defines the way the registers are stored on the + * kernel stack during an exception. + */ +#ifndef __ASSEMBLY__ + +struct pt_regs { + ulong d0; + ulong d1; + ulong d2; + ulong d3; + ulong d4; + ulong d5; + ulong d6; + ulong d7; + ulong a0; + ulong a1; + ulong a2; + ulong a3; + ulong a4; + ulong a5; + ulong a6; +#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) + unsigned format : 4; /* frame format specifier */ + unsigned vector : 12; /* vector offset */ + unsigned short sr; + unsigned long pc; +#else + unsigned short sr; + unsigned long pc; +#endif +}; + +#endif /* #ifndef __ASSEMBLY__ */ + +#endif /* #ifndef _M68K_PTRACE_H */ diff --git a/include/asm-m68k/string.h b/include/asm-m68k/string.h new file mode 100644 index 0000000..e0773a8 --- /dev/null +++ b/include/asm-m68k/string.h @@ -0,0 +1,31 @@ +#ifndef _M68K_STRING_H_ +#define _M68K_STRING_H_ + +#if 0 +#define __HAVE_ARCH_STRCPY +#define __HAVE_ARCH_STRNCPY +#define __HAVE_ARCH_STRLEN +#define __HAVE_ARCH_STRCMP +#define __HAVE_ARCH_STRCAT +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_BCOPY +#define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMMOVE +#define __HAVE_ARCH_MEMCMP +#define __HAVE_ARCH_MEMCHR +#endif + +extern int strcasecmp(const char *, const char *); +extern int strncasecmp(const char *, const char *, int); +extern char * strcpy(char *,const char *); +extern char * strncpy(char *,const char *, __kernel_size_t); +extern __kernel_size_t strlen(const char *); +extern int strcmp(const char *,const char *); +extern char * strcat(char *, const char *); +extern void * memset(void *,int,__kernel_size_t); +extern void * memcpy(void *,const void *,__kernel_size_t); +extern void * memmove(void *,const void *,__kernel_size_t); +extern int memcmp(const void *,const void *,__kernel_size_t); +extern void * memchr(const void *,int,__kernel_size_t); + +#endif diff --git a/include/asm-m68k/types.h b/include/asm-m68k/types.h new file mode 100644 index 0000000..e673cb0 --- /dev/null +++ b/include/asm-m68k/types.h @@ -0,0 +1,50 @@ +#ifndef _M68K_TYPES_H +#define _M68K_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +typedef struct { + __u32 u[4]; +} __attribute((aligned(16))) vector128; + +#ifdef __KERNEL__ +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* DMA addresses are 32-bits wide */ +typedef u32 dma_addr_t; + +#endif /* __KERNEL__ */ +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h new file mode 100644 index 0000000..7a6a8c1 --- /dev/null +++ b/include/asm-m68k/u-boot.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2000 - 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __U_BOOT_H__ +#define __U_BOOT_H__ + +/* + * Board information passed to Linux kernel from U-Boot + * + * include/asm-ppc/u-boot.h + */ + +#ifndef __ASSEMBLY__ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ + unsigned long bi_baudrate; /* Console Baudrate */ +} bd_t; + +#endif /* __ASSEMBLY__ */ + +#endif /* __U_BOOT_H__ */ diff --git a/include/asm-microblaze/arch-microblaze/xbasic_types.h b/include/asm-microblaze/arch-microblaze/xbasic_types.h new file mode 100644 index 0000000..25012e6 --- /dev/null +++ b/include/asm-microblaze/arch-microblaze/xbasic_types.h @@ -0,0 +1,301 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2003 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xbasic_types.h +* +* This file contains basic types for Xilinx software IP. These types do not +* follow the standard naming convention with respect to using the component +* name in front of each name because they are considered to be primitives. +* +* @note +* +* This file contains items which are architecture dependent. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	 Who	Date	Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  12/14/01 First release
+*	rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
+*		      compiler warnings
+*
+* +******************************************************************************/ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef NULL +#define NULL 0 +#endif +/** Null */ + +#define XCOMPONENT_IS_READY 0x11111111 /* component has been initialized */ +#define XCOMPONENT_IS_STARTED 0x22222222 /* component has been started */ + +/* the following constants and declarations are for unit test purposes and are + * designed to be used in test applications. + */ +#define XTEST_PASSED 0 +#define XTEST_FAILED 1 + +#define XASSERT_NONE 0 +#define XASSERT_OCCURRED 1 + +extern unsigned int XAssertStatus; +extern void XAssert(char *, int); + +/**************************** Type Definitions *******************************/ + +/** @name Primitive types + * These primitive types are created for transportability. + * They are dependent upon the target architecture. + * @{ + */ +#include + +typedef struct { + u32 Upper; + u32 Lower; +} Xuint64; + +/* Xilinx's unsigned integer types */ +typedef u32 Xuint32; +typedef u16 Xuint16; +typedef u8 Xuint8; + +/* and signed integer types */ +typedef s32 Xint32; +typedef s16 Xint16; +typedef s8 Xint8; + +#ifndef NULL +#define NULL 0 +#endif + +typedef unsigned long Xboolean; +#define XNULL NULL + +#define XTRUE 1 +#define XFALSE 0 + +/*@}*/ + +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber); + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return +* +* The upper 32 bits of the 64 bit word. +* +* @note +* +* None. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return +* +* The lower 32 bits of the 64 bit word. +* +* @note +* +* None. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do not return anything +* (void). This in conjunction with the XWaitInAssert boolean can be used to +* accomodate tests so that asserts which fail allow execution to continue. +* +* @param expression is the expression to evaluate. If it evaluates to false, +* the assert occurs. +* +* @return +* +* Returns void unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_VOID(expression) \ +{ \ + if (expression) { \ + XAssertStatus = XASSERT_NONE; \ + } else { \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do return a value. This in +* conjunction with the XWaitInAssert boolean can be used to accomodate tests so +* that asserts which fail allow execution to continue. +* +* @param expression is the expression to evaluate. If it evaluates to false, +* the assert occurs. +* +* @return +* +* Returns 0 unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_NONVOID(expression) \ +{ \ + if (expression) { \ + XAssertStatus = XASSERT_NONE; \ + } else { \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do not +* return anything (void). Use for instances where an assert should always +* occur. +* +* @return +* +* Returns void unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_VOID_ALWAYS() \ +{ \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do return +* a value. Use for instances where an assert should always occur. +* +* @return +* +* Returns void unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_NONVOID_ALWAYS() \ +{ \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return 0; \ +} + +#else + +#define XASSERT_VOID(expression) +#define XASSERT_VOID_ALWAYS() +#define XASSERT_NONVOID(expression) +#define XASSERT_NONVOID_ALWAYS() +#endif + +/************************** Function Prototypes ******************************/ + +void XAssertSetCallback(XAssertCallback Routine); + +#endif /* end of protection macro */ diff --git a/include/asm-microblaze/arch-microblaze/xio.h b/include/asm-microblaze/arch-microblaze/xio.h new file mode 100644 index 0000000..7eed327 --- /dev/null +++ b/include/asm-microblaze/arch-microblaze/xio.h @@ -0,0 +1,63 @@ +/* + * xio.h + * + * Defines XIo functions for Xilinx OCP in terms of Linux primitives + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2002 (c) MontaVista, Software, Inc. This file is licensed under the terms + * of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#ifndef XIO_H +#define XIO_H + +#include "xbasic_types.h" +#include + +typedef u32 XIo_Address; + +extern inline u8 +XIo_In8(XIo_Address InAddress) +{ + return (u8) in_8((volatile unsigned char *) InAddress); +} +extern inline u16 +XIo_In16(XIo_Address InAddress) +{ + return (u16) in_be16((volatile unsigned short *) InAddress); +} +extern inline u32 +XIo_In32(XIo_Address InAddress) +{ + return (u32) in_be32((volatile unsigned *) InAddress); +} +extern inline void +XIo_Out8(XIo_Address OutAddress, u8 Value) +{ + out_8((volatile unsigned char *) OutAddress, Value); +} +extern inline void +XIo_Out16(XIo_Address OutAddress, u16 Value) +{ + out_be16((volatile unsigned short *) OutAddress, Value); +} +extern inline void +XIo_Out32(XIo_Address OutAddress, u32 Value) +{ + out_be32((volatile unsigned *) OutAddress, Value); +} + +#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s))) +#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s))) +#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s))) +#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s))) + +#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s))) +#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s))) +#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s))) +#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s))) + +#endif /* XIO_H */ diff --git a/include/asm-microblaze/arch-microblaze/xuartlite_l.h b/include/asm-microblaze/arch-microblaze/xuartlite_l.h new file mode 100644 index 0000000..b381a0d --- /dev/null +++ b/include/asm-microblaze/arch-microblaze/xuartlite_l.h @@ -0,0 +1,256 @@ +/***************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002 Xilinx Inc. +* All rights reserved. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xuartlite_l.h +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the device. High-level driver functions +* are defined in xuartlite.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm  04/25/02 First release
+*
+* +*****************************************************************************/ + +#ifndef XUARTLITE_L_H /* prevent circular inclusions */ +#define XUARTLITE_L_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xbasic_types.h" +#include "xio.h" + +/************************** Constant Definitions ****************************/ + +/* UART Lite register offsets */ + +#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ +#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */ +#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */ +#define XUL_CONTROL_REG_OFFSET 12 /* control register, write only */ + +/* control register bit positions */ + +#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */ +#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */ +#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */ + +/* status register bit positions */ + +#define XUL_SR_PARITY_ERROR 0x80 +#define XUL_SR_FRAMING_ERROR 0x40 +#define XUL_SR_OVERRUN_ERROR 0x20 +#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */ +#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ +#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */ +#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ + +/* the following constant specifies the size of the FIFOs, the size of the + * FIFOs includes the transmitter and receiver such that it is the total number + * of bytes that the UART can buffer + */ +#define XUL_FIFO_SIZE 16 + +/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a + * per instance basis + */ +#define XUL_STOP_BITS 1 + +/* Parity definitions + */ +#define XUL_PARITY_NONE 0 +#define XUL_PARITY_ODD 1 +#define XUL_PARITY_EVEN 2 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/***************************************************************************** +* +* Low-level driver macros and functions. The list below provides signatures +* to help the user use the macros. +* +* void XUartLite_mSetControlReg(u32 BaseAddress, u32 Mask) +* u32 XUartLite_mGetControlReg(u32 BaseAddress) +* u32 XUartLite_mGetStatusReg(u32 BaseAddress) +* +* Xboolean XUartLite_mIsReceiveEmpty(u32 BaseAddress) +* Xboolean XUartLite_mIsTransmitFull(u32 BaseAddress) +* Xboolean XUartLite_mIsIntrEnabled(u32 BaseAddress) +* +* void XUartLite_mEnableIntr(u32 BaseAddress) +* void XUartLite_mDisableIntr(u32 BaseAddress) +* +* void XUartLite_SendByte(u32 BaseAddress, u8 Data); +* u8 XUartLite_RecvByte(u32 BaseAddress); +* +*****************************************************************************/ + +/****************************************************************************/ +/** +* +* Set the contents of the control register. Use the XUL_CR_* constants defined +* above to create the bit-mask to be written to the register. +* +* @param BaseAddress is the base address of the device +* @param Mask is the 32-bit value to write to the control register +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mSetControlReg(BaseAddress, Mask) \ + XIo_Out32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask)) + + +/****************************************************************************/ +/** +* +* Get the contents of the control register. Use the XUL_CR_* constants defined +* above to interpret the bit-mask returned. +* +* @param BaseAddress is the base address of the device +* +* @return A 32-bit value representing the contents of the control register. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mGetControlReg(BaseAddress) \ + XIo_In32((BaseAddress) + XUL_CONTROL_REG_OFFSET) + + +/****************************************************************************/ +/** +* +* Get the contents of the status register. Use the XUL_SR_* constants defined +* above to interpret the bit-mask returned. +* +* @param BaseAddress is the base address of the device +* +* @return A 32-bit value representing the contents of the status register. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mGetStatusReg(BaseAddress) \ + XIo_In32((BaseAddress) + XUL_STATUS_REG_OFFSET) + + +/****************************************************************************/ +/** +* +* Check to see if the receiver has data. +* +* @param BaseAddress is the base address of the device +* +* @return XTRUE if the receiver is empty, XFALSE if there is data present. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mIsReceiveEmpty(BaseAddress) \ + (!(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA)) + + +/****************************************************************************/ +/** +* +* Check to see if the transmitter is full. +* +* @param BaseAddress is the base address of the device +* +* @return XTRUE if the transmitter is full, XFALSE otherwise. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mIsTransmitFull(BaseAddress) \ + (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) + + +/****************************************************************************/ +/** +* +* Check to see if the interrupt is enabled. +* +* @param BaseAddress is the base address of the device +* +* @return XTRUE if the interrupt is enabled, XFALSE otherwise. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mIsIntrEnabled(BaseAddress) \ + (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) + + +/****************************************************************************/ +/** +* +* Enable the device interrupt. Preserve the contents of the control register. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mEnableIntr(BaseAddress) \ + XUartLite_mSetControlReg((BaseAddress), \ + XUartLite_mGetControlReg((BaseAddress)) | XUL_CR_ENABLE_INTR) + + +/****************************************************************************/ +/** +* +* Disable the device interrupt. Preserve the contents of the control register. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mDisableIntr(BaseAddress) \ + XUartLite_mSetControlReg((BaseAddress), \ + XUartLite_mGetControlReg((BaseAddress)) & ~XUL_CR_ENABLE_INTR) + + +/************************** Function Prototypes *****************************/ + +void XUartLite_SendByte(u32 BaseAddress, u8 Data); +u8 XUartLite_RecvByte(u32 BaseAddress); + + +#endif /* end of protection macro */ diff --git a/include/asm-microblaze/bitops.h b/include/asm-microblaze/bitops.h new file mode 100644 index 0000000..04ea020 --- /dev/null +++ b/include/asm-microblaze/bitops.h @@ -0,0 +1,392 @@ +#ifndef _MICROBLAZE_BITOPS_H +#define _MICROBLAZE_BITOPS_H + +/* + * Copyright 1992, Linus Torvalds. + */ + +#include +#include /* swab32 */ +#include /* save_flags */ + +#ifdef __KERNEL__ +/* + * Function prototypes to keep gcc -Wall happy + */ + +/* + * The __ functions are not atomic + */ + +extern void set_bit(int nr, volatile void * addr); +extern void __set_bit(int nr, volatile void * addr); + +extern void clear_bit(int nr, volatile void * addr); +#define __clear_bit(nr, addr) clear_bit(nr, addr) + +extern void change_bit(int nr, volatile void * addr); +extern void __change_bit(int nr, volatile void * addr); +extern int test_and_set_bit(int nr, volatile void * addr); +extern int __test_and_set_bit(int nr, volatile void * addr); +extern int test_and_clear_bit(int nr, volatile void * addr); +extern int __test_and_clear_bit(int nr, volatile void * addr); +extern int test_and_change_bit(int nr, volatile void * addr); +extern int __test_and_change_bit(int nr, volatile void * addr); +extern int __constant_test_bit(int nr, const volatile void * addr); +extern int __test_bit(int nr, volatile void * addr); +extern int find_first_zero_bit(void * addr, unsigned size); +extern int find_next_zero_bit (void * addr, int size, int offset); + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +extern __inline__ unsigned long ffz(unsigned long word) +{ + unsigned long result = 0; + + while(word & 1) { + result++; + word >>= 1; + } + return result; +} + + +extern __inline__ void set_bit(int nr, volatile void * addr) +{ + int * a = (int *) addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + *a |= mask; + restore_flags(flags); +} + +extern __inline__ void __set_bit(int nr, volatile void * addr) +{ + int * a = (int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +extern __inline__ void clear_bit(int nr, volatile void * addr) +{ + int * a = (int *) addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + *a &= ~mask; + restore_flags(flags); +} + +extern __inline__ void change_bit(int nr, volatile void * addr) +{ + int mask; + unsigned long flags; + unsigned long *ADDR = (unsigned long *) addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + save_flags_cli(flags); + *ADDR ^= mask; + restore_flags(flags); +} + +extern __inline__ void __change_bit(int nr, volatile void * addr) +{ + int mask; + unsigned long *ADDR = (unsigned long *) addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + *ADDR ^= mask; +} + +extern __inline__ int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + retval = (mask & *a) != 0; + *a |= mask; + restore_flags(flags); + + return retval; +} + +extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + return retval; +} + +extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + restore_flags(flags); + + return retval; +} + +extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + return retval; +} + +extern __inline__ int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_flags_cli(flags); + retval = (mask & *a) != 0; + *a ^= mask; + restore_flags(flags); + + return retval; +} + +extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + return retval; +} + +/* + * This routine doesn't need to be atomic. + */ +extern __inline__ int __constant_test_bit(int nr, const volatile void * addr) +{ + return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; +} + +extern __inline__ int __test_bit(int nr, volatile void * addr) +{ + int * a = (int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + return ((mask & *a) != 0); +} + +#define test_bit(nr,addr) \ +(__builtin_constant_p(nr) ? \ + __constant_test_bit((nr),(addr)) : \ + __test_bit((nr),(addr))) + +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32-offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL >> size; +found_middle: + return result + ffz(tmp); +} + +#define ffs(x) generic_ffs(x) + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + + +extern __inline__ int ext2_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_flags_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR |= mask; + restore_flags(flags); + return retval; +} + +extern __inline__ int ext2_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_flags_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR &= ~mask; + restore_flags(flags); + return retval; +} + +extern __inline__ int ext2_test_bit(int nr, const volatile void * addr) +{ + int mask; + const volatile unsigned char *ADDR = (const unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + return ((mask & *ADDR) != 0); +} + +#define ext2_find_first_zero_bit(addr, size) \ + ext2_find_next_zero_bit((addr), (size), 0) + +extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if(offset) { + /* We hold the little endian value in tmp, but then the + * shift is illegal. So we could keep a big endian value + * in tmp, like this: + * + * tmp = __swab32(*(p++)); + * tmp |= ~0UL >> (32-offset); + * + * but this would decrease preformance, so we change the + * shift: + */ + tmp = *(p++); + tmp |= __swab32(~0UL >> (32-offset)); + if(size < 32) + goto found_first; + if(~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while(size & ~31UL) { + if(~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if(!size) + return result; + tmp = *p; + +found_first: + /* tmp is little endian, so we would have to swab the shift, + * see above. But then we have to swab tmp below for ffz, so + * we might as well do this here. + */ + return result + ffz(__swab32(tmp) | (~0UL << size)); +found_middle: + return result + ffz(__swab32(tmp)); +} + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +/** + * hweightN - returns the hamming weight of a N-bit word + * @x: the word to weigh + * + * The Hamming Weight of a number is the total number of bits set in it. + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#endif /* __KERNEL__ */ + +#endif /* _MICROBLAZE_BITOPS_H */ diff --git a/include/asm-microblaze/byteorder.h b/include/asm-microblaze/byteorder.h new file mode 100644 index 0000000..51cacb0 --- /dev/null +++ b/include/asm-microblaze/byteorder.h @@ -0,0 +1,53 @@ +/* + * include/asm-microblaze/byteorder.h -- Endian id and conversion ops + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001 NEC Corporation + * Copyright (C) 2001 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_BYTEORDER_H__ +#define __MICROBLAZE_BYTEORDER_H__ + +#include + +#ifdef __GNUC__ + +/* This is effectively a dupe of the arch-independent byteswap + code in include/linux/byteorder/swab.h, however we force a cast + of the result up to 32 bits. This in turn forces the compiler + to explicitly clear the high 16 bits, which it wasn't doing otherwise. + + I think this is a symptom of a bug in mb-gcc. JW 20040303 +*/ +static __inline__ __const__ __u16 ___arch__swab16 (__u16 half_word) +{ + /* 32 bit temp to cast result, forcing clearing of high word */ + __u32 temp; + + temp = ((half_word & 0x00FFU) << 8) | ((half_word & 0xFF00U) >> 8); + + return (__u16) temp; +} + +#define __arch__swab16(x) ___arch__swab16(x) + +/* Microblaze has no arch-specific endian conversion insns */ + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#endif /* __GNUC__ */ + +#include + +#endif /* __MICROBLAZE_BYTEORDER_H__ */ diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h new file mode 100644 index 0000000..a6e7834 --- /dev/null +++ b/include/asm-microblaze/global_data.h @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long fb_base; /* base address of frame buffer */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") + +#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h new file mode 100644 index 0000000..3359045 --- /dev/null +++ b/include/asm-microblaze/io.h @@ -0,0 +1,128 @@ +/* + * include/asm-microblaze/io.h -- Misc I/O operations + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001,02 NEC Corporation + * Copyright (C) 2001,02 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_IO_H__ +#define __MICROBLAZE_IO_H__ + +#define IO_SPACE_LIMIT 0xFFFFFFFF + +#define readb(addr) \ + ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) +#define readw(addr) \ + ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) +#define readl(addr) \ + ({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; }) + +#define writeb(b, addr) \ + (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b, addr) \ + (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b, addr) \ + (void)((*(volatile unsigned int *) (addr)) = (b)) + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +#define inb(addr) readb (addr) +#define inw(addr) readw (addr) +#define inl(addr) readl (addr) +#define outb(x, addr) ((void) writeb (x, addr)) +#define outw(x, addr) ((void) writew (x, addr)) +#define outl(x, addr) ((void) writel (x, addr)) + +/* Some #definitions to keep strange Xilinx code happy */ +#define in_8(addr) readb (addr) +#define in_be16(addr) readw (addr) +#define in_be32(addr) readl (addr) + +#define out_8(addr,x ) outb (x,addr) +#define out_be16(addr,x ) outw (x,addr) +#define out_be32(addr,x ) outl (x,addr) + + +#define inb_p(port) inb((port)) +#define outb_p(val, port) outb((val), (port)) +#define inw_p(port) inw((port)) +#define outw_p(val, port) outw((val), (port)) +#define inl_p(port) inl((port)) +#define outl_p(val, port) outl((val), (port)) + +/* Some defines to keep the MTD flash drivers happy */ + +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +static inline void io_insb (unsigned long port, void *dst, unsigned long count) +{ + unsigned char *p = dst; + while (count--) + *p++ = inb (port); +} +static inline void io_insw (unsigned long port, void *dst, unsigned long count) +{ + unsigned short *p = dst; + while (count--) + *p++ = inw (port); +} +static inline void io_insl (unsigned long port, void *dst, unsigned long count) +{ + unsigned long *p = dst; + while (count--) + *p++ = inl (port); +} + +static inline void +io_outsb (unsigned long port, const void *src, unsigned long count) +{ + const unsigned char *p = src; + while (count--) + outb (*p++, port); +} +static inline void +io_outsw (unsigned long port, const void *src, unsigned long count) +{ + const unsigned short *p = src; + while (count--) + outw (*p++, port); +} +static inline void +io_outsl (unsigned long port, const void *src, unsigned long count) +{ + const unsigned long *p = src; + while (count--) + outl (*p++, port); +} + +#define outsb(a,b,l) io_outsb(a,b,l) +#define outsw(a,b,l) io_outsw(a,b,l) +#define outsl(a,b,l) io_outsl(a,b,l) + +#define insb(a,b,l) io_insb(a,b,l) +#define insw(a,b,l) io_insw(a,b,l) +#define insl(a,b,l) io_insl(a,b,l) + + +#define iounmap(addr) ((void)0) +#define ioremap(physaddr, size) (physaddr) +#define ioremap_nocache(physaddr, size) (physaddr) +#define ioremap_writethrough(physaddr, size) (physaddr) +#define ioremap_fullcache(physaddr, size) (physaddr) + +#endif /* __MICROBLAZE_IO_H__ */ diff --git a/include/asm-microblaze/platform.h b/include/asm-microblaze/platform.h new file mode 100644 index 0000000..2096cce --- /dev/null +++ b/include/asm-microblaze/platform.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_SUZAKU +#include +#endif diff --git a/include/asm-microblaze/posix_types.h b/include/asm-microblaze/posix_types.h new file mode 100644 index 0000000..9a2cc66 --- /dev/null +++ b/include/asm-microblaze/posix_types.h @@ -0,0 +1,76 @@ +/* + * include/asm-microblaze/posix_types.h -- Kernel versions of standard types + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001,2002 NEC Corporation + * Copyright (C) 2001,2002 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_POSIX_TYPES_H__ +#define __MICROBLAZE_POSIX_TYPES_H__ + +#include + + +typedef unsigned int __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned long long __kernel_ino64_t; +typedef unsigned int __kernel_mode_t; +typedef unsigned int __kernel_nlink_t; +typedef long __kernel_off_t; +typedef long long __kernel_loff_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fd_set) \ + __set_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) +#undef __FD_CLR +#define __FD_CLR(fd, fd_set) \ + __clear_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) +#undef __FD_ISSET +#define __FD_ISSET(fd, fd_set) \ + __test_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) +#undef __FD_ZERO +#define __FD_ZERO(fd_set) \ + memset (fd_set, 0, sizeof (*(fd_set *)fd_set)) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* __MICROBLAZE_POSIX_TYPES_H__ */ diff --git a/include/asm-microblaze/processor.h b/include/asm-microblaze/processor.h new file mode 100644 index 0000000..78b8976 --- /dev/null +++ b/include/asm-microblaze/processor.h @@ -0,0 +1 @@ +/* FIXME: Implement this! */ diff --git a/include/asm-microblaze/ptrace.h b/include/asm-microblaze/ptrace.h new file mode 100644 index 0000000..b796d4f --- /dev/null +++ b/include/asm-microblaze/ptrace.h @@ -0,0 +1,116 @@ +/* + * include/asm-microblaze/ptrace.h -- Access to CPU registers + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001,2002 NEC Corporation + * Copyright (C) 2001,2002 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_PTRACE_H__ +#define __MICROBLAZE_PTRACE_H__ + + +/* Microblaze general purpose registers with special meanings. */ +#define GPR_ZERO 0 /* constant zero */ +#define GPR_ASM 18 /* reserved for assembler */ +#define GPR_SP 1 /* stack pointer */ +#define GPR_GP 2 /* global data pointer */ +#define GPR_EP 30 /* `element pointer' */ +#define GPR_LP 15 /* link pointer (current return address) */ + +/* These aren't official names, but they make some code more descriptive. */ +#define GPR_ARG0 5 +#define GPR_ARG1 6 +#define GPR_ARG2 7 +#define GPR_ARG3 8 +#define GPR_ARG4 9 +#define GPR_ARG5 10 +#define GPR_RVAL0 3 +#define GPR_RVAL1 4 +#define GPR_RVAL GPR_RVAL0 + +#define NUM_GPRS 32 + +/* `system' registers. */ +/* Note these are old v850 values, microblaze has many fewer */ +#define SR_EIPC 0 +#define SR_EIPSW 1 +#define SR_FEPC 2 +#define SR_FEPSW 3 +#define SR_ECR 4 +#define SR_PSW 5 +#define SR_CTPC 16 +#define SR_CTPSW 17 +#define SR_DBPC 18 +#define SR_DBPSW 19 +#define SR_CTBP 20 +#define SR_DIR 21 +#define SR_ASID 23 + + +#ifndef __ASSEMBLY__ + +typedef unsigned long microblaze_reg_t; + +/* How processor state is stored on the stack during a syscall/signal. + If you change this structure, change the associated assembly-language + macros below too (PT_*)! */ +struct pt_regs +{ + /* General purpose registers. */ + microblaze_reg_t gpr[NUM_GPRS]; + + microblaze_reg_t pc; /* program counter */ + microblaze_reg_t psw; /* program status word */ + + microblaze_reg_t kernel_mode; /* 1 if in `kernel mode', 0 if user mode */ + microblaze_reg_t single_step; /* 1 if in single step mode */ +}; + + +#define instruction_pointer(regs) ((regs)->pc) +#define user_mode(regs) (!(regs)->kernel_mode) + +/* When a struct pt_regs is used to save user state for a system call in + the kernel, the system call is stored in the space for R0 (since it's + never used otherwise, R0 being a constant 0). Non-system-calls + simply store 0 there. */ +#define PT_REGS_SYSCALL(regs) (regs)->gpr[0] +#define PT_REGS_SET_SYSCALL(regs, val) ((regs)->gpr[0] = (val)) + +#endif /* !__ASSEMBLY__ */ + + +/* The number of bytes used to store each register. */ +#define _PT_REG_SIZE 4 + +/* Offset of a general purpose register in a stuct pt_regs. */ +#define PT_GPR(num) ((num) * _PT_REG_SIZE) + +/* Offsets of various special registers & fields in a struct pt_regs. */ +#define NUM_SPECIAL 4 +#define PT_PC ((NUM_GPRS + 0) * _PT_REG_SIZE) +#define PT_PSW ((NUM_GPRS + 1) * _PT_REG_SIZE) +#define PT_KERNEL_MODE ((NUM_GPRS + 2) * _PT_REG_SIZE) +#define PT_SINGLESTEP ((NUM_GPRS + 3) * _PT_REG_SIZE) + +#define PT_SYSCALL PT_GPR(0) + +/* Size of struct pt_regs, including alignment. */ +#define PT_SIZE ((NUM_GPRS + NUM_SPECIAL) * _PT_REG_SIZE) + +/* These are `magic' values for PTRACE_PEEKUSR that return info about where + a process is located in memory. */ +#define PT_TEXT_ADDR (PT_SIZE + 1) +#define PT_TEXT_LEN (PT_SIZE + 2) +#define PT_DATA_ADDR (PT_SIZE + 3) +#define PT_DATA_LEN (PT_SIZE + 4) + +#endif /* __MICROBLAZE_PTRACE_H__ */ diff --git a/include/asm-microblaze/serial_xuartlite.h b/include/asm-microblaze/serial_xuartlite.h new file mode 100644 index 0000000..6cd1e83 --- /dev/null +++ b/include/asm-microblaze/serial_xuartlite.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include diff --git a/include/asm-microblaze/string.h b/include/asm-microblaze/string.h new file mode 100644 index 0000000..724f5bd --- /dev/null +++ b/include/asm-microblaze/string.h @@ -0,0 +1,31 @@ +/* + * include/asm-microblaze/string.h -- Architecture specific string routines + * + * Copyright (C) 2003 John Williams + * Copyright (C) 2001,2002 NEC Corporation + * Copyright (C) 2001,2002 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_STRING_H__ +#define __MICROBLAZE_STRING_H__ + +#if 0 +#define __HAVE_ARCH_BCOPY +#define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_MEMMOVE + +extern void *memcpy (void *, const void *, __kernel_size_t); +extern void bcopy (const char *, char *, int); +extern void *memset (void *, int, __kernel_size_t); +extern void *memmove (void *, const void *, __kernel_size_t); +#endif + +#endif /* __MICROBLAZE_STRING_H__ */ diff --git a/include/asm-microblaze/suzaku.h b/include/asm-microblaze/suzaku.h new file mode 100644 index 0000000..c57a144 --- /dev/null +++ b/include/asm-microblaze/suzaku.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* System Register (GPIO) */ +#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000 +#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0) diff --git a/include/asm-microblaze/system.h b/include/asm-microblaze/system.h new file mode 100644 index 0000000..0297a11 --- /dev/null +++ b/include/asm-microblaze/system.h @@ -0,0 +1,161 @@ +/* + * include/asm-microblaze/system.h -- Low-level interrupt/thread ops + * + * Copyright (C) 2003 John Williams (jwilliams@itee.uq.edu.au) + * based upon microblaze version + * Copyright (C) 2001 NEC Corporation + * Copyright (C) 2001 Miles Bader + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader + * Microblaze port by John Williams + * Microblaze port by John Williams + */ + +#ifndef __MICROBLAZE_SYSTEM_H__ +#define __MICROBLAZE_SYSTEM_H__ + +#if 0 +#include +#endif +#include + +#define prepare_to_switch() do { } while (0) + +/* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. + */ +struct thread_struct; +extern void *switch_thread (struct thread_struct *last, + struct thread_struct *next); +#define switch_to(prev,next,last) do { \ + if (prev != next) { \ + (last) = switch_thread (&prev->thread, &next->thread); \ + } \ +} while (0) + + +/* Enable/disable interrupts. */ +#define __sti() \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + ori %0, %0, 2; \ + mts rmsr, %0" \ + : "=r" (tmp) \ + : \ + : "memory"); \ +} + +#define __cli() \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + andi %0, %0, ~2; \ + mts rmsr, %0" \ + : "=r" (tmp) \ + : \ + : "memory"); \ +} + +#define __save_flags(flags) \ + __asm__ __volatile__ ("mfs %0, rmsr" : "=r" (flags)) +#define __restore_flags(flags) \ + __asm__ __volatile__ ("mts rmsr, %0" :: "r" (flags)) + +#define __save_flags_cli(flags) \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + andi %1, %0, ~2; \ + mts rmsr, %1;" \ + : "=r" (flags), "=r" (tmp) \ + : \ + : "memory"); \ +} + +#define __save_flags_sti(flags) \ +{ \ + register unsigned tmp; \ + __asm__ __volatile__ (" \ + mfs %0, rmsr; \ + ori %1, %0, 2; \ + mts rmsr, %1;" \ + : "=r" (flags) ,"=r" (tmp) \ + : \ + : "memory"); \ +} + +/* For spinlocks etc */ +#define local_irq_save(flags) __save_flags_cli (flags) +#define local_irq_set(flags) __save_flags_sti (flags) +#define local_irq_restore(flags) __restore_flags (flags) +#define local_irq_disable() __cli () +#define local_irq_enable() __sti () + +#define cli() __cli () +#define sti() __sti () +#define save_flags(flags) __save_flags (flags) +#define restore_flags(flags) __restore_flags (flags) +#define save_flags_cli(flags) __save_flags_cli (flags) + +/* + * Force strict CPU ordering. + * Not really required on microblaze... + */ +#define nop() __asm__ __volatile__ ("nop") +#define mb() __asm__ __volatile__ ("nop" ::: "memory") +#define rmb() mb () +#define wmb() mb () +#define set_mb(var, value) do { var = value; mb(); } while (0) +#define set_wmb(var, value) do { var = value; wmb (); } while (0) + +#ifdef CONFIG_SMP +#define smp_mb() mb () +#define smp_rmb() rmb () +#define smp_wmb() wmb () +#else +#define smp_mb() barrier () +#define smp_rmb() barrier () +#define smp_wmb() barrier () +#endif + +#define xchg(ptr, with) \ + ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr)))) +#define tas(ptr) (xchg ((ptr), 1)) + +extern inline unsigned long __xchg (unsigned long with, + __volatile__ void *ptr, int size) +{ + unsigned long tmp, flags; + + save_flags_cli (flags); + + switch (size) { + case 1: + tmp = *(unsigned char *)ptr; + *(unsigned char *)ptr = with; + break; + case 2: + tmp = *(unsigned short *)ptr; + *(unsigned short *)ptr = with; + break; + case 4: + tmp = *(unsigned long *)ptr; + *(unsigned long *)ptr = with; + break; + } + + restore_flags (flags); + + return tmp; +} + +#endif /* __MICROBLAZE_SYSTEM_H__ */ diff --git a/include/asm-microblaze/types.h b/include/asm-microblaze/types.h new file mode 100644 index 0000000..8c4bef2 --- /dev/null +++ b/include/asm-microblaze/types.h @@ -0,0 +1,57 @@ +#ifndef _ASM_TYPES_H +#define _ASM_TYPES_H + +/* + * This file is never included by application software unless + * explicitly requested (e.g., via linux/types.h) in which case the + * application is Linux specific so (user-) name space pollution is + * not a major issue. However, for interoperability, libraries still + * need to be careful to avoid a name clashes. + */ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; +#endif /* __KERNEL__ */ + +#endif /* _ASM_TYPES_H */ diff --git a/include/asm-microblaze/u-boot.h b/include/asm-microblaze/u-boot.h new file mode 100644 index 0000000..e2035bd --- /dev/null +++ b/include/asm-microblaze/u-boot.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_baudrate; /* Console Baudrate */ +} bd_t; + + +#endif /* _U_BOOT_H_ */ diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h new file mode 100644 index 0000000..b8214b1 --- /dev/null +++ b/include/asm-mips/addrspace.h @@ -0,0 +1,82 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + * Copyright (C) 2000 by Maciej W. Rozycki + * + * Defitions for the address spaces of the MIPS CPUs. + */ +#ifndef __ASM_MIPS_ADDRSPACE_H +#define __ASM_MIPS_ADDRSPACE_H + +/* + * Memory segments (32bit kernel mode addresses) + */ +#define KUSEG 0x00000000 +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 +#define KSEG2 0xc0000000 +#define KSEG3 0xe0000000 + +#define K0BASE KSEG0 + +/* + * Returns the kernel segment base of a given address + */ +#ifndef __ASSEMBLY__ +#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) +#else +#define KSEGX(a) ((a) & 0xe0000000) +#endif + +/* + * Returns the physical address of a KSEG0/KSEG1 address + */ +#ifndef __ASSEMBLY__ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) +#else +#define PHYSADDR(a) ((a) & 0x1fffffff) +#endif + +/* + * Returns the uncached address of a sdram address + */ +#ifndef __ASSEMBLY__ +#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229) +/* We use a 36 bit physical address map here and + cannot access physical memory directly from core */ +#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) +#else /* !CONFIG_AU1X00 */ +#define UNCACHED_SDRAM(a) PHYSADDR(a) +#endif /* CONFIG_AU1X00 */ +#endif /* __ASSEMBLY__ */ +/* + * Map an address to a certain kernel segment + */ +#ifndef __ASSEMBLY__ +#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) +#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) +#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) +#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) +#else +#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) +#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) +#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2) +#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) +#endif + +/* + * Memory segments (64bit kernel mode addresses) + */ +#define XKUSEG 0x0000000000000000 +#define XKSSEG 0x4000000000000000 +#define XKPHYS 0x8000000000000000 +#define XKSEG 0xc000000000000000 +#define CKSEG0 0xffffffff80000000 +#define CKSEG1 0xffffffffa0000000 +#define CKSSEG 0xffffffffc0000000 +#define CKSEG3 0xffffffffe0000000 + +#endif /* __ASM_MIPS_ADDRSPACE_H */ diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h new file mode 100644 index 0000000..4e19dc4 --- /dev/null +++ b/include/asm-mips/au1x00.h @@ -0,0 +1,1085 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Include file for Alchemy Semiconductor's Au1k CPU. + * + * Copyright 2000,2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + /* + * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp + */ + +#ifndef _AU1X00_H_ +#define _AU1X00_H_ + +#ifndef __ASSEMBLY__ +/* cpu pipeline flush */ +void static inline au_sync(void) +{ + __asm__ volatile ("sync"); +} + +void static inline au_sync_udelay(int us) +{ + __asm__ volatile ("sync"); + udelay(us); +} + +void static inline au_writeb(u8 val, int reg) +{ + *(volatile u8 *)(reg) = val; +} + +void static inline au_writew(u16 val, int reg) +{ + *(volatile u16 *)(reg) = val; +} + +void static inline au_writel(u32 val, int reg) +{ + *(volatile u32 *)(reg) = val; +} + +static inline u8 au_readb(unsigned long port) +{ + return (*(volatile u8 *)port); +} + +static inline u16 au_readw(unsigned long port) +{ + return (*(volatile u16 *)port); +} + +static inline u32 au_readl(unsigned long port) +{ + return (*(volatile u32 *)port); +} + +/* These next three functions should be a generic part of the MIPS + * kernel (with the 'au_' removed from the name) and selected for + * processors that support the instructions. + * Taken from PPC tree. -- Dan + */ +/* Return the bit position of the most significant 1 bit in a word */ +static __inline__ int __ilog2(unsigned int x) +{ + int lz; + + asm volatile ( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips32\n\t" + "clz\t%0,%1\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (lz) + : "r" (x)); + + return 31 - lz; +} + +static __inline__ int au_ffz(unsigned int x) +{ + if ((x = ~x) == 0) + return 32; + return __ilog2(x & -x); +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static __inline__ int au_ffs(int x) +{ + return __ilog2(x & -x) + 1; +} + +#endif /* !ASSEMBLY */ + +#ifdef CONFIG_PM +/* no CP0 timer irq */ +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) +#else +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) +#endif + +#define CP0_IWATCHLO $18,1 +#define CP0_DEBUG $23 + +/* SDRAM Controller */ +#ifdef CONFIG_AU1550 + +#define MEM_SDMODE0 0xB4000800 +#define MEM_SDMODE1 0xB4000808 +#define MEM_SDMODE2 0xB4000810 + +#define MEM_SDADDR0 0xB4000820 +#define MEM_SDADDR1 0xB4000828 +#define MEM_SDADDR2 0xB4000830 + +#define MEM_SDCONFIGA 0xB4000840 +#define MEM_SDCONFIGB 0xB4000848 +#define MEM_SDPRECMD 0xB40008c0 +#define MEM_SDAUTOREF 0xB40008c8 + +#define MEM_SDWRMD0 0xB4000880 +#define MEM_SDWRMD1 0xB4000888 +#define MEM_SDWRMD2 0xB4000890 + +#else /* CONFIG_AU1550 */ + +#define MEM_SDMODE0 0xB4000000 +#define MEM_SDMODE1 0xB4000004 +#define MEM_SDMODE2 0xB4000008 + +#define MEM_SDADDR0 0xB400000C +#define MEM_SDADDR1 0xB4000010 +#define MEM_SDADDR2 0xB4000014 + +#define MEM_SDREFCFG 0xB4000018 +#define MEM_SDPRECMD 0xB400001C +#define MEM_SDAUTOREF 0xB4000020 + +#define MEM_SDWRMD0 0xB4000024 +#define MEM_SDWRMD1 0xB4000028 +#define MEM_SDWRMD2 0xB400002C + +#endif /* CONFIG_AU1550 */ + +#define MEM_SDSLEEP 0xB4000030 +#define MEM_SDSMCKE 0xB4000034 + +/* Static Bus Controller */ +#define MEM_STCFG0 0xB4001000 +#define MEM_STTIME0 0xB4001004 +#define MEM_STADDR0 0xB4001008 + +#define MEM_STCFG1 0xB4001010 +#define MEM_STTIME1 0xB4001014 +#define MEM_STADDR1 0xB4001018 + +#define MEM_STCFG2 0xB4001020 +#define MEM_STTIME2 0xB4001024 +#define MEM_STADDR2 0xB4001028 + +#define MEM_STCFG3 0xB4001030 +#define MEM_STTIME3 0xB4001034 +#define MEM_STADDR3 0xB4001038 + +/* Interrupt Controller 0 */ +#define IC0_CFG0RD 0xB0400040 +#define IC0_CFG0SET 0xB0400040 +#define IC0_CFG0CLR 0xB0400044 + +#define IC0_CFG1RD 0xB0400048 +#define IC0_CFG1SET 0xB0400048 +#define IC0_CFG1CLR 0xB040004C + +#define IC0_CFG2RD 0xB0400050 +#define IC0_CFG2SET 0xB0400050 +#define IC0_CFG2CLR 0xB0400054 + +#define IC0_REQ0INT 0xB0400054 +#define IC0_SRCRD 0xB0400058 +#define IC0_SRCSET 0xB0400058 +#define IC0_SRCCLR 0xB040005C +#define IC0_REQ1INT 0xB040005C + +#define IC0_ASSIGNRD 0xB0400060 +#define IC0_ASSIGNSET 0xB0400060 +#define IC0_ASSIGNCLR 0xB0400064 + +#define IC0_WAKERD 0xB0400068 +#define IC0_WAKESET 0xB0400068 +#define IC0_WAKECLR 0xB040006C + +#define IC0_MASKRD 0xB0400070 +#define IC0_MASKSET 0xB0400070 +#define IC0_MASKCLR 0xB0400074 + +#define IC0_RISINGRD 0xB0400078 +#define IC0_RISINGCLR 0xB0400078 +#define IC0_FALLINGRD 0xB040007C +#define IC0_FALLINGCLR 0xB040007C + +#define IC0_TESTBIT 0xB0400080 + +/* Interrupt Controller 1 */ +#define IC1_CFG0RD 0xB1800040 +#define IC1_CFG0SET 0xB1800040 +#define IC1_CFG0CLR 0xB1800044 + +#define IC1_CFG1RD 0xB1800048 +#define IC1_CFG1SET 0xB1800048 +#define IC1_CFG1CLR 0xB180004C + +#define IC1_CFG2RD 0xB1800050 +#define IC1_CFG2SET 0xB1800050 +#define IC1_CFG2CLR 0xB1800054 + +#define IC1_REQ0INT 0xB1800054 +#define IC1_SRCRD 0xB1800058 +#define IC1_SRCSET 0xB1800058 +#define IC1_SRCCLR 0xB180005C +#define IC1_REQ1INT 0xB180005C + +#define IC1_ASSIGNRD 0xB1800060 +#define IC1_ASSIGNSET 0xB1800060 +#define IC1_ASSIGNCLR 0xB1800064 + +#define IC1_WAKERD 0xB1800068 +#define IC1_WAKESET 0xB1800068 +#define IC1_WAKECLR 0xB180006C + +#define IC1_MASKRD 0xB1800070 +#define IC1_MASKSET 0xB1800070 +#define IC1_MASKCLR 0xB1800074 + +#define IC1_RISINGRD 0xB1800078 +#define IC1_RISINGCLR 0xB1800078 +#define IC1_FALLINGRD 0xB180007C +#define IC1_FALLINGCLR 0xB180007C + +#define IC1_TESTBIT 0xB1800080 + +/* Interrupt Configuration Modes */ +#define INTC_INT_DISABLED 0 +#define INTC_INT_RISE_EDGE 0x1 +#define INTC_INT_FALL_EDGE 0x2 +#define INTC_INT_RISE_AND_FALL_EDGE 0x3 +#define INTC_INT_HIGH_LEVEL 0x5 +#define INTC_INT_LOW_LEVEL 0x6 +#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 + +/* Interrupt Numbers */ +#define AU1X00_UART0_INT 0 +#define AU1000_UART1_INT 1 /* au1000 */ +#define AU1000_UART2_INT 2 /* au1000 */ + +#define AU1500_PCI_INTA 1 /* au1500 */ +#define AU1500_PCI_INTB 2 /* au1500 */ + +#define AU1X00_UART3_INT 3 + +#define AU1000_SSI0_INT 4 /* au1000 */ +#define AU1000_SSI1_INT 5 /* au1000 */ + +#define AU1500_PCI_INTC 4 /* au1500 */ +#define AU1500_PCI_INTD 5 /* au1500 */ + +#define AU1X00_DMA_INT_BASE 6 +#define AU1X00_TOY_INT 14 +#define AU1X00_TOY_MATCH0_INT 15 +#define AU1X00_TOY_MATCH1_INT 16 +#define AU1X00_TOY_MATCH2_INT 17 +#define AU1X00_RTC_INT 18 +#define AU1X00_RTC_MATCH0_INT 19 +#define AU1X00_RTC_MATCH1_INT 20 +#define AU1X00_RTC_MATCH2_INT 21 +#define AU1000_IRDA_TX_INT 22 /* au1000 */ +#define AU1000_IRDA_RX_INT 23 /* au1000 */ +#define AU1X00_USB_DEV_REQ_INT 24 +#define AU1X00_USB_DEV_SUS_INT 25 +#define AU1X00_USB_HOST_INT 26 +#define AU1X00_ACSYNC_INT 27 +#define AU1X00_MAC0_DMA_INT 28 +#define AU1X00_MAC1_DMA_INT 29 +#define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT +#define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT +#define AU1000_I2S_UO_INT 30 /* au1000 */ +#define AU1X00_AC97C_INT 31 +#define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT +#define AU1X00_GPIO_0 32 +#define AU1X00_GPIO_1 33 +#define AU1X00_GPIO_2 34 +#define AU1X00_GPIO_3 35 +#define AU1X00_GPIO_4 36 +#define AU1X00_GPIO_5 37 +#define AU1X00_GPIO_6 38 +#define AU1X00_GPIO_7 39 +#define AU1X00_GPIO_8 40 +#define AU1X00_GPIO_9 41 +#define AU1X00_GPIO_10 42 +#define AU1X00_GPIO_11 43 +#define AU1X00_GPIO_12 44 +#define AU1X00_GPIO_13 45 +#define AU1X00_GPIO_14 46 +#define AU1X00_GPIO_15 47 + +/* Au1000 only */ +#define AU1000_GPIO_16 48 +#define AU1000_GPIO_17 49 +#define AU1000_GPIO_18 50 +#define AU1000_GPIO_19 51 +#define AU1000_GPIO_20 52 +#define AU1000_GPIO_21 53 +#define AU1000_GPIO_22 54 +#define AU1000_GPIO_23 55 +#define AU1000_GPIO_24 56 +#define AU1000_GPIO_25 57 +#define AU1000_GPIO_26 58 +#define AU1000_GPIO_27 59 +#define AU1000_GPIO_28 60 +#define AU1000_GPIO_29 61 +#define AU1000_GPIO_30 62 +#define AU1000_GPIO_31 63 + +/* Au1500 only */ +#define AU1500_GPIO_200 48 +#define AU1500_GPIO_201 49 +#define AU1500_GPIO_202 50 +#define AU1500_GPIO_203 51 +#define AU1500_GPIO_20 52 +#define AU1500_GPIO_204 53 +#define AU1500_GPIO_205 54 +#define AU1500_GPIO_23 55 +#define AU1500_GPIO_24 56 +#define AU1500_GPIO_25 57 +#define AU1500_GPIO_26 58 +#define AU1500_GPIO_27 59 +#define AU1500_GPIO_28 60 +#define AU1500_GPIO_206 61 +#define AU1500_GPIO_207 62 +#define AU1500_GPIO_208_215 63 + +#define AU1X00_MAX_INTR 63 + +#define AU1100_SD 2 +#define AU1100_GPIO_208_215 29 +/* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */ + +/* Programmable Counters 0 and 1 */ +#define SYS_BASE 0xB1900000 +#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) +#define SYS_CNTRL_E1S (1<<23) +#define SYS_CNTRL_T1S (1<<20) +#define SYS_CNTRL_M21 (1<<19) +#define SYS_CNTRL_M11 (1<<18) +#define SYS_CNTRL_M01 (1<<17) +#define SYS_CNTRL_C1S (1<<16) +#define SYS_CNTRL_BP (1<<14) +#define SYS_CNTRL_EN1 (1<<13) +#define SYS_CNTRL_BT1 (1<<12) +#define SYS_CNTRL_EN0 (1<<11) +#define SYS_CNTRL_BT0 (1<<10) +#define SYS_CNTRL_E0 (1<<8) +#define SYS_CNTRL_E0S (1<<7) +#define SYS_CNTRL_32S (1<<5) +#define SYS_CNTRL_T0S (1<<4) +#define SYS_CNTRL_M20 (1<<3) +#define SYS_CNTRL_M10 (1<<2) +#define SYS_CNTRL_M00 (1<<1) +#define SYS_CNTRL_C0S (1<<0) + +/* Programmable Counter 0 Registers */ +#define SYS_TOYTRIM (SYS_BASE + 0) +#define SYS_TOYWRITE (SYS_BASE + 4) +#define SYS_TOYMATCH0 (SYS_BASE + 8) +#define SYS_TOYMATCH1 (SYS_BASE + 0xC) +#define SYS_TOYMATCH2 (SYS_BASE + 0x10) +#define SYS_TOYREAD (SYS_BASE + 0x40) + +/* Programmable Counter 1 Registers */ +#define SYS_RTCTRIM (SYS_BASE + 0x44) +#define SYS_RTCWRITE (SYS_BASE + 0x48) +#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) +#define SYS_RTCMATCH1 (SYS_BASE + 0x50) +#define SYS_RTCMATCH2 (SYS_BASE + 0x54) +#define SYS_RTCREAD (SYS_BASE + 0x58) + +/* I2S Controller */ +#define I2S_DATA 0xB1000000 +#define I2S_DATA_MASK (0xffffff) +#define I2S_CONFIG 0xB1000004 +#define I2S_CONFIG_XU (1<<25) +#define I2S_CONFIG_XO (1<<24) +#define I2S_CONFIG_RU (1<<23) +#define I2S_CONFIG_RO (1<<22) +#define I2S_CONFIG_TR (1<<21) +#define I2S_CONFIG_TE (1<<20) +#define I2S_CONFIG_TF (1<<19) +#define I2S_CONFIG_RR (1<<18) +#define I2S_CONFIG_RE (1<<17) +#define I2S_CONFIG_RF (1<<16) +#define I2S_CONFIG_PD (1<<11) +#define I2S_CONFIG_LB (1<<10) +#define I2S_CONFIG_IC (1<<9) +#define I2S_CONFIG_FM_BIT 7 +#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) +#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) +#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) +#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) +#define I2S_CONFIG_TN (1<<6) +#define I2S_CONFIG_RN (1<<5) +#define I2S_CONFIG_SZ_BIT 0 +#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) + +#define I2S_CONTROL 0xB1000008 +#define I2S_CONTROL_D (1<<1) +#define I2S_CONTROL_CE (1<<0) + +/* USB Host Controller */ +/* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */ +#define USB_OHCI_BASE 0x10100000 +#define USB_OHCI_LEN 0x00100000 +#define USB_HOST_CONFIG 0xB017fffc + +/* USB Device Controller */ +#define USBD_EP0RD 0xB0200000 +#define USBD_EP0WR 0xB0200004 +#define USBD_EP2WR 0xB0200008 +#define USBD_EP3WR 0xB020000C +#define USBD_EP4RD 0xB0200010 +#define USBD_EP5RD 0xB0200014 +#define USBD_INTEN 0xB0200018 +#define USBD_INTSTAT 0xB020001C +#define USBDEV_INT_SOF (1<<12) +#define USBDEV_INT_HF_BIT 6 +#define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) +#define USBDEV_INT_CMPLT_BIT 0 +#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) +#define USBD_CONFIG 0xB0200020 +#define USBD_EP0CS 0xB0200024 +#define USBD_EP2CS 0xB0200028 +#define USBD_EP3CS 0xB020002C +#define USBD_EP4CS 0xB0200030 +#define USBD_EP5CS 0xB0200034 +#define USBDEV_CS_SU (1<<14) +#define USBDEV_CS_NAK (1<<13) +#define USBDEV_CS_ACK (1<<12) +#define USBDEV_CS_BUSY (1<<11) +#define USBDEV_CS_TSIZE_BIT 1 +#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) +#define USBDEV_CS_STALL (1<<0) +#define USBD_EP0RDSTAT 0xB0200040 +#define USBD_EP0WRSTAT 0xB0200044 +#define USBD_EP2WRSTAT 0xB0200048 +#define USBD_EP3WRSTAT 0xB020004C +#define USBD_EP4RDSTAT 0xB0200050 +#define USBD_EP5RDSTAT 0xB0200054 +#define USBDEV_FSTAT_FLUSH (1<<6) +#define USBDEV_FSTAT_UF (1<<5) +#define USBDEV_FSTAT_OF (1<<4) +#define USBDEV_FSTAT_FCNT_BIT 0 +#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) +#define USBD_ENABLE 0xB0200058 +#define USBDEV_ENABLE (1<<1) +#define USBDEV_CE (1<<0) + +/* Ethernet Controllers */ +#define AU1000_ETH0_BASE 0xB0500000 +#define AU1000_ETH1_BASE 0xB0510000 +#define AU1500_ETH0_BASE 0xB1500000 +#define AU1500_ETH1_BASE 0xB1510000 +#define AU1100_ETH0_BASE 0xB0500000 +#define AU1550_ETH0_BASE 0xB0500000 +#define AU1550_ETH1_BASE 0xB0510000 + +/* 4 byte offsets from AU1000_ETH_BASE */ +#define MAC_CONTROL 0x0 +#define MAC_RX_ENABLE (1<<2) +#define MAC_TX_ENABLE (1<<3) +#define MAC_DEF_CHECK (1<<5) +#define MAC_SET_BL(X) (((X)&0x3)<<6) +#define MAC_AUTO_PAD (1<<8) +#define MAC_DISABLE_RETRY (1<<10) +#define MAC_DISABLE_BCAST (1<<11) +#define MAC_LATE_COL (1<<12) +#define MAC_HASH_MODE (1<<13) +#define MAC_HASH_ONLY (1<<15) +#define MAC_PASS_ALL (1<<16) +#define MAC_INVERSE_FILTER (1<<17) +#define MAC_PROMISCUOUS (1<<18) +#define MAC_PASS_ALL_MULTI (1<<19) +#define MAC_FULL_DUPLEX (1<<20) +#define MAC_NORMAL_MODE 0 +#define MAC_INT_LOOPBACK (1<<21) +#define MAC_EXT_LOOPBACK (1<<22) +#define MAC_DISABLE_RX_OWN (1<<23) +#define MAC_BIG_ENDIAN (1<<30) +#define MAC_RX_ALL (1<<31) +#define MAC_ADDRESS_HIGH 0x4 +#define MAC_ADDRESS_LOW 0x8 +#define MAC_MCAST_HIGH 0xC +#define MAC_MCAST_LOW 0x10 +#define MAC_MII_CNTRL 0x14 +#define MAC_MII_BUSY (1<<0) +#define MAC_MII_READ 0 +#define MAC_MII_WRITE (1<<1) +#define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) +#define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) +#define MAC_MII_DATA 0x18 +#define MAC_FLOW_CNTRL 0x1C +#define MAC_FLOW_CNTRL_BUSY (1<<0) +#define MAC_FLOW_CNTRL_ENABLE (1<<1) +#define MAC_PASS_CONTROL (1<<2) +#define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) +#define MAC_VLAN1_TAG 0x20 +#define MAC_VLAN2_TAG 0x24 + +/* Ethernet Controller Enable */ +#define AU1000_MAC0_ENABLE 0xB0520000 +#define AU1000_MAC1_ENABLE 0xB0520004 +#define AU1500_MAC0_ENABLE 0xB1520000 +#define AU1500_MAC1_ENABLE 0xB1520004 +#define AU1100_MAC0_ENABLE 0xB0520000 +#define AU1550_MAC0_ENABLE 0xB0520000 +#define AU1550_MAC1_ENABLE 0xB0520004 + +#define MAC_EN_CLOCK_ENABLE (1<<0) +#define MAC_EN_RESET0 (1<<1) +#define MAC_EN_TOSS (0<<2) +#define MAC_EN_CACHEABLE (1<<3) +#define MAC_EN_RESET1 (1<<4) +#define MAC_EN_RESET2 (1<<5) +#define MAC_DMA_RESET (1<<6) + +/* Ethernet Controller DMA Channels */ + +#define MAC0_TX_DMA_ADDR 0xB4004000 +#define MAC1_TX_DMA_ADDR 0xB4004200 +/* offsets from MAC_TX_RING_ADDR address */ +#define MAC_TX_BUFF0_STATUS 0x0 +#define TX_FRAME_ABORTED (1<<0) +#define TX_JAB_TIMEOUT (1<<1) +#define TX_NO_CARRIER (1<<2) +#define TX_LOSS_CARRIER (1<<3) +#define TX_EXC_DEF (1<<4) +#define TX_LATE_COLL_ABORT (1<<5) +#define TX_EXC_COLL (1<<6) +#define TX_UNDERRUN (1<<7) +#define TX_DEFERRED (1<<8) +#define TX_LATE_COLL (1<<9) +#define TX_COLL_CNT_MASK (0xF<<10) +#define TX_PKT_RETRY (1<<31) +#define MAC_TX_BUFF0_ADDR 0x4 +#define TX_DMA_ENABLE (1<<0) +#define TX_T_DONE (1<<1) +#define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) +#define MAC_TX_BUFF0_LEN 0x8 +#define MAC_TX_BUFF1_STATUS 0x10 +#define MAC_TX_BUFF1_ADDR 0x14 +#define MAC_TX_BUFF1_LEN 0x18 +#define MAC_TX_BUFF2_STATUS 0x20 +#define MAC_TX_BUFF2_ADDR 0x24 +#define MAC_TX_BUFF2_LEN 0x28 +#define MAC_TX_BUFF3_STATUS 0x30 +#define MAC_TX_BUFF3_ADDR 0x34 +#define MAC_TX_BUFF3_LEN 0x38 + +#define MAC0_RX_DMA_ADDR 0xB4004100 +#define MAC1_RX_DMA_ADDR 0xB4004300 +/* offsets from MAC_RX_RING_ADDR */ +#define MAC_RX_BUFF0_STATUS 0x0 +#define RX_FRAME_LEN_MASK 0x3fff +#define RX_WDOG_TIMER (1<<14) +#define RX_RUNT (1<<15) +#define RX_OVERLEN (1<<16) +#define RX_COLL (1<<17) +#define RX_ETHER (1<<18) +#define RX_MII_ERROR (1<<19) +#define RX_DRIBBLING (1<<20) +#define RX_CRC_ERROR (1<<21) +#define RX_VLAN1 (1<<22) +#define RX_VLAN2 (1<<23) +#define RX_LEN_ERROR (1<<24) +#define RX_CNTRL_FRAME (1<<25) +#define RX_U_CNTRL_FRAME (1<<26) +#define RX_MCAST_FRAME (1<<27) +#define RX_BCAST_FRAME (1<<28) +#define RX_FILTER_FAIL (1<<29) +#define RX_PACKET_FILTER (1<<30) +#define RX_MISSED_FRAME (1<<31) + +#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ + RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ + RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) +#define MAC_RX_BUFF0_ADDR 0x4 +#define RX_DMA_ENABLE (1<<0) +#define RX_T_DONE (1<<1) +#define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) +#define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) +#define MAC_RX_BUFF1_STATUS 0x10 +#define MAC_RX_BUFF1_ADDR 0x14 +#define MAC_RX_BUFF2_STATUS 0x20 +#define MAC_RX_BUFF2_ADDR 0x24 +#define MAC_RX_BUFF3_STATUS 0x30 +#define MAC_RX_BUFF3_ADDR 0x34 + + +/* UARTS 0-3 */ +#define UART0_ADDR 0xB1100000 +#define UART1_ADDR 0xB1200000 +#define UART2_ADDR 0xB1300000 +#define UART3_ADDR 0xB1400000 +#define UART_BASE UART0_ADDR +#define UART_DEBUG_BASE UART2_ADDR + +#define UART_RX 0 /* Receive buffer */ +#define UART_TX 4 /* Transmit buffer */ +#define UART_IER 8 /* Interrupt Enable Register */ +#define UART_IIR 0xC /* Interrupt ID Register */ +#define UART_FCR 0x10 /* FIFO Control Register */ +#define UART_LCR 0x14 /* Line Control Register */ +#define UART_MCR 0x18 /* Modem Control Register */ +#define UART_LSR 0x1C /* Line Status Register */ +#define UART_MSR 0x20 /* Modem Status Register */ +#define UART_CLK 0x28 /* Baud Rate Clock Divider */ +#define UART_ENABLE 0x100 /* Uart enable */ + +#define UART_EN_CE 1 /* Clock enable */ +#define UART_EN_E 2 /* Enable */ + +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ +#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ +#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ +#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ +#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ +#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ +#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ +#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ +#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ + +/* + * These are the definitions for the Line Control Register + */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +/* + * These are the definitions for the Modem Status Register + */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + + +/* SSIO */ +#define SSI0_STATUS 0xB1600000 +#define SSI_STATUS_BF (1<<4) +#define SSI_STATUS_OF (1<<3) +#define SSI_STATUS_UF (1<<2) +#define SSI_STATUS_D (1<<1) +#define SSI_STATUS_B (1<<0) +#define SSI0_INT 0xB1600004 +#define SSI_INT_OI (1<<3) +#define SSI_INT_UI (1<<2) +#define SSI_INT_DI (1<<1) +#define SSI0_INT_ENABLE 0xB1600008 +#define SSI_INTE_OIE (1<<3) +#define SSI_INTE_UIE (1<<2) +#define SSI_INTE_DIE (1<<1) +#define SSI0_CONFIG 0xB1600020 +#define SSI_CONFIG_AO (1<<24) +#define SSI_CONFIG_DO (1<<23) +#define SSI_CONFIG_ALEN_BIT 20 +#define SSI_CONFIG_ALEN_MASK (0x7<<20) +#define SSI_CONFIG_DLEN_BIT 16 +#define SSI_CONFIG_DLEN_MASK (0x7<<16) +#define SSI_CONFIG_DD (1<<11) +#define SSI_CONFIG_AD (1<<10) +#define SSI_CONFIG_BM_BIT 8 +#define SSI_CONFIG_BM_MASK (0x3<<8) +#define SSI_CONFIG_CE (1<<7) +#define SSI_CONFIG_DP (1<<6) +#define SSI_CONFIG_DL (1<<5) +#define SSI_CONFIG_EP (1<<4) +#define SSI0_ADATA 0xB1600024 +#define SSI_AD_D (1<<24) +#define SSI_AD_ADDR_BIT 16 +#define SSI_AD_ADDR_MASK (0xff<<16) +#define SSI_AD_DATA_BIT 0 +#define SSI_AD_DATA_MASK (0xfff<<0) +#define SSI0_CLKDIV 0xB1600028 +#define SSI0_CONTROL 0xB1600100 +#define SSI_CONTROL_CD (1<<1) +#define SSI_CONTROL_E (1<<0) + +/* SSI1 */ +#define SSI1_STATUS 0xB1680000 +#define SSI1_INT 0xB1680004 +#define SSI1_INT_ENABLE 0xB1680008 +#define SSI1_CONFIG 0xB1680020 +#define SSI1_ADATA 0xB1680024 +#define SSI1_CLKDIV 0xB1680028 +#define SSI1_ENABLE 0xB1680100 + +/* + * Register content definitions + */ +#define SSI_STATUS_BF (1<<4) +#define SSI_STATUS_OF (1<<3) +#define SSI_STATUS_UF (1<<2) +#define SSI_STATUS_D (1<<1) +#define SSI_STATUS_B (1<<0) + +/* SSI_INT */ +#define SSI_INT_OI (1<<3) +#define SSI_INT_UI (1<<2) +#define SSI_INT_DI (1<<1) + +/* SSI_INTEN */ +#define SSI_INTEN_OIE (1<<3) +#define SSI_INTEN_UIE (1<<2) +#define SSI_INTEN_DIE (1<<1) + +#define SSI_CONFIG_AO (1<<24) +#define SSI_CONFIG_DO (1<<23) +#define SSI_CONFIG_ALEN (7<<20) +#define SSI_CONFIG_DLEN (15<<16) +#define SSI_CONFIG_DD (1<<11) +#define SSI_CONFIG_AD (1<<10) +#define SSI_CONFIG_BM (3<<8) +#define SSI_CONFIG_CE (1<<7) +#define SSI_CONFIG_DP (1<<6) +#define SSI_CONFIG_DL (1<<5) +#define SSI_CONFIG_EP (1<<4) +#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) +#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) +#define SSI_CONFIG_BM_HI (0<<8) +#define SSI_CONFIG_BM_LO (1<<8) +#define SSI_CONFIG_BM_CY (2<<8) + +#define SSI_ADATA_D (1<<24) +#define SSI_ADATA_ADDR (0xFF<<16) +#define SSI_ADATA_DATA (0x0FFF) +#define SSI_ADATA_ADDR_N(N) (N<<16) + +#define SSI_ENABLE_CD (1<<1) +#define SSI_ENABLE_E (1<<0) + + +/* IrDA Controller */ +#define IRDA_BASE 0xB0300000 +#define IR_RING_PTR_STATUS (IRDA_BASE+0x00) +#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) +#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) +#define IR_RING_SIZE (IRDA_BASE+0x0C) +#define IR_RING_PROMPT (IRDA_BASE+0x10) +#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) +#define IR_INT_CLEAR (IRDA_BASE+0x18) +#define IR_CONFIG_1 (IRDA_BASE+0x20) +#define IR_RX_INVERT_LED (1<<0) +#define IR_TX_INVERT_LED (1<<1) +#define IR_ST (1<<2) +#define IR_SF (1<<3) +#define IR_SIR (1<<4) +#define IR_MIR (1<<5) +#define IR_FIR (1<<6) +#define IR_16CRC (1<<7) +#define IR_TD (1<<8) +#define IR_RX_ALL (1<<9) +#define IR_DMA_ENABLE (1<<10) +#define IR_RX_ENABLE (1<<11) +#define IR_TX_ENABLE (1<<12) +#define IR_LOOPBACK (1<<14) +#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ + IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) +#define IR_SIR_FLAGS (IRDA_BASE+0x24) +#define IR_ENABLE (IRDA_BASE+0x28) +#define IR_RX_STATUS (1<<9) +#define IR_TX_STATUS (1<<10) +#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) +#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) +#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) +#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) +#define IR_CONFIG_2 (IRDA_BASE+0x3C) +#define IR_MODE_INV (1<<0) +#define IR_ONE_PIN (1<<1) +#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) + +/* GPIO */ +#define SYS_PINFUNC 0xB190002C +#define SYS_PF_USB (1<<15) /* 2nd USB device/host */ +#define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ +#define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ +#define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ +#define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ +#define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ +#define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ +#define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ +#define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ +#define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ +#define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ +#define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ +#define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ +#define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ +#define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ +#define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ +#define SYS_TRIOUTRD 0xB1900100 +#define SYS_TRIOUTCLR 0xB1900100 +#define SYS_OUTPUTRD 0xB1900108 +#define SYS_OUTPUTSET 0xB1900108 +#define SYS_OUTPUTCLR 0xB190010C +#define SYS_PINSTATERD 0xB1900110 +#define SYS_PININPUTEN 0xB1900110 + +/* GPIO2, Au1500 only */ +#define GPIO2_BASE 0xB1700000 +#define GPIO2_DIR (GPIO2_BASE + 0) +#define GPIO2_DATA_EN (GPIO2_BASE + 8) +#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC) +#define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10) +#define GPIO2_ENABLE (GPIO2_BASE + 0x14) + +/* Power Management */ +#define SYS_SCRATCH0 0xB1900018 +#define SYS_SCRATCH1 0xB190001C +#define SYS_WAKEMSK 0xB1900034 +#define SYS_ENDIAN 0xB1900038 +#define SYS_POWERCTRL 0xB190003C +#define SYS_WAKESRC 0xB190005C +#define SYS_SLPPWR 0xB1900078 +#define SYS_SLEEP 0xB190007C + +/* Clock Controller */ +#define SYS_FREQCTRL0 0xB1900020 +#define SYS_FC_FRDIV2_BIT 22 +#define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT) +#define SYS_FC_FE2 (1<<21) +#define SYS_FC_FS2 (1<<20) +#define SYS_FC_FRDIV1_BIT 12 +#define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT) +#define SYS_FC_FE1 (1<<11) +#define SYS_FC_FS1 (1<<10) +#define SYS_FC_FRDIV0_BIT 2 +#define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT) +#define SYS_FC_FE0 (1<<1) +#define SYS_FC_FS0 (1<<0) +#define SYS_FREQCTRL1 0xB1900024 +#define SYS_FC_FRDIV5_BIT 22 +#define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT) +#define SYS_FC_FE5 (1<<21) +#define SYS_FC_FS5 (1<<20) +#define SYS_FC_FRDIV4_BIT 12 +#define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT) +#define SYS_FC_FE4 (1<<11) +#define SYS_FC_FS4 (1<<10) +#define SYS_FC_FRDIV3_BIT 2 +#define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT) +#define SYS_FC_FE3 (1<<1) +#define SYS_FC_FS3 (1<<0) +#define SYS_CLKSRC 0xB1900028 +#define SYS_CS_ME1_BIT 27 +#define SYS_CS_ME1_MASK (0x7< +#include /* sigh ... */ + +#ifdef __KERNEL__ + +#include +#include +#include + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +/* + * Only disable interrupt for kernel mode stuff to keep usermode stuff + * that dares to use kernel include files alive. + */ +#define __bi_flags unsigned long flags +#define __bi_cli() __cli() +#define __bi_save_flags(x) __save_flags(x) +#define __bi_save_and_cli(x) __save_and_cli(x) +#define __bi_restore_flags(x) __restore_flags(x) +#else +#define __bi_flags +#define __bi_cli() +#define __bi_save_flags(x) +#define __bi_save_and_cli(x) +#define __bi_restore_flags(x) +#endif /* __KERNEL__ */ + +#ifdef CONFIG_CPU_HAS_LLSC + +#include + +/* + * These functions for MIPS ISA > 1 are interrupt and SMP proof and + * interrupt friendly + */ + +/* + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +extern __inline__ void +set_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp; + + __asm__ __volatile__( + "1:\tll\t%0, %1\t\t# set_bit\n\t" + "or\t%0, %2\n\t" + "sc\t%0, %1\n\t" + "beqz\t%0, 1b" + : "=&r" (temp), "=m" (*m) + : "ir" (1UL << (nr & 0x1f)), "m" (*m)); +} + +/* + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +extern __inline__ void __set_bit(int nr, volatile void * addr) +{ + unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + + *m |= 1UL << (nr & 31); +} + +/* + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +extern __inline__ void +clear_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp; + + __asm__ __volatile__( + "1:\tll\t%0, %1\t\t# clear_bit\n\t" + "and\t%0, %2\n\t" + "sc\t%0, %1\n\t" + "beqz\t%0, 1b\n\t" + : "=&r" (temp), "=m" (*m) + : "ir" (~(1UL << (nr & 0x1f))), "m" (*m)); +} + +/* + * change_bit - Toggle a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +extern __inline__ void +change_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp; + + __asm__ __volatile__( + "1:\tll\t%0, %1\t\t# change_bit\n\t" + "xor\t%0, %2\n\t" + "sc\t%0, %1\n\t" + "beqz\t%0, 1b" + : "=&r" (temp), "=m" (*m) + : "ir" (1UL << (nr & 0x1f)), "m" (*m)); +} + +/* + * __change_bit - Toggle a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +extern __inline__ void __change_bit(int nr, volatile void * addr) +{ + unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + + *m ^= 1UL << (nr & 31); +} + +/* + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int +test_and_set_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp, res; + + __asm__ __volatile__( + ".set\tnoreorder\t\t# test_and_set_bit\n" + "1:\tll\t%0, %1\n\t" + "or\t%2, %0, %3\n\t" + "sc\t%2, %1\n\t" + "beqz\t%2, 1b\n\t" + " and\t%2, %0, %3\n\t" + ".set\treorder" + : "=&r" (temp), "=m" (*m), "=&r" (res) + : "r" (1UL << (nr & 0x1f)), "m" (*m) + : "memory"); + + return res != 0; +} + +/* + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + + return retval; +} + +/* + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int +test_and_clear_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp, res; + + __asm__ __volatile__( + ".set\tnoreorder\t\t# test_and_clear_bit\n" + "1:\tll\t%0, %1\n\t" + "or\t%2, %0, %3\n\t" + "xor\t%2, %3\n\t" + "sc\t%2, %1\n\t" + "beqz\t%2, 1b\n\t" + " and\t%2, %0, %3\n\t" + ".set\treorder" + : "=&r" (temp), "=m" (*m), "=&r" (res) + : "r" (1UL << (nr & 0x1f)), "m" (*m) + : "memory"); + + return res != 0; +} + +/* + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + + return retval; +} + +/* + * test_and_change_bit - Change a bit and return its new value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int +test_and_change_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp, res; + + __asm__ __volatile__( + ".set\tnoreorder\t\t# test_and_change_bit\n" + "1:\tll\t%0, %1\n\t" + "xor\t%2, %0, %3\n\t" + "sc\t%2, %1\n\t" + "beqz\t%2, 1b\n\t" + " and\t%2, %0, %3\n\t" + ".set\treorder" + : "=&r" (temp), "=m" (*m), "=&r" (res) + : "r" (1UL << (nr & 0x1f)), "m" (*m) + : "memory"); + + return res != 0; +} + +/* + * __test_and_change_bit - Change a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + + return retval; +} + +#else /* MIPS I */ + +/* + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +extern __inline__ void set_bit(int nr, volatile void * addr) +{ + int mask; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + *a |= mask; + __bi_restore_flags(flags); +} + +/* + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +extern __inline__ void __set_bit(int nr, volatile void * addr) +{ + int mask; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +/* + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +extern __inline__ void clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + *a &= ~mask; + __bi_restore_flags(flags); +} + +/* + * change_bit - Toggle a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +extern __inline__ void change_bit(int nr, volatile void * addr) +{ + int mask; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + *a ^= mask; + __bi_restore_flags(flags); +} + +/* + * __change_bit - Toggle a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +extern __inline__ void __change_bit(int nr, volatile void * addr) +{ + unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + + *m ^= 1UL << (nr & 31); +} + +/* + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + retval = (mask & *a) != 0; + *a |= mask; + __bi_restore_flags(flags); + + return retval; +} + +/* + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + + return retval; +} + +/* + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + __bi_restore_flags(flags); + + return retval; +} + +/* + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + + return retval; +} + +/* + * test_and_change_bit - Change a bit and return its new value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + retval = (mask & *a) != 0; + *a ^= mask; + __bi_restore_flags(flags); + + return retval; +} + +/* + * __test_and_change_bit - Change a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + + return retval; +} + +#undef __bi_flags +#undef __bi_cli +#undef __bi_save_flags +#undef __bi_restore_flags + +#endif /* MIPS I */ + +/* + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +extern __inline__ int test_bit(int nr, volatile void *addr) +{ + return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0; +} + +#ifndef __MIPSEB__ + +/* Little endian versions. */ + +/* + * find_first_zero_bit - find the first zero bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit-number of the first zero bit, not the number of the byte + * containing a bit. + */ +extern __inline__ int find_first_zero_bit (void *addr, unsigned size) +{ + unsigned long dummy; + int res; + + if (!size) + return 0; + + __asm__ (".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tsubu\t$1,%6,%0\n\t" + "blez\t$1,2f\n\t" + "lw\t$1,(%5)\n\t" + "addiu\t%5,4\n\t" +#if (_MIPS_ISA == _MIPS_ISA_MIPS2 ) || (_MIPS_ISA == _MIPS_ISA_MIPS3 ) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5 ) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) + "beql\t%1,$1,1b\n\t" + "addiu\t%0,32\n\t" +#else + "addiu\t%0,32\n\t" + "beq\t%1,$1,1b\n\t" + "nop\n\t" + "subu\t%0,32\n\t" +#endif +#ifdef __MIPSEB__ +#error "Fix this for big endian" +#endif /* __MIPSEB__ */ + "li\t%1,1\n" + "1:\tand\t%2,$1,%1\n\t" + "beqz\t%2,2f\n\t" + "sll\t%1,%1,1\n\t" + "bnez\t%1,1b\n\t" + "add\t%0,%0,1\n\t" + ".set\tat\n\t" + ".set\treorder\n" + "2:" + : "=r" (res), "=r" (dummy), "=r" (addr) + : "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff), + "2" (addr), "r" (size) + : "$1"); + + return res; +} + +/* + * find_next_zero_bit - find the first zero bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The maximum size to search + */ +extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) +{ + unsigned int *p = ((unsigned int *) addr) + (offset >> 5); + int set = 0, bit = offset & 31, res; + unsigned long dummy; + + if (bit) { + /* + * Look for zero in first byte + */ +#ifdef __MIPSEB__ +#error "Fix this for big endian byte order" +#endif + __asm__(".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tand\t$1,%4,%1\n\t" + "beqz\t$1,1f\n\t" + "sll\t%1,%1,1\n\t" + "bnez\t%1,1b\n\t" + "addiu\t%0,1\n\t" + ".set\tat\n\t" + ".set\treorder\n" + "1:" + : "=r" (set), "=r" (dummy) + : "0" (0), "1" (1 << bit), "r" (*p) + : "$1"); + if (set < (32 - bit)) + return set + offset; + set = 32 - bit; + p++; + } + /* + * No zero yet, search remaining full bytes for a zero + */ + res = find_first_zero_bit(p, size - 32 * (p - (unsigned int *) addr)); + return offset + set + res; +} + +#endif /* !(__MIPSEB__) */ + +/* + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + */ +extern __inline__ unsigned long ffz(unsigned long word) +{ + unsigned int __res; + unsigned int mask = 1; + + __asm__ ( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "move\t%0,$0\n" + "1:\tand\t$1,%2,%1\n\t" + "beqz\t$1,2f\n\t" + "sll\t%1,1\n\t" + "bnez\t%1,1b\n\t" + "addiu\t%0,1\n\t" + ".set\tat\n\t" + ".set\treorder\n" + "2:\n\t" + : "=&r" (__res), "=r" (mask) + : "r" (word), "1" (mask) + : "$1"); + + return __res; +} + +#ifdef __KERNEL__ + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +#define ffs(x) generic_ffs(x) + +/* + * hweightN - returns the hamming weight of a N-bit word + * @x: the word to weigh + * + * The Hamming Weight of a number is the total number of bits set in it. + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#endif /* __KERNEL__ */ + +#ifdef __MIPSEB__ +/* + * find_next_zero_bit - find the first zero bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The maximum size to search + */ +extern __inline__ int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32-offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL << size; +found_middle: + return result + ffz(tmp); +} + +/* Linus sez that gcc can optimize the following correctly, we'll see if this + * holds on the Sparc as it does for the ALPHA. + */ + +#if 0 /* Fool kernel-doc since it doesn't do macros yet */ +/* + * find_first_zero_bit - find the first zero bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit-number of the first zero bit, not the number of the byte + * containing a bit. + */ +extern int find_first_zero_bit (void *addr, unsigned size); +#endif + +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +#endif /* (__MIPSEB__) */ + +/* Now for the ext2 filesystem bit operations and helper routines. */ + +#ifdef __MIPSEB__ +extern __inline__ int ext2_set_bit(int nr, void * addr) +{ + int mask, retval, flags; + unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_and_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR |= mask; + restore_flags(flags); + return retval; +} + +extern __inline__ int ext2_clear_bit(int nr, void * addr) +{ + int mask, retval, flags; + unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_and_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR &= ~mask; + restore_flags(flags); + return retval; +} + +extern __inline__ int ext2_test_bit(int nr, const void * addr) +{ + int mask; + const unsigned char *ADDR = (const unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + return ((mask & *ADDR) != 0); +} + +#define ext2_find_first_zero_bit(addr, size) \ + ext2_find_next_zero_bit((addr), (size), 0) + +extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if(offset) { + /* We hold the little endian value in tmp, but then the + * shift is illegal. So we could keep a big endian value + * in tmp, like this: + * + * tmp = __swab32(*(p++)); + * tmp |= ~0UL >> (32-offset); + * + * but this would decrease preformance, so we change the + * shift: + */ + tmp = *(p++); + tmp |= __swab32(~0UL >> (32-offset)); + if(size < 32) + goto found_first; + if(~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while(size & ~31UL) { + if(~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if(!size) + return result; + tmp = *p; + +found_first: + /* tmp is little endian, so we would have to swab the shift, + * see above. But then we have to swab tmp below for ffz, so + * we might as well do this here. + */ + return result + ffz(__swab32(tmp) | (~0UL << size)); +found_middle: + return result + ffz(__swab32(tmp)); +} +#else /* !(__MIPSEB__) */ + +/* Native ext2 byte ordering, just collapse using defines. */ +#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr)) +#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr)) +#define ext2_test_bit(nr, addr) test_bit((nr), (addr)) +#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size)) +#define ext2_find_next_zero_bit(addr, size, offset) \ + find_next_zero_bit((addr), (size), (offset)) + +#endif /* !(__MIPSEB__) */ + +/* + * Bitmap functions for the minix filesystem. + * FIXME: These assume that Minix uses the native byte/bitorder. + * This limits the Minix filesystem's value for data exchange very much. + */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +#endif /* _ASM_BITOPS_H */ diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h new file mode 100644 index 0000000..b9604cf --- /dev/null +++ b/include/asm-mips/byteorder.h @@ -0,0 +1,31 @@ +/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) by Ralf Baechle + */ +#ifndef _MIPS_BYTEORDER_H +#define _MIPS_BYTEORDER_H + +#include + +#ifdef __GNUC__ + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#endif /* __GNUC__ */ + +#if defined (__MIPSEB__) +# include +#elif defined (__MIPSEL__) +# include +#else +# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" +#endif + +#endif /* _MIPS_BYTEORDER_H */ diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h new file mode 100644 index 0000000..9cc2b87 --- /dev/null +++ b/include/asm-mips/cachectl.h @@ -0,0 +1,24 @@ +/* + * cachectl.h -- defines for MIPS cache control system calls + * + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_CACHECTL +#define __ASM_MIPS_CACHECTL + +/* + * Options for cacheflush system call + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +/* + * Caching modes for the cachectl(2) call + * + * cachectl(2) is currently not supported and returns ENOSYS. + */ +#define CACHEABLE 0 /* make pages cacheable */ +#define UNCACHEABLE 1 /* make pages uncacheable */ + +#endif /* __ASM_MIPS_CACHECTL */ diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h new file mode 100644 index 0000000..66b0b36 --- /dev/null +++ b/include/asm-mips/cacheops.h @@ -0,0 +1,47 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 1997 by Ralf Baechle + */ +#ifndef __ASM_MIPS_CACHEOPS_H +#define __ASM_MIPS_CACHEOPS_H + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 + /* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + /* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b + /* 0x1c is unused */ + /* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +#endif /* __ASM_MIPS_CACHEOPS_H */ diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h new file mode 100644 index 0000000..a024194 --- /dev/null +++ b/include/asm-mips/global_data.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2002-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H + +#include + +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") + +#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-mips/inca-ip.h b/include/asm-mips/inca-ip.h new file mode 100644 index 0000000..e787a1d --- /dev/null +++ b/include/asm-mips/inca-ip.h @@ -0,0 +1,2441 @@ + +/****************************************************************************** + Copyright (c) 2002, Infineon Technologies. All rights reserved. + + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. +******************************************************************************/ + + +/***********************************************************************/ +/* Module : WDT register address and bits */ +/***********************************************************************/ + +#define INCA_IP_WDT (0xB8000000) +/***********************************************************************/ + + +/***Reset Status Register Power On***/ +#define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014)) + +/***Reset Request Register***/ +#define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010)) +#define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24) +#define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16) +#define INCA_IP_WDT_RST_REQ_RRPHY (1 << 5) +#define INCA_IP_WDT_RST_REQ_RRHSP (1 << 4) +#define INCA_IP_WDT_RST_REQ_RRFPI (1 << 3) +#define INCA_IP_WDT_RST_REQ_RREXT (1 << 2) +#define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1) +#define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0) + +/***NMI Status Register***/ +#define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C)) +#define INCA_IP_WDT_NMISR_NMIWDT (1 << 2) +#define INCA_IP_WDT_NMISR_NMIPLL (1 << 1) +#define INCA_IP_WDT_NMISR_NMIEXT (1 << 0) + +/***Manufacturer Identification Register***/ +#define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070)) +#define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5) + +/***Chip Identification Register***/ +#define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074)) +#define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28) +#define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12) +#define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1) + +/***Redesign Tracing Identification Register***/ +#define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078)) +#define INCA_IP_WDT_RTID_LC (1 << 15) +#define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***Watchdog Timer Control Register 0***/ +#define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020)) + +/***Watchdog Timer Control Register 1***/ +#define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024)) +#define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3) +#define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2) + +/***Watchdog Timer Status Register***/ +#define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028)) +#define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16) +#define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5) +#define INCA_IP_WDT_WDT_SR_WDTTO (1 << 4) +#define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3) +#define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2) +#define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1) +#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0) + +/***********************************************************************/ +/* Module : CGU register address and bits */ +/***********************************************************************/ + +#define INCA_IP_CGU (0xBF107000) +/***********************************************************************/ + + +/***CGU PLL1 Control Register***/ +#define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008)) +#define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31) +#define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30) +#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) +#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***CGU PLL0 Control Register***/ +#define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000)) +#define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31) +#define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30) +#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) +#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***CGU PLL0 Status Register***/ +#define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004)) +#define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31) +#define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29) +#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15) + +/***CGU PLL1 Status Register***/ +#define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C)) +#define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31) +#define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29) +#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15) + +/***CGU Divider Control Register***/ +#define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010)) + +/***CGU Multiplexer Control Register***/ +#define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014)) +#define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31) +#define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1) +#define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0) + +/***CGU Fractional Divider Control Register***/ +#define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018)) +#define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31) +#define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16) +#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : PMU register address and bits */ +/***********************************************************************/ + +#define INCA_IP_PMU (0xBF102000) +/***********************************************************************/ + + +/***PM Global Enable Register***/ +#define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000)) +#define INCA_IP_PMU_PM_GEN_EN16 (1 << 16) +#define INCA_IP_PMU_PM_GEN_EN15 (1 << 15) +#define INCA_IP_PMU_PM_GEN_EN14 (1 << 14) +#define INCA_IP_PMU_PM_GEN_EN13 (1 << 13) +#define INCA_IP_PMU_PM_GEN_EN12 (1 << 12) +#define INCA_IP_PMU_PM_GEN_EN11 (1 << 11) +#define INCA_IP_PMU_PM_GEN_EN10 (1 << 10) +#define INCA_IP_PMU_PM_GEN_EN9 (1 << 9) +#define INCA_IP_PMU_PM_GEN_EN8 (1 << 8) +#define INCA_IP_PMU_PM_GEN_EN7 (1 << 7) +#define INCA_IP_PMU_PM_GEN_EN6 (1 << 6) +#define INCA_IP_PMU_PM_GEN_EN5 (1 << 5) +#define INCA_IP_PMU_PM_GEN_EN4 (1 << 4) +#define INCA_IP_PMU_PM_GEN_EN3 (1 << 3) +#define INCA_IP_PMU_PM_GEN_EN2 (1 << 2) +#define INCA_IP_PMU_PM_GEN_EN0 (1 << 0) + +/***PM Power Down Enable Register***/ +#define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008)) +#define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16) +#define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15) +#define INCA_IP_PMU_PM_PDEN_EN14 (1 << 14) +#define INCA_IP_PMU_PM_PDEN_EN13 (1 << 13) +#define INCA_IP_PMU_PM_PDEN_EN12 (1 << 12) +#define INCA_IP_PMU_PM_PDEN_EN11 (1 << 11) +#define INCA_IP_PMU_PM_PDEN_EN10 (1 << 10) +#define INCA_IP_PMU_PM_PDEN_EN9 (1 << 9) +#define INCA_IP_PMU_PM_PDEN_EN8 (1 << 8) +#define INCA_IP_PMU_PM_PDEN_EN7 (1 << 7) +#define INCA_IP_PMU_PM_PDEN_EN5 (1 << 5) +#define INCA_IP_PMU_PM_PDEN_EN4 (1 << 4) +#define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3) +#define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2) +#define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0) + +/***PM Wake-Up from Power Down Register***/ +#define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010)) +#define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16) +#define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15) +#define INCA_IP_PMU_PM_WUP_WUP14 (1 << 14) +#define INCA_IP_PMU_PM_WUP_WUP13 (1 << 13) +#define INCA_IP_PMU_PM_WUP_WUP12 (1 << 12) +#define INCA_IP_PMU_PM_WUP_WUP11 (1 << 11) +#define INCA_IP_PMU_PM_WUP_WUP10 (1 << 10) +#define INCA_IP_PMU_PM_WUP_WUP9 (1 << 9) +#define INCA_IP_PMU_PM_WUP_WUP8 (1 << 8) +#define INCA_IP_PMU_PM_WUP_WUP7 (1 << 7) +#define INCA_IP_PMU_PM_WUP_WUP5 (1 << 5) +#define INCA_IP_PMU_PM_WUP_WUP4 (1 << 4) +#define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3) +#define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2) +#define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0) + +/***PM Control Register***/ +#define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014)) +#define INCA_IP_PMU_PM_CR_AWEN (1 << 31) +#define INCA_IP_PMU_PM_CR_SWRST (1 << 30) +#define INCA_IP_PMU_PM_CR_SWCR (1 << 2) +#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : BCU register address and bits */ +/***********************************************************************/ + +#define INCA_IP_BCU (0xB8000100) +/***********************************************************************/ + + +/***BCU Control Register (0010H)***/ +#define INCA_IP_BCU_BCU_CON ((volatile u32*)(INCA_IP_BCU+ 0x0010)) +#define INCA_IP_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) +#define INCA_IP_BCU_BCU_CON_SPE (1 << 19) +#define INCA_IP_BCU_BCU_CON_PSE (1 << 18) +#define INCA_IP_BCU_BCU_CON_DBG (1 << 16) +#define INCA_IP_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***BCU Error Control Capture Register (0020H)***/ +#define INCA_IP_BCU_BCU_ECON ((volatile u32*)(INCA_IP_BCU+ 0x0020)) +#define INCA_IP_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) +#define INCA_IP_BCU_BCU_ECON_RDN (1 << 23) +#define INCA_IP_BCU_BCU_ECON_WRN (1 << 22) +#define INCA_IP_BCU_BCU_ECON_SVM (1 << 21) +#define INCA_IP_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) +#define INCA_IP_BCU_BCU_ECON_ABT (1 << 18) +#define INCA_IP_BCU_BCU_ECON_RDY (1 << 17) +#define INCA_IP_BCU_BCU_ECON_TOUT (1 << 16) +#define INCA_IP_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) +#define INCA_IP_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) + +/***BCU Error Address Capture Register (0024 H)***/ +#define INCA_IP_BCU_BCU_EADD ((volatile u32*)(INCA_IP_BCU+ 0x0024)) +#define INCA_IP_BCU_BCU_EADD_FPIADR + +/***BCU Error Data Capture Register (0028H)***/ +#define INCA_IP_BCU_BCU_EDAT ((volatile u32*)(INCA_IP_BCU+ 0x0028)) +#define INCA_IP_BCU_BCU_EDAT_FPIDAT + +/***********************************************************************/ +/* Module : MBC register address and bits */ +/***********************************************************************/ + +#define INCA_IP_MBC (0xBF103000) +/***********************************************************************/ + + +/***Mailbox CPU Configuration Register***/ +#define INCA_IP_MBC_MBC_CFG ((volatile u32*)(INCA_IP_MBC+ 0x0080)) +#define INCA_IP_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) +#define INCA_IP_MBC_MBC_CFG_RES (1 << 5) +#define INCA_IP_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) +#define INCA_IP_MBC_MBC_CFG_SIZE (1 << 0) + +/***Mailbox CPU Interrupt Status Register***/ +#define INCA_IP_MBC_MBC_ISR ((volatile u32*)(INCA_IP_MBC+ 0x0084)) +#define INCA_IP_MBC_MBC_ISR_B3DA (1 << 31) +#define INCA_IP_MBC_MBC_ISR_B2DA (1 << 30) +#define INCA_IP_MBC_MBC_ISR_B1E (1 << 29) +#define INCA_IP_MBC_MBC_ISR_B0E (1 << 28) +#define INCA_IP_MBC_MBC_ISR_WDT (1 << 27) +#define INCA_IP_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) + +/***Mailbox CPU Mask Register***/ +#define INCA_IP_MBC_MBC_MSK ((volatile u32*)(INCA_IP_MBC+ 0x0088)) +#define INCA_IP_MBC_MBC_MSK_B3DA (1 << 31) +#define INCA_IP_MBC_MBC_MSK_B2DA (1 << 30) +#define INCA_IP_MBC_MBC_MSK_B1E (1 << 29) +#define INCA_IP_MBC_MBC_MSK_B0E (1 << 28) +#define INCA_IP_MBC_MBC_MSK_WDT (1 << 27) +#define INCA_IP_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) + +/***Mailbox CPU Mask 01 Register***/ +#define INCA_IP_MBC_MBC_MSK01 ((volatile u32*)(INCA_IP_MBC+ 0x008C)) +#define INCA_IP_MBC_MBC_MSK01_B3DA (1 << 31) +#define INCA_IP_MBC_MBC_MSK01_B2DA (1 << 30) +#define INCA_IP_MBC_MBC_MSK01_B1E (1 << 29) +#define INCA_IP_MBC_MBC_MSK01_B0E (1 << 28) +#define INCA_IP_MBC_MBC_MSK01_WDT (1 << 27) +#define INCA_IP_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) + +/***Mailbox CPU Mask 10 Register***/ +#define INCA_IP_MBC_MBC_MSK10 ((volatile u32*)(INCA_IP_MBC+ 0x0090)) +#define INCA_IP_MBC_MBC_MSK10_B3DA (1 << 31) +#define INCA_IP_MBC_MBC_MSK10_B2DA (1 << 30) +#define INCA_IP_MBC_MBC_MSK10_B1E (1 << 29) +#define INCA_IP_MBC_MBC_MSK10_B0E (1 << 28) +#define INCA_IP_MBC_MBC_MSK10_WDT (1 << 27) +#define INCA_IP_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) + +/***Mailbox CPU Short Command Register***/ +#define INCA_IP_MBC_MBC_CMD ((volatile u32*)(INCA_IP_MBC+ 0x0094)) +#define INCA_IP_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) + +/***Mailbox CPU Input Data of Buffer 0***/ +#define INCA_IP_MBC_MBC_ID0 ((volatile u32*)(INCA_IP_MBC+ 0x0000)) +#define INCA_IP_MBC_MBC_ID0_INDATA + +/***Mailbox CPU Input Data of Buffer 1***/ +#define INCA_IP_MBC_MBC_ID1 ((volatile u32*)(INCA_IP_MBC+ 0x0020)) +#define INCA_IP_MBC_MBC_ID1_INDATA + +/***Mailbox CPU Output Data of Buffer 2***/ +#define INCA_IP_MBC_MBC_OD2 ((volatile u32*)(INCA_IP_MBC+ 0x0040)) +#define INCA_IP_MBC_MBC_OD2_OUTDATA + +/***Mailbox CPU Output Data of Buffer 3***/ +#define INCA_IP_MBC_MBC_OD3 ((volatile u32*)(INCA_IP_MBC+ 0x0060)) +#define INCA_IP_MBC_MBC_OD3_OUTDATA + +/***Mailbox CPU Control Register of Buffer 0***/ +#define INCA_IP_MBC_MBC_CR0 ((volatile u32*)(INCA_IP_MBC+ 0x0004)) +#define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***Mailbox CPU Control Register of Buffer 1***/ +#define INCA_IP_MBC_MBC_CR1 ((volatile u32*)(INCA_IP_MBC+ 0x0024)) +#define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***Mailbox CPU Control Register of Buffer 2***/ +#define INCA_IP_MBC_MBC_CR2 ((volatile u32*)(INCA_IP_MBC+ 0x0044)) +#define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***Mailbox CPU Control Register of Buffer 3***/ +#define INCA_IP_MBC_MBC_CR3 ((volatile u32*)(INCA_IP_MBC+ 0x0064)) +#define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***Mailbox CPU Free Space of Buffer 0***/ +#define INCA_IP_MBC_MBC_FS0 ((volatile u32*)(INCA_IP_MBC+ 0x0008)) +#define INCA_IP_MBC_MBC_FS0_FS + +/***Mailbox CPU Free Space of Buffer 1***/ +#define INCA_IP_MBC_MBC_FS1 ((volatile u32*)(INCA_IP_MBC+ 0x0028)) +#define INCA_IP_MBC_MBC_FS1_FS + +/***Mailbox CPU Free Space of Buffer 2***/ +#define INCA_IP_MBC_MBC_FS2 ((volatile u32*)(INCA_IP_MBC+ 0x0048)) +#define INCA_IP_MBC_MBC_FS2_FS + +/***Mailbox CPU Free Space of Buffer 3***/ +#define INCA_IP_MBC_MBC_FS3 ((volatile u32*)(INCA_IP_MBC+ 0x0068)) +#define INCA_IP_MBC_MBC_FS3_FS + +/***Mailbox CPU Data Available in Buffer 0***/ +#define INCA_IP_MBC_MBC_DA0 ((volatile u32*)(INCA_IP_MBC+ 0x000C)) +#define INCA_IP_MBC_MBC_DA0_DA + +/***Mailbox CPU Data Available in Buffer 1***/ +#define INCA_IP_MBC_MBC_DA1 ((volatile u32*)(INCA_IP_MBC+ 0x002C)) +#define INCA_IP_MBC_MBC_DA1_DA + +/***Mailbox CPU Data Available in Buffer 2***/ +#define INCA_IP_MBC_MBC_DA2 ((volatile u32*)(INCA_IP_MBC+ 0x004C)) +#define INCA_IP_MBC_MBC_DA2_DA + +/***Mailbox CPU Data Available in Buffer 3***/ +#define INCA_IP_MBC_MBC_DA3 ((volatile u32*)(INCA_IP_MBC+ 0x006C)) +#define INCA_IP_MBC_MBC_DA3_DA + +/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ +#define INCA_IP_MBC_MBC_IABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0010)) +#define INCA_IP_MBC_MBC_IABS0_IABS + +/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ +#define INCA_IP_MBC_MBC_IABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0030)) +#define INCA_IP_MBC_MBC_IABS1_IABS + +/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ +#define INCA_IP_MBC_MBC_IABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0050)) +#define INCA_IP_MBC_MBC_IABS2_IABS + +/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ +#define INCA_IP_MBC_MBC_IABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0070)) +#define INCA_IP_MBC_MBC_IABS3_IABS + +/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ +#define INCA_IP_MBC_MBC_ITMP0 ((volatile u32*)(INCA_IP_MBC+ 0x0014)) +#define INCA_IP_MBC_MBC_ITMP0_ITMP + +/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ +#define INCA_IP_MBC_MBC_ITMP1 ((volatile u32*)(INCA_IP_MBC+ 0x0034)) +#define INCA_IP_MBC_MBC_ITMP1_ITMP + +/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ +#define INCA_IP_MBC_MBC_ITMP2 ((volatile u32*)(INCA_IP_MBC+ 0x0054)) +#define INCA_IP_MBC_MBC_ITMP2_ITMP + +/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ +#define INCA_IP_MBC_MBC_ITMP3 ((volatile u32*)(INCA_IP_MBC+ 0x0074)) +#define INCA_IP_MBC_MBC_ITMP3_ITMP + +/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ +#define INCA_IP_MBC_MBC_OABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0018)) +#define INCA_IP_MBC_MBC_OABS0_OABS + +/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ +#define INCA_IP_MBC_MBC_OABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0038)) +#define INCA_IP_MBC_MBC_OABS1_OABS + +/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ +#define INCA_IP_MBC_MBC_OABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0058)) +#define INCA_IP_MBC_MBC_OABS2_OABS + +/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ +#define INCA_IP_MBC_MBC_OABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0078)) +#define INCA_IP_MBC_MBC_OABS3_OABS + +/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ +#define INCA_IP_MBC_MBC_OTMP0 ((volatile u32*)(INCA_IP_MBC+ 0x001C)) +#define INCA_IP_MBC_MBC_OTMP0_OTMP + +/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ +#define INCA_IP_MBC_MBC_OTMP1 ((volatile u32*)(INCA_IP_MBC+ 0x003C)) +#define INCA_IP_MBC_MBC_OTMP1_OTMP + +/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ +#define INCA_IP_MBC_MBC_OTMP2 ((volatile u32*)(INCA_IP_MBC+ 0x005C)) +#define INCA_IP_MBC_MBC_OTMP2_OTMP + +/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ +#define INCA_IP_MBC_MBC_OTMP3 ((volatile u32*)(INCA_IP_MBC+ 0x007C)) +#define INCA_IP_MBC_MBC_OTMP3_OTMP + +/***DSP Control Register***/ +#define INCA_IP_MBC_DCTRL ((volatile u32*)(INCA_IP_MBC+ 0x00A0)) +#define INCA_IP_MBC_DCTRL_BA (1 << 0) +#define INCA_IP_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) +#define INCA_IP_MBC_DCTRL_IDL (1 << 4) +#define INCA_IP_MBC_DCTRL_RES (1 << 15) + +/***DSP Status Register***/ +#define INCA_IP_MBC_DSTA ((volatile u32*)(INCA_IP_MBC+ 0x00A4)) +#define INCA_IP_MBC_DSTA_IDLE (1 << 0) +#define INCA_IP_MBC_DSTA_PD (1 << 1) + +/***DSP Test 1 Register***/ +#define INCA_IP_MBC_DTST1 ((volatile u32*)(INCA_IP_MBC+ 0x00A8)) +#define INCA_IP_MBC_DTST1_ABORT (1 << 0) +#define INCA_IP_MBC_DTST1_HWF32 (1 << 1) +#define INCA_IP_MBC_DTST1_HWF4M (1 << 2) +#define INCA_IP_MBC_DTST1_HWFOP (1 << 3) + +/***********************************************************************/ +/* Module : Switch register address and bits */ +/***********************************************************************/ + +#define INCA_IP_Switch (0xBF104000) +/***********************************************************************/ + + +/***Unknown Destination Register***/ +#define INCA_IP_Switch_UN_DEST ((volatile u32*)(INCA_IP_Switch+ 0x0000)) +#define INCA_IP_Switch_UN_DEST_CB (1 << 8) +#define INCA_IP_Switch_UN_DEST_LB (1 << 7) +#define INCA_IP_Switch_UN_DEST_PB (1 << 6) +#define INCA_IP_Switch_UN_DEST_CM (1 << 5) +#define INCA_IP_Switch_UN_DEST_LM (1 << 4) +#define INCA_IP_Switch_UN_DEST_PM (1 << 3) +#define INCA_IP_Switch_UN_DEST_CU (1 << 2) +#define INCA_IP_Switch_UN_DEST_LU (1 << 1) +#define INCA_IP_Switch_UN_DEST_PU (1 << 0) + +/***VLAN Control Register***/ +#define INCA_IP_Switch_VLAN_CTRL ((volatile u32*)(INCA_IP_Switch+ 0x0004)) +#define INCA_IP_Switch_VLAN_CTRL_SC (1 << 6) +#define INCA_IP_Switch_VLAN_CTRL_SL (1 << 5) +#define INCA_IP_Switch_VLAN_CTRL_SP (1 << 4) +#define INCA_IP_Switch_VLAN_CTRL_TC (1 << 3) +#define INCA_IP_Switch_VLAN_CTRL_TL (1 << 2) +#define INCA_IP_Switch_VLAN_CTRL_TP (1 << 1) +#define INCA_IP_Switch_VLAN_CTRL_VA (1 << 0) + +/***PC VLAN Configuration Register***/ +#define INCA_IP_Switch_PC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0008)) +#define INCA_IP_Switch_PC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) +#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) + +/***LAN VLAN Configuration Register***/ +#define INCA_IP_Switch_LAN_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x000C)) +#define INCA_IP_Switch_LAN_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) +#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) + +/***CPU VLAN Configuration Register***/ +#define INCA_IP_Switch_CPU_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0010)) +#define INCA_IP_Switch_CPU_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) +#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) + +/***Priority CoS Mapping Register***/ +#define INCA_IP_Switch_PRI_CoS ((volatile u32*)(INCA_IP_Switch+ 0x0014)) +#define INCA_IP_Switch_PRI_CoS_P7 (1 << 7) +#define INCA_IP_Switch_PRI_CoS_P6 (1 << 6) +#define INCA_IP_Switch_PRI_CoS_P5 (1 << 5) +#define INCA_IP_Switch_PRI_CoS_P4 (1 << 4) +#define INCA_IP_Switch_PRI_CoS_P3 (1 << 3) +#define INCA_IP_Switch_PRI_CoS_P2 (1 << 2) +#define INCA_IP_Switch_PRI_CoS_P1 (1 << 1) +#define INCA_IP_Switch_PRI_CoS_P0 (1 << 0) + +/***Spanning Tree Port Status Register***/ +#define INCA_IP_Switch_ST_PT ((volatile u32*)(INCA_IP_Switch+ 0x0018)) +#define INCA_IP_Switch_ST_PT_CPS (value) (((( 1 << 2) - 1) & (value)) << 4) +#define INCA_IP_Switch_ST_PT_LPS (value) (((( 1 << 2) - 1) & (value)) << 2) +#define INCA_IP_Switch_ST_PT_PPS (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***ARL Control Register***/ +#define INCA_IP_Switch_ARL_CTL ((volatile u32*)(INCA_IP_Switch+ 0x001C)) +#define INCA_IP_Switch_ARL_CTL_CHCC (1 << 15) +#define INCA_IP_Switch_ARL_CTL_CHCL (1 << 14) +#define INCA_IP_Switch_ARL_CTL_CHCP (1 << 13) +#define INCA_IP_Switch_ARL_CTL_CC (1 << 12) +#define INCA_IP_Switch_ARL_CTL_CL (1 << 11) +#define INCA_IP_Switch_ARL_CTL_CP (1 << 10) +#define INCA_IP_Switch_ARL_CTL_CG (1 << 9) +#define INCA_IP_Switch_ARL_CTL_PS (1 << 8) +#define INCA_IP_Switch_ARL_CTL_MRO (1 << 7) +#define INCA_IP_Switch_ARL_CTL_SRC (1 << 6) +#define INCA_IP_Switch_ARL_CTL_ATS (1 << 5) +#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value) (((( 1 << 3) - 1) & (value)) << 2) +#define INCA_IP_Switch_ARL_CTL_MAF (1 << 1) +#define INCA_IP_Switch_ARL_CTL_ENL (1 << 0) +#define INCA_IP_Switch_ARL_CTL_Res (value) (((( 1 << 19) - 1) & (value)) << 13) + +/***CPU Access Control Register***/ +#define INCA_IP_Switch_CPU_ACTL ((volatile u32*)(INCA_IP_Switch+ 0x0020)) +#define INCA_IP_Switch_CPU_ACTL_RA (1 << 31) +#define INCA_IP_Switch_CPU_ACTL_RW (1 << 30) +#define INCA_IP_Switch_CPU_ACTL_Res (value) (((( 1 << 21) - 1) & (value)) << 9) +#define INCA_IP_Switch_CPU_ACTL_AVA (1 << 8) +#define INCA_IP_Switch_CPU_ACTL_IDX (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***CPU Access Data Register 1***/ +#define INCA_IP_Switch_DATA1 ((volatile u32*)(INCA_IP_Switch+ 0x0024)) +#define INCA_IP_Switch_DATA1_Data (value) (((( 1 << 24) - 1) & (value)) << 0) + +/***CPU Access Data Register 2***/ +#define INCA_IP_Switch_DATA2 ((volatile u32*)(INCA_IP_Switch+ 0x0028)) +#define INCA_IP_Switch_DATA2_Data + +/***CPU Port Control Register***/ +#define INCA_IP_Switch_CPU_PCTL ((volatile u32*)(INCA_IP_Switch+ 0x002C)) +#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value) (((( 1 << 3) - 1) & (value)) << 11) +#define INCA_IP_Switch_CPU_PCTL_DAC (1 << 10) +#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value) (((( 1 << 3) - 1) & (value)) << 7) +#define INCA_IP_Switch_CPU_PCTL_MAM (1 << 6) +#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value) (((( 1 << 3) - 1) & (value)) << 3) +#define INCA_IP_Switch_CPU_PCTL_MAC (1 << 2) +#define INCA_IP_Switch_CPU_PCTL_EML (1 << 1) +#define INCA_IP_Switch_CPU_PCTL_EDL (1 << 0) +#define INCA_IP_Switch_CPU_PCTL_Res (value) (((( 1 << 18) - 1) & (value)) << 14) + +/***DSCP CoS Mapping Register 1***/ +#define INCA_IP_Switch_DSCP_COS1 ((volatile u32*)(INCA_IP_Switch+ 0x0030)) +#define INCA_IP_Switch_DSCP_COS1_DSCP + +/***DSCP CoS Mapping Register 1***/ +#define INCA_IP_Switch_DSCP_COS2 ((volatile u32*)(INCA_IP_Switch+ 0x0034)) +#define INCA_IP_Switch_DSCP_COS2_DSCP + +/***PC WFQ Control Register***/ +#define INCA_IP_Switch_PC_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0080)) +#define INCA_IP_Switch_PC_WFQ_CTL_P1 (1 << 9) +#define INCA_IP_Switch_PC_WFQ_CTL_P0 (1 << 8) +#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) +#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) +#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***PC TX Control Register***/ +#define INCA_IP_Switch_PC_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0084)) +#define INCA_IP_Switch_PC_TX_CTL_ELR (1 << 1) +#define INCA_IP_Switch_PC_TX_CTL_EER (1 << 0) + +/***LAN WFQ Control Register***/ +#define INCA_IP_Switch_LAN_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0100)) +#define INCA_IP_Switch_LAN_WFQ_CTL_P1 (1 << 9) +#define INCA_IP_Switch_LAN_WFQ_CTL_P0 (1 << 8) +#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) +#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) +#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***LAN TX Control Register***/ +#define INCA_IP_Switch_LAN_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0104)) +#define INCA_IP_Switch_LAN_TX_CTL_ELR (1 << 1) +#define INCA_IP_Switch_LAN_TX_CTL_EER (1 << 0) + +/***CPU WFQ Control Register***/ +#define INCA_IP_Switch_CPU_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0180)) +#define INCA_IP_Switch_CPU_WFQ_CTL_P1 (1 << 9) +#define INCA_IP_Switch_CPU_WFQ_CTL_P0 (1 << 8) +#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) +#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) +#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***PM PC RX Watermark Register***/ +#define INCA_IP_Switch_PC_WM ((volatile u32*)(INCA_IP_Switch+ 0x0200)) +#define INCA_IP_Switch_PC_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) +#define INCA_IP_Switch_PC_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) +#define INCA_IP_Switch_PC_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_Switch_PC_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***PM LAN RX Watermark Register***/ +#define INCA_IP_Switch_LAN_WM ((volatile u32*)(INCA_IP_Switch+ 0x0204)) +#define INCA_IP_Switch_LAN_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) +#define INCA_IP_Switch_LAN_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) +#define INCA_IP_Switch_LAN_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_Switch_LAN_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***PM CPU RX Watermark Register***/ +#define INCA_IP_Switch_CPU_WM ((volatile u32*)(INCA_IP_Switch+ 0x0208)) +#define INCA_IP_Switch_CPU_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) +#define INCA_IP_Switch_CPU_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) +#define INCA_IP_Switch_CPU_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_Switch_CPU_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***PM CPU RX Watermark Register***/ +#define INCA_IP_Switch_GBL_WM ((volatile u32*)(INCA_IP_Switch+ 0x020C)) +#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) +#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) +#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***PM Control Register***/ +#define INCA_IP_Switch_PM_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0210)) +#define INCA_IP_Switch_PM_CTL_GDN (1 << 3) +#define INCA_IP_Switch_PM_CTL_CDN (1 << 2) +#define INCA_IP_Switch_PM_CTL_LDN (1 << 1) +#define INCA_IP_Switch_PM_CTL_PDN (1 << 0) + +/***PM Header Control Register***/ +#define INCA_IP_Switch_PMAC_HD_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0280)) +#define INCA_IP_Switch_PMAC_HD_CTL_RL2 (1 << 21) +#define INCA_IP_Switch_PMAC_HD_CTL_RC (1 << 20) +#define INCA_IP_Switch_PMAC_HD_CTL_CM (1 << 19) +#define INCA_IP_Switch_PMAC_HD_CTL_CV (1 << 18) +#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value) (((( 1 << 16) - 1) & (value)) << 2) +#define INCA_IP_Switch_PMAC_HD_CTL_TAG (1 << 1) +#define INCA_IP_Switch_PMAC_HD_CTL_ADD (1 << 0) + +/***PM Source Address Register 1***/ +#define INCA_IP_Switch_PMAC_SA1 ((volatile u32*)(INCA_IP_Switch+ 0x0284)) +#define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***PM Source Address Register 2***/ +#define INCA_IP_Switch_PMAC_SA2 ((volatile u32*)(INCA_IP_Switch+ 0x0288)) +#define INCA_IP_Switch_PMAC_SA2_SA_31_0 + +/***PM Dest Address Register 1***/ +#define INCA_IP_Switch_PMAC_DA1 ((volatile u32*)(INCA_IP_Switch+ 0x028C)) +#define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***PM Dest Address Register 2***/ +#define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290)) +#define INCA_IP_Switch_PMAC_DA2_DA_31_0 + +/***PM VLAN Register***/ +#define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294)) +#define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13) +#define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12) +#define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0) + +/***PM TX IPG Counter Register***/ +#define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298)) +#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***PM RX IPG Counter Register***/ +#define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C)) +#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Mirror Register***/ +#define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300)) +#define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6) +#define INCA_IP_Switch_MRR_EC (1 << 5) +#define INCA_IP_Switch_MRR_EL (1 << 4) +#define INCA_IP_Switch_MRR_EP (1 << 3) +#define INCA_IP_Switch_MRR_IC (1 << 2) +#define INCA_IP_Switch_MRR_IL (1 << 1) +#define INCA_IP_Switch_MRR_IP (1 << 0) + +/***Packet Length Register***/ +#define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304)) +#define INCA_IP_Switch_PKT_LEN_ADD (1 << 11) +#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0) + +/***MDIO Access Register***/ +#define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480)) +#define INCA_IP_Switch_MDIO_ACC_RA (1 << 31) +#define INCA_IP_Switch_MDIO_ACC_RW (1 << 30) +#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21) +#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16) +#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***Ethernet PHY Register***/ +#define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484)) +#define INCA_IP_Switch_EPHY_SL (1 << 7) +#define INCA_IP_Switch_EPHY_SP (1 << 6) +#define INCA_IP_Switch_EPHY_LL (1 << 5) +#define INCA_IP_Switch_EPHY_LP (1 << 4) +#define INCA_IP_Switch_EPHY_DL (1 << 3) +#define INCA_IP_Switch_EPHY_DP (1 << 2) +#define INCA_IP_Switch_EPHY_PL (1 << 1) +#define INCA_IP_Switch_EPHY_PP (1 << 0) + +/***Pause Write Enable Register***/ +#define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488)) +#define INCA_IP_Switch_PWR_EN_PL (1 << 1) +#define INCA_IP_Switch_PWR_EN_PP (1 << 0) + +/***MDIO Configuration Register***/ +#define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C)) +#define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14) +#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9) +#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4) +#define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3) +#define INCA_IP_Switch_MDIO_CFG_PS (1 << 2) +#define INCA_IP_Switch_MDIO_CFG_PT (1 << 1) +#define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0) + +/***Clock Configuration Register***/ +#define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500)) +#define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9) +#define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8) +#define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7) +#define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6) +#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5) + +/***********************************************************************/ +/* Module : SSC1 register address and bits */ +/***********************************************************************/ + +#define INCA_IP_SSC1 (0xB8000500) +/***********************************************************************/ + + +/***Control Register (Programming Mode)***/ +#define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) +#define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15) +#define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14) +#define INCA_IP_SSC1_SCC_CON_PRG_AREN (1 << 12) +#define INCA_IP_SSC1_SCC_CON_PRG_BEN (1 << 11) +#define INCA_IP_SSC1_SCC_CON_PRG_PEN (1 << 10) +#define INCA_IP_SSC1_SCC_CON_PRG_REN (1 << 9) +#define INCA_IP_SSC1_SCC_CON_PRG_TEN (1 << 8) +#define INCA_IP_SSC1_SCC_CON_PRG_LB (1 << 7) +#define INCA_IP_SSC1_SCC_CON_PRG_PO (1 << 6) +#define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5) +#define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4) +#define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***SCC Control Register (Operating Mode)***/ +#define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) +#define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15) +#define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14) +#define INCA_IP_SSC1_SCC_CON_OPR_BSY (1 << 12) +#define INCA_IP_SSC1_SCC_CON_OPR_BE (1 << 11) +#define INCA_IP_SSC1_SCC_CON_OPR_PE (1 << 10) +#define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9) +#define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8) +#define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***SSC Write Hardware Modified Control Register***/ +#define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040)) +#define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15) +#define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14) +#define INCA_IP_SSC1_SSC_WHBCON_SETRE (1 << 13) +#define INCA_IP_SSC1_SSC_WHBCON_SETTE (1 << 12) +#define INCA_IP_SSC1_SSC_WHBCON_CLRBE (1 << 11) +#define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10) +#define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9) +#define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8) + +/***SSC Baudrate Timer Reload Register***/ +#define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014)) +#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***SSC Transmitter Buffer Register***/ +#define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020)) +#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***SSC Receiver Buffer Register***/ +#define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024)) +#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***SSC Receive FIFO Control Register***/ +#define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030)) +#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) +#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2) +#define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1) +#define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0) + +/***SSC Transmit FIFO Control Register***/ +#define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034)) +#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) +#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2) +#define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1) +#define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0) + +/***SSC FIFO Status Register***/ +#define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038)) +#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) +#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) + +/***SSC Clock Control Register***/ +#define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000)) +#define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1) +#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0) + +/***********************************************************************/ +/* Module : SSC2 register address and bits */ +/***********************************************************************/ + +#define INCA_IP_SSC2 (0xB8000600) +/***********************************************************************/ + + +/***Control Register (Programming Mode)***/ +#define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) +#define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15) +#define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14) +#define INCA_IP_SSC2_SCC_CON_PRG_AREN (1 << 12) +#define INCA_IP_SSC2_SCC_CON_PRG_BEN (1 << 11) +#define INCA_IP_SSC2_SCC_CON_PRG_PEN (1 << 10) +#define INCA_IP_SSC2_SCC_CON_PRG_REN (1 << 9) +#define INCA_IP_SSC2_SCC_CON_PRG_TEN (1 << 8) +#define INCA_IP_SSC2_SCC_CON_PRG_LB (1 << 7) +#define INCA_IP_SSC2_SCC_CON_PRG_PO (1 << 6) +#define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5) +#define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4) +#define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***SCC Control Register (Operating Mode)***/ +#define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) +#define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15) +#define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14) +#define INCA_IP_SSC2_SCC_CON_OPR_BSY (1 << 12) +#define INCA_IP_SSC2_SCC_CON_OPR_BE (1 << 11) +#define INCA_IP_SSC2_SCC_CON_OPR_PE (1 << 10) +#define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9) +#define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8) +#define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***SSC Write Hardware Modified Control Register***/ +#define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040)) +#define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15) +#define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14) +#define INCA_IP_SSC2_SSC_WHBCON_SETRE (1 << 13) +#define INCA_IP_SSC2_SSC_WHBCON_SETTE (1 << 12) +#define INCA_IP_SSC2_SSC_WHBCON_CLRBE (1 << 11) +#define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10) +#define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9) +#define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8) + +/***SSC Baudrate Timer Reload Register***/ +#define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014)) +#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***SSC Transmitter Buffer Register***/ +#define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020)) +#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***SSC Receiver Buffer Register***/ +#define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024)) +#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***SSC Receive FIFO Control Register***/ +#define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030)) +#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) +#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2) +#define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1) +#define INCA_IP_SSC2_SSC_RXFCON_RXFEN (1 << 0) + +/***SSC Transmit FIFO Control Register***/ +#define INCA_IP_SSC2_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0034)) +#define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) +#define INCA_IP_SSC2_SSC_TXFCON_TXTMEN (1 << 2) +#define INCA_IP_SSC2_SSC_TXFCON_TXFLU (1 << 1) +#define INCA_IP_SSC2_SSC_TXFCON_TXFEN (1 << 0) + +/***SSC FIFO Status Register***/ +#define INCA_IP_SSC2_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC2+ 0x0038)) +#define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) +#define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) + +/***SSC Clock Control Register***/ +#define INCA_IP_SSC2_SSC_CLC ((volatile u32*)(INCA_IP_SSC2+ 0x0000)) +#define INCA_IP_SSC2_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_SSC2_SSC_CLC_DISS (1 << 1) +#define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0) + +/***********************************************************************/ +/* Module : EBU register address and bits */ +/***********************************************************************/ + +#if defined(CONFIG_INCA_IP) +#define INCA_IP_EBU (0xB8000200) +#elif defined(CONFIG_PURPLE) +#define INCA_IP_EBU (0xB800D800) +#endif + +/***********************************************************************/ + + +/***EBU Clock Control Register***/ +#define INCA_IP_EBU_EBU_CLC ((volatile u32*)(INCA_IP_EBU+ 0x0000)) +#define INCA_IP_EBU_EBU_CLC_DISS (1 << 1) +#define INCA_IP_EBU_EBU_CLC_DISR (1 << 0) + +/***EBU Global Control Register***/ +#define INCA_IP_EBU_EBU_CON ((volatile u32*)(INCA_IP_EBU+ 0x0010)) +#define INCA_IP_EBU_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) +#define INCA_IP_EBU_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) +#define INCA_IP_EBU_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_EBU_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) +#define INCA_IP_EBU_EBU_CON_ARBSYNC (1 << 5) +#define INCA_IP_EBU_EBU_CON_1 (1 << 3) + +/***EBU Address Select Register 0***/ +#define INCA_IP_EBU_EBU_ADDSEL0 ((volatile u32*)(INCA_IP_EBU+ 0x0020)) +#define INCA_IP_EBU_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) +#define INCA_IP_EBU_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) +#define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE (1 << 1) +#define INCA_IP_EBU_EBU_ADDSEL0_REGEN (1 << 0) + +/***EBU Address Select Register 1***/ +#define INCA_IP_EBU_EBU_ADDSEL1 ((volatile u32*)(INCA_IP_EBU+ 0x0024)) +#define INCA_IP_EBU_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) +#define INCA_IP_EBU_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) +#define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE (1 << 1) +#define INCA_IP_EBU_EBU_ADDSEL1_REGEN (1 << 0) + +/***EBU Address Select Register 2***/ +#define INCA_IP_EBU_EBU_ADDSEL2 ((volatile u32*)(INCA_IP_EBU+ 0x0028)) +#define INCA_IP_EBU_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) +#define INCA_IP_EBU_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) +#define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE (1 << 1) +#define INCA_IP_EBU_EBU_ADDSEL2_REGEN (1 << 0) + +/***EBU Bus Configuration Register 0***/ +#define INCA_IP_EBU_EBU_BUSCON0 ((volatile u32*)(INCA_IP_EBU+ 0x0060)) +#define INCA_IP_EBU_EBU_BUSCON0_WRDIS (1 << 31) +#define INCA_IP_EBU_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) +#define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) +#define INCA_IP_EBU_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) +#define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) +#define INCA_IP_EBU_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) +#define INCA_IP_EBU_EBU_BUSCON0_WAITINV (1 << 19) +#define INCA_IP_EBU_EBU_BUSCON0_SETUP (1 << 18) +#define INCA_IP_EBU_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) +#define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) +#define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) +#define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) +#define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) +#define INCA_IP_EBU_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***EBU Bus Configuration Register 1***/ +#define INCA_IP_EBU_EBU_BUSCON1 ((volatile u32*)(INCA_IP_EBU+ 0x0064)) +#define INCA_IP_EBU_EBU_BUSCON1_WRDIS (1 << 31) +#define INCA_IP_EBU_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) +#define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) +#define INCA_IP_EBU_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) +#define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) +#define INCA_IP_EBU_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) +#define INCA_IP_EBU_EBU_BUSCON1_WAITINV (1 << 19) +#define INCA_IP_EBU_EBU_BUSCON1_SETUP (1 << 18) +#define INCA_IP_EBU_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) +#define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) +#define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) +#define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) +#define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) +#define INCA_IP_EBU_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***EBU Bus Configuration Register 2***/ +#define INCA_IP_EBU_EBU_BUSCON2 ((volatile u32*)(INCA_IP_EBU+ 0x0068)) +#define INCA_IP_EBU_EBU_BUSCON2_WRDIS (1 << 31) +#define INCA_IP_EBU_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) +#define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) +#define INCA_IP_EBU_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) +#define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) +#define INCA_IP_EBU_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) +#define INCA_IP_EBU_EBU_BUSCON2_WAITINV (1 << 19) +#define INCA_IP_EBU_EBU_BUSCON2_SETUP (1 << 18) +#define INCA_IP_EBU_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) +#define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) +#define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) +#define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) +#define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) +#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : SDRAM register address and bits */ +/***********************************************************************/ + +#define INCA_IP_SDRAM (0xBF800000) +/***********************************************************************/ + + +/***MC Access Error Cause Register***/ +#define INCA_IP_SDRAM_MC_ERRCAUSE ((volatile u32*)(INCA_IP_SDRAM+ 0x0100)) +#define INCA_IP_SDRAM_MC_ERRCAUSE_ERR (1 << 31) +#define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) +#define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) +#define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) + +/***MC Access Error Address Register***/ +#define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108)) +#define INCA_IP_SDRAM_MC_ERRADDR_ADDR + +/***MC I/O General Purpose Register***/ +#define INCA_IP_SDRAM_MC_IOGP ((volatile u32*)(INCA_IP_SDRAM+ 0x0800)) +#define INCA_IP_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) +#define INCA_IP_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) +#define INCA_IP_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) +#define INCA_IP_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) +#define INCA_IP_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) +#define INCA_IP_SDRAM_MC_IOGP_CPS (1 << 11) +#define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) +#define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) +#define INCA_IP_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***MC Self Refresh Register***/ +#define INCA_IP_SDRAM_MC_SELFRFSH ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00)) +#define INCA_IP_SDRAM_MC_SELFRFSH_PWDS (1 << 1) +#define INCA_IP_SDRAM_MC_SELFRFSH_PWD (1 << 0) +#define INCA_IP_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) + +/***MC Enable Register***/ +#define INCA_IP_SDRAM_MC_CTRLENA ((volatile u32*)(INCA_IP_SDRAM+ 0x1000)) +#define INCA_IP_SDRAM_MC_CTRLENA_ENA (1 << 0) +#define INCA_IP_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) + +/***MC Mode Register Setup Code***/ +#define INCA_IP_SDRAM_MC_MRSCODE ((volatile u32*)(INCA_IP_SDRAM+ 0x1008)) +#define INCA_IP_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) +#define INCA_IP_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) +#define INCA_IP_SDRAM_MC_MRSCODE_WT (1 << 3) +#define INCA_IP_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***MC Configuration Data-word Width Register***/ +#define INCA_IP_SDRAM_MC_CFGDW ((volatile u32*)(INCA_IP_SDRAM+ 0x1010)) +#define INCA_IP_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) +#define INCA_IP_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) + +/***MC Configuration Physical Bank 0 Register***/ +#define INCA_IP_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP_SDRAM+ 0x1018)) +#define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) +#define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) +#define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) +#define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) +#define INCA_IP_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) + +/***MC Latency Register***/ +#define INCA_IP_SDRAM_MC_LATENCY ((volatile u32*)(INCA_IP_SDRAM+ 0x1038)) +#define INCA_IP_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) +#define INCA_IP_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) +#define INCA_IP_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) +#define INCA_IP_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) +#define INCA_IP_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) +#define INCA_IP_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) + +/***MC Refresh Cycle Time Register***/ +#define INCA_IP_SDRAM_MC_TREFRESH ((volatile u32*)(INCA_IP_SDRAM+ 0x1040)) +#define INCA_IP_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) +#define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) + +/***********************************************************************/ +/* Module : GPTU register address and bits */ +/***********************************************************************/ + +#define INCA_IP_GPTU (0xB8000300) +/***********************************************************************/ + + +/***GPT Clock Control Register***/ +#define INCA_IP_GPTU_GPT_CLC ((volatile u32*)(INCA_IP_GPTU+ 0x0000)) +#define INCA_IP_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_GPTU_GPT_CLC_DISS (1 << 1) +#define INCA_IP_GPTU_GPT_CLC_DISR (1 << 0) + +/***GPT Timer 3 Control Register***/ +#define INCA_IP_GPTU_GPT_T3CON ((volatile u32*)(INCA_IP_GPTU+ 0x0014)) +#define INCA_IP_GPTU_GPT_T3CON_T3RDIR (1 << 15) +#define INCA_IP_GPTU_GPT_T3CON_T3CHDIR (1 << 14) +#define INCA_IP_GPTU_GPT_T3CON_T3EDGE (1 << 13) +#define INCA_IP_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) +#define INCA_IP_GPTU_GPT_T3CON_T3OTL (1 << 10) +#define INCA_IP_GPTU_GPT_T3CON_T3UD (1 << 7) +#define INCA_IP_GPTU_GPT_T3CON_T3R (1 << 6) +#define INCA_IP_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) +#define INCA_IP_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Write Hardware Modified Timer 3 Control Register +If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define INCA_IP_GPTU_GPT_WHBT3CON ((volatile u32*)(INCA_IP_GPTU+ 0x004C)) +#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) +#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) +#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) +#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) +#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) +#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) + +/***GPT Timer 2 Control Register***/ +#define INCA_IP_GPTU_GPT_T2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0010)) +#define INCA_IP_GPTU_GPT_T2CON_TxRDIR (1 << 15) +#define INCA_IP_GPTU_GPT_T2CON_TxCHDIR (1 << 14) +#define INCA_IP_GPTU_GPT_T2CON_TxEDGE (1 << 13) +#define INCA_IP_GPTU_GPT_T2CON_TxIRDIS (1 << 12) +#define INCA_IP_GPTU_GPT_T2CON_TxRC (1 << 9) +#define INCA_IP_GPTU_GPT_T2CON_TxUD (1 << 7) +#define INCA_IP_GPTU_GPT_T2CON_TxR (1 << 6) +#define INCA_IP_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) +#define INCA_IP_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Timer 4 Control Register***/ +#define INCA_IP_GPTU_GPT_T4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0018)) +#define INCA_IP_GPTU_GPT_T4CON_TxRDIR (1 << 15) +#define INCA_IP_GPTU_GPT_T4CON_TxCHDIR (1 << 14) +#define INCA_IP_GPTU_GPT_T4CON_TxEDGE (1 << 13) +#define INCA_IP_GPTU_GPT_T4CON_TxIRDIS (1 << 12) +#define INCA_IP_GPTU_GPT_T4CON_TxRC (1 << 9) +#define INCA_IP_GPTU_GPT_T4CON_TxUD (1 << 7) +#define INCA_IP_GPTU_GPT_T4CON_TxR (1 << 6) +#define INCA_IP_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) +#define INCA_IP_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Write HW Modified Timer 2 Control Register If set + and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define INCA_IP_GPTU_GPT_WHBT2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0048)) +#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) +#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) +#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) +#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) + +/***GPT Write HW Modified Timer 4 Control Register If set + and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define INCA_IP_GPTU_GPT_WHBT4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0050)) +#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) +#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) +#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) +#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) + +/***GPT Capture Reload Register***/ +#define INCA_IP_GPTU_GPT_CAPREL ((volatile u32*)(INCA_IP_GPTU+ 0x0030)) +#define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 2 Register***/ +#define INCA_IP_GPTU_GPT_T2 ((volatile u32*)(INCA_IP_GPTU+ 0x0034)) +#define INCA_IP_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 3 Register***/ +#define INCA_IP_GPTU_GPT_T3 ((volatile u32*)(INCA_IP_GPTU+ 0x0038)) +#define INCA_IP_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 4 Register***/ +#define INCA_IP_GPTU_GPT_T4 ((volatile u32*)(INCA_IP_GPTU+ 0x003C)) +#define INCA_IP_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 5 Register***/ +#define INCA_IP_GPTU_GPT_T5 ((volatile u32*)(INCA_IP_GPTU+ 0x0040)) +#define INCA_IP_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 6 Register***/ +#define INCA_IP_GPTU_GPT_T6 ((volatile u32*)(INCA_IP_GPTU+ 0x0044)) +#define INCA_IP_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 6 Control Register***/ +#define INCA_IP_GPTU_GPT_T6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0020)) +#define INCA_IP_GPTU_GPT_T6CON_T6SR (1 << 15) +#define INCA_IP_GPTU_GPT_T6CON_T6CLR (1 << 14) +#define INCA_IP_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) +#define INCA_IP_GPTU_GPT_T6CON_T6OTL (1 << 10) +#define INCA_IP_GPTU_GPT_T6CON_T6UD (1 << 7) +#define INCA_IP_GPTU_GPT_T6CON_T6R (1 << 6) +#define INCA_IP_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) +#define INCA_IP_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Write HW Modified Timer 6 Control Register If set + and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define INCA_IP_GPTU_GPT_WHBT6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0054)) +#define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) +#define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) + +/***GPT Timer 5 Control Register***/ +#define INCA_IP_GPTU_GPT_T5CON ((volatile u32*)(INCA_IP_GPTU+ 0x001C)) +#define INCA_IP_GPTU_GPT_T5CON_T5SC (1 << 15) +#define INCA_IP_GPTU_GPT_T5CON_T5CLR (1 << 14) +#define INCA_IP_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) +#define INCA_IP_GPTU_GPT_T5CON_T5CC (1 << 11) +#define INCA_IP_GPTU_GPT_T5CON_CT3 (1 << 10) +#define INCA_IP_GPTU_GPT_T5CON_T5RC (1 << 9) +#define INCA_IP_GPTU_GPT_T5CON_T5UDE (1 << 8) +#define INCA_IP_GPTU_GPT_T5CON_T5UD (1 << 7) +#define INCA_IP_GPTU_GPT_T5CON_T5R (1 << 6) +#define INCA_IP_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) +#define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : IOM register address and bits */ +/***********************************************************************/ + +#define INCA_IP_IOM (0xBF105000) +/***********************************************************************/ + + +/***Receive FIFO***/ +#define INCA_IP_IOM_RFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) +#define INCA_IP_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Transmit FIFO***/ +#define INCA_IP_IOM_XFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) +#define INCA_IP_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Interrupt Status Register HDLC***/ +#define INCA_IP_IOM_ISTAH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) +#define INCA_IP_IOM_ISTAH_RME (1 << 7) +#define INCA_IP_IOM_ISTAH_RPF (1 << 6) +#define INCA_IP_IOM_ISTAH_RFO (1 << 5) +#define INCA_IP_IOM_ISTAH_XPR (1 << 4) +#define INCA_IP_IOM_ISTAH_XMR (1 << 3) +#define INCA_IP_IOM_ISTAH_XDU (1 << 2) + +/***Interrupt Mask Register HDLC***/ +#define INCA_IP_IOM_MASKH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) +#define INCA_IP_IOM_MASKH_RME (1 << 7) +#define INCA_IP_IOM_MASKH_RPF (1 << 6) +#define INCA_IP_IOM_MASKH_RFO (1 << 5) +#define INCA_IP_IOM_MASKH_XPR (1 << 4) +#define INCA_IP_IOM_MASKH_XMR (1 << 3) +#define INCA_IP_IOM_MASKH_XDU (1 << 2) + +/***Status Register***/ +#define INCA_IP_IOM_STAR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) +#define INCA_IP_IOM_STAR_XDOV (1 << 7) +#define INCA_IP_IOM_STAR_XFW (1 << 6) +#define INCA_IP_IOM_STAR_RACI (1 << 3) +#define INCA_IP_IOM_STAR_XACI (1 << 1) + +/***Command Register***/ +#define INCA_IP_IOM_CMDR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) +#define INCA_IP_IOM_CMDR_RMC (1 << 7) +#define INCA_IP_IOM_CMDR_RRES (1 << 6) +#define INCA_IP_IOM_CMDR_XTF (1 << 3) +#define INCA_IP_IOM_CMDR_XME (1 << 1) +#define INCA_IP_IOM_CMDR_XRES (1 << 0) + +/***Mode Register***/ +#define INCA_IP_IOM_MODEH ((volatile u32*)(INCA_IP_IOM+ 0x0088)) +#define INCA_IP_IOM_MODEH_MDS2 (1 << 7) +#define INCA_IP_IOM_MODEH_MDS1 (1 << 6) +#define INCA_IP_IOM_MODEH_MDS0 (1 << 5) +#define INCA_IP_IOM_MODEH_RAC (1 << 3) +#define INCA_IP_IOM_MODEH_DIM2 (1 << 2) +#define INCA_IP_IOM_MODEH_DIM1 (1 << 1) +#define INCA_IP_IOM_MODEH_DIM0 (1 << 0) + +/***Extended Mode Register***/ +#define INCA_IP_IOM_EXMR ((volatile u32*)(INCA_IP_IOM+ 0x008C)) +#define INCA_IP_IOM_EXMR_XFBS (1 << 7) +#define INCA_IP_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) +#define INCA_IP_IOM_EXMR_SRA (1 << 4) +#define INCA_IP_IOM_EXMR_XCRC (1 << 3) +#define INCA_IP_IOM_EXMR_RCRC (1 << 2) +#define INCA_IP_IOM_EXMR_ITF (1 << 0) + +/***SAPI1 Register***/ +#define INCA_IP_IOM_SAP1 ((volatile u32*)(INCA_IP_IOM+ 0x0094)) +#define INCA_IP_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) +#define INCA_IP_IOM_SAP1_MHA (1 << 0) + +/***Receive Frame Byte Count Low***/ +#define INCA_IP_IOM_RBCL ((volatile u32*)(INCA_IP_IOM+ 0x0098)) +#define INCA_IP_IOM_RBCL_RBC(value) (1 << value) + + +/***SAPI2 Register***/ +#define INCA_IP_IOM_SAP2 ((volatile u32*)(INCA_IP_IOM+ 0x0098)) +#define INCA_IP_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) +#define INCA_IP_IOM_SAP2_MLA (1 << 0) + +/***Receive Frame Byte Count High***/ +#define INCA_IP_IOM_RBCH ((volatile u32*)(INCA_IP_IOM+ 0x009C)) +#define INCA_IP_IOM_RBCH_OV (1 << 4) +#define INCA_IP_IOM_RBCH_RBC11 (1 << 3) +#define INCA_IP_IOM_RBCH_RBC10 (1 << 2) +#define INCA_IP_IOM_RBCH_RBC9 (1 << 1) +#define INCA_IP_IOM_RBCH_RBC8 (1 << 0) + +/***TEI1 Register 1***/ +#define INCA_IP_IOM_TEI1 ((volatile u32*)(INCA_IP_IOM+ 0x009C)) +#define INCA_IP_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) +#define INCA_IP_IOM_TEI1_EA (1 << 0) + +/***Receive Status Register***/ +#define INCA_IP_IOM_RSTA ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) +#define INCA_IP_IOM_RSTA_VFR (1 << 7) +#define INCA_IP_IOM_RSTA_RDO (1 << 6) +#define INCA_IP_IOM_RSTA_CRC (1 << 5) +#define INCA_IP_IOM_RSTA_RAB (1 << 4) +#define INCA_IP_IOM_RSTA_SA1 (1 << 3) +#define INCA_IP_IOM_RSTA_SA0 (1 << 2) +#define INCA_IP_IOM_RSTA_TA (1 << 0) +#define INCA_IP_IOM_RSTA_CR (1 << 1) + +/***TEI2 Register***/ +#define INCA_IP_IOM_TEI2 ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) +#define INCA_IP_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) +#define INCA_IP_IOM_TEI2_EA (1 << 0) + +/***Test Mode Register HDLC***/ +#define INCA_IP_IOM_TMH ((volatile u32*)(INCA_IP_IOM+ 0x00A4)) +#define INCA_IP_IOM_TMH_TLP (1 << 0) + +/***Command/Indication Receive 0***/ +#define INCA_IP_IOM_CIR0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) +#define INCA_IP_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) +#define INCA_IP_IOM_CIR0_CIC0 (1 << 3) +#define INCA_IP_IOM_CIR0_CIC1 (1 << 2) +#define INCA_IP_IOM_CIR0_SG (1 << 1) +#define INCA_IP_IOM_CIR0_BAS (1 << 0) + +/***Command/Indication Transmit 0***/ +#define INCA_IP_IOM_CIX0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) +#define INCA_IP_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) +#define INCA_IP_IOM_CIX0_TBA2 (1 << 3) +#define INCA_IP_IOM_CIX0_TBA1 (1 << 2) +#define INCA_IP_IOM_CIX0_TBA0 (1 << 1) +#define INCA_IP_IOM_CIX0_BAC (1 << 0) + +/***Command/Indication Receive 1***/ +#define INCA_IP_IOM_CIR1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) +#define INCA_IP_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) + +/***Command/Indication Transmit 1***/ +#define INCA_IP_IOM_CIX1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) +#define INCA_IP_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) +#define INCA_IP_IOM_CIX1_CICW (1 << 1) +#define INCA_IP_IOM_CIX1_CI1E (1 << 0) + +/***Controller Data Access Reg. (CH10)***/ +#define INCA_IP_IOM_CDA10 ((volatile u32*)(INCA_IP_IOM+ 0x0100)) +#define INCA_IP_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Controller Data Access Reg. (CH11)***/ +#define INCA_IP_IOM_CDA11 ((volatile u32*)(INCA_IP_IOM+ 0x0104)) +#define INCA_IP_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Controller Data Access Reg. (CH20)***/ +#define INCA_IP_IOM_CDA20 ((volatile u32*)(INCA_IP_IOM+ 0x0108)) +#define INCA_IP_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Controller Data Access Reg. (CH21)***/ +#define INCA_IP_IOM_CDA21 ((volatile u32*)(INCA_IP_IOM+ 0x010C)) +#define INCA_IP_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH10)***/ +#define INCA_IP_IOM_CDA_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0110)) +#define INCA_IP_IOM_CDA_TSDP10_DPS (1 << 7) +#define INCA_IP_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH11)***/ +#define INCA_IP_IOM_CDA_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0114)) +#define INCA_IP_IOM_CDA_TSDP11_DPS (1 << 7) +#define INCA_IP_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH20)***/ +#define INCA_IP_IOM_CDA_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0118)) +#define INCA_IP_IOM_CDA_TSDP20_DPS (1 << 7) +#define INCA_IP_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH21)***/ +#define INCA_IP_IOM_CDA_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x011C)) +#define INCA_IP_IOM_CDA_TSDP21_DPS (1 << 7) +#define INCA_IP_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH10)***/ +#define INCA_IP_IOM_CO_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0120)) +#define INCA_IP_IOM_CO_TSDP10_DPS (1 << 7) +#define INCA_IP_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH11)***/ +#define INCA_IP_IOM_CO_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0124)) +#define INCA_IP_IOM_CO_TSDP11_DPS (1 << 7) +#define INCA_IP_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH20)***/ +#define INCA_IP_IOM_CO_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0128)) +#define INCA_IP_IOM_CO_TSDP20_DPS (1 << 7) +#define INCA_IP_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Time Slot and Data Port Sel. (CH21)***/ +#define INCA_IP_IOM_CO_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x012C)) +#define INCA_IP_IOM_CO_TSDP21_DPS (1 << 7) +#define INCA_IP_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Ctrl. Reg. Contr. Data Access CH1x***/ +#define INCA_IP_IOM_CDA1_CR ((volatile u32*)(INCA_IP_IOM+ 0x0138)) +#define INCA_IP_IOM_CDA1_CR_EN_TBM (1 << 5) +#define INCA_IP_IOM_CDA1_CR_EN_I1 (1 << 4) +#define INCA_IP_IOM_CDA1_CR_EN_I0 (1 << 3) +#define INCA_IP_IOM_CDA1_CR_EN_O1 (1 << 2) +#define INCA_IP_IOM_CDA1_CR_EN_O0 (1 << 1) +#define INCA_IP_IOM_CDA1_CR_SWAP (1 << 0) + +/***Ctrl. Reg. Contr. Data Access CH1x***/ +#define INCA_IP_IOM_CDA2_CR ((volatile u32*)(INCA_IP_IOM+ 0x013C)) +#define INCA_IP_IOM_CDA2_CR_EN_TBM (1 << 5) +#define INCA_IP_IOM_CDA2_CR_EN_I1 (1 << 4) +#define INCA_IP_IOM_CDA2_CR_EN_I0 (1 << 3) +#define INCA_IP_IOM_CDA2_CR_EN_O1 (1 << 2) +#define INCA_IP_IOM_CDA2_CR_EN_O0 (1 << 1) +#define INCA_IP_IOM_CDA2_CR_SWAP (1 << 0) + +/***Control Register B-Channel Data***/ +#define INCA_IP_IOM_BCHA_CR ((volatile u32*)(INCA_IP_IOM+ 0x0144)) +#define INCA_IP_IOM_BCHA_CR_EN_BC2 (1 << 4) +#define INCA_IP_IOM_BCHA_CR_EN_BC1 (1 << 3) + +/***Control Register B-Channel Data***/ +#define INCA_IP_IOM_BCHB_CR ((volatile u32*)(INCA_IP_IOM+ 0x0148)) +#define INCA_IP_IOM_BCHB_CR_EN_BC2 (1 << 4) +#define INCA_IP_IOM_BCHB_CR_EN_BC1 (1 << 3) + +/***Control Reg. for HDLC and CI1 Data***/ +#define INCA_IP_IOM_DCI_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) +#define INCA_IP_IOM_DCI_CR_DPS_CI1 (1 << 7) +#define INCA_IP_IOM_DCI_CR_EN_CI1 (1 << 6) +#define INCA_IP_IOM_DCI_CR_EN_D (1 << 5) + +/***Control Reg. for HDLC and CI1 Data***/ +#define INCA_IP_IOM_DCIC_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) +#define INCA_IP_IOM_DCIC_CR_DPS_CI0 (1 << 7) +#define INCA_IP_IOM_DCIC_CR_EN_CI0 (1 << 6) +#define INCA_IP_IOM_DCIC_CR_DPS_D (1 << 5) + +/***Control Reg. Serial Data Strobe x***/ +#define INCA_IP_IOM_SDS_CR ((volatile u32*)(INCA_IP_IOM+ 0x0154)) +#define INCA_IP_IOM_SDS_CR_ENS_TSS (1 << 7) +#define INCA_IP_IOM_SDS_CR_ENS_TSS_1 (1 << 6) +#define INCA_IP_IOM_SDS_CR_ENS_TSS_3 (1 << 5) +#define INCA_IP_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Control Register IOM Data***/ +#define INCA_IP_IOM_IOM_CR ((volatile u32*)(INCA_IP_IOM+ 0x015C)) +#define INCA_IP_IOM_IOM_CR_SPU (1 << 7) +#define INCA_IP_IOM_IOM_CR_CI_CS (1 << 5) +#define INCA_IP_IOM_IOM_CR_TIC_DIS (1 << 4) +#define INCA_IP_IOM_IOM_CR_EN_BCL (1 << 3) +#define INCA_IP_IOM_IOM_CR_CLKM (1 << 2) +#define INCA_IP_IOM_IOM_CR_Res (1 << 1) +#define INCA_IP_IOM_IOM_CR_DIS_IOM (1 << 0) + +/***Synchronous Transfer Interrupt***/ +#define INCA_IP_IOM_STI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) +#define INCA_IP_IOM_STI_STOV21 (1 << 7) +#define INCA_IP_IOM_STI_STOV20 (1 << 6) +#define INCA_IP_IOM_STI_STOV11 (1 << 5) +#define INCA_IP_IOM_STI_STOV10 (1 << 4) +#define INCA_IP_IOM_STI_STI21 (1 << 3) +#define INCA_IP_IOM_STI_STI20 (1 << 2) +#define INCA_IP_IOM_STI_STI11 (1 << 1) +#define INCA_IP_IOM_STI_STI10 (1 << 0) + +/***Acknowledge Synchronous Transfer Interrupt***/ +#define INCA_IP_IOM_ASTI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) +#define INCA_IP_IOM_ASTI_ACK21 (1 << 3) +#define INCA_IP_IOM_ASTI_ACK20 (1 << 2) +#define INCA_IP_IOM_ASTI_ACK11 (1 << 1) +#define INCA_IP_IOM_ASTI_ACK10 (1 << 0) + +/***Mask Synchronous Transfer Interrupt***/ +#define INCA_IP_IOM_MSTI ((volatile u32*)(INCA_IP_IOM+ 0x0164)) +#define INCA_IP_IOM_MSTI_STOV21 (1 << 7) +#define INCA_IP_IOM_MSTI_STOV20 (1 << 6) +#define INCA_IP_IOM_MSTI_STOV11 (1 << 5) +#define INCA_IP_IOM_MSTI_STOV10 (1 << 4) +#define INCA_IP_IOM_MSTI_STI21 (1 << 3) +#define INCA_IP_IOM_MSTI_STI20 (1 << 2) +#define INCA_IP_IOM_MSTI_STI11 (1 << 1) +#define INCA_IP_IOM_MSTI_STI10 (1 << 0) + +/***Configuration Register for Serial Data Strobes***/ +#define INCA_IP_IOM_SDS_CONF ((volatile u32*)(INCA_IP_IOM+ 0x0168)) +#define INCA_IP_IOM_SDS_CONF_SDS_BCL (1 << 0) + +/***Monitoring CDA Bits***/ +#define INCA_IP_IOM_MCDA ((volatile u32*)(INCA_IP_IOM+ 0x016C)) +#define INCA_IP_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) +#define INCA_IP_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) +#define INCA_IP_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) +#define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : ASC register address and bits */ +/***********************************************************************/ + +#if defined(CONFIG_INCA_IP) +#define INCA_IP_ASC (0xB8000400) +#elif defined(CONFIG_PURPLE) +#define INCA_IP_ASC (0xBE500000) +#endif + +/***********************************************************************/ + + +/***ASC Port Input Select Register***/ +#define INCA_IP_ASC_ASC_PISEL ((volatile u32*)(INCA_IP_ASC+ 0x0004)) +#define INCA_IP_ASC_ASC_PISEL_RIS (1 << 0) + +/***ASC Control Register***/ +#define INCA_IP_ASC_ASC_CON ((volatile u32*)(INCA_IP_ASC+ 0x0010)) +#define INCA_IP_ASC_ASC_CON_R (1 << 15) +#define INCA_IP_ASC_ASC_CON_LB (1 << 14) +#define INCA_IP_ASC_ASC_CON_BRS (1 << 13) +#define INCA_IP_ASC_ASC_CON_ODD (1 << 12) +#define INCA_IP_ASC_ASC_CON_FDE (1 << 11) +#define INCA_IP_ASC_ASC_CON_OE (1 << 10) +#define INCA_IP_ASC_ASC_CON_FE (1 << 9) +#define INCA_IP_ASC_ASC_CON_PE (1 << 8) +#define INCA_IP_ASC_ASC_CON_OEN (1 << 7) +#define INCA_IP_ASC_ASC_CON_FEN (1 << 6) +#define INCA_IP_ASC_ASC_CON_PENRXDI (1 << 5) +#define INCA_IP_ASC_ASC_CON_REN (1 << 4) +#define INCA_IP_ASC_ASC_CON_STP (1 << 3) +#define INCA_IP_ASC_ASC_CON_M (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***ASC Write Hardware Modified Control Register***/ +#define INCA_IP_ASC_ASC_WHBCON ((volatile u32*)(INCA_IP_ASC+ 0x0050)) +#define INCA_IP_ASC_ASC_WHBCON_SETOE (1 << 13) +#define INCA_IP_ASC_ASC_WHBCON_SETFE (1 << 12) +#define INCA_IP_ASC_ASC_WHBCON_SETPE (1 << 11) +#define INCA_IP_ASC_ASC_WHBCON_CLROE (1 << 10) +#define INCA_IP_ASC_ASC_WHBCON_CLRFE (1 << 9) +#define INCA_IP_ASC_ASC_WHBCON_CLRPE (1 << 8) +#define INCA_IP_ASC_ASC_WHBCON_SETREN (1 << 5) +#define INCA_IP_ASC_ASC_WHBCON_CLRREN (1 << 4) + +/***ASC Baudrate Timer/Reload Register***/ +#define INCA_IP_ASC_ASC_BTR ((volatile u32*)(INCA_IP_ASC+ 0x0014)) +#define INCA_IP_ASC_ASC_BTR_BR_VALUE (value) (((( 1 << 13) - 1) & (value)) << 0) + +/***ASC Fractional Divider Register***/ +#define INCA_IP_ASC_ASC_FDV ((volatile u32*)(INCA_IP_ASC+ 0x0018)) +#define INCA_IP_ASC_ASC_FDV_FD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) + +/***ASC IrDA Pulse Mode/Width Register***/ +#define INCA_IP_ASC_ASC_PMW ((volatile u32*)(INCA_IP_ASC+ 0x001C)) +#define INCA_IP_ASC_ASC_PMW_IRPW (1 << 8) +#define INCA_IP_ASC_ASC_PMW_PW_VALUE (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***ASC Transmit Buffer Register***/ +#define INCA_IP_ASC_ASC_TBUF ((volatile u32*)(INCA_IP_ASC+ 0x0020)) +#define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) + +/***ASC Receive Buffer Register***/ +#define INCA_IP_ASC_ASC_RBUF ((volatile u32*)(INCA_IP_ASC+ 0x0024)) +#define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) + +/***ASC Autobaud Control Register***/ +#define INCA_IP_ASC_ASC_ABCON ((volatile u32*)(INCA_IP_ASC+ 0x0030)) +#define INCA_IP_ASC_ASC_ABCON_RXINV (1 << 11) +#define INCA_IP_ASC_ASC_ABCON_TXINV (1 << 10) +#define INCA_IP_ASC_ASC_ABCON_ABEM (value) (((( 1 << 2) - 1) & (value)) << 8) +#define INCA_IP_ASC_ASC_ABCON_FCDETEN (1 << 4) +#define INCA_IP_ASC_ASC_ABCON_ABDETEN (1 << 3) +#define INCA_IP_ASC_ASC_ABCON_ABSTEN (1 << 2) +#define INCA_IP_ASC_ASC_ABCON_AUREN (1 << 1) +#define INCA_IP_ASC_ASC_ABCON_ABEN (1 << 0) + +/***Receive FIFO Control Register***/ +#define INCA_IP_ASC_RXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0040)) +#define INCA_IP_ASC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) +#define INCA_IP_ASC_RXFCON_RXTMEN (1 << 2) +#define INCA_IP_ASC_RXFCON_RXFFLU (1 << 1) +#define INCA_IP_ASC_RXFCON_RXFEN (1 << 0) + +/***Transmit FIFO Control Register***/ +#define INCA_IP_ASC_TXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0044)) +#define INCA_IP_ASC_TXFCON_TXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) +#define INCA_IP_ASC_TXFCON_TXTMEN (1 << 2) +#define INCA_IP_ASC_TXFCON_TXFFLU (1 << 1) +#define INCA_IP_ASC_TXFCON_TXFEN (1 << 0) + +/***FIFO Status Register***/ +#define INCA_IP_ASC_FSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0048)) +#define INCA_IP_ASC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) +#define INCA_IP_ASC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) + +/***ASC Write HW Modified Autobaud Control Register***/ +#define INCA_IP_ASC_ASC_WHBABCON ((volatile u32*)(INCA_IP_ASC+ 0x0054)) +#define INCA_IP_ASC_ASC_WHBABCON_SETABEN (1 << 1) +#define INCA_IP_ASC_ASC_WHBABCON_CLRABEN (1 << 0) + +/***ASC Autobaud Status Register***/ +#define INCA_IP_ASC_ASC_ABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0034)) +#define INCA_IP_ASC_ASC_ABSTAT_DETWAIT (1 << 4) +#define INCA_IP_ASC_ASC_ABSTAT_SCCDET (1 << 3) +#define INCA_IP_ASC_ASC_ABSTAT_SCSDET (1 << 2) +#define INCA_IP_ASC_ASC_ABSTAT_FCCDET (1 << 1) +#define INCA_IP_ASC_ASC_ABSTAT_FCSDET (1 << 0) + +/***ASC Write HW Modified Autobaud Status Register***/ +#define INCA_IP_ASC_ASC_WHBABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0058)) +#define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT (1 << 9) +#define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) +#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET (1 << 7) +#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET (1 << 6) +#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET (1 << 5) +#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET (1 << 4) +#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET (1 << 3) +#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET (1 << 2) +#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET (1 << 1) +#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET (1 << 0) + +/***ASC Clock Control Register***/ +#define INCA_IP_ASC_ASC_CLC ((volatile u32*)(INCA_IP_ASC+ 0x0000)) +#define INCA_IP_ASC_ASC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_ASC_ASC_CLC_DISS (1 << 1) +#define INCA_IP_ASC_ASC_CLC_DISR (1 << 0) + +/***********************************************************************/ +/* Module : DMA register address and bits */ +/***********************************************************************/ + +#define INCA_IP_DMA (0xBF108000) +/***********************************************************************/ + + +/***DMA RX Channel 0 Command Register***/ +#define INCA_IP_DMA_DMA_RXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0800)) +#define INCA_IP_DMA_DMA_RXCCR0_LBE (1 << 31) +#define INCA_IP_DMA_DMA_RXCCR0_HPEN (1 << 30) +#define INCA_IP_DMA_DMA_RXCCR0_INIT (1 << 2) +#define INCA_IP_DMA_DMA_RXCCR0_OFF (1 << 1) +#define INCA_IP_DMA_DMA_RXCCR0_HR (1 << 0) + +/***DMA RX Channel 1 Command Register***/ +#define INCA_IP_DMA_DMA_RXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0804)) +#define INCA_IP_DMA_DMA_RXCCR1_LBE (1 << 31) +#define INCA_IP_DMA_DMA_RXCCR1_HPEN (1 << 30) +#define INCA_IP_DMA_DMA_RXCCR1_INIT (1 << 2) +#define INCA_IP_DMA_DMA_RXCCR1_OFF (1 << 1) +#define INCA_IP_DMA_DMA_RXCCR1_HR (1 << 0) + +/***DMA Receive Interrupt Status Register***/ +#define INCA_IP_DMA_DMA_RXISR ((volatile u32*)(INCA_IP_DMA+ 0x0808)) +#define INCA_IP_DMA_DMA_RXISR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) +#define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) +#define INCA_IP_DMA_DMA_RXISR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) +#define INCA_IP_DMA_DMA_RXISR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) +#define INCA_IP_DMA_DMA_RXISR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***DMA Receive Interrupt Mask Register***/ +#define INCA_IP_DMA_DMA_RXIMR ((volatile u32*)(INCA_IP_DMA+ 0x080C)) +#define INCA_IP_DMA_DMA_RXIMR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) +#define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) +#define INCA_IP_DMA_DMA_RXIMR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) +#define INCA_IP_DMA_DMA_RXIMR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) +#define INCA_IP_DMA_DMA_RXIMR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***DMA First Receive Descriptor Addr. for Rx Channel 0 +***/ +#define INCA_IP_DMA_DMA_RXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x0810)) +#define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) + +/***DMA First Receive Descriptor Addr. for Rx Channel 1 +***/ +#define INCA_IP_DMA_DMA_RXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x0814)) +#define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) + +/***DMA Receive Channel Polling Time***/ +#define INCA_IP_DMA_DMA_RXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x0818)) +#define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 30) +#define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 28) +#define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***DMA TX Channel 0 Command Register (Voice Port)***/ +#define INCA_IP_DMA_DMA_TXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0880)) +#define INCA_IP_DMA_DMA_TXCCR0_LBE (1 << 31) +#define INCA_IP_DMA_DMA_TXCCR0_HPEN (1 << 30) +#define INCA_IP_DMA_DMA_TXCCR0_HR (1 << 2) +#define INCA_IP_DMA_DMA_TXCCR0_OFF (1 << 1) +#define INCA_IP_DMA_DMA_TXCCR0_INIT (1 << 0) + +/***DMA TX Channel 1 Command Register (Mangmt Port)***/ +#define INCA_IP_DMA_DMA_TXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0884)) +#define INCA_IP_DMA_DMA_TXCCR1_LBE (1 << 31) +#define INCA_IP_DMA_DMA_TXCCR1_HPEN (1 << 30) +#define INCA_IP_DMA_DMA_TXCCR1_HR (1 << 2) +#define INCA_IP_DMA_DMA_TXCCR1_OFF (1 << 1) +#define INCA_IP_DMA_DMA_TXCCR1_INIT (1 << 0) + +/***DMA TX Channel 2 Command Register (SSC Port)***/ +#define INCA_IP_DMA_DMA_TXCCR2 ((volatile u32*)(INCA_IP_DMA+ 0x0888)) +#define INCA_IP_DMA_DMA_TXCCR2_LBE (1 << 31) +#define INCA_IP_DMA_DMA_TXCCR2_HPEN (1 << 30) +#define INCA_IP_DMA_DMA_TXCCR2_HBF (1 << 29) +#define INCA_IP_DMA_DMA_TXCCR2_HR (1 << 2) +#define INCA_IP_DMA_DMA_TXCCR2_OFF (1 << 1) +#define INCA_IP_DMA_DMA_TXCCR2_INIT (1 << 0) + +/***DMA First Receive Descriptor Addr. for Tx Channel 0 +***/ +#define INCA_IP_DMA_DMA_TXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x08A0)) +#define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) + +/***DMA First Receive Descriptor Addr. for Tx Channel 1 +***/ +#define INCA_IP_DMA_DMA_TXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x08A4)) +#define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) + +/***DMA First Receive Descriptor Addr. for Tx Channel 2 +***/ +#define INCA_IP_DMA_DMA_TXFRDA2 ((volatile u32*)(INCA_IP_DMA+ 0x08A8)) +#define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) + +/***DMA Transmit Channel Arbitration Register***/ +#define INCA_IP_DMA_DMA_TXWGT ((volatile u32*)(INCA_IP_DMA+ 0x08C0)) +#define INCA_IP_DMA_DMA_TXWGT_TX2PR (value) (((( 1 << 2) - 1) & (value)) << 4) +#define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value) (((( 1 << 2) - 1) & (value)) << 2) +#define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***DMA Transmit Channel Polling Time***/ +#define INCA_IP_DMA_DMA_TXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x08C4)) +#define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value) (((( 1 << 2) - 1) & (value)) << 30) +#define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 28) +#define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 26) +#define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***DMA Transmit Interrupt Status Register***/ +#define INCA_IP_DMA_DMA_TXISR ((volatile u32*)(INCA_IP_DMA+ 0x08C8)) +#define INCA_IP_DMA_DMA_TXISR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) +#define INCA_IP_DMA_DMA_TXISR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) +#define INCA_IP_DMA_DMA_TXISR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) +#define INCA_IP_DMA_DMA_TXISR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) +#define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***DMA Transmit Interrupt Mask Register***/ +#define INCA_IP_DMA_DMA_TXIMR ((volatile u32*)(INCA_IP_DMA+ 0x08CC)) +#define INCA_IP_DMA_DMA_TXIMR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) +#define INCA_IP_DMA_DMA_TXIMR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) +#define INCA_IP_DMA_DMA_TXIMR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) +#define INCA_IP_DMA_DMA_TXIMR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) +#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : Debug register address and bits */ +/***********************************************************************/ + +#define INCA_IP_Debug (0xBF106000) +/***********************************************************************/ + + +/***MCD Break Bus Switch Register***/ +#define INCA_IP_Debug_MCD_BBS ((volatile u32*)(INCA_IP_Debug+ 0x0000)) +#define INCA_IP_Debug_MCD_BBS_BTP1 (1 << 19) +#define INCA_IP_Debug_MCD_BBS_BTP0 (1 << 18) +#define INCA_IP_Debug_MCD_BBS_BSP1 (1 << 17) +#define INCA_IP_Debug_MCD_BBS_BSP0 (1 << 16) +#define INCA_IP_Debug_MCD_BBS_BT5EN (1 << 15) +#define INCA_IP_Debug_MCD_BBS_BT4EN (1 << 14) +#define INCA_IP_Debug_MCD_BBS_BT5 (1 << 13) +#define INCA_IP_Debug_MCD_BBS_BT4 (1 << 12) +#define INCA_IP_Debug_MCD_BBS_BS5EN (1 << 7) +#define INCA_IP_Debug_MCD_BBS_BS4EN (1 << 6) +#define INCA_IP_Debug_MCD_BBS_BS5 (1 << 5) +#define INCA_IP_Debug_MCD_BBS_BS4 (1 << 4) + +/***MCD Multiplexer Control Register***/ +#define INCA_IP_Debug_MCD_MCR ((volatile u32*)(INCA_IP_Debug+ 0x0008)) +#define INCA_IP_Debug_MCD_MCR_MUX5 (1 << 4) +#define INCA_IP_Debug_MCD_MCR_MUX4 (1 << 3) +#define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0) + +/***********************************************************************/ +/* Module : TSF register address and bits */ +/***********************************************************************/ + +#define INCA_IP_TSF (0xB8000900) +/***********************************************************************/ + + +/***TSF Configuration Register (0000H)***/ +#define INCA_IP_TSF_TSF_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0000)) +#define INCA_IP_TSF_TSF_CONF_PWMEN (1 << 2) +#define INCA_IP_TSF_TSF_CONF_LEDEN (1 << 1) +#define INCA_IP_TSF_TSF_CONF_KEYEN (1 << 0) + +/***Key scan Configuration Register (0004H)***/ +#define INCA_IP_TSF_KEY_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0004)) +#define INCA_IP_TSF_KEY_CONF_SL (value) (((( 1 << 4) - 1) & (value)) << 0) + +/***Scan Register Line 0 and 1 (0008H)***/ +#define INCA_IP_TSF_SREG01 ((volatile u32*)(INCA_IP_TSF+ 0x0008)) +#define INCA_IP_TSF_SREG01_RES1x (value) (((( 1 << 12) - 1) & (value)) << 16) +#define INCA_IP_TSF_SREG01_RES0x (value) (((( 1 << 13) - 1) & (value)) << 0) + +/***Scan Register Line 2 and 3 (000CH)***/ +#define INCA_IP_TSF_SREG23 ((volatile u32*)(INCA_IP_TSF+ 0x000C)) +#define INCA_IP_TSF_SREG23_RES3x (value) (((( 1 << 10) - 1) & (value)) << 16) +#define INCA_IP_TSF_SREG23_RES2x (value) (((( 1 << 11) - 1) & (value)) << 0) + +/***Scan Register Line 4, 5 and 6 (0010H)***/ +#define INCA_IP_TSF_SREG456 ((volatile u32*)(INCA_IP_TSF+ 0x0010)) +#define INCA_IP_TSF_SREG456_RES6x (value) (((( 1 << 7) - 1) & (value)) << 24) +#define INCA_IP_TSF_SREG456_RES5x (value) (((( 1 << 8) - 1) & (value)) << 16) +#define INCA_IP_TSF_SREG456_RES4x (value) (((( 1 << 9) - 1) & (value)) << 0) + +/***Scan Register Line 7 to 12 (0014H)***/ +#define INCA_IP_TSF_SREG7to12 ((volatile u32*)(INCA_IP_TSF+ 0x0014)) +#define INCA_IP_TSF_SREG7to12_RES12x (1 << 28) +#define INCA_IP_TSF_SREG7to12_RES11x (value) (((( 1 << 2) - 1) & (value)) << 24) +#define INCA_IP_TSF_SREG7to12_RES10x (value) (((( 1 << 3) - 1) & (value)) << 20) +#define INCA_IP_TSF_SREG7to12_RES9x (value) (((( 1 << 4) - 1) & (value)) << 16) +#define INCA_IP_TSF_SREG7to12_RES8x (value) (((( 1 << 5) - 1) & (value)) << 8) +#define INCA_IP_TSF_SREG7to12_RES7x (value) (((( 1 << 6) - 1) & (value)) << 0) + +/***LEDMUX Configuration Register (0018H)***/ +#define INCA_IP_TSF_LEDMUX_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0018)) +#define INCA_IP_TSF_LEDMUX_CONF_ETL1 (1 << 25) +#define INCA_IP_TSF_LEDMUX_CONF_ESTA1 (1 << 24) +#define INCA_IP_TSF_LEDMUX_CONF_EDPX1 (1 << 23) +#define INCA_IP_TSF_LEDMUX_CONF_EACT1 (1 << 22) +#define INCA_IP_TSF_LEDMUX_CONF_ESPD1 (1 << 21) +#define INCA_IP_TSF_LEDMUX_CONF_ETL0 (1 << 20) +#define INCA_IP_TSF_LEDMUX_CONF_ESTA0 (1 << 19) +#define INCA_IP_TSF_LEDMUX_CONF_EDPX0 (1 << 18) +#define INCA_IP_TSF_LEDMUX_CONF_EACT0 (1 << 17) +#define INCA_IP_TSF_LEDMUX_CONF_ESPD0 (1 << 16) +#define INCA_IP_TSF_LEDMUX_CONF_INV (1 << 1) +#define INCA_IP_TSF_LEDMUX_CONF_NCOL (1 << 0) + +/***LED Register (001CH)***/ +#define INCA_IP_TSF_LED_REG ((volatile u32*)(INCA_IP_TSF+ 0x001C)) +#define INCA_IP_TSF_LED_REG_Lxy (value) (((( 1 << 24) - 1) & (value)) << 0) + +/***Pulse Width Modulator 1 and 2 Register (0020H)***/ +#define INCA_IP_TSF_PWM12 ((volatile u32*)(INCA_IP_TSF+ 0x0020)) +#define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN) + +/***********************************************************************/ +/* Module : Ports register address and bits */ +/***********************************************************************/ + +#define INCA_IP_Ports (0xB8000A00) +/***********************************************************************/ + + +/***Port 1 Data Output Register (0020H)***/ +#define INCA_IP_Ports_P1_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0020)) +#define INCA_IP_Ports_P1_OUT_P(value) (1 << value) + + +/***Port 2 Data Output Register (0040H)***/ +#define INCA_IP_Ports_P2_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0040)) +#define INCA_IP_Ports_P2_OUT_P(value) (1 << value) + + +/***Port 1 Data Input Register (0024H)***/ +#define INCA_IP_Ports_P1_IN ((volatile u32*)(INCA_IP_Ports+ 0x0024)) +#define INCA_IP_Ports_P1_IN_P(value) (1 << value) + + +/***Port 2 Data Input Register (0044H)***/ +#define INCA_IP_Ports_P2_IN ((volatile u32*)(INCA_IP_Ports+ 0x0044)) +#define INCA_IP_Ports_P2_IN_P(value) (1 << value) + + +/***Port 1 Direction Register (0028H)***/ +#define INCA_IP_Ports_P1_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0028)) +#define INCA_IP_Ports_P1_DIR_Port1P(value) (1 << value) + +#define INCA_IP_Ports_P1_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***Port 2 Direction Register (0048H)***/ +#define INCA_IP_Ports_P2_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0048)) +#define INCA_IP_Ports_P2_DIR_Port1P(value) (1 << value) + +#define INCA_IP_Ports_P2_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) + +/***Port 0 Alternate Function Select Register 0 (000C H) +***/ +#define INCA_IP_Ports_P0_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x000C)) +#define INCA_IP_Ports_P0_ALTSEL_Port0P(value) (1 << value) + + +/***Port 1 Alternate Function Select Register 0 (002C H) +***/ +#define INCA_IP_Ports_P1_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x002C)) +#define INCA_IP_Ports_P1_ALTSEL_Port1P(value) (1 << value) + +#define INCA_IP_Ports_P1_ALTSEL_Port2P(value) (1 << value) + + +/***Port 2 Alternate Function Select Register 0 (004C H) +***/ +#define INCA_IP_Ports_P2_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x004C)) +#define INCA_IP_Ports_P2_ALTSEL_Port1P(value) (1 << value) + +#define INCA_IP_Ports_P2_ALTSEL_Port2P(value) (1 << value) + + +/***Port 0 Input Schmitt-Trigger Off Register (0010 H) +***/ +#define INCA_IP_Ports_P0_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0010)) +#define INCA_IP_Ports_P0_STOFF_Port0P(value) (1 << value) + + +/***Port 1 Input Schmitt-Trigger Off Register (0030 H) +***/ +#define INCA_IP_Ports_P1_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0030)) +#define INCA_IP_Ports_P1_STOFF_Port1P(value) (1 << value) + +#define INCA_IP_Ports_P1_STOFF_Port2P(value) (1 << value) + + +/***Port 2 Input Schmitt-Trigger Off Register (0050 H) +***/ +#define INCA_IP_Ports_P2_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0050)) +#define INCA_IP_Ports_P2_STOFF_Port1P(value) (1 << value) + +#define INCA_IP_Ports_P2_STOFF_Port2P(value) (1 << value) + + +/***Port 2 Open Drain Control Register (0054H)***/ +#define INCA_IP_Ports_P2_OD ((volatile u32*)(INCA_IP_Ports+ 0x0054)) +#define INCA_IP_Ports_P2_OD_Port2P(value) (1 << value) + + +/***Port 0 Pull Up Device Enable Register (0018 H)***/ +#define INCA_IP_Ports_P0_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0018)) +#define INCA_IP_Ports_P0_PUDEN_Port0P(value) (1 << value) + + +/***Port 2 Pull Up Device Enable Register (0058 H)***/ +#define INCA_IP_Ports_P2_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0058)) +#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) + +#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) + + +/***Port 0 Pull Up/Pull Down Select Register (001C H)***/ +#define INCA_IP_Ports_P0_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x001C)) +#define INCA_IP_Ports_P0_PUDSEL_Port0P(value) (1 << value) + + +/***Port 2 Pull Up/Pull Down Select Register (005C H)***/ +#define INCA_IP_Ports_P2_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x005C)) +#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) + +#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) + + +/***********************************************************************/ +/* Module : DES/3DES register address and bits */ +/***********************************************************************/ + +#define INCA_IP_DES_3DES (0xB8000800) +/***********************************************************************/ + + +/***DES Input Data High Register***/ +#define INCA_IP_DES_3DES_DES_IHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000)) +#define INCA_IP_DES_3DES_DES_IHR_IH(value) (1 << value) + + +/***DES Input Data Low Register***/ +#define INCA_IP_DES_3DES_DES_ILR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004)) +#define INCA_IP_DES_3DES_DES_ILR_IL(value) (1 << value) + + +/***DES Key #1 High Register***/ +#define INCA_IP_DES_3DES_DES_K1HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008)) +#define INCA_IP_DES_3DES_DES_K1HR_K1H(value) (1 << value) + + +/***DES Key #1 Low Register***/ +#define INCA_IP_DES_3DES_DES_K1LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C)) +#define INCA_IP_DES_3DES_DES_K1LR_K1L(value) (1 << value) + + +/***DES Key #2 High Register***/ +#define INCA_IP_DES_3DES_DES_K2HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010)) +#define INCA_IP_DES_3DES_DES_K2HR_K2H(value) (1 << value) + + +/***DES Key #2 Low Register***/ +#define INCA_IP_DES_3DES_DES_K2LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014)) +#define INCA_IP_DES_3DES_DES_K2LR_K2L(value) (1 << value) + + +/***DES Key #3 High Register***/ +#define INCA_IP_DES_3DES_DES_K3HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018)) +#define INCA_IP_DES_3DES_DES_K3HR_K3H(value) (1 << value) + + +/***DES Key #3 Low Register***/ +#define INCA_IP_DES_3DES_DES_K3LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C)) +#define INCA_IP_DES_3DES_DES_K3LR_K3L(value) (1 << value) + + +/***DES Initialization Vector High Register***/ +#define INCA_IP_DES_3DES_DES_IVHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020)) +#define INCA_IP_DES_3DES_DES_IVHR_IVH(value) (1 << value) + + +/***DES Initialization Vector Low Register***/ +#define INCA_IP_DES_3DES_DES_IVLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024)) +#define INCA_IP_DES_3DES_DES_IVLR_IVL(value) (1 << value) + + +/***DES Control Register***/ +#define INCA_IP_DES_3DES_DES_CONTROLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028)) +#define INCA_IP_DES_3DES_DES_CONTROLR_KRE (1 << 31) +#define INCA_IP_DES_3DES_DES_CONTROLR_DAU (1 << 16) +#define INCA_IP_DES_3DES_DES_CONTROLR_F(value) (1 << value) + +#define INCA_IP_DES_3DES_DES_CONTROLR_O(value) (1 << value) + +#define INCA_IP_DES_3DES_DES_CONTROLR_GO (1 << 8) +#define INCA_IP_DES_3DES_DES_CONTROLR_STP (1 << 7) +#define INCA_IP_DES_3DES_DES_CONTROLR_IEN (1 << 6) +#define INCA_IP_DES_3DES_DES_CONTROLR_BUS (1 << 5) +#define INCA_IP_DES_3DES_DES_CONTROLR_SM (1 << 4) +#define INCA_IP_DES_3DES_DES_CONTROLR_E_D (1 << 3) +#define INCA_IP_DES_3DES_DES_CONTROLR_M(value) (1 << value) + + +/***DES Output Data High Register***/ +#define INCA_IP_DES_3DES_DES_OHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C)) +#define INCA_IP_DES_3DES_DES_OHR_OH(value) (1 << value) + + +/***DES Output Data Low Register***/ +#define INCA_IP_DES_3DES_DES_OLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030)) +#define INCA_IP_DES_3DES_DES_OLR_OL(value) (1 << value) + + +/***********************************************************************/ +/* Module : AES register address and bits */ +/***********************************************************************/ + +#define INCA_IP_AES (0xB8000880) +/***********************************************************************/ + + +/***AES Input Data 3 Register***/ +#define INCA_IP_AES_AES_ID3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_ID3R_I(value) (1 << value) + + +/***AES Input Data 2 Register***/ +#define INCA_IP_AES_AES_ID2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_ID2R_I(value) (1 << value) + + +/***AES Input Data 1 Register***/ +#define INCA_IP_AES_AES_ID1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_ID1R_I(value) (1 << value) + + +/***AES Input Data 0 Register***/ +#define INCA_IP_AES_AES_ID0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_ID0R_I(value) (1 << value) + + +/***AES Output Data 3 Register***/ +#define INCA_IP_AES_AES_OD3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_OD3R_O(value) (1 << value) + + +/***AES Output Data 2 Register***/ +#define INCA_IP_AES_AES_OD2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_OD2R_O(value) (1 << value) + + +/***AES Output Data 1 Register***/ +#define INCA_IP_AES_AES_OD1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_OD1R_O(value) (1 << value) + + +/***AES Output Data 0 Register***/ +#define INCA_IP_AES_AES_OD0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_OD0R_O(value) (1 << value) + + +/***AES Key 7 Register***/ +#define INCA_IP_AES_AES_K7R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_K7R_K(value) (1 << value) + + +/***AES Key 6 Register***/ +#define INCA_IP_AES_AES_K6R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_K6R_K(value) (1 << value) + + +/***AES Key 5 Register***/ +#define INCA_IP_AES_AES_K5R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_K5R_K(value) (1 << value) + + +/***AES Key 4 Register***/ +#define INCA_IP_AES_AES_K4R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_K4R_K(value) (1 << value) + + +/***AES Key 3 Register***/ +#define INCA_IP_AES_AES_K3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_K3R_K(value) (1 << value) + + +/***AES Key 2 Register***/ +#define INCA_IP_AES_AES_K2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_K2R_K(value) (1 << value) + + +/***AES Key 1 Register***/ +#define INCA_IP_AES_AES_K1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_K1R_K(value) (1 << value) + + +/***AES Key 0 Register***/ +#define INCA_IP_AES_AES_K0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_K0R_K(value) (1 << value) + + +/***AES Initialization Vector 3 Register***/ +#define INCA_IP_AES_AES_IV3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_IV3R_IV(value) (1 << value) + + +/***AES Initialization Vector 2 Register***/ +#define INCA_IP_AES_AES_IV2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_IV2R_IV(value) (1 << value) + + +/***AES Initialization Vector 1 Register***/ +#define INCA_IP_AES_AES_IV1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_IV1R_IV(value) (1 << value) + + +/***AES Initialization Vector 0 Register***/ +#define INCA_IP_AES_AES_IV0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_IV0R_IV (value) (((( 1 << 32) - 1) &(value)) << 0) + +/***AES Control Register***/ +#define INCA_IP_AES_AES_CONTROLR ((volatile u32*)(INCA_IP_AES+ 0x0000)) +#define INCA_IP_AES_AES_CONTROLR_KRE (1 << 31) +#define INCA_IP_AES_AES_CONTROLR_DAU (1 << 16) +#define INCA_IP_AES_AES_CONTROLR_PNK (1 << 15) +#define INCA_IP_AES_AES_CONTROLR_F(value) (1 << value) + +#define INCA_IP_AES_AES_CONTROLR_O(value) (1 << value) + +#define INCA_IP_AES_AES_CONTROLR_GO (1 << 8) +#define INCA_IP_AES_AES_CONTROLR_STP (1 << 7) +#define INCA_IP_AES_AES_CONTROLR_IEN (1 << 6) +#define INCA_IP_AES_AES_CONTROLR_BUS (1 << 5) +#define INCA_IP_AES_AES_CONTROLR_SM (1 << 4) +#define INCA_IP_AES_AES_CONTROLR_E_D (1 << 3) +#define INCA_IP_AES_AES_CONTROLR_KV (1 << 2) +#define INCA_IP_AES_AES_CONTROLR_K(value) (1 << value) + + +/***********************************************************************/ +/* Module : I²C register address and bits */ +/***********************************************************************/ + +#define INCA_IP_IIC (0xB8000700) +/***********************************************************************/ + + +/***I²C Port Input Select Register***/ +#define INCA_IP_IIC_IIC_PISEL ((volatile u32*)(INCA_IP_IIC+ 0x0004)) +#define INCA_IP_IIC_IIC_PISEL_SDAIS(value) (1 << value) + +#define INCA_IP_IIC_IIC_PISEL_SCLIS(value) (1 << value) + + +/***I²C Clock Control Register***/ +#define INCA_IP_IIC_IIC_CLC ((volatile u32*)(INCA_IP_IIC+ 0x0000)) +#define INCA_IP_IIC_IIC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_IIC_IIC_CLC_DISS (1 << 1) +#define INCA_IP_IIC_IIC_CLC_DISR (1 << 0) + +/***I²C System Control Register***/ +#define INCA_IP_IIC_IIC_SYSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) +#define INCA_IP_IIC_IIC_SYSCON_0_WMEN (1 << 31) +#define INCA_IP_IIC_IIC_SYSCON_0_CI (value) (((( 1 << 2) - 1) & (value)) << 26) +#define INCA_IP_IIC_IIC_SYSCON_0_STP (1 << 25) +#define INCA_IP_IIC_IIC_SYSCON_0_IGE (1 << 24) +#define INCA_IP_IIC_IIC_SYSCON_0_TRX (1 << 23) +#define INCA_IP_IIC_IIC_SYSCON_0_INT (1 << 22) +#define INCA_IP_IIC_IIC_SYSCON_0_ACKDIS (1 << 21) +#define INCA_IP_IIC_IIC_SYSCON_0_BUM (1 << 20) +#define INCA_IP_IIC_IIC_SYSCON_0_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) +#define INCA_IP_IIC_IIC_SYSCON_0_RSC (1 << 17) +#define INCA_IP_IIC_IIC_SYSCON_0_M10 (1 << 16) +#define INCA_IP_IIC_IIC_SYSCON_0_RMEN (1 << 15) +#define INCA_IP_IIC_IIC_SYSCON_0_CO (value) (((( 1 << 3) - 1) & (value)) << 8) +#define INCA_IP_IIC_IIC_SYSCON_0_IRQE (1 << 7) +#define INCA_IP_IIC_IIC_SYSCON_0_IRQP (1 << 6) +#define INCA_IP_IIC_IIC_SYSCON_0_IRQD (1 << 5) +#define INCA_IP_IIC_IIC_SYSCON_0_BB (1 << 4) +#define INCA_IP_IIC_IIC_SYSCON_0_LRB (1 << 3) +#define INCA_IP_IIC_IIC_SYSCON_0_SLA (1 << 2) +#define INCA_IP_IIC_IIC_SYSCON_0_AL (1 << 1) +#define INCA_IP_IIC_IIC_SYSCON_0_ADR (1 << 0) + +/***I²C System Control Register***/ +#define INCA_IP_IIC_IIC_SYSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) +#define INCA_IP_IIC_IIC_SYSCON_1_RM (value) (((( 1 << 8) - 1) & (value)) << 24) +#define INCA_IP_IIC_IIC_SYSCON_1_TRX (1 << 23) +#define INCA_IP_IIC_IIC_SYSCON_1_INT (1 << 22) +#define INCA_IP_IIC_IIC_SYSCON_1_ACKDIS (1 << 21) +#define INCA_IP_IIC_IIC_SYSCON_1_BUM (1 << 20) +#define INCA_IP_IIC_IIC_SYSCON_1_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) +#define INCA_IP_IIC_IIC_SYSCON_1_RSC (1 << 17) +#define INCA_IP_IIC_IIC_SYSCON_1_M10 (1 << 16) +#define INCA_IP_IIC_IIC_SYSCON_1_RMEN (1 << 15) +#define INCA_IP_IIC_IIC_SYSCON_1_CO (value) (((( 1 << 3) - 1) & (value)) << 8) +#define INCA_IP_IIC_IIC_SYSCON_1_IRQE (1 << 7) +#define INCA_IP_IIC_IIC_SYSCON_1_IRQP (1 << 6) +#define INCA_IP_IIC_IIC_SYSCON_1_IRQD (1 << 5) +#define INCA_IP_IIC_IIC_SYSCON_1_BB (1 << 4) +#define INCA_IP_IIC_IIC_SYSCON_1_LRB (1 << 3) +#define INCA_IP_IIC_IIC_SYSCON_1_SLA (1 << 2) +#define INCA_IP_IIC_IIC_SYSCON_1_AL (1 << 1) +#define INCA_IP_IIC_IIC_SYSCON_1_ADR (1 << 0) + +/***I²C System Control Register***/ +#define INCA_IP_IIC_IIC_SYSCON_2 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) +#define INCA_IP_IIC_IIC_SYSCON_2_WMEN (1 << 31) +#define INCA_IP_IIC_IIC_SYSCON_2_CI (value) (((( 1 << 2) - 1) & (value)) << 26) +#define INCA_IP_IIC_IIC_SYSCON_2_STP (1 << 25) +#define INCA_IP_IIC_IIC_SYSCON_2_IGE (1 << 24) +#define INCA_IP_IIC_IIC_SYSCON_2_TRX (1 << 23) +#define INCA_IP_IIC_IIC_SYSCON_2_INT (1 << 22) +#define INCA_IP_IIC_IIC_SYSCON_2_ACKDIS (1 << 21) +#define INCA_IP_IIC_IIC_SYSCON_2_BUM (1 << 20) +#define INCA_IP_IIC_IIC_SYSCON_2_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) +#define INCA_IP_IIC_IIC_SYSCON_2_RSC (1 << 17) +#define INCA_IP_IIC_IIC_SYSCON_2_M10 (1 << 16) +#define INCA_IP_IIC_IIC_SYSCON_2_WM (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_IIC_IIC_SYSCON_2_IRQE (1 << 7) +#define INCA_IP_IIC_IIC_SYSCON_2_IRQP (1 << 6) +#define INCA_IP_IIC_IIC_SYSCON_2_IRQD (1 << 5) +#define INCA_IP_IIC_IIC_SYSCON_2_BB (1 << 4) +#define INCA_IP_IIC_IIC_SYSCON_2_LRB (1 << 3) +#define INCA_IP_IIC_IIC_SYSCON_2_SLA (1 << 2) +#define INCA_IP_IIC_IIC_SYSCON_2_AL (1 << 1) +#define INCA_IP_IIC_IIC_SYSCON_2_ADR (1 << 0) + +/***I²C Write Hardware Modified System Control Register +***/ +#define INCA_IP_IIC_IIC_WHBSYSCON ((volatile u32*)(INCA_IP_IIC+ 0x0020)) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRWMEN (1 << 31) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETWMEN (1 << 30) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETSTP (1 << 26) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRSTP (1 << 25) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETTRX (1 << 24) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRTRX (1 << 23) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETACKDIS (1 << 22) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRACKDIS (1 << 21) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETBUM (1 << 20) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRBUM (1 << 19) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETRSC (1 << 17) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRSC (1 << 16) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETRMEN (1 << 15) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRMEN (1 << 14) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQE (1 << 10) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQP (1 << 9) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQD (1 << 8) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQE (1 << 7) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQP (1 << 6) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD (1 << 5) +#define INCA_IP_IIC_IIC_WHBSYSCON_SETAL (1 << 2) +#define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL (1 << 1) + +/***I²C Bus Control Register***/ +#define INCA_IP_IIC_IIC_BUSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) +#define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD (1 << 31) +#define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) +#define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value) (((( 1 << 10) - 1) & (value)) << 16) +#define INCA_IP_IIC_IIC_BUSCON_0_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value) (1 << value) + +#define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value) (1 << value) + + +/***I²C Bus Control Register***/ +#define INCA_IP_IIC_IIC_BUSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) +#define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD (1 << 31) +#define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) +#define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value) (((( 1 << 7) - 1) & (value)) << 17) +#define INCA_IP_IIC_IIC_BUSCON_1_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value) (1 << value) + +#define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value) (1 << value) + + +/***I²C Receive Transmit Buffer***/ +#define INCA_IP_IIC_IIC_RTB ((volatile u32*)(INCA_IP_IIC+ 0x0018)) +#define INCA_IP_IIC_IIC_RTB_RTB(value) (1 << value) + + +/***********************************************************************/ +/* Module : FB register address and bits */ +/***********************************************************************/ + +#define INCA_IP_FB (0xBF880000) +/***********************************************************************/ + + +/***FB Access Error Cause Register***/ +#define INCA_IP_FB_FB_ERRCAUSE ((volatile u32*)(INCA_IP_FB+ 0x0100)) +#define INCA_IP_FB_FB_ERRCAUSE_ERR (1 << 31) +#define INCA_IP_FB_FB_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) +#define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***FB Access Error Address Register***/ +#define INCA_IP_FB_FB_ERRADDR ((volatile u32*)(INCA_IP_FB+ 0x0108)) +#define INCA_IP_FB_FB_ERRADDR_ADDR + +/***FB Configuration Register***/ +#define INCA_IP_FB_FB_CFG ((volatile u32*)(INCA_IP_FB+ 0x0800)) +#define INCA_IP_FB_FB_CFG_SVM (1 << 0) + +/***********************************************************************/ +/* Module : SRAM register address and bits */ +/***********************************************************************/ + +#define INCA_IP_SRAM (0xBF980000) +/***********************************************************************/ + + +/***SRAM Size Register***/ +#define INCA_IP_SRAM_SRAM_SIZE ((volatile u32*)(INCA_IP_SRAM+ 0x0800)) +#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : BIU register address and bits */ +/***********************************************************************/ + +#define INCA_IP_BIU (0xBFA80000) +/***********************************************************************/ + + +/***BIU Identification Register***/ +#define INCA_IP_BIU_BIU_ID ((volatile u32*)(INCA_IP_BIU+ 0x0000)) +#define INCA_IP_BIU_BIU_ID_ARCH (1 << 16) +#define INCA_IP_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) +#define INCA_IP_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) + +/***BIU Access Error Cause Register***/ +#define INCA_IP_BIU_BIU_ERRCAUSE ((volatile u32*)(INCA_IP_BIU+ 0x0100)) +#define INCA_IP_BIU_BIU_ERRCAUSE_ERR (1 << 31) +#define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) +#define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) + +/***BIU Access Error Address Register***/ +#define INCA_IP_BIU_BIU_ERRADDR ((volatile u32*)(INCA_IP_BIU+ 0x0108)) +#define INCA_IP_BIU_BIU_ERRADDR_ADDR + +/***********************************************************************/ +/* Module : ICU register address and bits */ +/***********************************************************************/ + +#define INCA_IP_ICU (0xBF101000) +/***********************************************************************/ + + +/***IM0 Interrupt Status Register***/ +#define INCA_IP_ICU_IM0_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0000)) +#define INCA_IP_ICU_IM0_ISR_IR(value) (1 << value) + + +/***IM1 Interrupt Status Register***/ +#define INCA_IP_ICU_IM1_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0200)) +#define INCA_IP_ICU_IM1_ISR_IR(value) (1 << value) + + +/***IM2 Interrupt Status Register***/ +#define INCA_IP_ICU_IM2_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0400)) +#define INCA_IP_ICU_IM2_ISR_IR(value) (1 << value) + + +/***IM0 Interrupt Enable Register***/ +#define INCA_IP_ICU_IM0_IER ((volatile u32*)(INCA_IP_ICU+ 0x0008)) +#define INCA_IP_ICU_IM0_IER_IR(value) (1 << value) + + +/***IM1 Interrupt Enable Register***/ +#define INCA_IP_ICU_IM1_IER ((volatile u32*)(INCA_IP_ICU+ 0x0208)) +#define INCA_IP_ICU_IM1_IER_IR(value) (1 << value) + + +/***IM2 Interrupt Enable Register***/ +#define INCA_IP_ICU_IM2_IER ((volatile u32*)(INCA_IP_ICU+ 0x0408)) +#define INCA_IP_ICU_IM2_IER_IR(value) (1 << value) + + +/***IM0 Interrupt Output Status Register***/ +#define INCA_IP_ICU_IM0_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0010)) +#define INCA_IP_ICU_IM0_IOSR_IR(value) (1 << value) + + +/***IM1 Interrupt Output Status Register***/ +#define INCA_IP_ICU_IM1_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0210)) +#define INCA_IP_ICU_IM1_IOSR_IR(value) (1 << value) + + +/***IM2 Interrupt Output Status Register***/ +#define INCA_IP_ICU_IM2_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0410)) +#define INCA_IP_ICU_IM2_IOSR_IR(value) (1 << value) + + +/***IM0 Interrupt Request Set Register***/ +#define INCA_IP_ICU_IM0_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0018)) +#define INCA_IP_ICU_IM0_IRSR_IR(value) (1 << value) + + +/***IM1 Interrupt Request Set Register***/ +#define INCA_IP_ICU_IM1_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0218)) +#define INCA_IP_ICU_IM1_IRSR_IR(value) (1 << value) + + +/***IM2 Interrupt Request Set Register***/ +#define INCA_IP_ICU_IM2_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0418)) +#define INCA_IP_ICU_IM2_IRSR_IR(value) (1 << value) + + +/***External Interrupt Control Register***/ +#define INCA_IP_ICU_ICU_EICR ((volatile u32*)(INCA_IP_ICU+ 0x0B00)) +#define INCA_IP_ICU_ICU_EICR_EII5 (value) (((( 1 << 3) - 1) & (value)) << 20) +#define INCA_IP_ICU_ICU_EICR_EII4 (value) (((( 1 << 3) - 1) & (value)) << 16) +#define INCA_IP_ICU_ICU_EICR_EII3 (value) (((( 1 << 3) - 1) & (value)) << 12) +#define INCA_IP_ICU_ICU_EICR_EII2 (value) (((( 1 << 3) - 1) & (value)) << 8) +#define INCA_IP_ICU_ICU_EICR_EII1 (value) (((( 1 << 3) - 1) & (value)) << 4) +#define INCA_IP_ICU_ICU_EICR_EII0 (value) (((( 1 << 3) - 1) & (value)) << 0) diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h new file mode 100644 index 0000000..857fb03 --- /dev/null +++ b/include/asm-mips/io.h @@ -0,0 +1,450 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995 Waldorf GmbH + * Copyright (C) 1994 - 2000 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 FSMLabs, Inc. + */ +#ifndef _ASM_IO_H +#define _ASM_IO_H + +#include +#if 0 +#include +#endif +#include +#include + +/* + * Slowdown I/O port space accesses for antique hardware. + */ +#undef CONF_SLOWDOWN_IO + +/* + * Sane hardware offers swapping of I/O space accesses in hardware; less + * sane hardware forces software to fiddle with this ... + */ +#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__) + +#define __ioswab8(x) (x) +#define __ioswab16(x) swab16(x) +#define __ioswab32(x) swab32(x) + +#else + +#define __ioswab8(x) (x) +#define __ioswab16(x) (x) +#define __ioswab32(x) (x) + +#endif + +/* + * This file contains the definitions for the MIPS counterpart of the + * x86 in/out instructions. This heap of macros and C results in much + * better code than the approach of doing it in plain C. The macros + * result in code that is to fast for certain hardware. On the other + * side the performance of the string functions should be improved for + * sake of certain devices like EIDE disks that do highspeed polled I/O. + * + * Ralf + * + * This file contains the definitions for the x86 IO instructions + * inb/inw/inl/outb/outw/outl and the "string versions" of the same + * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" + * versions of the single-IO instructions (inb_p/inw_p/..). + * + * This file is not meant to be obfuscating: it's just complicated + * to (a) handle it all in a way that makes gcc able to optimize it + * as well as possible and (b) trying to avoid writing the same thing + * over and over again with slight variations and possibly making a + * mistake somewhere. + */ + +/* + * On MIPS I/O ports are memory mapped, so we access them using normal + * load/store instructions. mips_io_port_base is the virtual address to + * which all ports are being mapped. For sake of efficiency some code + * assumes that this is an address that can be loaded with a single lui + * instruction, so the lower 16 bits must be zero. Should be true on + * on any sane architecture; generic code does not use this assumption. + */ +extern unsigned long mips_io_port_base; + +/* + * Thanks to James van Artsdalen for a better timing-fix than + * the two short jumps: using outb's to a nonexistent port seems + * to guarantee better timings even on fast machines. + * + * On the other hand, I'd like to be sure of a non-existent port: + * I feel a bit unsafe about using 0x80 (should be safe, though) + * + * Linus + * + */ + +#define __SLOW_DOWN_IO \ + __asm__ __volatile__( \ + "sb\t$0,0x80(%0)" \ + : : "r" (mips_io_port_base)); + +#ifdef CONF_SLOWDOWN_IO +#ifdef REALLY_SLOW_IO +#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } +#else +#define SLOW_DOWN_IO __SLOW_DOWN_IO +#endif +#else +#define SLOW_DOWN_IO +#endif + +/* + * Change virtual addresses to physical addresses and vv. + * These are trivial on the 1:1 Linux/MIPS mapping + */ +extern inline unsigned long virt_to_phys(volatile void * address) +{ + return PHYSADDR(address); +} + +extern inline void * phys_to_virt(unsigned long address) +{ + return (void *)KSEG0ADDR(address); +} + +/* + * IO bus memory addresses are also 1:1 with the physical address + */ +extern inline unsigned long virt_to_bus(volatile void * address) +{ + return PHYSADDR(address); +} + +extern inline void * bus_to_virt(unsigned long address) +{ + return (void *)KSEG0ADDR(address); +} + +/* + * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped + * for the processor. + */ +extern unsigned long isa_slot_offset; + +extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); + +#if 0 +extern inline void *ioremap(unsigned long offset, unsigned long size) +{ + return __ioremap(offset, size, _CACHE_UNCACHED); +} + +extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) +{ + return __ioremap(offset, size, _CACHE_UNCACHED); +} + +extern void iounmap(void *addr); +#endif + +/* + * XXX We need system specific versions of these to handle EISA address bits + * 24-31 on SNI. + * XXX more SNI hacks. + */ +#define readb(addr) (*(volatile unsigned char *)(addr)) +#define readw(addr) __ioswab16((*(volatile unsigned short *)(addr))) +#define readl(addr) __ioswab32((*(volatile unsigned int *)(addr))) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl + +#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b) +#define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b)) +#define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b)) +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +/* END SNI HACKS ... */ + +/* + * ISA space is 'always mapped' on currently supported MIPS systems, no need + * to explicitly ioremap() it. The fact that the ISA IO space is mapped + * to PAGE_OFFSET is pure coincidence - it does not mean ISA values + * are physical addresses. The following constant pointer can be + * used as the IO-area pointer (it can be iounmapped as well, so the + * analogy with PCI is quite large): + */ +#define __ISA_IO_base ((char *)(PAGE_OFFSET)) + +#define isa_readb(a) readb(a) +#define isa_readw(a) readw(a) +#define isa_readl(a) readl(a) +#define isa_writeb(b,a) writeb(b,a) +#define isa_writew(w,a) writew(w,a) +#define isa_writel(l,a) writel(l,a) + +#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) +#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) + +/* + * We don't have csum_partial_copy_fromio() yet, so we cheat here and + * just copy it. The net code will then do the checksum later. + */ +#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) +#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d)) + +static inline int check_signature(unsigned long io_addr, + const unsigned char *signature, int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} +#define isa_check_signature(io, s, l) check_signature(i,s,l) + +/* + * Talk about misusing macros.. + */ + +#define __OUT1(s) \ +extern inline void __out##s(unsigned int value, unsigned int port) { + +#define __OUT2(m) \ +__asm__ __volatile__ ("s" #m "\t%0,%1(%2)" + +#define __OUT(m,s,w) \ +__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \ +__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \ +__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \ + SLOW_DOWN_IO; } \ +__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \ + SLOW_DOWN_IO; } + +#define __IN1(t,s) \ +extern __inline__ t __in##s(unsigned int port) { t _v; + +/* + * Required nops will be inserted by the assembler + */ +#define __IN2(m) \ +__asm__ __volatile__ ("l" #m "\t%0,%1(%2)" + +#define __IN(t,m,s,w) \ +__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \ +__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \ +__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \ +__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); } + +#define __INS1(s) \ +extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) { + +#define __INS2(m) \ +if (count) \ +__asm__ __volatile__ ( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n" \ + "1:\tl" #m "\t$1,%4(%5)\n\t" \ + "subu\t%1,1\n\t" \ + "s" #m "\t$1,(%0)\n\t" \ + "bne\t$0,%1,1b\n\t" \ + "addiu\t%0,%6\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" + +#define __INS(m,s,i) \ +__INS1(s) __INS2(m) \ + : "=r" (addr), "=r" (count) \ + : "0" (addr), "1" (count), "i" (0), \ + "r" (mips_io_port_base+port), "I" (i) \ + : "$1");} \ +__INS1(s##c) __INS2(m) \ + : "=r" (addr), "=r" (count) \ + : "0" (addr), "1" (count), "ir" (port), \ + "r" (mips_io_port_base), "I" (i) \ + : "$1");} + +#define __OUTS1(s) \ +extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) { + +#define __OUTS2(m) \ +if (count) \ +__asm__ __volatile__ ( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n" \ + "1:\tl" #m "\t$1,(%0)\n\t" \ + "subu\t%1,1\n\t" \ + "s" #m "\t$1,%4(%5)\n\t" \ + "bne\t$0,%1,1b\n\t" \ + "addiu\t%0,%6\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" + +#define __OUTS(m,s,i) \ +__OUTS1(s) __OUTS2(m) \ + : "=r" (addr), "=r" (count) \ + : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \ + : "$1");} \ +__OUTS1(s##c) __OUTS2(m) \ + : "=r" (addr), "=r" (count) \ + : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \ + : "$1");} + +__IN(unsigned char,b,b,8) +__IN(unsigned short,h,w,16) +__IN(unsigned int,w,l,32) + +__OUT(b,b,8) +__OUT(h,w,16) +__OUT(w,l,32) + +__INS(b,b,1) +__INS(h,w,2) +__INS(w,l,4) + +__OUTS(b,b,1) +__OUTS(h,w,2) +__OUTS(w,l,4) + + +/* + * Note that due to the way __builtin_constant_p() works, you + * - can't use it inside an inline function (it will never be true) + * - you don't have to worry about side effects within the __builtin.. + */ +#define outb(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outbc((val),(port)) : \ + __outb((val),(port))) + +#define inb(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inbc(port) : \ + __inb(port)) + +#define outb_p(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outbc_p((val),(port)) : \ + __outb_p((val),(port))) + +#define inb_p(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inbc_p(port) : \ + __inb_p(port)) + +#define outw(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outwc((val),(port)) : \ + __outw((val),(port))) + +#define inw(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inwc(port) : \ + __inw(port)) + +#define outw_p(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outwc_p((val),(port)) : \ + __outw_p((val),(port))) + +#define inw_p(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inwc_p(port) : \ + __inw_p(port)) + +#define outl(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outlc((val),(port)) : \ + __outl((val),(port))) + +#define inl(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inlc(port) : \ + __inl(port)) + +#define outl_p(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outlc_p((val),(port)) : \ + __outl_p((val),(port))) + +#define inl_p(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inlc_p(port) : \ + __inl_p(port)) + + +#define outsb(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outsbc((port),(addr),(count)) : \ + __outsb ((port),(addr),(count))) + +#define insb(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __insbc((port),(addr),(count)) : \ + __insb((port),(addr),(count))) + +#define outsw(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outswc((port),(addr),(count)) : \ + __outsw ((port),(addr),(count))) + +#define insw(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inswc((port),(addr),(count)) : \ + __insw((port),(addr),(count))) + +#define outsl(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outslc((port),(addr),(count)) : \ + __outsl ((port),(addr),(count))) + +#define insl(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inslc((port),(addr),(count)) : \ + __insl((port),(addr),(count))) + +#define IO_SPACE_LIMIT 0xffff + +/* + * The caches on some architectures aren't dma-coherent and have need to + * handle this in software. There are three types of operations that + * can be applied to dma buffers. + * + * - dma_cache_wback_inv(start, size) makes caches and coherent by + * writing the content of the caches back to memory, if necessary. + * The function also invalidates the affected part of the caches as + * necessary before DMA transfers from outside to memory. + * - dma_cache_wback(start, size) makes caches and coherent by + * writing the content of the caches back to memory, if necessary. + * The function also invalidates the affected part of the caches as + * necessary before DMA transfers from outside to memory. + * - dma_cache_inv(start, size) invalidates the affected parts of the + * caches. Dirty lines of the caches may be written back or simply + * be discarded. This operation is necessary before dma operations + * to the memory. + */ +extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); +extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); +extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); + +#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size) +#define dma_cache_wback(start,size) _dma_cache_wback(start,size) +#define dma_cache_inv(start,size) _dma_cache_inv(start,size) + +#endif /* _ASM_IO_H */ diff --git a/include/asm-mips/isadep.h b/include/asm-mips/isadep.h new file mode 100644 index 0000000..3cd1eb8 --- /dev/null +++ b/include/asm-mips/isadep.h @@ -0,0 +1,35 @@ +/* + * Various ISA level dependant constants. + * Most of the following constants reflect the different layout + * of Coprocessor 0 registers. + * + * Copyright (c) 1998 Harald Koerfgen + */ +#include + +#ifndef __ASM_ISADEP_H +#define __ASM_ISADEP_H + +#if defined(CONFIG_CPU_R3000) +/* + * R2000 or R3000 + */ + +/* + * kernel or user mode? (CP0_STATUS) + */ +#define KU_MASK 0x08 +#define KU_USER 0x08 +#define KU_KERN 0x00 + +#else +/* + * kernel or user mode? + */ +#define KU_MASK 0x18 +#define KU_USER 0x10 +#define KU_KERN 0x00 + +#endif + +#endif /* __ASM_ISADEP_H */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h new file mode 100644 index 0000000..0586c53 --- /dev/null +++ b/include/asm-mips/mipsregs.h @@ -0,0 +1,547 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * Copyright (C) 2000 Silicon Graphics, Inc. + * Modified for further R[236]000 support by Paul M. Antoine, 1996. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2003 Maciej W. Rozycki + */ +#ifndef _ASM_MIPSREGS_H +#define _ASM_MIPSREGS_H + +#if 0 +#include +#endif + +/* + * The following macros are especially useful for __asm__ + * inline assembler. + */ +#ifndef __STR +#define __STR(x) #x +#endif +#ifndef STR +#define STR(x) __STR(x) +#endif + +/* + * Coprocessor 0 register names + */ +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONF $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_INFO $7 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 + +/* + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... + */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 + +/* + * Coprocessor 0 Set 1 register names + */ +#define CP0_S1_DERRADDR0 $26 +#define CP0_S1_DERRADDR1 $27 +#define CP0_S1_INTCONTROL $20 +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_STATUS $31 + +/* + * FPU Status Register Values + */ +/* + * Status Register Values + */ + +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ + +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* rounding mode */ +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + + +/* + * Values for PageMask register + */ +#include +#ifdef CONFIG_CPU_VR41XX +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 +#else +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#endif + +/* + * Values used for computation of new tlb entries + */ +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 + +/* + * Macros to access the system control coprocessor + */ +#define read_32bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "mfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +#define read_32bit_cp0_set1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +/* + * For now use this only with interrupts disabled! + */ +#define read_64bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0,"STR(source)"\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res;}) + +#define write_32bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_32bit_cp0_set1_register(register,value) \ + __asm__ __volatile__( \ + "ctc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_64bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%0,"STR(register)"\n\t" \ + ".set\tmips0" \ + : : "r" (value)) + +/* + * This should be changed when we get a compiler that support the MIPS32 ISA. + */ +#define read_mips32_cp0_config1() \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ + __res;}) + +#define tlb_write_indexed() \ + __asm__ __volatile__( \ + ".set noreorder\n\t" \ + "tlbwi\n\t" \ +".set reorder") + +/* + * R4x00 interrupt enable / cause bits + */ +#define IE_SW0 (1<< 8) +#define IE_SW1 (1<< 9) +#define IE_IRQ0 (1<<10) +#define IE_IRQ1 (1<<11) +#define IE_IRQ2 (1<<12) +#define IE_IRQ3 (1<<13) +#define IE_IRQ4 (1<<14) +#define IE_IRQ5 (1<<15) + +/* + * R4x00 interrupt cause bits + */ +#define C_SW0 (1<< 8) +#define C_SW1 (1<< 9) +#define C_IRQ0 (1<<10) +#define C_IRQ1 (1<<11) +#define C_IRQ2 (1<<12) +#define C_IRQ3 (1<<13) +#define C_IRQ4 (1<<14) +#define C_IRQ5 (1<<15) + +#ifndef _LANGUAGE_ASSEMBLY +/* + * Manipulate the status register. + * Mostly used to access the interrupt bits. + */ +#define __BUILD_SET_CP0(name,register) \ +extern __inline__ unsigned int \ +set_cp0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res |= set; \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} \ + \ +extern __inline__ unsigned int \ +clear_cp0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res &= ~clear; \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} \ + \ +extern __inline__ unsigned int \ +change_cp0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res &= ~change; \ + res |= (new & change); \ + if(change) \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} + +__BUILD_SET_CP0(status,CP0_STATUS) +__BUILD_SET_CP0(cause,CP0_CAUSE) +__BUILD_SET_CP0(config,CP0_CONFIG) + +#endif /* defined (_LANGUAGE_ASSEMBLY) */ + +/* + * Bitfields in the R4xx0 cp0 status register + */ +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC 0x00000001 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 +/* bits 6 & 7 are reserved on R[23]000 */ +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM (1 << 4) +#define ST0_IL (1 << 23) +#define ST0_DL (1 << 24) + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Status register bits available in all MIPS CPUs. + */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (1 << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (1 << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (1 << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (1 << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (1 << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (1 << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (1 << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (1 << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (1 << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (1 << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (1 << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (1 << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (1 << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (1 << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (1 << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (1 << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ + +/* + * Bitfields and bit numbers in the coprocessor 0 cause register. + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (31 << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (255 << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (1 << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (1 << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (1 << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (1 << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (1 << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (1 << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (1 << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (1 << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (1 << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (3 << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (1 << 31) + +/* + * Bits in the coprozessor 0 config register. + */ +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_DB (1 << 4) +#define CONF_IB (1 << 5) +#define CONF_SC (1 << 17) +#define CONF_AC (1 << 23) +#define CONF_HALT (1 << 25) + +/* + * R10000 performance counter definitions. + * + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... + */ + +/* + * Events counted by counter #0 + */ +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 + +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 + +/* + * These flags define in which priviledge mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + +#endif /* _ASM_MIPSREGS_H */ diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h new file mode 100644 index 0000000..879aae2 --- /dev/null +++ b/include/asm-mips/posix_types.h @@ -0,0 +1,123 @@ +/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle + */ +#ifndef _ASM_POSIX_TYPES_H +#define _ASM_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned int __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned int __kernel_mode_t; +typedef int __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef int __kernel_ipc_pid_t; +typedef int __kernel_uid_t; +typedef int __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef long __kernel_daddr_t; +typedef char * __kernel_caddr_t; + +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef int __kernel_uid32_t; +typedef int __kernel_gid32_t; +typedef __kernel_uid_t __kernel_old_uid_t; +typedef __kernel_gid_t __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { + long val[2]; +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* _ASM_POSIX_TYPES_H */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h new file mode 100644 index 0000000..6838aee --- /dev/null +++ b/include/asm-mips/processor.h @@ -0,0 +1,283 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 Waldorf GMBH + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001 Ralf Baechle + * Copyright (C) 1996 Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#ifndef _ASM_PROCESSOR_H +#define _ASM_PROCESSOR_H + +#include + +#include + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#if !defined (_LANGUAGE_ASSEMBLY) +#if 0 +#include +#endif +#include +#include +#include +#include + +struct mips_cpuinfo { + unsigned long udelay_val; + unsigned long *pgd_quick; + unsigned long *pte_quick; + unsigned long pgtable_cache_sz; +}; + +/* + * System setup and hardware flags.. + * XXX: Should go into mips_cpuinfo. + */ +extern void (*cpu_wait)(void); /* only available on R4[26]00 and R3081 */ +extern void r3081_wait(void); +extern void r4k_wait(void); +extern char cyclecounter_available; /* only available from R4000 upwards. */ + +extern struct mips_cpuinfo boot_cpu_data; +extern unsigned int vced_count, vcei_count; + +#ifdef CONFIG_SMP +extern struct mips_cpuinfo cpu_data[]; +#define current_cpu_data cpu_data[smp_processor_id()] +#else +#define cpu_data &boot_cpu_data +#define current_cpu_data boot_cpu_data +#endif + +/* + * Bus types (default is ISA, but people can check others with these..) + * MCA_bus hardcoded to 0 for now. + * + * This needs to be extended since MIPS systems are being delivered with + * numerous different types of bus systems. + */ +extern int EISA_bus; +#define MCA_bus 0 +#define MCA_bus__is_a_macro /* for versions in ksyms.c */ + +/* + * MIPS has no problems with write protection + */ +#define wp_works_ok 1 +#define wp_works_ok__is_a_macro /* for versions in ksyms.c */ + +/* Lazy FPU handling on uni-processor */ +extern struct task_struct *last_task_used_math; + +/* + * User space process size: 2GB. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. TASK_SIZE + * for a 64 bit kernel expandable to 8192EB, of which the current MIPS + * implementations will "only" be able to use 1TB ... + */ +#define TASK_SIZE (0x7fff8000UL) + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Size of io_bitmap in longwords: 32 is ports 0-0x3ff. + */ +#define IO_BITMAP_SIZE 32 + +#define NUM_FPU_REGS 32 + +struct mips_fpu_hard_struct { + double fp_regs[NUM_FPU_REGS]; + unsigned int control; +}; + +/* + * It would be nice to add some more fields for emulator statistics, but there + * are a number of fixed offsets in offset.h and elsewhere that would have to + * be recalculated by hand. So the additional information will be private to + * the FPU emulator for now. See asm-mips/fpu_emulator.h. + */ +typedef u64 fpureg_t; +struct mips_fpu_soft_struct { + fpureg_t regs[NUM_FPU_REGS]; + unsigned int sr; +}; + +union mips_fpu_union { + struct mips_fpu_hard_struct hard; + struct mips_fpu_soft_struct soft; +}; + +#define INIT_FPU { \ + {{0,},} \ +} + +typedef struct { + unsigned long seg; +} mm_segment_t; + +/* + * If you change thread_struct remember to change the #defines below too! + */ +struct thread_struct { + /* Saved main processor registers. */ + unsigned long reg16; + unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; + unsigned long reg29, reg30, reg31; + + /* Saved cp0 stuff. */ + unsigned long cp0_status; + + /* Saved fpu/fpu emulator stuff. */ + union mips_fpu_union fpu; + + /* Other stuff associated with the thread. */ + unsigned long cp0_badvaddr; /* Last user fault */ + unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ + unsigned long error_code; + unsigned long trap_no; +#define MF_FIXADE 1 /* Fix address errors in software */ +#define MF_LOGADE 2 /* Log address errors to syslog */ + unsigned long mflags; + mm_segment_t current_ds; + unsigned long irix_trampoline; /* Wheee... */ + unsigned long irix_oldctx; + + /* + * These are really only needed if the full FPU emulator is configured. + * Would be made conditional on MIPS_FPU_EMULATOR if it weren't for the + * fact that having offset.h rebuilt differently for different config + * options would be asking for trouble. + * + * Saved EPC during delay-slot emulation (see math-emu/cp1emu.c) + */ + unsigned long dsemul_epc; + + /* + * Pointer to instruction used to induce address error + */ + unsigned long dsemul_aerpc; +}; + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +#define INIT_THREAD { \ + /* \ + * saved main processor registers \ + */ \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, \ + /* \ + * saved cp0 stuff \ + */ \ + 0, \ + /* \ + * saved fpu/fpu emulator stuff \ + */ \ + INIT_FPU, \ + /* \ + * Other stuff associated with the process \ + */ \ + 0, 0, 0, 0, \ + /* \ + * For now the default is to fix address errors \ + */ \ + MF_FIXADE, { 0 }, 0, 0, \ + /* \ + * dsemul_epc and dsemul_aerpc should never be used uninitialized, \ + * but... \ + */ \ + 0 ,0 \ +} + +#ifdef __KERNEL__ + +#define KERNEL_STACK_SIZE 8192 + +#if !defined (_LANGUAGE_ASSEMBLY) + +/* Free all resources held by a thread. */ +#define release_thread(thread) do { } while(0) + +extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); + +/* Copy and release all segment info associated with a VM */ +#define copy_segments(p, mm) do { } while(0) +#define release_segments(mm) do { } while(0) + +/* + * Return saved PC of a blocked thread. + */ +extern inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + extern void ret_from_fork(void); + + /* New born processes are a special case */ + if (t->reg31 == (unsigned long) ret_from_fork) + return t->reg31; + + return ((unsigned long *)t->reg29)[10]; +} + +/* + * Do necessary setup to start up a newly executed thread. + */ +#define start_thread(regs, new_pc, new_sp) do { \ + /* New thread looses kernel privileges. */ \ + regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KU_USER;\ + regs->cp0_epc = new_pc; \ + regs->regs[29] = new_sp; \ + current->thread.current_ds = USER_DS; \ +} while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs)) +#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32) +#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc))) +#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29]))) + +/* Allocation and freeing of basic task resources. */ +/* + * NOTE! The task struct and the stack go together + */ +#define THREAD_SIZE (2*PAGE_SIZE) +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +#define cpu_relax() do { } while (0) + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ +#endif /* __KERNEL__ */ + +/* + * Return_address is a replacement for __builtin_return_address(count) + * which on certain architectures cannot reasonably be implemented in GCC + * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). + * Note that __builtin_return_address(x>=1) is forbidden because GCC + * aborts compilation on some CPUs. It's simply not possible to unwind + * some CPU's stackframes. + * + * __builtin_return_address works only for non-leaf functions. We avoid the + * overhead of a function call by forcing the compiler to save the return + * address register on the stack. + */ +#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) + +#endif /* _ASM_PROCESSOR_H */ diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h new file mode 100644 index 0000000..2517adb --- /dev/null +++ b/include/asm-mips/ptrace.h @@ -0,0 +1,86 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle + * + * Machine dependent structs and defines to help the user use + * the ptrace system call. + */ +#ifndef _ASM_PTRACE_H +#define _ASM_PTRACE_H + +#include +#include + +/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ +#define FPR_BASE 32 +#define PC 64 +#define CAUSE 65 +#define BADVADDR 66 +#define MMHI 67 +#define MMLO 68 +#define FPC_CSR 69 +#define FPC_EIR 70 + +#ifndef _LANGUAGE_ASSEMBLY +/* + * This struct defines the way the registers are stored on the stack during a + * system call/exception. As usual the registers k0/k1 aren't being saved. + */ +struct pt_regs { + /* Pad bytes for argument save space on the stack. */ + unsigned long pad0[6]; + + /* Saved main processor registers. */ + unsigned long regs[32]; + + /* Other saved registers. */ + unsigned long lo; + unsigned long hi; + + /* + * saved cp0 registers + */ + unsigned long cp0_epc; + unsigned long cp0_badvaddr; + unsigned long cp0_status; + unsigned long cp0_cause; +}; + +#endif /* !(_LANGUAGE_ASSEMBLY) */ + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +/* #define PTRACE_GETREGS 12 */ +/* #define PTRACE_SETREGS 13 */ +/* #define PTRACE_GETFPREGS 14 */ +/* #define PTRACE_SETFPREGS 15 */ +/* #define PTRACE_GETFPXREGS 18 */ +/* #define PTRACE_SETFPXREGS 19 */ + +#define PTRACE_SETOPTIONS 21 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +#if 0 /* def _LANGUAGE_ASSEMBLY */ +#include +#endif + +#ifdef __KERNEL__ + +#ifndef _LANGUAGE_ASSEMBLY +/* + * Does the process account for user or for system time? + */ +#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) + +#define instruction_pointer(regs) ((regs)->cp0_epc) + +extern void show_regs(struct pt_regs *); +#endif /* !(_LANGUAGE_ASSEMBLY) */ + +#endif + +#endif /* _ASM_PTRACE_H */ diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h new file mode 100644 index 0000000..35505b7 --- /dev/null +++ b/include/asm-mips/reg.h @@ -0,0 +1,66 @@ +/* + * Various register offset definitions for debuggers, core file + * examiners and whatnot. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1999 by Ralf Baechle + */ +#ifndef __ASM_MIPS_REG_H +#define __ASM_MIPS_REG_H + +/* + * This defines/structures correspond to the register layout on stack - + * if the order here is changed, it needs to be updated in + * include/asm-mips/stackframe.h + */ +#define EF_REG0 6 +#define EF_REG1 7 +#define EF_REG2 8 +#define EF_REG3 9 +#define EF_REG4 10 +#define EF_REG5 11 +#define EF_REG6 12 +#define EF_REG7 13 +#define EF_REG8 14 +#define EF_REG9 15 +#define EF_REG10 16 +#define EF_REG11 17 +#define EF_REG12 18 +#define EF_REG13 19 +#define EF_REG14 20 +#define EF_REG15 21 +#define EF_REG16 22 +#define EF_REG17 23 +#define EF_REG18 24 +#define EF_REG19 25 +#define EF_REG20 26 +#define EF_REG21 27 +#define EF_REG22 28 +#define EF_REG23 29 +#define EF_REG24 30 +#define EF_REG25 31 +/* + * k0/k1 unsaved + */ +#define EF_REG28 34 +#define EF_REG29 35 +#define EF_REG30 36 +#define EF_REG31 37 + +/* + * Saved special registers + */ +#define EF_LO 38 +#define EF_HI 39 + +#define EF_CP0_EPC 40 +#define EF_CP0_BADVADDR 41 +#define EF_CP0_STATUS 42 +#define EF_CP0_CAUSE 44 + +#define EF_SIZE 180 /* size in bytes */ + +#endif /* __ASM_MIPS_REG_H */ diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h new file mode 100644 index 0000000..691d047 --- /dev/null +++ b/include/asm-mips/regdef.h @@ -0,0 +1,52 @@ +/* + * include/asm-mips/regdefs.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995 by Ralf Baechle + */ + +#ifndef __ASM_MIPS_REGDEF_H +#define __ASM_MIPS_REGDEF_H + +/* + * Symbolic register names for 32 bit ABI + */ +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ + +#endif /* __ASM_MIPS_REGDEF_H */ diff --git a/include/asm-mips/sgidefs.h b/include/asm-mips/sgidefs.h new file mode 100644 index 0000000..67f2658 --- /dev/null +++ b/include/asm-mips/sgidefs.h @@ -0,0 +1,44 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1999, 2001 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. + */ +#ifndef __ASM_SGIDEFS_H +#define __ASM_SGIDEFS_H + +/* + * Using a Linux compiler for building Linux seems logic but not to + * everybody. + */ +#if 0 /* ndef __linux__ */ +#error Use a Linux compiler or give up. +#endif + +/* + * Definitions for the ISA levels + * + * With the introduction of MIPS32 / MIPS64 instruction sets definitions + * MIPS ISAs are no longer subsets of each other. Therefore comparisons + * on these symbols except with == may result in unexpected results and + * are forbidden! + */ +#define _MIPS_ISA_MIPS1 1 +#define _MIPS_ISA_MIPS2 2 +#define _MIPS_ISA_MIPS3 3 +#define _MIPS_ISA_MIPS4 4 +#define _MIPS_ISA_MIPS5 5 +#define _MIPS_ISA_MIPS32 6 +#define _MIPS_ISA_MIPS64 7 + +/* + * Subprogram calling convention + */ +#define _MIPS_SIM_ABI32 1 +#define _MIPS_SIM_NABI32 2 +#define _MIPS_SIM_ABI64 3 + +#endif /* __ASM_SGIDEFS_H */ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h new file mode 100644 index 0000000..463a111 --- /dev/null +++ b/include/asm-mips/string.h @@ -0,0 +1,157 @@ +/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle + */ +#ifndef __ASM_MIPS_STRING_H +#define __ASM_MIPS_STRING_H + +#include + +#define __HAVE_ARCH_STRCPY +extern __inline__ char *strcpy(char *__dest, __const__ char *__src) +{ + char *__xdest = __dest; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tlbu\t$1,(%1)\n\t" + "addiu\t%1,1\n\t" + "sb\t$1,(%0)\n\t" + "bnez\t$1,1b\n\t" + "addiu\t%0,1\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (__dest), "=r" (__src) + : "0" (__dest), "1" (__src) + : "$1","memory"); + + return __xdest; +} + +#define __HAVE_ARCH_STRNCPY +extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) +{ + char *__xdest = __dest; + + if (__n == 0) + return __xdest; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tlbu\t$1,(%1)\n\t" + "subu\t%2,1\n\t" + "sb\t$1,(%0)\n\t" + "beqz\t$1,2f\n\t" + "addiu\t%0,1\n\t" + "bnez\t%2,1b\n\t" + "addiu\t%1,1\n" + "2:\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (__dest), "=r" (__src), "=r" (__n) + : "0" (__dest), "1" (__src), "2" (__n) + : "$1","memory"); + + return __dest; +} + +#define __HAVE_ARCH_STRCMP +extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) +{ + int __res; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "lbu\t%2,(%0)\n" + "1:\tlbu\t$1,(%1)\n\t" + "addiu\t%0,1\n\t" + "bne\t$1,%2,2f\n\t" + "addiu\t%1,1\n\t" + "bnez\t%2,1b\n\t" + "lbu\t%2,(%0)\n\t" +#if defined(CONFIG_CPU_R3000) + "nop\n\t" +#endif + "move\t%2,$1\n" + "2:\tsubu\t%2,$1\n" + "3:\t.set\tat\n\t" + ".set\treorder" + : "=r" (__cs), "=r" (__ct), "=r" (__res) + : "0" (__cs), "1" (__ct) + : "$1"); + + return __res; +} + +#define __HAVE_ARCH_STRNCMP +extern __inline__ int +strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) +{ + int __res; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tlbu\t%3,(%0)\n\t" + "beqz\t%2,2f\n\t" + "lbu\t$1,(%1)\n\t" + "subu\t%2,1\n\t" + "bne\t$1,%3,3f\n\t" + "addiu\t%0,1\n\t" + "bnez\t%3,1b\n\t" + "addiu\t%1,1\n" + "2:\n\t" +#if defined(CONFIG_CPU_R3000) + "nop\n\t" +#endif + "move\t%3,$1\n" + "3:\tsubu\t%3,$1\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res) + : "0" (__cs), "1" (__ct), "2" (__count) + : "$1"); + + return __res; +} + +#undef __HAVE_ARCH_MEMSET +extern void *memset(void *__s, int __c, size_t __count); + +#undef __HAVE_ARCH_MEMCPY +extern void *memcpy(void *__to, __const__ void *__from, size_t __n); + +#undef __HAVE_ARCH_MEMMOVE +extern void *memmove(void *__dest, __const__ void *__src, size_t __n); + +/* Don't build bcopy at all ... */ +#define __HAVE_ARCH_BCOPY + +#define __HAVE_ARCH_MEMSCAN +extern __inline__ void *memscan(void *__addr, int __c, size_t __size) +{ + char *__end = (char *)__addr + __size; + + __asm__(".set\tpush\n\t" + ".set\tnoat\n\t" + ".set\treorder\n\t" + "1:\tbeq\t%0,%1,2f\n\t" + "addiu\t%0,1\n\t" + "lb\t$1,-1(%0)\n\t" + "bne\t$1,%4,1b\n" + "2:\t.set\tpop" + : "=r" (__addr), "=r" (__end) + : "0" (__addr), "1" (__end), "r" (__c) + : "$1"); + + return __addr; +} + +#endif /* __ASM_MIPS_STRING_H */ diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h new file mode 100644 index 0000000..b6d50e2 --- /dev/null +++ b/include/asm-mips/system.h @@ -0,0 +1,268 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1994 - 1999 by Ralf Baechle + * + * Changed set_except_vector declaration to allow return of previous + * vector address value - necessary for "borrowing" vectors. + * + * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#ifndef _ASM_SYSTEM_H +#define _ASM_SYSTEM_H + +#include +#include +#include +#if 0 +#include +#endif + +extern __inline__ void +__sti(void) +{ + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\treorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1,$12\n\t" + "ori\t$1,0x1f\n\t" + "xori\t$1,0x1e\n\t" + "mtc0\t$1,$12\n\t" + ".set\tpop\n\t" + : /* no outputs */ + : /* no inputs */ + : "$1", "memory"); +} + +/* + * For cli() we have to insert nops to make shure that the new value + * has actually arrived in the status register before the end of this + * macro. + * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs + * no nops at all. + */ +extern __inline__ void +__cli(void) +{ + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\treorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1,$12\n\t" + "ori\t$1,1\n\t" + "xori\t$1,1\n\t" + ".set\tnoreorder\n\t" + "mtc0\t$1,$12\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + ".set\tpop\n\t" + : /* no outputs */ + : /* no inputs */ + : "$1", "memory"); +} + +#define __save_flags(x) \ +__asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "mfc0\t%0,$12\n\t" \ + ".set\tpop\n\t" \ + : "=r" (x)) + +#define __save_and_cli(x) \ +__asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + ".set\tnoat\n\t" \ + "mfc0\t%0,$12\n\t" \ + "ori\t$1,%0,1\n\t" \ + "xori\t$1,1\n\t" \ + ".set\tnoreorder\n\t" \ + "mtc0\t$1,$12\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + ".set\tpop\n\t" \ + : "=r" (x) \ + : /* no inputs */ \ + : "$1", "memory") + +#define __restore_flags(flags) \ +do { \ + unsigned long __tmp1; \ + \ + __asm__ __volatile__( \ + ".set\tnoreorder\t\t\t# __restore_flags\n\t" \ + ".set\tnoat\n\t" \ + "mfc0\t$1, $12\n\t" \ + "andi\t%0, 1\n\t" \ + "ori\t$1, 1\n\t" \ + "xori\t$1, 1\n\t" \ + "or\t%0, $1\n\t" \ + "mtc0\t%0, $12\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + : "=r" (__tmp1) \ + : "0" (flags) \ + : "$1", "memory"); \ +} while(0) + +#ifdef CONFIG_SMP + +extern void __global_sti(void); +extern void __global_cli(void); +extern unsigned long __global_save_flags(void); +extern void __global_restore_flags(unsigned long); +# define sti() __global_sti() +# define cli() __global_cli() +# define save_flags(x) do { x = __global_save_flags(); } while (0) +# define restore_flags(x) __global_restore_flags(x) +# define save_and_cli(x) do { save_flags(x); cli(); } while(0) + +#else /* Single processor */ + +# define sti() __sti() +# define cli() __cli() +# define save_flags(x) __save_flags(x) +# define save_and_cli(x) __save_and_cli(x) +# define restore_flags(x) __restore_flags(x) + +#endif /* SMP */ + +/* For spinlocks etc */ +#define local_irq_save(x) __save_and_cli(x); +#define local_irq_restore(x) __restore_flags(x); +#define local_irq_disable() __cli(); +#define local_irq_enable() __sti(); + +/* + * These are probably defined overly paranoid ... + */ +#ifdef CONFIG_CPU_HAS_WB + +#include +#define rmb() do { } while(0) +#define wmb() wbflush() +#define mb() wbflush() + +#else /* CONFIG_CPU_HAS_WB */ + +#define mb() \ +__asm__ __volatile__( \ + "# prevent instructions being moved around\n\t" \ + ".set\tnoreorder\n\t" \ + "# 8 nops to fool the R4400 pipeline\n\t" \ + "nop;nop;nop;nop;nop;nop;nop;nop\n\t" \ + ".set\treorder" \ + : /* no output */ \ + : /* no input */ \ + : "memory") +#define rmb() mb() +#define wmb() mb() + +#endif /* CONFIG_CPU_HAS_WB */ + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#endif + +#define set_mb(var, value) \ +do { var = value; mb(); } while (0) + +#define set_wmb(var, value) \ +do { var = value; wmb(); } while (0) + +#if !defined (_LANGUAGE_ASSEMBLY) +/* + * switch_to(n) should switch tasks to task nr n, first + * checking that n isn't the current task, in which case it does nothing. + */ +#if 0 +extern asmlinkage void *resume(void *last, void *next); +#endif +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +#define prepare_to_switch() do { } while(0) +#define switch_to(prev,next,last) \ +do { \ + (last) = resume(prev, next); \ +} while(0) + +/* + * For 32 and 64 bit operands we can take advantage of ll and sc. + * FIXME: This doesn't work for R3000 machines. + */ +extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) +{ +#ifdef CONFIG_CPU_HAS_LLSC + unsigned long dummy; + + __asm__ __volatile__( + ".set\tnoreorder\t\t\t# xchg_u32\n\t" + ".set\tnoat\n\t" + "ll\t%0, %3\n" + "1:\tmove\t$1, %2\n\t" + "sc\t$1, %1\n\t" + "beqzl\t$1, 1b\n\t" + " ll\t%0, %3\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (val), "=o" (*m), "=r" (dummy) + : "o" (*m), "2" (val) + : "memory"); + + return val; +#else + unsigned long flags, retval; + + save_flags(flags); + cli(); + retval = *m; + *m = val; + restore_flags(flags); + return retval; +#endif /* Processor-dependent optimization */ +} + +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define tas(ptr) (xchg((ptr),1)) + +static __inline__ unsigned long +__xchg(unsigned long x, volatile void * ptr, int size) +{ + switch (size) { + case 4: + return xchg_u32(ptr, x); + } + return x; +} + +extern void *set_except_vector(int n, void *addr); + +extern void __die(const char *, struct pt_regs *, const char *where, + unsigned long line) __attribute__((noreturn)); +extern void __die_if_kernel(const char *, struct pt_regs *, const char *where, + unsigned long line); + +#define die(msg, regs) \ + __die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) +#define die_if_kernel(msg, regs) \ + __die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) + +#endif /* _ASM_SYSTEM_H */ diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h new file mode 100644 index 0000000..e757e22 --- /dev/null +++ b/include/asm-mips/types.h @@ -0,0 +1,77 @@ +/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#ifndef _ASM_TYPES_H +#define _ASM_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if (_MIPS_SZLONG == 64) + +typedef __signed__ long __s64; +typedef unsigned long __u64; + +#else + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef __signed char s8; +typedef unsigned char u8; + +typedef __signed short s16; +typedef unsigned short u16; + +typedef __signed int s32; +typedef unsigned int u32; + +#if (_MIPS_SZLONG == 64) + +typedef __signed__ long s64; +typedef unsigned long u64; + +#else + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long s64; +typedef unsigned long long u64; +#endif + +#endif + +#define BITS_PER_LONG _MIPS_SZLONG + +typedef unsigned long dma_addr_t; + +#endif /* __KERNEL__ */ + +#endif /* _ASM_TYPES_H */ diff --git a/include/asm-mips/u-boot.h b/include/asm-mips/u-boot.h new file mode 100644 index 0000000..d1273a4 --- /dev/null +++ b/include/asm-mips/u-boot.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ +} bd_t; +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +#endif /* _U_BOOT_H_ */ diff --git a/include/asm-nios/bitops.h b/include/asm-nios/bitops.h new file mode 100644 index 0000000..7744212 --- /dev/null +++ b/include/asm-nios/bitops.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_NIOS_BITOPS_H_ +#define _ASM_NIOS_BITOPS_H_ + + +extern void set_bit(int nr, volatile void * a); +extern void clear_bit(int nr, volatile void * a); +extern int test_and_clear_bit(int nr, volatile void * a); +extern void change_bit(unsigned long nr, volatile void *addr); +extern int test_and_set_bit(int nr, volatile void * a); +extern int test_and_change_bit(int nr, volatile void * addr); +extern int test_bit(int nr, volatile void * a); +extern int ffs(int i); + +#endif /* _ASM_NIOS_BITOPS_H */ diff --git a/include/asm-nios/byteorder.h b/include/asm-nios/byteorder.h new file mode 100644 index 0000000..dc71021 --- /dev/null +++ b/include/asm-nios/byteorder.h @@ -0,0 +1,30 @@ +/* +* (C) Copyright 2003, Psyent Corporation +* Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef __ASM_NIOS_BYTEORDER_H +#define __ASM_NIOS_BYTEORDER_H + +#include +#include + +#endif diff --git a/include/asm-nios/cache.h b/include/asm-nios/cache.h new file mode 100644 index 0000000..3cdb703 --- /dev/null +++ b/include/asm-nios/cache.h @@ -0,0 +1 @@ +/*FIXME: Implement this! */ diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h new file mode 100644 index 0000000..fd11389 --- /dev/null +++ b/include/asm-nios/global_data.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS_GLOBALDATA_H +#define __ASM_NIOS_GLOBALDATA_H + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid */ +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + unsigned long post_log_word; /* Record POST activities */ + unsigned long post_init_f_time; /* When post_init_f started */ +#endif + void **jt; /* Standalone app jump table */ +} gd_t; + +/* flags */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("%g7") + +#endif /* __ASM_NIOS_GLOBALDATA_H */ diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h new file mode 100644 index 0000000..07499d9 --- /dev/null +++ b/include/asm-nios/io.h @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_NIOS_IO_H_ +#define __ASM_NIOS_IO_H_ + +#define readb(addr)\ + ({unsigned char val;\ + asm volatile( " pfxio 0 \n"\ + " ld %0, [%1] \n"\ + " ext8d %0, %1 \n"\ + :"=r"(val) : "r" (addr)); val;}) + +#define readw(addr)\ + ({unsigned short val;\ + asm volatile( " pfxio 0 \n"\ + " ld %0, [%1] \n"\ + " ext16d %0, %1 \n"\ + :"=r"(val) : "r" (addr)); val;}) + +#define readl(addr)\ + ({unsigned long val;\ + asm volatile( " pfxio 0 \n"\ + " ld %0, [%1] \n"\ + :"=r"(val) : "r" (addr)); val;}) + +#define writeb(addr,val)\ + asm volatile ( " fill8 %%r0, %1 \n"\ + " st8d [%0], %%r0 \n"\ + : : "r" (addr), "r" (val) : "r0") + +#define writew(addr,val)\ + asm volatile ( " fill16 %%r0, %1 \n"\ + " st16d [%0], %%r0 \n"\ + : : "r" (addr), "r" (val) : "r0") + +#define writel(addr,val)\ + asm volatile ( " st [%0], %1 \n"\ + : : "r" (addr), "r" (val)) + +#define inb(addr) readb(addr) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(val,addr) writeb(addr,val) +#define outw(val,addr) writew(addr,val) +#define outl(val,addr) writel(addr,val) + +static inline void insb (unsigned long port, void *dst, unsigned long count) +{ + unsigned char *p = dst; + while (count--) *p++ = inb (port); +} +static inline void insw (unsigned long port, void *dst, unsigned long count) +{ + unsigned short *p = dst; + while (count--) *p++ = inw (port); +} +static inline void insl (unsigned long port, void *dst, unsigned long count) +{ + unsigned long *p = dst; + while (count--) *p++ = inl (port); +} + +static inline void outsb (unsigned long port, const void *src, unsigned long count) +{ + const unsigned char *p = src; + while (count--) outb (*p++, port); +} + +static inline void outsw (unsigned long port, const void *src, unsigned long count) +{ + const unsigned short *p = src; + while (count--) outw (*p++, port); +} +static inline void outsl (unsigned long port, const void *src, unsigned long count) +{ + const unsigned long *p = src; + while (count--) outl (*p++, port); +} + +#endif /* __ASM_NIOS_IO_H_ */ diff --git a/include/asm-nios/posix_types.h b/include/asm-nios/posix_types.h new file mode 100644 index 0000000..eb74214 --- /dev/null +++ b/include/asm-nios/posix_types.h @@ -0,0 +1,63 @@ +#ifndef __ASM_NIOS_POSIX_TYPES_H +#define __ASM_NIOS_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned long __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) + +#undef __FD_CLR +#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) + +#undef __FD_ISSET +#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif diff --git a/include/asm-nios/processor.h b/include/asm-nios/processor.h new file mode 100644 index 0000000..78b8976 --- /dev/null +++ b/include/asm-nios/processor.h @@ -0,0 +1 @@ +/* FIXME: Implement this! */ diff --git a/include/asm-nios/psr.h b/include/asm-nios/psr.h new file mode 100644 index 0000000..6e8eba8 --- /dev/null +++ b/include/asm-nios/psr.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _NIOS_PSR_H +#define _NIOS_PSR_H + + +#endif /* _NIOS_PSR_H */ diff --git a/include/asm-nios/ptrace.h b/include/asm-nios/ptrace.h new file mode 100644 index 0000000..73754c8 --- /dev/null +++ b/include/asm-nios/ptrace.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _NIOS_PTRACE_H +#define _NIOS_PTRACE_H + +struct pt_regs { + unsigned global[8]; + unsigned in[8]; + unsigned status; + unsigned istatus; + unsigned retaddr; +}; + + +#endif /* _NIOS_PTRACE_H */ diff --git a/include/asm-nios/status_led.h b/include/asm-nios/status_led.h new file mode 100644 index 0000000..241c917 --- /dev/null +++ b/include/asm-nios/status_led.h @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * asm-nios/status_led.h + * + * NIOS PIO based status led support functions + */ + +#ifndef __ASM_STATUS_LED_H__ +#define __ASM_STATUS_LED_H__ + +#include + +/* led_id_t is unsigned int mask */ +typedef unsigned int led_id_t; + +#ifdef STATUS_LED_WRONLY /* emulate read access */ +static led_id_t __led_portval = 0; +#endif + +static inline void __led_init (led_id_t mask, int state) +{ + nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE; + +#ifdef STATUS_LED_WRONLY /* emulate read access */ + +#if (STATUS_LED_ACTIVE == 0) + if (state == STATUS_LED_ON) + __led_portval &= ~mask; + else + __led_portval |= mask; +#else + if (state == STATUS_LED_ON) + __led_portval |= mask; + else + __led_portval &= ~mask; +#endif + + piop->data = __led_portval; + +#else /* !STATUS_LED_WRONLY */ + +#if (STATUS_LED_ACTIVE == 0) + if (state == STATUS_LED_ON) + piop->data &= ~mask; + else + piop->data |= mask; +#else + if (state == STATUS_LED_ON) + piop->data |= mask; + else + piop->data &= ~mask; +#endif + + piop->direction |= mask; + +#endif /* STATUS_LED_WRONLY */ +} + +static inline void __led_toggle (led_id_t mask) +{ + nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE; + +#ifdef STATUS_LED_WRONLY /* emulate read access */ + + __led_portval ^= mask; + piop->data = __led_portval; + +#else /* !STATUS_LED_WRONLY */ + + piop->data ^= mask; + +#endif /* STATUS_LED_WRONLY */ +} + +static inline void __led_set (led_id_t mask, int state) +{ + nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE; + +#ifdef STATUS_LED_WRONLY /* emulate read access */ + +#if (STATUS_LED_ACTIVE == 0) + if (state == STATUS_LED_ON) + __led_portval &= ~mask; + else + __led_portval |= mask; +#else + if (state == STATUS_LED_ON) + __led_portval |= mask; + else + __led_portval &= ~mask; +#endif + + piop->data = __led_portval; + +#else /* !STATUS_LED_WRONLY */ + +#if (STATUS_LED_ACTIVE == 0) + if (state == STATUS_LED_ON) + piop->data &= ~mask; + else + piop->data |= mask; +#else + if (state == STATUS_LED_ON) + piop->data |= mask; + else + piop->data &= ~mask; +#endif + +#endif /* STATUS_LED_WRONLY */ +} + +#endif /* __ASM_STATUS_LED_H__ */ diff --git a/include/asm-nios/string.h b/include/asm-nios/string.h new file mode 100644 index 0000000..fa33275 --- /dev/null +++ b/include/asm-nios/string.h @@ -0,0 +1,25 @@ +#ifndef __ASM_NIOS_STRING_H +#define __ASM_NIOS_STRING_H + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMSET +extern void * memset(void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +extern void memzero(void *ptr, __kernel_size_t n); + +#endif diff --git a/include/asm-nios/system.h b/include/asm-nios/system.h new file mode 100644 index 0000000..9a9383d --- /dev/null +++ b/include/asm-nios/system.h @@ -0,0 +1,4 @@ +#ifndef _ASM_NIOS_SYSTEM_H_ +#define _ASM_NIOS_SYSTEM_H_ + +#endif /* _ASM_NIOS_SYSTEM_H */ diff --git a/include/asm-nios/types.h b/include/asm-nios/types.h new file mode 100644 index 0000000..43fd8f6 --- /dev/null +++ b/include/asm-nios/types.h @@ -0,0 +1,57 @@ +#ifndef _NIOS_TYPES_H +#define _NIOS_TYPES_H + +/* + * This file is never included by application software unless + * explicitly requested (e.g., via linux/types.h) in which case the + * application is Linux specific so (user-) name space pollution is + * not a major issue. However, for interoperability, libraries still + * need to be careful to avoid a name clashes. + */ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; +#endif /* __KERNEL__ */ + +#endif /* _NIOS_TYPES_H */ diff --git a/include/asm-nios/u-boot.h b/include/asm-nios/u-boot.h new file mode 100644 index 0000000..aae4be1 --- /dev/null +++ b/include/asm-nios/u-boot.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2003 + * Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_baudrate; /* Console Baudrate */ +} bd_t; + + +#endif /* _U_BOOT_H_ */ diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h new file mode 100644 index 0000000..e6c1a85 --- /dev/null +++ b/include/asm-nios2/bitops.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_BITOPS_H_ +#define __ASM_NIOS2_BITOPS_H_ + + +extern void set_bit(int nr, volatile void * a); +extern void clear_bit(int nr, volatile void * a); +extern int test_and_clear_bit(int nr, volatile void * a); +extern void change_bit(unsigned long nr, volatile void *addr); +extern int test_and_set_bit(int nr, volatile void * a); +extern int test_and_change_bit(int nr, volatile void * addr); +extern int test_bit(int nr, volatile void * a); +extern int ffs(int i); + +#endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-nios2/byteorder.h b/include/asm-nios2/byteorder.h new file mode 100644 index 0000000..495c823 --- /dev/null +++ b/include/asm-nios2/byteorder.h @@ -0,0 +1,30 @@ +/* +* (C) Copyright 2004, Psyent Corporation +* Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef __ASM_NIOS2_BYTEORDER_H_ +#define __ASM_NIOS2_BYTEORDER_H_ + +#include +#include + +#endif /* __ASM_NIOS2_BYTEORDER_H_ */ diff --git a/include/asm-nios2/cache.h b/include/asm-nios2/cache.h new file mode 100644 index 0000000..c78f343 --- /dev/null +++ b/include/asm-nios2/cache.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_CACHE_H_ +#define __ASM_NIOS2_CACHE_H_ + +extern void flush_dcache (unsigned long start, unsigned long size); +extern void flush_icache (unsigned long start, unsigned long size); + +#endif /* __ASM_NIOS2_CACHE_H_ */ diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h new file mode 100644 index 0000000..a1ac288 --- /dev/null +++ b/include/asm-nios2/global_data.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_NIOS2_GLOBALDATA_H_ +#define __ASM_NIOS2_GLOBALDATA_H_ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid */ +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + unsigned long post_log_word; /* Record POST activities */ + unsigned long post_init_f_time; /* When post_init_f started */ +#endif + void **jt; /* Standalone app jump table */ +} gd_t; + +/* flags */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r15") + +#endif /* __ASM_NIOS2_GLOBALDATA_H_ */ diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h new file mode 100644 index 0000000..b16a988 --- /dev/null +++ b/include/asm-nios2/io.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_IO_H_ +#define __ASM_NIOS2_IO_H_ + +#define sync() asm volatile ("sync" : : : "memory"); + +extern unsigned char inb (unsigned char *port); +extern unsigned short inw (unsigned short *port); +extern unsigned inl (unsigned port); + +#define readb(addr)\ + ({unsigned char val;\ + asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readw(addr)\ + ({unsigned short val;\ + asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readl(addr)\ + ({unsigned long val;\ + asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define writeb(addr,val)\ + asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val)) +#define writew(addr,val)\ + asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val)) +#define writel(addr,val)\ + asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val)) + +#define inb(addr) readb(addr) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(addr,val) writeb(addr,val) +#define outw(addr,val) writew(addr,val) +#define outl(addr,val) writel(addr,val) + +static inline void insb (unsigned long port, void *dst, unsigned long count) +{ + unsigned char *p = dst; + while (count--) *p++ = inb (port); +} +static inline void insw (unsigned long port, void *dst, unsigned long count) +{ + unsigned short *p = dst; + while (count--) *p++ = inw (port); +} +static inline void insl (unsigned long port, void *dst, unsigned long count) +{ + unsigned long *p = dst; + while (count--) *p++ = inl (port); +} + +static inline void outsb (unsigned long port, const void *src, unsigned long count) +{ + const unsigned char *p = src; + while (count--) outb (*p++, port); +} + +static inline void outsw (unsigned long port, const void *src, unsigned long count) +{ + const unsigned short *p = src; + while (count--) outw (*p++, port); +} +static inline void outsl (unsigned long port, const void *src, unsigned long count) +{ + const unsigned long *p = src; + while (count--) outl (*p++, port); +} + +#endif /* __ASM_NIOS2_IO_H_ */ diff --git a/include/asm-nios2/opcodes.h b/include/asm-nios2/opcodes.h new file mode 100644 index 0000000..211f8ba --- /dev/null +++ b/include/asm-nios2/opcodes.h @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_OPCODES_H_ +#define __ASM_NIOS2_OPCODES_H_ + +#define OPCODE_OP(inst) ((inst) & 0x3f) +#define OPCODE_OPX(inst) (((inst)>>11) & 0x3f) +#define OPCODE_RA(inst) (((inst)>>27) & 01f) +#define OPCODE_RB(inst) (((inst)>>22) & 01f) +#define OPCODE_RC(inst) (((inst)>>17) & 01f) + +/* I-TYPE (immediate) and J-TYPE (jump) opcodes + */ +#define OPCODE_CALL 0x00 +#define OPCODE_LDBU 0x03 +#define OPCODE_ADDI 0x04 +#define OPCODE_STB 0x05 +#define OPCODE_BR 0x06 +#define OPCODE_LDB 0x07 +#define OPCODE_CMPGEI 0x08 +#define OPCODE_LDHU 0x0B +#define OPCODE_ANDI 0x0C +#define OPCODE_STH 0x0D +#define OPCODE_BGE 0x0E +#define OPCODE_LDH 0x0F +#define OPCODE_CMPLTI 0x10 +#define OPCODE_XORI 0x1C +#define OPCODE_ORI 0x14 +#define OPCODE_STW 0x15 +#define OPCODE_BLT 0x16 +#define OPCODE_LDW 0x17 +#define OPCODE_CMPNEI 0x18 +#define OPCODE_BNE 0x1E +#define OPCODE_CMPEQI 0x20 +#define OPCODE_LDBUIO 0x23 +#define OPCODE_MULI 0x24 +#define OPCODE_STBIO 0x25 +#define OPCODE_BEQ 0x26 +#define OPCODE_LDBIO 0x27 +#define OPCODE_CMPGEUI 0x28 +#define OPCODE_ANDHI 0x2C +#define OPCODE_STHIO 0x2D +#define OPCODE_BGEU 0x2E +#define OPCODE_LDHIO 0x2F +#define OPCODE_CMPLTUI 0x30 +#define OPCODE_CUSTOM 0x32 +#define OPCODE_INITD 0x33 +#define OPCODE_ORHI 0x34 +#define OPCODE_STWIO 0x35 +#define OPCODE_BLTU 0x36 +#define OPCODE_LDWIO 0x37 +#define OPCODE_RTYPE 0x3A +#define OPCODE_LDHUIO 0x2B +#define OPCODE_FLUSHD 0x3B +#define OPCODE_XORHI 0x3C + +/* R-Type (register) OPX field encodings + */ +#define OPCODE_ERET 0x01 +#define OPCODE_ROLI 0x02 +#define OPCODE_ROL 0x03 +#define OPCODE_FLUSHP 0x04 +#define OPCODE_RET 0x05 +#define OPCODE_NOR 0x06 +#define OPCODE_MULXUU 0x07 +#define OPCODE_CMPGE 0x08 +#define OPCODE_BRET 0x09 +#define OPCODE_ROR 0x0B +#define OPCODE_FLUSHI 0x0C +#define OPCODE_JMP 0x0D +#define OPCODE_AND 0x0E + +#define OPCODE_CMPLT 0x10 +#define OPCODE_SLLI 0x12 +#define OPCODE_SLL 0x13 +#define OPCODE_OR 0x16 +#define OPCODE_MULXSU 0x17 +#define OPCODE_CMPNE 0x18 +#define OPCODE_SRLI 0x1A +#define OPCODE_SRL 0x1B +#define OPCODE_NEXTPC 0x1C +#define OPCODE_CALLR 0x1D +#define OPCODE_XOR 0x1E +#define OPCODE_MULXSS 0x1F + +#define OPCODE_CMPEQ 0x20 +#define OPCODE_CMPLTU 0x30 +#define OPCODE_ADD 0x31 +#define OPCODE_DIVU 0x24 +#define OPCODE_DIV 0x25 +#define OPCODE_RDCTL 0x26 +#define OPCODE_MUL 0x27 +#define OPCODE_CMPGEU 0x28 +#define OPCODE_TRAP 0x2D +#define OPCODE_WRCTL 0x2E + +#define OPCODE_BREAK 0x34 +#define OPCODE_SYNC 0x36 +#define OPCODE_INITI 0x29 +#define OPCODE_SUB 0x39 +#define OPCODE_SRAI 0x3A +#define OPCODE_SRA 0x3B + +/*Full instruction encodings for R-Type, without the R's ;-) + * + * TODO: BREAK, BRET, ERET, RET, SYNC (as needed) + */ +#define OPC_TRAP 0x003b683a + +#endif /* __ASM_NIOS2_OPCODES_H_ */ diff --git a/include/asm-nios2/posix_types.h b/include/asm-nios2/posix_types.h new file mode 100644 index 0000000..c2deea6 --- /dev/null +++ b/include/asm-nios2/posix_types.h @@ -0,0 +1,63 @@ +#ifndef __ASM_NIOS2_POSIX_TYPES_H_ +#define __ASM_NIOS2_POSIX_TYPES_H_ + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned long __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) + +#undef __FD_CLR +#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) + +#undef __FD_ISSET +#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* __ASM_NIOS2_POSIX_TYPES_H_ */ diff --git a/include/asm-nios2/processor.h b/include/asm-nios2/processor.h new file mode 100644 index 0000000..68502a5 --- /dev/null +++ b/include/asm-nios2/processor.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_PROCESSOR_H_ +#define __ASM_NIOS2_PROCESSOR_H_ +#endif /* __ASM_NIOS2_PROCESSOR_H_ */ diff --git a/include/asm-nios2/psr.h b/include/asm-nios2/psr.h new file mode 100644 index 0000000..a498b46 --- /dev/null +++ b/include/asm-nios2/psr.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_PSR_H_ +#define __ASM_NIOS2_PSR_H_ + + +#endif /* __ASM_NIOS2_PSR_H_ */ diff --git a/include/asm-nios2/ptrace.h b/include/asm-nios2/ptrace.h new file mode 100644 index 0000000..5430880 --- /dev/null +++ b/include/asm-nios2/ptrace.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_PTRACE_H_ +#define __ASM_NIOS2_PTRACE_H_ + +struct pt_regs { + unsigned reg[32]; + unsigned status; +}; + + +#endif /* __ASM_NIOS2_PTRACE_H_ */ diff --git a/include/asm-nios2/status_led.h b/include/asm-nios2/status_led.h new file mode 100644 index 0000000..20f8d90 --- /dev/null +++ b/include/asm-nios2/status_led.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_STATUS_LED_H__ +#define __ASM_STATUS_LED_H__ + +typedef unsigned led_id_t; +extern void __led_init (led_id_t mask, int state); +extern void __led_set (led_id_t mask, int state); +inline void __led_toggle (led_id_t mask); + +#endif /* __ASM_STATUS_LED_H__ */ diff --git a/include/asm-nios2/string.h b/include/asm-nios2/string.h new file mode 100644 index 0000000..e864903 --- /dev/null +++ b/include/asm-nios2/string.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_NIOS2_STRING_H_ +#define __ASM_NIOS2_STRING_H_ + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMSET +extern void * memset(void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +extern void memzero(void *ptr, __kernel_size_t n); + +#endif /* __ASM_NIOS2_STRING_H_ */ diff --git a/include/asm-nios2/system.h b/include/asm-nios2/system.h new file mode 100644 index 0000000..ec84f59 --- /dev/null +++ b/include/asm-nios2/system.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_NIOS2_SYSTEM_H_ +#define __ASM_NIOS2_SYSTEM_H_ + +#endif /* __ASM_NIOS2_SYSTEM_H */ diff --git a/include/asm-nios2/types.h b/include/asm-nios2/types.h new file mode 100644 index 0000000..39e2641 --- /dev/null +++ b/include/asm-nios2/types.h @@ -0,0 +1,57 @@ +#ifndef __ASM_NIOS2_TYPES_H_ +#define __ASM_NIOS2_TYPES_H_ + +/* + * This file is never included by application software unless + * explicitly requested (e.g., via linux/types.h) in which case the + * application is Linux specific so (user-) name space pollution is + * not a major issue. However, for interoperability, libraries still + * need to be careful to avoid a name clashes. + */ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; +#endif /* __KERNEL__ */ + +#endif /* __ASM_NIOS2_TYPES_H */ diff --git a/include/asm-nios2/u-boot.h b/include/asm-nios2/u-boot.h new file mode 100644 index 0000000..3f29962 --- /dev/null +++ b/include/asm-nios2/u-boot.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __ASM_NIOS2_U_BOOT_H_ +#define __ASM_NIOS2_U_BOOT_H_ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_baudrate; /* Console Baudrate */ +} bd_t; + + +#endif /* __ASM_NIOS2_U_BOOT_H_ */ diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h new file mode 100644 index 0000000..8e57057 --- /dev/null +++ b/include/asm-ppc/5xx_immap.h @@ -0,0 +1,439 @@ +/* + * (C) Copyright 2003 + * Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, + */ + +/* + * File: 5xx_immap.h + * + * Discription: MPC555 Internal Memory Map + * + */ + +#ifndef __IMMAP_5XX__ +#define __IMMAP_5XX__ + +/* System Configuration Registers. +*/ +typedef struct sys_conf { + uint sc_siumcr; + uint sc_sypcr; + char res1[6]; + ushort sc_swsr; + uint sc_sipend; + uint sc_simask; + uint sc_siel; + uint sc_sivec; + uint sc_tesr; + uint sc_sgpiodt1; + uint sc_sgpiodt2; + uint sc_sgpiocr; + uint sc_emcr; + uint sc_res1aa; + uint sc_res1ab; + uint sc_pdmcr; + char res3[192]; +} sysconf5xx_t; + + +/* Memory Controller Registers. +*/ +typedef struct mem_ctlr { + uint memc_br0; + uint memc_or0; + uint memc_br1; + uint memc_or1; + uint memc_br2; + uint memc_or2; + uint memc_br3; + uint memc_or3; + char res1[32]; + uint memc_dmbr; + uint memc_dmor; + char res2[48]; + ushort memc_mstat; + ushort memc_res4a; + char res3[132]; +} memctl5xx_t; + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + ushort sit_tbscr; + char res1[2]; + uint sit_tbref0; + uint sit_tbref1; + char res2[20]; + ushort sit_rtcsc; + char res3[2]; + uint sit_rtc; + uint sit_rtsec; + uint sit_rtcal; + char res4[16]; + ushort sit_piscr; + char res5[2]; + uint sit_pitc; + uint sit_pitr; + char res6[52]; +} sit5xx_t; + +/* Clocks and Reset +*/ +typedef struct clk_and_reset { + uint car_sccr; + uint car_plprcr; + ushort car_rsr; + ushort car_res7a; + ushort car_colir; + ushort car_res7b; + ushort car_vsrmcr; + ushort car_res7c; + char res1[108]; + +} car5xx_t; + +#define TBSCR_TBE ((ushort)0x0001) + +/* System Integration Timer Keys +*/ +typedef struct sitk { + uint sitk_tbscrk; + uint sitk_tbref0k; + uint sitk_tbref1k; + uint sitk_tbk; + char res1[16]; + uint sitk_rtcsck; + uint sitk_rtck; + uint sitk_rtseck; + uint sitk_rtcalk; + char res2[16]; + uint sitk_piscrk; + uint sitk_pitck; + char res3[56]; +} sitk5xx_t; + +/* Clocks and Reset Keys. +*/ +typedef struct cark { + uint cark_sccrk; + uint cark_plprcrk; + uint cark_rsrk; + char res1[1140]; +} cark8xx_t; + +/* The key to unlock registers maintained by keep-alive power. +*/ +#define KAPWR_KEY ((unsigned int)0x55ccaa33) + +/* Flash Configuration +*/ +typedef struct fl { + uint fl_cmfmcr; + uint fl_cmftst; + uint fl_cmfctl; + char res1[52]; +} fl5xx_t; + +/* Dpram Control +*/ +typedef struct dprc { + ushort dprc_dptmcr; + ushort dprc_ramtst; + ushort dprc_rambar; + ushort dprc_misrh; + ushort dprc_misrl; + ushort dprc_miscnt; +} dprc5xx_t; + +/* Time Processor Unit +*/ +typedef struct tpu { + ushort tpu_tpumcr; + ushort tpu_tcr; + ushort tpu_dscr; + ushort tpu_dssr; + ushort tpu_ticr; + ushort tpu_cier; + ushort tpu_cfsr0; + ushort tpu_cfsr1; + ushort tpu_cfsr2; + ushort tpu_cfsr3; + ushort tpu_hsqr0; + ushort tpu_hsqr1; + ushort tpu_hsrr0; + ushort tpu_hsrr1; + ushort tpu_cpr0; + ushort tpu_cpr1; + ushort tpu_cisr; + ushort tpu_lr; + ushort tpu_sglr; + ushort tpu_dcnr; + ushort tpu_tpumcr2; + ushort tpu_tpumcr3; + ushort tpu_isdr; + ushort tpu_iscr; + char res1[208]; + char tpu[16][16]; + char res2[512]; +} tpu5xx_t; + +/* QADC +*/ +typedef struct qadc { + ushort qadc_64mcr; + ushort qadc_64test; + ushort qadc_64int; + u_char qadc_portqa; + u_char qadc_portqb; + ushort qadc_ddrqa; + ushort qadc_qacr0; + ushort qadc_qacr1; + ushort qadc_qacr2; + ushort qadc_qasr0; + ushort qadc_qasr1; + char res1[492]; + /* command convertion word table */ + ushort qadc_ccw[64]; + /* result word table, unsigned right justified */ + ushort qadc_rjurr[64]; + /* result word table, signed left justified */ + ushort qadc_ljsrr[64]; + /* result word table, unsigned left justified */ + ushort qadc_ljurr[64]; +} qadc5xx_t; + +/* QSMCM +*/ +typedef struct qsmcm { + ushort qsmcm_qsmcr; + ushort qsmcm_qtest; + ushort qsmcm_qdsci_il; + ushort qsmcm_qspi_il; + ushort qsmcm_scc1r0; + ushort qsmcm_scc1r1; + ushort qsmcm_sc1sr; + ushort qsmcm_sc1dr; + char res1[2]; + char res2[2]; + ushort qsmcm_portqs; + u_char qsmcm_pqspar; + u_char qsmcm_ddrqs; + ushort qsmcm_spcr0; + ushort qsmcm_spcr1; + ushort qsmcm_spcr2; + u_char qsmcm_spcr3; + u_char qsmcm_spsr; + ushort qsmcm_scc2r0; + ushort qsmcm_scc2r1; + ushort qsmcm_sc2sr; + ushort qsmcm_sc2dr; + ushort qsmcm_qsci1cr; + ushort qsmcm_qsci1sr; + ushort qsmcm_sctq[16]; + ushort qsmcm_scrq[16]; + char res3[212]; + ushort qsmcm_recram[32]; + ushort qsmcm_tranram[32]; + u_char qsmcm_comdram[32]; + char res[3616]; +} qsmcm5xx_t; + + +/* MIOS +*/ + +typedef struct mios { + ushort mios_mpwmsm0perr; /* mpwmsm0 */ + ushort mios_mpwmsm0pulr; + ushort mios_mpwmsm0cntr; + ushort mios_mpwmsm0scr; + ushort mios_mpwmsm1perr; /* mpwmsm1 */ + ushort mios_mpwmsm1pulr; + ushort mios_mpwmsm1cntr; + ushort mios_mpwmsm1scr; + ushort mios_mpwmsm2perr; /* mpwmsm2 */ + ushort mios_mpwmsm2pulr; + ushort mios_mpwmsm2cntr; + ushort mios_mpwmsm2scr; + ushort mios_mpwmsm3perr; /* mpwmsm3 */ + ushort mios_mpwmsm3pulr; + ushort mios_mpwmsm3cntr; + ushort mios_mpwmsm3scr; + char res1[16]; + ushort mios_mmcsm6cnt; /* mmcsm6 */ + ushort mios_mmcsm6mlr; + ushort mios_mmcsm6scrd, mmcsm6scr; + char res2[32]; + ushort mios_mdasm11ar; /* mdasm11 */ + ushort mios_mdasm11br; + ushort mios_mdasm11scrd, mdasm11scr; + ushort mios_mdasm12ar; /* mdasm12 */ + ushort mios_mdasm12br; + ushort mios_mdasm12scrd, mdasm12scr; + ushort mios_mdasm13ar; /* mdasm13 */ + ushort mios_mdasm13br; + ushort mios_mdasm13scrd, mdasm13scr; + ushort mios_mdasm14ar; /* mdasm14 */ + ushort mios_mdasm14br; + ushort mios_mdasm14scrd, mdasm14scr; + ushort mios_mdasm15ar; /* mdasm15 */ + ushort mios_mdasm15br; + ushort mios_mdasm15scrd, mdasm15scr; + ushort mios_mpwmsm16perr; /* mpwmsm16 */ + ushort mios_mpwmsm16pulr; + ushort mios_mpwmsm16cntr; + ushort mios_mpwmsm16scr; + ushort mios_mpwmsm17perr; /* mpwmsm17 */ + ushort mios_mpwmsm17pulr; + ushort mios_mpwmsm17cntr; + ushort mios_mpwmsm17scr; + ushort mios_mpwmsm18perr; /* mpwmsm18 */ + ushort mios_mpwmsm18pulr; + ushort mios_mpwmsm18cntr; + ushort mios_mpwmsm18scr; + ushort mios_mpwmsm19perr; /* mpwmsm19 */ + ushort mios_mpwmsm19pulr; + ushort mios_mpwmsm19cntr; + ushort mios_mpwmsm19scr; + char res3[16]; + ushort mios_mmcsm22cnt; /* mmcsm22 */ + ushort mios_mmcsm22mlr; + ushort mios_mmcsm22scrd, mmcsm22scr; + char res4[32]; + ushort mios_mdasm27ar; /* mdasm27 */ + ushort mios_mdasm27br; + ushort mios_mdasm27scrd, mdasm27scr; + ushort mios_mdasm28ar; /*mdasm28 */ + ushort mios_mdasm28br; + ushort mios_mdasm28scrd, mdasm28scr; + ushort mios_mdasm29ar; /* mdasm29 */ + ushort mios_mdasm29br; + ushort mios_mdasm29scrd, mdasm29scr; + ushort mios_mdasm30ar; /* mdasm30 */ + ushort mios_mdasm30br; + ushort mios_mdasm30scrd, mdasm30scr; + ushort mios_mdasm31ar; /* mdasm31 */ + ushort mios_mdasm31br; + ushort mios_mdasm31scrd, mdasm31scr; + ushort mios_mpiosm32dr; + ushort mios_mpiosm32ddr; + char res5[1788]; + ushort mios_mios1tpcr; + char mios_res13[2]; + ushort mios_mios1vnr; + ushort mios_mios1mcr; + char res6[12]; + ushort mios_res42z; + ushort mios_mcpsmscr; + char res7[1000]; + ushort mios_mios1sr0; + char res12[2]; + ushort mios_mios1er0; + ushort mios_mios1rpr0; + char res8[40]; + ushort mios_mios1lvl0; + char res9[14]; + ushort mios_mios1sr1; + char res10[2]; + ushort mios_mios1er1; + ushort mios_mios1rpr1; + char res11[40]; + ushort mios_mios1lvl1; + char res13[1038]; +} mios5xx_t; + +/* Toucan Module +*/ +typedef struct tcan { + ushort tcan_tcnmcr; + ushort tcan_cantcr; + ushort tcan_canicr; + u_char tcan_canctrl0; + u_char tcan_canctrl1; + u_char tcan_presdiv; + u_char tcan_canctrl2; + ushort tcan_timer; + char res1[4]; + ushort tcan_rxgmskhi; + ushort tcan_rxgmsklo; + ushort tcan_rx14mskhi; + ushort tcan_rx14msklo; + ushort tcan_rx15mskhi; + ushort tcan_rx15msklo; + char res2[4]; + ushort tcan_estat; + ushort tcan_imask; + ushort tcan_iflag; + u_char tcan_rxectr; + u_char tcan_txectr; + char res3[88]; + struct { + ushort scr; + ushort id_high; + ushort id_low; + u_char data[8]; + char res4[2]; + } tcan_mbuff[16]; + char res5[640]; +} tcan5xx_t; + +/* UIMB +*/ +typedef struct uimb { + uint uimb_umcr; + char res1[12]; + uint uimb_utstcreg; + char res2[12]; + uint uimb_uipend; +} uimb5xx_t; + + +/* Internal Memory Map MPC555 +*/ +typedef struct immap { + char res1[262144]; /* CMF Flash A 256 Kbytes */ + char res2[196608]; /* CMF Flash B 192 Kbytes */ + char res3[2670592]; /* Reserved for Flash */ + sysconf5xx_t im_siu_conf; /* SIU Configuration */ + memctl5xx_t im_memctl; /* Memory Controller */ + sit5xx_t im_sit; /* System Integration Timers */ + car5xx_t im_clkrst; /* Clocks and Reset */ + sitk5xx_t im_sitk; /* System Integration Timer Keys*/ + cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ + fl5xx_t im_fla; /* Flash Module A */ + fl5xx_t im_flb; /* Flash Module B */ + char res4[14208]; /* Reserved for SIU */ + dprc5xx_t im_dprc; /* Dpram Control Register */ + char res5[8180]; /* Reserved */ + char dptram[6144]; /* Dptram */ + char res6[2048]; /* Reserved */ + tpu5xx_t im_tpua; /* Time Proessing Unit A */ + tpu5xx_t im_tpub; /* Time Processing Unit B */ + qadc5xx_t im_qadca; /* QADC A */ + qadc5xx_t im_qadcb; /* QADC B */ + qsmcm5xx_t im_qsmcm; /* SCI and SPI */ + mios5xx_t im_mios; /* MIOS */ + tcan5xx_t im_tcana; /* Toucan A */ + tcan5xx_t im_tcanb; /* Toucan B */ + char res7[1792]; /* Reserved */ + uimb5xx_t im_uimb; /* UIMB */ +} immap_t; + +#endif /* __IMMAP_5XX__ */ diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h new file mode 100644 index 0000000..40679cb --- /dev/null +++ b/include/asm-ppc/8xx_immap.h @@ -0,0 +1,511 @@ + +/* + * MPC8xx Internal Memory Map + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * The I/O on the MPC860 is comprised of blocks of special registers + * and the dual port ram for the Communication Processor Module. + * Within this space are functional units such as the SIU, memory + * controller, system timers, and other control functions. It is + * a combination that I found difficult to separate into logical + * functional files.....but anyone else is welcome to try. -- Dan + */ +#ifndef __IMMAP_8XX__ +#define __IMMAP_8XX__ + +/* System configuration registers. +*/ +typedef struct sys_conf { + uint sc_siumcr; + uint sc_sypcr; + uint sc_swt; + char res1[2]; + ushort sc_swsr; + uint sc_sipend; + uint sc_simask; + uint sc_siel; + uint sc_sivec; + uint sc_tesr; + char res2[0xc]; + uint sc_sdcr; + char res3[0x4c]; +} sysconf8xx_t; + +/* PCMCIA configuration registers. +*/ +typedef struct pcmcia_conf { + uint pcmc_pbr0; + uint pcmc_por0; + uint pcmc_pbr1; + uint pcmc_por1; + uint pcmc_pbr2; + uint pcmc_por2; + uint pcmc_pbr3; + uint pcmc_por3; + uint pcmc_pbr4; + uint pcmc_por4; + uint pcmc_pbr5; + uint pcmc_por5; + uint pcmc_pbr6; + uint pcmc_por6; + uint pcmc_pbr7; + uint pcmc_por7; + char res1[0x20]; + uint pcmc_pgcra; + uint pcmc_pgcrb; + uint pcmc_pscr; + char res2[4]; + uint pcmc_pipr; + char res3[4]; + uint pcmc_per; + char res4[4]; +} pcmconf8xx_t; + +/* Memory controller registers. +*/ +typedef struct mem_ctlr { + uint memc_br0; + uint memc_or0; + uint memc_br1; + uint memc_or1; + uint memc_br2; + uint memc_or2; + uint memc_br3; + uint memc_or3; + uint memc_br4; + uint memc_or4; + uint memc_br5; + uint memc_or5; + uint memc_br6; + uint memc_or6; + uint memc_br7; + uint memc_or7; + char res1[0x24]; + uint memc_mar; + uint memc_mcr; + char res2[4]; + uint memc_mamr; + uint memc_mbmr; + ushort memc_mstat; + ushort memc_mptpr; + uint memc_mdr; + char res3[0x80]; +} memctl8xx_t; + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + ushort sit_tbscr; + char res0[0x02]; + uint sit_tbreff0; + uint sit_tbreff1; + char res1[0x14]; + ushort sit_rtcsc; + char res2[0x02]; + uint sit_rtc; + uint sit_rtsec; + uint sit_rtcal; + char res3[0x10]; + ushort sit_piscr; + char res4[2]; + uint sit_pitc; + uint sit_pitr; + char res5[0x34]; +} sit8xx_t; + +#define TBSCR_TBIRQ_MASK ((ushort)0xff00) +#define TBSCR_REFA ((ushort)0x0080) +#define TBSCR_REFB ((ushort)0x0040) +#define TBSCR_REFAE ((ushort)0x0008) +#define TBSCR_REFBE ((ushort)0x0004) +#define TBSCR_TBF ((ushort)0x0002) +#define TBSCR_TBE ((ushort)0x0001) + +#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) +#define RTCSC_SEC ((ushort)0x0080) +#define RTCSC_ALR ((ushort)0x0040) +#define RTCSC_38K ((ushort)0x0010) +#define RTCSC_SIE ((ushort)0x0008) +#define RTCSC_ALE ((ushort)0x0004) +#define RTCSC_RTF ((ushort)0x0002) +#define RTCSC_RTE ((ushort)0x0001) + +#define PISCR_PIRQ_MASK ((ushort)0xff00) +#define PISCR_PS ((ushort)0x0080) +#define PISCR_PIE ((ushort)0x0004) +#define PISCR_PTF ((ushort)0x0002) +#define PISCR_PTE ((ushort)0x0001) + +/* Clocks and Reset. +*/ +typedef struct clk_and_reset { + uint car_sccr; + uint car_plprcr; + uint car_rsr; + char res[0x74]; /* Reserved area */ +} car8xx_t; + +/* System Integration Timers keys. +*/ +typedef struct sitk { + uint sitk_tbscrk; + uint sitk_tbreff0k; + uint sitk_tbreff1k; + uint sitk_tbk; + char res1[0x10]; + uint sitk_rtcsck; + uint sitk_rtck; + uint sitk_rtseck; + uint sitk_rtcalk; + char res2[0x10]; + uint sitk_piscrk; + uint sitk_pitck; + char res3[0x38]; +} sitk8xx_t; + +/* Clocks and reset keys. +*/ +typedef struct cark { + uint cark_sccrk; + uint cark_plprcrk; + uint cark_rsrk; + char res[0x474]; +} cark8xx_t; + +/* The key to unlock registers maintained by keep-alive power. +*/ +#define KAPWR_KEY ((unsigned int)0x55ccaa33) + +/* Video interface. MPC823 Only. +*/ +typedef struct vid823 { + ushort vid_vccr; + ushort res1; + u_char vid_vsr; + u_char res2; + u_char vid_vcmr; + u_char res3; + uint vid_vbcb; + uint res4; + uint vid_vfcr0; + uint vid_vfaa0; + uint vid_vfba0; + uint vid_vfcr1; + uint vid_vfaa1; + uint vid_vfba1; + u_char res5[0x18]; +} vid823_t; + +/* LCD interface. 823 Only. +*/ +typedef struct lcd { + uint lcd_lccr; + uint lcd_lchcr; + uint lcd_lcvcr; + char res1[4]; + uint lcd_lcfaa; + uint lcd_lcfba; + char lcd_lcsr; + char res2[0x7]; +} lcd823_t; + +/* I2C +*/ +typedef struct i2c { + u_char i2c_i2mod; + char res1[3]; + u_char i2c_i2add; + char res2[3]; + u_char i2c_i2brg; + char res3[3]; + u_char i2c_i2com; + char res4[3]; + u_char i2c_i2cer; + char res5[3]; + u_char i2c_i2cmr; + char res6[0x8b]; +} i2c8xx_t; + +/* DMA control/status registers. +*/ +typedef struct sdma_csr { + char res1[4]; + uint sdma_sdar; + u_char sdma_sdsr; + char res3[3]; + u_char sdma_sdmr; + char res4[3]; + u_char sdma_idsr1; + char res5[3]; + u_char sdma_idmr1; + char res6[3]; + u_char sdma_idsr2; + char res7[3]; + u_char sdma_idmr2; + char res8[0x13]; +} sdma8xx_t; + +/* Communication Processor Module Interrupt Controller. +*/ +typedef struct cpm_ic { + ushort cpic_civr; + char res[0xe]; + uint cpic_cicr; + uint cpic_cipr; + uint cpic_cimr; + uint cpic_cisr; +} cpic8xx_t; + +/* Input/Output Port control/status registers. +*/ +typedef struct io_port { + ushort iop_padir; + ushort iop_papar; + ushort iop_paodr; + ushort iop_padat; + char res1[8]; + ushort iop_pcdir; + ushort iop_pcpar; + ushort iop_pcso; + ushort iop_pcdat; + ushort iop_pcint; + char res2[6]; + ushort iop_pddir; + ushort iop_pdpar; + char res3[2]; + ushort iop_pddat; + uint utmode; + char res4[4]; +} iop8xx_t; + +/* Communication Processor Module Timers +*/ +typedef struct cpm_timers { + ushort cpmt_tgcr; + char res1[0xe]; + ushort cpmt_tmr1; + ushort cpmt_tmr2; + ushort cpmt_trr1; + ushort cpmt_trr2; + ushort cpmt_tcr1; + ushort cpmt_tcr2; + ushort cpmt_tcn1; + ushort cpmt_tcn2; + ushort cpmt_tmr3; + ushort cpmt_tmr4; + ushort cpmt_trr3; + ushort cpmt_trr4; + ushort cpmt_tcr3; + ushort cpmt_tcr4; + ushort cpmt_tcn3; + ushort cpmt_tcn4; + ushort cpmt_ter1; + ushort cpmt_ter2; + ushort cpmt_ter3; + ushort cpmt_ter4; + char res2[8]; +} cpmtimer8xx_t; + +/* Finally, the Communication Processor stuff..... +*/ +typedef struct scc { /* Serial communication channels */ + uint scc_gsmrl; + uint scc_gsmrh; + ushort scc_psmr; + char res1[2]; + ushort scc_todr; + ushort scc_dsr; + ushort scc_scce; + char res2[2]; + ushort scc_sccm; + char res3; + u_char scc_sccs; + char res4[8]; +} scc_t; + +typedef struct smc { /* Serial management channels */ + char res1[2]; + ushort smc_smcmr; + char res2[2]; + u_char smc_smce; + char res3[3]; + u_char smc_smcm; + char res4[5]; +} smc_t; + +/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but + * it fits within the address space. + */ + +typedef struct fec { + uint fec_addr_low; /* lower 32 bits of station address */ + ushort fec_addr_high; /* upper 16 bits of station address */ + ushort res1; /* reserved */ + uint fec_hash_table_high; /* upper 32-bits of hash table */ + uint fec_hash_table_low; /* lower 32-bits of hash table */ + uint fec_r_des_start; /* beginning of Rx descriptor ring */ + uint fec_x_des_start; /* beginning of Tx descriptor ring */ + uint fec_r_buff_size; /* Rx buffer size */ + uint res2[9]; /* reserved */ + uint fec_ecntrl; /* ethernet control register */ + uint fec_ievent; /* interrupt event register */ + uint fec_imask; /* interrupt mask register */ + uint fec_ivec; /* interrupt level and vector status */ + uint fec_r_des_active; /* Rx ring updated flag */ + uint fec_x_des_active; /* Tx ring updated flag */ + uint res3[10]; /* reserved */ + uint fec_mii_data; /* MII data register */ + uint fec_mii_speed; /* MII speed control register */ + uint res4[17]; /* reserved */ + uint fec_r_bound; /* end of RAM (read-only) */ + uint fec_r_fstart; /* Rx FIFO start address */ + uint res5[6]; /* reserved */ + uint fec_x_fstart; /* Tx FIFO start address */ + uint res6[17]; /* reserved */ + uint fec_fun_code; /* fec SDMA function code */ + uint res7[3]; /* reserved */ + uint fec_r_cntrl; /* Rx control register */ + uint fec_r_hash; /* Rx hash register */ + uint res8[14]; /* reserved */ + uint fec_x_cntrl; /* Tx control register */ + uint res9[0x1e]; /* reserved */ +} fec_t; + +/* The FEC and LCD color map share the same address space.... + * I guess we will never see an 823T :-). + */ +union fec_lcd { + fec_t fl_un_fec; + u_char fl_un_cmap[0x200]; +}; + +typedef struct comm_proc { + /* General control and status registers. + */ + ushort cp_cpcr; + u_char res1[2]; + ushort cp_rccr; + u_char res2; + u_char cp_rmds; + u_char res3[4]; + ushort cp_cpmcr1; + ushort cp_cpmcr2; + ushort cp_cpmcr3; + ushort cp_cpmcr4; + u_char res4[2]; + ushort cp_rter; + u_char res5[2]; + ushort cp_rtmr; + u_char res6[0x14]; + + /* Baud rate generators. + */ + uint cp_brgc1; + uint cp_brgc2; + uint cp_brgc3; + uint cp_brgc4; + + /* Serial Communication Channels. + */ + scc_t cp_scc[4]; + + /* Serial Management Channels. + */ + smc_t cp_smc[2]; + + /* Serial Peripheral Interface. + */ + ushort cp_spmode; + u_char res7[4]; + u_char cp_spie; + u_char res8[3]; + u_char cp_spim; + u_char res9[2]; + u_char cp_spcom; + u_char res10[2]; + + /* Parallel Interface Port. + */ + u_char res11[2]; + ushort cp_pipc; + u_char res12[2]; + ushort cp_ptpr; + uint cp_pbdir; + uint cp_pbpar; + u_char res13[2]; + ushort cp_pbodr; + uint cp_pbdat; + + /* Port E - MPC87x/88x only. + */ + uint cp_pedir; + uint cp_pepar; + uint cp_peso; + uint cp_peodr; + uint cp_pedat; + + /* Communications Processor Timing Register - + Contains RMII Timing for the FECs on MPC87x/88x only. + */ + uint cp_cptr; + + /* Serial Interface and Time Slot Assignment. + */ + uint cp_simode; + u_char cp_sigmr; + u_char res15; + u_char cp_sistr; + u_char cp_sicmr; + u_char res16[4]; + uint cp_sicr; + uint cp_sirp; + u_char res17[0xc]; + + /* 256 bytes of MPC823 video controller RAM array. + */ + u_char cp_vcram[0x100]; + u_char cp_siram[0x200]; + + /* The fast ethernet controller is not really part of the CPM, + * but it resides in the address space. + * The LCD color map is also here. + */ + union fec_lcd fl_un; +#define cp_fec fl_un.fl_un_fec +#define lcd_cmap fl_un.fl_un_cmap + char res18[0xE00]; + + /* The MPC885 family has a second FEC here */ + fec_t cp_fec2; +#define cp_fec1 cp_fec /* consistency macro */ + + /* Dual Ported RAM follows. + * There are many different formats for this memory area + * depending upon the devices used and options chosen. + * Some processors don't have all of it populated. + */ + u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ + u_char cp_dparam[0x400]; /* Parameter RAM */ +} cpm8xx_t; + +/* Internal memory map. +*/ +typedef struct immap { + sysconf8xx_t im_siu_conf; /* SIU Configuration */ + pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ + memctl8xx_t im_memctl; /* Memory Controller */ + sit8xx_t im_sit; /* System integration timers */ + car8xx_t im_clkrst; /* Clocks and reset */ + sitk8xx_t im_sitk; /* Sys int timer keys */ + cark8xx_t im_clkrstk; /* Clocks and reset keys */ + vid823_t im_vid; /* Video (823 only) */ + lcd823_t im_lcd; /* LCD (823 only) */ + i2c8xx_t im_i2c; /* I2C control/status */ + sdma8xx_t im_sdma; /* SDMA control/status */ + cpic8xx_t im_cpic; /* CPM Interrupt Controller */ + iop8xx_t im_ioport; /* IO Port control/status */ + cpmtimer8xx_t im_cpmtimer; /* CPM timers */ + cpm8xx_t im_cpm; /* Communication processor */ +} immap_t; + +#endif /* __IMMAP_8XX__ */ diff --git a/include/asm-ppc/atomic.h b/include/asm-ppc/atomic.h new file mode 100644 index 0000000..23f22df --- /dev/null +++ b/include/asm-ppc/atomic.h @@ -0,0 +1,95 @@ +/* + * PowerPC atomic operations + */ + +#ifndef _ASM_PPC_ATOMIC_H_ +#define _ASM_PPC_ATOMIC_H_ + +#include + +#ifdef CONFIG_SMP +typedef struct { volatile int counter; } atomic_t; +#else +typedef struct { int counter; } atomic_t; +#endif + +#define ATOMIC_INIT(i) { (i) } + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v,i) (((v)->counter) = (i)) + +extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); +extern void atomic_set_mask(unsigned long mask, unsigned long *addr); + +extern __inline__ int atomic_add_return(int a, atomic_t *v) +{ + int t; + + __asm__ __volatile__("\n\ +1: lwarx %0,0,%3\n\ + add %0,%2,%0\n\ + stwcx. %0,0,%3\n\ + bne- 1b" + : "=&r" (t), "=m" (*v) + : "r" (a), "r" (v), "m" (*v) + : "cc"); + + return t; +} + +extern __inline__ int atomic_sub_return(int a, atomic_t *v) +{ + int t; + + __asm__ __volatile__("\n\ +1: lwarx %0,0,%3\n\ + subf %0,%2,%0\n\ + stwcx. %0,0,%3\n\ + bne- 1b" + : "=&r" (t), "=m" (*v) + : "r" (a), "r" (v), "m" (*v) + : "cc"); + + return t; +} + +extern __inline__ int atomic_inc_return(atomic_t *v) +{ + int t; + + __asm__ __volatile__("\n\ +1: lwarx %0,0,%2\n\ + addic %0,%0,1\n\ + stwcx. %0,0,%2\n\ + bne- 1b" + : "=&r" (t), "=m" (*v) + : "r" (v), "m" (*v) + : "cc"); + + return t; +} + +extern __inline__ int atomic_dec_return(atomic_t *v) +{ + int t; + + __asm__ __volatile__("\n\ +1: lwarx %0,0,%2\n\ + addic %0,%0,-1\n\ + stwcx. %0,0,%2\n\ + bne 1b" + : "=&r" (t), "=m" (*v) + : "r" (v), "m" (*v) + : "cc"); + + return t; +} + +#define atomic_add(a, v) ((void) atomic_add_return((a), (v))) +#define atomic_sub(a, v) ((void) atomic_sub_return((a), (v))) +#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0) +#define atomic_inc(v) ((void) atomic_inc_return((v))) +#define atomic_dec(v) ((void) atomic_dec_return((v))) +#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0) + +#endif /* _ASM_PPC_ATOMIC_H_ */ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h new file mode 100644 index 0000000..3264915 --- /dev/null +++ b/include/asm-ppc/bitops.h @@ -0,0 +1,333 @@ +/* + * bitops.h: Bit string operations on the ppc + */ + +#ifndef _PPC_BITOPS_H +#define _PPC_BITOPS_H + +#include +#include + +extern void set_bit(int nr, volatile void *addr); +extern void clear_bit(int nr, volatile void *addr); +extern void change_bit(int nr, volatile void *addr); +extern int test_and_set_bit(int nr, volatile void *addr); +extern int test_and_clear_bit(int nr, volatile void *addr); +extern int test_and_change_bit(int nr, volatile void *addr); + +/* + * Arguably these bit operations don't imply any memory barrier or + * SMP ordering, but in fact a lot of drivers expect them to imply + * both, since they do on x86 cpus. + */ +#ifdef CONFIG_SMP +#define SMP_WMB "eieio\n" +#define SMP_MB "\nsync" +#else +#define SMP_WMB +#define SMP_MB +#endif /* CONFIG_SMP */ + +#define __INLINE_BITOPS 1 + +#if __INLINE_BITOPS +/* + * These used to be if'd out here because using : "cc" as a constraint + * resulted in errors from egcs. Things may be OK with gcc-2.95. + */ +extern __inline__ void set_bit(int nr, volatile void * addr) +{ + unsigned long old; + unsigned long mask = 1 << (nr & 0x1f); + unsigned long *p = ((unsigned long *)addr) + (nr >> 5); + + __asm__ __volatile__(SMP_WMB "\ +1: lwarx %0,0,%3\n\ + or %0,%0,%2\n\ + stwcx. %0,0,%3\n\ + bne 1b" + SMP_MB + : "=&r" (old), "=m" (*p) + : "r" (mask), "r" (p), "m" (*p) + : "cc" ); +} + +extern __inline__ void clear_bit(int nr, volatile void *addr) +{ + unsigned long old; + unsigned long mask = 1 << (nr & 0x1f); + unsigned long *p = ((unsigned long *)addr) + (nr >> 5); + + __asm__ __volatile__(SMP_WMB "\ +1: lwarx %0,0,%3\n\ + andc %0,%0,%2\n\ + stwcx. %0,0,%3\n\ + bne 1b" + SMP_MB + : "=&r" (old), "=m" (*p) + : "r" (mask), "r" (p), "m" (*p) + : "cc"); +} + +extern __inline__ void change_bit(int nr, volatile void *addr) +{ + unsigned long old; + unsigned long mask = 1 << (nr & 0x1f); + unsigned long *p = ((unsigned long *)addr) + (nr >> 5); + + __asm__ __volatile__(SMP_WMB "\ +1: lwarx %0,0,%3\n\ + xor %0,%0,%2\n\ + stwcx. %0,0,%3\n\ + bne 1b" + SMP_MB + : "=&r" (old), "=m" (*p) + : "r" (mask), "r" (p), "m" (*p) + : "cc"); +} + +extern __inline__ int test_and_set_bit(int nr, volatile void *addr) +{ + unsigned int old, t; + unsigned int mask = 1 << (nr & 0x1f); + volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); + + __asm__ __volatile__(SMP_WMB "\ +1: lwarx %0,0,%4\n\ + or %1,%0,%3\n\ + stwcx. %1,0,%4\n\ + bne 1b" + SMP_MB + : "=&r" (old), "=&r" (t), "=m" (*p) + : "r" (mask), "r" (p), "m" (*p) + : "cc"); + + return (old & mask) != 0; +} + +extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) +{ + unsigned int old, t; + unsigned int mask = 1 << (nr & 0x1f); + volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); + + __asm__ __volatile__(SMP_WMB "\ +1: lwarx %0,0,%4\n\ + andc %1,%0,%3\n\ + stwcx. %1,0,%4\n\ + bne 1b" + SMP_MB + : "=&r" (old), "=&r" (t), "=m" (*p) + : "r" (mask), "r" (p), "m" (*p) + : "cc"); + + return (old & mask) != 0; +} + +extern __inline__ int test_and_change_bit(int nr, volatile void *addr) +{ + unsigned int old, t; + unsigned int mask = 1 << (nr & 0x1f); + volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); + + __asm__ __volatile__(SMP_WMB "\ +1: lwarx %0,0,%4\n\ + xor %1,%0,%3\n\ + stwcx. %1,0,%4\n\ + bne 1b" + SMP_MB + : "=&r" (old), "=&r" (t), "=m" (*p) + : "r" (mask), "r" (p), "m" (*p) + : "cc"); + + return (old & mask) != 0; +} +#endif /* __INLINE_BITOPS */ + +extern __inline__ int test_bit(int nr, __const__ volatile void *addr) +{ + __const__ unsigned int *p = (__const__ unsigned int *) addr; + + return ((p[nr >> 5] >> (nr & 0x1f)) & 1) != 0; +} + +/* Return the bit position of the most significant 1 bit in a word */ +extern __inline__ int __ilog2(unsigned int x) +{ + int lz; + + asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x)); + return 31 - lz; +} + +extern __inline__ int ffz(unsigned int x) +{ + if ((x = ~x) == 0) + return 32; + return __ilog2(x & -x); +} + +#ifdef __KERNEL__ + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +extern __inline__ int ffs(int x) +{ + return __ilog2(x & -x) + 1; +} + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#endif /* __KERNEL__ */ + +/* + * This implementation of find_{first,next}_zero_bit was stolen from + * Linus' asm-alpha/bitops.h. + */ +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +extern __inline__ unsigned long find_next_zero_bit(void * addr, + unsigned long size, unsigned long offset) +{ + unsigned int * p = ((unsigned int *) addr) + (offset >> 5); + unsigned int result = offset & ~31UL; + unsigned int tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *p++; + tmp |= ~0UL >> (32-offset); + if (size < 32) + goto found_first; + if (tmp != ~0U) + goto found_middle; + size -= 32; + result += 32; + } + while (size >= 32) { + if ((tmp = *p++) != ~0U) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; +found_first: + tmp |= ~0UL << size; +found_middle: + return result + ffz(tmp); +} + + +#define _EXT2_HAVE_ASM_BITOPS_ + +#ifdef __KERNEL__ +/* + * test_and_{set,clear}_bit guarantee atomicity without + * disabling interrupts. + */ +#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 0x18, addr) +#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 0x18, addr) + +#else +extern __inline__ int ext2_set_bit(int nr, void * addr) +{ + int mask; + unsigned char *ADDR = (unsigned char *) addr; + int oldbit; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + oldbit = (*ADDR & mask) ? 1 : 0; + *ADDR |= mask; + return oldbit; +} + +extern __inline__ int ext2_clear_bit(int nr, void * addr) +{ + int mask; + unsigned char *ADDR = (unsigned char *) addr; + int oldbit; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + oldbit = (*ADDR & mask) ? 1 : 0; + *ADDR = *ADDR & ~mask; + return oldbit; +} +#endif /* __KERNEL__ */ + +extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) +{ + __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; + + return (ADDR[nr >> 3] >> (nr & 7)) & 1; +} + +/* + * This implementation of ext2_find_{first,next}_zero_bit was stolen from + * Linus' asm-alpha/bitops.h and modified for a big-endian machine. + */ + +#define ext2_find_first_zero_bit(addr, size) \ + ext2_find_next_zero_bit((addr), (size), 0) + +extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, + unsigned long size, unsigned long offset) +{ + unsigned int *p = ((unsigned int *) addr) + (offset >> 5); + unsigned int result = offset & ~31UL; + unsigned int tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = cpu_to_le32p(p++); + tmp |= ~0UL >> (32-offset); + if (size < 32) + goto found_first; + if (tmp != ~0U) + goto found_middle; + size -= 32; + result += 32; + } + while (size >= 32) { + if ((tmp = cpu_to_le32p(p++)) != ~0U) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = cpu_to_le32p(p); +found_first: + tmp |= ~0U << size; +found_middle: + return result + ffz(tmp); +} + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr) +#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr)) +#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size) + +#endif /* _PPC_BITOPS_H */ diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h new file mode 100644 index 0000000..3f5bcf6 --- /dev/null +++ b/include/asm-ppc/byteorder.h @@ -0,0 +1,84 @@ +#ifndef _PPC_BYTEORDER_H +#define _PPC_BYTEORDER_H + +#include + +#ifdef __GNUC__ + +extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) +{ + unsigned val; + + __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); + return val; +} + +extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) +{ + __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); +} + +extern __inline__ unsigned ld_le32(const volatile unsigned *addr) +{ + unsigned val; + + __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); + return val; +} + +extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) +{ + __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); +} + +/* alas, egcs sounds like it has a bug in this code that doesn't use the + inline asm correctly, and can cause file corruption. Until I hear that + it's fixed, I can live without the extra speed. I hope. */ +#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90) +#if 0 +# define __arch_swab16(x) ld_le16(&x) +# define __arch_swab32(x) ld_le32(&x) +#else +static __inline__ __attribute__((const)) __u16 ___arch__swab16(__u16 value) +{ + __u16 result; + + __asm__("rlwimi %0,%1,8,16,23" + : "=r" (result) + : "r" (value), "0" (value >> 8)); + return result; +} + +static __inline__ __attribute__((const)) __u32 ___arch__swab32(__u32 value) +{ + __u32 result; + + __asm__("rlwimi %0,%1,24,16,23\n\t" + "rlwimi %0,%1,8,8,15\n\t" + "rlwimi %0,%1,24,0,7" + : "=r" (result) + : "r" (value), "0" (value >> 24)); + return result; +} +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) +#endif /* 0 */ + +#endif + +/* The same, but returns converted value from the location pointer by addr. */ +#define __arch__swab16p(addr) ld_le16(addr) +#define __arch__swab32p(addr) ld_le32(addr) + +/* The same, but do the conversion in situ, ie. put the value back to addr. */ +#define __arch__swab16s(addr) st_le16(addr,*addr) +#define __arch__swab32s(addr) st_le32(addr,*addr) + +#endif /* __GNUC__ */ + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +#define __BYTEORDER_HAS_U64__ +#endif +#include + +#endif /* _PPC_BYTEORDER_H */ diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h new file mode 100644 index 0000000..5befab4 --- /dev/null +++ b/include/asm-ppc/cache.h @@ -0,0 +1,89 @@ +/* + * include/asm-ppc/cache.h + */ +#ifndef __ARCH_PPC_CACHE_H +#define __ARCH_PPC_CACHE_H + +#include +#include + +/* bytes per L1 cache line */ +#if !defined(CONFIG_8xx) || defined(CONFIG_8260) +#if defined(CONFIG_PPC64BRIDGE) +#define L1_CACHE_BYTES 128 +#else +#define L1_CACHE_BYTES 32 +#endif /* PPC64 */ +#else +#define L1_CACHE_BYTES 16 +#endif /* !8xx || 8260 */ + +#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) +#define L1_CACHE_PAGES 8 + +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +#ifdef MODULE +#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) +#else +#define __cacheline_aligned \ + __attribute__((__aligned__(L1_CACHE_BYTES), \ + __section__(".data.cacheline_aligned"))) +#endif + +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +extern void flush_dcache_range(unsigned long start, unsigned long stop); +extern void clean_dcache_range(unsigned long start, unsigned long stop); +extern void invalidate_dcache_range(unsigned long start, unsigned long stop); +#ifdef CFG_INIT_RAM_LOCK +extern void unlock_ram_in_cache(void); +#endif /* CFG_INIT_RAM_LOCK */ +#endif /* __ASSEMBLY__ */ + +/* prep registers for L2 */ +#define CACHECRBA 0x80000823 /* Cache configuration register address */ +#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ +#define L2CACHE_512KB 0x00 /* 512KB */ +#define L2CACHE_256KB 0x01 /* 256KB */ +#define L2CACHE_1MB 0x02 /* 1MB */ +#define L2CACHE_NONE 0x03 /* NONE */ +#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ + +#ifdef CONFIG_8xx +/* Cache control on the MPC8xx is provided through some additional + * special purpose registers. + */ +#define IC_CST 560 /* Instruction cache control/status */ +#define IC_ADR 561 /* Address needed for some commands */ +#define IC_DAT 562 /* Read-only data register */ +#define DC_CST 568 /* Data cache control/status */ +#define DC_ADR 569 /* Address needed for some commands */ +#define DC_DAT 570 /* Read-only data register */ + +/* Commands. Only the first few are available to the instruction cache. +*/ +#define IDC_ENABLE 0x02000000 /* Cache enable */ +#define IDC_DISABLE 0x04000000 /* Cache disable */ +#define IDC_LDLCK 0x06000000 /* Load and lock */ +#define IDC_UNLINE 0x08000000 /* Unlock line */ +#define IDC_UNALL 0x0a000000 /* Unlock all */ +#define IDC_INVALL 0x0c000000 /* Invalidate all */ + +#define DC_FLINE 0x0e000000 /* Flush data cache line */ +#define DC_SFWT 0x01000000 /* Set forced writethrough mode */ +#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ +#define DC_SLES 0x05000000 /* Set little endian swap mode */ +#define DC_CLES 0x07000000 /* Clear little endian swap mode */ + +/* Status. +*/ +#define IDC_ENABLED 0x80000000 /* Cache is enabled */ +#define IDC_CERR1 0x00200000 /* Cache error 1 */ +#define IDC_CERR2 0x00100000 /* Cache error 2 */ +#define IDC_CERR3 0x00080000 /* Cache error 3 */ + +#define DC_DFWT 0x40000000 /* Data cache is forced write through */ +#define DC_LES 0x20000000 /* Caches are little endian mode */ +#endif /* CONFIG_8xx */ + +#endif diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h new file mode 100644 index 0000000..2a9774a --- /dev/null +++ b/include/asm-ppc/cpm_8260.h @@ -0,0 +1,768 @@ + +/* + * MPC8260 Communication Processor Module. + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * + * This file contains structures and information for the communication + * processor channels found in the dual port RAM or parameter RAM. + * All CPM control and status is available through the MPC8260 internal + * memory map. See immap.h for details. + */ +#ifndef __CPM_82XX__ +#define __CPM_82XX__ + +#include + +/* CPM Command register. +*/ +#define CPM_CR_RST ((uint)0x80000000) +#define CPM_CR_PAGE ((uint)0x7c000000) +#define CPM_CR_SBLOCK ((uint)0x03e00000) +#define CPM_CR_FLG ((uint)0x00010000) +#define CPM_CR_MCN ((uint)0x00003fc0) +#define CPM_CR_OPCODE ((uint)0x0000000f) + +/* Device sub-block and page codes. +*/ +#define CPM_CR_SCC1_SBLOCK (0x04) +#define CPM_CR_SCC2_SBLOCK (0x05) +#define CPM_CR_SCC3_SBLOCK (0x06) +#define CPM_CR_SCC4_SBLOCK (0x07) +#define CPM_CR_SMC1_SBLOCK (0x08) +#define CPM_CR_SMC2_SBLOCK (0x09) +#define CPM_CR_SPI_SBLOCK (0x0a) +#define CPM_CR_I2C_SBLOCK (0x0b) +#define CPM_CR_TIMER_SBLOCK (0x0f) +#define CPM_CR_RAND_SBLOCK (0x0e) +#define CPM_CR_FCC1_SBLOCK (0x10) +#define CPM_CR_FCC2_SBLOCK (0x11) +#define CPM_CR_FCC3_SBLOCK (0x12) +#define CPM_CR_IDMA1_SBLOCK (0x14) +#define CPM_CR_IDMA2_SBLOCK (0x15) +#define CPM_CR_IDMA3_SBLOCK (0x16) +#define CPM_CR_IDMA4_SBLOCK (0x17) +#define CPM_CR_MCC1_SBLOCK (0x1c) + +#define CPM_CR_SCC1_PAGE (0x00) +#define CPM_CR_SCC2_PAGE (0x01) +#define CPM_CR_SCC3_PAGE (0x02) +#define CPM_CR_SCC4_PAGE (0x03) +#define CPM_CR_SMC1_PAGE (0x07) +#define CPM_CR_SMC2_PAGE (0x08) +#define CPM_CR_SPI_PAGE (0x09) +#define CPM_CR_I2C_PAGE (0x0a) +#define CPM_CR_TIMER_PAGE (0x0a) +#define CPM_CR_RAND_PAGE (0x0a) +#define CPM_CR_FCC1_PAGE (0x04) +#define CPM_CR_FCC2_PAGE (0x05) +#define CPM_CR_FCC3_PAGE (0x06) +#define CPM_CR_IDMA1_PAGE (0x07) +#define CPM_CR_IDMA2_PAGE (0x08) +#define CPM_CR_IDMA3_PAGE (0x09) +#define CPM_CR_IDMA4_PAGE (0x0a) +#define CPM_CR_MCC1_PAGE (0x07) +#define CPM_CR_MCC2_PAGE (0x08) + +/* Some opcodes (there are more...later) +*/ +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_INIT_RX ((ushort)0x0001) +#define CPM_CR_INIT_TX ((ushort)0x0002) +#define CPM_CR_HUNT_MODE ((ushort)0x0003) +#define CPM_CR_STOP_TX ((ushort)0x0004) +#define CPM_CR_RESTART_TX ((ushort)0x0006) +#define CPM_CR_SET_GADDR ((ushort)0x0008) + +#define mk_cr_cmd(PG, SBC, MCN, OP) \ + ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) + +/* Dual Port RAM addresses. The first 16K is available for almost + * any CPM use, so we put the BDs there. The first 128 bytes are + * used for SMC1 and SMC2 parameter RAM, so we start allocating + * BDs above that. All of this must change when we start + * downloading RAM microcode. + */ +#define CPM_DATAONLY_BASE ((uint)128) +#define CPM_DP_NOSPACE ((uint)0x7fffffff) +#ifndef CONFIG_MPC8272_FAMILY +#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) +#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) +#else /* 8247/48/71/72 */ +#define CPM_DATAONLY_SIZE ((uint)(4 * 1024) - CPM_DATAONLY_BASE) +#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) +#endif /* !CONFIG_MPC8272_FAMILY */ + +/* The number of pages of host memory we allocate for CPM. This is + * done early in kernel initialization to get physically contiguous + * pages. + */ +#define NUM_CPM_HOST_PAGES 2 + + +/* Export the base address of the communication processor registers + * and dual port ram. + */ +extern cpm8260_t *cpmp; /* Pointer to comm processor */ +uint m8260_cpm_dpalloc(uint size, uint align); +uint m8260_cpm_hostalloc(uint size, uint align); +void m8260_cpm_setbrg(uint brg, uint rate); +void m8260_cpm_fastbrg(uint brg, uint rate, int div16); +void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel); + +/* Buffer descriptors used by many of the CPM protocols. +*/ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001) /* ?? */ + +/* Function code bits, usually generic to devices. +*/ +#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ +#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ +#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ +#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ +#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ + +/* Parameter RAM offsets from the base. +*/ +#ifndef CFG_CPM_POST_WORD_ADDR +#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ +#else +#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR +#endif + +#ifndef CFG_CPM_BOOTCOUNT_ADDR +#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) +#else +#define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR +#endif + +#define PROFF_SCC1 ((uint)0x8000) +#define PROFF_SCC2 ((uint)0x8100) +#define PROFF_SCC3 ((uint)0x8200) +#define PROFF_SCC4 ((uint)0x8300) +#define PROFF_FCC1 ((uint)0x8400) +#define PROFF_FCC2 ((uint)0x8500) +#define PROFF_FCC3 ((uint)0x8600) +#define PROFF_MCC1 ((uint)0x8700) +#define PROFF_SMC1_BASE ((uint)0x87fc) +#define PROFF_IDMA1_BASE ((uint)0x87fe) +#define PROFF_MCC2 ((uint)0x8800) +#define PROFF_SMC2_BASE ((uint)0x88fc) +#define PROFF_IDMA2_BASE ((uint)0x88fe) +#define PROFF_SPI_BASE ((uint)0x89fc) +#define PROFF_IDMA3_BASE ((uint)0x89fe) +#define PROFF_TIMERS ((uint)0x8ae0) +#define PROFF_REVNUM ((uint)0x8af0) +#define PROFF_RAND ((uint)0x8af8) +#define PROFF_I2C_BASE ((uint)0x8afc) +#define PROFF_IDMA4_BASE ((uint)0x8afe) + +/* The SMCs are relocated to any of the first eight DPRAM pages. + * We will fix these at the first locations of DPRAM, until we + * get some microcode patches :-). + * The parameter ram space for the SMCs is fifty-some bytes, and + * they are required to start on a 64 byte boundary. + */ +#define PROFF_SMC1 (0) +#define PROFF_SMC2 (64) +#define PROFF_SPI ((16*1024) - 128) + +/* Define enough so I can at least use the serial port as a UART. + */ +typedef struct smc_uart { + ushort smc_rbase; /* Rx Buffer descriptor base address */ + ushort smc_tbase; /* Tx Buffer descriptor base address */ + u_char smc_rfcr; /* Rx function code */ + u_char smc_tfcr; /* Tx function code */ + ushort smc_mrblr; /* Max receive buffer length */ + uint smc_rstate; /* Internal */ + uint smc_idp; /* Internal */ + ushort smc_rbptr; /* Internal */ + ushort smc_ibc; /* Internal */ + uint smc_rxtmp; /* Internal */ + uint smc_tstate; /* Internal */ + uint smc_tdp; /* Internal */ + ushort smc_tbptr; /* Internal */ + ushort smc_tbc; /* Internal */ + uint smc_txtmp; /* Internal */ + ushort smc_maxidl; /* Maximum idle characters */ + ushort smc_tmpidl; /* Temporary idle counter */ + ushort smc_brklen; /* Last received break length */ + ushort smc_brkec; /* rcv'd break condition counter */ + ushort smc_brkcr; /* xmt break count register */ + ushort smc_rmask; /* Temporary bit mask */ + uint smc_stmp; /* SDMA Temp */ +} smc_uart_t; + +/* SMC uart mode register (Internal memory map). +*/ +#define SMCMR_REN ((ushort)0x0001) +#define SMCMR_TEN ((ushort)0x0002) +#define SMCMR_DM ((ushort)0x000c) +#define SMCMR_SM_GCI ((ushort)0x0000) +#define SMCMR_SM_UART ((ushort)0x0020) +#define SMCMR_SM_TRANS ((ushort)0x0030) +#define SMCMR_SM_MASK ((ushort)0x0030) +#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ +#define SMCMR_REVD SMCMR_PM_EVEN +#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ +#define SMCMR_BS SMCMR_PEN +#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ +#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ +#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) + +/* SMC Event and Mask register. +*/ +#define SMCM_TXE ((unsigned char)0x10) +#define SMCM_BSY ((unsigned char)0x04) +#define SMCM_TX ((unsigned char)0x02) +#define SMCM_RX ((unsigned char)0x01) + +/* Baud rate generators. +*/ +#define CPM_BRG_RST ((uint)0x00020000) +#define CPM_BRG_EN ((uint)0x00010000) +#define CPM_BRG_EXTC_INT ((uint)0x00000000) +#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) +#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) +#define CPM_BRG_ATB ((uint)0x00002000) +#define CPM_BRG_CD_MASK ((uint)0x00001ffe) +#define CPM_BRG_DIV16 ((uint)0x00000001) + +/* SCCs. +*/ +#define SCC_GSMRH_IRP ((uint)0x00040000) +#define SCC_GSMRH_GDE ((uint)0x00010000) +#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) +#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) +#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) +#define SCC_GSMRH_REVD ((uint)0x00002000) +#define SCC_GSMRH_TRX ((uint)0x00001000) +#define SCC_GSMRH_TTX ((uint)0x00000800) +#define SCC_GSMRH_CDP ((uint)0x00000400) +#define SCC_GSMRH_CTSP ((uint)0x00000200) +#define SCC_GSMRH_CDS ((uint)0x00000100) +#define SCC_GSMRH_CTSS ((uint)0x00000080) +#define SCC_GSMRH_TFL ((uint)0x00000040) +#define SCC_GSMRH_RFW ((uint)0x00000020) +#define SCC_GSMRH_TXSY ((uint)0x00000010) +#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) +#define SCC_GSMRH_SYNL8 ((uint)0x00000008) +#define SCC_GSMRH_SYNL4 ((uint)0x00000004) +#define SCC_GSMRH_RTSM ((uint)0x00000002) +#define SCC_GSMRH_RSYN ((uint)0x00000001) + +#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ +#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) +#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) +#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) +#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) +#define SCC_GSMRL_TCI ((uint)0x10000000) +#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) +#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) +#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) +#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) +#define SCC_GSMRL_RINV ((uint)0x02000000) +#define SCC_GSMRL_TINV ((uint)0x01000000) +#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) +#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) +#define SCC_GSMRL_TPL_48 ((uint)0x00800000) +#define SCC_GSMRL_TPL_32 ((uint)0x00600000) +#define SCC_GSMRL_TPL_16 ((uint)0x00400000) +#define SCC_GSMRL_TPL_8 ((uint)0x00200000) +#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) +#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) +#define SCC_GSMRL_TPP_01 ((uint)0x00100000) +#define SCC_GSMRL_TPP_10 ((uint)0x00080000) +#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) +#define SCC_GSMRL_TEND ((uint)0x00040000) +#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) +#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) +#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) +#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) +#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) +#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) +#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) +#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) +#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) +#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) +#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) +#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) +#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) +#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) +#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ +#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) +#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) +#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) +#define SCC_GSMRL_ENR ((uint)0x00000020) +#define SCC_GSMRL_ENT ((uint)0x00000010) +#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) +#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) +#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) +#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) +#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) +#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) +#define SCC_GSMRL_MODE_UART ((uint)0x00000004) +#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) +#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) +#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) + +#define SCC_TODR_TOD ((ushort)0x8000) + +/* SCC Event and Mask register. +*/ +#define SCCM_TXE ((unsigned char)0x10) +#define SCCM_BSY ((unsigned char)0x04) +#define SCCM_TX ((unsigned char)0x02) +#define SCCM_RX ((unsigned char)0x01) + +typedef struct scc_param { + ushort scc_rbase; /* Rx Buffer descriptor base address */ + ushort scc_tbase; /* Tx Buffer descriptor base address */ + u_char scc_rfcr; /* Rx function code */ + u_char scc_tfcr; /* Tx function code */ + ushort scc_mrblr; /* Max receive buffer length */ + uint scc_rstate; /* Internal */ + uint scc_idp; /* Internal */ + ushort scc_rbptr; /* Internal */ + ushort scc_ibc; /* Internal */ + uint scc_rxtmp; /* Internal */ + uint scc_tstate; /* Internal */ + uint scc_tdp; /* Internal */ + ushort scc_tbptr; /* Internal */ + ushort scc_tbc; /* Internal */ + uint scc_txtmp; /* Internal */ + uint scc_rcrc; /* Internal */ + uint scc_tcrc; /* Internal */ +} sccp_t; + +/* CPM Ethernet through SCC1. + */ +typedef struct scc_enet { + sccp_t sen_genscc; + uint sen_cpres; /* Preset CRC */ + uint sen_cmask; /* Constant mask for CRC */ + uint sen_crcec; /* CRC Error counter */ + uint sen_alec; /* alignment error counter */ + uint sen_disfc; /* discard frame counter */ + ushort sen_pads; /* Tx short frame pad character */ + ushort sen_retlim; /* Retry limit threshold */ + ushort sen_retcnt; /* Retry limit counter */ + ushort sen_maxflr; /* maximum frame length register */ + ushort sen_minflr; /* minimum frame length register */ + ushort sen_maxd1; /* maximum DMA1 length */ + ushort sen_maxd2; /* maximum DMA2 length */ + ushort sen_maxd; /* Rx max DMA */ + ushort sen_dmacnt; /* Rx DMA counter */ + ushort sen_maxb; /* Max BD byte count */ + ushort sen_gaddr1; /* Group address filter */ + ushort sen_gaddr2; + ushort sen_gaddr3; + ushort sen_gaddr4; + uint sen_tbuf0data0; /* Save area 0 - current frame */ + uint sen_tbuf0data1; /* Save area 1 - current frame */ + uint sen_tbuf0rba; /* Internal */ + uint sen_tbuf0crc; /* Internal */ + ushort sen_tbuf0bcnt; /* Internal */ + ushort sen_paddrh; /* physical address (MSB) */ + ushort sen_paddrm; + ushort sen_paddrl; /* physical address (LSB) */ + ushort sen_pper; /* persistence */ + ushort sen_rfbdptr; /* Rx first BD pointer */ + ushort sen_tfbdptr; /* Tx first BD pointer */ + ushort sen_tlbdptr; /* Tx last BD pointer */ + uint sen_tbuf1data0; /* Save area 0 - current frame */ + uint sen_tbuf1data1; /* Save area 1 - current frame */ + uint sen_tbuf1rba; /* Internal */ + uint sen_tbuf1crc; /* Internal */ + ushort sen_tbuf1bcnt; /* Internal */ + ushort sen_txlen; /* Tx Frame length counter */ + ushort sen_iaddr1; /* Individual address filter */ + ushort sen_iaddr2; + ushort sen_iaddr3; + ushort sen_iaddr4; + ushort sen_boffcnt; /* Backoff counter */ + + /* NOTE: Some versions of the manual have the following items + * incorrectly documented. Below is the proper order. + */ + ushort sen_taddrh; /* temp address (MSB) */ + ushort sen_taddrm; + ushort sen_taddrl; /* temp address (LSB) */ +} scc_enet_t; + + +/* SCC Event register as used by Ethernet. +*/ +#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ +#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* SCC Mode Register (PSMR) as used by Ethernet. +*/ +#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ + +/* Buffer descriptor control/status used by Ethernet receive. + * Common to SCC and FCC. + */ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ +#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. + * Common to SCC and FCC. + */ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/* SCC as UART +*/ +typedef struct scc_uart { + sccp_t scc_genscc; + uint scc_res1; /* Reserved */ + uint scc_res2; /* Reserved */ + ushort scc_maxidl; /* Maximum idle chars */ + ushort scc_idlc; /* temp idle counter */ + ushort scc_brkcr; /* Break count register */ + ushort scc_parec; /* receive parity error counter */ + ushort scc_frmec; /* receive framing error counter */ + ushort scc_nosec; /* receive noise counter */ + ushort scc_brkec; /* receive break condition counter */ + ushort scc_brkln; /* last received break length */ + ushort scc_uaddr1; /* UART address character 1 */ + ushort scc_uaddr2; /* UART address character 2 */ + ushort scc_rtemp; /* Temp storage */ + ushort scc_toseq; /* Transmit out of sequence char */ + ushort scc_char1; /* control character 1 */ + ushort scc_char2; /* control character 2 */ + ushort scc_char3; /* control character 3 */ + ushort scc_char4; /* control character 4 */ + ushort scc_char5; /* control character 5 */ + ushort scc_char6; /* control character 6 */ + ushort scc_char7; /* control character 7 */ + ushort scc_char8; /* control character 8 */ + ushort scc_rccm; /* receive control character mask */ + ushort scc_rccr; /* receive control character register */ + ushort scc_rlbc; /* receive last break character */ +} scc_uart_t; + +/* SCC Event and Mask registers when it is used as a UART. +*/ +#define UART_SCCM_GLR ((ushort)0x1000) +#define UART_SCCM_GLT ((ushort)0x0800) +#define UART_SCCM_AB ((ushort)0x0200) +#define UART_SCCM_IDL ((ushort)0x0100) +#define UART_SCCM_GRA ((ushort)0x0080) +#define UART_SCCM_BRKE ((ushort)0x0040) +#define UART_SCCM_BRKS ((ushort)0x0020) +#define UART_SCCM_CCR ((ushort)0x0008) +#define UART_SCCM_BSY ((ushort)0x0004) +#define UART_SCCM_TX ((ushort)0x0002) +#define UART_SCCM_RX ((ushort)0x0001) + +/* The SCC PSMR when used as a UART. +*/ +#define SCU_PSMR_FLC ((ushort)0x8000) +#define SCU_PSMR_SL ((ushort)0x4000) +#define SCU_PSMR_CL ((ushort)0x3000) +#define SCU_PSMR_UM ((ushort)0x0c00) +#define SCU_PSMR_FRZ ((ushort)0x0200) +#define SCU_PSMR_RZS ((ushort)0x0100) +#define SCU_PSMR_SYN ((ushort)0x0080) +#define SCU_PSMR_DRT ((ushort)0x0040) +#define SCU_PSMR_PEN ((ushort)0x0010) +#define SCU_PSMR_RPM ((ushort)0x000c) +#define SCU_PSMR_REVP ((ushort)0x0008) +#define SCU_PSMR_TPM ((ushort)0x0003) +#define SCU_PSMR_TEVP ((ushort)0x0003) + +/* CPM Transparent mode SCC. + */ +typedef struct scc_trans { + sccp_t st_genscc; + uint st_cpres; /* Preset CRC */ + uint st_cmask; /* Constant mask for CRC */ +} scc_trans_t; + +#define BD_SCC_TX_LAST ((ushort)0x0800) + +/* How about some FCCs..... +*/ +#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) +#define FCC_GFMR_DIAG_LE ((uint)0x40000000) +#define FCC_GFMR_DIAG_AE ((uint)0x80000000) +#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) +#define FCC_GFMR_TCI ((uint)0x20000000) +#define FCC_GFMR_TRX ((uint)0x10000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_CDP ((uint)0x04000000) +#define FCC_GFMR_CTSP ((uint)0x02000000) +#define FCC_GFMR_CDS ((uint)0x01000000) +#define FCC_GFMR_CTSS ((uint)0x00800000) +#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) +#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) +#define FCC_GFMR_SYNL_8 ((uint)0x00008000) +#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) +#define FCC_GFMR_RTSM ((uint)0x00002000) +#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) +#define FCC_GFMR_REVD ((uint)0x00000400) +#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) +#define FCC_GFMR_TCRC_16 ((uint)0x00000000) +#define FCC_GFMR_TCRC_32 ((uint)0x00000080) +#define FCC_GFMR_ENR ((uint)0x00000020) +#define FCC_GFMR_ENT ((uint)0x00000010) +#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) +#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) +#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) + +/* Generic FCC parameter ram. +*/ +typedef struct fcc_param { + ushort fcc_riptr; /* Rx Internal temp pointer */ + ushort fcc_tiptr; /* Tx Internal temp pointer */ + ushort fcc_res1; + ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ + uint fcc_rstate; /* Upper byte is Func code, must be set */ + uint fcc_rbase; /* Receive BD base */ + ushort fcc_rbdstat; /* RxBD status */ + ushort fcc_rbdlen; /* RxBD down counter */ + uint fcc_rdptr; /* RxBD internal data pointer */ + uint fcc_tstate; /* Upper byte is Func code, must be set */ + uint fcc_tbase; /* Transmit BD base */ + ushort fcc_tbdstat; /* TxBD status */ + ushort fcc_tbdlen; /* TxBD down counter */ + uint fcc_tdptr; /* TxBD internal data pointer */ + uint fcc_rbptr; /* Rx BD Internal buf pointer */ + uint fcc_tbptr; /* Tx BD Internal buf pointer */ + uint fcc_rcrc; /* Rx temp CRC */ + uint fcc_res2; + uint fcc_tcrc; /* Tx temp CRC */ +} fccp_t; + + +/* Ethernet controller through FCC. +*/ +typedef struct fcc_enet { + fccp_t fen_genfcc; + uint fen_statbuf; /* Internal status buffer */ + uint fen_camptr; /* CAM address */ + uint fen_cmask; /* Constant mask for CRC */ + uint fen_cpres; /* Preset CRC */ + uint fen_crcec; /* CRC Error counter */ + uint fen_alec; /* alignment error counter */ + uint fen_disfc; /* discard frame counter */ + ushort fen_retlim; /* Retry limit */ + ushort fen_retcnt; /* Retry counter */ + ushort fen_pper; /* Persistence */ + ushort fen_boffcnt; /* backoff counter */ + uint fen_gaddrh; /* Group address filter, high 32-bits */ + uint fen_gaddrl; /* Group address filter, low 32-bits */ + ushort fen_tfcstat; /* out of sequence TxBD */ + ushort fen_tfclen; + uint fen_tfcptr; + ushort fen_mflr; /* Maximum frame length (1518) */ + ushort fen_paddrh; /* MAC address */ + ushort fen_paddrm; + ushort fen_paddrl; + ushort fen_ibdcount; /* Internal BD counter */ + ushort fen_idbstart; /* Internal BD start pointer */ + ushort fen_ibdend; /* Internal BD end pointer */ + ushort fen_txlen; /* Internal Tx frame length counter */ + uint fen_ibdbase[8]; /* Internal use */ + uint fen_iaddrh; /* Individual address filter */ + uint fen_iaddrl; + ushort fen_minflr; /* Minimum frame length (64) */ + ushort fen_taddrh; /* Filter transfer MAC address */ + ushort fen_taddrm; + ushort fen_taddrl; + ushort fen_padptr; /* Pointer to pad byte buffer */ + ushort fen_cftype; /* control frame type */ + ushort fen_cfrange; /* control frame range */ + ushort fen_maxb; /* maximum BD count */ + ushort fen_maxd1; /* Max DMA1 length (1520) */ + ushort fen_maxd2; /* Max DMA2 length (1520) */ + ushort fen_maxd; /* internal max DMA count */ + ushort fen_dmacnt; /* internal DMA counter */ + uint fen_octc; /* Total octect counter */ + uint fen_colc; /* Total collision counter */ + uint fen_broc; /* Total broadcast packet counter */ + uint fen_mulc; /* Total multicast packet count */ + uint fen_uspc; /* Total packets < 64 bytes */ + uint fen_frgc; /* Total packets < 64 bytes with errors */ + uint fen_ospc; /* Total packets > 1518 */ + uint fen_jbrc; /* Total packets > 1518 with errors */ + uint fen_p64c; /* Total packets == 64 bytes */ + uint fen_p65c; /* Total packets 64 < bytes <= 127 */ + uint fen_p128c; /* Total packets 127 < bytes <= 255 */ + uint fen_p256c; /* Total packets 256 < bytes <= 511 */ + uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ + uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ + uint fen_cambuf; /* Internal CAM buffer poiner */ + ushort fen_rfthr; /* Received frames threshold */ + ushort fen_rfcnt; /* Received frames count */ +} fcc_enet_t; + +/* FCC Event/Mask register as used by Ethernet. +*/ +#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ +#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ +#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ +#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* FCC Mode Register (FPSMR) as used by Ethernet. +*/ +#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ +#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ +#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ +#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ +#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ +#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ +#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ +#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ +#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ +#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ +#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ +#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ +#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ +#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ + +/* IIC parameter RAM. +*/ +typedef struct iic { + ushort iic_rbase; /* Rx Buffer descriptor base address */ + ushort iic_tbase; /* Tx Buffer descriptor base address */ + u_char iic_rfcr; /* Rx function code */ + u_char iic_tfcr; /* Tx function code */ + ushort iic_mrblr; /* Max receive buffer length */ + uint iic_rstate; /* Internal */ + uint iic_rdp; /* Internal */ + ushort iic_rbptr; /* Internal */ + ushort iic_rbc; /* Internal */ + uint iic_rxtmp; /* Internal */ + uint iic_tstate; /* Internal */ + uint iic_tdp; /* Internal */ + ushort iic_tbptr; /* Internal */ + ushort iic_tbc; /* Internal */ + uint iic_txtmp; /* Internal */ +} iic_t; + +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; /* Tx temp. */ + uint spi_res1[4]; /* SDMA temp. */ +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) +#define SPMODE_PM(x) ((x) &0xF) + +/* SPI Event/Mask register. +*/ +#define SPI_EMASK 0x37 /* Event Mask */ +#define SPI_MME 0x20 /* Multi-Master Error */ +#define SPI_TXE 0x10 /* Transmit Error */ +#define SPI_BSY 0x04 /* Busy */ +#define SPI_TXB 0x02 /* Tx Buffer Empty */ +#define SPI_RXB 0x01 /* RX Buffer full/closed */ + +#define SPI_STR 0x80 /* SPCOM: Start transmit */ + +#define SPI_EB ((u_char)0x10) /* big endian byte order */ + +#define BD_IIC_START ((ushort)0x0400) + +#endif /* __CPM_82XX__ */ diff --git a/include/asm-ppc/cpm_85xx.h b/include/asm-ppc/cpm_85xx.h new file mode 100644 index 0000000..a74a3a1 --- /dev/null +++ b/include/asm-ppc/cpm_85xx.h @@ -0,0 +1,830 @@ + +/* + * MPC85xx Communication Processor Module + * Copyright (c) 2003,Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * + * MPC8260 Communication Processor Module. + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * + * This file contains structures and information for the communication + * processor channels found in the dual port RAM or parameter RAM. + * All CPM control and status is available through the MPC8260 internal + * memory map. See immap.h for details. + */ +#ifndef __CPM_85XX__ +#define __CPM_85XX__ + +#include + +/* CPM Command register. +*/ +#define CPM_CR_RST ((uint)0x80000000) +#define CPM_CR_PAGE ((uint)0x7c000000) +#define CPM_CR_SBLOCK ((uint)0x03e00000) +#define CPM_CR_FLG ((uint)0x00010000) +#define CPM_CR_MCN ((uint)0x00003fc0) +#define CPM_CR_OPCODE ((uint)0x0000000f) + +/* Device sub-block and page codes. +*/ +#define CPM_CR_SCC1_SBLOCK (0x04) +#define CPM_CR_SCC2_SBLOCK (0x05) +#define CPM_CR_SCC3_SBLOCK (0x06) +#define CPM_CR_SCC4_SBLOCK (0x07) +#define CPM_CR_SMC1_SBLOCK (0x08) +#define CPM_CR_SMC2_SBLOCK (0x09) +#define CPM_CR_SPI_SBLOCK (0x0a) +#define CPM_CR_I2C_SBLOCK (0x0b) +#define CPM_CR_TIMER_SBLOCK (0x0f) +#define CPM_CR_RAND_SBLOCK (0x0e) +#define CPM_CR_FCC1_SBLOCK (0x10) +#define CPM_CR_FCC2_SBLOCK (0x11) +#define CPM_CR_FCC3_SBLOCK (0x12) +#define CPM_CR_MCC1_SBLOCK (0x1c) + +#define CPM_CR_SCC1_PAGE (0x00) +#define CPM_CR_SCC2_PAGE (0x01) +#define CPM_CR_SCC3_PAGE (0x02) +#define CPM_CR_SCC4_PAGE (0x03) +#define CPM_CR_SPI_PAGE (0x09) +#define CPM_CR_I2C_PAGE (0x0a) +#define CPM_CR_TIMER_PAGE (0x0a) +#define CPM_CR_RAND_PAGE (0x0a) +#define CPM_CR_FCC1_PAGE (0x04) +#define CPM_CR_FCC2_PAGE (0x05) +#define CPM_CR_FCC3_PAGE (0x06) +#define CPM_CR_MCC1_PAGE (0x07) +#define CPM_CR_MCC2_PAGE (0x08) + +/* Some opcodes (there are more...later) +*/ +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_INIT_RX ((ushort)0x0001) +#define CPM_CR_INIT_TX ((ushort)0x0002) +#define CPM_CR_HUNT_MODE ((ushort)0x0003) +#define CPM_CR_STOP_TX ((ushort)0x0004) +#define CPM_CR_RESTART_TX ((ushort)0x0006) +#define CPM_CR_SET_GADDR ((ushort)0x0008) + +#define mk_cr_cmd(PG, SBC, MCN, OP) \ + ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) + +/* Dual Port RAM addresses. The first 16K is available for almost + * any CPM use, so we put the BDs there. The first 128 bytes are + * used for SMC1 and SMC2 parameter RAM, so we start allocating + * BDs above that. All of this must change when we start + * downloading RAM microcode. + */ +#define CPM_DATAONLY_BASE ((uint)128) +#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF) +#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) +#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) +#else /* MPC8540, MPC8560 */ +#define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000) +#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) +#endif + +/* The number of pages of host memory we allocate for CPM. This is + * done early in kernel initialization to get physically contiguous + * pages. + */ +#define NUM_CPM_HOST_PAGES 2 + +/* Export the base address of the communication processor registers + * and dual port ram. + */ +/*extern cpm8560_t *cpmp; Pointer to comm processor */ +uint m8560_cpm_dpalloc(uint size, uint align); +uint m8560_cpm_hostalloc(uint size, uint align); +void m8560_cpm_setbrg(uint brg, uint rate); +void m8560_cpm_fastbrg(uint brg, uint rate, int div16); +void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel); + +/* Buffer descriptors used by many of the CPM protocols. +*/ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001) /* ?? */ + +/* Function code bits, usually generic to devices. +*/ +#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ +#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ +#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ +#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ +#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ + +/* Parameter RAM offsets from the base. +*/ +#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ +#define PROFF_SCC1 ((uint)0x8000) +#define PROFF_SCC2 ((uint)0x8100) +#define PROFF_SCC3 ((uint)0x8200) +#define PROFF_SCC4 ((uint)0x8300) +#define PROFF_FCC1 ((uint)0x8400) +#define PROFF_FCC2 ((uint)0x8500) +#define PROFF_FCC3 ((uint)0x8600) +#define PROFF_MCC1 ((uint)0x8700) +#define PROFF_MCC2 ((uint)0x8800) +#define PROFF_SPI_BASE ((uint)0x89fc) +#define PROFF_TIMERS ((uint)0x8ae0) +#define PROFF_REVNUM ((uint)0x8af0) +#define PROFF_RAND ((uint)0x8af8) +#define PROFF_I2C_BASE ((uint)0x8afc) + +/* Baud rate generators. +*/ +#define CPM_BRG_RST ((uint)0x00020000) +#define CPM_BRG_EN ((uint)0x00010000) +#define CPM_BRG_EXTC_INT ((uint)0x00000000) +#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) +#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) +#define CPM_BRG_ATB ((uint)0x00002000) +#define CPM_BRG_CD_MASK ((uint)0x00001ffe) +#define CPM_BRG_DIV16 ((uint)0x00000001) + +/* SCCs. +*/ +#define SCC_GSMRH_IRP ((uint)0x00040000) +#define SCC_GSMRH_GDE ((uint)0x00010000) +#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) +#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) +#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) +#define SCC_GSMRH_REVD ((uint)0x00002000) +#define SCC_GSMRH_TRX ((uint)0x00001000) +#define SCC_GSMRH_TTX ((uint)0x00000800) +#define SCC_GSMRH_CDP ((uint)0x00000400) +#define SCC_GSMRH_CTSP ((uint)0x00000200) +#define SCC_GSMRH_CDS ((uint)0x00000100) +#define SCC_GSMRH_CTSS ((uint)0x00000080) +#define SCC_GSMRH_TFL ((uint)0x00000040) +#define SCC_GSMRH_RFW ((uint)0x00000020) +#define SCC_GSMRH_TXSY ((uint)0x00000010) +#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) +#define SCC_GSMRH_SYNL8 ((uint)0x00000008) +#define SCC_GSMRH_SYNL4 ((uint)0x00000004) +#define SCC_GSMRH_RTSM ((uint)0x00000002) +#define SCC_GSMRH_RSYN ((uint)0x00000001) + +#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ +#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) +#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) +#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) +#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) +#define SCC_GSMRL_TCI ((uint)0x10000000) +#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) +#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) +#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) +#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) +#define SCC_GSMRL_RINV ((uint)0x02000000) +#define SCC_GSMRL_TINV ((uint)0x01000000) +#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) +#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) +#define SCC_GSMRL_TPL_48 ((uint)0x00800000) +#define SCC_GSMRL_TPL_32 ((uint)0x00600000) +#define SCC_GSMRL_TPL_16 ((uint)0x00400000) +#define SCC_GSMRL_TPL_8 ((uint)0x00200000) +#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) +#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) +#define SCC_GSMRL_TPP_01 ((uint)0x00100000) +#define SCC_GSMRL_TPP_10 ((uint)0x00080000) +#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) +#define SCC_GSMRL_TEND ((uint)0x00040000) +#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) +#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) +#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) +#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) +#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) +#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) +#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) +#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) +#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) +#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) +#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) +#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) +#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) +#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) +#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ +#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) +#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) +#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) +#define SCC_GSMRL_ENR ((uint)0x00000020) +#define SCC_GSMRL_ENT ((uint)0x00000010) +#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) +#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) +#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) +#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) +#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) +#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) +#define SCC_GSMRL_MODE_UART ((uint)0x00000004) +#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) +#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) +#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) + +#define SCC_TODR_TOD ((ushort)0x8000) + +/* SCC Event and Mask register. +*/ +#define SCCM_TXE ((unsigned char)0x10) +#define SCCM_BSY ((unsigned char)0x04) +#define SCCM_TX ((unsigned char)0x02) +#define SCCM_RX ((unsigned char)0x01) + +typedef struct scc_param { + ushort scc_rbase; /* Rx Buffer descriptor base address */ + ushort scc_tbase; /* Tx Buffer descriptor base address */ + u_char scc_rfcr; /* Rx function code */ + u_char scc_tfcr; /* Tx function code */ + ushort scc_mrblr; /* Max receive buffer length */ + uint scc_rstate; /* Internal */ + uint scc_idp; /* Internal */ + ushort scc_rbptr; /* Internal */ + ushort scc_ibc; /* Internal */ + uint scc_rxtmp; /* Internal */ + uint scc_tstate; /* Internal */ + uint scc_tdp; /* Internal */ + ushort scc_tbptr; /* Internal */ + ushort scc_tbc; /* Internal */ + uint scc_txtmp; /* Internal */ + uint scc_rcrc; /* Internal */ + uint scc_tcrc; /* Internal */ +} sccp_t; + +/* CPM Ethernet through SCC1. + */ +typedef struct scc_enet { + sccp_t sen_genscc; + uint sen_cpres; /* Preset CRC */ + uint sen_cmask; /* Constant mask for CRC */ + uint sen_crcec; /* CRC Error counter */ + uint sen_alec; /* alignment error counter */ + uint sen_disfc; /* discard frame counter */ + ushort sen_pads; /* Tx short frame pad character */ + ushort sen_retlim; /* Retry limit threshold */ + ushort sen_retcnt; /* Retry limit counter */ + ushort sen_maxflr; /* maximum frame length register */ + ushort sen_minflr; /* minimum frame length register */ + ushort sen_maxd1; /* maximum DMA1 length */ + ushort sen_maxd2; /* maximum DMA2 length */ + ushort sen_maxd; /* Rx max DMA */ + ushort sen_dmacnt; /* Rx DMA counter */ + ushort sen_maxb; /* Max BD byte count */ + ushort sen_gaddr1; /* Group address filter */ + ushort sen_gaddr2; + ushort sen_gaddr3; + ushort sen_gaddr4; + uint sen_tbuf0data0; /* Save area 0 - current frame */ + uint sen_tbuf0data1; /* Save area 1 - current frame */ + uint sen_tbuf0rba; /* Internal */ + uint sen_tbuf0crc; /* Internal */ + ushort sen_tbuf0bcnt; /* Internal */ + ushort sen_paddrh; /* physical address (MSB) */ + ushort sen_paddrm; + ushort sen_paddrl; /* physical address (LSB) */ + ushort sen_pper; /* persistence */ + ushort sen_rfbdptr; /* Rx first BD pointer */ + ushort sen_tfbdptr; /* Tx first BD pointer */ + ushort sen_tlbdptr; /* Tx last BD pointer */ + uint sen_tbuf1data0; /* Save area 0 - current frame */ + uint sen_tbuf1data1; /* Save area 1 - current frame */ + uint sen_tbuf1rba; /* Internal */ + uint sen_tbuf1crc; /* Internal */ + ushort sen_tbuf1bcnt; /* Internal */ + ushort sen_txlen; /* Tx Frame length counter */ + ushort sen_iaddr1; /* Individual address filter */ + ushort sen_iaddr2; + ushort sen_iaddr3; + ushort sen_iaddr4; + ushort sen_boffcnt; /* Backoff counter */ + + /* NOTE: Some versions of the manual have the following items + * incorrectly documented. Below is the proper order. + */ + ushort sen_taddrh; /* temp address (MSB) */ + ushort sen_taddrm; + ushort sen_taddrl; /* temp address (LSB) */ +} scc_enet_t; + + +/* SCC Event register as used by Ethernet. +*/ +#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ +#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* SCC Mode Register (PSMR) as used by Ethernet. +*/ +#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ + +/* Buffer descriptor control/status used by Ethernet receive. + * Common to SCC and FCC. + */ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ +#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. + * Common to SCC and FCC. + */ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/* SCC as UART +*/ +typedef struct scc_uart { + sccp_t scc_genscc; + uint scc_res1; /* Reserved */ + uint scc_res2; /* Reserved */ + ushort scc_maxidl; /* Maximum idle chars */ + ushort scc_idlc; /* temp idle counter */ + ushort scc_brkcr; /* Break count register */ + ushort scc_parec; /* receive parity error counter */ + ushort scc_frmec; /* receive framing error counter */ + ushort scc_nosec; /* receive noise counter */ + ushort scc_brkec; /* receive break condition counter */ + ushort scc_brkln; /* last received break length */ + ushort scc_uaddr1; /* UART address character 1 */ + ushort scc_uaddr2; /* UART address character 2 */ + ushort scc_rtemp; /* Temp storage */ + ushort scc_toseq; /* Transmit out of sequence char */ + ushort scc_char1; /* control character 1 */ + ushort scc_char2; /* control character 2 */ + ushort scc_char3; /* control character 3 */ + ushort scc_char4; /* control character 4 */ + ushort scc_char5; /* control character 5 */ + ushort scc_char6; /* control character 6 */ + ushort scc_char7; /* control character 7 */ + ushort scc_char8; /* control character 8 */ + ushort scc_rccm; /* receive control character mask */ + ushort scc_rccr; /* receive control character register */ + ushort scc_rlbc; /* receive last break character */ +} scc_uart_t; + +/* SCC Event and Mask registers when it is used as a UART. +*/ +#define UART_SCCM_GLR ((ushort)0x1000) +#define UART_SCCM_GLT ((ushort)0x0800) +#define UART_SCCM_AB ((ushort)0x0200) +#define UART_SCCM_IDL ((ushort)0x0100) +#define UART_SCCM_GRA ((ushort)0x0080) +#define UART_SCCM_BRKE ((ushort)0x0040) +#define UART_SCCM_BRKS ((ushort)0x0020) +#define UART_SCCM_CCR ((ushort)0x0008) +#define UART_SCCM_BSY ((ushort)0x0004) +#define UART_SCCM_TX ((ushort)0x0002) +#define UART_SCCM_RX ((ushort)0x0001) + +/* The SCC PSMR when used as a UART. +*/ +#define SCU_PSMR_FLC ((ushort)0x8000) +#define SCU_PSMR_SL ((ushort)0x4000) +#define SCU_PSMR_CL ((ushort)0x3000) +#define SCU_PSMR_UM ((ushort)0x0c00) +#define SCU_PSMR_FRZ ((ushort)0x0200) +#define SCU_PSMR_RZS ((ushort)0x0100) +#define SCU_PSMR_SYN ((ushort)0x0080) +#define SCU_PSMR_DRT ((ushort)0x0040) +#define SCU_PSMR_PEN ((ushort)0x0010) +#define SCU_PSMR_RPM ((ushort)0x000c) +#define SCU_PSMR_REVP ((ushort)0x0008) +#define SCU_PSMR_TPM ((ushort)0x0003) +#define SCU_PSMR_TEVP ((ushort)0x0003) + +/* CPM Transparent mode SCC. + */ +typedef struct scc_trans { + sccp_t st_genscc; + uint st_cpres; /* Preset CRC */ + uint st_cmask; /* Constant mask for CRC */ +} scc_trans_t; + +#define BD_SCC_TX_LAST ((ushort)0x0800) + +/* How about some FCCs..... +*/ +#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) +#define FCC_GFMR_DIAG_LE ((uint)0x40000000) +#define FCC_GFMR_DIAG_AE ((uint)0x80000000) +#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) +#define FCC_GFMR_TCI ((uint)0x20000000) +#define FCC_GFMR_TRX ((uint)0x10000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_TTX ((uint)0x08000000) +#define FCC_GFMR_CDP ((uint)0x04000000) +#define FCC_GFMR_CTSP ((uint)0x02000000) +#define FCC_GFMR_CDS ((uint)0x01000000) +#define FCC_GFMR_CTSS ((uint)0x00800000) +#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) +#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) +#define FCC_GFMR_SYNL_8 ((uint)0x00008000) +#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) +#define FCC_GFMR_RTSM ((uint)0x00002000) +#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) +#define FCC_GFMR_REVD ((uint)0x00000400) +#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) +#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) +#define FCC_GFMR_TCRC_16 ((uint)0x00000000) +#define FCC_GFMR_TCRC_32 ((uint)0x00000080) +#define FCC_GFMR_ENR ((uint)0x00000020) +#define FCC_GFMR_ENT ((uint)0x00000010) +#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) +#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) +#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) + +/* Generic FCC parameter ram. +*/ +typedef struct fcc_param { + ushort fcc_riptr; /* Rx Internal temp pointer */ + ushort fcc_tiptr; /* Tx Internal temp pointer */ + ushort fcc_res1; + ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ + uint fcc_rstate; /* Upper byte is Func code, must be set */ + uint fcc_rbase; /* Receive BD base */ + ushort fcc_rbdstat; /* RxBD status */ + ushort fcc_rbdlen; /* RxBD down counter */ + uint fcc_rdptr; /* RxBD internal data pointer */ + uint fcc_tstate; /* Upper byte is Func code, must be set */ + uint fcc_tbase; /* Transmit BD base */ + ushort fcc_tbdstat; /* TxBD status */ + ushort fcc_tbdlen; /* TxBD down counter */ + uint fcc_tdptr; /* TxBD internal data pointer */ + uint fcc_rbptr; /* Rx BD Internal buf pointer */ + uint fcc_tbptr; /* Tx BD Internal buf pointer */ + uint fcc_rcrc; /* Rx temp CRC */ + uint fcc_res2; + uint fcc_tcrc; /* Tx temp CRC */ +} fccp_t; + + +/* Ethernet controller through FCC. +*/ +typedef struct fcc_enet { + fccp_t fen_genfcc; + uint fen_statbuf; /* Internal status buffer */ + uint fen_camptr; /* CAM address */ + uint fen_cmask; /* Constant mask for CRC */ + uint fen_cpres; /* Preset CRC */ + uint fen_crcec; /* CRC Error counter */ + uint fen_alec; /* alignment error counter */ + uint fen_disfc; /* discard frame counter */ + ushort fen_retlim; /* Retry limit */ + ushort fen_retcnt; /* Retry counter */ + ushort fen_pper; /* Persistence */ + ushort fen_boffcnt; /* backoff counter */ + uint fen_gaddrh; /* Group address filter, high 32-bits */ + uint fen_gaddrl; /* Group address filter, low 32-bits */ + ushort fen_tfcstat; /* out of sequence TxBD */ + ushort fen_tfclen; + uint fen_tfcptr; + ushort fen_mflr; /* Maximum frame length (1518) */ + ushort fen_paddrh; /* MAC address */ + ushort fen_paddrm; + ushort fen_paddrl; + ushort fen_ibdcount; /* Internal BD counter */ + ushort fen_ibdstart; /* Internal BD start pointer */ + ushort fen_ibdend; /* Internal BD end pointer */ + ushort fen_txlen; /* Internal Tx frame length counter */ + uint fen_ibdbase[8]; /* Internal use */ + uint fen_iaddrh; /* Individual address filter */ + uint fen_iaddrl; + ushort fen_minflr; /* Minimum frame length (64) */ + ushort fen_taddrh; /* Filter transfer MAC address */ + ushort fen_taddrm; + ushort fen_taddrl; + ushort fen_padptr; /* Pointer to pad byte buffer */ + ushort fen_cftype; /* control frame type */ + ushort fen_cfrange; /* control frame range */ + ushort fen_maxb; /* maximum BD count */ + ushort fen_maxd1; /* Max DMA1 length (1520) */ + ushort fen_maxd2; /* Max DMA2 length (1520) */ + ushort fen_maxd; /* internal max DMA count */ + ushort fen_dmacnt; /* internal DMA counter */ + uint fen_octc; /* Total octect counter */ + uint fen_colc; /* Total collision counter */ + uint fen_broc; /* Total broadcast packet counter */ + uint fen_mulc; /* Total multicast packet count */ + uint fen_uspc; /* Total packets < 64 bytes */ + uint fen_frgc; /* Total packets < 64 bytes with errors */ + uint fen_ospc; /* Total packets > 1518 */ + uint fen_jbrc; /* Total packets > 1518 with errors */ + uint fen_p64c; /* Total packets == 64 bytes */ + uint fen_p65c; /* Total packets 64 < bytes <= 127 */ + uint fen_p128c; /* Total packets 127 < bytes <= 255 */ + uint fen_p256c; /* Total packets 256 < bytes <= 511 */ + uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ + uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ + uint fen_cambuf; /* Internal CAM buffer poiner */ + ushort fen_rfthr; /* Received frames threshold */ + ushort fen_rfcnt; /* Received frames count */ +} fcc_enet_t; + +/* FCC Event/Mask register as used by Ethernet. +*/ +#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ +#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ +#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ +#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* FCC Mode Register (FPSMR) as used by Ethernet. +*/ +#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ +#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ +#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ +#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ +#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ +#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ +#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ +#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ +#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ +#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ +#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ +#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ +#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ + +/* IIC parameter RAM. +*/ +typedef struct iic { + ushort iic_rbase; /* Rx Buffer descriptor base address */ + ushort iic_tbase; /* Tx Buffer descriptor base address */ + u_char iic_rfcr; /* Rx function code */ + u_char iic_tfcr; /* Tx function code */ + ushort iic_mrblr; /* Max receive buffer length */ + uint iic_rstate; /* Internal */ + uint iic_rdp; /* Internal */ + ushort iic_rbptr; /* Internal */ + ushort iic_rbc; /* Internal */ + uint iic_rxtmp; /* Internal */ + uint iic_tstate; /* Internal */ + uint iic_tdp; /* Internal */ + ushort iic_tbptr; /* Internal */ + ushort iic_tbc; /* Internal */ + uint iic_txtmp; /* Internal */ +} iic_t; + +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; /* Tx temp. */ + uint spi_res1[4]; /* SDMA temp. */ +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) +#define SPMODE_PM(x) ((x) &0xF) + +#define SPI_EB ((u_char)0x10) /* big endian byte order */ + +#define BD_IIC_START ((ushort)0x0400) + +/*----------------------------------------------------------------------- + * CMXFCR - CMX FCC Clock Route Register 15-12 + */ +#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ +#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ +#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ +#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ +#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ +#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ +#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ +#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ +#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ + +#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ +#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ +#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ +#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ +#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ +#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ +#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ +#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ + +#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ +#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ +#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ +#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ +#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ +#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ +#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ +#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ + +#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ +#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ +#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ +#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ +#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ +#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ +#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ +#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ + +#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ +#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ +#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ +#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ +#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ +#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ +#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ +#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ + +#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ +#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ +#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ +#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ +#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ +#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ +#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ +#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ + +#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ +#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ +#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ +#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ +#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ +#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ +#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ +#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ + +/*----------------------------------------------------------------------- + * CMXSCR - CMX SCC Clock Route Register 15-14 + */ +#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ +#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ +#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ +#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ +#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ +#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ +#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ +#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ +#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ +#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ +#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ +#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ +#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ +#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ +#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ +#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ + +#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ +#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ +#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ +#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ +#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ +#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ +#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ +#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ + +#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ +#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ +#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ +#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ +#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ +#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ +#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ +#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ + +#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ +#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ +#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ +#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ +#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ +#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ +#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ +#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ + +#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ +#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ +#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ +#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ +#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ +#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ +#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ +#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ + +#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ +#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ +#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ +#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ +#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ +#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ +#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ +#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ + +#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ +#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ +#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ +#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ +#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ +#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ +#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ +#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ + +#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ +#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ +#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ +#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ +#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ +#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ +#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ +#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ + +#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ +#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ +#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ +#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ +#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ +#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ +#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ +#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ + +#endif /* __CPM_85XX__ */ diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h new file mode 100644 index 0000000..908007c --- /dev/null +++ b/include/asm-ppc/e300.h @@ -0,0 +1,128 @@ +/* + * Copyright 2004 Freescale Semiconductor, Inc. + * Liberty Eran (liberty@freescale.com) + */ + +#ifndef __E300_H__ +#define __E300_H__ + +/* + * e300 Processor Version & Revision Numbers + */ +#define PVR_83xx 0x80830000 +#define PVR_8349_REV10 (PVR_83xx | 0x0010) +#define PVR_8349_REV11 (PVR_83xx | 0x0011) + +/* + * Hardware Implementation-Dependent Register 0 (HID0) + */ + +/* #define HID0 1008 already defined in processor.h */ +#define HID0_MASK_MACHINE_CHECK 0x00000000 +#define HID0_ENABLE_MACHINE_CHECK 0x80000000 + +#define HID0_DISABLE_CACHE_PARITY 0x00000000 +#define HID0_ENABLE_CACHE_PARITY 0x40000000 + +#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ +#define HID0_ENABLE_ADDRESS_PARITY 0x20000000 + +#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ +#define HID0_ENABLE_DATE_PARITY 0x10000000 + +#define HID0_CORE_CLK_OUT 0x00000000 +#define HID0_CORE_CLK_OUT_DIV_2 0x08000000 + +#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */ +#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000 + +#define HID0_DISABLE_DOSE_MODE 0x00000000 +#define HID0_ENABLE_DOSE_MODE 0x00800000 + +#define HID0_DISABLE_NAP_MODE 0x00000000 +#define HID0_ENABLE_NAP_MODE 0x00400000 + +#define HID0_DISABLE_SLEEP_MODE 0x00000000 +#define HID0_ENABLE_SLEEP_MODE 0x00200000 + +#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000 +#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000 + +#define HID0_SOFT_RESET 0x00010000 + +#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 +#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 + +#define HID0_DISABLE_DATA_CACHE 0x00000000 +#define HID0_ENABLE_DATA_CACHE 0x00004000 + +#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 + +#define HID0_LOCK_DATA_CACHE 0x00001000 + +#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800 + +#define HID0_INVALIDATE_DATA_CACHE 0x00000400 + +#define HID0_DISABLE_M_BIT 0x00000000 +#define HID0_ENABLE_M_BIT 0x00000080 + +#define HID0_FBIOB 0x00000010 + +#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 +#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 + +#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000 +#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001 + +/* + * Hardware Implementation-Dependent Register 2 (HID2) + */ +#define HID2 1011 + +#define HID2_LET 0x08000000 +#define HID2_HBE 0x00040000 +#define HID2_IWLCK_000 0x00000000 /* no ways locked */ +#define HID2_IWLCK_001 0x00002000 /* way 0 locked */ +#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */ +#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */ +#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */ +#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ +#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ + + +/* BAT (block address translation */ +#define BATU_BEPI_MSK 0xfffe0000 +#define BATU_BL_MSK 0x00001ffc + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 + +#define BATL_BRPN_MSK 0xfffe0000 +#define BATL_WIMG_MSK 0x00000078 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#endif /* __E300_H__ */ diff --git a/include/asm-ppc/errno.h b/include/asm-ppc/errno.h new file mode 100644 index 0000000..ff364b8 --- /dev/null +++ b/include/asm-ppc/errno.h @@ -0,0 +1,138 @@ +#ifndef _PPC_ERRNO_H +#define _PPC_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ +#define EDEADLOCK 58 /* File locking deadlock error */ +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +/* Should never be seen by user programs */ +#define ERESTARTSYS 512 +#define ERESTARTNOINTR 513 +#define ERESTARTNOHAND 514 /* restart if no handler.. */ +#define ENOIOCTLCMD 515 /* No ioctl command */ + +#define _LAST_ERRNO 515 + +#endif diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h new file mode 100644 index 0000000..b73af96 --- /dev/null +++ b/include/asm-ppc/global_data.h @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H + +#include "asm/types.h" + +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long bus_clk; +#if defined(CONFIG_CPM2) + /* There are many clocks on the MPC8260 - see page 9-5 */ + unsigned long vco_out; + unsigned long cpm_clk; + unsigned long scc_clk; + unsigned long brg_clk; +#endif +#if defined(CONFIG_MPC83XX) + /* There are other clocks in the MPC83XX */ + u32 csb_clk; + u32 tsec1_clk; + u32 tsec2_clk; + u32 core_clk; + u32 usbmph_clk; + u32 usbdr_clk; + u32 i2c_clk; + u32 enc_clk; + u32 lbiu_clk; + u32 lclk_clk; + u32 ddr_clk; + u32 pci_clk; +#endif +#if defined(CONFIG_MPC5xxx) + unsigned long ipb_clk; + unsigned long pci_clk; +#endif +#if defined(CONFIG_MPC8220) + unsigned long bExtUart; + unsigned long inp_clk; + unsigned long pci_clk; + unsigned long vco_clk; + unsigned long pev_clk; + unsigned long flb_clk; +#endif + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long reset_status; /* reset status register at boot */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long have_console; /* serial_init() was called */ +#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2) + unsigned int dp_alloc_base; + unsigned int dp_alloc_top; +#endif +#if defined(CFG_GT_6426x) + unsigned int mirror_hack[16]; +#endif +#if defined(CONFIG_A3000) || \ + defined(CONFIG_HIDDEN_DRAGON) || \ + defined(CONFIG_MUSENKI) || \ + defined(CONFIG_SANDPOINT) + void * console_addr; +#endif +#ifdef CONFIG_AMIGAONEG3SE + unsigned long relocaddr; /* Start address of U-Boot in RAM */ +#endif +#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) + unsigned long fb_base; /* Base address of framebuffer memory */ +#endif +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + unsigned long post_log_word; /* Record POST activities */ + unsigned long post_init_f_time; /* When post_init_f started */ +#endif +#ifdef CONFIG_BOARD_TYPES + unsigned long board_type; +#endif +#ifdef CONFIG_MODEM_SUPPORT + unsigned long do_mdm_init; + unsigned long be_quiet; +#endif +#ifdef CONFIG_LWMON + unsigned long kbd_status; +#endif + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#if 1 +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r29") +#else /* We could use plain global data, but the resulting code is bigger */ +#define XTRN_DECLARE_GLOBAL_DATA_PTR extern +#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \ + gd_t *gd +#endif + +#endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h new file mode 100644 index 0000000..fa9d164 --- /dev/null +++ b/include/asm-ppc/i2c.h @@ -0,0 +1,103 @@ +/* + * Freescale I2C Controller + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003, Motorola, Inc. + * author: Eran Liberty (liberty@freescale.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_I2C_H_ +#define _ASM_I2C_H_ + +#include + +typedef struct i2c +{ + u8 adr; /**< I2C slave address */ +#define I2C_ADR 0xFE +#define I2C_ADR_SHIFT 1 +#define I2C_ADR_RES ~(I2C_ADR) + u8 res0[3]; + u8 fdr; /**< I2C frequency divider register */ +#define IC2_FDR 0x3F +#define IC2_FDR_SHIFT 0 +#define IC2_FDR_RES ~(IC2_FDR) + u8 res1[3]; + u8 cr; /**< I2C control redister */ +#define I2C_CR_MEN 0x80 +#define I2C_CR_MIEN 0x40 +#define I2C_CR_MSTA 0x20 +#define I2C_CR_MTX 0x10 +#define I2C_CR_TXAK 0x08 +#define I2C_CR_RSTA 0x04 +#define I2C_CR_BCST 0x01 + u8 res2[3]; + u8 sr; /**< I2C status register */ +#define I2C_SR_MCF 0x80 +#define I2C_SR_MAAS 0x40 +#define I2C_SR_MBB 0x20 +#define I2C_SR_MAL 0x10 +#define I2C_SR_BCSTM 0x08 +#define I2C_SR_SRW 0x04 +#define I2C_SR_MIF 0x02 +#define I2C_SR_RXAK 0x01 + u8 res3[3]; + u8 dr; /**< I2C data register */ +#define I2C_DR 0xFF +#define I2C_DR_SHIFT 0 +#define I2C_DR_RES ~(I2C_DR) + u8 res4[3]; + u8 dfsrr; /**< I2C digital filter sampling rate register */ +#define I2C_DFSRR 0x3F +#define I2C_DFSRR_SHIFT 0 +#define I2C_DFSRR_RES ~(I2C_DR) + u8 res5[3]; + u8 res6[0xE8]; +} i2c_t; + +#ifndef CFG_HZ +#error CFG_HZ is not defined in /include/configs/${BOARD}.h +#endif +#define I2C_TIMEOUT (CFG_HZ/4) + +#ifndef CFG_IMMRBAR +#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h +#endif + +#ifndef CFG_I2C_OFFSET +#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h +#endif + +#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X) +/* + * MPC8349 have two i2c bus + */ +extern i2c_t * mpc8349_i2c; +#define I2C mpc8349_i2c +#else +#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET)) +#endif + +#define I2C_READ 1 +#define I2C_WRITE 0 + +#endif /* _ASM_I2C_H_ */ diff --git a/include/asm-ppc/immap_8220.h b/include/asm-ppc/immap_8220.h new file mode 100644 index 0000000..f9595f4 --- /dev/null +++ b/include/asm-ppc/immap_8220.h @@ -0,0 +1,246 @@ +/* + * MPC8220 Internal Memory Map + * Copyright (c) 2004 TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * The Internal Memory Map of the 8220. + * + */ +#ifndef __IMMAP_MPC8220__ +#define __IMMAP_MPC8220__ + +/* + * System configuration registers. + */ +typedef struct sys_conf { + u16 mbar; /* 0x00 */ + u16 res1; + + u16 res2; /* 0x04 */ + u16 sdramds; + + u32 res3[6]; /* 0x08 */ + + u32 cscfg[6]; /* 0x20 */ + + u32 res4[2]; /* 0x38 */ + + u8 res5[3]; /* 0x40 */ + u8 rstctrl; + + u8 res6[3]; /* 0x44 */ + u8 rststat; + + u32 res7[2]; /* 0x48 */ + + u32 jtagid; /* 0x50 */ +} sysconf8220_t; + + +/* + * Memory controller registers. + */ +typedef struct mem_ctlr { + ushort mode; /* 0x100 */ + ushort res1; + u32 ctrl; /* 0x104 */ + u32 cfg1; /* 0x108 */ + u32 cfg2; /* 0x10c */ +} memctl8220_t; + +/* + * XLB Arbitration registers + */ +typedef struct xlb_arb +{ + uint res1[16]; /* 0x200 */ + uint config; /* 0x240 */ + uint version; /* 0x244 */ + uint status; /* 0x248 */ + uint intEnable; /* 0x24c */ + uint addrCap; /* 0x250 */ + uint busSigCap; /* 0x254 */ + uint addrTenTimeOut; /* 0x258 */ + uint dataTenTimeOut; /* 0x25c */ + uint busActTimeOut; /* 0x260 */ + uint mastPriEn; /* 0x264 */ + uint mastPriority; /* 0x268 */ + uint baseAddr; /* 0x26c */ +} xlbarb8220_t; + +/* + * Flexbus registers + */ +typedef struct flexbus +{ + ushort csar0; /* 0x00 */ + ushort res1; + uint csmr0; /* 0x04 */ + uint cscr0; /* 0x08 */ + + ushort csar1; /* 0x0c */ + ushort res2; + uint csmr1; /* 0x10 */ + uint cscr1; /* 0x14 */ + + ushort csar2; /* 0x18 */ + ushort res3; + uint csmr2; /* 0x1c */ + uint cscr2; /* 0x20 */ + + ushort csar3; /* 0x24 */ + ushort res4; + uint csmr3; /* 0x28 */ + uint cscr3; /* 0x2c */ + + ushort csar4; /* 0x30 */ + ushort res5; + uint csmr4; /* 0x34 */ + uint cscr4; /* 0x38 */ + + ushort csar5; /* 0x3c */ + ushort res6; + uint csmr5; /* 0x40 */ + uint cscr5; /* 0x44 */ +} flexbus8220_t; + +/* + * GPIO registers + */ +typedef struct gpio +{ + u32 out; /* 0x00 */ + u32 obs; /* 0x04 */ + u32 obc; /* 0x08 */ + u32 obt; /* 0x0c */ + u32 en; /* 0x10 */ + u32 ebs; /* 0x14 */ + u32 ebc; /* 0x18 */ + u32 ebt; /* 0x1c */ + u32 mc; /* 0x20 */ + u32 st; /* 0x24 */ + u32 intr; /* 0x28 */ +} gpio8220_t; + +/* + * General Purpose Timer registers + */ +typedef struct gptimer +{ + u8 OCPW; + u8 OctIct; + u8 Control; + u8 Mode; + + u16 Prescl; /* Prescale */ + u16 Count; /* Count */ + + u16 PwmWid; /* PWM Width */ + u8 PwmOp; /* Output Polarity */ + u8 PwmLd; /* Immediate Update */ + + u16 Capture; /* Capture internal counter */ + u8 OvfPin; /* Ovf and Pin */ + u8 Int; /* Interrupts */ +} gptmr8220_t; + +/* + * PSC registers + */ +typedef struct psc +{ + u32 mr1_2; /* 0x00 Mode reg 1 & 2 */ + u32 sr_csr; /* 0x04 Status/Clock Select reg */ + u32 cr; /* 0x08 Command reg */ + u8 xmitbuf[4]; /* 0x0c Receive/Transmit Buffer */ + u32 ipcr_acr; /* 0x10 Input Port Change/Auxiliary Control reg */ + u32 isr_imr; /* 0x14 Interrupt Status/Mask reg */ + u32 ctur; /* 0x18 Counter Timer Upper reg */ + u32 ctlr; /* 0x1c Counter Timer Lower reg */ + u32 rsvd1[4]; /* 0x20 ... 0x2c */ + u32 ivr; /* 0x30 Interrupt Vector reg */ + u32 ipr; /* 0x34 Input Port reg */ + u32 opsetr; /* 0x38 Output Port Set reg */ + u32 opresetr; /* 0x3c Output Port Reset reg */ + u32 sicr; /* 0x40 PSC/IrDA control reg */ + u32 ircr1; /* 0x44 IrDA control reg 1*/ + u32 ircr2; /* 0x48 IrDA control reg 2*/ + u32 irsdr; /* 0x4c IrDA SIR Divide reg */ + u32 irmdr; /* 0x50 IrDA MIR Divide reg */ + u32 irfdr; /* 0x54 PSC IrDA FIR Divide reg */ + u32 rfnum; /* 0x58 RX-FIFO counter */ + u32 txnum; /* 0x5c TX-FIFO counter */ + u32 rfdata; /* 0x60 RX-FIFO data */ + u32 rfstat; /* 0x64 RX-FIFO status */ + u32 rfcntl; /* 0x68 RX-FIFO control */ + u32 rfalarm; /* 0x6c RX-FIFO alarm */ + u32 rfrptr; /* 0x70 RX-FIFO read pointer */ + u32 rfwptr; /* 0x74 RX-FIFO write pointer */ + u32 rflfrptr; /* 0x78 RX-FIFO last read frame pointer */ + u32 rflfwptr; /* 0x7c RX-FIFO last write frame pointer */ + + u32 tfdata; /* 0x80 TX-FIFO data */ + u32 tfstat; /* 0x84 TX-FIFO status */ + u32 tfcntl; /* 0x88 TX-FIFO control */ + u32 tfalarm; /* 0x8c TX-FIFO alarm */ + u32 tfrptr; /* 0x90 TX-FIFO read pointer */ + u32 tfwptr; /* 0x94 TX-FIFO write pointer */ + u32 tflfrptr; /* 0x98 TX-FIFO last read frame pointer */ + u32 tflfwptr; /* 0x9c TX-FIFO last write frame pointer */ +} psc8220_t; + +/* + * Interrupt Controller registers + */ +typedef struct interrupt_controller { +} intctl8220_t; + + +/* Fast controllers +*/ + +/* + * I2C registers + */ +typedef struct i2c +{ + u8 adr; /* 0x00 */ + u8 res1[3]; + u8 fdr; /* 0x04 */ + u8 res2[3]; + u8 cr; /* 0x08 */ + u8 res3[3]; + u8 sr; /* 0x0C */ + u8 res4[3]; + u8 dr; /* 0x10 */ + u8 res5[3]; + u32 reserved0; /* 0x14 */ + u32 reserved1; /* 0x18 */ + u32 reserved2; /* 0x1c */ + u8 icr; /* 0x20 */ + u8 res6[3]; +} i2c8220_t; + +/* + * Port Configuration Registers + */ +typedef struct pcfg +{ + uint pcfg0; /* 0x00 */ + uint pcfg1; /* 0x04 */ + uint pcfg2; /* 0x08 */ + uint pcfg3; /* 0x0c */ +} pcfg8220_t; + +/* ...and the whole thing wrapped up.... +*/ +typedef struct immap { + sysconf8220_t im_sysconf; /* System Configuration */ + memctl8220_t im_memctl; /* Memory Controller */ + xlbarb8220_t im_xlbarb; /* XLB Arbitration */ + psc8220_t im_psc; /* PSC controller */ + flexbus8220_t im_fb; /* FlexBus Controller */ + i2c8220_t im_i2c; /* I2C control/status */ + pcfg8220_t im_pcfg; /* Port configuration */ +} immap_t; + +#endif /* __IMMAP_MPC8220__ */ diff --git a/include/asm-ppc/immap_8260.h b/include/asm-ppc/immap_8260.h new file mode 100644 index 0000000..4974ae5 --- /dev/null +++ b/include/asm-ppc/immap_8260.h @@ -0,0 +1,599 @@ +/* + * MPC8260 Internal Memory Map + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * + * The Internal Memory Map of the 8260. I don't know how generic + * this will be, as I don't have any knowledge of the subsequent + * parts at this time. I copied this from the 8xx_immap.h. + */ +#ifndef __IMMAP_82XX__ +#define __IMMAP_82XX__ + +/* System configuration registers. +*/ +typedef struct sys_conf { + uint sc_siumcr; + uint sc_sypcr; + char res1[6]; + ushort sc_swsr; + char res2[20]; + uint sc_bcr; + u_char sc_ppc_acr; + char res3[3]; + uint sc_ppc_alrh; + uint sc_ppc_alrl; + u_char sc_lcl_acr; + char res4[3]; + uint sc_lcl_alrh; + uint sc_lcl_alrl; + uint sc_tescr1; + uint sc_tescr2; + uint sc_ltescr1; + uint sc_ltescr2; + uint sc_pdtea; + u_char sc_pdtem; + char res5[3]; + uint sc_ldtea; + u_char sc_ldtem; + char res6[163]; +} sysconf8260_t; + + +/* Memory controller registers. +*/ +typedef struct mem_ctlr { + uint memc_br0; + uint memc_or0; + uint memc_br1; + uint memc_or1; + uint memc_br2; + uint memc_or2; + uint memc_br3; + uint memc_or3; + uint memc_br4; + uint memc_or4; + uint memc_br5; + uint memc_or5; + uint memc_br6; + uint memc_or6; + uint memc_br7; + uint memc_or7; + uint memc_br8; + uint memc_or8; + uint memc_br9; + uint memc_or9; + uint memc_br10; + uint memc_or10; + uint memc_br11; + uint memc_or11; + char res1[8]; + uint memc_mar; + char res2[4]; + uint memc_mamr; + uint memc_mbmr; + uint memc_mcmr; + char res3[8]; + ushort memc_mptpr; + char res4[2]; + uint memc_mdr; + char res5[4]; + uint memc_psdmr; + uint memc_lsdmr; + u_char memc_purt; + char res6[3]; + u_char memc_psrt; + char res7[3]; + u_char memc_lurt; + char res8[3]; + u_char memc_lsrt; + char res9[3]; + uint memc_immr; + uint memc_pcibr0; + uint memc_pcibr1; + char res10[16]; + uint memc_pcimsk0; + uint memc_pcimsk1; + char res11[52]; +} memctl8260_t; + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + char res1[32]; + ushort sit_tmcntsc; + char res2[2]; + uint sit_tmcnt; + char res3[4]; + uint sit_tmcntal; + char res4[16]; + ushort sit_piscr; + char res5[2]; + uint sit_pitc; + uint sit_pitr; + char res6[94]; + char res7[390]; +} sit8260_t; + +/* PCI + */ +typedef struct pci_config { + uint pci_omisr; + uint pci_ominr; + char res1[8]; + uint pci_ifqpr; + uint pci_ofqpr; + char res2[8]; + uint pci_imr0; + uint pci_imr1; + uint pci_omr0; + uint pci_omr1; + uint pci_odr; + char res3[4]; + uint pci_idr; + char res4[20]; + uint pci_imisr; + uint pci_imimr; + char res5[24]; + uint pci_ifhpr; + char res5_2[4]; + uint pci_iftpr; + char res6[4]; + uint pci_iphpr; + char res6_2[4]; + uint pci_iptpr; + char res7[4]; + uint pci_ofhpr; + char res7_2[4]; + uint pci_oftpr; + char res8[4]; + uint pci_ophpr; + char res8_2[4]; + uint pci_optpr; + char res9[8]; + uint pci_mucr; + char res10[8]; + uint pci_qbar; + char res11[12]; + uint pci_dmamr0; + uint pci_dmasr0; + uint pci_dmacdar0; + char res12[4]; + uint pci_dmasar0; + char res13[4]; + uint pci_dmadar0; + char res14[4]; + uint pci_dmabcr0; + uint pci_dmandar0; + char res15[88]; + uint pci_dmamr1; + uint pci_dmasr1; + uint pci_dmacdar1; + char res16[4]; + uint pci_dmasar1; + char res17[4]; + uint pci_dmadar1; + char res18[4]; + uint pci_dmabcr1; + uint pci_dmandar1; + char res19[88]; + uint pci_dmamr2; + uint pci_dmasr2; + uint pci_dmacdar2; + char res20[4]; + uint pci_dmasar2; + char res21[4]; + uint pci_dmadar2; + char res22[4]; + uint pci_dmabcr2; + uint pci_dmandar2; + char res23[88]; + uint pci_dmamr3; + uint pci_dmasr3; + uint pci_dmacdar3; + char res24[4]; + uint pci_dmasar3; + char res25[4]; + uint pci_dmadar3; + char res26[4]; + uint pci_dmabcr3; + uint pci_dmandar3; + char res27[344]; + uint pci_potar0; + char res28[4]; + uint pci_pobar0; + char res29[4]; + uint pci_pocmr0; + char res30[4]; + uint pci_potar1; + char res31[4]; + uint pci_pobar1; + char res32[4]; + uint pci_pocmr1; + char res33[4]; + uint pci_potar2; + char res34[4]; + uint pci_pobar2; + char res35[4]; + uint pci_pocmr2; + char res36[52]; + uint pci_ptcr; + uint pci_gpcr; + uint pci_gcr; + uint pci_esr; + uint pci_emr; + uint pci_ecr; + uint pci_eacr; + char res37[4]; + uint pci_edcr; + char res38[4]; + uint pci_eccr; + char res39[44]; + uint pci_pitar1; + char res40[4]; + uint pci_pibar1; + char res41[4]; + uint pci_picmr1; + char res42[4]; + uint pci_pitar0; + char res43[4]; + uint pci_pibar0; + char res44[4]; + uint pci_picmr0; + char res45[4]; + uint pci_cfg_addr; + uint pci_cfg_data; + uint pci_int_ack; + char res46[756]; +}pci8260_t; +#define PISCR_PIRQ_MASK ((ushort)0xff00) +#define PISCR_PS ((ushort)0x0080) +#define PISCR_PIE ((ushort)0x0004) +#define PISCR_PTF ((ushort)0x0002) +#define PISCR_PTE ((ushort)0x0001) + +/* Interrupt Controller. +*/ +typedef struct interrupt_controller { + ushort ic_sicr; + char res1[2]; + uint ic_sivec; + uint ic_sipnrh; + uint ic_sipnrl; + uint ic_siprr; + uint ic_scprrh; + uint ic_scprrl; + uint ic_simrh; + uint ic_simrl; + uint ic_siexr; + char res2[88]; +} intctl8260_t; + +/* Clocks and Reset. +*/ +typedef struct clk_and_reset { + uint car_sccr; + char res1[4]; + uint car_scmr; + char res2[4]; + uint car_rsr; + uint car_rmr; + char res[104]; +} car8260_t; + +/* Input/Output Port control/status registers. + * Names consistent with processor manual, although they are different + * from the original 8xx names....... + */ +typedef struct io_port { + uint iop_pdira; + uint iop_ppara; + uint iop_psora; + uint iop_podra; + uint iop_pdata; + char res1[12]; + uint iop_pdirb; + uint iop_pparb; + uint iop_psorb; + uint iop_podrb; + uint iop_pdatb; + char res2[12]; + uint iop_pdirc; + uint iop_pparc; + uint iop_psorc; + uint iop_podrc; + uint iop_pdatc; + char res3[12]; + uint iop_pdird; + uint iop_ppard; + uint iop_psord; + uint iop_podrd; + uint iop_pdatd; + char res4[12]; +} iop8260_t; + +/* Communication Processor Module Timers +*/ +typedef struct cpm_timers { + u_char cpmt_tgcr1; + char res1[3]; + u_char cpmt_tgcr2; + char res2[11]; + ushort cpmt_tmr1; + ushort cpmt_tmr2; + ushort cpmt_trr1; + ushort cpmt_trr2; + ushort cpmt_tcr1; + ushort cpmt_tcr2; + ushort cpmt_tcn1; + ushort cpmt_tcn2; + ushort cpmt_tmr3; + ushort cpmt_tmr4; + ushort cpmt_trr3; + ushort cpmt_trr4; + ushort cpmt_tcr3; + ushort cpmt_tcr4; + ushort cpmt_tcn3; + ushort cpmt_tcn4; + ushort cpmt_ter1; + ushort cpmt_ter2; + ushort cpmt_ter3; + ushort cpmt_ter4; + char res3[584]; +} cpmtimer8260_t; + +/* DMA control/status registers. +*/ +typedef struct sdma_csr { + char res0[24]; + u_char sdma_sdsr; + char res1[3]; + u_char sdma_sdmr; + char res2[3]; + u_char sdma_idsr1; + char res3[3]; + u_char sdma_idmr1; + char res4[3]; + u_char sdma_idsr2; + char res5[3]; + u_char sdma_idmr2; + char res6[3]; + u_char sdma_idsr3; + char res7[3]; + u_char sdma_idmr3; + char res8[3]; + u_char sdma_idsr4; + char res9[3]; + u_char sdma_idmr4; + char res10[707]; +} sdma8260_t; + +/* Fast controllers +*/ +typedef struct fcc { + uint fcc_gfmr; + uint fcc_fpsmr; + ushort fcc_ftodr; + char res1[2]; + ushort fcc_fdsr; + char res2[2]; + ushort fcc_fcce; + char res3[2]; + ushort fcc_fccm; + char res4[2]; + u_char fcc_fccs; + char res5[3]; + u_char fcc_ftirr_phy[4]; +} fcc_t; + +/* Fast controllers continued + */ +typedef struct fcc_c { + uint fcc_firper; + uint fcc_firer; + uint fcc_firsr_hi; + uint fcc_firsr_lo; + u_char fcc_gfemr; + char res1[15]; +} fcc_c_t; + +/* TC Layer + */ +typedef struct tclayer { + ushort tc_tcmode; + ushort tc_cdsmr; + ushort tc_tcer; + ushort tc_rcc; + ushort tc_tcmr; + ushort tc_fcc; + ushort tc_ccc; + ushort tc_icc; + ushort tc_tcc; + ushort tc_ecc; + char res1[12]; +} tclayer_t; + +/* I2C +*/ +typedef struct i2c { + u_char i2c_i2mod; + char res1[3]; + u_char i2c_i2add; + char res2[3]; + u_char i2c_i2brg; + char res3[3]; + u_char i2c_i2com; + char res4[3]; + u_char i2c_i2cer; + char res5[3]; + u_char i2c_i2cmr; + char res6[331]; +} i2c8260_t; + +typedef struct scc { /* Serial communication channels */ + uint scc_gsmrl; + uint scc_gsmrh; + ushort scc_psmr; + char res1[2]; + ushort scc_todr; + ushort scc_dsr; + ushort scc_scce; + char res2[2]; + ushort scc_sccm; + char res3; + u_char scc_sccs; + char res4[8]; +} scc_t; + +typedef struct smc { /* Serial management channels */ + char res1[2]; + ushort smc_smcmr; + char res2[2]; + u_char smc_smce; + char res3[3]; + u_char smc_smcm; + char res4[5]; +} smc_t; + +/* Serial Peripheral Interface. +*/ +typedef struct im_spi { + ushort spi_spmode; + char res1[4]; + u_char spi_spie; + char res2[3]; + u_char spi_spim; + char res3[2]; + u_char spi_spcom; + char res4[82]; +} im_spi_t; + +/* CPM Mux. +*/ +typedef struct cpmux { + u_char cmx_si1cr; + char res1; + u_char cmx_si2cr; + char res2; + uint cmx_fcr; + uint cmx_scr; + u_char cmx_smr; + char res3; + ushort cmx_uar; + char res4[16]; +} cpmux_t; + +/* SIRAM control +*/ +typedef struct siram { + ushort si_amr; + ushort si_bmr; + ushort si_cmr; + ushort si_dmr; + u_char si_gmr; + char res1; + u_char si_cmdr; + char res2; + u_char si_str; + char res3; + ushort si_rsr; +} siramctl_t; + +typedef struct mcc { + ushort mcc_mcce; + char res1[2]; + ushort mcc_mccm; + char res2[2]; + u_char mcc_mccf; + char res3[7]; +} mcc_t; + +typedef struct comm_proc { + uint cp_cpcr; + uint cp_rccr; + char res1[14]; + ushort cp_rter; + char res2[2]; + ushort cp_rtmr; + ushort cp_rtscr; + char res3[2]; + uint cp_rtsr; + char res4[12]; +} cpm8260_t; + +/* ...and the whole thing wrapped up.... +*/ +typedef struct immap { + /* Some references are into the unique and known dpram spaces, + * others are from the generic base. + */ +#define im_dprambase im_dpram1 + u_char im_dpram1[16*1024]; + char res1[16*1024]; + u_char im_dpram2[4*1024]; + char res2[8*1024]; + u_char im_dpram3[4*1024]; + char res3[16*1024]; + + sysconf8260_t im_siu_conf; /* SIU Configuration */ + memctl8260_t im_memctl; /* Memory Controller */ + sit8260_t im_sit; /* System Integration Timers */ + pci8260_t im_pci; /* PCI Configuration */ + intctl8260_t im_intctl; /* Interrupt Controller */ + car8260_t im_clkrst; /* Clocks and reset */ + iop8260_t im_ioport; /* IO Port control/status */ + cpmtimer8260_t im_cpmtimer; /* CPM timers */ + sdma8260_t im_sdma; /* SDMA control/status */ + + fcc_t im_fcc[3]; /* Three FCCs */ + + char res4[32]; + fcc_c_t im_fcc_c[3]; /* Continued FCCs */ + char res4a[32]; + + tclayer_t im_tclayer[8]; /* Eight TCLayers */ + ushort tc_tcgsr; + ushort tc_tcger; + + /* First set of baud rate generators. + */ + char res4b[236]; + uint im_brgc5; + uint im_brgc6; + uint im_brgc7; + uint im_brgc8; + + char res5[608]; + + i2c8260_t im_i2c; /* I2C control/status */ + cpm8260_t im_cpm; /* Communication processor */ + + /* Second set of baud rate generators. + */ + uint im_brgc1; + uint im_brgc2; + uint im_brgc3; + uint im_brgc4; + + scc_t im_scc[4]; /* Four SCCs */ + smc_t im_smc[2]; /* Couple of SMCs */ + im_spi_t im_spi; /* A SPI */ + cpmux_t im_cpmux; /* CPM clock route mux */ + siramctl_t im_siramctl1; /* First SI RAM Control */ + mcc_t im_mcc1; /* First MCC */ + siramctl_t im_siramctl2; /* Second SI RAM Control */ + mcc_t im_mcc2; /* Second MCC */ + + char res6[1184]; + + ushort im_si1txram[256]; + char res7[512]; + ushort im_si1rxram[256]; + char res8[512]; + ushort im_si2txram[256]; + char res9[512]; + ushort im_si2rxram[256]; + char res10[512]; + char res11[4096]; +} immap_t; + +#endif /* __IMMAP_82XX__ */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h new file mode 100644 index 0000000..6c2c712 --- /dev/null +++ b/include/asm-ppc/immap_83xx.h @@ -0,0 +1,1049 @@ +/* + * MPC8349 Internal Memory Map + * Copyright (c) 2004 Freescale Semiconductor. + * Eran Liberty (liberty@freescale.com) + * + * based on: + * - MPC8260 Internal Memory Map + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * - MPC85xx Internal Memory Map + * Copyright(c) 2002,2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) + */ +#ifndef __IMMAP_8349__ +#define __IMMAP_8349__ + +#include +#include + +/* + * Local Access Window. + */ +typedef struct law8349 { + u32 bar; /* LBIU local access window base address register */ +/* Identifies the 20 most-significant address bits of the base of local + * access window n. The specified base address should be aligned to the + * window size, as defined by LBLAWARn[SIZE]. + */ +#define LAWBAR_BAR 0xFFFFF000 +#define LAWBAR_RES ~(LAWBAR_BAR) + u32 ar; /* LBIU local access window attribute register */ +} law8349_t; + +/* + * System configuration registers. + */ +typedef struct sysconf8349 { + u32 immrbar; /* Internal memory map base address register */ + u8 res0[0x04]; + u32 altcbar; /* Alternate configuration base address register */ +/* Identifies the12 most significant address bits of an alternate base + * address used for boot sequencer configuration accesses. + */ +#define ALTCBAR_BASE_ADDR 0xFFF00000 +#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ + u8 res1[0x14]; + law8349_t lblaw[4]; /* LBIU local access window */ + u8 res2[0x20]; + law8349_t pcilaw[2]; /* PCI local access window */ + u8 res3[0x30]; + law8349_t ddrlaw[2]; /* DDR local access window */ + u8 res4[0x50]; + u32 sgprl; /* System General Purpose Register Low */ + u32 sgprh; /* System General Purpose Register High */ + u32 spridr; /* System Part and Revision ID Register */ +#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ + u8 res5[0x04]; + u32 spcr; /* System Priority Configuration Register */ +#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ +#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ +#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ +#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ +#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ +#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ +#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */ +#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ +#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ +#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ +#define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \ + | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \ + | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) + u32 sicrl; /* System General Purpose Register Low */ +#define SICRL_LDP_A 0x80000000 +#define SICRL_USB0 0x40000000 +#define SICRL_USB1 0x20000000 +#define SICRL_UART 0x0C000000 +#define SICRL_GPIO1_A 0x02000000 +#define SICRL_GPIO1_B 0x01000000 +#define SICRL_GPIO1_C 0x00800000 +#define SICRL_GPIO1_D 0x00400000 +#define SICRL_GPIO1_E 0x00200000 +#define SICRL_GPIO1_F 0x00180000 +#define SICRL_GPIO1_G 0x00040000 +#define SICRL_GPIO1_H 0x00020000 +#define SICRL_GPIO1_I 0x00010000 +#define SICRL_GPIO1_J 0x00008000 +#define SICRL_GPIO1_K 0x00004000 +#define SICRL_GPIO1_L 0x00003000 +#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \ + | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \ + | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \ + | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \ + | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L ) + u32 sicrh; /* System General Purpose Register High */ +#define SICRH_DDR 0x80000000 +#define SICRH_TSEC1_A 0x10000000 +#define SICRH_TSEC1_B 0x08000000 +#define SICRH_TSEC1_C 0x04000000 +#define SICRH_TSEC1_D 0x02000000 +#define SICRH_TSEC1_E 0x01000000 +#define SICRH_TSEC1_F 0x00800000 +#define SICRH_TSEC2_A 0x00400000 +#define SICRH_TSEC2_B 0x00200000 +#define SICRH_TSEC2_C 0x00100000 +#define SICRH_TSEC2_D 0x00080000 +#define SICRH_TSEC2_E 0x00040000 +#define SICRH_TSEC2_F 0x00020000 +#define SICRH_TSEC2_G 0x00010000 +#define SICRH_TSEC2_H 0x00008000 +#define SICRH_GPIO2_A 0x00004000 +#define SICRH_GPIO2_B 0x00002000 +#define SICRH_GPIO2_C 0x00001000 +#define SICRH_GPIO2_D 0x00000800 +#define SICRH_GPIO2_E 0x00000400 +#define SICRH_GPIO2_F 0x00000200 +#define SICRH_GPIO2_G 0x00000180 +#define SICRH_GPIO2_H 0x00000060 +#define SICRH_TSOBI1 0x00000002 +#define SICRH_TSOBI2 0x00000001 +#define SICRh_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \ + | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \ + | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \ + | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \ + | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \ + | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \ + | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \ + | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \ + | SICRH_TSOBI2) + u8 res6[0xE4]; +} sysconf8349_t; + +/* + * Watch Dog Timer (WDT) Registers + */ +typedef struct wdt8349 { + u8 res0[4]; + u32 swcrr; /* System watchdog control register */ + u32 swcnr; /* System watchdog count register */ +#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. +#define SWCNR_RES ~(SWCNR_SWCN) + u8 res1[2]; + u16 swsrr; /* System watchdog service register */ + u8 res2[0xF0]; +} wdt8349_t; + +/* + * RTC/PIT Module Registers + */ +typedef struct rtclk8349 { + u32 cnr; /* control register */ +#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ +#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ +#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ +#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ +#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) + u32 ldr; /* load register */ + u32 psr; /* prescale register */ + u32 ctr; /* register */ + u32 evr; /* event register */ +#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ +#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ +#define RTEVR_RES ~(EVR_SIF | EVR_AIF) + u32 alr; /* alarm register */ + u8 res0[0xE8]; +} rtclk8349_t; + +/* + * Global timper module + */ + +typedef struct gtm8349 { + u8 cfr1; /* Timer1/2 Configuration */ +#define CFR1_PCAS 0x80 /* Pair Cascade mode */ +#define CFR1_BCM 0x40 /* Backward compatible mode */ +#define CFR1_STP2 0x20 /* Stop timer */ +#define CFR1_RST2 0x10 /* Reset timer */ +#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ +#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ +#define CFR1_STP1 0x02 /* Stop timer */ +#define CFR1_RST1 0x01 /* Reset timer */ + u8 res0[3]; + u8 cfr2; /* Timer3/4 Configuration */ +#define CFR2_PCAS 0x80 /* Pair Cascade mode */ +#define CFR2_SCAS 0x40 /* Super Cascade mode */ +#define CFR2_STP4 0x20 /* Stop timer */ +#define CFR2_RST4 0x10 /* Reset timer */ +#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ +#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ +#define CFR2_STP3 0x02 /* Stop timer */ +#define CFR2_RST3 0x01 /* Reset timer */ + u8 res1[10]; + u16 mdr1; /* Timer1 Mode Register */ +#define MDR_SPS 0xff00 /* Secondary Prescaler value */ +#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ +#define MDR_OM 0x0020 /* Output mode */ +#define MDR_ORI 0x0010 /* Output reference interrupt enable */ +#define MDR_FRR 0x0008 /* Free run/restart */ +#define MDR_ICLK 0x0006 /* Input clock source for the timer */ +#define MDR_GE 0x0001 /* Gate enable */ + u16 mdr2; /* Timer2 Mode Register */ + u16 rfr1; /* Timer1 Reference Register */ + u16 rfr2; /* Timer2 Reference Register */ + u16 cpr1; /* Timer1 Capture Register */ + u16 cpr2; /* Timer2 Capture Register */ + u16 cnr1; /* Timer1 Counter Register */ + u16 cnr2; /* Timer2 Counter Register */ + u16 mdr3; /* Timer3 Mode Register */ + u16 mdr4; /* Timer4 Mode Register */ + u16 rfr3; /* Timer3 Reference Register */ + u16 rfr4; /* Timer4 Reference Register */ + u16 cpr3; /* Timer3 Capture Register */ + u16 cpr4; /* Timer4 Capture Register */ + u16 cnr3; /* Timer3 Counter Register */ + u16 cnr4; /* Timer4 Counter Register */ + u16 evr1; /* Timer1 Event Register */ + u16 evr2; /* Timer2 Event Register */ + u16 evr3; /* Timer3 Event Register */ + u16 evr4; /* Timer4 Event Register */ +#define GTEVR_REF 0x0002 /* Output reference event */ +#define GTEVR_CAP 0x0001 /* Counter Capture event */ +#define GTEVR_RES ~(EVR_CAP|EVR_REF) + u16 psr1; /* Timer1 Prescaler Register */ + u16 psr2; /* Timer2 Prescaler Register */ + u16 psr3; /* Timer3 Prescaler Register */ + u16 psr4; /* Timer4 Prescaler Register */ + u8 res[0xC0]; +} gtm8349_t; + +/* + * Integrated Programmable Interrupt Controller + */ +typedef struct ipic8349 { + u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ +#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ +#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ +#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ +#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */ +#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */ +#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */ +#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT) + u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */ +#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ +#define SICVR_IVEC 0x0000007f /* Interrupt vector */ +#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) + u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ +#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ +#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ +#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ +#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ +#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ +#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */ +#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */ +#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ +#define SIIH_UART1 0x00000080 /* UART1 interrupt */ +#define SIIH_UART2 0x00000040 /* UART2 interrupt */ +#define SIIH_SEC 0x00000020 /* SEC interrupt */ +#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ +#define SIIH_I2C2 0x00000002 /* I2C1 interrupt */ +#define SIIH_SPI 0x00000001 /* SPI interrupt */ +#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ + | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ + | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \ + | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \ + | SIIH_I2C2 | SIIH_SPI) + u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ +#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ +#define SIIL_PIT 0x40000000 /* PIT interrupt */ +#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ +#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ +#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ +#define SIIL_MU 0x04000000 /* Message Unit interrupt */ +#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */ +#define SIIL_DMA 0x01000000 /* DMA interrupt */ +#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ +#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ +#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ +#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ +#define SIIL_DDR 0x00080000 /* DDR interrupt */ +#define SIIL_LBC 0x00040000 /* LBC interrupt */ +#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */ +#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */ +#define SIIL_PMC 0x00008000 /* PMC interrupt */ +#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */ +#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */ +#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ +#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ +#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ +#define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ + | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ + | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \ + | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \ + | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \ + | SIIL_GTM5 |SIIL_DPTC ) + u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ + u8 res0[8]; + u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ + u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */ + u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */ + u8 res1[4]; + u32 sepnr; /* System External Interrupt Pending Register (SEI) */ + u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */ + u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */ +#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */ +#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */ +#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */ +#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */ +#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */ +#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */ +#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */ +#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */ +#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7) + u32 semsr; /* System External Interrupt Mask Register (SEI) */ +#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */ +#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */ +#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */ +#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */ +#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */ +#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */ +#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ +#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ +#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ +#define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \ + | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \ + | SEI_SIRQ0) + u32 secnr; /* System External Interrupt Control Register (SECNR) */ +#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ +#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ +#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ +#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ +#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */ +#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */ +#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */ +#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */ +#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */ +#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ +#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ +#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ +#define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \ + | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \ + | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \ + | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7) + u32 sersr; /* System Error Status Register (SERR) */ + u32 sermr; /* System Error Mask Register (SERR) */ +#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ +#define SERR_WDT 0x40000000 /* WDT MCP request */ +#define SERR_SBA 0x20000000 /* SBA MCP request */ +#define SERR_DDR 0x10000000 /* DDR MCP request */ +#define SERR_LBC 0x08000000 /* LBC MCP request */ +#define SERR_PCI1 0x04000000 /* PCI1 MCP request */ +#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ +#define SERR_MU 0x01000000 /* MU MCP request */ +#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ +#define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ + |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ + |SERR_RNC ) + u32 sercr; /* System Error Control Register (SERCR) */ +#define SERCR_MCPR 0x00000001 /* MCP Route */ +#define SERCR_RES ~(SERCR_MCPR) + u8 res2[4]; + u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ + u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ + u32 sefcr; /* System External Interrupt Force Register (SEI) */ + u32 serfr; /* System Error Force Register (SERR) */ + u8 res3[0xA0]; +} ipic8349_t; + +/* + * System Arbiter Registers + */ +typedef struct arbiter8349 { + u32 acr; /* Arbiter Configuration Register */ +#define ACR_COREDIS 0x10000000 /* Core disable. */ +#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ +#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ +#define ACR_RPTCNT 0x00000700 /* Repeat count. */ +#define ACR_APARK 0x00000030 /* Address parking. */ +#define ACR_PARKM 0x0000000F /* Parking master. */ +#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) + u32 atr; /* Arbiter Timers Register */ +#define ATR_DTO 0x00FF0000 /* Data time out. */ +#define ATR_ATO 0x000000FF /* Address time out. */ +#define ATR_RES ~(ATR_DTO|ATR_ATO) + u8 res[4]; + u32 aer; /* Arbiter Event Register (AE)*/ + u32 aidr; /* Arbiter Interrupt Definition Register (AE) */ + u32 amr; /* Arbiter Mask Register (AE) */ + u32 aeatr; /* Arbiter Event Attributes Register */ +#define AEATR_EVENT 0x07000000 /* Event type. */ +#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */ +#define AEATR_TBST 0x00000800 /* Transfer burst. */ +#define AEATR_TSIZE 0x00000700 /* Transfer Size. */ +#define AEATR_TTYPE 0x0000001F /* Transfer Type. */ +#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE) + u32 aeadr; /* Arbiter Event Address Register */ + u32 aerr; /* Arbiter Event Response Register (AE)*/ +#define AE_ETEA 0x00000020 /* Transfer error. */ +#define AE_RES_ 0x00000010 /* Reserved transfer type. */ +#define AE_ECW 0x00000008 /* External control word transfer type. */ +#define AE_AO 0x00000004 /* Address Only transfer type. */ +#define AE_DTO 0x00000002 /* Data time out. */ +#define AE_ATO 0x00000001 /* Address time out. */ +#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO) + u8 res1[0xDC]; +} arbiter8349_t; + +/* + * Reset Module + */ +typedef struct reset8349 { + u32 rcwl; /* RCWL Register */ +#define RCWL_LBIUCM 0x80000000 /* LBIUCM */ +#define RCWL_LBIUCM_SHIFT 31 +#define RCWL_DDRCM 0x40000000 /* DDRCM */ +#define RCWL_DDRCM_SHIFT 30 +#define RCWL_SVCOD 0x30000000 /* SVCOD */ +#define RCWL_SPMF 0x0f000000 /* SPMF */ +#define RCWL_SPMF_SHIFT 24 +#define RCWL_COREPLL 0x007F0000 /* COREPLL */ +#define RCWL_COREPLL_SHIFT 16 +#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ +#define RCWL_CEPDF 0x00000020 /* CEPDF */ +#define RCWL_CEPMF 0x0000001F /* CEPMF */ +#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) + u32 rcwh; /* RCHL Register */ +#define RCWH_PCIHOST 0x80000000 /* PCIHOST */ +#define RCWH_PCIHOST_SHIFT 31 +#define RCWH_PCI64 0x40000000 /* PCI64 */ +#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ +#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ +#define RCWH_COREDIS 0x08000000 /* COREDIS */ +#define RCWH_BMS 0x04000000 /* BMS */ +#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ +#define RCWH_SWEN 0x00800000 /* SWEN */ +#define RCWH_ROMLOC 0x00700000 /* ROMLOC */ +#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ +#define RCWH_TSEC2M 0x00003000 /* TSEC2M */ +#define RCWH_TPR 0x00000100 /* TPR */ +#define RCWH_TLE 0x00000008 /* TLE */ +#define RCWH_LALE 0x00000004 /* LALE */ +#define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ + | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ + | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \ + | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \ + | RCWH_TLE | RCWH_LALE) + u8 res0[8]; + u32 rsr; /* Reset status Register */ +#define RSR_RSTSRC 0xE0000000 /* Reset source */ +#define RSR_RSTSRC_SHIFT 29 +#define RSR_BSF 0x00010000 /* Boot seq. fail */ +#define RSR_BSF_SHIFT 16 +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWSR_SHIFT 13 +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_SWHR_SHIFT 12 +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JHRS_SHIFT 9 +#define RSR_JSRS 0x00000100 /* jtag sreset status */ +#define RSR_JSRS_SHIFT 8 +#define RSR_CSHR 0x00000010 /* checkstop reset status */ +#define RSR_CSHR_SHIFT 4 +#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +#define RSR_SWRS_SHIFT 3 +#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +#define RSR_BMRS_SHIFT 2 +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_SRS_SHIFT 1 +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_HRS_SHIFT 0 +#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS) + u32 rmr; /* Reset mode Register */ +#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +#define RMR_CSRE_SHIFT 0 +#define RMR_RES ~(RMR_CSRE) + u32 rpr; /* Reset protection Register */ + u32 rcr; /* Reset Control Register */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_RES ~(RCR_SWHR | RCR_SWSR) + u32 rcer; /* Reset Control Enable Register */ +#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_RES ~(RCER_CRE) + u8 res1[0xDC]; +} reset8349_t; + +typedef struct clk8349 { + u32 spmr; /* system PLL mode Register */ +#define SPMR_LBIUCM 0x80000000 /* LBIUCM */ +#define SPMR_DDRCM 0x40000000 /* DDRCM */ +#define SPMR_SVCOD 0x30000000 /* SVCOD */ +#define SPMR_SPMF 0x0F000000 /* SPMF */ +#define SPMR_CKID 0x00800000 /* CKID */ +#define SPMR_CKID_SHIFT 23 +#define SPMR_COREPLL 0x007F0000 /* COREPLL */ +#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ +#define SPMR_CEPDF 0x00000020 /* CEPDF */ +#define SPMR_CEPMF 0x0000001F /* CEPMF */ +#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ + | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ + | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF) + u32 occr; /* output clock control Register */ +#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ +#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ +#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ +#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ +#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ +#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ +#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */ +#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */ +#define OCCR_PCICD0 0x00800000 /* PCICD0 */ +#define OCCR_PCICD1 0x00400000 /* PCICD1 */ +#define OCCR_PCICD2 0x00200000 /* PCICD2 */ +#define OCCR_PCICD3 0x00100000 /* PCICD3 */ +#define OCCR_PCICD4 0x00080000 /* PCICD4 */ +#define OCCR_PCICD5 0x00040000 /* PCICD5 */ +#define OCCR_PCICD6 0x00020000 /* PCICD6 */ +#define OCCR_PCICD7 0x00010000 /* PCICD7 */ +#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ +#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ +#define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \ + | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \ + | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \ + | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \ + | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \ + | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR ) + u32 sccr; /* system clock control Register */ +#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ +#define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ +#define SCCR_TSEC2CM_SHIFT 28 +#define SCCR_ENCCM 0x03000000 /* ENCCM */ +#define SCCR_ENCCM_SHIFT 24 +#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ +#define SCCR_USBMPHCM_SHIFT 22 +#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ +#define SCCR_USBDRCM_SHIFT 20 +#define SCCR_PCICM 0x00010000 /* PCICM */ +#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ + | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM) + u8 res0[0xF4]; +} clk8349_t; + +/* + * Power Management Control Module + */ +typedef struct pmc8349 { + u32 pmccr; /* PMC Configuration Register */ +#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ +#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ +#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) + u32 pmcer; /* PMC Event Register */ +#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ +#define PMCER_RES ~(PMCER_PMCI) + u32 pmcmr; /* PMC Mask Register */ +#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ +#define PMCMR_RES ~(PMCMR_PMCIE) + u8 res0[0xF4]; +} pmc8349_t; + + +/* + * general purpose I/O module + */ +typedef struct gpio8349 { + u32 dir; /* direction register */ + u32 odr; /* open drain register */ + u32 dat; /* data register */ + u32 ier; /* interrupt event register */ + u32 imr; /* interrupt mask register */ + u32 icr; /* external interrupt control register */ + u8 res0[0xE8]; +} gpio8349_t; + +/* + * DDR Memory Controller Memory Map + */ +typedef struct ddr_cs_bnds{ + u32 csbnds; +#define CSBNDS_SA 0x00FF0000 +#define CSBNDS_SA_SHIFT 8 +#define CSBNDS_EA 0x000000FF +#define CSBNDS_EA_SHIFT 24 + u8 res0[4]; +} ddr_cs_bnds_t; + +typedef struct ddr8349{ + ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ + u8 res0[0x60]; + u32 cs_config[4]; /**< Chip Select x Configuration */ +#define CSCONFIG_EN 0x80000000 +#define CSCONFIG_AP 0x00800000 +#define CSCONFIG_ROW_BIT 0x00000700 +#define CSCONFIG_ROW_BIT_12 0x00000000 +#define CSCONFIG_ROW_BIT_13 0x00000100 +#define CSCONFIG_ROW_BIT_14 0x00000200 +#define CSCONFIG_COL_BIT 0x00000007 +#define CSCONFIG_COL_BIT_8 0x00000000 +#define CSCONFIG_COL_BIT_9 0x00000001 +#define CSCONFIG_COL_BIT_10 0x00000002 +#define CSCONFIG_COL_BIT_11 0x00000003 + u8 res1[0x78]; + u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */ +#define TIMING_CFG1_PRETOACT 0x70000000 +#define TIMING_CFG1_PRETOACT_SHIFT 28 +#define TIMING_CFG1_ACTTOPRE 0x0F000000 +#define TIMING_CFG1_ACTTOPRE_SHIFT 24 +#define TIMING_CFG1_ACTTORW 0x00700000 +#define TIMING_CFG1_ACTTORW_SHIFT 20 +#define TIMING_CFG1_CASLAT 0x00070000 +#define TIMING_CFG1_CASLAT_SHIFT 16 +#define TIMING_CFG1_REFREC 0x0000F000 +#define TIMING_CFG1_REFREC_SHIFT 12 +#define TIMING_CFG1_WRREC 0x00000700 +#define TIMING_CFG1_WRREC_SHIFT 8 +#define TIMING_CFG1_ACTTOACT 0x00000070 +#define TIMING_CFG1_ACTTOACT_SHIFT 4 +#define TIMING_CFG1_WRTORD 0x00000007 +#define TIMING_CFG1_WRTORD_SHIFT 0 +#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ +#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ + + u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ +#define TIMING_CFG2_CPO 0x0F000000 +#define TIMING_CFG2_CPO_SHIFT 24 +#define TIMING_CFG2_ACSM 0x00080000 +#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 +#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 +#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ + + u32 sdram_cfg; /**< SDRAM Control Configuration */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 + + u8 res2[4]; + u32 sdram_mode; /**< SDRAM Mode Configuration */ +#define SDRAM_MODE_ESD 0xFFFF0000 +#define SDRAM_MODE_ESD_SHIFT 16 +#define SDRAM_MODE_SD 0x0000FFFF +#define SDRAM_MODE_SD_SHIFT 0 +#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ +#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ +#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ +#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ +#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ +#define DDR_MODE_WEAK 0x0002 /* weak drivers */ +#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ +#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ +#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ +#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ +#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ +#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ +#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ +#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ +#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ +#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ +#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ +#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ +#define DDR_MODE_MODEREG 0x0000 /* select mode register */ + + u8 res3[8]; + u32 sdram_interval; /**< SDRAM Interval Configuration */ +#define SDRAM_INTERVAL_REFINT 0x3FFF0000 +#define SDRAM_INTERVAL_REFINT_SHIFT 16 +#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF +#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 + u8 res9[8]; + u32 sdram_clk_cntl; +#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 + + u8 res4[0xCCC]; + u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ + u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ + u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ + u8 res5[0x14]; + u32 capture_data_hi; /**< Memory Data Path Read Capture High */ + u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ + u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ + u8 res6[0x14]; + u32 err_detect; /**< Memory Error Detect */ + u32 err_disable; /**< Memory Error Disable */ + u32 err_int_en; /**< Memory Error Interrupt Enable */ + u32 capture_attributes; /**< Memory Error Attributes Capture */ + u32 capture_address; /**< Memory Error Address Capture */ + u32 capture_ext_address;/**< Memory Error Extended Address Capture */ + u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ + u8 res7[0xA4]; + u32 debug_reg; + u8 res8[0xFC]; +} ddr8349_t; + +/* + * I2C1 Controller + */ + + +/* + * DUART + */ +typedef struct duart8349{ + u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */ + u8 uier_udmb; /**< combined register for UIER and UDMB */ + u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */ + u8 ulcr; /**< line control register */ + u8 umcr; /**< MODEM control register */ + u8 ulsr; /**< line status register */ + u8 umsr; /**< MODEM status register */ + u8 uscr; /**< scratch register */ + u8 res0[8]; + u8 udsr; /**< DMA status register */ + u8 res1[3]; + u8 res2[0xEC]; +} duart8349_t; + +/* + * Local Bus Controller Registers + */ +typedef struct lbus_bank{ + u32 br; /**< Base Register */ + u32 or; /**< Base Register */ +} lbus_bank_t; + +typedef struct lbus8349 { + lbus_bank_t bank[8]; + u8 res0[0x28]; + u32 mar; /**< UPM Address Register */ + u8 res1[0x4]; + u32 mamr; /**< UPMA Mode Register */ + u32 mbmr; /**< UPMB Mode Register */ + u32 mcmr; /**< UPMC Mode Register */ + u8 res2[0x8]; + u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ + u32 mdr; /**< UPM Data Register */ + u8 res3[0x8]; + u32 lsdmr; /**< SDRAM Mode Register */ + u8 res4[0x8]; + u32 lurt; /**< UPM Refresh Timer */ + u32 lsrt; /**< SDRAM Refresh Timer */ + u8 res5[0x8]; + u32 ltesr; /**< Transfer Error Status Register */ + u32 ltedr; /**< Transfer Error Disable Register */ + u32 lteir; /**< Transfer Error Interrupt Register */ + u32 lteatr; /**< Transfer Error Attributes Register */ + u32 ltear; /**< Transfer Error Address Register */ + u8 res6[0xC]; + u32 lbcr; /**< Configuration Register */ +#define LBCR_LDIS 0x80000000 +#define LBCR_LDIS_SHIFT 31 +#define LBCR_BCTLC 0x00C00000 +#define LBCR_BCTLC_SHIFT 22 +#define LBCR_LPBSE 0x00020000 +#define LBCR_LPBSE_SHIFT 17 +#define LBCR_EPAR 0x00010000 +#define LBCR_EPAR_SHIFT 16 +#define LBCR_BMT 0x0000FF00 +#define LBCR_BMT_SHIFT 8 + u32 lcrr; /**< Clock Ratio Register */ +#define LCRR_DBYP 0x80000000 +#define LCRR_DBYP_SHIFT 31 +#define LCRR_BUFCMDC 0x30000000 +#define LCRR_BUFCMDC_SHIFT 28 +#define LCRR_ECL 0x03000000 +#define LCRR_ECL_SHIFT 24 +#define LCRR_EADC 0x00030000 +#define LCRR_EADC_SHIFT 16 +#define LCRR_CLKDIV 0x0000000F +#define LCRR_CLKDIV_SHIFT 0 + + + u8 res7[0x28]; + u8 res8[0xF00]; +} lbus8349_t; + +/* + * Serial Peripheral Interface + */ +typedef struct spi8349 +{ + u32 mode; /**< mode register */ + u32 event; /**< event register */ + u32 mask; /**< mask register */ + u32 com; /**< command register */ + u8 res0[0x10]; + u32 tx; /**< transmit register */ + u32 rx; /**< receive register */ + u8 res1[0xD8]; +} spi8349_t; + +typedef struct dma8349 { + u8 fixme[0x300]; +} dma8349_t; + +/* + * PCI Software Configuration Registers + */ +typedef struct pciconf8349 { + u32 config_address; +#define PCI_CONFIG_ADDRESS_EN 0x80000000 +#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 +#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 +#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 +#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 +#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 +#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 +#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 +#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc + u32 config_data; + u32 int_ack; + u8 res[116]; +} pciconf8349_t; + +/* + * PCI Outbound Translation Register + */ +typedef struct pci_outbound_window { + u32 potar; + u8 res0[4]; + u32 pobar; + u8 res1[4]; + u32 pocmr; + u8 res2[4]; +} pot8349_t; +/* + * Sequencer + */ +typedef struct ios8349 { + pot8349_t pot[6]; +#define POTAR_TA_MASK 0x000fffff +#define POBAR_BA_MASK 0x000fffff +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ +#define POCMR_SE 0x20000000 /* streaming enable */ +#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2*/ +#define POCMR_CM_MASK 0x000fffff +#define POCMR_CM_4G 0x00000000 +#define POCMR_CM_2G 0x00080000 +#define POCMR_CM_1G 0x000C0000 +#define POCMR_CM_512M 0x000E0000 +#define POCMR_CM_256M 0x000F0000 +#define POCMR_CM_128M 0x000F8000 +#define POCMR_CM_64M 0x000FC000 +#define POCMR_CM_32M 0x000FE000 +#define POCMR_CM_16M 0x000FF000 +#define POCMR_CM_8M 0x000FF800 +#define POCMR_CM_4M 0x000FFC00 +#define POCMR_CM_2M 0x000FFE00 +#define POCMR_CM_1M 0x000FFF00 +#define POCMR_CM_512K 0x000FFF80 +#define POCMR_CM_256K 0x000FFFC0 +#define POCMR_CM_128K 0x000FFFE0 +#define POCMR_CM_64K 0x000FFFF0 +#define POCMR_CM_32K 0x000FFFF8 +#define POCMR_CM_16K 0x000FFFFC +#define POCMR_CM_8K 0x000FFFFE +#define POCMR_CM_4K 0x000FFFFF + u8 res0[0x60]; + u32 pmcr; + u8 res1[4]; + u32 dtcr; + u8 res2[4]; +} ios8349_t; + +/* + * PCI Controller Control and Status Registers + */ +typedef struct pcictrl8349 { + u32 esr; +#define ESR_MERR 0x80000000 +#define ESR_APAR 0x00000400 +#define ESR_PCISERR 0x00000200 +#define ESR_MPERR 0x00000100 +#define ESR_TPERR 0x00000080 +#define ESR_NORSP 0x00000040 +#define ESR_TABT 0x00000020 + u32 ecdr; +#define ECDR_APAR 0x00000400 +#define ECDR_PCISERR 0x00000200 +#define ECDR_MPERR 0x00000100 +#define ECDR_TPERR 0x00000080 +#define ECDR_NORSP 0x00000040 +#define ECDR_TABT 0x00000020 + u32 eer; +#define EER_APAR 0x00000400 +#define EER_PCISERR 0x00000200 +#define EER_MPERR 0x00000100 +#define EER_TPERR 0x00000080 +#define EER_NORSP 0x00000040 +#define EER_TABT 0x00000020 + u32 eatcr; +#define EATCR_ERRTYPR_MASK 0x70000000 +#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ +#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ +#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ +#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ +#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ +#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ +#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ +#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ +#define EATCR_BN_MASK 0x0f000000 /* beat number */ +#define EATCR_BN_1st 0x00000000 +#define EATCR_BN_2ed 0x01000000 +#define EATCR_BN_3rd 0x02000000 +#define EATCR_BN_4th 0x03000000 +#define EATCR_BN_5th 0x0400000 +#define EATCR_BN_6th 0x05000000 +#define EATCR_BN_7th 0x06000000 +#define EATCR_BN_8th 0x07000000 +#define EATCR_BN_9th 0x08000000 +#define EATCR_TS_MASK 0x00300000 /* transaction size */ +#define EATCR_TS_4 0x00000000 +#define EATCR_TS_1 0x00100000 +#define EATCR_TS_2 0x00200000 +#define EATCR_TS_3 0x00300000 +#define EATCR_ES_MASK 0x000f0000 /* error source */ +#define EATCR_ES_EM 0x00000000 /* external master */ +#define EATCR_ES_DMA 0x00050000 +#define EATCR_CMD_MASK 0x0000f000 +#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable*/ +#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ +#define EATCR_HPB 0x00000004 /* high parity bit */ +#define EATCR_PB 0x00000002 /* parity bit*/ +#define EATCR_VI 0x00000001 /* error information valid */ + u32 eacr; + u32 eeacr; + u32 edlcr; + u32 edhcr; + u32 gcr; + u32 ecr; + u32 gsr; + u8 res0[12]; + u32 pitar2; + u8 res1[4]; + u32 pibar2; + u32 piebar2; + u32 piwar2; + u8 res2[4]; + u32 pitar1; + u8 res3[4]; + u32 pibar1; + u32 piebar1; + u32 piwar1; + u8 res4[4]; + u32 pitar0; + u8 res5[4]; + u32 pibar0; + u8 res6[4]; + u32 piwar0; + u8 res7[132]; +#define PITAR_TA_MASK 0x000fffff +#define PIBAR_MASK 0xffffffff +#define PIEBAR_EBA_MASK 0x000fffff +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_SNOOP 0x00050000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_SNOOP 0x00005000 +#define PIWAR_IWS_MASK 0x0000003F +#define PIWAR_IWS_4K 0x0000000B +#define PIWAR_IWS_8K 0x0000000C +#define PIWAR_IWS_16K 0x0000000D +#define PIWAR_IWS_32K 0x0000000E +#define PIWAR_IWS_64K 0x0000000F +#define PIWAR_IWS_128K 0x00000010 +#define PIWAR_IWS_256K 0x00000011 +#define PIWAR_IWS_512K 0x00000012 +#define PIWAR_IWS_1M 0x00000013 +#define PIWAR_IWS_2M 0x00000014 +#define PIWAR_IWS_4M 0x00000015 +#define PIWAR_IWS_8M 0x00000016 +#define PIWAR_IWS_16M 0x00000017 +#define PIWAR_IWS_32M 0x00000018 +#define PIWAR_IWS_64M 0x00000019 +#define PIWAR_IWS_128M 0x0000001A +#define PIWAR_IWS_256M 0x0000001B +#define PIWAR_IWS_512M 0x0000001C +#define PIWAR_IWS_1G 0x0000001D +#define PIWAR_IWS_2G 0x0000001E +} pcictrl8349_t; + +/* + * USB + */ +typedef struct usb8349 { + u8 fixme[0x2000]; +} usb8349_t; + +/* + * TSEC + */ +typedef struct tsec8349 { + u8 fixme[0x1000]; +} tsec8349_t; + +/* + * Security + */ +typedef struct security8349 { + u8 fixme[0x10000]; +} security8349_t; + +typedef struct immap { + sysconf8349_t sysconf; /* System configuration */ + wdt8349_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk8349_t rtc; /* Real Time Clock Module Registers */ + rtclk8349_t pit; /* Periodic Interval Timer */ + gtm8349_t gtm[2]; /* Global Timers Module */ + ipic8349_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter8349_t arbiter; /* System Arbiter Registers */ + reset8349_t reset; /* Reset Module */ + clk8349_t clk; /* System Clock Module */ + pmc8349_t pmc; /* Power Management Control Module */ + gpio8349_t pgio[2]; /* general purpose I/O module */ + u8 res0[0x200]; + u8 DDL_DDR[0x100]; + u8 DDL_LBIU[0x100]; + u8 res1[0xE00]; + ddr8349_t ddr; /* DDR Memory Controller Memory */ + i2c_t i2c[2]; /* I2C1 Controller */ + u8 res2[0x1300]; + duart8349_t duart[2];/* DUART */ + u8 res3[0x900]; + lbus8349_t lbus; /* Local Bus Controller Registers */ + u8 res4[0x1000]; + spi8349_t spi; /* Serial Peripheral Interface */ + u8 res5[0xF00]; + dma8349_t dma; /* DMA */ + pciconf8349_t pci_conf[2]; /* PCI Software Configuration Registers */ + ios8349_t ios; /* Sequencer */ + pcictrl8349_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ + u8 res6[0x19900]; + usb8349_t usb; + tsec8349_t tsec[2]; + u8 res7[0xA000]; + security8349_t security; +} immap_t; + +#endif /* __IMMAP_8349__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h new file mode 100644 index 0000000..2f10e95 --- /dev/null +++ b/include/asm-ppc/immap_85xx.h @@ -0,0 +1,1594 @@ +/* + * MPC85xx Internal Memory Map + * + * Copyright(c) 2002,2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) + * + */ + +#ifndef __IMMAP_85xx__ +#define __IMMAP_85xx__ + +/* + * Local-Access Registers and ECM Registers(0x0000-0x2000) + */ +typedef struct ccsr_local_ecm { + uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ + char res1[4]; + uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ + char res2[4]; + uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ + char res3[12]; + uint bptr; /* 0x20 - Boot Page Translation Register */ + char res4[3044]; + uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ + char res5[4]; + uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ + char res6[20]; + uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ + char res7[4]; + uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ + char res8[20]; + uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ + char res9[4]; + uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ + char res10[20]; + uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ + char res11[4]; + uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ + char res12[20]; + uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ + char res13[4]; + uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ + char res14[20]; + uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ + char res15[4]; + uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ + char res16[20]; + uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ + char res17[4]; + uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ + char res18[20]; + uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ + char res19[4]; + uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ + char res20[780]; + uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ + char res21[12]; + uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ + char res22[3564]; + uint eedr; /* 0x1e00 - ECM Error Detect Register */ + char res23[4]; + uint eeer; /* 0x1e08 - ECM Error Enable Register */ + uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */ + uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */ + char res24[492]; +} ccsr_local_ecm_t; + +/* + * DDR memory controller registers(0x2000-0x3000) + */ +typedef struct ccsr_ddr { + uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ + char res1[4]; + uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ + char res2[4]; + uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ + char res3[4]; + uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ + char res4[100]; + uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ + uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ + uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ + uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ + char res5[112]; + uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ + uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ + uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ + uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ + uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */ + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ + uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */ + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/ + uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */ + uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */ + char res6[4]; + uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ + char res7[20]; + uint init_address; /* 0x2148 - DDR training initialization address */ + uint init_ext_address; /* 0x214C - DDR training initialization extended address */ + char res8_1[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res8_2[512]; + uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ + uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ + uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ + char res9[20]; + uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ + uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ + uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ + char res10[20]; + uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ + uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ + uint err_int_en; /* 0x2e48 - DDR */ + uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ + uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ + uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ + uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ + char res11[164]; + uint debug_1; /* 0x2f00 */ + uint debug_2; + uint debug_3; + uint debug_4; + char res12[240]; +} ccsr_ddr_t; + +/* + * I2C Registers(0x3000-0x4000) + */ +typedef struct ccsr_i2c { + u_char i2cadr; /* 0x3000 - I2C Address Register */ +#define MPC85xx_I2CADR_MASK 0xFE + char res1[3]; + u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */ +#define MPC85xx_I2CFDR_MASK 0x3F + char res2[3]; + u_char i2ccr; /* 0x3008 - I2C Control Register */ +#define MPC85xx_I2CCR_MEN 0x80 +#define MPC85xx_I2CCR_MIEN 0x40 +#define MPC85xx_I2CCR_MSTA 0x20 +#define MPC85xx_I2CCR_MTX 0x10 +#define MPC85xx_I2CCR_TXAK 0x08 +#define MPC85xx_I2CCR_RSTA 0x04 +#define MPC85xx_I2CCR_BCST 0x01 + char res3[3]; + u_char i2csr; /* 0x300c - I2C Status Register */ +#define MPC85xx_I2CSR_MCF 0x80 +#define MPC85xx_I2CSR_MAAS 0x40 +#define MPC85xx_I2CSR_MBB 0x20 +#define MPC85xx_I2CSR_MAL 0x10 +#define MPC85xx_I2CSR_BCSTM 0x08 +#define MPC85xx_I2CSR_SRW 0x04 +#define MPC85xx_I2CSR_MIF 0x02 +#define MPC85xx_I2CSR_RXAK 0x01 + char res4[3]; + u_char i2cdr; /* 0x3010 - I2C Data Register */ +#define MPC85xx_I2CDR_DATA 0xFF + char res5[3]; + u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */ +#define MPC85xx_I2CDFSRR 0x3F + char res6[4075]; +} ccsr_i2c_t; + +#if defined(CONFIG_MPC8540) \ + || defined(CONFIG_MPC8541) \ + || defined(CONFIG_MPC8548) \ + || defined(CONFIG_MPC8555) +/* DUART Registers(0x4000-0x5000) */ +typedef struct ccsr_duart { + char res1[1280]; + u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ + u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ + u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ + u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ + u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ + u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ + u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ + u_char uscr1; /* 0x4507 - UART1 Scratch Register */ + char res2[8]; + u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ + char res3[239]; + u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ + u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ + u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ + u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ + u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ + u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ + u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ + u_char uscr2; /* 0x4607 - UART2 Scratch Register */ + char res4[8]; + u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ + char res5[2543]; +} ccsr_duart_t; +#else /* MPC8560 uses UART on its CPM */ +typedef struct ccsr_duart { + char res[4096]; +} ccsr_duart_t; +#endif + +/* Local Bus Controller Registers(0x5000-0x6000) */ +/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */ + +typedef struct ccsr_lbc { + uint br0; /* 0x5000 - LBC Base Register 0 */ + uint or0; /* 0x5004 - LBC Options Register 0 */ + uint br1; /* 0x5008 - LBC Base Register 1 */ + uint or1; /* 0x500c - LBC Options Register 1 */ + uint br2; /* 0x5010 - LBC Base Register 2 */ + uint or2; /* 0x5014 - LBC Options Register 2 */ + uint br3; /* 0x5018 - LBC Base Register 3 */ + uint or3; /* 0x501c - LBC Options Register 3 */ + uint br4; /* 0x5020 - LBC Base Register 4 */ + uint or4; /* 0x5024 - LBC Options Register 4 */ + uint br5; /* 0x5028 - LBC Base Register 5 */ + uint or5; /* 0x502c - LBC Options Register 5 */ + uint br6; /* 0x5030 - LBC Base Register 6 */ + uint or6; /* 0x5034 - LBC Options Register 6 */ + uint br7; /* 0x5038 - LBC Base Register 7 */ + uint or7; /* 0x503c - LBC Options Register 7 */ + char res1[40]; + uint mar; /* 0x5068 - LBC UPM Address Register */ + char res2[4]; + uint mamr; /* 0x5070 - LBC UPMA Mode Register */ + uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ + uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ + char res3[8]; + uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ + uint mdr; /* 0x5088 - LBC UPM Data Register */ + char res4[8]; + uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ + char res5[8]; + uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ + uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ + char res6[8]; + uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ + uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ + uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ + uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ + uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ + char res7[12]; + uint lbcr; /* 0x50d0 - LBC Configuration Register */ + uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ + char res8[12072]; +} ccsr_lbc_t; + +/* + * PCI Registers(0x8000-0x9000) + * Omitting Reserved(0x9000-0x2_0000) + */ +typedef struct ccsr_pcix { + uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ + uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */ + uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */ + char res1[3060]; + uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */ + uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */ + uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */ + uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */ + uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */ + char res2[12]; + uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */ + uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */ + uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */ + uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */ + uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */ + char res3[12]; + uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */ + uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */ + uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */ + uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */ + uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */ + char res4[12]; + uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */ + uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */ + uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */ + uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */ + uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */ + char res5[12]; + uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */ + uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */ + uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */ + uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */ + uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */ + char res6[268]; + uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */ + uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */ + uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */ + uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */ + uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */ + char res7[12]; + uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */ + uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */ + uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */ + uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */ + uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */ + char res8[12]; + uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */ + uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */ + uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */ + char res9[4]; + uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */ + char res10[12]; + uint pedr; /* 0x8e00 - PCIX Error Detect Register */ + uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */ + uint peer; /* 0x8e08 - PCIX Error Enable Register */ + uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */ + uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */ + uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ + uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ + uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ + char res11[94688]; +} ccsr_pcix_t; + +/* + * L2 Cache Registers(0x2_0000-0x2_1000) + */ +typedef struct ccsr_l2cache { + uint l2ctl; /* 0x20000 - L2 configuration register 0 */ + char res1[12]; + uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */ + char res2[4]; + uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */ + char res3[4]; + uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */ + char res4[4]; + uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */ + char res5[4]; + uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */ + char res6[4]; + uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */ + char res7[4]; + uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */ + char res8[4]; + uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */ + char res9[180]; + uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */ + char res10[4]; + uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */ + char res11[3316]; + uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */ + uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */ + uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */ + char res12[20]; + uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */ + uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */ + uint l2captecc; /* 0x20e28 - L2 error ECC capture register */ + char res13[20]; + uint l2errdet; /* 0x20e40 - L2 error detect register */ + uint l2errdis; /* 0x20e44 - L2 error disable register */ + uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */ + uint l2errattr; /* 0x20e4c - L2 error attributes capture register */ + uint l2erraddr; /* 0x20e50 - L2 error address capture register */ + char res14[4]; + uint l2errctl; /* 0x20e58 - L2 error control register */ + char res15[420]; +} ccsr_l2cache_t; + +/* + * DMA Registers(0x2_1000-0x2_2000) + */ +typedef struct ccsr_dma { + char res1[256]; + uint mr0; /* 0x21100 - DMA 0 Mode Register */ + uint sr0; /* 0x21104 - DMA 0 Status Register */ + char res2[4]; + uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */ + uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */ + uint sar0; /* 0x21114 - DMA 0 Source Address Register */ + uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */ + uint dar0; /* 0x2111c - DMA 0 Destination Address Register */ + uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */ + char res3[4]; + uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */ + char res4[8]; + uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */ + char res5[4]; + uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */ + uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */ + uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */ + char res6[56]; + uint mr1; /* 0x21180 - DMA 1 Mode Register */ + uint sr1; /* 0x21184 - DMA 1 Status Register */ + char res7[4]; + uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */ + uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */ + uint sar1; /* 0x21194 - DMA 1 Source Address Register */ + uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */ + uint dar1; /* 0x2119c - DMA 1 Destination Address Register */ + uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */ + char res8[4]; + uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */ + char res9[8]; + uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */ + char res10[4]; + uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */ + uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */ + uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */ + char res11[56]; + uint mr2; /* 0x21200 - DMA 2 Mode Register */ + uint sr2; /* 0x21204 - DMA 2 Status Register */ + char res12[4]; + uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */ + uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */ + uint sar2; /* 0x21214 - DMA 2 Source Address Register */ + uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */ + uint dar2; /* 0x2121c - DMA 2 Destination Address Register */ + uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */ + char res13[4]; + uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */ + char res14[8]; + uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */ + char res15[4]; + uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */ + uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */ + uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */ + char res16[56]; + uint mr3; /* 0x21280 - DMA 3 Mode Register */ + uint sr3; /* 0x21284 - DMA 3 Status Register */ + char res17[4]; + uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */ + uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */ + uint sar3; /* 0x21294 - DMA 3 Source Address Register */ + uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */ + uint dar3; /* 0x2129c - DMA 3 Destination Address Register */ + uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */ + char res18[4]; + uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */ + char res19[8]; + uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */ + char res20[4]; + uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */ + uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */ + uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */ + char res21[56]; + uint dgsr; /* 0x21300 - DMA General Status Register */ + char res22[11516]; +} ccsr_dma_t; + +/* + * tsec1 tsec2: 24000-26000 + */ +typedef struct ccsr_tsec { + char res1[16]; + uint ievent; /* 0x24010 - Interrupt Event Register */ + uint imask; /* 0x24014 - Interrupt Mask Register */ + uint edis; /* 0x24018 - Error Disabled Register */ + char res2[4]; + uint ecntrl; /* 0x24020 - Ethernet Control Register */ + uint minflr; /* 0x24024 - Minimum Frame Length Register */ + uint ptv; /* 0x24028 - Pause Time Value Register */ + uint dmactrl; /* 0x2402c - DMA Control Register */ + uint tbipa; /* 0x24030 - TBI PHY Address Register */ + char res3[88]; + uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ + char res4[8]; + uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ + uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */ + char res5[96]; + uint tctrl; /* 0x24100 - Transmit Control Register */ + uint tstat; /* 0x24104 - Transmit Status Register */ + char res6[4]; + uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */ + char res7[16]; + uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */ + uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */ + char res8[88]; + uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */ + uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */ + char res9[120]; + uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ + uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */ + char res10[168]; + uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */ + uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */ + uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */ + uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */ + uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */ + uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */ + uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */ + char res11[52]; + uint rctrl; /* 0x24300 - Receive Control Register */ + uint rstat; /* 0x24304 - Receive Status Register */ + char res12[4]; + uint rbdlen; /* 0x2430c - RxBD Data Length Register */ + char res13[16]; + uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */ + uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */ + char res14[24]; + uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ + uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */ + char res15[56]; + uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */ + uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */ + uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */ + uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */ + uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */ + uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */ + uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */ + uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */ + char res16[96]; + uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ + uint rbase; /* 0x24404 - Receive Descriptor Base Address */ + uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */ + uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */ + uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */ + uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */ + uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */ + uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */ + char res17[224]; + uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ + uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ + uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ + uint hafdup; /* 0x2450c - Half Duplex Register */ + uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ + char res18[12]; + uint miimcfg; /* 0x24520 - MII Management Configuration Register */ + uint miimcom; /* 0x24524 - MII Management Command Register */ + uint miimadd; /* 0x24528 - MII Management Address Register */ + uint miimcon; /* 0x2452c - MII Management Control Register */ + uint miimstat; /* 0x24530 - MII Management Status Register */ + uint miimind; /* 0x24534 - MII Management Indicator Register */ + char res19[4]; + uint ifstat; /* 0x2453c - Interface Status Register */ + uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ + uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ + char res20[312]; + uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ + uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ + uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ + uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ + uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ + uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ + uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ + uint rbyt; /* 0x2469c - Receive Byte Counter */ + uint rpkt; /* 0x246a0 - Receive Packet Counter */ + uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ + uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ + uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ + uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ + uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ + uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ + uint raln; /* 0x246bc - Receive Alignment Error Counter */ + uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ + uint rcde; /* 0x246c4 - Receive Code Error Counter */ + uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ + uint rund; /* 0x246cc - Receive Undersize Packet Counter */ + uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ + uint rfrg; /* 0x246d4 - Receive Fragments Counter */ + uint rjbr; /* 0x246d8 - Receive Jabber Counter */ + uint rdrp; /* 0x246dc - Receive Drop Counter */ + uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ + uint tpkt; /* 0x246e4 - Transmit Packet Counter */ + uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ + uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ + uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ + uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ + uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ + uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ + uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ + uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ + uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ + uint tncl; /* 0x2470c - Transmit Total Collision Counter */ + char res21[4]; + uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ + uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ + uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ + uint txcf; /* 0x24720 - Transmit Control Frame Counter */ + uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ + uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ + uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ + uint car1; /* 0x24730 - Carry Register One */ + uint car2; /* 0x24734 - Carry Register Two */ + uint cam1; /* 0x24738 - Carry Mask Register One */ + uint cam2; /* 0x2473c - Carry Mask Register Two */ + char res22[192]; + uint iaddr0; /* 0x24800 - Indivdual address register 0 */ + uint iaddr1; /* 0x24804 - Indivdual address register 1 */ + uint iaddr2; /* 0x24808 - Indivdual address register 2 */ + uint iaddr3; /* 0x2480c - Indivdual address register 3 */ + uint iaddr4; /* 0x24810 - Indivdual address register 4 */ + uint iaddr5; /* 0x24814 - Indivdual address register 5 */ + uint iaddr6; /* 0x24818 - Indivdual address register 6 */ + uint iaddr7; /* 0x2481c - Indivdual address register 7 */ + char res23[96]; + uint gaddr0; /* 0x24880 - Global address register 0 */ + uint gaddr1; /* 0x24884 - Global address register 1 */ + uint gaddr2; /* 0x24888 - Global address register 2 */ + uint gaddr3; /* 0x2488c - Global address register 3 */ + uint gaddr4; /* 0x24890 - Global address register 4 */ + uint gaddr5; /* 0x24894 - Global address register 5 */ + uint gaddr6; /* 0x24898 - Global address register 6 */ + uint gaddr7; /* 0x2489c - Global address register 7 */ + char res24[96]; + uint pmd0; /* 0x24900 - Pattern Match Data Register */ + char res25[4]; + uint pmask0; /* 0x24908 - Pattern Mask Register */ + char res26[4]; + uint pcntrl0; /* 0x24910 - Pattern Match Control Register */ + char res27[4]; + uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */ + uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd1; /* 0x24920 - Pattern Match Data Register */ + char res28[4]; + uint pmask1; /* 0x24928 - Pattern Mask Register */ + char res29[4]; + uint pcntrl1; /* 0x24930 - Pattern Match Control Register */ + char res30[4]; + uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */ + uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd2; /* 0x24940 - Pattern Match Data Register */ + char res31[4]; + uint pmask2; /* 0x24948 - Pattern Mask Register */ + char res32[4]; + uint pcntrl2; /* 0x24950 - Pattern Match Control Register */ + char res33[4]; + uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */ + uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd3; /* 0x24960 - Pattern Match Data Register */ + char res34[4]; + uint pmask3; /* 0x24968 - Pattern Mask Register */ + char res35[4]; + uint pcntrl3; /* 0x24970 - Pattern Match Control Register */ + char res36[4]; + uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */ + uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd4; /* 0x24980 - Pattern Match Data Register */ + char res37[4]; + uint pmask4; /* 0x24988 - Pattern Mask Register */ + char res38[4]; + uint pcntrl4; /* 0x24990 - Pattern Match Control Register */ + char res39[4]; + uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */ + uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd5; /* 0x249a0 - Pattern Match Data Register */ + char res40[4]; + uint pmask5; /* 0x249a8 - Pattern Mask Register */ + char res41[4]; + uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */ + char res42[4]; + uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */ + uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd6; /* 0x249c0 - Pattern Match Data Register */ + char res43[4]; + uint pmask6; /* 0x249c8 - Pattern Mask Register */ + char res44[4]; + uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */ + char res45[4]; + uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */ + uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd7; /* 0x249e0 - Pattern Match Data Register */ + char res46[4]; + uint pmask7; /* 0x249e8 - Pattern Mask Register */ + char res47[4]; + uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */ + char res48[4]; + uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */ + uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd8; /* 0x24a00 - Pattern Match Data Register */ + char res49[4]; + uint pmask8; /* 0x24a08 - Pattern Mask Register */ + char res50[4]; + uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */ + char res51[4]; + uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */ + uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd9; /* 0x24a20 - Pattern Match Data Register */ + char res52[4]; + uint pmask9; /* 0x24a28 - Pattern Mask Register */ + char res53[4]; + uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */ + char res54[4]; + uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */ + uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd10; /* 0x24a40 - Pattern Match Data Register */ + char res55[4]; + uint pmask10; /* 0x24a48 - Pattern Mask Register */ + char res56[4]; + uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */ + char res57[4]; + uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */ + uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd11; /* 0x24a60 - Pattern Match Data Register */ + char res58[4]; + uint pmask11; /* 0x24a68 - Pattern Mask Register */ + char res59[4]; + uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */ + char res60[4]; + uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */ + uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd12; /* 0x24a80 - Pattern Match Data Register */ + char res61[4]; + uint pmask12; /* 0x24a88 - Pattern Mask Register */ + char res62[4]; + uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */ + char res63[4]; + uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */ + uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd13; /* 0x24aa0 - Pattern Match Data Register */ + char res64[4]; + uint pmask13; /* 0x24aa8 - Pattern Mask Register */ + char res65[4]; + uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */ + char res66[4]; + uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */ + uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd14; /* 0x24ac0 - Pattern Match Data Register */ + char res67[4]; + uint pmask14; /* 0x24ac8 - Pattern Mask Register */ + char res68[4]; + uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */ + char res69[4]; + uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */ + uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */ + uint pmd15; /* 0x24ae0 - Pattern Match Data Register */ + char res70[4]; + uint pmask15; /* 0x24ae8 - Pattern Mask Register */ + char res71[4]; + uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */ + char res72[4]; + uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */ + uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */ + char res73[248]; + uint attr; /* 0x24bf8 - Attributes Register */ + uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */ + char res74[1024]; +} ccsr_tsec_t; + +/* + * PIC Registers(0x2_6000-0x4_0000-0x8_0000) + */ +typedef struct ccsr_pic { + char res0[106496]; /* 0x26000-0x40000 */ + char res1[64]; + uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ + char res2[12]; + uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ + char res3[12]; + uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ + char res4[12]; + uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ + char res5[12]; + uint ctpr; /* 0x40080 - Current Task Priority Register */ + char res6[12]; + uint whoami; /* 0x40090 - Who Am I Register */ + char res7[12]; + uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ + char res8[12]; + uint eoi; /* 0x400b0 - End Of Interrupt Register */ + char res9[3916]; + uint frr; /* 0x41000 - Feature Reporting Register */ + char res10[28]; + uint gcr; /* 0x41020 - Global Configuration Register */ +#define MPC85xx_PICGCR_RST 0x80000000 +#define MPC85xx_PICGCR_M 0x20000000 + char res11[92]; + uint vir; /* 0x41080 - Vendor Identification Register */ + char res12[12]; + uint pir; /* 0x41090 - Processor Initialization Register */ + char res13[12]; + uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ + char res14[12]; + uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ + char res15[12]; + uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ + char res16[12]; + uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ + char res17[12]; + uint svr; /* 0x410e0 - Spurious Vector Register */ + char res18[12]; + uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ + char res19[12]; + uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ + char res20[12]; + uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ + char res21[12]; + uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ + char res22[12]; + uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ + char res23[12]; + uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ + char res24[12]; + uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ + char res25[12]; + uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ + char res26[12]; + uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ + char res27[12]; + uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ + char res28[12]; + uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ + char res29[12]; + uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ + char res30[12]; + uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ + char res31[12]; + uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ + char res32[12]; + uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ + char res33[12]; + uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ + char res34[12]; + uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ + char res35[268]; + uint tcr; /* 0x41300 - Timer Control Register */ + char res36[12]; + uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ + char res37[12]; + uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ + char res38[12]; + uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ + char res39[12]; + uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ + char res40[188]; + uint msgr0; /* 0x41400 - Message Register 0 */ + char res41[12]; + uint msgr1; /* 0x41410 - Message Register 1 */ + char res42[12]; + uint msgr2; /* 0x41420 - Message Register 2 */ + char res43[12]; + uint msgr3; /* 0x41430 - Message Register 3 */ + char res44[204]; + uint mer; /* 0x41500 - Message Enable Register */ + char res45[12]; + uint msr; /* 0x41510 - Message Status Register */ + char res46[60140]; + uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ + char res47[12]; + uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ + char res48[12]; + uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ + char res49[12]; + uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ + char res50[12]; + uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ + char res51[12]; + uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ + char res52[12]; + uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ + char res53[12]; + uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ + char res54[12]; + uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ + char res55[12]; + uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ + char res56[12]; + uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ + char res57[12]; + uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ + char res58[12]; + uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ + char res59[12]; + uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ + char res60[12]; + uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ + char res61[12]; + uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ + char res62[12]; + uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ + char res63[12]; + uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ + char res64[12]; + uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ + char res65[12]; + uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ + char res66[12]; + uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ + char res67[12]; + uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ + char res68[12]; + uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ + char res69[12]; + uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ + char res70[140]; + uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ + char res71[12]; + uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ + char res72[12]; + uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ + char res73[12]; + uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ + char res74[12]; + uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ + char res75[12]; + uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ + char res76[12]; + uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ + char res77[12]; + uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ + char res78[12]; + uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ + char res79[12]; + uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ + char res80[12]; + uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ + char res81[12]; + uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ + char res82[12]; + uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ + char res83[12]; + uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ + char res84[12]; + uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ + char res85[12]; + uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ + char res86[12]; + uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ + char res87[12]; + uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ + char res88[12]; + uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ + char res89[12]; + uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ + char res90[12]; + uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ + char res91[12]; + uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ + char res92[12]; + uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ + char res93[12]; + uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ + char res94[12]; + uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ + char res95[12]; + uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ + char res96[12]; + uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ + char res97[12]; + uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ + char res98[12]; + uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ + char res99[12]; + uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ + char res100[12]; + uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ + char res101[12]; + uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ + char res102[12]; + uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ + char res103[12]; + uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ + char res104[12]; + uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ + char res105[12]; + uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ + char res106[12]; + uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ + char res107[12]; + uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ + char res108[12]; + uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ + char res109[12]; + uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ + char res110[12]; + uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ + char res111[12]; + uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ + char res112[12]; + uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ + char res113[12]; + uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ + char res114[12]; + uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ + char res115[12]; + uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ + char res116[12]; + uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ + char res117[12]; + uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ + char res118[12]; + uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ + char res119[12]; + uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ + char res120[12]; + uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ + char res121[12]; + uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ + char res122[12]; + uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ + char res123[12]; + uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ + char res124[12]; + uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ + char res125[12]; + uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ + char res126[12]; + uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ + char res127[12]; + uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ + char res128[12]; + uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ + char res129[12]; + uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ + char res130[12]; + uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ + char res131[12]; + uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ + char res132[12]; + uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ + char res133[12]; + uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ + char res134[4108]; + uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ + char res135[12]; + uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ + char res136[12]; + uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ + char res137[12]; + uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ + char res138[12]; + uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ + char res139[12]; + uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ + char res140[12]; + uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ + char res141[12]; + uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ + char res142[59852]; + uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ + char res143[12]; + uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ + char res144[12]; + uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ + char res145[12]; + uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ + char res146[12]; + uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ + char res147[12]; + uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ + char res148[12]; + uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ + char res149[12]; + uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ + char res150[130892]; +} ccsr_pic_t; + +/* + * CPM Block(0x8_0000-0xc_0000) + */ +#ifndef CONFIG_CPM2 +typedef struct ccsr_cpm { + char res[262144]; +} ccsr_cpm_t; +#else +/* + * 0x8000-0x8ffff:DPARM + * 0x9000-0x90bff: General SIU + */ +typedef struct ccsr_cpm_siu { + char res1[80]; + uint smaer; + uint smser; + uint smevr; + char res2[4]; + uint lmaer; + uint lmser; + uint lmevr; + char res3[2964]; +} ccsr_cpm_siu_t; + +/* 0x90c00-0x90cff: Interrupt Controller */ +typedef struct ccsr_cpm_intctl { + ushort sicr; + char res1[2]; + uint sivec; + uint sipnrh; + uint sipnrl; + uint siprr; + uint scprrh; + uint scprrl; + uint simrh; + uint simrl; + uint siexr; + char res2[88]; + uint sccr; + char res3[124]; +} ccsr_cpm_intctl_t; + +/* 0x90d00-0x90d7f: input/output port */ +typedef struct ccsr_cpm_iop { + uint pdira; + uint ppara; + uint psora; + uint podra; + uint pdata; + char res1[12]; + uint pdirb; + uint pparb; + uint psorb; + uint podrb; + uint pdatb; + char res2[12]; + uint pdirc; + uint pparc; + uint psorc; + uint podrc; + uint pdatc; + char res3[12]; + uint pdird; + uint ppard; + uint psord; + uint podrd; + uint pdatd; + char res4[12]; +} ccsr_cpm_iop_t; + +/* 0x90d80-0x91017: CPM timers */ +typedef struct ccsr_cpm_timer { + u_char tgcr1; + char res1[3]; + u_char tgcr2; + char res2[11]; + ushort tmr1; + ushort tmr2; + ushort trr1; + ushort trr2; + ushort tcr1; + ushort tcr2; + ushort tcn1; + ushort tcn2; + ushort tmr3; + ushort tmr4; + ushort trr3; + ushort trr4; + ushort tcr3; + ushort tcr4; + ushort tcn3; + ushort tcn4; + ushort ter1; + ushort ter2; + ushort ter3; + ushort ter4; + char res3[608]; +} ccsr_cpm_timer_t; + +/* 0x91018-0x912ff: SDMA */ +typedef struct ccsr_cpm_sdma { + uchar sdsr; + char res1[3]; + uchar sdmr; + char res2[739]; +} ccsr_cpm_sdma_t; + +/* 0x91300-0x9131f: FCC1 */ +typedef struct ccsr_cpm_fcc1 { + uint gfmr; + uint fpsmr; + ushort ftodr; + char res1[2]; + ushort fdsr; + char res2[2]; + ushort fcce; + char res3[2]; + ushort fccm; + char res4[2]; + u_char fccs; + char res5[3]; + u_char ftirr_phy[4]; +} ccsr_cpm_fcc1_t; + +/* 0x91320-0x9133f: FCC2 */ +typedef struct ccsr_cpm_fcc2 { + uint gfmr; + uint fpsmr; + ushort ftodr; + char res1[2]; + ushort fdsr; + char res2[2]; + ushort fcce; + char res3[2]; + ushort fccm; + char res4[2]; + u_char fccs; + char res5[3]; + u_char ftirr_phy[4]; +} ccsr_cpm_fcc2_t; + +/* 0x91340-0x9137f: FCC3 */ +typedef struct ccsr_cpm_fcc3 { + uint gfmr; + uint fpsmr; + ushort ftodr; + char res1[2]; + ushort fdsr; + char res2[2]; + ushort fcce; + char res3[2]; + ushort fccm; + char res4[2]; + u_char fccs; + char res5[3]; + char res[36]; +} ccsr_cpm_fcc3_t; + +/* 0x91380-0x9139f: FCC1 extended */ +typedef struct ccsr_cpm_fcc1_ext { + uint firper; + uint firer; + uint firsr_h; + uint firsr_l; + u_char gfemr; + char res[15]; + +} ccsr_cpm_fcc1_ext_t; + +/* 0x913a0-0x913cf: FCC2 extended */ +typedef struct ccsr_cpm_fcc2_ext { + uint firper; + uint firer; + uint firsr_h; + uint firsr_l; + u_char gfemr; + char res[31]; +} ccsr_cpm_fcc2_ext_t; + +/* 0x913d0-0x913ff: FCC3 extended */ +typedef struct ccsr_cpm_fcc3_ext { + u_char gfemr; + char res[47]; +} ccsr_cpm_fcc3_ext_t; + +/* 0x91400-0x915ef: TC layers */ +typedef struct ccsr_cpm_tmp1 { + char res[496]; +} ccsr_cpm_tmp1_t; + +/* 0x915f0-0x9185f: BRGs:5,6,7,8 */ +typedef struct ccsr_cpm_brg2 { + uint brgc5; + uint brgc6; + uint brgc7; + uint brgc8; + char res[608]; +} ccsr_cpm_brg2_t; + +/* 0x91860-0x919bf: I2C */ +typedef struct ccsr_cpm_i2c { + u_char i2mod; + char res1[3]; + u_char i2add; + char res2[3]; + u_char i2brg; + char res3[3]; + u_char i2com; + char res4[3]; + u_char i2cer; + char res5[3]; + u_char i2cmr; + char res6[331]; +} ccsr_cpm_i2c_t; + +/* 0x919c0-0x919ef: CPM core */ +typedef struct ccsr_cpm_cp { + uint cpcr; + uint rccr; + char res1[14]; + ushort rter; + char res2[2]; + ushort rtmr; + ushort rtscr; + char res3[2]; + uint rtsr; + char res4[12]; +} ccsr_cpm_cp_t; + +/* 0x919f0-0x919ff: BRGs:1,2,3,4 */ +typedef struct ccsr_cpm_brg1 { + uint brgc1; + uint brgc2; + uint brgc3; + uint brgc4; +} ccsr_cpm_brg1_t; + +/* 0x91a00-0x91a9f: SCC1-SCC4 */ +typedef struct ccsr_cpm_scc { + uint gsmrl; + uint gsmrh; + ushort psmr; + char res1[2]; + ushort todr; + ushort dsr; + ushort scce; + char res2[2]; + ushort sccm; + char res3; + u_char sccs; + char res4[8]; +} ccsr_cpm_scc_t; + +/* 0x91a80-0x91a9f */ +typedef struct ccsr_cpm_tmp2 { + char res[32]; +} ccsr_cpm_tmp2_t; + +/* 0x91aa0-0x91aff: SPI */ +typedef struct ccsr_cpm_spi { + ushort spmode; + char res1[4]; + u_char spie; + char res2[3]; + u_char spim; + char res3[2]; + u_char spcom; + char res4[82]; +} ccsr_cpm_spi_t; + +/* 0x91b00-0x91b1f: CPM MUX */ +typedef struct ccsr_cpm_mux { + u_char cmxsi1cr; + char res1; + u_char cmxsi2cr; + char res2; + uint cmxfcr; + uint cmxscr; + char res3[2]; + ushort cmxuar; + char res4[16]; +} ccsr_cpm_mux_t; + +/* 0x91b20-0xbffff: SI,MCC,etc */ +typedef struct ccsr_cpm_tmp3 { + char res[58592]; +} ccsr_cpm_tmp3_t; + +typedef struct ccsr_cpm_iram { + unsigned long iram[8192]; + char res[98304]; +} ccsr_cpm_iram_t; + +typedef struct ccsr_cpm { + /* Some references are into the unique and known dpram spaces, + * others are from the generic base. + */ +#define im_dprambase im_dpram1 + u_char im_dpram1[16*1024]; + char res1[16*1024]; + u_char im_dpram2[16*1024]; + char res2[16*1024]; + ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ + ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ + ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ + ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ + ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ + ccsr_cpm_fcc1_t im_cpm_fcc1; + ccsr_cpm_fcc2_t im_cpm_fcc2; + ccsr_cpm_fcc3_t im_cpm_fcc3; + ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; + ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; + ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; + ccsr_cpm_tmp1_t im_cpm_tmp1; + ccsr_cpm_brg2_t im_cpm_brg2; + ccsr_cpm_i2c_t im_cpm_i2c; + ccsr_cpm_cp_t im_cpm_cp; + ccsr_cpm_brg1_t im_cpm_brg1; + ccsr_cpm_scc_t im_cpm_scc[4]; + ccsr_cpm_tmp2_t im_cpm_tmp2; + ccsr_cpm_spi_t im_cpm_spi; + ccsr_cpm_mux_t im_cpm_mux; + ccsr_cpm_tmp3_t im_cpm_tmp3; + ccsr_cpm_iram_t im_cpm_iram; +} ccsr_cpm_t; +#endif + +/* + * RapidIO Registers(0xc_0000-0xe_0000) + */ +typedef struct ccsr_rio { + uint didcar; /* 0xc0000 - Device Identity Capability Register */ + uint dicar; /* 0xc0004 - Device Information Capability Register */ + uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ + uint aicar; /* 0xc000c - Assembly Information Capability Register */ + uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ + uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ + uint socar; /* 0xc0018 - Source Operations Capability Register */ + uint docar; /* 0xc001c - Destination Operations Capability Register */ + char res1[32]; + uint msr; /* 0xc0040 - Mailbox Command And Status Register */ + uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ + char res2[4]; + uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ + char res3[12]; + uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ + uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ + char res4[4]; + uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ + uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ + char res5[144]; + uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ + char res6[28]; + uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ + uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ + char res7[20]; + uint pgccsr; /* 0xc013c - Port General Command and Status Register */ + uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ + uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ + uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ + char res8[12]; + uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ + uint pccsr; /* 0xc015c - Port Control Command and Status Register */ + char res9[65184]; + uint cr; /* 0xd0000 - Port Control Command and Status Register */ + char res10[12]; + uint pcr; /* 0xd0010 - Port Configuration Register */ + uint peir; /* 0xd0014 - Port Error Injection Register */ + char res11[3048]; + uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ + char res12[12]; + uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + char res13[12]; + uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ + char res14[4]; + uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ + char res15[4]; + uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + char res16[12]; + uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ + char res17[4]; + uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ + char res18[4]; + uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + char res19[12]; + uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ + char res20[4]; + uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ + char res21[4]; + uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + char res22[12]; + uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ + char res23[4]; + uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ + char res24[4]; + uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + char res25[12]; + uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ + char res26[4]; + uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ + char res27[4]; + uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + char res28[12]; + uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ + char res29[4]; + uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ + char res30[4]; + uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + char res31[12]; + uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ + char res32[4]; + uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ + char res33[4]; + uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + char res34[12]; + uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ + char res35[4]; + uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ + char res36[4]; + uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + char res37[76]; + uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ + char res38[4]; + uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ + char res39[4]; + uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + char res40[12]; + uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ + char res41[4]; + uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ + char res42[4]; + uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ + char res43[12]; + uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ + char res44[4]; + uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ + char res45[4]; + uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ + char res46[12]; + uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ + char res47[4]; + uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ + char res48[4]; + uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ + char res49[12]; + uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ + char res50[12]; + uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + char res51[12]; + uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ + uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ + uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ + uint pecr; /* 0xd0e0c - Port Error Control Register */ + uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ + uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + char res52[4]; + uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + char res53[4]; + uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ + char res54[464]; + uint omr; /* 0xd1000 - Outbound Mode Register */ + uint osr; /* 0xd1004 - Outbound Status Register */ + uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ + uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */ + uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */ + uint osar; /* 0xd1014 - Outbound Unit Source Address Register */ + uint odpr; /* 0xd1018 - Outbound Destination Port Register */ + uint odatr; /* 0xd101c - Outbound Destination Attributes Register */ + uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */ + uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ + uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */ + char res55[52]; + uint imr; /* 0xd1060 - Outbound Mode Register */ + uint isr; /* 0xd1064 - Inbound Status Register */ + uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ + uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */ + uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */ + uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */ + char res56[1000]; + uint dmr; /* 0xd1460 - Doorbell Mode Register */ + uint dsr; /* 0xd1464 - Doorbell Status Register */ + uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */ + uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */ + uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */ + uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */ + char res57[104]; + uint pwmr; /* 0xd14e0 - Port-Write Mode Register */ + uint pwsr; /* 0xd14e4 - Port-Write Status Register */ + uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */ + uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */ + char res58[60176]; +} ccsr_rio_t; + +/* + * Global Utilities Register Block(0xe_0000-0xf_ffff) + */ +typedef struct ccsr_gur { + uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ + uint porbmsr; /* 0xe0004 - POR boot mode status register */ + uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ + uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ + uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ + char res1[12]; + uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ + char res2[12]; + uint gpiocr; /* 0xe0030 - GPIO control register */ + char res3[12]; + uint gpoutdr; /* 0xe0040 - General-purpose output data register */ + char res4[12]; + uint gpindr; /* 0xe0050 - General-purpose input data register */ + char res5[12]; + uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + char res6[12]; + uint devdisr; /* 0xe0070 - Device disable control */ + char res7[12]; + uint powmgtcsr; /* 0xe0080 - Power management status and control register */ + char res8[12]; + uint mcpsumr; /* 0xe0090 - Machine check summary register */ + char res9[12]; + uint pvr; /* 0xe00a0 - Processor version register */ + uint svr; /* 0xe00a4 - System version register */ + char res10[3416]; + uint clkocr; /* 0xe0e00 - Clock out select register */ + char res11[12]; + uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ + char res12[12]; + uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ + char res13[248]; + uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */ + uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */ + uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */ + uint res14; /* 0xe0f28 */ + uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ + char res15[61651]; +} ccsr_gur_t; + +typedef struct immap { + ccsr_local_ecm_t im_local_ecm; + ccsr_ddr_t im_ddr; + ccsr_i2c_t im_i2c; + ccsr_duart_t im_duart; + ccsr_lbc_t im_lbc; + ccsr_pcix_t im_pcix; + ccsr_l2cache_t im_l2cache; + ccsr_dma_t im_dma; + ccsr_tsec_t im_tsec1; + ccsr_tsec_t im_tsec2; + ccsr_pic_t im_pic; + ccsr_cpm_t im_cpm; + ccsr_rio_t im_rio; + ccsr_gur_t im_gur; +} immap_t; + +extern immap_t *immr; + +#endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h new file mode 100644 index 0000000..8e5fe11 --- /dev/null +++ b/include/asm-ppc/io.h @@ -0,0 +1,180 @@ +/* originally from linux source. + * removed the dependencies on CONFIG_ values + * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__) + * Modified By Rob Taylor, Flying Pig Systems, 2000 + */ + +#ifndef _PPC_IO_H +#define _PPC_IO_H + +#include +#include + +#define SIO_CONFIG_RA 0x398 +#define SIO_CONFIG_RD 0x399 + + +#define readb(addr) in_8((volatile u8 *)(addr)) +#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) +#if !defined(__BIG_ENDIAN) +#define readw(addr) (*(volatile u16 *) (addr)) +#define readl(addr) (*(volatile u32 *) (addr)) +#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +#else +#define readw(addr) in_le16((volatile u16 *)(addr)) +#define readl(addr) in_le32((volatile u32 *)(addr)) +#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) +#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) +#endif + +/* + * The insw/outsw/insl/outsl macros don't do byte-swapping. + * They are only used in practice for transferring buffers which + * are arrays of bytes, and byte-swapping is not appropriate in + * that case. - paulus + */ +#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) +#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + +#define inb(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) +#if !defined(__BIG_ENDIAN) +#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) +#else +#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) +#endif + +#define inb_p(port) in_8((u8 *)((port)+_IO_BASE)) +#define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) +#define inw_p(port) in_le16((u16 *)((port)+_IO_BASE)) +#define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) +#define inl_p(port) in_le32((u32 *)((port)+_IO_BASE)) +#define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) + +extern void _insb(volatile u8 *port, void *buf, int ns); +extern void _outsb(volatile u8 *port, const void *buf, int ns); +extern void _insw(volatile u16 *port, void *buf, int ns); +extern void _outsw(volatile u16 *port, const void *buf, int ns); +extern void _insl(volatile u32 *port, void *buf, int nl); +extern void _outsl(volatile u32 *port, const void *buf, int nl); +extern void _insw_ns(volatile u16 *port, void *buf, int ns); +extern void _outsw_ns(volatile u16 *port, const void *buf, int ns); +extern void _insl_ns(volatile u32 *port, void *buf, int nl); +extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); + +/* + * The *_ns versions below don't do byte-swapping. + * Neither do the standard versions now, these are just here + * for older code. + */ +#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) +#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) +#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) + + +#define IO_SPACE_LIMIT ~0 + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +/* + * Enforce In-order Execution of I/O: + * Acts as a barrier to ensure all previous I/O accesses have + * completed before any further ones are issued. + */ +#define eieio() __asm__ __volatile__ ("eieio" : : : "memory"); +#define sync() __asm__ __volatile__ ("sync" : : : "memory"); + +/* Enforce in-order execution of data I/O. + * No distinction between read/write on PPC; use eieio for all three. + */ +#define iobarrier_rw() eieio() +#define iobarrier_r() eieio() +#define iobarrier_w() eieio() + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + */ +extern inline int in_8(volatile u8 *addr) +{ + int ret; + + __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_8(volatile u8 *addr, int val) +{ + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +extern inline int in_le16(volatile u16 *addr) +{ + int ret; + + __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline int in_be16(volatile u16 *addr) +{ + int ret; + + __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le16(volatile u16 *addr, int val) +{ + __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be16(volatile u16 *addr, int val) +{ + __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +extern inline unsigned in_le32(volatile u32 *addr) +{ + unsigned ret; + + __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline unsigned in_be32(volatile u32 *addr) +{ + unsigned ret; + + __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le32(volatile unsigned *addr, int val) +{ + __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be32(volatile unsigned *addr, int val) +{ + __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +#endif diff --git a/include/asm-ppc/iopin_8260.h b/include/asm-ppc/iopin_8260.h new file mode 100644 index 0000000..21ed8c2 --- /dev/null +++ b/include/asm-ppc/iopin_8260.h @@ -0,0 +1,168 @@ +/* + * MPC8260 I/O port pin manipulation functions + */ + +#ifndef _ASM_IOPIN_8260_H_ +#define _ASM_IOPIN_8260_H_ + +#include +#include + +#ifdef __KERNEL__ + +typedef + struct { + u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ + u_char pin:5; /* port pin (0-31) */ + u_char flag:1; /* for whatever */ + } +iopin_t; + +#define IOPIN_PORTA 0 +#define IOPIN_PORTB 1 +#define IOPIN_PORTC 2 +#define IOPIN_PORTD 3 + +extern __inline__ void +iopin_set_high(iopin_t *iopin) +{ + volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void +iopin_set_low(iopin_t *iopin) +{ + volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint +iopin_is_high(iopin_t *iopin) +{ + volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint +iopin_is_low(iopin_t *iopin) +{ + volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +extern __inline__ void +iopin_set_out(iopin_t *iopin) +{ + volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void +iopin_set_in(iopin_t *iopin) +{ + volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint +iopin_is_out(iopin_t *iopin) +{ + volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint +iopin_is_in(iopin_t *iopin) +{ + volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +extern __inline__ void +iopin_set_odr(iopin_t *iopin) +{ + volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void +iopin_set_act(iopin_t *iopin) +{ + volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint +iopin_is_odr(iopin_t *iopin) +{ + volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint +iopin_is_act(iopin_t *iopin) +{ + volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +extern __inline__ void +iopin_set_ded(iopin_t *iopin) +{ + volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void +iopin_set_gen(iopin_t *iopin) +{ + volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint +iopin_is_ded(iopin_t *iopin) +{ + volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint +iopin_is_gen(iopin_t *iopin) +{ + volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +extern __inline__ void +iopin_set_opt2(iopin_t *iopin) +{ + volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); +} + +extern __inline__ void +iopin_set_opt1(iopin_t *iopin) +{ + volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); +} + +extern __inline__ uint +iopin_is_opt2(iopin_t *iopin) +{ + volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; +} + +extern __inline__ uint +iopin_is_opt1(iopin_t *iopin) +{ + volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; +} + +#endif /* __KERNEL__ */ + +#endif /* _ASM_IOPIN_8260_H_ */ diff --git a/include/asm-ppc/iopin_8xx.h b/include/asm-ppc/iopin_8xx.h new file mode 100644 index 0000000..1946eb2 --- /dev/null +++ b/include/asm-ppc/iopin_8xx.h @@ -0,0 +1,395 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8xx I/O port pin manipulation functions + * Roughly based on iopin_8260.h + */ + +#ifndef _ASM_IOPIN_8XX_H_ +#define _ASM_IOPIN_8XX_H_ + +#include +#include + +#ifdef __KERNEL__ + +typedef struct { + u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ + u_char pin:5; /* port pin (0-31) */ + u_char flag:1; /* for whatever */ +} iopin_t; + +#define IOPIN_PORTA 0 +#define IOPIN_PORTB 1 +#define IOPIN_PORTC 2 +#define IOPIN_PORTD 3 + +extern __inline__ void +iopin_set_high(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + *datp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + *datp |= (1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + *datp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + *datp |= (1 << (15 - iopin->pin)); + } +} + +extern __inline__ void +iopin_set_low(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + *datp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + *datp &= ~(1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + *datp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + *datp &= ~(1 << (15 - iopin->pin)); + } +} + +extern __inline__ uint +iopin_is_high(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + return (*datp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + return (*datp >> (31 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + return (*datp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + return (*datp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +extern __inline__ uint +iopin_is_low(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + return ((*datp >> (31 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +extern __inline__ void +iopin_set_out(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + *dirp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + *dirp |= (1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + *dirp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + *dirp |= (1 << (15 - iopin->pin)); + } +} + +extern __inline__ void +iopin_set_in(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + *dirp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + *dirp &= ~(1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + *dirp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + *dirp &= ~(1 << (15 - iopin->pin)); + } +} + +extern __inline__ uint +iopin_is_out(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + return (*dirp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + return (*dirp >> (31 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + return (*dirp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + return (*dirp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +extern __inline__ uint +iopin_is_in(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +extern __inline__ void +iopin_set_odr(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + *odrp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + *odrp |= (1 << (31 - iopin->pin)); + } +} + +extern __inline__ void +iopin_set_act(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + *odrp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + *odrp &= ~(1 << (31 - iopin->pin)); + } +} + +extern __inline__ uint +iopin_is_odr(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + return (*odrp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + return (*odrp >> (31 - iopin->pin)) & 1; + } + return 0; +} + +extern __inline__ uint +iopin_is_act(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +extern __inline__ void +iopin_set_ded(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + *parp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + *parp |= (1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + *parp |= (1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + *parp |= (1 << (15 - iopin->pin)); + } +} + +extern __inline__ void +iopin_set_gen(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + *parp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + *parp &= ~(1 << (31 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + *parp &= ~(1 << (15 - iopin->pin)); + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + *parp &= ~(1 << (15 - iopin->pin)); + } +} + +extern __inline__ uint +iopin_is_ded(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + return (*parp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + return (*parp >> (31 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + return (*parp >> (15 - iopin->pin)) & 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + return (*parp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +extern __inline__ uint +iopin_is_gen(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTA) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTB) { + volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + return ((*parp >> (31 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTC) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; + } else if (iopin->port == IOPIN_PORTD) { + volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +extern __inline__ void +iopin_set_opt2(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + *sorp |= (1 << (15 - iopin->pin)); + } +} + +extern __inline__ void +iopin_set_opt1(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + *sorp &= ~(1 << (15 - iopin->pin)); + } +} + +extern __inline__ uint +iopin_is_opt2(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + return (*sorp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +extern __inline__ uint +iopin_is_opt1(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +extern __inline__ void +iopin_set_falledge(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + *intp |= (1 << (15 - iopin->pin)); + } +} + +extern __inline__ void +iopin_set_anyedge(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + *intp &= ~(1 << (15 - iopin->pin)); + } +} + +extern __inline__ uint +iopin_is_falledge(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + return (*intp >> (15 - iopin->pin)) & 1; + } + return 0; +} + +extern __inline__ uint +iopin_is_anyedge(iopin_t *iopin) +{ + if (iopin->port == IOPIN_PORTC) { + volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + return ((*intp >> (15 - iopin->pin)) & 1) ^ 1; + } + return 0; +} + +#endif /* __KERNEL__ */ + +#endif /* _ASM_IOPIN_8XX_H_ */ diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h new file mode 100644 index 0000000..45f01de --- /dev/null +++ b/include/asm-ppc/m8260_pci.h @@ -0,0 +1,166 @@ + +#ifndef _PPC_KERNEL_M8260_PCI_H +#define _PPC_KERNEL_M8260_PCI_H + +#define M8265_PCIBR0 0x101ac +#define M8265_PCIBR1 0x101b0 +#define M8265_PCIMSK0 0x101c4 +#define M8265_PCIMSK1 0x101c8 + +/* Bit definitions for PCIBR registers */ + +#define PCIBR_ENABLE 0x00000001 + +/* Bit definitions for PCIMSK registers */ + +#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ +#define PCIMSK_64KB 0xFFFF0000 +#define PCIMSK_128KB 0xFFFE0000 +#define PCIMSK_256KB 0xFFFC0000 +#define PCIMSK_512KB 0xFFF80000 +#define PCIMSK_1MB 0xFFF00000 +#define PCIMSK_2MB 0xFFE00000 +#define PCIMSK_4MB 0xFFC00000 +#define PCIMSK_8MB 0xFF800000 +#define PCIMSK_16MB 0xFF000000 +#define PCIMSK_32MB 0xFE000000 +#define PCIMSK_64MB 0xFC000000 +#define PCIMSK_128MB 0xF8000000 +#define PCIMSK_256MB 0xF0000000 +#define PCIMSK_512MB 0xE0000000 +#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ + + +#define M826X_SCCR_PCI_MODE_EN 0x100 + + +/* + * Outbound ATU registers (3 sets). These registers control how 60x bus (local) + * addresses are translated to PCI addresses when the MPC826x is a PCI bus + * master (initiator). + */ + +#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ +#define POTAR_REG1 0x10818 +#define POTAR_REG2 0x10830 + +#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ +#define POBAR_REG1 0x10820 +#define POBAR_REG2 0x10838 + +#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ +#define POCMR_REG1 0x10828 +#define POCMR_REG2 0x10840 + +/* Bit definitions for POMCR registers */ + +#define POCMR_MASK_4KB 0x000FFFFF +#define POCMR_MASK_8KB 0x000FFFFE +#define POCMR_MASK_16KB 0x000FFFFC +#define POCMR_MASK_32KB 0x000FFFF8 +#define POCMR_MASK_64KB 0x000FFFF0 +#define POCMR_MASK_128KB 0x000FFFE0 +#define POCMR_MASK_256KB 0x000FFFC0 +#define POCMR_MASK_512KB 0x000FFF80 +#define POCMR_MASK_1MB 0x000FFF00 +#define POCMR_MASK_2MB 0x000FFE00 +#define POCMR_MASK_4MB 0x000FFC00 +#define POCMR_MASK_8MB 0x000FF800 +#define POCMR_MASK_16MB 0x000FF000 +#define POCMR_MASK_32MB 0x000FE000 +#define POCMR_MASK_64MB 0x000FC000 +#define POCMR_MASK_128MB 0x000F8000 +#define POCMR_MASK_256MB 0x000F0000 +#define POCMR_MASK_512MB 0x000E0000 +#define POCMR_MASK_1GB 0x000C0000 + +#define POCMR_ENABLE 0x80000000 +#define POCMR_PCI_IO 0x40000000 +#define POCMR_PREFETCH_EN 0x20000000 + +/* Soft PCI reset */ + +#define PCI_GCR_REG 0x10880 + +/* Bit definitions for PCI_GCR registers */ + +#define PCIGCR_PCI_BUS_EN 0x1 + +/* + * Inbound ATU registers (2 sets). These registers control how PCI addresses + * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. + */ + +#define PITAR_REG1 0x108D0 +#define PIBAR_REG1 0x108D8 +#define PICMR_REG1 0x108E0 +#define PITAR_REG0 0x108E8 +#define PIBAR_REG0 0x108F0 +#define PICMR_REG0 0x108F8 + +/* Bit definitions for PCI Inbound Comparison Mask registers */ + +#define PICMR_MASK_4KB 0x000FFFFF +#define PICMR_MASK_8KB 0x000FFFFE +#define PICMR_MASK_16KB 0x000FFFFC +#define PICMR_MASK_32KB 0x000FFFF8 +#define PICMR_MASK_64KB 0x000FFFF0 +#define PICMR_MASK_128KB 0x000FFFE0 +#define PICMR_MASK_256KB 0x000FFFC0 +#define PICMR_MASK_512KB 0x000FFF80 +#define PICMR_MASK_1MB 0x000FFF00 +#define PICMR_MASK_2MB 0x000FFE00 +#define PICMR_MASK_4MB 0x000FFC00 +#define PICMR_MASK_8MB 0x000FF800 +#define PICMR_MASK_16MB 0x000FF000 +#define PICMR_MASK_32MB 0x000FE000 +#define PICMR_MASK_64MB 0x000FC000 +#define PICMR_MASK_128MB 0x000F8000 +#define PICMR_MASK_256MB 0x000F0000 +#define PICMR_MASK_512MB 0x000E0000 +#define PICMR_MASK_1GB 0x000C0000 + +#define PICMR_ENABLE 0x80000000 +#define PICMR_NO_SNOOP_EN 0x40000000 +#define PICMR_PREFETCH_EN 0x20000000 + +/* PCI error Registers */ + +#define PCI_ERROR_STATUS_REG 0x10884 +#define PCI_ERROR_MASK_REG 0x10888 +#define PCI_ERROR_CONTROL_REG 0x1088C +#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 +#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 +#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 + +/* PCI error Register bit defines */ + +#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 +#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 +#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 +#define PCI_ERROR_PCI_NO_RSP 0x00000008 +#define PCI_ERROR_PCI_TAR_ABT 0x00000010 +#define PCI_ERROR_PCI_SERR 0x00000020 +#define PCI_ERROR_PCI_PERR_RD 0x00000040 +#define PCI_ERROR_PCI_PERR_WR 0x00000080 +#define PCI_ERROR_I2O_OFQO 0x00000100 +#define PCI_ERROR_I2O_IPQO 0x00000200 +#define PCI_ERROR_IRA 0x00000400 +#define PCI_ERROR_NMI 0x00000800 +#define PCI_ERROR_I2O_DBMC 0x00001000 + +/* + * Register pair used to generate configuration cycles on the PCI bus + * and access the MPC826x's own PCI configuration registers. + */ + +#define PCI_CFG_ADDR_REG 0x10900 +#define PCI_CFG_DATA_REG 0x10904 + +/* Bus parking decides where the bus control sits when idle */ +/* If modifying memory controllers for PCI park on the core */ + +#define PPC_ACR_BUS_PARK_CORE 0x6 +#define PPC_ACR_BUS_PARK_PCI 0x3 + +#endif /* _PPC_KERNEL_M8260_PCI_H */ diff --git a/include/asm-ppc/mc146818rtc.h b/include/asm-ppc/mc146818rtc.h new file mode 100644 index 0000000..5f806c4 --- /dev/null +++ b/include/asm-ppc/mc146818rtc.h @@ -0,0 +1,27 @@ +/* + * Machine dependent access functions for RTC registers. + */ +#ifndef __ASM_PPC_MC146818RTC_H +#define __ASM_PPC_MC146818RTC_H + +#include + +#ifndef RTC_PORT +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ +#endif + +/* + * The yet supported machines all access the RTC index register via + * an ISA port access but the way to access the date register differs ... + */ +#define CMOS_READ(addr) ({ \ +outb_p((addr),RTC_PORT(0)); \ +inb_p(RTC_PORT(1)); \ +}) +#define CMOS_WRITE(val, addr) ({ \ +outb_p((addr),RTC_PORT(0)); \ +outb_p((val),RTC_PORT(1)); \ +}) + +#endif /* __ASM_PPC_MC146818RTC_H */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h new file mode 100644 index 0000000..2606b79 --- /dev/null +++ b/include/asm-ppc/mmu.h @@ -0,0 +1,473 @@ +/* + * PowerPC memory management structures + */ + +#ifndef _PPC_MMU_H_ +#define _PPC_MMU_H_ + +#include + +#ifndef __ASSEMBLY__ +/* Hardware Page Table Entry */ +typedef struct _PTE { +#ifdef CONFIG_PPC64BRIDGE + unsigned long long vsid:52; + unsigned long api:5; + unsigned long :5; + unsigned long h:1; + unsigned long v:1; + unsigned long long rpn:52; +#else /* CONFIG_PPC64BRIDGE */ + unsigned long v:1; /* Entry is valid */ + unsigned long vsid:24; /* Virtual segment identifier */ + unsigned long h:1; /* Hash algorithm indicator */ + unsigned long api:6; /* Abbreviated page index */ + unsigned long rpn:20; /* Real (physical) page number */ +#endif /* CONFIG_PPC64BRIDGE */ + unsigned long :3; /* Unused */ + unsigned long r:1; /* Referenced */ + unsigned long c:1; /* Changed */ + unsigned long w:1; /* Write-thru cache mode */ + unsigned long i:1; /* Cache inhibited */ + unsigned long m:1; /* Memory coherence */ + unsigned long g:1; /* Guarded */ + unsigned long :1; /* Unused */ + unsigned long pp:2; /* Page protection */ +} PTE; + +/* Values for PP (assumes Ks=0, Kp=1) */ +#define PP_RWXX 0 /* Supervisor read/write, User none */ +#define PP_RWRX 1 /* Supervisor read/write, User read */ +#define PP_RWRW 2 /* Supervisor read/write, User read/write */ +#define PP_RXRX 3 /* Supervisor read, User read */ + +/* Segment Register */ +typedef struct _SEGREG { + unsigned long t:1; /* Normal or I/O type */ + unsigned long ks:1; /* Supervisor 'key' (normally 0) */ + unsigned long kp:1; /* User 'key' (normally 1) */ + unsigned long n:1; /* No-execute */ + unsigned long :4; /* Unused */ + unsigned long vsid:24; /* Virtual Segment Identifier */ +} SEGREG; + +/* Block Address Translation (BAT) Registers */ +typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ + unsigned long bepi:15; /* Effective page index (virtual address) */ + unsigned long :8; /* unused */ + unsigned long w:1; + unsigned long i:1; /* Cache inhibit */ + unsigned long m:1; /* Memory coherence */ + unsigned long ks:1; /* Supervisor key (normally 0) */ + unsigned long kp:1; /* User key (normally 1) */ + unsigned long pp:2; /* Page access protections */ +} P601_BATU; + +typedef struct _BATU { /* Upper part of BAT (all except 601) */ +#ifdef CONFIG_PPC64BRIDGE + unsigned long long bepi:47; +#else /* CONFIG_PPC64BRIDGE */ + unsigned long bepi:15; /* Effective page index (virtual address) */ +#endif /* CONFIG_PPC64BRIDGE */ + unsigned long :4; /* Unused */ + unsigned long bl:11; /* Block size mask */ + unsigned long vs:1; /* Supervisor valid */ + unsigned long vp:1; /* User valid */ +} BATU; + +typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ + unsigned long brpn:15; /* Real page index (physical address) */ + unsigned long :10; /* Unused */ + unsigned long v:1; /* Valid bit */ + unsigned long bl:6; /* Block size mask */ +} P601_BATL; + +typedef struct _BATL { /* Lower part of BAT (all except 601) */ +#ifdef CONFIG_PPC64BRIDGE + unsigned long long brpn:47; +#else /* CONFIG_PPC64BRIDGE */ + unsigned long brpn:15; /* Real page index (physical address) */ +#endif /* CONFIG_PPC64BRIDGE */ + unsigned long :10; /* Unused */ + unsigned long w:1; /* Write-thru cache */ + unsigned long i:1; /* Cache inhibit */ + unsigned long m:1; /* Memory coherence */ + unsigned long g:1; /* Guarded (MBZ in IBAT) */ + unsigned long :1; /* Unused */ + unsigned long pp:2; /* Page access protections */ +} BATL; + +typedef struct _BAT { + BATU batu; /* Upper register */ + BATL batl; /* Lower register */ +} BAT; + +typedef struct _P601_BAT { + P601_BATU batu; /* Upper register */ + P601_BATL batl; /* Lower register */ +} P601_BAT; + +/* + * Simulated two-level MMU. This structure is used by the kernel + * to keep track of MMU mappings and is used to update/maintain + * the hardware HASH table which is really a cache of mappings. + * + * The simulated structures mimic the hardware available on other + * platforms, notably the 80x86 and 680x0. + */ + +typedef struct _pte { + unsigned long page_num:20; + unsigned long flags:12; /* Page flags (some unused bits) */ +} pte; + +#define PD_SHIFT (10+12) /* Page directory */ +#define PD_MASK 0x02FF +#define PT_SHIFT (12) /* Page Table */ +#define PT_MASK 0x02FF +#define PG_SHIFT (12) /* Page Entry */ + + +/* MMU context */ + +typedef struct _MMU_context { + SEGREG segs[16]; /* Segment registers */ + pte **pmap; /* Two-level page-map structure */ +} MMU_context; + +extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ +extern void _tlbia(void); /* invalidate all TLB entries */ + +typedef enum { + IBAT0 = 0, IBAT1, IBAT2, IBAT3, + DBAT0, DBAT1, DBAT2, DBAT3 +} ppc_bat_t; + +extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); +extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); + +#endif /* __ASSEMBLY__ */ + +/* Block size masks */ +#define BL_128K 0x000 +#define BL_256K 0x001 +#define BL_512K 0x003 +#define BL_1M 0x007 +#define BL_2M 0x00F +#define BL_4M 0x01F +#define BL_8M 0x03F +#define BL_16M 0x07F +#define BL_32M 0x0FF +#define BL_64M 0x1FF +#define BL_128M 0x3FF +#define BL_256M 0x7FF + +/* BAT Access Protection */ +#define BPP_XX 0x00 /* No access */ +#define BPP_RX 0x01 /* Read only */ +#define BPP_RW 0x02 /* Read/write */ + +/* Used to set up SDR1 register */ +#define HASH_TABLE_SIZE_64K 0x00010000 +#define HASH_TABLE_SIZE_128K 0x00020000 +#define HASH_TABLE_SIZE_256K 0x00040000 +#define HASH_TABLE_SIZE_512K 0x00080000 +#define HASH_TABLE_SIZE_1M 0x00100000 +#define HASH_TABLE_SIZE_2M 0x00200000 +#define HASH_TABLE_SIZE_4M 0x00400000 +#define HASH_TABLE_MASK_64K 0x000 +#define HASH_TABLE_MASK_128K 0x001 +#define HASH_TABLE_MASK_256K 0x003 +#define HASH_TABLE_MASK_512K 0x007 +#define HASH_TABLE_MASK_1M 0x00F +#define HASH_TABLE_MASK_2M 0x01F +#define HASH_TABLE_MASK_4M 0x03F + +/* Control/status registers for the MPC8xx. + * A write operation to these registers causes serialized access. + * During software tablewalk, the registers used perform mask/shift-add + * operations when written/read. A TLB entry is created when the Mx_RPN + * is written, and the contents of several registers are used to + * create the entry. + */ +#define MI_CTR 784 /* Instruction TLB control register */ +#define MI_GPM 0x80000000 /* Set domain manager mode */ +#define MI_PPM 0x40000000 /* Set subpage protection */ +#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ +#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ +#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ +#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ +#define MI_RESETVAL 0x00000000 /* Value of register at reset */ + +/* These are the Ks and Kp from the PowerPC books. For proper operation, + * Ks = 0, Kp = 1. + */ +#define MI_AP 786 +#define MI_Ks 0x80000000 /* Should not be set */ +#define MI_Kp 0x40000000 /* Should always be set */ + +/* The effective page number register. When read, contains the information + * about the last instruction TLB miss. When MI_RPN is written, bits in + * this register are used to create the TLB entry. + */ +#define MI_EPN 787 +#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ +#define MI_EVALID 0x00000200 /* Entry is valid */ +#define MI_ASIDMASK 0x0000000f /* ASID match value */ + /* Reset value is undefined */ + +/* A "level 1" or "segment" or whatever you want to call it register. + * For the instruction TLB, it contains bits that get loaded into the + * TLB entry when the MI_RPN is written. + */ +#define MI_TWC 789 +#define MI_APG 0x000001e0 /* Access protection group (0) */ +#define MI_GUARDED 0x00000010 /* Guarded storage */ +#define MI_PSMASK 0x0000000c /* Mask of page size bits */ +#define MI_PS8MEG 0x0000000c /* 8M page size */ +#define MI_PS512K 0x00000004 /* 512K page size */ +#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ +#define MI_SVALID 0x00000001 /* Segment entry is valid */ + /* Reset value is undefined */ + +/* Real page number. Defined by the pte. Writing this register + * causes a TLB entry to be created for the instruction TLB, using + * additional information from the MI_EPN, and MI_TWC registers. + */ +#define MI_RPN 790 + +/* Define an RPN value for mapping kernel memory to large virtual + * pages for boot initialization. This has real page number of 0, + * large page size, shared page, cache enabled, and valid. + * Also mark all subpages valid and write access. + */ +#define MI_BOOTINIT 0x000001fd + +#define MD_CTR 792 /* Data TLB control register */ +#define MD_GPM 0x80000000 /* Set domain manager mode */ +#define MD_PPM 0x40000000 /* Set subpage protection */ +#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ +#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ +#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ +#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ +#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ +#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ +#define MD_RESETVAL 0x04000000 /* Value of register at reset */ + +#define M_CASID 793 /* Address space ID (context) to match */ +#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ + + +/* These are the Ks and Kp from the PowerPC books. For proper operation, + * Ks = 0, Kp = 1. + */ +#define MD_AP 794 +#define MD_Ks 0x80000000 /* Should not be set */ +#define MD_Kp 0x40000000 /* Should always be set */ + +/* The effective page number register. When read, contains the information + * about the last instruction TLB miss. When MD_RPN is written, bits in + * this register are used to create the TLB entry. + */ +#define MD_EPN 795 +#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ +#define MD_EVALID 0x00000200 /* Entry is valid */ +#define MD_ASIDMASK 0x0000000f /* ASID match value */ + /* Reset value is undefined */ + +/* The pointer to the base address of the first level page table. + * During a software tablewalk, reading this register provides the address + * of the entry associated with MD_EPN. + */ +#define M_TWB 796 +#define M_L1TB 0xfffff000 /* Level 1 table base address */ +#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ + /* Reset value is undefined */ + +/* A "level 1" or "segment" or whatever you want to call it register. + * For the data TLB, it contains bits that get loaded into the TLB entry + * when the MD_RPN is written. It is also provides the hardware assist + * for finding the PTE address during software tablewalk. + */ +#define MD_TWC 797 +#define MD_L2TB 0xfffff000 /* Level 2 table base address */ +#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ +#define MD_APG 0x000001e0 /* Access protection group (0) */ +#define MD_GUARDED 0x00000010 /* Guarded storage */ +#define MD_PSMASK 0x0000000c /* Mask of page size bits */ +#define MD_PS8MEG 0x0000000c /* 8M page size */ +#define MD_PS512K 0x00000004 /* 512K page size */ +#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ +#define MD_WT 0x00000002 /* Use writethrough page attribute */ +#define MD_SVALID 0x00000001 /* Segment entry is valid */ + /* Reset value is undefined */ + + +/* Real page number. Defined by the pte. Writing this register + * causes a TLB entry to be created for the data TLB, using + * additional information from the MD_EPN, and MD_TWC registers. + */ +#define MD_RPN 798 + +/* This is a temporary storage register that could be used to save + * a processor working register during a tablewalk. + */ +#define M_TW 799 + +/* + * At present, all PowerPC 400-class processors share a similar TLB + * architecture. The instruction and data sides share a unified, + * 64-entry, fully-associative TLB which is maintained totally under + * software control. In addition, the instruction side has a + * hardware-managed, 4-entry, fully- associative TLB which serves as a + * first level to the shared TLB. These two TLBs are known as the UTLB + * and ITLB, respectively. + */ + +#define PPC4XX_TLB_SIZE 64 + +/* + * TLB entries are defined by a "high" tag portion and a "low" data + * portion. On all architectures, the data portion is 32-bits. + * + * TLB entries are managed entirely under software control by reading, + * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx + * instructions. + */ + +#define TLB_LO 1 +#define TLB_HI 0 + +#define TLB_DATA TLB_LO +#define TLB_TAG TLB_HI + +/* Tag portion */ + +#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ +#define TLB_PAGESZ_MASK 0x00000380 +#define TLB_PAGESZ(x) (((x) & 0x7) << 7) +#define PAGESZ_1K 0 +#define PAGESZ_4K 1 +#define PAGESZ_16K 2 +#define PAGESZ_64K 3 +#define PAGESZ_256K 4 +#define PAGESZ_1M 5 +#define PAGESZ_4M 6 +#define PAGESZ_16M 7 +#define TLB_VALID 0x00000040 /* Entry is valid */ + +/* Data portion */ + +#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ +#define TLB_PERM_MASK 0x00000300 +#define TLB_EX 0x00000200 /* Instruction execution allowed */ +#define TLB_WR 0x00000100 /* Writes permitted */ +#define TLB_ZSEL_MASK 0x000000F0 +#define TLB_ZSEL(x) (((x) & 0xF) << 4) +#define TLB_ATTR_MASK 0x0000000F +#define TLB_W 0x00000008 /* Caching is write-through */ +#define TLB_I 0x00000004 /* Caching is inhibited */ +#define TLB_M 0x00000002 /* Memory is coherent */ +#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ + +/* + * e500 support + */ + +#define MAS0_TLBSEL 0x10000000 +#define MAS0_ESEL 0x000F0000 +#define MAS0_NV 0x00000001 + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID 0x00FF0000 +#define MAS1_TS 0x00001000 +#define MAS1_TSIZE 0x00000F00 + +#define MAS2_EPN 0xFFFFF000 +#define MAS2_SHAREN 0x00000200 +#define MAS2_X0 0x00000040 +#define MAS2_X1 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 + +#define MAS3_RPN 0xFFFFF000 +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 + +#define MAS4_TLBSELD 0x10000000 +#define MAS4_TIDDSEL 0x00030000 +#define MAS4_DSHAREN 0x00001000 +#define MAS4_TSIZED(x) (x << 8) +#define MAS4_X0D 0x00000040 +#define MAS4_X1D 0x00000020 +#define MAS4_WD 0x00000010 +#define MAS4_ID 0x00000008 +#define MAS4_MD 0x00000004 +#define MAS4_GD 0x00000002 +#define MAS4_ED 0x00000001 + +#define MAS6_SPID 0x00FF0000 +#define MAS6_SAS 0x00000001 + +#define BOOKE_PAGESZ_1K 0 +#define BOOKE_PAGESZ_4K 1 +#define BOOKE_PAGESZ_16K 2 +#define BOOKE_PAGESZ_64K 3 +#define BOOKE_PAGESZ_256K 4 +#define BOOKE_PAGESZ_1M 5 +#define BOOKE_PAGESZ_4M 6 +#define BOOKE_PAGESZ_16M 7 +#define BOOKE_PAGESZ_64M 8 +#define BOOKE_PAGESZ_256M 9 +#define BOOKE_PAGESZ_1GB 10 +#define BOOKE_PAGESZ_4GB 11 + +#define LAWBAR_BASE_ADDR 0x000FFFFF +#define LAWAR_EN 0x80000000 +#define LAWAR_TRGT_IF 0x00F00000 +#define LAWAR_SIZE 0x0000003F + +#define LAWAR_TRGT_IF_PCI 0x00000000 +#define LAWAR_TRGT_IF_PCI1 0x00000000 +#define LAWAR_TRGT_IF_PCIX 0x00000000 +#define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_LBC 0x00400000 +#define LAWAR_TRGT_IF_CCSR 0x00800000 +#define LAWAR_TRGT_IF_RIO 0x00c00000 +#define LAWAR_TRGT_IF_DDR 0x00f00000 + +#define LAWAR_SIZE_BASE 0xa +#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) +#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2) +#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3) +#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4) +#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5) +#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6) +#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7) +#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8) +#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9) +#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10) +#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11) +#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12) +#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13) +#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14) +#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15) +#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16) +#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17) +#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) +#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) +#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) + +#endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/mpc8349_pci.h b/include/asm-ppc/mpc8349_pci.h new file mode 100644 index 0000000..48255a3 --- /dev/null +++ b/include/asm-ppc/mpc8349_pci.h @@ -0,0 +1,167 @@ +#ifndef _PPC_KERNEL_MPC8349_PCI_H +#define _PPC_KERNEL_MPC8349_PCI_H + + +#define M8265_PCIBR0 0x101ac +#define M8265_PCIBR1 0x101b0 +#define M8265_PCIMSK0 0x101c4 +#define M8265_PCIMSK1 0x101c8 + +/* Bit definitions for PCIBR registers */ + +#define PCIBR_ENABLE 0x00000001 + +/* Bit definitions for PCIMSK registers */ + +#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ +#define PCIMSK_64KB 0xFFFF0000 +#define PCIMSK_128KB 0xFFFE0000 +#define PCIMSK_256KB 0xFFFC0000 +#define PCIMSK_512KB 0xFFF80000 +#define PCIMSK_1MB 0xFFF00000 +#define PCIMSK_2MB 0xFFE00000 +#define PCIMSK_4MB 0xFFC00000 +#define PCIMSK_8MB 0xFF800000 +#define PCIMSK_16MB 0xFF000000 +#define PCIMSK_32MB 0xFE000000 +#define PCIMSK_64MB 0xFC000000 +#define PCIMSK_128MB 0xF8000000 +#define PCIMSK_256MB 0xF0000000 +#define PCIMSK_512MB 0xE0000000 +#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ + + +#define M826X_SCCR_PCI_MODE_EN 0x100 + + +/* + * Outbound ATU registers (3 sets). These registers control how 60x bus + * (local) addresses are translated to PCI addresses when the MPC826x is + * a PCI bus master (initiator). + */ + +#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ +#define POTAR_REG1 0x10818 +#define POTAR_REG2 0x10830 + +#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ +#define POBAR_REG1 0x10820 +#define POBAR_REG2 0x10838 + +#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ +#define POCMR_REG1 0x10828 +#define POCMR_REG2 0x10840 + +/* Bit definitions for POMCR registers */ + +#define POCMR_MASK_4KB 0x000FFFFF +#define POCMR_MASK_8KB 0x000FFFFE +#define POCMR_MASK_16KB 0x000FFFFC +#define POCMR_MASK_32KB 0x000FFFF8 +#define POCMR_MASK_64KB 0x000FFFF0 +#define POCMR_MASK_128KB 0x000FFFE0 +#define POCMR_MASK_256KB 0x000FFFC0 +#define POCMR_MASK_512KB 0x000FFF80 +#define POCMR_MASK_1MB 0x000FFF00 +#define POCMR_MASK_2MB 0x000FFE00 +#define POCMR_MASK_4MB 0x000FFC00 +#define POCMR_MASK_8MB 0x000FF800 +#define POCMR_MASK_16MB 0x000FF000 +#define POCMR_MASK_32MB 0x000FE000 +#define POCMR_MASK_64MB 0x000FC000 +#define POCMR_MASK_128MB 0x000F8000 +#define POCMR_MASK_256MB 0x000F0000 +#define POCMR_MASK_512MB 0x000E0000 +#define POCMR_MASK_1GB 0x000C0000 + +#define POCMR_ENABLE 0x80000000 +#define POCMR_PCI_IO 0x40000000 +#define POCMR_PREFETCH_EN 0x20000000 + +/* Soft PCI reset */ + +#define PCI_GCR_REG 0x10880 + +/* Bit definitions for PCI_GCR registers */ + +#define PCIGCR_PCI_BUS_EN 0x1 + +/* + * Inbound ATU registers (2 sets). These registers control how PCI + * addresses are translated to 60x bus (local) addresses when the + * MPC826x is a PCI bus target. + */ + +#define PITAR_REG1 0x108D0 +#define PIBAR_REG1 0x108D8 +#define PICMR_REG1 0x108E0 +#define PITAR_REG0 0x108E8 +#define PIBAR_REG0 0x108F0 +#define PICMR_REG0 0x108F8 + +/* Bit definitions for PCI Inbound Comparison Mask registers */ + +#define PICMR_MASK_4KB 0x000FFFFF +#define PICMR_MASK_8KB 0x000FFFFE +#define PICMR_MASK_16KB 0x000FFFFC +#define PICMR_MASK_32KB 0x000FFFF8 +#define PICMR_MASK_64KB 0x000FFFF0 +#define PICMR_MASK_128KB 0x000FFFE0 +#define PICMR_MASK_256KB 0x000FFFC0 +#define PICMR_MASK_512KB 0x000FFF80 +#define PICMR_MASK_1MB 0x000FFF00 +#define PICMR_MASK_2MB 0x000FFE00 +#define PICMR_MASK_4MB 0x000FFC00 +#define PICMR_MASK_8MB 0x000FF800 +#define PICMR_MASK_16MB 0x000FF000 +#define PICMR_MASK_32MB 0x000FE000 +#define PICMR_MASK_64MB 0x000FC000 +#define PICMR_MASK_128MB 0x000F8000 +#define PICMR_MASK_256MB 0x000F0000 +#define PICMR_MASK_512MB 0x000E0000 +#define PICMR_MASK_1GB 0x000C0000 + +#define PICMR_ENABLE 0x80000000 +#define PICMR_NO_SNOOP_EN 0x40000000 +#define PICMR_PREFETCH_EN 0x20000000 + +/* PCI error Registers */ + +#define PCI_ERROR_STATUS_REG 0x10884 +#define PCI_ERROR_MASK_REG 0x10888 +#define PCI_ERROR_CONTROL_REG 0x1088C +#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 +#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 +#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 + +/* PCI error Register bit defines */ + +#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 +#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 +#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 +#define PCI_ERROR_PCI_NO_RSP 0x00000008 +#define PCI_ERROR_PCI_TAR_ABT 0x00000010 +#define PCI_ERROR_PCI_SERR 0x00000020 +#define PCI_ERROR_PCI_PERR_RD 0x00000040 +#define PCI_ERROR_PCI_PERR_WR 0x00000080 +#define PCI_ERROR_I2O_OFQO 0x00000100 +#define PCI_ERROR_I2O_IPQO 0x00000200 +#define PCI_ERROR_IRA 0x00000400 +#define PCI_ERROR_NMI 0x00000800 +#define PCI_ERROR_I2O_DBMC 0x00001000 + +/* + * Register pair used to generate configuration cycles on the PCI bus + * and access the MPC826x's own PCI configuration registers. + */ + +#define PCI_CFG_ADDR_REG 0x10900 +#define PCI_CFG_DATA_REG 0x10904 + +/* Bus parking decides where the bus control sits when idle */ +/* If modifying memory controllers for PCI park on the core */ + +#define PPC_ACR_BUS_PARK_CORE 0x6 +#define PPC_ACR_BUS_PARK_PCI 0x3 + +#endif /* _PPC_KERNEL_M8260_PCI_H */ diff --git a/include/asm-ppc/pci_io.h b/include/asm-ppc/pci_io.h new file mode 100644 index 0000000..9b738c3 --- /dev/null +++ b/include/asm-ppc/pci_io.h @@ -0,0 +1,43 @@ +/* originally from linux source (asm-ppc/io.h). + * Sanity added by Rob Taylor, Flying Pig Systems, 2000 + */ +#ifndef _PCI_IO_H_ +#define _PCI_IO_H_ + +#include "io.h" + + +#define pci_read_le16(addr, dest) \ + __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \ + "r" (addr), "m" (*addr)); + +#define pci_write_le16(addr, val) \ + __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \ + "r" (val), "r" (addr)); + + +#define pci_read_le32(addr, dest) \ + __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \ + "r" (addr), "m" (*addr)); + +#define pci_write_le32(addr, val) \ +__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \ + "r" (val), "r" (addr)); + +#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr)) +#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) + +#if !defined(__BIG_ENDIAN) +#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr)) +#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr)) +#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) +#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +#else +#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b)) +#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b)) +#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b)) +#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b)) +#endif + + +#endif /* _PCI_IO_H_ */ diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h new file mode 100644 index 0000000..22ceba2 --- /dev/null +++ b/include/asm-ppc/pnp.h @@ -0,0 +1,643 @@ +/* 11/02/95 */ +/*----------------------------------------------------------------------------*/ +/* Plug and Play header definitions */ +/*----------------------------------------------------------------------------*/ + +/* Structure map for PnP on PowerPC Reference Platform */ +/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ +/* (or later versions) is available on Compuserve in the PLUGPLAY area. */ +/* This code has extensions to that specification, namely new short and */ +/* long tag types for platform dependent information */ + +/* Warning: LE notation used throughout this file */ + +/* For enum's: if given in hex then they are bit significant, i.e. */ +/* only one bit is on for each enum */ + +#ifndef _PNP_ +#define _PNP_ + +#ifndef __ASSEMBLY__ +#define MAX_MEM_REGISTERS 9 +#define MAX_IO_PORTS 20 +#define MAX_IRQS 7 +/*#define MAX_DMA_CHANNELS 7*/ + +/* Interrupt controllers */ + +#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ +#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ +#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ +#define PNPinterrupt3 "PNP0003" /* APIC */ +#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ + +/* Timers */ + +#define PNPtimer0 "PNP0100" /* AT Timer */ +#define PNPtimer1 "PNP0101" /* EISA Timer */ +#define PNPtimer2 "PNP0102" /* MCA Timer */ + +/* DMA controllers */ + +#define PNPdma0 "PNP0200" /* AT DMA Controller */ +#define PNPdma1 "PNP0201" /* EISA DMA Controller */ +#define PNPdma2 "PNP0202" /* MCA DMA Controller */ + +/* start of August 15, 1994 additions */ +/* CMOS */ +#define PNPCMOS "IBM0009" /* CMOS */ + +/* L2 Cache */ +#define PNPL2 "IBM0007" /* L2 Cache */ + +/* NVRAM */ +#define PNPNVRAM "IBM0008" /* NVRAM */ + +/* Power Management */ +#define PNPPM "IBM0005" /* Power Management */ +/* end of August 15, 1994 additions */ + +/* Keyboards */ + +#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ +#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ +#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ +#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ +#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ +#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ +#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ +#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ + +/* Parallel port controllers */ + +#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ +#define PNPparallel1 "PNP0401" /* ECP Parallel Port */ +#define PNPepp "IBM001C" /* EPP Parallel Port */ + +/* Serial port controllers */ + +#define PNPserial0 "PNP0500" /* Standard PC Serial port */ +#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ + +/* Disk controllers */ + +#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ +#define PNPdisk1 "PNP0601" /* Plus Hardcard II */ +#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ + +/* Diskette controllers */ + +#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ + +/* Display controllers */ + +#define PNPdisplay0 "PNP0900" /* VGA Compatible */ +#define PNPdisplay1 "PNP0901" /* Video Seven VGA */ +#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ +#define PNPdisplay3 "PNP0903" /* Trident VGA */ +#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ +#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ +#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ +#define PNPdisplay7 "PNP0907" /* Western Digital VGA */ +#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ +#define PNPdisplay9 "PNP0909" /* S3 */ +#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ +#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ +#define PNPdisplayC "PNP090C" /* XGA Compatible */ +#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ +#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ +#define PNPdisplayF "PNP090F" /* Oak Technology VGA */ + +/* Peripheral busses */ + +#define PNPbuses0 "PNP0A00" /* ISA Bus */ +#define PNPbuses1 "PNP0A01" /* EISA Bus */ +#define PNPbuses2 "PNP0A02" /* MCA Bus */ +#define PNPbuses3 "PNP0A03" /* PCI Bus */ +#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ + +/* RTC, BIOS, planar devices */ + +#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ +#define PNPrtc0 "PNP0B00" /* AT RTC */ +#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ +#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ +#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ +#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ + +/* PCMCIA controller */ + +#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ + +/* Mice */ + +#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ +#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ +#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ +#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ +#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ +#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ +#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ +#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ +#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ +#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ +#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ +#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ + +/* Modems */ + +#define PNPmodem0 "PNP9000" /* Specific IDs TBD */ + +/* Network controllers */ + +#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ +#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ +#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ +#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ +#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ +#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ +#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ +#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ + +/* SCSI controllers */ + +#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ +#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ +#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ +#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ +#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ +#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ +#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ + +/* Sound/Video, Multimedia */ + +#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ +#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ +#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ +#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ +#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ +#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ +#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ +#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ + +/* Operator Panel */ +#define PNPopctl "IBM000B" /* Operator's panel */ + +/* Service Processor */ +#define PNPsp "IBM0011" /* IBM Service Processor */ +#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ +#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ + +/* Memory Controller */ +#define PNPmemctl "IBM000A" /* Memory controller */ + +/* Graphics Assist */ +#define PNPg_assist "IBM0014" /* Graphics Assist */ + +/* Miscellaneous Device Controllers */ +#define PNPtablet "IBM0019" /* IBM Tablet Controller */ + +/* PNP Packet Handles */ + +#define S1_Packet 0x0A /* Version resource */ +#define S2_Packet 0x15 /* Logical DEVID (without flags) */ +#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ +#define S3_Packet 0x1C /* Compatible device ID */ +#define S4_Packet 0x22 /* IRQ resource (without flags) */ +#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ +#define S5_Packet 0x2A /* DMA resource */ +#define S6_Packet 0x30 /* Depend funct start (w/o priority) */ +#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ +#define S7_Packet 0x38 /* Depend funct end */ +#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ +#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ +#define S14_Packet 0x71 /* Vendor defined */ +#define S15_Packet 0x78 /* End of resource (w/o checksum) */ +#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ +#define L1_Packet 0x81 /* Memory range */ +#define L1_Shadow 0x20 /* Memory is shadowable */ +#define L1_32bit_mem 0x18 /* 32-bit memory only */ +#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ +#define L1_Decode_Hi 0x04 /* decode supports high address */ +#define L1_Cache 0x02 /* read cacheable, write-through */ +#define L1_Writeable 0x01 /* Memory is writeable */ +#define L2_Packet 0x82 /* ANSI ID string */ +#define L3_Packet 0x83 /* Unicode ID string */ +#define L4_Packet 0x84 /* Vendor defined */ +#define L5_Packet 0x85 /* Large I/O */ +#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ +#define END_TAG 0x78 /* End of resource */ +#define DF_START_TAG 0x30 /* Dependent function start */ +#define DF_START_TAG_priority 0x31 /* Dependent function start */ +#define DF_END_TAG 0x38 /* Dependent function end */ +#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ + +/* Device Base Type Codes */ + +typedef enum _PnP_BASE_TYPE { + Reserved = 0, + MassStorageDevice = 1, + NetworkInterfaceController = 2, + DisplayController = 3, + MultimediaController = 4, + MemoryController = 5, + BridgeController = 6, + CommunicationsDevice = 7, + SystemPeripheral = 8, + InputDevice = 9, + ServiceProcessor = 0x0A, /* 11/2/95 */ + } PnP_BASE_TYPE; + +/* Device Sub Type Codes */ + +typedef enum _PnP_SUB_TYPE { + SCSIController = 0, + IDEController = 1, + FloppyController = 2, + IPIController = 3, + OtherMassStorageController = 0x80, + + EthernetController = 0, + TokenRingController = 1, + FDDIController = 2, + OtherNetworkController = 0x80, + + VGAController= 0, + SVGAController= 1, + XGAController= 2, + OtherDisplayController = 0x80, + + VideoController = 0, + AudioController = 1, + OtherMultimediaController = 0x80, + + RAM = 0, + FLASH = 1, + OtherMemoryDevice = 0x80, + + HostProcessorBridge = 0, + ISABridge = 1, + EISABridge = 2, + MicroChannelBridge = 3, + PCIBridge = 4, + PCMCIABridge = 5, + VMEBridge = 6, + OtherBridgeDevice = 0x80, + + RS232Device = 0, + ATCompatibleParallelPort = 1, + OtherCommunicationsDevice = 0x80, + + ProgrammableInterruptController = 0, + DMAController = 1, + SystemTimer = 2, + RealTimeClock = 3, + L2Cache = 4, + NVRAM = 5, + PowerManagement = 6, + CMOS = 7, + OperatorPanel = 8, + ServiceProcessorClass1 = 9, + ServiceProcessorClass2 = 0xA, + ServiceProcessorClass3 = 0xB, + GraphicAssist = 0xC, + SystemPlanar = 0xF, /* 10/5/95 */ + OtherSystemPeripheral = 0x80, + + KeyboardController = 0, + Digitizer = 1, + MouseController = 2, + TabletController = 3, /* 10/27/95 */ + OtherInputController = 0x80, + + GeneralMemoryController = 0, + } PnP_SUB_TYPE; + +/* Device Interface Type Codes */ + +typedef enum _PnP_INTERFACE { + General = 0, + GeneralSCSI = 0, + GeneralIDE = 0, + ATACompatible = 1, + + GeneralFloppy = 0, + Compatible765 = 1, + NS398_Floppy = 2, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26E_Floppy = 3, /* Ports 26E and 26F */ + NS15C_Floppy = 4, /* Ports 15C and 15D */ + NS2E_Floppy = 5, /* Ports 2E and 2F */ + CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ + + GeneralIPI = 0, + + GeneralEther = 0, + GeneralToken = 0, + GeneralFDDI = 0, + + GeneralVGA = 0, + GeneralSVGA = 0, + GeneralXGA = 0, + + GeneralVideo = 0, + GeneralAudio = 0, + CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ + + GeneralRAM = 0, + GeneralFLASH = 0, + PCIMemoryController = 0, /* PCI Config Method */ + RS6KMemoryController = 1, /* RS6K Config Method */ + + GeneralHostBridge = 0, + GeneralISABridge = 0, + GeneralEISABridge = 0, + GeneralMCABridge = 0, + GeneralPCIBridge = 0, + PCIBridgeDirect = 0, + PCIBridgeIndirect = 1, + PCIBridgeRS6K = 2, + GeneralPCMCIABridge = 0, + GeneralVMEBridge = 0, + + GeneralRS232 = 0, + COMx = 1, + Compatible16450 = 2, + Compatible16550 = 3, + NS398SerPort = 4, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26ESerPort = 5, /* Ports 26E and 26F */ + NS15CSerPort = 6, /* Ports 15C and 15D */ + NS2ESerPort = 7, /* Ports 2E and 2F */ + + GeneralParPort = 0, + LPTx = 1, + NS398ParPort = 2, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26EParPort = 3, /* Ports 26E and 26F */ + NS15CParPort = 4, /* Ports 15C and 15D */ + NS2EParPort = 5, /* Ports 2E and 2F */ + + GeneralPIC = 0, + ISA_PIC = 1, + EISA_PIC = 2, + MPIC = 3, + RS6K_PIC = 4, + + GeneralDMA = 0, + ISA_DMA = 1, + EISA_DMA = 2, + + GeneralTimer = 0, + ISA_Timer = 1, + EISA_Timer = 2, + GeneralRTC = 0, + ISA_RTC = 1, + + StoreThruOnly = 1, + StoreInEnabled = 2, + RS6KL2Cache = 3, + + IndirectNVRAM = 0, /* Indirectly addressed */ + DirectNVRAM = 1, /* Memory Mapped */ + IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ + + GeneralPowerManagement = 0, + EPOWPowerManagement = 1, + PowerControl = 2, /* d1378 */ + + GeneralCMOS = 0, + + GeneralOPPanel = 0, + HarddiskLight = 1, + CDROMLight = 2, + PowerLight = 3, + KeyLock = 4, + ANDisplay = 5, /* AlphaNumeric Display */ + SystemStatusLED = 6, /* 3 digit 7 segment LED */ + CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ + + GeneralServiceProcessor = 0, + + TransferData = 1, + IGMC32 = 2, + IGMC64 = 3, + + GeneralSystemPlanar = 0, /* 10/5/95 */ + + } PnP_INTERFACE; + +/* PnP resources */ + +/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ + +typedef struct _SERIAL_ID { + unsigned char VendorID0; /* Bit(7)=0 */ + /* Bits(6:2)=1st character in */ + /* compressed ASCII */ + /* Bits(1:0)=2nd character in */ + /* compressed ASCII bits(4:3) */ + unsigned char VendorID1; /* Bits(7:5)=2nd character in */ + /* compressed ASCII bits(2:0) */ + /* Bits(4:0)=3rd character in */ + /* compressed ASCII */ + unsigned char VendorID2; /* Product number - vendor assigned */ + unsigned char VendorID3; /* Product number - vendor assigned */ + +/* Serial number is to provide uniqueness if more than one board of same */ +/* type is in system. Must be "FFFFFFFF" if feature not supported. */ + + unsigned char Serial0; /* Unique serial number bits (7:0) */ + unsigned char Serial1; /* Unique serial number bits (15:8) */ + unsigned char Serial2; /* Unique serial number bits (23:16) */ + unsigned char Serial3; /* Unique serial number bits (31:24) */ + unsigned char Checksum; + } SERIAL_ID; + +typedef enum _PnPItemName { + Unused = 0, + PnPVersion = 1, + LogicalDevice = 2, + CompatibleDevice = 3, + IRQFormat = 4, + DMAFormat = 5, + StartDepFunc = 6, + EndDepFunc = 7, + IOPort = 8, + FixedIOPort = 9, + Res1 = 10, + Res2 = 11, + Res3 = 12, + SmallVendorItem = 14, + EndTag = 15, + MemoryRange = 1, + ANSIIdentifier = 2, + UnicodeIdentifier = 3, + LargeVendorItem = 4, + MemoryRange32 = 5, + MemoryRangeFixed32 = 6, + } PnPItemName; + +/* Define a bunch of access functions for the bits in the tag field */ + +/* Tag type - 0 = small; 1 = large */ +#define tag_type(t) (((t) & 0x80)>>7) +#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) + +/* Small item name is 4 bits - one of PnPItemName enum above */ +#define tag_small_item_name(t) (((t) & 0x78)>>3) +#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) + +/* Small item count is 3 bits - count of further bytes in packet */ +#define tag_small_count(t) ((t) & 0x07) +#define set_tag_count(t,v) (t = (t & 0x78) | (v)) + +/* Large item name is 7 bits - one of PnPItemName enum above */ +#define tag_large_item_name(t) ((t) & 0x7f) +#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) + +/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ + +typedef union _PnP_TAG_PACKET { + struct _S1_Pack{ /* VERSION PACKET */ + unsigned char Tag; /* small tag = 0x0a */ + unsigned char Version[2]; /* PnP version, Vendor version */ + } S1_Pack; + + struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ + unsigned char Tag; /* small tag = 0x15 or 0x16 */ + unsigned char DevId[4]; /* Logical device id */ + unsigned char Flags[2]; /* bit(0) boot device; */ + /* bit(7:1) cmd in range x31-x37 */ + /* bit(7:0) cmd in range x28-x3f (opt)*/ + } S2_Pack; + + struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ + unsigned char Tag; /* small tag = 0x1c */ + unsigned char CompatId[4]; /* Compatible device id */ + } S3_Pack; + + struct _S4_Pack{ /* IRQ PACKET */ + unsigned char Tag; /* small tag = 0x22 or 0x23 */ + unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ + /* bit(0) is IRQ8 ... */ + unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ + /* bit(0) - high true edge sensitive */ + /* bit(1) - low true edge sensitive */ + /* bit(2) - high true level sensitive*/ + /* bit(3) - low true level sensitive */ + /* bit(7:4) - must be 0 */ + } S4_Pack; + + struct _S5_Pack{ /* DMA PACKET */ + unsigned char Tag; /* small tag = 0x2a */ + unsigned char DMAMask; /* bit(0) is channel 0 ... */ + unsigned char DMAInfo; + } S5_Pack; + + struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ + unsigned char Tag; /* small tag = 0x30 or 0x31 */ + unsigned char Priority; /* Optional; if missing then x01; else*/ + /* x00 = best possible */ + /* x01 = acceptible */ + /* x02 = sub-optimal but functional */ + } S6_Pack; + + struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ + unsigned char Tag; /* small tag = 0x38 */ + } S7_Pack; + + struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ + unsigned char Tag; /* small tag x47 */ + unsigned char IOInfo; /* x0 = decode only bits(9:0); */ +#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ + unsigned char RangeMin[2]; /* Min base address */ + unsigned char RangeMax[2]; /* Max base address */ + unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ + unsigned char IONum; /* number of contiguous I/O ports */ + } S8_Pack; + + struct _S9_Pack{ /* FIXED I/O PORT PACKET */ + unsigned char Tag; /* small tag = 0x4b */ + unsigned char Range[2]; /* base address 10 bits */ + unsigned char IONum; /* number of contiguous I/O ports */ + } S9_Pack; + + struct _S14_Pack{ /* VENDOR DEFINED PACKET */ + unsigned char Tag; /* small tag = 0x7m m = 1-7 */ + union _S14_Data{ + unsigned char Data[7]; /* Vendor defined */ + struct _S14_PPCPack{ /* Pr*p s14 pack */ + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[6]; /* Vendor defined */ + } S14_PPCPack; + } S14_Data; + } S14_Pack; + + struct _S15_Pack{ /* END PACKET */ + unsigned char Tag; /* small tag = 0x78 or 0x79 */ + unsigned char Check; /* optional - checksum */ + } S15_Pack; + + struct _L1_Pack{ /* MEMORY RANGE PACKET */ + unsigned char Tag; /* large tag = 0x81 */ + unsigned char Count0; /* x09 */ + unsigned char Count1; /* x00 */ + unsigned char Data[9]; /* a variable array of bytes, */ + /* count in tag */ + } L1_Pack; + + struct _L2_Pack{ /* ANSI ID STRING PACKET */ + unsigned char Tag; /* large tag = 0x82 */ + unsigned char Count0; /* Length of string */ + unsigned char Count1; + unsigned char Identifier[1]; /* a variable array of bytes, */ + /* count in tag */ + } L2_Pack; + + struct _L3_Pack{ /* UNICODE ID STRING PACKET */ + unsigned char Tag; /* large tag = 0x83 */ + unsigned char Count0; /* Length + 2 of string */ + unsigned char Count1; + unsigned char Country0; /* TBD */ + unsigned char Country1; /* TBD */ + unsigned char Identifier[1]; /* a variable array of bytes, */ + /* count in tag */ + } L3_Pack; + + struct _L4_Pack{ /* VENDOR DEFINED PACKET */ + unsigned char Tag; /* large tag = 0x84 */ + unsigned char Count0; + unsigned char Count1; + union _L4_Data{ + unsigned char Data[1]; /* a variable array of bytes, */ + /* count in tag */ + struct _L4_PPCPack{ /* Pr*p L4 packet */ + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[1]; /* a variable array of bytes, */ + /* count in tag */ + } L4_PPCPack; + } L4_Data; + } L4_Pack; + + struct _L5_Pack{ + unsigned char Tag; /* large tag = 0x85 */ + unsigned char Count0; /* Count = 17 */ + unsigned char Count1; + unsigned char Data[17]; + } L5_Pack; + + struct _L6_Pack{ + unsigned char Tag; /* large tag = 0x86 */ + unsigned char Count0; /* Count = 9 */ + unsigned char Count1; + unsigned char Data[9]; + } L6_Pack; + + } PnP_TAG_PACKET; + +#endif /* __ASSEMBLY__ */ +#endif /* ndef _PNP_ */ diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h new file mode 100644 index 0000000..9170728 --- /dev/null +++ b/include/asm-ppc/posix_types.h @@ -0,0 +1,109 @@ +#ifndef _PPC_POSIX_TYPES_H +#define _PPC_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned int __kernel_dev_t; +typedef unsigned int __kernel_ino_t; +typedef unsigned int __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned int __kernel_old_uid_t; +typedef unsigned int __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { + int val[2]; +} __kernel_fsid_t; + +#ifndef __GNUC__ + +#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) +#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) +#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) +#define __FD_ZERO(set) \ + ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set))) + +#else /* __GNUC__ */ + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ + || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) +/* With GNU C, use inline functions instead so args are evaluated only once: */ + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) +{ + unsigned long _tmp = fd / __NFDBITS; + unsigned long _rem = fd % __NFDBITS; + fdsetp->fds_bits[_tmp] |= (1UL<<_rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp) +{ + unsigned long _tmp = fd / __NFDBITS; + unsigned long _rem = fd % __NFDBITS; + fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem); +} + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p) +{ + unsigned long _tmp = fd / __NFDBITS; + unsigned long _rem = fd % __NFDBITS; + return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *p) +{ + unsigned int *tmp = (unsigned int *)p->fds_bits; + int i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 8: + tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0; + tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0; + return; + } + } + i = __FDSET_LONGS; + while (i) { + i--; + *tmp = 0; + tmp++; + } +} + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* __GNUC__ */ +#endif /* _PPC_POSIX_TYPES_H */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h new file mode 100644 index 0000000..8113783 --- /dev/null +++ b/include/asm-ppc/processor.h @@ -0,0 +1,1064 @@ +#ifndef __ASM_PPC_PROCESSOR_H +#define __ASM_PPC_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include + +#include +#include + +/* Machine State Register (MSR) Fields */ + +#ifdef CONFIG_PPC64BRIDGE +#define MSR_SF (1<<63) +#define MSR_ISF (1<<61) +#endif /* CONFIG_PPC64BRIDGE */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ +#define MSR_SPE (1<<25) /* Enable SPE(e500) */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait State Enable */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_ILE (1<<16) /* Interrupt Little Endian */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_PR (1<<14) /* Problem State / Privilege Level */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ +#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IS (1<<5) /* Book E Instruction space */ +#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DS (1<<4) /* Book E Data space */ +#define MSR_PE (1<<3) /* Protection Enable */ +#define MSR_PX (1<<2) /* Protection Exclusive Mode */ +#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little Endian */ + +#ifdef CONFIG_APUS_FAST_EXCEPT +#define MSR_ MSR_ME|MSR_IP|MSR_RI +#else +#define MSR_ MSR_ME|MSR_RI +#endif +#ifndef CONFIG_E500 +#define MSR_KERNEL MSR_|MSR_IR|MSR_DR +#else +#define MSR_KERNEL MSR_ME +#endif +#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE + +/* Floating Point Status and Control Register (FPSCR) Fields */ + +#define FPSCR_FX 0x80000000 /* FPU exception summary */ +#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ +#define FPSCR_VX 0x20000000 /* Invalid operation summary */ +#define FPSCR_OX 0x10000000 /* Overflow exception summary */ +#define FPSCR_UX 0x08000000 /* Underflow exception summary */ +#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ +#define FPSCR_XX 0x02000000 /* Inexact exception summary */ +#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ +#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ +#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ +#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ +#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ +#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ +#define FPSCR_FR 0x00040000 /* Fraction rounded */ +#define FPSCR_FI 0x00020000 /* Fraction inexact */ +#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ +#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ +#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ +#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ +#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ +#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ +#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ +#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ +#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ +#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ +#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ +#define FPSCR_RN 0x00000003 /* FPU rounding control */ + +/* Special Purpose Registers (SPRNs)*/ + +#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ +#define SPRN_CTR 0x009 /* Count Register */ +#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#ifndef CONFIG_BOOKE +#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ +#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#else +#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DAR 0x013 /* Data Address Register */ +#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ +#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ +#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ +#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ +#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ +#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ +#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ +#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ +#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define DBCR_EDM 0x80000000 +#define DBCR_IDM 0x40000000 +#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 +#define DBCR_RST_SYSTEM 3 +#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ +#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ +#define DBCR_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DAC_BYTE 0 +#define DAC_HALF 1 +#define DAC_WORD 2 +#define DAC_QUAD 3 +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#else +#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ +#endif /* CONFIG_BOOKE */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#else +#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ +#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ +#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ +#define DCCR_NOCACHE 0 /* Noncacheable */ +#define DCCR_CACHE 1 /* Cacheable */ +#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ +#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ +#define DCWR_COPY 0 /* Copy-back */ +#define DCWR_WRITE 1 /* Write-through */ +#ifndef CONFIG_BOOKE +#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#else +#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DEC 0x016 /* Decrement Register */ +#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#define SPRN_EAR 0x11A /* External Address Register */ +#ifndef CONFIG_BOOKE +#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#else +#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ +#endif /* CONFIG_BOOKE */ +#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ +#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ +#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ +#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ +#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ +#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ +#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ +#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ +#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ +#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ + +#define HID0_ICE_SHIFT 15 +#define HID0_DCE_SHIFT 14 +#define HID0_DLOCK_SHIFT 12 + +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ + +#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ +#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ +#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ +#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ +#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ +#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ +#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ + +/* System-On-Chip Version Numbers (version field only) */ +#define SVR_MPC5200 0x8011 + +/* Processor Version Register */ + +/* Processor Version Register (PVR) field extraction */ + +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ + +/* + * AMCC has further subdivided the standard PowerPC 16-bit version and + * revision subfields of the PVR for the PowerPC 403s into the following: + */ + +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ + +/* Processor Version Numbers */ + +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_405GP_RB 0x40110040 +#define PVR_405GP_RC 0x40110082 +#define PVR_405GP_RD 0x401100C4 +#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ +#define PVR_405CR_RA 0x40110041 +#define PVR_405CR_RB 0x401100C5 +#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ +#define PVR_405EP_RA 0x51210950 +#define PVR_405GPR_RB 0x50910951 +#define PVR_440GP_RB 0x40120440 +#define PVR_440GP_RC 0x40120481 +#define PVR_440EP_RA 0x42221850 +#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440GX_RA 0x51B21850 +#define PVR_440GX_RB 0x51B21851 +#define PVR_440GX_RC 0x51B21892 +#define PVR_440GX_RF 0x51B21894 +#define PVR_405EP_RB 0x51210950 +#define PVR_440SP_RA 0x53221850 +#define PVR_440SP_RB 0x53221891 +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 + +#define PVR_85xx 0x80200000 +#define PVR_85xx_REV1 (PVR_85xx | 0x0010) +#define PVR_85xx_REV2 (PVR_85xx | 0x0020) + + +/* + * For the 8xx processors, all of them report the same PVR family for + * the PowerPC core. The various versions of these processors must be + * differentiated by the version number in the Communication Processor + * Module (CPM). + */ +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_7400 0x000C0000 +#define PVR_8240 0x00810100 + +/* + * PowerQUICC II family processors report different PVR values depending + * on silicon process (HiP3, HiP4, HiP7, etc.) + */ +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 +#define PVR_8260_HIP7R1 0x80822013 +#define PVR_8260_HIP7RA 0x80822014 + + +/* + * System Version Register + */ + +/* System Version Register (SVR) field extraction */ + +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ + +#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ +#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ + + +/* + * SVR_VER() Version Values + */ + +#define SVR_8540 0x8030 +#define SVR_8560 0x8070 +#define SVR_8555 0x8079 +#define SVR_8541 0x807A +#define SVR_8548 0x8031 +#define SVR_8548_E 0x8039 + + +/* I am just adding a single entry for 8260 boards. I think we may be + * able to combine mbx, fads, rpxlite, bseip, and classic into a single + * generic 8xx as well. The boards containing these processors are either + * identical at the processor level (due to the high integration) or so + * wildly different that testing _machine at run time is best replaced by + * conditional compilation by board type (found in their respective .h file). + * -- Dan + */ +#define _MACH_prep 0x00000001 +#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */ +#define _MACH_chrp 0x00000004 /* chrp machine */ +#define _MACH_mbx 0x00000008 /* Motorola MBX board */ +#define _MACH_apus 0x00000010 /* amiga with phase5 powerup */ +#define _MACH_fads 0x00000020 /* Motorola FADS board */ +#define _MACH_rpxlite 0x00000040 /* RPCG RPX-Lite 8xx board */ +#define _MACH_bseip 0x00000080 /* Bright Star Engineering ip-Engine */ +#define _MACH_yk 0x00000100 /* Motorola Yellowknife */ +#define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */ +#define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */ +#define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */ +#define _MACH_walnut 0x00001000 /* AMCC "Walnut" 405GP eval. board */ +#define _MACH_8260 0x00002000 /* Generic 8260 */ +#define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */ +#define _MACH_tqm860 0x00008000 /* TQM860/L */ +#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */ +#define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */ + + +/* see residual.h for these */ +#define _PREP_Motorola 0x01 /* motorola prep */ +#define _PREP_Firm 0x02 /* firmworks prep */ +#define _PREP_IBM 0x00 /* ibm prep */ +#define _PREP_Bull 0x03 /* bull prep */ +#define _PREP_Radstone 0x04 /* Radstone Technology PLC prep */ + +/* + * Radstone board types + */ +#define RS_SYS_TYPE_PPC1 0 +#define RS_SYS_TYPE_PPC2 1 +#define RS_SYS_TYPE_PPC1a 2 +#define RS_SYS_TYPE_PPC2a 3 +#define RS_SYS_TYPE_PPC4 4 +#define RS_SYS_TYPE_PPC4a 5 +#define RS_SYS_TYPE_PPC2ep 6 + +/* these are arbitrary */ +#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ +#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ + +#define _GLOBAL(n)\ + .globl n;\ +n: + +/* Macros for setting and retrieving special purpose registers */ + +#define stringify(s) tostring(s) +#define tostring(s) #s + +#define mfdcr(rn) ({unsigned int rval; \ + asm volatile("mfdcr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) + +#define mfmsr() ({unsigned int rval; \ + asm volatile("mfmsr %0" : "=r" (rval)); rval;}) +#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) + +#define mfspr(rn) ({unsigned int rval; \ + asm volatile("mfspr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) + +#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) + +/* Segment Registers */ + +#define SR0 0 +#define SR1 1 +#define SR2 2 +#define SR3 3 +#define SR4 4 +#define SR5 5 +#define SR6 6 +#define SR7 7 +#define SR8 8 +#define SR9 9 +#define SR10 10 +#define SR11 11 +#define SR12 12 +#define SR13 13 +#define SR14 14 +#define SR15 15 + +#ifndef __ASSEMBLY__ +#ifndef CONFIG_MACH_SPECIFIC +extern int _machine; +extern int have_of; +#endif /* CONFIG_MACH_SPECIFIC */ + +/* what kind of prep workstation we are */ +extern int _prep_type; +/* + * This is used to identify the board type from a given PReP board + * vendor. Board revision is also made available. + */ +extern unsigned char ucSystemType; +extern unsigned char ucBoardRev; +extern unsigned char ucBoardRevMaj, ucBoardRevMin; + +struct task_struct; +void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); +void release_thread(struct task_struct *); + +/* + * Create a new kernel thread. + */ +extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +/* + * Bus types + */ +#define EISA_bus 0 +#define EISA_bus__is_a_macro /* for versions in ksyms.c */ +#define MCA_bus 0 +#define MCA_bus__is_a_macro /* for versions in ksyms.c */ + +/* Lazy FPU handling on uni-processor */ +extern struct task_struct *last_task_used_math; +extern struct task_struct *last_task_used_altivec; + +/* + * this is the minimum allowable io space due to the location + * of the io areas on prep (first one at 0x80000000) but + * as soon as I get around to remapping the io areas with the BATs + * to match the mac we can raise this. -- Cort + */ +#define TASK_SIZE (0x80000000UL) + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) + +typedef struct { + unsigned long seg; +} mm_segment_t; + +struct thread_struct { + unsigned long ksp; /* Kernel stack pointer */ + unsigned long wchan; /* Event task is sleeping on */ + struct pt_regs *regs; /* Pointer to saved register state */ + mm_segment_t fs; /* for get_fs() validation */ + void *pgdir; /* root of page-table tree */ + signed long last_syscall; + double fpr[32]; /* Complete floating point set */ + unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ + unsigned long fpscr; /* Floating point status */ +#ifdef CONFIG_ALTIVEC + vector128 vr[32]; /* Complete AltiVec set */ + vector128 vscr; /* AltiVec status */ + unsigned long vrsave; +#endif /* CONFIG_ALTIVEC */ +}; + +#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) + +#define INIT_THREAD { \ + INIT_SP, /* ksp */ \ + 0, /* wchan */ \ + (struct pt_regs *)INIT_SP - 1, /* regs */ \ + KERNEL_DS, /*fs*/ \ + swapper_pg_dir, /* pgdir */ \ + 0, /* last_syscall */ \ + {0}, 0, 0 \ +} + +/* + * Note: the vm_start and vm_end fields here should *not* + * be in kernel space. (Could vm_end == vm_start perhaps?) + */ +#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ + PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ + 1, NULL, NULL } + +/* + * Return saved PC of a blocked thread. For now, this is the "user" PC + */ +static inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + return (t->regs) ? t->regs->nip : 0; +} + +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) +#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) + +/* + * NOTE! The task struct and the stack go together + */ +#define THREAD_SIZE (2*PAGE_SIZE) +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + +/* in process.c - for early bootup debug -- Cort */ +int ll_printk(const char *, ...); +void ll_puts(const char *); + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +/* In misc.c */ +void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); + +#endif /* ndef ASSEMBLY*/ + +#ifdef CONFIG_MACH_SPECIFIC +#if defined(CONFIG_8xx) +#define _machine _MACH_8xx +#define have_of 0 +#elif defined(CONFIG_OAK) +#define _machine _MACH_oak +#define have_of 0 +#elif defined(CONFIG_WALNUT) +#define _machine _MACH_walnut +#define have_of 0 +#elif defined(CONFIG_APUS) +#define _machine _MACH_apus +#define have_of 0 +#elif defined(CONFIG_GEMINI) +#define _machine _MACH_gemini +#define have_of 0 +#elif defined(CONFIG_8260) +#define _machine _MACH_8260 +#define have_of 0 +#elif defined(CONFIG_SANDPOINT) +#define _machine _MACH_sandpoint +#elif defined(CONFIG_HIDDEN_DRAGON) +#define _machine _MACH_hidden_dragon +#define have_of 0 +#else +#error "Machine not defined correctly" +#endif +#endif /* CONFIG_MACH_SPECIFIC */ + +#endif /* __ASM_PPC_PROCESSOR_H */ diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h new file mode 100644 index 0000000..3c2f4e6 --- /dev/null +++ b/include/asm-ppc/ptrace.h @@ -0,0 +1,107 @@ +#ifndef _PPC_PTRACE_H +#define _PPC_PTRACE_H + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + * + * this should only contain volatile regs + * since we can keep non-volatile in the thread_struct + * should set this up when only volatiles are saved + * by intr code. + * + * Since this is going on the stack, *CARE MUST BE TAKEN* to insure + * that the overall structure is a multiple of 16 bytes in length. + * + * Note that the offsets of the fields in this struct correspond with + * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. + */ + +#include + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_PPC64BRIDGE +#define PPC_REG unsigned long /*long*/ +#else +#define PPC_REG unsigned long +#endif +struct pt_regs { + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ +}; +#endif + +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ + +/* Size of stack frame allocated when calling signal handler. */ +#define __SIGNAL_FRAMESIZE 64 + +#define instruction_pointer(regs) ((regs)->nip) +#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) + +/* + * Offsets used by 'ptrace' system call interface. + * These can't be changed without breaking binary compatibility + * with MkLinux, etc. + */ +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 + +#define PT_NIP 32 +#define PT_MSR 33 +#ifdef __KERNEL__ +#define PT_ORIG_R3 34 +#endif +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 + +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR31 (PT_FPR0 + 2*31) +#define PT_FPSCR (PT_FPR0 + 2*32 + 1) + +#endif diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h new file mode 100644 index 0000000..dc85edb --- /dev/null +++ b/include/asm-ppc/residual.h @@ -0,0 +1,331 @@ +/* 7/18/95 */ +/*----------------------------------------------------------------------------*/ +/* Residual Data header definitions and prototypes */ +/*----------------------------------------------------------------------------*/ + +/* Structure map for RESIDUAL on PowerPC Reference Platform */ +/* residual.h - Residual data structure passed in r3. */ +/* Load point passed in r4 to boot image. */ +/* For enum's: if given in hex then they are bit significant, */ +/* i.e. only one bit is on for each enum */ +/* Reserved fields must be filled with zeros. */ + +#ifndef _RESIDUAL_ +#define _RESIDUAL_ + +#ifndef __ASSEMBLY__ + +#define MAX_CPUS 32 /* These should be set to the maximum */ +#define MAX_MEMS 64 /* number possible for this system. */ +#define MAX_DEVICES 256 /* Changing these will change the */ +#define AVE_PNP_SIZE 32 /* structure, hence the version of */ +#define MAX_MEM_SEGS 64 /* this header file. */ + +/*----------------------------------------------------------------------------*/ +/* Public structures... */ +/*----------------------------------------------------------------------------*/ + +#include "pnp.h" + +typedef enum _L1CACHE_TYPE { + NoneCAC = 0, + SplitCAC = 1, + CombinedCAC = 2 + } L1CACHE_TYPE; + +typedef enum _TLB_TYPE { + NoneTLB = 0, + SplitTLB = 1, + CombinedTLB = 2 + } TLB_TYPE; + +typedef enum _FIRMWARE_SUPPORT { + Conventional = 0x01, + OpenFirmware = 0x02, + Diagnostics = 0x04, + LowDebug = 0x08, + Multiboot = 0x10, + LowClient = 0x20, + Hex41 = 0x40, + FAT = 0x80, + ISO9660 = 0x0100, + SCSI_InitiatorID_Override = 0x0200, + Tape_Boot = 0x0400, + FW_Boot_Path = 0x0800 + } FIRMWARE_SUPPORT; + +typedef enum _FIRMWARE_SUPPLIERS { + IBMFirmware = 0x00, + MotoFirmware = 0x01, /* 7/18/95 */ + FirmWorks = 0x02, /* 10/5/95 */ + Bull = 0x03, /* 04/03/96 */ + } FIRMWARE_SUPPLIERS; + +typedef enum _ENDIAN_SWITCH_METHODS { + UsePort92 = 0x01, + UsePCIConfigA8 = 0x02, + UseFF001030 = 0x03, + } ENDIAN_SWITCH_METHODS; + +typedef enum _SPREAD_IO_METHODS { + UsePort850 = 0x00, +/*UsePCIConfigA8 = 0x02,*/ + } SPREAD_IO_METHODS; + +typedef struct _VPD { + + /* Box dependent stuff */ + unsigned char PrintableModel[32]; /* Null terminated string. + Must be of the form: + vvv,<20h>,,<0x0> + where vvv is the vendor ID + e.g. IBM PPS MODEL 6015<0x0> */ + unsigned char Serial[16]; /* 12/94: + Serial Number; must be of the form: + vvv where vvv is the + vendor ID. + e.g. IBM60151234567<20h><20h> */ + unsigned char Reserved[48]; + unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ + unsigned long FirmwareSupports; /* See FirmwareSupport enum */ + unsigned long NvramSize; /* Size of nvram in bytes */ + unsigned long NumSIMMSlots; + unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ + unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ + unsigned long SmpIar; + unsigned long RAMErrLogOffset; /* Heap offset to error log */ + unsigned long Reserved5; + unsigned long Reserved6; + unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ + unsigned long ProcessorBusHz; /* Processor bus clock frequency */ + unsigned long Reserved7; + unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ + unsigned long WordWidth; /* Word width in bits */ + unsigned long PageSize; /* Page size in bytes */ + unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache + for which coherency is maintained; + normally <= CacheLineSize. */ + unsigned long GranuleSize; /* Unit of lock allocation to avoid */ + /* false sharing of locks. */ + + /* L1 Cache variables */ + unsigned long CacheSize; /* L1 Cache size in KB. This is the */ + /* total size of the L1, whether */ + /* combined or split */ + unsigned long CacheAttrib; /* L1CACHE_TYPE */ + unsigned long CacheAssoc; /* L1 Cache associativity. Use this + for combined cache. If split, put + zeros here. */ + unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use + for combined cache. If split, put + zeros here. */ + /* For split L1 Cache: (= combined if combined cache) */ + unsigned long I_CacheSize; + unsigned long I_CacheAssoc; + unsigned long I_CacheLineSize; + unsigned long D_CacheSize; + unsigned long D_CacheAssoc; + unsigned long D_CacheLineSize; + + /* Translation Lookaside Buffer variables */ + unsigned long TLBSize; /* Total number of TLBs on the system */ + unsigned long TLBAttrib; /* Combined I+D or split TLB */ + unsigned long TLBAssoc; /* TLB Associativity. Use this for + combined TLB. If split, put zeros + here. */ + /* For split TLB: (= combined if combined TLB) */ + unsigned long I_TLBSize; + unsigned long I_TLBAssoc; + unsigned long D_TLBSize; + unsigned long D_TLBAssoc; + + unsigned long ExtendedVPD; /* Offset to extended VPD area; + null if unused */ + } VPD; + +typedef enum _DEVICE_FLAGS { + Enabled = 0x4000, /* 1 - PCI device is enabled */ + Integrated = 0x2000, + Failed = 0x1000, /* 1 - device failed POST code tests */ + Static = 0x0800, /* 0 - dynamically configurable + 1 - static */ + Dock = 0x0400, /* 0 - not a docking station device + 1 - is a docking station device */ + Boot = 0x0200, /* 0 - device cannot be used for BOOT + 1 - can be a BOOT device */ + Configurable = 0x0100, /* 1 - device is configurable */ + Disableable = 0x80, /* 1 - device can be disabled */ + PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ + ReadOnly = 0x20, /* 1 - device is read only */ + Removable = 0x10, /* 1 - device is removable */ + ConsoleIn = 0x08, + ConsoleOut = 0x04, + Input = 0x02, + Output = 0x01 + } DEVICE_FLAGS; + +typedef enum _BUS_ID { + ISADEVICE = 0x01, + EISADEVICE = 0x02, + PCIDEVICE = 0x04, + PCMCIADEVICE = 0x08, + PNPISADEVICE = 0x10, + MCADEVICE = 0x20, + MXDEVICE = 0x40, /* Devices on mezzanine bus */ + PROCESSORDEVICE = 0x80, /* Devices on processor bus */ + VMEDEVICE = 0x100, + } BUS_ID; + +typedef struct _DEVICE_ID { + unsigned long BusId; /* See BUS_ID enum above */ + unsigned long DevId; /* Big Endian format */ + unsigned long SerialNum; /* For multiple usage of a single + DevId */ + unsigned long Flags; /* See DEVICE_FLAGS enum above */ + unsigned char BaseType; /* See pnp.h for bit definitions */ + unsigned char SubType; /* See pnp.h for bit definitions */ + unsigned char Interface; /* See pnp.h for bit definitions */ + unsigned char Spare; + } DEVICE_ID; + +typedef union _BUS_ACCESS { + struct _PnPAccess{ + unsigned char CSN; + unsigned char LogicalDevNumber; + unsigned short ReadDataPort; + } PnPAccess; + struct _ISAAccess{ + unsigned char SlotNumber; /* ISA Slot Number generally not + available; 0 if unknown */ + unsigned char LogicalDevNumber; + unsigned short ISAReserved; + } ISAAccess; + struct _MCAAccess{ + unsigned char SlotNumber; + unsigned char LogicalDevNumber; + unsigned short MCAReserved; + } MCAAccess; + struct _PCMCIAAccess{ + unsigned char SlotNumber; + unsigned char LogicalDevNumber; + unsigned short PCMCIAReserved; + } PCMCIAAccess; + struct _EISAAccess{ + unsigned char SlotNumber; + unsigned char FunctionNumber; + unsigned short EISAReserved; + } EISAAccess; + struct _PCIAccess{ + unsigned char BusNumber; + unsigned char DevFuncNumber; + unsigned short PCIReserved; + } PCIAccess; + struct _ProcBusAccess{ + unsigned char BusNumber; + unsigned char BUID; + unsigned short ProcBusReserved; + } ProcBusAccess; + } BUS_ACCESS; + +/* Per logical device information */ +typedef struct _PPC_DEVICE { + DEVICE_ID DeviceId; + BUS_ACCESS BusAccess; + + /* The following three are offsets into the DevicePnPHeap */ + /* All are in PnP compressed format */ + unsigned long AllocatedOffset; /* Allocated resource description */ + unsigned long PossibleOffset; /* Possible resource description */ + unsigned long CompatibleOffset; /* Compatible device identifiers */ + } PPC_DEVICE; + +typedef enum _CPU_STATE { + CPU_GOOD = 0, /* CPU is present, and active */ + CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ + CPU_OFF = 2, /* CPU is present, but inactive */ + CPU_FAILED = 3, /* CPU is present, but failed POST */ + CPU_NOT_PRESENT = 255 /* CPU not present */ + } CPU_STATE; + +typedef struct _PPC_CPU { + unsigned long CpuType; /* Result of mfspr from Processor + Version Register (PVR). + PVR(0-15) = Version (e.g. 601) + PVR(16-31 = EC Level */ + unsigned char CpuNumber; /* CPU Number for this processor */ + unsigned char CpuState; /* CPU State, see CPU_STATE enum */ + unsigned short Reserved; + } PPC_CPU; + +typedef struct _PPC_MEM { + unsigned long SIMMSize; /* 0 - absent or bad + 8M, 32M (in MB) */ + } PPC_MEM; + +typedef enum _MEM_USAGE { + Other = 0x8000, + ResumeBlock = 0x4000, /* for use by power management */ + SystemROM = 0x2000, /* Flash memory (populated) */ + UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ + IOMemory = 0x0800, + SystemIO = 0x0400, + SystemRegs = 0x0200, + PCIAddr = 0x0100, + PCIConfig = 0x80, + ISAAddr = 0x40, + Unpopulated = 0x20, /* Unpopulated part of System Memory */ + Free = 0x10, /* Free part of System Memory */ + BootImage = 0x08, /* BootImage part of System Memory */ + FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ + FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ + FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ + } MEM_USAGE; + +typedef struct _MEM_MAP { + unsigned long Usage; /* See MEM_USAGE above */ + unsigned long BasePage; /* Page number measured in 4KB pages */ + unsigned long PageCount; /* Page count measured in 4KB pages */ + } MEM_MAP; + +typedef struct _RESIDUAL { + unsigned long ResidualLength; /* Length of Residual */ + unsigned char Version; /* of this data structure */ + unsigned char Revision; /* of this data structure */ + unsigned short EC; /* of this data structure */ + /* VPD */ + VPD VitalProductData; + /* CPU */ + unsigned short MaxNumCpus; /* Max CPUs in this system */ + unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ + /* that there are unpopulated or */ + /* otherwise unusable cpu locations */ + PPC_CPU Cpus[MAX_CPUS]; + /* Memory */ + unsigned long TotalMemory; /* Total amount of memory installed */ + unsigned long GoodMemory; /* Total amount of good memory */ + unsigned long ActualNumMemSegs; + MEM_MAP Segs[MAX_MEM_SEGS]; + unsigned long ActualNumMemories; + PPC_MEM Memories[MAX_MEMS]; + /* Devices */ + unsigned long ActualNumDevices; + PPC_DEVICE Devices[MAX_DEVICES]; + unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; + } RESIDUAL; + + +extern RESIDUAL *res; +extern void print_residual_device_info(void); +extern PPC_DEVICE *residual_find_device(unsigned long BusMask, + unsigned char * DevID, int BaseType, + int SubType, int Interface, int n); +extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, + int n); +extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, + unsigned packet_type, + int n); +extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, + unsigned packet_type, + int n); +#endif /* __ASSEMBLY__ */ +#endif /* ndef _RESIDUAL_ */ diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h new file mode 100644 index 0000000..4bd66a7 --- /dev/null +++ b/include/asm-ppc/sigcontext.h @@ -0,0 +1,15 @@ +#ifndef _ASM_PPC_SIGCONTEXT_H +#define _ASM_PPC_SIGCONTEXT_H + +#include + + +struct sigcontext_struct { + unsigned long _unused[4]; + int signal; + unsigned long handler; + unsigned long oldmask; + struct pt_regs *regs; +}; + +#endif diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h new file mode 100644 index 0000000..b11a28e --- /dev/null +++ b/include/asm-ppc/signal.h @@ -0,0 +1,154 @@ +#ifndef _ASMPPC_SIGNAL_H +#define _ASMPPC_SIGNAL_H + +#include + +/* Avoid too many header ordering problems. */ +struct siginfo; + +/* Most things should be clean enough to redefine this at will, if care + is taken to make libc match. */ + +#define _NSIG 64 +#define _NSIG_BPW 32 +#define _NSIG_WORDS (_NSIG / _NSIG_BPW) + +typedef unsigned long old_sigset_t; /* at least 32 bits */ + +typedef struct { + unsigned long sig[_NSIG_WORDS]; +} sigset_t; + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +#define SIGABRT 6 +#define SIGIOT 6 +#define SIGBUS 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGUSR1 10 +#define SIGSEGV 11 +#define SIGUSR2 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGSTKFLT 16 +#define SIGCHLD 17 +#define SIGCONT 18 +#define SIGSTOP 19 +#define SIGTSTP 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGURG 23 +#define SIGXCPU 24 +#define SIGXFSZ 25 +#define SIGVTALRM 26 +#define SIGPROF 27 +#define SIGWINCH 28 +#define SIGIO 29 +#define SIGPOLL SIGIO +/* +#define SIGLOST 29 +*/ +#define SIGPWR 30 +#define SIGSYS 31 +#define SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define SIGRTMIN 32 +#define SIGRTMAX (_NSIG-1) + +/* + * SA_FLAGS values: + * + * SA_ONSTACK is not currently supported, but will allow sigaltstack(2). + * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_RESETHAND clears the handler when the signal is delivered. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_NODEFER prevents the current signal from being masked in the handler. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + */ +#define SA_NOCLDSTOP 0x00000001 +#define SA_NOCLDWAIT 0x00000002 /* not supported yet */ +#define SA_SIGINFO 0x00000004 +#define SA_ONSTACK 0x08000000 +#define SA_RESTART 0x10000000 +#define SA_NODEFER 0x40000000 +#define SA_RESETHAND 0x80000000 + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND +#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */ + +#define SA_RESTORER 0x04000000 + +/* + * sigaltstack controls + */ +#define SS_ONSTACK 1 +#define SS_DISABLE 2 + +#define MINSIGSTKSZ 2048 +#define SIGSTKSZ 8192 +#ifdef __KERNEL__ + +/* + * These values of sa_flags are used only by the kernel as part of the + * irq handling routines. + * + * SA_INTERRUPT is also used by the irq handling routines. + * SA_SHIRQ is for shared interrupt support on PCI and EISA. + */ +#define SA_PROBE SA_ONESHOT +#define SA_SAMPLE_RANDOM SA_RESTART +#define SA_SHIRQ 0x04000000 +#endif + +#define SIG_BLOCK 0 /* for blocking signals */ +#define SIG_UNBLOCK 1 /* for unblocking signals */ +#define SIG_SETMASK 2 /* for setting the signal mask */ + +/* Type of a signal handler. */ +typedef void (*__sighandler_t)(int); + +#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ +#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ +#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ + +struct old_sigaction { + __sighandler_t sa_handler; + old_sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +struct sigaction { + __sighandler_t sa_handler; + unsigned long sa_flags; + void (*sa_restorer)(void); + sigset_t sa_mask; /* mask last for extensibility */ +}; + +struct k_sigaction { + struct sigaction sa; +}; + +typedef struct sigaltstack { + void *ss_sp; + int ss_flags; + size_t ss_size; +} stack_t; + +#ifdef __KERNEL__ +#include + +#endif + +#endif diff --git a/include/asm-ppc/status_led.h b/include/asm-ppc/status_led.h new file mode 100644 index 0000000..eb81f37 --- /dev/null +++ b/include/asm-ppc/status_led.h @@ -0,0 +1,77 @@ +/* + * asm/status_led.h + * + * MPC8xx/MPC8260/MPC5xx based status led support functions + */ + +#ifndef __ASM_STATUS_LED_H__ +#define __ASM_STATUS_LED_H__ + +/* if not overriden */ +#ifndef CONFIG_BOARD_SPECIFIC_LED +# if defined(CONFIG_8xx) +# include +# elif defined(CONFIG_8260) +# include +# elif defined(CONFIG_5xx) +# include +# else +# error CPU specific Status LED header file missing. +#endif + +/* led_id_t is unsigned long mask */ +typedef unsigned long led_id_t; + +static inline void __led_init (led_id_t mask, int state) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + +#ifdef STATUS_LED_PAR + immr->STATUS_LED_PAR &= ~mask; +#endif +#ifdef STATUS_LED_ODR + immr->STATUS_LED_ODR &= ~mask; +#endif + +#if (STATUS_LED_ACTIVE == 0) + if (state == STATUS_LED_ON) + immr->STATUS_LED_DAT &= ~mask; + else + immr->STATUS_LED_DAT |= mask; +#else + if (state == STATUS_LED_ON) + immr->STATUS_LED_DAT |= mask; + else + immr->STATUS_LED_DAT &= ~mask; +#endif +#ifdef STATUS_LED_DIR + immr->STATUS_LED_DIR |= mask; +#endif +} + +static inline void __led_toggle (led_id_t mask) +{ + ((immap_t *) CFG_IMMR)->STATUS_LED_DAT ^= mask; +} + +static inline void __led_set (led_id_t mask, int state) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + +#if (STATUS_LED_ACTIVE == 0) + if (state == STATUS_LED_ON) + immr->STATUS_LED_DAT &= ~mask; + else + immr->STATUS_LED_DAT |= mask; +#else + if (state == STATUS_LED_ON) + immr->STATUS_LED_DAT |= mask; + else + immr->STATUS_LED_DAT &= ~mask; +#endif + +} + +#endif + +#endif /* __ASM_STATUS_LED_H__ */ diff --git a/include/asm-ppc/string.h b/include/asm-ppc/string.h new file mode 100644 index 0000000..d912a6b --- /dev/null +++ b/include/asm-ppc/string.h @@ -0,0 +1,29 @@ +#ifndef _PPC_STRING_H_ +#define _PPC_STRING_H_ + +#define __HAVE_ARCH_STRCPY +#define __HAVE_ARCH_STRNCPY +#define __HAVE_ARCH_STRLEN +#define __HAVE_ARCH_STRCMP +#define __HAVE_ARCH_STRCAT +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_BCOPY +#define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMMOVE +#define __HAVE_ARCH_MEMCMP +#define __HAVE_ARCH_MEMCHR + +extern int strcasecmp(const char *, const char *); +extern int strncasecmp(const char *, const char *, int); +extern char * strcpy(char *,const char *); +extern char * strncpy(char *,const char *, __kernel_size_t); +extern __kernel_size_t strlen(const char *); +extern int strcmp(const char *,const char *); +extern char * strcat(char *, const char *); +extern void * memset(void *,int,__kernel_size_t); +extern void * memcpy(void *,const void *,__kernel_size_t); +extern void * memmove(void *,const void *,__kernel_size_t); +extern int memcmp(const void *,const void *,__kernel_size_t); +extern void * memchr(const void *,int,__kernel_size_t); + +#endif diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h new file mode 100644 index 0000000..4ebbb9e --- /dev/null +++ b/include/asm-ppc/types.h @@ -0,0 +1,50 @@ +#ifndef _PPC_TYPES_H +#define _PPC_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +typedef struct { + __u32 u[4]; +} __attribute((aligned(16))) vector128; + +#ifdef __KERNEL__ +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* DMA addresses are 32-bits wide */ +typedef u32 dma_addr_t; + +#endif /* __KERNEL__ */ +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h new file mode 100644 index 0000000..f7aa55f --- /dev/null +++ b/include/asm-ppc/u-boot.h @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2000 - 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __U_BOOT_H__ +#define __U_BOOT_H__ + +/* + * Board information passed to Linux kernel from U-Boot + * + * include/asm-ppc/u-boot.h + */ + +#ifndef __ASSEMBLY__ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ + || defined(CONFIG_E500) + unsigned long bi_immr_base; /* base of IMMR register */ +#endif +#if defined(CONFIG_MPC5xxx) + unsigned long bi_mbar_base; /* base of internal registers */ +#endif +#if defined(CONFIG_MPC83XX) + unsigned long bi_immrbar; +#endif +#if defined(CONFIG_MPC8220) + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_inpfreq; /* Input Freq, In MHz */ + unsigned long bi_pcifreq; /* PCI Freq, in MHz */ + unsigned long bi_pevfreq; /* PEV Freq, in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ + unsigned long bi_vcofreq; /* VCO Freq, in MHz */ +#endif + unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ +#if defined(CONFIG_CPM2) + unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ + unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ + unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ + unsigned long bi_vco; /* VCO Out from PLL, in MHz */ +#endif +#if defined(CONFIG_MPC5xxx) + unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ + unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ +#endif + unsigned long bi_baudrate; /* Console Baudrate */ +#if defined(CONFIG_405) || \ + defined(CONFIG_405GP) || \ + defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || \ + defined(CONFIG_440) + unsigned char bi_s_version[4]; /* Version of this structure */ + unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ + unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ + unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ + unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ +#endif +#if defined(CONFIG_HYMOD) + hymod_conf_t bi_hymod_conf; /* hymod configuration information */ +#endif + +#ifdef CONFIG_HAS_ETH1 + /* second onboard ethernet port */ + unsigned char bi_enet1addr[6]; +#endif +#ifdef CONFIG_HAS_ETH2 + /* third onboard ethernet port */ + unsigned char bi_enet2addr[6]; +#endif +#ifdef CONFIG_HAS_ETH3 + unsigned char bi_enet3addr[6]; +#endif + +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) + unsigned int bi_opbfreq; /* OPB clock in Hz */ + int bi_iic_fast[2]; /* Use fast i2c mode */ +#endif +#if defined(CONFIG_NX823) + unsigned char bi_sernum[8]; +#endif +#if defined(CONFIG_4xx) +#if defined(CONFIG_440GX) + int bi_phynum[4]; /* Determines phy mapping */ + int bi_phymode[4]; /* Determines phy mode */ +#elif defined(CONFIG_405EP) || defined(CONFIG_440) + int bi_phynum[2]; /* Determines phy mapping */ + int bi_phymode[2]; /* Determines phy mode */ +#else + int bi_phynum[1]; /* Determines phy mapping */ + int bi_phymode[1]; /* Determines phy mode */ +#endif +#endif /* defined(CONFIG_4xx) */ +} bd_t; + +#endif /* __ASSEMBLY__ */ +#endif /* __U_BOOT_H__ */ diff --git a/include/at91rm9200_i2c.h b/include/at91rm9200_i2c.h new file mode 100644 index 0000000..c2ec2f1 --- /dev/null +++ b/include/at91rm9200_i2c.h @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* The software is delivered "AS IS" without warranty or condition of any */ +/* kind, either express, implied or statutory. This includes without */ +/* limitation any warranty or condition with respect to merchantability or */ +/* fitness for any particular purpose, or against the infringements of */ +/* intellectual property rights of others. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : at91rm9200_i2c.h */ +/* Object : AT91RM9200 / TWI definitions */ +/* Generated : AT91 SW Application Group 12/03/2002 (10:48:02) */ +/* */ +/* ---------------------------------------------------------------------------- */ + +#ifndef AT91RM9200_TWI_H +#define AT91RM9200_TWI_H + +/* ******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ******************************************************************************/ +#ifndef __ASSEMBLY__ + +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG TWI_SMR; /* Slave Mode Register */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved0[3]; + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[50]; + AT91_REG TWI_RPR; /* Receive Pointer Register */ + AT91_REG TWI_RCR; /* Receive Counter Register */ + AT91_REG TWI_TPR; /* Transmit Pointer Register */ + AT91_REG TWI_TCR; /* Transmit Counter Register */ + AT91_REG TWI_RNPR; /* Receive Next Pointer Register */ + AT91_REG TWI_RNCR; /* Receive Next Counter Register */ + AT91_REG TWI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG TWI_TNCR; /* Transmit Next Counter Register */ + AT91_REG TWI_PTCR; /* PDC Transfer Control Register */ + AT91_REG TWI_PTSR; /* PDC Transfer Status Register */ +} AT91S_TWI, *AT91PS_TWI; + +#endif + +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START (0x1 << 0) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP (0x1 << 1) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN (0x1 << 2) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS (0x1 << 3) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SVEN (0x1 << 4) /* (TWI) TWI Slave Transfer Enabled */ +#define AT91C_TWI_SVDIS (0x1 << 5) /* (TWI) TWI Slave Transfer Disabled */ +#define AT91C_TWI_SWRST (0x1 << 7) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ (0x3 << 8) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD (0x1 << 12) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR (0x7F << 6) /* (TWI) Device Address */ +/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */ +#define AT91C_TWI_SADR (0x7F << 16) /* (TWI) Slave Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV (0xFF << 0) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV (0xFF << 8) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV (0x7 << 16) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP (0x1 << 0) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY (0x1 << 1) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY (0x1 << 2) /* (TWI) Transmit holding register ReaDY*/ +#define AT91C_TWI_SVREAD (0x1 << 3) /* (TWI) Slave Read */ +#define AT91C_TWI_SVACC (0x1 << 4) /* (TWI) Slave Access */ +#define AT91C_TWI_GCACC (0x1 << 5) /* (TWI) General Call Access */ +#define AT91C_TWI_OVRE (0x1 << 6) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE (0x1 << 7) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK (0x1 << 8) /* (TWI) Not Acknowledged */ +#define AT91C_TWI_ARBLST (0x1 << 9) /* (TWI) Arbitration Lost */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register ------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* + i2c Support for Atmel's AT91RM9200 Two-Wire Interface + + (c) Rick Bronson + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef AT91_I2C_H +#define AT91_I2C_H + +#define AT91C_TWI_CLOCK 100000 +#define AT91C_TWI_SCLOCK (10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK) +#define AT91C_TWI_CKDIV1 (2 << 16) /* TWI clock divider. NOTE: see Errata #22 */ + +#if (AT91C_TWI_SCLOCK % 10) >= 5 +#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5) +#else +#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6) +#endif +#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2) + +#define AT91C_EEPROM_I2C_ADDRESS (0x50 << 16) + +#endif /* __ASSEMBLY__ */ +#endif /* AT91RM9200_TWI_H */ diff --git a/include/at91rm9200_net.h b/include/at91rm9200_net.h new file mode 100644 index 0000000..f799206 --- /dev/null +++ b/include/at91rm9200_net.h @@ -0,0 +1,57 @@ +/* + * Ethernet: An implementation of the Ethernet Device Driver suite for the + * uClinux 2.0.38 operating system. This Driver has been developed + * for AT75C220 board. + * + * NOTE: The driver is implemented for one MAC + * + * Version: @(#)at91rm9200_net.h 1.0.0 01/10/2001 + * + * Authors: Lineo Inc + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef AT91RM9200_ETHERNET +#define AT91RM9200_ETHERNET + +#include +#include +#include + +#define FALSE 0 +#define TRUE 1 + + +#define ETHERNET_ADDRESS_SIZE 6 + +typedef unsigned char UCHAR; + +/* Interface to drive the physical layer */ +typedef struct _AT91S_PhyOps +{ + unsigned char (*Init)(AT91S_EMAC *pmac); + unsigned int (*IsPhyConnected)(AT91S_EMAC *pmac); + unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac); + unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *); + +} AT91S_PhyOps,*AT91PS_PhyOps; + + +#define EMAC_DESC_DONE 0x00000001 /* ownership bit */ +#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */ + +/****************** function prototypes **********************/ + +/* MII functions */ +void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac); +void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac); +UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput); +UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput); +void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops); + +#endif /* AT91RM9200_ETHERNET */ diff --git a/include/ata.h b/include/ata.h new file mode 100644 index 0000000..8584226 --- /dev/null +++ b/include/ata.h @@ -0,0 +1,258 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Most of the following information was derived from the document + * "Information Technology - AT Attachment-3 Interface (ATA-3)" + * which can be found at: + * http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip + * ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP + * ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip + */ + +#ifndef _ATA_H +#define _ATA_H + +/* Register addressing depends on the hardware design; for instance, + * 8-bit (register) and 16-bit (data) accesses might use different + * address spaces. This is implemented by the following definitions. + */ +#ifndef CFG_ATA_STRIDE +#define CFG_ATA_STRIDE 1 +#endif + +#define ATA_IO_DATA(x) (CFG_ATA_DATA_OFFSET+((x) * CFG_ATA_STRIDE)) +#define ATA_IO_REG(x) (CFG_ATA_REG_OFFSET +((x) * CFG_ATA_STRIDE)) +#define ATA_IO_ALT(x) (CFG_ATA_ALT_OFFSET +((x) * CFG_ATA_STRIDE)) + +/* + * I/O Register Descriptions + */ +#define ATA_DATA_REG ATA_IO_DATA(0) +#define ATA_ERROR_REG ATA_IO_REG(1) +#define ATA_SECT_CNT ATA_IO_REG(2) +#define ATA_SECT_NUM ATA_IO_REG(3) +#define ATA_CYL_LOW ATA_IO_REG(4) +#define ATA_CYL_HIGH ATA_IO_REG(5) +#define ATA_DEV_HD ATA_IO_REG(6) +#define ATA_COMMAND ATA_IO_REG(7) +#define ATA_DATA_EVEN ATA_IO_REG(8) +#define ATA_DATA_ODD ATA_IO_REG(9) +#define ATA_STATUS ATA_COMMAND +#define ATA_DEV_CTL ATA_IO_ALT(6) +#define ATA_LBA_LOW ATA_SECT_NUM +#define ATA_LBA_MID ATA_CYL_LOW +#define ATA_LBA_HIGH ATA_CYL_HIGH +#define ATA_LBA_SEL ATA_DEV_CTL + +/* + * Status register bits + */ +#define ATA_STAT_BUSY 0x80 /* Device Busy */ +#define ATA_STAT_READY 0x40 /* Device Ready */ +#define ATA_STAT_FAULT 0x20 /* Device Fault */ +#define ATA_STAT_SEEK 0x10 /* Device Seek Complete */ +#define ATA_STAT_DRQ 0x08 /* Data Request (ready) */ +#define ATA_STAT_CORR 0x04 /* Corrected Data Error */ +#define ATA_STAT_INDEX 0x02 /* Vendor specific */ +#define ATA_STAT_ERR 0x01 /* Error */ + +/* + * Device / Head Register Bits + */ +#define ATA_DEVICE(x) ((x & 1)<<4) +#define ATA_LBA 0xE0 + +/* + * ATA Commands (only mandatory commands listed here) + */ +#define ATA_CMD_READ 0x20 /* Read Sectors (with retries) */ +#define ATA_CMD_READN 0x21 /* Read Sectors ( no retries) */ +#define ATA_CMD_WRITE 0x30 /* Write Sectores (with retries)*/ +#define ATA_CMD_WRITEN 0x31 /* Write Sectors ( no retries)*/ +#define ATA_CMD_VRFY 0x40 /* Read Verify (with retries) */ +#define ATA_CMD_VRFYN 0x41 /* Read verify ( no retries) */ +#define ATA_CMD_SEEK 0x70 /* Seek */ +#define ATA_CMD_DIAG 0x90 /* Execute Device Diagnostic */ +#define ATA_CMD_INIT 0x91 /* Initialize Device Parameters */ +#define ATA_CMD_RD_MULT 0xC4 /* Read Multiple */ +#define ATA_CMD_WR_MULT 0xC5 /* Write Multiple */ +#define ATA_CMD_SETMULT 0xC6 /* Set Multiple Mode */ +#define ATA_CMD_RD_DMA 0xC8 /* Read DMA (with retries) */ +#define ATA_CMD_RD_DMAN 0xC9 /* Read DMS ( no retries) */ +#define ATA_CMD_WR_DMA 0xCA /* Write DMA (with retries) */ +#define ATA_CMD_WR_DMAN 0xCB /* Write DMA ( no retires) */ +#define ATA_CMD_IDENT 0xEC /* Identify Device */ +#define ATA_CMD_SETF 0xEF /* Set Features */ +#define ATA_CMD_CHK_PWR 0xE5 /* Check Power Mode */ + +#define ATA_CMD_READ_EXT 0x24 /* Read Sectors (with retries) with 48bit addressing */ +#define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */ +#define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */ + +/* + * ATAPI Commands + */ +#define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */ +#define ATAPI_CMD_PACKET 0xA0 /* Packed Command */ + + +#define ATAPI_CMD_INQUIRY 0x12 +#define ATAPI_CMD_REQ_SENSE 0x03 +#define ATAPI_CMD_READ_CAP 0x25 +#define ATAPI_CMD_START_STOP 0x1B +#define ATAPI_CMD_READ_12 0xA8 + + +#define ATA_GET_ERR() inb(ATA_STATUS) +#define ATA_GET_STAT() inb(ATA_STATUS) +#define ATA_OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good)) +#define ATA_BAD_R_STAT (ATA_STAT_BUSY | ATA_STAT_ERR) +#define ATA_BAD_W_STAT (ATA_BAD_R_STAT | ATA_STAT_FAULT) +#define ATA_BAD_STAT (ATA_BAD_R_STAT | ATA_STAT_DRQ) +#define ATA_DRIVE_READY (ATA_READY_STAT | ATA_STAT_SEEK) +#define ATA_DATA_READY (ATA_STAT_DRQ) + +#define ATA_BLOCKSIZE 512 /* bytes */ +#define ATA_BLOCKSHIFT 9 /* 2 ^ ATA_BLOCKSIZESHIFT = 512 */ +#define ATA_SECTORWORDS (512 / sizeof(unsigned long)) + +#ifndef ATA_RESET_TIME +#define ATA_RESET_TIME 60 /* spec allows up to 31 seconds */ +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec + */ +typedef struct hd_driveid { + unsigned short config; /* lots of obsolete bit flags */ + unsigned short cyls; /* "physical" cyls */ + unsigned short reserved2; /* reserved (word 2) */ + unsigned short heads; /* "physical" heads */ + unsigned short track_bytes; /* unformatted bytes per track */ + unsigned short sector_bytes; /* unformatted bytes per sector */ + unsigned short sectors; /* "physical" sectors per track */ + unsigned short vendor0; /* vendor unique */ + unsigned short vendor1; /* vendor unique */ + unsigned short vendor2; /* vendor unique */ + unsigned char serial_no[20]; /* 0 = not_specified */ + unsigned short buf_type; + unsigned short buf_size; /* 512 byte increments; 0 = not_specified */ + unsigned short ecc_bytes; /* for r/w long cmds; 0 = not_specified */ + unsigned char fw_rev[8]; /* 0 = not_specified */ + unsigned char model[40]; /* 0 = not_specified */ + unsigned char max_multsect; /* 0=not_implemented */ + unsigned char vendor3; /* vendor unique */ + unsigned short dword_io; /* 0=not_implemented; 1=implemented */ + unsigned char vendor4; /* vendor unique */ + unsigned char capability; /* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/ + unsigned short reserved50; /* reserved (word 50) */ + unsigned char vendor5; /* vendor unique */ + unsigned char tPIO; /* 0=slow, 1=medium, 2=fast */ + unsigned char vendor6; /* vendor unique */ + unsigned char tDMA; /* 0=slow, 1=medium, 2=fast */ + unsigned short field_valid; /* bits 0:cur_ok 1:eide_ok */ + unsigned short cur_cyls; /* logical cylinders */ + unsigned short cur_heads; /* logical heads */ + unsigned short cur_sectors; /* logical sectors per track */ + unsigned short cur_capacity0; /* logical total sectors on drive */ + unsigned short cur_capacity1; /* (2 words, misaligned int) */ + unsigned char multsect; /* current multiple sector count */ + unsigned char multsect_valid; /* when (bit0==1) multsect is ok */ + unsigned int lba_capacity; /* total number of sectors */ + unsigned short dma_1word; /* single-word dma info */ + unsigned short dma_mword; /* multiple-word dma info */ + unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */ + unsigned short eide_dma_min; /* min mword dma cycle time (ns) */ + unsigned short eide_dma_time; /* recommended mword dma cycle time (ns) */ + unsigned short eide_pio; /* min cycle time (ns), no IORDY */ + unsigned short eide_pio_iordy; /* min cycle time (ns), with IORDY */ + unsigned short words69_70[2]; /* reserved words 69-70 */ + unsigned short words71_74[4]; /* reserved words 71-74 */ + unsigned short queue_depth; /* */ + unsigned short words76_79[4]; /* reserved words 76-79 */ + unsigned short major_rev_num; /* */ + unsigned short minor_rev_num; /* */ + unsigned short command_set_1; /* bits 0:Smart 1:Security 2:Removable 3:PM */ + unsigned short command_set_2; /* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/ + unsigned short cfsse; /* command set-feature supported extensions */ + unsigned short cfs_enable_1; /* command set-feature enabled */ + unsigned short cfs_enable_2; /* command set-feature enabled */ + unsigned short csf_default; /* command set-feature default */ + unsigned short dma_ultra; /* */ + unsigned short word89; /* reserved (word 89) */ + unsigned short word90; /* reserved (word 90) */ + unsigned short CurAPMvalues; /* current APM values */ + unsigned short word92; /* reserved (word 92) */ + unsigned short hw_config; /* hardware config */ + unsigned short words94_99[6];/* reserved words 94-99 */ + /*unsigned long long lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */ + unsigned short lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */ + unsigned short words104_125[22];/* reserved words 104-125 */ + unsigned short last_lun; /* reserved (word 126) */ + unsigned short word127; /* reserved (word 127) */ + unsigned short dlf; /* device lock function + * 15:9 reserved + * 8 security level 1:max 0:high + * 7:6 reserved + * 5 enhanced erase + * 4 expire + * 3 frozen + * 2 locked + * 1 en/disabled + * 0 capability + */ + unsigned short csfo; /* current set features options + * 15:4 reserved + * 3 auto reassign + * 2 reverting + * 1 read-look-ahead + * 0 write cache + */ + unsigned short words130_155[26];/* reserved vendor words 130-155 */ + unsigned short word156; + unsigned short words157_159[3];/* reserved vendor words 157-159 */ + unsigned short words160_255[95];/* reserved words 160-255 */ +} hd_driveid_t; + + +/* + * PIO Mode Configuration + * + * See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21 + */ + +typedef struct { + unsigned int t_setup; /* Setup Time in [ns] or clocks */ + unsigned int t_length; /* Length Time in [ns] or clocks */ + unsigned int t_hold; /* Hold Time in [ns] or clocks */ +} +pio_config_t; + +#define IDE_MAX_PIO_MODE 4 /* max suppurted PIO mode */ + +/* ------------------------------------------------------------------------- */ + +#endif /* _ATA_H */ diff --git a/include/bcm5221.h b/include/bcm5221.h new file mode 100644 index 0000000..6fb94aa --- /dev/null +++ b/include/bcm5221.h @@ -0,0 +1,104 @@ +/* + * Broadcom BCM5221 Ethernet PHY + * + * (C) Copyright 2005 REA Elektronik GmbH + * Anders Larsen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define BCM5221_BMCR 0 /* Basic Mode Control Register */ +#define BCM5221_BMSR 1 /* Basic Mode Status Register */ +#define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */ +#define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */ +#define BCM5221_ANAR 4 /* Auto-negotiation Advertisement Register */ +#define BCM5221_ANLPAR 5 /* Auto-negotiation Link Partner Ability Register */ +#define BCM5221_ANER 6 /* Auto-negotiation Expansion Register */ +#define BCM5221_ACSR 24 /* Auxiliary Control/Status Register */ +#define BCM5221_INTR 26 /* Interrupt Register */ + +/* --Bit definitions: BCM5221_BMCR */ +#define BCM5221_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */ +#define BCM5221_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */ +#define BCM5221_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */ +#define BCM5221_AUTONEG (1 << 12) +#define BCM5221_POWER_DOWN (1 << 11) +#define BCM5221_ISOLATE (1 << 10) +#define BCM5221_RESTART_AUTONEG (1 << 9) +#define BCM5221_DUPLEX_MODE (1 << 8) +#define BCM5221_COLLISION_TEST (1 << 7) + +/*--Bit definitions: BCM5221_BMSR */ +#define BCM5221_100BASE_T4 (1 << 15) +#define BCM5221_100BASE_TX_FD (1 << 14) +#define BCM5221_100BASE_TX_HD (1 << 13) +#define BCM5221_10BASE_T_FD (1 << 12) +#define BCM5221_10BASE_T_HD (1 << 11) +#define BCM5221_MF_PREAMB_SUPPR (1 << 6) +#define BCM5221_AUTONEG_COMP (1 << 5) +#define BCM5221_REMOTE_FAULT (1 << 4) +#define BCM5221_AUTONEG_ABILITY (1 << 3) +#define BCM5221_LINK_STATUS (1 << 2) +#define BCM5221_JABBER_DETECT (1 << 1) +#define BCM5221_EXTEND_CAPAB (1 << 0) + +/*--definitions: BCM5221_PHYID1 */ +#define BCM5221_PHYID1_OUI 0x1018 +#define BCM5221_LSB_MASK 0x3F + +/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */ +#define BCM5221_NP (1 << 15) +#define BCM5221_ACK (1 << 14) +#define BCM5221_RF (1 << 13) +#define BCM5221_FCS (1 << 10) +#define BCM5221_T4 (1 << 9) +#define BCM5221_TX_FDX (1 << 8) +#define BCM5221_TX_HDX (1 << 7) +#define BCM5221_10_FDX (1 << 6) +#define BCM5221_10_HDX (1 << 5) +#define BCM5221_AN_IEEE_802_3 0x0001 + +/*--Bit definitions: BCM5221_ANER */ +#define BCM5221_PDF (1 << 4) +#define BCM5221_LP_NP_ABLE (1 << 3) +#define BCM5221_NP_ABLE (1 << 2) +#define BCM5221_PAGE_RX (1 << 1) +#define BCM5221_LP_AN_ABLE (1 << 0) + +/*--Bit definitions: BCM5221_ACSR */ +#define BCM5221_100 (1 << 1) +#define BCM5221_FDX (1 << 0) + +/*--Bit definitions: BCM5221_INTR */ +#define BCM5221_FDX_LED (1 << 15) +#define BCM5221_INTR_ENABLE (1 << 14) +#define BCM5221_FDX_MASK (1 << 11) +#define BCM5221_SPD_MASK (1 << 10) +#define BCM5221_LINK_MASK (1 << 9) +#define BCM5221_INTR_MASK (1 << 8) +#define BCM5221_FDX_CHG (1 << 3) +#define BCM5221_SPD_CHG (1 << 2) +#define BCM5221_LINK_CHG (1 << 1) +#define BCM5221_INTR_STATUS (1 << 0) + +/****************** function prototypes **********************/ +unsigned int bcm5221_IsPhyConnected(AT91PS_EMAC p_mac); +unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac); +unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status); +unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac); diff --git a/include/bedbug/bedbug.h b/include/bedbug/bedbug.h new file mode 100644 index 0000000..471215e --- /dev/null +++ b/include/bedbug/bedbug.h @@ -0,0 +1,42 @@ +/* $Id$ */ + +#ifndef _BEDBUG_H +#define _BEDBUG_H + +#ifndef NULL +#define NULL 0 +#endif + +#define _USE_PROTOTYPES + +#ifndef isblank +#define isblank(c) isspace((int)(c)) +#endif + +#ifndef __P +#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus)) +#define __P(protos) protos /* full-blown ANSI C */ +#else +#define __P(protos) () /* traditional C preprocessor */ +#endif +#endif + +#define assert( condition ) if( (condition) ) _exit(0) + +#endif /* _BEDBUG_H */ + + +/* + * Copyright (c) 2001 William L. Pitts + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h new file mode 100644 index 0000000..9cc8f9f --- /dev/null +++ b/include/bedbug/ppc.h @@ -0,0 +1,413 @@ +/* $Id$ */ + +#ifndef _PPC_H +#define _PPC_H + +/*====================================================================== + * + * OPERANDS + * + *======================================================================*/ + +enum OP_FIELD { + O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD, + O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD, + O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr, + O_cr2 }; + +struct operand { + enum OP_FIELD field; /* The operand identifier from the + enum above */ + + char * name; /* Symbolic name of this operand */ + + unsigned int bits; /* The number of bits used by this + operand */ + + unsigned int shift; /* How far to the right the operand + should be shifted so that it is + aligned at the beginning of the + word */ + + unsigned int hint; /* A bitwise-inclusive-OR of the + values shown below. These are used + tell the disassembler how to print + this operand */ +}; + +/* Values for operand hint */ +#define OH_SILENT 0x01 /* dont print this operand */ +#define OH_ADDR 0x02 /* this operand is an address */ +#define OH_REG 0x04 /* this operand is a register */ +#define OH_SPR 0x08 /* this operand is an SPR */ +#define OH_TBR 0x10 /* this operand is a TBR */ +#define OH_OFFSET 0x20 /* this operand is an offset */ +#define OH_LITERAL 0x40 /* a literal string */ + + +/*====================================================================== + * + * OPCODES + * + *======================================================================*/ + +/* From the MPCxxx instruction set documentation, all instructions are + * 32 bits long and word aligned. Bits 0-5 always specify the primary + * opcode. Many instructions also have an extended opcode. + */ + +#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f) +#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26) + +/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the + * instruction forms + */ + + +/*------------------------------------------------- + * I-Form Instructions: + * bX + *------------------------------------------------- + * OPCD | LI |AA|LK + *-------------------------------------------------*/ + +#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1)) +#define I_MASK I_OPCODE(0x3f,0x1,0x1) + + +/*------------------------------------------------- + * B-Form Instructions: + * bcX + *------------------------------------------------- + * OPCD | BO | BI | BD |AA|LK + *-------------------------------------------------*/ + +#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1)) +#define B_MASK B_OPCODE(0x3f,0x1,0x1) + + +/*------------------------------------------------- + * SC-Form Instructions: + * sc + *------------------------------------------------- + * OPCD | 00000 | 00000 | 00000000000000 |1|0 + *-------------------------------------------------*/ + +#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2) +#define SC_MASK SC_OPCODE(0x3f) + + +/*------------------------------------------------- + * D-Form Instructions: + * addi addic addic. addis andi. andis. cmpi cmpli + * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli + * ori oris stb stbu sth sthu stmw stw stwu subfic + * twi xori xoris + *------------------------------------------------- + * OPCD | D | A | d + * OPCD | D | A | SIMM + * OPCD | S | A | d + * OPCD | S | A | UIMM + * OPCD |crfD|0|L| A | SIMM + * OPCD |crfD|0|L| A | UIMM + * OPCD | TO | A | SIMM + *-------------------------------------------------*/ + +#define D_OPCODE(i) MAKE_OPCODE(i) +#define D_MASK MAKE_OPCODE(0x3f) + + +/*------------------------------------------------- + * DS-Form Instructions: + * (none supported by MPC860) + *------------------------------------------------- + * OPCD | D | A | ds |XO + * OPCD | S | A | ds |XO + *-------------------------------------------------*/ + +#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3)) +#define DS_MASK DS_OPCODE(0x3f,0x1) + + +/*--------------------------------------------------- + * X-Form Instructions: + * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt + * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX + * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi + * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr + * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX + * orX orcX slwX srawX srawiX srwX stbux stbx + * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux + * stwx sync tlbie tlbld tlbli tlbsync tw xorX + *--------------------------------------------------- + * OPCD | D | A | B | XO |0 + * OPCD | D | A | NB | XO |0 + * OPCD | D | 00000 | B | XO |0 + * OPCD | D | 00000 | 00000 | XO |0 + * OPCD | D |0| SR | 00000 | XO |0 + * OPCD | S | A | B | XO |Rc + * OPCD | S | A | B | XO |1 + * OPCD | S | A | B | XO |0 + * OPCD | S | A | NB | XO |0 + * OPCD | S | A | 00000 | XO |Rc + * OPCD | S | 00000 | B | XO |0 + * OPCD | S | 00000 | 00000 | XO |0 + * OPCD | S |0| SR | 00000 | XO |0 + * OPCD | S | A | SH | XO |Rc + * OPCD |crfD|0|L| A | SH | XO |0 + * OPCD |crfD |00| A | B | XO |0 + * OPCD |crfD |00|crfS |00| 00000 | XO |0 + * OPCD |crfD |00| 00000 | 00000 | XO |0 + * OPCD |crfD |00| 00000 | IMM |0| XO |Rc + * OPCD | TO | A | B | XO |0 + * OPCD | D | 00000 | B | XO |Rc + * OPCD | D | 00000 | 00000 | XO |Rc + * OPCD | crbD | 00000 | 00000 | XO |Rc + * OPCD | 00000 | A | B | XO |0 + * OPCD | 00000 | 00000 | B | XO |0 + * OPCD | 00000 | 00000 | 00000 | XO |0 + *---------------------------------------------------*/ + +#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((rc) & 0x1)) +#define X_MASK X_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XL-Form Instructions: + * bcctrX bclrX crand crandc creqv crnand crnor cror + * croc crxorisync mcrf rfi + *--------------------------------------------------- + * OPCD | BO | BI | 00000 | XO |LK + * OPCD | crbD | crbA | crbB | XO |0 + * OPCD |crfD |00|crfS |00| 00000 | XO |0 + * OPCD | 00000 | 00000 | 00000 | XO |0 + *---------------------------------------------------*/ + +#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((lk) & 0x1)) +#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XFX-Form Instructions: + * mfspr mftb mtcrf mtspr + *--------------------------------------------------- + * OPCD | D | spr | XO |0 + * OPCD | D |0| CRM |0| XO |0 + * OPCD | S | spr | XO |0 + * OPCD | D | tbr | XO |0 + *---------------------------------------------------*/ + +#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((rc) & 0x1)) +#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XFL-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD |0| FM |0| B | XO |0 + *---------------------------------------------------*/ + +#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ + ((rc) & 0x1)) +#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1) + + +/*--------------------------------------------------- + * XS-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | S | A | sh | XO |sh|LK + *---------------------------------------------------*/ + +#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \ + ((rc) & 0x1)) +#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1) + + +/*--------------------------------------------------- + * XO-Form Instructions: + * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX + * mulhwuX mullwX negX subfX subfcX subfeX subfmeX + * subfzeX + *--------------------------------------------------- + * OPCD | D | A | B |OE| XO |Rc + * OPCD | D | A | B |0 | XO |Rc + * OPCD | D | A | 00000 |OE| XO |Rc + *---------------------------------------------------*/ + +#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \ + (((xo) & 0x1ff) << 1) | ((rc) & 0x1)) +#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1) + + +/*--------------------------------------------------- + * A-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | D | A | B |00000| XO |Rc + * OPCD | D | A | B | C | XO |Rc + * OPCD | D | A | 00000 | C | XO |Rc + * OPCD | D | 00000 | B |00000| XO |Rc + *---------------------------------------------------*/ + +#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \ + ((rc) & 0x1)) +#define A_MASK A_OPCODE(0x3f,0x1f,0x1) + + +/*--------------------------------------------------- + * M-Form Instructions: + * rlwimiX rlwinmX rlwnmX + *--------------------------------------------------- + * OPCD | S | A | SH | MB | ME |Rc + * OPCD | S | A | B | MB | ME |Rc + *---------------------------------------------------*/ + +#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1)) +#define M_MASK M_OPCODE(0x3f,0x1) + + +/*--------------------------------------------------- + * MD-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | S | A | sh | mb | XO |sh|Rc + * OPCD | S | A | sh | me | XO |sh|Rc + *---------------------------------------------------*/ + +#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \ + ((rc) & 0x1)) +#define MD_MASK MD_OPCODE(0x3f,0x7,0x1) + + +/*--------------------------------------------------- + * MDS-Form Instructions: + * (none supported by MPC860) + *--------------------------------------------------- + * OPCD | S | A | B | mb | XO |Rc + * OPCD | S | A | B | me | XO |Rc + *---------------------------------------------------*/ + +#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \ + ((rc) & 0x1)) +#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1) + +#ifndef FALSE +#define FALSE 0 +#define TRUE (!FALSE) +#endif + +#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr)) + +#define MAX_OPERANDS 8 + +struct ppc_ctx; + +struct opcode { + unsigned long opcode; /* The complete opcode as produced by + one of the XXX_OPCODE macros above */ + + unsigned long mask; /* The mask to use on an instruction + before comparing with the opcode + field to see if it matches */ + + enum OP_FIELD fields[MAX_OPERANDS]; + /* An array defining the operands for + this opcode. The values of the + array are the operand identifiers */ + + int (*hfunc)(struct ppc_ctx *); + /* Address of a function to handle the given + mnemonic */ + + char * name; /* The symbolic name of this opcode */ + + unsigned int hint; /* A bitwise-inclusive-OR of the + values shown below. These are used + tell the disassembler how to print + some operands for this opcode */ +}; + +/* values for opcode hints */ +#define H_RELATIVE 0x1 /* The address operand is relative */ +#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */ +#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */ + +struct ppc_ctx { + struct opcode * op; + unsigned long instr; + unsigned int flags; + int datalen; + char data[ 256 ]; + char radix_fmt[ 8 ]; + unsigned char * virtual; +}; + + +/*====================================================================== + * + * FUNCTIONS + * + *======================================================================*/ + +/* Values for flags as passed to various ppc routines */ +#define F_RADOCTAL 0x1 /* output radix = unsigned octal */ +#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */ +#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */ +#define F_RADHEX 0x8 /* output radix = unsigned hex */ +#define F_SIMPLE 0x10 /* use simplified mnemonics */ +#define F_SYMBOL 0x20 /* use symbol lookups for addresses */ +#define F_INSTR 0x40 /* output the raw instruction */ +#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory + rather than from the HMI */ +#define F_LINENO 0x100 /* show line number info if available */ +#define F_VALIDONLY 0x200 /* cache: valid entries only */ + +/* Values for assembler error codes */ +#define E_ASM_BAD_OPCODE 1 +#define E_ASM_NUM_OPERANDS 2 +#define E_ASM_BAD_REGISTER 3 +#define E_ASM_BAD_SPR 4 +#define E_ASM_BAD_TBR 5 + +extern int disppc __P((unsigned char *,unsigned char *,int, + int (*)(const char *), unsigned long)); +extern int print_source_line __P((char *,char *,int, + int (*pfunc)(const char *))); +extern int find_next_address __P((unsigned char *,int,struct pt_regs *)); +extern int handle_bc __P((struct ppc_ctx *)); +extern unsigned long asmppc __P((unsigned long,char*,int*)); +extern char *asm_error_str __P((int)); + +/*====================================================================== + * + * GLOBAL VARIABLES + * + *======================================================================*/ + +extern struct operand operands[]; +extern const unsigned int n_operands; +extern struct opcode opcodes[]; +extern const unsigned int n_opcodes; + +#endif /* _PPC_H */ + + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/include/bedbug/regs.h b/include/bedbug/regs.h new file mode 100644 index 0000000..938e435 --- /dev/null +++ b/include/bedbug/regs.h @@ -0,0 +1,403 @@ +/* $Id$ */ + +#ifndef _REGS_H +#define _REGS_H + +/* Special Purpose Registers */ + +#define SPR_CR -1 +#define SPR_MSR -2 + +#define SPR_XER 1 +#define SPR_LR 8 +#define SPR_CTR 9 +#define SPR_DSISR 18 +#define SPR_DAR 19 +#define SPR_DEC 22 +#define SPR_SRR0 26 +#define SPR_SRR1 27 +#define SPR_EIE 80 +#define SPR_EID 81 +#define SPR_CMPA 144 +#define SPR_CMPB 145 +#define SPR_CMPC 146 +#define SPR_CMPD 147 +#define SPR_ICR 148 +#define SPR_DER 149 +#define SPR_COUNTA 150 +#define SPR_COUNTB 151 +#define SPR_CMPE 152 +#define SPR_CMPF 153 +#define SPR_CMPG 154 +#define SPR_CMPH 155 +#define SPR_LCTRL1 156 +#define SPR_LCTRL2 157 +#define SPR_ICTRL 158 +#define SPR_BAR 159 +#define SPR_USPRG0 256 +#define SPR_SPRG4_RO 260 +#define SPR_SPRG5_RO 261 +#define SPR_SPRG6_RO 262 +#define SPR_SPRG7_RO 263 +#define SPR_SPRG0 272 +#define SPR_SPRG1 273 +#define SPR_SPRG2 274 +#define SPR_SPRG3 275 +#define SPR_SPRG4 276 +#define SPR_SPRG5 277 +#define SPR_SPRG6 278 +#define SPR_SPRG7 279 +#define SPR_EAR 282 /* MPC603e core */ +#define SPR_TBL 284 +#define SPR_TBU 285 +#define SPR_PVR 287 +#define SPR_IC_CST 560 +#define SPR_IC_ADR 561 +#define SPR_IC_DAT 562 +#define SPR_DC_CST 568 +#define SPR_DC_ADR 569 +#define SPR_DC_DAT 570 +#define SPR_DPDR 630 +#define SPR_IMMR 638 +#define SPR_MI_CTR 784 +#define SPR_MI_AP 786 +#define SPR_MI_EPN 787 +#define SPR_MI_TWC 789 +#define SPR_MI_RPN 790 +#define SPR_MD_CTR 792 +#define SPR_M_CASID 793 +#define SPR_MD_AP 794 +#define SPR_MD_EPN 795 +#define SPR_M_TWB 796 +#define SPR_MD_TWC 797 +#define SPR_MD_RPN 798 +#define SPR_M_TW 799 +#define SPR_MI_DBCAM 816 +#define SPR_MI_DBRAM0 817 +#define SPR_MI_DBRAM1 818 +#define SPR_MD_DBCAM 824 +#define SPR_MD_DBRAM0 825 +#define SPR_MD_DBRAM1 826 +#define SPR_ZPR 944 +#define SPR_PID 945 +#define SPR_CCR0 947 +#define SPR_IAC3 948 +#define SPR_IAC4 949 +#define SPR_DVC1 950 +#define SPR_DVC2 951 +#define SPR_SGR 953 +#define SPR_DCWR 954 +#define SPR_SLER 955 +#define SPR_SU0R 956 +#define SPR_DBCR1 957 +#define SPR_ICDBDR 979 +#define SPR_ESR 980 +#define SPR_DEAR 981 +#define SPR_EVPR 982 +#define SPR_TSR 984 +#define SPR_TCR 986 +#define SPR_PIT 987 +#define SPR_SRR2 990 +#define SPR_SRR3 991 +#define SPR_DBSR 1008 +#define SPR_DBCR0 1010 +#define SPR_IABR 1010 /* MPC603e core */ +#define SPR_IAC1 1012 +#define SPR_IAC2 1013 +#define SPR_DAC1 1014 +#define SPR_DAC2 1015 +#define SPR_DCCR 1018 +#define SPR_ICCR 1019 + +/* Bits for the DBCR0 register */ +#define DBCR0_EDM 0x80000000 +#define DBCR0_IDM 0x40000000 +#define DBCR0_RST 0x30000000 +#define DBCR0_IC 0x08000000 +#define DBCR0_BT 0x04000000 +#define DBCR0_EDE 0x02000000 +#define DBCR0_TDE 0x01000000 +#define DBCR0_IA1 0x00800000 +#define DBCR0_IA2 0x00400000 +#define DBCR0_IA12 0x00200000 +#define DBCR0_IA12X 0x00100000 +#define DBCR0_IA3 0x00080000 +#define DBCR0_IA4 0x00040000 +#define DBCR0_IA34 0x00020000 +#define DBCR0_IA34X 0x00010000 +#define DBCR0_IA12T 0x00008000 +#define DBCR0_IA34T 0x00004000 +#define DBCR0_FT 0x00000001 + +/* Bits for the DBCR1 register */ +#define DBCR1_D1R 0x80000000 +#define DBCR1_D2R 0x40000000 +#define DBCR1_D1W 0x20000000 +#define DBCR1_D2W 0x10000000 +#define DBCR1_D1S 0x0C000000 +#define DBCR1_D2S 0x03000000 +#define DBCR1_DA12 0x00800000 +#define DBCR1_DA12X 0x00400000 +#define DBCR1_DV1M 0x000C0000 +#define DBCR1_DV2M 0x00030000 +#define DBCR1_DV1BE 0x0000F000 +#define DBCR1_DV2BE 0x00000F00 + +/* Bits for the DBSR register */ +#define DBSR_IC 0x80000000 +#define DBSR_BT 0x40000000 +#define DBSR_EDE 0x20000000 +#define DBSR_TIE 0x10000000 +#define DBSR_UDE 0x08000000 +#define DBSR_IA1 0x04000000 +#define DBSR_IA2 0x02000000 +#define DBSR_DR1 0x01000000 +#define DBSR_DW1 0x00800000 +#define DBSR_DR2 0x00400000 +#define DBSR_DW2 0x00200000 +#define DBSR_IDE 0x00100000 +#define DBSR_IA3 0x00080000 +#define DBSR_IA4 0x00040000 +#define DBSR_MRR 0x00000300 + +struct spr_info { + int spr_val; + char spr_name[ 10 ]; +}; + +extern struct spr_info spr_map[]; +extern const unsigned int n_sprs; + + +#define SET_REGISTER( str, val ) \ +({ unsigned long __value = (val); \ + asm volatile( str : : "r" (__value)); \ + __value; }) + +#define GET_REGISTER( str ) \ +({ unsigned long __value; \ + asm volatile( str : "=r" (__value) : ); \ + __value; }) + +#define GET_CR() GET_REGISTER( "mfcr %0" ) +#define SET_CR(val) SET_REGISTER( "mtcr %0", val ) +#define GET_MSR() GET_REGISTER( "mfmsr %0" ) +#define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) +#define GET_XER() GET_REGISTER( "mfspr %0,1" ) +#define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) +#define GET_LR() GET_REGISTER( "mfspr %0,8" ) +#define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) +#define GET_CTR() GET_REGISTER( "mfspr %0,9" ) +#define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) +#define GET_DSISR() GET_REGISTER( "mfspr %0,18" ) +#define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) +#define GET_DAR() GET_REGISTER( "mfspr %0,19" ) +#define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) +#define GET_DEC() GET_REGISTER( "mfspr %0,22" ) +#define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) +#define GET_SRR0() GET_REGISTER( "mfspr %0,26" ) +#define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val ) +#define GET_SRR1() GET_REGISTER( "mfspr %0,27" ) +#define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val ) +#define GET_EIE() GET_REGISTER( "mfspr %0,80" ) +#define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val ) +#define GET_EID() GET_REGISTER( "mfspr %0,81" ) +#define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val ) +#define GET_CMPA() GET_REGISTER( "mfspr %0,144" ) +#define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val ) +#define GET_CMPB() GET_REGISTER( "mfspr %0,145" ) +#define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val ) +#define GET_CMPC() GET_REGISTER( "mfspr %0,146" ) +#define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val ) +#define GET_CMPD() GET_REGISTER( "mfspr %0,147" ) +#define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val ) +#define GET_ICR() GET_REGISTER( "mfspr %0,148" ) +#define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val ) +#define GET_DER() GET_REGISTER( "mfspr %0,149" ) +#define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val ) +#define GET_COUNTA() GET_REGISTER( "mfspr %0,150" ) +#define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val ) +#define GET_COUNTB() GET_REGISTER( "mfspr %0,151" ) +#define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val ) +#define GET_CMPE() GET_REGISTER( "mfspr %0,152" ) +#define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val ) +#define GET_CMPF() GET_REGISTER( "mfspr %0,153" ) +#define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val ) +#define GET_CMPG() GET_REGISTER( "mfspr %0,154" ) +#define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val ) +#define GET_CMPH() GET_REGISTER( "mfspr %0,155" ) +#define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val ) +#define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" ) +#define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val ) +#define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" ) +#define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val ) +#define GET_ICTRL() GET_REGISTER( "mfspr %0,158" ) +#define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val ) +#define GET_BAR() GET_REGISTER( "mfspr %0,159" ) +#define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val ) +#define GET_USPRG0() GET_REGISTER( "mfspr %0,256" ) +#define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val ) +#define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" ) +#define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val ) +#define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" ) +#define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val ) +#define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" ) +#define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val ) +#define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" ) +#define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val ) +#define GET_SPRG0() GET_REGISTER( "mfspr %0,272" ) +#define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val ) +#define GET_SPRG1() GET_REGISTER( "mfspr %0,273" ) +#define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val ) +#define GET_SPRG2() GET_REGISTER( "mfspr %0,274" ) +#define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val ) +#define GET_SPRG3() GET_REGISTER( "mfspr %0,275" ) +#define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val ) +#define GET_SPRG4() GET_REGISTER( "mfspr %0,276" ) +#define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val ) +#define GET_SPRG5() GET_REGISTER( "mfspr %0,277" ) +#define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val ) +#define GET_SPRG6() GET_REGISTER( "mfspr %0,278" ) +#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val ) +#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" ) +#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val ) +#define GET_EAR() GET_REGISTER( "mfspr %0,282" ) +#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val ) +#define GET_TBL() GET_REGISTER( "mfspr %0,284" ) +#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val ) +#define GET_TBU() GET_REGISTER( "mfspr %0,285" ) +#define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val ) +#define GET_PVR() GET_REGISTER( "mfspr %0,287" ) +#define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val ) +#define GET_IC_CST() GET_REGISTER( "mfspr %0,560" ) +#define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val ) +#define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" ) +#define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val ) +#define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" ) +#define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val ) +#define GET_DC_CST() GET_REGISTER( "mfspr %0,568" ) +#define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val ) +#define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" ) +#define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val ) +#define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" ) +#define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val ) +#define GET_DPDR() GET_REGISTER( "mfspr %0,630" ) +#define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val ) +#define GET_IMMR() GET_REGISTER( "mfspr %0,638" ) +#define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val ) +#define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" ) +#define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val ) +#define GET_MI_AP() GET_REGISTER( "mfspr %0,786" ) +#define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val ) +#define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" ) +#define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val ) +#define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" ) +#define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val ) +#define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" ) +#define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val ) +#define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" ) +#define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val ) +#define GET_M_CASID() GET_REGISTER( "mfspr %0,793" ) +#define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val ) +#define GET_MD_AP() GET_REGISTER( "mfspr %0,794" ) +#define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val ) +#define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" ) +#define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val ) +#define GET_M_TWB() GET_REGISTER( "mfspr %0,796" ) +#define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val ) +#define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" ) +#define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val ) +#define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" ) +#define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val ) +#define GET_M_TW() GET_REGISTER( "mfspr %0,799" ) +#define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val ) +#define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" ) +#define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val ) +#define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" ) +#define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val ) +#define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" ) +#define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val ) +#define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" ) +#define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val ) +#define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" ) +#define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val ) +#define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" ) +#define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val ) +#define GET_ZPR() GET_REGISTER( "mfspr %0,944" ) +#define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val ) +#define GET_PID() GET_REGISTER( "mfspr %0,945" ) +#define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val ) +#define GET_CCR0() GET_REGISTER( "mfspr %0,947" ) +#define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val ) +#define GET_IAC3() GET_REGISTER( "mfspr %0,948" ) +#define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val ) +#define GET_IAC4() GET_REGISTER( "mfspr %0,949" ) +#define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val ) +#define GET_DVC1() GET_REGISTER( "mfspr %0,950" ) +#define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val ) +#define GET_DVC2() GET_REGISTER( "mfspr %0,951" ) +#define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val ) +#define GET_SGR() GET_REGISTER( "mfspr %0,953" ) +#define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val ) +#define GET_DCWR() GET_REGISTER( "mfspr %0,954" ) +#define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val ) +#define GET_SLER() GET_REGISTER( "mfspr %0,955" ) +#define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val ) +#define GET_SU0R() GET_REGISTER( "mfspr %0,956" ) +#define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val ) +#define GET_DBCR1() GET_REGISTER( "mfspr %0,957" ) +#define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val ) +#define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" ) +#define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val ) +#define GET_ESR() GET_REGISTER( "mfspr %0,980" ) +#define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val ) +#define GET_DEAR() GET_REGISTER( "mfspr %0,981" ) +#define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val ) +#define GET_EVPR() GET_REGISTER( "mfspr %0,982" ) +#define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val ) +#define GET_TSR() GET_REGISTER( "mfspr %0,984" ) +#define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val ) +#define GET_TCR() GET_REGISTER( "mfspr %0,986" ) +#define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val ) +#define GET_PIT() GET_REGISTER( "mfspr %0,987" ) +#define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val ) +#define GET_SRR2() GET_REGISTER( "mfspr %0,990" ) +#define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val ) +#define GET_SRR3() GET_REGISTER( "mfspr %0,991" ) +#define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val ) +#define GET_DBSR() GET_REGISTER( "mfspr %0,1008" ) +#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val ) +#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" ) +#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val ) +#define GET_IABR() GET_REGISTER( "mfspr %0,1010" ) +#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val ) +#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" ) +#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val ) +#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" ) +#define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val ) +#define GET_DAC1() GET_REGISTER( "mfspr %0,1014" ) +#define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val ) +#define GET_DAC2() GET_REGISTER( "mfspr %0,1015" ) +#define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val ) +#define GET_DCCR() GET_REGISTER( "mfspr %0,1018" ) +#define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val ) +#define GET_ICCR() GET_REGISTER( "mfspr %0,1019" ) +#define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val ) + +#endif /* _REGS_H */ + + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h new file mode 100644 index 0000000..66cf8ea --- /dev/null +++ b/include/bedbug/tables.h @@ -0,0 +1,601 @@ +/* $Id$ */ + +#ifndef TABLES_H +#define TABLES_H + +/* This is only included by common/bedbug.c, and depends on the following + * files to already be included + * common.h + * bedbug/bedbug.h + * bedbug/ppc.h + * bedbug/regs.h + */ + +struct operand operands[] = { + /*Field Name Bits Shift Hint Position */ + /*----- ------ ----- ----- ---- ------------ */ + { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */ + { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */ + { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */ + { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */ + { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */ + { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */ + { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */ + { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */ + { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */ + { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */ + { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */ + { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */ + { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */ + { O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */ + { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */ + { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */ + { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */ + { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */ + { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */ + { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */ + { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */ + { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */ + { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */ + { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */ + { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */ + { O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */ + { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */ + { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */ + { O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */ + { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */ + { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */ + { O_L, "O_L", 1, 21, 0 }, /* 10 */ + { O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */ + { O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */ + { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */ +}; + +const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]); + +/* A note about the fields array in the opcodes structure: + The operands are listed in the order they appear in the output. + + This table is arranged in numeric order of the opcode. Note that some + opcodes have defined bits in odd places so not all forms of a command + will be in the same place. This is done so that a binary search can be + done to find the opcodes. Note that table D.2 in the MPC860 User's + Manual "Instructions Sorted by Opcode" does not account for these + bit locations */ + +struct opcode opcodes[] = { + { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0}, + 0, "twi", 0 }, + { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "mulli", 0 }, + { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "subfic", 0 }, + { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0}, + 0, "cmpli", 0 }, + { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0}, + 0, "cmpi", 0 }, + { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic", 0 }, + { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic.", 0 }, + { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addi", H_RA0_IS_0 }, + { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addis", H_RA0_IS_0|H_IMM_HIGH }, + { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + handle_bc, "bc", H_RELATIVE }, + { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcl", H_RELATIVE }, + { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bca", 0 }, + { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcla", 0 }, + { SC_OPCODE(17), SC_MASK, {0}, + 0, "sc", 0 }, + { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "b", H_RELATIVE }, + { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bl", H_RELATIVE }, + { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "ba", 0 }, + { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bla", 0 }, + { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS}, + 0, "mcrf", 0 }, + { XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bclr", 0 }, + { XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bclrl", 0 }, + { XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crnor", 0 }, + { XL_OPCODE(19,50,0), XL_MASK, {0}, + 0, "rfi", 0 }, + { XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crandc", 0 }, + { XL_OPCODE(19,150,0), XL_MASK, {0}, + 0, "isync", 0 }, + { XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crxor", 0 }, + { XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crnand", 0 }, + { XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crand", 0 }, + { XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "creqv", 0 }, + { XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "crorc", 0 }, + { XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, + 0, "cror", 0 }, + { XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bcctr", 0 }, + { XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, + 0, "bcctrl", 0 }, + { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi", 0 }, + { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi.", 0 }, + { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm", 0 }, + { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm.", 0 }, + { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm", 0 }, + { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm.", 0 }, + { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "ori", 0 }, + { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "oris", H_IMM_HIGH }, + { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xori", 0 }, + { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xoris", H_IMM_HIGH }, + { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andi.", 0 }, + { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andis.", H_IMM_HIGH }, + { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmp", 0 }, + { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0}, + 0, "tw", 0 }, + { XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfc", 0 }, + { XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfc.", 0 }, + { XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addc", 0 }, + { XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addc.", 0 }, + { XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhwu", 0 }, + { XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhwu.", 0 }, + { X_OPCODE(31,19,0), X_MASK, {O_rD, 0}, + 0, "mfcr", 0 }, + { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwarx", H_RA0_IS_0 }, + { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzx", H_RA0_IS_0 }, + { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw", 0 }, + { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw.", 0 }, + { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 }, + 0, "cntlzw", 0 }, + { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "cntlzw.", 0 }, + { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and", 0 }, + { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and.", 0 }, + { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmpl", 0 }, + { XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subf", 0 }, + { XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subf.", 0 }, + { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbst", H_RA0_IS_0 }, + { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzux", 0 }, + { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc", 0 }, + { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc.", 0 }, + { XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhw", 0 }, + { XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, + 0, "mulhw.", 0 }, + { X_OPCODE(31,83,0), X_MASK, {O_rD, 0}, + 0, "mfmsr", 0 }, + { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbf", H_RA0_IS_0 }, + { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lbzx", H_RA0_IS_0 }, + { XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "neg", 0 }, + { XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "neg.", 0 }, + { X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lbzux", 0 }, + { X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "nor", 0 }, + { X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "nor.", 0 }, + { XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfe", 0 }, + { XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfe.", 0 }, + { XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "adde", 0 }, + { XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "adde.", 0 }, + { XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0}, + 0, "mtcrf", 0 }, + { X_OPCODE(31,146,0), X_MASK, {O_rS, 0}, + 0, "mtmsr", 0 }, + { X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwcx.", 0 }, + { X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwx", 0 }, + { X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwux", 0 }, + { XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfze", 0 }, + { XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfze.", 0 }, + { XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addze", 0 }, + { XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addze.", 0 }, + { X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0}, + 0, "mtsr", 0 }, + { X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stbx", H_RA0_IS_0 }, + { XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfme", 0 }, + { XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfme.", 0 }, + { XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addme", 0 }, + { XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addme.", 0 }, + { XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullw", 0 }, + { XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullw.", 0 }, + { X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0}, + 0, "mtsrin", 0 }, + { X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbtst", H_RA0_IS_0 }, + { X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stbux", 0 }, + { XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "add", 0 }, + { XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "add.", 0 }, + { X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbt", H_RA0_IS_0 }, + { X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhzx", H_RA0_IS_0 }, + { X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "eqv", 0 }, + { X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "eqv.", 0 }, + { X_OPCODE(31,306,0), X_MASK, {O_rB, 0}, + 0, "tlbie", 0 }, + { X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "eciwx", H_RA0_IS_0 }, + { X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhzux", 0 }, + { X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "xor", 0 }, + { X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "xor.", 0 }, + { XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0}, + 0, "mfspr", 0 }, + { X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhax", H_RA0_IS_0 }, + { X_OPCODE(31,370,0), X_MASK, {0}, + 0, "tlbia", 0 }, + { XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0}, + 0, "mftb", 0 }, + { X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhaux", 0 }, + { X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "sthx", H_RA0_IS_0 }, + { X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "orc", 0 }, + { X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "orc.", 0 }, + { X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "ecowx", H_RA0_IS_0 }, + { X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "sthux", 0 }, + { X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "or", 0 }, + { X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "or.", 0 }, + { XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwu", 0 }, + { XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwu.", 0 }, + { XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0}, + 0, "mtspr", 0 }, + { X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbi", H_RA0_IS_0 }, + { X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "nand", 0 }, + { X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0}, + 0, "nand.", 0 }, + { XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divw", 0 }, + { XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divw.", 0 }, + { X_OPCODE(31,512,0), X_MASK, {O_crfD, 0}, + 0, "mcrxr", 0 }, + { XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfco", 0 }, + { XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfco.", 0 }, + { XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addco", 0 }, + { XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addco.", 0 }, + { X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lswx", H_RA0_IS_0 }, + { X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwbrx", H_RA0_IS_0 }, + { X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "srw", 0 }, + { X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "srw.", 0 }, + { XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfo", 0 }, + { XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfo.", 0 }, + { X_OPCODE(31,566,0), X_MASK, {0}, + 0, "tlbsync", 0 }, + { X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0}, + 0, "mfsr", 0 }, + { X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0}, + 0, "lswi", H_RA0_IS_0 }, + { X_OPCODE(31,598,0), X_MASK, {0}, + 0, "sync", 0 }, + { XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "nego", 0 }, + { XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "nego.", 0 }, + { XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfeo", 0 }, + { XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "subfeo.", 0 }, + { XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addeo", 0 }, + { XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addeo.", 0 }, + { X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0}, + 0, "mfsrin", 0 }, + { X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stswx", H_RA0_IS_0 }, + { X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "stwbrx", H_RA0_IS_0 }, + { XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfzeo", 0 }, + { XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfzeo.", 0 }, + { XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addzeo", 0 }, + { XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addzeo.", 0 }, + { X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0}, + 0, "stswi", H_RA0_IS_0 }, + { XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfmeo", 0 }, + { XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "subfmeo.", 0 }, + { XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addmeo", 0 }, + { XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, + 0, "addmeo.", 0 }, + { XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullwo", 0 }, + { XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "mullwo.", 0 }, + { XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addo", 0 }, + { XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "addo.", 0 }, + { X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lhbrx", H_RA0_IS_0 }, + { X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "sraw", 0 }, + { X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "sraw.", 0 }, + { X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, + 0, "srawi", 0 }, + { X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, + 0, "srawi.", 0 }, + { X_OPCODE(31,854,0), X_MASK, {0}, + 0, "eieio", 0 }, + { X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0}, + 0, "sthbrx", H_RA0_IS_0 }, + { X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsh", 0 }, + { X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsh.", 0 }, + { X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsb", 0 }, + { X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "extsb.", 0 }, + { XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwuo", 0 }, + { XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwuo.", 0 }, + { X_OPCODE(31,978,0), X_MASK, {O_rB, 0}, + 0, "tlbld", 0 }, + { X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0}, + 0, "icbi", H_RA0_IS_0 }, + { XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwo", 0 }, + { XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, + 0, "divwo.", 0 }, + { X_OPCODE(31,1010,0), X_MASK, {O_rB, 0}, + 0, "tlbli", 0 }, + { X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbz", H_RA0_IS_0 }, + { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwz", H_RA0_IS_0 }, + { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwzu", 0 }, + { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbz", H_RA0_IS_0 }, + { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbzu", 0 }, + { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stw", H_RA0_IS_0 }, + { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stwu", 0 }, + { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stb", H_RA0_IS_0 }, + { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stbu", 0 }, + { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhz", H_RA0_IS_0 }, + { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhzu", 0 }, + { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lha", H_RA0_IS_0 }, + { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhau", 0 }, + { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sth", H_RA0_IS_0 }, + { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sthu", 0 }, + { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lmw", H_RA0_IS_0 }, + { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stmw", H_RA0_IS_0 }, +}; + +const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]); + +struct spr_info spr_map[] = { + { SPR_XER, "XER" }, + { SPR_LR, "LR" }, + { SPR_CTR, "CTR" }, + { SPR_DSISR, "DSISR" }, + { SPR_DAR, "DAR" }, + { SPR_DEC, "DEC" }, + { SPR_SRR0, "SRR0" }, + { SPR_SRR1, "SRR1" }, + { SPR_EIE, "EIE" }, + { SPR_EID, "EID" }, + { SPR_CMPA, "CMPA" }, + { SPR_CMPB, "CMPB" }, + { SPR_CMPC, "CMPC" }, + { SPR_CMPD, "CMPD" }, + { SPR_ICR, "ICR" }, + { SPR_DER, "DER" }, + { SPR_COUNTA, "COUNTA" }, + { SPR_COUNTB, "COUNTB" }, + { SPR_CMPE, "CMPE" }, + { SPR_CMPF, "CMPF" }, + { SPR_CMPG, "CMPG" }, + { SPR_CMPH, "CMPH" }, + { SPR_LCTRL1, "LCTRL1" }, + { SPR_LCTRL2, "LCTRL2" }, + { SPR_ICTRL, "ICTRL" }, + { SPR_BAR, "BAR" }, + { SPR_USPRG0, "USPRG0" }, + { SPR_SPRG4_RO, "SPRG4_RO" }, + { SPR_SPRG5_RO, "SPRG5_RO" }, + { SPR_SPRG6_RO, "SPRG6_RO" }, + { SPR_SPRG7_RO, "SPRG7_RO" }, + { SPR_SPRG0, "SPRG0" }, + { SPR_SPRG1, "SPRG1" }, + { SPR_SPRG2, "SPRG2" }, + { SPR_SPRG3, "SPRG3" }, + { SPR_SPRG4, "SPRG4" }, + { SPR_SPRG5, "SPRG5" }, + { SPR_SPRG6, "SPRG6" }, + { SPR_SPRG7, "SPRG7" }, + { SPR_EAR, "EAR" }, + { SPR_TBL, "TBL" }, + { SPR_TBU, "TBU" }, + { SPR_IC_CST, "IC_CST" }, + { SPR_IC_ADR, "IC_ADR" }, + { SPR_IC_DAT, "IC_DAT" }, + { SPR_DC_CST, "DC_CST" }, + { SPR_DC_ADR, "DC_ADR" }, + { SPR_DC_DAT, "DC_DAT" }, + { SPR_DPDR, "DPDR" }, + { SPR_IMMR, "IMMR" }, + { SPR_MI_CTR, "MI_CTR" }, + { SPR_MI_AP, "MI_AP" }, + { SPR_MI_EPN, "MI_EPN" }, + { SPR_MI_TWC, "MI_TWC" }, + { SPR_MI_RPN, "MI_RPN" }, + { SPR_MD_CTR, "MD_CTR" }, + { SPR_M_CASID, "M_CASID" }, + { SPR_MD_AP, "MD_AP" }, + { SPR_MD_EPN, "MD_EPN" }, + { SPR_M_TWB, "M_TWB" }, + { SPR_MD_TWC, "MD_TWC" }, + { SPR_MD_RPN, "MD_RPN" }, + { SPR_M_TW, "M_TW" }, + { SPR_MI_DBCAM, "MI_DBCAM" }, + { SPR_MI_DBRAM0, "MI_DBRAM0" }, + { SPR_MI_DBRAM1, "MI_DBRAM1" }, + { SPR_MD_DBCAM, "MD_DBCAM" }, + { SPR_MD_DBRAM0, "MD_DBRAM0" }, + { SPR_MD_DBRAM1, "MD_DBRAM1" }, + { SPR_ZPR, "ZPR" }, + { SPR_PID, "PID" }, + { SPR_CCR0, "CCR0" }, + { SPR_IAC3, "IAC3" }, + { SPR_IAC4, "IAC4" }, + { SPR_DVC1, "DVC1" }, + { SPR_DVC2, "DVC2" }, + { SPR_SGR, "SGR" }, + { SPR_DCWR, "DCWR" }, + { SPR_SLER, "SLER" }, + { SPR_SU0R, "SU0R" }, + { SPR_DBCR1, "DBCR1" }, + { SPR_ICDBDR, "ICDBDR" }, + { SPR_ESR, "ESR" }, + { SPR_DEAR, "DEAR" }, + { SPR_EVPR, "EVPR" }, + { SPR_TSR, "TSR" }, + { SPR_TCR, "TCR" }, + { SPR_PIT, "PIT" }, + { SPR_SRR2, "SRR2" }, + { SPR_SRR3, "SRR3" }, + { SPR_DBSR, "DBSR" }, + { SPR_DBCR0, "DBCR0" }, + { SPR_IAC1, "IAC1" }, + { SPR_IAC2, "IAC2" }, + { SPR_DAC1, "DAC1" }, + { SPR_DAC2, "DAC2" }, + { SPR_DCCR, "DCCR" }, + { SPR_ICCR, "ICCR" }, +}; + +const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]); + +#endif + +/* + * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks + * All rights reserved. + * + * Redistribution and use in source and binary forms are freely + * permitted provided that the above copyright notice and this + * paragraph and the following disclaimer are duplicated in all + * such forms. + * + * This software is provided "AS IS" and without any express or + * implied warranties, including, without limitation, the implied + * warranties of merchantability and fitness for a particular + * purpose. + */ diff --git a/include/bedbug/type.h b/include/bedbug/type.h new file mode 100644 index 0000000..38ee9de --- /dev/null +++ b/include/bedbug/type.h @@ -0,0 +1,26 @@ +#ifndef _TYPE_BEDBUG_H +#define _TYPE_BEDBUG_H + +/* Supporting routines */ +int bedbug_puts (const char *); +void bedbug_init (void); +void bedbug860_init (void); +void do_bedbug_breakpoint (struct pt_regs *); +void bedbug_main_loop (unsigned long, struct pt_regs *); + + +typedef struct { + int hw_debug_enabled; + int stopped; + int current_bp; + struct pt_regs *regs; + + void (*do_break) (cmd_tbl_t *, int, int, char *[]); + void (*break_isr) (struct pt_regs *); + int (*find_empty) (void); + int (*set) (int, unsigned long); + int (*clear) (int); +} CPU_DEBUG_CTX; + + +#endif /* _TYPE_BEDBUG_H */ diff --git a/include/bmp_layout.h b/include/bmp_layout.h new file mode 100644 index 0000000..d823de9 --- /dev/null +++ b/include/bmp_layout.h @@ -0,0 +1,77 @@ +/* (C) Copyright 2002 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************/ +/* ** Layout of a bmp file */ +/************************************************************************/ + +#ifndef _BMP_H_ +#define _BMP_H_ + +typedef struct bmp_color_table_entry { + __u8 blue; + __u8 green; + __u8 red; + __u8 reserved; +} __attribute__ ((packed)) bmp_color_table_entry_t; + +/* When accessing these fields, remember that they are stored in little + endian format, so use linux macros, e.g. le32_to_cpu(width) */ + +typedef struct bmp_header { + /* Header */ + char signature[2]; + __u32 file_size; + __u32 reserved; + __u32 data_offset; + /* InfoHeader */ + __u32 size; + __u32 width; + __u32 height; + __u16 planes; + __u16 bit_count; + __u32 compression; + __u32 image_size; + __u32 x_pixels_per_m; + __u32 y_pixels_per_m; + __u32 colors_used; + __u32 colors_important; + /* ColorTable */ + +} __attribute__ ((packed)) bmp_header_t; + +typedef struct bmp_image { + bmp_header_t header; + /* We use a zero sized array just as a placeholder for variable + sized array */ + bmp_color_table_entry_t color_table[0]; +} bmp_image_t; + +/* Data in the bmp_image is aligned to this length */ +#define BMP_DATA_ALIGN 4 + +/* Constants for the compression field */ +#define BMP_BI_RGB 0 +#define BMP_BI_RLE8 1 +#define BMP_BI_RLE4 2 + +#endif /* _BMP_H_ */ diff --git a/include/bmp_logo.h b/include/bmp_logo.h new file mode 100644 index 0000000..9c924b8 --- /dev/null +++ b/include/bmp_logo.h @@ -0,0 +1,1948 @@ +/* + * Automatically generated by "tools/bmp_logo" + * + * DO NOT EDIT + * + */ + + +#ifndef __BMP_LOGO_H__ +#define __BMP_LOGO_H__ + +#define BMP_LOGO_WIDTH 160 +#define BMP_LOGO_HEIGHT 96 +#define BMP_LOGO_COLORS 31 +#define BMP_LOGO_OFFSET 16 + +unsigned short bmp_logo_palette[] = { + 0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999, + 0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3, + 0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA, + 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, +}; + +unsigned char bmp_logo_bitmap[] = { + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, + 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1B, 0x11, 0x10, 0x10, 0x10, 0x10, + 0x14, 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x1B, 0x14, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1B, 0x14, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x14, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x22, 0x2A, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x29, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x14, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x18, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x18, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x12, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x19, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x18, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2D, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x28, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x1C, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x19, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x12, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1B, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x18, + 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x18, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x16, 0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x19, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2B, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2D, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x28, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x20, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x22, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x22, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x14, 0x17, 0x15, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x17, 0x1B, 0x2E, 0x1A, 0x14, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x17, 0x1B, 0x2E, 0x1B, + 0x14, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1B, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2D, 0x29, + 0x23, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x23, 0x2A, + 0x2E, 0x2E, 0x2E, 0x2E, 0x14, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x14, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x1B, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x15, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x12, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x19, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2B, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x24, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x12, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x14, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x1B, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x1E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1C, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x16, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x11, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x11, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1E, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x1A, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2B, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x28, 0x2E, 0x2A, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x29, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x1E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x11, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x21, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x12, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x14, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x1B, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2A, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x14, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x1B, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x1B, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x23, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x20, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x22, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x18, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x23, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x23, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2A, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x21, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2D, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x1E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x12, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x1D, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x18, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x22, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x20, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x16, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2D, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1D, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x1C, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x1C, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x1E, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x16, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x21, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x24, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x14, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x18, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x15, 0x2E, 0x2E, 0x2E, 0x19, + 0x12, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x1E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x1B, 0x2E, 0x2E, 0x1B, 0x16, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2D, 0x26, + 0x22, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x22, 0x27, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x13, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2D, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2D, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x12, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2A, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x20, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x13, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x2C, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2D, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x11, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1C, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x11, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x12, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x2A, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2B, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x13, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1B, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1D, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x12, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x20, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x15, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2D, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x29, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x17, 0x14, 0x10, 0x11, 0x14, + 0x1A, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1B, 0x17, 0x17, 0x1A, 0x1B, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2B, 0x26, + 0x2A, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x26, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x17, 0x1B, 0x1B, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x16, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, + 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x12, 0x10, 0x10, 0x14, 0x14, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, + 0x10, 0x10, 0x14, 0x14, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x12, 0x10, 0x1B, 0x2E, 0x2E, 0x2E, 0x2E, + 0x17, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x13, 0x14, 0x13, 0x10, 0x10, 0x1C, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x2E, + 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x18, 0x10, 0x10, 0x17, 0x14, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, + 0x16, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x11, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x19, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x10, + 0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x12, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x10, 0x10, 0x19, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x15, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1B, 0x10, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x15, 0x10, 0x10, 0x10, + 0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x1B, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x14, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x10, + 0x19, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x10, + 0x1B, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1E, + 0x10, 0x10, 0x10, 0x17, 0x17, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x1B, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x1E, 0x12, 0x10, + 0x2E, 0x2E, 0x2E, 0x18, 0x10, 0x2E, 0x17, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, + 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x1B, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x15, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x17, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x14, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x1B, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x14, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x17, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x13, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x17, + 0x10, 0x10, 0x10, 0x18, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x1B, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10, 0x19, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x17, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x13, 0x10, 0x1A, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x1E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x19, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1C, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x16, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x15, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x17, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x1E, 0x10, 0x12, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x12, + 0x11, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x1C, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x10, 0x1C, + 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x16, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x1A, 0x2E, + 0x2E, 0x1D, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1E, 0x10, 0x19, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1A, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x13, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x13, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x17, 0x10, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x11, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x14, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x18, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x1D, 0x10, 0x15, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x14, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x19, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, + 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10, + 0x14, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x1A, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x1C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x13, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x13, 0x10, 0x10, 0x10, 0x10, 0x10, 0x16, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x13, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x1E, 0x10, 0x16, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10, 0x19, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x11, 0x10, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x11, 0x14, + 0x10, 0x10, 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, + 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10, + 0x10, 0x14, 0x13, 0x10, 0x10, 0x10, 0x2E, 0x2E, + +}; + +#endif /* __BMP_LOGO_H__ */ diff --git a/include/bzlib.h b/include/bzlib.h new file mode 100644 index 0000000..2d864d5 --- /dev/null +++ b/include/bzlib.h @@ -0,0 +1,329 @@ +/* + * This file is a modified version of bzlib.h from the bzip2-1.0.2 + * distribution which can be found at http://sources.redhat.com/bzip2/ + */ + +/*-------------------------------------------------------------*/ +/*--- Public header file for the library. ---*/ +/*--- bzlib.h ---*/ +/*-------------------------------------------------------------*/ + +/*-- + This file is a part of bzip2 and/or libbzip2, a program and + library for lossless, block-sorting data compression. + + Copyright (C) 1996-2002 Julian R Seward. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. The origin of this software must not be misrepresented; you must + not claim that you wrote the original software. If you use this + software in a product, an acknowledgment in the product + documentation would be appreciated but is not required. + + 3. Altered source versions must be plainly marked as such, and must + not be misrepresented as being the original software. + + 4. The name of the author may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Julian Seward, Cambridge, UK. + jseward@acm.org + bzip2/libbzip2 version 1.0 of 21 March 2000 + + This program is based on (at least) the work of: + Mike Burrows + David Wheeler + Peter Fenwick + Alistair Moffat + Radford Neal + Ian H. Witten + Robert Sedgewick + Jon L. Bentley + + For more information on these sources, see the manual. +--*/ + + +#ifndef _BZLIB_H +#define _BZLIB_H + +/* Configure for U-Boot environment */ +#define BZ_NO_STDIO +#define BZ_NO_COMPRESS +/* End of configuration for U-Boot environment */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BZ_RUN 0 +#define BZ_FLUSH 1 +#define BZ_FINISH 2 + +#define BZ_OK 0 +#define BZ_RUN_OK 1 +#define BZ_FLUSH_OK 2 +#define BZ_FINISH_OK 3 +#define BZ_STREAM_END 4 +#define BZ_SEQUENCE_ERROR (-1) +#define BZ_PARAM_ERROR (-2) +#define BZ_MEM_ERROR (-3) +#define BZ_DATA_ERROR (-4) +#define BZ_DATA_ERROR_MAGIC (-5) +#define BZ_IO_ERROR (-6) +#define BZ_UNEXPECTED_EOF (-7) +#define BZ_OUTBUFF_FULL (-8) +#define BZ_CONFIG_ERROR (-9) + +typedef + struct { + char *next_in; + unsigned int avail_in; + unsigned int total_in_lo32; + unsigned int total_in_hi32; + + char *next_out; + unsigned int avail_out; + unsigned int total_out_lo32; + unsigned int total_out_hi32; + + void *state; + + void *(*bzalloc)(void *,int,int); + void (*bzfree)(void *,void *); + void *opaque; + } + bz_stream; + + +#ifndef BZ_IMPORT +#define BZ_EXPORT +#endif + +#ifdef _WIN32 +# include +# ifdef small + /* windows.h define small to char */ +# undef small +# endif +# ifdef BZ_EXPORT +# define BZ_API(func) WINAPI func +# define BZ_EXTERN extern +# else + /* import windows dll dynamically */ +# define BZ_API(func) (WINAPI * func) +# define BZ_EXTERN +# endif +#else +# define BZ_API(func) func +# define BZ_EXTERN extern +#endif + + +/*-- Core (low-level) library functions --*/ + +BZ_EXTERN int BZ_API(BZ2_bzCompressInit) ( + bz_stream* strm, + int blockSize100k, + int verbosity, + int workFactor + ); + +BZ_EXTERN int BZ_API(BZ2_bzCompress) ( + bz_stream* strm, + int action + ); + +BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) ( + bz_stream* strm + ); + +BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) ( + bz_stream *strm, + int verbosity, + int small + ); + +BZ_EXTERN int BZ_API(BZ2_bzDecompress) ( + bz_stream* strm + ); + +BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) ( + bz_stream *strm + ); + + +/*-- High(er) level library functions --*/ + +#ifndef BZ_NO_STDIO +#define BZ_MAX_UNUSED 5000 + +/* Need a definitition for FILE */ +#include + +typedef void BZFILE; + +BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) ( + int* bzerror, + FILE* f, + int verbosity, + int small, + void* unused, + int nUnused + ); + +BZ_EXTERN void BZ_API(BZ2_bzReadClose) ( + int* bzerror, + BZFILE* b + ); + +BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) ( + int* bzerror, + BZFILE* b, + void** unused, + int* nUnused + ); + +BZ_EXTERN int BZ_API(BZ2_bzRead) ( + int* bzerror, + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) ( + int* bzerror, + FILE* f, + int blockSize100k, + int verbosity, + int workFactor + ); + +BZ_EXTERN void BZ_API(BZ2_bzWrite) ( + int* bzerror, + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN void BZ_API(BZ2_bzWriteClose) ( + int* bzerror, + BZFILE* b, + int abandon, + unsigned int* nbytes_in, + unsigned int* nbytes_out + ); + +BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) ( + int* bzerror, + BZFILE* b, + int abandon, + unsigned int* nbytes_in_lo32, + unsigned int* nbytes_in_hi32, + unsigned int* nbytes_out_lo32, + unsigned int* nbytes_out_hi32 + ); +#endif + + +/*-- Utility functions --*/ + +BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) ( + char* dest, + unsigned int* destLen, + char* source, + unsigned int sourceLen, + int blockSize100k, + int verbosity, + int workFactor + ); + +BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) ( + char* dest, + unsigned int* destLen, + char* source, + unsigned int sourceLen, + int small, + int verbosity + ); + + +/*-- + Code contributed by Yoshioka Tsuneo + (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp), + to support better zlib compatibility. + This code is not _officially_ part of libbzip2 (yet); + I haven't tested it, documented it, or considered the + threading-safeness of it. + If this code breaks, please contact both Yoshioka and me. +--*/ + +BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) ( + void + ); + +#ifndef BZ_NO_STDIO +BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) ( + const char *path, + const char *mode + ); + +BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) ( + int fd, + const char *mode + ); + +BZ_EXTERN int BZ_API(BZ2_bzread) ( + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN int BZ_API(BZ2_bzwrite) ( + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN int BZ_API(BZ2_bzflush) ( + BZFILE* b + ); + +BZ_EXTERN void BZ_API(BZ2_bzclose) ( + BZFILE* b + ); + +BZ_EXTERN const char * BZ_API(BZ2_bzerror) ( + BZFILE *b, + int *errnum + ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif + +/*-------------------------------------------------------------*/ +/*--- end bzlib.h ---*/ +/*-------------------------------------------------------------*/ diff --git a/include/circbuf.h b/include/circbuf.h new file mode 100644 index 0000000..e10ed95 --- /dev/null +++ b/include/circbuf.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __CIRCBUF_H__ +#define __CIRCBUF_H__ + +typedef struct circbuf { + unsigned int size; /* current number of bytes held */ + unsigned int totalsize; /* number of bytes allocated */ + + char *top; /* pointer to current buffer start */ + char *tail; /* pointer to space for next element */ + + char *data; /* all data */ + char *end; /* end of data buffer */ +} circbuf_t; + +int buf_init (circbuf_t * buf, unsigned int size); +int buf_free (circbuf_t * buf); +int buf_pop (circbuf_t * buf, char *dest, unsigned int len); +int buf_push (circbuf_t * buf, const char *src, unsigned int len); + +#endif diff --git a/include/clps7111.h b/include/clps7111.h new file mode 100644 index 0000000..d122d84 --- /dev/null +++ b/include/clps7111.h @@ -0,0 +1,276 @@ +/* + * linux/include/asm-arm/hardware/clps7111.h + * + * This file contains the hardware definitions of the CLPS7111 internal + * registers. + * + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_HARDWARE_CLPS7111_H +#define __ASM_HARDWARE_CLPS7111_H + +#define CLPS7111_PHYS_BASE (0x80000000) + +#ifndef __ASSEMBLY__ +#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) +#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) +#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) +#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) +#endif + +#define PADR (0x0000) +#define PBDR (0x0001) +#define PDDR (0x0003) +#define PADDR (0x0040) +#define PBDDR (0x0041) +#define PDDDR (0x0043) +#define PEDR (0x0080) +#define PEDDR (0x00c0) +#define SYSCON1 (0x0100) +#define SYSFLG1 (0x0140) +#define MEMCFG1 (0x0180) +#define MEMCFG2 (0x01c0) +#define DRFPR (0x0200) +#define INTSR1 (0x0240) +#define INTMR1 (0x0280) +#define LCDCON (0x02c0) +#define TC1D (0x0300) +#define TC2D (0x0340) +#define RTCDR (0x0380) +#define RTCMR (0x03c0) +#define PMPCON (0x0400) +#define CODR (0x0440) +#define UARTDR1 (0x0480) +#define UBRLCR1 (0x04c0) +#define SYNCIO (0x0500) +#define PALLSW (0x0540) +#define PALMSW (0x0580) +#define STFCLR (0x05c0) +#define BLEOI (0x0600) +#define MCEOI (0x0640) +#define TEOI (0x0680) +#define TC1EOI (0x06c0) +#define TC2EOI (0x0700) +#define RTCEOI (0x0740) +#define UMSEOI (0x0780) +#define COEOI (0x07c0) +#define HALT (0x0800) +#define STDBY (0x0840) + +#define FBADDR (0x1000) +#define SYSCON2 (0x1100) +#define SYSFLG2 (0x1140) +#define INTSR2 (0x1240) +#define INTMR2 (0x1280) +#define UARTDR2 (0x1480) +#define UBRLCR2 (0x14c0) +#define SS2DR (0x1500) +#define SRXEOF (0x1600) +#define SS2POP (0x16c0) +#define KBDEOI (0x1700) + +/* common bits: SYSCON1 / SYSCON2 */ +#define SYSCON_UARTEN (1 << 8) + +#define SYSCON1_KBDSCAN(x) ((x) & 15) +#define SYSCON1_KBDSCANMASK (15) +#define SYSCON1_TC1M (1 << 4) +#define SYSCON1_TC1S (1 << 5) +#define SYSCON1_TC2M (1 << 6) +#define SYSCON1_TC2S (1 << 7) +#define SYSCON1_UART1EN SYSCON_UARTEN +#define SYSCON1_BZTOG (1 << 9) +#define SYSCON1_BZMOD (1 << 10) +#define SYSCON1_DBGEN (1 << 11) +#define SYSCON1_LCDEN (1 << 12) +#define SYSCON1_CDENTX (1 << 13) +#define SYSCON1_CDENRX (1 << 14) +#define SYSCON1_SIREN (1 << 15) +#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) +#define SYSCON1_ADCKSEL_MASK (3 << 16) +#define SYSCON1_EXCKEN (1 << 18) +#define SYSCON1_WAKEDIS (1 << 19) +#define SYSCON1_IRTXM (1 << 20) + +/* common bits: SYSFLG1 / SYSFLG2 */ +#define SYSFLG_UBUSY (1 << 11) +#define SYSFLG_URXFE (1 << 22) +#define SYSFLG_UTXFF (1 << 23) + +#define SYSFLG1_MCDR (1 << 0) +#define SYSFLG1_DCDET (1 << 1) +#define SYSFLG1_WUDR (1 << 2) +#define SYSFLG1_WUON (1 << 3) +#define SYSFLG1_CTS (1 << 8) +#define SYSFLG1_DSR (1 << 9) +#define SYSFLG1_DCD (1 << 10) +#define SYSFLG1_UBUSY SYSFLG_UBUSY +#define SYSFLG1_NBFLG (1 << 12) +#define SYSFLG1_RSTFLG (1 << 13) +#define SYSFLG1_PFFLG (1 << 14) +#define SYSFLG1_CLDFLG (1 << 15) +#define SYSFLG1_URXFE SYSFLG_URXFE +#define SYSFLG1_UTXFF SYSFLG_UTXFF +#define SYSFLG1_CRXFE (1 << 24) +#define SYSFLG1_CTXFF (1 << 25) +#define SYSFLG1_SSIBUSY (1 << 26) +#define SYSFLG1_ID (1 << 29) + +#define SYSFLG2_SSRXOF (1 << 0) +#define SYSFLG2_RESVAL (1 << 1) +#define SYSFLG2_RESFRM (1 << 2) +#define SYSFLG2_SS2RXFE (1 << 3) +#define SYSFLG2_SS2TXFF (1 << 4) +#define SYSFLG2_SS2TXUF (1 << 5) +#define SYSFLG2_CKMODE (1 << 6) +#define SYSFLG2_UBUSY SYSFLG_UBUSY +#define SYSFLG2_URXFE SYSFLG_URXFE +#define SYSFLG2_UTXFF SYSFLG_UTXFF + +#define LCDCON_GSEN (1 << 30) +#define LCDCON_GSMD (1 << 31) + +#define SYSCON2_SERSEL (1 << 0) +#define SYSCON2_KBD6 (1 << 1) +#define SYSCON2_DRAMZ (1 << 2) +#define SYSCON2_KBWEN (1 << 3) +#define SYSCON2_SS2TXEN (1 << 4) +#define SYSCON2_PCCARD1 (1 << 5) +#define SYSCON2_PCCARD2 (1 << 6) +#define SYSCON2_SS2RXEN (1 << 7) +#define SYSCON2_UART2EN SYSCON_UARTEN +#define SYSCON2_SS2MAEN (1 << 9) +#define SYSCON2_OSTB (1 << 12) +#define SYSCON2_CLKENSL (1 << 13) +#define SYSCON2_BUZFREQ (1 << 14) + +/* common bits: UARTDR1 / UARTDR2 */ +#define UARTDR_FRMERR (1 << 8) +#define UARTDR_PARERR (1 << 9) +#define UARTDR_OVERR (1 << 10) + +/* common bits: UBRLCR1 / UBRLCR2 */ +#define UBRLCR_BAUD_MASK ((1 << 12) - 1) +#define UBRLCR_BREAK (1 << 12) +#define UBRLCR_PRTEN (1 << 13) +#define UBRLCR_EVENPRT (1 << 14) +#define UBRLCR_XSTOP (1 << 15) +#define UBRLCR_FIFOEN (1 << 16) +#define UBRLCR_WRDLEN5 (0 << 17) +#define UBRLCR_WRDLEN6 (1 << 17) +#define UBRLCR_WRDLEN7 (2 << 17) +#define UBRLCR_WRDLEN8 (3 << 17) +#define UBRLCR_WRDLEN_MASK (3 << 17) + +#define SYNCIO_SMCKEN (1 << 13) +#define SYNCIO_TXFRMEN (1 << 14) + +#define SYSCON3 0x2200 /* System Control register 3 ----------------------- */ +#define ADCCON 0x00000001 /* ADC configuration */ +#define CLKCTL 0x00000006 /* processor clock control */ +#define CLKCTL_18 0x0 /* 18.432 MHz */ +#define CLKCTL_36 0x2 /* 36.864 MHz */ +#define CLKCTL_49 0x4 /* 49.152 MHz */ +#define CLKCTL_73 0x6 /* 73.728 MHz */ +#define MCPSEL 0x00000008 /* MCP select */ +#define ADCCKNSEN 0x000010 /* ADC clock sense */ +#define VERSN 0x000000e0 /* additional version bits */ +#define VERSN_SHIFT 5 +#define FASTWAKE 0x0000100 /* Wakeup clock select: 0=8Hz, 1=4kHz */ + +#define INTSR3 0x2240 /* Interrupt Status register 3 --------------------- */ +#define MCPINT 0x00000001 /* MCP interface interrupt (FIQ) */ + +#define INTMR3 0x2280 /* Interrupt Mask register 3 ----------------------- */ +#define LEDFLSH 0x22C0 /* LED Flash control register ---------------------- */ +#define LEDFLSH_RATE 0x03 /* flash rate */ +#define LEDFLSH_RATE_SHIFT 0 +#define LEDFLSH_DUTY 0x3c /* duty ratio */ +#define LEDFLSH_DUTY_SHIFT 2 +#define LEDFLSH_ENABLE 0x40 /* enable */ + +#define IO_START CLPS7111_PHYS_BASE + +#define IO(offset) (IO_START + (offset)) + +#define IO_BYTE(offset) (*(volatile unsigned char *)(IO_START + (offset))) +#define IO_WORD(offset) (*(volatile unsigned long *)(IO_START + (offset))) + +#define IO_PADR IO_BYTE(PADR) +#define IO_PBDR IO_BYTE(PBDR) +#define IO_PDDR IO_BYTE(PDDR) +#define IO_PADDR IO_BYTE(PADDR) +#define IO_PBDDR IO_BYTE(PBDDR) +#define IO_PDDDR IO_BYTE(PDDDR) +#define IO_PEDR IO_BYTE(PEDR) +#define IO_PEDDR IO_BYTE(PEDDR) +#define IO_SYSCON IO_WORD(SYSCON) +#define IO_SYSFLG IO_WORD(SYSFLG) +#define IO_MEMCFG1 IO_WORD(MEMCFG1) +#define IO_MEMCFG2 IO_WORD(MEMCFG2) +#define IO_DRFPR IO_WORD(DRFPR) +#define IO_INTSR IO_WORD(INTSR) +#define IO_INTMR IO_WORD(INTMR) +#define IO_LCDCON IO_WORD(LCDCON) +#define IO_TC1D IO_WORD(TC1D) +#define IO_TC2D IO_WORD(TC2D) +#define IO_RTCDR IO_WORD(RTCDR) +#define IO_RTCMR IO_WORD(RTCMR) +#define IO_PMPCON IO_WORD(PMPCON) +#define IO_CODR IO_BYTE(CODR) +#define IO_UARTDR IO_WORD(UARTDR) +#define IO_UBRLCR IO_WORD(UBRLCR) +#define IO_SYNCIO IO_WORD(SYNCIO) +#define IO_PALLSW IO_WORD(PALLSW) +#define IO_PALMSW IO_WORD(PALMSW) +#define IO_STFCLR IO_WORD(STFCLR) +#define IO_BLEOI IO_WORD(BLEOI) +#define IO_MCEOI IO_WORD(MCEOI) +#define IO_TEOI IO_WORD(TEOI) +#define IO_TC1EOI IO_WORD(TC1EOI) +#define IO_TC2EOI IO_WORD(TC2EOI) +#define IO_RTCEOI IO_WORD(RTCEOI) +#define IO_UMSEOI IO_WORD(UMSEOI) +#define IO_COEOI IO_WORD(COEOI) +#define IO_HALT IO_WORD(HALT) +#define IO_STDBY IO_WORD(STDBY) +#define IO_SYSCON1 IO_WORD(SYSCON1) +#define IO_SYSFLG1 IO_WORD(SYSFLG1) +#define IO_INTSR1 IO_WORD(INTSR1) +#define IO_INTMR1 IO_WORD(INTMR1) +#define IO_UARTDR1 IO_WORD(UARTDR1) +#define IO_UBRLCR1 IO_WORD(UBRLCR1) +#define IO_FRBADDR IO_WORD(FRBADDR) +#define IO_SYSCON2 IO_WORD(SYSCON2) +#define IO_SYSFLG2 IO_WORD(SYSFLG2) +#define IO_INTSR2 IO_WORD(INTSR2) +#define IO_INTMR2 IO_WORD(INTMR2) +#define IO_UARTDR2 IO_WORD(UARTDR2) +#define IO_UBRLCR2 IO_WORD(UBRLCR2) +#define IO_KBDEOI IO_WORD(KBDEOI) + +#define IO_MCCR IO_WORD(MCCR) +#define IO_MCDR0 IO_WORD(MCDR0) +#define IO_MCDR1 IO_WORD(MCDR1) +#define IO_MCDR2 IO_WORD(MCDR2) +#define IO_MCSR IO_WORD(MCSR) +#define IO_SYSCON3 IO_WORD(SYSCON3) +#define IO_INTSR3 IO_WORD(INTSR3) +#define IO_INTMR3 IO_WORD(INTMR3) +#define IO_LEDFLSH IO_WORD(LEDFLSH) + +#endif /* __ASM_HARDWARE_CLPS7111_H */ diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h new file mode 100644 index 0000000..9ee4849 --- /dev/null +++ b/include/cmd_confdefs.h @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Definitions for Configuring the monitor commands + */ +#ifndef _CMD_CONFIG_H +#define _CMD_CONFIG_H + +/* + * Configurable monitor commands + */ +#define CFG_CMD_BDI 0x00000001ULL /* bdinfo */ +#define CFG_CMD_LOADS 0x00000002ULL /* loads */ +#define CFG_CMD_LOADB 0x00000004ULL /* loadb */ +#define CFG_CMD_IMI 0x00000008ULL /* iminfo */ +#define CFG_CMD_CACHE 0x00000010ULL /* icache, dcache */ +#define CFG_CMD_FLASH 0x00000020ULL /* flinfo, erase, protect */ +#define CFG_CMD_MEMORY 0x00000040ULL /* md, mm, nm, mw, cp, cmp, */ + /* crc, base, loop, mtest */ +#define CFG_CMD_NET 0x00000080ULL /* bootp, tftpboot, rarpboot */ +#define CFG_CMD_ENV 0x00000100ULL /* saveenv */ +#define CFG_CMD_KGDB 0x0000000000000200ULL /* kgdb */ +#define CFG_CMD_PCMCIA 0x00000400ULL /* PCMCIA support */ +#define CFG_CMD_IDE 0x00000800ULL /* IDE harddisk support */ +#define CFG_CMD_PCI 0x00001000ULL /* pciinfo */ +#define CFG_CMD_IRQ 0x00002000ULL /* irqinfo */ +#define CFG_CMD_BOOTD 0x00004000ULL /* bootd */ +#define CFG_CMD_CONSOLE 0x00008000ULL /* coninfo */ +#define CFG_CMD_EEPROM 0x00010000ULL /* EEPROM read/write support */ +#define CFG_CMD_ASKENV 0x00020000ULL /* ask for env variable */ +#define CFG_CMD_RUN 0x00040000ULL /* run command in env variable */ +#define CFG_CMD_ECHO 0x00080000ULL /* echo arguments */ +#define CFG_CMD_I2C 0x00100000ULL /* I2C serial bus support */ +#define CFG_CMD_REGINFO 0x00200000ULL /* Register dump */ +#define CFG_CMD_IMMAP 0x00400000ULL /* IMMR dump support */ +#define CFG_CMD_DATE 0x00800000ULL /* support for RTC, date/time...*/ +#define CFG_CMD_DHCP 0x01000000ULL /* DHCP Support */ +#define CFG_CMD_BEDBUG 0x02000000ULL /* Include BedBug Debugger */ +#define CFG_CMD_FDC 0x04000000ULL /* Floppy Disk Support */ +#define CFG_CMD_SCSI 0x08000000ULL /* SCSI Support */ +#define CFG_CMD_AUTOSCRIPT 0x10000000ULL /* Autoscript Support */ +#define CFG_CMD_MII 0x20000000ULL /* MII support */ +#define CFG_CMD_SETGETDCR 0x40000000ULL /* DCR support on 4xx */ +#define CFG_CMD_BSP 0x80000000ULL /* Board Specific functions */ + +#define CFG_CMD_ELF 0x0000000100000000ULL /* ELF (VxWorks) load/boot cmd */ +#define CFG_CMD_MISC 0x0000000200000000ULL /* Misc functions like sleep etc*/ +#define CFG_CMD_USB 0x0000000400000000ULL /* USB Support */ +#define CFG_CMD_DOC 0x0000000800000000ULL /* Disk-On-Chip Support */ +#define CFG_CMD_JFFS2 0x0000001000000000ULL /* JFFS2 Support */ +#define CFG_CMD_DTT 0x0000002000000000ULL /* Digital Therm and Thermostat */ +#define CFG_CMD_SDRAM 0x0000004000000000ULL /* SDRAM DIMM SPD info printout */ +#define CFG_CMD_DIAG 0x0000008000000000ULL /* Diagnostics */ +#define CFG_CMD_FPGA 0x0000010000000000ULL /* FPGA configuration Support */ +#define CFG_CMD_HWFLOW 0x0000020000000000ULL /* RTS/CTS hw flow control */ +#define CFG_CMD_SAVES 0x0000040000000000ULL /* save S record dump */ +#define CFG_CMD_SPI 0x0000100000000000ULL /* SPI utility */ +#define CFG_CMD_FDOS 0x0000200000000000ULL /* Floppy DOS support */ +#define CFG_CMD_VFD 0x0000400000000000ULL /* VFD support (TRAB) */ +#define CFG_CMD_NAND 0x0000800000000000ULL /* NAND support */ +#define CFG_CMD_BMP 0x0001000000000000ULL /* BMP support */ +#define CFG_CMD_PORTIO 0x0002000000000000ULL /* Port I/O */ +#define CFG_CMD_PING 0x0004000000000000ULL /* ping support */ +#define CFG_CMD_MMC 0x0008000000000000ULL /* MMC support */ +#define CFG_CMD_FAT 0x0010000000000000ULL /* FAT support */ +#define CFG_CMD_IMLS 0x0020000000000000ULL /* List all found images */ +#define CFG_CMD_ITEST 0x0040000000000000ULL /* Integer (and string) test */ +#define CFG_CMD_NFS 0x0080000000000000ULL /* NFS support */ +#define CFG_CMD_REISER 0x0100000000000000ULL /* Reiserfs support */ +#define CFG_CMD_CDP 0x0200000000000000ULL /* Cisco Discovery Protocol */ +#define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */ +#define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */ +#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ +#define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */ +#define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */ + +#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ + +/* Commands that are considered "non-standard" for some reason + * (memory hogs, requires special hardware, not fully tested, etc.) + */ +#define CFG_CMD_NONSTD (CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_CDP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FDC | \ + CFG_CMD_FAT | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_MII | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_PING | \ + CFG_CMD_PORTIO | \ + CFG_CMD_REGINFO | \ + CFG_CMD_REISER | \ + CFG_CMD_SAVES | \ + CFG_CMD_SCSI | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP | \ + CFG_CMD_SPI | \ + CFG_CMD_UNIVERSE | \ + CFG_CMD_USB | \ + CFG_CMD_VFD ) + +/* Default configuration + */ +#define CONFIG_CMD_DFL (CFG_CMD_ALL & ~CFG_CMD_NONSTD) + +#ifndef CONFIG_COMMANDS +#define CONFIG_COMMANDS CONFIG_CMD_DFL +#endif + + +/* + * optional BOOTP fields + */ + +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_NISDOMAIN 0x00000008 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 +#define CONFIG_BOOTP_BOOTFILESIZE 0x00000020 +#define CONFIG_BOOTP_DNS 0x00000040 +#define CONFIG_BOOTP_DNS2 0x00000080 +#define CONFIG_BOOTP_SEND_HOSTNAME 0x00000100 +#define CONFIG_BOOTP_NTPSERVER 0x00000200 +#define CONFIG_BOOTP_TIMEOFFSET 0x00000400 + +#define CONFIG_BOOTP_VENDOREX 0x80000000 + +#define CONFIG_BOOTP_ALL (~CONFIG_BOOTP_VENDOREX) + + +#define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | \ + CONFIG_BOOTP_GATEWAY | \ + CONFIG_BOOTP_HOSTNAME | \ + CONFIG_BOOTP_BOOTPATH) + +#ifndef CONFIG_BOOTP_MASK +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#endif + +#endif /* _CMD_CONFIG_H */ diff --git a/include/command.h b/include/command.h new file mode 100644 index 0000000..a2936ad --- /dev/null +++ b/include/command.h @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Definitions for Command Processor + */ +#ifndef __COMMAND_H +#define __COMMAND_H + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef __ASSEMBLY__ +/* + * Monitor Command Table + */ + +struct cmd_tbl_s { + char *name; /* Command Name */ + int maxargs; /* maximum number of arguments */ + int repeatable; /* autorepeat allowed? */ + /* Implementation function */ + int (*cmd)(struct cmd_tbl_s *, int, int, char *[]); + char *usage; /* Usage message (short) */ +#ifdef CFG_LONGHELP + char *help; /* Help message (long) */ +#endif +#ifdef CONFIG_AUTO_COMPLETE + /* do auto completion on the arguments */ + int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[]); +#endif +}; + +typedef struct cmd_tbl_s cmd_tbl_t; + +extern cmd_tbl_t __u_boot_cmd_start; +extern cmd_tbl_t __u_boot_cmd_end; + + +/* common/command.c */ +cmd_tbl_t *find_cmd(const char *cmd); + +#ifdef CONFIG_AUTO_COMPLETE +extern void install_auto_complete(void); +extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); +#endif + +/* + * Monitor Command + * + * All commands use a common argument format: + * + * void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + */ + +typedef void command_t (cmd_tbl_t *, int, int, char *[]); + +#endif /* __ASSEMBLY__ */ + +/* + * Command Flags: + */ +#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ +#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ + +/* + * Configurable monitor commands definitions have been moved + * to include/cmd_confdefs.h + */ + + +#define Struct_Section __attribute__ ((unused,section (".u_boot_cmd"))) + +#ifdef CFG_LONGHELP + +#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \ +cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help} + +#else /* no long help info */ + +#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \ +cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage} + +#endif /* CFG_LONGHELP */ + +#endif /* __COMMAND_H */ diff --git a/include/common.h b/include/common.h new file mode 100644 index 0000000..d2570a8 --- /dev/null +++ b/include/common.h @@ -0,0 +1,600 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __COMMON_H_ +#define __COMMON_H_ 1 + +#undef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +typedef unsigned char uchar; +typedef volatile unsigned long vu_long; +typedef volatile unsigned short vu_short; +typedef volatile unsigned char vu_char; + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PCI) && defined(CONFIG_440) +#include +#endif +#if defined(CONFIG_8xx) +#include +#if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \ + defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ + defined(CONFIG_MPC859DSL) || \ + defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \ + defined(CONFIG_MPC866P) +# define CONFIG_MPC866_FAMILY 1 +#elif defined(CONFIG_MPC870) \ + || defined(CONFIG_MPC875) \ + || defined(CONFIG_MPC880) \ + || defined(CONFIG_MPC885) +# define CONFIG_MPC885_FAMILY 1 +#endif +#if defined(CONFIG_MPC860) \ + || defined(CONFIG_MPC860T) \ + || defined(CONFIG_MPC866_FAMILY) \ + || defined(CONFIG_MPC885_FAMILY) +# define CONFIG_MPC86x 1 +#endif +#elif defined(CONFIG_5xx) +#include +#elif defined(CONFIG_MPC5xxx) +#include +#elif defined(CONFIG_MPC8220) +#include +#elif defined(CONFIG_8260) +#if defined(CONFIG_MPC8247) \ + || defined(CONFIG_MPC8248) \ + || defined(CONFIG_MPC8271) \ + || defined(CONFIG_MPC8272) +#define CONFIG_MPC8272_FAMILY 1 +#endif +#if defined(CONFIG_MPC8272_FAMILY) +#define CONFIG_MPC8260 1 +#endif +#include +#endif +#ifdef CONFIG_MPC85xx +#include +#include +#endif +#ifdef CONFIG_MPC83XX +#include +#include +#endif +#ifdef CONFIG_4xx +#include +#endif +#ifdef CONFIG_HYMOD +#include +#endif +#ifdef CONFIG_ARM +#define asmlinkage /* nothing */ +#endif + +#include +#include +#include + +#ifdef DEBUG +#define debug(fmt,args...) printf (fmt ,##args) +#define debugX(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args); +#else +#define debug(fmt,args...) +#define debugX(level,fmt,args...) +#endif /* DEBUG */ + +typedef void (interrupt_handler_t)(void *); + +#include /* boot information for Linux kernel */ +#include /* global data used for startup functions */ + +/* + * enable common handling for all TQM8xxL/M boards: + * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards + * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards + */ +#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ + defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ + defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) +# ifndef CONFIG_TQM8xxM +# define CONFIG_TQM8xxM +# endif +#endif +#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ + defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ + defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) +# ifndef CONFIG_TQM8xxL +# define CONFIG_TQM8xxL +# endif +#endif + +#ifndef CONFIG_SERIAL_MULTI + +#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \ + || defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \ + || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) + +#define CONFIG_SERIAL_MULTI 1 + +#endif + +#endif /* CONFIG_SERIAL_MULTI */ + +/* + * General Purpose Utilities + */ +#define min(X, Y) \ + ({ typeof (X) __x = (X), __y = (Y); \ + (__x < __y) ? __x : __y; }) + +#define max(X, Y) \ + ({ typeof (X) __x = (X), __y = (Y); \ + (__x > __y) ? __x : __y; }) + + +/* + * Function Prototypes + */ + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO +void serial_buffered_init (void); +void serial_buffered_putc (const char); +void serial_buffered_puts (const char *); +int serial_buffered_getc (void); +int serial_buffered_tstc (void); +#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ + +void hang (void) __attribute__ ((noreturn)); + +/* */ +long int initdram (int); +int display_options (void); +void print_size (ulong, const char *); + +/* common/main.c */ +void main_loop (void); +int run_command (const char *cmd, int flag); +int readline (const char *const prompt); +void init_cmd_timeout(void); +void reset_cmd_timeout(void); + +/* lib_$(ARCH)/board.c */ +void board_init_f (ulong); +void board_init_r (gd_t *, ulong); +int checkboard (void); +int checkflash (void); +int checkdram (void); +char * strmhz(char *buf, long hz); +int last_stage_init(void); +extern ulong monitor_flash_len; + +/* common/flash.c */ +void flash_perror (int); + +/* common/cmd_autoscript.c */ +int autoscript (ulong addr); + +/* common/cmd_bootm.c */ +void print_image_hdr (image_header_t *hdr); + +extern ulong load_addr; /* Default Load Address */ + +/* common/cmd_nvedit.c */ +int env_init (void); +void env_relocate (void); +char *getenv (char *); +int getenv_r (char *name, char *buf, unsigned len); +int saveenv (void); +#ifdef CONFIG_PPC /* ARM version to be fixed! */ +void inline setenv (char *, char *); +#else +void setenv (char *, char *); +#endif /* CONFIG_PPC */ +#ifdef CONFIG_ARM +# include +# include +# include /* ARM version to be fixed! */ +#endif /* CONFIG_ARM */ +#ifdef CONFIG_I386 /* x86 version to be fixed! */ +# include +#endif /* CONFIG_I386 */ + +#ifdef CONFIG_AUTO_COMPLETE +int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); +#endif + +void pci_init (void); +void pci_init_board(void); +void pciinfo (int, int); + +#if defined(CONFIG_PCI) && defined(CONFIG_440) +# if defined(CFG_PCI_PRE_INIT) + int pci_pre_init (struct pci_controller * ); +# endif +# if defined(CFG_PCI_TARGET_INIT) + void pci_target_init (struct pci_controller *); +# endif +# if defined(CFG_PCI_MASTER_INIT) + void pci_master_init (struct pci_controller *); +# endif + int is_pci_host (struct pci_controller *); +#endif + +int misc_init_f (void); +int misc_init_r (void); + +/* common/exports.c */ +void jumptable_init(void); + +/* common/memsize.c */ +int get_ram_size (volatile long *, long); + +/* $(BOARD)/$(BOARD).c */ +void reset_phy (void); +void fdc_hw_init (void); + +/* $(BOARD)/eeprom.c */ +void eeprom_init (void); +#ifndef CONFIG_SPI +int eeprom_probe (unsigned dev_addr, unsigned offset); +#endif +int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); +int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); +#ifdef CONFIG_LWMON +extern uchar pic_read (uchar reg); +extern void pic_write (uchar reg, uchar val); +#endif + +/* + * Set this up regardless of board + * type, to prevent errors. + */ +#if defined(CONFIG_SPI) || !defined(CFG_I2C_EEPROM_ADDR) +# define CFG_DEF_EEPROM_ADDR 0 +#else +# define CFG_DEF_EEPROM_ADDR CFG_I2C_EEPROM_ADDR +#endif /* CONFIG_SPI || !defined(CFG_I2C_EEPROM_ADDR) */ + +#if defined(CONFIG_SPI) +extern void spi_init_f (void); +extern void spi_init_r (void); +extern ssize_t spi_read (uchar *, int, uchar *, int); +extern ssize_t spi_write (uchar *, int, uchar *, int); +#endif + +#ifdef CONFIG_RPXCLASSIC +void rpxclassic_init (void); +#endif + +void rpxlite_init (void); + +#ifdef CONFIG_MBX +/* $(BOARD)/mbx8xx.c */ +void mbx_init (void); +void board_serial_init (void); +void board_ether_init (void); +#endif + +#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \ + defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \ + defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) +void board_get_enetaddr (uchar *addr); +#endif + +#ifdef CONFIG_HERMES +/* $(BOARD)/hermes.c */ +void hermes_start_lxt980 (int speed); +#endif + +#ifdef CONFIG_EVB64260 +void evb64260_init(void); +void debug_led(int, int); +void display_mem_map(void); +void perform_soft_reset(void); +#endif + +void load_sernum_ethaddr (void); + +/* $(BOARD)/$(BOARD).c */ +int board_early_init_f (void); +int board_late_init (void); +int board_postclk_init (void); /* after clocks/timebase, before env/serial */ +int board_early_init_r (void); +void board_poweroff (void); + +#if defined(CFG_DRAM_TEST) +int testdram(void); +#endif /* CFG_DRAM_TEST */ + +/* $(CPU)/start.S */ +#if defined(CONFIG_5xx) || \ + defined(CONFIG_8xx) +uint get_immr (uint); +#endif +uint get_pir (void); +#if defined(CONFIG_MPC5xxx) +uint get_svr (void); +#endif +uint get_pvr (void); +uint get_svr (void); +uint rd_ic_cst (void); +void wr_ic_cst (uint); +void wr_ic_adr (uint); +uint rd_dc_cst (void); +void wr_dc_cst (uint); +void wr_dc_adr (uint); +int icache_status (void); +void icache_enable (void); +void icache_disable(void); +int dcache_status (void); +void dcache_enable (void); +void dcache_disable(void); +void relocate_code (ulong, gd_t *, ulong); +ulong get_endaddr (void); +void trap_init (ulong); +#if defined (CONFIG_4xx) || \ + defined (CONFIG_MPC5xxx) || \ + defined (CONFIG_74xx_7xx) || \ + defined (CONFIG_74x) || \ + defined (CONFIG_75x) || \ + defined (CONFIG_74xx) || \ + defined (CONFIG_MPC8220) || \ + defined(CONFIG_MPC85xx) +unsigned char in8(unsigned int); +void out8(unsigned int, unsigned char); +unsigned short in16(unsigned int); +unsigned short in16r(unsigned int); +void out16(unsigned int, unsigned short value); +void out16r(unsigned int, unsigned short value); +unsigned long in32(unsigned int); +unsigned long in32r(unsigned int); +void out32(unsigned int, unsigned long value); +void out32r(unsigned int, unsigned long value); +void ppcDcbf(unsigned long value); +void ppcDcbi(unsigned long value); +void ppcSync(void); +void ppcDcbz(unsigned long value); +#endif + +/* $(CPU)/cpu.c */ +int checkcpu (void); +int checkicache (void); +int checkdcache (void); +void upmconfig (unsigned int, unsigned int *, unsigned int); +ulong get_tbclk (void); +void reset_cpu (ulong addr); + +/* $(CPU)/serial.c */ +int serial_init (void); +void serial_addr (unsigned int); +void serial_setbrg (void); +void serial_putc (const char); +void serial_putc_raw(const char); +void serial_puts (const char *); +int serial_getc (void); +int serial_tstc (void); + +void _serial_setbrg (const int); +void _serial_putc (const char, const int); +void _serial_putc_raw(const char, const int); +void _serial_puts (const char *, const int); +int _serial_getc (const int); +int _serial_tstc (const int); + +/* $(CPU)/speed.c */ +int get_clocks (void); +int get_clocks_866 (void); +int sdram_adjust_866 (void); +int adjust_sdram_tbs_8xx (void); +#if defined(CONFIG_8260) +int prt_8260_clks (void); +#elif defined(CONFIG_MPC83XX) +int print_clock_conf(void); +#elif defined(CONFIG_MPC5xxx) +int prt_mpc5xxx_clks (void); +#endif +#if defined(CONFIG_MPC8220) +int prt_mpc8220_clks (void); +#endif +#ifdef CONFIG_4xx +ulong get_OPB_freq (void); +ulong get_PCI_freq (void); +#endif +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X) +ulong get_FCLK (void); +ulong get_HCLK (void); +ulong get_PCLK (void); +ulong get_UCLK (void); +#endif +#if defined(CONFIG_LH7A40X) +ulong get_PLLCLK (void); +#endif +#if defined CONFIG_INCA_IP +uint incaip_get_cpuclk (void); +#endif +#if defined(CONFIG_IMX) +ulong get_systemPLLCLK(void); +ulong get_FCLK(void); +ulong get_HCLK(void); +ulong get_BCLK(void); +ulong get_PERCLK1(void); +ulong get_PERCLK2(void); +ulong get_PERCLK3(void); +#endif +ulong get_bus_freq (ulong); + +#if defined(CONFIG_MPC85xx) +typedef MPC85xx_SYS_INFO sys_info_t; +void get_sys_info ( sys_info_t * ); +#endif + +#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) +# if defined(CONFIG_440) + typedef PPC440_SYS_INFO sys_info_t; +# else + typedef PPC405_SYS_INFO sys_info_t; +# endif +void get_sys_info ( sys_info_t * ); +#endif + +/* $(CPU)/cpu_init.c */ +#if defined(CONFIG_8xx) || defined(CONFIG_8260) +void cpu_init_f (volatile immap_t *immr); +#endif +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) +void cpu_init_f (void); +#endif + +int cpu_init_r (void); +#if defined(CONFIG_8260) +int prt_8260_rsr (void); +#endif + +/* $(CPU)/interrupts.c */ +int interrupt_init (void); +void timer_interrupt (struct pt_regs *); +void external_interrupt (struct pt_regs *); +void irq_install_handler(int, interrupt_handler_t *, void *); +void irq_free_handler (int); +void reset_timer (void); +ulong get_timer (ulong base); +void set_timer (ulong t); +void enable_interrupts (void); +int disable_interrupts (void); + +/* $(CPU)/.../commproc.c */ +int dpram_init (void); +uint dpram_base(void); +uint dpram_base_align(uint align); +uint dpram_alloc(uint size); +uint dpram_alloc_align(uint size,uint align); +void post_word_store (ulong); +ulong post_word_load (void); +void bootcount_store (ulong); +ulong bootcount_load (void); +#define BOOTCOUNT_MAGIC 0xB001C041 + +/* $(CPU)/.../ */ +void mii_init (void); + +/* $(CPU)/.../lcd.c */ +ulong lcd_setmem (ulong); + +/* $(CPU)/.../vfd.c */ +ulong vfd_setmem (ulong); + +/* $(CPU)/.../video.c */ +ulong video_setmem (ulong); + +/* lib_$(ARCH)/cache.c */ +void flush_cache (unsigned long, unsigned long); + + +/* lib_$(ARCH)/ticks.S */ +unsigned long long get_ticks(void); +void wait_ticks (unsigned long); + +/* lib_$(ARCH)/time.c */ +void udelay (unsigned long); +ulong usec2ticks (unsigned long usec); +ulong ticks2usec (unsigned long ticks); +int init_timebase (void); + +/* lib_generic/vsprintf.c */ +ulong simple_strtoul(const char *cp,char **endp,unsigned int base); +#ifdef CFG_64BIT_VSPRINTF +unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); +#endif +long simple_strtol(const char *cp,char **endp,unsigned int base); +void panic(const char *fmt, ...); +int sprintf(char * buf, const char *fmt, ...); +int vsprintf(char *buf, const char *fmt, va_list args); + +/* lib_generic/crc32.c */ +ulong crc32 (ulong, const unsigned char *, uint); +ulong crc32_no_comp (ulong, const unsigned char *, uint); + +/* common/console.c */ +int console_init_f(void); /* Before relocation; uses the serial stuff */ +int console_init_r(void); /* After relocation; uses the console stuff */ +int console_assign (int file, char *devname); /* Assign the console */ +int ctrlc (void); +int had_ctrlc (void); /* have we had a Control-C since last clear? */ +void clear_ctrlc (void); /* clear the Control-C condition */ +int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ + +/* + * STDIO based functions (can always be used) + */ + +/* serial stuff */ +void serial_printf (const char *fmt, ...); + +/* stdin */ +int getc(void); +int tstc(void); + +/* stdout */ +void putc(const char c); +void puts(const char *s); +void printf(const char *fmt, ...); +void vprintf(const char *fmt, va_list args); + +/* stderr */ +#define eputc(c) fputc(stderr, c) +#define eputs(s) fputs(stderr, s) +#define eprintf(fmt,args...) fprintf(stderr,fmt ,##args) + +/* + * FILE based functions (can only be used AFTER relocation!) + */ + +#define stdin 0 +#define stdout 1 +#define stderr 2 +#define MAX_FILES 3 + +void fprintf(int file, const char *fmt, ...); +void fputs(int file, const char *s); +void fputc(int file, const char c); +int ftstc(int file); +int fgetc(int file); + +int pcmcia_init (void); + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress (int status); +#endif + +#ifdef CONFIG_INIT_CRITICAL +#error CONFIG_INIT_CRITICAL is depracted! +#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. +#endif + +#endif /* __COMMON_H_ */ diff --git a/include/commproc.h b/include/commproc.h new file mode 100644 index 0000000..7900166 --- /dev/null +++ b/include/commproc.h @@ -0,0 +1,1811 @@ +/* + * MPC8xx Communication Processor Module. + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file contains structures and information for the communication + * processor channels. Some CPM control and status is available + * throught the MPC8xx internal memory map. See immap.h for details. + * This file only contains what I need for the moment, not the total + * CPM capabilities. I (or someone else) will add definitions as they + * are needed. -- Dan + * + * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 + * bytes of the DP RAM and relocates the I2C parameter area to the + * IDMA1 space. The remaining DP RAM is available for buffer descriptors + * or other use. + */ +#ifndef __CPM_8XX__ +#define __CPM_8XX__ + +#include +#include + +/* CPM Command register. +*/ +#define CPM_CR_RST ((ushort)0x8000) +#define CPM_CR_OPCODE ((ushort)0x0f00) +#define CPM_CR_CHAN ((ushort)0x00f0) +#define CPM_CR_FLG ((ushort)0x0001) + +/* Some commands (there are more...later) +*/ +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_INIT_RX ((ushort)0x0001) +#define CPM_CR_INIT_TX ((ushort)0x0002) +#define CPM_CR_HUNT_MODE ((ushort)0x0003) +#define CPM_CR_STOP_TX ((ushort)0x0004) +#define CPM_CR_RESTART_TX ((ushort)0x0006) +#define CPM_CR_SET_GADDR ((ushort)0x0008) + +/* Channel numbers. +*/ +#define CPM_CR_CH_SCC1 ((ushort)0x0000) +#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ +#define CPM_CR_CH_SCC2 ((ushort)0x0004) +#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ +#define CPM_CR_CH_SCC3 ((ushort)0x0008) +#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ +#define CPM_CR_CH_SCC4 ((ushort)0x000c) +#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ + +#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) + +/* + * DPRAM defines and allocation functions + */ + +/* The dual ported RAM is multi-functional. Some areas can be (and are + * being) used for microcode. There is an area that can only be used + * as data ram for buffer descriptors, which is all we use right now. + * Currently the first 512 and last 256 bytes are used for microcode. + */ +#ifdef CFG_ALLOC_DPRAM + +#define CPM_DATAONLY_BASE ((uint)0x0800) +#define CPM_DATAONLY_SIZE ((uint)0x0700) +#define CPM_DP_NOSPACE ((uint)0x7fffffff) + +#else + +#define CPM_SERIAL_BASE 0x0800 +#define CPM_I2C_BASE 0x0820 +#define CPM_SPI_BASE 0x0840 +#define CPM_FEC_BASE 0x0860 +#define CPM_SERIAL2_BASE 0x08E0 +#define CPM_SCC_BASE 0x0900 +#define CPM_POST_BASE 0x0980 +#define CPM_WLKBD_BASE 0x0a00 + +#endif + +#ifndef CFG_CPM_POST_WORD_ADDR +#define CPM_POST_WORD_ADDR 0x07FC +#else +#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR +#endif + +#ifndef CFG_CPM_BOOTCOUNT_ADDR +#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) +#else +#define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR +#endif + +#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ + +/* Export the base address of the communication processor registers + * and dual port ram. + */ +extern cpm8xx_t *cpmp; /* Pointer to comm processor */ + +/* Buffer descriptors used by many of the CPM protocols. +*/ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ + +/* Parameter RAM offsets. +*/ +#define PROFF_SCC1 ((uint)0x0000) +#define PROFF_IIC ((uint)0x0080) +#define PROFF_SCC2 ((uint)0x0100) +#define PROFF_SPI ((uint)0x0180) +#define PROFF_SCC3 ((uint)0x0200) +#define PROFF_SMC1 ((uint)0x0280) +#define PROFF_SCC4 ((uint)0x0300) +#define PROFF_SMC2 ((uint)0x0380) + +/* Define enough so I can at least use the serial port as a UART. + * The MBX uses SMC1 as the host serial port. + */ +typedef struct smc_uart { + ushort smc_rbase; /* Rx Buffer descriptor base address */ + ushort smc_tbase; /* Tx Buffer descriptor base address */ + u_char smc_rfcr; /* Rx function code */ + u_char smc_tfcr; /* Tx function code */ + ushort smc_mrblr; /* Max receive buffer length */ + uint smc_rstate; /* Internal */ + uint smc_idp; /* Internal */ + ushort smc_rbptr; /* Internal */ + ushort smc_ibc; /* Internal */ + uint smc_rxtmp; /* Internal */ + uint smc_tstate; /* Internal */ + uint smc_tdp; /* Internal */ + ushort smc_tbptr; /* Internal */ + ushort smc_tbc; /* Internal */ + uint smc_txtmp; /* Internal */ + ushort smc_maxidl; /* Maximum idle characters */ + ushort smc_tmpidl; /* Temporary idle counter */ + ushort smc_brklen; /* Last received break length */ + ushort smc_brkec; /* rcv'd break condition counter */ + ushort smc_brkcr; /* xmt break count register */ + ushort smc_rmask; /* Temporary bit mask */ +} smc_uart_t; + +/* Function code bits. +*/ +#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ + +/* SMC uart mode register. +*/ +#define SMCMR_REN ((ushort)0x0001) +#define SMCMR_TEN ((ushort)0x0002) +#define SMCMR_DM ((ushort)0x000c) +#define SMCMR_SM_GCI ((ushort)0x0000) +#define SMCMR_SM_UART ((ushort)0x0020) +#define SMCMR_SM_TRANS ((ushort)0x0030) +#define SMCMR_SM_MASK ((ushort)0x0030) +#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ +#define SMCMR_REVD SMCMR_PM_EVEN +#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ +#define SMCMR_BS SMCMR_PEN +#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ +#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ +#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) + +/* SMC2 as Centronics parallel printer. It is half duplex, in that + * it can only receive or transmit. The parameter ram values for + * each direction are either unique or properly overlap, so we can + * include them in one structure. + */ +typedef struct smc_centronics { + ushort scent_rbase; + ushort scent_tbase; + u_char scent_cfcr; + u_char scent_smask; + ushort scent_mrblr; + uint scent_rstate; + uint scent_r_ptr; + ushort scent_rbptr; + ushort scent_r_cnt; + uint scent_rtemp; + uint scent_tstate; + uint scent_t_ptr; + ushort scent_tbptr; + ushort scent_t_cnt; + uint scent_ttemp; + ushort scent_max_sl; + ushort scent_sl_cnt; + ushort scent_character1; + ushort scent_character2; + ushort scent_character3; + ushort scent_character4; + ushort scent_character5; + ushort scent_character6; + ushort scent_character7; + ushort scent_character8; + ushort scent_rccm; + ushort scent_rccr; +} smc_cent_t; + +/* Centronics Status Mask Register. +*/ +#define SMC_CENT_F ((u_char)0x08) +#define SMC_CENT_PE ((u_char)0x04) +#define SMC_CENT_S ((u_char)0x02) + +/* SMC Event and Mask register. +*/ +#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ +#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ +#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ +#define SMCM_BSY ((unsigned char)0x04) +#define SMCM_TX ((unsigned char)0x02) +#define SMCM_RX ((unsigned char)0x01) + +/* Baud rate generators. +*/ +#define CPM_BRG_RST ((uint)0x00020000) +#define CPM_BRG_EN ((uint)0x00010000) +#define CPM_BRG_EXTC_INT ((uint)0x00000000) +#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) +#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) +#define CPM_BRG_ATB ((uint)0x00002000) +#define CPM_BRG_CD_MASK ((uint)0x00001ffe) +#define CPM_BRG_DIV16 ((uint)0x00000001) + +/* SI Clock Route Register +*/ +#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) +#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) +#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) +#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) +#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) +#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) +#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) + +/* SCCs. +*/ +#define SCC_GSMRH_IRP ((uint)0x00040000) +#define SCC_GSMRH_GDE ((uint)0x00010000) +#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) +#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) +#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) +#define SCC_GSMRH_REVD ((uint)0x00002000) +#define SCC_GSMRH_TRX ((uint)0x00001000) +#define SCC_GSMRH_TTX ((uint)0x00000800) +#define SCC_GSMRH_CDP ((uint)0x00000400) +#define SCC_GSMRH_CTSP ((uint)0x00000200) +#define SCC_GSMRH_CDS ((uint)0x00000100) +#define SCC_GSMRH_CTSS ((uint)0x00000080) +#define SCC_GSMRH_TFL ((uint)0x00000040) +#define SCC_GSMRH_RFW ((uint)0x00000020) +#define SCC_GSMRH_TXSY ((uint)0x00000010) +#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) +#define SCC_GSMRH_SYNL8 ((uint)0x00000008) +#define SCC_GSMRH_SYNL4 ((uint)0x00000004) +#define SCC_GSMRH_RTSM ((uint)0x00000002) +#define SCC_GSMRH_RSYN ((uint)0x00000001) + +#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ +#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) +#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) +#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) +#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) +#define SCC_GSMRL_TCI ((uint)0x10000000) +#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) +#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) +#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) +#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) +#define SCC_GSMRL_RINV ((uint)0x02000000) +#define SCC_GSMRL_TINV ((uint)0x01000000) +#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) +#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) +#define SCC_GSMRL_TPL_48 ((uint)0x00800000) +#define SCC_GSMRL_TPL_32 ((uint)0x00600000) +#define SCC_GSMRL_TPL_16 ((uint)0x00400000) +#define SCC_GSMRL_TPL_8 ((uint)0x00200000) +#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) +#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) +#define SCC_GSMRL_TPP_01 ((uint)0x00100000) +#define SCC_GSMRL_TPP_10 ((uint)0x00080000) +#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) +#define SCC_GSMRL_TEND ((uint)0x00040000) +#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) +#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) +#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) +#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) +#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) +#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) +#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) +#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) +#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) +#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) +#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) +#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) +#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) +#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) +#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ +#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) +#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) +#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) +#define SCC_GSMRL_ENR ((uint)0x00000020) +#define SCC_GSMRL_ENT ((uint)0x00000010) +#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) +#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) +#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) +#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) +#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) +#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) +#define SCC_GSMRL_MODE_UART ((uint)0x00000004) +#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) +#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) +#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) + +#define SCC_TODR_TOD ((ushort)0x8000) + +/* SCC Event and Mask register. +*/ +#define SCCM_TXE ((unsigned char)0x10) +#define SCCM_BSY ((unsigned char)0x04) +#define SCCM_TX ((unsigned char)0x02) +#define SCCM_RX ((unsigned char)0x01) + +typedef struct scc_param { + ushort scc_rbase; /* Rx Buffer descriptor base address */ + ushort scc_tbase; /* Tx Buffer descriptor base address */ + u_char scc_rfcr; /* Rx function code */ + u_char scc_tfcr; /* Tx function code */ + ushort scc_mrblr; /* Max receive buffer length */ + uint scc_rstate; /* Internal */ + uint scc_idp; /* Internal */ + ushort scc_rbptr; /* Internal */ + ushort scc_ibc; /* Internal */ + uint scc_rxtmp; /* Internal */ + uint scc_tstate; /* Internal */ + uint scc_tdp; /* Internal */ + ushort scc_tbptr; /* Internal */ + ushort scc_tbc; /* Internal */ + uint scc_txtmp; /* Internal */ + uint scc_rcrc; /* Internal */ + uint scc_tcrc; /* Internal */ +} sccp_t; + +/* Function code bits. +*/ +#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ + +/* CPM Ethernet through SCCx. + */ +typedef struct scc_enet { + sccp_t sen_genscc; + uint sen_cpres; /* Preset CRC */ + uint sen_cmask; /* Constant mask for CRC */ + uint sen_crcec; /* CRC Error counter */ + uint sen_alec; /* alignment error counter */ + uint sen_disfc; /* discard frame counter */ + ushort sen_pads; /* Tx short frame pad character */ + ushort sen_retlim; /* Retry limit threshold */ + ushort sen_retcnt; /* Retry limit counter */ + ushort sen_maxflr; /* maximum frame length register */ + ushort sen_minflr; /* minimum frame length register */ + ushort sen_maxd1; /* maximum DMA1 length */ + ushort sen_maxd2; /* maximum DMA2 length */ + ushort sen_maxd; /* Rx max DMA */ + ushort sen_dmacnt; /* Rx DMA counter */ + ushort sen_maxb; /* Max BD byte count */ + ushort sen_gaddr1; /* Group address filter */ + ushort sen_gaddr2; + ushort sen_gaddr3; + ushort sen_gaddr4; + uint sen_tbuf0data0; /* Save area 0 - current frame */ + uint sen_tbuf0data1; /* Save area 1 - current frame */ + uint sen_tbuf0rba; /* Internal */ + uint sen_tbuf0crc; /* Internal */ + ushort sen_tbuf0bcnt; /* Internal */ + ushort sen_paddrh; /* physical address (MSB) */ + ushort sen_paddrm; + ushort sen_paddrl; /* physical address (LSB) */ + ushort sen_pper; /* persistence */ + ushort sen_rfbdptr; /* Rx first BD pointer */ + ushort sen_tfbdptr; /* Tx first BD pointer */ + ushort sen_tlbdptr; /* Tx last BD pointer */ + uint sen_tbuf1data0; /* Save area 0 - current frame */ + uint sen_tbuf1data1; /* Save area 1 - current frame */ + uint sen_tbuf1rba; /* Internal */ + uint sen_tbuf1crc; /* Internal */ + ushort sen_tbuf1bcnt; /* Internal */ + ushort sen_txlen; /* Tx Frame length counter */ + ushort sen_iaddr1; /* Individual address filter */ + ushort sen_iaddr2; + ushort sen_iaddr3; + ushort sen_iaddr4; + ushort sen_boffcnt; /* Backoff counter */ + + /* NOTE: Some versions of the manual have the following items + * incorrectly documented. Below is the proper order. + */ + ushort sen_taddrh; /* temp address (MSB) */ + ushort sen_taddrm; + ushort sen_taddrl; /* temp address (LSB) */ +} scc_enet_t; + +/********************************************************************** + * + * Board specific configuration settings. + * + * Please note that we use the presence of a #define SCC_ENET and/or + * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. + **********************************************************************/ + + +/*** ADS *************************************************************/ + +#if defined(CONFIG_MPC860) && defined(CONFIG_ADS) +/* This ENET stuff is for the MPC860ADS with ethernet on SCC1. + */ + +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 + +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0100) +#define PA_ENET_RCLK ((ushort)0x0200) + +#define PB_ENET_TENA ((uint)0x00001000) + +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000002c) + +/* 68160 PHY control */ + +#define PC_ENET_ETHLOOP ((ushort)0x0800) +#define PC_ENET_TPFLDL ((ushort)0x0400) +#define PC_ENET_TPSQEL ((ushort)0x0200) + +#endif /* MPC860ADS */ + +/*** AMX860 **********************************************/ + +#if defined(CONFIG_AMX860) + +/* This ENET stuff is for the AMX860 with ethernet on SCC1. + */ + +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 + +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0400) +#define PA_ENET_RCLK ((ushort)0x0800) + +#define PB_ENET_TENA ((uint)0x00001000) + +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000003e) + +/* 68160 PHY control */ + +#define PB_ENET_ETHLOOP ((uint)0x00020000) +#define PB_ENET_TPFLDL ((uint)0x00010000) +#define PB_ENET_TPSQEL ((uint)0x00008000) +#define PD_ENET_ETH_EN ((ushort)0x0004) + +#endif /* CONFIG_AMX860 */ + +/*** BSEIP **********************************************************/ + +#ifdef CONFIG_BSEIP +/* This ENET stuff is for the MPC823 with ethernet on SCC2. + * This is unique to the BSE ip-Engine board. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0100) +#define PA_ENET_RCLK ((ushort)0x0200) +#define PB_ENET_TENA ((uint)0x00002000) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +/* BSE uses port B and C bits for PHY control also. +*/ +#define PB_BSE_POWERUP ((uint)0x00000004) +#define PB_BSE_FDXDIS ((uint)0x00008000) +#define PC_BSE_LOOPBACK ((ushort)0x0800) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002c00) +#endif /* CONFIG_BSEIP */ + +/*** BSEIP **********************************************************/ + +#ifdef CONFIG_FLAGADM +/* Enet configuration for the FLAGADM */ +/* Enet on SCC2 */ + +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0100) +#define PA_ENET_RCLK ((ushort)0x0400) +#define PB_ENET_TENA ((uint)0x00002000) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00003400) +#endif /* CONFIG_FLAGADM */ + +/*** C2MON **********************************************************/ + +#ifdef CONFIG_C2MON + +# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */ +# error "Ethernet on SCC not supported on C2MON Board!" +# else /* Use FEC for Fast Ethernet */ + +#undef SCC_ENET +#define FEC_ENET + +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ + +#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ + +# endif /* CONFIG_FEC_ENET */ +#endif /* CONFIG_C2MON */ + +/*********************************************************************/ + + +/*** CCM and PCU E ***********************************************/ + +/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */ + +#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM) + +#define FEC_ENET /* use FEC for EThernet */ +#undef SCC_ENET + +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ + +#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ + +#endif /* CONFIG_PCU_E, CONFIG_CCM */ + +/*** ELPT860 *********************************************************/ + +#ifdef CONFIG_ELPT860 +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +# define PROFF_ENET PROFF_SCC1 +# define CPM_CR_ENET CPM_CR_CH_SCC1 +# define SCC_ENET 0 + +# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ +# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ +# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */ + +# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ +# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ +# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ + +/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +# define SICR_ENET_MASK ((uint)0x000000FF) +# define SICR_ENET_CLKRT ((uint)0x00000025) +#endif /* CONFIG_ELPT860 */ + +/*** ESTEEM 192E **************************************************/ +#ifdef CONFIG_ESTEEM192E +/* ESTEEM192E + * This ENET stuff is for the MPC850 with ethernet on SCC2. This + * is very similar to the RPX-Lite configuration. + * Note TENA , LOOPBACK , FDPLEX_DIS on Port B. + */ + +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 + +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0200) +#define PA_ENET_RCLK ((ushort)0x0800) +#define PB_ENET_TENA ((uint)0x00002000) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00003d00) + +#define PB_ENET_LOOPBACK ((uint)0x00004000) +#define PB_ENET_FDPLEX_DIS ((uint)0x00008000) + +#endif + +/*** FADS823 ********************************************************/ + +#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS) +/* This ENET stuff is for the MPC823FADS with ethernet on SCC2. + */ +#ifdef CONFIG_SCC2_ENET +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define CPMVEC_ENET CPMVEC_SCC2 +#endif + +#ifdef CONFIG_SCC1_ENET +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 +#define CPMVEC_ENET CPMVEC_SCC1 +#endif + +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0400) +#define PA_ENET_RCLK ((ushort)0x0200) + +#define PB_ENET_TENA ((uint)0x00002000) + +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002e00) + +#endif /* CONFIG_FADS823FADS */ + +/*** FADS850SAR ********************************************************/ + +#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS) +/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of + * this may be unique to the FADS850SAR configuration. + * Note TENA is on Port B. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */ +#endif /* CONFIG_FADS850SAR */ + +/*** FADS860T********************************************************/ + +#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) +/* + * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1. + */ +#ifdef CONFIG_SCC1_ENET + +#define SCC_ENET 0 + +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 + +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0100) +#define PA_ENET_RCLK ((ushort)0x0200) + +#define PB_ENET_TENA ((uint)0x00001000) + +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000002c) + +#endif /* CONFIG_SCC1_ETHERNET */ + +/* + * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS + * with ethernet on FEC. + */ + +#ifdef CONFIG_FEC_ENET +#define FEC_ENET /* Use FEC for Ethernet */ +#endif /* CONFIG_FEC_ENET */ + +#endif /* CONFIG_FADS && CONFIG_MPC86x */ + +/*** FPS850L, FPS860L ************************************************/ + +#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L) +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC2 use. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002600) +#endif /* CONFIG_FPS850L, CONFIG_FPS860L */ + +/*** GEN860T **********************************************************/ +#if defined(CONFIG_GEN860T) +#undef SCC_ENET +#define FEC_ENET + +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ +#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ +#endif /* CONFIG_GEN860T */ + +/*** GENIETV ********************************************************/ + +#if defined(CONFIG_GENIETV) +/* Ethernet is only on SCC2 */ + +#define CONFIG_SCC2_ENET +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define CPMVEC_ENET CPMVEC_SCC2 + +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ + +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002e00) + +#endif /* CONFIG_GENIETV */ + +/*** GTH ******************************************************/ + +#ifdef CONFIG_GTH +#ifdef CONFIG_FEC_ENET +#define FEC_ENET /* use FEC for EThernet */ +#endif /* CONFIG_FEC_ETHERNET */ + +/* This ENET stuff is for GTH 10 Mbit ( SCC ) */ +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 + +#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ +#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ +#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ +#define PA_ENET_RCLK ((ushort)0x0400) /* PA5 */ + +#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ + +#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ +#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ + +/* NOTE. This is reset for 10Mbit port only */ +#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 */ + +#define SICR_ENET_MASK ((uint)0x000000ff) + +/* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */ +#define SICR_ENET_CLKRT ((uint)0x00000037) + +#endif /* CONFIG_GTH */ + +/*** HERMES-PRO ******************************************************/ + +/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ + +#ifdef CONFIG_HERMES + +#define FEC_ENET /* use FEC for EThernet */ +#undef SCC_ENET + + +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ + +#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ + +#endif /* CONFIG_HERMES */ + +/*** IAD210 **********************************************************/ + +/* The IAD210 uses the FEC on a MPC860P for Ethernet */ + +#if defined(CONFIG_IAD210) + +# define FEC_ENET /* use FEC for Ethernet */ +# undef SCC_ENET + +# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */ +# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */ +# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */ +# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */ +# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */ +# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */ +# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */ +# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */ +# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */ +# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */ +# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */ +# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */ +# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */ + +# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */ + +#endif /* CONFIG_IAD210 */ + +/*** ICU862 **********************************************************/ + +#if defined(CONFIG_ICU862) + +#ifdef CONFIG_FEC_ENET +#define FEC_ENET /* use FEC for EThernet */ +#endif /* CONFIG_FEC_ETHERNET */ + +#endif /* CONFIG_ICU862 */ + +/*** IP860 **********************************************************/ + +#if defined(CONFIG_IP860) +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 +#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ +#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */ + +#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ +#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ +#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ + +#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */ +#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */ + +/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000002C) +#endif /* CONFIG_IP860 */ + +/*** IVMS8 **********************************************************/ + +/* The IVMS8 uses the FEC on a MPC860T for Ethernet */ + +#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) + +#define FEC_ENET /* use FEC for EThernet */ +#undef SCC_ENET + +#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ + +#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ + +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ + +#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ + +#endif /* CONFIG_IVMS8, CONFIG_IVML24 */ + +/*** KUP4K, KUP4X ****************************************************/ +/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */ + +#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) + +#define FEC_ENET /* use FEC for EThernet */ +#undef SCC_ENET + +#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ + +#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ + +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ + +#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ + +#endif /* CONFIG_KUP4K */ + + +/*** LANTEC *********************************************************/ + +#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2 +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC2 use. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + +#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */ +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000FF00) +#define SICR_ENET_CLKRT ((uint)0x00002E00) +#endif /* CONFIG_LANTEC v2 */ + +/*** LWMON **********************************************************/ + +#if defined(CONFIG_LWMON) +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC2 use. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00003E00) +#endif /* CONFIG_LWMON */ + +/*** NX823 ***********************************************/ + +#if defined(CONFIG_NX823) +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ + +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002f00) + +#endif /* CONFIG_NX823 */ + +/*** MBX ************************************************************/ + +#ifdef CONFIG_MBX +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. The TCLK and RCLK seem unique + * to the MBX860 board. Any two of the four available clocks could be + * used, and the MPC860 cookbook manual has an example using different + * clock pins. + */ +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0200) +#define PA_ENET_RCLK ((ushort)0x0800) +#define PC_ENET_TENA ((ushort)0x0001) +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000003d) +#endif /* CONFIG_MBX */ + +/*** MHPC ********************************************************/ + +#if defined(CONFIG_MHPC) +/* This ENET stuff is for the MHPC with ethernet on SCC2. + * Note TENA is on Port B. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ +#endif /* CONFIG_MHPC */ + +/*** NETVIA *******************************************************/ + +/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */ +#if ( defined CONFIG_SVM_SC8xx ) +# ifndef CONFIG_FEC_ENET + +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 + + /* Bits in parallel I/O port registers that have to be set/cleared + * * * * to configure the pins for SCC2 use. + * * * */ +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */ +#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ + +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + * * * */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00003700) + +# else /* Use FEC for Fast Ethernet */ + +#undef SCC_ENET +#define FEC_ENET + +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ + +#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ + +# endif /* CONFIG_FEC_ENET */ +#endif /* CONFIG_SVM_SC8xx */ + + +#if defined(CONFIG_NETVIA) +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC2 use. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ + +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 +# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ +#elif CONFIG_NETVIA_VERSION >= 2 +# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */ +#endif + +#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002f00) + +#endif /* CONFIG_NETVIA */ + +/*** QS850/QS823 ***************************************************/ + +#if defined(CONFIG_QS850) || defined(CONFIG_QS823) +#undef FEC_ENET /* Don't use FEC for EThernet */ + +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 + +#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */ +#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */ +#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */ +#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */ +#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */ +#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */ +#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */ +#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */ +#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */ +#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */ + +/* SCC2 TXCLK from CLK2 + * SCC2 RXCLK from CLK4 + * SCC2 Connected to NMSI */ +#define SICR_ENET_MASK ((uint)0x00007F00) +#define SICR_ENET_CLKRT ((uint)0x00003D00) + +#endif /* CONFIG_QS850/QS823 */ + +/*** QS860T ***************************************************/ + +#ifdef CONFIG_QS860T +#ifdef CONFIG_FEC_ENET +#define FEC_ENET /* use FEC for EThernet */ +#endif /* CONFIG_FEC_ETHERNET */ + +/* This ENET stuff is for GTH 10 Mbit ( SCC ) */ +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 + +#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ +#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ +#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */ +#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ +#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ +#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ + +#define SICR_ENET_MASK ((uint)0x000000ff) +/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */ +#define SICR_ENET_CLKRT ((uint)0x0000003D) + +#endif /* CONFIG_QS860T */ + +/*** RPXCLASSIC *****************************************************/ + +#ifdef CONFIG_RPXCLASSIC + +#ifdef CONFIG_FEC_ENET + +# define FEC_ENET /* use FEC for EThernet */ +# undef SCC_ENET + +#else /* ! CONFIG_FEC_ENET */ + +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0200) +#define PA_ENET_RCLK ((ushort)0x0800) +#define PB_ENET_TENA ((uint)0x00001000) +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000003d) + +#endif /* CONFIG_FEC_ENET */ + +#endif /* CONFIG_RPXCLASSIC */ + +/*** RPXLITE ********************************************************/ + +#ifdef CONFIG_RPXLITE +/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of + * this may be unique to the RPX-Lite configuration. + * Note TENA is on Port B. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0200) +#define PA_ENET_RCLK ((ushort)0x0800) +#if defined(CONFIG_RMU) +#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */ +#else +#define PB_ENET_TENA ((uint)0x00002000) +#endif +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00003d00) +#endif /* CONFIG_RPXLITE */ + +/*** SM850 *********************************************************/ + +/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ + +#ifdef CONFIG_SM850 +#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ +#define CPM_CR_ENET CPM_CR_CH_SCC3 +#define SCC_ENET 2 +#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ +#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ +#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ +#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ + +#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ +#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. + */ +#define SICR_ENET_MASK ((uint)0x00FF0000) +#define SICR_ENET_CLKRT ((uint)0x00260000) +#endif /* CONFIG_SM850 */ + +/*** SPD823TS ******************************************************/ + +#ifdef CONFIG_SPD823TS +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC2 use. + */ +#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */ +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ +#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ +#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002E00) +#endif /* CONFIG_SPD823TS */ + +/*** SXNI855T ******************************************************/ + +#if defined(CONFIG_SXNI855T) + +#ifdef CONFIG_FEC_ENET +#define FEC_ENET /* use FEC for Ethernet */ +#endif /* CONFIG_FEC_ETHERNET */ + +#endif /* CONFIG_SXNI855T */ + +/*** MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI *******************/ + +#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ + defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ + defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \ + defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \ + defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \ + (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2) +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC2 use. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ +#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ +#if defined(CONFIG_R360MPI) +#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ +#endif /* CONFIG_R360MPI */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. + */ +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002600) +#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ + +/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ + +#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ + defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ + defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ + defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) + +# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ + +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 +#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ +#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ +#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ + +#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ +#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ +#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ + +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x00000026) + +# endif /* CONFIG_SCC1_ENET */ + +# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ + +#define FEC_ENET + +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ + +#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ + +# endif /* CONFIG_FEC_ENET */ +#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ + +/*** V37 **********************************************************/ + +#ifdef CONFIG_V37 +/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of + * this may be unique to the Marel V37 configuration. + * Note TENA is on Port B. + */ +#define PROFF_ENET PROFF_SCC2 +#define CPM_CR_ENET CPM_CR_CH_SCC2 +#define SCC_ENET 1 +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0400) +#define PA_ENET_RCLK ((ushort)0x0200) +#define PB_ENET_TENA ((uint)0x00002000) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002e00) +#endif /* CONFIG_V37 */ + + +/*********************************************************************/ + +/* SCC Event register as used by Ethernet. +*/ +#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ +#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* SCC Mode Register (PSMR) as used by Ethernet. +*/ +#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ + +/* Buffer descriptor control/status used by Ethernet receive. +*/ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. +*/ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/* SCC as UART +*/ +typedef struct scc_uart { + sccp_t scc_genscc; + uint scc_res1; /* Reserved */ + uint scc_res2; /* Reserved */ + ushort scc_maxidl; /* Maximum idle chars */ + ushort scc_idlc; /* temp idle counter */ + ushort scc_brkcr; /* Break count register */ + ushort scc_parec; /* receive parity error counter */ + ushort scc_frmec; /* receive framing error counter */ + ushort scc_nosec; /* receive noise counter */ + ushort scc_brkec; /* receive break condition counter */ + ushort scc_brkln; /* last received break length */ + ushort scc_uaddr1; /* UART address character 1 */ + ushort scc_uaddr2; /* UART address character 2 */ + ushort scc_rtemp; /* Temp storage */ + ushort scc_toseq; /* Transmit out of sequence char */ + ushort scc_char1; /* control character 1 */ + ushort scc_char2; /* control character 2 */ + ushort scc_char3; /* control character 3 */ + ushort scc_char4; /* control character 4 */ + ushort scc_char5; /* control character 5 */ + ushort scc_char6; /* control character 6 */ + ushort scc_char7; /* control character 7 */ + ushort scc_char8; /* control character 8 */ + ushort scc_rccm; /* receive control character mask */ + ushort scc_rccr; /* receive control character register */ + ushort scc_rlbc; /* receive last break character */ +} scc_uart_t; + +/* SCC Event and Mask registers when it is used as a UART. +*/ +#define UART_SCCM_GLR ((ushort)0x1000) +#define UART_SCCM_GLT ((ushort)0x0800) +#define UART_SCCM_AB ((ushort)0x0200) +#define UART_SCCM_IDL ((ushort)0x0100) +#define UART_SCCM_GRA ((ushort)0x0080) +#define UART_SCCM_BRKE ((ushort)0x0040) +#define UART_SCCM_BRKS ((ushort)0x0020) +#define UART_SCCM_CCR ((ushort)0x0008) +#define UART_SCCM_BSY ((ushort)0x0004) +#define UART_SCCM_TX ((ushort)0x0002) +#define UART_SCCM_RX ((ushort)0x0001) + +/* The SCC PSMR when used as a UART. +*/ +#define SCU_PSMR_FLC ((ushort)0x8000) +#define SCU_PSMR_SL ((ushort)0x4000) +#define SCU_PSMR_CL ((ushort)0x3000) +#define SCU_PSMR_UM ((ushort)0x0c00) +#define SCU_PSMR_FRZ ((ushort)0x0200) +#define SCU_PSMR_RZS ((ushort)0x0100) +#define SCU_PSMR_SYN ((ushort)0x0080) +#define SCU_PSMR_DRT ((ushort)0x0040) +#define SCU_PSMR_PEN ((ushort)0x0010) +#define SCU_PSMR_RPM ((ushort)0x000c) +#define SCU_PSMR_REVP ((ushort)0x0008) +#define SCU_PSMR_TPM ((ushort)0x0003) +#define SCU_PSMR_TEVP ((ushort)0x0003) + +/* CPM Transparent mode SCC. + */ +typedef struct scc_trans { + sccp_t st_genscc; + uint st_cpres; /* Preset CRC */ + uint st_cmask; /* Constant mask for CRC */ +} scc_trans_t; + +#define BD_SCC_TX_LAST ((ushort)0x0800) + +/* IIC parameter RAM. +*/ +typedef struct iic { + ushort iic_rbase; /* Rx Buffer descriptor base address */ + ushort iic_tbase; /* Tx Buffer descriptor base address */ + u_char iic_rfcr; /* Rx function code */ + u_char iic_tfcr; /* Tx function code */ + ushort iic_mrblr; /* Max receive buffer length */ + uint iic_rstate; /* Internal */ + uint iic_rdp; /* Internal */ + ushort iic_rbptr; /* Internal */ + ushort iic_rbc; /* Internal */ + uint iic_rxtmp; /* Internal */ + uint iic_tstate; /* Internal */ + uint iic_tdp; /* Internal */ + ushort iic_tbptr; /* Internal */ + ushort iic_tbc; /* Internal */ + uint iic_txtmp; /* Internal */ + uint iic_res; /* reserved */ + ushort iic_rpbase; /* Relocation pointer */ + ushort iic_res2; /* reserved */ +} iic_t; + +/* SPI parameter RAM. +*/ +typedef struct spi { + ushort spi_rbase; /* Rx Buffer descriptor base address */ + ushort spi_tbase; /* Tx Buffer descriptor base address */ + u_char spi_rfcr; /* Rx function code */ + u_char spi_tfcr; /* Tx function code */ + ushort spi_mrblr; /* Max receive buffer length */ + uint spi_rstate; /* Internal */ + uint spi_rdp; /* Internal */ + ushort spi_rbptr; /* Internal */ + ushort spi_rbc; /* Internal */ + uint spi_rxtmp; /* Internal */ + uint spi_tstate; /* Internal */ + uint spi_tdp; /* Internal */ + ushort spi_tbptr; /* Internal */ + ushort spi_tbc; /* Internal */ + uint spi_txtmp; /* Internal */ + uint spi_res; + ushort spi_rpbase; /* Relocation pointer */ + ushort spi_res2; +} spi_t; + +/* SPI Mode register. +*/ +#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ +#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ +#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ +#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ +#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ +#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ +#define SPMODE_EN ((ushort)0x0100) /* Enable */ +#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ +#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ + +#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) +#define SPMODE_PM(x) ((x) &0xF) + +/* HDLC parameter RAM. +*/ + +typedef struct hdlc_pram_s { + /* + * SCC parameter RAM + */ + ushort rbase; /* Rx Buffer descriptor base address */ + ushort tbase; /* Tx Buffer descriptor base address */ + uchar rfcr; /* Rx function code */ + uchar tfcr; /* Tx function code */ + ushort mrblr; /* Rx buffer length */ + ulong rstate; /* Rx internal state */ + ulong rptr; /* Rx internal data pointer */ + ushort rbptr; /* rb BD Pointer */ + ushort rcount; /* Rx internal byte count */ + ulong rtemp; /* Rx temp */ + ulong tstate; /* Tx internal state */ + ulong tptr; /* Tx internal data pointer */ + ushort tbptr; /* Tx BD pointer */ + ushort tcount; /* Tx byte count */ + ulong ttemp; /* Tx temp */ + ulong rcrc; /* temp receive CRC */ + ulong tcrc; /* temp transmit CRC */ + /* + * HDLC specific parameter RAM + */ + uchar res[4]; /* reserved */ + ulong c_mask; /* CRC constant */ + ulong c_pres; /* CRC preset */ + ushort disfc; /* discarded frame counter */ + ushort crcec; /* CRC error counter */ + ushort abtsc; /* abort sequence counter */ + ushort nmarc; /* nonmatching address rx cnt */ + ushort retrc; /* frame retransmission cnt */ + ushort mflr; /* maximum frame length reg */ + ushort max_cnt; /* maximum length counter */ + ushort rfthr; /* received frames threshold */ + ushort rfcnt; /* received frames count */ + ushort hmask; /* user defined frm addr mask */ + ushort haddr1; /* user defined frm address 1 */ + ushort haddr2; /* user defined frm address 2 */ + ushort haddr3; /* user defined frm address 3 */ + ushort haddr4; /* user defined frm address 4 */ + ushort tmp; /* temp */ + ushort tmp_mb; /* temp */ +} hdlc_pram_t; + +/* CPM interrupts. There are nearly 32 interrupts generated by CPM + * channels or devices. All of these are presented to the PPC core + * as a single interrupt. The CPM interrupt handler dispatches its + * own handlers, in a similar fashion to the PPC core handler. We + * use the table as defined in the manuals (i.e. no special high + * priority and SCC1 == SCCa, etc...). + */ +#define CPMVEC_NR 32 +#define CPMVEC_OFFSET 0x00010000 +#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) +#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) +#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) +#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) +#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) +#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) +#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) +#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) +#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) +#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) +#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) +#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) +#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) +#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) +#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) +#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) +#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) +#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) +#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) + +extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); + +/* CPM interrupt configuration vector. +*/ +#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ +#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ +#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ +#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ +#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ +#define CICR_IEN ((uint)0x00000080) /* Int. enable */ +#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ +#endif /* __CPM_8XX__ */ diff --git a/include/configs/A3000.h b/include/configs/A3000.h new file mode 100644 index 0000000..ca9592c --- /dev/null +++ b/include/configs/A3000.h @@ -0,0 +1,324 @@ +/* + * (C) Copyright 2001, 2002, 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ +/* + * Configuration settings for the A-3000 board (Artis Microsystems Inc.). + * http://artismicro.com + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_A3000 1 + + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 5 + +#if 0 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_FLASH | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_NET | \ + CFG_CMD_PCI ) +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#include + + +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "A3000> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 8 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00400000 /* Default load address */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +/* #define CONFIG_TULIP */ +/* #define CONFIG_EEPRO100 */ +#define CONFIG_NATSEMI + +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET0_MEMADDR 0x80000000 +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET1_MEMADDR 0x81000000 +#define PCI_ENET2_IOADDR 0x82000000 +#define PCI_ENET2_MEMADDR 0x82000000 +#define PCI_ENET3_IOADDR 0x83000000 +#define PCI_ENET3_MEMADDR 0x83000000 + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ +#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ +#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM +#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } + +/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the + * reset vector is actually located at FFB00100, but the 8245 + * takes care of us. + */ +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + + /* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */ + + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* #define CFG_MONITOR_BASE TEXT_BASE */ +/*#define CFG_GBL_DATA_SIZE 256*/ +#define CFG_GBL_DATA_SIZE 128 +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#define CFG_HZ 1000 + + /* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 7 +#define CFG_ROMFAL 11 +#define CFG_DBUS_SIZE 0x3 + + /* Bit-field values for MCCR2. + */ +#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ +#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ + + /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 121 + + /* Bit-field values for MCCR3. + */ +#define CFG_REFREC 8 /* Refresh to activate interval */ + + /* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ +#define CFG_ACTORW 3 /* FIXME was 2 */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + +#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ + +#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0xff + +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors per flash */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + + + /* Warining: environment is not EMBEDDED in the U-Boot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFFFE0000 +#define CFG_ENV_SIZE 0x00020000 /* Size of the Environment */ +#define CFG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h new file mode 100644 index 0000000..821efe5 --- /dev/null +++ b/include/configs/ADCIOP.h @@ -0,0 +1,210 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ +#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_CPUCLOCK 66 +#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ + +#undef CONFIG_BOOTARGS + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_IPADDR 10.0.18.222 +#define CONFIG_SERVERIP 10.0.18.190 + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_ASKENV ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0002 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0000 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0004 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 1 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_NVRAM_BASE_ADDR 0x10000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_ENV_SIZE 0x0400 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/ + +#else /* Use FLASH for environment variables */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ + +#define CFG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ + +#endif + +/*----------------------------------------------------------------------- + * PCI stuff + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP + +#define CFG_ETH_DEV_FN 0x0000 +#define CFG_ETH_IOBASE 0x0fff0000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */ + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h new file mode 100644 index 0000000..2efca10 --- /dev/null +++ b/include/configs/ADNPESC1.h @@ -0,0 +1,694 @@ +/* + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*********************************************************************** + * Include the whole NIOS CPU configuration. + * + * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! + * + ***********************************************************************/ + +#if defined(CONFIG_NIOS_BASE_32) +#include +#else +#error *** CFG_ERROR: you have to setup right NIOS CPU configuration +#endif + +/*------------------------------------------------------------------------ + * BOARD/CPU -- TOP-LEVEL + *----------------------------------------------------------------------*/ +#define CONFIG_NIOS 1 /* NIOS-32 core */ +#define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */ +#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */ +#define CFG_HZ 1000 /* 1 msec time tick */ +#undef CFG_CLKS_IN_HZ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ + +/*------------------------------------------------------------------------ + * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_SDRAM_SIZE != 0) + +#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE +#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE + +#else +#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config +#endif + +#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE) + +#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE +#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE + +#else + +#undef CFG_SRAM_BASE +#undef CFG_SRAM_SIZE + +#endif + +#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION - For the most part, you can put things pretty + * much anywhere. This is pretty flexible for Nios. So here we make some + * arbitrary choices & assume that the monitor is placed at the end of + * a memory resource (so you must make sure TEXT_BASE is chosen + * appropriately -- this is very important if you plan to move your + * memory to another place as configured at this time !!!). + * + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_FLASH_SIZE != 0) + +#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE +#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size */ + +#else +#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config +#endif + +/*------------------------------------------------------------------------ + * ENVIRONMENT + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_FLASH_SIZE != 0) + +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ + +/* Mem addr of environment */ +#if defined(CONFIG_NIOS_BASE_32) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#else +#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR +#endif + +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ + +#else +#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */ +#endif + +/*------------------------------------------------------------------------ + * NIOS APPLICATION CODE BASE AREA + *----------------------------------------------------------------------*/ +#if ((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000) +#define CFG_ADNPESC1_UPDATE_LOAD_ADDR "0x2000100" +#define CFG_ADNPESC1_NIOS_APPL_ENTRY "0x1050000" +#define CFG_ADNPESC1_NIOS_APPL_IDENT "0x105000c" +#define CFG_ADNPESC1_NIOS_APPL_END "0x11fffff" +#define CFG_ADNPESC1_FILESYSTEM_BASE "0x1200000" +#define CFG_ADNPESC1_FILESYSTEM_END "0x17fffff" +#else +#error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h +#endif +#define CFG_ADNPESC1_NIOS_IDENTIFIER "Nios" + +/*------------------------------------------------------------------------ + * BOOT ENVIRONMENT + *----------------------------------------------------------------------*/ +#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ +#define CFG_ADNPESC1_SLED_BOOT_OFF "sled boot off; " +#define CFG_ADNPESC1_SLED_RED_BLINK "sled red blink; " +#else +#define CFG_ADNPESC1_SLED_BOOT_OFF +#define CFG_ADNPESC1_SLED_RED_BLINK +#endif + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND \ + "if itest.s *$appl_ident_addr == \"$appl_ident_str\"; " \ + "then " \ + "wd off; " \ + CFG_ADNPESC1_SLED_BOOT_OFF \ + "go $appl_entry_addr; " \ + "else " \ + CFG_ADNPESC1_SLED_RED_BLINK \ + "echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\ + "echo *** invalid application at $appl_entry_addr; " \ + "echo *** stop bootup...; " \ + "fi" + +/*------------------------------------------------------------------------ + * EXTRA ENVIRONMENT + *----------------------------------------------------------------------*/ +#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ +#define CFG_ADNPESC1_SLED_YELLO_ON "sled yellow on; " +#define CFG_ADNPESC1_SLED_YELLO_OFF "sled yellow off; " +#else +#define CFG_ADNPESC1_SLED_YELLO_ON +#define CFG_ADNPESC1_SLED_YELLO_OFF +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_allowed=0\0" \ + "update_load_addr=" CFG_ADNPESC1_UPDATE_LOAD_ADDR "\0" \ + "appl_entry_addr=" CFG_ADNPESC1_NIOS_APPL_ENTRY "\0" \ + "appl_end_addr=" CFG_ADNPESC1_NIOS_APPL_END "\0" \ + "appl_ident_addr=" CFG_ADNPESC1_NIOS_APPL_IDENT "\0" \ + "appl_ident_str=" CFG_ADNPESC1_NIOS_IDENTIFIER "\0" \ + "appl_name=ADNPESC1/base32/linux.bin\0" \ + "appl_update=" \ + "if itest.b $update_allowed != 0; " \ + "then " \ + CFG_ADNPESC1_SLED_YELLO_ON \ + "tftp $update_load_addr $appl_name; " \ + "protect off $appl_entry_addr $appl_end_addr; " \ + "era $appl_entry_addr $appl_end_addr; " \ + "cp.b $update_load_addr $appl_entry_addr $filesize; "\ + CFG_ADNPESC1_SLED_YELLO_OFF \ + "else " \ + "echo *** update not allowed (update_allowed=$update_allowed); "\ + "fi\0" \ + "fs_base_addr=" CFG_ADNPESC1_FILESYSTEM_BASE "\0" \ + "fs_end_addr=" CFG_ADNPESC1_FILESYSTEM_END "\0" \ + "fs_name=ADNPESC1/base32/romfs.img\0" \ + "fs_update=" \ + "if itest.b $update_allowed != 0; " \ + "then " \ + CFG_ADNPESC1_SLED_YELLO_ON \ + "tftp $update_load_addr $fs_name; " \ + "protect off $fs_base_addr $fs_end_addr; " \ + "era $fs_base_addr $fs_end_addr; " \ + "cp.b $update_load_addr $fs_base_addr $filesize; "\ + CFG_ADNPESC1_SLED_YELLO_OFF \ + "else " \ + "echo *** update not allowed (update_allowed=$update_allowed); "\ + "fi\0" \ + "uboot_name=ADNPESC1/base32/u-boot.bin\0" \ + "uboot_loadnrun=" \ + "if ping $serverip; " \ + "then " \ + CFG_ADNPESC1_SLED_YELLO_ON \ + "tftp $update_load_addr $uboot_name; " \ + "wd off; " \ + "go $update_load_addr; " \ + "else " \ + "echo *** missing connection to $serverip; " \ + "echo *** check your network and try again...; "\ + "fi\0" + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_UART_NUMS != 0) + +#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */ + +#if (CFG_NIOS_CPU_UART0_BR != 0) +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR +#else +#undef CFG_NIOS_FIXEDBAUD +#define CONFIG_BAUDRATE 115200 +#endif + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#else +#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config +#endif + +/*------------------------------------------------------------------------ + * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, + * so an avalon bus timer is required. + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER) + +#if (CFG_NIOS_CPU_TICK_TIMER == 0) + +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */ +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ + +#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ + +#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ) +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ) +#else +#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ +#endif + +#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ + +#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */ + +#if (CFG_HZ <= 1000) +#define CFG_NIOS_TMRMS (1000 / CFG_HZ) +#else +#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 +#endif + +#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) + +#else +#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct +#endif + +#elif (CFG_NIOS_CPU_TICK_TIMER == 1) + +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */ +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ + +#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ + +#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ) +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ) +#else +#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ +#endif + +#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ + +#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */ + +#if (CFG_HZ <= 1000) +#define CFG_NIOS_TMRMS (1000 / CFG_HZ) +#else +#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 +#endif + +#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) + +#else +#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct +#endif + +#endif /* CFG_NIOS_CPU_TICK_TIMER */ + +#else +#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config +#endif + +/*------------------------------------------------------------------------ + * WATCHDOG (or better MAX823 supervisory circuite access) + *----------------------------------------------------------------------*/ +#define CONFIG_HW_WATCHDOG 1 /* board specific WD */ + +#ifdef CONFIG_HW_WATCHDOG + +/* MAX823 supervisor -- watchdog enable port at: */ +#if (CFG_NIOS_CPU_WDENA_PIO == 0) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */ +#elif (CFG_NIOS_CPU_WDENA_PIO == 1) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */ +#elif (CFG_NIOS_CPU_WDENA_PIO == 2) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */ +#elif (CFG_NIOS_CPU_WDENA_PIO == 3) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */ +#elif (CFG_NIOS_CPU_WDENA_PIO == 4) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */ +#elif (CFG_NIOS_CPU_WDENA_PIO == 5) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */ +#elif (CFG_NIOS_CPU_WDENA_PIO == 6) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */ +#elif (CFG_NIOS_CPU_WDENA_PIO == 7) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */ +#elif (CFG_NIOS_CPU_WDENA_PIO == 8) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */ +#elif (CFG_NIOS_CPU_WDENA_PIO == 9) +#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */ +#else +#error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config +#endif + +/* MAX823 supervisor -- watchdog trigger port at: */ +#if (CFG_NIOS_CPU_WDTOG_PIO == 0) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */ +#elif (CFG_NIOS_CPU_WDTOG_PIO == 1) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */ +#elif (CFG_NIOS_CPU_WDTOG_PIO == 2) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */ +#elif (CFG_NIOS_CPU_WDTOG_PIO == 3) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */ +#elif (CFG_NIOS_CPU_WDTOG_PIO == 4) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */ +#elif (CFG_NIOS_CPU_WDTOG_PIO == 5) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */ +#elif (CFG_NIOS_CPU_WDTOG_PIO == 6) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */ +#elif (CFG_NIOS_CPU_WDTOG_PIO == 7) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */ +#elif (CFG_NIOS_CPU_WDTOG_PIO == 8) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */ +#elif (CFG_NIOS_CPU_WDTOG_PIO == 9) +#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */ +#else +#error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config +#endif + +#if defined(CONFIG_NIOS_BASE_32) /* NIOS CPU specifics */ +#define CONFIG_HW_WDENA_BIT 0 /* WD enable @ Bit 0 */ +#define CONFIG_HW_WDTOG_BIT 0 /* WD trigger @ Bit 0 */ +#define CONFIG_HW_WDPORT_WRONLY 1 /* each WD port wr/only*/ +#else +#error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h +#endif + +#endif /* CONFIG_HW_WATCHDOG */ + +/*------------------------------------------------------------------------ + * SERIAL PERIPHAREL INTERFACE + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_SPI_NUMS == 1) + +#define CONFIG_NIOS_SPI 1 /* SPI support active */ +#define CFG_NIOS_SPIBASE CFG_NIOS_CPU_SPI0 +#define CFG_NIOS_SPIBITS CFG_NIOS_CPU_SPI0_BITS + +#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */ +#define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */ + +#define __SPI_CMD_OFF 0 /* allow default commands: */ + /* CFG_CMD_SPI */ + /* CFG_CMD_DATE */ + +#else +#undef CONFIG_NIOS_SPI /* NO SPI support */ +#define __SPI_CMD_OFF ( CFG_CMD_SPI \ + | CFG_CMD_DATE \ + ) +#endif + +/*------------------------------------------------------------------------ + * Ethernet -- needs work! + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_LAN_NUMS == 1) + +#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ + +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) + +#if (CFG_NIOS_CPU_LAN0_BUSW == 32) +#define CONFIG_SMC_USE_32_BIT 1 +#else /* no */ +#undef CONFIG_SMC_USE_32_BIT +#endif + +#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ + + /********************************************/ + /* !!! CS8900 is __not__ tested on NIOS !!! */ + /********************************************/ +#define CONFIG_DRIVER_CS8900 /* Using CS8900 */ +#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) + +#if (CFG_NIOS_CPU_LAN0_BUSW == 32) +#undef CS8900_BUS16 +#define CS8900_BUS32 1 +#else /* no */ +#define CS8900_BUS16 1 +#undef CS8900_BUS32 +#endif + +#else +#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config +#endif + +#define CONFIG_ETHADDR 02:80:ae:20:60:6f +#define CONFIG_NETMASK 255.255.255.248 +#define CONFIG_IPADDR 192.168.161.84 +#define CONFIG_SERVERIP 192.168.161.85 + +#else +#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h +#endif + +/*------------------------------------------------------------------------ + * STATUS LEDs + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO) + +#if (CFG_NIOS_CPU_LED_PIO == 0) + +#define STATUS_LED_BASE CFG_NIOS_CPU_PIO0 +#define STATUS_LED_BITS CFG_NIOS_CPU_PIO0_BITS +#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +#if (CFG_NIOS_CPU_PIO0_TYPE == 1) +#define STATUS_LED_WRONLY 1 +#else +#undef STATUS_LED_WRONLY +#endif + +#elif (CFG_NIOS_CPU_LED_PIO == 1) + +#define STATUS_LED_BASE CFG_NIOS_CPU_PIO1 +#define STATUS_LED_BITS CFG_NIOS_CPU_PIO1_BITS +#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +#if (CFG_NIOS_CPU_PIO1_TYPE == 1) +#define STATUS_LED_WRONLY 1 +#else +#undef STATUS_LED_WRONLY +#endif + +#elif (CFG_NIOS_CPU_LED_PIO == 2) + +#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2 +#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS +#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +#if (CFG_NIOS_CPU_PIO2_TYPE == 1) +#define STATUS_LED_WRONLY 1 +#else +#undef STATUS_LED_WRONLY +#endif + +#elif (CFG_NIOS_CPU_LED_PIO == 3) + +#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 4) + +#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 5) + +#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 6) + +#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 7) + +#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 8) + +#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 9) + +#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h + +#else +#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case +#endif + +#define CONFIG_STATUS_LED 1 /* enable status led driver */ + +#define STATUS_LED_BIT (1 << 0) /* LED[0] */ +#define STATUS_LED_STATE STATUS_LED_BLINKING +#define STATUS_LED_BOOT_STATE STATUS_LED_OFF +#define STATUS_LED_PERIOD (CFG_HZ / 2) /* ca. 1 Hz */ +#define STATUS_LED_BOOT 0 /* boot LED */ + +#if (STATUS_LED_BITS > 1) +#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CFG_HZ / 10) /* ca. 5 Hz */ +#define STATUS_LED_RED 1 /* fail LED */ +#endif + +#if (STATUS_LED_BITS > 2) +#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ +#define STATUS_LED_STATE2 STATUS_LED_OFF +#define STATUS_LED_PERIOD2 (CFG_HZ / 2) /* ca. 1 Hz */ +#define STATUS_LED_YELLOW 2 /* info LED */ +#endif + +#if (STATUS_LED_BITS > 3) +#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ +#define STATUS_LED_STATE3 STATUS_LED_OFF +#define STATUS_LED_PERIOD3 (CFG_HZ / 2) /* ca. 1 Hz */ +#define STATUS_LED_GREEN 3 /* info LED */ +#endif + +#define STATUS_LED_PAR 1 /* makes status_led.h happy */ + +#endif /* CFG_NIOS_CPU_PIO_NUMS */ + +/*------------------------------------------------------------------------ + * Diagnostics / Power On Self Tests + *----------------------------------------------------------------------*/ +#define CONFIG_POST CFG_POST_RTC +#define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_CACHE | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_MMC | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_SCSI | \ + CFG_CMD_VFD | \ + CFG_CMD_USB | \ + CFG_CMD_XIMG | \ + __SPI_CMD_OFF ) ) + + +#include + +/*------------------------------------------------------------------------ + * KGDB + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 9600 +#endif + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_HUSH_PARSER 1 /* use "hush" command parser + undef to save memory */ +#define CFG_PROMPT "ADNPESC1 > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 64 /* max number of command args*/ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "[]> " +#endif + +/* Default load address */ +#if (CFG_SRAM_SIZE != 0) + +/* default in SRAM */ +#define CFG_LOAD_ADDR CFG_SRAM_BASE + +#elif (CFG_SDRAM_SIZE != 0) + +/* default in SDRAM */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#if 1 +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) +#else +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x400000) +#endif +#else +#define CFG_LOAD_ADDR CFG_SDRAM_BASE +#endif + +#else +#undef CFG_LOAD_ADDR /* force error break */ +#endif + + +/* MEM test area */ +#if (CFG_SDRAM_SIZE != 0) + +/* SDRAM begin to stack area (1MB stack) */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#if 0 +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) +#else +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x400000) +#endif +#else +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#endif + +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) + +#else +#undef CFG_MEMTEST_START /* force error break */ +#undef CFG_MEMTEST_END +#endif + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "" +#define MTDPARTS_DEFAULT "" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h new file mode 100644 index 0000000..55210eb --- /dev/null +++ b/include/configs/ADNPESC1_base_32.h @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_ADNPESC1_BASE_32_H +#define __CONFIG_ADNPESC1_BASE_32_H + +/* + * NIOS CPU configuration. (PART OF configs/ADNPESC1.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be undefined or defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #undef CFG_NIOS_CPU_OCI_BASE + * #undef CFG_NIOS_CPU_OCI_SIZE + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (0) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x03000000 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x02000000 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* The offset address in flash to check for the Nios signature "Ni". + * (see GM_FlashExec in germs_monitor.s) */ +#define CFG_NIOS_CPU_EXES_OFFS 0x0C + +/* on-chip extensions */ +#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */ +#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */ +#undef CFG_NIOS_CPU_OCI_SIZE /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 1 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_UART1 0x00000820 /* UART1 addr */ +#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */ +#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* serial peripheral i/o */ +#define CFG_NIOS_CPU_SPI_NUMS 1 /* number of spis */ + +#define CFG_NIOS_CPU_SPI0 0x000008c0 /* SPI0 addr */ +#define CFG_NIOS_CPU_SPI0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_SPI0_BITS 16 /* data bit */ +#define CFG_NIOS_CPU_SPI0_MA 1 /* is master: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_SPI0_SLN 1 /* num slaves */ +#define CFG_NIOS_CPU_SPI0_TCLK 250000 /* clock (Hz) */ +#define CFG_NIOS_CPU_SPI0_TDELAY 2 /* delay (usec) */ +#define CFG_NIOS_CPU_SPI0_FB 0 /* first bit msb(0) */ + /* lsb(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 14 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ +#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 8 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 8 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO2 0x00000880 /* PIO2 addr */ +#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO2_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO2_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */ +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */ +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO4 0x000008a0 /* PIO4 addr */ +#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO4_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO5 0x000008b0 /* PIO5 addr */ +#undef CFG_NIOS_CPU_PIO5_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO5_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO5_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO5_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO5_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO6 0x00000900 /* PIO6 addr */ +#define CFG_NIOS_CPU_PIO6_IRQ 20 /* IRQ */ +#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO6_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO6_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO6_EDGE 2 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO6_ITYPE 1 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO7 0x00000910 /* PIO7 addr */ +#define CFG_NIOS_CPU_PIO7_IRQ 31 /* IRQ */ +#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO7_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO7_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO7_EDGE 2 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO7_ITYPE 1 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO8 0x00000920 /* PIO8 addr */ +#define CFG_NIOS_CPU_PIO8_IRQ 32 /* IRQ */ +#define CFG_NIOS_CPU_PIO8_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO8_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO8_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO8_EDGE 2 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO8_ITYPE 1 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO9 0x00000930 /* PIO9 addr */ +#define CFG_NIOS_CPU_PIO9_IRQ 33 /* IRQ */ +#define CFG_NIOS_CPU_PIO9_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO9_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO9_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO9_EDGE 2 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO9_ITYPE 1 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO10 0x00000940 /* PIO10 addr */ +#define CFG_NIOS_CPU_PIO10_IRQ 34 /* IRQ */ +#define CFG_NIOS_CPU_PIO10_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO10_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO10_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO10_EDGE 2 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO10_ITYPE 1 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO11 0x00000950 /* PIO11 addr */ +#define CFG_NIOS_CPU_PIO11_IRQ 35 /* IRQ */ +#define CFG_NIOS_CPU_PIO11_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO11_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO11_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO11_EDGE 2 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO11_ITYPE 1 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO12 0x00000960 /* PIO12 addr */ +#define CFG_NIOS_CPU_PIO12_IRQ 36 /* IRQ */ +#define CFG_NIOS_CPU_PIO12_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO12_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO12_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO12_EDGE 2 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO12_ITYPE 1 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO13 0x00000970 /* PIO113 addr */ +#define CFG_NIOS_CPU_PIO13_IRQ 37 /* IRQ */ +#define CFG_NIOS_CPU_PIO13_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO13_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO13_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO13_EDGE 2 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO13_ITYPE 1 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */ + +#define CFG_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */ +#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ + +#define CFG_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */ +#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ + +/* memory accessibility */ +#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ +#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x02000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x01000000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS (0) /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 16 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: openmac(2) */ + /* ex: alteramac(3) */ + +/* external extension */ +#define CFG_NIOS_CPU_CS0_BASE 0x40000000 /* board EXT0 addr */ +#define CFG_NIOS_CPU_CS0_SIZE (16*1024*1024) /* max. 16 MB size */ + +#define CFG_NIOS_CPU_CS1_BASE 0x41000000 /* board EXT1 addr */ +#define CFG_NIOS_CPU_CS1_SIZE (16*1024*1024) /* max. 16 MB size */ + +#define CFG_NIOS_CPU_CS2_BASE 0x42000000 /* board EXT2 addr */ +#define CFG_NIOS_CPU_CS2_SIZE (16*1024*1024) /* max. 16 MB size */ + +#define CFG_NIOS_CPU_CS3_BASE 0x43000000 /* board EXT3 addr */ +#define CFG_NIOS_CPU_CS3_SIZE (16*1024*1024) /* max. 16 MB size */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ +#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ + +#define CFG_NIOS_CPU_PORTA_PIO 0 /* PIO0: Port A */ +#define CFG_NIOS_CPU_PORTB_PIO 1 /* PIO1: Port D */ +#define CFG_NIOS_CPU_PORTC_PIO 2 /* PIO2: Port C */ +#define CFG_NIOS_CPU_RCM_PIO 3 /* PIO3: RCM jumper */ +#define CFG_NIOS_CPU_WDENA_PIO 4 /* PIO4: watchdog enable*/ +#define CFG_NIOS_CPU_WDTOG_PIO 5 /* PIO5: watchdog trigg.*/ + +/* PIOx: LED bar */ +#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ +#define CFG_NIOS_CPU_LED_PIO CFG_NIOS_CPU_PORTA_PIO +#else +#undef CFG_NIOS_CPU_LED_PIO /* no LED bar */ +#endif + +#endif /* __CONFIG_ADNPESC1_BASE_32_H */ diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h new file mode 100644 index 0000000..df20965 --- /dev/null +++ b/include/configs/ADS860.h @@ -0,0 +1,52 @@ +/* + * A collection of structures, addresses, and values associated with + * the Motorola 860 ADS board. Copied from the MBX stuff. + * Magnus Damm added defines for 8xxrom and extended bd_info. + * Helmut Buchsbaum added bitvalues for BCSRx + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * Values common to all FADS family boards are in board/fads/fads.h + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Board type */ +#define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */ + +/* Processor type */ +#define CONFIG_MPC860 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 38400 /* Console baudrate */ + +#if 0 +#define CFG_8XX_FACT 1526 /* 32.768 kHz crystal on XTAL/EXTAL */ +#else +#define CFG_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ +#endif + +#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +#define CONFIG_DRAM_50MHZ 1 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_PCMCIA \ + | CFG_CMD_PING \ + ) + + +#include "fads.h" + +#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h new file mode 100644 index 0000000..14d56bf --- /dev/null +++ b/include/configs/AMX860.h @@ -0,0 +1,297 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 +#define CONFIG_AMX860 1 + +#undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */ +#undef CONFIG_8xx_CONS_SMC2 +#define CONFIG_8xx_CONS_SCC2 1 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ + +#define MPC8XX_FACT 10 /* Multiply by 10 */ +#define MPC8XX_XIN 5000000 /* 5 MHz in */ +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" /* autoboot command */ + +#undef CONFIG_BOOTARGS + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ +#endif + + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * U-Boot for AMX board supports two types of memory extension + * modules: one that provides 4 MB flash memory, and another one with + * 16 MB EDO DRAM. + * + * The flash module swaps the CS0 and CS1 signals: if the module is + * installed, CS0 is connected to Flash on the module and CS1 is + * connected to the on-board Flash. This means that you must intall + * U-Boot when the Flash module is plugged in, if you plan to use + * it. + * + * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT + * must be defined. The DRAM module uses CS1. + * + * Only one of these modules may be installed at a time. If U-Boot + * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not + * work if the Flash extension module is installed instead of the + * DRAM module. + */ +#define CONFIG_AMX_RAM_EXT /* 16Mb Ext. DRAM module support */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + * + * Use 4 MB for without and 8 MB with 16 MB DRAM extension module + * (CONFIG_AMX_RAM_EXT) + */ +#ifdef CONFIG_AMX_RAM_EXT +# define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#else +# define CFG_BOOTMAPSZ (4 << 20) /* Initial Memory map for Linux */ +#endif +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control (15-29) + */ +#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) + +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#ifndef CONFIG_AMX_RAM_EXT +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ +#endif + +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ +/* 0x00000800 0x00000400 0x00000100 0x00000030 0x00000004 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) + +#define CFG_OR0_PRELIM 0xFFC00954 /* Real values for the board */ +#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */ + +#ifndef CONFIG_AMX_RAM_EXT +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM 0xFFC00954 /* Real values for the board */ +#define CFG_BR1_PRELIM 0x60000001 /* Real values for the board */ +#endif + +/* DSP ("Glue") Xilinx */ +#define CFG_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */ +#define CFG_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h new file mode 100644 index 0000000..ba4b1a2 --- /dev/null +++ b/include/configs/AP1000.h @@ -0,0 +1,249 @@ +/* + * AMIRIX.h: AMIRIX specific config options + * + * Author : Frank Smith (smith at amirix dot com) + * + * Derived from : other configuration header files in this tree + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#undef DEBUG + +#define CONFIG_405 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ + +#define CONFIG_AP1000 1 /* ...on an AP1000 board */ + +#define CONFIG_PCI 1 + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT "0> " +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CONFIG_COMMAND_EDIT 1 +#define CONFIG_COMMAND_HISTORY 1 +#define CONFIG_COMPLETE_ADDRESSES 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_FLASH_USE_BUFFER_WRITE + +#ifdef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#else +#ifdef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM +#endif +#endif + +#define CONFIG_BAUDRATE 57600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_BOOTCOMMAND "" /* autoboot command */ + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +#define CONFIG_BOOTARGS "console=ttyS0,57600" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_IRQ | \ + CFG_CMD_MVENV | \ + CFG_CMD_PCI | \ + CFG_CMD_PING \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SYS_CLK_FREQ 30000000 + +#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */ +#define CFG_PBSIZE (CFG_CBSIZE+4+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ + +#define CFG_NS16550_CLK 40000000 +#define CFG_DUART_CHAN 0 +#define CFG_NS16550_COM1 (0x4C000000 + 0x1000) +#define CFG_NS16550_COM2 (0x4C800000 + 0x1000) +#define CFG_NS16550_REG_SIZE 4 +#define CFG_NS16550 1 +#define CFG_INIT_CHAN1 1 +#define CFG_INIT_CHAN2 0 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x00200000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI 1 +#define CFG_PROGFLASH_BASE CFG_FLASH_BASE +#define CFG_CONFFLASH_BASE 0x24000000 + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ + +/* BEG ENVIRONNEMENT FLASH */ +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */ +#endif +/* END ENVIRONNEMENT FLASH */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +#define CFG_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* JFFS2 stuff */ + +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +#define CFG_JFFS2_FIRST_SECTOR 1 + +#define CONFIG_NET_MULTI +#define CONFIG_E1000 + +#define CFG_ETH_DEV_FN 0x0800 +#define CFG_ETH_IOBASE 0x31000000 +#define CFG_ETH_MEMBASE 0x32000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/APC405.h b/include/configs/APC405.h new file mode 100644 index 0000000..3df99a0 --- /dev/null +++ b/include/configs/APC405.h @@ -0,0 +1,387 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_APCG405 1 /* ...on a APC405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm ffc00000 ffca0000" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm ffc00000" +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#if 1 /* test-only */ +#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ +#else +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#endif + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/* Only interrupt boot if space is pressed */ +/* If a long serial cable is connected but */ +/* other end is dead, garbage will be read */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MONITOR_BASE 0xFFF80000 +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_BASE 0xFE000000 /* test-only...*/ +#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */ + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ +#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ +#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define DUART0_BA 0xF0000400 /* DUART Base Address */ +#define DUART1_BA 0xF0000408 /* DUART Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define PS2_BA 0xF0000600 /* PS/2 Base Address */ +#define CF_BA 0xF0100000 /* CompactFlash Base Address */ +#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ +#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ +#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ +#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ +#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ + +#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 1 (Flash Bank 1) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */ +#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/* Memory Bank 4 (PCMCIA Slot 1) initialization */ +#define CFG_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 5 (Epson VGA) initialization */ +#define CFG_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ +#define CFG_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 6 (PCMCIA Slot 2) initialization */ +#define CFG_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/ + +/*----------------------------------------------------------------------- + * FPGA stuff + */ + +/* FPGA internal regs */ +#define CFG_FPGA_CTRL 0x008 +#define CFG_FPGA_CTRL2 0x00a + +/* FPGA Control Reg */ +#define CFG_FPGA_CTRL_CF_RESET 0x0001 +#define CFG_FPGA_CTRL_WDI 0x0002 +#define CFG_FPGA_CTRL_PS2_RESET 0x0020 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * LCD Setup + */ + +#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ +#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ + +#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ + +/* Image information... */ +#define CONFIG_LCD_USED CONFIG_LCD_BIG +#define CFG_LCD_HEADER_NAME "../common/s1d13806_640_480_16bpp.h" +#define CFG_LCD_LOGO_NAME "logo_640_480_24bpp.c" + +#define CFG_LCD_MEM CFG_LCD_BIG_MEM +#define CFG_LCD_REG CFG_LCD_BIG_REG + +#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ + +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/AR405.h b/include/configs/AR405.h new file mode 100644 index 0000000..1cd0280 --- /dev/null +++ b/include/configs/AR405.h @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_AR405 1 /* ...on a AR405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#if 1 +#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */ +#else +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ +#endif + +#if 0 +#define CONFIG_BOOTARGS "root=/dev/nfs " \ + "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ + "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" +#else +#define CONFIG_BOOTARGS "root=/dev/hda1 " \ + "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" + +#endif + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_BSP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xfff00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xfff00001 /* 1MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFFFB0000 /* Address of Environment Sector*/ +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ +#define CFG_ENV_SIZE 0x04000 /* Size of Environment */ + +#define CFG_ENV_ADDR_REDUND 0xFFFA0000 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (CAN0, 1, 2, 3) initialization */ +#define CFG_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */ +#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (Expension Bus) initialization */ +#define CFG_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */ +#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (16552) initialization */ +#define CFG_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */ +#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 4 (FPGA regs) initialization */ +#define CFG_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */ +#define CFG_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */ + +/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */ +#define CFG_EBC_PB5AP 0x92015480 +#define CFG_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ + +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h new file mode 100644 index 0000000..9841893 --- /dev/null +++ b/include/configs/ASH405.h @@ -0,0 +1,387 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_ASH405 1 /* ...on a ASH405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define DUART0_BA 0xF0000400 /* DUART Base Address */ +#define DUART1_BA 0xF0000408 /* DUART Base Address */ +#define DUART2_BA 0xF0000410 /* DUART Base Address */ +#define DUART3_BA 0xF0000418 /* DUART Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define CFG_NAND_BASE 0xF4000000 + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555445 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xF7FE0014 + +#define CFG_DUART_RST (0x80000000 >> 14) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 1 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/Adder.h b/include/configs/Adder.h new file mode 100644 index 0000000..f807546 --- /dev/null +++ b/include/configs/Adder.h @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen + * + * Support for Analogue&Micro Adder boards family. + * Tested on AdderII and Adder87x. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T) +#define CONFIG_MPC875 +#endif + +#define CONFIG_ADDER /* Analogue&Micro Adder board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_FEC_ENET /* Ethernet is on FEC */ +#ifdef CONFIG_FEC_ENET +#define CFG_DISCOVER_PHY +#define FEC_ENET +#endif /* CONFIG_FEC_ENET */ + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#ifdef CONFIG_MPC852T +#define CFG_8xx_CPUCLK_MAX 50000000 +#else +#define CFG_8xx_CPUCLK_MAX 120000000 +#endif /* CONFIG_MPC852T */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS */ +#include + +#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" + +#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* #undef to save memory */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x100000 /* Default load address */ + +#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * RAM configuration (note that CFG_SDRAM_BASE must be zero) + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ + +#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2) +#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V) + +#define CFG_MAMR 0x00802114 + +/* + * 2048 SDRAM rows + * 1000 factor s -> ms + * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */ + +#define CFG_RESET_ADDRESS 0x09900000 + +/*----------------------------------------------------------------------- + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */ +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ +#else +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ +#endif /* CONFIG_BZIP2 */ + +/*----------------------------------------------------------------------- + * Flash organisation + */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ + +/* Environment is in flash */ +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +#define CFG_OR0_PRELIM 0xFF000774 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) + +#define CFG_DIRECT_FLASH_TFTP + +/*----------------------------------------------------------------------- + * Internal Memory Map Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Configuration registers + */ +#ifdef CONFIG_WATCHDOG +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ + SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ + SYPCR_SWF | SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) + +/* TBSCR - Time Base Status and Control Register */ +#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) + +/* PISCR - Periodic Interrupt Status and Control */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/* PLPRCR - PLL, Low-Power, and Reset Control Register */ +/* #define CFG_PLPRCR PLPRCR_TEXPS */ + +/* SCCR - System Clock and reset Control Register */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR SCCR_RTSEL + +#define CFG_DER 0 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */ + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h new file mode 100644 index 0000000..c08b2c3 --- /dev/null +++ b/include/configs/Alaska8220.h @@ -0,0 +1,326 @@ +/* + * (C) Copyright 2004 + * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC8220 1 +#define CONFIG_ALASKA8220 1 /* ... on Alaska board */ + +/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to + determine the CPU speed. */ +#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ +#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ + +/* Define this for PSC console +#define CONFIG_PSC_CONSOLE 1 +*/ + +#define CONFIG_EXTUART_CONSOLE 1 + +#ifdef CONFIG_EXTUART_CONSOLE +# define CONFIG_CONS_INDEX 1 +# define CFG_NS16550_SERIAL +# define CFG_NS16550 +# define CFG_NS16550_REG_SIZE 1 +# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008) +# define CFG_NS16550_CLK 18432000 +#endif + +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +#define CONFIG_NET_MULTI +#define CONFIG_MII + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTARGS "root=/dev/ram rw" +#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61 +#define CONFIG_IPADDR 192.162.1.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.162.1.1 +#define CONFIG_GATEWAYIP 192.162.1.1 +#define CONFIG_HOSTNAME Alaska +#define CONFIG_OVERWRITE_ETHADDR_ONCE + + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_MODULE 1 + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 +/* +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 256 +*/ + +/* If CFG_AMD_BOOT is defined, the the system will boot from AMD. + else undefined it will boot from Intel Strata flash */ +#define CFG_AMD_BOOT 1 + +/* + * Flexbus Chipselect configuration + */ +#if defined (CFG_AMD_BOOT) +#define CFG_CS0_BASE 0xfff0 +#define CFG_CS0_MASK 0x00080000 /* 512 KB */ +#define CFG_CS0_CTRL 0x003f0d40 + +#define CFG_CS1_BASE 0xfe00 +#define CFG_CS1_MASK 0x01000000 /* 16 MB */ +#define CFG_CS1_CTRL 0x003f1540 +#else +#define CFG_CS0_BASE 0xff00 +#define CFG_CS0_MASK 0x01000000 /* 16 MB */ +#define CFG_CS0_CTRL 0x003f1540 + +#define CFG_CS1_BASE 0xfe08 +#define CFG_CS1_MASK 0x00080000 /* 512 KB */ +#define CFG_CS1_CTRL 0x003f0d40 +#endif + +#define CFG_CS2_BASE 0xf100 +#define CFG_CS2_MASK 0x00040000 +#define CFG_CS2_CTRL 0x003f1140 + +#define CFG_CS3_BASE 0xf200 +#define CFG_CS3_MASK 0x00040000 +#define CFG_CS3_CTRL 0x003f1100 + + +#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) +#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16) + +#if defined (CFG_AMD_BOOT) +#define CFG_AMD_BASE CFG_FLASH0_BASE +#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000 +#define CFG_FLASH_BASE CFG_AMD_BASE +#else +#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000 +#define CFG_AMD_BASE CFG_FLASH1_BASE +#define CFG_FLASH_BASE CFG_INTEL_BASE +#endif + +#define CFG_CPLD_BASE (CFG_CS2_BASE << 16) +#define CFG_FPGA_BASE (CFG_CS3_BASE << 16) + + +#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ +#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */ + +#define CFG_FLASH_CHECKSUM +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#if defined (CFG_AMD_BOOT) +#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE) +#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE +#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE +#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE) +#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE +#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE +#else +#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE) +#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE +#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE +#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE) +#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE +#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE +#endif + +#define CONFIG_ENV_OVERWRITE 1 + +#if defined CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_EEPROM +#elif defined CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_EEPROM +#elif defined CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#endif + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 +#define CFG_SRAM_BASE (CFG_MBAR + 0x20000) +#define CFG_SRAM_SIZE 0x8000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) +#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* SDRAM configuration */ +#define CFG_SDRAM_TOTAL_BANKS 2 +#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */ +#define CFG_SDRAM_SPD_SIZE 0x40 +#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */ + +/* SDRAM drive strength register */ +#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ + (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \ + (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \ + (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT)) + +/* + * Ethernet configuration + */ +#define CONFIG_MPC8220_FEC 1 +#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ +#define CONFIG_PHY_ADDR 0x18 + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +/* + * JFFS2 partitions + */ + +/* No command line, one static partition */ +/* +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0x00400000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 +*/ + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=alaska-0" +#define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h new file mode 100644 index 0000000..ea50f41 --- /dev/null +++ b/include/configs/AmigaOneG3SE.h @@ -0,0 +1,397 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the AmigaOneG3SE board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_AMIGAONEG3SE 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_VERY_BIG_RAM 1 + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in Hz */ + +#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096" + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_AMIGA_PARTITION + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_NET | \ + CFG_CMD_IDE | \ + CFG_CMD_FDC | \ + CFG_CMD_CACHE | \ + CFG_CMD_CONSOLE| \ + CFG_CMD_USB | \ + CFG_CMD_BSP | \ + CFG_CMD_PCI ) + +/* CFG_CMD_MII | \ */ + +#define CONFIG_PCI 1 +/* #define CONFIG_PCI_SCAN_SHOW 1 */ +#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "] " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +/* #undef CFG_HUSH_PARSER */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 64 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00500000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_FLASH_MAX_SIZE 0x00080000 +/* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x80000000 /* 2G */ + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (768 << 10) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (2500 << 10) /* Reserve 128 kB for malloc() */ + +#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ + CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* Size in bytes reserved for initial data + */ +/* HJF: used to be 0x400000 */ +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x8000 +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_INIT_RAM_LOCK + +/* + * Temporary buffer for serial data until the real serial driver + * is initialised (memtest will destroy this buffer) + */ +#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR +#define CFG_SCONSOLE_SIZE 0x0002000 + +/* SDRAM 0 - 256MB + */ + +/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT0U CFG_IBAT0U*/ + +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +/* PCI Range + */ +#define CFG_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) +/* HJF: +#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) +#define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) +#define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP) +*/ + +/* Init RAM in the CPU DCache (no backing memory) + */ +#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +/* This used to be commented out */ +#define CFG_IBAT2L CFG_DBAT2L +/* This here too */ +#define CFG_IBAT2U CFG_DBAT2U + + +/* I/O and PCI memory at 0xf0000000 + */ +#define CFG_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + */ +#define CFG_HZ 1000 +#define CFG_BUS_HZ 133000000 /* bus speed - 100 mhz */ +#define CFG_CPU_CLK 133000000 +#define CFG_BUS_CLK 133000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 8 /* Max number of sectors in one bank */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +/* + * Environment is stored in NVRAM. + */ +#define CFG_ENV_IS_IN_NVRAM 1 +#define CFG_ENV_ADDR 0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to + * protect softex's settings for now. + * Original 768 bytes where not enough. + */ +#define CFG_ENV_SIZE 0x8000 /* Size of the Environment. See comment above */ + +#define CFG_CONSOLE_IS_IN_ENV 1 /* stdin/stdout/stderr are in environment */ +#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 +#define CONFIG_ENV_OVERWRITE 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * L2 cache + */ +#define CFG_L2 +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * IDE ATAPI Configuration + */ + +#define CONFIG_ATAPI 1 +#define CFG_IDE_MAXBUS 2 +#define CFG_IDE_MAXDEVICE 4 +#define CONFIG_ISO_PARTITION 1 + +#define CFG_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */ +#define CFG_ATA_IDE0_OFFSET 0x1F0 +#define CFG_ATA_IDE1_OFFSET 0x170 + +#define CFG_ATA_REG_OFFSET 0 +#define CFG_ATA_DATA_OFFSET 0 +#define CFG_ATA_ALT_OFFSET 0x0200 + +/*----------------------------------------------------------------------- + * Disk-On-Chip configuration + */ + +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#undef CFG_DOC_SUPPORT_MILLENNIUM + +/*----------------------------------------------------------------------- + RTC +*/ +#define CONFIG_RTC_MC146818 + +/*----------------------------------------------------------------------- + * NS16550 Configuration + */ + +#define CFG_NS16550 + +#define CFG_NS16550_COM1 0xFE0003F8 +#define CFG_NS16550_COM2 0xFE0002F8 + +#define CFG_NS16550_REG_SIZE 1 + +/* base address for ISA I/O + */ +#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000 + +/* ISA Interrupt stuff (taken from JWL) */ + +#define ISA_INT1_OCW1 0x21 +#define ISA_INT2_OCW1 0xA1 +#define ISA_INT1_OCW2 0x20 +#define ISA_INT2_OCW2 0xA0 +#define ISA_INT1_OCW3 0x20 +#define ISA_INT2_OCW3 0xA0 + +#define ISA_INT1_ICW1 0x20 +#define ISA_INT2_ICW1 0xA0 +#define ISA_INT1_ICW2 0x21 +#define ISA_INT2_ICW2 0xA1 +#define ISA_INT1_ICW3 0x21 +#define ISA_INT2_ICW3 0xA1 +#define ISA_INT1_ICW4 0x21 +#define ISA_INT2_ICW4 0xA1 + + +/* + * misc + */ + +#define CONFIG_NET_MULTI +#define CFG_BOARD_ASM_INIT +#define CONFIG_LAST_STAGE_INIT + +/* #define CONFIG_ETHADDR 00:09:D2:10:00:76 */ +/* #define CONFIG_IPADDR 192.168.0.2 */ +/* #define CONFIG_NETMASK 255.255.255.240 */ +/* #define CONFIG_GATEWAYIP 192.168.0.3 */ + +#define CONFIG_3COM +/* #define CONFIG_BOOTP_RANDOM_DELAY */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +/* + * USB configuration + */ +#define CONFIG_USB_UHCI 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_KEYBOARD 1 +#define CFG_DEVICE_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */ + +/* + * Autoboot stuff + */ +#define CONFIG_BOOTDELAY 5 /* Boot automatically after five seconds */ +#define CONFIG_PREBOOT "" +#define CONFIG_BOOTCOMMAND "fdcboot; diskboot" +#define CONFIG_MENUPROMPT "Press any key to interrupt autoboot: %2d " +#define CONFIG_MENUKEY ' ' +#define CONFIG_MENUCOMMAND "menu" +/* #define CONFIG_AUTOBOOT_KEYED */ + +/* + * Extra ENV stuff + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdout=vga\0" \ + "stdin=ps2kbd\0" \ + "ide_doreset=on\0" \ + "ide_maxbus=2\0" \ + "ide_cd_timeout=30\0" \ + "menucmd=menu\0" \ + "pci_irqa=9\0" \ + "pci_irqa_select=edge\0" \ + "pci_irqb=10\0" \ + "pci_irqb_select=edge\0" \ + "pci_irqc=11\0" \ + "pci_irqc_select=edge\0" \ + "pci_irqd=7\0" \ + "pci_irqd_select=edge\0" + + +/* #define CONFIG_MII 1 */ +/* #define CONFIG_BITBANGMII 1 */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/B2.h b/include/configs/B2.h new file mode 100644 index 0000000..e55858d --- /dev/null +++ b/include/configs/B2.h @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * Configuation settings for the B2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_B2 1 /* on an B2 Board */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ + + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + + +/* + * Size of malloc() pool + */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024 ) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */ +#define CONFIG_SMC_USE_32_BIT +#undef CONFIG_SHOW_ACTIVITY +#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_ETHADDR 00:50:c2:1e:af:fb +#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \ + ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb" +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.0.70 +#define CONFIG_SERVERIP 192.168.0.23 +#define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot" +#define CONFIG_BOOTCOMMAND "bootm 20000 f0000" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0C400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x0c700000 /* default load address */ + +#define CFG_HZ 1000 /* 1 kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x0 /* environment starts at the beginning of the EEPROM */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (STM24C02W6) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0xFE + +#define CFG_I2C_EEPROM_ADDR 0xA8 /* EEPROM STM24C02W6 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/* Flash banks JFFS2 should use */ +/* +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 2 +#define CFG_JFFS2_NUM_BANKS 1 +*/ + +/* + Linux TAGs (see lib_arm/armlinux.c) +*/ +#define CONFIG_CMDLINE_TAG +#undef CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#endif /* __CONFIG_H */ diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h new file mode 100644 index 0000000..46bdfa2 --- /dev/null +++ b/include/configs/BAB7xx.h @@ -0,0 +1,467 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG +#define GTREGREAD(x) 0xffffffff /* needed for debug */ + +/* + * High Level Configuration Options + * (easy to change) + */ + +/* these hardware addresses are pretty bogus, please change them to + suit your needs */ + +/* first ethernet */ +#define CONFIG_ETHADDR 00:00:5b:ee:de:ad + +#define CONFIG_IPADDR 192.168.0.105 +#define CONFIG_SERVERIP 192.168.0.100 + +#define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */ + +#define CONFIG_BAUDRATE 9600 /* console baudrate */ + +#undef CONFIG_WATCHDOG + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp 1000000; " \ + "setenv bootargs root=ramfs console=ttyS00,9600 " \ + "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ + "${netmask}:${hostname}:eth0:none; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\ + CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\ + CFG_CMD_FDC | CFG_CMD_ELF) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +/* + * choose between COM1 and COM2 as serial console + */ +#define CONFIG_CONS_INDEX 1 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ + +#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +#define CFG_BOARD_ASM_INIT +#define CONFIG_MISC_INIT_R + +/* + * Choose the address mapping scheme for the MPC106 mem controller. + * Default is mapping B (CHRP), set this define to choose mapping A (PReP). + */ +#define CFG_ADDRESS_MAP_A +#ifdef CFG_ADDRESS_MAP_A + +#define CFG_PCI_MEMORY_BUS 0x80000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#define CFG_PCI_MEM_BUS 0x00000000 +#define CFG_PCI_MEM_PHYS 0xc0000000 +#define CFG_PCI_MEM_SIZE 0x3f000000 + +#define CFG_ISA_MEM_BUS 0 +#define CFG_ISA_MEM_PHYS 0 +#define CFG_ISA_MEM_SIZE 0 + +#define CFG_PCI_IO_BUS 0x1000 +#define CFG_PCI_IO_PHYS 0x81000000 +#define CFG_PCI_IO_SIZE 0x01000000-CFG_PCI_IO_BUS + +#define CFG_ISA_IO_BUS 0x00000000 +#define CFG_ISA_IO_PHYS 0x80000000 +#define CFG_ISA_IO_SIZE 0x00800000 + +#else + +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x40000000 + +#define CFG_PCI_MEM_BUS 0x80000000 +#define CFG_PCI_MEM_PHYS 0x80000000 +#define CFG_PCI_MEM_SIZE 0x7d000000 + +#define CFG_ISA_MEM_BUS 0x00000000 +#define CFG_ISA_MEM_PHYS 0xfd000000 +#define CFG_ISA_MEM_SIZE 0x01000000 + +#define CFG_PCI_IO_BUS 0x00800000 +#define CFG_PCI_IO_PHYS 0xfe800000 +#define CFG_PCI_IO_SIZE 0x00400000 + +#define CFG_ISA_IO_BUS 0x00000000 +#define CFG_ISA_IO_PHYS 0xfe000000 +#define CFG_ISA_IO_SIZE 0x00800000 + +#endif /*CFG_ADDRESS_MAP_A */ + +#define CFG_60X_PCI_MEM_OFFSET 0x00000000 + +/* driver defines FDC,IDE,... */ +#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS +#define CFG_ISA_IO CFG_ISA_IO_PHYS +#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xfff00000 + +/* + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ +#define CFG_INIT_RAM_END 0x4000 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Flash mapping/organization on the MPC10x. + */ +#define FLASH_BASE0_PRELIM 0xff800000 +#define FLASH_BASE1_PRELIM 0xffc00000 + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support + * + * Note: fake mtd_id used, no linux mtd map file + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=bab7xx-0" +#define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)" +*/ + +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ +#undef CFG_MEMTEST + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */ +#define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ +/* + * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus, + * user applications can use the remaining space for other purposes. + */ +#define CFG_ENV_ADDR (CFG_NVRAM_SIZE +0x10 -0x800) +#define CFG_NV_SROM_COPY_ADDR (CFG_NVRAM_SIZE +0x10 -0x400) +#define CFG_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */ +#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ + +/* + * Serial devices + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 1843200 +#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) +#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) + +/* + * PCI stuff + */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO +#undef CONFIG_PCI_SCAN_SHOW + +/* + * Video console (graphic: SMI LynxEM, keyboard: i8042) + */ +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SMI_LYNXEM +#define CONFIG_I8042_KBD +#define CONFIG_VIDEO_LOGO +#define CONFIG_CONSOLE_TIME +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_CONSOLE_CURSOR +#define CFG_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */ + +/* + * IDE/SCSI globals + */ +#ifndef __ASSEMBLY__ +extern unsigned int eltec_board; +extern unsigned int ata_reset_time; +extern unsigned int scsi_reset_time; +extern unsigned short scsi_dev_id; +extern unsigned int scsi_max_scsi_id; +extern unsigned char scsi_sym53c8xx_ccf; +#endif + +/* + * ATAPI Support (experimental) + */ +#define CONFIG_ATAPI +#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */ +#define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */ +#define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ + +#define ATA_RESET_TIME (ata_reset_time) + +#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ + +/* + * SCSI support (experimental) only SYM53C8xx supported + */ +#define CONFIG_SCSI_SYM53C8XX +#define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */ +#define CFG_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */ +#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ +#define CFG_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */ +#define CFG_SCSI_MAX_DEVICE (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */ +#define CFG_SCSI_SPIN_UP_TIME (scsi_reset_time) + +/* + * Partion suppport + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION + +/* + * Winbond Configuration + */ +#define CFG_WINBOND_83C553 1 /* has a winbond bridge */ +#define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */ +#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */ +#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */ + +/* + * NS87308 Configuration + */ +#define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */ +#define CFG_NS87308_BADDR_10 1 +#define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \ + CFG_NS87308_UART2 | \ + CFG_NS87308_KBC1 | \ + CFG_NS87308_MOUSE | \ + CFG_NS87308_FDC | \ + CFG_NS87308_RARP | \ + CFG_NS87308_GPIO | \ + CFG_NS87308_POWRMAN | \ + CFG_NS87308_RTC_APC ) + +#define CFG_NS87308_PS2MOD +#define CFG_NS87308_GPIO_BASE 0x0220 +#define CFG_NS87308_PWMAN_BASE 0x0460 +#define CFG_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */ + +/* + * set up the NVRAM access registers + * NVRAM's controlled by the configurable CS line from the 87308 + */ +#define CFG_NS87308_CS0_BASE 0x0076 +#define CFG_NS87308_CS0_CONF 0x40 +#define CFG_NS87308_CS1_BASE 0x0070 +#define CFG_NS87308_CS1_CONF 0x1C +#define CFG_NS87308_CS2_BASE 0x0071 +#define CFG_NS87308_CS2_CONF 0x1C + +#define CONFIG_RTC_MK48T59 + +/* + * Initial BATs + */ +#if 1 + +#define CFG_IBAT0L 0 +#define CFG_IBAT0U 0 +#define CFG_DBAT0L CFG_IBAT1L +#define CFG_DBAT0U CFG_IBAT1U + +#define CFG_IBAT1L 0 +#define CFG_IBAT1U 0 +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +#define CFG_IBAT2L 0 +#define CFG_IBAT2U 0 +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +#define CFG_IBAT3L 0 +#define CFG_IBAT3U 0 +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +#else + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT1L +#define CFG_DBAT0U CFG_IBAT1U + +/* address range for flashes */ +#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* ISA IO space */ +#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* ISA memory space */ +#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +#endif + +/* + * Speed settings are board specific + */ +#ifndef __ASSEMBLY__ +extern unsigned long bab7xx_get_bus_freq (void); +extern unsigned long bab7xx_get_gclk_freq (void); +#endif +#define CFG_BUS_HZ bab7xx_get_bus_freq() +#define CFG_BUS_CLK CFG_BUS_HZ +#define CFG_CPU_CLK bab7xx_get_gclk_freq() + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * L2 Cache Configuration is board specific for BAB740/BAB750 + * Init values read from revision srom. + */ +#undef CFG_L2 +#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +#define CFG_L2_BAB7xx + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_TULIP +#define CONFIG_TULIP_SELECT_MEDIA + +#endif /* __CONFIG_H */ diff --git a/include/configs/BMW.h b/include/configs/BMW.h new file mode 100644 index 0000000..050054d --- /dev/null +++ b/include/configs/BMW.h @@ -0,0 +1,305 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the CU824 board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_BMW 1 + +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ + +#define CONFIG_BCM570x 1 /* Use Broadcom BCM570x Ethernet Driver */ +#define CONFIG_TIGON3 1 + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */ +#define CONFIG_BOOTDELAY 5 + +#define CFG_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */ +#define DOC_PASSIVE_PROBE 1 +#define CFG_DOC_SUPPORT_2000 1 +#define CFG_DOC_SUPPORT_MILLENNIUM 1 +#define CFG_DOC_SHORT_TIMEOUT 1 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_ELF | \ + 0 ) +#if 0 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \ + CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE) + +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ +#endif + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 8 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */ +#define CFG_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */ +#define CFG_FLASH_BASE CFG_MONITOR_BASE +#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM , CFG_FLASH_BASE1_PRELIM } + +/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the + * reset vector is actually located at FFB00100, but the 8245 + * takes care of us. + */ +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ + + /* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */ + + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ +#define CFG_HZ 1000 + +#define CFG_ETH_DEV_FN 0x7800 +#define CFG_ETH_IOBASE 0x00104000 + + /* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 0xf +#define CFG_ROMFAL 0x1f +#define CFG_DBUS_SIZE 0x3 + + /* Bit-field values for MCCR2. + */ +#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ +#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ + + /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 0 /* FIXME: was 192 */ + + /* Bit-field values for MCCR3. + */ +#define CFG_REFREC 2 /* Refresh to activate interval */ + + /* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length */ +#define CFG_ACTORW 0xa /* FIXME was 2 */ +#define CFG_REGISTERD_TYPE_BUFFER 1 + +#define CFG_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ + +#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0xff + +#define CONFIG_PCI 1 /* Include PCI support */ +#undef CONFIG_PCI_PNP + +/* PCI Memory space(s) */ +#define PCI_MEM_SPACE1_START 0x80000000 +#define PCI_MEM_SPACE2_START 0xfd000000 + +/* ROM Spaces */ +#include "../board/bmw/bmw.h" + +/* BAT configuration */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 0 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* + * Warining: environment is not EMBEDDED in the U-Boot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_NVRAM 1 +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_NVRAM_ACCESS_ROUTINE 1 +#define CFG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */ +#define CFG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */ +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h new file mode 100644 index 0000000..e0262a8 --- /dev/null +++ b/include/configs/CANBT.h @@ -0,0 +1,227 @@ +/* + * (C) Copyright 2001 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405CR 1 /* This is a PPC405CR CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_CANBT 1 /* ...on a CANBT board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \ + "bootm ffe00000 ffe80000" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#undef CONFIG_PCI_PNP /* no pci plug-and-play */ + +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ + CFG_CMD_IRQ | \ + CFG_CMD_EEPROM ) & \ + ~CFG_CMD_NET) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFE0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* Use FLASH for environment variables */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ + +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ + +#else /* Use EEPROM for environment variables */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ + /* total size of a CAT24WC08 is 1024 bytes */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC08) for environment + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (CAN/USB) initialization */ +#define CFG_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */ +#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (Misc-IO/LEDs) initialization */ +#define CFG_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */ +#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (CAN Features) initialization */ +#define CFG_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */ +#define CFG_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in RAM) + */ +#define CFG_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h new file mode 100644 index 0000000..ffe89cb --- /dev/null +++ b/include/configs/CATcenter.h @@ -0,0 +1,787 @@ +/* + * ueberarbeitet durch Christoph Seyfert + * + * (C) Copyright 2004-2005 DENX Software Engineering, + * Wolfgang Grandegger + * (C) Copyright 2003 + * DAVE Srl + * + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * Credits: Stefan Roese, Wolfgang Denk + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ +#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ +#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ +#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL +#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA +#endif + +/* Only one of the following two symbols must be defined (default is 25 MHz) + * CONFIG_PPCHAMELEON_CLK_25 + * CONFIG_PPCHAMELEON_CLK_33 + */ +#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) +#define CONFIG_PPCHAMELEON_CLK_25 +#endif + +#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) +#error "* Two external frequencies (SysClk) are defined! *" +#endif + +#undef CONFIG_PPCHAMELEON_SMI712 + +/* + * Debug stuff + */ +#undef __DEBUG_START_FROM_SRAM__ +#define __DISABLE_MACHINE_EXCEPTION__ + +#ifdef __DEBUG_START_FROM_SRAM__ +#define CFG_DUMMY_FLASH_SIZE 1024*1024*4 +#endif + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#ifdef CONFIG_PPCHAMELEON_CLK_25 +# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ +#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#else +# error "* External frequency (SysClk) not defined! *" +#endif + +#define CONFIG_UART1_CONSOLE 1 /* Use second UART */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_VERSION_VARIABLE 1 /* add version variable */ +#define CONFIG_IDENT_STRING "1" + +#undef CONFIG_BOOTARGS + +/* Ethernet stuff */ +#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ +#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + + +#undef CONFIG_EXT_PHY +#define CONFIG_NET_MULTI 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#ifndef CONFIG_EXT_PHY +#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ +#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */ +#else +#define CONFIG_PHY_ADDR 2 /* PHY address */ +#endif +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_NAND0_BASE 0xFF400000 +#define CFG_NAND1_BASE 0xFF000000 + +/* For CATcenter there is only NAND on the module */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 +#define NAND_NO_RB + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ +#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ +#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ +#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ + + +#define NAND_DISABLE_CE(nand) do \ +{ \ + switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \ + break; \ + } \ +} while(0) + +#define NAND_ENABLE_CE(nand) do \ +{ \ + switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \ + break; \ + } \ +} while(0) + + +#define NAND_CTL_CLRALE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \ + break; \ + } \ +} while(0) + +#define NAND_CTL_SETALE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \ + break; \ + } \ +} while(0) + +#define NAND_CTL_CLRCLE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \ + break; \ + } \ +} while(0) + +#define NAND_CTL_SETCLE(nandptr) do { \ + switch((unsigned long)nandptr) { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \ + break; \ + } \ +} while(0) + +#ifdef NAND_NO_RB +/* constant delay (see also tR in the datasheet) */ +#define NAND_WAIT_READY(nand) do { \ + udelay(12); \ +} while (0) +#else +/* use the R/B pin */ +/* TBD */ +#endif + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#if 0 /* No PCI on CATcenter */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ + +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#endif /* No PCI */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ +#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ +#define CFG_ENV_ADDR_REDUND 0xFFFFA000 +#define CFG_ENV_SIZE_REDUND 0x2000 + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (External SRAM) initialization */ +/* Since this must replace NOR Flash, we use the same settings for CS0 */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x92015480 +#define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x92015480 +#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ + +#ifdef CONFIG_PPCHAMELEON_SMI712 +/* + * Video console (graphic: SMI LynxEM) + */ +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SMI_LYNXEM +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_VIDEO_BMP_LOGO*/ +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ +#define CFG_ISA_IO 0xE8000000 +/* see also drivers/videomodes.c */ +#define CFG_DEFAULT_VIDEO_MODE 0x303 +#endif + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +/* FPGA internal regs */ +#define CFG_FPGA_MODE 0x00 +#define CFG_FPGA_STATUS 0x02 +#define CFG_FPGA_TS 0x04 +#define CFG_FPGA_TS_LOW 0x06 +#define CFG_FPGA_TS_CAP0 0x10 +#define CFG_FPGA_TS_CAP0_LOW 0x12 +#define CFG_FPGA_TS_CAP1 0x14 +#define CFG_FPGA_TS_CAP1_LOW 0x16 +#define CFG_FPGA_TS_CAP2 0x18 +#define CFG_FPGA_TS_CAP2_LOW 0x1a +#define CFG_FPGA_TS_CAP3 0x1c +#define CFG_FPGA_TS_CAP3_LOW 0x1e + +/* FPGA Mode Reg */ +#define CFG_FPGA_MODE_CF_RESET 0x0001 +#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 +#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 +#define CFG_FPGA_MODE_TS_CLEAR 0x2000 + +/* FPGA Status Reg */ +#define CFG_FPGA_STATUS_DIP0 0x0001 +#define CFG_FPGA_STATUS_DIP1 0x0002 +#define CFG_FPGA_STATUS_DIP2 0x0004 +#define CFG_FPGA_STATUS_FLASH 0x0008 +#define CFG_FPGA_STATUS_TS_IRQ 0x1000 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30] - EMAC0 input + * GPIO0[31] - EMAC1 reject packet as output + */ +#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +/*#define CFG_GPIO0_ISR1L 0x15555445*/ +#define CFG_GPIO0_ISR1L 0x15555444 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xF7FF8014 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define CONFIG_NO_SERIAL_EEPROM + +/*--------------------------------------------------------------------*/ + +#ifdef CONFIG_NO_SERIAL_EEPROM + +/* +!----------------------------------------------------------------------- +! Defines for entry options. +! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that +! are plugged in the board will be utilized as non-ECC DIMMs. +!----------------------------------------------------------------------- +*/ +#undef AUTO_MEMORY_CONFIG +#define DIMM_READ_ADDR 0xAB +#define DIMM_WRITE_ADDR 0xAA + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +#ifdef CONFIG_PPCHAMELEON_CLK_25 +/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ +#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) + +/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ +#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#else +#error "* External frequency (SysClk) not defined! *" +#endif + +#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) +/* Model HI */ +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 +#define CFG_OPB_FREQ 55555555 +/* Model ME */ +#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 +#define CFG_OPB_FREQ 66666666 +#else +/* Model BA (default) */ +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 +#define CFG_OPB_FREQ 66666666 +#endif + +#endif /* CONFIG_NO_SERIAL_EEPROM */ + +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand" +#define CONFIG_JFFS2_PART_SIZE 0x00200000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support + * + * Note: fake mtd_id used, no linux mtd map file + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=catcenter" +#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CCM.h b/include/configs/CCM.h new file mode 100644 index 0000000..e8994ff --- /dev/null +++ b/include/configs/CCM.h @@ -0,0 +1,478 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * configuration options, board specific, for Siemens Card Controller Module + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef CCM_80MHz /* define for 80 MHz CPU only */ + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ +#define CONFIG_CCM 1 /* on a Card Controller Module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +/* ENVIRONMENT */ + +#define CONFIG_BAUDRATE 19200 /* console baudrate in bps */ +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ + +#define CONFIG_IPADDR 192.168.0.42 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 0.0.0.0 +#define CONFIG_SERVERIP 192.168.0.254 + +#define CONFIG_HOSTNAME CCM + +#define CONFIG_LOADADDR 40180000 + +#undef CONFIG_BOOTARGS + +#define CONFIG_BOOTCOMMAND "setenv bootargs " \ + "mem=${mem} " \ + "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ + "wt_8xx=timeout:3600; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_WATCHDOG 1 /* watchdog enabled */ + +#undef CONFIG_STATUS_LED /* Status LED disabled */ + +#define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/ + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_SPI /* enable SPI driver */ +#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ + +/* ---------------------------------------------------------------- + * Offset to initial SPI buffers in DPRAM (used if the environment + * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to + * use at an early stage. It is used between the two initialization + * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it + * far enough from the start of the data area (as well as from the + * stack pointer). + * ---------------------------------------------------------------- */ +#define CFG_SPI_INIT_OFFSET 0xB00 + +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */ + + +#define CONFIG_MAC_PARTITION /* nod used yet */ +#define CONFIG_DOS_PARTITION + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +/* Ethernet hardware configuration done using port pins */ +#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */ +#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ +#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ +#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ +#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */ +#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */ + +/* Ethernet settings: + * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex + */ +#define CFG_ETH_MDDIS_VALUE 0 +#define CFG_ETH_CFG1_VALUE 1 +#define CFG_ETH_CFG2_VALUE 1 +#define CFG_ETH_CFG3_VALUE 1 + +/* PUMA configuration */ +#define CFG_PC_PUMA_PROG 0x0200 /* PC 6 */ +#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */ +#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Address accessed to reset the board - must not be mapped/assigned + */ +#define CFG_RESET_ADDRESS 0xFEFFFFFF + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#if 1 +/* Start port with environment in flash; switch to SPI EEPROM later */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#else +/* Final version: environment in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 2048 +#define CFG_ENV_SIZE 2048 +#endif + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * we must activate GPL5 in the SIUMCR for CAN + */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ +#define CFG_PLPRCR \ + ( (5-1)< + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +#undef CONFIG_PRAM /* no "protected RAM" */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * RTC stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_RTC_DS1337 +#define CFG_I2C_RTC_ADDR 0x68 + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) +# define CFG_RAMBOOT 1 +#else +# undef CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#define CFG_EEPROM_WREN 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ +#define CFG_PLD_BASE 0xf0000000 +#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ +/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ +/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ +/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ +#define CFG_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ +#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ +#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ +#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ +#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ +#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ + +#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ +#define CFG_PLD_RESET (0x80000000 >> 12) /* GPIO12 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 1 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h new file mode 100644 index 0000000..b882f7a --- /dev/null +++ b/include/configs/CPC45.h @@ -0,0 +1,513 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the CPC45 board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_CPC45 1 + + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ + CFG_CMD_FLASH | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#if 1 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ + +#define CFG_SDRAM_BASE 0x00000000 + +#if defined(CONFIG_BOOT_ROM) +#define CFG_FLASH_BASE 0xFF000000 +#else +#define CFG_FLASH_BASE 0xFF800000 +#endif + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFCE00000 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + +/* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x10000000 + + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* Size in bytes reserved for initial data + */ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) +#define DUART_DCR (CFG_EUMB_ADDR + 0x4511) + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 +#define CFG_HZ 1000 + + +/* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 8 + +#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ +#define CFG_BANK1_ROW 0 +#define CFG_BANK2_ROW 0 +#define CFG_BANK3_ROW 0 +#define CFG_BANK4_ROW 0 +#define CFG_BANK5_ROW 0 +#define CFG_BANK6_ROW 0 +#define CFG_BANK7_ROW 0 + +/* Bit-field values for MCCR2. + */ + +#define CFG_REFINT 0x2ec + +/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 160 + +/* Bit-field values for MCCR3. + */ +#define CFG_REFREC 2 /* Refresh to activate interval */ +#define CFG_RDLAT 0 /* Data latancy from read command */ + +/* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ +#define CFG_ACTORW 2 +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 0 +#define CFG_REGDIMM 0 + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0xff +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ +#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + + /* Warining: environment is not EMBEDDED in the ppcboot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7F8000) +#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */ +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ +#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define SRAM_BASE 0x80000000 /* SRAM base address */ +#define SRAM_END 0x801FFFFF + +/*----------------------------------------------------------------------*/ +/* CPC45 Memory Map */ +/*----------------------------------------------------------------------*/ +#define SRAM_BASE 0x80000000 /* SRAM base address */ +#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ +#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ +#define BCSR_BASE 0x80600000 /* board control / status registers */ +#define DISPLAY_BASE 0x80600040 /* DISPLAY base */ +#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */ +#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ + + +/*---------------------------------------------------------------------*/ +/* CPC45 Control/Status Registers */ +/*---------------------------------------------------------------------*/ +#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00)) +#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01)) +#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02)) +#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03)) +#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04)) +#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05)) +#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06)) +#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06)) +#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06)) +#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07)) + +/* IRQ_ENA_1 bit definitions */ +#define I_ENA_1_IERA 0x80 /* INTA enable */ +#define I_ENA_1_IERB 0x40 /* INTB enable */ +#define I_ENA_1_IERC 0x20 /* INTC enable */ +#define I_ENA_1_IERD 0x10 /* INTD enable */ + +/* IRQ_STAT_1 bit definitions */ +#define I_STAT_1_INTA 0x80 /* INTA status */ +#define I_STAT_1_INTB 0x40 /* INTB status */ +#define I_STAT_1_INTC 0x20 /* INTC status */ +#define I_STAT_1_INTD 0x10 /* INTD status */ + +/* IRQ_ENA_2 bit definitions */ +#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */ +#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */ +#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */ +#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */ +#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */ +#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */ +#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */ +#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */ + +/* IRQ_STAT_2 bit definitions */ +#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */ +#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */ +#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */ +#define I_STAT_2_RTC 0x10 /* RTC IRQ status */ +#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */ +#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */ +#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */ +#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */ + +/* BOARD_CTRL bit definitions */ +#define USER_LEDS 2 /* 2 user LEDs */ + +#if (USER_LEDS == 4) +#define B_CTRL_WRSE 0x80 +#define B_CTRL_KRSE 0x40 +#define B_CTRL_FWRE 0x20 /* Flash write enable */ +#define B_CTRL_FWPT 0x10 /* Flash write protect */ +#define B_CTRL_LED3 0x08 /* LED 3 control */ +#define B_CTRL_LED2 0x04 /* LED 2 control */ +#define B_CTRL_LED1 0x02 /* LED 1 control */ +#define B_CTRL_LED0 0x01 /* LED 0 control */ +#else +#define B_CTRL_WRSE 0x80 +#define B_CTRL_KRSE 0x40 +#define B_CTRL_FWRE_1 0x20 /* Flash write enable */ +#define B_CTRL_FWPT_1 0x10 /* Flash write protect */ +#define B_CTRL_LED1 0x08 /* LED 1 control */ +#define B_CTRL_LED0 0x04 /* LED 0 control */ +#define B_CTRL_FWRE_0 0x02 /* Flash write enable */ +#define B_CTRL_FWPT_0 0x01 /* Flash write protect */ +#endif + +/* BOARD_STAT bit definitions */ +#define B_STAT_WDGE 0x80 +#define B_STAT_WDGS 0x40 +#define B_STAT_WRST 0x20 +#define B_STAT_KRST 0x10 +#define B_STAT_CSW3 0x08 /* sitch bit 3 status */ +#define B_STAT_CSW2 0x04 /* sitch bit 2 status */ +#define B_STAT_CSW1 0x02 /* sitch bit 1 status */ +#define B_STAT_CSW0 0x01 /* sitch bit 0 status */ + +/*---------------------------------------------------------------------*/ +/* Display addresses */ +/*---------------------------------------------------------------------*/ +#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */ +#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */ +#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */ + +#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */ +#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */ + +#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */ +#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */ +#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */ +#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */ +#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */ +#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */ +#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */ +#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */ + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP +#undef CONFIG_PCI_SCAN_SHOW + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +#define PCI_ENET0_IOADDR 0x82000000 +#define PCI_ENET0_MEMADDR 0x82000000 +#define PCI_PLX9030_IOADDR 0x82100000 +#define PCI_PLX9030_MEMADDR 0x82100000 + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + */ + +#define CONFIG_I82365 + +#define CFG_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE +#define CFG_PCMCIA_MEM_SIZE 0x1000 + +#define CONFIG_PCMCIA_SLOT_A + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_RESET /* reset for IDE not supported */ +#define CONFIG_IDE_LED /* LED for IDE is supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +#define CFG_ATA_DATA_OFFSET CFG_PCMCIA_MEM_SIZE + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x400) + +#define CONFIG_DOS_PARTITION + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h new file mode 100644 index 0000000..756bb8c --- /dev/null +++ b/include/configs/CPCI2DP.h @@ -0,0 +1,272 @@ +/* + * (C) Copyright 2005 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOOPW 1 /* enable loopw command */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */ +#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */ +#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ + +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#define CFG_EEPROM_WREN 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ +#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (PB0) initialization */ +#define CFG_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ +#define CFG_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (PB1) initialization */ +#define CFG_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ +#define CFG_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ + +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * GPIO definitions + */ +#define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */ +#define CFG_PB_LED (0x80000000 >> 16) /* GPIO16 */ +#define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h new file mode 100644 index 0000000..d49020d --- /dev/null +++ b/include/configs/CPCI405.h @@ -0,0 +1,337 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOOPW 1 /* enable loopw command */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ + +#if 1 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ + +#else /* Use EEPROM for environment variables */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ + /* total size of a CAT24WC08 is 1024 bytes */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC08) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (CompactFlash IDE) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/* Memory Bank 4 (NVRAM) initialization */ +#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ +#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 5 (Quart) initialization */ +#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ +#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * FPGA stuff + */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +#if 1 /* test-only */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ + +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#else +#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ +#endif +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h new file mode 100644 index 0000000..13dbe80 --- /dev/null +++ b/include/configs/CPCI4052.h @@ -0,0 +1,422 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ +#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) + +#if 0 /* test-only */ +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI + +#ifdef CONFIG_NET_MULTI +#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ +#endif +#endif + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_SUPPORT_VFAT + +#if 0 /* test-only */ +#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOOPW 1 /* enable loopw command */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + + +/* + * JFFS2 partitions + */ + +/* No command line, one static partition, use whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ + +/* Use first bank for JFFS2, second bank contains U-Boot. + * + * Note: fake mtd_id's used, no linux mtd map file. + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=cpci4052-0" +#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)" +*/ + +#if 0 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */ + +#else /* Use EEPROM for environment variables */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ +#endif + +#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (CAN0, 1) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_LED_ADDR 0xF0000380 + +/* Memory Bank 3 (CompactFlash IDE) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/* Memory Bank 4 (NVRAM/RTC) initialization */ +/*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ +#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ +#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 5 (optional Quart) initialization */ +#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ +#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 6 (FPGA internal) initialization */ +#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ +#define CFG_FPGA_BASE_ADDR 0xF0400000 + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +/* FPGA internal regs */ +#define CFG_FPGA_MODE 0x00 +#define CFG_FPGA_STATUS 0x02 +#define CFG_FPGA_TS 0x04 +#define CFG_FPGA_TS_LOW 0x06 +#define CFG_FPGA_TS_CAP0 0x10 +#define CFG_FPGA_TS_CAP0_LOW 0x12 +#define CFG_FPGA_TS_CAP1 0x14 +#define CFG_FPGA_TS_CAP1_LOW 0x16 +#define CFG_FPGA_TS_CAP2 0x18 +#define CFG_FPGA_TS_CAP2_LOW 0x1a +#define CFG_FPGA_TS_CAP3 0x1c +#define CFG_FPGA_TS_CAP3_LOW 0x1e + +/* FPGA Mode Reg */ +#define CFG_FPGA_MODE_CF_RESET 0x0001 +#define CFG_FPGA_MODE_DUART_RESET 0x0002 +#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ +#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 +#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 +#define CFG_FPGA_MODE_TS_CLEAR 0x2000 + +/* FPGA Status Reg */ +#define CFG_FPGA_STATUS_DIP0 0x0001 +#define CFG_FPGA_STATUS_DIP1 0x0002 +#define CFG_FPGA_STATUS_DIP2 0x0004 +#define CFG_FPGA_STATUS_FLASH 0x0008 +#define CFG_FPGA_STATUS_TS_IRQ 0x1000 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ + +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h new file mode 100644 index 0000000..aaaafa9 --- /dev/null +++ b/include/configs/CPCI405AB.h @@ -0,0 +1,398 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ +#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ +#define CONFIG_CPCI405AB 1 /* ...and special AB version */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#undef CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/* + * JFFS2 partitions + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ + +/* Use first bank for JFFS2, second bank contains U-Boot. + * + * Note: fake mtd_id's used, no linux mtd map file. + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=cpci405ab-0" +#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)" +*/ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC32) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */ +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/* Use EEPROM for environment variables */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC32 is 4096 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (CAN0, 1) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_LED_ADDR 0xF0000380 + +/* Memory Bank 3 (CompactFlash IDE) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/* Memory Bank 4 (NVRAM/RTC) initialization */ +/*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ +#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ +#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 5 (optional Quart) initialization */ +#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ +#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 6 (FPGA internal) initialization */ +#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ +#define CFG_FPGA_BASE_ADDR 0xF0400000 + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +/* FPGA internal regs */ +#define CFG_FPGA_MODE 0x00 +#define CFG_FPGA_STATUS 0x02 +#define CFG_FPGA_TS 0x04 +#define CFG_FPGA_TS_LOW 0x06 +#define CFG_FPGA_TS_CAP0 0x10 +#define CFG_FPGA_TS_CAP0_LOW 0x12 +#define CFG_FPGA_TS_CAP1 0x14 +#define CFG_FPGA_TS_CAP1_LOW 0x16 +#define CFG_FPGA_TS_CAP2 0x18 +#define CFG_FPGA_TS_CAP2_LOW 0x1a +#define CFG_FPGA_TS_CAP3 0x1c +#define CFG_FPGA_TS_CAP3_LOW 0x1e + +/* FPGA Mode Reg */ +#define CFG_FPGA_MODE_CF_RESET 0x0001 +#define CFG_FPGA_MODE_DUART_RESET 0x0002 +#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ +#define CFG_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */ +#define CFG_FPGA_MODE_SIM_OK_DIR 0x0200 +#define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400 +#define CFG_FPGA_MODE_1WIRE 0x1000 +#define CFG_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */ +#define CFG_FPGA_MODE_TESTRIG_FAIL 0x4000 + +/* FPGA Status Reg */ +#define CFG_FPGA_STATUS_DIP0 0x0001 +#define CFG_FPGA_STATUS_DIP1 0x0002 +#define CFG_FPGA_STATUS_DIP2 0x0004 +#define CFG_FPGA_STATUS_FLASH 0x0008 +#define CFG_FPGA_STATUS_1WIRE 0x1000 +#define CFG_FPGA_STATUS_SIM_OK 0x2000 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ + +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h new file mode 100644 index 0000000..5cd9aba --- /dev/null +++ b/include/configs/CPCI405DT.h @@ -0,0 +1,425 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ +#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) + +#if 0 /* test-only */ +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI + +#ifdef CONFIG_NET_MULTI +#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ +#endif +#endif + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_SUPPORT_VFAT + +#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOOPW 1 /* enable loopw command */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/* Only interrupt boot if special string is typed */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n" +#undef CONFIG_AUTOBOOT_DELAY_STR +#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ +#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/* + * JFFS2 partitions + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ + +/* Use first bank for JFFS2, second bank contains U-Boot. + * + * Note: fake mtd_id's used, no linux mtd map file. + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=cpci405dt-0" +#define MTDPARTS_DEFAULT "mtdparts=cpci405dt-0:-(jffs2)" +*/ + +#if 0 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */ + +#else /* Use EEPROM for environment variables */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ +#endif + +#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (CAN0, 1) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_LED_ADDR 0xF0000380 + +/* Memory Bank 3 (CompactFlash IDE) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/* Memory Bank 4 (NVRAM/RTC) initialization */ +/*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ +#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ +#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 5 (optional Quart) initialization */ +#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ +#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 6 (FPGA internal) initialization */ +#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ +#define CFG_FPGA_BASE_ADDR 0xF0400000 + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +/* FPGA internal regs */ +#define CFG_FPGA_MODE 0x00 +#define CFG_FPGA_STATUS 0x02 +#define CFG_FPGA_TS 0x04 +#define CFG_FPGA_TS_LOW 0x06 +#define CFG_FPGA_TS_CAP0 0x10 +#define CFG_FPGA_TS_CAP0_LOW 0x12 +#define CFG_FPGA_TS_CAP1 0x14 +#define CFG_FPGA_TS_CAP1_LOW 0x16 +#define CFG_FPGA_TS_CAP2 0x18 +#define CFG_FPGA_TS_CAP2_LOW 0x1a +#define CFG_FPGA_TS_CAP3 0x1c +#define CFG_FPGA_TS_CAP3_LOW 0x1e + +/* FPGA Mode Reg */ +#define CFG_FPGA_MODE_CF_RESET 0x0001 +#define CFG_FPGA_MODE_DUART_RESET 0x0002 +#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ +#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 +#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 +#define CFG_FPGA_MODE_TS_CLEAR 0x2000 + +/* FPGA Status Reg */ +#define CFG_FPGA_STATUS_DIP0 0x0001 +#define CFG_FPGA_STATUS_DIP1 0x0002 +#define CFG_FPGA_STATUS_DIP2 0x0004 +#define CFG_FPGA_STATUS_FLASH 0x0008 +#define CFG_FPGA_STATUS_TS_IRQ 0x1000 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ + +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h new file mode 100644 index 0000000..a5bc773 --- /dev/null +++ b/include/configs/CPCI440.h @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2002 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * board/config_CPCI440.h - configuration for esd CPCI-440 board + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_EBONY 1 /* Board is ebony */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ +#if 1 +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#else +#define CFG_MONITOR_BASE 0x01fc0000 /* start of monitor */ +#endif +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ + +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */ +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#if 1 /* test-only */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#undef CFG_FLASH_BASE +#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/ + +#else /* test-only */ + +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 32 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#endif + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#if 0 /* test-only */ +#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ +#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ + +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) +#else + +#if 0 /* test-only */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ +#else +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#endif + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BAUDRATE 9600 + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#if 0 /* test-only */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_KGDB | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF ) +#else +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM ) +/* test-only: support fehlt bisher... */ +/* CFG_CMD_IDE | \*/ +/* CFG_CMD_PCI | \*/ +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#if 0 /* test-only */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#endif + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#if 0 +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h new file mode 100644 index 0000000..8bfd0ee --- /dev/null +++ b/include/configs/CPCI750.h @@ -0,0 +1,598 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +/************************************************************************* + * (c) 2004 esd gmbh Hannover + * + * + * from db64360.h file + * by Reinhard Arlt reinhard.arlt@esd-electronics.com + * + ************************************************************************/ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* This define must be before the core.h include */ +#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ + +#ifndef __ASSEMBLY__ +#include <../board/Marvell/include/core.h> +#endif +/*-----------------------------------------------------*/ + +#include "../board/esd/cpci750/local.h" + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_750FX /* we have a 750FX (override local.h) */ + +#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ + +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ + +#undef CONFIG_ECC /* enable ECC support */ + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_PRE_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#define CFG_BOARD_NAME "CPCI750" +#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" + +/*#define CFG_HUSH_PARSER*/ +#undef CFG_HUSH_PARSER + +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Define which ETH port will be used for connecting the network */ +#define CFG_ETH_PORT ETH_0 + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial + * cable onto the second DUART channel, change the CFG_DUART port from 1 + * to 0 below. + * + * to use the MPSC, #define CONFIG_MPSC. If you have wired up another + * mpsc channel, change CONFIG_MPSC_PORT to the desired value. + */ +#define CONFIG_MPSC +#define CONFIG_MPSC_PORT 0 + +/* to change the default ethernet port, use this define (options: 0, 1, 2) */ +#define CONFIG_NET_MULTI +#define MV_ETH_DEVS 1 +#define CONFIG_ETHER_PORT 0 + +#undef CONFIG_ETHER_PORT_MII /* use RMII */ + +#define CONFIG_BOOTDELAY 5 /* autoboot disabled */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK + + +#undef CONFIG_BOOTARGS + +/* ----------------------------------------------------------------------------- + * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus + */ + +#define CONFIG_IPADDR "192.168.0.185" + +#define CONFIG_SERIAL "AA000001" +#define CONFIG_SERVERIP "10.0.0.79" +#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" + +#define CONFIG_TESTDRAMDATA y +#define CONFIG_TESTDRAMADDRESS n +#define CONFIG_TESETDRAMWALK n + +/* ----------------------------------------------------------------------------- */ + + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_ALTIVEC /* undef to disable */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C \ + | CFG_CMD_CACHE \ + | CFG_CMD_EEPROM \ + | CFG_CMD_PCI \ + | CFG_CMD_ELF \ + | CFG_CMD_DATE \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_IDE \ + | CFG_CMD_FAT \ + | CFG_CMD_EXT2 \ + ) + +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_SPEED 80000 /* I2C speed default */ + +#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */ +/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ +/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ + +/* +#define CFG_DRAM_TEST + * DRAM tests + * CFG_DRAM_TEST - enables the following tests. + * + * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely + * addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. + */ +#define CFG_DRAM_TEST +#if defined(CFG_DRAM_TEST) +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_DRAM_TEST_DATA +#define CFG_DRAM_TEST_ADDRESS +#define CFG_DRAM_TEST_WALK +#endif /* CFG_DRAM_TEST */ + +#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ +#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ + +#define CFG_LOAD_ADDR 0x00300000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ +#define CFG_BUS_CLK CFG_BUS_HZ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_TCLK 133000000 + +/*#define CFG_750FX_HID0 0x8000c084*/ +#define CFG_750FX_HID0 0x80008484 +#define CFG_750FX_HID1 0x54800000 +#define CFG_750FX_HID2 0x00000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + + /* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized +*/ +#undef CFG_INIT_RAM_LOCK +/* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ +/* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ +#define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#define RELOCATE_INTERNAL_RAM_ADDR +#ifdef RELOCATE_INTERNAL_RAM_ADDR +/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/ +#define CFG_INTERNAL_RAM_ADDR 0xf1080000 +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +/* Dummies for BAT 4-7 */ +#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ +#define CFG_SDRAM2_BASE 0x20000000 +#define CFG_SDRAM3_BASE 0x30000000 +#define CFG_SDRAM4_BASE 0x40000000 +#define CFG_RESET_ADDRESS 0xfff00100 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE 0xfff00000 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ +#define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */ +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ + +/* areas to map different things with the GT in physical space */ +#define CFG_DRAM_BANKS 4 + +/* What to put in the bats. */ +#define CFG_MISC_REGION_BASE 0xf0000000 + +/* Peripheral Device section */ + +/*******************************************************/ +/* We have on the cpci750 Board : */ +/* GT-Chipset Register Area */ +/* GT-Chipset internal SRAM 256k */ +/* SRAM on external device module */ +/* Real time clock on external device module */ +/* dobble UART on external device module */ +/* Data flash on external device module */ +/* Boot flash on external device module */ +/*******************************************************/ +#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ +#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ + +#undef MARVEL_STANDARD_CFG +#ifndef MARVEL_STANDARD_CFG +/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ +/*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ +#define CFG_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ + +#define CFG_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ +#define CFG_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ +#define CFG_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ +#define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ +#define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ + +#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */ +#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */ +#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */ +#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */ +#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */ + +/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +#endif + +/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ +#define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ +#define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ +#define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ +#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */ +#define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ + + /* c 4 a 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ + /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ + /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ + + +/* MPP Control MV64360 Appendix P P. 632*/ +#define CFG_MPP_CONTROL_0 0x00002222 /* */ +#define CFG_MPP_CONTROL_1 0x11110000 /* */ +#define CFG_MPP_CONTROL_2 0x11111111 /* */ +#define CFG_MPP_CONTROL_3 0x00001111 /* */ +/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */ + + +#define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ + +/* setup new config_value for MV64360 DDR-RAM To_do !! */ +/*# define CFG_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ +/*# define CFG_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ + /* GB has high prio. + idma has low prio + MPSC has low prio + pci has low prio 1 and 2 + cpu has high prio + Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices + ECC disable + non registered DRAM */ + /* 31:26 25:22 21:20 19 18 17 16 */ + /* 100001 0000 010 0 0 0 0 */ + /* refresh_count=0x400 + phisical interleaving disable + virtual interleaving enable */ + /* 15 14 13:0 */ + /* 0 1 0x400 */ +# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ + +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ + +/* PCI MEMORY MAP section */ +#define CFG_PCI0_MEM_BASE 0x80000000 +#define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI1_MEM_BASE 0x88000000 +#define CFG_PCI1_MEM_SIZE _128M + +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) +#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) + +/* PCI I/O MAP section */ +#define CFG_PCI0_IO_BASE 0xfa000000 +#define CFG_PCI0_IO_SIZE _16M +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M + +#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) +#define CFG_PCI0_IO_SPACE_PCI 0x00000000 +#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) +#define CFG_PCI1_IO_SPACE_PCI 0x00000000 + +#if defined (CONFIG_750CX) +#define CFG_PCI_IDSEL 0x0 +#else +#define CFG_PCI_IDSEL 0x30 +#endif + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET /* no reset for ide supported */ +#define CONFIG_IDE_PREINIT /* check for units */ + +#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0 +#define CFG_ATA_IDE0_OFFSET 0 +#define CFG_ATA_IDE1_OFFSET 0 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + + +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITE_THRU not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT0U CFG_IBAT0U + +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI0, PCI1 in one BAT */ +#define CFG_IBAT2L BATL_NO_ACCESS +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* GT regs, bootrom, all the devices, PCI I/O */ +#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* + * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) + * IBAT4 and DBAT4 + * FIXME: ingo disable BATs for Linux Kernel + */ +#undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */ +/*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */ + +#ifdef SETUP_HIGH_BATS_FX750 +#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U CFG_IBAT4U + +/* IBAT5 and DBAT5 */ +#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT5U CFG_IBAT5U + +/* IBAT6 and DBAT6 */ +#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U CFG_IBAT6U + +/* IBAT7 and DBAT7 */ +#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT7U CFG_IBAT7U + +#else /* set em out of range for Linux !!!!!!!!!!! */ +#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U CFG_IBAT4U + +/* IBAT5 and DBAT5 */ +#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT5U CFG_IBAT4U + +/* IBAT6 and DBAT6 */ +#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U CFG_IBAT4U + +/* IBAT7 and DBAT7 */ +#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT7U CFG_IBAT4U + +#endif +/* FIXME: ingo end: disable BATs for Linux Kernel */ + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x51 +#define DIMM1_I2C_ADDR 0x52 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ + +#if 0 +#define CFG_ENV_IS_IN_FLASH 0 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ +/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ +#endif + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CFG_I2C_EEPROM_ADDR 0x050 +#define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ + +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/mpc74xx.h for the defines used here + */ + +/*#define CFG_L2*/ +#undef CFG_L2 + +/* #ifdef CONFIG_750CX*/ +#if defined (CONFIG_750CX) || defined (CONFIG_750FX) +#define L2_INIT 0 +#else +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#endif + +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_BOARD_ASM_INIT 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h new file mode 100644 index 0000000..93d49f3 --- /dev/null +++ b/include/configs/CPCIISER4.h @@ -0,0 +1,243 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND "bootm fff00000" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffe00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC08) for environment + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ + /* total size of a CAT24WC08 is 1024 bytes */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Uart 8bit) initialization */ +#define CFG_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */ +#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (Uart 32bit) initialization */ +#define CFG_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */ +#define CFG_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ + +/* Memory Bank 3 (FPGA Reset) initialization */ +#define CFG_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */ +#define CFG_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h new file mode 100644 index 0000000..16a9ea5 --- /dev/null +++ b/include/configs/CPU86.h @@ -0,0 +1,656 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_CPU86 1 /* ...on a CPU86 board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 9600 +#endif + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) + +/* + * - Rx-CLK is CLK11 + * - Tx-CLK is CLK12 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 64000000 /* in Hz */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT \ + "echo; " \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \ + "echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +/*----------------------------------------------------------------------- + * I2C/EEPROM/RTC configuration + */ +#define CONFIG_SOFT_I2C /* Software I2C support enabled */ + +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xFE +/* + * Software (bit-bang) I2C driver configuration + */ +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Disk-On-Chip configuration + */ + +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM + +/*----------------------------------------------------------------------- + * Miscellaneous configuration options + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Flash configuration + */ + +#define CFG_BOOTROM_BASE 0xFF800000 +#define CFG_BOOTROM_SIZE 0x00080000 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 0x00800000 + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/*----------------------------------------------------------------------- + * Other areas to be mapped + */ + +/* CS3: Dual ported SRAM */ +#define CFG_DPSRAM_BASE 0x40000000 +#define CFG_DPSRAM_SIZE 0x00020000 + +/* CS4: DiskOnChip */ +#define CFG_DOC_BASE 0xF4000000 +#define CFG_DOC_SIZE 0x00100000 + +/* CS5: FDC37C78 controller */ +#define CFG_FDC37C78_BASE 0xF1000000 +#define CFG_FDC37C78_SIZE 0x00100000 + +/* CS6: Board configuration registers */ +#define CFG_BCRS_BASE 0xF2000000 +#define CFG_BCRS_SIZE 0x00010000 + +/* CS7: VME Extended Access Range */ +#define CFG_VMEEAR_BASE 0x80000000 +#define CFG_VMEEAR_SIZE 0x01000000 + +/* CS8: VME Standard Access Range */ +#define CFG_VMESAR_BASE 0xFE000000 +#define CFG_VMESAR_SIZE 0x01000000 + +/* CS9: VME Short I/O Access Range */ +#define CFG_VMESIOAR_BASE 0xFD000000 +#define CFG_VMESIOAR_SIZE 0x01000000 + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#if defined(CONFIG_BOOT_ROM) +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ + HRCW_BPS01 | HRCW_CS10PC01) +#else +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) +#endif + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#if 0 +/* environment is in Flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#ifdef CONFIG_BOOT_ROM +# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000) +# define CFG_ENV_SIZE 0x10000 +# define CFG_ENV_SECT_SIZE 0x10000 +#endif +#else +/* environment is in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (2048 - 512) +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ + HID0_DCI|HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define BCR_APD01 0x10000000 +#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ + SIUMCR_CS10PC01|SIUMCR_BCTLC10) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR SCCR_DFBRG01 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +#define CFG_MIN_AM_MASK 0xC0000000 +/*----------------------------------------------------------------------- + * MPTPR - Memory Refresh Timer Prescaler Register 10-18 + *----------------------------------------------------------------------- + */ +#define CFG_MPTPR 0x1F00 + +/*----------------------------------------------------------------------- + * PSRT - Refresh Timer Register 10-16 + *----------------------------------------------------------------------- + */ +#define CFG_PSRT 0x0f + +/*----------------------------------------------------------------------- + * PSRT - SDRAM Mode Register 10-10 + *----------------------------------------------------------------------- + */ + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A10 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_1W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_1W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 8 bit Boot ROM + * 1 60x GPCM 64 bit FLASH + * 2 60x SDRAM 64 bit SDRAM + * + */ + +#define CFG_MRS_OFFS 0x00000000 + +#ifdef CONFIG_BOOT_ROM +/* Bank 0 - Boot ROM + */ +#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 1 - FLASH + */ +#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + +#else /* CONFIG_BOOT_ROM */ +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 1 - Boot ROM + */ +#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + +#endif /* CONFIG_BOOT_ROM */ + + +/* Bank 2 - 60x bus SDRAM + */ +#ifndef CFG_RAMBOOT +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR2_PRELIM CFG_OR2_9COL + +#define CFG_PSDMR CFG_PSDMR_9COL +#endif /* CFG_RAMBOOT */ + +/* Bank 3 - Dual Ported SRAM + */ +#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) + +/* Bank 4 - DiskOnChip + */ +#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 5 - FDC37C78 controller + */ +#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_8_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 6 - Board control registers + */ +#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ + ORxG_CSNT |\ + ORxG_SCY_5_CLK) + +/* Bank 7 - VME Extended Access Range + */ +#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) + +/* Bank 8 - VME Standard Access Range + */ +#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) + +/* Bank 9 - VME Short I/O Access Range + */ +#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) + +#endif /* __CONFIG_H */ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h new file mode 100644 index 0000000..a23d7e5 --- /dev/null +++ b/include/configs/CPU87.h @@ -0,0 +1,682 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_CPU87 1 /* ...on a CPU87 board */ +#define CONFIG_PCI +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 9600 +#endif + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) + +/* + * - Rx-CLK is CLK11 + * - Tx-CLK is CLK12 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 100000000 /* in Hz */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT \ + "echo; " \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \ + "echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +/*----------------------------------------------------------------------- + * I2C/EEPROM/RTC configuration + */ +#define CONFIG_SOFT_I2C /* Software I2C support enabled */ + +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xFE +/* + * Software (bit-bang) I2C driver configuration + */ +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Disk-On-Chip configuration + */ + +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM + +/*----------------------------------------------------------------------- + * Miscellaneous configuration options + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#ifdef CONFIG_PCI +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_PCI) +#else /* ! PCI */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C ) +#endif /* CONFIG_PCI */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ + +#define CONFIG_LOOPW + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Flash configuration + */ + +#define CFG_BOOTROM_BASE 0xFF800000 +#define CFG_BOOTROM_SIZE 0x00080000 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 0x00800000 + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/*----------------------------------------------------------------------- + * Other areas to be mapped + */ + +/* CS3: Dual ported SRAM */ +#define CFG_DPSRAM_BASE 0x40000000 +#define CFG_DPSRAM_SIZE 0x00100000 + +/* CS4: DiskOnChip */ +#define CFG_DOC_BASE 0xF4000000 +#define CFG_DOC_SIZE 0x00100000 + +/* CS5: FDC37C78 controller */ +#define CFG_FDC37C78_BASE 0xF1000000 +#define CFG_FDC37C78_SIZE 0x00100000 + +/* CS6: Board configuration registers */ +#define CFG_BCRS_BASE 0xF2000000 +#define CFG_BCRS_SIZE 0x00010000 + +/* CS7: VME Extended Access Range */ +#define CFG_VMEEAR_BASE 0x60000000 +#define CFG_VMEEAR_SIZE 0x01000000 + +/* CS8: VME Standard Access Range */ +#define CFG_VMESAR_BASE 0xFE000000 +#define CFG_VMESAR_SIZE 0x01000000 + +/* CS9: VME Short I/O Access Range */ +#define CFG_VMESIOAR_BASE 0xFD000000 +#define CFG_VMESIOAR_SIZE 0x01000000 + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#if defined(CONFIG_BOOT_ROM) +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ + HRCW_BPS01 | HRCW_CS10PC01) +#else +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) +#endif + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#ifdef CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#endif + +#if 0 +/* environment is in Flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#ifdef CONFIG_BOOT_ROM +# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000) +# define CFG_ENV_SIZE 0x10000 +# define CFG_ENV_SECT_SIZE 0x10000 +#endif +#else +/* environment is in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (2048 - 512) +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ + HID0_DCI|HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define BCR_APD01 0x10000000 +#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ + SIUMCR_CS10PC01|SIUMCR_BCTLC10) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR SCCR_DFBRG01 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +#define CFG_MIN_AM_MASK 0xC0000000 + +/* + * we use the same values for 32 MB and 128 MB SDRAM + * refresh rate = 7.68 uS (100 MHz Bus Clock) + */ + +/*----------------------------------------------------------------------- + * MPTPR - Memory Refresh Timer Prescaler Register 10-18 + *----------------------------------------------------------------------- + */ +#define CFG_MPTPR 0x2000 + +/*----------------------------------------------------------------------- + * PSRT - Refresh Timer Register 10-16 + *----------------------------------------------------------------------- + */ +#define CFG_PSRT 0x16 + +/*----------------------------------------------------------------------- + * PSRT - SDRAM Mode Register 10-10 + *----------------------------------------------------------------------- + */ + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A10 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 8 bit Boot ROM + * 1 60x GPCM 64 bit FLASH + * 2 60x SDRAM 64 bit SDRAM + * + */ + +#define CFG_MRS_OFFS 0x00000000 + +#ifdef CONFIG_BOOT_ROM +/* Bank 0 - Boot ROM + */ +#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 1 - FLASH + */ +#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxU_EHTR_8IDLE) + +#else /* CONFIG_BOOT_ROM */ +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 1 - Boot ROM + */ +#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxU_EHTR_8IDLE) + +#endif /* CONFIG_BOOT_ROM */ + + +/* Bank 2 - 60x bus SDRAM + */ +#ifndef CFG_RAMBOOT +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR2_PRELIM CFG_OR2_9COL + +#define CFG_PSDMR CFG_PSDMR_9COL +#endif /* CFG_RAMBOOT */ + +/* Bank 3 - Dual Ported SRAM + */ +#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_7_CLK |\ + ORxG_SETA) + +/* Bank 4 - DiskOnChip + */ +#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_9_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 5 - FDC37C78 controller + */ +#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_10_CLK |\ + ORxU_EHTR_8IDLE) + +/* Bank 6 - Board control registers + */ +#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ + ORxG_CSNT |\ + ORxG_SCY_7_CLK) + +/* Bank 7 - VME Extended Access Range + */ +#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_7_CLK |\ + ORxG_SETA) + +/* Bank 8 - VME Standard Access Range + */ +#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_7_CLK |\ + ORxG_SETA) + +/* Bank 9 - VME Short I/O Access Range + */ +#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_7_CLK |\ + ORxG_SETA) + +#endif /* __CONFIG_H */ diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h new file mode 100644 index 0000000..63d7a92 --- /dev/null +++ b/include/configs/CRAYL1.h @@ -0,0 +1,247 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite.. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_CRAYL1 +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC405 family */ +#define CONFIG_SYS_CLK_FREQ 25000000 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */ +#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ + +/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to + * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) + #define CONFIG_PRAM 16 + */ +#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */ +#undef CONFIG_BOOTARGS + +/* Bootcmd is overridden by the bootscript in board/cray/L1 + */ +#define CFG_AUTOLOAD "no" +#define CONFIG_BOOTCOMMAND "dhcp" + +/* + * ..during experiments.. + #define CONFIG_SERVERIP 10.0.0.1 + #define CONFIG_ETHADDR 00:40:a6:80:14:5 + */ +#define CONFIG_HARD_I2C 1 /* hardware support for i2c */ +#define CONFIG_SDRAM_BANK0 1 +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_IDENT_STRING "Cray L1" +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTOSCRIPT 1 + + +#define CONFIG_COMMANDS (\ + CFG_CMD_BDI|\ + CFG_CMD_IMI|\ + CFG_CMD_FLASH|\ + CFG_CMD_MEMORY|\ + CFG_CMD_NET|\ + CFG_CMD_ENV|\ + CFG_CMD_CONSOLE|\ + CFG_CMD_ASKENV|\ + CFG_CMD_ECHO|\ + CFG_CMD_IMMAP|\ + CFG_CMD_REGINFO|\ + CFG_CMD_DHCP|\ + CFG_CMD_DATE|\ + CFG_CMD_RUN|\ + CFG_CMD_I2C|\ + CFG_CMD_EEPROM|\ + CFG_CMD_DIAG|\ + CFG_CMD_AUTOSCRIPT|\ + CFG_CMD_SETGETDCR) + +/* + * optional BOOTP / DHCP fields + */ +#define CONFIG_BOOTP_MASK (\ + CONFIG_BOOTP_VENDOREX|\ + CONFIG_BOOTP_SUBNETMASK|\ + CONFIG_BOOTP_GATEWAY|\ + CONFIG_BOOTP_DNS|\ + CONFIG_BOOTP_HOSTNAME|\ + CONFIG_BOOTP_BOOTFILESIZE|\ + CONFIG_BOOTP_BOOTPATH) + +/* + * how many time to fail & restart a net-TFTP before giving up & resetting + * the board hoping that a reset of net interface might help.. + */ +#define CONFIG_NET_RESET 5 + +/* + * bauds. Just to make it compile; in our case, I read the base_baud + * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn + * drives the system clock. + */ +#define CFG_BASE_BAUD 403225 +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ + + +#define CFG_LOAD_ADDR 0x100000/* where to load what we get from TFTP */ +#define CFG_TFTP_LOADADDR CFG_LOAD_ADDR +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CFG_DRAM_TEST 1 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_BASE TEXT_BASE + + +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */ +#define CFG_ENV_OFFSET 0x3c8000 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment area */ +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ + +/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at + * 32meg-(128k+some_malloc_space+copy-of-ENV sector).. + */ +#define CFG_SDRAM_SIZE 32 /* megs of ram */ +#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ + /* the exception vector table */ + /* to the end of the DRAM */ + /* less monitor and malloc area */ +#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ +#define CFG_MALLOC_LEN (128 << 10) /* 128k for malloc space */ +#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ + + CFG_MALLOC_LEN \ + + CFG_ENV_SECT_SIZE \ + + CFG_STACK_USAGE ) + +#define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE) +/* END ENVIRONNEMENT FLASH */ + +/*----------------------------------------------------------------------- + * Cache Configuration. Only used to ..?? clear it, I guess.. + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in OnChipMem ) + */ +#if 1 +/* On Chip Memory location */ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR 0xF0000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#else +#define CFG_OCM_DATA_ADDR 0xF0000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#endif + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + */ +#define EEPROM_WRITE_ADDRESS 0xA0 +#define EEPROM_READ_ADDRESS 0xA1 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/CU824.h b/include/configs/CU824.h new file mode 100644 index 0000000..acc8484 --- /dev/null +++ b/include/configs/CU824.h @@ -0,0 +1,312 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the CU824 board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8240 1 +#define CONFIG_CU824 1 + + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + 0 /* CFG_CMD_DATE */ | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#if 1 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFCE00000 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + + /* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x10000000 + + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + + /* Size in bytes reserved for initial data + */ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 4 + +#define CFG_NS16550_CLK (14745600 / 2) + +#define CFG_NS16550_COM1 0xFE800080 +#define CFG_NS16550_COM2 0xFE8000C0 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 +#define CFG_HZ 1000 + + /* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 7 + + /* Bit-field values for MCCR2. + */ +#define CFG_REFINT 430 /* Refresh interval */ + + /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 192 + + /* Bit-field values for MCCR3. + */ +#define CFG_REFREC 2 /* Refresh to activate interval */ +#define CFG_RDLAT 3 /* Data latancy from read command */ + + /* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ +#define CFG_ACTORW 2 +#define CFG_REGISTERD_TYPE_BUFFER 1 + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0xff + +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + + /* Warining: environment is not EMBEDDED in the U-Boot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 +#if 0 +#define CFG_ENV_ADDR 0xFF008000 +#define CFG_ENV_SIZE 0x8000 /* Size of the Environment Sector */ +#else +#define CFG_ENV_ADDR 0xFFFC0000 +#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */ +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP +#define CONFIG_TULIP_USE_IO + +#define CFG_ETH_DEV_FN 0x7800 +#define CFG_ETH_IOBASE 0x00104000 + +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define PCI_ENET0_IOADDR 0x00104000 +#define PCI_ENET0_MEMADDR 0x80000000 +#endif /* __CONFIG_H */ diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h new file mode 100644 index 0000000..997e1ba --- /dev/null +++ b/include/configs/DASA_SIM.h @@ -0,0 +1,208 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ +#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_CPUCLOCK 66 +#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */ + +#undef CONFIG_BOOTARGS + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_IPADDR 10.0.18.222 +#define CONFIG_SERVERIP 10.0.18.190 + +#if 0 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_BSP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ELF ) +#else +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP ) +#endif + +#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */ +#define CONFIG_SOFT_I2C /* Software I2C support enabled */ +#endif +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 128 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0002 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0000 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0004 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ + +#if 0 +#define CFG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ +#else +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ +#endif + +/*----------------------------------------------------------------------- + * PCI stuff + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP + +#define CFG_ETH_DEV_FN 0x0000 +#define CFG_ETH_IOBASE 0x0fff0000 +#define CFG_PCI9054_DEV_FN 0x0800 +#define CFG_PCI9054_IOBASE 0x0eff0000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h new file mode 100644 index 0000000..bd7aff1 --- /dev/null +++ b/include/configs/DB64360.h @@ -0,0 +1,596 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +/************************************************************************* + * (c) 2002 Datentechnik AG - Project: Dino + * + * + * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $ + * + ************************************************************************/ + +/************************************************************************* + * + * History: + * + * $Log: DB64360.h,v $ + * Revision 1.3 2003/04/26 04:58:13 brad + * Cosmetic changes and compiler warning cleanups + * + * Revision 1.2 2003/04/23 15:48:15 ingo + * mem. map output added + * + * Revision 1.1 2003/04/17 09:31:42 ias + * keymile changes 17_04_2003 + * + * Revision 1.10 2003/03/06 12:25:04 ias + * 750 FX CPU HID settings updated + * + * Revision 1.9 2003/03/03 16:14:36 ias + * cleanup compiler warnings of printf fuctions + * + * Revision 1.8 2003/03/03 15:11:44 ias + * Marvell MPSC-UART is working + * + * Revision 1.7 2003/02/26 12:15:45 ssu + * adapted default parameters to new board flash address + * + * Revision 1.6 2003/02/25 14:55:42 ssu + * changed default environment parameters + * + * Revision 1.5 2003/02/21 17:14:23 ias + * added extended SPD handling + * + * Revision 1.4 2003/01/14 09:16:08 ias + * PPCBoot for Marvel Beta 0.9 + * + * Revision 1.3 2002/12/03 13:56:26 ias + * Environment in flash support added + * + * Revision 1.2 2002/11/29 16:53:29 ias + * Flash support for STM added + * + * Revision 1.1 2002/11/29 13:36:31 ias + * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board + * - working DDRRAM (only 32MByte of 128MB Modul) + * - working I2C Driver for SPD EEPROM read + * - working DUART 16650 for Serial Console + * - working "console" + * + * + * + ************************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* This define must be before the core.h include */ +#define CONFIG_DB64360 1 /* this is an DB64360 board */ + +#ifndef __ASSEMBLY__ +#include "../board/Marvell/include/core.h" +#endif + +/*-----------------------------------------------------*/ +/* #include "../board/db64360/local.h" */ +#ifndef __LOCAL_H +#define __LOCAL_H + +/* first ethernet */ +#define CONFIG_ETHADDR 64:36:00:00:00:01 + /* next two ethernet hwaddrs */ +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 64:36:00:00:00:02 +/* in the atlantis 64360 we have only 2 ETH port on the board, +if we use PCI it has its own MAC addr */ + +#define CONFIG_ENV_OVERWRITE +#endif /* __CONFIG_H */ + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_74xx /* we have a 750FX (override local.h) */ + +#define CONFIG_DB64360 1 /* this is an DB64360 board */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ +/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the + DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. + so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, + see sdram_init.c */ +#undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_MV64360_ECC + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ +#define CONFIG_BOARD_EARLY_INIT_F + +#define CFG_BOARD_NAME "DB64360" +#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)" + +/*#define CFG_HUSH_PARSER */ +#undef CFG_HUSH_PARSER + +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial + * cable onto the second DUART channel, change the CFG_DUART port from 1 + * to 0 below. + * + * to use the MPSC, #define CONFIG_MPSC. If you have wired up another + * mpsc channel, change CONFIG_MPSC_PORT to the desired value. + */ + +#define CONFIG_MPSC_PORT 0 + +/* to change the default ethernet port, use this define (options: 0, 1, 2) */ +#define CONFIG_NET_MULTI +#define MV_ETH_DEVS 2 + +/* #undef CONFIG_ETHER_PORT_MII */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK + + +#undef CONFIG_BOOTARGS +/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ + +/* ronen - autoboot using tftp */ +#if (CONFIG_BOOTDELAY >= 0) +#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ + setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ + ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " + +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#endif + +/* ronen - the u-boot.bin should be ~0x30000 bytes */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ +cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ + "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ +cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ + "bootargs_root=root=/dev/nfs rw\0" \ + "bootargs_end=:::DB64360:eth0:none \0"\ + "ethprime=mv_enet0\0"\ + "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ +ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" + +/* --------------------------------------------------------------------------------------------------------------- */ +/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */ + +#define CONFIG_IPADDR 10.2.40.90 + +#define CONFIG_SERIAL "No. 1" +#define CONFIG_SERVERIP 10.2.1.126 +#define CONFIG_ROOTPATH /mnt/yellow_dog_mini + + +#define CONFIG_TESTDRAMDATA y +#define CONFIG_TESTDRAMADDRESS n +#define CONFIG_TESETDRAMWALK n + +/* --------------------------------------------------------------------------------------------------------------- */ + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_ALTIVEC /* undef to disable */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor1" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ + +/* Use first bank for JFFS2, second bank contains U-Boot. + * + * Note: fake mtd_id's used, no linux mtd map file. + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor1=db64360-1" +#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" +*/ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_CACHE \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_PCI \ + | CFG_CMD_NET ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_SPEED 40000 /* I2C speed default */ + +/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/*#define CFG_MEMTEST_START 0x00400000 memtest works on */ +/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ +/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ + +/* +#define CFG_DRAM_TEST + * DRAM tests + * CFG_DRAM_TEST - enables the following tests. + * + * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely + * addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. + */ +#define CFG_DRAM_TEST +#if defined(CFG_DRAM_TEST) +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_DRAM_TEST_DATA +#define CFG_DRAM_TEST_ADDRESS +#define CFG_DRAM_TEST_WALK +#endif /* CFG_DRAM_TEST */ + +#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ +#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ + +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ +#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ +#define CFG_BUS_CLK CFG_BUS_HZ + +#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ +#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ + +/*ronen - this is the Tclk (MV64360 core) */ +#define CFG_TCLK 133000000 + + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_750FX_HID0 0x8000c084 +#define CFG_750FX_HID1 0x54800000 +#define CFG_750FX_HID2 0x00000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized +*/ +#define CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#define RELOCATE_INTERNAL_RAM_ADDR +#ifdef RELOCATE_INTERNAL_RAM_ADDR + #define CFG_INTERNAL_RAM_ADDR 0xf8000000 +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +/* Dummies for BAT 4-7 */ +#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ +#define CFG_SDRAM2_BASE 0x20000000 +#define CFG_SDRAM3_BASE 0x30000000 +#define CFG_SDRAM4_BASE 0x40000000 +#define CFG_FLASH_BASE 0xfff00000 + +#define CFG_DFL_BOOTCS_BASE 0xff800000 +#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ + +#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ +#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ +#define PCI0_IO_BASE_BOOTM 0xfd000000 + +#define CFG_RESET_ADDRESS 0xfff00100 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +/* areas to map different things with the GT in physical space */ +#define CFG_DRAM_BANKS 4 + +/* What to put in the bats. */ +#define CFG_MISC_REGION_BASE 0xf0000000 + +/* Peripheral Device section */ + +/*******************************************************/ +/* We have on the db64360 Board : */ +/* GT-Chipset Register Area */ +/* GT-Chipset internal SRAM 256k */ +/* SRAM on external device module */ +/* Real time clock on external device module */ +/* dobble UART on external device module */ +/* Data flash on external device module */ +/* Boot flash on external device module */ +/*******************************************************/ +#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ +#define CFG_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ + +/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ +#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */ + +#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */ +#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ +#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ +#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */ + +#define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ +#define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ +#define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ +#define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ +/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ + +/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ +#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ +#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ +#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ +#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ +#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ + + /* c 4 a 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ + /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ + /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ + + +/* ronen - update MPP Control MV64360*/ +#define CFG_MPP_CONTROL_0 0x02222222 +#define CFG_MPP_CONTROL_1 0x11333011 +#define CFG_MPP_CONTROL_2 0x40431111 +#define CFG_MPP_CONTROL_3 0x00000044 + +/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ + + +# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ + /* gpp[31] gpp[30] gpp[29] gpp[28] */ + /* gpp[27] gpp[24]*/ + /* gpp[19:14] */ + +/* setup new config_value for MV64360 DDR-RAM !! */ +# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ + +#define CFG_DUART_IO CFG_DEV2_SPACE +#define CFG_DUART_CHAN 1 /* channel to use for console */ +#define CFG_INIT_CHAN1 +#define CFG_INIT_CHAN2 + +#define SRAM_BASE CFG_DEV0_SPACE +#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ + +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ + +/* PCI MEMORY MAP section */ +#define CFG_PCI0_MEM_BASE 0x80000000 +#define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI1_MEM_BASE 0x88000000 +#define CFG_PCI1_MEM_SIZE _128M + +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) +#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) + +/* PCI I/O MAP section */ +#define CFG_PCI0_IO_BASE 0xfa000000 +#define CFG_PCI0_IO_SIZE _16M +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M + +#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) +#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ +#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) +#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ + +#if defined (CONFIG_750CX) +#define CFG_PCI_IDSEL 0x0 +#else +#define CFG_PCI_IDSEL 0x30 +#endif +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITE_THRU not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT0U CFG_IBAT0U + +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI0, PCI1 in one BAT */ +#define CFG_IBAT2L BATL_NO_ACCESS +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* GT regs, bootrom, all the devices, PCI I/O */ +#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x56 +#define DIMM1_I2C_ADDR 0x54 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ +#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ +#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ +#define CFG_FLASH_CFI 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ +/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/mpc74xx.h for the defines used here + */ + +#define CFG_L2 + + +#if defined (CONFIG_750CX) || defined (CONFIG_750FX) +#define L2_INIT 0 +#else + +#define L2_INIT 0 +/* +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +*/ +#endif + +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_BOARD_ASM_INIT 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h new file mode 100644 index 0000000..4b72e9b --- /dev/null +++ b/include/configs/DB64460.h @@ -0,0 +1,534 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* This define must be before the core.h include */ +#define CONFIG_DB64460 1 /* this is an DB64460 board */ + +#ifndef __ASSEMBLY__ +#include "../board/Marvell/include/core.h" +#endif + +/*-----------------------------------------------------*/ +/* #include "../board/db64460/local.h" */ +#ifndef __LOCAL_H +#define __LOCAL_H + +#define CONFIG_ETHADDR 64:46:00:00:00:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 64:46:00:00:00:02 +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 64:46:00:00:00:03 + +#define CONFIG_ENV_OVERWRITE +#endif /* __CONFIG_H */ + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_74xx /* we have a 750FX (override local.h) */ + +#define CONFIG_DB64460 1 /* this is an DB64460 board */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ +/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the + DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. + so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, + see sdram_init.c */ +#undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_MV64460_ECC + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ +#define CONFIG_BOARD_EARLY_INIT_F + +#define CFG_BOARD_NAME "DB64460" +#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)" + +/*#define CFG_HUSH_PARSER */ +#undef CFG_HUSH_PARSER + +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial + * cable onto the second DUART channel, change the CFG_DUART port from 1 + * to 0 below. + * + * to use the MPSC, #define CONFIG_MPSC. If you have wired up another + * mpsc channel, change CONFIG_MPSC_PORT to the desired value. + */ + +#define CONFIG_MPSC_PORT 0 + +/* to change the default ethernet port, use this define (options: 0, 1, 2) */ +#define CONFIG_NET_MULTI +#define MV_ETH_DEVS 3 + +/* #undef CONFIG_ETHER_PORT_MII */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK + + +#undef CONFIG_BOOTARGS +/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ + +/* ronen - autoboot using tftp */ +#if (CONFIG_BOOTDELAY >= 0) +#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ + setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ + ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " + +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#endif + +/* ronen - the u-boot.bin should be ~0x30000 bytes */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ +cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ + "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ +cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ + "bootargs_root=root=/dev/nfs rw\0" \ + "bootargs_end=:::DB64460:eth0:none \0"\ + "ethprime=mv_enet0\0"\ + "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ +ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" + +/* --------------------------------------------------------------------------------------------------------------- */ +/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */ + +#define CONFIG_IPADDR 10.2.40.90 + +#define CONFIG_SERIAL "No. 1" +#define CONFIG_SERVERIP 10.2.1.126 +#define CONFIG_ROOTPATH /mnt/yellow_dog_mini + + +#define CONFIG_TESTDRAMDATA y +#define CONFIG_TESTDRAMADDRESS n +#define CONFIG_TESETDRAMWALK n + +/* --------------------------------------------------------------------------------------------------------------- */ + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_ALTIVEC /* undef to disable */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor1" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ + +/* Use first bank for JFFS2, second bank contains U-Boot. + * + * Note: fake mtd_id's used, no linux mtd map file. + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor1=db64460-1" +#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" +*/ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_CACHE \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_PCI \ + | CFG_CMD_NET ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_SPEED 40000 /* I2C speed default */ + +/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/*#define CFG_MEMTEST_START 0x00400000 memtest works on */ +/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ +/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ + +/* +#define CFG_DRAM_TEST + * DRAM tests + * CFG_DRAM_TEST - enables the following tests. + * + * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely + * addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. + */ +#define CFG_DRAM_TEST +#if defined(CFG_DRAM_TEST) +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_DRAM_TEST_DATA +#define CFG_DRAM_TEST_ADDRESS +#define CFG_DRAM_TEST_WALK +#endif /* CFG_DRAM_TEST */ + +#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ +#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ + +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ +#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ +#define CFG_BUS_CLK CFG_BUS_HZ + +#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ +#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ + +/*ronen - this is the Tclk (MV64460 core) */ +#define CFG_TCLK 133000000 + + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_750FX_HID0 0x8000c084 +#define CFG_750FX_HID1 0x54800000 +#define CFG_750FX_HID2 0x00000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized +*/ +#define CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#define RELOCATE_INTERNAL_RAM_ADDR +#ifdef RELOCATE_INTERNAL_RAM_ADDR + #define CFG_INTERNAL_RAM_ADDR 0xf8000000 +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +/* Dummies for BAT 4-7 */ +#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ +#define CFG_SDRAM2_BASE 0x20000000 +#define CFG_SDRAM3_BASE 0x30000000 +#define CFG_SDRAM4_BASE 0x40000000 +#define CFG_FLASH_BASE 0xfff00000 + +#define CFG_DFL_BOOTCS_BASE 0xff800000 +#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ + +#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ +#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ +#define PCI0_IO_BASE_BOOTM 0xfd000000 + +#define CFG_RESET_ADDRESS 0xfff00100 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +/* areas to map different things with the GT in physical space */ +#define CFG_DRAM_BANKS 4 + +/* What to put in the bats. */ +#define CFG_MISC_REGION_BASE 0xf0000000 + +/* Peripheral Device section */ + +/*******************************************************/ +/* We have on the db64460 Board : */ +/* GT-Chipset Register Area */ +/* GT-Chipset internal SRAM 256k */ +/* SRAM on external device module */ +/* Real time clock on external device module */ +/* dobble UART on external device module */ +/* Data flash on external device module */ +/* Boot flash on external device module */ +/*******************************************************/ +#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ +#define CFG_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */ + +/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ +#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */ + +#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */ +#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ +#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ +#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */ + +#define CFG_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */ +#define CFG_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */ +#define CFG_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */ +#define CFG_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */ +/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ + +/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ +#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ +#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ +#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ +#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ +#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ + + /* c 4 a 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ + /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ + /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ + + +/* ronen - update MPP Control MV64460*/ +#define CFG_MPP_CONTROL_0 0x02222222 +#define CFG_MPP_CONTROL_1 0x11333011 +#define CFG_MPP_CONTROL_2 0x40431111 +#define CFG_MPP_CONTROL_3 0x00000044 + +/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ + + +# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ + /* gpp[31] gpp[30] gpp[29] gpp[28] */ + /* gpp[27] gpp[24]*/ + /* gpp[19:14] */ + +/* setup new config_value for MV64460 DDR-RAM !! */ +# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ + +#define CFG_DUART_IO CFG_DEV2_SPACE +#define CFG_DUART_CHAN 1 /* channel to use for console */ +#define CFG_INIT_CHAN1 +#define CFG_INIT_CHAN2 + +#define SRAM_BASE CFG_DEV0_SPACE +#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ + +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ + +/* PCI MEMORY MAP section */ +#define CFG_PCI0_MEM_BASE 0x80000000 +#define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI1_MEM_BASE 0x88000000 +#define CFG_PCI1_MEM_SIZE _128M + +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) +#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) + +/* PCI I/O MAP section */ +#define CFG_PCI0_IO_BASE 0xfa000000 +#define CFG_PCI0_IO_SIZE _16M +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M + +#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) +#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ +#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) +#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ + +#if defined (CONFIG_750CX) +#define CFG_PCI_IDSEL 0x0 +#else +#define CFG_PCI_IDSEL 0x30 +#endif +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITE_THRU not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT0U CFG_IBAT0U + +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI0, PCI1 in one BAT */ +#define CFG_IBAT2L BATL_NO_ACCESS +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* GT regs, bootrom, all the devices, PCI I/O */ +#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x56 +#define DIMM1_I2C_ADDR 0x54 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ +#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ +#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ +#define CFG_FLASH_CFI 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ +/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/mpc74xx.h for the defines used here + */ + +#define CFG_L2 + + +#if defined (CONFIG_750CX) || defined (CONFIG_750FX) +#define L2_INIT 0 +#else + +#define L2_INIT 0 +/* +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +*/ +#endif + +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_BOARD_ASM_INIT 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h new file mode 100644 index 0000000..b58846d --- /dev/null +++ b/include/configs/DK1C20.h @@ -0,0 +1,556 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * Stephan Linz + * + * CompactFlash/IDE: + * (C) Copyright 2004, Shlomo Kut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*********************************************************************** + * Include the whole NIOS CPU configuration. + * + * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! + * + ***********************************************************************/ + +#if defined(CONFIG_NIOS_SAFE_32) +#include +#elif defined(CONFIG_NIOS_STANDARD_32) +#include +#else +#error *** CFG_ERROR: you have to setup right NIOS CPU configuration +#endif + +/*------------------------------------------------------------------------ + * BOARD/CPU -- TOP-LEVEL + *----------------------------------------------------------------------*/ +#define CONFIG_NIOS 1 /* NIOS-32 core */ +#define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/ +#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */ +#define CFG_HZ 1000 /* 1 msec time tick */ +#undef CFG_CLKS_IN_HZ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ + +/*------------------------------------------------------------------------ + * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_SDRAM_SIZE != 0) + +#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE +#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE + +#else +#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config +#endif + +#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE +#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE +#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION - For the most part, you can put things pretty + * much anywhere. This is pretty flexible for Nios. So here we make some + * arbitrary choices & assume that the monitor is placed at the end of + * a memory resource (so you must make sure TEXT_BASE is chosen + * appropriately). + * + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_FLASH_SIZE != 0) + +#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE +#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ + +#else +#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config +#endif + +/*------------------------------------------------------------------------ + * ENVIRONMENT + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_FLASH_SIZE != 0) + +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ +#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */ +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ + +#else +#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */ +#endif + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_UART_NUMS != 0) + +#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */ + +#if (CFG_NIOS_CPU_UART0_BR != 0) +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR +#else +#undef CFG_NIOS_FIXEDBAUD +#define CONFIG_BAUDRATE 115200 +#endif + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#else +#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config +#endif + +/*------------------------------------------------------------------------ + * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, + * so an avalon bus timer is required. + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_TIMER_NUMS != 0) + +#if (CFG_NIOS_CPU_TICK_TIMER == 0) + +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */ +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ + +#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ + +#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ) +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ) +#else +#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ +#endif + +#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ + +#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */ + +#if (CFG_HZ <= 1000) +#define CFG_NIOS_TMRMS (1000 / CFG_HZ) +#else +#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 +#endif + +#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) + +#else +#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct +#endif + +#elif (CFG_NIOS_CPU_TICK_TIMER == 1) + +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */ +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ + +#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ + +#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ) +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ) +#else +#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ +#endif + +#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ + +#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */ + +#if (CFG_HZ <= 1000) +#define CFG_NIOS_TMRMS (1000 / CFG_HZ) +#else +#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 +#endif + +#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) + +#else +#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct +#endif + +#endif /* CFG_NIOS_CPU_TICK_TIMER */ + +#else +#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config +#endif + +/*------------------------------------------------------------------------ + * Ethernet + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_LAN_NUMS == 1) + +#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ + +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) + +#if (CFG_NIOS_CPU_LAN0_BUSW == 32) +#define CONFIG_SMC_USE_32_BIT 1 +#else /* no */ +#undef CONFIG_SMC_USE_32_BIT +#endif + +#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ + + /********************************************/ + /* !!! CS8900 is __not__ tested on NIOS !!! */ + /********************************************/ +#define CONFIG_DRIVER_CS8900 /* Using CS8900 */ +#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) + +#if (CFG_NIOS_CPU_LAN0_BUSW == 32) +#undef CS8900_BUS16 +#define CS8900_BUS32 1 +#else /* no */ +#define CS8900_BUS16 1 +#undef CS8900_BUS32 +#endif + +#else +#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config +#endif + +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.2.21 +#define CONFIG_SERVERIP 192.168.2.16 + +#else +#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h +#endif + +/*------------------------------------------------------------------------ + * STATUS LEDs + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_PIO_NUMS != 0) + +#if (CFG_NIOS_CPU_LED_PIO == 0) + +#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 1) + +#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 2) + +#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2 +#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS +#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +#if (CFG_NIOS_CPU_PIO2_TYPE == 1) +#define STATUS_LED_WRONLY 1 +#else +#undef STATUS_LED_WRONLY +#endif + +#elif (CFG_NIOS_CPU_LED_PIO == 3) + +#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 4) + +#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 5) + +#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 6) + +#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 7) + +#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 8) + +#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 9) + +#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h + +#else +#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case +#endif + +#define CONFIG_STATUS_LED 1 /* enable status led driver */ + +#define STATUS_LED_BIT (1 << 0) /* LED[0] */ +#define STATUS_LED_STATE STATUS_LED_BLINKING +#define STATUS_LED_BOOT_STATE STATUS_LED_OFF +#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */ +#define STATUS_LED_BOOT 0 /* boot LED */ + +#if (STATUS_LED_BITS > 1) +#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */ +#define STATUS_LED_RED 1 /* fail LED */ +#endif + +#if (STATUS_LED_BITS > 2) +#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ +#define STATUS_LED_STATE2 STATUS_LED_OFF +#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */ +#define STATUS_LED_YELLOW 2 /* info LED */ +#endif + +#if (STATUS_LED_BITS > 3) +#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ +#define STATUS_LED_STATE3 STATUS_LED_OFF +#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */ +#define STATUS_LED_GREEN 3 /* info LED */ +#endif + +#define STATUS_LED_PAR 1 /* makes status_led.h happy */ + +#endif /* CFG_NIOS_CPU_PIO_NUMS */ + +/*------------------------------------------------------------------------ + * SEVEN SEGMENT LED DISPLAY + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_PIO_NUMS != 0) + +#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0) + +#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1) + +#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2) + +#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3) + +#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3 +#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS +#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ + +#if (CFG_NIOS_CPU_PIO3_TYPE == 1) +#define SEVENSEG_WRONLY 1 +#else +#undef SEVENSEG_WRONLY +#endif + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4) + +#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5) + +#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6) + +#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7) + +#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8) + +#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9) + +#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h + +#else +#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case +#endif + +#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ + +/* + * Dual 7-Segment Display pin assignment -- read more in your + * "Nios Development Board Reference Manual" + * + * + * (U8) HI:D[15..8] (U9) LO:D[7..0] + * ______ ______ + * | D14 | | D6 | + * | | | | + * D9| |D13 D1| |D5 + * |______| |______| ___ + * | D8 | | D0 | | A | + * | | | | F|___|B + * D10| |D12 D2| |D4 | G | + * |______| |______| E|___|C + * D11 * D3 * D * + * D15 D7 DP + * + */ +#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ +#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ +#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ +#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ +#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ +#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ +#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ +#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ +#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ + +#endif /* CFG_NIOS_CPU_PIO_NUMS */ + +/*------------------------------------------------------------------------ + * ASMI - Active Serial Memory Interface. + * + * ASMI is for Cyclone devices only and only works when the configuration + * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details. + *----------------------------------------------------------------------*/ +#define CONFIG_NIOS_ASMI /* Enable ASMI */ +#define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */ + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_MMC | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_VFD | \ + CFG_CMD_USB | \ + CFG_CMD_XIMG ) ) + + +#include + +/*------------------------------------------------------------------------ + * COMPACT FLASH + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CONFIG_IDE_PREINIT /* Implement id_preinit */ +#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x00920a00 /* IDE/ATA base addr */ +#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ +#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ +#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ +#define CFG_ATA_STRIDE 4 /* Width betwix addrs */ +#define CONFIG_DOS_PARTITION + +/* Board-specific cf regs */ +#define CFG_CF_PRESENT 0x009209b0 /* CF Present PIO base */ +#define CFG_CF_POWER 0x009209c0 /* CF Power FET PIO base*/ +#define CFG_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */ + +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ + +/*------------------------------------------------------------------------ + * KGDB + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 9600 +#endif + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "DK1C20 > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#if (CFG_SRAM_SIZE != 0) +#define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */ +#else +#undef CFG_LOAD_ADDR +#endif + +#if (CFG_SDRAM_SIZE != 0) +#define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */ +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */ +#else +#undef CFG_MEMTEST_START +#undef CFG_MEMTEST_END +#endif + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "" +#define MTDPARTS_DEFAULT "" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/DK1C20_safe_32.h b/include/configs/DK1C20_safe_32.h new file mode 100644 index 0000000..a483e87 --- /dev/null +++ b/include/configs/DK1C20_safe_32.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1C20_SAFE_32_H +#define __CONFIG_DK1C20_SAFE_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1C20.h) + * + * !!! TODO !!! TODO !!! + */ +#error *** CFG_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template) + +#endif /* __CONFIG_DK1C20_SAFE_32_H */ diff --git a/include/configs/DK1C20_standard_32.h b/include/configs/DK1C20_standard_32.h new file mode 100644 index 0000000..ed08121 --- /dev/null +++ b/include/configs/DK1C20_standard_32.h @@ -0,0 +1,279 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1C20_STANDARD_32_H +#define __CONFIG_DK1C20_STANDARD_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1C20.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* on-chip extensions */ +#define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */ +#define CFG_NIOS_CPU_RAM_SIZE 0 /* size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ +#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ +#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ +#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ +#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ +#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ +#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ +#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ +#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ +#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ +#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ +#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ +#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ + +/* active serial memory i/f */ +#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ +#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ +#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ + +/* memory accessibility */ +#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ +#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: alteramac(2) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ +#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ + +#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ +#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ +#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ +#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ +#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ +#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ +#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ +#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ + +#endif /* __CONFIG_DK1C20_STANDARD_32_H */ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h new file mode 100644 index 0000000..3e3803c --- /dev/null +++ b/include/configs/DK1S10.h @@ -0,0 +1,565 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*********************************************************************** + * Include the whole NIOS CPU configuration. + * + * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! + * + ***********************************************************************/ + +#if defined(CONFIG_NIOS_SAFE_32) +#include +#elif defined(CONFIG_NIOS_STANDARD_32) +#include +#elif defined(CONFIG_NIOS_MTX_LDK_20) +#include +#else +#error *** CFG_ERROR: you have to setup right NIOS CPU configuration +#endif + +/*------------------------------------------------------------------------ + * BOARD/CPU -- TOP-LEVEL + *----------------------------------------------------------------------*/ +#define CONFIG_NIOS 1 /* NIOS-32 core */ +#define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/ +#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */ +#define CFG_HZ 1000 /* 1 msec time tick */ +#undef CFG_CLKS_IN_HZ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ + +/*------------------------------------------------------------------------ + * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_SDRAM_SIZE != 0) + +#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE +#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE + +#else +#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config +#endif + +#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE) + +#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE +#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE + +#else + +#undef CFG_SRAM_BASE +#undef CFG_SRAM_SIZE + +#endif + +#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION - For the most part, you can put things pretty + * much anywhere. This is pretty flexible for Nios. So here we make some + * arbitrary choices & assume that the monitor is placed at the end of + * a memory resource (so you must make sure TEXT_BASE is chosen + * appropriately). + * + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_FLASH_SIZE != 0) + +#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE +#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ + +#else +#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config +#endif + +/*------------------------------------------------------------------------ + * ENVIRONMENT + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_FLASH_SIZE != 0) + +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ + +#if defined(CONFIG_NIOS_STANDARD_32) +#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */ +#elif defined(CONFIG_NIOS_MTX_LDK_20) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#else +#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR +#endif + +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ + +#else +#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */ +#endif + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_UART_NUMS != 0) + +#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ + +#if (CFG_NIOS_CPU_UART0_BR != 0) +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR +#else +#undef CFG_NIOS_FIXEDBAUD +#define CONFIG_BAUDRATE 115200 +#endif + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#else +#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config +#endif + +/*------------------------------------------------------------------------ + * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, + * so an avalon bus timer is required. + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER) + +#if (CFG_NIOS_CPU_TICK_TIMER == 0) + +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */ +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ + +#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ + +#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ) +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ) +#else +#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ +#endif + +#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ + +#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */ + +#if (CFG_HZ <= 1000) +#define CFG_NIOS_TMRMS (1000 / CFG_HZ) +#else +#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 +#endif + +#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) + +#else +#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct +#endif + +#elif (CFG_NIOS_CPU_TICK_TIMER == 1) + +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */ +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ + +#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ + +#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ) +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ) +#else +#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ +#endif + +#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ + +#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */ + +#if (CFG_HZ <= 1000) +#define CFG_NIOS_TMRMS (1000 / CFG_HZ) +#else +#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 +#endif + +#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) + +#else +#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct +#endif + +#endif /* CFG_NIOS_CPU_TICK_TIMER */ + +#else +#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config +#endif + +/*------------------------------------------------------------------------ + * Ethernet -- needs work! + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_LAN_NUMS == 1) + +#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ + +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) + +#if (CFG_NIOS_CPU_LAN0_BUSW == 32) +#define CONFIG_SMC_USE_32_BIT 1 +#else /* no */ +#undef CONFIG_SMC_USE_32_BIT +#endif + +#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ + + /********************************************/ + /* !!! CS8900 is __not__ tested on NIOS !!! */ + /********************************************/ +#define CONFIG_DRIVER_CS8900 /* Using CS8900 */ +#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) + +#if (CFG_NIOS_CPU_LAN0_BUSW == 32) +#undef CS8900_BUS16 +#define CS8900_BUS32 1 +#else /* no */ +#define CS8900_BUS16 1 +#undef CS8900_BUS32 +#endif + +#else +#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config +#endif + +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.2.21 +#define CONFIG_SERVERIP 192.168.2.16 + +#else +#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h +#endif + +/*------------------------------------------------------------------------ + * STATUS LEDs + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO) + +#if (CFG_NIOS_CPU_LED_PIO == 0) + +#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 1) + +#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 2) + +#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2 +#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS +#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +#if (CFG_NIOS_CPU_PIO2_TYPE == 1) +#define STATUS_LED_WRONLY 1 +#else +#undef STATUS_LED_WRONLY +#endif + +#elif (CFG_NIOS_CPU_LED_PIO == 3) + +#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 4) + +#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 5) + +#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 6) + +#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 7) + +#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 8) + +#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_LED_PIO == 9) + +#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h + +#else +#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case +#endif + +#define CONFIG_STATUS_LED 1 /* enable status led driver */ + +#define STATUS_LED_BIT (1 << 0) /* LED[0] */ +#define STATUS_LED_STATE STATUS_LED_BLINKING +#define STATUS_LED_BOOT_STATE STATUS_LED_OFF +#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */ +#define STATUS_LED_BOOT 0 /* boot LED */ + +#if (STATUS_LED_BITS > 1) +#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */ +#define STATUS_LED_RED 1 /* fail LED */ +#endif + +#if (STATUS_LED_BITS > 2) +#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ +#define STATUS_LED_STATE2 STATUS_LED_OFF +#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */ +#define STATUS_LED_YELLOW 2 /* info LED */ +#endif + +#if (STATUS_LED_BITS > 3) +#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ +#define STATUS_LED_STATE3 STATUS_LED_OFF +#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */ +#define STATUS_LED_GREEN 3 /* info LED */ +#endif + +#define STATUS_LED_PAR 1 /* makes status_led.h happy */ + +#endif /* CFG_NIOS_CPU_PIO_NUMS */ + +/*------------------------------------------------------------------------ + * SEVEN SEGMENT LED DISPLAY + *----------------------------------------------------------------------*/ +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO) + +#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0) + +#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1) + +#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2) + +#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3) + +#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3 +#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS +#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ + +#if (CFG_NIOS_CPU_PIO3_TYPE == 1) +#define SEVENSEG_WRONLY 1 +#else +#undef SEVENSEG_WRONLY +#endif + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4) + +#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5) + +#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6) + +#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7) + +#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8) + +#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h + +#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9) + +#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h + +#else +#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case +#endif + +#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ + +/* + * Dual 7-Segment Display pin assignment -- read more in your + * "Nios Development Board Reference Manual" + * + * + * (U8) HI:D[15..8] (U9) LO:D[7..0] + * ______ ______ + * | D14 | | D6 | + * | | | | + * D9| |D13 D1| |D5 + * |______| |______| ___ + * | D8 | | D0 | | A | + * | | | | F|___|B + * D10| |D12 D2| |D4 | G | + * |______| |______| E|___|C + * D11 * D3 * D * + * D15 D7 DP + * + */ +#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ +#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ +#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ +#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ +#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ +#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ +#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ +#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ +#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ + +#endif /* CFG_NIOS_CPU_PIO_NUMS */ + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_MMC | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_VFD | \ + CFG_CMD_USB | \ + CFG_CMD_XIMG ) ) + + +#include + +/*------------------------------------------------------------------------ + * KGDB + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 9600 +#endif + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "DK1S10 > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Default load address */ +#if (CFG_SRAM_SIZE != 0) + +/* default in SRAM */ +#define CFG_LOAD_ADDR CFG_SRAM_BASE + +#elif (CFG_SDRAM_SIZE != 0) + +/* default in SDRAM */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) +#else +#define CFG_LOAD_ADDR CFG_SDRAM_BASE +#endif + +#else +#undef CFG_LOAD_ADDR /* force error break */ +#endif + + +/* MEM test area */ +#if (CFG_SDRAM_SIZE != 0) + +/* SDRAM begin to stack area (1MB stack) */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) +#else +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) +#endif + +#else +#undef CFG_MEMTEST_START /* force error break */ +#undef CFG_MEMTEST_END +#endif + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "" +#define MTDPARTS_DEFAULT "" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h new file mode 100644 index 0000000..4eb9629 --- /dev/null +++ b/include/configs/DK1S10_mtx_ldk_20.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_MTX_LDK_20_H +#define __CONFIG_DK1S10_MTX_LDK_20_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 75000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (0) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x02000000 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x01000000 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* The offset address in flash to check for the Nios signature "Ni". + * (see GM_FlashExec in germs_monitor.s) */ +#define CFG_NIOS_CPU_EXES_OFFS 0x0C + +/* on-chip extensions */ +#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */ +#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */ +#undef CFG_NIOS_CPU_OCI_SIZE /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 2 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_UART1 0x000008a0 /* UART1 addr */ +#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */ +#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 2 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ +#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ +#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ + +/* memory accessibility */ +#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ +#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00800000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: openmac(2) */ + /* ex: alteramac(3) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ +#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ + +#define CFG_NIOS_CPU_CFPOWER_PIO 0 /* PIO0: CF power/sw. */ +#define CFG_NIOS_CPU_BUTTON_PIO 1 /* PIO1: buttons */ +#undef CFG_NIOS_CPU_LCD_PIO /* PIOx: ASCII LCD */ +#undef CFG_NIOS_CPU_LED_PIO /* PIOx: LED bar */ +#undef CFG_NIOS_CPU_SEVENSEG_PIO /* PIOx: 7-seg. display */ +#undef CFG_NIOS_CPU_RECONF_PIO /* PIOx: reconf pin */ +#undef CFG_NIOS_CPU_CFPRESENT_PIO /* PIOx: CF present IRQ */ +#undef CFG_NIOS_CPU_CFATASEL_PIO /* PIOx: CF ATA select */ + +#endif /* __CONFIG_DK1S10_MTX_LDK_20_H */ diff --git a/include/configs/DK1S10_safe_32.h b/include/configs/DK1S10_safe_32.h new file mode 100644 index 0000000..8541a11 --- /dev/null +++ b/include/configs/DK1S10_safe_32.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_SAFE_32_H +#define __CONFIG_DK1S10_SAFE_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * !!! TODO !!! TODO !!! + */ +#error *** CFG_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template) + +#endif /* __CONFIG_DK1S10_SAFE_32_H */ diff --git a/include/configs/DK1S10_standard_32.h b/include/configs/DK1S10_standard_32.h new file mode 100644 index 0000000..b83c315 --- /dev/null +++ b/include/configs/DK1S10_standard_32.h @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2003, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_STANDARD_32_H +#define __CONFIG_DK1S10_STANDARD_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* on-chip extensions */ +#define CFG_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */ +#define CFG_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ +#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ +#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ +#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ +#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ +#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ +#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ +#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ +#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ +#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ +#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ +#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ +#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ + +/* memory accessibility */ +#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ +#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: alteramac(2) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ +#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ + +#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ +#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ +#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ +#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ +#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ +#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ +#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ +#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ + +#endif /* __CONFIG_DK1S10_STANDARD_32_H */ diff --git a/include/configs/DP405.h b/include/configs/DP405.h new file mode 100644 index 0000000..2ae794d --- /dev/null +++ b/include/configs/DP405.h @@ -0,0 +1,341 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_DP405 1 /* ...on a DP405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +#define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) +# define CFG_RAMBOOT 1 +#else +# undef CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +#if 0 /* test-only */ +/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ +#endif + +/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ +/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ +/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ +/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ +#define CFG_GPIO0_OSRH 0x40000540 /* 0 ... 15 */ +#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ +#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ +#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ +#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ +#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 1 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/DU405.h b/include/configs/DU405.h new file mode 100644 index 0000000..5489a53 --- /dev/null +++ b/include/configs/DU405.h @@ -0,0 +1,315 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IDENT_STRING " $Name: $" + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_DU405 1 /* ...on a DU405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND "bootm fff00000" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffe00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC08) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ + /* total size of a CAT24WC08 is 1024 bytes */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */ +#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */ +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define DUART_BA 0xF0300000 /* DUART Base Address */ +#define CF_BA 0xF0100000 /* CompactFlash Base Address */ +#define SRAM_BA 0xF0200000 /* SRAM Base Address */ +#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */ +#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */ + +#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (CAN0) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (DUART) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 4 (CompactFlash IDE) initialization */ +#define CFG_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/* Memory Bank 5 (SRAM) initialization */ +#define CFG_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ + +/* Memory Bank 6 (DURAG Bus IO Space) initialization */ +#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/ + +/* Memory Bank 7 (DURAG Bus Mem Space) initialization */ +#define CFG_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */ + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h new file mode 100644 index 0000000..2c99b4b --- /dev/null +++ b/include/configs/ELPPC.h @@ -0,0 +1,352 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG +#define GTREGREAD(x) 0xffffffff /* needed for debug */ + +/* + * High Level Configuration Options + * (easy to change) + */ + +/* these hardware addresses are pretty bogus, please change them to + suit your needs */ + +/* first ethernet */ +#define CONFIG_ETHADDR 00:00:5b:ee:de:ad + +#define CONFIG_IPADDR 192.168.0.105 +#define CONFIG_SERVERIP 192.168.0.100 + +#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */ + +#define CONFIG_BAUDRATE 9600 /* console baudrate */ + +#undef CONFIG_WATCHDOG + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp 1000000; " \ + "setenv bootargs root=ramfs console=ttyS00,9600 " \ + "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ + "${netmask}:${hostname}:eth0:none; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +/* + * choose between COM1 and COM2 as serial console + */ +#define CONFIG_CONS_INDEX 1 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ + +#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +#define CFG_BOARD_ASM_INIT +#define CONFIG_MISC_INIT_R + +/* + * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP) + */ +#undef CFG_ADDRESS_MAP_A + +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x40000000 + +#define CFG_PCI_MEM_BUS 0x80000000 +#define CFG_PCI_MEM_PHYS 0x80000000 +#define CFG_PCI_MEM_SIZE 0x7d000000 + +#define CFG_ISA_MEM_BUS 0x00000000 +#define CFG_ISA_MEM_PHYS 0xfd000000 +#define CFG_ISA_MEM_SIZE 0x01000000 + +#define CFG_PCI_IO_BUS 0x00800000 +#define CFG_PCI_IO_PHYS 0xfe800000 +#define CFG_PCI_IO_SIZE 0x00400000 + +#define CFG_ISA_IO_BUS 0x00000000 +#define CFG_ISA_IO_PHYS 0xfe000000 +#define CFG_ISA_IO_SIZE 0x00800000 + +/* driver defines FDC,IDE,... */ +#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS +#define CFG_ISA_IO CFG_ISA_IO_PHYS +#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_USR_LED_BASE 0x78000000 +#define CFG_NVRAM_BASE 0xff000000 +#define CFG_UART_BASE 0xff400000 +#define CFG_FLASH_BASE 0xfff00000 + +#define MPC107_EUMB_ADDR 0xfce00000 +#define MPC107_EUMB_PI 0xfce41090 +#define MPC107_EUMB_GCR 0xfce41020 +#define MPC107_EUMB_IACKR 0xfce600a0 +#define MPC107_I2C_ADDR 0xfce03000 + +/* + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ +#define CFG_INIT_RAM_END 0x4000 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Flash mapping/organization on the MPC10x. + */ +#define FLASH_BASE0_PRELIM 0xff800000 +#define FLASH_BASE1_PRELIM 0xffc00000 + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1" +#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)" +*/ + +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ +#undef CFG_MEMTEST + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */ +#define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ +#define CFG_ENV_ADDR 0x0 +#define CFG_ENV_MAP_ADRS 0xff000000 +#define CFG_NV_SROM_COPY_ADDR (CFG_ENV_ADDR + CFG_ENV_SIZE) +#define CFG_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */ +#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ + +/* + * Serial devices + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 24000000 +#define CFG_NS16550_COM1 (CFG_UART_BASE + 0) +#define CFG_NS16550_COM2 (CFG_UART_BASE + 8) + +/* + * PCI stuff + */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO +#undef CONFIG_PCI_SCAN_SHOW + +/* + * Optional Video console (graphic: SMI LynxEM) + */ +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10)) +#define VIDEO_TSTC_FCT serial_tstc +#define VIDEO_GETC_FCT serial_getc + +#define CONFIG_VIDEO_SMI_LYNXEM +#define CONFIG_VIDEO_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO + +/* + * Initial BATs + */ +#if 1 + +#define CFG_IBAT0L 0 +#define CFG_IBAT0U 0 +#define CFG_DBAT0L CFG_IBAT1L +#define CFG_DBAT0U CFG_IBAT1U + +#define CFG_IBAT1L 0 +#define CFG_IBAT1U 0 +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +#define CFG_IBAT2L 0 +#define CFG_IBAT2U 0 +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +#define CFG_IBAT3L 0 +#define CFG_IBAT3U 0 +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +#else + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT1L +#define CFG_DBAT0U CFG_IBAT1U + +/* address range for flashes */ +#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* ISA IO space */ +#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* ISA memory space */ +#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +#endif + +/* + * Speed settings are board specific + */ +#define CFG_BUS_HZ 100000000 +#define CFG_CPU_CLK 400000000 +#define CFG_BUS_CLK CFG_BUS_HZ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * L2CR setup -- make sure this is right for your board! + * look in include/74xx_7xx.h for the defines used here + */ + +#define CFG_L2 + +#if 1 +#define L2_INIT 0 /* cpu 750 CXe*/ +#else +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#endif +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_EEPRO100_SROM_WRITE + +#endif /* __CONFIG_H */ diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h new file mode 100644 index 0000000..e73bcec --- /dev/null +++ b/include/configs/ELPT860.h @@ -0,0 +1,390 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team , http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */ +#define CONFIG_MPC860T 1 +#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */ +#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* BOOT arguments */ +#define CONFIG_PREBOOT \ + "echo;" \ + "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "rootargs=setenv rootpath /tftp/${ipaddr}\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:eth0:off panic=1\0" \ + "ramboot=tftp 400000 /home/paugaml/pMulti;" \ + "run ramargs;bootm\0" \ + "nfsboot=tftp 400000 /home/paugaml/uImage;" \ + "run rootargs;run nfsargs;run addip;bootm\0" \ + "" +#define CONFIG_BOOTCOMMAND "run ramboot" + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ +#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */ +#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Environment Variables and Storages + */ +#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */ + +#undef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */ +#undef CFG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */ + +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_ETHADDR 00:01:77:00:60:40 +#define CONFIG_IPADDR 192.168.0.30 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_GATEWAYIP 192.168.0.1 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x02000000 +#define CFG_NVRAM_BASE 0x03000000 + +#if defined(CFG_ENV_IS_IN_FLASH) +# if defined(DEBUG) +# define CFG_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */ +# else +# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +# endif +#else +# if defined(DEBUG) +# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +# else +# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +# endif +#endif + +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ +# define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ +#define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */ + /* 8 top NVRAM locations */ + +#if defined(CFG_ENV_IS_IN_NVRAM) +# define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ +# define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) +#else +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC11) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC + * enabled + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler + *----------------------------------------------------------------------- + * + */ +#ifdef DEBUG +# define CFG_DER 0xFFE7400F /* Debug Enable Register */ +#else +# define CFG_DER 0 +#endif + +/* + * Init Memory Controller: + * ~~~~~~~~~~~~~~~~~~~~~~ + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR1 and OR1 (SDRAM) + * + */ +#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */ + +/* SDRAM timing: */ +#define CFG_OR_TIMING_SDRAM 0x00000000 + +#define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM ) +#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * BR2 and OR2 (NVRAM) + * + */ +#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */ +#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */ + +#define CFG_OR2_PRELIM 0xFFF80160 +#define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/*----------------------------------------------------------------------- + * Internal Definitions + *----------------------------------------------------------------------- + * + */ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h new file mode 100644 index 0000000..c203aea --- /dev/null +++ b/include/configs/ERIC.h @@ -0,0 +1,372 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_ERIC 1 /* ...on a ERIC board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* run board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#endif +#if 0 +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#endif +#if 0 +#define CFG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */ +#endif /* total size of a X1240 is 2048 bytes */ + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */ +#define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */ +#define CFG_I2C_RTC_ADDR 0x6F /* and one for RTC */ + +#ifdef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_EEPROM +#else +#ifdef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_EEPROM +#else +#ifdef CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#endif +#endif +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#if 1 +#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ +#else +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ +#endif + +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \ + "nfsroot=192.168.1.2:/eric_root_devel " \ + "ip=192.168.1.22:192.168.1.2" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH) + +/* + * #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \ + * CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \ + * CFG_CMD_ENV | CFG_CMD_FLASH) + */ + +/* CFG_CMD_ENV est definie */ +/* ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV)) + */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_EXT_SERIAL_CLOCK 14318180 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#undef CONFIG_PCI_PNP /* no pci plug-and-play */ + /* resource configuration */ + +#define CFG_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */ +#define CFG_PCI_PTM1LA 0xFFFC0000 /* point to flash */ +#define CFG_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * External peripheral base address + *----------------------------------------------------------------------- + */ +/* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */ +/* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */ +/* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */ +/* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */ +/* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */ +/* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */ +/* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */ +/* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */ + +/* ----------------------------------------------------------------------- */ +/* Memory Bank 0 (Flash) initialization */ +/* ----------------------------------------------------------------------- */ +#define CS0_AP 0x9B015480 +#define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */ +/* ----------------------------------------------------------------------- */ +/* Memory Bank 1 (NVRAM/RTC) initialization */ +/* ----------------------------------------------------------------------- */ +#define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ +#define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ + /* ----------------------------------------------------------------------- */ + /* Memory Bank 2 (A/D converter) initialization */ + /* ----------------------------------------------------------------------- */ +#define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ +#define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ +/* ----------------------------------------------------------------------- */ +/* Memory Bank 3 (Ethernet PHY Reset) initialization */ +/* ----------------------------------------------------------------------- */ +#define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ +#define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ +/* ----------------------------------------------------------------------- */ +/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */ +/* ----------------------------------------------------------------------- */ +#define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ +#define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ +/* ----------------------------------------------------------------------- */ +/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */ +/* ----------------------------------------------------------------------- */ +#define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ +#define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ +/* ----------------------------------------------------------------------- */ +/* Memory Bank 6 (CPU LED0) initialization */ +/* ----------------------------------------------------------------------- */ +#define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ +#define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ +/* ----------------------------------------------------------------------- */ +/* Memory Bank 7 (CPU LED1) initialization */ +/* ----------------------------------------------------------------------- */ +#define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ +#define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ + +#define CFG_NVRAM_REG_BASE_ADDR 0xF0000000 +#define CFG_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8) +#define CFG_ADC_REG_BASE_ADDR 0xF0100000 +#define CFG_PHYRES_REG_BASE_ADDR 0xF0200000 +#define CFG_PRSNT1_REG_BASE_ADDR 0xF0300000 +#define CFG_PRSNT2_REG_BASE_ADDR 0xF0400000 +#define CFG_LED0_REG_BASE_ADDR 0xF0500000 +#define CFG_LED1_REG_BASE_ADDR 0xF0600000 + + +/* SDRAM CONFIG */ +#define CFG_SDRAM_MANUALLY 1 +#define CFG_SDRAM_SINGLE_BANK 1 + +#ifdef CFG_SDRAM_MANUALLY +/*----------------------------------------------------------------------- + * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) + *----------------------------------------------------------------------*/ +#define MB0CF 0x00062001 /* 32MB @ 0 */ +/*----------------------------------------------------------------------- + * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) + *----------------------------------------------------------------------*/ +#ifdef CFG_SDRAM_SINGLE_BANK +#define MB1CF 0x0 /* 0MB @ 32MB */ +#else +#define MB1CF 0x02062001 /* 32MB @ 32MB */ +#endif +/*----------------------------------------------------------------------- + * Set MB2CF for bank 2. off + *----------------------------------------------------------------------*/ +#define MB2CF 0x0 /* 0MB */ +/*----------------------------------------------------------------------- + * Set MB3CF for bank 3. off + *----------------------------------------------------------------------*/ +#define MB3CF 0x0 /* 0MB */ + +#define SDTR_100 0x0086400D +#define RTR_100 0x05F0 +#define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */ +#define RTR_66 0x03f8 + +#endif /* CFG_SDRAM_MANUALLY */ + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 32 +#define CFG_FLASH_BASE 0xFF800000 /* 8 MByte Flash */ +#define CFG_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */ +/*#define CFG_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */ +#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ +#define CFG_FLASH_16BIT 1 /* Rom 16 bit data bus */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* BEG ENVIRONNEMENT FLASH */ +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE (128*1024) + +#if 0 /* force ENV to be NOT embedded */ +#define CFG_ENV_ADDR 0xfffa0000 +#else /* force ENV to be embedded */ +#define CFG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN - CFG_ENV_SIZE - 0x10) /* let space for reset vector */ +/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE)*/ +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#endif + +#endif +/* END ENVIRONNEMENT FLASH */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_REG_BASE_ADDR /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x7F8 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + +/* Configuration Port location */ +/* #define CONFIG_PORT_ADDR 0xF0000500 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h new file mode 100644 index 0000000..b176c6f --- /dev/null +++ b/include/configs/ESTEEM192E.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */ + +#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define MPC8XX_FACT 10 /* Multiply by 10 */ +#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */ +#define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20) +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */ + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_BAUDRATE 9600 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */ + +#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \ + "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 " +/* + * Miscellaneous configurable options + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "BOOT: " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 8 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + + /*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) + +/*----------------------------------------------------------------------- + * SUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) + +/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */ + + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (CFG_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 +/*#define CFG_DER 0x02002000 */ + + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH 0x00000160 + /*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ + OR_SCY_5_CLK | OR_EHTR) */ + +#define CFG_OR0_REMAP 0x80000160 /*(CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)*/ +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM 0xFC000E00 +#define CFG_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081) + +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081) + + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL 0x18803112 +#define CFG_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/ + + +/* + * Internal Definitions + * + * Boot Flags + */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h new file mode 100644 index 0000000..d55eb7d --- /dev/null +++ b/include/configs/ETX094.h @@ -0,0 +1,355 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_ETX094 1 /* ...on a ETX_094 board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 57600 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ +#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ +#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ + +#define CONFIG_ETHADDR 08:00:06:00:00:00 + +#ifdef CONFIG_ETHADDR +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */ +#endif + +#undef CONFIG_BOOTARGS +#define CONFIG_RAMBOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \ + "U-Boot_version=U-Boot-1.0.x-Date " \ + "panic=1 " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" +#define CONFIG_NFSBOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_WATCHDOG 1 /* watchdog enabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#ifdef CONFIG_FLASH_16BIT +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ +#else +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \ + OR_SCY_2_CLK | OR_TRLX ) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) + +#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) +#else /* 32 bit data port */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) +#endif /* CONFIG_FLASH_16BIT */ + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 23 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h new file mode 100644 index 0000000..78e5716 --- /dev/null +++ b/include/configs/EVB64260.h @@ -0,0 +1,425 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#include "../board/evb64260/local.h" + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ +#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ + +#undef CONFIG_ECC /* enable ECC support */ +/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#ifndef CONFIG_EVB64260_750CX +#define CFG_BOARD_NAME "EVB64260" +#else +#define CFG_BOARD_NAME "EVB64260-750CX" +#endif + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial + * cable onto the second DUART channel, change the CFG_DUART port from 1 + * to 0 below. + * + * to use the MPSC, #define CONFIG_MPSC. If you have wired up another + * mpsc channel, change CONFIG_MPSC_PORT to the desired value. + */ +#define CONFIG_MPSC +#define CONFIG_MPSC_PORT 0 + +#define CONFIG_NET_MULTI /* attempt all available adapters */ + +/* define this if you want to enable GT MAC filtering */ +#define CONFIG_GT_USE_MAC_HASH_TABLE + +#undef CONFIG_ETHER_PORT_MII /* use RMII */ + +#if 1 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp && " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:" \ + "$netmask:$hostname:eth0:none; && " \ + "bootm" + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_ALTIVEC /* undef to disable */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00300000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CFG_BUS_HZ 100000000 /* 100 MHz */ +#define CFG_BUS_CLK CFG_BUS_HZ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#ifdef CONFIG_EVB64260_750CX +#define CONFIG_750CX +#define CFG_BROKEN_CL2 +#endif + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_LOCK + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xfff00000 +#define CFG_RESET_ADDRESS 0xfff00100 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +/* areas to map different things with the GT in physical space */ +#define CFG_DRAM_BANKS 4 +#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ + +/* What to put in the bats. */ +#define CFG_MISC_REGION_BASE 0xf0000000 + +/* Peripheral Device section */ +#define CFG_GT_REGS 0xf8000000 +#define CFG_DEV_BASE 0xfc000000 + +#define CFG_DEV0_SPACE CFG_DEV_BASE +#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) +#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) +#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) + +#define CFG_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */ +#define CFG_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */ +#define CFG_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */ +#define CFG_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */ + +#define CFG_DEV0_PAR 0x20205093 +#define CFG_DEV1_PAR 0xcfcfffff +#define CFG_DEV2_PAR 0xc0059bd4 +#define CFG_8BIT_BOOT_PAR 0xc00b5e7c +#define CFG_32BIT_BOOT_PAR 0xc4a8241c + /* c 4 a 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ + /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ + /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ + +#if 0 /* Wrong?? NTL */ +#define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ + /* DMAAck[1:0] GNT0[1:0] */ +#else +#define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ + /* REQ0[1:0] GNT0[1:0] */ +#endif +#define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ + /* DMAReq[4] DMAAck[4] WDNMI WDE */ +#if 0 /* Wrong?? NTL */ +#define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ + /* DMAAck[1:0] GNT1[1:0] */ +#else +#define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ + /* GPP[22] (RS232IntB or PCI1Int) */ + /* GPP[21] (RS323IntA) */ + /* BClkIn */ + /* REQ1[1:0] GNT1[1:0] */ +#endif + +#if 0 /* Wrong?? NTL */ +# define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ + /* GPP[27:26] Int[1:0] */ +#else +# define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ + /* GPP[29] (PCI1Int) */ + /* BClkOut0 */ + /* GPP[27] (PCI0Int) */ + /* GPP[26] (RtcInt or PCI1Int) */ + /* CPUInt[25:24] */ +#endif + +# define CFG_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ + +#if 0 /* Wrong?? - NTL */ +# define CFG_GPP_LEVEL_CONTROL 0x000002c6 +#else +# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ + /* gpp[29] */ + /* gpp[27:26] */ + /* gpp[22:21] */ + +# define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ + /* idmas use buffer 1,1 + comm use buffer 0 + pci use buffer 1,1 + cpu use buffer 0 + normal load (see also ifdef HVL) + standard SDRAM (see also ifdef REG) + non staggered refresh */ + /* 31:26 25 23 20 19 18 16 */ + /* 110110 00 111 0 0 00 1 */ + /* refresh_count=0x200 + phisical interleaving disable + virtual interleaving enable */ + /* 15 14 13:0 */ + /* 1 0 0x200 */ +#endif + +#define CFG_DUART_IO CFG_DEV2_SPACE +#define CFG_DUART_CHAN 1 /* channel to use for console */ +#define CFG_INIT_CHAN1 +#define CFG_INIT_CHAN2 + +#define SRAM_BASE CFG_DEV0_SPACE +#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ + +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* PCI MEMORY MAP section */ +#define CFG_PCI0_MEM_BASE 0x80000000 +#define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI1_MEM_BASE 0x88000000 +#define CFG_PCI1_MEM_SIZE _128M + +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) +#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) + + +/* PCI I/O MAP section */ +#define CFG_PCI0_IO_BASE 0xfa000000 +#define CFG_PCI0_IO_SIZE _16M +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M + +#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) +#define CFG_PCI0_IO_SPACE_PCI 0x00000000 +#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) +#define CFG_PCI1_IO_SPACE_PCI 0x00000000 + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 + +#define CFG_NS16550_REG_SIZE -4 + +#define CFG_NS16550_CLK 3686400 + +#define CFG_NS16550_COM1 (CFG_DUART_IO + 0) +#define CFG_NS16550_COM2 (CFG_DUART_IO + 0x20) + +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITE_THRU not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT0U CFG_IBAT0U + +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI0, PCI1 in one BAT */ +#define CFG_IBAT2L BATL_NO_ACCESS +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* GT regs, bootrom, all the devices, PCI I/O */ +#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* I2C speed and slave address (for compatability) defaults */ +#define CFG_I2C_SPEED 400000 +#define CFG_I2C_SLAVE 0x7F + +/* I2C addresses for the two DIMM SPD chips */ +#ifndef CONFIG_EVB64260_750CX +#define DIMM0_I2C_ADDR 0x56 +#define DIMM1_I2C_ADDR 0x54 +#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ +#define DIMM0_I2C_ADDR 0x54 +#define DIMM1_I2C_ADDR 0x54 +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ +#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_CFI 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/74xx_7xx.h for the defines used here + */ + +#define CFG_L2 + +#ifdef CONFIG_750CX +#define L2_INIT 0 +#else +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#endif + +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_BOARD_ASM_INIT 1 + + +#endif /* __CONFIG_H */ diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h new file mode 100644 index 0000000..d85be42 --- /dev/null +++ b/include/configs/EXBITGEN.h @@ -0,0 +1,213 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ + +/* I2C configuration */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 40000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ + +/* environment is in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_I2C_EEPROM_ADDR 0x56 /* 1010110 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */ +#define CFG_ENV_OFFSET 4 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 350 /* that is 350 bytes only! */ +#endif + +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ +/* Explanation: + autbooting is altogether disabled and cannot be + enabled if CONFIG_BOOTDELAY is negative. + If you want shorter bootdelay, then + - "setenv bootdelay " to the proper value +*/ + +#define CONFIG_BOOTCOMMAND "bootm 20400000 20800000" + +#define CONFIG_BOOTARGS "root=/dev/ram " \ + "ramdisk_size=32768 " \ + "console=ttyS0,115200 " \ + "ram=128M debug" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* UART configuration */ +#define CFG_BASE_BAUD 691200 + +/* Default baud rate */ +#define CONFIG_BAUDRATE 115200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_PCI /* no pci support */ + +/*----------------------------------------------------------------------- + * External peripheral base address + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_KEY_REG_BASE_ADDR 0xF0100000 +#define CFG_IR_REG_BASE_ADDR 0xF0200000 +#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH0_BASE 0xFFF80000 +#define CFG_FLASH0_SIZE 0x00080000 +#define CFG_FLASH1_BASE 0x20000000 +#define CFG_FLASH1_SIZE 0x02000000 +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +#if CFG_MONITOR_BASE < CFG_FLASH0_BASE +#define CFG_RAMSTART +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 5 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */ +#endif + +/* On Chip Memory location/size */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +/* Global info and initial stack */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* Cache configuration */ +#define CFG_DCACHE_SIZE 8192 +#define CFG_CACHELINE_SIZE 32 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h new file mode 100644 index 0000000..1b562d6 --- /dev/null +++ b/include/configs/FADS823.h @@ -0,0 +1,464 @@ + /* + * A collection of structures, addresses, and values associated with + * the Motorola 860T FADS board. Copied from the MBX stuff. + * Magnus Damm added defines for 8xxrom and extended bd_info. + * Helmut Buchsbaum added bitvalues for BCSRx + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + */ + +/* + * 1999-nov-26: The FADS is using the following physical memorymap: + * + * ff020000 -> ff02ffff : pcmcia io remapping + * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot + * ff000000 -> ff00ffff : IMAP internal in the cpu + * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia + * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot + * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot +*/ + +#define CFG_PCMCIA_IO_ADDR 0xff020000 +#define CFG_PCMCIA_IO_SIZE 0x10000 +#define CFG_PCMCIA_MEM_ADDR 0xe0000000 +#define CFG_PCMCIA_MEM_SIZE 0x10000 +#define CFG_IMMR 0xFF000000 +#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x02800000 +#define BCSR_ADDR ((uint) 0xff010000) +#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ +#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ + +#define CONFIG_VIDEO 1 /* To enable video controller support */ +#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/*Now included by CFG_CMD_PCMCIA */ +/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */ + +/* Video related */ + +#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ +#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */ +#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */ +#define CONFIG_VIDEO_SIZE (2*1024*1024) +/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */ + +/* Wireless 56Khz 4PPM keyboard on SMCx */ + +/*#define CONFIG_KEYBOARD 1 */ +#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC823 1 +#define CONFIG_MPC823FADS 1 +#define CONFIG_FADS 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 + +/* Set the CPU speed to 50Mhz on the FADS */ + +#if 0 +#define MPC8XX_FACT 10 /* Multiply by 10 */ +#define MPC8XX_XIN 5000000 /* 5 MHz in */ +#else +#define MPC8XX_FACT 10 /* Multiply by 10 */ +#define MPC8XX_XIN 5000000 /* 5 MHz in */ +#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */ +#endif +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#if 1 +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ +#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ +#define CONFIG_BOOTARGS "" +#define CONFIG_BOOTCOMMAND \ +"bootp ;" \ +"setenv bootargs console=tty0 console=ttyS0 " \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ +"bootm" +#else +#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT ":>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR_SIZE ((uint)(64 * 1024)) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Also NOTE that it doesn't mean SDRAM - it means MEMORY. + */ +#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ +#if 0 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer * + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + + /*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the +* entire address space, we have to set the memory controller +* differently. Normally, you write the option register +* first, and then enable the chip select by writing the +* base register. For CS0, you must write the base register +* first, followed by the option register. +*/ + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ +/* the other CS:s are determined by looking at parameters in BCSRx */ + +#define BCSR_SIZE ((uint)(64 * 1024)) + +#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ + +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +/* BCSRx - Board Control and Status Registers */ +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ +#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) + + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +#define CFG_MAMR 0x13a01114 +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* values according to the manual */ + +#define BCSR0 ((uint) (BCSR_ADDR + 00)) +#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) +#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) +#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) +#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) + +/* FADS bitvalues by Helmut Buchsbaum + * see MPC8xxADS User's Manual for a proper description + * of the following structures + */ + +#define BCSR0_ERB ((uint)0x80000000) +#define BCSR0_IP ((uint)0x40000000) +#define BCSR0_BDIS ((uint)0x10000000) +#define BCSR0_BPS_MASK ((uint)0x0C000000) +#define BCSR0_ISB_MASK ((uint)0x01800000) +#define BCSR0_DBGC_MASK ((uint)0x00600000) +#define BCSR0_DBPC_MASK ((uint)0x00180000) +#define BCSR0_EBDF_MASK ((uint)0x00060000) + +#define BCSR1_FLASH_EN ((uint)0x80000000) +#define BCSR1_DRAM_EN ((uint)0x40000000) +#define BCSR1_ETHEN ((uint)0x20000000) +#define BCSR1_IRDEN ((uint)0x10000000) +#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) +#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) +#define BCSR1_BCSR_EN ((uint)0x02000000) +#define BCSR1_RS232EN_1 ((uint)0x01000000) +#define BCSR1_PCCEN ((uint)0x00800000) +#define BCSR1_PCCVCC0 ((uint)0x00400000) +#define BCSR1_PCCVPP_MASK ((uint)0x00300000) +#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) +#define BCSR1_RS232EN_2 ((uint)0x00040000) +#define BCSR1_SDRAM_EN ((uint)0x00020000) +#define BCSR1_PCCVCC1 ((uint)0x00010000) + +#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) +#define BCSR2_FLASH_PD_SHIFT 28 +#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) +#define BCSR2_DRAM_PD_SHIFT 23 +#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) +#define BCSR2_DBREVNR_MASK ((uint)0x00030000) + +#define BCSR3_DBID_MASK ((ushort)0x3800) +#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) +#define BCSR3_BREVNR0 ((ushort)0x0080) +#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) +#define BCSR3_BREVN1 ((ushort)0x0008) +#define BCSR3_BREVN2_MASK ((ushort)0x0003) + +#define BCSR4_ETHLOOP ((uint)0x80000000) +#define BCSR4_TFPLDL ((uint)0x40000000) +#define BCSR4_TPSQEL ((uint)0x20000000) +#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) +#ifdef CONFIG_MPC823 +#define BCSR4_USB_EN ((uint)0x08000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860SAR +#define BCSR4_UTOPIA_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860SAR */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETH_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_USB_SPEED ((uint)0x04000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHCFG0 ((uint)0x04000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VCCO ((uint)0x02000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHFDE ((uint)0x02000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VIDEO_ON ((uint)0x00800000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC823 +#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHCFG1 ((uint)0x00400000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VIDEO_RST ((uint)0x00200000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHRST ((uint)0x00200000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_MODEM_EN ((uint)0x00100000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC823 +#define BCSR4_DATA_VOICE ((uint)0x00080000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC850 +#define BCSR4_DATA_VOICE ((uint)0x00080000) +#endif /* CONFIG_MPC850 */ + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + +/* + * MPC8xx CPM Options + */ +#define CONFIG_SCC_ENET 1 +#define CONFIG_SCC2_ENET 1 +#undef CONFIG_FEC_ENET +#undef CONFIG_CPM_IIC +#undef CONFIG_UCODE_PATCH + +#define CONFIG_DISK_SPINUP_TIME 1000000 + +/* PCMCIA configuration */ + +#define PCMCIA_MAX_SLOTS 1 + +#ifdef CONFIG_MPC860 +#define PCMCIA_SLOT_A 1 +#endif + +#define CFG_DAUGHTERBOARD + +#endif /* __CONFIG_H */ diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h new file mode 100644 index 0000000..2a986f0 --- /dev/null +++ b/include/configs/FADS850SAR.h @@ -0,0 +1,416 @@ + /* + * A collection of structures, addresses, and values associated with + * the Motorola 860T FADS board. Copied from the MBX stuff. + * Magnus Damm added defines for 8xxrom and extended bd_info. + * Helmut Buchsbaum added bitvalues for BCSRx + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + */ + +/* + * 1999-nov-26: The FADS is using the following physical memorymap: + * + * ff020000 -> ff02ffff : pcmcia + * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom + * ff000000 -> ff00ffff : IMAP internal in the cpu + * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom + * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC850 1 +#define CONFIG_MPC850SAR 1 +#define CONFIG_FADS 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 + +#if 0 +#define MPC8XX_FACT 10 /* Multiply by 10 */ +#define MPC8XX_XIN 50000000 /* 50 MHz in */ +#else +#define MPC8XX_FACT 12 /* Multiply by 12 */ +#define MPC8XX_XIN 4000000 /* 4 MHz in */ +#endif +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#if 1 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */ +#define CONFIG_BOOTARGS " " + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT ":>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 +#define CFG_IMMR_SIZE ((uint)(64 * 1024)) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Also NOTE that it doesn't mean SDRAM - it means MEMORY. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ +#define CFG_FLASH_BASE 0x02800000 +#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ +#if 0 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer * + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (((MPC8XX_FACT-1) << 20) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + + /*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the +* entire address space, we have to set the memory controller +* differently. Normally, you write the option register +* first, and then enable the chip select by writing the +* base register. For CS0, you must write the base register +* first, followed by the option register. +*/ + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ +/* the other CS:s are determined by looking at parameters in BCSRx */ + + +#define BCSR_ADDR ((uint) 0x02100000) +#define BCSR_SIZE ((uint)(64 * 1024)) + +#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ + +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +/* BCSRx - Board Control and Status Registers */ +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ +#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) + + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +#define CFG_MAMR 0x13a01114 +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* values according to the manual */ + + +#define PCMCIA_MEM_ADDR ((uint)0xff020000) +#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) + +#define BCSR0 ((uint) (BCSR_ADDR + 00)) +#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) +#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) +#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) +#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) + +/* FADS bitvalues by Helmut Buchsbaum + * see MPC8xxADS User's Manual for a proper description + * of the following structures + */ + +#define BCSR0_ERB ((uint)0x80000000) +#define BCSR0_IP ((uint)0x40000000) +#define BCSR0_BDIS ((uint)0x10000000) +#define BCSR0_BPS_MASK ((uint)0x0C000000) +#define BCSR0_ISB_MASK ((uint)0x01800000) +#define BCSR0_DBGC_MASK ((uint)0x00600000) +#define BCSR0_DBPC_MASK ((uint)0x00180000) +#define BCSR0_EBDF_MASK ((uint)0x00060000) + +#define BCSR1_FLASH_EN ((uint)0x80000000) +#define BCSR1_DRAM_EN ((uint)0x40000000) +#define BCSR1_ETHEN ((uint)0x20000000) +#define BCSR1_IRDEN ((uint)0x10000000) +#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) +#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) +#define BCSR1_BCSR_EN ((uint)0x02000000) +#define BCSR1_RS232EN_1 ((uint)0x01000000) +#define BCSR1_PCCEN ((uint)0x00800000) +#define BCSR1_PCCVCC0 ((uint)0x00400000) +#define BCSR1_PCCVPP_MASK ((uint)0x00300000) +#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) +#define BCSR1_RS232EN_2 ((uint)0x00040000) +#define BCSR1_SDRAM_EN ((uint)0x00020000) +#define BCSR1_PCCVCC1 ((uint)0x00010000) + +#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) +#define BCSR2_FLASH_PD_SHIFT 28 +#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) +#define BCSR2_DRAM_PD_SHIFT 23 +#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) +#define BCSR2_DBREVNR_MASK ((uint)0x00030000) + +#define BCSR3_DBID_MASK ((ushort)0x3800) +#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) +#define BCSR3_BREVNR0 ((ushort)0x0080) +#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) +#define BCSR3_BREVN1 ((ushort)0x0008) +#define BCSR3_BREVN2_MASK ((ushort)0x0003) + +#define BCSR4_ETHLOOP ((uint)0x80000000) +#define BCSR4_TFPLDL ((uint)0x40000000) +#define BCSR4_TPSQEL ((uint)0x20000000) +#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) +#ifdef CONFIG_MPC823 +#define BCSR4_USB_EN ((uint)0x08000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860SAR +#define BCSR4_UTOPIA_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860SAR */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETH_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_USB_SPEED ((uint)0x04000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHCFG0 ((uint)0x04000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VCCO ((uint)0x02000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHFDE ((uint)0x02000000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VIDEO_ON ((uint)0x00800000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC823 +#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHCFG1 ((uint)0x00400000) +#endif /* CONFIG_MPC860T */ +#ifdef CONFIG_MPC823 +#define BCSR4_VIDEO_RST ((uint)0x00200000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETHRST ((uint)0x00200000) +#endif /* CONFIG_MPC860T */ +#define BCSR4_MODEM_EN ((uint)0x00100000) +#define BCSR4_DATA_VOICE ((uint)0x00080000) + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + +#define CONFIG_DISK_SPINUP_TIME 1000000 + + +/* PCMCIA configuration */ + +#define PCMCIA_MAX_SLOTS 2 + +#ifdef CONFIG_MPC860 +#define PCMCIA_SLOT_A 1 +#endif + +#define CFG_DAUGHTERBOARD + +#endif /* __CONFIG_H */ diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h new file mode 100644 index 0000000..18de6b0 --- /dev/null +++ b/include/configs/FADS860T.h @@ -0,0 +1,56 @@ +/* + * A collection of structures, addresses, and values associated with + * the Motorola 860T FADS board. Copied from the MBX stuff. + * Magnus Damm added defines for 8xxrom and extended bd_info. + * Helmut Buchsbaum added bitvalues for BCSRx + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * Values common to all FADS family boards are in board/fads/fads.h + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* board type */ +#define CONFIG_FADS 1 /* old/new FADS + new ADS */ + +/* processor type */ +#define CONFIG_MPC860T 1 /* 860T */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 38400 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ + +#if 0 /* old FADS */ +# define CFG_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ +#else /* new FADS */ +# define CFG_8XX_FACT 10 /* 5 MHz oscillator on EXTCLK */ +#endif + +#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ 1 + +#include "fads.h" + +#ifdef USE_REAL_FLASH_VALUES +/* + * These values fit our FADS860T ... + * The "default" behaviour with 1Mbyte initial doesn't work for us! + */ +#undef CFG_OR0_PRELIM +#undef CFG_BR0_PRELIM +#define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */ +#define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */ +#endif + +#define CFG_DAUGHTERBOARD /* FADS has processor-specific daughterboard */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h new file mode 100644 index 0000000..8babee1 --- /dev/null +++ b/include/configs/FLAGADM.h @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */ +#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/ + +#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ +#define CONFIG_8xx_CONS_SMC2 1 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ + +#undef CONFIG_CLOCKS_IN_MHZ + +#if 0 +#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp" +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/ram ip=off panic=1;" \ + "bootm 40040000 400e0000" +#else +#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1" +#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000" +#endif /* 0|1*/ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \ + CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \ + CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "EEG> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x40040000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +/* This is a litlebit wasteful, but one sector is 128kb and we have to + * assigne a whole sector for the environment, so that we can safely + * erase and write it without disturbing the boot sector + */ +#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#ifdef CONFIG_WATCHDOG +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \ + SIUMCR_MLRC01 | SIUMCR_GB5E) +#define CFG_SIUMCR (CFG_PRE_SIUMCR | SIUMCR_DLK) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit miltiplier of 0x00b i.e. operation clock is + * 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz + */ +#define CFG_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +#define CFG_DER 0 + +/* + * In the Flaga DM we have: + * Flash on BR0/OR0/CS0a at 0x40000000 + * Display on BR1/OR1/CS1 at 0x20000000 + * SDRAM on BR2/OR2/CS2 at 0x00000000 + * Free BR3/OR3/CS3 + * DSP1 on BR4/OR4/CS4 at 0x80000000 + * DSP2 on BR5/OR5/CS5 at 0xa0000000 + * + * For now we just configure the Flash and the SDRAM and leave the others + * untouched. +*/ + +#define CFG_FLASH_PROTECTION 0 + +#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_OR_AM 0xff000000 /* OR addr mask */ +#define CFG_OR_ATM 0x00006000 + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \ + OR_SCY_3_CLK | OR_TRLX | OR_EHTR ) + +#define CFG_OR0_PRELIM (CFG_OR_AM | CFG_OR_ATM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* + * BR2 and OR2 (SDRAM) + * + */ +#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM ( 0x00000800 ) + +#define CFG_OR2_PRELIM (CFG_OR_AM | CFG_OR_TIMING_SDRAM) +#define CFG_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#define CFG_BR2 CFG_BR2_PRELIM +#define CFG_OR2 CFG_OR2_PRELIM + +/* + * MAMR settings for SDRAM + */ +#define CFG_MAMR_48_SDR (CFG_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \ + | MAMR_G0CLA_A11) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 0x0F000000 + +/* + * BR4 and OR4 (DSP1) + * + * We do not wan't preliminary setup of the DSP, anyway we need the + * UPMB setup correctly before we can access the DSP. + * +*/ +#define DSP_BASE 0x80000000 + +#define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS) +#define CFG_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V ) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h new file mode 100644 index 0000000..0dd21bc --- /dev/null +++ b/include/configs/FPS850L.h @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */ + +#undef CONFIG_8xx_CONS_SMC1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 19200 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ + "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ + "nfsaddrs=10.0.0.99:10.0.0.2" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~( \ + CFG_CMD_CONSOLE | \ + CFG_CMD_BDI | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_CACHE ) ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h new file mode 100644 index 0000000..423d74e --- /dev/null +++ b/include/configs/FPS860L.h @@ -0,0 +1,330 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */ + +#undef CONFIG_8xx_CONS_SMC1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ + "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ + "nfsaddrs=10.0.0.99:10.0.0.2" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ + OR_SCY_5_CLK | OR_EHTR) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h new file mode 100644 index 0000000..db42fd0 --- /dev/null +++ b/include/configs/G2000.h @@ -0,0 +1,426 @@ +/* + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_G2000 1 /* ...on a PLU405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#if 0 /* test-only */ +#define CONFIG_BAUDRATE 115200 +#else +#define CONFIG_BAUDRATE 9600 +#endif + +#define CONFIG_PREBOOT + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "panic=1\0" \ + "flash_nfs=run nfsargs addip addmisc;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addmisc;bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/g2000/pImage\0" \ + "kernel_addr=ff800000\0" \ + "ramdisk_addr=ff900000\0" \ + "pciconfighost=yes\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_NET_MULTI 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY1_ADDR 1 /* PHY address */ + +#if 0 /* test-only */ +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#if 0 /* test-only */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------------*/ +/* adding Ethernet setting: FTS OUI 00:11:0B */ +/*----------------------------------------------------------------------------*/ +#define CONFIG_ETHADDR 00:11:0B:00:00:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:11:0B:00:00:02 +#define CONFIG_IPADDR 10.48.8.178 +#define CONFIG_IP1ADDR 10.48.8.188 +#define CONFIG_NETMASK 255.255.255.128 +#define CONFIG_SERVERIP 10.48.8.138 + +/*----------------------------------------------------------------------- + * RTC stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_RTC_DS1337 +#define CFG_I2C_RTC_ADDR 0x68 + +#if 0 /* test-only */ +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#endif + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#if 0 /* APC405 */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_BASE 0xFE000000 /* test-only...*/ +#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */ +#else /* G2000 */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/ +#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */ +#endif + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MONITOR_BASE 0xFFFC0000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#if 1 /* test-only */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#else /* DEFAULT: environment in flash, using redundand flash sectors */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_ADDR 0xFFFA0000 /* environment starts before u-boot */ +#define CFG_ENV_SECT_SIZE 0x20000 /* 128k bytes may be used for env vars*/ + +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ +/* CAT24WC08/16... */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Intel Strata Flash) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFF87A000 /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 1 ( Power TAU) initialization */ +/* #define CFG_EBC_PB1AP 0x04041000 */ +/* #define CFG_EBC_PB1CR 0xF0018000 */ /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB1AP 0x00000000 +#define CFG_EBC_PB1CR 0x00000000 + +/* Memory Bank 2 (Intel Flash) initialization */ +#define CFG_EBC_PB2AP 0x00000000 +#define CFG_EBC_PB2CR 0x00000000 + +/* Memory Bank 3 (NAND) initialization */ +#define CFG_EBC_PB3AP 0x92015480 +#define CFG_EBC_PB3CR 0xF40B8000 /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */ + +/* Memory Bank 4 (FPGA regs) initialization */ +#define CFG_EBC_PB4AP 0x00000000 +#define CFG_EBC_PB4CR 0x00000000 /* leave it blank */ + +#define CFG_NAND_BASE 0xF4000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + * + * following GPIO setting changed for G20000, 080304 + */ +#define CFG_GPIO0_OSRH 0x40005555 +#define CFG_GPIO0_OSRL 0x40000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555445 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xF7FF8014 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 1 +#define PLLMR0_DEFAULT PLLMR0_266_66_33_33 +#define PLLMR1_DEFAULT PLLMR1_266_66_33_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h new file mode 100644 index 0000000..de8f7ae --- /dev/null +++ b/include/configs/GEN860T.h @@ -0,0 +1,766 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Keith Outwater, keith_outwater@mvis.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config_GEN860T.h - board specific configuration options + */ + +#ifndef __CONFIG_GEN860T_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC860 +#define CONFIG_GEN860T + +/* + * Identify the board + */ +#if !defined(CONFIG_SC) +#define CONFIG_IDENT_STRING " B2" +#else +#define CONFIG_IDENT_STRING " SC" +#endif + +/* + * Don't depend on the RTC clock to determine clock frequency - + * the 860's internal rtc uses a 32.768 KHz clock which is + * generated by the DS1337 - and the DS1337 clock can be turned off. + */ +#if !defined(CONFIG_SC) +#define CONFIG_8xx_GCLK_FREQ 66600000 +#else +#define CONFIG_8xx_GCLK_FREQ 48000000 +#endif + +/* + * The RS-232 console port is on SMC1 + */ +#define CONFIG_8xx_CONS_SMC1 +#define CONFIG_BAUDRATE 38400 + +/* + * Set allowable console baud rates + */ +#define CFG_BAUDRATE_TABLE { 9600, \ + 19200, \ + 38400, \ + 57600, \ + 115200, \ + } + +/* + * Print console information + */ +#undef CFG_CONSOLE_INFO_QUIET + +/* + * Set the autoboot delay in seconds. A delay of -1 disables autoboot + */ +#define CONFIG_BOOTDELAY 5 + +/* + * Pass the clock frequency to the Linux kernel in units of MHz + */ +#define CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_PREBOOT \ + "echo;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +/* + * Turn off echo for serial download by default. Allow baud rate to be changed + * for downloads + */ +#undef CONFIG_LOADS_ECHO +#define CFG_LOADS_BAUD_CHANGE + +/* + * Set default load address for tftp network downloads + */ +#define CFG_TFTP_LOADADDR 0x01000000 + +/* + * Turn off the watchdog timer + */ +#undef CONFIG_WATCHDOG + +/* + * Do not reboot if a panic occurs + */ +#define CONFIG_PANIC_HANG + +/* + * Enable the status LED + */ +#define CONFIG_STATUS_LED + +/* + * Reset address. We pick an address such that when an instruction + * is executed at that address, a machine check exception occurs + */ +#define CFG_RESET_ADDRESS ((ulong) -1) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE \ + ) + +/* + * The GEN860T network interface uses the on-chip 10/100 FEC with + * an Intel LXT971A PHY connected to the 860T's MII. The PHY's + * MII address is hardwired on the board to zero. + */ +#define CONFIG_FEC_ENET +#define CFG_DISCOVER_PHY +#define CONFIG_MII +#define CONFIG_PHY_ADDR 0 + +/* + * Set default IP stuff just to get bootstrap entries into the + * environment so that we can autoscript the full default environment. + */ +#define CONFIG_ETHADDR 9a:52:63:15:85:25 +#define CONFIG_SERVERIP 10.0.4.201 +#define CONFIG_IPADDR 10.0.4.111 + +/* + * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to + * the MPC860T I2C interface. + */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ +#define CFG_ENV_EEPROM_SIZE (32 * 1024) + +/* + * Enable I2C and select the hardware/software driver + */ +#define CONFIG_HARD_I2C 1 /* CPM based I2C */ +#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ + +#ifdef CONFIG_HARD_I2C +#define CFG_I2C_SPEED 100000 /* clock speed in Hz */ +#define CFG_I2C_SLAVE 0xFE /* I2C slave address */ +#endif + +#ifdef CONFIG_SOFT_I2C +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif + +/* + * Allow environment overwrites by anyone + */ +#define CONFIG_ENV_OVERWRITE + +#if !defined(CONFIG_SC) +/* + * The MPC860's internal RTC is horribly broken in rev D masks. Three + * internal MPC860T circuit nodes were inadvertently left floating; this + * causes KAPWR current in power down mode to be three orders of magnitude + * higher than specified in the datasheet (from 10 uA to 10 mA). No + * reasonable battery can keep that kind RTC running during powerdown for any + * length of time, so we use an external RTC on the I2C bus instead. + */ +#define CONFIG_RTC_DS1337 +#define CFG_I2C_RTC_ADDR 0x68 + +#else +/* + * No external RTC on SC variant, so we're stuck with the internal one. + */ +#define CONFIG_RTC_MPC8xx +#endif + +/* + * Power On Self Test support + */ +#define CONFIG_POST ( CFG_POST_CACHE | \ + CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_SPR ) + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +/* + * List of available monitor commands. Use the system default list + * plus add some of the "non-standard" commands back in. + * See ./cmd_confdefs.h + */ +#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_FPGA | \ + CFG_CMD_MII | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_POST_DIAG ) + +#if !defined(CONFIG_SC) +#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC ) +#else +#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS +#endif + +/* + * There is no IDE/PCMCIA hardware support on the board. + */ +#undef CONFIG_IDE_PCMCIA +#undef CONFIG_IDE_LED +#undef CONFIG_IDE_RESET + +/* + * Enable the call to misc_init_r() for miscellaneous platform + * dependent initialization. + */ +#define CONFIG_MISC_INIT_R + +/* + * Enable call to last_stage_init() so we can twiddle some LEDS :) + */ +#define CONFIG_LAST_STAGE_INIT + +/* + * Virtex2 FPGA configuration support + */ +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA CFG_XILINX_VIRTEX2 +#define CFG_FPGA_PROG_FEEDBACK + + +/************************************************************************ + * This must be included AFTER the definition of any CONFIG_COMMANDS + */ +#include + +/* + * Verbose help from command monitor. + */ +#define CFG_LONGHELP +#if !defined(CONFIG_SC) +#define CFG_PROMPT "B2> " +#else +#define CFG_PROMPT "SC> " +#endif + + +/* + * Use the "hush" command parser + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * Set buffer size for console I/O + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 +#else +#define CFG_CBSIZE 256 +#endif + +/* + * Print buffer size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +/* + * Maximum number of arguments that a command can accept + */ +#define CFG_MAXARGS 16 + +/* + * Boot argument buffer size + */ +#define CFG_BARGSIZE CFG_CBSIZE + +/* + * Default memory test range + */ +#define CFG_MEMTEST_START 0x0100000 +#define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024)) + +/* + * Select the more full-featured memory test + */ +#define CFG_ALT_MEMTEST + +/* + * Default load address + */ +#define CFG_LOAD_ADDR 0x01000000 + +/* + * Set decrementer frequency (1 ms ticks) + */ +#define CFG_HZ 1000 + +/* + * Device memory map (after SDRAM remap to 0x0): + * + * CS Device Base Addr Size + * ---------------------------------------------------- + * CS0* Flash 0x40000000 64 M + * CS1* SDRAM 0x00000000 16 M + * CS2* Disk-On-Chip 0x50000000 32 K + * CS3* FPGA 0x60000000 64 M + * CS4* SelectMap 0x70000000 32 K + * CS5* Mil-Std 1553 I/F 0x80000000 32 K + * CS6* Unused + * CS7* Unused + * IMMR 860T Registers 0xfff00000 + */ + +/* + * Base addresses and block sizes + */ +#define CFG_IMMR 0xFF000000 + +#define SDRAM_BASE 0x00000000 +#define SDRAM_SIZE (64 * 1024 * 1024) + +#define FLASH_BASE 0x40000000 +#define FLASH_SIZE (16 * 1024 * 1024) + +#define DOC_BASE 0x50000000 +#define DOC_SIZE (32 * 1024) + +#define FPGA_BASE 0x60000000 +#define FPGA_SIZE (64 * 1024 * 1024) + +#define SELECTMAP_BASE 0x70000000 +#define SELECTMAP_SIZE (32 * 1024) + +#define M1553_BASE 0x80000000 +#define M1553_SIZE (64 * 1024) + +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE SDRAM_BASE + +/* + * FLASH organization + */ +#define CFG_FLASH_BASE FLASH_BASE +#define CFG_FLASH_SIZE FLASH_SIZE +#define CFG_FLASH_SECT_SIZE (128 * 1024) +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 128 + +/* + * The timeout values are for an entire chip and are in milliseconds. + * Yes I know that the write timeout is huge. Accroding to the + * datasheet a single byte takes 630 uS (round to 1 ms) max at worst + * case VCC and temp after 100K programming cycles. It works out + * to 280 minutes (might as well be forever). + */ +#define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000) +#define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1) + +/* + * Allow direct writes to FLASH from tftp transfers (** dangerous **) + */ +#define CFG_DIRECT_FLASH_TFTP + +/* + * Reserve memory for U-Boot. + */ +#define CFG_MAX_UBOOT_SECTS 4 +#define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE) +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +/* + * Select environment placement. NOTE that u-boot.lds must + * be edited if this is changed! + */ +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM + +#if defined(CFG_ENV_IS_IN_EEPROM) +#define CFG_ENV_SIZE (2 * 1024) +#define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024)) +#else +#define CFG_ENV_SIZE 0x1000 +#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE + +/* + * This ultimately gets passed right into the linker script, so we have to + * use a number :( + */ +#define CFG_ENV_OFFSET 0x060000 +#endif + +/* + * Reserve memory for malloc() + */ +#define CFG_MALLOC_LEN (128 * 1024) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */ +#endif + +/*------------------------------------------------------------------------ + * SYPCR - System Protection Control UM 11-9 + * ----------------------------------------------------------------------- + * SYPCR can only be written once after reset! + * + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR ( SYPCR_SWTC | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ + SYPCR_SWE | \ + SYPCR_SWRI | \ + SYPCR_SWP \ + ) +#else +#define CFG_SYPCR ( SYPCR_SWTC | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ + SYPCR_SWP \ + ) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration UM 11-6 + *----------------------------------------------------------------------- + * Set debug pin mux, enable SPKROUT and GPLB5*. + */ +#define CFG_SIUMCR ( SIUMCR_DBGC11 | \ + SIUMCR_DBPC11 | \ + SIUMCR_MLRC11 | \ + SIUMCR_GB5E \ + ) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control UM 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freeze enabled + */ +#define CFG_TBSCR ( TBSCR_REFA | \ + TBSCR_REFB | \ + TBSCR_TBF \ + ) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register UM 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC ( RTCSC_SEC | \ + RTCSC_ALR | \ + RTCSC_RTF | \ + RTCSC_RTE \ + ) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control UM 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR ( PISCR_PS | \ + PISCR_PITF \ + ) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit. Set MF for 1:2:1 mode. + */ +#define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \ + PLPRCR_SPLSS | \ + PLPRCR_TEXPS | \ + PLPRCR_TMIST \ + ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register UM 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 + +#if !defined(CONFIG_SC) +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ + SCCR_DFNL000 | \ + SCCR_DFNH000 \ + ) +#else +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ + SCCR_DFNL000 | \ + SCCR_DFNH000 | \ + SCCR_RTDIV | \ + SCCR_RTSEL \ + ) +#endif + +/*----------------------------------------------------------------------- + * DER - Debug Enable Register UM 37-46 + *----------------------------------------------------------------------- + * Mask all events that can cause entry into debug mode + */ +#define CFG_DER 0 + +/* + * Initialize Memory Controller: + * + * BR0 and OR0 (FLASH memory) + */ +#define FLASH_BASE0_PRELIM FLASH_BASE + +/* + * Flash address mask + */ +#define CFG_PRELIM_OR_AM 0xfe000000 + +/* + * FLASH timing: + * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 + */ +#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \ + OR_ACS_DIV2 | \ + OR_BI | \ + OR_SCY_2_CLK | \ + OR_TRLX | \ + OR_EHTR \ + ) + +#define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \ + CFG_OR_TIMING_FLASH \ + ) + +#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ + BR_MS_GPCM | \ + BR_PS_8 | \ + BR_V \ + ) + +/* + * SDRAM configuration + */ +#define CFG_OR1_AM 0xfc000000 +#define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \ + OR_CSNT_SAM \ + ) + +#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ + BR_MS_UPMA | \ + BR_PS_32 | \ + BR_V \ + ) + +/* + * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank + * of 256 MBit SDRAM + */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 + +/* + * Periodic timer for refresh @ 33 MHz system clock + */ +#define CFG_MAMR_PTA 64 + +/* + * MAMR settings for SDRAM + */ +#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ + MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | \ + MAMR_DSA_1_CYCL | \ + MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | \ + MAMR_WLFA_1X | \ + MAMR_TLFA_4X \ + ) + +/* + * CS2* configuration for Disk On Chip: + * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, + * no burst. + */ +#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ + OR_CSNT_SAM | \ + OR_ACS_DIV2 | \ + OR_BI | \ + OR_SCY_2_CLK | \ + OR_TRLX | \ + OR_EHTR \ + ) + +#define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V \ + ) + +/* + * CS3* configuration for FPGA: + * 33 MHz bus with SCY=15, no burst. + * The FPGA uses TA and TEA to terminate bus cycles, but we + * clear SETA and set the cycle length to a large number so that + * the cycle will still complete even if there is a configuration + * error that prevents TA from asserting on FPGA accesss. + */ +#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ + OR_SCY_15_CLK | \ + OR_BI \ + ) + +#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ + BR_PS_32 | \ + BR_MS_GPCM | \ + BR_V \ + ) +/* + * CS4* configuration for FPGA SelectMap configuration interface. + * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge + * of GCLK1_50 + */ +#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ + OR_G5LS | \ + OR_BI \ + ) + +#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ + BR_PS_8 | \ + BR_MS_UPMB | \ + BR_V \ + ) + +/* + * CS5* configuration for Mil-Std 1553 databus interface. + * 33 MHz bus, GPCM, no burst. + * The 1553 interface uses TA and TEA to terminate bus cycles, + * but we clear SETA and set the cycle length to a large number so that + * the cycle will still complete even if there is a configuration + * error that prevents TA from asserting on FPGA accesss. + */ +#define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ + OR_SCY_15_CLK | \ + OR_EHTR | \ + OR_TRLX | \ + OR_CSNT_SAM | \ + OR_BI \ + ) + +#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ + BR_PS_16 | \ + BR_MS_GPCM | \ + BR_V \ + ) + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Disk On Chip (millenium) configuration + */ +#if !defined(CONFIG_SC) +#define CFG_MAX_DOC_DEVICE 1 +#undef CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM +#undef CFG_DOC_PASSIVE_PROBE +#endif + +/* + * FEC interrupt assignment + */ +#define FEC_INTERRUPT SIU_LEVEL1 + +/* + * Sanity checks + */ +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#endif /* __CONFIG_GEN860T_H */ + +/* vim: set ts=4 tw=78 ai shiftwidth=4: */ diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h new file mode 100644 index 0000000..8c01d97 --- /dev/null +++ b/include/configs/GENIETV.h @@ -0,0 +1,354 @@ + /* + * A collection of structures, addresses, and values associated with + * the Motorola 860T FADS board. Copied from the MBX stuff. + * Magnus Damm added defines for 8xxrom and extended bd_info. + * Helmut Buchsbaum added bitvalues for BCSRx + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + */ + +/* + * The GENIETV is using the following physical memorymap (copied from + * the FADS configuration): + * + * ff020000 -> ff02ffff : pcmcia + * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM + * ff000000 -> ff00ffff : IMAP internal in the cpu + * 30000000 -> 300fffff : flash connected to CS0 + * 00000000 -> nnnnnnnn : sdram setup by U-Boot + * + * CS pins are connected as follows: + * + * CS0 -512Kb boot flash + * CS1 - SDRAM #1 + * CS2 - SDRAM #2 + * CS3 - Flash #1 + * CS4 - Flash #2 + * CS5 - Lon (if present) + * CS6 - PCMCIA #1 + * CS7 - PCMCIA #2 + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ +#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ + +#define CFG_ALLOC_DPRAM /* Use dynamic DPRAM allocation */ + +#define CFG_AUTOLOAD "n" /* No autoload */ + +/*#define CONFIG_VIDEO 1 / To enable the video initialization */ +/*#define CONFIG_VIDEO_ADDR 0x00200000 */ +/*#define CONFIG_HARD_I2C 1 / I2C with hardware support */ +/*#define CONFIG_PCMCIA 1 / To enable the PCMCIA initialization */ + +/*#define CFG_PCMCIA_IO_ADDR 0xff020000 */ +/*#define CFG_PCMCIA_IO_SIZE 0x10000 */ +/*#define CFG_PCMCIA_MEM_ADDR 0xe0000000 */ +/*#define CFG_PCMCIA_MEM_SIZE 0x10000 */ + +/* Video related */ + +/*#define CONFIG_VIDEO_LOGO 1 / Show the logo */ +/*#define CONFIG_VIDEO_ENCODER_AD7177 1 / Enable this encoder */ +/*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR 0xF4 / ALSB to ground */ + +/* Wireless 56Khz 4PPM keyboard on SMCx */ + +/*#define CONFIG_KEYBOARD 0 */ +/*#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 / SMC to use (0 indexed) */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#include + +#define CONFIG_GENIETV 1 +#define CONFIG_MPC823 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 + +#define MPC8XX_FACT 12 /* Multiply by 12 */ +#define MPC8XX_XIN 5000000 /* 4 MHz clock */ + +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) +#define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20) +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#if 1 +#define CONFIG_BOOTDELAY 1 /* autoboot after 2 seconds */ +#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ +#define CONFIG_BOOTARGS "" +#define CONFIG_BOOTCOMMAND \ +"bootp; tftp; " \ +"setenv bootargs console=tty0 console=ttyS0 " \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ +"bootm " +#else +#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT ":>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 8 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 +#define CFG_IMMR_SIZE ((uint)(64 * 1024)) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Also NOTE that it doesn't mean SDRAM - it means MEMORY. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x02800000 +#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ +#if 0 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/ + +/* values according to the manual */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + * +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer * + * interrupt status bit - leave PLL multiplication factor unchanged ! + * + * #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the +* entire address space, we have to set the memory controller +* differently. Normally, you write the option register +* first, and then enable the chip select by writing the +* base register. For CS0, you must write the base register +* first, followed by the option register. +*/ + +/* + * Init Memory Controller: + * + * BR0 and OR0(FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ + +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */ + +/* FLASH timing */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ + OR_SCY_15_CLK | OR_TRLX ) + +/*#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) */ +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */ + +/* + * BR1/2 and OR1/2 (SDRAM) +*/ + +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define SDRAM_MAX_SIZE 0x04000000 /* 64Mb bank */ +#define SDRAM_BASE1_PRELIM 0x00000000 /* First bank */ +#define SDRAM_BASE2_PRELIM 0x10000000 /* Second bank */ + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MBMR_PTB 0x5d /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 +/* + * MBMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \ + | MAMR_TLFA_4X) /* 0x5d802114 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* values according to the manual */ + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + +/* + * MPC8xx CPM Options + */ +#define CONFIG_SCC_ENET 1 + +#define CONFIG_DISK_SPINUP_TIME 1000000 + +/* PCMCIA configuration */ + +#define PCMCIA_MAX_SLOTS 1 +#define PCMCIA_SLOT_B 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/GTH.h b/include/configs/GTH.h new file mode 100644 index 0000000..03b9659 --- /dev/null +++ b/include/configs/GTH.h @@ -0,0 +1,374 @@ +/* + * Parameters for GTH board + * Based on FADS860T + * by thomas.lange@corelatus.com + + * A collection of structures, addresses, and values associated with + * the Motorola 860T FADS board. Copied from the MBX stuff. + * Magnus Damm added defines for 8xxrom and extended bd_info. + * Helmut Buchsbaum added bitvalues for BCSRx + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + */ + +/* + * ff000000 -> ff00ffff : IMAP internal in the cpu + * e0000000 -> ennnnnnn : pcmcia + * 98000000 -> 983nnnnn : FPGA 4MB + * 90000000 -> 903nnnnn : FPGA 4MB + * 80000000 -> 80nnnnnn : flash connected to CS0, final ( real ) location + * 00000000 -> nnnnnnnn : sdram + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#include + +#define CONFIG_MPC860 1 +#define CONFIG_MPC860T 1 +#define CONFIG_GTH 1 + +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ + +#define MPC8XX_FACT 3 /* Multiply by 3 */ +#define MPC8XX_XIN 16384000 /* 16.384 MHz */ +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) + +#define CONFIG_BOOTDELAY 1 /* autoboot after 0 seconds */ + +#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */ + +#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */ + +#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */ + +/* Only interrupt boot if space is pressed */ +/* If a long serial cable is connected but */ +/* other end is dead, garbage will be read */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +#if 0 +/* Net boot */ +/* Loads a tftp image and starts it */ +#define CONFIG_BOOTCOMMAND "bootp;bootm 100000" /* autoboot command */ +#define CONFIG_BOOTARGS "panic=1" +#else +/* Compact flash boot */ +#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7" +#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000" +#endif + +/* Enable watchdog */ +#define CONFIG_WATCHDOG 1 + +/* choose SCC1 ethernet (10BASET on motherboard) + * or FEC ethernet (10/100 on daughterboard) + */ +#if 1 +#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ +#undef CONFIG_FEC_ENET /* disable FEC ethernet */ +#define CFG_DISCOVER_PHY +#else +#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ +#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ +#define CFG_DISCOVER_PHY +#endif +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ + +/* Default location to load data from net */ +#define CFG_LOAD_ADDR 0x100000 + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 +#define CFG_IMMR_SIZE ((uint)(64 * 1024)) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE 0x80000000 + +#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ + +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#undef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_OFFSET 0x000E0000 +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +#define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*---------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ + +/*FIXME dont use for now */ +/*#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ +/*#define CFG_RTCSC (RTCSC_RTF) */ + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) +/* PITE */ +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control (15-29) + */ +#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ + +/* FIXME check values */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) + + /*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the +* entire address space, we have to set the memory controller +* differently. Normally, you write the option register +* first, and then enable the chip select by writing the +* base register. For CS0, you must write the base register +* first, followed by the option register. +*/ + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ +/* the other CS:s are determined by looking at parameters in BCSRx */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ + +#define CFG_REMAP_OR_AM 0xFF800000 /* 4 MB OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ + +#define FPGA_2_BASE 0x90000000 +#define FPGA_3_BASE 0x98000000 + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) + + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 ) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_ETHADDR DE:AD:BE:EF:00:01 /* Ethernet address */ + +#ifdef CONFIG_MPC860T + +/* Interrupt level assignments. +*/ +#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ + +#endif /* CONFIG_MPC860T */ + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_gth) + +#ifdef CONFIG_MPC860 +#define PCMCIA_SLOT_A 1 +#define CONFIG_PCMCIA_SLOT_A 1 +#endif + +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ + +#define PA_FRONT_LED ((u16)0x4) /* PA 13 */ +#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */ +#define PA_FL_CE ((u16)0x1000) /* PA 3 */ + +#define PB_ID_GND ((u32)1) /* PB 31 */ +#define PB_REV_1 ((u32)2) /* PB 30 */ +#define PB_REV_0 ((u32)4) /* PB 29 */ +#define PB_BLUE_LED ((u32)0x400) /* PB 21 */ +#define PB_EEPROM ((u32)0x800) /* PB 20 */ +#define PB_ID_3 ((u32)0x2000) /* PB 18 */ +#define PB_ID_2 ((u32)0x4000) /* PB 17 */ +#define PB_ID_1 ((u32)0x8000) /* PB 16 */ +#define PB_ID_0 ((u32)0x10000) /* PB 15 */ + +/* NOTE. This is reset for 100Mbit port only */ +#define PC_ENET100_RESET ((ushort)0x0080) /* PC 8 */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h new file mode 100644 index 0000000..131c215 --- /dev/null +++ b/include/configs/HH405.h @@ -0,0 +1,527 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_HH405 1 /* ...on a HH405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT "autoupd" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "pciconfighost=1\0" \ + "" + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ + +/* + * Video console + */ +#define CONFIG_VIDEO /* for sm501 video support */ + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_SM501 +#if 0 +#define CONFIG_VIDEO_SM501_32BPP +#else +#define CONFIG_VIDEO_SM501_16BPP +#endif +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CFG_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ +#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ + +#define ADD_BMP_CMD CFG_CMD_BMP +#else +#define ADD_BMP_CMD 0 +#endif /* CONFIG_VIDEO */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + ADD_BMP_CMD | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_SUPPORT_VFAT + +#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ +#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#undef CFG_CONSOLE_INFO_QUIET /* print console @ startup */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * RTC stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_RTC_DS1338 +#define CFG_I2C_RTC_ADDR 0x68 + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */ + +#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) +# define CFG_RAMBOOT 1 +#else +# undef CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x8000 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#if 0 /* test-only */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#else +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#endif +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ +#define CFG_EEPROM_WREN 1 + +#if 1 /* test-only */ +/* CAT24WC08/16... */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#else +/* CAT24WC32/64... */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ +#endif +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define LCD_BA 0xF1000000 /* Epson LCD Base Address */ +#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ +#define CFG_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/* Memory Bank 4 (Epson LCD) initialization */ +#define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ +#define CFG_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * LCD Setup + */ + +#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ +#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ +#define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ +#define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ + +/*----------------------------------------------------------------------- + * Universal Interrupt Controller (UIC) Setup + */ + +/* + * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high + */ +#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_EXT6) + +/*----------------------------------------------------------------------- + * FPGA stuff + */ + +#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ + +/* FPGA internal regs */ +#define CFG_FPGA_CTRL 0x000 + +/* FPGA Control Reg */ +#define CFG_FPGA_CTRL_REV0 0x0001 +#define CFG_FPGA_CTRL_REV1 0x0002 +#define CFG_FPGA_CTRL_VGA0_BL 0x0004 +#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008 +#define CFG_FPGA_CTRL_CF_RESET 0x0040 +#define CFG_FPGA_CTRL_PS2_PWR 0x0080 +#define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */ +#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200 +#define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */ + +#define LCD_CLK_OFF 0x0000 /* Off */ +#define LCD_CLK_02083 0x1000 /* 2.083 MHz */ +#define LCD_CLK_03135 0x2000 /* 3.135 MHz */ +#define LCD_CLK_04165 0x3000 /* 4.165 MHz */ +#define LCD_CLK_06250 0x4000 /* 6.250 MHz */ +#define LCD_CLK_08330 0x5000 /* 8.330 MHz */ +#define LCD_CLK_12500 0x6000 /* 12.50 MHz */ +#define LCD_CLK_25000 0x7000 /* 25.00 MHz */ + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555440 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xF7FE0017 + +#define CFG_LCD_ENDIAN (0x80000000 >> 7) +#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ +#define CFG_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */ +#define CFG_LCD0_RST (0x80000000 >> 30) +#define CFG_LCD1_RST (0x80000000 >> 31) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 1 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h new file mode 100644 index 0000000..6864740 --- /dev/null +++ b/include/configs/HIDDEN_DRAGON.h @@ -0,0 +1,387 @@ +/* + * (C) Copyright 2004 + * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com + * + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_HIDDEN_DRAGON 1 + +#if 0 +#define USE_DINK32 1 +#else +#undef USE_DINK32 +#endif + +#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ +#define CONFIG_BAUDRATE 9600 +#define CONFIG_DRAM_SPEED 100 /* MHz */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET0_MEMADDR 0x80000000 +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET1_MEMADDR 0x81000000 + +#define CONFIG_RTL8139 +#define _IO_BASE 0x00000000 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +/* Make sure the ethaddr can be overwritten + TODO: Remove this on final product +*/ +#define CONFIG_ENV_OVERWRITE + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x02000000 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#if defined (USE_DINK32) +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE 0x00090000 +#define CFG_RAMBOOT 1 +#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_INIT_RAM_END 0x10000 +#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#else +#undef CFG_RAMBOOT +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#endif + +#define CFG_FLASH_BASE 0xFFE00000 +#define CFG_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ + +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_ISA_MEM 0xFD000000 +#define CFG_ISA_IO 0xFE000000 + +#define CFG_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */ +#define CFG_FLASH_RANGE_SIZE 0x00200000 +#define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */ + +/* + * select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#ifdef CONFIG_SOFT_I2C +#error "Soft I2C is not configured properly. Please review!" +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM } + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + + +#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ +#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ +#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ +#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ + +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +/* TODO: Change this to VIA686A */ + +/* + * NS87308 Configuration + */ +#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ + +#define CFG_NS87308_BADDR_10 1 + +#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ + CFG_NS87308_UART2 | \ + CFG_NS87308_POWRMAN | \ + CFG_NS87308_RTC_APC ) + +#undef CFG_NS87308_PS2MOD + +#define CFG_NS87308_CS0_BASE 0x0076 +#define CFG_NS87308_CS0_CONF 0x30 +#define CFG_NS87308_CS1_BASE 0x0075 +#define CFG_NS87308_CS1_CONF 0x30 +#define CFG_NS87308_CS2_BASE 0x0074 +#define CFG_NS87308_CS2_CONF 0x30 + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#if (CONFIG_CONS_INDEX > 2) +#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000 +#else +#define CFG_NS16550_CLK 1843200 +#endif + +#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) +#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) +#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CFG_ROMNAL 7 /*rom/flash next access time */ +#define CFG_ROMFAL 11 /*rom/flash access time */ + +#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ + +/* the following are for SDRAM only*/ +#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT 4 /* data latency from read command */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 3 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#if 0 +#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ +#endif + +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + + +/* memory bank settings*/ +/* + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#if defined(USE_DINK32) +#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) +#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) +#else +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#endif + +/* PCI memory */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 36 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* values according to the manual */ +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +#undef NR_8259_INTS +#define NR_8259_INTS 1 + +#define CONFIG_DISK_SPINUP_TIME 1000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h new file mode 100644 index 0000000..7cce876 --- /dev/null +++ b/include/configs/HMI10.h @@ -0,0 +1,493 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_HMI10 +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ + +#define CONFIG_LCD +#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */ + +#ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ +#endif + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ +#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ +#define CONFIG_PS2SERIAL 2 /* .. on COM3 */ +#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/HMI10/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOARD_EARLY_INIT_R 1 +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +/* Software (bit-bang) I2C driver configuration */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +#ifdef CONFIG_SPLASH_SCREEN +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#else +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0100000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4100000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8100000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC100000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) +#define PCMCIA_MEM_WIN_NO 5 +#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ +#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */ +#define CONFIG_IDE_LED 1 /* LED for ide supported */ +#endif + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h new file mode 100644 index 0000000..eb627e8 --- /dev/null +++ b/include/configs/HUB405.h @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_HUB405 1 /* ...on a HUB405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/* Ethernet stuff */ +#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ +#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#undef CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (8 Bit Peripheral: UART) initialization */ +#if 0 +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#else +#define CFG_EBC_PB2AP 0x92015480 +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#endif + +#define DUART0_BA 0xF0000000 /* DUART Base Address */ +#define DUART1_BA 0xF0000008 /* DUART Base Address */ +#define DUART2_BA 0xF0000010 /* DUART Base Address */ +#define DUART3_BA 0xF0000018 /* DUART Base Address */ +#define CFG_NAND_BASE 0xF4000000 + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555445 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xF7FE0014 + +#define CFG_DUART_RST (0x80000000 >> 14) +#define CFG_UART2_RS232 (0x80000000 >> 5) +#define CFG_UART3_RS232 (0x80000000 >> 6) +#define CFG_UART4_RS232 (0x80000000 >> 7) +#define CFG_UART5_RS232 (0x80000000 >> 8) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 1 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h new file mode 100644 index 0000000..35d84ae --- /dev/null +++ b/include/configs/IAD210.h @@ -0,0 +1,379 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + + +# ifdef DEBUG +# warning DEBUG Defined +# endif /* DEBUG */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC860 1 +#define CONFIG_IAD210 1 /* ...on a IAD210 module */ +#define CONFIG_MPC860T 1 +#define CONFIG_MPC862 1 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ + +#undef CONFIG_8xx_CONS_SMC1 +#undef CONFIG_8xx_CONS_SMC2 +#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */ +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 + + +# define MPC8XX_FACT 16 +# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */ +# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#if 0 +# define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +/* using this define saves us updating another source file */ +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#undef CONFIG_BOOTARGS +/* #define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" +*/ + +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/nfs" \ + "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ +# define CONFIG_FEC_ENET 1 /* use FEC ethernet */ +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY 1 +# define CONFIG_FEC_UTOPIA 1 +# define CONFIG_ETHADDR 08:00:06:26:A2:6D +# define CONFIG_IPADDR 192.168.28.128 +# define CONFIG_SERVERIP 139.10.137.138 +# define CFG_DISCOVER_PHY 1 + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xDD +# define CFG_I2C_EEPROM_ADDR 0x50 +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 +#define CFG_IMMR_SIZE ((uint)(64 * 1024)) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x08000000 +#define CFG_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */ + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#if defined(DEBUG) +# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif + +# define CFG_MONITOR_BASE CFG_FLASH_BASE +# define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control (15-29) + */ +#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 + +#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ + SCCR_DFLCD000 |SCCR_DFALCD00 ) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ +#define CFG_RCCR 0x0020 + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + */ +#define PCMCIA_MEM_ADDR ((uint)0xff020000) +#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the +* entire address space, we have to set the memory controller +* differently. Normally, you write the option register +* first, and then enable the chip select by writing the +* base register. For CS0, you must write the base register +* first, followed by the option register. +*/ + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0xF8000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xF8000000 /* OR addr mask */ + +/* FLASH timing: + TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ + OR_SCY_3_CLK | OR_EHTR) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4) +#define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 124 /* start with divider for 64 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#ifdef CONFIG_MPC860T + +/* Interrupt level assignments. +*/ +#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ + +#endif /* CONFIG_MPC860T */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h new file mode 100644 index 0000000..cd17935 --- /dev/null +++ b/include/configs/ICU862.h @@ -0,0 +1,456 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC860 1 +#define CONFIG_MPC860T 1 +#define CONFIG_ICU862 1 +#define CONFIG_MPC862 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ + +#ifdef CONFIG_100MHz +#define MPC8XX_FACT 24 /* Multiply by 24 */ +#define MPC8XX_XIN 4165000 /* 4.165 MHz in */ +#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) + /* define if cant' use get_gclk_freq */ +#else +#if 1 /* for 50MHz version of processor */ +#define MPC8XX_FACT 12 /* Multiply by 12 */ +#define MPC8XX_XIN 4000000 /* 4 MHz in */ +#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */ +#else /* for 80MHz version of processor */ +#define MPC8XX_FACT 20 /* Multiply by 20 */ +#define MPC8XX_XIN 4000000 /* 4 MHz in */ +#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */ +#endif +#endif + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ +#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ +#define CONFIG_MII 1 +#if 1 +#define CFG_DISCOVER_PHY 1 +#else +#undef CFG_DISCOVER_PHY +#endif + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xFE +# define CFG_I2C_EEPROM_ADDR 0x50 +# define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */ + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 +#define CFG_IMMR_SIZE ((uint)(64 * 1024)) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#if 0 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#else +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00F40000 + +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ +#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control (15-29) + */ +#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */ +#define SCCR_MASK 0 +#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ + SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01) +#else /* up to 50 MHz we use a 1:1 clock */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ + SCCR_DFLCD000 |SCCR_DFALCD00 ) +#endif /* CONFIG_100MHz */ + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ +#define CFG_RCCR 0x0020 + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * PCMCIA Power Switch + * + * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to + * control the voltages on the PCMCIA slot which is connected to Port B + *----------------------------------------------------------------------- + */ + /* Output pins */ +#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */ +#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */ +#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */ +#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */ +#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */ +#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \ + TPS2205_VPP_PGM | TPS2205_VPP_VCC | \ + TPS2205_SHDN) + + /* Input pins */ +#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */ +#define TPS2205_INPUTS ( TPS2205_OC ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + + + /*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the +* entire address space, we have to set the memory controller +* differently. Normally, you write the option register +* first, and then enable the chip select by writing the +* base register. For CS0, you must write the base register +* first, followed by the option register. +*/ + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */ + +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) + +#define CFG_OR0_PRELIM 0xFF000954 /* Real values for the board */ +#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */ + +/* + * BR1 and OR1 (SDRAM) + */ +#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +#define CFG_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */ + +#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM) +#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +#define CFG_MAMR 0x13a01114 +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#ifdef CONFIG_MPC860T + +/* Interrupt level assignments. +*/ +#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ + +#endif /* CONFIG_MPC860T */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h new file mode 100644 index 0000000..aaa44c5 --- /dev/null +++ b/include/configs/IDS8247.h @@ -0,0 +1,525 @@ +/* + * (C) Copyright 2005 + * Heiko Schocher, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ +#define CONFIG_MPC8272_FAMILY 1 +#define CONFIG_IDS8247 1 +#define CPU_ID_STR "MPC8247" +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw " \ + "console=ttyS0,115200\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/IDS8247/uImage\0" \ + "kernel_addr=ff800000\0" \ + "ramdisk_addr=ffa00000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_MISC_INIT_R 1 + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ + +#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00000080) +#define I2C_TRISTATE (iop->pdir &= ~0x00000080) +#define I2C_READ ((iop->pdat & 0x00000080) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ + else iop->pdat &= ~0x00000080 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ + else iop->pdat &= ~0x00000100 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#if 0 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CONFIG_I2C_X +#endif + +/* + * select serial console configuration + * use the extern UART for the console + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 14745600 + +#define CFG_UART_BASE 0xE0000000 +#define CFG_UART_SIZE 0x10000 + +#define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000) + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 66666666 /* in Hz */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk + * The main FLASH is whichever is connected to *CS0. + */ +#define CFG_FLASH0_BASE 0xFFF00000 +#define CFG_FLASH0_SIZE 8 + +/* Flash bank size (for preliminary settings) + */ +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* Environment in flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x60000) +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#define CFG_NAND0_BASE 0xE1000000 + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 +#define NAND_NO_RB + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define NAND_DISABLE_CE(nand) do \ +{ \ + *(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \ +} while(0) + +#define NAND_ENABLE_CE(nand) do \ +{ \ + *(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \ +} while(0) + +#define NAND_CTL_CLRALE(nandptr) do \ +{ \ + *(((volatile __u8 *)nandptr) + 0x8) = 0; \ +} while(0) + +#define NAND_CTL_SETALE(nandptr) do \ +{ \ + *(((volatile __u8 *)nandptr) + 0x9) = 0; \ +} while(0) + +#define NAND_CTL_CLRCLE(nandptr) do \ +{ \ + *(((volatile __u8 *)nandptr) + 0x8) = 0; \ +} while(0) + +#define NAND_CTL_SETCLE(nandptr) do \ +{ \ + *(((volatile __u8 *)nandptr) + 0xa) = 0; \ +} while(0) + +#ifdef NAND_NO_RB +/* constant delay (see also tR in the datasheet) */ +#define NAND_WAIT_READY(nand) do { \ + udelay(12); \ +} while (0) +#else +/* use the R/B pin */ +#endif + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0))) + +#endif /* CFG_CMD_NAND */ + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ + +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) +#define CFG_HID0_FINAL 0 +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR 0 + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR (0x00000028 | SCCR_DFBRG01) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 16 bit FLASH + * 1 60x GPCM 8 bit NAND + * 2 60x SDRAM 32 bit SDRAM + * 3 60x GPCM 8 bit UART + * + */ + +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ + +/* Minimum mask to separate preliminary + * address ranges for CS[0:2] + */ +#define CFG_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ + +#define CFG_MPTPR 0x6600 + +/*----------------------------------------------------------------------------- + * Address for Mode Register Set (MRS) command + *----------------------------------------------------------------------------- + */ +#define CFG_MRS_OFFS 0x00000110 + + +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_SCY_6_CLK ) + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +/* Bank 1 - NAND Flash +*/ +#define CFG_NAND_BASE CFG_NAND0_BASE +#define CFG_NAND_SIZE 0x8000 + +#define CFG_OR_TIMING_NAND 0x000036 + +#define CFG_BR1_PRELIM ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND ) +#endif + +/* Bank 2 - 60x bus SDRAM + */ +#define CFG_PSRT 0x20 +#define CFG_LSRT 0x20 + +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR2_PRELIM CFG_OR2 + + +/* SDRAM initialization values +*/ +#define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A10 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\ + PSDMR_BSMA_A15_A17 |\ + PSDMR_SDA10_PBI0_A11 |\ + PSDMR_RFRC_5_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_2C |\ + PSDMR_WRC_3C |\ + PSDMR_CL_3) + +/* Bank 3 - UART +*/ + +#define CFG_BR3_PRELIM ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) +#define CFG_OR3_PRELIM (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) + +#endif /* __CONFIG_H */ diff --git a/include/configs/IP860.h b/include/configs/IP860.h new file mode 100644 index 0000000..0e20e56 --- /dev/null +++ b/include/configs/IP860.h @@ -0,0 +1,462 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_IP860 1 /* ...on a IP860 board */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \ +"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + + +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xFE +# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ +# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/*----------------------------------------------------------------------*/ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF1000000 /* Non-standard value!! */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x10000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#else +#if 0 /* need more space for I2C tests */ +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (256 << 10) +#endif +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_NVRAM +#undef DEBUG_I2C +#define CFG_ENV_IS_IN_EEPROM + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_ADDR 0x20000000 /* use SRAM */ +#define CFG_ENV_SIZE (16<<10) /* use 16 kB */ +#endif /* CFG_ENV_IS_IN_NVRAM */ + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */ +#define CFG_ENV_SIZE 1536 /* Use remaining space */ +#endif /* CFG_ENV_IS_IN_EEPROM */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + * +0x0004 + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * +0x0000 => 0x80600800 + */ +#define CFG_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \ + SIUMCR_DBGC11 | SIUMCR_MLRC10) + +/*----------------------------------------------------------------------- + * Clock Setting - get clock frequency from Board Revision Register + *----------------------------------------------------------------------- + */ +#ifndef __ASSEMBLY__ +extern unsigned long ip860_get_clk_freq (void); +#endif +#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq() + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + * +0x0200 => 0x00C2 + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + * +0x0240 => 0x0082 + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit, set PLL multiplication factor ! + */ +/* +0x0286 => was: 0x0000D000 */ +#define CFG_PLPRCR \ + ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ + /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ + PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ + ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ + SCCR_RTDIV | SCCR_RTSEL | \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + SCCR_EBDF00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | \ + SCCR_DFNH000) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/* +0x0220 => 0x00C3 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +/* +0x09C4 => TIMEP=1 */ +#define CFG_RCCR 0x0100 + +/*----------------------------------------------------------------------- + * RMDS - RISC Microcode Development Support Control Register + *----------------------------------------------------------------------- + */ +#define CFG_RMDS 0 + +/*----------------------------------------------------------------------- + * DER - Debug Event Register + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + */ + +/* + * MAMR settings for SDRAM - 16-14 + * => 0xC3804114 + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 0xC3 + +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* + * BR1 and OR1 (FLASH) + */ +#define FLASH_BASE 0x10000000 /* FLASH bank #0 */ + +/* used to re-map FLASH + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +/* allow for max 8 MB of Flash */ +#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ + +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +/* 16 bit, bank valid */ +#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) + +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM CFG_BR0_PRELIM + +/* + * BR2/OR2 - SDRAM + */ +#define SDRAM_BASE 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ +#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ + +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ + +#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CFG_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * BR3/OR3 - SRAM (16 bit) + */ +#define SRAM_BASE 0x20000000 +#define CFG_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */ +#define CFG_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) +#define SRAM_SIZE (1 + (~(CFG_OR3 & BR_BA_MSK))) +#define CFG_OR3_PRELIM CFG_OR3 /* Make sure to map early */ +#define CFG_BR3_PRELIM CFG_BR3 /* in case it's used for ENV */ + +/* + * BR4/OR4 - Board Control & Status (8 bit) + */ +#define BCSR_BASE 0xFC000000 +#define CFG_OR4 0xFFFF0120 /* BI (internal) */ +#define CFG_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) + +/* + * BR5/OR5 - IP Slot A/B (16 bit) + */ +#define IP_SLOT_BASE 0x40000000 +#define CFG_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */ +#define CFG_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) + +/* + * BR6/OR6 - VME STD (16 bit) + */ +#define VME_STD_BASE 0xFE000000 +#define CFG_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */ +#define CFG_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) + +/* + * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit) + */ +#define VME_SHORT_BASE 0xFF000000 +#define CFG_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */ +#define CFG_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) + +/*----------------------------------------------------------------------- + * Board Control and Status Region: + *----------------------------------------------------------------------- + */ +#ifndef __ASSEMBLY__ +typedef struct ip860_bcsr_s { + unsigned char shmem_addr; /* +00 shared memory address register */ + unsigned char reserved0; + unsigned char mbox_addr; /* +02 mailbox address register */ + unsigned char reserved1; + unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */ + unsigned char reserved2; + unsigned char vme_int_pend; /* +06 VME interrupt pending register */ + unsigned char reserved3; + unsigned char bd_int_mask; /* +08 board interrupt mask register */ + unsigned char reserved4; + unsigned char bd_int_pend; /* +0A board interrupt pending register */ + unsigned char reserved5; + unsigned char bd_ctrl; /* +0C board control register */ + unsigned char reserved6; + unsigned char bd_status; /* +0E board status register */ + unsigned char reserved7; + unsigned char vme_irq; /* +10 VME interrupt request register */ + unsigned char reserved8; + unsigned char vme_ivec; /* +12 VME interrupt vector register */ + unsigned char reserved9; + unsigned char cli_mbox; /* +14 clear mailbox irq */ + unsigned char reservedA; + unsigned char rtc; /* +16 RTC control register */ + unsigned char reservedB; + unsigned char mbox_data; /* +18 mailbox read/write register */ + unsigned char reservedC; + unsigned char wd_trigger; /* +1A Watchdog trigger register */ + unsigned char reservedD; + unsigned char rmw_req; /* +1C RMW request register */ + unsigned char reservedE; + unsigned char bd_rev; /* +1E Board Revision register */ +} ip860_bcsr_t; +#endif /* __ASSEMBLY__ */ + +/*----------------------------------------------------------------------- + * Board Control Register: bd_ctrl (Offset 0x0C) + *----------------------------------------------------------------------- + */ +#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */ +#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */ +#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */ +#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */ + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h new file mode 100644 index 0000000..c1565fc --- /dev/null +++ b/include/configs/IPHASE4539.h @@ -0,0 +1,356 @@ +/* + * (C) Copyright 2002 Wolfgang Grandegger + * + * This file is based on similar values for other boards found in + * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG /* General debug */ + +/*----------------------------------------------------------------------- + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */ + +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/*----------------------------------------------------------------------- + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +/*----------------------------------------------------------------------- + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 3 /* which channel for ether */ + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) + +/*----------------------------------------------------------------------- + * - Rx-CLK is CLK14 + * - Tx-CLK is CLK16 + * - Select bus for bd/buffers (see 28-13) + * - Half duplex + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + +/* other options */ + +#define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#define CONFIG_BAUDRATE 19200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +/* + * select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#ifdef CONFIG_SOFT_I2C +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CONFIG_COMMANDS CONFIG_CMD_DFL + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/ram rw" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */ + /* for versions < 2.4.5-pre5 */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0x04400000 + +#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */ + +/*----------------------------------------------------------------------- + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration (Setup by the + * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF800000 + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */ +#define CFG_MAX_FLASH_SIZE (CFG_MAX_FLASH_SECT * 0x10000) /* 4 MB */ + +#define CFG_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* Environment in FLASH, there is little space left in Serial EEPROM */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x10000) /* 2. sector */ + + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\ + ( HRCW_L2CPC10 | HRCW_ISB110 ) |\ + ( HRCW_MMR11 | HRCW_APPC10 ) |\ + ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ + ) /* 0x14863245 */ + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 /* We keep original value */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ + HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR 0xA01C0000 + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR 0X4205C000 + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined (CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + *----------------------------------------------------------------------- + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR 0 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/*----------------------------------------------------------------------- + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 64 bit FLASH + * 1 60x SDRAM 64 bit SDRAM + */ + +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801) +#define CFG_OR0_PRELIM 0xFF800882 +#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041) +#define CFG_OR1_PRELIM 0xF8002CD0 + +#define CFG_PSDMR 0x404A241A +#define CFG_MPTPR 0x00007400 +#define CFG_PSRT 0x00000007 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h new file mode 100644 index 0000000..65056a2 --- /dev/null +++ b/include/configs/ISPAN.h @@ -0,0 +1,347 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen + * + * Support for Interphase iSPAN Communications Controllers + * (453x and others). Tested on 4532. + * + * Derived from iSPAN 4539 port (iphase4539) by + * Wolfgang Grandegger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC8260 /* This is an MPC8260 CPU */ +#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/*----------------------------------------------------------------------- + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * If CONFIG_CONS_NONE is defined, then the serial console routines must be + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* Define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */ +#undef CONFIG_CONS_NONE /* Define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */ + +/*----------------------------------------------------------------------- + * Select Ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC). + * + * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must + * be defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */ +#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */ +#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */ +#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */ + +#ifdef CONFIG_ETHER_ON_FCC + +#if CONFIG_ETHER_INDEX == 3 + +#define CFG_PHY_ADDR 0 +#define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) +#define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) + +#endif /* CONFIG_ETHER_INDEX == 3 */ + +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */ +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 3 /* Port D */ + +#define CFG_MDIO_PIN 0x00040000 /* PD13 */ +#define CFG_MDC_PIN 0x00080000 /* PD12 */ + +#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) +#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) +#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ + else iop->pdat &= ~CFG_MDIO_PIN + +#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ + else iop->pdat &= ~CFG_MDC_PIN + +#define MIIDELAY udelay(1) + +#endif /* CONFIG_ETHER_ON_FCC */ + +#define CONFIG_8260_CLKIN 65536000 /* in Hz */ +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_REGINFO \ + ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS */ +#include + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/ram rw" + +#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* #undef to save memory */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* Default load address */ + +#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0x09900000 + +#define CONFIG_MISC_INIT_R /* We need misc_init_r() */ + +/*----------------------------------------------------------------------- + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#else +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ +#endif /* CONFIG_BZIP2 */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_MAX_FLASH_BANKS 1 /* Max num of memory banks */ +#define CFG_MAX_FLASH_SECT 142 /* Max num of sects on one chip */ + +/* Environment is in flash, there is little space left in Serial EEPROM */ +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * If you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +/* 0x1686B245 */ +#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\ + HRCW_L2CPC10 | HRCW_ISB110 |\ + HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\ + HRCW_CS10PC01 | HRCW_MODCK_H0101 \ + ) +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0F00000 +#ifdef CFG_REV_B +#define CFG_DEFAULT_IMMR 0xFF000000 +#endif /* CFG_REV_B */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ + HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR 0xA01C0000 + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR 0x42250000/* 0x4205C000 */ + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined (CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + *----------------------------------------------------------------------- + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR SCCR_DFBRG01 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/*----------------------------------------------------------------------- + * Init Memory Controller: + * + * Bank Bus Machine PortSize Device + * ---- --- ------- ----------------------------- ------ + * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash + * 1 60x SDRAM 64 bit SDRAM + * 2 Local SDRAM 32 bit SDRAM + */ +#define CFG_USE_FIRMWARE /* If defined - do not initialise memory + controller, rely on initialisation + performed by the Interphase boot firmware. + */ + +#define CFG_OR0_PRELIM 0xFE000882 +#ifdef CFG_REV_B +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_8 | BRx_V) +#else /* Rev. D */ +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_16 | BRx_V) +#endif /* CFG_REV_B */ + +#define CFG_MPTPR 0x7F00 + +/* Please note that 60x SDRAM MUST start at 0 */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_60x_BR 0x00000041 +#define CFG_60x_OR 0xF0002CD0 +#define CFG_PSDMR 0x0049929A +#define CFG_PSRT 0x07 + +#define CFG_LSDRAM_BASE 0xF7000000 +#define CFG_LOC_BR 0x00001861 +#define CFG_LOC_OR 0xFF803280 +#define CFG_LSDMR 0x8285A552 +#define CFG_LSRT 0x07 + +#endif /* __CONFIG_H */ diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h new file mode 100644 index 0000000..a0cb1dd --- /dev/null +++ b/include/configs/IVML24.h @@ -0,0 +1,474 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_IVML24 1 /* ...on a IVML24 board */ + +#if defined (CONFIG_IVML24_16M) +# define CONFIG_IDENT_STRING " IVML24" +#elif defined (CONFIG_IVML24_32M) +# define CONFIG_IDENT_STRING " IVML24_128" +#elif defined (CONFIG_IVML24_64M) +# define CONFIG_IDENT_STRING " IVML24_256" +#endif + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_8xx_GCLK_FREQ 50331648 + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ + +#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ + "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ + "nfsaddrs=10.0.0.99:10.0.0.2" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_BOOTP_MASK \ + ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +#define CFG_PB_12V_ENABLE 0x00002000 /* PB 18 */ +#define CFG_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */ +#define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ +#define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ +#define CFG_PB_IDE_MOTOR 0x00020000 /* PB 14 */ + +#define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ +#define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR + +#if defined (CONFIG_IVML24_16M) +# define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#elif defined (CONFIG_IVML24_32M) +# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#elif defined (CONFIG_IVML24_64M) +# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#endif + +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) + +# if defined (CONFIG_IVML24_16M) +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +# elif defined (CONFIG_IVML24_32M) +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWP) +# elif defined (CONFIG_IVML24_64M) +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWP) +# endif + +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +/* EARB, DBGC and DBPC are initialised by the HCW */ +/* => 0x000000C0 */ +#define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit, set PLL multiplication factor ! + */ +/* 0x00B0C0C0 */ +#define CFG_PLPRCR \ + ( (11 << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ + /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ + PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ + ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* 0x01800014 */ +#define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ + SCCR_RTDIV | SCCR_RTSEL | \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + SCCR_EBDF00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | \ + SCCR_DFNH000 | SCCR_DFLCD101 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/* 0x00C3 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +/* TIMEP=2 */ +#define CFG_RCCR 0x0200 + +/*----------------------------------------------------------------------- + * RMDS - RISC Microcode Development Support Control Register + *----------------------------------------------------------------------- + */ +#define CFG_RMDS 0 + +/*----------------------------------------------------------------------- + * + * Interrupt Levels + *----------------------------------------------------------------------- + */ +#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/ +#define CFG_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ + +#define CFG_ATA_BASE_ADDR 0xFE100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#undef CFG_ATA_IDE1_OFFSET /* only one IDE bus available */ + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +/* EPROMs are 512kb */ +#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR) + +#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \ + CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \ + CFG_OR_TIMING_FLASH) +/* 16 bit, bank valid */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* + * BR1/OR1 - ELIC SACCO bank @ 0xFE000000 + * + * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 + */ +#define ELIC_SACCO_BASE 0xFE000000 +#define ELIC_SACCO_OR_AM 0xFFFF8000 +#define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) + +#define CFG_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ + ELIC_SACCO_TIMING) +#define CFG_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR2/OR2 - ELIC EPIC bank @ 0xFE008000 + * + * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 + */ +#define ELIC_EPIC_BASE 0xFE008000 +#define ELIC_EPIC_OR_AM 0xFFFF8000 +#define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) + +#define CFG_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ + ELIC_EPIC_TIMING) +#define CFG_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR3/OR3: SDRAM + * + * Multiplexed addresses, GPL5 output to GPL5_A (don't care) + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ +#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ + +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ + +#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) + +/* + * BR4/OR4 - HDLC Address + * + * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0 + */ +#define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */ +#define HDLC_ADDR_OR_AM 0xFFFF8000 +#define HDLC_ADDR_TIMING OR_SCY_1_CLK + +#define CFG_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING) +#define CFG_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V ) + +/* + * BR5/OR5: SHARC ADSP-2165L + * + * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 + */ +#define SHARC_BASE 0xFE400000 +#define SHARC_OR_AM 0xFFC00000 +#define SHARC_TIMING OR_SCY_0_CLK + +#define CFG_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING ) +#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MBMR_PTB 204 + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ + +#if defined (CONFIG_IVML24_16M) +# define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +#elif defined (CONFIG_IVML24_32M) +# define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +#elif defined (CONFIG_IVML24_64M) +# define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ +#endif + + +/* + * MBMR settings for SDRAM + */ + +#if defined (CONFIG_IVML24_16M) + /* 8 column SDRAM */ +# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) +#elif defined (CONFIG_IVML24_32M) +/* 128 MBit SDRAM */ +# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) +#elif defined (CONFIG_IVML24_64M) +/* 128 MBit SDRAM */ +# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h new file mode 100644 index 0000000..46b4d53 --- /dev/null +++ b/include/configs/IVMS8.h @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */ + +#if defined (CONFIG_IVMS8_16M) +# define CONFIG_IDENT_STRING " IVMS8" +#elif defined (CONFIG_IVMS8_32M) +# define CONFIG_IDENT_STRING " IVMS8_128" +#elif defined (CONFIG_IVMS8_64M) +# define CONFIG_IDENT_STRING " IVMS8_256" +#endif + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_8xx_GCLK_FREQ 50331648 + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ + +#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ + "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ + "nfsaddrs=10.0.0.99:10.0.0.2" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_BOOTP_MASK \ + ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +#define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ +#define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ +#define CFG_PB_IDE_MOTOR 0x00020000 /* PB 14 */ + +#define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ +#define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#if defined (CONFIG_IVMS8_16M) +# define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#elif defined (CONFIG_IVMS8_32M) +# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#elif defined (CONFIG_IVMS8_64M) +# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#endif + +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +# if defined (CONFIG_IVMS8_16M) +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +# elif defined (CONFIG_IVMS8_32M) +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWP) +# elif defined (CONFIG_IVMS8_64M) +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWP) +# endif +#else +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +/* EARB, DBGC and DBPC are initialised by the HCW */ +/* => 0x000000C0 */ +#define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit, set PLL multiplication factor ! + */ +/* 0x00B0C0C0 */ +#define CFG_PLPRCR \ + ( (11 << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ + /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ + PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ + ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* 0x01800014 */ +#define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ + SCCR_RTDIV | SCCR_RTSEL | \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + SCCR_EBDF00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | \ + SCCR_DFNH000 | SCCR_DFLCD101 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/* 0x00C3 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +/* TIMEP=2 */ +#define CFG_RCCR 0x0200 + +/*----------------------------------------------------------------------- + * RMDS - RISC Microcode Development Support Control Register + *----------------------------------------------------------------------- + */ +#define CFG_RMDS 0 + +/*----------------------------------------------------------------------- + * + * Interrupt Levels + *----------------------------------------------------------------------- + */ +#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ + +#define CFG_ATA_BASE_ADDR 0xFE100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#undef CFG_ATA_IDE1_OFFSET /* only one IDE bus available */ + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +/* EPROMs are 512kb */ +#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ + OR_SCY_5_CLK | OR_EHTR) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +/* 16 bit, bank valid */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* + * BR1/OR1 - ELIC SACCO bank @ 0xFE000000 + * + * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 + */ +#define ELIC_SACCO_BASE 0xFE000000 +#define ELIC_SACCO_OR_AM 0xFFFF8000 +#define ELIC_SACCO_TIMING 0x00000F26 + +#define CFG_OR1 (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING) +#define CFG_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR2/OR2 - ELIC EPIC bank @ 0xFE008000 + * + * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 + */ +#define ELIC_EPIC_BASE 0xFE008000 +#define ELIC_EPIC_OR_AM 0xFFFF8000 +#define ELIC_EPIC_TIMING 0x00000F26 + +#define CFG_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING) +#define CFG_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR3/OR3: SDRAM + * + * Multiplexed addresses, GPL5 output to GPL5_A (don't care) + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ +#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ + +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ + +#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) + +/* + * BR4/OR4: not used + */ + +/* + * BR5/OR5: SHARC ADSP-2165L + * + * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 + */ +#define SHARC_BASE 0xFE400000 +#define SHARC_OR_AM 0xFFC00000 +#define SHARC_TIMING 0x00000700 + +#define CFG_OR5 (SHARC_OR_AM | SHARC_TIMING ) +#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MBMR_PTB 204 + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#if defined (CONFIG_IVMS8_16M) + #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +#elif defined (CONFIG_IVMS8_32M) +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ +#elif defined (CONFIG_IVMS8_64M) +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ +#endif + + +/* + * MBMR settings for SDRAM + */ + +#if defined (CONFIG_IVMS8_16M) + /* 8 column SDRAM */ +# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) +#elif defined (CONFIG_IVMS8_32M) +/* 128 MBit SDRAM */ +#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) +#elif defined (CONFIG_IVMS8_64M) +/* 128 MBit SDRAM */ +#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) + +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h new file mode 100644 index 0000000..afba5c6 --- /dev/null +++ b/include/configs/IceCube.h @@ -0,0 +1,356 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_ICECUBE 1 /* ... on IceCube board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CFG_XLB_PIPELINING 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 + +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MPC5100 */ + +#define CONFIG_MII 1 +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* USB */ +#if 1 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + ADD_PCI_CMD | \ + ADD_USB_CMD ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 +#endif +#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT08 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/MPC5200/uImage\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 0x01000000 +#if !defined(CFG_LOWBOOT) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000) +#else /* CFG_LOWBOOT */ +#if defined(CFG_LOWBOOT08) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000) +#endif +#if defined(CFG_LOWBOOT16) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) +#endif +#endif /* CFG_LOWBOOT */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ + +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ + + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + */ +#ifdef CONFIG_MPC5200_DDR +#define CFG_GPS_PORT_CONFIG 0x90000004 +#else +#define CFG_GPS_PORT_CONFIG 0x10000004 +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#ifdef CONFIG_MPC5200_DDR + +#define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE) +#define CFG_BOOTCS_SIZE 0x00800000 +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS1_START CFG_FLASH_BASE +#define CFG_CS1_SIZE 0x00800000 +#define CFG_CS1_CFG 0x00047800 + +#else /* !CONFIG_MPC5200_DDR */ + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#endif /* CONFIG_MPC5200_DDR */ + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#define CONFIG_ATAPI 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/JSE.h b/include/configs/JSE.h new file mode 100644 index 0000000..ccd1f19 --- /dev/null +++ b/include/configs/JSE.h @@ -0,0 +1,304 @@ +/* + * (C) Copyright 2003 Picture Elements, Inc. + * Stephen Williams + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options for the JSE board + * (Theoretically easy to change, but the board is fixed.) + */ + +#define CONFIG_JSE 1 + /* JSE has a PPC405GPr */ +#define CONFIG_405GP 1 + /* ... which is a 4xxx series */ +#define CONFIG_4xx 1 + /* ... with a 33MHz OSC. connected to the SysCLK input */ +#define CONFIG_SYS_CLK_FREQ 33333333 + /* ... with on-chip memory here (4KBytes) */ +#define CFG_OCM_DATA_ADDR 0xF4000000 +#define CFG_OCM_DATA_SIZE 0x00001000 + /* Do not set up locked dcache as init ram. */ +#undef CFG_INIT_DCACHE_CS + + /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ +#define CONFIG_SYSTEMACE 1 +#define CFG_SYSTEMACE_BASE 0xf0000000 +#define CONFIG_DOS_PARTITION 1 + + /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ +#define CFG_TEMP_STACK_OCM 1 + /* ... place INIT RAM in the OCM address */ +# define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR + /* ... give it the whole init ram */ +# define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE + /* ... Shave a bit off the end for global data */ +# define CFG_GBL_DATA_SIZE 128 +# define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + /* ... and place the stack pointer at the top of what's left. */ +# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + /* Enable board_pre_init function */ +#define CONFIG_BOARD_PRE_INIT 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 + /* Disable post-clk setup init function */ +#undef CONFIG_BOARD_POSTCLK_INIT + /* Disable call to post_init_f: late init function. */ +#undef CONFIG_POST + /* Enable DRAM test. */ +#define CFG_DRAM_TEST 1 + /* Enable misc_init_r function. */ +#define CONFIG_MISC_INIT_R 1 + + /* JSE has EEPROM chips that are good for environment. */ +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM 1 +#undef CFG_ENV_IS_NOWHERE + + /* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 + /* After the device address, need one more address byte. */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 + /* The EEPROM is 512 bytes. */ +#define CFG_EEPROM_SIZE 512 + /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + /* Put the environment in the second half. */ +#define CFG_ENV_OFFSET 0x00 +#define CFG_ENV_SIZE 512 + + + /* The JSE connects UART1 to the console tap connector. */ +#define CONFIG_UART1_CONSOLE 1 + /* Set console baudrate to 9600 */ +#define CONFIG_BAUDRATE 9600 + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* + * Configuration related to auto-boot. + * + * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait + * before resorting to autoboot. This value can be overridden by the + * bootdelay environment variable. + * + * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the + * user that an autoboot will happen. + * + * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will + * execute to boot the JSE. This loads the uimage and initrd.img files + * from CompactFlash into memory, then boots them from memory. + * + * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get + * it going on the JSE. + */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw" +#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000" + + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_FLASH | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + /* watchdog disabled */ +#undef CONFIG_WATCHDOG + /* SPD EEPROM (sdram speed config) disabled */ +#undef CONFIG_SPD_EEPROM +#undef SPD_EEPROM_ADDRESS + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * External peripheral base address + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_KEY_REG_BASE_ADDR 0xF0100000 +#define CFG_IR_REG_BASE_ADDR 0xF0200000 +#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h new file mode 100644 index 0000000..7bbceb0 --- /dev/null +++ b/include/configs/KAREF.h @@ -0,0 +1,310 @@ +/* + * (C) Copyright 2004 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference + * design. + ***********************************************************************/ + +/* + * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $ + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ +#undef CFG_DRAM_TEST /* Disable-takes long time!*/ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +#define CONFIG_VERY_BIG_RAM 1 +#define CONFIG_VERSION_VARIABLE + +#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design" + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) +#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000) +#define CFG_OFEM_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08400000) +#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000) +#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) + +/* Here for completeness */ +#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ +#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ +#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C hardware support */ +#undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */ + + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ +#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ +#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ + +#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */ +#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR) + +#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/*----------------------------------------------------------------------- + * Networking + *----------------------------------------------------------------------*/ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ +#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ +#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ +#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ +#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ +#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ +#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ +#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ + + +/*----------------------------------------------------------------------- + * Console/Commands/Parser + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT) + +/* Include NetConsole support */ +#define CONFIG_NETCONSOLE + +/* Include auto complete with tabs */ +#define CONFIG_AUTO_COMPLETE 1 +#define CFG_AUTO_COMPLETE 1 +#define CFG_ALT_MEMTEST 1 /* use real memory test */ + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */ +#define CFG_PROMPT_HUSH_PS2 "> " + + +/*----------------------------------------------------------------------- + * Console Buffer + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) + /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of cmd args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */ + +/*----------------------------------------------------------------------- + * Memory Test + *----------------------------------------------------------------------*/ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Compact Flash (in true IDE mode) + *----------------------------------------------------------------------*/ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ +#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ + +#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride + to get to the correct offset */ +#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ + +/*----------------------------------------------------------------------- + * PCI + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ +#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ +#define CFG_PCI_TARGET_INIT /* let board init pci target*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ +#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ +#endif + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CFG_LOAD_ADDR 0x8000000 /* default load address */ +#define CFG_EXTBDINFO 1 /* use extended board_info */ + +#define CFG_HZ 100 /* decr freq: 1 ms ticks */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h new file mode 100644 index 0000000..9b950fc --- /dev/null +++ b/include/configs/KUP4K.h @@ -0,0 +1,489 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + * Derived from ../tqm8xx/tqm8xx.c + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ +#define CONFIG_KUP4K 1 /* ...on a KUP4K module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ +#endif + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + + +#undef CONFIG_BOOTARGS + + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ + "run addhw; diskboot 200000 0:1; bootm 200000\0" \ +"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \ + "run addhw; diskboot 200000 2:1; bootm 200000\0" \ +"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \ +"panic_boot=echo No Bootdevice !!! reset\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ +"ramargs=setenv bootargs root=/dev/ram rw\0" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ + ":${netmask}:${hostname}:${netdev}:off\0" \ +"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ +"netdev=eth0\0" \ +"contrast=55\0" \ +"silent=1\0" \ +"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ +"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \ + "cp.b 200000 40050000 14000\0" + +#define CONFIG_BOOTCOMMAND \ + "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot" + + +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MISC_INIT_F 1 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_WATCHDOG 1 /* watchdog enabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + + +/* + * enable I2C and select the hardware/software driver + */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + + +/*----------------------------------------------------------------------- + * I2C Configuration + */ + +#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ +#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ + + +/* List of I2C addresses to be verified by POST */ + +#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \ + CFG_I2C_RTC_ADDR, \ + } + + +#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ + +#define CFG_DISCOVER_PHY +#define CONFIG_MII + +#if 0 +#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */ +#endif +#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */ + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#if 1 +/* POST support */ + +#define CONFIG_POST (CFG_POST_CPU | \ + CFG_POST_RTC | \ + CFG_POST_I2C) + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 +#endif +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x000400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } + +#define CFG_CONSOLE_INFO_QUIET 1 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 + +/* Address and size of Redundant Environment Sector */ +#if 0 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#if 1 +#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P' */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +#define CFG_PLPRCR ( (5-1)< ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ +#if defined(CONFIG_80MHz) +#define CFG_MAMR_PTA 156 +#elif defined(CONFIG_66MHz) +#define CFG_MAMR_PTA 129 +#else /* 50 MHz */ +#define CFG_MAMR_PTA 98 +#endif /*CONFIG_??MHz */ + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR 0x400 + +/* + * MAMR settings for SDRAM + */ +#define CFG_MAMR 0x80802114 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#if 0 +#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" +#endif +#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ +#define CONFIG_SILENT_CONSOLE 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h new file mode 100644 index 0000000..cd38b0f --- /dev/null +++ b/include/configs/KUP4X.h @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + * Derived from ../tqm8xx/tqm8xx.c + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ +#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ +#endif + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CFG_8XX_FACT 8 /* Multiply by 8 */ +#define CFG_8XX_XIN 16000000 /* 16 MHz in */ + + +#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) + +/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ +/* in general, we always know this for FADS+new ADS anyway */ +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ + + +#undef CONFIG_BOOTARGS + + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ + "run addhw;diskboot 200000 0:1;bootm 200000\0" \ +"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\ + run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\ + usb stop; bootm 200000\0" \ +"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \ +"panic_boot=echo No Bootdevice !!! reset\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ +"ramargs=setenv bootargs root=/dev/ram rw\0" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ + ":${netmask}:${hostname}:${netdev}:off\0" \ +"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ +"netdev=eth0\0" \ +"silent=1\0" \ +"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \ +"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \ + "cp.b 200000 40040000 14000\0" + +#define CONFIG_BOOTCOMMAND \ + "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot" + + +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MISC_INIT_F 1 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_WATCHDOG 1 /* watchdog enabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* + * enable I2C and select the hardware/software driver + */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + + +/*----------------------------------------------------------------------- + * I2C Configuration + */ + +#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ +#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ + + +/* List of I2C addresses to be verified by POST */ + +#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \ + CFG_I2C_RTC_ADDR, \ + } + + +#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ + +#define CFG_DISCOVER_PHY +#define CONFIG_MII + +#if 0 +#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */ +#endif +#undef CONFIG_KUP4K_LOGO + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + + +#if 1 +/* POST support */ + +#define CONFIG_POST (CFG_POST_CPU | \ + CFG_POST_RTC | \ + CFG_POST_I2C) + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 +#endif +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_SNTP | \ + CFG_CMD_USB ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x000400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */ +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } + +#define CFG_CONSOLE_INFO_QUIET 1 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 + +/* Address and size of Redundant Environment Sector */ +#if 0 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#if 1 +#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P' */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control (15-29) + */ +#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS) + + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ + +/* KUP4K use both slots, SLOT_A as "primary". */ +#define CONFIG_PCMCIA_SLOT_A 1 + +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +#define PCMCIA_SOCKETS_NO 1 +#define PCMCIA_MEM_WIN_NO 8 +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#define CONFIG_IDE_LED 1 /* LED for ide supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 2 + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + + +#define CFG_MPTPR 0x400 + +/* + * MAMR settings for SDRAM + */ +#define CFG_MAMR 0x80802114 + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#if 0 +#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" +#endif +#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ +#define CONFIG_SILENT_CONSOLE 1 + +#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_SL811HS 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h new file mode 100644 index 0000000..e44f1cc --- /dev/null +++ b/include/configs/LANTEC.h @@ -0,0 +1,377 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2001 + * Torsten Stevens, FHG IMS, stevens@ims.fhg.de + * Bruno Achauer, Exet AG, bruno@exet-ag.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + * [derived from config_TQM850L.h] + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */ + +/* + * Port assignments (CONFIG_LANTEC == 1): + * - SMC1: J11 (MDB) ? + * - SMC2: J6 (Feature connector) + * - SCC2: J9 (RJ45) + * - SCC3: J8 (Sub-D9) + * + * Port assignments (CONFIG_LANTEC == 2): TBD + */ + + +#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ +#define CONFIG_8xx_CONS_SCC3 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_CMD_MINIMAL 0 +#define CONFIG_CMD_TINY (CFG_CMD_FLASH | \ + CFG_CMD_MEMORY | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB) +#define CONFIG_CMD_NORMAL (CONFIG_CMD_DFL & ~CFG_CMD_BOOTD & ~CFG_CMD_REISER) +#define CONFIG_CMD_GDB (CONFIG_CMD_NORMAL | CFG_CMD_KGDB) +#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \ + & ~CFG_CMD_BMP \ + & ~CFG_CMD_BSP \ + & ~CFG_CMD_DISPLAY \ + & ~CFG_CMD_DOC \ + & ~CFG_CMD_DTT \ + & ~CFG_CMD_EEPROM \ + & ~CFG_CMD_ELF \ + & ~CFG_CMD_EXT2 \ + & ~CFG_CMD_FDC \ + & ~CFG_CMD_FDOS \ + & ~CFG_CMD_HWFLOW \ + & ~CFG_CMD_I2C \ + & ~CFG_CMD_IDE \ + & ~CFG_CMD_IRQ \ + & ~CFG_CMD_JFFS2 \ + & ~CFG_CMD_KGDB \ + & ~CFG_CMD_MII \ + & ~CFG_CMD_MMC \ + & ~CFG_CMD_NAND \ + & ~CFG_CMD_PCI \ + & ~CFG_CMD_PCMCIA \ + & ~CFG_CMD_REISER \ + & ~CFG_CMD_SCSI \ + & ~CFG_CMD_SPI \ + & ~CFG_CMD_UNIVERSE\ + & ~CFG_CMD_USB \ + & ~CFG_CMD_VFD \ + & ~CFG_CMD_XIMG ) + +#if CONFIG_LANTEC >= 2 +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#endif + +#if CONFIG_LANTEC >= 2 +# define CONFIG_COMMANDS CONFIG_CMD_FULL +#else +# define CONFIG_COMMANDS (CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK) + +/*----------------------------------------------------------------------- + * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX] + *----------------------------------------------------------------------- + */ +#define CONFIG_8xx_GCLK_FREQ 33000000 + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ + /* up to 50 MHz we use a 1:1 clock */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 + /* up to 50 MHz we use a 1:1 clock */ +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/5 and OR0/5 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ + OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR5_REMAP CFG_OR0_REMAP +#define CFG_OR5_PRELIM CFG_OR0_PRELIM +#define CFG_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses */ +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM) + +#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL \ + ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "" +#define MTDPARTS_DEFAULT "" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h new file mode 100644 index 0000000..5fd6a95 --- /dev/null +++ b/include/configs/M5272C3.h @@ -0,0 +1,189 @@ +/* + * Configuation settings for the Motorola MC5272C3 board. + * + * (C) Copyright 2003 Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5272C3_H +#define _M5272C3_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5272 /* define processor type */ + +#define FEC_ENET + +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ + +#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 +#else +#define CFG_ENV_ADDR 0xffe04000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \ + CFG_CMD_MII) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#define CONFIG_BOOTDELAY 5 + +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x20000 + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000 +#define CFG_CLK 66000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ + +#define CFG_SCR 0x0003; +#define CFG_SPR 0xffff; + +#define CFG_DISCOVER_PHY +#define CFG_ENET_BD_BASE 0x380000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_FLASH_BASE 0xffe00000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CFG_MONITOR_BASE 0x20000 +#else +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif + +#define CFG_MONITOR_LEN 0x20000 +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 1000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +#define CFG_BR0_PRELIM 0xFFE00201 +#define CFG_OR0_PRELIM 0xFFE00014 + +#define CFG_BR1_PRELIM 0 +#define CFG_OR1_PRELIM 0 + +#define CFG_BR2_PRELIM 0x30000001 +#define CFG_OR2_PRELIM 0xFFF80000 + +#define CFG_BR3_PRELIM 0 +#define CFG_OR3_PRELIM 0 + +#define CFG_BR4_PRELIM 0 +#define CFG_OR4_PRELIM 0 + +#define CFG_BR5_PRELIM 0 +#define CFG_OR5_PRELIM 0 + +#define CFG_BR6_PRELIM 0 +#define CFG_OR6_PRELIM 0 + +#define CFG_BR7_PRELIM 0x00000701 +#define CFG_OR7_PRELIM 0xFFC0007C + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_PACNT 0x00000000 +#define CFG_PADDR 0x0000 +#define CFG_PADAT 0x0000 +#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CFG_PBDDR 0x0000 +#define CFG_PBDAT 0x0000 +#define CFG_PDCNT 0x00000000 + +#endif /* _M5272C3_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h new file mode 100644 index 0000000..cbb3e3b --- /dev/null +++ b/include/configs/M5282EVB.h @@ -0,0 +1,151 @@ +/* + * Configuation settings for the Motorola MC5282EVB board. + * + * (C) Copyright 2003 Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _CONFIG_M5282EVB_H +#define _CONFIG_M5282EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5282 /* define processor type */ + +#define FEC_ENET + +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_ADDR 0xffe04000 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 + + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#define CONFIG_BOOTDELAY 5 + +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x20000 + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000000 +#define CFG_CLK 64000000 + + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +#define CFG_MBAR 0x40000000 + +#undef CFG_DISCOVER_PHY +#define CFG_ENET_BD_BASE 0x380000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_FLASH_BASE 0xffe00000 +#define CFG_INT_FLASH_BASE 0xf0000000 + +/* If M5282 port is fully implemented the monitor base will be behind + * the vector table. */ +/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */ +#define CFG_MONITOR_BASE 0x20000 + +#define CFG_MONITOR_LEN 0x20000 +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_BOOTPARAMS_LEN 64*1024 + + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_SECT 35 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_ERASE_TOUT 10000000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ + + +/*----------------------------------------------------------------------- + * Port configuration + */ + + +#endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/MBX.h b/include/configs/MBX.h new file mode 100644 index 0000000..d6e3fb8 --- /dev/null +++ b/include/configs/MBX.h @@ -0,0 +1,307 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the MBX8xx board. + * + * ----------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Changed 2002-10-01 + * Added PCMCIA defines mostly taken from other U-Boot boards that + * have PCMCIA already working. If you find any bugs, incorrect assumptions + * feel free to fix them yourself and submit a patch. + * Rod Boyce + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Physical memory map as defined by the MBX PGM + */ +#define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ +#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */ +#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ +#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */ +#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ +#define CFG_PCIMEM_OR 0xA0000108 +#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ +#define CFG_PCIBRIDGE_OR 0xFFFF0108 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ +#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) +#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) + +/*----------------------------------------------------------------------- + * Offset in DPMEM where we keep the VPD data + */ +#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xfe000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#endif +#undef CFG_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * NVRAM Configuration + * + * Note: the MBX is special because there is already a firmware on this + * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we + * access the NVRAM at the offset 0x1000. + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ +#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000) +#define CFG_ENV_SIZE 0x1000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +/* #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) +#define CFG_SCCR SCCR_TBS + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6 + +#define CONFIG_PCMCIA_SLOT_A 1 + + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * Debug Entry Mode + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h new file mode 100644 index 0000000..0ca0970 --- /dev/null +++ b/include/configs/MBX860T.h @@ -0,0 +1,407 @@ + /* + * A collection of structures, addresses, and values associated with + * the Motorola 860T MBX board. + * Copied from the FADS stuff, which was originally copied from the MBX stuff! + * Magnus Damm added defines for 8xxrom and extended bd_info. + * Helmut Buchsbaum added bitvalues for BCSRx + * Rob Taylor coverted it back to MBX + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#include + +#define CONFIG_MPC860 1 +#define CONFIG_MPC860T 1 +#define CONFIG_MBX 1 + +#define CONFIG_8xx_CPUCLOCK 40 +#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK) +#define TARGET_SYSTEM_FREQUENCY 40 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#define CONFIG_BAUDRATE 9600 + +#define MPC8XX_FACT 10 /* Multiply by 10 */ +#define MPC8XX_XIN 40000000 /* 50 MHz in */ +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#if 1 +#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */ +#define CONFIG_8xx_TFTP_MODE +#else +#define CONFIG_8xx_BOOTDELAY 5 /* autoboot after 5 seconds */ +#undef CONFIG_8xx_TFTP_MODE +#endif + +#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */ +#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ +#define CONFIG_BOOTARGS " " +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT ":>" /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFA00000 +#define CFG_IMMR_SIZE ((uint)(64 * 1024)) +#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */ +#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ +#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */ +#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ +#define CFG_PCIMEM_OR 0xA0000108 +#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ +#define CFG_PCIBRIDGE_OR 0xFFFF0108 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ +#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) +#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) + +/*----------------------------------------------------------------------- + * Offset in DPMEM where we keep the VPD data + */ +#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x00000000 +/*0xFE000000*/ +#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN) +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * NVRAM Configuration + * + * Note: the MBX is special because there is already a firmware on this + * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we + * access the NVRAM at the offset 0x1000. + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ +#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000) +#define CFG_ENV_SIZE 0x1000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) +#define CFG_SCCR SCCR_TBS + + /*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the +* entire address space, we have to set the memory controller +* differently. Normally, you write the option register +* first, and then enable the chip select by writing the +* base register. For CS0, you must write the base register +* first, followed by the option register. +*/ + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ +/* the other CS:s are determined by looking at parameters in BCSRx */ + + +#define BCSR_ADDR ((uint) 0xFF010000) +#define BCSR_SIZE ((uint)(64 * 1024)) + +#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */ + +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */ + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ +#define CFG_BR0_PRELIM (0xFE000000 | BR_V ) + +/* BCSRx - Board Control and Status Registers */ +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4 +#define CFG_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V ) + + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +#define CFG_MAMR 0x13821000 +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* values according to the manual */ + + +#define PCMCIA_MEM_ADDR ((uint)0xff020000) +#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) + +#define BCSR0 ((uint) (BCSR_ADDR + 00)) +#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) +#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) +#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) +#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) + +/* FADS bitvalues by Helmut Buchsbaum + * see MPC8xxADS User's Manual for a proper description + * of the following structures + */ + +#define BCSR0_ERB ((uint)0x80000000) +#define BCSR0_IP ((uint)0x40000000) +#define BCSR0_BDIS ((uint)0x10000000) +#define BCSR0_BPS_MASK ((uint)0x0C000000) +#define BCSR0_ISB_MASK ((uint)0x01800000) +#define BCSR0_DBGC_MASK ((uint)0x00600000) +#define BCSR0_DBPC_MASK ((uint)0x00180000) +#define BCSR0_EBDF_MASK ((uint)0x00060000) + +#define BCSR1_FLASH_EN ((uint)0x80000000) +#define BCSR1_DRAM_EN ((uint)0x40000000) +#define BCSR1_ETHEN ((uint)0x20000000) +#define BCSR1_IRDEN ((uint)0x10000000) +#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) +#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) +#define BCSR1_BCSR_EN ((uint)0x02000000) +#define BCSR1_RS232EN_1 ((uint)0x01000000) +#define BCSR1_PCCEN ((uint)0x00800000) +#define BCSR1_PCCVCC0 ((uint)0x00400000) +#define BCSR1_PCCVPP_MASK ((uint)0x00300000) +#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) +#define BCSR1_RS232EN_2 ((uint)0x00040000) +#define BCSR1_SDRAM_EN ((uint)0x00020000) +#define BCSR1_PCCVCC1 ((uint)0x00010000) + +#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) +#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) +#define BCSR2_DRAM_PD_SHIFT (23) +#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) +#define BCSR2_DBREVNR_MASK ((uint)0x00030000) + +#define BCSR3_DBID_MASK ((ushort)0x3800) +#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) +#define BCSR3_BREVNR0 ((ushort)0x0080) +#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) +#define BCSR3_BREVN1 ((ushort)0x0008) +#define BCSR3_BREVN2_MASK ((ushort)0x0003) + +#define BCSR4_ETHLOOP ((uint)0x80000000) +#define BCSR4_TFPLDL ((uint)0x40000000) +#define BCSR4_TPSQEL ((uint)0x20000000) +#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) +#ifdef CONFIG_MPC823 +#define BCSR4_USB_EN ((uint)0x08000000) +#endif /* CONFIG_MPC823 */ +#ifdef CONFIG_MPC860SAR +#define BCSR4_UTOPIA_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860SAR */ +#ifdef CONFIG_MPC860T +#define BCSR4_FETH_EN ((uint)0x08000000) +#endif /* CONFIG_MPC860T */ +#define BCSR4_USB_SPEED ((uint)0x04000000) +#define BCSR4_VCCO ((uint)0x02000000) +#define BCSR4_VIDEO_ON ((uint)0x00800000) +#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) +#define BCSR4_VIDEO_RST ((uint)0x00200000) +#define BCSR4_MODEM_EN ((uint)0x00100000) +#define BCSR4_DATA_VOICE ((uint)0x00080000) + +#define CONFIG_DRAM_40MHZ 1 + +#ifdef CONFIG_MPC860T + +/* Interrupt level assignments. +*/ +#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ + +#endif /* CONFIG_MPC860T */ + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + +/* + * MPC8xx CPM Options + */ +#define CONFIG_SCC_ENET 1 +#define CONFIG_SCC1_ENET 1 +#define CONFIG_FEC_ENET 1 +#undef CONFIG_CPM_IIC +#undef CONFIG_UCODE_PATCH + + +#define CONFIG_DISK_SPINUP_TIME 1000000 + + +/* PCMCIA configuration */ + +#define PCMCIA_MAX_SLOTS 2 + +#ifdef CONFIG_MPC860 +#define PCMCIA_SLOT_A 1 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h new file mode 100644 index 0000000..b965571 --- /dev/null +++ b/include/configs/METROBOX.h @@ -0,0 +1,378 @@ +/* + * (C) Copyright 2004 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * METROBOX.h - configuration Sandburst MetroBox + ***********************************************************************/ + +/* + * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $ + * + * + * $Log: METROBOX.h,v $ + * Revision 1.21 2005/06/03 15:05:25 tsawyer + * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB + * + * Revision 1.20 2005/04/11 20:51:11 tsawyer + * fix ethernet + * + * Revision 1.19 2005/04/06 15:13:36 tsawyer + * Update appropriate files to coincide with u-boot 1.1.3 + * + * Revision 1.18 2005/03/10 14:16:02 tsawyer + * add def'n for cis8201 short etch option. + * + * Revision 1.17 2005/03/09 19:49:51 tsawyer + * Remove KGDB to allow use of 2nd serial port + * + * Revision 1.16 2004/12/02 19:00:23 tsawyer + * Add misc_init_f to turn on i2c-1 and all four fans before sdram init + * + * Revision 1.15 2004/09/15 18:04:12 tsawyer + * add multiple serial port support + * + * Revision 1.14 2004/09/03 15:27:51 tsawyer + * All metrobox boards are at 66.66 sys clock + * + * Revision 1.13 2004/08/05 20:27:46 tsawyer + * Remove system ace definitions, add net console support + * + * Revision 1.12 2004/07/29 20:00:13 tsawyer + * Add i2c bus 1 + * + * Revision 1.11 2004/07/21 13:44:18 tsawyer + * SystemACE is out, CF direct to local bus is in + * + * Revision 1.10 2004/06/29 19:08:55 tsawyer + * Add CONFIG_MISC_INIT_R + * + * Revision 1.9 2004/06/28 21:30:53 tsawyer + * Fix default BOOTARGS + * + * Revision 1.8 2004/06/17 15:51:08 tsawyer + * auto complete + * + * Revision 1.7 2004/06/17 15:08:49 tsawyer + * Add autocomplete + * + * Revision 1.6 2004/06/15 12:33:57 tsawyer + * debugging checkpoint + * + * Revision 1.5 2004/06/12 19:48:28 tsawyer + * Debugging checkpoint + * + * Revision 1.4 2004/06/02 13:03:06 tsawyer + * Fix eth addrs + * + * Revision 1.3 2004/05/18 19:56:10 tsawyer + * Change default bootcommand to pImage.metrobox + * + * Revision 1.2 2004/05/18 14:13:44 tsawyer + * Add bringup values for bootargs and bootcommand. + * Remove definition of ipaddress and serverip addresses. + * + * Revision 1.1 2004/04/16 15:08:54 tsawyer + * Initial Revision + * + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_METROBOX 1 /* Board is Metrobox */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ +#undef CFG_DRAM_TEST /* Disable-takes long time!*/ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +#define CONFIG_VERY_BIG_RAM 1 +#define CONFIG_VERSION_VARIABLE + +#define CONFIG_IDENT_STRING " Sandburst Metrobox" + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000) +#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000) +#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ +#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ +#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C hardware support */ +#undef CONFIG_SOFT_I2C /* I2C !bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */ + + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ +#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ +#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ + +#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */ +#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR) + +#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none " +#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000" +#define CONFIG_BOOTDELAY 5 /* disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/*----------------------------------------------------------------------- + * Networking + *----------------------------------------------------------------------*/ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ +#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ +#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ +#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ +#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ +#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ +#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ +#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ + + +/*----------------------------------------------------------------------- + * Console/Commands/Parser + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT) + +/* tbs 09-March-2005 Removed to be able to use 2nd serial */ +/* CFG_CMD_KGDB | \ */ + + +/* Include NetConsole support */ +#define CONFIG_NETCONSOLE + +/* Include auto complete with tabs */ +#define CONFIG_AUTO_COMPLETE 1 +#define CFG_AUTO_COMPLETE 1 +#define CFG_ALT_MEMTEST 1 /* use real memory test */ + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */ +#define CFG_PROMPT_HUSH_PS2 "> " + + +/*----------------------------------------------------------------------- + * Console Buffer + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) + /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of cmd args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */ + +/*----------------------------------------------------------------------- + * Memory Test + *----------------------------------------------------------------------*/ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Compact Flash (in true IDE mode) + *----------------------------------------------------------------------*/ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ +#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ + +#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride + to get to the correct offset */ +#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ + +/*----------------------------------------------------------------------- + * PCI + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ +#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ +#define CFG_PCI_TARGET_INIT /* let board init pci target*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ +#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ +#endif + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CFG_LOAD_ADDR 0x8000000 /* default load address */ +#define CFG_EXTBDINFO 1 /* use extended board_info */ + +#define CFG_HZ 100 /* decr freq: 1 ms ticks */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h new file mode 100644 index 0000000..53684ca --- /dev/null +++ b/include/configs/MHPC.h @@ -0,0 +1,386 @@ +/* + * (C) Copyright 2001 + * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Configuation settings for the miniHiPerCam. + * + * ----------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_MHPC 1 /* on a miniHiPerCam */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */ +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED +#undef CONFIG_8xx_CONS_SMC1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ETHADDR 00:00:5b:ee:de:ad + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#undef CONFIG_UCODE_PATCH + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE) +#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */ +#define LCD_VIDEO_COLS 640 +#define LCD_VIDEO_ROWS 480 +#define LCD_VIDEO_FG 255 +#define LCD_VIDEO_BG 0 + +#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */ +#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */ +#define CONFIG_VIDEO_LOGO + +#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */ +#define VIDEO_TSTC_FCT serial_tstc +#define VIDEO_GETC_FCT serial_getc + +#define CONFIG_BR0_WORKAROUND 1 + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_REGINFO ) + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x300000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Physical memory map + */ +#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xfe000000 + +#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ +#undef CFG_MONITOR_BASE /* to run U-Boot from RAM */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=mhpc-0" +#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)" +*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET CFG_MONITOR_LEN /* Offset of Environment */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_SEME) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 12-18 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define MPC8XX_SPEED 50000000L +#define MPC8XX_XIN 5000000L /* ref clk */ +#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) +#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ + +#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */ +#define CFG_SCCR (SCCR_TBS | SCCR_DFLCD001) + + +/*----------------------------------------------------------------------- + * MAMR settings for SDRAM - 16-14 + * => 0xC080200F + *----------------------------------------------------------------------- + * periodic timer for refresh + */ +#define CFG_MAMR_PTA 0xC0 +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK) + +/* + * BR0 and OR0 (FLASH) used to re-map FLASH + */ + +/* allow for max 8 MB of Flash */ +#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/ +#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/ +#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ + +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/ + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V ) + +/* + * BR1 and OR1 (SDRAM) + */ +#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ +#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */ + +/* SDRAM timing: drive GPL5 high on first cycle */ +#define CFG_OR_TIMING_SDRAM (OR_G5LS) + +#define CFG_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM ) +#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * BR2/OR2 - DIMM + */ +#define CFG_OR2 (OR_ACS_DIV4) +#define CFG_BR2 (BR_MS_UPMA) + +/* + * BR3/OR3 - DIMM + */ +#define CFG_OR3 (OR_ACS_DIV4) +#define CFG_BR3 (BR_MS_UPMA) + +/* + * BR4/OR4 + */ +#define CFG_OR4 0 +#define CFG_BR4 0 + +/* + * BR5/OR5 + */ +#define CFG_OR5 0 +#define CFG_BR5 0 + +/* + * BR6/OR6 + */ +#define CFG_OR6 0 +#define CFG_BR6 0 + +/* + * BR7/OR7 + */ +#define CFG_OR7 0 +#define CFG_BR7 0 + + +/*----------------------------------------------------------------------- + * Debug Entry Mode + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h new file mode 100644 index 0000000..db2147b --- /dev/null +++ b/include/configs/MIP405.h @@ -0,0 +1,456 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*********************************************************** + * High Level Configuration Options + * (easy to change) + ***********************************************************/ +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_MIP405 1 /* ...on a MIP405 board */ +/*********************************************************** + * Note that it may also be a MIP405T board which is a subset of the + * MIP405 + ***********************************************************/ +/*********************************************************** + * WARNING: + * CONFIG_BOOT_PCI is only used for first boot-up and should + * NOT be enabled for production bootloader + ***********************************************************/ +/*#define CONFIG_BOOT_PCI 1*/ +/*********************************************************** + * Clock + ***********************************************************/ +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +/*********************************************************** + * Command definitions + ***********************************************************/ +#define MIP405_COMMON_CMDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SAVES | \ + CFG_CMD_BSP ) + +#if defined(CONFIG_MIP405T) +#define CONFIG_COMMANDS \ + MIP405_COMMON_CMDS +#else +#define CONFIG_COMMANDS \ + (MIP405_COMMON_CMDS | \ + CFG_CMD_USB | \ + CFG_CMD_DOC ) + +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +/************************************************************** + * I2C Stuff: + * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address + * 0x53. + * The Atmel EEPROM uses 16Bit addressing. + ***************************************************************/ + +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#undef CFG_I2C_EEPROM_ADDR_OVERFLOW +#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ + /* 64 byte page write mode using*/ + /* last 6 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ + +/*************************************************************** + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + ***************************************************************/ +/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 +#define SDRAM_EEPROM_READ_ADDRESS 0xA1 +*/ +/************************************************************** + * Environment definitions + **************************************************************/ +#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ +#define CONFIG_BOOTDELAY 5 +/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ +/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ + +#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ +#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ + +#define CONFIG_IPADDR 10.0.0.100 +#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_PREBOOT +/*************************************************************** + * defines if the console is stored in the environment + ***************************************************************/ +#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ +/*************************************************************** + * defines if an overwrite_console function exists + *************************************************************/ +#define CFG_CONSOLE_OVERWRITE_ROUTINE +#define CFG_CONSOLE_INFO_QUIET +/*************************************************************** + * defines if the overwrite_console should be stored in the + * environment + **************************************************************/ +#undef CFG_CONSOLE_ENV_OVERWRITE + +/************************************************************** + * loads config + *************************************************************/ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MISC_INIT_R +/*********************************************************** + * Miscellaneous configurable options + **********************************************************/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_BASE_BAUD 916667 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ + /* resource configuration */ +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=mip405-0" +#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" +*/ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * Logbuffer Configuration + */ +#undef CONFIG_LOGBUFFER /* supported but not enabled */ +/*----------------------------------------------------------------------- + * Bootcountlimit Configuration + */ +#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ + +/*----------------------------------------------------------------------- + * POST Configuration + */ +#if 0 /* enable this if POST is desired (is supported but not enabled) */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_RTC | \ + CFG_POST_I2C) + +#endif +/* + * Init Memory Controller: + */ +#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ +#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* Peripheral Bus Mapping */ +#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ +#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ +#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ + +#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 +#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in On Chip SRAM) + */ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR 0xF0000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +/* reserve some memory for POST and BOOT limit info */ +#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 32) + +#ifdef CONFIG_POST /* reserve one word for POST Info */ +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +#endif + +#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ +#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12) +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*********************************************************************** + * External peripheral base address + ***********************************************************************/ +#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 + +/*********************************************************************** + * Last Stage Init + ***********************************************************************/ +#define CONFIG_LAST_STAGE_INIT +/************************************************************ + * Ethernet Stuff + ***********************************************************/ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ +#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ +/************************************************************ + * RTC + ***********************************************************/ +#define CONFIG_RTC_MC146818 +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/************************************************************ + * IDE/ATA stuff + ************************************************************/ +#if defined(CONFIG_MIP405T) +#define CFG_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ +#else +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#endif + +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */ +#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ +#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ + +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET /* reset for ide supported... */ +#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ +#define CONFIG_SUPPORT_VFAT +/************************************************************ + * ATAPI support (experimental) + ************************************************************/ +#define CONFIG_ATAPI /* enable ATAPI Support */ + +/************************************************************ + * DISK Partition support + ************************************************************/ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */ + +/************************************************************ + * Disk-On-Chip configuration + ************************************************************/ +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ +#define CFG_DOC_SHORT_TIMEOUT +#define CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM +/************************************************************ + * Keyboard support + ************************************************************/ +#undef CONFIG_ISA_KEYBOARD + +/************************************************************ + * Video support + ************************************************************/ +#define CONFIG_VIDEO /*To enable video controller support */ +#define CONFIG_VIDEO_CT69000 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_SW_CURSOR +#undef CONFIG_VIDEO_ONBOARD +/************************************************************ + * USB support EXPERIMENTAL + ************************************************************/ +#if !defined(CONFIG_MIP405T) +#define CONFIG_USB_UHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE + +/* Enable needed helper functions */ +#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ +#endif +/************************************************************ + * Debug support + ************************************************************/ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/************************************************************ + * support BZIP2 compression + ************************************************************/ +#define CONFIG_BZIP2 1 + +/************************************************************ + * Ident + ************************************************************/ + +#define VERSION_TAG "released" +#if !defined(CONFIG_MIP405T) +#define CONFIG_ISO_STRING "MEV-10072-001" +#else +#define CONFIG_ISO_STRING "MEV-10082-001" +#endif + +#if !defined(CONFIG_BOOT_PCI) +#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG +#else +#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version" +#endif + + +#endif /* __CONFIG_H */ diff --git a/include/configs/ML2.h b/include/configs/ML2.h new file mode 100644 index 0000000..d8805ea --- /dev/null +++ b/include/configs/ML2.h @@ -0,0 +1,262 @@ +/* + * ML2.h: ML2 specific config options + * + * Copyright 2002 Mind NV + * + * http://www.mind.be/ + * + * Author : Peter De Schrijver (p2@mind.be) + * + * Derived from : other configuration header files in this tree + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire + * program is licensed under the GPL. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_ML2 1 /* ...on a ML2 board */ + + +#define CFG_ENV_IS_IN_FLASH 1 + +#ifdef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#else +#ifdef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM +#endif +#endif + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#if 1 +#define CONFIG_BOOTCOMMAND "bootm" /* autoboot command */ +#else +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ +#endif + +#define CONFIG_PREBOOT "fsload 0x00100000 /boot/image" + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#if 0 +#define CONFIG_SERIAL_SOFTWARE_FIFO 4000 +#else +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#endif + +#if 0 +#define CONFIG_BOOTARGS "root=/dev/nfs " \ + "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ + "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" +#else +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 " \ + "console=ttyS0 console=tty" + +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & \ + ~( CFG_CMD_NET | \ + CFG_CMD_RTC | \ + CFG_CMD_PCI | \ + CFG_CMD_I2C \ + ) ) | \ + CFG_CMD_IRQ | \ + CFG_CMD_KGDB | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF | \ + CFG_CMD_JFFS2 ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SYS_CLK_FREQ 50000000 + +#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ + +#define CFG_BASE_BAUD (3125000*16) +#define CFG_NS16550_CLK CFG_BASE_BAUD +#define CFG_DUART_CHAN 0 +#define CFG_NS16550_COM1 0xa0001003 +#define CFG_NS16550_COM2 0xa0011003 +#define CFG_NS16550_REG_SIZE -4 +#define CFG_NS16550 1 +#define CFG_INIT_CHAN1 1 +#define CFG_INIT_CHAN2 1 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x18000000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* BEG ENVIRONNEMENT FLASH */ +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ +#endif +/* END ENVIRONNEMENT FLASH */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +#define CFG_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00080000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=ml2-0" +#define MTDPARTS_DEFAULT "mtdparts=ml2-0:-@512k(jffs2)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h new file mode 100644 index 0000000..6ad2feb --- /dev/null +++ b/include/configs/MOUSSE.h @@ -0,0 +1,329 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * James F. Dougherty (jfd@cs.stanford.edu) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the MOUSSE board. + * See also: http://www.vooha.com/ + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8240 1 +#define CONFIG_MOUSSE 1 +#define CFG_ADDR_MAP_B 1 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#if 1 +#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */ +#else +#define CONFIG_BOOTCOMMAND "bootm ffe10000" +#endif +#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138" +#define CONFIG_BOOTDELAY 3 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL|CFG_CMD_ASKENV|CFG_CMD_DATE) +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ETH_ADDR "00:10:18:10:00:06" + +#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */ +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include +#include "../board/mousse/mousse.h" + +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 8 /* Max number of command args */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#ifdef DEBUG +#define CFG_MONITOR_BASE CFG_SDRAM_BASE +#else +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#endif + +#ifdef DEBUG +#define CFG_MONITOR_LEN (4 << 20) /* lots of mem ... */ +#else +#define CFG_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */ +#endif +#define CFG_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_ISA_MEM 0xFD000000 +#define CFG_ISA_IO 0xFE000000 + +#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_FLASH_SIZE ((uint)(512 * 1024)) +#define CFG_RESET_ADDRESS 0xFFF00100 +#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/ +#define FLASH_BASE0_SIZE 0x80000 /* 512K */ +#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB + 1MB - 64K FLASH0 SEG =960K + (size=0xf0000)*/ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 18432000 + +#define CFG_NS16550_COM1 0xFFE08080 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ +#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 +#define CFG_HZ 1000 + +#define CFG_ETH_DEV_FN 0x00 +#define CFG_ETH_IOBASE 0x00104000 + + + /* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 8 +#define CFG_ROMFAL 8 + + /* Bit-field values for MCCR2. + */ +#define CFG_REFINT 0xf5 /* Refresh interval */ + + /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 0x79 + +#ifdef INCLUDE_ECC +#define USE_ECC 1 +#else /* INCLUDE_ECC */ +#define USE_ECC 0 +#endif /* INCLUDE_ECC */ + + + /* Bit-field values for MCCR3. + */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT (4+USE_ECC) /* Data latancy from read command */ + + /* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ +#define CFG_ACTORW 2 +#define CFG_REGISTERD_TYPE_BUFFER (1-USE_ECC) + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ +#define CFG_RAM_SIZE 0x04000000 /* 64MB */ + + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0x7f + + +#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory + see 8240 book for details*/ +#define PCI_MEM_SPACE1_START 0x80000000 +#define PCI_MEM_SPACE2_START 0xfd000000 + +/* IBAT/DBAT Configuration */ +/* Ram: 64MB, starts at address-0, r/w instruction/data */ +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT0L CFG_IBAT0L + +/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */ +#define CFG_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP) +#if 0 +#define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\ + BATL_WRITETHROUGH | BATL_CACHEINHIBIT) +#else +#define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT) +#endif +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT1L CFG_IBAT1L + +/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */ +#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT2L CFG_IBAT2L + +/* PCI Memory region 2: PCI Devices in 0xFD space */ +#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT3L CFG_IBAT3L + + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 3 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#if 0 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Size of the Environment Sector */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 +#define CFG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/ +#define CFG_ENV_OFFSET CFG_ENV_ADDR +#define CFG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* Localizations */ +#if 0 +#define CONFIG_ETHADDR 0:0:0:0:1:d +#define CONFIG_IPADDR 172.16.40.113 +#define CONFIG_SERVERIP 172.16.40.111 +#else +#define CONFIG_ETHADDR 0:0:0:0:1:d +#define CONFIG_IPADDR 209.128.93.138 +#define CONFIG_SERVERIP 209.128.93.133 +#endif + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h new file mode 100644 index 0000000..6195bca --- /dev/null +++ b/include/configs/MPC8260ADS.h @@ -0,0 +1,509 @@ +/* + * (C) Copyright 2001 + * Stuart Hughes + * This file is based on similar values for other boards found in other + * U-Boot config files, and some that I found in the mpc8260ads manual. + * + * Note: my board is a PILOT rev. + * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. + * + * (C) Copyright 2003-2004 Arabella Software Ltd. + * Yuli Barcohen + * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2. + * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. + * Ported to MPC8272ADS board. + * + * Copyright (c) 2005 MontaVista Software, Inc. + * Vitaly Bordug + * Added support for PCI bridge on MPC8272ADS + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */ + +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* + * Figure out if we are booting low via flash HRCW or high via the BCSR. + */ +#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ +# define CFG_LOWBOOT 1 +#endif + +/* ADS flavours */ +#define CFG_8260ADS 1 /* MPC8260ADS */ +#define CFG_8266ADS 2 /* MPC8266ADS */ +#define CFG_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */ +#define CFG_8272ADS 4 /* MPC8272ADS */ + +#ifndef CONFIG_ADSTYPE +#define CONFIG_ADSTYPE CFG_8260ADS +#endif /* CONFIG_ADSTYPE */ + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CONFIG_MPC8272 1 +#else +#define CONFIG_MPC8260 1 +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* allow serial and ethaddr to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ + +#ifdef CONFIG_ETHER_ON_FCC + +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ + +#if CONFIG_ETHER_INDEX == 1 + +# define CFG_PHY_ADDR 0 +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) +# define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) + +#elif CONFIG_ETHER_INDEX == 2 + +#if CONFIG_ADSTYPE == CFG_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */ +# define CFG_PHY_ADDR 3 +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16) +#else /* RxCLK is CLK13, TxCLK is CLK14 */ +# define CFG_PHY_ADDR 0 +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + +# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + +#endif /* CONFIG_ETHER_INDEX */ + +#define CFG_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */ +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */ + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 2 /* Port C */ + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_MDIO_PIN 0x00002000 /* PC18 */ +#define CFG_MDC_PIN 0x00001000 /* PC19 */ +#else +#define CFG_MDIO_PIN 0x00400000 /* PC9 */ +#define CFG_MDC_PIN 0x00200000 /* PC10 */ +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + +#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) +#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) +#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ + else iop->pdat &= ~CFG_MDIO_PIN + +#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ + else iop->pdat &= ~CFG_MDC_PIN + +#define MIIDELAY udelay(1) + +#endif /* CONFIG_ETHER_ON_FCC */ + +#if CONFIG_ADSTYPE >= CFG_PQ2FADS +#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */ +#else +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) +#define CONFIG_SPD_ADDR 0x50 +#endif +#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ + +/*PCI*/ +#ifdef CONFIG_MPC8272 +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_BOOTDELAY 0 +#define CONFIG_PCI_SCAN_SHOW +#endif + +#ifndef CONFIG_SDRAM_PBI +#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ +#endif + +#ifndef CONFIG_8260_CLKIN +#if CONFIG_ADSTYPE >= CFG_PQ2FADS +#define CONFIG_8260_CLKIN 100000000 /* in Hz */ +#else +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_KGDB | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_SNTP | \ + CFG_CMD_UNIVERSE | \ + CFG_CMD_USB | \ + CFG_CMD_VFD | \ + CFG_CMD_XIMG + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_EXCLUDE ) ) +#elif CONFIG_ADSTYPE >= CFG_PQ2FADS +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_CMD_PCI | \ + CFG_EXCLUDE ) ) +#else +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CMD_CFG_PCI | \ + CFG_EXCLUDE ) ) +#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/mtdblock2" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_FLASH_BASE 0xff800000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ +#define CFG_FLASH_SIZE 8 +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +/* + * JFFS2 partitions + * + * Note: fake mtd_id used, no linux mtd map file + */ +#define MTDIDS_DEFAULT "nor0=mpc8260ads-0" +#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)" +#define CFG_JFFS2_SORT_FRAGMENTS + +/* this is stuff came out of the Motorola docs */ +#ifndef CFG_LOWBOOT +#define CFG_DEFAULT_IMMR 0x0F010000 +#endif + +#define CFG_IMMR 0xF0000000 +#define CFG_BCSR 0xF4500000 +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_PCI_INT 0xF8200000 +#endif +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_LSDRAM_BASE 0xFD000000 + +#define RS232EN_1 0x02000002 +#define RS232EN_2 0x01000001 +#define FETHIEN1 0x08000008 +#define FETH1_RST 0x04000004 +#define FETHIEN2 0x10000000 +#define FETH2_RST 0x08000000 +#define BCSR_PCI_MODE 0x01000000 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#ifdef CFG_LOWBOOT +/* PQ2FADS flash HRCW = 0x0EB4B645 */ +#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ + ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\ + ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ + ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ + ) +#else +/* PQ2FADS BCSR HRCW = 0x0CB23645 */ +#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ + ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ + ( HRCW_BMS | HRCW_APPC10 ) |\ + ( HRCW_MODCK_H0101 ) \ + ) +#endif +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#else +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ +#endif /* CONFIG_BZIP2 */ + +#ifndef CFG_RAMBOOT +# define CFG_ENV_IS_IN_FLASH 1 +# define CFG_ENV_SECT_SIZE 0x40000 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE) +#else +# define CFG_ENV_IS_IN_NVRAM 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +# define CFG_ENV_SIZE 0x200 +#endif /* CFG_RAMBOOT */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) + +#define CFG_HID2 0 + +#define CFG_SYPCR 0xFFFFFFC3 +#define CFG_BCR 0x100C0000 +#define CFG_SIUMCR 0x0A200000 +#define CFG_SCCR SCCR_DFBRG01 +#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801 +#define CFG_OR0_PRELIM 0xFF800876 +#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 +#define CFG_OR1_PRELIM 0xFFFF8010 + +/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_BR3_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */ +#define CFG_OR3_PRELIM 0xFFFF8010 +#endif + +#define CFG_RMR RMR_CSRE +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) +#define CFG_RCCR 0 + +#if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS) +#undef CFG_LSDRAM_BASE /* No local bus SDRAM on these boards */ +#endif /* CONFIG_ADSTYPE == CFG_8266ADS */ + +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CFG_OR2 0xFE002EC0 +#define CFG_PSDMR 0x824B36A3 +#define CFG_PSRT 0x13 +#define CFG_LSDMR 0x828737A3 +#define CFG_LSRT 0x13 +#define CFG_MPTPR 0x2800 +#elif CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_OR2 0xFC002CC0 +#define CFG_PSDMR 0x834E24A3 +#define CFG_PSRT 0x13 +#define CFG_MPTPR 0x2800 +#else +#define CFG_OR2 0xFF000CA0 +#define CFG_PSDMR 0x016EB452 +#define CFG_PSRT 0x21 +#define CFG_LSDMR 0x0086A522 +#define CFG_LSRT 0x21 +#define CFG_MPTPR 0x1900 +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + +#define CFG_RESET_ADDRESS 0x04400000 + +#if CONFIG_ADSTYPE == CFG_8272ADS + +/* PCI Memory map (if different from default map */ +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ + PICMR_PREFETCH_EN) + +/* + * These are the windows that allow the CPU to access PCI address space. + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within + * these windows. + */ + +/* + * Master window that allows the CPU to access PCI Memory (prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) + +/* + * Master window that allows the CPU to access PCI Memory (non-prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) + +/* + * Master window that allows the CPU to access PCI IO space. + * This window will be setup with the first set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) + + +/* PCIBR0 - for PCI IO*/ +#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ +#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ +/* PCIBR1 - prefetch and non-prefetch regions joined together */ +#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) + +#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CONFIG_HAS_ETH1 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h new file mode 100644 index 0000000..4953b70 --- /dev/null +++ b/include/configs/MPC8266ADS.h @@ -0,0 +1,594 @@ +/* + * (C) Copyright 2001 + * Stuart Hughes + * This file is based on similar values for other boards found in other + * U-Boot config files, and some that I found in the mpc8260ads manual. + * + * Note: my board is a PILOT rev. + * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm + */ + +/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + !! !! + !! This configuration requires JP3 to be in position 1-2 to work !! + !! To make it work for the default, the TEXT_BASE define in !! + !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !! + !! 0xfff00000 !! + !! The CFG_HRCW_MASTER define below must also be changed to match !! + !! !! + !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* allow serial and ethaddr to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +/* + * Port pins used for bit-banged MII communictions (if applicable). + */ +#define MDIO_PORT 2 /* Port C */ +#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +#define MDIO_READ ((iop->pdat & 0x00400000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + +#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + +#define MIIDELAY udelay(1) + +#if (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers (see 28-13) + * - Half duplex + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_INDEX */ + +/* other options */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* PCI */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_BOOTDELAY 0 +#undef CONFIG_PCI_SCAN_SHOW + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + + +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#define CONFIG_BAUDRATE 115200 + + +#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_SNTP | \ + CFG_CMD_VFD | \ + CFG_CMD_UNIVERSE | \ + CFG_CMD_USB | \ + CFG_CMD_XIMG ) ) + +/* Define a command string that is automatically executed when no character + * is read on the console interface withing "Boot Delay" after reset. + */ +#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ +#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ + +#ifdef CONFIG_BOOT_ROOT_INITRD +#define CONFIG_BOOTCOMMAND \ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/ram0 rw " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" +#endif /* CONFIG_BOOT_ROOT_INITRD */ + +#ifdef CONFIG_BOOT_ROOT_NFS +#define CONFIG_BOOTCOMMAND \ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" +#endif /* CONFIG_BOOT_ROOT_NFS */ + +/* Add support for a few extra bootp options like: + * - File size + * - DNS + */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ + /* for versions < 2.4.5-pre5 */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_FLASH_BASE 0xFE000000 +#define FLASH_BASE 0xFE000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ +#define CFG_FLASH_SIZE 8 +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ + +#undef CFG_FLASH_CHECKSUM + +/* this is stuff came out of the Motorola docs */ +/* Only change this if you also change the Hardware configuration Word */ +#define CFG_DEFAULT_IMMR 0x0F010000 + +/* Set IMMR to 0xF0000000 or above to boot Linux */ +#define CFG_IMMR 0xF0000000 +#define CFG_BCSR 0xF8000000 +#define CFG_PCI_INT 0xF8200000 /* PCI interrupt controller */ + +/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes + */ +/*#define CONFIG_VERY_BIG_RAM 1*/ + +/* What should be the base address of SDRAM DIMM and how big is + * it (in Mbytes)? This will normally auto-configure via the SPD. +*/ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 + +#define SDRAM_SPD_ADDR 0x50 + + +/*----------------------------------------------------------------------- + * BR2,BR3 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR2,OR3 - Option Register + * Ref: Section 10.3.2 on page 10-16 + *----------------------------------------------------------------------- + */ + +/* Bank 2,3 - SDRAM DIMM + */ + +/* The BR2 is configured as follows: + * + * - Base address of 0x00000000 + * - 64 bit port size (60x bus only) + * - Data errors checking is disabled + * - Read and write access + * - SDRAM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_BR3_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +/* With a 64 MB DIMM, the OR2 is configured as follows: + * + * - 64 MB + * - 4 internal banks per device + * - Row start address bit is A8 with PSDMR[PBI] = 0 + * - 12 row address lines + * - Back-to-back page mode + * - Internal bank interleaving within save device enabled + */ +#if (CFG_SDRAM_SIZE == 64) +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A8 |\ + ORxS_NUMR_12) +#elif (CFG_SDRAM_SIZE == 16) +#define CFG_OR2_PRELIM (0xFF000C80) +#else +#error "INVALID SDRAM CONFIGURATION" +#endif + +/*----------------------------------------------------------------------- + * PSDMR - 60x Bus SDRAM Mode Register + * Ref: Section 10.3.3 on page 10-21 + *----------------------------------------------------------------------- + */ + +#if (CFG_SDRAM_SIZE == 64) +/* With a 64 MB DIMM, the PSDMR is configured as follows: + * + * - Bank Based Interleaving, + * - Refresh Enable, + * - Address Multiplexing where A5 is output on A14 pin + * (A6 on A15, and so on), + * - use address pins A14-A16 as bank select, + * - A9 is output on SDA10 during an ACTIVATE command, + * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, + * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 3 clocks, + * - earliest timing for READ/WRITE command after ACTIVATE command is + * 2 clocks, + * - earliest timing for PRECHARGE after last data was read is 1 clock, + * - earliest timing for PRECHARGE after last data was written is 1 clock, + * - CAS Latency is 2. + */ +#define CFG_PSDMR (PSDMR_RFEN |\ + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) +#elif (CFG_SDRAM_SIZE == 16) +/* With a 16 MB DIMM, the PSDMR is configured as follows: + * + * configuration parameters found in Motorola documentation + */ +#define CFG_PSDMR (0x016EB452) +#else +#error "INVALID SDRAM CONFIGURATION" +#endif + + +#define RS232EN_1 0x02000002 +#define RS232EN_2 0x01000001 +#define FETHIEN 0x08000008 +#define FETH_RST 0x04000004 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */ +/* 0x0EB2B645 */ +#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\ + ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\ + ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ + ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ + ) + +/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */ +/* #define CFG_HRCW_MASTER 0x0cb23645 */ + +/* This value should actually be situated in the first 256 bytes of the FLASH + which on the standard MPC8266ADS board is at address 0xFF800000 + The linker script places it at 0xFFF00000 instead. + + It still works, however, as long as the ADS board jumper JP3 is set to + position 2-3 so the board is using the BCSR as Hardware Configuration Word + + If you want to use the one defined here instead, ust copy the first 256 bytes from + 0xfff00000 to 0xff800000 (for 8MB flash) + + - Rune + +*/ + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#ifndef CFG_RAMBOOT +# define CFG_ENV_IS_IN_FLASH 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +# define CFG_ENV_SECT_SIZE 0x40000 +#else +# define CFG_ENV_IS_IN_NVRAM 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +# define CFG_ENV_SIZE 0x200 +#endif /* CFG_RAMBOOT */ + + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +/*#define CFG_HID0_INIT 0 */ +#define CFG_HID0_INIT (HID0_ICE |\ + HID0_DCE |\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) + +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) + +#define CFG_HID2 0 + +#define CFG_SYPCR 0xFFFFFFC3 +#define CFG_BCR 0x004C0000 +#define CFG_SIUMCR 0x4E64C000 +#define CFG_SCCR 0x00000000 + +/* local bus memory map + * + * 0x00000000-0x03FFFFFF 64MB SDRAM + * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window + * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window + * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory + * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window + * 0xF8000000-0xF8007FFF 32KB BCSR + * 0xF8100000-0xF8107FFF 32KB ATM UNI + * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller + * 0xF8300000-0xF8307FFF 32KB EEPROM + * 0xFE000000-0xFFFFFFFF 32MB flash + */ +#define CFG_BR0_PRELIM 0xFE001801 /* flash */ +#define CFG_OR0_PRELIM 0xFE000836 +#define CFG_BR1_PRELIM (CFG_BCSR | 0x1801) /* BCSR */ +#define CFG_OR1_PRELIM 0xFFFF8010 +#define CFG_BR4_PRELIM 0xF8300801 /* EEPROM */ +#define CFG_OR4_PRELIM 0xFFFF8846 +#define CFG_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */ +#define CFG_OR5_PRELIM 0xFFFF8E36 +#define CFG_BR8_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */ +#define CFG_OR8_PRELIM 0xFFFF8010 + +#define CFG_RMR 0x0001 +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) +#define CFG_RCCR 0 +#define CFG_MPTPR 0x00001900 +#define CFG_PSRT 0x00000021 + +/* This address must not exist */ +#define CFG_RESET_ADDRESS 0xFCFFFF00 + +/* PCI Memory map (if different from default map */ +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ + PICMR_PREFETCH_EN) + +/* + * These are the windows that allow the CPU to access PCI address space. + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within + * these windows. + */ + +/* PCIBR0 */ +#define CFG_PCI_MSTR0_LOCAL 0x80000000 /* Local base */ +#define CFG_PCIMSK0_MASK PCIMSK_1GB /* Size of window */ +/* PCIBR1 */ +#define CFG_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ +#define CFG_PCIMSK1_MASK PCIMSK_64MB /* Size of window */ + +/* + * Master window that allows the CPU to access PCI Memory (prefetch). + * This window will be setup with the first set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) + +/* + * Master window that allows the CPU to access PCI Memory (non-prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) + +/* + * Master window that allows the CPU to access PCI IO space. + * This window will be setup with the third set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "" +#define MTDPARTS_DEFAULT "" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h new file mode 100644 index 0000000..d6d2fab --- /dev/null +++ b/include/configs/MPC8349ADS.h @@ -0,0 +1,584 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8349ads board configuration file + * + * Please refer to doc/README.mpc83xxads for more info. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +#define CONFIG_MII + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8349 1 /* MPC8349 specific */ +#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */ + +/* FIXME: Real PCI support will come in a follow-up update. */ +#undef CONFIG_PCI + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ + +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ + +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#endif +#endif + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMRBAR 0xE0000000 + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ + +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#undef CONFIG_DDR_2T_TIMING +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#else + /* + * Manually set up DDR parameters + */ + #define CFG_DDR_SIZE 256 /* Mb */ + #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) + #define CFG_DDR_TIMING_1 0x37344321 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ + #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ + #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ + #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ +#endif + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ +/* #define CFG_FLASH_USE_BUFFER_WRITE */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM 0xff806ff7 /* 16Mb Flash size*/ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MID_FLASH_JUMP 0x7F000000 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +/* + * BCSR register on local bus 32KB, 8-bit wide for ADS config reg + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ +#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/ +#define CFG_LBLAWBAR2_PRELIM 0xF0000000 +#define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ + | CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR8 \ + | CFG_LBC_LSDMR_PRETOACT6 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC3 \ + | CFG_LBC_LSDMR_CL3 \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) + +/* IO Configuration */ +#define CFG_IO_CONF (\ + IO_CONF_UART |\ + IO_CONF_TSEC1 |\ + IO_CONF_IRQ0 |\ + IO_CONF_IRQ1 |\ + IO_CONF_IRQ2 |\ + IO_CONF_IRQ3 |\ + IO_CONF_IRQ4 |\ + IO_CONF_IRQ5 |\ + IO_CONF_IRQ6 |\ + IO_CONF_IRQ7 ) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI2_MEM_BASE 0xA0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe3000000 +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#if defined(CONFIG_PCI) + +#define PCI_ALL_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + ) +#endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) + +#if defined(PCI_64BIT) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +#define CFG_HID0_INIT 0x000000000 + +#define CFG_HID0_FINAL CFG_HID0_INIT + +/* #define CFG_HID0_FINAL (\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_ENABLE_M_BIT |\ + HID0_ENABLE_ADDRESS_BROADCAST ) */ + +#define CFG_HID2 0x000000000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:04:9f:11:22:33 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01 +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=ramfs.83xx\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h new file mode 100644 index 0000000..131c832 --- /dev/null +++ b/include/configs/MPC8540ADS.h @@ -0,0 +1,520 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8540ads board configuration file + * + * Please refer to doc/README.mpc85xx for more info. + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC8540 1 /* MPC8540 specific */ +#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ + +#ifndef CONFIG_HAS_FEC +#define CONFIG_HAS_FEC 1 /* 8540 has FEC */ +#endif + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 33000000 +#endif + + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +#else + /* + * Manually set up DDR parameters + */ + #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ + #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ + #define CFG_DDR_CS0_CONFIG 0x80000002 + #define CFG_DDR_TIMING_1 0x37344321 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ + #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ + #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ + #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ +#endif + + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ + +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * Local Bus Definitions + */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR5 \ + | CFG_LBC_LSDMR_PRETOACT3 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC2 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) + + +/* + * 32KB, 8-bit wide for ADS config reg + */ +#define CFG_BR4_PRELIM 0xf8000801 +#define CFG_OR4_PRELIM 0xffffe1f1 +#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + + +#if CONFIG_HAS_FEC +#define CONFIG_MPC85XX_FEC 1 +#define CONFIG_MPC85XX_FEC_NAME "FEC" +#define FEC_PHY_ADDR 3 +#define FEC_PHYIDX 0 +#endif + +/* Options are: TSEC[0-1], FEC */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h new file mode 100644 index 0000000..1af9231 --- /dev/null +++ b/include/configs/MPC8540EVAL.h @@ -0,0 +1,347 @@ +/* + * (C) Copyright 2002,2003 Motorola,Inc. + * Modified by Lunsheng Wang, lunsheng@sohu.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* mpc8540eval board configuration file */ +/* please refer to doc/README.mpc85xxads for more info */ +/* make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC8540 1 /* MPC8540 specific */ +#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */ + +#undef CONFIG_PCI /* pci ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ + +/* Using Localbus SDRAM to emulate flash before we can program the flash, + * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. + * Not availabe for EVAL board + */ +#undef CONFIG_RAM_AS_FLASH + +/* sysclk for MPC8540EVAL */ +#if defined(CONFIG_SYSCLK_66M) + /* + * the oscillator on board is 66Mhz + * can also get 66M clock from external PCI + */ + #define CONFIG_SYS_CLK_FREQ 66000000 +#else + #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ +#endif + +/* below can be toggled for performance analysis. otherwise use default */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#undef CONFIG_BTB /* toggle branch predition */ +#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) +#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both." +#endif + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CFG_SDRAM_SIZE 256 /* DDR is now 256MB */ + +#if defined(CONFIG_RAM_AS_FLASH) +#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ +#else +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#endif +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */ + +#if defined(CONFIG_RAM_AS_FLASH) +#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ +#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ +#else /* Boot from real Flash */ +#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ +#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */ +#endif + +#define CFG_OR0_PRELIM 0xff806f67 /* 8MB Flash */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ +#define CFG_FLASH_CFI 1 + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* Here some DDR setting should be added */ + + +#undef CONFIG_CLOCKS_IN_MHZ + +/* local bus definitions */ +#define CFG_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ +#define CFG_OR2_PRELIM 0xfc006901 +#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/ +#define CFG_LBC_LBCR 0x00000000 +#define CFG_LBC_LSRT 0x20000000 +#define CFG_LBC_MRTPR 0x20000000 +#define CFG_LBC_LSDMR_1 0x2861b723 +#define CFG_LBC_LSDMR_2 0x0861b723 +#define CFG_LBC_LSDMR_3 0x0861b723 +#define CFG_LBC_LSDMR_4 0x1861b723 +#define CFG_LBC_LSDMR_5 0x4061b723 + +#if defined(CONFIG_RAM_AS_FLASH) +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ +#else +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ +#endif +#define CFG_OR4_PRELIM 0xffffe1f1 +#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* General PCI */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS 0x80000000 +#define CFG_PCI_MEM_SIZE 0x20000000 +#define CFG_PCI_IO_BASE 0xe2000000 + +#if defined(CONFIG_PCI) +#define CONFIG_NET_MULTI +#undef CONFIG_EEPRO100 +#define CONFIG_TULIP +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#if !defined(CONFIG_PCI_PNP) +#define PCI_ENET0_IOADDR 0xe0000000 +#define PCI_ENET0_MEMADDR 0xe0000000 +#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#endif +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0008 +#elif defined(CONFIG_TSEC_ENET) +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_MPC85XX_FEC 1 +#define CONFIG_MPC85XX_FEC_NAME "FEC" +#define TSEC1_PHY_ADDR 7 +#define TSEC2_PHY_ADDR 4 +#define FEC_PHY_ADDR 2 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define FEC_PHYIDX 0 +/* Options are: TSEC[0-1], FEC */ +#define CONFIG_ETHPRIME "TSEC0" + +#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ +#define INTEL_LXT971_PHY 1 +#endif + +#undef DEBUG + +/* Environment */ +#ifndef CFG_RAMBOOT +#if defined(CONFIG_RAM_AS_FLASH) +#define CFG_ENV_IS_NOWHERE +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) +#define CFG_ENV_SIZE 0x2000 +#else +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#endif +#define CFG_ENV_SIZE 0x2000 +#else +/* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */ +#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +#define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" +#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" +#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \ + | CFG_CMD_PCI | CFG_CMD_I2C ) & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS )) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \ + | CFG_CMD_I2C ) & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS )) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ + | CFG_CMD_PING | CFG_CMD_I2C ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) +#endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*****************************/ +/* Environment Configuration */ +/*****************************/ +/* The mac addresses for all ethernet interface */ +/* NOTE: change below for your network setting!!! */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:01:af:07:9b:8a +#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b +#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c +#endif + +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.101.1 +#define CONFIG_IPADDR 192.168.101.11 +#define CONFIG_GATEWAYIP 192.168.101.0 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_HOSTNAME MPC8540EVAL + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h new file mode 100644 index 0000000..c96b98b --- /dev/null +++ b/include/configs/MPC8541CDS.h @@ -0,0 +1,505 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8541cds board configuration file + * + * Please refer to doc/README.mpc85xxcds for more info. + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ +#define CONFIG_CPM2 1 /* has CPM2 */ +#define CONFIG_MPC8541 1 /* MPC8541 specific */ +#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ + +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ + +#define CFG_BR0_PRELIM 0xff801001 +#define CFG_BR1_PRELIM 0xff001001 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR1_PRELIM 0xff806e65 + +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * The CADMUS registers are connected to CS3 on CDS. + * The new memory map places CADMUS at 0xf8000000. + * + * For BR3, need: + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 + * port-size = 8-bits = BR[19:20] = 01 + * no parity checking = BR[21:22] = 00 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 + * + * For OR3, need: + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * disable buffer ctrl OR[19] = 0 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 + */ + +#define CADMUS_BASE_ADDR 0xf8000000 +#define CFG_BR3_PRELIM 0xf8000801 +#define CFG_OR3_PRELIM 0xfff00ff7 + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 2 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define FEC_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define FEC_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#endif +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h new file mode 100644 index 0000000..4ca8bc3 --- /dev/null +++ b/include/configs/MPC8548CDS.h @@ -0,0 +1,521 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8548cds board configuration file + * + * Please refer to doc/README.mpc85xxcds for more info. + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 /* MPC8548 specific */ +#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ + +#undef CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ + +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ + +#define CFG_BR0_PRELIM 0xff801001 +#define CFG_BR1_PRELIM 0xff001001 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR1_PRELIM 0xff806e65 + +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * The CADMUS registers are connected to CS3 on CDS. + * The new memory map places CADMUS at 0xf8000000. + * + * For BR3, need: + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 + * port-size = 8-bits = BR[19:20] = 01 + * no parity checking = BR[21:22] = 00 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 + * + * For OR3, need: + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * disable buffer ctrl OR[19] = 0 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 + */ + +#define CADMUS_BASE_ADDR 0xf8000000 +#define CFG_BR3_PRELIM 0xf8000801 +#define CFG_OR3_PRELIM 0xfff00ff7 + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 2 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" +#define CONFIG_MPC85XX_TSEC3 1 +#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" +#define CONFIG_MPC85XX_TSEC4 1 +#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 +#define FEC_PHY_ADDR 3 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define FEC_PHYIDX 0 + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#endif +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h new file mode 100644 index 0000000..a44e3ec --- /dev/null +++ b/include/configs/MPC8555CDS.h @@ -0,0 +1,505 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8555cds board configuration file + * + * Please refer to doc/README.mpc85xxcds for more info. + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ +#define CONFIG_CPM2 1 /* has CPM2 */ +#define CONFIG_MPC8555 1 /* MPC8555 specific */ +#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +/* + * Make sure required options are set + */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * Two banks, 8M each, using the CFI driver. + * Boot from BR0/OR0 bank at 0xff00_0000 + * Alternate BR1/OR1 bank at 0xff80_0000 + * + * BR0, BR1: + * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 + * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 + * Port Size = 16 bits = BRx[19:20] = 10 + * Use GPCM = BRx[24:26] = 000 + * Valid = BRx[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * + * OR0, OR1: + * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 + * Reserved ORx[17:18] = 11, confusion here? + * CSNT = ORx[20] = 1 + * ACS = half cycle delay = ORx[21:22] = 11 + * SCY = 6 = ORx[24:27] = 0110 + * TRLX = use relaxed timing = ORx[29] = 1 + * EAD = use external address latch delay = OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + */ + +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ + +#define CFG_BR0_PRELIM 0xff801001 +#define CFG_BR1_PRELIM 0xff001001 + +#define CFG_OR0_PRELIM 0xff806e65 +#define CFG_OR1_PRELIM 0xff806e65 + +#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +/* + * Common settings for all Local Bus SDRAM commands. + * At run time, either BSMA1516 (for CPU 1.1) + * or BSMA1617 (for CPU 1.0) (old) + * is OR'ed in too. + */ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ + | CFG_LBC_LSDMR_PRETOACT7 \ + | CFG_LBC_LSDMR_ACTTORW7 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC4 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * The CADMUS registers are connected to CS3 on CDS. + * The new memory map places CADMUS at 0xf8000000. + * + * For BR3, need: + * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 + * port-size = 8-bits = BR[19:20] = 01 + * no parity checking = BR[21:22] = 00 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 + * + * For OR3, need: + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * disable buffer ctrl OR[19] = 0 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 + * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 + */ + +#define CADMUS_BASE_ADDR 0xf8000000 +#define CFG_BR3_PRELIM 0xf8000801 +#define CFG_OR3_PRELIM 0xfff00ff7 + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 2 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define FEC_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define FEC_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#endif +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h new file mode 100644 index 0000000..2d5031b --- /dev/null +++ b/include/configs/MPC8560ADS.h @@ -0,0 +1,561 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8560ads board configuration file + * + * Please refer to doc/README.mpc85xx for more info. + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_CPM2 1 /* has CPM2 */ +#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 33000000 +#endif + + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +#else + /* + * Manually set up DDR parameters + */ + #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ + #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ + #define CFG_DDR_CS0_CONFIG 0x80000002 + #define CFG_DDR_TIMING_1 0x37344321 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ + #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ + #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ + #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ +#endif + + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ + +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * Local Bus Definitions + */ + +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR5 \ + | CFG_LBC_LSDMR_PRETOACT3 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC2 \ + | CFG_LBC_LSDMR_CL3 \ + | CFG_LBC_LSDMR_RFEN \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) + + +/* + * 32KB, 8-bit wide for ADS config reg + */ +#define CFG_BR4_PRELIM 0xf8000801 +#define CFG_OR4_PRELIM 0xffffe1f1 +#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ + +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + +#if (CONFIG_ETHER_INDEX == 2) + /* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers + * - Full duplex + */ + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CFG_CPMFCR_RAMTYPE 0 + #define CFG_FCC_PSMR (FCC_PSMR_FDE) + #define FETH2_RST 0x01 +#elif (CONFIG_ETHER_INDEX == 3) + /* need more definitions here for FE3 */ + #define FETH3_RST 0x80 +#endif /* CONFIG_ETHER_INDEX */ + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ + +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 2 /* Port C */ +#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +#define MDIO_READ ((iop->pdat & 0x00400000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + +#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + +#define MIIDELAY udelay(1) + +#endif + + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #elif defined(CONFIG_TSEC_ENET) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_ENV)) + #elif defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_ENV)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #elif defined(CONFIG_TSEC_ENET) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #elif defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h new file mode 100644 index 0000000..565f9bb --- /dev/null +++ b/include/configs/MPC86xADS.h @@ -0,0 +1,46 @@ +/* + * A collection of structures, addresses, and values associated with + * the Motorola MPC8xxADS board. Copied from the FADS config. + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * Values common to all FADS family boards are in board/fads/fads.h + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +/* board type */ +#define CONFIG_MPC86xADS 1 /* new ADS */ +#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ + +/* New MPC86xADS - pick one of these */ +#define CONFIG_MPC866T 1 +#undef CONFIG_MPC866P +#undef CONFIG_MPC859T +#undef CONFIG_MPC859DSL +#undef CONFIG_MPC852T + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ 1 + +#include "fads.h" + +#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h new file mode 100644 index 0000000..74318e5 --- /dev/null +++ b/include/configs/MPC885ADS.h @@ -0,0 +1,47 @@ +/* + * A collection of structures, addresses, and values associated with + * the Motorola DUET ADS board. Values common to all FADS family boards + * are in board/fads/fads.h + * + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Board type */ +#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ + +#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ + +#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) + +#define CONFIG_SDRAM_50MHZ 1 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) + +#include "fads.h" + +#undef CFG_SCCR +#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11) + +#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) + +#define CONFIG_HAS_ETH1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h new file mode 100644 index 0000000..da52e0e --- /dev/null +++ b/include/configs/MUSENKI.h @@ -0,0 +1,295 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the MUSENKI board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_MUSENKI 1 + + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#include + + +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 8 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_TULIP + +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET0_MEMADDR 0x80000000 +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET1_MEMADDR 0x81000000 + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ +#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ +#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM + +/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the + * reset vector is actually located at FFB00100, but the 8245 + * takes care of us. + */ +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + + /* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */ + + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* #define CFG_MONITOR_BASE TEXT_BASE */ +/*#define CFG_GBL_DATA_SIZE 256*/ +#define CFG_GBL_DATA_SIZE 128 +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#define CFG_HZ 1000 + + /* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 7 +#define CFG_ROMFAL 11 +#define CFG_DBUS_SIZE 0x3 + + /* Bit-field values for MCCR2. + */ +#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ +#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ + + /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 121 + + /* Bit-field values for MCCR3. + */ +#define CFG_REFREC 8 /* Refresh to activate interval */ + + /* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ +#define CFG_ACTORW 3 /* FIXME was 2 */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + +#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ + +#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0xff + +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + + + /* Warining: environment is not EMBEDDED in the U-Boot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFFFF0000 +#define CFG_ENV_SIZE 0x00010000 /* Size of the Environment */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h new file mode 100644 index 0000000..88eefa1 --- /dev/null +++ b/include/configs/MVBLUE.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define MV_VERSION "v0.2.0" + +/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */ +#define ERR_NONE 0 +#define ERR_ENV 1 +#define ERR_BOOTM_BADMAGIC 2 +#define ERR_BOOTM_BADCRC 3 +#define ERR_BOOTM_GUNZIP 4 +#define ERR_BOOTP_TIMEOUT 5 +#define ERR_DHCP 6 +#define ERR_TFTP 7 +#define ERR_NOLAN 8 +#define ERR_LANDRV 9 + +#define CONFIG_BOARD_TYPES 1 +#define MVBLUE_BOARD_BOX 1 +#define MVBLUE_BOARD_LYNX 2 + +#if 0 +#define ERR_LED(code) do { if (code) \ + *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ + else \ + *(volatile char *)(0xff000003) = ( 1 ); \ + } while(0) +#else +#define ERR_LED(code) +#endif + +#undef DEBUG + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_MVBLUE 1 + +#define CONFIG_CLOCKS_IN_MHZ 1 + +#define CONFIG_BOARD_TYPES 1 + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOT_RETRY_TIME -1 + +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "s" +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_RESET_TO_RETRY 60 + +#define CONFIG_COMMANDS ( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP | \ + CFG_CMD_ECHO | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMI | \ + CFG_CMD_IRQ | CFG_CMD_NET | CFG_CMD_PCI | CFG_CMD_RUN ) + + +#define CONFIG_BOOTP_MASK ( 0xffffffff ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +#define CONFIG_BOOTCOMMAND "run nfsboot" +#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2" + +#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_nr=0\0" \ + "dhcp_client_id=mvBOX-XP\0" \ + "dhcp_vendor-class-identifier=mvBOX\0" \ + "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \ + "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \ + "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \ + "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ + "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \ + "mv_version=" MV_VERSION "\0" \ + "bootretry=30\0" + +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ + +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_TULIP +#define CONFIG_TULIP_FIX_DAVICOM 1 +#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 + +#define CONFIG_HW_WATCHDOG + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_RESET_ADDRESS 0xFFF00100 +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_MONITOR_LEN 0x00100000 +#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ + +/* Maximum amount of RAM. */ +#define CFG_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */ + + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + +#define CFG_ISA_IO 0xFE000000 + +/* + * serial configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 +#define CFG_HZ 10000 + +/* Bit-field values for MCCR1. */ +#define CFG_ROMNAL 7 +#define CFG_ROMFAL 11 + +/* Bit-field values for MCCR2. */ +#define CFG_TSWAIT 0x5 +#define CFG_REFINT 430 + +/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ +#define CFG_BSTOPRE 121 + +/* Bit-field values for MCCR3. */ +#define CFG_REFREC 8 + +/* Bit-field values for MCCR4. */ +#define CFG_PRETOACT 3 +#define CFG_ACTTOPRE 5 +#define CFG_ACTORW 3 +#define CFG_SDMODE_CAS_LAT 3 +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 +#define CFG_DBUS_SIZE2 1 +#define CFG_SDMODE_WRAP 0 + +#define CFG_PGMAX 0x32 +#define CFG_SDRAM_DSCD 0x20 + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0xff + +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#undef CFG_FLASH_PROTECTION +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 63 /* Max number of sectors per flash */ + +#define CFG_FLASH_ERASE_TOUT 12000 +#define CFG_FLASH_WRITE_TOUT 1000 + + +#define CFG_ENV_IS_IN_FLASH + +#define CFG_ENV_OFFSET 0x00010000 +#define CFG_ENV_SIZE 0x00010000 +#define CFG_ENV_SECT_SIZE 0x00010000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h new file mode 100644 index 0000000..5995918 --- /dev/null +++ b/include/configs/MVS1.h @@ -0,0 +1,406 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_MVS 1 /* ...on a MVsensor module */ +#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */ +#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */ +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate */ +#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */ + +#define CONFIG_PREBOOT "echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use \"run bootflash\";echo" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_WATCHDOG /* watchdog disabled/enabled */ + +#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX ) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +/* MVsensor uses a really minimal U-Boot ! */ +#define CONFIG_COMMANDS (CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_IMI | \ + CFG_CMD_FLASH | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_DHCP | \ + CFG_CMD_ENV | \ + CFG_CMD_BOOTD | \ + CFG_CMD_RUN ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 + +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */ + +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 + +/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */ +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */ +#define CFG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 0 /* max. no. of IDE buses */ +#define CFG_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */ + + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#undef FLASH_BASE1_PRELIM + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + + +/* + * FLASH timing: + */ +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +/* +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ + OR_SCY_5_CLK | OR_EHTR) +*/ + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#ifdef CONFIG_MVS_16BIT_FLASH +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#else +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) +#endif + +#undef CFG_OR1_REMAP +#undef CFG_OR1_PRELIM +#undef CFG_BR1_PRELIM +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#undef SDRAM_BASE3_PRELIM +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#undef CFG_OR3_PRELIM +#undef CFG_BR3_PRELIM + + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ +#define CFG_MAMR_PTA 98 + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h new file mode 100644 index 0000000..371ea17 --- /dev/null +++ b/include/configs/NC650.h @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC852T 1 +#define CONFIG_NC650 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ + +/* + * 10 MHz - PLL input clock + */ +#define CONFIG_8xx_OSCLK 10000000 + +/* + * 50 MHz - default CPU clock + */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 + +/* + * 15 MHz - CPU minimum clock + */ +#define CFG_8xx_CPUCLK_MIN 15000000 + +/* + * 133 MHz - CPU maximum clock + */ +#define CFG_8xx_CPUCLK_MAX 133000000 + +#define CFG_MEASURE_CPUCLK +#define CFG_8XX_XIN CONFIG_8xx_OSCLK + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_STATUS_LED /* Status LED disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ +#define FEC_ENET +#define CONFIG_MII +#define CFG_DISCOVER_PHY 1 + + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7f + +/* + * Software (bit-bang) I2C driver configuration + */ +#define SCL 0x1000 /* PA 3 */ +#define SDA 0x2000 /* PA 2 */ + +#define __I2C_DIR immr->im_ioport.iop_padir +#define __I2C_DAT immr->im_ioport.iop_padat +#define __I2C_PAR immr->im_ioport.iop_papar +#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ + __I2C_DIR |= (SDA|SCL); } +#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) +#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } +#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } +#define I2C_DELAY { udelay(5); } +#define I2C_ACTIVE { __I2C_DIR |= SDA; } +#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } + +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_NAND | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 +#define CFG_IMMR_SIZE ((uint)(64 * 1024)) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00740000 + +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ +#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/* + * NAND flash support + */ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_ChipID_UNKNOWN 0x00 +#define SECTORSIZE 512 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define ADDR_COLUMN 1 +#define NAND_NO_RB + +#define NAND_WAIT_READY(nand) udelay(12) +#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND(d, adr + 2) +#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND(d, adr + 1) +#define WRITE_NAND(d, adr) (*(volatile uint8_t *)(adr) = (uint8_t)(d)) +#define READ_NAND(adr) (*(volatile uint8_t *)(adr)) +#define NAND_DISABLE_CE(nand) /* nop */ +#define NAND_ENABLE_CE(nand) /* nop */ +#define NAND_CTL_CLRALE(nandptr) /* nop */ +#define NAND_CTL_SETALE(nandptr) /* nop */ +#define NAND_CTL_CLRCLE(nandptr) /* nop */ +#define NAND_CTL_SETCLE(nandptr) /* nop */ + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ + SCCR_DFLCD000 | SCCR_DFALCD00) + + /*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: Default value of OR0 after reset */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ + OR_SCY_15_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) + +/* + * BR2 and OR2 (NAND Flash) - now addressed through UPMB + */ +#define CFG_NAND_BASE 0x50000000 +#define CFG_NAND_SIZE 0x04000000 + +#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + OR_SCY_15_CLK | OR_EHTR | OR_TRLX) + +#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V ) +#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI ) + +/* + * BR3 and OR3 (SDRAM) + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + + /* + * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) + */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) + +/* + * BR5 and OR5 (SRAM) + */ +#define CFG_SRAM_BASE 0x60000000 +#define CFG_SRAM_SIZE 0x00080000 + +#define CFG_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + OR_SCY_15_CLK | OR_EHTR | OR_TRLX) + +#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM) + + +/* + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 39 + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * MBMR settings for NAND flash + */ + +#define CFG_MBMR_NAND ( MBMR_WLFB_5X ) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ + +/* + * JFFS2 partitions + */ + +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_SIZE 0x00400000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand" + +#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \ + "2560k(cramfs1),2560k(cramfs2)," \ + "256k(u-boot),256k(env);" \ + "nc650-nand:4m(nand1),28m(nand2)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h new file mode 100644 index 0000000..bf4c899 --- /dev/null +++ b/include/configs/NETPHONE.h @@ -0,0 +1,811 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2 +#error Unsupported CONFIG_NETPHONE version +#endif + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ +#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +/* #define CONFIG_XIN 10000000 */ +#define CONFIG_XIN 50000000 +/* #define MPC8XX_HZ 120000000 */ +#define MPC8XX_HZ 66666666 + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" + +#define CONFIG_AUTOSCRIPT +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define FEC_ENET 1 /* eth.c needs it that way... */ +#undef CFG_DISCOVER_PHY +#define CONFIG_MII 1 +#define CONFIG_RMII 1 /* use RMII interface */ + +#define CONFIG_ETHER_ON_FEC1 1 +#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ +#define CONFIG_FEC1_PHY_NORXERR 1 + +#define CONFIG_ETHER_ON_FEC2 1 +#define CONFIG_FEC2_PHY 4 +#define CONFIG_FEC2_PHY_NORXERR 1 + +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_NAND | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_MII | \ + CFG_CMD_CDP \ + ) + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#if CONFIG_NETPHONE_VERSION == 2 +#define CFG_FLASH_BASE4 0x40080000 +#endif + +#define CFG_RESET_ADDRESS 0x80000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#if CONFIG_NETPHONE_VERSION == 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#elif CONFIG_NETPHONE_VERSION == 2 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#endif +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 + +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_OFFSET_REDUND 0 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + */ + +#if CONFIG_XIN == 10000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 50000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 25000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 40000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 75000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 10MHz +#endif + +#elif CONFIG_XIN == 50000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 66666666 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 50MHz +#endif + +#else + +#error unsupported XIN freq +#endif + + +/* + *----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + * + * Note: When TBS == 0 the timebase is independent of current cpu clock. + */ + +#define SCCR_MASK SCCR_EBDF11 +#if MPC8XX_HZ > 66666666 +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) +#else +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) +#endif + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +#if CONFIG_NETPHONE_VERSION == 2 + +#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ + +#define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +#endif + +/* + * BR3 and OR3 (SDRAM) + * + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) + +#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_MAMR_PTA 234 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_ARTOS /* include ARTOS support */ + +#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ + +/****************************************************************/ + +#define DSP_SIZE 0x00010000 /* 64K */ +#define NAND_SIZE 0x00010000 /* 64K */ + +#define DSP_BASE 0xF1000000 +#define NAND_BASE 0xF1010000 + +/****************************************************************/ + +/* NAND */ +#define CFG_NAND_BASE NAND_BASE +#define CONFIG_MTD_NAND_ECC_JFFS2 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_MTD_NAND_UNSAFE + +#define CFG_MAX_NAND_DEVICE 1 + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ +#define NAND_DISABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \ + } while(0) + +#define NAND_ENABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \ + } while(0) + +#define NAND_CTL_CLRALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \ + } while(0) + +#define NAND_CTL_SETALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \ + } while(0) + +#define NAND_CTL_CLRCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \ + } while(0) + +#define NAND_CTL_SETCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \ + } while(0) + +#if CONFIG_NETPHONE_VERSION == 1 +#define NAND_WAIT_READY(nand) \ + do { \ + int _tries = 0; \ + while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \ + if (++_tries > 100000) \ + break; \ + } while (0) +#elif CONFIG_NETPHONE_VERSION == 2 +#define NAND_WAIT_READY(nand) \ + do { \ + int _tries = 0; \ + while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \ + if (++_tries > 100000) \ + break; \ + } while (0) +#endif + +#define WRITE_NAND_COMMAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND_ADDRESS(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define READ_NAND(adr) \ + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) + +/*****************************************************************************/ + +#define CFG_DIRECT_FLASH_TFTP +#define CFG_DIRECT_NAND_TFTP + +/*****************************************************************************/ + +#if CONFIG_NETPHONE_VERSION == 1 +#define STATUS_LED_BIT 0x00000008 /* bit 28 */ +#elif CONFIG_NETPHONE_VERSION == 2 +#define STATUS_LED_BIT 0x00000080 /* bit 24 */ +#endif + +#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_BLINKING + +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#ifndef __ASSEMBLY__ + +/* LEDs */ + +/* led_id_t is unsigned int mask */ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \ + else \ + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ + } while(0) + +#define __led_init(msk, st) __led_set(msk, st) + +#endif + +/*********************************************************************************************************** + + ---------------------------------------------------------------------------------------------- + + (V1) version 1 of the board + (V2) version 2 of the board + + ---------------------------------------------------------------------------------------------- + + Pin definitions: + + +------+----------------+--------+------------------------------------------------------------ + | # | Name | Type | Comment + +------+----------------+--------+------------------------------------------------------------ + | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select + | PA7 | DSP_INT | Output | DSP interrupt + | PA10 | DSP_RESET | Output | DSP reset + | PA14 | USBOE | Output | USB (1) + | PA15 | USBRXD | Output | USB (1) + | PB19 | BT_RTS | Output | Bluetooth (0) + | PB23 | BT_CTS | Output | Bluetooth (0) + | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select + | PB27 | SPICS_DISP | Output | Display chip select + | PB28 | SPI_RXD_3V | Input | SPI Data Rx + | PB29 | SPI_TXD | Output | SPI Data Tx + | PB30 | SPI_CLK | Output | SPI Clock + | PC10 | DISPA0 | Output | Display A0 + | PC11 | BACKLIGHT | Output | Display backlit + | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD + | | IO_RESET | Output | (V2) General I/O reset + | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) + | | HOOK | Input | (V2) Hook input interrupt + | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK + | | F_RY_BY | Input | (V2) NAND F_RY_BY + | PE17 | F_ALE | Output | NAND F_ALE + | PE18 | F_CLE | Output | NAND F_CLE + | PE20 | F_CE | Output | NAND F_CE + | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select + | | LED | Output | (V2) LED + | PE27 | SPICS_ER | Output | External serial register CS + | PE28 | LEDIO1 | Output | (V1) LED + | | BKBR1 | Input | (V2) Keyboard input scan + | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) + | | BKBR2 | Input | (V2) Keyboard input scan + | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) + | | BKBR3 | Input | (V2) Keyboard input scan + | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY + | | BKBR4 | Input | (V2) Keyboard input scan + +------+----------------+--------+--------------------------------------------------- + + ---------------------------------------------------------------------------------------------- + + Serial register input: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | 0 | BKBR1 | (V1) Keyboard input scan + | 1 | BKBR3 | (V1) Keyboard input scan + | 2 | BKBR4 | (V1) Keyboard input scan + | 3 | BKBR2 | (V1) Keyboard input scan + | 4 | HOOK | (V1) Hook switch + | 5 | BT_LINK | (V1) Bluetooth link status + | 6 | HOST_WAKE | (V1) Bluetooth host wake up + | 7 | OK_ETH | (V1) Cisco inline power OK status + +------+----------------+------------------------------------------------------------ + + ---------------------------------------------------------------------------------------------- + + Serial register output: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | 0 | KEY1 | Keyboard output scan + | 1 | KEY2 | Keyboard output scan + | 2 | KEY3 | Keyboard output scan + | 3 | KEY4 | Keyboard output scan + | 4 | KEY5 | Keyboard output scan + | 5 | KEY6 | Keyboard output scan + | 6 | KEY7 | Keyboard output scan + | 7 | BT_WAKE | Bluetooth wake up + +------+----------------+------------------------------------------------------------ + + ---------------------------------------------------------------------------------------------- + + Chip selects: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | CS0 | CS0 | Boot flash + | CS1 | CS_FLASH | NAND flash + | CS2 | CS_DSP | DSP + | CS3 | DCS_DRAM | DRAM + | CS4 | CS_FLASH2 | (V2) 2nd flash + +------+----------------+------------------------------------------------------------ + + ---------------------------------------------------------------------------------------------- + + Interrupts: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | IRQ1 | IRQ_DSP | DSP interrupt + | IRQ3 | S_INTER | DUSLIC ??? + | IRQ4 | F_RY_BY | NAND + | IRQ7 | IRQ_MAX | MAX 3100 interrupt + +------+----------------+------------------------------------------------------------ + + ---------------------------------------------------------------------------------------------- + + Interrupts on PCMCIA pins: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface + | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface + | IP_A2| RMII1_MDINT | PHY interrupt for #1 + | IP_A3| RMII2_MDINT | PHY interrupt for #2 + | IP_A5| HOST_WAKE | (V2) Bluetooth host wake + | IP_A6| OK_ETH | (V2) Cisco inline power OK + +------+----------------+------------------------------------------------------------ + +*************************************************************************************************/ + +#define CONFIG_SED156X 1 /* use SED156X */ +#define CONFIG_SED156X_PG12864Q 1 /* type of display used */ + +/* serial interfacing macros */ + +#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define SED156X_SPI_RXD_MASK 0x00000008 + +#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define SED156X_SPI_TXD_MASK 0x00000004 + +#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define SED156X_SPI_CLK_MASK 0x00000002 + +#define SED156X_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define SED156X_CS_MASK 0x00000010 + +#define SED156X_A0_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define SED156X_A0_MASK 0x0020 + +/*************************************************************************************************/ + +#define CFG_CONSOLE_IS_IN_ENV 1 +#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 +#define CFG_CONSOLE_ENV_OVERWRITE 1 + +/*************************************************************************************************/ + +/* use board specific hardware */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_SHOW_ACTIVITY + +/*************************************************************************************************/ + +/* phone console configuration */ + +#define PHONE_CONSOLE_POLL_HZ (CFG_HZ/200) /* poll every 5ms */ + +/*************************************************************************************************/ + +#define CONFIG_CDP_DEVICE_ID 20 +#define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */ +#define CONFIG_CDP_PORT_ID "eth%d" +#define CONFIG_CDP_CAPABILITIES 0x00000010 +#define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__ +#define CONFIG_CDP_PLATFORM "Intracom NetPhone" +#define CONFIG_CDP_TRIGGER 0x20020001 +#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ +#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */ + +/*************************************************************************************************/ + +#define CONFIG_AUTO_COMPLETE 1 + +/*************************************************************************************************/ + +#define CONFIG_CRC32_VERIFY 1 + +/*************************************************************************************************/ + +#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 + +/*************************************************************************************************/ +#endif /* __CONFIG_H */ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h new file mode 100644 index 0000000..1bcd88d --- /dev/null +++ b/include/configs/NETTA.h @@ -0,0 +1,787 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ +#define CONFIG_NETTA 1 /* ...on a NetTA board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +/* #define CONFIG_XIN 10000000 */ +#define CONFIG_XIN 50000000 +#define MPC8XX_HZ 120000000 +/* #define MPC8XX_HZ 100000000 */ +/* #define MPC8XX_HZ 50000000 */ +/* #define MPC8XX_HZ 80000000 */ + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_HW_WATCHDOG + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define FEC_ENET 1 /* eth.c needs it that way... */ +#undef CFG_DISCOVER_PHY /* do not discover phys */ +#define CONFIG_MII 1 +#define CONFIG_RMII 1 /* use RMII interface */ + +#if defined(CONFIG_NETTA_ISDN) +#define CONFIG_ETHER_ON_FEC1 1 +#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY_NORXERR 1 +#undef CONFIG_ETHER_ON_FEC2 +#else +#define CONFIG_ETHER_ON_FEC1 1 +#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY_NORXERR 1 +#define CONFIG_ETHER_ON_FEC2 1 +#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ +#define CONFIG_FEC2_PHY_NORXERR 1 +#endif + +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CODEC | \ + CFG_POST_DSP ) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_CDP | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_FAT | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_PING | \ + 0) + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 + +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_OFFSET_REDUND 0 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + */ + +#if CONFIG_XIN == 10000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 50000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 25000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 40000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 75000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 10MHz +#endif + +#elif CONFIG_XIN == 50000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 80000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 50000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 50MHz +#endif + +#else + +#error unsupported XIN freq +#endif + + +/* + *----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + * + * Note: When TBS == 0 the timebase is independent of current cpu clock. + */ + +#define SCCR_MASK SCCR_EBDF11 +#if MPC8XX_HZ > 66666666 +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) +#else +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) +#endif + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR3 and OR3 (SDRAM) + * + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) + +#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#if MPC8XX_HZ == 120000000 +#define CFG_MAMR_PTA 234 +#elif MPC8XX_HZ == 100000000 +#define CFG_MAMR_PTA 195 +#elif MPC8XX_HZ == 80000000 +#define CFG_MAMR_PTA 156 +#elif MPC8XX_HZ == 50000000 +#define CFG_MAMR_PTA 98 +#else +#error Unknown frequency +#endif + + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_ARTOS /* include ARTOS support */ + +#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ + +/*********************************************************************************************************** + + Pin definitions: + + +------+----------------+--------+------------------------------------------------------------ + | # | Name | Type | Comment + +------+----------------+--------+------------------------------------------------------------ + | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK + | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK) + | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA + | PA7 | DCL1_3V | Periph | IDL1 PCM clock + | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx + | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx + | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA + | PA12 | P_SHDN | Output | TPS2211A PCMCIA + | PA13 | ETH_LOOP | Output | CISCO Loopback remote power + | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL) + | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA + | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA + | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board + | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only) + | PB16 | DREQ1 | Output | D channel request for S-interface chip 1. + | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC + | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC + | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only) + | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom + | PB21 | LEDIO | Output | Led mode indication for PHY + | PB22 | UART_CTS | Input | UART CTS + | PB23 | UART_RTS | Output | UART RTS + | PB24 | UART_RX | Periph | UART Data Rx + | PB25 | UART_TX | Periph | UART Data Tx + | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock) + | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data) + | PB28 | SPI_RXD_3V | Input | SPI Data Rx + | PB29 | SPI_TXD | Output | SPI Data Tx + | PB30 | SPI_CLK | Output | SPI Clock + | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1 + | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt) + | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt) + | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt) + | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt) + | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK) + | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt) + | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt) + | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt) + | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt) + | PC13 | F_RY_BY | Input | NAND ready signal (interrupt) + | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK) + | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request. + | PD3 | F_ALE | Output | NAND + | PD4 | F_CLE | Output | NAND + | PD5 | F_CE | Output | NAND + | PD6 | DSP_INT | Output | DSP debug interrupt + | PD7 | DSP_RESET | Output | DSP reset + | PD8 | RMII_MDC | Periph | MII mgt clock + | PD9 | SPIEN_C1 | Output | SPI CS for codec #1 + | PD10 | SPIEN_C2 | Output | SPI CS for codec #2 + | PD11 | SPIEN_C3 | Output | SPI CS for codec #3 + | PD12 | FSC2 | Periph | IDL2 frame sync + | PD13 | DGRANT2 | Input | D channel grant from S #2 + | PD14 | SPIEN_C4 | Output | SPI CS for codec #4 + | PD15 | TP700 | Output | Testpoint for software debugging + | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data + | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data + | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for + | | DCL2 | Periph | NetRoute: PCM clock #2 + | PE17 | TP703 | Output | Testpoint for software debugging + | PE18 | DGRANT1 | Input | D channel grant from S #1 + | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable + | | PCM2OUT | Periph | NetRoute: Tx data for IDL2 + | PE20 | FSC1 | Periph | IDL1 frame sync + | PE21 | RMII2-RXD0 | Periph | FEC2 receive data + | PE22 | RMII2-RXD1 | Periph | FEC2 receive data + | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC + | PE24 | U-N1 | Output | Select user/network for S #1 (0=user) + | PE25 | U-N2 | Output | Select user/network for S #2 (0=user) + | PE26 | RMII2-RXDV | Periph | FEC2 valid + | PE27 | DREQ2 | Output | D channel request for S #2. + | PE28 | FPGA_DONE | Input | FPGA done signal + | PE29 | FPGA_INIT | Output | FPGA init signal + | PE30 | UDOUT2_3V | Input | IDL2 PCM input + | PE31 | | | Free + +------+----------------+--------+--------------------------------------------------- + + Chip selects: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | CS0 | CS0 | Boot flash + | CS1 | CS_FLASH | NAND flash + | CS2 | CS_DSP | DSP + | CS3 | DCS_DRAM | DRAM + | CS4 | CS_ER1 | External output register + +------+----------------+------------------------------------------------------------ + + Interrupts: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | IRQ1 | UINTER_3V | S interupt chips interrupt (common) + | IRQ3 | IRQ_DSP | DSP interrupt + | IRQ4 | IRQ_DSP1 | Extra DSP interrupt + +------+----------------+------------------------------------------------------------ + +*************************************************************************************************/ + +#define DSP_SIZE 0x00010000 /* 64K */ +#define NAND_SIZE 0x00010000 /* 64K */ +#define ER_SIZE 0x00010000 /* 64K */ +#define DUMMY_SIZE 0x00010000 /* 64K */ + +#define DSP_BASE 0xF1000000 +#define NAND_BASE 0xF1010000 +#define ER_BASE 0xF1020000 +#define DUMMY_BASE 0xF1FF0000 + +/****************************************************************/ + +/* NAND */ +#define CFG_NAND_BASE NAND_BASE +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_MTD_NAND_UNSAFE + +#define CFG_MAX_NAND_DEVICE 1 +/* #define NAND_NO_RB */ + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */ +#define NAND_DISABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \ + } while(0) + +#define NAND_ENABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \ + } while(0) + +#define NAND_CTL_CLRALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \ + } while(0) + +#define NAND_CTL_SETALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \ + } while(0) + +#define NAND_CTL_CLRCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \ + } while(0) + +#define NAND_CTL_SETCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \ + } while(0) + +#ifndef NAND_NO_RB +#define NAND_WAIT_READY(nand) \ + do { \ + while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \ + WATCHDOG_RESET(); \ + } \ + } while (0) +#else +#define NAND_WAIT_READY(nand) udelay(12) +#endif + +#define WRITE_NAND_COMMAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND_ADDRESS(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define READ_NAND(adr) \ + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) + +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_SIZE 0x00100000 +#define CONFIG_JFFS2_PART_OFFSET 0x00200000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=netta-nand" +#define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)" +*/ + +/*****************************************************************************/ + +#define CFG_DIRECT_FLASH_TFTP +#define CFG_DIRECT_NAND_TFTP + +/*****************************************************************************/ + +#if 1 +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + */ + +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#endif + +/*************************************************************************************************/ + +#define CONFIG_CDP_DEVICE_ID 20 +#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */ +#define CONFIG_CDP_PORT_ID "eth%d" +#define CONFIG_CDP_CAPABILITIES 0x00000010 +#define CONFIG_CDP_VERSION "u-boot 1.0" " " __DATE__ " " __TIME__ +#define CONFIG_CDP_PLATFORM "Intracom NetTA" +#define CONFIG_CDP_TRIGGER 0x20020001 +#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ +#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */ + +/*************************************************************************************************/ + +#define CONFIG_AUTO_COMPLETE 1 + +/*************************************************************************************************/ + +#define CONFIG_CRC32_VERIFY 1 + +/*************************************************************************************************/ + +#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 + +/*************************************************************************************************/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h new file mode 100644 index 0000000..529cb4c --- /dev/null +++ b/include/configs/NETTA2.h @@ -0,0 +1,762 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetTA4 board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2 +#error Unsupported CONFIG_NETTA2 version +#endif + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ +#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +/* #define CONFIG_XIN 10000000 */ +#define CONFIG_XIN 50000000 +/* #define MPC8XX_HZ 120000000 */ +#define MPC8XX_HZ 66666666 + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_AUTOSCRIPT +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define FEC_ENET 1 /* eth.c needs it that way... */ +#undef CFG_DISCOVER_PHY +#define CONFIG_MII 1 +#define CONFIG_RMII 1 /* use RMII interface */ + +#define CONFIG_ETHER_ON_FEC1 1 +#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ +#define CONFIG_FEC1_PHY_NORXERR 1 + +#define CONFIG_ETHER_ON_FEC2 1 +#define CONFIG_FEC2_PHY 4 +#define CONFIG_FEC2_PHY_NORXERR 1 + +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_NAND | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_MII | \ + CFG_CMD_CDP \ + ) + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#if CONFIG_NETTA2_VERSION == 2 +#define CFG_FLASH_BASE4 0x40080000 +#endif + +#define CFG_RESET_ADDRESS 0x80000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#if CONFIG_NETTA2_VERSION == 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#elif CONFIG_NETTA2_VERSION == 2 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#endif +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 + +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_OFFSET_REDUND 0 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + */ + +#if CONFIG_XIN == 10000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 50000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 25000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 40000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 75000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 10MHz +#endif + +#elif CONFIG_XIN == 50000000 + +#if MPC8XX_HZ == 120000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 100000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 66666666 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 50MHz +#endif + +#else + +#error unsupported XIN freq +#endif + + +/* + *----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + * + * Note: When TBS == 0 the timebase is independent of current cpu clock. + */ + +#define SCCR_MASK SCCR_EBDF11 +#if MPC8XX_HZ > 66666666 +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) +#else +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) +#endif + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +#if CONFIG_NETTA2_VERSION == 2 + +#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ + +#define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +#endif + +/* + * BR3 and OR3 (SDRAM) + * + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) + +#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_MAMR_PTA 234 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_ARTOS /* include ARTOS support */ + +#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ + +/****************************************************************/ + +#define DSP_SIZE 0x00010000 /* 64K */ +#define NAND_SIZE 0x00010000 /* 64K */ + +#define DSP_BASE 0xF1000000 +#define NAND_BASE 0xF1010000 + +/****************************************************************/ + +/* NAND */ +#define CFG_NAND_BASE NAND_BASE +#define CONFIG_MTD_NAND_ECC_JFFS2 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_MTD_NAND_UNSAFE + +#define CFG_MAX_NAND_DEVICE 1 + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ +#define NAND_DISABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \ + } while(0) + +#define NAND_ENABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \ + } while(0) + +#define NAND_CTL_CLRALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \ + } while(0) + +#define NAND_CTL_SETALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \ + } while(0) + +#define NAND_CTL_CLRCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \ + } while(0) + +#define NAND_CTL_SETCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \ + } while(0) + +#if CONFIG_NETTA2_VERSION == 1 +#define NAND_WAIT_READY(nand) \ + do { \ + int _tries = 0; \ + while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \ + if (++_tries > 100000) \ + break; \ + } while (0) +#elif CONFIG_NETTA2_VERSION == 2 +#define NAND_WAIT_READY(nand) \ + do { \ + int _tries = 0; \ + while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \ + if (++_tries > 100000) \ + break; \ + } while (0) +#endif + +#define WRITE_NAND_COMMAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND_ADDRESS(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define READ_NAND(adr) \ + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) + +/*****************************************************************************/ + +#define CFG_DIRECT_FLASH_TFTP +#define CFG_DIRECT_NAND_TFTP + +/*****************************************************************************/ + +#if CONFIG_NETTA2_VERSION == 1 +#define STATUS_LED_BIT 0x00000008 /* bit 28 */ +#elif CONFIG_NETTA2_VERSION == 2 +#define STATUS_LED_BIT 0x00000080 /* bit 24 */ +#endif + +#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_BLINKING + +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#ifndef __ASSEMBLY__ + +/* LEDs */ + +/* led_id_t is unsigned int mask */ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \ + else \ + ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ + } while(0) + +#define __led_init(msk, st) __led_set(msk, st) + +#endif + +/*********************************************************************************************************** + + ---------------------------------------------------------------------------------------------- + + (V1) version 1 of the board + (V2) version 2 of the board + + ---------------------------------------------------------------------------------------------- + + Pin definitions: + + +------+----------------+--------+------------------------------------------------------------ + | # | Name | Type | Comment + +------+----------------+--------+------------------------------------------------------------ + | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select + | PA7 | DSP_INT | Output | DSP interrupt + | PA10 | DSP_RESET | Output | DSP reset + | PA14 | USBOE | Output | USB (1) + | PA15 | USBRXD | Output | USB (1) + | PB19 | BT_RTS | Output | Bluetooth (0) + | PB23 | BT_CTS | Output | Bluetooth (0) + | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select + | PB27 | SPICS_DISP | Output | Display chip select + | PB28 | SPI_RXD_3V | Input | SPI Data Rx + | PB29 | SPI_TXD | Output | SPI Data Tx + | PB30 | SPI_CLK | Output | SPI Clock + | PC10 | DISPA0 | Output | Display A0 + | PC11 | BACKLIGHT | Output | Display backlit + | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD + | | IO_RESET | Output | (V2) General I/O reset + | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) + | | HOOK | Input | (V2) Hook input interrupt + | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK + | | F_RY_BY | Input | (V2) NAND F_RY_BY + | PE17 | F_ALE | Output | NAND F_ALE + | PE18 | F_CLE | Output | NAND F_CLE + | PE20 | F_CE | Output | NAND F_CE + | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select + | | LED | Output | (V2) LED + | PE27 | SPICS_ER | Output | External serial register CS + | PE28 | LEDIO1 | Output | (V1) LED + | | BKBR1 | Input | (V2) Keyboard input scan + | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) + | | BKBR2 | Input | (V2) Keyboard input scan + | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) + | | BKBR3 | Input | (V2) Keyboard input scan + | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY + | | BKBR4 | Input | (V2) Keyboard input scan + +------+----------------+--------+--------------------------------------------------- + + ---------------------------------------------------------------------------------------------- + + Serial register input: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | 4 | HOOK | Hook switch + | 5 | BT_LINK | Bluetooth link status + | 6 | HOST_WAKE | Bluetooth host wake up + | 7 | OK_ETH | Cisco inline power OK status + +------+----------------+------------------------------------------------------------ + + ---------------------------------------------------------------------------------------------- + + Chip selects: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | CS0 | CS0 | Boot flash + | CS1 | CS_FLASH | NAND flash + | CS2 | CS_DSP | DSP + | CS3 | DCS_DRAM | DRAM + | CS4 | CS_FLASH2 | (V2) 2nd flash + +------+----------------+------------------------------------------------------------ + + ---------------------------------------------------------------------------------------------- + + Interrupts: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | IRQ1 | IRQ_DSP | DSP interrupt + | IRQ3 | S_INTER | DUSLIC ??? + | IRQ4 | F_RY_BY | NAND + | IRQ7 | IRQ_MAX | MAX 3100 interrupt + +------+----------------+------------------------------------------------------------ + + ---------------------------------------------------------------------------------------------- + + Interrupts on PCMCIA pins: + + +------+----------------+------------------------------------------------------------ + | # | Name | Comment + +------+----------------+------------------------------------------------------------ + | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface + | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface + | IP_A2| RMII1_MDINT | PHY interrupt for #1 + | IP_A3| RMII2_MDINT | PHY interrupt for #2 + | IP_A5| HOST_WAKE | (V2) Bluetooth host wake + | IP_A6| OK_ETH | (V2) Cisco inline power OK + +------+----------------+------------------------------------------------------------ + +**************************************************************************************************/ + +#define CFG_CONSOLE_IS_IN_ENV 1 +#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 +#define CFG_CONSOLE_ENV_OVERWRITE 1 + +/*************************************************************************************************/ + +/* use board specific hardware */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_SHOW_ACTIVITY + +/*************************************************************************************************/ + +#define CONFIG_CDP_DEVICE_ID 20 +#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */ +#define CONFIG_CDP_PORT_ID "eth%d" +#define CONFIG_CDP_CAPABILITIES 0x00000010 +#define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__ +#define CONFIG_CDP_PLATFORM "Intracom NetTA2" +#define CONFIG_CDP_TRIGGER 0x20020001 +#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ +#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */ + +/*************************************************************************************************/ + +#define CONFIG_AUTO_COMPLETE 1 + +/*************************************************************************************************/ + +#define CONFIG_CRC32_VERIFY 1 + +/*************************************************************************************************/ + +#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 + +/*************************************************************************************************/ +#endif /* __CONFIG_H */ diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h new file mode 100644 index 0000000..dc6b15f --- /dev/null +++ b/include/configs/NETVIA.h @@ -0,0 +1,530 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * U-Boot port on NetVia board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_NETVIA 1 /* ...on a NetVia board */ + +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#else +#define CONFIG_8xx_CONS_NONE +#define CONFIG_MAX3100_SERIAL +#endif + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_XIN 10000000 +#define CONFIG_8xx_GCLK_FREQ 80000000 + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ +#endif + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING ) + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 +#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND) +#else +#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE +#endif + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 + +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_OFFSET_REDUND 0 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * + *----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ + +#define SCCR_MASK SCCR_EBDF11 + +#if CONFIG_8xx_GCLK_FREQ == 50000000 + +#define CFG_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +#elif CONFIG_8xx_GCLK_FREQ == 80000000 + +#define CFG_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) + +#endif + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR3 and OR3 (SDRAM) + * + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) + +#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 208 + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* Ethernet at SCC2 */ +#define CONFIG_SCC2_ENET + +#define CONFIG_ARTOS /* include ARTOS support */ + +/****************************************************************/ + +#define DSP_SIZE 0x00010000 /* 64K */ +#define FPGA_SIZE 0x00010000 /* 64K */ + +#define DSP0_BASE 0xF1000000 +#define DSP1_BASE (DSP0_BASE + DSP_SIZE) +#define FPGA_BASE (DSP1_BASE + DSP_SIZE) + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + +#define ER_SIZE 0x00010000 /* 64K */ +#define ER_BASE (FPGA_BASE + FPGA_SIZE) + +#define NAND_SIZE 0x00010000 /* 64K */ +#define NAND_BASE (ER_BASE + ER_SIZE) + +#endif + +/****************************************************************/ + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + +#define STATUS_LED_BIT 0x00000001 /* bit 31 */ +#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_BLINKING + +#define STATUS_LED_BIT1 0x00000002 /* bit 30 */ +#define STATUS_LED_PERIOD1 (CFG_HZ / 2) +#define STATUS_LED_STATE1 STATUS_LED_OFF + +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#endif + +/*****************************************************************************/ + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + +/* NAND */ +#define CFG_NAND_BASE NAND_BASE +#define CONFIG_MTD_NAND_ECC_JFFS2 + +#define CFG_MAX_NAND_DEVICE 1 + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define NAND_DISABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0040; \ + } while(0) + +#define NAND_ENABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \ + } while(0) + +#define NAND_CTL_CLRALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \ + } while(0) + +#define NAND_CTL_SETALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0100; \ + } while(0) + +#define NAND_CTL_CLRCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \ + } while(0) + +#define NAND_CTL_SETCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0080; \ + } while(0) + +#define NAND_WAIT_READY(nand) \ + do { \ + while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \ + ; \ + } while (0) + +#define WRITE_NAND_COMMAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND_ADDRESS(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define READ_NAND(adr) \ + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) + +#endif + +/*****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + +/* LEDs */ + +/* last value written to the external register; we cannot read back */ +extern unsigned int last_er_val; + +/* led_id_t is unsigned long mask */ +typedef unsigned int led_id_t; + +static inline void __led_init(led_id_t mask, int state) +{ + unsigned int new_er_val; + + if (state) + new_er_val = last_er_val & ~mask; + else + new_er_val = last_er_val | mask; + + *(volatile unsigned int *)ER_BASE = new_er_val; + last_er_val = new_er_val; +} + +static inline void __led_toggle(led_id_t mask) +{ + unsigned int new_er_val; + + new_er_val = last_er_val ^ mask; + *(volatile unsigned int *)ER_BASE = new_er_val; + last_er_val = new_er_val; +} + +static inline void __led_set(led_id_t mask, int state) +{ + unsigned int new_er_val; + + if (state) + new_er_val = last_er_val & ~mask; + else + new_er_val = last_er_val | mask; + + *(volatile unsigned int *)ER_BASE = new_er_val; + last_er_val = new_er_val; +} + +/* MAX3100 console */ +#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define MAX3100_SPI_RXD_BIT 0x00000008 + +#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define MAX3100_SPI_TXD_BIT 0x00000004 + +#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define MAX3100_SPI_CLK_BIT 0x00000002 + +#define MAX3100_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) +#define MAX3100_CS_BIT 0x0010 + +#endif + +#endif + +/*************************************************************************************************/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h new file mode 100644 index 0000000..d994420 --- /dev/null +++ b/include/configs/NSCU.h @@ -0,0 +1,461 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ +#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ +#define CONFIG_NSCU 1 + +#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ + +#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/NSCU/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +/* NSCU use both slots, SLOT_A as "primary". */ +#define CONFIG_PCMCIA_SLOT_A 1 + +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) +#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ +#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ +#undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE buses */ +#define CFG_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) /* starts @ 4th window */ + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +#ifdef CONFIG_ISP1362_USB +#define CFG_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ +#define CFG_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR5_ISP1362 (CFG_ISP1362_OR_AM | OR_CSNT_SAM | \ + OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) +#define CFG_BR5_ISP1362 ((CFG_ISP1362_BASE & BR_BA_MSK) | \ + BR_PS_16 | BR_MS_GPCM | BR_V ) +#endif /* CONFIG_ISP1362_USB */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#undef CONFIG_SCC1_ENET +#define CONFIG_FEC_ENET +/* #define CONFIG_ETHPRIME "FEC ETHERNET" */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/NX823.h b/include/configs/NX823.h new file mode 100644 index 0000000..1cb8b8f --- /dev/null +++ b/include/configs/NX823.h @@ -0,0 +1,360 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */ + +/*#define CONFIG_VIDEO 1 */ + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */ +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ +#define CONFIG_BOOTARGS "ramdisk=8000 "\ + "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\ + "nfsaddrs=10.77.77.20:10.77.77.250" +#define CONFIG_BOOTCOMMAND "bootm 400e0000" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_WATCHDOG /* watchdog disabled, for now */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT) +#define CONFIG_AUTOSCRIPT + +/* call various generic functions */ +#define CONFIG_MISC_INIT_R + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define xEMBED +#ifdef EMBED +#define CFG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */ +#define CFG_ENV_ADDR CFG_MONITOR_BASE +#else +#define CFG_ENV_ADDR 0x40020000 /* absolute address for now */ +#define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ +#endif + +#define CFG_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */ +#define CFG_FLASH_SN_SECTOR 0x40000000 /* a serial number here */ +#define CFG_FLASH_SN_BYTES 8 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 12-30 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 12-16 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 12-18 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 12-23 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define MPC8XX_SPEED 66666666L +#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */ +#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) +#define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) +#define CFG_PLPRCR (CFG_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 5-3 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + OR_SCY_8_CLK ) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* + * BR1/2 and OR1/2 (SDRAM) + */ +#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */ +#define CFG_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM) + +#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#define CFG_OR2_PRELIM CFG_OR1_PRELIM +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* IO and memory mapped stuff */ +#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */ +#define NX823_IO_BASE 0xFF000000 /* start of IO */ +#define GPOUT_OFFSET (3<<16) +#define QUART_OFFSET (4<<16) +#define VIDAC_OFFSET (5<<16) +#define CPLD_OFFSET (6<<16) +#define SED1386_OFFSET (7<<16) + +/* + * BR3 and OR3 (general purpose output latches) + */ +#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET) +#define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI) +#define CFG_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING) +#define CFG_BR3_PRELIM (GPOUT_BASE | BR_V) + +/* + * BR4 and OR4 (QUART) + */ +#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET) +#define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX) +#define CFG_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI) +#define CFG_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V) + +/* + * BR5 and OR5 (Video DAC) + */ +#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET) +#define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) +#define CFG_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI) +#define CFG_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V) + +/* + * BR6 and OR6 (CPLD) + * FIXME timing not verified for CPLD + */ +#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET) +#define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) +#define CFG_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI) +#define CFG_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V ) + +/* + * BR7 and OR7 (SED1386) + * FIXME timing not verified for SED controller + */ +#define SED1386_BASE 0xF7000000 +#define CFG_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA) +#define CFG_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */ +#define CONFIG_ETHADDR 00:10:20:30:40:50 +#define CONFIG_IPADDR 10.77.77.20 +#define CONFIG_SERVERIP 10.77.77.250 + +#endif /* __CONFIG_H */ diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h new file mode 100644 index 0000000..aa9d1ba --- /dev/null +++ b/include/configs/OCRTC.h @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_OCRTC 1 /* ...on a OCRTC board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND "go fff00100" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ELF | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ + +#else /* Use EEPROM for environment variables */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ + /* total size of a CAT24WC08 is 1024 bytes */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC08) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (PLD - FPGA-boot) initialization */ +#define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (PLD - OSL) initialization */ +#define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 4 (Spartan2 1) initialization */ +#define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ + +/* Memory Bank 5 (Spartan2 2) initialization */ +#define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ + +/* Memory Bank 6 (Virtex 1) initialization */ +#define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 7 (Virtex 2) initialization */ +#define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ + + +#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h new file mode 100644 index 0000000..2e7c505 --- /dev/null +++ b/include/configs/ORSG.h @@ -0,0 +1,300 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_ORSG 1 /* ...on a ORSG board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND "go fff00100" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ELF | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */ +#undef CONFIG_PCI_PNP /* no pci plug-and-play */ + /* resource configuration */ + +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ + +#else /* Use EEPROM for environment variables */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ + /* total size of a CAT24WC08 is 1024 bytes */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC08) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (PLD - FPGA-boot) initialization */ +#define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (PLD - OSL) initialization */ +#define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 4 (Spartan2 1) initialization */ +#define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ + +/* Memory Bank 5 (Spartan2 2) initialization */ +#define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ + +/* Memory Bank 6 (Virtex 1) initialization */ +#define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 7 (Virtex 2) initialization */ +#define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ +#define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ + + +#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/OXC.h b/include/configs/OXC.h new file mode 100644 index 0000000..787407c --- /dev/null +++ b/include/configs/OXC.h @@ -0,0 +1,314 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8240 1 +#define CONFIG_OXC 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#define CONFIG_IDENT_STRING " [oxc] " + +#define CONFIG_WATCHDOG 1 +#define CONFIG_SHOW_ACTIVITY 1 +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ + +/*----------------------------------------------------------------------- + * Boot options + */ + +#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_GATEWAYIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_LOADADDR 0x10000 +#define CONFIG_BOOTFILE "/mnt/ide0/p2/usr/tftp/oxc.elf" +#define CONFIG_BOOTCOMMAND "tftp 0x10000 ; bootelf 0x10000" +#define CONFIG_BOOTDELAY 10 + +#define CFG_OXC_GENERATE_IP 1 /* Generate IP automatically */ +#define CFG_OXC_IPMASK 0x0A000000 /* 10.0.0.x */ + +/*----------------------------------------------------------------------- + * PCI stuff + */ + +#define CONFIG_PCI /* include pci support */ + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_EEPRO100 /* Ethernet Express PRO 100 */ +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET0_MEMADDR 0x80000000 +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET1_MEMADDR 0x81000000 + +/*----------------------------------------------------------------------- + * FLASH + */ + +#define CFG_FLASH_PRELIMBASE 0xFF800000 +#define CFG_FLASH_BASE (0-flash_info[0].size) + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * RAM + */ + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x10000000 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN 0x00030000 + +#if (CFG_MONITOR_BASE < CFG_FLASH_PRELIMBASE) +# define CFG_RAMBOOT 1 +#else +# undef CFG_RAMBOOT +#endif + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 + +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Memory mapping + */ + +#define CFG_CPLD_BASE 0xff000000 /* CPLD registers */ +#define CFG_CPLD_WATCHDOG (CFG_CPLD_BASE) /* Watchdog */ +#define CFG_CPLD_RESET (CFG_CPLD_BASE + 0x040000) /* Minor resets */ +#define CFG_UART_BASE (CFG_CPLD_BASE + 0x700000) /* debug UART */ + +/*----------------------------------------------------------------------- + * NS16550 Configuration + */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE -4 +#define CFG_NS16550_CLK 1843200 +#define CFG_NS16550_COM1 CFG_UART_BASE + +/*----------------------------------------------------------------------- + * I2C Bus + */ + +#define CONFIG_I2C 1 /* I2C support on ... */ +#define CONFIG_HARD_I2C 1 /* ... hardware one */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ + +#define CFG_I2C_EXPANDER0_ADDR 0x20 /* PCF8574 expander 0 addrerr */ +#define CFG_I2C_EXPANDER1_ADDR 0x21 /* PCF8574 expander 1 addrerr */ +#define CFG_I2C_EXPANDER2_ADDR 0x26 /* PCF8574 expander 2 addrerr */ + +/*----------------------------------------------------------------------- + * Environment + */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFFF30000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */ +#define CFG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ +#define CONFIG_ENV_OVERWRITE 1 /* Allow modifying the environment */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ +#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 + +#define CFG_EUMB_ADDR 0xFC000000 + +/* MCCR1 */ +#define CFG_ROMNAL 0 /* rom/flash next access time */ +#define CFG_ROMFAL 19 /* rom/flash access time */ + +/* MCCR2 */ +#define CFG_ASRISE 15 /* ASRISE=15 clocks */ +#define CFG_ASFALL 3 /* ASFALL=3 clocks */ +#define CFG_REFINT 1000 /* REFINT=1000 clocks */ + +/* MCCR3 */ +#define CFG_BSTOPRE 0x35c /* Burst To Precharge */ +#define CFG_REFREC 7 /* Refresh to activate interval */ +#define CFG_RDLAT 4 /* data latency from read command */ + +/* MCCR4 */ +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 2 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length 2=4, 3=8 */ +#define CFG_REGISTERD_TYPE_BUFFER 1 + +/* memory bank settings*/ +/* + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x00000000 +#define CFG_BANK1_END 0x00000000 +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x00000000 +#define CFG_BANK2_END 0x00000000 +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x00000000 +#define CFG_BANK3_END 0x00000000 +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* PCI memory */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h new file mode 100644 index 0000000..a933e1b --- /dev/null +++ b/include/configs/P3G4.h @@ -0,0 +1,426 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#include "../board/evb64260/local.h" + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_P3G4 1 /* this is a P3G4 board */ +#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ + +#undef CONFIG_ECC /* enable ECC support */ +/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#define CFG_BOARD_NAME "P3G4" + +#undef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * to use the MPSC, #define CONFIG_MPSC. If you have wired up another + * mpsc channel, change CONFIG_MPSC_PORT to the desired value. + */ +#define CONFIG_MPSC +#define CONFIG_MPSC_PORT 0 + +#define CONFIG_NET_MULTI /* attempt all available adapters */ + +/* define this if you want to enable GT MAC filtering */ +#define CONFIG_GT_USE_MAC_HASH_TABLE + +#undef CONFIG_ETHER_PORT_MII /* use RMII */ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=p3g4\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_74xx\0" \ + "bootfile=/tftpboot/p3g4/uImage\0" \ + "kernel_addr=ff000000\0" \ + "ramdisk_addr=ff010000\0" \ + "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ + "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ + "cp.b 100000 fff00000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_ALTIVEC /* undef to disable */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_UNIVERSE| \ + CFG_CMD_BSP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00300000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CFG_BUS_HZ 133000000 /* 133 MHz */ +#define CFG_BUS_CLK CFG_BUS_HZ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_LOCK + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xff000000 +#define CFG_RESET_ADDRESS 0xfff00100 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +/* areas to map different things with the GT in physical space */ +#define CFG_DRAM_BANKS 1 +#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ + +/* What to put in the bats. */ +#define CFG_MISC_REGION_BASE 0xf0000000 + +/* Peripheral Device section */ +#define CFG_GT_REGS 0xf8000000 +#define CFG_DEV_BASE 0xff000000 + +#define CFG_DEV0_SPACE CFG_DEV_BASE +#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) +#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) +#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) + +#define CFG_DEV0_SIZE _8M /* Flash bank */ +#define CFG_DEV1_SIZE 0 /* unused */ +#define CFG_DEV2_SIZE 0 /* unused */ +#define CFG_DEV3_SIZE 0 /* unused */ + +#define CFG_16BIT_BOOT_PAR 0xc01b5e7c +#define CFG_DEV0_PAR CFG_16BIT_BOOT_PAR + +#if 0 /* Wrong?? NTL */ +#define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ + /* DMAAck[1:0] GNT0[1:0] */ +#else +#define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ + /* REQ0[1:0] GNT0[1:0] */ +#endif +#define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ + /* DMAReq[4] DMAAck[4] WDNMI WDE */ +#if 0 /* Wrong?? NTL */ +#define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ + /* DMAAck[1:0] GNT1[1:0] */ +#else +#define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ + /* GPP[22] (RS232IntB or PCI1Int) */ + /* GPP[21] (RS323IntA) */ + /* BClkIn */ + /* REQ1[1:0] GNT1[1:0] */ +#endif + +#if 0 /* Wrong?? NTL */ +# define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ + /* GPP[27:26] Int[1:0] */ +#else +# define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ + /* GPP[29] (PCI1Int) */ + /* BClkOut0 */ + /* GPP[27] (PCI0Int) */ + /* GPP[26] (RtcInt or PCI1Int) */ + /* CPUInt[25:24] */ +#endif + +#define CFG_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */ + +#if 0 /* Wrong?? - NTL */ +# define CFG_GPP_LEVEL_CONTROL 0x000002c6 +#else +# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ + /* gpp[29] */ + /* gpp[27:26] */ + /* gpp[22:21] */ + +# define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ + /* idmas use buffer 1,1 + comm use buffer 0 + pci use buffer 1,1 + cpu use buffer 0 + normal load (see also ifdef HVL) + standard SDRAM (see also ifdef REG) + non staggered refresh */ + /* 31:26 25 23 20 19 18 16 */ + /* 110110 00 111 0 0 00 1 */ + /* refresh_count=0x200 + phisical interleaving disable + virtual interleaving enable */ + /* 15 14 13:0 */ + /* 1 0 0x200 */ +#endif + +#if 0 +#define CFG_DUART_IO CFG_DEV2_SPACE +#define CFG_DUART_CHAN 1 /* channel to use for console */ +#endif +#undef CFG_INIT_CHAN1 +#undef CFG_INIT_CHAN2 +#if 0 +#define SRAM_BASE CFG_DEV0_SPACE +#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ +#endif + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ + +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* PCI MEMORY MAP section */ +#define CFG_PCI0_MEM_BASE 0x80000000 +#define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) + +#define CFG_PCI1_MEM_BASE 0x88000000 +#define CFG_PCI1_MEM_SIZE _128M +#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) + +/* PCI I/O MAP section */ +#define CFG_PCI0_IO_BASE 0xfa000000 +#define CFG_PCI0_IO_SIZE _16M +#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) +#define CFG_PCI0_IO_SPACE_PCI 0x00000000 + +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M +#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) +#define CFG_PCI1_IO_SPACE_PCI 0x00000000 + +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITE_THRU not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT0U CFG_IBAT0U + +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI0, PCI1 in one BAT */ +#define CFG_IBAT2L BATL_NO_ACCESS +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* GT regs, bootrom, all the devices, PCI I/O */ +#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* I2C speed and slave address (for compatability) defaults */ +#define CFG_I2C_SPEED 400000 +#define CFG_I2C_SLAVE 0x7F + +/* I2C addresses for the two DIMM SPD chips */ +#ifndef CONFIG_EVB64260_750CX +#define DIMM0_I2C_ADDR 0x56 +#define DIMM1_I2C_ADDR 0x54 +#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ +#define DIMM0_I2C_ADDR 0x54 +#define DIMM1_I2C_ADDR 0x54 +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_EXTRA_FLASH_DEVICE BOOT_DEVICE +#define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */ +#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_CFI 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR 0xFFFE0000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/74xx_7xx.h for the defines used here + */ + +#define CFG_L2 + +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) + +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_BOARD_ASM_INIT 1 + + +#endif /* __CONFIG_H */ diff --git a/include/configs/PATI.h b/include/configs/PATI.h new file mode 100644 index 0000000..d88fff3 --- /dev/null +++ b/include/configs/PATI.h @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2003 + * Denis Peter d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, + */ + +/* + * File: PATI.h + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ +#define CONFIG_PATI 1 /* ...On a PATI board */ +/* Serial Console Configuration */ +#define CONFIG_5xx_CONS_SCI1 +#undef CONFIG_5xx_CONS_SCI2 + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ + CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV | CFG_CMD_REGINFO | \ + CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP | \ + CFG_CMD_IMI | CFG_CMD_EEPROM | CFG_CMD_IRQ | CFG_CMD_MISC \ +) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "" /* autoboot command */ + +#define CONFIG_BOOTARGS "" /* */ + +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ + +/*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ + +#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ + +/* + * Miscellaneous configurable options + */ +#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ +#define CONFIG_PREBOOT + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00010000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } + + +/*********************************************************************** + * Last Stage Init + ***********************************************************************/ +#define CONFIG_LAST_STAGE_INIT + +/* + * Low Level Configuration Settings + */ + +/* + * Internal Memory Mapped (This is not the IMMR content) + */ +#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ + +/* + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ +#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ +/* + * Start addresses for the final memory configuration + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CFG_FLASH_BASE 0xffC00000 /* External flash */ +#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ +#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ +#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ + +#define CFG_MONITOR_BASE 0xFFF00000 +/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ + /* This adress is given to the linker with -Ttext to */ + /* locate the text section at this adress. */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + + +/*----------------------------------------------------------------------- + * FLASH organization + *----------------------------------------------------------------------- + * + */ + +#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ + + +#define CFG_ENV_IS_IN_EEPROM +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 2048 +#endif + +#undef CFG_ENV_IS_IN_FLASH +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ +#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ +#endif + + +#define CONFIG_SPI 1 +#define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ +#define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */ +#define CFG_SPI_CS_ACT 0x00 /* CS3 is active low */ +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * SW Watchdog freeze + */ +#undef CONFIG_WATCHDOG +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ + SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration + *----------------------------------------------------------------------- + * Data show cycle + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register + *----------------------------------------------------------------------- + * Set all bits to 40 Mhz + * + */ +#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ + + +#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) + +/*----------------------------------------------------------------------- + * UMCR - UIMB Module Configuration Register + *----------------------------------------------------------------------- + * + */ +#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ + +/*----------------------------------------------------------------------- + * ICTRL - I-Bus Support Control Register + */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ + +/*----------------------------------------------------------------------- + * USIU - Memory Controller Register + *----------------------------------------------------------------------- + */ +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) +#define CFG_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ +/* SDRAM */ +#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) +#define CFG_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ +/* PCI */ +#define CFG_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) +#define CFG_OR2_PRELIM (OR_ADDR_MK_FF) +/* config registers: */ +#define CFG_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) +#define CFG_OR3_PRELIM (0xffff0000) + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ + +/*----------------------------------------------------------------------- + * DER - Timer Decrementer + *----------------------------------------------------------------------- + * Initialise to zero + */ +#define CFG_DER 0x00000000 + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define VERSION_TAG "released" +#define CONFIG_ISO_STRING "MEV-10084-001" + +#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG + +#endif /* __CONFIG_H */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h new file mode 100644 index 0000000..9d5c4f4 --- /dev/null +++ b/include/configs/PCI405.h @@ -0,0 +1,355 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $" + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_PCI405 1 /* ...on a PCI405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ + +#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */ + +#undef CONFIG_BOOTARGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mem_linux=14336k\0" \ + "optargs=panic=0\0" \ + "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ + "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ + "" +#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */ +#undef CONFIG_PCI_PNP /* no pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */ +#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ + +#if 0 /* test-only */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#else +#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */ +#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFD0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */ + +#else /* Use EEPROM for environment variables */ + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ + /* total size of a CAT24WC08 is 1024 bytes */ +#endif + +#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (NVRAM/RTC) initialization */ +#define CFG_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ +#define CFG_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (CAN0, 1) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +/*#define CFG_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (FPGA internal) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ +#define CFG_FPGA_BASE_ADDR 0xF0400000 + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +/* FPGA internal regs */ +#define CFG_FPGA_MODE 0x00 +#define CFG_FPGA_STATUS 0x02 +#define CFG_FPGA_TS 0x04 +#define CFG_FPGA_TS_LOW 0x06 +#define CFG_FPGA_TS_CAP0 0x10 +#define CFG_FPGA_TS_CAP0_LOW 0x12 +#define CFG_FPGA_TS_CAP1 0x14 +#define CFG_FPGA_TS_CAP1_LOW 0x16 +#define CFG_FPGA_TS_CAP2 0x18 +#define CFG_FPGA_TS_CAP2_LOW 0x1a +#define CFG_FPGA_TS_CAP3 0x1c +#define CFG_FPGA_TS_CAP3_LOW 0x1e + +/* FPGA Mode Reg */ +#define CFG_FPGA_MODE_CF_RESET 0x0001 +#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 +#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 +#define CFG_FPGA_MODE_TS_CLEAR 0x2000 + +/* FPGA Status Reg */ +#define CFG_FPGA_STATUS_DIP0 0x0001 +#define CFG_FPGA_STATUS_DIP1 0x0002 +#define CFG_FPGA_STATUS_DIP2 0x0004 +#define CFG_FPGA_STATUS_FLASH 0x0008 +#define CFG_FPGA_STATUS_TS_IRQ 0x1000 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ +/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */ +#define CFG_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +#if 0 /* test-only */ +#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ +#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#else +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h new file mode 100644 index 0000000..3a7f7f0 --- /dev/null +++ b/include/configs/PCI5441.h @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*------------------------------------------------------------------------ + * BOARD/CPU + *----------------------------------------------------------------------*/ +#define CONFIG_PCI5441 1 /* PCI-5441 board */ +#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ + +#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ +#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ +#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ + +/*------------------------------------------------------------------------ + * CACHE -- the following will support II/s and II/f. The II/s does not + * have dcache, so the cache instructions will behave as NOPs. + *----------------------------------------------------------------------*/ +#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ +#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ +#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ +#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ + +/*------------------------------------------------------------------------ + * MEMORY BASE ADDRESSES + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ +#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ + +/*------------------------------------------------------------------------ + * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above + * CFG_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if defined(CONFIG_CONSOLE_JTAG) +#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ +#else +#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */ +#endif + +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ + +/*------------------------------------------------------------------------ + * DEBUG + *----------------------------------------------------------------------*/ +#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ + +/*------------------------------------------------------------------------ + * TIMEBASE -- + * + * The high res timer defaults to 1 msec. Since it includes the period + * registers, we can slow it down to 10 msec using TMRCNT. If the default + * period is acceptable, TMRCNT can be left undefined. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ +#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ +#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) +#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* Provide extended help*/ +#define CFG_PROMPT "==> " /* Command prompt */ +#define CFG_CBSIZE 256 /* Console I/O buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ +#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ +#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ +#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h new file mode 100644 index 0000000..d03706e --- /dev/null +++ b/include/configs/PCIPPC2.h @@ -0,0 +1,267 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the PCIPPC-2 board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_PREBOOT "" +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_ELF | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) + +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 64 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_FLASH_MAX_SIZE 0x00100000 +/* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */ + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ + CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* Size in bytes reserved for initial data + */ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x8000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_INIT_RAM_LOCK + +/* + * Temporary buffer for serial data until the real serial driver + * is initialised (memtest will destroy this buffer) + */ +#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR +#define CFG_SCONSOLE_SIZE 0x0002000 + +/* SDRAM 0 - 256MB + */ +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (CFG_SDRAM_BASE | \ + BATU_BL_256M | BATU_VS | BATU_VP) +/* SDRAM 1 - 256MB + */ +#define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \ + BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \ + BATU_BL_256M | BATU_VS | BATU_VP) + +/* Init RAM in the CPU DCache (no backing memory) + */ +#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \ + BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \ + BATU_BL_128K | BATU_VS | BATU_VP) + +/* I/O and PCI memory at 0xf0000000 + */ +#define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT0L CFG_DBAT0L +#define CFG_IBAT0U CFG_DBAT0U +#define CFG_IBAT1L CFG_DBAT1L +#define CFG_IBAT1U CFG_DBAT1U +#define CFG_IBAT2L CFG_DBAT2L +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_IBAT3L CFG_DBAT3L +#define CFG_IBAT3U CFG_DBAT3U + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the PCIPPC2 user's manual. + */ +#define CFG_HZ 1000 +#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */ +#define CFG_CPU_CLK 300000000 +#define CFG_BUS_CLK 100000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +/* + * Note: environment is not EMBEDDED in the U-Boot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_SIZE 0x1000 /* Size of the Environment */ +#define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * L2 cache + */ +#undef CFG_L2 +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * Disk-On-Chip configuration + */ + +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#undef CFG_DOC_SUPPORT_MILLENNIUM + +/*----------------------------------------------------------------------- + RTC m48t59 +*/ +#define CONFIG_RTC_MK48T59 + +#define CONFIG_WATCHDOG + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_TULIP + +#endif /* __CONFIG_H */ diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h new file mode 100644 index 0000000..92b2f7c --- /dev/null +++ b/include/configs/PCIPPC6.h @@ -0,0 +1,281 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the PCIPPC-6 board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_PREBOOT "" +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_ELF | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SCSI | \ + CFG_CMD_SNTP ) + + +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 64 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_FLASH_MAX_SIZE 0x00100000 +/* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */ + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ + CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* Size in bytes reserved for initial data + */ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x8000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_INIT_RAM_LOCK + +/* + * Temporary buffer for serial data until the real serial driver + * is initialised (memtest will destroy this buffer) + */ +#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR +#define CFG_SCONSOLE_SIZE 0x0002000 + +/* SDRAM 0 - 256MB + */ +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (CFG_SDRAM_BASE | \ + BATU_BL_256M | BATU_VS | BATU_VP) +/* SDRAM 1 - 256MB + */ +#define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \ + BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \ + BATU_BL_256M | BATU_VS | BATU_VP) + +/* Init RAM in the CPU DCache (no backing memory) + */ +#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \ + BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \ + BATU_BL_128K | BATU_VS | BATU_VP) + +/* I/O and PCI memory at 0xf0000000 + */ +#define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT0L CFG_DBAT0L +#define CFG_IBAT0U CFG_DBAT0U +#define CFG_IBAT1L CFG_DBAT1L +#define CFG_IBAT1U CFG_DBAT1U +#define CFG_IBAT2L CFG_DBAT2L +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_IBAT3L CFG_DBAT3L +#define CFG_IBAT3U CFG_DBAT3U + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the PCIPPC2 user's manual. + */ +#define CFG_HZ 1000 +#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */ +#define CFG_CPU_CLK 300000000 +#define CFG_BUS_CLK 100000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +/* + * Note: environment is not EMBEDDED in the U-Boot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_SIZE 0x1000 /* Size of the Environment */ +#define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * L2 cache + */ +#undef CFG_L2 +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * Disk-On-Chip configuration + */ + +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#undef CFG_DOC_SUPPORT_MILLENNIUM + +/*----------------------------------------------------------------------- + RTC m48t59 +*/ +#define CONFIG_RTC_MK48T59 + +#define CONFIG_WATCHDOG + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_TULIP + + +#define CONFIG_SCSI_SYM53C8XX +#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */ +#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ +#define CFG_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */ +#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ +#define CFG_SCSI_SPIN_UP_TIME 2 +#define CFG_SCSI_SCAN_BUS_REVERSE 0 +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION + +#endif /* __CONFIG_H */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h new file mode 100644 index 0000000..9668fb0 --- /dev/null +++ b/include/configs/PIP405.h @@ -0,0 +1,386 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*********************************************************** + * High Level Configuration Options + * (easy to change) + ***********************************************************/ +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_PIP405 1 /* ...on a PIP405 board */ +/*********************************************************** + * Clock + ***********************************************************/ +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +/*********************************************************** + * Command definitions + ***********************************************************/ +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_IDE | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_CACHE | \ + CFG_CMD_IRQ | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_REGINFO | \ + CFG_CMD_FDC | \ + CFG_CMD_SCSI | \ + CFG_CMD_FAT | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_USB | \ + CFG_CMD_MII | \ + CFG_CMD_SDRAM | \ + CFG_CMD_DOC | \ + CFG_CMD_PING | \ + CFG_CMD_SAVES | \ + CFG_CMD_BSP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +/************************************************************** + * I2C Stuff: + * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address + * 0x53. + * Caution: on the same bus is the SPD (Serial Presens Detect + * EEPROM of the SDRAM + * The Atmel EEPROM uses 16Bit addressing. + ***************************************************************/ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x53 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */ + +#undef CFG_I2C_EEPROM_ADDR_OVERFLOW +#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ + /* 64 byte page write mode using*/ + /* last 6 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + + +/*************************************************************** + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + ***************************************************************/ +#define SPD_EEPROM_ADDRESS 0x50 + +#define CONFIG_BOARD_EARLY_INIT_F +/************************************************************** + * Environment definitions + **************************************************************/ +#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ + + +#define CONFIG_BOOTDELAY 5 +/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ +/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ + + +#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ +#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ + +#define CONFIG_IPADDR 10.0.0.100 +#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_PREBOOT +/*************************************************************** + * defines if the console is stored in the environment + ***************************************************************/ +#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ +/*************************************************************** + * defines if an overwrite_console function exists + *************************************************************/ +#define CFG_CONSOLE_OVERWRITE_ROUTINE +#define CFG_CONSOLE_INFO_QUIET +/*************************************************************** + * defines if the overwrite_console should be stored in the + * environment + **************************************************************/ +#undef CFG_CONSOLE_ENV_OVERWRITE + +/************************************************************** + * loads config + *************************************************************/ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MISC_INIT_R +/*********************************************************** + * Miscellaneous configurable options + **********************************************************/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ + /* resource configuration */ +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + */ +#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ +#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF4000000 +#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in On Chip SRAM) + */ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR 0xF0000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*********************************************************************** + * External peripheral base address + ***********************************************************************/ +#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 + +/*********************************************************************** + * Last Stage Init + ***********************************************************************/ +#define CONFIG_LAST_STAGE_INIT +/************************************************************ + * Ethernet Stuff + ***********************************************************/ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */ +/************************************************************ + * RTC + ***********************************************************/ +#define CONFIG_RTC_MC146818 +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/************************************************************ + * IDE/ATA stuff + ************************************************************/ +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */ +#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ +#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ + +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET /* reset for ide supported... */ +#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ +#define CONFIG_SUPPORT_VFAT + +/************************************************************ + * ATAPI support (experimental) + ************************************************************/ +#define CONFIG_ATAPI /* enable ATAPI Support */ + +/************************************************************ + * SCSI support (experimental) only SYM53C8xx supported + ************************************************************/ +#define CONFIG_SCSI_SYM53C8XX +#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ +#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */ +#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ +#define CFG_SCSI_SPIN_UP_TIME 2 + +/************************************************************ + * Disk-On-Chip configuration + ************************************************************/ +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ +#define CFG_DOC_SHORT_TIMEOUT +#define CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM + +/************************************************************ + * DISK Partition support + ************************************************************/ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */ + +/************************************************************ + * Keyboard support + ************************************************************/ +#define CONFIG_ISA_KEYBOARD + +/************************************************************ + * Video support + ************************************************************/ +#define CONFIG_VIDEO /*To enable video controller support */ +#define CONFIG_VIDEO_CT69000 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ + +/************************************************************ + * USB support + ************************************************************/ +#define CONFIG_USB_UHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE + +/* Enable needed helper functions */ +#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ + +/************************************************************ + * Debug support + ************************************************************/ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/************************************************************ + * support BZIP2 compression + ************************************************************/ +#define CONFIG_BZIP2 1 + +/************************************************************ + * Ident + ************************************************************/ +#define VERSION_TAG "released" +#define CONFIG_ISO_STRING "MEV-10066-001" +#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG + + +#endif /* __CONFIG_H */ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h new file mode 100644 index 0000000..91e9518 --- /dev/null +++ b/include/configs/PK1C20.h @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*------------------------------------------------------------------------ + * BOARD/CPU + *----------------------------------------------------------------------*/ +#define CONFIG_PK1C20 1 /* PK1C20 board */ +#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ + +#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ +#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ +#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ + +/*------------------------------------------------------------------------ + * CACHE -- the following will support II/s and II/f. The II/s does not + * have dcache, so the cache instructions will behave as NOPs. + *----------------------------------------------------------------------*/ +#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ +#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ +#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ +#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ + +/*------------------------------------------------------------------------ + * MEMORY BASE ADDRESSES + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ +#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ +#define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */ +#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ + +/*------------------------------------------------------------------------ + * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above + * CFG_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if defined(CONFIG_CONSOLE_JTAG) +#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ +#else +#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */ +#endif + +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ + +/*------------------------------------------------------------------------ + * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for + * epcs device access is enabled. The base address is the epcs + * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. + * The register base is currently at offset 0x400 from the memory base. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */ + +/*------------------------------------------------------------------------ + * DEBUG + *----------------------------------------------------------------------*/ +#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ + +/*------------------------------------------------------------------------ + * TIMEBASE -- + * + * The high res timer defaults to 1 msec. Since it includes the period + * registers, we can slow it down to 10 msec using TMRCNT. If the default + * period is acceptable, TMRCNT can be left undefined. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ +#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ +#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) +#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) + +/*------------------------------------------------------------------------ + * STATUS LED -- Provides a simple blinking led. For Nios2 each board + * must implement its own led routines -- leds are, after all, + * board-specific, no? + *----------------------------------------------------------------------*/ +#define CFG_LEDPIO_ADDR 0x00920840 /* LED PIO base addr */ +#define CONFIG_STATUS_LED /* Enable status driver */ + +#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ +#define STATUS_LED_STATE 1 /* Blinking */ +#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ + +/*------------------------------------------------------------------------ + * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... + * and really doesn't need any additional clutter. So I choose the lazy + * way out to avoid changes there -- define the base address to ensure + * cache bypass so there's no need to monkey with inx/outx macros. + *----------------------------------------------------------------------*/ +#define CONFIG_SMC91111_BASE 0x80910300 /* Base addr (bypass) */ +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ + +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.2.21 +#define CONFIG_SERVERIP 192.168.2.16 + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include + +/*------------------------------------------------------------------------ + * COMPACT FLASH + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CONFIG_IDE_PREINIT /* Implement id_preinit */ +#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ +#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ +#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ +#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ +#define CFG_ATA_STRIDE 4 /* Width betwix addrs */ +#define CONFIG_DOS_PARTITION + +/* Board-specific cf regs */ +#define CFG_CF_PRESENT 0x00900880 /* CF Present PIO base */ +#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/ +#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ + +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ + +/*------------------------------------------------------------------------ + * JFFS2 + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS_CUSTOM_PART /* board defined part */ +#endif + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* Provide extended help*/ +#define CFG_PROMPT "==> " /* Command prompt */ +#define CFG_CBSIZE 256 /* Console I/O buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ +#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ +#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ +#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +#endif /* __CONFIG_H */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h new file mode 100644 index 0000000..54ecfa4 --- /dev/null +++ b/include/configs/PLU405.h @@ -0,0 +1,455 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_PLU405 1 /* ...on a PLU405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if 0 /* test-only */ +#define CONFIG_NET_MULTI 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY1_ADDR 1 /* PHY address */ +#else +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#endif +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_SUPPORT_VFAT + +#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ +#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +/* Only interrupt boot if space is pressed */ +/* If a long serial cable is connected but */ +/* other end is dead, garbage will be read */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_AUTOBOOT_STOP_STR " " + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) +# define CFG_RAMBOOT 1 +#else +# undef CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ +#if 1 /* test-only */ +/* CAT24WC08/16... */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#else +/* CAT24WC32/64... */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ +#endif +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define DUART0_BA 0xF0000400 /* DUART Base Address */ +#define DUART1_BA 0xF0000408 /* DUART Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ +#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * FPGA stuff + */ + +#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ + +/* FPGA internal regs */ +#define CFG_FPGA_CTRL 0x000 + +/* FPGA Control Reg */ +#define CFG_FPGA_CTRL_CF_RESET 0x0001 +#define CFG_FPGA_CTRL_WDI 0x0002 +#define CFG_FPGA_CTRL_PS2_RESET 0x0020 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555445 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xF7FE0014 + +#define CFG_DUART_RST (0x80000000 >> 14) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 1 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/PM520.h b/include/configs/PM520.h new file mode 100644 index 0000000..9f1dec8 --- /dev/null +++ b/include/configs/PM520.h @@ -0,0 +1,384 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5200 +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_PM520 1 /* ... on PM520 board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ + +#define CONFIG_MISC_INIT_R + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#undef CONFIG_NS8382X + +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MPC5100 */ + +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + +#endif + +/* Partitions */ +#define CONFIG_DOS_PARTITION + +/* USB */ +#if 1 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +#if defined(CONFIG_BOOT_ROM) +#define ADD_DOC_CMD 0 +#else +#define ADD_DOC_CMD CFG_CMD_DOC +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_DOC_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=pm520\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk30/ppc_82xx\0" \ + "bootfile=/tftpboot/PM520/uImage\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Disk-On-Chip configuration + */ + +#define CFG_DOC_SHORT_TIMEOUT +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM +#define CFG_DOC_BASE 0xE0000000 +#define CFG_DOC_SIZE 0x00100000 + +#if defined(CONFIG_BOOT_ROM) +/* + * Flash configuration (8,16 or 32 MB) + * TEXT base always at 0xFFF00000 + * ENV_ADDR always at 0xFFF40000 + * FLASH_BASE at 0xFC000000 for 32 MB + * 0xFD000000 for 16 MB + * 0xFD800000 for 8 MB + */ +#define CFG_FLASH_BASE 0xfc000000 +#define CFG_FLASH_SIZE 0x02000000 +#define CFG_BOOTROM_BASE 0xFFF00000 +#define CFG_BOOTROM_SIZE 0x00080000 +#define CFG_ENV_ADDR (0xFDF00000 + 0x40000) +#else +/* + * Flash configuration (8,16 or 32 MB) + * TEXT base always at 0xFFF00000 + * ENV_ADDR always at 0xFFF40000 + * FLASH_BASE at 0xFE000000 for 32 MB + * 0xFF000000 for 16 MB + * 0xFF800000 for 8 MB + */ +#define CFG_FLASH_BASE 0xfe000000 +#define CFG_FLASH_SIZE 0x02000000 +#define CFG_ENV_ADDR (0xFFF00000 + 0x40000) +#endif +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ + +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */ + + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x40000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x10000004 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#if defined(CONFIG_BOOT_ROM) +#define CFG_BOOTCS_START CFG_BOOTROM_BASE +#define CFG_BOOTCS_SIZE CFG_BOOTROM_SIZE +#define CFG_BOOTCS_CFG 0x00047800 +#define CFG_CS0_START CFG_BOOTROM_BASE +#define CFG_CS0_SIZE CFG_BOOTROM_SIZE +#define CFG_CS1_START CFG_FLASH_BASE +#define CFG_CS1_SIZE CFG_FLASH_SIZE +#define CFG_CS1_CFG 0x0004fb00 +#else +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x0004fb00 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE +#define CFG_CS1_START CFG_DOC_BASE +#define CFG_CS1_SIZE CFG_DOC_SIZE +#define CFG_CS1_CFG 0x00047800 +#endif + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00005000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#undef CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/PM826.h b/include/configs/PM826.h new file mode 100644 index 0000000..6e5e3bb --- /dev/null +++ b/include/configs/PM826.h @@ -0,0 +1,576 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef CFG_RAMBOOT + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ +#define CONFIG_PM826 1 /* ...on a PM8260 module */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xFE +/* + * Software (bit-bang) I2C driver configuration + */ +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + + +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ + +/* + * select ethernet configuration + * + * if CONFIG_ETHER_ON_SCC is selected, then + * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) + * - CONFIG_NET_MULTI must not be defined + * + * if CONFIG_ETHER_ON_FCC is selected, then + * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected + * - CONFIG_NET_MULTI must be defined + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#define CONFIG_NET_MULTI +#undef CONFIG_ETHER_NONE /* define if ether on something else */ + +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ + +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +/* + * - Rx-CLK is CLK11 + * - Tx-CLK is CLK10 + */ +#define CONFIG_ETHER_ON_FCC1 +# define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +#ifndef CONFIG_DB_CR826_J30x_ON +# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) +#else +# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) +#endif +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK14 + */ +#define CONFIG_ETHER_ON_FCC2 +# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +/* + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 64000000 /* in Hz */ + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 9600 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#ifdef CONFIG_PCI +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) +#else /* ! PCI */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#endif /* CONFIG_PCI */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Disk-On-Chip configuration + */ + +#define CFG_DOC_SHORT_TIMEOUT +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Flash and Boot ROM mapping + */ +#ifdef CONFIG_FLASH_32MB +#define CFG_FLASH0_BASE 0x40000000 +#define CFG_FLASH0_SIZE 0x02000000 +#else +#define CFG_FLASH0_BASE 0xFF000000 +#define CFG_FLASH0_SIZE 0x00800000 +#endif +#define CFG_BOOTROM_BASE 0xFF800000 +#define CFG_BOOTROM_SIZE 0x00080000 +#define CFG_DOC_BASE 0xFF800000 +#define CFG_DOC_SIZE 0x00100000 + +/* Flash bank size (for preliminary settings) + */ +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#ifdef CONFIG_FLASH_32MB +#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */ +#else +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ +#endif +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#if 0 +/* Start port with environment in flash; switch to EEPROM later */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) +#define CFG_ENV_SIZE 0x40000 +#define CFG_ENV_SECT_SIZE 0x40000 +#else +/* Final version: environment in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (2048 - 512) +#endif + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#if defined(CONFIG_BOOT_ROM) +#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) +#else +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) +#endif + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM + * is mapped at SDRAM_BASE2_PRELIM. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#ifdef CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ + HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ + +#define BCR_APD01 0x10000000 +#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#if 0 +#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) +#else +#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) +#endif + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#define CFG_SCCR (SCCR_DFBRG00) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 64 bit FLASH + * 1 60x SDRAM 64 bit SDRAM + * + */ + + /* Initialize SDRAM on local bus + */ +#define CFG_INIT_LOCAL_SDRAM + + +/* Minimum mask to separate preliminary + * address ranges for CS[0:2] + */ +#define CFG_MIN_AM_MASK 0xC0000000 + +/* + * we use the same values for 32 MB and 128 MB SDRAM + * refresh rate = 7.73 uS (64 MHz Bus Clock) + */ +#define CFG_MPTPR 0x2000 +#define CFG_PSRT 0x0E + +#define CFG_MRS_OFFS 0x00000000 + + +#if defined(CONFIG_BOOT_ROM) +/* + * Bank 0 - Boot ROM (8 bit wide) + */ +#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + +/* + * Bank 1 - Flash (64 bit wide) + */ +#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + +#else /* ! CONFIG_BOOT_ROM */ + +/* + * Bank 0 - Flash (64 bit wide) + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + +/* + * Bank 1 - Disk-On-Chip + */ +#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + +#endif /* CONFIG_BOOT_ROM */ + +/* Bank 2 - SDRAM + */ + +#ifndef CFG_RAMBOOT +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A10 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_1W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_1W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +#define CFG_OR2_PRELIM CFG_OR2_9COL +#define CFG_PSDMR CFG_PSDMR_9COL + +#endif /* CFG_RAMBOOT */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h new file mode 100644 index 0000000..982a1f8 --- /dev/null +++ b/include/configs/PM828.h @@ -0,0 +1,570 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef CFG_RAMBOOT + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ +#define CONFIG_PM828 1 /* ...on a PM828 module */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xFE +/* + * Software (bit-bang) I2C driver configuration + */ +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + + +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ + +/* + * select ethernet configuration + * + * if CONFIG_ETHER_ON_SCC is selected, then + * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) + * - CONFIG_NET_MULTI must not be defined + * + * if CONFIG_ETHER_ON_FCC is selected, then + * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected + * - CONFIG_NET_MULTI must be defined + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#define CONFIG_NET_MULTI +#undef CONFIG_ETHER_NONE /* define if ether on something else */ + +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ + +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +/* + * - Rx-CLK is CLK11 + * - Tx-CLK is CLK10 + */ +#define CONFIG_ETHER_ON_FCC1 +# define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +#ifndef CONFIG_DB_CR826_J30x_ON +# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) +#else +# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) +#endif +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK14 + */ +#define CONFIG_ETHER_ON_FCC2 +# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +/* + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 100000000 /* in Hz */ + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 9600 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#ifdef CONFIG_PCI +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) +#else /* ! PCI */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#endif /* CONFIG_PCI */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Disk-On-Chip configuration + */ + +#define CFG_DOC_SHORT_TIMEOUT +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Flash and Boot ROM mapping + */ + +#define CFG_BOOTROM_BASE 0xFF800000 +#define CFG_BOOTROM_SIZE 0x00080000 +#define CFG_FLASH0_BASE 0x40000000 +#define CFG_FLASH0_SIZE 0x02000000 +#define CFG_DOC_BASE 0xFF800000 +#define CFG_DOC_SIZE 0x00100000 + + +/* Flash bank size (for preliminary settings) + */ +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#if 0 +/* Start port with environment in flash; switch to EEPROM later */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) +#define CFG_ENV_SIZE 0x40000 +#define CFG_ENV_SECT_SIZE 0x40000 +#else +/* Final version: environment in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (2048 - 512) +#endif + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#if defined(CONFIG_BOOT_ROM) +#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) +#else +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) +#endif + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM + * is mapped at SDRAM_BASE2_PRELIM. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#ifdef CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ + HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ + +#define BCR_APD01 0x10000000 +#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#if 0 +#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) +#else +#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) +#endif + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#define CFG_SCCR (SCCR_DFBRG00) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 64 bit FLASH + * 1 60x SDRAM 64 bit SDRAM + * + */ + + /* Initialize SDRAM on local bus + */ +#define CFG_INIT_LOCAL_SDRAM + + +/* Minimum mask to separate preliminary + * address ranges for CS[0:2] + */ +#define CFG_MIN_AM_MASK 0xC0000000 + +/* + * we use the same values for 32 MB and 128 MB SDRAM + * refresh rate = 7.68 uS (100 MHz Bus Clock) + */ +#define CFG_MPTPR 0x2000 +#define CFG_PSRT 0x16 + +#define CFG_MRS_OFFS 0x00000000 + + +#if defined(CONFIG_BOOT_ROM) +/* + * Bank 0 - Boot ROM (8 bit wide) + */ +#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + +/* + * Bank 1 - Flash (64 bit wide) + */ +#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + +#else /* ! CONFIG_BOOT_ROM */ + +/* + * Bank 0 - Flash (64 bit wide) + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + +/* + * Bank 1 - Disk-On-Chip + */ +#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + +#endif /* CONFIG_BOOT_ROM */ + +/* Bank 2 - SDRAM + */ + +#ifndef CFG_RAMBOOT +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A10 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +#define CFG_OR2_PRELIM CFG_OR2_9COL +#define CFG_PSDMR CFG_PSDMR_9COL + +#endif /* CFG_RAMBOOT */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/PM854.h b/include/configs/PM854.h new file mode 100644 index 0000000..da01186 --- /dev/null +++ b/include/configs/PM854.h @@ -0,0 +1,440 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * pm854 board configuration file + * + * Please refer to doc/README.mpc85xx for more info. + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC8540 1 /* MPC8540 specific */ +#define CONFIG_PM854 1 /* PM854 board specific */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF + + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */ + +#else + /* + * Manually set up DDR parameters + */ + #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */ + #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ + #define CFG_DDR_CS0_CONFIG 0x80000102 + #define CFG_DDR_TIMING_1 0x47444321 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ + #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ + #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ + #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ +#endif + + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ + +#define CFG_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */ +#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */ + +#define CFG_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Local Bus Definitions + */ +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ + + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_EEPRO100 +#define CONFIG_E1000 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define CONFIG_MPC85XX_FEC 1 +#define CONFIG_MPC85XX_FEC_NAME "FEC" +#define FEC_PHY_ADDR 3 +#define FEC_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 + +#endif /* CONFIG_TSEC_ENET */ + + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_MII \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_LOOPW + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:40:42:01:00:00 +#define CONFIG_ETH1ADDR 00:40:42:01:00:01 +#define CONFIG_ETH2ADDR 00:40:42:01:00:02 +#endif + + +#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx +#define CONFIG_BOOTFILE pm854/uImage + +#define CONFIG_HOSTNAME pm854 +#define CONFIG_IPADDR 192.168.0.103 +#define CONFIG_SERVERIP 192.168.0.64 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=pm854/uRamdisk\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h new file mode 100644 index 0000000..4d83487 --- /dev/null +++ b/include/configs/PM856.h @@ -0,0 +1,443 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MicroSys PM856 board configuration file + * + * Please refer to doc/README.mpc85xx for more info. + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC8560 1 /* MPC8560 specific */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ +#define CONFIG_PM856 1 /* PM856 board specific */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF + + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */ + +#else + /* + * Manually set up DDR parameters + */ + #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */ + #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ + #define CFG_DDR_CS0_CONFIG 0x80000102 + #define CFG_DDR_TIMING_1 0x47444321 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ + #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ + #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ + #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ +#endif + + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ + +#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ +#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */ + +#define CFG_OR0_PRELIM 0xfe006f67 /* 32MB Flash */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * Local Bus Definitions + */ + +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ + + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#endif /* CONFIG_TSEC_ENET */ + +#define CONFIG_ETHPRIME "TSEC0" + +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ + + +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers + * - Full duplex + */ +#define CONFIG_ETHER_ON_FCC3 +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE) + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_LOOPW + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_ETHADDR 00:40:42:01:00:00 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:40:42:01:00:01 +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:40:42:01:00:02 +#endif + + +#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx +#define CONFIG_BOOTFILE pm856/uImage + +#define CONFIG_HOSTNAME pm856 +#define CONFIG_IPADDR 192.168.0.103 +#define CONFIG_SERVERIP 192.168.0.64 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=pm856/uRamdisk\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h new file mode 100644 index 0000000..8bcab0b --- /dev/null +++ b/include/configs/PMC405.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_PMC405 1 /* ...on a PMC405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_I2C | \ + CFG_CMD_PING | \ + CFG_CMD_UNIVERSE | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOOPW 1 /* enable loopw command */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MONITOR_BASE 0xFFFC0000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_INCREMENT 0x01000000 + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_PROTECTION 1 /* don't use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT } +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/* + * JFFS2 partitions - second bank contains u-boot + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0x01b00000 +#define CONFIG_JFFS2_PART_OFFSET 0x00400000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=pmc405-0" +#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)" +*/ + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ +#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ +#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define CF_BA 0xF0100000 /* CompactFlash Base Address */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 1 (Flash Bank 1) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 2 (CAN0, 1, RTC) initialization */ +#define CFG_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ +#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */ +#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ + +#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ + +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/PN62.h b/include/configs/PN62.h new file mode 100644 index 0000000..a717659 --- /dev/null +++ b/include/configs/PN62.h @@ -0,0 +1,304 @@ +/* + * (C) Copyright 2002 + * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8240 1 +#define CONFIG_PN62 1 + +#define CONFIG_CONS_INDEX 1 + + +#define REMOVE_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_LOADS | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMLS ) + +#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~REMOVE_COMMANDS) |\ + CFG_CMD_PCI |\ + CFG_CMD_BSP) + +#define CONFIG_BAUDRATE 19200 /* console baudrate */ + +#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_SERVERIP 10.0.0.201 +#define CONFIG_IPADDR 10.0.0.200 +#define CONFIG_ROOTPATH /opt/eldk/ppc_82xx +#define CONFIG_NETMASK 255.255.255.0 +#undef CONFIG_BOOTARGS +#if 0 +/* Boot Linux with NFS root filesystem */ +#define CONFIG_BOOTCOMMAND \ + "setenv verify y;" \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ + "loadp 100000; bootm" + /* "tftpboot 100000 uImage; bootm" */ +#else +/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ +#define CONFIG_BOOTCOMMAND \ + "setenv verify n;" \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "root=/dev/ram rw " \ + "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ + "loadp 200000; bootm" +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */ + +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ + +#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ + +/* + * PCI stuff + */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* we need Plug 'n Play */ +#if 0 +#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */ +#endif + +/* + * Networking stuff + */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ +#define CONFIG_PCNET_79C973 + +#define _IO_BASE 0xfe000000 /* points to PCI I/O space */ + + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x10000000 + +#define CFG_RESET_ADDRESS 0xfff00100 + +#undef CFG_RAMBOOT +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE TEXT_BASE + +/*#define CFG_GBL_DATA_SIZE 256*/ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + + +#define CFG_NO_FLASH 1 /* There is no FLASH memory */ + +#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ + +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */ + +/* + * Serial port configuration + */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 1843200 + +#define CFG_NS16550_COM1 0xff800008 +#define CFG_NS16550_COM2 0xff800000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 + +#define CFG_EUMB_ADDR 0xFCE00000 + +/* MCCR1 */ +#define CFG_ROMNAL 3 /* rom/flash next access time */ +#define CFG_ROMFAL 7 /* rom/flash access time */ + +/* MCCR2 */ +#define CFG_ASRISE 6 /* ASRISE in clocks */ +#define CFG_ASFALL 12 /* ASFALL in clocks */ +#define CFG_REFINT 5600 /* REFINT in clocks */ + +/* MCCR3 */ +#define CFG_BSTOPRE 0x3cf /* Burst To Precharge */ +#define CFG_REFREC 2 /* Refresh to activate interval */ +#define CFG_RDLAT 3 /* data latency from read command */ + +/* MCCR4 */ +#define CFG_PRETOACT 1 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 3 /* Activate to Precharge interval */ +#define CFG_ACTORW 2 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE Wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ +#define CFG_REGISTERD_TYPE_BUFFER 1 + +/* Memory bank settings: + * + * only bits 20-29 are actually used from these vales to set the + * start/qend address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x00000000 +#define CFG_BANK1_END 0x00000000 +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x00000000 +#define CFG_BANK2_END 0x00000000 +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x00000000 +#define CFG_BANK3_END 0x00000000 +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 + +/* + * Memory bank enable bitmask, specifying which of the banks defined above + * are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* PCI memory space */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h new file mode 100644 index 0000000..7ca827f --- /dev/null +++ b/include/configs/PPChameleonEVB.h @@ -0,0 +1,810 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2003 + * DAVE Srl + * + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * Credits: Stefan Roese, Wolfgang Denk + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ +#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ +#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ +#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL +#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA +#endif + + +/* Only one of the following two symbols must be defined (default is 25 MHz) + * CONFIG_PPCHAMELEON_CLK_25 + * CONFIG_PPCHAMELEON_CLK_33 + */ +#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) +#define CONFIG_PPCHAMELEON_CLK_25 +#endif + +#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) +#error "* Two external frequencies (SysClk) are defined! *" +#endif + +#undef CONFIG_PPCHAMELEON_SMI712 + +/* + * Debug stuff + */ +#undef __DEBUG_START_FROM_SRAM__ +#define __DISABLE_MACHINE_EXCEPTION__ + +#ifdef __DEBUG_START_FROM_SRAM__ +#define CFG_DUMMY_FLASH_SIZE 1024*1024*4 +#endif + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + + +#ifdef CONFIG_PPCHAMELEON_CLK_25 +# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ +#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) +# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#else +# error "* External frequency (SysClk) not defined! *" +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#undef CONFIG_BOOTARGS + +/* Ethernet stuff */ +#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ +#define CONFIG_ETHADDR 00:50:c2:1e:af:fe +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#undef CONFIG_EXT_PHY +#define CONFIG_NET_MULTI 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#ifndef CONFIG_EXT_PHY +#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ +#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ +#else +#define CONFIG_PHY_ADDR 2 /* PHY address */ +#endif +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 1900 + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_NAND0_BASE 0xFF400000 +#define CFG_NAND1_BASE 0xFF000000 + +#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ +#define SECTORSIZE 512 +#define NAND_NO_RB + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ +#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ +#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ +#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ + +#define NAND_DISABLE_CE(nand) do \ +{ \ + switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \ + break; \ + } \ +} while(0) + +#define NAND_ENABLE_CE(nand) do \ +{ \ + switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \ + break; \ + } \ +} while(0) + +#define NAND_CTL_CLRALE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \ + break; \ + } \ +} while(0) + +#define NAND_CTL_SETALE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \ + break; \ + } \ +} while(0) + +#define NAND_CTL_CLRCLE(nandptr) do \ +{ \ + switch((unsigned long)nandptr) \ + { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \ + break; \ + } \ +} while(0) + +#define NAND_CTL_SETCLE(nandptr) do { \ + switch((unsigned long)nandptr) { \ + case CFG_NAND0_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ + break; \ + case CFG_NAND1_BASE: \ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \ + break; \ + } \ +} while(0) + +#ifdef NAND_NO_RB +/* constant delay (see also tR in the datasheet) */ +#define NAND_WAIT_READY(nand) do { \ + udelay(12); \ +} while (0) +#else +/* use the R/B pin */ +/* TBD */ +#endif + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ + +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +/* Reserve 256 kB for Monitor */ +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) + +/* Reserve 320 kB for Monitor */ +/* +#define CFG_FLASH_BASE 0xFFFB0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (320 * 1024) +*/ + +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#ifdef ENVIRONMENT_IN_EEPROM + +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/ + +#else /* DEFAULT: environment in flash, using redundand flash sectors */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ +#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ +#define CFG_ENV_ADDR_REDUND 0xFFFFA000 +#define CFG_ENV_SIZE_REDUND 0x2000 + +#endif /* ENVIRONMENT_IN_EEPROM */ + + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (External SRAM) initialization */ +/* Since this must replace NOR Flash, we use the same settings for CS0 */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x92015480 +#define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x92015480 +#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ + +#ifdef CONFIG_PPCHAMELEON_SMI712 +/* + * Video console (graphic: SMI LynxEM) + */ +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SMI_LYNXEM +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_VIDEO_BMP_LOGO*/ +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ +#define CFG_ISA_IO 0xE8000000 +/* see also drivers/videomodes.c */ +#define CFG_DEFAULT_VIDEO_MODE 0x303 +#endif + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +/* FPGA internal regs */ +#define CFG_FPGA_MODE 0x00 +#define CFG_FPGA_STATUS 0x02 +#define CFG_FPGA_TS 0x04 +#define CFG_FPGA_TS_LOW 0x06 +#define CFG_FPGA_TS_CAP0 0x10 +#define CFG_FPGA_TS_CAP0_LOW 0x12 +#define CFG_FPGA_TS_CAP1 0x14 +#define CFG_FPGA_TS_CAP1_LOW 0x16 +#define CFG_FPGA_TS_CAP2 0x18 +#define CFG_FPGA_TS_CAP2_LOW 0x1a +#define CFG_FPGA_TS_CAP3 0x1c +#define CFG_FPGA_TS_CAP3_LOW 0x1e + +/* FPGA Mode Reg */ +#define CFG_FPGA_MODE_CF_RESET 0x0001 +#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 +#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 +#define CFG_FPGA_MODE_TS_CLEAR 0x2000 + +/* FPGA Status Reg */ +#define CFG_FPGA_STATUS_DIP0 0x0001 +#define CFG_FPGA_STATUS_DIP1 0x0002 +#define CFG_FPGA_STATUS_DIP2 0x0004 +#define CFG_FPGA_STATUS_FLASH 0x0008 +#define CFG_FPGA_STATUS_TS_IRQ 0x1000 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30] - EMAC0 input + * GPIO0[31] - EMAC1 reject packet as output + */ +#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +/*#define CFG_GPIO0_ISR1L 0x15555445*/ +#define CFG_GPIO0_ISR1L 0x15555444 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xF7FF8014 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define CONFIG_NO_SERIAL_EEPROM + +/*--------------------------------------------------------------------*/ + +#ifdef CONFIG_NO_SERIAL_EEPROM + +/* +!----------------------------------------------------------------------- +! Defines for entry options. +! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that +! are plugged in the board will be utilized as non-ECC DIMMs. +!----------------------------------------------------------------------- +*/ +#undef AUTO_MEMORY_CONFIG +#define DIMM_READ_ADDR 0xAB +#define DIMM_WRITE_ADDR 0xAA + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +#ifdef CONFIG_PPCHAMELEON_CLK_25 +/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ +#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) + +/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ +#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#else +#error "* External frequency (SysClk) not defined! *" +#endif + +#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) +/* Model HI */ +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 +#define CFG_OPB_FREQ 55555555 +/* Model ME */ +#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 +#define CFG_OPB_FREQ 66666666 +#else +/* Model BA (default) */ +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 +#define CFG_OPB_FREQ 66666666 +#endif + +#endif /* CONFIG_NO_SERIAL_EEPROM */ + +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ + +/* + * JFFS2 partitions + */ + +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_SIZE 0x00400000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand" +*/ + +/* 256 kB U-boot image */ +/* +#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ + "1792k(user),256k(u-boot);" \ + "ppchameleonevb-nand:-(nand)" +*/ + +/* 320 kB U-boot image */ +/* +#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ + "1728k(user),320k(u-boot);" \ + "ppchameleonevb-nand:-(nand)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/QS823.h b/include/configs/QS823.h new file mode 100644 index 0000000..235bc48 --- /dev/null +++ b/include/configs/QS823.h @@ -0,0 +1,571 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2002 + * Simple Network Magic Corporation + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* various debug settings */ +#undef CFG_DEVICE_NULLDEV /* null device */ +#undef CONFIG_SILENT_CONSOLE /* silent console */ +#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ +#undef DEBUG /* debug output code */ +#undef DEBUG_FLASH /* debug flash code */ +#undef FLASH_DEBUG /* debug fash code */ +#undef DEBUG_ENV /* debug environment code */ + +#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ +#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_QS823 1 /* ...on a QS823 module */ +#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ + +/* Select the target clock speed */ +#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ +#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ +#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ +#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ +#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ + +#ifdef CONFIG_CLOCK_16MHZ +#define CONFIG_CLOCK_MULT 512 +#endif + +#ifdef CONFIG_CLOCK_33MHZ +#define CONFIG_CLOCK_MULT 1024 +#endif + +#ifdef CONFIG_CLOCK_50MHZ +#define CONFIG_CLOCK_MULT 1525 +#endif + +#ifdef CONFIG_CLOCK_66MHZ +#define CONFIG_CLOCK_MULT 2048 +#endif + +#ifdef CONFIG_CLOCK_80MHZ +#define CONFIG_CLOCK_MULT 2441 +#endif + +/* choose flash size, 4Mb or 8Mb */ +#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ +#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ + +#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ + +#undef CONFIG_8xx_CONS_SMC1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ + +/* Define default IP addresses */ +#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ +#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ + +/* message to say directly after booting */ +#define CONFIG_PREBOOT "echo '';" \ + "echo 'type:';" \ + "echo 'run boot_nfs to boot to NFS';" \ + "echo 'run boot_flash to boot to flash';" \ + "echo '';" \ + "echo 'run flash_rootfs to install a new rootfs';" \ + "echo 'run flash_env to clear the env sector';" \ + "echo 'run flash_rw to clear the rw fs';" \ + "echo 'run flash_uboot to install a new u-boot';" \ + "echo 'run flash_kernel to install a new kernel';" + +/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND "run boot_nfs" + +#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ + +/* Our flash filesystem looks like this + * + * 4Mb board: + * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) + * ffec 0000 - ffed ffff read-write filesystem (ext2) + * ffee 0000 - ffef ffff environment + * fff0 0000 - fff1 ffff u-boot + * fff2 0000 - ffff ffff linux kernel + * + * 8Mb board: + * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) + * ffec 0000 - ffed ffff read-write filesystem (ext2) + * ffee 0000 - ffef ffff environment + * fff0 0000 - fff1 ffff u-boot + * fff2 0000 - ffff ffff linux kernel + * + */ + +/* environment for 4Mb board */ +#ifdef CONFIG_FLASH_4MB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serial#=QS823\0" \ + "hostname=qs823\0" \ + "netdev=eth0\0" \ + "ethaddr=00:01:02:B4:36:56\0" \ + "rootpath=/exports/rootfs\0" \ + "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ + /* fill in variables */ \ + "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ + "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ + "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ + /* commands */ \ + "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ + "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ + /* reinstall flash parts */ \ + "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ + "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ + "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ + "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ + "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" +#endif /* CONFIG_FLASH_4MB */ + +/* environment for 8Mb board */ +#ifdef CONFIG_FLASH_8MB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serial#=QS823\0" \ + "hostname=qs823\0" \ + "netdev=eth0\0" \ + "ethaddr=00:01:02:B4:36:56\0" \ + "rootpath=/exports/rootfs\0" \ + "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ + /* fill in variables */ \ + "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ + "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ + "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ + /* commands */ \ + "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ + "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ + /* reinstall flash parts */ \ + "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ + "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ + "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ + "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ + "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" +#endif /* CONFIG_FLASH_8MB */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_STATUS_LED /* Status LED disabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_DATE | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_RUN) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------- + * Environment variable storage is in FLASH, one sector before U-boot + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ +#define CFG_ENV_SIZE 0x2000 /* 8kb */ +#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ + +#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ +#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * TODO flash parameters + * FLASH organization for Intel Strataflash + */ +#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ + +#ifdef CONFIG_WATCHDOG +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + */ + +/* MF (Multiplication Factor of SPLL) */ +/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */ +#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) +#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + */ +#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) +#define CFG_BRGCLK_PRESCALE 1 +#endif + +#if defined(CONFIG_CLOCK_66MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) +#define CFG_BRGCLK_PRESCALE 4 +#endif + +#if defined(CONFIG_CLOCK_80MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) +#define CFG_BRGCLK_PRESCALE 4 +#endif + +#define SCCR_MASK CFG_SCCR + +/*----------------------------------------------------------------------- + * Debug Enable Register + * 0x73E67C0F - All interrupts handled by BDM + * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM + *----------------------------------------------------------------------- +#define CFG_DER 0x73E67C0F +#define CFG_DER 0x0082400F + + #------------------------------------------------------------------------- + # Program the Debug Enable Register (DER). This register provides the user + # with the reason for entering into the debug mode. We want all conditions + # to end up as an exception. We don't want to enter into debug mode for + # any condition. See the back of of the Development Support section of the + # MPC860 User Manual for a description of this register. + #------------------------------------------------------------------------- +*/ +#define CFG_DER 0 + +/*----------------------------------------------------------------------- + * Memory Controller Initialization Constants + *----------------------------------------------------------------------- + */ + +/* + * BR0 and OR0 (AMD dual FLASH devices) + * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) + */ +#define CFG_PRELIM_OR_AM +#define CFG_OR_TIMING_FLASH + +/* + *----------------------------------------------------------------------- + * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) + * flash that resides on the QS823. + *----------------------------------------------------------------------- + */ + +/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ +/* represents a minumum 32K block size. */ +#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) +#define CFG_BR0_PRELIM (vBR0_BA | BR_V) + +/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ +/* which defines a 8 Mbyte memory block. */ +#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) + +#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) +/* 0101 = Add a 5 clock cycle wait state */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) +#endif + +#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) +/* 0011 = Add a 3 clock cycle wait state */ +/* 29.8ns clock * (3 + 2) = 149ns cycle time */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) +#endif + +#if defined(CONFIG_CLOCK_16MHZ) +/* 0010 = Add a 2 clock cycle wait state */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) +#endif + +/* + * BR1 and OR1 (SDRAM) + * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) + * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) + * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) + * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) + */ + +#define SDRAM_BASE 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ + +/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which + * represents a 128 Mbyte block the DRAM in + * this address base. + */ +#define vOR1_AM ((0xF800 << 16) + (0 << 15)) +#define vBR1_BA ((0x0000 << 16) + (0 << 15)) +#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) +#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) + +/* Machine A Mode Register */ + +/* PTA Periodic Timer A */ + +#if defined(CONFIG_CLOCK_80MHZ) +#define vMAMR_PTA (19 << 24) +#endif + +#if defined(CONFIG_CLOCK_66MHZ) +#define vMAMR_PTA (16 << 24) +#endif + +#if defined(CONFIG_CLOCK_50MHZ) +#define vMAMR_PTA (195 << 24) +#endif + +#if defined(CONFIG_CLOCK_33MHZ) +#define vMAMR_PTA (131 << 24) +#endif + +#if defined(CONFIG_CLOCK_16MHZ) +#define vMAMR_PTA (65 << 24) +#endif + +/* For boards with 16M of SDRAM */ +#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* For boards with 32M of SDRAM */ +#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* Memory Periodic Timer Prescaler Register */ + +#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) +/* Divide by 32 */ +#define CFG_MPTPR 0x02 +#endif + +#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) +/* Divide by 16 */ +#define CFG_MPTPR 0x04 +#endif + +/* + * BR2 and OR2 (Unused) + * Base address = 0xF020_0000 - 0xF020_0FFF + * + */ +#define CFG_OR2_PRELIM 0xFFF00000 +#define CFG_BR2_PRELIM 0xF0200000 + +/* + * BR3 and OR3 (External Bus CS3) + * Base address = 0xF030_0000 - 0xF030_0FFF + * + */ +#define CFG_OR3_PRELIM 0xFFF00000 +#define CFG_BR3_PRELIM 0xF0300000 + +/* + * BR4 and OR4 (External Bus CS3) + * Base address = 0xF040_0000 - 0xF040_0FFF + * + */ +#define CFG_OR4_PRELIM 0xFFF00000 +#define CFG_BR4_PRELIM 0xF0400000 + + +/* + * BR4 and OR4 (External Bus CS3) + * Base address = 0xF050_0000 - 0xF050_0FFF + * + */ +#define CFG_OR5_PRELIM 0xFFF00000 +#define CFG_BR5_PRELIM 0xF0500000 + +/* + * BR6 and OR6 (Unused) + * Base address = 0xF060_0000 - 0xF060_0FFF + * + */ +#define CFG_OR6_PRELIM 0xFFF00000 +#define CFG_BR6_PRELIM 0xF0600000 + +/* + * BR7 and OR7 (Unused) + * Base address = 0xF070_0000 - 0xF070_0FFF + * + */ +#define CFG_OR7_PRELIM 0xFFF00000 +#define CFG_BR7_PRELIM 0xF0700000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Sanity checks + */ +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/QS850.h b/include/configs/QS850.h new file mode 100644 index 0000000..967582b --- /dev/null +++ b/include/configs/QS850.h @@ -0,0 +1,571 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2002 + * Simple Network Magic Corporation + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* various debug settings */ +#undef CFG_DEVICE_NULLDEV /* null device */ +#undef CONFIG_SILENT_CONSOLE /* silent console */ +#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ +#undef DEBUG /* debug output code */ +#undef DEBUG_FLASH /* debug flash code */ +#undef FLASH_DEBUG /* debug fash code */ +#undef DEBUG_ENV /* debug environment code */ + +#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ +#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_QS850 1 /* ...on a QS850 module */ +#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ + +/* Select the target clock speed */ +#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ +#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ +#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ +#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ +#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ + +#ifdef CONFIG_CLOCK_16MHZ +#define CONFIG_CLOCK_MULT 512 +#endif + +#ifdef CONFIG_CLOCK_33MHZ +#define CONFIG_CLOCK_MULT 1024 +#endif + +#ifdef CONFIG_CLOCK_50MHZ +#define CONFIG_CLOCK_MULT 1525 +#endif + +#ifdef CONFIG_CLOCK_66MHZ +#define CONFIG_CLOCK_MULT 2048 +#endif + +#ifdef CONFIG_CLOCK_80MHZ +#define CONFIG_CLOCK_MULT 2441 +#endif + +/* choose flash size, 4Mb or 8Mb */ +#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ +#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ + +#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ + +/* Define default IP addresses */ +#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ +#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ + +/* message to say directly after booting */ +#define CONFIG_PREBOOT "echo '';" \ + "echo 'type:';" \ + "echo 'run boot_nfs to boot to NFS';" \ + "echo 'run boot_flash to boot to flash';" \ + "echo '';" \ + "echo 'run flash_rootfs to install a new rootfs';" \ + "echo 'run flash_env to clear the env sector';" \ + "echo 'run flash_rw to clear the rw fs';" \ + "echo 'run flash_uboot to install a new u-boot';" \ + "echo 'run flash_kernel to install a new kernel';" + +/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND "run boot_nfs" + +#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ + +/* Our flash filesystem looks like this + * + * 4Mb board: + * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) + * ffec 0000 - ffed ffff read-write filesystem (ext2) + * ffee 0000 - ffef ffff environment + * fff0 0000 - fff1 ffff u-boot + * fff2 0000 - ffff ffff linux kernel + * + * 8Mb board: + * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) + * ffec 0000 - ffed ffff read-write filesystem (ext2) + * ffee 0000 - ffef ffff environment + * fff0 0000 - fff1 ffff u-boot + * fff2 0000 - ffff ffff linux kernel + * + */ + +/* environment for 4Mb board */ +#ifdef CONFIG_FLASH_4MB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serial#=QS850\0" \ + "hostname=qs850\0" \ + "netdev=eth0\0" \ + "ethaddr=00:01:02:B4:36:56\0" \ + "rootpath=/exports/rootfs\0" \ + "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ + /* fill in variables */ \ + "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ + "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ + "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ + /* commands */ \ + "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ + "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ + /* reinstall flash parts */ \ + "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ + "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ + "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ + "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ + "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" +#endif /* CONFIG_FLASH_4MB */ + +/* environment for 8Mb board */ +#ifdef CONFIG_FLASH_8MB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serial#=QS850\0" \ + "hostname=qs850\0" \ + "netdev=eth0\0" \ + "ethaddr=00:01:02:B4:36:56\0" \ + "rootpath=/exports/rootfs\0" \ + "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ + /* fill in variables */ \ + "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ + "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ + "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ + /* commands */ \ + "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ + "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ + /* reinstall flash parts */ \ + "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ + "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ + "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ + "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ + "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" +#endif /* CONFIG_FLASH_8MB */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_STATUS_LED /* Status LED disabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_DATE | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_RUN) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------- + * Environment variable storage is in FLASH, one sector before U-boot + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ +#define CFG_ENV_SIZE 0x2000 /* 8kb */ +#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ + +#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ +#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * TODO flash parameters + * FLASH organization for Intel Strataflash + */ +#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ + +#ifdef CONFIG_WATCHDOG +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + */ + +/* MF (Multiplication Factor of SPLL) */ +/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */ +#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) +#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + */ +#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) +#define CFG_BRGCLK_PRESCALE 1 +#endif + +#if defined(CONFIG_CLOCK_66MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) +#define CFG_BRGCLK_PRESCALE 4 +#endif + +#if defined(CONFIG_CLOCK_80MHZ) +#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) +#define CFG_BRGCLK_PRESCALE 4 +#endif + +#define SCCR_MASK CFG_SCCR + +/*----------------------------------------------------------------------- + * Debug Enable Register + * 0x73E67C0F - All interrupts handled by BDM + * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM + *----------------------------------------------------------------------- +#define CFG_DER 0x73E67C0F +#define CFG_DER 0x0082400F + + #------------------------------------------------------------------------- + # Program the Debug Enable Register (DER). This register provides the user + # with the reason for entering into the debug mode. We want all conditions + # to end up as an exception. We don't want to enter into debug mode for + # any condition. See the back of of the Development Support section of the + # MPC860 User Manual for a description of this register. + #------------------------------------------------------------------------- +*/ +#define CFG_DER 0 + +/*----------------------------------------------------------------------- + * Memory Controller Initialization Constants + *----------------------------------------------------------------------- + */ + +/* + * BR0 and OR0 (AMD dual FLASH devices) + * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) + */ +#define CFG_PRELIM_OR_AM +#define CFG_OR_TIMING_FLASH + +/* + *----------------------------------------------------------------------- + * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) + * flash that resides on the QS850. + *----------------------------------------------------------------------- + */ + +/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ +/* represents a minumum 32K block size. */ +#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) +#define CFG_BR0_PRELIM (vBR0_BA | BR_V) + +/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ +/* which defines a 8 Mbyte memory block. */ +#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) + +#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) +/* 0101 = Add a 5 clock cycle wait state */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) +#endif + +#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) +/* 0011 = Add a 3 clock cycle wait state */ +/* 29.8ns clock * (3 + 2) = 149ns cycle time */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) +#endif + +#if defined(CONFIG_CLOCK_16MHZ) +/* 0010 = Add a 2 clock cycle wait state */ +#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) +#endif + +/* + * BR1 and OR1 (SDRAM) + * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) + * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) + * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) + * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) + */ + +#define SDRAM_BASE 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ + +/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which + * represents a 128 Mbyte block the DRAM in + * this address base. + */ +#define vOR1_AM ((0xF800 << 16) + (0 << 15)) +#define vBR1_BA ((0x0000 << 16) + (0 << 15)) +#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) +#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) + +/* Machine A Mode Register */ + +/* PTA Periodic Timer A */ + +#if defined(CONFIG_CLOCK_80MHZ) +#define vMAMR_PTA (19 << 24) +#endif + +#if defined(CONFIG_CLOCK_66MHZ) +#define vMAMR_PTA (16 << 24) +#endif + +#if defined(CONFIG_CLOCK_50MHZ) +#define vMAMR_PTA (195 << 24) +#endif + +#if defined(CONFIG_CLOCK_33MHZ) +#define vMAMR_PTA (131 << 24) +#endif + +#if defined(CONFIG_CLOCK_16MHZ) +#define vMAMR_PTA (65 << 24) +#endif + +/* For boards with 16M of SDRAM */ +#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* For boards with 32M of SDRAM */ +#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* Memory Periodic Timer Prescaler Register */ + +#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) +/* Divide by 32 */ +#define CFG_MPTPR 0x02 +#endif + +#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) +/* Divide by 16 */ +#define CFG_MPTPR 0x04 +#endif + +/* + * BR2 and OR2 (Unused) + * Base address = 0xF020_0000 - 0xF020_0FFF + * + */ +#define CFG_OR2_PRELIM 0xFFF00000 +#define CFG_BR2_PRELIM 0xF0200000 + +/* + * BR3 and OR3 (External Bus CS3) + * Base address = 0xF030_0000 - 0xF030_0FFF + * + */ +#define CFG_OR3_PRELIM 0xFFF00000 +#define CFG_BR3_PRELIM 0xF0300000 + +/* + * BR4 and OR4 (External Bus CS3) + * Base address = 0xF040_0000 - 0xF040_0FFF + * + */ +#define CFG_OR4_PRELIM 0xFFF00000 +#define CFG_BR4_PRELIM 0xF0400000 + + +/* + * BR4 and OR4 (External Bus CS3) + * Base address = 0xF050_0000 - 0xF050_0FFF + * + */ +#define CFG_OR5_PRELIM 0xFFF00000 +#define CFG_BR5_PRELIM 0xF0500000 + +/* + * BR6 and OR6 (Unused) + * Base address = 0xF060_0000 - 0xF060_0FFF + * + */ +#define CFG_OR6_PRELIM 0xFFF00000 +#define CFG_BR6_PRELIM 0xF0600000 + +/* + * BR7 and OR7 (Unused) + * Base address = 0xF070_0000 - 0xF070_0FFF + * + */ +#define CFG_OR7_PRELIM 0xFFF00000 +#define CFG_BR7_PRELIM 0xF0700000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Sanity checks + */ +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h new file mode 100644 index 0000000..32faa61 --- /dev/null +++ b/include/configs/QS860T.h @@ -0,0 +1,410 @@ +/* + * (C) Copyright 2003 + * MuLogic B.V. + * + * (C) Copyright 2002 + * Simple Network Magic Corporation + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* various debug settings */ +#undef CFG_DEVICE_NULLDEV /* null device */ +#undef CONFIG_SILENT_CONSOLE /* silent console */ +#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ +#undef DEBUG /* debug output code */ +#undef DEBUG_FLASH /* debug flash code */ +#undef FLASH_DEBUG /* debug fash code */ +#undef DEBUG_ENV /* debug environment code */ + +#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ +#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ + + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_QS860T 1 /* ...on a QS860T module */ + +#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */ +#define CONFIG_MII +#define FEC_INTERRUPT SIU_LEVEL1 +#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */ +#define CFG_DISCOVER_PHY + +#undef CONFIG_8xx_CONS_SMC1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */ +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* Pass clocks to Linux 2.4.18 in Hz */ +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;" \ + "echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \ + "echo" + +#undef CONFIG_BOOTARGS +/* TODO compare against CADM860 */ +#define CONFIG_BOOTCOMMAND "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_STATUS_LED /* Status LED disabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_NET | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/* TODO */ +#if 0 +/* Look at these */ +CONFIG_IPADDR +CONFIG_SERVERIP +CONFIG_I2C +CONFIG_SPI +#endif + +/* + * Environment variable storage is in NVRAM + */ +#define CFG_ENV_IS_IN_NVRAM 1 +#define CFG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */ +#define CFG_ENV_ADDR 0xD100E000 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* TODO - size? */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF00000 + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* TODO flash parameters */ +/*----------------------------------------------------------------------- + * FLASH organization for Intel Strataflash + */ +#define CFG_FLASH_16BIT 1 /* 16-bit wide flash memory */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#undef CFG_ENV_IS_IN_FLASH + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI) +#else +#define CFG_SYPCR 0xFFFFFF88 +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR 0x00620000 + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + */ +#define CFG_TBSCR 0x00C3 + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + */ +#define CFG_PISCR 0x0082 + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + */ +#define CFG_PLPRCR 0x0090D000 + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR 0x02000000 + + +/*----------------------------------------------------------------------- + * Debug Enable Register + * 0x73E67C0F - All interrupts handled by BDM + * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM + *----------------------------------------------------------------------- +#define CFG_DER 0x73E67C0F +*/ +#define CFG_DER 0x0082400F + + +/*----------------------------------------------------------------------- + * Memory Controller Initialization Constants + *----------------------------------------------------------------------- + */ + +/* + * BR0 and OR0 (AMD 512K Socketed FLASH) + * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) + */ +#define CFG_PRELIM_OR_AM +#define CFG_OR_TIMING_FLASH + +#define FLASH_BASE0_PRELIM 0xFFF00001 +#define CFG_OR0_PRELIM 0xFFF80D42 +#define CFG_BR0_PRELIM 0xFFF00401 + + +/* + * BR1 and OR1 (Intel 8M StrataFLASH) + * Base address = 0xD000_0000 - 0xD07F_FFFF + */ + +#define FLASH_BASE1_PRELIM 0xD0000000 +#define CFG_OR1_PRELIM 0xFF800D42 +#define CFG_BR1_PRELIM 0xD0000801 +/* #define CFG_OR1 0xFF800D42 */ +/* #define CFG_BR1 0xD0000801 */ + + +/* + * BR2 and OR2 (SDRAM) + * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) + * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) + * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) + * + */ +#define SDRAM_BASE 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ + +/* SDRAM timing */ +#define SDRAM_TIMING 0x00000A00 + +/* For boards with 16M of SDRAM */ +#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ +#define CFG_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */ + +/* For boards with 64M of SDRAM */ +#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */ +/* TODO - determine real value */ +#define CFG_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */ + +#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING) +#define CFG_BR2 (SDRAM_BASE | 0x000000C1) + + +/* + * BR3 and OR3 (NVRAM, Sipex, NAND Flash) + * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM) + * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register) + * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register) + * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register) + * + */ + +#define CFG_OR3_PRELIM 0xFFC00DF6 +#define CFG_BR3_PRELIM 0xD1000401 +/* #define CFG_OR3 0xFFC00DF6 */ +/* #define CFG_BR3 0xD1000401 */ + + +/* + * BR4 and OR4 (Unused) + * Base address = 0xE000_0000 - 0xE3FF_FFFF + * + */ + +#define CFG_OR4_PRELIM 0xFF000000 +#define CFG_BR4_PRELIM 0xE0000000 +/* #define CFG_OR4 0xFF000000 */ +/* #define CFG_BR4 0xE0000000 */ + + +/* + * BR5 and OR5 (Expansion bus) + * Base address = 0xE400_0000 - 0xE7FF_FFFF + * + */ + +#define CFG_OR5_PRELIM 0xFF000000 +#define CFG_BR5_PRELIM 0xE4000000 +/* #define CFG_OR5 0xFF000000 */ +/* #define CFG_BR5 0xE4000000 */ + + +/* + * BR6 and OR6 (Expansion bus) + * Base address = 0xE800_0000 - 0xEBFF_FFFF + * + */ + +#define CFG_OR6_PRELIM 0xFF000000 +#define CFG_BR6_PRELIM 0xE8000000 +/* #define CFG_OR6 0xFF000000 */ +/* #define CFG_BR6 0xE8000000 */ + + +/* + * BR7 and OR7 (Expansion bus) + * Base address = 0xEC00_0000 - 0xEFFF_FFFF + * + */ + +#define CFG_OR7_PRELIM 0xFF000000 +#define CFG_BR7_PRELIM 0xE8000000 +/* #define CFG_OR7 0xFF000000 */ +/* #define CFG_BR7 0xE8000000 */ + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Sanity checks + */ +#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) +#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h new file mode 100644 index 0000000..82228c0 --- /dev/null +++ b/include/configs/R360MPI.h @@ -0,0 +1,476 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_R360MPI 1 + +#define CONFIG_LCD +#undef CONFIG_EDT32F10 +#define CONFIG_SHARP_LQ057Q3DC02 + +#define CONFIG_SPLASH_SCREEN + +#define MPC8XX_FACT 1 /* Multiply by 1 */ +#define MPC8XX_XIN 50000000 /* 50 MHz in */ +#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */ +#if 0 +#define CONFIG_BOOTDELAY 0 /* immediate boot */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#undef CONFIG_SCC1_ENET +#define CONFIG_SCC2_ENET + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ +#undef CONFIG_SORT_I2C /* To I2C with software support */ +#define CFG_I2C_SPEED 4700 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(50) + +#define CFG_I2C_LCD_ADDR 0x8 /* LCD Control */ +#define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */ +#define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_DEVICE_NULLDEV 1 /* we need the null device */ +#define CFG_CONSOLE_IS_IN_ENV 1 /* must set console from env */ + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * JFFS2 partitions + */ +/* No command line, one static partition + * use all the space starting at offset 3MB*/ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00300000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=r360-0" +#define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)" +*/ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ +#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ +#define CFG_PLPRCR \ + ( (5-1)< ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ +#if defined(CONFIG_80MHz) +#define CFG_MAMR_PTA 156 +#elif defined(CONFIG_66MHz) +#define CFG_MAMR_PTA 129 +#else /* 50 MHz */ +#define CFG_MAMR_PTA 98 +#endif /*CONFIG_??MHz */ + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h new file mode 100644 index 0000000..242c837 --- /dev/null +++ b/include/configs/RBC823.h @@ -0,0 +1,439 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Udi Finkelstein udif@udif.com + * For the RBC823 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_RBC823 1 /* ...on a RBC823 module */ + + +#if 0 +#define DEBUG 1 +#define CONFIG_LAST_STAGE_INIT +#endif +#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */ +#define CONFIG_LCD 1 /* use LCD controller ... */ +#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */ + +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_SMC1 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ +#if 1 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_8xx_GCLK_FREQ 48000000L + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#undef CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */ + +#define CONFIG_HARD_I2C +#define CFG_I2C_SPEED 40000 +#define CFG_I2C_SLAVE 0xfe +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_WRITE_BITS 4 +#define CFG_EEPROM_WRITE_DELAY_MS 10 + +#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ + ~CFG_CMD_BSP & \ + ~CFG_CMD_DATE & \ + ~CFG_CMD_DISPLAY& \ + ~CFG_CMD_DTT & \ + ~CFG_CMD_EXT2 & \ + ~CFG_CMD_FDC & \ + ~CFG_CMD_FDOS & \ + ~CFG_CMD_HWFLOW & \ + ~CFG_CMD_IDE & \ + ~CFG_CMD_IRQ & \ + ~CFG_CMD_JFFS2 & \ + ~CFG_CMD_MII & \ + ~CFG_CMD_MMC & \ + ~CFG_CMD_NAND & \ + ~CFG_CMD_PCI & \ + ~CFG_CMD_PCMCIA & \ + ~CFG_CMD_REISER & \ + ~CFG_CMD_SCSI & \ + ~CFG_CMD_SETGETDCR & \ + ~CFG_CMD_SNTP & \ + ~CFG_CMD_SPI & \ + ~CFG_CMD_UNIVERSE & \ + ~CFG_CMD_USB & \ + ~CFG_CMD_VFD & \ + ~CFG_CMD_XIMG ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x0100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF00000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +/* +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +*/ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + */ + +/* + * for 48 MHz, we use a 4 MHz clock * 12 + */ +#define CFG_PLPRCR \ + ( (12-1)< + +/* + * Miscellaneous configurable options + */ +#define CFG_RESET_ADDRESS 0x80000000 +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFA200000 + +/*----------------------------------------------------------------------------- + * I2C Configuration + *----------------------------------------------------------------------------- + */ +#define CONFIG_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0x34 + + +/* enable I2C and select the hardware/software driver */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00000010) +#define I2C_TRISTATE (iop->pdir &= ~0x00000010) +#define I2C_READ ((iop->pdat & 0x00000010) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ + else iop->pdat &= ~0x00000010 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ + else iop->pdat &= ~0x00000020 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + + +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0x34 +# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ +# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 + +#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE 0xFF000000 +/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#if 0 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x8000 +#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 +#define CFG_ENV_ADDR 0xfa000100 +#define CFG_ENV_SIZE 0x1000 +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWP) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_MLRC10) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/* #define CFG_DER 0x2002000F */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ +#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ + +/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) + +/* + * BR1 and OR1 (SDRAM) + * + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ +#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000E00 + +#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* RPXLITE mem setting */ +#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */ +#define CFG_OR3_PRELIM 0xff7f8970 +#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ +#define CFG_OR4_PRELIM 0xFFF80970 + +/* ECCX CS settings */ +#define SED13806_OR 0xFFC00108 /* - 4 Mo + - Burst inhibit + - external TA */ +#define SED13806_REG_ADDR 0xa0000000 +#define SED13806_ACCES 0x801 /* 16 bit access */ + + +/* Global definitions for the ECCX board */ +#define ECCX_CSR_ADDR (0xfac00000) +#define ECCX_CSR8_OFFSET (0x8) +#define ECCX_CSR11_OFFSET (0xB) +#define ECCX_CSR12_OFFSET (0xC) + +#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET) +#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET) +#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET) + + +#define REG_GPIO_CTRL 0x008 + +/* Definitions for CSR8 */ +#define ECCX_ENEPSON 0x80 /* Bit 0: + 0= disable and reset SED1386 + 1= enable SED1386 */ +/* Bit 1: 0= SED1386 in Big Endian mode */ +/* 1= SED1386 in little endian mode */ +#define ECCX_LE 0x40 +#define ECCX_BE 0x00 + +/* Bit 2,3: Selection */ +/* 00 = Disabled */ +/* 01 = CS2 is used for the SED1386 */ +/* 10 = CS5 is used for the SED1386 */ +/* 11 = reserved */ +#define ECCX_CS2 0x10 +#define ECCX_CS5 0x20 + +/* Definitions for CSR12 */ +#define ECCX_ID 0x02 +#define ECCX_860 0x01 + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 58 + +/* + * Refresh clock Prescalar + */ +#define CFG_MPTPR MPTPR_PTP_DIV8 + +/* + * MAMR settings for SDRAM + */ + +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ + MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ +/* Configuration variable added by yooth. */ +/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ + +/* + * BCSRx + * + * Board Status and Control Registers + * + */ + +#define BCSR0 0xFA400000 +#define BCSR1 0xFA400001 +#define BCSR2 0xFA400002 +#define BCSR3 0xFA400003 + +#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ +#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ +#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ +#define BCSR0_COLTEST 0x20 +#define BCSR0_ETHLPBK 0x40 +#define BCSR0_ETHEN 0x80 + +#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ +#define BCSR1_PCVCTL6 0x02 +#define BCSR1_PCVCTL5 0x04 +#define BCSR1_PCVCTL4 0x08 +#define BCSR1_IPB5SEL 0x10 + +#define BCSR2_MIIRST 0x80 +#define BCSR2_MIIPWRDWN 0x40 +#define BCSR2_MIICTL 0x08 + +#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ +#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ +#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ +#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ +#define BCSR3_D27 0x10 /* Dip Switch settings */ +#define BCSR3_D26 0x20 +#define BCSR3_D25 0x40 +#define BCSR3_D24 0x80 + + +/* + * Environment setting + */ + +/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */ +/* #define CONFIG_IPADDR 10.10.106.1 */ +/* #define CONFIG_SERVERIP 10.10.104.11 */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h new file mode 100644 index 0000000..6b65031 --- /dev/null +++ b/include/configs/RPXlite.h @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * U-Boot port on RPXlite board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define RPXLite_50MHz + +/* + * High Level Configuration Options + * (easy to change) + */ + +#undef CONFIG_MPC860 +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_RPXLITE 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFA200000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFC00000 +/*%%% #define CFG_FLASH_BASE 0xFFF00000 */ +#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE 0xFFF00000 +/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_MLRC10) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_SCCR (SCCR_COM11 | SCCR_TBS) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ +#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ + +/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) + +/* + * BR1 and OR1 (SDRAM) + * + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ +#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000E00 + +#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* RPXLITE mem setting */ +#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */ +#define CFG_OR3_PRELIM 0xFFFF8910 +#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ +#define CFG_OR4_PRELIM 0xFFFE0970 + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 58 + +/* + * Refresh clock Prescalar + */ +#define CFG_MPTPR MPTPR_PTP_DIV8 + +/* + * MAMR settings for SDRAM + */ + +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ + MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ +/* Configuration variable added by yooth. */ +/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ + +/* + * BCSRx + * + * Board Status and Control Registers + * + */ + +#define BCSR0 0xFA400000 +#define BCSR1 0xFA400001 +#define BCSR2 0xFA400002 +#define BCSR3 0xFA400003 + +#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ +#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ +#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ +#define BCSR0_COLTEST 0x20 +#define BCSR0_ETHLPBK 0x40 +#define BCSR0_ETHEN 0x80 + +#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ +#define BCSR1_PCVCTL6 0x02 +#define BCSR1_PCVCTL5 0x04 +#define BCSR1_PCVCTL4 0x08 +#define BCSR1_IPB5SEL 0x10 + +#define BCSR2_ENPA5HDR 0x08 /* USB Control */ +#define BCSR2_ENUSBCLK 0x10 +#define BCSR2_USBPWREN 0x20 +#define BCSR2_USBSPD 0x40 +#define BCSR2_USBSUSP 0x80 + +#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ +#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ +#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ +#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ +#define BCSR3_D27 0x10 /* Dip Switch settings */ +#define BCSR3_D26 0x20 +#define BCSR3_D25 0x40 +#define BCSR3_D24 0x80 + + +/* + * Environment setting + */ + +#define CONFIG_ETHADDR 00:10:EC:00:1D:0B +#define CONFIG_IPADDR 192.168.1.65 +#define CONFIG_SERVERIP 192.168.1.27 + +#endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h new file mode 100644 index 0000000..8cd7df1 --- /dev/null +++ b/include/configs/RPXlite_DW.h @@ -0,0 +1,450 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr + * U-BOOT port on RPXlite board + */ + +/* + * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn + * U-BOOT port on RPXlite DW version board--RPXlite_DW + * June 8 ,2004 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +/* #define DEBUG 1 */ +/* #ifdef DEPLOYMENT 1 */ + +#undef CONFIG_MPC860 +#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ +#define CONFIG_RPXLITE 1 /* RPXlite DW version board */ + +#ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ +#endif + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ + +#ifdef DEBUG +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ + +#ifdef DEPLOYMENT +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" +#define CONFIG_AUTOBOOT_STOP_STR "st" +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_RESET_TO_RETRY 1 +#define CONFIG_BOOT_RETRY_MIN 1 +#endif /* DEPLOYMENT */ +#endif /* DEBUG */ + +/* pre-boot commands */ +#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" + +#undef CONFIG_BOOTARGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "gatewayip=172.16.115.254\0" \ + "netmask=255.255.255.0\0" \ + "kernel_addr=ff040000\0" \ + "ramdisk_addr=ff200000\0" \ + "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \ + "${filesize};md ${kernel_addr};" \ + "echo kernel updating finished\0" \ + "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \ + "${filesize};md ff000000;" \ + "echo u-boot updating finished\0" \ + "eu=protect off 1:6;era 1:6;reset\0" \ + "lcd=setenv stdout lcd;setenv stdin lcd\0" \ + "ser=setenv stdout serial;setenv stdin serial\0" \ + "verify=no" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFA200000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 + +#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif + +#define CFG_MONITOR_BASE 0xFF000000 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_ADDR 0xFA000100 +#define CFG_ENV_SIZE 0x1000 +#else +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ +#endif /* CFG_ENV_IS_IN_NVRAM */ + +#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 32-bit 12-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif /* We can get SYPCR: 0xFFFF0689. */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 32-bit 12-30 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */ + +/*--------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 16-bit 12-16 + *--------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) +/* TBSCR: 0x00C3 [SAM] */ + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18 + *----------------------------------------------------------------------- + * [RTC enabled but not stopped on FRZ] + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */ + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 16-bit 12-23 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + * [Periodic timer enabled,Periodic timer interrupt disable. ] + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */ + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +/* up to 64 MHz we use a 1:2 clock */ +#if defined(RPXlite_64MHz) +#define CFG_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */ +#else +#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) +#endif + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 5-3 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */ +#if defined(RPXlite_64MHz) +#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ +#else +#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ +#endif + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ +#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */ +#define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask */ + +/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) + +/* + * BR1 and OR1 (SDRAM) + * + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ +#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000E00 +#define CFG_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK)) +#define CFG_OR1_PRELIM ( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* RPXlite mem setting */ +#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */ +#define CFG_OR3_PRELIM 0xFF7F8900 +#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ +#define CFG_OR4_PRELIM 0xFFFE0040 + +/* + * Memory Periodic Timer Prescaler + */ +/* periodic timer for refresh */ +#if defined(RPXlite_64MHz) +#define CFG_MAMR_PTA 32 +#else +#define CFG_MAMR_PTA 20 +#endif + +/* + * Refresh clock Prescalar + */ +#define CFG_MPTPR MPTPR_PTP_DIV2 + +/* + * MAMR settings for SDRAM + */ + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10) +/* CFG_MAMR_9COL:0x20904000 @ 64MHz */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ +/* Configuration variable added by yooth. */ +/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ +/* + * BCSRx + * + * Board Status and Control Registers + * + */ +#define BCSR0 0xFA400000 +#define BCSR1 0xFA400001 +#define BCSR2 0xFA400002 +#define BCSR3 0xFA400003 + +#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ +#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ +#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ +#define BCSR0_COLTEST 0x20 +#define BCSR0_ETHLPBK 0x40 +#define BCSR0_ETHEN 0x80 + +#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ +#define BCSR1_PCVCTL6 0x02 +#define BCSR1_PCVCTL5 0x04 +#define BCSR1_PCVCTL4 0x08 +#define BCSR1_IPB5SEL 0x10 + +#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */ +#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */ + +#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */ +#define BCSR2_ENBRG1 0x04 /* Added by SAM. */ + +#define BCSR2_ENPA5HDR 0x08 /* USB Control */ +#define BCSR2_ENUSBCLK 0x10 +#define BCSR2_USBPWREN 0x20 +#define BCSR2_USBSPD 0x40 +#define BCSR2_USBSUSP 0x80 + +#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */ +#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */ +#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */ +#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */ + +#define BCSR3_D27 0x10 /* Dip Switch settings */ +#define BCSR3_D26 0x20 +#define BCSR3_D25 0x40 +#define BCSR3_D24 0x80 + +/* + * Environment setting + */ +#define CONFIG_ETHADDR 00:10:EC:00:37:5B +#define CONFIG_IPADDR 172.16.115.7 +#define CONFIG_SERVERIP 172.16.115.6 +#define CONFIG_ROOTPATH /workspace/myfilesystem/target/ +#define CONFIG_BOOTFILE uImage.rpxusb + +#endif /* __CONFIG_H */ diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h new file mode 100644 index 0000000..6ae9403 --- /dev/null +++ b/include/configs/RPXsuper.h @@ -0,0 +1,504 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + + +/***************************************************************************** + * + * These settings must match the way _your_ board is set up + * + *****************************************************************************/ +/* for the AY-Revision which does not use the HRCW */ +#define CFG_DEFAULT_IMMR 0x00010000 + +/* What is the oscillator's (UX2) frequency in Hz? */ +#define CONFIG_8260_CLKIN (66 * 1000 * 1000) + +/* How is switch S2 set? We really only want the MODCK[1-3] bits, so + * only the 3 least significant bits are important. +*/ +#define CFG_SBC_S2 0x04 + +/* What should MODCK_H be? It is dependent on the oscillator + * frequency, MODCK[1-3], and desired CPM and core frequencies. + * Some example values (all frequencies are in MHz): + * + * MODCK_H MODCK[1-3] Osc CPM Core + * 0x2 0x2 33 133 133 + * 0x2 0x4 33 133 200 + * 0x5 0x5 66 133 133 + * 0x5 0x7 66 133 200 + */ +#define CFG_SBC_MODCK_H 0x06 + +#define CFG_SBC_BOOT_LOW 1 /* only for HRCW */ +#undef CFG_SBC_BOOT_LOW + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk + * The main FLASH is whichever is connected to *CS0. U-Boot expects + * this to be the SIMM. + */ +#define CFG_FLASH0_BASE 0x80000000 +#define CFG_FLASH0_SIZE 16 + +/* What should the base address of the secondary FLASH be and how big + * is it (in Mbytes)? The secondary FLASH is whichever is connected + * to *CS6. U-Boot expects this to be the on board FLASH. If you don't + * want it enabled, don't define these constants. + */ +#define CFG_FLASH1_BASE 0 +#define CFG_FLASH1_SIZE 0 +#undef CFG_FLASH1_BASE +#undef CFG_FLASH1_SIZE + +/* What should be the base address of SDRAM DIMM and how big is + * it (in Mbytes)? +*/ +#define CFG_SDRAM0_BASE 0x00000000 +#define CFG_SDRAM0_SIZE 64 + +/* What should be the base address of SDRAM DIMM and how big is + * it (in Mbytes)? +*/ +#define CFG_SDRAM1_BASE 0x04000000 +#define CFG_SDRAM1_SIZE 32 + +/* What should be the base address of the LEDs and switch S0? + * If you don't want them enabled, don't define this. + */ +#define CFG_LED_BASE 0x00000000 + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere. + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on neither */ +#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ +#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ + +#if ( CONFIG_ETHER_INDEX == 3 ) + +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK16 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Half Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +# define CFG_CPMFCR_RAMTYPE 0 +/*#define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ +# define CFG_FCC_PSMR 0 + +#else /* CONFIG_ETHER_INDEX */ +# error "on RPX Super ethernet must be FCC3" +#endif /* CONFIG_ETHER_INDEX */ + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + + +/* Define this to reserve an entire FLASH sector (256 KB) for + * environment variables. Otherwise, the environment will be + * put in the same sector as U-Boot, and changing variables + * will erase U-Boot temporarily + */ +#define CFG_ENV_IN_OWN_SECT + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* What should the console's baud rate be? */ +#define CONFIG_BAUDRATE 115200 + +/* Ethernet MAC address */ +#define CONFIG_ETHADDR 08:00:22:50:70:63 + +#define CONFIG_IPADDR 192.168.1.99 +#define CONFIG_SERVERIP 192.168.1.3 + +/* Set to a positive value to delay for running BOOTCOMMAND */ +#define CONFIG_BOOTDELAY -1 + +/* undef this to save memory */ +#define CFG_LONGHELP + +/* Monitor Command Prompt */ +#define CFG_PROMPT "=> " + +/* What U-Boot subsytems do you want enabled? */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ECHO | \ + CFG_CMD_I2C | \ + CFG_CMD_REGINFO & \ + ~CFG_CMD_KGDB ) + +/* Where do the internal registers live? */ +#define CFG_IMMR 0xF0000000 + +/* Where do the on board registers (CS4) live? */ +#define CFG_REGS_BASE 0xFA000000 + +/***************************************************************************** + * + * You should not have to modify any of the following settings + * + *****************************************************************************/ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) + +#define CFG_MAXARGS 8 /* max number of command args */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x04000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_SDRAM_BASE CFG_SDRAM0_BASE + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + */ +#if defined(CFG_SBC_BOOT_LOW) +# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) +#else +# define CFG_SBC_HRCW_BOOT_FLAGS (0) +#endif /* defined(CFG_SBC_BOOT_LOW) */ + +/* get the HRCW ISB field from CFG_IMMR */ +#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ + ((CFG_IMMR & 0x01000000) >> 7) |\ + ((CFG_IMMR & 0x00100000) >> 4) ) + +#define CFG_HRCW_MASTER (HRCW_BPS11 |\ + HRCW_DPPC11 |\ + CFG_SBC_HRCW_IMMR |\ + HRCW_MMR00 |\ + HRCW_LBPC11 |\ + HRCW_APPC10 |\ + HRCW_CS10PC00 |\ + (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\ + CFG_SBC_HRCW_BOOT_FLAGS) + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CFG_RAMBOOT is platform dependent. + */ +#define CFG_MONITOR_BASE (CFG_FLASH0_BASE + 0x00F00000) + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +#ifndef CFG_RAMBOOT +# define CFG_ENV_IS_IN_FLASH 1 + +# ifdef CFG_ENV_IN_OWN_SECT +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +# define CFG_ENV_SECT_SIZE 0x40000 +# else +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) +# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ +# endif /* CFG_ENV_IN_OWN_SECT */ +#else +# define CFG_ENV_IS_IN_NVRAM 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +# define CFG_ENV_SIZE 0x200 +#endif /* CFG_RAMBOOT */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (/*HID0_ICE |*/\ + /*HID0_DCE |*/\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) + +#define CFG_HID0_FINAL (/*HID0_ICE |*/\ + HID0_IFEM |\ + HID0_ABE |\ + HID0_EMCP) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register + *----------------------------------------------------------------------- + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR (BCR_EBM |\ + BCR_PLDP |\ + BCR_EAV |\ + BCR_NPQM0) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ + +#define CFG_SIUMCR (SIUMCR_L2CPC01 |\ + SIUMCR_APPC10 |\ + SIUMCR_CS10PC01) + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#define CFG_SYPCR (SYPCR_SWTC |\ + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP) + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC |\ + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS |\ + PISCR_PTF |\ + PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#define CFG_SCCR (SCCR_DFBRG01) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90) + * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60) + * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60) + * 3 unused + * 4 60x GPCM 8 bit Board Regs, LEDs, switches + * 5 unused + * 6 unused + * 7 unused + * 8 PCMCIA + * 9 unused + * 10 unused + * 11 unused +*/ + +/* Bank 0 - FLASH + * + */ +#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_DECC_NONE |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_6_CLK |\ + ORxG_EHTR) + +/* Bank 1 - SDRAM + * + */ +#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A8 |\ + ORxS_NUMR_12 |\ + ORxS_IBID) + +#define CFG_PSDMR 0x014DA412 +#define CFG_PSRT 0x79 + + +/* Bank 2 - SDRAM + * + */ +#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) + +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) + +#define CFG_LSDMR 0x0169A512 +#define CFG_LSRT 0x79 + +#define CFG_MPTPR (0x0800 & MPTPR_PTP_MSK) + +/* Bank 4 - On board registers + * + */ +#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR4_PRELIM (ORxG_AM_MSK |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h new file mode 100644 index 0000000..3885bcd --- /dev/null +++ b/include/configs/RRvision.h @@ -0,0 +1,466 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_RRVISION 1 /* ...on a RRvision board */ + +#define CONFIG_8xx_GCLK_FREQ 64000000 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "setenv stdout serial" + +#undef CONFIG_BOOTARGS +#define CONFIG_ETHADDR 00:50:C2:00:E0:70 +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_IPADDR 10.0.0.5 +#define CONFIG_SERVERIP 10.0.0.2 +#define CONFIG_NETMASK 255.0.0.0 +#define CONFIG_ROOTPATH /opt/eldk/ppc_8xx +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \ + ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "load=tftp 100000 /tftpboot/u-boot.bin\0" \ + "update=protect off 1:0-8;era 1:0-8;" \ + "cp.b 100000 40000000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ + "kernel_img=/tftpboot/uImage\0" \ + "kernel_load=tftp 200000 ${kernel_img}\0" \ + "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \ + "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" + + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_STATUS_LED /* disturbs display */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + + +#ifndef CONFIG_LCD +#define CONFIG_VIDEO 1 /* To enable the video initialization */ + +/* Video related */ +#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ +#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */ +#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */ +#endif + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ + +# define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */ +# define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + + +#define CONFIG_COMMANDS ( ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_DATE ) & \ + ~( CFG_CMD_PCMCIA | \ + CFG_CMD_IDE ) ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +/* timeout values are in ticks = ms */ +#define CFG_FLASH_ERASE_TOUT (120*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (1 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ + +/* for 64 MHz, we use a 16 MHz clock * 4 */ +#define CFG_PLPRCR ( (4-1)< ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ +#define CFG_MAMR_PTA 129 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h new file mode 100644 index 0000000..a170f29 --- /dev/null +++ b/include/configs/Rattler.h @@ -0,0 +1,290 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen + * + * U-Boot configuration for Analogue&Micro Rattler boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_MPC8248 +#define CPU_ID_STR "MPC8248" +#else +#define CONFIG_MPC8260 +#define CPU_ID_STR "MPC8250" +#endif /* CONFIG_MPC8248 */ + +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#define CONFIG_RATTLER /* Analogue&Micro Rattler board */ + +#undef DEBUG + +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ + +#ifdef CONFIG_ETHER_ON_FCC + +#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ + +#if (CONFIG_ETHER_INDEX == 1) + +/* - Rx clock is CLK11 + * - Tx clock is CLK10 + * - BDs/buffers on 60x bus + * - Full duplex + */ +#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#elif (CONFIG_ETHER_INDEX == 2) + +/* - Rx clock is CLK15 + * - Tx clock is CLK14 + * - BDs/buffers on 60x bus + * - Full duplex + */ +#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_INDEX */ + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 2 /* Port C */ +#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +#define MDIO_READ ((iop->pdat & 0x00400000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + +#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \ + else iop->pdat &= ~0x00800000 + +#define MIIDELAY udelay(1) + +#endif /* CONFIG_ETHER_ON_FCC */ + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 100000000 /* in Hz */ +#endif + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ + | CFG_CMD_IMMAP \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ + +#define CFG_DIRECT_FLASH_TFTP + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS +#define CFG_JFFS2_SORT_FRAGMENTS + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00100000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=rattler-0" +#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)" +*/ +#endif /* CFG_CMD_JFFS2 */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_ENV_IS_IN_FLASH + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#endif /* CFG_ENV_IS_IN_FLASH */ + +#define CFG_DEFAULT_IMMR 0xFF010000 + +#define CFG_IMMR 0xF0000000 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 32 +#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041) +#define CFG_SDRAM_OR 0xFE002EC0 + +#define CFG_BCSR 0xFC000000 + +/* Hard reset configuration word */ +#define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */ +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) + +#define CFG_HID2 0 + +#define CFG_SIUMCR 0x0E04C000 +#define CFG_SYPCR 0xFFFFFFC3 +#define CFG_BCR 0x00000000 +#define CFG_SCCR SCCR_DFBRG01 + +#define CFG_RMR RMR_CSRE +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) +#define CFG_RCCR 0 + +#define CFG_PSDMR 0x8249A452 +#define CFG_PSRT 0x1F +#define CFG_MPTPR 0x2000 + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001001) +#define CFG_OR0_PRELIM 0xFF001ED6 +#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801) +#define CFG_OR7_PRELIM 0xFFFF87F6 + +#define CFG_RESET_ADDRESS 0xC0000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h new file mode 100644 index 0000000..0451b20 --- /dev/null +++ b/include/configs/SBC8540.h @@ -0,0 +1,422 @@ +/* + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * (C) Copyright 2004 Wind River Systems Inc . + * Added support for Wind River SBC8540 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* mpc8560ads board configuration file */ +/* please refer to doc/README.mpc85xx for more info */ +/* make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if XXX +#define DEBUG /* General debug */ +#define ET_DEBUG +#endif +#define TSEC_DEBUG + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ + + +#define CONFIG_CPM2 1 /* has CPM2 */ + +#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ + +#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_PCI /* pci ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ + + +#define CONFIG_ENV_OVERWRITE + +/* Using Localbus SDRAM to emulate flash before we can program the flash, + * normally you need a flash-boot image(u-boot.bin), if so undef this. + */ +#undef CONFIG_RAM_AS_FLASH + +#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ + #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */ +#else + #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ +#endif + +/* below can be toggled for performance analysis. otherwise use default */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#undef CONFIG_BTB /* toggle branch predition */ +#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ + defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ + defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) +#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." +#endif + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ + +#if XXX + #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ +#else + #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ +#endif +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ +#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ + +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ + +#if defined(CONFIG_MPC85xx_REV1) + #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#if defined(CONFIG_RAM_AS_FLASH) + #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ + #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ + #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ + #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ +#else /* Boot from real Flash */ + #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ + #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ + #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ + #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ +#endif +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* local bus definitions */ +#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ +#define CFG_OR1_PRELIM 0xfc000ff7 + +#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ +#define CFG_OR2_PRELIM 0x00000000 + +#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ +#define CFG_OR3_PRELIM 0xfc000cc1 + +#if defined(CONFIG_RAM_AS_FLASH) + #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ +#else + #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ +#endif +#define CFG_OR4_PRELIM 0xfc000cc1 + +#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ +#if 1 + #define CFG_OR5_PRELIM 0xff000ff7 +#else + #define CFG_OR5_PRELIM 0xff0000f0 +#endif + +#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ +#define CFG_OR6_PRELIM 0xfc000ff7 +#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ +#define CFG_LBC_LBCR 0x00000000 +#define CFG_LBC_LSRT 0x20000000 +#define CFG_LBC_MRTPR 0x20000000 +#define CFG_LBC_LSDMR_1 0x2861b723 +#define CFG_LBC_LSDMR_2 0x0861b723 +#define CFG_LBC_LSDMR_3 0x0861b723 +#define CFG_LBC_LSDMR_4 0x1861b723 +#define CFG_LBC_LSDMR_5 0x4061b723 + +/* just hijack the MOT BCSR def for SBC8560 misc devices */ +#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) +/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ + +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#if 0 +#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ +#else +#define CFG_NS16550_CLK 264000000 /* get_bus_freq(0) */ +#endif + +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#if 0 +#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) +#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) +#else +/* SBC8540 uses internal COMM controller */ +#define CFG_NS16550_COM1 ((CFG_CCSRBAR & 0xfff00000)+0x00004500) +#define CFG_NS16550_COM2 ((CFG_CCSRBAR & 0xfff00000)+0x00004600) +#endif + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_PCI_MEM_BASE 0xC0000000 +#define CFG_PCI_MEM_PHYS 0xC0000000 +#define CFG_PCI_MEM_SIZE 0x10000000 + +#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ + +# define CONFIG_NET_MULTI 1 +# define CONFIG_MPC85xx_TSEC1 +# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" +# define CONFIG_MII 1 /* MII PHY management */ +# define TSEC1_PHY_ADDR 25 +# define TSEC1_PHYIDX 0 +/* Options are: TSEC0 */ +# define CONFIG_ETHPRIME "TSEC0" + + +#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ + + #undef CONFIG_ETHER_NONE /* define if ether on something else */ + #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ + #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + + #if (CONFIG_ETHER_INDEX == 2) + /* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers + * - Full duplex + */ + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CFG_CPMFCR_RAMTYPE 0 + #define CFG_FCC_PSMR (FCC_PSMR_FDE) + + #elif (CONFIG_ETHER_INDEX == 3) + /* need more definitions here for FE3 */ + #endif /* CONFIG_ETHER_INDEX */ + + #define CONFIG_MII /* MII PHY management */ + #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ + /* + * GPIO pins used for bit-banged MII communications + */ + #define MDIO_PORT 2 /* Port C */ + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) + #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) + #define MDIO_READ ((iop->pdat & 0x00400000) != 0) + + #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + + #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + + #define MIIDELAY udelay(1) + +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#if 0 +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION /* use hardware protection */ +#endif +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if 0 +/* XXX This doesn't work and I don't want to fix it */ +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) + #define CFG_RAMBOOT +#else + #undef CFG_RAMBOOT +#endif +#endif + +/* Environment */ +#if !defined(CFG_RAMBOOT) + #if defined(CONFIG_RAM_AS_FLASH) + #define CFG_ENV_IS_NOWHERE + #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) + #define CFG_ENV_SIZE 0x2000 + #else + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) + #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ + #endif +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" +/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ +#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" +#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV | \ + CFG_CMD_LOADS )) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*Note: change below for your network setting!!! */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a +# define CONFIG_HAS_ETH1 +# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b +# define CONFIG_HAS_ETH2 +# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c +#endif + +#define CONFIG_SERVERIP YourServerIP +#define CONFIG_IPADDR YourTargetIP +#define CONFIG_GATEWAYIP YourGatewayIP +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_HOSTNAME SBC8560 +#define CONFIG_ROOTPATH YourRootPath +#define CONFIG_BOOTFILE YourImageName + +#endif /* __CONFIG_H */ diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h new file mode 100644 index 0000000..8b46a17 --- /dev/null +++ b/include/configs/SBC8560.h @@ -0,0 +1,410 @@ +/* + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * (C) Copyright 2004 Wind River Systems Inc . + * Added support for Wind River SBC8560 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* mpc8560ads board configuration file */ +/* please refer to doc/README.mpc85xx for more info */ +/* make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if XXX +#define DEBUG /* General debug */ +#define ET_DEBUG +#endif +#define TSEC_DEBUG + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ + + +#define CONFIG_CPM2 1 /* has CPM2 */ +#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ + +#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_PCI /* pci ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ + + +#define CONFIG_ENV_OVERWRITE + +/* Using Localbus SDRAM to emulate flash before we can program the flash, + * normally you need a flash-boot image(u-boot.bin), if so undef this. + */ +#undef CONFIG_RAM_AS_FLASH + +#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ + #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ +#else + #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ +#endif + +/* below can be toggled for performance analysis. otherwise use default */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#undef CONFIG_BTB /* toggle branch predition */ +#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ + defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ + defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) +#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." +#endif + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ + +#if XXX + #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ +#else + #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ +#endif +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ +#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ + +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ + +#if defined(CONFIG_MPC85xx_REV1) + #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#if defined(CONFIG_RAM_AS_FLASH) + #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ + #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ + #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ + #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ +#else /* Boot from real Flash */ + #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ + #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ + #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ + #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ +#endif +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* local bus definitions */ +#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ +#define CFG_OR1_PRELIM 0xfc000ff7 + +#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ +#define CFG_OR2_PRELIM 0x00000000 + +#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ +#define CFG_OR3_PRELIM 0xfc000cc1 + +#if defined(CONFIG_RAM_AS_FLASH) + #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ +#else + #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ +#endif +#define CFG_OR4_PRELIM 0xfc000cc1 + +#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ +#if 1 + #define CFG_OR5_PRELIM 0xff000ff7 +#else + #define CFG_OR5_PRELIM 0xff0000f0 +#endif + +#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ +#define CFG_OR6_PRELIM 0xfc000ff7 +#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ +#define CFG_LBC_LBCR 0x00000000 +#define CFG_LBC_LSRT 0x20000000 +#define CFG_LBC_MRTPR 0x20000000 +#define CFG_LBC_LSDMR_1 0x2861b723 +#define CFG_LBC_LSDMR_2 0x0861b723 +#define CFG_LBC_LSDMR_3 0x0861b723 +#define CFG_LBC_LSDMR_4 0x1861b723 +#define CFG_LBC_LSDMR_5 0x4061b723 + +/* just hijack the MOT BCSR def for SBC8560 misc devices */ +#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) +/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ + +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) +#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_PCI_MEM_BASE 0xC0000000 +#define CFG_PCI_MEM_PHYS 0xC0000000 +#define CFG_PCI_MEM_SIZE 0x10000000 + +#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ + +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 /* MII PHY management */ +# define CONFIG_MPC85xx_TSEC1 +# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" +# define TSEC1_PHY_ADDR 25 +# define TSEC1_PHYIDX 0 +/* Options are: TSEC0 */ +# define CONFIG_ETHPRIME "TSEC0" + + +#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ + + #undef CONFIG_ETHER_NONE /* define if ether on something else */ + #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ + #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + + #if (CONFIG_ETHER_INDEX == 2) + /* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers + * - Full duplex + */ + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CFG_CPMFCR_RAMTYPE 0 + #define CFG_FCC_PSMR (FCC_PSMR_FDE) + + #elif (CONFIG_ETHER_INDEX == 3) + /* need more definitions here for FE3 */ + #endif /* CONFIG_ETHER_INDEX */ + + #define CONFIG_MII /* MII PHY management */ + #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ + /* + * GPIO pins used for bit-banged MII communications + */ + #define MDIO_PORT 2 /* Port C */ + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) + #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) + #define MDIO_READ ((iop->pdat & 0x00400000) != 0) + + #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + + #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + + #define MIIDELAY udelay(1) + +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#if 0 +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION /* use hardware protection */ +#endif +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if 0 +/* XXX This doesn't work and I don't want to fix it */ +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) + #define CFG_RAMBOOT +#else + #undef CFG_RAMBOOT +#endif +#endif + +/* Environment */ +#if !defined(CFG_RAMBOOT) + #if defined(CONFIG_RAM_AS_FLASH) + #define CFG_ENV_IS_NOWHERE + #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) + #define CFG_ENV_SIZE 0x2000 + #else + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) + #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ + #endif +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" +/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ +#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" +#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV | \ + CFG_CMD_LOADS )) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*Note: change below for your network setting!!! */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a +# define CONFIG_HAS_ETH1 +# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b +# define CONFIG_HAS_ETH2 +# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c +#endif + +#define CONFIG_SERVERIP YourServerIP +#define CONFIG_IPADDR YourTargetIP +#define CONFIG_GATEWAYIP YourGatewayIP +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_HOSTNAME SBC8560 +#define CONFIG_ROOTPATH YourRootPath +#define CONFIG_BOOTFILE YourImageName + +#endif /* __CONFIG_H */ diff --git a/include/configs/SCM.h b/include/configs/SCM.h new file mode 100644 index 0000000..e263db6 --- /dev/null +++ b/include/configs/SCM.h @@ -0,0 +1,711 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ +#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ +#define CONFIG_SCM 1 /* ...on a System Controller Module */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#if (CONFIG_TQM8260 <= 100) +# error "TQM8260 module revison not supported" +#endif + +/* We use a TQM8260 module with a 300MHz CPU */ +#define CONFIG_300MHz + +/* Define 60x busmode only if your TQM8260 has L2 cache! */ +#ifdef CONFIG_L2_CACHE +# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ +#else +# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ +#endif + +/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ +#ifdef CONFIG_300MHz +# define CONFIG_BUSMODE_60x +#endif + +#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ + +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CONFIG_I2C_X + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#ifdef CONFIG_82xx_CONS_SMC1 +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#endif +#ifdef CONFIG_82xx_CONS_SMC2 +#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ +#endif + +#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ +#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ +#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * + * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the + * X.29 connector, and FCC2 is hardwired to the X.1 connector) + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) + +/* + * - Rx-CLK is CLK12 + * - Tx-CLK is CLK11 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) + +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK16 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#ifndef CONFIG_300MHz +#define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#else +#define CONFIG_8260_CLKIN 83333000 /* in Hz */ +#endif + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 115200 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_BSP) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ + +#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk + * The main FLASH is whichever is connected to *CS0. + */ +#define CFG_FLASH0_BASE 0x40000000 +#define CFG_FLASH1_BASE 0x60000000 +#define CFG_FLASH0_SIZE 32 +#define CFG_FLASH1_SIZE 32 + +/* Flash bank size (for preliminary settings) + */ +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#if 0 +/* Start port with environment in flash; switch to EEPROM later */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) +#define CFG_ENV_SIZE 0x40000 +#define CFG_ENV_SECT_SIZE 0x40000 +#else +/* Final version: environment in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 2048 +#endif + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#if defined(CONFIG_266MHz) +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ + HRCW_MODCK_H0111) +#elif defined(CONFIG_300MHz) +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ + HRCW_MODCK_H0110) +#else +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) +#endif + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM + * is mapped at SDRAM_BASE2_PRELIM. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ + HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#ifdef CONFIG_BUSMODE_60x +#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ + BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ +#else +#define BCR_APD01 0x10000000 +#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#if 0 +#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) +#else +#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) +#endif + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR 0 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 64 bit FLASH + * 1 60x SDRAM 64 bit SDRAM + * 2 Local SDRAM 32 bit SDRAM + * + */ + + /* Initialize SDRAM on local bus + */ +#define CFG_INIT_LOCAL_SDRAM + +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ + +/* Minimum mask to separate preliminary + * address ranges for CS[0:2] + */ +#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ +#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ + +#define CFG_MPTPR 0x4000 + +/*----------------------------------------------------------------------------- + * Address for Mode Register Set (MRS) command + *----------------------------------------------------------------------------- + * In fact, the address is rather configuration data presented to the SDRAM on + * its address lines. Because the address lines may be mux'ed externally either + * for 8 column or 9 column devices, some bits appear twice in the 8260's + * address: + * + * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | + * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | + * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | + * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | + * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | + *----------------------------------------------------------------------------- + */ +#define CFG_MRS_OFFS 0x00000110 + + +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + + /* SDRAM on TQM8260 can have either 8 or 9 columns. + * The number affects configuration values. + */ + +/* Bank 1 - 60x bus SDRAM + */ +#define CFG_PSRT 0x20 +#define CFG_LSRT 0x20 +#ifndef CFG_RAMBOOT +#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM CFG_OR1_8COL + + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A7 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR_8COL (PSDMR_PBI |\ + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A5 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_9COL (PSDMR_PBI |\ + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A7 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) + +/* Bank 2 - Local bus SDRAM + */ +#ifdef CFG_INIT_LOCAL_SDRAM +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) + +#define CFG_OR2_PRELIM CFG_OR2_8COL + +#define SDRAM_BASE2_PRELIM 0x80000000 + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A8 |\ + ORxS_NUMR_12) + +#define CFG_LSDMR_8COL (PSDMR_PBI |\ + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A6 |\ + ORxS_NUMR_13) + +#define CFG_LSDMR_9COL (PSDMR_PBI |\ + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) + +#endif /* CFG_INIT_LOCAL_SDRAM */ + +#endif /* CFG_RAMBOOT */ + +#define CFG_CAN0_BASE 0xc0000000 +#define CFG_CAN1_BASE 0xc0008000 +#define CFG_FIOX_BASE 0xc0010000 +#define CFG_FDOHM_BASE 0xc0018000 +#define CFG_EXTPROM_BASE 0xc2000000 + +#define CFG_CAN_SIZE 0x00000100 +#define CFG_FIOX_SIZE 0x00000020 +#define CFG_FDOHM_SIZE 0x00002000 +#define CFG_EXTPROM_BANK_SIZE 0x01000000 + +#define EXT_EEPROM_MAX_FLASH_BANKS 0x02 + +/* CS3 - CAN 0 + */ +#define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_UPMA |\ + BRx_V) + +#define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ + ORxU_BI |\ + ORxU_EHTR_4IDLE) + +/* CS4 - CAN 1 + */ +#define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_UPMA |\ + BRx_V) + +#define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ + ORxU_BI |\ + ORxU_EHTR_4IDLE) + +/* CS5 - Extended PROM (16MB optional) + */ +#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ + ORxG_CSNT |\ + ORxG_ACS_DIV4 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) + +/* CS6 - Extended PROM (16MB optional) + */ +#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \ + CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ + ORxG_CSNT |\ + ORxG_ACS_DIV4 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) + +/* CS7 - FPGA FIOX: Glue Logic + */ +#define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\ + ORxG_ACS_DIV4 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) + +/* CS8 - FPGA DOH Master + */ +#define CFG_FDOHM_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_FDOHM_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\ + ORxG_ACS_DIV4 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) + + +/* FPGA configuration */ +#define CFG_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */ +#define CFG_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */ +#define CFG_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */ + +#define CFG_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */ +#define CFG_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */ +#define CFG_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h new file mode 100644 index 0000000..61896d0 --- /dev/null +++ b/include/configs/SL8245.h @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2001 - 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ +/* + * Configuration settings for the SL8245 board. + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_SL8245 1 + + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#include + + +/* + * Miscellaneous configurable options + */ +#undef CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 32 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00400000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ +#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM +#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + + /* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x10000000 /* 0 .. 256 MB of (S)DRAM */ + + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +#define CFG_GBL_DATA_SIZE 128 +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 66666666 /* external frequency to pll */ +#define CFG_HZ 1000 + + /* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 7 +#define CFG_BANK0_ROW 2 + + /* Bit-field values for MCCR2. + */ +#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ + + /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 192 + + /* Bit-field values for MCCR3. + */ +#define CFG_REFREC 2 /* Refresh to activate interval */ + + /* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 3 /* FIXME was 2 */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8245 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8245 retains the */ + /* currently accessed page in memory */ + /* see 8245 book for details */ + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors per flash */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + + + /* Warining: environment is not EMBEDDED in the U-Boot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFFFF0000 +#define CFG_ENV_SIZE 0x00010000 /* Size of the Environment */ +#define CFG_ENV_SECT_SIZE 0x00010000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#undef CONFIG_PCI_SCAN_SHOW + + +#define CONFIG_SK98 +#define CONFIG_NET_MULTI + + +#endif /* __CONFIG_H */ diff --git a/include/configs/SM850.h b/include/configs/SM850.h new file mode 100644 index 0000000..4977629 --- /dev/null +++ b/include/configs/SM850.h @@ -0,0 +1,363 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */ + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_SM850 1 /*...on a MPC850 Service Module */ + +#undef CONFIG_8xx_CONS_SMC1 /* SMC1 not usable because Ethernet on SCC3 */ +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_STATUS_LED /* Status LED not enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ +#define CFG_PLPRCR \ + ( (5-1)< + +/*----------------------------------------------------------------------*/ +#define CONFIG_ETHADDR 00:D0:93:00:01:CB +#define CONFIG_IPADDR 10.0.0.98 +#define CONFIG_SERVERIP 10.0.0.1 +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000" +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 0 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +/* 0x00000040 */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit, set PLL multiplication factor ! + */ +/* 0x00b0c0c0 */ +#define CFG_PLPRCR \ + ( (11 << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ + /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ + PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ + ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* 0x01800014 */ +#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ + SCCR_RTDIV | SCCR_RTSEL | \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + SCCR_EBDF00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | \ + SCCR_DFNH000 | SCCR_DFLCD101 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register + *----------------------------------------------------------------------- + */ +/* 0x00C3 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register + *----------------------------------------------------------------------- + */ +/* TIMEP=2 */ +#define CFG_RCCR 0x0200 + +/*----------------------------------------------------------------------- + * RMDS - RISC Microcode Development Support Control Register + *----------------------------------------------------------------------- + */ +#define CFG_RMDS 0 + +/*----------------------------------------------------------------------- + * SDSR - SDMA Status Register + *----------------------------------------------------------------------- + */ +#define CFG_SDSR ((u_char)0x83) + +/*----------------------------------------------------------------------- + * SDMR - SDMA Mask Register + *----------------------------------------------------------------------- + */ +#define CFG_SDMR ((u_char)0x00) + +/*----------------------------------------------------------------------- + * + * Interrupt Levels + *----------------------------------------------------------------------- + */ +#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ +#define CONFIG_IDE_LED 1 /* LED for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xFE100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_IDE1_OFFSET 0x0C00 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +/* EPROMs are 512kb */ +#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ + OR_SCY_5_CLK | OR_EHTR) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +/* 16 bit, bank valid */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +/* 16 bit, bank valid */ +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* + * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC) + * + */ +#define SRAM_BASE 0xFE200000 /* SRAM bank */ +#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */ + +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ + +#define PER8_BASE 0xFE000000 /* PER8 bank */ +#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ + +#define SHARC_BASE 0xFE400000 /* SHARC bank */ +#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */ + +/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ + +#define CFG_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ +#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM ) +#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ + +#define CFG_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */ +#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) + +#define CFG_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ +#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 ) +#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) + +#define CFG_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ +#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC ) +#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MBMR_PTB 204 + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MBMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/SX1.h b/include/configs/SX1.h new file mode 100644 index 0000000..6ed98b8 --- /dev/null +++ b/include/configs/SX1.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ +#define CONFIG_OMAP_SX1 1 /* a SX1 Board */ + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 12000000 /* the SX1 has 12MHz input clock */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SX1 */ + +/* + * USB device configuration + */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 + +#define CONFIG_USBD_VENDORID 0x1234 +#define CONFIG_USBD_PRODUCTID 0x5678 +#define CONFIG_USBD_MANUFACTURER "Siemens" +#define CONFIG_USBD_PRODUCT_NAME "SX1" + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C +#define CFG_I2C_SPEED 100000 +#define CFG_I2C_SLAVE 1 +#define CONFIG_DRIVER_OMAP1510_I2C + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ + CFG_CMD_I2C ) & \ + ~CFG_CMD_NET) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#include + +#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw" +#define CONFIG_PREBOOT "setenv stdout usbtty;setenv stdin usbtty" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SX1# " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x10000000 /* default load address */ + +/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. + * This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define PHYS_FLASH_SIZE (16 << 10) /* 16 MB */ +#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE } + +/*----------------------------------------------------------------------- + * FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_SIZE_REDUND 0x20000 +#define CFG_ENV_OFFSET_REDUND 0x40000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h new file mode 100644 index 0000000..c1c765f --- /dev/null +++ b/include/configs/SXNI855T.h @@ -0,0 +1,460 @@ +/* + * U-Boot configuration for SIXNET SXNI855T CPU board. + * This board is based (loosely) on the Motorola FADS board, so this + * file is based (loosely) on config_FADS860T.h, see it for additional + * credits. + * + * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Memory map: + * + * ff100000 -> ff13ffff : FPGA CS1 + * ff030000 -> ff03ffff : EXPANSION CS7 + * ff020000 -> ff02ffff : DATA FLASH CS4 + * ff018000 -> ff01ffff : UART B CS6/UPMB + * ff010000 -> ff017fff : UART A CS5/UPMB + * ff000000 -> ff00ffff : IMAP internal to the MPC855T + * f8000000 -> fbffffff : FLASH CS0 up to 64MB + * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB + * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#include + +#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */ + +/* The 855T is just a stripped 860T and needs code for 860, so for now + * at least define 860, 860T and 855T + */ +#define CONFIG_MPC860 1 +#define CONFIG_MPC860T 1 +#define CONFIG_MPC855T 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_SCC1 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ + +#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_HAS_ETH1 + +/*----------------------------------------------------------------------- + * Definitions for status LED + */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +# define STATUS_LED_PAR im_ioport.iop_papar +# define STATUS_LED_DIR im_ioport.iop_padir +# define STATUS_LED_ODR im_ioport.iop_paodr +# define STATUS_LED_DAT im_ioport.iop_padat + +# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */ +# define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#ifdef DEV /* development (debug) settings */ +#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF +#else /* production settings */ +#define CONFIG_BOOT_LED_STATE STATUS_LED_ON +#endif + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/ram ip=off" + +#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ +#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */ + +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +# define CFG_I2C_SPEED 50000 +# define CFG_I2C_SLAVE 0xFE +# define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */ +# define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ + +#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ +#define CONFIG_MII 1 + +#define CFG_DISCOVER_PHY + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_JFFS2_SORT_FRAGMENTS + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE + +/* +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0x00780000 +#define CONFIG_JFFS2_PART_OFFSET 0x00080000 +*/ + +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_SIZE 0x00200000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand" +#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)" +*/ + +/* NAND flash support */ +#define CONFIG_MTD_NAND_ECC_JFFS2 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +/* DFBUSY is available on Port C, bit 12; 0 if busy */ +#define NAND_WAIT_READY(nand) \ + while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008)); +#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr)) +#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr)) +#define WRITE_NAND(d, adr) \ + do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0) +#define READ_NAND(adr) (*(volatile uint8_t *)(adr)) +#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */ +#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */ +#define CE_LO 0x04 /* 1 selects chip (CE low) */ +#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0) +#define NAND_DISABLE_CE(nand) \ + nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO) +#define NAND_ENABLE_CE(nand) \ + nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO) +#define NAND_CTL_CLRALE(nandptr) \ + nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) +#define NAND_CTL_SETALE(nandptr) \ + nand_setcr((nandptr) + 1, CE_LO | CLE_LO) +#define NAND_CTL_CLRCLE(nandptr) \ + nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) +#define NAND_CTL_SETCLE(nandptr) \ + nand_setcr((nandptr) + 1, CE_LO | ALE_LO) + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save a little memory */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 +#define CFG_IMMR_SIZE ((uint)(64 * 1024)) + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SRAM_BASE 0xF4000000 +#define CFG_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */ + +#define CFG_FLASH_BASE 0xF8000000 +#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ + +#define CFG_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */ +#define CFG_DFLASH_SIZE 0x00010000 + +#define CFG_FPGA_BASE 0xFF100000 /* Xilinx FPGA */ +#define CFG_FPGA_PROG 0xFF130000 /* Programming address */ +#define CFG_FPGA_SIZE 0x00040000 /* 256KiB usable */ + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks. + * AMD 29LV641 has 128 64K sectors in 8MB + */ +#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control (15-29) + */ +#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) + + /*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* Because of the way the 860 starts up and assigns CS0 the + * entire address space, we have to set the memory controller + * differently. Normally, you write the option register + * first, and then enable the chip select by writing the + * base register. For CS0, you must write the base register + * first, followed by the option register. + */ + +/* + * Init Memory Controller: + * + ********************************************************** + * BR0 and OR0 (FLASH) + */ + +#define CFG_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */ + +/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH) + +#define CONFIG_FLASH_16BIT +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CFG_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */ + +/********************************************************** + * BR1 and OR1 (FPGA) + * These preliminary values are also the final values. + */ +#define CFG_OR_TIMING_FPGA \ + (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX) +#define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA) + +/********************************************************** + * BR4 and OR4 (data flash) + * These preliminary values are also the final values. + */ +#define CFG_OR_TIMING_DFLASH \ + (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX) +#define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH) + +/********************************************************** + * BR5/6 and OR5/6 (Dual UART) + */ +#define CFG_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */ +#define CFG_DUARTA_BASE 0xff010000 +#define CFG_DUARTB_BASE 0xff018000 + +#define DUART_MBMR 0 +#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI) +#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V) +#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE) +#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE) + +/********************************************************** + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_RESET_ON_PANIC /* reset if system panic() */ + +#define CFG_ENV_IS_IN_FLASH +#ifdef CFG_ENV_IS_IN_FLASH + /* environment is in FLASH */ + #define CFG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */ + #define CFG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */ + #define CFG_ENV_SECT_SIZE 0x00010000 + #define CFG_ENV_SIZE 0x00002000 +#else + /* environment is in EEPROM */ + #define CFG_ENV_IS_IN_EEPROM 1 + #define CFG_ENV_OFFSET 0 /* at beginning of EEPROM */ + #define CFG_ENV_SIZE 1024 /* Use only a part of it*/ +#endif + +#if 1 +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "delayabit" +#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h new file mode 100644 index 0000000..f4339ec --- /dev/null +++ b/include/configs/Sandpoint8240.h @@ -0,0 +1,413 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8240 1 +#define CONFIG_SANDPOINT 1 + +#if 0 +#define USE_DINK32 1 +#else +#undef USE_DINK32 +#endif + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "net_self=tftp ${kernel_addr} ${bootfile};" \ + "tftp ${ramdisk_addr} ${ramdisk};" \ + "run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp ${kernel_addr} ${bootfile};" \ + "run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/SP8240/uImage\0" \ + "ramdisk=/tftpboot/SP8240/uRamdisk\0" \ + "kernel_addr=200000\0" \ + "ramdisk_addr=400000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_SDRAM | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_DRAM_SPEED 100 /* MHz */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET0_MEMADDR 0x80000000 +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET1_MEMADDR 0x81000000 + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x10000000 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#if defined (USE_DINK32) +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE 0x00090000 +#define CFG_RAMBOOT 1 +#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_INIT_RAM_END 0x10000 +#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#else +#undef CFG_RAMBOOT +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE TEXT_BASE + +/*#define CFG_GBL_DATA_SIZE 256*/ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#endif + +#define CFG_FLASH_BASE 0xFFF00000 +#if 0 +#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ +#else +#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ +#endif +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ + +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_ISA_MEM 0xFD000000 +#define CFG_ISA_IO 0xFE000000 + +#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ +#define CFG_FLASH_RANGE_SIZE 0x01000000 +#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ +#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ + +/* + * select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#ifdef CONFIG_SOFT_I2C +#error "Soft I2C is not configured properly. Please review!" +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + + +#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* write page size */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ + + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + + +#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ +#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ +#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ +#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ + +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +/* + * NS87308 Configuration + */ +#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ + +#define CFG_NS87308_BADDR_10 1 + +#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ + CFG_NS87308_UART2 | \ + CFG_NS87308_POWRMAN | \ + CFG_NS87308_RTC_APC ) + +#undef CFG_NS87308_PS2MOD + +#define CFG_NS87308_CS0_BASE 0x0076 +#define CFG_NS87308_CS0_CONF 0x30 +#define CFG_NS87308_CS1_BASE 0x0075 +#define CFG_NS87308_CS1_CONF 0x30 +#define CFG_NS87308_CS2_BASE 0x0074 +#define CFG_NS87308_CS2_CONF 0x30 + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 1843200 + +#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) +#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ +#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1 + +#define CFG_ROMNAL 7 /*rom/flash next access time */ +#define CFG_ROMFAL 11 /*rom/flash access time */ + +#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ + +/* the following are for SDRAM only*/ +#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT 4 /* data latency from read command */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 3 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ + +#define CFG_REGISTERD_TYPE_BUFFER 1 + +/* memory bank settings*/ +/* + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#if defined(USE_DINK32) +#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) +#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) +#else +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#endif + +/* PCI memory */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* values according to the manual */ + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +#undef NR_8259_INTS +#define NR_8259_INTS 1 + + +#define CONFIG_DISK_SPINUP_TIME 1000000 + + +#endif /* __CONFIG_H */ diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h new file mode 100644 index 0000000..d42bd69 --- /dev/null +++ b/include/configs/Sandpoint8245.h @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_SANDPOINT 1 + +#if 0 +#define USE_DINK32 1 +#else +#undef USE_DINK32 +#endif + +#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ +#define CONFIG_BAUDRATE 9600 +#define CONFIG_DRAM_SPEED 100 /* MHz */ + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NATSEMI +#define CONFIG_NS8382X + +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET0_MEMADDR 0x80000000 +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET1_MEMADDR 0x81000000 + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x10000000 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#if defined (USE_DINK32) +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE 0x00090000 +#define CFG_RAMBOOT 1 +#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_INIT_RAM_END 0x10000 +#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#else +#undef CFG_RAMBOOT +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE TEXT_BASE + +/*#define CFG_GBL_DATA_SIZE 256*/ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#endif + +#define CFG_FLASH_BASE 0xFFF00000 +#if 0 +#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ +#else +#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ +#endif +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ + +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_ISA_MEM 0xFD000000 +#define CFG_ISA_IO 0xFE000000 + +#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ +#define CFG_FLASH_RANGE_SIZE 0x01000000 +#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ +#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ + +/* + * select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#ifdef CONFIG_SOFT_I2C +#error "Soft I2C is not configured properly. Please review!" +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + + +#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ +#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ +#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ +#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ + +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +/* + * NS87308 Configuration + */ +#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ + +#define CFG_NS87308_BADDR_10 1 + +#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ + CFG_NS87308_UART2 | \ + CFG_NS87308_POWRMAN | \ + CFG_NS87308_RTC_APC ) + +#undef CFG_NS87308_PS2MOD + +#define CFG_NS87308_CS0_BASE 0x0076 +#define CFG_NS87308_CS0_CONF 0x30 +#define CFG_NS87308_CS1_BASE 0x0075 +#define CFG_NS87308_CS1_CONF 0x30 +#define CFG_NS87308_CS2_BASE 0x0074 +#define CFG_NS87308_CS2_CONF 0x30 + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#if (CONFIG_CONS_INDEX > 2) +#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000 +#else +#define CFG_NS16550_CLK 1843200 +#endif + +#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) +#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) +#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CFG_ROMNAL 7 /*rom/flash next access time */ +#define CFG_ROMFAL 11 /*rom/flash access time */ + +#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ + +/* the following are for SDRAM only*/ +#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT 4 /* data latency from read command */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 3 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#if 0 +#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ +#endif + +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + + +/* memory bank settings*/ +/* + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#if defined(USE_DINK32) +#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) +#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) +#else +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#endif + +/* PCI memory */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* values according to the manual */ + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +#undef NR_8259_INTS +#define NR_8259_INTS 1 + + +#define CONFIG_DISK_SPINUP_TIME 1000000 + + +#endif /* __CONFIG_H */ diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h new file mode 100644 index 0000000..119bc24 --- /dev/null +++ b/include/configs/TASREG.h @@ -0,0 +1,278 @@ +/* + * Configuation settings for the esd TASREG board. + * + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _TASREG_H +#define _TASREG_H + +#ifndef __ASSEMBLY__ +#include +#endif + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5249 /* define processor type */ + +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C ) & \ + ~(CFG_CMD_NET)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#define CONFIG_BOOTDELAY 3 + +#define CFG_PROMPT "=> " +#define CFG_LONGHELP /* undef to save memory */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ + +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000 + +/* + * Clock configuration: enable only one of the following options + */ + +#if 0 /* this setting will run the cpu at 11MHz */ +#define CFG_PLL_BYPASS 1 /* bypass PLL for test purpose */ +#undef CFG_FAST_CLK /* MCF5249 can run at 140MHz */ +#define CFG_CLK 11289600 /* PLL bypass */ +#endif + +#if 0 /* this setting will run the cpu at 70MHz */ +#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ +#undef CFG_FAST_CLK /* MCF5249 can run at 140MHz */ +#define CFG_CLK 72185018 /* The next lower speed */ +#endif + +#if 1 /* this setting will run the cpu at 140MHz */ +#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */ +#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */ +#endif + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_MBAR2 0x80000000 + +/*----------------------------------------------------------------------- + * I2C + */ +#define CONFIG_SOFT_I2C +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#if defined (CONFIG_SOFT_I2C) +#if 0 /* push-pull */ +#define SDA 0x00800000 +#define SCL 0x00000008 +#define DIR0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN)) +#define DIR1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN)) +#define OUT0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT)) +#define OUT1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT)) +#define IN0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ)) +#define IN1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ)) +#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;} +#define I2C_READ ((IN1&SDA)?1:0) +#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;} +#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;} +#define I2C_DELAY {udelay(5);} +#define I2C_ACTIVE {DIR1|=SDA;} +#define I2C_TRISTATE {DIR1&=~SDA;} +#else /* open-collector */ +#define SDA 0x00800000 +#define SCL 0x00000008 +#define DIR0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN)) +#define DIR1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN)) +#define OUT0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT)) +#define OUT1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT)) +#define IN0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ)) +#define IN1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ)) +#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;} +#define I2C_READ ((IN1&SDA)?1:0) +#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;} +#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;} +#define I2C_DELAY {udelay(5);} +#define I2C_ACTIVE {DIR1|=SDA;} +#define I2C_TRISTATE {DIR1&=~SDA;} +#endif +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_FLASH_BASE 0xffc00000 + +#if 0 /* test-only */ +#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ +#endif + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) + +#define CFG_MONITOR_LEN 0x20000 +#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ +#define CFG_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ + +/* CS0 - AMD Flash, address 0xffc00000 */ +#define CFG_CSAR0 0xffc0 +#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ +/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ +#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ + +/* CS1 - FPGA, address 0xe0000000 */ +#define CFG_CSAR1 0xe000 +#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ +#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ +#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ + +#define CFG_GPIO1_LED 0x00400000 /* user led */ + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */ + +#endif /* _TASREG_H */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h new file mode 100644 index 0000000..f41dbd0 --- /dev/null +++ b/include/configs/TOP5200.h @@ -0,0 +1,418 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de + * + * TOP5200 differences from IceCube: + * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks + * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins + * 1 SDRAM/DDRAM Bank up to 256 MB + * local VPD I2C Bus is software driven and uses + * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL + * FLASH is re-located at 0xff000000 + * Internal regs are at 0xf0000000 + * Reset jumps to 0x00000100 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ +#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +# define CONFIG_PCI 1 +# define CONFIG_PCI_PNP 1 +# define CONFIG_PCI_SCAN_SHOW 1 + +# define CONFIG_PCI_MEM_BUS 0x40000000 +# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +# define CONFIG_PCI_MEM_SIZE 0x10000000 + +# define CONFIG_PCI_IO_BUS 0x50000000 +# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +# define CONFIG_PCI_IO_SIZE 0x01000000 + +# define ADD_PCI_CMD CFG_CMD_PCI + +#else /* no Evaluation board */ + +# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + +#endif + +/* USB */ +#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) + +# define CONFIG_USB_OHCI +# define CONFIG_USB_CLOCK 0x0001bbbb +# if defined (CONFIG_EVAL5200) +# define CONFIG_USB_CONFIG 0x00005100 +# else +# define CONFIG_USB_CONFIG 0x00001000 +# endif +# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +# define CONFIG_DOS_PARTITION +# define CONFIG_USB_STORAGE + +#else + +# define ADD_USB_CMD 0 + +#endif + +/* IDE */ +#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) + +# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT +# define CONFIG_DOS_PARTITION + +#else + +# define ADD_IDE_CMD 0 + +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + ADD_IDE_CMD | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_BEDBUG \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * MUST be low boot - HIGHBOOT is not supported anymore + */ +#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 +#else +# error "TEXT_BASE must be 0xff000000" +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/MPC5200/uImage\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ + +/* + * I2C configuration + */ +/* + * EEPROM configuration + */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_SIZE 0x2000 + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_MISC_INIT_R + +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */ + +#if defined (CONFIG_SOFT_I2C) +# define SDA0 0x40 +# define SCL0 0x80 +# define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00)) +# define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08)) +# define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c)) +# define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20)) +# define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04)) +# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);} +# define I2C_READ ((DVI0&SDA0)?1:0) +# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;} +# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;} +# define I2C_DELAY {udelay(5);} +# define I2C_ACTIVE {DDR0|=SDA0;} +# define I2C_TRISTATE {DDR0&=~SDA0;} +# define CFG_I2C_SPEED 100000 +# define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_FACT_ADDR 0x57 +#endif + +#if defined (CONFIG_HARD_I2C) +# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +# define CFG_I2C_SPEED 100000 /* 100 kHz */ +# define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_EEPROM_ADDR 0x54 +#define CFG_I2C_FACT_ADDR 0x54 +#endif + +/* + * Flash configuration, expect one 16 Megabyte Bank at most + */ +#define CFG_FLASH_BASE 0xff000000 +#define CFG_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0) + +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ + +/* + * DRAM configuration - will be read from VPD later... TODO! + */ +#if 0 +/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */ +#define CFG_DRAM_DDR 0 +#define CFG_DRAM_EMODE 0 +#define CFG_DRAM_MODE 0x008D +#define CFG_DRAM_CONTROL 0x514F0000 +#define CFG_DRAM_CONFIG1 0xC2233A00 +#define CFG_DRAM_CONFIG2 0x88B70004 +#define CFG_DRAM_TAP_DEL 0x08 +#define CFG_DRAM_RAM_SIZE 0x19 +#endif +#if 1 +/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */ +#define CFG_DRAM_DDR 0 +#define CFG_DRAM_EMODE 0 +#define CFG_DRAM_MODE 0x00CD +#define CFG_DRAM_CONTROL 0x514F0000 +#define CFG_DRAM_CONFIG1 0xD2333A00 +#define CFG_DRAM_CONFIG2 0x8AD70004 +#define CFG_DRAM_TAP_DEL 0x08 +#define CFG_DRAM_RAM_SIZE 0x19 +#endif + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ +#define CFG_ENV_OFFSET 0x1000 +#define CFG_ENV_SIZE 0x0700 + +/* + * VPD settings + */ +#define CFG_FACT_OFFSET 0x1800 +#define CFG_FACT_SIZE 0x0800 + +/* + * Memory map + * + * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 + */ +#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ +#define CONFIG_PHY_ADDR 0x1f +#define CONFIG_PHY_TYPE 0x79c874 +/* + * GPIO configuration: + * PSC1,2,3 predefined as UART + * PCI disabled + * Ethernet 100 with MD + */ +#define CFG_GPS_PORT_CONFIG 0x00058044 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */ + #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */ + #define RTC(reg) (0xf0010000+reg) + /* setup CS2 for M48T08. Must MAP 64kB */ + #define CFG_CS2_START RTC(0) + #define CFG_CS2_SIZE 0x10000 + /* setup CS2 configuration register: */ + /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */ + /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */ + #define CFG_CS2_CFG 0x00047800 +#else + #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ +#endif + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0x7f000000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET 1 +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005c) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h new file mode 100644 index 0000000..2344b96 --- /dev/null +++ b/include/configs/TOP860.h @@ -0,0 +1,442 @@ +/* + * (C) Copyright 2003 + * EMK Elektronik GmbH + * Reinhard Meyer + * + * Configuation settings for the TOP860 board. + * + * ----------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * TOP860 is a simple module: + * 16-bit wide FLASH on CS0 (2MB or more) + * 32-bit wide DRAM on CS2 (either 4MB or 16MB) + * FEC with Am79C874 100-Base-T and Fiber Optic + * Ports available, but we choose SMC1 for Console + * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set + * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock + * + * This config has been copied from MBX.h / MBX860T.h + */ +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +/*----------------------------------------------------------------------- + * CPU and BOARD type + */ +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_MPC860T 1 /* even better... an FEC! */ +#define CONFIG_TOP860 1 /* ...on a TOP860 module */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_IDENT_STRING " EMK TOP860" + +/*----------------------------------------------------------------------- + * CLOCK settings + */ +#define CONFIG_SYSCLK 49152000 +#define CFG_XTAL 32768 +#define CONFIG_EBDF 1 +#define CONFIG_COM 3 +#define CONFIG_RTC_MPC8xx + +/*----------------------------------------------------------------------- + * Physical memory map as defined by EMK + */ +#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register */ +#define CFG_FLASH_BASE 0x80000000 /* FLASH in final mapping */ +#define CFG_DRAM_BASE 0x00000000 /* DRAM in final mapping */ +#define CFG_FLASH_MAX 0x00400000 /* max FLASH to expect */ +#define CFG_DRAM_MAX 0x01000000 /* max DRAM to expect */ + +/*----------------------------------------------------------------------- + * derived values + */ +#define CFG_MF (CONFIG_SYSCLK/CFG_XTAL) +#define CFG_CPUCLOCK CONFIG_SYSCLK +#define CFG_BRGCLOCK CONFIG_SYSCLK +#define CFG_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF) +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_CFI + +/*----------------------------------------------------------------------- + * Command interpreter + */ +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#define CONFIG_BAUDRATE 9600 + +/* + * Allow partial commands to be matched to uniqueness. + */ +#define CFG_MATCH_PARTIAL_CMD + +/* + * List of available monitor commands. Use the system default list + * plus add some of the "non-standard" commands back in. + * See ./cmd_confdefs.h + */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_BEDBUG \ + ) + +#define CONFIG_AUTOSCRIPT 1 +#define CFG_LOADS_BAUD_CHANGE 1 +#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */ + +#ifdef CFG_HUSH_PARSER + #define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/*----------------------------------------------------------------------- + * Memory Test Command + */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/*----------------------------------------------------------------------- + * Environment handler + * only the first 6k in EEPROM are available for user. Of that we use 256b + */ +#define CONFIG_SOFT_I2C +#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ +#define CFG_ENV_OFFSET 0x1000 +#define CFG_ENV_SIZE 0x0700 +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_FACT_OFFSET 0x1800 +#define CFG_FACT_SIZE 0x0800 +#define CFG_I2C_FACT_ADDR 0x57 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_SIZE 0x2000 +#define CFG_I2C_SPEED 100000 +#define CFG_I2C_SLAVE 0xFE +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 +#define CONFIG_ENV_OVERWRITE +#define CONFIG_MISC_INIT_R + +#if defined (CONFIG_SOFT_I2C) +#define SDA 0x00010 +#define SCL 0x00020 +#define __I2C_DIR immr->im_cpm.cp_pbdir +#define __I2C_DAT immr->im_cpm.cp_pbdat +#define __I2C_PAR immr->im_cpm.cp_pbpar +#define __I2C_ODR immr->im_cpm.cp_pbodr +#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ + __I2C_ODR &= ~(SDA|SCL); \ + __I2C_DAT |= (SDA|SCL); \ + __I2C_DIR|=(SDA|SCL); } +#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) +#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } +#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } +#define I2C_DELAY { udelay(5); } +#define I2C_ACTIVE { __I2C_DIR |= SDA; } +#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } +#endif + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/*----------------------------------------------------------------------- + * defines we need to get FEC running + */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ +#define FEC_ENET 1 /* eth.c needs it that way... */ +#define CFG_DISCOVER_PHY 1 +#define CONFIG_MII 1 +#define CONFIG_PHY_ADDR 31 + +/*----------------------------------------------------------------------- + * adresses + */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x80000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ +#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) +#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/* Interrupt level assignments. +*/ +#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * Debug Enable Register + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 /* used in start.S */ + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * set up PLPRCR (PLL, Low-Power, and Reset Control Register) + * 12 MF calculated Multiplication factor + * 4 0 0000 + * 1 SPLSS 0 System PLL lock status sticky + * 1 TEXPS 1 Timer expired status + * 1 0 0 + * 1 TMIST 0 Timers interrupt status + * 1 0 0 + * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL) + * 2 LPM 00 Low-power modes + * 1 CSR 0 Checkstop reset enable + * 1 LOLRE 0 Loss-of-lock reset enable + * 1 FIOPD 0 Force I/O pull down + * 5 0 00000 + */ +#define CFG_PLPRCR (PLPRCR_TEXPS | ((CFG_MF-1)<<20)) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * set up SYPCR: + * 16 SWTC 0xffff Software watchdog timer count + * 8 BMT 0xff Bus monitor timing + * 1 BME 1 Bus monitor enable + * 3 0 000 + * 1 SWF 1 Software watchdog freeze + * 1 SWE 0/1 Software watchdog enable + * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET) + * 1 SWP 0/1 Software watchdog prescale (1=/2048) + */ +#if defined (CONFIG_WATCHDOG) + #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else + #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * set up SIUMCR + * 1 EARB 0 External arbitration + * 3 EARP 000 External arbitration request priority + * 4 0 0000 + * 1 DSHW 0 Data show cycles + * 2 DBGC 00 Debug pin configuration + * 2 DBPC 00 Debug port pins configuration + * 1 0 0 + * 1 FRC 0 FRZ pin configuration + * 1 DLK 0 Debug register lock + * 1 OPAR 0 Odd parity + * 1 PNCS 0 Parity enable for non memory controller regions + * 1 DPC 0 Data parity pins configuration + * 1 MPRE 0 Multiprocessor reservation enable + * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT) + * 1 AEME 0 Async external master enable + * 1 SEME 0 Sync external master enable + * 1 BSC 0 Byte strobe configuration + * 1 GB5E 0 GPL_B5 enable + * 1 B2DD 0 Bank 2 double drive + * 1 B3DD 0 Bank 3 double drive + * 4 0 0000 + */ +#define CFG_SIUMCR (SIUMCR_MLRC11) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * set up SCCR (System Clock and Reset Control Register) + * 1 0 0 + * 2 COM 11 Clock output module (00=full, 01=half, 11=off) + * 3 0 000 + * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2) + * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512) + * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK) + * 1 CRQEN 0 CPM request enable + * 1 PRQEN 0 Power management request enable + * 2 0 00 + * 2 EBDF xx External bus division factor + * 2 0 00 + * 2 DFSYNC 00 Division factor for SYNCLK + * 2 DFBRG 00 Division factor for BRGCLK + * 3 DFNL 000 Division factor low frequency + * 3 DFNH 000 Division factor high frequency + * 5 0 00000 + */ +#define SCCR_MASK 0 +#ifdef CONFIG_EBDF + #define CFG_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01) +#else + #define CFG_SCCR (SCCR_COM11 | SCCR_TBS) +#endif + +/*----------------------------------------------------------------------- + * Chip Select 0 - FLASH + *----------------------------------------------------------------------- + * Preliminary Values + */ +/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR) +#define CFG_OR0_PRELIM (-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V ) + +/*----------------------------------------------------------------------- + * misc + *----------------------------------------------------------------------- + * + */ +/* + * Set the autoboot delay in seconds. A delay of -1 disables autoboot + */ +#define CONFIG_BOOTDELAY 5 + +/* + * Pass the clock frequency to the Linux kernel in units of MHz + */ +#define CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_PREBOOT \ + "echo;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_MASK +#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE \ + ) + + +/* + * Set default IP stuff just to get bootstrap entries into the + * environment so that we can autoscript the full default environment. + */ +#define CONFIG_ETHADDR 9a:52:63:15:85:25 +#define CONFIG_SERVERIP 10.0.4.200 +#define CONFIG_IPADDR 10.0.4.111 + +/*----------------------------------------------------------------------- + * Defaults for Autoscript + */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_TFTP_LOADADDR 0x00100000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h new file mode 100644 index 0000000..5ad1939 --- /dev/null +++ b/include/configs/TQM5200.h @@ -0,0 +1,564 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ +#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ +#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ +#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#ifdef CONFIG_STK52XX +#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ +#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ +#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ +#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ +#define CONFIG_BOARD_EARLY_INIT_R +#endif /* CONFIG_STK52XX */ + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#ifdef CONFIG_STK52XX +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +/* #define CONFIG_PCI_SCAN_SHOW 1 */ + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 +#endif /* CONFIG_STK52XX */ + +#ifdef CONFIG_PCI +#define ADD_PCI_CMD CFG_CMD_PCI +#else +#define ADD_PCI_CMD 0 +#endif + +/* + * Video console + */ +#if 1 +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SM501 +#define CONFIG_VIDEO_SM501_32BPP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CFG_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_VIDEO +#define ADD_BMP_CMD CFG_CMD_BMP +#else +#define ADD_BMP_CMD 0 +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* USB */ +#ifdef CONFIG_STK52XX +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_I2C) + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +/* preserve space for the post_word at end of on-chip SRAM */ +#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +/* IDE */ +#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) +#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) +#else +#define ADD_IDE_CMD 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_BMP_CMD | \ + ADD_IDE_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_TIMESTAMP /* display image timestamps */ + +#if (TEXT_BASE == 0xFC000000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#if defined (CONFIG_TQM5200_AA) +# define CONFIG_U_BOOT_SUFFIX "-AA\0" +#elif defined (CONFIG_TQM5200_AB) +# define CONFIG_U_BOOT_SUFFIX "-AB\0" +#elif defined (CONFIG_TQM5200_AC) +# define CONFIG_U_BOOT_SUFFIX "-AC\0" +#else +# define CONFIG_U_BOOT_SUFFIX "\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "bootfile=/tftpboot/tqm5200/uImage\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC05FFFF\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if defined(CFG_IPBSPEED_133) +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. + */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#ifdef CONFIG_TQM5200_REV100 +#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ +#else +#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ +#endif + +/* + * I2C clock frequency + * + * Please notice, that the resulting clock frequency could differ from the + * configured value. This is because the I2C clock is derived from system + * clock over a frequency divider with only a few divider values. U-boot + * calculates the best approximation for CFG_I2C_SPEED. However the calculated + * approximation allways lies below the configured value, never above. + */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work + * also). For other EEPROMs configuration should be verified. On Mini-FAP the + * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the + * same configuration could be used. + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* + * HW-Monitor configuration on Mini-FAP + */ +#if defined (CONFIG_MINIFAP) +#define CFG_I2C_HWMON_ADDR 0x2C +#endif + +/* List of I2C addresses to be verified by POST */ +#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB) +#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ + CFG_I2C_SLAVE } +#elif defined (CONFIG_TQM5200_AC) +#define I2C_ADDR_LIST { CFG_I2C_SLAVE } +#endif + +#if defined (CONFIG_MINIFAP) +#undef I2C_ADDR_LIST +#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ + CFG_I2C_HWMON_ADDR, \ + CFG_I2C_SLAVE } +#endif + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ + +/* use CFI flash driver if no module variant is spezified */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ + +#if !defined(CFG_LOWBOOT) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) +#else /* CFG_LOWBOOT */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) +#endif /* CFG_LOWBOOT */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* Dynamic MTD partition support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM5200-0" +#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ + "1408k(kernel)," \ + "2m(initrd)," \ + "4m(small-fs)," \ + "16m(big-fs)," \ + "8m(misc)" + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + * + * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): + * Bit 0 (mask: 0x80000000): 1 + * use ALT CAN position: Bits 2-3 (mask: 0x30000000): + * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. + * Use for REV200 STK52XX boards. Do not use with REV100 modules + * (because, there I2C1 is used as I2C bus) + * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 + * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) + * 000 -> All PSC2 pins are GIOPs + * 001 -> CAN1/2 on PSC2 pins + * Use for REV100 STK52xx boards + * use PSC6: + * on STK52xx: + * use as UART. Pins PSC6_0 to PSC6_3 are used. + * Bits 9:11 (mask: 0x00700000): + * 101 -> PSC6 : Extended POST test is not available + * on MINI-FAP and TQM5200_IB: + * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): + * 000 -> PSC6 could not be used as UART, CODEC or IrDA + * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST + * tests. + */ +#if defined (CONFIG_MINIFAP) +# define CFG_GPS_PORT_CONFIG 0x91000004 +#elif defined (CONFIG_STK52XX) +# if defined (CONFIG_STK52XX_REV100) +# define CFG_GPS_PORT_CONFIG 0x81500014 +# else /* STK52xx REV200 and above */ +# if defined (CONFIG_TQM5200_REV100) +# error TQM5200 REV100 not supported on STK52XX REV200 or above +# else/* TQM5200 REV200 and above */ +# define CFG_GPS_PORT_CONFIG 0x91500004 +# endif +# endif +#else /* TMQ5200 Inbetriebnahme-Board */ +# define CFG_GPS_PORT_CONFIG 0x81000004 +#endif + +/* + * RTC configuration + */ +#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100) +# define CONFIG_RTC_M41T11 1 +# define CFG_I2C_RTC_ADDR 0x68 +#else +# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Enable an alternate, more extensive memory test */ +#define CFG_ALT_MEMTEST + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#ifdef CFG_PCISPEED_66 +#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ +#else +#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ +#endif +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* automatic configuration of chip selects */ +#ifdef CONFIG_CS_AUTOCONF +#define CONFIG_LAST_STAGE_INIT +#endif + +/* + * SRAM - Do not map below 2 GB in address space, because this area is used + * for SDRAM autosizing. + */ +#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF) +#define CFG_CS2_START 0xE5000000 +#ifdef CONFIG_TQM5200_AB +#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ +#else /* CONFIG_CS_AUTOCONF */ +#define CFG_CS2_SIZE 0x100000 /* 1 MByte */ +#endif +#define CFG_CS2_CFG 0x0004D930 +#endif + +/* + * Grafic controller - Do not map below 2 GB in address space, because this + * area is used for SDRAM autosizing. + */ +#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \ + defined (CONFIG_CS_AUTOCONF) +#define SM501_FB_BASE 0xE0000000 +#define CFG_CS1_START (SM501_FB_BASE) +#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ +#define CFG_CS1_CFG 0x8F48FF70 +#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 +#endif + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h new file mode 100644 index 0000000..b1c70f8 --- /dev/null +++ b/include/configs/TQM823L.h @@ -0,0 +1,453 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ + +#ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ +#endif + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM823L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#if defined(CONFIG_LCD) +# undef CONFIG_STATUS_LED /* disturbs display */ +#else +# define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#endif /* CONFIG_LCD */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#ifdef CONFIG_SPLASH_SCREEN +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#else +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h new file mode 100644 index 0000000..9f958f5 --- /dev/null +++ b/include/configs/TQM823M.h @@ -0,0 +1,443 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ + +#ifdef CONFIG_LCD /* with LCD controller ? */ +/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ +#endif + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM823M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#ifdef CONFIG_LCD +# undef CONFIG_STATUS_LED /* disturbs display */ +#else +# define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#endif /* CONFIG_LCD */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h new file mode 100644 index 0000000..49c3872 --- /dev/null +++ b/include/configs/TQM8260.h @@ -0,0 +1,639 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Imported from global configuration: + * CONFIG_MPC8255 + * CONFIG_MPC8265 + * CONFIG_200MHz + * CONFIG_266MHz + * CONFIG_300MHz + * CONFIG_L2_CACHE + * CONFIG_BUSMODE_60x + */ + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ + +#if 0 +#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ +#else +#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ +#endif + +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 9600 +#endif + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/TQM8260/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ + +/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ +#if (CONFIG_TQM8260 <= 100) + +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00020000) +#define I2C_TRISTATE (iop->pdir &= ~0x00020000) +#define I2C_READ ((iop->pdat & 0x00020000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#else + +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif + +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CONFIG_I2C_X + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#ifdef CONFIG_82xx_CONS_SMC1 +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#endif +#ifdef CONFIG_82xx_CONS_SMC2 +#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ +#endif + +#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ +#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ +#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * + * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the + * X.29 connector, and FCC2 is hardwired to the X.1 connector) + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ + +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) + +/* + * - RX clk is CLK11 + * - TX clk is CLK12 + */ +# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) +# define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ +# ifndef CONFIG_300MHz +# define CONFIG_8260_CLKIN 66666666 /* in Hz */ +# else +# define CONFIG_8260_CLKIN 83333000 /* in Hz */ +# endif +#endif /* CONFIG_MPC8255 */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk + * The main FLASH is whichever is connected to *CS0. + */ +#define CFG_FLASH0_BASE 0x40000000 +#define CFG_FLASH1_BASE 0x60000000 +#define CFG_FLASH0_SIZE 32 +#define CFG_FLASH1_SIZE 32 + +/* Flash bank size (for preliminary settings) + */ +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#if 0 +/* Start port with environment in flash; switch to EEPROM later */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) +#define CFG_ENV_SIZE 0x40000 +#define CFG_ENV_SECT_SIZE 0x40000 +#else +/* Final version: environment in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 2048 +#endif + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) + +#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) +#else /* ! MPC8255 && !MPC8265 */ +# if defined(CONFIG_266MHz) +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) +# elif defined(CONFIG_300MHz) +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) +# else +# define CFG_HRCW_MASTER (__HRCW__ALL__) +# endif +#endif /* CONFIG_MPC8255 */ + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM + * is mapped at SDRAM_BASE2_PRELIM. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ + HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#ifdef CONFIG_BUSMODE_60x +#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ + BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ +#else +#define BCR_APD01 0x10000000 +#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#if 0 +#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) +#else +#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) +#endif + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR 0 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 64 bit FLASH + * 1 60x SDRAM 64 bit SDRAM + * 2 Local SDRAM 32 bit SDRAM + * + */ + + /* Initialize SDRAM on local bus + */ +#define CFG_INIT_LOCAL_SDRAM + +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ + +/* Minimum mask to separate preliminary + * address ranges for CS[0:2] + */ +#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ +#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ + +#define CFG_MPTPR 0x4000 + +/*----------------------------------------------------------------------------- + * Address for Mode Register Set (MRS) command + *----------------------------------------------------------------------------- + * In fact, the address is rather configuration data presented to the SDRAM on + * its address lines. Because the address lines may be mux'ed externally either + * for 8 column or 9 column devices, some bits appear twice in the 8260's + * address: + * + * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | + * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | + * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | + * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | + * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | + *----------------------------------------------------------------------------- + */ +#define CFG_MRS_OFFS 0x00000110 + + +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) + + /* SDRAM on TQM8260 can have either 8 or 9 columns. + * The number affects configuration values. + */ + +/* Bank 1 - 60x bus SDRAM + */ +#define CFG_PSRT 0x20 +#define CFG_LSRT 0x20 +#ifndef CFG_RAMBOOT +#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM CFG_OR1_8COL + + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A7 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR_8COL (PSDMR_PBI |\ + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A5 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_9COL (PSDMR_PBI |\ + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A7 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) + +/* Bank 2 - Local bus SDRAM + */ +#ifdef CFG_INIT_LOCAL_SDRAM +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) + +#define CFG_OR2_PRELIM CFG_OR2_8COL + +#define SDRAM_BASE2_PRELIM 0x80000000 + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A8 |\ + ORxS_NUMR_12) + +#define CFG_LSDMR_8COL (PSDMR_PBI |\ + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A6 |\ + ORxS_NUMR_13) + +#define CFG_LSDMR_9COL (PSDMR_PBI |\ + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) + +#endif /* CFG_INIT_LOCAL_SDRAM */ + +#endif /* CFG_RAMBOOT */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h new file mode 100644 index 0000000..41f44c5 --- /dev/null +++ b/include/configs/TQM834x.h @@ -0,0 +1,511 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * TQM8349 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DEBUG +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC834X 1 /* MPC834X specific */ +#define CONFIG_TQM834X 1 /* TQM834X board specific */ + +/* IMMR Base Addres Register, use Freescale default: 0xff400000 */ +#define CFG_IMMRBAR 0xff400000 + +/* System clock. Primary input clock when in PCI host mode */ +#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ + +/* + * Local Bus LCRR + * LCRR: DLL bypass, Clock divider is 8 + * + * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz + * + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) + +/* board pre init: do not call, nothing to do */ +#undef CONFIG_BOARD_EARLY_INIT_F + +/* detect the number of flash banks */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define DDR_CASLAT_25 /* CASLAT set to 2.5 */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ + +/* buffered writes in the AMD chip set is not supported yet */ +#undef CFG_FLASH_USE_BUFFER_WRITE + +/* + * FLASH bank number detection + */ + +/* + * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash + * banks has to be determined at runtime and stored in a gloabl variable + * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only + * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and + * should be made sufficiently large to accomodate the number of banks that + * might actually be detected. Since most (all?) Flash related functions use + * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is + * defined as tqm834x_num_flash_banks. + */ +#define CFG_MAX_FLASH_BANKS_DETECT 2 +#ifndef __ASSEMBLY__ +extern int tqm834x_num_flash_banks; +#endif +#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks) + +#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */ + +/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \ + BR_MS_GPCM | BR_PS_32 | BR_V) + +/* FLASH timing (0x0000_0c54) */ +#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ + OR_GPCM_SCY_5 | OR_GPCM_TRLX) + +#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) + +#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ + +/* disable remaining mappings */ +#define CFG_BR1_PRELIM 0x00000000 +#define CFG_OR1_PRELIM 0x00000000 +#define CFG_LBLAWBAR1_PRELIM 0x00000000 +#define CFG_LBLAWAR1_PRELIM 0x00000000 + +#define CFG_BR2_PRELIM 0x00000000 +#define CFG_OR2_PRELIM 0x00000000 +#define CFG_LBLAWBAR2_PRELIM 0x00000000 +#define CFG_LBLAWAR2_PRELIM 0x00000000 + +#define CFG_BR3_PRELIM 0x00000000 +#define CFG_OR3_PRELIM 0x00000000 +#define CFG_LBLAWBAR3_PRELIM 0x00000000 +#define CFG_LBLAWAR3_PRELIM 0x00000000 + +#define CFG_BR4_PRELIM 0x00000000 +#define CFG_OR4_PRELIM 0x00000000 +#define CFG_LBLAWBAR4_PRELIM 0x00000000 +#define CFG_LBLAWAR4_PRELIM 0x00000000 + +#define CFG_BR5_PRELIM 0x00000000 +#define CFG_OR5_PRELIM 0x00000000 +#define CFG_LBLAWBAR5_PRELIM 0x00000000 +#define CFG_LBLAWAR5_PRELIM 0x00000000 + +#define CFG_BR6_PRELIM 0x00000000 +#define CFG_OR6_PRELIM 0x00000000 +#define CFG_LBLAWBAR6_PRELIM 0x00000000 +#define CFG_LBLAWAR6_PRELIM 0x00000000 + +#define CFG_BR7_PRELIM 0x00000000 +#define CFG_OR7_PRELIM 0x00000000 +#define CFG_LBLAWBAR7_PRELIM 0x00000000 +#define CFG_LBLAWAR7_PRELIM 0x00000000 + +/* + * Monitor config + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) + +/* + * I2C + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ +#define CFG_I2C_SLAVE 0x7F /* slave address */ +#define CFG_I2C_OFFSET 0x3000 + +/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ + +/* I2C RTC */ +#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_MII + +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_PCI + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* PCI1 host bridge */ +#define CFG_PCI1_MEM_BASE 0xc0000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + + +#undef CONFIG_EEPRO100 +#define CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE + #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE + #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ +#endif + +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* Common commands */ +#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ + | CFG_CMD_PING | CFG_CMD_EEPROM \ + | CFG_CMD_MII | CFG_CMD_JFFS2 + +#if defined(CFG_RAMBOOT) + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ + | CFG_CMD_TQM8349_COMMON) \ + & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_TQM8349_COMMON) \ + & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS)) +#endif + +#else /* CFG_RAMBOOT */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ + | CFG_CMD_TQM8349_COMMON) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_TQM8349_COMMON) +#endif + +#endif /* CFG_RAMBOOT */ + +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) + +#if defined(PCI_64BIT) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +/* i-cache and d-cache disabled */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID2 0x000000000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR D2:DA:5E:44:BC:29 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 +#endif + +#define CONFIG_IPADDR 192.168.205.1 + +#define CONFIG_HOSTNAME tqm8349 +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx +#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=tqm83xx\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=/tftpboot/tqm83xx/uImage\0" \ + "kernel_addr=80060000\0" \ + "ramdisk_addr=80160000\0" \ + "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ + "update=protect off 80000000 8003ffff; " \ + "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ + "upd=run load;run update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * JFFS2 partitions + */ +/* mtdparts command line support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM834x-0" + +/* default mtd partition table */ +#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ + "1m(kernel),2m(initrd),"\ + "-(user);"\ + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h new file mode 100644 index 0000000..16b2ce3 --- /dev/null +++ b/include/configs/TQM850L.h @@ -0,0 +1,434 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM850L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h new file mode 100644 index 0000000..bbc6960 --- /dev/null +++ b/include/configs/TQM850M.h @@ -0,0 +1,433 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM850M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h new file mode 100644 index 0000000..198db19 --- /dev/null +++ b/include/configs/TQM855L.h @@ -0,0 +1,441 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ +#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM855L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_SCC1_ENET +#define CONFIG_FEC_ENET +#define CONFIG_ETHPRIME "SCC ETHERNET" + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h new file mode 100644 index 0000000..e25a7a2 --- /dev/null +++ b/include/configs/TQM855M.h @@ -0,0 +1,476 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ +#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM855M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ +#if 0 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#endif + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_SCC1_ENET +#define CONFIG_FEC_ENET +#define CONFIG_ETHPRIME "SCC ETHERNET" + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h new file mode 100644 index 0000000..18197f2 --- /dev/null +++ b/include/configs/TQM85xx.h @@ -0,0 +1,452 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Wolfgang Denk + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * TQM85xx (8560/40/55/41) board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ + +#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ + +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/* + * Only MPC8540 doesn't have CPM module + */ +#ifndef CONFIG_MPC8540 +#define CONFIG_CPM2 1 /* has CPM2 */ +#endif + +/* + * sysclk for MPC85xx + * + * Two valid values are: + * 33000000 + * 66000000 + * + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz + * is likely the desired value here, so that is now the default. + * The board, however, can run at 66MHz. In any event, this value + * must match the settings of some switches. Details can be found + * in the README.mpc85xxads. + */ + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 33333333 +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 +#define CFG_MEMTEST_END 0x10000000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/ + +#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) +/* TQM8540 & 8560 need DLL-override */ +#define CONFIG_DDR_DLL /* DLL fix needed */ +#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ +#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */ + +#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) +#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ +#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */ + +/* + * Flash on the Local Bus + */ +#define CFG_FLASH0 0xFC000000 +#define CFG_FLASH1 0xF8000000 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } + +#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ +#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ + +#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ +#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ +#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ +#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ + +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#if defined(CONFIG_TQM8560) + +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ + +#else + +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +#endif /* CONFIG_TQM8560 */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ + +/* I2C RTC */ +#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* I2C EEPROM */ +/* + * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also). + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#define CONFIG_NET_MULTI 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define FEC_PHY_ADDR 3 +#define FEC_PHYIDX 0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 + +/* Options are TSEC[0-1], FEC */ +#define CONFIG_ETHPRIME "TSEC0" + +#if defined(CONFIG_TQM8540) +/* + * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC. + * The FEC port is connected on the same signals as the FCC3 port + * of the TQM8560 to the baseboard (STK85xx Starterkit). + * + * On the STK85xx Starterkit the X47/X50 jumper has to be set to + * a - d (X50.2 - 3) to enable the FEC port. + */ +#define CONFIG_MPC85XX_FEC 1 +#define CONFIG_MPC85XX_FEC_NAME "FEC" +#endif + +#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) +/* + * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port + * can be used at once, since only one FCC port is available on the STK85xx + * Starterkit. + * + * To use this port you have to configure U-Boot to use the FCC port 1...2 + * and set the X47/X50 jumper to: + * FCC1: a - b (X47.2 - X50.2) + * FCC2: a - c (X50.2 - 1) + */ +#define CONFIG_ETHER_ON_FCC +#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ +#endif + +#if defined(CONFIG_TQM8560) +/* + * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port + * can be used at once, since only one FCC port is available on the STK85xx + * Starterkit. + * + * To use this port you have to configure U-Boot to use the FCC port 1...3 + * and set the X47/X50 jumper to: + * FCC1: a - b (X47.2 - X50.2) + * FCC2: a - c (X50.2 - 1) + * FCC3: a - d (X50.2 - 3) + */ +#define CONFIG_ETHER_ON_FCC +#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ +#endif + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) +#define CONFIG_ETHER_ON_FCC1 +#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#endif + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) +#define CONFIG_ETHER_ON_FCC2 +#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#endif + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) +#define CONFIG_ETHER_ON_FCC3 +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#endif + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_TIMESTAMP /* Print image info with ts */ + +#if defined(CONFIG_PCI) +# define ADD_PCI_CMD (CFG_CMD_PCI) +#else +# define ADD_PCI_CMD 0 +#endif + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + ADD_PCI_CMD | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DTT | \ + CFG_CMD_MII | \ + CFG_CMD_PING ) +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + "netdev=eth0\0" \ + "consdev=ttyS0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ + ":$hostname:$netdev:off panic=1\0" \ + "addcons=setenv bootargs $bootargs " \ + "console=$consdev,$baudrate\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm $kernel_addr\0" \ + "flash_self=run ramargs addip addcons;" \ + "bootm $kernel_addr $ramdisk_addr\0" \ + "net_nfs=tftp $loadaddr $bootfile;" \ + "run nfsargs addip addcons;bootm\0" \ + "rootpath=/opt/eldk/ppc_85xx\0" \ + "kernel_addr=FE000000\0" \ + "ramdisk_addr=FE100000\0" \ + "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h new file mode 100644 index 0000000..4a1a432 --- /dev/null +++ b/include/configs/TQM860L.h @@ -0,0 +1,444 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM860L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +#define CONFIG_NETCONSOLE + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_SCC1_ENET +#define CONFIG_FEC_ENET +#define CONFIG_ETHPRIME "SCC ETHERNET" + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h new file mode 100644 index 0000000..4b754ba --- /dev/null +++ b/include/configs/TQM860M.h @@ -0,0 +1,443 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ +#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM860M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_SCC1_ENET +#define CONFIG_FEC_ENET +#define CONFIG_ETHPRIME "SCC ETHERNET" + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h new file mode 100644 index 0000000..1dc9f74 --- /dev/null +++ b/include/configs/TQM862L.h @@ -0,0 +1,447 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 +#define CONFIG_MPC860T 1 +#define CONFIG_MPC862 1 + +#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM862L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + * 100 Mhz => 100.000.000 / Divider = 195 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_NET_MULTI +#define CONFIG_SCC1_ENET +#define CONFIG_FEC_ENET +#define CONFIG_ETHPRIME "SCC ETHERNET" + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h new file mode 100644 index 0000000..3df060c --- /dev/null +++ b/include/configs/TQM862M.h @@ -0,0 +1,448 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 +#define CONFIG_MPC860T 1 +#define CONFIG_MPC862 1 + +#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM862M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + * 100 Mhz => 100.000.000 / Divider = 195 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_NET_MULTI +#define CONFIG_SCC1_ENET +#define CONFIG_FEC_ENET +#define CONFIG_ETHPRIME "SCC ETHERNET" + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h new file mode 100644 index 0000000..8f9c2c9 --- /dev/null +++ b/include/configs/TQM866M.h @@ -0,0 +1,461 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC866 1 /* This is a MPC866 CPU */ +#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ +#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ +#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ + /* (it will be used if there is no */ + /* 'cpuclk' variable with valid value) */ + +#undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */ + /* (function measure_gclk() */ + /* will be called) */ +#ifdef CFG_MEASURE_CPUCLK +#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ +#endif + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM866M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ + +#define CONFIG_TIMESTAMP /* but print image timestmps */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: Default value of OR0 after reset + */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ + OR_SCY_15_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) + +/* + * Memory Periodic Timer Prescaler + * Periodic timer for refresh, start with refresh rate for 40 MHz clock + * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) + */ +#define CFG_MAMR_PTA 39 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_SCC1_ENET +#define CONFIG_FEC_ENET +#define CONFIG_ETHPRIME "SCC ETHERNET" + +#endif /* __CONFIG_H */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h new file mode 100644 index 0000000..8175703 --- /dev/null +++ b/include/configs/Total5200.h @@ -0,0 +1,415 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Check valid setting of revision define. + * Total5100 and Total5200 Rev.1 are identical except for the processor. + */ +#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) +#error CONFIG_TOTAL5200_REV must be 1 or 2 +#endif + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Video console + */ +#if 1 +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SED13806 +#define CONFIG_VIDEO_SED13806_16BPP + +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +/* #define CONFIG_VIDEO_BMP_LOGO */ +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN + +#define ADD_VIDEO_CMD CFG_CMD_BMP +#else +#define ADD_VIDEO_CMD 0 +#endif + +#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 + +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MGT5100 */ + +#define CONFIG_MII 1 +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* USB */ +#if 1 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_IDE | \ + ADD_VIDEO_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (TEXT_BASE == 0xFE000000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT \ + "setenv stdout serial;setenv stderr serial;" \ + "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/MPC5200/uImage\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +/* + * Flash configuration + */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#if CONFIG_TOTAL5200_REV==2 +# define CFG_MAX_FLASH_BANKS 3 /* max num of flash banks */ +# define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START } +#else +# define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +# define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#endif +#define CFG_FLASH_EMPTY_INFO +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#if CONFIG_TOTAL5200_REV==1 +# define CFG_FLASH_BASE 0xFE000000 +# define CFG_FLASH_SIZE 0x02000000 +#elif CONFIG_TOTAL5200_REV==2 +# define CFG_FLASH_BASE 0xFA000000 +# define CFG_FLASH_SIZE 0x06000000 +#endif /* CONFIG_TOTAL5200_REV */ + +#if defined(CFG_LOWBOOT) +# define CFG_ENV_ADDR 0xFE040000 +#else /* CFG_LOWBOOT */ +# define CFG_ENV_ADDR 0xFFF40000 +#endif /* CFG_LOWBOOT */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x40000 +#define CFG_ENV_SECT_SIZE 0x40000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 +#define CFG_MBAR 0xF0000000 /* 64 kB */ +#define CFG_FPGA_BASE 0xF0010000 /* 64 kB */ +#define CFG_CPLD_BASE 0xF0020000 /* 64 kB */ +#define CFG_LCD_BASE 0xF1000000 /* 4096 kB */ + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* dummy, 7-wire FEC does not have phy address */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + * + * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 + * Reserved 0 + * ALTs: CAN1/2 on PSC2, SPI on PSC3 00 + * CS7: Interrupt GPIO on PSC3_5 0 + * CS8: Interrupt GPIO on PSC3_4 0 + * ATA: reset default, changed in ATA driver 00 + * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 + * IRDA: reset default, changed in IrDA driver 000 + * ETHER: reset default, changed in Ethernet driver 0000 + * PCI_DIS: reset default, changed in PCI driver 0 + * USB_SE: reset default, changed in USB driver 0 + * USB: reset default, changed in USB driver 00 + * PSC3: SPI and UART functionality without CD 1100 + * Reserved 0 + * PSC2: CAN1/2 001 + * Reserved 0 + * PSC1: reset default, changed in AC'97 driver 000 + * + */ +#define CFG_GPS_PORT_CONFIG 0x00000C10 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#if defined (CONFIG_MGT5100) +# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */ +#endif + +#if CONFIG_TOTAL5200_REV==1 +# define CFG_BOOTCS_START CFG_FLASH_BASE +# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */ +# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ +# define CFG_CS0_START CFG_FLASH_BASE +# define CFG_CS0_SIZE 0x02000000 /* 32 MB */ +#else +# define CFG_BOOTCS_START (CFG_CS4_START + CFG_CS4_SIZE) +# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */ +# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ +# define CFG_CS4_START (CFG_CS5_START + CFG_CS5_SIZE) +# define CFG_CS4_SIZE 0x02000000 /* 32 MB */ +# define CFG_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ +# define CFG_CS5_START CFG_FLASH_BASE +# define CFG_CS5_SIZE 0x02000000 /* 32 MB */ +# define CFG_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ +#endif + +#define CFG_CS1_START CFG_FPGA_BASE +#define CFG_CS1_SIZE 0x00010000 /* 64 kB */ +#define CFG_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ + +#define CFG_CS2_START CFG_LCD_BASE +#define CFG_CS2_SIZE 0x00400000 /* 4096 kB */ +#define CFG_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ + +#if CONFIG_TOTAL5200_REV==1 +# define CFG_CS3_START CFG_CPLD_BASE +# define CFG_CS3_SIZE 0x00010000 /* 64 kB */ +# define CFG_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ +#else +# define CFG_CS3_START CFG_CPLD_BASE +# define CFG_CS3_SIZE 0x00010000 /* 64 kB */ +# define CFG_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ +#endif + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h new file mode 100644 index 0000000..3f29190 --- /dev/null +++ b/include/configs/VCMA9.h @@ -0,0 +1,284 @@ +/* + * (C) Copyright 2002, 2003 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Gary Jennejohn + * David Mueller + * + * Configuation settings for the MPL VCMA9 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ + +#define USE_920T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/*********************************************************** + * Command definition + ***********************************************************/ +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + /*CFG_CMD_JFFS2 |*/ \ + /*CFG_CMD_NAND |*/ \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_USB | \ + CFG_CMD_REGINFO | \ + CFG_CMD_FAT | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_BSP) + +/* this must be included after the definiton of CONFIG_COMMANDS */ +#include + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +/*********************************************************** + * I2C stuff: + * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at + * address 0x50 with 16bit addressing + ***********************************************************/ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ + +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ +#define CFG_ENV_SIZE 0x800 /* 2KB should be more than enough */ + +#undef CFG_I2C_EEPROM_ADDR_OVERFLOW +#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * Size of malloc() pool + */ +/*#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)*/ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CFG_MONITOR_LEN (256 * 1024) +#define CFG_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x20000300 +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ + +/************************************************************ + * USB support + ************************************************************/ +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_KEYBOARD 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 + +/* Enable needed helper functions */ +#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ + +/************************************************************ + * RTC + ************************************************************/ +#define CONFIG_RTC_S3C24X0 1 + + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_BOOTDELAY 5 +/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ +/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "VCMA9 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ + +#define CFG_ALT_MEMTEST +#define CFG_LOAD_ADDR 0x30800000 /* default load address */ + + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/* we configure PWM Timer 4 to 1us ~ 1MHz */ +/*#define CFG_HZ 1000000 */ +#define CFG_HZ 1562500 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* support BZIP2 compression */ +#define CONFIG_BZIP2 1 + +/************************************************************ + * Ident + ************************************************************/ +/*#define VERSION_TAG "released"*/ +#define VERSION_TAG "unstable" +#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ +#if 0 +#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ +#endif + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ +#endif + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + +#if 0 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#endif + + +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 + +#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 + +/*----------------------------------------------------------------------- + * NAND flash settings + */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define NAND_WAIT_READY(nand) NF_WaitRB() + +#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) +#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW) + + +#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d) +#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d) +#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d) +#define WRITE_NAND(d, adr) NF_Write(d) +#define READ_NAND(adr) NF_Read() +/* the following functions are NOP's because S3C24X0 handles this in hardware */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_MTD_NAND_ECC_JFFS2 1 + +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h new file mode 100644 index 0000000..3ca137e --- /dev/null +++ b/include/configs/VOH405.h @@ -0,0 +1,457 @@ +/* + * (C) Copyright 2001-2003 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_VOH405 1 /* ...on a VOH405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ + +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CONFIG_ATAPI 1 /* ATAPI for Travelstar */ + +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_IDE1_OFFSET 0x0010 + +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */ + +#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) +# define CFG_RAMBOOT 1 +#else +# undef CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ +#if 0 /* test-only */ +/* CAT24WC08/16... */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#else +/* CAT24WC32/64... */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ +#endif +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define DUART0_BA 0xF0000400 /* DUART Base Address */ +#define DUART1_BA 0xF0000408 /* DUART Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ +#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +/* Memory Bank 4 (Epson VGA) initialization */ +#define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ +#define CFG_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * LCD Setup + */ + +#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ +#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ +#define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ +#define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ + +#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) + +/*----------------------------------------------------------------------- + * FPGA stuff + */ + +#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ + +/* FPGA internal regs */ +#define CFG_FPGA_CTRL 0x000 + +/* FPGA Control Reg */ +#define CFG_FPGA_CTRL_CF_RESET 0x0001 +#define CFG_FPGA_CTRL_WDI 0x0002 +#define CFG_FPGA_CTRL_PS2_RESET 0x0020 + +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO + */ +#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555440 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xF7FE0017 + +#define CFG_DUART_RST (0x80000000 >> 14) +#define CFG_LCD_ENDIAN (0x80000000 >> 7) +#define CFG_LCD0_RST (0x80000000 >> 30) +#define CFG_LCD1_RST (0x80000000 >> 31) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 1 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h new file mode 100644 index 0000000..f2f3ea7 --- /dev/null +++ b/include/configs/VOM405.h @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2001-2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_VOM405 1 /* ...on a VOM405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_BSP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +#undef CONFIG_PRAM /* no "protected RAM" */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) +# define CFG_RAMBOOT 1 +#else +# undef CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +#define CAN_BA 0xF0000000 /* CAN Base Address */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ +/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ +/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ +/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ +#define CFG_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ +#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ +#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ +#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ +#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ +#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 1 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h new file mode 100644 index 0000000..92bade5 --- /dev/null +++ b/include/configs/VoVPN-GW.h @@ -0,0 +1,406 @@ +/* + * (C) Copyright 2004 + * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) + * + * Support for the Elmeg VoVPN Gateway Module + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* define cpu used */ +#define CONFIG_MPC8272 1 + +/* define busmode: 8260 */ +#undef CONFIG_BUSMODE_60x + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#ifdef CONFIG_CLKIN_66MHz +#define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#else +#define CONFIG_8260_CLKIN 100000000 /* in Hz */ +#endif + +/* call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* have misc_init_r() function */ +#define CONFIG_MISC_INIT_R 1 + +/* have reset_phy_r() function */ +#define CONFIG_RESET_PHY_R 1 + +/* have special reset function */ +#define CONFIG_HAVE_OWN_RESET 1 + +/* allow serial and ethaddr to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* watchdog disabled */ +#undef CONFIG_WATCHDOG + +/* include support for bzip2 compressed images */ +#undef CONFIG_BZIP2 + +/* status led */ +#undef CONFIG_STATUS_LED /* XXX jse */ + +/* vendor parameter protection */ +#define CONFIG_ENV_OVERWRITE + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC +#undef CONFIG_CONS_ON_SCC +#undef CONFIG_CONS_NONE +#define CONFIG_CONS_INDEX 1 + +/* serial port default baudrate */ +#define CONFIG_BAUDRATE 115200 + +/* echo on for serial download */ +#define CONFIG_LOADS_ECHO 1 + +/* don't allow baudrate change */ +#undef CFG_LOADS_BAUD_CHANGE + +/* supported baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC +#define CONFIG_ETHER_ON_FCC +#undef CONFIG_ETHER_NONE + +#ifdef CONFIG_ETHER_ON_FCC + +/* which SCC/FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 1 + +/* Marvell Switch SMI base addr */ +#define CFG_PHY_ADDR 0x10 + +/* FCC1 RMII REFCLK is CLK10 */ +#define CFG_CMXFCR_VALUE CMXFCR_TF1CS_CLK10 +#define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK) + +/* BDs and buffers on 60x bus */ +#define CFG_CPMFCR_RAMTYPE 0 + +/* Local Protect, Full duplex, Flowcontrol, RMII */ +#define CFG_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\ + FCC_PSMR_FCE|FCC_PSMR_RMII) + +/* bit-bang MII PHY management */ +#define CONFIG_BITBANGMII + +#define MDIO_PORT 1 /* Port B */ +#define CFG_MDIO_PIN 0x00002000 /* PB18 */ +#define CFG_MDC_PIN 0x00001000 /* PB19 */ +#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) +#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) +#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) +#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ + else iop->pdat &= ~CFG_MDIO_PIN +#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ + else iop->pdat &= ~CFG_MDC_PIN +#define MIIDELAY udelay(1) + +#endif + +/* configure commands */ +#define CONFIG_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_BDI | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IMLS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * boot options & environment + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "run flash_self" +#undef CONFIG_BOOTARGS +#define CONFIG_EXTRA_ENV_SETTINGS \ +"clean_nv=erase fff20000 ffffffff\0" \ +"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \ +"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \ +"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \ +"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \ +"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ +"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \ +"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \ +"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \ +"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \ +"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \ +"fstype=cramfs\0" \ +"rootpath=/root_fs\0" \ +"uboot=PPC/u-boot.bin\0" \ +"kernel=PPC/uImage\0" \ +"kernel_addr=ffe00000\0" \ +"fs=PPC/root_fs\0" \ +"console=ttyS0\0" \ +"netdev=eth0\0" \ +"rootdev=31:3\0" \ +"ethaddr=00:09:4f:01:02:03\0" \ +"ipaddr=10.0.0.201\0" \ +"netmask=255.255.255.0\0" \ +"serverip=10.0.0.136\0" \ +"gatewayip=10.0.0.10\0" \ +"hostname=bastard\0" \ +"" + + +/* + * miscellaneous configurable options + */ + +/* undef to save memory */ +#define CFG_LONGHELP + +/* monitor command prompt */ +#define CFG_PROMPT "=> " + +/* console i/o buffer size */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 +#else +#define CFG_CBSIZE 256 +#endif + +/* print buffer size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +/* max number of command args */ +#define CFG_MAXARGS 16 + +/* boot argument buffer size */ +#define CFG_BARGSIZE CFG_CBSIZE + +/* memtest works on */ +#define CFG_MEMTEST_START 0x00100000 +/* 1 ... 15 MB in DRAM */ +#define CFG_MEMTEST_END 0x00f00000 +/* full featured memtest */ +#define CFG_ALT_MEMTEST + +/* default load address */ +#define CFG_LOAD_ADDR 0x00100000 + +/* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 + +/* configure flash */ +#define CFG_FLASH_BASE 0xff800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 64 +#define CFG_FLASH_SIZE 8 +#undef CFG_FLASH_16BIT +#define CFG_FLASH_ERASE_TOUT 240000 +#define CFG_FLASH_WRITE_TOUT 500 +#define CFG_FLASH_LOCK_TOUT 500 +#define CFG_FLASH_UNLOCK_TOUT 10000 +#define CFG_FLASH_PROTECTION + +/* monitor in flash */ +#define CFG_MONITOR_OFFSET 0x00700000 + +/* environment in flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00020000) +#define CFG_ENV_SIZE 0x00020000 +#define CFG_ENV_SECT_SIZE 0x00020000 + +/* + * Initial memory map for linux + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) + +/* hard reset configuration words */ +#ifdef CONFIG_CLKIN_66MHz +#define CFG_HRCW_MASTER 0x04643050 +#else +#error NO HRCW FOR 100MHZ SPECIFIED !!! +#endif +#define CFG_HRCW_SLAVE1 0x00000000 +#define CFG_HRCW_SLAVE2 0x00000000 +#define CFG_HRCW_SLAVE3 0x00000000 +#define CFG_HRCW_SLAVE4 0x00000000 +#define CFG_HRCW_SLAVE5 0x00000000 +#define CFG_HRCW_SLAVE6 0x00000000 +#define CFG_HRCW_SLAVE7 0x00000000 + +/* internal memory mapped register */ +#define CFG_IMMR 0xF0000000 + +/* definitions for initial stack pointer and data area (in DPRAM) */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE (32*1024*1024) +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_FLASH (CFG_FLASH_BASE + CFG_MONITOR_OFFSET) +#define CFG_MONITOR_LEN 0x00020000 +#define CFG_MALLOC_LEN 0x00020000 + +/* boot flags */ +#define BOOTFLAG_COLD 0x01 /* normal power-on */ +#define BOOTFLAG_WARM 0x02 /* software reboot */ + +/* cache configuration */ +#define CFG_CACHELINE_SIZE 32 /* for MPC8260 */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */ +#endif + +/* + * HIDx - Hardware Implementation-dependent Registers + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|\ + HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/* RMR - reset mode register - turn on checkstop reset enable */ +#define CFG_RMR RMR_CSRE + +/* BCR - bus configuration */ +#define CFG_BCR 0x00000000 + +/* SIUMCR - siu module configuration */ +#define CFG_SIUMCR 0x4905c000 + +/* SYPCR - system protection control */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR 0xffffff87 +#else +#define CFG_SYPCR 0xffffff83 +#endif + +/* TMCNTSC - time counter status and control */ +/* clear interrupts XXX jse */ +/*#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\ + TMCNTSC_TCF|TMCNTSC_TCE) + +/* PISCR - periodic interrupt status and control */ +/* clear interrupts XXX jse */ +/*#define CFG_PISCR (PISCR_PS) */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/* SCCR - system clock control */ +#define CFG_SCCR 0x000001a9 + +/* RCCR - risc controller configuration */ +#define CFG_RCCR 0 + +/* + * MEMORY MAP + * ---------- + * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) + * CS1 - SDRAM 32MB/64Bit base=0x00000000 + * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000 + * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000 + * CS4 - DSP/SL3 1MB/16Bit base=0xf0300000 + * CS5 - DSP/SL4 1MB/16Bit base=0xf0400000 + * CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored) + * x - IMMR 384KB base=0xf0000000 + */ +/* XXX jse 100MHz TODO */ +#define CFG_BR0_PRELIM 0xff800801 +#define CFG_OR0_PRELIM 0xff801e44 +#define CFG_BR1_PRELIM 0x00000041 +#define CFG_OR1_PRELIM 0xfe002ec0 +#if 1 +#define CFG_BR2_PRELIM 0xf0101001 +#define CFG_OR2_PRELIM 0xfff00ef4 +#define CFG_BR3_PRELIM 0xf0201001 +#define CFG_OR3_PRELIM 0xfff00ef4 +#define CFG_BR4_PRELIM 0xf0301001 +#define CFG_OR4_PRELIM 0xfff00ef4 +#define CFG_BR5_PRELIM 0xf0401001 +#define CFG_OR5_PRELIM 0xfff00ef4 +#else +#define CFG_BR2_PRELIM 0xf0101081 +#define CFG_OR2_PRELIM 0xfff00104 +#define CFG_BR3_PRELIM 0xf0201081 +#define CFG_OR3_PRELIM 0xfff00104 +#define CFG_BR4_PRELIM 0xf0301081 +#define CFG_OR4_PRELIM 0xfff00104 +#define CFG_BR5_PRELIM 0xf0401081 +#define CFG_OR5_PRELIM 0xfff00104 +#endif +#define CFG_BR7_PRELIM 0xf0500881 +#define CFG_OR7_PRELIM 0xffff8104 +#define CFG_MPTPR 0x2700 +#define CFG_PSDMR 0x822a2452 /* optimal */ +/*#define CFG_PSDMR 0x822a48a3 */ /* relaxed */ +#define CFG_PSRT 0x1a + +/* "bad" address */ +#define CFG_RESET_ADDRESS 0x40000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h new file mode 100644 index 0000000..8dc623e --- /dev/null +++ b/include/configs/W7OLMC.h @@ -0,0 +1,326 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_4xx 1 /* ...member of PPC405 family */ +#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ +#define CONFIG_W7OLMC 1 /* ...specifically an LMC */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#if 1 +#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ +#else +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ +#endif + +#undef CONFIG_BOOTARGS + +#define CONFIG_LOADADDR F0080000 + +#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.1.2 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ + +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ + CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ + +#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ +#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ +#undef CFG_HUSH_PARSER /* No hush parse for U-Boot */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 384000 + + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE {9600} + +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ +/* resource configuration */ +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Set up values for external bus controller + * used by cpu_init.c + *----------------------------------------------------------------------- + */ + /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */ +#undef CONFIG_USE_PERWE + +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* bank 0 is boot flash */ +/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ +#define CFG_W7O_EBC_PB0AP 0x03050440 +/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ +#define CFG_W7O_EBC_PB0CR 0xFFE38000 + +/* bank 1 is main flash */ +/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ +#define CFG_EBC_PB1AP 0x05850240 +/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ +#define CFG_EBC_PB1CR 0xF00FC000 + +/* bank 2 is RTC/NVRAM */ +/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ +#define CFG_EBC_PB2AP 0x03000440 +/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ +#define CFG_EBC_PB2CR 0xFC018000 + +/* bank 3 is FPGA 0 */ +/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ +#define CFG_EBC_PB3AP 0x02000400 +/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ +#define CFG_EBC_PB3CR 0xFD01A000 + +/* bank 4 is FPGA 1 */ +/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ +#define CFG_EBC_PB4AP 0x02000400 +/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ +#define CFG_EBC_PB4CR 0xFD11A000 + +/* bank 5 is FPGA 2 */ +/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ +#define CFG_EBC_PB5AP 0x02000400 +/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ +#define CFG_EBC_PB5CR 0xFD21A000 + +/* bank 6 is unused */ +/* pb6ap = 0 */ +#define CFG_EBC_PB6AP 0x00000000 +/* pb6cr = 0 */ +#define CFG_EBC_PB6CR 0x00000000 + +/* bank 7 is LED register */ +/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ +#define CFG_W7O_EBC_PB7AP 0x03050440 +/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ +#define CFG_W7O_EBC_PB7CR 0xFE01C000 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ +#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */ + +#if 1 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ +#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +/*define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */ +#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR + +#else /* Use Boot Flash for environment variables */ +/*----------------------------------------------------------------------- + * Flash EEPROM for environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */ + +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC08) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_I2C_MULTI_EEPROMS +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ +#endif + +/* + * Init Memory Controller: + */ +#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in RAM) + */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * FPGA(s) configuration + */ +#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ +#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */ +#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ +#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ +#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h new file mode 100644 index 0000000..2bd98b3 --- /dev/null +++ b/include/configs/W7OLMG.h @@ -0,0 +1,327 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_4xx 1 /* ...member of PPC405 family */ +#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ +#define CONFIG_W7OLMG 1 /* ...specifically an LMG */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#if 1 +#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ +#else +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ +#endif + +#undef CONFIG_BOOTARGS + +#define CONFIG_LOADADDR F0080000 + +#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.1.2 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ + CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \ + CFG_CMD_DTT) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ + +#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ +#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ +#undef CFG_HUSH_PARSER /* No hush parse for U-Boot */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 384000 + + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE {9600} + +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ +/* resource configuration */ +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Set up values for external bus controller + * used by cpu_init.c + *----------------------------------------------------------------------- + */ + /* use PerWE instead of PCI_INT ( these functions share a pin ) */ +#define CONFIG_USE_PERWE 1 + +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* bank 0 is boot flash */ +/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ +#define CFG_W7O_EBC_PB0AP 0x03050440 +/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ +#define CFG_W7O_EBC_PB0CR 0xFFE38000 + +/* bank 1 is main flash */ +/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ +#define CFG_EBC_PB1AP 0x04850240 +/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ +#define CFG_EBC_PB1CR 0xF00FC000 + +/* bank 2 is RTC/NVRAM */ +/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ +#define CFG_EBC_PB2AP 0x03000440 +/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ +#define CFG_EBC_PB2CR 0xFC018000 + +/* bank 3 is FPGA 0 */ +/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ +#define CFG_EBC_PB3AP 0x02000400 +/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ +#define CFG_EBC_PB3CR 0xFD01A000 + +/* bank 4 is SAM 8 bit range */ +/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ +#define CFG_EBC_PB4AP 0x02840380 +/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ +#define CFG_EBC_PB4CR 0xFE878000 + +/* bank 5 is SAM 16 bit range */ +/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */ +#define CFG_EBC_PB5AP 0x05040d80 +/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ +#define CFG_EBC_PB5CR 0xFD87A000 + +/* bank 6 is unused */ +/* pb6ap = 0 */ +#define CFG_EBC_PB6AP 0x00000000 +/* pb6cr = 0 */ +#define CFG_EBC_PB6CR 0x00000000 + +/* bank 7 is LED register */ +/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ +#define CFG_W7O_EBC_PB7AP 0x03050440 +/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ +#define CFG_W7O_EBC_PB7CR 0xFE01C000 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ +#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */ + +#if 1 /* Use NVRAM for environment variables */ +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ +#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +/*define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */ +#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR + +#else /* Use Boot Flash for environment variables */ +/*----------------------------------------------------------------------- + * Flash EEPROM for environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */ + +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (ATMEL 24C04N) + */ +#define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_I2C_MULTI_EEPROMS +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ +#endif + +/* + * Init Memory Controller: + */ +#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in RAM) + */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * FPGA(s) configuration + */ +#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ +#define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */ +#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ +#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ +#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h new file mode 100644 index 0000000..d92f81f --- /dev/null +++ b/include/configs/WUH405.h @@ -0,0 +1,388 @@ +/* + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IDENT_STRING " $Name: $" + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_WUH405 1 /* ...on a WUH405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#undef CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFFC0000 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ + +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ +#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x92015480 +#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ +#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ +#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ +#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ + +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define DUART0_BA 0xF0000400 /* DUART Base Address */ +#define DUART1_BA 0xF0000408 /* DUART Base Address */ +#define DUART2_BA 0xF0000410 /* DUART Base Address */ +#define DUART3_BA 0xF0000418 /* DUART Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define CFG_NAND_BASE 0xF4000000 + +/*----------------------------------------------------------------------- + * FPGA stuff + */ +#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ +#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ + +/* FPGA program pin configuration */ +#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ +#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs -> GPIO + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x40000550 +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555445 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xF7FE0014 + +#define CFG_DUART_RST (0x80000000 >> 14) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#if 0 +#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 +#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 +#endif +#if 1 +#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 +#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 +#endif +#if 0 +#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 +#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h new file mode 100644 index 0000000..9b32514 --- /dev/null +++ b/include/configs/XPEDITE1K.h @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * config for XPedite1000 from XES Inc. + * Ported from EBONY config by Travis B. Sawyer + * (C) Copyright 2003 Sandburst Corporation + * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 +#define CONFIG_440GX 1 /* 440 GX */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + + +/* POST support */ +#define CONFIG_POST (CFG_POST_RTC | \ + CFG_POST_I2C) + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ + +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) +#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) + +#define USR_LED0 0x00000080 +#define USR_LED1 0x00000100 +#define USR_LED2 0x00000200 +#define USR_LED3 0x00000400 + +#ifndef __ASSEMBLY__ +extern unsigned long in32(unsigned int); +extern void out32(unsigned int, unsigned long); + +#define LED0_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED0)) +#define LED1_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED1)) +#define LED2_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED2)) +#define LED3_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED3)) + +#define LED0_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED0)) +#define LED1_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED1)) +#define LED2_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED2)) +#define LED3_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED3)) +#endif + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */ +#define CONFIG_RTC_M41T11 1 +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 2000 + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ +#define CONFIG_VERY_BIG_RAM 1 +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7f +#define CFG_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */ + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_SIZE 0x100 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x100 +#define CFG_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CONFIG_BOOTARGS "root=/dev/hda1 " +#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ +#define CONFIG_BOOTDELAY 5 /* disable autoboot */ +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */ +#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */ +#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ +#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ +#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_DIAG | \ + CFG_CMD_FAT ) + +/* CFG_CMD_DHCP | \ */ +/* CFG_CMD_KGDB | \ */ + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CFG_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h new file mode 100644 index 0000000..37ef105 --- /dev/null +++ b/include/configs/Yukon8220.h @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2004 + * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC8220 1 +#define CONFIG_YUKON8220 1 /* ... on Yukon board */ + +/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to + determine the CPU speed. */ +#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ +#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ + +/* Define this for PSC console +#define CONFIG_PSC_CONSOLE 1 +*/ + +#define CONFIG_EXTUART_CONSOLE 1 + +#ifdef CONFIG_EXTUART_CONSOLE +# define CONFIG_CONS_INDEX 1 +# define CFG_NS16550_SERIAL +# define CFG_NS16550 +# define CFG_NS16550_REG_SIZE 1 +# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008) +# define CFG_NS16550_CLK 18432000 +#endif + +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +#define CONFIG_NET_MULTI +#define CONFIG_MII + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTARGS "root=/dev/ram rw" +#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61 +#define CONFIG_IPADDR 192.162.1.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.162.1.1 +#define CONFIG_GATEWAYIP 192.162.1.1 +#define CONFIG_HOSTNAME yukon +#define CONFIG_OVERWRITE_ETHADDR_ONCE + + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_MODULE 1 + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 +/* +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 256 +*/ + +/* If CFG_AMD_BOOT is defined, the the system will boot from AMD. + else undefined it will boot from Intel Strata flash */ +#define CFG_AMD_BOOT 1 + +/* + * Flexbus Chipselect configuration + */ +#if defined (CFG_AMD_BOOT) +#define CFG_CS0_BASE 0xfff0 +#define CFG_CS0_MASK 0x00080000 /* 512 KB */ +#define CFG_CS0_CTRL 0x003f0d40 + +#define CFG_CS1_BASE 0xfe00 +#define CFG_CS1_MASK 0x01000000 /* 16 MB */ +#define CFG_CS1_CTRL 0x003f1540 +#else +#define CFG_CS0_BASE 0xff00 +#define CFG_CS0_MASK 0x01000000 /* 16 MB */ +#define CFG_CS0_CTRL 0x003f1540 + +#define CFG_CS1_BASE 0xfe08 +#define CFG_CS1_MASK 0x00080000 /* 512 KB */ +#define CFG_CS1_CTRL 0x003f0d40 +#endif + +#define CFG_CS2_BASE 0xf100 +#define CFG_CS2_MASK 0x00040000 +#define CFG_CS2_CTRL 0x003f1140 + +#define CFG_CS3_BASE 0xf200 +#define CFG_CS3_MASK 0x00040000 +#define CFG_CS3_CTRL 0x003f1100 + + +#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) +#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16) + +#if defined (CFG_AMD_BOOT) +#define CFG_AMD_BASE CFG_FLASH0_BASE +#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000 +#define CFG_FLASH_BASE CFG_AMD_BASE +#else +#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000 +#define CFG_AMD_BASE CFG_FLASH1_BASE +#define CFG_FLASH_BASE CFG_INTEL_BASE +#endif + +#define CFG_CPLD_BASE (CFG_CS2_BASE << 16) +#define CFG_FPGA_BASE (CFG_CS3_BASE << 16) + + +#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ +#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */ + +#define CFG_FLASH_CHECKSUM +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#if defined (CFG_AMD_BOOT) +#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE) +#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE +#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE +#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE) +#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE +#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE +#else +#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE) +#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE +#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE +#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE) +#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE +#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE +#endif + +#define CONFIG_ENV_OVERWRITE 1 + +#if defined CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_EEPROM +#elif defined CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_EEPROM +#elif defined CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#endif + +#ifndef CFG_JFFS2_FIRST_SECTOR +#define CFG_JFFS2_FIRST_SECTOR 0 +#endif +#ifndef CFG_JFFS2_FIRST_BANK +#define CFG_JFFS2_FIRST_BANK 0 +#endif +#ifndef CFG_JFFS2_NUM_BANKS +#define CFG_JFFS2_NUM_BANKS 1 +#endif +#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 +#define CFG_SRAM_BASE (CFG_MBAR + 0x20000) +#define CFG_SRAM_SIZE 0x8000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) +#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* SDRAM configuration */ +#define CFG_SDRAM_TOTAL_BANKS 2 +#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */ +#define CFG_SDRAM_SPD_SIZE 0x40 +#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */ + +/* SDRAM drive strength register */ +#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ + (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \ + (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \ + (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT)) + +/* + * Ethernet configuration + */ +#define CONFIG_MPC8220_FEC 1 +#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ +#define CONFIG_PHY_ADDR 0x18 + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#endif /* __CONFIG_H */ diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h new file mode 100644 index 0000000..f71e691 --- /dev/null +++ b/include/configs/ZPC1900.h @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2003-2004 Arabella Software Ltd. + * Yuli Barcohen + * + * U-Boot configuration for Zephyr Engineering ZPC.1900 board. + * This port was developed and tested on Revision C board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */ +#define CPU_ID_STR "MPC8265" +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#undef DEBUG + +#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */ + +/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ + +#ifdef CONFIG_ETHER_ON_FCC + +#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */ + +#if (CONFIG_ETHER_INDEX == 2) +/* + * - Rx clock is CLK13 + * - Tx clock is CLK14 + * - Select bus for bd/buffers (see 28-13) + * - Full duplex + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_INDEX */ + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 2 /* Port C */ +#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +#define MDIO_READ ((iop->pdat & 0x00400000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + +#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + +#define MIIDELAY udelay(1) + +#endif /* CONFIG_ETHER_ON_FCC */ + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#endif + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_FLASH_BASE 0xFFE00000 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ + +#define CFG_DEFAULT_IMMR 0x0F010000 + +#define CFG_IMMR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 64 +#define CFG_FLSIMM_BASE 0xFC000000 +#define CFG_LSDRAM_BASE 0xFE000000 +#define CFG_BCSR 0xFEA00000 +#define CFG_EEPROM 0xFEB00000 + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define BCSR_PCI_MODE 0x01 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* Hard reset configuration word */ +#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\ + HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\ + HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10 |\ + HRCW_MODCK_H0101 \ + ) /* 0x16828605 */ +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM) +#define CFG_ENV_IS_IN_NVRAM 1 +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +# define CFG_ENV_SECT_SIZE 0x10000 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#else +# define CFG_ENV_ADDR (CFG_EEPROM + 0x400) +# define CFG_ENV_SIZE 0x1000 +# define CFG_NVRAM_ACCESS_ROUTINE +#endif + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) + +#define CFG_HID2 0 + +#define CFG_SIUMCR 0x42200000 +#define CFG_SYPCR 0xFFFFFFC3 +#define CFG_BCR 0x90400000 +#define CFG_SCCR SCCR_DFBRG01 + +#define CFG_RMR RMR_CSRE +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) +#define CFG_RCCR 0 + +#define CFG_PSDMR 0x014EB45A +#define CFG_PSRT 0x0C +#define CFG_LSDMR 0x008AB552 +#define CFG_LSRT 0x0E +#define CFG_MPTPR 0x4000 + +#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 +#define CFG_OR0_PRELIM 0xFFE00856 +#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 +#define CFG_OR5_PRELIM 0xFFFF03F6 +#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801 +#define CFG_OR6_PRELIM 0xFE000856 +#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 +#define CFG_OR7_PRELIM 0xFFFF83F6 + +#define CFG_RESET_ADDRESS 0xC0000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h new file mode 100644 index 0000000..f163d00 --- /dev/null +++ b/include/configs/ZUMA.h @@ -0,0 +1,391 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ +#define CONFIG_ETHER_PORT_MII /* use two MII ports */ +#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */ + +#ifndef __ASSEMBLY__ +#include +#endif + +#include "../board/evb64260/local.h" + +#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ +#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */ + +/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */ + +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ + +#define CONFIG_ECC /* enable ECC support */ + +#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */ + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_EARLY_INIT_F +#define CFG_BOARD_ASM_INIT + +#define CFG_BOARD_NAME "Zuma APv2" + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial + * cable onto the second DUART channel, change the CFG_DUART port from 1 + * to 0 below. + * + * to use the MPSC, #define CONFIG_MPSC. If you have wired up another + * mpsc channel, change CONFIG_MPSC_PORT to the desired value. + */ +#define CONFIG_MPSC + +#define CONFIG_MPSC_PORT 0 + +#define CONFIG_NET_MULTI /* attempt all available adapters */ + +/* define this if you want to enable GT MAC filtering */ +#define CONFIG_GT_USE_MAC_HASH_TABLE + +#if 1 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#undef CONFIG_BOOTARGS + +#define CONFIG_BOOTCOMMAND \ + "tftpboot && " \ + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:" \ + "$netmask:$hostname:eth0:none panic=5 && bootm" + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_ALTIVEC /* undef to disable */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MII /* enable MII commands */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_DATE) + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" +#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" +*/ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00300000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ + +#define CFG_BUS_HZ 133000000 /* 133 MHz */ + +#define CFG_BUS_CLK CFG_BUS_HZ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_LOCK + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xfff00000 +#define CFG_RESET_ADDRESS 0xfff00100 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +/* areas to map different things with the GT in physical space */ +#define CFG_DRAM_BANKS 4 +#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ + +/* What to put in the bats. */ +#define CFG_MISC_REGION_BASE 0xf0000000 + +/* Peripheral Device section */ +#define CFG_GT_REGS 0xf8000000 /* later mapped GT_REGS */ +#define CFG_DEV_BASE 0xf0000000 +#define CFG_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/ +#define CFG_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */ +#define CFG_DEV2_SIZE _8M /* unused */ +#define CFG_DEV3_SIZE _8M /* unused */ + +#define CFG_DEV0_PAR 0xc498243c + /* c 4 9 8 2 4 3 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ + /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */ + /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */ + +#define CFG_DEV1_PAR 0xc01b6ac5 + /* c 0 1 b 6 a c 5 */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ + /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */ + /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */ + + +#define CFG_8BIT_BOOT_PAR 0xc00b5e7c + +#define CFG_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ +#define CFG_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */ +#define CFG_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */ +#define CFG_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */ + /* GPP[27:24] (27 is int4, rest are GPP) */ + +#define CFG_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */ +#define CFG_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */ + +#define CFG_SDRAM_CONFIG 0xe4e18200 /* 0x448 */ + /* idmas use buffer 1,1 + comm use buffer 1 + pci use buffer 0,0 (pci1->0 pci0->0) + cpu use buffer 1 (R*18) + normal load (see also ifdef HVL) + standard SDRAM (see also ifdef REG) + non staggered refresh */ + /* 31:26 25 23 20 19 18 16 */ + /* 111001 00 111 0 0 00 1 */ + + /* refresh count=0x200 + phy interleave disable (by default, + set later by dram config..) + virt interleave enable */ + /* 15 14 13:0 */ + /* 1 0 0x200 */ + +#define CFG_DEV0_SPACE CFG_DEV_BASE +#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) +#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) +#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) + +/*----------------------------------------------------------------------- + * PCI stuff + */ + +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* PCI MEMORY MAP section */ +#define CFG_PCI0_MEM_BASE 0x80000000 +#define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI1_MEM_BASE 0x88000000 +#define CFG_PCI1_MEM_SIZE _128M + +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) +#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) + +/* PCI I/O MAP section */ +#define CFG_PCI0_IO_BASE 0xfa000000 +#define CFG_PCI0_IO_SIZE _16M +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M + +#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) +#define CFG_PCI0_IO_SPACE_PCI 0x00000000 +#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) +#define CFG_PCI1_IO_SPACE_PCI 0x00000000 + + +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITE_THRU not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT0U CFG_IBAT0U + +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */ +#define CFG_IBAT2L BATL_NO_ACCESS +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* GT regs, bootrom, all the devices, PCI I/O */ +#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 130 /* max number of sectors on one chip */ + +#define CFG_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ +#define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_CFI 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ +#define CFG_ENV_ADDR (0xfff80000 - CFG_ENV_SECT_SIZE) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/74xx_7xx.h for the defines used here + */ + +#define CFG_L2 + +#ifdef CONFIG_750CX +#define L2_INIT 0 +#else +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#endif + +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/*------------------------------------------------------------------------ + * Real time clock + */ +#define CONFIG_RTC_DS1302 + + +/*------------------------------------------------------------------------ + * Galileo I2C driver + */ +#define CONFIG_GT_I2C + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h new file mode 100644 index 0000000..c410891 --- /dev/null +++ b/include/configs/adsvix.h @@ -0,0 +1,347 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ +#define CONFIG_ADSVIX 1 /* on a Adsvix Board */ +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define RTC + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on ADSVIX */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 192.168.1.99 +#define CONFIG_BOOTCOMMAND "run boot_flash" +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ + " rw root=/dev/ram initrd=0xa0800000,5m" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "program_boot_cf=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if pinit on && " \ + "ide reset && " \ + "fatload ide 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_cf=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if pinit on && " \ + "ide reset && " \ + "fatload ide 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_cf=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if pinit on && " \ + "ide reset && " \ + "fatload ide 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_cf=" \ + "if pinit on && " \ + "ide reset && " \ + "fatload ide 0 0xa0030000 uzImage && " \ + "fatload ide 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "program_boot_mmc=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_mmc=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_mmc=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa0030000 uzImage && " \ + "fatload mmc 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "boot_flash=" \ + "cp.b 0x1c0000 0xa0800000 0x500000; " \ + "bootm 0x40000\0" \ + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ + +#define CFG_GPSR0_VAL 0x00018004 +#define CFG_GPSR1_VAL 0x004F0080 +#define CFG_GPSR2_VAL 0x13EFC000 +#define CFG_GPSR3_VAL 0x0006E032 +#define CFG_GPCR0_VAL 0x084AFE1A +#define CFG_GPCR1_VAL 0x003003F2 +#define CFG_GPCR2_VAL 0x0C014000 +#define CFG_GPCR3_VAL 0x00000C00 +#define CFG_GPDR0_VAL 0xCBC3BFFC +#define CFG_GPDR1_VAL 0x00FFABF3 +#define CFG_GPDR2_VAL 0x1EEFFC00 +#define CFG_GPDR3_VAL 0x0187EC32 +#define CFG_GAFR0_L_VAL 0x84400000 +#define CFG_GAFR0_U_VAL 0xA51A8010 +#define CFG_GAFR1_L_VAL 0x699A955A +#define CFG_GAFR1_U_VAL 0x0005A0AA +#define CFG_GAFR2_L_VAL 0x40000000 +#define CFG_GAFR2_U_VAL 0x0109A400 +#define CFG_GAFR3_L_VAL 0x54000000 +#define CFG_GAFR3_U_VAL 0x00001409 + +#define CFG_PSSR_VAL 0x20 + +/* + * Clock settings + */ +#define CFG_CKEN 0x00400200 +#define CFG_CCCR 0x02000290 /* 520Mhz */ +/* #define CFG_CCCR 0x02000210 416 Mhz */ + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x23F2B3DB +#define CFG_MSC1_VAL 0x0000CCD1 +#define CFG_MSC2_VAL 0x0000B884 +#define CFG_MDCNFG_VAL 0x08000AC8 +#define CFG_MDREFR_VAL 0x0000001E +#define CFG_MDMRS_VAL 0x00000000 + +#define CFG_FLYCNFG_VAL 0x00010001 +#define CFG_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000002 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00000000 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00000000 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x00000000 + +#define CONFIG_PXA_PCMCIA 1 +#define CONFIG_PXA_IDE 1 + +#define CONFIG_PCMCIA_SLOT_A 1 +/* just to keep build system happy */ + +#define CFG_PCMCIA_MEM_ADDR 0x28000000 +#define CFG_PCMCIA_MEM_SIZE 0x04000000 + + +#define CFG_IDE_MAXBUS 1 +/* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 +/* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR 0x20000000 + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 0x1f0 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET 0x1f0 + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x3f0 + +/* + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x20000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/aev.h b/include/configs/aev.h new file mode 100644 index 0000000..aa6bc91 --- /dev/null +++ b/include/configs/aev.h @@ -0,0 +1,401 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ +#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ +#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ +#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ +#define CONFIG_AEVFIFO 1 +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#ifdef CONFIG_AEVFIFO +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +/* #define CONFIG_PCI_SCAN_SHOW 1 */ + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 +#endif /* CONFIG_AEVFIFO */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_I2C) + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +/* preserve space for the post_word at end of on-chip SRAM */ +#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_BMP_CMD | \ + CFG_CMD_PCI | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_TIMESTAMP /* display image timestamps */ + +#if (TEXT_BASE == 0xFC000000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "console=ttyS0,${baudrate}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "bootfile=/tftpboot/tqm5200/uImage\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC05FFFF\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if defined(CFG_IPBSPEED_133) +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. + */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#ifdef CONFIG_TQM5200_REV100 +#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ +#else +#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ +#endif + +/* + * I2C clock frequency + * + * Please notice, that the resulting clock frequency could differ from the + * configured value. This is because the I2C clock is derived from system + * clock over a frequency divider with only a few divider values. U-boot + * calculates the best approximation for CFG_I2C_SPEED. However the calculated + * approximation allways lies below the configured value, never above. + */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work + * also). For other EEPROMs configuration should be verified. On Mini-FAP the + * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the + * same configuration could be used. + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ + +/* use CFI flash driver if no module variant is spezified */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ + +#if !defined(CFG_LOWBOOT) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) +#else /* CFG_LOWBOOT */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) +#endif /* CFG_LOWBOOT */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + * + * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): + * Bit 0 (mask: 0x80000000): 1 + * use ALT CAN position: Bits 2-3 (mask: 0x30000000): + * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. + * Use for REV200 STK52XX boards. Do not use with REV100 modules + * (because, there I2C1 is used as I2C bus) + * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 + * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) + * 000 -> All PSC2 pins are GIOPs + * 001 -> CAN1/2 on PSC2 pins + * Use for REV100 STK52xx boards + * use PSC6: + * on STK52xx: + * use as UART. Pins PSC6_0 to PSC6_3 are used. + * Bits 9:11 (mask: 0x00700000): + * 101 -> PSC6 : Extended POST test is not available + * on MINI-FAP and TQM5200_IB: + * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): + * 000 -> PSC6 could not be used as UART, CODEC or IrDA + * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST + * tests. + */ +#define CFG_GPS_PORT_CONFIG 0x81500014 + +/* + * RTC configuration + */ +#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Enable an alternate, more extensive memory test */ +#define CFG_ALT_MEMTEST + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#ifdef CFG_PCISPEED_66 +#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ +#else +#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ +#endif +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* automatic configuration of chip selects */ +#ifdef CONFIG_CS_AUTOCONF +#define CONFIG_LAST_STAGE_INIT +#endif + +/* + * SRAM - Do not map below 2 GB in address space, because this area is used + * for SDRAM autosizing. + */ +#define CFG_CS2_START 0xE5000000 +#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ +#define CFG_CS2_CFG 0x0004D930 + +/* + * Grafic controller - Do not map below 2 GB in address space, because this + * area is used for SDRAM autosizing. + */ +#define SM501_FB_BASE 0xE0000000 +#define CFG_CS1_START (SM501_FB_BASE) +#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ +#define CFG_CS1_CFG 0x8F48FF70 +#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ + +#define CFG_RESET_ADDRESS 0xff000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h new file mode 100644 index 0000000..9a1c559 --- /dev/null +++ b/include/configs/armadillo.h @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the EP7312 board. + * + * Modified to work on Armadillo HT1070 ARM720T board + * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +/*#define CONFIG_INIT_CRITICAL*/ /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x20000300 /* armadillo board */ +#define CS8900_BUS16 1 +#undef CS8900_BUS32 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" + +#define CONFIG_BOOTCOMMAND "bootm 40000 180000" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "ARMADILLO # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/ + +#define CFG_HZ 2000 /* decrementer freq: 2 kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB armadillo SDRAM */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#endif /* __CONFIG_H */ diff --git a/include/configs/assabet.h b/include/configs/assabet.h new file mode 100644 index 0000000..1a69ebe --- /dev/null +++ b/include/configs/assabet.h @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * 2004 (c) MontaVista Software, Inc. + * + * Configuation settings for the Intel Assabet board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ +#define CONFIG_ASSABET 1 /* on an Intel Assabet Board */ + +#undef CONFIG_USE_IRQ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */ +#define CONFIG_LAN91C96_BASE 0x18000000 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" +#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" +#define CFG_AUTOLOAD "n" /* No autoload */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Intel Assabet # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ + +#define CFG_LOAD_ADDR 0xc0000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ + +#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#define CFG_RAMSTART +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_FLASH_SIZE PHYS_FLASH_SIZE +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ +#undef CFG_FLASH_PROTECTION +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_ENV_IS_IN_FLASH 1 + +#if defined(CFG_ENV_IS_IN_FLASH) +#define CFG_ENV_IN_OWN_SECTOR 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) +#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h new file mode 100644 index 0000000..8fad55d --- /dev/null +++ b/include/configs/at91rm9200dk.h @@ -0,0 +1,234 @@ +/* + * Rick Bronson + * + * Configuation settings for the AT91RM9200DK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ +#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ +/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_BOOTDELAY 3 +/* #define CONFIG_ENV_OVERWRITE 1 */ + +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | CFG_CMD_MII |\ + CFG_CMD_DHCP ) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_IMI | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS )) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ +#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ + +#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) +#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) + +#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 + +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_AT91C_USE_RMII + +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 2 +#define CFG_MAX_DATAFLASH_PAGES 16384 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ + +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#undef CFG_ENV_IS_IN_DATAFLASH + +#ifdef CFG_ENV_IS_IN_DATAFLASH +#define CFG_ENV_OFFSET 0x20000 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ +#else +#define CFG_ENV_IS_IN_FLASH 1 +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ +#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ +#else +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ +#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CFG_ENV_IS_IN_DATAFLASH */ + + +#define CFG_LOAD_ADDR 0x21000000 /* default load address */ + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ +#define CFG_U_BOOT_BASE PHYS_FLASH_1 +#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */ +#else +#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ +#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) +#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/atc.h b/include/configs/atc.h new file mode 100644 index 0000000..bf6c170 --- /dev/null +++ b/include/configs/atc.h @@ -0,0 +1,509 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_ATC 1 /* ...on a ATC board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ + +#define CONFIG_BAUDRATE 115200 + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_ON_FCC + +#define CONFIG_NET_MULTI +#define CONFIG_ETHER_ON_FCC2 + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#define CONFIG_ETHER_ON_FCC3 + +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK16 + * - RAM for BD/Buffers is on the local Bus (see 28-13) + * - Enable Half Duplex in FSMR + */ +# define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +# define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 64000000 /* in Hz */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ + +#define CONFIG_PREBOOT \ + "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\ + "echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\ + "bootm" + +/*----------------------------------------------------------------------- + * Miscellaneous configuration options + */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_DATE | \ + CFG_CMD_IDE) + + +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ + +#define CFG_ALLOC_DPRAM + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SPI + +#define CONFIG_RTC_DS12887 + +#define RTC_BASE_ADDR 0xF5000000 +#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 +#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 + +#define CONFIG_MISC_INIT_R + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Flash configuration + */ + +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 0x00800000 + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CONFIG_FLASH_16BIT + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ + HRCW_BPS10 |\ + HRCW_APPC10) + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * 60x SDRAM is mapped at CFG_SDRAM_BASE. + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ + +#if 1 +/* environment is in Flash */ +#define CFG_ENV_IS_IN_FLASH 1 +# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x30000) +# define CFG_ENV_SIZE 0x10000 +# define CFG_ENV_SECT_SIZE 0x10000 +#else +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 2048 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#endif +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ + HID0_DCI|HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define BCR_APD01 0x10000000 +#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\ + SIUMCR_CS10PC00|SIUMCR_BCTLC10) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR SCCR_DFBRG01 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +#define CFG_MIN_AM_MASK 0xC0000000 +/*----------------------------------------------------------------------- + * MPTPR - Memory Refresh Timer Prescaler Register 10-18 + *----------------------------------------------------------------------- + */ +#define CFG_MPTPR 0x1F00 + +/*----------------------------------------------------------------------- + * PSRT - Refresh Timer Register 10-16 + *----------------------------------------------------------------------- + */ +#define CFG_PSRT 0x0f + +/*----------------------------------------------------------------------- + * PSRT - SDRAM Mode Register 10-10 + *----------------------------------------------------------------------- + */ + + /* SDRAM initialization values for 8-column chips + */ +#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A7 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR_8COL (PSDMR_PBI |\ + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A15_A17 |\ + PSDMR_SDA10_PBI1_A7 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + + /* SDRAM initialization values for 9-column chips + */ +#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A6 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR_9COL (PSDMR_PBI |\ + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A15_A17 |\ + PSDMR_SDA10_PBI1_A6 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 8 bit Boot ROM + * 1 60x GPCM 64 bit FLASH + * 2 60x SDRAM 64 bit SDRAM + * + */ + +#define CFG_MRS_OFFS 0x00000000 + +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) + + +/* Bank 2 - 60x bus SDRAM + */ +#ifndef CFG_RAMBOOT +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR2_PRELIM CFG_OR2_8COL + +#define CFG_PSDMR CFG_PSDMR_8COL +#endif /* CFG_RAMBOOT */ + +#define CFG_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_UPMA |\ + BRx_V) + +#define CFG_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CONFIG_I82365 + +#define CFG_PCMCIA_MEM_ADDR 0x81000000 +#define CFG_PCMCIA_MEM_SIZE 0x1000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR 0xa0000000 + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 0x100 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET 0x100 + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x108 + +#endif /* __CONFIG_H */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h new file mode 100644 index 0000000..eacc744 --- /dev/null +++ b/include/configs/bamboo.h @@ -0,0 +1,406 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * bamboo.h - configuration for BAMBOO board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_BAMBOO 1 /* Board is BAMBOO */ +#define CONFIG_440EP 1 /* Specific PPC440EP support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* + * Please note that, if NAND support is enabled, the 2nd ethernet port + * can't be used because of pin multiplexing. So, if you want to use the + * 2nd ethernet port you have to "undef" the following define. + */ +#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ +#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ +#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ +/*Don't change either of these*/ + +#define CFG_USB_DEVICE 0x50000000 +#define CFG_NVRAM_BASE_ADDR 0x80000000 +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_NAND_ADDR 0x90000000 +#define CFG_NAND2_ADDR 0x94000000 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in SDRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF + * The DS1558 code assumes this condition + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2aa +#define CFG_FLASH_WORD_SIZE unsigned char + +#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ +#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * NAND-FLASH related + *----------------------------------------------------------------------*/ +#define NAND_CMD_REG (0x00) /* NandFlash Command Register */ +#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */ +#define NAND_DATA_REG (0x08) /* NandFlash Data Register */ +#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */ +#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */ +#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */ +#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */ +#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */ +#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */ +#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */ +#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */ +#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */ +#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */ +#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */ +#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */ +#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */ +#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */ +#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */ +#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */ + +/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */ +#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */ +#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */ +#define NAND0_CMD_READ2 0x50 +#define NAND0_CMD_READ_ID 0x90 +#define NAND0_CMD_READ_STATUS 0x70 +#define NAND0_CMD_RESET 0xFF +#define NAND0_CMD_PAGE_PROG 0x80 +#define NAND0_CMD_PAGE_PROG_TRUE 0x10 +#define NAND0_CMD_PAGE_PROG_DUMMY 0x11 +#define NAND0_CMD_BLOCK_ERASE 0x60 +#define NAND0_CMD_BLOCK_ERASE_END 0xD0 + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0) +#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0) +#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG)) +#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01)) + +/* not needed with 440EP NAND controller */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------------- */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#undef CONFIG_DDR_ECC /* don't use ECC */ +#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ +#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#endif /* CFG_ENV_IS_IN_EEPROM */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=bamboo\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/bamboo/uImage\0" \ + "kernel_addr=fff00000\0" \ + "ramdisk_addr=fff10000\0" \ + "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \ + "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ + "cp.b 100000 fff80000 80000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 1 + +#ifndef CONFIG_BAMBOO_NAND +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#endif /* CONFIG_BAMBOO_NAND */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#ifdef CONFIG_440EP +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/*Comment this out to enable USB 1.1 device*/ +#define USB_2_0_DEVICE +#endif /*CONFIG_440EP*/ + +#ifdef CONFIG_BAMBOO_NAND +#define _CFG_CMD_NAND CFG_CMD_NAND +#else +#define _CFG_CMD_NAND 0 +#endif /* CONFIG_BAMBOO_NAND */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_USB | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ + _CFG_CMD_NAND | \ + CFG_CMD_SNTP ) + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/barco.h b/include/configs/barco.h new file mode 100644 index 0000000..624fa1d --- /dev/null +++ b/include/configs/barco.h @@ -0,0 +1,364 @@ +/******************************************************************** + * + * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms + * + * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $ + * $Revision: 1.2 $ + * $Author: mleeman $ + * $Date: 2005/02/21 12:48:58 $ + * + * Last ChangeLog Entry + * $Log: barco.h,v $ + * Revision 1.2 2005/02/21 12:48:58 mleeman + * update of copyright years (feedback wd) + * + * Revision 1.1 2005/02/14 09:29:25 mleeman + * moved barcohydra.h to barco.h + * + * Revision 1.4 2005/02/09 12:56:23 mleeman + * add generic header to track changes in sources + * + * + *******************************************************************/ + +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_BARCOBCD_STREAMING 1 + +#undef USE_DINK32 + +#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ +#define CONFIG_BAUDRATE 9600 +#define CONFIG_DRAM_SPEED 100 /* MHz */ + +#define CONFIG_BOOTARGS "mem=32M" + +/* Add support for a few extra bootp options like: + * - File size + * - DNS + */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_PCI ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTCOMMAND "boot_default" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP +#undef CFG_CMD_NET + +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET0_MEMADDR 0x80000000 +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET1_MEMADDR 0x81000000 + + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x02000000 + +#define CONFIG_LOGBUFFER +#ifdef CONFIG_LOGBUFFER +#define CFG_STDOUT_ADDR 0x1FFC000 +#else +#define CFG_STDOUT_ADDR 0x2B9000 +#endif + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#if defined (USE_DINK32) +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE 0x00090000 +#define CFG_RAMBOOT 1 +#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_INIT_RAM_END 0x10000 +#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#else +#undef CFG_RAMBOOT +#define CFG_MONITOR_LEN 0x00030000 +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#endif + +#define CFG_FLASH_BASE 0xFFF00000 +#define CFG_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ +/* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */ + +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ + +#define CFG_EUMB_ADDR 0xFDF00000 + +#define CFG_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */ +#define CFG_FLASH_RANGE_SIZE 0x00400000 +#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ +#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ + +/* + * select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#ifdef CONFIG_SOFT_I2C +#error "Soft I2C is not configured properly. Please review!" +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } +#define CFG_DBUS_SIZE2 1 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + + + /* + * NS16550 Configuration (internal DUART) + */ + /* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CFG_ROMNAL 0x0F /*rom/flash next access time */ +#define CFG_ROMFAL 0x1E /*rom/flash access time */ + +#define CFG_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */ + +/* the following are for SDRAM only*/ +#define CFG_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT 4 /* data latency from read command */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 2 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ + +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 0 +#define CFG_REGDIMM 0 + + +/* memory bank settings*/ +/* + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END 0x01FFFFFF +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x02000000 +#define CFG_BANK1_END 0x02ffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x03f00000 +#define CFG_BANK2_END 0x03ffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x04000000 +#define CFG_BANK3_END 0x04ffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x05000000 +#define CFG_BANK4_END 0x05FFFFFF +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x06000000 +#define CFG_BANK5_END 0x06FFFFFF +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x07000000 +#define CFG_BANK6_END 0x07FFFFFF +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x08000000 +#define CFG_BANK7_END 0x08FFFFFF +#define CFG_BANK7_ENABLE 0 +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0xff /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#if defined(USE_DINK32) +#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) +#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) +#else +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#endif + +/* PCI memory */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_CHECKSUM + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* values according to the manual */ + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +#define CONFIG_DISK_SPINUP_TIME 1000000 + + +#endif /* __CONFIG_H */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h new file mode 100644 index 0000000..4a79835 --- /dev/null +++ b/include/configs/bubinga.h @@ -0,0 +1,432 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_NO_SERIAL_EEPROM +/*#undef CONFIG_NO_SERIAL_EEPROM*/ +/*----------------------------------------------------------------------------*/ +#ifdef CONFIG_NO_SERIAL_EEPROM + +/* +!------------------------------------------------------------------------------- +! Defines for entry options. +! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that +! are plugged in the board will be utilized as non-ECC DIMMs. +!------------------------------------------------------------------------------- +*/ +#define AUTO_MEMORY_CONFIG +#define DIMM_READ_ADDR 0xAB +#define DIMM_WRITE_ADDR 0xAA + +/* +!------------------------------------------------------------------------------- +! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, +! assuming a 33MHz input clock to the 405EP from the C9531. +!------------------------------------------------------------------------------- +*/ +#define PLLMR0_DEFAULT PLLMR0_266_133_66 +#define PLLMR1_DEFAULT PLLMR1_266_133_66 + +#endif +/*----------------------------------------------------------------------------*/ + +/* + * Define here the location of the environment variables (FLASH or NVRAM). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#endif + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=bubinga\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/bubinga/uImage\0" \ + "kernel_addr=fff80000\0" \ + "ramdisk_addr=fff90000\0" \ + "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ + +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#endif + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * External peripheral base address + *----------------------------------------------------------------------- + */ +#define CFG_KEY_REG_BASE_ADDR 0xF0100000 +#define CFG_IR_REG_BASE_ADDR 0xF0200000 +#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SRAM_BASE 0xFFF00000 +#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash/SRAM) initialization */ +#define CFG_EBC_PB0AP 0x04006000 +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 1 (NVRAM/RTC) initialization */ +#define CFG_EBC_PB1AP 0x04041000 +#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 2 (not used) initialization */ +#define CFG_EBC_PB2AP 0x00000000 +#define CFG_EBC_PB2CR 0x00000000 + +/* Memory Bank 2 (not used) initialization */ +#define CFG_EBC_PB3AP 0x00000000 +#define CFG_EBC_PB3CR 0x00000000 + +/* Memory Bank 4 (FPGA regs) initialization */ +#define CFG_EBC_PB4AP 0x01815000 +#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x55 + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x55555555 +#define CFG_GPIO0_OSRL 0x40000110 +#define CFG_GPIO0_ISR1H 0x00000000 +#define CFG_GPIO0_ISR1L 0x15555445 +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xFFFF8014 + +/*----------------------------------------------------------------------- + * Some BUBINGA stuff... + */ +#define NVRAM_BASE 0xF0000000 +#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */ +#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */ +#define NVRVFY1 0x4f532d4f /* used to determine if state data in */ +#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/ + +#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */ +#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */ +#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */ +#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */ +#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */ +#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */ + +#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */ +#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */ +#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */ +#define FPGA_REG1_CLOCK_BIT_SHIFT 4 +#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */ +#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */ +#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */ +#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h new file mode 100644 index 0000000..ae75539 --- /dev/null +++ b/include/configs/c2mon.h @@ -0,0 +1,418 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ +#define CONFIG_C2MON 1 /* ...on a C2MON module */ + +#define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_STATUS_LED /* Status LED disabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */ + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ +#define CFG_PLPRCR \ + ( (5-1)< + +/* + * MUST be low boot - HIGHBOOT is not supported anymore + */ +#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 +#else +# error "TEXT_BASE must be 0xFE000000" +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=/tftpboot/canmb/uImage\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ + +/* + * Flash configuration, expect one 16 Megabyte Bank at most + */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_SIZE 0x02000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET (2*128*1024) +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE (128*1024) + +/* + * Memory map + * + * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 + */ +#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x0 +/* + * GPIO configuration: + * PSC1,2,3 predefined as UART + * PCI disabled + * Ethernet 100 with MD + */ +#define CFG_GPS_PORT_CONFIG 0x00058444 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047D01 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0x7f000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h new file mode 100644 index 0000000..6997c7a --- /dev/null +++ b/include/configs/cerf250.h @@ -0,0 +1,214 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the CERF250 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_CERF250 1 /* on Cerf PXA Board */ +#define BOARD_LATE_INIT 1 +#define CONFIG_BAUDRATE 38400 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE 0x04000300 +#define CONFIG_SMC_USE_32_BIT + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on CERF PXA */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.5 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_BOOTCOMMAND "bootm 0xC0000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400" +#define CONFIG_CMDLINE_TAG + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "uboot$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) + /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ + +#define CFG_LOAD_ADDR 0xa2000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ + + +#define CFG_GPSR0_VAL 0x00408030 +#define CFG_GPSR1_VAL 0x00BFA882 +#define CFG_GPSR2_VAL 0x0001C000 +#define CFG_GPCR0_VAL 0xC0031100 +#define CFG_GPCR1_VAL 0xFC400300 +#define CFG_GPCR2_VAL 0x00003FFF +#define CFG_GPDR0_VAL 0xC0439330 +#define CFG_GPDR1_VAL 0xFCFFAB82 +#define CFG_GPDR2_VAL 0x0001FFFF +#define CFG_GAFR0_L_VAL 0x80000000 +#define CFG_GAFR0_U_VAL 0xA5000010 +#define CFG_GAFR1_L_VAL 0x60008018 +#define CFG_GAFR1_U_VAL 0xAAA5AAAA +#define CFG_GAFR2_L_VAL 0xAAA0000A +#define CFG_GAFR2_U_VAL 0x00000002 + +#define CFG_PSSR_VAL 0x20 + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x12447FF0 +#define CFG_MSC1_VAL 0x12BC5554 +#define CFG_MSC2_VAL 0x7FF97FF1 +#define CFG_MDCNFG_VAL 0x00001AC9 +#define CFG_MDREFR_VAL 0x03CDC017 +#define CFG_MDMRS_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +#define _LED 0x08000010 /*check this */ +#define LED_BLANK 0x08000040 +#define LED_GPIO 0x10 + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_MONITOR_LEN 0x40000 /* 256 KiB */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h new file mode 100644 index 0000000..5947c2a --- /dev/null +++ b/include/configs/cm4008.h @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2004 + * Greg Ungerer . + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ +#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CFG_ENV_IS_NOWHERE +#define CONFIG_SERIAL1 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#undef CONFIG_COMMANDS +#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV)) + +#define CONFIG_BOOTDELAY 0 +#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200" +#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00800000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00008000 /* default load address */ + +#define CFG_HZ (1000) /* 1ms resolution ticks */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ + +#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h new file mode 100644 index 0000000..e62fc06 --- /dev/null +++ b/include/configs/cm41xx.h @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2005 + * Greg Ungerer . + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ +#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CFG_ENV_IS_NOWHERE +#define CONFIG_SERIAL1 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#undef CONFIG_COMMANDS +#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV)) + +#define CONFIG_BOOTDELAY 0 +#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200" +#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00800000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00008000 /* default load address */ + +#define CFG_HZ (1000) /* 1ms resolution ticks */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h new file mode 100644 index 0000000..46280f7 --- /dev/null +++ b/include/configs/cmc_pu2.h @@ -0,0 +1,253 @@ +/* + * 2004-2005 Gary Jennejohn + * + * Configuration settings for the CMC PU2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ +#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ +#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 9600 + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#undef CONFIG_DBGU +#define CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_HARD_I2C + +#ifdef CONFIG_HARD_I2C +#define CFG_I2C_SPEED 0 /* not used */ +#define CFG_I2C_SLAVE 0 /* not used */ +#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ +#define CFG_I2C_RTC_ADDR 0x32 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW +#endif +/* still about 20 kB free with this defined */ +#define CFG_LONGHELP + +#define CONFIG_BOOTDELAY 3 + +#ifdef CONFIG_HARD_I2C +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) & \ + ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) +#else +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) & \ + ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) +#define CONFIG_TIMESTAMP +#endif +#define CFG_LONGHELP + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ +#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 + +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_AT91C_USE_RMII + +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 2 +#define CFG_MAX_DATAFLASH_PAGES 16384 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ + +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_ERASE_TOUT (11 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT ( 2 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */ +#define CFG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */ +#define CFG_ENV_SIZE (16 << 10) /* Use only 16 kB */ + +#define CFG_LOAD_ADDR 0x21000000 /* default load address */ + +#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } + +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 32 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif /* __ASSEMBLY__ */ + +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#define CFG_DEVICE_NULLDEV 1 /* enble null device */ +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ + +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_STOP_STR "R" /* default password */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \ + "addmtd;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \ + "addcons addmtd; bootm\0" \ + "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \ + "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \ + "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ + "${hostname}::off\0" \ + "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \ + "64k(environment),768k(linux),4096k(root),-\0" \ + "load=tftp ${loadaddr} ${loadfile}\0" \ + "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \ + "cp.b ${loadaddr} 10000000 ${filesize};" \ + "protect on 10000000 1001ffff\0" \ + "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \ + "cp.b ${loadaddr} 10030000 ${filesize}\0" \ + "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \ + "cp.b ${loadaddr} 100f0000 ${filesize}\0" \ + "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \ + "cp.b ${loadaddr} 104f0000 ${filesize}\0" \ + "cramfsimage=cramfs_cmc-pu2.img\0" \ + "jffsimage=jffs2_cmc-pu2.img\0" \ + "loadfile=u-boot_cmc-pu2.bin\0" \ + "bootfile=uImage_cmc-pu2\0" \ + "loadaddr=0x20800000\0" \ + "hostname=CMC-TC-PU2\0" \ + "bootcmd=run dhcp_start;run flash_cramfs\0" \ + "autoload=n\0" \ + "dhcp_start=echo no DHCP\0" \ + "ipaddr=192.168.0.190\0" +#endif /* __CONFIG_H */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h new file mode 100644 index 0000000..e459919 --- /dev/null +++ b/include/configs/cmi_mpc5xx.h @@ -0,0 +1,256 @@ +/* + * (C) Copyright 2003 + * Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, + */ + +/* + * File: cmi_mpc5xx.h + * + * Discription: Config header file for cmi + * board using an MPC5xx CPU + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ +#define CONFIG_CMI 1 /* Using the customized cmi board */ + +/* Serial Console Configuration */ +#define CONFIG_5xx_CONS_SCI1 +#undef CONFIG_5xx_CONS_SCI2 + +#define CONFIG_BAUDRATE 57600 + +#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ + CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV | \ + CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN | \ + CFG_CMD_IMI) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ + +#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */ + +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ + +#define CONFIG_STATUS_LED 1 /* Enable status led */ + +#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ + +/* + * Miscellaneous configurable options + */ + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } + + +/* + * Low Level Configuration Settings + */ + +/* + * Internal Memory Mapped (This is not the IMMR content) + */ +#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */ + +/* + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ +#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ + +/* + * Start addresses for the final memory configuration + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CFG_FLASH_BASE 0x02000000 /* External flash */ +#define PLD_BASE 0x03000000 /* PLD */ +#define ANYBUS_BASE 0x03010000 /* Anybus Module */ + +#define CFG_RESET_ADRESS 0x01000000 /* Adress which causes reset */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */ + /* This adress is given to the linker with -Ttext to */ + /* locate the text section at this adress. */ +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + + +/*----------------------------------------------------------------------- + * FLASH organization + *----------------------------------------------------------------------- + * + */ + +#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_PROTECTION 1 /* Physically section protection on */ + +#define CFG_ENV_IS_IN_FLASH 1 + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ +#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ + SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration + *----------------------------------------------------------------------- + * Data show cycle + */ +#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register + *----------------------------------------------------------------------- + * Set all bits to 40 Mhz + * + */ +#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ +#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) + + +/*----------------------------------------------------------------------- + * UMCR - UIMB Module Configuration Register + *----------------------------------------------------------------------- + * + */ +#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ + +/*----------------------------------------------------------------------- + * ICTRL - I-Bus Support Control Register + */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ + +/*----------------------------------------------------------------------- + * USIU - Memory Controller Register + *----------------------------------------------------------------------- + */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16) +#define CFG_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3) +#define CFG_BR1_PRELIM (ANYBUS_BASE) +#define CFG_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR) +#define CFG_BR2_PRELIM (CFG_SDRAM_BASE | BR_V | BR_PS_32) +#define CFG_OR2_PRELIM (OR_ADDR_MK_FF) +#define CFG_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8) +#define CFG_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \ + OR_ACS_10 | OR_ETHR | OR_CSNT) + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ + +/*----------------------------------------------------------------------- + * DER - Timer Decrementer + *----------------------------------------------------------------------- + * Initialise to zero + */ +#define CFG_DER 0x00000000 + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h new file mode 100644 index 0000000..9033fa8 --- /dev/null +++ b/include/configs/cobra5272.h @@ -0,0 +1,355 @@ +/* + * Configuation settings for the Sentec Cobra Board. + * + * (C) Copyright 2003 Josef Baumgartner + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* --- + * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board + * Date: 2004-03-29 + * Author: Florian Schlote + * + * For a description of configuration options please refer also to the + * general u-boot-1.x.x/README file + * --- + */ + +/* --- + * board/config.h - configuration options, board specific + * --- + */ + +#ifndef _CONFIG_COBRA5272_H +#define _CONFIG_COBRA5272_H + +/* --- + * Define processor + * possible values for Sentec board: only Coldfire M5272 processor supported + * (please do not change) + * --- + */ + +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5272 /* define processor type */ + +/* --- + * Defines processor clock - important for correct timings concerning serial + * interface etc. + * CFG_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms + * --- + */ + +#define CFG_HZ 1000 +#define CFG_CLK 66000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ + +/* --- + * Enable use of Ethernet + * --- + */ + +#define FEC_ENET + +/* --- + * Define baudrate for UART1 (console output, tftp, ...) + * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud + * CFG_BAUDRATE_TABLE defines values that can be selected in u-boot command + * interface + * --- + */ + +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +/* --- + * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change + * timeout acc. to your needs + * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 + * for 10 sec + * --- + */ + +#if 0 +#define CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ +#endif + +/* --- + * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different + * bootloader residing in flash ('chainloading'); if you want to use + * chainloading or want to compile a u-boot binary that can be loaded into + * RAM via BDM set + * "#if 0" to "#if 1" + * You will need a first stage bootloader then, e. g. colilo or a working BDM + * cable (Background Debug Mode) + * + * Setting #if 0: u-boot will start from flash and relocate itself to RAM + * + * Please do not forget to modify the setting of TEXT_BASE + * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) + * + * --- + */ + +#if 0 +#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ +#endif + +/* --- + * Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + * --- + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 +#else +#define CFG_ENV_ADDR 0xffe04000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#endif + +/* --- + * Define which commmands should be available at u-boot command prompt + * --- + */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | CFG_CMD_PING & ~(CFG_CMD_LOADS | \ +CFG_CMD_LOADB) | CFG_CMD_MII) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + *----------------------------------------------------------------------------- + * Define user parameters that have to be customized most likely + *----------------------------------------------------------------------------- + */ + +/*AUTOBOOT settings - booting images automatically by u-boot after power on*/ + +#define CONFIG_BOOTDELAY 5 /* used for autoboot, delay in +seconds u-boot will wait before starting defined (auto-)boot command, setting +to -1 disables delay, setting to 0 will too prevent access to u-boot command +interface: u-boot then has to reflashed */ + + +/* The following settings will be contained in the environment block ; if you +want to use a neutral environment all those settings can be manually set in +u-boot: 'set' command */ + +#if 0 + +#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please +enter a valid image address in flash */ + +#define CONFIG_BOOTARGS " " /* default bootargs that are +considered during boot */ + +/* User network settings */ + +#define CONFIG_ETHADDR 00:00:00:00:00:09 /* default ethernet MAC addr. */ +#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ +#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ + +#endif + +#define CFG_PROMPT "COBRA > " /* Layout of u-boot prompt*/ + +#define CFG_LOAD_ADDR 0x20000 /*Defines default RAM address +from which user programs will be started */ + +/*---*/ + +#define CFG_LONGHELP /* undef to save memory */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* + *----------------------------------------------------------------------------- + * End of user parameters to be customized + *----------------------------------------------------------------------------- + */ + +/* --- + * Defines memory range for test + * --- + */ + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +/* --- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * --- + */ + +/* --- + * Base register address + * --- + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ + +/* --- + * System Conf. Reg. & System Protection Reg. + * --- + */ + +#define CFG_SCR 0x0003; +#define CFG_SPR 0xffff; + +/* --- + * Ethernet settings + * --- + */ + +#define CFG_DISCOVER_PHY +#define CFG_ENET_BD_BASE 0x780000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +/* + *------------------------------------------------------------------------- + * RAM SIZE (is defined above) + *----------------------------------------------------------------------- + */ + +/* #define CFG_SDRAM_SIZE 16 */ + +/* + *----------------------------------------------------------------------- + */ + +#define CFG_FLASH_BASE 0xffe00000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CFG_MONITOR_BASE 0x20000 +#else +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif + +#define CFG_MONITOR_LEN 0x20000 +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 1000 /* flash timeout */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + * + * Please refer also to Motorola Coldfire user manual - Chapter XXX + * + */ +#define CFG_BR0_PRELIM 0xFFE00201 +#define CFG_OR0_PRELIM 0xFFE00014 + +#define CFG_BR1_PRELIM 0 +#define CFG_OR1_PRELIM 0 + +#define CFG_BR2_PRELIM 0 +#define CFG_OR2_PRELIM 0 + +#define CFG_BR3_PRELIM 0 +#define CFG_OR3_PRELIM 0 + +#define CFG_BR4_PRELIM 0 +#define CFG_OR4_PRELIM 0 + +#define CFG_BR5_PRELIM 0 +#define CFG_OR5_PRELIM 0 + +#define CFG_BR6_PRELIM 0 +#define CFG_OR6_PRELIM 0 + +#define CFG_BR7_PRELIM 0x00000701 +#define CFG_OR7_PRELIM 0xFF00007C + +/*----------------------------------------------------------------------- + * LED config + */ +#define LED_STAT_0 0xffff /*all LEDs off*/ +#define LED_STAT_1 0xfffe +#define LED_STAT_2 0xfffd +#define LED_STAT_3 0xfffb +#define LED_STAT_4 0xfff7 +#define LED_STAT_5 0xffef +#define LED_STAT_6 0xffdf +#define LED_STAT_7 0xff00 /*all LEDs on*/ + +/*----------------------------------------------------------------------- + * Port configuration (GPIO) + */ +#define CFG_PACNT 0x00000000 /* PortA control reg.: All pins are external +GPIO*/ +#define CFG_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs +(1^=output, 0^=input) */ +#define CFG_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ +#define CFG_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART +configuration */ +#define CFG_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ +#define CFG_PBDAT 0x0000 /* PortB value reg. */ +#define CFG_PDCNT 0x00000000 /* PortD control reg. */ + +#endif /* _CONFIG_COBRA5272_H */ diff --git a/include/configs/cogent_common.h b/include/configs/cogent_common.h new file mode 100644 index 0000000..cdf5802 --- /dev/null +++ b/include/configs/cogent_common.h @@ -0,0 +1,208 @@ +/* + * (C) Copyright 2000 + * Murray Jensen, CSIRO-MST + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CONFIG_COGENT_COMMON_H +#define _CONFIG_COGENT_COMMON_H + +/* + * Cogent Motherboard Capabilities + */ +#define CMA_MB_CAP_SERPAR 0x0001 /* has dual serial+parallel (16C552) */ +#define CMA_MB_CAP_LCD 0x0002 /* has LCD display (HD44780) */ +#define CMA_MB_CAP_FLASH 0x0004 /* has flash (E28F800B or AM29F800BB) */ +#define CMA_MB_CAP_RTC 0x0008 /* has RTC+NVRAM (MK48T02) */ +#define CMA_MB_CAP_ETHER 0x0010 /* has Ethernet (MB86964) */ +#define CMA_MB_CAP_SLOT1 0x0020 /* has CMABus slot 1 */ +#define CMA_MB_CAP_SLOT2 0x0040 /* has CMABus slot 2 */ +#define CMA_MB_CAP_SLOT3 0x0080 /* has CMABus slot 3 */ +#define CMA_MB_CAP_KBM 0x0100 /* has PS/2 keyboard+mouse (HT6542B) */ +#define CMA_MB_CAP_SER2 0x0200 /* has 2nd dual serial (16C2552) */ +#define CMA_MB_CAP_PCI 0x0400 /* has pci bridge (V360EPC) */ +#define CMA_MB_CAP_PCI_EXT 0x0800 /* can access extended pci space */ +#define CMA_MB_CAP_PCI_ETHER 0x1000 /* has 10/100 ether on PCI (GD82559) */ +#define CMA_MB_CAP_PCI_VIDEO 0x2000 /* has video int'face on PCI (B69000) */ +#define CMA_MB_CAP_PCI_CARDBUS 0x4000 /* has Cardbus Ctlr on PCI (PD6832) */ + +/* + * Cogent option sanity checking + */ + +#if defined(CONFIG_MPC821) || defined(CONFIG_MPC823) || \ + defined(CONFIG_MPC850) || defined(CONFIG_MPC860) + +/* + * check a PowerPC 8xx cpu module has been selected + */ + +# if defined(CONFIG_CMA286_21) + +# define COGENT_CPU_MODULE "CMA286-21" + +# elif defined(CONFIG_CMA286_60_OLD) + +# define COGENT_CPU_MODULE "CMA286-60 (old)" + +# elif defined(CONFIG_CMA286_60) + +# define COGENT_CPU_MODULE "CMA286-60" + +# elif defined(CONFIG_CMA286_60P) + +# define COGENT_CPU_MODULE "CMA286-60P" + +# elif defined(CONFIG_CMA287_21) + +# define COGENT_CPU_MODULE "CMA287-21" + +# elif defined(CONFIG_CMA287_50) + +# define COGENT_CPU_MODULE "CMA287-50" + +# else + +# error Cogent CPU Module must be a PowerPC MPC8xx module + +# endif + +#elif defined(CONFIG_MPC8260) + +/* + * check a PowerPC 8260 cpu module has been selected + */ + +# if defined(CONFIG_CMA282) + +# define COGENT_CPU_MODULE "CMA282" + +# else + +# error Cogent CPU Module must be a PowerPC MPC8260 module + +# endif + +#else + +# error CPU type must be PowerPC 8xx or 8260 + +#endif + +/* + * check a motherboard has been selected + * define the motherboard capabilities while we're at it + */ + +#if defined(CONFIG_CMA101) + +# define COGENT_MOTHERBOARD "CMA101" +# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ + CMA_MB_CAP_RTC | CMA_MB_CAP_ETHER | \ + CMA_MB_CAP_SLOT1 | CMA_MB_CAP_SLOT2 | \ + CMA_MB_CAP_SLOT3) +# define CMA_MB_NSLOTS 3 + +#elif defined(CONFIG_CMA102) + +# define COGENT_MOTHERBOARD "CMA102" +# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ + CMA_MB_CAP_RTC | CMA_MB_CAP_SLOT1 | \ + CMA_MB_CAP_SLOT2 | CMA_MB_CAP_SLOT3) +# define CMA_MB_NSLOTS 3 + +#elif defined(CONFIG_CMA110) + +# define COGENT_MOTHERBOARD "CMA110" +# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ + CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ + CMA_MB_CAP_KBM | CMA_MB_CAP_PCI) +# define CMA_MB_NSLOTS 0 + +#elif defined(CONFIG_CMA111) + +# define COGENT_MOTHERBOARD "CMA111" +# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ + CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ + CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \ + CMA_MB_CAP_PCI | CMA_MB_CAP_PCI_EXT | \ + CMA_MB_CAP_PCI_ETHER) +# define CMA_MB_NSLOTS 1 + +#elif defined(CONFIG_CMA120) + +# define COGENT_MOTHERBOARD "CMA120" +# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ + CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ + CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \ + CMA_MB_CAP_SER2 | CMA_MB_CAP_PCI | \ + CMA_MB_CAP_PCI_EXT | CMA_MB_CAP_PCI_ETHER | \ + CMA_MB_CAP_PCI_VIDEO | CMA_MB_CAP_PCI_CARDBUS) +# define CMA_MB_NSLOTS 1 + +#elif defined(CONFIG_CMA150) + +# define COGENT_MOTHERBOARD "CMA150" +# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ + CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ + CMA_MB_CAP_KBM) +# define CMA_MB_NSLOTS 0 + +#else + +# error Cogent Motherboard either unsupported or undefined + +#endif + +/* + * check a flash i/o module has been selected if no flash on m/b + */ + +#if defined(CONFIG_CMA302) + +# define COGENT_FLASH_MODULE "CMA302" + +#elif (CMA_MB_CAPS & CMA_MB_CAP_FLASH) == 0 + +# error Cogent Flash I/O module (e.g. CMA302) is required with this Motherboard + +#endif + +/* + * some further sanity checks + */ + +#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) && (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) +#error Cogent Sanity Check: Both Slot2 and PCI are defined +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI) +#error Extended PCI capability defined without PCI capability +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_ETHER) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI) +#error Motherboard ethernet capability defined without PCI capability +#endif + +#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR) +#error 2nd dual serial capability defined without serial/parallel capability +#endif +#include "../board/cogent/mb.h" +#endif /* _CONFIG_COGENT_COMMON_H */ diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h new file mode 100644 index 0000000..aea2e64 --- /dev/null +++ b/include/configs/cogent_mpc8260.h @@ -0,0 +1,404 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Config header file for Cogent platform using an MPC8xx CPU module + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ + +/* Cogent Modular Architecture options */ +#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */ +#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */ + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ +#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ +#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#define CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 66666666 /* in Hz */ + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 9600 +#endif + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#ifdef DEBUG +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ + +#define CONFIG_BOOTARGS "root=/dev/ram rw" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ +#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ +#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ +#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ +# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */ +# else +#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ +# endif +#endif + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Low Level Cogent settings + * if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not. + * also, make sure CONFIG_CONS_INDEX is still defined - the index will be + * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B + * (second 2 for CMA120 only) + */ +#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */ + +#include + +#ifdef CONFIG_CONS_NONE +#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ +#endif +#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ +#define CONFIG_SHOW_ACTIVITY + +#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) +/* + * flash exists on the motherboard + * set these four according to TOP dipsw: + * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) + * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) + */ +#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE +#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE +#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE +#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE +#endif +#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE +#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#define CFG_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\ + HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101) +/* no slaves so just duplicate the master hrcw */ +#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE CMA_MB_RAM_BASE +#ifdef CONFIG_CMA302 +#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ +#else +#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ +#endif +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */ +#ifdef CONFIG_CMA302 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ +#else +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ + HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR BCR_EBM + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR (SCCR_DFBRG01) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +#if defined(CONFIG_CMA282) + +/* + * Init Memory Controller: + * + * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM + * and CS2 for (optional) local bus RAM on the CPU module. + * + * Note the motherboard address space (256 Mbyte in size) is connected + * to the 60x Bus and is located starting at address 0. The Hard Reset + * Configuration Word should put the 60x Bus into External Bus Mode, since + * we dont set up any memory controller maps for it (see BCR[EBM], 4-26). + * + * (the *_SIZE vars must be a power of 2) + */ + +#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */ +#define CFG_CMA_CS0_SIZE (1 << 20) +#if 0 +#define CFG_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */ +#define CFG_CMA_CS2_SIZE (16 << 20) +#endif + +/* + * CS0 maps the EPROM on the cpu module + * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M + * + * Note: We must have already transferred control to the final location + * of the EPROM before these are used, because when BR0/OR0 are set, the + * mirror of the eprom at any other addresses will disappear. + */ + +/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */ +#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V) +/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */ +#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\ + ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) + +/* + * CS2 enables the Local Bus SDRAM on the CPU Module + * + * Will leave this unset for the moment, because a) my CPU module has no + * SDRAM installed (it is optional); and b) it will require programming + * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right + * if you can't test it. + */ + +#if 0 +/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */ +#define CFG_BR0_PRELIM ((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V) +/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */ +#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/) +#endif + +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h new file mode 100644 index 0000000..80962d3 --- /dev/null +++ b/include/configs/cogent_mpc8xx.h @@ -0,0 +1,360 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Config header file for Cogent platform using an MPC8xx CPU module + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is an MPC860 CPU */ +#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ + +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ + +/* Cogent Modular Architecture options */ +#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */ +#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */ +#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */ + +/* serial console configuration */ +#undef CONFIG_8xx_CONS_SMC1 +#undef CONFIG_8xx_CONS_SMC2 +#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */ + +#if defined(CONFIG_CMA286_60_OLD) +#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */ +#endif + +#define CONFIG_BAUDRATE 230400 + +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ + +#define CONFIG_BOOTARGS "root=/dev/ram rw" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#define CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_ALLOC_DPRAM + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Low Level Cogent settings + * if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not. + * also, make sure CONFIG_CONS_INDEX is still defined - the index will be + * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B + * (second 2 for CMA120 only) + */ +#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */ + +#include + +#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ +#define CONFIG_CONS_INDEX 1 +#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ +#define CONFIG_SHOW_ACTIVITY +#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) +/* + * flash exists on the motherboard + * set these four according to TOP dipsw: + * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) + * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) + */ +#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE +#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE +#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE +#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE +#endif +#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE +#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE CMA_MB_RAM_BASE +#ifdef CONFIG_CMA302 +#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ +#else +#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ +#endif +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */ +#ifdef CONFIG_CMA302 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ +#else +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +#if defined(CONFIG_CMA286_60_OLD) + +/* + * Init Memory Controller: + * + * NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings, + * they are actually the final settings for this cpu/board, because the + * flash and RAM are on the motherboard, accessed via the CMAbus, and the + * mappings are pretty much fixed. + * + * (the *_SIZE vars must be a power of 2) + */ + +#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */ +#define CFG_CMA_CS0_SIZE (1 << 20) +#define CFG_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */ +#define CFG_CMA_CS1_SIZE (64 << 20) +#define CFG_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */ +#define CFG_CMA_CS2_SIZE (64 << 20) +#define CFG_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */ +#define CFG_CMA_CS3_SIZE (32 << 20) + +/* + * CS0 maps the EPROM on the cpu module + * Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M + * + * Note: We must have already transferred control to the final location + * of the EPROM before these are used, because when BR0/OR0 are set, the + * mirror of the eprom at any other addresses will disappear. + */ + +/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */ +#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V) +/* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */ +#define CFG_OR0_PRELIM ((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK) + +/* + * CS1 maps motherboard DRAM and motherboard I/O slot 1 + * (each 32Mbyte in size) + */ + +/* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */ +#define CFG_BR1_PRELIM ((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V) +/* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */ +#define CFG_OR1_PRELIM ((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA) + +/* + * CS2 maps motherboard I/O slots 2 and 3 + * (each 32Mbyte in size) + */ + +/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */ +#define CFG_BR2_PRELIM ((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V) +/* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */ +#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA) + +/* + * CS3 maps motherboard I/O + * (32Mbyte in size) + */ + +/* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */ +#define CFG_BR3_PRELIM ((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V) +/* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */ +#define CFG_OR3_PRELIM ((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA) + +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h new file mode 100644 index 0000000..f9586fb --- /dev/null +++ b/include/configs/cpci5200.h @@ -0,0 +1,417 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + + */ + +/************************************************************************* + * (c) 2005 esd gmbh Hannover + * + * + * from IceCube.h file + * by Reinhard Arlt reinhard.arlt@esd-electronics.com + * + *************************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_ICECUBE 1 /* ... on IceCube board */ +#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */ +#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#if 1 +#define CONFIG_PCI 1 +#if 1 +#define CONFIG_PCI_PNP 1 +#endif +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 +#endif + +#define CONFIG_MII +#if 0 /* test-only !!! */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 +#endif + +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MPC5100 */ + +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* USB */ +#if 0 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_IDE | \ + CFG_CMD_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_DATE | \ + ADD_PCI_CMD ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 +#endif +#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT08 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Welcome to esd CPU CPCI/5200;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ + "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ + "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ + "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ + "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ + "loadaddr=01000000\0" \ + "serverip=192.168.2.99\0" \ + "gatewayip=10.0.0.79\0" \ + "user=mu\0" \ + "target=cpci5200.esd\0" \ + "script=cpci5200.bat\0" \ + "image=/tftpboot/vxWorks_cpci5200\0" \ + "ipaddr=10.0.13.196\0" \ + "netmask=255.255.0.0\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_vxworks0" + +#if defined(CONFIG_MPC5200) + +#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ +#define CFG_NVRAM_BASE_ADDR 0xfd010000 +#define CFG_NVRAM_SIZE 32*1024 + +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 86000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CFG_I2C_MULTI_EEPROMS 1 +/* + * Flash configuration + */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_SIZE 0x02000000 +#define CFG_FLASH_INCREMENT 0x01000000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) +#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 + +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* + * Environment settings + */ +#if 1 /* test-only */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OVERWRITE 1 +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ + /* total size of a CAT24WC32 is 8192 bytes */ +#define CONFIG_ENV_OVERWRITE 1 +#endif + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_UDP_CHECKSUM 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x01052444 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x0004DD00 + +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS1_START 0xfd000000 +#define CFG_CS1_SIZE 0x00010000 +#define CFG_CS1_CFG 0x10101410 + +#define CFG_CS3_START 0xfd010000 +#define CFG_CS3_SIZE 0x00010000 +#define CFG_CS3_CFG 0x10109410 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +/*----------------------------------------------------------------------- + * CPLD stuff + */ +#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ + +/* CPLD program pin configuration */ +#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ +#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ +#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ + +#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ +#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ + +#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00) +#define JTAG_GPIO_CFG_SET 0x00000000 +#define JTAG_GPIO_CFG_RESET 0x00F00000 + +#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04) +#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ +#define JTAG_GPIO_TMS_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ +#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00) +#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ +#define JTAG_GPIO_TCK_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08) +#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ +#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00) +#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ +#define JTAG_GPIO_TDI_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08) +#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ +#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04) +#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ +#define JTAG_GPIO_TDO_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_TDO_DDR_SET 0x00000000 +#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h new file mode 100644 index 0000000..776e1d2 --- /dev/null +++ b/include/configs/cradle.h @@ -0,0 +1,349 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE 0x10000300 +#define CONFIG_SMC91111_EXT_PHY +#define CONFIG_SMC_USE_32_BIT + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200" +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.0.21 +#define CONFIG_SERVERIP 192.168.0.250 +#define CONFIG_BOOTCOMMAND "bootm 40000" +#define CONFIG_CMDLINE_TAG + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa2000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x00020000 /* absolute address for now */ +#define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ + +/****************************************************************************** + * + * CPU specific defines + * + ******************************************************************************/ + +/* + * GPIO settings + * + * GPIO pin assignments + * GPIO Name Dir Out AF + * 0 NC + * 1 NC + * 2 SIRQ1 I + * 3 SIRQ2 I + * 4 SIRQ3 I + * 5 DMAACK1 O 0 + * 6 DMAACK2 O 0 + * 7 DMAACK3 O 0 + * 8 TC1 O 0 + * 9 TC2 O 0 + * 10 TC3 O 0 + * 11 nDMAEN O 1 + * 12 AENCTRL O 0 + * 13 PLDTC O 0 + * 14 ETHIRQ I + * 15 NC + * 16 NC + * 17 NC + * 18 RDY I + * 19 DMASIO I + * 20 ETHIRQ NC + * 21 NC + * 22 PGMEN O 1 FIXME for debug only enable flash + * 23 NC + * 24 NC + * 25 NC + * 26 NC + * 27 NC + * 28 NC + * 29 NC + * 30 NC + * 31 NC + * 32 NC + * 33 NC + * 34 FFRXD I 01 + * 35 FFCTS I 01 + * 36 FFDCD I 01 + * 37 FFDSR I 01 + * 38 FFRI I 01 + * 39 FFTXD O 1 10 + * 40 FFDTR O 0 10 + * 41 FFRTS O 0 10 + * 42 RS232FOFF O 0 00 + * 43 NC + * 44 NC + * 45 IRSL0 O 0 + * 46 IRRX0 I 01 + * 47 IRTX0 O 0 10 + * 48 NC + * 49 nIOWE O 0 + * 50 NC + * 51 NC + * 52 NC + * 53 NC + * 54 NC + * 55 NC + * 56 NC + * 57 NC + * 58 DKDIRQ I + * 59 NC + * 60 NC + * 61 NC + * 62 NC + * 63 NC + * 64 COMLED O 0 + * 65 COMLED O 0 + * 66 COMLED O 0 + * 67 COMLED O 0 + * 68 COMLED O 0 + * 69 COMLED O 0 + * 70 COMLED O 0 + * 71 COMLED O 0 + * 72 NC + * 73 NC + * 74 NC + * 75 NC + * 76 NC + * 77 NC + * 78 CSIO O 1 + * 79 NC + * 80 CSETH O 1 + * + * NOTE: All NC's are defined to be outputs + * + */ +/* Pin direction control */ +/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */ +#define CFG_GPDR0_VAL 0xfff3bf02 +#define CFG_GPDR1_VAL 0xfbffbf83 +#define CFG_GPDR2_VAL 0x0001ffff +/* Set and Clear registers */ +#define CFG_GPSR0_VAL 0x00400800 +#define CFG_GPSR1_VAL 0x00000480 +#define CFG_GPSR2_VAL 0x00014000 +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +/* Edge detect registers (these are set by the kernel) */ +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 +/* Alternate function registers */ +#define CFG_GAFR0_L_VAL 0x00000000 +#define CFG_GAFR0_U_VAL 0x00000010 +#define CFG_GAFR1_L_VAL 0x900a9550 +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0x20000000 +#define CFG_GAFR2_U_VAL 0x00000002 + +/* + * Clocks, power control and interrupts + */ +#define CFG_PSSR_VAL 0x00000020 +#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ +#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ +#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ + +/* FIXME + * + * RTC settings + * Watchdog + * + */ + +/* + * Memory settings + * + * FIXME Can ethernet be burst read and/or write?? This is set for lubbock + * Verify timings on all + */ +#define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */ +/*#define CFG_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */ +#define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */ +#define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */ +#ifdef REDBOOT_WAY +#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ +#define CFG_MDMRS_VAL 0x00000000 +#define CFG_MDREFR_VAL 0x00018018 +#else +#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ +#define CFG_MDMRS_VAL 0x00000000 +#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */ +#endif + +/* + * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +/* Board specific defines */ + +/* LED defines */ +#define YELLOW 0x03 +#define RED 0x02 +#define GREEN 0x01 +#define OFF 0x00 +#define LED_IRDA0 0 +#define LED_IRDA1 2 +#define LED_IRDA2 4 +#define LED_IRDA3 6 +#define CRADLE_LED_SET_REG GPSR2 +#define CRADLE_LED_CLR_REG GPCR2 + +/* SuperIO defines */ +#define CRADLE_SIO_INDEX 0x2e +#define CRADLE_SIO_DATA 0x2f + +/* IO defines */ +#define CRADLE_CPLD_PHYS 0x08000000 +#define CRADLE_SIO1_PHYS 0x08100000 +#define CRADLE_SIO2_PHYS 0x08200000 +#define CRADLE_SIO3_PHYS 0x08300000 +#define CRADLE_ETH_PHYS 0x10000000 + +#ifndef __ASSEMBLY__ + +/* global prototypes */ +void led_code(int code, int color); + +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h new file mode 100644 index 0000000..f04102e --- /dev/null +++ b/include/configs/csb226.h @@ -0,0 +1,472 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. + * + * Configuration for the Cogent CSB226 board. For details see + * http://www.cogcomp.com/csb_csb226.htm + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * include/configs/csb226.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DEBUG 1 + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_CSB226 1 /* on a CSB226 board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + /* for timer/console/ethernet */ +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 19200 +#undef CONFIG_MISC_INIT_R /* not used yet */ + +#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0" +#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.1.56 +#define CONFIG_SERVERIP 192.168.1.5 +#define CONFIG_BOOTCOMMAND "bootm 0x40000" +#define CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_CMDLINE_TAG 1 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ + +/* + * Size of malloc() pool; this lives below the uppermost 128 KiB which are + * used for the RAM copy of the uboot code + * + */ +#define CFG_MALLOC_LEN (128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 128 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa3000000 /* default load address */ + /* RS: where is this documented? */ + /* RS: is this where U-Boot is */ + /* RS: relocated to in RAM? */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ + /* RS: the oscillator is actually 3680130?? */ +#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ + /* 0101000001 */ + /* ^^^^^ Memory Speed 99.53 MHz */ + /* ^^ Run Mode Speed = 2x Mem Speed */ + /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ + +#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Network chip + */ +#define CONFIG_DRIVER_CS8900 1 +#define CS8900_BUS32 1 +#define CS8900_BASE 0x08000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ + +#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */ +#define CFG_DRAM_SIZE 0x02000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +# if 0 +/* FIXME: switch to _documented_ registers */ +/* + * GPIO settings + * + * GP15 == nCS1 is 1 + * GP24 == SFRM is 1 + * GP25 == TXD is 1 + * GP33 == nCS5 is 1 + * GP39 == FFTXD is 1 + * GP41 == RTS is 1 + * GP47 == TXD is 1 + * GP49 == nPWE is 1 + * GP62 == LED_B is 1 + * GP63 == TDM_OE is 1 + * GP78 == nCS2 is 1 + * GP79 == nCS3 is 1 + * GP80 == nCS4 is 1 + */ +#define CFG_GPSR0_VAL 0x03008000 +#define CFG_GPSR1_VAL 0xC0028282 +#define CFG_GPSR2_VAL 0x0001C000 + +/* GP02 == DON_RST is 0 + * GP23 == SCLK is 0 + * GP45 == USB_ACT is 0 + * GP60 == PLLEN is 0 + * GP61 == LED_A is 0 + * GP73 == SWUPD_LED is 0 + */ +#define CFG_GPCR0_VAL 0x00800004 +#define CFG_GPCR1_VAL 0x30002000 +#define CFG_GPCR2_VAL 0x00000100 + +/* GP00 == DON_READY is input + * GP01 == DON_OK is input + * GP02 == DON_RST is output + * GP03 == RESET_IND is input + * GP07 == RES11 is input + * GP09 == RES12 is input + * GP11 == SWUPDATE is input + * GP14 == nPOWEROK is input + * GP15 == nCS1 is output + * GP17 == RES22 is input + * GP18 == RDY is input + * GP23 == SCLK is output + * GP24 == SFRM is output + * GP25 == TXD is output + * GP26 == RXD is input + * GP32 == RES21 is input + * GP33 == nCS5 is output + * GP34 == FFRXD is input + * GP35 == CTS is input + * GP39 == FFTXD is output + * GP41 == RTS is output + * GP42 == USB_OK is input + * GP45 == USB_ACT is output + * GP46 == RXD is input + * GP47 == TXD is output + * GP49 == nPWE is output + * GP58 == nCPUBUSINT is input + * GP59 == LANINT is input + * GP60 == PLLEN is output + * GP61 == LED_A is output + * GP62 == LED_B is output + * GP63 == TDM_OE is output + * GP64 == nDSPINT is input + * GP65 == STRAP0 is input + * GP67 == STRAP1 is input + * GP69 == STRAP2 is input + * GP70 == STRAP3 is input + * GP71 == STRAP4 is input + * GP73 == SWUPD_LED is output + * GP78 == nCS2 is output + * GP79 == nCS3 is output + * GP80 == nCS4 is output + */ +#define CFG_GPDR0_VAL 0x03808004 +#define CFG_GPDR1_VAL 0xF002A282 +#define CFG_GPDR2_VAL 0x0001C200 + +/* GP15 == nCS1 is AF10 + * GP18 == RDY is AF01 + * GP23 == SCLK is AF10 + * GP24 == SFRM is AF10 + * GP25 == TXD is AF10 + * GP26 == RXD is AF01 + * GP33 == nCS5 is AF10 + * GP34 == FFRXD is AF01 + * GP35 == CTS is AF01 + * GP39 == FFTXD is AF10 + * GP41 == RTS is AF10 + * GP46 == RXD is AF10 + * GP47 == TXD is AF01 + * GP49 == nPWE is AF10 + * GP78 == nCS2 is AF10 + * GP79 == nCS3 is AF10 + * GP80 == nCS4 is AF10 + */ +#define CFG_GAFR0_L_VAL 0x80000000 +#define CFG_GAFR0_U_VAL 0x001A8010 +#define CFG_GAFR1_L_VAL 0x60088058 +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x00000002 + + +/* FIXME: set GPIO_RER/FER */ + +/* RDH = 1 + * PH = 1 + * VFS = 1 + * BFS = 1 + * SSS = 1 + */ +#define CFG_PSSR_VAL 0x37 + +/* + * Memory settings + * + * This is the configuration for nCS0/1 -> flash banks + * configuration for nCS1: + * [31] 0 - Slower Device + * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns + * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns + * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [19] 1 - 16 Bit bus width + * [18:16] 000 - nonburst RAM or FLASH + * configuration for nCS0: + * [15] 0 - Slower Device + * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns + * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns + * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [03] 1 - 16 Bit bus width + * [02:00] 000 - nonburst RAM or FLASH + */ +#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */ + +/* This is the configuration for nCS2/3 -> TDM-Switch, DSP + * configuration for nCS3: DSP + * [31] 0 - Slower Device + * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns + * [19] 1 - 16 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS2: TDM-Switch + * [15] 0 - Slower Device + * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns + * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns + * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */ + +/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller + * + * configuration for nCS5: LAN Controller + * [31] 0 - Slower Device + * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns + * [19] 1 - 16 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS4: ExtBus + * [15] 0 - Slower Device + * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns + * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns + * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ + +/* MDCNFG: SDRAM Configuration Register + * + * [31:29] 000 - reserved + * [28] 0 - no SA1111 compatiblity mode + * [27] 0 - latch return data with return clock + * [26] 0 - alternate addressing for pair 2/3 + * [25:24] 00 - timings + * [23] 0 - internal banks in lower partition 2/3 (not used) + * [22:21] 00 - row address bits for partition 2/3 (not used) + * [20:19] 00 - column address bits for partition 2/3 (not used) + * [18] 0 - SDRAM partition 2/3 width is 32 bit + * [17] 0 - SDRAM partition 3 disabled + * [16] 0 - SDRAM partition 2 disabled + * [15:13] 000 - reserved + * [12] 1 - SA1111 compatiblity mode + * [11] 1 - latch return data with return clock + * [10] 0 - no alternate addressing for pair 0/1 + * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk + * [7] 1 - 4 internal banks in lower partition pair + * [06:05] 10 - 13 row address bits for partition 0/1 + * [04:03] 01 - 9 column address bits for partition 0/1 + * [02] 0 - SDRAM partition 0/1 width is 32 bit + * [01] 0 - disable SDRAM partition 1 + * [00] 1 - enable SDRAM partition 0 + */ +/* use the configuration above but disable partition 0 */ +#define CFG_MDCNFG_VAL 0x000019c8 + +/* MDREFR: SDRAM Refresh Control Register + * + * [32:26] 0 - reserved + * [25] 0 - K2FREE: not free running + * [24] 0 - K1FREE: not free running + * [23] 1 - K0FREE: not free running + * [22] 0 - SLFRSH: self refresh disabled + * [21] 0 - reserved + * [20] 0 - APD: no auto power down + * [19] 0 - K2DB2: SDCLK2 is MemClk + * [18] 0 - K2RUN: disable SDCLK2 + * [17] 0 - K1DB2: SDCLK1 is MemClk + * [16] 1 - K1RUN: enable SDCLK1 + * [15] 1 - E1PIN: SDRAM clock enable + * [14] 1 - K0DB2: SDCLK0 is MemClk + * [13] 0 - K0RUN: disable SDCLK0 + * [12] 1 - E0PIN: disable SDCKE0 + * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 + */ +#define CFG_MDREFR_VAL 0x0081D018 + +/* MDMRS: Mode Register Set Configuration Register + * + * [31] 0 - reserved + * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) + * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) + * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) + * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) + * [15] 0 - reserved + * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. + * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. + * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. + * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. + */ +#define CFG_MDMRS_VAL 0x00020022 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00000000 +#define CFG_MCMEM1_VAL 0x00000000 +#define CFG_MCATT0_VAL 0x00000000 +#define CFG_MCATT1_VAL 0x00000000 +#define CFG_MCIO0_VAL 0x00000000 +#define CFG_MCIO1_VAL 0x00000000 +#endif + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0xFFFFFFFF +#define CFG_GPSR1_VAL 0xFFFFFFFF +#define CFG_GPSR2_VAL 0xFFFFFFFF +#define CFG_GPCR0_VAL 0x08022080 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPDR0_VAL 0xCD82A878 +#define CFG_GPDR1_VAL 0xFCFFAB80 +#define CFG_GPDR2_VAL 0x0001FFFF +#define CFG_GAFR0_L_VAL 0x80000000 +#define CFG_GAFR0_U_VAL 0xA5254010 +#define CFG_GAFR1_L_VAL 0x599A9550 +#define CFG_GAFR1_U_VAL 0xAAA5AAAA +#define CFG_GAFR2_L_VAL 0xAAAAAAAA +#define CFG_GAFR2_U_VAL 0x00000002 + +/* FIXME: set GPIO_RER/FER */ + +#define CFG_PSSR_VAL 0x20 + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x2ef15af0 +#define CFG_MSC1_VAL 0x00003ff4 +#define CFG_MSC2_VAL 0x7ff07ff0 +#define CFG_MDCNFG_VAL 0x09a909a9 +#define CFG_MDREFR_VAL 0x038ff030 +#define CFG_MDMRS_VAL 0x00220022 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00000000 +#define CFG_MCMEM1_VAL 0x00000000 +#define CFG_MCATT0_VAL 0x00000000 +#define CFG_MCATT1_VAL 0x00000000 +#define CFG_MCIO0_VAL 0x00000000 +#define CFG_MCIO1_VAL 0x00000000 + +#define CSB226_USER_LED0 0x00000008 +#define CSB226_USER_LED1 0x00000010 +#define CSB226_USER_LED2 0x00000020 + + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) + /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h new file mode 100644 index 0000000..27d64c1 --- /dev/null +++ b/include/configs/csb272.h @@ -0,0 +1,314 @@ +/* + * (C) Copyright 2004 + * Tolunay Orkun, Nextio Inc., torkun@nextio.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ +#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +/* + * OS Bootstrap configuration + * + */ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ +#endif + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ + +#if 1 +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs console=ttyS0,38400 debug " \ + "root=/dev/ram rw ramdisk_size=4096 " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm fe000000 fe100000" +#endif + +#if 0 +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs console=ttyS0,38400 debug " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" +#endif + +/* + * BOOTP/DHCP protocol configuration + * + */ +#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_BOOTFILESIZE ) +/* + * U-Boot Monitor Command Line Functions Configuration + * + */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_PCI | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Serial download configuration + * + */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * KGDB Configuration + * + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + * + */ +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */ +#endif + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ +#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * watchdog configuration + * + */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * UART configuration + * + */ +#define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ +#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#undef CFG_BASE_BAUD +#define CONFIG_BAUDRATE 38400 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * I2C configuration + * + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ + +/* + * MII PHY configuration + * + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ + /* 32usec min. for LXT971A */ +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ + +/* + * RTC configuration + * + * Note that DS1307 RTC is limited to 100Khz I2C bus. + * + */ +#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ + +/* + * PCI stuff + * + */ +#define CONFIG_PCI /* include pci support */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/* + * IDE stuff + * + */ +#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +/* + * Environment configuration + * + */ +#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_EEPROM + +/* + * General Memory organization + * + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_SIZE 0x02000000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ + +#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#define CFG_RAMSTART +#endif + +#if defined(CFG_ENV_IS_IN_FLASH) +#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ +#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ +#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ +#endif + +/* + * FLASH Device configuration + * + */ +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +/* + * On Chip Memory location/size + * + */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +/* + * Global info and initial stack + * + */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Cache configuration + * + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 + +/* + * Miscellaneous board specific definitions + * + */ +#define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */ +#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ + +/* + * Internal Definitions + * + * Boot Flags + * + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h new file mode 100644 index 0000000..09d52de --- /dev/null +++ b/include/configs/csb472.h @@ -0,0 +1,313 @@ +/* + * (C) Copyright 2004 + * Tolunay Orkun, Nextio Inc., torkun@nextio.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ +#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ +#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ + +/* + * OS Bootstrap configuration + * + */ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ +#endif + +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ + +#if 1 +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs console=ttyS0,38400 debug " \ + "root=/dev/ram rw ramdisk_size=4096 " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm ff800000 ff900000" +#endif + +#if 0 +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs console=ttyS0,38400 debug " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" +#endif + +/* + * BOOTP/DHCP protocol configuration + * + */ +#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_BOOTFILESIZE ) +/* + * U-Boot Monitor Command Line Functions Configuration + * + */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_PCI | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Serial download configuration + * + */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * KGDB Configuration + * + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + * + */ +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */ +#endif + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ +#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * watchdog configuration + * + */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * UART configuration + * + */ +#undef CFG_EXT_SERIAL_CLOCK /* use internal serial clock */ +#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 38400 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * I2C configuration + * + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ + +/* + * MII PHY configuration + * + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ + /* 32usec min. for LXT971A */ +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ + +/* + * RTC configuration + * + * Note that DS1307 RTC is limited to 100Khz I2C bus. + * + */ +#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ + +/* + * PCI stuff + * + */ +#define CONFIG_PCI /* include pci support */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/* + * IDE stuff + * + */ +#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +/* + * Environment configuration + * + */ +#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_EEPROM + +/* + * General Memory organization + * + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF800000 +#define CFG_FLASH_SIZE 0x00800000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ + +#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#define CFG_RAMSTART +#endif + +#if defined(CFG_ENV_IS_IN_FLASH) +#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ +#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ +#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ +#endif + +/* + * FLASH Device configuration + * + */ +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_MAX_FLASH_SECT 64 /* max # of sectors on one chip */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +/* + * On Chip Memory location/size + * + */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +/* + * Global info and initial stack + * + */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Cache configuration + * + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 + +/* + * Miscellaneous board specific definitions + * + */ +#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ + +/* + * Internal Definitions + * + * Boot Flags + * + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h new file mode 100644 index 0000000..071d5b7 --- /dev/null +++ b/include/configs/csb637.h @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2005 REA Elektronik GmbH + * Anders Larsen + * + * Configuation settings for the Cogent CSB637 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */ +#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_CSB637 1 /* on a CSB637 board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ +#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ +#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_BOOTDELAY 3 +/* #define CONFIG_ENV_OVERWRITE 1 */ + +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING ) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_IMI | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS )) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ +#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ + +#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) +#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) + +#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4 +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_SCRATCH CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4 + +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 +#undef CONFIG_AT91C_USE_RMII + +#undef CONFIG_HAS_DATAFLASH +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 0 +#define CFG_MAX_DATAFLASH_PAGES 16384 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ + +/* + * FLASH Device configuration + */ +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ +#define CFG_MAX_FLASH_SECT 64 + +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 3 +#define CFG_JFFS2_NUM_BANKS 1 + +#undef CFG_ENV_IS_IN_DATAFLASH + +#ifdef CFG_ENV_IS_IN_DATAFLASH +#define CFG_ENV_OFFSET 0x20000 +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ +#else +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */ +#define CFG_ENV_SIZE 0x20000 /* sectors are 128K here */ +#endif /* CFG_ENV_IS_IN_DATAFLASH */ + + +#define CFG_LOAD_ADDR 0x21000000 /* default load address */ + +#define CFG_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600 } + +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h new file mode 100644 index 0000000..0a10e3c --- /dev/null +++ b/include/configs/dbau1x00.h @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for the dbau1x00 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_DBAU1X00 1 +#define CONFIG_AU1X00 1 /* alchemy series cpu */ + +#ifdef CONFIG_DBAU1000 +/* Also known as Merlot */ +#define CONFIG_AU1000 1 +#else +#ifdef CONFIG_DBAU1100 +#define CONFIG_AU1100 1 +#else +#ifdef CONFIG_DBAU1500 +#define CONFIG_AU1500 1 +#else +#ifdef CONFIG_DBAU1550 +/* Cabernet */ +#define CONFIG_AU1550 1 +#else +#error "No valid board set" +#endif +#endif +#endif +#endif + +#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ + +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ + +#define CONFIG_BAUDRATE 115200 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "panic=1\0" \ + "bootfile=/tftpboot/vmlinux.srec\0" \ + "load=tftp 80500000 ${u-boot}\0" \ + "" + +#ifdef CONFIG_DBAU1550 +/* Boot from flash by default, revert to bootp */ +#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \ + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \ + CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \ + CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C)) +#else /* CONFIG_DBAU1550 */ +/* Boot from Compact flash partition 2 as default */ +#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;bootm" + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \ + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ + CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \ + CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG)) +#endif /* CONFIG_DBAU1550 */ + +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ + +#define CFG_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */ + +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ + +#define CFG_MALLOC_LEN 128*1024 + +#define CFG_BOOTPARAMS_LEN 128*1024 + +#define CFG_MHZ 396 + +#if (CFG_MHZ % 12) != 0 +#error "Invalid CPU frequency - must be multiple of 12!" +#endif + +#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ + +#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ + +#define CFG_LOAD_ADDR 0x81000000 /* default load address */ + +#define CFG_MEMTEST_START 0x80100000 +#define CFG_MEMTEST_END 0x80800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#ifdef CONFIG_DBAU1550 + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ + +#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ + +#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} + +#else /* CONFIG_DBAU1550 */ + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ + +#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ + +#endif /* CONFIG_DBAU1550 */ + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +#define CFG_INIT_SP_OFFSET 0x400000 + +/* We boot from this flash, selected with dip switch */ +#define CFG_FLASH_BASE PHYS_FLASH_2 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_NOWHERE 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR 0xB0030000 +#define CFG_ENV_SIZE 0x10000 + +#define CONFIG_FLASH_16BIT + +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_NET_MULTI + +#ifdef CONFIG_DBAU1550 +#define MEM_SIZE 192 +#else +#define MEM_SIZE 64 +#endif + +#define CONFIG_MEMSIZE_IN_BYTES + +#ifndef CONFIG_DBAU1550 +/*---ATA PCMCIA ------------------------------------*/ +#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ +#define CFG_PCMCIA_MEM_ADDR 0x20000000 +#define CONFIG_PCMCIA_SLOT_A + +#define CONFIG_ATAPI 1 +#define CONFIG_MAC_PARTITION 1 + +/* We run CF in "true ide" mode or a harddrive via pcmcia */ +#define CONFIG_IDE_PCMCIA 1 + +/* We only support one slot for now */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 8 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET 0 + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 +#endif /* CONFIG_DBAU1550 */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_ICACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */ diff --git a/include/configs/debris.h b/include/configs/debris.h new file mode 100644 index 0000000..8ff963f --- /dev/null +++ b/include/configs/debris.h @@ -0,0 +1,459 @@ +/* + * (C) Copyright 2001, 2002 + * Sangmoon Kim, Etin Systems, dogoil@etinsys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Environments */ + +/* bootargs */ +#define CONFIG_BOOTARGS \ + "console=ttyS0,9600 init=/linuxrc " \ + "root=/dev/nfs rw nfsroot=192.168.0.1:" \ + "/tftpboot/target " \ + "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \ + "255.255.255.0:debris:eth0:none " \ + "mtdparts=phys:12m(root),-(kernel)" + +/* bootcmd */ +#define CONFIG_BOOTCOMMAND \ + "tftp 800000 pImage; " \ + "setenv bootargs console=ttyS0,9600 init=/linuxrc " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:eth0:none " \ + "mtdparts=phys:12m(root),-(kernel); " \ + "bootm 800000" + +/* bootdelay */ +#define CONFIG_BOOTDELAY 5 /* autoboot 5s */ + +/* baudrate */ +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ + +/* loads_echo */ +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ + +/* ethaddr */ +#undef CONFIG_ETHADDR + +/* eth2addr */ +#undef CONFIG_ETH2ADDR + +/* eth3addr */ +#undef CONFIG_ETH3ADDR + +/* ipaddr */ +#define CONFIG_IPADDR 192.168.0.2 + +/* serverip */ +#define CONFIG_SERVERIP 192.168.0.1 + +/* autoload */ +#undef CFG_AUTOLOAD + +/* rootpath */ +#define CONFIG_ROOTPATH /tftpboot/target + +/* gatewayip */ +#define CONFIG_GATEWAYIP 192.168.0.1 + +/* netmask */ +#define CONFIG_NETMASK 255.255.255.0 + +/* hostname */ +#define CONFIG_HOSTNAME debris + +/* bootfile */ +#define CONFIG_BOOTFILE pImage + +/* loadaddr */ +#define CONFIG_LOADADDR 800000 + +/* preboot */ +#undef CONFIG_PREBOOT + +/* clocks_in_mhz */ +#undef CONFIG_CLOCKS_IN_MHZ + + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_DEBRIS 1 + +#if 0 +#define USE_DINK32 1 +#else +#undef USE_DINK32 +#endif + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_DRAM_SPEED 100 /* MHz */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGBD | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_SAVES | \ + CFG_CMD_SDRAM) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_EEPRO100_SROM_WRITE + +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET0_MEMADDR 0x80000000 +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET1_MEMADDR 0x81000000 +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x20000000 +#define CONFIG_VERY_BIG_RAM + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#if defined (USE_DINK32) +#define CFG_MONITOR_LEN 0x00040000 +#define CFG_MONITOR_BASE 0x00090000 +#define CFG_RAMBOOT 1 +#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_INIT_RAM_END 0x10000 +#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#else +#undef CFG_RAMBOOT +#define CFG_MONITOR_LEN 0x00040000 +#define CFG_MONITOR_BASE TEXT_BASE + +/*#define CFG_GBL_DATA_SIZE 256*/ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#endif + +#define CFG_FLASH_BASE 0x7C000000 +#define CFG_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */ + +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ +#define CFG_FLASH_RANGE_SIZE 0x01000000 +#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ + +/* Use first bank for JFFS2, second bank contains U-Boot. + * + * Note: fake mtd_id's used, no linux mtd map file. + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=debris-0" +#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)" +*/ + +#define CFG_ENV_IS_IN_NVRAM 1 +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_NVRAM_ACCESS_ROUTINE 1 +#define CFG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */ +#define CFG_ENV_SIZE 0x400 /* Size of the Environment - 8K */ +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ + +#define CFG_NVRAM_BASE_ADDR 0xff000000 + +/* + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS = + * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET + */ +#define CFG_NVRAM_VXWORKS_OFFS 0x6900 + +/* + * select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#ifdef CONFIG_SOFT_I2C +#error "Soft I2C is not configured properly. Please review!" +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM } + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 7372800 + +#define CFG_NS16550_COM1 0xFF080000 +#define CFG_NS16550_COM2 (CFG_NS16550_COM1 + 8) +#define CFG_NS16550_COM3 (CFG_NS16550_COM1 + 16) +#define CFG_NS16550_COM4 (CFG_NS16550_COM1 + 24) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 + +#define CFG_DLL_EXTEND 0x00 +#define CFG_PCI_HOLD_DEL 0x20 + +#define CFG_ROMNAL 15 /* rom/flash next access time */ +#define CFG_ROMFAL 31 /* rom/flash access time */ + +#define CFG_REFINT 430 /* # of clocks between CBR refresh cycles */ + +#define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ + +/* the following are for SDRAM only*/ +#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ +#define CFG_REFREC 8 /* Refresh to activate interval */ +#define CFG_RDLAT 4 /* data latency from read command */ +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 3 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#if 0 +#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ +#endif + +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + + +/* memory bank settings*/ +/* + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (0x4000000 - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x04000000 +#define CFG_BANK1_END (0x8000000 - 1) +#define CFG_BANK1_ENABLE 1 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 +/* + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#define CFG_ODCR 0x75 /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#if defined(USE_DINK32) +#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) +#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) +#else +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#endif + +/* PCI memory */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* values according to the manual */ + +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +#define CONFIG_DISK_SPINUP_TIME 1000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h new file mode 100644 index 0000000..9ac2856 --- /dev/null +++ b/include/configs/dnp1110.h @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Rolf Offermanns + * + * Configuation settings for the SSV DNP1110 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#undef CONFIG_SKIP_RELOCATE_UBOOT + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SA1110 1 /* This is an SA1110 CPU */ +#define CONFIG_DNP1110 1 /* on an DNP/1110 Board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE 0x20000300 + + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" +#define CONFIG_ETHADDR 02:80:ad:20:31:b8 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 172.22.2.23 +#define CONFIG_SERVERIP 172.22.2.22 +#define CONFIG_BOOTFILE "dnp1110" +#define CONFIG_BOOTCOMMAND "tftp; bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "DNP1110 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xc0200000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x0b /* set core clock to 220 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ +#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xF80000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h new file mode 100644 index 0000000..a014c7c --- /dev/null +++ b/include/configs/eXalion.h @@ -0,0 +1,454 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +/* #define CONFIG_MPC8240 1 */ +#define CONFIG_MPC8245 1 +#define CONFIG_EXALION 1 + +#if defined (CONFIG_MPC8240) + /* #warning ---------- eXalion with MPC8240 --------------- */ +#elif defined (CONFIG_MPC8245) + /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */ +#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245) +#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245) +#else +#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif +/* older kernels need clock in MHz newer in Hz */ + /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */ +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_BOOTDELAY 10 + + + /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_FLASH | \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ENV | \ + CFG_CMD_PCI ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 8 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_MISC_INIT_R 1 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */ + /* return real value. */ + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#undef CFG_RAMBOOT +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) + +#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +#if defined (CONFIG_MPC8240) +#define CFG_FLASH_BASE 0xFFE00000 +#define CFG_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */ +#elif defined (CONFIG_MPC8245) +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */ +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */ +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */ +#define CFG_ENV_ADDR 0xFFFC0000 +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ + +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +#define CFG_ALT_MEMTEST 1 /* use real memory test */ +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + +#define CFG_EUMB_ADDR 0xFC000000 + +/* #define CFG_ISA_MEM 0xFD000000 */ +#define CFG_ISA_IO 0xFE000000 + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE +#define FLASH_BASE1_PRELIM 0 + + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + + +/*----------------------------------------------------------------------- + * PCI stuff + */ +#define CONFIG_PCI 1 /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI 1 /* Multi ethernet cards support */ + +#define CONFIG_EEPRO100 1 + +#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */ +#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */ +#define PCI_ENET1_IOADDR 0x81000000 +#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */ +#define PCI_ENET2_IOADDR 0x82000000 +#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */ +#define PCI_ENET3_IOADDR 0x83000000 + +/*----------------------------------------------------------------------- + * NS16550 Configuration + */ +#define CFG_NS16550 1 +#define CFG_NS16550_SERIAL 1 + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 38400 + +#define CFG_NS16550_REG_SIZE 1 + +#if (CONFIG_CONS_INDEX == 1) +#define CFG_NS16550_CLK 1843200 /* COM1 only ! */ +#else +#define CFG_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); }) +#endif + +#define CFG_NS16550_COM1 (CFG_ISA_IO + 0x3F8) +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4600) + +/*----------------------------------------------------------------------- + * select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/*----------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +#define CFG_HZ 1000 + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ +#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */ + + /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */ + +#if defined (CONFIG_MPC8245) +/* Bit-field values for PMCR2. */ +#if defined (CONFIG_133MHZ_DRAM) +#define CFG_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */ +#define CFG_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */ +#endif + +/* Bit-field values for MIOCR1. */ +#if !defined (CONFIG_133MHZ_DRAM) +#define CFG_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */ +#endif +/* Bit-field values for MIOCR2. */ +#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */ + /* - note bottom 3 bits MUST be 0 */ +#endif + +/* Bit-field values for MCCR1. */ +#define CFG_ROMNAL 7 /*rom/flash next access time */ +#define CFG_ROMFAL 11 /*rom/flash access time */ + +/* Bit-field values for MCCR2. */ +#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ +#if defined (CONFIG_133MHZ_DRAM) +#define CFG_REFINT 1300 /* no of clock cycles between CBR */ +#else /* refresh cycles */ +#define CFG_REFINT 750 +#endif + +/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ +#if defined (CONFIG_133MHZ_DRAM) +#define CFG_BSTOPRE 1023 +#else +#define CFG_BSTOPRE 250 +#endif + +/* Bit-field values for MCCR3. */ +/* the following are for SDRAM only */ + +#if defined (CONFIG_133MHZ_DRAM) +#define CFG_REFREC 9 /* Refresh to activate interval */ +#else +#define CFG_REFREC 5 /* Refresh to activate interval */ +#endif +#if defined (CONFIG_MPC8240) +#define CFG_RDLAT 2 /* data latency from read command */ +#endif + +/* Bit-field values for MCCR4. */ +#if defined (CONFIG_133MHZ_DRAM) +#define CFG_PRETOACT 3 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 7 /* Activate to Precharge interval */ +#define CFG_ACTORW 5 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#else +#if 0 +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 3 /* Activate to Precharge interval */ +#define CFG_ACTORW 3 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ +#endif +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_ACTORW 3 /* Activate to R/W */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#endif +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ +#define CFG_REGDIMM 0 +#if defined (CONFIG_MPC8240) +#define CFG_REGISTERD_TYPE_BUFFER 0 +#elif defined (CONFIG_MPC8245) +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 0 +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif + + +/*----------------------------------------------------------------------- + memory bank settings + * only bits 20-29 are actually used from these vales to set the + * start/end address the upper two bits will be 0, and the lower 20 + * bits will be set to 0x00000 for a start address, or 0xfffff for an + * end address + */ +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 + +/*----------------------------------------------------------------------- + * Memory bank enable bitmask, specifying which of the banks defined above + are actually present. MSB is for bank #7, LSB is for bank #0. + */ +#define CFG_BANK_ENABLE 0x01 + +#if defined (CONFIG_MPC8240) +#define CFG_ODCR 0xDF /* configures line driver impedances, */ + /* see 8240 book for bit definitions */ +#elif defined (CONFIG_MPC8245) +#if defined (CONFIG_133MHZ_DRAM) +#define CFG_ODCR 0xFE /* configures line driver impedances - 133MHz */ +#else +#define CFG_ODCR 0xDE /* configures line driver impedances - 66MHz */ +#endif +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif + +#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ + /* currently accessed page in memory */ + /* see 8240 book for details */ + +/*----------------------------------------------------------------------- + * Block Address Translation (BAT) register settings. + */ +/* SDRAM 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* PCI memory */ +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* Flash, config addrs, etc */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +/* values according to the manual */ +#define CONFIG_DRAM_50MHZ 1 +#define CONFIG_SDRAM_50MHZ + +#undef NR_8259_INTS +#define NR_8259_INTS 1 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + */ +#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR CFG_ISA_IO /* base address */ +#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ +#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ + +#define CONFIG_ATAPI + +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* reset for ide supported... */ +#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ + +/*----------------------------------------------------------------------- + * DISK Partition support + */ +#define CONFIG_DOS_PARTITION + +/*----------------------------------------------------------------------- + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h new file mode 100644 index 0000000..a26af69 --- /dev/null +++ b/include/configs/ebony.h @@ -0,0 +1,295 @@ +/* + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_EBONY 1 /* Board is ebony */ +#define CONFIG_440GP 1 /* Specifc GP support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/* + * Define here the location of the environment variables (FLASH or NVRAM). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_NVRAM */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 32 /* sectors per device */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=ebony\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/ebony/uImage\0" \ + "kernel_addr=ff800000\0" \ + "ramdisk_addr=ff810000\0" \ + "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 8 /* PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h new file mode 100644 index 0000000..bdda629 --- /dev/null +++ b/include/configs/ep7312.h @@ -0,0 +1,163 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the EP7312 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_EP7312 1 /* on an EP7312 Board */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x20000000 +#define CS8900_BUS16 1 +#undef CS8900_BUS32 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" +#define CONFIG_ETHADDR 08:00:3e:21:c7:f7 +/*#define CONFIG_NETMASK 255.255.0.0 */ +/*#define CONFIG_IPADDR 172.22.2.128 */ +/*#define CONFIG_SERVERIP 172.22.2.126 */ +/*#define CONFIG_BOOTFILE "impa7" */ +#define CONFIG_BOOTCOMMAND "bootp;bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "EP7312 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xc0500000 /* default load address */ + +#define CFG_HZ 2000 /* decrementer freq: 2 kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=ep7312-0" +#define MTDPARTS_DEFAULT "mtdparts=ep7312-0:-(jffs2)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h new file mode 100644 index 0000000..04147a5 --- /dev/null +++ b/include/configs/ep8248.h @@ -0,0 +1,277 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen + * + * U-Boot configuration for Embedded Planet EP8248 boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC8248 +#define CPU_ID_STR "MPC8248" + +#define CONFIG_EP8248 /* Embedded Planet EP8248 board */ + +#undef DEBUG + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ + +#define CFG_BCSR 0xFA000000 + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ + +#ifdef CONFIG_ETHER_ON_FCC + +#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ + +#if (CONFIG_ETHER_INDEX == 1) + +/* - Rx clock is CLK10 + * - Tx clock is CLK11 + * - BDs/buffers on 60x bus + * - Full duplex + */ +#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#elif (CONFIG_ETHER_INDEX == 2) + +/* - Rx clock is CLK13 + * - Tx clock is CLK14 + * - BDs/buffers on 60x bus + * - Full duplex + */ +#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_INDEX */ + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 0 /* Not used - implemented in BCSR */ +#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB) +#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04) +#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1) + +#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \ + else *(vu_char *)(CFG_BCSR + 8) &= 0xFE + +#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \ + else *(vu_char *)(CFG_BCSR + 8) &= 0xFD + +#define MIIDELAY udelay(1) + +#endif /* CONFIG_ETHER_ON_FCC */ + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ + | CFG_CMD_I2C \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_FLASH_BASE 0xFF800000 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ + +#define CFG_DIRECT_FLASH_TFTP + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS +#define CFG_JFFS2_FIRST_SECTOR 0 +#define CFG_JFFS2_LAST_SECTOR 62 +#define CFG_JFFS2_SORT_FRAGMENTS +#define CFG_JFFS_CUSTOM_PART +#endif /* CFG_CMD_JFFS2 */ + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ +#endif /* CFG_CMD_I2C */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ + +#define CFG_ENV_IS_IN_FLASH + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#endif /* CFG_ENV_IS_IN_FLASH */ + +#define CFG_DEFAULT_IMMR 0x00010000 + +#define CFG_IMMR 0xF0000000 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* Hard reset configuration word */ +#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */ +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) + +#define CFG_HID2 0 + +#define CFG_SIUMCR 0x01240200 +#define CFG_SYPCR 0xFFFF0683 +#define CFG_BCR 0x00000000 +#define CFG_SCCR SCCR_DFBRG01 + +#define CFG_RMR RMR_CSRE +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) +#define CFG_RCCR 0 + +#define CFG_MPTPR 0x1300 +#define CFG_PSDMR 0x82672522 +#define CFG_PSRT 0x4B + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00001841) +#define CFG_SDRAM_OR 0xFF0030C0 + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) +#define CFG_OR0_PRELIM 0xFF8008C2 +#define CFG_BR2_PRELIM (CFG_BCSR | 0x00000801) +#define CFG_OR2_PRELIM 0xFFF00864 + +#define CFG_RESET_ADDRESS 0xC0000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h new file mode 100644 index 0000000..6862519 --- /dev/null +++ b/include/configs/ep8260.h @@ -0,0 +1,775 @@ +/* + * (C) Copyright 2002 + * Frank Panno , Delphin Technology AG + * + * This file is based on similar values for other boards found in other + * U-Boot config files, and some that I found in the EP8260 manual. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + * + * "EP8260 H, V.1.1" + * - 64M 60x Bus SDRAM + * - 32M Local Bus SDRAM + * - 16M Flash (4 x AM29DL323DB90WDI) + * - 128k NVRAM with RTC + * + * "EP8260 H2, V.1.3" (CFG_EP8260_H2) + * - 300MHz/133MHz/66MHz + * - 64M 60x Bus SDRAM + * - 32M Local Bus SDRAM + * - 32M Flash + * - 128k NVRAM with RTC + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Define this to enable support the EP8260 H2 version */ +#define CFG_EP8260_H2 1 +/* #undef CFG_EP8260_H2 */ + +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* What is the oscillator's (UX2) frequency in Hz? */ +#define CONFIG_8260_CLKIN (66 * 1000 * 1000) + +/*----------------------------------------------------------------------- + * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual + *----------------------------------------------------------------------- + * What should MODCK_H be? It is dependent on the oscillator + * frequency, MODCK[1-3], and desired CPM and core frequencies. + * Here are some example values (all frequencies are in MHz): + * + * MODCK_H MODCK[1-3] Osc CPM Core + * ------- ---------- --- --- ---- + * 0x2 0x2 33 133 133 + * 0x2 0x3 33 133 166 + * 0x2 0x4 33 133 200 + * 0x2 0x5 33 133 233 + * 0x2 0x6 33 133 266 + * + * 0x5 0x5 66 133 133 + * 0x5 0x6 66 133 166 + * 0x5 0x7 66 133 200 * + * 0x6 0x0 66 133 233 + * 0x6 0x1 66 133 266 + * 0x6 0x2 66 133 300 + */ +#ifdef CFG_EP8260_H2 +#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110) +#else +#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110) +#endif + +/* Define this if you want to boot from 0x00000100. If you don't define + * this, you will need to program the bootloader to 0xfff00000, and + * get the hardware reset config words at 0xfe000000. The simplest + * way to do that is to program the bootloader at both addresses. + * It is suggested that you just let U-Boot live at 0x00000000. + */ +/* #define CFG_SBC_BOOT_LOW 1 */ /* only for HRCW */ +/* #undef CFG_SBC_BOOT_LOW */ + +/* The reset command will not work as expected if the reset address does + * not point to the correct address. + */ + +#define CFG_RESET_ADDRESS 0xFFF00100 + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk + * The main FLASH is whichever is connected to *CS0. U-Boot expects + * this to be the SIMM. + */ +#ifdef CFG_EP8260_H2 +#define CFG_FLASH0_BASE 0xFE000000 +#define CFG_FLASH0_SIZE 32 +#else +#define CFG_FLASH0_BASE 0xFF000000 +#define CFG_FLASH0_SIZE 16 +#endif + +/* What should the base address of the secondary FLASH be and how big + * is it (in Mbytes)? The secondary FLASH is whichever is connected + * to *CS6. U-Boot expects this to be the on board FLASH. If you don't + * want it enabled, don't define these constants. + */ +#define CFG_FLASH1_BASE 0 +#define CFG_FLASH1_SIZE 0 +#undef CFG_FLASH1_BASE +#undef CFG_FLASH1_SIZE + +/* What should be the base address of SDRAM DIMM (60x bus) and how big is + * it (in Mbytes)? +*/ +#define CFG_SDRAM0_BASE 0x00000000 +#define CFG_SDRAM0_SIZE 64 + +/* define CFG_LSDRAM if you want to enable the 32M SDRAM on the + * local bus (8260 local bus is NOT cacheable!) +*/ +/* #define CFG_LSDRAM */ +#undef CFG_LSDRAM + +#ifdef CFG_LSDRAM +/* What should be the base address of SDRAM DIMM (local bus) and how big is + * it (in Mbytes)? +*/ + #define CFG_SDRAM1_BASE 0x04000000 + #define CFG_SDRAM1_SIZE 32 +#else + #define CFG_SDRAM1_BASE 0 + #define CFG_SDRAM1_SIZE 0 + #undef CFG_SDRAM1_BASE + #undef CFG_SDRAM1_SIZE +#endif /* CFG_LSDRAM */ + +/* What should be the base address of NVRAM and how big is + * it (in Bytes) + */ +#define CFG_NVRAM_BASE_ADDR 0xFA080000 +#define CFG_NVRAM_SIZE (128*1024)-16 + +/* The RTC is a Dallas DS1556 + */ +#define CONFIG_RTC_DS1556 + +/* What should be the base address of the LEDs and switch S0? + * If you don't want them enabled, don't define this. + */ +#define CFG_LED_BASE 0x00000000 +#undef CFG_LED_BASE + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere. + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on neither */ +#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ +#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ + +#if ( CONFIG_ETHER_INDEX == 3 ) + +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK16 + * - RAM for BD/Buffers is on the local Bus (see 28-13) + * - Enable Half Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) + +/* + * - RAM for BD/Buffers is on the local Bus (see 28-13) + */ +#ifdef CFG_LSDRAM + #define CFG_CPMFCR_RAMTYPE 3 +#else /* CFG_LSDRAM */ + #define CFG_CPMFCR_RAMTYPE 0 +#endif /* CFG_LSDRAM */ + +/* - Enable Half Duplex in FSMR */ +/* # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ +# define CFG_FCC_PSMR 0 + +#else /* CONFIG_ETHER_INDEX */ +# error "on EP8260 ethernet must be FCC3" +#endif /* CONFIG_ETHER_INDEX */ + +/* + * select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#ifdef CONFIG_SOFT_I2C +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +/* #define CONFIG_RTC_DS174x */ + +/* Define this to reserve an entire FLASH sector (256 KB) for + * environment variables. Otherwise, the environment will be + * put in the same sector as U-Boot, and changing variables + * will erase U-Boot temporarily + */ +#define CFG_ENV_IN_OWN_SECT + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* What should the console's baud rate be? */ +#ifdef CFG_EP8260_H2 +#define CONFIG_BAUDRATE 9600 +#else +#define CONFIG_BAUDRATE 115200 +#endif + +/* Ethernet MAC address */ +#define CONFIG_ETHADDR 00:10:EC:00:30:8C + +#define CONFIG_IPADDR 192.168.254.130 +#define CONFIG_SERVERIP 192.168.254.49 + +/* Set to a positive value to delay for running BOOTCOMMAND */ +#define CONFIG_BOOTDELAY -1 + +/* undef this to save memory */ +#define CFG_LONGHELP + +/* Monitor Command Prompt */ +#define CFG_PROMPT "=> " + +/* Define this variable to enable the "hush" shell (from + Busybox) as command line interpreter, thus enabling + powerful command line syntax like + if...then...else...fi conditionals or `&&' and '||' + constructs ("shell scripts"). + If undefined, you get the old, much simpler behaviour + with a somewhat smapper memory footprint. +*/ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* What U-Boot subsytems do you want enabled? */ +/* +*/ +#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ + ~( CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DCR | \ + CFG_CMD_DHCP | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_MII | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_UNIVERSE| \ + CFG_CMD_USB | \ + CFG_CMD_VFD | \ + CFG_CMD_XIMG ) ) + + +/* Where do the internal registers live? */ +#define CFG_IMMR 0xF0000000 +#define CFG_DEFAULT_IMMR 0x00010000 + +/* Where do the on board registers (CS4) live? */ +#define CFG_REGS_BASE 0xFA000000 + +/***************************************************************************** + * + * You should not have to modify any of the following settings + * + *****************************************************************************/ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) + +#define CFG_MAXARGS 8 /* max number of command args */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#ifdef CFG_LSDRAM + #define CFG_MEMTEST_START 0x04000000 /* memtest works on */ + #define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ +#else + #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ + #define CFG_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */ +#endif /* CFG_LSDRAM */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CFG_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_SDRAM_BASE CFG_SDRAM0_BASE + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + */ + +#if defined(CFG_SBC_BOOT_LOW) +# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) +#else +# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000) +#endif /* defined(CFG_SBC_BOOT_LOW) */ + +#ifdef CFG_EP8260_H2 +/* get the HRCW ISB field from CFG_DEFAULT_IMMR */ +#define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\ + ((CFG_DEFAULT_IMMR & 0x01000000) >> 7) |\ + ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) ) + +#define CFG_HRCW_MASTER (HRCW_EBM |\ + HRCW_L2CPC01 |\ + CFG_SBC_HRCW_IMMR |\ + HRCW_APPC10 |\ + HRCW_CS10PC01 |\ + CFG_SBC_MODCK_H |\ + CFG_SBC_HRCW_BOOT_FLAGS) +#else +#define CFG_HRCW_MASTER 0x10400245 +#endif + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CFG_RAMBOOT is platform dependent. + */ +#define CFG_MONITOR_BASE TEXT_BASE + + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#ifdef CFG_EP8260_H2 +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#else +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#endif + +#ifdef CFG_EP8260_H2 +#define CFG_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#else +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ +#endif + +#ifndef CFG_RAMBOOT +# define CFG_ENV_IS_IN_FLASH 1 + +# ifdef CFG_ENV_IN_OWN_SECT +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +# define CFG_ENV_SECT_SIZE 0x40000 +# else +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) +# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ +# endif /* CFG_ENV_IN_OWN_SECT */ +#else +# define CFG_ENV_IS_IN_NVRAM 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +# define CFG_ENV_SIZE 0x200 +#endif /* CFG_RAMBOOT */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE |\ + HID0_DCE |\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) +#ifdef CFG_LSDRAM +/* 8260 local bus is NOT cacheable */ +#define CFG_HID0_FINAL (/*HID0_ICE |*/\ + HID0_IFEM |\ + HID0_ABE |\ + HID0_EMCP) +#else /* !CFG_LSDRAM */ +#define CFG_HID0_FINAL (HID0_ICE |\ + HID0_IFEM |\ + HID0_ABE |\ + HID0_EMCP) +#endif /* CFG_LSDRAM */ + +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register + *----------------------------------------------------------------------- + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR (BCR_EBM |\ + BCR_PLDP |\ + BCR_EAV |\ + BCR_NPQM0) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_L2CPC01 |\ + SIUMCR_APPC10 |\ + SIUMCR_CS10PC01) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#ifdef CFG_EP8260_H2 +/* TBD: Find out why setting the BMT to 0xff causes the FCC to + * generate TX buffer underrun errors for large packets under + * Linux + */ +#define CFG_SYPCR_BMT 0x00000600 +#else +#define CFG_SYPCR_BMT SYPCR_BMT +#endif + +#ifdef CFG_LSDRAM +#define CFG_SYPCR (SYPCR_SWTC |\ + CFG_SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC |\ + CFG_SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC |\ + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#ifdef CFG_EP8260_H2 +#define CFG_PISCR (PISCR_PS |\ + PISCR_PTF |\ + PISCR_PTE) +#else +#define CFG_PISCR 0 +#endif + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#ifdef CFG_EP8260_H2 +#define CFG_SCCR (SCCR_DFBRG00) +#else +#define CFG_SCCR (SCCR_DFBRG01) +#endif + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/*----------------------------------------------------------------------- + * MPTPR - Memory Refresh Timer Prescale Register 10-32 + *----------------------------------------------------------------------- + */ +#define CFG_MPTPR (0x0A00 & MPTPR_PTP_MSK) + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI) + * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG) + * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG) + * 3 unused + * 4 60x GPCM 8 bit Board Regs, NVRTC + * 5 unused + * 6 unused + * 7 unused + * 8 PCMCIA + * 9 unused + * 10 unused + * 11 unused +*/ + +/*----------------------------------------------------------------------- + * BRx - Base Register + * Ref: Section 10.3.1 on page 10-14 + * ORx - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 0 - FLASH + * + */ +#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_DECC_NONE |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_8_CLK |\ + ORxG_EHTR) + +/* Bank 1 - SDRAM + * PSDRAM + */ +#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A6 |\ + ORxS_NUMR_12) + +#ifdef CFG_EP8260_H2 +#define CFG_PSDMR 0xC34E246E +#else +#define CFG_PSDMR 0xC34E2462 +#endif + +#define CFG_PSRT 0x64 + +#ifdef CFG_LSDRAM +/* Bank 2 - SDRAM + * LSDRAM + */ + + #define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) + + #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) + + #define CFG_LSDMR 0x416A2562 + #define CFG_LSRT 0x64 +#else + #define CFG_LSRT 0x0 +#endif /* CFG_LSDRAM */ + +/* Bank 4 - On board registers + * NVRTC and BCSR + */ +#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) +/* +#define CFG_OR4_PRELIM (ORxG_AM_MSK |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_10_CLK |\ + ORxG_TRLX) +*/ +#define CFG_OR4_PRELIM 0xfff00854 + +#ifdef _NOT_USED_SINCE_NOT_WORKING_ +/* Bank 8 - On board registers + * PCMCIA (currently not working!) + */ +#define CFG_BR8_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR8_PRELIM (ORxG_AM_MSK |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SETA |\ + ORxG_SCY_10_CLK) +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "" +#define MTDPARTS_DEFAULT "" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h new file mode 100644 index 0000000..88c2c74 --- /dev/null +++ b/include/configs/evb4510.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * Configuation settings for evb4510 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start u-boot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + * + * Also swap the flash1 and flash2 addresses during debug. + * + * #define CONFIG_SKIP_LOWLEVEL_INIT + */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ +#define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */ +#define CONFIG_EVB4510 1 /* on an EVB4510 Board */ + +#define CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) +#define CONFIG_STACKSIZE_FIQ (4*1024) + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_S3C4510_ETH 1 +#define CONFIG_DRIVER_S3C4510_I2C 1 +#define CONFIG_DRIVER_S3C4510_UART 1 +#define CONFIG_DRIVER_S3C4510_FLASH 1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1, could also use 2 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 19200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_ETHADDR 00:40:95:36:35:33 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.11 +#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */ + +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTCOMMAND "tftp 100000 uImage" +/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "evb4510 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_CMDLINE_TAG /* allow passing of command line args to linux */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00780000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00000000 /* default load address */ + +#define CFG_SYS_CLK_FREQ 50000000 /* CPU freq: 50 MHz */ +#define CFG_HZ 1000 /* decrementer freq: 1 KHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map after relocation + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ + +#define PHYS_FLASH_1 0x01000000 /* Flash Bank #1 */ +#define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip, 8bit access) */ + +#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ +#define PHYS_FLASH_2_SIZE 0x00080000 /* 512KB (one chip, 8bit access) */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_FLASH_SIZE PHYS_FLASH_1_SIZE + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ +#define CFG_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (4*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +/* environment settings */ +#define CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_NOWHERE + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x20000) /* environment start address */ +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x1000 /* max size for environment */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h new file mode 100644 index 0000000..b68a2dc --- /dev/null +++ b/include/configs/gcplus.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * 2003-2004 (c) MontaVista Software, Inc. + * + * Configuation settings for the ADS GraphicsClient+ board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000. + * We don't actually init RAM in this case since we're using U-Boot as + * an secondary boot loader during Linux kernel development and testing, + * e.g. bootp/tftp download of the kernel is a far more convenient + * when testing new kernels on this target. However the ADS GCPlus Linux + * boot ROM leaves the MMU enabled when it passes control to U-Boot. So + * we use lowlevel_init (CONFIG_INIT_CRITICAL) to remedy that problem. + */ +#undef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT 1 + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ +#define CONFIG_GCPLUS 1 /* on an ADS GCPlus Board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */ + + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */ +#define CONFIG_LAN91C96_BASE 0x100e0000 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on ADS GCPlus */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp" +#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" +#define CFG_AUTOLOAD "n" /* No autoload */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "ADS GCPlus # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xc0000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +#define PHYS_SDRAM_2 0xc8000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */ + + +#define PHYS_FLASH_1 0x08000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ +#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#if 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ +#else +/* REVISIT: This doesn't work on ADS GCPlus just yet: */ +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ +/*#define CFG_FLASH_PROTECTION 1 /--* hardware flash protection */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE + +#endif /* __CONFIG_H */ diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h new file mode 100644 index 0000000..6c08043 --- /dev/null +++ b/include/configs/gw8260.h @@ -0,0 +1,821 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Oliver Brown + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*********************************************************************/ +/* DESCRIPTION: + * This file contains the board configuartion for the GW8260 board. + * + * MODULE DEPENDENCY: + * None + * + * RESTRICTIONS/LIMITATIONS: + * None + * + * Copyright (c) 2001, Advent Networks, Inc. + */ +/*********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Enable debug prints */ +#undef DEBUG /* General debug */ +#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ + +/* What is the oscillator's (UX2) frequency in Hz? */ +#define CONFIG_8260_CLKIN (66 * 1000 * 1000) + +/*----------------------------------------------------------------------- + * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual + *----------------------------------------------------------------------- + * What should MODCK_H be? It is dependent on the oscillator + * frequency, MODCK[1-3], and desired CPM and core frequencies. + * Here are some example values (all frequencies are in MHz): + * + * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 + * ------- ---------- --- --- ---- ----- ----- ----- + * 0x5 0x5 66 133 133 Open Close Open + * 0x5 0x6 66 133 166 Open Open Close + * 0x5 0x7 66 133 200 Open Open Open + * 0x6 0x0 66 133 233 Close Close Close + * 0x6 0x1 66 133 266 Close Close Open + * 0x6 0x2 66 133 300 Close Open Close + */ +#define CFG_SBC_MODCK_H 0x05 + +/* Define this if you want to boot from 0x00000100. If you don't define + * this, you will need to program the bootloader to 0xfff00000, and + * get the hardware reset config words at 0xfe000000. The simplest + * way to do that is to program the bootloader at both addresses. + * It is suggested that you just let U-Boot live at 0x00000000. + */ +#define CFG_SBC_BOOT_LOW 1 + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk + * The main FLASH is whichever is connected to *CS0. U-Boot expects + * this to be the SIMM. + */ +#define CFG_FLASH0_BASE 0x40000000 +#define CFG_FLASH0_SIZE 8 + +/* Define CFG_FLASH_CHECKSUM to enable flash checksum during boot. + * Note: the 'flashchecksum' environment variable must also be set to 'y'. + */ +#define CFG_FLASH_CHECKSUM + +/* What should be the base address of SDRAM DIMM and how big is + * it (in Mbytes)? + */ +#define CFG_SDRAM0_BASE 0x00000000 +#define CFG_SDRAM0_SIZE 64 + +/* + * DRAM tests + * CFG_DRAM_TEST - enables the following tests. + * + * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines + * Environment variable 'test_dram_data' must be + * set to 'y'. + * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely + * addressable. Environment variable + * 'test_dram_address' must be set to 'y'. + * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. + */ +#define CFG_DRAM_TEST +#if defined(CFG_DRAM_TEST) +#define CFG_DRAM_TEST_DATA +#define CFG_DRAM_TEST_ADDRESS +#define CFG_DRAM_TEST_WALK +#endif /* CFG_DRAM_TEST */ + +/* + * GW8260 with 16 MB DIMM: + * + * 0x0000 0000 Exception Vector code, 8k + * : + * 0x0000 1FFF + * 0x0000 2000 Free for Application Use + * : + * : + * + * : + * : + * 0x00F5 FF30 Monitor Stack (Growing downward) + * Monitor Stack Buffer (0x80) + * 0x00F5 FFB0 Board Info Data + * 0x00F6 0000 Malloc Arena + * : CFG_ENV_SECT_SIZE, 256k + * : CFG_MALLOC_LEN, 128k + * 0x00FC 0000 RAM Copy of Monitor Code + * : CFG_MONITOR_LEN, 256k + * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 + */ + +/* + * GW8260 with 64 MB DIMM: + * + * 0x0000 0000 Exception Vector code, 8k + * : + * 0x0000 1FFF + * 0x0000 2000 Free for Application Use + * : + * : + * + * : + * : + * 0x03F5 FF30 Monitor Stack (Growing downward) + * Monitor Stack Buffer (0x80) + * 0x03F5 FFB0 Board Info Data + * 0x03F6 0000 Malloc Arena + * : CFG_ENV_SECT_SIZE, 256k + * : CFG_MALLOC_LEN, 128k + * 0x03FC 0000 RAM Copy of Monitor Code + * : CFG_MONITOR_LEN, 256k + * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 + */ + + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere. + */ +#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on neither */ +#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ + +#undef CONFIG_ETHER_ON_SCC +#define CONFIG_ETHER_ON_FCC +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ + +#ifdef CONFIG_ETHER_ON_SCC +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ +#endif /* CONFIG_ETHER_ON_SCC */ + +#ifdef CONFIG_ETHER_ON_FCC +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +/* + * Port pins used for bit-banged MII communictions (if applicable). + */ +#define MDIO_PORT 2 /* Port C */ +#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +#define MDIO_READ ((iop->pdat & 0x00400000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + +#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + +#define MIIDELAY udelay(1) +#endif /* CONFIG_ETHER_ON_FCC */ + +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) + +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK16 + * - Select bus for bd/buffers (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + +/* Define this to reserve an entire FLASH sector (256 KB) for + * environment variables. Otherwise, the environment will be + * put in the same sector as U-Boot, and changing variables + * will erase U-Boot temporarily + */ +#define CFG_ENV_IN_OWN_SECT + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* What should the console's baud rate be? */ +#define CONFIG_BAUDRATE 115200 + +/* Ethernet MAC address - This is set to all zeros to force an + * an error if we use BOOTP without setting + * the MAC address + */ +#define CONFIG_ETHADDR 00:00:00:00:00:00 + +/* Set to a positive value to delay for running BOOTCOMMAND */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* Be selective on what keys can delay or stop the autoboot process + * To stop use: " " + */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" +#define CONFIG_AUTOBOOT_STOP_STR " " +#undef CONFIG_AUTOBOOT_DELAY_STR +#define DEBUG_BOOTKEYS 0 + +/* Add support for a few extra bootp options like: + * - File size + * - DNS + */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS) + +/* undef this to save memory */ +#define CFG_LONGHELP + +/* Monitor Command Prompt */ +#define CFG_PROMPT "=> " + +/* What U-Boot subsytems do you want enabled? */ +#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ECHO | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MII) + +/* Where do the internal registers live? */ +#define CFG_IMMR 0xf0000000 + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* What is the address of IO controller */ +#define CFG_IO_BASE 0xe0000000 + +/***************************************************************************** + * + * You should not have to modify any of the following settings + * + *****************************************************************************/ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_GW8260 1 /* on an GW8260 Board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) + +#define CFG_MAXARGS 8 /* max number of command args */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Convert clocks to MHZ when passing board info to kernel. + * This must be defined for eariler 2.4 kernels (~2.4.4). + */ +#define CONFIG_CLOCKS_IN_MHZ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/* memtest works from the end of the exception vector table + * to the end of the DRAM less monitor and malloc area + */ +#define CFG_MEMTEST_START 0x2000 + +#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ + +#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ + + CFG_MALLOC_LEN \ + + CFG_ENV_SECT_SIZE \ + + CFG_STACK_USAGE ) + +#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ + - CFG_MEM_END_USAGE ) + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE +#define CFG_SDRAM_BASE CFG_SDRAM0_BASE +#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + */ +#if defined(CFG_SBC_BOOT_LOW) +# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) +#else +# define CFG_SBC_HRCW_BOOT_FLAGS (0) +#endif /* defined(CFG_SBC_BOOT_LOW) */ + +/* get the HRCW ISB field from CFG_IMMR */ +#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ + ((CFG_IMMR & 0x01000000) >> 7) | \ + ((CFG_IMMR & 0x00100000) >> 4) ) + +#define CFG_HRCW_MASTER ( HRCW_BPS11 | \ + HRCW_DPPC11 | \ + CFG_SBC_HRCW_IMMR | \ + HRCW_MMR00 | \ + HRCW_LBPC11 | \ + HRCW_APPC10 | \ + HRCW_CS10PC00 | \ + (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ + CFG_SBC_HRCW_BOOT_FLAGS ) + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CFG_RAMBOOT is platform dependent. + */ +#define CFG_MONITOR_BASE CFG_FLASH0_BASE + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 + +#ifdef CFG_ENV_IN_OWN_SECT +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + (256 * 1024)) +# define CFG_ENV_SECT_SIZE (256 * 1024) +#else +# define CFG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */ +# define CFG_ENV_ADD ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) - CFG_ENV_SIZE) +# define CFG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */ +#endif /* CFG_ENV_IN_OWN_SECT */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE |\ + HID0_DCE |\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) + +#define CFG_HID0_FINAL (HID0_ICE |\ + HID0_IFEM |\ + HID0_ABE |\ + HID0_EMCP) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register + *----------------------------------------------------------------------- + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR (BCR_ETM) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_DPPC11 |\ + SIUMCR_L2CPC00 |\ + SIUMCR_APPC10 |\ + SIUMCR_MMR00) + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#define CFG_SYPCR (SYPCR_SWTC |\ + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP) + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC |\ + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS |\ + PISCR_PTF |\ + PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#define CFG_SCCR 0 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Initialize Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) + * 1 60x GPCM 32 bit unused + * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB) + * 3 60x SDRAM 64 bit unused + * 4 Local GPCM 8 bit IO (on board - 64k) + * 5 60x GPCM 8 bit unused + * 6 60x GPCM 8 bit unused + * 7 60x GPCM 8 bit unused + * + */ + +/*----------------------------------------------------------------------- + * BR0 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR0 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 0,1 - FLASH SIMM + * + * This expects the FLASH SIMM to be connected to *CS0 + * It consists of 4 AM29F016D parts. + * + * Note: For the 8 MB SIMM, *CS1 is unused. + */ + +/* BR0 is configured as follows: + * + * - Base address of 0x40000000 + * - 32 bit port size + * - Data errors checking is disabled + * - Read and write access + * - GPCM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +/* OR0 is configured as follows: + * + * - 8 MB + * - *BCTL0 is asserted upon access to the current memory bank + * - *CW / *WE are negated a quarter of a clock earlier + * - *CS is output at the same time as the address lines + * - Uses a clock cycle length of 5 + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + +/*----------------------------------------------------------------------- + * BR2 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR2 - Option Register + * Ref: Section 10.3.2 on page 10-16 + *----------------------------------------------------------------------- + */ + +/* Bank 2 - SDRAM DIMM + * + * 16MB DIMM: P/N + * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or + * MT4LSDT864AG-10EB1 (Micron) + * + * Note: *CS3 is unused for this DIMM + */ + +/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows: + * + * - Base address of 0x00000000 + * - 64 bit port size (60x bus only) + * - Data errors checking is disabled + * - Read and write access + * - SDRAM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +/* With a 16 MB DIMM, the OR2 is configured as follows: + * + * - 16 MB + * - 2 internal banks per device + * - Row start address bit is A9 with PSDMR[PBI] = 0 + * - 11 row address lines + * - Back-to-back page mode + * - Internal bank interleaving within save device enabled + */ +#if (CFG_SDRAM0_SIZE == 16) +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ + ORxS_BPD_2 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_11) + +/* With a 16 MB DIMM, the PSDMR is configured as follows: + * + * - Page Based Interleaving, + * - Refresh Enable, + * - Address Multiplexing where A5 is output on A14 pin + * (A6 on A15, and so on), + * - use address pins A16-A18 as bank select, + * - A9 is output on SDA10 during an ACTIVATE command, + * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, + * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 3 clocks, + * - earliest timing for READ/WRITE command after ACTIVATE command is + * 2 clocks, + * - earliest timing for PRECHARGE after last data was read is 1 clock, + * - earliest timing for PRECHARGE after last data was written is 1 clock, + * - CAS Latency is 2. + */ + +/*----------------------------------------------------------------------- + * PSDMR - 60x Bus SDRAM Mode Register + * Ref: Section 10.3.3 on page 10-21 + *----------------------------------------------------------------------- + */ +#define CFG_PSDMR (PSDMR_RFEN |\ + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A16_A18 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) +#endif /* (CFG_SDRAM0_SIZE == 16) */ + +/* With a 64 MB DIMM, the OR2 is configured as follows: + * + * - 64 MB + * - 4 internal banks per device + * - Row start address bit is A8 with PSDMR[PBI] = 0 + * - 12 row address lines + * - Back-to-back page mode + * - Internal bank interleaving within save device enabled + */ +#if (CFG_SDRAM0_SIZE == 64) +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A8 |\ + ORxS_NUMR_12) + +/* With a 64 MB DIMM, the PSDMR is configured as follows: + * + * - Page Based Interleaving, + * - Refresh Enable, + * - Address Multiplexing where A5 is output on A14 pin + * (A6 on A15, and so on), + * - use address pins A14-A16 as bank select, + * - A9 is output on SDA10 during an ACTIVATE command, + * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, + * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 3 clocks, + * - earliest timing for READ/WRITE command after ACTIVATE command is + * 2 clocks, + * - earliest timing for PRECHARGE after last data was read is 1 clock, + * - earliest timing for PRECHARGE after last data was written is 1 clock, + * - CAS Latency is 2. + */ + +/*----------------------------------------------------------------------- + * PSDMR - 60x Bus SDRAM Mode Register + * Ref: Section 10.3.3 on page 10-21 + *----------------------------------------------------------------------- + */ +#define CFG_PSDMR (PSDMR_RFEN |\ + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) +#endif /* (CFG_SDRAM0_SIZE == 64) */ + +#define CFG_PSRT 0x0e +#define CFG_MPTPR MPTPR_PTP_DIV32 + + +/*----------------------------------------------------------------------- + * BR4 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR4 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ +/* Bank 4 - Onboard Memory Mapped IO controller + * + * This expects the onboard IO controller to connected to *CS4 and + * the local bus. + * - Base address of 0xe0000000 + * - 8 bit port size (local bus only) + * - Read and write access + * - GPCM local bus + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + * - extended hold time + * - 11 wait states + */ + +#ifdef CFG_IO_BASE +# define CFG_BR4_PRELIM ((CFG_IO_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_L |\ + BRx_V) + +# define CFG_OR4_PRELIM (ORxG_AM_MSK |\ + ORxG_SCY_11_CLK |\ + ORxG_EHTR) +#endif /* CFG_IO_BASE */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h new file mode 100644 index 0000000..e0d823f --- /dev/null +++ b/include/configs/h2_p2_dbg_board.h @@ -0,0 +1,138 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * TI H2 and P2 Debug Board hardware map + * + * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk) + * Author: MPC-Data Limited + * Dave Peverley + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __INCLUDED_H2_P2_DBH_BOARD_H +#define __INCLUDED_H2_P2_DBH_BOARD_H + +#include + +/* + * The Debug board is designed to function with the P2 Sample, H2 + * Sample and 1610 Innovator boards. The main difference AFAICT is + * the chip selects used with each system ; + * + * P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs + * H2 Sample : CS1a is used to select the CPLD registers. + * + */ + +/*************************************************************************** + * CPLD Registers + **************************************************************************/ + +#define H2DBG_CPLD_REVISION 0x04000010 +#define H2DBG_BOARD_REVISION 0x04000012 +#define H2DBG_GPIO_REGISTER 0x04000014 +#define H2DBG_LED_CONTROL 0x04000016 +#define H2DBG_MISC_INPUT 0x04000018 +#define H2DBG_LAN_STATUS 0x0400001A +#define H2DBG_LAN_RESET 0x0400001C +#define H2DBG_ETH_REG_BASE 0x04000300 + +/*************************************************************************** + * Ethernet Control Registers + * These are for the LAN91C96 on the debug board + **************************************************************************/ + +/* Bank 0 in IO space */ + +#define ETH_TCR (H2DBG_ETH_REG_BASE + 0x00) /* Transmit Control Register */ +#define ETH_EPH_STATUS (H2DBG_ETH_REG_BASE + 0x02) /* EPH Status Register */ +#define ETH_RCR (H2DBG_ETH_REG_BASE + 0x04) /* Receive Control Register */ +#define ETH_COUNTER (H2DBG_ETH_REG_BASE + 0x06) /* Counter Register */ +#define ETH_MIR (H2DBG_ETH_REG_BASE + 0x08) /* Memory Information Register */ +#define ETH_MCR (H2DBG_ETH_REG_BASE + 0x0A) /* Memory Configuration Register */ + +/* Bank 1 in IO space */ + +#define ETH_CONFIG (H2DBG_ETH_REG_BASE + 0x00) /* Configuration Register */ +#define ETH_BASE (H2DBG_ETH_REG_BASE + 0x02) /* Base Address Register */ +#define ETH_IA0 (H2DBG_ETH_REG_BASE + 0x04) /* Individual Address Register - 0 */ +#define ETH_IA1 (H2DBG_ETH_REG_BASE + 0x05) /* Individual Address Register - 1 */ +#define ETH_IA2 (H2DBG_ETH_REG_BASE + 0x06) /* Individual Address Register - 2 */ +#define ETH_IA3 (H2DBG_ETH_REG_BASE + 0x07) /* Individual Address Register - 3 */ +#define ETH_IA4 (H2DBG_ETH_REG_BASE + 0x08) /* Individual Address Register - 4 */ +#define ETH_IA5 (H2DBG_ETH_REG_BASE + 0x09) /* Individual Address Register - 5 */ +#define ETH_GEN_PURPOSE (H2DBG_ETH_REG_BASE + 0x0A) /* General Address Registers */ +#define ETH_CONTROL (H2DBG_ETH_REG_BASE + 0x0B) /* Control Register */ + +/* Bank 2 in IO space */ + +#define ETH_MMU (H2DBG_ETH_REG_BASE + 0x00) /* MMU Command Register */ +#define ETH_AUTO_TX_START (H2DBG_ETH_REG_BASE + 0x01) /* Auto Tx Start Register */ +#define ETH_PNR (H2DBG_ETH_REG_BASE + 0x02) /* Packet Number Register */ +#define ETH_ARR (H2DBG_ETH_REG_BASE + 0x03) /* Allocation Result Register */ +#define ETH_FIFO (H2DBG_ETH_REG_BASE + 0x04) /* FIFO Ports Register */ +#define ETH_POINTER (H2DBG_ETH_REG_BASE + 0x06) /* Pointer Register */ +#define ETH_DATA_HIGH (H2DBG_ETH_REG_BASE + 0x08) /* Data High Register */ +#define ETH_DATA_LOW (H2DBG_ETH_REG_BASE + 0x0A) /* Data Low Register */ +#define ETH_INT_STATS (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Status Register - RO */ +#define ETH_INT_ACK (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Acknowledge Register -WO */ +#define ETH_INT_MASK (H2DBG_ETH_REG_BASE + 0x0D) /* Interrupt Mask Register */ + + +#ifndef __ASSEMBLY__ + +/* + * A couple of utility inlines to aid debugging using the LED's on the + * debug board. + */ + +static inline void set_led_state(int state) +{ + static unsigned long hw_led_state = 0; + volatile unsigned short *led_address = (volatile unsigned short *)0x04000016; + + hw_led_state = ((unsigned long)state); + *((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF); +} + + +static inline void spin_up_leds(void) +{ + volatile int i, j, k; + + for (k = 0; k < 2; k++) { + for (i = 0; i < 16; i++) { + for (j = 0; j < 5000; j++) { + set_led_state(1 << i); + } + } + for (i = 15; i >= 0; i--) { + for (j = 0; j < 5000; j++) { + set_led_state(1 << i); + } + } + } +} + +#endif /* ! __ASSEMBLY__ */ + +#endif /* ! __INCLUDED_H2_P2_DBH_BOARD_H */ diff --git a/include/configs/hermes.h b/include/configs/hermes.h new file mode 100644 index 0000000..91117ba --- /dev/null +++ b/include/configs/hermes.h @@ -0,0 +1,339 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ +#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_COMMANDS CONFIG_CMD_DFL + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/*----------------------------------------------------------------------*/ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 /* Non-Standard value! */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFE000000 +#ifdef DEBUG +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + * +0x0004 + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * +0x0000 => 0x000000C0 + */ +#define CFG_SIUMCR 0 + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + * +0x0200 => 0x00C2 + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + * +0x0240 => 0x0082 + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit, set PLL multiplication factor ! + */ +/* +0x0286 => 0x00B0D0C0 */ +#define CFG_PLPRCR \ + ( (11 << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ + /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ + PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ + ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* +0x0282 => 0x03800000 */ +#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ + SCCR_RTDIV | SCCR_RTSEL | \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + SCCR_EBDF00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | \ + SCCR_DFNH000) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/* +0x0220 => 0x00C3 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +/* +0x09C4 => TIMEP=1 */ +#define CFG_RCCR 0x0100 + +/*----------------------------------------------------------------------- + * RMDS - RISC Microcode Development Support Control Register + *----------------------------------------------------------------------- + */ +#define CFG_RMDS 0 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ + +/* used to re-map FLASH + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +/* allow for max 4 MB of Flash */ +#define CFG_REMAP_OR_AM 0xFFC00000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ + +/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \ + OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +/* 8 bit, bank valid */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR1/OR1 - SDRAM + * + * Multiplexed addresses, GPL5 output to GPL5_A (don't care) + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ +#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ + +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ + +#define CFG_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide + */ +#define HPRO2_BASE 0xE0000000 +#define HPRO2_OR_AM 0xFFFF8000 +#define HPRO2_TIMING 0x00000934 + +#define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING) +#define CFG_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR3/OR3: not used + * BR4/OR4: not used + * BR5/OR5: not used + * BR6/OR6: not used + * BR7/OR7: not used + */ + +/* + * MAMR settings for SDRAM + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h new file mode 100644 index 0000000..cfaf153 --- /dev/null +++ b/include/configs/hmi1001.h @@ -0,0 +1,348 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_HMI1001 1 /* HMI1001 board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* Partitions */ +#define CONFIG_DOS_PARTITION + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ + +#if (TEXT_BASE == 0xFFF00000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#define CONFIG_MISC_INIT_R 1 + +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFF800000 + +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ + +#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_CFI_AMD_RESET + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 +#define CFG_DISPLAY_BASE 0x80600000 +#define CFG_STATUS1_BASE 0x80600200 +#define CFG_STATUS2_BASE 0x80600300 + +/* Settings for XLB = 132 MHz */ +#define SDRAM_DDR 1 +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x01051004 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Enable an alternate, more extensive memory test */ +#define CFG_ALT_MEMTEST + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x0004FB00 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* 8Mbit SRAM @0x80100000 */ +#define CFG_CS1_START 0x80100000 +#define CFG_CS1_SIZE 0x00100000 +#define CFG_CS1_CFG 0x19B00 + +/* FRAM 32Kbyte @0x80700000 */ +#define CFG_CS2_START 0x80700000 +#define CFG_CS2_SIZE 0x00008000 +#define CFG_CS2_CFG 0x19800 + +/* Display H1, Status Inputs, EPLD @0x80600000 */ +#define CFG_CS3_START 0x80600000 +#define CFG_CS3_SIZE 0x00100000 +#define CFG_CS3_CFG 0x00019800 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ + +#define CONFIG_IDE_PREINIT 1 + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#define CONFIG_ATAPI 1 + +#define CONFIG_VIDEO_SMI_LYNXEM +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CFG_ISA_IO CONFIG_PCI_IO_BUS + +/*---------------------------------------------------------------------*/ +/* Display addresses */ +/*---------------------------------------------------------------------*/ + +#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38) +#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30) + +#endif /* __CONFIG_H */ diff --git a/include/configs/hymod.h b/include/configs/hymod.h new file mode 100644 index 0000000..8cad98d --- /dev/null +++ b/include/configs/hymod.h @@ -0,0 +1,733 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Config header file for Hymod board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_HYMOD 1 /* ...on a Hymod board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ + +#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ +#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ +#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ +#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ + +#ifdef CONFIG_ETHER_ON_FCC + +#if (CONFIG_ETHER_INDEX == 1) + +/* + * - Rx-CLK is CLK10 + * - Tx-CLK is CLK11 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +# define MDIO_PORT 0 /* Port A */ +# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ +# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ + +#elif (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +# define MDIO_PORT 0 /* Port A */ +# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ +# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ + +#elif (CONFIG_ETHER_INDEX == 3) + +/* + * - Rx-CLK is CLK15 + * - Tx-CLK is CLK16 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +# define MDIO_PORT 0 /* Port A */ +# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ +# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ + +#endif /* CONFIG_ETHER_INDEX */ + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ + +#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) +#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) +#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ + else iop->pdat &= ~MDIO_DATA_PINMASK + +#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ + else iop->pdat &= ~MDIO_CLCK_PINMASK + +#define MIIDELAY udelay(1) + +#endif /* CONFIG_ETHER_ON_FCC */ + + +/* other options */ +#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ +#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#ifdef DEBUG +#define CONFIG_8260_CLKIN 33333333 /* in Hz */ +#else +#define CONFIG_8260_CLKIN 66666666 /* in Hz */ +#endif + +#if defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 115200 +#else +#define CONFIG_BAUDRATE 9600 +#endif + +/* default ip addresses - these will be overridden */ +#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ +#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ + +#define CONFIG_LAST_STAGE_INIT + +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_FPGA | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NAND | \ + CFG_CMD_MMC | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_PCI | \ + CFG_CMD_USB | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_UNIVERSE| \ + CFG_CMD_VFD | \ + CFG_CMD_XIMG ) ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#ifdef DEBUG +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ +#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ +/* Be selective on what keys can delay or stop the autoboot process + * To stop use: " " + */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ + "press to stop\n" +#define CONFIG_AUTOBOOT_STOP_STR " " +#undef CONFIG_AUTOBOOT_DELAY_STR +#define DEBUG_BOOTKEYS 0 +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ +#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ +#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ +#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ +# if defined(CONFIG_KGDB_USE_EXTC) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +# else +#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ +# endif +#endif + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ + +/* + * Hymod specific configurable options + */ +#undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ + +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0x7e + +/* these are for the ST M24C02 2kbit serial i2c eeprom */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 + +#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CFG_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ + +#define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ + +/* + * standard dtt sensor configuration - bottom bit will determine local or + * remote sensor of the ADM1021, the rest determines index into + * CFG_DTT_ADM1021 array below. + * + * On HYMOD board, the remote sensor should be connected to the MPC8260 + * temperature diode thingy, but an errata said this didn't work and + * should be disabled - so it isn't connected. + */ +#if 0 +#define CONFIG_DTT_SENSORS { 0, 1 } +#else +#define CONFIG_DTT_SENSORS { 0 } +#endif + +/* + * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). + * there will be one entry in this array for each two (dummy) sensors in + * CONFIG_DTT_SENSORS. + * + * For HYMOD board: + * - only one ADM1021 + * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) + * - conversion rate 0x02 = 0.25 conversions/second + * - ALERT ouput disabled + * - local temp sensor enabled, min set to 0 deg, max set to 85 deg + * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) + */ +#define CFG_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#ifdef DEBUG +#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ + HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ + HRCW_MODCK_H0010) +#else +#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ + HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ + HRCW_MODCK_H0101) +#endif +/* no slaves so just duplicate the master hrcw */ +#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER +#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE TEXT_BASE +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_FPGA_BASE 0x80000000 +/* + * unfortunately, CFG_MONITOR_LEN must include the + * (very large i.e. 256kB) environment flash sector + */ +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ + HID0_IFEM|HID0_ABE) +#ifdef DEBUG +#define CFG_HID0_FINAL 0 +#else +#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) +#endif +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#ifdef DEBUG +#define CFG_RMR 0 +#else +#define CFG_RMR RMR_CSRE +#endif + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR (BCR_ETM) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ + SIUMCR_APPC10|SIUMCR_MMR11) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR (SCCR_DFBRG01) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 32 bit FLASH + * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) + * 2 60x SDRAM 64 bit SDRAM + * 3 Local UPMC 8 bit Main Xilinx configuration + * 4 Local GPCM 32 bit Main Xilinx register mode + * 5 Local UPMB 32 bit Main Xilinx port mode + * 6 Local UPMC 8 bit Mezz Xilinx configuration + */ + +/* + * Bank 0 - FLASH + * + * Quotes from the HYMOD IO Board Reference manual: + * + * "The flash memory is two Intel StrataFlash chips, each configured for + * 16 bit operation and connected to give a 32 bit wide port." + * + * "The chip select logic is configured to respond to both *CS0 and *CS1. + * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. + * It is suggested that bank 0 be read-only and bank 1 be read/write. The + * FLASH will then appear as ROM during boot." + * + * Initially, we are only going to use bank 0 in read/write mode. + */ + +/* 32 bit, read-write, GPCM on 60x bus */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\ + BRx_PS_32|BRx_MS_GPCM_P|BRx_V) +/* up to 32 Mb */ +#define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) + +/* + * Bank 2 - SDRAM + * + * Quotes from the HYMOD IO Board Reference manual: + * + * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a + * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous + * dynamic random access memory organised as 4 banks by 4096 rows by 512 + * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." + * + * "The locations in SDRAM are accessed using multiplexed address pins to + * specify row and column. The pins also act to specify commands. The state + * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP + * pin may function as a row address or as the AUTO PRECHARGE control line, + * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 + * address lines to be configured to the required multiplexing scheme." + */ + +#define CFG_SDRAM_SIZE 64 + +/* 64 bit, read-write, SDRAM on 60x bus */ +#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\ + BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) +/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\ + ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) + +/* + * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: + * + * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 + * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 + * as bank select, A7 is output on SDA10 during an ACTIVATE command, + * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, + * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE + * command is 2 clocks, earliest timing for PRECHARGE after last data + * was read is 1 clock, earliest timing for PRECHARGE after last data + * was written is 1 clock, CAS Latency is 2. + */ + +#define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ + PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ + PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ + PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ + PSDMR_WRC_1C|PSDMR_CL_2) + +/* + * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh + * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register + * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer + * Prescaler, hence the P instead of the R). The refresh timer period is given + * by (note that there was a change in the 8260 UM Errata): + * + * TimerPeriod = (PSRT + 1) / Fmptc + * + * where Fmptc is the BusClock divided by PTP. i.e. + * + * TimerPeriod = (PSRT + 1) / (BusClock / PTP) + * + * or + * + * TImerPeriod = (PTP * (PSRT + 1)) / BusClock + * + * The requirement for the Toshiba TC59SM716FTL-10 is that there must be + * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 + * = 15.625 usecs. + * + * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 + * appear to be reasonable. + */ + +#ifdef DEBUG +#define CFG_PSRT 39 +#define CFG_MPTPR MPTPR_PTP_DIV8 +#else +#define CFG_PSRT 31 +#define CFG_MPTPR MPTPR_PTP_DIV32 +#endif + +/* + * Banks 3,4,5 and 6 - FPGA access + * + * Quotes from the HYMOD IO Board Reference manual: + * + * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made + * for configuring an optional FPGA on the mezzanine interface. + * + * Access to the FPGAs may be divided into several catagories: + * + * 1. Configuration + * 2. Register mode access + * 3. Port mode access + * + * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be + * configured only (mode 1). Consequently there are four access types. + * + * To improve interface performance and simplify software design, the four + * possible access types are separately mapped to different memory banks. + * + * All are accessed using the local bus." + * + * Device Mode Memory Bank Machine Port Size Access + * + * Main Configuration 3 UPMC 8bit R/W + * Main Register 4 GPCM 32bit R/W + * Main Port 5 UPMB 32bit R/W + * Mezzanine Configuration 6 UPMC 8bit W/O + * + * "Note that mezzanine mode 1 access is write-only." + */ + +/* all the bank sizes must be a power of two, greater or equal to 32768 */ +#define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE) +#define FPGA_MAIN_CFG_SIZE 32768 +#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) +#define FPGA_MAIN_REG_SIZE 32768 +#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) +#define FPGA_MAIN_PORT_SIZE 32768 +#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) +#define FPGA_MEZZ_CFG_SIZE 32768 + +/* 8 bit, read-write, UPMC */ +#define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) +/* up to 32Kbyte, burst inhibit */ +#define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) + +/* 32 bit, read-write, GPCM */ +#define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) +/* up to 32Kbyte */ +#define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) + +/* 32 bit, read-write, UPMB */ +#define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) +/* up to 32Kbyte */ +#define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) + +/* 8 bit, write-only, UPMC */ +#define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) +/* up to 32Kbyte, burst inhibit */ +#define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) + +/*----------------------------------------------------------------------- + * MBMR - Machine B Mode 10-27 + *----------------------------------------------------------------------- + */ +#define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ + +/*----------------------------------------------------------------------- + * MCMR - Machine C Mode 10-27 + *----------------------------------------------------------------------- + */ +#define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ + +/* + * FPGA I/O Port/Bit information + */ + +#define FPGA_MAIN_PROG_PORT IOPIN_PORTA +#define FPGA_MAIN_PROG_PIN 4 /* PA4 */ +#define FPGA_MAIN_INIT_PORT IOPIN_PORTA +#define FPGA_MAIN_INIT_PIN 5 /* PA5 */ +#define FPGA_MAIN_DONE_PORT IOPIN_PORTA +#define FPGA_MAIN_DONE_PIN 6 /* PA6 */ + +#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA +#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ +#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA +#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ +#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA +#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ +#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA +#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ + +/* + * FPGA Interrupt configuration + */ +#define FPGA_MAIN_IRQ SIU_INT_IRQ2 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "" +#define MTDPARTS_DEFAULT "" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/impa7.h b/include/configs/impa7.h new file mode 100644 index 0000000..8b841ff --- /dev/null +++ b/include/configs/impa7.h @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the implementa impA7 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_IMPA7 1 /* on an impA7 Board */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x20000000 +#define CS8900_BUS32 1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" +/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5a */ +/*#define CONFIG_NETMASK 255.255.0.0 */ +/*#define CONFIG_IPADDR 172.22.2.128 */ +/*#define CONFIG_SERVERIP 172.22.2.126 */ +/*#define CONFIG_BOOTFILE "impa7" */ +#define CONFIG_BOOTCOMMAND "bootp;bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "impA7 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xc1000000 /* default load address */ + +#define CFG_HZ 2000 /* decrementer freq: 2 kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ +#define PHYS_SDRAM_2 0xc1000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x10000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x00800000 /* 16 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00020000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=impA7 NOR Flash Bank #0,nor1=impA7 NOR Flash Bank #1" +#define MTDPARTS_DEFAULT "mtdparts=impA7 NOR Flash Bank #0:-(FileSystem1);impA7 NOR Flash Bank #1:-(FileSystem2)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h new file mode 100644 index 0000000..1c6216b --- /dev/null +++ b/include/configs/incaip.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for the INCA-IP board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ +#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */ + +#ifndef CPU_CLOCK_RATE +/* allowed values: 100000000, 133000000, and 150000000 */ +#define CPU_CLOCK_RATE 150000000 /* default: 150 MHz clock for the MIPS core */ +#endif + +#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BAUDRATE 115200 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "ethaddr=${ethaddr} " \ + "panic=1\0" \ + "flash_nfs=run nfsargs addip addmisc;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 80500000 ${bootfile};" \ + "run nfsargs addip addmisc;bootm\0" \ + "rootpath=/opt/eldk/mips_4KC\0" \ + "bootfile=/tftpboot/INCA/uImage\0" \ + "kernel_addr=B0040000\0" \ + "ramdisk_addr=B0100000\0" \ + "u-boot=/tftpboot/INCA/u-boot.bin\0" \ + "load=tftp 80500000 ${u-boot}\0" \ + "update=protect off 1:0-2;era 1:0-2;" \ + "cp.b 80500000 B0000000 ${filesize}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_SNTP ) +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "INCA-IP # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ + +#define CFG_MALLOC_LEN 128*1024 + +#define CFG_BOOTPARAMS_LEN 128*1024 + +#define CFG_HZ (incaip_get_cpuclk() / 2) + +#define CFG_SDRAM_BASE 0x80000000 + +#define CFG_LOAD_ADDR 0x80100000 /* default load address */ + +#define CFG_MEMTEST_START 0x80100000 +#define CFG_MEMTEST_END 0x80800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ + +#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */ + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +#define CFG_INIT_SP_OFFSET 0x400000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR 0xB0030000 +#define CFG_ENV_SIZE 0x10000 + +#define CONFIG_FLASH_16BIT + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_INCA_IP_SWITCH +#define CONFIG_NET_MULTI +#define CONFIG_INCA_IP_SWITCH_AMDIX + +/* + * JFFS2 partitions + */ +/* No command line, one static partition, use all space on the device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor1" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=INCA-IP Bank 0" +#define MTDPARTS_DEFAULT "mtdparts=INCA-IP Bank 0:192k(uboot)," \ + "64k(env)," \ + "768k(linux)," \ + "1m@3m(rootfs)," \ + "768k(linux2)," \ + "3m@5m(rootfs2)" +*/ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 4096 +#define CFG_ICACHE_SIZE 4096 +#define CFG_CACHELINE_SIZE 16 + +#endif /* __CONFIG_H */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h new file mode 100644 index 0000000..c0cc4f1 --- /dev/null +++ b/include/configs/inka4x0.h @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_INKA4X0 1 /* INKA4x0 board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CFG_XLB_PIPELINING 1 + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP | \ + CFG_CMD_USB ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ + +#if (TEXT_BASE == 0xFFE00000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFFE00000 + +#define CFG_FLASH_SIZE 0x00200000 /* 2 MByte */ +#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */ + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) /* second sector */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +#define CONFIG_MPC5200_DDR + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + * + * use CS1 as gpio_wkup_6 output + * Bit 0 (mask: 0x80000000): 0 + * use ALT CAN position: Bits 2-3 (mask: 0x30000000): + * 00 -> No Alternatives, I2C1 is used for onboard EEPROM + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard + * EEPROM + * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 + * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000): + * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible. + */ +#define CFG_GPS_PORT_CONFIG 0x01001004 + +/* + * RTC configuration + */ +#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Enable an alternate, more extensive memory test */ +#define CFG_ALT_MEMTEST + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */ +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* 32Mbit SRAM @0x30000000 */ +#define CFG_CS1_START 0x30000000 +#define CFG_CS1_SIZE 0x00400000 +#define CFG_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */ + +/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ +#define CFG_CS2_START 0x80000000 +#define CFG_CS2_SIZE 0x0001000 +#define CFG_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */ + +/* GPIO in @0x30400000 */ +#define CFG_CS3_START 0x30400000 +#define CFG_CS3_SIZE 0x00100000 +#define CFG_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */ + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_CLOCK 0x00015555 +#define CONFIG_USB_CONFIG 0x00001000 +#define CONFIG_USB_STORAGE + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA +#define CFG_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 4 /* Interval between registers */ + +#define CONFIG_ATAPI 1 + +#define CFG_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h new file mode 100644 index 0000000..3cb9ebc --- /dev/null +++ b/include/configs/innokom.h @@ -0,0 +1,468 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. + * + * Configuration for the Auerswald Innokom CPU board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * include/configs/innokom.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + /* for timer/console/ethernet */ +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 19200 +#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ + +#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE) +/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ +#define CONFIG_BOOTARGS "console=ttyS0,19200" +#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.1.56 +#define CONFIG_SERVERIP 192.168.1.2 +#define CONFIG_BOOTCOMMAND "bootm 0x40000" +#define CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_CMDLINE_TAG 1 + +/* + * Miscellaneous configurable options + */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (256*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa3000000 /* load kernel to this address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ + /* RS: the oscillator is actually 3680130?? */ + +#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ + /* 0101000001 */ + /* ^^^^^ Memory Speed 99.53 MHz */ + /* ^^ Run Mode Speed = 2x Mem Speed */ + /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ + +#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * I2C bus + */ +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xfe + +#define CFG_ENV_IS_IN_EEPROM 1 + +#define CFG_ENV_OFFSET 0x00 /* environment starts here */ +#define CFG_ENV_SIZE 1024 /* 1 KiB */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */ +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */ +#define CFG_EEPROM_SIZE 4096 /* size in bytes */ +#define CFG_I2C_INIT_BOARD 1 /* board has it's own init */ + +/* + * SMSC91C111 Network Card + */ +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */ +#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ +#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ +#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */ +#undef CONFIG_SHOW_ACTIVITY +#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ + +#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */ +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * JFFS2 partitions + * + */ +/* development flash */ +#define CONFIG_MTD_INNOKOM_16MB 1 +#undef CONFIG_MTD_INNOKOM_64MB + +/* production flash */ +/* +#define CONFIG_MTD_INNOKOM_64MB 1 +#undef CONFIG_MTD_INNOKOM_16MB +*/ + +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=innokom-0" +*/ + +/* development flash */ +/* +#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)" +*/ + +/* production flash */ +/* +#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)" +*/ + +/* + * GPIO settings + * + * GP15 == nCS1 is 1 + * GP24 == SFRM is 1 + * GP25 == TXD is 1 + * GP33 == nCS5 is 1 + * GP39 == FFTXD is 1 + * GP41 == RTS is 1 + * GP47 == TXD is 1 + * GP49 == nPWE is 1 + * GP62 == LED_B is 1 + * GP63 == TDM_OE is 1 + * GP78 == nCS2 is 1 + * GP79 == nCS3 is 1 + * GP80 == nCS4 is 1 + */ +#define CFG_GPSR0_VAL 0x03008000 +#define CFG_GPSR1_VAL 0xC0028282 +#define CFG_GPSR2_VAL 0x0001C000 + +/* GP02 == DON_RST is 0 + * GP23 == SCLK is 0 + * GP45 == USB_ACT is 0 + * GP60 == PLLEN is 0 + * GP61 == LED_A is 0 + * GP73 == SWUPD_LED is 0 + */ +#define CFG_GPCR0_VAL 0x00800004 +#define CFG_GPCR1_VAL 0x30002000 +#define CFG_GPCR2_VAL 0x00000100 + +/* GP00 == DON_READY is input + * GP01 == DON_OK is input + * GP02 == DON_RST is output + * GP03 == RESET_IND is input + * GP07 == RES11 is input + * GP09 == RES12 is input + * GP11 == SWUPDATE is input + * GP14 == nPOWEROK is input + * GP15 == nCS1 is output + * GP17 == RES22 is input + * GP18 == RDY is input + * GP23 == SCLK is output + * GP24 == SFRM is output + * GP25 == TXD is output + * GP26 == RXD is input + * GP32 == RES21 is input + * GP33 == nCS5 is output + * GP34 == FFRXD is input + * GP35 == CTS is input + * GP39 == FFTXD is output + * GP41 == RTS is output + * GP42 == USB_OK is input + * GP45 == USB_ACT is output + * GP46 == RXD is input + * GP47 == TXD is output + * GP49 == nPWE is output + * GP58 == nCPUBUSINT is input + * GP59 == LANINT is input + * GP60 == PLLEN is output + * GP61 == LED_A is output + * GP62 == LED_B is output + * GP63 == TDM_OE is output + * GP64 == nDSPINT is input + * GP65 == STRAP0 is input + * GP67 == STRAP1 is input + * GP69 == STRAP2 is input + * GP70 == STRAP3 is input + * GP71 == STRAP4 is input + * GP73 == SWUPD_LED is output + * GP78 == nCS2 is output + * GP79 == nCS3 is output + * GP80 == nCS4 is output + */ +#define CFG_GPDR0_VAL 0x03808004 +#define CFG_GPDR1_VAL 0xF002A282 +#define CFG_GPDR2_VAL 0x0001C200 + +/* GP15 == nCS1 is AF10 + * GP18 == RDY is AF01 + * GP23 == SCLK is AF10 + * GP24 == SFRM is AF10 + * GP25 == TXD is AF10 + * GP26 == RXD is AF01 + * GP33 == nCS5 is AF10 + * GP34 == FFRXD is AF01 + * GP35 == CTS is AF01 + * GP39 == FFTXD is AF10 + * GP41 == RTS is AF10 + * GP46 == RXD is AF10 + * GP47 == TXD is AF01 + * GP49 == nPWE is AF10 + * GP78 == nCS2 is AF10 + * GP79 == nCS3 is AF10 + * GP80 == nCS4 is AF10 + */ +#define CFG_GAFR0_L_VAL 0x80000000 +#define CFG_GAFR0_U_VAL 0x001A8010 +#define CFG_GAFR1_L_VAL 0x60088058 +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x00000002 + + +/* FIXME: set GPIO_RER/FER */ + +/* RDH = 1 + * PH = 1 + * VFS = 1 + * BFS = 1 + * SSS = 1 + */ +#define CFG_PSSR_VAL 0x37 + +/* + * Memory settings + * + * This is the configuration for nCS0/1 -> flash banks + * configuration for nCS1: + * [31] 0 - Slower Device + * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns + * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns + * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [19] 1 - 16 Bit bus width + * [18:16] 000 - nonburst RAM or FLASH + * configuration for nCS0: + * [15] 0 - Slower Device + * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns + * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns + * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [03] 1 - 16 Bit bus width + * [02:00] 000 - nonburst RAM or FLASH + */ +#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */ + +/* This is the configuration for nCS2/3 -> TDM-Switch, DSP + * configuration for nCS3: DSP + * [31] 0 - Slower Device + * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns + * [19] 1 - 16 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS2: TDM-Switch + * [15] 0 - Slower Device + * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns + * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns + * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */ + +/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller + * + * configuration for nCS5: LAN Controller + * [31] 0 - Slower Device + * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns + * [19] 1 - 16 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS4: ExtBus + * [15] 0 - Slower Device + * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns + * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns + * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ + +/* MDCNFG: SDRAM Configuration Register + * + * [31:29] 000 - reserved + * [28] 0 - no SA1111 compatiblity mode + * [27] 0 - latch return data with return clock + * [26] 0 - alternate addressing for pair 2/3 + * [25:24] 00 - timings + * [23] 0 - internal banks in lower partition 2/3 (not used) + * [22:21] 00 - row address bits for partition 2/3 (not used) + * [20:19] 00 - column address bits for partition 2/3 (not used) + * [18] 0 - SDRAM partition 2/3 width is 32 bit + * [17] 0 - SDRAM partition 3 disabled + * [16] 0 - SDRAM partition 2 disabled + * [15:13] 000 - reserved + * [12] 1 - SA1111 compatiblity mode + * [11] 1 - latch return data with return clock + * [10] 0 - no alternate addressing for pair 0/1 + * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk + * [7] 1 - 4 internal banks in lower partition pair + * [06:05] 10 - 13 row address bits for partition 0/1 + * [04:03] 01 - 9 column address bits for partition 0/1 + * [02] 0 - SDRAM partition 0/1 width is 32 bit + * [01] 0 - disable SDRAM partition 1 + * [00] 1 - enable SDRAM partition 0 + */ +/* use the configuration above but disable partition 0 */ +#define CFG_MDCNFG_VAL 0x000019c8 + +/* MDREFR: SDRAM Refresh Control Register + * + * [32:26] 0 - reserved + * [25] 0 - K2FREE: not free running + * [24] 0 - K1FREE: not free running + * [23] 1 - K0FREE: not free running + * [22] 0 - SLFRSH: self refresh disabled + * [21] 0 - reserved + * [20] 0 - APD: no auto power down + * [19] 0 - K2DB2: SDCLK2 is MemClk + * [18] 0 - K2RUN: disable SDCLK2 + * [17] 0 - K1DB2: SDCLK1 is MemClk + * [16] 1 - K1RUN: enable SDCLK1 + * [15] 1 - E1PIN: SDRAM clock enable + * [14] 1 - K0DB2: SDCLK0 is MemClk + * [13] 0 - K0RUN: disable SDCLK0 + * [12] 1 - E0PIN: disable SDCKE0 + * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 + */ +#define CFG_MDREFR_VAL 0x0081D018 + +/* MDMRS: Mode Register Set Configuration Register + * + * [31] 0 - reserved + * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) + * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) + * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) + * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) + * [15] 0 - reserved + * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. + * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. + * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. + * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. + */ +#define CFG_MDMRS_VAL 0x00020022 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00000000 +#define CFG_MCMEM1_VAL 0x00000000 +#define CFG_MCATT0_VAL 0x00000000 +#define CFG_MCATT1_VAL 0x00000000 +#define CFG_MCIO0_VAL 0x00000000 +#define CFG_MCIO1_VAL 0x00000000 + +/* +#define CSB226_USER_LED0 0x00000008 +#define CSB226_USER_LED1 0x00000010 +#define CSB226_USER_LED2 0x00000020 +*/ + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h new file mode 100644 index 0000000..2f6e399 --- /dev/null +++ b/include/configs/integratorap.h @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP Innovator board. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * Configuration for Integrator AP board. + *. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +/* + * High Level Configuration Options + * (easy to change) + */ +#define CFG_MEMTEST_START 0x100000 +#define CFG_MEMTEST_END 0x10000000 +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ +#define CFG_TIMERBASE 0x13000100 /* Timer1 */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ + +#undef CONFIG_INIT_CRITICAL +#define CONFIG_CM_INIT 1 +#define CONFIG_CM_REMAP 1 +#undef CONFIG_CM_SPD_DETECT + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * PL010 Configuration + */ +#define CFG_PL010_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 38400 +#define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SERIAL0 0x16000000 +#define CFG_SERIAL1 0x17000000 + +/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */ +/*#define CONFIG_NET_MULTI */ +/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ + +#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" +#define CONFIG_BOOTCOMMAND "" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define CFG_FLASH_BASE 0x24000000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_ENV_IS_NOWHERE +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ +#define CFG_MAX_FLASH_SECT 128 +#define CFG_ENV_SIZE 32768 + +#define PHYS_FLASH_1 (CFG_FLASH_BASE) + +/*----------------------------------------------------------------------- + * PCI definitions + */ + +/*#define CONFIG_PCI /--* include pci support */ +#undef CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define DEBUG + +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + + +#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 +#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 + +/* PCI Base area */ +#define INTEGRATOR_PCI_BASE 0x40000000 +#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF + +/* memory map as seen by the CPU on the local bus */ +#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ +#define CPU_PCI_IO_SIZE 0x10000 + +#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ +#define CPU_PCI_CNFG_SIZE 0x1000000 + +#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ +/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ +#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ +/* unused (128-16)M from B1000000-B7FFFFFF */ +#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ +/* unused ((128-16)M - 64K) from XXX */ + +#define PCI_V3_BASE 0x62000000 + +/* V3 PCI bridge controller */ +#define V3_BASE 0x62000000 /* V360EPC registers */ + +#define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS) +#define PCI_ENET0_MEMADDR (PCI_MEM_BASE) + + +#define V3_PCI_VENDOR 0x00000000 +#define V3_PCI_DEVICE 0x00000002 +#define V3_PCI_CMD 0x00000004 +#define V3_PCI_STAT 0x00000006 +#define V3_PCI_CC_REV 0x00000008 +#define V3_PCI_HDR_CF 0x0000000C +#define V3_PCI_IO_BASE 0x00000010 +#define V3_PCI_BASE0 0x00000014 +#define V3_PCI_BASE1 0x00000018 +#define V3_PCI_SUB_VENDOR 0x0000002C +#define V3_PCI_SUB_ID 0x0000002E +#define V3_PCI_ROM 0x00000030 +#define V3_PCI_BPARAM 0x0000003C +#define V3_PCI_MAP0 0x00000040 +#define V3_PCI_MAP1 0x00000044 +#define V3_PCI_INT_STAT 0x00000048 +#define V3_PCI_INT_CFG 0x0000004C +#define V3_LB_BASE0 0x00000054 +#define V3_LB_BASE1 0x00000058 +#define V3_LB_MAP0 0x0000005E +#define V3_LB_MAP1 0x00000062 +#define V3_LB_BASE2 0x00000064 +#define V3_LB_MAP2 0x00000066 +#define V3_LB_SIZE 0x00000068 +#define V3_LB_IO_BASE 0x0000006E +#define V3_FIFO_CFG 0x00000070 +#define V3_FIFO_PRIORITY 0x00000072 +#define V3_FIFO_STAT 0x00000074 +#define V3_LB_ISTAT 0x00000076 +#define V3_LB_IMASK 0x00000077 +#define V3_SYSTEM 0x00000078 +#define V3_LB_CFG 0x0000007A +#define V3_PCI_CFG 0x0000007C +#define V3_DMA_PCI_ADR0 0x00000080 +#define V3_DMA_PCI_ADR1 0x00000090 +#define V3_DMA_LOCAL_ADR0 0x00000084 +#define V3_DMA_LOCAL_ADR1 0x00000094 +#define V3_DMA_LENGTH0 0x00000088 +#define V3_DMA_LENGTH1 0x00000098 +#define V3_DMA_CSR0 0x0000008B +#define V3_DMA_CSR1 0x0000009B +#define V3_DMA_CTLB_ADR0 0x0000008C +#define V3_DMA_CTLB_ADR1 0x0000009C +#define V3_DMA_DELAY 0x000000E0 +#define V3_MAIL_DATA 0x000000C0 +#define V3_PCI_MAIL_IEWR 0x000000D0 +#define V3_PCI_MAIL_IERD 0x000000D2 +#define V3_LB_MAIL_IEWR 0x000000D4 +#define V3_LB_MAIL_IERD 0x000000D6 +#define V3_MAIL_WR_STAT 0x000000D8 +#define V3_MAIL_RD_STAT 0x000000DA +#define V3_QBA_MAP 0x000000DC + +/* SYSTEM register bits */ +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) + +/* PCI_CFG bits */ +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) + +/* PCI MAP register bits (PCI -> Local bus) */ +#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) +#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) +#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) + +/* 9 => 512M window size */ +#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 + +/* A => 1024M window size */ +#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 + +/* LB_BASE register bits (Local bus -> PCI) */ +#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 +#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) +#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 +#define V3_LB_BASE_M_PREFETCH (1 << 3) +#define V3_LB_BASE_M_ENABLE (1 << 0) + +/* PCI COMMAND REGISTER bits */ +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) + +#define INTEGRATOR_SC_BASE 0x11000000 +#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 +#define INTEGRATOR_SC_PCIENABLE \ + (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) + +/*----------------------------------------------------------------------- + * There are various dependencies on the core module (CM) fitted + * Users should refer to their CM user guide + * - when porting adjust u-boot/Makefile accordingly + * to define the necessary CONFIG_ s for the CM involved + * see e.g. integratorcp_CM926EJ-S_config + */ +#include "armcoremodule.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h new file mode 100644 index 0000000..4189f9c --- /dev/null +++ b/include/configs/integratorcp.h @@ -0,0 +1,243 @@ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP Innovator board. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * Configuration for Compact Integrator board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CFG_MEMTEST_START 0x100000 +#define CFG_MEMTEST_END 0x10000000 +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ +#define CFG_TIMERBASE 0x13000100 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC_USE_32_BIT +#define CONFIG_SMC91111_BASE 0xC8000000 +#undef CONFIG_SMC91111_EXT_PHY + +/* + * NS16550 Configuration + */ +#define CFG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 14745600 +#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 38400 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SERIAL0 0x16000000 +#define CFG_SERIAL1 0x17000000 + +/* +#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_PCI) +*/ +#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \ + CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \ + ) + +/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if 0 +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=:/ mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" +#define CONFIG_BOOTCOMMAND "bootp ; bootm" +#endif +/* The kernel command line & boot command below are for a platform flashed with afu.axf + +Image 666 Block 0 End Block 0 address 0x24000000 exec 0x24000000- name u-boot +Image 667 Block 1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux +Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs +SIB at Block62 End Block62 address 0x24f80000 + +*/ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0" +#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + + * Top varies according to amount fitted + * Reserve top 4 blocks of flash + * - ARM Boot Monitor + * - Unused + * - SIB block + * - U-Boot environment + * + * Base is always 0x24000000 + + */ +#define CFG_FLASH_BASE 0x24000000 +#define CFG_MAX_FLASH_SECT 64 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_MONITOR_LEN 0x00100000 +#define CFG_ENV_IS_IN_FLASH (1) + +/* + * Move up the U-Boot & monitor area if more flash is fitted. + * If this U-Boot is to be run on Integrators with varying flash sizes, + * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG + * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE + * - CFG_MONITOR_BASE is set to indicate that the environment is not + * embedded in the boot monitor(s) area + */ +#if ( PHYS_FLASH_SIZE == 0x04000000 ) + +#define CFG_ENV_ADDR 0x27F00000 +#define CFG_MONITOR_BASE 0x27F40000 + +#elif (PHYS_FLASH_SIZE == 0x02000000 ) + +#define CFG_ENV_ADDR 0x25F00000 +#define CFG_MONITOR_BASE 0x25F40000 + +#else + +#define CFG_ENV_ADDR 0x24F00000 +#define CFG_MONITOR_BASE 0x27F40000 + +#endif + +#define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#define CFG_ENV_SIZE 8192 /* 8KB */ +/*----------------------------------------------------------------------- + * CP control registers + */ +#define CPCR_BASE 0xCB000000 /* CP Registers*/ +#define OS_FLASHPROG 0x00000004 /* Flash register*/ +#define CPMASK_EXTRABANK 0x8 +#define CPMASK_FLASHSIZE 0x4 +#define CPMASK_FLWREN 0x2 +#define CPMASK_FLVPPEN 0x1 + +/* + * The ARM boot monitor initializes the board. + * However, the default U-Boot code also performs the initialization. + * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT + * - see documentation supplied with board for details of how to choose the + * image to run at reset/power up + * e.g. whether the ARM Boot Monitor runs before U-Boot + +#define CONFIG_SKIP_LOWLEVEL_INIT + + */ + +/* + * The ARM boot monitor does not relocate U-Boot. + * However, the default U-Boot code performs the relocation check, + * and may relocate the code if the memory map is changed. + * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT + +#define SKIP_CONFIG_RELOCATE_UBOOT + + */ +/*----------------------------------------------------------------------- + * There are various dependencies on the core module (CM) fitted + * Users should refer to their CM user guide + * - when porting adjust u-boot/Makefile accordingly + * to define the necessary CONFIG_ s for the CM involved + * see e.g. cp_926ejs_config + */ + +#include "armcoremodule.h" + +/* + * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & + * the core module has a CM_INIT register + * then the U-Boot initialisation code will + * e.g. ARM Boot Monitor or pre-loader is repeated once + * (to re-initialise any existing CM_INIT settings to safe values). + * + * This is usually not the desired behaviour since the platform + * will either reboot into the ARM monitor (or pre-loader) + * or continuously cycle thru it without U-Boot running, + * depending upon the setting of Integrator/CP switch S2-4. + * + * However it may be needed if Integrator/CP switch S2-1 + * is set OFF to boot direct into U-Boot. + * In that case comment out the line below. +#undef CONFIG_CM_INIT + */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h new file mode 100644 index 0000000..b0a80a3 --- /dev/null +++ b/include/configs/ixdp425.h @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2003 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * Configuation settings for the IXDP425 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ +#define CONFIG_IXDP425 1 /* on an IXDP425 Board */ + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI) + +#define CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_EEPRO100 +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +/* These are u-boot generic parameters */ +#include + +#define CONFIG_BOOTDELAY 3 +/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.21 +#define CONFIG_SERVERIP 192.168.0.148 +#define CONFIG_BOOTCOMMAND "bootm 50040000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00010000 /* default load address */ + +#define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*************************************************************** + * Platform/Board specific defines start here. + ***************************************************************/ + +/* + * Hardware drivers + */ + + +/* + * select serial console configuration + */ +#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ + +#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ +#define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ + +#define CFG_DRAM_BASE 0x00000000 +#define CFG_DRAM_SIZE 0x01000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * Expansion bus settings + */ +#define CFG_EXP_CS0 0xbcd23c42 + +/* + * SDRAM settings + */ +#define CFG_SDR_CONFIG 0xd +#define CFG_SDR_MODE_CONFIG 0x1 +#define CFG_SDRAM_REFRESH_CNT 0x81a + +/* + * GPIO settings + */ + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* FIXME */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h new file mode 100644 index 0000000..6590f6f --- /dev/null +++ b/include/configs/kb9202.h @@ -0,0 +1,173 @@ +/* + * Rick Bronson + * + * Configuation settings for the AT91RM9200DK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Adatped for KwikByte KB920x board from at91rm9200dk.h: 22APR2005 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */ +#define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +/* Only define one of the following, based on board type */ +/* #define CONFIG_KB9200 1 KwikByte KB9202 board */ +/* #define CONFIG_KB9201 1 KwikByte KB9202 board */ +#define CONFIG_KB9202 1 /* KwikByte KB9202 board */ + +#define CONFIG_KB920x 1 /* Any KB920x board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CFG_LONGHELP + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_I2C | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP ) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024) + +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 + +#define CFG_FLASH_BASE 0x10000000 + +#ifdef CONFIG_KB9202 +#define PHYS_FLASH_SIZE 0x1000000 +#else +#define PHYS_FLASH_SIZE 0x200000 +#endif + +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 + +#define CONFIG_HARD_I2C + +#define CFG_ENV_IS_IN_EEPROM + +#ifdef CONFIG_KB9202 +#define CFG_ENV_OFFSET 0x3E00 +#define CFG_ENV_SIZE 0x0200 +#else +#define CFG_ENV_OFFSET 0x1000 +#define CFG_ENV_SIZE 0x1000 +#endif +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0 /* not used */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CFG_LOAD_ADDR 0x21000000 /* default load address */ + +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/lart.h b/include/configs/lart.h new file mode 100644 index 0000000..a00640b --- /dev/null +++ b/include/configs/lart.h @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the LART board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SA1100 1 /* This is an SA1100 CPU */ +#define CONFIG_LART 1 /* on an LART Board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x20008300 +#define CS8900_BUS16 1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on LART */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 172.22.2.131 +#define CONFIG_SERVERIP 172.22.2.126 +#define CONFIG_BOOTFILE "elinos-lart" +#define CONFIG_BOOTCOMMAND "tftp; bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "LART # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xc8000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x0b /* set core clock to 220 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ +#define PHYS_SDRAM_2 0xc1000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ +#define PHYS_SDRAM_3 0xc8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00800000 /* 8 MB */ +#define PHYS_SDRAM_4 0xc9000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00800000 /* 8 MB */ + + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (31+8) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/logodl.h b/include/configs/logodl.h new file mode 100644 index 0000000..715ed74 --- /dev/null +++ b/include/configs/logodl.h @@ -0,0 +1,279 @@ +/* + * (C) Copyright 2003 + * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. + * + * Configuration for the Logotronic DL board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * include/configs/logodl.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + /* for timer/console/ethernet */ +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 19200 +#undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */ + +#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO) +/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ +#define CONFIG_BOOTARGS "console=ttyS0,19200" +#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.1.56 +#define CONFIG_SERVERIP 192.168.1.2 +#define CONFIG_BOOTCOMMAND "bootm 0x40000" +#define CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_CMDLINE_TAG 1 + +/* + * Miscellaneous configurable options + */ + +/* + * Size of malloc() pool; this lives below the uppermost 128 KiB which are + * used for the RAM copy of the uboot code + * + */ +#define CFG_MALLOC_LEN (256*1024) + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x08000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0800ffff /* 64 KiB */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x08000000 /* load kernel to this address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ + /* RS: the oscillator is actually 3680130?? */ + +#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ + /* 0101000001 */ + /* ^^^^^ Memory Speed 99.53 MHz */ + /* ^^ Run Mode Speed = 2x Mem Speed */ + /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ + +#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * SMSC91C111 Network Card + */ +#if 0 +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */ +#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ +#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ +#undef CONFIG_SHOW_ACTIVITY +#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ +#endif + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */ +#define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB */ + +#define CFG_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here */ +#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE + +#define CFG_FLASH_BASE PHYS_FLASH_1 + + +/* + * GPIO settings + * + * GP?? == FOOBAR is 0/1 + */ + +#define _BIT0 0x00000001 +#define _BIT1 0x00000002 +#define _BIT2 0x00000004 +#define _BIT3 0x00000008 + +#define _BIT4 0x00000010 +#define _BIT5 0x00000020 +#define _BIT6 0x00000040 +#define _BIT7 0x00000080 + +#define _BIT8 0x00000100 +#define _BIT9 0x00000200 +#define _BIT10 0x00000400 +#define _BIT11 0x00000800 + +#define _BIT12 0x00001000 +#define _BIT13 0x00002000 +#define _BIT14 0x00004000 +#define _BIT15 0x00008000 + +#define _BIT16 0x00010000 +#define _BIT17 0x00020000 +#define _BIT18 0x00040000 +#define _BIT19 0x00080000 + +#define _BIT20 0x00100000 +#define _BIT21 0x00200000 +#define _BIT22 0x00400000 +#define _BIT23 0x00800000 + +#define _BIT24 0x01000000 +#define _BIT25 0x02000000 +#define _BIT26 0x04000000 +#define _BIT27 0x08000000 + +#define _BIT28 0x10000000 +#define _BIT29 0x20000000 +#define _BIT30 0x40000000 +#define _BIT31 0x80000000 + + +#define CFG_LED_A_BIT (_BIT18) +#define CFG_LED_A_SR GPSR0 +#define CFG_LED_A_CR GPCR0 + +#define CFG_LED_B_BIT (_BIT16) +#define CFG_LED_B_SR GPSR1 +#define CFG_LED_B_CR GPCR1 + + +/* LED A: off, LED B: off */ +#define CFG_GPSR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18) +#define CFG_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13) +#define CFG_GPSR2_VAL (_BIT14+_BIT15+_BIT16) + +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 + +#define CFG_GPDR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18) +#define CFG_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13) +#define CFG_GPDR2_VAL (_BIT14+_BIT15+_BIT16) + +#define CFG_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31) +#define CFG_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\ + _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31) +#define CFG_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\ + _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31) +#define CFG_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) +#define CFG_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\ + _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) +#define CFG_GAFR2_U_VAL (_BIT1) + +#define CFG_PSSR_VAL (0x20) + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x123c2980 +#define CFG_MSC1_VAL 0x123c2661 +#define CFG_MSC2_VAL 0x7ff87ff8 + + +/* no sdram/pcmcia here */ +#define CFG_MDCNFG_VAL 0x00000000 +#define CFG_MDREFR_VAL 0x00000000 +#define CFG_MDREFR_VAL_100 0x00000000 +#define CFG_MDMRS_VAL 0x00000000 + +/* only SRAM */ +#define SXCNFG_SETTINGS 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ + +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +/* FIXME */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h new file mode 100644 index 0000000..3722fd2 --- /dev/null +++ b/include/configs/lpd7a400-10.h @@ -0,0 +1,80 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Logic LH7A400-10 card engine + */ + +#ifndef __LPD7A400_10_H +#define __LPD7A400_10_H + + +#define CONFIG_ARM920T 1 /* arm920t core */ +#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */ +#define CONFIG_LH7A400 1 /* Sharp LH7A400 S0C */ + +/* The system clock PLL input frequency */ +#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */ + +/* ticks per second */ +#define CFG_HZ (508469) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + +/*---------------------------------------------------------------------- + * Using SMC91C111 LAN chip + * + * Default IO base of chip is 0x300, Card Engine has this address lines + * (LAN chip) tied to Vcc, so we just care about the chip select + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE (0x70000000) +#undef CONFIG_SMC_USE_32_BIT +#define CONFIG_SMC_USE_IOFUNCS + +#endif /* __LPD7A400_10_H */ diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h new file mode 100644 index 0000000..d7d0460 --- /dev/null +++ b/include/configs/lpd7a400.h @@ -0,0 +1,106 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __LPD7A400_H_ +#define __LPD7A400_H_ + +#define CONFIG_LPD7A400 /* Logic LH7A400 SDK */ + +#undef CONFIG_USE_IRQ + +/* + * This board uses the logic LH7A400-10 card engine + */ +#include + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * select serial console configuration + */ +#define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_IPADDR 192.168.1.100 +#define CONFIG_NETMASK 255.255.1.0 +#define CONFIG_SERVERIP 192.168.1.1 + +#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ + +#ifndef USE_920T_MMU +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) +#endif + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "LPD7A400> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xc0f00000 /* default load address */ + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* size and location of u-boot in flash */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256<<10) + +#define CFG_ENV_IS_IN_FLASH 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0xFC0000) +#define CFG_ENV_SIZE 0x40000 + +#endif /* __LPD7A400_H_ */ diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h new file mode 100644 index 0000000..a8af950 --- /dev/null +++ b/include/configs/lpd7a404-10.h @@ -0,0 +1,80 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Logic LH7A400-10 card engine + */ + +#ifndef __LPD7A404_10_H +#define __LPD7A404_10_H + + +#define CONFIG_ARM920T 1 /* arm920t core */ +#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */ +#define CONFIG_LH7A404 1 /* Sharp LH7A404 SoC */ + +/* The system clock PLL input frequency */ +#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */ + +/* ticks per second */ +#define CFG_HZ (508469) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + +/*---------------------------------------------------------------------- + * Using SMC91C111 LAN chip + * + * Default IO base of chip is 0x300, Card Engine has this address lines + * (LAN chip) tied to Vcc, so we just care about the chip select + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE (0x70000000) +#undef CONFIG_SMC_USE_32_BIT +#define CONFIG_SMC_USE_IOFUNCS + +#endif /* __LPD7A404_10_H */ diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h new file mode 100644 index 0000000..4002e68 --- /dev/null +++ b/include/configs/lpd7a404.h @@ -0,0 +1,106 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __LPD7A404_H_ +#define __LPD7A404_H_ + +#define CONFIG_LPD7A404 /* Logic LH7A400 SDK */ + +#undef CONFIG_USE_IRQ + +/* + * This board uses the logic LH7A404-10 card engine + */ +#include + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * select serial console configuration + */ +#define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_IPADDR 192.168.1.100 +#define CONFIG_NETMASK 255.255.1.0 +#define CONFIG_SERVERIP 192.168.1.1 + +#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ + +#ifndef USE_920T_MMU +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) +#endif + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "LPD7A404> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xc0f00000 /* default load address */ + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* size and location of u-boot in flash */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256<<10) + +#define CFG_ENV_IS_IN_FLASH 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0xFC0000) +#define CFG_ENV_SIZE 0x40000 + +#endif /* __LPD7A404_H_ */ diff --git a/include/configs/luan.h b/include/configs/luan.h new file mode 100644 index 0000000..0335a00 --- /dev/null +++ b/include/configs/luan.h @@ -0,0 +1,306 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * John Otken, jotken@softadvances.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * luan.h - configuration for LUAN board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_LUAN 1 /* Board is Luan */ +#define CONFIG_440SP 1 /* Specific PPC440SP support */ +#define CONFIG_4xx 1 /* PPC4xx family */ +#define CONFIG_440 1 +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) +#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */ + +#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ +#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ +#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ +#define CFG_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */ + +#define CFG_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ + +#define CFG_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */ + +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +#if CFG_LARGE_FLASH == 0xffc00000 +#define CFG_FLASH_BASE CFG_LARGE_FLASH +#else +#define CFG_FLASH_BASE CFG_SMALL_FLASH +#endif + +#undef CFG_DRAM_TEST +#if CFG_SRAM_BASE +#define CFG_KBYTES_SDRAM 1024*2 +#else +#define CFG_KBYTES_SDRAM 1024 +#endif + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in SDRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_END (8 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#undef CONFIG_SERIAL_MULTI +#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2aa +#define CFG_FLASH_WORD_SIZE unsigned char + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */ +#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */ +#define IIC0_DIMM0_ADDR 0x52 +#define IIC0_DIMM1_ADDR 0x53 + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=luan\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/luan/uImage\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc100000\0" \ + "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#else +#define CONFIG_HW_WATCHDOG /* watchdog */ +#endif + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SETGETDCR | \ + CFG_CMD_SDRAM | \ + 0) + +/* this must be included AFTER the definition of CONFIG_COMMANDS */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#undef CONFIG_LYNXKDI /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#if (CONFIG_COMMANDS & CFG_CMD_PCI) + +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#undef CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */ + +#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h new file mode 100644 index 0000000..ad1035b --- /dev/null +++ b/include/configs/lubbock.h @@ -0,0 +1,240 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ +#define CONFIG_LCD 1 +#ifdef CONFIG_LCD +#define CONFIG_SHARP_LM8V31 +#endif +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE 0x0C000000 + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.0.21 +#define CONFIG_SERVERIP 192.168.0.250 +#define CONFIG_BOOTCOMMAND "bootm 80000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG +#define CONFIG_TIMESTAMP + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +#define FPGA_REGS_BASE_PHYSICAL 0x08000000 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00008000 +#define CFG_GPSR1_VAL 0x00FC0382 +#define CFG_GPSR2_VAL 0x0001FFFF +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x0060A800 +#define CFG_GPDR1_VAL 0x00FF0382 +#define CFG_GPDR2_VAL 0x0001C000 +#define CFG_GAFR0_L_VAL 0x98400000 +#define CFG_GAFR0_U_VAL 0x00002950 +#define CFG_GAFR1_L_VAL 0x000A9558 +#define CFG_GAFR1_U_VAL 0x0005AAAA +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x00000002 + +#define CFG_PSSR_VAL 0x20 + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x23F223F2 +#define CFG_MSC1_VAL 0x3FF1A441 +#define CFG_MSC2_VAL 0x7FF97FF1 +#define CFG_MDCNFG_VAL 0x00001AC9 +#define CFG_MDREFR_VAL 0x00018018 +#define CFG_MDMRS_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +#define _LED 0x08000010 +#define LED_BLANK 0x08000040 + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* NOTE: many default partitioning schemes assume the kernel starts at the + * second sector, not an environment. You have been warned! + */ +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) + + +/* + * FPGA Offsets + */ +#define WHOAMI_OFFSET 0x00 +#define HEXLED_OFFSET 0x10 +#define BLANKLED_OFFSET 0x40 +#define DISCRETELED_OFFSET 0x40 +#define CNFG_SWITCHES_OFFSET 0x50 +#define USER_SWITCHES_OFFSET 0x60 +#define MISC_WR_OFFSET 0x80 +#define MISC_RD_OFFSET 0x90 +#define INT_MASK_OFFSET 0xC0 +#define INT_CLEAR_OFFSET 0xD0 +#define GP_OFFSET 0x100 + +#endif /* __CONFIG_H */ diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h new file mode 100644 index 0000000..9b4c004 --- /dev/null +++ b/include/configs/lwmon.h @@ -0,0 +1,612 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* External logbuffer support */ +#define CONFIG_LOGBUFFER + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823E CPU */ +#define CONFIG_LWMON 1 /* ...on a LWMON board */ + +/* Default Ethernet MAC address */ +#define CONFIG_ETHADDR 00:11:B0:00:00:00 + +/* The default Ethernet MAC address can be overwritten just once */ +#ifdef CONFIG_ETHADDR +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#endif + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ + +#define CONFIG_LCD 1 /* use LCD controller ... */ +#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ + +#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ +#define CONFIG_LCD_INFO 1 /* ... and some board info */ +#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ + +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ +#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */ + +#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */ + +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +/* pre-boot commands */ +#define CONFIG_PREBOOT "setenv bootdelay 15" + +#undef CONFIG_BOOTARGS + +/* POST support */ +#define CONFIG_POST (CFG_POST_CACHE | \ + CFG_POST_WATCHDOG | \ + CFG_POST_RTC | \ + CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_ETHER | \ + CFG_POST_I2C | \ + CFG_POST_SPI | \ + CFG_POST_USB | \ + CFG_POST_SPR | \ + CFG_POST_SYSMON) + +/* + * Keyboard commands: + * # = 0x28 = ENTER : enable bootmessages on LCD + * 2 = 0x3A+0x3C = F1 + F3 : enable update mode + * 3 = 0x3C+0x3F = F3 + F6 : enable test mode + */ + +#define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv" + +/* "gatewayip=10.8.211.250\0" \ */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40280000\0" \ + "netmask=255.255.192.0\0" \ + "serverip=10.8.2.101\0" \ + "ipaddr=10.8.57.0\0" \ + "magic_keys=#23\0" \ + "key_magic#=28\0" \ + "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \ + "key_magic2=3A+3C\0" \ + "key_cmd2=echo *** Entering Update Mode ***;" \ + "if fatload ide 0:3 10000 update.scr;" \ + "then autoscr 10000;" \ + "else echo *** UPDATE FAILED ***;" \ + "fi\0" \ + "key_magic3=3C+3F\0" \ + "key_cmd3=echo *** Entering Test Mode ***;" \ + "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \ + "addip=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ + "panic=1\0" \ + "add_wdt=setenv bootargs $bootargs $wdt_args\0" \ + "add_misc=setenv bootargs $bootargs runmode\0" \ + "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \ + "bootm $kernel_addr\0" \ + "flash_self=run ramargs addip add_wdt addfb add_misc;" \ + "bootm $kernel_addr $ramdisk_addr\0" \ + "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \ + "run nfsargs addip add_wdt addfb;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "load=tftp 100000 /tftpboot/u-boot.bin\0" \ + "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \ + "wdt_args=wdt_8xx=off\0" \ + "verify=no" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_WATCHDOG 1 /* watchdog enabled */ +#define CFG_WATCHDOG_FREQ (CFG_HZ / 20) + +#undef CONFIG_STATUS_LED /* Status LED disabled */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + + +#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_SNTP ) +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * When the watchdog is enabled, output must be fast enough in Linux. + */ +#ifdef CONFIG_WATCHDOG +#define CFG_BAUDRATE_TABLE { 38400, 57600, 115200 } +#else +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#endif + +/*----------------------------------------------------------------------*/ +#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */ +#undef CONFIG_MODEM_SUPPORT_DEBUG + +#define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */ +#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ +#if 0 +#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ +#endif +/*----------------------------------------------------------------------*/ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_USE_BUFFER_WRITE +#define CFG_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */ +/* Buffer size. + We have two flash devices connected in parallel. + Each device incorporates a Write Buffer of 32 bytes. + */ +#define CFG_FLASH_BUFFER_SIZE (2*32) + +/* Put environment in flash which is much faster to boot than using the EEPROM */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */ + +/*----------------------------------------------------------------------- + * I2C/EEPROM Configuration + */ + +#define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */ +#define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */ +#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ +#define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */ +#define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */ +#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ +#define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */ + +#undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */ + +#ifdef CONFIG_USE_FRAM /* use FRAM */ +#define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#else /* use EEPROM */ +#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ +#endif /* CONFIG_USE_FRAM */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 + +/* List of I2C addresses to be verified by POST */ +#ifdef CONFIG_USE_FRAM +#define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \ + CFG_I2C_SYSMON_ADDR, \ + CFG_I2C_RTC_ADDR, \ + CFG_I2C_POWER_A_ADDR, \ + CFG_I2C_POWER_B_ADDR, \ + CFG_I2C_KEYBD_ADDR, \ + CFG_I2C_PICIO_ADDR, \ + CFG_I2C_EEPROM_ADDR, \ + } +#else /* Use EEPROM - which show up on 8 consequtive addresses */ +#define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \ + CFG_I2C_SYSMON_ADDR, \ + CFG_I2C_RTC_ADDR, \ + CFG_I2C_POWER_A_ADDR, \ + CFG_I2C_POWER_B_ADDR, \ + CFG_I2C_KEYBD_ADDR, \ + CFG_I2C_PICIO_ADDR, \ + CFG_I2C_EEPROM_ADDR+0, \ + CFG_I2C_EEPROM_ADDR+1, \ + CFG_I2C_EEPROM_ADDR+2, \ + CFG_I2C_EEPROM_ADDR+3, \ + CFG_I2C_EEPROM_ADDR+4, \ + CFG_I2C_EEPROM_ADDR+5, \ + CFG_I2C_EEPROM_ADDR+6, \ + CFG_I2C_EEPROM_ADDR+7, \ + } +#endif /* CONFIG_USE_FRAM */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +/* EARB, DBGC and DBPC are initialised by the HCW */ +/* => 0x000000C0 */ +#define CFG_SIUMCR (SIUMCR_GB5E) +/*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit, set PLL multiplication factor ! + */ +/* 0x00405000 */ +#define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */ +#define CFG_PLPRCR \ + ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ + /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ + PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ + ) + +#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* 0x01800000 */ +#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ + SCCR_RTDIV | SCCR_RTSEL | \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + SCCR_EBDF00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | \ + SCCR_DFNH000 | SCCR_DFLCD100 | \ + SCCR_DFALCD01) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/* 0x00C3 => 0x0003 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0x0000 + +/*----------------------------------------------------------------------- + * RMDS - RISC Microcode Development Support Control Register + *----------------------------------------------------------------------- + */ +#define CFG_RMDS 0 + +/*----------------------------------------------------------------------- + * + * Interrupt Levels + *----------------------------------------------------------------------- + */ +#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0x50000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0x54000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0x58000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0x5C000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +#define CONFIG_SUPPORT_VFAT /* enable VFAT support */ + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) - second Flash bank optional + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */ + +/* used to re-map FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */ + +/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK) + +#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ + CFG_OR_TIMING_FLASH) +/* 16 bit, bank valid */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) + +/* + * BR3/OR3: SDRAM + * + * Multiplexed addresses, GPL5 output to GPL5_A (don't care) + */ +#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ +#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */ +#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ + +#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */ + +#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * BR5/OR5: Touch Panel + * + * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 + */ +#define TOUCHPNL_BASE 0x20000000 +#define TOUCHPNL_OR_AM 0xFFFF8000 +#define TOUCHPNL_TIMING OR_SCY_0_CLK + +#define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + TOUCHPNL_TIMING ) +#define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) + +#define CFG_MEMORY_75 +#undef CFG_MEMORY_7E +#undef CFG_MEMORY_8E + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MPTPR 0x200 + +/* + * MAMR settings for SDRAM + */ + +#define CFG_MAMR_8COL 0x80802114 +#define CFG_MAMR_9COL 0x80904114 + +/* + * MAR setting for SDRAM + */ +#define CFG_MAR 0x00000088 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h new file mode 100644 index 0000000..6762cd6 --- /dev/null +++ b/include/configs/ml300.h @@ -0,0 +1,171 @@ +/* + * ML300.h: ML300 specific config options + * + * http://www.xilinx.com/ml300 + * + * Derived from : ML2.h + * + * Author: Xilinx, Inc. + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, + * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE + * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR + * OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY + * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM + * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * + * Xilinx products are not intended for use in life support appliances, + * devices, or systems. Use in such applications is expressly prohibited. + * + * + * (c) Copyright 2002 Xilinx Inc. + * All rights reserved. + * + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* #define DEBUG */ +/* #define ET_DEBUG 1 */ + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ + +#define CONFIG_SYSTEMACE 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_SYSTEMACE_BASE XPAR_OPB_SYSACE_0_BASEADDR +#define CFG_SYSTEMACE_WIDTH XPAR_XSYSACE_MEM_WIDTH + +#define CFG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */ + +/* following are used only if env is in EEPROM */ +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_I2C_EEPROM_ADDR XPAR_PERSISTENT_0_IIC_0_EEPROMADDR +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_ENV_OFFSET XPAR_PERSISTENT_0_IIC_0_BASEADDR +#define CONFIG_MISC_INIT_R 1 /* used to call out convert_env() */ +#define CONFIG_ENV_OVERWRITE 1 /* allow users to update ethaddr and serial# */ +#endif + +#include "../board/xilinx/ml300/xparameters.h" + +#define CFG_NO_FLASH 1 /* no flash */ +#define CFG_ENV_SIZE XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ + +#define CONFIG_BOOTARGS "console=ttyS0,9600 ip=off " \ + "root=/dev/xsysace/disc0/part3 rw" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define REMOVE_COMMANDS (CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_FAT | \ + CFG_CMD_IMLS ) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NET) \ + & ~REMOVE_COMMANDS) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */ +/* 300000000 */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_DUART_CHAN 0 +#define CFG_NS16550_REG_SIZE -4 +#define CFG_NS16550 1 +#define CFG_INIT_CHAN1 1 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MONITOR_BASE 0x04000000 +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +#define CFG_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h new file mode 100644 index 0000000..2028767 --- /dev/null +++ b/include/configs/modnet50.h @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2004 + * IMMS, gGmbH + * Thomas Elste + * + * Configuation settings for ModNET50 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#define CONFIG_NETARM /* it's a Netsiclicon NET+ARM */ +#undef CONFIG_NETARM_NET40_REV2 /* it's a Net+40 Rev. 2 */ +#undef CONFIG_NETARM_NET40_REV4 /* it's a Net+40 Rev. 4 */ +#define CONFIG_NETARM_NET50 /* it's a Net+50 */ + +#define CONFIG_MODNET50 1 /* on an ModNET50 Board */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_NETARMETH 1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_JFFS2)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.30.2 +#define CONFIG_SERVERIP 192.168.30.122 +#define CFG_ETH_PHY_ADDR 0x100 +#define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */ + +/*#define CONFIG_BOOTDELAY 10*/ +/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */ +#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000" +#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "modnet50 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00500000 /* default load address */ + +#define CFG_HZ 900 /* decrementer freq: 2 kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +#define PHYS_SDRAM_2 0x01000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */ + +#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */ +#define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip only, 16bit access) */ + +#define PHYS_FLASH_2 0x10200001 +#define PHYS_FLASH_2_SIZE 0x00200000 + +#define CONFIG_NETARM_EEPROM +/* #ifdef CONFIG_NETARM_EEPROM */ +#define PHYS_NVRAM_1 0x20000000 /* EEPROM Bank #1 */ +#define PHYS_NVRAM_SIZE 0x00002000 /* 8 KB */ +/* #endif */ + +#define PHYS_EXT_1 0x30000000 /* Extensions Bank #1 */ +#define PHYS_EXT_SIZE 0x01000000 /* 32 MB memory mapped I/O */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_FLASH_SIZE PHYS_FLASH_1_SIZE + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ +#define CFG_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +/* environment settings */ +#define CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_NOWHERE + +#define CFG_ENV_ADDR 0x1001C000 /* environment start address */ +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* max size for environment */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00080000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=modnet50-0" +#define MTDPARTS_DEFAULT "mtdparts=modnet50-0:-@512k(jffs2)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h new file mode 100644 index 0000000..04f1f24 --- /dev/null +++ b/include/configs/mp2usb.h @@ -0,0 +1,236 @@ +/* + * 2004-2005 Gary Jennejohn + * + * Modified for the MP2USB by (C) Copyright 2005 Eric Benard + * ebenard@eukrea.com + * + * Configuration settings for the MP2USB board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */ +#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ +#define CONFIG_MP2USB 1 /* on an MP2USB Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CFG_ATMEL_PLL_INIT_BUG 1 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ +#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ +#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ + +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000020 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */ + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_KEYBOARD 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_AT91C_PQFP_UHPBUG 1 + +#undef CONFIG_HARD_I2C + +#ifdef CONFIG_HARD_I2C +#define CFG_I2C_SPEED 0 /* not used */ +#define CFG_I2C_SLAVE 0 /* not used */ +#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ +#define CFG_I2C_RTC_ADDR 0x32 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW +#endif +/* still about 20 kB free with this defined */ +#define CFG_LONGHELP + +#define CONFIG_BOOTDELAY 3 + +#ifdef CONFIG_HARD_I2C +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + CFG_CMD_MISC)) +#else +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + CFG_CMD_USB | \ + CFG_CMD_CACHE) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_IMI | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS )) +#define CONFIG_TIMESTAMP +#endif +#define CFG_LONGHELP + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 + +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 +#undef CONFIG_AT91C_USE_RMII + +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x1000000 /* 16 megs main flash */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ +#define CFG_FLASH_LOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Set Lock Bit */ +#define CFG_FLASH_UNLOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Clear Lock Bits */ +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x20000 + +#define CFG_LOAD_ADDR 0x21000000 /* default load address */ + +#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } + +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 32 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif /* __ASSEMBLY__ */ + +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#define CFG_DEVICE_NULLDEV 1 /* enble null device */ +#undef CONFIG_SILENT_CONSOLE /* enable silent startup */ + +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_DELAY_STR "d" + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h new file mode 100644 index 0000000..7f3dfd5 --- /dev/null +++ b/include/configs/mx1ads.h @@ -0,0 +1,184 @@ +/* + * include/configs/mx1ads.h + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu + * + * This is the Configuration setting for Motorola MX1ADS board + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */ +#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Select serial console configuration + */ +#define CONFIG_IMX_SERIAL1 /* internal uart 1 */ +/* #define _CONFIG_UART2 */ /* internal uart 2 */ +/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */ + +#define BOARD_LATE_INIT 1 +#define USE_920T_MMU 1 + +#if 0 +#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ +#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ +#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ +#endif + +/* + * Size of malloc() pool + */ + +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * CS8900 Ethernet drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x15000300 +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* + * select serial console configuration + */ + +/* #define CONFIG_UART1 */ +/* #define CONFIG_UART2 1 */ + +#define CONFIG_BAUDRATE 115200 + +/*********************************************************** + * Command definition + ***********************************************************/ + +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + CFG_CMD_REGINFO | \ + CFG_CMD_ELF) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" +#define CONFIG_BOOTFILE "mx1ads" +#define CONFIG_BOOTCOMMAND "tftp; bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ + /* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ + +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ + +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "MX1ADS$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "MX1ADS=> " /* Monitor Command Prompt */ +#endif + +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) + /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x09000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CFG_LOAD_ADDR 0x08800000 /* default load address */ +/*#define CFG_HZ 1000 */ +#define CFG_HZ 3686400 +#define CFG_CPUSPEED 0x141 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ +#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CONFIG_SYNCFLASH 1 +#define PHYS_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_SECT (16) +#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff8000) + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x100000 + +/*----------------------------------------------------------------------- + * Enable passing ATAGS + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 + +#define CONFIG_SYS_CLK_FREQ 16780000 +#define CONFIG_SYSPLL_CLK_FREQ 16000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h new file mode 100644 index 0000000..9816be8 --- /dev/null +++ b/include/configs/mx1fs2.h @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ +#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ +#define CONFIG_MX1FS2 1 /* on a mx1fs2 board */ +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ + +/* + * Select serial console configuration + */ +#undef _CONFIG_UART1 /* internal uart 1 */ +#define _CONFIG_UART2 /* internal uart 2 */ +#undef _CONFIG_UART3 /* internal uart 3 */ +#undef _CONFIG_UART4 /* internal uart 4 */ +#undef CONFIG_SILENT_CONSOLE /* use this to disable output */ + +/* + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + & ~CFG_CMD_LOADS \ + & ~CFG_CMD_CONSOLE \ + & ~CFG_CMD_AUTOSCRIPT \ + & ~CFG_CMD_NET \ + & ~CFG_CMD_PING \ + & ~CFG_CMD_DHCP \ + | CFG_CMD_JFFS2 \ + ) + +#include + +/* + * Boot options. Setting delay to -1 stops autostart count down. + */ +#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "bootm 10080000" +#define CONFIG_SHOW_BOOT_PROGRESS + +/* + * General options for u-boot. Modify to save memory foot print + */ +#define CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "mx1fs2> " /* prompt string */ +#define CFG_CBSIZE 256 /* console I/O buffer */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ +#define CFG_MAXARGS 16 /* max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ + +#define CFG_MEMTEST_START 0x08100000 /* memtest test area */ +#define CFG_MEMTEST_END 0x08F00000 + +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* core clock - register value */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 115200 +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG 1 /* send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + +/* + * Malloc pool need to host env + 128 Kb reserve for other allocations. + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_STACKSIZE (120<<10) /* stack size */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ +#endif + +/* SDRAM Setup Values + * 0x910a8300 Precharge Command CAS 3 + * 0x910a8200 Precharge Command CAS 2 + * + * 0xa10a8300 AutoRefresh Command CAS 3 + * 0xa10a8200 Set AutoRefresh Command CAS 2 + */ +#define PRECHARGE_CMD 0x910a8300 +#define AUTOREFRESH_CMD 0xa10a8300 + +#define BUS32BIT_VERSION +/* + * SDRAM Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */ +#ifdef BUS32BIT_VERSION +#define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */ +#else +#define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */ +#endif +/* + * Flash Controller settings + */ + +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ + +#ifdef BUS32BIT_VERSION +#define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ +#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ +#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/ +#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ +#else +#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ +#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ +#define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/ +#define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */ +#endif +#define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */ +#define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */ + +/* This should be defined if CFI FLASH device is present. Actually benefit + is not so clear to me. In other words we can provide more informations + to user, but this expects more complex flash handling we do not provide + now.*/ +#undef CFG_FLASH_CFI + +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ + +#define CFG_FLASH_BASE MX1FS2_FLASH_BASE + +/* + * This is setting for JFFS2 support in u-boot. + * Right now there is no gain for user, but later on booting kernel might be + * possible. Consider using XIP kernel running from flash to save RAM + * footprint. + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + */ + +/* + * JFFS2 partitions + */ +/* No command line, one static partition, whole device */ +/* +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00050000 +*/ + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=mx1fs2-0" + +#ifdef BUS32BIT_VERSION +#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)" +#else +#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:-@320k(jffs2)" +#endif + +/* + * Environment setup. Definitions of monitor location and size with + * definition of environment setup ends up in 2 possibilities. + * 1. Embeded environment - in u-boot code is space for environment + * 2. Environment is read from predefined sector of flash + * Right now we support 2. possiblity, but expecting no env placed + * on mentioned address right now. This also needs to provide whole + * sector for it - for us 256Kb is really waste of memory. U-boot uses + * default env. and until kernel parameters could be sent to kernel + * env. has no sense to us. + */ + +#define CFG_MONITOR_BASE 0x10000000 +#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */ +#define CFG_ENV_SIZE 0x20000 + +#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ + +/* Setup CS4 and CS5 */ +#define CFG_GIUS_A_VAL 0x0003fffe + +/* + * CSxU_VAL: + * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 + * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | + * + * CSxL_VAL: + * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 + * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| + */ + +#define CFG_CS0U_VAL 0x00008C00 +#define CFG_CS0L_VAL 0x22222601 +#define CFG_CS1U_VAL 0x00008C00 +#define CFG_CS1L_VAL 0x22222301 +#define CFG_CS4U_VAL 0x00008C00 +#define CFG_CS4L_VAL 0x22222301 +#define CFG_CS5U_VAL 0x00008C00 +#define CFG_CS5L_VAL 0x22222301 + +/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) + f_ref=16,777MHz + + 0x002a141f: 191,9944MHz + 0x040b2007: 144MHz + 0x042a141f: 96MHz + 0x0811140d: 64MHz + 0x040e200e: 150MHz + 0x00321431: 200MHz + + 0x08001800: 64MHz mit 16er Quarz + 0x04001800: 96MHz mit 16er Quarz + 0x04002400: 144MHz mit 16er Quarz + + 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 + |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ + +#define CFG_MPCTL0_VAL 0x07E723AD +#define CFG_MPCTL1_VAL 0x00000040 +#define CFG_PCDR_VAL 0x00010005 +#define CFG_GPCR_VAL 0x00000FFB + +#define USE_16M_OSZI /* If you have one, you want to use it + The internal 32kHz oszillator jitters */ +#ifdef USE_16M_OSZI + +#define CFG_SPCTL0_VAL 0x04001401 +#define CFG_SPCTL1_VAL 0x0C000040 +#define CFG_CSCR_VAL 0x07030003 +#define CONFIG_SYS_CLK_FREQ 16780000 +#define CONFIG_SYSPLL_CLK_FREQ 16000000 + +#else + +#define CFG_SPCTL0_VAL 0x07E716D1 +#define CFG_CSCR_VAL 0x06000003 +#define CONFIG_SYS_CLK_FREQ 16780000 +#define CONFIG_SYSPLL_CLK_FREQ 16780000 + +#endif + +/* + * Well this has to be defined, but on the other hand it is used differently + * one may expect. For instance loadb command do not cares :-) + * So advice is - do not relay on this... + */ +#define CFG_LOAD_ADDR 0x08400000 + +#define CFG_FMCR_VAL 0x00000003 /* Reset Default */ + +/* Bit[0:3] contain PERCLK1DIV for UART 1 + 0x000b00b ->b<- -> 192MHz/12=16MHz + 0x000b00b ->8<- -> 144MHz/09=16MHz + 0x000b00b ->3<- -> 64MHz/4=16MHz */ + +#ifdef _CONFIG_UART1 +#define CONFIG_IMX_SERIAL1 +#elif defined _CONFIG_UART2 +#define CONFIG_IMX_SERIAL2 +#elif defined _CONFIG_UART3 | defined _CONFIG_UART4 +#define CONFIG_IMX_SERIAL_NONE +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_CLK 3686400 +#define CFG_NS16550_REG_SIZE 1 +#define CONFIG_CONS_INDEX 1 +#ifdef _CONFIG_UART3 +#define CFG_NS16550_COM1 0x15000000 +#elif defined _CONFIG_UART4 +#define CFG_NS16550_COM1 0x16000000 +#endif +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h new file mode 100644 index 0000000..0b1541d --- /dev/null +++ b/include/configs/ns9750dev.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * Markus Pietrek + * + * Configuation settings for the NetSilicon NS9750 DevBoard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */ +#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */ + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */ + +#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2) +#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4) +#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8) + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/*@TODO #define CONFIG_STATUS_LED*/ +#define CONFIG_USE_IRQ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial + * data */ + +/* + * Hardware drivers + */ +#define CFG_NS9750_UART 1 /* use on-chip UART */ +#define CONFIG_DRIVER_NS9750_ETHERNET 1 /* use on-chip ethernet */ + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 /* Port B */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +/*********************************************************** + * Command definition + ***********************************************************/ +#if 0 /* @TODO */ +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + /*CFG_CMD_NAND |*/ \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF) +#else +#define CONFIG_COMMANDS \ + (CONFIG_CMD_BDI | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_LOADB | \ + CFG_CMD_LOADS | \ + CFG_CMD_MEMORY) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ + +#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.42.30 +#define CONFIG_SERVERIP 192.168.42.1 + +/*#define CONFIG_BOOTFILE "elinos-lart" */ +/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "NS9750DEV # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */ + +#define CFG_HZ (CPU_CLK_FREQ/64) + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define NS9750_ETH_PHY_ADDRESS (0x0000) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +/* TODO */ +#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ +#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ + +#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* @TODO*/ +#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ +#if 0 +#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ +#endif + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ +#endif + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + +/* @TODO */ +/*#define CFG_ENV_IS_IN_FLASH 1*/ +#define CFG_ENV_IS_NOWHERE +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +#ifdef CONFIG_STATUS_LED + +extern void __led_init(led_id_t mask, int state); +extern void __led_toggle(led_id_t mask); +extern void __led_set(led_id_t mask, int state); + +#endif /* CONFIG_STATUS_LED */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h new file mode 100644 index 0000000..5c05a74 --- /dev/null +++ b/include/configs/o2dnt.h @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 +#define CONFIG_O2DNT 1 /* ... on O2DNT board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +/* #define CONFIG_PCI_SCAN_SHOW 1 */ + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CFG_XLB_PIPELINING 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 + +#define ADD_PCI_CMD CFG_CMD_PCI + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + ADD_PCI_CMD ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ +# define CFG_LOWBOOT 1 +#else +# error "TEXT_BASE must be 0xFF000000" +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/MPC5200/uImage\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if defined(CFG_IPBSPEED_133) +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. + */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#endif +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration: + * + * O2DNT board is equiped with Ramtron FRAM device FM24CL16 + * 16 Kib Ferroelectric Nonvolatile serial RAM memory + * organized as 2048 x 8 bits and addressable as eight I2C devices + * 0x50 ... 0x57 each 256 bytes in size + * + */ +#define CFG_I2C_FRAM +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +/* + * There is no write delay with FRAM, write operations are performed at bus + * speed. Thus, no status polling or write delay is needed. + */ +/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70*/ + + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 0x01000000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) + +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + */ +/*#define CFG_GPS_PORT_CONFIG 0x10002004 */ +#define CFG_GPS_PORT_CONFIG 0x00002006 /* no CAN */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE + +#ifdef CFG_PCISPEED_66 +/* + * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). + */ +#define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */ +#else +#define CFG_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */ +#endif + +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h new file mode 100644 index 0000000..a13d6a8 --- /dev/null +++ b/include/configs/ocotea.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2004 Paul Reynolds + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * 1 March 2004 Travis B. Sawyer + * Adapted to current Das U-Boot source + ***********************************************************************/ + + +/************************************************************************ + * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_OCOTEA 1 /* Board is ebony */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or NVRAM). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#endif + + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_NVRAM */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=ocotea\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/ocotea/uImage\0" \ + "kernel_addr=fff00000\0" \ + "ramdisk_addr=fff10000\0" \ + "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 2 +#define CONFIG_PHY2_ADDR 0x10 +#define CONFIG_PHY3_ADDR 0x18 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h new file mode 100644 index 0000000..6787b19 --- /dev/null +++ b/include/configs/omap1510.h @@ -0,0 +1,790 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * OMAP hardware map + * + * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) + * Author: RidgeRun, Inc. + * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +/* + There are 2 sets of general I/O --> + 1. GPIO (shared between ARM & DSP, configured by ARM) + 2. MPUIO which can be used only by the ARM. + + Base address FFFB:5000 is where the ARM accesses the MPUIO control registers + (see 7.2.2 of the TRM for MPUIO reg definitions). + + Base address E101:5000 is reserved for ARM access of the same MPUIO control + regs, but via the DSP I/O map. This address is unavailable on 1510. + + Base address FFFC:E000 is where the ARM accesses the GPIO config registers + directly via its own peripheral bus. + + Base address E101:E000 is where the ARM can access the same GPIO config + registers, but the access takes place through the ARM port interface (called + API or MPUI) via the DSP's peripheral bus (DSP I/O space). + + Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses + instead of the E101:E000 addresses. The DSP has only read access of the pin + control register, so this may explain the inability to write to E101:E018. + Try accessing pin control reg at FFFC:E018. + */ +#define OMAP1510_GPIO_BASE 0xfffce000 +#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE +#define OMAP1510_GPIO_SIZE SZ_4K + +#define OMAP1510_MCBSP1_BASE 0xE1011000 +#define OMAP1510_MCBSP1_SIZE SZ_4K +#define OMAP1510_MCBSP1_START 0xE1011000 + +#define OMAP1510_MCBSP2_BASE 0xFFFB1000 + +#define OMAP1510_MCBSP3_BASE 0xE1017000 +#define OMAP1510_MCBSP3_SIZE SZ_4K +#define OMAP1510_MCBSP3_START 0xE1017000 + +/* + * Where's the flush address (for flushing D and I cache?) + */ +#define FLUSH_BASE 0xdf000000 +#define FLUSH_BASE_PHYS 0x00000000 + +#ifndef __ASSEMBLER__ + +#define PCIO_BASE 0 + +/* + * RAM definitions + */ +#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) +#define KERNTOPHYS(a) ((unsigned long)(&a)) +#define KERNEL_BASE (0x10008000) +#endif + +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) ((x)) + +/* ---------------------------------------------------------------------------- + * OMAP1510 system registers + * ---------------------------------------------------------------------------- + */ + +#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ +#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ +#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ +#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ +#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ +#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ +#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ + +/* + * OMAP1510 UART3 Registers + */ + +#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ + +/* UART3 Registers Maping through MPU bus */ + +#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) +#define UART3_THR (OMAP_MPU_UART3_BASE + 0) +#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) +#define UART3_IER (OMAP_MPU_UART3_BASE + 4) +#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) +#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) +#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) +#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) +#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) +#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) +#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) +#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) +#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) +#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) +#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) +#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) +#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) +#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) +#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) +#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) +#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) +#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) +#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) +#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) +#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) +#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) +#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) +#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) +#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) +#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) +#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) +#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) +#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) +#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) +#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) +#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) +#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) + +/* + * Configuration Registers + */ +#define FUNC_MUX_CTRL_0 0xfffe1000 +#define FUNC_MUX_CTRL_1 0xfffe1004 +#define FUNC_MUX_CTRL_2 0xfffe1008 +#define COMP_MODE_CTRL_0 0xfffe100c +#define FUNC_MUX_CTRL_3 0xfffe1010 +#define FUNC_MUX_CTRL_4 0xfffe1014 +#define FUNC_MUX_CTRL_5 0xfffe1018 +#define FUNC_MUX_CTRL_6 0xfffe101C +#define FUNC_MUX_CTRL_7 0xfffe1020 +#define FUNC_MUX_CTRL_8 0xfffe1024 +#define FUNC_MUX_CTRL_9 0xfffe1028 +#define FUNC_MUX_CTRL_A 0xfffe102C +#define FUNC_MUX_CTRL_B 0xfffe1030 +#define FUNC_MUX_CTRL_C 0xfffe1034 +#define FUNC_MUX_CTRL_D 0xfffe1038 +#define PULL_DWN_CTRL_0 0xfffe1040 +#define PULL_DWN_CTRL_1 0xfffe1044 +#define PULL_DWN_CTRL_2 0xfffe1048 +#define PULL_DWN_CTRL_3 0xfffe104c +#define GATE_INH_CTRL_0 0xfffe1050 +#define VOLTAGE_CTRL_0 0xfffe1060 +#define TEST_DBG_CTRL_0 0xfffe1070 + +#define MOD_CONF_CTRL_0 0xfffe1080 + +#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */ + +#define USB_OTG_CTRL 0xFFFB040C +#define USB_TRANSCEIVER_CTRL 0xFFFE1064 +#define PULL_DWN_CTRL_4 0xFFFE10AC +#define PU_PD_SEL_0 0xFFFE10B4 +#define PU_PD_SEL_1 0xFFFE10B8 +#define PU_PD_SEL_2 0xFFFE10BC +#define PU_PD_SEL_3 0xFFFE10C0 +#define PU_PD_SEL_4 0xFFFE10C4 + +#endif +/* + * Traffic Controller Memory Interface Registers + */ +#define TCMIF_BASE 0xfffecc00 +#define IMIF_PRIO (TCMIF_BASE + 0x00) +#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) +#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) +#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) +#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) +#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) +#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) +#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) +#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) +#define EMIFF_MRS (TCMIF_BASE + 0x24) +#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) +#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) +#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) +#define TC_ENDIANISM (TCMIF_BASE + 0x34) +#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) +#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) + +/* + * LCD Panel + */ +#define TI925_LCD_BASE 0xFFFEC000 +#define TI925_LCD_CONTROL (TI925_LCD_BASE) +#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) +#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) +#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) +#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) +#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) + +#define OMAP_LCD_CONTROL TI925_LCD_CONTROL + +/* I2C Registers */ + +#define I2C_BASE 0xfffb3800 + +#define I2C_REV (I2C_BASE + 0x00) +#define I2C_IE (I2C_BASE + 0x04) +#define I2C_STAT (I2C_BASE + 0x08) +#define I2C_IV (I2C_BASE + 0x0c) +#define I2C_BUF (I2C_BASE + 0x14) +#define I2C_CNT (I2C_BASE + 0x18) +#define I2C_DATA (I2C_BASE + 0x1c) +#define I2C_CON (I2C_BASE + 0x24) +#define I2C_OA (I2C_BASE + 0x28) +#define I2C_SA (I2C_BASE + 0x2c) +#define I2C_PSC (I2C_BASE + 0x30) +#define I2C_SCLL (I2C_BASE + 0x34) +#define I2C_SCLH (I2C_BASE + 0x38) +#define I2C_SYSTEST (I2C_BASE + 0x3c) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ + +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_AD0 (1 << 8) /* Address zero */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Interrupt Vector Register (I2C_IV): */ + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ + +/* + * MMC/SD Host Controller Registers + */ + +#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ +#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ +#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ +#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ +#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ +#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ +#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ +#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ +#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ +#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ +#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ +#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ +#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ +#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ +#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ +#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ +#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ +#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ +#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ +#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ +#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ +#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ +#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ +#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ + +/* MMC masks */ + +#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ +#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ +#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ +#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ +#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ +#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ +#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ +#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ +#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ +#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ +#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ +#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ +#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ + +/* 2.9.2 MPUI Interface Registers FFFE:C900 */ + +#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) +#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) +#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) +#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) +#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) +#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) +#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) +#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) + +/* 2.9.6 Traffic Controller Memory Interface Registers: */ +#define OMAP_IMIF_PRIO_REG 0xfffecc00 +#define OMAP_EMIFS_PRIO_REG 0xfffecc04 +#define OMAP_EMIFF_PRIO_REG 0xfffecc08 +#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c +#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 +#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 +#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 +#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c +#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 +#define OMAP_EMIFF_MRS 0xfffecc24 +#define OMAP_TIMEOUT1 0xfffecc28 +#define OMAP_TIMEOUT2 0xfffecc2c +#define OMAP_TIMEOUT3 0xfffecc30 +#define OMAP_ENDIANISM 0xfffecc34 + +/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ +#define OMAP_EMIFS_CONFIG_FR (1 << 4) +#define OMAP_EMIFS_CONFIG_PDE (1 << 3) +#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) +#define OMAP_EMIFS_CONFIG_BM (1 << 1) +#define OMAP_EMIFS_CONFIG_WP (1 << 0) + +/* + * Memory chunk set aside for the Framebuffer in SRAM + */ +#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE + + +/* + * DMA + */ + +#define OMAP1510_DMA_BASE 0xFFFED800 +#define OMAP_DMA_BASE OMAP1510_DMA_BASE + +/* Global Register selection */ +#define NO_GLOBAL_DMA_ACCESS 0 + +/* Channel select field + * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... + */ +#define LCD_CHANNEL 0xc + +/* Register Select Field (LCD) */ +#define DMA_LCD_CTRL 0 +#define DMA_LCD_TOP_F1_L 1 +#define DMA_LCD_TOP_F1_U 2 +#define DMA_LCD_BOT_F1_L 3 +#define DMA_LCD_BOT_F1_U 4 + +#define LCD_FRAME_MODE (1<<0) +#define LCD_FRAME_IT_IE (1<<1) +#define LCD_BUS_ERROR_IT_IE (1<<2) +#define LCD_FRAME_1_IT_COND (1<<3) +#define LCD_FRAME_2_IT_COND (1<<4) +#define LCD_BUS_ERROR_IT_COND (1<<5) +#define LCD_SOURCE_IMIF (1<<6) + +/* + * Real-Time Clock + */ + +#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) +#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) +#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) +#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) +#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) +#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) +#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) + + +/* --------------------------------------------------------------------------- + * OMAP1510 Interrupt Handlers + * --------------------------------------------------------------------------- + * + */ +#define OMAP_IH1_BASE 0xfffecb00 +#define OMAP_IH2_BASE 0xfffe0000 +#define OMAP1510_ITR 0x0 +#define OMAP1510_MASK 0x4 + +#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE +#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR +#define INTERRUPT_MASK_REGISTER OMAP1510_MASK + + +/* --------------------------------------------------------------------------- + * OMAP1510 TIMERS + * --------------------------------------------------------------------------- + * + */ + +#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 + +/* 32k Timer Registers */ +#define TIMER32k_CR 0x08 +#define TIMER32k_TVR 0x00 +#define TIMER32k_TCR 0x04 + +/* 32k Timer Control Register definition */ +#define TIMER32k_TSS (1<<0) +#define TIMER32k_TRB (1<<1) +#define TIMER32k_INT (1<<2) +#define TIMER32k_ARL (1<<3) + +/* MPU Timer base addresses */ +#define OMAP1510_MPUTIMER_BASE 0xfffec500 +#define OMAP1510_MPUTIMER_OFF 0x00000100 + +#define OMAP1510_TIMER1_BASE 0xfffec500 +#define OMAP1510_TIMER2_BASE 0xfffec600 +#define OMAP1510_TIMER3_BASE 0xfffec700 + +/* MPU Timer Registers */ +#define CNTL_TIMER 0 +#define LOAD_TIM 4 +#define READ_TIM 8 + +/* CNTL_TIMER register bits */ +#define MPUTIM_FREE (1<<6) +#define MPUTIM_CLOCK_ENABLE (1<<5) +#define MPUTIM_PTV_MASK (0x7< + * Configuation settings for the TI OMAP Innovator board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ +#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */ + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +/* +#define CONFIG_DRIVER_SMC9196 +#define CONFIG_SMC9196_BASE 0x08000300 +#define CONFIG_SMC9196_EXT_PHY +*/ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE 0x08000300 +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp" +#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" +#define CFG_AUTOLOAD "n" /* No autoload */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x10000000 /* default load address */ + +/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. + * This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE) +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE } + +/*----------------------------------------------------------------------- + * FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h new file mode 100644 index 0000000..c6ca689 --- /dev/null +++ b/include/configs/omap1610h2.h @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2004 + * Texas Instruments. + * Kshitij Gupta + * Configuration settings for the TI OMAP 1610 H2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP1610 1 /* which is in a 1610 */ +#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */ +#define CONFIG_MACH_OMAP_H2 /* Select board mach-type */ + +/* input clock of PLL */ +/* the OMAP1610 H2 has 12MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE 0x04000300 +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp" +#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" +#define CFG_AUTOLOAD "n" /* No autoload */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x10000000 /* default load address */ + +/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by + * DPLL1. This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ +#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ + +#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ + +#ifndef __ASSEMBLY__ +extern unsigned long omap_flash_base; /* set in flash__init */ +#endif +#define CFG_FLASH_BASE omap_flash_base + +#elif defined(CONFIG_CS0_BOOT) + +#define CFG_FLASH_BASE PHYS_FLASH_1_BM0 + +#else + +#define CFG_FLASH_BASE PHYS_FLASH_1_BM1 + +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h new file mode 100644 index 0000000..f28ede0 --- /dev/null +++ b/include/configs/omap1610inn.h @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP Innovator board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP1610 1 /* which is in a 1610 */ +#define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */ +#define CONFIG_MACH_OMAP_INNOVATOR /* Select board mach-type */ + +/* input clock of PLL */ +/* the OMAP1610 Innovator has 12MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +/* +*/ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE 0x04000300 +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ + root=/dev/nfs rw nfsroot=157.87.82.48:\ + /home/a0875451/mwd/myfs/target ip=dhcp" +#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ +#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ +#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ +#define CONFIG_BOOTFILE "uImage" /* file to load */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x10000000 /* default load address */ + +/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by + * DPLL1. This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ +#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ + +#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ + +#ifndef __ASSEMBLY__ +extern unsigned long omap_flash_base; /* set in flash__init */ +#endif +#define CFG_FLASH_BASE omap_flash_base + +#elif defined(CONFIG_CS0_BOOT) + +#define CFG_FLASH_BASE PHYS_FLASH_1_BM0 + +#else + +#define CFG_FLASH_BASE PHYS_FLASH_1_BM1 + +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h new file mode 100644 index 0000000..12252ac --- /dev/null +++ b/include/configs/omap2420h4.h @@ -0,0 +1,293 @@ +/* + * (C) Copyright 2004 + * Texas Instruments. + * Richard Woodruff + * Kshitij Gupta + * + * Configuration settings for the 242x TI H4 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP2420 1 /* which is in a 2420 */ +#define CONFIG_OMAP2420H4 1 /* and on a H4 board */ +/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ +/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ + +/* Clock config to target*/ +#define PRCM_CONFIG_II 1 +/* #define PRCM_CONFIG_III 1 */ + +#include /* get chip and board defs */ + +/* On H4, NOR and NAND flash are mutual exclusive. + Define this if you want to use NAND + */ +/*#define CFG_NAND_BOOT */ + +#ifdef CONFIG_APTIX +#define V_SCLK 1500000 +#else +#define V_SCLK 12000000 +#endif + +/* input clock of PLL */ +/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ +#define CONFIG_SYS_CLK_FREQ V_SCLK + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * SMC91c96 Etherent + */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300) +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ +#ifdef CONFIG_APTIX +#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */ +#else +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ +#endif + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ +#define CFG_NS16550_COM1 OMAP2420_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on H4 */ + + /* + * I2C configuration + */ +#define CONFIG_HARD_I2C +#define CFG_I2C_SPEED 100000 +#define CFG_I2C_SLAVE 1 +#define CONFIG_DRIVER_OMAP24XX_I2C + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +#ifdef CFG_NAND_BOOT +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) +#endif +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) +#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0) +#define READ_NAND(adr) (*(volatile u16 *)0x6800A084) +#define NAND_WAIT_READY(nand) udelay(10) + +#define NAND_NO_RB 1 + +#define CFG_NAND_WP +#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) + +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) + +#define CONFIG_BOOTDELAY 3 + +#ifdef NFS_BOOT_DEFAULTS +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" +#else +#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" +#endif + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" + +/* + * Miscellaneous configurable options + */ +#ifdef CONFIG_APTIX +#define V_PROMPT "OMAP2420 Aptix # " +#else +#define V_PROMPT "OMAP242x H4 # " +#endif + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ + +/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#ifdef CONFIG_APTIX +#define V_PVT 3 +#else +#define V_PVT 7 /* use with 12MHz/128 */ +#endif + +#define CFG_TIMERBASE OMAP2420_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 + +#define PHYS_FLASH_SECT_SIZE SZ_128K +#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE_1 SZ_32M +#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ +#define PHYS_FLASH_SIZE_2 SZ_32M + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ +#define CFG_MONITOR_LEN SZ_128K /* Reserve 1 sector */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 } + +#ifdef CFG_NAND_BOOT +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x80000 /* environment starts here */ +#else +#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K) +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ +#endif + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_JFFS2_MEM_NAND + +/* + * JFFS2 partitions + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor1" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor1=omap2420-1" +#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h new file mode 100644 index 0000000..605563a --- /dev/null +++ b/include/configs/omap5912osk.h @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP Innovator board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */ +#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */ + +/* input clock of PLL */ +/* the OMAP5912 OSK has 12MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +/* + * Hardware drivers + */ +/* +*/ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE 0x04800300 +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart + on helen */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ + root=/dev/nfs rw nfsroot=157.87.82.48:\ + /home/mwd/myfs/target ip=dhcp" +#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ +#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ +#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ +#define CONFIG_BOOTFILE "uImage" /* file to load */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x10000000 /* default load address */ + +/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by + * DPLL1. This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap730.h b/include/configs/omap730.h new file mode 100644 index 0000000..03abcb3 --- /dev/null +++ b/include/configs/omap730.h @@ -0,0 +1,264 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * OMAP730 hardware map + * + * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk) + * Author: MPC-Data Limited + * Dave Peverley + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __INCLUDED_OMAP730_H +#define __INCLUDED_OMAP730_H + +#include + +/*************************************************************************** + * OMAP730 Configuration Registers + **************************************************************************/ + +#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000)) +#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000)) +#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002)) +#define DSP_CONF ((unsigned int)(0xFFFE1004)) +#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008)) +#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008)) +#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C)) +#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010)) +#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010)) +#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012)) +#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014)) +#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014)) +#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016)) +#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018)) +#define SPECCTL ((unsigned int)(0xFFFE101C)) +#define SPARE1 ((unsigned int)(0xFFFE1020)) +#define SPARE2 ((unsigned int)(0xFFFE1024)) +#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028)) +#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030)) +#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060)) +#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070)) +#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074)) +#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078)) +#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C)) +#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080)) +#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084)) +#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088)) +#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C)) +#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090)) +#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094)) +#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098)) +#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C)) +#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0)) +#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4)) +#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4)) +#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8)) +#define BIST_CONTROL ((unsigned int)(0xFFFE10C0)) +#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4)) +#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8)) +#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0)) +#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4)) +#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8)) +#define DEBUG1 ((unsigned int)(0xFFFE10E0)) +#define DEBUG2 ((unsigned int)(0xFFFE10E4)) +#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8)) + +/*************************************************************************** + * OMAP730 EMIFS Registers (TRM 2.5.7) + **************************************************************************/ + +#define TCMIF_BASE 0xFFFECC00 + +#define EMIFS_LRUREG (TCMIF_BASE + 0x04) +#define EMIFS_CONFIG (TCMIF_BASE + 0x0C) +#define FLASH_CFG_0 (TCMIF_BASE + 0x10) +#define FLASH_CFG_1 (TCMIF_BASE + 0x14) +#define FLASH_CFG_2 (TCMIF_BASE + 0x18) +#define FLASH_CFG_3 (TCMIF_BASE + 0x1C) +#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40) +#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28) +#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C) +#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30) +#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44) +#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48) +#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C) +#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50) +#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54) +#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58) +#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C) + +/*************************************************************************** + * OMAP730 Interrupt handlers + **************************************************************************/ + +#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */ +#define OMAP_IH2_BASE 0xfffe0000 + +/*************************************************************************** + * OMAP730 Timers + * + * There are three general purpose OS timers in the 730 that can be + * configured in autoreload or one-shot modes. + **************************************************************************/ + +#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000 + +/* 32k Timer Registers */ +#define TIMER32k_CR 0x08 +#define TIMER32k_TVR 0x00 +#define TIMER32k_TCR 0x04 + +/* 32k Timer Control Register definition */ +#define TIMER32k_TSS (1<<0) +#define TIMER32k_TRB (1<<1) +#define TIMER32k_INT (1<<2) +#define TIMER32k_ARL (1<<3) + +/* MPU Timer base addresses */ +#define OMAP730_MPUTIMER_BASE 0xfffec500 +#define OMAP730_MPUTIMER_OFF 0x00000100 + +#define OMAP730_TIMER1_BASE 0xFFFEC500 +#define OMAP730_TIMER2_BASE 0xFFFEC600 +#define OMAP730_TIMER3_BASE 0xFFFEC700 + +/* MPU Timer Register offsets */ +#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */ +#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */ +#define READ_TIM 0x08 /* MPU_READ_TIMER */ + +/* MPU_CNTL_TIMER register bits */ +#define MPUTIM_FREE (1<<6) +#define MPUTIM_CLOCK_ENABLE (1<<5) +#define MPUTIM_PTV_MASK (0x7< + * + * Configuation settings for the TI OMAP Perseus 2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP730 1 /* which is in a 730 */ +#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */ + +/* + * Input clock of PLL + * The OMAP730 Perseus 2 has 13MHz input clock + */ + +#define CONFIG_SYS_CLK_FREQ 13000000 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 + +/* + * Size of malloc() pool + */ + +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE 0x04000300 +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (1) +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart + * on perseus */ + +/* + * select serial console configuration + */ + +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* + * This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ + +#include +#include +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp" + +#define CONFIG_LOADADDR 0x10000000 + +#define CONFIG_ETHADDR +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.23 +#define CONFIG_SERVERIP 192.150.0.100 +#define CONFIG_BOOTFILE "uImage" /* File to load */ + +#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x10000000 /* default load address */ + +/* The OMAP730 has 3 general purpose MPU timers, they can be driven by + * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a + * local divisor. + */ + +#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ + +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#if defined(CONFIG_CS0_BOOT) +#define PHYS_FLASH_1 0x0C000000 +#elif defined(CONFIG_CS3_BOOT) +#define PHYS_FLASH_1 0x00000000 +#else +#error Unknown Boot Chip-Select number +#endif + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ + +#endif /* ! __CONFIG_H */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h new file mode 100644 index 0000000..831d018 --- /dev/null +++ b/include/configs/p3p440.h @@ -0,0 +1,318 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * board/config_p3p440.h - configuration for Prodrive P3P440 + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_P3P440 1 /* Board is P3P440 */ +#define CONFIG_440GP 1 /* Specifc GP support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_USB_BASE (CFG_PERIPHERAL_BASE + 0x00000000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ +#define CFG_SDRAM_TABLE { \ + {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \ + {(64 << 20), 0x00082001}} /* 64MB mode 2, 12x9(4) */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/*----------------------------------------------------------------------- + * I2C RTC + *----------------------------------------------------------------------*/ +#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (PCF8594C) for environment + *----------------------------------------------------------------------*/ +#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ + /* 8 byte page write mode using */ + /* last 3 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/*----------------------------------------------------------------------- + * Default configuration (environment varibles...) + *----------------------------------------------------------------------*/ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=p3p440\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/p3p440/uImage\0" \ + "kernel_addr=ff800000\0" \ + "ramdisk_addr=ff810000\0" \ + "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x1c /* PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ + +#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH0 0xFF800000 +#define CFG_FLASH1 0xFF000000 +#define CFG_FLASH2 0xFE800000 +#define CFG_FLASH3 0xFE000000 +#define CFG_USB 0xF0000000 + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03050200 +#define CFG_EBC_PB0CR (CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x03050200 +#define CFG_EBC_PB1CR (CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x03050200 +#define CFG_EBC_PB2CR (CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ + +/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x03050200 +#define CFG_EBC_PB3CR (CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ + +/* Memory Bank 7 (USB controller) initialization */ +#define CFG_EBC_PB7AP 0x02015000 +#define CFG_EBC_PB7CR (CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 } + +#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h new file mode 100644 index 0000000..ed1893f --- /dev/null +++ b/include/configs/pb1x00.h @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for the dbau1x00 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_PB1X00 1 +#define CONFIG_AU1X00 1 /* alchemy series cpu */ + +#ifdef CONFIG_PB1000 +#define CONFIG_AU1000 1 +#else +#ifdef CONFIG_PB1100 +#define CONFIG_AU1100 1 +#else +#ifdef CONFIG_PB1500 +#define CONFIG_AU1500 1 +#else +#error "No valid board set" +#endif +#endif +#endif + +#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ + +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ + +#define CONFIG_BAUDRATE 115200 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "panic=1\0" \ + "bootfile=/vmlinux.img\0" \ + "load=tftp 80500000 ${u-boot}\0" \ + "" +/* Boot from NFS root */ +#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Pb1x00 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ + +#define CFG_MALLOC_LEN 128*1024 + +#define CFG_BOOTPARAMS_LEN 128*1024 + +#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ + +#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ + +#define CFG_LOAD_ADDR 0x81000000 /* default load address */ + +#define CFG_MEMTEST_START 0x80100000 +#undef CFG_MEMTEST_START +#define CFG_MEMTEST_START 0x80200000 +#define CFG_MEMTEST_END 0x83800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ + +#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +#define CFG_INIT_SP_OFFSET 0x4000000 + +/* We boot from this flash, selected with dip switch */ +#define CFG_FLASH_BASE PHYS_FLASH_2 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_NOWHERE 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR 0xB0030000 +#define CFG_ENV_SIZE 0x10000 + +#define CONFIG_FLASH_16BIT + +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_NET_MULTI + +#define CONFIG_MEMSIZE_IN_BYTES + + +/*---USB -------------------------------------------*/ +#if 0 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#else +#define ADD_USB_CMD 0 +#endif + +/*---ATA PCMCIA ------------------------------------*/ +#if 0 +#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ +#define CFG_PCMCIA_MEM_ADDR 0x20000000 +#define CONFIG_PCMCIA_SLOT_A + +#define CONFIG_ATAPI 1 +#define CONFIG_MAC_PARTITION 1 + +/* We run CF in "true ide" mode or a harddrive via pcmcia */ +#define CONFIG_IDE_PCMCIA 1 + +/* We only support one slot for now */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 8 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET 0 + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +#endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_ICACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 + +#define CONFIG_COMMANDS \ + (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \ + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \ + CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \ + CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD) +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h new file mode 100644 index 0000000..73aa3a8 --- /dev/null +++ b/include/configs/pcu_e.h @@ -0,0 +1,539 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Workaround for layout bug on prototype board + */ +#define PCU_E_WITH_SWAPPED_CS 1 + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ +#define CONFIG_MPC860T 1 +#define CONFIG_PCU_E 1 /* ...on a PCU E board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ + +#define CONFIG_BAUDRATE 9600 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_SPI /* enable SPI driver */ +#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + + +/* ---------------------------------------------------------------- + * Offset to initial SPI buffers in DPRAM (used if the environment + * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to + * use at an early stage. It is used between the two initialization + * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it + * far enough from the start of the data area (as well as from the + * stack pointer). + * ---------------------------------------------------------------- */ +#define CFG_SPI_INIT_OFFSET 0xB00 + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +#define CONFIG_BOOTP_MASK \ + ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ + +/* Ethernet hardware configuration done using port pins */ +#define CFG_PB_ETH_RESET 0x00000020 /* PB 26 */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ +#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ +#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ +#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */ +#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */ +#else /* XXX */ +#define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */ +#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ +#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */ +#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */ +#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */ +#endif /* XXX */ + +/* Ethernet settings: + * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex + */ +#define CFG_ETH_MDDIS_VALUE 0 +#define CFG_ETH_CFG1_VALUE 1 +#define CFG_ETH_CFG2_VALUE 1 +#define CFG_ETH_CFG3_VALUE 1 + +/* PUMA configuration */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define CFG_PB_PUMA_PROG 0x00000010 /* PB 27 */ +#else /* XXX */ +#define CFG_PA_PUMA_PROG 0x4000 /* PA 1 */ +#endif /* XXX */ +#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */ +#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFE000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Address accessed to reset the board - must not be mapped/assigned + */ +#define CFG_RESET_ADDRESS 0xFEFFFFFF + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +/* this is an ugly hack needed because of the silly non-constant address map */ +#define CFG_FLASH_BASE (0-flash_info[0].size-flash_info[1].size) + +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 160 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ + +#if 0 +/* Start port with environment in flash; switch to SPI EEPROM later */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ +#define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */ +#define CFG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ +#else +/* Final version: environment in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_I2C_EEPROM_ADDR 0 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_ENV_OFFSET 1024 +#define CFG_ENV_SIZE 1024 +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * External Arbitration max. priority (7), + * Debug pins configuration '11', + * Asynchronous external master enable. + */ +/* => 0x70600200 */ +#define CFG_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit, set PLL multiplication factor ! + */ +/* 0x00004080 */ +#define CFG_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */ +#define CFG_PLPRCR \ + ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ + /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ + PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ + ) + +#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*50000000) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + * + * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz + */ +#define SCCR_MASK SCCR_EBDF11 +/* 0x01800000 */ +#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ + SCCR_RTDIV | SCCR_RTSEL | \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + SCCR_EBDF00 | SCCR_DFSYNC00 | \ + SCCR_DFBRG00 | SCCR_DFNL000 | \ + SCCR_DFNH000 | SCCR_DFLCD100 | \ + SCCR_DFALCD01) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + * + * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!! + * + * Don't expect the "date" command to work without a 32kHz clock input! + */ +/* 0x00C3 => 0x0003 */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration Register 19-4 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0x0000 + +/*----------------------------------------------------------------------- + * RMDS - RISC Microcode Development Support Control Register + *----------------------------------------------------------------------- + */ +#define CFG_RMDS 0 + +/*----------------------------------------------------------------------- + * + * Interrupt Levels + *----------------------------------------------------------------------- + */ +#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) - second Flash bank optional + */ + +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */ +#else /* XXX */ +#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */ +#endif /* XXX */ + +/* + * used to re-map FLASH: restrict access enough but not too much to + * meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ + +/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR) + +#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \ + CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ + CFG_OR_TIMING_FLASH) +/* 16 bit, bank valid */ +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define CFG_OR6_REMAP CFG_OR0_REMAP +#define CFG_OR6_PRELIM CFG_OR0_PRELIM +#define CFG_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#else /* XXX */ +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#endif /* XXX */ + +/* + * BR2/OR2: SDRAM + * + * Multiplexed addresses, GPL5 output to GPL5_A (don't care) + */ +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */ +#else /* XXX */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */ +#endif /* XXX */ +#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */ +#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */ + +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* XXX */ +#define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#endif /* XXX */ + +/* + * BR3/OR3: CAN Controller + * BR3: 0x10000401 OR3: 0xffff818a + */ +#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */ +#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */ +#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR) + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define CFG_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) +#define CFG_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) +#else /* XXX */ +#define CFG_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) +#define CFG_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) +#endif /* XXX */ + +/* + * BR4/OR4: PUMA Config + * + * Memory controller will be used in 2 modes: + * + * - "read" mode: + * BR4: 0x10100801 OR4: 0xffff8530 + * - "load" mode (chip select on UPM B): + * BR4: 0x101008c1 OR4: 0xffff8630 + * + * Default initialization is in "read" mode + */ +#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ +#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ +#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK) +#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK) + +#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ + BR_PS_16 | BR_MS_UPMB | BR_V) +#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) + +#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) +#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define CFG_BR3_PRELIM PUMA_CONF_BR_READ +#define CFG_OR3_PRELIM PUMA_CONF_OR_READ +#else /* XXX */ +#define CFG_BR4_PRELIM PUMA_CONF_BR_READ +#define CFG_OR4_PRELIM PUMA_CONF_OR_READ +#endif /* XXX */ + +/* + * BR5/OR5: PUMA: SMA Bus 8 Bit + * BR5: 0x10200401 OR5: 0xffe0010a + */ +#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ +#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ +#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define CFG_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) +#define CFG_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) +#else /* XXX */ +#define CFG_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) +#define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) +#endif /* XXX */ + +/* + * BR6/OR6: PUMA: SMA Bus 16 Bit + * BR6: 0x10600801 OR6: 0xffe0010a + */ +#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ +#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ +#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) + +#if PCU_E_WITH_SWAPPED_CS /* XXX */ +#define CFG_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) +#define CFG_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) +#else /* XXX */ +#define CFG_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) +#define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) +#endif /* XXX */ + +/* + * BR7/OR7: PUMA: external Flash + * BR7: 0x10a00801 OR7: 0xfe00010a + */ +#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ +#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ +#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) + +#define CFG_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) +#define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MPTPR 0x0200 + +/* + * MAMR settings for SDRAM + * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10, + * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X + * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X + */ +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 0x30 /* = 48 */ + +#define CFG_MAMR ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ + MAMR_AMA_TYPE_1 | \ + MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | \ + MAMR_WLFA_1X | \ + MAMR_TLFA_8X ) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h new file mode 100644 index 0000000..fefdb3c --- /dev/null +++ b/include/configs/pf5200.h @@ -0,0 +1,399 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * (c) 2005 esd gmbh Hannover + * + * + * from IceCube.h file + * by Reinhard Arlt reinhard.arlt@esd-electronics.com + * + *************************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_ICECUBE 1 /* ... on IceCube board */ +#define CONFIG_PF5200 1 /* ... on PF5200 board */ +#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#if 0 /* test-only */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#else +#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ +#endif +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_MII 1 +#if 0 /* test-only !!! */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 +#endif + +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MPC5100 */ + +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* USB */ +#if 0 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + ADD_PCI_CMD ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 +#endif +#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT08 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Welcome to ParaFinder pf5200;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ + "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ + "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ + "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ + "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ + "loadaddr=01000000\0" \ + "serverip=192.168.2.99\0" \ + "gatewayip=10.0.0.79\0" \ + "user=mu\0" \ + "target=pf5200.esd\0" \ + "script=pf5200.bat\0" \ + "image=/tftpboot/vxWorks_pf5200\0" \ + "ipaddr=10.0.13.196\0" \ + "netmask=255.255.0.0\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_vxworks0" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 86000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CFG_I2C_MULTI_EEPROMS 1 +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_SIZE 0x02000000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 512 + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* + * Environment settings + */ +#if 1 /* test-only */ +#define CFG_ENV_IS_IN_FLASH 0 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ + /* total size of a CAT24WC32 is 8192 bytes */ +#define CONFIG_ENV_OVERWRITE 1 +#endif + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_UDP_CHECKSUM 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x01052444 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x0004DD00 + +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS1_START 0xfd000000 +#define CFG_CS1_SIZE 0x00010000 +#define CFG_CS1_CFG 0x10101410 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +/*----------------------------------------------------------------------- + * CPLD stuff + */ +#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ + +/* CPLD program pin configuration */ +#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ +#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ +#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ +#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ + +#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ +#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ +#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ + +#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00) +#define JTAG_GPIO_CFG_SET 0x00000000 +#define JTAG_GPIO_CFG_RESET 0x00F00000 + +#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04) +#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ +#define JTAG_GPIO_TMS_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ +#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00) +#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ +#define JTAG_GPIO_TCK_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08) +#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ +#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00) +#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ +#define JTAG_GPIO_TDI_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08) +#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ +#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 + +#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04) +#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ +#define JTAG_GPIO_TDO_EN_RESET 0x00000000 +#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C) +#define JTAG_GPIO_TDO_DDR_SET 0x00000000 +#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h new file mode 100644 index 0000000..a6c2371 --- /dev/null +++ b/include/configs/pleb2.h @@ -0,0 +1,244 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuration settings for the PLEB 2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA255 CPU */ +#define CONFIG_PLEB2 1 /* on an PLEB2 Board */ +#undef CONFIG_LCD +#undef CONFIG_MMC +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* None - PLEB 2 doesn't have any of this. + #define CONFIG_DRIVER_LAN91C96 + #define CONFIG_LAN91C96_BASE 0x0C000000 */ + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.0.21 +#define CONFIG_SERVERIP 192.168.0.250 +#define CONFIG_BOOTCOMMAND "bootm 40000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200" + +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa2000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */ + +/* Not entirely sure about this - DS/CHC */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ + +#define CFG_DRAM_BASE PHYS_SDRAM_1 +#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00000000 /* Don't set anything */ +#define CFG_GPSR1_VAL 0x00000080 +#define CFG_GPSR2_VAL 0x00000000 + +#define CFG_GPCR0_VAL 0x00000000 /* Don't clear anything */ +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 + +#define CFG_GPDR0_VAL 0x00000000 +#define CFG_GPDR1_VAL 0x000007C3 +#define CFG_GPDR2_VAL 0x00000000 + +/* Edge detect registers (these are set by the kernel) */ +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 + +#define CFG_GAFR0_L_VAL 0x00000000 +#define CFG_GAFR0_U_VAL 0x00000000 +#define CFG_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */ +#define CFG_GAFR1_U_VAL 0x00000000 +#define CFG_GAFR2_L_VAL 0x00000000 +#define CFG_GAFR2_U_VAL 0x00000000 + +#define CFG_PSSR_VAL 0x20 +#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ +#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ +#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */ +#define CFG_MSC1_VAL 0x00000000 +#define CFG_MSC2_VAL 0x00000000 + +#define CFG_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM. + tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */ + +#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual */ + /* bits set in lowlevel_init.S */ +#define CFG_MDMRS_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 /* Hangover from Lubbock. + Needs calculating. (DS/CHC) */ +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +/* FIXME */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash protection */ +#define CFG_FLASH_PROTECTION 1 + +/* FIXME */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x20000 + +/* Option added to get around byte ordering issues in the flash driver */ +#define CFG_LITTLE_ENDIAN 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h new file mode 100644 index 0000000..7579222 --- /dev/null +++ b/include/configs/ppmc8260.h @@ -0,0 +1,1006 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * Configuation settings for the WindRiver PPMC8260 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/***************************************************************************** + * + * These settings must match the way _your_ board is set up + * + *****************************************************************************/ + +/* What is the oscillator's (UX2) frequency in Hz? */ +#define CONFIG_8260_CLKIN (66 * 1000 * 1000) + +/*----------------------------------------------------------------------- + * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual + *----------------------------------------------------------------------- + * What should MODCK_H be? It is dependent on the oscillator + * frequency, MODCK[1-3], and desired CPM and core frequencies. + * Here are some example values (all frequencies are in MHz): + * + * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 + * ------- ---------- --- --- ---- ----- ----- ----- + * 0x2 0x2 33 133 133 Close Open Close + * 0x2 0x3 33 133 166 Close Open Open + * 0x2 0x4 33 133 200 Open Close Close + * 0x2 0x5 33 133 233 Open Close Open + * 0x2 0x6 33 133 266 Open Open Close + * + * 0x5 0x5 66 133 133 Open Close Open + * 0x5 0x6 66 133 166 Open Open Close + * 0x5 0x7 66 133 200 Open Open Open + * 0x6 0x0 66 133 233 Close Close Close + * 0x6 0x1 66 133 266 Close Close Open + * 0x6 0x2 66 133 300 Close Open Close + */ +#define CFG_PPMC_MODCK_H 0x05 + +/* Define this if you want to boot from 0x00000100. If you don't define + * this, you will need to program the bootloader to 0xfff00000, and + * get the hardware reset config words at 0xfe000000. The simplest + * way to do that is to program the bootloader at both addresses. + * It is suggested that you just let U-Boot live at 0x00000000. + */ +#define CFG_PPMC_BOOT_LOW 1 + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk + * The main FLASH is whichever is connected to *CS0. U-Boot expects + * this to be the SIMM. + */ +#define CFG_FLASH0_BASE 0xFE000000 +#define CFG_FLASH0_SIZE 16 + +/* What should be the base address of the first SDRAM DIMM and how big is + * it (in Mbytes)? +*/ +#define CFG_SDRAM0_BASE 0x00000000 +#define CFG_SDRAM0_SIZE 128 + +/* What should be the base address of the second SDRAM DIMM and how big is + * it (in Mbytes)? +*/ +#define CFG_SDRAM1_BASE 0x08000000 +#define CFG_SDRAM1_SIZE 128 + +/* What should be the base address of the on board SDRAM and how big is + * it (in Mbytes)? +*/ +#define CFG_SDRAM2_BASE 0x38000000 +#define CFG_SDRAM2_SIZE 16 + +/* What should be the base address of the MAILBOX and how big is it + * (in Bytes) + * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000 + */ +#define CFG_MAILBOX_BASE 0x32000000 +#define CFG_MAILBOX_SIZE 8192 + +/* What is the base address of the I/O select lines and how big is it + * (In Mbytes)? + */ + +#define CFG_IOSELECT_BASE 0xE0000000 +#define CFG_IOSELECT_SIZE 32 + + +/* What should be the base address of the LEDs and switch S0? + * If you don't want them enabled, don't define this. + */ +#define CFG_LED_BASE 0xF1000000 + +/* + * PPMC8260 with 256 16 MB DIMM: + * + * 0x0000 0000 Exception Vector code, 8k + * : + * 0x0000 1FFF + * 0x0000 2000 Free for Application Use + * : + * : + * + * : + * : + * 0x0FF5 FF30 Monitor Stack (Growing downward) + * Monitor Stack Buffer (0x80) + * 0x0FF5 FFB0 Board Info Data + * 0x0FF6 0000 Malloc Arena + * : CFG_ENV_SECT_SIZE, 256k + * : CFG_MALLOC_LEN, 128k + * 0x0FFC 0000 RAM Copy of Monitor Code + * : CFG_MONITOR_LEN, 256k + * 0x0FFF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 + */ + + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere. + * The console can be on SMC1 or SMC2 + */ +#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on neither */ +#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ + +#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +/* + * Port pins used for bit-banged MII communictions (if applicable). + */ +#define MDIO_PORT 2 /* Port C */ +#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +#define MDIO_READ ((iop->pdat & 0x00400000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + +#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + +#define MIIDELAY udelay(1) + + +/* Define this to reserve an entire FLASH sector (256 KB) for + * environment variables. Otherwise, the environment will be + * put in the same sector as U-Boot, and changing variables + * will erase U-Boot temporarily + */ +#define CFG_ENV_IN_OWN_SECT 1 + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* What should the console's baud rate be? */ +#define CONFIG_BAUDRATE 9600 + +/* Ethernet MAC address */ + +#define CONFIG_ETHADDR 00:a0:1e:90:2b:00 + +/* Define this to set the last octet of the ethernet address + * from the DS0-DS7 switch and light the leds with the result + * The DS0-DS7 switch and the leds are backwards with respect + * to each other. DS7 is on the board edge side of both the + * led strip and the DS0-DS7 switch. + */ +#define CONFIG_MISC_INIT_R + +/* Set to a positive value to delay for running BOOTCOMMAND */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#if 0 +/* Be selective on what keys can delay or stop the autoboot process + * To stop use: " " + */ +# define CONFIG_AUTOBOOT_KEYED +# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" +# define CONFIG_AUTOBOOT_STOP_STR " " +# undef CONFIG_AUTOBOOT_DELAY_STR +# define DEBUG_BOOTKEYS 0 +#endif + +/* Define a command string that is automatically executed when no character + * is read on the console interface withing "Boot Delay" after reset. + */ +#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ +#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ + +#ifdef CONFIG_BOOT_ROOT_INITRD +#define CONFIG_BOOTCOMMAND \ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/ram0 rw " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" +#endif /* CONFIG_BOOT_ROOT_INITRD */ + +#ifdef CONFIG_BOOT_ROOT_NFS +#define CONFIG_BOOTCOMMAND \ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" +#endif /* CONFIG_BOOT_ROOT_NFS */ + +/* Add support for a few extra bootp options like: + * - File size + * - DNS + */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS) + +/* undef this to save memory */ +#define CFG_LONGHELP + +/* Monitor Command Prompt */ +#define CFG_PROMPT "=> " + +/* What U-Boot subsytems do you want enabled? */ +#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ + CFG_CMD_ELF | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ECHO | \ + CFG_CMD_REGINFO | \ + CFG_CMD_MEMTEST | \ + CFG_CMD_MII | \ + CFG_CMD_IMMAP) + + +/* Where do the internal registers live? */ +#define CFG_IMMR 0xf0000000 + +/***************************************************************************** + * + * You should not have to modify any of the following settings + * + *****************************************************************************/ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) + +#define CFG_MAXARGS 32 /* max number of command args */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x140000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ + /* the exception vector table */ + /* to the end of the DRAM */ + /* less monitor and malloc area */ +#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ +#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ + + CFG_MALLOC_LEN \ + + CFG_ENV_SECT_SIZE \ + + CFG_STACK_USAGE ) + +#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ + - CFG_MEM_END_USAGE ) + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) +/* + * Attention: This is board specific + * - RX clk is CLK11 + * - TX clk is CLK12 + */ +#define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\ + CMXSCR_TS1CS_CLK12) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) +/* + * Attention: this is board-specific + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers (see 28-13) + * - Enable Full Duplex in FSMR + */ +#define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#endif /* CONFIG_ETHER_INDEX */ + +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE +#define CFG_SDRAM_BASE CFG_SDRAM0_BASE +#define CFG_SDRAM_SIZE (CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE) + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + */ +#if defined(CFG_PPMC_BOOT_LOW) +# define CFG_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) +#else +# define CFG_PPMC_HRCW_BOOT_FLAGS (0) +#endif /* defined(CFG_PPMC_BOOT_LOW) */ + +/* get the HRCW ISB field from CFG_IMMR */ +#define CFG_PPMC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ + ((CFG_IMMR & 0x01000000) >> 7) | \ + ((CFG_IMMR & 0x00100000) >> 4) ) + +#define CFG_HRCW_MASTER ( HRCW_EBM | \ + HRCW_BPS11 | \ + HRCW_L2CPC10 | \ + HRCW_DPPC00 | \ + CFG_PPMC_HRCW_IMMR | \ + HRCW_MMR00 | \ + HRCW_LBPC00 | \ + HRCW_APPC10 | \ + HRCW_CS10PC00 | \ + (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \ + CFG_PPMC_HRCW_BOOT_FLAGS ) + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CFG_RAMBOOT is platform dependent. + */ +#define CFG_MONITOR_BASE CFG_FLASH0_BASE + +#ifndef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE 0x0ff80000 +#endif + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + + +#ifndef CFG_RAMBOOT + +# define CFG_ENV_IS_IN_FLASH 1 +# ifdef CFG_ENV_IN_OWN_SECT +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +# define CFG_ENV_SECT_SIZE 0x40000 +# else +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) +# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +# define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ +# endif /* CFG_ENV_IN_OWN_SECT */ + +#else +# define CFG_ENV_IS_IN_FLASH 1 +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) +#define CFG_ENV_SIZE 0x1000 +# define CFG_ENV_SECT_SIZE 0x40000 +#endif /* CFG_RAMBOOT */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE |\ + HID0_DCE |\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) + +#define CFG_HID0_FINAL (HID0_ICE |\ + HID0_IFEM |\ + HID0_ABE |\ + HID0_EMCP) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register + *----------------------------------------------------------------------- + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR (BCR_EBM |\ + 0x30000000) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + * Ref Section 4.3.2.6 page 4-31 + *----------------------------------------------------------------------- + */ + +#define CFG_SIUMCR (SIUMCR_ESE |\ + SIUMCR_DPPC00 |\ + SIUMCR_L2CPC10 |\ + SIUMCR_LBPC00 |\ + SIUMCR_APPC10 |\ + SIUMCR_CS10PC00 |\ + SIUMCR_BCTLC00 |\ + SIUMCR_MMR00) + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#define CFG_SYPCR (SYPCR_SWTC |\ + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP) + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC |\ + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS |\ + PISCR_PTF |\ + PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#define CFG_SCCR 0 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Initialize Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) * + * 1 unused + * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB) + * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB) + * 4 Local SDRAM 32 bit SDRAM (on board - 16MB) + * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB) + * 6 60x GPCM 8 bit FLASH (on board - 2MB) * + * 7 60x GPCM 8 bit LEDs, switches + * + * (*) This configuration requires the PPMC8260 be configured + * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to + * the on board FLASH. In other words, JP24 should have + * pins 1 and 2 jumpered and pins 3 and 4 jumpered. + * + */ + +/*----------------------------------------------------------------------- + * BR0,BR1 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR0,OR1 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 0,1 - FLASH SIMM + * + * This expects the FLASH SIMM to be connected to *CS0 + * It consists of 4 AM29F080B parts. + * + * Note: For the 4 MB SIMM, *CS1 is unused. + */ + +/* BR0 is configured as follows: + * + * - Base address of 0xFE000000 + * - 32 bit port size + * - Data errors checking is disabled + * - Read and write access + * - GPCM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +/* OR0 is configured as follows: + * + * - 32 MB + * - *BCTL0 is asserted upon access to the current memory bank + * - *CW / *WE are negated a quarter of a clock earlier + * - *CS is output at the same time as the address lines + * - Uses a clock cycle length of 5 + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + +/*----------------------------------------------------------------------- + * BR2,BR3 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR2,OR3 - Option Register + * Ref: Section 10.3.2 on page 10-16 + *----------------------------------------------------------------------- + */ + +/* + * Bank 2,3 - 128 MB SDRAM DIMM + */ + +/* With a 128 MB DIMM, the BR2 is configured as follows: + * + * - Base address of 0x00000000/0x08000000 + * - 64 bit port size (60x bus only) + * - Data errors checking is disabled + * - Read and write access + * - SDRAM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_BR3_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +/* With a 128 MB DIMM, the OR2 is configured as follows: + * + * - 128 MB + * - 4 internal banks per device + * - Row start address bit is A8 with PSDMR[PBI] = 0 + * - 13 row address lines + * - Back-to-back page mode + * - Internal bank interleaving within save device enabled + */ + +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CFG_OR3_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + + +/*----------------------------------------------------------------------- + * PSDMR - 60x Bus SDRAM Mode Register + * Ref: Section 10.3.3 on page 10-21 + *----------------------------------------------------------------------- + */ + +/* With a 128 MB DIMM, the PSDMR is configured as follows: + * + * - Page Based Interleaving, + * - Refresh Enable, + * - Normal Operation + * - Address Multiplexing where A5 is output on A14 pin + * (A6 on A15, and so on), + * - use address pins A13-A15 as bank select, + * - A9 is output on SDA10 during an ACTIVATE command, + * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, + * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 3 clocks, + * - earliest timing for READ/WRITE command after ACTIVATE command is + * 2 clocks, + * - earliest timing for PRECHARGE after last data was read is 1 clock, + * - earliest timing for PRECHARGE after last data was written is 1 clock, + * - External Address Multiplexing enabled + * - CAS Latency is 2. + */ +#define CFG_PSDMR (PSDMR_RFEN |\ + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) + + +#define CFG_PSRT 0x0e +#define CFG_MPTPR MPTPR_PTP_DIV32 + + +/*----------------------------------------------------------------------- + * BR4 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR4 - Option Register + * Ref: Section 10.3.2 on page 10-16 + *----------------------------------------------------------------------- + */ + +/* + * Bank 4 - On board SDRAM + * + */ +/* With 16 MB of onboard SDRAM BR4 is configured as follows + * + * - Base address 0x38000000 + * - 32 bit port size + * - Data error checking disabled + * - Read/Write access + * - SDRAM local bus + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + * + */ + +#define CFG_BR4_PRELIM ((CFG_SDRAM2_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_DECC_NONE |\ + BRx_MS_SDRAM_L |\ + BRx_V) + +/* + * With 16MB SDRAM, OR4 is configured as follows + * - 4 internal banks per device + * - Row start address bit is A10 with LSDMR[PBI] = 0 + * - 12 row address lines + * - Back-to-back page mode + * - Internal bank interleaving within save device enabled + */ + +#define CFG_OR4_PRELIM (MEG_TO_AM(CFG_SDRAM2_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A10 |\ + ORxS_NUMR_12) + + +/*----------------------------------------------------------------------- + * LSDMR - Local Bus SDRAM Mode Register + * Ref: Section 10.3.4 on page 10-24 + *----------------------------------------------------------------------- + */ + +/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows: + * + * - Page Based Interleaving, + * - Refresh Enable, + * - Normal Operation + * - Address Multiplexing where A5 is output on A13 pin + * (A6 on A15, and so on), + * - use address pins A15-A17 as bank select, + * - A11 is output on SDA10 during an ACTIVATE command, + * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, + * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 2 clocks, + * - earliest timing for READ/WRITE command after ACTIVATE command is + * 2 clocks, + * - SDRAM burst length is 8 + * - earliest timing for PRECHARGE after last data was read is 1 clock, + * - earliest timing for PRECHARGE after last data was written is 1 clock, + * - External Address Multiplexing disabled + * - CAS Latency is 2. + */ +#define CFG_LSDMR (PSDMR_RFEN |\ + PSDMR_SDAM_A13_IS_A5 |\ + PSDMR_BSMA_A15_A17 |\ + PSDMR_SDA10_PBI0_A11 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + +#define CFG_LSRT 0x0e + +/*----------------------------------------------------------------------- + * BR5 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR5 - Option Register + * Ref: Section 10.3.2 on page 10-16 + *----------------------------------------------------------------------- + */ + +/* + * Bank 5 EEProm and Mailbox + * + * The EEPROM and mailbox live on the same chip select. + * the eeprom is selected if the MSb of the address is set and the mailbox is + * selected if the MSb of the address is clear. + * + */ + +/* BR5 is configured as follows: + * + * - Base address of 0x32000000/0xF2000000 + * - 8 bit + * - Data error checking disabled + * - Read/Write access + * - GPCM 60x Bus + * - SDRAM local bus + * - No data pipelining is done + * - Valid + */ + +#define CFG_BR5_PRELIM ((CFG_MAILBOX_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_DECC_NONE |\ + BRx_MS_GPCM_P |\ + BRx_V) +/* OR5 is configured as follows + * - buffer control enabled + * - chip select negated normally + * - CS output 1/2 clock after address + * - 15 wait states + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ + +#define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_15_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + +/*----------------------------------------------------------------------- + * BR6 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR6 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 6 - I/O select + * + */ + +/* BR6 is configured as follows: + * + * - Base address of 0xE0000000 + * - 16 bit port size + * - Data errors checking is disabled + * - Read and write access + * - GPCM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR6_PRELIM ((CFG_IOSELECT_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +/* OR6 is configured as follows + * - buffer control enabled + * - chip select negated normally + * - CS output 1/2 clock after address + * - 15 wait states + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ + +#define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\ + ORxG_ACS_DIV2 |\ + ORxG_SCY_15_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + + +/*----------------------------------------------------------------------- + * BR7 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR7 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 7 - LEDs and switches + * + * LEDs are at 0x00001 (write only) + * switches are at 0x00001 (read only) + */ +#ifdef CFG_LED_BASE + +/* BR7 is configured as follows: + * + * - Base address of 0xA0000000 + * - 8 bit port size + * - Data errors checking is disabled + * - Read and write access + * - GPCM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_DECC_NONE |\ + BRx_MS_GPCM_P |\ + BRx_V) + +/* OR7 is configured as follows: + * + * - 1 byte + * - *BCTL0 is asserted upon access to the current memory bank + * - *CW / *WE are negated a quarter of a clock earlier + * - *CS is output at the same time as the address lines + * - Uses a clock cycle length of 15 + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ +#define CFG_OR7_PRELIM (ORxG_AM_MSK |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_15_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) +#endif /* CFG_LED_BASE */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/purple.h b/include/configs/purple.h new file mode 100644 index 0000000..2ecb7fb --- /dev/null +++ b/include/configs/purple.h @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for the PURPLE board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 1 /* MIPS 5Kc CPU core */ +#define CONFIG_PURPLE 1 /* on a PURPLE Board */ + +#define CPU_CLOCK_RATE 125000000 /* 125 MHz clock for the MIPS core */ +#define ASC_CLOCK_RATE 62500000 /* 62.5 MHz ASC clock */ + +#define INFINEON_EBU_BOOTCFG 0xE0CC + +#define CONFIG_STACKSIZE (128 * 1024) + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BAUDRATE 19200 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off\0" \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "ethaddr=${ethaddr} " \ + "panic=1\0" \ + "flash_nfs=run nfsargs addip addmisc;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 80500000 ${bootfile};" \ + "run nfsargs addip addmisc;bootm\0" \ + "rootpath=/opt/eldk/mips_5KC\0" \ + "bootfile=/tftpboot/purple/uImage\0" \ + "kernel_addr=B0040000\0" \ + "ramdisk_addr=B0100000\0" \ + "u-boot=/tftpboot/purple/u-boot.bin\0" \ + "load=tftp 80500000 ${u-boot}\0" \ + "update=protect off 1:0-4;era 1:0-4;" \ + "cp.b 80500000 B0000000 ${filesize}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF) +#include + +#define CFG_SDRAM_BASE 0x80000000 + +#define CFG_INIT_SP_OFFSET 0x400000 + +#define CFG_MALLOC_LEN 128*1024 + +#define CFG_BOOTPARAMS_LEN 128*1024 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "PURPLE # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_HZ (CPU_CLOCK_RATE/2) +#define CFG_MAXARGS 16 /* max number of command args*/ + +#define CFG_LOAD_ADDR 0x80500000 /* default load address */ + +#define CFG_MEMTEST_START 0x80200000 +#define CFG_MEMTEST_END 0x80800000 + +#define CONFIG_MISC_INIT_R + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (35) /* max number of sectors on one chip */ + +#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */ + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (6 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (6 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR 0xB0008000 +#define CFG_ENV_SIZE 0x4000 + +#define CONFIG_FLASH_32BIT +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_PLB2800_ETHER +#define CONFIG_NET_MULTI + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_ICACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 + +/* + * Temporary buffer for serial data until the real serial driver + * is initialised (memtest will destroy this buffer) + */ +#define CFG_SCONSOLE_ADDR (CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET - \ + CFG_DCACHE_SIZE / 2) +#define CFG_SCONSOLE_SIZE (CFG_DCACHE_SIZE / 4) + +#endif /* __CONFIG_H */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h new file mode 100644 index 0000000..e5e2772 --- /dev/null +++ b/include/configs/pxa255_idp.h @@ -0,0 +1,338 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copied from lubbock.h + * + * (C) Copyright 2004 + * BEC Systems + * Cliff Brake + * Configuation settings for the Accelent/Vibren PXA255 IDP + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL /* undef for developing */ + +/* + * define the following to enable debug blinks. A debug blink function + * must be defined in memsetup.S + */ +#undef DEBUG_BLINK_ENABLE +#undef DEBUG_BLINKC_ENABLE + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ + +#undef CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_SHARP_LM8V31 +#endif + +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * PXA250 IDP memory map information + */ + +#define IDP_CS5_ETH_OFFSET 0x03400000 + + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) +#define CONFIG_SMC_USE_32_BIT 1 +/* #define CONFIG_SMC_USE_IOFUNCS */ + +/* the following has to be set high -- suspect something is wrong with + * with the tftp timeout routines. FIXME!!! + */ +#define CONFIG_NET_RETRY_COUNT 100 + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "bootm 40000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG + +/* + * Current memory map for Vibren supplied Linux images: + * + * Flash: + * 0 - 0x3ffff (size = 0x40000): bootloader + * 0x40000 - 0x13ffff (size = 0x100000): kernel + * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs + * + * RAM: + * 0xa0008000 - kernel is loaded + * 0xa3000000 - Uboot runs (48MB into RAM) + * + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "prog_boot_mmc=" \ + "mw.b 0xa0000000 0xff 0x40000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0000000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x3ffff; " \ + "erase 0x0 0x3ffff; " \ + "cp.b 0xa0000000 0x0 0x40000; " \ + "reset;" \ + "fi\0" \ + "prog_uzImage_mmc=" \ + "mw.b 0xa0000000 0xff 0x100000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0000000 uzImage; " \ + "then " \ + "protect off 0x40000 0xfffff; " \ + "erase 0x40000 0xfffff; " \ + "cp.b 0xa0000000 0x40000 0x100000; " \ + "fi\0" \ + "prog_jffs_mmc=" \ + "mw.b 0xa0000000 0xff 0x1e00000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0000000 root.jffs; " \ + "then " \ + "protect off 0x140000 0x1f3ffff; " \ + "erase 0x140000 0x1f3ffff; " \ + "cp.b 0xa0000000 0x140000 0x1e00000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa1000000 uzImage && " \ + "then " \ + "bootm 0xa1000000; " \ + "fi\0" \ + "prog_boot_net=" \ + "mw.b 0xa0000000 0xff 0x100000; " \ + "if bootp 0xa0000000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x3ffff; " \ + "erase 0x0 0x3ffff; " \ + "cp.b 0xa0000000 0x0 0x40000; " \ + "reset; " \ + "fi\0" \ + "prog_uzImage_net=" \ + "mw.b 0xa0000000 0xff 0x100000; " \ + "if bootp 0xa0000000 uzImage; " \ + "then " \ + "protect off 0x40000 0xfffff; " \ + "erase 0x40000 0xfffff; " \ + "cp.b 0xa0000000 0x40000 0x100000; " \ + "fi\0" \ + "prog_jffs_net=" \ + "mw.b 0xa0000000 0xff 0x1e00000; " \ + "if bootp 0xa0000000 root.jffs; " \ + "then " \ + "protect off 0x140000 0x1f3ffff; " \ + "erase 0x140000 0x1f3ffff; " \ + "cp.b 0xa0000000 0x140000 0x1e00000; " \ + "fi\0" + + +/* "erase_env=" */ +/* "protect off" */ + + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa0800000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ + +#define RTC 1 /* enable 32KHz osc */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ + +#define CFG_GAFR0_L_VAL 0x80001005 +#define CFG_GAFR0_U_VAL 0xa5128012 +#define CFG_GAFR1_L_VAL 0x699a9558 +#define CFG_GAFR1_U_VAL 0xaaa5aa6a +#define CFG_GAFR2_L_VAL 0xaaaaaaaa +#define CFG_GAFR2_U_VAL 0x2 +#define CFG_GPCR0_VAL 0x1800400 +#define CFG_GPCR1_VAL 0x0 +#define CFG_GPCR2_VAL 0x0 +#define CFG_GPDR0_VAL 0xc1818440 +#define CFG_GPDR1_VAL 0xfcffab82 +#define CFG_GPDR2_VAL 0x1ffff +#define CFG_GPSR0_VAL 0x8000 +#define CFG_GPSR1_VAL 0x3f0002 +#define CFG_GPSR2_VAL 0x1c000 + +#define CFG_PSSR_VAL 0x20 + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x29DCA4D2 +#define CFG_MSC1_VAL 0x43AC494C +#define CFG_MSC2_VAL 0x39D449D4 +#define CFG_MDCNFG_VAL 0x090009C9 +#define CFG_MDREFR_VAL 0x0085C017 +#define CFG_MDMRS_VAL 0x00220022 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000003 +#define CFG_MCMEM0_VAL 0x00014405 +#define CFG_MCMEM1_VAL 0x00014405 +#define CFG_MCATT0_VAL 0x00014405 +#define CFG_MCATT1_VAL 0x00014405 +#define CFG_MCIO0_VAL 0x00014405 +#define CFG_MCIO1_VAL 0x00014405 + +/* + * FLASH and environment organization + */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x40000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* put cfg at end of flash for now */ +#define CFG_ENV_IS_IN_FLASH 1 + /* Addr of Environment Sector */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x40000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/quantum.h b/include/configs/quantum.h new file mode 100644 index 0000000..21ec5ac --- /dev/null +++ b/include/configs/quantum.h @@ -0,0 +1,446 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + * changes for 16M board + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#undef CONFIG_MPC860 +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */ +#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +/* default developmenmt environment */ + +#define CONFIG_ETHADDR 00:0B:17:00:00:00 + +#define CONFIG_IPADDR 10.10.69.10 +#define CONFIG_SERVERIP 10.10.69.49 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_HOSTNAME QUANTUM +#define CONFIG_ROOTPATH /opt/eldk/pcc_8xx + +#define CONFIG_BOOTARGS "root=/dev/ram rw" + +#define CONFIG_BOOTCOMMAND "bootm ff000000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serial#=12345\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" + +/* + * Select the more full-featured memory test (Barr embedded systems) + */ +#define CFG_ALT_MEMTEST + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + + +/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/ +#define CONFIG_RTC_M48T35A 1 + +#if 0 +#define CONFIG_WATCHDOG 1 /* watchdog enabled */ +#else +#undef CONFIG_WATCHDOG +#endif + +/* NVRAM and RTC */ +#define CFG_NVRAM_BASE_ADDR 0xFA000000 +#define CFG_NVRAM_SIZE 2048 + + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP ) + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR "system" +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00040000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFA200000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 + +#if 1 + #define CFG_FLASH_CFI_DRIVER +#else + #undef CFG_FLASH_CFI_DRIVER +#endif + + +#ifdef CFG_FLASH_CFI_DRIVER + #define CFG_FLASH_CFI 1 + #undef CFG_FLASH_USE_BUFFER_WRITE + #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#endif + +/*%%% #define CFG_FLASH_BASE 0xFFF00000 */ +#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE 0xFFF00000 +/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x00F40000 /* Offset of Environment Sector absolute address 0xfff40000*/ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* FPGA */ +#define CONFIG_MISC_INIT_R +#define CFG_FPGA_SPARTAN2 +#define CFG_FPGA_PROG_FEEDBACK + + +/*----------------------------------------------------------------------- + * Reset address + */ +#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_MLRC10) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ +#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ + +/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) + +/* + * BR1 and OR1 (SDRAM) + * + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ +#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000E00 + +#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */ +#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* RPXLITE mem setting */ +#define CFG_BR3_PRELIM 0xFA400001 /* FPGA */ +#define CFG_OR3_PRELIM 0xFFFF8910 + +#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ +#define CFG_OR4_PRELIM 0xFFFE0970 + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 20 + +/* + * Refresh clock Prescalar + */ +#define CFG_MPTPR MPTPR_PTP_DIV2 + +/* + * MAMR settings for SDRAM + */ + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * BCSRx + * + * Board Status and Control Registers + * + */ + +#define BCSR0 0xFA400000 +#define BCSR1 0xFA400001 +#define BCSR2 0xFA400002 +#define BCSR3 0xFA400003 + +#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ +#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ +#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ +#define BCSR0_COLTEST 0x20 +#define BCSR0_ETHLPBK 0x40 +#define BCSR0_ETHEN 0x80 + +#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ +#define BCSR1_PCVCTL6 0x02 +#define BCSR1_PCVCTL5 0x04 +#define BCSR1_PCVCTL4 0x08 +#define BCSR1_IPB5SEL 0x10 + +#define BCSR2_ENPA5HDR 0x08 /* USB Control */ +#define BCSR2_ENUSBCLK 0x10 +#define BCSR2_USBPWREN 0x20 +#define BCSR2_USBSPD 0x40 +#define BCSR2_USBSUSP 0x80 + +#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ +#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ +#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ +#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ +#define BCSR3_D27 0x10 /* Dip Switch settings */ +#define BCSR3_D26 0x20 +#define BCSR3_D25 0x40 +#define BCSR3_D24 0x80 + +#endif /* __CONFIG_H */ diff --git a/include/configs/rmu.h b/include/configs/rmu.h new file mode 100644 index 0000000..b319cf4 --- /dev/null +++ b/include/configs/rmu.h @@ -0,0 +1,420 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +/* + * High Level Configuration Options + * (easy to change) + */ + +#undef CONFIG_MPC860 +#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ +#define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */ +#define CONFIG_RMU 1 + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +/* Software (bit-bang) I2C driver configuration */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +/* M41T11 Serial Access Timekeeper(R) SRAM */ +#define CONFIG_RTC_M41T11 1 +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR "system" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFA200000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */ +#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR ((TEXT_BASE) + 0x40000) +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Reset address + */ +#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_MLRC10) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF00 +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */ +#define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */ + +/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ +#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) + +/* + * BR1 and OR1 (SDRAM) + * + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ +#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000E00 + +#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */ +#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* RPXLITE mem setting */ +#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */ +/* IMMR: 0xFA200000 IMMR base address - see above */ +#define CFG_BCSR_BASE 0xFA400000 /* BCSR base address */ + +#define CFG_BR3_PRELIM (CFG_BCSR_BASE | BR_V) /* BCSR */ +#define CFG_OR3_PRELIM 0xFFFF8910 +#define CFG_BR4_PRELIM (CFG_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */ +#define CFG_OR4_PRELIM 0xFFFE0970 + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 20 + +/* + * Refresh clock Prescalar + */ +#define CFG_MPTPR MPTPR_PTP_DIV2 + +/* + * MAMR settings for SDRAM + */ + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * BCSRx + * + * Board Status and Control Registers + * + */ + +#define BCSR0 (CFG_BCSR_BASE + 0) +#define BCSR1 (CFG_BCSR_BASE + 1) +#define BCSR2 (CFG_BCSR_BASE + 2) +#define BCSR3 (CFG_BCSR_BASE + 3) + +#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ +#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ +#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ +#define BCSR0_COLTEST 0x20 +#define BCSR0_ETHLPBK 0x40 +#define BCSR0_ETHEN 0x80 + +#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ +#define BCSR1_PCVCTL6 0x02 +#define BCSR1_PCVCTL5 0x04 +#define BCSR1_PCVCTL4 0x08 +#define BCSR1_IPB5SEL 0x10 + +#define BCSR2_ENPA5HDR 0x08 /* USB Control */ +#define BCSR2_ENUSBCLK 0x10 +#define BCSR2_USBPWREN 0x20 +#define BCSR2_USBSPD 0x40 +#define BCSR2_USBSUSP 0x80 + +#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ +#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ +#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ +#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ +#define BCSR3_D27 0x10 /* Dip Switch settings */ +#define BCSR3_D26 0x20 +#define BCSR3_D25 0x40 +#define BCSR3_D24 0x80 + +#endif /* __CONFIG_H */ diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h new file mode 100644 index 0000000..6c9e392 --- /dev/null +++ b/include/configs/rsdproto.h @@ -0,0 +1,418 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the R&S Protocol Board board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere. + */ +#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on neither */ +#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ + +#if (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE (0) +# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_INDEX */ + + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* enable I2C */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 50000000 /* in Hz */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_KGDB) + +/* Define this if you want to boot from 0x00000100. If you don't define + * this, you will need to program the bootloader to 0xfff00000, and + * get the hardware reset config words at 0xfe000000. The simplest + * way to do that is to program the bootloader at both addresses. + * It is suggested that you just let U-Boot live at 0x00000000. + */ +#define CFG_RSD_BOOT_LOW 1 + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "devfs=mount root=ramfs" +#define CONFIG_ETHADDR 08:00:3e:26:0a:5a +#define CONFIG_NETMASK 255.255.0.0 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */ +#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */ + +#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */ +#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ +#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ + +/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */ +/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */ + +#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ +#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ + +/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */ +/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */ + +#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */ +#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100 + +#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */ +#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */ + +#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */ + +#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ + +#define CFG_IMMR PHYS_IMMR + +/*----------------------------------------------------------------------- + * Reset Address + * + * In order to reset the CPU, U-Boot jumps to a special address which + * causes a machine check exception. The default address for this is + * CFG_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when + * testing the monitor in RAM using a JTAG debugger. + * + * Just set CFG_RESET_ADDRESS to an address that you know is sure to + * cause a bus error on your hardware. + */ +#define CFG_RESET_ADDRESS 0x20000000 + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + */ + +#if defined(CFG_RSD_BOOT_LOW) +# define CFG_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) +#else +# define CFG_RSD_HRCW_BOOT_FLAGS (0) +#endif /* defined(CFG_RSD_BOOT_LOW) */ + +/* get the HRCW ISB field from CFG_IMMR */ +#define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ + ((CFG_IMMR & 0x01000000) >> 7) |\ + ((CFG_IMMR & 0x00100000) >> 4) ) + +#define CFG_HRCW_MASTER (HRCW_L2CPC10 | \ + HRCW_DPPC11 | \ + CFG_RSD_HRCW_IMMR |\ + HRCW_MMR00 | \ + HRCW_APPC10 | \ + HRCW_CS10PC00 | \ + HRCW_MODCK_H0000 |\ + CFG_RSD_HRCW_BOOT_FLAGS) + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CFG_RAMBOOT is platform dependend. + */ +#define CFG_SDRAM_BASE PHYS_SDRAM_60X +#define CFG_FLASH_BASE PHYS_FLASH +/*#define CFG_MONITOR_BASE 0x200000 */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#define CFG_RAMBOOT +#endif +#define CFG_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 63 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */ + +/* turn off NVRAM env feature */ +#undef CONFIG_NVRAM_ENV + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register + *----------------------------------------------------------------------- + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR 0x100c0000 + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ + +#define CFG_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \ + SIUMCR_CS10PC01 | SIUMCR_BCTLC01) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \ + SYPCR_SWRI | SYPCR_SWP) + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#define CFG_SCCR 0x00000000 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + */ + +#define CFG_PSDMR 0x494D2452 +#define CFG_LSDMR 0x49492552 + +/* Flash */ +#define CFG_BR0_PRELIM (PHYS_FLASH | BRx_V) +#define CFG_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \ + ORxG_BCTLD | \ + ORxG_SCY_5_CLK) + +/* DPRAM to the PCI BUS on the protocol board */ +#define CFG_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V) +#define CFG_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \ + ORxG_ACS_DIV4) + +/* 60x Bus SDRAM */ +#define CFG_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V) +#define CFG_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \ + ORxS_BPD_4 | \ + ORxS_ROWST_PBI1_A2 | \ + ORxS_NUMR_13 | \ + ORxS_IBID) + +/* Virtex-FPGA - Register */ +#define CFG_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V) +#define CFG_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \ + ORxG_SCY_1_CLK | \ + ORxG_ACS_DIV2 | \ + ORxG_CSNT ) + +/* local bus SDRAM */ +#define CFG_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V) +#define CFG_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \ + ORxS_BPD_4 | \ + ORxS_ROWST_PBI1_A4 | \ + ORxS_NUMR_13) + +/* DPRAM to the Sharc-Bus on the protocol board */ +#define CFG_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V) +#define CFG_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \ + ORxG_ACS_DIV4) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h new file mode 100644 index 0000000..4e0cfdb --- /dev/null +++ b/include/configs/sacsng.h @@ -0,0 +1,1074 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * Configuration settings for the WindRiver SBC8260 board. + * See http://www.windriver.com/products/html/sbc8260.html + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG /* General debug */ +#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ + +#undef CONFIG_LOGBUFFER /* External logbuffer support */ + +/***************************************************************************** + * + * These settings must match the way _your_ board is set up + * + *****************************************************************************/ + +/* What is the oscillator's (UX2) frequency in Hz? */ +#define CONFIG_8260_CLKIN 66666600 + +/*----------------------------------------------------------------------- + * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual + *----------------------------------------------------------------------- + * What should MODCK_H be? It is dependent on the oscillator + * frequency, MODCK[1-3], and desired CPM and core frequencies. + * Here are some example values (all frequencies are in MHz): + * + * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 + * ------- ---------- --- --- ---- ----- ----- ----- + * 0x1 0x5 33 100 133 Open Close Open + * 0x1 0x6 33 100 166 Open Open Close + * 0x1 0x7 33 100 200 Open Open Open + * + * 0x2 0x2 33 133 133 Close Open Close + * 0x2 0x3 33 133 166 Close Open Open + * 0x2 0x4 33 133 200 Open Close Close + * 0x2 0x5 33 133 233 Open Close Open + * 0x2 0x6 33 133 266 Open Open Close + * + * 0x5 0x5 66 133 133 Open Close Open + * 0x5 0x6 66 133 166 Open Open Close + * 0x5 0x7 66 133 200 Open Open Open + * 0x6 0x0 66 133 233 Close Close Close + * 0x6 0x1 66 133 266 Close Close Open + * 0x6 0x2 66 133 300 Close Open Close + */ +#define CFG_SBC_MODCK_H 0x05 + +/* Define this if you want to boot from 0x00000100. If you don't define + * this, you will need to program the bootloader to 0xfff00000, and + * get the hardware reset config words at 0xfe000000. The simplest + * way to do that is to program the bootloader at both addresses. + * It is suggested that you just let U-Boot live at 0x00000000. + */ +#define CFG_SBC_BOOT_LOW 1 + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk + * The main FLASH is whichever is connected to *CS0. + */ +#define CFG_FLASH0_BASE 0x40000000 +#define CFG_FLASH0_SIZE 2 + +/* What should the base address of the secondary FLASH be and how big + * is it (in Mbytes)? The secondary FLASH is whichever is connected + * to *CS6. + */ +#define CFG_FLASH1_BASE 0x60000000 +#define CFG_FLASH1_SIZE 2 + +/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes + */ +#define CONFIG_VERY_BIG_RAM 1 + +/* What should be the base address of SDRAM DIMM and how big is + * it (in Mbytes)? This will normally auto-configure via the SPD. +*/ +#define CFG_SDRAM0_BASE 0x00000000 +#define CFG_SDRAM0_SIZE 64 + +/* + * Memory map example with 64 MB DIMM: + * + * 0x0000 0000 Exception Vector code, 8k + * : + * 0x0000 1FFF + * 0x0000 2000 Free for Application Use + * : + * : + * + * : + * : + * 0x03F5 FF30 Monitor Stack (Growing downward) + * Monitor Stack Buffer (0x80) + * 0x03F5 FFB0 Board Info Data + * 0x03F6 0000 Malloc Arena + * : CFG_ENV_SECT_SIZE, 16k + * : CFG_MALLOC_LEN, 128k + * 0x03FC 0000 RAM Copy of Monitor Code + * : CFG_MONITOR_LEN, 256k + * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 + */ + +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU) + + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere. + */ +#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on neither */ +#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ + +#undef CONFIG_ETHER_ON_SCC +#define CONFIG_ETHER_ON_FCC +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ + +#ifdef CONFIG_ETHER_ON_SCC +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ +#endif /* CONFIG_ETHER_ON_SCC */ + +#ifdef CONFIG_ETHER_ON_FCC +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ +#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +/* + * Port pins used for bit-banged MII communictions (if applicable). + */ + +#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */ +#define MDIO_ACTIVE (iop->pdir |= 0x40000000) +#define MDIO_TRISTATE (iop->pdir &= ~0x40000000) +#define MDIO_READ ((iop->pdat & 0x40000000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \ + else iop->pdat &= ~0x40000000 + +#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \ + else iop->pdat &= ~0x80000000 + +#define MIIDELAY udelay(50) +#endif /* CONFIG_ETHER_ON_FCC */ + +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) + +/* + * - RX clk is CLK11 + * - TX clk is CLK12 + */ +# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */ + +/* + * Configure for RAM tests. + */ +#undef CFG_DRAM_TEST /* calls other tests in board.c */ + + +/* + * Status LED for power up status feedback. + */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#define STATUS_LED_PAR im_ioport.iop_ppara +#define STATUS_LED_DIR im_ioport.iop_pdira +#define STATUS_LED_ODR im_ioport.iop_podra +#define STATUS_LED_DAT im_ioport.iop_pdata + +#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */ +#define STATUS_LED_PERIOD (CFG_HZ) +#define STATUS_LED_STATE STATUS_LED_OFF +#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */ +#define STATUS_LED_PERIOD1 (CFG_HZ) +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */ +#define STATUS_LED_PERIOD2 (CFG_HZ/2) +#define STATUS_LED_STATE2 STATUS_LED_ON + +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ + +#define STATUS_LED_YELLOW 0 +#define STATUS_LED_GREEN 1 +#define STATUS_LED_RED 2 +#define STATUS_LED_BOOT 1 + + +/* + * Select SPI support configuration + */ +#define CONFIG_SOFT_SPI /* Enable SPI driver */ +#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */ +#undef DEBUG_SPI /* Disable SPI debugging */ + +/* + * Software (bit-bang) SPI driver configuration + */ +#ifdef CONFIG_SOFT_SPI + +/* + * Software (bit-bang) SPI driver configuration + */ +#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */ +#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */ +#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */ + +#undef SPI_INIT /* no port initialization needed */ +#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) +#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ + else immr->im_ioport.iop_pdatd &= ~I2C_MOSI +#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ + else immr->im_ioport.iop_pdatd &= ~I2C_SCLK +#define SPI_DELAY /* No delay is needed */ +#endif /* CONFIG_SOFT_SPI */ + + +/* + * select I2C support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#ifdef CONFIG_SOFT_I2C +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +/* Define this to reserve an entire FLASH sector for + * environment variables. Otherwise, the environment will be + * put in the same sector as U-Boot, and changing variables + * will erase U-Boot temporarily + */ +#define CFG_ENV_IN_OWN_SECT 1 + +/* Define this to contain any number of null terminated strings that + * will be part of the default enviroment compiled into the boot image. + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ +"quiet=0\0" \ +"serverip=192.168.123.205\0" \ +"ipaddr=192.168.123.203\0" \ +"checkhostname=VR8500\0" \ +"reprog="\ + "bootp; " \ + "tftpboot 0x140000 /bdi2000/u-boot.bin; " \ + "protect off 60000000 6003FFFF; " \ + "erase 60000000 6003FFFF; " \ + "cp.b 140000 60000000 ${filesize}; " \ + "protect on 60000000 6003FFFF\0" \ +"copyenv="\ + "protect off 60040000 6004FFFF; " \ + "erase 60040000 6004FFFF; " \ + "cp.b 40040000 60040000 10000; " \ + "protect on 60040000 6004FFFF\0" \ +"copyprog="\ + "protect off 60000000 6003FFFF; " \ + "erase 60000000 6003FFFF; " \ + "cp.b 40000000 60000000 40000; " \ + "protect on 60000000 6003FFFF\0" \ +"zapenv="\ + "protect off 40040000 4004FFFF; " \ + "erase 40040000 4004FFFF; " \ + "protect on 40040000 4004FFFF\0" \ +"zapotherenv="\ + "protect off 60040000 6004FFFF; " \ + "erase 60040000 6004FFFF; " \ + "protect on 60040000 6004FFFF\0" \ +"root-on-initrd="\ + "setenv bootcmd "\ + "version\\;" \ + "echo\\;" \ + "bootp\\;" \ + "setenv bootargs root=/dev/ram0 rw quiet " \ + "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ + "run boot-hook\\;" \ + "bootm\0" \ +"root-on-initrd-debug="\ + "setenv bootcmd "\ + "version\\;" \ + "echo\\;" \ + "bootp\\;" \ + "setenv bootargs root=/dev/ram0 rw debug " \ + "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ + "run debug-hook\\;" \ + "run boot-hook\\;" \ + "bootm\0" \ +"root-on-nfs="\ + "setenv bootcmd "\ + "version\\;" \ + "echo\\;" \ + "bootp\\;" \ + "setenv bootargs root=/dev/nfs rw quiet " \ + "nfsroot=\\${serverip}:\\${rootpath} " \ + "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ + "run boot-hook\\;" \ + "bootm\0" \ +"root-on-nfs-debug="\ + "setenv bootcmd "\ + "version\\;" \ + "echo\\;" \ + "bootp\\;" \ + "setenv bootargs root=/dev/nfs rw debug " \ + "nfsroot=\\${serverip}:\\${rootpath} " \ + "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ + "run debug-hook\\;" \ + "run boot-hook\\;" \ + "bootm\0" \ +"debug-checkout="\ + "setenv checkhostname;" \ + "setenv ethaddr 00:09:70:00:00:01;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "run debug-hook;" \ + "run boot-hook;" \ + "bootm\0" \ +"debug-hook="\ + "echo ipaddr ${ipaddr};" \ + "echo serverip ${serverip};" \ + "echo gatewayip ${gatewayip};" \ + "echo netmask ${netmask};" \ + "echo hostname ${hostname}\0" \ +"ana=run adc ; run dac\0" \ +"adc=run adc-12 ; run adc-34\0" \ +"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \ +"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \ +"dac=echo ### DAC ; imd.b 11 81 5\0" \ +"boot-hook=echo\0" + +/* What should the console's baud rate be? */ +#define CONFIG_BAUDRATE 9600 + +/* Ethernet MAC address */ +#define CONFIG_ETHADDR 00:09:70:00:00:00 + +/* The default Ethernet MAC address can be overwritten just once */ +#ifdef CONFIG_ETHADDR +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#endif + +/* + * Define this to do some miscellaneous board-specific initialization. + */ +#define CONFIG_MISC_INIT_R + +/* Set to a positive value to delay for running BOOTCOMMAND */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ + +/* Be selective on what keys can delay or stop the autoboot process + * To stop use: " " + */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n" +#define CONFIG_AUTOBOOT_STOP_STR " " +#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define DEBUG_BOOTKEYS 0 + +/* Define a command string that is automatically executed when no character + * is read on the console interface withing "Boot Delay" after reset. + */ +#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ +#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ + +#ifdef CONFIG_BOOT_ROOT_INITRD +#define CONFIG_BOOTCOMMAND \ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/ram0 rw quiet " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "run boot-hook;" \ + "bootm" +#endif /* CONFIG_BOOT_ROOT_INITRD */ + +#ifdef CONFIG_BOOT_ROOT_NFS +#define CONFIG_BOOTCOMMAND \ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "run boot-hook;" \ + "bootm" +#endif /* CONFIG_BOOT_ROOT_NFS */ + +#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */ + +/* Add support for a few extra bootp options like: + * - File size + * - DNS (up to 2 servers) + * - Send hostname to DHCP server + */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME) + +/* undef this to save memory */ +#define CFG_LONGHELP + +/* Monitor Command Prompt */ +#define CFG_PROMPT "=> " + +#undef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) + * of an image is printed by image commands like bootm or iminfo. + */ +#define CONFIG_TIMESTAMP + +/* If this variable is defined, an environment variable named "ver" + * is created by U-Boot showing the U-Boot version. + */ +#define CONFIG_VERSION_VARIABLE + +/* What U-Boot subsytems do you want enabled? */ +#ifdef CONFIG_ETHER_ON_FCC +# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ + CFG_CMD_ELF | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ECHO | \ + CFG_CMD_I2C | \ + CFG_CMD_SPI | \ + CFG_CMD_SDRAM | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_PING | \ + CFG_CMD_MII ) +#else +# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ + CFG_CMD_ELF | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ECHO | \ + CFG_CMD_I2C | \ + CFG_CMD_SPI | \ + CFG_CMD_SDRAM | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_PING ) +#endif /* CONFIG_ETHER_ON_FCC */ + +/* Where do the internal registers live? */ +#define CFG_IMMR 0xF0000000 + +#undef CONFIG_WATCHDOG /* disable the watchdog */ + +/***************************************************************************** + * + * You should not have to modify any of the following settings + * + *****************************************************************************/ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */ +#define CONFIG_SACSng 1 /* munged for the SACSng */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */ + /* in the bootm command. */ +#define CFG_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */ + /* "## " from the bootm cmd */ +#define CFG_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */ + /* defined, then the hostname param */ + /* validated against checkhostname. */ +#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */ +#define CFG_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */ + /* (limited to maximum of 1024 msec) */ +#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1 + /* Check for abort key presses */ + /* at least once in dependent of the */ + /* CONFIG_BOOTDELAY value. */ +#define CFG_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */ +#define CFG_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */ + /* state to the fault LED. */ +#define CFG_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */ + /* the Ethernet link state. */ +#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */ + /* until the TFTP is successful. */ +#define CFG_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */ + /* turn off the STATUS LEDs. */ +#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */ + /* incoming data. */ +#define CFG_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */ + /* to signify that tftp is moving. */ +#define CFG_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */ + /* flash the status LED. */ +#define CFG_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */ + /* during the tftp file transfer. */ +#define CFG_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */ + /* '#'s from the tftp command. */ +#define CFG_TFTP_STATUS_QUIET 1 /* Suppress the status displays */ + /* issued during the tftp command. */ +#define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */ + /* before it gives up. */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) + +#define CFG_MAXARGS 32 /* max number of command args */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_ALT_MEMTEST /* Select full-featured memory test */ +#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ + /* the exception vector table */ + /* to the end of the DRAM */ + /* less monitor and malloc area */ +#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ +#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ + + CFG_MALLOC_LEN \ + + CFG_ENV_SECT_SIZE \ + + CFG_STACK_USAGE ) + +#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ + - CFG_MEM_END_USAGE ) + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE +#define CFG_SDRAM_BASE CFG_SDRAM0_BASE +#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + */ +#if defined(CFG_SBC_BOOT_LOW) +# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) +#else +# define CFG_SBC_HRCW_BOOT_FLAGS (0) +#endif /* defined(CFG_SBC_BOOT_LOW) */ + +/* get the HRCW ISB field from CFG_IMMR */ +#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ + ((CFG_IMMR & 0x01000000) >> 7) | \ + ((CFG_IMMR & 0x00100000) >> 4) ) + +#define CFG_HRCW_MASTER ( HRCW_BPS10 | \ + HRCW_DPPC11 | \ + CFG_SBC_HRCW_IMMR | \ + HRCW_MMR00 | \ + HRCW_LBPC11 | \ + HRCW_APPC10 | \ + HRCW_CS10PC00 | \ + (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ + CFG_SBC_HRCW_BOOT_FLAGS ) + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CFG_RAMBOOT is platform dependent. + */ +#define CFG_MONITOR_BASE CFG_FLASH0_BASE + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#undef CFG_FLASH_PROTECTION /* use hardware protection */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +#ifndef CFG_RAMBOOT +# define CFG_ENV_IS_IN_FLASH 1 + +# ifdef CFG_ENV_IN_OWN_SECT +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +# define CFG_ENV_SECT_SIZE 0x10000 +# else +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) +# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ +# endif /* CFG_ENV_IN_OWN_SECT */ + +#else +# define CFG_ENV_IS_IN_NVRAM 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +# define CFG_ENV_SIZE 0x200 +#endif /* CFG_RAMBOOT */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE |\ + HID0_DCE |\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) + +#define CFG_HID0_FINAL (HID0_ICE |\ + HID0_IFEM |\ + HID0_ABE |\ + HID0_EMCP) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register + *----------------------------------------------------------------------- + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR (BCR_ETM) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ + +#define CFG_SIUMCR (SIUMCR_DPPC11 |\ + SIUMCR_L2CPC00 |\ + SIUMCR_APPC10 |\ + SIUMCR_MMR00) + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC |\ + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP |\ + SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC |\ + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC |\ + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS |\ + PISCR_PTF |\ + PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#define CFG_SCCR 0 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Initialize Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 16 bit FLASH (primary flash - 2MB) + * 1 60x GPCM -- bit (Unused) + * 2 60x SDRAM 64 bit SDRAM (DIMM) + * 3 60x SDRAM 64 bit SDRAM (DIMM) + * 4 60x GPCM -- bit (Unused) + * 5 60x GPCM -- bit (Unused) + * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB) + */ + +/*----------------------------------------------------------------------- + * BR0,BR1 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR0,OR1 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 0 - Primary FLASH + */ + +/* BR0 is configured as follows: + * + * - Base address of 0x40000000 + * - 16 bit port size + * - Data errors checking is disabled + * - Read and write access + * - GPCM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +/* OR0 is configured as follows: + * + * - 4 MB + * - *BCTL0 is asserted upon access to the current memory bank + * - *CW / *WE are negated a quarter of a clock earlier + * - *CS is output at the same time as the address lines + * - Uses a clock cycle length of 5 + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + +/*----------------------------------------------------------------------- + * BR2,BR3 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR2,OR3 - Option Register + * Ref: Section 10.3.2 on page 10-16 + *----------------------------------------------------------------------- + */ + +/* Bank 2,3 - SDRAM DIMM + */ + +/* The BR2 is configured as follows: + * + * - Base address of 0x00000000 + * - 64 bit port size (60x bus only) + * - Data errors checking is disabled + * - Read and write access + * - SDRAM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +/* With a 64 MB DIMM, the OR2 is configured as follows: + * + * - 64 MB + * - 4 internal banks per device + * - Row start address bit is A8 with PSDMR[PBI] = 0 + * - 12 row address lines + * - Back-to-back page mode + * - Internal bank interleaving within save device enabled + */ +#if (CFG_SDRAM0_SIZE == 64) +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A8 |\ + ORxS_NUMR_12) +#else +#error "INVALID SDRAM CONFIGURATION" +#endif + +/*----------------------------------------------------------------------- + * PSDMR - 60x Bus SDRAM Mode Register + * Ref: Section 10.3.3 on page 10-21 + *----------------------------------------------------------------------- + */ + +/* Address that the DIMM SPD memory lives at. + */ +#define SDRAM_SPD_ADDR 0x50 + +#if (CFG_SDRAM0_SIZE == 64) +/* With a 64 MB DIMM, the PSDMR is configured as follows: + * + * - Bank Based Interleaving, + * - Refresh Enable, + * - Address Multiplexing where A5 is output on A14 pin + * (A6 on A15, and so on), + * - use address pins A14-A16 as bank select, + * - A9 is output on SDA10 during an ACTIVATE command, + * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, + * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 3 clocks, + * - earliest timing for READ/WRITE command after ACTIVATE command is + * 2 clocks, + * - earliest timing for PRECHARGE after last data was read is 1 clock, + * - earliest timing for PRECHARGE after last data was written is 1 clock, + * - CAS Latency is 2. + */ +#define CFG_PSDMR (PSDMR_RFEN |\ + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) +#else +#error "INVALID SDRAM CONFIGURATION" +#endif + +/* + * Shoot for approximately 1MHz on the prescaler. + */ +#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000)) +#define CFG_MPTPR MPTPR_PTP_DIV64 +#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000)) +#define CFG_MPTPR MPTPR_PTP_DIV32 +#else +#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK" +#define CFG_MPTPR MPTPR_PTP_DIV32 +#endif +#define CFG_PSRT 14 + + +/*----------------------------------------------------------------------- + * BR6 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR6 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 6 - Secondary FLASH + * + * The secondary FLASH is connected to *CS6 + */ +#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) + +/* BR6 is configured as follows: + * + * - Base address of 0x60000000 + * - 16 bit port size + * - Data errors checking is disabled + * - Read and write access + * - GPCM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\ + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +/* OR6 is configured as follows: + * + * - 2 MB + * - *BCTL0 is asserted upon access to the current memory bank + * - *CW / *WE are negated a quarter of a clock earlier + * - *CS is output at the same time as the address lines + * - Uses a clock cycle length of 5 + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ +# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) +#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h new file mode 100644 index 0000000..beff28a --- /dev/null +++ b/include/configs/sbc405.h @@ -0,0 +1,277 @@ +/* + * (C) Copyright 2001 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo" + +#define CONFIG_RAMBOOT \ + "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm ffc00000 ffca0000" +#define CONFIG_NFSBOOT \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm ffc00000" + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */ + + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \ + "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \ + "f=0x08 tn=sbc405 o=emac \0" \ + "env_startaddr=FF000000\0" \ + "env_endaddr=FF03FFFF\0" \ + "loadfile=vxWorks.st\0" \ + "loadaddr=0x01000000\0" \ + "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ + "uboot_startaddr=FFFC0000\0" \ + "uboot_endaddr=FFFFFFFF\0" \ + "update=tftp ${loadaddr} u-boot.bin;" \ + "protect off ${uboot_startaddr} ${uboot_endaddr};" \ + "era ${uboot_startaddr} ${uboot_endaddr};" \ + "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \ + "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \ + "zapenv=protect off ${env_startaddr} ${env_endaddr};" \ + "era ${env_startaddr} ${env_endaddr};" \ + "protect on ${env_startaddr} ${env_endaddr}\0" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_SDRAM | \ + 0 ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ + +#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ +#define CONFIG_IPADDR 192.168.193.102 +#define CONFIG_NETMASK 255.255.255.224 +#define CONFIG_SERVERIP 192.168.193.119 +#define CONFIG_GATEWAYIP 192.168.193.97 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MONITOR_BASE 0xFFFC0000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_INCREMENT 0x01000000 +#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/*----------------------------------------------------------------------- + * Environment Variable setup + */ +#define CFG_ENV_ADDR CFG_FLASH_BASE /* starting right at the beginning */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ +#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ +#define FLASH0_BA CFG_FLASH_BASE /* FLASH 0 Base Address */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ + +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 +#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h new file mode 100644 index 0000000..d891e07 --- /dev/null +++ b/include/configs/sbc8240.h @@ -0,0 +1,365 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Configuration settings for the sbc8240 board. + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8240 1 +#define CONFIG_WRSBC8240 1 + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $loadaddr $loadfile;bootvx" /* autoboot command */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \ + "e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \ + "tn=sbc8240 o=fei \0" \ + "env_startaddr=FFF70000\0" \ + "env_endaddr=FFF7FFFF\0" \ + "loadfile=vxWorks.st\0" \ + "loadaddr=0x01000000\0" \ + "net_load=tftpboot $loadaddr $loadfile\0" \ + "uboot_startaddr=FFF00000\0" \ + "uboot_endaddr=FFF3FFFF\0" \ + "update=tftp $loadaddr /u-boot.bin;" \ + "protect off $uboot_startaddr $uboot_endaddr;" \ + "era $uboot_startaddr $uboot_endaddr;" \ + "cp.b $loadaddr $uboot_startaddr $filesize;" \ + "protect on $uboot_startaddr $uboot_endaddr\0" \ + "zapenv=protect off $env_startaddr $env_endaddr;" \ + "era $env_startaddr $env_endaddr;" \ + "protect on $env_startaddr $env_endaddr\0" + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_SDRAM | \ + 0 ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#if 1 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ +#define CONFIG_IPADDR 192.168.193.102 +#define CONFIG_NETMASK 255.255.255.248 +#define CONFIG_SERVERIP 192.168.193.99 + +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define STATUS_LED_BIT 0x00000001 +#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_BLINKING +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#ifndef __ASSEMBLY__ +/* LEDs */ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + *((volatile char *) (CFG_LED_BASE)) ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + *((volatile char *) (CFG_LED_BASE)) |= (_msk); \ + else \ + *((volatile char *) (CFG_LED_BASE)) &= ~(_msk); \ + } while(0) + +#define __led_init(msk, st) __led_set(msk, st) + +#endif + +#define CONFIG_MISC_INIT_R +#define CFG_LED_BASE 0xFFE80000 + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF00000 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFCE00000 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + + /* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x10000000 + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + + /* Size in bytes reserved for initial data + */ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK 3686400 + +#define CFG_NS16550_COM1 0xFFF80000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 +#define CFG_HZ 1000 +#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 + + /* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 7 + + /* Bit-field values for MCCR2. + */ +#define CFG_REFINT 430 /* Refresh interval */ + + /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 192 + + /* Bit-field values for MCCR3. + */ +#define CFG_REFREC 2 /* Refresh to activate interval */ +#define CFG_RDLAT 3 /* Data latancy from read command */ + + /* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ +#define CFG_ACTORW 2 +#define CFG_REGISTERD_TYPE_BUFFER 1 + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0xff + +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 256 /* Max number of sectors in one bank */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + /* Warining: environment is not EMBEDDED in the U-Boot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFFF70000 +#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */ +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* we need Plug 'n Play */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_TULIP +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h new file mode 100644 index 0000000..180ce05 --- /dev/null +++ b/include/configs/sbc8260.h @@ -0,0 +1,1088 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2001 + * Advent Networks, Inc. + * Jay Monkman + * + * Configuration settings for the WindRiver SBC8260 board. + * See http://www.windriver.com/products/html/sbc8260.html + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Enable debug prints */ +#undef DEBUG /* General debug */ +#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ + +/***************************************************************************** + * + * These settings must match the way _your_ board is set up + * + *****************************************************************************/ + +/* What is the oscillator's (UX2) frequency in Hz? */ +#define CONFIG_8260_CLKIN (66 * 1000 * 1000) + +/*----------------------------------------------------------------------- + * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual + *----------------------------------------------------------------------- + * What should MODCK_H be? It is dependent on the oscillator + * frequency, MODCK[1-3], and desired CPM and core frequencies. + * Here are some example values (all frequencies are in MHz): + * + * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 + * ------- ---------- --- --- ---- ----- ----- ----- + * 0x1 0x5 33 100 133 Open Close Open + * 0x1 0x6 33 100 166 Open Open Close + * 0x1 0x7 33 100 200 Open Open Open + * + * 0x2 0x2 33 133 133 Close Open Close + * 0x2 0x3 33 133 166 Close Open Open + * 0x2 0x4 33 133 200 Open Close Close + * 0x2 0x5 33 133 233 Open Close Open + * 0x2 0x6 33 133 266 Open Open Close + * + * 0x5 0x5 66 133 133 Open Close Open + * 0x5 0x6 66 133 166 Open Open Close + * 0x5 0x7 66 133 200 Open Open Open + * 0x6 0x0 66 133 233 Close Close Close + * 0x6 0x1 66 133 266 Close Close Open + * 0x6 0x2 66 133 300 Close Open Close + */ +#define CFG_SBC_MODCK_H 0x05 + +/* Define this if you want to boot from 0x00000100. If you don't define + * this, you will need to program the bootloader to 0xfff00000, and + * get the hardware reset config words at 0xfe000000. The simplest + * way to do that is to program the bootloader at both addresses. + * It is suggested that you just let U-Boot live at 0x00000000. + */ +#define CFG_SBC_BOOT_LOW 1 + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk + * The main FLASH is whichever is connected to *CS0. U-Boot expects + * this to be the SIMM. + */ +#define CFG_FLASH0_BASE 0x40000000 +#define CFG_FLASH0_SIZE 4 + +/* What should the base address of the secondary FLASH be and how big + * is it (in Mbytes)? The secondary FLASH is whichever is connected + * to *CS6. U-Boot expects this to be the on board FLASH. If you don't + * want it enabled, don't define these constants. + */ +#define CFG_FLASH1_BASE 0x60000000 +#define CFG_FLASH1_SIZE 2 + +/* What should be the base address of SDRAM DIMM and how big is + * it (in Mbytes)? +*/ +#define CFG_SDRAM0_BASE 0x00000000 +#define CFG_SDRAM0_SIZE 64 + +/* What should be the base address of the LEDs and switch S0? + * If you don't want them enabled, don't define this. + */ +#define CFG_LED_BASE 0xa0000000 + + +/* + * SBC8260 with 16 MB DIMM: + * + * 0x0000 0000 Exception Vector code, 8k + * : + * 0x0000 1FFF + * 0x0000 2000 Free for Application Use + * : + * : + * + * : + * : + * 0x00F5 FF30 Monitor Stack (Growing downward) + * Monitor Stack Buffer (0x80) + * 0x00F5 FFB0 Board Info Data + * 0x00F6 0000 Malloc Arena + * : CFG_ENV_SECT_SIZE, 256k + * : CFG_MALLOC_LEN, 128k + * 0x00FC 0000 RAM Copy of Monitor Code + * : CFG_MONITOR_LEN, 256k + * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 + */ + +/* + * SBC8260 with 64 MB DIMM: + * + * 0x0000 0000 Exception Vector code, 8k + * : + * 0x0000 1FFF + * 0x0000 2000 Free for Application Use + * : + * : + * + * : + * : + * 0x03F5 FF30 Monitor Stack (Growing downward) + * Monitor Stack Buffer (0x80) + * 0x03F5 FFB0 Board Info Data + * 0x03F6 0000 Malloc Arena + * : CFG_ENV_SECT_SIZE, 256k + * : CFG_MALLOC_LEN, 128k + * 0x03FC 0000 RAM Copy of Monitor Code + * : CFG_MONITOR_LEN, 256k + * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 + */ + + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere. + */ +#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on neither */ +#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + */ + +#undef CONFIG_ETHER_ON_SCC +#define CONFIG_ETHER_ON_FCC +#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ + +#ifdef CONFIG_ETHER_ON_SCC +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ +#endif /* CONFIG_ETHER_ON_SCC */ + +#ifdef CONFIG_ETHER_ON_FCC +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ +#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +/* + * Port pins used for bit-banged MII communictions (if applicable). + */ +#define MDIO_PORT 2 /* Port C */ +#define MDIO_ACTIVE (iop->pdir |= 0x00400000) +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) +#define MDIO_READ ((iop->pdat & 0x00400000) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + +#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + +#define MIIDELAY udelay(1) +#endif /* CONFIG_ETHER_ON_FCC */ + +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) + +/* + * - RX clk is CLK11 + * - TX clk is CLK12 + */ +# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + +/* + * Select SPI support configuration + */ +#undef CONFIG_SPI /* Disable SPI driver */ + +/* + * Select i2c support configuration + * + * Supported configurations are {none, software, hardware} drivers. + * If the software driver is chosen, there are some additional + * configuration items that the driver uses to drive the port pins. + */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#ifdef CONFIG_SOFT_I2C +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + + +/* Define this to reserve an entire FLASH sector (256 KB) for + * environment variables. Otherwise, the environment will be + * put in the same sector as U-Boot, and changing variables + * will erase U-Boot temporarily + */ +#define CFG_ENV_IN_OWN_SECT 1 + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* What should the console's baud rate be? */ +#define CONFIG_BAUDRATE 9600 + +/* Ethernet MAC address + * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx) + * http://standards.ieee.org/regauth/oui/index.shtml + */ +#define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb + +/* + * Define this to set the last octet of the ethernet address from the + * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7 + * switch and the LEDs are backwards with respect to each other. DS7 + * is on the board edge side of both the LED strip and the DS0-DS7 + * switch. + */ +#undef CONFIG_MISC_INIT_R + +/* Set to a positive value to delay for running BOOTCOMMAND */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* Be selective on what keys can delay or stop the autoboot process + * To stop use: " " + */ +#undef CONFIG_AUTOBOOT_KEYED +#ifdef CONFIG_AUTOBOOT_KEYED +# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" +# define CONFIG_AUTOBOOT_STOP_STR " " +# undef CONFIG_AUTOBOOT_DELAY_STR +# define DEBUG_BOOTKEYS 0 +#endif + +/* Define this to contain any number of null terminated strings that + * will be part of the default enviroment compiled into the boot image. + * + * Variable Usage + * -------------- ------------------------------------------------------- + * serverip server IP address + * ipaddr my IP address + * reprog Reload flash with a new copy of U-Boot + * zapenv Erase the environment area in flash + * root-on-initrd Set the bootcmd variable to allow booting of an initial + * ram disk. + * root-on-nfs Set the bootcmd variable to allow booting of a NFS + * mounted root filesystem. + * boot-hook Convenient stub to do something useful before the + * bootm command is executed. + * + * Example usage of root-on-initrd and root-on-nfs : + * + * Note: The lines have been wrapped to improved its readability. + * + * => printenv bootcmd + * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw + * nfsroot=${serverip}:${rootpath} + * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm + * + * => run root-on-initrd + * => printenv bootcmd + * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw + * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm + * + * => run root-on-nfs + * => printenv bootcmd + * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw + * nfsroot=${serverip}:${rootpath} + * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm + * + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "serverip=192.168.123.205\0" \ + "ipaddr=192.168.123.213\0" \ + "reprog="\ + "bootp;" \ + "tftpboot 0x140000 /bdi2000/u-boot.bin;" \ + "protect off 1:0;" \ + "erase 1:0;" \ + "cp.b 140000 40000000 ${filesize};" \ + "protect on 1:0\0" \ + "zapenv="\ + "protect off 1:1;" \ + "erase 1:1;" \ + "protect on 1:1\0" \ + "root-on-initrd="\ + "setenv bootcmd "\ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/ram0 rw " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "run boot-hook;" \ + "bootm\0" \ + "root-on-nfs="\ + "setenv bootcmd "\ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "run boot-hook;" \ + "bootm\0" \ + "boot-hook=echo\0" + +/* Define a command string that is automatically executed when no character + * is read on the console interface withing "Boot Delay" after reset. + */ +#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ +#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ + +#ifdef CONFIG_BOOT_ROOT_INITRD +#define CONFIG_BOOTCOMMAND \ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/ram0 rw " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" +#endif /* CONFIG_BOOT_ROOT_INITRD */ + +#ifdef CONFIG_BOOT_ROOT_NFS +#define CONFIG_BOOTCOMMAND \ + "version;" \ + "echo;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" +#endif /* CONFIG_BOOT_ROOT_NFS */ + +/* Add support for a few extra bootp options like: + * - File size + * - DNS (up to 2 servers) + * - Send hostname to DHCP server + */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME) + +/* undef this to save memory */ +#define CFG_LONGHELP + +/* Monitor Command Prompt */ +#define CFG_PROMPT "=> " + +#undef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) + * of an image is printed by image commands like bootm or iminfo. + */ +#define CONFIG_TIMESTAMP + +/* If this variable is defined, an environment variable named "ver" + * is created by U-Boot showing the U-Boot version. + */ +#define CONFIG_VERSION_VARIABLE + +/* What U-Boot subsytems do you want enabled? */ +#ifdef CONFIG_ETHER_ON_FCC +# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ECHO | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM ) +#else +# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ECHO | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IMMAP | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM ) +#endif /* CONFIG_ETHER_ON_FCC */ + +#undef CONFIG_WATCHDOG /* disable the watchdog */ + +/* Where do the internal registers live? */ +#define CFG_IMMR 0xF0000000 + +/***************************************************************************** + * + * You should not have to modify any of the following settings + * + *****************************************************************************/ + +#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ +#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) + +#define CFG_MAXARGS 32 /* max number of command args */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x400000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_ALT_MEMTEST /* Select full-featured memory test */ +#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ + /* the exception vector table */ + /* to the end of the DRAM */ + /* less monitor and malloc area */ +#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ +#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ + + CFG_MALLOC_LEN \ + + CFG_ENV_SECT_SIZE \ + + CFG_STACK_USAGE ) + +#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ + - CFG_MEM_END_USAGE ) + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE +#define CFG_SDRAM_BASE CFG_SDRAM0_BASE +#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + */ +#if defined(CFG_SBC_BOOT_LOW) +# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) +#else +# define CFG_SBC_HRCW_BOOT_FLAGS (0) +#endif /* defined(CFG_SBC_BOOT_LOW) */ + +/* get the HRCW ISB field from CFG_IMMR */ +#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ + ((CFG_IMMR & 0x01000000) >> 7) | \ + ((CFG_IMMR & 0x00100000) >> 4) ) + +#define CFG_HRCW_MASTER ( HRCW_BPS11 | \ + HRCW_DPPC11 | \ + CFG_SBC_HRCW_IMMR | \ + HRCW_MMR00 | \ + HRCW_LBPC11 | \ + HRCW_APPC10 | \ + HRCW_CS10PC00 | \ + (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ + CFG_SBC_HRCW_BOOT_FLAGS ) + +/* no slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Note also that the logic that sets CFG_RAMBOOT is platform dependent. + */ +#define CFG_MONITOR_BASE CFG_FLASH0_BASE + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +#ifndef CFG_RAMBOOT +# define CFG_ENV_IS_IN_FLASH 1 + +# ifdef CFG_ENV_IN_OWN_SECT +# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +# define CFG_ENV_SECT_SIZE 0x40000 +# else +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) +# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ +# endif /* CFG_ENV_IN_OWN_SECT */ + +#else +# define CFG_ENV_IS_IN_NVRAM 1 +# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +# define CFG_ENV_SIZE 0x200 +#endif /* CFG_RAMBOOT */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE |\ + HID0_DCE |\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) + +#define CFG_HID0_FINAL (HID0_ICE |\ + HID0_IFEM |\ + HID0_ABE |\ + HID0_EMCP) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register + *----------------------------------------------------------------------- + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR (BCR_ETM) + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ + +#define CFG_SIUMCR (SIUMCR_DPPC11 |\ + SIUMCR_L2CPC00 |\ + SIUMCR_APPC10 |\ + SIUMCR_MMR00) + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC |\ + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP |\ + SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC |\ + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC |\ + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS |\ + PISCR_PTF |\ + PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + */ +#define CFG_SCCR 0 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Initialize Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) * + * 1 60x GPCM 32 bit FLASH (SIMM - Unused) + * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB) + * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused) + * 4 Local SDRAM 32 bit SDRAM (on board - 4MB) + * 5 60x GPCM 8 bit EEPROM (8KB) + * 6 60x GPCM 8 bit FLASH (on board - 2MB) * + * 7 60x GPCM 8 bit LEDs, switches + * + * (*) This configuration requires the SBC8260 be configured + * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to + * the on board FLASH. In other words, JP24 should have + * pins 1 and 2 jumpered and pins 3 and 4 jumpered. + * + */ + +/*----------------------------------------------------------------------- + * BR0,BR1 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR0,OR1 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 0,1 - FLASH SIMM + * + * This expects the FLASH SIMM to be connected to *CS0 + * It consists of 4 AM29F080B parts. + * + * Note: For the 4 MB SIMM, *CS1 is unused. + */ + +/* BR0 is configured as follows: + * + * - Base address of 0x40000000 + * - 32 bit port size + * - Data errors checking is disabled + * - Read and write access + * - GPCM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +/* OR0 is configured as follows: + * + * - 4 MB + * - *BCTL0 is asserted upon access to the current memory bank + * - *CW / *WE are negated a quarter of a clock earlier + * - *CS is output at the same time as the address lines + * - Uses a clock cycle length of 5 + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) + +/*----------------------------------------------------------------------- + * BR2,BR3 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR2,OR3 - Option Register + * Ref: Section 10.3.2 on page 10-16 + *----------------------------------------------------------------------- + */ + +/* Bank 2,3 - SDRAM DIMM + * + * 16MB DIMM: P/N + * 64MB DIMM: P/N 1W-8864X8-4-P1-EST + * + * Note: *CS3 is unused for this DIMM + */ + +/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows: + * + * - Base address of 0x00000000 + * - 64 bit port size (60x bus only) + * - Data errors checking is disabled + * - Read and write access + * - SDRAM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +/* With a 16 MB DIMM, the OR2 is configured as follows: + * + * - 16 MB + * - 2 internal banks per device + * - Row start address bit is A9 with PSDMR[PBI] = 0 + * - 11 row address lines + * - Back-to-back page mode + * - Internal bank interleaving within save device enabled + */ +#if (CFG_SDRAM0_SIZE == 16) +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ + ORxS_BPD_2 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_11) +#endif + +/* With a 64 MB DIMM, the OR2 is configured as follows: + * + * - 64 MB + * - 4 internal banks per device + * - Row start address bit is A8 with PSDMR[PBI] = 0 + * - 12 row address lines + * - Back-to-back page mode + * - Internal bank interleaving within save device enabled + */ +#if (CFG_SDRAM0_SIZE == 64) +#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A8 |\ + ORxS_NUMR_12) +#endif + +/*----------------------------------------------------------------------- + * PSDMR - 60x Bus SDRAM Mode Register + * Ref: Section 10.3.3 on page 10-21 + *----------------------------------------------------------------------- + */ + +/* Address that the DIMM SPD memory lives at. + */ +#define SDRAM_SPD_ADDR 0x54 + +#if (CFG_SDRAM0_SIZE == 16) +/* With a 16 MB DIMM, the PSDMR is configured as follows: + * + * - Bank Based Interleaving, + * - Refresh Enable, + * - Address Multiplexing where A5 is output on A14 pin + * (A6 on A15, and so on), + * - use address pins A16-A18 as bank select, + * - A9 is output on SDA10 during an ACTIVATE command, + * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, + * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 3 clocks, + * - earliest timing for READ/WRITE command after ACTIVATE command is + * 2 clocks, + * - earliest timing for PRECHARGE after last data was read is 1 clock, + * - earliest timing for PRECHARGE after last data was written is 1 clock, + * - CAS Latency is 2. + */ +#define CFG_PSDMR (PSDMR_RFEN |\ + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A16_A18 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) +#endif + +#if (CFG_SDRAM0_SIZE == 64) +/* With a 64 MB DIMM, the PSDMR is configured as follows: + * + * - Bank Based Interleaving, + * - Refresh Enable, + * - Address Multiplexing where A5 is output on A14 pin + * (A6 on A15, and so on), + * - use address pins A14-A16 as bank select, + * - A9 is output on SDA10 during an ACTIVATE command, + * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, + * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command + * is 3 clocks, + * - earliest timing for READ/WRITE command after ACTIVATE command is + * 2 clocks, + * - earliest timing for PRECHARGE after last data was read is 1 clock, + * - earliest timing for PRECHARGE after last data was written is 1 clock, + * - CAS Latency is 2. + */ +#define CFG_PSDMR (PSDMR_RFEN |\ + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) +#endif + +/* + * Shoot for approximately 1MHz on the prescaler. + */ +#if (CONFIG_8260_CLKIN == (66 * 1000 * 1000)) +#define CFG_MPTPR MPTPR_PTP_DIV64 +#elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000)) +#define CFG_MPTPR MPTPR_PTP_DIV32 +#else +#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK" +#define CFG_MPTPR MPTPR_PTP_DIV32 +#endif +#define CFG_PSRT 14 + + +/* Bank 4 - On board SDRAM + * + * This is not implemented yet. + */ + +/*----------------------------------------------------------------------- + * BR6 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR6 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 6 - On board FLASH + * + * This expects the on board FLASH SIMM to be connected to *CS6 + * It consists of 1 AM29F016A part. + */ +#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) + +/* BR6 is configured as follows: + * + * - Base address of 0x60000000 + * - 8 bit port size + * - Data errors checking is disabled + * - Read and write access + * - GPCM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +/* OR6 is configured as follows: + * + * - 2 MB + * - *BCTL0 is asserted upon access to the current memory bank + * - *CW / *WE are negated a quarter of a clock earlier + * - *CS is output at the same time as the address lines + * - Uses a clock cycle length of 5 + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ +# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) +#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */ + +/*----------------------------------------------------------------------- + * BR7 - Base Register + * Ref: Section 10.3.1 on page 10-14 + * OR7 - Option Register + * Ref: Section 10.3.2 on page 10-18 + *----------------------------------------------------------------------- + */ + +/* Bank 7 - LEDs and switches + * + * LEDs are at 0x00001 (write only) + * switches are at 0x00001 (read only) + */ +#ifdef CFG_LED_BASE + +/* BR7 is configured as follows: + * + * - Base address of 0xA0000000 + * - 8 bit port size + * - Data errors checking is disabled + * - Read and write access + * - GPCM 60x bus + * - Access are handled by the memory controller according to MSEL + * - Not used for atomic operations + * - No data pipelining is done + * - Valid + */ +# define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +/* OR7 is configured as follows: + * + * - 1 byte + * - *BCTL0 is asserted upon access to the current memory bank + * - *CW / *WE are negated a quarter of a clock earlier + * - *CS is output at the same time as the address lines + * - Uses a clock cycle length of 15 + * - *PSDVAL is generated internally by the memory controller + * unless *GTA is asserted earlier externally. + * - Relaxed timing is generated by the GPCM for accesses + * initiated to this memory region. + * - One idle clock is inserted between a read access from the + * current bank and the next access. + */ +# define CFG_OR7_PRELIM (ORxG_AM_MSK |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_15_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) +#endif /* CFG_LED_BASE */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h new file mode 100644 index 0000000..5a434dc --- /dev/null +++ b/include/configs/sbc8560.h @@ -0,0 +1,404 @@ +/* + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * (C) Copyright 2004 Wind River Systems Inc . + * Added support for Wind River SBC8560 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* mpc8560ads board configuration file */ +/* please refer to doc/README.mpc85xx for more info */ +/* make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ + + +#define CONFIG_CPM2 1 /* has CPM2 */ +#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ + +/* XXX flagging this as something I might want to delete */ +#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_PCI /* pci ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ + + +#define CONFIG_ENV_OVERWRITE + +/* Using Localbus SDRAM to emulate flash before we can program the flash, + * normally you need a flash-boot image(u-boot.bin), if so undef this. + */ +#undef CONFIG_RAM_AS_FLASH + +#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ + #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ +#else + #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ +#endif + +/* below can be toggled for performance analysis. otherwise use default */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#undef CONFIG_BTB /* toggle branch predition */ +#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ + defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ + defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) +#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." +#endif + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ + +#if XXX + #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ +#else + #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ +#endif +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ +#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ + +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ + +#if defined(CONFIG_MPC85xx_REV1) + #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#if defined(CONFIG_RAM_AS_FLASH) + #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ + #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ + #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ + #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ +#else /* Boot from real Flash */ + #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ + #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ + #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ + #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ +#endif +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* local bus definitions */ +#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ +#define CFG_OR1_PRELIM 0xfc000ff7 + +#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ +#define CFG_OR2_PRELIM 0x00000000 + +#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ +#define CFG_OR3_PRELIM 0xfc000cc1 + +#if defined(CONFIG_RAM_AS_FLASH) + #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ +#else + #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ +#endif +#define CFG_OR4_PRELIM 0xfc000cc1 + +#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ +#if 1 + #define CFG_OR5_PRELIM 0xff000ff7 +#else + #define CFG_OR5_PRELIM 0xff0000f0 +#endif + +#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ +#define CFG_OR6_PRELIM 0xfc000ff7 +#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ +#define CFG_LBC_LBCR 0x00000000 +#define CFG_LBC_LSRT 0x20000000 +#define CFG_LBC_MRTPR 0x20000000 +#define CFG_LBC_LSDMR_1 0x2861b723 +#define CFG_LBC_LSDMR_2 0x0861b723 +#define CFG_LBC_LSDMR_3 0x0861b723 +#define CFG_LBC_LSDMR_4 0x1861b723 +#define CFG_LBC_LSDMR_5 0x4061b723 + +/* just hijack the MOT BCSR def for SBC8560 misc devices */ +#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) +/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ + +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) +#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_PCI_MEM_BASE 0xC0000000 +#define CFG_PCI_MEM_PHYS 0xC0000000 +#define CFG_PCI_MEM_SIZE 0x10000000 + +#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ + +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 /* MII PHY management */ +# define CONFIG_MPC85xx_TSEC1 +# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" +# define TSEC1_PHY_ADDR 25 +# define TSEC1_PHYIDX 0 +/* Options are: TSEC0 */ +# define CONFIG_ETHPRIME "TSEC0" + +#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ + + #undef CONFIG_ETHER_NONE /* define if ether on something else */ + #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ + #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + + #if (CONFIG_ETHER_INDEX == 2) + /* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers + * - Full duplex + */ + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CFG_CPMFCR_RAMTYPE 0 + #define CFG_FCC_PSMR (FCC_PSMR_FDE) + + #elif (CONFIG_ETHER_INDEX == 3) + /* need more definitions here for FE3 */ + #endif /* CONFIG_ETHER_INDEX */ + + #define CONFIG_MII /* MII PHY management */ + #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ + /* + * GPIO pins used for bit-banged MII communications + */ + #define MDIO_PORT 2 /* Port C */ + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) + #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) + #define MDIO_READ ((iop->pdat & 0x00400000) != 0) + + #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + + #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + + #define MIIDELAY udelay(1) + +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#if 0 +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION /* use hardware protection */ +#endif +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if 0 +/* XXX This doesn't work and I don't want to fix it */ +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) + #define CFG_RAMBOOT +#else + #undef CFG_RAMBOOT +#endif +#endif + +/* Environment */ +#if !defined(CFG_RAMBOOT) + #if defined(CONFIG_RAM_AS_FLASH) + #define CFG_ENV_IS_NOWHERE + #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) + #define CFG_ENV_SIZE 0x2000 + #else + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) + #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ + #endif +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" +/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ +#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" +#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV | \ + CFG_CMD_LOADS )) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*Note: change below for your network setting!!! */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +# define CONFIG_ETHADDR 00:01:af:07:9b:8a +# define CONFIG_HAS_ETH1 +# define CONFIG_ETH1ADDR 00:01:af:07:9b:8b +# define CONFIG_HAS_ETH2 +# define CONFIG_ETH2ADDR 00:01:af:07:9b:8c +#endif + +#define CONFIG_SERVERIP 192.168.0.131 +#define CONFIG_IPADDR 192.168.0.105 +#define CONFIG_GATEWAYIP 0.0.0.0 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_HOSTNAME SBC8560 +#define CONFIG_ROOTPATH /home/ppc +#define CONFIG_BOOTFILE pImage + +#endif /* __CONFIG_H */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h new file mode 100644 index 0000000..d7d07a6 --- /dev/null +++ b/include/configs/sc520_cdp.h @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_X86 1 /* This is a X86 CPU */ +#define CONFIG_SC520 1 /* Include support for AMD SC520 */ +#define CONFIG_ALI152X 1 /* Include support for Ali 152x SIO */ + +#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ +#define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ +#define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */ + +/* define at most one of these */ +#undef CFG_SDRAM_CAS_LATENCY_2T +#define CFG_SDRAM_CAS_LATENCY_3T + +#define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ +#define CFG_RESET_GENERIC 1 /* use tripple-fault to reset cpu */ +#undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */ +#undef CFG_TIMER_SC520 /* use SC520 swtimers */ +#define CFG_TIMER_GENERIC 1 /* use the i8254 PIT timers */ +#undef CFG_TIMER_TSC /* use the Pentium TSC timers */ +#define CFG_USE_SIO_UART 0 /* prefer the uarts on the SIO to those + * in the SC520 on the CDP */ + +#define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) + + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_EEPROM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 15 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" +/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1024 /* incrementer freq: 1kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + + +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */ +#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */ + + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + + +/* Environment in EEPROM */ +#define CFG_ENV_IS_IN_EEPROM 1 +#define CONFIG_SPI +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/ +#define CFG_ENV_OFFSET 0 +#define CONFIG_SC520_CDP_USE_SPI /* Store configuration in the SPI part */ +#undef CONFIG_SC520_CDP_USE_MW /* Store configuration in the MicroWire part */ +#define CONFIG_SPI_X 1 + +/* + * JFFS2 partitions + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=SC520CDP Flash Bank #0" +#define MTDPARTS_DEFAULT "mtdparts=SC520CDP Flash Bank #0:-(jffs2)" +*/ + +/*----------------------------------------------------------------------- + * Device drivers + */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_PCNET +#define CONFIG_PCNET_79C973 +#define CONFIG_PCNET_79C975 +#define PCNET_HAS_PROM 1 + +/************************************************************ + * IDE/ATA stuff + ************************************************************/ +#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ +/*#define CFG_ATA_IDE1_OFFSET 0x0170 /###* ide1 offset */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ +#define CFG_ATA_BASE_ADDR 0 + +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* reset for ide unsupported... */ +#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ + +/************************************************************ + * ATAPI support (experimental) + ************************************************************/ +#define CONFIG_ATAPI /* enable ATAPI Support */ + +/************************************************************ + * DISK Partition support + ************************************************************/ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */ + +/************************************************************ + * Video/Keyboard support + ************************************************************/ +#define CONFIG_VIDEO /* To enable video controller support */ +#define CONFIG_I8042_KBD +#define CFG_ISA_IO 0 + + +/************************************************************ + * RTC + ***********************************************************/ +#define CONFIG_RTC_MC146818 +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * PCI stuff + */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW + +#define CFG_FIRST_PCI_IRQ 10 +#define CFG_SECOND_PCI_IRQ 9 +#define CFG_THIRD_PCI_IRQ 11 +#define CFG_FORTH_PCI_IRQ 15 + +#endif /* __CONFIG_H */ diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h new file mode 100644 index 0000000..a8e3555 --- /dev/null +++ b/include/configs/sc520_spunk.h @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_X86 1 /* This is a X86 CPU */ +#define CONFIG_SC520 1 /* Include support for AMD SC520 */ + +#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ +#define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ +#define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */ + +/* define at most one of these */ +#undef CFG_SDRAM_CAS_LATENCY_2T +#define CFG_SDRAM_CAS_LATENCY_3T + +#define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ +#define CFG_RESET_GENERIC 1 /* use tripple-fault to reset cpu */ +#undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */ +#undef CFG_TIMER_SC520 /* use SC520 swtimers */ +#define CFG_TIMER_GENERIC 1 /* use the i8254 PIT timers */ +#undef CFG_TIMER_TSC /* use the Pentium TSC timers */ + +#define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) + + +#define CONFIG_BAUDRATE 9600 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA | CFG_CMD_EEPROM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 15 +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) " +#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1024 /* incrementer freq: 1kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + + +#define CONFIG_SPI_EEPROM /* SPI EEPROMs such as AT25010 or AT25640 */ +#define CONFIG_MW_EEPROM /* MicroWire EEPROMS such as AT93LC46 */ +#define CONFIG_DS1722 /* Dallas DS1722 SPI Temperature probe */ + + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + + +#if 0 +/* Environment in flash */ +#define CFG_ENV_IS_IN_FLASH 1 +# define CFG_ENV_ADDR (0x387a0000) /* Addr of Environment Sector */ +# define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector (or 0x10000) */ +# define CFG_ENV_OFFSET 0 + +#else +/* Environment in EEPROM */ + +# define CFG_ENV_IS_IN_EEPROM 1 +# define CONFIG_SPI +# define CONFIG_SPI_X 1 +# define CFG_ENV_SIZE 0x2000 /* Total Size of Environment EEPROM */ +# define CFG_ENV_OFFSET 0x1c00 + +#endif + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=sc520_spunk-0" +#define MTDPARTS_DEFAULT "mtdparts=sc520_spunk-0:-(jffs2)" +*/ + +/*----------------------------------------------------------------------- + * Device drivers + */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +/************************************************************ + * IDE/ATA stuff + ************************************************************/ +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ +#define CFG_ATA_BASE_ADDR 0 +#define CFG_ATA_IDE0_OFFSET 0x01f0 /* ide0 offset */ +#define CFG_ATA_IDE1_OFFSET 0xe000 /* ide1 offset */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ + +#define CFG_FIRST_PCMCIA_BUS 1 + +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* reset for ide unsupported... */ +#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ + +#define CONFIG_IDE_TI_CARDBUS +#define CFG_PCMCIA_CIS_WIN 0x27f00000 +#define CFG_PCMCIA_CIS_WIN_SIZE 0x00100000 +#define CFG_PCMCIA_IO_WIN 0xe000 +#define CFG_PCMCIA_IO_WIN_SIZE 16 + +/************************************************************ + * DISK Partition support + ************************************************************/ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */ + + +/************************************************************ + * RTC + ***********************************************************/ +#define CONFIG_RTC_MC146818 +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * PCI stuff + */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW + +#define CFG_FIRST_PCI_IRQ 9 +#define CFG_SECOND_PCI_IRQ 10 +#define CFG_THIRD_PCI_IRQ 11 +#define CFG_FORTH_PCI_IRQ 12 + +#endif /* __CONFIG_H */ diff --git a/include/configs/sc520_spunk_rel.h b/include/configs/sc520_spunk_rel.h new file mode 100644 index 0000000..2e7a7e1 --- /dev/null +++ b/include/configs/sc520_spunk_rel.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _outer_config +#define _outer_config + +#include "sc520_spunk.h" + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "fsload boot/vmlinuz ; bootm" + +#endif diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h new file mode 100644 index 0000000..a4249c4 --- /dev/null +++ b/include/configs/scb9328.h @@ -0,0 +1,356 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + * 2003/13/06 Initial MP10 Support copied from wepep250 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ +#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ +#define CONFIG_SCB9328 1 /* on a scb9328tronix board */ +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ + +#define CONFIG_IMX_SERIAL1 +/* + * Select serial console configuration + */ + + +/* + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + & ~CFG_CMD_LOADS \ + & ~CFG_CMD_CONSOLE \ + & ~CFG_CMD_AUTOSCRIPT \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_DHCP \ + ) + +#include + +/* + * Boot options. Setting delay to -1 stops autostart count down. + * NOTE: Sending parameters to kernel depends on kernel version and + * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept + * parameters at all! Do not get confused by them so. + */ +#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" +#define CONFIG_BOOTCOMMAND "bootm 10040000" +#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_ETHADDR 80:81:82:83:84:85 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.10.10.9 +#define CONFIG_SERVERIP 10.10.10.10 + +/* + * General options for u-boot. Modify to save memory foot print + */ +#define CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "scb9328> " /* prompt string */ +#define CFG_CBSIZE 256 /* console I/O buffer */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ +#define CFG_MAXARGS 16 /* max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ + +#define CFG_MEMTEST_START 0x08100000 /* memtest test area */ +#define CFG_MEMTEST_END 0x08F00000 + +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* core clock - register value */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 115200 +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG 1 /* send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + + +/* + * Malloc pool need to host env + 128 Kb reserve for other allocations. + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_STACKSIZE (120<<10) /* stack size */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ +#endif + +/* SDRAM Setup Values +0x910a8300 Precharge Command CAS 3 +0x910a8200 Precharge Command CAS 2 + +0xa10a8300 AutoRefresh Command CAS 3 +0xa10a8200 Set AutoRefresh Command CAS 2 */ + +#define PRECHARGE_CMD 0x910a8200 +#define AUTOREFRESH_CMD 0xa10a8200 + +/* + * SDRAM Memory Map + */ +/* SH FIXME */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ +#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ + +/* + * Flash Controller settings + */ + +/* + * Hardware drivers + */ + + +/* + * Configuration for FLASH memory for the Synertronixx board + */ + +/* #define SCB9328_FLASH_32M */ + +/* 32MB */ +#ifdef SCB9328_FLASH_32M +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ +#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ +#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ +#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ +#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ +#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ +#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ +#else + +/* 16MB */ +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ +#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ +#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ +#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ +#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ +#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ +#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ +#endif /* SCB9328_FLASH_32M */ + +/* This should be defined if CFI FLASH device is present. Actually benefit + is not so clear to me. In other words we can provide more informations + to user, but this expects more complex flash handling we do not provide + now.*/ +#undef CFG_FLASH_CFI + +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ + +#define CFG_FLASH_BASE SCB9328_FLASH_BASE + +/* + * This is setting for JFFS2 support in u-boot. + * Right now there is no gain for user, but later on booting kernel might be + * possible. Consider using XIP kernel running from flash to save RAM + * footprint. + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 5 +#define CFG_JFFS2_NUM_BANKS 1 + +/* + * Environment setup. Definitions of monitor location and size with + * definition of environment setup ends up in 2 possibilities. + * 1. Embeded environment - in u-boot code is space for environment + * 2. Environment is read from predefined sector of flash + * Right now we support 2. possiblity, but expecting no env placed + * on mentioned address right now. This also needs to provide whole + * sector for it - for us 256Kb is really waste of memory. U-boot uses + * default env. and until kernel parameters could be sent to kernel + * env. has no sense to us. + */ + +/* Setup for PA23 which is Reset Default PA23 but has to become + CS5 */ + +#define CFG_GPR_A_VAL 0x00800000 +#define CFG_GIUS_A_VAL 0x0043fffe + +#define CFG_MONITOR_BASE 0x10000000 +#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */ +#define CFG_ENV_SIZE 0x20000 + +#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ + +/* + * CSxU_VAL: + * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 + * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | + * + * CSxL_VAL: + * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 + * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| + */ + +#define CFG_CS0U_VAL 0x000F2000 +#define CFG_CS0L_VAL 0x11110d01 +#define CFG_CS1U_VAL 0x000F0a00 +#define CFG_CS1L_VAL 0x11110601 +#define CFG_CS2U_VAL 0x0 +#define CFG_CS2L_VAL 0x0 + +#define CFG_CS3U_VAL 0x000FFFFF +#define CFG_CS3L_VAL 0x00000303 + +#define CFG_CS4U_VAL 0x000F0a00 +#define CFG_CS4L_VAL 0x11110301 + +/* CNC == 3 too long + #define CFG_CS5U_VAL 0x0000C210 */ + +/* #define CFG_CS5U_VAL 0x00008400 + mal laenger mahcen, ob der bei 150MHz laenger haelt dann und + kaum langsamer ist */ +/* #define CFG_CS5U_VAL 0x00009400 + #define CFG_CS5L_VAL 0x11010D03 */ + +#define CFG_CS5U_VAL 0x00008400 +#define CFG_CS5L_VAL 0x00000D03 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x16000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4) +/* #define CONFIG_DM9000_USE_8BIT */ +#define CONFIG_DM9000_USE_16BIT +/* #define CONFIG_DM9000_USE_32BIT */ + +/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) + f_ref=16,777MHz + + 0x002a141f: 191,9944MHz + 0x040b2007: 144MHz + 0x042a141f: 96MHz + 0x0811140d: 64MHz + 0x040e200e: 150MHz + 0x00321431: 200MHz + + 0x08001800: 64MHz mit 16er Quarz + 0x04001800: 96MHz mit 16er Quarz + 0x04002400: 144MHz mit 16er Quarz + + 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 + |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ + +#define CPU200 + +#ifdef CPU200 +#define CFG_MPCTL0_VAL 0x00321431 +#else +#define CFG_MPCTL0_VAL 0x040e200e +#endif + +/* #define BUS64 */ +#define BUS72 + +#ifdef BUS72 +#define CFG_SPCTL0_VAL 0x04002400 +#endif + +#ifdef BUS96 +#define CFG_SPCTL0_VAL 0x04001800 +#endif + +#ifdef BUS64 +#define CFG_SPCTL0_VAL 0x08001800 +#endif + +/* Das ist der BCLK Divider, der aus der System PLL + BCLK und HCLK erzeugt: + 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 + 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 + 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 + 0x2f001003 : 192MHz/5=38,4MHz + 0x2f000003 : 64MHz/1 + Bit 22: SPLL Restart + Bit 21: MPLL Restart */ + +#ifdef BUS64 +#define CFG_CSCR_VAL 0x2f030003 +#endif + +#ifdef BUS72 +#define CFG_CSCR_VAL 0x2f030403 +#endif + +/* + * Well this has to be defined, but on the other hand it is used differently + * one may expect. For instance loadb command do not cares :-) + * So advice is - do not relay on this... + */ +#define CFG_LOAD_ADDR 0x08400000 + +#define MHZ16QUARZINUSE + +#ifdef MHZ16QUARZINUSE +#define CONFIG_SYSPLL_CLK_FREQ 16000000 +#else +#define CONFIG_SYSPLL_CLK_FREQ 16780000 +#endif + +#define CONFIG_SYS_CLK_FREQ 16780000 + +/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ +#define CFG_FMCR_VAL 0x00000001 + +/* Bit[0:3] contain PERCLK1DIV for UART 1 + 0x000b00b ->b<- -> 192MHz/12=16MHz + 0x000b00b ->8<- -> 144MHz/09=16MHz + 0x000b00b ->3<- -> 64MHz/4=16MHz */ + +#ifdef BUS96 +#define CFG_PCDR_VAL 0x000b00b5 +#endif + +#ifdef BUS64 +#define CFG_PCDR_VAL 0x000b00b3 +#endif + +#ifdef BUS72 +#define CFG_PCDR_VAL 0x000b00b8 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/shannon.h b/include/configs/shannon.h new file mode 100644 index 0000000..572985b --- /dev/null +++ b/include/configs/shannon.h @@ -0,0 +1,216 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Configuation settings for the Shannon/TuxScreen/IS2630 WebPhone Board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Since we use the Inferno-Loader to bring us to live, + * we skip the lowlevel init stuff. + * But U-Boot still relocates itself into RAM + */ +#define CONFIG_INFERNO /* we are using the inferno bootldr */ +#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#undef CONFIG_SKIP_RELOCATE_UBOOT + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SA1100 1 /* This is an SA1100 CPU */ +#define CONFIG_SHANNON 1 /* on an SHANNON/TuxScreen Board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_3C589 1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL3 1 /* we use SERIAL 3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#if 0 /* XXX - cannot test IDE anyway, so disabled for now - wd */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_IDE) +#endif /* 0 */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_BOOTCOMMAND "help" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "TuxScreen # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xd0000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x09 /* 190 MHz for Shannon */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_DOS_PARTITION 1 /* DOS partitiion support */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +/* BE CAREFUL */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of EDORAM */ +#define PHYS_SDRAM_1 0xc0000000 /* RAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x00400000 /* 4 MB */ +#define PHYS_SDRAM_2 0xc8000000 /* RAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00400000 /* 4 MB */ +#define PHYS_SDRAM_3 0xd0000000 /* RAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00400000 /* 4 MB */ +#define PHYS_SDRAM_4 0xd8000000 /* RAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00400000 /* 4 MB */ + + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (31+4) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#ifdef CONFIG_INFERNO +/* we take the last sector, 128 KB in size, but we only use 4 KB of it for stack reasons */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x003E0000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#else +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ + +/* we pick the upper one */ + +#define CONFIG_PCMCIA_SLOT_A + +#define CFG_PCMCIA_IO_ADDR (0x20000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0x24000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0x2C000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_MEM_ADDR (0x28000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) + +/* in fact, MEM and ATTRB are swapped - has to be corrected soon in cmd_pcmcia or so */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +/* it's simple, all regs are in I/O space */ +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_ATTRB_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 0 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET 0 + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0 + +/*----------------------------------------------------------------------- + */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h new file mode 100644 index 0000000..a137f9d --- /dev/null +++ b/include/configs/smdk2400.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Gary Jennejohn + * + * Configuation settings for the SAMSUNG board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T core */ +#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ +#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SAMSUNG */ + +#undef CONFIG_HWFLOW /* include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* enable modem initialization stuff */ + +/* + * The following enables modem debugging stuff. The dbg() and + * 'char screen[1024]' are used for debug printfs. Unfortunately, + * it is usable only from BDI + */ +#undef CONFIG_MODEM_SUPPORT_DEBUG + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ + +/* Use s3c2400's RTC */ +#define CONFIG_RTC_S3C24X0 1 + +#ifndef USE_920T_MMU +#define CONFIG_COMMANDS_tmp ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \ + CFG_CMD_DATE | \ + CFG_CMD_SNTP ) +#else +#define CONFIG_COMMANDS_tmp (CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_SNTP ) +#endif + +#ifdef CONFIG_HWFLOW +#define CONFIG_COMMANDS (CONFIG_COMMANDS_tmp | CFG_CMD_HWFLOW) +#else +#define CONFIG_COMMANDS CONFIG_COMMANDS_tmp +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#if 0 +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#endif +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 134.98.93.36 +#define CONFIG_SERVERIP 134.98.93.22 +#if 0 +#define CONFIG_BOOTFILE "elinos-lart" +#define CONFIG_BOOTCOMMAND "tftp; bootm" +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SMDK2400 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0c000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0e000000 /* 32 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x0cf00000 /* default load address */ + +/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ +/* it to wrap 100 times (total 1562500) to get 1 sec. */ +#define CFG_HZ 1562500 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) +#define CFG_ENV_SIZE 0x40000 + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#endif /* __CONFIG_H */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h new file mode 100644 index 0000000..7edec0d --- /dev/null +++ b/include/configs/smdk2410.h @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Gary Jennejohn + * David Mueller + * + * Configuation settings for the SAMSUNG SMDK2410 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ +#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */ + + +#define USE_920T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x19000300 +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ + +/************************************************************ + * RTC + ************************************************************/ +#define CONFIG_RTC_S3C24X0 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +/*********************************************************** + * Command definition + ***********************************************************/ +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + /*CFG_CMD_NAND |*/ \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ +/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1 +/*#define CONFIG_BOOTFILE "elinos-lart" */ +/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x33000000 /* default load address */ + +/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ +/* it to wrap 100 times (total 1562500) to get 1 sec. */ +#define CFG_HZ 1562500 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ +#if 0 +#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ +#endif + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ +#endif +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ +#endif + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h new file mode 100644 index 0000000..3d907f8 --- /dev/null +++ b/include/configs/sorcery.h @@ -0,0 +1,297 @@ +/* + * (C) Copyright 2004 + * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC8220 1 +#define CONFIG_SORCERY 1 /* Sorcery board */ + +/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to + determine the CPU speed. */ +#define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ +#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */ + +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* PCI */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 + +#define CONFIG_PCI_MEM_BUS 0x80000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x71000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_PCI_CFG_BUS 0x70000000 +#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS +#define CONFIG_PCI_CFG_SIZE 0x01000000 + +/* + * Supported commands + */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP | \ + 0) + +/* CFG_CMD_MII | \ */ +/* CFG_CMD_USB | \ */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Default Environment + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_HOSTNAME sorcery + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ + ":$hostname:$netdev:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm $kernel_addr\0" \ + "flash_self=run ramargs addip;" \ + "bootm $kernel_addr $ramdisk_addr\0" \ + "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/sorcery/uImage\0" \ + "kernel_addr=FFE00000\0" \ + "ramdisk_addr=FFB00000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_NET_MULTI +#define CONFIG_EEPRO100 + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_MODULE 1 +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Flexbus Chipselect configuration + * Beware: Some CS# seem to be mandatory (if these CS# are not set, + * board can hang-up in unpredictable place). + * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS# + */ + +/* Flash */ +#define CFG_CS0_BASE 0xf800 +#define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */ +#define CFG_CS0_CTRL 0x001019c0 + +/* NVM */ +#define CFG_CS1_BASE 0xf7e8 +#define CFG_CS1_MASK 0x00040000 /* 256K */ +#define CFG_CS1_CTRL 0x00101940 /* 8bit port size */ + +/* Atlas2 + Gemini */ +#define CFG_CS2_BASE 0xf7e7 +#define CFG_CS2_MASK 0x00010000 /* 64K*/ +#define CFG_CS2_CTRL 0x001011c0 /* 16bit port size */ + +/* CAN Controller */ +#define CFG_CS3_BASE 0xf7e6 +#define CFG_CS3_MASK 0x00010000 /* 64K */ +#define CFG_CS3_CTRL 0x00102140 /* 8Bit port size */ + +/* Foreign interface */ +#define CFG_CS4_BASE 0xf7e5 +#define CFG_CS4_MASK 0x00010000 /* 64K */ +#define CFG_CS4_CTRL 0x00101dc0 /* 16bit port size */ + +/* CPLD */ +#define CFG_CS5_BASE 0xf7e4 +#define CFG_CS5_MASK 0x00010000 /* 64K */ +#define CFG_CS5_CTRL 0x001000c0 /* 16bit port size */ + +#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) +#define CFG_FLASH_BASE (CFG_FLASH0_BASE) + +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ + CFG_FLASH_BASE+0x04000000 } /* two banks */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000000 - 0x40000) +#define CFG_ENV_SIZE 0x4000 /* 16K */ +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + 0x20000) +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +#define CONFIG_ENV_OVERWRITE 1 + +#if defined CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_EEPROM +#elif defined CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_IN_EEPROM +#elif defined CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#endif + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 +#define CFG_SRAM_BASE (CFG_MBAR + 0x20000) +#define CFG_SRAM_SIZE 0x8000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) +#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* SDRAM configuration (for SPD) */ +#define CFG_SDRAM_TOTAL_BANKS 1 +#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */ +#define CFG_SDRAM_SPD_SIZE 0x100 +#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ + +/* SDRAM drive strength register (for SSTL_2 class II)*/ +#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT)) + +/* + * Ethernet configuration + */ +#define CONFIG_MPC8220_FEC 1 +#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ +#define CONFIG_PHY_ADDR 0x1F + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 + +/* +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h new file mode 100644 index 0000000..96cb6e4 --- /dev/null +++ b/include/configs/spieval.h @@ -0,0 +1,548 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ +#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ +#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ +#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#ifdef CONFIG_STK52XX +#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */ +#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ +#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ +#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ +#define CONFIG_BOARD_EARLY_INIT_R +#endif /* CONFIG_STK52XX */ + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +#ifdef CONFIG_STK52XX +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +/* #define CONFIG_PCI_SCAN_SHOW 1 */ + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 +#endif /* CONFIG_STK52XX */ + +#ifdef CONFIG_PCI +#define ADD_PCI_CMD CFG_CMD_PCI +#else +#define ADD_PCI_CMD 0 +#endif + +/* + * Video console + */ +#if 1 +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SM501 +#define CONFIG_VIDEO_SM501_32BPP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CFG_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_VIDEO +#define ADD_BMP_CMD CFG_CMD_BMP +#else +#define ADD_BMP_CMD 0 +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* USB */ +#ifdef CONFIG_STK52XX +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_I2C) + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +/* preserve space for the post_word at end of on-chip SRAM */ +#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +/* IDE */ +#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) +#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) +#else +#define ADD_IDE_CMD 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_BMP_CMD | \ + ADD_IDE_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_TIMESTAMP /* display image timestamps */ + +#if (TEXT_BASE == 0xFC000000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#if defined (CONFIG_TQM5200_AA) +# define CONFIG_U_BOOT_SUFFIX "-AA\0" +#elif defined (CONFIG_TQM5200_AB) +# define CONFIG_U_BOOT_SUFFIX "-AB\0" +#elif defined (CONFIG_TQM5200_AC) +# define CONFIG_U_BOOT_SUFFIX "-AC\0" +#else +# define CONFIG_U_BOOT_SUFFIX "\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "bootfile=/tftpboot/tqm5200/uImage\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC05FFFF\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if defined(CFG_IPBSPEED_133) +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. + */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#ifdef CONFIG_TQM5200_REV100 +#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ +#else +#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ +#endif + +/* + * I2C clock frequency + * + * Please notice, that the resulting clock frequency could differ from the + * configured value. This is because the I2C clock is derived from system + * clock over a frequency divider with only a few divider values. U-boot + * calculates the best approximation for CFG_I2C_SPEED. However the calculated + * approximation allways lies below the configured value, never above. + */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work + * also). For other EEPROMs configuration should be verified. On Mini-FAP the + * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the + * same configuration could be used. + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* + * HW-Monitor configuration on Mini-FAP + */ +#if defined (CONFIG_MINIFAP) +#define CFG_I2C_HWMON_ADDR 0x2C +#endif + +/* List of I2C addresses to be verified by POST */ +#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB) +#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ + CFG_I2C_SLAVE } +#elif defined (CONFIG_TQM5200_AC) +#define I2C_ADDR_LIST { CFG_I2C_SLAVE } +#endif + +#if defined (CONFIG_MINIFAP) +#undef I2C_ADDR_LIST +#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ + CFG_I2C_HWMON_ADDR, \ + CFG_I2C_SLAVE } +#endif + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ + +/* use CFI flash driver if no module variant is spezified */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ + +#if !defined(CFG_LOWBOOT) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) +#else /* CFG_LOWBOOT */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) +#endif /* CFG_LOWBOOT */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + * + * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): + * Bit 0 (mask: 0x80000000): 1 + * use ALT CAN position: Bits 2-3 (mask: 0x30000000): + * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. + * Use for REV200 STK52XX boards. Do not use with REV100 modules + * (because, there I2C1 is used as I2C bus) + * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 + * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) + * 000 -> All PSC2 pins are GIOPs + * 001 -> CAN1/2 on PSC2 pins + * Use for REV100 STK52xx boards + * use PSC6: + * on STK52xx: + * use as UART. Pins PSC6_0 to PSC6_3 are used. + * Bits 9:11 (mask: 0x00700000): + * 101 -> PSC6 : Extended POST test is not available + * on MINI-FAP and TQM5200_IB: + * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): + * 000 -> PSC6 could not be used as UART, CODEC or IrDA + * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST + * tests. + */ +#if defined (CONFIG_MINIFAP) +# define CFG_GPS_PORT_CONFIG 0x91000004 +#elif defined (CONFIG_STK52XX) +# if defined (CONFIG_STK52XX_REV100) +# define CFG_GPS_PORT_CONFIG 0x81500014 +# else /* STK52xx REV200 and above */ +# if defined (CONFIG_TQM5200_REV100) +# error TQM5200 REV100 not supported on STK52XX REV200 or above +# else/* TQM5200 REV200 and above */ +# define CFG_GPS_PORT_CONFIG 0x91500004 +# endif +# endif +#else /* TMQ5200 Inbetriebnahme-Board */ +# define CFG_GPS_PORT_CONFIG 0x81000004 +#endif + +/* + * RTC configuration + */ +#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Enable an alternate, more extensive memory test */ +#define CFG_ALT_MEMTEST + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#ifdef CFG_PCISPEED_66 +#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ +#else +#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ +#endif +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* automatic configuration of chip selects */ +#ifdef CONFIG_CS_AUTOCONF +#define CONFIG_LAST_STAGE_INIT +#endif + +/* + * SRAM - Do not map below 2 GB in address space, because this area is used + * for SDRAM autosizing. + */ +#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF) +#define CFG_CS2_START 0xE5000000 +#ifdef CONFIG_TQM5200_AB +#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ +#else /* CONFIG_CS_AUTOCONF */ +#define CFG_CS2_SIZE 0x100000 /* 1 MByte */ +#endif +#define CFG_CS2_CFG 0x0004D930 +#endif + +/* + * Grafic controller - Do not map below 2 GB in address space, because this + * area is used for SDRAM autosizing. + */ +#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \ + defined (CONFIG_CS_AUTOCONF) +#define SM501_FB_BASE 0xE0000000 +#define CFG_CS1_START (SM501_FB_BASE) +#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ +#define CFG_CS1_CFG 0x8F48FF70 +#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 +#endif + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h new file mode 100644 index 0000000..e218597 --- /dev/null +++ b/include/configs/stxgp3.h @@ -0,0 +1,389 @@ +/* + * (C) Copyright 2003 Embedded Edge, LLC + * Dan Malek + * Copied from ADS85xx. + * Updates for Silicon Tx GP3 8560 board. + * + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* mpc8560ads board configuration file */ +/* please refer to doc/README.mpc85xx for more info */ +/* make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_CPM2 1 /* has CPM2 */ +#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ + +#undef CONFIG_PCI /* pci ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support*/ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + + +/* sysclk for MPC85xx + */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ + +/* Blinkin' LEDs for Robert :-) +*/ +#define CONFIG_SHOW_ACTIVITY 1 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* Localbus SDRAM is an option, not all boards have it. + * This address, however, is used to configure a 256M local bus + * window that includes the Config latch below. + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ + +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ + +#define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 136 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* The configuration latch is Chip Select 1. + * It's an 8-bit latch in the lower 8 bits of the word. + */ +#define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */ +#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ +#define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#ifdef CFG_RAMBOOT +#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ +#else +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif +#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ + +#undef CONFIG_CLOCKS_IN_MHZ + +/* local bus definitions */ +#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ +#define CFG_OR2_PRELIM 0xfc006901 +#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ +#define CFG_LBC_LBCR 0x00000000 +#define CFG_LBC_LSRT 0x20000000 +#define CFG_LBC_MRTPR 0x20000000 +#define CFG_LBC_LSDMR_1 0x2861b723 +#define CFG_LBC_LSDMR_2 0x0861b723 +#define CFG_LBC_LSDMR_3 0x0861b723 +#define CFG_LBC_LSDMR_4 0x1861b723 +#define CFG_LBC_LSDMR_5 0x4061b723 + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ + +#define CONFIG_BAUDRATE 38400 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#if 0 +#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */ +#else +/* I did the 'if 0' so we could keep the syntax above if ever needed. */ +#undef CFG_I2C_NOPROBES +#endif + +/* RapdIO Map configuration, mapped 1:1. +*/ +#define CFG_RIO_MEM_BASE 0xc0000000 +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x200000000 /* 512 M */ + +/* Standard 8560 PCI addressing, mapped 1:1. +*/ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */ + +#if defined(CONFIG_PCI) /* PCI Ethernet card */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ + +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPS85XX_FEC + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 4 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define CONFIG_ETHPRIME "TSEC0" + +#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ + +#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + +#if (CONFIG_ETHER_INDEX == 2) + /* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers + * - Full duplex + */ + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CFG_CPMFCR_RAMTYPE 0 +#if 0 + #define CFG_FCC_PSMR (FCC_PSMR_FDE) +#else + #define CFG_FCC_PSMR 0 +#endif + #define FETH2_RST 0x01 +#elif (CONFIG_ETHER_INDEX == 3) + /* need more definitions here for FE3 */ + #define FETH3_RST 0x80 +#endif /* CONFIG_ETHER_INDEX */ + +/* MDIO is done through the TSEC0 control. +*/ +#define CONFIG_MII /* MII PHY management */ +#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ + +#endif + +/* Environment */ +/* We use the top boot sector flash, so we have some 16K sectors for env + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) + #define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" +#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000" +#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV | \ + CFG_CMD_LOADS )) + #elif defined(CONFIG_TSEC_ENET) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \ + CFG_CMD_MII | CFG_CMD_I2C ) & \ + ~(CFG_CMD_ENV)) + #elif defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) + #elif defined(CONFIG_TSEC_ENET) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \ + CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C) + #elif defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) + #endif +#endif +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*Note: change below for your network setting!!! */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c +#endif + +#define CONFIG_SERVERIP 192.168.85.1 +#define CONFIG_IPADDR 192.168.85.60 +#define CONFIG_GATEWAYIP 192.168.85.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_HOSTNAME STX_GP3 +#define CONFIG_ROOTPATH /gppproot +#define CONFIG_BOOTFILE uImage +#define CONFIG_LOADADDR 0x1000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h new file mode 100644 index 0000000..3ffe6b2 --- /dev/null +++ b/include/configs/stxxtc.h @@ -0,0 +1,588 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com + * U-Boot port on STx XTc 8xx board + * Mostly copied from Panto's NETTA2 board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC875 1 /* This is a MPC875 CPU */ +#define CONFIG_STXXTC 1 /* ...on a STx XTc board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */ + +#define CONFIG_XIN 10000000 /* 10 MHz input xtal */ + +/* Select one of few clock rates defined later in this file. +*/ +/* #define MPC8XX_HZ 50000000 */ +#define MPC8XX_HZ 66666666 + +#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_AUTOSCRIPT +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) + +#undef CONFIG_MAC_PARTITION +#undef CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define FEC_ENET 1 /* eth.c needs it that way... */ +#undef CFG_DISCOVER_PHY +#define CONFIG_MII 1 +#undef CONFIG_RMII + +#define CONFIG_ETHER_ON_FEC1 1 +#define CONFIG_FEC1_PHY 1 /* phy address of FEC */ +#undef CONFIG_FEC1_PHY_NORXERR + +#define CONFIG_ETHER_ON_FEC2 1 +#define CONFIG_FEC2_PHY 3 +#undef CONFIG_FEC2_PHY_NORXERR + +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_NAND | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_MII | \ + CFG_CMD_NFS) + +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "xtc> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif + +/* yes this is weird, I know :) */ +#define CFG_MONITOR_BASE (CFG_FLASH_BASE | 0x00F00000) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_RESET_ADDRESS 0x80000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x10000 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 + +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000) +#define CFG_ENV_OFFSET_REDUND 0 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 } + +#define CFG_FLASH_PROTECTION + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + */ + +#if CONFIG_XIN == 10000000 + +#if MPC8XX_HZ == 50000000 +#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#elif MPC8XX_HZ == 66666666 +#define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ + (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ + PLPRCR_TEXPS) +#else +#error unsupported CPU freq for XIN = 10MHz +#endif +#else +#error unsupported freq for XIN (must be 10MHz) +#endif + + +/* + *----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + * + * Note: When TBS == 0 the timebase is independent of current cpu clock. + */ + +#define SCCR_MASK SCCR_EBDF11 +#if MPC8XX_HZ > 66666666 +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00 | SCCR_EBDF01) +#else +#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) +#endif + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ + +#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */ + +#define CFG_REMAP_OR_AM 0x80000000 +#define CFG_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH) +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) + +/* + * BR4 and OR4 (SDRAM) + * + */ +#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) + +#define CFG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) +#define CFG_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) + +/* + * Memory Periodic Timer Prescaler + */ + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + */ + +#define CFG_MAMR_PTA 234 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ + +/****************************************************************/ + +#define NAND_SIZE 0x00010000 /* 64K */ +#define NAND_BASE 0xF1000000 + +/****************************************************************/ + +/* NAND */ +#define CFG_NAND_BASE NAND_BASE +#define CONFIG_MTD_NAND_ECC_JFFS2 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_MTD_NAND_UNSAFE + +#define CFG_MAX_NAND_DEVICE 1 +#undef NAND_NO_RB + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ +#define NAND_DISABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \ + } while(0) + +#define NAND_ENABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \ + } while(0) + +#define NAND_CTL_CLRALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \ + } while(0) + +#define NAND_CTL_SETALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \ + } while(0) + +#define NAND_CTL_CLRCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \ + } while(0) + +#define NAND_CTL_SETCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \ + } while(0) + +#ifndef NAND_NO_RB +#define NAND_WAIT_READY(nand) \ + do { \ + int _tries = 0; \ + while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \ + if (++_tries > 100000) \ + break; \ + } while (0) +#else +#define NAND_WAIT_READY(nand) udelay(12) +#endif + +#define WRITE_NAND_COMMAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND_ADDRESS(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define READ_NAND(adr) \ + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) + +/*****************************************************************************/ + +#define CFG_DIRECT_FLASH_TFTP +#define CFG_DIRECT_NAND_TFTP + +/*****************************************************************************/ + +/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB, + * CxOE and CxRESET. We use the CxOE. + */ +#define STATUS_LED_BIT 0x00000080 /* bit 24 */ + +#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_BLINKING + +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#ifndef __ASSEMBLY__ + +/* LEDs */ + +/* led_id_t is unsigned int mask */ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \ + else \ + ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \ + } while(0) + +#define __led_init(msk, st) __led_set(msk, st) + +#endif + +/******************************************************************************/ + +#define CFG_CONSOLE_IS_IN_ENV 1 +#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 +#define CFG_CONSOLE_ENV_OVERWRITE 1 + +/******************************************************************************/ + +/* use board specific hardware */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_SHOW_ACTIVITY + +/*****************************************************************************/ + +#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_CRC32_VERIFY 1 +#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 + +/*****************************************************************************/ + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,MPC870@0" +#define OF_TBCLK (MPC8XX_HZ / 16) + +#endif /* __CONFIG_H */ diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h new file mode 100644 index 0000000..1ee6be1 --- /dev/null +++ b/include/configs/suzaku.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MICROBLAZE 1 /* This is an MicroBlaze CPU */ +#define CONFIG_SUZAKU 1 /* on an SUZAKU Board */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x80000000 +#define CFG_SDRAM_SIZE 0x01000000 +#define CFG_FLASH_BASE 0xfff00000 +#define CFG_FLASH_SIZE 0x00400000 +#define CFG_RESET_ADDRESS 0xfff00100 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024)) +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 115200 } + +#define CONFIG_COMMANDS (CONFIG__CMD_DFL) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_UART1_BASE (0xFFFF2000) +#define CONFIG_SERIAL_BASE CFG_UART1_BASE + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SUZAKU> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ + +#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* default load address */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 1 /* max number of sectors on one chip */ + +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_ENV_IS_NOWHERE 1 +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ + +#define CFG_INIT_RAM_ADDR 0x80000000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#endif /* __CONFIG_H */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h new file mode 100644 index 0000000..7118f3f --- /dev/null +++ b/include/configs/svm_sc8xx.h @@ -0,0 +1,470 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific, + * for SinoVee Microsystems SC8xx series SBC + * http://www.fel.com.cn (Chinese) + * http://www.sinovee.com (English) + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Custom configuration */ +/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */ +/* SC85T,SC860T, FEL8xx-AT(855T/860T) */ +/*#define CONFIG_FEL8xx_AT */ +/*#define CONFIG_LCD */ +/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ +/* #define CONFIG_50MHz */ +/* #define CONFIG_66MHz */ +/* #define CONFIG_75MHz */ +#define CONFIG_80MHz +/*#define CONFIG_100MHz */ +/* #define CONFIG_BUS_DIV2 1 */ +/* for BOOT device port size */ +/* #define CONFIG_BOOT_8B */ +#define CONFIG_BOOT_16B +/* #define CONFIG_BOOT_32B */ +/* #define CONFIG_CAN_DRIVER */ +/* #define DEBUG */ +#define CONFIG_FEC_ENET + +/* #define CONFIG_SDRAM_16M */ +#define CONFIG_SDRAM_32M +/* #define CONFIG_SDRAM_64M */ +#define CFG_RESET_ADDRESS 0xffffffff +/* + * High Level Configuration Options + * (easy to change) + */ + +/* #define CONFIG_MPC823 1 */ +/* #define CONFIG_MPC850 1 */ +#define CONFIG_MPC855 1 +/* #define CONFIG_MPC860 1 */ +/* #define CONFIG_MPC860T 1 */ + +#undef CONFIG_WATCHDOG /* watchdog */ + +#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ + +#ifdef CONFIG_LCD /* with LCD controller ? */ +/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ +#endif + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ + "bootfile=pImage-sc855t\0" \ + "kernel_addr=48000000\0" \ + "ramdisk_addr=48100000\0" \ + "" +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + + +#ifdef CONFIG_LCD +# undef CONFIG_STATUS_LED /* disturbs display */ +#else +# define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#endif /* CONFIG_LCD */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ +/* CFG_CMD_IDE |*/ \ + CFG_CMD_DATE ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 + +#ifdef CONFIG_BOOT_8B +#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#elif defined (CONFIG_BOOT_16B) +#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#elif defined (CONFIG_BOOT_32B) +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#endif + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +/*#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +*/ +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR 0xffffff88 +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +/*#define CFG_SIUMCR 0x00610c00 */ +#define CFG_SIUMCR 0x00000000 +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR 0x0001 + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC 0x00c3 + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR 0x0000 + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#if defined (CONFIG_100MHz) +#define CFG_PLPRCR 0x06301000 +#define CONFIG_8xx_GCLK_FREQ 100000000 +#elif defined (CONFIG_80MHz) +#define CFG_PLPRCR 0x04f01000 +#define CONFIG_8xx_GCLK_FREQ 80000000 +#elif defined(CONFIG_75MHz) +#define CFG_PLPRCR 0x04a00100 +#define CONFIG_8xx_GCLK_FREQ 75000000 +#elif defined(CONFIG_66MHz) +#define CFG_PLPRCR 0x04101000 +#define CONFIG_8xx_GCLK_FREQ 66000000 +#elif defined(CONFIG_50MHz) +#define CFG_PLPRCR 0x03101000 +#define CONFIG_8xx_GCLK_FREQ 50000000 +#endif + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#ifdef CONFIG_BUS_DIV2 +#define CFG_SCCR 0x02020000 | SCCR_RTSEL +#else /* up to 50 MHz we use a 1:1 clock */ +#define CFG_SCCR 0x02000000 | SCCR_RTSEL +#endif + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xFE100010 +#define CFG_ATA_IDE0_OFFSET 0x0000 +/*#define CFG_ATA_IDE1_OFFSET 0x0C00 */ +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O + */ +#define CFG_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses + */ +#define CFG_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers + */ +#define CONFIG_ATAPI +#define CFG_PIO_MODE 0 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +/*#define CFG_DER 0x2002000F*/ +#define CFG_DER 0x0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#if defined(CONFIG_100MHz) +#define CFG_OR_TIMING_FLASH 0x000002f4 +#define CFG_OR_TIMING_DOC 0x000002f4 +#define CFG_MxMR_PTx 0x61000000 +#define CFG_MPTPR 0x400 + +#elif defined(CONFIG_80MHz) +#define CFG_OR_TIMING_FLASH 0x00000ff4 +#define CFG_OR_TIMING_DOC 0x000001f4 +#define CFG_MxMR_PTx 0x4e000000 +#define CFG_MPTPR 0x400 + +#elif defined(CONFIG_75MHz) +#define CFG_OR_TIMING_FLASH 0x000008f4 +#define CFG_OR_TIMING_DOC 0x000002f4 +#define CFG_MxMR_PTx 0x49000000 +#define CFG_MPTPR 0x400 + +#elif defined(CONFIG_66MHz) +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) +/*#define CFG_OR_TIMING_FLASH 0x000001f4 */ +#define CFG_OR_TIMING_DOC 0x000003f4 +#define CFG_MxMR_PTx 0x40000000 +#define CFG_MPTPR 0x400 + +#else /* 50 MHz */ +#define CFG_OR_TIMING_FLASH 0x00000ff4 +#define CFG_OR_TIMING_DOC 0x000001f4 +#define CFG_MxMR_PTx 0x30000000 +#define CFG_MPTPR 0x400 +#endif /*CONFIG_??MHz */ + + +#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */ +#define CFG_OR0_PRELIM (0xffe00000 | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) +#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */ +#define CFG_OR0_PRELIM (0xffc00000 | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) +#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */ +#define CFG_OR0_PRELIM (0xfc000000 | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) +#else +#error Boot device port size missing. +#endif + +/* + * Disk-On-Chip configuration + */ + +#define CFG_DOC_SHORT_TIMEOUT +#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ + +#define CFG_DOC_SUPPORT_2000 +#define CFG_DOC_SUPPORT_MILLENNIUM +#define CFG_DOC_BASE 0x80000000 + + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h new file mode 100644 index 0000000..dac1eb7 --- /dev/null +++ b/include/configs/tb0229.h @@ -0,0 +1,177 @@ +/* + * (C) Copyright 2003 + * Masami Komiya + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Config header file for TANBAC TB0229 board using an VR4131 CPU module + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ +#define CONFIG_TB0229 1 /* on a TB0229 Board */ + +#ifndef CPU_CLOCK_RATE +#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */ +#endif +#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"boot\" for the network boot using DHCP, TFTP and NFS;" \ + "echo Type \"run netboot_initrd\" for the network boot with initrd;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_local\" to mount local root filesystem;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netboot=dhcp;tftp;run netargs; bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \ + "localargs=setenv bootargs root=1F02 ip=dhcp\0" \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "read-only=readonly\0" \ + "netargs=run nfsargs addmisc\0" \ + "flash_nfs=run nfsargs addmisc;" \ + "bootm ${kernel_addr}\0" \ + "flash_local=run localargs addmisc;" \ + "bootm ${kernel_addr}\0" \ + "netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \ + "setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\ + "run addmisc;" \ + "bootm 80400000 80600000\0" \ + "rootpath=/export/miniroot-mipsel\0" \ + "autoload=no\0" \ + "kernel_addr=BFC60000\0" \ + "ramdisk_addr=B0100000\0" \ + "u-boot=u-boot.bin\0" \ + "bootfile=uImage\0" \ + "load=dhcp;tftp 80400000 ${u-boot}\0" \ + "load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \ + "update_uboot=run load;" \ + "protect off BFC00000 BFC3FFFF;" \ + "erase BFC00000 BFC3FFFF;" \ + "cp.b 80400000 BFC00000 ${filesize}\0" \ + "update_kernel=run load_kernel;" \ + "erase BFC60000 BFD5FFFF;" \ + "cp.b 80400000 BFC60000 ${filesize}\0" \ + "initenv=erase bfc40000 bfc5ffff\0" \ + "" +/*#define CONFIG_BOOTCOMMAND "run flash_local" */ +#define CONFIG_BOOTCOMMAND "run netboot" + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_PCI | \ + CFG_CMD_ELF ) +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "# " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ + +#define CFG_MALLOC_LEN 128*1024 + +#define CFG_BOOTPARAMS_LEN 128*1024 + +#define CFG_HZ (CPU_TCLOCK_RATE/4) + +#define CFG_SDRAM_BASE 0x80000000 + +#define CFG_LOAD_ADDR 0x80400000 /* default load address */ + +#define CFG_MEMTEST_START 0x80000000 +#define CFG_MEMTEST_END 0x80800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ + +#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */ + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +#define CFG_INIT_SP_OFFSET 0x400000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20 * CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_ADDR 0xBFC40000 +#define CFG_ENV_SIZE 0x20000 + +#define CFG_DIRECT_FLASH_TFTP + +#define CONFIG_NR_DRAM_BANKS 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_ICACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Serial Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 18432000 +#define CFG_NS16550_COM1 0xaf000800 + +/*----------------------------------------------------------------------- + * PCI stuff + */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_NET_MULTI +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +#define CONFIG_RTL8139 + +#endif /* __CONFIG_H */ diff --git a/include/configs/trab.h b/include/configs/trab.h new file mode 100644 index 0000000..85ee756 --- /dev/null +++ b/include/configs/trab.h @@ -0,0 +1,430 @@ +/* + * (C) Copyright 2002-2005 + * Gary Jennejohn + * + * Configuation settings for the TRAB board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Default configuration is with 8 MB Flash, 32 MB RAM + */ +#if (!defined(CONFIG_FLASH_8MB)) && (!defined(CONFIG_FLASH_16MB)) +# define CONFIG_FLASH_8MB /* 8 MB Flash */ +#endif +#if (!defined(CONFIG_RAM_16MB)) && (!defined(CONFIG_RAM_32MB)) +# define CONFIG_RAM_32MB /* 32 MB SDRAM */ +#endif + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ +#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ +#define CONFIG_TRAB 1 /* on a TRAB Board */ +#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +/* automatic software updates (see board/trab/auto_update.c) */ +#define CONFIG_AUTO_UPDATE 1 + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 12000000 /* TRAB has 12 MHz input clock */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CFG_DEVICE_NULLDEV 1 /* enble null device */ +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ + +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*********************************************************** + * I2C stuff: + * the TRAB is equipped with an ATMEL 24C04 EEPROM at + * address 0x54 with 8bit addressing + ***********************************************************/ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ + +#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM address */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 1 address byte */ + +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 bytes page write mode on 24C04 */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* USB stuff */ +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ + +#define CONFIG_VFD 1 /* VFD linear frame buffer driver */ +#define VFD_TEST_LOGO 1 /* output a test logo to the VFDs */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */ + +#define CONFIG_HWFLOW /* include RTS/CTS flow control support */ + +#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */ + +#define CONFIG_MODEM_KEY_MAGIC "23" /* hold down these keys to enable modem */ + +/* + * The following enables modem debugging stuff. The dbg() and + * 'char screen[1024]' are used for debug printfs. Unfortunately, + * it is usable only from BDI + */ +#undef CONFIG_MODEM_SUPPORT_DEBUG + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ + +/* Use s3c2400's RTC */ +#define CONFIG_RTC_S3C24X0 1 + +#ifdef CONFIG_HWFLOW +#define CONFIG_COMMANDS_ADD_HWFLOW CFG_CMD_HWFLOW +#else +#define CONFIG_COMMANDS_ADD_HWFLOW 0 +#endif + +#ifdef CONFIG_VFD +#define CONFIG_COMMANDS_ADD_VFD CFG_CMD_VFD +#else +#define CONFIG_COMMANDS_ADD_VFD 0 +#endif + +#ifdef CONFIG_DRIVER_S3C24X0_I2C +#define CONFIG_COMMANDS_ADD_EEPROM CFG_CMD_EEPROM +#define CONFIG_COMMANDS_I2C CFG_CMD_I2C +#else +#define CONFIG_COMMANDS_ADD_EEPROM 0 +#define CONFIG_COMMANDS_I2C 0 +#endif + +#ifndef USE_920T_MMU +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \ + CONFIG_COMMANDS_ADD_HWFLOW | \ + CONFIG_COMMANDS_ADD_VFD | \ + CONFIG_COMMANDS_ADD_EEPROM | \ + CONFIG_COMMANDS_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + CFG_CMD_USB ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CONFIG_COMMANDS_ADD_HWFLOW | \ + CONFIG_COMMANDS_ADD_VFD | \ + CONFIG_COMMANDS_ADD_EEPROM | \ + CONFIG_COMMANDS_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + CFG_CMD_USB ) +#endif + +/* moved up */ +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ +#define CONFIG_PREBOOT "echo;echo *** booting ***;echo" +#define CONFIG_BOOTARGS "console=ttyS0" +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.3.68 +#define CONFIG_HOSTNAME trab +#define CONFIG_SERVERIP 192.168.3.1 +#define CONFIG_BOOTCOMMAND "burn_in" + +#ifndef CONFIG_FLASH_8MB /* current config: 16 MB flash */ +#ifdef CFG_HUSH_PARSER +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfs_args=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath\0" \ + "rootpath=/opt/eldk/arm_920TDI\0" \ + "ram_args=setenv bootargs root=/dev/ram rw\0" \ + "add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ + "add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \ + "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ + "load=tftp C100000 ${u-boot}\0" \ + "update=protect off 0 5FFFF;era 0 5FFFF;" \ + "cp.b C100000 0 $filesize\0" \ + "loadfile=/tftpboot/TRAB/uImage\0" \ + "loadaddr=c400000\0" \ + "net_load=tftpboot $loadaddr $loadfile\0" \ + "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ + "kernel_addr=00060000\0" \ + "flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \ + "mdm_init1=ATZ\0" \ + "mdm_init2=ATS0=1\0" \ + "mdm_flow_control=rts/cts\0" +#else /* !CFG_HUSH_PARSER */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfs_args=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "rootpath=/opt/eldk/arm_920TDI\0" \ + "ram_args=setenv bootargs root=/dev/ram rw\0" \ + "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ + "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \ + "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ + "load=tftp C100000 ${u-boot}\0" \ + "update=protect off 0 5FFFF;era 0 5FFFF;" \ + "cp.b C100000 0 ${filesize}\0" \ + "loadfile=/tftpboot/TRAB/uImage\0" \ + "loadaddr=c400000\0" \ + "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ + "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ + "kernel_addr=000C0000\0" \ + "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \ + "mdm_init1=ATZ\0" \ + "mdm_init2=ATS0=1\0" \ + "mdm_flow_control=rts/cts\0" +#endif /* CFG_HUSH_PARSER */ +#else /* CONFIG_FLASH_8MB => 8 MB flash */ +#ifdef CFG_HUSH_PARSER +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfs_args=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath\0" \ + "rootpath=/opt/eldk/arm_920TDI\0" \ + "ram_args=setenv bootargs root=/dev/ram rw\0" \ + "add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ + "add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \ + "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ + "load=tftp C100000 ${u-boot}\0" \ + "update=protect off 0 3FFFF;era 0 3FFFF;" \ + "cp.b C100000 0 $filesize;" \ + "setenv filesize;saveenv\0" \ + "loadfile=/tftpboot/TRAB/uImage\0" \ + "loadaddr=C400000\0" \ + "net_load=tftpboot $loadaddr $loadfile\0" \ + "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ + "kernel_addr=000C0000\0" \ + "flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \ + "mdm_init1=ATZ\0" \ + "mdm_init2=ATS0=1\0" \ + "mdm_flow_control=rts/cts\0" +#else /* !CFG_HUSH_PARSER */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nfs_args=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "rootpath=/opt/eldk/arm_920TDI\0" \ + "ram_args=setenv bootargs root=/dev/ram rw\0" \ + "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ + "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \ + "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ + "load=tftp C100000 ${u-boot}\0" \ + "update=protect off 0 3FFFF;era 0 3FFFF;" \ + "cp.b C100000 0 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "loadfile=/tftpboot/TRAB/uImage\0" \ + "loadaddr=C400000\0" \ + "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ + "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ + "kernel_addr=000C0000\0" \ + "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \ + "mdm_init1=ATZ\0" \ + "mdm_init2=ATS0=1\0" \ + "mdm_flow_control=rts/cts\0" +#endif /* CFG_HUSH_PARSER */ +#endif /* CONFIG_FLASH_8MB */ + +#if 1 /* feel free to disable for development */ +#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */ +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "TRAB # " /* Monitor Command Prompt */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0C000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0D000000 /* 16 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x0CF00000 /* default load address */ + +#ifdef CONFIG_TRAB_50MHZ +/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ +/* it to wrap 100 times (total 1562500) to get 1 sec. */ +/* this should _really_ be calculated !! */ +#define CFG_HZ 1562500 +#else +/* the PWM TImer 4 uses a counter of 10390 for 10 ms, so we need */ +/* it to wrap 100 times (total 1039000) to get 1 sec. */ +/* this should _really_ be calculated !! */ +#define CFG_HZ 1039000 +#endif + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ + +/*----------------------------------------------------------------------- + * burn-in test stuff. + * + * BURN_IN_CYCLE_DELAY defines the seconds to wait between each burn-in cycle + * Because the burn-in test itself causes also an delay of about 4 seconds, + * this time must be subtracted from the desired overall burn-in cycle time. + */ +#define BURN_IN_CYCLE_DELAY 296 /* seconds between burn-in cycles */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x0C000000 /* SDRAM Bank #1 */ +#ifndef CONFIG_RAM_16MB +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ +#else +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +#endif + +#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN (256 << 10) + +/* Dynamic MTD partition support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=0" + +/* production flash layout */ +#define MTDPARTS_DEFAULT "mtdparts=0:32k(Firmware1)ro," \ + "16k(Env1)," \ + "16k(Env2)," \ + "320k(Firmware2)ro," \ + "896k(Kernel)," \ + "5376k(Root-FS)," \ + "1408k(JFFS2)," \ + "-(VFD)" + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#ifndef CONFIG_FLASH_8MB +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#else +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#endif + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 + +/* Address and size of Primary Environment Sector */ +#ifndef CONFIG_FLASH_8MB +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_SECT_SIZE 0x20000 +#else +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_SECT_SIZE 0x4000 +#endif + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* Initial value of the on-board touch screen brightness */ +#define CFG_BRIGHTNESS 0x20 + +#endif /* __CONFIG_H */ diff --git a/include/configs/uc100.h b/include/configs/uc100.h new file mode 100644 index 0000000..c4e629a --- /dev/null +++ b/include/configs/uc100.h @@ -0,0 +1,507 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 +#define CONFIG_MPC860T 1 +#define CONFIG_MPC862 1 /* enable 862 since the */ +#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */ + +#define CONFIG_UC100 1 /* ...on a UC100 module */ + +#define MPC8XX_FACT 4 /* Multiply by 4 */ +#define MPC8XX_XIN 25000000 /* 25.0 MHz in */ +#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) + /* define if cant' use get_gclk_freq */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/uc100/uImage\0" \ + "kernel_addr=40000000\0" \ + "ramdisk_addr=40100000\0" \ + "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \ + "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \ + "cp.b 100000 40700000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_STATUS_LED /* no status-led */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#undef CONFIG_RTC_MPC8xx +#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ +#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ + +/* + * Power On Self Test support + */ +#define CONFIG_POST ( CFG_POST_CACHE | \ + CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_SPR ) +#undef CONFIG_POST + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_SNTP ) + +#define CONFIG_NETCONSOLE + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_FLASH_BASE+0x00700000) /* resetvec fff00100*/ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/*----------------------------------------------------------------------- + * Address accessed to reset the board - must not be mapped/assigned + */ +#define CFG_RESET_ADDRESS 0x90000000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN) +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + */ +#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK 0x00000000 +#define CFG_SCCR (SCCR_EBDF11) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (0x00000d24) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */ +#define CFG_OR1_PRELIM 0xfc000a00 +#define CFG_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */ +#define CFG_OR2_PRELIM 0xfff00d24 +#define CFG_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */ +#define CFG_OR3_PRELIM 0xffff8f44 +#define CFG_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */ +#define CFG_OR4_PRELIM 0xffff0300 +#define CFG_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */ +#define CFG_OR5_PRELIM 0xffff8db0 + +/* + * Memory Periodic Timer Prescaler + * + * The Divider for PTA (refresh timer) configuration is based on an + * example SDRAM configuration (64 MBit, one bank). The adjustment to + * the number of chip selects (NCS) and the actually needed refresh + * rate is done by setting MPTPR. + * + * PTA is calculated from + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) + * + * gclk CPU clock (not bus clock!) + * Trefresh Refresh cycle * 4 (four word bursts used) + * + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + * -------------------------------------------- + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 + * + * 50 MHz => 50.000.000 / Divider = 98 + * 66 Mhz => 66.000.000 / Divider = 129 + * 80 Mhz => 80.000.000 / Divider = 156 + * 100 Mhz => 100.000.000 / Divider = 195 + */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +#define CFG_MAMR_VAL 0x30904114 /* for SDRAM */ +#define CFG_MBMR_VAL 0xff001111 /* for Interbus-MPM */ + +/*----------------------------------------------------------------------- + * I2C stuff + */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (24C164) + */ +#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ +#define FEC_ENET +#define CONFIG_MII +#define CFG_DISCOVER_PHY 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h new file mode 100644 index 0000000..d312b65 --- /dev/null +++ b/include/configs/utx8245.h @@ -0,0 +1,420 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Gregory E. Allen, gallen@arlut.utexas.edu + * Matthew E. Karger, karger@arlut.utexas.edu + * Applied Research Laboratories, The University of Texas at Austin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the utx8245 board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_UTX8245 1 +#define DEBUG 1 + +#define CONFIG_IDENT_STRING " [UTX5] " + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 2 +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" +#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */ +#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */ +#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */ +#define CONFIG_SERVERIP 10.8.17.105 /* Spree */ +#define CFG_TFTP_LOADADDR 10000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=FFA00000\0" \ + "ramdisk_addr=FF800000\0" \ + "u-boot_startaddr=FFB00000\0" \ + "u-boot_endaddr=FFB2FFFF\0" \ + "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \ +nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \ + "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \ + "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \ + "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \ + "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \ + "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \ +${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \ +${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\ +protect on ${u-boot_startaddr} ${u-boot_endaddr}" + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \ + | CFG_CMD_FLASH | CFG_CMD_MEMORY \ + | CFG_CMD_ENV | CFG_CMD_CONSOLE \ + | CFG_CMD_LOADS | CFG_CMD_LOADB \ + | CFG_CMD_IMI | CFG_CMD_CACHE \ + | CFG_CMD_RUN | CFG_CMD_ECHO \ + | CFG_CMD_REGINFO | CFG_CMD_NET\ + | CFG_CMD_DHCP | CFG_CMD_I2C \ + | CFG_CMD_DATE) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + + +/*----------------------------------------------------------------------- + * PCI configuration + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_NET_MULTI +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_EEPRO100_SROM_WRITE + +#define PCI_ENET0_IOADDR 0xF0000000 +#define PCI_ENET0_MEMADDR 0xF0000000 + +#define PCI_FIREWIRE_IOADDR 0xF1000000 +#define PCI_FIREWIRE_MEMADDR 0xF1000000 +/* +#define PCI_ENET0_IOADDR 0xFE000000 +#define PCI_ENET0_MEMADDR 0x80000000 + +#define PCI_FIREWIRE_IOADDR 0x81000000 +#define PCI_FIREWIRE_MEMADDR 0x81000000 +*/ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x10000000 /* 256MB */ +/*#define CFG_VERY_BIG_RAM 1 */ + +/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector + * is actually located at FFF00100. Therefore, U-Boot is + * physically located at 0xFFB0_0000, but is also mirrored at + * 0xFFF0_0000. + */ +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFC000000 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/*#define CFG_DRAM_TEST 1 */ +#define CFG_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */ +#define CFG_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */ + /* vectors and U-Boot */ + + +/*-------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + *------------------------------------------------------------------*/ +#define CFG_INIT_DATA_SIZE 128 /* Size in bytes reserved for */ + /* initial data */ +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/*-------------------------------------------------------------------- + * NS16550 Configuration + *------------------------------------------------------------------*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2) +# define CFG_NS16550_CLK get_bus_freq(0) +#else +# define CFG_NS16550_CLK 33000000 +#endif + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) +#define CFG_NS16550_COM3 0xFF000000 +#define CFG_NS16550_COM4 0xFF000008 + +/*-------------------------------------------------------------------- + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + *------------------------------------------------------------------*/ + +#define CONFIG_SYS_CLK_FREQ 33000000 +#define CFG_HZ 1000 + +/*#define CFG_ETH_DEV_FN 0x7800 */ +/*#define CFG_ETH_IOBASE 0x00104000 */ + +/*-------------------------------------------------------------------- + * I2C Configuration + *------------------------------------------------------------------*/ +#if 1 +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#endif + +#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */ + /* Philips PCF8563 RTC */ +#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ + +/*-------------------------------------------------------------------- + * Memory Control Configuration Register values + * - see sec. 4.12 of MPC8245 UM + *------------------------------------------------------------------*/ + +/**** MCCR1 ****/ +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2, + mem_freq = 100MHz */ + +#define CFG_BANK7_ROW 0 /* SDRAM bank 7-0 row address */ +#define CFG_BANK6_ROW 0 /* bit count */ +#define CFG_BANK5_ROW 0 +#define CFG_BANK4_ROW 0 +#define CFG_BANK3_ROW 0 +#define CFG_BANK2_ROW 0 +#define CFG_BANK1_ROW 2 +#define CFG_BANK0_ROW 2 + +/**** MCCR2, refresh interval clock cycles ****/ +#define CFG_REFINT 480 /* 33 MHz SDRAM clock was 480 */ + +/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ +#define CFG_BSTOPRE 1023 /* burst to precharge[0..9], */ + /* sets open page interval */ + +/**** MCCR3 ****/ +#define CFG_REFREC 7 /* Refresh to activate interval, trc */ + +/**** MCCR4 ****/ +#define CFG_PRETOACT 2 /* trp */ +#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */ +#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */ +#define CFG_ACTORW 2 /* trcd min */ +#define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 0 /* we don't need extended ROM space */ +#define CFG_REGDIMM 0 + +/* calculate according to formula in sec. 6-22 of 8245 UM */ +#define CFG_PGMAX 50 /* how long the 8245 retains the */ + /* currently accessed page in memory */ + /* was 45 */ + +#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */ + /* bits 7,6, and 3-0 MUST be 0 */ + +#if 0 +#define CFG_DLL_MAX_DELAY 0x04 +#else +#define CFG_DLL_MAX_DELAY 0 +#endif +#if 0 /* need for 33MHz SDRAM */ +#define CFG_DLL_EXTEND 0x80 +#else +#define CFG_DLL_EXTEND 0 +#endif +#define CFG_PCI_HOLD_DEL 0x20 + + +/* Memory bank settings. + * Only bits 20-29 are actually used from these values to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8245 user manual. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE/2 - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START CFG_MAX_RAM_SIZE/2 +#define CFG_BANK1_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK1_ENABLE 1 +#define CFG_BANK2_START 0x3ff00000 /* not available in this design */ +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +/*--------------------------------------------------------------------*/ +/* 4.4 - Output Driver Control Register */ +/*--------------------------------------------------------------------*/ +#define CFG_ODCR 0xe5 + +/*--------------------------------------------------------------------*/ +/* 4.8 - Error Handling Registers */ +/*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/ +#define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */ + +/* SDRAM 0-256 MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +/*#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */ +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in dcache */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + + +#define CFG_IBAT2L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT2U (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI memory */ +/*#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */ +/*#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */ + +/*Flash, config addrs, etc. */ +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0xFF800000 +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ + +/* NOTE: environment is not EMBEDDED in the u-boot code. + It's stored in flash in its own separate sector. */ +#define CFG_ENV_IS_IN_FLASH 1 + +#if 1 /* AMD AM29LV033C */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ +#define CFG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */ +#define CFG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */ +#else /* AMD AM29LV116D */ +#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */ +#define CFG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */ +#define CFG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */ +#endif /* #if */ + +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Size of the Environment */ +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/v37.h b/include/configs/v37.h new file mode 100644 index 0000000..a2e99b5 --- /dev/null +++ b/include/configs/v37.h @@ -0,0 +1,391 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ +#define CONFIG_V37 1 /* ...on a Marel V37 board */ + +#define CONFIG_LCD +#define CONFIG_SHARP_LQ084V1DG21 +#undef CONFIG_LCD_LOGO + +/*----------------------------------------------------------------------------- + * I2C Configuration + *----------------------------------------------------------------------------- + */ +#define CONFIG_I2C 1 +#define CFG_I2C_SLAVE 0x2 + +#define CONFIG_8xx_CONS_SMC1 1 +#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ +#undef CONFIG_8xx_CONS_NONE +#define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */ +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ +#endif + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_BOOTCOMMAND \ + "tftpboot; " \ + "setenv bootargs console=tty0 " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE ) + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor1" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor1=v37-1" +#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)" +*/ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE0 0x40000000 +#define CFG_FLASH_BASE1 0x60000000 +#define CFG_FLASH_BASE CFG_FLASH_BASE1 + +#if defined(DEBUG) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#endif +#define CFG_MONITOR_BASE CFG_FLASH_BASE0 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_NVRAM 1 +#define CFG_ENV_ADDR 0x80000000/* Address of Environment */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +#define CFG_ENV_OFFSET 0 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR 0xFFFFFF88 +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + */ +/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) +/* +#define CFG_PISCR (PISCR_PS | PISCR_PITF) +*/ + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit + * + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! + */ +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS ) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* up to 50 MHz we use a 1:1 clock */ +#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ + +#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ + +#define CFG_OR_TIMING_FLASH 0xF56 + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V) + +#define CFG_OR5_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V) + +/* + * BR1 and OR1 (Battery backed SRAM) + */ +#define CFG_BR1_PRELIM 0x80000401 +#define CFG_OR1_PRELIM 0xFFC00736 + +/* + * BR2 and OR2 (SDRAM) + */ +#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */ + +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* Marel V37 mem setting */ + +#define CFG_BR3_CAN 0xC0000401 +#define CFG_OR3_CAN 0xFFFF0724 + +/* +#define CFG_BR3_PRELIM 0xFA400001 +#define CFG_OR3_PRELIM 0xFFFF8910 +#define CFG_BR4_PRELIM 0xFA000401 +#define CFG_OR4_PRELIM 0xFFFE0970 +*/ + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* + * Refresh clock Prescalar + */ +#define CFG_MPTPR MPTPR_PTP_DIV16 + +/* + * MAMR settings for SDRAM + */ + +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ + MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/versatile.h b/include/configs/versatile.h new file mode 100644 index 0000000..16db43b --- /dev/null +++ b/include/configs/versatile.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP Innovator board. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * Configuration for Versatile PB. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ +#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */ +#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ + + +#define CFG_MEMTEST_START 0x100000 +#define CFG_MEMTEST_END 0x10000000 +#define CFG_HZ (1000000 / 256) +#define CFG_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ + +#define CFG_TIMER_INTERVAL 10000 +#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL >> 4) /* Divide by 16 */ +#define CFG_TIMER_CTRL 0x84 /* Enable, Clock / 16 */ + +/* + * control registers + */ +#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ + +/* + * System controller bit assignment + */ +#define VERSATILE_REFCLK 0 +#define VERSATILE_TIMCLK 1 + +#define VERSATILE_TIMER1_EnSel 15 +#define VERSATILE_TIMER2_EnSel 17 +#define VERSATILE_TIMER3_EnSel 19 +#define VERSATILE_TIMER4_EnSel 21 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC_USE_32_BIT +#define CONFIG_SMC91111_BASE 0x10010000 +#undef CONFIG_SMC91111_EXT_PHY + +/* + * NS16550 Configuration + */ +#define CFG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } +#define CONFIG_CONS_INDEX 0 + +#define CONFIG_BAUDRATE 38400 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SERIAL0 0x101F1000 +#define CFG_SERIAL1 0x101F2000 + +#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV) + +/*#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */ + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0" +/*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */ + +/* + * Static configuration when assigning fixed address + */ +/*#define CONFIG_NETMASK 255.255.255.0 /--* talk on MY local net */ +/*#define CONFIG_IPADDR xx.xx.xx.xx /--* static IP I currently own */ +/*#define CONFIG_SERVERIP xx.xx.xx.xx /--* current IP of my dev pc */ +#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Versatile # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ + +#define CFG_FLASH_BASE 0x34000000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define VERSATILE_SYS_BASE 0x10000000 +#define VERSATILE_SYS_FLASH_OFFSET 0x4C +#define VERSATILE_FLASHCTRL (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) +#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */ +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ +#define CFG_MAX_FLASH_SECT (256) + +#define PHYS_FLASH_1 (CFG_FLASH_BASE) + +#define CFG_ENV_IS_IN_FLASH 1 /* env in flash instead of CFG_ENV_IS_NOWHERE */ +#define CFG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x01f00000 /* environment starts here */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) + +#endif /* __CONFIG_H */ diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h new file mode 100644 index 0000000..c5ee78f --- /dev/null +++ b/include/configs/voiceblue.h @@ -0,0 +1,268 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * Configuation settings for the TI OMAP VoiceBlue board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP1510 1 /* which is in a 5910 */ + +/* Input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ +#define CONFIG_XTAL_FREQ 12000000 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R /* There is nothing to really init */ +#define BOARD_LATE_INIT /* but we flash the LEDs here */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE SZ_64M + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x0c000000 + +#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ + +/* + * FLASH organization + */ +#define CFG_FLASH_CFI /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER /* Use the common driver */ +#define CFG_MAX_FLASH_BANKS 1 +#ifdef VOICEBLUE_SMALL_FLASH +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_2 } +#else +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } +#endif + +/* FIXME: Does not work on AMD flash */ +/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */ +#define CFG_MAX_FLASH_SECT 512 /* max # of sectors on one chip */ + +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN SZ_128K + +/* + * Environment settings + */ +#ifdef VOICEBLUE_SMALL_FLASH +#define CFG_ENV_IS_NOWHERE +#define CFG_ENV_SIZE SZ_1K +#else +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) +#define CFG_ENV_SIZE SZ_8K +#define CFG_ENV_SECT_SIZE SZ_64K +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +#define CONFIG_ENV_OVERWRITE + +#define CFG_JFFS_CUSTOM_PART /* see board/voiceblue/jffs2parts.c */ +#endif + +/* + * Size of malloc() pool and stack + */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#ifdef VOICEBLUE_SMALL_FLASH +#define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKSIZE SZ_8K +#else +#define CFG_MALLOC_LEN SZ_4M +#define CONFIG_STACKSIZE SZ_1M +#endif + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE 0x08000300 + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#ifdef VOICEBLUE_SMALL_FLASH +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_LOADB | \ + CFG_CMD_IMI | \ + CFG_CMD_FLASH | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_BOOTD | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_RUN) +#else +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_LOADB | \ + CFG_CMD_IMI | \ + CFG_CMD_FLASH | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_ENV | \ + CFG_CMD_BOOTD | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_JFFS2) +#endif + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#define CONFIG_LOOPW + +#ifdef VOICEBLUE_SMALL_FLASH +#define CONFIG_BOOTDELAY 0 +#undef CONFIG_BOOTARGS /* the preboot command will set bootargs*/ +#define CFG_AUTOLOAD "n" /* no autoload */ +#define CONFIG_PREBOOT "run setup" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "setup=setenv bootargs console=ttyS0,${baudrate} " \ + "root=/dev/nfs ip=dhcp\0" \ + "update=erase c000000 c03ffff; " \ + "cp.b 10400000 c000000 ${filesize}\0" +#else +#define CONFIG_BOOTDELAY 3 +#undef CONFIG_BOOTARGS /* boot command will set bootargs */ +#define CFG_AUTOLOAD "n" /* no autoload */ +#define CONFIG_BOOTCOMMAND "run nboot" +#define CONFIG_PREBOOT "run setup" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ospart=0\0" \ + "swapos=no\0" \ + "setpart=" \ + "if test $swapos = yes; then " \ + "if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\ + "setenv swapos no; saveenv; " \ + "else " \ + "if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\ + "fi\0" \ + "setup=setenv bootargs console=ttyS0,$baudrate " \ + "mtdparts=$mtdparts\0" \ + "nfsargs=run setpart; setenv bootargs $bootargs " \ + "root=/dev/nfs ip=dhcp\0" \ + "flashargs=run setpart; setenv bootargs $bootargs " \ + "root=/dev/mtdblock$partition ro " \ + "rootfstype=jffs2\0" \ + "nboot=run nfsargs; bootp; tftp; bootm\0" \ + "fboot=run flashargs; fsload /boot/uImage; bootm\0" +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#ifndef VOICEBLUE_SMALL_FLASH +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#endif +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "# " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START PHYS_SDRAM_1 +#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. + * This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE OMAP1510_TIMER1_BASE +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +#define OMAP5910_DPLL_DIV 1 +#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ + (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) + +#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ +#define OMAP5910_LCD_DIV 2 /* CKL/4 */ +#define OMAP5910_ARM_DIV 0 /* CKL/1 */ +#define OMAP5910_DSP_DIV 0 /* CKL/1 */ +#define OMAP5910_TC_DIV 1 /* CKL/2 */ +#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ +#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ + +#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ +#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ + (OMAP5910_LCD_DIV << 2) | \ + (OMAP5910_ARM_DIV << 4) | \ + (OMAP5910_DSP_DIV << 6) | \ + (OMAP5910_TC_DIV << 8) | \ + (OMAP5910_DSP_MMU_DIV << 10) | \ + (OMAP5910_ARM_TIM_SEL << 12)) + +#define VOICEBLUE_LED_REG 0x04030000 + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00040000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=voiceblue-0" +#define MTDPARTS_DEFAULT "mtdparts=voiceblue-0:128k(uboot),64k(env),64k(renv),-(jffs2)" +*/ + +#endif /* __CONFIG_H */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h new file mode 100644 index 0000000..1171ee5 --- /dev/null +++ b/include/configs/walnut.h @@ -0,0 +1,337 @@ +/* + * (C) Copyright 2000-2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_405GP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ + /* ...and on a SYCAMORE board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=walnut\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/walnut/uImage\0" \ + "kernel_addr=fff80000\0" \ + "ramdisk_addr=fff80000\0" \ + "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ + +#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + +/*----------------------------------------------------------------------- + * I2C stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * Define here the location of the environment variables (FLASH or NVRAM). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x9B015480 +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB1AP 0x02815480 +#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB2AP 0x04815A80 +#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB3AP 0x01815280 +#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB7AP 0x01815280 +#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * External peripheral base address + *----------------------------------------------------------------------- + */ +#define CFG_KEY_REG_BASE_ADDR 0xF0100000 +#define CFG_IR_REG_BASE_ADDR 0xF0200000 +#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ + +#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h new file mode 100644 index 0000000..47251bb --- /dev/null +++ b/include/configs/wepep250.h @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_PXA250 1 /* this is an PXA250 CPU */ +#define CONFIG_WEPEP250 1 /* config for wepep250 board */ +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ + + +/* + * Select serial console configuration + */ +#define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */ +#define CONFIG_BAUDRATE 115200 + + +/* + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + & ~CFG_CMD_NET \ + & ~CFG_CMD_LOADS \ + & ~CFG_CMD_CONSOLE \ + & ~CFG_CMD_AUTOSCRIPT \ +/* | CFG_CMD_JFFS2 */ \ + ) +#include + +/* + * Boot options. Setting delay to -1 stops autostart count down. + * NOTE: Sending parameters to kernel depends on kernel version and + * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept + * parameters at all! Do not get confused by them so. + */ +#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8" +#define CONFIG_BOOTCOMMAND "bootm 40000" + + +/* + * General options for u-boot. Modify to save memory foot print + */ +#define CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "WEP> " /* prompt string */ +#define CFG_CBSIZE 256 /* console I/O buffer */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ +#define CFG_MAXARGS 16 /* max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ + +#define CFG_MEMTEST_START 0xa0400000 /* memtest test area */ +#define CFG_MEMTEST_END 0xa0800000 + +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* core clock - register value */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#undef CONFIG_INITRD_TAG /* do not send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + + +/* + * Malloc pool need to host env + 128 Kb reserve for other allocations. + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_STACKSIZE (120<<10) /* stack size */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ +#endif + +/* + * SDRAM Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define WEP_SDRAM_1 0xa0000000 /* SDRAM bank #1 */ +#define WEP_SDRAM_1_SIZE 0x02000000 /* 32 MB ( 2 chip ) */ +#define WEP_SDRAM_2 0xa2000000 /* SDRAM bank #2 */ +#define WEP_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define WEP_SDRAM_3 0xa8000000 /* SDRAM bank #3 */ +#define WEP_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define WEP_SDRAM_4 0xac000000 /* SDRAM bank #4 */ +#define WEP_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x02000000 + +/* Uncomment used SDRAM chip */ +#define WEP_SDRAM_K4S281633 +/*#define WEP_SDRAM_K4S561633*/ + + +/* + * Configuration for FLASH memory + */ +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ +#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ +#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ +#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/ +#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */ +#define WEP_FLASH_BASE 0x0000000 /* location of flash memory */ +#define WEP_FLASH_UNLOCK 1 /* perform hw unlock first */ + + +/* This should be defined if CFI FLASH device is present. Actually benefit + is not so clear to me. In other words we can provide more informations + to user, but this expects more complex flash handling we do not provide + now.*/ +#undef CFG_FLASH_CFI + +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ + +#define CFG_FLASH_BASE WEP_FLASH_BASE + +/* + * This is setting for JFFS2 support in u-boot. + * Right now there is no gain for user, but later on booting kernel might be + * possible. Consider using XIP kernel running from flash to save RAM + * footprint. + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 5 +#define CFG_JFFS2_NUM_BANKS 1 + +/* + * Environment setup. Definitions of monitor location and size with + * definition of environment setup ends up in 2 possibilities. + * 1. Embeded environment - in u-boot code is space for environment + * 2. Environment is read from predefined sector of flash + * Right now we support 2. possiblity, but expecting no env placed + * on mentioned address right now. This also needs to provide whole + * sector for it - for us 256Kb is really waste of memory. U-boot uses + * default env. and until kernel parameters could be sent to kernel + * env. has no sense to us. + */ + +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20000 /* absolute address for now */ +#define CFG_ENV_SIZE 0x2000 + +#undef CONFIG_ENV_OVERWRITE /* env is not writable now */ + +/* + * Well this has to be defined, but on the other hand it is used differently + * one may expect. For instance loadb command do not cares :-) + * So advice is - do not relay on this... + */ +#define CFG_LOAD_ADDR 0x40000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h new file mode 100644 index 0000000..1039762 --- /dev/null +++ b/include/configs/xaeniax.h @@ -0,0 +1,557 @@ +/* + * (C) Copyright 2004-2005 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2004 + * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the xaeniax board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA255 CPU */ +#define CONFIG_XAENIAX 1 /* on a xaeniax board */ + + +#define BOARD_LATE_INIT 1 + + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * select serial console configuration + */ +#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ + + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_DTT) | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_NFS | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.68.201 +#define CONFIG_SERVERIP 192.168.68.62 + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "bootm 0x00100000" +#define CONFIG_BOOTARGS "console=ttyS1,115200" +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Size of malloc() pool; this lives below the uppermost 128 KiB which are + * used for the RAM copy of the uboot code + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_HUSH_PARSER 1 + +#define CFG_PROMPT_HUSH_PS2 "> " + +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "u-boot$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "u-boot=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* FIXME */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * SMSC91C111 Network Card + */ +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ +#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ +#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ +#undef CONFIG_SHOW_ACTIVITY +#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ + +/* + * GPIO settings + */ + +/* + * GP05 == nUSBReset is 1 + * GP10 == CFReset is 1 + * GP13 == nCFDataEnable is 1 + * GP14 == nCFAddrEnable is 1 + * GP15 == nCS1 is 1 + * GP21 == ComBrdReset is 1 + * GP24 == SFRM is 1 + * GP25 == TXD is 1 + * GP31 == SYNC is 1 + * GP33 == nCS5 is 1 + * GP39 == FFTXD is 1 + * GP41 == RTS is 1 + * GP43 == BTTXD is 1 + * GP45 == BTRTS is 1 + * GP47 == TXD is 1 + * GP48 == nPOE is 1 + * GP49 == nPWE is 1 + * GP50 == nPIOR is 1 + * GP51 == nPIOW is 1 + * GP52 == nPCE[1] is 1 + * GP53 == nPCE[2] is 1 + * GP54 == nPSKTSEL is 1 + * GP55 == nPREG is 1 + * GP78 == nCS2 is 1 + * GP79 == nCS3 is 1 + * GP80 == nCS4 is 1 + * GP82 == NSSPSFRM is 1 + * GP83 == NSSPTXD is 1 + */ +#define CFG_GPSR0_VAL 0x8320E420 +#define CFG_GPSR1_VAL 0x00FFAA82 +#define CFG_GPSR2_VAL 0x000DC000 + +/* + * GP03 == LANReset is 0 + * GP06 == USBWakeUp is 0 + * GP11 == USBControl is 0 + * GP12 == Buzzer is 0 + * GP16 == PWM0 is 0 + * GP17 == PWM1 is 0 + * GP23 == SCLK is 0 + * GP30 == SDATA_OUT is 0 + * GP81 == NSSPCLK is 0 + */ +#define CFG_GPCR0_VAL 0x40C31848 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00020000 + +/* + * GP00 == CPUWakeUpUSB is input + * GP01 == GP reset is input + * GP02 == LANInterrupt is input + * GP03 == LANReset is output + * GP04 == USBInterrupt is input + * GP05 == nUSBReset is output + * GP06 == USBWakeUp is output + * GP07 == CFReady/nBusy is input + * GP08 == nCFCardDetect1 is input + * GP09 == nCFCardDetect2 is input + * GP10 == nCFReset is output + * GP11 == USBControl is output + * GP12 == Buzzer is output + * GP13 == CFDataEnable is output + * GP14 == CFAddressEnable is output + * GP15 == nCS1 is output + * GP16 == PWM0 is output + * GP17 == PWM1 is output + * GP18 == RDY is input + * GP19 == ReaderReady is input + * GP20 == ReaderReset is input + * GP21 == ComBrdReset is output + * GP23 == SCLK is output + * GP24 == SFRM is output + * GP25 == TXD is output + * GP26 == RXD is input + * GP27 == EXTCLK is input + * GP28 == BITCLK is output + * GP29 == SDATA_IN0 is input + * GP30 == SDATA_OUT is output + * GP31 == SYNC is output + * GP32 == SYSSCLK is output + * GP33 == nCS5 is output + * GP34 == FFRXD is input + * GP35 == CTS is input + * GP36 == DCD is input + * GP37 == DSR is input + * GP38 == RI is input + * GP39 == FFTXD is output + * GP40 == DTR is output + * GP41 == RTS is output + * GP42 == BTRXD is input + * GP43 == BTTXD is output + * GP44 == BTCTS is input + * GP45 == BTRTS is output + * GP46 == RXD is input + * GP47 == TXD is output + * GP48 == nPOE is output + * GP49 == nPWE is output + * GP50 == nPIOR is output + * GP51 == nPIOW is output + * GP52 == nPCE[1] is output + * GP53 == nPCE[2] is output + * GP54 == nPSKTSEL is output + * GP55 == nPREG is output + * GP56 == nPWAIT is input + * GP57 == nPIOS16 is input + * GP58 == LDD[0] is output + * GP59 == LDD[1] is output + * GP60 == LDD[2] is output + * GP61 == LDD[3] is output + * GP62 == LDD[4] is output + * GP63 == LDD[5] is output + * GP64 == LDD[6] is output + * GP65 == LDD[7] is output + * GP66 == LDD[8] is output + * GP67 == LDD[9] is output + * GP68 == LDD[10] is output + * GP69 == LDD[11] is output + * GP70 == LDD[12] is output + * GP71 == LDD[13] is output + * GP72 == LDD[14] is output + * GP73 == LDD[15] is output + * GP74 == LCD_FCLK is output + * GP75 == LCD_LCLK is output + * GP76 == LCD_PCLK is output + * GP77 == LCD_ACBIAS is output + * GP78 == nCS2 is output + * GP79 == nCS3 is output + * GP80 == nCS4 is output + * GP81 == NSSPCLK is output + * GP82 == NSSPSFRM is output + * GP83 == NSSPTXD is output + * GP84 == NSSPRXD is input + */ +#define CFG_GPDR0_VAL 0xD3E3FC68 +#define CFG_GPDR1_VAL 0xFCFFAB83 +#define CFG_GPDR2_VAL 0x000FFFFF + +/* + * GP01 == GP reset is AF01 + * GP15 == nCS1 is AF10 + * GP16 == PWM0 is AF10 + * GP17 == PWM1 is AF10 + * GP18 == RDY is AF01 + * GP23 == SCLK is AF10 + * GP24 == SFRM is AF10 + * GP25 == TXD is AF10 + * GP26 == RXD is AF01 + * GP27 == EXTCLK is AF01 + * GP28 == BITCLK is AF01 + * GP29 == SDATA_IN0 is AF10 + * GP30 == SDATA_OUT is AF01 + * GP31 == SYNC is AF01 + * GP32 == SYSCLK is AF01 + * GP33 == nCS5 is AF10 + * GP34 == FFRXD is AF01 + * GP35 == CTS is AF01 + * GP36 == DCD is AF01 + * GP37 == DSR is AF01 + * GP38 == RI is AF01 + * GP39 == FFTXD is AF10 + * GP40 == DTR is AF10 + * GP41 == RTS is AF10 + * GP42 == BTRXD is AF01 + * GP43 == BTTXD is AF10 + * GP44 == BTCTS is AF01 + * GP45 == BTRTS is AF10 + * GP46 == RXD is AF10 + * GP47 == TXD is AF01 + * GP48 == nPOE is AF10 + * GP49 == nPWE is AF10 + * GP50 == nPIOR is AF10 + * GP51 == nPIOW is AF10 + * GP52 == nPCE[1] is AF10 + * GP53 == nPCE[2] is AF10 + * GP54 == nPSKTSEL is AF10 + * GP55 == nPREG is AF10 + * GP56 == nPWAIT is AF01 + * GP57 == nPIOS16 is AF01 + * GP58 == LDD[0] is AF10 + * GP59 == LDD[1] is AF10 + * GP60 == LDD[2] is AF10 + * GP61 == LDD[3] is AF10 + * GP62 == LDD[4] is AF10 + * GP63 == LDD[5] is AF10 + * GP64 == LDD[6] is AF10 + * GP65 == LDD[7] is AF10 + * GP66 == LDD[8] is AF10 + * GP67 == LDD[9] is AF10 + * GP68 == LDD[10] is AF10 + * GP69 == LDD[11] is AF10 + * GP70 == LDD[12] is AF10 + * GP71 == LDD[13] is AF10 + * GP72 == LDD[14] is AF10 + * GP73 == LDD[15] is AF10 + * GP74 == LCD_FCLK is AF10 + * GP75 == LCD_LCLK is AF10 + * GP76 == LCD_PCLK is AF10 + * GP77 == LCD_ACBIAS is AF10 + * GP78 == nCS2 is AF10 + * GP79 == nCS3 is AF10 + * GP80 == nCS4 is AF10 + * GP81 == NSSPCLK is AF01 + * GP82 == NSSPSFRM is AF01 + * GP83 == NSSPTXD is AF01 + * GP84 == NSSPRXD is AF10 + */ +#define CFG_GAFR0_L_VAL 0x80000004 +#define CFG_GAFR0_U_VAL 0x595A801A +#define CFG_GAFR1_L_VAL 0x699A9559 +#define CFG_GAFR1_U_VAL 0xAAA5AAAA +#define CFG_GAFR2_L_VAL 0xAAAAAAAA +#define CFG_GAFR2_U_VAL 0x00000256 + +/* + * clock settings + */ +/* RDH = 1 + * PH = 0 + * VFS = 0 + * BFS = 0 + * SSS = 0 + */ +#define CFG_PSSR_VAL 0x00000030 + +#define CFG_CKEN_VAL 0x00000080 /* */ +#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ + + +/* + * Memory settings + * + * This is the configuration for nCS0/1 -> flash banks + * configuration for nCS1 : + * [31] 0 - + * [30:28] 000 - + * [27:24] 0000 - + * [23:20] 0000 - + * [19] 0 - + * [18:16] 000 - + * configuration for nCS0: + * [15] 0 - Slower Device + * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns + * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns + * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?) + * [03] 0 - 32 Bit bus width + * [02:00] 010 - burst OF 4 ROM or FLASH +*/ +#define CFG_MSC0_VAL 0x000023D2 + +/* This is the configuration for nCS2/3 -> USB controller, LAN + * configuration for nCS3: LAN + * [31] 0 - Slower Device + * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns + * [19] 0 - 32 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS2: USB + * [15] 1 - Faster Device + * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns + * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC1_VAL 0x1224A26C + +/* This is the configuration for nCS4/5 -> LAN + * configuration for nCS5: + * [31] 0 - + * [30:28] 000 - + * [27:24] 0000 - + * [23:20] 0000 - + * [19] 0 - + * [18:16] 000 - + * configuration for nCS4: LAN + * [15] 1 - Faster Device + * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns + * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns + * [03] 0 - 32 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC2_VAL 0x00001224 + +/* MDCNFG: SDRAM Configuration Register + * + * [31:29] 000 - reserved + * [28] 0 - no SA1111 compatiblity mode + * [27] 0 - latch return data with return clock + * [26] 0 - alternate addressing for pair 2/3 + * [25:24] 00 - timings + * [23] 0 - internal banks in lower partition 2/3 (not used) + * [22:21] 00 - row address bits for partition 2/3 (not used) + * [20:19] 00 - column address bits for partition 2/3 (not used) + * [18] 0 - SDRAM partition 2/3 width is 32 bit + * [17] 0 - SDRAM partition 3 disabled + * [16] 0 - SDRAM partition 2 disabled + * [15:13] 000 - reserved + * [12] 0 - no SA1111 compatiblity mode + * [11] 1 - latch return data with return clock + * [10] 0 - no alternate addressing for pair 0/1 + * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk + * [7] 1 - 4 internal banks in lower partition pair + * [06:05] 10 - 13 row address bits for partition 0/1 + * [04:03] 01 - 9 column address bits for partition 0/1 + * [02] 0 - SDRAM partition 0/1 width is 32 bit + * [01] 0 - disable SDRAM partition 1 + * [00] 1 - enable SDRAM partition 0 + */ +/* use the configuration above but disable partition 0 */ +#define CFG_MDCNFG_VAL 0x00000AC9 + +/* MDREFR: SDRAM Refresh Control Register + * + * [32:26] 0 - reserved + * [25] 0 - K2FREE: not free running + * [24] 0 - K1FREE: not free running + * [23] 0 - K0FREE: not free running + * [22] 0 - SLFRSH: self refresh disabled + * [21] 0 - reserved + * [20] 1 - APD: auto power down + * [19] 0 - K2DB2: SDCLK2 is MemClk + * [18] 0 - K2RUN: disable SDCLK2 + * [17] 0 - K1DB2: SDCLK1 is MemClk + * [16] 1 - K1RUN: enable SDCLK1 + * [15] 1 - E1PIN: SDRAM clock enable + * [14] 0 - K0DB2: SDCLK0 is MemClk + * [13] 0 - K0RUN: disable SDCLK0 + * [12] 0 - E0PIN: disable SDCKE0 + * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 + */ +#define CFG_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */ + +/* MDMRS: Mode Register Set Configuration Register + * + * [31] 0 - reserved + * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) + * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used) + * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) + * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) + * [15] 0 - reserved + * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. + * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency. + * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. + * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. + */ +#define CFG_MDMRS_VAL 0x00320032 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + + +#endif /* __CONFIG_H */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h new file mode 100644 index 0000000..952f73b --- /dev/null +++ b/include/configs/xm250.h @@ -0,0 +1,349 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool; this lives below the uppermost 128 KiB which are + * used for the RAM copy of the uboot code + * + */ +#define CFG_MALLOC_LEN (256*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE 0x04000300 +#undef CONFIG_SMC91111_EXT_PHY +#define CONFIG_SMC_USE_32_BIT +#undef CONFIG_SHOW_ACTIVITY +#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ + +/* + * I2C bus + */ +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xfe + +#define CONFIG_RTC_PCF8563 1 +#define CFG_I2C_RTC_ADDR 0x51 + +#define CFG_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* length of address */ +#define CFG_EEPROM_SIZE 2048 /* size in bytes */ +#undef CFG_I2C_INIT_BOARD /* board has no own init */ + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa3000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */ + + /* valid baudrates */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#undef CONFIG_INITRD_TAG /* do not send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ +#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ +#define CFG_FLASH_LOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Set Lock Bit */ +#define CFG_FLASH_UNLOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Clear Lock Bits */ +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ +#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ + +/****************************************************************************** + * + * CPU specific defines + * + ******************************************************************************/ + +/* + * GPIO settings + * + * GPIO pin assignments + * GPIO Name Dir Out AF + * 0 NC + * 1 NC + * 2 SIRQ1 I + * 3 SIRQ2 I + * 4 SIRQ3 I + * 5 DMAACK1 O 0 + * 6 DMAACK2 O 0 + * 7 DMAACK3 O 0 + * 8 TC1 O 0 + * 9 TC2 O 0 + * 10 TC3 O 0 + * 11 nDMAEN O 1 + * 12 AENCTRL O 0 + * 13 PLDTC O 0 + * 14 ETHIRQ I + * 15 NC + * 16 NC + * 17 NC + * 18 RDY I + * 19 DMASIO I + * 20 ETHIRQ NC + * 21 NC + * 22 PGMEN O 1 FIXME for debug only enable flash + * 23 NC + * 24 NC + * 25 NC + * 26 NC + * 27 NC + * 28 NC + * 29 NC + * 30 NC + * 31 NC + * 32 NC + * 33 NC + * 34 FFRXD I 01 + * 35 FFCTS I 01 + * 36 FFDCD I 01 + * 37 FFDSR I 01 + * 38 FFRI I 01 + * 39 FFTXD O 1 10 + * 40 FFDTR O 0 10 + * 41 FFRTS O 0 10 + * 42 RS232FOFF O 0 00 + * 43 NC + * 44 NC + * 45 IRSL0 O 0 + * 46 IRRX0 I 01 + * 47 IRTX0 O 0 10 + * 48 NC + * 49 nIOWE O 0 + * 50 NC + * 51 NC + * 52 NC + * 53 NC + * 54 NC + * 55 NC + * 56 NC + * 57 NC + * 58 DKDIRQ I + * 59 NC + * 60 NC + * 61 NC + * 62 NC + * 63 NC + * 64 COMLED O 0 + * 65 COMLED O 0 + * 66 COMLED O 0 + * 67 COMLED O 0 + * 68 COMLED O 0 + * 69 COMLED O 0 + * 70 COMLED O 0 + * 71 COMLED O 0 + * 72 NC + * 73 NC + * 74 NC + * 75 NC + * 76 NC + * 77 NC + * 78 CSIO O 1 + * 79 NC + * 80 CSETH O 1 + * + * NOTE: All NC's are defined to be outputs + * + */ +/* Pin direction control */ +#define CFG_GPDR0_VAL 0xd3808000 +#define CFG_GPDR1_VAL 0xfcffab83 +#define CFG_GPDR2_VAL 0x0001ffff +/* Set and Clear registers */ +#define CFG_GPSR0_VAL 0x00008000 +#define CFG_GPSR1_VAL 0x00ff0002 +#define CFG_GPSR2_VAL 0x0001c000 +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +/* Edge detect registers (these are set by the kernel) */ +#define CFG_GRER0_VAL 0x00002180 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GFER0_VAL 0x000043e0 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 +/* Alternate function registers */ +#define CFG_GAFR0_L_VAL 0x80000004 +#define CFG_GAFR0_U_VAL 0x595a8010 +#define CFG_GAFR1_L_VAL 0x699a9559 +#define CFG_GAFR1_U_VAL 0xaaa5aaaa +#define CFG_GAFR2_L_VAL 0xaaaaaaaa +#define CFG_GAFR2_U_VAL 0x00000002 + +/* + * Clocks, power control and interrupts + */ +#define CFG_PSSR_VAL 0x00000030 +#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */ +#define CFG_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */ +#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ + +/* FIXME + * + * RTC settings + * Watchdog + * + */ + +/* + * Memory settings + * + */ +#define CFG_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */ +#define CFG_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */ +#define CFG_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */ +#define CFG_MDCNFG_VAL 0x000009c9 +#define CFG_MDMRS_VAL 0x00220022 +#define CFG_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */ + +/* + * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +/* Board specific defines */ + +#ifndef __ASSEMBLY__ + +/* global prototypes */ +void led_code(int code, int color); + +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h new file mode 100644 index 0000000..dc702cf --- /dev/null +++ b/include/configs/xsengine.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_XSENGINE 1 +#define CONFIG_MMC 1 +#define BOARD_POST_INIT 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +/* FLASH organization */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */ +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * JFFS2 partitions + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=xsengine-0" +#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)" +*/ + +/* Environment settings */ +#define CONFIG_ENV_OVERWRITE +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/ +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */ + +/* Size of malloc() pool */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* Hardware drivers */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE 0x04000300 +#define CONFIG_SMC_USE_32_BIT 1 + +/* select serial console configuration */ +#define CONFIG_FFUART 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.1.50 +#define CONFIG_SERVERIP 192.168.1.2 +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200" +#define CONFIG_CMDLINE_TAG + +/* Miscellaneous configurable options */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0xA0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */ +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ +#define CFG_MMC_BASE 0xF0000000 +#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */ + +/* Stack sizes - The stack sizes are set up in start.S using the settings below */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* GP set register */ +#define CFG_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */ +#define CFG_GPSR1_VAL 0x00020000 /* nPWE */ +#define CFG_GPSR2_VAL 0x0000C000 /* CS2, CS3 */ + +/* GP clear register */ +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 + +/* GP direction register */ +#define CFG_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */ +#define CFG_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */ +#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */ + +/* GP rising edge detect register */ +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 + +/* GP falling edge detect register */ +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 + +/* GP alternate function register */ +#define CFG_GAFR0_L_VAL 0x80000000 /* CS1 */ +#define CFG_GAFR0_U_VAL 0x00000010 /* RDY */ +#define CFG_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */ +#define CFG_GAFR1_U_VAL 0x00000008 /* nPWE */ +#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */ +#define CFG_GAFR2_U_VAL 0x00000000 + +#define CFG_PSSR_VAL 0x00000020 /* Power manager sleep status */ +#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */ +#define CFG_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */ +#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ + +/* Memory settings */ +#define CFG_MSC0_VAL 0x25F425F0 + +/* MDCNFG: SDRAM Configuration Register */ +#define CFG_MDCNFG_VAL 0x000009C9 + +/* MDREFR: SDRAM Refresh Control Register */ +#define CFG_MDREFR_VAL 0x00018018 + +/* MDMRS: Mode Register Set Configuration Register */ +#define CFG_MDMRS_VAL 0x00220022 + +#endif /* __CONFIG_H */ diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h new file mode 100644 index 0000000..d3e9671 --- /dev/null +++ b/include/configs/yellowstone.h @@ -0,0 +1,315 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * yellowstone.h - configuration for YELLOWSTONE board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_YOLLOWSTONE 1 /* Board is Yellowstone */ +#define CONFIG_440GR 1 /* Specific PPC440EP support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ +#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ +/*Don't change either of these*/ + +#define CFG_USB_DEVICE 0x50000000 +#define CFG_NVRAM_BASE_ADDR 0x80000000 +#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) +#define CFG_BOOT_BASE_ADDR 0xf0000000 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in SDRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CFG_INIT_RAM_END (8 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/*define this if you want console on UART1*/ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CFG_SDRAM_BANKS (2) + + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#endif /* CFG_ENV_IS_IN_EEPROM */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=yellowstone\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/yellowstone/uImage\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc100000\0" \ + "load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \ + "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ + "cp.b 100000 fff80000 80000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ +#define CONFIG_PHY1_ADDR 3 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#ifdef CONFIG_440EP +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/*Comment this out to enable USB 1.1 device*/ +#define USB_2_0_DEVICE +#endif /*CONFIG_440EP*/ + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#else +#define CONFIG_HW_WATCHDOG /* watchdog */ +#endif + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h new file mode 100644 index 0000000..a67b834 --- /dev/null +++ b/include/configs/yosemite.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * yosemite.h - configuration for YOSEMITE board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_YOSEMITE 1 /* Board is Yosemite */ +#define CONFIG_440EP 1 /* Specific PPC440EP support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ +#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ +/*Don't change either of these*/ + +#define CFG_USB_DEVICE 0x50000000 +#define CFG_NVRAM_BASE_ADDR 0x80000000 +#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) +#define CFG_BOOT_BASE_ADDR 0xf0000000 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in SDRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CFG_INIT_RAM_END (8 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/*define this if you want console on UART1*/ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CFG_SDRAM_BANKS (2) + + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#endif /* CFG_ENV_IS_IN_EEPROM */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=yosemite\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/yosemite/uImage\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc100000\0" \ + "load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0" \ + "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ + "cp.b 100000 fff80000 80000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ +#define CONFIG_PHY1_ADDR 3 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#ifdef CONFIG_440EP +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/*Comment this out to enable USB 1.1 device*/ +#define USB_2_0_DEVICE +#endif /*CONFIG_440EP*/ + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#else +#define CONFIG_HW_WATCHDOG /* watchdog */ +#endif + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ + CFG_CMD_USB ) + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/console.h b/include/console.h new file mode 100644 index 0000000..06ec32a --- /dev/null +++ b/include/console.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CONSOLE_H_ +#define _CONSOLE_H_ + +#include + +/* +** VARIABLES +*/ + +extern device_t *stdio_devices[] ; +extern char *stdio_names[MAX_FILES] ; + +int console_realloc(int top); + +#endif diff --git a/include/cramfs/cramfs_fs.h b/include/cramfs/cramfs_fs.h new file mode 100644 index 0000000..9f1b1d5 --- /dev/null +++ b/include/cramfs/cramfs_fs.h @@ -0,0 +1,122 @@ +#ifndef __CRAMFS_H +#define __CRAMFS_H + +#define CRAMFS_MAGIC 0x28cd3d45 /* some random number */ +#define CRAMFS_SIGNATURE "Compressed ROMFS" + +/* + * Width of various bitfields in struct cramfs_inode. + * Primarily used to generate warnings in mkcramfs. + */ +#define CRAMFS_MODE_WIDTH 16 +#define CRAMFS_UID_WIDTH 16 +#define CRAMFS_SIZE_WIDTH 24 +#define CRAMFS_GID_WIDTH 8 +#define CRAMFS_NAMELEN_WIDTH 6 +#define CRAMFS_OFFSET_WIDTH 26 + +/* + * Since inode.namelen is a unsigned 6-bit number, the maximum cramfs + * path length is 63 << 2 = 252. + */ +#define CRAMFS_MAXPATHLEN (((1 << CRAMFS_NAMELEN_WIDTH) - 1) << 2) + +/* + * Reasonably terse representation of the inode data. + */ +struct cramfs_inode { + u32 mode:CRAMFS_MODE_WIDTH, uid:CRAMFS_UID_WIDTH; + + /* SIZE for device files is i_rdev */ + u32 size:CRAMFS_SIZE_WIDTH, gid:CRAMFS_GID_WIDTH; + + /* NAMELEN is the length of the file name, divided by 4 and + rounded up. (cramfs doesn't support hard links.) */ + /* OFFSET: For symlinks and non-empty regular files, this + contains the offset (divided by 4) of the file data in + compressed form (starting with an array of block pointers; + see README). For non-empty directories it is the offset + (divided by 4) of the inode of the first file in that + directory. For anything else, offset is zero. */ + u32 namelen:CRAMFS_NAMELEN_WIDTH, offset:CRAMFS_OFFSET_WIDTH; +}; + +struct cramfs_info { + u32 crc; + u32 edition; + u32 blocks; + u32 files; +}; + +/* + * Superblock information at the beginning of the FS. + */ +struct cramfs_super { + u32 magic; /* 0x28cd3d45 - random number */ + u32 size; /* length in bytes */ + u32 flags; /* feature flags */ + u32 future; /* reserved for future use */ + u8 signature[16]; /* "Compressed ROMFS" */ + struct cramfs_info fsid; /* unique filesystem info */ + u8 name[16]; /* user-defined name */ + struct cramfs_inode root; /* root inode data */ +}; + +/* + * Feature flags + * + * 0x00000000 - 0x000000ff: features that work for all past kernels + * 0x00000100 - 0xffffffff: features that don't work for past kernels + */ +#define CRAMFS_FLAG_FSID_VERSION_2 0x00000001 /* fsid version #2 */ +#define CRAMFS_FLAG_SORTED_DIRS 0x00000002 /* sorted dirs */ +#define CRAMFS_FLAG_HOLES 0x00000100 /* support for holes */ +#define CRAMFS_FLAG_WRONG_SIGNATURE 0x00000200 /* reserved */ +#define CRAMFS_FLAG_SHIFTED_ROOT_OFFSET 0x00000400 /* shifted root fs */ + +/* + * Valid values in super.flags. Currently we refuse to mount + * if (flags & ~CRAMFS_SUPPORTED_FLAGS). Maybe that should be + * changed to test super.future instead. + */ +#define CRAMFS_SUPPORTED_FLAGS ( 0x000000ff \ + | CRAMFS_FLAG_HOLES \ + | CRAMFS_FLAG_WRONG_SIGNATURE \ + | CRAMFS_FLAG_SHIFTED_ROOT_OFFSET ) + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define CRAMFS_16(x) (x) +#define CRAMFS_24(x) (x) +#define CRAMFS_32(x) (x) +#define CRAMFS_GET_NAMELEN(x) ((x)->namelen) +#define CRAMFS_GET_OFFSET(x) ((x)->offset) +#define CRAMFS_SET_OFFSET(x,y) ((x)->offset = (y)) +#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y)) +#elif __BYTE_ORDER == __BIG_ENDIAN +#ifdef __KERNEL__ +#define CRAMFS_16(x) swab16(x) +#define CRAMFS_24(x) ((swab32(x)) >> 8) +#define CRAMFS_32(x) swab32(x) +#else /* not __KERNEL__ */ +#define CRAMFS_16(x) bswap_16(x) +#define CRAMFS_24(x) ((bswap_32(x)) >> 8) +#define CRAMFS_32(x) bswap_32(x) +#endif /* not __KERNEL__ */ +#define CRAMFS_GET_NAMELEN(x) (((u8*)(x))[8] & 0x3f) +#define CRAMFS_GET_OFFSET(x) ((CRAMFS_24(((u32*)(x))[2] & 0xffffff) << 2) |\ + ((((u32*)(x))[2] & 0xc0000000) >> 30)) +#define CRAMFS_SET_NAMELEN(x,y) (((u8*)(x))[8] = (((0x3f & (y))) | \ + (0xc0 & ((u8*)(x))[8]))) +#define CRAMFS_SET_OFFSET(x,y) (((u32*)(x))[2] = (((y) & 3) << 30) | \ + CRAMFS_24((((y) & 0x03ffffff) >> 2)) | \ + (((u32)(((u8*)(x))[8] & 0x3f)) << 24)) +#else +#error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN" +#endif + +/* Uncompression interfaces to the underlying zlib */ +int cramfs_uncompress_block(void *dst, void *src, int srclen); +int cramfs_uncompress_init(void); +int cramfs_uncompress_exit(void); + +#endif /* __CRAMFS_H */ diff --git a/include/cramfs/cramfs_fs_sb.h b/include/cramfs/cramfs_fs_sb.h new file mode 100644 index 0000000..bc23f94 --- /dev/null +++ b/include/cramfs/cramfs_fs_sb.h @@ -0,0 +1,19 @@ +#ifndef _CRAMFS_FS_SB +#define _CRAMFS_FS_SB + +/* + * cramfs super-block data in memory + */ +struct cramfs_sb_info { + unsigned long magic; + unsigned long size; + unsigned long blocks; + unsigned long files; + unsigned long flags; +#ifdef CONFIG_CRAMFS_LINEAR + unsigned long linear_phys_addr; + char * linear_virt_addr; +#endif +}; + +#endif diff --git a/include/dataflash.h b/include/dataflash.h new file mode 100644 index 0000000..650454e --- /dev/null +++ b/include/dataflash.h @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2003 + * Data Flash Atmel Description File + * Author : Hamid Ikdoumi (Atmel) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* File Name : dataflash.h */ +/* Object : Data Flash Atmel Description File */ +/* Translator : */ +/* */ +/* 1.0 03/04/01 HI : Creation */ +/* 1.2 20/10/02 FB : Adapatation Service and Lib v3 */ +/*----------------------------------------------------------------------*/ + +#ifndef _DataFlash_h +#define _DataFlash_h + + +#include +#include "config.h" + +/*number of protected area*/ +#define NB_DATAFLASH_AREA 4 + +/*define the area structure*/ +typedef struct { + unsigned long start; + unsigned long end; + unsigned char protected; +} dataflash_protect_t; + +typedef unsigned int AT91S_DataFlashStatus; + +/*----------------------------------------------------------------------*/ +/* DataFlash Structures */ +/*----------------------------------------------------------------------*/ + +/*---------------------------------------------*/ +/* DataFlash Descriptor Structure Definition */ +/*---------------------------------------------*/ +typedef struct _AT91S_DataflashDesc { + unsigned char *tx_cmd_pt; + unsigned int tx_cmd_size; + unsigned char *rx_cmd_pt; + unsigned int rx_cmd_size; + unsigned char *tx_data_pt; + unsigned int tx_data_size; + unsigned char *rx_data_pt; + unsigned int rx_data_size; + volatile unsigned char state; + volatile unsigned char DataFlash_state; + unsigned char command[8]; +} AT91S_DataflashDesc, *AT91PS_DataflashDesc; + +/*---------------------------------------------*/ +/* DataFlash device definition structure */ +/*---------------------------------------------*/ +typedef struct _AT91S_Dataflash { + int pages_number; /* dataflash page number */ + int pages_size; /* dataflash page size */ + int page_offset; /* page offset in command */ + int byte_mask; /* byte mask in command */ + int cs; + dataflash_protect_t area_list[NB_DATAFLASH_AREA]; /* area protection status */ +} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures; + +/*---------------------------------------------*/ +/* DataFlash Structure Definition */ +/*---------------------------------------------*/ +typedef struct _AT91S_DataFlash { + AT91PS_DataflashDesc pDataFlashDesc; /* dataflash descriptor */ + AT91PS_DataflashFeatures pDevice; /* Pointer on a dataflash features array */ +} AT91S_DataFlash, *AT91PS_DataFlash; + + +typedef struct _AT91S_DATAFLASH_INFO { + + AT91S_DataflashDesc Desc; + AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */ + unsigned long logical_address; + unsigned int id; /* device id */ +} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO; + + +/*-------------------------------------------------------------------------------------------------*/ + +#define AT45DB161 0x2c +#define AT45DB321 0x34 +#define AT45DB642 0x3c +#define AT45DB128 0x10 + +#define AT91C_DATAFLASH_TIMEOUT 10000 /* For AT91F_DataFlashWaitReady */ + +/* DataFlash return value */ +#define DATAFLASH_BUSY 0x00 +#define DATAFLASH_OK 0x01 +#define DATAFLASH_ERROR 0x02 +#define DATAFLASH_MEMORY_OVERFLOW 0x03 +#define DATAFLASH_BAD_COMMAND 0x04 +#define DATAFLASH_BAD_ADDRESS 0x05 + + +/* Driver State */ +#define IDLE 0x0 +#define BUSY 0x1 +#define ERROR 0x2 + +/* DataFlash Driver State */ +#define GET_STATUS 0x0F + +/*-------------------------------------------------------------------------------------------------*/ +/* Command Definition */ +/*-------------------------------------------------------------------------------------------------*/ + +/* READ COMMANDS */ +#define DB_CONTINUOUS_ARRAY_READ 0xE8 /* Continuous array read */ +#define DB_BURST_ARRAY_READ 0xE8 /* Burst array read */ +#define DB_PAGE_READ 0xD2 /* Main memory page read */ +#define DB_BUF1_READ 0xD4 /* Buffer 1 read */ +#define DB_BUF2_READ 0xD6 /* Buffer 2 read */ +#define DB_STATUS 0xD7 /* Status Register */ + +/* PROGRAM and ERASE COMMANDS */ +#define DB_BUF1_WRITE 0x84 /* Buffer 1 write */ +#define DB_BUF2_WRITE 0x87 /* Buffer 2 write */ +#define DB_BUF1_PAGE_ERASE_PGM 0x83 /* Buffer 1 to main memory page program with built-In erase */ +#define DB_BUF1_PAGE_ERASE_FASTPGM 0x93 /* Buffer 1 to main memory page program with built-In erase, Fast program */ +#define DB_BUF2_PAGE_ERASE_PGM 0x86 /* Buffer 2 to main memory page program with built-In erase */ +#define DB_BUF2_PAGE_ERASE_FASTPGM 0x96 /* Buffer 1 to main memory page program with built-In erase, Fast program */ +#define DB_BUF1_PAGE_PGM 0x88 /* Buffer 1 to main memory page program without built-In erase */ +#define DB_BUF1_PAGE_FASTPGM 0x98 /* Buffer 1 to main memory page program without built-In erase, Fast program */ +#define DB_BUF2_PAGE_PGM 0x89 /* Buffer 2 to main memory page program without built-In erase */ +#define DB_BUF2_PAGE_FASTPGM 0x99 /* Buffer 1 to main memory page program without built-In erase, Fast program */ +#define DB_PAGE_ERASE 0x81 /* Page Erase */ +#define DB_BLOCK_ERASE 0x50 /* Block Erase */ +#define DB_PAGE_PGM_BUF1 0x82 /* Main memory page through buffer 1 */ +#define DB_PAGE_FASTPGM_BUF1 0x92 /* Main memory page through buffer 1, Fast program */ +#define DB_PAGE_PGM_BUF2 0x85 /* Main memory page through buffer 2 */ +#define DB_PAGE_FastPGM_BUF2 0x95 /* Main memory page through buffer 2, Fast program */ + +/* ADDITIONAL COMMANDS */ +#define DB_PAGE_2_BUF1_TRF 0x53 /* Main memory page to buffer 1 transfert */ +#define DB_PAGE_2_BUF2_TRF 0x55 /* Main memory page to buffer 2 transfert */ +#define DB_PAGE_2_BUF1_CMP 0x60 /* Main memory page to buffer 1 compare */ +#define DB_PAGE_2_BUF2_CMP 0x61 /* Main memory page to buffer 2 compare */ +#define DB_AUTO_PAGE_PGM_BUF1 0x58 /* Auto page rewrite throught buffer 1 */ +#define DB_AUTO_PAGE_PGM_BUF2 0x59 /* Auto page rewrite throught buffer 2 */ + +/*-------------------------------------------------------------------------------------------------*/ + +extern int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size); +extern int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr); +extern int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr); +extern int addr_dataflash (unsigned long addr); +extern int read_dataflash (unsigned long addr, unsigned long size, char *result); +extern int write_dataflash (unsigned long addr, unsigned long dest, unsigned long size); +extern void dataflash_print_info (void); +extern void dataflash_perror (int err); + +#endif diff --git a/include/devices.h b/include/devices.h new file mode 100644 index 0000000..2d9e282 --- /dev/null +++ b/include/devices.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifndef _DEVICES_H_ +#define _DEVICES_H_ + +/* + * CONSOLE DEVICES + */ + +#define DEV_FLAGS_INPUT 0x00000001 /* Device can be used as input console */ +#define DEV_FLAGS_OUTPUT 0x00000002 /* Device can be used as output console */ +#define DEV_FLAGS_SYSTEM 0x80000000 /* Device is a system device */ +#define DEV_EXT_VIDEO 0x00000001 /* Video extensions supported */ + +/* Device information */ +typedef struct { + int flags; /* Device flags: input/output/system */ + int ext; /* Supported extensions */ + char name[16]; /* Device name */ + +/* GENERAL functions */ + + int (*start) (void); /* To start the device */ + int (*stop) (void); /* To stop the device */ + +/* OUTPUT functions */ + + void (*putc) (const char c); /* To put a char */ + void (*puts) (const char *s); /* To put a string (accelerator) */ + +/* INPUT functions */ + + int (*tstc) (void); /* To test if a char is ready... */ + int (*getc) (void); /* To get that char */ + +/* Other functions */ + + void *priv; /* Private extensions */ +} device_t; + +/* + * VIDEO EXTENSIONS + */ +#define VIDEO_FORMAT_RGB_INDEXED 0x0000 +#define VIDEO_FORMAT_RGB_DIRECTCOLOR 0x0001 +#define VIDEO_FORMAT_YUYV_4_4_4 0x0010 +#define VIDEO_FORMAT_YUYV_4_2_2 0x0011 + +typedef struct { + void *address; /* Address of framebuffer */ + ushort width; /* Horizontal resolution */ + ushort height; /* Vertical resolution */ + uchar format; /* Format */ + uchar colors; /* Colors number or color depth */ + void (*setcolreg) (int, int, int, int); + void (*getcolreg) (int, void *); +} video_ext_t; + +/* + * VARIABLES + */ +extern list_t devlist; +extern device_t *stdio_devices[]; +extern char *stdio_names[MAX_FILES]; + +/* + * PROTOTYPES + */ +int device_register (device_t * dev); +int devices_init (void); +int devices_done (void); +int device_deregister(char *devname); +#ifdef CONFIG_LCD +int drv_lcd_init (void); +#endif +#ifdef CONFIG_VFD +int drv_vfd_init (void); +#endif +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +int drv_video_init (void); +#endif +#ifdef CONFIG_KEYBOARD +int drv_keyboard_init (void); +#endif +#ifdef CONFIG_USB_TTY +int drv_usbtty_init (void); +#endif +#ifdef CONFIG_NETCONSOLE +int drv_nc_init (void); +#endif + +#endif /* _DEVICES_H_ */ diff --git a/include/dm9161.h b/include/dm9161.h new file mode 100644 index 0000000..f5bfb19 --- /dev/null +++ b/include/dm9161.h @@ -0,0 +1,130 @@ +/* + * NOTE: DAVICOM ethernet Physical layer + * + * Version: @(#)DM9161.h 1.0.0 01/10/2001 + * + * Authors: ATMEL Rousset + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + + +/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */ + +#define DM9161_BMCR 0 /* Basic Mode Control Register */ +#define DM9161_BMSR 1 /* Basic Mode Status Register */ +#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */ +#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */ +#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */ +#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */ +#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */ +#define DM9161_DSCR 16 /* Specified Configuration Register */ +#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */ +#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */ +#define DM9161_MDINTR 21 /* Specified Interrupt Register */ +#define DM9161_RECR 22 /* Specified Receive Error Counter Register */ +#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */ +#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */ + + +/* --Bit definitions: DM9161_BMCR */ +#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */ +#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */ +#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */ +#define DM9161_AUTONEG (1 << 12) +#define DM9161_POWER_DOWN (1 << 11) +#define DM9161_ISOLATE (1 << 10) +#define DM9161_RESTART_AUTONEG (1 << 9) +#define DM9161_DUPLEX_MODE (1 << 8) +#define DM9161_COLLISION_TEST (1 << 7) + +/*--Bit definitions: DM9161_BMSR */ +#define DM9161_100BASE_T4 (1 << 15) +#define DM9161_100BASE_TX_FD (1 << 14) +#define DM9161_100BASE_T4_HD (1 << 13) +#define DM9161_10BASE_T_FD (1 << 12) +#define DM9161_10BASE_T_HD (1 << 11) +#define DM9161_MF_PREAMB_SUPPR (1 << 6) +#define DM9161_AUTONEG_COMP (1 << 5) +#define DM9161_REMOTE_FAULT (1 << 4) +#define DM9161_AUTONEG_ABILITY (1 << 3) +#define DM9161_LINK_STATUS (1 << 2) +#define DM9161_JABBER_DETECT (1 << 1) +#define DM9161_EXTEND_CAPAB (1 << 0) + +/*--definitions: DM9161_PHYID1 */ +#define DM9161_PHYID1_OUI 0x606E +#define DM9161_LSB_MASK 0x3F + +/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */ +#define DM9161_NP (1 << 15) +#define DM9161_ACK (1 << 14) +#define DM9161_RF (1 << 13) +#define DM9161_FCS (1 << 10) +#define DM9161_T4 (1 << 9) +#define DM9161_TX_FDX (1 << 8) +#define DM9161_TX_HDX (1 << 7) +#define DM9161_10_FDX (1 << 6) +#define DM9161_10_HDX (1 << 5) +#define DM9161_AN_IEEE_802_3 0x0001 + +/*--Bit definitions: DM9161_ANER */ +#define DM9161_PDF (1 << 4) +#define DM9161_LP_NP_ABLE (1 << 3) +#define DM9161_NP_ABLE (1 << 2) +#define DM9161_PAGE_RX (1 << 1) +#define DM9161_LP_AN_ABLE (1 << 0) + +/*--Bit definitions: DM9161_DSCR */ +#define DM9161_BP4B5B (1 << 15) +#define DM9161_BP_SCR (1 << 14) +#define DM9161_BP_ALIGN (1 << 13) +#define DM9161_BP_ADPOK (1 << 12) +#define DM9161_REPEATER (1 << 11) +#define DM9161_TX (1 << 10) +#define DM9161_RMII_ENABLE (1 << 8) +#define DM9161_F_LINK_100 (1 << 7) +#define DM9161_SPLED_CTL (1 << 6) +#define DM9161_COLLED_CTL (1 << 5) +#define DM9161_RPDCTR_EN (1 << 4) +#define DM9161_SM_RST (1 << 3) +#define DM9161_MFP SC (1 << 2) +#define DM9161_SLEEP (1 << 1) +#define DM9161_RLOUT (1 << 0) + +/*--Bit definitions: DM9161_DSCSR */ +#define DM9161_100FDX (1 << 15) +#define DM9161_100HDX (1 << 14) +#define DM9161_10FDX (1 << 13) +#define DM9161_10HDX (1 << 12) + +/*--Bit definitions: DM9161_10BTCSR */ +#define DM9161_LP_EN (1 << 14) +#define DM9161_HBE (1 << 13) +#define DM9161_SQUELCH (1 << 12) +#define DM9161_JABEN (1 << 11) +#define DM9161_10BT_SER (1 << 10) +#define DM9161_POLR (1 << 0) + + +/*--Bit definitions: DM9161_MDINTR */ +#define DM9161_INTR_PEND (1 << 15) +#define DM9161_FDX_MASK (1 << 11) +#define DM9161_SPD_MASK (1 << 10) +#define DM9161_LINK_MASK (1 << 9) +#define DM9161_INTR_MASK (1 << 8) +#define DM9161_FDX_CHANGE (1 << 4) +#define DM9161_SPD_CHANGE (1 << 3) +#define DM9161_LINK_CHANGE (1 << 2) +#define DM9161_INTR_STATUS (1 << 0) + + +/****************** function prototypes **********************/ +unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac); +unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac); +unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status); +unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac); diff --git a/include/dtt.h b/include/dtt.h new file mode 100644 index 0000000..a17aa67 --- /dev/null +++ b/include/dtt.h @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Digital Thermometers and Thermostats. + */ +#ifndef _DTT_H_ +#define _DTT_H_ + +#if defined(CONFIG_DTT_LM75) || \ + defined(CONFIG_DTT_DS1621) || \ + defined(CONFIG_DTT_ADM1021) + +#define CONFIG_DTT /* We have a DTT */ + +#ifndef CONFIG_DTT_ADM1021 +#define DTT_COMMERCIAL_MAX_TEMP 70 /* 0 - +70 C */ +#define DTT_INDUSTRIAL_MAX_TEMP 85 /* -40 - +85 C */ +#define DTT_AUTOMOTIVE_MAX_TEMP 105 /* -40 - +105 C */ +#ifndef CFG_DTT_MAX_TEMP +#define CFG_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP +#endif +#ifndef CFG_DTT_HYSTERESIS +#define CFG_DTT_HYSTERESIS 5 /* 5 C */ +#endif +#endif /* CONFIG_DTT_ADM1021 */ + +extern int dtt_init (void); +extern int dtt_read(int sensor, int reg); +extern int dtt_write(int sensor, int reg, int val); +extern int dtt_get_temp(int sensor); +#endif + +#if defined(CONFIG_DTT_LM75) +#define DTT_READ_TEMP 0x0 +#define DTT_CONFIG 0x1 +#define DTT_TEMP_HYST 0x2 +#define DTT_TEMP_SET 0x3 +#endif + +#if defined(CONFIG_DTT_DS1621) +#define DTT_READ_TEMP 0xAA +#define DTT_READ_COUNTER 0xA8 +#define DTT_READ_SLOPE 0xA9 +#define DTT_WRITE_START_CONV 0xEE +#define DTT_WRITE_STOP_CONV 0x22 +#define DTT_TEMP_HIGH 0xA1 +#define DTT_TEMP_LOW 0xA2 +#define DTT_CONFIG 0xAC +#endif + +#if defined(CONFIG_DTT_ADM1021) +#define DTT_READ_LOC_VALUE 0x00 +#define DTT_READ_REM_VALUE 0x01 +#define DTT_READ_STATUS 0x02 +#define DTT_READ_CONFIG 0x03 +#define DTT_READ_CONVRATE 0x04 +#define DTT_READ_LOC_HIGHLIM 0x05 +#define DTT_READ_LOC_LOWLIM 0x06 +#define DTT_READ_REM_HIGHLIM 0x07 +#define DTT_READ_REM_LOWLIM 0x08 +#define DTT_READ_DEVID 0xfe + +#define DTT_WRITE_CONFIG 0x09 +#define DTT_WRITE_CONVRATE 0x0a +#define DTT_WRITE_LOC_HIGHLIM 0x0b +#define DTT_WRITE_LOC_LOWLIM 0x0c +#define DTT_WRITE_REM_HIGHLIM 0x0d +#define DTT_WRITE_REM_LOWLIM 0x0e +#define DTT_WRITE_ONESHOT 0x0f + +#define DTT_STATUS_BUSY 0x80 /* 1=ADC Converting */ +#define DTT_STATUS_LHIGH 0x40 /* 1=Local High Temp Limit Tripped */ +#define DTT_STATUS_LLOW 0x20 /* 1=Local Low Temp Limit Tripped */ +#define DTT_STATUS_RHIGH 0x10 /* 1=Remote High Temp Limit Tripped */ +#define DTT_STATUS_RLOW 0x08 /* 1=Remote Low Temp Limit Tripped */ +#define DTT_STATUS_OPEN 0x04 /* 1=Remote Sensor Open-Circuit */ + +#define DTT_CONFIG_ALERT_MASKED 0x80 /* 0=ALERT Enabled, 1=ALERT Masked */ +#define DTT_CONFIG_STANDBY 0x40 /* 0=Run, 1=Standby */ + +#define DTT_ADM1021_DEVID 0x41 +#endif + +#endif /* _DTT_H_ */ diff --git a/include/e500.h b/include/e500.h new file mode 100644 index 0000000..8e3bf8c --- /dev/null +++ b/include/e500.h @@ -0,0 +1,115 @@ +/* + * Copyright 2003 Motorola,Inc. + * Xianghua Xiao(x.xiao@motorola.com) + */ + +#ifndef __E500_H__ +#define __E500_H__ + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqProcessor; + unsigned long freqSystemBus; +} MPC85xx_SYS_INFO; + +#endif /* _ASMLANGUAGE */ + +/* Motorola E500 core provides 16 TLB1 entries; they can be used for + * initial memory mapping like legacy BAT registers do. Usually we + * use four MAS registers(MAS0-3) to operate on TLB1 entries. + * + * While there are 16 Entries with variable Page Sizes in TLB1, + * there are also 256 Entries with fixed 4K pages in TLB0. + * + * We also need LAWs(Local Access Window) to associate a range of + * the local 32-bit address space with a particular target interface + * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM. + * + * We put TLB1/LAW code here because memory mapping is board-specific + * instead of cpu-specific. + * + * While these macros are all nominally for TLB1 by name, they can + * also be used for TLB0 as well. + */ + + +/* + * Convert addresses to Effective and Real Page Numbers. + * Grab the high 20-bits and shift 'em down, dropping the "byte offset". + */ +#define E500_TLB_EPN(addr) (((addr) >> 12) & 0xfffff) +#define E500_TLB_RPN(addr) (((addr) >> 12) & 0xfffff) + + +/* MAS0 + * tlbsel(TLB Select):0,1 + * esel(Entry Select): 0,1,2,...,15 for TLB1 + * nv(Next victim):0,1 + */ +#define TLB1_MAS0(tlbsel,esel,nv) \ + ((((tlbsel) << 28) & MAS0_TLBSEL) |\ + (((esel) << 16) & MAS0_ESEL ) |\ + (nv) ) + + +/* MAS1 + * v(TLB valid bit):0,1 + * iprot(invalidate protect):0,1 + * tid(translation identity):8bit to match process IDs + * ts(translation space,comparing with MSR[IS,DS]): 0,1 + * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M) + */ +#define TLB1_MAS1(v,iprot,tid,ts,tsize) \ + ((((v) << 31) & MAS1_VALID) |\ + (((iprot) << 30) & MAS1_IPROT) |\ + (((tid) << 16) & MAS1_TID) |\ + (((ts) << 12) & MAS1_TS) |\ + (((tsize) << 8) & MAS1_TSIZE) ) + + +/* MAS2 + * epn(effective page number):20bits + * sharen(Shared cache state):0,1 + * x0,x1(implementation specific page attribute):0,1 + * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded, + * endianness):0,1 + */ +#define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \ + ((((epn) << 12) & MAS2_EPN) |\ + (((sharen) << 9) & MAS2_SHAREN) |\ + (((x0) << 6) & MAS2_X0) |\ + (((x1) << 5) & MAS2_X1) |\ + (((w) << 4) & MAS2_W) |\ + (((i) << 3) & MAS2_I) |\ + (((m) << 2) & MAS2_M) |\ + (((g) << 1) & MAS2_G) |\ + (e) ) + + +/* MAS3 + * rpn(real page number):20bits + * u0-u3(user bits, useful for page table management in OS):0,1 + * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read, + * write,execute permission). + */ +#define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \ + ((((rpn) << 12) & MAS3_RPN) |\ + (((u0) << 9) & MAS3_U0) |\ + (((u1) << 8) & MAS3_U1) |\ + (((u2) << 7) & MAS3_U2) |\ + (((u3) << 6) & MAS3_U3) |\ + (((ux) << 5) & MAS3_UX) |\ + (((sx) << 4) & MAS3_SX) |\ + (((uw) << 3) & MAS3_UW) |\ + (((sw) << 2) & MAS3_SW) |\ + (((ur) << 1) & MAS3_UR) |\ + (sr) ) + + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ + +#endif /* __E500_H__ */ diff --git a/include/elf.h b/include/elf.h new file mode 100644 index 0000000..d0febc5 --- /dev/null +++ b/include/elf.h @@ -0,0 +1,606 @@ +/* + * Copyright (c) 1995, 1996, 2001, 2002 + * Erik Theisen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This is the ELF ABI header file + * formerly known as "elf_abi.h". + */ + +#ifndef _ELF_H +#define _ELF_H + +#if defined(__BEOS__) || \ + defined(__NetBSD__) || \ + defined(__FreeBSD__) || \ + defined(__sun__) || \ + defined(__APPLE__) +#include +#elif defined(__linux__) && defined(USE_HOSTCC) +#include +#elif defined(__WIN32__) +#include +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +#endif + +/* + * This version doesn't work for 64-bit ABIs - Erik. + */ + +/* + * These typedefs need to be handled better. + */ +typedef uint32_t Elf32_Addr; /* Unsigned program address */ +typedef uint32_t Elf32_Off; /* Unsigned file offset */ +typedef int32_t Elf32_Sword; /* Signed large integer */ +typedef uint32_t Elf32_Word; /* Unsigned large integer */ +typedef uint16_t Elf32_Half; /* Unsigned medium integer */ + +/* e_ident[] identification indexes */ +#define EI_MAG0 0 /* file ID */ +#define EI_MAG1 1 /* file ID */ +#define EI_MAG2 2 /* file ID */ +#define EI_MAG3 3 /* file ID */ +#define EI_CLASS 4 /* file class */ +#define EI_DATA 5 /* data encoding */ +#define EI_VERSION 6 /* ELF header version */ +#define EI_OSABI 7 /* OS/ABI specific ELF extensions */ +#define EI_ABIVERSION 8 /* ABI target version */ +#define EI_PAD 9 /* start of pad bytes */ +#define EI_NIDENT 16 /* Size of e_ident[] */ + +/* e_ident[] magic number */ +#define ELFMAG0 0x7f /* e_ident[EI_MAG0] */ +#define ELFMAG1 'E' /* e_ident[EI_MAG1] */ +#define ELFMAG2 'L' /* e_ident[EI_MAG2] */ +#define ELFMAG3 'F' /* e_ident[EI_MAG3] */ +#define ELFMAG "\177ELF" /* magic */ +#define SELFMAG 4 /* size of magic */ + +/* e_ident[] file class */ +#define ELFCLASSNONE 0 /* invalid */ +#define ELFCLASS32 1 /* 32-bit objs */ +#define ELFCLASS64 2 /* 64-bit objs */ +#define ELFCLASSNUM 3 /* number of classes */ + +/* e_ident[] data encoding */ +#define ELFDATANONE 0 /* invalid */ +#define ELFDATA2LSB 1 /* Little-Endian */ +#define ELFDATA2MSB 2 /* Big-Endian */ +#define ELFDATANUM 3 /* number of data encode defines */ + +/* e_ident[] OS/ABI specific ELF extensions */ +#define ELFOSABI_NONE 0 /* No extension specified */ +#define ELFOSABI_HPUX 1 /* Hewlett-Packard HP-UX */ +#define ELFOSABI_NETBSD 2 /* NetBSD */ +#define ELFOSABI_LINUX 3 /* Linux */ +#define ELFOSABI_SOLARIS 6 /* Sun Solaris */ +#define ELFOSABI_AIX 7 /* AIX */ +#define ELFOSABI_IRIX 8 /* IRIX */ +#define ELFOSABI_FREEBSD 9 /* FreeBSD */ +#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX */ +#define ELFOSABI_MODESTO 11 /* Novell Modesto */ +#define ELFOSABI_OPENBSD 12 /* OpenBSD */ +/* 64-255 Architecture-specific value range */ + +/* e_ident[] ABI Version */ +#define ELFABIVERSION 0 + +/* e_ident */ +#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \ + (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \ + (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \ + (ehdr).e_ident[EI_MAG3] == ELFMAG3) + +/* ELF Header */ +typedef struct elfhdr{ + unsigned char e_ident[EI_NIDENT]; /* ELF Identification */ + Elf32_Half e_type; /* object file type */ + Elf32_Half e_machine; /* machine */ + Elf32_Word e_version; /* object file version */ + Elf32_Addr e_entry; /* virtual entry point */ + Elf32_Off e_phoff; /* program header table offset */ + Elf32_Off e_shoff; /* section header table offset */ + Elf32_Word e_flags; /* processor-specific flags */ + Elf32_Half e_ehsize; /* ELF header size */ + Elf32_Half e_phentsize; /* program header entry size */ + Elf32_Half e_phnum; /* number of program header entries */ + Elf32_Half e_shentsize; /* section header entry size */ + Elf32_Half e_shnum; /* number of section header entries */ + Elf32_Half e_shstrndx; /* section header table's "section + header string table" entry offset */ +} Elf32_Ehdr; + +/* e_type */ +#define ET_NONE 0 /* No file type */ +#define ET_REL 1 /* relocatable file */ +#define ET_EXEC 2 /* executable file */ +#define ET_DYN 3 /* shared object file */ +#define ET_CORE 4 /* core file */ +#define ET_NUM 5 /* number of types */ +#define ET_LOOS 0xfe00 /* reserved range for operating */ +#define ET_HIOS 0xfeff /* system specific e_type */ +#define ET_LOPROC 0xff00 /* reserved range for processor */ +#define ET_HIPROC 0xffff /* specific e_type */ + +/* e_machine */ +#define EM_NONE 0 /* No Machine */ +#define EM_M32 1 /* AT&T WE 32100 */ +#define EM_SPARC 2 /* SPARC */ +#define EM_386 3 /* Intel 80386 */ +#define EM_68K 4 /* Motorola 68000 */ +#define EM_88K 5 /* Motorola 88000 */ +#if 0 +#define EM_486 6 /* RESERVED - was Intel 80486 */ +#endif +#define EM_860 7 /* Intel 80860 */ +#define EM_MIPS 8 /* MIPS R3000 Big-Endian only */ +#define EM_S370 9 /* IBM System/370 Processor */ +#define EM_MIPS_RS4_BE 10 /* MIPS R4000 Big-Endian */ +#if 0 +#define EM_SPARC64 11 /* RESERVED - was SPARC v9 + 64-bit unoffical */ +#endif +/* RESERVED 11-14 for future use */ +#define EM_PARISC 15 /* HPPA */ +/* RESERVED 16 for future use */ +#define EM_VPP500 17 /* Fujitsu VPP500 */ +#define EM_SPARC32PLUS 18 /* Enhanced instruction set SPARC */ +#define EM_960 19 /* Intel 80960 */ +#define EM_PPC 20 /* PowerPC */ +#define EM_PPC64 21 /* 64-bit PowerPC */ +#define EM_S390 22 /* IBM System/390 Processor */ +/* RESERVED 23-35 for future use */ +#define EM_V800 36 /* NEC V800 */ +#define EM_FR20 37 /* Fujitsu FR20 */ +#define EM_RH32 38 /* TRW RH-32 */ +#define EM_RCE 39 /* Motorola RCE */ +#define EM_ARM 40 /* Advanced Risc Machines ARM */ +#define EM_ALPHA 41 /* Digital Alpha */ +#define EM_SH 42 /* Hitachi SH */ +#define EM_SPARCV9 43 /* SPARC Version 9 */ +#define EM_TRICORE 44 /* Siemens TriCore embedded processor */ +#define EM_ARC 45 /* Argonaut RISC Core */ +#define EM_H8_300 46 /* Hitachi H8/300 */ +#define EM_H8_300H 47 /* Hitachi H8/300H */ +#define EM_H8S 48 /* Hitachi H8S */ +#define EM_H8_500 49 /* Hitachi H8/500 */ +#define EM_IA_64 50 /* Intel Merced */ +#define EM_MIPS_X 51 /* Stanford MIPS-X */ +#define EM_COLDFIRE 52 /* Motorola Coldfire */ +#define EM_68HC12 53 /* Motorola M68HC12 */ +#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ +#define EM_PCP 55 /* Siemens PCP */ +#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ +#define EM_NDR1 57 /* Denso NDR1 microprocessor */ +#define EM_STARCORE 58 /* Motorola Start*Core processor */ +#define EM_ME16 59 /* Toyota ME16 processor */ +#define EM_ST100 60 /* STMicroelectronic ST100 processor */ +#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ +#define EM_X86_64 62 /* AMD x86-64 */ +#define EM_PDSP 63 /* Sony DSP Processor */ +/* RESERVED 64,65 for future use */ +#define EM_FX66 66 /* Siemens FX66 microcontroller */ +#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ +#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ +#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ +#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ +#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ +#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ +#define EM_SVX 73 /* Silicon Graphics SVx */ +#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ +#define EM_VAX 75 /* Digital VAX */ +#define EM_CHRIS 76 /* Axis Communications embedded proc. */ +#define EM_JAVELIN 77 /* Infineon Technologies emb. proc. */ +#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ +#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ +#define EM_MMIX 80 /* Donald Knuth's edu 64-bit proc. */ +#define EM_HUANY 81 /* Harvard University mach-indep objs */ +#define EM_PRISM 82 /* SiTera Prism */ +#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ +#define EM_FR30 84 /* Fujitsu FR30 */ +#define EM_D10V 85 /* Mitsubishi DV10V */ +#define EM_D30V 86 /* Mitsubishi DV30V */ +#define EM_V850 87 /* NEC v850 */ +#define EM_M32R 88 /* Mitsubishi M32R */ +#define EM_MN10300 89 /* Matsushita MN10200 */ +#define EM_MN10200 90 /* Matsushita MN10200 */ +#define EM_PJ 91 /* picoJava */ +#define EM_NUM 92 /* number of machine types */ + +/* Version */ +#define EV_NONE 0 /* Invalid */ +#define EV_CURRENT 1 /* Current */ +#define EV_NUM 2 /* number of versions */ + +/* Section Header */ +typedef struct { + Elf32_Word sh_name; /* name - index into section header + string table section */ + Elf32_Word sh_type; /* type */ + Elf32_Word sh_flags; /* flags */ + Elf32_Addr sh_addr; /* address */ + Elf32_Off sh_offset; /* file offset */ + Elf32_Word sh_size; /* section size */ + Elf32_Word sh_link; /* section header table index link */ + Elf32_Word sh_info; /* extra information */ + Elf32_Word sh_addralign; /* address alignment */ + Elf32_Word sh_entsize; /* section entry size */ +} Elf32_Shdr; + +/* Special Section Indexes */ +#define SHN_UNDEF 0 /* undefined */ +#define SHN_LORESERVE 0xff00 /* lower bounds of reserved indexes */ +#define SHN_LOPROC 0xff00 /* reserved range for processor */ +#define SHN_HIPROC 0xff1f /* specific section indexes */ +#define SHN_LOOS 0xff20 /* reserved range for operating */ +#define SHN_HIOS 0xff3f /* specific semantics */ +#define SHN_ABS 0xfff1 /* absolute value */ +#define SHN_COMMON 0xfff2 /* common symbol */ +#define SHN_XINDEX 0xffff /* Index is an extra table */ +#define SHN_HIRESERVE 0xffff /* upper bounds of reserved indexes */ + +/* sh_type */ +#define SHT_NULL 0 /* inactive */ +#define SHT_PROGBITS 1 /* program defined information */ +#define SHT_SYMTAB 2 /* symbol table section */ +#define SHT_STRTAB 3 /* string table section */ +#define SHT_RELA 4 /* relocation section with addends*/ +#define SHT_HASH 5 /* symbol hash table section */ +#define SHT_DYNAMIC 6 /* dynamic section */ +#define SHT_NOTE 7 /* note section */ +#define SHT_NOBITS 8 /* no space section */ +#define SHT_REL 9 /* relation section without addends */ +#define SHT_SHLIB 10 /* reserved - purpose unknown */ +#define SHT_DYNSYM 11 /* dynamic symbol table section */ +#define SHT_INIT_ARRAY 14 /* Array of constructors */ +#define SHT_FINI_ARRAY 15 /* Array of destructors */ +#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ +#define SHT_GROUP 17 /* Section group */ +#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ +#define SHT_NUM 19 /* number of section types */ +#define SHT_LOOS 0x60000000 /* Start OS-specific */ +#define SHT_HIOS 0x6fffffff /* End OS-specific */ +#define SHT_LOPROC 0x70000000 /* reserved range for processor */ +#define SHT_HIPROC 0x7fffffff /* specific section header types */ +#define SHT_LOUSER 0x80000000 /* reserved range for application */ +#define SHT_HIUSER 0xffffffff /* specific indexes */ + +/* Section names */ +#define ELF_BSS ".bss" /* uninitialized data */ +#define ELF_COMMENT ".comment" /* version control information */ +#define ELF_DATA ".data" /* initialized data */ +#define ELF_DATA1 ".data1" /* initialized data */ +#define ELF_DEBUG ".debug" /* debug */ +#define ELF_DYNAMIC ".dynamic" /* dynamic linking information */ +#define ELF_DYNSTR ".dynstr" /* dynamic string table */ +#define ELF_DYNSYM ".dynsym" /* dynamic symbol table */ +#define ELF_FINI ".fini" /* termination code */ +#define ELF_FINI_ARRAY ".fini_array" /* Array of destructors */ +#define ELF_GOT ".got" /* global offset table */ +#define ELF_HASH ".hash" /* symbol hash table */ +#define ELF_INIT ".init" /* initialization code */ +#define ELF_INIT_ARRAY ".init_array" /* Array of constuctors */ +#define ELF_INTERP ".interp" /* Pathname of program interpreter */ +#define ELF_LINE ".line" /* Symbolic line numnber information */ +#define ELF_NOTE ".note" /* Contains note section */ +#define ELF_PLT ".plt" /* Procedure linkage table */ +#define ELF_PREINIT_ARRAY ".preinit_array" /* Array of pre-constructors */ +#define ELF_REL_DATA ".rel.data" /* relocation data */ +#define ELF_REL_FINI ".rel.fini" /* relocation termination code */ +#define ELF_REL_INIT ".rel.init" /* relocation initialization code */ +#define ELF_REL_DYN ".rel.dyn" /* relocaltion dynamic link info */ +#define ELF_REL_RODATA ".rel.rodata" /* relocation read-only data */ +#define ELF_REL_TEXT ".rel.text" /* relocation code */ +#define ELF_RODATA ".rodata" /* read-only data */ +#define ELF_RODATA1 ".rodata1" /* read-only data */ +#define ELF_SHSTRTAB ".shstrtab" /* section header string table */ +#define ELF_STRTAB ".strtab" /* string table */ +#define ELF_SYMTAB ".symtab" /* symbol table */ +#define ELF_SYMTAB_SHNDX ".symtab_shndx"/* symbol table section index */ +#define ELF_TBSS ".tbss" /* thread local uninit data */ +#define ELF_TDATA ".tdata" /* thread local init data */ +#define ELF_TDATA1 ".tdata1" /* thread local init data */ +#define ELF_TEXT ".text" /* code */ + +/* Section Attribute Flags - sh_flags */ +#define SHF_WRITE 0x1 /* Writable */ +#define SHF_ALLOC 0x2 /* occupies memory */ +#define SHF_EXECINSTR 0x4 /* executable */ +#define SHF_MERGE 0x10 /* Might be merged */ +#define SHF_STRINGS 0x20 /* Contains NULL terminated strings */ +#define SHF_INFO_LINK 0x40 /* sh_info contains SHT index */ +#define SHF_LINK_ORDER 0x80 /* Preserve order after combining*/ +#define SHF_OS_NONCONFORMING 0x100 /* Non-standard OS specific handling */ +#define SHF_GROUP 0x200 /* Member of section group */ +#define SHF_TLS 0x400 /* Thread local storage */ +#define SHF_MASKOS 0x0ff00000 /* OS specific */ +#define SHF_MASKPROC 0xf0000000 /* reserved bits for processor */ + /* specific section attributes */ + +/* Section Group Flags */ +#define GRP_COMDAT 0x1 /* COMDAT group */ +#define GRP_MASKOS 0x0ff00000 /* Mask OS specific flags */ +#define GRP_MASKPROC 0xf0000000 /* Mask processor specific flags */ + +/* Symbol Table Entry */ +typedef struct elf32_sym { + Elf32_Word st_name; /* name - index into string table */ + Elf32_Addr st_value; /* symbol value */ + Elf32_Word st_size; /* symbol size */ + unsigned char st_info; /* type and binding */ + unsigned char st_other; /* 0 - no defined meaning */ + Elf32_Half st_shndx; /* section header index */ +} Elf32_Sym; + +/* Symbol table index */ +#define STN_UNDEF 0 /* undefined */ + +/* Extract symbol info - st_info */ +#define ELF32_ST_BIND(x) ((x) >> 4) +#define ELF32_ST_TYPE(x) (((unsigned int) x) & 0xf) +#define ELF32_ST_INFO(b,t) (((b) << 4) + ((t) & 0xf)) +#define ELF32_ST_VISIBILITY(x) ((x) & 0x3) + +/* Symbol Binding - ELF32_ST_BIND - st_info */ +#define STB_LOCAL 0 /* Local symbol */ +#define STB_GLOBAL 1 /* Global symbol */ +#define STB_WEAK 2 /* like global - lower precedence */ +#define STB_NUM 3 /* number of symbol bindings */ +#define STB_LOOS 10 /* reserved range for operating */ +#define STB_HIOS 12 /* system specific symbol bindings */ +#define STB_LOPROC 13 /* reserved range for processor */ +#define STB_HIPROC 15 /* specific symbol bindings */ + +/* Symbol type - ELF32_ST_TYPE - st_info */ +#define STT_NOTYPE 0 /* not specified */ +#define STT_OBJECT 1 /* data object */ +#define STT_FUNC 2 /* function */ +#define STT_SECTION 3 /* section */ +#define STT_FILE 4 /* file */ +#define STT_NUM 5 /* number of symbol types */ +#define STT_TLS 6 /* Thread local storage symbol */ +#define STT_LOOS 10 /* reserved range for operating */ +#define STT_HIOS 12 /* system specific symbol types */ +#define STT_LOPROC 13 /* reserved range for processor */ +#define STT_HIPROC 15 /* specific symbol types */ + +/* Symbol visibility - ELF32_ST_VISIBILITY - st_other */ +#define STV_DEFAULT 0 /* Normal visibility rules */ +#define STV_INTERNAL 1 /* Processor specific hidden class */ +#define STV_HIDDEN 2 /* Symbol unavailable in other mods */ +#define STV_PROTECTED 3 /* Not preemptible, not exported */ + + +/* Relocation entry with implicit addend */ +typedef struct +{ + Elf32_Addr r_offset; /* offset of relocation */ + Elf32_Word r_info; /* symbol table index and type */ +} Elf32_Rel; + +/* Relocation entry with explicit addend */ +typedef struct +{ + Elf32_Addr r_offset; /* offset of relocation */ + Elf32_Word r_info; /* symbol table index and type */ + Elf32_Sword r_addend; +} Elf32_Rela; + +/* Extract relocation info - r_info */ +#define ELF32_R_SYM(i) ((i) >> 8) +#define ELF32_R_TYPE(i) ((unsigned char) (i)) +#define ELF32_R_INFO(s,t) (((s) << 8) + (unsigned char)(t)) + +/* Program Header */ +typedef struct { + Elf32_Word p_type; /* segment type */ + Elf32_Off p_offset; /* segment offset */ + Elf32_Addr p_vaddr; /* virtual address of segment */ + Elf32_Addr p_paddr; /* physical address - ignored? */ + Elf32_Word p_filesz; /* number of bytes in file for seg. */ + Elf32_Word p_memsz; /* number of bytes in mem. for seg. */ + Elf32_Word p_flags; /* flags */ + Elf32_Word p_align; /* memory alignment */ +} Elf32_Phdr; + +/* Segment types - p_type */ +#define PT_NULL 0 /* unused */ +#define PT_LOAD 1 /* loadable segment */ +#define PT_DYNAMIC 2 /* dynamic linking section */ +#define PT_INTERP 3 /* the RTLD */ +#define PT_NOTE 4 /* auxiliary information */ +#define PT_SHLIB 5 /* reserved - purpose undefined */ +#define PT_PHDR 6 /* program header */ +#define PT_TLS 7 /* Thread local storage template */ +#define PT_NUM 8 /* Number of segment types */ +#define PT_LOOS 0x60000000 /* reserved range for operating */ +#define PT_HIOS 0x6fffffff /* system specific segment types */ +#define PT_LOPROC 0x70000000 /* reserved range for processor */ +#define PT_HIPROC 0x7fffffff /* specific segment types */ + +/* Segment flags - p_flags */ +#define PF_X 0x1 /* Executable */ +#define PF_W 0x2 /* Writable */ +#define PF_R 0x4 /* Readable */ +#define PF_MASKOS 0x0ff00000 /* OS specific segment flags */ +#define PF_MASKPROC 0xf0000000 /* reserved bits for processor */ + /* specific segment flags */ +/* Dynamic structure */ +typedef struct +{ + Elf32_Sword d_tag; /* controls meaning of d_val */ + union + { + Elf32_Word d_val; /* Multiple meanings - see d_tag */ + Elf32_Addr d_ptr; /* program virtual address */ + } d_un; +} Elf32_Dyn; + +extern Elf32_Dyn _DYNAMIC[]; + +/* Dynamic Array Tags - d_tag */ +#define DT_NULL 0 /* marks end of _DYNAMIC array */ +#define DT_NEEDED 1 /* string table offset of needed lib */ +#define DT_PLTRELSZ 2 /* size of relocation entries in PLT */ +#define DT_PLTGOT 3 /* address PLT/GOT */ +#define DT_HASH 4 /* address of symbol hash table */ +#define DT_STRTAB 5 /* address of string table */ +#define DT_SYMTAB 6 /* address of symbol table */ +#define DT_RELA 7 /* address of relocation table */ +#define DT_RELASZ 8 /* size of relocation table */ +#define DT_RELAENT 9 /* size of relocation entry */ +#define DT_STRSZ 10 /* size of string table */ +#define DT_SYMENT 11 /* size of symbol table entry */ +#define DT_INIT 12 /* address of initialization func. */ +#define DT_FINI 13 /* address of termination function */ +#define DT_SONAME 14 /* string table offset of shared obj */ +#define DT_RPATH 15 /* string table offset of library + search path */ +#define DT_SYMBOLIC 16 /* start sym search in shared obj. */ +#define DT_REL 17 /* address of rel. tbl. w addends */ +#define DT_RELSZ 18 /* size of DT_REL relocation table */ +#define DT_RELENT 19 /* size of DT_REL relocation entry */ +#define DT_PLTREL 20 /* PLT referenced relocation entry */ +#define DT_DEBUG 21 /* bugger */ +#define DT_TEXTREL 22 /* Allow rel. mod. to unwritable seg */ +#define DT_JMPREL 23 /* add. of PLT's relocation entries */ +#define DT_BIND_NOW 24 /* Process relocations of object */ +#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ +#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ +#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ +#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ +#define DT_RUNPATH 29 /* Library search path */ +#define DT_FLAGS 30 /* Flags for the object being loaded */ +#define DT_ENCODING 32 /* Start of encoded range */ +#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ +#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ +#define DT_NUM 34 /* Number used. */ +#define DT_LOOS 0x60000000 /* reserved range for OS */ +#define DT_HIOS 0x6fffffff /* specific dynamic array tags */ +#define DT_LOPROC 0x70000000 /* reserved range for processor */ +#define DT_HIPROC 0x7fffffff /* specific dynamic array tags */ + +/* Dynamic Tag Flags - d_un.d_val */ +#define DF_ORIGIN 0x01 /* Object may use DF_ORIGIN */ +#define DF_SYMBOLIC 0x02 /* Symbol resolutions starts here */ +#define DF_TEXTREL 0x04 /* Object contains text relocations */ +#define DF_BIND_NOW 0x08 /* No lazy binding for this object */ +#define DF_STATIC_TLS 0x10 /* Static thread local storage */ + +/* Standard ELF hashing function */ +unsigned long elf_hash(const unsigned char *name); + +#define ELF_TARG_VER 1 /* The ver for which this code is intended */ + +/* + * XXX - PowerPC defines really don't belong in here, + * but we'll put them in for simplicity. + */ + +/* Values for Elf32/64_Ehdr.e_flags. */ +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ + +/* Cygnus local bits below */ +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib + flag */ + +/* PowerPC relocations defined by the ABIs */ +#define R_PPC_NONE 0 +#define R_PPC_ADDR32 1 /* 32bit absolute address */ +#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ +#define R_PPC_ADDR16 3 /* 16bit absolute address */ +#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ +#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ +#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ +#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ +#define R_PPC_ADDR14_BRTAKEN 8 +#define R_PPC_ADDR14_BRNTAKEN 9 +#define R_PPC_REL24 10 /* PC relative 26 bit */ +#define R_PPC_REL14 11 /* PC relative 16 bit */ +#define R_PPC_REL14_BRTAKEN 12 +#define R_PPC_REL14_BRNTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLTREL24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_UADDR32 24 +#define R_PPC_UADDR16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 +/* Keep this the last entry. */ +#define R_PPC_NUM 37 + +/* The remaining relocs are from the Embedded ELF ABI, and are not + in the SVR4 ELF ABI. */ +#define R_PPC_EMB_NADDR32 101 +#define R_PPC_EMB_NADDR16 102 +#define R_PPC_EMB_NADDR16_LO 103 +#define R_PPC_EMB_NADDR16_HI 104 +#define R_PPC_EMB_NADDR16_HA 105 +#define R_PPC_EMB_SDAI16 106 +#define R_PPC_EMB_SDA2I16 107 +#define R_PPC_EMB_SDA2REL 108 +#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ +#define R_PPC_EMB_MRKREF 110 +#define R_PPC_EMB_RELSEC16 111 +#define R_PPC_EMB_RELST_LO 112 +#define R_PPC_EMB_RELST_HI 113 +#define R_PPC_EMB_RELST_HA 114 +#define R_PPC_EMB_BIT_FLD 115 +#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ + +/* Diab tool relocations. */ +#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ +#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ +#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ +#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ +#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ +#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ + +/* This is a phony reloc to handle any old fashioned TOC16 references + that may still be in object files. */ +#define R_PPC_TOC16 255 + +#endif /* _ELF_H */ diff --git a/include/environment.h b/include/environment.h new file mode 100644 index 0000000..bb10964 --- /dev/null +++ b/include/environment.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ENVIRONMENT_H_ +#define _ENVIRONMENT_H_ 1 + +/************************************************************************** + * + * The "environment" is stored as a list of '\0' terminated + * "name=value" strings. The end of the list is marked by a double + * '\0'. New entries are always added at the end. Deleting an entry + * shifts the remaining entries to the front. Replacing an entry is a + * combination of deleting the old value and adding the new one. + * + * The environment is preceeded by a 32 bit CRC over the data part. + * + ************************************************************************** + */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_OFFSET +# define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +# endif +# if !defined(CFG_ENV_ADDR_REDUND) && defined(CFG_ENV_OFFSET_REDUND) +# define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + CFG_ENV_OFFSET_REDUND) +# endif +# if defined(CFG_ENV_SECT_SIZE) || defined(CFG_ENV_SIZE) +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# else +# error "Both CFG_ENV_SECT_SIZE and CFG_ENV_SIZE undefined" +# endif +# if defined(CFG_ENV_ADDR_REDUND) && !defined(CFG_ENV_SIZE_REDUND) +# define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE +# endif +# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \ + (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +# define ENV_IS_EMBEDDED 1 +# endif +# if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND) +# define CFG_REDUNDAND_ENVIRONMENT 1 +# endif +#endif /* CFG_ENV_IS_IN_FLASH */ + + +#ifdef CFG_REDUNDAND_ENVIRONMENT +# define ENV_HEADER_SIZE (sizeof(unsigned long) + 1) +#else +# define ENV_HEADER_SIZE (sizeof(unsigned long)) +#endif + + +#define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE) + +typedef struct environment_s { + unsigned long crc; /* CRC32 over data bytes */ +#ifdef CFG_REDUNDAND_ENVIRONMENT + unsigned char flags; /* active/obsolete flags */ +#endif + unsigned char data[ENV_SIZE]; /* Environment data */ +} env_t; + +#endif /* _ENVIRONMENT_H_ */ diff --git a/include/exports.h b/include/exports.h new file mode 100644 index 0000000..0eaf66e --- /dev/null +++ b/include/exports.h @@ -0,0 +1,46 @@ +#ifndef __EXPORTS_H__ +#define __EXPORTS_H__ + +#ifndef __ASSEMBLY__ + +#include + +/* These are declarations of exported functions available in C code */ +unsigned long get_version(void); +int getc(void); +int tstc(void); +void putc(const char); +void puts(const char*); +void printf(const char* fmt, ...); +void install_hdlr(int, interrupt_handler_t*, void*); +void free_hdlr(int); +void *malloc(size_t); +void free(void*); +void udelay(unsigned long); +unsigned long get_timer(unsigned long); +void vprintf(const char *, va_list); +void do_reset (void); +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +int i2c_write (uchar, uint, int , uchar* , int); +int i2c_read (uchar, uint, int , uchar* , int); +#endif /* CFG_CMD_I2C */ + +void app_startup(char **); + +#endif /* ifndef __ASSEMBLY__ */ + +enum { +#define EXPORT_FUNC(x) XF_ ## x , +#include <_exports.h> +#undef EXPORT_FUNC + + XF_MAX +}; + +#define XF_VERSION 2 + +#if defined(CONFIG_I386) +extern gd_t *global_data; +#endif + +#endif /* __EXPORTS_H__ */ diff --git a/include/ext2fs.h b/include/ext2fs.h new file mode 100644 index 0000000..de935b0 --- /dev/null +++ b/include/ext2fs.h @@ -0,0 +1,81 @@ +/* + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2000, 2001 Free Software Foundation, Inc. + * + * (C) Copyright 2003 Sysgo Real-Time Solutions, AG + * Pavel Bartusek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* An implementation for the Ext2FS filesystem ported from GRUB. + * Some parts of this code (mainly the structures and defines) are + * from the original ext2 fs code, as found in the linux kernel. + */ + + +#define SECTOR_SIZE 0x200 +#define SECTOR_BITS 9 + +/* Error codes */ +typedef enum +{ + ERR_NONE = 0, + ERR_BAD_FILENAME, + ERR_BAD_FILETYPE, + ERR_BAD_GZIP_DATA, + ERR_BAD_GZIP_HEADER, + ERR_BAD_PART_TABLE, + ERR_BAD_VERSION, + ERR_BELOW_1MB, + ERR_BOOT_COMMAND, + ERR_BOOT_FAILURE, + ERR_BOOT_FEATURES, + ERR_DEV_FORMAT, + ERR_DEV_VALUES, + ERR_EXEC_FORMAT, + ERR_FILELENGTH, + ERR_FILE_NOT_FOUND, + ERR_FSYS_CORRUPT, + ERR_FSYS_MOUNT, + ERR_GEOM, + ERR_NEED_LX_KERNEL, + ERR_NEED_MB_KERNEL, + ERR_NO_DISK, + ERR_NO_PART, + ERR_NUMBER_PARSING, + ERR_OUTSIDE_PART, + ERR_READ, + ERR_SYMLINK_LOOP, + ERR_UNRECOGNIZED, + ERR_WONT_FIT, + ERR_WRITE, + ERR_BAD_ARGUMENT, + ERR_UNALIGNED, + ERR_PRIVILEGED, + ERR_DEV_NEED_INIT, + ERR_NO_DISK_SPACE, + ERR_NUMBER_OVERFLOW, + + MAX_ERR_NUM +} ext2fs_error_t; + + +extern int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part); +extern int ext2fs_ls (char *dirname); +extern int ext2fs_open (char *filename); +extern int ext2fs_read (char *buf, unsigned len); +extern int ext2fs_mount (unsigned part_length); +extern int ext2fs_close(void); diff --git a/include/fat.h b/include/fat.h new file mode 100644 index 0000000..0645458 --- /dev/null +++ b/include/fat.h @@ -0,0 +1,215 @@ +/* + * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg + * + * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 + * 2003-03-10 - kharris@nexus-tech.net - ported to u-boot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _FAT_H_ +#define _FAT_H_ + +#include + +#define CONFIG_SUPPORT_VFAT + +#define SECTOR_SIZE FS_BLOCK_SIZE + +#define FS_BLOCK_SIZE 512 + +#if FS_BLOCK_SIZE != SECTOR_SIZE +#error FS_BLOCK_SIZE != SECTOR_SIZE - This code needs to be fixed! +#endif + +#define MAX_CLUSTSIZE 65536 +#define DIRENTSPERBLOCK (FS_BLOCK_SIZE/sizeof(dir_entry)) +#define DIRENTSPERCLUST ((mydata->clust_size*SECTOR_SIZE)/sizeof(dir_entry)) + +#define FATBUFBLOCKS 6 +#define FATBUFSIZE (FS_BLOCK_SIZE*FATBUFBLOCKS) +#define FAT12BUFSIZE ((FATBUFSIZE*2)/3) +#define FAT16BUFSIZE (FATBUFSIZE/2) +#define FAT32BUFSIZE (FATBUFSIZE/4) + + +/* Filesystem identifiers */ +#define FAT12_SIGN "FAT12 " +#define FAT16_SIGN "FAT16 " +#define FAT32_SIGN "FAT32 " +#define SIGNLEN 8 + +/* File attributes */ +#define ATTR_RO 1 +#define ATTR_HIDDEN 2 +#define ATTR_SYS 4 +#define ATTR_VOLUME 8 +#define ATTR_DIR 16 +#define ATTR_ARCH 32 + +#define ATTR_VFAT (ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME) + +#define DELETED_FLAG ((char)0xe5) /* Marks deleted files when in name[0] */ +#define aRING 0x05 /* Used to represent 'ċ' in name[0] */ + +/* Indicates that the entry is the last long entry in a set of long + * dir entries + */ +#define LAST_LONG_ENTRY_MASK 0x40 + +/* Flags telling whether we should read a file or list a directory */ +#define LS_NO 0 +#define LS_YES 1 +#define LS_DIR 1 +#define LS_ROOT 2 + +#ifdef DEBUG +#define FAT_DPRINT(args...) printf(args) +#else +#define FAT_DPRINT(args...) +#endif +#define FAT_ERROR(arg) printf(arg) + +#define ISDIRDELIM(c) ((c) == '/' || (c) == '\\') + +#define FSTYPE_NONE (-1) + +#if defined(__linux__) && defined(__KERNEL__) +#define FAT2CPU16 le16_to_cpu +#define FAT2CPU32 le32_to_cpu +#else +#if __LITTLE_ENDIAN +#define FAT2CPU16(x) (x) +#define FAT2CPU32(x) (x) +#else +#define FAT2CPU16(x) ((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8)) +#define FAT2CPU32(x) ((((x) & 0x000000ff) << 24) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0xff000000) >> 24)) +#endif +#endif + +#define TOLOWER(c) if((c) >= 'A' && (c) <= 'Z'){(c)+=('a' - 'A');} +#define START(dent) (FAT2CPU16((dent)->start) \ + + (mydata->fatsize != 32 ? 0 : \ + (FAT2CPU16((dent)->starthi) << 16))) + + +typedef struct boot_sector { + __u8 ignored[3]; /* Bootstrap code */ + char system_id[8]; /* Name of fs */ + __u8 sector_size[2]; /* Bytes/sector */ + __u8 cluster_size; /* Sectors/cluster */ + __u16 reserved; /* Number of reserved sectors */ + __u8 fats; /* Number of FATs */ + __u8 dir_entries[2]; /* Number of root directory entries */ + __u8 sectors[2]; /* Number of sectors */ + __u8 media; /* Media code */ + __u16 fat_length; /* Sectors/FAT */ + __u16 secs_track; /* Sectors/track */ + __u16 heads; /* Number of heads */ + __u32 hidden; /* Number of hidden sectors */ + __u32 total_sect; /* Number of sectors (if sectors == 0) */ + + /* FAT32 only */ + __u32 fat32_length; /* Sectors/FAT */ + __u16 flags; /* Bit 8: fat mirroring, low 4: active fat */ + __u8 version[2]; /* Filesystem version */ + __u32 root_cluster; /* First cluster in root directory */ + __u16 info_sector; /* Filesystem info sector */ + __u16 backup_boot; /* Backup boot sector */ + __u16 reserved2[6]; /* Unused */ +} boot_sector; + +typedef struct volume_info +{ + __u8 drive_number; /* BIOS drive number */ + __u8 reserved; /* Unused */ + __u8 ext_boot_sign; /* 0x29 if fields below exist (DOS 3.3+) */ + __u8 volume_id[4]; /* Volume ID number */ + char volume_label[11]; /* Volume label */ + char fs_type[8]; /* Typically FAT12, FAT16, or FAT32 */ + /* Boot code comes next, all but 2 bytes to fill up sector */ + /* Boot sign comes last, 2 bytes */ +} volume_info; + +typedef struct dir_entry { + char name[8],ext[3]; /* Name and extension */ + __u8 attr; /* Attribute bits */ + __u8 lcase; /* Case for base and extension */ + __u8 ctime_ms; /* Creation time, milliseconds */ + __u16 ctime; /* Creation time */ + __u16 cdate; /* Creation date */ + __u16 adate; /* Last access date */ + __u16 starthi; /* High 16 bits of cluster in FAT32 */ + __u16 time,date,start;/* Time, date and first cluster */ + __u32 size; /* File size in bytes */ +} dir_entry; + +typedef struct dir_slot { + __u8 id; /* Sequence number for slot */ + __u8 name0_4[10]; /* First 5 characters in name */ + __u8 attr; /* Attribute byte */ + __u8 reserved; /* Unused */ + __u8 alias_checksum;/* Checksum for 8.3 alias */ + __u8 name5_10[12]; /* 6 more characters in name */ + __u16 start; /* Unused */ + __u8 name11_12[4]; /* Last 2 characters in name */ +} dir_slot; + +/* Private filesystem parameters */ +typedef struct { + int fatsize; /* Size of FAT in bits */ + __u16 fatlength; /* Length of FAT in sectors */ + __u16 fat_sect; /* Starting sector of the FAT */ + __u16 rootdir_sect; /* Start sector of root directory */ + __u16 clust_size; /* Size of clusters in sectors */ + short data_begin; /* The sector of the first cluster, can be negative */ + __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ + int fatbufnum; /* Used by get_fatent, init to -1 */ +} fsdata; + +typedef int (file_detectfs_func)(void); +typedef int (file_ls_func)(const char *dir); +typedef long (file_read_func)(const char *filename, void *buffer, + unsigned long maxsize); + +struct filesystem { + file_detectfs_func *detect; + file_ls_func *ls; + file_read_func *read; + const char name[12]; +}; + +/* FAT tables */ +file_detectfs_func file_fat_detectfs; +file_ls_func file_fat_ls; +file_read_func file_fat_read; + +/* Currently this doesn't check if the dir exists or is valid... */ +int file_cd(const char *path); +int file_fat_detectfs(void); +int file_fat_ls(const char *dir); +long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); +const char *file_getfsname(int idx); +int fat_register_device(block_dev_desc_t *dev_desc, int part_no); + +#endif /* _FAT_H_ */ diff --git a/include/fdc.h b/include/fdc.h new file mode 100644 index 0000000..b66f202 --- /dev/null +++ b/include/fdc.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FDC_H_ +#define _FDC_H_ + +/* Functions prototype */ +int fdc_fdos_init (int drive); +int fdc_fdos_seek (int where); +int fdc_fdos_read (void *buffer, int len); + +int dos_open(char *name); +int dos_read (ulong addr); +int dos_dir (void); + +#endif diff --git a/include/flash.h b/include/flash.h new file mode 100644 index 0000000..decb046 --- /dev/null +++ b/include/flash.h @@ -0,0 +1,448 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FLASH_H_ +#define _FLASH_H_ + +#ifndef CFG_NO_FLASH +/*----------------------------------------------------------------------- + * FLASH Info: contains chip specific data, per FLASH bank + */ + +typedef struct { + ulong size; /* total bank size in bytes */ + ushort sector_count; /* number of erase units */ + ulong flash_id; /* combined device & manufacturer code */ + ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */ + uchar protect[CFG_MAX_FLASH_SECT]; /* sector protection status */ +#ifdef CFG_FLASH_CFI + uchar portwidth; /* the width of the port */ + uchar chipwidth; /* the width of the chip */ + ushort buffer_size; /* # of bytes in write buffer */ + ulong erase_blk_tout; /* maximum block erase timeout */ + ulong write_tout; /* maximum write timeout */ + ulong buffer_write_tout; /* maximum buffer write timeout */ + ushort vendor; /* the primary vendor id */ + ushort cmd_reset; /* Vendor specific reset command */ + ushort interface; /* used for x8/x16 adjustments */ +#endif +} flash_info_t; + +/* + * Values for the width of the port + */ +#define FLASH_CFI_8BIT 0x01 +#define FLASH_CFI_16BIT 0x02 +#define FLASH_CFI_32BIT 0x04 +#define FLASH_CFI_64BIT 0x08 +/* + * Values for the width of the chip + */ +#define FLASH_CFI_BY8 0x01 +#define FLASH_CFI_BY16 0x02 +#define FLASH_CFI_BY32 0x04 +#define FLASH_CFI_BY64 0x08 +/* convert between bit value and numeric value */ +#define CFI_FLASH_SHIFT_WIDTH 3 +/* + * Values for the flash device interface + */ +#define FLASH_CFI_X8 0x00 +#define FLASH_CFI_X16 0x01 +#define FLASH_CFI_X8X16 0x02 + +/* convert between bit value and numeric value */ +#define CFI_FLASH_SHIFT_WIDTH 3 +/* Prototypes */ + +extern unsigned long flash_init (void); +extern void flash_print_info (flash_info_t *); +extern int flash_erase (flash_info_t *, int, int); +extern int flash_sect_erase (ulong addr_first, ulong addr_last); +extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last); + +/* common/flash.c */ +extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info); +extern int flash_write (char *, ulong, ulong); +extern flash_info_t *addr2info (ulong); +extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); + +/* board/?/flash.c */ +#if defined(CFG_FLASH_PROTECTION) +extern int flash_real_protect(flash_info_t *info, long sector, int prot); +extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len); +extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len); +#endif /* CFG_FLASH_PROTECTION */ + +/*----------------------------------------------------------------------- + * return codes from flash_write(): + */ +#define ERR_OK 0 +#define ERR_TIMOUT 1 +#define ERR_NOT_ERASED 2 +#define ERR_PROTECTED 4 +#define ERR_INVAL 8 +#define ERR_ALIGN 16 +#define ERR_UNKNOWN_FLASH_VENDOR 32 +#define ERR_UNKNOWN_FLASH_TYPE 64 +#define ERR_PROG_ERROR 128 + +/*----------------------------------------------------------------------- + * Protection Flags for flash_protect(): + */ +#define FLAG_PROTECT_SET 0x01 +#define FLAG_PROTECT_CLEAR 0x02 + +/*----------------------------------------------------------------------- + * Device IDs + */ + +#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */ +#define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ +#define ATM_MANUFACT 0x001F001F /* ATMEL */ +#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */ +#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */ +#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */ +#define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */ +#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */ +#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */ +#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ +#define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ +#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ + + /* Micron Technologies (INTEL compat.) */ +#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ +#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */ + +#define AMD_ID_LV040B 0x4F /* 29LV040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define AMD_ID_F033C 0xA3 /* 29LV033C ID */ + /* 32 Mbit, 4Mbits x 8, */ + /* 64 64K x 8 uniform sectors */ +#define AMD_ID_F065D 0x93 /* 29LV065D ID */ + /* 64 Mbit, 8Mbits x 8, */ + /* 126 64K x 8 uniform sectors */ +#define ATM_ID_LV040 0x13 /* 29LV040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define AMD_ID_F040B 0xA4 /* 29F040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define STM_ID_M29W040B 0xE3 /* M29W040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */ + /* 8 Mbit, 512K x 16, */ + /* 8 64K x 16 uniform sectors */ +#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */ +#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */ +#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */ +#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */ +#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */ + +#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */ + +#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */ +#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */ + +#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */ +#define AMD_ID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */ + +#define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */ +#define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */ + +#define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */ +#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */ + +#define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */ +#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */ + +#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */ +#define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */ +#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */ +#define MX_ID_LV320B 0x22A822A8 /* 29LV320B by Macronix, AMD compatible */ + +#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */ +#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */ +#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */ +#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */ +#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */ +#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */ + +#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/ +#define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */ +#define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */ +#define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */ +#define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */ +#define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */ +#define AMD_ID_LV640MT_2 0x22102210 /* 2nd ID word for AM29LV640MT at 0x38 */ +#define AMD_ID_LV640MT_3 0x22012201 /* 3rd ID word for AM29LV640MT at 0x3c */ +#define AMD_ID_LV640MB_2 0x22102210 /* 2nd ID word for AM29LV640MB at 0x38 */ +#define AMD_ID_LV640MB_3 0x22002200 /* 3rd ID word for AM29LV640MB at 0x3c */ +#define AMD_ID_LV128U_2 0x22122212 /* 2nd ID word for AM29LV128M at 0x38 */ +#define AMD_ID_LV128U_3 0x22002200 /* 3rd ID word for AM29LV128M at 0x3c */ +#define AMD_ID_LV256U_2 0x22122212 /* 2nd ID word for AM29LV256M at 0x38 */ +#define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */ +#define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */ +#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */ +#define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */ +#define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */ + +#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */ +#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */ + +#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */ +#define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */ + +#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */ +#define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */ +#define ATM_ID_BV6416 0x000000D6 /* 49BV6416 ID */ + +#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */ +#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */ +#define FUJI_ID_29LV650UE 0x22d722d7 /* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */ + +#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */ +#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */ +#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */ +#define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */ +#define SST_ID_xF1601 0x234B234B /* 39xF1601 ID (16M = 1M x 16 ) */ +#define SST_ID_xF1602 0x234A234A /* 39xF1602 ID (16M = 1M x 16 ) */ +#define SST_ID_xF3201 0x235B235B /* 39xF3201 ID (32M = 2M x 16 ) */ +#define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */ +#define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */ +#define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */ +#define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */ + +#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */ + /* 8 64K x 8 uniform sectors */ + +#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */ +#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */ +#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */ +#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */ + +#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ +#define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */ +#define INTEL_ID_28F800B3B 0x88938893 /* 8M = 512K x 16 bottom boot sector */ +#define INTEL_ID_28F160B3T 0x88908890 /* 16M = 1M x 16 top boot sector */ +#define INTEL_ID_28F160B3B 0x88918891 /* 16M = 1M x 16 bottom boot sector */ +#define INTEL_ID_28F320B3T 0x88968896 /* 32M = 2M x 16 top boot sector */ +#define INTEL_ID_28F320B3B 0x88978897 /* 32M = 2M x 16 bottom boot sector */ +#define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */ +#define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */ +#define INTEL_ID_28F160F3B 0x88F488F4 /* 16M = 1M x 16 bottom boot sector */ + +#define INTEL_ID_28F800C3T 0x88C088C0 /* 8M = 512K x 16 top boot sector */ +#define INTEL_ID_28F800C3B 0x88C188C1 /* 8M = 512K x 16 bottom boot sector */ +#define INTEL_ID_28F160C3T 0x88C288C2 /* 16M = 1M x 16 top boot sector */ +#define INTEL_ID_28F160C3B 0x88C388C3 /* 16M = 1M x 16 bottom boot sector */ +#define INTEL_ID_28F320C3T 0x88C488C4 /* 32M = 2M x 16 top boot sector */ +#define INTEL_ID_28F320C3B 0x88C588C5 /* 32M = 2M x 16 bottom boot sector */ +#define INTEL_ID_28F640C3T 0x88CC88CC /* 64M = 4M x 16 top boot sector */ +#define INTEL_ID_28F640C3B 0x88CD88CD /* 64M = 4M x 16 bottom boot sector */ + +#define INTEL_ID_28F128J3 0x89188918 /* 16M = 8M x 16 x 128 */ +#define INTEL_ID_28F320J5 0x00140014 /* 32M = 128K x 32 */ +#define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */ +#define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */ +#define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */ +#define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */ +#define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */ +#define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */ +#define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */ + +#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ +#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */ + +/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */ +#define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */ +#define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */ +#define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */ + /* LH28F008SCR-L85 1Mx8, 16 64k blocks */ + +#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ +#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ + +/*----------------------------------------------------------------------- + * Internal FLASH identification codes + * + * Be careful when adding new type! Odd numbers are "bottom boot sector" types! + */ + +#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */ + /* Bright Micro BM29F040 */ + /* Fujitsu MBM29F040A */ + /* STM M29W040B */ + /* SGS Thomson M29F040B */ + /* 8 64K x 8 uniform sectors */ +#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */ +#define FLASH_AM400B 0x0003 +#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */ +#define FLASH_AM800B 0x0005 +#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */ +#define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */ +#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */ +#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */ +#define FLASH_AM160B 0x0007 +#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */ +#define FLASH_AM320B 0x0009 + +#define FLASH_AM080 0x000A /* AMD Am29F080B */ + /* 16 64K x 8 uniform sectors */ + +#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */ +#define FLASH_AMDL322B 0x0011 +#define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */ +#define FLASH_AMDL323B 0x0013 +#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */ +#define FLASH_AMDL324B 0x0015 + +#define FLASH_AMDLV033C 0x0018 +#define FLASH_AMDLV065D 0x001A + +#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */ +#define FLASH_AMD016 0x0018 /* AMD AM29F016D */ +#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/ +#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */ + +#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */ +#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */ +#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */ +#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */ + +#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */ +#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */ +#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/ +#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/ +#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ +#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/ + +#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ +#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ + +#define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */ +#define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */ +#define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */ +#define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */ +#define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */ +#define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */ +#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */ +#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */ + +#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ +#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */ +#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */ +#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */ +#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */ +#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */ +#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */ +#define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */ +#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */ +#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */ +#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */ +#define FLASH_AM065D 0x0093 + +#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */ + +#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */ +#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */ +#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */ +#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */ +#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */ +#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */ +#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */ +#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */ +#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */ + +#define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */ +#define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */ +#define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */ + +#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */ +#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */ +#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */ +#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */ +#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */ +#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */ +#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */ +#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */ +#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */ +#define FLASH_AMDL163B 0x00B3 +#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */ +#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */ +#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */ + +#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */ +#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */ +#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */ + +#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ +#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ +#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ + +#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ + + +/* manufacturer offsets + */ +#define FLASH_MAN_AMD 0x00000000 /* AMD */ +#define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */ +#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */ +#define FLASH_MAN_MX 0x00030000 /* MXIC */ +#define FLASH_MAN_STM 0x00040000 +#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */ +#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */ +#define FLASH_MAN_SST 0x00100000 +#define FLASH_MAN_INTEL 0x00300000 +#define FLASH_MAN_MT 0x00400000 +#define FLASH_MAN_SHARP 0x00500000 +#define FLASH_MAN_ATM 0x00600000 + + +#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ +#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */ + +#define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */ + /* with AMD, Fujitsu and SST */ + /* (JEDEC standard commands ?) */ + +#define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */ + +/*----------------------------------------------------------------------- + * Timeout constants: + * + * We can't find any specifications for maximum chip erase times, + * so these values are guestimates. + */ +#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */ +#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */ + +#endif /* !CFG_NO_FLASH */ + +#endif /* _FLASH_H_ */ diff --git a/include/fpga.h b/include/fpga.h new file mode 100644 index 0000000..a038aa1 --- /dev/null +++ b/include/fpga.h @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include /* for ulong typedef */ + +#ifndef _FPGA_H_ +#define _FPGA_H_ + +#ifndef CONFIG_MAX_FPGA_DEVICES +#define CONFIG_MAX_FPGA_DEVICES 5 +#endif + +/* these probably belong somewhere else */ +#ifndef FALSE +#define FALSE (0) +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +/* CONFIG_FPGA bit assignments */ +#define CFG_FPGA_MAN(x) (x) +#define CFG_FPGA_DEV(x) ((x) << 8 ) +#define CFG_FPGA_IF(x) ((x) << 16 ) + +/* FPGA Manufacturer bits in CONFIG_FPGA */ +#define CFG_FPGA_XILINX CFG_FPGA_MAN( 0x1 ) +#define CFG_FPGA_ALTERA CFG_FPGA_MAN( 0x2 ) + + +/* fpga_xxxx function return value definitions */ +#define FPGA_SUCCESS 0 +#define FPGA_FAIL -1 + +/* device numbers must be non-negative */ +#define FPGA_INVALID_DEVICE -1 + +/* root data type defintions */ +typedef enum { /* typedef fpga_type */ + fpga_min_type, /* range check value */ + fpga_xilinx, /* Xilinx Family) */ + fpga_altera, /* unimplemented */ + fpga_undefined /* invalid range check value */ +} fpga_type; /* end, typedef fpga_type */ + +typedef struct { /* typedef fpga_desc */ + fpga_type devtype; /* switch value to select sub-functions */ + void * devdesc; /* real device descriptor */ +} fpga_desc; /* end, typedef fpga_desc */ + + +/* root function definitions */ +extern void fpga_init( ulong reloc_off ); +extern int fpga_add( fpga_type devtype, void *desc ); +extern int fpga_count( void ); +extern int fpga_load( int devnum, void *buf, size_t bsize ); +extern int fpga_dump( int devnum, void *buf, size_t bsize ); +extern int fpga_info( int devnum ); + +#endif /* _FPGA_H_ */ diff --git a/include/ft_build.h b/include/ft_build.h new file mode 100644 index 0000000..9104b1a --- /dev/null +++ b/include/ft_build.h @@ -0,0 +1,66 @@ +/* + * OF Flat tree builder + * + */ + +#ifndef FT_BUILD_H +#define FT_BUILD_H + +#include +#include + +/* Definitions used by the flattened device tree */ +#define OF_DT_HEADER 0xd00dfeed /* marker */ +#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */ +#define OF_DT_END_NODE 0x2 /* End node */ +#define OF_DT_PROP 0x3 /* Property: name off, size, + * content */ +#define OF_DT_NOP 0x4 /* nop */ +#define OF_DT_END 0x9 + +#define OF_DT_VERSION 0x10 + +struct boot_param_header { + u32 magic; /* magic word OF_DT_HEADER */ + u32 totalsize; /* total size of DT block */ + u32 off_dt_struct; /* offset to structure */ + u32 off_dt_strings; /* offset to strings */ + u32 off_mem_rsvmap; /* offset to memory reserve map */ + u32 version; /* format version */ + u32 last_comp_version; /* last compatible version */ + /* version 2 fields below */ + u32 boot_cpuid_phys; /* Physical CPU id we're booting on */ + /* version 3 fields below */ + u32 dt_strings_size; /* size of the DT strings block */ +}; + +struct ft_cxt { + struct boot_param_header *bph; + int max_size; /* maximum size of tree */ + int overflow; /* set when this happens */ + u8 *p, *pstr, *pres; /* running pointers */ + u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */ + u8 *p_anchor; /* start of constructed area */ + int struct_size, strings_size, res_size; +}; + +void ft_begin_node(struct ft_cxt *cxt, const char *name); +void ft_end_node(struct ft_cxt *cxt); + +void ft_begin_tree(struct ft_cxt *cxt); +int ft_end_tree(struct ft_cxt *cxt); + +void ft_nop(struct ft_cxt *cxt); +void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz); +void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str); +void ft_prop_int(struct ft_cxt *cxt, const char *name, int val); +void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); +void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); + +void ft_setup(void *blob, int size, bd_t * bd); + +void ft_dump_blob(const void *bphp); +void ft_merge_blob(struct ft_cxt *cxt, void *blob); +void *ft_get_prop(void *bphp, const char *propname, int *szp); + +#endif diff --git a/include/galileo/core.h b/include/galileo/core.h new file mode 100644 index 0000000..0735d07 --- /dev/null +++ b/include/galileo/core.h @@ -0,0 +1,218 @@ +/* Core.h - Basic core logic functions and definitions */ + +/* Copyright Galileo Technology. */ + +/* +DESCRIPTION +This header file contains simple read/write macros for addressing +the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address +space). The macros take care of Big/Little endian conversions. +*/ + +#ifndef __INCcoreh +#define __INCcoreh + +/* includes */ +#include "gt64260R.h" + +extern unsigned int INTERNAL_REG_BASE_ADDR; + +/* + * GT-6426x variants + */ +#define GT_64260 0 /* includes both 64260A and 64260B */ +#define GT_64261 1 + +#if (CFG_GT_6426x == GT_64260) +#ifdef CONFIG_ETHER_PORT_MII +#define GAL_ETH_DEVS 2 +#else +#define GAL_ETH_DEVS 3 +#endif +#elif (CFG_GT_6426x == GT_64261) +#define GAL_ETH_DEVS 2 +#else +#define GAL_ETH_DEVS 3 /* default to a 64260 */ +#endif + +/****************************************/ +/* GENERAL Definitions */ +/****************************************/ + +#define NO_BIT 0x00000000 +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#define _1K 0x00000400 +#define _2K 0x00000800 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _3M 0x00300000 +#define _4M 0x00400000 +#define _5M 0x00500000 +#define _6M 0x00600000 +#define _7M 0x00700000 +#define _8M 0x00800000 +#define _9M 0x00900000 +#define _10M 0x00a00000 +#define _11M 0x00b00000 +#define _12M 0x00c00000 +#define _13M 0x00d00000 +#define _14M 0x00e00000 +#define _15M 0x00f00000 +#define _16M 0x01000000 + +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + +typedef enum _bool{false,true} bool; + +/* Little to Big endian conversion macros */ + +#ifdef LE /* Little Endian */ +#define SHORT_SWAP(X) (X) +#define WORD_SWAP(X) (X) +#define LONG_SWAP(X) ((l64)(X)) + +#else /* Big Endian */ +#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) + +#define WORD_SWAP(X) (((X)&0xff)<<24)+ \ + (((X)&0xff00)<<8)+ \ + (((X)&0xff0000)>>8)+ \ + (((X)&0xff000000)>>24) + +#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ + (((X)&0xff00ULL)<<40)+ \ + (((X)&0xff0000ULL)<<24)+ \ + (((X)&0xff000000ULL)<<8)+ \ + (((X)&0xff00000000ULL)>>8)+ \ + (((X)&0xff0000000000ULL)>>24)+ \ + (((X)&0xff000000000000ULL)>>40)+ \ + (((X)&0xff00000000000000ULL)>>56)) + +#endif + +#ifndef NULL +#define NULL 0 +#endif + +/* Those two definitions were defined to be compatible with MIPS */ +#define NONE_CACHEABLE 0x00000000 +#define CACHEABLE 0x00000000 + +/* 750 cache line */ +#define CACHE_LINE_SIZE 32 +#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1) +#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS) + +/* Read/Write to/from GT`s internal registers */ +#define GT_REG_READ(offset, pData) \ +*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ + INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ +*pData = WORD_SWAP(*pData) + +#define GTREGREAD(offset) \ + (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ + INTERNAL_REG_BASE_ADDR | (offset))) )) + +#define GT_REG_WRITE(offset, data) \ +*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \ + WORD_SWAP(data) + +/* Write 32/16/8 bit */ +#define WRITE_CHAR(address, data) \ + *((unsigned char *)(address)) = data +#define WRITE_SHORT(address, data) \ + *((unsigned short *)(address)) = data +#define WRITE_WORD(address, data) \ + *((unsigned int *)(address)) = data + +/* Read 32/16/8 bits - returns data in variable. */ +#define READ_CHAR(address, pData) \ + *pData = *((volatile unsigned char *)(address)) + +#define READ_SHORT(address, pData) \ + *pData = *((volatile unsigned short *)(address)) + +#define READ_WORD(address, pData) \ + *pData = *((volatile unsigned int *)(address)) + +/* Read 32/16/8 bit - returns data direct. */ +#define READCHAR(address) \ + *((volatile unsigned char *)((address) | NONE_CACHEABLE)) + +#define READSHORT(address) \ + *((volatile unsigned short *)((address) | NONE_CACHEABLE)) + +#define READWORD(address) \ + *((volatile unsigned int *)((address) | NONE_CACHEABLE)) + +/* Those two Macros were defined to be compatible with MIPS */ +#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff) +#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE) + +/* SET_REG_BITS(regOffset,bits) - + gets register offset and bits: a 32bit value. It set to logic '1' in the + internal register the bits which given as an input example: + SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic + '1' in register 0x840 while the other bits stays as is. */ +#define SET_REG_BITS(regOffset,bits) \ + *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ + regOffset) |= (unsigned int)WORD_SWAP(bits) + +/* RESET_REG_BITS(regOffset,bits) - + gets register offset and bits: a 32bit value. It set to logic '0' in the + internal register the bits which given as an input example: + RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic + '0' in register 0x840 while the other bits stays as is. */ +#define RESET_REG_BITS(regOffset,bits) \ + *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ + | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) + +#endif /* __INCcoreh */ diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h new file mode 100644 index 0000000..ebf087a --- /dev/null +++ b/include/galileo/gt64260R.h @@ -0,0 +1,1194 @@ +/* gt64260R.h - GT64260 Internal registers definition file */ + +/* Copyright - Galileo technology. */ + +#ifndef __INCgt64260rh +#define __INCgt64260rh + +#ifndef GT64260 +#define GT64260 +#endif + +/* CPU MASTER CONTROL REGISTER */ +#define CPU_CONFIGURATION 0x0 +#define CPU_MASTER_CONTROL 0x160 + +/****************************************/ +/* Processor Address Space */ +/****************************************/ + +/* Sdram's BAR'S */ +#define SCS_0_LOW_DECODE_ADDRESS 0x008 +#define SCS_0_HIGH_DECODE_ADDRESS 0x010 +#define SCS_1_LOW_DECODE_ADDRESS 0x208 +#define SCS_1_HIGH_DECODE_ADDRESS 0x210 +#define SCS_2_LOW_DECODE_ADDRESS 0x018 +#define SCS_2_HIGH_DECODE_ADDRESS 0x020 +#define SCS_3_LOW_DECODE_ADDRESS 0x218 +#define SCS_3_HIGH_DECODE_ADDRESS 0x220 +/* Devices BAR'S */ +#define CS_0_LOW_DECODE_ADDRESS 0x028 +#define CS_0_HIGH_DECODE_ADDRESS 0x030 +#define CS_1_LOW_DECODE_ADDRESS 0x228 +#define CS_1_HIGH_DECODE_ADDRESS 0x230 +#define CS_2_LOW_DECODE_ADDRESS 0x248 +#define CS_2_HIGH_DECODE_ADDRESS 0x250 +#define CS_3_LOW_DECODE_ADDRESS 0x038 +#define CS_3_HIGH_DECODE_ADDRESS 0x040 +#define BOOTCS_LOW_DECODE_ADDRESS 0x238 +#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 + +#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 +#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 +#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 +#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 +#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 +#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 +#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 +#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 +#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 +#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 + +#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 +#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 +#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 +#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 +#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 +#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 +#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 +#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 +#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 +#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 + + +#define INTERNAL_SPACE_DECODE 0x068 + +#define CPU_0_LOW_DECODE_ADDRESS 0x290 +#define CPU_0_HIGH_DECODE_ADDRESS 0x298 +#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 +#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 + +#define PCI_0I_O_ADDRESS_REMAP 0x0f0 +#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 +#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 +#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 +#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 +#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 +#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 +#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 +#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 + +#define PCI_1I_O_ADDRESS_REMAP 0x108 +#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 +#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 +#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 +#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 +#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 +#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 +#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 +#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 + + +/****************************************/ +/* CPU Sync Barrier */ +/****************************************/ + +#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0 +#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8 + + +/****************************************/ +/* CPU Access Protect */ +/****************************************/ + +#define CPU_LOW_PROTECT_ADDRESS_0 0x180 +#define CPU_HIGH_PROTECT_ADDRESS_0 0x188 +#define CPU_LOW_PROTECT_ADDRESS_1 0x190 +#define CPU_HIGH_PROTECT_ADDRESS_1 0x198 +#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0 +#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8 +#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0 +#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8 +#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0 +#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8 +#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0 +#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8 +#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0 +#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8 +#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0 +#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8 + + +/****************************************/ +/* Snoop Control */ +/****************************************/ + +#define SNOOP_BASE_ADDRESS_0 0x380 +#define SNOOP_TOP_ADDRESS_0 0x388 +#define SNOOP_BASE_ADDRESS_1 0x390 +#define SNOOP_TOP_ADDRESS_1 0x398 +#define SNOOP_BASE_ADDRESS_2 0x3a0 +#define SNOOP_TOP_ADDRESS_2 0x3a8 +#define SNOOP_BASE_ADDRESS_3 0x3b0 +#define SNOOP_TOP_ADDRESS_3 0x3b8 + +/****************************************/ +/* CPU Error Report */ +/****************************************/ + +#define CPU_ERROR_ADDRESS_LOW 0x070 +#define CPU_ERROR_ADDRESS_HIGH 0x078 +#define CPU_ERROR_DATA_LOW 0x128 +#define CPU_ERROR_DATA_HIGH 0x130 +#define CPU_ERROR_PARITY 0x138 +#define CPU_ERROR_CAUSE 0x140 +#define CPU_ERROR_MASK 0x148 + +/****************************************/ +/* Pslave Debug */ +/****************************************/ + +#define X_0_ADDRESS 0x360 +#define X_0_COMMAND_ID 0x368 +#define X_1_ADDRESS 0x370 +#define X_1_COMMAND_ID 0x378 +#define WRITE_DATA_LOW 0x3c0 +#define WRITE_DATA_HIGH 0x3c8 +#define WRITE_BYTE_ENABLE 0x3e0 +#define READ_DATA_LOW 0x3d0 +#define READ_DATA_HIGH 0x3d8 +#define READ_ID 0x3e8 + + +/****************************************/ +/* SDRAM and Device Address Space */ +/****************************************/ + + +/****************************************/ +/* SDRAM Configuration */ +/****************************************/ + + +#define SDRAM_CONFIGURATION 0x448 +#define SDRAM_OPERATION_MODE 0x474 +#define SDRAM_ADDRESS_DECODE 0x47c +#define SDRAM_UMA_CONTROL 0x4a4 +#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 +#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac +#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 +#define SDRAM_TIMING 0x4b4 + + +/****************************************/ +/* SDRAM Parameters */ +/****************************************/ + +#define SDRAM_BANK0PARAMETERS 0x44C +#define SDRAM_BANK1PARAMETERS 0x450 +#define SDRAM_BANK2PARAMETERS 0x454 +#define SDRAM_BANK3PARAMETERS 0x458 + + +/****************************************/ +/* SDRAM Error Report */ +/****************************************/ + +#define SDRAM_ERROR_DATA_LOW 0x484 +#define SDRAM_ERROR_DATA_HIGH 0x480 +#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490 +#define SDRAM_RECEIVED_ECC 0x488 +#define SDRAM_CALCULATED_ECC 0x48c +#define SDRAM_ECC_CONTROL 0x494 +#define SDRAM_ECC_ERROR_COUNTER 0x498 + + +/****************************************/ +/* SDunit Debug (for internal use) */ +/****************************************/ + +#define X0_ADDRESS 0x500 +#define X0_COMMAND_AND_ID 0x504 +#define X0_WRITE_DATA_LOW 0x508 +#define X0_WRITE_DATA_HIGH 0x50c +#define X0_WRITE_BYTE_ENABLE 0x518 +#define X0_READ_DATA_LOW 0x510 +#define X0_READ_DATA_HIGH 0x514 +#define X0_READ_ID 0x51c +#define X1_ADDRESS 0x520 +#define X1_COMMAND_AND_ID 0x524 +#define X1_WRITE_DATA_LOW 0x528 +#define X1_WRITE_DATA_HIGH 0x52c +#define X1_WRITE_BYTE_ENABLE 0x538 +#define X1_READ_DATA_LOW 0x530 +#define X1_READ_DATA_HIGH 0x534 +#define X1_READ_ID 0x53c +#define X0_SNOOP_ADDRESS 0x540 +#define X0_SNOOP_COMMAND 0x544 +#define X1_SNOOP_ADDRESS 0x548 +#define X1_SNOOP_COMMAND 0x54c + + +/****************************************/ +/* Device Parameters */ +/****************************************/ + +#define DEVICE_BANK0PARAMETERS 0x45c +#define DEVICE_BANK1PARAMETERS 0x460 +#define DEVICE_BANK2PARAMETERS 0x464 +#define DEVICE_BANK3PARAMETERS 0x468 +#define DEVICE_BOOT_BANK_PARAMETERS 0x46c +#define DEVICE_CONTROL 0x4c0 +#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 +#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc +#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 + + +/****************************************/ +/* Device Interrupt */ +/****************************************/ + +#define DEVICE_INTERRUPT_CAUSE 0x4d0 +#define DEVICE_INTERRUPT_MASK 0x4d4 +#define DEVICE_ERROR_ADDRESS 0x4d8 + +/****************************************/ +/* DMA Record */ +/****************************************/ + +#define CHANNEL0_DMA_BYTE_COUNT 0x800 +#define CHANNEL1_DMA_BYTE_COUNT 0x804 +#define CHANNEL2_DMA_BYTE_COUNT 0x808 +#define CHANNEL3_DMA_BYTE_COUNT 0x80C +#define CHANNEL4_DMA_BYTE_COUNT 0x900 +#define CHANNEL5_DMA_BYTE_COUNT 0x904 +#define CHANNEL6_DMA_BYTE_COUNT 0x908 +#define CHANNEL7_DMA_BYTE_COUNT 0x90C +#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 +#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 +#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 +#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C +#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910 +#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914 +#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918 +#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C +#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 +#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 +#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 +#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C +#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920 +#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924 +#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928 +#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C +#define CHANNEL0NEXT_RECORD_POINTER 0x830 +#define CHANNEL1NEXT_RECORD_POINTER 0x834 +#define CHANNEL2NEXT_RECORD_POINTER 0x838 +#define CHANNEL3NEXT_RECORD_POINTER 0x83C +#define CHANNEL4NEXT_RECORD_POINTER 0x930 +#define CHANNEL5NEXT_RECORD_POINTER 0x934 +#define CHANNEL6NEXT_RECORD_POINTER 0x938 +#define CHANNEL7NEXT_RECORD_POINTER 0x93C +#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 +#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 +#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 +#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C +#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970 +#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974 +#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978 +#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C +#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890 +#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894 +#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898 +#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c +#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990 +#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994 +#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998 +#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c +#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0 +#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4 +#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8 +#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac +#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0 +#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4 +#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8 +#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac +#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0 +#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4 +#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8 +#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc +#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0 +#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4 +#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8 +#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc + +/****************************************/ +/* DMA Channel Control */ +/****************************************/ + +#define CHANNEL0CONTROL 0x840 +#define CHANNEL0CONTROL_HIGH 0x880 +#define CHANNEL1CONTROL 0x844 +#define CHANNEL1CONTROL_HIGH 0x884 +#define CHANNEL2CONTROL 0x848 +#define CHANNEL2CONTROL_HIGH 0x888 +#define CHANNEL3CONTROL 0x84C +#define CHANNEL3CONTROL_HIGH 0x88C + +#define CHANNEL4CONTROL 0x940 +#define CHANNEL4CONTROL_HIGH 0x980 +#define CHANNEL5CONTROL 0x944 +#define CHANNEL5CONTROL_HIGH 0x984 +#define CHANNEL6CONTROL 0x948 +#define CHANNEL6CONTROL_HIGH 0x988 +#define CHANNEL7CONTROL 0x94C +#define CHANNEL7CONTROL_HIGH 0x98C + + +/****************************************/ +/* DMA Arbiter */ +/****************************************/ + +#define ARBITER_CONTROL_0_3 0x860 +#define ARBITER_CONTROL_4_7 0x960 + + +/****************************************/ +/* DMA Interrupt */ +/****************************************/ + +#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 +#define CHANELS0_3_INTERRUPT_MASK 0x8c4 +#define CHANELS0_3_ERROR_ADDRESS 0x8c8 +#define CHANELS0_3_ERROR_SELECT 0x8cc +#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0 +#define CHANELS4_7_INTERRUPT_MASK 0x9c4 +#define CHANELS4_7_ERROR_ADDRESS 0x9c8 +#define CHANELS4_7_ERROR_SELECT 0x9cc + + +/****************************************/ +/* DMA Debug (for internal use) */ +/****************************************/ + +#define DMA_X0_ADDRESS 0x8e0 +#define DMA_X0_COMMAND_AND_ID 0x8e4 +#define DMA_X0_WRITE_DATA_LOW 0x8e8 +#define DMA_X0_WRITE_DATA_HIGH 0x8ec +#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8 +#define DMA_X0_READ_DATA_LOW 0x8f0 +#define DMA_X0_READ_DATA_HIGH 0x8f4 +#define DMA_X0_READ_ID 0x8fc +#define DMA_X1_ADDRESS 0x9e0 +#define DMA_X1_COMMAND_AND_ID 0x9e4 +#define DMA_X1_WRITE_DATA_LOW 0x9e8 +#define DMA_X1_WRITE_DATA_HIGH 0x9ec +#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8 +#define DMA_X1_READ_DATA_LOW 0x9f0 +#define DMA_X1_READ_DATA_HIGH 0x9f4 +#define DMA_X1_READ_ID 0x9fc + +/****************************************/ +/* Timer_Counter */ +/****************************************/ + +#define TIMER_COUNTER0 0x850 +#define TIMER_COUNTER1 0x854 +#define TIMER_COUNTER2 0x858 +#define TIMER_COUNTER3 0x85C +#define TIMER_COUNTER_0_3_CONTROL 0x864 +#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 +#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c +#define TIMER_COUNTER4 0x950 +#define TIMER_COUNTER5 0x954 +#define TIMER_COUNTER6 0x958 +#define TIMER_COUNTER7 0x95C +#define TIMER_COUNTER_4_7_CONTROL 0x964 +#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968 +#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c + +/****************************************/ +/* PCI Slave Address Decoding */ +/****************************************/ + +#define PCI_0SCS_0_BANK_SIZE 0xc08 +#define PCI_1SCS_0_BANK_SIZE 0xc88 +#define PCI_0SCS_1_BANK_SIZE 0xd08 +#define PCI_1SCS_1_BANK_SIZE 0xd88 +#define PCI_0SCS_2_BANK_SIZE 0xc0c +#define PCI_1SCS_2_BANK_SIZE 0xc8c +#define PCI_0SCS_3_BANK_SIZE 0xd0c +#define PCI_1SCS_3_BANK_SIZE 0xd8c +#define PCI_0CS_0_BANK_SIZE 0xc10 +#define PCI_1CS_0_BANK_SIZE 0xc90 +#define PCI_0CS_1_BANK_SIZE 0xd10 +#define PCI_1CS_1_BANK_SIZE 0xd90 +#define PCI_0CS_2_BANK_SIZE 0xd18 +#define PCI_1CS_2_BANK_SIZE 0xd98 +#define PCI_0CS_3_BANK_SIZE 0xc14 +#define PCI_1CS_3_BANK_SIZE 0xc94 +#define PCI_0CS_BOOT_BANK_SIZE 0xd14 +#define PCI_1CS_BOOT_BANK_SIZE 0xd94 +#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c +#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c +#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 +#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 +#define PCI_0P2P_I_O_BAR_SIZE 0xd24 +#define PCI_1P2P_I_O_BAR_SIZE 0xda4 +#define PCI_0CPU_BAR_SIZE 0xd28 +#define PCI_1CPU_BAR_SIZE 0xda8 +#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 +#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 +#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 +#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 +#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 +#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 +#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c +#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c +#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 +#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 +#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 +#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 +#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 +#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 +#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c +#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c +#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 +#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 +#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 +#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 +#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 +#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 +#define PCI_0DAC_CPU_BAR_SIZE 0xe2c +#define PCI_1DAC_CPU_BAR_SIZE 0xeac +#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c +#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac +#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c +#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc +#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 +#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 +#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 +#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 +#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c +#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc +#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c +#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc +#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 +#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 +#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 +#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 +#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 +#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 +#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 +#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 +#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 +#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 +#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c +#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc +#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 +#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 +#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 +#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 +#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 +#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 +#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c +#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec +#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 +#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 +#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 +#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 +#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 +#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 +#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 +#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 +#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c +#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c +#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 +#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 +#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 +#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 +#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 +#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 +#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c +#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c +#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 +#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 +#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 +#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 +#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 +#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 +#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c +#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac +#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 +#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 +#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 +#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 +#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 +#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 +#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c +#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc + +/****************************************/ +/* PCI Control */ +/****************************************/ + +#define PCI_0COMMAND 0xc00 +#define PCI_1COMMAND 0xc80 +#define PCI_0MODE 0xd00 +#define PCI_1MODE 0xd80 +#define PCI_0TIMEOUT_RETRY 0xc04 +#define PCI_1TIMEOUT_RETRY 0xc84 +#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 +#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 +#define MSI_0TRIGGER_TIMER 0xc38 +#define MSI_1TRIGGER_TIMER 0xcb8 +#define PCI_0ARBITER_CONTROL 0x1d00 +#define PCI_1ARBITER_CONTROL 0x1d80 +/* changing untill here */ +#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 +#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c +#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 +#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 +#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c +#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 +#define PCI_0P2P_CONFIGURATION 0x1d14 +#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 +#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 +#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 +#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10 +#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 +#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 +#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20 +#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 +#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 +#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30 +#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 +#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 +#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40 +#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 +#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 +#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50 +#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 +#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 +#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60 +#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 +#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 +#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70 +#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 +#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 +#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 +#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c +#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 +#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 +#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c +#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 +#define PCI_1P2P_CONFIGURATION 0x1d94 +#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 +#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 +#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 +#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90 +#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 +#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 +#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0 +#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 +#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 +#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0 +#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 +#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 +#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0 +#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 +#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 +#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0 +#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 +#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 +#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0 +#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 +#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 +#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0 +#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 +#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 + +/****************************************/ +/* PCI Snoop Control */ +/****************************************/ + +#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 +#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 +#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 +#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 +#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 +#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 +#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 +#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 +#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 +#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 +#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 +#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 +#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 +#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 +#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 +#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 +#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 +#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 +#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 +#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 +#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 +#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 +#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 +#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 + +/****************************************/ +/* PCI Configuration Address */ +/****************************************/ + +#define PCI_0CONFIGURATION_ADDRESS 0xcf8 +#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc +#define PCI_1CONFIGURATION_ADDRESS 0xc78 +#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c +#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 +#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 + +/****************************************/ +/* PCI Error Report */ +/****************************************/ + +#define PCI_0SERR_MASK 0xc28 +#define PCI_0ERROR_ADDRESS_LOW 0x1d40 +#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 +#define PCI_0ERROR_DATA_LOW 0x1d48 +#define PCI_0ERROR_DATA_HIGH 0x1d4c +#define PCI_0ERROR_COMMAND 0x1d50 +#define PCI_0ERROR_CAUSE 0x1d58 +#define PCI_0ERROR_MASK 0x1d5c +#define PCI_1SERR_MASK 0xca8 +#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 +#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 +#define PCI_1ERROR_DATA_LOW 0x1dc8 +#define PCI_1ERROR_DATA_HIGH 0x1dcc +#define PCI_1ERROR_COMMAND 0x1dd0 +#define PCI_1ERROR_CAUSE 0x1dd8 +#define PCI_1ERROR_MASK 0x1ddc + + +/****************************************/ +/* Lslave Debug (for internal use) */ +/****************************************/ + +#define L_SLAVE_X0_ADDRESS 0x1d20 +#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 +#define L_SLAVE_X1_ADDRESS 0x1d28 +#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c +#define L_SLAVE_WRITE_DATA_LOW 0x1d30 +#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 +#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 +#define L_SLAVE_READ_DATA_LOW 0x1d38 +#define L_SLAVE_READ_DATA_HIGH 0x1d3c +#define L_SLAVE_READ_ID 0x1d64 + +/****************************************/ +/* PCI Configuration Function 0 */ +/****************************************/ + +#define PCI_DEVICE_AND_VENDOR_ID 0x000 +#define PCI_STATUS_AND_COMMAND 0x004 +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C +#define PCI_SCS_0_BASE_ADDRESS 0x010 +#define PCI_SCS_1_BASE_ADDRESS 0x014 +#define PCI_SCS_2_BASE_ADDRESS 0x018 +#define PCI_SCS_3_BASE_ADDRESS 0x01C +#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 +#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 +#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C +#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 +#define PCI_CAPABILTY_LIST_POINTER 0x034 +#define PCI_INTERRUPT_PIN_AND_LINE 0x03C +#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define PCI_VPD_ADDRESS 0x048 +#define PCI_VPD_DATA 0x04c +#define PCI_MSI_MESSAGE_CONTROL 0x050 +#define PCI_MSI_MESSAGE_ADDRESS 0x054 +#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 +#define PCI_MSI_MESSAGE_DATA 0x05c +#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 + +/****************************************/ +/* PCI Configuration Function 1 */ +/****************************************/ + +#define PCI_CS_0_BASE_ADDRESS 0x110 +#define PCI_CS_1_BASE_ADDRESS 0x114 +#define PCI_CS_2_BASE_ADDRESS 0x118 +#define PCI_CS_3_BASE_ADDRESS 0x11c +#define PCI_BOOTCS_BASE_ADDRESS 0x120 + +/****************************************/ +/* PCI Configuration Function 2 */ +/****************************************/ + +#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 +#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 +#define PCI_P2P_I_O_BASE_ADDRESS 0x218 +#define PCI_CPU_BASE_ADDRESS 0x21c + +/****************************************/ +/* PCI Configuration Function 4 */ +/****************************************/ + +#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 +#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 +#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 +#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 + + +/****************************************/ +/* PCI Configuration Function 5 */ +/****************************************/ + +#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 +#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 +#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 +#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 + + +/****************************************/ +/* PCI Configuration Function 6 */ +/****************************************/ + +#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 +#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 +#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 +#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c +#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 +#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 + +/****************************************/ +/* PCI Configuration Function 7 */ +/****************************************/ + +#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 +#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c +#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 +#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 + +/****************************************/ +/* Interrupts */ +/****************************************/ + +#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18 +#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68 +#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c +#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c +#define CPU_SELECT_CAUSE_REGISTER 0xc70 +#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24 +#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64 +#define PCI_0SELECT_CAUSE 0xc74 +#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4 +#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4 +#define PCI_1SELECT_CAUSE 0xcf4 +#define CPU_INT_0_MASK 0xe60 +#define CPU_INT_1_MASK 0xe64 +#define CPU_INT_2_MASK 0xe68 +#define CPU_INT_3_MASK 0xe6c + +/****************************************/ +/* I20 Support registers */ +/****************************************/ + +#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 +#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 +#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 +#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C +#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 +#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 +#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 +#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 +#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 +#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 +#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C + +#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10 +#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14 +#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18 +#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C +#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24 +#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28 +#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44 +#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50 +#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64 +#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68 +#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C + +/****************************************/ +/* Communication Unit Registers */ +/****************************************/ + +#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200 +#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 +#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 +#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c +#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 +#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 +#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 +#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 +#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 +#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 +#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c +#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 +#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 +#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 +#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 +#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 +#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 +#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c +#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 +#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 +#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 +#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 +#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 +#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 +#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c +#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 +#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 +#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0 +#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4 +#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 +#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc +#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 +#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 +#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320 +#define SERIAL_INIT_LAST_DATA 0xf324 +#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328 +#define COMM_UNIT_ARBITER_CONTROL 0xf300 +#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 +#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 +#define COMM_UNIT_INTERRUPT_MASK 0xf314 +#define COMM_UNIT_ERROR_ADDRESS 0xf314 + +/****************************************/ +/* Cunit Debug (for internal use) */ +/****************************************/ + +#define CUNIT_ADDRESS 0xf340 +#define CUNIT_COMMAND_AND_ID 0xf344 +#define CUNIT_WRITE_DATA_LOW 0xf348 +#define CUNIT_WRITE_DATA_HIGH 0xf34c +#define CUNIT_WRITE_BYTE_ENABLE 0xf358 +#define CUNIT_READ_DATA_LOW 0xf350 +#define CUNIT_READ_DATA_HIGH 0xf354 +#define CUNIT_READ_ID 0xf35c + +/****************************************/ +/* Fast Ethernet Unit Registers */ +/****************************************/ + +/* Ethernet */ + +#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 +#define ETHERNET_SMI_REGISTER 0x2010 + +/* Ethernet 0 */ + +#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 +#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 +#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 +#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 +#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 +#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 +#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 +#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 +#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 +#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 +#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 +#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac +#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 +#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 +#define ETHERNET0_MIB_COUNTER_BASE 0x2500 + +/* Ethernet 1 */ + +#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 +#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 +#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 +#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 +#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 +#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 +#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 +#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 +#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 +#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 +#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 +#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac +#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 +#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 +#define ETHERNET1_MIB_COUNTER_BASE 0x2900 + +/* Ethernet 2 */ + +#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 +#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 +#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 +#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 +#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 +#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 +#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 +#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 +#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 +#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 +#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 +#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac +#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 +#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 +#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 + +/****************************************/ +/* SDMA Registers */ +/****************************************/ + +#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 +#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 +#define CHANNEL0_COMMAND_REGISTER 0x4008 +#define CHANNEL0_RX_CMD_STATUS 0x4800 +#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 +#define CHANNEL0_RX_BUFFER_POINTER 0x4808 +#define CHANNEL0_RX_NEXT_POINTER 0x480c +#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 +#define CHANNEL0_TX_CMD_STATUS 0x4C00 +#define CHANNEL0_TX_PACKET_SIZE 0x4C04 +#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 +#define CHANNEL0_TX_NEXT_POINTER 0x4C0c +#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 +#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 +#define CHANNEL1_CONFIGURATION_REGISTER 0x5000 +#define CHANNEL1_COMMAND_REGISTER 0x5008 +#define CHANNEL1_RX_CMD_STATUS 0x5800 +#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804 +#define CHANNEL1_RX_BUFFER_POINTER 0x5808 +#define CHANNEL1_RX_NEXT_POINTER 0x580c +#define CHANNEL1_TX_CMD_STATUS 0x5C00 +#define CHANNEL1_TX_PACKET_SIZE 0x5C04 +#define CHANNEL1_TX_BUFFER_POINTER 0x5C08 +#define CHANNEL1_TX_NEXT_POINTER 0x5C0c +#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810 +#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10 +#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14 +#define CHANNEL2_CONFIGURATION_REGISTER 0x6000 +#define CHANNEL2_COMMAND_REGISTER 0x6008 +#define CHANNEL2_RX_CMD_STATUS 0x6800 +#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804 +#define CHANNEL2_RX_BUFFER_POINTER 0x6808 +#define CHANNEL2_RX_NEXT_POINTER 0x680c +#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 +#define CHANNEL2_TX_CMD_STATUS 0x6C00 +#define CHANNEL2_TX_PACKET_SIZE 0x6C04 +#define CHANNEL2_TX_BUFFER_POINTER 0x6C08 +#define CHANNEL2_TX_NEXT_POINTER 0x6C0c +#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 +#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 +#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 + +/* SDMA Interrupt */ + +#define SDMA_CAUSE 0xb820 +#define SDMA_MASK 0xb8a0 + + +/****************************************/ +/* Baude Rate Generators Registers */ +/****************************************/ + +/* BRG 0 */ + +#define BRG0_CONFIGURATION_REGISTER 0xb200 +#define BRG0_BAUDE_TUNING_REGISTER 0xb204 + +/* BRG 1 */ + +#define BRG1_CONFIGURATION_REGISTER 0xb208 +#define BRG1_BAUDE_TUNING_REGISTER 0xb20c + +/* BRG 2 */ + +#define BRG2_CONFIGURATION_REGISTER 0xb210 +#define BRG2_BAUDE_TUNING_REGISTER 0xb214 + +/* BRG Interrupts */ + +#define BRG_CAUSE_REGISTER 0xb834 +#define BRG_MASK_REGISTER 0xb8b4 + +/* MISC */ + +#define MAIN_ROUTING_REGISTER 0xb400 +#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 +#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 +#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c +#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 +#define WATCHDOG_VALUE_REGISTER 0xb414 + + +/****************************************/ +/* Flex TDM Registers */ +/****************************************/ + +/* FTDM Port */ + +#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 +#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 +#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 +#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c +#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 +#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 +#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 + +/* FTDM Interrupts */ + +#define FTDM_CAUSE_REGISTER 0xb830 +#define FTDM_MASK_REGISTER 0xb8b0 + + +/****************************************/ +/* GPP Interface Registers */ +/****************************************/ + +#define GPP_IO_CONTROL 0xf100 +#define GPP_LEVEL_CONTROL 0xf110 +#define GPP_VALUE 0xf104 +#define GPP_INTERRUPT_CAUSE 0xf108 +#define GPP_INTERRUPT_MASK 0xf10c + +#define MPP_CONTROL0 0xf000 +#define MPP_CONTROL1 0xf004 +#define MPP_CONTROL2 0xf008 +#define MPP_CONTROL3 0xf00c +#define DEBUG_PORT_MULTIPLEX 0xf014 +#define SERIAL_PORT_MULTIPLEX 0xf010 + +/****************************************/ +/* I2C Registers */ +/****************************************/ + +#define I2C_SLAVE_ADDRESS 0xc000 +#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 +#define I2C_DATA 0xc004 +#define I2C_CONTROL 0xc008 +#define I2C_STATUS_BAUDE_RATE 0xc00C +#define I2C_SOFT_RESET 0xc01c + +/****************************************/ +/* MPSC Registers */ +/****************************************/ + +/* MPSC0 */ + +#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 +#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 +#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 +#define CHANNEL0_REGISTER1 0x800c +#define CHANNEL0_REGISTER2 0x8010 +#define CHANNEL0_REGISTER3 0x8014 +#define CHANNEL0_REGISTER4 0x8018 +#define CHANNEL0_REGISTER5 0x801c +#define CHANNEL0_REGISTER6 0x8020 +#define CHANNEL0_REGISTER7 0x8024 +#define CHANNEL0_REGISTER8 0x8028 +#define CHANNEL0_REGISTER9 0x802c +#define CHANNEL0_REGISTER10 0x8030 +#define CHANNEL0_REGISTER11 0x8034 + +/* MPSC1 */ + +#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840 +#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844 +#define MPSC1_PROTOCOL_CONFIGURATION 0x8848 +#define CHANNEL1_REGISTER1 0x884c +#define CHANNEL1_REGISTER2 0x8850 +#define CHANNEL1_REGISTER3 0x8854 +#define CHANNEL1_REGISTER4 0x8858 +#define CHANNEL1_REGISTER5 0x885c +#define CHANNEL1_REGISTER6 0x8860 +#define CHANNEL1_REGISTER7 0x8864 +#define CHANNEL1_REGISTER8 0x8868 +#define CHANNEL1_REGISTER9 0x886c +#define CHANNEL1_REGISTER10 0x8870 +#define CHANNEL1_REGISTER11 0x8874 + +/* MPSC2 */ + +#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040 +#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044 +#define MPSC2_PROTOCOL_CONFIGURATION 0x9048 +#define CHANNEL2_REGISTER1 0x904c +#define CHANNEL2_REGISTER2 0x9050 +#define CHANNEL2_REGISTER3 0x9054 +#define CHANNEL2_REGISTER4 0x9058 +#define CHANNEL2_REGISTER5 0x905c +#define CHANNEL2_REGISTER6 0x9060 +#define CHANNEL2_REGISTER7 0x9064 +#define CHANNEL2_REGISTER8 0x9068 +#define CHANNEL2_REGISTER9 0x906c +#define CHANNEL2_REGISTER10 0x9070 +#define CHANNEL2_REGISTER11 0x9074 + +/* MPSCs Interupts */ + +#define MPSC0_CAUSE 0xb824 +#define MPSC0_MASK 0xb8a4 +#define MPSC1_CAUSE 0xb828 +#define MPSC1_MASK 0xb8a8 +#define MPSC2_CAUSE 0xb82c +#define MPSC2_MASK 0xb8ac + +#endif /* __INCgt64260rh */ diff --git a/include/galileo/memory.h b/include/galileo/memory.h new file mode 100644 index 0000000..0c46c24 --- /dev/null +++ b/include/galileo/memory.h @@ -0,0 +1,85 @@ +/* Memory.h - Memory mappings and remapping functions declarations */ + +/* Copyright - Galileo technology. */ + +#ifndef __INCmemoryh +#define __INCmemoryh + +/* includes */ + +#include "core.h" + +/* defines */ + +#define DONT_MODIFY 0xffffffff +#define PARITY_SUPPORT 0x40000000 + +#define _8BIT 0x00000000 +#define _16BIT 0x00100000 +#define _32BIT 0x00200000 +#define _64BIT 0x00300000 + +/* typedefs */ + + typedef struct deviceParam +{ /* boundary values */ + unsigned int turnOff; /* 0x0 - 0xf */ + unsigned int acc2First; /* 0x0 - 0x1f */ + unsigned int acc2Next; /* 0x0 - 0x1f */ + unsigned int ale2Wr; /* 0x0 - 0xf */ + unsigned int wrLow; /* 0x0 - 0xf */ + unsigned int wrHigh; /* 0x0 - 0xf */ + unsigned int deviceWidth; /* in Bytes */ +} DEVICE_PARAM; + +typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK; +typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE; + +typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \ + MEM_REGION3,MEM_REGION4,MEM_REGION5, \ + MEM_REGION6,MEM_REGION7} \ + MEMORY_PROTECT_REGION; +typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \ + MEMORY_ACCESS; +typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \ + MEMORY_ACCESS_WRITE; +typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \ + MEMORY_CACHE_PROTECT; +typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \ + MEMORY_SNOOP_TYPE; +typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \ + MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \ + MEMORY_SNOOP_REGION; + +/* functions */ +unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank); +unsigned int memoryGetDeviceBaseAddress(DEVICE device); +unsigned int memoryGetBankSize(MEMORY_BANK bank); +unsigned int memoryGetDeviceSize(DEVICE device); +unsigned int memoryGetDeviceWidth(DEVICE device); + +/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/ +bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength); +bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength); + +/* Change the Internal Register Base Address to a new given Address. */ +bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); +/* returns internal Register Space Base Address. */ +unsigned int memoryGetInternalRegistersSpace(void); +/* Configurate the protection feature to a given space. */ +bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, + MEMORY_ACCESS memoryAccess, + MEMORY_ACCESS_WRITE memoryWrite, + MEMORY_CACHE_PROTECT cacheProtection, + unsigned int baseAddress, + unsigned int regionLength); +/* Configurate the snoop feature to a given space. */ +bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, + MEMORY_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength); + +bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue); +bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); +bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); +#endif /* __INCmemoryh */ diff --git a/include/galileo/pci.h b/include/galileo/pci.h new file mode 100644 index 0000000..6ed8b95 --- /dev/null +++ b/include/galileo/pci.h @@ -0,0 +1,113 @@ +/* PCI.h - PCI functions header file */ + +/* Copyright - Galileo technology. */ + +#ifndef __INCpcih +#define __INCpcih + +/* includes */ + +#include "core.h" +#include "memory.h" + +/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ +#define PCI_MAX_DEVICES 22 + + +/* Macros */ +#define SELF 32 + +/* Defines for the access regions. */ +#define PREFETCH_ENABLE BIT12 +#define PREFETCH_DISABLE NO_BIT +#define DELAYED_READ_ENABLE BIT13 +/* #define CACHING_ENABLE BIT14 */ +/* aggressive prefetch: PCI slave prefetch two burst in advance*/ +#define AGGRESSIVE_PREFETCH BIT16 +/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/ +#define READ_LINE_AGGRESSIVE_PREFETCH BIT17 +/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/ +#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18 +#define MAX_BURST_4 NO_BIT +#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */ +#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */ +#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */ +#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */ +#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */ +#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */ +#define PCI_ACCESS_PROTECT BIT28 +#define PCI_WRITE_PROTECT BIT29 + +/* typedefs */ + +typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5, + REGION6,REGION7} PCI_ACCESS_REGIONS; + +typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO; +typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK; + +typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} + PCI_SNOOP_TYPE; +typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, + PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} + PCI_SNOOP_REGION; + +typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; +typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, + PCI_REGION2,PCI_REGION3, + PCI_IO} + PCI_REGION; + +/* read/write configuration registers on local PCI bus. */ +void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum, unsigned int data); +unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, + unsigned int pciDevNum); + +/* read/write configuration registers on another PCI bus. */ +void pciOverBridgeWriteConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum,unsigned int data); +unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum); + +/* Master`s memory space */ +bool pciMapSpace(PCI_HOST host, PCI_REGION region, + unsigned int remapBase, + unsigned int deviceBase, + unsigned int deviceLength); +unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); +unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); + +/* Slave`s memory space */ +void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, + unsigned int pci0Dram0Base, unsigned int pci0Dram0Size); + +/* PCI region options */ + +bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region, + unsigned int features, unsigned int baseAddress, + unsigned int regionLength); + +void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); + +/* PCI arbiter */ + +bool pciArbiterEnable(PCI_HOST host); +bool pciArbiterDisable(PCI_HOST host); +bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, + PCI_AGENT_PARK externalAgent0, + PCI_AGENT_PARK externalAgent1, + PCI_AGENT_PARK externalAgent2, + PCI_AGENT_PARK externalAgent3, + PCI_AGENT_PARK externalAgent4, + PCI_AGENT_PARK externalAgent5); +bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, + PCI_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength); + +#endif /* __INCpcih */ diff --git a/include/hush.h b/include/hush.h new file mode 100644 index 0000000..20e48db --- /dev/null +++ b/include/hush.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _HUSH_H_ +#define _HUSH_H_ + +#define FLAG_EXIT_FROM_LOOP 1 +#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ +#define FLAG_REPARSING (1 << 2) /* >=2nd pass */ + +extern int u_boot_hush_start(void); +extern int parse_string_outer(char *, int); +extern int parse_file_outer(void); + +#endif diff --git a/include/i2c.h b/include/i2c.h new file mode 100644 index 0000000..6d39080 --- /dev/null +++ b/include/i2c.h @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * The original I2C interface was + * (C) 2000 by Paolo Scaffardi (arsenio@tin.it) + * AIRVENT SAM s.p.a - RIMINI(ITALY) + * but has been changed substantially. + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +/* + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + * + * The implementation MUST NOT use static or global variables if the + * I2C routines are used to read SDRAM configuration information + * because this is done before the memories are initialized. Limited + * use of stack-based variables are OK (the initial stack size is + * limited). + * + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + */ + +/* + * Configuration items. + */ +#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +void i2c_init(int speed, int slaveaddr); +#ifdef CFG_I2C_INIT_BOARD +void i2c_init_board(void); +#endif + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uchar chip); + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); + +/* + * Utility routines to read/write registers. + */ +uchar i2c_reg_read (uchar chip, uchar reg); +void i2c_reg_write(uchar chip, uchar reg, uchar val); + +#endif /* _I2C_H_ */ diff --git a/include/i8042.h b/include/i8042.h new file mode 100644 index 0000000..f77239f --- /dev/null +++ b/include/i8042.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* i8042.h - Intel 8042 keyboard driver header */ + +#ifndef _I8042_H_ +#define _I8042_H_ + +#ifdef __I386__ +#include +#include +#define in8(p) inb(p) +#define out8(p,v) outb(v,p) +#endif + +/* defines */ + +#define I8042_DATA_REG (CFG_ISA_IO + 0x0060) /* keyboard i/o buffer */ +#define I8042_STATUS_REG (CFG_ISA_IO + 0x0064) /* keyboard status read */ +#define I8042_COMMAND_REG (CFG_ISA_IO + 0x0064) /* keyboard ctrl write */ + +#define KBD_US 0 /* default US layout */ +#define KBD_GER 1 /* german layout */ + +#define KBD_TIMEOUT 1000 /* 1 sec */ +#define KBD_RESET_TRIES 3 + +#define AS 0 /* normal character index */ +#define SH 1 /* shift index */ +#define CN 2 /* control index */ +#define NM 3 /* numeric lock index */ +#define AK 4 /* right alt key */ +#define CP 5 /* capslock index */ +#define ST 6 /* stop output index */ +#define EX 7 /* extended code index */ +#define ES 8 /* escape and extended code index */ + +#define NORMAL 0x0000 /* normal key */ +#define STP 0x0001 /* scroll lock stop output*/ +#define NUM 0x0002 /* numeric lock */ +#define CAPS 0x0004 /* capslock */ +#define SHIFT 0x0008 /* shift */ +#define CTRL 0x0010 /* control*/ +#define EXT 0x0020 /* extended scan code 0xe0 */ +#define ESC 0x0040 /* escape key press */ +#define E1 0x0080 /* extended scan code 0xe1 */ +#define BRK 0x0100 /* make break flag for keyboard */ +#define ALT 0x0200 /* right alt */ + +/* exports */ + +int i8042_kbd_init(void); +int i8042_tstc(void); +int i8042_getc(void); + +#endif /* _I8042_H_ */ diff --git a/include/ide.h b/include/ide.h new file mode 100644 index 0000000..dfef32f --- /dev/null +++ b/include/ide.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IDE_H +#define _IDE_H + +#define IDE_BUS(dev) (dev >> 1) + +#ifdef CONFIG_IDE_LED + +/* + * LED Port + */ +#define LED_PORT ((uchar *)(PER8_BASE + 0x3000)) +#define LED_IDE1 0x01 +#define LED_IDE2 0x02 +#define DEVICE_LED(d) ((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */ + +#endif /* CONFIG_IDE_LED */ + +#ifdef CFG_64BIT_LBA +typedef uint64_t lbaint_t; +#else +typedef ulong lbaint_t; +#endif + +/* + * Function Prototypes + */ + +void ide_init (void); +ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer); +ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer); + +#endif /* _IDE_H */ diff --git a/include/image.h b/include/image.h new file mode 100644 index 0000000..af37bca --- /dev/null +++ b/include/image.h @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __IMAGE_H__ +#define __IMAGE_H__ + +/* + * Operating System Codes + */ +#define IH_OS_INVALID 0 /* Invalid OS */ +#define IH_OS_OPENBSD 1 /* OpenBSD */ +#define IH_OS_NETBSD 2 /* NetBSD */ +#define IH_OS_FREEBSD 3 /* FreeBSD */ +#define IH_OS_4_4BSD 4 /* 4.4BSD */ +#define IH_OS_LINUX 5 /* Linux */ +#define IH_OS_SVR4 6 /* SVR4 */ +#define IH_OS_ESIX 7 /* Esix */ +#define IH_OS_SOLARIS 8 /* Solaris */ +#define IH_OS_IRIX 9 /* Irix */ +#define IH_OS_SCO 10 /* SCO */ +#define IH_OS_DELL 11 /* Dell */ +#define IH_OS_NCR 12 /* NCR */ +#define IH_OS_LYNXOS 13 /* LynxOS */ +#define IH_OS_VXWORKS 14 /* VxWorks */ +#define IH_OS_PSOS 15 /* pSOS */ +#define IH_OS_QNX 16 /* QNX */ +#define IH_OS_U_BOOT 17 /* Firmware */ +#define IH_OS_RTEMS 18 /* RTEMS */ +#define IH_OS_ARTOS 19 /* ARTOS */ +#define IH_OS_UNITY 20 /* Unity OS */ + +/* + * CPU Architecture Codes (supported by Linux) + */ +#define IH_CPU_INVALID 0 /* Invalid CPU */ +#define IH_CPU_ALPHA 1 /* Alpha */ +#define IH_CPU_ARM 2 /* ARM */ +#define IH_CPU_I386 3 /* Intel x86 */ +#define IH_CPU_IA64 4 /* IA64 */ +#define IH_CPU_MIPS 5 /* MIPS */ +#define IH_CPU_MIPS64 6 /* MIPS 64 Bit */ +#define IH_CPU_PPC 7 /* PowerPC */ +#define IH_CPU_S390 8 /* IBM S390 */ +#define IH_CPU_SH 9 /* SuperH */ +#define IH_CPU_SPARC 10 /* Sparc */ +#define IH_CPU_SPARC64 11 /* Sparc 64 Bit */ +#define IH_CPU_M68K 12 /* M68K */ +#define IH_CPU_NIOS 13 /* Nios-32 */ +#define IH_CPU_MICROBLAZE 14 /* MicroBlaze */ +#define IH_CPU_NIOS2 15 /* Nios-II */ + +/* + * Image Types + * + * "Standalone Programs" are directly runnable in the environment + * provided by U-Boot; it is expected that (if they behave + * well) you can continue to work in U-Boot after return from + * the Standalone Program. + * "OS Kernel Images" are usually images of some Embedded OS which + * will take over control completely. Usually these programs + * will install their own set of exception handlers, device + * drivers, set up the MMU, etc. - this means, that you cannot + * expect to re-enter U-Boot except by resetting the CPU. + * "RAMDisk Images" are more or less just data blocks, and their + * parameters (address, size) are passed to an OS kernel that is + * being started. + * "Multi-File Images" contain several images, typically an OS + * (Linux) kernel image and one or more data images like + * RAMDisks. This construct is useful for instance when you want + * to boot over the network using BOOTP etc., where the boot + * server provides just a single image file, but you want to get + * for instance an OS kernel and a RAMDisk image. + * + * "Multi-File Images" start with a list of image sizes, each + * image size (in bytes) specified by an "uint32_t" in network + * byte order. This list is terminated by an "(uint32_t)0". + * Immediately after the terminating 0 follow the images, one by + * one, all aligned on "uint32_t" boundaries (size rounded up to + * a multiple of 4 bytes - except for the last file). + * + * "Firmware Images" are binary images containing firmware (like + * U-Boot or FPGA images) which usually will be programmed to + * flash memory. + * + * "Script files" are command sequences that will be executed by + * U-Boot's command interpreter; this feature is especially + * useful when you configure U-Boot to use a real shell (hush) + * as command interpreter (=> Shell Scripts). + */ + +#define IH_TYPE_INVALID 0 /* Invalid Image */ +#define IH_TYPE_STANDALONE 1 /* Standalone Program */ +#define IH_TYPE_KERNEL 2 /* OS Kernel Image */ +#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */ +#define IH_TYPE_MULTI 4 /* Multi-File Image */ +#define IH_TYPE_FIRMWARE 5 /* Firmware Image */ +#define IH_TYPE_SCRIPT 6 /* Script file */ +#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ + +/* + * Compression Types + */ +#define IH_COMP_NONE 0 /* No Compression Used */ +#define IH_COMP_GZIP 1 /* gzip Compression Used */ +#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */ + +#define IH_MAGIC 0x27051956 /* Image Magic Number */ +#define IH_NMLEN 32 /* Image Name Length */ + +/* + * all data in network byte order (aka natural aka bigendian) + */ + +typedef struct image_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +} image_header_t; + + +#endif /* __IMAGE_H__ */ diff --git a/include/ioports.h b/include/ioports.h new file mode 100644 index 0000000..d7e19e1 --- /dev/null +++ b/include/ioports.h @@ -0,0 +1,55 @@ +/* + * definitions for MPC8260 I/O Ports + * + * (in addition to those provided in ) + * + * Murray.Jensen@cmst.csiro.au, 20-Oct-00 + */ + +/* + * this structure mirrors the layout of the five port registers in + * the internal memory map - see iop8260_t in + */ +typedef struct { + unsigned int pdir; /* Port Data Direction Register (35-3) */ + unsigned int ppar; /* Port Pin Assignment Register (35-4) */ + unsigned int psor; /* Port Special Options Register (35-5) */ + unsigned int podr; /* Port Open Drain Register (35-2) */ + unsigned int pdat; /* Port Data Register (35-3) */ +} ioport_t; + +/* + * this macro calculates the address within the internal + * memory map (im) of the set of registers for a port (idx) + * + * the internal memory map aligns the above structure on + * a 0x20 byte boundary + */ +#ifdef CONFIG_MPC85xx +#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20)) +#else +#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) +#endif + +/* + * this structure provides configuration + * information for one port pin + */ +typedef struct { + unsigned char conf:1; /* if 1, configure this port */ + unsigned char ppar:1; /* Port Pin Assignment Register (35-4) */ + unsigned char psor:1; /* Port Special Options Register (35-2) */ + unsigned char pdir:1; /* Port Data Direction Register (35-3) */ + unsigned char podr:1; /* Port Open Drain Register (35-2) */ + unsigned char pdat:1; /* Port Data Register (35-2) */ +} iop_conf_t; + +/* + * a table that contains configuration information for all 32 pins + * of all four MPC8260 I/O ports. + * + * NOTE: in the second dimension of this table, index 0 refers to pin 31 + * and index 31 refers to pin 0. this made the code in the table look more + * like the table in the 8260UM (and in the hymod manuals). + */ +extern const iop_conf_t iop_conf_tab[4][32]; diff --git a/include/jffs2/compr_rubin.h b/include/jffs2/compr_rubin.h new file mode 100644 index 0000000..f26f476 --- /dev/null +++ b/include/jffs2/compr_rubin.h @@ -0,0 +1,11 @@ +/* Rubin encoder/decoder header */ +/* work started at : aug 3, 1994 */ +/* last modification : aug 15, 1994 */ +/* $Id: compr_rubin.h,v 1.1 2002/01/16 23:34:32 nyet Exp $ */ + +#define RUBIN_REG_SIZE 16 +#define UPPER_BIT_RUBIN (((long) 1)<<(RUBIN_REG_SIZE-1)) +#define LOWER_BITS_RUBIN ((((long) 1)<<(RUBIN_REG_SIZE-1))-1) + +void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, + unsigned long sourcelen, unsigned long dstlen); diff --git a/include/jffs2/jffs2.h b/include/jffs2/jffs2.h new file mode 100644 index 0000000..d142cd1 --- /dev/null +++ b/include/jffs2/jffs2.h @@ -0,0 +1,218 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by David Woodhouse + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: jffs2.h,v 1.2 2002/01/17 00:53:20 nyet Exp $ + * + */ + +#ifndef __LINUX_JFFS2_H__ +#define __LINUX_JFFS2_H__ + +#include +#include + +#define JFFS2_SUPER_MAGIC 0x72b6 + +/* Values we may expect to find in the 'magic' field */ +#define JFFS2_OLD_MAGIC_BITMASK 0x1984 +#define JFFS2_MAGIC_BITMASK 0x1985 +#define KSAMTIB_CIGAM_2SFFJ 0x5981 /* For detecting wrong-endian fs */ +#define JFFS2_EMPTY_BITMASK 0xffff +#define JFFS2_DIRTY_BITMASK 0x0000 + +/* We only allow a single char for length, and 0xFF is empty flash so + we don't want it confused with a real length. Hence max 254. +*/ +#define JFFS2_MAX_NAME_LEN 254 + +/* How small can we sensibly write nodes? */ +#define JFFS2_MIN_DATA_LEN 128 + +#define JFFS2_COMPR_NONE 0x00 +#define JFFS2_COMPR_ZERO 0x01 +#define JFFS2_COMPR_RTIME 0x02 +#define JFFS2_COMPR_RUBINMIPS 0x03 +#define JFFS2_COMPR_COPY 0x04 +#define JFFS2_COMPR_DYNRUBIN 0x05 +#define JFFS2_COMPR_ZLIB 0x06 +#if defined(CONFIG_JFFS2_LZO_LZARI) +#define JFFS2_COMPR_LZO 0x07 +#define JFFS2_COMPR_LZARI 0x08 +#define JFFS2_NUM_COMPR 9 +#else +#define JFFS2_NUM_COMPR 7 +#endif + +/* Compatibility flags. */ +#define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */ +#define JFFS2_NODE_ACCURATE 0x2000 +/* INCOMPAT: Fail to mount the filesystem */ +#define JFFS2_FEATURE_INCOMPAT 0xc000 +/* ROCOMPAT: Mount read-only */ +#define JFFS2_FEATURE_ROCOMPAT 0x8000 +/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */ +#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000 +/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */ +#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000 + +#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1) +#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2) +#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) +#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4) + +/* Maybe later... */ +/*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */ +/*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */ + +/* Same as the non_ECC versions, but with extra space for real + * ECC instead of just the checksum. For use on NAND flash + */ +/*#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5) */ +/*#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6) */ + +#define JFFS2_INO_FLAG_PREREAD 1 /* Do read_inode() for this one at + mount time, don't wait for it to + happen later */ +#define JFFS2_INO_FLAG_USERCOMPR 2 /* User has requested a specific + compression type */ + + +struct jffs2_unknown_node +{ + /* All start like this */ + __u16 magic; + __u16 nodetype; + __u32 totlen; /* So we can skip over nodes we don't grok */ + __u32 hdr_crc; +} __attribute__((packed)); + +struct jffs2_raw_dirent +{ + __u16 magic; + __u16 nodetype; /* == JFFS_NODETYPE_DIRENT */ + __u32 totlen; + __u32 hdr_crc; + __u32 pino; + __u32 version; + __u32 ino; /* == zero for unlink */ + __u32 mctime; + __u8 nsize; + __u8 type; + __u8 unused[2]; + __u32 node_crc; + __u32 name_crc; + __u8 name[0]; +} __attribute__((packed)); + +/* The JFFS2 raw inode structure: Used for storage on physical media. */ +/* The uid, gid, atime, mtime and ctime members could be longer, but + are left like this for space efficiency. If and when people decide + they really need them extended, it's simple enough to add support for + a new type of raw node. +*/ +struct jffs2_raw_inode +{ + __u16 magic; /* A constant magic number. */ + __u16 nodetype; /* == JFFS_NODETYPE_INODE */ + __u32 totlen; /* Total length of this node (inc data, etc.) */ + __u32 hdr_crc; + __u32 ino; /* Inode number. */ + __u32 version; /* Version number. */ + __u32 mode; /* The file's type or mode. */ + __u16 uid; /* The file's owner. */ + __u16 gid; /* The file's group. */ + __u32 isize; /* Total resultant size of this inode (used for truncations) */ + __u32 atime; /* Last access time. */ + __u32 mtime; /* Last modification time. */ + __u32 ctime; /* Change time. */ + __u32 offset; /* Where to begin to write. */ + __u32 csize; /* (Compressed) data size */ + __u32 dsize; /* Size of the node's data. (after decompression) */ + __u8 compr; /* Compression algorithm used */ + __u8 usercompr; /* Compression algorithm requested by the user */ + __u16 flags; /* See JFFS2_INO_FLAG_* */ + __u32 data_crc; /* CRC for the (compressed) data. */ + __u32 node_crc; /* CRC for the raw inode (excluding data) */ +/* __u8 data[dsize]; */ +} __attribute__((packed)); + +union jffs2_node_union { + struct jffs2_raw_inode i; + struct jffs2_raw_dirent d; + struct jffs2_unknown_node u; +} __attribute__((packed)); + +enum + { + DT_UNKNOWN = 0, +# define DT_UNKNOWN DT_UNKNOWN + DT_FIFO = 1, +# define DT_FIFO DT_FIFO + DT_CHR = 2, +# define DT_CHR DT_CHR + DT_DIR = 4, +# define DT_DIR DT_DIR + DT_BLK = 6, +# define DT_BLK DT_BLK + DT_REG = 8, +# define DT_REG DT_REG + DT_LNK = 10, +# define DT_LNK DT_LNK + DT_SOCK = 12, +# define DT_SOCK DT_SOCK + DT_WHT = 14 +# define DT_WHT DT_WHT + }; + + +u32 jffs2_1pass_ls(struct part_info *part,const char *fname); +u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname); +u32 jffs2_1pass_info(struct part_info *part); + +void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen); +void rubin_do_decompress(unsigned char *bits, unsigned char *in, + unsigned char *page_out, __u32 destlen); +void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, + unsigned long sourcelen, unsigned long dstlen); +long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, + __u32 srclen, __u32 destlen); +#if defined(CONFIG_JFFS2_LZO_LZARI) +int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen); +int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen); +#endif + +char *mkmodestr(unsigned long mode, char *str); +#endif /* __LINUX_JFFS2_H__ */ diff --git a/include/jffs2/jffs2_1pass.h b/include/jffs2/jffs2_1pass.h new file mode 100644 index 0000000..5bc3e66 --- /dev/null +++ b/include/jffs2/jffs2_1pass.h @@ -0,0 +1,3 @@ +u32 jffs2_1pass_ls(struct part_info *part,const char *fname); +u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname); +u32 jffs2_1pass_info(struct part_info *part); diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h new file mode 100644 index 0000000..882a80e --- /dev/null +++ b/include/jffs2/load_kernel.h @@ -0,0 +1,73 @@ +#ifndef load_kernel_h +#define load_kernel_h +/*------------------------------------------------------------------------- + * Filename: load_kernel.h + * Version: $Id: load_kernel.h,v 1.3 2002/01/25 01:34:11 nyet Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: header for load kernel modules + *-----------------------------------------------------------------------*/ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +/* mtd device types */ +#define MTD_DEV_TYPE_NOR 0x0001 +#define MTD_DEV_TYPE_NAND 0x0002 +#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" : "nor") + +struct mtd_device { + struct list_head link; + struct mtdids *id; /* parent mtd id entry */ + u16 num_parts; /* number of partitions on this device */ + struct list_head parts; /* partitions */ +}; + +struct part_info { + struct list_head link; + char *name; /* partition name */ + u8 auto_name; /* set to 1 for generated name */ + u32 size; /* total size of the partition */ + u32 offset; /* offset within device */ + void *jffs2_priv; /* used internaly by jffs2 */ + u32 mask_flags; /* kernel MTD mask flags */ + struct mtd_device *dev; /* parent device */ +}; + +struct mtdids { + struct list_head link; + u8 type; /* device type */ + u8 num; /* device number */ + u32 size; /* device size */ + char *mtd_id; /* linux kernel device id */ +}; + +#define ldr_strlen strlen +#define ldr_strncmp strncmp +#define ldr_memcpy memcpy +#define putstr(x) printf("%s", x) +#define mmalloc malloc +#define UDEBUG printf + +#define putnstr(str, size) printf("%*.*s", size, size, str) +#define ldr_output_string(x) puts(x) +#define putLabeledWord(x, y) printf("%s %08x\n", x, (unsigned int)y) +#define led_blink(x, y, z, a) + +#endif /* load_kernel_h */ diff --git a/include/jffs2/mini_inflate.h b/include/jffs2/mini_inflate.h new file mode 100644 index 0000000..f79aac7 --- /dev/null +++ b/include/jffs2/mini_inflate.h @@ -0,0 +1,82 @@ +/*------------------------------------------------------------------------- + * Filename: mini_inflate.h + * Version: $Id: mini_inflate.h,v 1.2 2002/01/17 00:53:20 nyet Exp $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: Mini deflate implementation + *-----------------------------------------------------------------------*/ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +typedef __SIZE_TYPE__ size; + +#define NO_ERROR 0 +#define COMP_UNKNOWN 1 /* The specififed bytype is invalid */ +#define CODE_NOT_FOUND 2 /* a huffman code in the stream could not be decoded */ +#define TOO_MANY_BITS 3 /* pull_bits was passed an argument that is too + * large */ + +/* This struct represents an entire huffman code set. It has various lookup + * tables to speed decoding */ +struct huffman_set { + int bits; /* maximum bit length */ + int num_symbols; /* Number of symbols this code can represent */ + int *lengths; /* The bit length of symbols */ + int *symbols; /* All of the symbols, sorted by the huffman code */ + int *count; /* the number of codes of this bit length */ + int *first; /* the first code of this bit length */ + int *pos; /* the symbol that first represents (in the symbols + * array) */ +}; + +struct bitstream { + unsigned char *data; /* increments as we move from byte to byte */ + unsigned char bit; /* 0 to 7 */ + void *(*memcpy)(void *, const void *, size); + unsigned long decoded; /* The number of bytes decoded */ + int error; + + int distance_count[16]; + int distance_first[16]; + int distance_pos[16]; + int distance_lengths[32]; + int distance_symbols[32]; + + int code_count[8]; + int code_first[8]; + int code_pos[8]; + int code_lengths[19]; + int code_symbols[19]; + + int length_count[16]; + int length_first[16]; + int length_pos[16]; + int length_lengths[288]; + int length_symbols[288]; + + struct huffman_set codes; + struct huffman_set lengths; + struct huffman_set distance; +}; + +#define NO_COMP 0 +#define FIXED_COMP 1 +#define DYNAMIC_COMP 2 + +long decompress_block(unsigned char *dest, unsigned char *source, + void *(*inflate_memcpy)(void *dest, const void *src, size n)); diff --git a/include/keyboard.h b/include/keyboard.h new file mode 100644 index 0000000..88ae12b --- /dev/null +++ b/include/keyboard.h @@ -0,0 +1,22 @@ +#ifndef __KEYBOARD_H +#define __KEYBOARD_H + +#ifdef CONFIG_PS2MULT +#include +#endif + +#if !defined(kbd_request_region) || \ + !defined(kbd_request_irq) || \ + !defined(kbd_read_input) || \ + !defined(kbd_read_status) || \ + !defined(kbd_write_output) || \ + !defined(kbd_write_command) +#error PS/2 low level routines not defined +#endif + +extern int kbd_init (void); +extern void handle_scancode(unsigned char scancode); +extern int kbd_init_hw(void); +extern void pckbd_leds(unsigned char leds); + +#endif /* __KEYBOARD_H */ diff --git a/include/kgdb.h b/include/kgdb.h new file mode 100644 index 0000000..f543cd6 --- /dev/null +++ b/include/kgdb.h @@ -0,0 +1,70 @@ +#ifndef __KGDB_H__ +#define __KGDB_H__ + +#include + +#define KGDBERR_BADPARAMS 1 +#define KGDBERR_NOTHEXDIG 2 +#define KGDBERR_MEMFAULT 3 +#define KGDBERR_NOSPACE 4 +#define KGDBERR_ALIGNFAULT 5 + +#define KGDBDATA_MAXREGS 8 +#define KGDBDATA_MAXPRIV 8 + +#define KGDBEXIT_TYPEMASK 0xff + +#define KGDBEXIT_KILL 0 +#define KGDBEXIT_CONTINUE 1 +#define KGDBEXIT_SINGLE 2 + +#define KGDBEXIT_WITHADDR 0x100 + +typedef + struct { + int num; + unsigned long val; + } +kgdb_reg; + +typedef + struct { + int sigval; + int extype; + unsigned long exaddr; + int nregs; + kgdb_reg regs[KGDBDATA_MAXREGS]; + unsigned long private[KGDBDATA_MAXPRIV]; + } +kgdb_data; + +/* these functions are provided by the generic kgdb support */ +extern void kgdb_init(void); +extern void kgdb_error(int); +extern int kgdb_output_string(const char *, unsigned int); +extern void breakpoint(void); + +/* these functions are provided by the platform specific kgdb support */ +extern void kgdb_flush_cache_range(void *, void *); +extern void kgdb_flush_cache_all(void); +extern int kgdb_setjmp(long *); +extern void kgdb_longjmp(long *, int); +extern void kgdb_enter(struct pt_regs *, kgdb_data *); +extern void kgdb_exit(struct pt_regs *, kgdb_data *); +extern int kgdb_getregs(struct pt_regs *, char *, int); +extern void kgdb_putreg(struct pt_regs *, int, char *, int); +extern void kgdb_putregs(struct pt_regs *, char *, int); +extern int kgdb_trap(struct pt_regs *); +extern void kgdb_breakpoint(int argc, char *argv[]); + +/* these functions are provided by the platform serial driver */ +extern void kgdb_serial_init(void); +extern int getDebugChar(void); +extern void putDebugChar(int); +extern void putDebugStr(const char *); +extern void kgdb_interruptible(int); + +/* this is referenced in the trap handler for the platform */ +extern int (*debugger_exception_handler)(struct pt_regs *); + +#endif /* __KGDB_H__ */ diff --git a/include/lcd.h b/include/lcd.h new file mode 100644 index 0000000..7e23736 --- /dev/null +++ b/include/lcd.h @@ -0,0 +1,283 @@ +/* + * MPC823 and PXA LCD Controller + * + * Modeled after video interface by Paolo Scaffardi + * + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _LCD_H_ +#define _LCD_H_ + +extern char lcd_is_enabled; + +extern int lcd_line_length; +extern int lcd_color_fg; +extern int lcd_color_bg; + +/* + * Frame buffer memory information + */ +extern void *lcd_base; /* Start of framebuffer memory */ +extern void *lcd_console_address; /* Start of console buffer */ + +extern short console_col; +extern short console_row; + +#if defined CONFIG_MPC823 +/* + * LCD controller stucture for MPC823 CPU + */ +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ + u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ + u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ + u_char vl_clor; /* Color, 0 = mono, 1 = color */ + u_char vl_tft; /* 0 = passive, 1 = TFT */ + + /* Horizontal control register. Timing from data sheet */ + ushort vl_wbl; /* Wait between lines */ + + /* Vertical control register */ + u_char vl_vpw; /* Vertical sync pulse width */ + u_char vl_lcdac; /* LCD AC timing */ + u_char vl_wbf; /* Wait between frames */ +} vidinfo_t; + +extern vidinfo_t panel_info; + +#elif defined CONFIG_PXA250 +/* + * PXA LCD DMA descriptor + */ +struct pxafb_dma_descriptor { + u_long fdadr; /* Frame descriptor address register */ + u_long fsadr; /* Frame source address register */ + u_long fidr; /* Frame ID register */ + u_long ldcmd; /* Command register */ +}; + +/* + * PXA LCD info + */ +struct pxafb_info { + + /* Misc registers */ + u_long reg_lccr3; + u_long reg_lccr2; + u_long reg_lccr1; + u_long reg_lccr0; + u_long fdadr0; + u_long fdadr1; + + /* DMA descriptors */ + struct pxafb_dma_descriptor * dmadesc_fblow; + struct pxafb_dma_descriptor * dmadesc_fbhigh; + struct pxafb_dma_descriptor * dmadesc_palette; + + u_long screen; /* physical address of frame buffer */ + u_long palette; /* physical address of palette memory */ + u_int palette_size; +}; + +/* + * LCD controller stucture for PXA CPU + */ +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ + u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ + u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ + u_char vl_clor; /* Color, 0 = mono, 1 = color */ + u_char vl_tft; /* 0 = passive, 1 = TFT */ + + /* Horizontal control register. Timing from data sheet */ + ushort vl_hpw; /* Horz sync pulse width */ + u_char vl_blw; /* Wait before of line */ + u_char vl_elw; /* Wait end of line */ + + /* Vertical control register. */ + u_char vl_vpw; /* Vertical sync pulse width */ + u_char vl_bfw; /* Wait before of frame */ + u_char vl_efw; /* Wait end of frame */ + + /* PXA LCD controller params */ + struct pxafb_info pxa; +} vidinfo_t; + +extern vidinfo_t panel_info; + +#endif /* CONFIG_MPC823 or CONFIG_PXA250 */ + +/* Video functions */ + +#if defined(CONFIG_RBC823) +void lcd_disable (void); +#endif + + +/* int lcd_init (void *lcdbase); */ +void lcd_putc (const char c); +void lcd_puts (const char *s); +void lcd_printf (const char *fmt, ...); + + +/************************************************************************/ +/* ** BITMAP DISPLAY SUPPORT */ +/************************************************************************/ +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +# include +# include +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ + +/* + * Information about displays we are using. This is for configuring + * the LCD controller and memory allocation. Someone has to know what + * is connected, as we can't autodetect anything. + */ +#define CFG_HIGH 0 /* Pins are active high */ +#define CFG_LOW 1 /* Pins are active low */ + +#define LCD_MONOCHROME 0 +#define LCD_COLOR2 1 +#define LCD_COLOR4 2 +#define LCD_COLOR8 3 +#define LCD_COLOR16 4 + +/*----------------------------------------------------------------------*/ +#if defined(CONFIG_LCD_INFO_BELOW_LOGO) +# define LCD_INFO_X 0 +# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) +#elif defined(CONFIG_LCD_LOGO) +# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) +# define LCD_INFO_Y (VIDEO_FONT_HEIGHT) +#else +# define LCD_INFO_X (VIDEO_FONT_WIDTH) +# define LCD_INFO_Y (VIDEO_FONT_HEIGHT) +#endif + +/* Default to 8bpp if bit depth not specified */ +#ifndef LCD_BPP +# define LCD_BPP LCD_COLOR8 +#endif +#ifndef LCD_DF +# define LCD_DF 1 +#endif + +/* Calculate nr. of bits per pixel and nr. of colors */ +#define NBITS(bit_code) (1 << (bit_code)) +#define NCOLORS(bit_code) (1 << NBITS(bit_code)) + +/************************************************************************/ +/* ** CONSOLE CONSTANTS */ +/************************************************************************/ +#if LCD_BPP == LCD_MONOCHROME + +/* + * Simple black/white definitions + */ +# define CONSOLE_COLOR_BLACK 0 +# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */ + +#elif LCD_BPP == LCD_COLOR8 + +/* + * 8bpp color definitions + */ +# define CONSOLE_COLOR_BLACK 0 +# define CONSOLE_COLOR_RED 1 +# define CONSOLE_COLOR_GREEN 2 +# define CONSOLE_COLOR_YELLOW 3 +# define CONSOLE_COLOR_BLUE 4 +# define CONSOLE_COLOR_MAGENTA 5 +# define CONSOLE_COLOR_CYAN 6 +# define CONSOLE_COLOR_GREY 14 +# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ + +#else + +/* + * 16bpp color definitions + */ +# define CONSOLE_COLOR_BLACK 0x0000 +# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ + +#endif /* color definitions */ + +/************************************************************************/ +#ifndef PAGE_SIZE +# define PAGE_SIZE 4096 +#endif + +/************************************************************************/ +/* ** CONSOLE DEFINITIONS & FUNCTIONS */ +/************************************************************************/ +#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) +# define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \ + / VIDEO_FONT_HEIGHT) +#else +# define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT) +#endif + +#define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) +#define CONSOLE_ROW_FIRST (lcd_console_address) +#define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE) +#define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \ + - CONSOLE_ROW_SIZE) +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) +#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) + +#if LCD_BPP == LCD_MONOCHROME +# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ + (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) +#elif LCD_BPP == LCD_COLOR8 +# define COLOR_MASK(c) (c) +#else +# error Unsupported LCD BPP. +#endif + +/************************************************************************/ + +#endif /* _LCD_H_ */ diff --git a/include/lcdvideo.h b/include/lcdvideo.h new file mode 100644 index 0000000..f0640a5 --- /dev/null +++ b/include/lcdvideo.h @@ -0,0 +1,69 @@ +/* + * MPC823 LCD and Video Controller + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + */ +#ifndef __LCDVIDEO_H__ +#define __LCDVIDEO_H__ + + +/* LCD Controller Configuration Register. +*/ +#define LCCR_BNUM ((uint)0xfffe0000) +#define LCCR_EIEN ((uint)0x00010000) +#define LCCR_IEN ((uint)0x00008000) +#define LCCR_IRQL ((uint)0x00007000) +#define LCCR_CLKP ((uint)0x00000800) +#define LCCR_OEP ((uint)0x00000400) +#define LCCR_HSP ((uint)0x00000200) +#define LCCR_VSP ((uint)0x00000100) +#define LCCR_DP ((uint)0x00000080) +#define LCCR_BPIX ((uint)0x00000060) +#define LCCR_LBW ((uint)0x00000010) +#define LCCR_SPLT ((uint)0x00000008) +#define LCCR_CLOR ((uint)0x00000004) +#define LCCR_TFT ((uint)0x00000002) +#define LCCR_PON ((uint)0x00000001) + +/* Define the bit shifts to load values into the register. +*/ +#define LCDBIT(BIT, VAL) ((VAL) << (31 - BIT)) + +#define LCCR_BNUM_BIT ((uint)14) +#define LCCR_EIEN_BIT ((uint)15) +#define LCCR_IEN_BIT ((uint)16) +#define LCCR_IROL_BIT ((uint)19) +#define LCCR_CLKP_BIT ((uint)20) +#define LCCR_OEP_BIT ((uint)21) +#define LCCR_HSP_BIT ((uint)22) +#define LCCR_VSP_BIT ((uint)23) +#define LCCR_DP_BIT ((uint)24) +#define LCCR_BPIX_BIT ((uint)26) +#define LCCR_LBW_BIT ((uint)27) +#define LCCR_SPLT_BIT ((uint)28) +#define LCCR_CLOR_BIT ((uint)29) +#define LCCR_TFT_BIT ((uint)30) +#define LCCR_PON_BIT ((uint)31) + +/* LCD Horizontal control register. +*/ +#define LCHCR_BO ((uint)0x01000000) +#define LCHCR_AT ((uint)0x00e00000) +#define LCHCR_HPC ((uint)0x001ffc00) +#define LCHCR_WBL ((uint)0x000003ff) + +#define LCHCR_AT_BIT ((uint)10) +#define LCHCR_HPC_BIT ((uint)21) +#define LCHCR_WBL_BIT ((uint)31) + +/* LCD Vertical control register. +*/ +#define LCVCR_VPW ((uint)0xf0000000) +#define LCVCR_LCD_AC ((uint)0x01e00000) +#define LCVCR_VPC ((uint)0x001ff800) +#define LCVCR_WBF ((uint)0x000003ff) + +#define LCVCR_VPW_BIT ((uint)3) +#define LCVCR_LCD_AC_BIT ((uint)10) +#define LCVCR_VPC_BIT ((uint)20) + +#endif /* __LCDVIDEO_H__ */ diff --git a/include/lh7a400.h b/include/lh7a400.h new file mode 100644 index 0000000..d1e70a2 --- /dev/null +++ b/include/lh7a400.h @@ -0,0 +1,75 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * lh7a400 SoC interface + */ + +#ifndef __LH7A400_H__ +#define __LH7A400_H__ + +#include "lh7a40x.h" + +/* Interrupt Controller (userguide 8.2.1) */ +typedef struct { + volatile u32 intsr; + volatile u32 intrsr; + volatile u32 intens; + volatile u32 intenc; + volatile u32 rsvd1; + volatile u32 rsvd2; + volatile u32 rsvd3; +} /*__attribute__((__packed__))*/ lh7a400_interrupt_t; +#define LH7A400_INTERRUPT_BASE (0x80000500) +#define LH7A400_INTERRUPT_PTR ((lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE) + +/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */ +typedef struct { + lh7a40x_dmachan_t chan[15]; + volatile u32 glblint; + volatile u32 rsvd1; + volatile u32 rsvd2; + volatile u32 rsvd3; +} /*__attribute__((__packed__))*/ lh7a400_dma_t; + +#define LH7A400_DMA_BASE (0x80002800) +#define DMA_USBTX_OFFSET (0x000) +#define DMA_USBRX_OFFSET (0x040) +#define DMA_MMCTX_OFFSET (0x080) +#define DMA_MMCRX_OFFSET (0x0C0) +#define DMA_AC97_BASE (0x80002A00) + +#define LH7A400_DMA_PTR ((lh7a400_dma_t*) LH7A400_DMA_BASE) +#define LH7A400_DMA_USBTX \ + ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET)) +#define LH7A400_DMA_USBRX \ + ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET)) +#define LH7A400_DMA_MMCTX \ + ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET)) +#define LH7A400_DMA_MMCRX \ + ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET)) +#define LH7A400_AC97RX(n) \ + ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \ + ((2*n) * sizeof(lh7a400_dmachan_t)))) +#define LH7A400_AC97TX(n) \ + ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \ + (((2*n)+1) * sizeof(lh7a400_dmachan_t)))) + +#endif /* __LH7A400_H__ */ diff --git a/include/lh7a404.h b/include/lh7a404.h new file mode 100644 index 0000000..4098af3 --- /dev/null +++ b/include/lh7a404.h @@ -0,0 +1,83 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * lh7a404 SoC interface + */ + +#ifndef __LH7A404_H__ +#define __LH7A404_H__ + +#include "lh7a40x.h" + +/* Interrupt Controller (userguide 8.2.1) */ +typedef struct { + volatile u32 irqstatus; + volatile u32 fiqstatus; + volatile u32 rawintr; + volatile u32 intsel; + volatile u32 inten; + volatile u32 intenclr; + volatile u32 softint; + volatile u32 softintclr; + volatile u32 protect; + volatile u32 unused1; + volatile u32 unused2; + volatile u32 vectaddr; + volatile u32 nvaddr; + volatile u32 unused3[32]; + volatile u32 vad[16]; + volatile u32 unused4[44]; + volatile u32 vectcntl[16]; + volatile u32 unused5[44]; + volatile u32 itcr; + volatile u32 itip1; + volatile u32 itip2; + volatile u32 itop1; + volatile u32 itop2; + volatile u32 unused6[333]; + volatile u32 periphid[4]; + volatile u32 pcellid[4]; +} /*__attribute__((__packed__))*/ lh7a404_vic_t; +#define LH7A404_VIC_BASE (0x80008000) +#define LH7A400_VIC_PTR(x) ((lh7a404_vic_t*)(LH7A400_VIC_BASE + (x*0x2000))) + + +typedef struct { + lh7a40x_dmachan_t m2p0_tx; + lh7a40x_dmachan_t m2p1_rx; + lh7a40x_dmachan_t m2p2_tx; + lh7a40x_dmachan_t m2p3_rx; + lh7a40x_dmachan_t m2m0; + lh7a40x_dmachan_t m2m1; + lh7a40x_dmachan_t unused1; + lh7a40x_dmachan_t unused2; + lh7a40x_dmachan_t m2p5_rx; + lh7a40x_dmachan_t m2p4_tx; + lh7a40x_dmachan_t m2p7_rx; + lh7a40x_dmachan_t m2p6_tx; + lh7a40x_dmachan_t m2p9_rx; + lh7a40x_dmachan_t m2p8_tx; + volatile u32 chanarb; + volatile u32 glblint; +} /*__attribute__((__packed__))*/ lh7a400_dma_t; + + +#endif /* __LH7A404_H__ */ diff --git a/include/lh7a40x.h b/include/lh7a40x.h new file mode 100644 index 0000000..c897a7c --- /dev/null +++ b/include/lh7a40x.h @@ -0,0 +1,279 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * lh7a40x SoC series common interface + */ + +#ifndef __LH7A40X_H__ +#define __LH7A40X_H__ + +/* (SMC) Static Memory Controller (usersguide 4.2.1) */ +typedef struct { + volatile u32 attib; + volatile u32 com; + volatile u32 io; + volatile u32 rsvd1; +} /*__attribute__((__packed__))*/ lh7a40x_pccard_t; + +typedef struct { + volatile u32 bcr[8]; + lh7a40x_pccard_t pccard[2]; + volatile u32 pcmciacon; +} /*__attribute__((__packed__))*/ lh7a40x_smc_t; +#define LH7A40X_SMC_BASE (0x80002000) +#define LH7A40X_SMC_PTR ((lh7a40x_smc_t*) LH7A40X_SMC_BASE) + +/* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */ +typedef struct { + volatile u32 rsvd1; + volatile u32 gblcnfg; + volatile u32 rfshtmr; + volatile u32 bootstat; + volatile u32 sdcsc[4]; +} /*__attribute__((__packed__))*/ lh7a40x_sdmc_t; +#define LH7A40X_SDMC_BASE (0x80002400) +#define LH7A40X_SDMC_PTR ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE) + +/* (CSC) Clock and State Controller (userguide 6.2.1) */ +typedef struct { + volatile u32 pwrsr; + volatile u32 pwrcnt; + volatile u32 halt; + volatile u32 stby; + volatile u32 bleoi; + volatile u32 mceoi; + volatile u32 teoi; + volatile u32 stfclr; + volatile u32 clkset; + volatile u32 scrreg[2]; + volatile u32 rsvd1; + volatile u32 usbreset; +} /*__attribute__((__packed__))*/ lh7a40x_csc_t; +#define LH7A40X_STPWR_BASE (0x80000400) +#define LH7A40X_CSC_PTR ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE) + +#define CLKSET_SMCROM (0x01000000) +#define CLKSET_PS (0x000C0000) +#define CLKSET_PS_0 (0x00000000) +#define CLKSET_PS_1 (0x00040000) +#define CLKSET_PS_2 (0x00080000) +#define CLKSET_PS_3 (0x000C0000) +#define CLKSET_PCLKDIV (0x00030000) +#define CLKSET_PCLKDIV_2 (0x00000000) +#define CLKSET_PCLKDIV_4 (0x00010000) +#define CLKSET_PCLKDIV_8 (0x00020000) +#define CLKSET_MAINDIV2 (0x0000f800) +#define CLKSET_MAINDIV1 (0x00000780) +#define CLKSET_PREDIV (0x0000007C) +#define CLKSET_HCLKDIV (0x00000003) + +/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */ +typedef struct { + volatile u32 maxcnt; + volatile u32 base; + volatile u32 current; + volatile u32 rsvd1; +} lh7a40x_dmabuf_t; + +typedef struct { + volatile u32 control; + volatile u32 interrupt; + volatile u32 rsvd1; + volatile u32 status; + volatile u32 rsvd2; + volatile u32 remain; + volatile u32 rsvd3; + volatile u32 rsvd4; + lh7a40x_dmabuf_t buf[2]; +} /*__attribute__((__packed__))*/ lh7a40x_dmachan_t; + + +/* (WDT) Watchdog Timer (userguide 11.2.1) */ +typedef struct { + volatile u32 ctl; + volatile u32 rst; + volatile u32 status; + volatile u32 count[4]; +} /*__attribute__((__packed__))*/ lh7a40x_wdt_t; +#define LH7A40X_WDT_BASE (0x80001400) +#define LH7A40X_WDT_PTR ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE) + +/* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */ +typedef struct { + volatile u32 rtcdr; + volatile u32 rtclr; + volatile u32 rtcmr; + volatile u32 unk1; + volatile u32 rtcstat_eoi; + volatile u32 rtccr; + volatile u32 rsvd1[58]; +} /*__attribute__((__packed__))*/ lh7a40x_rtc_t; +#define LH7A40X_RTC_BASE (0x80000D00) +#define LH7A40X_RTC_PTR ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE) + +/* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */ +typedef struct { + volatile u32 load; + volatile u32 value; + volatile u32 control; + volatile u32 tceoi; +} /*__attribute__((__packed__))*/ lh7a40x_timer_t; + +typedef struct { + lh7a40x_timer_t timer1; + volatile u32 rsvd1[4]; + lh7a40x_timer_t timer2; + volatile u32 unk1[4]; + volatile u32 bzcon; + volatile u32 unk2[15]; + lh7a40x_timer_t timer3; + /*volatile u32 rsvd2;*/ +} /*__attribute__((__packed__))*/ lh7a40x_timers_t; +#define LH7A40X_TIMERS_BASE (0x80000C00) +#define LH7A40X_TIMERS_PTR ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE) + +#define TIMER_EN (0x00000080) +#define TIMER_PER (0x00000040) +#define TIMER_FREE (0x00000000) +#define TIMER_CLK508K (0x00000008) +#define TIMER_CLK2K (0x00000000) + +/* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */ +typedef struct { + volatile u32 cr0; + volatile u32 cr1; + volatile u32 irr_roeoi; + volatile u32 dr; + volatile u32 cpr; + volatile u32 sr; + /*volatile u32 rsvd1[58];*/ +} /*__attribute__((__packed__))*/ lh7a40x_ssp_t; +#define LH7A40X_SSP_BASE (0x80000B00) +#define LH7A40X_SSP_PTR ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE) + +/* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */ +typedef struct { + volatile u32 data; + volatile u32 fcon; + volatile u32 brcon; + volatile u32 con; + volatile u32 status; + volatile u32 rawisr; + volatile u32 inten; + volatile u32 isr; + volatile u32 rsvd1[56]; +} /*__attribute__((__packed__))*/ lh7a40x_uart_t; +#define LH7A40X_UART_BASE (0x80000600) +#define LH7A40X_UART_PTR(n) \ + ((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t)))) + +#define UART_BE (0x00000800) /* the rx error bits */ +#define UART_OE (0x00000400) +#define UART_PE (0x00000200) +#define UART_FE (0x00000100) + +#define UART_WLEN (0x00000060) /* fcon bits */ +#define UART_WLEN_8 (0x00000060) +#define UART_WLEN_7 (0x00000040) +#define UART_WLEN_6 (0x00000020) +#define UART_WLEN_5 (0x00000000) +#define UART_FEN (0x00000010) +#define UART_STP2 (0x00000008) +#define UART_STP2_2 (0x00000008) +#define UART_STP2_1 (0x00000000) +#define UART_EPS (0x00000004) +#define UART_EPS_EVEN (0x00000004) +#define UART_EPS_ODD (0x00000000) +#define UART_PEN (0x00000002) +#define UART_BRK (0x00000001) + +#define UART_BAUDDIV (0x0000ffff) /* brcon bits */ + +#define UART_SIRBD (0x00000080) /* con bits */ +#define UART_LBE (0x00000040) +#define UART_MXP (0x00000020) +#define UART_TXP (0x00000010) +#define UART_RXP (0x00000008) +#define UART_SIRLP (0x00000004) +#define UART_SIRD (0x00000002) +#define UART_EN (0x00000001) + +#define UART_TXFE (0x00000080) /* status bits */ +#define UART_RXFF (0x00000040) +#define UART_TXFF (0x00000020) +#define UART_RXFE (0x00000010) +#define UART_BUSY (0x00000008) +#define UART_DCD (0x00000004) +#define UART_DSR (0x00000002) +#define UART_CTS (0x00000001) + +#define UART_MSEOI (0xfffffff0) /* rawisr interrupt bits */ + +#define UART_RTI (0x00000008) /* generic interrupt bits */ +#define UART_MI (0x00000004) +#define UART_TI (0x00000002) +#define UART_RI (0x00000001) + +/* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */ +typedef struct { + volatile u32 pad; + volatile u32 pbd; + volatile u32 pcd; + volatile u32 pdd; + volatile u32 padd; + volatile u32 pbdd; + volatile u32 pcdd; + volatile u32 pddd; + volatile u32 ped; + volatile u32 pedd; + volatile u32 kbdctl; + volatile u32 pinmux; + volatile u32 pfd; + volatile u32 pfdd; + volatile u32 pgd; + volatile u32 pgdd; + volatile u32 phd; + volatile u32 phdd; + volatile u32 rsvd1; + volatile u32 inttype1; + volatile u32 inttype2; + volatile u32 gpiofeoi; + volatile u32 gpiointen; + volatile u32 intstatus; + volatile u32 rawintstatus; + volatile u32 gpiodb; + volatile u32 papd; + volatile u32 pbpd; + volatile u32 pcpd; + volatile u32 pdpd; + volatile u32 pepd; + volatile u32 pfpd; + volatile u32 pgpd; + volatile u32 phpd; +} /*__attribute__((__packed__))*/ lh7a40x_gpioint_t; +#define LH7A40X_GPIOINT_BASE (0x80000E00) +#define LH7A40X_GPIOINT_PTR ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE) + +/* Embedded SRAM */ +#define CFG_SRAM_BASE (0xB0000000) +#define CFG_SRAM_SIZE (80*1024) /* 80kB */ + +#endif /* __LH7A40X_H__ */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h new file mode 100644 index 0000000..7d41ae6 --- /dev/null +++ b/include/linux/bitops.h @@ -0,0 +1,72 @@ +#ifndef _LINUX_BITOPS_H +#define _LINUX_BITOPS_H + + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +static inline int generic_ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +static inline unsigned int generic_hweight32(unsigned int w) +{ + unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555); + res = (res & 0x33333333) + ((res >> 2) & 0x33333333); + res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F); + res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF); + return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF); +} + +static inline unsigned int generic_hweight16(unsigned int w) +{ + unsigned int res = (w & 0x5555) + ((w >> 1) & 0x5555); + res = (res & 0x3333) + ((res >> 2) & 0x3333); + res = (res & 0x0F0F) + ((res >> 4) & 0x0F0F); + return (res & 0x00FF) + ((res >> 8) & 0x00FF); +} + +static inline unsigned int generic_hweight8(unsigned int w) +{ + unsigned int res = (w & 0x55) + ((w >> 1) & 0x55); + res = (res & 0x33) + ((res >> 2) & 0x33); + return (res & 0x0F) + ((res >> 4) & 0x0F); +} + +#include + + +#endif diff --git a/include/linux/byteorder/big_endian.h b/include/linux/byteorder/big_endian.h new file mode 100644 index 0000000..19b0c86 --- /dev/null +++ b/include/linux/byteorder/big_endian.h @@ -0,0 +1,69 @@ +#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H +#define _LINUX_BYTEORDER_BIG_ENDIAN_H + +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN 4321 +#endif +#ifndef __BIG_ENDIAN_BITFIELD +#define __BIG_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __BIG_ENDIAN + +#include + +#define __constant_htonl(x) ((__u32)(x)) +#define __constant_ntohl(x) ((__u32)(x)) +#define __constant_htons(x) ((__u16)(x)) +#define __constant_ntohs(x) ((__u16)(x)) +#define __constant_cpu_to_le64(x) ___swab64((x)) +#define __constant_le64_to_cpu(x) ___swab64((x)) +#define __constant_cpu_to_le32(x) ___swab32((x)) +#define __constant_le32_to_cpu(x) ___swab32((x)) +#define __constant_cpu_to_le16(x) ___swab16((x)) +#define __constant_le16_to_cpu(x) ___swab16((x)) +#define __constant_cpu_to_be64(x) ((__u64)(x)) +#define __constant_be64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_be32(x) ((__u32)(x)) +#define __constant_be32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_be16(x) ((__u16)(x)) +#define __constant_be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64(x) __swab64((x)) +#define __le64_to_cpu(x) __swab64((x)) +#define __cpu_to_le32(x) __swab32((x)) +#define __le32_to_cpu(x) __swab32((x)) +#define __cpu_to_le16(x) __swab16((x)) +#define __le16_to_cpu(x) __swab16((x)) +#define __cpu_to_be64(x) ((__u64)(x)) +#define __be64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_be32(x) ((__u32)(x)) +#define __be32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_be16(x) ((__u16)(x)) +#define __be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64p(x) __swab64p((x)) +#define __le64_to_cpup(x) __swab64p((x)) +#define __cpu_to_le32p(x) __swab32p((x)) +#define __le32_to_cpup(x) __swab32p((x)) +#define __cpu_to_le16p(x) __swab16p((x)) +#define __le16_to_cpup(x) __swab16p((x)) +#define __cpu_to_be64p(x) (*(__u64*)(x)) +#define __be64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_be32p(x) (*(__u32*)(x)) +#define __be32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_be16p(x) (*(__u16*)(x)) +#define __be16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_le64s(x) __swab64s((x)) +#define __le64_to_cpus(x) __swab64s((x)) +#define __cpu_to_le32s(x) __swab32s((x)) +#define __le32_to_cpus(x) __swab32s((x)) +#define __cpu_to_le16s(x) __swab16s((x)) +#define __le16_to_cpus(x) __swab16s((x)) +#define __cpu_to_be64s(x) do {} while (0) +#define __be64_to_cpus(x) do {} while (0) +#define __cpu_to_be32s(x) do {} while (0) +#define __be32_to_cpus(x) do {} while (0) +#define __cpu_to_be16s(x) do {} while (0) +#define __be16_to_cpus(x) do {} while (0) + +#include + +#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/generic.h new file mode 100644 index 0000000..cff850f --- /dev/null +++ b/include/linux/byteorder/generic.h @@ -0,0 +1,180 @@ +#ifndef _LINUX_BYTEORDER_GENERIC_H +#define _LINUX_BYTEORDER_GENERIC_H + +/* + * linux/byteorder_generic.h + * Generic Byte-reordering support + * + * Francois-Rene Rideau 19970707 + * gathered all the good ideas from all asm-foo/byteorder.h into one file, + * cleaned them up. + * I hope it is compliant with non-GCC compilers. + * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, + * because I wasn't sure it would be ok to put it in types.h + * Upgraded it to 2.1.43 + * Francois-Rene Rideau 19971012 + * Upgraded it to 2.1.57 + * to please Linus T., replaced huge #ifdef's between little/big endian + * by nestedly #include'd files. + * Francois-Rene Rideau 19971205 + * Made it to 2.1.71; now a facelift: + * Put files under include/linux/byteorder/ + * Split swab from generic support. + * + * TODO: + * = Regular kernel maintainers could also replace all these manual + * byteswap macros that remain, disseminated among drivers, + * after some grep or the sources... + * = Linus might want to rename all these macros and files to fit his taste, + * to fit his personal naming scheme. + * = it seems that a few drivers would also appreciate + * nybble swapping support... + * = every architecture could add their byteswap macro in asm/byteorder.h + * see how some architectures already do (i386, alpha, ppc, etc) + * = cpu_to_beXX and beXX_to_cpu might some day need to be well + * distinguished throughout the kernel. This is not the case currently, + * since little endian, big endian, and pdp endian machines needn't it. + * But this might be the case for, say, a port of Linux to 20/21 bit + * architectures (and F21 Linux addict around?). + */ + +/* + * The following macros are to be defined by : + * + * Conversion of long and short int between network and host format + * ntohl(__u32 x) + * ntohs(__u16 x) + * htonl(__u32 x) + * htons(__u16 x) + * It seems that some programs (which? where? or perhaps a standard? POSIX?) + * might like the above to be functions, not macros (why?). + * if that's true, then detect them, and take measures. + * Anyway, the measure is: define only ___ntohl as a macro instead, + * and in a separate file, have + * unsigned long inline ntohl(x){return ___ntohl(x);} + * + * The same for constant arguments + * __constant_ntohl(__u32 x) + * __constant_ntohs(__u16 x) + * __constant_htonl(__u32 x) + * __constant_htons(__u16 x) + * + * Conversion of XX-bit integers (16- 32- or 64-) + * between native CPU format and little/big endian format + * 64-bit stuff only defined for proper architectures + * cpu_to_[bl]eXX(__uXX x) + * [bl]eXX_to_cpu(__uXX x) + * + * The same, but takes a pointer to the value to convert + * cpu_to_[bl]eXXp(__uXX x) + * [bl]eXX_to_cpup(__uXX x) + * + * The same, but change in situ + * cpu_to_[bl]eXXs(__uXX x) + * [bl]eXX_to_cpus(__uXX x) + * + * See asm-foo/byteorder.h for examples of how to provide + * architecture-optimized versions + * + */ + + +#if defined(__KERNEL__) +/* + * inside the kernel, we can use nicknames; + * outside of it, we must avoid POSIX namespace pollution... + */ +#define cpu_to_le64 __cpu_to_le64 +#define le64_to_cpu __le64_to_cpu +#define cpu_to_le32 __cpu_to_le32 +#define le32_to_cpu __le32_to_cpu +#define cpu_to_le16 __cpu_to_le16 +#define le16_to_cpu __le16_to_cpu +#define cpu_to_be64 __cpu_to_be64 +#define be64_to_cpu __be64_to_cpu +#define cpu_to_be32 __cpu_to_be32 +#define be32_to_cpu __be32_to_cpu +#define cpu_to_be16 __cpu_to_be16 +#define be16_to_cpu __be16_to_cpu +#define cpu_to_le64p __cpu_to_le64p +#define le64_to_cpup __le64_to_cpup +#define cpu_to_le32p __cpu_to_le32p +#define le32_to_cpup __le32_to_cpup +#define cpu_to_le16p __cpu_to_le16p +#define le16_to_cpup __le16_to_cpup +#define cpu_to_be64p __cpu_to_be64p +#define be64_to_cpup __be64_to_cpup +#define cpu_to_be32p __cpu_to_be32p +#define be32_to_cpup __be32_to_cpup +#define cpu_to_be16p __cpu_to_be16p +#define be16_to_cpup __be16_to_cpup +#define cpu_to_le64s __cpu_to_le64s +#define le64_to_cpus __le64_to_cpus +#define cpu_to_le32s __cpu_to_le32s +#define le32_to_cpus __le32_to_cpus +#define cpu_to_le16s __cpu_to_le16s +#define le16_to_cpus __le16_to_cpus +#define cpu_to_be64s __cpu_to_be64s +#define be64_to_cpus __be64_to_cpus +#define cpu_to_be32s __cpu_to_be32s +#define be32_to_cpus __be32_to_cpus +#define cpu_to_be16s __cpu_to_be16s +#define be16_to_cpus __be16_to_cpus +#endif + + +/* + * Handle ntohl and suches. These have various compatibility + * issues - like we want to give the prototype even though we + * also have a macro for them in case some strange program + * wants to take the address of the thing or something.. + * + * Note that these used to return a "long" in libc5, even though + * long is often 64-bit these days.. Thus the casts. + * + * They have to be macros in order to do the constant folding + * correctly - if the argument passed into a inline function + * it is no longer constant according to gcc.. + */ + +#undef ntohl +#undef ntohs +#undef htonl +#undef htons + +/* + * Do the prototypes. Somebody might want to take the + * address or some such sick thing.. + */ +#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) +extern __u32 ntohl(__u32); +extern __u32 htonl(__u32); +#else +extern unsigned long int ntohl(unsigned long int); +extern unsigned long int htonl(unsigned long int); +#endif +extern unsigned short int ntohs(unsigned short int); +extern unsigned short int htons(unsigned short int); + + +#if defined(__GNUC__) && (__GNUC__ >= 2) + +#define ___htonl(x) __cpu_to_be32(x) +#define ___htons(x) __cpu_to_be16(x) +#define ___ntohl(x) __be32_to_cpu(x) +#define ___ntohs(x) __be16_to_cpu(x) + +#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) +#define htonl(x) ___htonl(x) +#define ntohl(x) ___ntohl(x) +#else +#define htonl(x) ((unsigned long)___htonl(x)) +#define ntohl(x) ((unsigned long)___ntohl(x)) +#endif +#define htons(x) ___htons(x) +#define ntohs(x) ___ntohs(x) + +#endif /* OPTIMIZE */ + + +#endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/include/linux/byteorder/little_endian.h b/include/linux/byteorder/little_endian.h new file mode 100644 index 0000000..a46f3ec --- /dev/null +++ b/include/linux/byteorder/little_endian.h @@ -0,0 +1,69 @@ +#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H +#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H + +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN 1234 +#endif +#ifndef __LITTLE_ENDIAN_BITFIELD +#define __LITTLE_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __LITTLE_ENDIAN + +#include + +#define __constant_htonl(x) ___constant_swab32((x)) +#define __constant_ntohl(x) ___constant_swab32((x)) +#define __constant_htons(x) ___constant_swab16((x)) +#define __constant_ntohs(x) ___constant_swab16((x)) +#define __constant_cpu_to_le64(x) ((__u64)(x)) +#define __constant_le64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_le32(x) ((__u32)(x)) +#define __constant_le32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_le16(x) ((__u16)(x)) +#define __constant_le16_to_cpu(x) ((__u16)(x)) +#define __constant_cpu_to_be64(x) ___constant_swab64((x)) +#define __constant_be64_to_cpu(x) ___constant_swab64((x)) +#define __constant_cpu_to_be32(x) ___constant_swab32((x)) +#define __constant_be32_to_cpu(x) ___constant_swab32((x)) +#define __constant_cpu_to_be16(x) ___constant_swab16((x)) +#define __constant_be16_to_cpu(x) ___constant_swab16((x)) +#define __cpu_to_le64(x) ((__u64)(x)) +#define __le64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_le32(x) ((__u32)(x)) +#define __le32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_le16(x) ((__u16)(x)) +#define __le16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_be64(x) __swab64((x)) +#define __be64_to_cpu(x) __swab64((x)) +#define __cpu_to_be32(x) __swab32((x)) +#define __be32_to_cpu(x) __swab32((x)) +#define __cpu_to_be16(x) __swab16((x)) +#define __be16_to_cpu(x) __swab16((x)) +#define __cpu_to_le64p(x) (*(__u64*)(x)) +#define __le64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_le32p(x) (*(__u32*)(x)) +#define __le32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_le16p(x) (*(__u16*)(x)) +#define __le16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_be64p(x) __swab64p((x)) +#define __be64_to_cpup(x) __swab64p((x)) +#define __cpu_to_be32p(x) __swab32p((x)) +#define __be32_to_cpup(x) __swab32p((x)) +#define __cpu_to_be16p(x) __swab16p((x)) +#define __be16_to_cpup(x) __swab16p((x)) +#define __cpu_to_le64s(x) do {} while (0) +#define __le64_to_cpus(x) do {} while (0) +#define __cpu_to_le32s(x) do {} while (0) +#define __le32_to_cpus(x) do {} while (0) +#define __cpu_to_le16s(x) do {} while (0) +#define __le16_to_cpus(x) do {} while (0) +#define __cpu_to_be64s(x) __swab64s((x)) +#define __be64_to_cpus(x) __swab64s((x)) +#define __cpu_to_be32s(x) __swab32s((x)) +#define __be32_to_cpus(x) __swab32s((x)) +#define __cpu_to_be16s(x) __swab16s((x)) +#define __be16_to_cpus(x) __swab16s((x)) + +#include + +#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h new file mode 100644 index 0000000..b1d570e --- /dev/null +++ b/include/linux/byteorder/swab.h @@ -0,0 +1,158 @@ +#ifndef _LINUX_BYTEORDER_SWAB_H +#define _LINUX_BYTEORDER_SWAB_H + +/* + * linux/byteorder/swab.h + * Byte-swapping, independently from CPU endianness + * swabXX[ps]?(foo) + * + * Francois-Rene Rideau 19971205 + * separated swab functions from cpu_to_XX, + * to clean up support for bizarre-endian architectures. + * + * See asm-i386/byteorder.h and suches for examples of how to provide + * architecture-dependent optimized versions + * + */ + +/* casts are necessary for constants, because we never know how for sure + * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. + */ +#define ___swab16(x) \ + ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8) )) +#define ___swab32(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) +#define ___swab64(x) \ + ((__u64)( \ + (__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ + (__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) )) + +/* + * provide defaults when no architecture-specific optimization is detected + */ +#ifndef __arch__swab16 +# define __arch__swab16(x) ___swab16(x) +#endif +#ifndef __arch__swab32 +# define __arch__swab32(x) ___swab32(x) +#endif +#ifndef __arch__swab64 +# define __arch__swab64(x) ___swab64(x) +#endif + +#ifndef __arch__swab16p +# define __arch__swab16p(x) __swab16(*(x)) +#endif +#ifndef __arch__swab32p +# define __arch__swab32p(x) __swab32(*(x)) +#endif +#ifndef __arch__swab64p +# define __arch__swab64p(x) __swab64(*(x)) +#endif + +#ifndef __arch__swab16s +# define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0) +#endif +#ifndef __arch__swab32s +# define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0) +#endif +#ifndef __arch__swab64s +# define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0) +#endif + + +/* + * Allow constant folding + */ +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) +# define __swab16(x) \ +(__builtin_constant_p((__u16)(x)) ? \ + ___swab16((x)) : \ + __fswab16((x))) +# define __swab32(x) \ +(__builtin_constant_p((__u32)(x)) ? \ + ___swab32((x)) : \ + __fswab32((x))) +# define __swab64(x) \ +(__builtin_constant_p((__u64)(x)) ? \ + ___swab64((x)) : \ + __fswab64((x))) +#else +# define __swab16(x) __fswab16(x) +# define __swab32(x) __fswab32(x) +# define __swab64(x) __fswab64(x) +#endif /* OPTIMIZE */ + + +static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x) +{ + return __arch__swab16(x); +} +static __inline__ __u16 __swab16p(__u16 *x) +{ + return __arch__swab16p(x); +} +static __inline__ void __swab16s(__u16 *addr) +{ + __arch__swab16s(addr); +} + +static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x) +{ + return __arch__swab32(x); +} +static __inline__ __u32 __swab32p(__u32 *x) +{ + return __arch__swab32p(x); +} +static __inline__ void __swab32s(__u32 *addr) +{ + __arch__swab32s(addr); +} + +#ifdef __BYTEORDER_HAS_U64__ +static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x) +{ +# ifdef __SWAB_64_THRU_32__ + __u32 h = x >> 32; + __u32 l = x & ((1ULL<<32)-1); + return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h))); +# else + return __arch__swab64(x); +# endif +} +static __inline__ __u64 __swab64p(__u64 *x) +{ + return __arch__swab64p(x); +} +static __inline__ void __swab64s(__u64 *addr) +{ + __arch__swab64s(addr); +} +#endif /* __BYTEORDER_HAS_U64__ */ + +#if defined(__KERNEL__) +#define swab16 __swab16 +#define swab32 __swab32 +#define swab64 __swab64 +#define swab16p __swab16p +#define swab32p __swab32p +#define swab64p __swab64p +#define swab16s __swab16s +#define swab32s __swab32s +#define swab64s __swab64s +#endif + +#endif /* _LINUX_BYTEORDER_SWAB_H */ diff --git a/include/linux/config.h b/include/linux/config.h new file mode 100644 index 0000000..a0194cb --- /dev/null +++ b/include/linux/config.h @@ -0,0 +1,6 @@ +#ifndef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H + +/* #include */ + +#endif diff --git a/include/linux/ctype.h b/include/linux/ctype.h new file mode 100644 index 0000000..afa3639 --- /dev/null +++ b/include/linux/ctype.h @@ -0,0 +1,54 @@ +#ifndef _LINUX_CTYPE_H +#define _LINUX_CTYPE_H + +/* + * NOTE! This ctype does not handle EOF like the standard C + * library is required to. + */ + +#define _U 0x01 /* upper */ +#define _L 0x02 /* lower */ +#define _D 0x04 /* digit */ +#define _C 0x08 /* cntrl */ +#define _P 0x10 /* punct */ +#define _S 0x20 /* white space (space/lf/tab) */ +#define _X 0x40 /* hex digit */ +#define _SP 0x80 /* hard space (0x20) */ + +extern unsigned char _ctype[]; + +#define __ismask(x) (_ctype[(int)(unsigned char)(x)]) + +#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) +#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) +#define iscntrl(c) ((__ismask(c)&(_C)) != 0) +#define isdigit(c) ((__ismask(c)&(_D)) != 0) +#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) +#define islower(c) ((__ismask(c)&(_L)) != 0) +#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) +#define ispunct(c) ((__ismask(c)&(_P)) != 0) +#define isspace(c) ((__ismask(c)&(_S)) != 0) +#define isupper(c) ((__ismask(c)&(_U)) != 0) +#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) + +#define isascii(c) (((unsigned char)(c))<=0x7f) +#define toascii(c) (((unsigned char)(c))&0x7f) + +static inline unsigned char __tolower(unsigned char c) +{ + if (isupper(c)) + c -= 'A'-'a'; + return c; +} + +static inline unsigned char __toupper(unsigned char c) +{ + if (islower(c)) + c -= 'a'-'A'; + return c; +} + +#define tolower(c) __tolower(c) +#define toupper(c) __toupper(c) + +#endif diff --git a/include/linux/list.h b/include/linux/list.h new file mode 100644 index 0000000..e6492f7 --- /dev/null +++ b/include/linux/list.h @@ -0,0 +1,258 @@ +#ifndef _LINUX_LIST_H +#define _LINUX_LIST_H + +#ifndef ARCH_HAS_PREFETCH +#define ARCH_HAS_PREFETCH +static inline void prefetch(const void *x) {;} +#endif + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +struct list_head { + struct list_head *next, *prev; +}; + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +#define INIT_LIST_HEAD(ptr) do { \ + (ptr)->next = (ptr); (ptr)->prev = (ptr); \ +} while (0) + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_add(struct list_head *new, + struct list_head *prev, + struct list_head *next) +{ + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; +} + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static inline void list_add(struct list_head *new, struct list_head *head) +{ + __list_add(new, head, head->next); +} + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *new, struct list_head *head) +{ + __list_add(new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head *prev, struct list_head *next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty on entry does not return true after this, the entry is in an undefined state. + */ +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = (void *) 0; + entry->prev = (void *) 0; +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static inline void list_del_init(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + INIT_LIST_HEAD(entry); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static inline void list_move(struct list_head *list, struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add(list, head); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static inline void list_move_tail(struct list_head *list, + struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add_tail(list, head); +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(struct list_head *head) +{ + return head->next == head; +} + +static inline void __list_splice(struct list_head *list, + struct list_head *head) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + struct list_head *at = head->next; + + first->prev = head; + head->next = first; + + last->next = at; + at->prev = last; +} + +/** + * list_splice - join two lists + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice(struct list_head *list, struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head); +} + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static inline void list_splice_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head); + INIT_LIST_HEAD(list); + } +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member))) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop counter. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next, prefetch(pos->next); pos != (head); \ + pos = pos->next, prefetch(pos->next)) +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop counter. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev, prefetch(pos->prev); pos != (head); \ + pos = pos->prev, prefetch(pos->prev)) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop counter. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop counter. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + prefetch(pos->member.next); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member), \ + prefetch(pos->member.next)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop counter. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_continue - iterate over list of given type + * continuing after existing point + * @pos: the type * to use as a loop counter. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + prefetch(pos->member.next); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member), \ + prefetch(pos->member.next)) + +#endif diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h new file mode 100644 index 0000000..227feeb --- /dev/null +++ b/include/linux/mc146818rtc.h @@ -0,0 +1,98 @@ +/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM + * Copyright Torsten Duwe 1993 + * derived from Data Sheet, Copyright Motorola 1984 (!). + * It was written to be part of the Linux operating system. + */ +/* permission is hereby granted to copy, modify and redistribute this code + * in terms of the GNU Library General Public License, Version 2 or later, + * at your option. + */ + +#ifndef _MC146818RTC_H +#define _MC146818RTC_H + +#include +#include /* get the user-level API */ +#include /* register access macros */ + +/********************************************************************** + * register summary + **********************************************************************/ +#define RTC_SECONDS 0 +#define RTC_SECONDS_ALARM 1 +#define RTC_MINUTES 2 +#define RTC_MINUTES_ALARM 3 +#define RTC_HOURS 4 +#define RTC_HOURS_ALARM 5 +/* RTC_*_alarm is always true if 2 MSBs are set */ +# define RTC_ALARM_DONT_CARE 0xC0 + +#define RTC_DAY_OF_WEEK 6 +#define RTC_DAY_OF_MONTH 7 +#define RTC_MONTH 8 +#define RTC_YEAR 9 + +/* control registers - Moto names + */ +#define RTC_REG_A 10 +#define RTC_REG_B 11 +#define RTC_REG_C 12 +#define RTC_REG_D 13 + +/********************************************************************** + * register details + **********************************************************************/ +#define RTC_FREQ_SELECT RTC_REG_A + +/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, + * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, + * totalling to a max high interval of 2.228 ms. + */ +# define RTC_UIP 0x80 +# define RTC_DIV_CTL 0x70 + /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ +# define RTC_REF_CLCK_4MHZ 0x00 +# define RTC_REF_CLCK_1MHZ 0x10 +# define RTC_REF_CLCK_32KHZ 0x20 + /* 2 values for divider stage reset, others for "testing purposes only" */ +# define RTC_DIV_RESET1 0x60 +# define RTC_DIV_RESET2 0x70 + /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ +# define RTC_RATE_SELECT 0x0F + +/**********************************************************************/ +#define RTC_CONTROL RTC_REG_B +# define RTC_SET 0x80 /* disable updates for clock setting */ +# define RTC_PIE 0x40 /* periodic interrupt enable */ +# define RTC_AIE 0x20 /* alarm interrupt enable */ +# define RTC_UIE 0x10 /* update-finished interrupt enable */ +# define RTC_SQWE 0x08 /* enable square-wave output */ +# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ +# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ +# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ + +/**********************************************************************/ +#define RTC_INTR_FLAGS RTC_REG_C +/* caution - cleared by read */ +# define RTC_IRQF 0x80 /* any of the following 3 is active */ +# define RTC_PF 0x40 +# define RTC_AF 0x20 +# define RTC_UF 0x10 + +/**********************************************************************/ +#define RTC_VALID RTC_REG_D +# define RTC_VRT 0x80 /* valid RAM and time */ +/**********************************************************************/ + +/* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) + * determines if the following two #defines are needed + */ +#ifndef BCD_TO_BIN +#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) +#endif + +#ifndef BIN_TO_BCD +#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) +#endif + +#endif /* _MC146818RTC_H */ diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h new file mode 100644 index 0000000..ebf9a76 --- /dev/null +++ b/include/linux/mtd/doc2000.h @@ -0,0 +1,151 @@ + +/* Linux driver for Disk-On-Chip 2000 */ +/* (c) 1999 Machine Vision Holdings, Inc. */ +/* Author: David Woodhouse */ +/* $Id: doc2000.h,v 1.15 2001/09/19 00:22:15 dwmw2 Exp $ */ + +#ifndef __MTD_DOC2000_H__ +#define __MTD_DOC2000_H__ + +struct DiskOnChip; + +#include + +#define DoC_Sig1 0 +#define DoC_Sig2 1 + +#define DoC_ChipID 0x1000 +#define DoC_DOCStatus 0x1001 +#define DoC_DOCControl 0x1002 +#define DoC_FloorSelect 0x1003 +#define DoC_CDSNControl 0x1004 +#define DoC_CDSNDeviceSelect 0x1005 +#define DoC_ECCConf 0x1006 +#define DoC_2k_ECCStatus 0x1007 + +#define DoC_CDSNSlowIO 0x100d +#define DoC_ECCSyndrome0 0x1010 +#define DoC_ECCSyndrome1 0x1011 +#define DoC_ECCSyndrome2 0x1012 +#define DoC_ECCSyndrome3 0x1013 +#define DoC_ECCSyndrome4 0x1014 +#define DoC_ECCSyndrome5 0x1015 +#define DoC_AliasResolution 0x101b +#define DoC_ConfigInput 0x101c +#define DoC_ReadPipeInit 0x101d +#define DoC_WritePipeTerm 0x101e +#define DoC_LastDataRead 0x101f +#define DoC_NOP 0x1020 + +#define DoC_Mil_CDSN_IO 0x0800 +#define DoC_2k_CDSN_IO 0x1800 + +#define ReadDOC_(adr, reg) ((volatile unsigned char)(*(volatile __u8 *)(((unsigned long)adr)+((reg))))) +#define WriteDOC_(d, adr, reg) do{ *(volatile __u8 *)(((unsigned long)adr)+((reg))) = (__u8)d; eieio();} while(0) + +#define DOC_IOREMAP_LEN 0x4000 + +/* These are provided to directly use the DoC_xxx defines */ +#define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg) +#define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg) + +#define DOC_MODE_RESET 0 +#define DOC_MODE_NORMAL 1 +#define DOC_MODE_RESERVED1 2 +#define DOC_MODE_RESERVED2 3 + +#define DOC_MODE_MDWREN 4 +#define DOC_MODE_CLR_ERR 0x80 + +#define DOC_ChipID_UNKNOWN 0x00 +#define DOC_ChipID_Doc2k 0x20 +#define DOC_ChipID_DocMil 0x30 + +#define CDSN_CTRL_FR_B 0x80 +#define CDSN_CTRL_ECC_IO 0x20 +#define CDSN_CTRL_FLASH_IO 0x10 +#define CDSN_CTRL_WP 0x08 +#define CDSN_CTRL_ALE 0x04 +#define CDSN_CTRL_CLE 0x02 +#define CDSN_CTRL_CE 0x01 + +#define DOC_ECC_RESET 0 +#define DOC_ECC_ERROR 0x80 +#define DOC_ECC_RW 0x20 +#define DOC_ECC__EN 0x08 +#define DOC_TOGGLE_BIT 0x04 +#define DOC_ECC_RESV 0x02 +#define DOC_ECC_IGNORE 0x01 + +/* We have to also set the reserved bit 1 for enable */ +#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV) +#define DOC_ECC_DIS (DOC_ECC_RESV) + +#define MAX_FLOORS 4 +#define MAX_CHIPS 4 + +#define MAX_FLOORS_MIL 4 +#define MAX_CHIPS_MIL 1 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +struct DiskOnChip { + unsigned long physadr; + unsigned long virtadr; + unsigned long totlen; + char* name; + char ChipID; /* Type of DiskOnChip */ + int ioreg; + + char* chips_name; + unsigned long mfr; /* Flash IDs - only one type of flash per device */ + unsigned long id; + int chipshift; + char page256; + char pageadrlen; + unsigned long erasesize; + + int curfloor; + int curchip; + + int numchips; + struct Nand *chips; + + int nftl_found; + struct NFTLrecord nftl; +}; + +#define SECTORSIZE 512 + +/* Return codes from doc_write(), doc_read(), and doc_erase(). + */ +#define DOC_OK 0 +#define DOC_EIO 1 +#define DOC_EINVAL 2 +#define DOC_EECC 3 +#define DOC_ETIMEOUT 4 + +/* + * Function Prototypes + */ +int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]); + +int doc_rw(struct DiskOnChip* this, int cmd, loff_t from, size_t len, + size_t *retlen, u_char *buf); +int doc_read_ecc(struct DiskOnChip* this, loff_t from, size_t len, + size_t *retlen, u_char *buf, u_char *eccbuf); +int doc_write_ecc(struct DiskOnChip* this, loff_t to, size_t len, + size_t *retlen, const u_char *buf, u_char *eccbuf); +int doc_read_oob(struct DiskOnChip* this, loff_t ofs, size_t len, + size_t *retlen, u_char *buf); +int doc_write_oob(struct DiskOnChip* this, loff_t ofs, size_t len, + size_t *retlen, const u_char *buf); +int doc_erase (struct DiskOnChip* this, loff_t ofs, size_t len); + +void doc_probe(unsigned long physadr); + +void doc_print(struct DiskOnChip*); + +#endif /* __MTD_DOC2000_H__ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h new file mode 100644 index 0000000..5236904 --- /dev/null +++ b/include/linux/mtd/nand.h @@ -0,0 +1,200 @@ +/* + * linux/include/linux/mtd/nand.h + * + * Copyright (c) 2000 David Woodhouse + * Steven J. Hill + * Thomas Gleixner + * + * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Info: + * Contains standard defines and IDs for NAND flash devices + * + * Changelog: + * 01-31-2000 DMW Created + * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers + * so it can be used by other NAND flash device + * drivers. I also changed the copyright since none + * of the original contents of this file are specific + * to DoC devices. David can whack me with a baseball + * bat later if I did something naughty. + * 10-11-2000 SJH Added private NAND flash structure for driver + * 10-24-2000 SJH Added prototype for 'nand_scan' function + * 10-29-2001 TG changed nand_chip structure to support + * hardwarespecific function for accessing control lines + * 02-21-2002 TG added support for different read/write adress and + * ready/busy line access function + * 02-26-2002 TG added chip_delay to nand_chip structure to optimize + * command delay times for different chips + * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate + * defines in jffs2/wbuf.c + */ +#ifndef __LINUX_MTD_NAND_H +#define __LINUX_MTD_NAND_H + +/* + * Standard NAND flash commands + */ +#define NAND_CMD_READ0 0 +#define NAND_CMD_READ1 1 +#define NAND_CMD_PAGEPROG 0x10 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_ERASE1 0x60 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_ERASE2 0xd0 +#define NAND_CMD_RESET 0xff + +/* + * Enumeration for NAND flash chip state + */ +typedef enum { + FL_READY, + FL_READING, + FL_WRITING, + FL_ERASING, + FL_SYNCING +} nand_state_t; + + +/* + * NAND Private Flash Chip Data + * + * Structure overview: + * + * IO_ADDR - address to access the 8 I/O lines of the flash device + * + * hwcontrol - hardwarespecific function for accesing control-lines + * + * dev_ready - hardwarespecific function for accesing device ready/busy line + * + * chip_lock - spinlock used to protect access to this structure + * + * wq - wait queue to sleep on if a NAND operation is in progress + * + * state - give the current state of the NAND device + * + * page_shift - number of address bits in a page (column address bits) + * + * data_buf - data buffer passed to/from MTD user modules + * + * data_cache - data cache for redundant page access and shadow for + * ECC failure + * + * ecc_code_buf - used only for holding calculated or read ECCs for + * a page read or written when ECC is in use + * + * reserved - padding to make structure fall on word boundary if + * when ECC is in use + */ +struct Nand { + char floor, chip; + unsigned long curadr; + unsigned char curmode; + /* Also some erase/write/pipeline info when we get that far */ +}; + +struct nand_chip { + int page_shift; + u_char *data_buf; + u_char *data_cache; + int cache_page; + u_char ecc_code_buf[6]; + u_char reserved[2]; + char ChipID; /* Type of DiskOnChip */ + struct Nand *chips; + int chipshift; + char* chips_name; + unsigned long erasesize; + unsigned long mfr; /* Flash IDs - only one type of flash per device */ + unsigned long id; + char* name; + int numchips; + char page256; + char pageadrlen; + unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */ + unsigned long totlen; + uint oobblock; /* Size of OOB blocks (e.g. 512) */ + uint oobsize; /* Amount of OOB data per block (e.g. 16) */ + uint eccsize; + int bus16; +}; + +/* + * NAND Flash Manufacturer ID Codes + */ +#define NAND_MFR_TOSHIBA 0x98 +#define NAND_MFR_SAMSUNG 0xec + +/* + * NAND Flash Device ID Structure + * + * Structure overview: + * + * name - Complete name of device + * + * manufacture_id - manufacturer ID code of device. + * + * model_id - model ID code of device. + * + * chipshift - total number of address bits for the device which + * is used to calculate address offsets and the total + * number of bytes the device is capable of. + * + * page256 - denotes if flash device has 256 byte pages or not. + * + * pageadrlen - number of bytes minus one needed to hold the + * complete address into the flash array. Keep in + * mind that when a read or write is done to a + * specific address, the address is input serially + * 8 bits at a time. This structure member is used + * by the read/write routines as a loop index for + * shifting the address out 8 bits at a time. + * + * erasesize - size of an erase block in the flash device. + */ +struct nand_flash_dev { + char * name; + int manufacture_id; + int model_id; + int chipshift; + char page256; + char pageadrlen; + unsigned long erasesize; + int bus16; +}; + +/* +* Constants for oob configuration +*/ +#define NAND_NOOB_ECCPOS0 0 +#define NAND_NOOB_ECCPOS1 1 +#define NAND_NOOB_ECCPOS2 2 +#define NAND_NOOB_ECCPOS3 3 +#define NAND_NOOB_ECCPOS4 6 +#define NAND_NOOB_ECCPOS5 7 +#define NAND_NOOB_BADBPOS -1 +#define NAND_NOOB_ECCVPOS -1 + +#define NAND_JFFS2_OOB_ECCPOS0 0 +#define NAND_JFFS2_OOB_ECCPOS1 1 +#define NAND_JFFS2_OOB_ECCPOS2 2 +#define NAND_JFFS2_OOB_ECCPOS3 3 +#define NAND_JFFS2_OOB_ECCPOS4 6 +#define NAND_JFFS2_OOB_ECCPOS5 7 +#define NAND_JFFS2_OOB_BADBPOS 5 +#define NAND_JFFS2_OOB_ECCVPOS 4 + +#define NAND_JFFS2_OOB8_FSDAPOS 6 +#define NAND_JFFS2_OOB16_FSDAPOS 8 +#define NAND_JFFS2_OOB8_FSDALEN 2 +#define NAND_JFFS2_OOB16_FSDALEN 8 + +unsigned long nand_probe(unsigned long physadr); + +#endif /* __LINUX_MTD_NAND_H */ diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h new file mode 100644 index 0000000..a3d0363 --- /dev/null +++ b/include/linux/mtd/nand_ids.h @@ -0,0 +1,55 @@ +/* + * u-boot/include/linux/mtd/nand_ids.h + * + * Copyright (c) 2000 David Woodhouse + * Steven J. Hill + * + * $Id: nand_ids.h,v 1.1 2000/10/13 16:16:26 mdeans Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Info: + * Contains standard defines and IDs for NAND flash devices + * + * Changelog: + * 01-31-2000 DMW Created + * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers + * so it can be used by other NAND flash device + * drivers. I also changed the copyright since none + * of the original contents of this file are specific + * to DoC devices. David can whack me with a baseball + * bat later if I did something naughty. + * 10-11-2000 SJH Added private NAND flash structure for driver + * 2000-10-13 BE Moved out of 'nand.h' - avoids duplication. + */ + +#ifndef __LINUX_MTD_NAND_IDS_H +#define __LINUX_MTD_NAND_IDS_H + +static struct nand_flash_dev nand_flash_ids[] = { + {"Toshiba TC5816BDC", NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0}, + {"Toshiba TC5832DC", NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0}, + {"Toshiba TH58V128DC", NAND_MFR_TOSHIBA, 0x73, 24, 0, 2, 0x4000, 0}, + {"Toshiba TC58256FT/DC", NAND_MFR_TOSHIBA, 0x75, 25, 0, 2, 0x4000, 0}, + {"Toshiba TH58512FT", NAND_MFR_TOSHIBA, 0x76, 26, 0, 3, 0x4000, 0}, + {"Toshiba TC58V32DC", NAND_MFR_TOSHIBA, 0xe5, 22, 0, 2, 0x2000, 0}, + {"Toshiba TC58V64AFT/DC", NAND_MFR_TOSHIBA, 0xe6, 23, 0, 2, 0x2000, 0}, + {"Toshiba TC58V16BDC", NAND_MFR_TOSHIBA, 0xea, 21, 1, 2, 0x1000, 0}, + {"Toshiba TH58100FT", NAND_MFR_TOSHIBA, 0x79, 27, 0, 3, 0x4000, 0}, + {"Samsung KM29N16000", NAND_MFR_SAMSUNG, 0x64, 21, 1, 2, 0x1000, 0}, + {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0x6b, 22, 0, 2, 0x2000, 0}, + {"Samsung KM29U128T", NAND_MFR_SAMSUNG, 0x73, 24, 0, 2, 0x4000, 0}, + {"Samsung KM29U256T", NAND_MFR_SAMSUNG, 0x75, 25, 0, 2, 0x4000, 0}, + {"Samsung unknown 64Mb", NAND_MFR_SAMSUNG, 0x76, 26, 0, 3, 0x4000, 0}, + {"Samsung KM29W32000", NAND_MFR_SAMSUNG, 0xe3, 22, 0, 2, 0x2000, 0}, + {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0xe5, 22, 0, 2, 0x2000, 0}, + {"Samsung KM29U64000", NAND_MFR_SAMSUNG, 0xe6, 23, 0, 2, 0x2000, 0}, + {"Samsung KM29W16000", NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0}, + {"Samsung K9F5616Q0C", NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1}, + {"Samsung K9K1216Q0C", NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1}, + {NULL,} +}; + +#endif /* __LINUX_MTD_NAND_IDS_H */ diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h new file mode 100644 index 0000000..4381306 --- /dev/null +++ b/include/linux/mtd/nftl.h @@ -0,0 +1,105 @@ + +/* Defines for NAND Flash Translation Layer */ +/* (c) 1999 Machine Vision Holdings, Inc. */ +/* Author: David Woodhouse */ +/* $Id: nftl.h,v 1.10 2000/12/29 00:25:38 dwmw2 Exp $ */ + +#ifndef __MTD_NFTL_H__ +#define __MTD_NFTL_H__ + +/* Block Control Information */ + +struct nftl_bci { + unsigned char ECCSig[6]; + __u8 Status; + __u8 Status1; +}__attribute__((packed)); + +/* Unit Control Information */ + +struct nftl_uci0 { + __u16 VirtUnitNum; + __u16 ReplUnitNum; + __u16 SpareVirtUnitNum; + __u16 SpareReplUnitNum; +} __attribute__((packed)); + +struct nftl_uci1 { + __u32 WearInfo; + __u16 EraseMark; + __u16 EraseMark1; +} __attribute__((packed)); + +struct nftl_uci2 { + __u16 FoldMark; + __u16 FoldMark1; + __u32 unused; +} __attribute__((packed)); + +union nftl_uci { + struct nftl_uci0 a; + struct nftl_uci1 b; + struct nftl_uci2 c; +}; + +struct nftl_oob { + struct nftl_bci b; + union nftl_uci u; +}; + +/* NFTL Media Header */ + +struct NFTLMediaHeader { + char DataOrgID[6]; + __u16 NumEraseUnits; + __u16 FirstPhysicalEUN; + __u32 FormattedSize; + unsigned char UnitSizeFactor; +} __attribute__((packed)); + +#define MAX_ERASE_ZONES (8192 - 512) + +#define ERASE_MARK 0x3c69 +#define SECTOR_FREE 0xff +#define SECTOR_USED 0x55 +#define SECTOR_IGNORE 0x11 +#define SECTOR_DELETED 0x00 + +#define FOLD_MARK_IN_PROGRESS 0x5555 + +#define ZONE_GOOD 0xff +#define ZONE_BAD_ORIGINAL 0 +#define ZONE_BAD_MARKED 7 + +/* these info are used in ReplUnitTable */ +#define BLOCK_NIL 0xffff /* last block of a chain */ +#define BLOCK_FREE 0xfffe /* free block */ +#define BLOCK_NOTEXPLORED 0xfffd /* non explored block, only used during mounting */ +#define BLOCK_RESERVED 0xfffc /* bios block or bad block */ + +struct NFTLrecord { + struct DiskOnChip *mtd; + __u16 MediaUnit, SpareMediaUnit; + __u32 EraseSize; + struct NFTLMediaHeader MediaHdr; + int usecount; + unsigned char heads; + unsigned char sectors; + unsigned short cylinders; + __u16 numvunits; + __u16 lastEUN; /* should be suppressed */ + __u16 numfreeEUNs; + __u16 LastFreeEUN; /* To speed up finding a free EUN */ + __u32 nr_sects; + int head,sect,cyl; + __u16 *EUNtable; /* [numvunits]: First EUN for each virtual unit */ + __u16 *ReplUnitTable; /* [numEUNs]: ReplUnitNumber for each */ + unsigned int nb_blocks; /* number of physical blocks */ + unsigned int nb_boot_blocks; /* number of blocks used by the bios */ +}; + +#define MAX_NFTLS 16 +#define MAX_SECTORS_PER_UNIT 32 +#define NFTL_PARTN_BITS 4 + +#endif /* __MTD_NFTL_H__ */ diff --git a/include/linux/posix_types.h b/include/linux/posix_types.h new file mode 100644 index 0000000..bd37e1f --- /dev/null +++ b/include/linux/posix_types.h @@ -0,0 +1,48 @@ +#ifndef _LINUX_POSIX_TYPES_H +#define _LINUX_POSIX_TYPES_H + +#include + +/* + * This allows for 1024 file descriptors: if NR_OPEN is ever grown + * beyond that you'll have to change this too. But 1024 fd's seem to be + * enough even for such "real" unices like OSF/1, so hopefully this is + * one limit that doesn't have to be changed [again]. + * + * Note that POSIX wants the FD_CLEAR(fd,fdsetp) defines to be in + * (and thus ) - but this is a more logical + * place for them. Solved by having dummy defines in . + */ + +/* + * Those macros may have been defined in . But we always + * use the ones here. + */ +#undef __NFDBITS +#define __NFDBITS (8 * sizeof(unsigned long)) + +#undef __FD_SETSIZE +#define __FD_SETSIZE 1024 + +#undef __FDSET_LONGS +#define __FDSET_LONGS (__FD_SETSIZE/__NFDBITS) + +#undef __FDELT +#define __FDELT(d) ((d) / __NFDBITS) + +#undef __FDMASK +#define __FDMASK(d) (1UL << ((d) % __NFDBITS)) + +typedef struct { + unsigned long fds_bits [__FDSET_LONGS]; +} __kernel_fd_set; + +/* Type of a signal handler. */ +typedef void (*__kernel_sighandler_t)(int); + +/* Type of a SYSV IPC key. */ +typedef int __kernel_key_t; + +#include + +#endif /* _LINUX_POSIX_TYPES_H */ diff --git a/include/linux/stat.h b/include/linux/stat.h new file mode 100644 index 0000000..2f7a3b3 --- /dev/null +++ b/include/linux/stat.h @@ -0,0 +1,132 @@ +#ifndef _LINUX_STAT_H +#define _LINUX_STAT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define S_IFMT 00170000 /* type of file */ +#define S_IFSOCK 0140000 /* named socket */ +#define S_IFLNK 0120000 /* symbolic link */ +#define S_IFREG 0100000 /* regular */ +#define S_IFBLK 0060000 /* block special */ +#define S_IFDIR 0040000 /* directory */ +#define S_IFCHR 0020000 /* character special */ +#define S_IFIFO 0010000 /* fifo */ +#define S_ISUID 0004000 /* set user id on execution */ +#define S_ISGID 0002000 /* set group id on execution */ +#define S_ISVTX 0001000 /* save swapped text even after use */ + +#define S_ISLNK(m) (((m) & S_IFMT) == S_IFLNK) +#define S_ISREG(m) (((m) & S_IFMT) == S_IFREG) +#define S_ISDIR(m) (((m) & S_IFMT) == S_IFDIR) +#define S_ISCHR(m) (((m) & S_IFMT) == S_IFCHR) +#define S_ISBLK(m) (((m) & S_IFMT) == S_IFBLK) +#define S_ISFIFO(m) (((m) & S_IFMT) == S_IFIFO) +#define S_ISSOCK(m) (((m) & S_IFMT) == S_IFSOCK) + +#define S_IRWXU 00700 /* rwx for owner */ +#define S_IRUSR 00400 /* read permission for owner */ +#define S_IWUSR 00200 /* write permission for owner */ +#define S_IXUSR 00100 /* execute/search permission for owner */ + +#define S_IRWXG 00070 /* rwx for group */ +#define S_IRGRP 00040 /* read permission for group */ +#define S_IWGRP 00020 /* write permission for group */ +#define S_IXGRP 00010 /* execute/search permission for group */ + +#define S_IRWXO 00007 /* rwx for other */ +#define S_IROTH 00004 /* read permission for other */ +#define S_IWOTH 00002 /* read permission for other */ +#define S_IXOTH 00001 /* execute/search permission for other */ + +#ifdef __PPC__ + +struct stat { + dev_t st_dev; /* file system id */ + ino_t st_ino; /* file id */ + mode_t st_mode; /* ownership/protection */ + nlink_t st_nlink; /* number of links */ + uid_t st_uid; /* user id */ + gid_t st_gid; /* group id */ + dev_t st_rdev; + off_t st_size; /* file size in # of bytes */ + unsigned long st_blksize; /* block size */ + unsigned long st_blocks; /* file size in # of blocks */ + unsigned long st_atime; /* time file was last accessed */ + unsigned long __unused1; + unsigned long st_mtime; /* time file was last modified */ + unsigned long __unused2; + unsigned long st_ctime; /* time file status was last changed */ + unsigned long __unused3; + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* __PPC__ */ + +#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) + +struct stat { + unsigned short st_dev; + unsigned short __pad1; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned short __pad2; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long __unused1; + unsigned long st_mtime; + unsigned long __unused2; + unsigned long st_ctime; + unsigned long __unused3; + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* __ARM__ */ + +#if defined (__MIPS__) + +struct stat { + dev_t st_dev; + long st_pad1[3]; + ino_t st_ino; + mode_t st_mode; + nlink_t st_nlink; + uid_t st_uid; + gid_t st_gid; + dev_t st_rdev; + long st_pad2[2]; + off_t st_size; + long st_pad3; + /* + * Actually this should be timestruc_t st_atime, st_mtime and st_ctime + * but we don't have it under Linux. + */ + time_t st_atime; + long reserved0; + time_t st_mtime; + long reserved1; + time_t st_ctime; + long reserved2; + long st_blksize; + long st_blocks; + long st_pad4[14]; +}; + +#endif /* __MIPS__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/linux/stddef.h b/include/linux/stddef.h new file mode 100644 index 0000000..81e34c2 --- /dev/null +++ b/include/linux/stddef.h @@ -0,0 +1,18 @@ +#ifndef _LINUX_STDDEF_H +#define _LINUX_STDDEF_H + +#undef NULL +#if defined(__cplusplus) +#define NULL 0 +#else +#define NULL ((void *)0) +#endif + +#ifndef _SIZE_T +#include +#endif + +#undef offsetof +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +#endif diff --git a/include/linux/string.h b/include/linux/string.h new file mode 100644 index 0000000..1a45fd3 --- /dev/null +++ b/include/linux/string.h @@ -0,0 +1,89 @@ +#ifndef _LINUX_STRING_H_ +#define _LINUX_STRING_H_ + +#include /* for size_t */ +#include /* for NULL */ + +#ifdef __cplusplus +extern "C" { +#endif + +extern char * ___strtok; +extern char * strpbrk(const char *,const char *); +extern char * strtok(char *,const char *); +extern char * strsep(char **,const char *); +extern __kernel_size_t strspn(const char *,const char *); + + +/* + * Include machine specific inline routines + */ +#include + +#ifndef __HAVE_ARCH_STRCPY +extern char * strcpy(char *,const char *); +#endif +#ifndef __HAVE_ARCH_STRNCPY +extern char * strncpy(char *,const char *, __kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRCAT +extern char * strcat(char *, const char *); +#endif +#ifndef __HAVE_ARCH_STRNCAT +extern char * strncat(char *, const char *, __kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRCMP +extern int strcmp(const char *,const char *); +#endif +#ifndef __HAVE_ARCH_STRNCMP +extern int strncmp(const char *,const char *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRNICMP +extern int strnicmp(const char *, const char *, __kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRCHR +extern char * strchr(const char *,int); +#endif +#ifndef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char *,int); +#endif +#ifndef __HAVE_ARCH_STRSTR +extern char * strstr(const char *,const char *); +#endif +#ifndef __HAVE_ARCH_STRLEN +extern __kernel_size_t strlen(const char *); +#endif +#ifndef __HAVE_ARCH_STRNLEN +extern __kernel_size_t strnlen(const char *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRDUP +extern char * strdup(const char *); +#endif +#ifndef __HAVE_ARCH_STRSWAB +extern char * strswab(const char *); +#endif + +#ifndef __HAVE_ARCH_MEMSET +extern void * memset(void *,int,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *,const void *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *,const void *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMSCAN +extern void * memscan(void *,int,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMCMP +extern int memcmp(const void *,const void *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *,int,__kernel_size_t); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _LINUX_STRING_H_ */ diff --git a/include/linux/time.h b/include/linux/time.h new file mode 100644 index 0000000..bf12b99 --- /dev/null +++ b/include/linux/time.h @@ -0,0 +1,158 @@ +#ifndef _LINUX_TIME_H +#define _LINUX_TIME_H + +#include + +#define _DEFUN(a,b,c) a(c) +#define _CONST const +#define _AND , + +#define _REENT_ONLY + +#define SECSPERMIN 60L +#define MINSPERHOUR 60L +#define HOURSPERDAY 24L +#define SECSPERHOUR (SECSPERMIN * MINSPERHOUR) +#define SECSPERDAY (SECSPERHOUR * HOURSPERDAY) +#define DAYSPERWEEK 7 +#define MONSPERYEAR 12 + +#define YEAR_BASE 1900 +#define EPOCH_YEAR 1970 +#define EPOCH_WDAY 4 + +#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) + + +/* Used by other time functions. */ +struct tm { + int tm_sec; /* Seconds. [0-60] (1 leap second) */ + int tm_min; /* Minutes. [0-59] */ + int tm_hour; /* Hours. [0-23] */ + int tm_mday; /* Day. [1-31] */ + int tm_mon; /* Month. [0-11] */ + int tm_year; /* Year - 1900. */ + int tm_wday; /* Day of week. [0-6] */ + int tm_yday; /* Days in year.[0-365] */ + int tm_isdst; /* DST. [-1/0/1]*/ + +# ifdef __USE_BSD + long int tm_gmtoff; /* Seconds east of UTC. */ + __const char *tm_zone; /* Timezone abbreviation. */ +# else + long int __tm_gmtoff; /* Seconds east of UTC. */ + __const char *__tm_zone; /* Timezone abbreviation. */ +# endif +}; + +static inline char * +_DEFUN (asctime_r, (tim_p, result), + _CONST struct tm *tim_p _AND + char *result) +{ + static _CONST char day_name[7][3] = { + "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat" + }; + static _CONST char mon_name[12][3] = { + "Jan", "Feb", "Mar", "Apr", "May", "Jun", + "Jul", "Aug", "Sep", "Oct", "Nov", "Dec" + }; + + sprintf (result, "%.3s %.3s %.2d %.2d:%.2d:%.2d %d\n", + day_name[tim_p->tm_wday], + mon_name[tim_p->tm_mon], + tim_p->tm_mday, tim_p->tm_hour, tim_p->tm_min, + tim_p->tm_sec, 1900 + tim_p->tm_year); + return result; +} + +static inline struct tm * +_DEFUN (localtime_r, (tim_p, res), + _CONST time_t * tim_p _AND + struct tm *res) +{ + static _CONST int mon_lengths[2][MONSPERYEAR] = { + {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}, + {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31} + } ; + + static _CONST int year_lengths[2] = { + 365, + 366 + } ; + + long days, rem; + int y; + int yleap; + _CONST int *ip; + + days = ((long) *tim_p) / SECSPERDAY; + rem = ((long) *tim_p) % SECSPERDAY; + while (rem < 0) + { + rem += SECSPERDAY; + --days; + } + while (rem >= SECSPERDAY) + { + rem -= SECSPERDAY; + ++days; + } + + /* compute hour, min, and sec */ + res->tm_hour = (int) (rem / SECSPERHOUR); + rem %= SECSPERHOUR; + res->tm_min = (int) (rem / SECSPERMIN); + res->tm_sec = (int) (rem % SECSPERMIN); + + /* compute day of week */ + if ((res->tm_wday = ((EPOCH_WDAY + days) % DAYSPERWEEK)) < 0) + res->tm_wday += DAYSPERWEEK; + + /* compute year & day of year */ + y = EPOCH_YEAR; + if (days >= 0) + { + for (;;) + { + yleap = isleap(y); + if (days < year_lengths[yleap]) + break; + y++; + days -= year_lengths[yleap]; + } + } + else + { + do + { + --y; + yleap = isleap(y); + days += year_lengths[yleap]; + } while (days < 0); + } + + res->tm_year = y - YEAR_BASE; + res->tm_yday = days; + ip = mon_lengths[yleap]; + for (res->tm_mon = 0; days >= ip[res->tm_mon]; ++res->tm_mon) + days -= ip[res->tm_mon]; + res->tm_mday = days + 1; + + /* set daylight saving time flag */ + res->tm_isdst = -1; + + return (res); +} + +static inline char * +_DEFUN (ctime_r, (tim_p, result), + _CONST time_t * tim_p _AND + char * result) + +{ + struct tm tm; + return asctime_r (localtime_r (tim_p, &tm), result); +} + +#endif diff --git a/include/linux/types.h b/include/linux/types.h new file mode 100644 index 0000000..df4808f --- /dev/null +++ b/include/linux/types.h @@ -0,0 +1,130 @@ +#ifndef _LINUX_TYPES_H +#define _LINUX_TYPES_H + +#ifdef __KERNEL__ +#include +#endif + +#include +#include + +#ifndef __KERNEL_STRICT_NAMES + +typedef __kernel_fd_set fd_set; +typedef __kernel_dev_t dev_t; +typedef __kernel_ino_t ino_t; +typedef __kernel_mode_t mode_t; +typedef __kernel_nlink_t nlink_t; +typedef __kernel_off_t off_t; +typedef __kernel_pid_t pid_t; +typedef __kernel_daddr_t daddr_t; +typedef __kernel_key_t key_t; +typedef __kernel_suseconds_t suseconds_t; + +#ifdef __KERNEL__ +typedef __kernel_uid32_t uid_t; +typedef __kernel_gid32_t gid_t; +typedef __kernel_uid16_t uid16_t; +typedef __kernel_gid16_t gid16_t; + +#ifdef CONFIG_UID16 +/* This is defined by include/asm-{arch}/posix_types.h */ +typedef __kernel_old_uid_t old_uid_t; +typedef __kernel_old_gid_t old_gid_t; +#endif /* CONFIG_UID16 */ + +/* libc5 includes this file to define uid_t, thus uid_t can never change + * when it is included by non-kernel code + */ +#else +typedef __kernel_uid_t uid_t; +typedef __kernel_gid_t gid_t; +#endif /* __KERNEL__ */ + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __kernel_loff_t loff_t; +#endif + +/* + * The following typedefs are also protected by individual ifdefs for + * historical reasons: + */ +#ifndef _SIZE_T +#define _SIZE_T +typedef __kernel_size_t size_t; +#endif + +#ifndef _SSIZE_T +#define _SSIZE_T +typedef __kernel_ssize_t ssize_t; +#endif + +#ifndef _PTRDIFF_T +#define _PTRDIFF_T +typedef __kernel_ptrdiff_t ptrdiff_t; +#endif + +#ifndef _TIME_T +#define _TIME_T +typedef __kernel_time_t time_t; +#endif + +#ifndef _CLOCK_T +#define _CLOCK_T +typedef __kernel_clock_t clock_t; +#endif + +#ifndef _CADDR_T +#define _CADDR_T +typedef __kernel_caddr_t caddr_t; +#endif + +/* bsd */ +typedef unsigned char u_char; +typedef unsigned short u_short; +typedef unsigned int u_int; +typedef unsigned long u_long; + +/* sysv */ +typedef unsigned char unchar; +typedef unsigned short ushort; +typedef unsigned int uint; +typedef unsigned long ulong; + +#ifndef __BIT_TYPES_DEFINED__ +#define __BIT_TYPES_DEFINED__ + +typedef __u8 u_int8_t; +typedef __s8 int8_t; +typedef __u16 u_int16_t; +typedef __s16 int16_t; +typedef __u32 u_int32_t; +typedef __s32 int32_t; + +#endif /* !(__BIT_TYPES_DEFINED__) */ + +typedef __u8 uint8_t; +typedef __u16 uint16_t; +typedef __u32 uint32_t; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __u64 uint64_t; +typedef __u64 u_int64_t; +typedef __s64 int64_t; +#endif + +#endif /* __KERNEL_STRICT_NAMES */ + +/* + * Below are truly Linux-specific types that should never collide with + * any application/library that wants linux/types.h. + */ + +struct ustat { + __kernel_daddr_t f_tfree; + __kernel_ino_t f_tinode; + char f_fname[6]; + char f_fpack[6]; +}; + +#endif /* _LINUX_TYPES_H */ diff --git a/include/linux_logo.h b/include/linux_logo.h new file mode 100644 index 0000000..9aa712e --- /dev/null +++ b/include/linux_logo.h @@ -0,0 +1,1445 @@ +/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $ + * include/linux/linux_logo.h: This is a linux logo + * to be displayed on boot. + * + * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu) + * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) + * + * You can put anything here, but: + * LINUX_LOGO_COLORS has to be less than 224 + * image size has to be 80x80 + * values have to start from 0x20 + * (i.e. RGB(linux_logo_red[0], + * linux_logo_green[0], + * linux_logo_blue[0]) is color 0x20) + * BW image has to be 80x80 as well, with MS bit + * on the left + * Serial_console ascii image can be any size, + * but should contain %s to display the version + */ + +#if LINUX_LOGO_COLORS == 214 + +unsigned char linux_logo_red[] __initdata = { + 0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9, + 0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6, + 0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2, + 0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54, + 0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74, + 0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E, + 0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38, + 0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3, + 0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA, + 0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC, + 0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B, + 0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52, + 0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2, + 0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6, + 0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF, + 0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46, + 0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6, + 0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA, + 0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E, + 0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7, + 0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4, + 0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA, + 0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59, + 0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB, + 0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6, + 0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72, + 0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4 +}; + +unsigned char linux_logo_green[] __initdata = { + 0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5, + 0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86, + 0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96, + 0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54, + 0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74, + 0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42, + 0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24, + 0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C, + 0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2, + 0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D, + 0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E, + 0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A, + 0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE, + 0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE, + 0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB, + 0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E, + 0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E, + 0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A, + 0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62, + 0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6, + 0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA, + 0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6, + 0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45, + 0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92, + 0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA, + 0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56, + 0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE +}; + +unsigned char linux_logo_blue[] __initdata = { + 0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7, + 0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20, + 0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40, + 0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56, + 0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74, + 0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11, + 0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A, + 0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11, + 0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C, + 0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C, + 0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E, + 0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C, + 0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94, + 0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC, + 0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91, + 0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C, + 0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C, + 0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74, + 0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04, + 0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2, + 0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10, + 0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C, + 0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E, + 0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C, + 0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C, + 0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24, + 0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7 +}; + +unsigned char linux_logo[] __initdata = { + 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C, + 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95, + 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C, + 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6, + 0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55, + 0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A, + 0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, + 0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, + 0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, + 0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, + 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95, + 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB, + 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C, + 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C, + 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C, + 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6, + 0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, + 0x2C, 0x95, 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, + 0x55, 0xCB, 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, + 0xA1, 0x2C, 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, + 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, 0x2C, 0x95, + 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x70, + 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C, + 0x95, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, + 0x95, 0x55, 0xCB, 0x95, 0xD6, 0xA1, 0x2C, 0x95, + 0xA1, 0xD6, 0xD6, 0xA1, 0xA1, 0xD6, 0xA1, 0xA1, + 0xA1, 0x2C, 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, + 0x2C, 0x95, 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, + 0x55, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, + 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0xD6, 0xD6, 0xA1, + 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95, + 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB, + 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C, + 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x95, + 0x55, 0x55, 0x2C, 0x3F, 0x80, 0x20, 0x88, 0x88, + 0x88, 0x20, 0x88, 0xB1, 0x2C, 0xA1, 0x2C, 0x2C, + 0x95, 0xCB, 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, + 0xA1, 0x95, 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, + 0xCB, 0xCB, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, + 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, + 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, + 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, + 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x95, + 0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, + 0x2C, 0x94, 0x80, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x88, 0x92, 0xA1, 0x95, + 0x55, 0x90, 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, + 0xA1, 0x2C, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, + 0x55, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1, + 0x2C, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95, + 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95, + 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C, + 0xA1, 0xD6, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x55, + 0x55, 0x55, 0x95, 0x95, 0x2C, 0x95, 0x95, 0xD6, + 0xB1, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x80, 0x34, 0x88, 0x43, 0x47, + 0x95, 0xCB, 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, + 0xA1, 0x95, 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, + 0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C, + 0x55, 0x55, 0x55, 0x55, 0x2C, 0x95, 0x2C, 0x2C, + 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55, + 0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0xA1, 0xA1, + 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x95, + 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD5, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x88, 0x7D, 0x3F, 0xB1, 0x80, 0x20, + 0x99, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1, + 0x2C, 0x55, 0x90, 0x70, 0x90, 0x55, 0x95, 0x95, + 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C, + 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, + 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0xCB, + 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1, 0xA1, 0xA1, + 0x2C, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95, + 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x88, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0xB1, 0x47, 0xD5, 0x7D, 0x43, + 0x20, 0x70, 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, + 0x95, 0xCB, 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1, + 0xA1, 0xA1, 0x2C, 0x95, 0x2C, 0x2C, 0x95, 0x95, + 0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, + 0x95, 0x90, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0x90, + 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xA1, + 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x55, + 0xCB, 0xCB, 0xCB, 0x55, 0xCB, 0x55, 0x47, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x88, 0xB1, 0x3F, 0x92, 0x2B, 0x80, + 0x20, 0x80, 0xD6, 0x70, 0x55, 0x2C, 0xD6, 0xD6, + 0x2C, 0x90, 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6, + 0xD6, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x95, + 0x95, 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55, + 0xD6, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x70, + 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x95, + 0x55, 0x55, 0x55, 0x95, 0x55, 0x55, 0xCB, 0x90, + 0x70, 0x90, 0xCB, 0x55, 0x55, 0xA1, 0xD8, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x88, 0xD8, 0xE1, 0x88, 0x20, 0x20, + 0x88, 0x88, 0xE6, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, + 0x55, 0x70, 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1, + 0xA1, 0x95, 0x55, 0x55, 0x95, 0x95, 0x55, 0x55, + 0x90, 0x90, 0x90, 0x90, 0xCB, 0x55, 0x55, 0x55, + 0xD6, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0xCB, 0x70, + 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x55, + 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x95, 0x2C, 0x95, 0x2C, 0xD6, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x80, 0xD6, 0xA1, 0xD6, 0xD6, 0xA1, + 0xCB, 0x70, 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, + 0x2C, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, + 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x94, + 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95, 0xCB, 0x55, + 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x95, 0xA1, + 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x95, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x88, 0x95, 0xA1, 0xA1, 0xA1, 0x55, + 0x70, 0x94, 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95, + 0xCB, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55, + 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, + 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70, + 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x70, 0x90, 0xCB, + 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x2C, 0xD6, + 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x70, 0x20, 0x20, + 0x88, 0x43, 0xD8, 0x43, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x88, 0x88, 0x43, 0x2B, 0xD8, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x3F, 0x2C, 0x95, 0x95, 0xCB, + 0x70, 0x70, 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90, + 0x90, 0xCB, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x95, + 0x2C, 0xD6, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C, + 0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x90, 0x55, + 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70, 0x55, 0x95, + 0x95, 0xCB, 0x90, 0x90, 0x90, 0x95, 0x2C, 0xA1, + 0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x70, 0x20, 0x20, + 0x80, 0x2B, 0x34, 0x2B, 0x88, 0x20, 0x20, 0x20, + 0x88, 0xB1, 0x28, 0x28, 0x2B, 0x7D, 0x80, 0x20, + 0x20, 0x20, 0x20, 0x92, 0x95, 0x55, 0xCB, 0x70, + 0x90, 0x55, 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70, + 0x55, 0x95, 0x55, 0x55, 0x90, 0x90, 0x90, 0x55, + 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95, + 0xA1, 0x95, 0x55, 0xCB, 0x90, 0x70, 0xCB, 0x95, + 0xA1, 0x95, 0x95, 0xCB, 0x90, 0xCB, 0x95, 0x2C, + 0x95, 0x70, 0x70, 0x90, 0x55, 0x2C, 0xA1, 0xA1, + 0x2C, 0x2C, 0x55, 0xCB, 0x55, 0x90, 0x20, 0x34, + 0x90, 0x6D, 0x70, 0xD8, 0x43, 0x20, 0x20, 0x88, + 0x3F, 0x55, 0xA1, 0x2A, 0xD6, 0x7D, 0x43, 0x20, + 0x20, 0x20, 0x88, 0x7D, 0x55, 0xCB, 0x90, 0x70, + 0xCB, 0x95, 0xA1, 0x95, 0x95, 0xCB, 0x70, 0xCB, + 0x95, 0xA1, 0x95, 0x70, 0x70, 0xCB, 0x55, 0x2C, + 0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95, + 0x2C, 0x55, 0x90, 0x70, 0x94, 0x90, 0x95, 0x2C, + 0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95, 0xA1, 0xA1, + 0x95, 0x90, 0x90, 0x95, 0xA1, 0xD6, 0xD6, 0x6D, + 0xA1, 0x95, 0x55, 0xCB, 0x55, 0xCB, 0x20, 0x99, + 0xBF, 0xA3, 0xA3, 0x90, 0x20, 0x20, 0x20, 0x92, + 0x83, 0x6B, 0x6B, 0x6B, 0xA3, 0x70, 0x88, 0x20, + 0x20, 0x20, 0x20, 0x2B, 0x90, 0x70, 0x94, 0x90, + 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95, + 0xA1, 0x2C, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xD6, + 0xD6, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55, + 0x2C, 0x55, 0x70, 0x70, 0x94, 0x90, 0x95, 0x2C, + 0x2C, 0x55, 0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x2C, + 0x55, 0x55, 0x95, 0xA1, 0x6D, 0xBF, 0x6D, 0xD6, + 0x95, 0x55, 0x90, 0xCB, 0x55, 0x95, 0x88, 0x95, + 0x2C, 0x3F, 0x6D, 0x6B, 0x34, 0x20, 0x20, 0x47, + 0x65, 0xD6, 0xE1, 0x3F, 0x2A, 0x6B, 0x2B, 0x20, + 0x20, 0x20, 0x20, 0x43, 0x70, 0x70, 0x94, 0x90, + 0x95, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x95, 0x2C, + 0xA1, 0x2C, 0x55, 0xCB, 0x95, 0xA1, 0x6D, 0xBF, + 0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95, + 0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1, + 0x2C, 0x55, 0xCB, 0x55, 0x2C, 0x95, 0x2C, 0x95, + 0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6, 0x95, + 0x70, 0x94, 0x94, 0x70, 0x55, 0x55, 0x20, 0xBF, + 0xC9, 0xB1, 0x99, 0x42, 0xB1, 0x61, 0x7D, 0x94, + 0x65, 0xB1, 0x88, 0x99, 0xD5, 0xE5, 0x7F, 0x20, + 0x20, 0x20, 0x20, 0x43, 0x70, 0x94, 0x70, 0x55, + 0x2C, 0xA1, 0x2C, 0x55, 0x90, 0x55, 0x2C, 0x95, + 0x2C, 0x95, 0x95, 0x2C, 0xA1, 0x6D, 0xBF, 0xBF, + 0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55, + 0x55, 0xCB, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xA1, + 0x95, 0x55, 0x55, 0x95, 0x2C, 0x95, 0x95, 0x95, + 0x95, 0xA1, 0x6D, 0x2A, 0x2A, 0xD6, 0x55, 0x94, + 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x95, 0x20, 0x2A, + 0xD8, 0x43, 0xC9, 0x83, 0x98, 0x79, 0x34, 0x9F, + 0x6B, 0x43, 0x20, 0x88, 0x2B, 0x65, 0xA0, 0x20, + 0x20, 0x20, 0x20, 0xE1, 0x70, 0x94, 0x70, 0x95, + 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x95, 0x2C, 0x95, + 0x95, 0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6, + 0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55, + 0x94, 0x70, 0x94, 0x47, 0x70, 0x95, 0x2C, 0x2C, + 0x95, 0xCB, 0x95, 0x2C, 0x2C, 0xA1, 0x2C, 0x2C, + 0xA1, 0xD6, 0x6D, 0x6D, 0xA1, 0xCB, 0x47, 0x28, + 0xE6, 0x47, 0x70, 0x55, 0x95, 0xA1, 0x20, 0x2C, + 0x7F, 0x88, 0xF0, 0xC6, 0x25, 0x5E, 0xCF, 0x2F, + 0xE7, 0x9A, 0x20, 0x88, 0x99, 0x65, 0x3F, 0x20, + 0x20, 0x20, 0x20, 0x34, 0x94, 0x47, 0x70, 0x95, + 0xA1, 0x2C, 0x55, 0xCB, 0x95, 0x2C, 0x2C, 0xA1, + 0x2C, 0x2C, 0xA1, 0xD6, 0x6D, 0x6D, 0xA1, 0xCB, + 0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95, + 0x47, 0x70, 0x90, 0x94, 0x70, 0x95, 0xA1, 0x2C, + 0x55, 0x55, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, + 0xA1, 0x6D, 0x2A, 0xD6, 0x55, 0x47, 0x28, 0x28, + 0x47, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0x20, 0x28, + 0xEC, 0x86, 0xBE, 0x48, 0x3E, 0x3E, 0x3A, 0x25, + 0x4E, 0xAE, 0x93, 0xD7, 0xEC, 0xD1, 0x34, 0x20, + 0x20, 0x20, 0x20, 0x43, 0x55, 0x94, 0x70, 0x95, + 0xA1, 0xA1, 0x55, 0xCB, 0x2C, 0xA1, 0xA1, 0xA1, + 0xA1, 0x2C, 0xA1, 0x6D, 0x6D, 0xD6, 0x55, 0x47, + 0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C, + 0x95, 0x95, 0x55, 0x90, 0xCB, 0x2C, 0xA1, 0xA1, + 0x55, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0xA1, 0x2C, + 0xD6, 0x6D, 0x6D, 0xA1, 0x70, 0x28, 0xD5, 0xE6, + 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0x20, 0xE1, + 0x26, 0x84, 0x76, 0x73, 0x9C, 0x22, 0x4E, 0x35, + 0x8C, 0x7A, 0x4E, 0xDC, 0x8E, 0x7E, 0x3D, 0x88, + 0x20, 0x20, 0x20, 0x88, 0x2C, 0x90, 0x90, 0x95, + 0xA1, 0x2C, 0x55, 0x55, 0x2C, 0xD6, 0xD6, 0xD6, + 0x2C, 0x2C, 0xD6, 0x2A, 0x6D, 0x2C, 0x70, 0x28, + 0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1, + 0xBF, 0xA1, 0x95, 0xCB, 0xCB, 0x2C, 0xA1, 0xA1, + 0x95, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C, 0x95, + 0xD6, 0x6D, 0xD6, 0x95, 0x94, 0x28, 0xE6, 0x70, + 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xD6, 0x20, 0x57, + 0xE4, 0xDF, 0x50, 0x3E, 0x22, 0x4E, 0x35, 0x8C, + 0x8C, 0x52, 0x52, 0x7A, 0x4E, 0x58, 0xD7, 0x20, + 0x20, 0x20, 0x20, 0x88, 0x2C, 0xCB, 0x55, 0x2C, + 0xA1, 0xA1, 0x95, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, + 0x2C, 0x95, 0xA1, 0x6D, 0x6D, 0x95, 0x47, 0xA0, + 0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, + 0xD2, 0x95, 0x55, 0x90, 0x55, 0x2C, 0xD6, 0xA1, + 0x95, 0x95, 0xA1, 0xD6, 0xD6, 0x2C, 0x95, 0x2C, + 0xA1, 0x6D, 0xA1, 0x55, 0x94, 0x47, 0x94, 0xCB, + 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0x59, 0xC8, + 0xE3, 0x76, 0x2D, 0x3E, 0x22, 0x4E, 0x8C, 0x35, + 0x52, 0x52, 0xEE, 0x3A, 0x4D, 0xED, 0x24, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x28, 0xCB, 0x55, 0x2C, + 0xD6, 0xA1, 0x95, 0x95, 0xA1, 0xD6, 0xA1, 0x2C, + 0x95, 0x2C, 0xD6, 0x6D, 0xA1, 0x55, 0x94, 0xE6, + 0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, + 0xD0, 0x94, 0x94, 0x90, 0x55, 0x2C, 0xA1, 0xA1, + 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x2C, + 0xA1, 0xD6, 0x2C, 0x70, 0x94, 0x94, 0x94, 0x94, + 0x70, 0x55, 0xA1, 0xD6, 0xA1, 0xD6, 0x88, 0x77, + 0x38, 0xC4, 0x3E, 0x69, 0x4E, 0x35, 0x8C, 0xEE, + 0x35, 0x89, 0x30, 0x30, 0x4A, 0x48, 0x3C, 0x20, + 0x20, 0x88, 0x20, 0x20, 0xD8, 0x2C, 0x55, 0x2C, + 0xD6, 0xA1, 0x95, 0x95, 0x2C, 0xD6, 0xA1, 0x2C, + 0x95, 0x2C, 0xA1, 0xD6, 0x2C, 0x90, 0x94, 0x47, + 0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95, + 0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C, + 0x95, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, + 0xA1, 0xA1, 0x55, 0x70, 0x94, 0x47, 0x94, 0x94, + 0x70, 0x2C, 0xD6, 0xD6, 0x2C, 0xA1, 0x43, 0x98, + 0x54, 0x48, 0x3E, 0x22, 0x35, 0xEE, 0xEE, 0x9C, + 0x4D, 0x45, 0x75, 0x4A, 0xDF, 0x7B, 0x3D, 0x20, + 0xD8, 0x28, 0x2B, 0x88, 0x20, 0x95, 0x95, 0x2C, + 0xA1, 0x2C, 0x55, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, + 0x2C, 0x95, 0xA1, 0x2C, 0x55, 0x70, 0x94, 0x94, + 0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95, + 0x70, 0x28, 0x47, 0x55, 0x95, 0x2C, 0x2C, 0x2C, + 0x95, 0x95, 0x95, 0xA1, 0xA1, 0xA1, 0x95, 0x55, + 0x95, 0x95, 0x55, 0x70, 0x70, 0x70, 0x94, 0x70, + 0x55, 0xD6, 0x6D, 0xD6, 0x95, 0x2C, 0x20, 0x43, + 0xBB, 0xC8, 0x36, 0x30, 0x30, 0x38, 0x45, 0x6E, + 0xE3, 0x75, 0x78, 0x37, 0xBD, 0xD9, 0x3F, 0x20, + 0x88, 0xD5, 0x70, 0xB1, 0x88, 0xA0, 0x95, 0x2C, + 0x2C, 0xA1, 0x95, 0x55, 0x95, 0xA1, 0xA1, 0xA1, + 0x2C, 0x55, 0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, + 0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55, + 0x94, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1, + 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x55, + 0x55, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0x95, + 0xA1, 0x6D, 0x4B, 0xD6, 0x55, 0xD6, 0x20, 0xD8, + 0xD6, 0x67, 0xDA, 0x4D, 0xED, 0x62, 0x78, 0x78, + 0x23, 0x84, 0x67, 0xF5, 0x4B, 0xBF, 0x90, 0x88, + 0x88, 0x2B, 0x47, 0x99, 0x20, 0x43, 0xD6, 0x2C, + 0x2C, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, + 0x95, 0x95, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB, + 0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, + 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, + 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, + 0x6D, 0x2A, 0x2A, 0xA1, 0x55, 0x55, 0x20, 0xD8, + 0x6D, 0xAB, 0x96, 0x7E, 0x64, 0x53, 0x36, 0x36, + 0xC6, 0x63, 0x6D, 0xD0, 0x6B, 0xE5, 0xA3, 0x7D, + 0x20, 0x88, 0x80, 0x88, 0x20, 0x20, 0xC9, 0xA1, + 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, + 0x95, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, + 0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55, + 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0xA1, + 0xA1, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x95, + 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6, + 0x6D, 0x6D, 0xA1, 0x55, 0x2C, 0xD8, 0x20, 0xB1, + 0xA3, 0x4B, 0x6D, 0xD9, 0xA7, 0x6C, 0xAF, 0xB2, + 0x6D, 0x2A, 0x83, 0x42, 0xE5, 0xE5, 0x65, 0x2C, + 0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x88, 0x95, + 0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, + 0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1, + 0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55, + 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x2C, + 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95, + 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xA1, + 0xA1, 0x2C, 0x55, 0x55, 0x28, 0x88, 0x43, 0x2A, + 0xE5, 0xA3, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, + 0xBF, 0xA3, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0x65, + 0xB1, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0xD8, + 0xD6, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x2C, + 0x95, 0x95, 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, + 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x90, 0x90, 0x55, + 0x90, 0xCB, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, + 0x2C, 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x55, + 0x55, 0xCB, 0x55, 0x2C, 0x95, 0x95, 0x95, 0x95, + 0x55, 0x90, 0x90, 0x90, 0xE1, 0x43, 0x28, 0xE5, + 0xE5, 0x65, 0xD0, 0x6D, 0x6D, 0x6D, 0x2A, 0xD2, + 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xD6, 0x20, 0x20, 0x20, 0x20, 0x20, 0x88, 0x88, + 0xD5, 0x2C, 0x2C, 0x2C, 0x95, 0x55, 0x95, 0x95, + 0x95, 0x55, 0x55, 0xCB, 0x55, 0x95, 0x2C, 0x95, + 0x95, 0x95, 0x55, 0x90, 0x70, 0x70, 0x70, 0x90, + 0x70, 0x70, 0xCB, 0x55, 0x55, 0x95, 0x95, 0x95, + 0x2C, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0xCB, + 0x70, 0x70, 0x70, 0xCB, 0x90, 0x90, 0x70, 0x94, + 0x94, 0x94, 0x2C, 0x80, 0x20, 0xE1, 0xA3, 0xE5, + 0xE5, 0xE5, 0x42, 0xEC, 0xD0, 0x83, 0xA3, 0x65, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0x65, 0x7D, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x88, 0x2C, 0x95, 0x95, 0x95, 0x55, 0x55, 0x55, + 0x55, 0xCB, 0x70, 0x70, 0x90, 0x90, 0x90, 0x90, + 0x70, 0x94, 0x94, 0x94, 0x70, 0x70, 0x70, 0x70, + 0x70, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95, 0x95, + 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, + 0x90, 0x70, 0x90, 0x55, 0x55, 0xCB, 0x70, 0x94, + 0x94, 0x95, 0xD8, 0x20, 0x88, 0x70, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0x47, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0xE1, 0x6D, 0x2C, 0x95, 0x55, 0x55, 0x55, + 0x55, 0x55, 0x90, 0x70, 0x70, 0x55, 0x55, 0xCB, + 0x70, 0x94, 0x94, 0x94, 0x70, 0x90, 0x70, 0x94, + 0x55, 0x2C, 0x2C, 0x2C, 0x95, 0x2C, 0x95, 0x95, + 0x2C, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x55, 0x55, + 0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x90, + 0x55, 0x99, 0x20, 0x20, 0xE1, 0xA3, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xD6, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x2B, 0x6D, 0x95, 0x95, 0x55, 0x55, + 0x55, 0x55, 0xCB, 0x55, 0x95, 0x2C, 0x2C, 0x95, + 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x90, 0x70, + 0x2C, 0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x95, 0x95, + 0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, + 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x55, 0x95, + 0xE6, 0x88, 0x20, 0x20, 0x3F, 0xA3, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0x42, 0xA3, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x88, 0x2B, 0xD6, 0x95, 0x95, 0x95, + 0x95, 0x95, 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x95, + 0x55, 0x55, 0x95, 0x95, 0x95, 0x55, 0x55, 0x55, + 0xA1, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x2C, + 0x2C, 0x2C, 0x95, 0x2C, 0x95, 0x95, 0x55, 0x95, + 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0xCB, 0xCB, 0x94, + 0x20, 0x20, 0x20, 0x20, 0xE6, 0x83, 0x65, 0xE5, + 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0x6B, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0x6B, 0xA3, 0xD2, + 0xD2, 0x6B, 0xC9, 0x20, 0x20, 0x88, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x88, 0x8A, 0xA1, 0x95, 0x95, + 0x95, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0xCB, + 0xCB, 0x55, 0x95, 0x95, 0x95, 0x55, 0x55, 0x95, + 0x6D, 0x6D, 0x6D, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, + 0x2C, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, + 0x95, 0x95, 0x95, 0x55, 0x70, 0x70, 0x2C, 0x80, + 0x88, 0x20, 0x20, 0x80, 0x94, 0xD6, 0x32, 0x6B, + 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xA3, 0xD2, 0xD0, 0xBF, 0x2A, + 0x2A, 0xD0, 0x6D, 0x34, 0x20, 0xE1, 0x88, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x88, 0xA1, 0x95, 0x95, + 0x95, 0x95, 0x95, 0x95, 0x95, 0x55, 0x70, 0x70, + 0x70, 0x90, 0xCB, 0xCB, 0xCB, 0x95, 0x95, 0x2C, + 0xD0, 0x6D, 0xD6, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C, + 0x2C, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x55, 0x95, + 0x95, 0x2C, 0x95, 0x55, 0xCB, 0xCB, 0x95, 0x88, + 0x20, 0x20, 0x88, 0xD8, 0x2C, 0xD1, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0xEC, + 0xBF, 0x2A, 0xEC, 0x95, 0x20, 0x34, 0x2B, 0xE1, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x99, 0x95, 0x55, + 0x55, 0x55, 0x95, 0x95, 0x95, 0x55, 0xCB, 0xCB, + 0x55, 0x55, 0xCB, 0xCB, 0xCB, 0x55, 0x95, 0x95, + 0x32, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, + 0xA1, 0x95, 0x95, 0x95, 0x55, 0xCB, 0xCB, 0x55, + 0x95, 0x95, 0x95, 0x95, 0x95, 0x55, 0x99, 0x20, + 0xE1, 0xE1, 0x43, 0x47, 0x6B, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0x42, 0xEC, 0xBF, 0xA3, 0x8A, 0x20, 0x88, 0xD8, + 0x2B, 0x20, 0x20, 0x20, 0x88, 0x88, 0x2C, 0xCB, + 0xCB, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x55, 0x95, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x95, 0x55, 0x95, + 0x6D, 0x55, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x95, + 0x2C, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0x95, + 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x34, 0x20, + 0xC9, 0x20, 0xE1, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xA3, 0x83, 0x6D, 0x20, 0x88, 0x88, + 0x2B, 0x34, 0x20, 0x20, 0x20, 0x88, 0xD5, 0x55, + 0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, + 0x95, 0x95, 0x95, 0x95, 0x55, 0x55, 0x95, 0x95, + 0x2C, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x55, 0x95, + 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, + 0x2C, 0x95, 0x95, 0x55, 0x95, 0x2C, 0x20, 0xD8, + 0xE1, 0x20, 0x70, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0x65, 0xA3, 0x92, 0x43, 0x7D, + 0xD8, 0xC9, 0x88, 0x20, 0x20, 0x20, 0x43, 0xD6, + 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x55, 0x95, 0x2C, + 0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95, 0x2C, + 0xA1, 0x55, 0x55, 0x55, 0x55, 0x95, 0x95, 0x55, + 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0xA1, 0x2C, + 0xA1, 0x2C, 0x2C, 0x95, 0x2C, 0x99, 0x88, 0xB1, + 0x20, 0xD8, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x34, 0x8A, + 0xC9, 0x34, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x90, + 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x95, 0x2C, + 0x2C, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, + 0xD6, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, + 0x55, 0xCB, 0x55, 0x2C, 0x2C, 0xA1, 0x2C, 0xA1, + 0xA1, 0xA1, 0x2C, 0x2C, 0x6D, 0x43, 0xD8, 0x80, + 0x88, 0xCB, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x32, 0x80, 0xE1, + 0x80, 0x20, 0xB1, 0x20, 0x20, 0x20, 0x20, 0xC9, + 0xD6, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1, 0x2C, 0x2C, + 0x2C, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55, + 0xD6, 0x95, 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x2C, + 0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95, 0x2C, + 0x2C, 0x2C, 0x2C, 0x95, 0xCB, 0x20, 0xC9, 0x20, + 0xE1, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xD8, 0x20, + 0x20, 0x20, 0x2B, 0x43, 0x20, 0x20, 0x20, 0x88, + 0xD6, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x55, + 0x95, 0x55, 0x55, 0xCB, 0x55, 0xCB, 0xCB, 0x55, + 0x2C, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0x95, + 0x55, 0x95, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, + 0x55, 0xCB, 0x70, 0xCB, 0xC9, 0x80, 0x2B, 0x20, + 0xA0, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x92, 0x20, + 0x20, 0x20, 0xE1, 0xD8, 0x20, 0x20, 0x20, 0x20, + 0x95, 0x95, 0x55, 0xCB, 0x90, 0x90, 0x70, 0x90, + 0x90, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55, 0x95, + 0x95, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, + 0x95, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x55, + 0x90, 0x47, 0xA0, 0x55, 0x20, 0x2B, 0x43, 0x88, + 0x6D, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x28, 0x20, + 0x20, 0x20, 0xE1, 0xE1, 0x20, 0x20, 0x20, 0x20, + 0x28, 0x55, 0x90, 0x47, 0xA0, 0x47, 0x94, 0x70, + 0x55, 0x95, 0x95, 0x55, 0xCB, 0x55, 0x55, 0x2C, + 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, + 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x55, + 0x94, 0xE6, 0x70, 0x2B, 0x88, 0x2B, 0x88, 0xE1, + 0x65, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x47, 0x20, + 0x20, 0x20, 0xE1, 0x34, 0x20, 0x20, 0x20, 0x20, + 0xB1, 0x95, 0x94, 0xE6, 0xA0, 0x47, 0x70, 0x55, + 0x2C, 0xA1, 0x2C, 0x55, 0x90, 0xCB, 0x2C, 0xD6, + 0x6D, 0xA1, 0x2C, 0x95, 0x95, 0xA1, 0x2C, 0xA1, + 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x55, + 0x70, 0xE6, 0x70, 0x20, 0x20, 0x7D, 0x20, 0x8A, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0x65, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x94, 0x20, + 0x20, 0x20, 0xD8, 0x88, 0x20, 0x20, 0x20, 0x20, + 0xD8, 0x2C, 0x94, 0x47, 0x47, 0x90, 0x95, 0x95, + 0xA1, 0x6D, 0xA1, 0x90, 0x94, 0x55, 0x2C, 0xD6, + 0xD0, 0xA1, 0x95, 0x95, 0x2C, 0x2C, 0xA1, 0x2C, + 0x95, 0x95, 0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C, + 0xCB, 0x95, 0xD8, 0x20, 0x20, 0xB1, 0x88, 0x28, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE2, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20, + 0x20, 0x20, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x88, 0xD6, 0x55, 0x47, 0x94, 0x55, 0x2C, 0xA1, + 0xA1, 0xD6, 0x95, 0x94, 0x94, 0x55, 0xD6, 0x6D, + 0xBF, 0x95, 0x90, 0xCB, 0x2C, 0x2C, 0x2C, 0x2C, + 0x55, 0x95, 0xCB, 0x90, 0x90, 0x95, 0x2C, 0x95, + 0x90, 0x70, 0x20, 0x20, 0x34, 0x8A, 0x20, 0x94, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20, + 0x20, 0x88, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x88, 0xD6, 0xCB, 0x47, 0x94, 0x55, 0xA1, 0xD6, + 0xD6, 0x2C, 0xCB, 0x47, 0x70, 0xA1, 0x6D, 0x2A, + 0x95, 0x47, 0x47, 0x70, 0x95, 0xA1, 0x2C, 0x95, + 0x55, 0x55, 0x90, 0x90, 0x55, 0x55, 0x55, 0x90, + 0x47, 0xD5, 0x20, 0x20, 0x80, 0xD5, 0x43, 0xCB, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20, + 0x20, 0x80, 0x34, 0x20, 0x20, 0x20, 0x88, 0x20, + 0x20, 0x2C, 0x47, 0xE6, 0x70, 0x2C, 0xD6, 0xD6, + 0xA1, 0x2C, 0x55, 0xCB, 0x95, 0xA1, 0x6D, 0xD6, + 0x90, 0x47, 0x47, 0x90, 0x2C, 0xA1, 0x2C, 0x95, + 0x55, 0x55, 0x90, 0x90, 0x55, 0x55, 0x55, 0x70, + 0x94, 0x8A, 0x20, 0x88, 0x88, 0xE1, 0xD8, 0x95, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE2, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x47, 0x20, + 0x43, 0x7D, 0x43, 0x80, 0x88, 0x20, 0x20, 0x20, + 0x88, 0xCB, 0x94, 0x70, 0x55, 0xA1, 0xD6, 0xD6, + 0xA1, 0x2C, 0x2C, 0x95, 0xA1, 0xA1, 0xD6, 0xA1, + 0x94, 0xE6, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95, + 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB, + 0x55, 0xA0, 0x43, 0x86, 0x86, 0x43, 0xD8, 0xCB, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x3F, 0x80, + 0xD8, 0x80, 0x88, 0x34, 0xD8, 0x2B, 0xD8, 0x20, + 0x99, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, + 0xA1, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, + 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, + 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, + 0x95, 0x44, 0xBC, 0x3E, 0x5D, 0xD3, 0x79, 0x92, + 0xA3, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0x65, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x9A, 0x34, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x43, 0x99, 0xE1, + 0x70, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1, + 0x2C, 0x95, 0x55, 0x55, 0x95, 0x95, 0x95, 0x95, + 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95, + 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C, + 0x32, 0x9D, 0xEB, 0x5D, 0x69, 0x49, 0x84, 0xF0, + 0xB1, 0xEC, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xC1, 0x4E, 0x21, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x34, 0xC9, 0xD8, + 0xBB, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, + 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, + 0x55, 0xCB, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55, + 0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0x6D, 0xD0, + 0xC2, 0x48, 0x6A, 0x49, 0x69, 0x82, 0x5D, 0x2F, + 0x59, 0x7D, 0xBF, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xEA, 0xC7, 0x7E, 0x66, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x34, 0x43, 0x5A, + 0x46, 0x27, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, + 0x95, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, + 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0x55, + 0x94, 0x94, 0x2C, 0x2A, 0x72, 0x3B, 0x56, 0xDD, + 0xDF, 0x29, 0x5D, 0x49, 0x89, 0x5D, 0x3E, 0x69, + 0x93, 0x66, 0x34, 0xA1, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0x65, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xEA, 0x3E, 0x5A, 0x66, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x66, 0x5B, 0x73, + 0x89, 0x4C, 0xBF, 0x2C, 0x95, 0x2C, 0x2C, 0x95, + 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, + 0x2C, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0xCB, + 0x70, 0x55, 0xE7, 0x60, 0x4A, 0x48, 0xCD, 0x4A, + 0x29, 0x73, 0x5D, 0x82, 0x49, 0x49, 0x49, 0x49, + 0x3A, 0x57, 0x88, 0x88, 0x70, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0x42, 0x73, 0x50, 0xBE, 0x79, + 0x20, 0x20, 0x20, 0x20, 0x66, 0xCC, 0x37, 0x9C, + 0x3E, 0xCE, 0xBF, 0x95, 0x95, 0x95, 0x2C, 0x95, + 0x95, 0x55, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0x55, + 0xA1, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x94, + 0x94, 0xE8, 0x60, 0xC4, 0x3E, 0x2D, 0x2D, 0x2D, + 0x33, 0x5D, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x89, 0xAA, 0x59, 0x20, 0x20, 0x28, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xEC, 0x4A, 0x2D, 0x50, 0x78, 0x2E, + 0x57, 0x51, 0xF0, 0x57, 0x31, 0x4D, 0x50, 0x2D, + 0x5D, 0xF2, 0xA1, 0x2C, 0x95, 0x95, 0x55, 0x55, + 0x90, 0x90, 0x70, 0x90, 0xCB, 0x55, 0x55, 0x55, + 0x6D, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x55, 0x94, + 0x70, 0xB9, 0x75, 0x50, 0x3E, 0x49, 0x49, 0x49, + 0x5D, 0x82, 0x49, 0x49, 0x82, 0x49, 0x49, 0x49, + 0x89, 0x69, 0x4F, 0x20, 0x20, 0x20, 0x8A, 0x42, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0x83, 0x4A, 0x3A, 0x50, 0x62, 0x23, + 0x81, 0xB8, 0xB8, 0xE9, 0x5F, 0x29, 0x33, 0x5D, + 0x5D, 0x73, 0xE8, 0xCB, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, + 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x70, + 0xCB, 0x68, 0x75, 0x50, 0x82, 0x49, 0x49, 0x49, + 0x5D, 0x49, 0x49, 0x5D, 0x49, 0x49, 0x5D, 0x82, + 0x69, 0x5D, 0x25, 0xF0, 0x20, 0x20, 0x20, 0xE1, + 0x2A, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0x4B, 0xF4, 0xDF, 0x50, 0x73, 0x76, 0x48, + 0x75, 0xDF, 0x75, 0x62, 0xC4, 0x33, 0x82, 0x49, + 0x5D, 0x5D, 0xA8, 0xF5, 0x55, 0x55, 0x55, 0x55, + 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, + 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70, + 0x95, 0x83, 0x5F, 0xEA, 0x2D, 0x49, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x5D, 0x49, 0x22, 0x5A, 0x79, 0x20, 0x20, 0x20, + 0x80, 0xD2, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0x65, 0xD0, 0x63, 0x5F, 0x29, 0x2D, 0x2D, 0xEA, + 0x29, 0x29, 0x76, 0x50, 0x2D, 0x82, 0x49, 0x49, + 0x3E, 0x49, 0x5C, 0xB0, 0xBA, 0x95, 0x55, 0x55, + 0x2C, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C, + 0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x70, 0x55, + 0x2C, 0x83, 0x60, 0x76, 0x5D, 0x49, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x49, 0x5D, 0x89, 0xDC, 0x8B, 0x20, 0x20, 0x20, + 0x20, 0x95, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE2, 0x32, 0x85, 0xE3, 0x29, 0x2D, 0x33, 0x2D, + 0x2D, 0x2D, 0x6A, 0x2D, 0x33, 0x5D, 0x49, 0x82, + 0x49, 0x49, 0x82, 0x73, 0x5C, 0x9E, 0x2C, 0x55, + 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95, + 0x2C, 0x95, 0x55, 0xCB, 0x90, 0x90, 0xCB, 0x95, + 0x2C, 0x6D, 0x41, 0x6F, 0x3E, 0x49, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x49, 0x82, 0x3E, 0x4E, 0x38, 0xCA, 0x20, 0x20, + 0x20, 0x55, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x65, + 0x42, 0xA0, 0xD4, 0xE3, 0x29, 0x2D, 0x82, 0x5D, + 0x5D, 0x82, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x49, 0x3E, 0x49, 0x49, 0x49, 0x5C, 0x56, 0xD6, + 0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95, + 0xA1, 0x55, 0x90, 0x70, 0x94, 0x70, 0x95, 0x2C, + 0x2C, 0xD6, 0xDD, 0x6F, 0x33, 0x49, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x5D, 0x5D, 0x82, 0x69, 0x22, 0x62, 0x80, 0x34, + 0x94, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0x65, 0x6B, + 0xD5, 0x88, 0x5B, 0xE3, 0x29, 0x5D, 0x5D, 0x5D, + 0x5D, 0x5D, 0x5D, 0x5D, 0x49, 0x49, 0x49, 0x82, + 0x49, 0x49, 0x89, 0x49, 0x82, 0x49, 0x71, 0xBA, + 0x6D, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55, + 0x2C, 0x55, 0x70, 0x70, 0x70, 0x90, 0x95, 0xA1, + 0x2C, 0xA1, 0x41, 0x76, 0x5D, 0x5D, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x49, 0x5D, 0x82, 0x5D, 0x89, 0x5E, 0x96, 0x65, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xEC, 0xB1, + 0x20, 0x20, 0xCA, 0x23, 0x29, 0x33, 0x49, 0x5D, + 0x49, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49, 0x82, + 0x49, 0x82, 0x5D, 0x5D, 0x5D, 0x2D, 0x5C, 0x8F, + 0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95, + 0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1, + 0x95, 0xE8, 0x5F, 0x76, 0x33, 0x5D, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x3E, 0x9C, 0x2F, 0x68, + 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, + 0x65, 0xE5, 0x65, 0xE5, 0x6B, 0x90, 0x80, 0x20, + 0x20, 0x20, 0x4F, 0x81, 0x50, 0x3E, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x69, 0x69, 0x49, 0x5D, 0x2D, 0xC4, 0x46, 0xA3, + 0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55, + 0x55, 0xCB, 0x70, 0x47, 0x70, 0x95, 0xA1, 0xA1, + 0x95, 0xBD, 0x75, 0x2D, 0x33, 0x49, 0x49, 0x49, + 0x49, 0x49, 0x5D, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x5D, 0x2D, 0xB5, 0xDB, + 0xD6, 0x65, 0xE5, 0x65, 0xE5, 0xE5, 0x65, 0xE5, + 0x65, 0x65, 0x6B, 0x95, 0x2B, 0x88, 0x20, 0x20, + 0x20, 0x20, 0x8B, 0x81, 0x29, 0x33, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x49, 0x3E, 0x3E, 0x5E, 0x41, 0x97, 0x27, 0xD6, + 0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55, + 0x94, 0x70, 0x94, 0x94, 0x70, 0x55, 0xA1, 0x2C, + 0x6D, 0xC5, 0x39, 0x6A, 0x5D, 0x5D, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x3E, 0xEA, 0x30, 0x77, + 0xE1, 0xC9, 0x94, 0x2C, 0xD6, 0xD6, 0xA1, 0x55, + 0x47, 0x9F, 0x43, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x80, 0x91, 0x81, 0x6A, 0x2D, 0x49, 0x49, + 0x49, 0x5D, 0x5D, 0x49, 0x49, 0x5D, 0x5D, 0x82, + 0xEB, 0x4A, 0x41, 0xC2, 0x8F, 0xF5, 0xA1, 0x55, + 0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95, + 0x47, 0x70, 0x70, 0x94, 0x90, 0x95, 0xA1, 0x2C, + 0xE8, 0xA6, 0x39, 0x76, 0x50, 0x50, 0x2D, 0x2D, + 0x3E, 0x3E, 0x5D, 0x3E, 0x5D, 0x5D, 0x49, 0x82, + 0x49, 0x49, 0x49, 0x82, 0x82, 0x50, 0x75, 0xE0, + 0x57, 0x20, 0x88, 0x88, 0x20, 0x20, 0x88, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x79, 0x91, 0x81, 0x76, 0x33, 0x49, 0x49, + 0x5D, 0x82, 0x49, 0x49, 0x3E, 0x6A, 0xEA, 0x29, + 0xDF, 0x97, 0xBF, 0x6D, 0x6D, 0xD6, 0x55, 0x47, + 0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C, + 0x95, 0x95, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xA1, + 0xD6, 0x26, 0x45, 0x81, 0x5F, 0x30, 0x48, 0x6F, + 0x6F, 0x29, 0x29, 0x6A, 0x2D, 0x2D, 0x5D, 0x49, + 0x49, 0x49, 0x49, 0x49, 0x2D, 0x76, 0x6E, 0x77, + 0x5B, 0x66, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x79, 0xA9, 0xB8, 0x39, 0x50, 0x5D, 0x5D, + 0x5D, 0x5D, 0x3E, 0x2D, 0x29, 0x76, 0xCD, 0x37, + 0xB9, 0xA1, 0xA1, 0x6D, 0x6D, 0x2C, 0x94, 0x28, + 0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1, + 0xBF, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0xA1, 0x2C, + 0x95, 0x83, 0xDE, 0x87, 0xB6, 0xBE, 0x40, 0x6E, + 0x81, 0x81, 0x78, 0x78, 0x39, 0x6F, 0xEA, 0x2D, + 0x2D, 0x33, 0x33, 0x33, 0x76, 0x30, 0x64, 0x54, + 0x5B, 0x66, 0x20, 0x20, 0x66, 0x20, 0x88, 0x20, + 0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x88, 0x34, 0x8B, 0xF1, 0x23, 0x6F, 0x50, 0x2D, + 0x2D, 0x6A, 0x29, 0x6F, 0x78, 0x84, 0x9B, 0xD2, + 0x2C, 0x2C, 0xD6, 0x6D, 0x6D, 0x2C, 0x47, 0xA0, + 0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, + 0xD2, 0x95, 0x55, 0xCB, 0x55, 0x2C, 0xD6, 0xA1, + 0x95, 0x95, 0xA1, 0xD6, 0x6D, 0x6D, 0xBA, 0xF3, + 0x8D, 0x36, 0x74, 0x36, 0xF1, 0xB8, 0x23, 0x78, + 0x62, 0x4A, 0x29, 0x62, 0x23, 0xF1, 0x54, 0x31, + 0x57, 0x2B, 0x90, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, + 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C, 0xCB, + 0xE6, 0x7D, 0xCA, 0xB7, 0xB8, 0x75, 0x6F, 0x6F, + 0x76, 0x6F, 0x78, 0x81, 0x53, 0xBD, 0x6D, 0x2C, + 0x95, 0x95, 0xA1, 0x6D, 0xA1, 0x55, 0x94, 0xE6, + 0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, + 0xD0, 0x94, 0x94, 0x90, 0x95, 0x2C, 0xD6, 0xA1, + 0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x2C, + 0xD6, 0x68, 0xAB, 0x6C, 0xA4, 0x77, 0x77, 0xAD, + 0x40, 0x53, 0x6E, 0x40, 0xB7, 0x54, 0x31, 0xD7, + 0xAC, 0xD6, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55, + 0x95, 0x2C, 0x2C, 0xA1, 0x95, 0x95, 0x2C, 0xA1, + 0x6D, 0xD2, 0x7C, 0x54, 0xAD, 0x40, 0x6E, 0x81, + 0x81, 0x6E, 0x36, 0xDA, 0xE8, 0xD6, 0xD6, 0x2C, + 0x2C, 0x2C, 0xA1, 0xD6, 0x95, 0x90, 0x94, 0x47, + 0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95, + 0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C, + 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C, + 0x2C, 0xA1, 0x55, 0x70, 0x95, 0x2C, 0xB2, 0xB4, + 0xC3, 0xC3, 0x54, 0x54, 0xA9, 0x31, 0xCA, 0x2A, + 0x95, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95, + 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD6, + 0x6D, 0x2A, 0xB2, 0x4F, 0x31, 0x2E, 0xE0, 0xAD, + 0xB7, 0xC8, 0xB4, 0xF5, 0x2C, 0xA1, 0xA1, 0xA1, + 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x70, 0x94, 0x94, + 0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95, + 0x94, 0x28, 0x47, 0xCB, 0x95, 0x2C, 0xA1, 0xA1, + 0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x95, + 0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, 0x94, 0x2C, + 0x63, 0xBB, 0xA5, 0xD7, 0xCA, 0xB3, 0x6D, 0x2C, + 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0x95, + 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, + 0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF, + 0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1, + 0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70, + 0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55, + 0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1, + 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55, + 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95, + 0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95, + 0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95, + 0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1, + 0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D, + 0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, + 0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB, + 0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, + 0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, + 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, + 0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95, + 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95, + 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, + 0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C, + 0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C, + 0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, + 0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55, + 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, + 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95, + 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6, + 0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55, + 0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95, + 0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, + 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, + 0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, + 0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1, + 0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55 +}; + +#endif + +#ifdef INCLUDE_LINUX_LOGOBW + +unsigned char linux_logo_bw[] __initdata = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, + 0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, + 0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, + 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7, + 0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, + 0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, + 0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4, + 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C, + 0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF, + 0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF, + 0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29, + 0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F, + 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00, + 0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, + 0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF, + 0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19, + 0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E, + 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00, + 0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, + 0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF, + 0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11, + 0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06, + 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00, + 0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1, + 0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF, + 0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10, + 0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00, + 0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00, + 0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7, + 0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, + 0xFF, 0xC7, 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, + 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, 0x00, 0x01, + 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, + 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x9F, + 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, + 0xFF, 0x9F, 0x80, 0x00, 0x00, 0x01, 0x80, 0x18, + 0xFF, 0xFF, 0xFF, 0x9E, 0x80, 0x00, 0x00, 0x03, + 0xA8, 0x11, 0xFF, 0xFF, 0xFF, 0x9F, 0x80, 0x00, + 0x00, 0x02, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0x99, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x09, 0xFF, 0xFF, + 0xFF, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x01, + 0xFF, 0xFF, 0xFE, 0x20, 0x60, 0x00, 0x00, 0x00, + 0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x00, 0x30, 0x00, + 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0, 0x40, + 0x38, 0x00, 0x00, 0x00, 0xFE, 0x47, 0xFF, 0xFF, + 0x81, 0x00, 0x1C, 0x00, 0x00, 0x00, 0xFC, 0x23, + 0xFF, 0xFF, 0x90, 0x00, 0x1E, 0x00, 0x00, 0x00, + 0x78, 0x11, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x80, + 0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x00, + 0x07, 0xC0, 0x00, 0x00, 0x00, 0x08, 0xFF, 0xFF, + 0xC0, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x04, + 0x7F, 0xFF, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x10, + 0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x01, 0x80, + 0x00, 0x30, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, 0x4F, 0xFF, + 0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, + 0x0F, 0xFF, 0xC0, 0x00, 0x00, 0x80, 0x03, 0xF0, + 0x00, 0x00, 0x8F, 0xFF, 0x80, 0x00, 0x00, 0x40, + 0x0F, 0xF0, 0x00, 0x04, 0x1F, 0xFF, 0x80, 0x00, + 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x10, 0x1F, 0xFF, + 0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x40, + 0xFF, 0xFF, 0x98, 0x00, 0x00, 0xFF, 0xFF, 0xF0, + 0x00, 0x83, 0xFF, 0xFF, 0x81, 0xE0, 0x01, 0xFF, + 0xFF, 0xF8, 0x02, 0x07, 0xFF, 0xFF, 0x80, 0x3F, + 0x07, 0xE0, 0x00, 0x1C, 0x0C, 0x1F, 0xFF, 0xFF, + 0xF8, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0x78, 0x1F, + 0xFF, 0xFF, 0xFF, 0x80, 0x7F, 0x00, 0x07, 0x0F, + 0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFE, 0x0C, 0x07, + 0xFF, 0x83, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x00, 0x1F, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x07, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +}; + +#endif + +#ifdef INCLUDE_LINUX_LOGO16 + +unsigned char linux_logo16_red[] __initdata = { + 0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x35, 0x83, 0xa5, + 0x65, 0x8f, 0x98, 0xc9, 0xdb, 0xe1, 0xe7, 0xf8 +}; + +unsigned char linux_logo16_green[] __initdata = { + 0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x2e, 0x83, 0xa5, + 0x65, 0x6e, 0x98, 0x89, 0xbf, 0xac, 0xda, 0xf8 +}; + +unsigned char linux_logo16_blue[] __initdata = { + 0x00, 0x90, 0xaf, 0x9c, 0xf7, 0x2b, 0x82, 0xa5, + 0x65, 0x41, 0x97, 0x1e, 0x60, 0x29, 0xa5, 0xf8 +}; + +unsigned char linux_logo16[] __initdata = { + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa1, 0x11, 0x11, + 0x61, 0x16, 0x66, 0x66, 0x11, 0x11, 0x11, 0x11, + 0x11, 0x11, 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xa8, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x87, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x77, 0x73, 0x33, 0x33, 0x3a, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77, + 0x77, 0x27, 0x77, 0x77, 0x77, 0x33, 0x3a, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xa3, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x55, 0x50, 0x08, 0x33, 0x77, 0x77, + 0x77, 0x72, 0x72, 0x27, 0x77, 0x77, 0x33, 0x33, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xa3, 0x33, 0x33, 0x77, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x58, 0x85, 0x00, 0x11, 0x11, 0xaa, + 0xa3, 0x37, 0x77, 0x72, 0x22, 0x22, 0x77, 0x73, + 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, + 0x33, 0x37, 0x77, 0x33, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x56, 0x85, 0x00, 0x06, 0x66, 0x11, + 0x11, 0x1a, 0xa3, 0x37, 0x77, 0x72, 0x22, 0x77, + 0x73, 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, + 0x33, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x55, 0x00, 0x00, 0x06, 0x66, 0x66, + 0x66, 0x66, 0x11, 0x1a, 0xa3, 0x77, 0x72, 0x22, + 0x77, 0x73, 0x3a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, + 0x33, 0x33, 0x33, 0xa0, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11, + 0x66, 0x66, 0x66, 0x66, 0x11, 0xa3, 0x77, 0x22, + 0x22, 0x77, 0x33, 0x33, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33, + 0x33, 0x3a, 0xa1, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x33, + 0xaa, 0x11, 0x16, 0x66, 0x66, 0x61, 0x1a, 0x37, + 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x33, + 0x3a, 0xa1, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x22, + 0x22, 0x77, 0x3a, 0x11, 0x66, 0x66, 0x66, 0x1a, + 0x37, 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33, 0x3a, + 0xa1, 0x11, 0x11, 0x10, 0x00, 0x00, 0x50, 0x00, + 0x00, 0x05, 0x80, 0x50, 0x00, 0x00, 0x07, 0x72, + 0x22, 0x22, 0x22, 0x73, 0xa1, 0x66, 0x66, 0x61, + 0x1a, 0x77, 0x22, 0x27, 0x73, 0x33, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x3a, 0xaa, + 0x11, 0x11, 0x1a, 0xa0, 0x08, 0x71, 0x05, 0x00, + 0x00, 0x12, 0x22, 0x50, 0x00, 0x00, 0x07, 0x77, + 0x77, 0x72, 0x22, 0x22, 0x27, 0x31, 0x16, 0x66, + 0x61, 0x13, 0x77, 0x22, 0x77, 0x33, 0x3a, 0xaa, + 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xa1, + 0x11, 0x1a, 0x33, 0x70, 0x07, 0x2e, 0x70, 0x00, + 0x01, 0x44, 0x42, 0x60, 0x00, 0x00, 0x02, 0x22, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x31, 0x66, + 0x66, 0x61, 0xa3, 0x72, 0x22, 0x77, 0x33, 0xaa, + 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xaa, 0x11, + 0x1a, 0x33, 0x77, 0x30, 0x04, 0x82, 0x40, 0x00, + 0x54, 0x48, 0x54, 0x40, 0x00, 0x00, 0x01, 0xaa, + 0x32, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x31, + 0x66, 0x66, 0x11, 0x37, 0x22, 0x27, 0x73, 0x3a, + 0xaa, 0xaa, 0xa3, 0x33, 0x3a, 0xaa, 0xaa, 0xaa, + 0xa3, 0x77, 0xaa, 0x10, 0x50, 0x08, 0x46, 0x05, + 0x54, 0x80, 0x50, 0x42, 0x00, 0x00, 0x08, 0x66, + 0x66, 0x1a, 0x32, 0x22, 0x22, 0x22, 0x22, 0x27, + 0x31, 0x66, 0x66, 0x13, 0x72, 0x22, 0x77, 0x33, + 0xaa, 0xaa, 0xaa, 0x33, 0xaa, 0xa1, 0xaa, 0xa3, + 0x37, 0xa1, 0x1a, 0x30, 0x50, 0x06, 0x26, 0x00, + 0x54, 0x00, 0x00, 0x44, 0x00, 0x00, 0x08, 0xe2, + 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22, 0x22, + 0x27, 0xa6, 0x66, 0x61, 0xa7, 0x72, 0x27, 0x73, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, + 0x31, 0x11, 0x37, 0x70, 0x02, 0x00, 0xab, 0xbb, + 0xb6, 0x00, 0x00, 0xf4, 0x00, 0x00, 0xee, 0xee, + 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22, + 0x22, 0x23, 0x16, 0x66, 0x1a, 0x37, 0x22, 0x77, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x3a, + 0x11, 0xa7, 0x33, 0x10, 0x04, 0x09, 0xbd, 0xdd, + 0xbd, 0xd0, 0x04, 0x45, 0x00, 0x0e, 0xee, 0xee, + 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22, + 0x22, 0x22, 0x71, 0x66, 0x66, 0x13, 0x72, 0x27, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x11, + 0xa3, 0x73, 0xa1, 0x60, 0x08, 0xbd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdb, 0x90, 0x00, 0x02, 0xec, 0xee, + 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xce, 0x22, + 0x22, 0x22, 0x27, 0xa6, 0x66, 0x61, 0x37, 0x27, + 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x1a, + 0x33, 0xa1, 0x16, 0x60, 0x0b, 0xbd, 0xdd, 0xdd, + 0xcd, 0xdd, 0xdd, 0xd9, 0x00, 0x00, 0xec, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xce, 0xa2, + 0x22, 0x22, 0x22, 0x7a, 0x66, 0x66, 0x13, 0x77, + 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0x3a, 0x11, 0x33, + 0xaa, 0x11, 0x66, 0x60, 0x9b, 0xdd, 0xdd, 0xdd, + 0xcd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0xec, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x61, + 0x72, 0x22, 0x22, 0x22, 0xa1, 0x66, 0x61, 0x37, + 0x1a, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x13, 0x3a, + 0x11, 0x11, 0x11, 0x10, 0x5b, 0xdd, 0xdd, 0xdc, + 0xdd, 0xdd, 0xbd, 0xd9, 0x00, 0x00, 0xec, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x86, + 0x17, 0x22, 0x22, 0x22, 0x23, 0x16, 0x66, 0xaa, + 0xaa, 0xa3, 0x3a, 0xaa, 0xaa, 0x1a, 0x3a, 0xa1, + 0x11, 0x11, 0x1a, 0x70, 0x05, 0xbd, 0xdd, 0xdd, + 0xdb, 0x5b, 0xdd, 0xb0, 0x00, 0x60, 0x2e, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe6, 0x88, + 0x66, 0x32, 0x22, 0x22, 0x22, 0x36, 0x66, 0x11, + 0x33, 0x33, 0x3a, 0xaa, 0x11, 0xaa, 0xaa, 0xa1, + 0x11, 0x1a, 0x3a, 0x60, 0x02, 0x99, 0xbb, 0xb9, + 0x9b, 0xbb, 0xbc, 0x22, 0x00, 0x86, 0x5e, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe1, 0x68, + 0x86, 0x63, 0x22, 0x22, 0x22, 0x2a, 0x66, 0x66, + 0x33, 0x33, 0xaa, 0xaa, 0x1a, 0xaa, 0xaa, 0x11, + 0x1a, 0xa7, 0x68, 0x80, 0x02, 0x2b, 0xbd, 0xbb, + 0xbb, 0xb9, 0x22, 0x22, 0x00, 0x06, 0x6e, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc7, 0xa6, + 0x88, 0x86, 0x32, 0x22, 0x22, 0x27, 0xa6, 0x66, + 0x33, 0x3a, 0xaa, 0xa1, 0xaa, 0xaa, 0xa1, 0x11, + 0xa3, 0xa6, 0x88, 0x80, 0x02, 0x22, 0x9b, 0xbb, + 0xbb, 0x22, 0x24, 0xf4, 0x60, 0x00, 0x0c, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc2, 0x21, + 0x68, 0x88, 0x63, 0x22, 0x22, 0x22, 0x71, 0x66, + 0x33, 0x3a, 0x11, 0x11, 0xaa, 0xaa, 0x11, 0xaa, + 0x71, 0x88, 0x88, 0x00, 0x02, 0xe2, 0x26, 0x99, + 0x22, 0x22, 0x4f, 0xf4, 0x40, 0x00, 0x0c, 0xcc, + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x22, 0x22, + 0x16, 0x88, 0x86, 0xa2, 0x22, 0x22, 0x27, 0x11, + 0x33, 0xa1, 0x11, 0x11, 0xaa, 0x31, 0x1a, 0xa3, + 0x68, 0x88, 0x81, 0x00, 0x54, 0x42, 0x22, 0x22, + 0x22, 0x44, 0xff, 0xff, 0x48, 0x00, 0x00, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x22, + 0x21, 0x88, 0x88, 0x6a, 0x22, 0x22, 0x22, 0x31, + 0x3a, 0xa1, 0x11, 0x1a, 0xa3, 0x11, 0x33, 0x36, + 0x88, 0x86, 0x30, 0x00, 0x4f, 0x44, 0x22, 0x22, + 0x24, 0xff, 0xff, 0xff, 0x44, 0x00, 0x00, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x95, 0x22, 0x72, + 0x22, 0x18, 0x88, 0x86, 0x32, 0x22, 0x22, 0x27, + 0xaa, 0x11, 0x11, 0x1a, 0x31, 0x13, 0x33, 0x68, + 0x88, 0x6a, 0x00, 0x02, 0x4f, 0x4f, 0x42, 0x24, + 0x4f, 0xff, 0xff, 0xff, 0xf4, 0x50, 0x00, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x73, + 0x72, 0x26, 0x88, 0x88, 0x63, 0x22, 0x22, 0x22, + 0x11, 0x11, 0x11, 0xa3, 0xa1, 0x73, 0xa6, 0x88, + 0x81, 0xa5, 0x00, 0x04, 0x4f, 0x4f, 0x44, 0x4f, + 0xff, 0xff, 0xff, 0xff, 0xf4, 0x40, 0x00, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x12, 0x27, + 0xaa, 0x22, 0x68, 0x55, 0x86, 0x72, 0x22, 0x22, + 0x11, 0x11, 0x1a, 0x33, 0x13, 0x3a, 0x18, 0x88, + 0x1a, 0x10, 0x00, 0x44, 0x4f, 0x4f, 0xff, 0x4f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x61, 0x22, + 0x3a, 0xa2, 0x26, 0x85, 0x58, 0x67, 0x22, 0x22, + 0x61, 0x61, 0x1a, 0x7a, 0x37, 0x31, 0x88, 0x81, + 0x11, 0x00, 0x05, 0xe4, 0x44, 0xff, 0xff, 0xff, + 0x4f, 0xf4, 0x44, 0xff, 0xff, 0xf5, 0x00, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x88, 0x12, + 0x2a, 0xaa, 0x72, 0x68, 0x55, 0x81, 0x22, 0x22, + 0x66, 0x61, 0xa3, 0x33, 0x73, 0x16, 0x88, 0x11, + 0x10, 0x00, 0x08, 0x74, 0x44, 0x4f, 0x44, 0x44, + 0xf4, 0xf4, 0x44, 0x44, 0xe2, 0x44, 0x00, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x88, 0x81, + 0x22, 0xaa, 0xa7, 0x26, 0x85, 0x88, 0x12, 0x22, + 0x66, 0x61, 0x37, 0xa7, 0x3a, 0x66, 0x66, 0x11, + 0x80, 0x00, 0x0a, 0x72, 0x44, 0x4f, 0x44, 0x4f, + 0xff, 0x44, 0x44, 0x22, 0x22, 0x24, 0x00, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x85, 0x88, + 0x12, 0x2a, 0xaa, 0x22, 0x68, 0x58, 0x63, 0x22, + 0x66, 0x1a, 0x73, 0x77, 0x31, 0x66, 0x61, 0x11, + 0x00, 0x00, 0x07, 0x44, 0xff, 0x4f, 0xf4, 0x4f, + 0xff, 0x4f, 0x44, 0xf4, 0x42, 0x22, 0x40, 0x9b, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x85, 0x55, + 0x81, 0x27, 0xaa, 0xa2, 0x78, 0x88, 0x86, 0x72, + 0x66, 0x13, 0x77, 0x73, 0x11, 0x66, 0x61, 0x76, + 0x00, 0x50, 0x84, 0xf4, 0xff, 0x4f, 0xf4, 0xff, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x42, 0x40, 0x9b, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x68, 0x55, + 0x58, 0x12, 0x3a, 0xaa, 0x23, 0x88, 0x88, 0xa7, + 0x66, 0xa7, 0x77, 0x7a, 0x16, 0x66, 0x1a, 0x15, + 0x05, 0x00, 0x4f, 0xf4, 0xff, 0x4f, 0xf4, 0xff, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0x24, 0x9b, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x26, 0x55, + 0x55, 0x81, 0x23, 0xaa, 0x32, 0x18, 0x88, 0x6a, + 0x61, 0x37, 0x77, 0x31, 0x66, 0x66, 0x17, 0x60, + 0x05, 0x08, 0x4f, 0xf4, 0xff, 0x4f, 0xf4, 0xff, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x4e, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0xa2, 0x65, + 0x55, 0x58, 0xa2, 0x7a, 0xa2, 0x26, 0x88, 0x61, + 0x61, 0x32, 0x27, 0xa1, 0x66, 0x61, 0x31, 0x60, + 0x00, 0x04, 0x4f, 0xf4, 0xff, 0x44, 0x44, 0xff, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0xf4, 0x99, + 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x9b, 0xaa, 0x26, + 0x55, 0x55, 0x87, 0x27, 0x33, 0x27, 0x68, 0x61, + 0x1a, 0x72, 0x27, 0xa6, 0x66, 0x6a, 0x71, 0x00, + 0x80, 0x84, 0xff, 0xf4, 0xff, 0x44, 0x44, 0xff, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0xf4, 0x99, + 0x9b, 0x9b, 0x99, 0xb9, 0xb9, 0x99, 0xaa, 0xa2, + 0x85, 0x55, 0x56, 0x22, 0x27, 0x22, 0x36, 0x66, + 0x13, 0x22, 0x23, 0x16, 0x86, 0x63, 0x73, 0x00, + 0x00, 0x44, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0xff, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x4f, 0x99, + 0x9b, 0x99, 0x99, 0x99, 0xb9, 0x99, 0xaa, 0xaa, + 0x28, 0x55, 0x58, 0x12, 0x22, 0x22, 0x21, 0x11, + 0xa3, 0x27, 0x7a, 0x66, 0x86, 0x17, 0x75, 0x05, + 0x05, 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0xff, + 0xff, 0x4f, 0x44, 0x4f, 0x4f, 0x44, 0x4f, 0x99, + 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x3a, 0xaa, + 0xa2, 0x85, 0x58, 0x67, 0x72, 0x22, 0x27, 0xa1, + 0x37, 0x27, 0x7a, 0x68, 0x86, 0xa2, 0x70, 0x00, + 0x02, 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0x4f, + 0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0xf4, 0x99, + 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x23, 0xaa, + 0xa7, 0x78, 0x88, 0x81, 0x77, 0x22, 0x27, 0x3a, + 0x72, 0x73, 0x71, 0x68, 0x66, 0x32, 0x50, 0x00, + 0x04, 0x4f, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0x4f, + 0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0x44, 0x95, + 0x99, 0x99, 0x99, 0x99, 0x99, 0x55, 0x12, 0x3a, + 0xaa, 0x21, 0x88, 0x81, 0x77, 0x27, 0x73, 0x73, + 0x72, 0x33, 0x36, 0x86, 0x61, 0x72, 0x00, 0x00, + 0x04, 0x44, 0xf4, 0xf4, 0xf4, 0x44, 0x44, 0x4f, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x44, 0x55, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x8a, 0x27, + 0xaa, 0x77, 0x68, 0x61, 0x23, 0x71, 0x11, 0x3a, + 0x27, 0xa3, 0x36, 0x86, 0x61, 0x20, 0x00, 0x00, + 0x04, 0xf4, 0xf4, 0xf4, 0xf4, 0x44, 0x44, 0x4f, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x41, 0x59, + 0x99, 0x99, 0x99, 0x99, 0x99, 0x95, 0x58, 0x77, + 0x27, 0x32, 0x36, 0x63, 0x23, 0x71, 0x66, 0x11, + 0x27, 0x13, 0xa6, 0x86, 0x6a, 0x20, 0x00, 0x50, + 0x04, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x41, 0x99, + 0x9b, 0xbb, 0xbb, 0xbb, 0xb9, 0x99, 0x68, 0x13, + 0x32, 0x22, 0x73, 0xa7, 0x2a, 0x31, 0x88, 0x66, + 0x7a, 0x13, 0x18, 0x66, 0x63, 0x20, 0x00, 0x06, + 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f, + 0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x49, 0x95, + 0xa9, 0xa9, 0x99, 0x97, 0x92, 0x99, 0x65, 0x6a, + 0x17, 0x22, 0x23, 0x72, 0x27, 0xaa, 0x88, 0x88, + 0xa1, 0x17, 0x68, 0x66, 0x67, 0x70, 0x00, 0x05, + 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f, + 0xff, 0x4f, 0x44, 0xff, 0xf4, 0xf4, 0x49, 0x9c, + 0x2e, 0xee, 0xee, 0xee, 0xee, 0xa9, 0x65, 0x8a, + 0x1a, 0xaa, 0x37, 0x72, 0x27, 0x37, 0x88, 0x88, + 0x11, 0x17, 0x68, 0x66, 0x67, 0x10, 0x9d, 0xd0, + 0x84, 0x44, 0xff, 0x4f, 0x4f, 0x44, 0xf4, 0x4f, + 0xff, 0x4f, 0x44, 0xff, 0xf4, 0xf4, 0x4f, 0x69, + 0xcc, 0xee, 0xee, 0xee, 0xec, 0x99, 0x88, 0x63, + 0x61, 0x68, 0x61, 0x72, 0x22, 0x7a, 0x68, 0x88, + 0x11, 0x17, 0x88, 0x66, 0x12, 0x1b, 0xdd, 0xdd, + 0x02, 0x44, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f, + 0xff, 0x4f, 0x44, 0xff, 0xff, 0x4f, 0x4c, 0xc5, + 0x0c, 0xc1, 0x11, 0x1c, 0xc0, 0x26, 0x66, 0x17, + 0x66, 0x88, 0x88, 0x12, 0x22, 0x23, 0xa8, 0x88, + 0x11, 0x13, 0x88, 0x66, 0x17, 0xbb, 0xdd, 0xdd, + 0xd0, 0x8f, 0xff, 0xf4, 0xf4, 0x44, 0xf4, 0x4f, + 0xff, 0x4f, 0x44, 0xf4, 0x4f, 0x44, 0xdd, 0xdd, + 0x00, 0x00, 0x00, 0x05, 0x9d, 0x21, 0x66, 0x27, + 0xa6, 0x65, 0x58, 0x67, 0x22, 0x27, 0x28, 0x88, + 0x11, 0xaa, 0x86, 0x68, 0x1a, 0xbb, 0xdd, 0xdd, + 0xdb, 0x05, 0xf4, 0xf4, 0xf4, 0xf4, 0x44, 0x4f, + 0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0xdd, 0xdb, + 0x00, 0x00, 0x00, 0x00, 0xdd, 0xda, 0x66, 0x22, + 0x71, 0x15, 0x55, 0x81, 0x22, 0x22, 0x76, 0x88, + 0x11, 0x31, 0x88, 0x88, 0xab, 0xbd, 0xdd, 0xdd, + 0xdd, 0x00, 0x04, 0x44, 0xff, 0xff, 0x4f, 0x4f, + 0xff, 0x4f, 0x44, 0xf4, 0xf4, 0x44, 0xdd, 0xdb, + 0x00, 0x00, 0x00, 0x0b, 0xdd, 0xda, 0x11, 0x22, + 0x23, 0x68, 0x55, 0x86, 0x22, 0x22, 0x7a, 0x88, + 0x1a, 0x71, 0x88, 0x89, 0xbb, 0xdd, 0xdd, 0xdd, + 0xdd, 0xd0, 0x00, 0x4f, 0x44, 0xff, 0x4f, 0x4f, + 0xff, 0x4f, 0x44, 0xf4, 0xff, 0xe2, 0xdd, 0xdb, + 0x90, 0x00, 0x05, 0xbd, 0xdd, 0xb8, 0x63, 0x22, + 0x27, 0xa6, 0x55, 0x88, 0x77, 0x22, 0x22, 0x88, + 0x1a, 0x28, 0xbd, 0xdb, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdb, 0x00, 0x07, 0x44, 0x4f, 0x4f, 0x4f, + 0xff, 0x4f, 0x44, 0x4f, 0x4f, 0x22, 0xdd, 0xdb, + 0xbb, 0x9b, 0xbb, 0xbd, 0xdd, 0xd5, 0x86, 0x22, + 0x22, 0x77, 0x85, 0x88, 0x17, 0x22, 0x22, 0x88, + 0xaa, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0x00, 0x00, 0x54, 0x4f, 0x4f, 0x4f, + 0xff, 0x4f, 0x44, 0xf4, 0x44, 0x22, 0xbd, 0xdd, + 0xbb, 0xbb, 0xbb, 0xdd, 0xdd, 0xdd, 0x88, 0x72, + 0x27, 0x22, 0x88, 0x88, 0x67, 0x72, 0x22, 0x18, + 0x33, 0x2d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xd0, 0x00, 0x05, 0x4f, 0x4f, 0x4f, + 0xff, 0x4f, 0x44, 0x44, 0x4f, 0x22, 0xbd, 0xdd, + 0xdb, 0xbb, 0xdd, 0xdd, 0xdd, 0xdd, 0x88, 0x17, + 0x27, 0x72, 0x68, 0x88, 0x87, 0x32, 0x22, 0x36, + 0x37, 0x2d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xd5, 0x00, 0x00, 0x4f, 0x4f, 0x4f, + 0xff, 0xf4, 0xf4, 0xf4, 0xf4, 0x22, 0xbb, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x67, + 0x72, 0x77, 0x38, 0x88, 0x83, 0x37, 0x22, 0x26, + 0x72, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0x00, 0x00, 0x4f, 0x4f, 0x4f, + 0xff, 0xf4, 0xf4, 0xf4, 0x44, 0x25, 0xbb, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd3, + 0x32, 0x73, 0x76, 0x88, 0x81, 0x33, 0x22, 0x2a, + 0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xb0, 0x54, 0x4f, 0x4f, 0x4f, + 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x00, 0xbb, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xa7, 0x73, 0x26, 0x88, 0x86, 0x7a, 0x72, 0x27, + 0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0xff, 0x4f, 0x4f, + 0xff, 0xf4, 0xf4, 0x44, 0x40, 0x05, 0xbb, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0x13, 0x23, 0x21, 0x68, 0x86, 0x17, 0x72, 0x22, + 0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0x4f, 0x4f, 0x4f, + 0xff, 0xff, 0x44, 0x42, 0x00, 0x05, 0xbd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0x87, 0x27, 0x27, 0x16, 0x66, 0x67, 0x22, 0x22, + 0x72, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0x94, 0x44, 0x44, 0x44, + 0x44, 0x44, 0x44, 0x00, 0x00, 0x05, 0xbb, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb8, + 0x86, 0x22, 0x22, 0x7a, 0x68, 0x81, 0x22, 0x22, + 0x37, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x44, 0x44, 0x44, + 0x44, 0x47, 0x00, 0x00, 0x00, 0x05, 0xbd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x68, + 0x58, 0x72, 0x22, 0x27, 0x18, 0x86, 0x72, 0x22, + 0x1a, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x18, 0x85, + 0x58, 0x12, 0x22, 0x36, 0x18, 0x88, 0x32, 0x22, + 0x61, 0x3b, 0xbb, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd, + 0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x7a, 0x68, 0x85, + 0x88, 0x62, 0x27, 0x16, 0x18, 0x88, 0x12, 0x27, + 0x86, 0x18, 0x9b, 0xbb, 0xbb, 0xbb, 0xbb, 0xbd, + 0xdd, 0xdd, 0xdd, 0xbb, 0xb5, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0xbb, 0xbd, + 0xdd, 0xdd, 0xdb, 0xbb, 0x87, 0x31, 0x68, 0x65, + 0x88, 0x82, 0x23, 0x16, 0x18, 0x88, 0x12, 0x23, + 0x88, 0x67, 0x27, 0xa8, 0x9b, 0xbb, 0xbb, 0xbb, + 0xbd, 0xdd, 0xbb, 0xbb, 0x95, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x9b, 0xbb, + 0xbb, 0xbb, 0xbb, 0x96, 0x87, 0x16, 0x68, 0x18, + 0x88, 0x62, 0x31, 0x66, 0x18, 0x88, 0x62, 0x73, + 0x88, 0x63, 0x27, 0x33, 0x65, 0x55, 0x99, 0x9b, + 0xbb, 0xbb, 0xbb, 0x99, 0x55, 0x0a, 0xa1, 0x86, + 0x81, 0x68, 0x88, 0x55, 0x58, 0x85, 0x9b, 0xbb, + 0xbb, 0xbb, 0x95, 0x88, 0x83, 0x66, 0x66, 0x18, + 0x66, 0x82, 0xa1, 0x66, 0x18, 0x88, 0x62, 0x33, + 0x88, 0x81, 0x27, 0x7a, 0x18, 0x58, 0x86, 0x85, + 0x99, 0x99, 0x99, 0x95, 0x53, 0x2a, 0xaa, 0x88, + 0x67, 0x31, 0x68, 0x55, 0x58, 0x85, 0x59, 0xbb, + 0xbb, 0xb9, 0x58, 0x68, 0x83, 0x66, 0x61, 0x16, + 0x66, 0x62, 0x16, 0x66, 0x68, 0x88, 0x62, 0xaa, + 0x88, 0x86, 0x27, 0x77, 0x78, 0x55, 0x88, 0x22, + 0x25, 0x55, 0x95, 0x55, 0x6a, 0xa2, 0x2a, 0x88, + 0x62, 0x27, 0x37, 0x38, 0x88, 0x87, 0x55, 0x59, + 0x95, 0x58, 0x16, 0x88, 0x8a, 0x66, 0x63, 0x68, + 0x86, 0x67, 0x66, 0x66, 0x68, 0x88, 0x12, 0x11, + 0x88, 0x88, 0x72, 0x77, 0x78, 0x85, 0x58, 0x17, + 0x23, 0x32, 0x55, 0x55, 0x81, 0x13, 0x73, 0x66, + 0x62, 0x7a, 0xaa, 0x38, 0x88, 0x58, 0x27, 0x55, + 0x58, 0x32, 0x38, 0x88, 0x81, 0x66, 0xa2, 0x88, + 0x86, 0x61, 0x66, 0x61, 0x66, 0x68, 0x13, 0x11, + 0x88, 0x88, 0x12, 0x22, 0x71, 0x85, 0x58, 0x62, + 0x23, 0xa2, 0x68, 0x88, 0x81, 0x66, 0x88, 0x88, + 0x63, 0x2a, 0xaa, 0x28, 0x88, 0x55, 0x86, 0x61, + 0x66, 0x66, 0x68, 0x88, 0x66, 0x66, 0x77, 0x88, + 0x68, 0x16, 0x66, 0x62, 0x66, 0x68, 0xa1, 0x61, + 0x88, 0x88, 0x62, 0x22, 0x22, 0x85, 0x55, 0x83, + 0x72, 0x37, 0xa8, 0x88, 0x61, 0x66, 0x85, 0x55, + 0x86, 0x23, 0xaa, 0x71, 0x88, 0x85, 0x88, 0x66, + 0x88, 0x86, 0x88, 0x88, 0x16, 0x61, 0x21, 0x88, + 0x66, 0xa6, 0x86, 0x17, 0x66, 0x66, 0x31, 0x61, + 0x88, 0x88, 0x87, 0x72, 0x22, 0x68, 0x55, 0x86, + 0x77, 0x77, 0x36, 0x88, 0x13, 0x68, 0x85, 0x55, + 0x58, 0x12, 0x73, 0x72, 0x76, 0x88, 0x88, 0x68, + 0x88, 0x88, 0x88, 0x66, 0x36, 0x63, 0x26, 0x86, + 0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61, + 0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58, + 0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55, + 0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68, + 0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68, + 0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66, + 0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88, + 0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55, + 0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66, + 0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68, + 0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66, + 0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88, + 0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85, + 0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68, + 0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88, + 0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a +}; + +#endif diff --git a/include/lists.h b/include/lists.h new file mode 100644 index 0000000..804b5cd --- /dev/null +++ b/include/lists.h @@ -0,0 +1,77 @@ +#ifndef _LISTS_H_ +#define _LISTS_H_ + +#define LIST_START -1 /* Handy Constants that substitute for item positions */ +#define LIST_END 0 /* END_OF_LIST means one past current length of list when */ + /* inserting. Otherwise it refers the last item in the list. */ + +typedef struct + { + void *ptr; + unsigned int size; + } HandleRecord; + +typedef void **Handle; + +typedef int (*CompareFunction)(void *data1, void *data2) ; + +typedef struct ListStructTag + { + int signature; /* debugging aid */ + int percentIncrease; /* %of current size to increase by when list is out of space */ + int minNumItemsIncrease; /* fixed number of items to increase by when list is out of space */ + int listSize; /* number of items than can fit in the currently allocated memory */ + int itemSize; /* the size of each item in the list (same for every item) */ + int numItems; /* number of items currently in the list */ + unsigned char itemList[1]; /* resizable array of list elements */ + } ListStruct; + +typedef struct ListStructTag **list_t; /* The list abstract data type */ +typedef int ( * ListApplicationFunc)(int index, void *ptrToItem, void *callbackData); + +/* Basic List Operations */ +list_t ListCreate(int elementSize); +int ListNumItems(list_t list); +int ListInsertItem(list_t list, void *ptrToItem, int itemPosition); +int ListInsertItems(list_t list, void *ptrToItems, int firstItemPosition, int numItemsToInsert); +void ListDispose(list_t list); +void *ListGetPtrToItem(list_t list, int itemPosition); +void ListRemoveItem(list_t list, void *itemDestination, int itemPosition); +void ListRemoveItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToRemove); + +#if 0 /* rarely ever used; kept here for reference just in case ... */ +void ListDisposePtrList(list_t list); +void ListGetItem(list_t list, void *itemDestination, int itemPosition); +void ListReplaceItem(list_t list, void *ptrToItem, int itemPosition); +void ListRemoveItem(list_t list, void *itemDestination, int itemPosition); +void ListGetItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToGet); +void ListReplaceItems(list_t list, void *ptrToItems, int firstItemPosition, int numItemsToReplace); +void ListRemoveItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToRemove); +list_t ListCopy(list_t originalList); +int ListAppend(list_t list1, list_t list2); +void ListClear(list_t list); +int ListEqual(list_t list1, list_t list2); +int ListInsertInOrder(list_t list, void *ptrToItem, CompareFunction compareFunction); +void *ListGetDataPtr(list_t list); +int ListApplyToEach(list_t list, int ascending, ListApplicationFunc funcToApply, void *callbackData); + +/* List Searching and Sorting */ +int ListFindItem(list_t list, void *ptrToItem, int startingPosition, CompareFunction compareFunction); +void ListRemoveDuplicates(list_t list, CompareFunction compareFunction); +int ListBinSearch(list_t list, void *itemPtr, CompareFunction compareFunction); +void ListQuickSort(list_t list, CompareFunction compareFunction); +void ListHeapSort(list_t list, CompareFunction compareFunction); +void ListInsertionSort(list_t list, CompareFunction compareFunction); +int ListIsSorted(list_t list, CompareFunction compareFunction); + +/* Advanced List Functions */ +void ListSetAllocationPolicy(list_t list, int minItemsPerAlloc, int percentIncreasePerAlloc); +void ListCompact(list_t list); +int ListPreAllocate(list_t list, int numItems); +int ListGetItemSize(list_t list); +int GetIntListFromParmInfo(va_list parmInfo, int numIntegers, list_t *integerList); +int ListInsertAfterItem(list_t list, void *ptrToItem, void *ptrToItemToInsertAfter, CompareFunction compareFunction); +int ListInsertBeforeItem(list_t list, void *ptrToItem, void *ptrToItemToInsertBefore, CompareFunction compareFunction); +#endif /* 0 */ + +#endif /* _LISTS_H_ */ diff --git a/include/logbuff.h b/include/logbuff.h new file mode 100644 index 0000000..3acfc18 --- /dev/null +++ b/include/logbuff.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2002 + * Detlev Zundel, dzu@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _LOGBUFF_H +#define _LOGBUFF_H + +#ifdef CONFIG_LOGBUFFER + +#define LOGBUFF_LEN (16384) /* Must be 16k right now */ +#define LOGBUFF_MASK (LOGBUFF_LEN-1) +#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */ +#define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD) + +#define LOGBUFF_INITIALIZED (1<<31) + +int drv_logbuff_init (void); +void logbuff_init_ptrs (void); +void logbuff_log(char *msg); +void logbuff_reset (void); + +#endif /* CONFIG_LOGBUFFER */ + +#endif /* _LOGBUFF_H */ diff --git a/include/lpd7a400_cpld.h b/include/lpd7a400_cpld.h new file mode 100644 index 0000000..c70af09 --- /dev/null +++ b/include/lpd7a400_cpld.h @@ -0,0 +1,195 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Logic lh7a400-10 Card Engine CPLD interface + */ + +#ifndef __LPD7A400_CPLD_H_ +#define __LPD7A400_CPLD_H_ + + +/* + * IO Controller Address and Register Definitions + * - using LH7A400-10 Card Engine IO Controller Specification + * (logic PN: 70000079) + */ + +/*------------------------------------------------------------------ + * Slow Peripherals (nCS6) + */ +#define LPD7A400_CPLD_CF (0x60200000) +#define LPD7A400_CPLD_ISA (0x60400000) + +/*------------------------------------------------------------------ + * Fast Peripherals (nCS7) + * + * The CPLD directs access to 0x70000000-0x701fffff to the onboard + * ethernet controller + */ +#define LPD7A400_CPLD_WLAN_BASE (0x70000000) + +/* All registers are 8 bit */ +#define LPD7A400_CPLD_CECTL_REG (0x70200000) +#define LPD7A400_CPLD_SPIDATA_REG (0x70600000) +#define LPD7A400_CPLD_SPICTL_REG (0x70800000) +#define LPD7A400_CPLD_EEPSPI_REG (0x70a00000) +#define LPD7A400_CPLD_INTMASK_REG (0x70c00000) +#define LPD7A400_CPLD_MODE_REG (0x70e00000) +#define LPD7A400_CPLD_FLASH_REG (0x71000000) +#define LPD7A400_CPLD_PWRMG_REG (0x71200000) +#define LPD7A400_CPLD_REV_REG (0x71400000) +#define LPD7A400_CPLD_EXTGPIO_REG (0x71600000) +#define LPD7A400_CPLD_GPIODATA_REG (0x71800000) +#define LPD7A400_CPLD_GPIODIR_REG (0x71a00000) + +#define LPD7A400_CPLD_REGPTR (volatile u8*) + +/* Card Engine Control Register (section 3.1.2) */ +#define CECTL_SWINT (0x80) /* Software settable interrupt source + (routed to uP PF3) + 0 = generate interrupt, 1 = do not */ +#define CECTL_OCMSK (0x40) /* USB1 connection interrupt mask + 0 = not masked, 1 = masked */ +#define CECTL_PDRV (0x20) /* PCC_nDRV output + 0 = active, 1 = inactive */ +#define CECTL_USB1C (0x10) /* USB1 connection interrupt + 0 = active, 1 = inactive */ +#define CECTL_USB1P (0x08) /* USB1 Power enable + 0 = enabled, 1 = disabled */ +#define CECTL_AWKP (0x04) /* Auto-Wakeup enable + 0 = enabled, 1 = disabled */ +#define CECTL_LCDV (0x02) /* LCD VEE enable + 0 = disabled, 1 = enabled */ +#define CECTL_WLPE (0x01) /* Wired LAN power enable + 0 = enabled, 1 = disabled */ + +/* SPI Control Register (section 3.1.5) */ +#define SPICTL_SPLD (0x20) /* SPI load (R) + 0 = data reg. has not been loaded, shift + count has not been reset + 1 = data reg. loaded, shift count reset */ +#define SPICTL_SPST (0x10) /* SPI start (RW) + 0 = don't load data reg. and reset shift count + 1 = ready to load data reg and reset shift count */ +#define SPICTL_SPDN (0x08) /* SPI done (R) + 0 = not done + 1 = access done */ +#define SPICTL_SPRW (0x04) /* SPI read/write (RW) + 0 = SPI write access + 1 = SPI read access */ +#define SPICTL_STCS (0x02) /* SPI touch chip select (RW) + 0 = not selected + 1 = selected */ +#define SPICTL_SCCS (0x01) /* SPI CODEC chip select (RW) {not used} + 0 = not selected + 1 = selected */ + +/* EEPROM SPI Interface Register (section 3.1.6) */ +#define EEPSPI_EECS (0x08) /* EEPROM chip select (RW) + 0 = not selected + 1 = selected */ +#define EEPSPI_EECK (0x04) /* EEPROM SPI clock (RW) */ +#define EEPSPI_EETX (0x02) /* EEPROM SPI tx data (RW) */ +#define EEPSPI_EERX (0x01) /* EEPROM SPI rx data (R) */ + +/* Interrupt/Mask Register (section 3.1.7) */ +#define INTMASK_CMSK (0x80) /* CPLD_nIRQD interrupt mask (RW) + 0 = not masked + 1 = masked */ +#define INTMASK_CIRQ (0x40) /* interrupt signal to CPLD (R) + 0 = interrupt active + 1 = no interrupt */ +#define INTMASK_PIRQ (0x10) /* legacy, no effect */ +#define INTMASK_TMSK (0x08) /* Touch chip interrupt mask (RW) + 0 = not masked + 1 = masked */ +#define INTMASK_WMSK (0x04) /* Wired LAN interrupt mask (RW) + 0 = not masked + 1 = masked */ +#define INTMASK_TIRQ (0x02) /* Touch chip interrupt request (R) + 0 = interrupt active + 1 = no interrupt */ +#define INTMASK_WIRQ (0x01) /* Wired LAN interrupt request (R) + 0 = interrupt active + 1 = no interrupt */ + +/* Mode Register (section 3.1.8) */ +#define MODE_VS1 (0x80) /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R) + 0 = active slot VS1 pin is low + 1 = active slot VS1 pin is high */ +#define MODE_CD2 (0x40) /* PCMCIA Card Detect 2 input (PCC_nCD2) (R) + 0 = active slot CD2 is low + 1 = active slot CD2 is high */ +#define MODE_IOIS16 (0x20) /* PCMCIA IOIS16 input (PCC_nIOIS16) (R) + 0 = 16 bit access area + 1 = 8 bit access area */ +#define MODE_CD1 (0x10) /* PCMCIA Card Detect 1 input (PCC_nCD1) (R) + 0 = active slot CD1 is low + 1 = active slot CD1 is high */ +#define MODE_upMODE3 (0x08) /* Mode Pin 3 (R) + 0 = off-board boot device + 1 = on-board boot device (flash) */ +#define MODE_upMODE2 (0x04) /* Mode Pin 2 (R) (LH7A400 Little Endian only) + 0 = big endian + 1 = little endian */ +#define MODE_upMODE1 (0x02) /* Mode Pin 1 and Mode Pin 2 (R) */ +#define MODE_upMODE0 (0x01) /* - bus width at boot */ + + +/* Flash Register (section 3.1.9) */ +#define FLASH_FPOP (0x08) /* Flash populated (RW) + 0 = populated, 1 = not */ +#define FLASH_FST2 (0x04) /* Flash status (R) (RY/BY# pin for upper 16 bit chip + 0 = busy, 1 = ready */ +#define FLASH_FST1 (0x02) /* Flash status (R) (RY/BY# pin for lower 16 bit chip + 0 = busy, 1 = ready */ +#define FLASH_FPEN (0x01) /* Flash program enable (RW) + 0 = flash write protected + 1 = programming enabled */ + +/* Power Management Register (section 3.1.10) + * - when either of these is low an unmaskable interrupt to cpu + * is generated + */ +#define PWRMG_STBY (0x10) /* state of nSTANDBY signal to CPLD (R) + 0 = low, 1 = high */ +#define PWRMG_SPND (0x04) /* state of nSUSPEND signal to CPLD (R) + 0 = low, 1 = high */ + + +/* Extended GPIO Register (section 3.1.12) */ +#define EXTGPIO_STATUS1 (0x04) /* Status 1 output (RW) (uP_STATUS_1) + 0 = set pin low, 1 = set pin high */ +#define EXTGPIO_STATUS2 (0x02) /* Status 2 output (RW) (uP_STATUS_2) + 0 = set pin low, 1 = set pin high */ +#define EXTGPIO_GPIO1 (0x01) /* General purpose output (RW) (CPLD_GPIO_1) + 0 = set pin low, 1 = set pin high */ + +/* GPIO Data Register (section 3.1.13) */ +#define GPIODATA_GPIO2 (0x01) /* General purpose input/output (RW) (CPLD_GPIO_2) + 0 = set low (output) / read low (input) + 1 = set high (output) / read high (input) */ + +/* GPIO Direction Register (section 3.1.14) */ +#define GPIODIR_GPDR0 (0x01) /* GPIO2 direction (RW) + 0 = output, 1 = input */ + +#endif /* __LH7A400_H__ */ diff --git a/include/lxt971a.h b/include/lxt971a.h new file mode 100644 index 0000000..2b5b6d4 --- /dev/null +++ b/include/lxt971a.h @@ -0,0 +1,246 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $ + * @Author: Markus Pietrek + * @References: [1] NS9750 Hardware Reference, December 2003 + * [2] Intel LXT971 Datasheet #249414 Rev. 02 + * [3] NS7520 Linux Ethernet Driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifndef __LXT971A_H__ +#define __LXT971A_H__ + +/* PHY definitions (LXT971A) [2] */ +#define PHY_COMMON_CTRL (0x00) +#define PHY_COMMON_STAT (0x01) +#define PHY_COMMON_ID1 (0x02) +#define PHY_COMMON_ID2 (0x03) +#define PHY_COMMON_AUTO_ADV (0x04) +#define PHY_COMMON_AUTO_LNKB (0x05) +#define PHY_COMMON_AUTO_EXP (0x06) +#define PHY_COMMON_AUTO_NEXT (0x07) +#define PHY_COMMON_AUTO_LNKN (0x08) +#define PHY_LXT971_PORT_CFG (0x10) +#define PHY_LXT971_STAT2 (0x11) +#define PHY_LXT971_INT_ENABLE (0x12) +#define PHY_LXT971_INT_STATUS (0x13) +#define PHY_LXT971_LED_CFG (0x14) +#define PHY_LXT971_DIG_CFG (0x1A) +#define PHY_LXT971_TX_CTRL (0x1E) + +/* CTRL PHY Control Register Bit Fields */ +#define PHY_COMMON_CTRL_RESET (0x8000) +#define PHY_COMMON_CTRL_LOOPBACK (0x4000) +#define PHY_COMMON_CTRL_SPD_MA (0x2040) +#define PHY_COMMON_CTRL_SPD_10 (0x0000) +#define PHY_COMMON_CTRL_SPD_100 (0x2000) +#define PHY_COMMON_CTRL_SPD_1000 (0x0040) +#define PHY_COMMON_CTRL_SPD_RES (0x2040) +#define PHY_COMMON_CTRL_AUTO_NEG (0x1000) +#define PHY_COMMON_CTRL_POWER_DN (0x0800) +#define PHY_COMMON_CTRL_ISOLATE (0x0400) +#define PHY_COMMON_CTRL_RES_AUTO (0x0200) +#define PHY_COMMON_CTRL_DUPLEX (0x0100) +#define PHY_COMMON_CTRL_COL_TEST (0x0080) +#define PHY_COMMON_CTRL_RES1 (0x003F) + +/* STAT Status Register Bit Fields */ +#define PHY_COMMON_STAT_100BT4 (0x8000) +#define PHY_COMMON_STAT_100BXFD (0x4000) +#define PHY_COMMON_STAT_100BXHD (0x2000) +#define PHY_COMMON_STAT_10BTFD (0x1000) +#define PHY_COMMON_STAT_10BTHD (0x0800) +#define PHY_COMMON_STAT_100BT2FD (0x0400) +#define PHY_COMMON_STAT_100BT2HD (0x0200) +#define PHY_COMMON_STAT_EXT_STAT (0x0100) +#define PHY_COMMON_STAT_RES1 (0x0080) +#define PHY_COMMON_STAT_MF_PSUP (0x0040) +#define PHY_COMMON_STAT_AN_COMP (0x0020) +#define PHY_COMMON_STAT_RMT_FLT (0x0010) +#define PHY_COMMON_STAT_AN_CAP (0x0008) +#define PHY_COMMON_STAT_LNK_STAT (0x0004) +#define PHY_COMMON_STAT_JAB_DTCT (0x0002) +#define PHY_COMMON_STAT_EXT_CAP (0x0001) + +/* AUTO_ADV Auto-neg Advert Register Bit Fields */ +#define PHY_COMMON_AUTO_ADV_NP (0x8000) +#define PHY_COMMON_AUTO_ADV_RES1 (0x4000) +#define PHY_COMMON_AUTO_ADV_RMT_FLT (0x2000) +#define PHY_COMMON_AUTO_ADV_RES2 (0x1000) +#define PHY_COMMON_AUTO_ADV_AS_PAUSE (0x0800) +#define PHY_COMMON_AUTO_ADV_PAUSE (0x0400) +#define PHY_COMMON_AUTO_ADV_100BT4 (0x0200) +#define PHY_COMMON_AUTO_ADV_100BTXFD (0x0100) +#define PHY_COMMON_AUTO_ADV_100BTX (0x0080) +#define PHY_COMMON_AUTO_ADV_10BTFD (0x0040) +#define PHY_COMMON_AUTO_ADV_10BT (0x0020) +#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA (0x001F) +#define PHY_COMMON_AUTO_ADV_802_9 (0x0002) +#define PHY_COMMON_AUTO_ADV_802_3 (0x0001) + +/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */ +#define PHY_COMMON_AUTO_LNKB_NP (0x8000) +#define PHY_COMMON_AUTO_LNKB_ACK (0x4000) +#define PHY_COMMON_AUTO_LNKB_RMT_FLT (0x2000) +#define PHY_COMMON_AUTO_LNKB_RES2 (0x1000) +#define PHY_COMMON_AUTO_LNKB_AS_PAUSE (0x0800) +#define PHY_COMMON_AUTO_LNKB_PAUSE (0x0400) +#define PHY_COMMON_AUTO_LNKB_100BT4 (0x0200) +#define PHY_COMMON_AUTO_LNKB_100BTXFD (0x0100) +#define PHY_COMMON_AUTO_LNKB_100BTX (0x0080) +#define PHY_COMMON_AUTO_LNKB_10BTFD (0x0040) +#define PHY_COMMON_AUTO_LNKB_10BT (0x0020) +#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F) +#define PHY_COMMON_AUTO_LNKB_802_9 (0x0002) +#define PHY_COMMON_AUTO_LNKB_802_3 (0x0001) + +/* AUTO_EXP Auto-neg Expansion Register Bit Fields */ +#define PHY_COMMON_AUTO_EXP_RES1 (0xFFC0) +#define PHY_COMMON_AUTO_EXP_BASE_PAGE (0x0020) +#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT (0x0010) +#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP (0x0008) +#define PHY_COMMON_AUTO_EXP_NP_CAP (0x0004) +#define PHY_COMMON_AUTO_EXP_PAGE_REC (0x0002) +#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP (0x0001) + +/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */ +#define PHY_COMMON_AUTO_NEXT_NP (0x8000) +#define PHY_COMMON_AUTO_NEXT_RES1 (0x4000) +#define PHY_COMMON_AUTO_NEXT_MSG_PAGE (0x2000) +#define PHY_COMMON_AUTO_NEXT_ACK_2 (0x1000) +#define PHY_COMMON_AUTO_NEXT_TOGGLE (0x0800) +#define PHY_COMMON_AUTO_NEXT_MSG (0x07FF) + +/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */ +#define PHY_COMMON_AUTO_LNKN_NP (0x8000) +#define PHY_COMMON_AUTO_LNKN_ACK (0x4000) +#define PHY_COMMON_AUTO_LNKN_MSG_PAGE (0x2000) +#define PHY_COMMON_AUTO_LNKN_ACK_2 (0x1000) +#define PHY_COMMON_AUTO_LNKN_TOGGLE (0x0800) +#define PHY_COMMON_AUTO_LNKN_MSG (0x07FF) + +/* PORT_CFG Port Configuration Register Bit Fields */ +#define PHY_LXT971_PORT_CFG_RES1 (0x8000) +#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000) +#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000) +#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000) +#define PHY_LXT971_PORT_CFG_RES2 (0x0800) +#define PHY_LXT971_PORT_CFG_JABBER (0x0400) +#define PHY_LXT971_PORT_CFG_SQE (0x0200) +#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100) +#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080) +#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040) +#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020) +#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018) +#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010) +#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001) +#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000) +#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004) +#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002) +#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001) + +/* STAT2 Status Register #2 Bit Fields */ +#define PHY_LXT971_STAT2_RES1 (0x8000) +#define PHY_LXT971_STAT2_100BTX (0x4000) +#define PHY_LXT971_STAT2_TX_STATUS (0x2000) +#define PHY_LXT971_STAT2_RX_STATUS (0x1000) +#define PHY_LXT971_STAT2_COL_STATUS (0x0800) +#define PHY_LXT971_STAT2_LINK (0x0400) +#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200) +#define PHY_LXT971_STAT2_AUTO_NEG (0x0100) +#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080) +#define PHY_LXT971_STAT2_RES2 (0x0040) +#define PHY_LXT971_STAT2_POLARITY (0x0020) +#define PHY_LXT971_STAT2_PAUSE (0x0010) +#define PHY_LXT971_STAT2_ERROR (0x0008) +#define PHY_LXT971_STAT2_RES3 (0x0007) + +/* INT_ENABLE Interrupt Enable Register Bit Fields */ +#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00) +#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080) +#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040) +#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020) +#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010) +#define PHY_LXT971_INT_ENABLE_RES2 (0x000C) +#define PHY_LXT971_INT_ENABLE_INTEN (0x0002) +#define PHY_LXT971_INT_ENABLE_TINT (0x0001) + +/* INT_STATUS Interrupt Status Register Bit Fields */ +#define PHY_LXT971_INT_STATUS_RES1 (0xFF00) +#define PHY_LXT971_INT_STATUS_ANDONE (0x0080) +#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040) +#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020) +#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010) +#define PHY_LXT971_INT_STATUS_RES2 (0x0008) +#define PHY_LXT971_INT_STATUS_MDINT (0x0004) +#define PHY_LXT971_INT_STATUS_RES3 (0x0003) + +/* LED_CFG Interrupt LED Configuration Register Bit Fields */ +#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C) +#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008) +#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004) +#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C) +#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C) +#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008) +#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004) +#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000) +#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002) +#define PHY_LXT971_LED_CFG_RES1 (0x0001) + +/* only one of these values must be shifted for each SHIFT_LED? */ +#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F) +#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E) +#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D) +#define PHY_LXT971_LED_CFG_LINK_RX (0x000C) +#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B) +#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A) +#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009) +#define PHY_LXT971_LED_CFG_TEST_ON (0x0008) +#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007) +#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006) +#define PHY_LXT971_LED_CFG_DUPLEX (0x0005) +#define PHY_LXT971_LED_CFG_LINK (0x0004) +#define PHY_LXT971_LED_CFG_COLLISION (0x0003) +#define PHY_LXT971_LED_CFG_RECEIVE (0x0002) +#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001) +#define PHY_LXT971_LED_CFG_SPEED (0x0000) + +/* DIG_CFG Digitial Configuration Register Bit Fields */ +#define PHY_LXT971_DIG_CFG_RES1 (0xF000) +#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800) +#define PHY_LXT971_DIG_CFG_RES2 (0x0400) +#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200) +#define PHY_LXT971_DIG_CFG_RES3 (0x01FF) + +#define PHY_LXT971_MDIO_MAX_CLK (8000000) +#define PHY_MDIO_MAX_CLK (2500000) + +/* TX_CTRL Transmit Control Register Bit Fields + documentation is buggy for this register, therefore setting not included */ + +typedef enum +{ + PHY_NONE = 0x0000, /* no PHY detected yet */ + PHY_LXT971A = 0x0013 +} PhyType; + +#endif /* __LXT971A_H__ */ diff --git a/include/lynxkdi.h b/include/lynxkdi.h new file mode 100644 index 0000000..fbf7617 --- /dev/null +++ b/include/lynxkdi.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2003 + * Orbacom Systems, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __LYNXKDI_H__ +#define __LYNXKDI_H__ + + +/* Boot parameter struct passed to kernel + */ +typedef struct lynxos_bootparms_t { + uint8_t rsvd1[2]; /* Reserved */ + uint8_t ethaddr[6]; /* Ethernet address */ + uint16_t flags; /* Boot flags */ + uint32_t rate; /* System frequency */ + uint32_t clock_ref; /* Time reference */ + uint32_t dramsz; /* DRAM size */ + uint32_t rsvd2; /* Reserved */ +} lynxos_bootparms_t; + + +#endif /* __LYNXKDI_H__ */ diff --git a/include/malloc.h b/include/malloc.h new file mode 100644 index 0000000..47154b0 --- /dev/null +++ b/include/malloc.h @@ -0,0 +1,942 @@ +/* + A version of malloc/free/realloc written by Doug Lea and released to the + public domain. Send questions/comments/complaints/performance data + to dl@cs.oswego.edu + +* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee) + + Note: There may be an updated version of this malloc obtainable at + ftp://g.oswego.edu/pub/misc/malloc.c + Check before installing! + +* Why use this malloc? + + This is not the fastest, most space-conserving, most portable, or + most tunable malloc ever written. However it is among the fastest + while also being among the most space-conserving, portable and tunable. + Consistent balance across these factors results in a good general-purpose + allocator. For a high-level description, see + http://g.oswego.edu/dl/html/malloc.html + +* Synopsis of public routines + + (Much fuller descriptions are contained in the program documentation below.) + + malloc(size_t n); + Return a pointer to a newly allocated chunk of at least n bytes, or null + if no space is available. + free(Void_t* p); + Release the chunk of memory pointed to by p, or no effect if p is null. + realloc(Void_t* p, size_t n); + Return a pointer to a chunk of size n that contains the same data + as does chunk p up to the minimum of (n, p's size) bytes, or null + if no space is available. The returned pointer may or may not be + the same as p. If p is null, equivalent to malloc. Unless the + #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a + size argument of zero (re)allocates a minimum-sized chunk. + memalign(size_t alignment, size_t n); + Return a pointer to a newly allocated chunk of n bytes, aligned + in accord with the alignment argument, which must be a power of + two. + valloc(size_t n); + Equivalent to memalign(pagesize, n), where pagesize is the page + size of the system (or as near to this as can be figured out from + all the includes/defines below.) + pvalloc(size_t n); + Equivalent to valloc(minimum-page-that-holds(n)), that is, + round up n to nearest pagesize. + calloc(size_t unit, size_t quantity); + Returns a pointer to quantity * unit bytes, with all locations + set to zero. + cfree(Void_t* p); + Equivalent to free(p). + malloc_trim(size_t pad); + Release all but pad bytes of freed top-most memory back + to the system. Return 1 if successful, else 0. + malloc_usable_size(Void_t* p); + Report the number usable allocated bytes associated with allocated + chunk p. This may or may not report more bytes than were requested, + due to alignment and minimum size constraints. + malloc_stats(); + Prints brief summary statistics on stderr. + mallinfo() + Returns (by copy) a struct containing various summary statistics. + mallopt(int parameter_number, int parameter_value) + Changes one of the tunable parameters described below. Returns + 1 if successful in changing the parameter, else 0. + +* Vital statistics: + + Alignment: 8-byte + 8 byte alignment is currently hardwired into the design. This + seems to suffice for all current machines and C compilers. + + Assumed pointer representation: 4 or 8 bytes + Code for 8-byte pointers is untested by me but has worked + reliably by Wolfram Gloger, who contributed most of the + changes supporting this. + + Assumed size_t representation: 4 or 8 bytes + Note that size_t is allowed to be 4 bytes even if pointers are 8. + + Minimum overhead per allocated chunk: 4 or 8 bytes + Each malloced chunk has a hidden overhead of 4 bytes holding size + and status information. + + Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead) + 8-byte ptrs: 24/32 bytes (including, 4/8 overhead) + + When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte + ptrs but 4 byte size) or 24 (for 8/8) additional bytes are + needed; 4 (8) for a trailing size field + and 8 (16) bytes for free list pointers. Thus, the minimum + allocatable size is 16/24/32 bytes. + + Even a request for zero bytes (i.e., malloc(0)) returns a + pointer to something of the minimum allocatable size. + + Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes + 8-byte size_t: 2^63 - 16 bytes + + It is assumed that (possibly signed) size_t bit values suffice to + represent chunk sizes. `Possibly signed' is due to the fact + that `size_t' may be defined on a system as either a signed or + an unsigned type. To be conservative, values that would appear + as negative numbers are avoided. + Requests for sizes with a negative sign bit when the request + size is treaded as a long will return null. + + Maximum overhead wastage per allocated chunk: normally 15 bytes + + Alignnment demands, plus the minimum allocatable size restriction + make the normal worst-case wastage 15 bytes (i.e., up to 15 + more bytes will be allocated than were requested in malloc), with + two exceptions: + 1. Because requests for zero bytes allocate non-zero space, + the worst case wastage for a request of zero bytes is 24 bytes. + 2. For requests >= mmap_threshold that are serviced via + mmap(), the worst case wastage is 8 bytes plus the remainder + from a system page (the minimal mmap unit); typically 4096 bytes. + +* Limitations + + Here are some features that are NOT currently supported + + * No user-definable hooks for callbacks and the like. + * No automated mechanism for fully checking that all accesses + to malloced memory stay within their bounds. + * No support for compaction. + +* Synopsis of compile-time options: + + People have reported using previous versions of this malloc on all + versions of Unix, sometimes by tweaking some of the defines + below. It has been tested most extensively on Solaris and + Linux. It is also reported to work on WIN32 platforms. + People have also reported adapting this malloc for use in + stand-alone embedded systems. + + The implementation is in straight, hand-tuned ANSI C. Among other + consequences, it uses a lot of macros. Because of this, to be at + all usable, this code should be compiled using an optimizing compiler + (for example gcc -O2) that can simplify expressions and control + paths. + + __STD_C (default: derived from C compiler defines) + Nonzero if using ANSI-standard C compiler, a C++ compiler, or + a C compiler sufficiently close to ANSI to get away with it. + DEBUG (default: NOT defined) + Define to enable debugging. Adds fairly extensive assertion-based + checking to help track down memory errors, but noticeably slows down + execution. + REALLOC_ZERO_BYTES_FREES (default: NOT defined) + Define this if you think that realloc(p, 0) should be equivalent + to free(p). Otherwise, since malloc returns a unique pointer for + malloc(0), so does realloc(p, 0). + HAVE_MEMCPY (default: defined) + Define if you are not otherwise using ANSI STD C, but still + have memcpy and memset in your C library and want to use them. + Otherwise, simple internal versions are supplied. + USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise) + Define as 1 if you want the C library versions of memset and + memcpy called in realloc and calloc (otherwise macro versions are used). + At least on some platforms, the simple macro versions usually + outperform libc versions. + HAVE_MMAP (default: defined as 1) + Define to non-zero to optionally make malloc() use mmap() to + allocate very large blocks. + HAVE_MREMAP (default: defined as 0 unless Linux libc set) + Define to non-zero to optionally make realloc() use mremap() to + reallocate very large blocks. + malloc_getpagesize (default: derived from system #includes) + Either a constant or routine call returning the system page size. + HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined) + Optionally define if you are on a system with a /usr/include/malloc.h + that declares struct mallinfo. It is not at all necessary to + define this even if you do, but will ensure consistency. + INTERNAL_SIZE_T (default: size_t) + Define to a 32-bit type (probably `unsigned int') if you are on a + 64-bit machine, yet do not want or need to allow malloc requests of + greater than 2^31 to be handled. This saves space, especially for + very small chunks. + INTERNAL_LINUX_C_LIB (default: NOT defined) + Defined only when compiled as part of Linux libc. + Also note that there is some odd internal name-mangling via defines + (for example, internally, `malloc' is named `mALLOc') needed + when compiling in this case. These look funny but don't otherwise + affect anything. + WIN32 (default: undefined) + Define this on MS win (95, nt) platforms to compile in sbrk emulation. + LACKS_UNISTD_H (default: undefined if not WIN32) + Define this if your system does not have a . + LACKS_SYS_PARAM_H (default: undefined if not WIN32) + Define this if your system does not have a . + MORECORE (default: sbrk) + The name of the routine to call to obtain more memory from the system. + MORECORE_FAILURE (default: -1) + The value returned upon failure of MORECORE. + MORECORE_CLEARS (default 1) + True (1) if the routine mapped to MORECORE zeroes out memory (which + holds for sbrk). + DEFAULT_TRIM_THRESHOLD + DEFAULT_TOP_PAD + DEFAULT_MMAP_THRESHOLD + DEFAULT_MMAP_MAX + Default values of tunable parameters (described in detail below) + controlling interaction with host system routines (sbrk, mmap, etc). + These values may also be changed dynamically via mallopt(). The + preset defaults are those that give best performance for typical + programs/systems. + USE_DL_PREFIX (default: undefined) + Prefix all public routines with the string 'dl'. Useful to + quickly avoid procedure declaration conflicts and linker symbol + conflicts with existing memory allocation routines. + + +*/ + + + + +/* Preliminaries */ + +#ifndef __STD_C +#ifdef __STDC__ +#define __STD_C 1 +#else +#if __cplusplus +#define __STD_C 1 +#else +#define __STD_C 0 +#endif /*__cplusplus*/ +#endif /*__STDC__*/ +#endif /*__STD_C*/ + +#ifndef Void_t +#if (__STD_C || defined(WIN32)) +#define Void_t void +#else +#define Void_t char +#endif +#endif /*Void_t*/ + +#if __STD_C +#include /* for size_t */ +#else +#include +#endif /* __STD_C */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if 0 /* not for U-Boot */ +#include /* needed for malloc_stats */ +#endif + + +/* + Compile-time options +*/ + + +/* + Debugging: + + Because freed chunks may be overwritten with link fields, this + malloc will often die when freed memory is overwritten by user + programs. This can be very effective (albeit in an annoying way) + in helping track down dangling pointers. + + If you compile with -DDEBUG, a number of assertion checks are + enabled that will catch more memory errors. You probably won't be + able to make much sense of the actual assertion errors, but they + should help you locate incorrectly overwritten memory. The + checking is fairly extensive, and will slow down execution + noticeably. Calling malloc_stats or mallinfo with DEBUG set will + attempt to check every non-mmapped allocated and free chunk in the + course of computing the summmaries. (By nature, mmapped regions + cannot be checked very much automatically.) + + Setting DEBUG may also be helpful if you are trying to modify + this code. The assertions in the check routines spell out in more + detail the assumptions and invariants underlying the algorithms. + +*/ + +#ifdef DEBUG +/* #include */ +#define assert(x) ((void)0) +#else +#define assert(x) ((void)0) +#endif + + +/* + INTERNAL_SIZE_T is the word-size used for internal bookkeeping + of chunk sizes. On a 64-bit machine, you can reduce malloc + overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' + at the expense of not being able to handle requests greater than + 2^31. This limitation is hardly ever a concern; you are encouraged + to set this. However, the default version is the same as size_t. +*/ + +#ifndef INTERNAL_SIZE_T +#define INTERNAL_SIZE_T size_t +#endif + +/* + REALLOC_ZERO_BYTES_FREES should be set if a call to + realloc with zero bytes should be the same as a call to free. + Some people think it should. Otherwise, since this malloc + returns a unique pointer for malloc(0), so does realloc(p, 0). +*/ + + +/* #define REALLOC_ZERO_BYTES_FREES */ + + +/* + WIN32 causes an emulation of sbrk to be compiled in + mmap-based options are not currently supported in WIN32. +*/ + +/* #define WIN32 */ +#ifdef WIN32 +#define MORECORE wsbrk +#define HAVE_MMAP 0 + +#define LACKS_UNISTD_H +#define LACKS_SYS_PARAM_H + +/* + Include 'windows.h' to get the necessary declarations for the + Microsoft Visual C++ data structures and routines used in the 'sbrk' + emulation. + + Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft + Visual C++ header files are included. +*/ +#define WIN32_LEAN_AND_MEAN +#include +#endif + + +/* + HAVE_MEMCPY should be defined if you are not otherwise using + ANSI STD C, but still have memcpy and memset in your C library + and want to use them in calloc and realloc. Otherwise simple + macro versions are defined here. + + USE_MEMCPY should be defined as 1 if you actually want to + have memset and memcpy called. People report that the macro + versions are often enough faster than libc versions on many + systems that it is better to use them. + +*/ + +#define HAVE_MEMCPY + +#ifndef USE_MEMCPY +#ifdef HAVE_MEMCPY +#define USE_MEMCPY 1 +#else +#define USE_MEMCPY 0 +#endif +#endif + +#if (__STD_C || defined(HAVE_MEMCPY)) + +#if __STD_C +void* memset(void*, int, size_t); +void* memcpy(void*, const void*, size_t); +#else +#ifdef WIN32 +/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */ +/* 'windows.h' */ +#else +Void_t* memset(); +Void_t* memcpy(); +#endif +#endif +#endif + +#if USE_MEMCPY + +/* The following macros are only invoked with (2n+1)-multiples of + INTERNAL_SIZE_T units, with a positive integer n. This is exploited + for fast inline execution when n is small. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T mzsz = (nbytes); \ + if(mzsz <= 9*sizeof(mzsz)) { \ + INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \ + if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; }}} \ + *mz++ = 0; \ + *mz++ = 0; \ + *mz = 0; \ + } else memset((charp), 0, mzsz); \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T mcsz = (nbytes); \ + if(mcsz <= 9*sizeof(mcsz)) { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \ + if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; }}} \ + *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + *mcdst = *mcsrc ; \ + } else memcpy(dest, src, mcsz); \ +} while(0) + +#else /* !USE_MEMCPY */ + +/* Use Duff's device for good zeroing/copying performance. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mzp++ = 0; \ + case 7: *mzp++ = 0; \ + case 6: *mzp++ = 0; \ + case 5: *mzp++ = 0; \ + case 4: *mzp++ = 0; \ + case 3: *mzp++ = 0; \ + case 2: *mzp++ = 0; \ + case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mcdst++ = *mcsrc++; \ + case 7: *mcdst++ = *mcsrc++; \ + case 6: *mcdst++ = *mcsrc++; \ + case 5: *mcdst++ = *mcsrc++; \ + case 4: *mcdst++ = *mcsrc++; \ + case 3: *mcdst++ = *mcsrc++; \ + case 2: *mcdst++ = *mcsrc++; \ + case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#endif + + +/* + Define HAVE_MMAP to optionally make malloc() use mmap() to + allocate very large blocks. These will be returned to the + operating system immediately after a free(). +*/ + +/*** +#ifndef HAVE_MMAP +#define HAVE_MMAP 1 +#endif +***/ +#undef HAVE_MMAP /* Not available for U-Boot */ + +/* + Define HAVE_MREMAP to make realloc() use mremap() to re-allocate + large blocks. This is currently only possible on Linux with + kernel versions newer than 1.3.77. +*/ + +/*** +#ifndef HAVE_MREMAP +#ifdef INTERNAL_LINUX_C_LIB +#define HAVE_MREMAP 1 +#else +#define HAVE_MREMAP 0 +#endif +#endif +***/ +#undef HAVE_MREMAP /* Not available for U-Boot */ + +#if HAVE_MMAP + +#include +#include +#include + +#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON) +#define MAP_ANONYMOUS MAP_ANON +#endif + +#endif /* HAVE_MMAP */ + +/* + Access to system page size. To the extent possible, this malloc + manages memory from the system in page-size units. + + The following mechanics for getpagesize were adapted from + bsd/gnu getpagesize.h +*/ + +#define LACKS_UNISTD_H /* Shortcut for U-Boot */ +#define malloc_getpagesize 4096 + +#ifndef LACKS_UNISTD_H +# include +#endif + +#ifndef malloc_getpagesize +# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */ +# ifndef _SC_PAGE_SIZE +# define _SC_PAGE_SIZE _SC_PAGESIZE +# endif +# endif +# ifdef _SC_PAGE_SIZE +# define malloc_getpagesize sysconf(_SC_PAGE_SIZE) +# else +# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE) + extern size_t getpagesize(); +# define malloc_getpagesize getpagesize() +# else +# ifdef WIN32 +# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */ +# else +# ifndef LACKS_SYS_PARAM_H +# include +# endif +# ifdef EXEC_PAGESIZE +# define malloc_getpagesize EXEC_PAGESIZE +# else +# ifdef NBPG +# ifndef CLSIZE +# define malloc_getpagesize NBPG +# else +# define malloc_getpagesize (NBPG * CLSIZE) +# endif +# else +# ifdef NBPC +# define malloc_getpagesize NBPC +# else +# ifdef PAGESIZE +# define malloc_getpagesize PAGESIZE +# else +# define malloc_getpagesize (4096) /* just guess */ +# endif +# endif +# endif +# endif +# endif +# endif +# endif +#endif + + +/* + + This version of malloc supports the standard SVID/XPG mallinfo + routine that returns a struct containing the same kind of + information you can get from malloc_stats. It should work on + any SVID/XPG compliant system that has a /usr/include/malloc.h + defining struct mallinfo. (If you'd like to install such a thing + yourself, cut out the preliminary declarations as described above + and below and save them in a malloc.h file. But there's no + compelling reason to bother to do this.) + + The main declaration needed is the mallinfo struct that is returned + (by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a + bunch of fields, most of which are not even meaningful in this + version of malloc. Some of these fields are are instead filled by + mallinfo() with other numbers that might possibly be of interest. + + HAVE_USR_INCLUDE_MALLOC_H should be set if you have a + /usr/include/malloc.h file that includes a declaration of struct + mallinfo. If so, it is included; else an SVID2/XPG2 compliant + version is declared below. These must be precisely the same for + mallinfo() to work. + +*/ + +/* #define HAVE_USR_INCLUDE_MALLOC_H */ + +#if HAVE_USR_INCLUDE_MALLOC_H +#include "/usr/include/malloc.h" +#else + +/* SVID2/XPG mallinfo structure */ + +struct mallinfo { + int arena; /* total space allocated from system */ + int ordblks; /* number of non-inuse chunks */ + int smblks; /* unused -- always zero */ + int hblks; /* number of mmapped regions */ + int hblkhd; /* total space in mmapped regions */ + int usmblks; /* unused -- always zero */ + int fsmblks; /* unused -- always zero */ + int uordblks; /* total allocated space */ + int fordblks; /* total non-inuse space */ + int keepcost; /* top-most, releasable (via malloc_trim) space */ +}; + +/* SVID2/XPG mallopt options */ + +#define M_MXFAST 1 /* UNUSED in this malloc */ +#define M_NLBLKS 2 /* UNUSED in this malloc */ +#define M_GRAIN 3 /* UNUSED in this malloc */ +#define M_KEEP 4 /* UNUSED in this malloc */ + +#endif + +/* mallopt options that actually do something */ + +#define M_TRIM_THRESHOLD -1 +#define M_TOP_PAD -2 +#define M_MMAP_THRESHOLD -3 +#define M_MMAP_MAX -4 + + +#ifndef DEFAULT_TRIM_THRESHOLD +#define DEFAULT_TRIM_THRESHOLD (128 * 1024) +#endif + +/* + M_TRIM_THRESHOLD is the maximum amount of unused top-most memory + to keep before releasing via malloc_trim in free(). + + Automatic trimming is mainly useful in long-lived programs. + Because trimming via sbrk can be slow on some systems, and can + sometimes be wasteful (in cases where programs immediately + afterward allocate more large chunks) the value should be high + enough so that your overall system performance would improve by + releasing. + + The trim threshold and the mmap control parameters (see below) + can be traded off with one another. Trimming and mmapping are + two different ways of releasing unused memory back to the + system. Between these two, it is often possible to keep + system-level demands of a long-lived program down to a bare + minimum. For example, in one test suite of sessions measuring + the XF86 X server on Linux, using a trim threshold of 128K and a + mmap threshold of 192K led to near-minimal long term resource + consumption. + + If you are using this malloc in a long-lived program, it should + pay to experiment with these values. As a rough guide, you + might set to a value close to the average size of a process + (program) running on your system. Releasing this much memory + would allow such a process to run in memory. Generally, it's + worth it to tune for trimming rather tham memory mapping when a + program undergoes phases where several large chunks are + allocated and released in ways that can reuse each other's + storage, perhaps mixed with phases where there are no such + chunks at all. And in well-behaved long-lived programs, + controlling release of large blocks via trimming versus mapping + is usually faster. + + However, in most programs, these parameters serve mainly as + protection against the system-level effects of carrying around + massive amounts of unneeded memory. Since frequent calls to + sbrk, mmap, and munmap otherwise degrade performance, the default + parameters are set to relatively high values that serve only as + safeguards. + + The default trim value is high enough to cause trimming only in + fairly extreme (by current memory consumption standards) cases. + It must be greater than page size to have any useful effect. To + disable trimming completely, you can set to (unsigned long)(-1); + + +*/ + + +#ifndef DEFAULT_TOP_PAD +#define DEFAULT_TOP_PAD (0) +#endif + +/* + M_TOP_PAD is the amount of extra `padding' space to allocate or + retain whenever sbrk is called. It is used in two ways internally: + + * When sbrk is called to extend the top of the arena to satisfy + a new malloc request, this much padding is added to the sbrk + request. + + * When malloc_trim is called automatically from free(), + it is used as the `pad' argument. + + In both cases, the actual amount of padding is rounded + so that the end of the arena is always a system page boundary. + + The main reason for using padding is to avoid calling sbrk so + often. Having even a small pad greatly reduces the likelihood + that nearly every malloc request during program start-up (or + after trimming) will invoke sbrk, which needlessly wastes + time. + + Automatic rounding-up to page-size units is normally sufficient + to avoid measurable overhead, so the default is 0. However, in + systems where sbrk is relatively slow, it can pay to increase + this value, at the expense of carrying around more memory than + the program needs. + +*/ + + +#ifndef DEFAULT_MMAP_THRESHOLD +#define DEFAULT_MMAP_THRESHOLD (128 * 1024) +#endif + +/* + + M_MMAP_THRESHOLD is the request size threshold for using mmap() + to service a request. Requests of at least this size that cannot + be allocated using already-existing space will be serviced via mmap. + (If enough normal freed space already exists it is used instead.) + + Using mmap segregates relatively large chunks of memory so that + they can be individually obtained and released from the host + system. A request serviced through mmap is never reused by any + other request (at least not directly; the system may just so + happen to remap successive requests to the same locations). + + Segregating space in this way has the benefit that mmapped space + can ALWAYS be individually released back to the system, which + helps keep the system level memory demands of a long-lived + program low. Mapped memory can never become `locked' between + other chunks, as can happen with normally allocated chunks, which + menas that even trimming via malloc_trim would not release them. + + However, it has the disadvantages that: + + 1. The space cannot be reclaimed, consolidated, and then + used to service later requests, as happens with normal chunks. + 2. It can lead to more wastage because of mmap page alignment + requirements + 3. It causes malloc performance to be more dependent on host + system memory management support routines which may vary in + implementation quality and may impose arbitrary + limitations. Generally, servicing a request via normal + malloc steps is faster than going through a system's mmap. + + All together, these considerations should lead you to use mmap + only for relatively large requests. + + +*/ + + +#ifndef DEFAULT_MMAP_MAX +#if HAVE_MMAP +#define DEFAULT_MMAP_MAX (64) +#else +#define DEFAULT_MMAP_MAX (0) +#endif +#endif + +/* + M_MMAP_MAX is the maximum number of requests to simultaneously + service using mmap. This parameter exists because: + + 1. Some systems have a limited number of internal tables for + use by mmap. + 2. In most systems, overreliance on mmap can degrade overall + performance. + 3. If a program allocates many large regions, it is probably + better off using normal sbrk-based allocation routines that + can reclaim and reallocate normal heap memory. Using a + small value allows transition into this mode after the + first few allocations. + + Setting to 0 disables all use of mmap. If HAVE_MMAP is not set, + the default value is 0, and attempts to set it to non-zero values + in mallopt will fail. +*/ + + +/* + USE_DL_PREFIX will prefix all public routines with the string 'dl'. + Useful to quickly avoid procedure declaration conflicts and linker + symbol conflicts with existing memory allocation routines. + +*/ + +/* #define USE_DL_PREFIX */ + + +/* + + Special defines for linux libc + + Except when compiled using these special defines for Linux libc + using weak aliases, this malloc is NOT designed to work in + multithreaded applications. No semaphores or other concurrency + control are provided to ensure that multiple malloc or free calls + don't run at the same time, which could be disasterous. A single + semaphore could be used across malloc, realloc, and free (which is + essentially the effect of the linux weak alias approach). It would + be hard to obtain finer granularity. + +*/ + + +#ifdef INTERNAL_LINUX_C_LIB + +#if __STD_C + +Void_t * __default_morecore_init (ptrdiff_t); +Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init; + +#else + +Void_t * __default_morecore_init (); +Void_t *(*__morecore)() = __default_morecore_init; + +#endif + +#define MORECORE (*__morecore) +#define MORECORE_FAILURE 0 +#define MORECORE_CLEARS 1 + +#else /* INTERNAL_LINUX_C_LIB */ + +#if __STD_C +extern Void_t* sbrk(ptrdiff_t); +#else +extern Void_t* sbrk(); +#endif + +#ifndef MORECORE +#define MORECORE sbrk +#endif + +#ifndef MORECORE_FAILURE +#define MORECORE_FAILURE -1 +#endif + +#ifndef MORECORE_CLEARS +#define MORECORE_CLEARS 1 +#endif + +#endif /* INTERNAL_LINUX_C_LIB */ + +#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__) + +#define cALLOc __libc_calloc +#define fREe __libc_free +#define mALLOc __libc_malloc +#define mEMALIGn __libc_memalign +#define rEALLOc __libc_realloc +#define vALLOc __libc_valloc +#define pvALLOc __libc_pvalloc +#define mALLINFo __libc_mallinfo +#define mALLOPt __libc_mallopt + +#pragma weak calloc = __libc_calloc +#pragma weak free = __libc_free +#pragma weak cfree = __libc_free +#pragma weak malloc = __libc_malloc +#pragma weak memalign = __libc_memalign +#pragma weak realloc = __libc_realloc +#pragma weak valloc = __libc_valloc +#pragma weak pvalloc = __libc_pvalloc +#pragma weak mallinfo = __libc_mallinfo +#pragma weak mallopt = __libc_mallopt + +#else + +#ifdef USE_DL_PREFIX +#define cALLOc dlcalloc +#define fREe dlfree +#define mALLOc dlmalloc +#define mEMALIGn dlmemalign +#define rEALLOc dlrealloc +#define vALLOc dlvalloc +#define pvALLOc dlpvalloc +#define mALLINFo dlmallinfo +#define mALLOPt dlmallopt +#else /* USE_DL_PREFIX */ +#define cALLOc calloc +#define fREe free +#define mALLOc malloc +#define mEMALIGn memalign +#define rEALLOc realloc +#define vALLOc valloc +#define pvALLOc pvalloc +#define mALLINFo mallinfo +#define mALLOPt mallopt +#endif /* USE_DL_PREFIX */ + +#endif + +/* Public routines */ + +#if __STD_C + +Void_t* mALLOc(size_t); +void fREe(Void_t*); +Void_t* rEALLOc(Void_t*, size_t); +Void_t* mEMALIGn(size_t, size_t); +Void_t* vALLOc(size_t); +Void_t* pvALLOc(size_t); +Void_t* cALLOc(size_t, size_t); +void cfree(Void_t*); +int malloc_trim(size_t); +size_t malloc_usable_size(Void_t*); +void malloc_stats(void); +int mALLOPt(int, int); +struct mallinfo mALLINFo(void); +#else +Void_t* mALLOc(); +void fREe(); +Void_t* rEALLOc(); +Void_t* mEMALIGn(); +Void_t* vALLOc(); +Void_t* pvALLOc(); +Void_t* cALLOc(); +void cfree(); +int malloc_trim(); +size_t malloc_usable_size(); +void malloc_stats(); +int mALLOPt(); +struct mallinfo mALLINFo(); +#endif + + +#ifdef __cplusplus +}; /* end of extern "C" */ +#endif diff --git a/include/mii_phy.h b/include/mii_phy.h new file mode 100644 index 0000000..f0d3e62 --- /dev/null +++ b/include/mii_phy.h @@ -0,0 +1,8 @@ +#ifndef _MII_PHY_H_ +#define _MII_PHY_H_ + +void mii_discover_phy(void); +unsigned short mii_phy_read(unsigned short reg); +void mii_phy_write(unsigned short reg, unsigned short val); + +#endif diff --git a/include/miiphy.h b/include/miiphy.h new file mode 100644 index 0000000..71716b0 --- /dev/null +++ b/include/miiphy.h @@ -0,0 +1,160 @@ +/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ +| +| File Name: miiphy.h +| +| Function: Include file defining PHY registers. +| +| Author: Mark Wisner +| +| Change Activity- +| +| Date Description of Change BY +| --------- --------------------- --- +| 04-May-99 Created MKW +| 07-Jul-99 Added full duplex support MKW +| 08-Sep-01 Tweaks gvb +| ++----------------------------------------------------------------------------*/ +#ifndef _miiphy_h_ +#define _miiphy_h_ + +#include + +int miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value); +int miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value); +int miiphy_info(char *devname, unsigned char addr, unsigned int *oui, + unsigned char *model, unsigned char *rev); +int miiphy_reset(char *devname, unsigned char addr); +int miiphy_speed(char *devname, unsigned char addr); +int miiphy_duplex(char *devname, unsigned char addr); +#ifdef CFG_FAULT_ECHO_LINK_DOWN +int miiphy_link(char *devname, unsigned char addr); +#endif + +void miiphy_init(void); + +void miiphy_register(char *devname, + int (* read)(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value), + int (* write)(char *devname, unsigned char addr, + unsigned char reg, unsigned short value)); + +int miiphy_set_current_dev(char *devname); +char *miiphy_get_current_dev(void); + +void miiphy_listdev(void); + +#define BB_MII_DEVNAME "bbmii" + +int bb_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +int bb_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value); + +/* phy seed setup */ +#define AUTO 99 +#define _1000BASET 1000 +#define _100BASET 100 +#define _10BASET 10 +#define HALF 22 +#define FULL 44 + +/* phy register offsets */ +#define PHY_BMCR 0x00 +#define PHY_BMSR 0x01 +#define PHY_PHYIDR1 0x02 +#define PHY_PHYIDR2 0x03 +#define PHY_ANAR 0x04 +#define PHY_ANLPAR 0x05 +#define PHY_ANER 0x06 +#define PHY_ANNPTR 0x07 +#define PHY_ANLPNP 0x08 +#define PHY_1000BTCR 0x09 +#define PHY_1000BTSR 0x0A +#define PHY_PHYSTS 0x10 +#define PHY_MIPSCR 0x11 +#define PHY_MIPGSR 0x12 +#define PHY_DCR 0x13 +#define PHY_FCSCR 0x14 +#define PHY_RECR 0x15 +#define PHY_PCSR 0x16 +#define PHY_LBR 0x17 +#define PHY_10BTSCR 0x18 +#define PHY_PHYCTRL 0x19 + +/* PHY BMCR */ +#define PHY_BMCR_RESET 0x8000 +#define PHY_BMCR_LOOP 0x4000 +#define PHY_BMCR_100MB 0x2000 +#define PHY_BMCR_AUTON 0x1000 +#define PHY_BMCR_POWD 0x0800 +#define PHY_BMCR_ISO 0x0400 +#define PHY_BMCR_RST_NEG 0x0200 +#define PHY_BMCR_DPLX 0x0100 +#define PHY_BMCR_COL_TST 0x0080 + +#define PHY_BMCR_SPEED_MASK 0x2040 +#define PHY_BMCR_1000_MBPS 0x0040 +#define PHY_BMCR_100_MBPS 0x2000 +#define PHY_BMCR_10_MBPS 0x0000 + +/* phy BMSR */ +#define PHY_BMSR_100T4 0x8000 +#define PHY_BMSR_100TXF 0x4000 +#define PHY_BMSR_100TXH 0x2000 +#define PHY_BMSR_10TF 0x1000 +#define PHY_BMSR_10TH 0x0800 +#define PHY_BMSR_PRE_SUP 0x0040 +#define PHY_BMSR_AUTN_COMP 0x0020 +#define PHY_BMSR_RF 0x0010 +#define PHY_BMSR_AUTN_ABLE 0x0008 +#define PHY_BMSR_LS 0x0004 +#define PHY_BMSR_JD 0x0002 +#define PHY_BMSR_EXT 0x0001 + +/*phy ANLPAR */ +#define PHY_ANLPAR_NP 0x8000 +#define PHY_ANLPAR_ACK 0x4000 +#define PHY_ANLPAR_RF 0x2000 +#define PHY_ANLPAR_T4 0x0200 +#define PHY_ANLPAR_TXFD 0x0100 +#define PHY_ANLPAR_TX 0x0080 +#define PHY_ANLPAR_10FD 0x0040 +#define PHY_ANLPAR_10 0x0020 +#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ + +#define PHY_ANLPAR_PSB_MASK 0x001f +#define PHY_ANLPAR_PSB_802_3 0x0001 +#define PHY_ANLPAR_PSB_802_9 0x0002 + +/* PHY_1000BTSR */ +#define PHY_1000BTSR_MSCF 0x8000 +#define PHY_1000BTSR_MSCR 0x4000 +#define PHY_1000BTSR_LRS 0x2000 +#define PHY_1000BTSR_RRS 0x1000 +#define PHY_1000BTSR_1000FD 0x0800 +#define PHY_1000BTSR_1000HD 0x0400 + +#endif diff --git a/include/mk48t59.h b/include/mk48t59.h new file mode 100644 index 0000000..03c992e --- /dev/null +++ b/include/mk48t59.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the MK48T59 RTC + */ + + +#if defined(CONFIG_RTC_MK48T59) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +#define RTC_PORT_ADDR0 CFG_ISA_IO + 0x70 +#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1 +#define RTC_PORT_DATA CFG_ISA_IO + 0x76 + +/* RTC Offsets */ +#define RTC_SECONDS 0x1FF9 +#define RTC_MINUTES 0x1FFA +#define RTC_HOURS 0x1FFB +#define RTC_DAY_OF_WEEK 0x1FFC +#define RTC_DAY_OF_MONTH 0x1FFD +#define RTC_MONTH 0x1FFE +#define RTC_YEAR 0x1FFF + +#define RTC_CONTROLA 0x1FF8 +#define RTC_CA_WRITE 0x80 +#define RTC_CA_READ 0x40 +#define RTC_CA_CALIB_SIGN 0x20 +#define RTC_CA_CALIB_MASK 0x1f + +#define RTC_CONTROLB 0x1FF9 +#define RTC_CB_STOP 0x80 + +#define RTC_WATCHDOG 0x1FF7 +#define RTC_WDS 0x80 +#define RTC_WD_RB_16TH 0x0 +#define RTC_WD_RB_4TH 0x1 +#define RTC_WD_RB_1 0x2 +#define RTC_WD_RB_4 0x3 + +void rtc_set_watchdog(short multi, short res); +void *nvram_read(void *dest, const short src, size_t count); +void nvram_write(short dest, const void *src, size_t count); + +#endif diff --git a/include/mmc.h b/include/mmc.h new file mode 100644 index 0000000..a271695 --- /dev/null +++ b/include/mmc.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MMC_H_ +#define _MMC_H_ +#include + +int mmc_init(int verbose); +int mmc_read(ulong src, uchar *dst, int size); +int mmc_write(uchar *src, ulong dst, int size); +int mmc2info(ulong addr); + +#endif /* _MMC_H_ */ diff --git a/include/mpc106.h b/include/mpc106.h new file mode 100644 index 0000000..ab6d57e --- /dev/null +++ b/include/mpc106.h @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MPC106_PCI_H +#define _MPC106_PCI_H + +/* + * Defines for the MPC106 PCI Config address and data registers followed by + * defines for the standard PCI device configuration header. + */ +#define PCIDEVID_MPC106 0x0 + +/* + * MPC106 Registers + */ +#define MPC106_REG 0x80000000 + +#ifdef CFG_ADDRESS_MAP_A +#define MPC106_REG_ADDR 0x80000cf8 +#define MPC106_REG_DATA 0x80000cfc +#define MPC106_ISA_IO_PHYS 0x80000000 +#define MPC106_ISA_IO_BUS 0x00000000 +#define MPC106_ISA_IO_SIZE 0x00800000 +#define MPC106_PCI_IO_PHYS 0x81000000 +#define MPC106_PCI_IO_BUS 0x01000000 +#define MPC106_PCI_IO_SIZE 0x3e800000 +#define MPC106_PCI_MEM_PHYS 0xc0000000 +#define MPC106_PCI_MEM_BUS 0x00000000 +#define MPC106_PCI_MEM_SIZE 0x3f000000 +#define MPC106_PCI_MEMORY_PHYS 0x00000000 +#define MPC106_PCI_MEMORY_BUS 0x80000000 +#define MPC106_PCI_MEMORY_SIZE 0x80000000 +#else +#define MPC106_REG_ADDR 0xfec00cf8 +#define MPC106_REG_DATA 0xfee00cfc +#define MPC106_ISA_MEM_PHYS 0xfd000000 +#define MPC106_ISA_MEM_BUS 0x00000000 +#define MPC106_ISA_MEM_SIZE 0x01000000 +#define MPC106_ISA_IO_PHYS 0xfe000000 +#define MPC106_ISA_IO_BUS 0x00000000 +#define MPC106_ISA_IO_SIZE 0x00800000 +#define MPC106_PCI_IO_PHYS 0xfe800000 +#define MPC106_PCI_IO_BUS 0x00800000 +#define MPC106_PCI_IO_SIZE 0x00400000 +#define MPC106_PCI_MEM_PHYS 0x80000000 +#define MPC106_PCI_MEM_BUS 0x80000000 +#define MPC106_PCI_MEM_SIZE 0x7d000000 +#define MPC106_PCI_MEMORY_PHYS 0x00000000 +#define MPC106_PCI_MEMORY_BUS 0x00000000 +#define MPC106_PCI_MEMORY_SIZE 0x40000000 +#endif + +#define CMD_SERR 0x0100 +#define PCI_CMD_MASTER 0x0004 +#define PCI_CMD_MEMEN 0x0002 +#define PCI_CMD_IOEN 0x0001 + +#define PCI_STAT_NO_RSV_BITS 0xffff + +#define PCI_BUSNUM 0x40 +#define PCI_SUBBUSNUM 0x41 +#define PCI_DISCOUNT 0x42 + +#define PCI_PICR1 0xA8 +#define PICR1_CF_CBA(value) ((value & 0xff) << 24) +#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) +#define PICR1_PROC_TYPE_603 0x40000 +#define PICR1_PROC_TYPE_604 0x60000 +#define PICR1_MCP_EN 0x800 +#define PICR1_CF_DPARK 0x200 +#define PICR1_CF_LOOP_SNOOP 0x10 +#define PICR1_CF_L2_COPY_BACK 0x2 +#define PICR1_CF_L2_CACHE_MASK 0x3 +#define PICR1_CF_APARK 0x8 +#define PICR1_ADDRESS_MAP 0x10000 +#define PICR1_XIO_MODE 0x80000 +#define PICR1_CF_CACHE_1G 0x200000 + +#define PCI_PICR2 0xAC +#define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) +#define PICR2_CF_FLUSH_L2 0x10000000 +#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) +#define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) +#define PICR2_CF_INV_MODE 0x00001000 +#define PICR2_CF_MOD_HIGH 0x00020000 +#define PICR2_CF_HIT_HIGH 0x00010000 +#define PICR2_L2_SIZE_256K 0x00000000 +#define PICR2_L2_SIZE_512K 0x00000010 +#define PICR2_L2_SIZE_1MB 0x00000020 +#define PICR2_L2_EN 0x40000000 +#define PICR2_L2_UPDATE_EN 0x80000000 +#define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000 +#define PICR2_CF_FAST_CASTOUT 0x00000080 +#define PICR2_CF_WDATA 0x00000001 +#define PICR2_CF_DATA_RAM_PBURST 0x00400000 + +/* + * Memory controller + */ +#define MPC106_MCCR1 0xF0 +#define MCCR1_TYPE_EDO 0x00020000 +#define MCCR1_BK0_9BITS 0x0 +#define MCCR1_BK0_10BITS 0x1 +#define MCCR1_BK0_11BITS 0x2 +#define MCCR1_BK0_12BITS 0x3 +#define MCCR1_BK1_9BITS 0x0 +#define MCCR1_BK1_10BITS 0x4 +#define MCCR1_BK1_11BITS 0x8 +#define MCCR1_BK1_12BITS 0xC +#define MCCR1_BK2_9BITS 0x00 +#define MCCR1_BK2_10BITS 0x10 +#define MCCR1_BK2_11BITS 0x20 +#define MCCR1_BK2_12BITS 0x30 +#define MCCR1_BK3_9BITS 0x00 +#define MCCR1_BK3_10BITS 0x40 +#define MCCR1_BK3_11BITS 0x80 +#define MCCR1_BK3_12BITS 0xC0 +#define MCCR1_MEMGO 0x00080000 + +#define MPC106_MCCR2 0xF4 +#define MPC106_MCCR3 0xF8 +#define MPC106_MCCR4 0xFC + +#define MPC106_MSAR1 0x80 +#define MPC106_EMSAR1 0x88 +#define MPC106_EMSAR2 0x8C +#define MPC106_MEAR1 0x90 +#define MPC106_EMEAR1 0x98 +#define MPC106_EMEAR2 0x9C + +#define MPC106_MBER 0xA0 +#define MBER_BANK0 0x1 +#define MBER_BANK1 0x2 +#define MBER_BANK2 0x4 +#define MBER_BANK3 0x8 + +#endif diff --git a/include/mpc5xx.h b/include/mpc5xx.h new file mode 100644 index 0000000..7508f6d --- /dev/null +++ b/include/mpc5xx.h @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2003 + * Martin Winistoerfer, martinwinistoerfer@gmx.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * File: mpc5xx.h + * + * Discription: mpc5xx specific definitions + * + */ + +#ifndef __MPC5XX_H__ +#define __MPC5XX_H__ + + +/*----------------------------------------------------------------------- + * Exception offsets (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ + +/*----------------------------------------------------------------------- + * ISB bit in IMMR to set internal memory map + */ + +#define CFG_ISB ((CFG_IMMR / 0x00400000) << 1) + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control Register + */ +#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */ +#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */ +#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */ +#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */ +#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ +#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */ +#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration Register + */ +#define SIUMCR_EARB 0x80000000 /* External Arbitration */ +#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */ +#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */ +#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */ +#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */ +#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */ +#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */ +#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */ +#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */ +#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */ +#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */ +#define SIUMCR_DBGC01 0x00200000 /* - " - */ +#define SIUMCR_DBGC10 0x00400000 /* - " - */ +#define SIUMCR_DBGC11 0x00600000 /* - " - */ +#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */ +#define SIUMCR_DBPC01 0x00080000 /* - " - */ +#define SIUMCR_DBPC10 0x00100000 /* - " - */ +#define SIUMCR_DBPC11 0x00180000 /* - " - */ +#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ +#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ +#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ +#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ +#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ +#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ +#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ +#define SIUMCR_SC10 0x00004000 /* Single adress show */ +#define SIUMCR_SC11 0x00006000 /* Single adress */ +#define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */ +#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */ +#define SIUMCR_MLRC01 0x00000400 /* - " - */ +#define SIUMCR_MLRC10 0x00000800 /* - " - */ +#define SIUMCR_MLRC11 0x00000c00 /* - " - */ +#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control Register + */ +#define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */ +#define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */ +#define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */ + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control Register + */ +#define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */ +#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register + */ +#define PLPRCR_MF_MSK 0xfff00000 /* MF mask */ +#define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */ +#define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */ +#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */ +#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */ +#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */ +#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ +#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ +#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ +#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register + */ +#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ +#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ +#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ +#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ +#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ +#define SCCR_EBDF11 0x00060000 /* reserved */ +#define SCCR_TBS 0x02000000 /* Time Base Source */ +#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ +#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ +#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ +#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ +#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ + +/*----------------------------------------------------------------------- + * MC - Memory Controller + */ +#define BR_V 0x00000001 /* Bank valid */ +#define BR_BI 0x00000002 /* Burst inhibit */ +#define BR_PS_8 0x00000400 /* 8 bit port size */ +#define BR_PS_16 0x00000800 /* 16 bit port size */ +#define BR_PS_32 0x00000000 /* 32 bit port size */ +#define BR_LBDIR 0x00000008 /* Late burst data in progess */ +#define BR_SETA 0x00000004 /* External Data Acknowledge */ +#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ +#define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */ +#define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */ +#define OR_TRLX 0x00000001 /* Timing relaxed */ +#define OR_BSCY 0x00000060 /* Burst beats length in clocks */ +#define OR_ACS_10 0x00000600 /* Adress to chip-select setup */ +#define OR_CSNT 0x00000800 /* Chip-select negotation time */ +#define OR_ETHR 0x00000100 /* Extended hold time on read */ +#define OR_ADDR_MK_FF 0xFF000000 +#define OR_ADDR_MK_FFFF 0xFFFF0000 + +/*----------------------------------------------------------------------- + * UMCR - UIMB Module Configuration Register + */ +#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ +#define UMCR_HSPEED 0x10000000 /* Half speed */ + +/*----------------------------------------------------------------------- + * ICTRL - I-Bus Support Control Register + */ +#define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */ + + +#define NR_IRQS 0 /* Place this later in a separate file */ + +/*----------------------------------------------------------------------- + * SCI - Serial communication interface + */ + +#define SCI_TDRE 0x0100 /* Transmit data register empty */ +#define SCI_TE 0x0008 /* Transmitter enabled */ +#define SCI_RE 0x0004 /* Receiver enabled */ +#define SCI_RDRF 0x0040 /* Receive data register full */ +#define SCI_PE 0x0400 /* Parity enable */ +#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ +#define SCI_SCXDR_MK 0x00ff /* Data register mask */ +#define SCI_M_11 0x0200 /* Frame size is 11 bit */ +#define SCI_M_10 0x0000 /* Frame size is 10 bit */ +#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ +#define SCI_PORT_2 ((int)2) + +#endif /* __MPC5XX_H__ */ diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h new file mode 100644 index 0000000..f33d858 --- /dev/null +++ b/include/mpc5xxx.h @@ -0,0 +1,704 @@ +/* + * include/asm-ppc/mpc5xxx.h + * + * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx + * embedded cpu chips + * + * 2003 (c) MontaVista, Software, Inc. + * Author: Dale Farnsworth + * + * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASMPPC_MPC5XXX_H +#define __ASMPPC_MPC5XXX_H + +/* Processor name */ +#if defined(CONFIG_MPC5200) +#define CPU_ID_STR "MPC5200" +#elif defined(CONFIG_MGT5100) +#define CPU_ID_STR "MGT5100" +#endif + +/* Exception offsets (PowerPC standard) */ +#define EXC_OFF_SYS_RESET 0x0100 + +/* useful macros for manipulating CSx_START/STOP */ +#if defined(CONFIG_MGT5100) +#define START_REG(start) ((start) >> 15) +#define STOP_REG(start, size) (((start) + (size) - 1) >> 15) +#elif defined(CONFIG_MPC5200) +#define START_REG(start) ((start) >> 16) +#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) +#endif + +/* Internal memory map */ + +#define MPC5XXX_CS0_START (CFG_MBAR + 0x0004) +#define MPC5XXX_CS0_STOP (CFG_MBAR + 0x0008) +#define MPC5XXX_CS1_START (CFG_MBAR + 0x000c) +#define MPC5XXX_CS1_STOP (CFG_MBAR + 0x0010) +#define MPC5XXX_CS2_START (CFG_MBAR + 0x0014) +#define MPC5XXX_CS2_STOP (CFG_MBAR + 0x0018) +#define MPC5XXX_CS3_START (CFG_MBAR + 0x001c) +#define MPC5XXX_CS3_STOP (CFG_MBAR + 0x0020) +#define MPC5XXX_CS4_START (CFG_MBAR + 0x0024) +#define MPC5XXX_CS4_STOP (CFG_MBAR + 0x0028) +#define MPC5XXX_CS5_START (CFG_MBAR + 0x002c) +#define MPC5XXX_CS5_STOP (CFG_MBAR + 0x0030) +#define MPC5XXX_BOOTCS_START (CFG_MBAR + 0x004c) +#define MPC5XXX_BOOTCS_STOP (CFG_MBAR + 0x0050) +#define MPC5XXX_ADDECR (CFG_MBAR + 0x0054) + +#if defined(CONFIG_MGT5100) +#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034) +#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038) +#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c) +#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040) +#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044) +#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048) +#elif defined(CONFIG_MPC5200) +#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058) +#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c) +#define MPC5XXX_CS7_START (CFG_MBAR + 0x0060) +#define MPC5XXX_CS7_STOP (CFG_MBAR + 0x0064) +#define MPC5XXX_SDRAM_CS0CFG (CFG_MBAR + 0x0034) +#define MPC5XXX_SDRAM_CS1CFG (CFG_MBAR + 0x0038) +#endif + +#define MPC5XXX_SDRAM (CFG_MBAR + 0x0100) +#define MPC5XXX_CDM (CFG_MBAR + 0x0200) +#define MPC5XXX_LPB (CFG_MBAR + 0x0300) +#define MPC5XXX_ICTL (CFG_MBAR + 0x0500) +#define MPC5XXX_GPT (CFG_MBAR + 0x0600) +#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00) +#define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00) +#define MPC5XXX_PCI (CFG_MBAR + 0x0d00) +#define MPC5XXX_SPI (CFG_MBAR + 0x0f00) +#define MPC5XXX_USB (CFG_MBAR + 0x1000) +#define MPC5XXX_SDMA (CFG_MBAR + 0x1200) +#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00) + +#if defined(CONFIG_MGT5100) +#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000) +#define MPC5XXX_PSC2 (CFG_MBAR + 0x2400) +#define MPC5XXX_PSC3 (CFG_MBAR + 0x2800) +#elif defined(CONFIG_MPC5200) +#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000) +#define MPC5XXX_PSC2 (CFG_MBAR + 0x2200) +#define MPC5XXX_PSC3 (CFG_MBAR + 0x2400) +#define MPC5XXX_PSC4 (CFG_MBAR + 0x2600) +#define MPC5XXX_PSC5 (CFG_MBAR + 0x2800) +#define MPC5XXX_PSC6 (CFG_MBAR + 0x2c00) +#endif + +#define MPC5XXX_FEC (CFG_MBAR + 0x3000) +#define MPC5XXX_ATA (CFG_MBAR + 0x3A00) + +#define MPC5XXX_I2C1 (CFG_MBAR + 0x3D00) +#define MPC5XXX_I2C2 (CFG_MBAR + 0x3D40) + +#if defined(CONFIG_MGT5100) +#define MPC5XXX_SRAM (CFG_MBAR + 0x4000) +#define MPC5XXX_SRAM_SIZE (8*1024) +#elif defined(CONFIG_MPC5200) +#define MPC5XXX_SRAM (CFG_MBAR + 0x8000) +#define MPC5XXX_SRAM_SIZE (16*1024) +#endif + +/* SDRAM Controller */ +#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) +#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) +#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) +#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) +#if defined(CONFIG_MGT5100) +#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010) +#endif + +/* Clock Distribution Module */ +#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) +#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004) +#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c) +#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010) +#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020) + +/* Local Plus Bus interface */ +#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000) +#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004) +#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008) +#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c) +#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010) +#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014) +#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG +#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) +#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) +#if defined(CONFIG_MPC5200) +#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) +#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) +#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) +#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) +#endif + +#if defined(CONFIG_MPC5200) +/* XLB Arbiter registers */ +#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) +#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) +#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) +#endif + +/* GPIO registers */ +#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) + +/* Standard GPIO registers (simple, output only and simple interrupt */ +#define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) +#define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008) +#define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c) +#define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010) +#define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014) +#define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018) +#define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C) +#define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020) +#define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024) +#define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028) +#define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C) +#define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030) +#define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034) +#define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038) +#define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C) + +/* WakeUp GPIO registers */ +#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) +#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) +#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) +#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c) + +/* PCI registers */ +#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) +#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) +#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) +#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) +#if defined(CONFIG_MGT5100) +#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68) +#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c) +#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70) +#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74) +#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78) +#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c) +#elif defined(CONFIG_MPC5200) +#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) +#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) +#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) +#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c) +#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70) +#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74) +#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78) +#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80) +#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84) +#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) +#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) +#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) +#endif + +/* Interrupt Controller registers */ +#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) +#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004) +#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008) +#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c) +#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010) +#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014) +#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018) +#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c) +#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024) +#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028) +#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c) +#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030) +#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038) + +/* General Purpose Timers registers */ +#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) +#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) +#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) +#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) +#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) +#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) +#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) +#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) +#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) +#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) +#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) +#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) +#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) +#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) +#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) +#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) + +#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78) + +/* ATA registers */ +#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000) +#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008) +#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C) +#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C) + +/* I2Cn control register bits */ +#define I2C_EN 0x80 +#define I2C_IEN 0x40 +#define I2C_STA 0x20 +#define I2C_TX 0x10 +#define I2C_TXAK 0x08 +#define I2C_RSTA 0x04 +#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) + +/* I2Cn status register bits */ +#define I2C_CF 0x80 +#define I2C_AAS 0x40 +#define I2C_BB 0x20 +#define I2C_AL 0x10 +#define I2C_SRW 0x04 +#define I2C_IF 0x02 +#define I2C_RXAK 0x01 + +/* Programmable Serial Controller (PSC) status register bits */ +#define PSC_SR_CDE 0x0080 +#define PSC_SR_RXRDY 0x0100 +#define PSC_SR_RXFULL 0x0200 +#define PSC_SR_TXRDY 0x0400 +#define PSC_SR_TXEMP 0x0800 +#define PSC_SR_OE 0x1000 +#define PSC_SR_PE 0x2000 +#define PSC_SR_FE 0x4000 +#define PSC_SR_RB 0x8000 + +/* PSC Command values */ +#define PSC_RX_ENABLE 0x0001 +#define PSC_RX_DISABLE 0x0002 +#define PSC_TX_ENABLE 0x0004 +#define PSC_TX_DISABLE 0x0008 +#define PSC_SEL_MODE_REG_1 0x0010 +#define PSC_RST_RX 0x0020 +#define PSC_RST_TX 0x0030 +#define PSC_RST_ERR_STAT 0x0040 +#define PSC_RST_BRK_CHG_INT 0x0050 +#define PSC_START_BRK 0x0060 +#define PSC_STOP_BRK 0x0070 + +/* PSC Rx FIFO status bits */ +#define PSC_RX_FIFO_ERR 0x0040 +#define PSC_RX_FIFO_UF 0x0020 +#define PSC_RX_FIFO_OF 0x0010 +#define PSC_RX_FIFO_FR 0x0008 +#define PSC_RX_FIFO_FULL 0x0004 +#define PSC_RX_FIFO_ALARM 0x0002 +#define PSC_RX_FIFO_EMPTY 0x0001 + +/* PSC interrupt mask bits */ +#define PSC_IMR_TXRDY 0x0100 +#define PSC_IMR_RXRDY 0x0200 +#define PSC_IMR_DB 0x0400 +#define PSC_IMR_IPC 0x8000 + +/* PSC input port change bits */ +#define PSC_IPCR_CTS 0x01 +#define PSC_IPCR_DCD 0x02 + +/* PSC mode fields */ +#define PSC_MODE_5_BITS 0x00 +#define PSC_MODE_6_BITS 0x01 +#define PSC_MODE_7_BITS 0x02 +#define PSC_MODE_8_BITS 0x03 +#define PSC_MODE_PAREVEN 0x00 +#define PSC_MODE_PARODD 0x04 +#define PSC_MODE_PARFORCE 0x08 +#define PSC_MODE_PARNONE 0x10 +#define PSC_MODE_ERR 0x20 +#define PSC_MODE_FFULL 0x40 +#define PSC_MODE_RXRTS 0x80 + +#define PSC_MODE_ONE_STOP_5_BITS 0x00 +#define PSC_MODE_ONE_STOP 0x07 +#define PSC_MODE_TWO_STOP 0x0f + +/* ATA config fields */ +#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine + reset */ +#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */ +#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt + in PIO */ +#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports + IORDY protocol */ + +#ifndef __ASSEMBLY__ +struct mpc5xxx_psc { + volatile u8 mode; /* PSC + 0x00 */ + volatile u8 reserved0[3]; + union { /* PSC + 0x04 */ + volatile u16 status; + volatile u16 clock_select; + } sr_csr; +#define psc_status sr_csr.status +#define psc_clock_select sr_csr.clock_select + volatile u16 reserved1; + volatile u8 command; /* PSC + 0x08 */ + volatile u8 reserved2[3]; + union { /* PSC + 0x0c */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } buffer; +#define psc_buffer_8 buffer.buffer_8 +#define psc_buffer_16 buffer.buffer_16 +#define psc_buffer_32 buffer.buffer_32 + union { /* PSC + 0x10 */ + volatile u8 ipcr; + volatile u8 acr; + } ipcr_acr; +#define psc_ipcr ipcr_acr.ipcr +#define psc_acr ipcr_acr.acr + volatile u8 reserved3[3]; + union { /* PSC + 0x14 */ + volatile u16 isr; + volatile u16 imr; + } isr_imr; +#define psc_isr isr_imr.isr +#define psc_imr isr_imr.imr + volatile u16 reserved4; + volatile u8 ctur; /* PSC + 0x18 */ + volatile u8 reserved5[3]; + volatile u8 ctlr; /* PSC + 0x1c */ + volatile u8 reserved6[3]; + volatile u16 ccr; /* PSC + 0x20 */ + volatile u8 reserved7[14]; + volatile u8 ivr; /* PSC + 0x30 */ + volatile u8 reserved8[3]; + volatile u8 ip; /* PSC + 0x34 */ + volatile u8 reserved9[3]; + volatile u8 op1; /* PSC + 0x38 */ + volatile u8 reserved10[3]; + volatile u8 op0; /* PSC + 0x3c */ + volatile u8 reserved11[3]; + volatile u32 sicr; /* PSC + 0x40 */ + volatile u8 ircr1; /* PSC + 0x44 */ + volatile u8 reserved12[3]; + volatile u8 ircr2; /* PSC + 0x44 */ + volatile u8 reserved13[3]; + volatile u8 irsdr; /* PSC + 0x4c */ + volatile u8 reserved14[3]; + volatile u8 irmdr; /* PSC + 0x50 */ + volatile u8 reserved15[3]; + volatile u8 irfdr; /* PSC + 0x54 */ + volatile u8 reserved16[3]; + volatile u16 rfnum; /* PSC + 0x58 */ + volatile u16 reserved17; + volatile u16 tfnum; /* PSC + 0x5c */ + volatile u16 reserved18; + volatile u32 rfdata; /* PSC + 0x60 */ + volatile u16 rfstat; /* PSC + 0x64 */ + volatile u16 reserved20; + volatile u8 rfcntl; /* PSC + 0x68 */ + volatile u8 reserved21[5]; + volatile u16 rfalarm; /* PSC + 0x6e */ + volatile u16 reserved22; + volatile u16 rfrptr; /* PSC + 0x72 */ + volatile u16 reserved23; + volatile u16 rfwptr; /* PSC + 0x76 */ + volatile u16 reserved24; + volatile u16 rflrfptr; /* PSC + 0x7a */ + volatile u16 reserved25; + volatile u16 rflwfptr; /* PSC + 0x7e */ + volatile u32 tfdata; /* PSC + 0x80 */ + volatile u16 tfstat; /* PSC + 0x84 */ + volatile u16 reserved26; + volatile u8 tfcntl; /* PSC + 0x88 */ + volatile u8 reserved27[5]; + volatile u16 tfalarm; /* PSC + 0x8e */ + volatile u16 reserved28; + volatile u16 tfrptr; /* PSC + 0x92 */ + volatile u16 reserved29; + volatile u16 tfwptr; /* PSC + 0x96 */ + volatile u16 reserved30; + volatile u16 tflrfptr; /* PSC + 0x9a */ + volatile u16 reserved31; + volatile u16 tflwfptr; /* PSC + 0x9e */ +}; + +struct mpc5xxx_intr { + volatile u32 per_mask; /* INTR + 0x00 */ + volatile u32 per_pri1; /* INTR + 0x04 */ + volatile u32 per_pri2; /* INTR + 0x08 */ + volatile u32 per_pri3; /* INTR + 0x0c */ + volatile u32 ctrl; /* INTR + 0x10 */ + volatile u32 main_mask; /* INTR + 0x14 */ + volatile u32 main_pri1; /* INTR + 0x18 */ + volatile u32 main_pri2; /* INTR + 0x1c */ + volatile u32 reserved1; /* INTR + 0x20 */ + volatile u32 enc_status; /* INTR + 0x24 */ + volatile u32 crit_status; /* INTR + 0x28 */ + volatile u32 main_status; /* INTR + 0x2c */ + volatile u32 per_status; /* INTR + 0x30 */ + volatile u32 reserved2; /* INTR + 0x34 */ + volatile u32 per_error; /* INTR + 0x38 */ +}; + +struct mpc5xxx_gpio { + volatile u32 port_config; /* GPIO + 0x00 */ + volatile u32 simple_gpioe; /* GPIO + 0x04 */ + volatile u32 simple_ode; /* GPIO + 0x08 */ + volatile u32 simple_ddr; /* GPIO + 0x0c */ + volatile u32 simple_dvo; /* GPIO + 0x10 */ + volatile u32 simple_ival; /* GPIO + 0x14 */ + volatile u8 outo_gpioe; /* GPIO + 0x18 */ + volatile u8 reserved1[3]; /* GPIO + 0x19 */ + volatile u8 outo_dvo; /* GPIO + 0x1c */ + volatile u8 reserved2[3]; /* GPIO + 0x1d */ + volatile u8 sint_gpioe; /* GPIO + 0x20 */ + volatile u8 reserved3[3]; /* GPIO + 0x21 */ + volatile u8 sint_ode; /* GPIO + 0x24 */ + volatile u8 reserved4[3]; /* GPIO + 0x25 */ + volatile u8 sint_ddr; /* GPIO + 0x28 */ + volatile u8 reserved5[3]; /* GPIO + 0x29 */ + volatile u8 sint_dvo; /* GPIO + 0x2c */ + volatile u8 reserved6[3]; /* GPIO + 0x2d */ + volatile u8 sint_inten; /* GPIO + 0x30 */ + volatile u8 reserved7[3]; /* GPIO + 0x31 */ + volatile u16 sint_itype; /* GPIO + 0x34 */ + volatile u16 reserved8; /* GPIO + 0x36 */ + volatile u8 gpio_control; /* GPIO + 0x38 */ + volatile u8 reserved9[3]; /* GPIO + 0x39 */ + volatile u8 sint_istat; /* GPIO + 0x3c */ + volatile u8 sint_ival; /* GPIO + 0x3d */ + volatile u8 bus_errs; /* GPIO + 0x3e */ + volatile u8 reserved10; /* GPIO + 0x3f */ +}; + +struct mpc5xxx_sdma { + volatile u32 taskBar; /* SDMA + 0x00 */ + volatile u32 currentPointer; /* SDMA + 0x04 */ + volatile u32 endPointer; /* SDMA + 0x08 */ + volatile u32 variablePointer; /* SDMA + 0x0c */ + + volatile u8 IntVect1; /* SDMA + 0x10 */ + volatile u8 IntVect2; /* SDMA + 0x11 */ + volatile u16 PtdCntrl; /* SDMA + 0x12 */ + + volatile u32 IntPend; /* SDMA + 0x14 */ + volatile u32 IntMask; /* SDMA + 0x18 */ + + volatile u16 tcr_0; /* SDMA + 0x1c */ + volatile u16 tcr_1; /* SDMA + 0x1e */ + volatile u16 tcr_2; /* SDMA + 0x20 */ + volatile u16 tcr_3; /* SDMA + 0x22 */ + volatile u16 tcr_4; /* SDMA + 0x24 */ + volatile u16 tcr_5; /* SDMA + 0x26 */ + volatile u16 tcr_6; /* SDMA + 0x28 */ + volatile u16 tcr_7; /* SDMA + 0x2a */ + volatile u16 tcr_8; /* SDMA + 0x2c */ + volatile u16 tcr_9; /* SDMA + 0x2e */ + volatile u16 tcr_a; /* SDMA + 0x30 */ + volatile u16 tcr_b; /* SDMA + 0x32 */ + volatile u16 tcr_c; /* SDMA + 0x34 */ + volatile u16 tcr_d; /* SDMA + 0x36 */ + volatile u16 tcr_e; /* SDMA + 0x38 */ + volatile u16 tcr_f; /* SDMA + 0x3a */ + + volatile u8 IPR0; /* SDMA + 0x3c */ + volatile u8 IPR1; /* SDMA + 0x3d */ + volatile u8 IPR2; /* SDMA + 0x3e */ + volatile u8 IPR3; /* SDMA + 0x3f */ + volatile u8 IPR4; /* SDMA + 0x40 */ + volatile u8 IPR5; /* SDMA + 0x41 */ + volatile u8 IPR6; /* SDMA + 0x42 */ + volatile u8 IPR7; /* SDMA + 0x43 */ + volatile u8 IPR8; /* SDMA + 0x44 */ + volatile u8 IPR9; /* SDMA + 0x45 */ + volatile u8 IPR10; /* SDMA + 0x46 */ + volatile u8 IPR11; /* SDMA + 0x47 */ + volatile u8 IPR12; /* SDMA + 0x48 */ + volatile u8 IPR13; /* SDMA + 0x49 */ + volatile u8 IPR14; /* SDMA + 0x4a */ + volatile u8 IPR15; /* SDMA + 0x4b */ + volatile u8 IPR16; /* SDMA + 0x4c */ + volatile u8 IPR17; /* SDMA + 0x4d */ + volatile u8 IPR18; /* SDMA + 0x4e */ + volatile u8 IPR19; /* SDMA + 0x4f */ + volatile u8 IPR20; /* SDMA + 0x50 */ + volatile u8 IPR21; /* SDMA + 0x51 */ + volatile u8 IPR22; /* SDMA + 0x52 */ + volatile u8 IPR23; /* SDMA + 0x53 */ + volatile u8 IPR24; /* SDMA + 0x54 */ + volatile u8 IPR25; /* SDMA + 0x55 */ + volatile u8 IPR26; /* SDMA + 0x56 */ + volatile u8 IPR27; /* SDMA + 0x57 */ + volatile u8 IPR28; /* SDMA + 0x58 */ + volatile u8 IPR29; /* SDMA + 0x59 */ + volatile u8 IPR30; /* SDMA + 0x5a */ + volatile u8 IPR31; /* SDMA + 0x5b */ + + volatile u32 res1; /* SDMA + 0x5c */ + volatile u32 res2; /* SDMA + 0x60 */ + volatile u32 res3; /* SDMA + 0x64 */ + volatile u32 MDEDebug; /* SDMA + 0x68 */ + volatile u32 ADSDebug; /* SDMA + 0x6c */ + volatile u32 Value1; /* SDMA + 0x70 */ + volatile u32 Value2; /* SDMA + 0x74 */ + volatile u32 Control; /* SDMA + 0x78 */ + volatile u32 Status; /* SDMA + 0x7c */ + volatile u32 EU00; /* SDMA + 0x80 */ + volatile u32 EU01; /* SDMA + 0x84 */ + volatile u32 EU02; /* SDMA + 0x88 */ + volatile u32 EU03; /* SDMA + 0x8c */ + volatile u32 EU04; /* SDMA + 0x90 */ + volatile u32 EU05; /* SDMA + 0x94 */ + volatile u32 EU06; /* SDMA + 0x98 */ + volatile u32 EU07; /* SDMA + 0x9c */ + volatile u32 EU10; /* SDMA + 0xa0 */ + volatile u32 EU11; /* SDMA + 0xa4 */ + volatile u32 EU12; /* SDMA + 0xa8 */ + volatile u32 EU13; /* SDMA + 0xac */ + volatile u32 EU14; /* SDMA + 0xb0 */ + volatile u32 EU15; /* SDMA + 0xb4 */ + volatile u32 EU16; /* SDMA + 0xb8 */ + volatile u32 EU17; /* SDMA + 0xbc */ + volatile u32 EU20; /* SDMA + 0xc0 */ + volatile u32 EU21; /* SDMA + 0xc4 */ + volatile u32 EU22; /* SDMA + 0xc8 */ + volatile u32 EU23; /* SDMA + 0xcc */ + volatile u32 EU24; /* SDMA + 0xd0 */ + volatile u32 EU25; /* SDMA + 0xd4 */ + volatile u32 EU26; /* SDMA + 0xd8 */ + volatile u32 EU27; /* SDMA + 0xdc */ + volatile u32 EU30; /* SDMA + 0xe0 */ + volatile u32 EU31; /* SDMA + 0xe4 */ + volatile u32 EU32; /* SDMA + 0xe8 */ + volatile u32 EU33; /* SDMA + 0xec */ + volatile u32 EU34; /* SDMA + 0xf0 */ + volatile u32 EU35; /* SDMA + 0xf4 */ + volatile u32 EU36; /* SDMA + 0xf8 */ + volatile u32 EU37; /* SDMA + 0xfc */ +}; + +struct mpc5xxx_i2c { + volatile u32 madr; /* I2Cn + 0x00 */ + volatile u32 mfdr; /* I2Cn + 0x04 */ + volatile u32 mcr; /* I2Cn + 0x08 */ + volatile u32 msr; /* I2Cn + 0x0C */ + volatile u32 mdr; /* I2Cn + 0x10 */ +}; + +struct mpc5xxx_spi { + volatile u8 cr1; /* SPI + 0x0F00 */ + volatile u8 cr2; /* SPI + 0x0F01 */ + volatile u8 reserved1[2]; + volatile u8 brr; /* SPI + 0x0F04 */ + volatile u8 sr; /* SPI + 0x0F05 */ + volatile u8 reserved2[3]; + volatile u8 dr; /* SPI + 0x0F09 */ + volatile u8 reserved3[3]; + volatile u8 pdr; /* SPI + 0x0F0D */ + volatile u8 reserved4[2]; + volatile u8 ddr; /* SPI + 0x0F10 */ +}; + + +struct mpc5xxx_gpt { + volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */ + volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */ + volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */ + volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */ +}; + +struct mpc5xxx_gpt_0_7 { + struct mpc5xxx_gpt gpt0; + struct mpc5xxx_gpt gpt1; + struct mpc5xxx_gpt gpt2; + struct mpc5xxx_gpt gpt3; + struct mpc5xxx_gpt gpt4; + struct mpc5xxx_gpt gpt5; + struct mpc5xxx_gpt gpt6; + struct mpc5xxx_gpt gpt7; +}; + +struct mscan_buffer { + volatile u8 idr[0x8]; /* 0x00 */ + volatile u8 dsr[0x10]; /* 0x08 */ + volatile u8 dlr; /* 0x18 */ + volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */ + volatile u16 rsrv1; /* 0x1A */ + volatile u8 tsrh; /* 0x1C */ + volatile u8 tsrl; /* 0x1D */ + volatile u16 rsrv2; /* 0x1E */ +}; + +struct mpc5xxx_mscan { + volatile u8 canctl0; /* MSCAN + 0x00 */ + volatile u8 canctl1; /* MSCAN + 0x01 */ + volatile u16 rsrv1; /* MSCAN + 0x02 */ + volatile u8 canbtr0; /* MSCAN + 0x04 */ + volatile u8 canbtr1; /* MSCAN + 0x05 */ + volatile u16 rsrv2; /* MSCAN + 0x06 */ + volatile u8 canrflg; /* MSCAN + 0x08 */ + volatile u8 canrier; /* MSCAN + 0x09 */ + volatile u16 rsrv3; /* MSCAN + 0x0A */ + volatile u8 cantflg; /* MSCAN + 0x0C */ + volatile u8 cantier; /* MSCAN + 0x0D */ + volatile u16 rsrv4; /* MSCAN + 0x0E */ + volatile u8 cantarq; /* MSCAN + 0x10 */ + volatile u8 cantaak; /* MSCAN + 0x11 */ + volatile u16 rsrv5; /* MSCAN + 0x12 */ + volatile u8 cantbsel; /* MSCAN + 0x14 */ + volatile u8 canidac; /* MSCAN + 0x15 */ + volatile u16 rsrv6[3]; /* MSCAN + 0x16 */ + volatile u8 canrxerr; /* MSCAN + 0x1C */ + volatile u8 cantxerr; /* MSCAN + 0x1D */ + volatile u16 rsrv7; /* MSCAN + 0x1E */ + volatile u8 canidar0; /* MSCAN + 0x20 */ + volatile u8 canidar1; /* MSCAN + 0x21 */ + volatile u16 rsrv8; /* MSCAN + 0x22 */ + volatile u8 canidar2; /* MSCAN + 0x24 */ + volatile u8 canidar3; /* MSCAN + 0x25 */ + volatile u16 rsrv9; /* MSCAN + 0x26 */ + volatile u8 canidmr0; /* MSCAN + 0x28 */ + volatile u8 canidmr1; /* MSCAN + 0x29 */ + volatile u16 rsrv10; /* MSCAN + 0x2A */ + volatile u8 canidmr2; /* MSCAN + 0x2C */ + volatile u8 canidmr3; /* MSCAN + 0x2D */ + volatile u16 rsrv11; /* MSCAN + 0x2E */ + volatile u8 canidar4; /* MSCAN + 0x30 */ + volatile u8 canidar5; /* MSCAN + 0x31 */ + volatile u16 rsrv12; /* MSCAN + 0x32 */ + volatile u8 canidar6; /* MSCAN + 0x34 */ + volatile u8 canidar7; /* MSCAN + 0x35 */ + volatile u16 rsrv13; /* MSCAN + 0x36 */ + volatile u8 canidmr4; /* MSCAN + 0x38 */ + volatile u8 canidmr5; /* MSCAN + 0x39 */ + volatile u16 rsrv14; /* MSCAN + 0x3A */ + volatile u8 canidmr6; /* MSCAN + 0x3C */ + volatile u8 canidmr7; /* MSCAN + 0x3D */ + volatile u16 rsrv15; /* MSCAN + 0x3E */ + + struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */ + struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */ + }; + +/* function prototypes */ +void loadtask(int basetask, int tasks); + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASMPPC_MPC5XXX_H */ diff --git a/include/mpc8220.h b/include/mpc8220.h new file mode 100644 index 0000000..ff7acc6 --- /dev/null +++ b/include/mpc8220.h @@ -0,0 +1,716 @@ +/* + * include/mpc8220.h + * + * Prototypes, etc. for the Motorola MPC8220 + * embedded cpu chips + * + * 2004 (c) Freescale, Inc. + * Author: TsiChung Liew + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MPC8220_H__ +#define __MPC8220_H__ + +/* Processor name */ +#if defined(CONFIG_MPC8220) +#define CPU_ID_STR "MPC8220" +#endif + +/* Exception offsets (PowerPC standard) */ +#define EXC_OFF_SYS_RESET 0x0100 + +/* Internal memory map */ +/* MPC8220 Internal Register MMAP */ +#define MMAP_MBAR (CFG_MBAR + 0x00000000) /* chip selects */ +#define MMAP_MEMCTL (CFG_MBAR + 0x00000100) /* sdram controller */ +#define MMAP_XLBARB (CFG_MBAR + 0x00000200) /* xlb arbitration control */ +#define MMAP_CDM (CFG_MBAR + 0x00000300) /* clock distribution module */ +#define MMAP_VDOPLL (CFG_MBAR + 0x00000400) /* video PLL */ +#define MMAP_FB (CFG_MBAR + 0x00000500) /* flex bus controller */ +#define MMAP_PCFG (CFG_MBAR + 0x00000600) /* port config */ +#define MMAP_ICTL (CFG_MBAR + 0x00000700) /* interrupt controller */ +#define MMAP_GPTMR (CFG_MBAR + 0x00000800) /* general purpose timers */ +#define MMAP_SLTMR (CFG_MBAR + 0x00000900) /* slice timers */ +#define MMAP_GPIO (CFG_MBAR + 0x00000A00) /* gpio module */ +#define MMAP_XCPCI (CFG_MBAR + 0x00000B00) /* pci controller */ +#define MMAP_PCIARB (CFG_MBAR + 0x00000C00) /* pci arbiter */ +#define MMAP_EXTDMA1 (CFG_MBAR + 0x00000D00) /* external dma1 */ +#define MMAP_EXTDMA2 (CFG_MBAR + 0x00000E00) /* external dma1 */ +#define MMAP_USBH (CFG_MBAR + 0x00001000) /* usb host */ +#define MMAP_CMTMR (CFG_MBAR + 0x00007f00) /* comm timers */ +#define MMAP_DMA (CFG_MBAR + 0x00008000) /* dma */ +#define MMAP_USBD (CFG_MBAR + 0x00008200) /* usb device */ +#define MMAP_COMMPCI (CFG_MBAR + 0x00008400) /* pci comm Bus regs */ +#define MMAP_1284 (CFG_MBAR + 0x00008500) /* 1284 */ +#define MMAP_PEV (CFG_MBAR + 0x00008600) /* print engine video */ +#define MMAP_PSC1 (CFG_MBAR + 0x00008800) /* psc1 block */ +#define MMAP_I2C (CFG_MBAR + 0x00008f00) /* i2c controller */ +#define MMAP_FEC1 (CFG_MBAR + 0x00009000) /* fast ethernet 1 */ +#define MMAP_FEC2 (CFG_MBAR + 0x00009800) /* fast ethernet 2 */ +#define MMAP_JBIGRAM (CFG_MBAR + 0x0000a000) /* jbig RAM */ +#define MMAP_JBIG (CFG_MBAR + 0x0000c000) /* jbig */ +#define MMAP_PDLA (CFG_MBAR + 0x00010000) /* */ +#define MMAP_SRAMCFG (CFG_MBAR + 0x0001ff00) /* SRAM config */ +#define MMAP_SRAM (CFG_MBAR + 0x00020000) /* SRAM */ + +#define SRAM_SIZE 0x8000 /* 32 KB */ + +/* ------------------------------------------------------------------------ */ +/* + * Macro for Programmable Serial Channel + */ +/* equates for mode reg. 1 for channel A or B */ +#define PSC_MR1_RX_RTS 0x80000000 /* receiver RTS enabled */ +#define PSC_MR1_RX_INT 0x40000000 /* receiver intrupt enabled */ +#define PSC_MR1_ERR_MODE 0x20000000 /* block error mode */ +#define PSC_MR1_PAR_MODE_MULTI 0x18000000 /* multi_drop mode */ +#define PSC_MR1_NO_PARITY 0x10000000 /* no parity mode */ +#define PSC_MR1_ALWAYS_0 0x08000000 /* force parity mode */ +#define PSC_MR1_ALWAYS_1 0x0c000000 /* force parity mode */ +#define PSC_MR1_EVEN_PARITY 0x00000000 /* parity mode */ +#define PSC_MR1_ODD_PARITY 0x04000000 /* 0 = even, 1 = odd */ +#define PSC_MR1_BITS_CHAR_8 0x03000000 /* 8 bits */ +#define PSC_MR1_BITS_CHAR_7 0x02000000 /* 7 bits */ +#define PSC_MR1_BITS_CHAR_6 0x01000000 /* 6 bits */ +#define PSC_MR1_BITS_CHAR_5 0x00000000 /* 5 bits */ + +/* equates for mode reg. 2 for channel A or B */ +#define PSC_MR2_NORMAL_MODE 0x00000000 /* normal channel mode */ +#define PSC_MR2_AUTO_MODE 0x40000000 /* automatic channel mode */ +#define PSC_MR2_LOOPBACK_LOCL 0x80000000 /* local loopback channel mode */ +#define PSC_MR2_LOOPBACK_REMT 0xc0000000 /* remote loopback channel mode */ +#define PSC_MR2_TX_RTS 0x20000000 /* transmitter RTS enabled */ +#define PSC_MR2_TX_CTS 0x10000000 /* transmitter CTS enabled */ +#define PSC_MR2_STOP_BITS_2 0x0f000000 /* 2 stop bits */ +#define PSC_MR2_STOP_BITS_1 0x07000000 /* 1 stop bit */ + +/* equates for status reg. A or B */ +#define PSC_SR_BREAK 0x80000000 /* received break */ +#define PSC_SR_NEOF PSC_SR_BREAK /* Next byte is EOF - MIR/FIR */ +#define PSC_SR_FRAMING 0x40000000 /* framing error */ +#define PSC_SR_PHYERR PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */ +#define PSC_SR_PARITY 0x20000000 /* parity error */ +#define PSC_SR_CRCERR PSC_SR_PARITY /* CRC error */ +#define PSC_SR_OVERRUN 0x10000000 /* overrun error */ +#define PSC_SR_TXEMT 0x08000000 /* transmitter empty */ +#define PSC_SR_TXRDY 0x04000000 /* transmitter ready*/ +#define PSC_SR_FFULL 0x02000000 /* fifo full */ +#define PSC_SR_RXRDY 0x01000000 /* receiver ready */ +#define PSC_SR_DEOF 0x00800000 /* Detect EOF or RX-FIFO contain EOF */ +#define PSC_SR_ERR 0x00400000 /* Error Status including FIFO */ + +/* equates for clock select reg. */ +#define PSC_CSRX16EXT_CLK 0x1110 /* x 16 ext_clock */ +#define PSC_CSRX1EXT_CLK 0x1111 /* x 1 ext_clock */ + +/* equates for command reg. A or B */ +#define PSC_CR_NO_COMMAND 0x00000000 /* no command */ +#define PSC_CR_RST_MR_PTR_CMD 0x10000000 /* reset mr pointer command */ +#define PSC_CR_RST_RX_CMD 0x20000000 /* reset receiver command */ +#define PSC_CR_RST_TX_CMD 0x30000000 /* reset transmitter command */ +#define PSC_CR_RST_ERR_STS_CMD 0x40000000 /* reset error status cmnd */ +#define PSC_CR_RST_BRK_INT_CMD 0x50000000 /* reset break int. command */ +#define PSC_CR_STR_BREAK_CMD 0x60000000 /* start break command */ +#define PSC_CR_STP_BREAK_CMD 0x70000000 /* stop break command */ +#define PSC_CR_RX_ENABLE 0x01000000 /* receiver enabled */ +#define PSC_CR_RX_DISABLE 0x02000000 /* receiver disabled */ +#define PSC_CR_TX_ENABLE 0x04000000 /* transmitter enabled */ +#define PSC_CR_TX_DISABLE 0x08000000 /* transmitter disabled */ + +/* equates for input port change reg. */ +#define PSC_IPCR_SYNC 0x80000000 /* Sync Detect */ +#define PSC_IPCR_D_CTS 0x10000000 /* Delta CTS */ +#define PSC_IPCR_CTS 0x01000000 /* CTS - current state of PSC_CTS */ + +/* equates for auxiliary control reg. (timer and counter clock selects) */ +#define PSC_ACR_BRG 0x80000000 /* for 68681 compatibility + baud rate gen select + 0 = set 1; 1 = set 2 + equates are set 2 ONLY */ +#define PSC_ACR_TMR_EXT_CLK_16 0x70000000 /* xtnl clock divided by 16 */ +#define PSC_ACR_TMR_EXT_CLK 0x60000000 /* external clock */ +#define PSC_ACR_TMR_IP2_16 0x50000000 /* ip2 divided by 16 */ +#define PSC_ACR_TMR_IP2 0x40000000 /* ip2 */ +#define PSC_ACR_CTR_EXT_CLK_16 0x30000000 /* xtnl clock divided by 16 */ +#define PSC_ACR_CTR_TXCB 0x20000000 /* channel B xmitr clock */ +#define PSC_ACR_CTR_TXCA 0x10000000 /* channel A xmitr clock */ +#define PSC_ACR_CTR_IP2 0x00000000 /* ip2 */ +#define PSC_ACR_IEC0 0x01000000 /* interrupt enable ctrl for D_CTS */ + +/* equates for int. status reg. */ +#define PSC_ISR_IPC 0x80000000 /* input port change*/ +#define PSC_ISR_BREAK 0x04000000 /* delta break */ +#define PSC_ISR_RX_RDY 0x02000000 /* receiver rdy /fifo full */ +#define PSC_ISR_TX_RDY 0x01000000 /* transmitter ready */ +#define PSC_ISR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */ +#define PSC_ISR_ERR 0x00400000 /* Error Status including FIFO */ + +/* equates for int. mask reg. */ +#define PSC_IMR_CLEAR 0xff000000 /* Clear the imr */ +#define PSC_IMR_IPC 0x80000000 /* input port change*/ +#define PSC_IMR_BREAK 0x04000000 /* delta break */ +#define PSC_IMR_RX_RDY 0x02000000 /* rcvr ready / fifo full */ +#define PSC_IMR_TX_RDY 0x01000000 /* transmitter ready */ +#define PSC_IMR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */ +#define PSC_IMR_ERR 0x00400000 /* Error Status including FIFO */ + +/* equates for input port reg. */ +#define PSC_IP_LPWRB 0x80000000 /* Low power mode in Ac97 */ +#define PSC_IP_TGL 0x40000000 /* test usage */ +#define PSC_IP_CTS 0x01000000 /* CTS */ + +/* equates for output port bit set reg. */ +#define PSC_OPSET_RTS 0x01000000 /* Assert PSC_RTS output */ + +/* equates for output port bit reset reg. */ +#define PSC_OPRESET_RTS 0x01000000 /* Assert PSC_RTS output */ + +/* equates for rx FIFO number of data reg. */ +#define PSC_RFNUM(x) ((x&0xff)<<24)/* receive count */ + +/* equates for tx FIFO number of data reg. */ +#define PSC_TFNUM(x) ((x&0xff)<<24)/* receive count */ + +/* equates for rx FIFO status reg */ +#define PSC_RFSTAT_TAG(x) ((x&3)<<28) /* tag */ +#define PSC_RFSTAT_FRAME0 0x08 /* Frame Indicator 0 */ +#define PSC_RFSTAT_FRAME1 0x04 /* Frame Indicator 1 */ +#define PSC_RFSTAT_FRAME2 0x02 /* Frame Indicator 2 */ +#define PSC_RFSTAT_FRAME3 0x01 /* Frame Indicator 3 */ +#define PSC_RFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */ +#define PSC_RFSTAT_ERR 0x00400000 /* Fifo err */ +#define PSC_RFSTAT_UF 0x00200000 /* Underflow */ +#define PSC_RFSTAT_OF 0x00100000 /* overflow */ +#define PSC_RFSTAT_FR 0x00080000 /* frame ready */ +#define PSC_RFSTAT_FULL 0x00040000 /* full */ +#define PSC_RFSTAT_ALARM 0x00020000 /* alarm */ +#define PSC_RFSTAT_EMPTY 0x00010000 /* empty */ + +/* equates for tx FIFO status reg */ +#define PSC_TFSTAT_TAG(x) ((x&3)<<28) /* tag */ +#define PSC_TFSTAT_FRAME0 0x08 /* Frame Indicator 0 */ +#define PSC_TFSTAT_FRAME1 0x04 /* Frame Indicator 1 */ +#define PSC_TFSTAT_FRAME2 0x02 /* Frame Indicator 2 */ +#define PSC_TFSTAT_FRAME3 0x01 /* Frame Indicator 3 */ +#define PSC_TFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */ +#define PSC_TFSTAT_ERR 0x00400000 /* Fifo err */ +#define PSC_TFSTAT_UF 0x00200000 /* Underflow */ +#define PSC_TFSTAT_OF 0x00100000 /* overflow */ +#define PSC_TFSTAT_FR 0x00080000 /* frame ready */ +#define PSC_TFSTAT_FULL 0x00040000 /* full */ +#define PSC_TFSTAT_ALARM 0x00020000 /* alarm */ +#define PSC_TFSTAT_EMPTY 0x00010000 /* empty */ + +/* equates for rx FIFO control reg. */ +#define PSC_RFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */ +#define PSC_RFCNTL_FRAME 0x08000000 /* Frame mode enable */ +#define PSC_RFCNTL_GR(x) ((x&7)<<24) /* Granularity */ + +/* equates for tx FIFO control reg. */ +#define PSC_TFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */ +#define PSC_TFCNTL_FRAME 0x08000000 /* Frame mode enable */ +#define PSC_TFCNTL_GR(x) ((x&7)<<24) /* Granularity */ + +/* equates for rx FIFO alarm reg */ +#define PSC_RFALARM(x) (x&0x1ff) /* Alarm */ + +/* equates for tx FIFO alarm reg */ +#define PSC_TFALARM(x) (x&0x1ff) /* Alarm */ + +/* equates for rx FIFO read pointer */ +#define PSC_RFRPTR(x) (x&0x1ff) /* read pointer */ + +/* equates for tx FIFO read pointer */ +#define PSC_TFRPTR(x) (x&0x1ff) /* read pointer */ + +/* equates for rx FIFO write pointer */ +#define PSC_RFWPTR(x) (x&0x1ff) /* write pointer */ + +/* equates for rx FIFO write pointer */ +#define PSC_TFWPTR(x) (x&0x1ff) /* write pointer */ + +/* equates for rx FIFO last read frame pointer reg */ +#define PSC_RFLRFPTR(x) (x&0x1ff) /* last read frame pointer */ + +/* equates for tx FIFO last read frame pointer reg */ +#define PSC_TFLRFPTR(x) (x&0x1ff) /* last read frame pointer */ + +/* equates for rx FIFO last write frame pointer reg */ +#define PSC_RFLWFPTR(x) (x&0x1ff) /* last write frame pointer */ + +/* equates for tx FIFO last write frame pointer reg */ +#define PSC_TFLWFPTR(x) (x&0x1ff) /* last write frame pointer */ + +/* PCI configuration (only for PLL determination)*/ +#define PCI_REG_PCIGSCR (MMAP_XCPCI + 0x60) /* Global status/control register */ +#define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK 0x07000000 +#define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT 24 + +#define PCI_REG_PCICAR (MMAP_XCPCI + 0xF8) /* Configuration Address Register */ + +/* ------------------------------------------------------------------------ */ +/* + * Macro for General Purpose Timer + */ +/* Enable and Mode Select */ +#define GPT_OCT(x) (x & 0x3)<<4/* Output Compare Type */ +#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */ +#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */ +#define GPT_CTRL_CE 0x10 /* Counter Enable */ +#define GPT_CTRL_STPCNT 0x04 /* Stop continous */ +#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */ +#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */ +#define GPT_MODE_GPIO(x) (x & 0x3)<<4/* Gpio Mode Type */ +#define GPT_TMS_ICT 0x01 /* Input Capture Enable */ +#define GPT_TMS_OCT 0x02 /* Output Capture Enable */ +#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */ +#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */ + +#define GPT_PWM_WIDTH(x) (x & 0xffff) + +/* Status */ +#define GPT_STA_CAPTURE(x) (x & 0xffff)/* Read of internal counter */ + +#define GPT_OVFPIN_OVF(x) (x & 0x70) /* Internal counter roll over */ +#define GPT_OVFPIN_PIN 0x01 /* Input pin - Timer 0 and 1 */ + +#define GPT_INT_TEXP 0x08 /* Timer Expired in Internal Timer mode */ +#define GPT_INT_PWMP 0x04 /* PWM end of period occurred */ +#define GPT_INT_COMP 0x02 /* OC reference event occurred */ +#define GPT_INT_CAPT 0x01 /* IC reference event occurred */ + +/* ------------------------------------------------------------------------ */ +/* + * Port configuration + */ +#define CFG_FEC1_PORT0_CONFIG 0x00000000 +#define CFG_FEC1_PORT1_CONFIG 0x00000000 +#define CFG_1284_PORT0_CONFIG 0x00000000 +#define CFG_1284_PORT1_CONFIG 0x00000000 +#define CFG_FEC2_PORT2_CONFIG 0x00000000 +#define CFG_PEV_PORT2_CONFIG 0x00000000 +#define CFG_GP0_PORT0_CONFIG 0x00000000 +#define CFG_GP1_PORT2_CONFIG 0xaaaaaac0 +#define CFG_PSC_PORT3_CONFIG 0x00020000 +#define CFG_CS1_PORT3_CONFIG 0x00000000 +#define CFG_CS2_PORT3_CONFIG 0x10000000 +#define CFG_CS3_PORT3_CONFIG 0x40000000 +#define CFG_CS4_PORT3_CONFIG 0x00000400 +#define CFG_CS5_PORT3_CONFIG 0x00000200 +#define CFG_PCI_PORT3_CONFIG 0x01400180 +#define CFG_I2C_PORT3_CONFIG 0x00000000 +#define CFG_GP2_PORT3_CONFIG 0x000200a0 + +/* ------------------------------------------------------------------------ */ +/* + * DRAM configuration + */ + +/* Field definitions for the control register */ +#define CTL_MODE_ENABLE_SHIFT 31 +#define CTL_CKE_SHIFT 30 +#define CTL_DDR_SHIFT 29 +#define CTL_REFRESH_SHIFT 28 +#define CTL_ADDRMUX_SHIFT 24 +#define CTL_PRECHARGE_SHIFT 23 +#define CTL_DRIVE_RULE_SHIFT 22 +#define CTL_REFRESH_INTERVAL_SHIFT 16 +#define CTL_DQSOEN_SHIFT 8 +#define CTL_BUFFERED_SHIFT 4 +#define CTL_REFRESH_CMD_SHIFT 2 +#define CTL_PRECHARGE_CMD_SHIFT 1 + +#define CTL_MODE_ENABLE (1<0xd27 - base address 2 - 5 */ + u32 cis; /* 0xb28 - cardBus CIS pointer */ + u32 sub_sys_ven_id; /* 0xb2c - sub system ID/ subsystem vendor ID */ + u32 reserved2; /* 0xb30 - expansion ROM base address */ + u32 reserved3; /* 0xb00 - reserved */ + u32 reserved4; /* 0xb00 - reserved */ + u32 mlat_mgnt_ipl; /* 0xb3c - MaxLat/MinGnt/ int pin/int line */ + u32 reserved5[8]; + /* MPC8220 specific - not accessible in PCI header space externally */ + u32 glb_stat_ctl; /* 0xb60 - Global Status Control */ + u32 target_bar0; /* 0xb64 - Target Base Address 0 */ + u32 target_bar1; /* 0xb68 - Target Base Address 1 */ + u32 target_ctrl; /* 0xb6c - Target Control */ + u32 init_win0; /* 0xb70 - Initiator Window 0 Base/Translation */ + u32 init_win1; /* 0xb74 - Initiator Window 1 Base/Translation */ + u32 init_win2; /* 0xb78 - Initiator Window 2 Base/Translation */ + u32 reserved6; /* 0xb7c - reserved */ + u32 init_win_cfg; /* 0xb80 */ + u32 init_ctrl; /* 0xb84 */ + u32 init_stat; /* 0xb88 */ + u32 reserved7[27]; + u32 cfg_adr; /* 0xbf8 */ + u32 reserved8; +} mpc8220_xcpci_t; + +/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB, + reg1 - 1GB */ +#define PCI_BASE_ADDR_REG0 0x40000000 +#define PCI_BASE_ADDR_REG1 (CFG_SDRAM_BASE) +#define PCI_TARGET_BASE_ADDR_REG0 (CFG_MBAR) +#define PCI_TARGET_BASE_ADDR_REG1 (CFG_SDRAM_BASE) +#define PCI_TARGET_BASE_ADDR_EN 1<<0 + + +/* PCI Global Status/Control Register (PCIGSCR) */ +#define PCI_GLB_STAT_CTRL_PE_SHIFT 29 +#define PCI_GLB_STAT_CTRL_SE_SHIFT 28 +#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT 24 +#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK 0x7 +#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT 16 +#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK 0x7 +#define PCI_GLB_STAT_CTRL_PEE_SHIFT 13 +#define PCI_GLB_STAT_CTRL_SEE_SHIFT 12 +#define PCI_GLB_STAT_CTRL_PR_SHIFT 0 + +#define PCI_GLB_STAT_CTRL_PE (1< + +/* CPU Types */ +#define CPU_TYPE_601 0x01 /* PPC 601 CPU */ +#define CPU_TYPE_602 0x02 /* PPC 602 CPU */ +#define CPU_TYPE_603 0x03 /* PPC 603 CPU */ +#define CPU_TYPE_603E 0x06 /* PPC 603e CPU */ +#define CPU_TYPE_603P 0x07 /* PPC 603p CPU */ +#define CPU_TYPE_604 0x04 /* PPC 604 CPU */ +#define CPU_TYPE_604E 0x09 /* PPC 604e CPU */ +#define CPU_TYPE_604R 0x0a /* PPC 604r CPU */ +#define CPU_TYPE_750 0x08 /* PPC 750 CPU */ +#define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */ +#define CPU_TYPE_8245 0x8081 /* PPC 8245/8241 CPU */ +#define _CACHE_ALIGN_SIZE 32 /* cache line size */ + +/* spr976 - DMISS data tlb miss address register + * spr977 - DCMP data tlb miss compare register + * spr978 - HASH1 PTEG1 address register + * spr980 - HASH2 PTEG2 address register + * IMISS - instruction tlb miss address register + * ICMP - instruction TLB mis compare register + * RPA - real page address register + * HID0 - hardware implemntation register + * HID2 - instruction address breakpoint register + */ + +/* Kahlua/MPC8240 defines */ +#define VEN_DEV_ID 0x00021057 /* Vendor and Dev. ID for MPC106 */ +#define KAHLUA_ID 0x00031057 /* Vendor & Dev Id for Kahlua's PCI */ +#define KAHLUA2_ID 0x00061057 /* 8245 is aka Kahlua-2 */ +#define BMC_BASE 0x80000000 /* Kahlua ID in PCI Memory space */ +#define CHRP_REG_ADDR 0xfec00000 /* MPC107 Config, Map B */ +#define CHRP_REG_DATA 0xfee00000 /* MPC107 Config, Map B */ +#define CHRP_ISA_MEM_PHYS 0xfd000000 +#define CHRP_ISA_MEM_BUS 0x00000000 +#define CHRP_ISA_MEM_SIZE 0x01000000 +#define CHRP_ISA_IO_PHYS 0xfe000000 +#define CHRP_ISA_IO_BUS 0x00000000 +#define CHRP_ISA_IO_SIZE 0x00800000 +#define CHRP_PCI_IO_PHYS 0xfe800000 +#define CHRP_PCI_IO_BUS 0x00800000 +#define CHRP_PCI_IO_SIZE 0x00400000 +#define CHRP_PCI_MEM_PHYS 0x80000000 +#define CHRP_PCI_MEM_BUS 0x80000000 +#define CHRP_PCI_MEM_SIZE 0x7d000000 +#define CHRP_PCI_MEMORY_PHYS 0x00000000 +#define CHRP_PCI_MEMORY_BUS 0x00000000 +#define CHRP_PCI_MEMORY_SIZE 0x40000000 +#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ +#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ +#define PREP_ISA_IO_PHYS 0x80000000 +#define PREP_ISA_IO_BUS 0x00000000 +#define PREP_ISA_IO_SIZE 0x00800000 +#define PREP_PCI_IO_PHYS 0x81000000 +#define PREP_PCI_IO_BUS 0x01000000 +#define PREP_PCI_IO_SIZE 0x3e800000 +#define PREP_PCI_MEM_PHYS 0xc0000000 +#define PREP_PCI_MEM_BUS 0x00000000 +#define PREP_PCI_MEM_SIZE 0x3f000000 +#define PREP_PCI_MEMORY_PHYS 0x00000000 +#define PREP_PCI_MEMORY_BUS 0x80000000 +#define PREP_PCI_MEMORY_SIZE 0x80000000 +#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */ +#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ +#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */ +#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */ +#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */ +#define MEM_CONT2_ADR 0x800000f4 /* MPC107 Memory control config. 2 */ +#define MEM_CONT3_ADR 0x800000f8 /* MPC107 Memory control config. 3 */ +#define MEM_CONT4_ADR 0x800000fc /* MPC107 Memory control config. 4 */ +#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */ +#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */ +#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */ +#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ +#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ +#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */ +#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */ +#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */ +#define XMEM_END2_ADR 0x8000009c /* MPC107 Extended mem. end addrs-lo*/ +#define OUT_DRV_CONT 0x80000073 /* MPC107 Output Driver Control reg */ +#define MEM_EN_ADR 0x800000a0 /* Memory bank enable */ +#define PAGE_MODE 0x800000a3 /* MPC107 Page Mode Counter/Timer */ + +/*----------------------------------------------------------------------- + * Exception offsets (PowerPC standard) + */ +#define EXC_OFF_RESERVED0 0x0000 /* Reserved */ +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define EXC_OFF_MACH_CHCK 0x0200 /* Machine Check */ +#define EXC_OFF_DATA_STOR 0x0300 /* Data Storage */ +#define EXC_OFF_INS_STOR 0x0400 /* Instruction Storage */ +#define EXC_OFF_EXTERNAL 0x0500 /* External */ +#define EXC_OFF_ALIGN 0x0600 /* Alignment */ +#define EXC_OFF_PROGRAM 0x0700 /* Program */ +#define EXC_OFF_FPUNAVAIL 0x0800 /* Floating-point Unavailable */ +#define EXC_OFF_DECR 0x0900 /* Decrementer */ +#define EXC_OFF_RESERVED1 0x0A00 /* Reserved */ +#define EXC_OFF_RESERVED2 0x0B00 /* Reserved */ +#define EXC_OFF_SYS_CALL 0x0C00 /* System Call */ +#define EXC_OFF_TRACE 0x0D00 /* Trace */ +#define EXC_OFF_FPUNASSIST 0x0E00 /* Floating-point Assist */ + + /* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */ + /* these found in DINK code - may not apply to 8240*/ +#define EXC_OFF_PMI 0x0F00 /* Performance Monitoring Interrupt */ +#define EXC_OFF_VMXUI 0x0F20 /* VMX (AltiVec) Unavailable Interrupt */ + + /* 0x1000 - 0x2FFF are implementation specific */ + /* these found in DINK code - may not apply to 8240 */ +#define EXC_OFF_ITME 0x1000 /* Instruction Translation Miss Exception */ +#define EXC_OFF_DLTME 0x1100 /* Data Load Translation Miss Exception */ +#define EXC_OFF_DSTME 0x1200 /* Data Store Translation Miss Exception */ +#define EXC_OFF_IABE 0x1300 /* Instruction Addr Breakpoint Exception */ +#define EXC_OFF_SMIE 0x1400 /* System Management Interrupt Exception */ +#define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/ +#define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */ + +#define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */ +#define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */ +#define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */ +#define MAP_A_CONFIG_DATA_LOW 0x0CFC /* Lower half of CONFIG_DAT for Map A */ +#define MAP_B_CONFIG_ADDR_HIGH 0xfec0 /* Upper half of CONFIG_ADDR for Map B */ +#define MAP_B_CONFIG_ADDR_LOW 0x0000 /* Lower half of CONFIG_ADDR for Map B */ +#define MAP_B_CONFIG_DATA_HIGH 0xfee0 /* Upper half of CONFIG_DAT for Map B */ +#define MAP_B_CONFIG_DATA_LOW 0x0000 /* Lower half of CONFIG_DAT for Map B */ + + +#if defined(CFG_ADDR_MAP_A) +#define CONFIG_ADDR_HIGH MAP_A_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */ +#define CONFIG_ADDR_LOW MAP_A_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */ +#define CONFIG_DATA_HIGH MAP_A_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */ +#define CONFIG_DATA_LOW MAP_A_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */ +#else /* Assume Map B, default */ +#define CONFIG_ADDR_HIGH MAP_B_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */ +#define CONFIG_ADDR_LOW MAP_B_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */ +#define CONFIG_DATA_HIGH MAP_B_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */ +#define CONFIG_DATA_LOW MAP_B_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */ +#endif + +#define CONFIG_ADDR (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW) + +#define CONFIG_DATA (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW) + +/* Macros to write to config registers. addr should be a constant in all cases */ + +#define CONFIG_WRITE_BYTE( addr, data ) \ + __asm__ __volatile__( \ + " stwbrx %1, 0, %0\n \ + sync\n \ + stb %3, %4(%2)\n \ + sync " \ + : /* no output */ \ + : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ + "b" (CONFIG_DATA), "r" (data), \ + "n" ((addr) & 3)); + +#define CONFIG_WRITE_HALFWORD( addr, data ) \ + __asm__ __volatile__( \ + " stwbrx %1, 0, %0\n \ + sync\n \ + sthbrx %3, %4, %2\n \ + sync " \ + : /* no output */ \ + : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ + "r" (CONFIG_DATA), "r" (data), \ + "b" ((addr) & 3)); + +/* this assumes it's writeing on word boundaries*/ +#define CONFIG_WRITE_WORD( addr, data ) \ + __asm__ __volatile__( \ + " stwbrx %1, 0, %0\n \ + sync\n \ + stwbrx %3, 0, %2\n \ + sync " \ + : /* no output */ \ + : "r" (CONFIG_ADDR), "r" (addr), \ + "r" (CONFIG_DATA), "r" (data)); + +/* Configuration register reads*/ + +#define CONFIG_READ_BYTE( addr, reg ) \ + __asm__ ( \ + " stwbrx %1, 0, %2\n \ + sync\n \ + lbz %0, %4(%3)\n \ + sync " \ + : "=r" (reg) \ + : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ + "b" (CONFIG_DATA), "n" ((addr) & 3)); + + +#define CONFIG_READ_HALFWORD( addr, reg ) \ + __asm__ ( \ + " stwbrx %1, 0, %2\n \ + sync\n \ + lhbrx %0, %4, %3\n \ + sync " \ + : "=r" (reg) \ + : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ + "r" (CONFIG_DATA), \ + "b" ((addr) & 3)); + +/* this assumes it's reading on word boundaries*/ +#define CONFIG_READ_WORD( addr, reg ) \ + __asm__ ( \ + " stwbrx %1, 0, %2\n \ + sync\n \ + lwbrx %0, 0, %3\n \ + sync " \ + : "=r" (reg) \ + : "r" (addr), "r" (CONFIG_ADDR),\ + "r" (CONFIG_DATA)); + +/* + * configuration register 'addresses'. + * These are described in chaper 5 of the 8240 users manual. + * Where the register has an abreviation in the manual, this has + * been usaed here, otherwise a name in keeping with the norm has + * been invented. + * Note that some of these registers aren't documented in the manual. + */ + +#define PCICR 0x80000004 /* PCI Command Register */ +#define PCISR 0x80000006 /* PCI Status Register */ +#define REVID 0x80000008 /* CPU revision id */ +#define PIR 0x80000009 /* PCI Programming Interface Register */ +#define PBCCR 0x8000000b /* PCI Base Class Code Register */ +#define PCLSR 0x8000000c /* Processor Cache Line Size Register */ +#define PLTR 0x8000000d /* PCI Latancy Timer Register */ +#define PHTR 0x8000000e /* PCI Header Type Register */ +#define BISTCTRL 0x8000000f /* BIST Control */ +#define LMBAR 0x80000010 /* Local Base Addres Register */ +#define PCSRBAR 0x80000014 /* PCSR Base Address Register */ +#define ILR 0x8000003c /* PCI Interrupt Line Register */ +#define IPR 0x8000003d /* Interrupt Pin Register */ +#define MINGNT 0x8000003e /* MIN GNI */ +#define MAXLAT 0x8000003f /* MAX LAT */ +#define PCIACR 0x80000046 /* PCI Arbiter Control Register */ +#define PMCR1 0x80000070 /* Power management config. 1 */ +#define PMCR2 0x80000072 /* Power management config. 2 */ +#define ODCR 0x80000073 /* Output Driver Control Register */ +#define CLKDCR 0x80000074 /* CLK Driver Control Register */ +#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) +#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */ +#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */ +#endif +#define EUMBBAR 0x80000078 /* Embedded Utilities Memory Block Base Address Register */ +#define EUMBBAR_VAL 0x80500000 /* PCI Relocation offset for EUMB region */ +#define EUMBSIZE 0x00100000 /* Size of EUMB region */ + +#define MSAR1 0x80000080 /* Memory Starting Address Register 1 */ +#define MSAR2 0x80000084 /* Memory Starting Address Register 2 */ +#define EMSAR1 0x80000088 /* Extended Memory Starting Address Register 1*/ +#define EMSAR2 0x8000008c /* Extended Memory Starting Address Register 2*/ +#define MEAR1 0x80000090 /* Memory Ending Address Register 1 */ +#define MEAR2 0x80000094 /* Memory Ending Address Register 2 */ +#define EMEAR1 0x80000098 /* Extended Memory Ending Address Register 1 */ +#define EMEAR2 0x8000009c /* Extended Memory Ending Address Register 2 */ +#define MBER 0x800000a0 /* Memory bank Enable Register*/ +#define MPMR 0x800000a3 /* Memory Page Mode Register (stores PGMAX) */ +#define PICR1 0x800000a8 /* Processor Interface Configuration Register 1 */ +#define PICR2 0x800000ac /* Processor Interface Configuration Register 2 */ +#define ECCSBECR 0x800000b8 /* ECC Single-Bit Error Counter Register */ +#define ECCSBETR 0x800000b8 /* ECC Single-Bit Error Trigger Register */ +#define ERRENR1 0x800000c0 /* Error Enableing Register 1 */ +#define ERRENR2 0x800000c4 /* Error Enableing Register 2 */ +#define ERRDR1 0x800000c1 /* Error Detection Register 1 */ +#define IPBESR 0x800000c3 /* Internal Processor Error Status Register */ +#define ERRDR2 0x800000c5 /* Error Detection Register 2 */ +#define PBESR 0x800000c7 /* PCI Bus Error Status Register */ +#define PBEAR 0x800000c8 /* Processor/PCI Bus Error Status Register */ +#define AMBOR 0x800000e0 /* Address Map B Options Register */ +#define PCMBCR 0x800000e1 /* PCI/Memory Buffer Configuration */ +#define MCCR1 0x800000f0 /* Memory Control Configuration Register 1 */ +#define MCCR2 0x800000f4 /* Memory Control Configuration Register 2 */ +#define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */ +#define MCCR4 0x800000fc /* Memory Control Configuration Register 4 */ + +/* some values for some of the above */ + +#define PICR1_CF_APARK 0x00000008 +#define PICR1_LE_MODE 0x00000020 +#define PICR1_ST_GATH_EN 0x00000040 +#if defined(CONFIG_MPC8240) +#define PICR1_EN_PCS 0x00000080 /* according to dink code, sets the 8240 to handle pci config space */ +#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) +#define PICR1_NO_BUSW_CK 0x00000080 /* no bus width check for flash writes */ +#define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */ +#define ERCR1 0x800000d0 /* Extended ROM Configuration Register 1 */ +#define ERCR2 0x800000d4 /* Extended ROM Configuration Register 2 */ +#define ERCR3 0x800000d8 /* Extended ROM Configuration Register 3 */ +#define ERCR4 0x800000dc /* Extended ROM Configuration Register 4 */ +#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */ +#define MIOCR1_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */ +#define MIOCR1_SHIFT 2 +#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */ +#define MIOCR2_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */ +#define MIOCR2_SHIFT 3 +#define ODCR_ADR_X 0x80000070 /* Output Driver Control register */ +#define ODCR_SHIFT 3 +#define PMCR2_ADR 0x80000072 /* Power Mgmnt Cfg 2 register */ +#define PMCR2_ADR_X 0x80000070 +#define PMCR2_SHIFT 3 +#define PMCR1_ADR 0x80000070 /* Power Mgmnt Cfg 1 reister */ +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif +#define PICR1_CF_DPARK 0x00000200 +#define PICR1_MCP_EN 0x00000800 +#define PICR1_FLASH_WR_EN 0x00001000 +#ifdef CONFIG_MPC8240 +#define PICR1_ADDRESS_MAP 0x00010000 +#define PIRC1_MSK 0xff000000 +#endif +#define PICR1_PROC_TYPE_MSK 0x00060000 +#define PICR1_PROC_TYPE_603E 0x00040000 +#define PICR1_RCS0 0x00100000 + +#define PICR2_CF_SNOOP_WS_MASK 0x000c0000 +#define PICR2_CF_SNOOP_WS_0WS 0x00000000 +#define PICR2_CF_SNOOP_WS_1WS 0x00040000 +#define PICR2_CF_SNOOP_WS_2WS 0x00080000 +#define PICR2_CF_SNOOP_WS_3WS 0x000c0000 +#define PICR2_CF_APHASE_WS_MASK 0x0000000c +#define PICR2_CF_APHASE_WS_0WS 0x00000000 +#define PICR2_CF_APHASE_WS_1WS 0x00000004 +#define PICR2_CF_APHASE_WS_2WS 0x00000008 +#define PICR2_CF_APHASE_WS_3WS 0x0000000c + +#define MCCR1_ROMNAL_SHIFT 28 +#define MCCR1_ROMNAL_MSK 0xf0000000 +#define MCCR1_ROMFAL_SHIFT 23 +#define MCCR1_ROMFAL_MSK 0x0f800000 +#define MCCR1_DBUS_SIZE0 0x00400000 +#define MCCR1_BURST 0x00100000 +#define MCCR1_MEMGO 0x00080000 +#define MCCR1_SREN 0x00040000 +#if defined(CONFIG_MPC8240) +#define MCCR1_RAM_TYPE 0x00020000 +#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) +#define MCCR1_SDRAM_EN 0x00020000 +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif +#define MCCR1_PCKEN 0x00010000 +#define MCCR1_BANK1ROW_SHIFT 2 +#define MCCR1_BANK2ROW_SHIFT 4 +#define MCCR1_BANK3ROW_SHIFT 6 +#define MCCR1_BANK4ROW_SHIFT 8 +#define MCCR1_BANK5ROW_SHIFT 10 +#define MCCR1_BANK6ROW_SHIFT 12 +#define MCCR1_BANK7ROW_SHIFT 14 + +#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000 +#define MCCR2_TS_WAIT_TIMER_SHIFT 29 +#define MCCR2_ASRISE_MSK 0x1e000000 +#define MCCR2_ASRISE_SHIFT 25 +#define MCCR2_ASFALL_MSK 0x01e00000 +#define MCCR2_ASFALL_SHIFT 21 + +#define MCCR2_INLINE_PAR_NOT_ECC 0x00100000 +#define MCCR2_WRITE_PARITY_CHK 0x00080000 +#define MCCR2_INLFRD_PARECC_CHK_EN 0x00040000 +#ifdef CONFIG_MPC8240 +#define MCCR2_ECC_EN 0x00020000 +#define MCCR2_EDO 0x00010000 +#endif +#define MCCR2_REFINT_MSK 0x0000fffc +#define MCCR2_REFINT_SHIFT 2 +#define MCCR2_RSV_PG 0x00000002 +#define MCCR2_PMW_PAR 0x00000001 + +#define MCCR3_BSTOPRE2TO5_MSK 0xf0000000 /*BSTOPRE[2-5]*/ +#define MCCR3_BSTOPRE2TO5_SHIFT 28 +#define MCCR3_REFREC_MSK 0x0f000000 +#define MCCR3_REFREC_SHIFT 24 +#ifdef CONFIG_MPC8240 +#define MCCR3_RDLAT_MSK 0x00f00000 +#define MCCR3_RDLAT_SHIFT 20 +#define MCCR3_CPX 0x00010000 +#define MCCR3_RAS6P_MSK 0x00078000 +#define MCCR3_RAS6P_SHIFT 15 +#define MCCR3_CAS5_MSK 0x00007000 +#define MCCR3_CAS5_SHIFT 12 +#define MCCR3_CP4_MSK 0x00000e00 +#define MCCR3_CP4_SHIFT 9 +#define MCCR3_CAS3_MSK 0x000001c0 +#define MCCR3_CAS3_SHIFT 6 +#define MCCR3_RCD2_MSK 0x00000038 +#define MCCR3_RCD2_SHIFT 3 +#define MCCR3_RP1_MSK 0x00000007 +#define MCCR3_RP1_SHIFT 0 +#endif + +#define MCCR4_PRETOACT_MSK 0xf0000000 +#define MCCR4_PRETOACT_SHIFT 28 +#define MCCR4_ACTTOPRE_MSK 0x0f000000 +#define MCCR4_ACTTOPRE_SHIFT 24 +#define MCCR4_WMODE 0x00800000 +#define MCCR4_INLINE 0x00400000 +#if defined(CONFIG_MPC8240) +#define MCCR4_BIT21 0x00200000 /* this include cos DINK code sets it- unknown function*/ +#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) +#define MCCR4_EXTROM 0x00200000 /* enables Extended ROM space */ +#else +#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) +#endif +#define MCCR4_REGISTERED 0x00100000 +#define MCCR4_BSTOPRE0TO1_MSK 0x000c0000 /*BSTOPRE[0-1]*/ +#define MCCR4_BSTOPRE0TO1_SHIFT 18 +#define MCCR4_REGDIMM 0x00008000 +#define MCCR4_SDMODE_MSK 0x00007f00 +#define MCCR4_SDMODE_SHIFT 8 +#define MCCR4_ACTTORW_MSK 0x000000f0 +#define MCCR4_ACTTORW_SHIFT 4 +#define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[6-9]*/ +#define MCCR4_BSTOPRE6TO9_SHIFT 0 +#define MCCR4_DBUS_SIZE2_SHIFT 17 + +#define MICR_ADDR_MASK 0x0ff00000 +#define MICR_ADDR_SHIFT 20 +#define MICR_EADDR_MASK 0x30000000 +#define MICR_EADDR_SHIFT 28 + +#define BATU_BEPI_MSK 0xfffe0000 +#define BATU_BL_MSK 0x00001ffc + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 + +#define BATL_BRPN_MSK 0xfffe0000 +#define BATL_WIMG_MSK 0x00000078 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +/* + * I'd attempt to do defines for the PP bits, but it's use is a bit + * too complex, see the PowerPC Operating Environment Architecture + * section in the PowerPc arch book, chapter 4. + */ + +/*eumb and epic config*/ + +#define EPIC_FPR 0x00041000 +#define EPIC_GCR 0x00041020 +#define EPIC_EICR 0x00041030 +#define EPIC_EVI 0x00041080 +#define EPIC_PI 0x00041090 +#define EPIC_SVR 0x000410E0 +#define EPIC_TFRR 0x000410F0 + +/* + * Note the information for these is rather mangled in the 8240 manual. + * These are guesses. + */ + +#define EPIC_GTCCR0 0x00041100 +#define EPIC_GTCCR1 0x00041140 +#define EPIC_GTCCR2 0x00041180 +#define EPIC_GTCCR3 0x000411C0 +#define EPIC_GTBCR0 0x00041110 +#define EPIC_GTBCR1 0x00041150 +#define EPIC_GTBCR2 0x00041190 +#define EPIC_GTBCR3 0x000411D0 +#define EPIC_GTVPR0 0x00041120 +#define EPIC_GTVPR1 0x00041160 +#define EPIC_GTVPR2 0x000411a0 +#define EPIC_GTVPR3 0x000411e0 +#define EPIC_GTDR0 0x00041130 +#define EPIC_GTDR1 0x00041170 +#define EPIC_GTDR2 0x000411b0 +#define EPIC_GTDR3 0x000411f0 + +#define EPIC_IVPR0 0x00050200 +#define EPIC_IVPR1 0x00050220 +#define EPIC_IVPR2 0x00050240 +#define EPIC_IVPR3 0x00050260 +#define EPIC_IVPR4 0x00050280 + +#define EPIC_SVPR0 0x00050200 +#define EPIC_SVPR1 0x00050220 +#define EPIC_SVPR2 0x00050240 +#define EPIC_SVPR3 0x00050260 +#define EPIC_SVPR4 0x00050280 +#define EPIC_SVPR5 0x000502A0 +#define EPIC_SVPR6 0x000502C0 +#define EPIC_SVPR7 0x000502E0 +#define EPIC_SVPR8 0x00050300 +#define EPIC_SVPR9 0x00050320 +#define EPIC_SVPRa 0x00050340 +#define EPIC_SVPRb 0x00050360 +#define EPIC_SVPRc 0x00050380 +#define EPIC_SVPRd 0x000503A0 +#define EPIC_SVPRe 0x000503C0 +#define EPIC_SVPRf 0x000503E0 + +/* MPC8240 Byte Swap/PCI Support Macros */ +#define BYTE_SWAP_16_BIT(x) ( (((x) & 0x00ff) << 8) | ( (x) >> 8) ) +#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ + (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) +#define PCISWAP(x) LONGSWAP(x) + +#ifndef __ASSEMBLY__ + +/* + * MPC107 Support + * + */ +unsigned int mpc824x_mpc107_getreg(unsigned int regNum); +void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal); +void mpc824x_mpc107_write8(unsigned int address, unsigned char data); +void mpc824x_mpc107_write16(unsigned int address, unsigned short data); +void mpc824x_mpc107_write32(unsigned int address, unsigned int data); +unsigned char mpc824x_mpc107_read8(unsigned int address); +unsigned short mpc824x_mpc107_read16(unsigned int address); +unsigned int mpc824x_mpc107_read32(unsigned int address); +unsigned int mpc824x_eummbar_read(unsigned int regNum); +void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal); + +#ifdef CONFIG_PCI +struct pci_controller; +void pci_cpm824x_init(struct pci_controller* hose); +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __MPC824X_H__ */ diff --git a/include/mpc8260.h b/include/mpc8260.h new file mode 100644 index 0000000..ff52a7b --- /dev/null +++ b/include/mpc8260.h @@ -0,0 +1,913 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8260.h + * + * MPC8255 / MPC8260 specific definitions + */ + +#ifndef __MPC8260_H__ +#define __MPC8260_H__ + +#ifdef CONFIG_MPC8255 +#define CPU_ID_STR "MPC8255" +#endif +#ifndef CPU_ID_STR +#if defined(CONFIG_MPC8272_FAMILY) +#define CPU_ID_STR "MPC8272" +#else +#define CPU_ID_STR "MPC8260" +#endif +#endif /* !CPU_ID_STR */ + +/*----------------------------------------------------------------------- + * Exception offsets (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ + + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration Register 4-25 + */ +#define BCR_EBM 0x80000000 /* External Bus Mode */ +#define BCR_APD_MSK 0x70000000 /* Address Phase Delay Mask */ +#define BCR_L2C 0x08000000 /* Secondary Cache Controller */ +#define BCR_L2D_MSK 0x07000000 /* L2 Cache Hit Delay Mask */ +#define BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */ +#define BCR_EAV 0x00400000 /* Enable Address Visibility */ +#define BCR_ETM 0x00080000 /* Compatibility Mode Enable */ +#define BCR_LETM 0x00040000 /* LocalBus Compatibility Mode Enable*/ +#define BCR_EPAR 0x00020000 /* Even Parity */ +#define BCR_LEPAR 0x00010000 /* Local Bus Even Parity */ +#define BCR_NPQM0 0x00008000 /* Non PowerQUICC-II Master 0 */ +#define BCR_NPQM1 0x00004000 /* Non PowerQUICC-II Master 1 */ +#define BCR_NPQM2 0x00002000 /* Non PowerQUICC-II Master 2 */ +#define BCR_EXDD 0x00000400 /* External Master Delay Disable*/ +#define BCR_ISPS 0x00000010 /* Internal Space Port Size */ + +/*----------------------------------------------------------------------- + * PPC_ACR - 60x Bus Arbiter Configuration Register 4-28 + */ +#define PPC_ACR_DBGD 0x20 /* Data Bus Grant Delay */ +#define PPC_ACR_EARB 0x10 /* External Arbitration */ +#define PPC_ACR_PRKM_MSK 0x0f /* Parking Master */ + +#define PPC_ACR_PRKM_CPMH 0x00 /* CPM high request level */ +#define PPC_ACR_PRKM_CPMM 0x01 /* CPM middle request level */ +#define PPC_ACR_PRKM_CPML 0x02 /* CPM low request level */ +#define PPC_ACR_PRKM_CORE 0x06 /* Internal Core */ +#define PPC_ACR_PRKM_EXT1 0x07 /* External Master 1 */ +#define PPC_ACR_PRKM_EXT2 0x08 /* External Master 2 */ +#define PPC_ACR_PRKM_EXT3 0x09 /* External Master 3 */ + +/*----------------------------------------------------------------------- + * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers 4-28 + */ +#define PPC_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */ +#define PPC_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */ +#define PPC_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */ +#define PPC_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */ +#define PPC_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */ +#define PPC_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */ +#define PPC_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */ +#define PPC_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */ +#define PPC_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */ +#define PPC_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */ +#define PPC_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */ +#define PPC_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */ +#define PPC_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */ +#define PPC_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */ +#define PPC_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */ +#define PPC_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */ + +/*----------------------------------------------------------------------- + * LCL_ACR - Local Bus Arbiter Configuration Register 4-29 + */ +#define LCL_ACR_DBGD 0x20 /* Data Bus Grant Delay */ +#define LCL_ACR_PRKM_MSK 0x0f /* Parking Master */ + +#define LCL_ACR_PRKM_CPMH 0x00 /* CPM high request level */ +#define LCL_ACR_PRKM_CPMM 0x01 /* CPM middle request level */ +#define LCL_ACR_PRKM_CPML 0x02 /* CPM low request level */ +#define LCL_ACR_PRKM_HOST 0x03 /* Host Bridge */ + +/*----------------------------------------------------------------------- + * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers 4-30 + */ +#define LCL_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */ +#define LCL_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */ +#define LCL_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */ +#define LCL_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */ +#define LCL_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */ +#define LCL_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */ +#define LCL_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */ +#define LCL_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */ +#define LCL_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */ +#define LCL_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */ +#define LCL_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */ +#define LCL_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */ +#define LCL_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */ +#define LCL_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */ +#define LCL_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */ +#define LCL_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration Register 4-31 + */ +#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ +#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ +#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ +#define SIUMCR_CDIS 0x10000000 /* Core Disable */ +#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ +#define SIUMCR_DPPC01 0x04000000 /* - " - */ +#define SIUMCR_DPPC10 0x08000000 /* - " - */ +#define SIUMCR_DPPC11 0x0c000000 /* - " - */ +#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ +#define SIUMCR_L2CPC01 0x01000000 /* - " - */ +#define SIUMCR_L2CPC10 0x02000000 /* - " - */ +#define SIUMCR_L2CPC11 0x03000000 /* - " - */ +#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ +#define SIUMCR_LBPC01 0x00400000 /* - " - */ +#define SIUMCR_LBPC10 0x00800000 /* - " - */ +#define SIUMCR_LBPC11 0x00c00000 /* - " - */ +#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ +#define SIUMCR_APPC01 0x00100000 /* - " - */ +#define SIUMCR_APPC10 0x00200000 /* - " - */ +#define SIUMCR_APPC11 0x00300000 /* - " - */ +#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ +#define SIUMCR_CS10PC01 0x00040000 /* - " - */ +#define SIUMCR_CS10PC10 0x00080000 /* - " - */ +#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ +#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ +#define SIUMCR_BCTLC01 0x00010000 /* - " - */ +#define SIUMCR_BCTLC10 0x00020000 /* - " - */ +#define SIUMCR_BCTLC11 0x00030000 /* - " - */ +#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ +#define SIUMCR_MMR01 0x00004000 /* - " - */ +#define SIUMCR_MMR10 0x00008000 /* - " - */ +#define SIUMCR_MMR11 0x0000c000 /* - " - */ +#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ + +/*----------------------------------------------------------------------- + * IMMR - Internal Memory Map Register 4-34 + */ +#define IMMR_ISB_MSK 0xfffe0000 /* Internal Space base */ +#define IMMR_PARTNUM_MSK 0x0000ff00 /* Part number */ +#define IMMR_MASKNUM_MSK 0x000000ff /* Mask number */ + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control Register 4-35 + */ +#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count*/ +#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */ +#define SYPCR_PBME 0x00000080 /* 60x Bus Monitor Enable */ +#define SYPCR_LBME 0x00000040 /* Local Bus Monitor Enable */ +#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ +#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select*/ +#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control Register 4-40 + */ +#define TMCNTSC_SEC 0x0080 /* Once Per Second Interrupt */ +#define TMCNTSC_ALR 0x0040 /* Alarm Interrupt */ +#define TMCNTSC_SIE 0x0008 /* Second Interrupt Enable */ +#define TMCNTSC_ALE 0x0004 /* Alarm Interrupt Enable */ +#define TMCNTSC_TCF 0x0002 /* Time Counter Frequency */ +#define TMCNTSC_TCE 0x0001 /* Time Counter Enable */ + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control Register 4-42 + */ +#if 0 /* already defined in asm/immap_8260.h */ +#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ +#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */ +#define PISCR_PTF 0x0002 /* Periodic Timer Frequency */ +#define PISCR_PTE 0x0001 /* Periodic Timer Enable */ +#endif + +/*----------------------------------------------------------------------- + * RSR - Reset Status Register 5-4 + */ +#define RSR_JTRS 0x00000020 /* JTAG Reset Status */ +#define RSR_CSRS 0x00000010 /* Check Stop Reset Status */ +#define RSR_SWRS 0x00000008 /* Software Watchdog Reset Status*/ +#define RSR_BMRS 0x00000004 /* Bus Monitor Reset Status */ +#define RSR_ESRS 0x00000002 /* External Soft Reset Status */ +#define RSR_EHRS 0x00000001 /* External Hard Reset Status */ + +#define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS) + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + */ +#define RMR_CSRE 0x00000001 /* Checkstop Reset Enable */ + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Word 5-8 + */ +#define HRCW_EARB 0x80000000 /* External Arbitration */ +#define HRCW_EXMC 0x40000000 /* External Memory Controller */ +#define HRCW_CDIS 0x20000000 /* Core Disable */ +#define HRCW_EBM 0x10000000 /* External Bus Mode */ +#define HRCW_BPS00 0x00000000 /* Boot Port Size */ +#define HRCW_BPS01 0x04000000 /* - " - */ +#define HRCW_BPS10 0x08000000 /* - " - */ +#define HRCW_BPS11 0x0c000000 /* - " - */ +#define HRCW_CIP 0x02000000 /* Core Initial Prefix */ +#define HRCW_ISPS 0x01000000 /* Internal Space Port Size */ +#define HRCW_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ +#define HRCW_L2CPC01 0x00400000 /* - " - */ +#define HRCW_L2CPC10 0x00800000 /* - " - */ +#define HRCW_L2CPC11 0x00c00000 /* - " - */ +#define HRCW_DPPC00 0x00000000 /* Data Parity Pin Configuration*/ +#define HRCW_DPPC01 0x00100000 /* - " - */ +#define HRCW_DPPC10 0x00200000 /* - " - */ +#define HRCW_DPPC11 0x00300000 /* - " - */ +#define HRCW_reserved1 0x00080000 /* reserved */ +#define HRCW_ISB000 0x00000000 /* Initial Internal Space Base */ +#define HRCW_ISB001 0x00010000 /* - " - */ +#define HRCW_ISB010 0x00020000 /* - " - */ +#define HRCW_ISB011 0x00030000 /* - " - */ +#define HRCW_ISB100 0x00040000 /* - " - */ +#define HRCW_ISB101 0x00050000 /* - " - */ +#define HRCW_ISB110 0x00060000 /* - " - */ +#define HRCW_ISB111 0x00070000 /* - " - */ +#define HRCW_BMS 0x00008000 /* Boot Memory Space */ +#define HRCW_BBD 0x00004000 /* Bus Busy Disable */ +#define HRCW_MMR00 0x00000000 /* Mask Masters Requests */ +#define HRCW_MMR01 0x00001000 /* - " - */ +#define HRCW_MMR10 0x00002000 /* - " - */ +#define HRCW_MMR11 0x00003000 /* - " - */ +#define HRCW_LBPC00 0x00000000 /* Local Bus Pin Configuration */ +#define HRCW_LBPC01 0x00000400 /* - " - */ +#define HRCW_LBPC10 0x00000800 /* - " - */ +#define HRCW_LBPC11 0x00000c00 /* - " - */ +#define HRCW_APPC00 0x00000000 /* Address Parity Pin Configuration*/ +#define HRCW_APPC01 0x00000100 /* - " - */ +#define HRCW_APPC10 0x00000200 /* - " - */ +#define HRCW_APPC11 0x00000300 /* - " - */ +#define HRCW_CS10PC00 0x00000000 /* CS10 Pin Configuration */ +#define HRCW_CS10PC01 0x00000040 /* - " - */ +#define HRCW_CS10PC10 0x00000080 /* - " - */ +#define HRCW_CS10PC11 0x000000c0 /* - " - */ +#define HRCW_MODCK_H0000 0x00000000 /* High-order bits of MODCK Bus */ +#define HRCW_MODCK_H0001 0x00000001 /* - " - */ +#define HRCW_MODCK_H0010 0x00000002 /* - " - */ +#define HRCW_MODCK_H0011 0x00000003 /* - " - */ +#define HRCW_MODCK_H0100 0x00000004 /* - " - */ +#define HRCW_MODCK_H0101 0x00000005 /* - " - */ +#define HRCW_MODCK_H0110 0x00000006 /* - " - */ +#define HRCW_MODCK_H0111 0x00000007 /* - " - */ +#define HRCW_MODCK_H1000 0x00000008 /* - " - */ +#define HRCW_MODCK_H1001 0x00000009 /* - " - */ +#define HRCW_MODCK_H1010 0x0000000a /* - " - */ +#define HRCW_MODCK_H1011 0x0000000b /* - " - */ +#define HRCW_MODCK_H1100 0x0000000c /* - " - */ +#define HRCW_MODCK_H1101 0x0000000d /* - " - */ +#define HRCW_MODCK_H1110 0x0000000e /* - " - */ +#define HRCW_MODCK_H1111 0x0000000f /* - " - */ + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control Register 9-8 + */ +#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ +#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ +#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ +#define SCCR_PCIDF_SHIFT 3 +#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ +#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ +#define SCCR_DFBRG_SHIFT 0 + +#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ +#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ +#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ +#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 128 */ + +/*----------------------------------------------------------------------- + * SCMR - System Clock Mode Register 9-9 + */ +#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */ +#define SCMR_CORECNF_SHIFT 24 +#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */ +#define SCMR_BUSDF_SHIFT 20 +#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */ +#define SCMR_CPMDF_SHIFT 16 +#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */ +#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/ +#define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */ +#define SCMR_PLLMF_SHIFT 0 + + +/*----------------------------------------------------------------------- + * MxMR - Machine A/B/C Mode Registers 10-13 + */ +#define MxMR_BSEL 0x80000000 /* Bus Select */ +#define MxMR_RFEN 0x40000000 /* Refresh Enable */ +#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */ +#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */ +#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */ +#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */ +#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */ +#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */ +#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */ +#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */ +#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */ + +#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ +#define MxMR_OP_WARR 0x10000000 /* Write to Array */ +#define MxMR_OP_RARR 0x20000000 /* Read from Array */ +#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */ + +#define MxMR_AMx_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ +#define MxMR_AMx_TYPE_1 0x01000000 /* Addess Multiplexing Type 1 */ +#define MxMR_AMx_TYPE_2 0x02000000 /* Addess Multiplexing Type 2 */ +#define MxMR_AMx_TYPE_3 0x03000000 /* Addess Multiplexing Type 3 */ +#define MxMR_AMx_TYPE_4 0x04000000 /* Addess Multiplexing Type 4 */ +#define MxMR_AMx_TYPE_5 0x05000000 /* Addess Multiplexing Type 5 */ + +#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */ +#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ +#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ +#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */ + +#define MxMR_G0CLx_A12 0x00000000 /* General Line 0 : A12 */ +#define MxMR_G0CLx_A11 0x00080000 /* General Line 0 : A11 */ +#define MxMR_G0CLx_A10 0x00100000 /* General Line 0 : A10 */ +#define MxMR_G0CLx_A9 0x00180000 /* General Line 0 : A9 */ +#define MxMR_G0CLx_A8 0x00200000 /* General Line 0 : A8 */ +#define MxMR_G0CLx_A7 0x00280000 /* General Line 0 : A7 */ +#define MxMR_G0CLx_A6 0x00300000 /* General Line 0 : A6 */ +#define MxMR_G0CLx_A5 0x00380000 /* General Line 0 : A5 */ + +#define MxMR_RLFx_1X 0x00004000 /* Read Loop is executed 1 time */ +#define MxMR_RLFx_2X 0x00008000 /* Read Loop is executed 2 times*/ +#define MxMR_RLFx_3X 0x0000c000 /* Read Loop is executed 3 times*/ +#define MxMR_RLFx_4X 0x00010000 /* Read Loop is executed 4 times*/ +#define MxMR_RLFx_5X 0x00014000 /* Read Loop is executed 5 times*/ +#define MxMR_RLFx_6X 0x00018000 /* Read Loop is executed 6 times*/ +#define MxMR_RLFx_7X 0x0001c000 /* Read Loop is executed 7 times*/ +#define MxMR_RLFx_8X 0x00020000 /* Read Loop is executed 8 times*/ +#define MxMR_RLFx_9X 0x00024000 /* Read Loop is executed 9 times*/ +#define MxMR_RLFx_10X 0x00028000 /* Read Loop is executed 10 times*/ +#define MxMR_RLFx_11X 0x0002c000 /* Read Loop is executed 11 times*/ +#define MxMR_RLFx_12X 0x00030000 /* Read Loop is executed 12 times*/ +#define MxMR_RLFx_13X 0x00034000 /* Read Loop is executed 13 times*/ +#define MxMR_RLFx_14X 0x00038000 /* Read Loop is executed 14 times*/ +#define MxMR_RLFx_15X 0x0003c000 /* Read Loop is executed 15 times*/ +#define MxMR_RLFx_16X 0x00000000 /* Read Loop is executed 16 times*/ + +#define MxMR_WLFx_1X 0x00000400 /* Write Loop is executed 1 time*/ +#define MxMR_WLFx_2X 0x00000800 /* Write Loop is executed 2 times*/ +#define MxMR_WLFx_3X 0x00000c00 /* Write Loop is executed 3 times*/ +#define MxMR_WLFx_4X 0x00001000 /* Write Loop is executed 4 times*/ +#define MxMR_WLFx_5X 0x00001400 /* Write Loop is executed 5 times*/ +#define MxMR_WLFx_6X 0x00001800 /* Write Loop is executed 6 times*/ +#define MxMR_WLFx_7X 0x00001c00 /* Write Loop is executed 7 times*/ +#define MxMR_WLFx_8X 0x00002000 /* Write Loop is executed 8 times*/ +#define MxMR_WLFx_9X 0x00002400 /* Write Loop is executed 9 times*/ +#define MxMR_WLFx_10X 0x00002800 /* Write Loop is executed 10 times*/ +#define MxMR_WLFx_11X 0x00002c00 /* Write Loop is executed 11 times*/ +#define MxMR_WLFx_12X 0x00003000 /* Write Loop is executed 12 times*/ +#define MxMR_WLFx_13X 0x00003400 /* Write Loop is executed 13 times*/ +#define MxMR_WLFx_14X 0x00003800 /* Write Loop is executed 14 times*/ +#define MxMR_WLFx_15X 0x00003c00 /* Write Loop is executed 15 times*/ +#define MxMR_WLFx_16X 0x00000000 /* Write Loop is executed 16 times*/ + +#define MxMR_TLFx_1X 0x00000040 /* Timer Loop is executed 1 time*/ +#define MxMR_TLFx_2X 0x00000080 /* Timer Loop is executed 2 times*/ +#define MxMR_TLFx_3X 0x000000c0 /* Timer Loop is executed 3 times*/ +#define MxMR_TLFx_4X 0x00000100 /* Timer Loop is executed 4 times*/ +#define MxMR_TLFx_5X 0x00000140 /* Timer Loop is executed 5 times*/ +#define MxMR_TLFx_6X 0x00000180 /* Timer Loop is executed 6 times*/ +#define MxMR_TLFx_7X 0x000001c0 /* Timer Loop is executed 7 times*/ +#define MxMR_TLFx_8X 0x00000200 /* Timer Loop is executed 8 times*/ +#define MxMR_TLFx_9X 0x00000240 /* Timer Loop is executed 9 times*/ +#define MxMR_TLFx_10X 0x00000280 /* Timer Loop is executed 10 times*/ +#define MxMR_TLFx_11X 0x000002c0 /* Timer Loop is executed 11 times*/ +#define MxMR_TLFx_12X 0x00000300 /* Timer Loop is executed 12 times*/ +#define MxMR_TLFx_13X 0x00000340 /* Timer Loop is executed 13 times*/ +#define MxMR_TLFx_14X 0x00000380 /* Timer Loop is executed 14 times*/ +#define MxMR_TLFx_15X 0x000003c0 /* Timer Loop is executed 15 times*/ +#define MxMR_TLFx_16X 0x00000000 /* Timer Loop is executed 16 times*/ + + +/*----------------------------------------------------------------------- + * BRx - Memory Controller: Base Register 10-14 + */ +#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */ +#define BRx_PS_MSK 0x00001800 /* Port Size Mask */ +#define BRx_DECC_MSK 0x00000600 /* Data Error Correct+Check Mask*/ +#define BRx_WP 0x00000100 /* Write Protect */ +#define BRx_MS_MSK 0x000000e0 /* Machine Select Mask */ +#define BRx_EMEMC 0x00000010 /* External MEMC Enable */ +#define BRx_ATOM_MSK 0x0000000c /* Atomic Operation Mask */ +#define BRx_DR 0x00000002 /* Data Pipelining */ +#define BRx_V 0x00000001 /* Bank Valid */ + +#define BRx_PS_64 0x00000000 /* 64 bit port size (60x bus only)*/ +#define BRx_PS_8 0x00000800 /* 8 bit port size */ +#define BRx_PS_16 0x00001000 /* 16 bit port size */ +#define BRx_PS_32 0x00001800 /* 32 bit port size */ + +#define BRx_DECC_NONE 0x00000000 /* Data Errors Checking Disabled*/ +#define BRx_DECC_NORMAL 0x00000200 /* Normal Parity Checking */ +#define BRx_DECC_RMWPC 0x00000400 /* Read-Modify-Write Parity Checking*/ +#define BRx_DECC_ECC 0x00000600 /* ECC Correction and Checking */ + +#define BRx_MS_GPCM_P 0x00000000 /* G.P.C.M. 60x Bus Machine Select*/ +#define BRx_MS_GPCM_L 0x00000020 /* G.P.C.M. Local Bus Machine Select*/ +#define BRx_MS_SDRAM_P 0x00000040 /* SDRAM 60x Bus Machine Select */ +#define BRx_MS_SDRAM_L 0x00000060 /* SDRAM Local Bus Machine Select*/ +#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ +#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */ +#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */ + +#define BRx_ATOM_RAWA 0x00000004 /* Read-After-Write-Atomic */ +#define BRx_ATOM_WARA 0x00000008 /* Write-After-Read-Atomic */ + +/*----------------------------------------------------------------------- + * ORx - Memory Controller: Option Register - SDRAM Mode 10-16 + */ +#define ORxS_SDAM_MSK 0xfff00000 /* SDRAM Address Mask Mask */ +#define ORxS_LSDAM_MSK 0x000f8000 /* Lower SDRAM Address Mask Mask*/ +#define ORxS_BPD_MSK 0x00006000 /* Banks Per Device Mask */ +#define ORxS_ROWST_MSK 0x00001e00 /* Row Start Address Bit Mask */ +#define ORxS_NUMR_MSK 0x000001c0 /* Number of Row Addr Lines Mask*/ +#define ORxS_PMSEL 0x00000020 /* Page Mode Select */ +#define ORxS_IBID 0x00000010 /* Internal Bank Interleaving Disable*/ + +#define ORxS_BPD_2 0x00000000 /* 2 Banks Per Device */ +#define ORxS_BPD_4 0x00002000 /* 4 Banks Per Device */ +#define ORxS_BPD_8 0x00004000 /* 8 Banks Per Device */ + +/* ROWST values for xSDMR[PBI] = 0 */ +#define ORxS_ROWST_PBI0_A7 0x00000400 /* Row Start Address Bit is A7 */ +#define ORxS_ROWST_PBI0_A8 0x00000800 /* Row Start Address Bit is A8 */ +#define ORxS_ROWST_PBI0_A9 0x00000c00 /* Row Start Address Bit is A9 */ +#define ORxS_ROWST_PBI0_A10 0x00001000 /* Row Start Address Bit is A10 */ +#define ORxS_ROWST_PBI0_A11 0x00001400 /* Row Start Address Bit is A11 */ +#define ORxS_ROWST_PBI0_A12 0x00001800 /* Row Start Address Bit is A12 */ +#define ORxS_ROWST_PBI0_A13 0x00001c00 /* Row Start Address Bit is A13 */ + +/* ROWST values for xSDMR[PBI] = 1 */ +#define ORxS_ROWST_PBI1_A0 0x00000000 /* Row Start Address Bit is A0 */ +#define ORxS_ROWST_PBI1_A1 0x00000200 /* Row Start Address Bit is A1 */ +#define ORxS_ROWST_PBI1_A2 0x00000400 /* Row Start Address Bit is A2 */ +#define ORxS_ROWST_PBI1_A3 0x00000600 /* Row Start Address Bit is A3 */ +#define ORxS_ROWST_PBI1_A4 0x00000800 /* Row Start Address Bit is A4 */ +#define ORxS_ROWST_PBI1_A5 0x00000a00 /* Row Start Address Bit is A5 */ +#define ORxS_ROWST_PBI1_A6 0x00000c00 /* Row Start Address Bit is A6 */ +#define ORxS_ROWST_PBI1_A7 0x00000e00 /* Row Start Address Bit is A7 */ +#define ORxS_ROWST_PBI1_A8 0x00001000 /* Row Start Address Bit is A8 */ +#define ORxS_ROWST_PBI1_A9 0x00001200 /* Row Start Address Bit is A9 */ +#define ORxS_ROWST_PBI1_A10 0x00001400 /* Row Start Address Bit is A10 */ +#define ORxS_ROWST_PBI1_A11 0x00001600 /* Row Start Address Bit is A11 */ +#define ORxS_ROWST_PBI1_A12 0x00001800 /* Row Start Address Bit is A12 */ + +#define ORxS_NUMR_9 0x00000000 /* 9 Row Address Lines */ +#define ORxS_NUMR_10 0x00000040 /* 10 Row Address Lines */ +#define ORxS_NUMR_11 0x00000080 /* 11 Row Address Lines */ +#define ORxS_NUMR_12 0x000000c0 /* 12 Row Address Lines */ +#define ORxS_NUMR_13 0x00000100 /* 13 Row Address Lines */ +#define ORxS_NUMR_14 0x00000140 /* 14 Row Address Lines */ +#define ORxS_NUMR_15 0x00000180 /* 15 Row Address Lines */ +#define ORxS_NUMR_16 0x000001c0 /* 16 Row Address Lines */ + +/* helper to determine the AM for a given size (SDRAM mode) */ +#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ + +/*----------------------------------------------------------------------- + * ORx - Memory Controller: Option Register - GPCM Mode 10-18 + */ +#define ORxG_AM_MSK 0xffff8000 /* Address Mask Mask */ +#define ORxG_BCTLD 0x00001000 /* Data Buffer Control Disable */ +#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ +#define ORxG_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask*/ +#define ORxG_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ +#define ORxG_SETA 0x00000008 /* External Access Termination */ +#define ORxG_TRLX 0x00000004 /* Timing Relaxed */ +#define ORxG_EHTR 0x00000002 /* Extended Hold Time on Read */ + +#define ORxG_ACS_DIV1 0x00000000 /* CS is output at the same time*/ +#define ORxG_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later*/ +#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ + +#define ORxG_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ +#define ORxG_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ +#define ORxG_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ +#define ORxG_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ +#define ORxG_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ +#define ORxG_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ +#define ORxG_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ +#define ORxG_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ +#define ORxG_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ +#define ORxG_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ +#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ +#define ORxG_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ +#define ORxG_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ +#define ORxG_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ +#define ORxG_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ +#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ + +/*----------------------------------------------------------------------- + * ORx - Memory Controller: Option Register - UPM Mode 10-20 + */ +#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */ +#define ORxU_BCTLD 0x00001000 /* Data Buffer Control Disable */ +#define ORxU_BI 0x00000100 /* Burst Inhibit */ +#define ORxU_EHTR_MSK 0x00000006 /* Extended Hold Time on Read Mask*/ + +#define ORxU_EHTR_NORM 0x00000000 /* Normal Timing */ +#define ORxU_EHTR_1IDLE 0x00000002 /* One Idle Clock Cycle Inserted*/ +#define ORxU_EHTR_4IDLE 0x00000004 /* Four Idle Clock Cycles Inserted*/ +#define ORxU_EHTR_8IDLE 0x00000006 /* Eight Idle Clock Cycles Inserted*/ + + +/* helpers to convert values into an OR address mask (GPCM mode) */ +#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ +#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) + + +/*----------------------------------------------------------------------- + * PSDMR - 60x SDRAM Mode Register 10-21 + */ +#define PSDMR_PBI 0x80000000 /* Page-based Interleaving */ +#define PSDMR_RFEN 0x40000000 /* Refresh Enable */ +#define PSDMR_OP_MSK 0x38000000 /* SDRAM Operation Mask */ +#define PSDMR_SDAM_MSK 0x07000000 /* SDRAM Address Multiplex Mask */ +#define PSDMR_BSMA_MSK 0x00e00000 /* Bank Select Muxd Addr Line Mask*/ +#define PSDMR_SDA10_MSK 0x001c0000 /* A10 Control Mask */ +#define PSDMR_RFRC_MSK 0x00038000 /* Refresh Recovery Mask */ +#define PSDMR_PRETOACT_MSK 0x00007000 /* Precharge to Activate Intvl Mask*/ +#define PSDMR_ACTTORW_MSK 0x00000e00 /* Activate to Read/Write Intvl Mask*/ +#define PSDMR_BL 0x00000100 /* Burst Length */ +#define PSDMR_LDOTOPRE_MSK 0x000000c0 /* Last Data Out to Precharge Mask*/ +#define PSDMR_WRC_MSK 0x00000030 /* Write Recovery Time Mask */ +#define PSDMR_EAMUX 0x00000008 /* External Address Multiplexing*/ +#define PSDMR_BUFCMD 0x00000004 /* SDRAM ctl lines asrtd for 2 cycles*/ +#define PSDMR_CL_MSK 0x00000003 /* CAS Latency Mask */ + +#define PSDMR_OP_NORM 0x00000000 /* Normal Operation */ +#define PSDMR_OP_CBRR 0x08000000 /* CBR Refresh */ +#define PSDMR_OP_SELFR 0x10000000 /* Self Refresh */ +#define PSDMR_OP_MRW 0x18000000 /* Mode Register Write */ +#define PSDMR_OP_PREB 0x20000000 /* Precharge Bank */ +#define PSDMR_OP_PREA 0x28000000 /* Precharge All Banks */ +#define PSDMR_OP_ACTB 0x30000000 /* Activate Bank */ +#define PSDMR_OP_RW 0x38000000 /* Read/Write */ + +#define PSDMR_SDAM_A13_IS_A5 0x00000000 /* SDRAM Address Multiplex A13 is A5 */ +#define PSDMR_SDAM_A14_IS_A5 0x01000000 /* SDRAM Address Multiplex A14 is A5 */ +#define PSDMR_SDAM_A15_IS_A5 0x02000000 /* SDRAM Address Multiplex A15 is A5 */ +#define PSDMR_SDAM_A16_IS_A5 0x03000000 /* SDRAM Address Multiplex A16 is A5 */ +#define PSDMR_SDAM_A17_IS_A5 0x04000000 /* SDRAM Address Multiplex A17 is A5 */ +#define PSDMR_SDAM_A18_IS_A5 0x05000000 /* SDRAM Address Multiplex A18 is A5 */ + +#define PSDMR_BSMA_A12_A14 0x00000000 /* A12 - A14 */ +#define PSDMR_BSMA_A13_A15 0x00200000 /* A13 - A15 */ +#define PSDMR_BSMA_A14_A16 0x00400000 /* A14 - A16 */ +#define PSDMR_BSMA_A15_A17 0x00600000 /* A15 - A17 */ +#define PSDMR_BSMA_A16_A18 0x00800000 /* A16 - A18 */ +#define PSDMR_BSMA_A17_A19 0x00a00000 /* A17 - A19 */ +#define PSDMR_BSMA_A18_A20 0x00c00000 /* A18 - A20 */ +#define PSDMR_BSMA_A19_A21 0x00e00000 /* A19 - A21 */ + +/* SDA10 values for xSDMR[PBI] = 0 */ +#define PSDMR_SDA10_PBI0_A12 0x00000000 /* "A10" Control is A12 */ +#define PSDMR_SDA10_PBI0_A11 0x00040000 /* "A10" Control is A11 */ +#define PSDMR_SDA10_PBI0_A10 0x00080000 /* "A10" Control is A10 */ +#define PSDMR_SDA10_PBI0_A9 0x000c0000 /* "A10" Control is A9 */ +#define PSDMR_SDA10_PBI0_A8 0x00100000 /* "A10" Control is A8 */ +#define PSDMR_SDA10_PBI0_A7 0x00140000 /* "A10" Control is A7 */ +#define PSDMR_SDA10_PBI0_A6 0x00180000 /* "A10" Control is A6 */ +#define PSDMR_SDA10_PBI0_A5 0x001c0000 /* "A10" Control is A5 */ + +/* SDA10 values for xSDMR[PBI] = 1 */ +#define PSDMR_SDA10_PBI1_A10 0x00000000 /* "A10" Control is A10 */ +#define PSDMR_SDA10_PBI1_A9 0x00040000 /* "A10" Control is A9 */ +#define PSDMR_SDA10_PBI1_A8 0x00080000 /* "A10" Control is A8 */ +#define PSDMR_SDA10_PBI1_A7 0x000c0000 /* "A10" Control is A7 */ +#define PSDMR_SDA10_PBI1_A6 0x00100000 /* "A10" Control is A6 */ +#define PSDMR_SDA10_PBI1_A5 0x00140000 /* "A10" Control is A5 */ +#define PSDMR_SDA10_PBI1_A4 0x00180000 /* "A10" Control is A4 */ +#define PSDMR_SDA10_PBI1_A3 0x001c0000 /* "A10" Control is A3 */ + +#define PSDMR_RFRC_3_CLK 0x00008000 /* 3 Clocks */ +#define PSDMR_RFRC_4_CLK 0x00010000 /* 4 Clocks */ +#define PSDMR_RFRC_5_CLK 0x00018000 /* 5 Clocks */ +#define PSDMR_RFRC_6_CLK 0x00020000 /* 6 Clocks */ +#define PSDMR_RFRC_7_CLK 0x00028000 /* 7 Clocks */ +#define PSDMR_RFRC_8_CLK 0x00030000 /* 8 Clocks */ +#define PSDMR_RFRC_16_CLK 0x00038000 /* 16 Clocks */ + +#define PSDMR_PRETOACT_8W 0x00000000 /* 8 Clock-cycle Wait States */ +#define PSDMR_PRETOACT_1W 0x00001000 /* 1 Clock-cycle Wait States */ +#define PSDMR_PRETOACT_2W 0x00002000 /* 2 Clock-cycle Wait States */ +#define PSDMR_PRETOACT_3W 0x00003000 /* 3 Clock-cycle Wait States */ +#define PSDMR_PRETOACT_4W 0x00004000 /* 4 Clock-cycle Wait States */ +#define PSDMR_PRETOACT_5W 0x00005000 /* 5 Clock-cycle Wait States */ +#define PSDMR_PRETOACT_6W 0x00006000 /* 6 Clock-cycle Wait States */ +#define PSDMR_PRETOACT_7W 0x00007000 /* 7 Clock-cycle Wait States */ + +#define PSDMR_ACTTORW_8W 0x00000000 /* 8 Clock-cycle Wait States */ +#define PSDMR_ACTTORW_1W 0x00000200 /* 1 Clock-cycle Wait States */ +#define PSDMR_ACTTORW_2W 0x00000400 /* 2 Clock-cycle Wait States */ +#define PSDMR_ACTTORW_3W 0x00000600 /* 3 Clock-cycle Wait States */ +#define PSDMR_ACTTORW_4W 0x00000800 /* 4 Clock-cycle Wait States */ +#define PSDMR_ACTTORW_5W 0x00000a00 /* 5 Clock-cycle Wait States */ +#define PSDMR_ACTTORW_6W 0x00000c00 /* 6 Clock-cycle Wait States */ +#define PSDMR_ACTTORW_7W 0x00000e00 /* 7 Clock-cycle Wait States */ + +#define PSDMR_LDOTOPRE_0C 0x00000000 /* 0 Clock Cycles */ +#define PSDMR_LDOTOPRE_1C 0x00000040 /* 1 Clock Cycles */ +#define PSDMR_LDOTOPRE_2C 0x00000080 /* 2 Clock Cycles */ + +#define PSDMR_WRC_4C 0x00000000 /* 4 Clock Cycles */ +#define PSDMR_WRC_1C 0x00000010 /* 1 Clock Cycles */ +#define PSDMR_WRC_2C 0x00000020 /* 2 Clock Cycles */ +#define PSDMR_WRC_3C 0x00000030 /* 3 Clock Cycles */ + +#define PSDMR_CL_1 0x00000001 /* CAS Latency = 1 */ +#define PSDMR_CL_2 0x00000002 /* CAS Latency = 2 */ +#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */ + +/*----------------------------------------------------------------------- + * LSDMR - Local Bus SDRAM Mode Register 10-24 + */ + +/* + * No definitions here - the LSDMR has the same fields as the PSDMR. + */ + +/*----------------------------------------------------------------------- + * MPTPR - Memory Refresh Timer Prescaler Register 10-32 + * See User's Manual Errata for the changed definition (matches the + * 8xx now). The wrong prescaler definition causes excessive refreshes + * (typically "divide by 2" when "divide by 32" is intended) which will + * cause unnecessary memory subsystem slowdown. + */ +#define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */ +#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */ +#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */ +#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */ +#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */ +#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */ +#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */ + + +/*----------------------------------------------------------------------- + * TGCR1/TGCR2 - Timer Global Configuration Registers 17-4 + */ +#define TGCR1_CAS2 0x80 /* Cascade Timer 1 and 2 */ +#define TGCR1_STP2 0x20 /* Stop timer 2 */ +#define TGCR1_RST2 0x10 /* Reset timer 2 */ +#define TGCR1_GM1 0x08 /* Gate Mode for Pin 1 */ +#define TGCR1_STP1 0x02 /* Stop timer 1 */ +#define TGCR1_RST1 0x01 /* Reset timer 1 */ +#define TGCR2_CAS4 0x80 /* Cascade Timer 3 and 4 */ +#define TGCR2_STP4 0x20 /* Stop timer 4 */ +#define TGCR2_RST4 0x10 /* Reset timer 4 */ +#define TGCR2_GM2 0x08 /* Gate Mode for Pin 2 */ +#define TGCR2_STP3 0x02 /* Stop timer 3 */ +#define TGCR2_RST3 0x01 /* Reset timer 3 */ + + +/*----------------------------------------------------------------------- + * TMR1-TMR4 - Timer Mode Registers 17-6 + */ +#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ +#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/ +#define TMRx_OM 0x0020 /* Output Mode */ +#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/ +#define TMRx_FRR 0x0008 /* Free Run/Restart */ +#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ +#define TMRx_GE 0x0001 /* Gate Enable */ + +#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/ +#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ +#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ +#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ + +#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ +#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/ +#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/ +#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ + + +/*----------------------------------------------------------------------- + * CMXFCR - CMX FCC Clock Route Register 15-12 + */ +#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ +#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ +#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ +#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ +#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ +#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ +#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ +#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ +#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ + +#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ +#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ +#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ +#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ +#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ +#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ +#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ +#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ + +#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ +#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ +#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ +#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ +#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ +#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ +#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ +#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ + +#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ +#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ +#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ +#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ +#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ +#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ +#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ +#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ + +#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ +#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ +#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ +#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ +#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ +#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ +#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ +#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ + +#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ +#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ +#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ +#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ +#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ +#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ +#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ +#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ + +#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ +#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ +#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ +#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ +#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ +#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ +#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ +#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ + +/*----------------------------------------------------------------------- + * CMXSCR - CMX SCC Clock Route Register 15-14 + */ +#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ +#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ +#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ +#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ +#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ +#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ +#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ +#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ +#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ +#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ +#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ +#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ +#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ +#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ +#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ +#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ + +#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ +#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ +#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ +#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ +#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ +#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ +#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ +#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ + +#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ +#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ +#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ +#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ +#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ +#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ +#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ +#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ + +#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ +#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ +#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ +#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ +#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ +#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ +#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ +#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ + +#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ +#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ +#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ +#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ +#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ +#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ +#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ +#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ + +#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ +#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ +#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ +#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ +#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ +#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ +#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ +#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ + +#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ +#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ +#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ +#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ +#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ +#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ +#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ +#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ + +#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ +#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ +#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ +#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ +#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ +#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ +#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ +#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ + +#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ +#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ +#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ +#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ +#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ +#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ +#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ +#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ + +/*----------------------------------------------------------------------- + * CMXSMR - CMX SMC Clock Route Register 15-17 + */ +#define CMXSMR_SMC1 0x80 /* SMC1 Connection */ +#define CMXSMR_SMC1CS_MSK 0x30 /* SMC1 Clock Source */ +#define CMXSMR_SMC2 0x08 /* SMC2 Connection */ +#define CMXSMR_SMC2CS_MSK 0x03 /* SMC2 Clock Source */ + +#define CMXSMR_SMC1CS_BRG1 0x00 /* SMC1 Tx and Rx Clocks are BRG1 */ +#define CMXSMR_SMC1CS_BRG7 0x10 /* SMC1 Tx and Rx Clocks are BRG7 */ +#define CMXSMR_SMC1CS_CLK7 0x20 /* SMC1 Tx and Rx Clocks are CLK7 */ +#define CMXSMR_SMC1CS_CLK9 0x30 /* SMC1 Tx and Rx Clocks are CLK9 */ + +#define CMXSMR_SMC2CS_BRG2 0x00 /* SMC2 Tx and Rx Clocks are BRG2 */ +#define CMXSMR_SMC2CS_BRG8 0x01 /* SMC2 Tx and Rx Clocks are BRG8 */ +#define CMXSMR_SMC2CS_CLK19 0x02 /* SMC2 Tx and Rx Clocks are CLK19 */ +#define CMXSMR_SMC2CS_CLK20 0x03 /* SMC2 Tx and Rx Clocks are CLK20 */ + +/*----------------------------------------------------------------------- + * miscellaneous + */ + +#define UPMA 1 +#define UPMB 2 +#define UPMC 3 + +#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG) +extern __inline__ void +reset_8260_watchdog(volatile immap_t *immr) +{ + immr->im_siu_conf.sc_swsr = 0x556c; + immr->im_siu_conf.sc_swsr = 0xaa39; +} +#endif /* !__ASSEMBLY && CONFIG_WATCHDOG */ + +#endif /* __MPC8260_H__ */ diff --git a/include/mpc8260_irq.h b/include/mpc8260_irq.h new file mode 100644 index 0000000..9bee9a3 --- /dev/null +++ b/include/mpc8260_irq.h @@ -0,0 +1,48 @@ +#ifndef _MPC8260_IRQ_H +#define _MPC8260_IRQ_H + +/****************************************************************************/ +/* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC */ +/* source. There was no copyright information in the file. */ + +/* + * this is the # irq's for all ppc arch's (pmac/chrp/prep) + * so it is the max of them all + * + * [let's just worry about 8260 for now - mjj] + */ +#define NR_IRQS 64 + +/* The 8260 has an internal interrupt controller with a maximum of + * 64 IRQs. We will use NR_IRQs from above since it is large enough. + * Don't be confused by the 8260 documentation where they list an + * "interrupt number" and "interrupt vector". We are only interested + * in the interrupt vector. There are "reserved" holes where the + * vector number increases, but the interrupt number in the table does not. + * (Document errata updates have fixed this...make sure you have up to + * date processor documentation -- Dan). + */ +#define NR_SIU_INTS 64 + +/* There are many more than these, we will add them as we need them. +*/ +#define SIU_INT_SMC1 ((uint)0x04) +#define SIU_INT_SMC2 ((uint)0x05) +#define SIU_INT_IRQ1 ((uint)0x13) +#define SIU_INT_IRQ2 ((uint)0x14) +#define SIU_INT_IRQ3 ((uint)0x15) +#define SIU_INT_IRQ4 ((uint)0x16) +#define SIU_INT_IRQ5 ((uint)0x17) +#define SIU_INT_IRQ6 ((uint)0x18) +#define SIU_INT_IRQ7 ((uint)0x19) +#define SIU_INT_FCC1 ((uint)0x20) +#define SIU_INT_FCC2 ((uint)0x21) +#define SIU_INT_FCC3 ((uint)0x22) +#define SIU_INT_SCC1 ((uint)0x28) +#define SIU_INT_SCC2 ((uint)0x29) +#define SIU_INT_SCC3 ((uint)0x2a) +#define SIU_INT_SCC4 ((uint)0x2b) + +#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) + +#endif /* _MPC8260_IRQ_H */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h new file mode 100644 index 0000000..ea40bad --- /dev/null +++ b/include/mpc83xx.h @@ -0,0 +1,313 @@ +/* + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc83xx.h + * + * MPC83xx specific definitions + */ + +#ifndef __MPC83XX_H__ +#define __MPC83XX_H__ + +#if defined(CONFIG_E300) +#include +#endif + +/* + * MPC83xx cpu provide RCR register to do reset thing specially. easier + * to implement + */ + +#define MPC83xx_RESET + +/* + * System reset offset (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 + +/* + * Default Internal Memory Register Space (Freescale recomandation) + */ +#define CONFIG_DEFAULT_IMMR 0xFF400000 + +/* + * Watchdog + */ +#define SWCRR 0x0204 +#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ +#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ +#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ +#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ +#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + +#define SWCNR 0x0208 +#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. +#define SWCNR_RES ~(SWCNR_SWCN) + +#define SWSRR 0x020E + +/* + * Default Internal Memory Register Space (Freescale recomandation) + */ +#define IMMRBAR 0x0000 +#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ +#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) + +/* + * Default Internal Memory Register Space (Freescale recomandation) + */ +#define LBLAWBAR0 0x0020 +#define LBLAWAR0 0x0024 +#define LBLAWBAR1 0x0028 +#define LBLAWAR1 0x002C +#define LBLAWBAR2 0x0030 +#define LBLAWAR2 0x0034 +#define LBLAWBAR3 0x0038 +#define LBLAWAR3 0x003C + + +/* + * Base Registers & Option Registers + */ +#define BR0 0x5000 +#define BR1 0x5008 +#define BR2 0x5010 +#define BR3 0x5018 +#define BR4 0x5020 +#define BR5 0x5028 +#define BR6 0x5030 +#define BR7 0x5038 + +#define BR_BA 0xFFFF8000 +#define BR_BA_SHIFT 15 +#define BR_PS 0x00001800 +#define BR_PS_SHIFT 11 +#define BR_PS_8 0x00000800 /* Port Size 8 bit */ +#define BR_PS_16 0x00001000 /* Port Size 16 bit */ +#define BR_PS_32 0x00001800 /* Port Size 32 bit */ +#define BR_DECC 0x00000600 +#define BR_DECC_SHIFT 9 +#define BR_WP 0x00000100 +#define BR_WP_SHIFT 8 +#define BR_MSEL 0x000000E0 +#define BR_MSEL_SHIFT 5 +#define BR_MS_GPCM 0x00000000 /* GPCM */ +#define BR_MS_SDRAM 0x00000060 /* SDRAM */ +#define BR_MS_UPMA 0x00000080 /* UPMA */ +#define BR_MS_UPMB 0x000000A0 /* UPMB */ +#define BR_MS_UPMC 0x000000C0 /* UPMC */ +#define BR_V 0x00000001 +#define BR_V_SHIFT 0 +#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) + +#define OR0 0x5004 +#define OR1 0x500C +#define OR2 0x5014 +#define OR3 0x501C +#define OR4 0x5024 +#define OR5 0x502C +#define OR6 0x5034 +#define OR7 0x503C + +#define OR_GPCM_AM 0xFFFF8000 +#define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_BCTLD 0x00001000 +#define OR_GPCM_BCTLD_SHIFT 12 +#define OR_GPCM_CSNT 0x00000800 +#define OR_GPCM_CSNT_SHIFT 11 +#define OR_GPCM_ACS 0x00000600 +#define OR_GPCM_ACS_SHIFT 9 +#define OR_GPCM_ACS_0b10 0x00000400 +#define OR_GPCM_ACS_0b11 0x00000600 +#define OR_GPCM_XACS 0x00000100 +#define OR_GPCM_XACS_SHIFT 8 +#define OR_GPCM_SCY 0x000000F0 +#define OR_GPCM_SCY_SHIFT 4 +#define OR_GPCM_SCY_1 0x00000010 +#define OR_GPCM_SCY_2 0x00000020 +#define OR_GPCM_SCY_3 0x00000030 +#define OR_GPCM_SCY_4 0x00000040 +#define OR_GPCM_SCY_5 0x00000050 +#define OR_GPCM_SCY_6 0x00000060 +#define OR_GPCM_SCY_7 0x00000070 +#define OR_GPCM_SCY_8 0x00000080 +#define OR_GPCM_SCY_9 0x00000090 +#define OR_GPCM_SCY_10 0x000000a0 +#define OR_GPCM_SCY_11 0x000000b0 +#define OR_GPCM_SCY_12 0x000000c0 +#define OR_GPCM_SCY_13 0x000000d0 +#define OR_GPCM_SCY_14 0x000000e0 +#define OR_GPCM_SCY_15 0x000000f0 +#define OR_GPCM_SETA 0x00000008 +#define OR_GPCM_SETA_SHIFT 3 +#define OR_GPCM_TRLX 0x00000004 +#define OR_GPCM_TRLX_SHIFT 2 +#define OR_GPCM_EHTR 0x00000002 +#define OR_GPCM_EHTR_SHIFT 1 +#define OR_GPCM_EAD 0x00000001 +#define OR_GPCM_EAD_SHIFT 0 + +#define OR_UPM_AM 0xFFFF8000 +#define OR_UPM_AM_SHIFT 15 +#define OR_UPM_XAM 0x00006000 +#define OR_UPM_XAM_SHIFT 13 +#define OR_UPM_BCTLD 0x00001000 +#define OR_UPM_BCTLD_SHIFT 12 +#define OR_UPM_BI 0x00000100 +#define OR_UPM_BI_SHIFT 8 +#define OR_UPM_TRLX 0x00000004 +#define OR_UPM_TRLX_SHIFT 2 +#define OR_UPM_EHTR 0x00000002 +#define OR_UPM_EHTR_SHIFT 1 +#define OR_UPM_EAD 0x00000001 +#define OR_UPM_EAD_SHIFT 0 + +#define OR_SDRAM_AM 0xFFFF8000 +#define OR_SDRAM_AM_SHIFT 15 +#define OR_SDRAM_XAM 0x00006000 +#define OR_SDRAM_XAM_SHIFT 13 +#define OR_SDRAM_COLS 0x00001C00 +#define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_ROWS 0x000001C0 +#define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_PMSEL 0x00000020 +#define OR_SDRAM_PMSEL_SHIFT 5 +#define OR_SDRAM_EAD 0x00000001 +#define OR_SDRAM_EAD_SHIFT 0 + +/* + * Hard Reset Configration Word - High + */ +#define HRCWH_PCI_AGENT 0x00000000 +#define HRCWH_PCI_HOST 0x80000000 + +#define HRCWH_32_BIT_PCI 0x00000000 +#define HRCWH_64_BIT_PCI 0x40000000 + +#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 + +#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 + +#define HRCWH_CORE_DISABLE 0x08000000 +#define HRCWH_CORE_ENABLE 0x00000000 + +#define HRCWH_FROM_0X00000100 0x00000000 +#define HRCWH_FROM_0XFFF00100 0x04000000 + +#define HRCWH_BOOTSEQ_DISABLE 0x00000000 +#define HRCWH_BOOTSEQ_NORMAL 0x01000000 +#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 + +#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 +#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 + +#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 +#define HRCWH_ROM_LOC_PCI1 0x00100000 +#define HRCWH_ROM_LOC_PCI2 0x00200000 +#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 +#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 +#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 + +#define HRCWH_TSEC1M_IN_RGMII 0x00000000 +#define HRCWH_TSEC1M_IN_RTBI 0x00004000 +#define HRCWH_TSEC1M_IN_GMII 0x00008000 +#define HRCWH_TSEC1M_IN_TBI 0x0000C000 + +#define HRCWH_TSEC2M_IN_RGMII 0x00000000 +#define HRCWH_TSEC2M_IN_RTBI 0x00001000 +#define HRCWH_TSEC2M_IN_GMII 0x00002000 +#define HRCWH_TSEC2M_IN_TBI 0x00003000 + +#define HRCWH_BIG_ENDIAN 0x00000000 +#define HRCWH_LITTLE_ENDIAN 0x00000008 + +/* + * Hard Reset Configration Word - Low + */ +#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 +#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 + +#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 +#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 + +#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 +#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 +#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 +#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 +#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 +#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 +#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 +#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 +#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 +#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 +#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 +#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 +#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 +#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 +#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 +#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 + +#define HRCWL_VCO_BYPASS 0x00000000 +#define HRCWL_VCO_1X2 0x00000000 +#define HRCWL_VCO_1X4 0x00200000 +#define HRCWL_VCO_1X8 0x00400000 + +#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 +#define HRCWL_CORE_TO_CSB_1X1 0x00020000 +#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 +#define HRCWL_CORE_TO_CSB_2X1 0x00040000 +#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 +#define HRCWL_CORE_TO_CSB_3X1 0x00060000 + +/* + * LCRR - Clock Ratio Register (10.3.1.16) + */ +#define LCRR_DBYP 0x80000000 +#define LCRR_DBYP_SHIFT 31 +#define LCRR_BUFCMDC 0x30000000 +#define LCRR_BUFCMDC_1 0x10000000 +#define LCRR_BUFCMDC_2 0x20000000 +#define LCRR_BUFCMDC_3 0x30000000 +#define LCRR_BUFCMDC_4 0x00000000 +#define LCRR_BUFCMDC_SHIFT 28 +#define LCRR_ECL 0x03000000 +#define LCRR_ECL_4 0x00000000 +#define LCRR_ECL_5 0x01000000 +#define LCRR_ECL_6 0x02000000 +#define LCRR_ECL_7 0x03000000 +#define LCRR_ECL_SHIFT 24 +#define LCRR_EADC 0x00030000 +#define LCRR_EADC_1 0x00010000 +#define LCRR_EADC_2 0x00020000 +#define LCRR_EADC_3 0x00030000 +#define LCRR_EADC_4 0x00000000 +#define LCRR_EADC_SHIFT 16 +#define LCRR_CLKDIV 0x0000000F +#define LCRR_CLKDIV_2 0x00000002 +#define LCRR_CLKDIV_4 0x00000004 +#define LCRR_CLKDIV_8 0x00000008 +#define LCRR_CLKDIV_SHIFT 0 + +#endif /* __MPC83XX_H__ */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h new file mode 100644 index 0000000..60b6c61 --- /dev/null +++ b/include/mpc85xx.h @@ -0,0 +1,28 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright(c) 2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) + */ + +#ifndef __MPC85xx_H__ +#define __MPC85xx_H__ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ + +#if defined(CONFIG_E500) +#include +#endif + +/* + * SCCR - System Clock Control Register, 9-8 + */ +#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ +#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ +#define SCCR_DFBRG_SHIFT 0 + +#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ +#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ +#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ +#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ + +#endif /* __MPC85xx_H__ */ diff --git a/include/mpc8xx.h b/include/mpc8xx.h new file mode 100644 index 0000000..2911758 --- /dev/null +++ b/include/mpc8xx.h @@ -0,0 +1,634 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8xx.h + * + * MPC8xx specific definitions + */ + +#ifndef __MPCXX_H__ +#define __MPCXX_H__ + + +/*----------------------------------------------------------------------- + * Exception offsets (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ + + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control Register 11-9 + */ +#define SYPCR_SWTC 0xFFFF0000 /* Software Watchdog Timer Count */ +#define SYPCR_BMT 0x0000FF00 /* Bus Monitor Timing */ +#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */ +#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */ +#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ +#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */ +#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration Register 11-6 + */ +#define SIUMCR_EARB 0x80000000 /* External Arbitration */ +#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */ +#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */ +#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */ +#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */ +#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */ +#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */ +#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */ +#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */ +#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */ +#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */ +#define SIUMCR_DBGC01 0x00200000 /* - " - */ +#define SIUMCR_DBGC10 0x00400000 /* - " - */ +#define SIUMCR_DBGC11 0x00600000 /* - " - */ +#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */ +#define SIUMCR_DBPC01 0x00080000 /* - " - */ +#define SIUMCR_DBPC10 0x00100000 /* - " - */ +#define SIUMCR_DBPC11 0x00180000 /* - " - */ +#define SIUMCR_FRC 0x00020000 /* FRZ pin Configuration */ +#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ +#define SIUMCR_PNCS 0x00008000 /* Parity Non-mem Crtl reg */ +#define SIUMCR_OPAR 0x00004000 /* Odd Parity */ +#define SIUMCR_DPC 0x00002000 /* Data Parity pins Config. */ +#define SIUMCR_MPRE 0x00001000 /* Multi CPU Reserva. Enable */ +#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */ +#define SIUMCR_MLRC01 0x00000400 /* - " - */ +#define SIUMCR_MLRC10 0x00000800 /* - " - */ +#define SIUMCR_MLRC11 0x00000C00 /* - " - */ +#define SIUMCR_AEME 0x00000200 /* Asynchro External Master */ +#define SIUMCR_SEME 0x00000100 /* Synchro External Master */ +#define SIUMCR_BSC 0x00000080 /* Byte Select Configuration */ +#define SIUMCR_GB5E 0x00000040 /* GPL_B(5) Enable */ +#define SIUMCR_B2DD 0x00000020 /* Bank 2 Double Drive */ +#define SIUMCR_B3DD 0x00000010 /* Bank 3 Double Drive */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control Register 11-26 + */ +#define TBSCR_TBIRQ7 0x8000 /* Time Base Interrupt Request 7 */ +#define TBSCR_TBIRQ6 0x4000 /* Time Base Interrupt Request 6 */ +#define TBSCR_TBIRQ5 0x2000 /* Time Base Interrupt Request 5 */ +#define TBSCR_TBIRQ4 0x1000 /* Time Base Interrupt Request 4 */ +#define TBSCR_TBIRQ3 0x0800 /* Time Base Interrupt Request 3 */ +#define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */ +#define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */ +#define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */ +#if 0 /* already in asm/8xx_immap.h */ +#define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */ +#define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */ +#define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */ +#define TBSCR_REFBE 0x0004 /* Second Interrupt Enable B */ +#define TBSCR_TBF 0x0002 /* Time Base Freeze */ +#define TBSCR_TBE 0x0001 /* Time Base Enable */ +#endif + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control Register 11-31 + */ +#undef PISCR_PIRQ /* TBD */ +#define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */ +#if 0 /* already in asm/8xx_immap.h */ +#define PISCR_PS 0x0080 /* Periodic interrupt Status */ +#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */ +#define PISCR_PTE 0x0001 /* Periodic Timer Enable */ +#endif + +/*----------------------------------------------------------------------- + * RSR - Reset Status Register 5-4 + */ +#define RSR_JTRS 0x01000000 /* JTAG Reset Status */ +#define RSR_DBSRS 0x02000000 /* Debug Port Soft Reset Status */ +#define RSR_DBHRS 0x04000000 /* Debug Port Hard Reset Status */ +#define RSR_CSRS 0x08000000 /* Check Stop Reset Status */ +#define RSR_SWRS 0x10000000 /* Software Watchdog Reset Status*/ +#define RSR_LLRS 0x20000000 /* Loss-of-Lock Reset Status */ +#define RSR_ESRS 0x40000000 /* External Soft Reset Status */ +#define RSR_EHRS 0x80000000 /* External Hard Reset Status */ + +#define RSR_ALLBITS (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS) + +/*----------------------------------------------------------------------- + * Newer chips (MPC866 family and MPC87x/88x family) have different + * clock distribution system. Their IMMR lower half is >= 0x0800 + */ +#define MPC8xx_NEW_CLK 0x0800 + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + */ +/* Newer chips (MPC866/87x/88x et al) defines */ +#define PLPRCR_MFN_MSK 0xF8000000 /* Multiplication factor numerator bits */ +#define PLPRCR_MFN_SHIFT 27 /* Multiplication factor numerator shift*/ +#define PLPRCR_MFD_MSK 0x07C00000 /* Multiplication factor denominator bits */ +#define PLPRCR_MFD_SHIFT 22 /* Multiplication factor denominator shift*/ +#define PLPRCR_S_MSK 0x00300000 /* Multiplication factor integer bits */ +#define PLPRCR_S_SHIFT 20 /* Multiplication factor integer shift */ +#define PLPRCR_MFI_MSK 0x000F0000 /* Multiplication factor integer bits */ +#define PLPRCR_MFI_SHIFT 16 /* Multiplication factor integer shift */ + +#define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */ +#define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */ +#define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */ + +/* Multiplication factor + PDF bits */ +#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \ + PLPRCR_MFD_MSK | \ + PLPRCR_S_MSK | \ + PLPRCR_MFI_MSK | \ + PLPRCR_PDF_MSK) + +/* Older chips (MPC860/862 et al) defines */ +#define PLPRCR_MF_MSK 0xFFF00000 /* Multiplication factor bits */ +#define PLPRCR_MF_SHIFT 20 /* Multiplication factor shift value */ + +#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ +#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ + +#define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */ +#define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */ +#define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */ +#define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */ +#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */ +#define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */ + +/* Common defines */ +#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ +#define PLPRCR_CSRC 0x00000400 /* Clock Source */ + +#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ +#define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */ +#define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */ + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + */ +#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ +#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ +#define SCCR_COM10 0x40000000 /* reserved */ +#define SCCR_COM11 0x60000000 /* CLKOUT output buffer disabled */ +#define SCCR_TBS 0x02000000 /* Time Base Source */ +#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ +#define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */ +#define SCCR_CRQEN 0x00400000 /* CPM Request Enable */ +#define SCCR_PRQEN 0x00200000 /* Power Management Request Enable */ +#define SCCR_EBDF00 0x00000000 /* CLKOUT is GCLK2 / 1 (normal op.) */ +#define SCCR_EBDF01 0x00020000 /* CLKOUT is GCLK2 / 2 */ +#define SCCR_EBDF10 0x00040000 /* reserved */ +#define SCCR_EBDF11 0x00060000 /* reserved */ +#define SCCR_DFSYNC00 0x00000000 /* SyncCLK division by 1 (normal op.) */ +#define SCCR_DFSYNC01 0x00002000 /* SyncCLK division by 4 */ +#define SCCR_DFSYNC10 0x00004000 /* SyncCLK division by 16 */ +#define SCCR_DFSYNC11 0x00006000 /* SyncCLK division by 64 */ +#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 1 (normal op.) */ +#define SCCR_DFBRG01 0x00000800 /* BRGCLK division by 4 */ +#define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ +#define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ +#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ +#define SCCR_DFNL001 0x00000100 /* Division by 4 */ +#define SCCR_DFNL010 0x00000200 /* Division by 8 */ +#define SCCR_DFNL011 0x00000300 /* Division by 16 */ +#define SCCR_DFNL100 0x00000400 /* Division by 32 */ +#define SCCR_DFNL101 0x00000500 /* Division by 64 */ +#define SCCR_DFNL110 0x00000600 /* Division by 128 */ +#define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ +#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ +#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */ +#define SCCR_DFNH111 0x000000E0 /* reserved */ +#define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */ +#define SCCR_DFLCD001 0x00000004 /* Division by 2 */ +#define SCCR_DFLCD010 0x00000008 /* Division by 4 */ +#define SCCR_DFLCD011 0x0000000C /* Division by 8 */ +#define SCCR_DFLCD100 0x00000010 /* Division by 16 */ +#define SCCR_DFLCD101 0x00000014 /* Division by 32 */ +#define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */ +#define SCCR_DFLCD111 0x0000001C /* reserved */ +#define SCCR_DFALCD00 0x00000000 /* Division by 1 (default = minimum) */ +#define SCCR_DFALCD01 0x00000001 /* Division by 3 */ +#define SCCR_DFALCD10 0x00000002 /* Division by 5 */ +#define SCCR_DFALCD11 0x00000003 /* Division by 7 (maximum) */ + + +/*----------------------------------------------------------------------- + * BR - Memory Controler: Base Register 16-9 + */ +#define BR_BA_MSK 0xFFFF8000 /* Base Address Mask */ +#define BR_AT_MSK 0x00007000 /* Address Type Mask */ +#define BR_PS_MSK 0x00000C00 /* Port Size Mask */ +#define BR_PS_32 0x00000000 /* 32 bit port size */ +#define BR_PS_16 0x00000800 /* 16 bit port size */ +#define BR_PS_8 0x00000400 /* 8 bit port size */ +#define BR_PARE 0x00000200 /* Parity Enable */ +#define BR_WP 0x00000100 /* Write Protect */ +#define BR_MS_MSK 0x000000C0 /* Machine Select Mask */ +#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ +#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ +#define BR_MS_UPMB 0x000000C0 /* U.P.M.B Machine Select */ +#define BR_V 0x00000001 /* Bank Valid */ + +/*----------------------------------------------------------------------- + * OR - Memory Controler: Option Register 16-11 + */ +#define OR_AM_MSK 0xFFFF8000 /* Address Mask Mask */ +#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ +#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ + /* Address Multiplex */ +#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ +#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ +#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ +#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ +#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ +#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ +#define OR_BI 0x00000100 /* Burst inhibit */ +#define OR_SCY_MSK 0x000000F0 /* Cycle Lenght in Clocks */ +#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ +#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ +#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ +#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ +#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ +#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ +#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ +#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ +#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ +#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ +#define OR_SCY_10_CLK 0x000000A0 /* 10 clock cycles wait states */ +#define OR_SCY_11_CLK 0x000000B0 /* 11 clock cycles wait states */ +#define OR_SCY_12_CLK 0x000000C0 /* 12 clock cycles wait states */ +#define OR_SCY_13_CLK 0x000000D0 /* 13 clock cycles wait states */ +#define OR_SCY_14_CLK 0x000000E0 /* 14 clock cycles wait states */ +#define OR_SCY_15_CLK 0x000000F0 /* 15 clock cycles wait states */ +#define OR_SETA 0x00000008 /* External Transfer Acknowledge */ +#define OR_TRLX 0x00000004 /* Timing Relaxed */ +#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ + + +/*----------------------------------------------------------------------- + * MPTPR - Memory Periodic Timer Prescaler Register 16-17 + */ +#define MPTPR_PTP_MSK 0xFF00 /* Periodic Timers Prescaler Mask */ +#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */ +#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */ +#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */ +#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */ +#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */ +#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */ + +/*----------------------------------------------------------------------- + * MCR - Memory Command Register + */ +#define MCR_OP_WRITE 0x00000000 /* WRITE command */ +#define MCR_OP_READ 0x40000000 /* READ command */ +#define MCR_OP_RUN 0x80000000 /* RUN command */ +#define MCR_UPM_A 0x00000000 /* Select UPM A */ +#define MCR_UPM_B 0x00800000 /* Select UPM B */ +#define MCR_MB_CS0 0x00000000 /* Use Chip Select /CS0 */ +#define MCR_MB_CS1 0x00002000 /* Use Chip Select /CS1 */ +#define MCR_MB_CS2 0x00004000 /* Use Chip Select /CS2 */ +#define MCR_MB_CS3 0x00006000 /* Use Chip Select /CS3 */ +#define MCR_MB_CS4 0x00008000 /* Use Chip Select /CS4 */ +#define MCR_MB_CS5 0x0000A000 /* Use Chip Select /CS5 */ +#define MCR_MB_CS6 0x0000C000 /* Use Chip Select /CS6 */ +#define MCR_MB_CS7 0x0000E000 /* Use Chip Select /CS7 */ +#define MCR_MLCF(n) (((n)&0xF)<<8) /* Memory Command Loop Count Field */ +#define MCR_MAD(addr) ((addr)&0x3F) /* Memory Array Index */ + +/*----------------------------------------------------------------------- + * Machine A Mode Register 16-13 + */ +#define MAMR_PTA_MSK 0xFF000000 /* Periodic Timer A period mask */ +#define MAMR_PTA_SHIFT 0x00000018 /* Periodic Timer A period shift */ +#define MAMR_PTAE 0x00800000 /* Periodic Timer A Enable */ +#define MAMR_AMA_MSK 0x00700000 /* Addess Multiplexing size A */ +#define MAMR_AMA_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ +#define MAMR_AMA_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */ +#define MAMR_AMA_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */ +#define MAMR_AMA_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */ +#define MAMR_AMA_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */ +#define MAMR_AMA_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */ +#define MAMR_DSA_MSK 0x00060000 /* Disable Timer period mask */ +#define MAMR_DSA_1_CYCL 0x00000000 /* 1 cycle Disable Period */ +#define MAMR_DSA_2_CYCL 0x00020000 /* 2 cycle Disable Period */ +#define MAMR_DSA_3_CYCL 0x00040000 /* 3 cycle Disable Period */ +#define MAMR_DSA_4_CYCL 0x00060000 /* 4 cycle Disable Period */ +#define MAMR_G0CLA_MSK 0x0000E000 /* General Line 0 Control A */ +#define MAMR_G0CLA_A12 0x00000000 /* General Line 0 : A12 */ +#define MAMR_G0CLA_A11 0x00002000 /* General Line 0 : A11 */ +#define MAMR_G0CLA_A10 0x00004000 /* General Line 0 : A10 */ +#define MAMR_G0CLA_A9 0x00006000 /* General Line 0 : A9 */ +#define MAMR_G0CLA_A8 0x00008000 /* General Line 0 : A8 */ +#define MAMR_G0CLA_A7 0x0000A000 /* General Line 0 : A7 */ +#define MAMR_G0CLA_A6 0x0000C000 /* General Line 0 : A6 */ +#define MAMR_G0CLA_A5 0x0000E000 /* General Line 0 : A5 */ +#define MAMR_GPL_A4DIS 0x00001000 /* GPL_A4 ouput line Disable */ +#define MAMR_RLFA_MSK 0x00000F00 /* Read Loop Field A mask */ +#define MAMR_RLFA_1X 0x00000100 /* The Read Loop is executed 1 time */ +#define MAMR_RLFA_2X 0x00000200 /* The Read Loop is executed 2 times */ +#define MAMR_RLFA_3X 0x00000300 /* The Read Loop is executed 3 times */ +#define MAMR_RLFA_4X 0x00000400 /* The Read Loop is executed 4 times */ +#define MAMR_RLFA_5X 0x00000500 /* The Read Loop is executed 5 times */ +#define MAMR_RLFA_6X 0x00000600 /* The Read Loop is executed 6 times */ +#define MAMR_RLFA_7X 0x00000700 /* The Read Loop is executed 7 times */ +#define MAMR_RLFA_8X 0x00000800 /* The Read Loop is executed 8 times */ +#define MAMR_RLFA_9X 0x00000900 /* The Read Loop is executed 9 times */ +#define MAMR_RLFA_10X 0x00000A00 /* The Read Loop is executed 10 times */ +#define MAMR_RLFA_11X 0x00000B00 /* The Read Loop is executed 11 times */ +#define MAMR_RLFA_12X 0x00000C00 /* The Read Loop is executed 12 times */ +#define MAMR_RLFA_13X 0x00000D00 /* The Read Loop is executed 13 times */ +#define MAMR_RLFA_14X 0x00000E00 /* The Read Loop is executed 14 times */ +#define MAMR_RLFA_15X 0x00000F00 /* The Read Loop is executed 15 times */ +#define MAMR_RLFA_16X 0x00000000 /* The Read Loop is executed 16 times */ +#define MAMR_WLFA_MSK 0x000000F0 /* Write Loop Field A mask */ +#define MAMR_WLFA_1X 0x00000010 /* The Write Loop is executed 1 time */ +#define MAMR_WLFA_2X 0x00000020 /* The Write Loop is executed 2 times */ +#define MAMR_WLFA_3X 0x00000030 /* The Write Loop is executed 3 times */ +#define MAMR_WLFA_4X 0x00000040 /* The Write Loop is executed 4 times */ +#define MAMR_WLFA_5X 0x00000050 /* The Write Loop is executed 5 times */ +#define MAMR_WLFA_6X 0x00000060 /* The Write Loop is executed 6 times */ +#define MAMR_WLFA_7X 0x00000070 /* The Write Loop is executed 7 times */ +#define MAMR_WLFA_8X 0x00000080 /* The Write Loop is executed 8 times */ +#define MAMR_WLFA_9X 0x00000090 /* The Write Loop is executed 9 times */ +#define MAMR_WLFA_10X 0x000000A0 /* The Write Loop is executed 10 times */ +#define MAMR_WLFA_11X 0x000000B0 /* The Write Loop is executed 11 times */ +#define MAMR_WLFA_12X 0x000000C0 /* The Write Loop is executed 12 times */ +#define MAMR_WLFA_13X 0x000000D0 /* The Write Loop is executed 13 times */ +#define MAMR_WLFA_14X 0x000000E0 /* The Write Loop is executed 14 times */ +#define MAMR_WLFA_15X 0x000000F0 /* The Write Loop is executed 15 times */ +#define MAMR_WLFA_16X 0x00000000 /* The Write Loop is executed 16 times */ +#define MAMR_TLFA_MSK 0x0000000F /* Timer Loop Field A mask */ +#define MAMR_TLFA_1X 0x00000001 /* The Timer Loop is executed 1 time */ +#define MAMR_TLFA_2X 0x00000002 /* The Timer Loop is executed 2 times */ +#define MAMR_TLFA_3X 0x00000003 /* The Timer Loop is executed 3 times */ +#define MAMR_TLFA_4X 0x00000004 /* The Timer Loop is executed 4 times */ +#define MAMR_TLFA_5X 0x00000005 /* The Timer Loop is executed 5 times */ +#define MAMR_TLFA_6X 0x00000006 /* The Timer Loop is executed 6 times */ +#define MAMR_TLFA_7X 0x00000007 /* The Timer Loop is executed 7 times */ +#define MAMR_TLFA_8X 0x00000008 /* The Timer Loop is executed 8 times */ +#define MAMR_TLFA_9X 0x00000009 /* The Timer Loop is executed 9 times */ +#define MAMR_TLFA_10X 0x0000000A /* The Timer Loop is executed 10 times */ +#define MAMR_TLFA_11X 0x0000000B /* The Timer Loop is executed 11 times */ +#define MAMR_TLFA_12X 0x0000000C /* The Timer Loop is executed 12 times */ +#define MAMR_TLFA_13X 0x0000000D /* The Timer Loop is executed 13 times */ +#define MAMR_TLFA_14X 0x0000000E /* The Timer Loop is executed 14 times */ +#define MAMR_TLFA_15X 0x0000000F /* The Timer Loop is executed 15 times */ +#define MAMR_TLFA_16X 0x00000000 /* The Timer Loop is executed 16 times */ + +/*----------------------------------------------------------------------- + * Machine B Mode Register 16-13 + */ +#define MBMR_PTB_MSK 0xFF000000 /* Periodic Timer B period mask */ +#define MBMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */ +#define MBMR_PTBE 0x00800000 /* Periodic Timer B Enable */ +#define MBMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */ +#define MBMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ +#define MBMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */ +#define MBMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */ +#define MBMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */ +#define MBMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */ +#define MBMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */ +#define MBMR_DSB_MSK 0x00060000 /* Disable Timer period mask */ +#define MBMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */ +#define MBMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */ +#define MBMR_DSB_3_CYCL 0x00040000 /* 3 cycle Disable Period */ +#define MBMR_DSB_4_CYCL 0x00060000 /* 4 cycle Disable Period */ +#define MBMR_G0CLB_MSK 0x0000E000 /* General Line 0 Control B */ +#define MBMR_G0CLB_A12 0x00000000 /* General Line 0 : A12 */ +#define MBMR_G0CLB_A11 0x00002000 /* General Line 0 : A11 */ +#define MBMR_G0CLB_A10 0x00004000 /* General Line 0 : A10 */ +#define MBMR_G0CLB_A9 0x00006000 /* General Line 0 : A9 */ +#define MBMR_G0CLB_A8 0x00008000 /* General Line 0 : A8 */ +#define MBMR_G0CLB_A7 0x0000A000 /* General Line 0 : A7 */ +#define MBMR_G0CLB_A6 0x0000C000 /* General Line 0 : A6 */ +#define MBMR_G0CLB_A5 0x0000E000 /* General Line 0 : A5 */ +#define MBMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */ +#define MBMR_RLFB_MSK 0x00000F00 /* Read Loop Field B mask */ +#define MBMR_RLFB_1X 0x00000100 /* The Read Loop is executed 1 time */ +#define MBMR_RLFB_2X 0x00000200 /* The Read Loop is executed 2 times */ +#define MBMR_RLFB_3X 0x00000300 /* The Read Loop is executed 3 times */ +#define MBMR_RLFB_4X 0x00000400 /* The Read Loop is executed 4 times */ +#define MBMR_RLFB_5X 0x00000500 /* The Read Loop is executed 5 times */ +#define MBMR_RLFB_6X 0x00000600 /* The Read Loop is executed 6 times */ +#define MBMR_RLFB_7X 0x00000700 /* The Read Loop is executed 7 times */ +#define MBMR_RLFB_8X 0x00000800 /* The Read Loop is executed 8 times */ +#define MBMR_RLFB_9X 0x00000900 /* The Read Loop is executed 9 times */ +#define MBMR_RLFB_10X 0x00000A00 /* The Read Loop is executed 10 times */ +#define MBMR_RLFB_11X 0x00000B00 /* The Read Loop is executed 11 times */ +#define MBMR_RLFB_12X 0x00000C00 /* The Read Loop is executed 12 times */ +#define MBMR_RLFB_13X 0x00000D00 /* The Read Loop is executed 13 times */ +#define MBMR_RLFB_14X 0x00000E00 /* The Read Loop is executed 14 times */ +#define MBMR_RLFB_15X 0x00000f00 /* The Read Loop is executed 15 times */ +#define MBMR_RLFB_16X 0x00000000 /* The Read Loop is executed 16 times */ +#define MBMR_WLFB_MSK 0x000000F0 /* Write Loop Field B mask */ +#define MBMR_WLFB_1X 0x00000010 /* The Write Loop is executed 1 time */ +#define MBMR_WLFB_2X 0x00000020 /* The Write Loop is executed 2 times */ +#define MBMR_WLFB_3X 0x00000030 /* The Write Loop is executed 3 times */ +#define MBMR_WLFB_4X 0x00000040 /* The Write Loop is executed 4 times */ +#define MBMR_WLFB_5X 0x00000050 /* The Write Loop is executed 5 times */ +#define MBMR_WLFB_6X 0x00000060 /* The Write Loop is executed 6 times */ +#define MBMR_WLFB_7X 0x00000070 /* The Write Loop is executed 7 times */ +#define MBMR_WLFB_8X 0x00000080 /* The Write Loop is executed 8 times */ +#define MBMR_WLFB_9X 0x00000090 /* The Write Loop is executed 9 times */ +#define MBMR_WLFB_10X 0x000000A0 /* The Write Loop is executed 10 times */ +#define MBMR_WLFB_11X 0x000000B0 /* The Write Loop is executed 11 times */ +#define MBMR_WLFB_12X 0x000000C0 /* The Write Loop is executed 12 times */ +#define MBMR_WLFB_13X 0x000000D0 /* The Write Loop is executed 13 times */ +#define MBMR_WLFB_14X 0x000000E0 /* The Write Loop is executed 14 times */ +#define MBMR_WLFB_15X 0x000000F0 /* The Write Loop is executed 15 times */ +#define MBMR_WLFB_16X 0x00000000 /* The Write Loop is executed 16 times */ +#define MBMR_TLFB_MSK 0x0000000F /* Timer Loop Field B mask */ +#define MBMR_TLFB_1X 0x00000001 /* The Timer Loop is executed 1 time */ +#define MBMR_TLFB_2X 0x00000002 /* The Timer Loop is executed 2 times */ +#define MBMR_TLFB_3X 0x00000003 /* The Timer Loop is executed 3 times */ +#define MBMR_TLFB_4X 0x00000004 /* The Timer Loop is executed 4 times */ +#define MBMR_TLFB_5X 0x00000005 /* The Timer Loop is executed 5 times */ +#define MBMR_TLFB_6X 0x00000006 /* The Timer Loop is executed 6 times */ +#define MBMR_TLFB_7X 0x00000007 /* The Timer Loop is executed 7 times */ +#define MBMR_TLFB_8X 0x00000008 /* The Timer Loop is executed 8 times */ +#define MBMR_TLFB_9X 0x00000009 /* The Timer Loop is executed 9 times */ +#define MBMR_TLFB_10X 0x0000000A /* The Timer Loop is executed 10 times */ +#define MBMR_TLFB_11X 0x0000000B /* The Timer Loop is executed 11 times */ +#define MBMR_TLFB_12X 0x0000000C /* The Timer Loop is executed 12 times */ +#define MBMR_TLFB_13X 0x0000000D /* The Timer Loop is executed 13 times */ +#define MBMR_TLFB_14X 0x0000000E /* The Timer Loop is executed 14 times */ +#define MBMR_TLFB_15X 0x0000000F /* The Timer Loop is executed 15 times */ +#define MBMR_TLFB_16X 0x00000000 /* The Timer Loop is executed 16 times */ + +/*----------------------------------------------------------------------- + * Timer Global Configuration Register 18-8 + */ +#define TGCR_CAS4 0x8000 /* Cascade Timer 3 and 4 */ +#define TGCR_FRZ4 0x4000 /* Freeze timer 4 */ +#define TGCR_STP4 0x2000 /* Stop timer 4 */ +#define TGCR_RST4 0x1000 /* Reset timer 4 */ +#define TGCR_GM2 0x0800 /* Gate Mode for Pin 2 */ +#define TGCR_FRZ3 0x0400 /* Freeze timer 3 */ +#define TGCR_STP3 0x0200 /* Stop timer 3 */ +#define TGCR_RST3 0x0100 /* Reset timer 3 */ +#define TGCR_CAS2 0x0080 /* Cascade Timer 1 and 2 */ +#define TGCR_FRZ2 0x0040 /* Freeze timer 2 */ +#define TGCR_STP2 0x0020 /* Stop timer 2 */ +#define TGCR_RST2 0x0010 /* Reset timer 2 */ +#define TGCR_GM1 0x0008 /* Gate Mode for Pin 1 */ +#define TGCR_FRZ1 0x0004 /* Freeze timer 1 */ +#define TGCR_STP1 0x0002 /* Stop timer 1 */ +#define TGCR_RST1 0x0001 /* Reset timer 1 */ + + +/*----------------------------------------------------------------------- + * Timer Mode Register 18-9 + */ +#define TMR_PS_MSK 0xFF00 /* Prescaler Value */ +#define TMR_PS_SHIFT 8 /* Prescaler position */ +#define TMR_CE_MSK 0x00C0 /* Capture Edge and Enable Interrupt */ +#define TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */ +#define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ +#define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ +#define TMR_CE_ANY 0x00C0 /* Capture on any TINx edge */ +#define TMR_OM 0x0020 /* Output Mode */ +#define TMR_ORI 0x0010 /* Output Reference Interrupt Enable */ +#define TMR_FRR 0x0008 /* Free Run/Restart */ +#define TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ +#define TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ +#define TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */ +#define TMR_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16 */ +#define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */ +#define TMR_GE 0x0001 /* Gate Enable */ + + +/*----------------------------------------------------------------------- + * I2C Controller Registers + */ +#define I2MOD_REVD 0x20 /* Reverese Data */ +#define I2MOD_GCD 0x10 /* General Call Disable */ +#define I2MOD_FLT 0x08 /* Clock Filter */ +#define I2MOD_PDIV32 0x00 /* Pre-Divider 32 */ +#define I2MOD_PDIV16 0x02 /* Pre-Divider 16 */ +#define I2MOD_PDIV8 0x04 /* Pre-Divider 8 */ +#define I2MOD_PDIV4 0x06 /* Pre-Divider 4 */ +#define I2MOD_EN 0x01 /* Enable */ + +#define I2CER_TXE 0x10 /* Tx Error */ +#define I2CER_BSY 0x04 /* Busy Condition */ +#define I2CER_TXB 0x02 /* Tx Buffer Transmitted */ +#define I2CER_RXB 0x01 /* Rx Buffer Received */ +#define I2CER_ALL (I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB) + +#define I2COM_STR 0x80 /* Start Transmit */ +#define I2COM_MASTER 0x01 /* Master mode */ + +/*----------------------------------------------------------------------- + * SPI Controller Registers 31-10 + */ +#define SPI_EMASK 0x37 /* Event Mask */ +#define SPI_MME 0x20 /* Multi-Master Error */ +#define SPI_TXE 0x10 /* Transmit Error */ +#define SPI_BSY 0x04 /* Busy */ +#define SPI_TXB 0x02 /* Tx Buffer Empty */ +#define SPI_RXB 0x01 /* RX Buffer full/closed */ + +#define SPI_STR 0x80 /* SPCOM: Start transmit */ + +/*----------------------------------------------------------------------- + * PCMCIA Interface General Control Register 17-12 + */ +#define PCMCIA_GCRX_CXRESET 0x00000040 +#define PCMCIA_GCRX_CXOE 0x00000080 + +#define PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) +#define PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) +#define PCMCIA_VS_MASK(slot) (0xC0000000 >> (slot << 4)) +#define PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) + +#define PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) +#define PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) +#define PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) +#define PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) +#define PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) +#define PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) +#define PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) +#define PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) +#define PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) +#define PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) +#define PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) + +/*----------------------------------------------------------------------- + * PCMCIA Option Register Definitions + * + * Bank Sizes: + */ +#define PCMCIA_BSIZE_1 0x00000000 /* Bank size: 1 Bytes */ +#define PCMCIA_BSIZE_2 0x08000000 /* Bank size: 2 Bytes */ +#define PCMCIA_BSIZE_4 0x18000000 /* Bank size: 4 Bytes */ +#define PCMCIA_BSIZE_8 0x10000000 /* Bank size: 8 Bytes */ +#define PCMCIA_BSIZE_16 0x30000000 /* Bank size: 16 Bytes */ +#define PCMCIA_BSIZE_32 0x38000000 /* Bank size: 32 Bytes */ +#define PCMCIA_BSIZE_64 0x28000000 /* Bank size: 64 Bytes */ +#define PCMCIA_BSIZE_128 0x20000000 /* Bank size: 128 Bytes */ +#define PCMCIA_BSIZE_256 0x60000000 /* Bank size: 256 Bytes */ +#define PCMCIA_BSIZE_512 0x68000000 /* Bank size: 512 Bytes */ +#define PCMCIA_BSIZE_1K 0x78000000 /* Bank size: 1 kB */ +#define PCMCIA_BSIZE_2K 0x70000000 /* Bank size: 2 kB */ +#define PCMCIA_BSIZE_4K 0x50000000 /* Bank size: 4 kB */ +#define PCMCIA_BSIZE_8K 0x58000000 /* Bank size: 8 kB */ +#define PCMCIA_BSIZE_16K 0x48000000 /* Bank size: 16 kB */ +#define PCMCIA_BSIZE_32K 0x40000000 /* Bank size: 32 kB */ +#define PCMCIA_BSIZE_64K 0xC0000000 /* Bank size: 64 kB */ +#define PCMCIA_BSIZE_128K 0xC8000000 /* Bank size: 128 kB */ +#define PCMCIA_BSIZE_256K 0xD8000000 /* Bank size: 256 kB */ +#define PCMCIA_BSIZE_512K 0xD0000000 /* Bank size: 512 kB */ +#define PCMCIA_BSIZE_1M 0xF0000000 /* Bank size: 1 MB */ +#define PCMCIA_BSIZE_2M 0xF8000000 /* Bank size: 2 MB */ +#define PCMCIA_BSIZE_4M 0xE8000000 /* Bank size: 4 MB */ +#define PCMCIA_BSIZE_8M 0xE0000000 /* Bank size: 8 MB */ +#define PCMCIA_BSIZE_16M 0xA0000000 /* Bank size: 16 MB */ +#define PCMCIA_BSIZE_32M 0xA8000000 /* Bank size: 32 MB */ +#define PCMCIA_BSIZE_64M 0xB8000000 /* Bank size: 64 MB */ + +/* PCMCIA Timing */ +#define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */ +#define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */ +#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */ + +/* PCMCIA Port Sizes */ +#define PCMCIA_PPS_8 0x00000000 /* 8 bit port size */ +#define PCMCIA_PPS_16 0x00000040 /* 16 bit port size */ + +/* PCMCIA Region Select */ +#define PCMCIA_PRS_MEM 0x00000000 /* Common Memory Space */ +#define PCMCIA_PRS_ATTR 0x00000010 /* Attribute Space */ +#define PCMCIA_PRS_IO 0x00000018 /* I/O Space */ +#define PCMCIA_PRS_DMA 0x00000020 /* DMA, normal transfer */ +#define PCMCIA_PRS_DMA_LAST 0x00000028 /* DMA, last transactn */ +#define PCMCIA_PRS_CEx 0x00000030 /* A[22:23] ==> CE1,CE2 */ + +#define PCMCIA_PSLOT_A 0x00000000 /* Slot A */ +#define PCMCIA_PSLOT_B 0x00000004 /* Slot B */ +#define PCMCIA_WPROT 0x00000002 /* Write Protect */ +#define PCMCIA_PV 0x00000001 /* Valid Bit */ + +#define UPMA 0x00000000 +#define UPMB 0x00800000 + +#endif /* __MPCXX_H__ */ diff --git a/include/mpc8xx_irq.h b/include/mpc8xx_irq.h new file mode 100644 index 0000000..d2a81c0 --- /dev/null +++ b/include/mpc8xx_irq.h @@ -0,0 +1,59 @@ +#ifndef _MPC8XX_IRQ_H +#define _MPC8XX_IRQ_H + +/* The MPC8xx cores have 16 possible interrupts. There are eight + * possible level sensitive interrupts assigned and generated internally + * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. + * There are eight external interrupts (IRQs) that can be configured + * as either level or edge sensitive. + * + * On some implementations, there is also the possibility of an 8259 + * through the PCI and PCI-ISA bridges. + * + * We don't support the 8259 (yet). + */ +#define NR_SIU_INTS 16 +#define NR_8259_INTS 0 + +#define NR_IRQS (NR_SIU_INTS + NR_8259_INTS) + +/* These values must be zero-based and map 1:1 with the SIU configuration. + * They are used throughout the 8xx I/O subsystem to generate + * interrupt masks, flags, and other control patterns. This is why the + * current kernel assumption of the 8259 as the base controller is such + * a pain in the butt. + */ +#define SIU_IRQ0 (0) /* Highest priority */ +#define SIU_LEVEL0 (1) +#define SIU_IRQ1 (2) +#define SIU_LEVEL1 (3) +#define SIU_IRQ2 (4) +#define SIU_LEVEL2 (5) +#define SIU_IRQ3 (6) +#define SIU_LEVEL3 (7) +#define SIU_IRQ4 (8) +#define SIU_LEVEL4 (9) +#define SIU_IRQ5 (10) +#define SIU_LEVEL5 (11) +#define SIU_IRQ6 (12) +#define SIU_LEVEL6 (13) +#define SIU_IRQ7 (14) +#define SIU_LEVEL7 (15) + +/* The internal interrupts we can configure as we see fit. + * My personal preference is CPM at level 2, which puts it above the + * MBX PCI/ISA/IDE interrupts. + */ + +#ifdef CFG_CPM_INTERRUPT +# define CPM_INTERRUPT CFG_CPM_INTERRUPT +#else +# define CPM_INTERRUPT SIU_LEVEL2 +#endif + +/* Some internal interrupt registers use an 8-bit mask for the interrupt + * level instead of a number. + */ +#define mk_int_int_mask(IL) (1 << (7 - (IL/2))) + +#endif /* _MPC8XX_IRQ_H */ diff --git a/include/net.h b/include/net.h new file mode 100644 index 0000000..461e038 --- /dev/null +++ b/include/net.h @@ -0,0 +1,461 @@ +/* + * LiMon Monitor (LiMon) - Network. + * + * Copyright 1994 - 2000 Neil Russell. + * (See License) + * + * + * History + * 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added + */ + +#ifndef __NET_H__ +#define __NET_H__ + +#if defined(CONFIG_8xx) +#include +# if !defined(CONFIG_NET_MULTI) +# if defined(FEC_ENET) || defined(SCC_ENET) +# define CONFIG_NET_MULTI +# endif +# endif +#endif /* CONFIG_8xx */ + +#if defined(CONFIG_MPC5xxx) +# if !defined(CONFIG_NET_MULTI) +# if defined(CONFIG_MPC5xxx_FEC) +# define CONFIG_NET_MULTI +# endif +# endif +#endif /* CONFIG_MPC5xxx */ + +#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_CPM2) +#include +#if defined(CONFIG_ETHER_ON_FCC) +#if defined(CONFIG_ETHER_ON_SCC) +#error "Ethernet not correctly defined" +#endif /* CONFIG_ETHER_ON_SCC */ +#define CONFIG_NET_MULTI +#if (CONFIG_ETHER_INDEX == 1) +#define CONFIG_ETHER_ON_FCC1 +# define CFG_CMXFCR_MASK1 CFG_CMXFCR_MASK +# define CFG_CMXFCR_VALUE1 CFG_CMXFCR_VALUE +#elif (CONFIG_ETHER_INDEX == 2) +#define CONFIG_ETHER_ON_FCC2 +# define CFG_CMXFCR_MASK2 CFG_CMXFCR_MASK +# define CFG_CMXFCR_VALUE2 CFG_CMXFCR_VALUE +#elif (CONFIG_ETHER_INDEX == 3) +#define CONFIG_ETHER_ON_FCC3 +# define CFG_CMXFCR_MASK3 CFG_CMXFCR_MASK +# define CFG_CMXFCR_VALUE3 CFG_CMXFCR_VALUE +#endif /* CONFIG_ETHER_INDEX */ +#endif /* CONFIG_ETHER_ON_FCC */ +#endif /* !CONFIG_NET_MULTI && CONFIG_8260 */ + +#include /* for nton* / ntoh* stuff */ + + +/* + * The number of receive packet buffers, and the required packet buffer + * alignment in memory. + * + */ + +#ifdef CFG_RX_ETH_BUFFER +# define PKTBUFSRX CFG_RX_ETH_BUFFER +#else +# define PKTBUFSRX 4 +#endif + +#define PKTALIGN 32 + +typedef ulong IPaddr_t; + + +/* + * The current receive packet handler. Called with a pointer to the + * application packet, and a protocol type (PORT_BOOTPC or PORT_TFTP). + * All other packets are dealt with without calling the handler. + */ +typedef void rxhand_f(uchar *, unsigned, unsigned, unsigned); + +/* + * A timeout handler. Called after time interval has expired. + */ +typedef void thand_f(void); + +#define NAMESIZE 16 + +enum eth_state_t { + ETH_STATE_INIT, + ETH_STATE_PASSIVE, + ETH_STATE_ACTIVE +}; + +struct eth_device { + char name[NAMESIZE]; + unsigned char enetaddr[6]; + int iobase; + int state; + + int (*init) (struct eth_device*, bd_t*); + int (*send) (struct eth_device*, volatile void* pachet, int length); + int (*recv) (struct eth_device*); + void (*halt) (struct eth_device*); + + struct eth_device *next; + void *priv; +}; + +extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */ +extern int eth_register(struct eth_device* dev);/* Register network device */ +extern void eth_try_another(int first_restart); /* Change the device */ +#ifdef CONFIG_NET_MULTI +extern void eth_set_current(void); /* set nterface to ethcur var. */ +#endif +extern struct eth_device *eth_get_dev(void); /* get the current device MAC */ +extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */ +extern int eth_get_dev_index (void); /* get the device index */ +extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */ + +extern int eth_init(bd_t *bis); /* Initialize the device */ +extern int eth_send(volatile void *packet, int length); /* Send a packet */ +extern int eth_rx(void); /* Check for received packets */ +extern void eth_halt(void); /* stop SCC */ +extern char *eth_get_name(void); /* get name of current device */ + + +/**********************************************************************/ +/* + * Protocol headers. + */ + +/* + * Ethernet header + */ +typedef struct { + uchar et_dest[6]; /* Destination node */ + uchar et_src[6]; /* Source node */ + ushort et_protlen; /* Protocol or length */ + uchar et_dsap; /* 802 DSAP */ + uchar et_ssap; /* 802 SSAP */ + uchar et_ctl; /* 802 control */ + uchar et_snap1; /* SNAP */ + uchar et_snap2; + uchar et_snap3; + ushort et_prot; /* 802 protocol */ +} Ethernet_t; + +#define ETHER_HDR_SIZE 14 /* Ethernet header size */ +#define E802_HDR_SIZE 22 /* 802 ethernet header size */ + +/* + * Ethernet header + */ +typedef struct { + uchar vet_dest[6]; /* Destination node */ + uchar vet_src[6]; /* Source node */ + ushort vet_vlan_type; /* PROT_VLAN */ + ushort vet_tag; /* TAG of VLAN */ + ushort vet_type; /* protocol type */ +} VLAN_Ethernet_t; + +#define VLAN_ETHER_HDR_SIZE 18 /* VLAN Ethernet header size */ + +#define PROT_IP 0x0800 /* IP protocol */ +#define PROT_ARP 0x0806 /* IP ARP protocol */ +#define PROT_RARP 0x8035 /* IP ARP protocol */ +#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */ + +#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */ +#define IPPROTO_UDP 17 /* User Datagram Protocol */ + +/* + * Internet Protocol (IP) header. + */ +typedef struct { + uchar ip_hl_v; /* header length and version */ + uchar ip_tos; /* type of service */ + ushort ip_len; /* total length */ + ushort ip_id; /* identification */ + ushort ip_off; /* fragment offset field */ + uchar ip_ttl; /* time to live */ + uchar ip_p; /* protocol */ + ushort ip_sum; /* checksum */ + IPaddr_t ip_src; /* Source IP address */ + IPaddr_t ip_dst; /* Destination IP address */ + ushort udp_src; /* UDP source port */ + ushort udp_dst; /* UDP destination port */ + ushort udp_len; /* Length of UDP packet */ + ushort udp_xsum; /* Checksum */ +} IP_t; + +#define IP_HDR_SIZE_NO_UDP (sizeof (IP_t) - 8) +#define IP_HDR_SIZE (sizeof (IP_t)) + + +/* + * Address Resolution Protocol (ARP) header. + */ +typedef struct +{ + ushort ar_hrd; /* Format of hardware address */ +# define ARP_ETHER 1 /* Ethernet hardware address */ + ushort ar_pro; /* Format of protocol address */ + uchar ar_hln; /* Length of hardware address */ + uchar ar_pln; /* Length of protocol address */ + ushort ar_op; /* Operation */ +# define ARPOP_REQUEST 1 /* Request to resolve address */ +# define ARPOP_REPLY 2 /* Response to previous request */ + +# define RARPOP_REQUEST 3 /* Request to resolve address */ +# define RARPOP_REPLY 4 /* Response to previous request */ + + /* + * The remaining fields are variable in size, according to + * the sizes above, and are defined as appropriate for + * specific hardware/protocol combinations. + */ + uchar ar_data[0]; +#if 0 + uchar ar_sha[]; /* Sender hardware address */ + uchar ar_spa[]; /* Sender protocol address */ + uchar ar_tha[]; /* Target hardware address */ + uchar ar_tpa[]; /* Target protocol address */ +#endif /* 0 */ +} ARP_t; + +#define ARP_HDR_SIZE (8+20) /* Size assuming ethernet */ + +/* + * ICMP stuff (just enough to handle (host) redirect messages) + */ +#define ICMP_ECHO_REPLY 0 /* Echo reply */ +#define ICMP_REDIRECT 5 /* Redirect (change route) */ +#define ICMP_ECHO_REQUEST 8 /* Echo request */ + +/* Codes for REDIRECT. */ +#define ICMP_REDIR_NET 0 /* Redirect Net */ +#define ICMP_REDIR_HOST 1 /* Redirect Host */ + +typedef struct icmphdr { + uchar type; + uchar code; + ushort checksum; + union { + struct { + ushort id; + ushort sequence; + } echo; + ulong gateway; + struct { + ushort __unused; + ushort mtu; + } frag; + } un; +} ICMP_t; + + +/* + * Maximum packet size; used to allocate packet storage. + * TFTP packets can be 524 bytes + IP header + ethernet header. + * Lets be conservative, and go for 38 * 16. (Must also be + * a multiple of 32 bytes). + */ +/* + * AS.HARNOIS : Better to set PKTSIZE to maximum size because + * traffic type is not always controlled + * maximum packet size = 1518 + * maximum packet size and multiple of 32 bytes = 1536 + */ +#define PKTSIZE 1518 +#define PKTSIZE_ALIGN 1536 +/*#define PKTSIZE 608*/ + +/* + * Maximum receive ring size; that is, the number of packets + * we can buffer before overflow happens. Basically, this just + * needs to be enough to prevent a packet being discarded while + * we are processing the previous one. + */ +#define RINGSZ 4 +#define RINGSZ_LOG2 2 + +/**********************************************************************/ +/* + * Globals. + * + * Note: + * + * All variables of type IPaddr_t are stored in NETWORK byte order + * (big endian). + */ + +/* net.c */ +/** BOOTP EXTENTIONS **/ +extern IPaddr_t NetOurGatewayIP; /* Our gateway IP addresse */ +extern IPaddr_t NetOurSubnetMask; /* Our subnet mask (0 = unknown)*/ +extern IPaddr_t NetOurDNSIP; /* Our Domain Name Server (0 = unknown)*/ +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) +extern IPaddr_t NetOurDNS2IP; /* Our 2nd Domain Name Server (0 = unknown)*/ +#endif +extern char NetOurNISDomain[32]; /* Our NIS domain */ +extern char NetOurHostName[32]; /* Our hostname */ +extern char NetOurRootPath[64]; /* Our root path */ +extern ushort NetBootFileSize; /* Our boot file size in blocks */ +/** END OF BOOTP EXTENTIONS **/ +extern ulong NetBootFileXferSize; /* size of bootfile in bytes */ +extern uchar NetOurEther[6]; /* Our ethernet address */ +extern uchar NetServerEther[6]; /* Boot server enet address */ +extern IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */ +extern IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */ +extern volatile uchar * NetTxPacket; /* THE transmit packet */ +extern volatile uchar * NetRxPackets[PKTBUFSRX];/* Receive packets */ +extern volatile uchar * NetRxPkt; /* Current receive packet */ +extern int NetRxPktLen; /* Current rx packet length */ +extern unsigned NetIPID; /* IP ID (counting) */ +extern uchar NetBcastAddr[6]; /* Ethernet boardcast address */ +extern uchar NetEtherNullAddr[6]; + +#define VLAN_NONE 4095 /* untagged */ +#define VLAN_IDMASK 0x0fff /* mask of valid vlan id */ +extern ushort NetOurVLAN; /* Our VLAN */ +extern ushort NetOurNativeVLAN; /* Our Native VLAN */ + +extern uchar NetCDPAddr[6]; /* Ethernet CDP address */ +extern ushort CDPNativeVLAN; /* CDP returned native VLAN */ +extern ushort CDPApplianceVLAN; /* CDP returned appliance VLAN */ + +extern int NetState; /* Network loop state */ +#define NETLOOP_CONTINUE 1 +#define NETLOOP_RESTART 2 +#define NETLOOP_SUCCESS 3 +#define NETLOOP_FAIL 4 + +#ifdef CONFIG_NET_MULTI +extern int NetRestartWrap; /* Tried all network devices */ +#endif + +typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP } proto_t; + +/* from net/net.c */ +extern char BootFile[128]; /* Boot File name */ + +#if (CONFIG_COMMANDS & CFG_CMD_PING) +extern IPaddr_t NetPingIP; /* the ip address to ping */ +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_CDP) +/* when CDP completes these hold the return values */ +extern ushort CDPNativeVLAN; +extern ushort CDPApplianceVLAN; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) +extern IPaddr_t NetNtpServerIP; /* the ip address to NTP */ +extern int NetTimeOffset; /* offset time from UTC */ +#endif + +/* Initialize the network adapter */ +extern int NetLoop(proto_t); + +/* Shutdown adapters and cleanup */ +extern void NetStop(void); + +/* Load failed. Start again. */ +extern void NetStartAgain(void); + +/* Get size of the ethernet header when we send */ +extern int NetEthHdrSize(void); + +/* Set ethernet header; returns the size of the header */ +extern int NetSetEther(volatile uchar *, uchar *, uint); + +/* Set IP header */ +extern void NetSetIP(volatile uchar *, IPaddr_t, int, int, int); + +/* Checksum */ +extern int NetCksumOk(uchar *, int); /* Return true if cksum OK */ +extern uint NetCksum(uchar *, int); /* Calculate the checksum */ + +/* Set callbacks */ +extern void NetSetHandler(rxhand_f *); /* Set RX packet handler */ +extern void NetSetTimeout(ulong, thand_f *);/* Set timeout handler */ + +/* Transmit "NetTxPacket" */ +extern void NetSendPacket(volatile uchar *, int); + +/* Transmit UDP packet, performing ARP request if needed */ +extern int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len); + +/* Processes a received packet */ +extern void NetReceive(volatile uchar *, int); + +/* Print an IP address on the console */ +extern void print_IPaddr (IPaddr_t); + +/* + * The following functions are a bit ugly, but necessary to deal with + * alignment restrictions on ARM. + * + * We're using inline functions, which had the smallest memory + * footprint in our tests. + */ +/* return IP *in network byteorder* */ +static inline IPaddr_t NetReadIP(void *from) +{ + IPaddr_t ip; + memcpy((void*)&ip, from, sizeof(ip)); + return ip; +} + +/* return ulong *in network byteorder* */ +static inline ulong NetReadLong(ulong *from) +{ + ulong l; + memcpy((void*)&l, (void*)from, sizeof(l)); + return l; +} + +/* write IP *in network byteorder* */ +static inline void NetWriteIP(void *to, IPaddr_t ip) +{ + memcpy(to, (void*)&ip, sizeof(ip)); +} + +/* copy IP */ +static inline void NetCopyIP(void *to, void *from) +{ + memcpy(to, from, sizeof(IPaddr_t)); +} + +/* copy ulong */ +static inline void NetCopyLong(ulong *to, ulong *from) +{ + memcpy((void*)to, (void*)from, sizeof(ulong)); +} + +/* Convert an IP address to a string */ +extern void ip_to_string (IPaddr_t x, char *s); + +/* Convert a string to ip address */ +extern IPaddr_t string_to_ip(char *s); + +/* Convert a VLAN id to a string */ +extern void VLAN_to_string (ushort x, char *s); + +/* Convert a string to a vlan id */ +extern ushort string_to_VLAN(char *s); + +/* read an IP address from a environment variable */ +extern IPaddr_t getenv_IPaddr (char *); + +/* read a VLAN id from an environment variable */ +extern ushort getenv_VLAN(char *); + +/* copy a filename (allow for "..." notation, limit length) */ +extern void copy_filename (char *dst, char *src, int size); + +/**********************************************************************/ + +#endif /* __NET_H__ */ diff --git a/include/nios-io.h b/include/nios-io.h new file mode 100644 index 0000000..dc7e127 --- /dev/null +++ b/include/nios-io.h @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera Nios Standard Peripherals + ************************************************************************/ + +#ifndef __NIOSIO_H__ +#define __NIOSIO_H__ + +/*------------------------------------------------------------------------ + * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_uart_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned divisor; /* Baud rate divisor reg */ + unsigned endofpacket; /* End-of-packet reg */ +}nios_uart_t; + +/* status register */ +#define NIOS_UART_PE (1 << 0) /* parity error */ +#define NIOS_UART_FE (1 << 1) /* frame error */ +#define NIOS_UART_BRK (1 << 2) /* break detect */ +#define NIOS_UART_ROE (1 << 3) /* rx overrun */ +#define NIOS_UART_TOE (1 << 4) /* tx overrun */ +#define NIOS_UART_TMT (1 << 5) /* tx empty */ +#define NIOS_UART_TRDY (1 << 6) /* tx ready */ +#define NIOS_UART_RRDY (1 << 7) /* rx ready */ +#define NIOS_UART_E (1 << 8) /* exception */ +#define NIOS_UART_DCTS (1 << 10) /* cts change */ +#define NIOS_UART_CTS (1 << 11) /* cts */ +#define NIOS_UART_EOP (1 << 12) /* eop detected */ + +/* control register */ +#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ +#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ +#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ +#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ +#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_UART_IE (1 << 8) /* exception int ena */ +#define NIOS_UART_TBRK (1 << 9) /* transmit break */ +#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ +#define NIOS_UART_RTS (1 << 11) /* rts */ +#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ + + +/*------------------------------------------------------------------------ + * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_timer_t { + unsigned status; /* Timer status reg */ + unsigned control; /* Timer control reg */ + unsigned periodl; /* Timeout period low */ + unsigned periodh; /* Timeout period high */ + unsigned snapl; /* Snapshot low */ + unsigned snaph; /* Snapshot high */ +}nios_timer_t; + +/* status register */ +#define NIOS_TIMER_TO (1 << 0) /* Timeout */ +#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ + +/* control register */ +#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ +#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ +#define NIOS_TIMER_START (1 << 2) /* Start timer */ +#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ + + +/*------------------------------------------------------------------------ + * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_pio_t { + unsigned int data; /* Data value at each PIO in/out */ + unsigned int direction; /* Data direct. for each PIO bit */ + unsigned int interruptmask; /* Per-bit IRQ enable/disable */ + unsigned int edgecapture; /* Per-bit sync. edge detect & hold */ +}nios_pio_t; + +/* direction register */ +#define NIOS_PIO_OUT (1) /* PIO bit is output */ +#define NIOS_PIO_IN (0) /* PIO bit is input */ + + +/*------------------------------------------------------------------------ + * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_spi_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned reserved; /* (master only) */ + unsigned slaveselect; /* SPI slave select mask (master only) */ +}nios_spi_t; + +/* status register */ +#define NIOS_SPI_ROE (1 << 3) /* rx overrun */ +#define NIOS_SPI_TOE (1 << 4) /* tx overrun */ +#define NIOS_SPI_TMT (1 << 5) /* tx empty */ +#define NIOS_SPI_TRDY (1 << 6) /* tx ready */ +#define NIOS_SPI_RRDY (1 << 7) /* rx ready */ +#define NIOS_SPI_E (1 << 8) /* exception */ + +/* control register */ +#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_SPI_IE (1 << 8) /* exception int ena */ +#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ + +/*------------------------------------------------------------------------ + * ASMI + *----------------------------------------------------------------------*/ +typedef volatile struct nios_asmi_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned reserved; + unsigned slavesel; /* Slave select */ + unsigned endofpacket; /* End-of-packet reg */ +}nios_asmi_t; + +/* status register */ +#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */ +#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */ +#define NIOS_ASMI_TMT (1 << 5) /* tx empty */ +#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */ +#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */ +#define NIOS_ASMI_E (1 << 8) /* exception */ +#define NIOS_ASMI_EOP (1 << 9) /* eop detected */ + +/* control register */ +#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_ASMI_IE (1 << 8) /* exception int ena */ +#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */ +#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */ + +/*------------------------------------------------------------------------ + * JTAG UART + *----------------------------------------------------------------------*/ +typedef volatile struct nios_jtag_t { + unsigned short rxcntl; /* Rx data/cntl reg */ + unsigned short txcntl; /* Tx data/cntl reg */ + unsigned short errcntl; /* Err dta/cntl reg */ +}nios_jtag_t; + +/* status register */ +#define NIOS_JTAG_TRDY (1 << 8) /* tx ready bit */ +#define NIOS_JTAG_RRDY (1 << 8) /* rx ready bit */ + +#endif /* __NIOSIO_H__ */ diff --git a/include/nios.h b/include/nios.h new file mode 100644 index 0000000..46b685a --- /dev/null +++ b/include/nios.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __NIOS_H__ +#define __NIOS_H__ + +/*------------------------------------------------------------------------ + * Control registers -- use with wrctl() & rdctl() + *----------------------------------------------------------------------*/ +#define CTL_STATUS 0x00 /* Processor status */ +#define CTL_ISTATUS 0x01 /* Saved status (exception) */ +#define CTL_WVALID 0x02 /* Valid window limit */ +#define CTL_ICACHE 0x05 /* I-cache line-invalidate */ +#define CTL_CPU_ID 0x06 /* CPU version id */ +#define CTL_DCACHE 0x07 /* D-cache line-invalidate */ +#define CTL_CLR_IE 0x08 /* Interrupt clear (disable) */ +#define CTL_SET_IE 0x09 /* Interrupt set (enable) */ + +/*------------------------------------------------------------------------ + * Access to control regs + *----------------------------------------------------------------------*/ +#define _str_(s) #s + +#define rdctl(reg)\ + ({unsigned int val;\ + asm volatile( "pfx " _str_(reg) "\n\t rdctl %0"\ + : "=r" (val) ); val;}) + +#define wrctl(reg,val)\ + asm volatile( "pfx " _str_(reg) "\n\t wrctl %0 \n\t nop"\ + : : "r" (val)) + +/*------------------------------------------------------------------------ + * Control reg bit masks + *----------------------------------------------------------------------*/ +#define STATUS_DC (1<<17) /* Data cache enable */ +#define STATUS_IC (1<<16) /* Instruction cache enable */ +#define STATUS_IE (1<<15) /* Interrupt enable */ +#define STATUS_IPRI (0x3f<<9) /* Interrupt priority */ +#define STATUS_CWP (0x1f<<4) /* Current window pointer */ +#define STATUS_N (1<<3) /* Condition code: negative */ +#define STATUS_V (1<<2) /* Condition code: overflow */ +#define STATUS_Z (1<<1) /* Condition code: zero */ +#define STATUS_C (1<<0) /* Condition code: carry/borrow */ + +static inline unsigned ipri( unsigned prio ) +{ + unsigned tmp; + unsigned status = rdctl(CTL_STATUS); + prio = (prio << 9) & STATUS_IPRI; + tmp = (status & ~STATUS_IPRI) | prio; + wrctl(CTL_STATUS,tmp); + return( (status & STATUS_IPRI) >> 9); +} + + +#endif /* __NIOS_H__ */ diff --git a/include/nios2-epcs.h b/include/nios2-epcs.h new file mode 100644 index 0000000..2c9522c --- /dev/null +++ b/include/nios2-epcs.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera Nios-II EPCS Controller Core interfaces + ************************************************************************/ + +#ifndef __NIOS2_EPCS_H__ +#define __NIOS2_EPCS_H__ + +typedef struct epcs_devinfo_t { + const char *name; /* Device name */ + unsigned char id; /* Device silicon id */ + unsigned char size; /* Total size log2(bytes)*/ + unsigned char num_sects; /* Number of sectors */ + unsigned char sz_sect; /* Sector size log2(bytes) */ + unsigned char sz_page; /* Page size log2(bytes) */ + unsigned char prot_mask; /* Protection mask */ +}epcs_devinfo_t; + +/* Returns the devinfo struct if EPCS device is found; + * NULL otherwise. + */ +extern epcs_devinfo_t *epcs_dev_find (void); + +/* Returns the number of bytes used by config data. + * Negative on error. + */ +extern int epcs_cfgsz (void); + +/* Erase sectors 'start' to 'end' - return zero on success + */ +extern int epcs_erase (unsigned start, unsigned end); + +/* Read 'cnt' bytes from device offset 'off' into buf at 'addr' + * Zero return on success + */ +extern int epcs_read (ulong addr, ulong off, ulong cnt); + +/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'. + * Zero return on success + */ +extern int epcs_write (ulong addr, ulong off, ulong cnt); + +/* Verify 'cnt' bytes at device offset 'off' comparing with buf + * at 'addr'. On failure, write first invalid offset to *err. + * Zero return on success + */ +extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err); + +#endif /* __NIOS2_EPCS_H__ */ diff --git a/include/nios2-io.h b/include/nios2-io.h new file mode 100644 index 0000000..d5c8652 --- /dev/null +++ b/include/nios2-io.h @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera Nios2 Standard Peripherals + ************************************************************************/ + +#ifndef __NIOS2IO_H__ +#define __NIOS2IO_H__ + +/*------------------------------------------------------------------------ + * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_uart_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned divisor; /* Baud rate divisor reg */ + unsigned endofpacket; /* End-of-packet reg */ +}nios_uart_t; + +/* status register */ +#define NIOS_UART_PE (1 << 0) /* parity error */ +#define NIOS_UART_FE (1 << 1) /* frame error */ +#define NIOS_UART_BRK (1 << 2) /* break detect */ +#define NIOS_UART_ROE (1 << 3) /* rx overrun */ +#define NIOS_UART_TOE (1 << 4) /* tx overrun */ +#define NIOS_UART_TMT (1 << 5) /* tx empty */ +#define NIOS_UART_TRDY (1 << 6) /* tx ready */ +#define NIOS_UART_RRDY (1 << 7) /* rx ready */ +#define NIOS_UART_E (1 << 8) /* exception */ +#define NIOS_UART_DCTS (1 << 10) /* cts change */ +#define NIOS_UART_CTS (1 << 11) /* cts */ +#define NIOS_UART_EOP (1 << 12) /* eop detected */ + +/* control register */ +#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ +#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ +#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ +#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ +#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_UART_IE (1 << 8) /* exception int ena */ +#define NIOS_UART_TBRK (1 << 9) /* transmit break */ +#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ +#define NIOS_UART_RTS (1 << 11) /* rts */ +#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ + + +/*------------------------------------------------------------------------ + * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_timer_t { + unsigned status; /* Timer status reg */ + unsigned control; /* Timer control reg */ + unsigned periodl; /* Timeout period low */ + unsigned periodh; /* Timeout period high */ + unsigned snapl; /* Snapshot low */ + unsigned snaph; /* Snapshot high */ +}nios_timer_t; + +/* status register */ +#define NIOS_TIMER_TO (1 << 0) /* Timeout */ +#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ + +/* control register */ +#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ +#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ +#define NIOS_TIMER_START (1 << 2) /* Start timer */ +#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ + + +/*------------------------------------------------------------------------ + * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_pio_t { + unsigned int data; /* Data value at each PIO in/out */ + unsigned int direction; /* Data direct. for each PIO bit */ + unsigned int interruptmask; /* Per-bit IRQ enable/disable */ + unsigned int edgecapture; /* Per-bit sync. edge detect & hold */ +}nios_pio_t; + +/* direction register */ +#define NIOS_PIO_OUT (1) /* PIO bit is output */ +#define NIOS_PIO_IN (0) /* PIO bit is input */ + + +/*------------------------------------------------------------------------ + * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf) + *----------------------------------------------------------------------*/ +typedef volatile struct nios_spi_t { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned reserved; /* (master only) */ + unsigned slaveselect; /* SPI slave select mask (master only) */ +}nios_spi_t; + +/* status register */ +#define NIOS_SPI_ROE (1 << 3) /* rx overrun */ +#define NIOS_SPI_TOE (1 << 4) /* tx overrun */ +#define NIOS_SPI_TMT (1 << 5) /* tx empty */ +#define NIOS_SPI_TRDY (1 << 6) /* tx ready */ +#define NIOS_SPI_RRDY (1 << 7) /* rx ready */ +#define NIOS_SPI_E (1 << 8) /* exception */ + +/* control register */ +#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_SPI_IE (1 << 8) /* exception int ena */ +#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ + +/*------------------------------------------------------------------------ + * JTAG UART + *----------------------------------------------------------------------*/ +typedef volatile struct nios_jtag_t { + unsigned data; /* Data register */ + unsigned control; /* Control register */ +}nios_jtag_t; + +/* data register */ +#define NIOS_JTAG_RVALID (1<<15) /* Read valid */ +#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */ +#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */ + +/* control register */ +#define NIOS_JTAG_RE (1 << 0) /* read intr enable */ +#define NIOS_JTAG_WE (1 << 1) /* write intr enable */ +#define NIOS_JTAG_RI (1 << 8) /* read intr pending */ +#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/ +#define NIOS_JTAG_AC (1 << 10) /* activity indicator */ +#define NIOS_JTAG_RRDY (1 << 12) /* read available */ +#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ + +/*------------------------------------------------------------------------ + * SYSTEM ID + *----------------------------------------------------------------------*/ +typedef volatile struct nios_sysid_t { + unsigned id; /* The system build id*/ + unsigned timestamp; /* Timestamp */ +}nios_sysid_t; + +#endif /* __NIOS2IO_H__ */ diff --git a/include/nios2.h b/include/nios2.h new file mode 100644 index 0000000..54954e3 --- /dev/null +++ b/include/nios2.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __NIOS2_H__ +#define __NIOS2_H__ + +/*------------------------------------------------------------------------ + * Control registers -- use with wrctl() & rdctl() + *----------------------------------------------------------------------*/ +#define CTL_STATUS 0 /* Processor status reg */ +#define CTL_ESTATUS 1 /* Exception status reg */ +#define CTL_BSTATUS 2 /* Break status reg */ +#define CTL_IENABLE 3 /* Interrut enable reg */ +#define CTL_IPENDING 4 /* Interrut pending reg */ + +/*------------------------------------------------------------------------ + * Access to control regs + *----------------------------------------------------------------------*/ +#define _str_(x) #x + +#define rdctl(reg)\ + ({unsigned int val;\ + asm volatile( "rdctl %0, ctl" _str_(reg)\ + : "=r" (val) ); val;}) + +#define wrctl(reg,val)\ + asm volatile( "wrctl ctl" _str_(reg) ",%0"\ + : : "r" (val)) + +/*------------------------------------------------------------------------ + * Control reg bit masks + *----------------------------------------------------------------------*/ +#define STATUS_IE (1<<0) /* Interrupt enable */ +#define STATUS_U (1<<1) /* User-mode */ + +/*------------------------------------------------------------------------ + * Bit-31 Cache bypass -- only valid for data access. When data cache + * is not implemented, bit 31 is ignored for compatibility. + *----------------------------------------------------------------------*/ +#define CACHE_BYPASS(a) ((a) | 0x80000000) +#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) + +#endif /* __NIOS2_H__ */ diff --git a/include/ns16550.h b/include/ns16550.h new file mode 100644 index 0000000..e17a11e --- /dev/null +++ b/include/ns16550.h @@ -0,0 +1,137 @@ +/* + * NS16550 Serial Port + * originally from linux source (arch/ppc/boot/ns16550.h) + * modified slightly to + * have addresses as offsets from CFG_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + */ + +#if (CFG_NS16550_REG_SIZE == 1) +struct NS16550 { + unsigned char rbr; /* 0 */ + unsigned char ier; /* 1 */ + unsigned char fcr; /* 2 */ + unsigned char lcr; /* 3 */ + unsigned char mcr; /* 4 */ + unsigned char lsr; /* 5 */ + unsigned char msr; /* 6 */ + unsigned char scr; /* 7 */ +#if defined(CONFIG_OMAP730) + unsigned char mdr1; /* 8 */ + unsigned char reg9; /* 9 */ + unsigned char regA; /* A */ + unsigned char regB; /* B */ + unsigned char regC; /* C */ + unsigned char regD; /* D */ + unsigned char regE; /* E */ + unsigned char regF; /* F */ + unsigned char reg10; /* 10 */ + unsigned char ssr; /* 11*/ +#endif +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == 2) +struct NS16550 { + unsigned short rbr; /* 0 */ + unsigned short ier; /* 1 */ + unsigned short fcr; /* 2 */ + unsigned short lcr; /* 3 */ + unsigned short mcr; /* 4 */ + unsigned short lsr; /* 5 */ + unsigned short msr; /* 6 */ + unsigned short scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == 4) +struct NS16550 { + unsigned long rbr; /* 0 */ + unsigned long ier; /* 1 */ + unsigned long fcr; /* 2 */ + unsigned long lcr; /* 3 */ + unsigned long mcr; /* 4 */ + unsigned long lsr; /* 5 */ + unsigned long msr; /* 6 */ + unsigned long scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == -4) +struct NS16550 { + unsigned char rbr; /* 0 */ + int pad1:24; + unsigned char ier; /* 1 */ + int pad2:24; + unsigned char fcr; /* 2 */ + int pad3:24; + unsigned char lcr; /* 3 */ + int pad4:24; + unsigned char mcr; /* 4 */ + int pad5:24; + unsigned char lsr; /* 5 */ + int pad6:24; + unsigned char msr; /* 6 */ + int pad7:24; + unsigned char scr; /* 7 */ + int pad8:24; +#if defined(CONFIG_OMAP) + unsigned char mdr1; /* mode select reset TL16C750*/ +#endif +#ifdef CONFIG_OMAP1510 + int pad9:24; + unsigned long pad[10]; + unsigned char osc_12m_sel; + int pad10:24; +#endif +} __attribute__ ((packed)); +#else +#error "Please define NS16550 registers size." +#endif + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef volatile struct NS16550 *NS16550_t; + +#define FCR_FIFO_EN 0x01 /* Fifo enable */ +#define FCR_RXSR 0x02 /* Receiver soft reset */ +#define FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_DMA_EN 0x04 +#define MCR_TX_DFR 0x08 + +#define LCR_WLS_MSK 0x03 /* character length slect mask */ +#define LCR_WLS_5 0x00 /* 5 bit character length */ +#define LCR_WLS_6 0x01 /* 6 bit character length */ +#define LCR_WLS_7 0x02 /* 7 bit character length */ +#define LCR_WLS_8 0x03 /* 8 bit character length */ +#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define LCR_PEN 0x08 /* Parity eneble */ +#define LCR_EPS 0x10 /* Even Parity Select */ +#define LCR_STKP 0x20 /* Stick Parity */ +#define LCR_SBRK 0x40 /* Set Break */ +#define LCR_BKSE 0x80 /* Bank select enable */ + +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +#ifdef CONFIG_OMAP1510 +#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */ +#endif + +/* useful defaults for LCR */ +#define LCR_8N1 0x03 + +void NS16550_init (NS16550_t com_port, int baud_divisor); +void NS16550_putc (NS16550_t com_port, char c); +char NS16550_getc (NS16550_t com_port); +int NS16550_tstc (NS16550_t com_port); +void NS16550_reinit (NS16550_t com_port, int baud_divisor); diff --git a/include/ns7520_eth.h b/include/ns7520_eth.h new file mode 100644 index 0000000..5019802 --- /dev/null +++ b/include/ns7520_eth.h @@ -0,0 +1,335 @@ +/*********************************************************************** + * + * Copyright 2003 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id$ + * @Author: Markus Pietrek + * @Descr: Defines the NS7520 ethernet registers. + * Stick with the old ETH prefix names instead going to the + * new EFE names in the manual. + * NS7520_ETH_* refer to NS7520 Hardware + * Reference/January 2003 [1] + * PHY_LXT971_* refer to Intel LXT971 Datasheet + * #249414 Rev. 02 [2] + * Partly derived from netarm_eth_module.h + * + * Modified by Arthur Shipkowski from the + * Linux version to be properly formatted for U-Boot (i.e. no C++ comments) + * + ***********************************************************************/ + +#ifndef FS_NS7520_ETH_H +#define FS_NS7520_ETH_H + +#ifdef CONFIG_DRIVER_NS7520_ETHERNET + +#include "lxt971a.h" + +/* The port addresses */ + +#define NS7520_ETH_MODULE_BASE (0xFF800000) + +#define get_eth_reg_addr(c) \ + ((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c))) +#define NS7520_ETH_EGCR (0x0000) /* Ethernet Gen Control */ +#define NS7520_ETH_EGSR (0x0004) /* Ethernet Gen Status */ +#define NS7520_ETH_FIFO (0x0008) /* FIFO Data */ +#define NS7520_ETH_FIFOL (0x000C) /* FIFO Data Last */ +#define NS7520_ETH_ETSR (0x0010) /* Ethernet Transmit Status */ +#define NS7520_ETH_ERSR (0x0014) /* Ethernet Receive Status */ +#define NS7520_ETH_MAC1 (0x0400) /* MAC Config 1 */ +#define NS7520_ETH_MAC2 (0x0404) /* MAC Config 2 */ +#define NS7520_ETH_IPGT (0x0408) /* Back2Back InterPacket Gap */ +#define NS7520_ETH_IPGR (0x040C) /* non back2back InterPacket Gap */ +#define NS7520_ETH_CLRT (0x0410) /* Collision Window/Retry */ +#define NS7520_ETH_MAXF (0x0414) /* Maximum Frame Register */ +#define NS7520_ETH_SUPP (0x0418) /* PHY Support */ +#define NS7520_ETH_TEST (0x041C) /* Test Register */ +#define NS7520_ETH_MCFG (0x0420) /* MII Management Configuration */ +#define NS7520_ETH_MCMD (0x0424) /* MII Management Command */ +#define NS7520_ETH_MADR (0x0428) /* MII Management Address */ +#define NS7520_ETH_MWTD (0x042C) /* MII Management Write Data */ +#define NS7520_ETH_MRDD (0x0430) /* MII Management Read Data */ +#define NS7520_ETH_MIND (0x0434) /* MII Management Indicators */ +#define NS7520_ETH_SMII (0x0438) /* SMII Status Register */ +#define NS7520_ETH_SA1 (0x0440) /* Station Address 1 */ +#define NS7520_ETH_SA2 (0x0444) /* Station Address 2 */ +#define NS7520_ETH_SA3 (0x0448) /* Station Address 3 */ +#define NS7520_ETH_SAFR (0x05C0) /* Station Address Filter */ +#define NS7520_ETH_HT1 (0x05D0) /* Hash Table 1 */ +#define NS7520_ETH_HT2 (0x05D4) /* Hash Table 2 */ +#define NS7520_ETH_HT3 (0x05D8) /* Hash Table 3 */ +#define NS7520_ETH_HT4 (0x05DC) /* Hash Table 4 */ + +/* EGCR Ethernet General Control Register Bit Fields*/ + +#define NS7520_ETH_EGCR_ERX (0x80000000) /* Enable Receive FIFO */ +#define NS7520_ETH_EGCR_ERXDMA (0x40000000) /* Enable Receive DMA */ +#define NS7520_ETH_EGCR_ERXLNG (0x20000000) /* Accept Long packets */ +#define NS7520_ETH_EGCR_ERXSHT (0x10000000) /* Accept Short packets */ +#define NS7520_ETH_EGCR_ERXREG (0x08000000) /* Enable Receive Data Interrupt */ +#define NS7520_ETH_EGCR_ERFIFOH (0x04000000) /* Enable Receive Half-Full Int */ +#define NS7520_ETH_EGCR_ERXBR (0x02000000) /* Enable Receive buffer ready */ +#define NS7520_ETH_EGCR_ERXBAD (0x01000000) /* Accept bad receive packets */ +#define NS7520_ETH_EGCR_ETX (0x00800000) /* Enable Transmit FIFO */ +#define NS7520_ETH_EGCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ +#define NS7520_ETH_EGCR_ETXWM_R (0x00300000) /* Enable Transmit FIFO mark Reserv */ +#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000) /* Enable Transmit FIFO mark 75% */ +#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000) /* Enable Transmit FIFO mark 50% */ +#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000) /* Enable Transmit FIFO mark 25% */ +#define NS7520_ETH_EGCR_ETXREG (0x00080000) /* Enable Transmit Data Read Int */ +#define NS7520_ETH_EGCR_ETFIFOH (0x00040000) /* Enable Transmit Fifo Half Int */ +#define NS7520_ETH_EGCR_ETXBC (0x00020000) /* Enable Transmit Buffer Compl Int */ +#define NS7520_ETH_EGCR_EFULLD (0x00010000) /* Enable Full Duplex Operation */ +#define NS7520_ETH_EGCR_MODE_MA (0x0000C000) /* Mask */ +#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000) /* 10 Mbps SEEQ ENDEC PHY */ +#define NS7520_ETH_EGCR_MODE_LEV (0x00008000) /* 10 Mbps Level1 ENDEC PHY */ +#define NS7520_ETH_EGCR_RES1 (0x00002000) /* Reserved */ +#define NS7520_ETH_EGCR_RXCINV (0x00001000) /* Invert the receive clock input */ +#define NS7520_ETH_EGCR_TXCINV (0x00000800) /* Invert the transmit clock input */ +#define NS7520_ETH_EGCR_PNA (0x00000400) /* pSOS pNA buffer */ +#define NS7520_ETH_EGCR_MAC_RES (0x00000200) /* MAC Software reset */ +#define NS7520_ETH_EGCR_ITXA (0x00000100) /* Insert Transmit Source Address */ +#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC) /* ENDEC media control bits */ +#define NS7520_ETH_EGCR_EXINT_MA (0x00000003) /* Mask */ +#define NS7520_ETH_EGCR_EXINT_RE (0x00000003) /* Reserved */ +#define NS7520_ETH_EGCR_EXINT_TP (0x00000002) /* TP-PMD Mode */ +#define NS7520_ETH_EGCR_EXINT_10 (0x00000001) /* 10-MBit Mode */ +#define NS7520_ETH_EGCR_EXINT_NO (0x00000000) /* MII normal operation */ + +/* EGSR Ethernet General Status Register Bit Fields*/ + +#define NS7520_ETH_EGSR_RES1 (0xC0000000) /* Reserved */ +#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000) /* Receive FIFO mask */ +#define NS7520_ETH_EGSR_RXFDB_3 (0x30000000) /* Receive FIFO 3 bytes available */ +#define NS7520_ETH_EGSR_RXFDB_2 (0x20000000) /* Receive FIFO 2 bytes available */ +#define NS7520_ETH_EGCR_RXFDB_1 (0x10000000) /* Receive FIFO 1 Bytes available */ +#define NS7520_ETH_EGCR_RXFDB_4 (0x00000000) /* Receive FIFO 4 Bytes available */ +#define NS7520_ETH_EGSR_RXREGR (0x08000000) /* Receive Register Ready */ +#define NS7520_ETH_EGSR_RXFIFOH (0x04000000) /* Receive FIFO Half Full */ +#define NS7520_ETH_EGSR_RXBR (0x02000000) /* Receive Buffer Ready */ +#define NS7520_ETH_EGSR_RXSKIP (0x01000000) /* Receive Buffer Skip */ +#define NS7520_ETH_EGSR_RES2 (0x00F00000) /* Reserved */ +#define NS7520_ETH_EGSR_TXREGE (0x00080000) /* Transmit Register Empty */ +#define NS7520_ETH_EGSR_TXFIFOH (0x00040000) /* Transmit FIFO half empty */ +#define NS7520_ETH_EGSR_TXBC (0x00020000) /* Transmit buffer complete */ +#define NS7520_ETH_EGSR_TXFIFOE (0x00010000) /* Transmit FIFO empty */ +#define NS7520_ETH_EGSR_RXPINS (0x0000FC00) /* ENDEC Phy Status */ +#define NS7520_ETH_EGSR_RES3 (0x000003FF) /* Reserved */ + +/* ETSR Ethernet Transmit Status Register Bit Fields*/ + +#define NS7520_ETH_ETSR_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_ETSR_TXOK (0x00008000) /* Packet transmitted OK */ +#define NS7520_ETH_ETSR_TXBR (0x00004000) /* Broadcast packet transmitted */ +#define NS7520_ETH_ETSR_TXMC (0x00002000) /* Multicast packet transmitted */ +#define NS7520_ETH_ETSR_TXAL (0x00001000) /* Transmit abort - late collision */ +#define NS7520_ETH_ETSR_TXAED (0x00000800) /* Transmit abort - deferral */ +#define NS7520_ETH_ETSR_TXAEC (0x00000400) /* Transmit abort - exc collisions */ +#define NS7520_ETH_ETSR_TXAUR (0x00000200) /* Transmit abort - underrun */ +#define NS7520_ETH_ETSR_TXAJ (0x00000100) /* Transmit abort - jumbo */ +#define NS7520_ETH_ETSR_RES2 (0x00000080) /* Reserved */ +#define NS7520_ETH_ETSR_TXDEF (0x00000040) /* Transmit Packet Deferred */ +#define NS7520_ETH_ETSR_TXCRC (0x00000020) /* Transmit CRC error */ +#define NS7520_ETH_ETSR_RES3 (0x00000010) /* Reserved */ +#define NS7520_ETH_ETSR_TXCOLC (0x0000000F) /* Transmit Collision Count */ + +/* ERSR Ethernet Receive Status Register Bit Fields*/ + +#define NS7520_ETH_ERSR_RXSIZE (0xFFFF0000) /* Receive Buffer Size */ +#define NS7520_ETH_ERSR_RXCE (0x00008000) /* Receive Carrier Event */ +#define NS7520_ETH_ERSR_RXDV (0x00004000) /* Receive Data Violation Event */ +#define NS7520_ETH_ERSR_RXOK (0x00002000) /* Receive Packet OK */ +#define NS7520_ETH_ERSR_RXBR (0x00001000) /* Receive Broadcast Packet */ +#define NS7520_ETH_ERSR_RXMC (0x00000800) /* Receive Multicast Packet */ +#define NS7520_ETH_ERSR_RXCRC (0x00000400) /* Receive Packet has CRC error */ +#define NS7520_ETH_ERSR_RXDR (0x00000200) /* Receive Packet has dribble error */ +#define NS7520_ETH_ERSR_RXCV (0x00000100) /* Receive Packet code violation */ +#define NS7520_ETH_ERSR_RXLNG (0x00000080) /* Receive Packet too long */ +#define NS7520_ETH_ERSR_RXSHT (0x00000040) /* Receive Packet too short */ +#define NS7520_ETH_ERSR_ROVER (0x00000020) /* Recive overflow */ +#define NS7520_ETH_ERSR_RES (0x0000001F) /* Reserved */ + +/* MAC1 MAC Configuration Register 1 Bit Fields*/ + +#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MAC1_SRST (0x00008000) /* Soft Reset */ +#define NS7520_ETH_MAC1_SIMMRST (0x00004000) /* Simulation Reset */ +#define NS7520_ETH_MAC1_RES2 (0x00003000) /* Reserved */ +#define NS7520_ETH_MAC1_RPEMCSR (0x00000800) /* Reset PEMCS/RX */ +#define NS7520_ETH_MAC1_RPERFUN (0x00000400) /* Reset PERFUN */ +#define NS7520_ETH_MAC1_RPEMCST (0x00000200) /* Reset PEMCS/TX */ +#define NS7520_ETH_MAC1_RPETFUN (0x00000100) /* Reset PETFUN */ +#define NS7520_ETH_MAC1_RES3 (0x000000E0) /* Reserved */ +#define NS7520_ETH_MAC1_LOOPBK (0x00000010) /* Internal Loopback */ +#define NS7520_ETH_MAC1_TXFLOW (0x00000008) /* TX flow control */ +#define NS7520_ETH_MAC1_RXFLOW (0x00000004) /* RX flow control */ +#define NS7520_ETH_MAC1_PALLRX (0x00000002) /* Pass ALL receive frames */ +#define NS7520_ETH_MAC1_RXEN (0x00000001) /* Receive enable */ + +/* MAC Configuration Register 2 Bit Fields*/ + +#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */ +#define NS7520_ETH_MAC2_EDEFER (0x00004000) /* Excess Deferral */ +#define NS7520_ETH_MAC2_BACKP (0x00002000) /* Backpressure/NO back off */ +#define NS7520_ETH_MAC2_NOBO (0x00001000) /* No back off */ +#define NS7520_ETH_MAC2_RES2 (0x00000C00) /* Reserved */ +#define NS7520_ETH_MAC2_LONGP (0x00000200) /* Long Preable enforcement */ +#define NS7520_ETH_MAC2_PUREP (0x00000100) /* Pure preamble enforcement */ +#define NS7520_ETH_MAC2_AUTOP (0x00000080) /* Auto detect PAD enable */ +#define NS7520_ETH_MAC2_VLANP (0x00000040) /* VLAN pad enable */ +#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */ +#define NS7520_ETH_MAC2_CRCEN (0x00000010) /* CRC enable */ +#define NS7520_ETH_MAC2_DELCRC (0x00000008) /* Delayed CRC */ +#define NS7520_ETH_MAC2_HUGE (0x00000004) /* Huge frame enable */ +#define NS7520_ETH_MAC2_FLENC (0x00000002) /* Frame length checking */ +#define NS7520_ETH_MAC2_FULLD (0x00000001) /* Full duplex */ + +/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/ + +#define NS7520_ETH_IPGT_RES (0xFFFFFF80) /* Reserved */ +#define NS7520_ETH_IPGT_IPGT (0x0000007F) /* Back-to-Back Interpacket Gap */ + +/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/ + +#define NS7520_ETH_IPGR_RES1 (0xFFFF8000) /* Reserved */ +#define NS7520_ETH_IPGR_IPGR1 (0x00007F00) /* Non Back-to-back Interpacket Gap */ +#define NS7520_ETH_IPGR_RES2 (0x00000080) /* Reserved */ +#define NS7520_ETH_IPGR_IPGR2 (0x0000007F) /* Non back-to-back Interpacket Gap */ + +/* CLRT Collision Windows/Collision Retry Register Bit Fields*/ + +#define NS7520_ETH_CLRT_RES1 (0xFFFFC000) /* Reserved */ +#define NS7520_ETH_CLRT_CWIN (0x00003F00) /* Collision Windows */ +#define NS7520_ETH_CLRT_RES2 (0x000000F0) /* Reserved */ +#define NS7520_ETH_CLRT_RETX (0x0000000F) /* Retransmission maximum */ + +/* MAXF Maximum Frame Register Bit Fields*/ + +#define NS7520_ETH_MAXF_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MAXF_MAXF (0x0000FFFF) /* Maximum frame length */ + +/* SUPP PHY Support Register Bit Fields*/ + +#define NS7520_ETH_SUPP_RES1 (0xFFFFFF00) /* Reserved */ +#define NS7520_ETH_SUPP_RPE100X (0x00000080) /* Reset PE100X module */ +#define NS7520_ETH_SUPP_FORCEQ (0x00000040) /* Force Quit */ +#define NS7520_ETH_SUPP_NOCIPH (0x00000020) /* No Cipher */ +#define NS7520_ETH_SUPP_DLINKF (0x00000010) /* Disable link fail */ +#define NS7520_ETH_SUPP_RPE10T (0x00000008) /* Reset PE10T module */ +#define NS7520_ETH_SUPP_RES2 (0x00000004) /* Reserved */ +#define NS7520_ETH_SUPP_JABBER (0x00000002) /* Enable Jabber protection */ +#define NS7520_ETH_SUPP_BITMODE (0x00000001) /* Bit Mode */ + +/* TEST Register Bit Fields*/ + +#define NS7520_ETH_TEST_RES1 (0xFFFFFFF8) /* Reserved */ +#define NS7520_ETH_TEST_TBACK (0x00000004) /* Test backpressure */ +#define NS7520_ETH_TEST_TPAUSE (0x00000002) /* Test Pause */ +#define NS7520_ETH_TEST_SPQ (0x00000001) /* Shortcut pause quanta */ + +/* MCFG MII Management Configuration Register Bit Fields*/ + +#define NS7520_ETH_MCFG_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MCFG_RMIIM (0x00008000) /* Reset MII management */ +#define NS7520_ETH_MCFG_RES2 (0x00007FE0) /* Reserved */ +#define NS7520_ETH_MCFG_CLKS_MA (0x0000001C) /* Clock Select */ +#define NS7520_ETH_MCFG_CLKS_4 (0x00000004) /* Sysclk / 4 */ +#define NS7520_ETH_MCFG_CLKS_6 (0x00000008) /* Sysclk / 6 */ +#define NS7520_ETH_MCFG_CLKS_8 (0x0000000C) /* Sysclk / 8 */ +#define NS7520_ETH_MCFG_CLKS_10 (0x00000010) /* Sysclk / 10 */ +#define NS7520_ETH_MCFG_CLKS_14 (0x00000014) /* Sysclk / 14 */ +#define NS7520_ETH_MCFG_CLKS_20 (0x00000018) /* Sysclk / 20 */ +#define NS7520_ETH_MCFG_CLKS_28 (0x0000001C) /* Sysclk / 28 */ +#define NS7520_ETH_MCFG_SPRE (0x00000002) /* Suppress preamble */ +#define NS7520_ETH_MCFG_SCANI (0x00000001) /* Scan increment */ + +/* MCMD MII Management Command Register Bit Fields*/ + +#define NS7520_ETH_MCMD_RES1 (0xFFFFFFFC) /* Reserved */ +#define NS7520_ETH_MCMD_SCAN (0x00000002) /* Automatically Scan for Read Data */ +#define NS7520_ETH_MCMD_READ (0x00000001) /* Single scan for Read Data */ + +/* MCMD MII Management Address Register Bit Fields*/ + +#define NS7520_ETH_MADR_RES1 (0xFFFFE000) /* Reserved */ +#define NS7520_ETH_MADR_DADR (0x00001F00) /* MII PHY device address */ +#define NS7520_ETH_MADR_RES2 (0x000000E0) /* Reserved */ +#define NS7520_ETH_MADR_RADR (0x0000001F) /* MII PHY register address */ + +/* MWTD MII Management Write Data Register Bit Fields*/ + +#define NS7520_ETH_MWTD_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MWTD_MWTD (0x0000FFFF) /* MII Write Data */ + +/* MRRD MII Management Read Data Register Bit Fields*/ + +#define NS7520_ETH_MRRD_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_MRRD_MRDD (0x0000FFFF) /* MII Read Data */ + +/* MIND MII Management Indicators Register Bit Fields*/ + +#define NS7520_ETH_MIND_RES1 (0xFFFFFFF8) /* Reserved */ +#define NS7520_ETH_MIND_NVALID (0x00000004) /* Read Data not valid */ +#define NS7520_ETH_MIND_SCAN (0x00000002) /* Automatically scan for read data */ +#define NS7520_ETH_MIND_BUSY (0x00000001) /* MII interface busy */ + +/* SMII Status Register Bit Fields*/ + +#define NS7520_ETH_SMII_RES1 (0xFFFFFFE0) /* Reserved */ +#define NS7520_ETH_SMII_CLASH (0x00000010) /* MAC-to-MAC with PHY */ +#define NS7520_ETH_SMII_JABBER (0x00000008) /* Jabber condition present */ +#define NS7520_ETH_SMII_LINK (0x00000004) /* Link OK */ +#define NS7520_ETH_SMII_DUPLEX (0x00000002) /* Full-duplex operation */ +#define NS7520_ETH_SMII_SPEED (0x00000001) /* 100 Mbps */ + +/* SA1 Station Address 1 Register Bit Fields*/ + +#define NS7520_ETH_SA1_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_SA1_OCTET1 (0x0000FF00) /* Station Address octet 1 */ +#define NS7520_ETH_SA1_OCTET2 (0x000000FF) /* Station Address octet 2 */ + +/* SA2 Station Address 2 Register Bit Fields*/ + +#define NS7520_ETH_SA2_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_SA2_OCTET3 (0x0000FF00) /* Station Address octet 3 */ +#define NS7520_ETH_SA2_OCTET4 (0x000000FF) /* Station Address octet 4 */ + +/* SA3 Station Address 3 Register Bit Fields*/ + +#define NS7520_ETH_SA3_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_SA3_OCTET5 (0x0000FF00) /* Station Address octet 5 */ +#define NS7520_ETH_SA3_OCTET6 (0x000000FF) /* Station Address octet 6 */ + +/* SAFR Station Address Filter Register Bit Fields*/ + +#define NS7520_ETH_SAFR_RES1 (0xFFFFFFF0) /* Reserved */ +#define NS7520_ETH_SAFR_PRO (0x00000008) /* Enable Promiscuous mode */ +#define NS7520_ETH_SAFR_PRM (0x00000004) /* Accept ALL multicast packets */ +#define NS7520_ETH_SAFR_PRA (0x00000002) /* Accept multicast packets table */ +#define NS7520_ETH_SAFR_BROAD (0x00000001) /* Accept ALL Broadcast packets */ + +/* HT1 Hash Table 1 Register Bit Fields*/ + +#define NS7520_ETH_HT1_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_HT1_HT1 (0x0000FFFF) /* CRC value 15-0 */ + +/* HT2 Hash Table 2 Register Bit Fields*/ + +#define NS7520_ETH_HT2_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_HT2_HT2 (0x0000FFFF) /* CRC value 31-16 */ + +/* HT3 Hash Table 3 Register Bit Fields*/ + +#define NS7520_ETH_HT3_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_HT3_HT3 (0x0000FFFF) /* CRC value 47-32 */ + +/* HT4 Hash Table 4 Register Bit Fields*/ + +#define NS7520_ETH_HT4_RES1 (0xFFFF0000) /* Reserved */ +#define NS7520_ETH_HT4_HT4 (0x0000FFFF) /* CRC value 63-48 */ + +#endif /* CONFIG_DRIVER_NS7520_ETHERNET */ + +#endif /* FS_NS7520_ETH_H */ diff --git a/include/ns87308.h b/include/ns87308.h new file mode 100644 index 0000000..feeb940 --- /dev/null +++ b/include/ns87308.h @@ -0,0 +1,250 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _NS87308_H_ +#define _NS87308_H_ + +#include + +/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty + functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */ + +void initialise_ns87308(void); + +/* + * The following struct represents the GPIO registers on the NS87308/NS97307 + */ +struct GPIO +{ + unsigned char dta1; /* 0 data port 1 */ + unsigned char dir1; /* 1 direction port 1 */ + unsigned char out1; /* 2 output type port 1 */ + unsigned char puc1; /* 3 pull-up control port 1 */ + unsigned char dta2; /* 4 data port 2 */ + unsigned char dir2; /* 5 direction port 2 */ + unsigned char out2; /* 6 output type port 2 */ + unsigned char puc2; /* 7 pull-up control port 2 */ +}; + +/* + * The following represents the power management registers on the NS87308/NS97307 + */ +#define PWM_FER1 0 /* 0 function enable reg. 1 */ +#define PWM_FER2 1 /* 1 function enable reg. 2 */ +#define PWM_PMC1 2 /* 2 power mgmt. control 1 */ +#define PWM_PMC2 3 /* 3 power mgmt. control 2 */ +#define PWM_PMC3 4 /* 4 power mgmt. control 3 */ +#define PWM_WDTO 5 /* 5 watchdog time-out */ +#define PWM_WDCF 6 /* 6 watchdog config. */ +#define PWM_WDST 7 /* 7 watchdog status */ + +/*PNP config registers: + * these depend on the stated of BADDR1 and BADDR0 on startup + * so there's three versions here with the last two digits indicating + * for which configuration their valid + * the 1st of the two digits indicates the state of BADDR1 + * the 2st of the two digits indicates the state of BADDR0 + */ + + +#define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */ +#define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */ +#define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */ +#define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */ +#define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */ +#define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */ + +#if defined(CFG_NS87308_BADDR_0x) +#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_0x) +#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_0x) +#elif defined(CFG_NS87308_BADDR_10) +#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_10) +#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_10) +#elif defined(CFG_NS87308_BADDR_11) +#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_11) +#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_11) +#endif + +/* PnP register definitions */ + +#define SET_RD_DATA_PORT 0x00 +#define SERIAL_ISOLATION 0x01 +#define CONFIG_CONTROL 0x02 +#define WAKE_CSN 0x03 +#define RES_DATA 0x04 +#define STATUS 0x05 +#define SET_CSN 0x06 +#define LOGICAL_DEVICE 0x07 + +/*vendor defined values */ +#define SID_REG 0x20 +#define SUPOERIO_CONF1 0x21 +#define SUPOERIO_CONF2 0x22 +#define PGCS_INDEX 0x23 +#define PGCS_DATA 0x24 + +/* values above 30 are different for each logical device + but I can't be arsed to enter them all. the ones here + are pretty consistent between all logical devices + feel free to correct the situation if you want.. ;) + */ +#define ACTIVATE 0x30 +#define ACTIVATE_OFF 0x00 +#define ACTIVATE_ON 0x01 + +#define BASE_ADDR_HIGH 0x60 +#define BASE_ADDR_LOW 0x61 +#define LUN_CONFIG_REG 0xF0 +#define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */ +#define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */ +#define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */ +#define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */ + +/* the logical devices*/ +#define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/ +#define LDEV_KBC2 0x01 +#define LDEV_MOUSE 0x01 +#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/ +#define LDEV_FDC 0x03 /*floppy disk controller*/ +#define LDEV_PARP 0x04 /*Parallel port*/ +#define LDEV_UART2 0x05 +#define LDEV_UART1 0x06 +#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/ +#define LDEV_POWRMAN 0x08 /*Power Managment*/ + +#define CFG_NS87308_KBC1 (1 << LDEV_KBC1) +#define CFG_NS87308_KBC2 (1 << LDEV_KBC2) +#define CFG_NS87308_MOUSE (1 << LDEV_MOUSE) +#define CFG_NS87308_RTC_APC (1 << LDEV_RTC_APC) +#define CFG_NS87308_FDC (1 << LDEV_FDC) +#define CFG_NS87308_PARP (1 << LDEV_PARP) +#define CFG_NS87308_UART2 (1 << LDEV_UART2) +#define CFG_NS87308_UART1 (1 << LDEV_UART1) +#define CFG_NS87308_GPIO (1 << LDEV_GPIO) +#define CFG_NS87308_POWRMAN (1 << LDEV_POWRMAN) + +/*some functions and macro's for doing configuration */ + +static inline void read_pnp_config(unsigned char index, unsigned char *data) +{ + pci_writeb(index,IO_INDEX); + pci_readb(IO_DATA, *data); +} + +static inline void write_pnp_config(unsigned char index, unsigned char data) +{ + pci_writeb(index,IO_INDEX); + pci_writeb(data, IO_DATA); +} + +static inline void pnp_set_device(unsigned char dev) +{ + write_pnp_config(LOGICAL_DEVICE, dev); +} + +static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data) +{ + pci_writeb(index, CFG_ISA_IO + base); + eieio(); + pci_writeb(data, CFG_ISA_IO + base + 1); +} + +/*void write_pnp_config(unsigned char index, unsigned char data); +void pnp_set_device(unsigned char dev); +*/ + +#define PNP_SET_DEVICE_BASE(dev,base) \ + pnp_set_device(dev); \ + write_pnp_config(ACTIVATE, ACTIVATE_OFF); \ + write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \ + write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \ + write_pnp_config(ACTIVATE, ACTIVATE_ON); + +#define PNP_ACTIVATE_DEVICE(dev) \ + pnp_set_device(dev); \ + write_pnp_config(ACTIVATE, ACTIVATE_ON); + +#define PNP_DEACTIVATE_DEVICE(dev) \ + pnp_set_device(dev); \ + write_pnp_config(ACTIVATE, ACTIVATE_OFF); + + +static inline void write_pgcs_config(unsigned char index, unsigned char data) +{ + write_pnp_config(PGCS_INDEX, index); + write_pnp_config(PGCS_DATA, data); +} + +/* these macrose configure the 3 CS lines + on the sandpoint board these controll NVRAM + CS0 is connected to NVRAMCS + CS1 is connected to NVRAMAS0 + CS2 is connected to NVRAMAS1 + */ +#define PGCS_CS_ASSERT_ON_WRITE 0x10 +#define PGCS_CS_ASSERT_ON_READ 0x20 + +#define PNP_PGCS_CSLINE_BASE(cs, base) \ + write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \ + write_pgcs_config(((cs) << 2) + 1, (base) & 0xff ); + +#define PNP_PGCS_CSLINE_CONF(cs, conf) \ + write_pgcs_config(((cs) << 2) + 2, (conf) ); + + +/* The following sections are for 87308 extensions to the standard compoents it emulates */ + +/* extensions to 16550*/ + +#define MCR_MDSL_MSK 0xe0 /*mode select mask*/ +#define MCR_MDSL_UART 0x00 /*uart, default*/ +#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/ +#define MCR_MDSL_SIR 0x03 /*SIR*/ +#define MCR_MDSL_CIR 0x06 /*Consumer IR*/ + +#define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */ +#define FCR_TXFTH1 0x20 /* for interrupt trigger */ + +/* + * Default NS87308 configuration + */ +#ifndef CFG_NS87308_KBC1_BASE +#define CFG_NS87308_KBC1_BASE 0x0060 +#endif +#ifndef CFG_NS87308_RTC_BASE +#define CFG_NS87308_RTC_BASE 0x0070 +#endif +#ifndef CFG_NS87308_FDC_BASE +#define CFG_NS87308_FDC_BASE 0x03F0 +#endif +#ifndef CFG_NS87308_LPT_BASE +#define CFG_NS87308_LPT_BASE 0x0278 +#endif +#ifndef CFG_NS87308_UART1_BASE +#define CFG_NS87308_UART1_BASE 0x03F8 +#endif +#ifndef CFG_NS87308_UART2_BASE +#define CFG_NS87308_UART2_BASE 0x02F8 +#endif + +#endif /*_NS87308_H_*/ diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h new file mode 100644 index 0000000..0918931 --- /dev/null +++ b/include/ns9750_bbus.h @@ -0,0 +1,125 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Definitions for BBus usage + * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + ***********************************************************************/ + +#ifndef FS_NS9750_BBUS_H +#define FS_NS9750_BBUS_H + +#define NS9750_BBUS_MODULE_BASE (0x90600000) + +#define get_bbus_reg_addr(c) \ + ((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c))) + +/* We have support for 50 GPIO pins */ + +#define get_gpio_cfg_reg_addr(pin) \ + get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) ) + +/* To Read/Modify/Write a pin configuration register, use it like + set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT ); + They should be wrapped by cli()/sti() */ +#define set_gpio_cfg_reg_val(pin,cfg) \ + *get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \ + ~NS9750_GPIO_CFG_MASK((pin))) |\ + NS9750_GPIO_CFG_VAL((pin),(cfg)); + +#define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \ + NS9750_GPIO_CFG_MA)) +#define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4)) + +#define NS9750_GPIO_CFG_MA (0x0F) +#define NS9750_GPIO_CFG_INPUT (0x00) +#define NS9750_GPIO_CFG_OUTPUT (0x08) +#define NS9750_GPIO_CFG_FUNC_GPIO (0x03) +#define NS9750_GPIO_CFG_FUNC_2 (0x02) +#define NS9750_GPIO_CFG_FUNC_1 (0x01) +#define NS9750_GPIO_CFG_FUNC_0 (0x00) + +/* the register addresses */ + +#define NS9750_BBUS_MASTER_RESET (0x00) +#define NS9750_BBUS_GPIO_CFG_BASE (0x10) +#define NS9750_BBUS_GPIO_CTRL_BASE (0x30) +#define NS9750_BBUS_GPIO_STAT_BASE (0x40) +#define NS9750_BBUS_MONITOR (0x50) +#define NS9750_BBUS_DMA_INT_STAT (0x60) +#define NS9750_BBUS_DMA_INT_ENABLE (0x64) +#define NS9750_BBUS_USB_CFG (0x70) +#define NS9750_BBUS_ENDIAN_CFG (0x80) +#define NS9750_BBUS_ARM_WAKE_UP (0x90) + +/* register bit fields */ + +#define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100) +#define NS9750_BBUS_MASTER_RESET_I2C (0x00000080) +#define NS9750_BBUS_MASTER_RESET_1284 (0x00000040) +#define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020) +#define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010) +#define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008) +#define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004) +#define NS9750_BBUS_MASTER_RESET_USB (0x00000002) +#define NS9750_BBUS_MASTER_RESET_DMA (0x00000001) + +/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */ + +#define NS9750_BBUS_DMA_INT_BINT16 (0x00010000) +#define NS9750_BBUS_DMA_INT_BINT15 (0x00008000) +#define NS9750_BBUS_DMA_INT_BINT14 (0x00004000) +#define NS9750_BBUS_DMA_INT_BINT13 (0x00002000) +#define NS9750_BBUS_DMA_INT_BINT12 (0x00001000) +#define NS9750_BBUS_DMA_INT_BINT11 (0x00000800) +#define NS9750_BBUS_DMA_INT_BINT10 (0x00000400) +#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200) +#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100) +#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080) +#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040) +#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020) +#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010) +#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008) +#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004) +#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002) +#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001) + +#define NS9750_BBUS_USB_CFG_OUTEN (0x00000008) +#define NS9750_BBUS_USB_CFG_SPEED (0x00000004) +#define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003) +#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003) +#define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002) +#define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001) +#define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000) + +#define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000) +#define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080) +#define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040) +#define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020) +#define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010) +#define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008) +#define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004) +#define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002) +#define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001) + +#endif /* FS_NS9750_BBUS_H */ diff --git a/include/ns9750_eth.h b/include/ns9750_eth.h new file mode 100644 index 0000000..978c0bb --- /dev/null +++ b/include/ns9750_eth.h @@ -0,0 +1,297 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $ + * @Author: Markus Pietrek + * @References: [1] NS9750 Hardware Reference, December 2003 + * [2] Intel LXT971 Datasheet #249414 Rev. 02 + * [3] NS7520 Linux Ethernet Driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifndef FS_NS9750_ETH_H +#define FS_NS9750_ETH_H + +#ifdef CONFIG_DRIVER_NS9750_ETHERNET + +#include "lxt971a.h" + +#define NS9750_ETH_MODULE_BASE (0xA0600000) + +#define get_eth_reg_addr(c) \ + ((volatile unsigned int*) ( NS9750_ETH_MODULE_BASE+(unsigned int) (c))) + +#define NS9750_ETH_EGCR1 (0x0000) +#define NS9750_ETH_EGCR2 (0x0004) +#define NS9750_ETH_EGSR (0x0008) +#define NS9750_ETH_FIFORX (0x000C) +#define NS9750_ETH_FIFOTX (0x0010) +#define NS9750_ETH_FIFOTXS (0x0014) +#define NS9750_ETH_ETSR (0x0018) +#define NS9750_ETH_ERSR (0x001C) +#define NS9750_ETH_MAC1 (0x0400) +#define NS9750_ETH_MAC2 (0x0404) +#define NS9750_ETH_IPGT (0x0408) +#define NS9750_ETH_IPGR (0x040C) +#define NS9750_ETH_CLRT (0x0410) +#define NS9750_ETH_MAXF (0x0414) +#define NS9750_ETH_SUPP (0x0418) +#define NS9750_ETH_TEST (0x041C) +#define NS9750_ETH_MCFG (0x0420) +#define NS9750_ETH_MCMD (0x0424) +#define NS9750_ETH_MADR (0x0428) +#define NS9750_ETH_MWTD (0x042C) +#define NS9750_ETH_MRDD (0x0430) +#define NS9750_ETH_MIND (0x0434) +#define NS9750_ETH_SA1 (0x0440) +#define NS9750_ETH_SA2 (0x0444) +#define NS9750_ETH_SA3 (0x0448) +#define NS9750_ETH_SAFR (0x0500) +#define NS9750_ETH_HT1 (0x0504) +#define NS9750_ETH_HT2 (0x0508) +#define NS9750_ETH_STAT_BASE (0x0680) +#define NS9750_ETH_RXAPTR (0x0A00) +#define NS9750_ETH_RXBPTR (0x0A04) +#define NS9750_ETH_RXCPTR (0x0A08) +#define NS9750_ETH_RXDPTR (0x0A0C) +#define NS9750_ETH_EINTR (0x0A10) +#define NS9750_ETH_EINTREN (0x0A14) +#define NS9750_ETH_TXPTR (0x0A18) +#define NS9750_ETH_TXRPTR (0x0A1C) +#define NS9750_ETH_TXERBD (0x0A20) +#define NS9750_ETH_TXSPTR (0x0A24) +#define NS9750_ETH_RXAOFF (0x0A28) +#define NS9750_ETH_RXBOFF (0x0A2C) +#define NS9750_ETH_RXCOFF (0x0A30) +#define NS9750_ETH_RXDOFF (0x0A34) +#define NS9750_ETH_TXOFF (0x0A38) +#define NS9750_ETH_RXFREE (0x0A3C) +#define NS9750_ETH_TXBD (0x1000) + +/* register bit fields */ + +#define NS9750_ETH_EGCR1_ERX (0x80000000) +#define NS9750_ETH_EGCR1_ERXDMA (0x40000000) +#define NS9750_ETH_EGCR1_ERXSHT (0x10000000) +#define NS9750_ETH_EGCR1_ERXSIZ (0x08000000) +#define NS9750_ETH_EGCR1_ETXSIZ (0x04000000) +#define NS9750_ETH_EGCR1_ETXDIAG (0x02000000) +#define NS9750_ETH_EGCR1_ERXBAD (0x01000000) +#define NS9750_ETH_EGCR1_ETX (0x00800000) +#define NS9750_ETH_EGCR1_ETXDMA (0x00400000) +#define NS9750_ETH_EGCR1_ETXWM (0x00200000) +#define NS9750_ETH_EGCR1_ERXADV (0x00100000) +#define NS9750_ETH_EGCR1_ERXINIT (0x00080000) +#define NS9750_ETH_EGCR1_PHY_MODE_MA (0x0000C000) +#define NS9750_ETH_EGCR1_PHY_MODE_MII (0x00008000) +#define NS9750_ETH_EGCR1_PHY_MODE_RMII (0x00004000) +#define NS9750_ETH_EGCR1_RXCINV (0x00001000) +#define NS9750_ETH_EGCR1_TXCINV (0x00000800) +#define NS9750_ETH_EGCR1_RXALIGN (0x00000400) +#define NS9750_ETH_EGCR1_MAC_HRST (0x00000200) +#define NS9750_ETH_EGCR1_ITXA (0x00000100) + +#define NS9750_ETH_EGCR2_TPTV_MA (0xFFFF0000) +#define NS9750_ETH_EGCR2_TPCF (0x00000040) +#define NS9750_ETH_EGCR2_THPDF (0x00000020) +#define NS9750_ETH_EGCR2_TCLER (0x00000008) +#define NS9750_ETH_EGCR2_AUTOZ (0x00000004) +#define NS9750_ETH_EGCR2_CLRCNT (0x00000002) +#define NS9750_ETH_EGCR2_STEN (0x00000001) + +#define NS9750_ETH_EGSR_RXINIT (0x00100000) +#define NS9750_ETH_EGSR_TXFIFONF (0x00080000) +#define NS9750_ETH_EGSR_TXFIFOH (0x00040000) +#define NS9750_ETH_EGSR_TXFIFOE (0x00010000) + +#define NS9750_ETH_FIFOTXS_ALL (0x00000055) +#define NS9750_ETH_FIFOTXS_3 (0x000000d5) +#define NS9750_ETH_FIFOTXS_2 (0x00000035) +#define NS9750_ETH_FIFOTXS_1 (0x0000000D) +#define NS9750_ETH_FIFOTXS_0 (0x00000003) + +#define NS9750_ETH_ETSR_TXOK (0x00008000) +#define NS9750_ETH_ETSR_TXBR (0x00004000) +#define NS9750_ETH_ETSR_TXMC (0x00002000) +#define NS9750_ETH_ETSR_TXAL (0x00001000) +#define NS9750_ETH_ETSR_TXAED (0x00000800) +#define NS9750_ETH_ETSR_TXAEC (0x00000400) +#define NS9750_ETH_ETSR_TXAUR (0x00000200) +#define NS9750_ETH_ETSR_TXAJ (0x00000100) +#define NS9750_ETH_ETSR_TXDEF (0x00000040) +#define NS9750_ETH_ETSR_TXCRC (0x00000020) +#define NS9750_ETH_ETSR_TXCOLC (0x0000000F) + +#define NS9750_ETH_ERSR_RXSIZE_MA (0x0FFF0000) +#define NS9750_ETH_ERSR_RXCE (0x00008000) +#define NS9750_ETH_ERSR_RXDV (0x00004000) +#define NS9750_ETH_ERSR_RXOK (0x00002000) +#define NS9750_ETH_ERSR_RXBR (0x00001000) +#define NS9750_ETH_ERSR_RXMC (0x00000800) +#define NS9750_ETH_ERSR_RXCRC (0x00000400) +#define NS9750_ETH_ERSR_RXDR (0x00000200) +#define NS9750_ETH_ERSR_RXCV (0x00000100) +#define NS9750_ETH_ERSR_RXSHT (0x00000040) + +#define NS9750_ETH_MAC1_SRST (0x00008000) +#define NS9750_ETH_MAC1_SIMMRST (0x00004000) +#define NS9750_ETH_MAC1_RPEMCSR (0x00000800) +#define NS9750_ETH_MAC1_RPERFUN (0x00000400) +#define NS9750_ETH_MAC1_RPEMCST (0x00000200) +#define NS9750_ETH_MAC1_RPETFUN (0x00000100) +#define NS9750_ETH_MAC1_LOOPBK (0x00000010) +#define NS9750_ETH_MAC1_TXFLOW (0x00000008) +#define NS9750_ETH_MAC1_RXFLOW (0x00000004) +#define NS9750_ETH_MAC1_PALLRX (0x00000002) +#define NS9750_ETH_MAC1_RXEN (0x00000001) + +#define NS9750_ETH_MAC2_EDEFER (0x00004000) +#define NS9750_ETH_MAC2_BACKP (0x00002000) +#define NS9750_ETH_MAC2_NOBO (0x00001000) +#define NS9750_ETH_MAC2_LONGP (0x00000200) +#define NS9750_ETH_MAC2_PUREP (0x00000100) +#define NS9750_ETH_MAC2_AUTOP (0x00000080) +#define NS9750_ETH_MAC2_VLANP (0x00000040) +#define NS9750_ETH_MAC2_PADEN (0x00000020) +#define NS9750_ETH_MAC2_CRCEN (0x00000010) +#define NS9750_ETH_MAC2_DELCRC (0x00000008) +#define NS9750_ETH_MAC2_HUGE (0x00000004) +#define NS9750_ETH_MAC2_FLENC (0x00000002) +#define NS9750_ETH_MAC2_FULLD (0x00000001) + +#define NS9750_ETH_IPGT_MA (0x0000007F) + +#define NS9750_ETH_IPGR_IPGR1 (0x00007F00) +#define NS9750_ETH_IPGR_IPGR2 (0x0000007F) + +#define NS9750_ETH_CLRT_CWIN (0x00003F00) +#define NS9750_ETH_CLRT_RETX (0x0000000F) + +#define NS9750_ETH_MAXF_MAXF (0x0000FFFF) + +#define NS9750_ETH_SUPP_RPERMII (0x00008000) +#define NS9750_ETH_SUPP_SPEED (0x00000080) + +#define NS9750_ETH_TEST_TBACK (0x00000004) +#define NS9750_ETH_TEST_TPAUSE (0x00000002) +#define NS9750_ETH_TEST_SPQ (0x00000001) + +#define NS9750_ETH_MCFG_RMIIM (0x00008000) +#define NS9750_ETH_MCFG_CLKS_MA (0x0000001C) +#define NS9750_ETH_MCFG_CLKS_4 (0x00000004) +#define NS9750_ETH_MCFG_CLKS_6 (0x00000008) +#define NS9750_ETH_MCFG_CLKS_8 (0x0000000C) +#define NS9750_ETH_MCFG_CLKS_10 (0x00000010) +#define NS9750_ETH_MCFG_CLKS_20 (0x00000014) +#define NS9750_ETH_MCFG_CLKS_30 (0x00000018) +#define NS9750_ETH_MCFG_CLKS_40 (0x0000001C) +#define NS9750_ETH_MCFG_SPRE (0x00000002) +#define NS9750_ETH_MCFG_SCANI (0x00000001) + +#define NS9750_ETH_MCMD_SCAN (0x00000002) +#define NS9750_ETH_MCMD_READ (0x00000001) + +#define NS9750_ETH_MADR_DADR_MA (0x00001F00) +#define NS9750_ETH_MADR_RADR_MA (0x0000001F) + +#define NS9750_ETH_MWTD_MA (0x0000FFFF) + +#define NS9750_ETH_MRRD_MA (0x0000FFFF) + +#define NS9750_ETH_MIND_MIILF (0x00000008) +#define NS9750_ETH_MIND_NVALID (0x00000004) +#define NS9750_ETH_MIND_SCAN (0x00000002) +#define NS9750_ETH_MIND_BUSY (0x00000001) + +#define NS9750_ETH_SA1_OCTET1_MA (0x0000FF00) +#define NS9750_ETH_SA1_OCTET2_MA (0x000000FF) + +#define NS9750_ETH_SA2_OCTET3_MA (0x0000FF00) +#define NS9750_ETH_SA2_OCTET4_MA (0x000000FF) + +#define NS9750_ETH_SA3_OCTET5_MA (0x0000FF00) +#define NS9750_ETH_SA3_OCTET6_MA (0x000000FF) + +#define NS9750_ETH_SAFR_PRO (0x00000008) +#define NS9750_ETH_SAFR_PRM (0x00000004) +#define NS9750_ETH_SAFR_PRA (0x00000002) +#define NS9750_ETH_SAFR_BROAD (0x00000001) + +#define NS9750_ETH_HT1_MA (0x0000FFFF) + +#define NS9750_ETH_HT2_MA (0x0000FFFF) + +/* also valid for EINTREN */ +#define NS9750_ETH_EINTR_RXOVL_DATA (0x02000000) +#define NS9750_ETH_EINTR_RXOVL_STAT (0x01000000) +#define NS9750_ETH_EINTR_RXBUFC (0x00800000) +#define NS9750_ETH_EINTR_RXDONEA (0x00400000) +#define NS9750_ETH_EINTR_RXDONEB (0x00200000) +#define NS9750_ETH_EINTR_RXDONEC (0x00100000) +#define NS9750_ETH_EINTR_RXDONED (0x00080000) +#define NS9750_ETH_EINTR_RXNOBUF (0x00040000) +#define NS9750_ETH_EINTR_RXBUFFUL (0x00020000) +#define NS9750_ETH_EINTR_RXBR (0x00010000) +#define NS9750_ETH_EINTR_STOVFL (0x00000040) +#define NS9750_ETH_EINTR_TXPAUSE (0x00000020) +#define NS9750_ETH_EINTR_TXBUFC (0x00000010) +#define NS9750_ETH_EINTR_TXBUFNR (0x00000008) +#define NS9750_ETH_EINTR_TXDONE (0x00000004) +#define NS9750_ETH_EINTR_TXERR (0x00000002) +#define NS9750_ETH_EINTR_TXIDLE (0x00000001) +#define NS9750_ETH_EINTR_RX_MA \ + (NS9750_ETH_EINTR_RXOVL_DATA | \ + NS9750_ETH_EINTR_RXOVL_STAT | \ + NS9750_ETH_EINTR_RXBUFC | \ + NS9750_ETH_EINTR_RXDONEA | \ + NS9750_ETH_EINTR_RXDONEB | \ + NS9750_ETH_EINTR_RXDONEC | \ + NS9750_ETH_EINTR_RXDONED | \ + NS9750_ETH_EINTR_RXNOBUF | \ + NS9750_ETH_EINTR_RXBUFFUL | \ + NS9750_ETH_EINTR_RXBR ) +#define NS9750_ETH_EINTR_TX_MA \ + (NS9750_ETH_EINTR_TXPAUSE | \ + NS9750_ETH_EINTR_TXBUFC | \ + NS9750_ETH_EINTR_TXBUFNR | \ + NS9750_ETH_EINTR_TXDONE | \ + NS9750_ETH_EINTR_TXERR | \ + NS9750_ETH_EINTR_TXIDLE) + +/* for TXPTR, TXRPTR, TXERBD and TXSPTR */ +#define NS9750_ETH_TXPTR_MA (0x000000FF) + +/* for RXAOFF, RXBOFF, RXCOFF and RXDOFF */ +#define NS9750_ETH_RXOFF_MA (0x000007FF) + +#define NS9750_ETH_TXOFF_MA (0x000003FF) + +#define NS9750_ETH_RXFREE_D (0x00000008) +#define NS9750_ETH_RXFREE_C (0x00000004) +#define NS9750_ETH_RXFREE_B (0x00000002) +#define NS9750_ETH_RXFREE_A (0x00000001) + +#ifndef NS9750_ETH_PHY_ADDRESS +# define NS9750_ETH_PHY_ADDRESS (0x0001) /* suitable for UNC20 */ +#endif /* NETARM_ETH_PHY_ADDRESS */ + +#endif /* CONFIG_DRIVER_NS9750_ETHERNET */ + +#endif /* FS_NS9750_ETH_H */ diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h new file mode 100644 index 0000000..44c8ddc --- /dev/null +++ b/include/ns9750_mem.h @@ -0,0 +1,172 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Definitions for Memory Control Module + * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifndef FS_NS9750_MEM_H +#define FS_NS9750_SYS_H + +#define NS9750_MEM_MODULE_BASE (0xA0700000) + +#define get_mem_reg_addr(c) \ + ((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c))) + +/* the register addresses */ + +#define NS9750_MEM_CTRL (0x0000) +#define NS9750_MEM_STATUS (0x0004) +#define NS9750_MEM_CFG (0x0008) +#define NS9750_MEM_DYN_CTRL (0x0020) +#define NS9750_MEM_DYN_REFRESH (0x0024) +#define NS9750_MEM_DYN_READ_CFG (0x0028) +#define NS9750_MEM_DYN_TRP (0x0030) +#define NS9750_MEM_DYN_TRAS (0x0034) +#define NS9750_MEM_DYN_TSREX (0x0038) +#define NS9750_MEM_DYN_TAPR (0x003C) +#define NS9750_MEM_DYN_TDAL (0x0040) +#define NS9750_MEM_DYN_TWR (0x0044) +#define NS9750_MEM_DYN_TRC (0x0048) +#define NS9750_MEM_DYN_TRFC (0x004C) +#define NS9750_MEM_DYN_TXSR (0x0050) +#define NS9750_MEM_DYN_TRRD (0x0054) +#define NS9750_MEM_DYN_TMRD (0x0058) +#define NS9750_MEM_STAT_EXT_WAIT (0x0080) +#define NS9750_MEM_DYN_CFG_BASE (0x0100) +#define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104) +#define NS9750_MEM_STAT_CFG_BASE (0x0200) +#define NS9750_MEM_STAT_WAIT_WEN_BASE (0x0204) +#define NS9750_MEM_STAT_WAIT_OEN_BASE (0x0208) +#define NS9750_MEM_STAT_WAIT_RD_BASE (0x020C) +#define NS9750_MEM_STAT_WAIT_PAGE_BASE (0x0210) +#define NS9750_MEM_STAT_WAIR_WR_BASE (0x0214) +#define NS9750_MEM_STAT_WAIT_TURN_BASE (0x0218) + +/* the vectored register addresses */ + +#define NS9750_MEM_DYN_CFG(c) (NS9750_MEM_DYN_CFG_BASE + (c)*0x20) +#define NS9750_MEM_DYN_RAS_CAS(c) (NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20) +#define NS9750_MEM_STAT_CFG(c) (NS9750_MEM_STAT_CFG_BASE + (c)*0x20) +#define NS9750_MEM_STAT_WAIT_WEN(c) (NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20) +#define NS9750_MEM_STAT_WAIT_OEN(c) (NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20) +#define NS9750_MEM_STAT_RD(c) (NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20) +#define NS9750_MEM_STAT_PAGE(c) (NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20) +#define NS9750_MEM_STAT_WR(c) (NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20) +#define NS9750_MEM_STAT_TURN(c) (NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20) + +/* register bit fields */ + +#define NS9750_MEM_CTRL_L (0x00000004) +#define NS9750_MEM_CTRL_M (0x00000002) +#define NS9750_MEM_CTRL_E (0x00000001) + +#define NS9750_MEM_STAT_SA (0x00000004) +#define NS9750_MEM_STAT_S (0x00000002) +#define NS9750_MEM_STAT_B (0x00000001) + +#define NS9750_MEM_CFG_CLK (0x00000010) +#define NS9750_MEM_CFG_N (0x00000001) + +#define NS9750_MEM_DYN_CTRL_NRP (0x00004000) +#define NS9750_MEM_DYN_CTRL_DP (0x00002000) +#define NS9750_MEM_DYN_CTRL_I_MA (0x00000180) +#define NS9750_MEM_DYN_CTRL_I_NORMAL (0x00000000) +#define NS9750_MEM_DYN_CTRL_I_MODE (0x00000080) +#define NS9750_MEM_DYN_CTRL_I_PALL (0x00000100) +#define NS9750_MEM_DYN_CTRL_I_NOP (0x00000180) +#define NS9750_MEM_DYN_CTRL_SR (0x00000002) +#define NS9750_MEM_DYN_CTRL_CE (0x00000001) + + +#define NS9750_MEM_DYN_REFRESH_MA (0x000007FF) + +#define NS9750_MEM_DYN_READ_CFG_MA (0x00000003) +#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001) +#define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002) +#define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003) + +#define NS9750_MEM_DYN_TRP_MA (0x0000000F) + +#define NS9750_MEM_DYN_TRAS_MA (0x0000000F) + +#define NS9750_MEM_DYN_TSREX_MA (0x0000000F) + +#define NS9750_MEM_DYN_TAPR_MA (0x0000000F) + +#define NS9750_MEM_DYN_TDAL_MA (0x0000000F) + +#define NS9750_MEM_DYN_TWR_MA (0x0000000F) + +#define NS9750_MEM_DYN_TRC_MA (0x0000001F) + +#define NS9750_MEM_DYN_TRFC_MA (0x0000001F) + +#define NS9750_MEM_DYN_TXSR_MA (0x0000001F) + +#define NS9750_MEM_DYN_TRRD_MA (0x0000000F) + +#define NS9750_MEM_DYN_TMRD_MA (0x0000000F) + +#define NS9750_MEM_STAT_EXTW_WAIT_MA (0x0000003F) + +#define NS9750_MEM_DYN_CFG_P (0x00100000) +#define NS9750_MEM_DYN_CFG_BDMC (0x00080000) +#define NS9750_MEM_DYN_CFG_AM (0x00004000) +#define NS9750_MEM_DYN_CFG_AM_MA (0x00001F80) +#define NS9750_MEM_DYN_CFG_MD (0x00000018) + +#define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300) +#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100) +#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200) +#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300) +#define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003) +#define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001) +#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002) +#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003) + +#define NS9750_MEM_STAT_CFG_PSMC (0x00100000) +#define NS9750_MEM_STAT_CFG_BSMC (0x00080000) +#define NS9750_MEM_STAT_CFG_EW (0x00000100) +#define NS9750_MEM_STAT_CFG_PB (0x00000080) +#define NS9750_MEM_STAT_CFG_PC (0x00000040) +#define NS9750_MEM_STAT_CFG_PM (0x00000008) +#define NS9750_MEM_STAT_CFG_MW_MA (0x00000003) +#define NS9750_MEM_STAT_CFG_MW_8 (0x00000000) +#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001) +#define NS9750_MEM_STAT_CFG_MW_32 (0x00000002) + +#define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F) + +#define NS9750_MEM_STAT_WAIT_OEN_MA (0x0000000F) + +#define NS9750_MEM_STAT_WAIT_RD_MA (0x0000001F) + +#define NS9750_MEM_STAT_WAIT_PAGE_MA (0x0000001F) + +#define NS9750_MEM_STAT_WAIT_WR_MA (0x0000001F) + +#define NS9750_MEM_STAT_WAIT_TURN_MA (0x0000000F) + + +#endif /* FS_NS9750_MEM_H */ diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h new file mode 100644 index 0000000..e6ff3e1 --- /dev/null +++ b/include/ns9750_ser.h @@ -0,0 +1,202 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @References: [1] NS9750 Hardware Reference, December 2003 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifndef FS_NS9750_SER_H +#define FS_NS9750_SER_H + +#define NS9750_SER_MODULE_BASE (0x90200000) + +#define get_ser_reg_addr(c) \ + ((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c))) + +#define get_ser_reg_addr_channel(reg,chan) \ + get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0)) + +/* the register addresses */ + +#define NS9750_SER_CTRL_A (0x00) +#define NS9750_SER_CTRL_B (0x04) +#define NS9750_SER_STAT_A (0x08) +#define NS9750_SER_BITRATE (0x0C) +#define NS9750_SER_FIFO (0x10) +#define NS9750_SER_RX_BUF_TIMER (0x14) +#define NS9750_SER_RX_CHAR_TIMER (0x18) +#define NS9750_SER_RX_MATCH (0x1C) +#define NS9750_SER_RX_MATCH_MASK (0x20) +#define NS9750_SER_FLOW_CTRL (0x34) +#define NS9750_SER_FLOW_CTRL_FORCE (0x38) + +/* register bit fields */ + +/* control A register */ + +#define NS9750_SER_CTRL_A_CE (0x80000000) +#define NS9750_SER_CTRL_A_BRK (0x40000000) +#define NS9750_SER_CTRL_A_STICKP (0x20000000) +#define NS9750_SER_CTRL_A_EPS (0x10000000) +#define NS9750_SER_CTRL_A_PE (0x08000000) +#define NS9750_SER_CTRL_A_STOP (0x04000000) +#define NS9750_SER_CTRL_A_WLS_MA (0x03000000) +#define NS9750_SER_CTRL_A_WLS_5 (0x00000000) +#define NS9750_SER_CTRL_A_WLS_6 (0x01000000) +#define NS9750_SER_CTRL_A_WLS_7 (0x02000000) +#define NS9750_SER_CTRL_A_WLS_8 (0x03000000) +#define NS9750_SER_CTRL_A_CTSTX (0x00800000) +#define NS9750_SER_CTRL_A_RTSRX (0x00400000) +#define NS9750_SER_CTRL_A_RL (0x00200000) +#define NS9750_SER_CTRL_A_LL (0x00100000) +#define NS9750_SER_CTRL_A_RES (0x000CF000) +#define NS9750_SER_CTRL_A_DTR (0x00020000) +#define NS9750_SER_CTRL_A_RTS (0x00010000) +#define NS9750_SER_CTRL_A_RIE_MA (0x00000E00) +#define NS9750_SER_CTRL_A_ERXDMA (0x00000100) +#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0) +#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E) +#define NS9750_SER_CTRL_A_ETXDMA (0x00000001) + +/* control B register */ + +#define NS9750_SER_CTRL_B_RDM1 (0x80000000) +#define NS9750_SER_CTRL_B_RDM2 (0x40000000) +#define NS9750_SER_CTRL_B_RDM3 (0x20000000) +#define NS9750_SER_CTRL_B_RDM4 (0x10000000) +#define NS9750_SER_CTRL_B_RBGT (0x08000000) +#define NS9750_SER_CTRL_B_RCGT (0x04000000) +#define NS9750_SER_CTRL_B_MODE_MA (0x00300000) +#define NS9750_SER_CTRL_B_MODE_UART (0x00000000) +#define NS9750_SER_CTRL_B_MODE_HDLC (0x00100000) +#define NS9750_SER_CTRL_B_MODE_SPI_M (0x00200000) +#define NS9750_SER_CTRL_B_MODE_SPI_S (0x00300000) +#define NS9750_SER_CTRL_B_BITORDR (0x00080000) +#define NS9750_SER_CTRL_B_RES (0x0007703F) +#define NS9750_SER_CTRL_B_RTSTX (0x00008000) +#define NS9750_SER_CTRL_B_ENDEC_MA (0x00000FC0) + +/* status A register */ + +#define NS9750_SER_STAT_A_MATCH1 (0x80000000) +#define NS9750_SER_STAT_A_MATCH2 (0x40000000) +#define NS9750_SER_STAT_A_MATCH3 (0x20000000) +#define NS9750_SER_STAT_A_MATCH4 (0x10000000) +#define NS9750_SER_STAT_A_BGAP (0x08000000) +#define NS9750_SER_STAT_A_CGAP (0x04000000) +#define NS9750_SER_STAT_A_RXFDB_MA (0x00300000) +#define NS9750_SER_STAT_A_RXFDB_FULL (0x00000000) +#define NS9750_SER_STAT_A_RXFDB_1 (0x00100000) +#define NS9750_SER_STAT_A_RXFDB_2 (0x00200000) +#define NS9750_SER_STAT_A_RXFDB_3 (0x00300000) +#define NS9750_SER_STAT_A_DCD (0x00080000) +#define NS9750_SER_STAT_A_RI (0x00040000) +#define NS9750_SER_STAT_A_DSR (0x00020000) +#define NS9750_SER_STAT_A_CTS (0x00010000) +#define NS9750_SER_STAT_A_RBRK (0x00008000) +#define NS9750_SER_STAT_A_RFE (0x00004000) +#define NS9750_SER_STAT_A_RPE (0x00002000) +#define NS9750_SER_STAT_A_ROVER (0x00001000) +#define NS9750_SER_STAT_A_RRDY (0x00000800) +#define NS9750_SER_STAT_A_RHALF (0x00000400) +#define NS9750_SER_STAT_A_RBC (0x00000200) +#define NS9750_SER_STAT_A_RFULL (0x00000100) +#define NS9750_SER_STAT_A_DCDI (0x00000080) +#define NS9750_SER_STAT_A_RII (0x00000040) +#define NS9750_SER_STAT_A_DSRI (0x00000020) +#define NS9750_SER_STAT_A_CTSI (0x00000010) +#define NS9750_SER_STAT_A_TRDY (0x00000008) +#define NS9750_SER_STAT_A_THALF (0x00000004) +#define NS9750_SER_STAT_A_TBC (0x00000002) +#define NS9750_SER_STAT_A_TEMPTY (0x00000001) + +#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \ + NS9750_SER_STAT_A_ROVER | \ + NS9750_SER_STAT_A_RPE ) +#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \ + NS9750_SER_STAT_A_RBRK | \ + NS9750_SER_STAT_A_RRDY | \ + NS9750_SER_STAT_A_RHALF | \ + NS9750_SER_STAT_A_RBC | \ + NS9750_SER_STAT_A_DCDI | \ + NS9750_SER_STAT_A_RII | \ + NS9750_SER_STAT_A_DSRI | \ + NS9750_SER_STAT_A_CTSI ) +#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \ + NS9750_SER_STAT_A_THALF | \ + NS9750_SER_STAT_A_TBC | \ + NS9750_SER_STAT_A_TEMPTY ) +/* bit rate register */ + +#define NS9750_SER_BITRATE_EBIT (0x80000000) +#define NS9750_SER_BITRATE_TMODE (0x40000000) +#define NS9750_SER_BITRATE_RXSRC (0x20000000) +#define NS9750_SER_BITRATE_TXSRC (0x10000000) +#define NS9750_SER_BITRATE_RXEXT (0x08000000) +#define NS9750_SER_BITRATE_TXEXT (0x04000000) +#define NS9750_SER_BITRATE_CLKMUX_MA (0x03000000) +#define NS9750_SER_BITRATE_CLKMUX_XTAL (0x00000000) +#define NS9750_SER_BITRATE_CLKMUX_BCLK (0x01000000) +#define NS9750_SER_BITRATE_CLKMUX_OUT1 (0x02000000) +#define NS9750_SER_BITRATE_CLKMUX_OUT2 (0x03000000) +#define NS9750_SER_BITRATE_TXCINV (0x00800000) +#define NS9750_SER_BITRATE_RXCINV (0x00400000) +#define NS9750_SER_BITRATE_TCDR_MA (0x00180000) +#define NS9750_SER_BITRATE_TCDR_1 (0x00000000) +#define NS9750_SER_BITRATE_TCDR_8 (0x00080000) +#define NS9750_SER_BITRATE_TCDR_16 (0x00100000) +#define NS9750_SER_BITRATE_TCDR_32 (0x00180000) +#define NS9750_SER_BITRATE_RCDR_MA (0x00070000) +#define NS9750_SER_BITRATE_RCDR_1 (0x00000000) +#define NS9750_SER_BITRATE_RCDR_8 (0x00020000) +#define NS9750_SER_BITRATE_RCDR_16 (0x00040000) +#define NS9750_SER_BITRATE_RCDR_32 (0x00060000) +#define NS9750_SER_BITRATE_TICS (0x00010000) +#define NS9750_SER_BITRATE_RICS (0x00008000) +#define NS9750_SER_BITRATE_N_MA (0x00007FFF) + +/* receive buffer gap timer */ + +#define NS9750_SER_RX_BUF_TIMER_TRUN (0x80000000) /* UART and SPI */ +#define NS9750_SER_RX_BUF_TIMER_BT_MA (0x0000FFFF) /* UART and SPI */ +#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */ + +/* receive character gap timer */ + +#define NS9750_SER_RX_CHAR_TIMER_TRUN (0x80000000) +#define NS9750_SER_RX_CHAR_TIMER_CT_MA (0x000FFFFF) + +/* receive match */ + +#define NS9750_SER_RX_MATCH_RDMB1_MA (0xFF000000) +#define NS9750_SER_RX_MATCH_RDMB2_MA (0x00FF0000) +#define NS9750_SER_RX_MATCH_RDMB3_MA (0x0000FF00) +#define NS9750_SER_RX_MATCH_RDMB4_MA (0x000000FF) + +/* receive match mask */ + +#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000) +#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000) +#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00) +#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF) + +#endif /* FS_NS9750_SER_H */ diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h new file mode 100644 index 0000000..c563cad --- /dev/null +++ b/include/ns9750_sys.h @@ -0,0 +1,215 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Definitions for SYS Control Module + * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#ifndef FS_NS9750_SYS_H +#define FS_NS9750_SYS_H + +#define NS9750_SYS_MODULE_BASE (0xA0900000) + +#define get_sys_reg_addr(c) \ + ((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c))) + +/* the register addresses */ + +#define NS9750_SYS_AHB_GEN (0x0000) +#define NS9750_SYS_BRC_BASE (0x0004) +#define NS9750_SYS_AHB_TIMEOUT (0x0014) +#define NS9750_SYS_AHB_ERROR1 (0x0018) +#define NS9750_SYS_AHB_ERROR2 (0x001C) +#define NS9750_SYS_AHB_MON (0x0020) +#define NS9750_SYS_TIMER_COUNT_BASE (0x0044) +#define NS9750_SYS_TIMER_READ_BASE (0x0084) +#define NS9750_SYS_INT_VEC_ADR_BASE (0x00C4) +#define NS9750_SYS_INT_CFG_BASE (0x0144) +#define NS9750_SYS_ISRADDR (0x0164) +#define NS9750_SYS_INT_STAT_ACTIVE (0x0168) +#define NS9750_SYS_INT_STAT_RAW (0x016C) +#define NS9750_SYS_TIMER_INT_STAT (0x0170) +#define NS9750_SYS_SW_WDOG_CFG (0x0174) +#define NS9750_SYS_SW_WDOG_TIMER (0x0178) +#define NS9750_SYS_CLOCK (0x017C) +#define NS9750_SYS_RESET (0x0180) +#define NS9750_SYS_MISC (0x0184) +#define NS9750_SYS_PLL (0x0188) +#define NS9750_SYS_ACT_INT_STAT (0x018C) +#define NS9750_SYS_TIMER_CTRL_BASE (0x0190) +#define NS9750_SYS_CS_DYN_BASE_BASE (0x01D0) +#define NS9750_SYS_CS_DYN_MASK_BASE (0x01D4) +#define NS9750_SYS_CS_STATIC_BASE_BASE (0x01F0) +#define NS9750_SYS_CS_STATIC_MASK_BASE (0x01F4) +#define NS9750_SYS_GEN_ID (0x0210) +#define NS9750_SYS_EXT_INT_CTRL_BASE (0x0214) + +/* the vectored register addresses */ + +#define NS9750_SYS_TIMER_COUNT(c) (NS9750_SYS_TIMER_COUNT_BASE + (c)) +#define NS9750_SYS_TIMER_READ(c) (NS9750_SYS_TIMER_READ_BASE + (c)) +#define NS9750_SYS_INT_VEC_ADR(c) (NS9750_SYS_INT_VEC_ADR_BASE + (c)) +#define NS9750_SYS_TIMER_CTRL(c) (NS9750_SYS_TIMER_CTRL_BASE + (c)) +/* CS_DYN start with 4 */ +#define NS9750_SYS_CS_DYN_BASE(c) (NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2) +#define NS9750_SYS_CS_DYN_MASK(c) (NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2) +/* CS_STATIC start with 0 */ +#define NS9750_SYS_CS_STATIC_BASE(c) (NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2) +#define NS9750_SYS_CS_STATIC_MASK(c) (NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2) +#define NS9750_SYS_EXT_INT_CTRL(c) (NS9750_SYS_EXT_INT_CTRL + (c)) + +/* register bit fields */ + +#define NS9750_SYS_AHB_GEN_EXMAM (0x00000001) + +/* need to be n*8bit to BRC channel */ +#define NS9750_SYS_BRC_CEB (0x00000080) +#define NS9750_SYS_BRC_BRF_MA (0x00000030) +#define NS9750_SYS_BRC_BRF_100 (0x00000000) +#define NS9750_SYS_BRC_BRF_75 (0x00000010) +#define NS9750_SYS_BRC_BRF_50 (0x00000020) +#define NS9750_SYS_BRC_BRF_25 (0x00000030) + +#define NS9750_SYS_AHB_TIMEOUT_BAT_MA (0xFFFF0000) +#define NS9750_SYS_AHB_TIMEOUT_BMT_MA (0x0000FFFF) + +#define NS9750_SYS_AHB_ERROR2_ABL (0x00040000) +#define NS9750_SYS_AHB_ERROR2_AER (0x00020000) +#define NS9750_SYS_AHB_ERROR2_ABM (0x00010000) +#define NS9750_SYS_AHB_ERROR2_ABA (0x00008000) +#define NS9750_SYS_AHB_ERROR2_HWRT (0x00004000) +#define NS9750_SYS_AHB_ERROR2_HMID_MA (0x00003C00) +#define NS9750_SYS_AHB_ERROR2_HTPC_MA (0x000003C0) +#define NS9750_SYS_AHB_ERROR2_HSZ_MA (0x00000038) +#define NS9750_SYS_AHB_ERROR2_RR_MA (0x00000007) + +#define NS9750_SYS_AHB_MON_EIC (0x00800000) +#define NS9750_SYS_AHB_MON_MBII (0x00400000) +#define NS9750_SYS_AHB_MON_MBL_MA (0x003FFFC0) +#define NS9750_SYS_AHB_MON_MBLDC (0x00000020) +#define NS9750_SYS_AHB_MON_SERDC (0x00000010) +#define NS9750_SYS_AHB_MON_BMTC_MA (0x0000000C) +#define NS9750_SYS_AHB_MON_BMTC_RECORD (0x00000000) +#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ (0x00000004) +#define NS9750_SYS_AHB_MON_BMTC_GEN_RES (0x00000008) +#define NS9750_SYS_AHB_MON_BATC_MA (0x00000003) +#define NS9750_SYS_AHB_MON_BATC_RECORD (0x00000000) +#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ (0x00000001) +#define NS9750_SYS_AHB_MON_BATC_GEN_RES (0x00000002) + +/* need to be n*8bit to Int Level */ + +#define NS9750_SYS_INT_CFG_IE (0x00000080) +#define NS9750_SYS_INT_CFG_IT (0x00000020) +#define NS9750_SYS_INT_CFG_IAD_MA (0x0000001F) + +#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF) + +#define NS9750_SYS_SW_WDOG_CFG_SWWE (0x00000080) +#define NS9750_SYS_SW_WDOG_CFG_SWWI (0x00000020) +#define NS9750_SYS_SW_WDOG_CFG_SWWIC (0x00000010) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA (0x00000007) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16 (0x00000003) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32 (0x00000004) +#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64 (0x00000005) + +#define NS9750_SYS_CLOCK_LPCS_MA (0x00000380) +#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000) +#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080) +#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100) +#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180) +#define NS9750_SYS_CLOCK_LPCS_EXT (0x00000200) +#define NS9750_SYS_CLOCK_BBC (0x00000040) +#define NS9750_SYS_CLOCK_LCC (0x00000020) +#define NS9750_SYS_CLOCK_MCC (0x00000010) +#define NS9750_SYS_CLOCK_PARBC (0x00000008) +#define NS9750_SYS_CLOCK_PC (0x00000004) +#define NS9750_SYS_CLOCK_MACC (0x00000001) + +#define NS9750_SYS_RESET_SR (0x80000000) +#define NS9750_SYS_RESET_I2CW (0x00100000) +#define NS9750_SYS_RESET_CSE (0x00080000) +#define NS9750_SYS_RESET_SMWE (0x00040000) +#define NS9750_SYS_RESET_EWE (0x00020000) +#define NS9750_SYS_RESET_PI3WE (0x00010000) +#define NS9750_SYS_RESET_BBT (0x00000040) +#define NS9750_SYS_RESET_LCDC (0x00000020) +#define NS9750_SYS_RESET_MEMC (0x00000010) +#define NS9750_SYS_RESET_PCIAR (0x00000008) +#define NS9750_SYS_RESET_PCIM (0x00000004) +#define NS9750_SYS_RESET_MACM (0x00000001) + +#define NS9750_SYS_MISC_REV_MA (0xFF000000) +#define NS9750_SYS_MISC_PCIA (0x00002000) +#define NS9750_SYS_MISC_VDIS (0x00001000) +#define NS9750_SYS_MISC_BMM (0x00000800) +#define NS9750_SYS_MISC_CS1DB (0x00000400) +#define NS9750_SYS_MISC_CS1DW_MA (0x00000300) +#define NS9750_SYS_MISC_MCCM (0x00000080) +#define NS9750_SYS_MISC_PMSS (0x00000040) +#define NS9750_SYS_MISC_CS1P (0x00000020) +#define NS9750_SYS_MISC_ENDM (0x00000008) +#define NS9750_SYS_MISC_MBAR (0x00000004) +#define NS9750_SYS_MISC_IRAM0 (0x00000001) + +#define NS9750_SYS_PLL_PLLBS (0x02000000) +#define NS9750_SYS_PLL_PLLFS_MA (0x01800000) +#define NS9750_SYS_PLL_PLLIS_MA (0x00600000) +#define NS9750_SYS_PLL_PLLND_MA (0x001F0000) +#define NS9750_SYS_PLL_PLLSW (0x00008000) +#define NS9750_SYS_PLL_PLLBSSW (0x00000200) +#define NS9750_SYS_PLL_FSEL_MA (0x00000180) +#define NS9750_SYS_PLL_CPCC_MA (0x00000060) +#define NS9750_SYS_PLL_NDSW_MA (0x0000001F) + +#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF) + +#define NS9750_SYS_TIMER_CTRL_TEN (0x00008000) +#define NS9750_SYS_TIMER_CTRL_INTC (0x00000200) +#define NS9750_SYS_TIMER_CTRL_TLCS_MA (0x000001C0) +#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000) +#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040) +#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080) +#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0) +#define NS9750_SYS_TIMER_CTRL_TLCS_16 (0x00000100) +#define NS9750_SYS_TIMER_CTRL_TLCS_32 (0x00000140) +#define NS9750_SYS_TIMER_CTRL_TLCS_64 (0x00000180) +#define NS9750_SYS_TIMER_CTRL_TLCS_EXT (0x000001C0) +#define NS9750_SYS_TIMER_CTRL_TM_MA (0x00000030) +#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000) +#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010) +#define NS9750_SYS_TIMER_CTRL_TM_HIGH (0x00000020) +#define NS9750_SYS_TIMER_CTRL_INTS (0x00000008) +#define NS9750_SYS_TIMER_CTRL_UDS (0x00000004) +#define NS9750_SYS_TIMER_CTRL_TSZ (0x00000002) +#define NS9750_SYS_TIMER_CTRL_REN (0x00000001) + +#define NS9750_SYS_EXT_INT_CTRL_STS (0x00000008) +#define NS9750_SYS_EXT_INT_CTRL_CLR (0x00000004) +#define NS9750_SYS_EXT_INT_CTRL_PLTY (0x00000002) +#define NS9750_SYS_EXT_INT_CTRL_LVEDG (0x00000001) + +#endif /* FS_NS9750_SYS_H */ diff --git a/include/part.h b/include/part.h new file mode 100644 index 0000000..318aa3c --- /dev/null +++ b/include/part.h @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _PART_H +#define _PART_H +#include + +typedef struct block_dev_desc { + int if_type; /* type of the interface */ + int dev; /* device number */ + unsigned char part_type; /* partition type */ + unsigned char target; /* target SCSI ID */ + unsigned char lun; /* target LUN */ + unsigned char type; /* device type */ + unsigned char removable; /* removable device */ +#ifdef CONFIG_LBA48 + unsigned char lba48; /* device can use 48bit addr (ATA/ATAPI v7) */ +#endif + lbaint_t lba; /* number of blocks */ + unsigned long blksz; /* block size */ + unsigned char vendor [40+1]; /* IDE model, SCSI Vendor */ + unsigned char product[20+1]; /* IDE Serial no, SCSI product */ + unsigned char revision[8+1]; /* firmware revision */ + unsigned long (*block_read)(int dev, + unsigned long start, + lbaint_t blkcnt, + unsigned long *buffer); +}block_dev_desc_t; + +/* Interface types: */ +#define IF_TYPE_UNKNOWN 0 +#define IF_TYPE_IDE 1 +#define IF_TYPE_SCSI 2 +#define IF_TYPE_ATAPI 3 +#define IF_TYPE_USB 4 +#define IF_TYPE_DOC 5 +#define IF_TYPE_MMC 6 + +/* Part types */ +#define PART_TYPE_UNKNOWN 0x00 +#define PART_TYPE_MAC 0x01 +#define PART_TYPE_DOS 0x02 +#define PART_TYPE_ISO 0x03 +#define PART_TYPE_AMIGA 0x04 + +/* + * Type string for U-Boot bootable partitions + */ +#define BOOT_PART_TYPE "U-Boot" /* primary boot partition type */ +#define BOOT_PART_COMP "PPCBoot" /* PPCBoot compatibility type */ + +/* device types */ +#define DEV_TYPE_UNKNOWN 0xff /* not connected */ +#define DEV_TYPE_HARDDISK 0x00 /* harddisk */ +#define DEV_TYPE_TAPE 0x01 /* Tape */ +#define DEV_TYPE_CDROM 0x05 /* CD-ROM */ +#define DEV_TYPE_OPDISK 0x07 /* optical disk */ + +typedef struct disk_partition { + ulong start; /* # of first block in partition */ + ulong size; /* number of blocks in partition */ + ulong blksz; /* block size in bytes */ + uchar name[32]; /* partition name */ + uchar type[32]; /* string type description */ +} disk_partition_t; + +/* disk/part.c */ +int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part (block_dev_desc_t *dev_desc); +void init_part (block_dev_desc_t *dev_desc); +void dev_print(block_dev_desc_t *dev_desc); + + +#ifdef CONFIG_MAC_PARTITION +/* disk/part_mac.c */ +int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part_mac (block_dev_desc_t *dev_desc); +int test_part_mac (block_dev_desc_t *dev_desc); +#endif + +#ifdef CONFIG_DOS_PARTITION +/* disk/part_dos.c */ +int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part_dos (block_dev_desc_t *dev_desc); +int test_part_dos (block_dev_desc_t *dev_desc); +#endif + +#ifdef CONFIG_ISO_PARTITION +/* disk/part_iso.c */ +int get_partition_info_iso (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part_iso (block_dev_desc_t *dev_desc); +int test_part_iso (block_dev_desc_t *dev_desc); +#endif + +#ifdef CONFIG_AMIGA_PARTITION +/* disk/part_amiga.c */ +int get_partition_info_amiga (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part_amiga (block_dev_desc_t *dev_desc); +int test_part_amiga (block_dev_desc_t *dev_desc); +#endif + +#endif /* _PART_H */ diff --git a/include/pc_keyb.h b/include/pc_keyb.h new file mode 100644 index 0000000..ab51703 --- /dev/null +++ b/include/pc_keyb.h @@ -0,0 +1,121 @@ +/* + * include/linux/pc_keyb.h + * + * PC Keyboard And Keyboard Controller + * + * (c) 1997 Martin Mares + */ + +/* + * Configuration Switches + */ +#undef KBD_REPORT_ERR /* Report keyboard errors */ +#define KBD_REPORT_UNKN /* Report unknown scan codes */ +#define KBD_REPORT_TIMEOUTS /* Report keyboard timeouts */ +#undef KBD_IS_FOCUS_9000 /* We have the brain-damaged FOCUS-9000 keyboard */ +#undef INITIALIZE_MOUSE /* Define if your PS/2 mouse needs initialization. */ + +#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */ +#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */ +#define KBD_TIMEOUT 1000 /* Timeout in ms for keyboard command acknowledge */ + +/* + * Internal variables of the driver + */ +extern unsigned char pckbd_read_mask; +extern unsigned char aux_device_present; + +/* + * Keyboard Controller Registers on normal PCs. + */ +#define KBD_STATUS_REG 0x64 /* Status register (R) */ +#define KBD_CNTL_REG 0x64 /* Controller command register (W) */ +#define KBD_DATA_REG 0x60 /* Keyboard data register (R/W) */ + +/* + * Keyboard Controller Commands + */ +#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ +#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ +#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ +#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ +#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ +#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ +#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ +#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ +#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ +#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ +#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if + initiated by the auxiliary device */ +#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ + +/* + * Keyboard Commands + */ +#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ +#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ +#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ +#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ +#define KBD_CMD_RESET 0xFF /* Reset */ + +/* + * Keyboard Replies + */ +#define KBD_REPLY_POR 0xAA /* Power on reset */ +#define KBD_REPLY_ACK 0xFA /* Command ACK */ +#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ + +/* + * Status Register Bits + */ +#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ +#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ +#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ +#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ +#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ +#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ +#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ +#define KBD_STAT_PERR 0x80 /* Parity error */ + +#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF) + +/* + * Controller Mode Register Bits + */ +#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ +#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ +#define KBD_MODE_SYS 0x04 /* The system flag (?) */ +#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ +#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ +#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ +#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ +#define KBD_MODE_RFU 0x80 + +/* + * Mouse Commands + */ +#define AUX_SET_RES 0xE8 /* Set resolution */ +#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ +#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ +#define AUX_GET_SCALE 0xE9 /* Get scaling factor */ +#define AUX_SET_STREAM 0xEA /* Set stream mode */ +#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */ +#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */ +#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */ +#define AUX_RESET 0xFF /* Reset aux device */ +#define AUX_ACK 0xFA /* Command byte ACK. */ + +#define AUX_BUF_SIZE 2048 /* This might be better divisible by + three to make overruns stay in sync + but then the read function would need + a lock etc - ick */ + +#if 0 +struct aux_queue { + unsigned long head; + unsigned long tail; + wait_queue_head_t proc_list; + struct fasync_struct *fasync; + unsigned char buf[AUX_BUF_SIZE]; +}; +#endif diff --git a/include/pci.h b/include/pci.h new file mode 100644 index 0000000..8f19997 --- /dev/null +++ b/include/pci.h @@ -0,0 +1,493 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * aloong with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PCI_H +#define _PCI_H + +/* + * Under PCI, each device has 256 bytes of configuration address space, + * of which the first 64 bytes are standardized as follows: + */ +#define PCI_VENDOR_ID 0x00 /* 16 bits */ +#define PCI_DEVICE_ID 0x02 /* 16 bits */ +#define PCI_COMMAND 0x04 /* 16 bits */ +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ +#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ +#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ + +#define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ +#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ +#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ +#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ +#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ +#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ +#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_MEDIUM 0x200 +#define PCI_STATUS_DEVSEL_SLOW 0x400 +#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ +#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ +#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ +#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ +#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ + +#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 + revision */ +#define PCI_REVISION_ID 0x08 /* Revision ID */ +#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ +#define PCI_CLASS_DEVICE 0x0a /* Device class */ +#define PCI_CLASS_CODE 0x0b /* Device class code */ +#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ + +#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ +#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ +#define PCI_HEADER_TYPE 0x0e /* 8 bits */ +#define PCI_HEADER_TYPE_NORMAL 0 +#define PCI_HEADER_TYPE_BRIDGE 1 +#define PCI_HEADER_TYPE_CARDBUS 2 + +#define PCI_BIST 0x0f /* 8 bits */ +#define PCI_BIST_CODE_MASK 0x0f /* Return result */ +#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ +#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ + +/* + * Base addresses specify locations in memory or I/O space. + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only + * 1 bits are decoded. + */ +#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ +#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ +#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ +#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ +#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ +#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCI_BASE_ADDRESS_SPACE_IO 0x01 +#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 +#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ +#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ +#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ +#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ +#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) +#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) +/* bit 1 is reserved if address_space = 1 */ + +/* Header type 0 (normal devices) */ +#define PCI_CARDBUS_CIS 0x28 +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c +#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 +#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) + +#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ + +/* 0x35-0x3b are reserved */ +#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ +#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ +#define PCI_MIN_GNT 0x3e /* 8 bits */ +#define PCI_MAX_LAT 0x3f /* 8 bits */ + +/* Header type 1 (PCI-to-PCI bridges) */ +#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ +#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ +#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ +#define PCI_IO_LIMIT 0x1d +#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ +#define PCI_IO_RANGE_TYPE_16 0x00 +#define PCI_IO_RANGE_TYPE_32 0x01 +#define PCI_IO_RANGE_MASK ~0x0f +#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ +#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ +#define PCI_MEMORY_LIMIT 0x22 +#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f +#define PCI_MEMORY_RANGE_MASK ~0x0f +#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ +#define PCI_PREF_MEMORY_LIMIT 0x26 +#define PCI_PREF_RANGE_TYPE_MASK 0x0f +#define PCI_PREF_RANGE_TYPE_32 0x00 +#define PCI_PREF_RANGE_TYPE_64 0x01 +#define PCI_PREF_RANGE_MASK ~0x0f +#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +#define PCI_PREF_LIMIT_UPPER32 0x2c +#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ +#define PCI_IO_LIMIT_UPPER16 0x32 +/* 0x34 same as for htype 0 */ +/* 0x35-0x3b is reserved */ +#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_BRIDGE_CONTROL 0x3e +#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ +#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ +#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ +#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ +#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ +#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ + +/* From 440ep */ +#define PCI_ERREN 0x48 /* Error Enable */ +#define PCI_ERRSTS 0x49 /* Error Status */ +#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ +#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ +#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ +#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ +#define PCI_CAPID 0x58 /* Capability Identifier */ +#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ +#define PCI_PMC 0x5A /* Power Management Capabilities */ +#define PCI_PMCSR 0x5C /* Power Management Control Status */ +#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ +#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ +#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ + +/* Header type 2 (CardBus bridges) */ +#define PCI_CB_CAPABILITY_LIST 0x14 +/* 0x15 reserved */ +#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ +#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ +#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ +#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ +#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ +#define PCI_CB_MEMORY_BASE_0 0x1c +#define PCI_CB_MEMORY_LIMIT_0 0x20 +#define PCI_CB_MEMORY_BASE_1 0x24 +#define PCI_CB_MEMORY_LIMIT_1 0x28 +#define PCI_CB_IO_BASE_0 0x2c +#define PCI_CB_IO_BASE_0_HI 0x2e +#define PCI_CB_IO_LIMIT_0 0x30 +#define PCI_CB_IO_LIMIT_0_HI 0x32 +#define PCI_CB_IO_BASE_1 0x34 +#define PCI_CB_IO_BASE_1_HI 0x36 +#define PCI_CB_IO_LIMIT_1 0x38 +#define PCI_CB_IO_LIMIT_1_HI 0x3a +#define PCI_CB_IO_RANGE_MASK ~0x03 +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_CB_BRIDGE_CONTROL 0x3e +#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ +#define PCI_CB_BRIDGE_CTL_SERR 0x02 +#define PCI_CB_BRIDGE_CTL_ISA 0x04 +#define PCI_CB_BRIDGE_CTL_VGA 0x08 +#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 +#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ +#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 +#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 +#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 +#define PCI_CB_SUBSYSTEM_ID 0x42 +#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ +/* 0x48-0x7f reserved */ + +/* Capability lists */ + +#define PCI_CAP_LIST_ID 0 /* Capability ID */ +#define PCI_CAP_ID_PM 0x01 /* Power Management */ +#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ +#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ +#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ +#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ +#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ +#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ +#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ +#define PCI_CAP_SIZEOF 4 + +/* Power Management Registers */ + +#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ +#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ +#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ +#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ +#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ +#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ +#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ +#define PCI_PM_CTRL 4 /* PM control and status register */ +#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ +#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ +#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ +#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ +#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ +#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ +#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ +#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ +#define PCI_PM_DATA_REGISTER 7 /* (??) */ +#define PCI_PM_SIZEOF 8 + +/* AGP registers */ + +#define PCI_AGP_VERSION 2 /* BCD version number */ +#define PCI_AGP_RFU 3 /* Rest of capability flags */ +#define PCI_AGP_STATUS 4 /* Status register */ +#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ +#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ +#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ +#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ +#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ +#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ +#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ +#define PCI_AGP_COMMAND 8 /* Control register */ +#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ +#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ +#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ +#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ +#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ +#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ +#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ +#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ +#define PCI_AGP_SIZEOF 12 + +/* Slot Identification */ + +#define PCI_SID_ESR 2 /* Expansion Slot Register */ +#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ +#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ +#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ + +/* Message Signalled Interrupts registers */ + +#define PCI_MSI_FLAGS 2 /* Various flags */ +#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ +#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ +#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ +#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ +#define PCI_MSI_RFU 3 /* Rest of capability flags */ +#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ +#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ +#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ +#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ + +#define PCI_MAX_PCI_DEVICES 32 +#define PCI_MAX_PCI_FUNCTIONS 8 + +/* Include the ID list */ + +#include + +struct pci_region { + unsigned long bus_start; /* Start on the bus */ + unsigned long phys_start; /* Start in physical address space */ + unsigned long size; /* Size */ + unsigned long flags; /* Resource flags */ + + unsigned long bus_lower; +}; + +#define PCI_REGION_MEM 0x00000000 /* PCI memory space */ +#define PCI_REGION_IO 0x00000001 /* PCI IO space */ +#define PCI_REGION_TYPE 0x00000001 + +#define PCI_REGION_MEMORY 0x00000100 /* System memory */ +#define PCI_REGION_RO 0x00000200 /* Read-only memory */ + +extern __inline__ void pci_set_region(struct pci_region *reg, + unsigned long bus_start, + unsigned long phys_start, + unsigned long size, + unsigned long flags) { + reg->bus_start = bus_start; + reg->phys_start = phys_start; + reg->size = size; + reg->flags = flags; +} + +typedef int pci_dev_t; + +#define PCI_BUS(d) (((d) >> 16) & 0xff) +#define PCI_DEV(d) (((d) >> 11) & 0x1f) +#define PCI_FUNC(d) (((d) >> 8) & 0x7) +#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8) + +#define PCI_ANY_ID (~0) + +struct pci_device_id { + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ +}; + +struct pci_controller; + +struct pci_config_table { + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ + unsigned int class; /* Class ID, or PCI_ANY_ID */ + unsigned int bus; /* Bus number, or PCI_ANY_ID */ + unsigned int dev; /* Device number, or PCI_ANY_ID */ + unsigned int func; /* Function number, or PCI_ANY_ID */ + + void (*config_device)(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *); + unsigned long priv[3]; +}; + +extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *); +extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *); + +#define MAX_PCI_REGIONS 7 + +/* + * Structure of a PCI controller (host bridge) + */ +struct pci_controller { + struct pci_controller *next; + + int first_busno; + int last_busno; + + volatile unsigned int *cfg_addr; + volatile unsigned char *cfg_data; + + struct pci_region regions[MAX_PCI_REGIONS]; + int region_count; + + struct pci_config_table *config_table; + + void (*fixup_irq)(struct pci_controller *, pci_dev_t); + + /* Low-level architecture-dependent routines */ + int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); + int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); + int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); + int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); + int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); + int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); + + /* Used by auto config */ + struct pci_region *pci_mem, *pci_io; + + /* Used by ppc405 autoconfig*/ + struct pci_region *pci_fb; + int current_busno; +}; + +extern __inline__ void pci_set_ops(struct pci_controller *hose, + int (*read_byte)(struct pci_controller*, + pci_dev_t, int where, u8 *), + int (*read_word)(struct pci_controller*, + pci_dev_t, int where, u16 *), + int (*read_dword)(struct pci_controller*, + pci_dev_t, int where, u32 *), + int (*write_byte)(struct pci_controller*, + pci_dev_t, int where, u8), + int (*write_word)(struct pci_controller*, + pci_dev_t, int where, u16), + int (*write_dword)(struct pci_controller*, + pci_dev_t, int where, u32)) { + hose->read_byte = read_byte; + hose->read_word = read_word; + hose->read_dword = read_dword; + hose->write_byte = write_byte; + hose->write_word = write_word; + hose->write_dword = write_dword; +} + +extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); + +extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose, + unsigned long addr, unsigned long flags); +extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose, + unsigned long addr, unsigned long flags); + +#define pci_phys_to_bus(dev, addr, flags) \ + pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) +#define pci_bus_to_phys(dev, addr, flags) \ + pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) + +#define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) +#define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) +#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) +#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) + +extern int pci_hose_read_config_byte(struct pci_controller *hose, + pci_dev_t dev, int where, u8 *val); +extern int pci_hose_read_config_word(struct pci_controller *hose, + pci_dev_t dev, int where, u16 *val); +extern int pci_hose_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u32 *val); +extern int pci_hose_write_config_byte(struct pci_controller *hose, + pci_dev_t dev, int where, u8 val); +extern int pci_hose_write_config_word(struct pci_controller *hose, + pci_dev_t dev, int where, u16 val); +extern int pci_hose_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u32 val); + +extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); +extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); +extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); +extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); +extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); +extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); + +extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u8 *val); +extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u16 *val); +extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u8 val); +extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, + pci_dev_t dev, int where, u16 val); + +extern void pci_register_hose(struct pci_controller* hose); +extern struct pci_controller* pci_bus_to_hose(int bus); + +extern int pci_hose_scan(struct pci_controller *hose); +extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); + +extern void pciauto_region_init(struct pci_region* res); +extern void pciauto_region_align(struct pci_region *res, unsigned long size); +extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar); +extern void pciauto_setup_device(struct pci_controller *hose, + pci_dev_t dev, int bars_num, + struct pci_region *mem, + struct pci_region *io); +int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); + +extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); +extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); +extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code, + int wanted_prog_if, int index); + +extern int pci_hose_config_device(struct pci_controller *hose, + pci_dev_t dev, + unsigned long io, + unsigned long mem, + unsigned long command); + +#ifdef CONFIG_MPC824X +extern void pci_mpc824x_init (struct pci_controller *hose); +#endif + +#endif /* _PCI_H */ diff --git a/include/pci_ids.h b/include/pci_ids.h new file mode 100644 index 0000000..7dec378 --- /dev/null +++ b/include/pci_ids.h @@ -0,0 +1,2048 @@ +/* + * PCI Class, Vendor and Device IDs + * + * Please keep sorted. + */ + +/* Device classes and subclasses */ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 +#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_SCANNER 0x0903 +#define PCI_CLASS_INPUT_GAMEPORT 0x0904 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a80 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_FIBER 0x0c04 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 + +#define PCI_BASE_CLASS_INTELLIGENT 0x0e +#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 + +#define PCI_BASE_CLASS_SATELLITE 0x0f +#define PCI_CLASS_SATELLITE_TV 0x0f00 +#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 +#define PCI_CLASS_SATELLITE_VOICE 0x0f03 +#define PCI_CLASS_SATELLITE_DATA 0x0f04 + +#define PCI_BASE_CLASS_CRYPT 0x10 +#define PCI_CLASS_CRYPT_NETWORK 0x1000 +#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 +#define PCI_CLASS_CRYPT_OTHER 0x1080 + +#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 +#define PCI_CLASS_SP_DPIO 0x1100 +#define PCI_CLASS_SP_OTHER 0x1180 + +#define PCI_CLASS_OTHERS 0xff + +/* Vendors and devices. Sort key: vendor first, device next. */ + +#define PCI_VENDOR_ID_DYNALINK 0x0675 +#define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 + +#define PCI_VENDOR_ID_BERKOM 0x0871 +#define PCI_DEVICE_ID_BERKOM_A1T 0xffa1 +#define PCI_DEVICE_ID_BERKOM_T_CONCEPT 0xffa2 +#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4 +#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8 + +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 +#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 +#define PCI_DEVICE_ID_COMPAQ_6010 0x6010 +#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc +#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 +#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33 +#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 +#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060 +#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178 +#define PCI_DEVICE_ID_COMPAQ_CISSC 0x0046 +#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 + +#define PCI_VENDOR_ID_NCR 0x1000 +#define PCI_VENDOR_ID_LSI_LOGIC 0x1000 +#define PCI_DEVICE_ID_NCR_53C810 0x0001 +#define PCI_DEVICE_ID_NCR_53C820 0x0002 +#define PCI_DEVICE_ID_NCR_53C825 0x0003 +#define PCI_DEVICE_ID_NCR_53C815 0x0004 +#define PCI_DEVICE_ID_LSI_53C810AP 0x0005 +#define PCI_DEVICE_ID_NCR_53C860 0x0006 +#define PCI_DEVICE_ID_LSI_53C1510 0x000a +#define PCI_DEVICE_ID_NCR_53C896 0x000b +#define PCI_DEVICE_ID_NCR_53C895 0x000c +#define PCI_DEVICE_ID_NCR_53C885 0x000d +#define PCI_DEVICE_ID_NCR_53C875 0x000f +#define PCI_DEVICE_ID_NCR_53C1510 0x0010 +#define PCI_DEVICE_ID_LSI_53C895A 0x0012 +#define PCI_DEVICE_ID_LSI_53C875A 0x0013 +#define PCI_DEVICE_ID_LSI_53C1010_33 0x0020 +#define PCI_DEVICE_ID_LSI_53C1010_66 0x0021 +#define PCI_DEVICE_ID_LSI_53C1030 0x0030 +#define PCI_DEVICE_ID_LSI_53C1035 0x0040 +#define PCI_DEVICE_ID_NCR_53C875J 0x008f +#define PCI_DEVICE_ID_LSI_FC909 0x0621 +#define PCI_DEVICE_ID_LSI_FC929 0x0622 +#define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623 +#define PCI_DEVICE_ID_LSI_FC919 0x0624 +#define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625 +#define PCI_DEVICE_ID_LSI_FC929X 0x0626 +#define PCI_DEVICE_ID_LSI_FC919X 0x0628 +#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701 +#define PCI_DEVICE_ID_LSI_61C102 0x0901 +#define PCI_DEVICE_ID_LSI_63C815 0x1000 + +#define PCI_VENDOR_ID_ATI 0x1002 +/* Mach64 */ +#define PCI_DEVICE_ID_ATI_68800 0x4158 +#define PCI_DEVICE_ID_ATI_215CT222 0x4354 +#define PCI_DEVICE_ID_ATI_210888CX 0x4358 +#define PCI_DEVICE_ID_ATI_215ET222 0x4554 +/* Mach64 / Rage */ +#define PCI_DEVICE_ID_ATI_215GB 0x4742 +#define PCI_DEVICE_ID_ATI_215GD 0x4744 +#define PCI_DEVICE_ID_ATI_215GI 0x4749 +#define PCI_DEVICE_ID_ATI_215GP 0x4750 +#define PCI_DEVICE_ID_ATI_215GQ 0x4751 +#define PCI_DEVICE_ID_ATI_215XL 0x4752 +#define PCI_DEVICE_ID_ATI_215GT 0x4754 +#define PCI_DEVICE_ID_ATI_215GTB 0x4755 +#define PCI_DEVICE_ID_ATI_215_IV 0x4756 +#define PCI_DEVICE_ID_ATI_215_IW 0x4757 +#define PCI_DEVICE_ID_ATI_215_IZ 0x475A +#define PCI_DEVICE_ID_ATI_210888GX 0x4758 +#define PCI_DEVICE_ID_ATI_215_LB 0x4c42 +#define PCI_DEVICE_ID_ATI_215_LD 0x4c44 +#define PCI_DEVICE_ID_ATI_215_LG 0x4c47 +#define PCI_DEVICE_ID_ATI_215_LI 0x4c49 +#define PCI_DEVICE_ID_ATI_215_LM 0x4c4D +#define PCI_DEVICE_ID_ATI_215_LN 0x4c4E +#define PCI_DEVICE_ID_ATI_215_LR 0x4c52 +#define PCI_DEVICE_ID_ATI_215_LS 0x4c53 +#define PCI_DEVICE_ID_ATI_264_LT 0x4c54 +/* Mach64 VT */ +#define PCI_DEVICE_ID_ATI_264VT 0x5654 +#define PCI_DEVICE_ID_ATI_264VU 0x5655 +#define PCI_DEVICE_ID_ATI_264VV 0x5656 +/* Rage128 Pro GL */ +#define PCI_DEVICE_ID_ATI_Rage128_PA 0x5041 +#define PCI_DEVICE_ID_ATI_Rage128_PB 0x5042 +#define PCI_DEVICE_ID_ATI_Rage128_PC 0x5043 +#define PCI_DEVICE_ID_ATI_Rage128_PD 0x5044 +#define PCI_DEVICE_ID_ATI_Rage128_PE 0x5045 +#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046 +/* Rage128 Pro VR */ +#define PCI_DEVICE_ID_ATI_RAGE128_PG 0x5047 +#define PCI_DEVICE_ID_ATI_RAGE128_PH 0x5048 +#define PCI_DEVICE_ID_ATI_RAGE128_PI 0x5049 +#define PCI_DEVICE_ID_ATI_RAGE128_PJ 0x504A +#define PCI_DEVICE_ID_ATI_RAGE128_PK 0x504B +#define PCI_DEVICE_ID_ATI_RAGE128_PL 0x504C +#define PCI_DEVICE_ID_ATI_RAGE128_PM 0x504D +#define PCI_DEVICE_ID_ATI_RAGE128_PN 0x504E +#define PCI_DEVICE_ID_ATI_RAGE128_PO 0x504F +#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050 +#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051 +#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052 +#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452 +#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053 +#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054 +#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055 +#define PCI_DEVICE_ID_ATI_RAGE128_PV 0x5056 +#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057 +#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058 +/* Rage128 GL */ +#define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245 +#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246 +#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x534b +#define PCI_DEVICE_ID_ATI_RAGE128_RH 0x534c +#define PCI_DEVICE_ID_ATI_RAGE128_RI 0x534d +/* Rage128 VR */ +#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b +#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c +#define PCI_DEVICE_ID_ATI_RAGE128_RM 0x5345 +#define PCI_DEVICE_ID_ATI_RAGE128_RN 0x5346 +#define PCI_DEVICE_ID_ATI_RAGE128_RO 0x5347 +/* Rage128 M3 */ +#define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45 +#define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46 +/* Rage128 Pro Ultra */ +#define PCI_DEVICE_ID_ATI_RAGE128_U1 0x5446 +#define PCI_DEVICE_ID_ATI_RAGE128_U2 0x544C +#define PCI_DEVICE_ID_ATI_RAGE128_U3 0x5452 +/* Rage M4 */ +#define PCI_DEVICE_ID_ATI_RADEON_LE 0x4d45 +#define PCI_DEVICE_ID_ATI_RADEON_LF 0x4d46 +/* Radeon R100 */ +#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144 +#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145 +#define PCI_DEVICE_ID_ATI_RADEON_QF 0x5146 +#define PCI_DEVICE_ID_ATI_RADEON_QG 0x5147 +/* Radeon RV100 (VE) */ +#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 +#define PCI_DEVICE_ID_ATI_RADEON_QZ 0x515a +/* Radeon R200 (8500) */ +#define PCI_DEVICE_ID_ATI_RADEON_QL 0x514c +#define PCI_DEVICE_ID_ATI_RADEON_QN 0x514e +#define PCI_DEVICE_ID_ATI_RADEON_QO 0x514f +#define PCI_DEVICE_ID_ATI_RADEON_Ql 0x516c +#define PCI_DEVICE_ID_ATI_RADEON_BB 0x4242 +/* Radeon R200 (9100) */ +#define PCI_DEVICE_ID_ATI_RADEON_QM 0x514d +/* Radeon RV200 (7500) */ +#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157 +#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158 +/* Radeon RV250 (9000) */ +#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964 +#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965 +#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966 +#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967 +/* Radeon RV280 (9200) */ +#define PCI_DEVICE_ID_ATI_RADEON_Y_ 0x5960 +#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961 +#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964 +/* Radeon R300 (9700) */ +#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44 +#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45 +#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46 +#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47 +#define PCI_DEVICE_ID_ATI_RADEON_AE 0x4145 +#define PCI_DEVICE_ID_ATI_RADEON_AF 0x4146 +/* Radeon R300 (9500) */ +#define PCI_DEVICE_ID_ATI_RADEON_AD 0x4144 +/* Radeon R350 (9800) */ +#define PCI_DEVICE_ID_ATI_RADEON_NH 0x4e48 +#define PCI_DEVICE_ID_ATI_RADEON_NI 0x4e49 +/* Radeon RV350 (9600) */ +#define PCI_DEVICE_ID_ATI_RADEON_AP 0x4150 +#define PCI_DEVICE_ID_ATI_RADEON_AR 0x4152 +/* Radeon M6 */ +#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59 +#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a +/* Radeon M7 */ +#define PCI_DEVICE_ID_ATI_RADEON_LW 0x4c57 +#define PCI_DEVICE_ID_ATI_RADEON_LX 0x4c58 +/* Radeon M9 */ +#define PCI_DEVICE_ID_ATI_RADEON_Ld 0x4c64 +#define PCI_DEVICE_ID_ATI_RADEON_Le 0x4c65 +#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66 +#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67 +/* RadeonIGP */ +#define PCI_DEVICE_ID_ATI_RADEON_IGP 0xCAB0 +/* ATI IXP Chipset */ +#define PCI_DEVICE_ID_ATI_IXP_IDE 0x4349 + +#define PCI_VENDOR_ID_VLSI 0x1004 +#define PCI_DEVICE_ID_VLSI_82C592 0x0005 +#define PCI_DEVICE_ID_VLSI_82C593 0x0006 +#define PCI_DEVICE_ID_VLSI_82C594 0x0007 +#define PCI_DEVICE_ID_VLSI_82C597 0x0009 +#define PCI_DEVICE_ID_VLSI_82C541 0x000c +#define PCI_DEVICE_ID_VLSI_82C543 0x000d +#define PCI_DEVICE_ID_VLSI_82C532 0x0101 +#define PCI_DEVICE_ID_VLSI_82C534 0x0102 +#define PCI_DEVICE_ID_VLSI_82C535 0x0104 +#define PCI_DEVICE_ID_VLSI_82C147 0x0105 +#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 + +#define PCI_VENDOR_ID_ADL 0x1005 +#define PCI_DEVICE_ID_ADL_2301 0x2301 + +#define PCI_VENDOR_ID_NS 0x100b +#define PCI_DEVICE_ID_NS_87415 0x0002 +#define PCI_DEVICE_ID_NS_87560_LIO 0x000e +#define PCI_DEVICE_ID_NS_87560_USB 0x0012 +#define PCI_DEVICE_ID_NS_83815 0x0020 +#define PCI_DEVICE_ID_NS_83820 0x0022 +#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 +#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 +#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 +#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 +#define PCI_DEVICE_ID_NS_87410 0xd001 + +#define PCI_VENDOR_ID_TSENG 0x100c +#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 +#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 +#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 +#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 +#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 + +#define PCI_VENDOR_ID_WEITEK 0x100e +#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 +#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 + +#define PCI_VENDOR_ID_DEC 0x1011 +#define PCI_DEVICE_ID_DEC_BRD 0x0001 +#define PCI_DEVICE_ID_DEC_TULIP 0x0002 +#define PCI_DEVICE_ID_DEC_TGA 0x0004 +#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 +#define PCI_DEVICE_ID_DEC_TGA2 0x000D +#define PCI_DEVICE_ID_DEC_FDDI 0x000F +#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 +#define PCI_DEVICE_ID_DEC_21142 0x0019 +#define PCI_DEVICE_ID_DEC_21052 0x0021 +#define PCI_DEVICE_ID_DEC_21150 0x0022 +#define PCI_DEVICE_ID_DEC_21152 0x0024 +#define PCI_DEVICE_ID_DEC_21153 0x0025 +#define PCI_DEVICE_ID_DEC_21154 0x0026 +#define PCI_DEVICE_ID_DEC_21285 0x1065 +#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 + +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 +#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 +#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 +#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 +#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac +#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 +#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc +#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0 +#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 +#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 +#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 +#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 +#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 +#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 +#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 + +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a +#define PCI_DEVICE_ID_IBM_TR 0x0018 +#define PCI_DEVICE_ID_IBM_82G2675 0x001d +#define PCI_DEVICE_ID_IBM_MCA 0x0020 +#define PCI_DEVICE_ID_IBM_82351 0x0022 +#define PCI_DEVICE_ID_IBM_PYTHON 0x002d +#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e +#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e +#define PCI_DEVICE_ID_IBM_MPIC 0x0046 +#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d +#define PCI_DEVICE_ID_IBM_CHUKAR 0x0096 +#define PCI_DEVICE_ID_IBM_CPC700 0x00f9 +#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc +#define PCI_DEVICE_ID_IBM_CPC710_PCI32 0x0105 +#define PCI_DEVICE_ID_IBM_405GP 0x0156 +#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd +#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff + +#define PCI_VENDOR_ID_COMPEX2 0x101a /* pci.ids says "AT&T GIS (NCR)" */ +#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 + +#define PCI_VENDOR_ID_WD 0x101c +#define PCI_DEVICE_ID_WD_7197 0x3296 +#define PCI_DEVICE_ID_WD_90C 0xc24a + +#define PCI_VENDOR_ID_AMI 0x101e +#define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960 +#define PCI_DEVICE_ID_AMI_MEGARAID 0x9010 +#define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060 + +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 +#define PCI_DEVICE_ID_AMD_SERENADE 0x36c0 +#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 +#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 +#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C +#define PCI_DEVICE_ID_AMD_FE_GATE_700D 0x700D +#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E +#define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F +#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400 +#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 +#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403 +#define PCI_DEVICE_ID_AMD_COBRA_7404 0x7404 +#define PCI_DEVICE_ID_AMD_VIPER_7408 0x7408 +#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 +#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B +#define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C +#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 +#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 +#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 +#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414 +#define PCI_DEVICE_ID_AMD_OPUS_7440 0x7440 +# define PCI_DEVICE_ID_AMD_VIPER_7440 PCI_DEVICE_ID_AMD_OPUS_7440 +#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441 +# define PCI_DEVICE_ID_AMD_VIPER_7441 PCI_DEVICE_ID_AMD_OPUS_7441 +#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443 +# define PCI_DEVICE_ID_AMD_VIPER_7443 PCI_DEVICE_ID_AMD_OPUS_7443 +#define PCI_DEVICE_ID_AMD_OPUS_7448 0x7448 +# define PCI_DEVICE_ID_AMD_VIPER_7448 PCI_DEVICE_ID_AMD_OPUS_7448 +#define PCI_DEVICE_ID_AMD_OPUS_7449 0x7449 +# define PCI_DEVICE_ID_AMD_VIPER_7449 PCI_DEVICE_ID_AMD_OPUS_7449 +#define PCI_DEVICE_ID_AMD_8111_LAN 0x7462 +#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 +#define PCI_DEVICE_ID_AMD_8111_AC97 0x746d +#define PCI_DEVICE_ID_AMD_8131_APIC 0x7450 + +#define PCI_VENDOR_ID_TRIDENT 0x1023 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001 +#define PCI_DEVICE_ID_TRIDENT_9320 0x9320 +#define PCI_DEVICE_ID_TRIDENT_9388 0x9388 +#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 +#define PCI_DEVICE_ID_TRIDENT_939A 0x939A +#define PCI_DEVICE_ID_TRIDENT_9520 0x9520 +#define PCI_DEVICE_ID_TRIDENT_9525 0x9525 +#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 +#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 +#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 +#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 +#define PCI_DEVICE_ID_TRIDENT_9850 0x9850 +#define PCI_DEVICE_ID_TRIDENT_9880 0x9880 +#define PCI_DEVICE_ID_TRIDENT_8400 0x8400 +#define PCI_DEVICE_ID_TRIDENT_8420 0x8420 +#define PCI_DEVICE_ID_TRIDENT_8500 0x8500 + +#define PCI_VENDOR_ID_AI 0x1025 +#define PCI_DEVICE_ID_AI_M1435 0x1435 + +#define PCI_VENDOR_ID_DELL 0x1028 + +#define PCI_VENDOR_ID_MATROX 0x102B +#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 +#define PCI_DEVICE_ID_MATROX_MIL 0x0519 +#define PCI_DEVICE_ID_MATROX_MYS 0x051A +#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f +#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 +#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000 +#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 +#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 +#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 +#define PCI_DEVICE_ID_MATROX_G400 0x0525 +#define PCI_DEVICE_ID_MATROX_G550 0x2527 +#define PCI_DEVICE_ID_MATROX_VIA 0x4536 + +#define PCI_VENDOR_ID_CT 0x102c +#define PCI_DEVICE_ID_CT_65545 0x00d8 +#define PCI_DEVICE_ID_CT_65548 0x00dc +#define PCI_DEVICE_ID_CT_65550 0x00e0 +#define PCI_DEVICE_ID_CT_65554 0x00e4 +#define PCI_DEVICE_ID_CT_65555 0x00e5 +#define PCI_DEVICE_ID_CT_69000 0x00c0 + +#define PCI_VENDOR_ID_MIRO 0x1031 +#define PCI_DEVICE_ID_MIRO_36050 0x5601 + +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e +#define PCI_DEVICE_ID_NEC_PCX2 0x0046 +#define PCI_DEVICE_ID_NEC_NILE4 0x005a +#define PCI_DEVICE_ID_NEC_VRC5476 0x009b +#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 +#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 + +#define PCI_VENDOR_ID_FD 0x1036 +#define PCI_DEVICE_ID_FD_36C70 0x0000 + +#define PCI_VENDOR_ID_SI 0x1039 +#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 +#define PCI_DEVICE_ID_SI_6202 0x0002 +#define PCI_DEVICE_ID_SI_503 0x0008 +#define PCI_DEVICE_ID_SI_ACPI 0x0009 +#define PCI_DEVICE_ID_SI_180 0x0180 +#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 +#define PCI_DEVICE_ID_SI_6205 0x0205 +#define PCI_DEVICE_ID_SI_501 0x0406 +#define PCI_DEVICE_ID_SI_496 0x0496 +#define PCI_DEVICE_ID_SI_300 0x0300 +#define PCI_DEVICE_ID_SI_315H 0x0310 +#define PCI_DEVICE_ID_SI_315 0x0315 +#define PCI_DEVICE_ID_SI_315PRO 0x0325 +#define PCI_DEVICE_ID_SI_530 0x0530 +#define PCI_DEVICE_ID_SI_540 0x0540 +#define PCI_DEVICE_ID_SI_550 0x0550 +#define PCI_DEVICE_ID_SI_540_VGA 0x5300 +#define PCI_DEVICE_ID_SI_550_VGA 0x5315 +#define PCI_DEVICE_ID_SI_601 0x0601 +#define PCI_DEVICE_ID_SI_620 0x0620 +#define PCI_DEVICE_ID_SI_630 0x0630 +#define PCI_DEVICE_ID_SI_633 0x0633 +#define PCI_DEVICE_ID_SI_635 0x0635 +#define PCI_DEVICE_ID_SI_640 0x0640 +#define PCI_DEVICE_ID_SI_645 0x0645 +#define PCI_DEVICE_ID_SI_646 0x0646 +#define PCI_DEVICE_ID_SI_648 0x0648 +#define PCI_DEVICE_ID_SI_650 0x0650 +#define PCI_DEVICE_ID_SI_651 0x0651 +#define PCI_DEVICE_ID_SI_652 0x0652 +#define PCI_DEVICE_ID_SI_655 0x0655 +#define PCI_DEVICE_ID_SI_730 0x0730 +#define PCI_DEVICE_ID_SI_733 0x0733 +#define PCI_DEVICE_ID_SI_630_VGA 0x6300 +#define PCI_DEVICE_ID_SI_730_VGA 0x7300 +#define PCI_DEVICE_ID_SI_735 0x0735 +#define PCI_DEVICE_ID_SI_740 0x0740 +#define PCI_DEVICE_ID_SI_745 0x0745 +#define PCI_DEVICE_ID_SI_746 0x0746 +#define PCI_DEVICE_ID_SI_748 0x0748 +#define PCI_DEVICE_ID_SI_750 0x0750 +#define PCI_DEVICE_ID_SI_751 0x0751 +#define PCI_DEVICE_ID_SI_752 0x0752 +#define PCI_DEVICE_ID_SI_755 0x0755 +#define PCI_DEVICE_ID_SI_900 0x0900 +#define PCI_DEVICE_ID_SI_5107 0x5107 +#define PCI_DEVICE_ID_SI_5300 0x5300 +#define PCI_DEVICE_ID_SI_5511 0x5511 +#define PCI_DEVICE_ID_SI_5513 0x5513 +#define PCI_DEVICE_ID_SI_5518 0x5518 +#define PCI_DEVICE_ID_SI_5571 0x5571 +#define PCI_DEVICE_ID_SI_5581 0x5581 +#define PCI_DEVICE_ID_SI_5582 0x5582 +#define PCI_DEVICE_ID_SI_5591 0x5591 +#define PCI_DEVICE_ID_SI_5596 0x5596 +#define PCI_DEVICE_ID_SI_5597 0x5597 +#define PCI_DEVICE_ID_SI_5598 0x5598 +#define PCI_DEVICE_ID_SI_5600 0x5600 +#define PCI_DEVICE_ID_SI_6300 0x6300 +#define PCI_DEVICE_ID_SI_6306 0x6306 +#define PCI_DEVICE_ID_SI_6326 0x6326 +#define PCI_DEVICE_ID_SI_7001 0x7001 +#define PCI_DEVICE_ID_SI_7016 0x7016 + +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_DEVICE_ID_HP_DONNER_GFX 0x1008 +#define PCI_DEVICE_ID_HP_TACHYON 0x1028 +#define PCI_DEVICE_ID_HP_TACHLITE 0x1029 +#define PCI_DEVICE_ID_HP_J2585A 0x1030 +#define PCI_DEVICE_ID_HP_J2585B 0x1031 +#define PCI_DEVICE_ID_HP_SAS 0x1048 +#define PCI_DEVICE_ID_HP_DIVA1 0x1049 +#define PCI_DEVICE_ID_HP_DIVA2 0x104A +#define PCI_DEVICE_ID_HP_SP2_0 0x104B +#define PCI_DEVICE_ID_HP_PCI_LBA 0x1054 +#define PCI_DEVICE_ID_HP_REO_SBA 0x10f0 +#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1 +#define PCI_DEVICE_ID_HP_ZX1_SBA 0x1229 +#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a +#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e +#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c + +#define PCI_VENDOR_ID_PCTECH 0x1042 +#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 +#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 + +#define PCI_VENDOR_ID_ASUSTEK 0x1043 +#define PCI_DEVICE_ID_ASUSTEK_0675 0x0675 + +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 + +#define PCI_VENDOR_ID_OPTI 0x1045 +#define PCI_DEVICE_ID_OPTI_92C178 0xc178 +#define PCI_DEVICE_ID_OPTI_82C557 0xc557 +#define PCI_DEVICE_ID_OPTI_82C558 0xc558 +#define PCI_DEVICE_ID_OPTI_82C621 0xc621 +#define PCI_DEVICE_ID_OPTI_82C700 0xc700 +#define PCI_DEVICE_ID_OPTI_82C701 0xc701 +#define PCI_DEVICE_ID_OPTI_82C814 0xc814 +#define PCI_DEVICE_ID_OPTI_82C822 0xc822 +#define PCI_DEVICE_ID_OPTI_82C861 0xc861 +#define PCI_DEVICE_ID_OPTI_82C825 0xd568 + +#define PCI_VENDOR_ID_ELSA 0x1048 +#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 +#define PCI_DEVICE_ID_ELSA_QS3000 0x3000 + +#define PCI_VENDOR_ID_SGS 0x104a +#define PCI_DEVICE_ID_SGS_2000 0x0008 +#define PCI_DEVICE_ID_SGS_1764 0x0009 + +#define PCI_VENDOR_ID_BUSLOGIC 0x104B +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 + +#define PCI_VENDOR_ID_TI 0x104c +#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 +#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 +#define PCI_DEVICE_ID_TI_1130 0xac12 +#define PCI_DEVICE_ID_TI_1031 0xac13 +#define PCI_DEVICE_ID_TI_1131 0xac15 +#define PCI_DEVICE_ID_TI_1250 0xac16 +#define PCI_DEVICE_ID_TI_1220 0xac17 +#define PCI_DEVICE_ID_TI_1221 0xac19 +#define PCI_DEVICE_ID_TI_1210 0xac1a +#define PCI_DEVICE_ID_TI_1410 0xac50 +#define PCI_DEVICE_ID_TI_1450 0xac1b +#define PCI_DEVICE_ID_TI_1225 0xac1c +#define PCI_DEVICE_ID_TI_1251A 0xac1d +#define PCI_DEVICE_ID_TI_1211 0xac1e +#define PCI_DEVICE_ID_TI_1251B 0xac1f +#define PCI_DEVICE_ID_TI_4410 0xac41 +#define PCI_DEVICE_ID_TI_4451 0xac42 +#define PCI_DEVICE_ID_TI_1420 0xac51 +#define PCI_DEVICE_ID_TI_1520 0xac55 +#define PCI_DEVICE_ID_TI_1510 0xac56 + +#define PCI_VENDOR_ID_SONY 0x104d +#define PCI_DEVICE_ID_SONY_CXD3222 0x8039 + +#define PCI_VENDOR_ID_OAK 0x104e +#define PCI_DEVICE_ID_OAK_OTI107 0x0107 + +/* Winbond have two vendor IDs! See 0x10ad as well */ +#define PCI_VENDOR_ID_WINBOND2 0x1050 +#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 +#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a +#define PCI_DEVICE_ID_WINBOND2_6692 0x6692 + +#define PCI_VENDOR_ID_ANIGMA 0x1051 +#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100 + +#define PCI_VENDOR_ID_EFAR 0x1055 +#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130 +#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 +#define PCI_DEVICE_ID_EFAR_SLC90E66_2 0x9462 +#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463 + +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507 +#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 +#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 +#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004 +#define PCI_DEVICE_ID_MOTOROLA_MPC8540 0x0008 +#define PCI_DEVICE_ID_MOTOROLA_MPC8560 0x0009 +#define PCI_DEVICE_ID_MOTOROLA_MPC8265A 0x18c0 +#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 +#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 +#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803 +#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806 +#define PCI_DEVICE_ID_MOTOROLA_MPC190 0x6400 + +#define PCI_VENDOR_ID_PROMISE 0x105a +#define PCI_DEVICE_ID_PROMISE_20265 0x0d30 +#define PCI_DEVICE_ID_PROMISE_20267 0x4d30 +#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 +#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 +#define PCI_DEVICE_ID_PROMISE_20263 0x0D38 +#define PCI_DEVICE_ID_PROMISE_20268 0x4d68 +#define PCI_DEVICE_ID_PROMISE_20270 0x6268 +#define PCI_DEVICE_ID_PROMISE_20269 0x4d69 +#define PCI_DEVICE_ID_PROMISE_20271 0x6269 +#define PCI_DEVICE_ID_PROMISE_20275 0x1275 +#define PCI_DEVICE_ID_PROMISE_20276 0x5275 +#define PCI_DEVICE_ID_PROMISE_20277 0x7275 +#define PCI_DEVICE_ID_PROMISE_5300 0x5300 + +#define PCI_VENDOR_ID_N9 0x105d +#define PCI_DEVICE_ID_N9_I128 0x2309 +#define PCI_DEVICE_ID_N9_I128_2 0x2339 +#define PCI_DEVICE_ID_N9_I128_T2R 0x493d + +#define PCI_VENDOR_ID_UMC 0x1060 +#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 +#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 +#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a +#define PCI_DEVICE_ID_UMC_UM8886A 0x886a +#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 +#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 +#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 +#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 +#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 + +#define PCI_VENDOR_ID_X 0x1061 +#define PCI_DEVICE_ID_X_AGX016 0x0001 + +#define PCI_VENDOR_ID_MYLEX 0x1069 +#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020 +#define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050 +#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 + +#define PCI_VENDOR_ID_PICOP 0x1066 +#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 +#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 + +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 +#define PCI_DEVICE_ID_APPLE_GC 0x0002 +#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e +#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018 +#define PCI_DEVICE_ID_APPLE_KL_USB 0x0019 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 +#define PCI_DEVICE_ID_APPLE_KEYLARGO 0x0022 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024 +#define PCI_DEVICE_ID_APPLE_KEYLARGO_P 0x0025 +#define PCI_DEVICE_ID_APPLE_KL_USB_P 0x0026 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d +#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030 +#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645 + +#define PCI_VENDOR_ID_YAMAHA 0x1073 +#define PCI_DEVICE_ID_YAMAHA_724 0x0004 +#define PCI_DEVICE_ID_YAMAHA_724F 0x000d +#define PCI_DEVICE_ID_YAMAHA_740 0x000a +#define PCI_DEVICE_ID_YAMAHA_740C 0x000c +#define PCI_DEVICE_ID_YAMAHA_744 0x0010 +#define PCI_DEVICE_ID_YAMAHA_754 0x0012 + +#define PCI_VENDOR_ID_NEXGEN 0x1074 +#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 + +#define PCI_VENDOR_ID_QLOGIC 0x1077 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 +#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 +#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 + +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_DEVICE_ID_CYRIX_5510 0x0000 +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 +#define PCI_DEVICE_ID_CYRIX_5520 0x0002 +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 +#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 +#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 + +#define PCI_VENDOR_ID_LEADTEK 0x107d +#define PCI_DEVICE_ID_LEADTEK_805 0x0000 + +#define PCI_VENDOR_ID_INTERPHASE 0x107e +#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 +#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 +#define PCI_DEVICE_ID_INTERPHASE_5575 0x0008 + +#define PCI_VENDOR_ID_CONTAQ 0x1080 +#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 +#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 + +#define PCI_VENDOR_ID_FOREX 0x1083 + +#define PCI_VENDOR_ID_OLICOM 0x108d +#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 +#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 +#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 +#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 +#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 +#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 + +#define PCI_VENDOR_ID_SUN 0x108e +#define PCI_DEVICE_ID_SUN_EBUS 0x1000 +#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 +#define PCI_DEVICE_ID_SUN_RIO_EBUS 0x1100 +#define PCI_DEVICE_ID_SUN_RIO_GEM 0x1101 +#define PCI_DEVICE_ID_SUN_RIO_1394 0x1102 +#define PCI_DEVICE_ID_SUN_RIO_USB 0x1103 +#define PCI_DEVICE_ID_SUN_GEM 0x2bad +#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 +#define PCI_DEVICE_ID_SUN_PBM 0x8000 +#define PCI_DEVICE_ID_SUN_SCHIZO 0x8001 +#define PCI_DEVICE_ID_SUN_SABRE 0xa000 +#define PCI_DEVICE_ID_SUN_HUMMINGBIRD 0xa001 +#define PCI_DEVICE_ID_SUN_TOMATILLO 0xa801 + +#define PCI_VENDOR_ID_CMD 0x1095 +#define PCI_DEVICE_ID_SII_1210SA 0x0240 + +#define PCI_DEVICE_ID_CMD_640 0x0640 +#define PCI_DEVICE_ID_CMD_643 0x0643 +#define PCI_DEVICE_ID_CMD_646 0x0646 +#define PCI_DEVICE_ID_CMD_647 0x0647 +#define PCI_DEVICE_ID_CMD_648 0x0648 +#define PCI_DEVICE_ID_CMD_649 0x0649 +#define PCI_DEVICE_ID_CMD_670 0x0670 + +#define PCI_DEVICE_ID_SII_680 0x0680 +#define PCI_DEVICE_ID_SII_3112 0x3112 + +#define PCI_VENDOR_ID_VISION 0x1098 +#define PCI_DEVICE_ID_VISION_QD8500 0x0001 +#define PCI_DEVICE_ID_VISION_QD8580 0x0002 + +#define PCI_VENDOR_ID_BROOKTREE 0x109e +#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 +#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 +#define PCI_DEVICE_ID_BROOKTREE_878_1 0x036e +#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 +#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 + +#define PCI_VENDOR_ID_SIERRA 0x10a8 +#define PCI_DEVICE_ID_SIERRA_STB 0x0000 + +#define PCI_VENDOR_ID_SGI 0x10a9 +#define PCI_DEVICE_ID_SGI_IOC3 0x0003 +#define PCI_DEVICE_ID_SGI_IOC4 0x100a + +#define PCI_VENDOR_ID_ACC 0x10aa +#define PCI_DEVICE_ID_ACC_2056 0x0000 + +#define PCI_VENDOR_ID_WINBOND 0x10ad +#define PCI_DEVICE_ID_WINBOND_83769 0x0001 +#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 +#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 + +#define PCI_VENDOR_ID_DATABOOK 0x10b3 +#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 + +#define PCI_VENDOR_ID_PLX 0x10b5 +#define PCI_DEVICE_ID_PLX_R685 0x1030 +#define PCI_DEVICE_ID_PLX_ROMULUS 0x106a +#define PCI_DEVICE_ID_PLX_SPCOM800 0x1076 +#define PCI_DEVICE_ID_PLX_1077 0x1077 +#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 +#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 +#define PCI_DEVICE_ID_PLX_R753 0x1152 +#define PCI_DEVICE_ID_PLX_9050 0x9050 +#define PCI_DEVICE_ID_PLX_9060 0x9060 +#define PCI_DEVICE_ID_PLX_9060ES 0x906E +#define PCI_DEVICE_ID_PLX_9060SD 0x906D +#define PCI_DEVICE_ID_PLX_9080 0x9080 +#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 + +#define PCI_VENDOR_ID_MADGE 0x10b6 +#define PCI_DEVICE_ID_MADGE_MK2 0x0002 +#define PCI_DEVICE_ID_MADGE_C155S 0x1001 + +#define PCI_VENDOR_ID_3COM 0x10b7 +#define PCI_DEVICE_ID_3COM_3C985 0x0001 +#define PCI_DEVICE_ID_3COM_3C339 0x3390 +#define PCI_DEVICE_ID_3COM_3C590 0x5900 +#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 +#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 +#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 +#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 +#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 +#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 +#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 +#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 +#define PCI_DEVICE_ID_3COM_3CR990 0x9900 +#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902 +#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903 +#define PCI_DEVICE_ID_3COM_3CR990B 0x9904 +#define PCI_DEVICE_ID_3COM_3CR990_FX 0x9905 +#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908 +#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 +#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a + +#define PCI_VENDOR_ID_SMC 0x10b8 +#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 + +#define PCI_VENDOR_ID_AL 0x10b9 +#define PCI_DEVICE_ID_AL_M1445 0x1445 +#define PCI_DEVICE_ID_AL_M1449 0x1449 +#define PCI_DEVICE_ID_AL_M1451 0x1451 +#define PCI_DEVICE_ID_AL_M1461 0x1461 +#define PCI_DEVICE_ID_AL_M1489 0x1489 +#define PCI_DEVICE_ID_AL_M1511 0x1511 +#define PCI_DEVICE_ID_AL_M1513 0x1513 +#define PCI_DEVICE_ID_AL_M1521 0x1521 +#define PCI_DEVICE_ID_AL_M1523 0x1523 +#define PCI_DEVICE_ID_AL_M1531 0x1531 +#define PCI_DEVICE_ID_AL_M1533 0x1533 +#define PCI_DEVICE_ID_AL_M1535 0x1535 +#define PCI_DEVICE_ID_AL_M1541 0x1541 +#define PCI_DEVICE_ID_AL_M1621 0x1621 +#define PCI_DEVICE_ID_AL_M1631 0x1631 +#define PCI_DEVICE_ID_AL_M1641 0x1641 +#define PCI_DEVICE_ID_AL_M1644 0x1644 +#define PCI_DEVICE_ID_AL_M1647 0x1647 +#define PCI_DEVICE_ID_AL_M1651 0x1651 +#define PCI_DEVICE_ID_AL_M1543 0x1543 +#define PCI_DEVICE_ID_AL_M3307 0x3307 +#define PCI_DEVICE_ID_AL_M4803 0x5215 +#define PCI_DEVICE_ID_AL_M5219 0x5219 +#define PCI_DEVICE_ID_AL_M5229 0x5229 +#define PCI_DEVICE_ID_AL_M5237 0x5237 +#define PCI_DEVICE_ID_AL_M5243 0x5243 +#define PCI_DEVICE_ID_AL_M5451 0x5451 +#define PCI_DEVICE_ID_AL_M7101 0x7101 + +#define PCI_VENDOR_ID_MITSUBISHI 0x10ba + +#define PCI_VENDOR_ID_SURECOM 0x10bd +#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 + +#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083 + +#define PCI_VENDOR_ID_ASP 0x10cd +#define PCI_DEVICE_ID_ASP_ABP940 0x1200 +#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 +#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 + +#define PCI_VENDOR_ID_MACRONIX 0x10d9 +#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 +#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 + +#define PCI_VENDOR_ID_TCONRAD 0x10da +#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 + +#define PCI_VENDOR_ID_CERN 0x10dc +#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 +#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 +#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 +#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 + +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 +#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 +#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 +#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C +#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE 0x0085 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA 0x008e +#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S 0x00e1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA 0x00e3 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE 0x00e5 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2 0x00ee +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 +#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 +#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 +#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc +#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203 + +#define PCI_VENDOR_ID_IMS 0x10e0 +#define PCI_DEVICE_ID_IMS_8849 0x8849 +#define PCI_DEVICE_ID_IMS_TT128 0x9128 +#define PCI_DEVICE_ID_IMS_TT3D 0x9135 + +#define PCI_VENDOR_ID_TEKRAM2 0x10e1 +#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c + +#define PCI_VENDOR_ID_TUNDRA 0x10e3 +#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 + +#define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 +#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062 +#define PCI_DEVICE_ID_AMCC_S5933 0x807d +#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c + +#define PCI_VENDOR_ID_INTERG 0x10ea +#define PCI_DEVICE_ID_INTERG_1680 0x1680 +#define PCI_DEVICE_ID_INTERG_1682 0x1682 +#define PCI_DEVICE_ID_INTERG_2000 0x2000 +#define PCI_DEVICE_ID_INTERG_2010 0x2010 +#define PCI_DEVICE_ID_INTERG_5000 0x5000 +#define PCI_DEVICE_ID_INTERG_5050 0x5050 + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_8029 0x8029 +#define PCI_DEVICE_ID_REALTEK_8129 0x8129 +#define PCI_DEVICE_ID_REALTEK_8139 0x8139 +#define PCI_DEVICE_ID_REALTEK_8169 0x8169 + +#define PCI_VENDOR_ID_XILINX 0x10ee +#define PCI_DEVICE_ID_TURBOPAM 0x4020 + +#define PCI_VENDOR_ID_TRUEVISION 0x10fa +#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c + +#define PCI_VENDOR_ID_INIT 0x1101 +#define PCI_DEVICE_ID_INIT_320P 0x9100 +#define PCI_DEVICE_ID_INIT_360P 0x9500 + +#define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */ +#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002 + +#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */ +#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938 + +#define PCI_VENDOR_ID_TTI 0x1103 +#define PCI_DEVICE_ID_TTI_HPT343 0x0003 +#define PCI_DEVICE_ID_TTI_HPT366 0x0004 +#define PCI_DEVICE_ID_TTI_HPT372 0x0005 +#define PCI_DEVICE_ID_TTI_HPT302 0x0006 +#define PCI_DEVICE_ID_TTI_HPT371 0x0007 +#define PCI_DEVICE_ID_TTI_HPT374 0x0008 +#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 /* appoarently a 372N variant? */ + +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_8363_0 0x0305 +#define PCI_DEVICE_ID_VIA_8371_0 0x0391 +#define PCI_DEVICE_ID_VIA_8501_0 0x0501 +#define PCI_DEVICE_ID_VIA_82C505 0x0505 +#define PCI_DEVICE_ID_VIA_82C561 0x0561 +#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 +#define PCI_DEVICE_ID_VIA_82C576 0x0576 +#define PCI_DEVICE_ID_VIA_82C585 0x0585 +#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 +#define PCI_DEVICE_ID_VIA_82C595 0x0595 +#define PCI_DEVICE_ID_VIA_82C596 0x0596 +#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 +#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 +#define PCI_DEVICE_ID_VIA_8601_0 0x0601 +#define PCI_DEVICE_ID_VIA_8605_0 0x0605 +#define PCI_DEVICE_ID_VIA_82C680 0x0680 +#define PCI_DEVICE_ID_VIA_82C686 0x0686 +#define PCI_DEVICE_ID_VIA_82C691 0x0691 +#define PCI_DEVICE_ID_VIA_82C693 0x0693 +#define PCI_DEVICE_ID_VIA_82C693_1 0x0698 +#define PCI_DEVICE_ID_VIA_82C926 0x0926 +#define PCI_DEVICE_ID_VIA_82C576_1 0x1571 +#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 +#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 +#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 +#define PCI_DEVICE_ID_VIA_6305 0x3044 +#define PCI_DEVICE_ID_VIA_82C596_3 0x3050 +#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051 +#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 +#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 +#define PCI_DEVICE_ID_VIA_8233_5 0x3059 +#define PCI_DEVICE_ID_VIA_8233_7 0x3065 +#define PCI_DEVICE_ID_VIA_82C686_6 0x3068 +#define PCI_DEVICE_ID_VIA_8233_0 0x3074 +#define PCI_DEVICE_ID_VIA_8633_0 0x3091 +#define PCI_DEVICE_ID_VIA_8367_0 0x3099 +#define PCI_DEVICE_ID_VIA_8622 0x3102 +#define PCI_DEVICE_ID_VIA_8233C_0 0x3109 +#define PCI_DEVICE_ID_VIA_8361 0x3112 +#define PCI_DEVICE_ID_VIA_8375 0x3116 +#define PCI_DEVICE_ID_VIA_CLE266 0x3123 +#define PCI_DEVICE_ID_VIA_8233A 0x3147 +#define PCI_DEVICE_ID_VIA_P4M266 0x3148 +#define PCI_DEVICE_ID_VIA_8237_SATA 0x3149 +#define PCI_DEVICE_ID_VIA_P4X333 0x3168 +#define PCI_DEVICE_ID_VIA_8235 0x3177 +#define PCI_DEVICE_ID_VIA_8377_0 0x3189 +#define PCI_DEVICE_ID_VIA_K8T400M_0 0x3188 +#define PCI_DEVICE_ID_VIA_8237 0x3227 +#define PCI_DEVICE_ID_VIA_86C100A 0x6100 +#define PCI_DEVICE_ID_VIA_8231 0x8231 +#define PCI_DEVICE_ID_VIA_8231_4 0x8235 +#define PCI_DEVICE_ID_VIA_8365_1 0x8305 +#define PCI_DEVICE_ID_VIA_8371_1 0x8391 +#define PCI_DEVICE_ID_VIA_8501_1 0x8501 +#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 +#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 +#define PCI_DEVICE_ID_VIA_8601_1 0x8601 +#define PCI_DEVICE_ID_VIA_8505_1 0x8605 +#define PCI_DEVICE_ID_VIA_8633_1 0xB091 +#define PCI_DEVICE_ID_VIA_8367_1 0xB099 + +#define PCI_VENDOR_ID_SIEMENS 0x110A +#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 + +#define PCI_VENDOR_ID_SMC2 0x1113 +#define PCI_DEVICE_ID_SMC2_1211TX 0x1211 + +#define PCI_VENDOR_ID_VORTEX 0x1119 +#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 +#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 +#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 +#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 +#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 +#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 +#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 +#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 +#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 +#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 +#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a +#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b +#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c +#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 + +#define PCI_VENDOR_ID_EF 0x111a +#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 +#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 + +#define PCI_VENDOR_ID_IDT 0x111d +#define PCI_DEVICE_ID_IDT_IDT77201 0x0001 + +#define PCI_VENDOR_ID_FORE 0x1127 +#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 +#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 + +#define PCI_VENDOR_ID_IMAGINGTECH 0x112f +#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 + +#define PCI_VENDOR_ID_PHILIPS 0x1131 +#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145 +#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 +#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 + +#define PCI_VENDOR_ID_EICON 0x1133 +#define PCI_DEVICE_ID_EICON_DIVA20PRO 0xe001 +#define PCI_DEVICE_ID_EICON_DIVA20 0xe002 +#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003 +#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004 +#define PCI_DEVICE_ID_EICON_DIVA201 0xe005 +#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b +#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010 +#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012 +#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013 +#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014 + +#define PCI_VENDOR_ID_CYCLONE 0x113c +#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 + +#define PCI_VENDOR_ID_ALLIANCE 0x1142 +#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 +#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 +#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 +#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d + +#define PCI_VENDOR_ID_SYSKONNECT 0x1148 +#define PCI_DEVICE_ID_SYSKONNECT_FP 0x4000 +#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 +#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 +#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320 +#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 +#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 + +#define PCI_VENDOR_ID_VMIC 0x114a +#define PCI_DEVICE_ID_VMIC_VME 0x7587 + +#define PCI_VENDOR_ID_DIGI 0x114f +#define PCI_DEVICE_ID_DIGI_EPC 0x0002 +#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 +#define PCI_DEVICE_ID_DIGI_XEM 0x0004 +#define PCI_DEVICE_ID_DIGI_XR 0x0005 +#define PCI_DEVICE_ID_DIGI_CX 0x0006 +#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 +#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a +#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 +#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072 +#define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073 + +#define PCI_VENDOR_ID_MUTECH 0x1159 +#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 + +#define PCI_VENDOR_ID_XIRCOM 0x115d +#define PCI_DEVICE_ID_XIRCOM_X3201_ETH 0x0003 +#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 + +#define PCI_VENDOR_ID_RENDITION 0x1163 +#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 +#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 + +#define PCI_VENDOR_ID_SERVERWORKS 0x1166 +#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 +#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 +#define PCI_DEVICE_ID_SERVERWORKS_CIOB30 0x0010 +#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011 +#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB +#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230 + +#define PCI_VENDOR_ID_SBE 0x1176 +#define PCI_DEVICE_ID_SBE_WANXL100 0x0301 +#define PCI_DEVICE_ID_SBE_WANXL200 0x0302 +#define PCI_DEVICE_ID_SBE_WANXL400 0x0104 + +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO 0x0102 +#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f + +#define PCI_VENDOR_ID_TOSHIBA_2 0x102f +#define PCI_DEVICE_ID_TOSHIBA_TX3927 0x000a +#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 +#define PCI_DEVICE_ID_TOSHIBA_TX4927 0x0180 + +#define PCI_VENDOR_ID_RICOH 0x1180 +#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 +#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 +#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 +#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 +#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 + +#define PCI_VENDOR_ID_ARTOP 0x1191 +#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 +#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 +#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 +#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 +#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008 +#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009 +#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 +#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 +#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 +#define PCI_DEVICE_ID_ARTOP_AEC7612S 0x8030 +#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040 +#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050 +#define PCI_DEVICE_ID_ARTOP_8060 0x8060 + +#define PCI_VENDOR_ID_ZEITNET 0x1193 +#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 +#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 + +#define PCI_VENDOR_ID_OMEGA 0x119b +#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 + +#define PCI_VENDOR_ID_FUJITSU_ME 0x119e +#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 +#define PCI_DEVICE_ID_FUJITSU_FS50 0x0003 + +#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9 +#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 + +#define PCI_VENDOR_ID_GALILEO 0x11ab +#define PCI_DEVICE_ID_GALILEO_GT64011 0x4146 +#define PCI_DEVICE_ID_GALILEO_GT64111 0x4146 +#define PCI_DEVICE_ID_GALILEO_GT96100 0x9652 +#define PCI_DEVICE_ID_GALILEO_GT96100A 0x9653 + +#define PCI_VENDOR_ID_LITEON 0x11ad +#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 + +#define PCI_VENDOR_ID_V3 0x11b0 +#define PCI_DEVICE_ID_V3_V960 0x0001 +#define PCI_DEVICE_ID_V3_V350 0x0001 +#define PCI_DEVICE_ID_V3_V961 0x0002 +#define PCI_DEVICE_ID_V3_V351 0x0002 + +#define PCI_VENDOR_ID_NP 0x11bc +#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 + +#define PCI_VENDOR_ID_ATT 0x11c1 +#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 +#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 + +#define PCI_VENDOR_ID_SPECIALIX 0x11cb +#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 +#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 +#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 +#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 + +#define PCI_VENDOR_ID_AURAVISION 0x11d1 +#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 + +#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 +#define PCI_DEVICE_ID_AD1889JS 0x1889 + +#define PCI_VENDOR_ID_IKON 0x11d5 +#define PCI_DEVICE_ID_IKON_10115 0x0115 +#define PCI_DEVICE_ID_IKON_10117 0x0117 + +#define PCI_VENDOR_ID_ZORAN 0x11de +#define PCI_DEVICE_ID_ZORAN_36057 0x6057 +#define PCI_DEVICE_ID_ZORAN_36120 0x6120 + +#define PCI_VENDOR_ID_KINETIC 0x11f4 +#define PCI_DEVICE_ID_KINETIC_2915 0x2915 + +#define PCI_VENDOR_ID_COMPEX 0x11f6 +#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 +#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 + +#define PCI_VENDOR_ID_RP 0x11fe +#define PCI_DEVICE_ID_RP32INTF 0x0001 +#define PCI_DEVICE_ID_RP8INTF 0x0002 +#define PCI_DEVICE_ID_RP16INTF 0x0003 +#define PCI_DEVICE_ID_RP4QUAD 0x0004 +#define PCI_DEVICE_ID_RP8OCTA 0x0005 +#define PCI_DEVICE_ID_RP8J 0x0006 +#define PCI_DEVICE_ID_RPP4 0x000A +#define PCI_DEVICE_ID_RPP8 0x000B +#define PCI_DEVICE_ID_RP8M 0x000C + +#define PCI_VENDOR_ID_CYCLADES 0x120e +#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 +#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 +#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102 +#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103 +#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104 +#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105 +#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 +#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 +#define PCI_DEVICE_ID_PC300_RX_2 0x0300 +#define PCI_DEVICE_ID_PC300_RX_1 0x0301 +#define PCI_DEVICE_ID_PC300_TE_2 0x0310 +#define PCI_DEVICE_ID_PC300_TE_1 0x0311 + +#define PCI_VENDOR_ID_ESSENTIAL 0x120f +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 + +#define PCI_VENDOR_ID_O2 0x1217 +#define PCI_DEVICE_ID_O2_6729 0x6729 +#define PCI_DEVICE_ID_O2_6730 0x673a +#define PCI_DEVICE_ID_O2_6832 0x6832 +#define PCI_DEVICE_ID_O2_6836 0x6836 + +#define PCI_VENDOR_ID_3DFX 0x121a +#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 +#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 +#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003 +#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 + +#define PCI_VENDOR_ID_SIGMADES 0x1236 +#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 + +#define PCI_VENDOR_ID_CCUBE 0x123f + +#define PCI_VENDOR_ID_AVM 0x1244 +#define PCI_DEVICE_ID_AVM_B1 0x0700 +#define PCI_DEVICE_ID_AVM_C4 0x0800 +#define PCI_DEVICE_ID_AVM_A1 0x0a00 +#define PCI_DEVICE_ID_AVM_A1_V2 0x0e00 +#define PCI_DEVICE_ID_AVM_C2 0x1100 +#define PCI_DEVICE_ID_AVM_T1 0x1200 + +#define PCI_VENDOR_ID_DIPIX 0x1246 + +#define PCI_VENDOR_ID_STALLION 0x124d +#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 +#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 +#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 + +#define PCI_VENDOR_ID_OPTIBASE 0x1255 +#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 +#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 +#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 +#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 +#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 + +#define PCI_VENDOR_ID_ESS 0x125d +#define PCI_DEVICE_ID_ESS_ESS1968 0x1968 +#define PCI_DEVICE_ID_ESS_AUDIOPCI 0x1969 +#define PCI_DEVICE_ID_ESS_ESS1978 0x1978 + +#define PCI_VENDOR_ID_SATSAGEM 0x1267 +#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 +#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 +#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b + +#define PCI_VENDOR_ID_SMI 0x126f +#define PCI_DEVICE_ID_SMI_710 0x0710 +#define PCI_DEVICE_ID_SMI_712 0x0712 +#define PCI_DEVICE_ID_SMI_810 0x0810 + +#define PCI_VENDOR_ID_HUGHES 0x1273 +#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 + +#define PCI_VENDOR_ID_ENSONIQ 0x1274 +#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 +#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 +#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 + +#define PCI_VENDOR_ID_ROCKWELL 0x127A + +#define PCI_VENDOR_ID_DAVICOM 0x1282 +#define PCI_DEVICE_ID_DAVICOM_DM9102A 0x9102 + +#define PCI_VENDOR_ID_ITE 0x1283 +#define PCI_DEVICE_ID_ITE_IT8172G 0x8172 +#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 +#define PCI_DEVICE_ID_ITE_IT8181 0x8181 +#define PCI_DEVICE_ID_ITE_8872 0x8872 + +#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 + +/* formerly Platform Tech */ +#define PCI_VENDOR_ID_ESS_OLD 0x1285 +#define PCI_DEVICE_ID_ESS_ESS0100 0x0100 + +#define PCI_VENDOR_ID_ALTEON 0x12ae +#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001 + +#define PCI_VENDOR_ID_USR 0x12B9 + +#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B + +#define PCI_VENDOR_ID_PICTUREL 0x12c5 +#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 + +#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 + +#define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16 0x0011 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC 0x0041 +#define PCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4 0xF001 +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8 0xF010 + +#define PCI_VENDOR_ID_AUREAL 0x12eb +#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001 +#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002 + +#define PCI_VENDOR_ID_CBOARDS 0x1307 +#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 + +#define PCI_VENDOR_ID_SIIG 0x131f +#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 +#define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001 +#define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012 +#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020 +#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021 +#define PCI_DEVICE_ID_SIIG_2S_10x_550 0x1030 +#define PCI_DEVICE_ID_SIIG_2S_10x_650 0x1031 +#define PCI_DEVICE_ID_SIIG_2S_10x_850 0x1032 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036 +#define PCI_DEVICE_ID_SIIG_4S_10x_550 0x1050 +#define PCI_DEVICE_ID_SIIG_4S_10x_650 0x1051 +#define PCI_DEVICE_ID_SIIG_4S_10x_850 0x1052 +#define PCI_DEVICE_ID_SIIG_1S_20x_550 0x2000 +#define PCI_DEVICE_ID_SIIG_1S_20x_650 0x2001 +#define PCI_DEVICE_ID_SIIG_1S_20x_850 0x2002 +#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020 +#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021 +#define PCI_DEVICE_ID_SIIG_2S_20x_550 0x2030 +#define PCI_DEVICE_ID_SIIG_2S_20x_650 0x2031 +#define PCI_DEVICE_ID_SIIG_2S_20x_850 0x2032 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012 +#define PCI_DEVICE_ID_SIIG_4S_20x_550 0x2050 +#define PCI_DEVICE_ID_SIIG_4S_20x_650 0x2051 +#define PCI_DEVICE_ID_SIIG_4S_20x_850 0x2052 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 + +#define PCI_VENDOR_ID_DOMEX 0x134a +#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 + +#define PCI_VENDOR_ID_QUATECH 0x135C +#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 +#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 +#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030 +#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040 +#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 +#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 + +#define PCI_VENDOR_ID_SEALEVEL 0x135e +#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 +#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 +#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 + +#define PCI_VENDOR_ID_HYPERCOPE 0x1365 +#define PCI_DEVICE_ID_HYPERCOPE_PLX 0x9050 +#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO 0x0104 +#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106 +#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107 +#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108 +#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS 0x0109 + +#define PCI_VENDOR_ID_KAWASAKI 0x136b +#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01 + +#define PCI_VENDOR_ID_LMC 0x1376 +#define PCI_DEVICE_ID_LMC_HSSI 0x0003 +#define PCI_DEVICE_ID_LMC_DS3 0x0004 +#define PCI_DEVICE_ID_LMC_SSI 0x0005 +#define PCI_DEVICE_ID_LMC_T1 0x0006 + +#define PCI_VENDOR_ID_NETGEAR 0x1385 +#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a +#define PCI_DEVICE_ID_NETGEAR_GA622 0x622a + +#define PCI_VENDOR_ID_APPLICOM 0x1389 +#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001 +#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002 +#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003 + +#define PCI_VENDOR_ID_MOXA 0x1393 +#define PCI_DEVICE_ID_MOXA_C104 0x1040 +#define PCI_DEVICE_ID_MOXA_C168 0x1680 +#define PCI_DEVICE_ID_MOXA_CP204J 0x2040 +#define PCI_DEVICE_ID_MOXA_C218 0x2180 +#define PCI_DEVICE_ID_MOXA_C320 0x3200 + +#define PCI_VENDOR_ID_CCD 0x1397 +#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0 +#define PCI_DEVICE_ID_CCD_B000 0xb000 +#define PCI_DEVICE_ID_CCD_B006 0xb006 +#define PCI_DEVICE_ID_CCD_B007 0xb007 +#define PCI_DEVICE_ID_CCD_B008 0xb008 +#define PCI_DEVICE_ID_CCD_B009 0xb009 +#define PCI_DEVICE_ID_CCD_B00A 0xb00a +#define PCI_DEVICE_ID_CCD_B00B 0xb00b +#define PCI_DEVICE_ID_CCD_B00C 0xb00c +#define PCI_DEVICE_ID_CCD_B100 0xb100 + +#define PCI_VENDOR_ID_3WARE 0x13C1 +#define PCI_DEVICE_ID_3WARE_1000 0x1000 + +#define PCI_VENDOR_ID_ABOCOM 0x13D1 +#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 + +#define PCI_VENDOR_ID_CMEDIA 0x13f6 +#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 +#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 +#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 +#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 + +#define PCI_VENDOR_ID_LAVA 0x1407 +#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ +#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_A 0x0180 /* 4x 16550A, half of 8 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_B 0x0181 /* 4x 16550A, half of 8 port */ +#define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */ +#define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_SSERIAL 0x0500 /* 1x 16550 */ +#define PCI_DEVICE_ID_LAVA_PORT_650 0x0600 /* 1x 16650 */ +#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000 +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */ +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */ +#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800 + +#define PCI_VENDOR_ID_TIMEDIA 0x1409 +#define PCI_DEVICE_ID_TIMEDIA_1889 0x7168 + +#define PCI_VENDOR_ID_OXSEMI 0x1415 +#define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403 +#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501 +#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511 +#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513 +#define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521 + +#define PCI_VENDOR_ID_AIRONET 0x14b9 +#define PCI_DEVICE_ID_AIRONET_4800_1 0x0001 +#define PCI_DEVICE_ID_AIRONET_4800 0x4500 /* values switched? see */ +#define PCI_DEVICE_ID_AIRONET_4500 0x4800 /* drivers/net/aironet4500_card.c */ + +#define PCI_VENDOR_ID_TITAN 0x14D2 +#define PCI_DEVICE_ID_TITAN_010L 0x8001 +#define PCI_DEVICE_ID_TITAN_100L 0x8010 +#define PCI_DEVICE_ID_TITAN_110L 0x8011 +#define PCI_DEVICE_ID_TITAN_200L 0x8020 +#define PCI_DEVICE_ID_TITAN_210L 0x8021 +#define PCI_DEVICE_ID_TITAN_400L 0x8040 +#define PCI_DEVICE_ID_TITAN_800L 0x8080 +#define PCI_DEVICE_ID_TITAN_100 0xA001 +#define PCI_DEVICE_ID_TITAN_200 0xA005 +#define PCI_DEVICE_ID_TITAN_400 0xA003 +#define PCI_DEVICE_ID_TITAN_800B 0xA004 + +#define PCI_VENDOR_ID_PANACOM 0x14d4 +#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 +#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 + +#define PCI_VENDOR_ID_AFAVLAB 0x14db +#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 + +#define PCI_VENDOR_ID_BROADCOM 0x14e4 +#define PCI_DEVICE_ID_TIGON3_5700 0x1644 +#define PCI_DEVICE_ID_TIGON3_5701 0x1645 +#define PCI_DEVICE_ID_TIGON3_5702 0x1646 +#define PCI_DEVICE_ID_TIGON3_5703 0x1647 +#define PCI_DEVICE_ID_TIGON3_5704 0x1648 +#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649 +#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d +#define PCI_DEVICE_ID_TIGON3_5705 0x1653 +#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 +#define PCI_DEVICE_ID_TIGON3_5705M 0x165d +#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e +#define PCI_DEVICE_ID_TIGON3_5705F 0x166e +#define PCI_DEVICE_ID_TIGON3_5782 0x1696 +#define PCI_DEVICE_ID_TIGON3_5788 0x169c +#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 +#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 +#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 +#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 +#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 +#define PCI_DEVICE_ID_TIGON3_5901 0x170d +#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e +#define PCI_DEVICE_ID_BCM4401 0x4401 + +#define PCI_VENDOR_ID_ENE 0x1524 +#define PCI_DEVICE_ID_ENE_1211 0x1211 +#define PCI_DEVICE_ID_ENE_1225 0x1225 +#define PCI_DEVICE_ID_ENE_1410 0x1410 +#define PCI_DEVICE_ID_ENE_1420 0x1420 + +#define PCI_VENDOR_ID_SYBA 0x1592 +#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 +#define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 + +#define PCI_VENDOR_ID_MORETON 0x15aa +#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000 + +#define PCI_VENDOR_ID_ZOLTRIX 0x15b0 +#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0 + +#define PCI_VENDOR_ID_PDC 0x15e9 +#define PCI_DEVICE_ID_PDC_ADMA100 0x1841 + +#define PCI_VENDOR_ID_ALTIMA 0x173b +#define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 +#define PCI_DEVICE_ID_ALTIMA_AC1001 0x03e9 +#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea +#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb + +#define PCI_VENDOR_ID_SYMPHONY 0x1c1c +#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 + +#define PCI_VENDOR_ID_TEKRAM 0x1de1 +#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 + +#define PCI_VENDOR_ID_HINT 0x3388 +#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + +#define PCI_VENDOR_ID_3DLABS 0x3d3d +#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 +#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 +#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 +#define PCI_DEVICE_ID_3DLABS_MX 0x0006 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 +#define PCI_DEVICE_ID_3DLABS_GAMMA 0x0008 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 + +#define PCI_VENDOR_ID_AVANCE 0x4005 +#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 +#define PCI_DEVICE_ID_AVANCE_2302 0x2302 + +#define PCI_VENDOR_ID_AKS 0x416c +#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 +#define PCI_DEVICE_ID_AKS_CPC 0x0200 + +#define PCI_VENDOR_ID_REDCREEK 0x4916 +#define PCI_DEVICE_ID_RC45 0x1960 + +#define PCI_VENDOR_ID_NETVIN 0x4a14 +#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 + +#define PCI_VENDOR_ID_S3 0x5333 +#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 +#define PCI_DEVICE_ID_S3_ViRGE 0x5631 +#define PCI_DEVICE_ID_S3_TRIO 0x8811 +#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 +#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 +#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d +#define PCI_DEVICE_ID_S3_868 0x8880 +#define PCI_DEVICE_ID_S3_928 0x88b0 +#define PCI_DEVICE_ID_S3_864_1 0x88c0 +#define PCI_DEVICE_ID_S3_864_2 0x88c1 +#define PCI_DEVICE_ID_S3_964_1 0x88d0 +#define PCI_DEVICE_ID_S3_964_2 0x88d1 +#define PCI_DEVICE_ID_S3_968 0x88f0 +#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 +#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 +#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 +#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 +#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 +#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 +#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 +#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 + +#define PCI_VENDOR_ID_DUNORD 0x5544 +#define PCI_DEVICE_ID_DUNORD_I3000 0x0001 +#define PCI_VENDOR_ID_GENROCO 0x5555 +#define PCI_DEVICE_ID_GENROCO_HFP832 0x0003 + +#define PCI_VENDOR_ID_DCI 0x6666 +#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 +#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_21145 0x0039 +#define PCI_DEVICE_ID_INTEL_21152BB 0xb152 +#define PCI_DEVICE_ID_INTEL_82375 0x0482 +#define PCI_DEVICE_ID_INTEL_82424 0x0483 +#define PCI_DEVICE_ID_INTEL_82378 0x0484 +#define PCI_DEVICE_ID_INTEL_82430 0x0486 +#define PCI_DEVICE_ID_INTEL_82434 0x04a3 +#define PCI_DEVICE_ID_INTEL_I960 0x0960 +#define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_82542 0x1000 +#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001 +#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004 +#define PCI_DEVICE_ID_INTEL_82544EI_COPPER 0x1008 +#define PCI_DEVICE_ID_INTEL_82544EI_FIBER 0x1009 +#define PCI_DEVICE_ID_INTEL_82544GC_COPPER 0x100C +#define PCI_DEVICE_ID_INTEL_82544GC_LOM 0x100D +#define PCI_DEVICE_ID_INTEL_82540EM 0x100E +#define PCI_DEVICE_ID_INTEL_82545EM_COPPER 0x100F +#define PCI_DEVICE_ID_INTEL_82546EB_COPPER 0x1010 +#define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011 +#define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012 +#define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015 +#define PCI_DEVICE_ID_INTEL_82559 0x1030 + +#define PCI_DEVICE_ID_INTEL_82562ET 0x1031 + +#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130 + +#define PCI_DEVICE_ID_INTEL_82559ER 0x1209 +#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 +#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 +#define PCI_DEVICE_ID_INTEL_7116 0x1223 +#define PCI_DEVICE_ID_INTEL_7205_0 0x255d +#define PCI_DEVICE_ID_INTEL_82596 0x1226 +#define PCI_DEVICE_ID_INTEL_82865 0x1227 +#define PCI_DEVICE_ID_INTEL_82557 0x1229 +#define PCI_DEVICE_ID_INTEL_82437 0x122d +#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e +#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 +#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 +#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_82380FB 0x124b +#define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 +#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 +#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 +#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 +#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 +#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 +#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 +#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 +#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 +#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 +#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 +#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 +#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 +#define PCI_DEVICE_ID_INTEL_82801AA_2 0x2412 +#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 +#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 +#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416 +#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418 +#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420 +#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421 +#define PCI_DEVICE_ID_INTEL_82801AB_2 0x2422 +#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423 +#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425 +#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426 +#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428 +#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440 +#define PCI_DEVICE_ID_INTEL_82801BA_1 0x2442 +#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443 +#define PCI_DEVICE_ID_INTEL_82801BA_3 0x2444 +#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445 +#define PCI_DEVICE_ID_INTEL_82801BA_5 0x2446 +#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448 +#define PCI_DEVICE_ID_INTEL_82801BA_7 0x2449 +#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a +#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b +#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e +#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450 +#define PCI_DEVICE_ID_INTEL_82801E_2 0x2452 +#define PCI_DEVICE_ID_INTEL_82801E_3 0x2453 +#define PCI_DEVICE_ID_INTEL_82801E_9 0x2459 +#define PCI_DEVICE_ID_INTEL_82801E_11 0x245B +#define PCI_DEVICE_ID_INTEL_82801E_14 0x245D +#define PCI_DEVICE_ID_INTEL_82801E_15 0x245E +#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480 +#define PCI_DEVICE_ID_INTEL_82801CA_2 0x2482 +#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 +#define PCI_DEVICE_ID_INTEL_82801CA_4 0x2484 +#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485 +#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486 +#define PCI_DEVICE_ID_INTEL_82801CA_7 0x2487 +#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a +#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b +#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c +#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0 +#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2 +#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3 +#define PCI_DEVICE_ID_INTEL_82801DB_4 0x24c4 +#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5 +#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6 +#define PCI_DEVICE_ID_INTEL_82801DB_7 0x24c7 +#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca +#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb +#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc +#define PCI_DEVICE_ID_INTEL_82801DB_13 0x24cd +#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0 +#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1 +#define PCI_DEVICE_ID_INTEL_82801EB_2 0x24d2 +#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3 +#define PCI_DEVICE_ID_INTEL_82801EB_4 0x24d4 +#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5 +#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6 +#define PCI_DEVICE_ID_INTEL_82801EB_7 0x24d7 +#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca +#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db +#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd +#define PCI_DEVICE_ID_INTEL_ESB_0 0x25a0 +#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1 +#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2 +#define PCI_DEVICE_ID_INTEL_ESB_3 0x25a3 +#define PCI_DEVICE_ID_INTEL_ESB_31 0x25b0 +#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4 +#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6 +#define PCI_DEVICE_ID_INTEL_ESB_6 0x25a7 +#define PCI_DEVICE_ID_INTEL_ESB_7 0x25a9 +#define PCI_DEVICE_ID_INTEL_ESB_8 0x25aa +#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab +#define PCI_DEVICE_ID_INTEL_ESB_11 0x25ac +#define PCI_DEVICE_ID_INTEL_ESB_12 0x25ad +#define PCI_DEVICE_ID_INTEL_ESB_13 0x25ae +#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 +#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641 +#define PCI_DEVICE_ID_INTEL_ICH6_2 0x266f +#define PCI_DEVICE_ID_INTEL_ICH6_3 0x266e +#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530 +#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 +#define PCI_DEVICE_ID_INTEL_80310 0x530d +#define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 +#define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 +#define PCI_DEVICE_ID_INTEL_82810_MC3 0x7122 +#define PCI_DEVICE_ID_INTEL_82810_IG3 0x7123 +#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 +#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 +#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 +#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 +#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198 +#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199 +#define PCI_DEVICE_ID_INTEL_82443MX_2 0x719a +#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b +#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0 +#define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1 +#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2 +#define PCI_DEVICE_ID_INTEL_82372FB_0 0x7600 +#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 +#define PCI_DEVICE_ID_INTEL_82372FB_2 0x7602 +#define PCI_DEVICE_ID_INTEL_82372FB_3 0x7603 +#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 +#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 +#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca +#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb + +#define PCI_VENDOR_ID_COMPUTONE 0x8e0e +#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 +#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 +#define PCI_SUBVENDOR_ID_COMPUTONE 0x8e0e +#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003 + +#define PCI_VENDOR_ID_KTI 0x8e2e +#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 + +#define PCI_VENDOR_ID_ADAPTEC 0x9004 +#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 +#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178 +#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 +#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 +#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 +#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 +#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 +#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 +#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 +#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 +#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 +#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 +#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 +#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 +#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 +#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 +#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 +#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 +#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 +#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 +#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 +#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578 +#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 +#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 +#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 +#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 + +#define PCI_VENDOR_ID_ADAPTEC2 0x9005 +#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 +#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 +#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013 +#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f +#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 +#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051 +#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f +#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080 +#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081 +#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083 +#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f +#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0 +#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 +#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 +#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf + +#define PCI_VENDOR_ID_ATRONICS 0x907f +#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 + +#define PCI_VENDOR_ID_HOLTEK 0x9412 +#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 + +#define PCI_VENDOR_ID_NETMOS 0x9710 +#define PCI_DEVICE_ID_NETMOS_9735 0x9735 +#define PCI_DEVICE_ID_NETMOS_9835 0x9835 + +#define PCI_SUBVENDOR_ID_EXSYS 0xd84d +#define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 +#define PCI_SUBDEVICE_ID_EXSYS_4055 0x4055 + +#define PCI_VENDOR_ID_TIGERJET 0xe159 +#define PCI_DEVICE_ID_TIGERJET_300 0x0001 +#define PCI_DEVICE_ID_TIGERJET_100 0x0002 + +#define PCI_VENDOR_ID_ARK 0xedd8 +#define PCI_DEVICE_ID_ARK_STING 0xa091 +#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 +#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 + +#define PCI_VENDOR_ID_MICROGATE 0x13c0 +#define PCI_DEVICE_ID_MICROGATE_USC 0x0010 +#define PCI_DEVICE_ID_MICROGATE_SCC 0x0020 +#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 diff --git a/include/pcmcia.h b/include/pcmcia.h new file mode 100644 index 0000000..43d4510 --- /dev/null +++ b/include/pcmcia.h @@ -0,0 +1,311 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PCMCIA_H +#define _PCMCIA_H + +#include +#include + +/* + * Allow configuration to select PCMCIA slot, + * or try to generate a useful default + */ +#if ( CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \ + ((CONFIG_COMMANDS & CFG_CMD_IDE) && \ + (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) + +#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) + + /* The RPX series use SLOT_B */ +#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) +# define CONFIG_PCMCIA_SLOT_B +#elif defined(CONFIG_ADS) /* The ADS board uses SLOT_A */ +# define CONFIG_PCMCIA_SLOT_A +#elif defined(CONFIG_FADS) /* The FADS series are a mess */ +# if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) +# define CONFIG_PCMCIA_SLOT_A +# else +# define CONFIG_PCMCIA_SLOT_B +# endif +#elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx) +# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ +#elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */ +# define CONFIG_PCMCIA_SLOT_B +#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */ +# define CONFIG_PCMCIA_SLOT_A +#elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */ +# define CONFIG_PCMCIA_SLOT_B +#elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */ +# define CONFIG_PCMCIA_SLOT_B +#elif defined(CONFIG_C2MON) /* The C2MON use SLOT_B */ +# define CONFIG_PCMCIA_SLOT_B +#elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */ +# define CONFIG_PCMCIA_SLOT_B +#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ +# define CONFIG_PCMCIA_SLOT_A +#elif defined(CONFIG_NETTA) +# define CONFIG_PCMCIA_SLOT_A +#elif defined(CONFIG_UC100) /* The UC100 use SLOT_B */ +# define CONFIG_PCMCIA_SLOT_B +#else +# error "PCMCIA Slot not configured" +#endif + +#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ + +/* Make sure exactly one slot is defined - we support only one for now */ +#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) +#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured +#endif +#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) +#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured +#endif + +#ifndef PCMCIA_SOCKETS_NO +#define PCMCIA_SOCKETS_NO 1 +#endif +#ifndef PCMCIA_MEM_WIN_NO +#define PCMCIA_MEM_WIN_NO 4 +#endif +#define PCMCIA_IO_WIN_NO 2 + +/* define _slot_ to be able to optimize macros */ +#ifdef CONFIG_PCMCIA_SLOT_A +# define _slot_ 0 +# define PCMCIA_SLOT_MSG "slot A" +# define PCMCIA_SLOT_x PCMCIA_PSLOT_A +#else +# define _slot_ 1 +# define PCMCIA_SLOT_MSG "slot B" +# define PCMCIA_SLOT_x PCMCIA_PSLOT_B +#endif + +/* + * The TQM850L hardware has two pins swapped! Grrrrgh! + */ +#ifdef CONFIG_TQM850L +#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE +#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET +#else +#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET +#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE +#endif + +/* + * This structure is used to address each window in the PCMCIA controller. + * + * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly + * after pcmcia_win_t[n]... + */ + +typedef struct { + ulong br; + ulong or; +} pcmcia_win_t; + +/* + * Definitions for PCMCIA control registers to operate in IDE mode + * + * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) + * to be done later (depending on CPU clock) + */ + +/* Window 0: + * Base: 0xFE100000 CS1 + * Port Size: 2 Bytes + * Port Size: 16 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR0 0xFE100000 +#define CFG_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ + | PCMCIA_PPS_16 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_SLOT_x \ + | PCMCIA_PV \ + ) + +/* Window 1: + * Base: 0xFE100080 CS1 + * Port Size: 8 Bytes + * Port Size: 8 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR1 0xFE100080 +#define CFG_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ + | PCMCIA_PPS_8 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_SLOT_x \ + | PCMCIA_PV \ + ) + +/* Window 2: + * Base: 0xFE100100 CS2 + * Port Size: 8 Bytes + * Port Size: 8 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR2 0xFE100100 +#define CFG_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ + | PCMCIA_PPS_8 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_SLOT_x \ + | PCMCIA_PV \ + ) + +/* Window 3: + * not used + */ +#define CFG_PCMCIA_PBR3 0 +#define CFG_PCMCIA_POR3 0 + +/* Window 4: + * Base: 0xFE100C00 CS1 + * Port Size: 2 Bytes + * Port Size: 16 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR4 0xFE100C00 +#define CFG_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ + | PCMCIA_PPS_16 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_SLOT_x \ + | PCMCIA_PV \ + ) + +/* Window 5: + * Base: 0xFE100C80 CS1 + * Port Size: 8 Bytes + * Port Size: 8 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR5 0xFE100C80 +#define CFG_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ + | PCMCIA_PPS_8 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_SLOT_x \ + | PCMCIA_PV \ + ) + +/* Window 6: + * Base: 0xFE100D00 CS2 + * Port Size: 8 Bytes + * Port Size: 8 Bit + * Common Memory Space + */ + +#define CFG_PCMCIA_PBR6 0xFE100D00 +#define CFG_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ + | PCMCIA_PPS_8 \ + | PCMCIA_PRS_MEM \ + | PCMCIA_SLOT_x \ + | PCMCIA_PV \ + ) + +/* Window 7: + * not used + */ +#define CFG_PCMCIA_PBR7 0 +#define CFG_PCMCIA_POR7 0 + +/**********************************************************************/ + +/* + * CIS Tupel codes + */ +#define CISTPL_NULL 0x00 +#define CISTPL_DEVICE 0x01 +#define CISTPL_LONGLINK_CB 0x02 +#define CISTPL_INDIRECT 0x03 +#define CISTPL_CONFIG_CB 0x04 +#define CISTPL_CFTABLE_ENTRY_CB 0x05 +#define CISTPL_LONGLINK_MFC 0x06 +#define CISTPL_BAR 0x07 +#define CISTPL_PWR_MGMNT 0x08 +#define CISTPL_EXTDEVICE 0x09 +#define CISTPL_CHECKSUM 0x10 +#define CISTPL_LONGLINK_A 0x11 +#define CISTPL_LONGLINK_C 0x12 +#define CISTPL_LINKTARGET 0x13 +#define CISTPL_NO_LINK 0x14 +#define CISTPL_VERS_1 0x15 +#define CISTPL_ALTSTR 0x16 +#define CISTPL_DEVICE_A 0x17 +#define CISTPL_JEDEC_C 0x18 +#define CISTPL_JEDEC_A 0x19 +#define CISTPL_CONFIG 0x1a +#define CISTPL_CFTABLE_ENTRY 0x1b +#define CISTPL_DEVICE_OC 0x1c +#define CISTPL_DEVICE_OA 0x1d +#define CISTPL_DEVICE_GEO 0x1e +#define CISTPL_DEVICE_GEO_A 0x1f +#define CISTPL_MANFID 0x20 +#define CISTPL_FUNCID 0x21 +#define CISTPL_FUNCE 0x22 +#define CISTPL_SWIL 0x23 +#define CISTPL_END 0xff + +/* + * CIS Function ID codes + */ +#define CISTPL_FUNCID_MULTI 0x00 +#define CISTPL_FUNCID_MEMORY 0x01 +#define CISTPL_FUNCID_SERIAL 0x02 +#define CISTPL_FUNCID_PARALLEL 0x03 +#define CISTPL_FUNCID_FIXED 0x04 +#define CISTPL_FUNCID_VIDEO 0x05 +#define CISTPL_FUNCID_NETWORK 0x06 +#define CISTPL_FUNCID_AIMS 0x07 +#define CISTPL_FUNCID_SCSI 0x08 + +/* + * Fixed Disk FUNCE codes + */ +#define CISTPL_IDE_INTERFACE 0x01 + +#define CISTPL_FUNCE_IDE_IFACE 0x01 +#define CISTPL_FUNCE_IDE_MASTER 0x02 +#define CISTPL_FUNCE_IDE_SLAVE 0x03 + +/* First feature byte */ +#define CISTPL_IDE_SILICON 0x04 +#define CISTPL_IDE_UNIQUE 0x08 +#define CISTPL_IDE_DUAL 0x10 + +/* Second feature byte */ +#define CISTPL_IDE_HAS_SLEEP 0x01 +#define CISTPL_IDE_HAS_STANDBY 0x02 +#define CISTPL_IDE_HAS_IDLE 0x04 +#define CISTPL_IDE_LOW_POWER 0x08 +#define CISTPL_IDE_REG_INHIBIT 0x10 +#define CISTPL_IDE_HAS_INDEX 0x20 +#define CISTPL_IDE_IOIS16 0x40 + +#endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */ + +#endif /* _PCMCIA_H */ diff --git a/include/pcmcia/cirrus.h b/include/pcmcia/cirrus.h new file mode 100644 index 0000000..cd34dd8 --- /dev/null +++ b/include/pcmcia/cirrus.h @@ -0,0 +1,180 @@ +/* + * cirrus.h 1.4 1999/10/25 20:03:34 + * + * The contents of this file are subject to the Mozilla Public License + * Version 1.1 (the "License"); you may not use this file except in + * compliance with the License. You may obtain a copy of the License + * at http://www.mozilla.org/MPL/ + * + * Software distributed under the License is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See + * the License for the specific language governing rights and + * limitations under the License. + * + * The initial developer of the original code is David A. Hinds + * . Portions created by David A. Hinds + * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in which + * case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use + * your version of this file under the MPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the MPL or the GPL. + */ + +#ifndef _LINUX_CIRRUS_H +#define _LINUX_CIRRUS_H + +#ifndef PCI_VENDOR_ID_CIRRUS +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#endif +#ifndef PCI_DEVICE_ID_CIRRUS_6729 +#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 +#endif +#ifndef PCI_DEVICE_ID_CIRRUS_6832 +#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 +#endif + +#define PD67_MISC_CTL_1 0x16 /* Misc control 1 */ +#define PD67_FIFO_CTL 0x17 /* FIFO control */ +#define PD67_MISC_CTL_2 0x1E /* Misc control 2 */ +#define PD67_CHIP_INFO 0x1f /* Chip information */ +#define PD67_ATA_CTL 0x026 /* 6730: ATA control */ +#define PD67_EXT_INDEX 0x2e /* Extension index */ +#define PD67_EXT_DATA 0x2f /* Extension data */ + +/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */ +#define PD67_DATA_MASK0 0x01 /* Data mask 0 */ +#define PD67_DATA_MASK1 0x02 /* Data mask 1 */ +#define PD67_DMA_CTL 0x03 /* DMA control */ + +/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */ +#define PD67_EXT_CTL_1 0x03 /* Extension control 1 */ +#define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */ +#define PD67_EXTERN_DATA 0x0a +#define PD67_MISC_CTL_3 0x25 +#define PD67_SMB_PWR_CTL 0x26 + +/* I/O window address offset */ +#define PD67_IO_OFF(w) (0x36+((w)<<1)) + +/* Timing register sets */ +#define PD67_TIME_SETUP(n) (0x3a + 3*(n)) +#define PD67_TIME_CMD(n) (0x3b + 3*(n)) +#define PD67_TIME_RECOV(n) (0x3c + 3*(n)) + +/* Flags for PD67_MISC_CTL_1 */ +#define PD67_MC1_5V_DET 0x01 /* 5v detect */ +#define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */ +#define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */ +#define PD67_MC1_PULSE_MGMT 0x04 +#define PD67_MC1_PULSE_IRQ 0x08 +#define PD67_MC1_SPKR_ENA 0x10 +#define PD67_MC1_INPACK_ENA 0x80 + +/* Flags for PD67_FIFO_CTL */ +#define PD67_FIFO_EMPTY 0x80 + +/* Flags for PD67_MISC_CTL_2 */ +#define PD67_MC2_FREQ_BYPASS 0x01 +#define PD67_MC2_DYNAMIC_MODE 0x02 +#define PD67_MC2_SUSPEND 0x04 +#define PD67_MC2_5V_CORE 0x08 +#define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */ +#define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */ +#define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */ +#define PD67_MC2_DMA_MODE 0x40 +#define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */ + +/* Flags for PD67_CHIP_INFO */ +#define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */ +#define PD67_INFO_CHIP_ID 0xc0 +#define PD67_INFO_REV 0x1c + +/* Fields in PD67_TIME_* registers */ +#define PD67_TIME_SCALE 0xc0 +#define PD67_TIME_SCALE_1 0x00 +#define PD67_TIME_SCALE_16 0x40 +#define PD67_TIME_SCALE_256 0x80 +#define PD67_TIME_SCALE_4096 0xc0 +#define PD67_TIME_MULT 0x3f + +/* Fields in PD67_DMA_CTL */ +#define PD67_DMA_MODE 0xc0 +#define PD67_DMA_OFF 0x00 +#define PD67_DMA_DREQ_INPACK 0x40 +#define PD67_DMA_DREQ_WP 0x80 +#define PD67_DMA_DREQ_BVD2 0xc0 +#define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */ + +/* Fields in PD67_EXT_CTL_1 */ +#define PD67_EC1_VCC_PWR_LOCK 0x01 +#define PD67_EC1_AUTO_PWR_CLEAR 0x02 +#define PD67_EC1_LED_ENA 0x04 +#define PD67_EC1_INV_CARD_IRQ 0x08 +#define PD67_EC1_INV_MGMT_IRQ 0x10 +#define PD67_EC1_PULLUP_CTL 0x20 + +/* Fields in PD67_MISC_CTL_3 */ +#define PD67_MC3_IRQ_MASK 0x03 +#define PD67_MC3_IRQ_PCPCI 0x00 +#define PD67_MC3_IRQ_EXTERN 0x01 +#define PD67_MC3_IRQ_PCIWAY 0x02 +#define PD67_MC3_IRQ_PCI 0x03 +#define PD67_MC3_PWR_MASK 0x0c +#define PD67_MC3_PWR_SERIAL 0x00 +#define PD67_MC3_PWR_TI2202 0x08 +#define PD67_MC3_PWR_SMB 0x0c + +/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */ + +/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */ +#define PD68_EXT_CTL_2 0x0b +#define PD68_PCI_SPACE 0x22 +#define PD68_PCCARD_SPACE 0x23 +#define PD68_WINDOW_TYPE 0x24 +#define PD68_EXT_CSC 0x2e +#define PD68_MISC_CTL_4 0x2f +#define PD68_MISC_CTL_5 0x30 +#define PD68_MISC_CTL_6 0x31 + +/* Extra flags in PD67_MISC_CTL_3 */ +#define PD68_MC3_HW_SUSP 0x10 +#define PD68_MC3_MM_EXPAND 0x40 +#define PD68_MC3_MM_ARM 0x80 + +/* Bridge Control Register */ +#define PD6832_BCR_MGMT_IRQ_ENA 0x0800 + +/* Socket Number Register */ +#define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */ + + +typedef struct cirrus_state_t { + u_char misc1, misc2; + u_char timer[6]; +} cirrus_state_t; + +/* Cirrus options */ +static int has_dma = -1; +static int has_led = -1; +static int has_ring = -1; +static int dynamic_mode = 0; +static int freq_bypass = -1; +#ifdef CONFIG_CPC45 +static int setup_time = 2; +static int cmd_time = 6; +static int recov_time = 1; +#else +static int setup_time = -1; +static int cmd_time = -1; +static int recov_time = -1; +#endif + + +#endif /* _LINUX_CIRRUS_H */ diff --git a/include/pcmcia/i82365.h b/include/pcmcia/i82365.h new file mode 100644 index 0000000..0b432a8 --- /dev/null +++ b/include/pcmcia/i82365.h @@ -0,0 +1,154 @@ +/* + * i82365.h 1.21 2001/08/24 12:15:33 + * + * The contents of this file are subject to the Mozilla Public License + * Version 1.1 (the "License"); you may not use this file except in + * compliance with the License. You may obtain a copy of the License + * at http://www.mozilla.org/MPL/ + * + * Software distributed under the License is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See + * the License for the specific language governing rights and + * limitations under the License. + * + * The initial developer of the original code is David A. Hinds + * . Portions created by David A. Hinds + * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use + * your version of this file under the MPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the MPL or the GPL. + */ + +#ifndef _LINUX_I82365_H +#define _LINUX_I82365_H + +/* register definitions for the Intel 82365SL PCMCIA controller */ + +/* Offsets for PCIC registers */ +#define I365_IDENT 0x00 /* Identification and revision */ +#define I365_STATUS 0x01 /* Interface status */ +#define I365_POWER 0x02 /* Power and RESETDRV control */ +#define I365_INTCTL 0x03 /* Interrupt and general control */ +#define I365_CSC 0x04 /* Card status change */ +#define I365_CSCINT 0x05 /* Card status change interrupt control */ +#define I365_ADDRWIN 0x06 /* Address window enable */ +#define I365_IOCTL 0x07 /* I/O control */ +#define I365_GENCTL 0x16 /* Card detect and general control */ +#define I365_GBLCTL 0x1E /* Global control register */ + +/* Offsets for I/O and memory window registers */ +#define I365_IO(map) (0x08+((map)<<2)) +#define I365_MEM(map) (0x10+((map)<<3)) +#define I365_W_START 0 +#define I365_W_STOP 2 +#define I365_W_OFF 4 + +/* Flags for I365_STATUS */ +#define I365_CS_BVD1 0x01 +#define I365_CS_STSCHG 0x01 +#define I365_CS_BVD2 0x02 +#define I365_CS_SPKR 0x02 +#define I365_CS_DETECT 0x0C +#define I365_CS_WRPROT 0x10 +#define I365_CS_READY 0x20 /* Inverted */ +#define I365_CS_POWERON 0x40 +#define I365_CS_GPI 0x80 + +/* Flags for I365_POWER */ +#define I365_PWR_OFF 0x00 /* Turn off the socket */ +#define I365_PWR_OUT 0x80 /* Output enable */ +#define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */ +#define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */ +#define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */ +/* There are different layouts for B-step and DF-step chips: the B + step has independent Vpp1/Vpp2 control, and the DF step has only + Vpp1 control, plus 3V control */ +#define I365_VCC_5V 0x10 /* Vcc = 5.0v */ +#define I365_VCC_3V 0x18 /* Vcc = 3.3v */ +#define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */ +#define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */ +#define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */ +#define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */ +#define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */ +#define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */ + +/* Flags for I365_INTCTL */ +#define I365_RING_ENA 0x80 +#define I365_PC_RESET 0x40 +#define I365_PC_IOCARD 0x20 +#define I365_INTR_ENA 0x10 +#define I365_IRQ_MASK 0x0F + +/* Flags for I365_CSC and I365_CSCINT*/ +#define I365_CSC_BVD1 0x01 +#define I365_CSC_STSCHG 0x01 +#define I365_CSC_BVD2 0x02 +#define I365_CSC_READY 0x04 +#define I365_CSC_DETECT 0x08 +#define I365_CSC_ANY 0x0F +#define I365_CSC_GPI 0x10 + +/* Flags for I365_ADDRWIN */ +#define I365_ADDR_MEMCS16 0x20 +#define I365_ENA_IO(map) (0x40 << (map)) +#define I365_ENA_MEM(map) (0x01 << (map)) + +/* Flags for I365_IOCTL */ +#define I365_IOCTL_MASK(map) (0x0F << (map<<2)) +#define I365_IOCTL_WAIT(map) (0x08 << (map<<2)) +#define I365_IOCTL_0WS(map) (0x04 << (map<<2)) +#define I365_IOCTL_IOCS16(map) (0x02 << (map<<2)) +#define I365_IOCTL_16BIT(map) (0x01 << (map<<2)) + +/* Flags for I365_GENCTL */ +#define I365_CTL_16DELAY 0x01 +#define I365_CTL_RESET 0x02 +#define I365_CTL_GPI_ENA 0x04 +#define I365_CTL_GPI_CTL 0x08 +#define I365_CTL_RESUME 0x10 +#define I365_CTL_SW_IRQ 0x20 + +/* Flags for I365_GBLCTL */ +#define I365_GBL_PWRDOWN 0x01 +#define I365_GBL_CSC_LEV 0x02 +#define I365_GBL_WRBACK 0x04 +#define I365_GBL_IRQ_0_LEV 0x08 +#define I365_GBL_IRQ_1_LEV 0x10 + +/* Flags for memory window registers */ +#define I365_MEM_16BIT 0x8000 /* In memory start high byte */ +#define I365_MEM_0WS 0x4000 +#define I365_MEM_WS1 0x8000 /* In memory stop high byte */ +#define I365_MEM_WS0 0x4000 +#define I365_MEM_WRPROT 0x8000 /* In offset high byte */ +#define I365_MEM_REG 0x4000 + +#define I365_REG(slot, reg) (((slot) << 6) | (reg)) + +/* Default ISA interrupt mask */ +#define I365_ISA_IRQ_MASK 0xdeb8 /* irq's 3-5,7,9-12,14,15 */ + +/* Device ID's for PCI-to-PCMCIA bridges */ + +#ifndef PCI_VENDOR_ID_INTEL +#define PCI_VENDOR_ID_INTEL 0x8086 +#endif +#ifndef PCI_DEVICE_ID_INTEL_82092AA_0 +#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 +#endif +#ifndef PCI_VENDOR_ID_OMEGA +#define PCI_VENDOR_ID_OMEGA 0x119b +#endif +#ifndef PCI_DEVICE_ID_OMEGA_82C092G +#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 +#endif + +#endif /* _LINUX_I82365_H */ diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h new file mode 100644 index 0000000..aafae8a --- /dev/null +++ b/include/pcmcia/ss.h @@ -0,0 +1,133 @@ +/* + * ss.h 1.31 2001/08/24 12:16:13 + * + * The contents of this file are subject to the Mozilla Public License + * Version 1.1 (the "License"); you may not use this file except in + * compliance with the License. You may obtain a copy of the License + * at http://www.mozilla.org/MPL/ + * + * Software distributed under the License is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See + * the License for the specific language governing rights and + * limitations under the License. + * + * The initial developer of the original code is David A. Hinds + * . Portions created by David A. Hinds + * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use + * your version of this file under the MPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the MPL or the GPL. + */ + +#ifndef _LINUX_SS_H +#define _LINUX_SS_H + +/* For RegisterCallback */ +typedef struct ss_callback_t { + void (*handler)(void *info, u_int events); + void *info; +} ss_callback_t; + +/* Definitions for card status flags for GetStatus */ +#define SS_WRPROT 0x0001 +#define SS_CARDLOCK 0x0002 +#define SS_EJECTION 0x0004 +#define SS_INSERTION 0x0008 +#define SS_BATDEAD 0x0010 +#define SS_BATWARN 0x0020 +#define SS_READY 0x0040 +#define SS_DETECT 0x0080 +#define SS_POWERON 0x0100 +#define SS_GPI 0x0200 +#define SS_STSCHG 0x0400 +#define SS_CARDBUS 0x0800 +#define SS_3VCARD 0x1000 +#define SS_XVCARD 0x2000 +#define SS_PENDING 0x4000 + +/* for InquireSocket */ +typedef struct socket_cap_t { + u_int features; + u_int irq_mask; + u_int map_size; + u_char pci_irq; + u_char cardbus; + struct pci_bus *cb_bus; + struct bus_operations *bus; +} socket_cap_t; + +/* InquireSocket capabilities */ +#define SS_CAP_PAGE_REGS 0x0001 +#define SS_CAP_VIRTUAL_BUS 0x0002 +#define SS_CAP_MEM_ALIGN 0x0004 +#define SS_CAP_STATIC_MAP 0x0008 +#define SS_CAP_PCCARD 0x4000 +#define SS_CAP_CARDBUS 0x8000 + +/* for GetSocket, SetSocket */ +typedef struct socket_state_t { + u_int flags; + u_int csc_mask; + u_char Vcc, Vpp; + u_char io_irq; +} socket_state_t; + +/* Socket configuration flags */ +#define SS_PWR_AUTO 0x0010 +#define SS_IOCARD 0x0020 +#define SS_RESET 0x0040 +#define SS_DMA_MODE 0x0080 +#define SS_SPKR_ENA 0x0100 +#define SS_OUTPUT_ENA 0x0200 +#define SS_ZVCARD 0x0400 + +/* Flags for I/O port and memory windows */ +#define MAP_ACTIVE 0x01 +#define MAP_16BIT 0x02 +#define MAP_AUTOSZ 0x04 +#define MAP_0WS 0x08 +#define MAP_WRPROT 0x10 +#define MAP_ATTRIB 0x20 +#define MAP_USE_WAIT 0x40 +#define MAP_PREFETCH 0x80 + +/* Use this just for bridge windows */ +#define MAP_IOSPACE 0x20 + +typedef struct pccard_io_map { + u_char map; + u_char flags; + u_short speed; + u_short start, stop; +} pccard_io_map; + +typedef struct pccard_mem_map { + u_char map; + u_char flags; + u_short speed; + u_long sys_start, sys_stop; + u_int card_start; +} pccard_mem_map; + +typedef struct cb_bridge_map { + u_char map; + u_char flags; + u_int start, stop; +} cb_bridge_map; + +enum ss_service { + SS_RegisterCallback, SS_InquireSocket, + SS_GetStatus, SS_GetSocket, SS_SetSocket, + SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap, + SS_GetBridge, SS_SetBridge, SS_ProcSetup +}; + +#endif /* _LINUX_SS_H */ diff --git a/include/pcmcia/ti113x.h b/include/pcmcia/ti113x.h new file mode 100644 index 0000000..5453588 --- /dev/null +++ b/include/pcmcia/ti113x.h @@ -0,0 +1,234 @@ +/* + * ti113x.h 1.31 2002/05/12 18:19:47 + * + * The contents of this file are subject to the Mozilla Public License + * Version 1.1 (the "License"); you may not use this file except in + * compliance with the License. You may obtain a copy of the License + * at http://www.mozilla.org/MPL/ + * + * Software distributed under the License is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See + * the License for the specific language governing rights and + * limitations under the License. + * + * The initial developer of the original code is David A. Hinds + * . Portions created by David A. Hinds + * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use + * your version of this file under the MPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the MPL or the GPL. + */ + +#ifndef _LINUX_TI113X_H +#define _LINUX_TI113X_H + +#ifndef PCI_VENDOR_ID_TI +#define PCI_VENDOR_ID_TI 0x104c +#endif + +#ifndef PCI_DEVICE_ID_TI_1130 +#define PCI_DEVICE_ID_TI_1130 0xac12 +#endif +#ifndef PCI_DEVICE_ID_TI_1031 +#define PCI_DEVICE_ID_TI_1031 0xac13 +#endif +#ifndef PCI_DEVICE_ID_TI_1131 +#define PCI_DEVICE_ID_TI_1131 0xac15 +#endif +#ifndef PCI_DEVICE_ID_TI_1210 +#define PCI_DEVICE_ID_TI_1210 0xac1a +#endif +#ifndef PCI_DEVICE_ID_TI_1211 +#define PCI_DEVICE_ID_TI_1211 0xac1e +#endif +#ifndef PCI_DEVICE_ID_TI_1220 +#define PCI_DEVICE_ID_TI_1220 0xac17 +#endif +#ifndef PCI_DEVICE_ID_TI_1221 +#define PCI_DEVICE_ID_TI_1221 0xac19 +#endif +#ifndef PCI_DEVICE_ID_TI_1250A +#define PCI_DEVICE_ID_TI_1250A 0xac16 +#endif +#ifndef PCI_DEVICE_ID_TI_1225 +#define PCI_DEVICE_ID_TI_1225 0xac1c +#endif +#ifndef PCI_DEVICE_ID_TI_1251A +#define PCI_DEVICE_ID_TI_1251A 0xac1d +#endif +#ifndef PCI_DEVICE_ID_TI_1251B +#define PCI_DEVICE_ID_TI_1251B 0xac1f +#endif +#ifndef PCI_DEVICE_ID_TI_1410 +#define PCI_DEVICE_ID_TI_1410 0xac50 +#endif +#ifndef PCI_DEVICE_ID_TI_1420 +#define PCI_DEVICE_ID_TI_1420 0xac51 +#endif +#ifndef PCI_DEVICE_ID_TI_1450 +#define PCI_DEVICE_ID_TI_1450 0xac1b +#endif +#ifndef PCI_DEVICE_ID_TI_1451 +#define PCI_DEVICE_ID_TI_1451 0xac52 +#endif +#ifndef PCI_DEVICE_ID_TI_1510 +#define PCI_DEVICE_ID_TI_1510 0xac56 +#endif +#ifndef PCI_DEVICE_ID_TI_4410 +#define PCI_DEVICE_ID_TI_4410 0xac41 +#endif +#ifndef PCI_DEVICE_ID_TI_4450 +#define PCI_DEVICE_ID_TI_4450 0xac40 +#endif +#ifndef PCI_DEVICE_ID_TI_4451 +#define PCI_DEVICE_ID_TI_4451 0xac42 +#endif + +/* Register definitions for TI 113X PCI-to-CardBus bridges */ + +/* System Control Register */ +#define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */ +#define TI113X_SCR_SMIROUTE 0x04000000 +#define TI113X_SCR_SMISTATUS 0x02000000 +#define TI113X_SCR_SMIENB 0x01000000 +#define TI113X_SCR_VCCPROT 0x00200000 +#define TI113X_SCR_REDUCEZV 0x00100000 +#define TI113X_SCR_CDREQEN 0x00080000 +#define TI113X_SCR_CDMACHAN 0x00070000 +#define TI113X_SCR_SOCACTIVE 0x00002000 +#define TI113X_SCR_PWRSTREAM 0x00000800 +#define TI113X_SCR_DELAYUP 0x00000400 +#define TI113X_SCR_DELAYDOWN 0x00000200 +#define TI113X_SCR_INTERROGATE 0x00000100 +#define TI113X_SCR_CLKRUN_SEL 0x00000080 +#define TI113X_SCR_PWRSAVINGS 0x00000040 +#define TI113X_SCR_SUBSYSRW 0x00000020 +#define TI113X_SCR_CB_DPAR 0x00000010 +#define TI113X_SCR_CDMA_EN 0x00000008 +#define TI113X_SCR_ASYNC_IRQ 0x00000004 +#define TI113X_SCR_KEEPCLK 0x00000002 +#define TI113X_SCR_CLKRUN_ENA 0x00000001 + +#define TI122X_SCR_SER_STEP 0xc0000000 +#define TI122X_SCR_INTRTIE 0x20000000 +#define TI122X_SCR_P2CCLK 0x08000000 +#define TI122X_SCR_CBRSVD 0x00400000 +#define TI122X_SCR_MRBURSTDN 0x00008000 +#define TI122X_SCR_MRBURSTUP 0x00004000 +#define TI122X_SCR_RIMUX 0x00000001 + +/* Multimedia Control Register */ +#define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */ +#define TI1250_MMC_ZVOUTEN 0x80 +#define TI1250_MMC_PORTSEL 0x40 +#define TI1250_MMC_ZVEN1 0x02 +#define TI1250_MMC_ZVEN0 0x01 + +#define TI1250_GENERAL_STATUS 0x85 /* 8 bit */ +#define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */ +#define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */ +#define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */ +#define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */ +#define TI12XX_IRQMUX 0x8c /* 32 bit */ + +/* Retry Status Register */ +#define TI113X_RETRY_STATUS 0x90 /* 8 bit */ +#define TI113X_RSR_PCIRETRY 0x80 +#define TI113X_RSR_CBRETRY 0x40 +#define TI113X_RSR_TEXP_CBB 0x20 +#define TI113X_RSR_MEXP_CBB 0x10 +#define TI113X_RSR_TEXP_CBA 0x08 +#define TI113X_RSR_MEXP_CBA 0x04 +#define TI113X_RSR_TEXP_PCI 0x02 +#define TI113X_RSR_MEXP_PCI 0x01 + +/* Card Control Register */ +#define TI113X_CARD_CONTROL 0x91 /* 8 bit */ +#define TI113X_CCR_RIENB 0x80 +#define TI113X_CCR_ZVENABLE 0x40 +#define TI113X_CCR_PCI_IRQ_ENA 0x20 +#define TI113X_CCR_PCI_IREQ 0x10 +#define TI113X_CCR_PCI_CSC 0x08 +#define TI113X_CCR_SPKROUTEN 0x02 +#define TI113X_CCR_IFG 0x01 + +#define TI1220_CCR_PORT_SEL 0x20 +#define TI122X_CCR_AUD2MUX 0x04 + +/* Device Control Register */ +#define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */ +#define TI113X_DCR_5V_FORCE 0x40 +#define TI113X_DCR_3V_FORCE 0x20 +#define TI113X_DCR_IMODE_MASK 0x06 +#define TI113X_DCR_IMODE_ISA 0x02 +#define TI113X_DCR_IMODE_SERIAL 0x04 + +#define TI12XX_DCR_IMODE_PCI_ONLY 0x00 +#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06 + +/* Buffer Control Register */ +#define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */ +#define TI113X_BCR_CB_READ_DEPTH 0x08 +#define TI113X_BCR_CB_WRITE_DEPTH 0x04 +#define TI113X_BCR_PCI_READ_DEPTH 0x02 +#define TI113X_BCR_PCI_WRITE_DEPTH 0x01 + +/* Diagnostic Register */ +#define TI1250_DIAGNOSTIC 0x93 /* 8 bit */ +#define TI1250_DIAG_TRUE_VALUE 0x80 +#define TI1250_DIAG_PCI_IREQ 0x40 +#define TI1250_DIAG_PCI_CSC 0x20 +#define TI1250_DIAG_ASYNC_CSC 0x01 + +/* DMA Registers */ +#define TI113X_DMA_0 0x94 /* 32 bit */ +#define TI113X_DMA_1 0x98 /* 32 bit */ + +/* ExCA IO offset registers */ +#define TI113X_IO_OFFSET(map) (0x36+((map)<<1)) + +/* Data structure for tracking vendor-specific state */ +typedef struct ti113x_state_t { + u32 sysctl; /* TI113X_SYSTEM_CONTROL */ + u8 cardctl; /* TI113X_CARD_CONTROL */ + u8 devctl; /* TI113X_DEVICE_CONTROL */ + u8 diag; /* TI1250_DIAGNOSTIC */ + u32 irqmux; /* TI12XX_IRQMUX */ +} ti113x_state_t; + +#define TI_PCIC_ID \ + IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \ + IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \ + IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \ + IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451 + +#define TI_PCIC_INFO \ + { "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \ + { "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \ + { "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \ + { "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \ + { "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \ + { "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \ + { "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \ + { "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \ + { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \ + { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \ + { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \ + { "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \ + { "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \ + { "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \ + { "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \ + { "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \ + { "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \ + { "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \ + { "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) } + +#endif /* _LINUX_TI113X_H */ diff --git a/include/pcmcia/yenta.h b/include/pcmcia/yenta.h new file mode 100644 index 0000000..5cd58a7 --- /dev/null +++ b/include/pcmcia/yenta.h @@ -0,0 +1,156 @@ +/* + * yenta.h 1.20 2001/08/24 12:15:34 + * + * The contents of this file are subject to the Mozilla Public License + * Version 1.1 (the "License"); you may not use this file except in + * compliance with the License. You may obtain a copy of the License + * at http://www.mozilla.org/MPL/ + * + * Software distributed under the License is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See + * the License for the specific language governing rights and + * limitations under the License. + * + * The initial developer of the original code is David A. Hinds + * . Portions created by David A. Hinds + * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use + * your version of this file under the MPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the MPL or the GPL. + */ + +#ifndef _LINUX_YENTA_H +#define _LINUX_YENTA_H + +/* PCI Configuration Registers */ + +#define PCI_STATUS_CAPLIST 0x10 +#define PCI_CB_CAPABILITY_POINTER 0x14 /* 8 bit */ +#define PCI_CAPABILITY_ID 0x00 /* 8 bit */ +#define PCI_CAPABILITY_PM 0x01 +#define PCI_NEXT_CAPABILITY 0x01 /* 8 bit */ +#define PCI_PM_CAPABILITIES 0x02 /* 16 bit */ +#define PCI_PMCAP_PME_D3COLD 0x8000 +#define PCI_PMCAP_PME_D3HOT 0x4000 +#define PCI_PMCAP_PME_D2 0x2000 +#define PCI_PMCAP_PME_D1 0x1000 +#define PCI_PMCAP_PME_D0 0x0800 +#define PCI_PMCAP_D2_CAP 0x0400 +#define PCI_PMCAP_D1_CAP 0x0200 +#define PCI_PMCAP_DYN_DATA 0x0100 +#define PCI_PMCAP_DSI 0x0020 +#define PCI_PMCAP_AUX_PWR 0x0010 +#define PCI_PMCAP_PMECLK 0x0008 +#define PCI_PMCAP_VERSION_MASK 0x0007 +#define PCI_PM_CONTROL_STATUS 0x04 /* 16 bit */ +#define PCI_PMCS_PME_STATUS 0x8000 +#define PCI_PMCS_DATASCALE_MASK 0x6000 +#define PCI_PMCS_DATASCALE_SHIFT 13 +#define PCI_PMCS_DATASEL_MASK 0x1e00 +#define PCI_PMCS_DATASEL_SHIFT 9 +#define PCI_PMCS_PME_ENABLE 0x0100 +#define PCI_PMCS_PWR_STATE_MASK 0x0003 +#define PCI_PMCS_PWR_STATE_D0 0x0000 +#define PCI_PMCS_PWR_STATE_D1 0x0001 +#define PCI_PMCS_PWR_STATE_D2 0x0002 +#define PCI_PMCS_PWR_STATE_D3 0x0003 +#define PCI_PM_BRIDGE_EXT 0x06 /* 8 bit */ +#define PCI_PM_DATA 0x07 /* 8 bit */ + +#define CB_PRIMARY_BUS 0x18 /* 8 bit */ +#define CB_CARDBUS_BUS 0x19 /* 8 bit */ +#define CB_SUBORD_BUS 0x1a /* 8 bit */ +#define CB_LATENCY_TIMER 0x1b /* 8 bit */ + +#define CB_MEM_BASE(m) (0x1c + 8*(m)) +#define CB_MEM_LIMIT(m) (0x20 + 8*(m)) +#define CB_IO_BASE(m) (0x2c + 8*(m)) +#define CB_IO_LIMIT(m) (0x30 + 8*(m)) + +#define CB_BRIDGE_CONTROL 0x3e /* 16 bit */ +#define CB_BCR_PARITY_ENA 0x0001 +#define CB_BCR_SERR_ENA 0x0002 +#define CB_BCR_ISA_ENA 0x0004 +#define CB_BCR_VGA_ENA 0x0008 +#define CB_BCR_MABORT 0x0020 +#define CB_BCR_CB_RESET 0x0040 +#define CB_BCR_ISA_IRQ 0x0080 +#define CB_BCR_PREFETCH(m) (0x0100 << (m)) +#define CB_BCR_WRITE_POST 0x0400 + +#define CB_LEGACY_MODE_BASE 0x44 + +/* Memory mapped registers */ + +#define CB_SOCKET_EVENT 0x0000 +#define CB_SE_CSTSCHG 0x00000001 +#define CB_SE_CCD 0x00000006 +#define CB_SE_CCD1 0x00000002 +#define CB_SE_CCD2 0x00000004 +#define CB_SE_PWRCYCLE 0x00000008 + +#define CB_SOCKET_MASK 0x0004 +#define CB_SM_CSTSCHG 0x00000001 +#define CB_SM_CCD 0x00000006 +#define CB_SM_PWRCYCLE 0x00000008 + +#define CB_SOCKET_STATE 0x0008 +#define CB_SS_CSTSCHG 0x00000001 +#define CB_SS_CCD 0x00000006 +#define CB_SS_CCD1 0x00000002 +#define CB_SS_CCD2 0x00000004 +#define CB_SS_PWRCYCLE 0x00000008 +#define CB_SS_16BIT 0x00000010 +#define CB_SS_32BIT 0x00000020 +#define CB_SS_CINT 0x00000040 +#define CB_SS_BADCARD 0x00000080 +#define CB_SS_DATALOST 0x00000100 +#define CB_SS_BADVCC 0x00000200 +#define CB_SS_5VCARD 0x00000400 +#define CB_SS_3VCARD 0x00000800 +#define CB_SS_XVCARD 0x00001000 +#define CB_SS_YVCARD 0x00002000 +#define CB_SS_VSENSE 0x00003c86 +#define CB_SS_5VSOCKET 0x10000000 +#define CB_SS_3VSOCKET 0x20000000 +#define CB_SS_XVSOCKET 0x40000000 +#define CB_SS_YVSOCKET 0x80000000 + +#define CB_SOCKET_FORCE 0x000c +#define CB_SF_CVSTEST 0x00004000 + +#define CB_SOCKET_CONTROL 0x0010 +#define CB_SC_VPP_MASK 0x00000007 +#define CB_SC_VPP_OFF 0x00000000 +#define CB_SC_VPP_12V 0x00000001 +#define CB_SC_VPP_5V 0x00000002 +#define CB_SC_VPP_3V 0x00000003 +#define CB_SC_VPP_XV 0x00000004 +#define CB_SC_VPP_YV 0x00000005 +#define CB_SC_VCC_MASK 0x00000070 +#define CB_SC_VCC_OFF 0x00000000 +#define CB_SC_VCC_5V 0x00000020 +#define CB_SC_VCC_3V 0x00000030 +#define CB_SC_VCC_XV 0x00000040 +#define CB_SC_VCC_YV 0x00000050 +#define CB_SC_CCLK_STOP 0x00000080 + +#define CB_SOCKET_POWER 0x0020 +#define CB_SP_CLK_CTRL 0x00000001 +#define CB_SP_CLK_CTRL_ENA 0x00010000 +#define CB_SP_CLK_MODE 0x01000000 +#define CB_SP_ACCESS 0x02000000 + +/* Address bits 31..24 for memory windows for 16-bit cards, + accessable only by memory mapping the 16-bit register set */ +#define CB_MEM_PAGE(map) (0x40 + (map)) + +#endif /* _LINUX_YENTA_H */ diff --git a/include/post.h b/include/post.h new file mode 100644 index 0000000..cdefbdd --- /dev/null +++ b/include/post.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _POST_H +#define _POST_H + +#ifndef __ASSEMBLY__ +#include +#endif + +#ifdef CONFIG_POST + +#define POST_POWERON 0x01 /* test runs on power-on booting */ +#define POST_NORMAL 0x02 /* test runs on normal booting */ +#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */ +#define POST_POWERTEST 0x08 /* test runs after watchdog reset */ + +#define POST_COLDBOOT 0x80 /* first boot after power-on */ + +#define POST_ROM 0x0100 /* test runs in ROM */ +#define POST_RAM 0x0200 /* test runs in RAM */ +#define POST_MANUAL 0x0400 /* test runs on diag command */ +#define POST_REBOOT 0x0800 /* test may cause rebooting */ +#define POST_PREREL 0x1000 /* test runs before relocation */ + +#define POST_MEM (POST_RAM | POST_ROM) +#define POST_ALWAYS (POST_NORMAL | \ + POST_SLOWTEST | \ + POST_MANUAL | \ + POST_POWERON ) + +#ifndef __ASSEMBLY__ + +struct post_test { + char *name; + char *cmd; + char *desc; + int flags; + int (*test) (int flags); + int (*init_f) (void); + void (*reloc) (void); + unsigned long testid; +}; +int post_init_f (void); +void post_bootmode_init (void); +int post_bootmode_get (unsigned int * last_test); +void post_bootmode_clear (void); +void post_output_backlog ( void ); +int post_run (char *name, int flags); +int post_info (char *name); +int post_log (char *format, ...); +void post_reloc (void); +unsigned long post_time_ms (unsigned long base); + +extern struct post_test post_list[]; +extern unsigned int post_list_size; +extern int post_hotkeys_pressed(void); + +#endif /* __ASSEMBLY__ */ + +#define CFG_POST_RTC 0x00000001 +#define CFG_POST_WATCHDOG 0x00000002 +#define CFG_POST_MEMORY 0x00000004 +#define CFG_POST_CPU 0x00000008 +#define CFG_POST_I2C 0x00000010 +#define CFG_POST_CACHE 0x00000020 +#define CFG_POST_UART 0x00000040 +#define CFG_POST_ETHER 0x00000080 +#define CFG_POST_SPI 0x00000100 +#define CFG_POST_USB 0x00000200 +#define CFG_POST_SPR 0x00000400 +#define CFG_POST_SYSMON 0x00000800 +#define CFG_POST_DSP 0x00001000 +#define CFG_POST_CODEC 0x00002000 + +#endif /* CONFIG_POST */ + +#endif /* _POST_H */ diff --git a/include/ppc405.h b/include/ppc405.h new file mode 100644 index 0000000..4470240 --- /dev/null +++ b/include/ppc405.h @@ -0,0 +1,695 @@ +/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC405_H__ +#define __PPC405_H__ + +/*--------------------------------------------------------------------- */ +/* Special Purpose Registers */ +/*--------------------------------------------------------------------- */ + #define srr2 0x3de /* save/restore register 2 */ + #define srr3 0x3df /* save/restore register 3 */ + #define dbsr 0x3f0 /* debug status register */ + #define dbcr0 0x3f2 /* debug control register 0 */ + #define dbcr1 0x3bd /* debug control register 1 */ + #define iac1 0x3f4 /* instruction address comparator 1 */ + #define iac2 0x3f5 /* instruction address comparator 2 */ + #define iac3 0x3b4 /* instruction address comparator 3 */ + #define iac4 0x3b5 /* instruction address comparator 4 */ + #define dac1 0x3f6 /* data address comparator 1 */ + #define dac2 0x3f7 /* data address comparator 2 */ + #define dccr 0x3fa /* data cache control register */ + #define iccr 0x3fb /* instruction cache control register */ + #define esr 0x3d4 /* execption syndrome register */ + #define dear 0x3d5 /* data exeption address register */ + #define evpr 0x3d6 /* exeption vector prefix register */ + #define tsr 0x3d8 /* timer status register */ + #define tcr 0x3da /* timer control register */ + #define pit 0x3db /* programmable interval timer */ + #define sgr 0x3b9 /* storage guarded reg */ + #define dcwr 0x3ba /* data cache write-thru reg*/ + #define sler 0x3bb /* storage little-endian reg */ + #define cdbcr 0x3d7 /* cache debug cntrl reg */ + #define icdbdr 0x3d3 /* instr cache dbug data reg*/ + #define ccr0 0x3b3 /* core configuration register */ + #define dvc1 0x3b6 /* data value compare register 1 */ + #define dvc2 0x3b7 /* data value compare register 2 */ + #define pid 0x3b1 /* process ID */ + #define su0r 0x3bc /* storage user-defined register 0 */ + #define zpr 0x3b0 /* zone protection regsiter */ + + #define tbl 0x11c /* time base lower - privileged write */ + #define tbu 0x11d /* time base upper - privileged write */ + + #define sprg4r 0x104 /* Special purpose general 4 - read only */ + #define sprg5r 0x105 /* Special purpose general 5 - read only */ + #define sprg6r 0x106 /* Special purpose general 6 - read only */ + #define sprg7r 0x107 /* Special purpose general 7 - read only */ + #define sprg4w 0x114 /* Special purpose general 4 - write only */ + #define sprg5w 0x115 /* Special purpose general 5 - write only */ + #define sprg6w 0x116 /* Special purpose general 6 - write only */ + #define sprg7w 0x117 /* Special purpose general 7 - write only */ + +/****************************************************************************** + * Special for PPC405GP + ******************************************************************************/ + +/****************************************************************************** + * DMA + ******************************************************************************/ +#define DMA_DCR_BASE 0x100 +#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ +#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ +#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ +#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ +#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ +#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ +#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ +#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ +#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ +#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ +#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ +#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ + +/****************************************************************************** + * Universal interrupt controller + ******************************************************************************/ +#define UIC_DCR_BASE 0xc0 +#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */ +#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */ +#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */ +#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */ +#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */ +#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */ +#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */ +#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ +#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ + +/*-----------------------------------------------------------------------------+ +| Universal interrupt controller interrupts ++-----------------------------------------------------------------------------*/ +#define UIC_UART0 0x80000000 /* UART 0 */ +#define UIC_UART1 0x40000000 /* UART 1 */ +#define UIC_IIC 0x20000000 /* IIC */ +#define UIC_EXT_MAST 0x10000000 /* External Master */ +#define UIC_PCI 0x08000000 /* PCI write to command reg */ +#define UIC_DMA0 0x04000000 /* DMA chan. 0 */ +#define UIC_DMA1 0x02000000 /* DMA chan. 1 */ +#define UIC_DMA2 0x01000000 /* DMA chan. 2 */ +#define UIC_DMA3 0x00800000 /* DMA chan. 3 */ +#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */ +#define UIC_MAL_SERR 0x00200000 /* MAL SERR */ +#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */ +#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */ +#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */ +#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */ +#define UIC_ENET 0x00010000 /* Ethernet0 */ +#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */ +#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */ +#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */ +#define UIC_PCI_PM 0x00002000 /* PCI Power Management */ +#define UIC_EXT0 0x00000040 /* External interrupt 0 */ +#define UIC_EXT1 0x00000020 /* External interrupt 1 */ +#define UIC_EXT2 0x00000010 /* External interrupt 2 */ +#define UIC_EXT3 0x00000008 /* External interrupt 3 */ +#define UIC_EXT4 0x00000004 /* External interrupt 4 */ +#define UIC_EXT5 0x00000002 /* External interrupt 5 */ +#define UIC_EXT6 0x00000001 /* External interrupt 6 */ + +/****************************************************************************** + * SDRAM Controller + ******************************************************************************/ +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ +#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ + /* values for memcfga register - indirect addressing of these regs */ +#ifndef CONFIG_405EP + #define mem_besra 0x00 /* bus error syndrome reg a */ + #define mem_besrsa 0x04 /* bus error syndrome reg set a */ + #define mem_besrb 0x08 /* bus error syndrome reg b */ + #define mem_besrsb 0x0c /* bus error syndrome reg set b */ + #define mem_bear 0x10 /* bus error address reg */ +#endif + #define mem_mcopt1 0x20 /* memory controller options 1 */ + #define mem_rtr 0x30 /* refresh timer reg */ + #define mem_pmit 0x34 /* power management idle timer */ + #define mem_mb0cf 0x40 /* memory bank 0 configuration */ + #define mem_mb1cf 0x44 /* memory bank 1 configuration */ +#ifndef CONFIG_405EP + #define mem_mb2cf 0x48 /* memory bank 2 configuration */ + #define mem_mb3cf 0x4c /* memory bank 3 configuration */ +#endif + #define mem_sdtr1 0x80 /* timing reg 1 */ +#ifndef CONFIG_405EP + #define mem_ecccf 0x94 /* ECC configuration */ + #define mem_eccerr 0x98 /* ECC error status */ +#endif + +#ifndef CONFIG_405EP +/****************************************************************************** + * Decompression Controller + ******************************************************************************/ +#define DECOMP_DCR_BASE 0x14 +#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ +#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ + /* values for kiar register - indirect addressing of these regs */ + #define kitor0 0x00 /* index table origin register 0 */ + #define kitor1 0x01 /* index table origin register 1 */ + #define kitor2 0x02 /* index table origin register 2 */ + #define kitor3 0x03 /* index table origin register 3 */ + #define kaddr0 0x04 /* address decode definition regsiter 0 */ + #define kaddr1 0x05 /* address decode definition regsiter 1 */ + #define kconf 0x40 /* decompression core config register */ + #define kid 0x41 /* decompression core ID register */ + #define kver 0x42 /* decompression core version # reg */ + #define kpear 0x50 /* bus error addr reg (PLB addr) */ + #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ + #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ + #define kesr0s 0x53 /* bus error status reg 0 (set) */ + /* There are 0x400 of the following registers, from krom0 to krom3ff*/ + /* Only the first one is given here. */ + #define krom0 0x400 /* SRAM/ROM read/write */ +#endif + +/****************************************************************************** + * Power Management + ******************************************************************************/ +#define POWERMAN_DCR_BASE 0xb8 +#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ + +/****************************************************************************** + * Extrnal Bus Controller + ******************************************************************************/ +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ +#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ + /* values for ebccfga register - indirect addressing of these regs */ + #define pb0cr 0x00 /* periph bank 0 config reg */ + #define pb1cr 0x01 /* periph bank 1 config reg */ + #define pb2cr 0x02 /* periph bank 2 config reg */ + #define pb3cr 0x03 /* periph bank 3 config reg */ + #define pb4cr 0x04 /* periph bank 4 config reg */ +#ifndef CONFIG_405EP + #define pb5cr 0x05 /* periph bank 5 config reg */ + #define pb6cr 0x06 /* periph bank 6 config reg */ + #define pb7cr 0x07 /* periph bank 7 config reg */ +#endif + #define pb0ap 0x10 /* periph bank 0 access parameters */ + #define pb1ap 0x11 /* periph bank 1 access parameters */ + #define pb2ap 0x12 /* periph bank 2 access parameters */ + #define pb3ap 0x13 /* periph bank 3 access parameters */ + #define pb4ap 0x14 /* periph bank 4 access parameters */ +#ifndef CONFIG_405EP + #define pb5ap 0x15 /* periph bank 5 access parameters */ + #define pb6ap 0x16 /* periph bank 6 access parameters */ + #define pb7ap 0x17 /* periph bank 7 access parameters */ +#endif + #define pbear 0x20 /* periph bus error addr reg */ + #define pbesr0 0x21 /* periph bus error status reg 0 */ + #define pbesr1 0x22 /* periph bus error status reg 1 */ + #define epcr 0x23 /* external periph control reg */ + +#ifdef CONFIG_405EP +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0f0 +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ + +/* Bit definitions */ +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 + +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 + +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 + +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 + +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 + +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 + +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_DIV_16 0x00000000 +#define PLLMR1_FBMUL_DIV_1 0x00100000 +#define PLLMR1_FBMUL_DIV_2 0x00200000 +#define PLLMR1_FBMUL_DIV_3 0x00300000 +#define PLLMR1_FBMUL_DIV_4 0x00400000 +#define PLLMR1_FBMUL_DIV_5 0x00500000 +#define PLLMR1_FBMUL_DIV_6 0x00600000 +#define PLLMR1_FBMUL_DIV_7 0x00700000 +#define PLLMR1_FBMUL_DIV_8 0x00800000 +#define PLLMR1_FBMUL_DIV_9 0x00900000 +#define PLLMR1_FBMUL_DIV_10 0x00A00000 +#define PLLMR1_FBMUL_DIV_11 0x00B00000 +#define PLLMR1_FBMUL_DIV_12 0x00C00000 +#define PLLMR1_FBMUL_DIV_13 0x00D00000 +#define PLLMR1_FBMUL_DIV_14 0x00E00000 +#define PLLMR1_FBMUL_DIV_15 0x00F00000 + +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_DIV_8 0x00000000 +#define PLLMR1_FWDVA_DIV_7 0x00010000 +#define PLLMR1_FWDVA_DIV_6 0x00020000 +#define PLLMR1_FWDVA_DIV_5 0x00030000 +#define PLLMR1_FWDVA_DIV_4 0x00040000 +#define PLLMR1_FWDVA_DIV_3 0x00050000 +#define PLLMR1_FWDVA_DIV_2 0x00060000 +#define PLLMR1_FWDVA_DIV_1 0x00070000 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +/* Defines for CPC0_PCI Register */ +#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ +#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ +#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ + +/* Defines for CPC0_BOOR Register */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +/* + *------------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 33.3MHz input clock to the 405EP. + *------------------------------------------------------------------------------- + */ +#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 500 +#define VCO_MAX 1000 +#else /* #ifdef CONFIG_405EP */ +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0b0 +#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ +#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ +#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ +#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ +#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ + +#define ecr (0xaa) /* edge conditioner register (405gpr) */ + +/* Bit definitions */ +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_BYPASS 0xE0000000 +#define PLLMR_FWD_DIV_3 0xA0000000 +#define PLLMR_FWD_DIV_4 0x80000000 +#define PLLMR_FWD_DIV_6 0x40000000 + +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_1 0x02000000 +#define PLLMR_FB_DIV_2 0x04000000 +#define PLLMR_FB_DIV_3 0x06000000 +#define PLLMR_FB_DIV_4 0x08000000 + +#define PLLMR_TUNING_MASK 0x01F80000 + +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_PLB_DIV_1 0x00000000 +#define PLLMR_CPU_PLB_DIV_2 0x00020000 +#define PLLMR_CPU_PLB_DIV_3 0x00040000 +#define PLLMR_CPU_PLB_DIV_4 0x00060000 + +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_PLB_DIV_1 0x00000000 +#define PLLMR_OPB_PLB_DIV_2 0x00008000 +#define PLLMR_OPB_PLB_DIV_3 0x00010000 +#define PLLMR_OPB_PLB_DIV_4 0x00018000 + +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_PLB_DIV_1 0x00000000 +#define PLLMR_PCI_PLB_DIV_2 0x00002000 +#define PLLMR_PCI_PLB_DIV_3 0x00004000 +#define PLLMR_PCI_PLB_DIV_4 0x00006000 + +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_PLB_DIV_2 0x00000000 +#define PLLMR_EXB_PLB_DIV_3 0x00000800 +#define PLLMR_EXB_PLB_DIV_4 0x00001000 +#define PLLMR_EXB_PLB_DIV_5 0x00001800 + +/* definitions for PPC405GPr (new mode strapping) */ +#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ + +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ +#define PSR_PCI_ARBIT_EN 0x00000400 +#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ + +#ifndef CONFIG_IOP480 +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 400 +#define VCO_MAX 800 +#endif /* #ifndef CONFIG_IOP480 */ +#endif /* #ifdef CONFIG_405EP */ + +/****************************************************************************** + * Memory Access Layer + ******************************************************************************/ +#define MAL_DCR_BASE 0x180 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ + +/*----------------------------------------------------------------------------- +| IIC Register Offsets +'----------------------------------------------------------------------------*/ +#define IICMDBUF 0x00 +#define IICSDBUF 0x02 +#define IICLMADR 0x04 +#define IICHMADR 0x05 +#define IICCNTL 0x06 +#define IICMDCNTL 0x07 +#define IICSTS 0x08 +#define IICEXTSTS 0x09 +#define IICLSADR 0x0A +#define IICHSADR 0x0B +#define IICCLKDIV 0x0C +#define IICINTRMSK 0x0D +#define IICXFRCNT 0x0E +#define IICXTCNTLSS 0x0F +#define IICDIRECTCNTL 0x10 + +/*----------------------------------------------------------------------------- +| UART Register Offsets +'----------------------------------------------------------------------------*/ +#define DATA_REG 0x00 +#define DL_LSB 0x00 +#define DL_MSB 0x01 +#define INT_ENABLE 0x01 +#define FIFO_CONTROL 0x02 +#define LINE_CONTROL 0x03 +#define MODEM_CONTROL 0x04 +#define LINE_STATUS 0x05 +#define MODEM_STATUS 0x06 +#define SCRATCH 0x07 + +/****************************************************************************** + * On Chip Memory + ******************************************************************************/ +#define OCM_DCR_BASE 0x018 +#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ +#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ +#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ +#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ + +/****************************************************************************** + * GPIO macro register defines + ******************************************************************************/ +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRH (GPIO_BASE+0x8) +#define GPIO0_OSRL (GPIO_BASE+0xC) +#define GPIO0_TSRH (GPIO_BASE+0x10) +#define GPIO0_TSRL (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1H (GPIO_BASE+0x30) +#define GPIO0_ISR1L (GPIO_BASE+0x34) +#define GPIO0_ISR2H (GPIO_BASE+0x38) +#define GPIO0_ISR2L (GPIO_BASE+0x3C) + + +/* + * Macro for accessing the indirect EBC register + */ +#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) +#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) + + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long pllFwdDiv; + unsigned long pllFwdDivB; + unsigned long pllFbkDiv; + unsigned long pllPlbDiv; + unsigned long pllPciDiv; + unsigned long pllExtBusDiv; + unsigned long pllOpbDiv; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long freqProcessor; + unsigned long freqPLB; + unsigned long freqPCI; + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long freqVCOHz; +} PPC405_SYS_INFO; + +#endif /* _ASMLANGUAGE */ + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ + +#endif /* __PPC405_H__ */ diff --git a/include/ppc440.h b/include/ppc440.h new file mode 100644 index 0000000..018f7be --- /dev/null +++ b/include/ppc440.h @@ -0,0 +1,1461 @@ +/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC440_H__ +#define __PPC440_H__ + +/*--------------------------------------------------------------------- */ +/* Special Purpose Registers */ +/*--------------------------------------------------------------------- */ +#define dec 0x016 /* decrementer */ +#define srr0 0x01a /* save/restore register 0 */ +#define srr1 0x01b /* save/restore register 1 */ +#define pid 0x030 /* process id */ +#define decar 0x036 /* decrementer auto-reload */ +#define csrr0 0x03a /* critical save/restore register 0 */ +#define csrr1 0x03b /* critical save/restore register 1 */ +#define dear 0x03d /* data exception address register */ +#define esr 0x03e /* exception syndrome register */ +#define ivpr 0x03f /* interrupt prefix register */ +#define usprg0 0x100 /* user special purpose register general 0 */ +#define usprg1 0x110 /* user special purpose register general 1 */ +#define sprg1 0x111 /* special purpose register general 1 */ +#define sprg2 0x112 /* special purpose register general 2 */ +#define sprg3 0x113 /* special purpose register general 3 */ +#define sprg4 0x114 /* special purpose register general 4 */ +#define sprg5 0x115 /* special purpose register general 5 */ +#define sprg6 0x116 /* special purpose register general 6 */ +#define sprg7 0x117 /* special purpose register general 7 */ +#define tbl 0x11c /* time base lower (supervisor)*/ +#define tbu 0x11d /* time base upper (supervisor)*/ +#define pir 0x11e /* processor id register */ +/*#define pvr 0x11f processor version register */ +#define dbsr 0x130 /* debug status register */ +#define dbcr0 0x134 /* debug control register 0 */ +#define dbcr1 0x135 /* debug control register 1 */ +#define dbcr2 0x136 /* debug control register 2 */ +#define iac1 0x138 /* instruction address compare 1 */ +#define iac2 0x139 /* instruction address compare 2 */ +#define iac3 0x13a /* instruction address compare 3 */ +#define iac4 0x13b /* instruction address compare 4 */ +#define dac1 0x13c /* data address compare 1 */ +#define dac2 0x13d /* data address compare 2 */ +#define dvc1 0x13e /* data value compare 1 */ +#define dvc2 0x13f /* data value compare 2 */ +#define tsr 0x150 /* timer status register */ +#define tcr 0x154 /* timer control register */ +#define ivor0 0x190 /* interrupt vector offset register 0 */ +#define ivor1 0x191 /* interrupt vector offset register 1 */ +#define ivor2 0x192 /* interrupt vector offset register 2 */ +#define ivor3 0x193 /* interrupt vector offset register 3 */ +#define ivor4 0x194 /* interrupt vector offset register 4 */ +#define ivor5 0x195 /* interrupt vector offset register 5 */ +#define ivor6 0x196 /* interrupt vector offset register 6 */ +#define ivor7 0x197 /* interrupt vector offset register 7 */ +#define ivor8 0x198 /* interrupt vector offset register 8 */ +#define ivor9 0x199 /* interrupt vector offset register 9 */ +#define ivor10 0x19a /* interrupt vector offset register 10 */ +#define ivor11 0x19b /* interrupt vector offset register 11 */ +#define ivor12 0x19c /* interrupt vector offset register 12 */ +#define ivor13 0x19d /* interrupt vector offset register 13 */ +#define ivor14 0x19e /* interrupt vector offset register 14 */ +#define ivor15 0x19f /* interrupt vector offset register 15 */ +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#define mcsrr0 0x23a /* machine check save/restore register 0 */ +#define mcsrr1 0x23b /* mahcine check save/restore register 1 */ +#define mcsr 0x23c /* machine check status register */ +#endif +#define inv0 0x370 /* instruction cache normal victim 0 */ +#define inv1 0x371 /* instruction cache normal victim 1 */ +#define inv2 0x372 /* instruction cache normal victim 2 */ +#define inv3 0x373 /* instruction cache normal victim 3 */ +#define itv0 0x374 /* instruction cache transient victim 0 */ +#define itv1 0x375 /* instruction cache transient victim 1 */ +#define itv2 0x376 /* instruction cache transient victim 2 */ +#define itv3 0x377 /* instruction cache transient victim 3 */ +#define dnv0 0x390 /* data cache normal victim 0 */ +#define dnv1 0x391 /* data cache normal victim 1 */ +#define dnv2 0x392 /* data cache normal victim 2 */ +#define dnv3 0x393 /* data cache normal victim 3 */ +#define dtv0 0x394 /* data cache transient victim 0 */ +#define dtv1 0x395 /* data cache transient victim 1 */ +#define dtv2 0x396 /* data cache transient victim 2 */ +#define dtv3 0x397 /* data cache transient victim 3 */ +#define dvlim 0x398 /* data cache victim limit */ +#define ivlim 0x399 /* instruction cache victim limit */ +#define rstcfg 0x39b /* reset configuration */ +#define dcdbtrl 0x39c /* data cache debug tag register low */ +#define dcdbtrh 0x39d /* data cache debug tag register high */ +#define icdbtrl 0x39e /* instruction cache debug tag register low */ +#define icdbtrh 0x39f /* instruction cache debug tag register high */ +#define mmucr 0x3b2 /* mmu control register */ +#define ccr0 0x3b3 /* core configuration register 0 */ +#define ccr1 0x378 /* core configuration for 440x5 only */ +#define icdbdr 0x3d3 /* instruction cache debug data register */ +#define dbdr 0x3f3 /* debug data register */ + +/****************************************************************************** + * DCRs & Related + ******************************************************************************/ + +/*----------------------------------------------------------------------------- + | Clocking Controller + +----------------------------------------------------------------------------*/ +#define CLOCKING_DCR_BASE 0x0c +#define clkcfga (CLOCKING_DCR_BASE+0x0) +#define clkcfgd (CLOCKING_DCR_BASE+0x1) + +/* values for clkcfga register - indirect addressing of these regs */ +#define clk_clkukpd 0x0020 +#define clk_pllc 0x0040 +#define clk_plld 0x0060 +#define clk_primad 0x0080 +#define clk_primbd 0x00a0 +#define clk_opbd 0x00c0 +#define clk_perd 0x00e0 +#define clk_mald 0x0100 +#define clk_spcid 0x0120 +#define clk_icfg 0x0140 + +/* 440gx sdr register definations */ +#define SDR_DCR_BASE 0x0e +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) +#define sdr_sdstp0 0x0020 /* */ +#define sdr_sdstp1 0x0021 /* */ +#define sdr_pinstp 0x0040 +#define sdr_sdcs 0x0060 +#define sdr_ecid0 0x0080 +#define sdr_ecid1 0x0081 +#define sdr_ecid2 0x0082 +#define sdr_jtag 0x00c0 +#define sdr_ddrdl 0x00e0 +#define sdr_ebc 0x0100 +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_uart2 0x0122 /* UART2 Config */ +#define sdr_uart3 0x0123 /* UART3 Config */ +#define sdr_cp440 0x0180 +#define sdr_xcr 0x01c0 +#define sdr_xpllc 0x01c1 +#define sdr_xplld 0x01c2 +#define sdr_srst 0x0200 +#define sdr_slpipe 0x0220 +#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ +#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ +#define sdr_mirq0 0x0260 +#define sdr_mirq1 0x0261 +#define sdr_maltbl 0x0280 +#define sdr_malrbl 0x02a0 +#define sdr_maltbs 0x02c0 +#define sdr_malrbs 0x02e0 +#define sdr_pci0 0x0300 +#define sdr_usb0 0x0320 +#define sdr_cust0 0x4000 +#define sdr_sdstp2 0x4001 +#define sdr_cust1 0x4002 +#define sdr_sdstp3 0x4003 +#define sdr_pfc0 0x4100 /* Pin Function 0 */ +#define sdr_pfc1 0x4101 /* Pin Function 1 */ +#define sdr_plbtr 0x4200 +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ + +/*----------------------------------------------------------------------------- + | SDRAM Controller + +----------------------------------------------------------------------------*/ +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ +#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ + +/* values for memcfga register - indirect addressing of these regs */ +#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ +#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ +#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ +#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ +#define mem_bear 0x0010 /* bus error address reg */ +#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ +#define mem_mirq_set 0x0012 /* bus master interrupt (set) */ +#define mem_slio 0x0018 /* ddr sdram slave interface options */ +#define mem_cfg0 0x0020 /* ddr sdram options 0 */ +#define mem_cfg1 0x0021 /* ddr sdram options 1 */ +#define mem_devopt 0x0022 /* ddr sdram device options */ +#define mem_mcsts 0x0024 /* memory controller status */ +#define mem_rtr 0x0030 /* refresh timer register */ +#define mem_pmit 0x0034 /* power management idle timer */ +#define mem_uabba 0x0038 /* plb UABus base address */ +#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */ +#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */ +#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */ +#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */ +#define mem_tr0 0x0080 /* sdram timing register 0 */ +#define mem_tr1 0x0081 /* sdram timing register 1 */ +#define mem_clktr 0x0082 /* ddr clock timing register */ +#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */ +#define mem_dlycal 0x0084 /* delay line calibration register */ +#define mem_eccesr 0x0098 /* ECC error status */ + +/*----------------------------------------------------------------------------- + | External Bus Controller + +----------------------------------------------------------------------------*/ +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ +#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ +/* values for ebccfga register - indirect addressing of these regs */ +#define pb0cr 0x00 /* periph bank 0 config reg */ +#define pb1cr 0x01 /* periph bank 1 config reg */ +#define pb2cr 0x02 /* periph bank 2 config reg */ +#define pb3cr 0x03 /* periph bank 3 config reg */ +#define pb4cr 0x04 /* periph bank 4 config reg */ +#define pb5cr 0x05 /* periph bank 5 config reg */ +#define pb6cr 0x06 /* periph bank 6 config reg */ +#define pb7cr 0x07 /* periph bank 7 config reg */ +#define pb0ap 0x10 /* periph bank 0 access parameters */ +#define pb1ap 0x11 /* periph bank 1 access parameters */ +#define pb2ap 0x12 /* periph bank 2 access parameters */ +#define pb3ap 0x13 /* periph bank 3 access parameters */ +#define pb4ap 0x14 /* periph bank 4 access parameters */ +#define pb5ap 0x15 /* periph bank 5 access parameters */ +#define pb6ap 0x16 /* periph bank 6 access parameters */ +#define pb7ap 0x17 /* periph bank 7 access parameters */ +#define pbear 0x20 /* periph bus error addr reg */ +#define pbesr 0x21 /* periph bus error status reg */ +#define xbcfg 0x23 /* external bus configuration reg */ +#define xbcid 0x24 /* external bus core id reg */ + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + +/* PLB4 to PLB3 Bridge OUT */ +#define P4P3_DCR_BASE 0x020 +#define p4p3_esr0_read (P4P3_DCR_BASE+0x0) +#define p4p3_esr0_write (P4P3_DCR_BASE+0x1) +#define p4p3_eadr (P4P3_DCR_BASE+0x2) +#define p4p3_euadr (P4P3_DCR_BASE+0x3) +#define p4p3_esr1_read (P4P3_DCR_BASE+0x4) +#define p4p3_esr1_write (P4P3_DCR_BASE+0x5) +#define p4p3_confg (P4P3_DCR_BASE+0x6) +#define p4p3_pic (P4P3_DCR_BASE+0x7) +#define p4p3_peir (P4P3_DCR_BASE+0x8) +#define p4p3_rev (P4P3_DCR_BASE+0xA) + +/* PLB3 to PLB4 Bridge IN */ +#define P3P4_DCR_BASE 0x030 +#define p3p4_esr0_read (P3P4_DCR_BASE+0x0) +#define p3p4_esr0_write (P3P4_DCR_BASE+0x1) +#define p3p4_eadr (P3P4_DCR_BASE+0x2) +#define p3p4_euadr (P3P4_DCR_BASE+0x3) +#define p3p4_esr1_read (P3P4_DCR_BASE+0x4) +#define p3p4_esr1_write (P3P4_DCR_BASE+0x5) +#define p3p4_confg (P3P4_DCR_BASE+0x6) +#define p3p4_pic (P3P4_DCR_BASE+0x7) +#define p3p4_peir (P3P4_DCR_BASE+0x8) +#define p3p4_rev (P3P4_DCR_BASE+0xA) + +/* PLB3 Arbiter */ +#define PLB3_DCR_BASE 0x070 +#define plb3_revid (PLB3_DCR_BASE+0x2) +#define plb3_besr (PLB3_DCR_BASE+0x3) +#define plb3_bear (PLB3_DCR_BASE+0x6) +#define plb3_acr (PLB3_DCR_BASE+0x7) + +/* PLB4 Arbiter - PowerPC440EP Pass1 */ +#define PLB4_DCR_BASE 0x080 +#define plb4_revid (PLB4_DCR_BASE+0x2) +#define plb4_acr (PLB4_DCR_BASE+0x3) +#define plb4_besr (PLB4_DCR_BASE+0x4) +#define plb4_bearl (PLB4_DCR_BASE+0x6) +#define plb4_bearh (PLB4_DCR_BASE+0x7) + +/* Nebula PLB4 Arbiter - PowerPC440EP */ +#define PLB_ARBITER_BASE 0x80 + +#define plb0_revid (PLB_ARBITER_BASE+ 0x00) +#define plb0_acr (PLB_ARBITER_BASE+ 0x01) +#define plb0_acr_ppm_mask 0xF0000000 +#define plb0_acr_ppm_fixed 0x00000000 +#define plb0_acr_ppm_fair 0xD0000000 +#define plb0_acr_hbu_mask 0x08000000 +#define plb0_acr_hbu_disabled 0x00000000 +#define plb0_acr_hbu_enabled 0x08000000 +#define plb0_acr_rdp_mask 0x06000000 +#define plb0_acr_rdp_disabled 0x00000000 +#define plb0_acr_rdp_2deep 0x02000000 +#define plb0_acr_rdp_3deep 0x04000000 +#define plb0_acr_rdp_4deep 0x06000000 +#define plb0_acr_wrp_mask 0x01000000 +#define plb0_acr_wrp_disabled 0x00000000 +#define plb0_acr_wrp_2deep 0x01000000 + +#define plb0_besrl (PLB_ARBITER_BASE+ 0x02) +#define plb0_besrh (PLB_ARBITER_BASE+ 0x03) +#define plb0_bearl (PLB_ARBITER_BASE+ 0x04) +#define plb0_bearh (PLB_ARBITER_BASE+ 0x05) +#define plb0_ccr (PLB_ARBITER_BASE+ 0x08) + +#define plb1_acr (PLB_ARBITER_BASE+ 0x09) +#define plb1_acr_ppm_mask 0xF0000000 +#define plb1_acr_ppm_fixed 0x00000000 +#define plb1_acr_ppm_fair 0xD0000000 +#define plb1_acr_hbu_mask 0x08000000 +#define plb1_acr_hbu_disabled 0x00000000 +#define plb1_acr_hbu_enabled 0x08000000 +#define plb1_acr_rdp_mask 0x06000000 +#define plb1_acr_rdp_disabled 0x00000000 +#define plb1_acr_rdp_2deep 0x02000000 +#define plb1_acr_rdp_3deep 0x04000000 +#define plb1_acr_rdp_4deep 0x06000000 +#define plb1_acr_wrp_mask 0x01000000 +#define plb1_acr_wrp_disabled 0x00000000 +#define plb1_acr_wrp_2deep 0x01000000 + +#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) +#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) +#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) +#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) + +/* Pin Function Control Register 1 */ +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ + +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ + +/* USB Control Register */ +#define SDR0_USB0 0x0320 +#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ +#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ +#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ +#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ +#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ +#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +/* CUST1 Customer Configuration Register1 */ +#define SDR0_CUST1 0x4002 +#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */ +#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) + +/* Pin Function Control Register 0 */ +#define SDR0_PFC0 0x4100 +#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */ +#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */ +#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */ +#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) +#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) + +/* Pin Function Control Register 1 */ +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ + +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ + +/* Miscealleneaous Function Reg. */ +#define SDR0_MFR 0x4300 +#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ +#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) + +#define SDR0_MFR_ERRATA3_EN0 0x00800000 +#define SDR0_MFR_ERRATA3_EN1 0x00400000 +#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ + +#else + +/*----------------------------------------------------------------------------- + | Internal SRAM + +----------------------------------------------------------------------------*/ +#define ISRAM0_DCR_BASE 0x020 +#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/ +#define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/ +#define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/ +#define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/ +#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */ +#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */ +#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */ +#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */ +#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */ +#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ +#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ + +/*----------------------------------------------------------------------------- + | L2 Cache + +----------------------------------------------------------------------------*/ +#if defined (CONFIG_440GX) || defined(CONFIG_440SP) +#define L2_CACHE_BASE 0x030 +#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ +#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ +#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */ +#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */ +#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */ +#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */ +#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */ +#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ + +#endif /* CONFIG_440GX */ +#endif /* !CONFIG_440EP !CONFIG_440GR*/ + +/*----------------------------------------------------------------------------- + | On-Chip Buses + +----------------------------------------------------------------------------*/ +/* TODO: as needed */ + +/*----------------------------------------------------------------------------- + | Clocking, Power Management and Chip Control + +----------------------------------------------------------------------------*/ +#define CNTRL_DCR_BASE 0x0b0 +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ +#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ +#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ +#else +#define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */ +#define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */ +#define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */ +#endif + +#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ +#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ +#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */ +#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */ + +#define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ +#define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ +#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ +#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ + +#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ + +#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ +#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ + +/*----------------------------------------------------------------------------- + | Universal interrupt controller + +----------------------------------------------------------------------------*/ +#define UIC0_DCR_BASE 0xc0 +#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ + +#define UIC1_DCR_BASE 0xd0 +#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ +#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ +#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ +#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ +#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ +#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ +#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ +#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ + +#if defined(CONFIG_440GX) +#define UIC2_DCR_BASE 0x210 +#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */ +#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ +#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ +#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ +#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ +#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ +#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ +#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ + + +#define UIC_DCR_BASE 0x200 +#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */ +#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */ +#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */ +#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */ +#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */ +#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */ +#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */ +#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */ +#endif /* CONFIG_440GX */ + +/* The following is for compatibility with 405 code */ +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr + +/*----------------------------------------------------------------------------- + | DMA + +----------------------------------------------------------------------------*/ +#define DMA_DCR_BASE 0x100 +#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ +#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */ +#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */ +#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */ +#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */ +#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */ +#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */ +#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */ +#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */ +#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */ +#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */ +#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */ +#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */ +#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */ +#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */ +#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */ +#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */ +#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */ +#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ +#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */ +#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */ +#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */ +#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */ +#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */ +#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */ +#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */ +#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ +#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */ +#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */ + +/*----------------------------------------------------------------------------- + | Memory Access Layer + +----------------------------------------------------------------------------*/ +#define MAL_DCR_BASE 0x180 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */ +#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */ +#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ +#if defined(CONFIG_440GX) +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */ +#endif /* CONFIG_440GX */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#if defined(CONFIG_440GX) +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#endif /* CONFIG_440GX */ + + +/*---------------------------------------------------------------------------+ +| Universal interrupt controller 0 interrupts (UIC0) ++---------------------------------------------------------------------------*/ +#if defined(CONFIG_440SP) +#define UIC_U0 0x80000000 /* UART 0 */ +#define UIC_U1 0x40000000 /* UART 1 */ +#define UIC_IIC0 0x20000000 /* IIC */ +#define UIC_IIC1 0x10000000 /* IIC */ +#define UIC_PIM 0x08000000 /* PCI0 inbound message */ +#define UIC_PCRW 0x04000000 /* PCI0 command write register */ +#define UIC_PPM 0x02000000 /* PCI0 power management */ +#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */ +#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */ +#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */ +#define UIC_P1CRW 0x00200000 /* PCI1 command write register */ +#define UIC_P1PM 0x00100000 /* PCI1 power management */ +#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */ +#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */ +#define UIC_P2IM 0x00020000 /* PCI2 inbound message */ +#define UIC_P2CRW 0x00010000 /* PCI2 command register write */ +#define UIC_P2PM 0x00008000 /* PCI2 power management */ +#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */ +#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */ +#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */ +#define UIC_D0CSF 0x00000800 /* DMA0 command status */ +#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */ +#define UIC_D1CSF 0x00000200 /* DMA1 command status */ +#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */ +#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */ +#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */ +#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */ +#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */ +#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */ +#define UIC_GPTCT 0x00000004 /* GPT count timer */ +#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ +#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ +#else /* CONFIG_440SP */ +#define UIC_U0 0x80000000 /* UART 0 */ +#define UIC_U1 0x40000000 /* UART 1 */ +#define UIC_IIC0 0x20000000 /* IIC */ +#define UIC_IIC1 0x10000000 /* IIC */ +#define UIC_PIM 0x08000000 /* PCI inbound message */ +#define UIC_PCRW 0x04000000 /* PCI command register write */ +#define UIC_PPM 0x02000000 /* PCI power management */ +#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ +#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ +#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ +#define UIC_MTE 0x00200000 /* MAL TXEOB */ +#define UIC_MRE 0x00100000 /* MAL RXEOB */ +#define UIC_D0 0x00080000 /* DMA channel 0 */ +#define UIC_D1 0x00040000 /* DMA channel 1 */ +#define UIC_D2 0x00020000 /* DMA channel 2 */ +#define UIC_D3 0x00010000 /* DMA channel 3 */ +#define UIC_RSVD0 0x00008000 /* Reserved */ +#define UIC_RSVD1 0x00004000 /* Reserved */ +#define UIC_CT0 0x00002000 /* GPT compare timer 0 */ +#define UIC_CT1 0x00001000 /* GPT compare timer 1 */ +#define UIC_CT2 0x00000800 /* GPT compare timer 2 */ +#define UIC_CT3 0x00000400 /* GPT compare timer 3 */ +#define UIC_CT4 0x00000200 /* GPT compare timer 4 */ +#define UIC_EIR0 0x00000100 /* External interrupt 0 */ +#define UIC_EIR1 0x00000080 /* External interrupt 1 */ +#define UIC_EIR2 0x00000040 /* External interrupt 2 */ +#define UIC_EIR3 0x00000020 /* External interrupt 3 */ +#define UIC_EIR4 0x00000010 /* External interrupt 4 */ +#define UIC_EIR5 0x00000008 /* External interrupt 5 */ +#define UIC_EIR6 0x00000004 /* External interrupt 6 */ +#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ +#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ +#endif /* CONFIG_440SP */ + +/* For compatibility with 405 code */ +#define UIC_MAL_TXEOB UIC_MTE +#define UIC_MAL_RXEOB UIC_MRE + +/*---------------------------------------------------------------------------+ +| Universal interrupt controller 1 interrupts (UIC1) ++---------------------------------------------------------------------------*/ +#if defined(CONFIG_440SP) +#define UIC_EIR0 0x80000000 /* External interrupt 0 */ +#define UIC_MS 0x40000000 /* MAL SERR */ +#define UIC_MTDE 0x20000000 /* MAL TXDE */ +#define UIC_MRDE 0x10000000 /* MAL RXDE */ +#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ +#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ +#define UIC_MTE 0x02000000 /* MAL TXEOB */ +#define UIC_MRE 0x01000000 /* MAL RXEOB */ +#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ +#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */ +#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */ +#define UIC_L2C 0x00100000 /* L2 cache */ +#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ +#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ +#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ +#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ +#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ +#define UIC_EIR1 0x00004000 /* External interrupt 1 */ +#define UIC_EIR2 0x00002000 /* External interrupt 2 */ +#define UIC_EIR3 0x00001000 /* External interrupt 3 */ +#define UIC_EIR4 0x00000800 /* External interrupt 4 */ +#define UIC_EIR5 0x00000400 /* External interrupt 5 */ +#define UIC_DMAE 0x00000200 /* DMA error */ +#define UIC_I2OE 0x00000100 /* I2O error */ +#define UIC_SRE 0x00000080 /* Serial ROM error */ +#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ +#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */ +#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */ +#define UIC_ETH0 0x00000008 /* Ethernet 0 */ +#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ +#define UIC_ETH1 0x00000002 /* Reserved */ +#define UIC_XOR 0x00000001 /* XOR */ +#else /* CONFIG_440SP */ +#define UIC_MS 0x80000000 /* MAL SERR */ +#define UIC_MTDE 0x40000000 /* MAL TXDE */ +#define UIC_MRDE 0x20000000 /* MAL RXDE */ +#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ +#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ +#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ +#define UIC_EBMI 0x02000000 /* EBMI interrupt status */ +#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ +#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ +#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ +#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ +#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ +#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ +#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ +#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ +#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ +#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ +#define UIC_PPMI 0x00004000 /* PPM interrupt status */ +#define UIC_EIR7 0x00002000 /* External interrupt 7 */ +#define UIC_EIR8 0x00001000 /* External interrupt 8 */ +#define UIC_EIR9 0x00000800 /* External interrupt 9 */ +#define UIC_EIR10 0x00000400 /* External interrupt 10 */ +#define UIC_EIR11 0x00000200 /* External interrupt 11 */ +#define UIC_EIR12 0x00000100 /* External interrupt 12 */ +#define UIC_SRE 0x00000080 /* Serial ROM error */ +#define UIC_RSVD2 0x00000040 /* Reserved */ +#define UIC_RSVD3 0x00000020 /* Reserved */ +#define UIC_PAE 0x00000010 /* PCI asynchronous error */ +#define UIC_ETH0 0x00000008 /* Ethernet 0 */ +#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ +#define UIC_ETH1 0x00000002 /* Ethernet 1 */ +#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ +#endif /* CONFIG_440SP */ + +/* For compatibility with 405 code */ +#define UIC_MAL_SERR UIC_MS +#define UIC_MAL_TXDE UIC_MTDE +#define UIC_MAL_RXDE UIC_MRDE +#define UIC_ENET UIC_ETH0 + +/*---------------------------------------------------------------------------+ +| Universal interrupt controller 2 interrupts (UIC2) ++---------------------------------------------------------------------------*/ +#if defined(CONFIG_440GX) +#define UIC_ETH2 0x80000000 /* Ethernet 2 */ +#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */ +#define UIC_ETH3 0x20000000 /* Ethernet 3 */ +#define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */ +#define UIC_TAH0 0x08000000 /* TAH 0 */ +#define UIC_TAH1 0x04000000 /* TAH 1 */ +#define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */ +#define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */ +#define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */ +#define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */ +#define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */ +#define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */ +#define UIC_IMUTO 0x00080000 /* IMU timeout */ +#define UIC_MSI12 0x00040000 /* PCI MSI level 12 */ +#define UIC_MSI13 0x00020000 /* PCI MSI level 13 */ +#define UIC_MSI14 0x00010000 /* PCI MSI level 14 */ +#define UIC_MSI15 0x00008000 /* PCI MSI level 15 */ +#define UIC_EIR13 0x00004000 /* External interrupt 13 */ +#define UIC_EIR14 0x00002000 /* External interrupt 14 */ +#define UIC_EIR15 0x00001000 /* External interrupt 15 */ +#define UIC_EIR16 0x00000800 /* External interrupt 16 */ +#define UIC_EIR17 0x00000400 /* External interrupt 17 */ +#define UIC_PCIVPD 0x00000200 /* PCI VPD */ +#define UIC_L2C 0x00000100 /* L2 Cache */ +#define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */ +#define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */ +#define UIC_RSVD26 0x00000020 /* Reserved */ +#define UIC_RSVD27 0x00000010 /* Reserved */ +#define UIC_RSVD28 0x00000008 /* Reserved */ +#define UIC_RSVD29 0x00000004 /* Reserved */ +#define UIC_RSVD30 0x00000002 /* Reserved */ +#define UIC_RSVD31 0x00000001 /* Reserved */ +#endif /* CONFIG_440GX */ + +/*---------------------------------------------------------------------------+ +| Universal interrupt controller Base 0 interrupts (UICB0) ++---------------------------------------------------------------------------*/ +#if defined(CONFIG_440GX) +#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */ +#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */ +#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */ +#define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */ +#define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */ +#define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */ + +#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ + UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) +#endif /* CONFIG_440GX */ + +/*-----------------------------------------------------------------------------+ +| External Bus Controller Bit Settings ++-----------------------------------------------------------------------------*/ +#define EBC_CFGADDR_MASK 0x0000003F + +#define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) +#define EBC_BXCR_BS_MASK 0x000E0000 +#define EBC_BXCR_BS_1MB 0x00000000 +#define EBC_BXCR_BS_2MB 0x00020000 +#define EBC_BXCR_BS_4MB 0x00040000 +#define EBC_BXCR_BS_8MB 0x00060000 +#define EBC_BXCR_BS_16MB 0x00080000 +#define EBC_BXCR_BS_32MB 0x000A0000 +#define EBC_BXCR_BS_64MB 0x000C0000 +#define EBC_BXCR_BS_128MB 0x000E0000 +#define EBC_BXCR_BU_MASK 0x00018000 +#define EBC_BXCR_BU_R 0x00008000 +#define EBC_BXCR_BU_W 0x00010000 +#define EBC_BXCR_BU_RW 0x00018000 +#define EBC_BXCR_BW_MASK 0x00006000 +#define EBC_BXCR_BW_8BIT 0x00000000 +#define EBC_BXCR_BW_16BIT 0x00002000 +#define EBC_BXCR_BW_32BIT 0x00006000 +#define EBC_BXAP_BME_ENABLED 0x80000000 +#define EBC_BXAP_BME_DISABLED 0x00000000 +#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) +#define EBC_BXAP_BCE_DISABLE 0x00000000 +#define EBC_BXAP_BCE_ENABLE 0x00400000 +#define EBC_BXAP_BCT_MASK 0x00300000 +#define EBC_BXAP_BCT_2TRANS 0x00000000 +#define EBC_BXAP_BCT_4TRANS 0x00100000 +#define EBC_BXAP_BCT_8TRANS 0x00200000 +#define EBC_BXAP_BCT_16TRANS 0x00300000 +#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) +#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) +#define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) +#define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) +#define EBC_BXAP_RE_ENABLED 0x00000100 +#define EBC_BXAP_RE_DISABLED 0x00000000 +#define EBC_BXAP_SOR_DELAYED 0x00000000 +#define EBC_BXAP_SOR_NONDELAYED 0x00000080 +#define EBC_BXAP_BEM_WRITEONLY 0x00000000 +#define EBC_BXAP_BEM_RW 0x00000040 +#define EBC_BXAP_PEN_DISABLED 0x00000000 + +#define EBC_CFG_LE_MASK 0x80000000 +#define EBC_CFG_LE_UNLOCK 0x00000000 +#define EBC_CFG_LE_LOCK 0x80000000 +#define EBC_CFG_PTD_MASK 0x40000000 +#define EBC_CFG_PTD_ENABLE 0x00000000 +#define EBC_CFG_PTD_DISABLE 0x40000000 +#define EBC_CFG_RTC_MASK 0x38000000 +#define EBC_CFG_RTC_16PERCLK 0x00000000 +#define EBC_CFG_RTC_32PERCLK 0x08000000 +#define EBC_CFG_RTC_64PERCLK 0x10000000 +#define EBC_CFG_RTC_128PERCLK 0x18000000 +#define EBC_CFG_RTC_256PERCLK 0x20000000 +#define EBC_CFG_RTC_512PERCLK 0x28000000 +#define EBC_CFG_RTC_1024PERCLK 0x30000000 +#define EBC_CFG_RTC_2048PERCLK 0x38000000 +#define EBC_CFG_ATC_MASK 0x04000000 +#define EBC_CFG_ATC_HI 0x00000000 +#define EBC_CFG_ATC_PREVIOUS 0x04000000 +#define EBC_CFG_DTC_MASK 0x02000000 +#define EBC_CFG_DTC_HI 0x00000000 +#define EBC_CFG_DTC_PREVIOUS 0x02000000 +#define EBC_CFG_CTC_MASK 0x01000000 +#define EBC_CFG_CTC_HI 0x00000000 +#define EBC_CFG_CTC_PREVIOUS 0x01000000 +#define EBC_CFG_OEO_MASK 0x00800000 +#define EBC_CFG_OEO_HI 0x00000000 +#define EBC_CFG_OEO_PREVIOUS 0x00800000 +#define EBC_CFG_EMC_MASK 0x00400000 +#define EBC_CFG_EMC_NONDEFAULT 0x00000000 +#define EBC_CFG_EMC_DEFAULT 0x00400000 +#define EBC_CFG_PME_MASK 0x00200000 +#define EBC_CFG_PME_DISABLE 0x00000000 +#define EBC_CFG_PME_ENABLE 0x00200000 +#define EBC_CFG_PMT_MASK 0x001F0000 +#define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) +#define EBC_CFG_PR_MASK 0x0000C000 +#define EBC_CFG_PR_16 0x00000000 +#define EBC_CFG_PR_32 0x00004000 +#define EBC_CFG_PR_64 0x00008000 +#define EBC_CFG_PR_128 0x0000C000 + +/*-----------------------------------------------------------------------------+ +| SDR0 Bit Settings ++-----------------------------------------------------------------------------*/ +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +#if defined(CONFIG_440GP) +#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11) +#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13) +#endif /* defined(CONFIG_440GP) */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) +#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) +#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) +#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) +#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ + +#define SDR0_UARTX_UXICS_MASK 0xF0000000 +#define SDR0_UARTX_UXICS_PLB 0x20000000 +#define SDR0_UARTX_UXEC_MASK 0x00800000 +#define SDR0_UARTX_UXEC_INT 0x00000000 +#define SDR0_UARTX_UXEC_EXT 0x00800000 +#define SDR0_UARTX_UXDTE_MASK 0x00400000 +#define SDR0_UARTX_UXDTE_DISABLE 0x00000000 +#define SDR0_UARTX_UXDTE_ENABLE 0x00400000 +#define SDR0_UARTX_UXDRE_MASK 0x00200000 +#define SDR0_UARTX_UXDRE_DISABLE 0x00000000 +#define SDR0_UARTX_UXDRE_ENABLE 0x00200000 +#define SDR0_UARTX_UXDC_MASK 0x00100000 +#define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000 +#define SDR0_UARTX_UXDC_CLEARED 0x00100000 +#define SDR0_UARTX_UXDIV_MASK 0x000000FF +#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) + +#define SDR0_CPU440_EARV_MASK 0x30000000 +#define SDR0_CPU440_EARV_EBC 0x10000000 +#define SDR0_CPU440_EARV_PCI 0x20000000 +#define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) +#define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03) +#define SDR0_CPU440_NTO1_MASK 0x00000002 +#define SDR0_CPU440_NTO1_NTOP 0x00000000 +#define SDR0_CPU440_NTO1_NTO1 0x00000002 +#define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) +#define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) + +#define SDR0_XCR_PAE_MASK 0x80000000 +#define SDR0_XCR_PAE_DISABLE 0x00000000 +#define SDR0_XCR_PAE_ENABLE 0x80000000 +#define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) +#define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) +#define SDR0_XCR_PHCE_MASK 0x40000000 +#define SDR0_XCR_PHCE_DISABLE 0x00000000 +#define SDR0_XCR_PHCE_ENABLE 0x40000000 +#define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) +#define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) +#define SDR0_XCR_PISE_MASK 0x20000000 +#define SDR0_XCR_PISE_DISABLE 0x00000000 +#define SDR0_XCR_PISE_ENABLE 0x20000000 +#define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) +#define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) +#define SDR0_XCR_PCWE_MASK 0x10000000 +#define SDR0_XCR_PCWE_DISABLE 0x00000000 +#define SDR0_XCR_PCWE_ENABLE 0x10000000 +#define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) +#define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) +#define SDR0_XCR_PPIM_MASK 0x0F000000 +#define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) +#define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) +#define SDR0_XCR_PR64E_MASK 0x00800000 +#define SDR0_XCR_PR64E_DISABLE 0x00000000 +#define SDR0_XCR_PR64E_ENABLE 0x00800000 +#define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) +#define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) +#define SDR0_XCR_PXFS_MASK 0x00600000 +#define SDR0_XCR_PXFS_HIGH 0x00000000 +#define SDR0_XCR_PXFS_MED 0x00200000 +#define SDR0_XCR_PXFS_LOW 0x00400000 +#define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) +#define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) +#define SDR0_XCR_PDM_MASK 0x00000040 +#define SDR0_XCR_PDM_MULTIPOINT 0x00000000 +#define SDR0_XCR_PDM_P2P 0x00000040 +#define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19) +#define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01) + +#define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000 +#define SDR0_PFC0_GEIE_MASK 0x00003E00 +#define SDR0_PFC0_GEIE_TRE 0x00003E00 +#define SDR0_PFC0_GEIE_NOTRE 0x00000000 +#define SDR0_PFC0_TRE_MASK 0x00000100 +#define SDR0_PFC0_TRE_DISABLE 0x00000000 +#define SDR0_PFC0_TRE_ENABLE 0x00000100 +#define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) +#define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) + +#define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000 +#define SDR0_PFC1_EPS_MASK 0x01C00000 +#define SDR0_PFC1_EPS_GROUP0 0x00000000 +#define SDR0_PFC1_EPS_GROUP1 0x00400000 +#define SDR0_PFC1_EPS_GROUP2 0x00800000 +#define SDR0_PFC1_EPS_GROUP3 0x00C00000 +#define SDR0_PFC1_EPS_GROUP4 0x01000000 +#define SDR0_PFC1_EPS_GROUP5 0x01400000 +#define SDR0_PFC1_EPS_GROUP6 0x01800000 +#define SDR0_PFC1_EPS_GROUP7 0x01C00000 +#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) +#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) +#define SDR0_PFC1_RMII_MASK 0x00200000 +#define SDR0_PFC1_RMII_100MBIT 0x00000000 +#define SDR0_PFC1_RMII_10MBIT 0x00200000 +#define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21) +#define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01) +#define SDR0_PFC1_CTEMS_MASK 0x00100000 +#define SDR0_PFC1_CTEMS_EMS 0x00000000 +#define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000 + +#define SDR0_MFR_TAH0_MASK 0x80000000 +#define SDR0_MFR_TAH0_ENABLE 0x00000000 +#define SDR0_MFR_TAH0_DISABLE 0x80000000 +#define SDR0_MFR_TAH1_MASK 0x40000000 +#define SDR0_MFR_TAH1_ENABLE 0x00000000 +#define SDR0_MFR_TAH1_DISABLE 0x40000000 +#define SDR0_MFR_PCM_MASK 0x20000000 +#define SDR0_MFR_PCM_PPC440GX 0x00000000 +#define SDR0_MFR_PCM_PPC440GP 0x20000000 +#define SDR0_MFR_ECS_MASK 0x10000000 +#define SDR0_MFR_ECS_INTERNAL 0x10000000 + +#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ +#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ERRATA3_EN0 0x00800000 +#define SDR0_MFR_ERRATA3_EN1 0x00400000 +#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ + +#define SDR0_SRST_BGO 0x80000000 +#define SDR0_SRST_PLB 0x40000000 +#define SDR0_SRST_EBC 0x20000000 +#define SDR0_SRST_OPB 0x10000000 +#define SDR0_SRST_UART0 0x08000000 +#define SDR0_SRST_UART1 0x04000000 +#define SDR0_SRST_IIC0 0x02000000 +#define SDR0_SRST_IIC1 0x01000000 +#define SDR0_SRST_GPIO 0x00800000 +#define SDR0_SRST_GPT 0x00400000 +#define SDR0_SRST_DMC 0x00200000 +#define SDR0_SRST_PCI 0x00100000 +#define SDR0_SRST_EMAC0 0x00080000 +#define SDR0_SRST_EMAC1 0x00040000 +#define SDR0_SRST_CPM 0x00020000 +#define SDR0_SRST_IMU 0x00010000 +#define SDR0_SRST_UIC01 0x00008000 +#define SDR0_SRST_UICB2 0x00004000 +#define SDR0_SRST_SRAM 0x00002000 +#define SDR0_SRST_EBM 0x00001000 +#define SDR0_SRST_BGI 0x00000800 +#define SDR0_SRST_DMA 0x00000400 +#define SDR0_SRST_DMAC 0x00000200 +#define SDR0_SRST_MAL 0x00000100 +#define SDR0_SRST_ZMII 0x00000080 +#define SDR0_SRST_GPTR 0x00000040 +#define SDR0_SRST_PPM 0x00000020 +#define SDR0_SRST_EMAC2 0x00000010 +#define SDR0_SRST_EMAC3 0x00000008 +#define SDR0_SRST_RGMII 0x00000001 + +/*-----------------------------------------------------------------------------+ +| Clocking ++-----------------------------------------------------------------------------*/ +#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) +#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ +#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ +#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ +#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ +#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ +#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ +#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ +#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ +#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ + +#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ +#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ +#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ +#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ +#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */ +#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ +#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ +#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ +#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ +#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ +#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ + +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ +#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ + +#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PRADV_MASK 0x07000000 /* Primary Divisor A */ +#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + +#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ +#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ +#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ +#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ + +/* Strap 1 Register */ +#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ +#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ +#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ +#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ +#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ +#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ +#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ +#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ +#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ +#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ +#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ +#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ +#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ +#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ +#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ +#endif /* CONFIG_440GX */ + +/*----------------------------------------------------------------------------- +| IIC Register Offsets +'----------------------------------------------------------------------------*/ +#define IICMDBUF 0x00 +#define IICSDBUF 0x02 +#define IICLMADR 0x04 +#define IICHMADR 0x05 +#define IICCNTL 0x06 +#define IICMDCNTL 0x07 +#define IICSTS 0x08 +#define IICEXTSTS 0x09 +#define IICLSADR 0x0A +#define IICHSADR 0x0B +#define IICCLKDIV 0x0C +#define IICINTRMSK 0x0D +#define IICXFRCNT 0x0E +#define IICXTCNTLSS 0x0F +#define IICDIRECTCNTL 0x10 + +/*----------------------------------------------------------------------------- +| UART Register Offsets +'----------------------------------------------------------------------------*/ +#define DATA_REG 0x00 +#define DL_LSB 0x00 +#define DL_MSB 0x01 +#define INT_ENABLE 0x01 +#define FIFO_CONTROL 0x02 +#define LINE_CONTROL 0x03 +#define MODEM_CONTROL 0x04 +#define LINE_STATUS 0x05 +#define MODEM_STATUS 0x06 +#define SCRATCH 0x07 + +/*----------------------------------------------------------------------------- +| PCI Internal Registers et. al. (accessed via plb) ++----------------------------------------------------------------------------*/ +#define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000) +#define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004) +#define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000) +#define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000) + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + +/* PCI Local Configuration Registers + --------------------------------- */ +#define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ + +/* PCI Master Local Configuration Registers */ +#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ +#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ +#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ +#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ +#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ +#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ +#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ +#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ +#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ +#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ +#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ +#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ + +/* PCI Target Local Configuration Registers */ +#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */ +#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ +#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */ +#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ + +#else + +#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID ) +#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID ) +#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND ) +#define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS ) +#define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID ) +#define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE) +#define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE ) +#define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER ) +#define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE ) +#define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST ) +#define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 ) +#define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 ) +#define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 ) +#define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 ) +#define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 ) +#define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 ) +#define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS ) +#define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) +#define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID ) +#define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS ) +#define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST ) +#define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 ) +#define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 ) +#define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 ) +#define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE ) +#define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN ) +#define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT ) +#define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT ) + +#define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040) +#define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044) + +#define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068) +#define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c) +#define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070) +#define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074) +#define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078) +#define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c) +#define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080) +#define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084) +#define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088) +#define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c) +#define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090) + +#define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098) +#define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c) +#define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0) +#define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4) +#define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8) +#define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac) +#define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0) +#define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4) +#define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8) + +#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0) + +#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */ + +/****************************************************************************** + * GPIO macro register defines + ******************************************************************************/ +#if defined(CONFIG_440GP) +#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000700) + +#define GPIO0_OR (GPIO_BASE0+0x0) +#define GPIO0_TCR (GPIO_BASE0+0x4) +#define GPIO0_ODR (GPIO_BASE0+0x18) +#define GPIO0_IR (GPIO_BASE0+0x1C) +#endif /* CONFIG_440GP */ + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00) +#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00) + +#define GPIO0_OR (GPIO_BASE0+0x0) +#define GPIO0_TCR (GPIO_BASE0+0x4) +#define GPIO0_OSRL (GPIO_BASE0+0x8) +#define GPIO0_OSRH (GPIO_BASE0+0xC) +#define GPIO0_TSRL (GPIO_BASE0+0x10) +#define GPIO0_TSRH (GPIO_BASE0+0x14) +#define GPIO0_ODR (GPIO_BASE0+0x18) +#define GPIO0_IR (GPIO_BASE0+0x1C) +#define GPIO0_RR1 (GPIO_BASE0+0x20) +#define GPIO0_RR2 (GPIO_BASE0+0x24) +#define GPIO0_RR3 (GPIO_BASE0+0x28) +#define GPIO0_ISR1L (GPIO_BASE0+0x30) +#define GPIO0_ISR1H (GPIO_BASE0+0x34) +#define GPIO0_ISR2L (GPIO_BASE0+0x38) +#define GPIO0_ISR2H (GPIO_BASE0+0x3C) +#define GPIO0_ISR3L (GPIO_BASE0+0x40) +#define GPIO0_ISR3H (GPIO_BASE0+0x44) + +#define GPIO1_OR (GPIO_BASE1+0x0) +#define GPIO1_TCR (GPIO_BASE1+0x4) +#define GPIO1_OSRL (GPIO_BASE1+0x8) +#define GPIO1_OSRH (GPIO_BASE1+0xC) +#define GPIO1_TSRL (GPIO_BASE1+0x10) +#define GPIO1_TSRH (GPIO_BASE1+0x14) +#define GPIO1_ODR (GPIO_BASE1+0x18) +#define GPIO1_IR (GPIO_BASE1+0x1C) +#define GPIO1_RR1 (GPIO_BASE1+0x20) +#define GPIO1_RR2 (GPIO_BASE1+0x24) +#define GPIO1_RR3 (GPIO_BASE1+0x28) +#define GPIO1_ISR1L (GPIO_BASE1+0x30) +#define GPIO1_ISR1H (GPIO_BASE1+0x34) +#define GPIO1_ISR2L (GPIO_BASE1+0x38) +#define GPIO1_ISR2H (GPIO_BASE1+0x3C) +#define GPIO1_ISR3L (GPIO_BASE1+0x40) +#define GPIO1_ISR3H (GPIO_BASE1+0x44) +#endif + +/* + * Macros for accessing the indirect EBC registers + */ +#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) +#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) + +/* + * Macros for accessing the indirect SDRAM controller registers + */ +#define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) +#define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd) + +/* + * Macros for accessing the indirect clocking controller registers + */ +#define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data) +#define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd) + +/* + * Macros for accessing the sdr controller registers + */ +#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) +#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) + + +#ifndef __ASSEMBLY__ + +typedef struct { + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllFbkDiv; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllExtBusDiv; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long freqProcessor; + unsigned long freqTmrClk; + unsigned long freqPLB; + unsigned long freqOPB; + unsigned long freqEPB; + unsigned long freqPCI; + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pciClkSync; /* PCI clock is synchronous */ +} PPC440_SYS_INFO; + +#endif /* _ASMLANGUAGE */ + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */ + /* cache line aligned data. */ + +#endif /* __PPC440_H__ */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h new file mode 100644 index 0000000..67759c7 --- /dev/null +++ b/include/ppc4xx.h @@ -0,0 +1,32 @@ +/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC4XX_H__ +#define __PPC4XX_H__ + + +#if defined(CONFIG_440) +#include +#else +#include +#endif + +#endif /* __PPC4XX_H__ */ diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h new file mode 100644 index 0000000..d6d33b6 --- /dev/null +++ b/include/ppc4xx_enet.h @@ -0,0 +1,478 @@ +/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ +| +| File Name: enetemac.h +| +| Function: Header file for the EMAC3 macro on the 405GP. +| +| Author: Mark Wisner +| +| Change Activity- +| +| Date Description of Change BY +| --------- --------------------- --- +| 29-Apr-99 Created MKW +| ++----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ +| 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com +| ported to handle 440GP and 440GX multiple EMACs ++----------------------------------------------------------------------------*/ + +#ifndef _PPC4XX_ENET_H_ +#define _PPC4XX_ENET_H_ + +#include +#include "405_mal.h" + + +/*-----------------------------------------------------------------------------+ +| General enternet defines. 802 frames are not supported. ++-----------------------------------------------------------------------------*/ +#define ENET_ADDR_LENGTH 6 +#define ENET_ARPTYPE 0x806 +#define ARP_REQUEST 1 +#define ARP_REPLY 2 +#define ENET_IPTYPE 0x800 +#define ARP_CACHE_SIZE 5 + +#define NUM_TX_BUFF 1 +#define NUM_RX_BUFF PKTBUFSRX + +struct enet_frame { + unsigned char dest_addr[ENET_ADDR_LENGTH]; + unsigned char source_addr[ENET_ADDR_LENGTH]; + unsigned short type; + unsigned char enet_data[1]; +}; + +struct arp_entry { + unsigned long inet_address; + unsigned char mac_address[ENET_ADDR_LENGTH]; + unsigned long valid; + unsigned long sec; + unsigned long nsec; +}; + + +/* Statistic Areas */ +#define MAX_ERR_LOG 10 + +typedef struct emac_stats_st{ /* Statistic Block */ + int data_len_err; + int rx_frames; + int rx; + int rx_prot_err; + int int_err; + int pkts_tx; + int pkts_rx; + int pkts_handled; + short tx_err_log[MAX_ERR_LOG]; + short rx_err_log[MAX_ERR_LOG]; +} EMAC_STATS_ST, *EMAC_STATS_PST; + +/* Structure containing variables used by the shared code (4xx_enet.c) */ +typedef struct emac_4xx_hw_st { + uint32_t hw_addr; /* EMAC offset */ + uint32_t tah_addr; /* TAH offset */ + uint32_t phy_id; + uint32_t phy_addr; + uint32_t original_fc; + uint32_t txcw; + uint32_t autoneg_failed; + uint32_t emac_ier; + volatile mal_desc_t *tx; + volatile mal_desc_t *rx; + bd_t *bis; /* for eth_init upon mal error */ + mal_desc_t *alloc_tx_buf; + mal_desc_t *alloc_rx_buf; + char *txbuf_ptr; + uint16_t devnum; + int get_link_status; + int tbi_compatibility_en; + int tbi_compatibility_on; + int fc_send_xon; + int report_tx_early; + int first_init; + int tx_err_index; + int rx_err_index; + int rx_slot; /* MAL Receive Slot */ + int rx_i_index; /* Receive Interrupt Queue Index */ + int rx_u_index; /* Receive User Queue Index */ + int tx_slot; /* MAL Transmit Slot */ + int tx_i_index; /* Transmit Interrupt Queue Index */ + int tx_u_index; /* Transmit User Queue Index */ + int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */ + int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */ + int is_receiving; /* sync with eth interrupt */ + int print_speed; /* print speed message upon start */ + EMAC_STATS_ST stats; +} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST; + + +#if defined(CONFIG_440GX) +#define EMAC_NUM_DEV 4 +#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \ + defined(CONFIG_NET_MULTI) && \ + !defined(CONFIG_440SP) +#define EMAC_NUM_DEV 2 +#else +#define EMAC_NUM_DEV 1 +#endif + + +/*ZMII Bridge Register addresses */ +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) +#else +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) +#endif +#define ZMII_FER (ZMII_BASE) +#define ZMII_SSR (ZMII_BASE + 4) +#define ZMII_SMIISR (ZMII_BASE + 8) + +#define ZMII_RMII 0x22000000 +#define ZMII_MDI0 0x80000000 + +/* ZMII FER Register Bit Definitions */ +#define ZMII_FER_MDI (0x8) +#define ZMII_FER_SMII (0x4) +#define ZMII_FER_RMII (0x2) +#define ZMII_FER_MII (0x1) + +#define ZMII_FER_RSVD11 (0x00200000) +#define ZMII_FER_RSVD10 (0x00100000) +#define ZMII_FER_RSVD14_31 (0x0003FFFF) + +#define ZMII_FER_V(__x) (((3 - __x) * 4) + 16) + + +/* ZMII Speed Selection Register Bit Definitions */ +#define ZMII_SSR_SCI (0x4) +#define ZMII_SSR_FSS (0x2) +#define ZMII_SSR_SP (0x1) +#define ZMII_SSR_RSVD16_31 (0x0000FFFF) + +#define ZMII_SSR_V(__x) (((3 - __x) * 4) + 16) + + +/* ZMII SMII Status Register Bit Definitions */ +#define ZMII_SMIISR_E1 (0x80) +#define ZMII_SMIISR_EC (0x40) +#define ZMII_SMIISR_EN (0x20) +#define ZMII_SMIISR_EJ (0x10) +#define ZMII_SMIISR_EL (0x08) +#define ZMII_SMIISR_ED (0x04) +#define ZMII_SMIISR_ES (0x02) +#define ZMII_SMIISR_EF (0x01) + +#define ZMII_SMIISR_V(__x) ((3 - __x) * 8) + +/* RGMII Register Addresses */ +#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790) +#define RGMII_FER (RGMII_BASE + 0x00) +#define RGMII_SSR (RGMII_BASE + 0x04) + +/* RGMII Function Enable (FER) Register Bit Definitions */ +/* Note: for EMAC 2 and 3 only, 440GX only */ +#define RGMII_FER_DIS (0x00) +#define RGMII_FER_RTBI (0x04) +#define RGMII_FER_RGMII (0x05) +#define RGMII_FER_TBI (0x06) +#define RGMII_FER_GMII (0x07) + +#define RGMII_FER_V(__x) ((__x - 2) * 4) + +/* RGMII Speed Selection Register Bit Definitions */ +#define RGMII_SSR_SP_10MBPS (0x00) +#define RGMII_SSR_SP_100MBPS (0x02) +#define RGMII_SSR_SP_1000MBPS (0x04) + +#define RGMII_SSR_V(__x) ((__x -2) * 8) + + +/*---------------------------------------------------------------------------+ +| TCP/IP Acceleration Hardware (TAH) 440GX Only ++---------------------------------------------------------------------------*/ +#if defined(CONFIG_440GX) +#define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50) +#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/ +#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */ +#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */ +#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */ +#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */ +#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */ +#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */ +#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */ +#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */ + +/* TAH Revision */ +#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */ +#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */ + +#define TAH_REV_RN_V (8) +#define TAH_REV_BN_V (0) + +/* TAH Mode Register */ +#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */ +#define TAH_MR_SR (0x40000000) /* Software reset */ +#define TAH_MR_ST (0x3F000000) /* Send Threshold */ +#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */ +#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */ +#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */ +#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */ + +#define TAH_MR_ST_V (20) +#define TAH_MR_TFS_V (17) + +#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */ +#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */ +#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */ +#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */ +#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/ + + +/* TAH Segment Size Registers 0:5 */ +#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */ +#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */ +#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */ + +/* TAH Transmit Status Register */ +#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */ +#define TAH_TSR_UH (0x40000000) /* Unrecognized header */ +#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */ +#define TAH_TSR_IPOP (0x10000000) /* IP option present */ +#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */ +#define TAH_TSR_ILTS (0x04000000) /* IP length too short */ +#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */ +#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */ +#define TAH_TSR_TFP (0x00800000) /* TCP flags present */ +#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */ +#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */ +#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */ +#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */ +#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */ +#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */ +#endif /* CONFIG_440GX */ + + +/* Ethernet MAC Regsiter Addresses */ +#if defined(CONFIG_440) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) +#else +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) +#endif +#else +#define EMAC_BASE 0xEF600800 +#endif + +#define EMAC_M0 (EMAC_BASE) +#define EMAC_M1 (EMAC_BASE + 4) +#define EMAC_TXM0 (EMAC_BASE + 8) +#define EMAC_TXM1 (EMAC_BASE + 12) +#define EMAC_RXM (EMAC_BASE + 16) +#define EMAC_ISR (EMAC_BASE + 20) +#define EMAC_IER (EMAC_BASE + 24) +#define EMAC_IAH (EMAC_BASE + 28) +#define EMAC_IAL (EMAC_BASE + 32) +#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36) +#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40) +#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44) +#define EMAC_IND_HASH_1 (EMAC_BASE + 48) +#define EMAC_IND_HASH_2 (EMAC_BASE + 52) +#define EMAC_IND_HASH_3 (EMAC_BASE + 56) +#define EMAC_IND_HASH_4 (EMAC_BASE + 60) +#define EMAC_GRP_HASH_1 (EMAC_BASE + 64) +#define EMAC_GRP_HASH_2 (EMAC_BASE + 68) +#define EMAC_GRP_HASH_3 (EMAC_BASE + 72) +#define EMAC_GRP_HASH_4 (EMAC_BASE + 76) +#define EMAC_LST_SRC_LOW (EMAC_BASE + 80) +#define EMAC_LST_SRC_HI (EMAC_BASE + 84) +#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88) +#define EMAC_STACR (EMAC_BASE + 92) +#define EMAC_TRTR (EMAC_BASE + 96) +#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) + +/* bit definitions */ +/* MODE REG 0 */ +#define EMAC_M0_RXI (0x80000000) +#define EMAC_M0_TXI (0x40000000) +#define EMAC_M0_SRST (0x20000000) +#define EMAC_M0_TXE (0x10000000) +#define EMAC_M0_RXE (0x08000000) +#define EMAC_M0_WKE (0x04000000) + +/* on 440GX EMAC_MR1 has a different layout! */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +/* MODE Reg 1 */ +#define EMAC_M1_FDE (0x80000000) +#define EMAC_M1_ILE (0x40000000) +#define EMAC_M1_VLE (0x20000000) +#define EMAC_M1_EIFC (0x10000000) +#define EMAC_M1_APP (0x08000000) +#define EMAC_M1_RSVD (0x06000000) +#define EMAC_M1_IST (0x01000000) +#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ +#define EMAC_M1_MF_100MBPS (0x00400000) +#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_2K (0x00100000) +#define EMAC_M1_RFS_1K (0x00080000) +#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_8K (0x00040000) +#define EMAC_M1_TX_FIFO_4K (0x00030000) +#define EMAC_M1_TX_FIFO_2K (0x00020000) +#define EMAC_M1_TX_FIFO_1K (0x00010000) +#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ +#define EMAC_M1_MWSW (0x00007000) +#define EMAC_M1_JUMBO_ENABLE (0x00000800) +#define EMAC_M1_IPPA (0x000007c0) +#define EMAC_M1_OBCI_GT100 (0x00000020) +#define EMAC_M1_OBCI_100 (0x00000018) +#define EMAC_M1_OBCI_83 (0x00000010) +#define EMAC_M1_OBCI_66 (0x00000008) +#define EMAC_M1_RSVD1 (0x00000007) +#else /* defined(CONFIG_440GX) */ +/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */ +#define EMAC_M1_FDE 0x80000000 +#define EMAC_M1_ILE 0x40000000 +#define EMAC_M1_VLE 0x20000000 +#define EMAC_M1_EIFC 0x10000000 +#define EMAC_M1_APP 0x08000000 +#define EMAC_M1_AEMI 0x02000000 +#define EMAC_M1_IST 0x01000000 +#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ +#define EMAC_M1_MF_100MBPS 0x00400000 +#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ +#define EMAC_M1_RFS_2K 0x00200000 +#define EMAC_M1_RFS_1K 0x00100000 +#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_1K 0x00040000 +#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ +#define EMAC_M1_TR0_MULTI 0x00008000 +#define EMAC_M1_TR1_DEPEND 0x00004000 +#define EMAC_M1_TR1_MULTI 0x00002000 +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define EMAC_M1_JUMBO_ENABLE 0x00001000 +#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ +#endif /* defined(CONFIG_440GX) */ + +/* Transmit Mode Register 0 */ +#define EMAC_TXM0_GNP0 (0x80000000) +#define EMAC_TXM0_GNP1 (0x40000000) +#define EMAC_TXM0_GNPD (0x20000000) +#define EMAC_TXM0_FC (0x10000000) + +/* Receive Mode Register */ +#define EMAC_RMR_SP (0x80000000) +#define EMAC_RMR_SFCS (0x40000000) +#define EMAC_RMR_ARRP (0x20000000) +#define EMAC_RMR_ARP (0x10000000) +#define EMAC_RMR_AROP (0x08000000) +#define EMAC_RMR_ARPI (0x04000000) +#define EMAC_RMR_PPP (0x02000000) +#define EMAC_RMR_PME (0x01000000) +#define EMAC_RMR_PMME (0x00800000) +#define EMAC_RMR_IAE (0x00400000) +#define EMAC_RMR_MIAE (0x00200000) +#define EMAC_RMR_BAE (0x00100000) +#define EMAC_RMR_MAE (0x00080000) + +/* Interrupt Status & enable Regs */ +#define EMAC_ISR_OVR (0x02000000) +#define EMAC_ISR_PP (0x01000000) +#define EMAC_ISR_BP (0x00800000) +#define EMAC_ISR_RP (0x00400000) +#define EMAC_ISR_SE (0x00200000) +#define EMAC_ISR_SYE (0x00100000) +#define EMAC_ISR_BFCS (0x00080000) +#define EMAC_ISR_PTLE (0x00040000) +#define EMAC_ISR_ORE (0x00020000) +#define EMAC_ISR_IRE (0x00010000) +#define EMAC_ISR_DBDM (0x00000200) +#define EMAC_ISR_DB0 (0x00000100) +#define EMAC_ISR_SE0 (0x00000080) +#define EMAC_ISR_TE0 (0x00000040) +#define EMAC_ISR_DB1 (0x00000020) +#define EMAC_ISR_SE1 (0x00000010) +#define EMAC_ISR_TE1 (0x00000008) +#define EMAC_ISR_MOS (0x00000002) +#define EMAC_ISR_MOF (0x00000001) + + +/* STA CONTROL REG */ +#define EMAC_STACR_OC (0x00008000) +#define EMAC_STACR_PHYE (0x00004000) +#define EMAC_STACR_WRITE (0x00002000) +#define EMAC_STACR_READ (0x00001000) +#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */ +#define EMAC_STACR_CLK_66MHZ (0x00000400) +#define EMAC_STACR_CLK_100MHZ (0x00000C00) + +/* Transmit Request Threshold Register */ +#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ +#define EMAC_TRTR_192 (0x10000000) +#define EMAC_TRTR_128 (0x01000000) + +/* the follwing defines are for the MadMAL status and control registers. */ +/* For bits 0..5 look at the mal.h file */ +#define EMAC_TX_CTRL_GFCS (0x0200) +#define EMAC_TX_CTRL_GP (0x0100) +#define EMAC_TX_CTRL_ISA (0x0080) +#define EMAC_TX_CTRL_RSA (0x0040) +#define EMAC_TX_CTRL_IVT (0x0020) +#define EMAC_TX_CTRL_RVT (0x0010) + +#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP) + +#define EMAC_TX_ST_BFCS (0x0200) +#define EMAC_TX_ST_BPP (0x0100) +#define EMAC_TX_ST_LCS (0x0080) +#define EMAC_TX_ST_ED (0x0040) +#define EMAC_TX_ST_EC (0x0020) +#define EMAC_TX_ST_LC (0x0010) +#define EMAC_TX_ST_MC (0x0008) +#define EMAC_TX_ST_SC (0x0004) +#define EMAC_TX_ST_UR (0x0002) +#define EMAC_TX_ST_SQE (0x0001) + +#define EMAC_TX_ST_DEFAULT (0x03F3) + + +/* madmal receive status / Control bits */ + +#define EMAC_RX_ST_OE (0x0200) +#define EMAC_RX_ST_PP (0x0100) +#define EMAC_RX_ST_BP (0x0080) +#define EMAC_RX_ST_RP (0x0040) +#define EMAC_RX_ST_SE (0x0020) +#define EMAC_RX_ST_AE (0x0010) +#define EMAC_RX_ST_BFCS (0x0008) +#define EMAC_RX_ST_PTL (0x0004) +#define EMAC_RX_ST_ORE (0x0002) +#define EMAC_RX_ST_IRE (0x0001) +/* all the errors we care about */ +#define EMAC_RX_ERRORS (0x03FF) + +#endif /* _PPC4XX_ENET_H_ */ diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl new file mode 100644 index 0000000..72d690e --- /dev/null +++ b/include/ppc_asm.tmpl @@ -0,0 +1,322 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains all the macros and symbols which define + * a PowerPC assembly language environment. + */ +#ifndef __PPC_ASM_TMPL__ +#define __PPC_ASM_TMPL__ + +/*************************************************************************** + * + * These definitions simplify the ugly declarations necessary for GOT + * definitions. + * + * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es + * + * Uses r14 to access the GOT + */ + +#define START_GOT \ + .section ".got2","aw"; \ +.LCTOC1 = .+32768 + +#define END_GOT \ + .text + +#define GET_GOT \ + bl 1f ; \ + .text 2 ; \ +0: .long .LCTOC1-1f ; \ + .text ; \ +1: mflr r14 ; \ + lwz r0,0b-1b(r14) ; \ + add r14,r0,r14 ; + +#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME + +#define GOT(NAME) .L_ ## NAME (r14) + + +/*************************************************************************** + * Register names + */ +#define r0 0 +#define r1 1 +#define r2 2 +#define r3 3 +#define r4 4 +#define r5 5 +#define r6 6 +#define r7 7 +#define r8 8 +#define r9 9 +#define r10 10 +#define r11 11 +#define r12 12 +#define r13 13 +#define r14 14 +#define r15 15 +#define r16 16 +#define r17 17 +#define r18 18 +#define r19 19 +#define r20 20 +#define r21 21 +#define r22 22 +#define r23 23 +#define r24 24 +#define r25 25 +#define r26 26 +#define r27 27 +#define r28 28 +#define r29 29 +#define r30 30 +#define r31 31 + + +#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X) + +/* Some special registers */ + +#define ICR 148 /* Interrupt Cause Register (37-44) */ +#define DER 149 +#define COUNTA 150 /* Breakpoint Counter (37-44) */ +#define COUNTB 151 /* Breakpoint Counter (37-44) */ +#define LCTRL1 156 /* Load/Store Support (37-40) */ +#define LCTRL2 157 /* Load/Store Support (37-41) */ +#define ICTRL 158 + +#endif /* CONFIG_8xx, CONFIG_MPC824X */ + + +#if defined(CONFIG_5xx) +/* Some special purpose registers */ +#define DER 149 /* Debug Enable Register */ +#define COUNTA 150 /* Breakpoint Counter */ +#define COUNTB 151 /* Breakpoint Counter */ +#define LCTRL1 156 /* Load/Store Support */ +#define LCTRL2 157 /* Load/Store Support */ +#define ICTRL 158 /* I-Bus Support Control Register */ +#define EID 81 +#endif /* CONFIG_5xx */ + +#if defined(CONFIG_8xx) + +/* Registers in the processor's internal memory map that we use. +*/ +#define SYPCR 0x00000004 +#define BR0 0x00000100 +#define OR0 0x00000104 +#define BR1 0x00000108 +#define OR1 0x0000010c +#define BR2 0x00000110 +#define OR2 0x00000114 +#define BR3 0x00000118 +#define OR3 0x0000011c +#define BR4 0x00000120 +#define OR4 0x00000124 + +#define MAR 0x00000164 +#define MCR 0x00000168 +#define MAMR 0x00000170 +#define MBMR 0x00000174 +#define MSTAT 0x00000178 +#define MPTPR 0x0000017a +#define MDR 0x0000017c + +#define TBSCR 0x00000200 +#define TBREFF0 0x00000204 + +#define PLPRCR 0x00000284 + +#elif defined(CONFIG_8260) + +#define HID2 1011 + +#define HID0_IFEM (1<<7) + +#define HID0_ICE_BITPOS 16 +#define HID0_DCE_BITPOS 17 + +#define IM_REGBASE 0x10000 +#define IM_SYPCR (IM_REGBASE+0x0004) +#define IM_SWSR (IM_REGBASE+0x000e) +#define IM_BR0 (IM_REGBASE+0x0100) +#define IM_OR0 (IM_REGBASE+0x0104) +#define IM_BR1 (IM_REGBASE+0x0108) +#define IM_OR1 (IM_REGBASE+0x010c) +#define IM_BR2 (IM_REGBASE+0x0110) +#define IM_OR2 (IM_REGBASE+0x0114) +#define IM_MPTPR (IM_REGBASE+0x0184) +#define IM_PSDMR (IM_REGBASE+0x0190) +#define IM_PSRT (IM_REGBASE+0x019c) +#define IM_IMMR (IM_REGBASE+0x01a8) +#define IM_SCCR (IM_REGBASE+0x0c80) + +#elif defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8220) + +#define HID0_ICE_BITPOS 16 +#define HID0_DCE_BITPOS 17 + +#endif + +#define curptr r2 + +#define SYNC \ + sync; \ + isync + +/* + * Macros for storing registers into and loading registers from + * exception frames. + */ +#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) +#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) +#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) +#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) +#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) +#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) +#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) +#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) +#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) +#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) + +/* + * GCC sometimes accesses words at negative offsets from the stack + * pointer, although the SysV ABI says it shouldn't. To cope with + * this, we leave this much untouched space on the stack on exception + * entry. + */ +#define STACK_UNDERHEAD 64 + +/* + * Exception entry code. This code runs with address translation + * turned off, i.e. using physical addresses. + * We assume sprg3 has the physical address of the current + * task's thread_struct. + */ +#define EXCEPTION_PROLOG \ + mtspr SPRG0,r20; \ + mtspr SPRG1,r21; \ + mfcr r20; \ + subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ + stw r20,_CCR(r21); /* save registers */ \ + stw r22,GPR22(r21); \ + stw r23,GPR23(r21); \ + mfspr r20,SPRG0; \ + stw r20,GPR20(r21); \ + mfspr r22,SPRG1; \ + stw r22,GPR21(r21); \ + mflr r20; \ + stw r20,_LINK(r21); \ + mfctr r22; \ + stw r22,_CTR(r21); \ + mfspr r20,XER; \ + stw r20,_XER(r21); \ + mfspr r22,SRR0; \ + mfspr r23,SRR1; \ + stw r0,GPR0(r21); \ + stw r1,GPR1(r21); \ + stw r2,GPR2(r21); \ + stw r1,0(r21); \ + mr r1,r21; /* set new kernel sp */ \ + SAVE_4GPRS(3, r21); +/* + * Note: code which follows this uses cr0.eq (set if from kernel), + * r21, r22 (SRR0), and r23 (SRR1). + */ + +/* + * Critical exception entry code. This is just like the other exception + * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1. + */ +#define CRITICAL_EXCEPTION_PROLOG \ + mtspr SPRG0,r20; \ + mtspr SPRG1,r21; \ + mfcr r20; \ + subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ + stw r20,_CCR(r21); /* save registers */ \ + stw r22,GPR22(r21); \ + stw r23,GPR23(r21); \ + mfspr r20,SPRG0; \ + stw r20,GPR20(r21); \ + mfspr r22,SPRG1; \ + stw r22,GPR21(r21); \ + mflr r20; \ + stw r20,_LINK(r21); \ + mfctr r22; \ + stw r22,_CTR(r21); \ + mfspr r20,XER; \ + stw r20,_XER(r21); \ + mfspr r22,990; /* SRR2 */ \ + mfspr r23,991; /* SRR3 */ \ + stw r0,GPR0(r21); \ + stw r1,GPR1(r21); \ + stw r2,GPR2(r21); \ + stw r1,0(r21); \ + mr r1,r21; /* set new kernel sp */ \ + SAVE_4GPRS(3, r21); +/* + * Note: code which follows this uses cr0.eq (set if from kernel), + * r21, r22 (SRR2), and r23 (SRR3). + */ + +/* + * Exception vectors. + * + * The data words for `hdlr' and `int_return' are initialized with + * OFFSET values only; they must be relocated first before they can + * be used! + */ +#define STD_EXCEPTION(n, label, hdlr) \ + . = n; \ +label: \ + EXCEPTION_PROLOG; \ + lwz r3,GOT(transfer_to_handler); \ + mtlr r3; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + li r20,MSR_KERNEL; \ + rlwimi r20,r23,0,25,25; \ + blrl ; \ +.L_ ## label : \ + .long hdlr - _start + EXC_OFF_SYS_RESET; \ + .long int_return - _start + EXC_OFF_SYS_RESET + + +#define CRIT_EXCEPTION(n, label, hdlr) \ + . = n; \ +label: \ + CRITICAL_EXCEPTION_PROLOG; \ + lwz r3,GOT(transfer_to_handler); \ + mtlr r3; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + li r20,MSR_KERNEL; \ + rlwimi r20,r23,0,25,25; \ + blrl ; \ +.L_ ## label : \ + .long hdlr - _start + EXC_OFF_SYS_RESET; \ + .long crit_return - _start + EXC_OFF_SYS_RESET + +#endif /* __PPC_ASM_TMPL__ */ diff --git a/include/ppc_defs.h b/include/ppc_defs.h new file mode 100644 index 0000000..8b2b3b5 --- /dev/null +++ b/include/ppc_defs.h @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * WARNING! This file is automatically generated - DO NOT EDIT! + */ +#define KERNELBASE -1073741824 +#define STATE 0 +#define NEXT_TASK 64 +#define COUNTER 52 +#define PROCESSOR 916 +#define SIGPENDING 8 +#define TSS 576 +#define MM 880 +#define TASK_STRUCT_SIZE 928 +#define KSP 0 +#define PG_TABLES 4 +#define PGD 8 +#define LAST_SYSCALL 20 +#define PT_REGS 12 +#define PF_TRACESYS 32 +#define TASK_FLAGS 4 +#define TSS_FPR0 24 +#define TSS_FPSCR 284 +#define TSS_SMP_FORK_RET 288 +#define TASK_UNION_SIZE 8192 +#define STACK_FRAME_OVERHEAD 16 +#define INT_FRAME_SIZE 192 +#define GPR0 16 +#define GPR1 20 +#define GPR2 24 +#define GPR3 28 +#define GPR4 32 +#define GPR5 36 +#define GPR6 40 +#define GPR7 44 +#define GPR8 48 +#define GPR9 52 +#define GPR10 56 +#define GPR11 60 +#define GPR12 64 +#define GPR13 68 +#define GPR14 72 +#define GPR15 76 +#define GPR16 80 +#define GPR17 84 +#define GPR18 88 +#define GPR19 92 +#define GPR20 96 +#define GPR21 100 +#define GPR22 104 +#define GPR23 108 +#define GPR24 112 +#define GPR25 116 +#define GPR26 120 +#define GPR27 124 +#define GPR28 128 +#define GPR29 132 +#define GPR30 136 +#define GPR31 140 +#define _NIP 144 +#define _MSR 148 +#define _CTR 156 +#define _LINK 160 +#define _CCR 168 +#define _XER 164 +#define _DAR 180 +#define _DSISR 184 +#define ORIG_GPR3 152 +#define RESULT 188 +#define TRAP 176 diff --git a/include/ps2mult.h b/include/ps2mult.h new file mode 100644 index 0000000..e685817 --- /dev/null +++ b/include/ps2mult.h @@ -0,0 +1,155 @@ +#ifndef __LINUX_PS2MULT_H +#define __LINUX_PS2MULT_H + +#define kbd_request_region() ps2mult_init() +#define kbd_request_irq(handler) ps2mult_request_irq(handler) + +#define kbd_read_input() ps2mult_read_input() +#define kbd_read_status() ps2mult_read_status() +#define kbd_write_output(val) ps2mult_write_output(val) +#define kbd_write_command(val) ps2mult_write_command(val) + +#define aux_request_irq(hand, dev_id) 0 +#define aux_free_irq(dev_id) + +#define PS2MULT_KB_SELECTOR 0xA0 +#define PS2MULT_MS_SELECTOR 0xA1 +#define PS2MULT_ESCAPE 0x7D +#define PS2MULT_BSYNC 0x7E +#define PS2MULT_SESSION_START 0x55 +#define PS2MULT_SESSION_END 0x56 + +#define PS2BUF_SIZE 512 /* power of 2, please */ + +#ifndef CONFIG_PS2MULT_DELAY +#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ +#endif + + /* PS/2 controller interface (include/asm/keyboard.h) + */ +extern int ps2mult_init (void); +extern int ps2mult_request_irq(void (*handler)(void *)); +extern u_char ps2mult_read_input(void); +extern u_char ps2mult_read_status(void); +extern void ps2mult_write_output(u_char val); +extern void ps2mult_write_command(u_char val); + +extern void ps2mult_early_init (void); +extern void ps2mult_callback (int in_cnt); + + /* Simple serial interface + */ +extern int ps2ser_init(void); +extern void ps2ser_putc(int chr); +extern int ps2ser_getc(void); +extern int ps2ser_check(void); + + + /* Serial related stuff + */ +struct serial_state { + int baud_base; + int irq; + u8 *iomem_base; +}; + +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ + +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ +#define UART_IER 1 /* Out: Interrupt Enable Register */ + +#define UART_IIR 2 /* In: Interrupt ID Register */ +#define UART_FCR 2 /* Out: FIFO Control Register */ + +#define UART_LCR 3 /* Out: Line Control Register */ +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_LSR 5 /* In: Line Status Register */ +#define UART_MSR 6 /* In: Modem Status Register */ +#define UART_SCR 7 /* I/O: Scratch Register */ + +/* + * These are the definitions for the FIFO Control Register + * (16650 only) + */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +/* + * These are the definitions for the Modem Status Register + */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +#endif /* __LINUX_PS2MULT_H */ diff --git a/include/reiserfs.h b/include/reiserfs.h new file mode 100644 index 0000000..c465b3c --- /dev/null +++ b/include/reiserfs.h @@ -0,0 +1,82 @@ +/* + * Copyright 2000-2002 by Hans Reiser, licensing governed by reiserfs/README + * + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2000, 2001 Free Software Foundation, Inc. + * + * (C) Copyright 2003 Sysgo Real-Time Solutions, AG + * Pavel Bartusek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* An implementation for the ReiserFS filesystem ported from GRUB. + * Some parts of this code (mainly the structures and defines) are + * from the original reiser fs code, as found in the linux kernel. + */ + + +#define SECTOR_SIZE 0x200 +#define SECTOR_BITS 9 + +/* Error codes */ +typedef enum +{ + ERR_NONE = 0, + ERR_BAD_FILENAME, + ERR_BAD_FILETYPE, + ERR_BAD_GZIP_DATA, + ERR_BAD_GZIP_HEADER, + ERR_BAD_PART_TABLE, + ERR_BAD_VERSION, + ERR_BELOW_1MB, + ERR_BOOT_COMMAND, + ERR_BOOT_FAILURE, + ERR_BOOT_FEATURES, + ERR_DEV_FORMAT, + ERR_DEV_VALUES, + ERR_EXEC_FORMAT, + ERR_FILELENGTH, + ERR_FILE_NOT_FOUND, + ERR_FSYS_CORRUPT, + ERR_FSYS_MOUNT, + ERR_GEOM, + ERR_NEED_LX_KERNEL, + ERR_NEED_MB_KERNEL, + ERR_NO_DISK, + ERR_NO_PART, + ERR_NUMBER_PARSING, + ERR_OUTSIDE_PART, + ERR_READ, + ERR_SYMLINK_LOOP, + ERR_UNRECOGNIZED, + ERR_WONT_FIT, + ERR_WRITE, + ERR_BAD_ARGUMENT, + ERR_UNALIGNED, + ERR_PRIVILEGED, + ERR_DEV_NEED_INIT, + ERR_NO_DISK_SPACE, + ERR_NUMBER_OVERFLOW, + + MAX_ERR_NUM +} reiserfs_error_t; + + +extern int reiserfs_set_blk_dev(block_dev_desc_t *rbdd, int part); +extern int reiserfs_ls (char *dirname); +extern int reiserfs_open (char *filename); +extern int reiserfs_read (char *buf, unsigned len); +extern int reiserfs_mount (unsigned part_length); diff --git a/include/rtc.h b/include/rtc.h new file mode 100644 index 0000000..15f3571 --- /dev/null +++ b/include/rtc.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Generic RTC interface. + */ +#ifndef _RTC_H_ +#define _RTC_H_ + +/* + * The struct used to pass data from the generic interface code to + * the hardware dependend low-level code ande vice versa. Identical + * to struct rtc_time used by the Linux kernel. + * + * Note that there are small but significant differences to the + * common "struct time": + * + * struct time: struct rtc_time: + * tm_mon 0 ... 11 1 ... 12 + * tm_year years since 1900 years since 0 + */ + +struct rtc_time { + int tm_sec; + int tm_min; + int tm_hour; + int tm_mday; + int tm_mon; + int tm_year; + int tm_wday; + int tm_yday; + int tm_isdst; +}; + +void rtc_get (struct rtc_time *); +void rtc_set (struct rtc_time *); +void rtc_reset (void); + +void GregorianDay (struct rtc_time *); +void to_tm (int, struct rtc_time *); +unsigned long mktime (unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int); + +#endif /* _RTC_H_ */ diff --git a/include/s3c2400.h b/include/s3c2400.h new file mode 100644 index 0000000..bc1f1e9 --- /dev/null +++ b/include/s3c2400.h @@ -0,0 +1,554 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c2400.h + * Version : 31.3.2003 + * + * Based on S3C2400X User's manual Rev 1.1 + ************************************************/ + +#ifndef __S3C2400_H__ +#define __S3C2400_H__ + +#define S3C24X0_UART_CHANNELS 2 +#define S3C24X0_SPI_CHANNELS 1 +#define PALETTE (0x14A00400) /* SJS */ + +typedef enum { + S3C24X0_UART0, + S3C24X0_UART1, +} S3C24X0_UARTS_NR; + +/* S3C2400 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x14000000 +#define S3C24X0_USB_HOST_BASE 0x14200000 +#define S3C24X0_INTERRUPT_BASE 0x14400000 +#define S3C24X0_DMA_BASE 0x14600000 +#define S3C24X0_CLOCK_POWER_BASE 0x14800000 +#define S3C24X0_LCD_BASE 0x14A00000 +#define S3C24X0_UART_BASE 0x15000000 +#define S3C24X0_TIMER_BASE 0x15100000 +#define S3C24X0_USB_DEVICE_BASE 0x15200140 +#define S3C24X0_WATCHDOG_BASE 0x15300000 +#define S3C24X0_I2C_BASE 0x15400000 +#define S3C24X0_I2S_BASE 0x15508000 +#define S3C24X0_GPIO_BASE 0x15600000 +#define S3C24X0_RTC_BASE 0x15700000 +#define S3C24X0_ADC_BASE 0x15800000 +#define S3C24X0_SPI_BASE 0x15900000 +#define S3C2400_MMC_BASE 0x15A00000 + +/* include common stuff */ +#include + + +static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void) +{ + return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; +} +static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void) +{ + return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE; +} +static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void) +{ + return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE; +} +static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void) +{ + return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE; +} +static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void) +{ + return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE; +} +static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void) +{ + return (S3C24X0_LCD * const)S3C24X0_LCD_BASE; +} +static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) +{ + return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000)); +} +static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void) +{ + return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE; +} +static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void) +{ + return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE; +} +static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void) +{ + return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE; +} +static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void) +{ + return (S3C24X0_I2C * const)S3C24X0_I2C_BASE; +} +static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void) +{ + return (S3C24X0_I2S * const)S3C24X0_I2S_BASE; +} +static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void) +{ + return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE; +} +static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void) +{ + return (S3C24X0_RTC * const)S3C24X0_RTC_BASE; +} +static inline S3C2400_ADC * const S3C2400_GetBase_ADC(void) +{ + return (S3C2400_ADC * const)S3C24X0_ADC_BASE; +} +static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void) +{ + return (S3C24X0_SPI * const)S3C24X0_SPI_BASE; +} +static inline S3C2400_MMC * const S3C2400_GetBase_MMC(void) +{ + return (S3C2400_MMC * const)S3C2400_MMC_BASE; +} + +#if 0 +/* Memory control */ +#define rBWSCON (*(volatile unsigned *)0x14000000) +#define rBANKCON0 (*(volatile unsigned *)0x14000004) +#define rBANKCON1 (*(volatile unsigned *)0x14000008) +#define rBANKCON2 (*(volatile unsigned *)0x1400000C) +#define rBANKCON3 (*(volatile unsigned *)0x14000010) +#define rBANKCON4 (*(volatile unsigned *)0x14000014) +#define rBANKCON5 (*(volatile unsigned *)0x14000018) +#define rBANKCON6 (*(volatile unsigned *)0x1400001C) +#define rBANKCON7 (*(volatile unsigned *)0x14000020) +#define rREFRESH (*(volatile unsigned *)0x14000024) +#define rBANKSIZE (*(volatile unsigned *)0x14000028) +#define rMRSRB6 (*(volatile unsigned *)0x1400002C) +#define rMRSRB7 (*(volatile unsigned *)0x14000030) + + +/* INTERRUPT */ +#define rSRCPND (*(volatile unsigned *)0x14400000) +#define rINTMOD (*(volatile unsigned *)0x14400004) +#define rINTMSK (*(volatile unsigned *)0x14400008) +#define rPRIORITY (*(volatile unsigned *)0x1440000C) +#define rINTPND (*(volatile unsigned *)0x14400010) +#define rINTOFFSET (*(volatile unsigned *)0x14400014) + + +/* DMA */ +#define rDISRC0 (*(volatile unsigned *)0x14600000) +#define rDIDST0 (*(volatile unsigned *)0x14600004) +#define rDCON0 (*(volatile unsigned *)0x14600008) +#define rDSTAT0 (*(volatile unsigned *)0x1460000C) +#define rDCSRC0 (*(volatile unsigned *)0x14600010) +#define rDCDST0 (*(volatile unsigned *)0x14600014) +#define rDMASKTRIG0 (*(volatile unsigned *)0x14600018) +#define rDISRC1 (*(volatile unsigned *)0x14600020) +#define rDIDST1 (*(volatile unsigned *)0x14600024) +#define rDCON1 (*(volatile unsigned *)0x14600028) +#define rDSTAT1 (*(volatile unsigned *)0x1460002C) +#define rDCSRC1 (*(volatile unsigned *)0x14600030) +#define rDCDST1 (*(volatile unsigned *)0x14600034) +#define rDMASKTRIG1 (*(volatile unsigned *)0x14600038) +#define rDISRC2 (*(volatile unsigned *)0x14600040) +#define rDIDST2 (*(volatile unsigned *)0x14600044) +#define rDCON2 (*(volatile unsigned *)0x14600048) +#define rDSTAT2 (*(volatile unsigned *)0x1460004C) +#define rDCSRC2 (*(volatile unsigned *)0x14600050) +#define rDCDST2 (*(volatile unsigned *)0x14600054) +#define rDMASKTRIG2 (*(volatile unsigned *)0x14600058) +#define rDISRC3 (*(volatile unsigned *)0x14600060) +#define rDIDST3 (*(volatile unsigned *)0x14600064) +#define rDCON3 (*(volatile unsigned *)0x14600068) +#define rDSTAT3 (*(volatile unsigned *)0x1460006C) +#define rDCSRC3 (*(volatile unsigned *)0x14600070) +#define rDCDST3 (*(volatile unsigned *)0x14600074) +#define rDMASKTRIG3 (*(volatile unsigned *)0x14600078) + + +/* CLOCK & POWER MANAGEMENT */ +#define rLOCKTIME (*(volatile unsigned *)0x14800000) +#define rMPLLCON (*(volatile unsigned *)0x14800004) +#define rUPLLCON (*(volatile unsigned *)0x14800008) +#define rCLKCON (*(volatile unsigned *)0x1480000C) +#define rCLKSLOW (*(volatile unsigned *)0x14800010) +#define rCLKDIVN (*(volatile unsigned *)0x14800014) + + +/* LCD CONTROLLER */ +#define rLCDCON1 (*(volatile unsigned *)0x14A00000) +#define rLCDCON2 (*(volatile unsigned *)0x14A00004) +#define rLCDCON3 (*(volatile unsigned *)0x14A00008) +#define rLCDCON4 (*(volatile unsigned *)0x14A0000C) +#define rLCDCON5 (*(volatile unsigned *)0x14A00010) +#define rLCDSADDR1 (*(volatile unsigned *)0x14A00014) +#define rLCDSADDR2 (*(volatile unsigned *)0x14A00018) +#define rLCDSADDR3 (*(volatile unsigned *)0x14A0001C) +#define rREDLUT (*(volatile unsigned *)0x14A00020) +#define rGREENLUT (*(volatile unsigned *)0x14A00024) +#define rBLUELUT (*(volatile unsigned *)0x14A00028) +#define rDP1_2 (*(volatile unsigned *)0x14A0002C) +#define rDP4_7 (*(volatile unsigned *)0x14A00030) +#define rDP3_5 (*(volatile unsigned *)0x14A00034) +#define rDP2_3 (*(volatile unsigned *)0x14A00038) +#define rDP5_7 (*(volatile unsigned *)0x14A0003c) +#define rDP3_4 (*(volatile unsigned *)0x14A00040) +#define rDP4_5 (*(volatile unsigned *)0x14A00044) +#define rDP6_7 (*(volatile unsigned *)0x14A00048) +#define rDITHMODE (*(volatile unsigned *)0x14A0004C) +#define rTPAL (*(volatile unsigned *)0x14A00050) +#define PALETTE (0x14A00400) /* SJS */ + + +/* UART */ +#define rULCON0 (*(volatile unsigned char *)0x15000000) +#define rUCON0 (*(volatile unsigned short *)0x15000004) +#define rUFCON0 (*(volatile unsigned char *)0x15000008) +#define rUMCON0 (*(volatile unsigned char *)0x1500000C) +#define rUTRSTAT0 (*(volatile unsigned char *)0x15000010) +#define rUERSTAT0 (*(volatile unsigned char *)0x15000014) +#define rUFSTAT0 (*(volatile unsigned short *)0x15000018) +#define rUMSTAT0 (*(volatile unsigned char *)0x1500001C) +#define rUBRDIV0 (*(volatile unsigned short *)0x15000028) + +#define rULCON1 (*(volatile unsigned char *)0x15004000) +#define rUCON1 (*(volatile unsigned short *)0x15004004) +#define rUFCON1 (*(volatile unsigned char *)0x15004008) +#define rUMCON1 (*(volatile unsigned char *)0x1500400C) +#define rUTRSTAT1 (*(volatile unsigned char *)0x15004010) +#define rUERSTAT1 (*(volatile unsigned char *)0x15004014) +#define rUFSTAT1 (*(volatile unsigned short *)0x15004018) +#define rUMSTAT1 (*(volatile unsigned char *)0x1500401C) +#define rUBRDIV1 (*(volatile unsigned short *)0x15004028) + +#ifdef __BIG_ENDIAN +#define rUTXH0 (*(volatile unsigned char *)0x15000023) +#define rURXH0 (*(volatile unsigned char *)0x15000027) +#define rUTXH1 (*(volatile unsigned char *)0x15004023) +#define rURXH1 (*(volatile unsigned char *)0x15004027) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x15000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x15004027) + +#define UTXH0 (0x15000020+3) /* byte_access address by DMA */ +#define URXH0 (0x15000024+3) +#define UTXH1 (0x15004020+3) +#define URXH1 (0x15004024+3) + +#else /* Little Endian */ +#define rUTXH0 (*(volatile unsigned char *)0x15000020) +#define rURXH0 (*(volatile unsigned char *)0x15000024) +#define rUTXH1 (*(volatile unsigned char *)0x15004020) +#define rURXH1 (*(volatile unsigned char *)0x15004024) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x15000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x15004024) + +#define UTXH0 (0x15000020) /* byte_access address by DMA */ +#define URXH0 (0x15000024) +#define UTXH1 (0x15004020) +#define URXH1 (0x15004024) +#endif + + +/* PWM TIMER */ +#define rTCFG0 (*(volatile unsigned *)0x15100000) +#define rTCFG1 (*(volatile unsigned *)0x15100004) +#define rTCON (*(volatile unsigned *)0x15100008) +#define rTCNTB0 (*(volatile unsigned *)0x1510000C) +#define rTCMPB0 (*(volatile unsigned *)0x15100010) +#define rTCNTO0 (*(volatile unsigned *)0x15100014) +#define rTCNTB1 (*(volatile unsigned *)0x15100018) +#define rTCMPB1 (*(volatile unsigned *)0x1510001C) +#define rTCNTO1 (*(volatile unsigned *)0x15100020) +#define rTCNTB2 (*(volatile unsigned *)0x15100024) +#define rTCMPB2 (*(volatile unsigned *)0x15100028) +#define rTCNTO2 (*(volatile unsigned *)0x1510002C) +#define rTCNTB3 (*(volatile unsigned *)0x15100030) +#define rTCMPB3 (*(volatile unsigned *)0x15100034) +#define rTCNTO3 (*(volatile unsigned *)0x15100038) +#define rTCNTB4 (*(volatile unsigned *)0x1510003C) +#define rTCNTO4 (*(volatile unsigned *)0x15100040) + + +/* USB DEVICE */ +#define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140) +#define rPWR_REG (*(volatile unsigned *)0x15200144) +#define rINT_REG (*(volatile unsigned *)0x15200148) +#define rINT_MASK_REG (*(volatile unsigned *)0x1520014C) +#define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150) +#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154) +#define rEP0_CSR (*(volatile unsigned *)0x15200160) +#define rEP0_MAXP (*(volatile unsigned *)0x15200164) +#define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168) +#define rEP0_FIFO (*(volatile unsigned *)0x1520016C) +#define rEP1_IN_CSR (*(volatile unsigned *)0x15200180) +#define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184) +#define rEP1_FIFO (*(volatile unsigned *)0x15200188) +#define rEP2_IN_CSR (*(volatile unsigned *)0x15200190) +#define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194) +#define rEP2_FIFO (*(volatile unsigned *)0x15200198) +#define rEP3_OUT_CSR (*(volatile unsigned *)0x152001A0) +#define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001A4) +#define rEP3_OUT_CNT (*(volatile unsigned *)0x152001A8) +#define rEP3_FIFO (*(volatile unsigned *)0x152001AC) +#define rEP4_OUT_CSR (*(volatile unsigned *)0x152001B0) +#define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001B4) +#define rEP4_OUT_CNT (*(volatile unsigned *)0x152001B8) +#define rEP4_FIFO (*(volatile unsigned *)0x152001BC) +#define rDMA_CON (*(volatile unsigned *)0x152001C0) +#define rDMA_UNIT (*(volatile unsigned *)0x152001C4) +#define rDMA_FIFO (*(volatile unsigned *)0x152001C8) +#define rDMA_TX (*(volatile unsigned *)0x152001CC) +#define rTEST_MODE (*(volatile unsigned *)0x152001F4) +#define rIN_CON_REG (*(volatile unsigned *)0x152001F8) + + +/* WATCH DOG TIMER */ +#define rWTCON (*(volatile unsigned *)0x15300000) +#define rWTDAT (*(volatile unsigned *)0x15300004) +#define rWTCNT (*(volatile unsigned *)0x15300008) + + +/* IIC */ +#define rIICCON (*(volatile unsigned *)0x15400000) +#define rIICSTAT (*(volatile unsigned *)0x15400004) +#define rIICADD (*(volatile unsigned *)0x15400008) +#define rIICDS (*(volatile unsigned *)0x1540000C) + + +/* IIS */ +#define rIISCON (*(volatile unsigned *)0x15508000) +#define rIISMOD (*(volatile unsigned *)0x15508004) +#define rIISPSR (*(volatile unsigned *)0x15508008) +#define rIISFIFCON (*(volatile unsigned *)0x1550800C) + +#ifdef __BIG_ENDIAN +#define IISFIF ((volatile unsigned short *)0x15508012) + +#else /* Little Endian */ +#define IISFIF ((volatile unsigned short *)0x15508010) +#endif + + +/* I/O PORT */ +#define rPACON (*(volatile unsigned *)0x15600000) +#define rPADAT (*(volatile unsigned *)0x15600004) + +#define rPBCON (*(volatile unsigned *)0x15600008) +#define rPBDAT (*(volatile unsigned *)0x1560000C) +#define rPBUP (*(volatile unsigned *)0x15600010) + +#define rPCCON (*(volatile unsigned *)0x15600014) +#define rPCDAT (*(volatile unsigned *)0x15600018) +#define rPCUP (*(volatile unsigned *)0x1560001C) + +#define rPDCON (*(volatile unsigned *)0x15600020) +#define rPDDAT (*(volatile unsigned *)0x15600024) +#define rPDUP (*(volatile unsigned *)0x15600028) + +#define rPECON (*(volatile unsigned *)0x1560002C) +#define rPEDAT (*(volatile unsigned *)0x15600030) +#define rPEUP (*(volatile unsigned *)0x15600034) + +#define rPFCON (*(volatile unsigned *)0x15600038) +#define rPFDAT (*(volatile unsigned *)0x1560003C) +#define rPFUP (*(volatile unsigned *)0x15600040) + +#define rPGCON (*(volatile unsigned *)0x15600044) +#define rPGDAT (*(volatile unsigned *)0x15600048) +#define rPGUP (*(volatile unsigned *)0x1560004C) + +#define rOPENCR (*(volatile unsigned *)0x15600050) +#define rMISCCR (*(volatile unsigned *)0x15600054) +#define rEXTINT (*(volatile unsigned *)0x15600058) + + +/* RTC */ +#ifdef __BIG_ENDIAN +#define rRTCCON (*(volatile unsigned char *)0x15700043) +#define rRTCALM (*(volatile unsigned char *)0x15700053) +#define rALMSEC (*(volatile unsigned char *)0x15700057) +#define rALMMIN (*(volatile unsigned char *)0x1570005B) +#define rALMHOUR (*(volatile unsigned char *)0x1570005F) +#define rALMDAY (*(volatile unsigned char *)0x15700063) +#define rALMMON (*(volatile unsigned char *)0x15700067) +#define rALMYEAR (*(volatile unsigned char *)0x1570006B) +#define rRTCRST (*(volatile unsigned char *)0x1570006F) +#define rBCDSEC (*(volatile unsigned char *)0x15700073) +#define rBCDMIN (*(volatile unsigned char *)0x15700077) +#define rBCDHOUR (*(volatile unsigned char *)0x1570007B) +#define rBCDDAY (*(volatile unsigned char *)0x1570007F) +#define rBCDDATE (*(volatile unsigned char *)0x15700083) +#define rBCDMON (*(volatile unsigned char *)0x15700087) +#define rBCDYEAR (*(volatile unsigned char *)0x1570008B) +#define rTICINT (*(volatile unsigned char *)0x15700047) + +#else /* Little Endian */ +#define rRTCCON (*(volatile unsigned char *)0x15700040) +#define rRTCALM (*(volatile unsigned char *)0x15700050) +#define rALMSEC (*(volatile unsigned char *)0x15700054) +#define rALMMIN (*(volatile unsigned char *)0x15700058) +#define rALMHOUR (*(volatile unsigned char *)0x1570005C) +#define rALMDAY (*(volatile unsigned char *)0x15700060) +#define rALMMON (*(volatile unsigned char *)0x15700064) +#define rALMYEAR (*(volatile unsigned char *)0x15700068) +#define rRTCRST (*(volatile unsigned char *)0x1570006C) +#define rBCDSEC (*(volatile unsigned char *)0x15700070) +#define rBCDMIN (*(volatile unsigned char *)0x15700074) +#define rBCDHOUR (*(volatile unsigned char *)0x15700078) +#define rBCDDAY (*(volatile unsigned char *)0x1570007C) +#define rBCDDATE (*(volatile unsigned char *)0x15700080) +#define rBCDMON (*(volatile unsigned char *)0x15700084) +#define rBCDYEAR (*(volatile unsigned char *)0x15700088) +#define rTICINT (*(volatile unsigned char *)0x15700044) +#endif + + +/* ADC */ +#define rADCCON (*(volatile unsigned *)0x15800000) +#define rADCDAT (*(volatile unsigned *)0x15800004) + + +/* SPI */ +#define rSPCON (*(volatile unsigned *)0x15900000) +#define rSPSTA (*(volatile unsigned *)0x15900004) +#define rSPPIN (*(volatile unsigned *)0x15900008) +#define rSPPRE (*(volatile unsigned *)0x1590000C) +#define rSPTDAT (*(volatile unsigned *)0x15900010) +#define rSPRDAT (*(volatile unsigned *)0x15900014) + + +/* MMC INTERFACE */ +#define rMMCON (*(volatile unsigned *)0x15a00000) +#define rMMCRR (*(volatile unsigned *)0x15a00004) +#define rMMFCON (*(volatile unsigned *)0x15a00008) +#define rMMSTA (*(volatile unsigned *)0x15a0000C) +#define rMMFSTA (*(volatile unsigned *)0x15a00010) +#define rMMPRE (*(volatile unsigned *)0x15a00014) +#define rMMLEN (*(volatile unsigned *)0x15a00018) +#define rMMCR7 (*(volatile unsigned *)0x15a0001C) +#define rMMRSP0 (*(volatile unsigned *)0x15a00020) +#define rMMRSP1 (*(volatile unsigned *)0x15a00024) +#define rMMRSP2 (*(volatile unsigned *)0x15a00028) +#define rMMRSP3 (*(volatile unsigned *)0x15a0002C) +#define rMMCMD0 (*(volatile unsigned *)0x15a00030) +#define rMMCMD1 (*(volatile unsigned *)0x15a00034) +#define rMMCR16 (*(volatile unsigned *)0x15a00038) +#define rMMDAT (*(volatile unsigned *)0x15a0003C) + + +/* ISR */ +#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) +#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) +#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) +#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) +#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) +#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) +#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) +#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) + +#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) +#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) +#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) +#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) +#define pISR_EINT4 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) +#define pISR_EINT5 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) +#define pISR_EINT6 (*(unsigned *)(_ISR_STARTADDRESS+0x38)) +#define pISR_EINT7 (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) +#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) +#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) +#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) +#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) +#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) +#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) +#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) +#define pISR_UERR01 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) +#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) +#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) +#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) +#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) +#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) +#define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74)) +#define pISR_SPI (*(unsigned *)(_ISR_STARTADDRESS+0x78)) +#define pISR_URXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) +#define pISR_URXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x80)) +#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) +#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) +#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) +#define pISR_UTXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) +#define pISR_UTXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) +#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) +#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) + + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4 (0x1<<4) +#define BIT_EINT5 (0x1<<5) +#define BIT_EINT6 (0x1<<6) +#define BIT_EINT7 (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UERR01 (0x1<<15) +#define BIT_NOTUSED (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_MMC (0x1<<21) +#define BIT_SPI (0x1<<22) +#define BIT_URXD0 (0x1<<23) +#define BIT_URXD1 (0x1<<24) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UTXD0 (0x1<<28) +#define BIT_UTXD1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define ClearPending(bit) {\ + rSRCPND = bit;\ + rINTPND = bit;\ + rINTPND;\ + } +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif +#endif /*__S3C2400_H__*/ diff --git a/include/s3c2410.h b/include/s3c2410.h new file mode 100644 index 0000000..86495f6 --- /dev/null +++ b/include/s3c2410.h @@ -0,0 +1,227 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c2410.h + * Version : 31.3.2003 + * + * Based on S3C2410X User's manual Rev 1.1 + ************************************************/ + +#ifndef __S3C2410_H__ +#define __S3C2410_H__ + +#define S3C24X0_UART_CHANNELS 3 +#define S3C24X0_SPI_CHANNELS 2 + +/* S3C2410 only supports 512 Byte HW ECC */ +#define S3C2410_ECCSIZE 512 +#define S3C2410_ECCBYTES 3 + +typedef enum { + S3C24X0_UART0, + S3C24X0_UART1, + S3C24X0_UART2 +} S3C24X0_UARTS_NR; + +/* S3C2410 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C24X0_USB_HOST_BASE 0x49000000 +#define S3C24X0_INTERRUPT_BASE 0x4A000000 +#define S3C24X0_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C24X0_LCD_BASE 0x4D000000 +#define S3C2410_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C24X0_I2C_BASE 0x54000000 +#define S3C24X0_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_RTC_BASE 0x57000000 +#define S3C2410_ADC_BASE 0x58000000 +#define S3C24X0_SPI_BASE 0x59000000 +#define S3C2410_SDI_BASE 0x5A000000 + + +/* include common stuff */ +#include + + +static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void) +{ + return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; +} +static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void) +{ + return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE; +} +static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void) +{ + return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE; +} +static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void) +{ + return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE; +} +static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void) +{ + return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE; +} +static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void) +{ + return (S3C24X0_LCD * const)S3C24X0_LCD_BASE; +} +static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void) +{ + return (S3C2410_NAND * const)S3C2410_NAND_BASE; +} +static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) +{ + return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000)); +} +static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void) +{ + return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE; +} +static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void) +{ + return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE; +} +static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void) +{ + return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE; +} +static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void) +{ + return (S3C24X0_I2C * const)S3C24X0_I2C_BASE; +} +static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void) +{ + return (S3C24X0_I2S * const)S3C24X0_I2S_BASE; +} +static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void) +{ + return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE; +} +static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void) +{ + return (S3C24X0_RTC * const)S3C24X0_RTC_BASE; +} +static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void) +{ + return (S3C2410_ADC * const)S3C2410_ADC_BASE; +} +static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void) +{ + return (S3C24X0_SPI * const)S3C24X0_SPI_BASE; +} +static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void) +{ + return (S3C2410_SDI * const)S3C2410_SDI_BASE; +} + + +/* ISR */ +#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) +#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) +#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) +#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) +#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) +#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) +#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) +#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) + +#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) +#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) +#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) +#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) +#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) +#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) +#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) +#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) +#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) +#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) +#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) +#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) +#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) +#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) +#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) +#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) +#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) +#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) +#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) +#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) +#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74)) +#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78)) +#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) +#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) +#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) +#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) +#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) +#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) +#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) +#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) + + +/* PENDING BIT */ +#define BIT_EINT0 (0x1) +#define BIT_EINT1 (0x1<<1) +#define BIT_EINT2 (0x1<<2) +#define BIT_EINT3 (0x1<<3) +#define BIT_EINT4_7 (0x1<<4) +#define BIT_EINT8_23 (0x1<<5) +#define BIT_BAT_FLT (0x1<<7) +#define BIT_TICK (0x1<<8) +#define BIT_WDT (0x1<<9) +#define BIT_TIMER0 (0x1<<10) +#define BIT_TIMER1 (0x1<<11) +#define BIT_TIMER2 (0x1<<12) +#define BIT_TIMER3 (0x1<<13) +#define BIT_TIMER4 (0x1<<14) +#define BIT_UART2 (0x1<<15) +#define BIT_LCD (0x1<<16) +#define BIT_DMA0 (0x1<<17) +#define BIT_DMA1 (0x1<<18) +#define BIT_DMA2 (0x1<<19) +#define BIT_DMA3 (0x1<<20) +#define BIT_SDI (0x1<<21) +#define BIT_SPI0 (0x1<<22) +#define BIT_UART1 (0x1<<23) +#define BIT_USBD (0x1<<25) +#define BIT_USBH (0x1<<26) +#define BIT_IIC (0x1<<27) +#define BIT_UART0 (0x1<<28) +#define BIT_SPI1 (0x1<<29) +#define BIT_RTC (0x1<<30) +#define BIT_ADC (0x1<<31) +#define BIT_ALLMSK (0xFFFFFFFF) + +#define ClearPending(bit) {\ + rSRCPND = bit;\ + rINTPND = bit;\ + rINTPND;\ + } +/* Wait until rINTPND is changed for the case that the ISR is very short. */ +#endif /*__S3C2410_H__*/ diff --git a/include/s3c24x0.h b/include/s3c24x0.h new file mode 100644 index 0000000..71f35a5 --- /dev/null +++ b/include/s3c24x0.h @@ -0,0 +1,1135 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c24x0.h + * Version : 31.3.2003 + * + * common stuff for SAMSUNG S3C24X0 SoC + ************************************************/ + +#ifndef __S3C24X0_H__ +#define __S3C24X0_H__ + +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; + +/* Memory controller (see manual chapter 5) */ +typedef struct { + S3C24X0_REG32 BWSCON; + S3C24X0_REG32 BANKCON[8]; + S3C24X0_REG32 REFRESH; + S3C24X0_REG32 BANKSIZE; + S3C24X0_REG32 MRSRB6; + S3C24X0_REG32 MRSRB7; +} /*__attribute__((__packed__))*/ S3C24X0_MEMCTL; + + +/* USB HOST (see manual chapter 12) */ +typedef struct { + S3C24X0_REG32 HcRevision; + S3C24X0_REG32 HcControl; + S3C24X0_REG32 HcCommonStatus; + S3C24X0_REG32 HcInterruptStatus; + S3C24X0_REG32 HcInterruptEnable; + S3C24X0_REG32 HcInterruptDisable; + S3C24X0_REG32 HcHCCA; + S3C24X0_REG32 HcPeriodCuttendED; + S3C24X0_REG32 HcControlHeadED; + S3C24X0_REG32 HcControlCurrentED; + S3C24X0_REG32 HcBulkHeadED; + S3C24X0_REG32 HcBuldCurrentED; + S3C24X0_REG32 HcDoneHead; + S3C24X0_REG32 HcRmInterval; + S3C24X0_REG32 HcFmRemaining; + S3C24X0_REG32 HcFmNumber; + S3C24X0_REG32 HcPeriodicStart; + S3C24X0_REG32 HcLSThreshold; + S3C24X0_REG32 HcRhDescriptorA; + S3C24X0_REG32 HcRhDescriptorB; + S3C24X0_REG32 HcRhStatus; + S3C24X0_REG32 HcRhPortStatus1; + S3C24X0_REG32 HcRhPortStatus2; +} /*__attribute__((__packed__))*/ S3C24X0_USB_HOST; + + +/* INTERRUPT (see manual chapter 14) */ +typedef struct { + S3C24X0_REG32 SRCPND; + S3C24X0_REG32 INTMOD; + S3C24X0_REG32 INTMSK; + S3C24X0_REG32 PRIORITY; + S3C24X0_REG32 INTPND; + S3C24X0_REG32 INTOFFSET; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 SUBSRCPND; + S3C24X0_REG32 INTSUBMSK; +#endif +} /*__attribute__((__packed__))*/ S3C24X0_INTERRUPT; + + +/* DMAS (see manual chapter 8) */ +typedef struct { + S3C24X0_REG32 DISRC; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 DISRCC; +#endif + S3C24X0_REG32 DIDST; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 DIDSTC; +#endif + S3C24X0_REG32 DCON; + S3C24X0_REG32 DSTAT; + S3C24X0_REG32 DCSRC; + S3C24X0_REG32 DCDST; + S3C24X0_REG32 DMASKTRIG; +#ifdef CONFIG_S3C2400 + S3C24X0_REG32 res[1]; +#endif +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 res[7]; +#endif +} /*__attribute__((__packed__))*/ S3C24X0_DMA; + +typedef struct { + S3C24X0_DMA dma[4]; +} /*__attribute__((__packed__))*/ S3C24X0_DMAS; + + +/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ +/* (see S3C2410 manual chapter 7) */ +typedef struct { + S3C24X0_REG32 LOCKTIME; + S3C24X0_REG32 MPLLCON; + S3C24X0_REG32 UPLLCON; + S3C24X0_REG32 CLKCON; + S3C24X0_REG32 CLKSLOW; + S3C24X0_REG32 CLKDIVN; +} /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER; + + +/* LCD CONTROLLER (see manual chapter 15) */ +typedef struct { + S3C24X0_REG32 LCDCON1; + S3C24X0_REG32 LCDCON2; + S3C24X0_REG32 LCDCON3; + S3C24X0_REG32 LCDCON4; + S3C24X0_REG32 LCDCON5; + S3C24X0_REG32 LCDSADDR1; + S3C24X0_REG32 LCDSADDR2; + S3C24X0_REG32 LCDSADDR3; + S3C24X0_REG32 REDLUT; + S3C24X0_REG32 GREENLUT; + S3C24X0_REG32 BLUELUT; + S3C24X0_REG32 res[8]; + S3C24X0_REG32 DITHMODE; + S3C24X0_REG32 TPAL; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 LCDINTPND; + S3C24X0_REG32 LCDSRCPND; + S3C24X0_REG32 LCDINTMSK; + S3C24X0_REG32 LPCSEL; +#endif +} /*__attribute__((__packed__))*/ S3C24X0_LCD; + + +/* NAND FLASH (see S3C2410 manual chapter 6) */ +typedef struct { + S3C24X0_REG32 NFCONF; + S3C24X0_REG32 NFCMD; + S3C24X0_REG32 NFADDR; + S3C24X0_REG32 NFDATA; + S3C24X0_REG32 NFSTAT; + S3C24X0_REG32 NFECC; +} /*__attribute__((__packed__))*/ S3C2410_NAND; + + +/* UART (see manual chapter 11) */ +typedef struct { + S3C24X0_REG32 ULCON; + S3C24X0_REG32 UCON; + S3C24X0_REG32 UFCON; + S3C24X0_REG32 UMCON; + S3C24X0_REG32 UTRSTAT; + S3C24X0_REG32 UERSTAT; + S3C24X0_REG32 UFSTAT; + S3C24X0_REG32 UMSTAT; +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 UTXH; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 URXH; +#else /* Little Endian */ + S3C24X0_REG8 UTXH; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 URXH; + S3C24X0_REG8 res2[3]; +#endif + S3C24X0_REG32 UBRDIV; +} /*__attribute__((__packed__))*/ S3C24X0_UART; + + +/* PWM TIMER (see manual chapter 10) */ +typedef struct { + S3C24X0_REG32 TCNTB; + S3C24X0_REG32 TCMPB; + S3C24X0_REG32 TCNTO; +} /*__attribute__((__packed__))*/ S3C24X0_TIMER; + +typedef struct { + S3C24X0_REG32 TCFG0; + S3C24X0_REG32 TCFG1; + S3C24X0_REG32 TCON; + S3C24X0_TIMER ch[4]; + S3C24X0_REG32 TCNTB4; + S3C24X0_REG32 TCNTO4; +} /*__attribute__((__packed__))*/ S3C24X0_TIMERS; + + +/* USB DEVICE (see manual chapter 13) */ +typedef struct { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res[3]; + S3C24X0_REG8 EP_FIFO_REG; +#else /* little endian */ + S3C24X0_REG8 EP_FIFO_REG; + S3C24X0_REG8 res[3]; +#endif +} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_FIFOS; + +typedef struct { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 EP_DMA_CON; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 EP_DMA_UNIT; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 EP_DMA_FIFO; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 EP_DMA_TTC_L; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 EP_DMA_TTC_M; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 EP_DMA_TTC_H; +#else /* little endian */ + S3C24X0_REG8 EP_DMA_CON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 EP_DMA_UNIT; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 EP_DMA_FIFO; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 EP_DMA_TTC_L; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 EP_DMA_TTC_M; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 EP_DMA_TTC_H; + S3C24X0_REG8 res6[3]; +#endif +} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS; + +typedef struct { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 FUNC_ADDR_REG; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 PWR_REG; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 EP_INT_REG; + S3C24X0_REG8 res4[15]; + S3C24X0_REG8 USB_INT_REG; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 EP_INT_EN_REG; + S3C24X0_REG8 res6[15]; + S3C24X0_REG8 USB_INT_EN_REG; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 FRAME_NUM1_REG; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 FRAME_NUM2_REG; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 INDEX_REG; + S3C24X0_REG8 res10[7]; + S3C24X0_REG8 MAXP_REG; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 IN_CSR2_REG; + S3C24X0_REG8 res13[7]; + S3C24X0_REG8 OUT_CSR1_REG; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 OUT_CSR2_REG; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 OUT_FIFO_CNT1_REG; + S3C24X0_REG8 res16[3]; + S3C24X0_REG8 OUT_FIFO_CNT2_REG; +#else /* little endian */ + S3C24X0_REG8 FUNC_ADDR_REG; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 PWR_REG; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 EP_INT_REG; + S3C24X0_REG8 res3[15]; + S3C24X0_REG8 USB_INT_REG; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 EP_INT_EN_REG; + S3C24X0_REG8 res5[15]; + S3C24X0_REG8 USB_INT_EN_REG; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 FRAME_NUM1_REG; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 FRAME_NUM2_REG; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 INDEX_REG; + S3C24X0_REG8 res9[7]; + S3C24X0_REG8 MAXP_REG; + S3C24X0_REG8 res10[7]; + S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 IN_CSR2_REG; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 OUT_CSR1_REG; + S3C24X0_REG8 res13[7]; + S3C24X0_REG8 OUT_CSR2_REG; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 OUT_FIFO_CNT1_REG; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 OUT_FIFO_CNT2_REG; + S3C24X0_REG8 res16[3]; +#endif /* __BIG_ENDIAN */ + S3C24X0_USB_DEV_FIFOS fifo[5]; + S3C24X0_USB_DEV_DMAS dma[5]; +} /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE; + + +/* WATCH DOG TIMER (see manual chapter 18) */ +typedef struct { + S3C24X0_REG32 WTCON; + S3C24X0_REG32 WTDAT; + S3C24X0_REG32 WTCNT; +} /*__attribute__((__packed__))*/ S3C24X0_WATCHDOG; + + +/* IIC (see manual chapter 20) */ +typedef struct { + S3C24X0_REG32 IICCON; + S3C24X0_REG32 IICSTAT; + S3C24X0_REG32 IICADD; + S3C24X0_REG32 IICDS; +} /*__attribute__((__packed__))*/ S3C24X0_I2C; + + +/* IIS (see manual chapter 21) */ +typedef struct { +#ifdef __BIG_ENDIAN + S3C24X0_REG16 res1; + S3C24X0_REG16 IISCON; + S3C24X0_REG16 res2; + S3C24X0_REG16 IISMOD; + S3C24X0_REG16 res3; + S3C24X0_REG16 IISPSR; + S3C24X0_REG16 res4; + S3C24X0_REG16 IISFCON; + S3C24X0_REG16 res5; + S3C24X0_REG16 IISFIFO; +#else /* little endian */ + S3C24X0_REG16 IISCON; + S3C24X0_REG16 res1; + S3C24X0_REG16 IISMOD; + S3C24X0_REG16 res2; + S3C24X0_REG16 IISPSR; + S3C24X0_REG16 res3; + S3C24X0_REG16 IISFCON; + S3C24X0_REG16 res4; + S3C24X0_REG16 IISFIFO; + S3C24X0_REG16 res5; +#endif +} /*__attribute__((__packed__))*/ S3C24X0_I2S; + + +/* I/O PORT (see manual chapter 9) */ +typedef struct { +#ifdef CONFIG_S3C2400 + S3C24X0_REG32 PACON; + S3C24X0_REG32 PADAT; + + S3C24X0_REG32 PBCON; + S3C24X0_REG32 PBDAT; + S3C24X0_REG32 PBUP; + + S3C24X0_REG32 PCCON; + S3C24X0_REG32 PCDAT; + S3C24X0_REG32 PCUP; + + S3C24X0_REG32 PDCON; + S3C24X0_REG32 PDDAT; + S3C24X0_REG32 PDUP; + + S3C24X0_REG32 PECON; + S3C24X0_REG32 PEDAT; + S3C24X0_REG32 PEUP; + + S3C24X0_REG32 PFCON; + S3C24X0_REG32 PFDAT; + S3C24X0_REG32 PFUP; + + S3C24X0_REG32 PGCON; + S3C24X0_REG32 PGDAT; + S3C24X0_REG32 PGUP; + + S3C24X0_REG32 OPENCR; + + S3C24X0_REG32 MISCCR; + S3C24X0_REG32 EXTINT; +#endif +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 GPACON; + S3C24X0_REG32 GPADAT; + S3C24X0_REG32 res1[2]; + S3C24X0_REG32 GPBCON; + S3C24X0_REG32 GPBDAT; + S3C24X0_REG32 GPBUP; + S3C24X0_REG32 res2; + S3C24X0_REG32 GPCCON; + S3C24X0_REG32 GPCDAT; + S3C24X0_REG32 GPCUP; + S3C24X0_REG32 res3; + S3C24X0_REG32 GPDCON; + S3C24X0_REG32 GPDDAT; + S3C24X0_REG32 GPDUP; + S3C24X0_REG32 res4; + S3C24X0_REG32 GPECON; + S3C24X0_REG32 GPEDAT; + S3C24X0_REG32 GPEUP; + S3C24X0_REG32 res5; + S3C24X0_REG32 GPFCON; + S3C24X0_REG32 GPFDAT; + S3C24X0_REG32 GPFUP; + S3C24X0_REG32 res6; + S3C24X0_REG32 GPGCON; + S3C24X0_REG32 GPGDAT; + S3C24X0_REG32 GPGUP; + S3C24X0_REG32 res7; + S3C24X0_REG32 GPHCON; + S3C24X0_REG32 GPHDAT; + S3C24X0_REG32 GPHUP; + S3C24X0_REG32 res8; + + S3C24X0_REG32 MISCCR; + S3C24X0_REG32 DCLKCON; + S3C24X0_REG32 EXTINT0; + S3C24X0_REG32 EXTINT1; + S3C24X0_REG32 EXTINT2; + S3C24X0_REG32 EINTFLT0; + S3C24X0_REG32 EINTFLT1; + S3C24X0_REG32 EINTFLT2; + S3C24X0_REG32 EINTFLT3; + S3C24X0_REG32 EINTMASK; + S3C24X0_REG32 EINTPEND; + S3C24X0_REG32 GSTATUS0; + S3C24X0_REG32 GSTATUS1; + S3C24X0_REG32 GSTATUS2; + S3C24X0_REG32 GSTATUS3; + S3C24X0_REG32 GSTATUS4; +#endif +} /*__attribute__((__packed__))*/ S3C24X0_GPIO; + + +/* RTC (see manual chapter 17) */ +typedef struct { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[67]; + S3C24X0_REG8 RTCCON; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 TICNT; + S3C24X0_REG8 res3[11]; + S3C24X0_REG8 RTCALM; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 ALMSEC; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 ALMMIN; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 ALMHOUR; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 ALMDATE; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 ALMMON; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 ALMYEAR; + S3C24X0_REG8 res10[3]; + S3C24X0_REG8 RTCRST; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 BCDSEC; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 BCDMIN; + S3C24X0_REG8 res13[3]; + S3C24X0_REG8 BCDHOUR; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 BCDDATE; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 BCDDAY; + S3C24X0_REG8 res16[3]; + S3C24X0_REG8 BCDMON; + S3C24X0_REG8 res17[3]; + S3C24X0_REG8 BCDYEAR; +#else /* little endian */ + S3C24X0_REG8 res0[64]; + S3C24X0_REG8 RTCCON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 TICNT; + S3C24X0_REG8 res2[11]; + S3C24X0_REG8 RTCALM; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 ALMSEC; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 ALMMIN; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 ALMHOUR; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 ALMDATE; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 ALMMON; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 ALMYEAR; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 RTCRST; + S3C24X0_REG8 res10[3]; + S3C24X0_REG8 BCDSEC; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 BCDMIN; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 BCDHOUR; + S3C24X0_REG8 res13[3]; + S3C24X0_REG8 BCDDATE; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 BCDDAY; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 BCDMON; + S3C24X0_REG8 res16[3]; + S3C24X0_REG8 BCDYEAR; + S3C24X0_REG8 res17[3]; +#endif +} /*__attribute__((__packed__))*/ S3C24X0_RTC; + + +/* ADC (see manual chapter 16) */ +typedef struct { + S3C24X0_REG32 ADCCON; + S3C24X0_REG32 ADCDAT; +} /*__attribute__((__packed__))*/ S3C2400_ADC; + + +/* ADC (see manual chapter 16) */ +typedef struct { + S3C24X0_REG32 ADCCON; + S3C24X0_REG32 ADCTSC; + S3C24X0_REG32 ADCDLY; + S3C24X0_REG32 ADCDAT0; + S3C24X0_REG32 ADCDAT1; +} /*__attribute__((__packed__))*/ S3C2410_ADC; + + +/* SPI (see manual chapter 22) */ +typedef struct { + S3C24X0_REG32 SPCON; + S3C24X0_REG32 SPSTA; + S3C24X0_REG32 SPPIN; + S3C24X0_REG32 SPPRE; + S3C24X0_REG32 SPTDAT; + S3C24X0_REG32 SPRDAT; + S3C24X0_REG32 res[2]; +} __attribute__((__packed__)) S3C24X0_SPI_CHANNEL; + +typedef struct { + S3C24X0_SPI_CHANNEL ch[S3C24X0_SPI_CHANNELS]; +} /*__attribute__((__packed__))*/ S3C24X0_SPI; + + +/* MMC INTERFACE (see S3C2400 manual chapter 19) */ +typedef struct { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 MMCON; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 MMCRR; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 MMFCON; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 MMSTA; + S3C24X0_REG16 res5; + S3C24X0_REG16 MMFSTA; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 MMPRE; + S3C24X0_REG16 res7; + S3C24X0_REG16 MMLEN; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 MMCR7; + S3C24X0_REG32 MMRSP[4]; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 MMCMD0; + S3C24X0_REG32 MMCMD1; + S3C24X0_REG16 res10; + S3C24X0_REG16 MMCR16; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 MMDAT; +#else + S3C24X0_REG8 MMCON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 MMCRR; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 MMFCON; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 MMSTA; + S3C24X0_REG8 res4[3]; + S3C24X0_REG16 MMFSTA; + S3C24X0_REG16 res5; + S3C24X0_REG8 MMPRE; + S3C24X0_REG8 res6[3]; + S3C24X0_REG16 MMLEN; + S3C24X0_REG16 res7; + S3C24X0_REG8 MMCR7; + S3C24X0_REG8 res8[3]; + S3C24X0_REG32 MMRSP[4]; + S3C24X0_REG8 MMCMD0; + S3C24X0_REG8 res9[3]; + S3C24X0_REG32 MMCMD1; + S3C24X0_REG16 MMCR16; + S3C24X0_REG16 res10; + S3C24X0_REG8 MMDAT; + S3C24X0_REG8 res11[3]; +#endif +} /*__attribute__((__packed__))*/ S3C2400_MMC; + + +/* SD INTERFACE (see S3C2410 manual chapter 19) */ +typedef struct { + S3C24X0_REG32 SDICON; + S3C24X0_REG32 SDIPRE; + S3C24X0_REG32 SDICARG; + S3C24X0_REG32 SDICCON; + S3C24X0_REG32 SDICSTA; + S3C24X0_REG32 SDIRSP0; + S3C24X0_REG32 SDIRSP1; + S3C24X0_REG32 SDIRSP2; + S3C24X0_REG32 SDIRSP3; + S3C24X0_REG32 SDIDTIMER; + S3C24X0_REG32 SDIBSIZE; + S3C24X0_REG32 SDIDCON; + S3C24X0_REG32 SDIDCNT; + S3C24X0_REG32 SDIDSTA; + S3C24X0_REG32 SDIFSTA; +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res[3]; + S3C24X0_REG8 SDIDAT; +#else + S3C24X0_REG8 SDIDAT; + S3C24X0_REG8 res[3]; +#endif + S3C24X0_REG32 SDIIMSK; +} /*__attribute__((__packed__))*/ S3C2410_SDI; + + +#if 0 +/* Memory control */ +#define rBWSCON (*(volatile unsigned *)0x48000000) +#define rBANKCON0 (*(volatile unsigned *)0x48000004) +#define rBANKCON1 (*(volatile unsigned *)0x48000008) +#define rBANKCON2 (*(volatile unsigned *)0x4800000C) +#define rBANKCON3 (*(volatile unsigned *)0x48000010) +#define rBANKCON4 (*(volatile unsigned *)0x48000014) +#define rBANKCON5 (*(volatile unsigned *)0x48000018) +#define rBANKCON6 (*(volatile unsigned *)0x4800001C) +#define rBANKCON7 (*(volatile unsigned *)0x48000020) +#define rREFRESH (*(volatile unsigned *)0x48000024) +#define rBANKSIZE (*(volatile unsigned *)0x48000028) +#define rMRSRB6 (*(volatile unsigned *)0x4800002C) +#define rMRSRB7 (*(volatile unsigned *)0x48000030) + + +/* USB HOST */ +#define rHcRevision (*(volatile unsigned *)0x49000000) +#define rHcControl (*(volatile unsigned *)0x49000004) +#define rHcCommonStatus (*(volatile unsigned *)0x49000008) +#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C) +#define rHcInterruptEnable (*(volatile unsigned *)0x49000010) +#define rHcInterruptDisable (*(volatile unsigned *)0x49000014) +#define rHcHCCA (*(volatile unsigned *)0x49000018) +#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C) +#define rHcControlHeadED (*(volatile unsigned *)0x49000020) +#define rHcControlCurrentED (*(volatile unsigned *)0x49000024) +#define rHcBulkHeadED (*(volatile unsigned *)0x49000028) +#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C) +#define rHcDoneHead (*(volatile unsigned *)0x49000030) +#define rHcRmInterval (*(volatile unsigned *)0x49000034) +#define rHcFmRemaining (*(volatile unsigned *)0x49000038) +#define rHcFmNumber (*(volatile unsigned *)0x4900003C) +#define rHcPeriodicStart (*(volatile unsigned *)0x49000040) +#define rHcLSThreshold (*(volatile unsigned *)0x49000044) +#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048) +#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C) +#define rHcRhStatus (*(volatile unsigned *)0x49000050) +#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054) +#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058) + + +/* INTERRUPT */ +#define rSRCPND (*(volatile unsigned *)0x4A000000) +#define rINTMOD (*(volatile unsigned *)0x4A000004) +#define rINTMSK (*(volatile unsigned *)0x4A000008) +#define rPRIORITY (*(volatile unsigned *)0x4A00000C) +#define rINTPND (*(volatile unsigned *)0x4A000010) +#define rINTOFFSET (*(volatile unsigned *)0x4A000014) +#define rSUBSRCPND (*(volatile unsigned *)0x4A000018) +#define rINTSUBMSK (*(volatile unsigned *)0x4A00001C) + + +/* DMA */ +#define rDISRC0 (*(volatile unsigned *)0x4B000000) +#define rDISRCC0 (*(volatile unsigned *)0x4B000004) +#define rDIDST0 (*(volatile unsigned *)0x4B000008) +#define rDIDSTC0 (*(volatile unsigned *)0x4B00000C) +#define rDCON0 (*(volatile unsigned *)0x4B000010) +#define rDSTAT0 (*(volatile unsigned *)0x4B000014) +#define rDCSRC0 (*(volatile unsigned *)0x4B000018) +#define rDCDST0 (*(volatile unsigned *)0x4B00001C) +#define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020) +#define rDISRC1 (*(volatile unsigned *)0x4B000040) +#define rDISRCC1 (*(volatile unsigned *)0x4B000044) +#define rDIDST1 (*(volatile unsigned *)0x4B000048) +#define rDIDSTC1 (*(volatile unsigned *)0x4B00004C) +#define rDCON1 (*(volatile unsigned *)0x4B000050) +#define rDSTAT1 (*(volatile unsigned *)0x4B000054) +#define rDCSRC1 (*(volatile unsigned *)0x4B000058) +#define rDCDST1 (*(volatile unsigned *)0x4B00005C) +#define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060) +#define rDISRC2 (*(volatile unsigned *)0x4B000080) +#define rDISRCC2 (*(volatile unsigned *)0x4B000084) +#define rDIDST2 (*(volatile unsigned *)0x4B000088) +#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C) +#define rDCON2 (*(volatile unsigned *)0x4B000090) +#define rDSTAT2 (*(volatile unsigned *)0x4B000094) +#define rDCSRC2 (*(volatile unsigned *)0x4B000098) +#define rDCDST2 (*(volatile unsigned *)0x4B00009C) +#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0) +#define rDISRC3 (*(volatile unsigned *)0x4B0000C0) +#define rDISRCC3 (*(volatile unsigned *)0x4B0000C4) +#define rDIDST3 (*(volatile unsigned *)0x4B0000C8) +#define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC) +#define rDCON3 (*(volatile unsigned *)0x4B0000D0) +#define rDSTAT3 (*(volatile unsigned *)0x4B0000D4) +#define rDCSRC3 (*(volatile unsigned *)0x4B0000D8) +#define rDCDST3 (*(volatile unsigned *)0x4B0000DC) +#define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0) + + +/* CLOCK & POWER MANAGEMENT */ +#define rLOCKTIME (*(volatile unsigned *)0x4C000000) +#define rMPLLCON (*(volatile unsigned *)0x4C000004) +#define rUPLLCON (*(volatile unsigned *)0x4C000008) +#define rCLKCON (*(volatile unsigned *)0x4C00000C) +#define rCLKSLOW (*(volatile unsigned *)0x4C000010) +#define rCLKDIVN (*(volatile unsigned *)0x4C000014) + + +/* LCD CONTROLLER */ +#define rLCDCON1 (*(volatile unsigned *)0x4D000000) +#define rLCDCON2 (*(volatile unsigned *)0x4D000004) +#define rLCDCON3 (*(volatile unsigned *)0x4D000008) +#define rLCDCON4 (*(volatile unsigned *)0x4D00000C) +#define rLCDCON5 (*(volatile unsigned *)0x4D000010) +#define rLCDSADDR1 (*(volatile unsigned *)0x4D000014) +#define rLCDSADDR2 (*(volatile unsigned *)0x4D000018) +#define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C) +#define rREDLUT (*(volatile unsigned *)0x4D000020) +#define rGREENLUT (*(volatile unsigned *)0x4D000024) +#define rBLUELUT (*(volatile unsigned *)0x4D000028) +#define rDITHMODE (*(volatile unsigned *)0x4D00004C) +#define rTPAL (*(volatile unsigned *)0x4D000050) +#define rLCDINTPND (*(volatile unsigned *)0x4D000054) +#define rLCDSRCPND (*(volatile unsigned *)0x4D000058) +#define rLCDINTMSK (*(volatile unsigned *)0x4D00005C) + + +/* NAND FLASH */ +#define rNFCONF (*(volatile unsigned *)0x4E000000) +#define rNFCMD (*(volatile unsigned *)0x4E000004) +#define rNFADDR (*(volatile unsigned *)0x4E000008) +#define rNFDATA (*(volatile unsigned *)0x4E00000C) +#define rNFSTAT (*(volatile unsigned *)0x4E000010) +#define rNFECC (*(volatile unsigned *)0x4E000014) + + +/* UART */ +#define rULCON0 (*(volatile unsigned *)0x50000000) +#define rUCON0 (*(volatile unsigned *)0x50000004) +#define rUFCON0 (*(volatile unsigned *)0x50000008) +#define rUMCON0 (*(volatile unsigned *)0x5000000C) +#define rUTRSTAT0 (*(volatile unsigned *)0x50000010) +#define rUERSTAT0 (*(volatile unsigned *)0x50000014) +#define rUFSTAT0 (*(volatile unsigned *)0x50000018) +#define rUMSTAT0 (*(volatile unsigned *)0x5000001C) +#define rUBRDIV0 (*(volatile unsigned *)0x50000028) + +#define rULCON1 (*(volatile unsigned *)0x50004000) +#define rUCON1 (*(volatile unsigned *)0x50004004) +#define rUFCON1 (*(volatile unsigned *)0x50004008) +#define rUMCON1 (*(volatile unsigned *)0x5000400C) +#define rUTRSTAT1 (*(volatile unsigned *)0x50004010) +#define rUERSTAT1 (*(volatile unsigned *)0x50004014) +#define rUFSTAT1 (*(volatile unsigned *)0x50004018) +#define rUMSTAT1 (*(volatile unsigned *)0x5000401C) +#define rUBRDIV1 (*(volatile unsigned *)0x50004028) + +#define rULCON2 (*(volatile unsigned *)0x50008000) +#define rUCON2 (*(volatile unsigned *)0x50008004) +#define rUFCON2 (*(volatile unsigned *)0x50008008) +#define rUTRSTAT2 (*(volatile unsigned *)0x50008010) +#define rUERSTAT2 (*(volatile unsigned *)0x50008014) +#define rUFSTAT2 (*(volatile unsigned *)0x50008018) +#define rUBRDIV2 (*(volatile unsigned *)0x50008028) + +#ifdef __BIG_ENDIAN +#define rUTXH0 (*(volatile unsigned char *)0x50000023) +#define rURXH0 (*(volatile unsigned char *)0x50000027) +#define rUTXH1 (*(volatile unsigned char *)0x50004023) +#define rURXH1 (*(volatile unsigned char *)0x50004027) +#define rUTXH2 (*(volatile unsigned char *)0x50008023) +#define rURXH2 (*(volatile unsigned char *)0x50008027) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004027) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008027) + +#define UTXH0 (0x50000020+3) /* byte_access address by DMA */ +#define URXH0 (0x50000024+3) +#define UTXH1 (0x50004020+3) +#define URXH1 (0x50004024+3) +#define UTXH2 (0x50008020+3) +#define URXH2 (0x50008024+3) + +#else /* Little Endian */ +#define rUTXH0 (*(volatile unsigned char *)0x50000020) +#define rURXH0 (*(volatile unsigned char *)0x50000024) +#define rUTXH1 (*(volatile unsigned char *)0x50004020) +#define rURXH1 (*(volatile unsigned char *)0x50004024) +#define rUTXH2 (*(volatile unsigned char *)0x50008020) +#define rURXH2 (*(volatile unsigned char *)0x50008024) + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004024) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008024) + +#define UTXH0 (0x50000020) /* byte_access address by DMA */ +#define URXH0 (0x50000024) +#define UTXH1 (0x50004020) +#define URXH1 (0x50004024) +#define UTXH2 (0x50008020) +#define URXH2 (0x50008024) +#endif + + +/* PWM TIMER */ +#define rTCFG0 (*(volatile unsigned *)0x51000000) +#define rTCFG1 (*(volatile unsigned *)0x51000004) +#define rTCON (*(volatile unsigned *)0x51000008) +#define rTCNTB0 (*(volatile unsigned *)0x5100000C) +#define rTCMPB0 (*(volatile unsigned *)0x51000010) +#define rTCNTO0 (*(volatile unsigned *)0x51000014) +#define rTCNTB1 (*(volatile unsigned *)0x51000018) +#define rTCMPB1 (*(volatile unsigned *)0x5100001C) +#define rTCNTO1 (*(volatile unsigned *)0x51000020) +#define rTCNTB2 (*(volatile unsigned *)0x51000024) +#define rTCMPB2 (*(volatile unsigned *)0x51000028) +#define rTCNTO2 (*(volatile unsigned *)0x5100002C) +#define rTCNTB3 (*(volatile unsigned *)0x51000030) +#define rTCMPB3 (*(volatile unsigned *)0x51000034) +#define rTCNTO3 (*(volatile unsigned *)0x51000038) +#define rTCNTB4 (*(volatile unsigned *)0x5100003C) +#define rTCNTO4 (*(volatile unsigned *)0x51000040) + + +/* USB DEVICE */ +#ifdef __BIG_ENDIAN +#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) +#define rPWR_REG (*(volatile unsigned char *)0x52000147) +#define rEP_INT_REG (*(volatile unsigned char *)0x5200014B) +#define rUSB_INT_REG (*(volatile unsigned char *)0x5200015B) +#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015F) +#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016F) +#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) +#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) +#define rINDEX_REG (*(volatile unsigned char *)0x5200017B) +#define rMAXP_REG (*(volatile unsigned char *)0x52000183) +#define rEP0_CSR (*(volatile unsigned char *)0x52000187) +#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187) +#define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018B) +#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193) +#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197) +#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019B) +#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019F) +#define rEP0_FIFO (*(volatile unsigned char *)0x520001C3) +#define rEP1_FIFO (*(volatile unsigned char *)0x520001C7) +#define rEP2_FIFO (*(volatile unsigned char *)0x520001CB) +#define rEP3_FIFO (*(volatile unsigned char *)0x520001CF) +#define rEP4_FIFO (*(volatile unsigned char *)0x520001D3) +#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203) +#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) +#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020B) +#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020F) +#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000213) +#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000217) +#define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021B) +#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021F) +#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) +#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000227) +#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x5200022B) +#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022F) +#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243) +#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) +#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024B) +#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024F) +#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000253) +#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000257) +#define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025B) +#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025F) +#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) +#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000267) +#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x5200026B) +#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026F) +#else /* little endian */ +#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) +#define rPWR_REG (*(volatile unsigned char *)0x52000144) +#define rEP_INT_REG (*(volatile unsigned char *)0x52000148) +#define rUSB_INT_REG (*(volatile unsigned char *)0x52000158) +#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015C) +#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016C) +#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) +#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) +#define rINDEX_REG (*(volatile unsigned char *)0x52000178) +#define rMAXP_REG (*(volatile unsigned char *)0x52000180) +#define rEP0_CSR (*(volatile unsigned char *)0x52000184) +#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184) +#define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188) +#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190) +#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194) +#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) +#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019C) +#define rEP0_FIFO (*(volatile unsigned char *)0x520001C0) +#define rEP1_FIFO (*(volatile unsigned char *)0x520001C4) +#define rEP2_FIFO (*(volatile unsigned char *)0x520001C8) +#define rEP3_FIFO (*(volatile unsigned char *)0x520001CC) +#define rEP4_FIFO (*(volatile unsigned char *)0x520001D0) +#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200) +#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) +#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) +#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020C) +#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000210) +#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000214) +#define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218) +#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021C) +#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) +#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000224) +#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x52000228) +#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022C) +#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240) +#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) +#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) +#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024C) +#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000250) +#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000254) +#define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258) +#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025C) +#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) +#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000264) +#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x52000268) +#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026C) +#endif /* __BIG_ENDIAN */ + + +/* WATCH DOG TIMER */ +#define rWTCON (*(volatile unsigned *)0x53000000) +#define rWTDAT (*(volatile unsigned *)0x53000004) +#define rWTCNT (*(volatile unsigned *)0x53000008) + + +/* IIC */ +#define rIICCON (*(volatile unsigned *)0x54000000) +#define rIICSTAT (*(volatile unsigned *)0x54000004) +#define rIICADD (*(volatile unsigned *)0x54000008) +#define rIICDS (*(volatile unsigned *)0x5400000C) + + +/* IIS */ +#define rIISCON (*(volatile unsigned *)0x55000000) +#define rIISMOD (*(volatile unsigned *)0x55000004) +#define rIISPSR (*(volatile unsigned *)0x55000008) +#define rIISFCON (*(volatile unsigned *)0x5500000C) + +#ifdef __BIG_ENDIAN +#define IISFIF ((volatile unsigned short *)0x55000012) +#else /* little endian */ +#define IISFIF ((volatile unsigned short *)0x55000010) +#endif + + +/* I/O PORT */ +#define rGPACON (*(volatile unsigned *)0x56000000) +#define rGPADAT (*(volatile unsigned *)0x56000004) + +#define rGPBCON (*(volatile unsigned *)0x56000010) +#define rGPBDAT (*(volatile unsigned *)0x56000014) +#define rGPBUP (*(volatile unsigned *)0x56000018) + +#define rGPCCON (*(volatile unsigned *)0x56000020) +#define rGPCDAT (*(volatile unsigned *)0x56000024) +#define rGPCUP (*(volatile unsigned *)0x56000028) + +#define rGPDCON (*(volatile unsigned *)0x56000030) +#define rGPDDAT (*(volatile unsigned *)0x56000034) +#define rGPDUP (*(volatile unsigned *)0x56000038) + +#define rGPECON (*(volatile unsigned *)0x56000040) +#define rGPEDAT (*(volatile unsigned *)0x56000044) +#define rGPEUP (*(volatile unsigned *)0x56000048) + +#define rGPFCON (*(volatile unsigned *)0x56000050) +#define rGPFDAT (*(volatile unsigned *)0x56000054) +#define rGPFUP (*(volatile unsigned *)0x56000058) + +#define rGPGCON (*(volatile unsigned *)0x56000060) +#define rGPGDAT (*(volatile unsigned *)0x56000064) +#define rGPGUP (*(volatile unsigned *)0x56000068) + +#define rGPHCON (*(volatile unsigned *)0x56000070) +#define rGPHDAT (*(volatile unsigned *)0x56000074) +#define rGPHUP (*(volatile unsigned *)0x56000078) + +#define rMISCCR (*(volatile unsigned *)0x56000080) +#define rDCLKCON (*(volatile unsigned *)0x56000084) +#define rEXTINT0 (*(volatile unsigned *)0x56000088) +#define rEXTINT1 (*(volatile unsigned *)0x5600008C) +#define rEXTINT2 (*(volatile unsigned *)0x56000090) +#define rEINTFLT0 (*(volatile unsigned *)0x56000094) +#define rEINTFLT1 (*(volatile unsigned *)0x56000098) +#define rEINTFLT2 (*(volatile unsigned *)0x5600009C) +#define rEINTFLT3 (*(volatile unsigned *)0x560000A0) +#define rEINTMASK (*(volatile unsigned *)0x560000A4) +#define rEINTPEND (*(volatile unsigned *)0x560000A8) +#define rGSTATUS0 (*(volatile unsigned *)0x560000AC) +#define rGSTATUS1 (*(volatile unsigned *)0x560000B0) + + +/* RTC */ +#ifdef __BIG_ENDIAN +#define rRTCCON (*(volatile unsigned char *)0x57000043) +#define rTICNT (*(volatile unsigned char *)0x57000047) +#define rRTCALM (*(volatile unsigned char *)0x57000053) +#define rALMSEC (*(volatile unsigned char *)0x57000057) +#define rALMMIN (*(volatile unsigned char *)0x5700005B) +#define rALMHOUR (*(volatile unsigned char *)0x5700005F) +#define rALMDATE (*(volatile unsigned char *)0x57000063) +#define rALMMON (*(volatile unsigned char *)0x57000067) +#define rALMYEAR (*(volatile unsigned char *)0x5700006B) +#define rRTCRST (*(volatile unsigned char *)0x5700006F) +#define rBCDSEC (*(volatile unsigned char *)0x57000073) +#define rBCDMIN (*(volatile unsigned char *)0x57000077) +#define rBCDHOUR (*(volatile unsigned char *)0x5700007B) +#define rBCDDATE (*(volatile unsigned char *)0x5700007F) +#define rBCDDAY (*(volatile unsigned char *)0x57000083) +#define rBCDMON (*(volatile unsigned char *)0x57000087) +#define rBCDYEAR (*(volatile unsigned char *)0x5700008B) +#else /* little endian */ +#define rRTCCON (*(volatile unsigned char *)0x57000040) +#define rTICNT (*(volatile unsigned char *)0x57000044) +#define rRTCALM (*(volatile unsigned char *)0x57000050) +#define rALMSEC (*(volatile unsigned char *)0x57000054) +#define rALMMIN (*(volatile unsigned char *)0x57000058) +#define rALMHOUR (*(volatile unsigned char *)0x5700005C) +#define rALMDATE (*(volatile unsigned char *)0x57000060) +#define rALMMON (*(volatile unsigned char *)0x57000064) +#define rALMYEAR (*(volatile unsigned char *)0x57000068) +#define rRTCRST (*(volatile unsigned char *)0x5700006C) +#define rBCDSEC (*(volatile unsigned char *)0x57000070) +#define rBCDMIN (*(volatile unsigned char *)0x57000074) +#define rBCDHOUR (*(volatile unsigned char *)0x57000078) +#define rBCDDATE (*(volatile unsigned char *)0x5700007C) +#define rBCDDAY (*(volatile unsigned char *)0x57000080) +#define rBCDMON (*(volatile unsigned char *)0x57000084) +#define rBCDYEAR (*(volatile unsigned char *)0x57000088) +#endif + + +/* ADC */ +#define rADCCON (*(volatile unsigned *)0x58000000) +#define rADCTSC (*(volatile unsigned *)0x58000004) +#define rADCDLY (*(volatile unsigned *)0x58000008) +#define rADCDAT0 (*(volatile unsigned *)0x5800000C) +#define rADCDAT1 (*(volatile unsigned *)0x58000010) + + +/* SPI */ +#define rSPCON0 (*(volatile unsigned *)0x59000000) +#define rSPSTA0 (*(volatile unsigned *)0x59000004) +#define rSPPIN0 (*(volatile unsigned *)0x59000008) +#define rSPPRE0 (*(volatile unsigned *)0x5900000C) +#define rSPTDAT0 (*(volatile unsigned *)0x59000010) +#define rSPRDAT0 (*(volatile unsigned *)0x59000014) +#define rSPCON1 (*(volatile unsigned *)0x59000020) +#define rSPSTA1 (*(volatile unsigned *)0x59000024) +#define rSPPIN1 (*(volatile unsigned *)0x59000028) +#define rSPPRE1 (*(volatile unsigned *)0x5900002C) +#define rSPTDAT1 (*(volatile unsigned *)0x59000030) +#define rSPRDAT1 (*(volatile unsigned *)0x59000034) + + +/* SD INTERFACE */ +#define rSDICON (*(volatile unsigned *)0x5A000000) +#define rSDIPRE (*(volatile unsigned *)0x5A000004) +#define rSDICmdArg (*(volatile unsigned *)0x5A000008) +#define rSDICmdCon (*(volatile unsigned *)0x5A00000C) +#define rSDICmdSta (*(volatile unsigned *)0x5A000010) +#define rSDIRSP0 (*(volatile unsigned *)0x5A000014) +#define rSDIRSP1 (*(volatile unsigned *)0x5A000018) +#define rSDIRSP2 (*(volatile unsigned *)0x5A00001C) +#define rSDIRSP3 (*(volatile unsigned *)0x5A000020) +#define rSDIDTimer (*(volatile unsigned *)0x5A000024) +#define rSDIBSize (*(volatile unsigned *)0x5A000028) +#define rSDIDatCon (*(volatile unsigned *)0x5A00002C) +#define rSDIDatCnt (*(volatile unsigned *)0x5A000030) +#define rSDIDatSta (*(volatile unsigned *)0x5A000034) +#define rSDIFSTA (*(volatile unsigned *)0x5A000038) +#ifdef __BIG_ENDIAN +#define rSDIDAT (*(volatile unsigned char *)0x5A00003F) +#else +#define rSDIDAT (*(volatile unsigned char *)0x5A00003C) +#endif +#define rSDIIntMsk (*(volatile unsigned *)0x5A000040) + +#endif + +#endif /*__S3C24X0_H__*/ diff --git a/include/s_record.h b/include/s_record.h new file mode 100644 index 0000000..07806d5 --- /dev/null +++ b/include/s_record.h @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*-------------------------------------------------------------------------- + * + * Motorola S-Record Format: + * + * Motorola S-Records are an industry-standard format for + * transmitting binary files to target systems and PROM + * programmers. LSI Logic have extended this standard to include + * an S4-record containing an address and a symbol. + * + * The extended S-record standard is as follows: + * + * S
+ * S4
, + * + * Where: + * + * type + * is the record type. Where: + * + * 0 starting record (optional) + * 1 data record with 16-bit address + * 2 data record with 24-bit address + * 3 data record with 32-bit address + * 4 symbol record (LSI extension) + * 5 number of data records in preceeding block + * 6 unused + * 7 ending record for S3 records + * 8 ending record for S2 records + * 9 ending record for S1 records + * + * length + * is two hex characters. This defines the length of the + * record in bytes (not characters). It includes the address + * field, the data field, and the checksum field. + * + * address + * is 4, 6, or 8 characters. Corresponding to a 16-, 24-, or + * 32-bit address. The address field for S4 records is + * always 32 bits. + * + * data + * + * Are the data bytes. Each pair of hex characters represent + * one byte in memory. + * + * name + * Is the symbol name. The symbol is terminated by a ','. + * + * checksum + * Is the one's complement of the 8-bit checksum. + * + * Example + * + * S0030000FC + * . + * . + * S325000004403C0880018D08DD900000000011000026000000003C0880012508DC50C50000B401 + * S32500000460C50100B8C50200BCC50300C0C50400C4C50500C8C50600CCC50700D0C50800D4FA + * S32500000480C50900D8C50A00DCC50B00E0C50C00E4C50D00E8C50E00ECC50F00F0C51000F49A + * S325000004A0C51100F8C51200FCC5130100C5140104C5150108C516010CC5170110C518011434 + * . + * . + * S70500000000FA + * + * The S0 record starts the file. The S3 records contain the + * data. The S7 record contains the entry address and terminates + * the download. + * + *-------------------------------------------------------------------------- + */ + +#define SREC_START 0 /* Start Record (module name) */ +#define SREC_DATA2 1 /* Data Record with 2 byte address */ +#define SREC_DATA3 2 /* Data Record with 3 byte address */ +#define SREC_DATA4 3 /* Data Record with 4 byte address */ +#define SREC_COUNT 5 /* Count Record (previously transmitted) */ +#define SREC_END4 7 /* End Record with 4 byte start address */ +#define SREC_END3 8 /* End Record with 3 byte start address */ +#define SREC_END2 9 /* End Record with 2 byte start address */ +#define SREC_EMPTY 10 /* Empty Record without any data */ + +#define SREC_REC_OK SREC_EMPTY /* last code without error condition */ + +#define SREC_E_BADTYPE -1 /* no valid S-Record */ +#define SREC_E_NOSREC -2 /* line format differs from s-record */ +#define SREC_E_BADCHKS -3 /* checksum error in an s-record line */ + +#define SREC_MAXRECLEN (512 + 4) /* max ASCII record length */ +#define SREC_MAXBINLEN 255 /* resulting binary length */ + +int srec_decode (char *input, int *count, ulong *addr, char *data); diff --git a/include/sa1100.h b/include/sa1100.h new file mode 100644 index 0000000..e69de29 diff --git a/include/scsi.h b/include/scsi.h new file mode 100644 index 0000000..2be4d40 --- /dev/null +++ b/include/scsi.h @@ -0,0 +1,208 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + #ifndef _SCSI_H + #define _SCSI_H + +typedef struct SCSI_cmd_block{ + unsigned char cmd[16]; /* command */ + unsigned char sense_buf[64]; /* for request sense */ + unsigned char status; /* SCSI Status */ + unsigned char target; /* Target ID */ + unsigned char lun; /* Target LUN */ + unsigned char cmdlen; /* command len */ + unsigned long datalen; /* Total data length */ + unsigned char * pdata; /* pointer to data */ + unsigned char msgout[12]; /* Messge out buffer (NOT USED) */ + unsigned char msgin[12]; /* Message in buffer */ + unsigned char sensecmdlen; /* Sense command len */ + unsigned long sensedatalen; /* Sense data len */ + unsigned char sensecmd[6]; /* Sense command */ + unsigned long contr_stat; /* Controller Status */ + unsigned long trans_bytes; /* tranfered bytes */ + + unsigned int priv; +}ccb; + +/*----------------------------------------------------------- +** +** SCSI constants. +** +**----------------------------------------------------------- +*/ + +/* +** Messages +*/ + +#define M_COMPLETE (0x00) +#define M_EXTENDED (0x01) +#define M_SAVE_DP (0x02) +#define M_RESTORE_DP (0x03) +#define M_DISCONNECT (0x04) +#define M_ID_ERROR (0x05) +#define M_ABORT (0x06) +#define M_REJECT (0x07) +#define M_NOOP (0x08) +#define M_PARITY (0x09) +#define M_LCOMPLETE (0x0a) +#define M_FCOMPLETE (0x0b) +#define M_RESET (0x0c) +#define M_ABORT_TAG (0x0d) +#define M_CLEAR_QUEUE (0x0e) +#define M_INIT_REC (0x0f) +#define M_REL_REC (0x10) +#define M_TERMINATE (0x11) +#define M_SIMPLE_TAG (0x20) +#define M_HEAD_TAG (0x21) +#define M_ORDERED_TAG (0x22) +#define M_IGN_RESIDUE (0x23) +#define M_IDENTIFY (0x80) + +#define M_X_MODIFY_DP (0x00) +#define M_X_SYNC_REQ (0x01) +#define M_X_WIDE_REQ (0x03) +#define M_X_PPR_REQ (0x04) + + +/* +** Status +*/ + +#define S_GOOD (0x00) +#define S_CHECK_COND (0x02) +#define S_COND_MET (0x04) +#define S_BUSY (0x08) +#define S_INT (0x10) +#define S_INT_COND_MET (0x14) +#define S_CONFLICT (0x18) +#define S_TERMINATED (0x20) +#define S_QUEUE_FULL (0x28) +#define S_ILLEGAL (0xff) +#define S_SENSE (0x80) + +/* + * Sense_keys + */ + +#define SENSE_NO_SENSE 0x0 +#define SENSE_RECOVERED_ERROR 0x1 +#define SENSE_NOT_READY 0x2 +#define SENSE_MEDIUM_ERROR 0x3 +#define SENSE_HARDWARE_ERROR 0x4 +#define SENSE_ILLEGAL_REQUEST 0x5 +#define SENSE_UNIT_ATTENTION 0x6 +#define SENSE_DATA_PROTECT 0x7 +#define SENSE_BLANK_CHECK 0x8 +#define SENSE_VENDOR_SPECIFIC 0x9 +#define SENSE_COPY_ABORTED 0xA +#define SENSE_ABORTED_COMMAND 0xB +#define SENSE_VOLUME_OVERFLOW 0xD +#define SENSE_MISCOMPARE 0xE + + +#define SCSI_CHANGE_DEF 0x40 /* Change Definition (Optional) */ +#define SCSI_COMPARE 0x39 /* Compare (O) */ +#define SCSI_COPY 0x18 /* Copy (O) */ +#define SCSI_COP_VERIFY 0x3A /* Copy and Verify (O) */ +#define SCSI_INQUIRY 0x12 /* Inquiry (MANDATORY) */ +#define SCSI_LOG_SELECT 0x4C /* Log Select (O) */ +#define SCSI_LOG_SENSE 0x4D /* Log Sense (O) */ +#define SCSI_MODE_SEL6 0x15 /* Mode Select 6-byte (Device Specific) */ +#define SCSI_MODE_SEL10 0x55 /* Mode Select 10-byte (Device Specific) */ +#define SCSI_MODE_SEN6 0x1A /* Mode Sense 6-byte (Device Specific) */ +#define SCSI_MODE_SEN10 0x5A /* Mode Sense 10-byte (Device Specific) */ +#define SCSI_READ_BUFF 0x3C /* Read Buffer (O) */ +#define SCSI_REQ_SENSE 0x03 /* Request Sense (MANDATORY) */ +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostic (O) */ +#define SCSI_TST_U_RDY 0x00 /* Test Unit Ready (MANDATORY) */ +#define SCSI_WRITE_BUFF 0x3B /* Write Buffer (O) */ +/*************************************************************************** + * %%% Commands Unique to Direct Access Devices %%% + ***************************************************************************/ +#define SCSI_COMPARE 0x39 /* Compare (O) */ +#define SCSI_FORMAT 0x04 /* Format Unit (MANDATORY) */ +#define SCSI_LCK_UN_CAC 0x36 /* Lock Unlock Cache (O) */ +#define SCSI_PREFETCH 0x34 /* Prefetch (O) */ +#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */ +#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */ +#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */ +#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */ +#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */ +#define SCSI_READ_LONG 0x3E /* Read Long (O) */ +#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */ +#define SCSI_RCV_DIAG 0x1C /* Receive Diagnostic Results (O) */ +#define SCSI_RELEASE 0x17 /* Release Unit (MANDATORY) */ +#define SCSI_REZERO 0x01 /* Rezero Unit (O) */ +#define SCSI_SRCH_DAT_E 0x31 /* Search Data Equal (O) */ +#define SCSI_SRCH_DAT_H 0x30 /* Search Data High (O) */ +#define SCSI_SRCH_DAT_L 0x32 /* Search Data Low (O) */ +#define SCSI_SEEK6 0x0B /* Seek 6-Byte (O) */ +#define SCSI_SEEK10 0x2B /* Seek 10-Byte (O) */ +#define SCSI_SEND_DIAG 0x1D /* Send Diagnostics (MANDATORY) */ +#define SCSI_SET_LIMIT 0x33 /* Set Limits (O) */ +#define SCSI_START_STP 0x1B /* Start/Stop Unit (O) */ +#define SCSI_SYNC_CACHE 0x35 /* Synchronize Cache (O) */ +#define SCSI_VERIFY 0x2F /* Verify (O) */ +#define SCSI_WRITE6 0x0A /* Write 6-Byte (MANDATORY) */ +#define SCSI_WRITE10 0x2A /* Write 10-Byte (MANDATORY) */ +#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */ +#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */ +#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */ + + +/**************************************************************************** + * decleration of functions which have to reside in the LowLevel Part Driver + */ + +void scsi_print_error(ccb *pccb); +int scsi_exec(ccb *pccb); +void scsi_bus_reset(void); +void scsi_low_level_init(int busdevfunc); + + +/*************************************************************************** + * functions residing inside cmd_scsi.c + */ +void scsi_init(void); + + +#define SCSI_IDENTIFY 0xC0 /* not used */ + +/* Hardware errors */ +#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */ +#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */ +#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */ +#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */ + +#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */ + + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#endif /* _SCSI_H */ diff --git a/include/sed13806.h b/include/sed13806.h new file mode 100644 index 0000000..216e788 --- /dev/null +++ b/include/sed13806.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* Video support for Epson SED13806 chipset */ + + +#ifndef _SED13806_H_ +#define _SED13806_H_ + + +/* General definitions */ +#define FRAME_BUFFER_OFFSET 0x200000 /* Frame buffer offset */ +#define TOTAL_SPACE_SIZE 0x400000 + +#define DEFAULT_VIDEO_MEMORY_SIZE 0x140000 /* Video Memory Size */ + +#define HWCURSORSIZE 1024 /* Size of memory reserved + for HW cursor*/ + +/* Offset of chipset registers */ +#define BLT_CTRL0 (0x0100) +#define BLT_CTRL1 (0x0101) +#define BLT_ROP (0x0102) +#define BLT_OP (0x0103) +#define BLT_SRC_ADDR0 (0x0104) +#define BLT_SRC_ADDR1 (0x0105) +#define BLT_SRC_ADDR2 (0x0106) +#define BLT_DST_ADDR0 (0x0108) +#define BLT_DST_ADDR1 (0x0109) +#define BLT_DST_ADDR2 (0x010A) +#define BLT_MEM_OFF0 (0x010C) +#define BLT_MEM_OFF1 (0x010D) +#define BLT_WIDTH0 (0x0110) +#define BLT_WIDTH1 (0x0111) +#define BLT_HEIGHT0 (0x0112) +#define BLT_HEIGHT1 (0x0113) +#define BLT_BGCOLOR0 (0x0114) +#define BLT_BGCOLOR1 (0x0115) +#define BLT_FGCOLOR0 (0x0118) +#define BLT_FGCOLOR1 (0x0119) + +#define BLT_REG (0x100000) + +/* Lookup table registers */ +#define REG_LUT_ADDR 0x1e2 +#define REG_LUT_DATA 0x1e4 + +/* Cursor/Ink registers */ +#define LCD_CURSOR_CNTL (0x0070) +#define LCD_CURSOR_START (0x0071) +#define LCD_CURSOR_XL (0x0072) +#define LCD_CURSOR_XM (0x0073) +#define LCD_CURSOR_YL (0x0074) +#define LCD_CURSOR_YM (0x0075) +#define LCD_CURSOR_COL0_B (0x0076) +#define LCD_CURSOR_COL0_G (0x0077) +#define LCD_CURSOR_COL0_R (0x0078) +#define LCD_CURSOR_COL1_B (0x007A) +#define LCD_CURSOR_COL1_G (0x007B) +#define LCD_CURSOR_COL1_R (0x007C) +#define LCD_CURSOR_FIFO (0x007E) + +typedef struct +{ + unsigned short Index; + unsigned char Value; +} S1D_REGS; + + +/* Board specific functions */ +unsigned int board_video_init (void); +void board_validate_screen (unsigned int base); +const S1D_REGS *board_get_regs (void); +int board_get_width (void); +int board_get_height (void); + +#endif /* _SED13806_H_ */ diff --git a/include/sed156x.h b/include/sed156x.h new file mode 100644 index 0000000..e980975 --- /dev/null +++ b/include/sed156x.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2004 + * + * Pantelis Antoniou + * Intracom S.A. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Video support for Epson SED156x chipset(s) */ + +#ifndef SED156X_H +#define SED156X_H + +void sed156x_init(void); +void sed156x_clear(void); +void sed156x_output_at(int x, int y, const char *str, int size); +void sed156x_reverse_at(int x, int y, int size); +void sed156x_sync(void); +void sed156x_scroll(int dx, int dy); + +/* export display */ +extern const int sed156x_text_width; +extern const int sed156x_text_height; + +#endif /* SED156X_H */ diff --git a/include/serial.h b/include/serial.h new file mode 100644 index 0000000..c8abb72 --- /dev/null +++ b/include/serial.h @@ -0,0 +1,37 @@ +#ifndef __SERIAL_H__ +#define __SERIAL_H__ + +#define NAMESIZE 16 +#define CTLRSIZE 8 + +struct serial_device { + char name[NAMESIZE]; + char ctlr[CTLRSIZE]; + + int (*init) (void); + void (*setbrg) (void); + int (*getc) (void); + int (*tstc) (void); + void (*putc) (const char c); + void (*puts) (const char *s); + + struct serial_device *next; +}; + +extern struct serial_device serial_smc_device; +extern struct serial_device serial_scc_device; +extern struct serial_device * default_serial_console (void); + +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ + || defined(CONFIG_405EP) +extern struct serial_device serial0_device; +extern struct serial_device serial1_device; +#endif + + +extern void serial_initialize(void); +extern void serial_devices_init(void); +extern int serial_assign(char * name); +extern void serial_reinit_all(void); + +#endif diff --git a/include/sm501.h b/include/sm501.h new file mode 100644 index 0000000..3e71dbb --- /dev/null +++ b/include/sm501.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * (C) Copyright 2005 + * Martin Krause TQ-Systems GmbH martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Basic video support for SMI SM501 "Voyager" graphic controller + */ + +#ifndef _SM501_H_ +#define _SM501_H_ + +#define PCI_VENDOR_SM 0x126f +#define PCI_DEVICE_SM501 0x0501 + +typedef struct { + unsigned int Index; + unsigned int Value; +} SMI_REGS; + +/* Board specific functions */ +unsigned int board_video_init (void); +void board_validate_screen (unsigned int base); +const SMI_REGS *board_get_regs (void); +int board_get_width (void); +int board_get_height (void); +unsigned int board_video_get_fb (void); + +#endif /* _SM501_H_ */ diff --git a/include/smiLynxEM.h b/include/smiLynxEM.h new file mode 100644 index 0000000..017964b --- /dev/null +++ b/include/smiLynxEM.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 1997-2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * smiLynxEM.h + * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator + * + * + * modification history + * -------------------- + * 04-18-2002 Rewritten for U-Boot . + */ + +#ifndef _SMI_LYNX_EM_H_ +#define _SMI_LYNX_EM_H_ + +/* + * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external + */ +#define VIDEO_MEM_SIZE 0x400000 + +/* + * Supported video modes for SMI Lynx E/EM/EM+ + */ +#define VIDEO_MODES 7 +#define DUAL_800_600 0 /* SMI710:VGA1:75Hz (pitch=1600) */ + /* VGA2:60/120Hz (pitch=1600) */ + /* SMI810:VGA1:75Hz (pitch=1600) */ + /* VGA2:75Hz (pitch=1600) */ +#define DUAL_1024_768 1 /* VGA1:75Hz VGA2:73Hz (pitch=2048) */ +#define SINGLE_800_600 2 /* VGA1:75Hz (pitch=800) */ +#define SINGLE_1024_768 3 /* VGA1:75Hz (pitch=1024) */ +#define SINGLE_1280_1024 4 /* VGA1:75Hz (pitch=1280) */ +#define TV_MODE_CCIR 5 /* VGA1:50Hz (h=720;v=576;pitch=720) */ +#define TV_MODE_EIA 6 /* VGA1:60Hz (h=720;v=484;pitch=720) */ + + +/* + * ISA mapped regs + */ +#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */ +#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */ +#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */ +#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */ +#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */ +#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */ +#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */ +#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */ +#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */ +#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */ +#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/ + + +/* + * Video processor control + */ +typedef struct { + unsigned int control; + unsigned int colorKey; + unsigned int colorKeyMask; + unsigned int start; + unsigned short offset; + unsigned short width; + unsigned int fifoPrio; + unsigned int fifoERL; + unsigned int YUVtoRGB; +} SmiVideoProc; + +/* + * Video window control + */ +typedef struct { + unsigned short top; + unsigned short left; + unsigned short bottom; + unsigned short right; + unsigned int srcStart; + unsigned short width; + unsigned short offset; + unsigned char hStretch; + unsigned char vStretch; +} SmiVideoWin; + +/* + * Capture port control + */ +typedef struct { + unsigned int control; + unsigned short topClip; + unsigned short leftClip; + unsigned short srcHeight; + unsigned short srcWidth; + unsigned int srcBufStart1; + unsigned int srcBufStart2; + unsigned short srcOffset; + unsigned short fifoControl; +} SmiCapturePort; + + +/******************************************************************************/ +/* Export Graphic Driver Control */ +/******************************************************************************/ + +typedef struct { + unsigned int isaBase; + unsigned int pciBase; + unsigned int dprBase; + unsigned int vprBase; + unsigned int cprBase; + unsigned int frameAdrs; + unsigned int memSize; + unsigned int mode; + unsigned int gdfIndex; + unsigned int gdfBytesPP; + unsigned int fg; + unsigned int bg; + unsigned int plnSizeX; + unsigned int plnSizeY; + unsigned int winSizeX; + unsigned int winSizeY; + char modeIdent[80]; +} GraphicDevice; + +extern GraphicDevice smi; + + +/******************************************************************************/ +/* Export Graphic Functions */ +/******************************************************************************/ + +void *video_hw_init (void); /* returns GraphicDevice struct or NULL */ + +void video_hw_bitblt ( + unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ); + +void video_hw_rectfill ( + unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ); + +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ); + +#endif /*_SMI_LYNX_EM_H_ */ diff --git a/include/spartan2.h b/include/spartan2.h new file mode 100644 index 0000000..d2e81e3 --- /dev/null +++ b/include/spartan2.h @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _SPARTAN2_H_ +#define _SPARTAN2_H_ + +#include + +extern int Spartan2_load( Xilinx_desc *desc, void *image, size_t size ); +extern int Spartan2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); +extern int Spartan2_info( Xilinx_desc *desc ); +extern int Spartan2_reloc( Xilinx_desc *desc, ulong reloc_off ); + +/* Slave Parallel Implementation function table */ +typedef struct { + Xilinx_pre_fn pre; + Xilinx_pgm_fn pgm; + Xilinx_init_fn init; + Xilinx_err_fn err; + Xilinx_done_fn done; + Xilinx_clk_fn clk; + Xilinx_cs_fn cs; + Xilinx_wr_fn wr; + Xilinx_rdata_fn rdata; + Xilinx_wdata_fn wdata; + Xilinx_busy_fn busy; + Xilinx_abort_fn abort; + Xilinx_post_fn post; + int relocated; +} Xilinx_Spartan2_Slave_Parallel_fns; + +/* Slave Serial Implementation function table */ +typedef struct { + Xilinx_pre_fn pre; + Xilinx_pgm_fn pgm; + Xilinx_clk_fn clk; + Xilinx_init_fn init; + Xilinx_done_fn done; + Xilinx_wr_fn wr; + int relocated; +} Xilinx_Spartan2_Slave_Serial_fns; + +/* Device Image Sizes + *********************************************************************/ +/* Spartan-II (2.5V) */ +#define XILINX_XC2S15_SIZE 197728/8 +#define XILINX_XC2S30_SIZE 336800/8 +#define XILINX_XC2S50_SIZE 559232/8 +#define XILINX_XC2S100_SIZE 781248/8 +#define XILINX_XC2S150_SIZE 1040128/8 + +/* Spartan-IIE (1.8V) */ +#define XILINX_XC2S50E_SIZE 630048/8 +#define XILINX_XC2S100E_SIZE 863840/8 +#define XILINX_XC2S150E_SIZE 1134496/8 +#define XILINX_XC2S200E_SIZE 1442016/8 +#define XILINX_XC2S300E_SIZE 1875648/8 + +/* Descriptor Macros + *********************************************************************/ +/* Spartan-II devices */ +#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie } + +#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie } + +#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie } + +#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie } + +#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } + +#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } + +#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie } + +#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie } + +#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie } + +#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie } + +#endif /* _SPARTAN2_H_ */ diff --git a/include/spartan3.h b/include/spartan3.h new file mode 100644 index 0000000..b14db03 --- /dev/null +++ b/include/spartan3.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _SPARTAN3_H_ +#define _SPARTAN3_H_ + +#include + +extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size ); +extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize ); +extern int Spartan3_info( Xilinx_desc *desc ); +extern int Spartan3_reloc( Xilinx_desc *desc, ulong reloc_off ); + +/* Slave Parallel Implementation function table */ +typedef struct { + Xilinx_pre_fn pre; + Xilinx_pgm_fn pgm; + Xilinx_init_fn init; + Xilinx_err_fn err; + Xilinx_done_fn done; + Xilinx_clk_fn clk; + Xilinx_cs_fn cs; + Xilinx_wr_fn wr; + Xilinx_rdata_fn rdata; + Xilinx_wdata_fn wdata; + Xilinx_busy_fn busy; + Xilinx_abort_fn abort; + Xilinx_post_fn post; + int relocated; +} Xilinx_Spartan3_Slave_Parallel_fns; + +/* Slave Serial Implementation function table */ +typedef struct { + Xilinx_pre_fn pre; + Xilinx_pgm_fn pgm; + Xilinx_clk_fn clk; + Xilinx_init_fn init; + Xilinx_done_fn done; + Xilinx_wr_fn wr; + int relocated; +} Xilinx_Spartan3_Slave_Serial_fns; + +/* Device Image Sizes + *********************************************************************/ +/* Spartan-III (1.2V) */ +#define XILINX_XC3S50_SIZE 439264/8 +#define XILINX_XC3S200_SIZE 1047616/8 +#define XILINX_XC3S400_SIZE 1699136/8 +#define XILINX_XC3S1000_SIZE 3223488/8 +#define XILINX_XC3S1500_SIZE 5214784/8 +#define XILINX_XC3S2000_SIZE 7673024/8 +#define XILINX_XC3S4000_SIZE 11316864/8 +#define XILINX_XC3S5000_SIZE 13271936/8 + +/* Descriptor Macros + *********************************************************************/ +/* Spartan-II devices */ +#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } + +#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie } + +#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie } + +#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie } + +#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie } + +#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S2000E_SIZE, fn_table, cookie } + +#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S4000E_SIZE, fn_table, cookie } + +#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie } + +#endif /* _SPARTAN3_H_ */ diff --git a/include/spd.h b/include/spd.h new file mode 100644 index 0000000..54b60d1 --- /dev/null +++ b/include/spd.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen + * + * Serial Presence Detect (SPD) EEPROM format according to the + * Intel's PC SDRAM Serial Presence Detect (SPD) Specification, + * revision 1.2B, November 1999 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _SPD_H_ +#define _SPD_H_ + +typedef struct spd_eeprom_s { + unsigned char info_size; /* 0 # bytes written into serial memory */ + unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ + unsigned char mem_type; /* 2 Fundamental memory type */ + unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ + unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ + unsigned char nrows; /* 5 # of Module Rows on this assembly */ + unsigned char dataw_lsb; /* 6 Data Width of this assembly */ + unsigned char dataw_msb; /* 7 ... Data Width continuation */ + unsigned char voltage; /* 8 Voltage intf std of this assembly */ + unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */ + unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X */ + unsigned char config; /* 11 DIMM Configuration type */ + unsigned char refresh; /* 12 Refresh Rate/Type */ + unsigned char primw; /* 13 Primary SDRAM Width */ + unsigned char ecw; /* 14 Error Checking SDRAM width */ + unsigned char min_delay; /* 15 for Back to Back Random Address */ + unsigned char burstl; /* 16 Burst Lengths Supported */ + unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ + unsigned char cas_lat; /* 18 CAS# Latencies Supported */ + unsigned char cs_lat; /* 19 CS# Latency */ + unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ + unsigned char mod_attr; /* 21 SDRAM Module Attributes */ + unsigned char dev_attr; /* 22 SDRAM Device Attributes */ + unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */ + unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */ + unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */ + unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */ + unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ + unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ + unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ + unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ + unsigned char row_dens; /* 31 Density of each row on module */ + unsigned char ca_setup; /* 32 Cmd + Addr signal input setup time */ + unsigned char ca_hold; /* 33 Cmd and Addr signal input hold time */ + unsigned char data_setup; /* 34 Data signal input setup time */ + unsigned char data_hold; /* 35 Data signal input hold time */ + unsigned char twr; /* 36 Write Recovery time tWR */ + unsigned char twtr; /* 37 Int write to read delay tWTR */ + unsigned char trtp; /* 38 Int read to precharge delay tRTP */ + unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ + unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ + unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ + unsigned char trfc; /* 42 Min Auto to Active period tRFC */ + unsigned char tckmax; /* 43 Max device cycle time tCKmax */ + unsigned char tdqsq; /* 44 Max DQS to DQ skew */ + unsigned char tqhs; /* 45 Max Read DataHold skew tQHS */ + unsigned char pll_relock; /* 46 PLL Relock time */ + unsigned char res[15]; /* 47-xx IDD in SPD and Reserved space */ + unsigned char spd_rev; /* 62 SPD Data Revision Code */ + unsigned char cksum; /* 63 Checksum for bytes 0-62 */ + unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-108E */ + unsigned char mloc; /* 72 Manufacturing Location */ + unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ + unsigned char rev[2]; /* 91 Revision Code */ + unsigned char mdate[2]; /* 93 Manufacturing Date */ + unsigned char sernum[4]; /* 95 Assembly Serial Number */ + unsigned char mspec[27]; /* 99 Manufacturer Specific Data */ + + /* + * Open for Customer Use starting with byte 128. + */ + unsigned char freq; /* 128 Intel spec: frequency */ + unsigned char intel_cas; /* 129 Intel spec: CAS# Latency support */ +} spd_eeprom_t; + + +/* + * Byte 2 Fundamental Memory Types. + */ +#define SPD_MEMTYPE_FPM (0x01) +#define SPD_MEMTYPE_EDO (0x02) +#define SPD_MEMTYPE_PIPE_NIBBLE (0x03) +#define SPD_MEMTYPE_SDRAM (0x04) +#define SPD_MEMTYPE_ROM (0x05) +#define SPD_MEMTYPE_SGRAM (0x06) +#define SPD_MEMTYPE_DDR (0x07) +#define SPD_MEMTYPE_DDR2 (0x08) + +#endif /* _SPD_H_ */ diff --git a/include/spd_sdram.h b/include/spd_sdram.h new file mode 100644 index 0000000..4e754ec --- /dev/null +++ b/include/spd_sdram.h @@ -0,0 +1,6 @@ +#ifndef _SPD_SDRAM_H_ +#define _SPD_SDRAM_H_ + +long int spd_sdram(int(read_spd)(uint addr)); + +#endif diff --git a/include/spi.h b/include/spi.h new file mode 100644 index 0000000..03dc5bc --- /dev/null +++ b/include/spi.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPI_H_ +#define _SPI_H_ + +/* + * The function call pointer type used to drive the chip select. + */ +typedef void (*spi_chipsel_type)(int cs); + + +/*----------------------------------------------------------------------- + * Initialization, must be called once on start up. + */ +void spi_init(void); + + +/*----------------------------------------------------------------------- + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks + * "bitlen" bits in the SPI MISO port. That's just the way SPI works. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that "dout" + * and "din" can point to the same memory location, in which case the + * input data overwrites the output data (since both are buffered by + * temporary variables, this is OK). + * + * If the chipsel() function is not NULL, it is called with a parameter + * of '1' (chip select active) at the start of the transfer and again with + * a parameter of '0' at the end of the transfer. + * + * If the chipsel() function _is_ NULL, it the responsibility of the + * caller to make the appropriate chip select active before calling + * spi_xfer() and making it inactive after spi_xfer() returns. + * + * spi_xfer() interface: + * chipsel: Routine to call to set/clear the chip select: + * if chipsel is NULL, it is not used. + * if(cs), make the chip select active (typically '0'). + * if(!cs), make the chip select inactive (typically '1'). + * dout: Pointer to a string of bits to send out. The bits are + * held in a byte array and are sent MSB first. + * din: Pointer to a string of bits that will be filled in. + * bitlen: How many bits to write and read. + * + * Returns: 0 on success, not 0 on failure + */ +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din); + +#endif /* _SPI_H_ */ diff --git a/include/status_led.h b/include/status_led.h new file mode 100644 index 0000000..a56883b --- /dev/null +++ b/include/status_led.h @@ -0,0 +1,360 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * The purpose of this code is to signal the operational status of a + * target which usually boots over the network; while running in + * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply + * message has been received, the LED is turned off. The Linux + * kernel, once it is running, will start blinking the LED again, + * with another frequency. + */ + +#ifndef _STATUS_LED_H_ +#define _STATUS_LED_H_ + +#ifdef CONFIG_STATUS_LED + +#define STATUS_LED_OFF 0 +#define STATUS_LED_BLINKING 1 +#define STATUS_LED_ON 2 + +void status_led_tick (unsigned long timestamp); +void status_led_set (int led, int state); + +/***** TQM8xxL ********************************************************/ +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_HMI10) +# define STATUS_LED_PAR im_cpm.cp_pbpar +# define STATUS_LED_DIR im_cpm.cp_pbdir +# define STATUS_LED_ODR im_cpm.cp_pbodr +# define STATUS_LED_DAT im_cpm.cp_pbdat + +# define STATUS_LED_BIT 0x00000001 +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** MVS v1 **********************************************************/ +#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2) +# define STATUS_LED_PAR im_ioport.iop_pdpar +# define STATUS_LED_DIR im_ioport.iop_pddir +# undef STATUS_LED_ODR +# define STATUS_LED_DAT im_ioport.iop_pddat + +# define STATUS_LED_BIT 0x00000001 +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** ETX_094 ********************************************************/ +#elif defined(CONFIG_ETX094) + +# define STATUS_LED_PAR im_ioport.iop_pdpar +# define STATUS_LED_DIR im_ioport.iop_pddir +# undef STATUS_LED_ODR +# define STATUS_LED_DAT im_ioport.iop_pddat + +# define STATUS_LED_BIT 0x00000001 +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** GEN860T *********************************************************/ +#elif defined(CONFIG_GEN860T) + +# define STATUS_LED_PAR im_ioport.iop_papar +# define STATUS_LED_DIR im_ioport.iop_padir +# define STATUS_LED_ODR im_ioport.iop_paodr +# define STATUS_LED_DAT im_ioport.iop_padat + +# define STATUS_LED_BIT 0x0800 /* Red LED 0 is on PA.4 */ +# define STATUS_LED_PERIOD (CFG_HZ / 4) +# define STATUS_LED_STATE STATUS_LED_OFF +# define STATUS_LED_BIT1 0x0400 /* Grn LED 1 is on PA.5 */ +# define STATUS_LED_PERIOD1 (CFG_HZ / 8) +# define STATUS_LED_STATE1 STATUS_LED_BLINKING +# define STATUS_LED_BIT2 0x0080 /* Red LED 2 is on PA.8 */ +# define STATUS_LED_PERIOD2 (CFG_HZ / 4) +# define STATUS_LED_STATE2 STATUS_LED_OFF +# define STATUS_LED_BIT3 0x0040 /* Grn LED 3 is on PA.9 */ +# define STATUS_LED_PERIOD3 (CFG_HZ / 4) +# define STATUS_LED_STATE3 STATUS_LED_OFF + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ +# define STATUS_LED_BOOT 1 /* Boot status on LED 1 */ + +/***** IVMS8 **********************************************************/ +#elif defined(CONFIG_IVMS8) + +# define STATUS_LED_PAR im_cpm.cp_pbpar +# define STATUS_LED_DIR im_cpm.cp_pbdir +# define STATUS_LED_ODR im_cpm.cp_pbodr +# define STATUS_LED_DAT im_cpm.cp_pbdat + +# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */ +# define STATUS_LED_PERIOD (1 * CFG_HZ) +# define STATUS_LED_STATE STATUS_LED_OFF +# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */ +# define STATUS_LED_PERIOD1 (1 * CFG_HZ) +# define STATUS_LED_STATE1 STATUS_LED_OFF +/* IDE LED usable for other purposes, too */ +# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */ +# define STATUS_LED_PERIOD2 (1 * CFG_HZ) +# define STATUS_LED_STATE2 STATUS_LED_OFF + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_ILOCK_SWITCH 0x00800000 /* ILOCK switch in IRQ4 */ + +# define STATUS_ILOCK_PERIOD (CFG_HZ / 10) /* about every 100 ms */ + +# define STATUS_LED_YELLOW 0 +# define STATUS_LED_GREEN 1 +# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */ + +/***** IVML24 *********************************************************/ +#elif defined(CONFIG_IVML24) + +# define STATUS_LED_PAR im_cpm.cp_pbpar +# define STATUS_LED_DIR im_cpm.cp_pbdir +# define STATUS_LED_ODR im_cpm.cp_pbodr +# define STATUS_LED_DAT im_cpm.cp_pbdat + +# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */ +# define STATUS_LED_PERIOD (1 * CFG_HZ) +# define STATUS_LED_STATE STATUS_LED_OFF +# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */ +# define STATUS_LED_PERIOD1 (1 * CFG_HZ) +# define STATUS_LED_STATE1 STATUS_LED_OFF +/* IDE LED usable for other purposes, too */ +# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */ +# define STATUS_LED_PERIOD2 (1 * CFG_HZ) +# define STATUS_LED_STATE2 STATUS_LED_OFF + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_ILOCK_SWITCH 0x00004000 /* ILOCK is on PB.17 */ + +# define STATUS_ILOCK_PERIOD (CFG_HZ / 10) /* about every 100 ms */ + +# define STATUS_LED_YELLOW 0 +# define STATUS_LED_GREEN 1 +# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */ + +/***** LANTEC *********************************************************/ +#elif defined(CONFIG_LANTEC) + +# define STATUS_LED_PAR im_ioport.iop_pdpar +# define STATUS_LED_DIR im_ioport.iop_pddir +# undef STATUS_LED_ODR +# define STATUS_LED_DAT im_ioport.iop_pddat + +# if CONFIG_LATEC < 2 +# define STATUS_LED_BIT 0x1000 +# else +# define STATUS_LED_BIT 0x0800 +# endif +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** PCU E and CCM ************************************************/ +#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM)) + +# define STATUS_LED_PAR im_cpm.cp_pbpar +# define STATUS_LED_DIR im_cpm.cp_pbdir +# define STATUS_LED_ODR im_cpm.cp_pbodr +# define STATUS_LED_DAT im_cpm.cp_pbdat + +# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** ICU862 ********************************************************/ +#elif defined(CONFIG_ICU862) + +# define STATUS_LED_PAR im_ioport.iop_papar +# define STATUS_LED_DIR im_ioport.iop_padir +# define STATUS_LED_ODR im_ioport.iop_paodr +# define STATUS_LED_DAT im_ioport.iop_padat + +# define STATUS_LED_BIT 0x4000 /* LED 0 is on PA.1 */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING +# define STATUS_LED_BIT1 0x1000 /* LED 1 is on PA.3 */ +# define STATUS_LED_PERIOD1 (CFG_HZ) +# define STATUS_LED_STATE1 STATUS_LED_OFF + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** Someone else defines these *************************************/ +#elif defined(STATUS_LED_PAR) + + /* + * ADVICE: Define in your board configuration file rather than + * filling this file up with lots of custom board stuff. + */ + +/***** NetVia ********************************************************/ +#elif defined(CONFIG_NETVIA) + +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 + +#define STATUS_LED_PAR im_ioport.iop_pdpar +#define STATUS_LED_DIR im_ioport.iop_pddir +#undef STATUS_LED_ODR +#define STATUS_LED_DAT im_ioport.iop_pddat + +# define STATUS_LED_BIT 0x0080 /* PD.8 */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_BIT1 0x0040 /* PD.9 */ +# define STATUS_LED_PERIOD1 (CFG_HZ / 2) +# define STATUS_LED_STATE1 STATUS_LED_OFF + +# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#endif + +/***** CMI ********************************************************/ +#elif defined(CONFIG_CMI) +# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr +# define STATUS_LED_DAT im_mios.mios_mpiosm32dr + +# define STATUS_LED_BIT 0x2000 /* Select one of the 16 possible*/ + /* MIOS outputs */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) /* Blinking periode is 500 ms */ +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */ +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** KUP4K, KUP4X ****************************************************/ +#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM) + +# define STATUS_LED_PAR im_ioport.iop_papar +# define STATUS_LED_DIR im_ioport.iop_padir +# define STATUS_LED_ODR im_ioport.iop_paodr +# define STATUS_LED_DAT im_ioport.iop_padat + +# define STATUS_LED_BIT 0x00000300 /* green + red PA[8]=yellow, PA[7]=red, PA[6]=green */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#elif defined(CONFIG_SVM_SC8xx) +# define STATUS_LED_PAR im_cpm.cp_pbpar +# define STATUS_LED_DIR im_cpm.cp_pbdir +# define STATUS_LED_ODR im_cpm.cp_pbodr +# define STATUS_LED_DAT im_cpm.cp_pbdat + +# define STATUS_LED_BIT 0x00000001 +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** RBC823 ********************************************************/ +#elif defined(CONFIG_RBC823) + +# define STATUS_LED_PAR im_ioport.iop_pcpar +# define STATUS_LED_DIR im_ioport.iop_pcdir +# undef STATUS_LED_ODR +# define STATUS_LED_DAT im_ioport.iop_pcdat + +# define STATUS_LED_BIT 0x0002 /* LED 0 is on PC.14 */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING +# define STATUS_LED_BIT1 0x0004 /* LED 1 is on PC.13 */ +# define STATUS_LED_PERIOD1 (CFG_HZ) +# define STATUS_LED_STATE1 STATUS_LED_OFF + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** HMI10 **********************************************************/ +#elif defined(CONFIG_HMI10) +# define STATUS_LED_PAR im_ioport.iop_papar +# define STATUS_LED_DIR im_ioport.iop_padir +# define STATUS_LED_ODR im_ioport.iop_paodr +# define STATUS_LED_DAT im_ioport.iop_padat + +# define STATUS_LED_BIT 0x00000001 /* LED is on PA15 */ +# define STATUS_LED_PERIOD (CFG_HZ / 2) +# define STATUS_LED_STATE STATUS_LED_BLINKING + +# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ + +# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +/***** NetPhone ********************************************************/ +#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) +/* XXX empty just to avoid the error */ +/***** STx XTc ********************************************************/ +#elif defined(CONFIG_STXXTC) +/* XXX empty just to avoid the error */ +/***** sbc8240 ********************************************************/ +#elif defined(CONFIG_WRSBC8240) +/* XXX empty just to avoid the error */ +/************************************************************************/ +#elif defined(CONFIG_NIOS2) +/* XXX empty just to avoid the error */ +/************************************************************************/ +#else +# error Status LED configuration missing +#endif +/************************************************************************/ + +#ifndef CONFIG_BOARD_SPECIFIC_LED +# include +#endif + +#endif /* CONFIG_STATUS_LED */ + +#endif /* _STATUS_LED_H_ */ diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h new file mode 100644 index 0000000..0734fe4 --- /dev/null +++ b/include/sym53c8xx.h @@ -0,0 +1,578 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + * Most of these definitions are derived from + * linux/drivers/scsi/sym53c8xx_defs.h + * + */ + +#ifndef _SYM53C8XX_DEFS_H +#define _SYM53C8XX_DEFS_H + + +#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ + +#define SCNTL1 0x01 /* no reset */ + #define ISCON 0x10 /* connected to scsi */ + #define CRST 0x08 /* force reset */ + #define IARB 0x02 /* immediate arbitration */ + +#define SCNTL2 0x02 /* no disconnect expected */ + #define SDU 0x80 /* cmd: disconnect will raise error */ + #define CHM 0x40 /* sta: chained mode */ + #define WSS 0x08 /* sta: wide scsi send [W]*/ + #define WSR 0x01 /* sta: wide scsi received [W]*/ + +#define SCNTL3 0x03 /* cnf system clock dependent */ + #define EWS 0x08 /* cmd: enable wide scsi [W]*/ + #define ULTRA 0x80 /* cmd: ULTRA enable */ + /* bits 0-2, 7 rsvd for C1010 */ + +#define SCID 0x04 /* cnf host adapter scsi address */ + #define RRE 0x40 /* r/w:e enable response to resel. */ + #define SRE 0x20 /* r/w:e enable response to select */ + +#define SXFER 0x05 /* ### Sync speed and count */ + /* bits 6-7 rsvd for C1010 */ + +#define SDID 0x06 /* ### Destination-ID */ + +#define GPREG 0x07 /* ??? IO-Pins */ + +#define SFBR 0x08 /* ### First byte in phase */ + +#define SOCL 0x09 + #define CREQ 0x80 /* r/w: SCSI-REQ */ + #define CACK 0x40 /* r/w: SCSI-ACK */ + #define CBSY 0x20 /* r/w: SCSI-BSY */ + #define CSEL 0x10 /* r/w: SCSI-SEL */ + #define CATN 0x08 /* r/w: SCSI-ATN */ + #define CMSG 0x04 /* r/w: SCSI-MSG */ + #define CC_D 0x02 /* r/w: SCSI-C_D */ + #define CI_O 0x01 /* r/w: SCSI-I_O */ + +#define SSID 0x0a + +#define SBCL 0x0b + +#define DSTAT 0x0c + #define DFE 0x80 /* sta: dma fifo empty */ + #define MDPE 0x40 /* int: master data parity error */ + #define BF 0x20 /* int: script: bus fault */ + #define ABRT 0x10 /* int: script: command aborted */ + #define SSI 0x08 /* int: script: single step */ + #define SIR 0x04 /* int: script: interrupt instruct. */ + #define IID 0x01 /* int: script: illegal instruct. */ + +#define SSTAT0 0x0d + #define ILF 0x80 /* sta: data in SIDL register lsb */ + #define ORF 0x40 /* sta: data in SODR register lsb */ + #define OLF 0x20 /* sta: data in SODL register lsb */ + #define AIP 0x10 /* sta: arbitration in progress */ + #define LOA 0x08 /* sta: arbitration lost */ + #define WOA 0x04 /* sta: arbitration won */ + #define IRST 0x02 /* sta: scsi reset signal */ + #define SDP 0x01 /* sta: scsi parity signal */ + +#define SSTAT1 0x0e + #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ + +#define SSTAT2 0x0f + #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ + #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ + #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ + #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ + #define LDSC 0x02 /* sta: disconnect & reconnect */ + +#define DSA 0x10 /* --> Base page */ +#define DSA1 0x11 +#define DSA2 0x12 +#define DSA3 0x13 + +#define ISTAT 0x14 /* --> Main Command and status */ + #define CABRT 0x80 /* cmd: abort current operation */ + #define SRST 0x40 /* mod: reset chip */ + #define SIGP 0x20 /* r/w: message from host to ncr */ + #define SEM 0x10 /* r/w: message between host + ncr */ + #define CON 0x08 /* sta: connected to scsi */ + #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ + #define SIP 0x02 /* sta: scsi-interrupt */ + #define DIP 0x01 /* sta: host/script interrupt */ + + +#define CTEST0 0x18 +#define CTEST1 0x19 +#define CTEST2 0x1a + #define CSIGP 0x40 + /* bits 0-2,7 rsvd for C1010 */ + +#define CTEST3 0x1b + #define FLF 0x08 /* cmd: flush dma fifo */ + #define CLF 0x04 /* cmd: clear dma fifo */ + #define FM 0x02 /* mod: fetch pin mode */ + #define WRIE 0x01 /* mod: write and invalidate enable */ + /* bits 4-7 rsvd for C1010 */ + +#define DFIFO 0x20 +#define CTEST4 0x21 + #define BDIS 0x80 /* mod: burst disable */ + #define MPEE 0x08 /* mod: master parity error enable */ + +#define CTEST5 0x22 + #define DFS 0x20 /* mod: dma fifo size */ + /* bits 0-1, 3-7 rsvd for C1010 */ +#define CTEST6 0x23 + +#define DBC 0x24 /* ### Byte count and command */ +#define DNAD 0x28 /* ### Next command register */ +#define DSP 0x2c /* --> Script Pointer */ +#define DSPS 0x30 /* --> Script pointer save/opcode#2 */ + +#define SCRATCHA 0x34 /* Temporary register a */ +#define SCRATCHA1 0x35 +#define SCRATCHA2 0x36 +#define SCRATCHA3 0x37 + +#define DMODE 0x38 + #define BL_2 0x80 /* mod: burst length shift value +2 */ + #define BL_1 0x40 /* mod: burst length shift value +1 */ + #define ERL 0x08 /* mod: enable read line */ + #define ERMP 0x04 /* mod: enable read multiple */ + #define BOF 0x02 /* mod: burst op code fetch */ + #define MAN 0x01 /* mod: manual start */ + +#define DIEN 0x39 +#define SBR 0x3a + +#define DCNTL 0x3b /* --> Script execution control */ + #define CLSE 0x80 /* mod: cache line size enable */ + #define PFF 0x40 /* cmd: pre-fetch flush */ + #define PFEN 0x20 /* mod: pre-fetch enable */ + #define SSM 0x10 /* mod: single step mode */ + #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ + #define STD 0x04 /* cmd: start dma mode */ + #define IRQD 0x02 /* mod: irq disable */ + #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ + /* bits 0-1 rsvd for C1010 */ + +#define ADDER 0x3c + +#define SIEN 0x40 /* -->: interrupt enable */ +#define SIST 0x42 /* <--: interrupt status */ + #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ + #define STO 0x0400/* sta: timeout (select) */ + #define GEN 0x0200/* sta: timeout (general) */ + #define HTH 0x0100/* sta: timeout (handshake) */ + #define MA 0x80 /* sta: phase mismatch */ + #define CMP 0x40 /* sta: arbitration complete */ + #define SEL 0x20 /* sta: selected by another device */ + #define RSL 0x10 /* sta: reselected by another device*/ + #define SGE 0x08 /* sta: gross error (over/underflow)*/ + #define UDC 0x04 /* sta: unexpected disconnect */ + #define RST 0x02 /* sta: scsi bus reset detected */ + #define PAR 0x01 /* sta: scsi parity error */ + +#define SLPAR 0x44 +#define SWIDE 0x45 +#define MACNTL 0x46 +#define GPCNTL 0x47 +#define STIME0 0x48 /* cmd: timeout for select&handshake*/ +#define STIME1 0x49 /* cmd: timeout user defined */ +#define RESPID 0x4a /* sta: Reselect-IDs */ + +#define STEST0 0x4c + +#define STEST1 0x4d + #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ + #define DBLEN 0x08 /* clock doubler running */ + #define DBLSEL 0x04 /* clock doubler selected */ + + +#define STEST2 0x4e + #define ROF 0x40 /* reset scsi offset (after gross error!) */ + #define EXT 0x02 /* extended filtering */ + +#define STEST3 0x4f + #define TE 0x80 /* c: tolerAnt enable */ + #define HSC 0x20 /* c: Halt SCSI Clock */ + #define CSF 0x02 /* c: clear scsi fifo */ + +#define SIDL 0x50 /* Lowlevel: latched from scsi data */ +#define STEST4 0x52 + #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ + #define SMODE_HVD 0x40 /* High Voltage Differential */ + #define SMODE_SE 0x80 /* Single Ended */ + #define SMODE_LVD 0xc0 /* Low Voltage Differential */ + #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ + /* bits 0-5 rsvd for C1010 */ + +#define SODL 0x54 /* Lowlevel: data out to scsi data */ + +#define SBDL 0x58 /* Lowlevel: data from scsi data */ + + +/*----------------------------------------------------------- +** +** Utility macros for the script. +** +**----------------------------------------------------------- +*/ + +#define REG(r) (r) + +/*----------------------------------------------------------- +** +** SCSI phases +** +** DT phases illegal for ncr driver. +** +**----------------------------------------------------------- +*/ + +#define SCR_DATA_OUT 0x00000000 +#define SCR_DATA_IN 0x01000000 +#define SCR_COMMAND 0x02000000 +#define SCR_STATUS 0x03000000 +#define SCR_DT_DATA_OUT 0x04000000 +#define SCR_DT_DATA_IN 0x05000000 +#define SCR_MSG_OUT 0x06000000 +#define SCR_MSG_IN 0x07000000 + +#define SCR_ILG_OUT 0x04000000 +#define SCR_ILG_IN 0x05000000 + +/*----------------------------------------------------------- +** +** Data transfer via SCSI. +** +**----------------------------------------------------------- +** +** MOVE_ABS (LEN) +** <> +** +** MOVE_IND (LEN) +** <> +** +** MOVE_TBL +** <> +** +**----------------------------------------------------------- +*/ + +#define OPC_MOVE 0x08000000 + +#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) +#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) +#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) + +#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) +#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) +#define SCR_CHMOV_TBL (0x10000000) + + +/*----------------------------------------------------------- +** +** Selection +** +**----------------------------------------------------------- +** +** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] +** <> +** +** SEL_TBL | << dnad_offset>> [ | REL_JMP] +** <> +** +**----------------------------------------------------------- +*/ + +#define SCR_SEL_ABS 0x40000000 +#define SCR_SEL_ABS_ATN 0x41000000 +#define SCR_SEL_TBL 0x42000000 +#define SCR_SEL_TBL_ATN 0x43000000 + + +#define SCR_JMP_REL 0x04000000 +#define SCR_ID(id) (((unsigned long)(id)) << 16) + +/*----------------------------------------------------------- +** +** Waiting for Disconnect or Reselect +** +**----------------------------------------------------------- +** +** WAIT_DISC +** dummy: <> +** +** WAIT_RESEL +** <> +** +**----------------------------------------------------------- +*/ + +#define SCR_WAIT_DISC 0x48000000 +#define SCR_WAIT_RESEL 0x50000000 + +/*----------------------------------------------------------- +** +** Bit Set / Reset +** +**----------------------------------------------------------- +** +** SET (flags {|.. }) +** +** CLR (flags {|.. }) +** +**----------------------------------------------------------- +*/ + +#define SCR_SET(f) (0x58000000 | (f)) +#define SCR_CLR(f) (0x60000000 | (f)) + +#define SCR_CARRY 0x00000400 +#define SCR_TRG 0x00000200 +#define SCR_ACK 0x00000040 +#define SCR_ATN 0x00000008 + + +/*----------------------------------------------------------- +** +** Memory to memory move +** +**----------------------------------------------------------- +** +** COPY (bytecount) +** << source_address >> +** << destination_address >> +** +** SCR_COPY sets the NO FLUSH option by default. +** SCR_COPY_F does not set this option. +** +** For chips which do not support this option, +** ncr_copy_and_bind() will remove this bit. +**----------------------------------------------------------- +*/ + +#define SCR_NO_FLUSH 0x01000000 + +#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) +#define SCR_COPY_F(n) (0xc0000000 | (n)) + +/*----------------------------------------------------------- +** +** Register move and binary operations +** +**----------------------------------------------------------- +** +** SFBR_REG (reg, op, data) reg = SFBR op data +** << 0 >> +** +** REG_SFBR (reg, op, data) SFBR = reg op data +** << 0 >> +** +** REG_REG (reg, op, data) reg = reg op data +** << 0 >> +** +**----------------------------------------------------------- +** On 810A, 860, 825A, 875, 895 and 896 chips the content +** of SFBR register can be used as data (SCR_SFBR_DATA). +** The 896 has additionnal IO registers starting at +** offset 0x80. Bit 7 of register offset is stored in +** bit 7 of the SCRIPTS instruction first DWORD. +**----------------------------------------------------------- +*/ + +#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ + +#define SCR_SFBR_REG(reg,op,data) \ + (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) + +#define SCR_REG_SFBR(reg,op,data) \ + (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) + +#define SCR_REG_REG(reg,op,data) \ + (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) + + +#define SCR_LOAD 0x00000000 +#define SCR_SHL 0x01000000 +#define SCR_OR 0x02000000 +#define SCR_XOR 0x03000000 +#define SCR_AND 0x04000000 +#define SCR_SHR 0x05000000 +#define SCR_ADD 0x06000000 +#define SCR_ADDC 0x07000000 + +#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ + +/*----------------------------------------------------------- +** +** FROM_REG (reg) SFBR = reg +** << 0 >> +** +** TO_REG (reg) reg = SFBR +** << 0 >> +** +** LOAD_REG (reg, data) reg = +** << 0 >> +** +** LOAD_SFBR(data) SFBR = +** << 0 >> +** +**----------------------------------------------------------- +*/ + +#define SCR_FROM_REG(reg) \ + SCR_REG_SFBR(reg,SCR_OR,0) + +#define SCR_TO_REG(reg) \ + SCR_SFBR_REG(reg,SCR_OR,0) + +#define SCR_LOAD_REG(reg,data) \ + SCR_REG_REG(reg,SCR_LOAD,data) + +#define SCR_LOAD_SFBR(data) \ + (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) + +/*----------------------------------------------------------- +** +** LOAD from memory to register. +** STORE from register to memory. +** +** Only supported by 810A, 860, 825A, 875, 895 and 896. +** +**----------------------------------------------------------- +** +** LOAD_ABS (LEN) +** <> +** +** LOAD_REL (LEN) (DSA relative) +** <> +** +**----------------------------------------------------------- +*/ + +#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) +#define SCR_NO_FLUSH2 0x02000000 +#define SCR_DSA_REL2 0x10000000 + +#define SCR_LOAD_R(reg, how, n) \ + (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) + +#define SCR_STORE_R(reg, how, n) \ + (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) + +#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) +#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) +#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) +#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) + +#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) +#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) +#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) +#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) + + +/*----------------------------------------------------------- +** +** Waiting for Disconnect or Reselect +** +**----------------------------------------------------------- +** +** JUMP [ | IFTRUE/IFFALSE ( ... ) ] +** <
> +** +** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** CALL [ | IFTRUE/IFFALSE ( ... ) ] +** <
> +** +** CALLR [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** RETURN [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** INT [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] +** <> +** +** Conditions: +** WHEN (phase) +** IF (phase) +** CARRYSET +** DATA (data, mask) +** +**----------------------------------------------------------- +*/ + +#define SCR_NO_OP 0x80000000 +#define SCR_JUMP 0x80080000 +#define SCR_JUMP64 0x80480000 +#define SCR_JUMPR 0x80880000 +#define SCR_CALL 0x88080000 +#define SCR_CALLR 0x88880000 +#define SCR_RETURN 0x90080000 +#define SCR_INT 0x98080000 +#define SCR_INT_FLY 0x98180000 + +#define IFFALSE(arg) (0x00080000 | (arg)) +#define IFTRUE(arg) (0x00000000 | (arg)) + +#define WHEN(phase) (0x00030000 | (phase)) +#define IF(phase) (0x00020000 | (phase)) + +#define DATA(D) (0x00040000 | ((D) & 0xff)) +#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) + +#define CARRYSET (0x00200000) + + +#define SIR_COMPLETE 0x10000000 +/* script errors */ +#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 +#define SIR_CMD_OUT_ILL_PH 0x00000002 +#define SIR_STATUS_ILL_PH 0x00000003 +#define SIR_MSG_RECEIVED 0x00000004 +#define SIR_DATA_IN_ERR 0x00000005 +#define SIR_DATA_OUT_ERR 0x00000006 +#define SIR_SCRIPT_ERROR 0x00000007 +#define SIR_MSG_OUT_NO_CMD 0x00000008 +#define SIR_MSG_OVER7 0x00000009 +/* Fly interrupt */ +#define INT_ON_FY 0x00000080 + +/* Hardware errors are defined in scsi.h */ + +#define SCSI_IDENTIFY 0xC0 + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#endif diff --git a/include/systemace.h b/include/systemace.h new file mode 100644 index 0000000..be43d46 --- /dev/null +++ b/include/systemace.h @@ -0,0 +1,31 @@ +#ifndef __SYSTEMACE_H +#define __SYSTEMACE_H +/* + * Copyright (c) 2004 Picture Elements, Inc. + * Stephen Williams (steve@picturel.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +#ident "$Id:$" + +#ifdef CONFIG_SYSTEMACE + +# include + +block_dev_desc_t * systemace_get_dev(int dev); + +#endif /* CONFIG_SYSTEMACE */ +#endif /* __SYSTEMACE_H */ diff --git a/include/universe.h b/include/universe.h new file mode 100644 index 0000000..2892d31 --- /dev/null +++ b/include/universe.h @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _universe_h +#define _universe_h + +typedef struct _UNIVERSE UNIVERSE; +typedef struct _SLAVE_IMAGE SLAVE_IMAGE; +typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET; + +struct _SLAVE_IMAGE { + unsigned int ctl; /* Control */ + unsigned int bs; /* Base */ + unsigned int bd; /* Bound */ + unsigned int to; /* Translation */ + unsigned int reserved; +}; + +struct _UNIVERSE { + unsigned int pci_id; + unsigned int pci_csr; + unsigned int pci_class; + unsigned int pci_misc0; + unsigned int pci_bs; + unsigned int spare0[10]; + unsigned int pci_misc1; + unsigned int spare1[48]; + SLAVE_IMAGE lsi[4]; + unsigned int spare2[8]; + unsigned int scyc_ctl; + unsigned int scyc_addr; + unsigned int scyc_en; + unsigned int scyc_cmp; + unsigned int scyc_swp; + unsigned int lmisc; + unsigned int slsi; + unsigned int l_cmderr; + unsigned int laerr; + unsigned int spare3[27]; + unsigned int dctl; + unsigned int dtbc; + unsigned int dla; + unsigned int spare4[1]; + unsigned int dva; + unsigned int spare5[1]; + unsigned int dcpp; + unsigned int spare6[1]; + unsigned int dgcs; + unsigned int d_llue; + unsigned int spare7[54]; + unsigned int lint_en; + unsigned int lint_stat; + unsigned int lint_map0; + unsigned int lint_map1; + unsigned int vint_en; + unsigned int vint_stat; + unsigned int vint_map0; + unsigned int vint_map1; + unsigned int statid; + unsigned int vx_statid[7]; + unsigned int spare8[48]; + unsigned int mast_ctl; + unsigned int misc_ctl; + unsigned int misc_stat; + unsigned int user_am; + unsigned int spare9[700]; + SLAVE_IMAGE vsi[4]; + unsigned int spare10[8]; + unsigned int vrai_ctl; + unsigned int vrai_bs; + unsigned int spare11[2]; + unsigned int vcsr_ctl; + unsigned int vcsr_to; + unsigned int v_amerr; + unsigned int vaerr; + unsigned int spare12[25]; + unsigned int vcsr_clr; + unsigned int vcsr_set; + unsigned int vcsr_bs; +}; + +#define IRQ_VOWN 0x0001 +#define IRQ_VIRQ1 0x0002 +#define IRQ_VIRQ2 0x0004 +#define IRQ_VIRQ3 0x0008 +#define IRQ_VIRQ4 0x0010 +#define IRQ_VIRQ5 0x0020 +#define IRQ_VIRQ6 0x0040 +#define IRQ_VIRQ7 0x0080 +#define IRQ_DMA 0x0100 +#define IRQ_LERR 0x0200 +#define IRQ_VERR 0x0400 +#define IRQ_res 0x0800 +#define IRQ_IACK 0x1000 +#define IRQ_SWINT 0x2000 +#define IRQ_SYSFAIL 0x4000 +#define IRQ_ACFAIL 0x8000 + +struct _TDMA_CMD_PACKET { + unsigned int dctl; /* DMA Control */ + unsigned int dtbc; /* Transfer Byte Count */ + unsigned int dlv; /* PCI Address */ + unsigned int res1; /* Reserved */ + unsigned int dva; /* Vme Address */ + unsigned int res2; /* Reserved */ + unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ + unsigned int res3; /* Reserved */ +}; + +#define VME_AM_A16 0x01 +#define VME_AM_A24 0x02 +#define VME_AM_A32 0x03 +#define VME_AM_Axx 0x03 +#define VME_AM_SUP 0x04 +#define VME_AM_DATA 0x10 +#define VME_AM_PROG 0x20 +#define VME_AM_Mxx 0x30 + +#define VME_FLAG_D8 0x01 +#define VME_FLAG_D16 0x02 +#define VME_FLAG_D32 0x03 +#define VME_FLAG_Dxx 0x03 + +#define PCI_MS_MEM 0x01 +#define PCI_MS_IO 0x02 +#define PCI_MS_CONFIG 0x03 +#define PCI_MS_Mxx 0x03 + +#endif diff --git a/include/usb.h b/include/usb.h new file mode 100644 index 0000000..39d7f23 --- /dev/null +++ b/include/usb.h @@ -0,0 +1,360 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: Part of this code has been derived from linux + * + */ +#ifndef _USB_H_ +#define _USB_H_ + +#include + +/* Everything is aribtrary */ +#define USB_ALTSETTINGALLOC 4 +#define USB_MAXALTSETTING 128 /* Hard limit */ + +#define USB_MAX_DEVICE 32 +#define USB_MAXCONFIG 8 +#define USB_MAXINTERFACES 8 +#define USB_MAXENDPOINTS 16 +#define USB_MAXCHILDREN 8 /* This is arbitrary */ +#define USB_MAX_HUB 16 + +#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */ + +/* String descriptor */ +struct usb_string_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned short wData[1]; +} __attribute__ ((packed)); + +/* device request (setup) */ +struct devrequest { + unsigned char requesttype; + unsigned char request; + unsigned short value; + unsigned short index; + unsigned short length; +} __attribute__ ((packed)); + + +/* All standard descriptors have these 2 fields in common */ +struct usb_descriptor_header { + unsigned char bLength; + unsigned char bDescriptorType; +} __attribute__ ((packed)); + +/* Device descriptor */ +struct usb_device_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned short bcdUSB; + unsigned char bDeviceClass; + unsigned char bDeviceSubClass; + unsigned char bDeviceProtocol; + unsigned char bMaxPacketSize0; + unsigned short idVendor; + unsigned short idProduct; + unsigned short bcdDevice; + unsigned char iManufacturer; + unsigned char iProduct; + unsigned char iSerialNumber; + unsigned char bNumConfigurations; +} __attribute__ ((packed)); + + +/* Endpoint descriptor */ +struct usb_endpoint_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bEndpointAddress; + unsigned char bmAttributes; + unsigned short wMaxPacketSize; + unsigned char bInterval; + unsigned char bRefresh; + unsigned char bSynchAddress; + +} __attribute__ ((packed)); +/* Interface descriptor */ +struct usb_interface_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bInterfaceNumber; + unsigned char bAlternateSetting; + unsigned char bNumEndpoints; + unsigned char bInterfaceClass; + unsigned char bInterfaceSubClass; + unsigned char bInterfaceProtocol; + unsigned char iInterface; + + unsigned char no_of_ep; + unsigned char act_altsetting; + struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS]; +} __attribute__ ((packed)); + + +/* Configuration descriptor information.. */ +struct usb_config_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned short wTotalLength; + unsigned char bNumInterfaces; + unsigned char bConfigurationValue; + unsigned char iConfiguration; + unsigned char bmAttributes; + unsigned char MaxPower; + + unsigned char no_of_if; /* number of interfaces */ + struct usb_interface_descriptor if_desc[USB_MAXINTERFACES]; +} __attribute__ ((packed)); + + +struct usb_device { + int devnum; /* Device number on USB bus */ + int slow; /* Slow device? */ + char mf[32]; /* manufacturer */ + char prod[32]; /* product */ + char serial[32]; /* serial number */ + + int maxpacketsize; /* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */ + unsigned int toggle[2]; /* one bit for each endpoint ([0] = IN, [1] = OUT) */ + unsigned int halted[2]; /* endpoint halts; one bit per endpoint # & direction; */ + /* [0] = IN, [1] = OUT */ + int epmaxpacketin[16]; /* INput endpoint specific maximums */ + int epmaxpacketout[16]; /* OUTput endpoint specific maximums */ + + int configno; /* selected config number */ + struct usb_device_descriptor descriptor; /* Device Descriptor */ + struct usb_config_descriptor config; /* config descriptor */ + + int have_langid; /* whether string_langid is valid yet */ + int string_langid; /* language ID for strings */ + int (*irq_handle)(struct usb_device *dev); + unsigned long irq_status; + int irq_act_len; /* transfered bytes */ + void *privptr; + /* + * Child devices - if this is a hub device + * Each instance needs its own set of data structures. + */ + unsigned long status; + int act_len; /* transfered bytes */ + int maxchild; /* Number of ports if hub */ + struct usb_device *parent; + struct usb_device *children[USB_MAXCHILDREN]; +}; + +/********************************************************************** + * this is how the lowlevel part communicate with the outer world + */ + +#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined (CONFIG_USB_SL811HS) +int usb_lowlevel_init(void); +int usb_lowlevel_stop(void); +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len); +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len,struct devrequest *setup); +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval); + +/* Defines */ +#define USB_UHCI_VEND_ID 0x8086 +#define USB_UHCI_DEV_ID 0x7112 + +#else +#error USB Lowlevel not defined +#endif + +#ifdef CONFIG_USB_STORAGE + +#define USB_MAX_STOR_DEV 5 +block_dev_desc_t *usb_stor_get_dev(int index); +int usb_stor_scan(int mode); +void usb_stor_info(void); + +#endif + +#ifdef CONFIG_USB_KEYBOARD + +int drv_usb_kbd_init(void); +int usb_kbd_deregister(void); + +#endif +/* routines */ +int usb_init(void); /* initialize the USB Controller */ +int usb_stop(void); /* stop the USB Controller */ + + +int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol); +int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id); +struct usb_device * usb_get_dev_index(int index); +int usb_control_msg(struct usb_device *dev, unsigned int pipe, + unsigned char request, unsigned char requesttype, + unsigned short value, unsigned short index, + void *data, unsigned short size, int timeout); +int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, + void *data, int len, int *actual_length, int timeout); +int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe, + void *buffer,int transfer_len, int interval); +void usb_disable_asynch(int disable); +int usb_maxpacket(struct usb_device *dev,unsigned long pipe); +void __inline__ wait_ms(unsigned long ms); +int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cfgno); +int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, unsigned char id, void *buf, int size); +int usb_get_class_descriptor(struct usb_device *dev, int ifnum, + unsigned char type, unsigned char id, void *buf, int size); +int usb_clear_halt(struct usb_device *dev, int pipe); +int usb_string(struct usb_device *dev, int index, char *buf, size_t size); +int usb_set_interface(struct usb_device *dev, int interface, int alternate); + +/* big endian -> little endian conversion */ +/* some CPUs are already little endian e.g. the ARM920T */ +#ifdef LITTLEENDIAN +#define swap_16(x) ((unsigned short)(x)) +#define swap_32(x) ((unsigned long)(x)) +#else +#define swap_16(x) \ + ({ unsigned short x_ = (unsigned short)x; \ + (unsigned short)( \ + ((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8) ); \ + }) +#define swap_32(x) \ + ({ unsigned long x_ = (unsigned long)x; \ + (unsigned long)( \ + ((x_ & 0x000000FFUL) << 24) | \ + ((x_ & 0x0000FF00UL) << 8) | \ + ((x_ & 0x00FF0000UL) >> 8) | \ + ((x_ & 0xFF000000UL) >> 24) ); \ + }) +#endif /* LITTLEENDIAN */ + +/* + * Calling this entity a "pipe" is glorifying it. A USB pipe + * is something embarrassingly simple: it basically consists + * of the following information: + * - device number (7 bits) + * - endpoint number (4 bits) + * - current Data0/1 state (1 bit) + * - direction (1 bit) + * - speed (1 bit) + * - max packet size (2 bits: 8, 16, 32 or 64) + * - pipe type (2 bits: control, interrupt, bulk, isochronous) + * + * That's 18 bits. Really. Nothing more. And the USB people have + * documented these eighteen bits as some kind of glorious + * virtual data structure. + * + * Let's not fall in that trap. We'll just encode it as a simple + * unsigned int. The encoding is: + * + * - max size: bits 0-1 (00 = 8, 01 = 16, 10 = 32, 11 = 64) + * - direction: bit 7 (0 = Host-to-Device [Out], 1 = Device-to-Host [In]) + * - device: bits 8-14 + * - endpoint: bits 15-18 + * - Data0/1: bit 19 + * - speed: bit 26 (0 = Full, 1 = Low Speed) + * - pipe type: bits 30-31 (00 = isochronous, 01 = interrupt, 10 = control, 11 = bulk) + * + * Why? Because it's arbitrary, and whatever encoding we select is really + * up to us. This one happens to share a lot of bit positions with the UHCI + * specification, so that much of the uhci driver can just mask the bits + * appropriately. + */ +/* Create various pipes... */ +#define create_pipe(dev,endpoint) \ + (((dev)->devnum << 8) | (endpoint << 15) | ((dev)->slow << 26) | (dev)->maxpacketsize) +#define default_pipe(dev) ((dev)->slow <<26) + +#define usb_sndctrlpipe(dev,endpoint) ((PIPE_CONTROL << 30) | create_pipe(dev,endpoint)) +#define usb_rcvctrlpipe(dev,endpoint) ((PIPE_CONTROL << 30) | create_pipe(dev,endpoint) | USB_DIR_IN) +#define usb_sndisocpipe(dev,endpoint) ((PIPE_ISOCHRONOUS << 30) | create_pipe(dev,endpoint)) +#define usb_rcvisocpipe(dev,endpoint) ((PIPE_ISOCHRONOUS << 30) | create_pipe(dev,endpoint) | USB_DIR_IN) +#define usb_sndbulkpipe(dev,endpoint) ((PIPE_BULK << 30) | create_pipe(dev,endpoint)) +#define usb_rcvbulkpipe(dev,endpoint) ((PIPE_BULK << 30) | create_pipe(dev,endpoint) | USB_DIR_IN) +#define usb_sndintpipe(dev,endpoint) ((PIPE_INTERRUPT << 30) | create_pipe(dev,endpoint)) +#define usb_rcvintpipe(dev,endpoint) ((PIPE_INTERRUPT << 30) | create_pipe(dev,endpoint) | USB_DIR_IN) +#define usb_snddefctrl(dev) ((PIPE_CONTROL << 30) | default_pipe(dev)) +#define usb_rcvdefctrl(dev) ((PIPE_CONTROL << 30) | default_pipe(dev) | USB_DIR_IN) + +/* The D0/D1 toggle bits */ +#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1) +#define usb_dotoggle(dev, ep, out) ((dev)->toggle[out] ^= (1 << ep)) +#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = ((dev)->toggle[out] & ~(1 << ep)) | ((bit) << ep)) + +/* Endpoint halt control/status */ +#define usb_endpoint_out(ep_dir) (((ep_dir >> 7) & 1) ^ 1) +#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep))) +#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep))) +#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep))) + +#define usb_packetid(pipe) (((pipe) & USB_DIR_IN) ? USB_PID_IN : USB_PID_OUT) + +#define usb_pipeout(pipe) ((((pipe) >> 7) & 1) ^ 1) +#define usb_pipein(pipe) (((pipe) >> 7) & 1) +#define usb_pipedevice(pipe) (((pipe) >> 8) & 0x7f) +#define usb_pipe_endpdev(pipe) (((pipe) >> 8) & 0x7ff) +#define usb_pipeendpoint(pipe) (((pipe) >> 15) & 0xf) +#define usb_pipedata(pipe) (((pipe) >> 19) & 1) +#define usb_pipeslow(pipe) (((pipe) >> 26) & 1) +#define usb_pipetype(pipe) (((pipe) >> 30) & 3) +#define usb_pipeisoc(pipe) (usb_pipetype((pipe)) == PIPE_ISOCHRONOUS) +#define usb_pipeint(pipe) (usb_pipetype((pipe)) == PIPE_INTERRUPT) +#define usb_pipecontrol(pipe) (usb_pipetype((pipe)) == PIPE_CONTROL) +#define usb_pipebulk(pipe) (usb_pipetype((pipe)) == PIPE_BULK) + + +/************************************************************************* + * Hub Stuff + */ +struct usb_port_status { + unsigned short wPortStatus; + unsigned short wPortChange; +} __attribute__ ((packed)); + +struct usb_hub_status { + unsigned short wHubStatus; + unsigned short wHubChange; +} __attribute__ ((packed)); + + +/* Hub descriptor */ +struct usb_hub_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bNbrPorts; + unsigned short wHubCharacteristics; + unsigned char bPwrOn2PwrGood; + unsigned char bHubContrCurrent; + unsigned char DeviceRemovable[(USB_MAXCHILDREN+1+7)/8]; + unsigned char PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8]; + /* DeviceRemovable and PortPwrCtrlMask want to be variable-length + bitmaps that hold max 255 entries. (bit0 is ignored) */ +} __attribute__ ((packed)); + + +struct usb_hub_device { + struct usb_device *pusb_dev; + struct usb_hub_descriptor desc; +}; + +#endif /*_USB_H_ */ diff --git a/include/usb_defs.h b/include/usb_defs.h new file mode 100644 index 0000000..353019f --- /dev/null +++ b/include/usb_defs.h @@ -0,0 +1,241 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: Part of this code has been derived from linux + * + */ +#ifndef _USB_DEFS_H_ +#define _USB_DEFS_H_ + +/* USB constants */ + +/* Device and/or Interface Class codes */ +#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ +#define USB_CLASS_AUDIO 1 +#define USB_CLASS_COMM 2 +#define USB_CLASS_HID 3 +#define USB_CLASS_PRINTER 7 +#define USB_CLASS_MASS_STORAGE 8 +#define USB_CLASS_HUB 9 +#define USB_CLASS_DATA 10 +#define USB_CLASS_VENDOR_SPEC 0xff + +/* some HID sub classes */ +#define USB_SUB_HID_NONE 0 +#define USB_SUB_HID_BOOT 1 + +/* some UID Protocols */ +#define USB_PROT_HID_NONE 0 +#define USB_PROT_HID_KEYBOARD 1 +#define USB_PROT_HID_MOUSE 2 + + +/* Sub STORAGE Classes */ +#define US_SC_RBC 1 /* Typically, flash devices */ +#define US_SC_8020 2 /* CD-ROM */ +#define US_SC_QIC 3 /* QIC-157 Tapes */ +#define US_SC_UFI 4 /* Floppy */ +#define US_SC_8070 5 /* Removable media */ +#define US_SC_SCSI 6 /* Transparent */ +#define US_SC_MIN US_SC_RBC +#define US_SC_MAX US_SC_SCSI + +/* STORAGE Protocols */ +#define US_PR_CB 1 /* Control/Bulk w/o interrupt */ +#define US_PR_CBI 0 /* Control/Bulk/Interrupt */ +#define US_PR_BULK 0x50 /* bulk only */ + +/* USB types */ +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + +/* USB recipients */ +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 + +/* USB directions */ +#define USB_DIR_OUT 0 +#define USB_DIR_IN 0x80 + +/* Descriptor types */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 + +#define USB_DT_HID (USB_TYPE_CLASS | 0x01) +#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02) +#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) +#define USB_DT_HUB (USB_TYPE_CLASS | 0x09) + +/* Descriptor sizes per descriptor type */ +#define USB_DT_DEVICE_SIZE 18 +#define USB_DT_CONFIG_SIZE 9 +#define USB_DT_INTERFACE_SIZE 9 +#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ +#define USB_DT_HUB_NONVAR_SIZE 7 +#define USB_DT_HID_SIZE 9 + +/* Endpoints */ +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 + +/* USB Packet IDs (PIDs) */ +#define USB_PID_UNDEF_0 0xf0 +#define USB_PID_OUT 0xe1 +#define USB_PID_ACK 0xd2 +#define USB_PID_DATA0 0xc3 +#define USB_PID_UNDEF_4 0xb4 +#define USB_PID_SOF 0xa5 +#define USB_PID_UNDEF_6 0x96 +#define USB_PID_UNDEF_7 0x87 +#define USB_PID_UNDEF_8 0x78 +#define USB_PID_IN 0x69 +#define USB_PID_NAK 0x5a +#define USB_PID_DATA1 0x4b +#define USB_PID_PREAMBLE 0x3c +#define USB_PID_SETUP 0x2d +#define USB_PID_STALL 0x1e +#define USB_PID_UNDEF_F 0x0f + +/* Standard requests */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +/* HID requests */ +#define USB_REQ_GET_REPORT 0x01 +#define USB_REQ_GET_IDLE 0x02 +#define USB_REQ_GET_PROTOCOL 0x03 +#define USB_REQ_SET_REPORT 0x09 +#define USB_REQ_SET_IDLE 0x0A +#define USB_REQ_SET_PROTOCOL 0x0B + + +/* "pipe" definitions */ + +#define PIPE_ISOCHRONOUS 0 +#define PIPE_INTERRUPT 1 +#define PIPE_CONTROL 2 +#define PIPE_BULK 3 +#define PIPE_DEVEP_MASK 0x0007ff00 + +#define USB_ISOCHRONOUS 0 +#define USB_INTERRUPT 1 +#define USB_CONTROL 2 +#define USB_BULK 3 + +/* USB-status codes: */ +#define USB_ST_ACTIVE 0x1 /* TD is active */ +#define USB_ST_STALLED 0x2 /* TD is stalled */ +#define USB_ST_BUF_ERR 0x4 /* buffer error */ +#define USB_ST_BABBLE_DET 0x8 /* Babble detected */ +#define USB_ST_NAK_REC 0x10 /* NAK Received*/ +#define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */ +#define USB_ST_BIT_ERR 0x40 /* Bitstuff error */ +#define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */ + + +/************************************************************************* + * Hub defines + */ + +/* + * Hub request types + */ + +#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE) +#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER) + +/* + * Hub Class feature numbers + */ +#define C_HUB_LOCAL_POWER 0 +#define C_HUB_OVER_CURRENT 1 + +/* + * Port feature numbers + */ +#define USB_PORT_FEAT_CONNECTION 0 +#define USB_PORT_FEAT_ENABLE 1 +#define USB_PORT_FEAT_SUSPEND 2 +#define USB_PORT_FEAT_OVER_CURRENT 3 +#define USB_PORT_FEAT_RESET 4 +#define USB_PORT_FEAT_POWER 8 +#define USB_PORT_FEAT_LOWSPEED 9 +#define USB_PORT_FEAT_C_CONNECTION 16 +#define USB_PORT_FEAT_C_ENABLE 17 +#define USB_PORT_FEAT_C_SUSPEND 18 +#define USB_PORT_FEAT_C_OVER_CURRENT 19 +#define USB_PORT_FEAT_C_RESET 20 + +/* wPortStatus bits */ +#define USB_PORT_STAT_CONNECTION 0x0001 +#define USB_PORT_STAT_ENABLE 0x0002 +#define USB_PORT_STAT_SUSPEND 0x0004 +#define USB_PORT_STAT_OVERCURRENT 0x0008 +#define USB_PORT_STAT_RESET 0x0010 +#define USB_PORT_STAT_POWER 0x0100 +#define USB_PORT_STAT_LOW_SPEED 0x0200 + +/* wPortChange bits */ +#define USB_PORT_STAT_C_CONNECTION 0x0001 +#define USB_PORT_STAT_C_ENABLE 0x0002 +#define USB_PORT_STAT_C_SUSPEND 0x0004 +#define USB_PORT_STAT_C_OVERCURRENT 0x0008 +#define USB_PORT_STAT_C_RESET 0x0010 + +/* wHubCharacteristics (masks) */ +#define HUB_CHAR_LPSM 0x0003 +#define HUB_CHAR_COMPOUND 0x0004 +#define HUB_CHAR_OCPM 0x0018 + +/* + *Hub Status & Hub Change bit masks + */ +#define HUB_STATUS_LOCAL_POWER 0x0001 +#define HUB_STATUS_OVERCURRENT 0x0002 + +#define HUB_CHANGE_LOCAL_POWER 0x0001 +#define HUB_CHANGE_OVERCURRENT 0x0002 + +#endif /*_USB_DEFS_H_ */ diff --git a/include/usbdcore.h b/include/usbdcore.h new file mode 100644 index 0000000..6e92df1 --- /dev/null +++ b/include/usbdcore.h @@ -0,0 +1,671 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on linux/drivers/usbd/usbd.h + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __USBDCORE_H__ +#define __USBDCORE_H__ + +#include +#include "usbdescriptors.h" + + +#define MAX_URBS_QUEUED 5 + + +#if 1 +#define usberr(fmt,args...) serial_printf("ERROR: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#else +#define usberr(fmt,args...) do{}while(0) +#endif + +#if 0 +#define usbdbg(fmt,args...) serial_printf("debug: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#else +#define usbdbg(fmt,args...) do{}while(0) +#endif + +#if 0 +#define usbinfo(fmt,args...) serial_printf("info: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args) +#else +#define usbinfo(fmt,args...) do{}while(0) +#endif + +#ifndef le16_to_cpu +#define le16_to_cpu(x) (x) +#endif + +#ifndef inb +#define inb(p) (*(volatile u8*)(p)) +#endif + +#ifndef outb +#define outb(val,p) (*(volatile u8*)(p) = (val)) +#endif + +#ifndef inw +#define inw(p) (*(volatile u16*)(p)) +#endif + +#ifndef outw +#define outw(val,p) (*(volatile u16*)(p) = (val)) +#endif + +#ifndef inl +#define inl(p) (*(volatile u32*)(p)) +#endif + +#ifndef outl +#define outl(val,p) (*(volatile u32*)(p) = (val)) +#endif + +#ifndef insw +#define insw(p,to,len) mmio_insw(p,to,len) +#endif + +#ifndef outsw +#define outsw(p,from,len) mmio_outsw(p,from,len) +#endif + +#ifndef insb +#define insb(p,to,len) mmio_insb(p,to,len) +#endif + +#ifndef mmio_insw +#define mmio_insw(r,b,l) ({ int __i ; \ + u16 *__b2; \ + __b2 = (u16 *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = inw(r); \ + }; \ + }) +#endif + +#ifndef mmio_outsw +#define mmio_outsw(r,b,l) ({ int __i; \ + u16 *__b2; \ + __b2 = (u16 *) b; \ + for (__i = 0; __i < l; __i++) { \ + outw( *(__b2 + __i), r); \ + } \ + }) +#endif + +#ifndef mmio_insb +#define mmio_insb(r,b,l) ({ int __i ; \ + u8 *__b2; \ + __b2 = (u8 *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = inb(r); \ + }; \ + }) +#endif + +#ifndef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif +#ifndef MAX +#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif + + +/* + * Structure member address manipulation macros. + * These are used by client code (code using the urb_link routines), since + * the urb_link structure is embedded in the client data structures. + * + * Note: a macro offsetof equivalent to member_offset is defined in stddef.h + * but this is kept here for the sake of portability. + * + * p2surround returns a pointer to the surrounding structure given + * type of the surrounding structure, the name memb of the structure + * member pointed at by ptr. For example, if you have: + * + * struct foo { + * int x; + * float y; + * char z; + * } thingy; + * + * char *cp = &thingy.z; + * + * then + * + * &thingy == p2surround(struct foo, z, cp) + * + * Clear? + */ +#define _cv_(ptr) ((char*)(void*)(ptr)) +#define member_offset(type,memb) (_cv_(&(((type*)0)->memb))-(char*)0) +#define p2surround(type,memb,ptr) ((type*)(void*)(_cv_(ptr)-member_offset(type,memb))) + +struct urb; + +struct usb_endpoint_instance; +struct usb_interface_instance; +struct usb_configuration_instance; +struct usb_device_instance; +struct usb_bus_instance; + +/* + * Device and/or Interface Class codes + */ +#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ +#define USB_CLASS_AUDIO 1 +#define USB_CLASS_COMM 2 +#define USB_CLASS_HID 3 +#define USB_CLASS_PHYSICAL 5 +#define USB_CLASS_PRINTER 7 +#define USB_CLASS_MASS_STORAGE 8 +#define USB_CLASS_HUB 9 +#define USB_CLASS_DATA 10 +#define USB_CLASS_APP_SPEC 0xfe +#define USB_CLASS_VENDOR_SPEC 0xff + +/* + * USB types + */ +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + +/* + * USB recipients + */ +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 + +/* + * USB directions + */ +#define USB_DIR_OUT 0 +#define USB_DIR_IN 0x80 + +/* + * Descriptor types + */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 + +#define USB_DT_HID (USB_TYPE_CLASS | 0x01) +#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02) +#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) +#define USB_DT_HUB (USB_TYPE_CLASS | 0x09) + +/* + * Descriptor sizes per descriptor type + */ +#define USB_DT_DEVICE_SIZE 18 +#define USB_DT_CONFIG_SIZE 9 +#define USB_DT_INTERFACE_SIZE 9 +#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ +#define USB_DT_HUB_NONVAR_SIZE 7 +#define USB_DT_HID_SIZE 9 + +/* + * Endpoints + */ +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 + +/* + * USB Packet IDs (PIDs) + */ +#define USB_PID_UNDEF_0 0xf0 +#define USB_PID_OUT 0xe1 +#define USB_PID_ACK 0xd2 +#define USB_PID_DATA0 0xc3 +#define USB_PID_PING 0xb4 /* USB 2.0 */ +#define USB_PID_SOF 0xa5 +#define USB_PID_NYET 0x96 /* USB 2.0 */ +#define USB_PID_DATA2 0x87 /* USB 2.0 */ +#define USB_PID_SPLIT 0x78 /* USB 2.0 */ +#define USB_PID_IN 0x69 +#define USB_PID_NAK 0x5a +#define USB_PID_DATA1 0x4b +#define USB_PID_PREAMBLE 0x3c /* Token mode */ +#define USB_PID_ERR 0x3c /* USB 2.0: handshake mode */ +#define USB_PID_SETUP 0x2d +#define USB_PID_STALL 0x1e +#define USB_PID_MDATA 0x0f /* USB 2.0 */ + +/* + * Standard requests + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USBD_DEVICE_REQUESTS(x) (((unsigned int)x <= USB_REQ_SYNCH_FRAME) ? usbd_device_requests[x] : "UNKNOWN") + +/* + * HID requests + */ +#define USB_REQ_GET_REPORT 0x01 +#define USB_REQ_GET_IDLE 0x02 +#define USB_REQ_GET_PROTOCOL 0x03 +#define USB_REQ_SET_REPORT 0x09 +#define USB_REQ_SET_IDLE 0x0A +#define USB_REQ_SET_PROTOCOL 0x0B + + +/* + * USB Spec Release number + */ + +#define USB_BCD_VERSION 0x0110 + + +/* + * Device Requests (c.f Table 9-2) + */ + +#define USB_REQ_DIRECTION_MASK 0x80 +#define USB_REQ_TYPE_MASK 0x60 +#define USB_REQ_RECIPIENT_MASK 0x1f + +#define USB_REQ_DEVICE2HOST 0x80 +#define USB_REQ_HOST2DEVICE 0x00 + +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 + +#define USB_REQ_RECIPIENT_DEVICE 0x00 +#define USB_REQ_RECIPIENT_INTERFACE 0x01 +#define USB_REQ_RECIPIENT_ENDPOINT 0x02 +#define USB_REQ_RECIPIENT_OTHER 0x03 + +/* + * get status bits + */ + +#define USB_STATUS_SELFPOWERED 0x01 +#define USB_STATUS_REMOTEWAKEUP 0x02 + +#define USB_STATUS_HALT 0x01 + +/* + * descriptor types + */ + +#define USB_DESCRIPTOR_TYPE_DEVICE 0x01 +#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02 +#define USB_DESCRIPTOR_TYPE_STRING 0x03 +#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04 +#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05 +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06 +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION 0x07 +#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08 +#define USB_DESCRIPTOR_TYPE_HID 0x21 +#define USB_DESCRIPTOR_TYPE_REPORT 0x22 + +#define USBD_DEVICE_DESCRIPTORS(x) (((unsigned int)x <= USB_DESCRIPTOR_TYPE_INTERFACE_POWER) ? \ + usbd_device_descriptors[x] : "UNKNOWN") + +/* + * standard feature selectors + */ +#define USB_ENDPOINT_HALT 0x00 +#define USB_DEVICE_REMOTE_WAKEUP 0x01 +#define USB_TEST_MODE 0x02 + + +/* USB Requests + * + */ + +struct usb_device_request { + u8 bmRequestType; + u8 bRequest; + u16 wValue; + u16 wIndex; + u16 wLength; +} __attribute__ ((packed)); + + +/* USB Status + * + */ +typedef enum urb_send_status { + SEND_IN_PROGRESS, + SEND_FINISHED_OK, + SEND_FINISHED_ERROR, + RECV_READY, + RECV_OK, + RECV_ERROR +} urb_send_status_t; + +/* + * Device State (c.f USB Spec 2.0 Figure 9-1) + * + * What state the usb device is in. + * + * Note the state does not change if the device is suspended, we simply set a + * flag to show that it is suspended. + * + */ +typedef enum usb_device_state { + STATE_INIT, /* just initialized */ + STATE_CREATED, /* just created */ + STATE_ATTACHED, /* we are attached */ + STATE_POWERED, /* we have seen power indication (electrical bus signal) */ + STATE_DEFAULT, /* we been reset */ + STATE_ADDRESSED, /* we have been addressed (in default configuration) */ + STATE_CONFIGURED, /* we have seen a set configuration device command */ + STATE_UNKNOWN, /* destroyed */ +} usb_device_state_t; + +#define USBD_DEVICE_STATE(x) (((unsigned int)x <= STATE_UNKNOWN) ? usbd_device_states[x] : "UNKNOWN") + +/* + * Device status + * + * Overall state + */ +typedef enum usb_device_status { + USBD_OPENING, /* we are currently opening */ + USBD_OK, /* ok to use */ + USBD_SUSPENDED, /* we are currently suspended */ + USBD_CLOSING, /* we are currently closing */ +} usb_device_status_t; + +#define USBD_DEVICE_STATUS(x) (((unsigned int)x <= USBD_CLOSING) ? usbd_device_status[x] : "UNKNOWN") + +/* + * Device Events + * + * These are defined in the USB Spec (c.f USB Spec 2.0 Figure 9-1). + * + * There are additional events defined to handle some extra actions we need + * to have handled. + * + */ +typedef enum usb_device_event { + + DEVICE_UNKNOWN, /* bi - unknown event */ + DEVICE_INIT, /* bi - initialize */ + DEVICE_CREATE, /* bi - */ + DEVICE_HUB_CONFIGURED, /* bi - bus has been plugged int */ + DEVICE_RESET, /* bi - hub has powered our port */ + + DEVICE_ADDRESS_ASSIGNED, /* ep0 - set address setup received */ + DEVICE_CONFIGURED, /* ep0 - set configure setup received */ + DEVICE_SET_INTERFACE, /* ep0 - set interface setup received */ + + DEVICE_SET_FEATURE, /* ep0 - set feature setup received */ + DEVICE_CLEAR_FEATURE, /* ep0 - clear feature setup received */ + + DEVICE_DE_CONFIGURED, /* ep0 - set configure setup received for ?? */ + + DEVICE_BUS_INACTIVE, /* bi - bus in inactive (no SOF packets) */ + DEVICE_BUS_ACTIVITY, /* bi - bus is active again */ + + DEVICE_POWER_INTERRUPTION, /* bi - hub has depowered our port */ + DEVICE_HUB_RESET, /* bi - bus has been unplugged */ + DEVICE_DESTROY, /* bi - device instance should be destroyed */ + + DEVICE_HOTPLUG, /* bi - a hotplug event has occured */ + + DEVICE_FUNCTION_PRIVATE, /* function - private */ + +} usb_device_event_t; + + +typedef struct urb_link { + struct urb_link *next; + struct urb_link *prev; +} urb_link; + +/* USB Data structure - for passing data around. + * + * This is used for both sending and receiving data. + * + * The callback function is used to let the function driver know when + * transmitted data has been sent. + * + * The callback function is set by the alloc_recv function when an urb is + * allocated for receiving data for an endpoint and used to call the + * function driver to inform it that data has arrived. + */ + +#define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer static data */ +struct urb { + + struct usb_endpoint_instance *endpoint; + struct usb_device_instance *device; + + struct usb_device_request device_request; /* contents of received SETUP packet */ + + struct urb_link link; /* embedded struct for circular doubly linked list of urbs */ + + u8* buffer; + unsigned int buffer_length; + unsigned int actual_length; + + urb_send_status_t status; + int data; + + u16 buffer_data[URB_BUF_SIZE]; /* data received (OUT) or being sent (IN) */ +}; + +/* Endpoint configuration + * + * Per endpoint configuration data. Used to track which function driver owns + * an endpoint. + * + */ +struct usb_endpoint_instance { + int endpoint_address; /* logical endpoint address */ + + /* control */ + int status; /* halted */ + int state; /* available for use by bus interface driver */ + + /* receive side */ + struct urb_link rcv; /* received urbs */ + struct urb_link rdy; /* empty urbs ready to receive */ + struct urb *rcv_urb; /* active urb */ + int rcv_attributes; /* copy of bmAttributes from endpoint descriptor */ + int rcv_packetSize; /* maximum packet size from endpoint descriptor */ + int rcv_transferSize; /* maximum transfer size from function driver */ + int rcv_queue; + + /* transmit side */ + struct urb_link tx; /* urbs ready to transmit */ + struct urb_link done; /* transmitted urbs */ + struct urb *tx_urb; /* active urb */ + int tx_attributes; /* copy of bmAttributes from endpoint descriptor */ + int tx_packetSize; /* maximum packet size from endpoint descriptor */ + int tx_transferSize; /* maximum transfer size from function driver */ + int tx_queue; + + int sent; /* data already sent */ + int last; /* data sent in last packet XXX do we need this */ +}; + +struct usb_alternate_instance { + struct usb_interface_descriptor *interface_descriptor; + + int endpoints; + int *endpoint_transfersize_array; + struct usb_endpoint_descriptor **endpoints_descriptor_array; +}; + +struct usb_interface_instance { + int alternates; + struct usb_alternate_instance *alternates_instance_array; +}; + +struct usb_configuration_instance { + int interfaces; + struct usb_configuration_descriptor *configuration_descriptor; + struct usb_interface_instance *interface_instance_array; +}; + + +/* USB Device Instance + * + * For each physical bus interface we create a logical device structure. This + * tracks all of the required state to track the USB HOST's view of the device. + * + * Keep track of the device configuration for a real physical bus interface, + * this includes the bus interface, multiple function drivers, the current + * configuration and the current state. + * + * This will show: + * the specific bus interface driver + * the default endpoint 0 driver + * the configured function driver + * device state + * device status + * endpoint list + */ + +struct usb_device_instance { + + /* generic */ + char *name; + struct usb_device_descriptor *device_descriptor; /* per device descriptor */ + + void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data); + + /* bus interface */ + struct usb_bus_instance *bus; /* which bus interface driver */ + + /* configuration descriptors */ + int configurations; + struct usb_configuration_instance *configuration_instance_array; + + /* device state */ + usb_device_state_t device_state; /* current USB Device state */ + usb_device_state_t device_previous_state; /* current USB Device state */ + + u8 address; /* current address (zero is default) */ + u8 configuration; /* current show configuration (zero is default) */ + u8 interface; /* current interface (zero is default) */ + u8 alternate; /* alternate flag */ + + usb_device_status_t status; /* device status */ + + int urbs_queued; /* number of submitted urbs */ + + /* Shouldn't need to make this atomic, all we need is a change indicator */ + unsigned long usbd_rxtx_timestamp; + unsigned long usbd_last_rxtx_timestamp; + +}; + +/* Bus Interface configuration structure + * + * This is allocated for each configured instance of a bus interface driver. + * + * The privdata pointer may be used by the bus interface driver to store private + * per instance state information. + */ +struct usb_bus_instance { + + struct usb_device_instance *device; + struct usb_endpoint_instance *endpoint_array; /* array of available configured endpoints */ + + int max_endpoints; /* maximimum number of rx enpoints */ + unsigned char maxpacketsize; + + unsigned int serial_number; + char *serial_number_str; + void *privdata; /* private data for the bus interface */ + +}; + +extern char *usbd_device_events[]; +extern char *usbd_device_states[]; +extern char *usbd_device_status[]; +extern char *usbd_device_requests[]; +extern char *usbd_device_descriptors[]; + +void urb_link_init (urb_link * ul); +void urb_detach (struct urb *urb); +urb_link *first_urb_link (urb_link * hd); +struct urb *first_urb (urb_link * hd); +struct urb *first_urb_detached (urb_link * hd); +void urb_append (urb_link * hd, struct urb *urb); + +struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint); +void usbd_dealloc_urb (struct urb *urb); + +/* + * usbd_device_event is used by bus interface drivers to tell the higher layers that + * certain events have taken place. + */ +void usbd_device_event_irq (struct usb_device_instance *conf, usb_device_event_t, int); +void usbd_device_event (struct usb_device_instance *conf, usb_device_event_t, int); + +/* descriptors + * + * Various ways of finding descriptors based on the current device and any + * possible configuration / interface / endpoint for it. + */ +struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct usb_device_instance *, int, int); +struct usb_function_instance *usbd_device_function_instance (struct usb_device_instance *, unsigned int); +struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *, int, int, int); +struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *, int, int, int, int); +struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance *, int, int, int, int); +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance *, int, int, int, int, int); +struct usb_class_descriptor *usbd_device_class_descriptor_index (struct usb_device_instance *, int, int, int, int, int); +struct usb_class_report_descriptor *usbd_device_class_report_descriptor_index( struct usb_device_instance *, int , int , int , int , int ); +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *, int, int, int, int, int); +int usbd_device_endpoint_transfersize (struct usb_device_instance *, int, int, int, int, int); +struct usb_string_descriptor *usbd_get_string (u8); +struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *, int); + +int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint); +void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad); +void usbd_tx_complete (struct usb_endpoint_instance *endpoint); + +#endif diff --git a/include/usbdcore_ep0.h b/include/usbdcore_ep0.h new file mode 100644 index 0000000..3bec106 --- /dev/null +++ b/include/usbdcore_ep0.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usbd/ep0.c + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __USBDCORE_EP0_H__ +#define __USBDCORE_EP0_H__ + + +int ep0_recv_setup (struct urb *urb); + + +#endif diff --git a/include/usbdcore_omap1510.h b/include/usbdcore_omap1510.h new file mode 100644 index 0000000..6ea3331 --- /dev/null +++ b/include/usbdcore_omap1510.h @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usb/device/bi/omap.h + * Register definitions for TI OMAP1510 USB bus interface driver + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __USBDCORE_OMAP1510_H__ +#define __USBDCORE_OMAP1510_H__ + + +/* + * 13.2 MPU Register Map + */ + +/* Table 13-1. USB Function Module Registers (endpoint) */ +#define UDC_BASE 0xFFFB4000 +#define UDC_OFFSET(offset) (UDC_BASE + (offset)) +#define UDC_REV UDC_OFFSET(0x0) /* Revision */ +#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */ +#define UDC_DATA UDC_OFFSET(0x08) /* Data */ +#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */ +#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */ +#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */ +#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */ +#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */ +#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */ +#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */ +#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */ +#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */ +#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */ +#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */ +#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */ + +/* IRQ_EN register fields */ +#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */ +#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */ +#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */ +#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */ +#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */ + +/* IRQ_SRC register fields */ +#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */ +#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */ +#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */ +#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */ +#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */ +#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */ +#define UDC_DS_Chg (1 << 3) /* Device state changed */ +#define UDC_Setup (1 << 2) /* Setup transaction */ +#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */ +#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */ + +/* DEVSTAT register fields, 14.2.9 */ +#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */ +#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */ +#define UDC_SUS (1 << 4) /* Suspended state */ +#define UDC_CFG (1 << 3) /* Configured state */ +#define UDC_ADD (1 << 2) /* Addressed state */ +#define UDC_DEF (1 << 1) /* Default state */ +#define UDC_ATT (1 << 0) /* Attached state */ + +/* SYSCON1 register fields */ +#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */ +#define UDC_Nak_En (1 << 4) /* NAK enable */ +#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */ +#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */ +#define UDC_Pullup_En (1 << 0) /* External pullup enabled */ + +/* SYSCON2 register fields */ +#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */ +#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */ +#define UDC_Dev_Cfg (1 << 3) /* Device configured */ +#define UDC_Clr_Cfg (1 << 2) /* Clear configured */ + +/* + * Select and enable endpoints + */ + +/* Table 13-1. USB Function Module Registers (endpoint configuration) */ +#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */ +#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */ +#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */ +#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4) +#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */ +#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4) + +/* EP_NUM register fields */ +#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */ +#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */ +#define UDC_EP_Dir (1 << 4) /* Endpoint direction */ + +/* CTRL register fields */ +#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */ +#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */ +#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */ +#define UDC_Clr_EP (1 << 1) /* Clear endpoint */ +#define UDC_Reset_EP (1 << 0) /* Reset endpoint */ + +/* STAT_FLG register fields */ +#define UDC_Miss_In (1 << 14) +#define UDC_Data_Flush (1 << 13) +#define UDC_ISO_Err (1 << 12) +#define UDC_ISO_FIFO_Empty (1 << 9) +#define UDC_ISO_FIFO_Full (1 << 8) +#define UDC_EP_Halted (1 << 6) +#define UDC_STALL (1 << 5) +#define UDC_NAK (1 << 4) +#define UDC_ACK (1 << 3) +#define UDC_FIFO_En (1 << 2) +#define UDC_Non_ISO_FIFO_Empty (1 << 1) +#define UDC_Non_ISO_FIFO_Full (1 << 0) + +/* EPn_RX register fields */ +#define UDC_EPn_RX_Valid (1 << 15) /* valid */ +#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */ +#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */ + +/* EPn_TX register fields */ +#define UDC_EPn_TX_Valid (1 << 15) /* valid */ +#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */ +#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */ + +#define EP0_PACKETSIZE 0x40 + +/* physical to logical endpoint mapping + * Physical endpoints are an index into device->bus->endpoint_array. + * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in + * the USB specification. + * + * physical ep logical ep direction endpoint_address + * 0 0 IN and OUT 0x00 + * 1 to 15 1 to 15 OUT 0x01 to 0x0f + * 16 to 30 1 to 15 IN 0x81 to 0x8f + */ +#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80)) +#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a)) + +/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */ +#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17) + +/* Other registers (may be) related to USB */ + +#define CLOCK_CTRL (0xFFFE0830) +#define APLL_CTRL (0xFFFE084C) +#define DPLL_CTRL (0xFFFE083C) +#define SOFT_REQ (0xFFFE0834) +#define STATUS_REQ (0xFFFE0840) + +/* FUNC_MUX_CTRL_0 bits related to USB */ +#define UDC_VBUS_CTRL (1 << 19) +#define UDC_VBUS_MODE (1 << 18) + + +void omap1510_udc_irq(void); +void omap1510_udc_noniso_irq(void); + + +/* Higher level functions for abstracting away from specific device */ +void udc_endpoint_write(struct usb_endpoint_instance *endpoint); + +int udc_init (void); + +void udc_enable(struct usb_device_instance *device); +void udc_disable(void); + +void udc_connect(void); +void udc_disconnect(void); + +void udc_startup_events(struct usb_device_instance *device); +void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint); + +#endif diff --git a/include/usbdescriptors.h b/include/usbdescriptors.h new file mode 100644 index 0000000..2d9f739 --- /dev/null +++ b/include/usbdescriptors.h @@ -0,0 +1,497 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usbd/usb-function.h - USB Function + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +/* USB Descriptors - Create a complete description of all of the + * function driver capabilities. These map directly to the USB descriptors. + * + * This heirarchy is created by the functions drivers and is passed to the + * usb-device driver when the function driver is registered. + * + * device + * configuration + * interface + * alternate + * class + * class + * alternate + * endpoint + * endpoint + * interface + * alternate + * endpoint + * endpoint + * configuration + * interface + * alternate + * endpoint + * endpoint + * + * + * The configuration structures refer to the USB Configurations that will be + * made available to a USB HOST during the enumeration process. + * + * The USB HOST will select a configuration and optionally an interface with + * the usb set configuration and set interface commands. + * + * The selected interface (or the default interface if not specifically + * selected) will define the list of endpoints that will be used. + * + * The configuration and interfaces are stored in an array that is indexed + * by the specified configuratin or interface number minus one. + * + * A configuration number of zero is used to specify a return to the unconfigured + * state. + * + */ + + +#ifndef __USBDESCRIPTORS_H__ +#define __USBDESCRIPTORS_H__ + +#include + +/* + * communications class types + * + * c.f. CDC USB Class Definitions for Communications Devices + * c.f. WMCD USB CDC Subclass Specification for Wireless Mobile Communications Devices + * + */ + +#define CLASS_BCD_VERSION 0x0110 + +/* c.f. CDC 4.1 Table 14 */ +#define COMMUNICATIONS_DEVICE_CLASS 0x02 + +/* c.f. CDC 4.2 Table 15 */ +#define COMMUNICATIONS_INTERFACE_CLASS 0x02 + +/* c.f. CDC 4.3 Table 16 */ +#define COMMUNICATIONS_NO_SUBCLASS 0x00 +#define COMMUNICATIONS_DLCM_SUBCLASS 0x01 +#define COMMUNICATIONS_ACM_SUBCLASS 0x02 +#define COMMUNICATIONS_TCM_SUBCLASS 0x03 +#define COMMUNICATIONS_MCCM_SUBCLASS 0x04 +#define COMMUNICATIONS_CCM_SUBCLASS 0x05 +#define COMMUNICATIONS_ENCM_SUBCLASS 0x06 +#define COMMUNICATIONS_ANCM_SUBCLASS 0x07 + +/* c.f. WMCD 5.1 */ +#define COMMUNICATIONS_WHCM_SUBCLASS 0x08 +#define COMMUNICATIONS_DMM_SUBCLASS 0x09 +#define COMMUNICATIONS_MDLM_SUBCLASS 0x0a +#define COMMUNICATIONS_OBEX_SUBCLASS 0x0b + +/* c.f. CDC 4.6 Table 18 */ +#define DATA_INTERFACE_CLASS 0x0a + +/* c.f. CDC 4.7 Table 19 */ +#define COMMUNICATIONS_NO_PROTOCOL 0x00 + + +/* c.f. CDC 5.2.3 Table 24 */ +#define CS_INTERFACE 0x24 +#define CS_ENDPOINT 0x25 + +/* + * bDescriptorSubtypes + * + * c.f. CDC 5.2.3 Table 25 + * c.f. WMCD 5.3 Table 5.3 + */ + +#define USB_ST_HEADER 0x00 +#define USB_ST_CMF 0x01 +#define USB_ST_ACMF 0x02 +#define USB_ST_DLMF 0x03 +#define USB_ST_TRF 0x04 +#define USB_ST_TCLF 0x05 +#define USB_ST_UF 0x06 +#define USB_ST_CSF 0x07 +#define USB_ST_TOMF 0x08 +#define USB_ST_USBTF 0x09 +#define USB_ST_NCT 0x0a +#define USB_ST_PUF 0x0b +#define USB_ST_EUF 0x0c +#define USB_ST_MCMF 0x0d +#define USB_ST_CCMF 0x0e +#define USB_ST_ENF 0x0f +#define USB_ST_ATMNF 0x10 + +#define USB_ST_WHCM 0x11 +#define USB_ST_MDLM 0x12 +#define USB_ST_MDLMD 0x13 +#define USB_ST_DMM 0x14 +#define USB_ST_OBEX 0x15 +#define USB_ST_CS 0x16 +#define USB_ST_CSD 0x17 +#define USB_ST_TCM 0x18 + +/* endpoint modifiers + * static struct usb_endpoint_description function_default_A_1[] = { + * + * {this_endpoint: 0, attributes: CONTROL, max_size: 8, polling_interval: 0 }, + * {this_endpoint: 1, attributes: BULK, max_size: 64, polling_interval: 0, direction: IN}, + * {this_endpoint: 2, attributes: BULK, max_size: 64, polling_interval: 0, direction: OUT}, + * {this_endpoint: 3, attributes: INTERRUPT, max_size: 8, polling_interval: 0}, + * + * + */ +#define OUT 0x00 +#define IN 0x80 + +#define CONTROL 0x00 +#define ISOCHRONOUS 0x01 +#define BULK 0x02 +#define INTERRUPT 0x03 + + +/* configuration modifiers + */ +#define BMATTRIBUTE_RESERVED 0x80 +#define BMATTRIBUTE_SELF_POWERED 0x40 + +/* + * standard usb descriptor structures + */ + +struct usb_endpoint_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x5 */ + u8 bEndpointAddress; + u8 bmAttributes; + u16 wMaxPacketSize; + u8 bInterval; +} __attribute__ ((packed)); + +struct usb_interface_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x04 */ + u8 bInterfaceNumber; + u8 bAlternateSetting; + u8 bNumEndpoints; + u8 bInterfaceClass; + u8 bInterfaceSubClass; + u8 bInterfaceProtocol; + u8 iInterface; +} __attribute__ ((packed)); + +struct usb_configuration_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x2 */ + u16 wTotalLength; + u8 bNumInterfaces; + u8 bConfigurationValue; + u8 iConfiguration; + u8 bmAttributes; + u8 bMaxPower; +} __attribute__ ((packed)); + +struct usb_device_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x01 */ + u16 bcdUSB; + u8 bDeviceClass; + u8 bDeviceSubClass; + u8 bDeviceProtocol; + u8 bMaxPacketSize0; + u16 idVendor; + u16 idProduct; + u16 bcdDevice; + u8 iManufacturer; + u8 iProduct; + u8 iSerialNumber; + u8 bNumConfigurations; +} __attribute__ ((packed)); + +struct usb_string_descriptor { + u8 bLength; + u8 bDescriptorType; /* 0x03 */ + u16 wData[0]; +} __attribute__ ((packed)); + +struct usb_generic_descriptor { + u8 bLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; +} __attribute__ ((packed)); + + +/* + * communications class descriptor structures + * + * c.f. CDC 5.2 Table 25c + */ + +struct usb_class_function_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; +} __attribute__ ((packed)); + +struct usb_class_function_descriptor_generic { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_header_function_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x00 */ + u16 bcdCDC; +} __attribute__ ((packed)); + +struct usb_class_call_management_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x01 */ + u8 bmCapabilities; + u8 bDataInterface; +} __attribute__ ((packed)); + +struct usb_class_abstract_control_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x02 */ + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_direct_line_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x03 */ +} __attribute__ ((packed)); + +struct usb_class_telephone_ringer_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x04 */ + u8 bRingerVolSeps; + u8 bNumRingerPatterns; +} __attribute__ ((packed)); + +struct usb_class_telephone_call_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x05 */ + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_union_function_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x06 */ + u8 bMasterInterface; + u8 bSlaveInterface0[0]; +} __attribute__ ((packed)); + +struct usb_class_country_selection_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x07 */ + u8 iCountryCodeRelDate; + u16 wCountryCode0[0]; +} __attribute__ ((packed)); + + +struct usb_class_telephone_operational_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x08 */ + u8 bmCapabilities; +} __attribute__ ((packed)); + + +struct usb_class_usb_terminal_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x09 */ + u8 bEntityId; + u8 bInterfaceNo; + u8 bOutInterfaceNo; + u8 bmOptions; + u8 bChild0[0]; +} __attribute__ ((packed)); + +struct usb_class_network_channel_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0a */ + u8 bEntityId; + u8 iName; + u8 bChannelIndex; + u8 bPhysicalInterface; +} __attribute__ ((packed)); + +struct usb_class_protocol_unit_function_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0b */ + u8 bEntityId; + u8 bProtocol; + u8 bChild0[0]; +} __attribute__ ((packed)); + +struct usb_class_extension_unit_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0c */ + u8 bEntityId; + u8 bExtensionCode; + u8 iName; + u8 bChild0[0]; +} __attribute__ ((packed)); + +struct usb_class_multi_channel_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0d */ + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_capi_control_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0e */ + u8 bmCapabilities; +} __attribute__ ((packed)); + +struct usb_class_ethernet_networking_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x0f */ + u8 iMACAddress; + u32 bmEthernetStatistics; + u16 wMaxSegmentSize; + u16 wNumberMCFilters; + u8 bNumberPowerFilters; +} __attribute__ ((packed)); + +struct usb_class_atm_networking_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x10 */ + u8 iEndSystermIdentifier; + u8 bmDataCapabilities; + u8 bmATMDeviceStatistics; + u16 wType2MaxSegmentSize; + u16 wType3MaxSegmentSize; + u16 wMaxVC; +} __attribute__ ((packed)); + + +struct usb_class_mdlm_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x12 */ + u16 bcdVersion; + u8 bGUID[16]; +} __attribute__ ((packed)); + +struct usb_class_mdlmd_descriptor { + u8 bFunctionLength; + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x13 */ + u8 bGuidDescriptorType; + u8 bDetailData[0]; + +} __attribute__ ((packed)); + +/* + * HID class descriptor structures + * + * c.f. HID 6.2.1 + */ + +struct usb_class_hid_descriptor { + u8 bLength; + u8 bDescriptorType; + u16 bcdCDC; + u8 bCountryCode; + u8 bNumDescriptors; /* 0x01 */ + u8 bDescriptorType0; + u16 wDescriptorLength0; + /* optional descriptors are not supported. */ +} __attribute__((packed)); + +struct usb_class_report_descriptor { + u8 bLength; /* dummy */ + u8 bDescriptorType; + u16 wLength; + u8 bData[0]; +} __attribute__((packed)); + +/* + * descriptor union structures + */ + +struct usb_descriptor { + union { + struct usb_generic_descriptor generic; + struct usb_endpoint_descriptor endpoint; + struct usb_interface_descriptor interface; + struct usb_configuration_descriptor configuration; + struct usb_device_descriptor device; + struct usb_string_descriptor string; + } descriptor; + +} __attribute__ ((packed)); + +struct usb_class_descriptor { + union { + struct usb_class_function_descriptor function; + struct usb_class_function_descriptor_generic generic; + struct usb_class_header_function_descriptor header_function; + struct usb_class_call_management_descriptor call_management; + struct usb_class_abstract_control_descriptor abstract_control; + struct usb_class_direct_line_descriptor direct_line; + struct usb_class_telephone_ringer_descriptor telephone_ringer; + struct usb_class_telephone_operational_descriptor telephone_operational; + struct usb_class_telephone_call_descriptor telephone_call; + struct usb_class_union_function_descriptor union_function; + struct usb_class_country_selection_descriptor country_selection; + struct usb_class_usb_terminal_descriptor usb_terminal; + struct usb_class_network_channel_descriptor network_channel; + struct usb_class_extension_unit_descriptor extension_unit; + struct usb_class_multi_channel_descriptor multi_channel; + struct usb_class_capi_control_descriptor capi_control; + struct usb_class_ethernet_networking_descriptor ethernet_networking; + struct usb_class_atm_networking_descriptor atm_networking; + struct usb_class_mdlm_descriptor mobile_direct; + struct usb_class_mdlmd_descriptor mobile_direct_detail; + struct usb_class_hid_descriptor hid; + } descriptor; + +} __attribute__ ((packed)); + +#endif diff --git a/include/version.h b/include/version.h new file mode 100644 index 0000000..4f8b498 --- /dev/null +++ b/include/version.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __VERSION_H__ +#define __VERSION_H__ + +#define U_BOOT_VERSION "U-Boot 1.1.4" + +#endif /* __VERSION_H__ */ diff --git a/include/vfd_logo.h b/include/vfd_logo.h new file mode 100644 index 0000000..c41867a --- /dev/null +++ b/include/vfd_logo.h @@ -0,0 +1,1032 @@ +/* + * Automatically generated by "tools/bmp_logo" + * + * DO NOT EDIT + * + */ + + +#ifndef __VFD_LOGO_H__ +#define __VFD_LOGO_H__ + +#define VFD_LOGO_WIDTH 112 +#define VFD_LOGO_HEIGHT 72 +#define VFD_LOGO_COLORS 0 +#define VFD_LOGO_OFFSET 0 + + +unsigned char vfd_test_logo_bitmap[] = { + 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, + 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDF, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xFD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, + 0xDD, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, + 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDF, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xFD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, + 0xDD, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, + 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDF, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xFD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, + 0xDD, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, + 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDF, 0xDD, 0xDD, 0xFF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDF, 0xFD, 0xDD, 0xDF, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, + 0xDD, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, + 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, + 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, + 0xDD, 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, + 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, + 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, +}; + +unsigned char vfd_remote_logo_bitmap[] = { + 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, + 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, + 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x9F, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xF9, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0xF9, 0x99, 0x9F, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, + 0x99, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, + 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, + 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x9F, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xF9, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0xF9, 0x99, 0x9F, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, + 0x99, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, + 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, + 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x9F, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xF9, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0xF9, 0x99, 0x9F, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, + 0x99, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, + 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, + 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x9F, 0x99, 0x99, 0xFF, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xF9, + 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, + 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x9F, 0xF9, 0x99, 0x9F, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, + 0x99, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, + 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, + 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, + 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, + 0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, + 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, + 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, + 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, + 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, +}; + +#endif /* __VFD_LOGO_H__ */ diff --git a/include/video.h b/include/video.h new file mode 100644 index 0000000..efcc682 --- /dev/null +++ b/include/video.h @@ -0,0 +1,19 @@ +/* +** MPC823 Video Controller +** ======================= +** (C) 2000 by Paolo Scaffardi (arsenio@tin.it) +** AIRVENT SAM s.p.a - RIMINI(ITALY) +** +*/ + +#ifndef _VIDEO_H_ +#define _VIDEO_H_ + +/* Video functions */ + +int video_init (void *videobase); +void video_putc (const char c); +void video_puts (const char *s); +void video_printf (const char *fmt, ...); + +#endif diff --git a/include/video_ad7176.h b/include/video_ad7176.h new file mode 100644 index 0000000..92ddcb7 --- /dev/null +++ b/include/video_ad7176.h @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _VIDEO_AD7176_H_ +#define _VIDEO_AD7176_H_ + +#define VIDEO_ENCODER_NAME "Analog Devices AD7176" + +#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */ +#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ + +#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ +#undef VIDEO_MODE_RGB +#define VIDEO_MODE_BPP 16 + +#ifdef VIDEO_MODE_PAL +#define VIDEO_ACTIVE_COLS 720 +#define VIDEO_ACTIVE_ROWS 576 +#define VIDEO_VISIBLE_COLS 640 +#define VIDEO_VISIBLE_ROWS 480 +#endif + +#ifdef VIDEO_MODE_NTSC +#define VIDEO_ACTIVE_COLS 720 +#define VIDEO_ACTIVE_ROWS 525 +#define VIDEO_VISIBLE_COLS 640 +#define VIDEO_VISIBLE_ROWS 400 +#endif + +static unsigned char video_encoder_data[] = { +#ifdef VIDEO_MODE_NTSC + 0x04, /* Mode Register 0 */ +#ifdef VIDEO_DEBUG_COLORBARS + 0x82, +#else + 0x02, /* Mode Register 1 */ +#endif /* VIDEO_DEBUG_COLORBARS */ + 0x16, /* Subcarrier Freq 0 */ + 0x7c, /* Subcarrier Freq 1 */ + 0xf0, /* Subcarrier Freq 2 */ + 0x21, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x02, /* Timing Register 0 */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ + 0x08, /* Mode Register 2 */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x00 /* Mode Register 3 */ + +#endif /* VIDEO_MODE_NTSC */ + +#ifdef VIDEO_MODE_PAL + 0x05, /* Mode Register 0 */ +#ifdef VIDEO_DEBUG_COLORBARS + 0x82, +#else + 0x02, /* Mode Register 1 (2) */ +#endif /* VIDEO_DEBUG_COLORBARS */ + 0xcb, /* Subcarrier Freq 0 */ + 0x8a, /* Subcarrier Freq 1 */ + 0x09, /* Subcarrier Freq 2 */ + 0x2a, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x0a, /* Timing Register 0 (a) */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ + 0x08, /* Mode Register 2 (8) */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x00 /* Mode Register 3 */ +#endif /* VIDEO_MODE_PAL */ +} ; + +#endif /* _VIDEO_AD7176_H_ */ diff --git a/include/video_ad7177.h b/include/video_ad7177.h new file mode 100644 index 0000000..de3863d --- /dev/null +++ b/include/video_ad7177.h @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _VIDEO_AD7177_H_ +#define _VIDEO_AD7177_H_ + +/* #define VIDEO_DEBUG_DISABLE_COLORS 0 */ + +#define VIDEO_ENCODER_NAME "Analog Devices AD7177" + +#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */ +#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ + +#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ +#undef VIDEO_MODE_RGB +#define VIDEO_MODE_BPP 16 + +#ifdef VIDEO_MODE_PAL +#define VIDEO_ACTIVE_COLS 720 +#define VIDEO_ACTIVE_ROWS 576 +#define VIDEO_VISIBLE_COLS 640 +#define VIDEO_VISIBLE_ROWS 480 +#endif + +#ifdef VIDEO_MODE_NTSC +#define VIDEO_ACTIVE_COLS 720 +#define VIDEO_ACTIVE_ROWS 525 +#define VIDEO_VISIBLE_COLS 640 +#define VIDEO_VISIBLE_ROWS 400 +#endif + +static unsigned char + video_encoder_data[] = { +#ifdef VIDEO_MODE_NTSC + 0x04, /* Mode Register 0 */ +#ifdef VIDEO_DEBUG_COLORBARS + 0xc2, +#else + 0x42, /* Mode Register 1 */ +#endif /* VIDEO_DEBUG_COLORBARS */ + 0x16, /* Subcarrier Freq 0 */ + 0x7c, /* Subcarrier Freq 1 */ + 0xf0, /* Subcarrier Freq 2 */ + 0x21, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x02, /* Timing Register 0 */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ + 0x08, /* Mode Register 2 */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x08, /* Mode Register 3 */ + +#endif /* VIDEO_MODE_NTSC */ + +#ifdef VIDEO_MODE_PAL +#ifdef VIDEO_MODE_RGB_OUT + + 0x69, /* Mode Register 0 */ +#ifdef VIDEO_DEBUG_COLORBARS + 0xc0, /* Mode Register 1 (c0) */ +#else + 0x40, /* Mode Register 1 (c0) */ +#endif /* VIDEO_DEBUG_COLORBARS */ + 0xcb, /* Subcarrier Freq 0 */ + 0x8a, /* Subcarrier Freq 1 */ + 0x09, /* Subcarrier Freq 2 */ + 0x2a, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x02, /* Timing Register 0 */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ + 0x28, /* Mode Register 2 */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x08, /* Mode Register 3 */ + +#else /* ! VIDEO_MODE_RGB_OUT */ + + 0x09, /* Mode Register 0 (was 01) */ +#ifdef VIDEO_DEBUG_COLORBARS + 0xd8, /* */ +#else + 0x59, /* Mode Register 1 (was 58) */ +#endif /* VIDEO_DEBUG_COLORBARS */ + 0xcb, /* Subcarrier Freq 0 */ + 0x8a, /* Subcarrier Freq 1 */ + 0x09, /* Subcarrier Freq 2 */ + 0x2a, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x02, /* Timing Register 0 (was a) */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ +#ifdef VIDEO_DEBUG_LOWPOWER +#ifdef VIDEO_DEBUG_DISABLE_COLORS + 0x98, /* Mode Register 2 */ +#else + 0x88, /* Mode Register 2 */ +#endif /* VIDEO_DEBUG_DISABLE_COLORS */ +#else /* ! VIDEO_DEBUG_LOWPOWER */ +#ifdef VIDEO_DEBUG_DISABLE_COLORS + 0x18, /* Mode Register 2 */ +#else + 0x08, /* Mode Register 2 */ +#endif /* VIDEO_DEBUG_DISABLE_COLORS */ +#endif /* VIDEO_DEBUG_LOWPOWER */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x08 /* Mode Register 3 */ +#endif /* VIDEO_MODE_RGB_OUT */ +#endif /* VIDEO_MODE_PAL */ + } ; + +#endif /* _VIDEO_AD7177_H_ */ diff --git a/include/video_ad7179.h b/include/video_ad7179.h new file mode 100644 index 0000000..6a1ec86 --- /dev/null +++ b/include/video_ad7179.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2003 Wolfgang Grandegger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _VIDEO_AD7179_H_ +#define _VIDEO_AD7179_H_ + +/* + * The video encoder data are board specific now! + */ + +#if defined(CONFIG_RRVISION) +#include "../board/RRvision/video_ad7179.h" +#else +#error "Please provide a board-specific video_ad7179.h" +#endif + +#endif /* _VIDEO_AD7179_H_ */ diff --git a/include/video_easylogo.h b/include/video_easylogo.h new file mode 100644 index 0000000..1e00818 --- /dev/null +++ b/include/video_easylogo.h @@ -0,0 +1,26 @@ +/* +** video easylogo +** ============== +** (C) 2000 by Paolo Scaffardi (arsenio@tin.it) +** AIRVENT SAM s.p.a - RIMINI(ITALY) +** +** This utility is still under construction! +*/ + +#ifndef _EASYLOGO_H_ +#define _EASYLOGO_H_ + +#if 0 +#define ENABLE_ASCII_BANNERS +#endif + +typedef struct { + unsigned char *data; + int width; + int height; + int bpp; + int pixel_size; + int size; +} fastimage_t ; + +#endif /* _EASYLOGO_H_ */ diff --git a/include/video_fb.h b/include/video_fb.h new file mode 100644 index 0000000..9825f0c --- /dev/null +++ b/include/video_fb.h @@ -0,0 +1,115 @@ + /* + * (C) Copyright 1997-2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * smiLynxEM.h + * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator + * + * + * modification history + * -------------------- + * 04-18-2002 Rewritten for U-Boot . + */ + +#ifndef _VIDEO_FB_H_ +#define _VIDEO_FB_H_ + +#define CONSOLE_BG_COL 0x00 +#define CONSOLE_FG_COL 0xa0 + +/* + * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT + */ +#define GDF__8BIT_INDEX 0 +#define GDF_15BIT_555RGB 1 +#define GDF_16BIT_565RGB 2 +#define GDF_32BIT_X888RGB 3 +#define GDF_24BIT_888RGB 4 +#define GDF__8BIT_332RGB 5 + +/******************************************************************************/ +/* Export Graphic Driver Control */ +/******************************************************************************/ + +typedef struct { + unsigned int isaBase; + unsigned int pciBase; + unsigned int dprBase; + unsigned int vprBase; + unsigned int cprBase; + unsigned int frameAdrs; + unsigned int memSize; + unsigned int mode; + unsigned int gdfIndex; + unsigned int gdfBytesPP; + unsigned int fg; + unsigned int bg; + unsigned int plnSizeX; + unsigned int plnSizeY; + unsigned int winSizeX; + unsigned int winSizeY; + char modeIdent[80]; +} GraphicDevice; + + +/******************************************************************************/ +/* Export Graphic Functions */ +/******************************************************************************/ + +void *video_hw_init (void); /* returns GraphicDevice struct or NULL */ + +#ifdef VIDEO_HW_BITBLT +void video_hw_bitblt ( + unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ); +#endif + +#ifdef VIDEO_HW_RECTFILL +void video_hw_rectfill ( + unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ); +#endif + +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ); +#ifdef CONFIG_VIDEO_HW_CURSOR +void video_set_hw_cursor(int x, int y); /* x y in pixel */ +void video_init_hw_cursor(int font_width, int font_height); +#endif + +#endif /*_VIDEO_FB_H_ */ diff --git a/include/video_font.h b/include/video_font.h new file mode 100644 index 0000000..706e185 --- /dev/null +++ b/include/video_font.h @@ -0,0 +1,4644 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _VIDEO_FONT_ +#define _VIDEO_FONT_ + +#define VIDEO_FONT_CHARS 256 +#define VIDEO_FONT_WIDTH 8 +#define VIDEO_FONT_HEIGHT 16 +#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT) + +static unsigned char video_fontdata[VIDEO_FONT_SIZE] = { + + /* 0 0x00 '^@' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 1 0x01 '^A' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x81, /* 10000001 */ + 0xa5, /* 10100101 */ + 0x81, /* 10000001 */ + 0x81, /* 10000001 */ + 0xbd, /* 10111101 */ + 0x99, /* 10011001 */ + 0x81, /* 10000001 */ + 0x81, /* 10000001 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 2 0x02 '^B' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xff, /* 11111111 */ + 0xdb, /* 11011011 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xc3, /* 11000011 */ + 0xe7, /* 11100111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 3 0x03 '^C' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0x10, /* 00010000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 4 0x04 '^D' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x7c, /* 01111100 */ + 0xfe, /* 11111110 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0x10, /* 00010000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 5 0x05 '^E' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0xe7, /* 11100111 */ + 0xe7, /* 11100111 */ + 0xe7, /* 11100111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 6 0x06 '^F' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 7 0x07 '^G' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 8 0x08 '^H' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xe7, /* 11100111 */ + 0xc3, /* 11000011 */ + 0xc3, /* 11000011 */ + 0xe7, /* 11100111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 9 0x09 '^I' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x42, /* 01000010 */ + 0x42, /* 01000010 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 10 0x0a '^J' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xc3, /* 11000011 */ + 0x99, /* 10011001 */ + 0xbd, /* 10111101 */ + 0xbd, /* 10111101 */ + 0x99, /* 10011001 */ + 0xc3, /* 11000011 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 11 0x0b '^K' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1e, /* 00011110 */ + 0x0e, /* 00001110 */ + 0x1a, /* 00011010 */ + 0x32, /* 00110010 */ + 0x78, /* 01111000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 12 0x0c '^L' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 13 0x0d '^M' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3f, /* 00111111 */ + 0x33, /* 00110011 */ + 0x3f, /* 00111111 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x70, /* 01110000 */ + 0xf0, /* 11110000 */ + 0xe0, /* 11100000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 14 0x0e '^N' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7f, /* 01111111 */ + 0x63, /* 01100011 */ + 0x7f, /* 01111111 */ + 0x63, /* 01100011 */ + 0x63, /* 01100011 */ + 0x63, /* 01100011 */ + 0x63, /* 01100011 */ + 0x67, /* 01100111 */ + 0xe7, /* 11100111 */ + 0xe6, /* 11100110 */ + 0xc0, /* 11000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 15 0x0f '^O' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xdb, /* 11011011 */ + 0x3c, /* 00111100 */ + 0xe7, /* 11100111 */ + 0x3c, /* 00111100 */ + 0xdb, /* 11011011 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 16 0x10 '^P' */ + 0x00, /* 00000000 */ + 0x80, /* 10000000 */ + 0xc0, /* 11000000 */ + 0xe0, /* 11100000 */ + 0xf0, /* 11110000 */ + 0xf8, /* 11111000 */ + 0xfe, /* 11111110 */ + 0xf8, /* 11111000 */ + 0xf0, /* 11110000 */ + 0xe0, /* 11100000 */ + 0xc0, /* 11000000 */ + 0x80, /* 10000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 17 0x11 '^Q' */ + 0x00, /* 00000000 */ + 0x02, /* 00000010 */ + 0x06, /* 00000110 */ + 0x0e, /* 00001110 */ + 0x1e, /* 00011110 */ + 0x3e, /* 00111110 */ + 0xfe, /* 11111110 */ + 0x3e, /* 00111110 */ + 0x1e, /* 00011110 */ + 0x0e, /* 00001110 */ + 0x06, /* 00000110 */ + 0x02, /* 00000010 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 18 0x12 '^R' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 19 0x13 '^S' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 20 0x14 '^T' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7f, /* 01111111 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0x7b, /* 01111011 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 21 0x15 '^U' */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x60, /* 01100000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x0c, /* 00001100 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 22 0x16 '^V' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 23 0x17 '^W' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 24 0x18 '^X' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 25 0x19 '^Y' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 26 0x1a '^Z' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0xfe, /* 11111110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 27 0x1b '^[' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xfe, /* 11111110 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 28 0x1c '^\' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 29 0x1d '^]' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x28, /* 00101000 */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x28, /* 00101000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 30 0x1e '^^' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x38, /* 00111000 */ + 0x7c, /* 01111100 */ + 0x7c, /* 01111100 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 31 0x1f '^_' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0x7c, /* 01111100 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0x38, /* 00111000 */ + 0x10, /* 00010000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 32 0x20 ' ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 33 0x21 '!' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 34 0x22 '"' */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x24, /* 00100100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 35 0x23 '#' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 36 0x24 '$' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc2, /* 11000010 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x86, /* 10000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 37 0x25 '%' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc2, /* 11000010 */ + 0xc6, /* 11000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc6, /* 11000110 */ + 0x86, /* 10000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 38 0x26 '&' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 39 0x27 ''' */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 40 0x28 '(' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 41 0x29 ')' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 42 0x2a '*' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0xff, /* 11111111 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 43 0x2b '+' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 44 0x2c ',' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 45 0x2d '-' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 46 0x2e '.' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 47 0x2f '/' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x02, /* 00000010 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0x80, /* 10000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 48 0x30 '0' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 49 0x31 '1' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x38, /* 00111000 */ + 0x78, /* 01111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 50 0x32 '2' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 51 0x33 '3' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x3c, /* 00111100 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 52 0x34 '4' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x0c, /* 00001100 */ + 0x1c, /* 00011100 */ + 0x3c, /* 00111100 */ + 0x6c, /* 01101100 */ + 0xcc, /* 11001100 */ + 0xfe, /* 11111110 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x1e, /* 00011110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 53 0x35 '5' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xfc, /* 11111100 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 54 0x36 '6' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xfc, /* 11111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 55 0x37 '7' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 56 0x38 '8' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 57 0x39 '9' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7e, /* 01111110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 58 0x3a ':' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 59 0x3b ';' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 60 0x3c '<' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 61 0x3d '=' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 62 0x3e '>' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 63 0x3f '?' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 64 0x40 '@' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xde, /* 11011110 */ + 0xde, /* 11011110 */ + 0xde, /* 11011110 */ + 0xdc, /* 11011100 */ + 0xc0, /* 11000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 65 0x41 'A' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 66 0x42 'B' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfc, /* 11111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xfc, /* 11111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 67 0x43 'C' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0xc2, /* 11000010 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc2, /* 11000010 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 68 0x44 'D' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xf8, /* 11111000 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 69 0x45 'E' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x66, /* 01100110 */ + 0x62, /* 01100010 */ + 0x68, /* 01101000 */ + 0x78, /* 01111000 */ + 0x68, /* 01101000 */ + 0x60, /* 01100000 */ + 0x62, /* 01100010 */ + 0x66, /* 01100110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 70 0x46 'F' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x66, /* 01100110 */ + 0x62, /* 01100010 */ + 0x68, /* 01101000 */ + 0x78, /* 01111000 */ + 0x68, /* 01101000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 71 0x47 'G' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0xc2, /* 11000010 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xde, /* 11011110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x66, /* 01100110 */ + 0x3a, /* 00111010 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 72 0x48 'H' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 73 0x49 'I' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 74 0x4a 'J' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1e, /* 00011110 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 75 0x4b 'K' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xe6, /* 11100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0x78, /* 01111000 */ + 0x78, /* 01111000 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 76 0x4c 'L' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xf0, /* 11110000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x62, /* 01100010 */ + 0x66, /* 01100110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 77 0x4d 'M' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xee, /* 11101110 */ + 0xfe, /* 11111110 */ + 0xfe, /* 11111110 */ + 0xd6, /* 11010110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 78 0x4e 'N' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xe6, /* 11100110 */ + 0xf6, /* 11110110 */ + 0xfe, /* 11111110 */ + 0xde, /* 11011110 */ + 0xce, /* 11001110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 79 0x4f 'O' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 80 0x50 'P' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfc, /* 11111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 81 0x51 'Q' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xde, /* 11011110 */ + 0x7c, /* 01111100 */ + 0x0c, /* 00001100 */ + 0x0e, /* 00001110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 82 0x52 'R' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfc, /* 11111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 83 0x53 'S' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x60, /* 01100000 */ + 0x38, /* 00111000 */ + 0x0c, /* 00001100 */ + 0x06, /* 00000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 84 0x54 'T' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x5a, /* 01011010 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 85 0x55 'U' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 86 0x56 'V' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x10, /* 00010000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 87 0x57 'W' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xfe, /* 11111110 */ + 0xee, /* 11101110 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 88 0x58 'X' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x7c, /* 01111100 */ + 0x38, /* 00111000 */ + 0x38, /* 00111000 */ + 0x7c, /* 01111100 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 89 0x59 'Y' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 90 0x5a 'Z' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x86, /* 10000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc2, /* 11000010 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 91 0x5b '[' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 92 0x5c '\' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x80, /* 10000000 */ + 0xc0, /* 11000000 */ + 0xe0, /* 11100000 */ + 0x70, /* 01110000 */ + 0x38, /* 00111000 */ + 0x1c, /* 00011100 */ + 0x0e, /* 00001110 */ + 0x06, /* 00000110 */ + 0x02, /* 00000010 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 93 0x5d ']' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 94 0x5e '^' */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 95 0x5f '_' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 96 0x60 '`' */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 97 0x61 'a' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 98 0x62 'b' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xe0, /* 11100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x78, /* 01111000 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 99 0x63 'c' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 100 0x64 'd' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1c, /* 00011100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x3c, /* 00111100 */ + 0x6c, /* 01101100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 101 0x65 'e' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 102 0x66 'f' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1c, /* 00011100 */ + 0x36, /* 00110110 */ + 0x32, /* 00110010 */ + 0x30, /* 00110000 */ + 0x78, /* 01111000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 103 0x67 'g' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x7c, /* 01111100 */ + 0x0c, /* 00001100 */ + 0xcc, /* 11001100 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + + /* 104 0x68 'h' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xe0, /* 11100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x6c, /* 01101100 */ + 0x76, /* 01110110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 105 0x69 'i' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 106 0x6a 'j' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + 0x0e, /* 00001110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + + /* 107 0x6b 'k' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xe0, /* 11100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0x78, /* 01111000 */ + 0x78, /* 01111000 */ + 0x6c, /* 01101100 */ + 0x66, /* 01100110 */ + 0xe6, /* 11100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 108 0x6c 'l' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 109 0x6d 'm' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xec, /* 11101100 */ + 0xfe, /* 11111110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 110 0x6e 'n' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 111 0x6f 'o' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 112 0x70 'p' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + + /* 113 0x71 'q' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x7c, /* 01111100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x1e, /* 00011110 */ + 0x00, /* 00000000 */ + + /* 114 0x72 'r' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x76, /* 01110110 */ + 0x66, /* 01100110 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 115 0x73 's' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0x60, /* 01100000 */ + 0x38, /* 00111000 */ + 0x0c, /* 00001100 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 116 0x74 't' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0xfc, /* 11111100 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x36, /* 00110110 */ + 0x1c, /* 00011100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 117 0x75 'u' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 118 0x76 'v' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 119 0x77 'w' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xd6, /* 11010110 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 120 0x78 'x' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x38, /* 00111000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 121 0x79 'y' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7e, /* 01111110 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + + /* 122 0x7a 'z' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xcc, /* 11001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 123 0x7b '{' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x0e, /* 00001110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x70, /* 01110000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x0e, /* 00001110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 124 0x7c '|' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 125 0x7d '}' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x70, /* 01110000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x0e, /* 00001110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 126 0x7e '~' */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 127 0x7f '' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 128 0x80 '€' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0xc2, /* 11000010 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc2, /* 11000010 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 129 0x81 '' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 130 0x82 '‚' */ + 0x00, /* 00000000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 131 0x83 'ƒ' */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 132 0x84 '„' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 133 0x85 '…' */ + 0x00, /* 00000000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 134 0x86 '†' */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 135 0x87 '‡' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x18, /* 00011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 136 0x88 'ˆ' */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 137 0x89 '‰' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 138 0x8a 'Š' */ + 0x00, /* 00000000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 139 0x8b '‹' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 140 0x8c 'Œ' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 141 0x8d '' */ + 0x00, /* 00000000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 142 0x8e 'Ž' */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 143 0x8f '' */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 144 0x90 '' */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x66, /* 01100110 */ + 0x62, /* 01100010 */ + 0x68, /* 01101000 */ + 0x78, /* 01111000 */ + 0x68, /* 01101000 */ + 0x62, /* 01100010 */ + 0x66, /* 01100110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 145 0x91 '‘' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xec, /* 11101100 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x7e, /* 01111110 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0x6e, /* 01101110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 146 0x92 '’' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3e, /* 00111110 */ + 0x6c, /* 01101100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xfe, /* 11111110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xce, /* 11001110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 147 0x93 '“' */ + 0x00, /* 00000000 */ + 0x10, /* 00010000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 148 0x94 '”' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 149 0x95 '•' */ + 0x00, /* 00000000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 150 0x96 '–' */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x78, /* 01111000 */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 151 0x97 '—' */ + 0x00, /* 00000000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 152 0x98 '˜' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7e, /* 01111110 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x78, /* 01111000 */ + 0x00, /* 00000000 */ + + /* 153 0x99 '™' */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 154 0x9a 'š' */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 155 0x9b '›' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 156 0x9c 'œ' */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x64, /* 01100100 */ + 0x60, /* 01100000 */ + 0xf0, /* 11110000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xe6, /* 11100110 */ + 0xfc, /* 11111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 157 0x9d '' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 158 0x9e 'ž' */ + 0x00, /* 00000000 */ + 0xf8, /* 11111000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xf8, /* 11111000 */ + 0xc4, /* 11000100 */ + 0xcc, /* 11001100 */ + 0xde, /* 11011110 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 159 0x9f 'Ÿ' */ + 0x00, /* 00000000 */ + 0x0e, /* 00001110 */ + 0x1b, /* 00011011 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xd8, /* 11011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 160 0xa0 ' ' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0x0c, /* 00001100 */ + 0x7c, /* 01111100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 161 0xa1 'Ħ' */ + 0x00, /* 00000000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 162 0xa2 '˘' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 163 0xa3 '£' */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x00, /* 00000000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 164 0xa4 '¤' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0xdc, /* 11011100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 165 0xa5 '' */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0xc6, /* 11000110 */ + 0xe6, /* 11100110 */ + 0xf6, /* 11110110 */ + 0xfe, /* 11111110 */ + 0xde, /* 11011110 */ + 0xce, /* 11001110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 166 0xa6 'Ĥ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x3e, /* 00111110 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 167 0xa7 '§' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 168 0xa8 '¨' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x7c, /* 01111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 169 0xa9 'İ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 170 0xaa 'Ş' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 171 0xab 'Ğ' */ + 0x00, /* 00000000 */ + 0x60, /* 01100000 */ + 0xe0, /* 11100000 */ + 0x62, /* 01100010 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xdc, /* 11011100 */ + 0x86, /* 10000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x3e, /* 00111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 172 0xac 'Ĵ' */ + 0x00, /* 00000000 */ + 0x60, /* 01100000 */ + 0xe0, /* 11100000 */ + 0x62, /* 01100010 */ + 0x66, /* 01100110 */ + 0x6c, /* 01101100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x66, /* 01100110 */ + 0xce, /* 11001110 */ + 0x9a, /* 10011010 */ + 0x3f, /* 00111111 */ + 0x06, /* 00000110 */ + 0x06, /* 00000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 173 0xad '­' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 174 0xae '' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x36, /* 00110110 */ + 0x6c, /* 01101100 */ + 0xd8, /* 11011000 */ + 0x6c, /* 01101100 */ + 0x36, /* 00110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 175 0xaf 'Ż' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xd8, /* 11011000 */ + 0x6c, /* 01101100 */ + 0x36, /* 00110110 */ + 0x6c, /* 01101100 */ + 0xd8, /* 11011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 176 0xb0 '°' */ + 0x11, /* 00010001 */ + 0x44, /* 01000100 */ + 0x11, /* 00010001 */ + 0x44, /* 01000100 */ + 0x11, /* 00010001 */ + 0x44, /* 01000100 */ + 0x11, /* 00010001 */ + 0x44, /* 01000100 */ + 0x11, /* 00010001 */ + 0x44, /* 01000100 */ + 0x11, /* 00010001 */ + 0x44, /* 01000100 */ + 0x11, /* 00010001 */ + 0x44, /* 01000100 */ + 0x11, /* 00010001 */ + 0x44, /* 01000100 */ + + /* 177 0xb1 'ħ' */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + 0x55, /* 01010101 */ + 0xaa, /* 10101010 */ + + /* 178 0xb2 '²' */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + 0xdd, /* 11011101 */ + 0x77, /* 01110111 */ + + /* 179 0xb3 '³' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 180 0xb4 '´' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 181 0xb5 'µ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 182 0xb6 'ĥ' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf6, /* 11110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 183 0xb7 '·' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 184 0xb8 '¸' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 185 0xb9 'ı' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf6, /* 11110110 */ + 0x06, /* 00000110 */ + 0xf6, /* 11110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 186 0xba 'ş' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 187 0xbb 'ğ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x06, /* 00000110 */ + 0xf6, /* 11110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 188 0xbc 'ĵ' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf6, /* 11110110 */ + 0x06, /* 00000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 189 0xbd '½' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 190 0xbe '' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 191 0xbf 'ż' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xf8, /* 11111000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 192 0xc0 'À' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 193 0xc1 'Á' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 194 0xc2 'Â' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 195 0xc3 '' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 196 0xc4 'Ä' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 197 0xc5 'Ċ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 198 0xc6 'Ĉ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 199 0xc7 'Ç' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x37, /* 00110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 200 0xc8 'È' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x37, /* 00110111 */ + 0x30, /* 00110000 */ + 0x3f, /* 00111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 201 0xc9 'É' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3f, /* 00111111 */ + 0x30, /* 00110000 */ + 0x37, /* 00110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 202 0xca 'Ê' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf7, /* 11110111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 203 0xcb 'Ë' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xf7, /* 11110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 204 0xcc 'Ì' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x37, /* 00110111 */ + 0x30, /* 00110000 */ + 0x37, /* 00110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 205 0xcd 'Í' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 206 0xce 'Î' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xf7, /* 11110111 */ + 0x00, /* 00000000 */ + 0xf7, /* 11110111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 207 0xcf 'Ï' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 208 0xd0 '' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 209 0xd1 'Ñ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 210 0xd2 'Ò' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 211 0xd3 'Ó' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x3f, /* 00111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 212 0xd4 'Ô' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 213 0xd5 'Ġ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 214 0xd6 'Ö' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x3f, /* 00111111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 215 0xd7 '×' */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0xff, /* 11111111 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + + /* 216 0xd8 'Ĝ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0xff, /* 11111111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 217 0xd9 'Ù' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xf8, /* 11111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 218 0xda 'Ú' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1f, /* 00011111 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 219 0xdb 'Û' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 220 0xdc 'Ü' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + + /* 221 0xdd 'Ŭ' */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + 0xf0, /* 11110000 */ + + /* 222 0xde 'Ŝ' */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + 0x0f, /* 00001111 */ + + /* 223 0xdf 'ß' */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0xff, /* 11111111 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 224 0xe0 'à' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0xdc, /* 11011100 */ + 0x76, /* 01110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 225 0xe1 'á' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x78, /* 01111000 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xcc, /* 11001100 */ + 0xd8, /* 11011000 */ + 0xcc, /* 11001100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xcc, /* 11001100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 226 0xe2 'â' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0xc0, /* 11000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 227 0xe3 '' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 228 0xe4 'ä' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 229 0xe5 'ċ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 230 0xe6 'ĉ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x7c, /* 01111100 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0x00, /* 00000000 */ + + /* 231 0xe7 'ç' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 232 0xe8 'è' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 233 0xe9 'é' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xfe, /* 11111110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 234 0xea 'ê' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0xee, /* 11101110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 235 0xeb 'ë' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1e, /* 00011110 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x3e, /* 00111110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x66, /* 01100110 */ + 0x3c, /* 00111100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 236 0xec 'ì' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 237 0xed 'í' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x03, /* 00000011 */ + 0x06, /* 00000110 */ + 0x7e, /* 01111110 */ + 0xdb, /* 11011011 */ + 0xdb, /* 11011011 */ + 0xf3, /* 11110011 */ + 0x7e, /* 01111110 */ + 0x60, /* 01100000 */ + 0xc0, /* 11000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 238 0xee 'î' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x1c, /* 00011100 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x7c, /* 01111100 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x1c, /* 00011100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 239 0xef 'ï' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7c, /* 01111100 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0xc6, /* 11000110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 240 0xf0 '' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0xfe, /* 11111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 241 0xf1 'ñ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x7e, /* 01111110 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 242 0xf2 'ò' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x06, /* 00000110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 243 0xf3 'ó' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x30, /* 00110000 */ + 0x60, /* 01100000 */ + 0x30, /* 00110000 */ + 0x18, /* 00011000 */ + 0x0c, /* 00001100 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 244 0xf4 'ô' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x0e, /* 00001110 */ + 0x1b, /* 00011011 */ + 0x1b, /* 00011011 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + + /* 245 0xf5 'ġ' */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0xd8, /* 11011000 */ + 0x70, /* 01110000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 246 0xf6 'ö' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 247 0xf7 '÷' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0x76, /* 01110110 */ + 0xdc, /* 11011100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 248 0xf8 'ĝ' */ + 0x00, /* 00000000 */ + 0x38, /* 00111000 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x38, /* 00111000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 249 0xf9 'ù' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 250 0xfa 'ú' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x18, /* 00011000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 251 0xfb 'û' */ + 0x00, /* 00000000 */ + 0x0f, /* 00001111 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0x0c, /* 00001100 */ + 0xec, /* 11101100 */ + 0x6c, /* 01101100 */ + 0x6c, /* 01101100 */ + 0x3c, /* 00111100 */ + 0x1c, /* 00011100 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 252 0xfc 'ü' */ + 0x00, /* 00000000 */ + 0x6c, /* 01101100 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x36, /* 00110110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 253 0xfd 'ŭ' */ + 0x00, /* 00000000 */ + 0x3c, /* 00111100 */ + 0x66, /* 01100110 */ + 0x0c, /* 00001100 */ + 0x18, /* 00011000 */ + 0x32, /* 00110010 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 254 0xfe 'ŝ' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x7e, /* 01111110 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + + /* 255 0xff '˙' */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + 0x00, /* 00000000 */ + +}; + +#endif diff --git a/include/video_logo.h b/include/video_logo.h new file mode 100644 index 0000000..c12e8f8 --- /dev/null +++ b/include/video_logo.h @@ -0,0 +1,1951 @@ +/* */ +/* Generated by EasyLogo, (C) 2000 by Paolo Scaffardi */ +/* */ +/* To use this, include it and call: easylogo_plot(screen,&u_boot_logo, width,x,y) */ +/* */ +/* Where: 'screen' is the pointer to the frame buffer */ +/* 'width' is the screen width */ +/* 'x' is the horizontal position */ +/* 'y' is the vertical position */ +/* */ + +#include + +#define DEF_U_BOOT_LOGO_WIDTH 160 +#define DEF_U_BOOT_LOGO_HEIGHT 96 +#define DEF_U_BOOT_LOGO_PIXELS 15360 +#define DEF_U_BOOT_LOGO_BPP 16 +#define DEF_U_BOOT_LOGO_PIXEL_SIZE 2 +#define DEF_U_BOOT_LOGO_SIZE 30720 + +unsigned char DEF_U_BOOT_LOGO_DATA[DEF_U_BOOT_LOGO_SIZE] = { + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, + 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7c, 0x4b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7c, 0x69, 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xb6, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7c, 0x69, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa1, 0xa5, 0x70, 0xcc, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x6d, 0xc7, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x55, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x84, 0xdb, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x91, 0xc3, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xc0, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7d, 0x80, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x75, 0xd1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0xdb, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x91, 0xc3, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0xa7, 0x9a, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x51, 0xa5, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x51, 0xa5, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x7f, 0x8b, 0x7d, 0x75, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xb6, 0x80, 0xe1, 0x7e, 0xaa, 0x7c, 0x69, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xb6, + 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0xdb, 0x8f, 0xc7, + 0x54, 0xa9, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x54, 0xa9, 0x8c, 0xcc, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7c, 0x69, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x75, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x89, 0xd1, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x59, 0xae, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xc0, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xaa, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x89, 0xd1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x69, 0xc3, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x8f, 0xc7, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x4b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x4c, 0x9f, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7c, 0x55, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x8c, 0xcc, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x9e, 0xa9, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa7, 0x9a, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa1, 0xa5, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x9e, 0xa9, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x9e, 0xa9, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x8c, 0xcc, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x4c, 0x9f, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x7c, 0xdb, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xca, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0xa1, 0xa5, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa7, 0x9a, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7c, 0xdb, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xca, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x7c, 0xdb, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x4c, 0x9f, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0x9d, 0xae, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x75, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0, + 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7d, 0x80, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0xdb, 0x97, 0xb8, + 0x51, 0xa5, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x51, 0xa5, 0x94, 0xbd, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7b, 0x60, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x7c, 0xdb, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7c, 0xdb, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x8c, 0xcc, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0xa7, 0x9a, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x78, 0xd6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0xdb, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x4b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xc0, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xd5, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0x8c, 0xcc, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x89, 0xd1, 0x45, 0x95, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xb6, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xca, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x55, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa7, 0x9a, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x75, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, + 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x84, 0xdb, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x8f, 0xc7, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7c, 0x69, 0x7a, 0x3f, 0x7c, 0x4b, 0x7c, 0x69, + 0x7e, 0xaa, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7f, 0x8b, 0x7f, 0x8b, 0x7e, 0xaa, 0x80, 0xb6, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x75, 0xd1, 0x97, 0xb8, + 0x70, 0xcc, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0x97, 0xb8, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7d, 0x80, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, + 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x7c, 0x69, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7b, 0x60, 0x7c, 0x69, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, + 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7c, 0x4b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7e, 0xa0, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7d, 0x75, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x75, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x80, 0xb6, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xb6, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x80, 0xd5, 0x7c, 0x55, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0x96, 0x7a, 0x3f, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, + 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xb6, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x75, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xb6, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xb6, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f, 0x7e, 0xaa, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x75, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x7f, 0x8b, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xd5, 0x7a, 0x3f, 0x7c, 0x55, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7c, 0x55, + 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xc0, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7e, 0xaa, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xca, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7b, 0x60, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7b, 0x60, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7c, 0x69, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7e, 0x96, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xca, 0x7a, 0x3f, 0x7d, 0x75, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, + 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, + 0x7c, 0x69, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xaa, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xc0, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7b, 0x60, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x4b, 0x7a, 0x3f, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x7c, 0x69, + 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, + 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f, + 0x7a, 0x3f, 0x7c, 0x69, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1 +}; + +fastimage_t u_boot_logo = { + DEF_U_BOOT_LOGO_DATA, + DEF_U_BOOT_LOGO_WIDTH, + DEF_U_BOOT_LOGO_HEIGHT, + DEF_U_BOOT_LOGO_BPP, + DEF_U_BOOT_LOGO_PIXEL_SIZE, + DEF_U_BOOT_LOGO_SIZE +}; diff --git a/include/virtex2.h b/include/virtex2.h new file mode 100644 index 0000000..f59227b --- /dev/null +++ b/include/virtex2.h @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _VIRTEX2_H_ +#define _VIRTEX2_H_ + +#include + +extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size ); +extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); +extern int Virtex2_info( Xilinx_desc *desc ); +extern int Virtex2_reloc( Xilinx_desc *desc, ulong reloc_off ); + +/* + * Slave SelectMap Implementation function table. + */ +typedef struct { + Xilinx_pre_fn pre; + Xilinx_pgm_fn pgm; + Xilinx_init_fn init; + Xilinx_err_fn err; + Xilinx_done_fn done; + Xilinx_clk_fn clk; + Xilinx_cs_fn cs; + Xilinx_wr_fn wr; + Xilinx_rdata_fn rdata; + Xilinx_wdata_fn wdata; + Xilinx_busy_fn busy; + Xilinx_abort_fn abort; + Xilinx_post_fn post; + int relocated; +} Xilinx_Virtex2_Slave_SelectMap_fns; + +/* Slave Serial Implementation function table */ +typedef struct { + Xilinx_pgm_fn pgm; + Xilinx_clk_fn clk; + Xilinx_rdata_fn rdata; + Xilinx_wdata_fn wdata; + int relocated; +} Xilinx_Virtex2_Slave_Serial_fns; + +/* Device Image Sizes (in bytes) + *********************************************************************/ +#define XILINX_XC2V40_SIZE (338208 / 8) +#define XILINX_XC2V80_SIZE (597408 / 8) +#define XILINX_XC2V250_SIZE (1591584 / 8) +#define XILINX_XC2V500_SIZE (2557857 / 8) +#define XILINX_XC2V1000_SIZE (3749408 / 8) +#define XILINX_XC2V1500_SIZE (5166240 / 8) +#define XILINX_XC2V2000_SIZE (6808352 / 8) +#define XILINX_XC2V3000_SIZE (9589408 / 8) +#define XILINX_XC2V4000_SIZE (14220192 / 8) +#define XILINX_XC2V6000_SIZE (19752096 / 8) +#define XILINX_XC2V8000_SIZE (26185120 / 8) +#define XILINX_XC2V10000_SIZE (33519264 / 8) + +/* Descriptor Macros + *********************************************************************/ +#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie } + +#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie } + +#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie } + +#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie } + +#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie } + +#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie } + +#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie } + +#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie } + +#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie } + +#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie } + +#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie } + +#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ +{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie } + +#endif /* _VIRTEX2_H_ */ + +/* vim: set ts=4 tw=78: */ diff --git a/include/w83c553f.h b/include/w83c553f.h new file mode 100644 index 0000000..88ea9da --- /dev/null +++ b/include/w83c553f.h @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + /* winbond access routines and defines*/ + +/* from the winbond data sheet - + The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. + Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. +*/ + +/*ISA bridge configuration space*/ + +#define W83C553F_VID 0x10AD +#define W83C553F_DID 0x0565 + +#define WINBOND_PCICONTR 0x40 /*pci control reg*/ +#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/ +#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/ +#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ +#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ +#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/ +#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ +#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ +#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ +#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ +#define WINBOND_CDR 0x4c /*Clock Divisor Register*/ +#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/ +#define WINBOND_ATSCR 0x4e /*AT System Control register*/ +#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/ +#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ +#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ +#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/ +#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/ + +#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/ + +#define IPADCR_MBE512 0x1 +#define IPADCR_MBE640 0x2 +#define IPADCR_IPATOM4 0x10 +#define IPADCR_IPATOM5 0x20 +#define IPADCR_IPATOM6 0x40 +#define IPADCR_IPATOM7 0x80 + +#define CSCR_UBIOSCSE 0x10 +#define CSCR_BIOSWP 0x20 + +#define IDECSR_P0EN 0x01 +#define IDECSR_P0F16 0x02 +#define IDECSR_P1EN 0x10 +#define IDECSR_P1F16 0x20 +#define IDECSR_LEGIRQ 0x800 + +/* + * Interrupt controller + */ +#define W83C553F_PIC1_ICW1 CFG_ISA_IO + 0x20 +#define W83C553F_PIC1_ICW2 CFG_ISA_IO + 0x21 +#define W83C553F_PIC1_ICW3 CFG_ISA_IO + 0x21 +#define W83C553F_PIC1_ICW4 CFG_ISA_IO + 0x21 +#define W83C553F_PIC1_OCW1 CFG_ISA_IO + 0x21 +#define W83C553F_PIC1_OCW2 CFG_ISA_IO + 0x20 +#define W83C553F_PIC1_OCW3 CFG_ISA_IO + 0x20 +#define W83C553F_PIC1_ELC CFG_ISA_IO + 0x4D0 +#define W83C553F_PIC2_ICW1 CFG_ISA_IO + 0xA0 +#define W83C553F_PIC2_ICW2 CFG_ISA_IO + 0xA1 +#define W83C553F_PIC2_ICW3 CFG_ISA_IO + 0xA1 +#define W83C553F_PIC2_ICW4 CFG_ISA_IO + 0xA1 +#define W83C553F_PIC2_OCW1 CFG_ISA_IO + 0xA1 +#define W83C553F_PIC2_OCW2 CFG_ISA_IO + 0xA0 +#define W83C553F_PIC2_OCW3 CFG_ISA_IO + 0xA0 +#define W83C553F_PIC2_ELC CFG_ISA_IO + 0x4D1 + +#define W83C553F_TMR1_CMOD CFG_ISA_IO + 0x43 + +/* + * DMA controller + */ +#define W83C553F_DMA1 CFG_ISA_IO + 0x000 /* channel 0 - 3 */ +#define W83C553F_DMA2 CFG_ISA_IO + 0x0C0 /* channel 4 - 7 */ + +/* command/status register bit definitions */ + +#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ +#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ +#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ +#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ + +#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */ +#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */ +#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */ +#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */ + +#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */ +#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */ +#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */ +#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */ + +/* mode register bit definitions */ + +#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */ +#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */ +#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */ +#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */ +#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */ +#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */ +#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */ +#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */ +#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */ +#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */ +#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */ +#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */ +#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */ +#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */ + +/* request register bit definitions */ + +#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */ +#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */ +#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */ +#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */ +#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */ + +/* write single mask bit register bit definitions */ + +#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */ +#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */ +#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */ +#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */ +#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */ + +/* read/write all mask bits register bit definitions */ + +#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */ +#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */ +#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */ +#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */ + +/* typedefs */ + +#define W83C553F_DMA1_CS 0x8 +#define W83C553F_DMA1_WR 0x9 +#define W83C553F_DMA1_WSMB 0xA +#define W83C553F_DMA1_WM 0xB +#define W83C553F_DMA1_CBP 0xC +#define W83C553F_DMA1_MC 0xD +#define W83C553F_DMA1_CM 0xE +#define W83C553F_DMA1_RWAMB 0xF + +#define W83C553F_DMA2_CS 0x10 +#define W83C553F_DMA2_WR 0x12 +#define W83C553F_DMA2_WSMB 0x14 +#define W83C553F_DMA2_WM 0x16 +#define W83C553F_DMA2_CBP 0x18 +#define W83C553F_DMA2_MC 0x1A +#define W83C553F_DMA2_CM 0x1C +#define W83C553F_DMA2_RWAMB 0x1E + +void initialise_w83c553f(void); diff --git a/include/watchdog.h b/include/watchdog.h new file mode 100644 index 0000000..9265be9 --- /dev/null +++ b/include/watchdog.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Watchdog functions and macros. + */ +#ifndef _WATCHDOG_H_ +#define _WATCHDOG_H_ + +#if defined(CONFIG_HW_WATCHDOG) && defined(CONFIG_WATCHDOG) +# error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together." +#endif + +#if defined(__ASSEMBLY__) && defined(__NIOS__) +# error "Configuration error: WATCHDOG_RESET inside assembler not supported for Nios platforms." +#endif + +/* + * Hardware watchdog + */ +#ifdef CONFIG_HW_WATCHDOG + #if defined(__ASSEMBLY__) + #define WATCHDOG_RESET bl hw_watchdog_reset + #else + extern void hw_watchdog_reset(void); + + #define WATCHDOG_RESET hw_watchdog_reset + #endif /* __ASSEMBLY__ */ +#else + /* + * Maybe a software watchdog? + */ + #if defined(CONFIG_WATCHDOG) + #if defined(__ASSEMBLY__) + #define WATCHDOG_RESET bl watchdog_reset + #else + extern void watchdog_reset(void); + + #define WATCHDOG_RESET watchdog_reset + #endif + #else + /* + * No hardware or software watchdog. + */ + #if defined(__ASSEMBLY__) + #define WATCHDOG_RESET /*XXX DO_NOT_DEL_THIS_COMMENT*/ + #else + #define WATCHDOG_RESET() {} + #endif /* __ASSEMBLY__ */ + #endif /* CONFIG_WATCHDOG && !__ASSEMBLY__ */ +#endif /* CONFIG_HW_WATCHDOG */ + +/* + * Prototypes from $(CPU)/cpu.c. + */ + +/* MPC 8xx */ +#if (defined(CONFIG_8xx) || defined(CONFIG_MPC860)) && !defined(__ASSEMBLY__) + void reset_8xx_watchdog(volatile immap_t *immr); +#endif + +/* MPC 5xx */ +#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__) + void reset_5xx_watchdog(volatile immap_t *immr); +#endif + +/* AMCC 4xx */ +#if defined(CONFIG_4xx) && !defined(__ASSEMBLY__) + void reset_4xx_watchdog(void); +#endif + +#endif /* _WATCHDOG_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h new file mode 100644 index 0000000..3704e1d --- /dev/null +++ b/include/xilinx.h @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include + +#ifndef _XILINX_H_ +#define _XILINX_H_ + +/* Xilinx Model definitions + *********************************************************************/ +#define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 ) +#define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 ) +#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 ) +#define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 ) +#define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2) +#define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E) +#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2) +#define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3) +/* XXX - Add new models here */ + + +/* Xilinx Interface definitions + *********************************************************************/ +#define CFG_XILINX_IF_SS CFG_FPGA_IF( 0x1 ) /* slave serial */ +#define CFG_XILINX_IF_MS CFG_FPGA_IF( 0x2 ) /* master serial */ +#define CFG_XILINX_IF_SP CFG_FPGA_IF( 0x4 ) /* slave parallel */ +#define CFG_XILINX_IF_JTAG CFG_FPGA_IF( 0x8 ) /* jtag */ +#define CFG_XILINX_IF_MSM CFG_FPGA_IF( 0x10 ) /* master selectmap */ +#define CFG_XILINX_IF_SSM CFG_FPGA_IF( 0x20 ) /* slave selectmap */ + +/* Xilinx types + *********************************************************************/ +typedef enum { /* typedef Xilinx_iface */ + min_xilinx_iface_type, /* low range check value */ + slave_serial, /* serial data and external clock */ + master_serial, /* serial data w/ internal clock (not used) */ + slave_parallel, /* parallel data w/ external latch */ + jtag_mode, /* jtag/tap serial (not used ) */ + master_selectmap, /* master SelectMap (virtex2) */ + slave_selectmap, /* slave SelectMap (virtex2) */ + max_xilinx_iface_type /* insert all new types before this */ +} Xilinx_iface; /* end, typedef Xilinx_iface */ + +typedef enum { /* typedef Xilinx_Family */ + min_xilinx_type, /* low range check value */ + Xilinx_Spartan2, /* Spartan-II Family */ + Xilinx_VirtexE, /* Virtex-E Family */ + Xilinx_Virtex2, /* Virtex2 Family */ + Xilinx_Spartan3, /* Spartan-III Family */ + max_xilinx_type /* insert all new types before this */ +} Xilinx_Family; /* end, typedef Xilinx_Family */ + +typedef struct { /* typedef Xilinx_desc */ + Xilinx_Family family; /* part type */ + Xilinx_iface iface; /* interface type */ + size_t size; /* bytes of data part can accept */ + void * iface_fns; /* interface function table */ + int cookie; /* implementation specific cookie */ +} Xilinx_desc; /* end, typedef Xilinx_desc */ + +/* Generic Xilinx Functions + *********************************************************************/ +extern int xilinx_load( Xilinx_desc *desc, void *image, size_t size ); +extern int xilinx_dump( Xilinx_desc *desc, void *buf, size_t bsize ); +extern int xilinx_info( Xilinx_desc *desc ); +extern int xilinx_reloc( Xilinx_desc *desc, ulong reloc_offset ); + +/* Board specific implementation specific function types + *********************************************************************/ +typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie ); +typedef int (*Xilinx_init_fn)( int cookie ); +typedef int (*Xilinx_err_fn)( int cookie ); +typedef int (*Xilinx_done_fn)( int cookie ); +typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie ); +typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie ); +typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie ); +typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie ); +typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie ); +typedef int (*Xilinx_busy_fn)( int cookie ); +typedef int (*Xilinx_abort_fn)( int cookie ); +typedef int (*Xilinx_pre_fn)( int cookie ); +typedef int (*Xilinx_post_fn)( int cookie ); + +#endif /* _XILINX_H_ */ diff --git a/include/zlib.h b/include/zlib.h new file mode 100644 index 0000000..e441494 --- /dev/null +++ b/include/zlib.h @@ -0,0 +1,434 @@ +/* + * This file is derived from zlib.h and zconf.h from the zlib-0.95 + * distribution by Jean-loup Gailly and Mark Adler, with some additions + * by Paul Mackerras to aid in implementing Deflate compression and + * decompression for PPP packets. + */ + +/* + * ==FILEVERSION 960122== + * + * This marker is used by the Linux installation script to determine + * whether an up-to-date version of this file is already installed. + */ + +/* zlib.h -- interface of the 'zlib' general purpose compression library + version 0.95, Aug 16th, 1995. + + Copyright (C) 1995 Jean-loup Gailly and Mark Adler + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages + arising from the use of this software. + + Permission is granted to anyone to use this software for any purpose, + including commercial applications, and to alter it and redistribute it + freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + 3. This notice may not be removed or altered from any source distribution. + + Jean-loup Gailly Mark Adler + gzip@prep.ai.mit.edu madler@alumni.caltech.edu + */ + +#ifndef _ZLIB_H +#define _ZLIB_H + +/* #include "zconf.h" */ /* included directly here */ + +/* zconf.h -- configuration of the zlib compression library + * Copyright (C) 1995 Jean-loup Gailly. + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* From: zconf.h,v 1.12 1995/05/03 17:27:12 jloup Exp */ + +/* + The library does not install any signal handler. It is recommended to + add at least a handler for SIGSEGV when decompressing; the library checks + the consistency of the input data whenever possible but may go nuts + for some forms of corrupted input. + */ + +/* + * Compile with -DMAXSEG_64K if the alloc function cannot allocate more + * than 64k bytes at a time (needed on systems with 16-bit int). + * Compile with -DUNALIGNED_OK if it is OK to access shorts or ints + * at addresses which are not a multiple of their size. + * Under DOS, -DFAR=far or -DFAR=__far may be needed. + */ + +#ifndef STDC +# if defined(MSDOS) || defined(__STDC__) || defined(__cplusplus) +# define STDC +# endif +#endif + +#ifdef __MWERKS__ /* Metrowerks CodeWarrior declares fileno() in unix.h */ +# include +#endif + +/* Maximum value for memLevel in deflateInit2 */ +#ifndef MAX_MEM_LEVEL +# ifdef MAXSEG_64K +# define MAX_MEM_LEVEL 8 +# else +# define MAX_MEM_LEVEL 9 +# endif +#endif + +#ifndef FAR +# define FAR +#endif + +/* Maximum value for windowBits in deflateInit2 and inflateInit2 */ +#ifndef MAX_WBITS +# define MAX_WBITS 15 /* 32K LZ77 window */ +#endif + +/* The memory requirements for deflate are (in bytes): + 1 << (windowBits+2) + 1 << (memLevel+9) + that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values) + plus a few kilobytes for small objects. For example, if you want to reduce + the default memory requirements from 256K to 128K, compile with + make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7" + Of course this will generally degrade compression (there's no free lunch). + + The memory requirements for inflate are (in bytes) 1 << windowBits + that is, 32K for windowBits=15 (default value) plus a few kilobytes + for small objects. +*/ + + /* Type declarations */ + +#ifndef OF /* function prototypes */ +# ifdef STDC +# define OF(args) args +# else +# define OF(args) () +# endif +#endif + +typedef unsigned char Byte; /* 8 bits */ +typedef unsigned int uInt; /* 16 bits or more */ +typedef unsigned long uLong; /* 32 bits or more */ + +typedef Byte FAR Bytef; +typedef char FAR charf; +typedef int FAR intf; +typedef uInt FAR uIntf; +typedef uLong FAR uLongf; + +#ifdef STDC + typedef void FAR *voidpf; + typedef void *voidp; +#else + typedef Byte FAR *voidpf; + typedef Byte *voidp; +#endif + +/* end of original zconf.h */ + +#define ZLIB_VERSION "0.95P" + +/* + The 'zlib' compression library provides in-memory compression and + decompression functions, including integrity checks of the uncompressed + data. This version of the library supports only one compression method + (deflation) but other algorithms may be added later and will have the same + stream interface. + + For compression the application must provide the output buffer and + may optionally provide the input buffer for optimization. For decompression, + the application must provide the input buffer and may optionally provide + the output buffer for optimization. + + Compression can be done in a single step if the buffers are large + enough (for example if an input file is mmap'ed), or can be done by + repeated calls of the compression function. In the latter case, the + application must provide more input and/or consume the output + (providing more output space) before each call. +*/ + +typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size)); +typedef void (*free_func) OF((voidpf opaque, voidpf address, uInt nbytes)); + +typedef void (*cb_func) OF((Bytef *buf, uInt len)); + +struct internal_state; + +typedef struct z_stream_s { + Bytef *next_in; /* next input byte */ + uInt avail_in; /* number of bytes available at next_in */ + uLong total_in; /* total nb of input bytes read so far */ + + Bytef *next_out; /* next output byte should be put there */ + uInt avail_out; /* remaining free space at next_out */ + uLong total_out; /* total nb of bytes output so far */ + + char *msg; /* last error message, NULL if no error */ + struct internal_state FAR *state; /* not visible by applications */ + + alloc_func zalloc; /* used to allocate the internal state */ + free_func zfree; /* used to free the internal state */ + voidp opaque; /* private data object passed to zalloc and zfree */ + + Byte data_type; /* best guess about the data type: ascii or binary */ + + cb_func outcb; /* called regularly just before blocks of output */ + +} z_stream; + +/* + The application must update next_in and avail_in when avail_in has + dropped to zero. It must update next_out and avail_out when avail_out + has dropped to zero. The application must initialize zalloc, zfree and + opaque before calling the init function. All other fields are set by the + compression library and must not be updated by the application. + + The opaque value provided by the application will be passed as the first + parameter for calls of zalloc and zfree. This can be useful for custom + memory management. The compression library attaches no meaning to the + opaque value. + + zalloc must return Z_NULL if there is not enough memory for the object. + On 16-bit systems, the functions zalloc and zfree must be able to allocate + exactly 65536 bytes, but will not be required to allocate more than this + if the symbol MAXSEG_64K is defined (see zconf.h). WARNING: On MSDOS, + pointers returned by zalloc for objects of exactly 65536 bytes *must* + have their offset normalized to zero. The default allocation function + provided by this library ensures this (see zutil.c). To reduce memory + requirements and avoid any allocation of 64K objects, at the expense of + compression ratio, compile the library with -DMAX_WBITS=14 (see zconf.h). + + The fields total_in and total_out can be used for statistics or + progress reports. After compression, total_in holds the total size of + the uncompressed data and may be saved for use in the decompressor + (particularly if the decompressor wants to decompress everything in + a single step). +*/ + + /* constants */ + +#define Z_NO_FLUSH 0 +#define Z_PARTIAL_FLUSH 1 +#define Z_FULL_FLUSH 2 +#define Z_SYNC_FLUSH 3 /* experimental: partial_flush + byte align */ +#define Z_FINISH 4 +#define Z_PACKET_FLUSH 5 +/* See deflate() below for the usage of these constants */ + +#define Z_OK 0 +#define Z_STREAM_END 1 +#define Z_ERRNO (-1) +#define Z_STREAM_ERROR (-2) +#define Z_DATA_ERROR (-3) +#define Z_MEM_ERROR (-4) +#define Z_BUF_ERROR (-5) +/* error codes for the compression/decompression functions */ + +#define Z_BEST_SPEED 1 +#define Z_BEST_COMPRESSION 9 +#define Z_DEFAULT_COMPRESSION (-1) +/* compression levels */ + +#define Z_FILTERED 1 +#define Z_HUFFMAN_ONLY 2 +#define Z_DEFAULT_STRATEGY 0 + +#define Z_BINARY 0 +#define Z_ASCII 1 +#define Z_UNKNOWN 2 +/* Used to set the data_type field */ + +#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */ + +extern char *zlib_version; +/* The application can compare zlib_version and ZLIB_VERSION for consistency. + If the first character differs, the library code actually used is + not compatible with the zlib.h header file used by the application. + */ + + /* basic functions */ + +extern int inflateInit OF((z_stream *strm)); +/* + Initializes the internal stream state for decompression. The fields + zalloc and zfree must be initialized before by the caller. If zalloc and + zfree are set to Z_NULL, inflateInit updates them to use default allocation + functions. + + inflateInit returns Z_OK if success, Z_MEM_ERROR if there was not + enough memory. msg is set to null if there is no error message. + inflateInit does not perform any decompression: this will be done by + inflate(). +*/ + + +extern int inflate OF((z_stream *strm, int flush)); +/* + Performs one or both of the following actions: + + - Decompress more input starting at next_in and update next_in and avail_in + accordingly. If not all input can be processed (because there is not + enough room in the output buffer), next_in is updated and processing + will resume at this point for the next call of inflate(). + + - Provide more output starting at next_out and update next_out and avail_out + accordingly. inflate() always provides as much output as possible + (until there is no more input data or no more space in the output buffer). + + Before the call of inflate(), the application should ensure that at least + one of the actions is possible, by providing more input and/or consuming + more output, and updating the next_* and avail_* values accordingly. + The application can consume the uncompressed output when it wants, for + example when the output buffer is full (avail_out == 0), or after each + call of inflate(). + + If the parameter flush is set to Z_PARTIAL_FLUSH or Z_PACKET_FLUSH, + inflate flushes as much output as possible to the output buffer. The + flushing behavior of inflate is not specified for values of the flush + parameter other than Z_PARTIAL_FLUSH, Z_PACKET_FLUSH or Z_FINISH, but the + current implementation actually flushes as much output as possible + anyway. For Z_PACKET_FLUSH, inflate checks that once all the input data + has been consumed, it is expecting to see the length field of a stored + block; if not, it returns Z_DATA_ERROR. + + inflate() should normally be called until it returns Z_STREAM_END or an + error. However if all decompression is to be performed in a single step + (a single call of inflate), the parameter flush should be set to + Z_FINISH. In this case all pending input is processed and all pending + output is flushed; avail_out must be large enough to hold all the + uncompressed data. (The size of the uncompressed data may have been saved + by the compressor for this purpose.) The next operation on this stream must + be inflateEnd to deallocate the decompression state. The use of Z_FINISH + is never required, but can be used to inform inflate that a faster routine + may be used for the single inflate() call. + + inflate() returns Z_OK if some progress has been made (more input + processed or more output produced), Z_STREAM_END if the end of the + compressed data has been reached and all uncompressed output has been + produced, Z_DATA_ERROR if the input data was corrupted, Z_STREAM_ERROR if + the stream structure was inconsistent (for example if next_in or next_out + was NULL), Z_MEM_ERROR if there was not enough memory, Z_BUF_ERROR if no + progress is possible or if there was not enough room in the output buffer + when Z_FINISH is used. In the Z_DATA_ERROR case, the application may then + call inflateSync to look for a good compression block. */ + + +extern int inflateEnd OF((z_stream *strm)); +/* + All dynamically allocated data structures for this stream are freed. + This function discards any unprocessed input and does not flush any + pending output. + + inflateEnd returns Z_OK if success, Z_STREAM_ERROR if the stream state + was inconsistent. In the error case, msg may be set but then points to a + static string (which must not be deallocated). +*/ + + /* advanced functions */ + +extern int inflateInit2 OF((z_stream *strm, + int windowBits)); +/* + This is another version of inflateInit with more compression options. The + fields next_out, zalloc and zfree must be initialized before by the caller. + + The windowBits parameter is the base two logarithm of the maximum window + size (the size of the history buffer). It should be in the range 8..15 for + this version of the library (the value 16 will be allowed soon). The + default value is 15 if inflateInit is used instead. If a compressed stream + with a larger window size is given as input, inflate() will return with + the error code Z_DATA_ERROR instead of trying to allocate a larger window. + + If next_out is not null, the library will use this buffer for the history + buffer; the buffer must either be large enough to hold the entire output + data, or have at least 1< $@ + +sinclude .depend + +######################################################################### diff --git a/lib_arm/_udivsi3.S b/lib_arm/_udivsi3.S new file mode 100644 index 0000000..2cdcd48 --- /dev/null +++ b/lib_arm/_udivsi3.S @@ -0,0 +1,77 @@ +/* # 1 "libgcc1.S" */ +@ libgcc1 routines for ARM cpu. +@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) +dividend .req r0 +divisor .req r1 +result .req r2 +curbit .req r3 +/* ip .req r12 */ +/* sp .req r13 */ +/* lr .req r14 */ +/* pc .req r15 */ + .text + .globl __udivsi3 + .type __udivsi3 ,function + .align 0 + __udivsi3 : + cmp divisor, #0 + beq Ldiv0 + mov curbit, #1 + mov result, #0 + cmp dividend, divisor + bcc Lgot_result +Loop1: + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + cmp divisor, #0x10000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #4 + movcc curbit, curbit, lsl #4 + bcc Loop1 +Lbignum: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. + cmp divisor, #0x80000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #1 + movcc curbit, curbit, lsl #1 + bcc Lbignum +Loop3: + @ Test for possible subtractions, and note which bits + @ are done in the result. On the final pass, this may subtract + @ too much from the dividend, but the result will be ok, since the + @ "bit" will have been shifted out at the bottom. + cmp dividend, divisor + subcs dividend, dividend, divisor + orrcs result, result, curbit + cmp dividend, divisor, lsr #1 + subcs dividend, dividend, divisor, lsr #1 + orrcs result, result, curbit, lsr #1 + cmp dividend, divisor, lsr #2 + subcs dividend, dividend, divisor, lsr #2 + orrcs result, result, curbit, lsr #2 + cmp dividend, divisor, lsr #3 + subcs dividend, dividend, divisor, lsr #3 + orrcs result, result, curbit, lsr #3 + cmp dividend, #0 @ Early termination? + movnes curbit, curbit, lsr #4 @ No, any more bits to do? + movne divisor, divisor, lsr #4 + bne Loop3 +Lgot_result: + mov r0, result + mov pc, lr +Ldiv0: + str lr, [sp, #-4]! + bl __div0 (PLT) + mov r0, #0 @ about as wrong as it could be + ldmia sp!, {pc} + .size __udivsi3 , . - __udivsi3 +/* # 235 "libgcc1.S" */ +/* # 320 "libgcc1.S" */ +/* # 421 "libgcc1.S" */ +/* # 433 "libgcc1.S" */ +/* # 456 "libgcc1.S" */ +/* # 500 "libgcc1.S" */ +/* # 580 "libgcc1.S" */ diff --git a/lib_arm/_umodsi3.S b/lib_arm/_umodsi3.S new file mode 100644 index 0000000..e4aebe8 --- /dev/null +++ b/lib_arm/_umodsi3.S @@ -0,0 +1,88 @@ +/* # 1 "libgcc1.S" */ +@ libgcc1 routines for ARM cpu. +@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) +/* # 145 "libgcc1.S" */ +dividend .req r0 +divisor .req r1 +overdone .req r2 +curbit .req r3 +/* ip .req r12 */ +/* sp .req r13 */ +/* lr .req r14 */ +/* pc .req r15 */ + .text + .globl __umodsi3 + .type __umodsi3 ,function + .align 0 + __umodsi3 : + cmp divisor, #0 + beq Ldiv0 + mov curbit, #1 + cmp dividend, divisor + movcc pc, lr +Loop1: + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + cmp divisor, #0x10000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #4 + movcc curbit, curbit, lsl #4 + bcc Loop1 +Lbignum: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. + cmp divisor, #0x80000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #1 + movcc curbit, curbit, lsl #1 + bcc Lbignum +Loop3: + @ Test for possible subtractions. On the final pass, this may + @ subtract too much from the dividend, so keep track of which + @ subtractions are done, we can fix them up afterwards... + mov overdone, #0 + cmp dividend, divisor + subcs dividend, dividend, divisor + cmp dividend, divisor, lsr #1 + subcs dividend, dividend, divisor, lsr #1 + orrcs overdone, overdone, curbit, ror #1 + cmp dividend, divisor, lsr #2 + subcs dividend, dividend, divisor, lsr #2 + orrcs overdone, overdone, curbit, ror #2 + cmp dividend, divisor, lsr #3 + subcs dividend, dividend, divisor, lsr #3 + orrcs overdone, overdone, curbit, ror #3 + mov ip, curbit + cmp dividend, #0 @ Early termination? + movnes curbit, curbit, lsr #4 @ No, any more bits to do? + movne divisor, divisor, lsr #4 + bne Loop3 + @ Any subtractions that we should not have done will be recorded in + @ the top three bits of "overdone". Exactly which were not needed + @ are governed by the position of the bit, stored in ip. + @ If we terminated early, because dividend became zero, + @ then none of the below will match, since the bit in ip will not be + @ in the bottom nibble. + ands overdone, overdone, #0xe0000000 + moveq pc, lr @ No fixups needed + tst overdone, ip, ror #3 + addne dividend, dividend, divisor, lsr #3 + tst overdone, ip, ror #2 + addne dividend, dividend, divisor, lsr #2 + tst overdone, ip, ror #1 + addne dividend, dividend, divisor, lsr #1 + mov pc, lr +Ldiv0: + str lr, [sp, #-4]! + bl __div0 (PLT) + mov r0, #0 @ about as wrong as it could be + ldmia sp!, {pc} + .size __umodsi3 , . - __umodsi3 +/* # 320 "libgcc1.S" */ +/* # 421 "libgcc1.S" */ +/* # 433 "libgcc1.S" */ +/* # 456 "libgcc1.S" */ +/* # 500 "libgcc1.S" */ +/* # 580 "libgcc1.S" */ diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c new file mode 100644 index 0000000..ca630b3 --- /dev/null +++ b/lib_arm/armlinux.c @@ -0,0 +1,418 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_HAS_DATAFLASH +#include +#endif + +/*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ + defined (CONFIG_CMDLINE_TAG) || \ + defined (CONFIG_INITRD_TAG) || \ + defined (CONFIG_SERIAL_TAG) || \ + defined (CONFIG_REVISION_TAG) || \ + defined (CONFIG_VFD) || \ + defined (CONFIG_LCD) +static void setup_start_tag (bd_t *bd); + +# ifdef CONFIG_SETUP_MEMORY_TAGS +static void setup_memory_tags (bd_t *bd); +# endif +static void setup_commandline_tag (bd_t *bd, char *commandline); + +#if 0 +static void setup_ramdisk_tag (bd_t *bd); +#endif +# ifdef CONFIG_INITRD_TAG +static void setup_initrd_tag (bd_t *bd, ulong initrd_start, + ulong initrd_end); +# endif +static void setup_end_tag (bd_t *bd); + +# if defined (CONFIG_VFD) || defined (CONFIG_LCD) +static void setup_videolfb_tag (gd_t *gd); +# endif + + +static struct tag *params; +#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +extern image_header_t header; /* from cmd_bootm.c */ + + +void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong len = 0, checksum; + ulong initrd_start, initrd_end; + ulong data; + void (*theKernel)(int zero, int arch, uint params); + image_header_t *hdr = &header; + bd_t *bd = gd->bd; + +#ifdef CONFIG_CMDLINE_TAG + char *commandline = getenv ("bootargs"); +#endif + + theKernel = (void (*)(int, int, uint))ntohl(hdr->ih_ep); + + /* + * Check if there is an initrd image + */ + if (argc >= 3) { + SHOW_BOOT_PROGRESS (9); + + addr = simple_strtoul (argv[2], NULL, 16); + + printf ("## Loading Ramdisk Image at %08lx ...\n", addr); + + /* Copy header so we can blank CRC field for re-calculation */ +#ifdef CONFIG_HAS_DATAFLASH + if (addr_dataflash (addr)) { + read_dataflash (addr, sizeof (image_header_t), + (char *) &header); + } else +#endif + memcpy (&header, (char *) addr, + sizeof (image_header_t)); + + if (ntohl (hdr->ih_magic) != IH_MAGIC) { + printf ("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS (-10); + do_reset (cmdtp, flag, argc, argv); + } + + data = (ulong) & header; + len = sizeof (image_header_t); + + checksum = ntohl (hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (char *) data, len) != checksum) { + printf ("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS (-11); + do_reset (cmdtp, flag, argc, argv); + } + + SHOW_BOOT_PROGRESS (10); + + print_image_hdr (hdr); + + data = addr + sizeof (image_header_t); + len = ntohl (hdr->ih_size); + +#ifdef CONFIG_HAS_DATAFLASH + if (addr_dataflash (addr)) { + read_dataflash (data, len, (char *) CFG_LOAD_ADDR); + data = CFG_LOAD_ADDR; + } +#endif + + if (verify) { + ulong csum = 0; + + printf (" Verifying Checksum ... "); + csum = crc32 (0, (char *) data, len); + if (csum != ntohl (hdr->ih_dcrc)) { + printf ("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS (-12); + do_reset (cmdtp, flag, argc, argv); + } + printf ("OK\n"); + } + + SHOW_BOOT_PROGRESS (11); + + if ((hdr->ih_os != IH_OS_LINUX) || + (hdr->ih_arch != IH_CPU_ARM) || + (hdr->ih_type != IH_TYPE_RAMDISK)) { + printf ("No Linux ARM Ramdisk Image\n"); + SHOW_BOOT_PROGRESS (-13); + do_reset (cmdtp, flag, argc, argv); + } + +#if defined(CONFIG_B2) || defined(CONFIG_EVB4510) || defined(CONFIG_ARMADILLO) + /* + *we need to copy the ramdisk to SRAM to let Linux boot + */ + memmove ((void *) ntohl(hdr->ih_load), (uchar *)data, len); + data = ntohl(hdr->ih_load); +#endif /* CONFIG_B2 || CONFIG_EVB4510 */ + + /* + * Now check if we have a multifile image + */ + } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { + ulong tail = ntohl (len_ptr[0]) % 4; + int i; + + SHOW_BOOT_PROGRESS (13); + + /* skip kernel length and terminator */ + data = (ulong) (&len_ptr[2]); + /* skip any additional image length fields */ + for (i = 1; len_ptr[i]; ++i) + data += 4; + /* add kernel length, and align */ + data += ntohl (len_ptr[0]); + if (tail) { + data += 4 - tail; + } + + len = ntohl (len_ptr[1]); + + } else { + /* + * no initrd image + */ + SHOW_BOOT_PROGRESS (14); + + len = data = 0; + } + +#ifdef DEBUG + if (!data) { + printf ("No initrd\n"); + } +#endif + + if (data) { + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = 0; + initrd_end = 0; + } + + SHOW_BOOT_PROGRESS (15); + + debug ("## Transferring control to Linux (at address %08lx) ...\n", + (ulong) theKernel); + +#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ + defined (CONFIG_CMDLINE_TAG) || \ + defined (CONFIG_INITRD_TAG) || \ + defined (CONFIG_SERIAL_TAG) || \ + defined (CONFIG_REVISION_TAG) || \ + defined (CONFIG_LCD) || \ + defined (CONFIG_VFD) + setup_start_tag (bd); +#ifdef CONFIG_SERIAL_TAG + setup_serial_tag (¶ms); +#endif +#ifdef CONFIG_REVISION_TAG + setup_revision_tag (¶ms); +#endif +#ifdef CONFIG_SETUP_MEMORY_TAGS + setup_memory_tags (bd); +#endif +#ifdef CONFIG_CMDLINE_TAG + setup_commandline_tag (bd, commandline); +#endif +#ifdef CONFIG_INITRD_TAG + if (initrd_start && initrd_end) + setup_initrd_tag (bd, initrd_start, initrd_end); +#endif +#if defined (CONFIG_VFD) || defined (CONFIG_LCD) + setup_videolfb_tag ((gd_t *) gd); +#endif + setup_end_tag (bd); +#endif + + /* we assume that the kernel is in place */ + printf ("\nStarting kernel ...\n\n"); + +#ifdef CONFIG_USB_DEVICE + { + extern void udc_disconnect (void); + udc_disconnect (); + } +#endif + + cleanup_before_linux (); + + theKernel (0, bd->bi_arch_number, bd->bi_boot_params); +} + + +#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ + defined (CONFIG_CMDLINE_TAG) || \ + defined (CONFIG_INITRD_TAG) || \ + defined (CONFIG_SERIAL_TAG) || \ + defined (CONFIG_REVISION_TAG) || \ + defined (CONFIG_LCD) || \ + defined (CONFIG_VFD) +static void setup_start_tag (bd_t *bd) +{ + params = (struct tag *) bd->bi_boot_params; + + params->hdr.tag = ATAG_CORE; + params->hdr.size = tag_size (tag_core); + + params->u.core.flags = 0; + params->u.core.pagesize = 0; + params->u.core.rootdev = 0; + + params = tag_next (params); +} + + +#ifdef CONFIG_SETUP_MEMORY_TAGS +static void setup_memory_tags (bd_t *bd) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + params->hdr.tag = ATAG_MEM; + params->hdr.size = tag_size (tag_mem32); + + params->u.mem.start = bd->bi_dram[i].start; + params->u.mem.size = bd->bi_dram[i].size; + + params = tag_next (params); + } +} +#endif /* CONFIG_SETUP_MEMORY_TAGS */ + + +static void setup_commandline_tag (bd_t *bd, char *commandline) +{ + char *p; + + if (!commandline) + return; + + /* eat leading white space */ + for (p = commandline; *p == ' '; p++); + + /* skip non-existent command lines so the kernel will still + * use its default command line. + */ + if (*p == '\0') + return; + + params->hdr.tag = ATAG_CMDLINE; + params->hdr.size = + (sizeof (struct tag_header) + strlen (p) + 1 + 4) >> 2; + + strcpy (params->u.cmdline.cmdline, p); + + params = tag_next (params); +} + + +#ifdef CONFIG_INITRD_TAG +static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) +{ + /* an ATAG_INITRD node tells the kernel where the compressed + * ramdisk can be found. ATAG_RDIMG is a better name, actually. + */ + params->hdr.tag = ATAG_INITRD2; + params->hdr.size = tag_size (tag_initrd); + + params->u.initrd.start = initrd_start; + params->u.initrd.size = initrd_end - initrd_start; + + params = tag_next (params); +} +#endif /* CONFIG_INITRD_TAG */ + + +#if defined (CONFIG_VFD) || defined (CONFIG_LCD) +extern ulong calc_fbsize (void); +static void setup_videolfb_tag (gd_t *gd) +{ + /* An ATAG_VIDEOLFB node tells the kernel where and how large + * the framebuffer for video was allocated (among other things). + * Note that a _physical_ address is passed ! + * + * We only use it to pass the address and size, the other entries + * in the tag_videolfb are not of interest. + */ + params->hdr.tag = ATAG_VIDEOLFB; + params->hdr.size = tag_size (tag_videolfb); + + params->u.videolfb.lfb_base = (u32) gd->fb_base; + /* Fb size is calculated according to parameters for our panel + */ + params->u.videolfb.lfb_size = calc_fbsize(); + + params = tag_next (params); +} +#endif /* CONFIG_VFD || CONFIG_LCD */ + +#ifdef CONFIG_SERIAL_TAG +void setup_serial_tag (struct tag **tmp) +{ + struct tag *params = *tmp; + struct tag_serialnr serialnr; + void get_board_serial(struct tag_serialnr *serialnr); + + get_board_serial(&serialnr); + params->hdr.tag = ATAG_SERIAL; + params->hdr.size = tag_size (tag_serialnr); + params->u.serialnr.low = serialnr.low; + params->u.serialnr.high= serialnr.high; + params = tag_next (params); + *tmp = params; +} +#endif + +#ifdef CONFIG_REVISION_TAG +void setup_revision_tag(struct tag **in_params) +{ + u32 rev = 0; + u32 get_board_rev(void); + + rev = get_board_rev(); + params->hdr.tag = ATAG_REVISION; + params->hdr.size = tag_size (tag_revision); + params->u.revision.rev = rev; + params = tag_next (params); +} +#endif /* CONFIG_REVISION_TAG */ + + +static void setup_end_tag (bd_t *bd) +{ + params->hdr.tag = ATAG_NONE; + params->hdr.size = 0; +} + +#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ diff --git a/lib_arm/board.c b/lib_arm/board.c new file mode 100644 index 0000000..fa3c92e --- /dev/null +++ b/lib_arm/board.c @@ -0,0 +1,464 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_SMC91111 +#include "../drivers/smc91111.h" +#endif +#ifdef CONFIG_DRIVER_LAN91C96 +#include "../drivers/lan91c96.h" +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +void nand_init (void); +#endif + +ulong monitor_flash_len; + +#ifdef CONFIG_HAS_DATAFLASH +extern int AT91F_DataflashInit(void); +extern void dataflash_print_info(void); +#endif + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +const char version_string[] = + U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"CONFIG_IDENT_STRING; + +#ifdef CONFIG_DRIVER_CS8900 +extern void cs8900_get_enetaddr (uchar * addr); +#endif + +#ifdef CONFIG_DRIVER_RTL8019 +extern void rtl8019_get_enetaddr (uchar * addr); +#endif + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start = 0; +static ulong mem_malloc_end = 0; +static ulong mem_malloc_brk = 0; + +static +void mem_malloc_init (ulong dest_addr) +{ + mem_malloc_start = dest_addr; + mem_malloc_end = dest_addr + CFG_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + + memset ((void *) mem_malloc_start, 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk (ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) { + return (NULL); + } + mem_malloc_brk = new; + + return ((void *) old); +} + +/************************************************************************ + * Init Utilities * + ************************************************************************ + * Some of this code should be moved into the core functions, + * or dropped completely, + * but let's get it working (again) first... + */ + +static int init_baudrate (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uchar tmp[64]; /* long enough for environment variables */ + int i = getenv_r ("baudrate", tmp, sizeof (tmp)); + gd->bd->bi_baudrate = gd->baudrate = (i > 0) + ? (int) simple_strtoul (tmp, NULL, 10) + : CONFIG_BAUDRATE; + + return (0); +} + +static int display_banner (void) +{ + printf ("\n\n%s\n\n", version_string); + printf ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", + _armboot_start, _bss_start, _bss_end); +#ifdef CONFIG_MODEM_SUPPORT + puts ("Modem Support enabled\n"); +#endif +#ifdef CONFIG_USE_IRQ + printf ("IRQ Stack: %08lx\n", IRQ_STACK_START); + printf ("FIQ Stack: %08lx\n", FIQ_STACK_START); +#endif + + return (0); +} + +/* + * WARNING: this code looks "cleaner" than the PowerPC version, but + * has the disadvantage that you either get nothing, or everything. + * On PowerPC, you might see "DRAM: " before the system hangs - which + * gives a simple yet clear indication which part of the + * initialization if failing. + */ +static int display_dram_config (void) +{ + DECLARE_GLOBAL_DATA_PTR; + int i; + + puts ("RAM Configuration:\n"); + + for(i=0; ibd->bi_dram[i].start); + print_size (gd->bd->bi_dram[i].size, "\n"); + } + + return (0); +} + +static void display_flash_config (ulong size) +{ + puts ("Flash: "); + print_size (size, "\n"); +} + + +/* + * Breathe some life into the board... + * + * Initialize a serial port as console, and carry out some hardware + * tests. + * + * The first part of initialization is running from Flash memory; + * its main purpose is to initialize the RAM so that we + * can relocate the monitor code to RAM. + */ + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependent #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ +typedef int (init_fnc_t) (void); + +init_fnc_t *init_sequence[] = { + cpu_init, /* basic cpu dependent setup */ + board_init, /* basic board dependent setup */ + interrupt_init, /* set up exceptions */ + env_init, /* initialize environment */ + init_baudrate, /* initialze baudrate settings */ + serial_init, /* serial communications setup */ + console_init_f, /* stage 1 init of console */ + display_banner, /* say that we are here */ + dram_init, /* configure available RAM banks */ + display_dram_config, +#if defined(CONFIG_VCMA9) || defined (CONFIG_CMC_PU2) + checkboard, +#endif + NULL, +}; + +void start_armboot (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong size; + init_fnc_t **init_fnc_ptr; + char *s; +#if defined(CONFIG_VFD) || defined(CONFIG_LCD) + unsigned long addr; +#endif + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t*)(_armboot_start - CFG_MALLOC_LEN - sizeof(gd_t)); + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset ((void*)gd, 0, sizeof (gd_t)); + gd->bd = (bd_t*)((char*)gd - sizeof(bd_t)); + memset (gd->bd, 0, sizeof (bd_t)); + + monitor_flash_len = _bss_start - _armboot_start; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) { + hang (); + } + } + + /* configure available FLASH banks */ + size = flash_init (); + display_flash_config (size); + +#ifdef CONFIG_VFD +# ifndef PAGE_SIZE +# define PAGE_SIZE 4096 +# endif + /* + * reserve memory for VFD display (always full pages) + */ + /* bss_end is defined in the board-specific linker script */ + addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); + size = vfd_setmem (addr); + gd->fb_base = addr; +#endif /* CONFIG_VFD */ + +#ifdef CONFIG_LCD +# ifndef PAGE_SIZE +# define PAGE_SIZE 4096 +# endif + /* + * reserve memory for LCD display (always full pages) + */ + /* bss_end is defined in the board-specific linker script */ + addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); + size = lcd_setmem (addr); + gd->fb_base = addr; +#endif /* CONFIG_LCD */ + + /* armboot_start is defined in the board-specific linker script */ + mem_malloc_init (_armboot_start - CFG_MALLOC_LEN); + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + puts ("NAND:"); + nand_init(); /* go init the NAND */ +#endif + +#ifdef CONFIG_HAS_DATAFLASH + AT91F_DataflashInit(); + dataflash_print_info(); +#endif + + /* initialize environment */ + env_relocate (); + +#ifdef CONFIG_VFD + /* must do this after the framebuffer is allocated */ + drv_vfd_init(); +#endif /* CONFIG_VFD */ + + /* IP Address */ + gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + + /* MAC Address */ + { + int i; + ulong reg; + char *s, *e; + uchar tmp[64]; + + i = getenv_r ("ethaddr", tmp, sizeof (tmp)); + s = (i > 0) ? tmp : NULL; + + for (reg = 0; reg < 6; ++reg) { + gd->bd->bi_enetaddr[reg] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + } + + devices_init (); /* get the devices list going. */ + +#ifdef CONFIG_CMC_PU2 + load_sernum_ethaddr (); +#endif /* CONFIG_CMC_PU2 */ + + jumptable_init (); + + console_init_r (); /* fully init console as a device */ + +#if defined(CONFIG_MISC_INIT_R) + /* miscellaneous platform dependent initialisations */ + misc_init_r (); +#endif + + /* enable exceptions */ + enable_interrupts (); + + /* Perform network card initialisation if necessary */ +#ifdef CONFIG_DRIVER_CS8900 + cs8900_get_enetaddr (gd->bd->bi_enetaddr); +#endif + +#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) + if (getenv ("ethaddr")) { + smc_set_mac_addr(gd->bd->bi_enetaddr); + } +#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ + + /* Initialize from environment */ + if ((s = getenv ("loadaddr")) != NULL) { + load_addr = simple_strtoul (s, NULL, 16); + } +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif /* CFG_CMD_NET */ + +#ifdef BOARD_LATE_INIT + board_late_init (); +#endif +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); +#endif + eth_initialize(gd->bd); +#endif + /* main_loop() can return to retry autoboot, if so just run it again. */ + for (;;) { + main_loop (); + } + + /* NOTREACHED - no way out of command loop except booting */ +} + +void hang (void) +{ + puts ("### ERROR ### Please RESET the board ###\n"); + for (;;); +} + +#ifdef CONFIG_MODEM_SUPPORT +/* called from main loop (common/main.c) */ +extern void dbg(const char *fmt, ...); +int mdm_init (void) +{ + char env_str[16]; + char *init_str; + int i; + extern char console_buffer[]; + static inline void mdm_readline(char *buf, int bufsiz); + extern void enable_putc(void); + extern int hwflow_onoff(int); + + enable_putc(); /* enable serial_putc() */ + +#ifdef CONFIG_HWFLOW + init_str = getenv("mdm_flow_control"); + if (init_str && (strcmp(init_str, "rts/cts") == 0)) + hwflow_onoff (1); + else + hwflow_onoff(-1); +#endif + + for (i = 1;;i++) { + sprintf(env_str, "mdm_init%d", i); + if ((init_str = getenv(env_str)) != NULL) { + serial_puts(init_str); + serial_puts("\n"); + for(;;) { + mdm_readline(console_buffer, CFG_CBSIZE); + dbg("ini%d: [%s]", i, console_buffer); + + if ((strcmp(console_buffer, "OK") == 0) || + (strcmp(console_buffer, "ERROR") == 0)) { + dbg("ini%d: cmd done", i); + break; + } else /* in case we are originating call ... */ + if (strncmp(console_buffer, "CONNECT", 7) == 0) { + dbg("ini%d: connect", i); + return 0; + } + } + } else + break; /* no init string - stop modem init */ + + udelay(100000); + } + + udelay(100000); + + /* final stage - wait for connect */ + for(;i > 1;) { /* if 'i' > 1 - wait for connection + message from modem */ + mdm_readline(console_buffer, CFG_CBSIZE); + dbg("ini_f: [%s]", console_buffer); + if (strncmp(console_buffer, "CONNECT", 7) == 0) { + dbg("ini_f: connected"); + return 0; + } + } + + return 0; +} + +/* 'inline' - We have to do it fast */ +static inline void mdm_readline(char *buf, int bufsiz) +{ + char c; + char *p; + int n; + + n = 0; + p = buf; + for(;;) { + c = serial_getc(); + + /* dbg("(%c)", c); */ + + switch(c) { + case '\r': + break; + case '\n': + *p = '\0'; + return; + + default: + if(n++ > bufsiz) { + *p = '\0'; + return; /* sanity check */ + } + *p = c; + p++; + break; + } + } +} +#endif /* CONFIG_MODEM_SUPPORT */ diff --git a/lib_arm/cache.c b/lib_arm/cache.c new file mode 100644 index 0000000..61ee9d3 --- /dev/null +++ b/lib_arm/cache.c @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* for now: just dummy functions to satisfy the linker */ + +#include + +void flush_cache (unsigned long dummy1, unsigned long dummy2) +{ +#ifdef CONFIG_OMAP2420 + void arm1136_cache_flush(void); + + arm1136_cache_flush(); +#endif + return; +} diff --git a/lib_arm/div0.c b/lib_arm/div0.c new file mode 100644 index 0000000..6267bf1 --- /dev/null +++ b/lib_arm/div0.c @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Replacement (=dummy) for GNU/Linux division-by zero handler */ +void __div0 (void) +{ + extern void hang (void); + + hang(); +} diff --git a/lib_generic/Makefile b/lib_generic/Makefile new file mode 100644 index 0000000..18c41b1 --- /dev/null +++ b/lib_generic/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libgeneric.a + +OBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \ + bzlib_randtable.o bzlib_huffman.o \ + crc32.o ctype.o display_options.o ldiv.o \ + string.o vsprintf.o zlib.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_generic/bzlib.c b/lib_generic/bzlib.c new file mode 100644 index 0000000..87e6a6e --- /dev/null +++ b/lib_generic/bzlib.c @@ -0,0 +1,1600 @@ +#include +#include +#include +#ifdef CONFIG_BZIP2 + +/* + * This file is a modified version of bzlib.c from the bzip2-1.0.2 + * distribution which can be found at http://sources.redhat.com/bzip2/ + */ + +/*-------------------------------------------------------------*/ +/*--- Library top-level functions. ---*/ +/*--- bzlib.c ---*/ +/*-------------------------------------------------------------*/ + +/*-- + This file is a part of bzip2 and/or libbzip2, a program and + library for lossless, block-sorting data compression. + + Copyright (C) 1996-2002 Julian R Seward. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. The origin of this software must not be misrepresented; you must + not claim that you wrote the original software. If you use this + software in a product, an acknowledgment in the product + documentation would be appreciated but is not required. + + 3. Altered source versions must be plainly marked as such, and must + not be misrepresented as being the original software. + + 4. The name of the author may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Julian Seward, Cambridge, UK. + jseward@acm.org + bzip2/libbzip2 version 1.0 of 21 March 2000 + + This program is based on (at least) the work of: + Mike Burrows + David Wheeler + Peter Fenwick + Alistair Moffat + Radford Neal + Ian H. Witten + Robert Sedgewick + Jon L. Bentley + + For more information on these sources, see the manual. +--*/ + +/*-- + CHANGES + ~~~~~~~ + 0.9.0 -- original version. + + 0.9.0a/b -- no changes in this file. + + 0.9.0c + * made zero-length BZ_FLUSH work correctly in bzCompress(). + * fixed bzWrite/bzRead to ignore zero-length requests. + * fixed bzread to correctly handle read requests after EOF. + * wrong parameter order in call to bzDecompressInit in + bzBuffToBuffDecompress. Fixed. +--*/ + +#include "bzlib_private.h" + +/*---------------------------------------------------*/ +/*--- Compression stuff ---*/ +/*---------------------------------------------------*/ + + +/*---------------------------------------------------*/ +#ifndef BZ_NO_STDIO +void BZ2_bz__AssertH__fail ( int errcode ) +{ + fprintf(stderr, + "\n\nbzip2/libbzip2: internal error number %d.\n" + "This is a bug in bzip2/libbzip2, %s.\n" + "Please report it to me at: jseward@acm.org. If this happened\n" + "when you were using some program which uses libbzip2 as a\n" + "component, you should also report this bug to the author(s)\n" + "of that program. Please make an effort to report this bug;\n" + "timely and accurate bug reports eventually lead to higher\n" + "quality software. Thanks. Julian Seward, 30 December 2001.\n\n", + errcode, + BZ2_bzlibVersion() + ); + + if (errcode == 1007) { + fprintf(stderr, + "\n*** A special note about internal error number 1007 ***\n" + "\n" + "Experience suggests that a common cause of i.e. 1007\n" + "is unreliable memory or other hardware. The 1007 assertion\n" + "just happens to cross-check the results of huge numbers of\n" + "memory reads/writes, and so acts (unintendedly) as a stress\n" + "test of your memory system.\n" + "\n" + "I suggest the following: try compressing the file again,\n" + "possibly monitoring progress in detail with the -vv flag.\n" + "\n" + "* If the error cannot be reproduced, and/or happens at different\n" + " points in compression, you may have a flaky memory system.\n" + " Try a memory-test program. I have used Memtest86\n" + " (www.memtest86.com). At the time of writing it is free (GPLd).\n" + " Memtest86 tests memory much more thorougly than your BIOSs\n" + " power-on test, and may find failures that the BIOS doesn't.\n" + "\n" + "* If the error can be repeatably reproduced, this is a bug in\n" + " bzip2, and I would very much like to hear about it. Please\n" + " let me know, and, ideally, save a copy of the file causing the\n" + " problem -- without which I will be unable to investigate it.\n" + "\n" + ); + } + + exit(3); +} +#endif + + +/*---------------------------------------------------*/ +static +int bz_config_ok ( void ) +{ + if (sizeof(int) != 4) return 0; + if (sizeof(short) != 2) return 0; + if (sizeof(char) != 1) return 0; + return 1; +} + + +/*---------------------------------------------------*/ +static +void* default_bzalloc ( void* opaque, Int32 items, Int32 size ) +{ + void* v = malloc ( items * size ); + return v; +} + +static +void default_bzfree ( void* opaque, void* addr ) +{ + if (addr != NULL) free ( addr ); +} + +#ifndef BZ_NO_COMPRESS +/*---------------------------------------------------*/ +static +void prepare_new_block ( EState* s ) +{ + Int32 i; + s->nblock = 0; + s->numZ = 0; + s->state_out_pos = 0; + BZ_INITIALISE_CRC ( s->blockCRC ); + for (i = 0; i < 256; i++) s->inUse[i] = False; + s->blockNo++; +} + + +/*---------------------------------------------------*/ +static +void init_RL ( EState* s ) +{ + s->state_in_ch = 256; + s->state_in_len = 0; +} + + +static +Bool isempty_RL ( EState* s ) +{ + if (s->state_in_ch < 256 && s->state_in_len > 0) + return False; else + return True; +} + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzCompressInit) + ( bz_stream* strm, + int blockSize100k, + int verbosity, + int workFactor ) +{ + Int32 n; + EState* s; + + if (!bz_config_ok()) return BZ_CONFIG_ERROR; + + if (strm == NULL || + blockSize100k < 1 || blockSize100k > 9 || + workFactor < 0 || workFactor > 250) + return BZ_PARAM_ERROR; + + if (workFactor == 0) workFactor = 30; + if (strm->bzalloc == NULL) strm->bzalloc = default_bzalloc; + if (strm->bzfree == NULL) strm->bzfree = default_bzfree; + + s = BZALLOC( sizeof(EState) ); + if (s == NULL) return BZ_MEM_ERROR; + s->strm = strm; + + s->arr1 = NULL; + s->arr2 = NULL; + s->ftab = NULL; + + n = 100000 * blockSize100k; + s->arr1 = BZALLOC( n * sizeof(UInt32) ); + s->arr2 = BZALLOC( (n+BZ_N_OVERSHOOT) * sizeof(UInt32) ); + s->ftab = BZALLOC( 65537 * sizeof(UInt32) ); + + if (s->arr1 == NULL || s->arr2 == NULL || s->ftab == NULL) { + if (s->arr1 != NULL) BZFREE(s->arr1); + if (s->arr2 != NULL) BZFREE(s->arr2); + if (s->ftab != NULL) BZFREE(s->ftab); + if (s != NULL) BZFREE(s); + return BZ_MEM_ERROR; + } + + s->blockNo = 0; + s->state = BZ_S_INPUT; + s->mode = BZ_M_RUNNING; + s->combinedCRC = 0; + s->blockSize100k = blockSize100k; + s->nblockMAX = 100000 * blockSize100k - 19; + s->verbosity = verbosity; + s->workFactor = workFactor; + + s->block = (UChar*)s->arr2; + s->mtfv = (UInt16*)s->arr1; + s->zbits = NULL; + s->ptr = (UInt32*)s->arr1; + + strm->state = s; + strm->total_in_lo32 = 0; + strm->total_in_hi32 = 0; + strm->total_out_lo32 = 0; + strm->total_out_hi32 = 0; + init_RL ( s ); + prepare_new_block ( s ); + return BZ_OK; +} + + +/*---------------------------------------------------*/ +static +void add_pair_to_block ( EState* s ) +{ + Int32 i; + UChar ch = (UChar)(s->state_in_ch); + for (i = 0; i < s->state_in_len; i++) { + BZ_UPDATE_CRC( s->blockCRC, ch ); + } + s->inUse[s->state_in_ch] = True; + switch (s->state_in_len) { + case 1: + s->block[s->nblock] = (UChar)ch; s->nblock++; + break; + case 2: + s->block[s->nblock] = (UChar)ch; s->nblock++; + s->block[s->nblock] = (UChar)ch; s->nblock++; + break; + case 3: + s->block[s->nblock] = (UChar)ch; s->nblock++; + s->block[s->nblock] = (UChar)ch; s->nblock++; + s->block[s->nblock] = (UChar)ch; s->nblock++; + break; + default: + s->inUse[s->state_in_len-4] = True; + s->block[s->nblock] = (UChar)ch; s->nblock++; + s->block[s->nblock] = (UChar)ch; s->nblock++; + s->block[s->nblock] = (UChar)ch; s->nblock++; + s->block[s->nblock] = (UChar)ch; s->nblock++; + s->block[s->nblock] = ((UChar)(s->state_in_len-4)); + s->nblock++; + break; + } +} + + +/*---------------------------------------------------*/ +static +void flush_RL ( EState* s ) +{ + if (s->state_in_ch < 256) add_pair_to_block ( s ); + init_RL ( s ); +} + + +/*---------------------------------------------------*/ +#define ADD_CHAR_TO_BLOCK(zs,zchh0) \ +{ \ + UInt32 zchh = (UInt32)(zchh0); \ + /*-- fast track the common case --*/ \ + if (zchh != zs->state_in_ch && \ + zs->state_in_len == 1) { \ + UChar ch = (UChar)(zs->state_in_ch); \ + BZ_UPDATE_CRC( zs->blockCRC, ch ); \ + zs->inUse[zs->state_in_ch] = True; \ + zs->block[zs->nblock] = (UChar)ch; \ + zs->nblock++; \ + zs->state_in_ch = zchh; \ + } \ + else \ + /*-- general, uncommon cases --*/ \ + if (zchh != zs->state_in_ch || \ + zs->state_in_len == 255) { \ + if (zs->state_in_ch < 256) \ + add_pair_to_block ( zs ); \ + zs->state_in_ch = zchh; \ + zs->state_in_len = 1; \ + } else { \ + zs->state_in_len++; \ + } \ +} + + +/*---------------------------------------------------*/ +static +Bool copy_input_until_stop ( EState* s ) +{ + Bool progress_in = False; + + if (s->mode == BZ_M_RUNNING) { + + /*-- fast track the common case --*/ + while (True) { + /*-- block full? --*/ + if (s->nblock >= s->nblockMAX) break; + /*-- no input? --*/ + if (s->strm->avail_in == 0) break; + progress_in = True; + ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) ); + s->strm->next_in++; + s->strm->avail_in--; + s->strm->total_in_lo32++; + if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++; + } + + } else { + + /*-- general, uncommon case --*/ + while (True) { + /*-- block full? --*/ + if (s->nblock >= s->nblockMAX) break; + /*-- no input? --*/ + if (s->strm->avail_in == 0) break; + /*-- flush/finish end? --*/ + if (s->avail_in_expect == 0) break; + progress_in = True; + ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) ); + s->strm->next_in++; + s->strm->avail_in--; + s->strm->total_in_lo32++; + if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++; + s->avail_in_expect--; + } + } + return progress_in; +} + + +/*---------------------------------------------------*/ +static +Bool copy_output_until_stop ( EState* s ) +{ + Bool progress_out = False; + + while (True) { + + /*-- no output space? --*/ + if (s->strm->avail_out == 0) break; + + /*-- block done? --*/ + if (s->state_out_pos >= s->numZ) break; + + progress_out = True; + *(s->strm->next_out) = s->zbits[s->state_out_pos]; + s->state_out_pos++; + s->strm->avail_out--; + s->strm->next_out++; + s->strm->total_out_lo32++; + if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++; + } + + return progress_out; +} + + +/*---------------------------------------------------*/ +static +Bool handle_compress ( bz_stream* strm ) +{ + Bool progress_in = False; + Bool progress_out = False; + EState* s = strm->state; + + while (True) { + + if (s->state == BZ_S_OUTPUT) { + progress_out |= copy_output_until_stop ( s ); + if (s->state_out_pos < s->numZ) break; + if (s->mode == BZ_M_FINISHING && + s->avail_in_expect == 0 && + isempty_RL(s)) break; + prepare_new_block ( s ); + s->state = BZ_S_INPUT; + if (s->mode == BZ_M_FLUSHING && + s->avail_in_expect == 0 && + isempty_RL(s)) break; + } + + if (s->state == BZ_S_INPUT) { + progress_in |= copy_input_until_stop ( s ); + if (s->mode != BZ_M_RUNNING && s->avail_in_expect == 0) { + flush_RL ( s ); + BZ2_compressBlock ( s, (Bool)(s->mode == BZ_M_FINISHING) ); + s->state = BZ_S_OUTPUT; + } + else + if (s->nblock >= s->nblockMAX) { + BZ2_compressBlock ( s, False ); + s->state = BZ_S_OUTPUT; + } + else + if (s->strm->avail_in == 0) { + break; + } + } + + } + + return progress_in || progress_out; +} + + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzCompress) ( bz_stream *strm, int action ) +{ + Bool progress; + EState* s; + if (strm == NULL) return BZ_PARAM_ERROR; + s = strm->state; + if (s == NULL) return BZ_PARAM_ERROR; + if (s->strm != strm) return BZ_PARAM_ERROR; + + preswitch: + switch (s->mode) { + + case BZ_M_IDLE: + return BZ_SEQUENCE_ERROR; + + case BZ_M_RUNNING: + if (action == BZ_RUN) { + progress = handle_compress ( strm ); + return progress ? BZ_RUN_OK : BZ_PARAM_ERROR; + } + else + if (action == BZ_FLUSH) { + s->avail_in_expect = strm->avail_in; + s->mode = BZ_M_FLUSHING; + goto preswitch; + } + else + if (action == BZ_FINISH) { + s->avail_in_expect = strm->avail_in; + s->mode = BZ_M_FINISHING; + goto preswitch; + } + else + return BZ_PARAM_ERROR; + + case BZ_M_FLUSHING: + if (action != BZ_FLUSH) return BZ_SEQUENCE_ERROR; + if (s->avail_in_expect != s->strm->avail_in) + return BZ_SEQUENCE_ERROR; + progress = handle_compress ( strm ); + if (s->avail_in_expect > 0 || !isempty_RL(s) || + s->state_out_pos < s->numZ) return BZ_FLUSH_OK; + s->mode = BZ_M_RUNNING; + return BZ_RUN_OK; + + case BZ_M_FINISHING: + if (action != BZ_FINISH) return BZ_SEQUENCE_ERROR; + if (s->avail_in_expect != s->strm->avail_in) + return BZ_SEQUENCE_ERROR; + progress = handle_compress ( strm ); + if (!progress) return BZ_SEQUENCE_ERROR; + if (s->avail_in_expect > 0 || !isempty_RL(s) || + s->state_out_pos < s->numZ) return BZ_FINISH_OK; + s->mode = BZ_M_IDLE; + return BZ_STREAM_END; + } + return BZ_OK; /*--not reached--*/ +} + + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzCompressEnd) ( bz_stream *strm ) +{ + EState* s; + if (strm == NULL) return BZ_PARAM_ERROR; + s = strm->state; + if (s == NULL) return BZ_PARAM_ERROR; + if (s->strm != strm) return BZ_PARAM_ERROR; + + if (s->arr1 != NULL) BZFREE(s->arr1); + if (s->arr2 != NULL) BZFREE(s->arr2); + if (s->ftab != NULL) BZFREE(s->ftab); + BZFREE(strm->state); + + strm->state = NULL; + + return BZ_OK; +} +#endif /* BZ_NO_COMPRESS */ + +/*---------------------------------------------------*/ +/*--- Decompression stuff ---*/ +/*---------------------------------------------------*/ + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzDecompressInit) + ( bz_stream* strm, + int verbosity, + int small ) +{ + DState* s; + + if (!bz_config_ok()) return BZ_CONFIG_ERROR; + + if (strm == NULL) return BZ_PARAM_ERROR; + if (small != 0 && small != 1) return BZ_PARAM_ERROR; + if (verbosity < 0 || verbosity > 4) return BZ_PARAM_ERROR; + + if (strm->bzalloc == NULL) strm->bzalloc = default_bzalloc; + if (strm->bzfree == NULL) strm->bzfree = default_bzfree; + + s = BZALLOC( sizeof(DState) ); + if (s == NULL) return BZ_MEM_ERROR; + s->strm = strm; + strm->state = s; + s->state = BZ_X_MAGIC_1; + s->bsLive = 0; + s->bsBuff = 0; + s->calculatedCombinedCRC = 0; + strm->total_in_lo32 = 0; + strm->total_in_hi32 = 0; + strm->total_out_lo32 = 0; + strm->total_out_hi32 = 0; + s->smallDecompress = (Bool)small; + s->ll4 = NULL; + s->ll16 = NULL; + s->tt = NULL; + s->currBlockNo = 0; + s->verbosity = verbosity; + + return BZ_OK; +} + + +/*---------------------------------------------------*/ +static +void unRLE_obuf_to_output_FAST ( DState* s ) +{ + UChar k1; + + if (s->blockRandomised) { + + while (True) { + /* try to finish existing run */ + while (True) { + if (s->strm->avail_out == 0) return; + if (s->state_out_len == 0) break; + *( (UChar*)(s->strm->next_out) ) = s->state_out_ch; + BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch ); + s->state_out_len--; + s->strm->next_out++; + s->strm->avail_out--; + s->strm->total_out_lo32++; + if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++; + } + + /* can a new run be started? */ + if (s->nblock_used == s->save_nblock+1) return; + + + s->state_out_len = 1; + s->state_out_ch = s->k0; + BZ_GET_FAST(k1); BZ_RAND_UPD_MASK; + k1 ^= BZ_RAND_MASK; s->nblock_used++; + if (s->nblock_used == s->save_nblock+1) continue; + if (k1 != s->k0) { s->k0 = k1; continue; }; + + s->state_out_len = 2; + BZ_GET_FAST(k1); BZ_RAND_UPD_MASK; + k1 ^= BZ_RAND_MASK; s->nblock_used++; + if (s->nblock_used == s->save_nblock+1) continue; + if (k1 != s->k0) { s->k0 = k1; continue; }; + + s->state_out_len = 3; + BZ_GET_FAST(k1); BZ_RAND_UPD_MASK; + k1 ^= BZ_RAND_MASK; s->nblock_used++; + if (s->nblock_used == s->save_nblock+1) continue; + if (k1 != s->k0) { s->k0 = k1; continue; }; + + BZ_GET_FAST(k1); BZ_RAND_UPD_MASK; + k1 ^= BZ_RAND_MASK; s->nblock_used++; + s->state_out_len = ((Int32)k1) + 4; + BZ_GET_FAST(s->k0); BZ_RAND_UPD_MASK; + s->k0 ^= BZ_RAND_MASK; s->nblock_used++; + } + + } else { + + /* restore */ + UInt32 c_calculatedBlockCRC = s->calculatedBlockCRC; + UChar c_state_out_ch = s->state_out_ch; + Int32 c_state_out_len = s->state_out_len; + Int32 c_nblock_used = s->nblock_used; + Int32 c_k0 = s->k0; + UInt32* c_tt = s->tt; + UInt32 c_tPos = s->tPos; + char* cs_next_out = s->strm->next_out; + unsigned int cs_avail_out = s->strm->avail_out; + /* end restore */ + + UInt32 avail_out_INIT = cs_avail_out; + Int32 s_save_nblockPP = s->save_nblock+1; + unsigned int total_out_lo32_old; + + while (True) { + + /* try to finish existing run */ + if (c_state_out_len > 0) { + while (True) { + if (cs_avail_out == 0) goto return_notr; + if (c_state_out_len == 1) break; + *( (UChar*)(cs_next_out) ) = c_state_out_ch; + BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch ); + c_state_out_len--; + cs_next_out++; + cs_avail_out--; + } + s_state_out_len_eq_one: + { + if (cs_avail_out == 0) { + c_state_out_len = 1; goto return_notr; + }; + *( (UChar*)(cs_next_out) ) = c_state_out_ch; + BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch ); + cs_next_out++; + cs_avail_out--; + } + } + /* can a new run be started? */ + if (c_nblock_used == s_save_nblockPP) { + c_state_out_len = 0; goto return_notr; + }; + c_state_out_ch = c_k0; + BZ_GET_FAST_C(k1); c_nblock_used++; + if (k1 != c_k0) { + c_k0 = k1; goto s_state_out_len_eq_one; + }; + if (c_nblock_used == s_save_nblockPP) + goto s_state_out_len_eq_one; + + c_state_out_len = 2; + BZ_GET_FAST_C(k1); c_nblock_used++; + if (c_nblock_used == s_save_nblockPP) continue; + if (k1 != c_k0) { c_k0 = k1; continue; }; + + c_state_out_len = 3; + BZ_GET_FAST_C(k1); c_nblock_used++; + if (c_nblock_used == s_save_nblockPP) continue; + if (k1 != c_k0) { c_k0 = k1; continue; }; + + BZ_GET_FAST_C(k1); c_nblock_used++; + c_state_out_len = ((Int32)k1) + 4; + BZ_GET_FAST_C(c_k0); c_nblock_used++; + } + + return_notr: + total_out_lo32_old = s->strm->total_out_lo32; + s->strm->total_out_lo32 += (avail_out_INIT - cs_avail_out); + if (s->strm->total_out_lo32 < total_out_lo32_old) + s->strm->total_out_hi32++; + + /* save */ + s->calculatedBlockCRC = c_calculatedBlockCRC; + s->state_out_ch = c_state_out_ch; + s->state_out_len = c_state_out_len; + s->nblock_used = c_nblock_used; + s->k0 = c_k0; + s->tt = c_tt; + s->tPos = c_tPos; + s->strm->next_out = cs_next_out; + s->strm->avail_out = cs_avail_out; + /* end save */ + } +} + + +/*---------------------------------------------------*/ +__inline__ Int32 BZ2_indexIntoF ( Int32 indx, Int32 *cftab ) +{ + Int32 nb, na, mid; + nb = 0; + na = 256; + do { + mid = (nb + na) >> 1; + if (indx >= cftab[mid]) nb = mid; else na = mid; + } + while (na - nb != 1); + return nb; +} + + +/*---------------------------------------------------*/ +static +void unRLE_obuf_to_output_SMALL ( DState* s ) +{ + UChar k1; + + if (s->blockRandomised) { + + while (True) { + /* try to finish existing run */ + while (True) { + if (s->strm->avail_out == 0) return; + if (s->state_out_len == 0) break; + *( (UChar*)(s->strm->next_out) ) = s->state_out_ch; + BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch ); + s->state_out_len--; + s->strm->next_out++; + s->strm->avail_out--; + s->strm->total_out_lo32++; + if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++; + } + + /* can a new run be started? */ + if (s->nblock_used == s->save_nblock+1) return; + + + s->state_out_len = 1; + s->state_out_ch = s->k0; + BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK; + k1 ^= BZ_RAND_MASK; s->nblock_used++; + if (s->nblock_used == s->save_nblock+1) continue; + if (k1 != s->k0) { s->k0 = k1; continue; }; + + s->state_out_len = 2; + BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK; + k1 ^= BZ_RAND_MASK; s->nblock_used++; + if (s->nblock_used == s->save_nblock+1) continue; + if (k1 != s->k0) { s->k0 = k1; continue; }; + + s->state_out_len = 3; + BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK; + k1 ^= BZ_RAND_MASK; s->nblock_used++; + if (s->nblock_used == s->save_nblock+1) continue; + if (k1 != s->k0) { s->k0 = k1; continue; }; + + BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK; + k1 ^= BZ_RAND_MASK; s->nblock_used++; + s->state_out_len = ((Int32)k1) + 4; + BZ_GET_SMALL(s->k0); BZ_RAND_UPD_MASK; + s->k0 ^= BZ_RAND_MASK; s->nblock_used++; + } + + } else { + + while (True) { + /* try to finish existing run */ + while (True) { + if (s->strm->avail_out == 0) return; + if (s->state_out_len == 0) break; + *( (UChar*)(s->strm->next_out) ) = s->state_out_ch; + BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch ); + s->state_out_len--; + s->strm->next_out++; + s->strm->avail_out--; + s->strm->total_out_lo32++; + if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++; + } + + /* can a new run be started? */ + if (s->nblock_used == s->save_nblock+1) return; + + s->state_out_len = 1; + s->state_out_ch = s->k0; + BZ_GET_SMALL(k1); s->nblock_used++; + if (s->nblock_used == s->save_nblock+1) continue; + if (k1 != s->k0) { s->k0 = k1; continue; }; + + s->state_out_len = 2; + BZ_GET_SMALL(k1); s->nblock_used++; + if (s->nblock_used == s->save_nblock+1) continue; + if (k1 != s->k0) { s->k0 = k1; continue; }; + + s->state_out_len = 3; + BZ_GET_SMALL(k1); s->nblock_used++; + if (s->nblock_used == s->save_nblock+1) continue; + if (k1 != s->k0) { s->k0 = k1; continue; }; + + BZ_GET_SMALL(k1); s->nblock_used++; + s->state_out_len = ((Int32)k1) + 4; + BZ_GET_SMALL(s->k0); s->nblock_used++; + } + + } +} + + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzDecompress) ( bz_stream *strm ) +{ + DState* s; + if (strm == NULL) return BZ_PARAM_ERROR; + s = strm->state; + if (s == NULL) return BZ_PARAM_ERROR; + if (s->strm != strm) return BZ_PARAM_ERROR; + + while (True) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif + if (s->state == BZ_X_IDLE) return BZ_SEQUENCE_ERROR; + if (s->state == BZ_X_OUTPUT) { + if (s->smallDecompress) + unRLE_obuf_to_output_SMALL ( s ); else + unRLE_obuf_to_output_FAST ( s ); + if (s->nblock_used == s->save_nblock+1 && s->state_out_len == 0) { + BZ_FINALISE_CRC ( s->calculatedBlockCRC ); + if (s->verbosity >= 3) + VPrintf2 ( " {0x%x, 0x%x}", s->storedBlockCRC, + s->calculatedBlockCRC ); + if (s->verbosity >= 2) VPrintf0 ( "]" ); + if (s->calculatedBlockCRC != s->storedBlockCRC) + return BZ_DATA_ERROR; + s->calculatedCombinedCRC + = (s->calculatedCombinedCRC << 1) | + (s->calculatedCombinedCRC >> 31); + s->calculatedCombinedCRC ^= s->calculatedBlockCRC; + s->state = BZ_X_BLKHDR_1; + } else { + return BZ_OK; + } + } + if (s->state >= BZ_X_MAGIC_1) { + Int32 r = BZ2_decompress ( s ); + if (r == BZ_STREAM_END) { + if (s->verbosity >= 3) + VPrintf2 ( "\n combined CRCs: stored = 0x%x, computed = 0x%x", + s->storedCombinedCRC, s->calculatedCombinedCRC ); + if (s->calculatedCombinedCRC != s->storedCombinedCRC) + return BZ_DATA_ERROR; + return r; + } + if (s->state != BZ_X_OUTPUT) return r; + } + } + + AssertH ( 0, 6001 ); + + return 0; /*NOTREACHED*/ +} + + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzDecompressEnd) ( bz_stream *strm ) +{ + DState* s; + if (strm == NULL) return BZ_PARAM_ERROR; + s = strm->state; + if (s == NULL) return BZ_PARAM_ERROR; + if (s->strm != strm) return BZ_PARAM_ERROR; + + if (s->tt != NULL) BZFREE(s->tt); + if (s->ll16 != NULL) BZFREE(s->ll16); + if (s->ll4 != NULL) BZFREE(s->ll4); + + BZFREE(strm->state); + strm->state = NULL; + + return BZ_OK; +} + + +#ifndef BZ_NO_STDIO +/*---------------------------------------------------*/ +/*--- File I/O stuff ---*/ +/*---------------------------------------------------*/ + +#define BZ_SETERR(eee) \ +{ \ + if (bzerror != NULL) *bzerror = eee; \ + if (bzf != NULL) bzf->lastErr = eee; \ +} + +typedef + struct { + FILE* handle; + Char buf[BZ_MAX_UNUSED]; + Int32 bufN; + Bool writing; + bz_stream strm; + Int32 lastErr; + Bool initialisedOk; + } + bzFile; + + +/*---------------------------------------------*/ +static Bool myfeof ( FILE* f ) +{ + Int32 c = fgetc ( f ); + if (c == EOF) return True; + ungetc ( c, f ); + return False; +} + + +/*---------------------------------------------------*/ +BZFILE* BZ_API(BZ2_bzWriteOpen) + ( int* bzerror, + FILE* f, + int blockSize100k, + int verbosity, + int workFactor ) +{ + Int32 ret; + bzFile* bzf = NULL; + + BZ_SETERR(BZ_OK); + + if (f == NULL || + (blockSize100k < 1 || blockSize100k > 9) || + (workFactor < 0 || workFactor > 250) || + (verbosity < 0 || verbosity > 4)) + { BZ_SETERR(BZ_PARAM_ERROR); return NULL; }; + + if (ferror(f)) + { BZ_SETERR(BZ_IO_ERROR); return NULL; }; + + bzf = malloc ( sizeof(bzFile) ); + if (bzf == NULL) + { BZ_SETERR(BZ_MEM_ERROR); return NULL; }; + + BZ_SETERR(BZ_OK); + bzf->initialisedOk = False; + bzf->bufN = 0; + bzf->handle = f; + bzf->writing = True; + bzf->strm.bzalloc = NULL; + bzf->strm.bzfree = NULL; + bzf->strm.opaque = NULL; + + if (workFactor == 0) workFactor = 30; + ret = BZ2_bzCompressInit ( &(bzf->strm), blockSize100k, + verbosity, workFactor ); + if (ret != BZ_OK) + { BZ_SETERR(ret); free(bzf); return NULL; }; + + bzf->strm.avail_in = 0; + bzf->initialisedOk = True; + return bzf; +} + + +/*---------------------------------------------------*/ +void BZ_API(BZ2_bzWrite) + ( int* bzerror, + BZFILE* b, + void* buf, + int len ) +{ + Int32 n, n2, ret; + bzFile* bzf = (bzFile*)b; + + BZ_SETERR(BZ_OK); + if (bzf == NULL || buf == NULL || len < 0) + { BZ_SETERR(BZ_PARAM_ERROR); return; }; + if (!(bzf->writing)) + { BZ_SETERR(BZ_SEQUENCE_ERROR); return; }; + if (ferror(bzf->handle)) + { BZ_SETERR(BZ_IO_ERROR); return; }; + + if (len == 0) + { BZ_SETERR(BZ_OK); return; }; + + bzf->strm.avail_in = len; + bzf->strm.next_in = buf; + + while (True) { + bzf->strm.avail_out = BZ_MAX_UNUSED; + bzf->strm.next_out = bzf->buf; + ret = BZ2_bzCompress ( &(bzf->strm), BZ_RUN ); + if (ret != BZ_RUN_OK) + { BZ_SETERR(ret); return; }; + + if (bzf->strm.avail_out < BZ_MAX_UNUSED) { + n = BZ_MAX_UNUSED - bzf->strm.avail_out; + n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar), + n, bzf->handle ); + if (n != n2 || ferror(bzf->handle)) + { BZ_SETERR(BZ_IO_ERROR); return; }; + } + + if (bzf->strm.avail_in == 0) + { BZ_SETERR(BZ_OK); return; }; + } +} + + +/*---------------------------------------------------*/ +void BZ_API(BZ2_bzWriteClose) + ( int* bzerror, + BZFILE* b, + int abandon, + unsigned int* nbytes_in, + unsigned int* nbytes_out ) +{ + BZ2_bzWriteClose64 ( bzerror, b, abandon, + nbytes_in, NULL, nbytes_out, NULL ); +} + + +void BZ_API(BZ2_bzWriteClose64) + ( int* bzerror, + BZFILE* b, + int abandon, + unsigned int* nbytes_in_lo32, + unsigned int* nbytes_in_hi32, + unsigned int* nbytes_out_lo32, + unsigned int* nbytes_out_hi32 ) +{ + Int32 n, n2, ret; + bzFile* bzf = (bzFile*)b; + + if (bzf == NULL) + { BZ_SETERR(BZ_OK); return; }; + if (!(bzf->writing)) + { BZ_SETERR(BZ_SEQUENCE_ERROR); return; }; + if (ferror(bzf->handle)) + { BZ_SETERR(BZ_IO_ERROR); return; }; + + if (nbytes_in_lo32 != NULL) *nbytes_in_lo32 = 0; + if (nbytes_in_hi32 != NULL) *nbytes_in_hi32 = 0; + if (nbytes_out_lo32 != NULL) *nbytes_out_lo32 = 0; + if (nbytes_out_hi32 != NULL) *nbytes_out_hi32 = 0; + + if ((!abandon) && bzf->lastErr == BZ_OK) { + while (True) { + bzf->strm.avail_out = BZ_MAX_UNUSED; + bzf->strm.next_out = bzf->buf; + ret = BZ2_bzCompress ( &(bzf->strm), BZ_FINISH ); + if (ret != BZ_FINISH_OK && ret != BZ_STREAM_END) + { BZ_SETERR(ret); return; }; + + if (bzf->strm.avail_out < BZ_MAX_UNUSED) { + n = BZ_MAX_UNUSED - bzf->strm.avail_out; + n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar), + n, bzf->handle ); + if (n != n2 || ferror(bzf->handle)) + { BZ_SETERR(BZ_IO_ERROR); return; }; + } + + if (ret == BZ_STREAM_END) break; + } + } + + if ( !abandon && !ferror ( bzf->handle ) ) { + fflush ( bzf->handle ); + if (ferror(bzf->handle)) + { BZ_SETERR(BZ_IO_ERROR); return; }; + } + + if (nbytes_in_lo32 != NULL) + *nbytes_in_lo32 = bzf->strm.total_in_lo32; + if (nbytes_in_hi32 != NULL) + *nbytes_in_hi32 = bzf->strm.total_in_hi32; + if (nbytes_out_lo32 != NULL) + *nbytes_out_lo32 = bzf->strm.total_out_lo32; + if (nbytes_out_hi32 != NULL) + *nbytes_out_hi32 = bzf->strm.total_out_hi32; + + BZ_SETERR(BZ_OK); + BZ2_bzCompressEnd ( &(bzf->strm) ); + free ( bzf ); +} + + +/*---------------------------------------------------*/ +BZFILE* BZ_API(BZ2_bzReadOpen) + ( int* bzerror, + FILE* f, + int verbosity, + int small, + void* unused, + int nUnused ) +{ + bzFile* bzf = NULL; + int ret; + + BZ_SETERR(BZ_OK); + + if (f == NULL || + (small != 0 && small != 1) || + (verbosity < 0 || verbosity > 4) || + (unused == NULL && nUnused != 0) || + (unused != NULL && (nUnused < 0 || nUnused > BZ_MAX_UNUSED))) + { BZ_SETERR(BZ_PARAM_ERROR); return NULL; }; + + if (ferror(f)) + { BZ_SETERR(BZ_IO_ERROR); return NULL; }; + + bzf = malloc ( sizeof(bzFile) ); + if (bzf == NULL) + { BZ_SETERR(BZ_MEM_ERROR); return NULL; }; + + BZ_SETERR(BZ_OK); + + bzf->initialisedOk = False; + bzf->handle = f; + bzf->bufN = 0; + bzf->writing = False; + bzf->strm.bzalloc = NULL; + bzf->strm.bzfree = NULL; + bzf->strm.opaque = NULL; + + while (nUnused > 0) { + bzf->buf[bzf->bufN] = *((UChar*)(unused)); bzf->bufN++; + unused = ((void*)( 1 + ((UChar*)(unused)) )); + nUnused--; + } + + ret = BZ2_bzDecompressInit ( &(bzf->strm), verbosity, small ); + if (ret != BZ_OK) + { BZ_SETERR(ret); free(bzf); return NULL; }; + + bzf->strm.avail_in = bzf->bufN; + bzf->strm.next_in = bzf->buf; + + bzf->initialisedOk = True; + return bzf; +} + + +/*---------------------------------------------------*/ +void BZ_API(BZ2_bzReadClose) ( int *bzerror, BZFILE *b ) +{ + bzFile* bzf = (bzFile*)b; + + BZ_SETERR(BZ_OK); + if (bzf == NULL) + { BZ_SETERR(BZ_OK); return; }; + + if (bzf->writing) + { BZ_SETERR(BZ_SEQUENCE_ERROR); return; }; + + if (bzf->initialisedOk) + (void)BZ2_bzDecompressEnd ( &(bzf->strm) ); + free ( bzf ); +} + + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzRead) + ( int* bzerror, + BZFILE* b, + void* buf, + int len ) +{ + Int32 n, ret; + bzFile* bzf = (bzFile*)b; + + BZ_SETERR(BZ_OK); + + if (bzf == NULL || buf == NULL || len < 0) + { BZ_SETERR(BZ_PARAM_ERROR); return 0; }; + + if (bzf->writing) + { BZ_SETERR(BZ_SEQUENCE_ERROR); return 0; }; + + if (len == 0) + { BZ_SETERR(BZ_OK); return 0; }; + + bzf->strm.avail_out = len; + bzf->strm.next_out = buf; + + while (True) { + + if (ferror(bzf->handle)) + { BZ_SETERR(BZ_IO_ERROR); return 0; }; + + if (bzf->strm.avail_in == 0 && !myfeof(bzf->handle)) { + n = fread ( bzf->buf, sizeof(UChar), + BZ_MAX_UNUSED, bzf->handle ); + if (ferror(bzf->handle)) + { BZ_SETERR(BZ_IO_ERROR); return 0; }; + bzf->bufN = n; + bzf->strm.avail_in = bzf->bufN; + bzf->strm.next_in = bzf->buf; + } + + ret = BZ2_bzDecompress ( &(bzf->strm) ); + + if (ret != BZ_OK && ret != BZ_STREAM_END) + { BZ_SETERR(ret); return 0; }; + + if (ret == BZ_OK && myfeof(bzf->handle) && + bzf->strm.avail_in == 0 && bzf->strm.avail_out > 0) + { BZ_SETERR(BZ_UNEXPECTED_EOF); return 0; }; + + if (ret == BZ_STREAM_END) + { BZ_SETERR(BZ_STREAM_END); + return len - bzf->strm.avail_out; }; + if (bzf->strm.avail_out == 0) + { BZ_SETERR(BZ_OK); return len; }; + + } + + return 0; /*not reached*/ +} + + +/*---------------------------------------------------*/ +void BZ_API(BZ2_bzReadGetUnused) + ( int* bzerror, + BZFILE* b, + void** unused, + int* nUnused ) +{ + bzFile* bzf = (bzFile*)b; + if (bzf == NULL) + { BZ_SETERR(BZ_PARAM_ERROR); return; }; + if (bzf->lastErr != BZ_STREAM_END) + { BZ_SETERR(BZ_SEQUENCE_ERROR); return; }; + if (unused == NULL || nUnused == NULL) + { BZ_SETERR(BZ_PARAM_ERROR); return; }; + + BZ_SETERR(BZ_OK); + *nUnused = bzf->strm.avail_in; + *unused = bzf->strm.next_in; +} +#endif + + +/*---------------------------------------------------*/ +/*--- Misc convenience stuff ---*/ +/*---------------------------------------------------*/ +#ifndef BZ_NO_COMPRESS +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzBuffToBuffCompress) + ( char* dest, + unsigned int* destLen, + char* source, + unsigned int sourceLen, + int blockSize100k, + int verbosity, + int workFactor ) +{ + bz_stream strm; + int ret; + + if (dest == NULL || destLen == NULL || + source == NULL || + blockSize100k < 1 || blockSize100k > 9 || + verbosity < 0 || verbosity > 4 || + workFactor < 0 || workFactor > 250) + return BZ_PARAM_ERROR; + + if (workFactor == 0) workFactor = 30; + strm.bzalloc = NULL; + strm.bzfree = NULL; + strm.opaque = NULL; + ret = BZ2_bzCompressInit ( &strm, blockSize100k, + verbosity, workFactor ); + if (ret != BZ_OK) return ret; + + strm.next_in = source; + strm.next_out = dest; + strm.avail_in = sourceLen; + strm.avail_out = *destLen; + + ret = BZ2_bzCompress ( &strm, BZ_FINISH ); + if (ret == BZ_FINISH_OK) goto output_overflow; + if (ret != BZ_STREAM_END) goto errhandler; + + /* normal termination */ + *destLen -= strm.avail_out; + BZ2_bzCompressEnd ( &strm ); + return BZ_OK; + + output_overflow: + BZ2_bzCompressEnd ( &strm ); + return BZ_OUTBUFF_FULL; + + errhandler: + BZ2_bzCompressEnd ( &strm ); + return ret; +} +#endif /* BZ_NO_COMPRESS */ + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzBuffToBuffDecompress) + ( char* dest, + unsigned int* destLen, + char* source, + unsigned int sourceLen, + int small, + int verbosity ) +{ + bz_stream strm; + int ret; + + if (destLen == NULL || source == NULL) + return BZ_PARAM_ERROR; + + strm.bzalloc = NULL; + strm.bzfree = NULL; + strm.opaque = NULL; + ret = BZ2_bzDecompressInit ( &strm, verbosity, small ); + if (ret != BZ_OK) return ret; + + strm.next_in = source; + strm.next_out = dest; + strm.avail_in = sourceLen; + strm.avail_out = *destLen; + + ret = BZ2_bzDecompress ( &strm ); + if (ret == BZ_OK) goto output_overflow_or_eof; + if (ret != BZ_STREAM_END) goto errhandler; + + /* normal termination */ + *destLen -= strm.avail_out; + BZ2_bzDecompressEnd ( &strm ); + return BZ_OK; + + output_overflow_or_eof: + if (strm.avail_out > 0) { + BZ2_bzDecompressEnd ( &strm ); + return BZ_UNEXPECTED_EOF; + } else { + BZ2_bzDecompressEnd ( &strm ); + return BZ_OUTBUFF_FULL; + }; + + errhandler: + BZ2_bzDecompressEnd ( &strm ); + return ret; +} + + +/*---------------------------------------------------*/ +/*-- + Code contributed by Yoshioka Tsuneo + (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp), + to support better zlib compatibility. + This code is not _officially_ part of libbzip2 (yet); + I haven't tested it, documented it, or considered the + threading-safeness of it. + If this code breaks, please contact both Yoshioka and me. +--*/ +/*---------------------------------------------------*/ + +/*---------------------------------------------------*/ +/*-- + return version like "0.9.0c". +--*/ +const char * BZ_API(BZ2_bzlibVersion)(void) +{ + return BZ_VERSION; +} + + +#ifndef BZ_NO_STDIO +/*---------------------------------------------------*/ + +#if defined(_WIN32) || defined(OS2) || defined(MSDOS) +# include +# include +# define SET_BINARY_MODE(file) setmode(fileno(file),O_BINARY) +#else +# define SET_BINARY_MODE(file) +#endif +static +BZFILE * bzopen_or_bzdopen + ( const char *path, /* no use when bzdopen */ + int fd, /* no use when bzdopen */ + const char *mode, + int open_mode) /* bzopen: 0, bzdopen:1 */ +{ + int bzerr; + char unused[BZ_MAX_UNUSED]; + int blockSize100k = 9; + int writing = 0; + char mode2[10] = ""; + FILE *fp = NULL; + BZFILE *bzfp = NULL; + int verbosity = 0; + int workFactor = 30; + int smallMode = 0; + int nUnused = 0; + + if (mode == NULL) return NULL; + while (*mode) { + switch (*mode) { + case 'r': + writing = 0; break; + case 'w': + writing = 1; break; + case 's': + smallMode = 1; break; + default: + if (isdigit((int)(*mode))) { + blockSize100k = *mode-BZ_HDR_0; + } + } + mode++; + } + strcat(mode2, writing ? "w" : "r" ); + strcat(mode2,"b"); /* binary mode */ + + if (open_mode==0) { + if (path==NULL || strcmp(path,"")==0) { + fp = (writing ? stdout : stdin); + SET_BINARY_MODE(fp); + } else { + fp = fopen(path,mode2); + } + } else { +#ifdef BZ_STRICT_ANSI + fp = NULL; +#else + fp = fdopen(fd,mode2); +#endif + } + if (fp == NULL) return NULL; + + if (writing) { + /* Guard against total chaos and anarchy -- JRS */ + if (blockSize100k < 1) blockSize100k = 1; + if (blockSize100k > 9) blockSize100k = 9; + bzfp = BZ2_bzWriteOpen(&bzerr,fp,blockSize100k, + verbosity,workFactor); + } else { + bzfp = BZ2_bzReadOpen(&bzerr,fp,verbosity,smallMode, + unused,nUnused); + } + if (bzfp == NULL) { + if (fp != stdin && fp != stdout) fclose(fp); + return NULL; + } + return bzfp; +} + + +/*---------------------------------------------------*/ +/*-- + open file for read or write. + ex) bzopen("file","w9") + case path="" or NULL => use stdin or stdout. +--*/ +BZFILE * BZ_API(BZ2_bzopen) + ( const char *path, + const char *mode ) +{ + return bzopen_or_bzdopen(path,-1,mode,/*bzopen*/0); +} + + +/*---------------------------------------------------*/ +BZFILE * BZ_API(BZ2_bzdopen) + ( int fd, + const char *mode ) +{ + return bzopen_or_bzdopen(NULL,fd,mode,/*bzdopen*/1); +} + + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzread) (BZFILE* b, void* buf, int len ) +{ + int bzerr, nread; + if (((bzFile*)b)->lastErr == BZ_STREAM_END) return 0; + nread = BZ2_bzRead(&bzerr,b,buf,len); + if (bzerr == BZ_OK || bzerr == BZ_STREAM_END) { + return nread; + } else { + return -1; + } +} + + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzwrite) (BZFILE* b, void* buf, int len ) +{ + int bzerr; + + BZ2_bzWrite(&bzerr,b,buf,len); + if(bzerr == BZ_OK){ + return len; + }else{ + return -1; + } +} + + +/*---------------------------------------------------*/ +int BZ_API(BZ2_bzflush) (BZFILE *b) +{ + /* do nothing now... */ + return 0; +} + + +/*---------------------------------------------------*/ +void BZ_API(BZ2_bzclose) (BZFILE* b) +{ + int bzerr; + FILE *fp = ((bzFile *)b)->handle; + + if (b==NULL) {return;} + if(((bzFile*)b)->writing){ + BZ2_bzWriteClose(&bzerr,b,0,NULL,NULL); + if(bzerr != BZ_OK){ + BZ2_bzWriteClose(NULL,b,1,NULL,NULL); + } + }else{ + BZ2_bzReadClose(&bzerr,b); + } + if(fp!=stdin && fp!=stdout){ + fclose(fp); + } +} + + +/*---------------------------------------------------*/ +/*-- + return last error code +--*/ +static char *bzerrorstrings[] = { + "OK" + ,"SEQUENCE_ERROR" + ,"PARAM_ERROR" + ,"MEM_ERROR" + ,"DATA_ERROR" + ,"DATA_ERROR_MAGIC" + ,"IO_ERROR" + ,"UNEXPECTED_EOF" + ,"OUTBUFF_FULL" + ,"CONFIG_ERROR" + ,"???" /* for future */ + ,"???" /* for future */ + ,"???" /* for future */ + ,"???" /* for future */ + ,"???" /* for future */ + ,"???" /* for future */ +}; + + +const char * BZ_API(BZ2_bzerror) (BZFILE *b, int *errnum) +{ + int err = ((bzFile *)b)->lastErr; + + if(err>0) err = 0; + *errnum = err; + return bzerrorstrings[err*-1]; +} +#endif + + +/*-------------------------------------------------------------*/ +/*--- end bzlib.c ---*/ +/*-------------------------------------------------------------*/ + +#endif /* CONFIG_BZIP2 */ diff --git a/lib_generic/bzlib_crctable.c b/lib_generic/bzlib_crctable.c new file mode 100644 index 0000000..63770cd --- /dev/null +++ b/lib_generic/bzlib_crctable.c @@ -0,0 +1,148 @@ +#include +#ifdef CONFIG_BZIP2 + +/*-------------------------------------------------------------*/ +/*--- Table for doing CRCs ---*/ +/*--- crctable.c ---*/ +/*-------------------------------------------------------------*/ + +/*-- + This file is a part of bzip2 and/or libbzip2, a program and + library for lossless, block-sorting data compression. + + Copyright (C) 1996-2002 Julian R Seward. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. The origin of this software must not be misrepresented; you must + not claim that you wrote the original software. If you use this + software in a product, an acknowledgment in the product + documentation would be appreciated but is not required. + + 3. Altered source versions must be plainly marked as such, and must + not be misrepresented as being the original software. + + 4. The name of the author may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Julian Seward, Cambridge, UK. + jseward@acm.org + bzip2/libbzip2 version 1.0 of 21 March 2000 + + This program is based on (at least) the work of: + Mike Burrows + David Wheeler + Peter Fenwick + Alistair Moffat + Radford Neal + Ian H. Witten + Robert Sedgewick + Jon L. Bentley + + For more information on these sources, see the manual. +--*/ + + +#include "bzlib_private.h" + +/*-- + I think this is an implementation of the AUTODIN-II, + Ethernet & FDDI 32-bit CRC standard. Vaguely derived + from code by Rob Warnock, in Section 51 of the + comp.compression FAQ. +--*/ + +UInt32 BZ2_crc32Table[256] = { + + /*-- Ugly, innit? --*/ + + 0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L, + 0x130476dcL, 0x17c56b6bL, 0x1a864db2L, 0x1e475005L, + 0x2608edb8L, 0x22c9f00fL, 0x2f8ad6d6L, 0x2b4bcb61L, + 0x350c9b64L, 0x31cd86d3L, 0x3c8ea00aL, 0x384fbdbdL, + 0x4c11db70L, 0x48d0c6c7L, 0x4593e01eL, 0x4152fda9L, + 0x5f15adacL, 0x5bd4b01bL, 0x569796c2L, 0x52568b75L, + 0x6a1936c8L, 0x6ed82b7fL, 0x639b0da6L, 0x675a1011L, + 0x791d4014L, 0x7ddc5da3L, 0x709f7b7aL, 0x745e66cdL, + 0x9823b6e0L, 0x9ce2ab57L, 0x91a18d8eL, 0x95609039L, + 0x8b27c03cL, 0x8fe6dd8bL, 0x82a5fb52L, 0x8664e6e5L, + 0xbe2b5b58L, 0xbaea46efL, 0xb7a96036L, 0xb3687d81L, + 0xad2f2d84L, 0xa9ee3033L, 0xa4ad16eaL, 0xa06c0b5dL, + 0xd4326d90L, 0xd0f37027L, 0xddb056feL, 0xd9714b49L, + 0xc7361b4cL, 0xc3f706fbL, 0xceb42022L, 0xca753d95L, + 0xf23a8028L, 0xf6fb9d9fL, 0xfbb8bb46L, 0xff79a6f1L, + 0xe13ef6f4L, 0xe5ffeb43L, 0xe8bccd9aL, 0xec7dd02dL, + 0x34867077L, 0x30476dc0L, 0x3d044b19L, 0x39c556aeL, + 0x278206abL, 0x23431b1cL, 0x2e003dc5L, 0x2ac12072L, + 0x128e9dcfL, 0x164f8078L, 0x1b0ca6a1L, 0x1fcdbb16L, + 0x018aeb13L, 0x054bf6a4L, 0x0808d07dL, 0x0cc9cdcaL, + 0x7897ab07L, 0x7c56b6b0L, 0x71159069L, 0x75d48ddeL, + 0x6b93dddbL, 0x6f52c06cL, 0x6211e6b5L, 0x66d0fb02L, + 0x5e9f46bfL, 0x5a5e5b08L, 0x571d7dd1L, 0x53dc6066L, + 0x4d9b3063L, 0x495a2dd4L, 0x44190b0dL, 0x40d816baL, + 0xaca5c697L, 0xa864db20L, 0xa527fdf9L, 0xa1e6e04eL, + 0xbfa1b04bL, 0xbb60adfcL, 0xb6238b25L, 0xb2e29692L, + 0x8aad2b2fL, 0x8e6c3698L, 0x832f1041L, 0x87ee0df6L, + 0x99a95df3L, 0x9d684044L, 0x902b669dL, 0x94ea7b2aL, + 0xe0b41de7L, 0xe4750050L, 0xe9362689L, 0xedf73b3eL, + 0xf3b06b3bL, 0xf771768cL, 0xfa325055L, 0xfef34de2L, + 0xc6bcf05fL, 0xc27dede8L, 0xcf3ecb31L, 0xcbffd686L, + 0xd5b88683L, 0xd1799b34L, 0xdc3abdedL, 0xd8fba05aL, + 0x690ce0eeL, 0x6dcdfd59L, 0x608edb80L, 0x644fc637L, + 0x7a089632L, 0x7ec98b85L, 0x738aad5cL, 0x774bb0ebL, + 0x4f040d56L, 0x4bc510e1L, 0x46863638L, 0x42472b8fL, + 0x5c007b8aL, 0x58c1663dL, 0x558240e4L, 0x51435d53L, + 0x251d3b9eL, 0x21dc2629L, 0x2c9f00f0L, 0x285e1d47L, + 0x36194d42L, 0x32d850f5L, 0x3f9b762cL, 0x3b5a6b9bL, + 0x0315d626L, 0x07d4cb91L, 0x0a97ed48L, 0x0e56f0ffL, + 0x1011a0faL, 0x14d0bd4dL, 0x19939b94L, 0x1d528623L, + 0xf12f560eL, 0xf5ee4bb9L, 0xf8ad6d60L, 0xfc6c70d7L, + 0xe22b20d2L, 0xe6ea3d65L, 0xeba91bbcL, 0xef68060bL, + 0xd727bbb6L, 0xd3e6a601L, 0xdea580d8L, 0xda649d6fL, + 0xc423cd6aL, 0xc0e2d0ddL, 0xcda1f604L, 0xc960ebb3L, + 0xbd3e8d7eL, 0xb9ff90c9L, 0xb4bcb610L, 0xb07daba7L, + 0xae3afba2L, 0xaafbe615L, 0xa7b8c0ccL, 0xa379dd7bL, + 0x9b3660c6L, 0x9ff77d71L, 0x92b45ba8L, 0x9675461fL, + 0x8832161aL, 0x8cf30badL, 0x81b02d74L, 0x857130c3L, + 0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L, + 0x4e8ee645L, 0x4a4ffbf2L, 0x470cdd2bL, 0x43cdc09cL, + 0x7b827d21L, 0x7f436096L, 0x7200464fL, 0x76c15bf8L, + 0x68860bfdL, 0x6c47164aL, 0x61043093L, 0x65c52d24L, + 0x119b4be9L, 0x155a565eL, 0x18197087L, 0x1cd86d30L, + 0x029f3d35L, 0x065e2082L, 0x0b1d065bL, 0x0fdc1becL, + 0x3793a651L, 0x3352bbe6L, 0x3e119d3fL, 0x3ad08088L, + 0x2497d08dL, 0x2056cd3aL, 0x2d15ebe3L, 0x29d4f654L, + 0xc5a92679L, 0xc1683bceL, 0xcc2b1d17L, 0xc8ea00a0L, + 0xd6ad50a5L, 0xd26c4d12L, 0xdf2f6bcbL, 0xdbee767cL, + 0xe3a1cbc1L, 0xe760d676L, 0xea23f0afL, 0xeee2ed18L, + 0xf0a5bd1dL, 0xf464a0aaL, 0xf9278673L, 0xfde69bc4L, + 0x89b8fd09L, 0x8d79e0beL, 0x803ac667L, 0x84fbdbd0L, + 0x9abc8bd5L, 0x9e7d9662L, 0x933eb0bbL, 0x97ffad0cL, + 0xafb010b1L, 0xab710d06L, 0xa6322bdfL, 0xa2f33668L, + 0xbcb4666dL, 0xb8757bdaL, 0xb5365d03L, 0xb1f740b4L +}; + + +/*-------------------------------------------------------------*/ +/*--- end crctable.c ---*/ +/*-------------------------------------------------------------*/ + +#endif /* CONFIG_BZIP2 */ diff --git a/lib_generic/bzlib_decompress.c b/lib_generic/bzlib_decompress.c new file mode 100644 index 0000000..a575052 --- /dev/null +++ b/lib_generic/bzlib_decompress.c @@ -0,0 +1,677 @@ +#include +#include +#include +#ifdef CONFIG_BZIP2 + +/*-------------------------------------------------------------*/ +/*--- Decompression machinery ---*/ +/*--- decompress.c ---*/ +/*-------------------------------------------------------------*/ + +/*-- + This file is a part of bzip2 and/or libbzip2, a program and + library for lossless, block-sorting data compression. + + Copyright (C) 1996-2002 Julian R Seward. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. The origin of this software must not be misrepresented; you must + not claim that you wrote the original software. If you use this + software in a product, an acknowledgment in the product + documentation would be appreciated but is not required. + + 3. Altered source versions must be plainly marked as such, and must + not be misrepresented as being the original software. + + 4. The name of the author may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Julian Seward, Cambridge, UK. + jseward@acm.org + bzip2/libbzip2 version 1.0 of 21 March 2000 + + This program is based on (at least) the work of: + Mike Burrows + David Wheeler + Peter Fenwick + Alistair Moffat + Radford Neal + Ian H. Witten + Robert Sedgewick + Jon L. Bentley + + For more information on these sources, see the manual. +--*/ + + +#include "bzlib_private.h" + + +/*---------------------------------------------------*/ +static +void makeMaps_d ( DState* s ) +{ + Int32 i; + s->nInUse = 0; + for (i = 0; i < 256; i++) + if (s->inUse[i]) { + s->seqToUnseq[s->nInUse] = i; + s->nInUse++; + } +} + + +/*---------------------------------------------------*/ +#define RETURN(rrr) \ + { retVal = rrr; goto save_state_and_return; }; + +#define GET_BITS(lll,vvv,nnn) \ + case lll: s->state = lll; \ + while (True) { \ + if (s->bsLive >= nnn) { \ + UInt32 v; \ + v = (s->bsBuff >> \ + (s->bsLive-nnn)) & ((1 << nnn)-1); \ + s->bsLive -= nnn; \ + vvv = v; \ + break; \ + } \ + if (s->strm->avail_in == 0) RETURN(BZ_OK); \ + s->bsBuff \ + = (s->bsBuff << 8) | \ + ((UInt32) \ + (*((UChar*)(s->strm->next_in)))); \ + s->bsLive += 8; \ + s->strm->next_in++; \ + s->strm->avail_in--; \ + s->strm->total_in_lo32++; \ + if (s->strm->total_in_lo32 == 0) \ + s->strm->total_in_hi32++; \ + } + +#define GET_UCHAR(lll,uuu) \ + GET_BITS(lll,uuu,8) + +#define GET_BIT(lll,uuu) \ + GET_BITS(lll,uuu,1) + +/*---------------------------------------------------*/ +#define GET_MTF_VAL(label1,label2,lval) \ +{ \ + if (groupPos == 0) { \ + groupNo++; \ + if (groupNo >= nSelectors) \ + RETURN(BZ_DATA_ERROR); \ + groupPos = BZ_G_SIZE; \ + gSel = s->selector[groupNo]; \ + gMinlen = s->minLens[gSel]; \ + gLimit = &(s->limit[gSel][0]); \ + gPerm = &(s->perm[gSel][0]); \ + gBase = &(s->base[gSel][0]); \ + } \ + groupPos--; \ + zn = gMinlen; \ + GET_BITS(label1, zvec, zn); \ + while (1) { \ + if (zn > 20 /* the longest code */) \ + RETURN(BZ_DATA_ERROR); \ + if (zvec <= gLimit[zn]) break; \ + zn++; \ + GET_BIT(label2, zj); \ + zvec = (zvec << 1) | zj; \ + }; \ + if (zvec - gBase[zn] < 0 \ + || zvec - gBase[zn] >= BZ_MAX_ALPHA_SIZE) \ + RETURN(BZ_DATA_ERROR); \ + lval = gPerm[zvec - gBase[zn]]; \ +} + + +/*---------------------------------------------------*/ +Int32 BZ2_decompress ( DState* s ) +{ + UChar uc; + Int32 retVal; + Int32 minLen, maxLen; + bz_stream* strm = s->strm; + + /* stuff that needs to be saved/restored */ + Int32 i; + Int32 j; + Int32 t; + Int32 alphaSize; + Int32 nGroups; + Int32 nSelectors; + Int32 EOB; + Int32 groupNo; + Int32 groupPos; + Int32 nextSym; + Int32 nblockMAX; + Int32 nblock; + Int32 es; + Int32 N; + Int32 curr; + Int32 zt; + Int32 zn; + Int32 zvec; + Int32 zj; + Int32 gSel; + Int32 gMinlen; + Int32* gLimit; + Int32* gBase; + Int32* gPerm; + + if (s->state == BZ_X_MAGIC_1) { + /*initialise the save area*/ + s->save_i = 0; + s->save_j = 0; + s->save_t = 0; + s->save_alphaSize = 0; + s->save_nGroups = 0; + s->save_nSelectors = 0; + s->save_EOB = 0; + s->save_groupNo = 0; + s->save_groupPos = 0; + s->save_nextSym = 0; + s->save_nblockMAX = 0; + s->save_nblock = 0; + s->save_es = 0; + s->save_N = 0; + s->save_curr = 0; + s->save_zt = 0; + s->save_zn = 0; + s->save_zvec = 0; + s->save_zj = 0; + s->save_gSel = 0; + s->save_gMinlen = 0; + s->save_gLimit = NULL; + s->save_gBase = NULL; + s->save_gPerm = NULL; + } + + /*restore from the save area*/ + i = s->save_i; + j = s->save_j; + t = s->save_t; + alphaSize = s->save_alphaSize; + nGroups = s->save_nGroups; + nSelectors = s->save_nSelectors; + EOB = s->save_EOB; + groupNo = s->save_groupNo; + groupPos = s->save_groupPos; + nextSym = s->save_nextSym; + nblockMAX = s->save_nblockMAX; + nblock = s->save_nblock; + es = s->save_es; + N = s->save_N; + curr = s->save_curr; + zt = s->save_zt; + zn = s->save_zn; + zvec = s->save_zvec; + zj = s->save_zj; + gSel = s->save_gSel; + gMinlen = s->save_gMinlen; + gLimit = s->save_gLimit; + gBase = s->save_gBase; + gPerm = s->save_gPerm; + + retVal = BZ_OK; + + switch (s->state) { + + GET_UCHAR(BZ_X_MAGIC_1, uc); + if (uc != BZ_HDR_B) RETURN(BZ_DATA_ERROR_MAGIC); + + GET_UCHAR(BZ_X_MAGIC_2, uc); + if (uc != BZ_HDR_Z) RETURN(BZ_DATA_ERROR_MAGIC); + + GET_UCHAR(BZ_X_MAGIC_3, uc) + if (uc != BZ_HDR_h) RETURN(BZ_DATA_ERROR_MAGIC); + + GET_BITS(BZ_X_MAGIC_4, s->blockSize100k, 8) + if (s->blockSize100k < (BZ_HDR_0 + 1) || + s->blockSize100k > (BZ_HDR_0 + 9)) RETURN(BZ_DATA_ERROR_MAGIC); + s->blockSize100k -= BZ_HDR_0; + + if (s->smallDecompress) { + s->ll16 = BZALLOC( s->blockSize100k * 100000 * sizeof(UInt16) ); + s->ll4 = BZALLOC( + ((1 + s->blockSize100k * 100000) >> 1) * sizeof(UChar) + ); + if (s->ll16 == NULL || s->ll4 == NULL) RETURN(BZ_MEM_ERROR); + } else { + s->tt = BZALLOC( s->blockSize100k * 100000 * sizeof(Int32) ); + if (s->tt == NULL) RETURN(BZ_MEM_ERROR); + } + + GET_UCHAR(BZ_X_BLKHDR_1, uc); + + if (uc == 0x17) goto endhdr_2; + if (uc != 0x31) RETURN(BZ_DATA_ERROR); + GET_UCHAR(BZ_X_BLKHDR_2, uc); + if (uc != 0x41) RETURN(BZ_DATA_ERROR); + GET_UCHAR(BZ_X_BLKHDR_3, uc); + if (uc != 0x59) RETURN(BZ_DATA_ERROR); + GET_UCHAR(BZ_X_BLKHDR_4, uc); + if (uc != 0x26) RETURN(BZ_DATA_ERROR); + GET_UCHAR(BZ_X_BLKHDR_5, uc); + if (uc != 0x53) RETURN(BZ_DATA_ERROR); + GET_UCHAR(BZ_X_BLKHDR_6, uc); + if (uc != 0x59) RETURN(BZ_DATA_ERROR); + + s->currBlockNo++; + if (s->verbosity >= 2) + VPrintf1 ( "\n [%d: huff+mtf ", s->currBlockNo ); + + s->storedBlockCRC = 0; + GET_UCHAR(BZ_X_BCRC_1, uc); + s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc); + GET_UCHAR(BZ_X_BCRC_2, uc); + s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc); + GET_UCHAR(BZ_X_BCRC_3, uc); + s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc); + GET_UCHAR(BZ_X_BCRC_4, uc); + s->storedBlockCRC = (s->storedBlockCRC << 8) | ((UInt32)uc); + + GET_BITS(BZ_X_RANDBIT, s->blockRandomised, 1); + + s->origPtr = 0; + GET_UCHAR(BZ_X_ORIGPTR_1, uc); + s->origPtr = (s->origPtr << 8) | ((Int32)uc); + GET_UCHAR(BZ_X_ORIGPTR_2, uc); + s->origPtr = (s->origPtr << 8) | ((Int32)uc); + GET_UCHAR(BZ_X_ORIGPTR_3, uc); + s->origPtr = (s->origPtr << 8) | ((Int32)uc); + + if (s->origPtr < 0) + RETURN(BZ_DATA_ERROR); + if (s->origPtr > 10 + 100000*s->blockSize100k) + RETURN(BZ_DATA_ERROR); + + /*--- Receive the mapping table ---*/ + for (i = 0; i < 16; i++) { + GET_BIT(BZ_X_MAPPING_1, uc); + if (uc == 1) + s->inUse16[i] = True; else + s->inUse16[i] = False; + } + + for (i = 0; i < 256; i++) s->inUse[i] = False; + + for (i = 0; i < 16; i++) + if (s->inUse16[i]) + for (j = 0; j < 16; j++) { + GET_BIT(BZ_X_MAPPING_2, uc); + if (uc == 1) s->inUse[i * 16 + j] = True; + } + makeMaps_d ( s ); + if (s->nInUse == 0) RETURN(BZ_DATA_ERROR); + alphaSize = s->nInUse+2; + + /*--- Now the selectors ---*/ + GET_BITS(BZ_X_SELECTOR_1, nGroups, 3); + if (nGroups < 2 || nGroups > 6) RETURN(BZ_DATA_ERROR); + GET_BITS(BZ_X_SELECTOR_2, nSelectors, 15); + if (nSelectors < 1) RETURN(BZ_DATA_ERROR); + for (i = 0; i < nSelectors; i++) { + j = 0; + while (True) { + GET_BIT(BZ_X_SELECTOR_3, uc); + if (uc == 0) break; + j++; + if (j >= nGroups) RETURN(BZ_DATA_ERROR); + } + s->selectorMtf[i] = j; + } + + /*--- Undo the MTF values for the selectors. ---*/ + { + UChar pos[BZ_N_GROUPS], tmp, v; + for (v = 0; v < nGroups; v++) pos[v] = v; + + for (i = 0; i < nSelectors; i++) { + v = s->selectorMtf[i]; + tmp = pos[v]; + while (v > 0) { pos[v] = pos[v-1]; v--; } + pos[0] = tmp; + s->selector[i] = tmp; + } + } + + /*--- Now the coding tables ---*/ + for (t = 0; t < nGroups; t++) { + GET_BITS(BZ_X_CODING_1, curr, 5); + for (i = 0; i < alphaSize; i++) { + while (True) { + if (curr < 1 || curr > 20) RETURN(BZ_DATA_ERROR); + GET_BIT(BZ_X_CODING_2, uc); + if (uc == 0) break; + GET_BIT(BZ_X_CODING_3, uc); + if (uc == 0) curr++; else curr--; + } + s->len[t][i] = curr; + } + } + + /*--- Create the Huffman decoding tables ---*/ + for (t = 0; t < nGroups; t++) { + minLen = 32; + maxLen = 0; + for (i = 0; i < alphaSize; i++) { + if (s->len[t][i] > maxLen) maxLen = s->len[t][i]; + if (s->len[t][i] < minLen) minLen = s->len[t][i]; + } + BZ2_hbCreateDecodeTables ( + &(s->limit[t][0]), + &(s->base[t][0]), + &(s->perm[t][0]), + &(s->len[t][0]), + minLen, maxLen, alphaSize + ); + s->minLens[t] = minLen; + } + + /*--- Now the MTF values ---*/ + + EOB = s->nInUse+1; + nblockMAX = 100000 * s->blockSize100k; + groupNo = -1; + groupPos = 0; + + for (i = 0; i <= 255; i++) s->unzftab[i] = 0; + + /*-- MTF init --*/ + { + Int32 ii, jj, kk; + kk = MTFA_SIZE-1; + for (ii = 256 / MTFL_SIZE - 1; ii >= 0; ii--) { + for (jj = MTFL_SIZE-1; jj >= 0; jj--) { + s->mtfa[kk] = (UChar)(ii * MTFL_SIZE + jj); + kk--; + } + s->mtfbase[ii] = kk + 1; + } + } + /*-- end MTF init --*/ + + nblock = 0; + GET_MTF_VAL(BZ_X_MTF_1, BZ_X_MTF_2, nextSym); + + while (True) { + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif + if (nextSym == EOB) break; + + if (nextSym == BZ_RUNA || nextSym == BZ_RUNB) { + + es = -1; + N = 1; + do { + if (nextSym == BZ_RUNA) es = es + (0+1) * N; else + if (nextSym == BZ_RUNB) es = es + (1+1) * N; + N = N * 2; + GET_MTF_VAL(BZ_X_MTF_3, BZ_X_MTF_4, nextSym); + } + while (nextSym == BZ_RUNA || nextSym == BZ_RUNB); + + es++; + uc = s->seqToUnseq[ s->mtfa[s->mtfbase[0]] ]; + s->unzftab[uc] += es; + + if (s->smallDecompress) + while (es > 0) { + if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR); + s->ll16[nblock] = (UInt16)uc; + nblock++; + es--; + } + else + while (es > 0) { + if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR); + s->tt[nblock] = (UInt32)uc; + nblock++; + es--; + }; + + continue; + + } else { + + if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR); + + /*-- uc = MTF ( nextSym-1 ) --*/ + { + Int32 ii, jj, kk, pp, lno, off; + UInt32 nn; + nn = (UInt32)(nextSym - 1); + + if (nn < MTFL_SIZE) { + /* avoid general-case expense */ + pp = s->mtfbase[0]; + uc = s->mtfa[pp+nn]; + while (nn > 3) { + Int32 z = pp+nn; + s->mtfa[(z) ] = s->mtfa[(z)-1]; + s->mtfa[(z)-1] = s->mtfa[(z)-2]; + s->mtfa[(z)-2] = s->mtfa[(z)-3]; + s->mtfa[(z)-3] = s->mtfa[(z)-4]; + nn -= 4; + } + while (nn > 0) { + s->mtfa[(pp+nn)] = s->mtfa[(pp+nn)-1]; nn--; + }; + s->mtfa[pp] = uc; + } else { + /* general case */ + lno = nn / MTFL_SIZE; + off = nn % MTFL_SIZE; + pp = s->mtfbase[lno] + off; + uc = s->mtfa[pp]; + while (pp > s->mtfbase[lno]) { + s->mtfa[pp] = s->mtfa[pp-1]; pp--; + }; + s->mtfbase[lno]++; + while (lno > 0) { + s->mtfbase[lno]--; + s->mtfa[s->mtfbase[lno]] + = s->mtfa[s->mtfbase[lno-1] + MTFL_SIZE - 1]; + lno--; + } + s->mtfbase[0]--; + s->mtfa[s->mtfbase[0]] = uc; + if (s->mtfbase[0] == 0) { + kk = MTFA_SIZE-1; + for (ii = 256 / MTFL_SIZE-1; ii >= 0; ii--) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif + for (jj = MTFL_SIZE-1; jj >= 0; jj--) { + s->mtfa[kk] = s->mtfa[s->mtfbase[ii] + jj]; + kk--; + } + s->mtfbase[ii] = kk + 1; + } + } + } + } + /*-- end uc = MTF ( nextSym-1 ) --*/ + + s->unzftab[s->seqToUnseq[uc]]++; + if (s->smallDecompress) + s->ll16[nblock] = (UInt16)(s->seqToUnseq[uc]); else + s->tt[nblock] = (UInt32)(s->seqToUnseq[uc]); + nblock++; + + GET_MTF_VAL(BZ_X_MTF_5, BZ_X_MTF_6, nextSym); + continue; + } + } + + /* Now we know what nblock is, we can do a better sanity + check on s->origPtr. + */ + if (s->origPtr < 0 || s->origPtr >= nblock) + RETURN(BZ_DATA_ERROR); + + s->state_out_len = 0; + s->state_out_ch = 0; + BZ_INITIALISE_CRC ( s->calculatedBlockCRC ); + s->state = BZ_X_OUTPUT; + if (s->verbosity >= 2) VPrintf0 ( "rt+rld" ); + + /*-- Set up cftab to facilitate generation of T^(-1) --*/ + s->cftab[0] = 0; + for (i = 1; i <= 256; i++) s->cftab[i] = s->unzftab[i-1]; + for (i = 1; i <= 256; i++) s->cftab[i] += s->cftab[i-1]; + + if (s->smallDecompress) { + + /*-- Make a copy of cftab, used in generation of T --*/ + for (i = 0; i <= 256; i++) s->cftabCopy[i] = s->cftab[i]; + + /*-- compute the T vector --*/ + for (i = 0; i < nblock; i++) { + uc = (UChar)(s->ll16[i]); + SET_LL(i, s->cftabCopy[uc]); + s->cftabCopy[uc]++; + } + + /*-- Compute T^(-1) by pointer reversal on T --*/ + i = s->origPtr; + j = GET_LL(i); + do { + Int32 tmp = GET_LL(j); + SET_LL(j, i); + i = j; + j = tmp; + } + while (i != s->origPtr); + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif + s->tPos = s->origPtr; + s->nblock_used = 0; + if (s->blockRandomised) { + BZ_RAND_INIT_MASK; + BZ_GET_SMALL(s->k0); s->nblock_used++; + BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK; + } else { + BZ_GET_SMALL(s->k0); s->nblock_used++; + } + + } else { + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif + /*-- compute the T^(-1) vector --*/ + for (i = 0; i < nblock; i++) { + uc = (UChar)(s->tt[i] & 0xff); + s->tt[s->cftab[uc]] |= (i << 8); + s->cftab[uc]++; + } + + s->tPos = s->tt[s->origPtr] >> 8; + s->nblock_used = 0; + if (s->blockRandomised) { + BZ_RAND_INIT_MASK; + BZ_GET_FAST(s->k0); s->nblock_used++; + BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK; + } else { + BZ_GET_FAST(s->k0); s->nblock_used++; + } + + } + + RETURN(BZ_OK); + + + endhdr_2: + + GET_UCHAR(BZ_X_ENDHDR_2, uc); + if (uc != 0x72) RETURN(BZ_DATA_ERROR); + GET_UCHAR(BZ_X_ENDHDR_3, uc); + if (uc != 0x45) RETURN(BZ_DATA_ERROR); + GET_UCHAR(BZ_X_ENDHDR_4, uc); + if (uc != 0x38) RETURN(BZ_DATA_ERROR); + GET_UCHAR(BZ_X_ENDHDR_5, uc); + if (uc != 0x50) RETURN(BZ_DATA_ERROR); + GET_UCHAR(BZ_X_ENDHDR_6, uc); + if (uc != 0x90) RETURN(BZ_DATA_ERROR); + + s->storedCombinedCRC = 0; + GET_UCHAR(BZ_X_CCRC_1, uc); + s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc); + GET_UCHAR(BZ_X_CCRC_2, uc); + s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc); + GET_UCHAR(BZ_X_CCRC_3, uc); + s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc); + GET_UCHAR(BZ_X_CCRC_4, uc); + s->storedCombinedCRC = (s->storedCombinedCRC << 8) | ((UInt32)uc); + + s->state = BZ_X_IDLE; + RETURN(BZ_STREAM_END); + + default: AssertH ( False, 4001 ); + } + + AssertH ( False, 4002 ); + + save_state_and_return: + + s->save_i = i; + s->save_j = j; + s->save_t = t; + s->save_alphaSize = alphaSize; + s->save_nGroups = nGroups; + s->save_nSelectors = nSelectors; + s->save_EOB = EOB; + s->save_groupNo = groupNo; + s->save_groupPos = groupPos; + s->save_nextSym = nextSym; + s->save_nblockMAX = nblockMAX; + s->save_nblock = nblock; + s->save_es = es; + s->save_N = N; + s->save_curr = curr; + s->save_zt = zt; + s->save_zn = zn; + s->save_zvec = zvec; + s->save_zj = zj; + s->save_gSel = gSel; + s->save_gMinlen = gMinlen; + s->save_gLimit = gLimit; + s->save_gBase = gBase; + s->save_gPerm = gPerm; + + return retVal; +} + + +/*-------------------------------------------------------------*/ +/*--- end decompress.c ---*/ +/*-------------------------------------------------------------*/ + +#endif /* CONFIG_BZIP2 */ diff --git a/lib_generic/bzlib_huffman.c b/lib_generic/bzlib_huffman.c new file mode 100644 index 0000000..effae98 --- /dev/null +++ b/lib_generic/bzlib_huffman.c @@ -0,0 +1,232 @@ +#include +#ifdef CONFIG_BZIP2 + +/*-------------------------------------------------------------*/ +/*--- Huffman coding low-level stuff ---*/ +/*--- huffman.c ---*/ +/*-------------------------------------------------------------*/ + +/*-- + This file is a part of bzip2 and/or libbzip2, a program and + library for lossless, block-sorting data compression. + + Copyright (C) 1996-2002 Julian R Seward. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. The origin of this software must not be misrepresented; you must + not claim that you wrote the original software. If you use this + software in a product, an acknowledgment in the product + documentation would be appreciated but is not required. + + 3. Altered source versions must be plainly marked as such, and must + not be misrepresented as being the original software. + + 4. The name of the author may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Julian Seward, Cambridge, UK. + jseward@acm.org + bzip2/libbzip2 version 1.0 of 21 March 2000 + + This program is based on (at least) the work of: + Mike Burrows + David Wheeler + Peter Fenwick + Alistair Moffat + Radford Neal + Ian H. Witten + Robert Sedgewick + Jon L. Bentley + + For more information on these sources, see the manual. +--*/ + + +#include "bzlib_private.h" + +/*---------------------------------------------------*/ +#define WEIGHTOF(zz0) ((zz0) & 0xffffff00) +#define DEPTHOF(zz1) ((zz1) & 0x000000ff) +#define MYMAX(zz2,zz3) ((zz2) > (zz3) ? (zz2) : (zz3)) + +#define ADDWEIGHTS(zw1,zw2) \ + (WEIGHTOF(zw1)+WEIGHTOF(zw2)) | \ + (1 + MYMAX(DEPTHOF(zw1),DEPTHOF(zw2))) + +#define UPHEAP(z) \ +{ \ + Int32 zz, tmp; \ + zz = z; tmp = heap[zz]; \ + while (weight[tmp] < weight[heap[zz >> 1]]) { \ + heap[zz] = heap[zz >> 1]; \ + zz >>= 1; \ + } \ + heap[zz] = tmp; \ +} + +#define DOWNHEAP(z) \ +{ \ + Int32 zz, yy, tmp; \ + zz = z; tmp = heap[zz]; \ + while (True) { \ + yy = zz << 1; \ + if (yy > nHeap) break; \ + if (yy < nHeap && \ + weight[heap[yy+1]] < weight[heap[yy]]) \ + yy++; \ + if (weight[tmp] < weight[heap[yy]]) break; \ + heap[zz] = heap[yy]; \ + zz = yy; \ + } \ + heap[zz] = tmp; \ +} + + +/*---------------------------------------------------*/ +void BZ2_hbMakeCodeLengths ( UChar *len, + Int32 *freq, + Int32 alphaSize, + Int32 maxLen ) +{ + /*-- + Nodes and heap entries run from 1. Entry 0 + for both the heap and nodes is a sentinel. + --*/ + Int32 nNodes, nHeap, n1, n2, i, j, k; + Bool tooLong; + + Int32 heap [ BZ_MAX_ALPHA_SIZE + 2 ]; + Int32 weight [ BZ_MAX_ALPHA_SIZE * 2 ]; + Int32 parent [ BZ_MAX_ALPHA_SIZE * 2 ]; + + for (i = 0; i < alphaSize; i++) + weight[i+1] = (freq[i] == 0 ? 1 : freq[i]) << 8; + + while (True) { + + nNodes = alphaSize; + nHeap = 0; + + heap[0] = 0; + weight[0] = 0; + parent[0] = -2; + + for (i = 1; i <= alphaSize; i++) { + parent[i] = -1; + nHeap++; + heap[nHeap] = i; + UPHEAP(nHeap); + } + + AssertH( nHeap < (BZ_MAX_ALPHA_SIZE+2), 2001 ); + + while (nHeap > 1) { + n1 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1); + n2 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1); + nNodes++; + parent[n1] = parent[n2] = nNodes; + weight[nNodes] = ADDWEIGHTS(weight[n1], weight[n2]); + parent[nNodes] = -1; + nHeap++; + heap[nHeap] = nNodes; + UPHEAP(nHeap); + } + + AssertH( nNodes < (BZ_MAX_ALPHA_SIZE * 2), 2002 ); + + tooLong = False; + for (i = 1; i <= alphaSize; i++) { + j = 0; + k = i; + while (parent[k] >= 0) { k = parent[k]; j++; } + len[i-1] = j; + if (j > maxLen) tooLong = True; + } + + if (! tooLong) break; + + for (i = 1; i < alphaSize; i++) { + j = weight[i] >> 8; + j = 1 + (j / 2); + weight[i] = j << 8; + } + } +} + + +/*---------------------------------------------------*/ +void BZ2_hbAssignCodes ( Int32 *code, + UChar *length, + Int32 minLen, + Int32 maxLen, + Int32 alphaSize ) +{ + Int32 n, vec, i; + + vec = 0; + for (n = minLen; n <= maxLen; n++) { + for (i = 0; i < alphaSize; i++) + if (length[i] == n) { code[i] = vec; vec++; }; + vec <<= 1; + } +} + + +/*---------------------------------------------------*/ +void BZ2_hbCreateDecodeTables ( Int32 *limit, + Int32 *base, + Int32 *perm, + UChar *length, + Int32 minLen, + Int32 maxLen, + Int32 alphaSize ) +{ + Int32 pp, i, j, vec; + + pp = 0; + for (i = minLen; i <= maxLen; i++) + for (j = 0; j < alphaSize; j++) + if (length[j] == i) { perm[pp] = j; pp++; }; + + for (i = 0; i < BZ_MAX_CODE_LEN; i++) base[i] = 0; + for (i = 0; i < alphaSize; i++) base[length[i]+1]++; + + for (i = 1; i < BZ_MAX_CODE_LEN; i++) base[i] += base[i-1]; + + for (i = 0; i < BZ_MAX_CODE_LEN; i++) limit[i] = 0; + vec = 0; + + for (i = minLen; i <= maxLen; i++) { + vec += (base[i+1] - base[i]); + limit[i] = vec-1; + vec <<= 1; + } + for (i = minLen + 1; i <= maxLen; i++) + base[i] = ((limit[i-1] + 1) << 1) - base[i]; +} + + +/*-------------------------------------------------------------*/ +/*--- end huffman.c ---*/ +/*-------------------------------------------------------------*/ + +#endif /* CONFIG_BZIP2 */ diff --git a/lib_generic/bzlib_private.h b/lib_generic/bzlib_private.h new file mode 100644 index 0000000..87d8f94 --- /dev/null +++ b/lib_generic/bzlib_private.h @@ -0,0 +1,530 @@ +/* + * This file is a modified version of bzlib_private.h from the bzip2-1.0.2 + * distribution which can be found at http://sources.redhat.com/bzip2/ + */ + +/*-------------------------------------------------------------*/ +/*--- Private header file for the library. ---*/ +/*--- bzlib_private.h ---*/ +/*-------------------------------------------------------------*/ + +/*-- + This file is a part of bzip2 and/or libbzip2, a program and + library for lossless, block-sorting data compression. + + Copyright (C) 1996-2002 Julian R Seward. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. The origin of this software must not be misrepresented; you must + not claim that you wrote the original software. If you use this + software in a product, an acknowledgment in the product + documentation would be appreciated but is not required. + + 3. Altered source versions must be plainly marked as such, and must + not be misrepresented as being the original software. + + 4. The name of the author may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Julian Seward, Cambridge, UK. + jseward@acm.org + bzip2/libbzip2 version 1.0 of 21 March 2000 + + This program is based on (at least) the work of: + Mike Burrows + David Wheeler + Peter Fenwick + Alistair Moffat + Radford Neal + Ian H. Witten + Robert Sedgewick + Jon L. Bentley + + For more information on these sources, see the manual. +--*/ + + +#ifndef _BZLIB_PRIVATE_H +#define _BZLIB_PRIVATE_H + +#include + +#include "bzlib.h" + +#ifndef BZ_NO_STDIO +#include +#include +#include +#endif + + +/*-- General stuff. --*/ + +#define BZ_VERSION "1.0.2, 30-Dec-2001" + +typedef char Char; +typedef unsigned char Bool; +typedef unsigned char UChar; +typedef int Int32; +typedef unsigned int UInt32; +typedef short Int16; +typedef unsigned short UInt16; + +#define True ((Bool)1) +#define False ((Bool)0) + +#ifndef __GNUC__ +#define __inline__ /* */ +#endif + +#ifndef BZ_NO_STDIO +extern void BZ2_bz__AssertH__fail ( int errcode ); +#define AssertH(cond,errcode) \ + { if (!(cond)) BZ2_bz__AssertH__fail ( errcode ); } +#if BZ_DEBUG +#define AssertD(cond,msg) \ + { if (!(cond)) { \ + fprintf ( stderr, \ + "\n\nlibbzip2(debug build): internal error\n\t%s\n", msg );\ + exit(1); \ + }} +#else +#define AssertD(cond,msg) /* */ +#endif +#define VPrintf0(zf) \ + fprintf(stderr,zf) +#define VPrintf1(zf,za1) \ + fprintf(stderr,zf,za1) +#define VPrintf2(zf,za1,za2) \ + fprintf(stderr,zf,za1,za2) +#define VPrintf3(zf,za1,za2,za3) \ + fprintf(stderr,zf,za1,za2,za3) +#define VPrintf4(zf,za1,za2,za3,za4) \ + fprintf(stderr,zf,za1,za2,za3,za4) +#define VPrintf5(zf,za1,za2,za3,za4,za5) \ + fprintf(stderr,zf,za1,za2,za3,za4,za5) +#else +extern void bz_internal_error ( int errcode ); +#define AssertH(cond,errcode) \ + { if (!(cond)) bz_internal_error ( errcode ); } +#define AssertD(cond,msg) /* */ +#define VPrintf0(zf) /* */ +#define VPrintf1(zf,za1) /* */ +#define VPrintf2(zf,za1,za2) /* */ +#define VPrintf3(zf,za1,za2,za3) /* */ +#define VPrintf4(zf,za1,za2,za3,za4) /* */ +#define VPrintf5(zf,za1,za2,za3,za4,za5) /* */ +#endif + + +#define BZALLOC(nnn) (strm->bzalloc)(strm->opaque,(nnn),1) +#define BZFREE(ppp) (strm->bzfree)(strm->opaque,(ppp)) + + +/*-- Header bytes. --*/ + +#define BZ_HDR_B 0x42 /* 'B' */ +#define BZ_HDR_Z 0x5a /* 'Z' */ +#define BZ_HDR_h 0x68 /* 'h' */ +#define BZ_HDR_0 0x30 /* '0' */ + +/*-- Constants for the back end. --*/ + +#define BZ_MAX_ALPHA_SIZE 258 +#define BZ_MAX_CODE_LEN 23 + +#define BZ_RUNA 0 +#define BZ_RUNB 1 + +#define BZ_N_GROUPS 6 +#define BZ_G_SIZE 50 +#define BZ_N_ITERS 4 + +#define BZ_MAX_SELECTORS (2 + (900000 / BZ_G_SIZE)) + + +/*-- Stuff for randomising repetitive blocks. --*/ + +extern Int32 BZ2_rNums[512]; + +#define BZ_RAND_DECLS \ + Int32 rNToGo; \ + Int32 rTPos \ + +#define BZ_RAND_INIT_MASK \ + s->rNToGo = 0; \ + s->rTPos = 0 \ + +#define BZ_RAND_MASK ((s->rNToGo == 1) ? 1 : 0) + +#define BZ_RAND_UPD_MASK \ + if (s->rNToGo == 0) { \ + s->rNToGo = BZ2_rNums[s->rTPos]; \ + s->rTPos++; \ + if (s->rTPos == 512) s->rTPos = 0; \ + } \ + s->rNToGo--; + + +/*-- Stuff for doing CRCs. --*/ + +extern UInt32 BZ2_crc32Table[256]; + +#define BZ_INITIALISE_CRC(crcVar) \ +{ \ + crcVar = 0xffffffffL; \ +} + +#define BZ_FINALISE_CRC(crcVar) \ +{ \ + crcVar = ~(crcVar); \ +} + +#define BZ_UPDATE_CRC(crcVar,cha) \ +{ \ + crcVar = (crcVar << 8) ^ \ + BZ2_crc32Table[(crcVar >> 24) ^ \ + ((UChar)cha)]; \ +} + + +/*-- States and modes for compression. --*/ + +#define BZ_M_IDLE 1 +#define BZ_M_RUNNING 2 +#define BZ_M_FLUSHING 3 +#define BZ_M_FINISHING 4 + +#define BZ_S_OUTPUT 1 +#define BZ_S_INPUT 2 + +#define BZ_N_RADIX 2 +#define BZ_N_QSORT 12 +#define BZ_N_SHELL 18 +#define BZ_N_OVERSHOOT (BZ_N_RADIX + BZ_N_QSORT + BZ_N_SHELL + 2) + + +/*-- Structure holding all the compression-side stuff. --*/ + +typedef + struct { + /* pointer back to the struct bz_stream */ + bz_stream* strm; + + /* mode this stream is in, and whether inputting */ + /* or outputting data */ + Int32 mode; + Int32 state; + + /* remembers avail_in when flush/finish requested */ + UInt32 avail_in_expect; + + /* for doing the block sorting */ + UInt32* arr1; + UInt32* arr2; + UInt32* ftab; + Int32 origPtr; + + /* aliases for arr1 and arr2 */ + UInt32* ptr; + UChar* block; + UInt16* mtfv; + UChar* zbits; + + /* for deciding when to use the fallback sorting algorithm */ + Int32 workFactor; + + /* run-length-encoding of the input */ + UInt32 state_in_ch; + Int32 state_in_len; + BZ_RAND_DECLS; + + /* input and output limits and current posns */ + Int32 nblock; + Int32 nblockMAX; + Int32 numZ; + Int32 state_out_pos; + + /* map of bytes used in block */ + Int32 nInUse; + Bool inUse[256]; + UChar unseqToSeq[256]; + + /* the buffer for bit stream creation */ + UInt32 bsBuff; + Int32 bsLive; + + /* block and combined CRCs */ + UInt32 blockCRC; + UInt32 combinedCRC; + + /* misc administratium */ + Int32 verbosity; + Int32 blockNo; + Int32 blockSize100k; + + /* stuff for coding the MTF values */ + Int32 nMTF; + Int32 mtfFreq [BZ_MAX_ALPHA_SIZE]; + UChar selector [BZ_MAX_SELECTORS]; + UChar selectorMtf[BZ_MAX_SELECTORS]; + + UChar len [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; + Int32 code [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; + Int32 rfreq [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; + /* second dimension: only 3 needed; 4 makes index calculations faster */ + UInt32 len_pack[BZ_MAX_ALPHA_SIZE][4]; + + } + EState; + + +/*-- externs for compression. --*/ + +extern void +BZ2_blockSort ( EState* ); + +extern void +BZ2_compressBlock ( EState*, Bool ); + +extern void +BZ2_bsInitWrite ( EState* ); + +extern void +BZ2_hbAssignCodes ( Int32*, UChar*, Int32, Int32, Int32 ); + +extern void +BZ2_hbMakeCodeLengths ( UChar*, Int32*, Int32, Int32 ); + + +/*-- states for decompression. --*/ + +#define BZ_X_IDLE 1 +#define BZ_X_OUTPUT 2 + +#define BZ_X_MAGIC_1 10 +#define BZ_X_MAGIC_2 11 +#define BZ_X_MAGIC_3 12 +#define BZ_X_MAGIC_4 13 +#define BZ_X_BLKHDR_1 14 +#define BZ_X_BLKHDR_2 15 +#define BZ_X_BLKHDR_3 16 +#define BZ_X_BLKHDR_4 17 +#define BZ_X_BLKHDR_5 18 +#define BZ_X_BLKHDR_6 19 +#define BZ_X_BCRC_1 20 +#define BZ_X_BCRC_2 21 +#define BZ_X_BCRC_3 22 +#define BZ_X_BCRC_4 23 +#define BZ_X_RANDBIT 24 +#define BZ_X_ORIGPTR_1 25 +#define BZ_X_ORIGPTR_2 26 +#define BZ_X_ORIGPTR_3 27 +#define BZ_X_MAPPING_1 28 +#define BZ_X_MAPPING_2 29 +#define BZ_X_SELECTOR_1 30 +#define BZ_X_SELECTOR_2 31 +#define BZ_X_SELECTOR_3 32 +#define BZ_X_CODING_1 33 +#define BZ_X_CODING_2 34 +#define BZ_X_CODING_3 35 +#define BZ_X_MTF_1 36 +#define BZ_X_MTF_2 37 +#define BZ_X_MTF_3 38 +#define BZ_X_MTF_4 39 +#define BZ_X_MTF_5 40 +#define BZ_X_MTF_6 41 +#define BZ_X_ENDHDR_2 42 +#define BZ_X_ENDHDR_3 43 +#define BZ_X_ENDHDR_4 44 +#define BZ_X_ENDHDR_5 45 +#define BZ_X_ENDHDR_6 46 +#define BZ_X_CCRC_1 47 +#define BZ_X_CCRC_2 48 +#define BZ_X_CCRC_3 49 +#define BZ_X_CCRC_4 50 + + +/*-- Constants for the fast MTF decoder. --*/ + +#define MTFA_SIZE 4096 +#define MTFL_SIZE 16 + + +/*-- Structure holding all the decompression-side stuff. --*/ + +typedef + struct { + /* pointer back to the struct bz_stream */ + bz_stream* strm; + + /* state indicator for this stream */ + Int32 state; + + /* for doing the final run-length decoding */ + UChar state_out_ch; + Int32 state_out_len; + Bool blockRandomised; + BZ_RAND_DECLS; + + /* the buffer for bit stream reading */ + UInt32 bsBuff; + Int32 bsLive; + + /* misc administratium */ + Int32 blockSize100k; + Bool smallDecompress; + Int32 currBlockNo; + Int32 verbosity; + + /* for undoing the Burrows-Wheeler transform */ + Int32 origPtr; + UInt32 tPos; + Int32 k0; + Int32 unzftab[256]; + Int32 nblock_used; + Int32 cftab[257]; + Int32 cftabCopy[257]; + + /* for undoing the Burrows-Wheeler transform (FAST) */ + UInt32 *tt; + + /* for undoing the Burrows-Wheeler transform (SMALL) */ + UInt16 *ll16; + UChar *ll4; + + /* stored and calculated CRCs */ + UInt32 storedBlockCRC; + UInt32 storedCombinedCRC; + UInt32 calculatedBlockCRC; + UInt32 calculatedCombinedCRC; + + /* map of bytes used in block */ + Int32 nInUse; + Bool inUse[256]; + Bool inUse16[16]; + UChar seqToUnseq[256]; + + /* for decoding the MTF values */ + UChar mtfa [MTFA_SIZE]; + Int32 mtfbase[256 / MTFL_SIZE]; + UChar selector [BZ_MAX_SELECTORS]; + UChar selectorMtf[BZ_MAX_SELECTORS]; + UChar len [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; + + Int32 limit [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; + Int32 base [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; + Int32 perm [BZ_N_GROUPS][BZ_MAX_ALPHA_SIZE]; + Int32 minLens[BZ_N_GROUPS]; + + /* save area for scalars in the main decompress code */ + Int32 save_i; + Int32 save_j; + Int32 save_t; + Int32 save_alphaSize; + Int32 save_nGroups; + Int32 save_nSelectors; + Int32 save_EOB; + Int32 save_groupNo; + Int32 save_groupPos; + Int32 save_nextSym; + Int32 save_nblockMAX; + Int32 save_nblock; + Int32 save_es; + Int32 save_N; + Int32 save_curr; + Int32 save_zt; + Int32 save_zn; + Int32 save_zvec; + Int32 save_zj; + Int32 save_gSel; + Int32 save_gMinlen; + Int32* save_gLimit; + Int32* save_gBase; + Int32* save_gPerm; + + } + DState; + + +/*-- Macros for decompression. --*/ + +#define BZ_GET_FAST(cccc) \ + s->tPos = s->tt[s->tPos]; \ + cccc = (UChar)(s->tPos & 0xff); \ + s->tPos >>= 8; + +#define BZ_GET_FAST_C(cccc) \ + c_tPos = c_tt[c_tPos]; \ + cccc = (UChar)(c_tPos & 0xff); \ + c_tPos >>= 8; + +#define SET_LL4(i,n) \ + { if (((i) & 0x1) == 0) \ + s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0xf0) | (n); else \ + s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0x0f) | ((n) << 4); \ + } + +#define GET_LL4(i) \ + ((((UInt32)(s->ll4[(i) >> 1])) >> (((i) << 2) & 0x4)) & 0xF) + +#define SET_LL(i,n) \ + { s->ll16[i] = (UInt16)(n & 0x0000ffff); \ + SET_LL4(i, n >> 16); \ + } + +#define GET_LL(i) \ + (((UInt32)s->ll16[i]) | (GET_LL4(i) << 16)) + +#define BZ_GET_SMALL(cccc) \ + cccc = BZ2_indexIntoF ( s->tPos, s->cftab ); \ + s->tPos = GET_LL(s->tPos); + + +/*-- externs for decompression. --*/ + +extern Int32 +BZ2_indexIntoF ( Int32, Int32* ); + +extern Int32 +BZ2_decompress ( DState* ); + +extern void +BZ2_hbCreateDecodeTables ( Int32*, Int32*, Int32*, UChar*, + Int32, Int32, Int32 ); + + +#endif + + +/*-- BZ_NO_STDIO seems to make NULL disappear on some platforms. --*/ + +#ifdef BZ_NO_STDIO +#ifndef NULL +#define NULL 0 +#endif +#endif + + +/*-------------------------------------------------------------*/ +/*--- end bzlib_private.h ---*/ +/*-------------------------------------------------------------*/ diff --git a/lib_generic/bzlib_randtable.c b/lib_generic/bzlib_randtable.c new file mode 100644 index 0000000..a0dd573 --- /dev/null +++ b/lib_generic/bzlib_randtable.c @@ -0,0 +1,128 @@ +#include +#ifdef CONFIG_BZIP2 + +/*-------------------------------------------------------------*/ +/*--- Table for randomising repetitive blocks ---*/ +/*--- randtable.c ---*/ +/*-------------------------------------------------------------*/ + +/*-- + This file is a part of bzip2 and/or libbzip2, a program and + library for lossless, block-sorting data compression. + + Copyright (C) 1996-2002 Julian R Seward. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. The origin of this software must not be misrepresented; you must + not claim that you wrote the original software. If you use this + software in a product, an acknowledgment in the product + documentation would be appreciated but is not required. + + 3. Altered source versions must be plainly marked as such, and must + not be misrepresented as being the original software. + + 4. The name of the author may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Julian Seward, Cambridge, UK. + jseward@acm.org + bzip2/libbzip2 version 1.0 of 21 March 2000 + + This program is based on (at least) the work of: + Mike Burrows + David Wheeler + Peter Fenwick + Alistair Moffat + Radford Neal + Ian H. Witten + Robert Sedgewick + Jon L. Bentley + + For more information on these sources, see the manual. +--*/ + + +#include "bzlib_private.h" + + +/*---------------------------------------------*/ +Int32 BZ2_rNums[512] = { + 619, 720, 127, 481, 931, 816, 813, 233, 566, 247, + 985, 724, 205, 454, 863, 491, 741, 242, 949, 214, + 733, 859, 335, 708, 621, 574, 73, 654, 730, 472, + 419, 436, 278, 496, 867, 210, 399, 680, 480, 51, + 878, 465, 811, 169, 869, 675, 611, 697, 867, 561, + 862, 687, 507, 283, 482, 129, 807, 591, 733, 623, + 150, 238, 59, 379, 684, 877, 625, 169, 643, 105, + 170, 607, 520, 932, 727, 476, 693, 425, 174, 647, + 73, 122, 335, 530, 442, 853, 695, 249, 445, 515, + 909, 545, 703, 919, 874, 474, 882, 500, 594, 612, + 641, 801, 220, 162, 819, 984, 589, 513, 495, 799, + 161, 604, 958, 533, 221, 400, 386, 867, 600, 782, + 382, 596, 414, 171, 516, 375, 682, 485, 911, 276, + 98, 553, 163, 354, 666, 933, 424, 341, 533, 870, + 227, 730, 475, 186, 263, 647, 537, 686, 600, 224, + 469, 68, 770, 919, 190, 373, 294, 822, 808, 206, + 184, 943, 795, 384, 383, 461, 404, 758, 839, 887, + 715, 67, 618, 276, 204, 918, 873, 777, 604, 560, + 951, 160, 578, 722, 79, 804, 96, 409, 713, 940, + 652, 934, 970, 447, 318, 353, 859, 672, 112, 785, + 645, 863, 803, 350, 139, 93, 354, 99, 820, 908, + 609, 772, 154, 274, 580, 184, 79, 626, 630, 742, + 653, 282, 762, 623, 680, 81, 927, 626, 789, 125, + 411, 521, 938, 300, 821, 78, 343, 175, 128, 250, + 170, 774, 972, 275, 999, 639, 495, 78, 352, 126, + 857, 956, 358, 619, 580, 124, 737, 594, 701, 612, + 669, 112, 134, 694, 363, 992, 809, 743, 168, 974, + 944, 375, 748, 52, 600, 747, 642, 182, 862, 81, + 344, 805, 988, 739, 511, 655, 814, 334, 249, 515, + 897, 955, 664, 981, 649, 113, 974, 459, 893, 228, + 433, 837, 553, 268, 926, 240, 102, 654, 459, 51, + 686, 754, 806, 760, 493, 403, 415, 394, 687, 700, + 946, 670, 656, 610, 738, 392, 760, 799, 887, 653, + 978, 321, 576, 617, 626, 502, 894, 679, 243, 440, + 680, 879, 194, 572, 640, 724, 926, 56, 204, 700, + 707, 151, 457, 449, 797, 195, 791, 558, 945, 679, + 297, 59, 87, 824, 713, 663, 412, 693, 342, 606, + 134, 108, 571, 364, 631, 212, 174, 643, 304, 329, + 343, 97, 430, 751, 497, 314, 983, 374, 822, 928, + 140, 206, 73, 263, 980, 736, 876, 478, 430, 305, + 170, 514, 364, 692, 829, 82, 855, 953, 676, 246, + 369, 970, 294, 750, 807, 827, 150, 790, 288, 923, + 804, 378, 215, 828, 592, 281, 565, 555, 710, 82, + 896, 831, 547, 261, 524, 462, 293, 465, 502, 56, + 661, 821, 976, 991, 658, 869, 905, 758, 745, 193, + 768, 550, 608, 933, 378, 286, 215, 979, 792, 961, + 61, 688, 793, 644, 986, 403, 106, 366, 905, 644, + 372, 567, 466, 434, 645, 210, 389, 550, 919, 135, + 780, 773, 635, 389, 707, 100, 626, 958, 165, 504, + 920, 176, 193, 713, 857, 265, 203, 50, 668, 108, + 645, 990, 626, 197, 510, 357, 358, 850, 858, 364, + 936, 638 +}; + + +/*-------------------------------------------------------------*/ +/*--- end randtable.c ---*/ +/*-------------------------------------------------------------*/ + +#endif /* CONFIG_BZIP2 */ diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c new file mode 100644 index 0000000..50ca4ff --- /dev/null +++ b/lib_generic/crc32.c @@ -0,0 +1,197 @@ +/* + * This file is derived from crc32.c from the zlib-1.1.3 distribution + * by Jean-loup Gailly and Mark Adler. + */ + +/* crc32.c -- compute the CRC-32 of a data stream + * Copyright (C) 1995-1998 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +#ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */ +#include /* to get command definitions like CFG_CMD_JFFS2 */ +#endif + +#include "zlib.h" + +#define local static +#define ZEXPORT /* empty */ +unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); + +#ifdef DYNAMIC_CRC_TABLE + +local int crc_table_empty = 1; +local uLongf crc_table[256]; +local void make_crc_table OF((void)); + +/* + Generate a table for a byte-wise 32-bit CRC calculation on the polynomial: + x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1. + + Polynomials over GF(2) are represented in binary, one bit per coefficient, + with the lowest powers in the most significant bit. Then adding polynomials + is just exclusive-or, and multiplying a polynomial by x is a right shift by + one. If we call the above polynomial p, and represent a byte as the + polynomial q, also with the lowest power in the most significant bit (so the + byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p, + where a mod b means the remainder after dividing a by b. + + This calculation is done using the shift-register method of multiplying and + taking the remainder. The register is initialized to zero, and for each + incoming bit, x^32 is added mod p to the register if the bit is a one (where + x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by + x (which is shifting right by one and adding x^32 mod p if the bit shifted + out is a one). We start with the highest power (least significant bit) of + q and repeat for all eight bits of q. + + The table is simply the CRC of all possible eight bit values. This is all + the information needed to generate CRC's on data a byte at a time for all + combinations of CRC register values and incoming bytes. +*/ +local void make_crc_table() +{ + uLong c; + int n, k; + uLong poly; /* polynomial exclusive-or pattern */ + /* terms of polynomial defining this crc (except x^32): */ + static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26}; + + /* make exclusive-or pattern from polynomial (0xedb88320L) */ + poly = 0L; + for (n = 0; n < sizeof(p)/sizeof(Byte); n++) + poly |= 1L << (31 - p[n]); + + for (n = 0; n < 256; n++) + { + c = (uLong)n; + for (k = 0; k < 8; k++) + c = c & 1 ? poly ^ (c >> 1) : c >> 1; + crc_table[n] = c; + } + crc_table_empty = 0; +} +#else +/* ======================================================================== + * Table of CRC-32's of all single-byte values (made by make_crc_table) + */ +local const uLongf crc_table[256] = { + 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, + 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L, + 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, + 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL, + 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L, + 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L, + 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L, + 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL, + 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L, + 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL, + 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L, + 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L, + 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L, + 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL, + 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL, + 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L, + 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL, + 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L, + 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L, + 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L, + 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL, + 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L, + 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L, + 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL, + 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L, + 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L, + 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L, + 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L, + 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L, + 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL, + 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL, + 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L, + 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L, + 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL, + 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL, + 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L, + 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL, + 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L, + 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL, + 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L, + 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL, + 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L, + 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L, + 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL, + 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L, + 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L, + 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L, + 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L, + 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L, + 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L, + 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL, + 0x2d02ef8dL +}; +#endif + +#if 0 +/* ========================================================================= + * This function can be used by asm versions of crc32() + */ +const uLongf * ZEXPORT get_crc_table() +{ +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) make_crc_table(); +#endif + return (const uLongf *)crc_table; +} +#endif + +/* ========================================================================= */ +#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8); +#define DO2(buf) DO1(buf); DO1(buf); +#define DO4(buf) DO2(buf); DO2(buf); +#define DO8(buf) DO4(buf); DO4(buf); + +/* ========================================================================= */ +uLong ZEXPORT crc32(crc, buf, len) + uLong crc; + const Bytef *buf; + uInt len; +{ +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) + make_crc_table(); +#endif + crc = crc ^ 0xffffffffL; + while (len >= 8) + { + DO8(buf); + len -= 8; + } + if (len) do { + DO1(buf); + } while (--len); + return crc ^ 0xffffffffL; +} + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +/* No ones complement version. JFFS2 (and other things ?) + * don't use ones compliment in their CRC calculations. + */ +uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len) +{ +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) + make_crc_table(); +#endif + while (len >= 8) + { + DO8(buf); + len -= 8; + } + if (len) do { + DO1(buf); + } while (--len); + + return crc; +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/lib_generic/ctype.c b/lib_generic/ctype.c new file mode 100644 index 0000000..6ed0468 --- /dev/null +++ b/lib_generic/ctype.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * linux/lib/ctype.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +#include + +unsigned char _ctype[] = { +_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ +_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ +_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ +_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ +_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ +_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ +_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ +_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ +_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ +_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ +_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */ +_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */ +_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */ +_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */ +_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */ +_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */ diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c new file mode 100644 index 0000000..512e898 --- /dev/null +++ b/lib_generic/display_options.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +int display_options (void) +{ + extern char version_string[]; + +#if defined(BUILD_TAG) + printf ("\n\n%s, Build: %s\n\n", version_string, BUILD_TAG); +#else + printf ("\n\n%s\n\n", version_string); +#endif + return 0; +} + +/* + * print sizes as "xxx kB", "xxx.y kB", "xxx MB" or "xxx.y MB" as needed; + * allow for optional trailing string (like "\n") + */ +void print_size (ulong size, const char *s) +{ + ulong m, n; + ulong d = 1 << 20; /* 1 MB */ + char c = 'M'; + + if (size < d) { /* print in kB */ + c = 'k'; + d = 1 << 10; + } + + n = size / d; + + m = (10 * (size - (n * d)) + (d / 2) ) / d; + + if (m >= 10) { + m -= 10; + n += 1; + } + + printf ("%2ld", n); + if (m) { + printf (".%ld", m); + } + printf (" %cB%s", c, s); +} diff --git a/lib_generic/ldiv.c b/lib_generic/ldiv.c new file mode 100644 index 0000000..5d231a2 --- /dev/null +++ b/lib_generic/ldiv.c @@ -0,0 +1,55 @@ +/* Copyright (C) 1992, 1997 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with the GNU C Library; see the file COPYING.LIB. If not, + write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +typedef struct { + long quot; + long rem; +} ldiv_t; +/* Return the `ldiv_t' representation of NUMER over DENOM. */ +ldiv_t +ldiv (long int numer, long int denom) +{ + ldiv_t result; + + result.quot = numer / denom; + result.rem = numer % denom; + + /* The ANSI standard says that |QUOT| <= |NUMER / DENOM|, where + NUMER / DENOM is to be computed in infinite precision. In + other words, we should always truncate the quotient towards + zero, never -infinity. Machine division and remainer may + work either way when one or both of NUMER or DENOM is + negative. If only one is negative and QUOT has been + truncated towards -infinity, REM will have the same sign as + DENOM and the opposite sign of NUMER; if both are negative + and QUOT has been truncated towards -infinity, REM will be + positive (will have the opposite sign of NUMER). These are + considered `wrong'. If both are NUM and DENOM are positive, + RESULT will always be positive. This all boils down to: if + NUMER >= 0, but REM < 0, we got the wrong answer. In that + case, to get the right answer, add 1 to QUOT and subtract + DENOM from REM. */ + + if (numer >= 0 && result.rem < 0) + { + ++result.quot; + result.rem -= denom; + } + + return result; +} diff --git a/lib_generic/string.c b/lib_generic/string.c new file mode 100644 index 0000000..0e99d1b --- /dev/null +++ b/lib_generic/string.c @@ -0,0 +1,578 @@ +/* + * linux/lib/string.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* + * stupid library routines.. The optimized versions should generally be found + * as inline code in + * + * These are buggy as well.. + * + * * Fri Jun 25 1999, Ingo Oeser + * - Added strsep() which will replace strtok() soon (because strsep() is + * reentrant and should be faster). Use only strsep() in new code, please. + */ + +#include +#include +#include +#include + + +#ifndef __HAVE_ARCH_STRNICMP +/** + * strnicmp - Case insensitive, length-limited string comparison + * @s1: One string + * @s2: The other string + * @len: the maximum number of characters to compare + */ +int strnicmp(const char *s1, const char *s2, size_t len) +{ + /* Yes, Virginia, it had better be unsigned */ + unsigned char c1, c2; + + c1 = 0; c2 = 0; + if (len) { + do { + c1 = *s1; c2 = *s2; + s1++; s2++; + if (!c1) + break; + if (!c2) + break; + if (c1 == c2) + continue; + c1 = tolower(c1); + c2 = tolower(c2); + if (c1 != c2) + break; + } while (--len); + } + return (int)c1 - (int)c2; +} +#endif + +char * ___strtok; + +#ifndef __HAVE_ARCH_STRCPY +/** + * strcpy - Copy a %NUL terminated string + * @dest: Where to copy the string to + * @src: Where to copy the string from + */ +char * strcpy(char * dest,const char *src) +{ + char *tmp = dest; + + while ((*dest++ = *src++) != '\0') + /* nothing */; + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRNCPY +/** + * strncpy - Copy a length-limited, %NUL-terminated string + * @dest: Where to copy the string to + * @src: Where to copy the string from + * @count: The maximum number of bytes to copy + * + * Note that unlike userspace strncpy, this does not %NUL-pad the buffer. + * However, the result is not %NUL-terminated if the source exceeds + * @count bytes. + */ +char * strncpy(char * dest,const char *src,size_t count) +{ + char *tmp = dest; + + while (count-- && (*dest++ = *src++) != '\0') + /* nothing */; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCAT +/** + * strcat - Append one %NUL-terminated string to another + * @dest: The string to be appended to + * @src: The string to append to it + */ +char * strcat(char * dest, const char * src) +{ + char *tmp = dest; + + while (*dest) + dest++; + while ((*dest++ = *src++) != '\0') + ; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRNCAT +/** + * strncat - Append a length-limited, %NUL-terminated string to another + * @dest: The string to be appended to + * @src: The string to append to it + * @count: The maximum numbers of bytes to copy + * + * Note that in contrast to strncpy, strncat ensures the result is + * terminated. + */ +char * strncat(char *dest, const char *src, size_t count) +{ + char *tmp = dest; + + if (count) { + while (*dest) + dest++; + while ((*dest++ = *src++)) { + if (--count == 0) { + *dest = '\0'; + break; + } + } + } + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCMP +/** + * strcmp - Compare two strings + * @cs: One string + * @ct: Another string + */ +int strcmp(const char * cs,const char * ct) +{ + register signed char __res; + + while (1) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRNCMP +/** + * strncmp - Compare two length-limited strings + * @cs: One string + * @ct: Another string + * @count: The maximum number of bytes to compare + */ +int strncmp(const char * cs,const char * ct,size_t count) +{ + register signed char __res = 0; + + while (count) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + count--; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRCHR +/** + * strchr - Find the first occurrence of a character in a string + * @s: The string to be searched + * @c: The character to search for + */ +char * strchr(const char * s, int c) +{ + for(; *s != (char) c; ++s) + if (*s == '\0') + return NULL; + return (char *) s; +} +#endif + +#ifndef __HAVE_ARCH_STRRCHR +/** + * strrchr - Find the last occurrence of a character in a string + * @s: The string to be searched + * @c: The character to search for + */ +char * strrchr(const char * s, int c) +{ + const char *p = s + strlen(s); + do { + if (*p == (char)c) + return (char *)p; + } while (--p >= s); + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_STRLEN +/** + * strlen - Find the length of a string + * @s: The string to be sized + */ +size_t strlen(const char * s) +{ + const char *sc; + + for (sc = s; *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRNLEN +/** + * strnlen - Find the length of a length-limited string + * @s: The string to be sized + * @count: The maximum number of bytes to search + */ +size_t strnlen(const char * s, size_t count) +{ + const char *sc; + + for (sc = s; count-- && *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRDUP +char * strdup(const char *s) +{ + char *new; + + if ((s == NULL) || + ((new = malloc (strlen(s) + 1)) == NULL) ) { + return NULL; + } + + strcpy (new, s); + return new; +} +#endif + +#ifndef __HAVE_ARCH_STRSPN +/** + * strspn - Calculate the length of the initial substring of @s which only + * contain letters in @accept + * @s: The string to be searched + * @accept: The string to search for + */ +size_t strspn(const char *s, const char *accept) +{ + const char *p; + const char *a; + size_t count = 0; + + for (p = s; *p != '\0'; ++p) { + for (a = accept; *a != '\0'; ++a) { + if (*p == *a) + break; + } + if (*a == '\0') + return count; + ++count; + } + + return count; +} +#endif + +#ifndef __HAVE_ARCH_STRPBRK +/** + * strpbrk - Find the first occurrence of a set of characters + * @cs: The string to be searched + * @ct: The characters to search for + */ +char * strpbrk(const char * cs,const char * ct) +{ + const char *sc1,*sc2; + + for( sc1 = cs; *sc1 != '\0'; ++sc1) { + for( sc2 = ct; *sc2 != '\0'; ++sc2) { + if (*sc1 == *sc2) + return (char *) sc1; + } + } + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_STRTOK +/** + * strtok - Split a string into tokens + * @s: The string to be searched + * @ct: The characters to search for + * + * WARNING: strtok is deprecated, use strsep instead. + */ +char * strtok(char * s,const char * ct) +{ + char *sbegin, *send; + + sbegin = s ? s : ___strtok; + if (!sbegin) { + return NULL; + } + sbegin += strspn(sbegin,ct); + if (*sbegin == '\0') { + ___strtok = NULL; + return( NULL ); + } + send = strpbrk( sbegin, ct); + if (send && *send != '\0') + *send++ = '\0'; + ___strtok = send; + return (sbegin); +} +#endif + +#ifndef __HAVE_ARCH_STRSEP +/** + * strsep - Split a string into tokens + * @s: The string to be searched + * @ct: The characters to search for + * + * strsep() updates @s to point after the token, ready for the next call. + * + * It returns empty tokens, too, behaving exactly like the libc function + * of that name. In fact, it was stolen from glibc2 and de-fancy-fied. + * Same semantics, slimmer shape. ;) + */ +char * strsep(char **s, const char *ct) +{ + char *sbegin = *s, *end; + + if (sbegin == NULL) + return NULL; + + end = strpbrk(sbegin, ct); + if (end) + *end++ = '\0'; + *s = end; + + return sbegin; +} +#endif + +#ifndef __HAVE_ARCH_STRSWAB +/** + * strswab - swap adjacent even and odd bytes in %NUL-terminated string + * s: address of the string + * + * returns the address of the swapped string or NULL on error. If + * string length is odd, last byte is untouched. + */ +char *strswab(const char *s) +{ + char *p, *q; + + if ((NULL == s) || ('\0' == *s)) { + return (NULL); + } + + for (p=(char *)s, q=p+1; (*p != '\0') && (*q != '\0'); p+=2, q+=2) { + char tmp; + + tmp = *p; + *p = *q; + *q = tmp; + } + + return (char *) s; +} +#endif + +#ifndef __HAVE_ARCH_MEMSET +/** + * memset - Fill a region of memory with the given value + * @s: Pointer to the start of the area. + * @c: The byte to fill the area with + * @count: The size of the area. + * + * Do not use memset() to access IO space, use memset_io() instead. + */ +void * memset(void * s,int c,size_t count) +{ + char *xs = (char *) s; + + while (count--) + *xs++ = c; + + return s; +} +#endif + +#ifndef __HAVE_ARCH_BCOPY +/** + * bcopy - Copy one area of memory to another + * @src: Where to copy from + * @dest: Where to copy to + * @count: The size of the area. + * + * Note that this is the same as memcpy(), with the arguments reversed. + * memcpy() is the standard, bcopy() is a legacy BSD function. + * + * You should not use this function to access IO space, use memcpy_toio() + * or memcpy_fromio() instead. + */ +char * bcopy(const char * src, char * dest, int count) +{ + char *tmp = dest; + + while (count--) + *tmp++ = *src++; + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMCPY +/** + * memcpy - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * You should not use this function to access IO space, use memcpy_toio() + * or memcpy_fromio() instead. + */ +void * memcpy(void * dest,const void *src,size_t count) +{ + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMMOVE +/** + * memmove - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * Unlike memcpy(), memmove() copes with overlapping areas. + */ +void * memmove(void * dest,const void *src,size_t count) +{ + char *tmp, *s; + + if (dest <= src) { + tmp = (char *) dest; + s = (char *) src; + while (count--) + *tmp++ = *s++; + } + else { + tmp = (char *) dest + count; + s = (char *) src + count; + while (count--) + *--tmp = *--s; + } + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMCMP +/** + * memcmp - Compare two areas of memory + * @cs: One area of memory + * @ct: Another area of memory + * @count: The size of the area. + */ +int memcmp(const void * cs,const void * ct,size_t count) +{ + const unsigned char *su1, *su2; + int res = 0; + + for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) + if ((res = *su1 - *su2) != 0) + break; + return res; +} +#endif + +#ifndef __HAVE_ARCH_MEMSCAN +/** + * memscan - Find a character in an area of memory. + * @addr: The memory area + * @c: The byte to search for + * @size: The size of the area. + * + * returns the address of the first occurrence of @c, or 1 byte past + * the area if @c is not found + */ +void * memscan(void * addr, int c, size_t size) +{ + unsigned char * p = (unsigned char *) addr; + + while (size) { + if (*p == c) + return (void *) p; + p++; + size--; + } + return (void *) p; +} +#endif + +#ifndef __HAVE_ARCH_STRSTR +/** + * strstr - Find the first substring in a %NUL terminated string + * @s1: The string to be searched + * @s2: The string to search for + */ +char * strstr(const char * s1,const char * s2) +{ + int l1, l2; + + l2 = strlen(s2); + if (!l2) + return (char *) s1; + l1 = strlen(s1); + while (l1 >= l2) { + l1--; + if (!memcmp(s1,s2,l2)) + return (char *) s1; + s1++; + } + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_MEMCHR +/** + * memchr - Find a character in an area of memory. + * @s: The memory area + * @c: The byte to search for + * @n: The size of the area. + * + * returns the address of the first occurrence of @c, or %NULL + * if @c is not found + */ +void *memchr(const void *s, int c, size_t n) +{ + const unsigned char *p = s; + while (n-- != 0) { + if ((unsigned char)c == *p++) { + return (void *)(p-1); + } + } + return NULL; +} + +#endif diff --git a/lib_generic/vsprintf.c b/lib_generic/vsprintf.c new file mode 100644 index 0000000..2740f2e --- /dev/null +++ b/lib_generic/vsprintf.c @@ -0,0 +1,385 @@ +/* + * linux/lib/vsprintf.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */ +/* + * Wirzenius wrote this portably, Torvalds fucked it up :-) + */ + +#include +#include +#include +#include + +#include +#if !defined (CONFIG_PANIC_HANG) +#include +/*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +#endif + +unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) +{ + unsigned long result = 0,value; + + if (*cp == '0') { + cp++; + if ((*cp == 'x') && isxdigit(cp[1])) { + base = 16; + cp++; + } + if (!base) { + base = 8; + } + } + if (!base) { + base = 10; + } + while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) + ? toupper(*cp) : *cp)-'A'+10) < base) { + result = result*base + value; + cp++; + } + if (endp) + *endp = (char *)cp; + return result; +} + +long simple_strtol(const char *cp,char **endp,unsigned int base) +{ + if(*cp=='-') + return -simple_strtoul(cp+1,endp,base); + return simple_strtoul(cp,endp,base); +} + +#ifdef CFG_64BIT_STRTOUL +unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base) +{ + unsigned long long result = 0, value; + + if (*cp == '0') { + cp++; + if ((*cp == 'x') && isxdigit (cp[1])) { + base = 16; + cp++; + } + if (!base) { + base = 8; + } + } + if (!base) { + base = 10; + } + while (isxdigit (*cp) && (value = isdigit (*cp) + ? *cp - '0' + : (islower (*cp) ? toupper (*cp) : *cp) - 'A' + 10) < base) { + result = result * base + value; + cp++; + } + if (endp) + *endp = (char *) cp; + return result; +} +#endif /* CFG_64BIT_STRTOUL */ + +/* we use this so that we can do without the ctype library */ +#define is_digit(c) ((c) >= '0' && (c) <= '9') + +static int skip_atoi(const char **s) +{ + int i=0; + + while (is_digit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} + +#define ZEROPAD 1 /* pad with zero */ +#define SIGN 2 /* unsigned/signed long */ +#define PLUS 4 /* show plus */ +#define SPACE 8 /* space if plus */ +#define LEFT 16 /* left justified */ +#define SPECIAL 32 /* 0x */ +#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ + +#define do_div(n,base) ({ \ + int __res; \ + __res = ((unsigned long) n) % (unsigned) base; \ + n = ((unsigned long) n) / (unsigned) base; \ + __res; \ +}) + +#ifdef CFG_64BIT_VSPRINTF +static char * number(char * str, long long num, int base, int size, int precision ,int type) +#else +static char * number(char * str, long num, int base, int size, int precision ,int type) +#endif +{ + char c,sign,tmp[66]; + const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; + int i; + + if (type & LARGE) + digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + if (type & LEFT) + type &= ~ZEROPAD; + if (base < 2 || base > 36) + return 0; + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + if (type & SIGN) { + if (num < 0) { + sign = '-'; + num = -num; + size--; + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (type & SPECIAL) { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } + i = 0; + if (num == 0) + tmp[i++]='0'; + else while (num != 0) + tmp[i++] = digits[do_div(num,base)]; + if (i > precision) + precision = i; + size -= precision; + if (!(type&(ZEROPAD+LEFT))) + while(size-->0) + *str++ = ' '; + if (sign) + *str++ = sign; + if (type & SPECIAL) { + if (base==8) + *str++ = '0'; + else if (base==16) { + *str++ = '0'; + *str++ = digits[33]; + } + } + if (!(type & LEFT)) + while (size-- > 0) + *str++ = c; + while (i < precision--) + *str++ = '0'; + while (i-- > 0) + *str++ = tmp[i]; + while (size-- > 0) + *str++ = ' '; + return str; +} + +/* Forward decl. needed for IP address printing stuff... */ +int sprintf(char * buf, const char *fmt, ...); + +int vsprintf(char *buf, const char *fmt, va_list args) +{ + int len; +#ifdef CFG_64BIT_VSPRINTF + unsigned long long num; +#else + unsigned long num; +#endif + int i, base; + char * str; + const char *s; + + int flags; /* flags to number() */ + + int field_width; /* width of output field */ + int precision; /* min. # of digits for integers; max + number of chars for from string */ + int qualifier; /* 'h', 'l', or 'q' for integer fields */ + + for (str=buf ; *fmt ; ++fmt) { + if (*fmt != '%') { + *str++ = *fmt; + continue; + } + + /* process flags */ + flags = 0; + repeat: + ++fmt; /* this also skips first '%' */ + switch (*fmt) { + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= SPECIAL; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } + + /* get field width */ + field_width = -1; + if (is_digit(*fmt)) + field_width = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + field_width = va_arg(args, int); + if (field_width < 0) { + field_width = -field_width; + flags |= LEFT; + } + } + + /* get the precision */ + precision = -1; + if (*fmt == '.') { + ++fmt; + if (is_digit(*fmt)) + precision = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + precision = va_arg(args, int); + } + if (precision < 0) + precision = 0; + } + + /* get the conversion qualifier */ + qualifier = -1; + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'q') { + qualifier = *fmt; + ++fmt; + } + + /* default base */ + base = 10; + + switch (*fmt) { + case 'c': + if (!(flags & LEFT)) + while (--field_width > 0) + *str++ = ' '; + *str++ = (unsigned char) va_arg(args, int); + while (--field_width > 0) + *str++ = ' '; + continue; + + case 's': + s = va_arg(args, char *); + if (!s) + s = ""; + + len = strnlen(s, precision); + + if (!(flags & LEFT)) + while (len < field_width--) + *str++ = ' '; + for (i = 0; i < len; ++i) + *str++ = *s++; + while (len < field_width--) + *str++ = ' '; + continue; + + case 'p': + if (field_width == -1) { + field_width = 2*sizeof(void *); + flags |= ZEROPAD; + } + str = number(str, + (unsigned long) va_arg(args, void *), 16, + field_width, precision, flags); + continue; + + + case 'n': + if (qualifier == 'l') { + long * ip = va_arg(args, long *); + *ip = (str - buf); + } else { + int * ip = va_arg(args, int *); + *ip = (str - buf); + } + continue; + + case '%': + *str++ = '%'; + continue; + + /* integer number formats - set up the flags and "break" */ + case 'o': + base = 8; + break; + + case 'X': + flags |= LARGE; + case 'x': + base = 16; + break; + + case 'd': + case 'i': + flags |= SIGN; + case 'u': + break; + + default: + *str++ = '%'; + if (*fmt) + *str++ = *fmt; + else + --fmt; + continue; + } +#ifdef CFG_64BIT_VSPRINTF + if (qualifier == 'q') /* "quad" for 64 bit variables */ + num = va_arg(args, unsigned long long); + else +#endif + if (qualifier == 'l') + num = va_arg(args, unsigned long); + else if (qualifier == 'h') { + num = (unsigned short) va_arg(args, int); + if (flags & SIGN) + num = (short) num; + } else if (flags & SIGN) + num = va_arg(args, int); + else + num = va_arg(args, unsigned int); + str = number(str, num, base, field_width, precision, flags); + } + *str = '\0'; + return str-buf; +} + +int sprintf(char * buf, const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i=vsprintf(buf,fmt,args); + va_end(args); + return i; +} + +void panic(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + vprintf(fmt, args); + putc('\n'); + va_end(args); +#if defined (CONFIG_PANIC_HANG) + hang(); +#else + udelay (100000); /* allow messages to go out */ + do_reset (NULL, 0, 0, NULL); +#endif +} diff --git a/lib_generic/zlib.c b/lib_generic/zlib.c new file mode 100644 index 0000000..668ac8f --- /dev/null +++ b/lib_generic/zlib.c @@ -0,0 +1,2161 @@ +/* + * This file is derived from various .h and .c files from the zlib-0.95 + * distribution by Jean-loup Gailly and Mark Adler, with some additions + * by Paul Mackerras to aid in implementing Deflate compression and + * decompression for PPP packets. See zlib.h for conditions of + * distribution and use. + * + * Changes that have been made include: + * - changed functions not used outside this file to "local" + * - added minCompression parameter to deflateInit2 + * - added Z_PACKET_FLUSH (see zlib.h for details) + * - added inflateIncomp + */ + +/*+++++*/ +/* zutil.h -- internal interface and configuration of the compression library + * Copyright (C) 1995 Jean-loup Gailly. + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* WARNING: this file should *not* be used by applications. It is + part of the implementation of the compression library and is + subject to change. Applications should only use zlib.h. + */ + +/* From: zutil.h,v 1.9 1995/05/03 17:27:12 jloup Exp */ + +#define _Z_UTIL_H + +#include "zlib.h" + +#ifndef local +# define local static +#endif +/* compile with -Dlocal if your debugger can't find static symbols */ + +#define FAR + +typedef unsigned char uch; +typedef uch FAR uchf; +typedef unsigned short ush; +typedef ush FAR ushf; +typedef unsigned long ulg; + +extern char *z_errmsg[]; /* indexed by 1-zlib_error */ + +#define ERR_RETURN(strm,err) return (strm->msg=z_errmsg[1-err], err) +/* To be used only when the state is known to be valid */ + +#ifndef NULL +#define NULL ((void *) 0) +#endif + + /* common constants */ + +#define DEFLATED 8 + +#ifndef DEF_WBITS +# define DEF_WBITS MAX_WBITS +#endif +/* default windowBits for decompression. MAX_WBITS is for compression only */ + +#if MAX_MEM_LEVEL >= 8 +# define DEF_MEM_LEVEL 8 +#else +# define DEF_MEM_LEVEL MAX_MEM_LEVEL +#endif +/* default memLevel */ + +#define STORED_BLOCK 0 +#define STATIC_TREES 1 +#define DYN_TREES 2 +/* The three kinds of block type */ + +#define MIN_MATCH 3 +#define MAX_MATCH 258 +/* The minimum and maximum match lengths */ + + /* functions */ + +#include +#define zmemcpy memcpy +#define zmemzero(dest, len) memset(dest, 0, len) + +/* Diagnostic functions */ +#ifdef DEBUG_ZLIB +# include +# ifndef verbose +# define verbose 0 +# endif +# define Assert(cond,msg) {if(!(cond)) z_error(msg);} +# define Trace(x) fprintf x +# define Tracev(x) {if (verbose) fprintf x ;} +# define Tracevv(x) {if (verbose>1) fprintf x ;} +# define Tracec(c,x) {if (verbose && (c)) fprintf x ;} +# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;} +#else +# define Assert(cond,msg) +# define Trace(x) +# define Tracev(x) +# define Tracevv(x) +# define Tracec(c,x) +# define Tracecv(c,x) +#endif + + +typedef uLong (*check_func) OF((uLong check, Bytef *buf, uInt len)); + +/* voidpf zcalloc OF((voidpf opaque, unsigned items, unsigned size)); */ +/* void zcfree OF((voidpf opaque, voidpf ptr)); */ + +#define ZALLOC(strm, items, size) \ + (*((strm)->zalloc))((strm)->opaque, (items), (size)) +#define ZFREE(strm, addr, size) \ + (*((strm)->zfree))((strm)->opaque, (voidpf)(addr), (size)) +#define TRY_FREE(s, p, n) {if (p) ZFREE(s, p, n);} + +/* deflate.h -- internal compression state + * Copyright (C) 1995 Jean-loup Gailly + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* WARNING: this file should *not* be used by applications. It is + part of the implementation of the compression library and is + subject to change. Applications should only use zlib.h. + */ + +/*+++++*/ +/* infblock.h -- header to use infblock.c + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* WARNING: this file should *not* be used by applications. It is + part of the implementation of the compression library and is + subject to change. Applications should only use zlib.h. + */ + +struct inflate_blocks_state; +typedef struct inflate_blocks_state FAR inflate_blocks_statef; + +local inflate_blocks_statef * inflate_blocks_new OF(( + z_stream *z, + check_func c, /* check function */ + uInt w)); /* window size */ + +local int inflate_blocks OF(( + inflate_blocks_statef *, + z_stream *, + int)); /* initial return code */ + +local void inflate_blocks_reset OF(( + inflate_blocks_statef *, + z_stream *, + uLongf *)); /* check value on output */ + +local int inflate_blocks_free OF(( + inflate_blocks_statef *, + z_stream *, + uLongf *)); /* check value on output */ + +local int inflate_addhistory OF(( + inflate_blocks_statef *, + z_stream *)); + +local int inflate_packet_flush OF(( + inflate_blocks_statef *)); + +/*+++++*/ +/* inftrees.h -- header to use inftrees.c + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* WARNING: this file should *not* be used by applications. It is + part of the implementation of the compression library and is + subject to change. Applications should only use zlib.h. + */ + +/* Huffman code lookup table entry--this entry is four bytes for machines + that have 16-bit pointers (e.g. PC's in the small or medium model). */ + +typedef struct inflate_huft_s FAR inflate_huft; + +struct inflate_huft_s { + union { + struct { + Byte Exop; /* number of extra bits or operation */ + Byte Bits; /* number of bits in this code or subcode */ + } what; + uInt Nalloc; /* number of these allocated here */ + Bytef *pad; /* pad structure to a power of 2 (4 bytes for */ + } word; /* 16-bit, 8 bytes for 32-bit machines) */ + union { + uInt Base; /* literal, length base, or distance base */ + inflate_huft *Next; /* pointer to next level of table */ + } more; +}; + +#ifdef DEBUG_ZLIB + local uInt inflate_hufts; +#endif + +local int inflate_trees_bits OF(( + uIntf *, /* 19 code lengths */ + uIntf *, /* bits tree desired/actual depth */ + inflate_huft * FAR *, /* bits tree result */ + z_stream *)); /* for zalloc, zfree functions */ + +local int inflate_trees_dynamic OF(( + uInt, /* number of literal/length codes */ + uInt, /* number of distance codes */ + uIntf *, /* that many (total) code lengths */ + uIntf *, /* literal desired/actual bit depth */ + uIntf *, /* distance desired/actual bit depth */ + inflate_huft * FAR *, /* literal/length tree result */ + inflate_huft * FAR *, /* distance tree result */ + z_stream *)); /* for zalloc, zfree functions */ + +local int inflate_trees_fixed OF(( + uIntf *, /* literal desired/actual bit depth */ + uIntf *, /* distance desired/actual bit depth */ + inflate_huft * FAR *, /* literal/length tree result */ + inflate_huft * FAR *)); /* distance tree result */ + +local int inflate_trees_free OF(( + inflate_huft *, /* tables to free */ + z_stream *)); /* for zfree function */ + + +/*+++++*/ +/* infcodes.h -- header to use infcodes.c + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* WARNING: this file should *not* be used by applications. It is + part of the implementation of the compression library and is + subject to change. Applications should only use zlib.h. + */ + +struct inflate_codes_state; +typedef struct inflate_codes_state FAR inflate_codes_statef; + +local inflate_codes_statef *inflate_codes_new OF(( + uInt, uInt, + inflate_huft *, inflate_huft *, + z_stream *)); + +local int inflate_codes OF(( + inflate_blocks_statef *, + z_stream *, + int)); + +local void inflate_codes_free OF(( + inflate_codes_statef *, + z_stream *)); + + +/*+++++*/ +/* inflate.c -- zlib interface to inflate modules + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* inflate private state */ +struct internal_state { + + /* mode */ + enum { + METHOD, /* waiting for method byte */ + FLAG, /* waiting for flag byte */ + BLOCKS, /* decompressing blocks */ + CHECK4, /* four check bytes to go */ + CHECK3, /* three check bytes to go */ + CHECK2, /* two check bytes to go */ + CHECK1, /* one check byte to go */ + DONE, /* finished check, done */ + BAD} /* got an error--stay here */ + mode; /* current inflate mode */ + + /* mode dependent information */ + union { + uInt method; /* if FLAGS, method byte */ + struct { + uLong was; /* computed check value */ + uLong need; /* stream check value */ + } check; /* if CHECK, check values to compare */ + uInt marker; /* if BAD, inflateSync's marker bytes count */ + } sub; /* submode */ + + /* mode independent information */ + int nowrap; /* flag for no wrapper */ + uInt wbits; /* log2(window size) (8..15, defaults to 15) */ + inflate_blocks_statef + *blocks; /* current inflate_blocks state */ + +}; + + +int inflateReset(z) +z_stream *z; +{ + uLong c; + + if (z == Z_NULL || z->state == Z_NULL) + return Z_STREAM_ERROR; + z->total_in = z->total_out = 0; + z->msg = Z_NULL; + z->state->mode = z->state->nowrap ? BLOCKS : METHOD; + inflate_blocks_reset(z->state->blocks, z, &c); + Trace((stderr, "inflate: reset\n")); + return Z_OK; +} + + +int inflateEnd(z) +z_stream *z; +{ + uLong c; + + if (z == Z_NULL || z->state == Z_NULL || z->zfree == Z_NULL) + return Z_STREAM_ERROR; + if (z->state->blocks != Z_NULL) + inflate_blocks_free(z->state->blocks, z, &c); + ZFREE(z, z->state, sizeof(struct internal_state)); + z->state = Z_NULL; + Trace((stderr, "inflate: end\n")); + return Z_OK; +} + + +int inflateInit2(z, w) +z_stream *z; +int w; +{ + /* initialize state */ + if (z == Z_NULL) + return Z_STREAM_ERROR; +/* if (z->zalloc == Z_NULL) z->zalloc = zcalloc; */ +/* if (z->zfree == Z_NULL) z->zfree = zcfree; */ + if ((z->state = (struct internal_state FAR *) + ZALLOC(z,1,sizeof(struct internal_state))) == Z_NULL) + return Z_MEM_ERROR; + z->state->blocks = Z_NULL; + + /* handle undocumented nowrap option (no zlib header or check) */ + z->state->nowrap = 0; + if (w < 0) + { + w = - w; + z->state->nowrap = 1; + } + + /* set window size */ + if (w < 8 || w > 15) + { + inflateEnd(z); + return Z_STREAM_ERROR; + } + z->state->wbits = (uInt)w; + + /* create inflate_blocks state */ + if ((z->state->blocks = + inflate_blocks_new(z, z->state->nowrap ? Z_NULL : adler32, 1 << w)) + == Z_NULL) + { + inflateEnd(z); + return Z_MEM_ERROR; + } + Trace((stderr, "inflate: allocated\n")); + + /* reset state */ + inflateReset(z); + return Z_OK; +} + + +int inflateInit(z) +z_stream *z; +{ + return inflateInit2(z, DEF_WBITS); +} + + +#define NEEDBYTE {if(z->avail_in==0)goto empty;r=Z_OK;} +#define NEXTBYTE (z->avail_in--,z->total_in++,*z->next_in++) + +int inflate(z, f) +z_stream *z; +int f; +{ + int r; + uInt b; + + if (z == Z_NULL || z->next_in == Z_NULL) + return Z_STREAM_ERROR; + r = Z_BUF_ERROR; + while (1) switch (z->state->mode) + { + case METHOD: + NEEDBYTE + if (((z->state->sub.method = NEXTBYTE) & 0xf) != DEFLATED) + { + z->state->mode = BAD; + z->msg = "unknown compression method"; + z->state->sub.marker = 5; /* can't try inflateSync */ + break; + } + if ((z->state->sub.method >> 4) + 8 > z->state->wbits) + { + z->state->mode = BAD; + z->msg = "invalid window size"; + z->state->sub.marker = 5; /* can't try inflateSync */ + break; + } + z->state->mode = FLAG; + case FLAG: + NEEDBYTE + if ((b = NEXTBYTE) & 0x20) + { + z->state->mode = BAD; + z->msg = "invalid reserved bit"; + z->state->sub.marker = 5; /* can't try inflateSync */ + break; + } + if (((z->state->sub.method << 8) + b) % 31) + { + z->state->mode = BAD; + z->msg = "incorrect header check"; + z->state->sub.marker = 5; /* can't try inflateSync */ + break; + } + Trace((stderr, "inflate: zlib header ok\n")); + z->state->mode = BLOCKS; + case BLOCKS: + r = inflate_blocks(z->state->blocks, z, r); + if (f == Z_PACKET_FLUSH && z->avail_in == 0 && z->avail_out != 0) + r = inflate_packet_flush(z->state->blocks); + if (r == Z_DATA_ERROR) + { + z->state->mode = BAD; + z->state->sub.marker = 0; /* can try inflateSync */ + break; + } + if (r != Z_STREAM_END) + return r; + r = Z_OK; + inflate_blocks_reset(z->state->blocks, z, &z->state->sub.check.was); + if (z->state->nowrap) + { + z->state->mode = DONE; + break; + } + z->state->mode = CHECK4; + case CHECK4: + NEEDBYTE + z->state->sub.check.need = (uLong)NEXTBYTE << 24; + z->state->mode = CHECK3; + case CHECK3: + NEEDBYTE + z->state->sub.check.need += (uLong)NEXTBYTE << 16; + z->state->mode = CHECK2; + case CHECK2: + NEEDBYTE + z->state->sub.check.need += (uLong)NEXTBYTE << 8; + z->state->mode = CHECK1; + case CHECK1: + NEEDBYTE + z->state->sub.check.need += (uLong)NEXTBYTE; + + if (z->state->sub.check.was != z->state->sub.check.need) + { + z->state->mode = BAD; + z->msg = "incorrect data check"; + z->state->sub.marker = 5; /* can't try inflateSync */ + break; + } + Trace((stderr, "inflate: zlib check ok\n")); + z->state->mode = DONE; + case DONE: + return Z_STREAM_END; + case BAD: + return Z_DATA_ERROR; + default: + return Z_STREAM_ERROR; + } + + empty: + if (f != Z_PACKET_FLUSH) + return r; + z->state->mode = BAD; + z->state->sub.marker = 0; /* can try inflateSync */ + return Z_DATA_ERROR; +} + +/* + * This subroutine adds the data at next_in/avail_in to the output history + * without performing any output. The output buffer must be "caught up"; + * i.e. no pending output (hence s->read equals s->write), and the state must + * be BLOCKS (i.e. we should be willing to see the start of a series of + * BLOCKS). On exit, the output will also be caught up, and the checksum + * will have been updated if need be. + */ + +int inflateIncomp(z) +z_stream *z; +{ + if (z->state->mode != BLOCKS) + return Z_DATA_ERROR; + return inflate_addhistory(z->state->blocks, z); +} + + +int inflateSync(z) +z_stream *z; +{ + uInt n; /* number of bytes to look at */ + Bytef *p; /* pointer to bytes */ + uInt m; /* number of marker bytes found in a row */ + uLong r, w; /* temporaries to save total_in and total_out */ + + /* set up */ + if (z == Z_NULL || z->state == Z_NULL) + return Z_STREAM_ERROR; + if (z->state->mode != BAD) + { + z->state->mode = BAD; + z->state->sub.marker = 0; + } + if ((n = z->avail_in) == 0) + return Z_BUF_ERROR; + p = z->next_in; + m = z->state->sub.marker; + + /* search */ + while (n && m < 4) + { + if (*p == (Byte)(m < 2 ? 0 : 0xff)) + m++; + else if (*p) + m = 0; + else + m = 4 - m; + p++, n--; + } + + /* restore */ + z->total_in += p - z->next_in; + z->next_in = p; + z->avail_in = n; + z->state->sub.marker = m; + + /* return no joy or set up to restart on a new block */ + if (m != 4) + return Z_DATA_ERROR; + r = z->total_in; w = z->total_out; + inflateReset(z); + z->total_in = r; z->total_out = w; + z->state->mode = BLOCKS; + return Z_OK; +} + +#undef NEEDBYTE +#undef NEXTBYTE + +/*+++++*/ +/* infutil.h -- types and macros common to blocks and codes + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* WARNING: this file should *not* be used by applications. It is + part of the implementation of the compression library and is + subject to change. Applications should only use zlib.h. + */ + +/* inflate blocks semi-private state */ +struct inflate_blocks_state { + + /* mode */ + enum { + TYPE, /* get type bits (3, including end bit) */ + LENS, /* get lengths for stored */ + STORED, /* processing stored block */ + TABLE, /* get table lengths */ + BTREE, /* get bit lengths tree for a dynamic block */ + DTREE, /* get length, distance trees for a dynamic block */ + CODES, /* processing fixed or dynamic block */ + DRY, /* output remaining window bytes */ + DONEB, /* finished last block, done */ + BADB} /* got a data error--stuck here */ + mode; /* current inflate_block mode */ + + /* mode dependent information */ + union { + uInt left; /* if STORED, bytes left to copy */ + struct { + uInt table; /* table lengths (14 bits) */ + uInt index; /* index into blens (or border) */ + uIntf *blens; /* bit lengths of codes */ + uInt bb; /* bit length tree depth */ + inflate_huft *tb; /* bit length decoding tree */ + int nblens; /* # elements allocated at blens */ + } trees; /* if DTREE, decoding info for trees */ + struct { + inflate_huft *tl, *td; /* trees to free */ + inflate_codes_statef + *codes; + } decode; /* if CODES, current state */ + } sub; /* submode */ + uInt last; /* true if this block is the last block */ + + /* mode independent information */ + uInt bitk; /* bits in bit buffer */ + uLong bitb; /* bit buffer */ + Bytef *window; /* sliding window */ + Bytef *end; /* one byte after sliding window */ + Bytef *read; /* window read pointer */ + Bytef *write; /* window write pointer */ + check_func checkfn; /* check function */ + uLong check; /* check on output */ + +}; + + +/* defines for inflate input/output */ +/* update pointers and return */ +#define UPDBITS {s->bitb=b;s->bitk=k;} +#define UPDIN {z->avail_in=n;z->total_in+=p-z->next_in;z->next_in=p;} +#define UPDOUT {s->write=q;} +#define UPDATE {UPDBITS UPDIN UPDOUT} +#define LEAVE {UPDATE return inflate_flush(s,z,r);} +/* get bytes and bits */ +#define LOADIN {p=z->next_in;n=z->avail_in;b=s->bitb;k=s->bitk;} +#define NEEDBYTE {if(n)r=Z_OK;else LEAVE} +#define NEXTBYTE (n--,*p++) +#define NEEDBITS(j) {while(k<(j)){NEEDBYTE;b|=((uLong)NEXTBYTE)<>=(j);k-=(j);} +/* output bytes */ +#define WAVAIL (qread?s->read-q-1:s->end-q) +#define LOADOUT {q=s->write;m=WAVAIL;} +#define WRAP {if(q==s->end&&s->read!=s->window){q=s->window;m=WAVAIL;}} +#define FLUSH {UPDOUT r=inflate_flush(s,z,r); LOADOUT} +#define NEEDOUT {if(m==0){WRAP if(m==0){FLUSH WRAP if(m==0) LEAVE}}r=Z_OK;} +#define OUTBYTE(a) {*q++=(Byte)(a);m--;} +/* load local pointers */ +#define LOAD {LOADIN LOADOUT} + +/* + * The IBM 150 firmware munges the data right after _etext[]. This + * protects it. -- Cort + */ +#if 0 +local uInt protect_mask[] = {0, 0, 0, 0, 0, 0, 0, 0, 0 ,0 ,0 ,0}; +#endif +/* And'ing with mask[n] masks the lower n bits */ +local uInt inflate_mask[] = { + 0x0000, + 0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff, + 0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff +}; + +/* copy as much as possible from the sliding window to the output area */ +local int inflate_flush OF(( + inflate_blocks_statef *, + z_stream *, + int)); + +/*+++++*/ +/* inffast.h -- header to use inffast.c + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* WARNING: this file should *not* be used by applications. It is + part of the implementation of the compression library and is + subject to change. Applications should only use zlib.h. + */ + +local int inflate_fast OF(( + uInt, + uInt, + inflate_huft *, + inflate_huft *, + inflate_blocks_statef *, + z_stream *)); + + +/*+++++*/ +/* infblock.c -- interpret and process block types to last block + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* Table for deflate from PKZIP's appnote.txt. */ +local uInt border[] = { /* Order of the bit length code lengths */ + 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15}; + +/* + Notes beyond the 1.93a appnote.txt: + + 1. Distance pointers never point before the beginning of the output + stream. + 2. Distance pointers can point back across blocks, up to 32k away. + 3. There is an implied maximum of 7 bits for the bit length table and + 15 bits for the actual data. + 4. If only one code exists, then it is encoded using one bit. (Zero + would be more efficient, but perhaps a little confusing.) If two + codes exist, they are coded using one bit each (0 and 1). + 5. There is no way of sending zero distance codes--a dummy must be + sent if there are none. (History: a pre 2.0 version of PKZIP would + store blocks with no distance codes, but this was discovered to be + too harsh a criterion.) Valid only for 1.93a. 2.04c does allow + zero distance codes, which is sent as one code of zero bits in + length. + 6. There are up to 286 literal/length codes. Code 256 represents the + end-of-block. Note however that the static length tree defines + 288 codes just to fill out the Huffman codes. Codes 286 and 287 + cannot be used though, since there is no length base or extra bits + defined for them. Similarily, there are up to 30 distance codes. + However, static trees define 32 codes (all 5 bits) to fill out the + Huffman codes, but the last two had better not show up in the data. + 7. Unzip can check dynamic Huffman blocks for complete code sets. + The exception is that a single code would not be complete (see #4). + 8. The five bits following the block type is really the number of + literal codes sent minus 257. + 9. Length codes 8,16,16 are interpreted as 13 length codes of 8 bits + (1+6+6). Therefore, to output three times the length, you output + three codes (1+1+1), whereas to output four times the same length, + you only need two codes (1+3). Hmm. + 10. In the tree reconstruction algorithm, Code = Code + Increment + only if BitLength(i) is not zero. (Pretty obvious.) + 11. Correction: 4 Bits: # of Bit Length codes - 4 (4 - 19) + 12. Note: length code 284 can represent 227-258, but length code 285 + really is 258. The last length deserves its own, short code + since it gets used a lot in very redundant files. The length + 258 is special since 258 - 3 (the min match length) is 255. + 13. The literal/length and distance code bit lengths are read as a + single stream of lengths. It is possible (and advantageous) for + a repeat code (16, 17, or 18) to go across the boundary between + the two sets of lengths. + */ + + +local void inflate_blocks_reset(s, z, c) +inflate_blocks_statef *s; +z_stream *z; +uLongf *c; +{ + if (s->checkfn != Z_NULL) + *c = s->check; + if (s->mode == BTREE || s->mode == DTREE) + ZFREE(z, s->sub.trees.blens, s->sub.trees.nblens * sizeof(uInt)); + if (s->mode == CODES) + { + inflate_codes_free(s->sub.decode.codes, z); + inflate_trees_free(s->sub.decode.td, z); + inflate_trees_free(s->sub.decode.tl, z); + } + s->mode = TYPE; + s->bitk = 0; + s->bitb = 0; + s->read = s->write = s->window; + if (s->checkfn != Z_NULL) + s->check = (*s->checkfn)(0L, Z_NULL, 0); + if (z->outcb != Z_NULL) + (*z->outcb)(Z_NULL, 0); + Trace((stderr, "inflate: blocks reset\n")); +} + + +local inflate_blocks_statef *inflate_blocks_new(z, c, w) +z_stream *z; +check_func c; +uInt w; +{ + inflate_blocks_statef *s; + + if ((s = (inflate_blocks_statef *)ZALLOC + (z,1,sizeof(struct inflate_blocks_state))) == Z_NULL) + return s; + if ((s->window = (Bytef *)ZALLOC(z, 1, w)) == Z_NULL) + { + ZFREE(z, s, sizeof(struct inflate_blocks_state)); + return Z_NULL; + } + s->end = s->window + w; + s->checkfn = c; + s->mode = TYPE; + Trace((stderr, "inflate: blocks allocated\n")); + inflate_blocks_reset(s, z, &s->check); + return s; +} + + +local int inflate_blocks(s, z, r) +inflate_blocks_statef *s; +z_stream *z; +int r; +{ + uInt t; /* temporary storage */ + uLong b; /* bit buffer */ + uInt k; /* bits in bit buffer */ + Bytef *p; /* input data pointer */ + uInt n; /* bytes available there */ + Bytef *q; /* output window write pointer */ + uInt m; /* bytes to end of window or read pointer */ + + /* copy input/output information to locals (UPDATE macro restores) */ + LOAD + + /* process input based on current state */ + while (1) switch (s->mode) + { + case TYPE: + NEEDBITS(3) + t = (uInt)b & 7; + s->last = t & 1; + switch (t >> 1) + { + case 0: /* stored */ + Trace((stderr, "inflate: stored block%s\n", + s->last ? " (last)" : "")); + DUMPBITS(3) + t = k & 7; /* go to byte boundary */ + DUMPBITS(t) + s->mode = LENS; /* get length of stored block */ + break; + case 1: /* fixed */ + Trace((stderr, "inflate: fixed codes block%s\n", + s->last ? " (last)" : "")); + { + uInt bl, bd; + inflate_huft *tl, *td; + + inflate_trees_fixed(&bl, &bd, &tl, &td); + s->sub.decode.codes = inflate_codes_new(bl, bd, tl, td, z); + if (s->sub.decode.codes == Z_NULL) + { + r = Z_MEM_ERROR; + LEAVE + } + s->sub.decode.tl = Z_NULL; /* don't try to free these */ + s->sub.decode.td = Z_NULL; + } + DUMPBITS(3) + s->mode = CODES; + break; + case 2: /* dynamic */ + Trace((stderr, "inflate: dynamic codes block%s\n", + s->last ? " (last)" : "")); + DUMPBITS(3) + s->mode = TABLE; + break; + case 3: /* illegal */ + DUMPBITS(3) + s->mode = BADB; + z->msg = "invalid block type"; + r = Z_DATA_ERROR; + LEAVE + } + break; + case LENS: + NEEDBITS(32) + if (((~b) >> 16) != (b & 0xffff)) + { + s->mode = BADB; + z->msg = "invalid stored block lengths"; + r = Z_DATA_ERROR; + LEAVE + } + s->sub.left = (uInt)b & 0xffff; + b = k = 0; /* dump bits */ + Tracev((stderr, "inflate: stored length %u\n", s->sub.left)); + s->mode = s->sub.left ? STORED : TYPE; + break; + case STORED: + if (n == 0) + LEAVE + NEEDOUT + t = s->sub.left; + if (t > n) t = n; + if (t > m) t = m; + zmemcpy(q, p, t); + p += t; n -= t; + q += t; m -= t; + if ((s->sub.left -= t) != 0) + break; + Tracev((stderr, "inflate: stored end, %lu total out\n", + z->total_out + (q >= s->read ? q - s->read : + (s->end - s->read) + (q - s->window)))); + s->mode = s->last ? DRY : TYPE; + break; + case TABLE: + NEEDBITS(14) + s->sub.trees.table = t = (uInt)b & 0x3fff; +#ifndef PKZIP_BUG_WORKAROUND + if ((t & 0x1f) > 29 || ((t >> 5) & 0x1f) > 29) + { + s->mode = BADB; + z->msg = "too many length or distance symbols"; + r = Z_DATA_ERROR; + LEAVE + } +#endif + t = 258 + (t & 0x1f) + ((t >> 5) & 0x1f); + if (t < 19) + t = 19; + if ((s->sub.trees.blens = (uIntf*)ZALLOC(z, t, sizeof(uInt))) == Z_NULL) + { + r = Z_MEM_ERROR; + LEAVE + } + s->sub.trees.nblens = t; + DUMPBITS(14) + s->sub.trees.index = 0; + Tracev((stderr, "inflate: table sizes ok\n")); + s->mode = BTREE; + case BTREE: + while (s->sub.trees.index < 4 + (s->sub.trees.table >> 10)) + { + NEEDBITS(3) + s->sub.trees.blens[border[s->sub.trees.index++]] = (uInt)b & 7; + DUMPBITS(3) + } + while (s->sub.trees.index < 19) + s->sub.trees.blens[border[s->sub.trees.index++]] = 0; + s->sub.trees.bb = 7; + t = inflate_trees_bits(s->sub.trees.blens, &s->sub.trees.bb, + &s->sub.trees.tb, z); + if (t != Z_OK) + { + r = t; + if (r == Z_DATA_ERROR) + s->mode = BADB; + LEAVE + } + s->sub.trees.index = 0; + Tracev((stderr, "inflate: bits tree ok\n")); + s->mode = DTREE; + case DTREE: + while (t = s->sub.trees.table, + s->sub.trees.index < 258 + (t & 0x1f) + ((t >> 5) & 0x1f)) + { + inflate_huft *h; + uInt i, j, c; + + t = s->sub.trees.bb; + NEEDBITS(t) + h = s->sub.trees.tb + ((uInt)b & inflate_mask[t]); + t = h->word.what.Bits; + c = h->more.Base; + if (c < 16) + { + DUMPBITS(t) + s->sub.trees.blens[s->sub.trees.index++] = c; + } + else /* c == 16..18 */ + { + i = c == 18 ? 7 : c - 14; + j = c == 18 ? 11 : 3; + NEEDBITS(t + i) + DUMPBITS(t) + j += (uInt)b & inflate_mask[i]; + DUMPBITS(i) + i = s->sub.trees.index; + t = s->sub.trees.table; + if (i + j > 258 + (t & 0x1f) + ((t >> 5) & 0x1f) || + (c == 16 && i < 1)) + { + s->mode = BADB; + z->msg = "invalid bit length repeat"; + r = Z_DATA_ERROR; + LEAVE + } + c = c == 16 ? s->sub.trees.blens[i - 1] : 0; + do { + s->sub.trees.blens[i++] = c; + } while (--j); + s->sub.trees.index = i; + } + } + inflate_trees_free(s->sub.trees.tb, z); + s->sub.trees.tb = Z_NULL; + { + uInt bl, bd; + inflate_huft *tl, *td; + inflate_codes_statef *c; + + bl = 9; /* must be <= 9 for lookahead assumptions */ + bd = 6; /* must be <= 9 for lookahead assumptions */ + t = s->sub.trees.table; + t = inflate_trees_dynamic(257 + (t & 0x1f), 1 + ((t >> 5) & 0x1f), + s->sub.trees.blens, &bl, &bd, &tl, &td, z); + if (t != Z_OK) + { + if (t == (uInt)Z_DATA_ERROR) + s->mode = BADB; + r = t; + LEAVE + } + Tracev((stderr, "inflate: trees ok\n")); + if ((c = inflate_codes_new(bl, bd, tl, td, z)) == Z_NULL) + { + inflate_trees_free(td, z); + inflate_trees_free(tl, z); + r = Z_MEM_ERROR; + LEAVE + } + ZFREE(z, s->sub.trees.blens, s->sub.trees.nblens * sizeof(uInt)); + s->sub.decode.codes = c; + s->sub.decode.tl = tl; + s->sub.decode.td = td; + } + s->mode = CODES; + case CODES: + UPDATE + if ((r = inflate_codes(s, z, r)) != Z_STREAM_END) + return inflate_flush(s, z, r); + r = Z_OK; + inflate_codes_free(s->sub.decode.codes, z); + inflate_trees_free(s->sub.decode.td, z); + inflate_trees_free(s->sub.decode.tl, z); + LOAD + Tracev((stderr, "inflate: codes end, %lu total out\n", + z->total_out + (q >= s->read ? q - s->read : + (s->end - s->read) + (q - s->window)))); + if (!s->last) + { + s->mode = TYPE; + break; + } + if (k > 7) /* return unused byte, if any */ + { + Assert(k < 16, "inflate_codes grabbed too many bytes") + k -= 8; + n++; + p--; /* can always return one */ + } + s->mode = DRY; + case DRY: + FLUSH + if (s->read != s->write) + LEAVE + s->mode = DONEB; + case DONEB: + r = Z_STREAM_END; + LEAVE + case BADB: + r = Z_DATA_ERROR; + LEAVE + default: + r = Z_STREAM_ERROR; + LEAVE + } +} + + +local int inflate_blocks_free(s, z, c) +inflate_blocks_statef *s; +z_stream *z; +uLongf *c; +{ + inflate_blocks_reset(s, z, c); + ZFREE(z, s->window, s->end - s->window); + ZFREE(z, s, sizeof(struct inflate_blocks_state)); + Trace((stderr, "inflate: blocks freed\n")); + return Z_OK; +} + +/* + * This subroutine adds the data at next_in/avail_in to the output history + * without performing any output. The output buffer must be "caught up"; + * i.e. no pending output (hence s->read equals s->write), and the state must + * be BLOCKS (i.e. we should be willing to see the start of a series of + * BLOCKS). On exit, the output will also be caught up, and the checksum + * will have been updated if need be. + */ +local int inflate_addhistory(s, z) +inflate_blocks_statef *s; +z_stream *z; +{ + uLong b; /* bit buffer */ /* NOT USED HERE */ + uInt k; /* bits in bit buffer */ /* NOT USED HERE */ + uInt t; /* temporary storage */ + Bytef *p; /* input data pointer */ + uInt n; /* bytes available there */ + Bytef *q; /* output window write pointer */ + uInt m; /* bytes to end of window or read pointer */ + + if (s->read != s->write) + return Z_STREAM_ERROR; + if (s->mode != TYPE) + return Z_DATA_ERROR; + + /* we're ready to rock */ + LOAD + /* while there is input ready, copy to output buffer, moving + * pointers as needed. + */ + while (n) { + t = n; /* how many to do */ + /* is there room until end of buffer? */ + if (t > m) t = m; + /* update check information */ + if (s->checkfn != Z_NULL) + s->check = (*s->checkfn)(s->check, q, t); + /* output callback */ + if (z->outcb != Z_NULL) + (*z->outcb)(q, t); + zmemcpy(q, p, t); + q += t; + p += t; + n -= t; + z->total_out += t; + s->read = q; /* drag read pointer forward */ +/* WRAP */ /* expand WRAP macro by hand to handle s->read */ + if (q == s->end) { + s->read = q = s->window; + m = WAVAIL; + } + } + UPDATE + return Z_OK; +} + + +/* + * At the end of a Deflate-compressed PPP packet, we expect to have seen + * a `stored' block type value but not the (zero) length bytes. + */ +local int inflate_packet_flush(s) + inflate_blocks_statef *s; +{ + if (s->mode != LENS) + return Z_DATA_ERROR; + s->mode = TYPE; + return Z_OK; +} + + +/*+++++*/ +/* inftrees.c -- generate Huffman trees for efficient decoding + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* simplify the use of the inflate_huft type with some defines */ +#define base more.Base +#define next more.Next +#define exop word.what.Exop +#define bits word.what.Bits + + +local int huft_build OF(( + uIntf *, /* code lengths in bits */ + uInt, /* number of codes */ + uInt, /* number of "simple" codes */ + uIntf *, /* list of base values for non-simple codes */ + uIntf *, /* list of extra bits for non-simple codes */ + inflate_huft * FAR*,/* result: starting table */ + uIntf *, /* maximum lookup bits (returns actual) */ + z_stream *)); /* for zalloc function */ + +local voidpf falloc OF(( + voidpf, /* opaque pointer (not used) */ + uInt, /* number of items */ + uInt)); /* size of item */ + +local void ffree OF(( + voidpf q, /* opaque pointer (not used) */ + voidpf p, /* what to free (not used) */ + uInt n)); /* number of bytes (not used) */ + +/* Tables for deflate from PKZIP's appnote.txt. */ +local uInt cplens[] = { /* Copy lengths for literal codes 257..285 */ + 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31, + 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0}; + /* actually lengths - 2; also see note #13 above about 258 */ +local uInt cplext[] = { /* Extra bits for literal codes 257..285 */ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, + 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0, 192, 192}; /* 192==invalid */ +local uInt cpdist[] = { /* Copy offsets for distance codes 0..29 */ + 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193, + 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145, + 8193, 12289, 16385, 24577}; +local uInt cpdext[] = { /* Extra bits for distance codes */ + 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, + 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, + 12, 12, 13, 13}; + +/* + Huffman code decoding is performed using a multi-level table lookup. + The fastest way to decode is to simply build a lookup table whose + size is determined by the longest code. However, the time it takes + to build this table can also be a factor if the data being decoded + is not very long. The most common codes are necessarily the + shortest codes, so those codes dominate the decoding time, and hence + the speed. The idea is you can have a shorter table that decodes the + shorter, more probable codes, and then point to subsidiary tables for + the longer codes. The time it costs to decode the longer codes is + then traded against the time it takes to make longer tables. + + This results of this trade are in the variables lbits and dbits + below. lbits is the number of bits the first level table for literal/ + length codes can decode in one step, and dbits is the same thing for + the distance codes. Subsequent tables are also less than or equal to + those sizes. These values may be adjusted either when all of the + codes are shorter than that, in which case the longest code length in + bits is used, or when the shortest code is *longer* than the requested + table size, in which case the length of the shortest code in bits is + used. + + There are two different values for the two tables, since they code a + different number of possibilities each. The literal/length table + codes 286 possible values, or in a flat code, a little over eight + bits. The distance table codes 30 possible values, or a little less + than five bits, flat. The optimum values for speed end up being + about one bit more than those, so lbits is 8+1 and dbits is 5+1. + The optimum values may differ though from machine to machine, and + possibly even between compilers. Your mileage may vary. + */ + + +/* If BMAX needs to be larger than 16, then h and x[] should be uLong. */ +#define BMAX 15 /* maximum bit length of any code */ +#define N_MAX 288 /* maximum number of codes in any set */ + +#ifdef DEBUG_ZLIB + uInt inflate_hufts; +#endif + +local int huft_build(b, n, s, d, e, t, m, zs) +uIntf *b; /* code lengths in bits (all assumed <= BMAX) */ +uInt n; /* number of codes (assumed <= N_MAX) */ +uInt s; /* number of simple-valued codes (0..s-1) */ +uIntf *d; /* list of base values for non-simple codes */ +uIntf *e; /* list of extra bits for non-simple codes */ +inflate_huft * FAR *t; /* result: starting table */ +uIntf *m; /* maximum lookup bits, returns actual */ +z_stream *zs; /* for zalloc function */ +/* Given a list of code lengths and a maximum table size, make a set of + tables to decode that set of codes. Return Z_OK on success, Z_BUF_ERROR + if the given code set is incomplete (the tables are still built in this + case), Z_DATA_ERROR if the input is invalid (all zero length codes or an + over-subscribed set of lengths), or Z_MEM_ERROR if not enough memory. */ +{ + + uInt a; /* counter for codes of length k */ + uInt c[BMAX+1]; /* bit length count table */ + uInt f; /* i repeats in table every f entries */ + int g; /* maximum code length */ + int h; /* table level */ + register uInt i; /* counter, current code */ + register uInt j; /* counter */ + register int k; /* number of bits in current code */ + int l; /* bits per table (returned in m) */ + register uIntf *p; /* pointer into c[], b[], or v[] */ + inflate_huft *q; /* points to current table */ + struct inflate_huft_s r; /* table entry for structure assignment */ + inflate_huft *u[BMAX]; /* table stack */ + uInt v[N_MAX]; /* values in order of bit length */ + register int w; /* bits before this table == (l * h) */ + uInt x[BMAX+1]; /* bit offsets, then code stack */ + uIntf *xp; /* pointer into x */ + int y; /* number of dummy codes added */ + uInt z; /* number of entries in current table */ + + + /* Generate counts for each bit length */ + p = c; +#define C0 *p++ = 0; +#define C2 C0 C0 C0 C0 +#define C4 C2 C2 C2 C2 + C4 /* clear c[]--assume BMAX+1 is 16 */ + p = b; i = n; + do { + c[*p++]++; /* assume all entries <= BMAX */ + } while (--i); + if (c[0] == n) /* null input--all zero length codes */ + { + *t = (inflate_huft *)Z_NULL; + *m = 0; + return Z_OK; + } + + + /* Find minimum and maximum length, bound *m by those */ + l = *m; + for (j = 1; j <= BMAX; j++) + if (c[j]) + break; + k = j; /* minimum code length */ + if ((uInt)l < j) + l = j; + for (i = BMAX; i; i--) + if (c[i]) + break; + g = i; /* maximum code length */ + if ((uInt)l > i) + l = i; + *m = l; + + + /* Adjust last length count to fill out codes, if needed */ + for (y = 1 << j; j < i; j++, y <<= 1) + if ((y -= c[j]) < 0) + return Z_DATA_ERROR; + if ((y -= c[i]) < 0) + return Z_DATA_ERROR; + c[i] += y; + + + /* Generate starting offsets into the value table for each length */ + x[1] = j = 0; + p = c + 1; xp = x + 2; + while (--i) { /* note that i == g from above */ + *xp++ = (j += *p++); + } + + + /* Make a table of values in order of bit lengths */ + p = b; i = 0; + do { + if ((j = *p++) != 0) + v[x[j]++] = i; + } while (++i < n); + + + /* Generate the Huffman codes and for each, make the table entries */ + x[0] = i = 0; /* first Huffman code is zero */ + p = v; /* grab values in bit order */ + h = -1; /* no tables yet--level -1 */ + w = -l; /* bits decoded == (l * h) */ + u[0] = (inflate_huft *)Z_NULL; /* just to keep compilers happy */ + q = (inflate_huft *)Z_NULL; /* ditto */ + z = 0; /* ditto */ + + /* go through the bit lengths (k already is bits in shortest code) */ + for (; k <= g; k++) + { + a = c[k]; + while (a--) + { + /* here i is the Huffman code of length k bits for value *p */ + /* make tables up to required level */ + while (k > w + l) + { + h++; + w += l; /* previous table always l bits */ + + /* compute minimum size table less than or equal to l bits */ + z = (z = g - w) > (uInt)l ? l : z; /* table size upper limit */ + if ((f = 1 << (j = k - w)) > a + 1) /* try a k-w bit table */ + { /* too few codes for k-w bit table */ + f -= a + 1; /* deduct codes from patterns left */ + xp = c + k; + if (j < z) + while (++j < z) /* try smaller tables up to z bits */ + { + if ((f <<= 1) <= *++xp) + break; /* enough codes to use up j bits */ + f -= *xp; /* else deduct codes from patterns */ + } + } + z = 1 << j; /* table entries for j-bit table */ + + /* allocate and link in new table */ + if ((q = (inflate_huft *)ZALLOC + (zs,z + 1,sizeof(inflate_huft))) == Z_NULL) + { + if (h) + inflate_trees_free(u[0], zs); + return Z_MEM_ERROR; /* not enough memory */ + } + q->word.Nalloc = z + 1; +#ifdef DEBUG_ZLIB + inflate_hufts += z + 1; +#endif + *t = q + 1; /* link to list for huft_free() */ + *(t = &(q->next)) = Z_NULL; + u[h] = ++q; /* table starts after link */ + + /* connect to last table, if there is one */ + if (h) + { + x[h] = i; /* save pattern for backing up */ + r.bits = (Byte)l; /* bits to dump before this table */ + r.exop = (Byte)j; /* bits in this table */ + r.next = q; /* pointer to this table */ + j = i >> (w - l); /* (get around Turbo C bug) */ + u[h-1][j] = r; /* connect to last table */ + } + } + + /* set up table entry in r */ + r.bits = (Byte)(k - w); + if (p >= v + n) + r.exop = 128 + 64; /* out of values--invalid code */ + else if (*p < s) + { + r.exop = (Byte)(*p < 256 ? 0 : 32 + 64); /* 256 is end-of-block */ + r.base = *p++; /* simple code is just the value */ + } + else + { + r.exop = (Byte)e[*p - s] + 16 + 64; /* non-simple--look up in lists */ + r.base = d[*p++ - s]; + } + + /* fill code-like entries with r */ + f = 1 << (k - w); + for (j = i >> w; j < z; j += f) + q[j] = r; + + /* backwards increment the k-bit code i */ + for (j = 1 << (k - 1); i & j; j >>= 1) + i ^= j; + i ^= j; + + /* backup over finished tables */ + while ((i & ((1 << w) - 1)) != x[h]) + { + h--; /* don't need to update q */ + w -= l; + } + } + } + + + /* Return Z_BUF_ERROR if we were given an incomplete table */ + return y != 0 && g != 1 ? Z_BUF_ERROR : Z_OK; +} + + +local int inflate_trees_bits(c, bb, tb, z) +uIntf *c; /* 19 code lengths */ +uIntf *bb; /* bits tree desired/actual depth */ +inflate_huft * FAR *tb; /* bits tree result */ +z_stream *z; /* for zfree function */ +{ + int r; + + r = huft_build(c, 19, 19, (uIntf*)Z_NULL, (uIntf*)Z_NULL, tb, bb, z); + if (r == Z_DATA_ERROR) + z->msg = "oversubscribed dynamic bit lengths tree"; + else if (r == Z_BUF_ERROR) + { + inflate_trees_free(*tb, z); + z->msg = "incomplete dynamic bit lengths tree"; + r = Z_DATA_ERROR; + } + return r; +} + + +local int inflate_trees_dynamic(nl, nd, c, bl, bd, tl, td, z) +uInt nl; /* number of literal/length codes */ +uInt nd; /* number of distance codes */ +uIntf *c; /* that many (total) code lengths */ +uIntf *bl; /* literal desired/actual bit depth */ +uIntf *bd; /* distance desired/actual bit depth */ +inflate_huft * FAR *tl; /* literal/length tree result */ +inflate_huft * FAR *td; /* distance tree result */ +z_stream *z; /* for zfree function */ +{ + int r; + + /* build literal/length tree */ + if ((r = huft_build(c, nl, 257, cplens, cplext, tl, bl, z)) != Z_OK) + { + if (r == Z_DATA_ERROR) + z->msg = "oversubscribed literal/length tree"; + else if (r == Z_BUF_ERROR) + { + inflate_trees_free(*tl, z); + z->msg = "incomplete literal/length tree"; + r = Z_DATA_ERROR; + } + return r; + } + + /* build distance tree */ + if ((r = huft_build(c + nl, nd, 0, cpdist, cpdext, td, bd, z)) != Z_OK) + { + if (r == Z_DATA_ERROR) + z->msg = "oversubscribed literal/length tree"; + else if (r == Z_BUF_ERROR) { +#ifdef PKZIP_BUG_WORKAROUND + r = Z_OK; + } +#else + inflate_trees_free(*td, z); + z->msg = "incomplete literal/length tree"; + r = Z_DATA_ERROR; + } + inflate_trees_free(*tl, z); + return r; +#endif + } + + /* done */ + return Z_OK; +} + + +/* build fixed tables only once--keep them here */ +local int fixed_lock = 0; +local int fixed_built = 0; +#define FIXEDH 530 /* number of hufts used by fixed tables */ +local uInt fixed_left = FIXEDH; +local inflate_huft fixed_mem[FIXEDH]; +local uInt fixed_bl; +local uInt fixed_bd; +local inflate_huft *fixed_tl; +local inflate_huft *fixed_td; + + +local voidpf falloc(q, n, s) +voidpf q; /* opaque pointer (not used) */ +uInt n; /* number of items */ +uInt s; /* size of item */ +{ + Assert(s == sizeof(inflate_huft) && n <= fixed_left, + "inflate_trees falloc overflow"); + if (q) s++; /* to make some compilers happy */ + fixed_left -= n; + return (voidpf)(fixed_mem + fixed_left); +} + + +local void ffree(q, p, n) +voidpf q; +voidpf p; +uInt n; +{ + Assert(0, "inflate_trees ffree called!"); + if (q) q = p; /* to make some compilers happy */ +} + + +local int inflate_trees_fixed(bl, bd, tl, td) +uIntf *bl; /* literal desired/actual bit depth */ +uIntf *bd; /* distance desired/actual bit depth */ +inflate_huft * FAR *tl; /* literal/length tree result */ +inflate_huft * FAR *td; /* distance tree result */ +{ + /* build fixed tables if not built already--lock out other instances */ + while (++fixed_lock > 1) + fixed_lock--; + if (!fixed_built) + { + int k; /* temporary variable */ + unsigned c[288]; /* length list for huft_build */ + z_stream z; /* for falloc function */ + + /* set up fake z_stream for memory routines */ + z.zalloc = falloc; + z.zfree = ffree; + z.opaque = Z_NULL; + + /* literal table */ + for (k = 0; k < 144; k++) + c[k] = 8; + for (; k < 256; k++) + c[k] = 9; + for (; k < 280; k++) + c[k] = 7; + for (; k < 288; k++) + c[k] = 8; + fixed_bl = 7; + huft_build(c, 288, 257, cplens, cplext, &fixed_tl, &fixed_bl, &z); + + /* distance table */ + for (k = 0; k < 30; k++) + c[k] = 5; + fixed_bd = 5; + huft_build(c, 30, 0, cpdist, cpdext, &fixed_td, &fixed_bd, &z); + + /* done */ + fixed_built = 1; + } + fixed_lock--; + *bl = fixed_bl; + *bd = fixed_bd; + *tl = fixed_tl; + *td = fixed_td; + return Z_OK; +} + + +local int inflate_trees_free(t, z) +inflate_huft *t; /* table to free */ +z_stream *z; /* for zfree function */ +/* Free the malloc'ed tables built by huft_build(), which makes a linked + list of the tables it made, with the links in a dummy first entry of + each table. */ +{ + register inflate_huft *p, *q; + + /* Go through linked list, freeing from the malloced (t[-1]) address. */ + p = t; + while (p != Z_NULL) + { + q = (--p)->next; + ZFREE(z, p, p->word.Nalloc * sizeof(inflate_huft)); + p = q; + } + return Z_OK; +} + +/*+++++*/ +/* infcodes.c -- process literals and length/distance pairs + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* simplify the use of the inflate_huft type with some defines */ +#define base more.Base +#define next more.Next +#define exop word.what.Exop +#define bits word.what.Bits + +/* inflate codes private state */ +struct inflate_codes_state { + + /* mode */ + enum { /* waiting for "i:"=input, "o:"=output, "x:"=nothing */ + START, /* x: set up for LEN */ + LEN, /* i: get length/literal/eob next */ + LENEXT, /* i: getting length extra (have base) */ + DIST, /* i: get distance next */ + DISTEXT, /* i: getting distance extra */ + COPY, /* o: copying bytes in window, waiting for space */ + LIT, /* o: got literal, waiting for output space */ + WASH, /* o: got eob, possibly still output waiting */ + END, /* x: got eob and all data flushed */ + BADCODE} /* x: got error */ + mode; /* current inflate_codes mode */ + + /* mode dependent information */ + uInt len; + union { + struct { + inflate_huft *tree; /* pointer into tree */ + uInt need; /* bits needed */ + } code; /* if LEN or DIST, where in tree */ + uInt lit; /* if LIT, literal */ + struct { + uInt get; /* bits to get for extra */ + uInt dist; /* distance back to copy from */ + } copy; /* if EXT or COPY, where and how much */ + } sub; /* submode */ + + /* mode independent information */ + Byte lbits; /* ltree bits decoded per branch */ + Byte dbits; /* dtree bits decoder per branch */ + inflate_huft *ltree; /* literal/length/eob tree */ + inflate_huft *dtree; /* distance tree */ + +}; + + +local inflate_codes_statef *inflate_codes_new(bl, bd, tl, td, z) +uInt bl, bd; +inflate_huft *tl, *td; +z_stream *z; +{ + inflate_codes_statef *c; + + if ((c = (inflate_codes_statef *) + ZALLOC(z,1,sizeof(struct inflate_codes_state))) != Z_NULL) + { + c->mode = START; + c->lbits = (Byte)bl; + c->dbits = (Byte)bd; + c->ltree = tl; + c->dtree = td; + Tracev((stderr, "inflate: codes new\n")); + } + return c; +} + + +local int inflate_codes(s, z, r) +inflate_blocks_statef *s; +z_stream *z; +int r; +{ + uInt j; /* temporary storage */ + inflate_huft *t; /* temporary pointer */ + uInt e; /* extra bits or operation */ + uLong b; /* bit buffer */ + uInt k; /* bits in bit buffer */ + Bytef *p; /* input data pointer */ + uInt n; /* bytes available there */ + Bytef *q; /* output window write pointer */ + uInt m; /* bytes to end of window or read pointer */ + Bytef *f; /* pointer to copy strings from */ + inflate_codes_statef *c = s->sub.decode.codes; /* codes state */ + + /* copy input/output information to locals (UPDATE macro restores) */ + LOAD + + /* process input and output based on current state */ + while (1) switch (c->mode) + { /* waiting for "i:"=input, "o:"=output, "x:"=nothing */ + case START: /* x: set up for LEN */ +#ifndef SLOW + if (m >= 258 && n >= 10) + { + UPDATE + r = inflate_fast(c->lbits, c->dbits, c->ltree, c->dtree, s, z); + LOAD + if (r != Z_OK) + { + c->mode = r == Z_STREAM_END ? WASH : BADCODE; + break; + } + } +#endif /* !SLOW */ + c->sub.code.need = c->lbits; + c->sub.code.tree = c->ltree; + c->mode = LEN; + case LEN: /* i: get length/literal/eob next */ + j = c->sub.code.need; + NEEDBITS(j) + t = c->sub.code.tree + ((uInt)b & inflate_mask[j]); + DUMPBITS(t->bits) + e = (uInt)(t->exop); + if (e == 0) /* literal */ + { + c->sub.lit = t->base; + Tracevv((stderr, t->base >= 0x20 && t->base < 0x7f ? + "inflate: literal '%c'\n" : + "inflate: literal 0x%02x\n", t->base)); + c->mode = LIT; + break; + } + if (e & 16) /* length */ + { + c->sub.copy.get = e & 15; + c->len = t->base; + c->mode = LENEXT; + break; + } + if ((e & 64) == 0) /* next table */ + { + c->sub.code.need = e; + c->sub.code.tree = t->next; + break; + } + if (e & 32) /* end of block */ + { + Tracevv((stderr, "inflate: end of block\n")); + c->mode = WASH; + break; + } + c->mode = BADCODE; /* invalid code */ + z->msg = "invalid literal/length code"; + r = Z_DATA_ERROR; + LEAVE + case LENEXT: /* i: getting length extra (have base) */ + j = c->sub.copy.get; + NEEDBITS(j) + c->len += (uInt)b & inflate_mask[j]; + DUMPBITS(j) + c->sub.code.need = c->dbits; + c->sub.code.tree = c->dtree; + Tracevv((stderr, "inflate: length %u\n", c->len)); + c->mode = DIST; + case DIST: /* i: get distance next */ + j = c->sub.code.need; + NEEDBITS(j) + t = c->sub.code.tree + ((uInt)b & inflate_mask[j]); + DUMPBITS(t->bits) + e = (uInt)(t->exop); + if (e & 16) /* distance */ + { + c->sub.copy.get = e & 15; + c->sub.copy.dist = t->base; + c->mode = DISTEXT; + break; + } + if ((e & 64) == 0) /* next table */ + { + c->sub.code.need = e; + c->sub.code.tree = t->next; + break; + } + c->mode = BADCODE; /* invalid code */ + z->msg = "invalid distance code"; + r = Z_DATA_ERROR; + LEAVE + case DISTEXT: /* i: getting distance extra */ + j = c->sub.copy.get; + NEEDBITS(j) + c->sub.copy.dist += (uInt)b & inflate_mask[j]; + DUMPBITS(j) + Tracevv((stderr, "inflate: distance %u\n", c->sub.copy.dist)); + c->mode = COPY; + case COPY: /* o: copying bytes in window, waiting for space */ +#ifndef __TURBOC__ /* Turbo C bug for following expression */ + f = (uInt)(q - s->window) < c->sub.copy.dist ? + s->end - (c->sub.copy.dist - (q - s->window)) : + q - c->sub.copy.dist; +#else + f = q - c->sub.copy.dist; + if ((uInt)(q - s->window) < c->sub.copy.dist) + f = s->end - (c->sub.copy.dist - (q - s->window)); +#endif + while (c->len) + { + NEEDOUT + OUTBYTE(*f++) + if (f == s->end) + f = s->window; + c->len--; + } + c->mode = START; + break; + case LIT: /* o: got literal, waiting for output space */ + NEEDOUT + OUTBYTE(c->sub.lit) + c->mode = START; + break; + case WASH: /* o: got eob, possibly more output */ + FLUSH + if (s->read != s->write) + LEAVE + c->mode = END; + case END: + r = Z_STREAM_END; + LEAVE + case BADCODE: /* x: got error */ + r = Z_DATA_ERROR; + LEAVE + default: + r = Z_STREAM_ERROR; + LEAVE + } +} + + +local void inflate_codes_free(c, z) +inflate_codes_statef *c; +z_stream *z; +{ + ZFREE(z, c, sizeof(struct inflate_codes_state)); + Tracev((stderr, "inflate: codes free\n")); +} + +/*+++++*/ +/* inflate_util.c -- data and routines common to blocks and codes + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* copy as much as possible from the sliding window to the output area */ +local int inflate_flush(s, z, r) +inflate_blocks_statef *s; +z_stream *z; +int r; +{ + uInt n; + Bytef *p, *q; + + /* local copies of source and destination pointers */ + p = z->next_out; + q = s->read; + + /* compute number of bytes to copy as far as end of window */ + n = (uInt)((q <= s->write ? s->write : s->end) - q); + if (n > z->avail_out) n = z->avail_out; + if (n && r == Z_BUF_ERROR) r = Z_OK; + + /* update counters */ + z->avail_out -= n; + z->total_out += n; + + /* update check information */ + if (s->checkfn != Z_NULL) + s->check = (*s->checkfn)(s->check, q, n); + + /* output callback */ + if (z->outcb != Z_NULL) + (*z->outcb)(q, n); + + /* copy as far as end of window */ + zmemcpy(p, q, n); + p += n; + q += n; + + /* see if more to copy at beginning of window */ + if (q == s->end) + { + /* wrap pointers */ + q = s->window; + if (s->write == s->end) + s->write = s->window; + + /* compute bytes to copy */ + n = (uInt)(s->write - q); + if (n > z->avail_out) n = z->avail_out; + if (n && r == Z_BUF_ERROR) r = Z_OK; + + /* update counters */ + z->avail_out -= n; + z->total_out += n; + + /* update check information */ + if (s->checkfn != Z_NULL) + s->check = (*s->checkfn)(s->check, q, n); + + /* output callback */ + if (z->outcb != Z_NULL) + (*z->outcb)(q, n); + + /* copy */ + zmemcpy(p, q, n); + p += n; + q += n; + } + + /* update pointers */ + z->next_out = p; + s->read = q; + + /* done */ + return r; +} + + +/*+++++*/ +/* inffast.c -- process literals and length/distance pairs fast + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* simplify the use of the inflate_huft type with some defines */ +#define base more.Base +#define next more.Next +#define exop word.what.Exop +#define bits word.what.Bits + +/* macros for bit input with no checking and for returning unused bytes */ +#define GRABBITS(j) {while(k<(j)){b|=((uLong)NEXTBYTE)<>3);p-=c;k&=7;} + +/* Called with number of bytes left to write in window at least 258 + (the maximum string length) and number of input bytes available + at least ten. The ten bytes are six bytes for the longest length/ + distance pair plus four bytes for overloading the bit buffer. */ + +local int inflate_fast(bl, bd, tl, td, s, z) +uInt bl, bd; +inflate_huft *tl, *td; +inflate_blocks_statef *s; +z_stream *z; +{ + inflate_huft *t; /* temporary pointer */ + uInt e; /* extra bits or operation */ + uLong b; /* bit buffer */ + uInt k; /* bits in bit buffer */ + Bytef *p; /* input data pointer */ + uInt n; /* bytes available there */ + Bytef *q; /* output window write pointer */ + uInt m; /* bytes to end of window or read pointer */ + uInt ml; /* mask for literal/length tree */ + uInt md; /* mask for distance tree */ + uInt c; /* bytes to copy */ + uInt d; /* distance back to copy from */ + Bytef *r; /* copy source pointer */ + + /* load input, output, bit values */ + LOAD + + /* initialize masks */ + ml = inflate_mask[bl]; + md = inflate_mask[bd]; + + /* do until not enough input or output space for fast loop */ + do { /* assume called with m >= 258 && n >= 10 */ + /* get literal/length code */ + GRABBITS(20) /* max bits for literal/length code */ + if ((e = (t = tl + ((uInt)b & ml))->exop) == 0) + { + DUMPBITS(t->bits) + Tracevv((stderr, t->base >= 0x20 && t->base < 0x7f ? + "inflate: * literal '%c'\n" : + "inflate: * literal 0x%02x\n", t->base)); + *q++ = (Byte)t->base; + m--; + continue; + } + do { + DUMPBITS(t->bits) + if (e & 16) + { + /* get extra bits for length */ + e &= 15; + c = t->base + ((uInt)b & inflate_mask[e]); + DUMPBITS(e) + Tracevv((stderr, "inflate: * length %u\n", c)); + + /* decode distance base of block to copy */ + GRABBITS(15); /* max bits for distance code */ + e = (t = td + ((uInt)b & md))->exop; + do { + DUMPBITS(t->bits) + if (e & 16) + { + /* get extra bits to add to distance base */ + e &= 15; + GRABBITS(e) /* get extra bits (up to 13) */ + d = t->base + ((uInt)b & inflate_mask[e]); + DUMPBITS(e) + Tracevv((stderr, "inflate: * distance %u\n", d)); + + /* do the copy */ + m -= c; + if ((uInt)(q - s->window) >= d) /* offset before dest */ + { /* just copy */ + r = q - d; + *q++ = *r++; c--; /* minimum count is three, */ + *q++ = *r++; c--; /* so unroll loop a little */ + } + else /* else offset after destination */ + { + e = d - (q - s->window); /* bytes from offset to end */ + r = s->end - e; /* pointer to offset */ + if (c > e) /* if source crosses, */ + { + c -= e; /* copy to end of window */ + do { + *q++ = *r++; + } while (--e); + r = s->window; /* copy rest from start of window */ + } + } + do { /* copy all or what's left */ + *q++ = *r++; + } while (--c); + break; + } + else if ((e & 64) == 0) + e = (t = t->next + ((uInt)b & inflate_mask[e]))->exop; + else + { + z->msg = "invalid distance code"; + UNGRAB + UPDATE + return Z_DATA_ERROR; + } + } while (1); + break; + } + if ((e & 64) == 0) + { + if ((e = (t = t->next + ((uInt)b & inflate_mask[e]))->exop) == 0) + { + DUMPBITS(t->bits) + Tracevv((stderr, t->base >= 0x20 && t->base < 0x7f ? + "inflate: * literal '%c'\n" : + "inflate: * literal 0x%02x\n", t->base)); + *q++ = (Byte)t->base; + m--; + break; + } + } + else if (e & 32) + { + Tracevv((stderr, "inflate: * end of block\n")); + UNGRAB + UPDATE + return Z_STREAM_END; + } + else + { + z->msg = "invalid literal/length code"; + UNGRAB + UPDATE + return Z_DATA_ERROR; + } + } while (1); + } while (m >= 258 && n >= 10); + + /* not enough input or output--restore pointers and return */ + UNGRAB + UPDATE + return Z_OK; +} + + +/*+++++*/ +/* zutil.c -- target dependent utility functions for the compression library + * Copyright (C) 1995 Jean-loup Gailly. + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* From: zutil.c,v 1.8 1995/05/03 17:27:12 jloup Exp */ + +char *zlib_version = ZLIB_VERSION; + +char *z_errmsg[] = { +"stream end", /* Z_STREAM_END 1 */ +"", /* Z_OK 0 */ +"file error", /* Z_ERRNO (-1) */ +"stream error", /* Z_STREAM_ERROR (-2) */ +"data error", /* Z_DATA_ERROR (-3) */ +"insufficient memory", /* Z_MEM_ERROR (-4) */ +"buffer error", /* Z_BUF_ERROR (-5) */ +""}; + + +/*+++++*/ +/* adler32.c -- compute the Adler-32 checksum of a data stream + * Copyright (C) 1995 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* From: adler32.c,v 1.6 1995/05/03 17:27:08 jloup Exp */ + +#define BASE 65521L /* largest prime smaller than 65536 */ +#define NMAX 5552 +/* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */ + +#define DO1(buf) {s1 += *buf++; s2 += s1;} +#define DO2(buf) DO1(buf); DO1(buf); +#define DO4(buf) DO2(buf); DO2(buf); +#define DO8(buf) DO4(buf); DO4(buf); +#define DO16(buf) DO8(buf); DO8(buf); + +/* ========================================================================= */ +uLong adler32(adler, buf, len) + uLong adler; + Bytef *buf; + uInt len; +{ + unsigned long s1 = adler & 0xffff; + unsigned long s2 = (adler >> 16) & 0xffff; + int k; + + if (buf == Z_NULL) return 1L; + + while (len > 0) { + k = len < NMAX ? len : NMAX; + len -= k; + while (k >= 16) { + DO16(buf); + k -= 16; + } + if (k != 0) do { + DO1(buf); + } while (--k); + s1 %= BASE; + s2 %= BASE; + } + return (s2 << 16) | s1; +} diff --git a/lib_i386/Makefile b/lib_i386/Makefile new file mode 100644 index 0000000..e5925e5 --- /dev/null +++ b/lib_i386/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = bios.o bios_pci.o realmode_switch.o + +COBJS = board.o bios_setup.o i386_linux.o zimage.o realmode.o \ + pci_type1.o pci.o video_bios.o video.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_i386/bios.S b/lib_i386/bios.S new file mode 100644 index 0000000..4606419 --- /dev/null +++ b/lib_i386/bios.S @@ -0,0 +1,462 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Based on msbios.c from rolo 1.6: + *---------------------------------------------------------------------- + * (C) Copyright 2000 + * Sysgo Real-Time Solutions GmbH + * Klein-Winternheim, Germany + *---------------------------------------------------------------------- + */ + +#include "bios.h" + +/* + * During it's initialization phase, before switching to protected + * mode, the Linux Kernel makes a few BIOS calls. This won't work + * if the board does not have a BIOS. + * + * This is a very minimalisic BIOS that supplies just enough + * functionality to keep the Linux Kernel happy. It is NOT + * a general purpose replacement for a real BIOS !! + */ + + +.section .bios, "ax" +.code16 +.org 0 + /* a call to f000:0 should warmboot */ + jmp realmode_reset + +.globl rm_int00 +rm_int00: + pushw $0 + jmp any_interrupt16 +.globl rm_int01 +rm_int01: + pushw $1 + jmp any_interrupt16 +.globl rm_int02 +rm_int02: + pushw $2 + jmp any_interrupt16 +.globl rm_int03 +rm_int03: + pushw $3 + jmp any_interrupt16 +.globl rm_int04 +rm_int04: + pushw $4 + jmp any_interrupt16 +.globl rm_int05 +rm_int05: + pushw $5 + jmp any_interrupt16 +.globl rm_int06 +rm_int06: + pushw $6 + jmp any_interrupt16 +.globl rm_int07 +rm_int07: + pushw $7 + jmp any_interrupt16 +.globl rm_int08 +rm_int08: + pushw $8 + jmp any_interrupt16 +.globl rm_int09 +rm_int09: + pushw $9 + jmp any_interrupt16 +.globl rm_int0a +rm_int0a: + pushw $10 + jmp any_interrupt16 +.globl rm_int0b +rm_int0b: + pushw $11 + jmp any_interrupt16 +.globl rm_int0c +rm_int0c: + pushw $12 + jmp any_interrupt16 +.globl rm_int0d +rm_int0d: + pushw $13 + jmp any_interrupt16 +.globl rm_int0e +rm_int0e: + pushw $14 + jmp any_interrupt16 +.globl rm_int0f +rm_int0f: + pushw $15 + jmp any_interrupt16 +.globl rm_int10 +rm_int10: + pushw $16 + jmp any_interrupt16 +.globl rm_int11 +rm_int11: + pushw $17 + jmp any_interrupt16 +.globl rm_int12 +rm_int12: + pushw $18 + jmp any_interrupt16 +.globl rm_int13 +rm_int13: + pushw $19 + jmp any_interrupt16 +.globl rm_int14 +rm_int14: + pushw $20 + jmp any_interrupt16 +.globl rm_int15 +rm_int15: + pushw $21 + jmp any_interrupt16 +.globl rm_int16 +rm_int16: + pushw $22 + jmp any_interrupt16 +.globl rm_int17 +rm_int17: + pushw $23 + jmp any_interrupt16 +.globl rm_int18 +rm_int18: + pushw $24 + jmp any_interrupt16 +.globl rm_int19 +rm_int19: + pushw $25 + jmp any_interrupt16 +.globl rm_int1a +rm_int1a: + pushw $26 + jmp any_interrupt16 +.globl rm_int1b +rm_int1b: + pushw $27 + jmp any_interrupt16 +.globl rm_int1c +rm_int1c: + pushw $28 + jmp any_interrupt16 +.globl rm_int1d +rm_int1d: + pushw $29 + jmp any_interrupt16 +.globl rm_int1e +rm_int1e: + pushw $30 + jmp any_interrupt16 +.globl rm_int1f +rm_int1f: + pushw $31 + jmp any_interrupt16 +.globl rm_def_int +rm_def_int: + iret + + + /* + * All interrupt jumptable entries jump to here + * after pushing the interrupt vector number onto the + * stack. + */ +any_interrupt16: + MAKE_BIOS_STACK + +gs movw OFFS_VECTOR(%bp), %ax + cmpw $0x10, %ax + je Lint_10h + cmpw $0x11, %ax + je Lint_11h + cmpw $0x12, %ax + je Lint_12h + cmpw $0x13, %ax + je Lint_13h + cmpw $0x15, %ax + je Lint_15h + cmpw $0x16, %ax + je Lint_16h + cmpw $0x1a, %ax + je Lint_1ah + movw $0xffff, %ax + jmp Lout +Lint_10h: /* VGA BIOS services */ + call bios_10h + jmp Lout +Lint_11h: + call bios_11h + jmp Lout +Lint_12h: + call bios_12h + jmp Lout +Lint_13h: /* BIOS disk services */ + call bios_13h + jmp Lout +Lint_15h: /* Misc. BIOS services */ + call bios_15h + jmp Lout +Lint_16h: /* keyboard services */ + call bios_16h + jmp Lout +Lint_1ah: /* PCI bios */ + call bios_1ah + jmp Lout +Lout: + cmpw $0, %ax + je Lhandeled + + /* Insert code for unhandeled INTs here. + * + * ROLO prints a message to the console + * (we could do that but then we're in 16bit mode + * so we'll have to get back into 32bit mode + * to use the console I/O routines (if we do this + * we shuls make int 0x10 and int 0x16 work as well)) + */ +Lhandeled: + RESTORE_CALLERS_STACK + addw $2,%sp /* dump vector number */ + iret /* return from interrupt */ + + +/* + ************************************************************ + * BIOS interrupt 10h -- VGA services + ************************************************************ + */ +bios_10h: +gs movw OFFS_AX(%bp), %ax + shrw $8, %ax + cmpw $0x3, %ax + je Lcur_pos + cmpw $0xf, %ax + je Lvid_state + cmpw $0x12, %ax + je Lvid_cfg + movw $0xffff, %ax + ret +Lcur_pos: /* Read Cursor Position and Size */ +gs movw $0, OFFS_CX(%bp) +gs movw $0, OFFS_DX(%bp) + xorw %ax, %ax + ret +Lvid_state: /* Get Video State */ +gs movw $(80 << 8|0x03), OFFS_AX(%bp) /* 80 columns, 80x25, 16 colors */ +gs movw $0, OFFS_BX(%bp) + xorw %ax, %ax + ret +Lvid_cfg: /* Video Subsystem Configuration (EGA/VGA) */ +gs movw $0x10, OFFS_BX(%bp) /* indicate CGA/MDA/HGA */ + xorw %ax, %ax + ret + + +/* + ************************************************************ + * BIOS interrupt 11h -- Equipment determination + ************************************************************ + */ + +bios_11h: +cs movw bios_equipment, %ax +gs movw %ax, OFFS_AX(%bp) + xorw %ax, %ax + ret + + +/* + ************************************************************ + * BIOS interrupt 12h -- Get Memory Size + ************************************************************ + */ +bios_12h: +cs movw ram_in_64kb_chunks, %ax + cmpw $0xa, %ax + ja b12_more_than_640k + shlw $6, %ax + jmp b12_return +b12_more_than_640k: + movw $0x280, %ax +b12_return: +gs movw %ax, OFFS_AX(%bp) /* return number of kilobytes in ax */ + +gs movw OFFS_FLAGS(%bp), %ax + andw $0xfffe, %ax /* clear carry -- function succeeded */ +gs movw %ax, OFFS_FLAGS(%bp) + + xorw %ax, %ax + ret + + +/* + ************************************************************ + * BIOS interrupt 13h -- Disk services + ************************************************************ + */ +bios_13h: +gs movw OFFS_AX(%bp), %ax + shrw $8, %ax + cmpw $0x15, %ax + je Lfunc_15h + movw $0xffff, %ax + ret +Lfunc_15h: +gs movw OFFS_AX(%bp), %ax + andw $0xff, %ax /* return AH=0->drive not present */ +gs movw %ax, OFFS_AX(%bp) + xorw %ax, %ax + ret + + +/* + *********************************************************** + * BIOS interrupt 15h -- Miscellaneous services + *********************************************************** + */ +bios_15h: +gs movw OFFS_AX(%bp), %ax + shrw $8, %ax + cmpw $0xc0, %ax + je Lfunc_c0h + cmpw $0xe8, %ax + je Lfunc_e8h + cmpw $0x88, %ax + je Lfunc_88h + movw $0xffff, %ax + ret + +Lfunc_c0h: /* Return System Configuration Parameters (PS2 only) */ +gs movw OFFS_FLAGS(%bp), %ax + orw $1, %ax /* return carry -- function not supported */ +gs movw %ax, OFFS_FLAGS(%bp) + xorw %ax, %ax + ret + +Lfunc_e8h: +gs movw OFFS_AX(%bp), %ax + andw $0xff, %ax + cmpw $1, %ax + je Lfunc_e801h +gs movw OFFS_FLAGS(%bp), %ax + orw $1, %ax /* return carry -- function not supported */ +gs movw %ax, OFFS_FLAGS(%bp) + xorw %ax, %ax + ret + +Lfunc_e801h: /* Get memory size for >64M Configurations */ +cs movw ram_in_64kb_chunks, %ax + cmpw $0x100, %ax + ja e801_more_than_16mb + shlw $6, %ax /* multiply by 64 */ + subw $0x400, %ax /* 1st meg does not count */ + +gs movw %ax, OFFS_AX(%bp) /* return memory size between 1M and 16M in 1kb chunks in AX and CX */ +gs movw %ax, OFFS_CX(%bp) +gs movw $0, OFFS_BX(%bp) /* set BX and DX to 0*/ +gs movw $0, OFFS_DX(%bp) +gs movw OFFS_FLAGS(%bp), %ax + andw $0xfffe, %ax /* clear carry -- function succeeded */ +gs movw %ax, OFFS_FLAGS(%bp) + xorw %ax, %ax + ret + +e801_more_than_16mb: + subw $0x100, %ax /* subtract 16MB */ + +gs movw $0x3c00, OFFS_AX(%bp) /* return 0x3c00 (16MB-1MB) in AX and CX */ +gs movw $0x3c00, OFFS_CX(%bp) +gs movw %ax, OFFS_BX(%bp) /* set BX and DX to number of 64kb chunks above 16MB */ +gs movw %ax, OFFS_DX(%bp) + +gs movw OFFS_FLAGS(%bp), %ax + andw $0xfffe, %ax /* clear carry -- function succeeded */ +gs movw %ax, OFFS_FLAGS(%bp) + xorw %ax, %ax + ret + +Lfunc_88h: +cs movw ram_in_64kb_chunks, %ax + cmpw $0x100, %ax + jna b88_not_more_than16 + movw $0x100, %ax +b88_not_more_than16: + shlw $6, %ax + subw $0x400, %ax /* 1st meg does not count */ + +gs movw %ax, OFFS_AX(%bp) /* return number of kilobytes between 16MB and 16MB in ax */ + +gs movw OFFS_FLAGS(%bp), %ax + andw $0xfffe, %ax /* clear carry -- function succeeded */ +gs movw %ax, OFFS_FLAGS(%bp) + + xorw %ax, %ax + ret + + +/* + ************************************************************ + * BIOS interrupt 16h -- keyboard services + ************************************************************ + */ +bios_16h: +gs movw OFFS_AX(%bp), %ax + shrw $8, %ax + cmpw $0x03, %ax + je Lfunc_03h + movw $0xffff, %ax + ret +Lfunc_03h: + xorw %ax, %ax /* do nothing -- function not supported */ + ret + +/* + ************************************************************ + * BIOS interrupt 1ah -- PCI bios + ************************************************************ + */ +bios_1ah: +gs movw OFFS_AX(%bp), %ax + cmpb $0xb1, %ah + je Lfunc_b1h + movw $0xffff, %ax + ret +Lfunc_b1h: + call realmode_pci_bios + xorw %ax, %ax /* do nothing -- function not supported */ + ret + + +.globl ram_in_64kb_chunks +ram_in_64kb_chunks: + .word 0 + +.globl bios_equipment +bios_equipment: + .word 0 diff --git a/lib_i386/bios.h b/lib_i386/bios.h new file mode 100644 index 0000000..59143dd --- /dev/null +++ b/lib_i386/bios.h @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BIOS_H_ +#define _BIOS_H_ + +#define OFFS_ES 0 /* 16bit */ +#define OFFS_GS 2 /* 16bit */ +#define OFFS_DS 4 /* 16bit */ +#define OFFS_EDI 6 /* 32bit */ +#define OFFS_DI 6 /* low 16 bits of EDI */ +#define OFFS_ESI 10 /* 32bit */ +#define OFFS_SI 10 /* low 16 bits of ESI */ +#define OFFS_EBP 14 /* 32bit */ +#define OFFS_BP 14 /* low 16 bits of EBP */ +#define OFFS_ESP 18 /* 32bit */ +#define OFFS_SP 18 /* low 16 bits of ESP */ +#define OFFS_EBX 22 /* 32bit */ +#define OFFS_BX 22 /* low 16 bits of EBX */ +#define OFFS_BL 22 /* low 8 bits of BX */ +#define OFFS_BH 23 /* high 8 bits of BX */ +#define OFFS_EDX 26 /* 32bit */ +#define OFFS_DX 26 /* low 16 bits of EBX */ +#define OFFS_DL 26 /* low 8 bits of BX */ +#define OFFS_DH 27 /* high 8 bits of BX */ +#define OFFS_ECX 30 /* 32bit */ +#define OFFS_CX 30 /* low 16 bits of EBX */ +#define OFFS_CL 30 /* low 8 bits of BX */ +#define OFFS_CH 31 /* high 8 bits of BX */ +#define OFFS_EAX 34 /* 32bit */ +#define OFFS_AX 34 /* low 16 bits of EBX */ +#define OFFS_AL 34 /* low 8 bits of BX */ +#define OFFS_AH 35 /* high 8 bits of BX */ +#define OFFS_VECTOR 38 /* 16bit */ +#define OFFS_IP 40 /* 16bit */ +#define OFFS_CS 42 /* 16bit */ +#define OFFS_FLAGS 44 /* 16bit */ + +#define SEGMENT 0x40 +#define STACK 0x800 /* stack at 0x40:0x800 -> 0x800 */ + +/* save general registers */ +/* save some segments */ +/* save callers stack segment .. */ +/* ... in gs */ + /* setup my segments */ + /* setup BIOS stackpointer */ + +#define MAKE_BIOS_STACK \ + pushal ; \ + pushw %ds ; \ + pushw %gs ; \ + pushw %es ; \ + pushw %ss ; \ + popw %gs ; \ + movw $SEGMENT,%ax ; \ + movw %ax,%ds ; \ + movw %ax,%es ; \ + movw %ax,%ss ; \ + movw %sp,%bp ; \ + movw $STACK,%sp + +#define RESTORE_CALLERS_STACK \ + pushw %gs ; /* restore callers stack segment */ \ + popw %ss ; \ + movw %bp,%sp ; /* restore stackpointer */ \ + \ + popw %es ; /* restore segment selectors */ \ + popw %gs ; \ + popw %ds ; \ + \ + popal /* restore GP registers */ + +#endif diff --git a/lib_i386/bios_pci.S b/lib_i386/bios_pci.S new file mode 100644 index 0000000..b57b726 --- /dev/null +++ b/lib_i386/bios_pci.S @@ -0,0 +1,411 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * x86 realmode assembly implementation of a PCI BIOS + * for platforms that use one PCI hose and configuration + * access type 1. (The common case for low-end PC's) + */ + +#include "bios.h" + +#define PCI_BIOS_DEBUG + +.section .bios, "ax" +.code16 +.globl realmode_pci_bios_call_entry +realmode_pci_bios_call_entry: + MAKE_BIOS_STACK + call realmode_pci_bios + RESTORE_CALLERS_STACK + ret + + +.globl realmode_pci_bios +realmode_pci_bios: +gs movw OFFS_AX(%bp), %ax + cmpb $1, %al + je pci_bios_present + cmpb $2, %al + je pci_bios_find_device + cmpb $3, %al + je pci_bios_find_class + cmpb $6, %al + je pci_bios_generate_special_cycle + cmpb $8, %al + je pci_bios_read_cfg_byte + cmpb $9, %al + je pci_bios_read_cfg_word + cmpb $10, %al + je pci_bios_read_cfg_dword + cmpb $11, %al + je pci_bios_write_cfg_byte + cmpb $12, %al + je pci_bios_write_cfg_word + cmpb $13, %al + je pci_bios_write_cfg_dword + cmpb $14, %al + je pci_bios_get_irq_routing + cmpb $15, %al + je pci_bios_set_irq + jmp unknown_function + +/*****************************************************************************/ + +pci_bios_present: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_present +#endif + movl $0x20494350, %eax +gs movl %eax, OFFS_EDX(%bp) + movb $0x01, %al +gs movb %al, OFFS_AL(%bp) /* We support cfg type 1 */ + movw $0x0210, %ax /* version 2.10 */ +gs movw %ax, OFFS_BX(%bp) +cs movb pci_last_bus, %al /* last bus number */ +gs movb %al, OFFS_CL(%bp) + jmp clear_carry + +/*****************************************************************************/ + +/* device 0-31, function 0-7 */ +pci_bios_find_device: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_find_device +#endif +gs movw OFFS_CX(%bp), %di + shll $16, %edi +gs movw OFFS_DX(%bp), %di /* edi now holds device in upper 16 + * bits and vendor in lower 16 bits */ +gs movw OFFS_SI(%bp), %si + xorw %bx, %bx /* start at bus 0 dev 0 function 0 */ +pfd_loop: + xorw %ax, %ax /* dword 0 is vendor/device */ + call __pci_bios_select_register + movw $0xcfc, %dx + inl %dx, %eax + cmpl %edi, %eax /* our device ? */ + je pfd_found_one +pfd_next_dev: + /* check for multi function devices */ + movw %bx, %ax + andw $3, %ax + jnz pfd_function_not_zero + movw $0x000c, %ax + call __pci_bios_select_register + movw $0xcfe, %dx + inb %dx, %al + andb $0x80, %al + jz pfd_not_multi_function +pfd_function_not_zero: + incw %bx /* next function, overflows in to + * device number, then bus number */ + jmp pfd_check_bus + +pfd_not_multi_function: + andw $0xfff8, %bx /* remove function bits */ + addw $0x0008, %bx /* next device, overflows in to bus number */ +pfd_check_bus: +cs movb pci_last_bus, %ah + cmpb %ah, %bh + ja pfd_not_found + jmp pfd_loop +pfd_found_one: + decw %si + js pfd_done + jmp pfd_next_dev + +pfd_done: +gs movw %bx, OFFS_BX(%bp) + jmp clear_carry + +pfd_not_found: + movb $0x86, %ah /* device not found */ + jmp set_carry + +/*****************************************************************************/ + +pci_bios_find_class: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_find_class +#endif +gs movl OFFS_ECX(%bp), %edi + andl $0x00ffffff, %edi /* edi now holds class-code in lower 24 bits */ +gs movw OFFS_SI(%bp), %si + xorw %bx, %bx /* start at bus 0 dev 0 function 0 */ +pfc_loop: + movw $8, %ax /* dword 8 is class-code high 24bits */ + call __pci_bios_select_register + movw $0xcfc, %dx + inl %dx, %eax + shrl $8, %eax + andl $0x00ffffff, %eax + cmpl %edi, %eax /* our device ? */ + je pfc_found_one +pfc_next_dev: + /* check for multi function devices */ + andw $3, %bx + jnz pfc_function_not_zero + movw $0x000c, %ax + call __pci_bios_select_register + movw $0xcfe, %dx + inb %dx, %al + andb $0x80, %al + jz pfc_not_multi_function +pfc_function_not_zero: + incw %bx /* next function, overflows in to + * device number, then bus number */ + jmp pfc_check_bus + +pfc_not_multi_function: + andw $0xfff8, %bx /* remove function bits */ + addw $0x0008, %bx /* next device, overflows in to bus number */ +pfc_check_bus: +cs movb pci_last_bus, %ah + cmpb %ah, %bh + ja pfc_not_found + jmp pfc_loop +pfc_found_one: + decw %si + js pfc_done + jmp pfc_next_dev + +pfc_done: +gs movw %bx, OFFS_BX(%bp) + jmp clear_carry + +pfc_not_found: + movb $0x86, %ah /* device not found */ + jmp set_carry + +/*****************************************************************************/ + +pci_bios_generate_special_cycle: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_generate_special_cycle +#endif + movb $0x81, %ah /* function not supported */ + jmp set_carry + +/*****************************************************************************/ + +pci_bios_read_cfg_byte: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_read_cfg_byte +#endif + call pci_bios_select_register +gs movw OFFS_DI(%bp), %dx + andw $3, %dx + addw $0xcfc, %dx + inb %dx, %al +gs movb %al, OFFS_CL(%bp) + jmp clear_carry + +/*****************************************************************************/ + +pci_bios_read_cfg_word: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_read_cfg_word +#endif + call pci_bios_select_register +gs movw OFFS_DI(%bp), %dx + andw $2, %dx + addw $0xcfc, %dx + inw %dx, %ax +gs movw %ax, OFFS_CX(%bp) + jmp clear_carry + + +/*****************************************************************************/ + +pci_bios_read_cfg_dword: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_read_cfg_dword +#endif + call pci_bios_select_register + movw $0xcfc, %dx + inl %dx, %eax +gs movl %eax, OFFS_ECX(%bp) + jmp clear_carry + +/*****************************************************************************/ + +pci_bios_write_cfg_byte: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_write_cfg_byte +#endif + call pci_bios_select_register +gs movw OFFS_DI(%bp), %dx +gs movb OFFS_CL(%bp), %al + andw $3, %dx + addw $0xcfc, %dx + outb %al, %dx + jmp clear_carry + +/*****************************************************************************/ + +pci_bios_write_cfg_word: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_write_cfg_word +#endif + call pci_bios_select_register +gs movw OFFS_DI(%bp), %dx +gs movw OFFS_CX(%bp), %ax + andw $2, %dx + addw $0xcfc, %dx + outw %ax, %dx + jmp clear_carry + +/*****************************************************************************/ + +pci_bios_write_cfg_dword: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_write_cfg_dword +#endif + call pci_bios_select_register +gs movl OFFS_ECX(%bp), %eax + movw $0xcfc, %dx + outl %eax, %dx + jmp clear_carry + +/*****************************************************************************/ + +pci_bios_get_irq_routing: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_get_irq_routing +#endif + movb $0x81, %ah /* function not supported */ + jmp set_carry + +/*****************************************************************************/ + +pci_bios_set_irq: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_set_irq +#endif + movb $0x81, %ah /* function not supported */ + jmp set_carry + +/*****************************************************************************/ + +unknown_function: +#ifdef PCI_BIOS_DEBUG +cs incl num_pci_bios_unknown_function +#endif + movb $0x81, %ah /* function not supported */ + jmp set_carry + +/*****************************************************************************/ + +pci_bios_select_register: +gs movw OFFS_BX(%bp), %bx +gs movw OFFS_DI(%bp), %ax +/* destroys eax, dx */ +__pci_bios_select_register: /* BX holds device id, AX holds register index */ + pushl %ebx + andl $0xfc, %eax + andl $0xffff, %ebx + shll $8, %ebx + orl %ebx, %eax + orl $0x80000000, %eax + movw $0xcf8, %dx + outl %eax, %dx + popl %ebx + ret + + +clear_carry: +gs movw OFFS_FLAGS(%bp), %ax + andw $0xfffe, %ax /* clear carry -- function succeeded */ +gs movw %ax, OFFS_FLAGS(%bp) + xorw %ax, %ax +gs movb %ah, OFFS_AH(%bp) + ret + +set_carry: +gs movb %ah, OFFS_AH(%bp) +gs movw OFFS_FLAGS(%bp), %ax + orw $1, %ax /* return carry -- function not supported */ +gs movw %ax, OFFS_FLAGS(%bp) + movw $-1, %ax + ret + +/*****************************************************************************/ + +.globl pci_last_bus +pci_last_bus: + .byte 0 + +#ifdef PCI_BIOS_DEBUG +.globl num_pci_bios_present +num_pci_bios_present: + .long 0 + +.globl num_pci_bios_find_device +num_pci_bios_find_device: + .long 0 + +.globl num_pci_bios_find_class +num_pci_bios_find_class: + .long 0 + +.globl num_pci_bios_generate_special_cycle +num_pci_bios_generate_special_cycle: + .long 0 + +.globl num_pci_bios_read_cfg_byte +num_pci_bios_read_cfg_byte: + .long 0 + +.globl num_pci_bios_read_cfg_word +num_pci_bios_read_cfg_word: + .long 0 + +.globl num_pci_bios_read_cfg_dword +num_pci_bios_read_cfg_dword: + .long 0 + +.globl num_pci_bios_write_cfg_byte +num_pci_bios_write_cfg_byte: + .long 0 + +.globl num_pci_bios_write_cfg_word +num_pci_bios_write_cfg_word: + .long 0 + +.globl num_pci_bios_write_cfg_dword +num_pci_bios_write_cfg_dword: + .long 0 + +.globl num_pci_bios_get_irq_routing +num_pci_bios_get_irq_routing: + .long 0 + +.globl num_pci_bios_set_irq +num_pci_bios_set_irq: + .long 0 + +.globl num_pci_bios_unknown_function +num_pci_bios_unknown_function: + .long 0 +#endif diff --git a/lib_i386/bios_setup.c b/lib_i386/bios_setup.c new file mode 100644 index 0000000..bc97815 --- /dev/null +++ b/lib_i386/bios_setup.c @@ -0,0 +1,233 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +/* + * Partly based on msbios.c from rolo 1.6: + *---------------------------------------------------------------------- + * (C) Copyright 2000 + * Sysgo Real-Time Solutions GmbH + * Klein-Winternheim, Germany + *---------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define NUMVECTS 256 + +#define BIOS_DATA ((char*)0x400) +#define BIOS_DATA_SIZE 256 +#define BIOS_BASE ((char*)0xf0000) +#define BIOS_CS 0xf000 + +/* these are defined in a 16bit segment and needs + * to be accessed with the RELOC_16_xxxx() macros below + */ +extern u16 ram_in_64kb_chunks; +extern u16 bios_equipment; +extern u8 pci_last_bus; + +extern void *rm_int00; +extern void *rm_int01; +extern void *rm_int02; +extern void *rm_int03; +extern void *rm_int04; +extern void *rm_int05; +extern void *rm_int06; +extern void *rm_int07; +extern void *rm_int08; +extern void *rm_int09; +extern void *rm_int0a; +extern void *rm_int0b; +extern void *rm_int0c; +extern void *rm_int0d; +extern void *rm_int0e; +extern void *rm_int0f; +extern void *rm_int10; +extern void *rm_int11; +extern void *rm_int12; +extern void *rm_int13; +extern void *rm_int14; +extern void *rm_int15; +extern void *rm_int16; +extern void *rm_int17; +extern void *rm_int18; +extern void *rm_int19; +extern void *rm_int1a; +extern void *rm_int1b; +extern void *rm_int1c; +extern void *rm_int1d; +extern void *rm_int1e; +extern void *rm_int1f; +extern void *rm_def_int; + +extern void *realmode_reset; +extern void *realmode_pci_bios_call_entry; + +static int set_jmp_vector(int entry_point, void *target) +{ + if (entry_point & ~0xffff) { + return -1; + } + + if (((u32)target-0xf0000) & ~0xffff) { + return -1; + } + printf("set_jmp_vector: 0xf000:%04x -> %p\n", + entry_point, target); + + /* jmp opcode */ + writeb(0xea, 0xf0000 + entry_point); + + /* offset */ + writew(((u32)target-0xf0000), 0xf0000 + entry_point + 1); + + /* segment */ + writew(0xf000, 0xf0000 + entry_point + 3); + + return 0; +} + + +/* + ************************************************************ + * Install an interrupt vector + ************************************************************ + */ + +static void setvector(int vector, u16 segment, void *handler) +{ + u16 *ptr = (u16*)(vector*4); + ptr[0] = ((u32)handler - (segment << 4))&0xffff; + ptr[1] = segment; + +#if 0 + printf("setvector: int%02x -> %04x:%04x\n", + vector, ptr[1], ptr[0]); +#endif +} + +#define RELOC_16_LONG(seg, off) *(u32*)(seg << 4 | (u32)&off) +#define RELOC_16_WORD(seg, off) *(u16*)(seg << 4 | (u32)&off) +#define RELOC_16_BYTE(seg, off) *(u8*)(seg << 4 | (u32)&off) + +int bios_setup(void) +{ + DECLARE_GLOBAL_DATA_PTR; + static int done=0; + int vector; + struct pci_controller *pri_hose; + + if (done) { + return 0; + } + done = 1; + + if (i386boot_bios_size > 65536) { + printf("BIOS too large (%ld bytes, max is 65536)\n", + i386boot_bios_size); + return -1; + } + + memcpy(BIOS_BASE, (void*)i386boot_bios, i386boot_bios_size); + + /* clear bda */ + memset(BIOS_DATA, 0, BIOS_DATA_SIZE); + + /* enter some values to the bda */ + writew(0x3f8, BIOS_DATA); /* com1 addr */ + writew(0x2f8, BIOS_DATA+2); /* com2 addr */ + writew(0x3e8, BIOS_DATA+4); /* com3 addr */ + writew(0x2e8, BIOS_DATA+6); /* com4 addr */ + writew(0x278, BIOS_DATA+8); /* lpt1 addr */ + /* + * The kernel wants to read the base memory size + * from 40:13. Put a zero there to avoid an error message + */ + writew(0, BIOS_DATA+0x13); /* base memory size */ + + + /* setup realmode interrupt vectors */ + for (vector = 0; vector < NUMVECTS; vector++) { + setvector(vector, BIOS_CS, &rm_def_int); + } + + setvector(0x00, BIOS_CS, &rm_int00); + setvector(0x01, BIOS_CS, &rm_int01); + setvector(0x02, BIOS_CS, &rm_int02); + setvector(0x03, BIOS_CS, &rm_int03); + setvector(0x04, BIOS_CS, &rm_int04); + setvector(0x05, BIOS_CS, &rm_int05); + setvector(0x06, BIOS_CS, &rm_int06); + setvector(0x07, BIOS_CS, &rm_int07); + setvector(0x08, BIOS_CS, &rm_int08); + setvector(0x09, BIOS_CS, &rm_int09); + setvector(0x0a, BIOS_CS, &rm_int0a); + setvector(0x0b, BIOS_CS, &rm_int0b); + setvector(0x0c, BIOS_CS, &rm_int0c); + setvector(0x0d, BIOS_CS, &rm_int0d); + setvector(0x0e, BIOS_CS, &rm_int0e); + setvector(0x0f, BIOS_CS, &rm_int0f); + setvector(0x10, BIOS_CS, &rm_int10); + setvector(0x11, BIOS_CS, &rm_int11); + setvector(0x12, BIOS_CS, &rm_int12); + setvector(0x13, BIOS_CS, &rm_int13); + setvector(0x14, BIOS_CS, &rm_int14); + setvector(0x15, BIOS_CS, &rm_int15); + setvector(0x16, BIOS_CS, &rm_int16); + setvector(0x17, BIOS_CS, &rm_int17); + setvector(0x18, BIOS_CS, &rm_int18); + setvector(0x19, BIOS_CS, &rm_int19); + setvector(0x1a, BIOS_CS, &rm_int1a); + setvector(0x1b, BIOS_CS, &rm_int1b); + setvector(0x1c, BIOS_CS, &rm_int1c); + setvector(0x1d, BIOS_CS, &rm_int1d); + setvector(0x1e, BIOS_CS, &rm_int1e); + setvector(0x1f, BIOS_CS, &rm_int1f); + + set_jmp_vector(0xfff0, &realmode_reset); + set_jmp_vector(0xfe6e, &realmode_pci_bios_call_entry); + + /* fill in data area */ + RELOC_16_WORD(0xf000, ram_in_64kb_chunks) = gd->ram_size >> 16; + RELOC_16_WORD(0xf000, bios_equipment) = 0; /* FixMe */ + + /* If we assume only one PCI hose, this PCI hose + * will own PCI bus #0, and the last PCI bus of + * that PCI hose will be the last PCI bus in the + * system. + * (This, ofcause break on multi hose systems, + * but our PCI BIOS only support one hose anyway) + */ + pri_hose = pci_bus_to_hose(0); + if (NULL != pri_hose) { + /* fill in last pci bus number for use by the realmode + * PCI BIOS */ + RELOC_16_BYTE(0xf000, pci_last_bus) = pri_hose->last_busno; + } + + return 0; +} diff --git a/lib_i386/board.c b/lib_i386/board.c new file mode 100644 index 0000000..e90eb6e --- /dev/null +++ b/lib_i386/board.c @@ -0,0 +1,427 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern long _i386boot_start; +extern long _i386boot_end; +extern long _i386boot_romdata_start; +extern long _i386boot_romdata_dest; +extern long _i386boot_romdata_size; +extern long _i386boot_bss_start; +extern long _i386boot_bss_size; + +extern long _i386boot_realmode; +extern long _i386boot_realmode_size; +extern long _i386boot_bios; +extern long _i386boot_bios_size; + +/* The symbols defined by the linker script becomes pointers + * which is somewhat inconveient ... */ +ulong i386boot_start = (ulong)&_i386boot_start; /* code start (in flash) defined in start.S */ +ulong i386boot_end = (ulong)&_i386boot_end; /* code end (in flash) */ +ulong i386boot_romdata_start = (ulong)&_i386boot_romdata_start; /* datasegment in flash (also code+rodata end) */ +ulong i386boot_romdata_dest = (ulong)&_i386boot_romdata_dest; /* data location segment in ram */ +ulong i386boot_romdata_size = (ulong)&_i386boot_romdata_size; /* size of data segment */ +ulong i386boot_bss_start = (ulong)&_i386boot_bss_start; /* bss start */ +ulong i386boot_bss_size = (ulong)&_i386boot_bss_size; /* bss size */ + +ulong i386boot_realmode = (ulong)&_i386boot_realmode; /* start of realmode entry code */ +ulong i386boot_realmode_size = (ulong)&_i386boot_realmode_size; /* size of realmode entry code */ +ulong i386boot_bios = (ulong)&_i386boot_bios; /* start of BIOS emulation code */ +ulong i386boot_bios_size = (ulong)&_i386boot_bios_size; /* size of BIOS emulation code */ + + +const char version_string[] = + U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"; + + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start = 0; +static ulong mem_malloc_end = 0; +static ulong mem_malloc_brk = 0; + +static int mem_malloc_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* start malloc area right after the stack */ + mem_malloc_start = i386boot_bss_start + + i386boot_bss_size + CFG_STACK_SIZE; + mem_malloc_start = (mem_malloc_start+3)&~3; + + /* Use all available RAM for malloc() */ + mem_malloc_end = gd->ram_size; + + mem_malloc_brk = mem_malloc_start; + + return 0; +} + +void *sbrk (ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) { + return (NULL); + } + mem_malloc_brk = new; + + return ((void *) old); +} + +char *strmhz (char *buf, long hz) +{ + long l, n; + long m; + + n = hz / 1000000L; + l = sprintf (buf, "%ld", n); + m = (hz % 1000000L) / 1000L; + if (m != 0) + sprintf (buf + l, ".%03ld", m); + return (buf); +} + +/************************************************************************ + * Init Utilities * + ************************************************************************ + * Some of this code should be moved into the core functions, + * or dropped completely, + * but let's get it working (again) first... + */ +static int init_baudrate (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + char tmp[64]; /* long enough for environment variables */ + int i = getenv_r("baudrate", tmp, 64); + + gd->baudrate = (i != 0) + ? (int) simple_strtoul (tmp, NULL, 10) + : CONFIG_BAUDRATE; + + return (0); +} + +static int display_banner (void) +{ + + printf ("\n\n%s\n\n", version_string); + printf ("U-Boot code: %08lX -> %08lX data: %08lX -> %08lX\n" + " BSS: %08lX -> %08lX stack: %08lX -> %08lX\n", + i386boot_start, i386boot_romdata_start-1, + i386boot_romdata_dest, i386boot_romdata_dest+i386boot_romdata_size-1, + i386boot_bss_start, i386boot_bss_start+i386boot_bss_size-1, + i386boot_bss_start+i386boot_bss_size, + i386boot_bss_start+i386boot_bss_size+CFG_STACK_SIZE-1); + + + return (0); +} + +/* + * WARNING: this code looks "cleaner" than the PowerPC version, but + * has the disadvantage that you either get nothing, or everything. + * On PowerPC, you might see "DRAM: " before the system hangs - which + * gives a simple yet clear indication which part of the + * initialization if failing. + */ +static int display_dram_config (void) +{ + DECLARE_GLOBAL_DATA_PTR; + int i; + + puts ("DRAM Configuration:\n"); + + for (i=0; ibd->bi_dram[i].start); + print_size (gd->bd->bi_dram[i].size, "\n"); + } + + return (0); +} + +static void display_flash_config (ulong size) +{ + puts ("Flash: "); + print_size (size, "\n"); +} + + +/* + * Breath some life into the board... + * + * Initialize an SMC for serial comms, and carry out some hardware + * tests. + * + * The first part of initialization is running from Flash memory; + * its main purpose is to initialize the RAM so that we + * can relocate the monitor code to RAM. + */ + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ +typedef int (init_fnc_t) (void); + +init_fnc_t *init_sequence[] = { + cpu_init, /* basic cpu dependent setup */ + board_init, /* basic board dependent setup */ + dram_init, /* configure available RAM banks */ + mem_malloc_init, /* dependant on dram_init */ + interrupt_init, /* set up exceptions */ + timer_init, + serial_init, + env_init, /* initialize environment */ + init_baudrate, /* initialze baudrate settings */ + serial_init, /* serial communications setup */ + display_banner, + display_dram_config, + + NULL, +}; + +gd_t *global_data; + +void start_i386boot (void) +{ + DECLARE_GLOBAL_DATA_PTR; + char *s; + int i; + ulong size; + static gd_t gd_data; + static bd_t bd_data; + init_fnc_t **init_fnc_ptr; + + show_boot_progress(0x21); + + gd = global_data = &gd_data; + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset (gd, 0, sizeof (gd_t)); + gd->bd = &bd_data; + memset (gd->bd, 0, sizeof (bd_t)); + show_boot_progress(0x22); + + gd->baudrate = CONFIG_BAUDRATE; + + for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) { + show_boot_progress(0xa130|i); + + if ((*init_fnc_ptr)() != 0) { + hang (); + } + } + show_boot_progress(0x23); + + /* configure available FLASH banks */ + size = flash_init(); + display_flash_config(size); + show_boot_progress(0x24); + + show_boot_progress(0x25); + + /* initialize environment */ + env_relocate (); + show_boot_progress(0x26); + + + /* IP Address */ + bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr"); + + /* MAC Address */ + { + int i; + ulong reg; + char *s, *e; + uchar tmp[64]; + + i = getenv_r ("ethaddr", tmp, sizeof (tmp)); + s = (i > 0) ? tmp : NULL; + + for (reg = 0; reg < 6; ++reg) { + bd_data.bi_enetaddr[reg] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + } + +#if defined(CONFIG_PCI) + /* + * Do pci configuration + */ + pci_init(); +#endif + + show_boot_progress(0x27); + + + devices_init (); + + jumptable_init (); + + /* Initialize the console (after the relocation and devices init) */ + console_init_r(); + +#ifdef CONFIG_MISC_INIT_R + /* miscellaneous platform dependent initialisations */ + misc_init_r(); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE) + WATCHDOG_RESET(); + puts ("PCMCIA:"); + pcmcia_init(); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + WATCHDOG_RESET(); + puts("KGDB: "); + kgdb_init(); +#endif + + /* enable exceptions */ + enable_interrupts(); + show_boot_progress(0x28); + + /* Must happen after interrupts are initialized since + * an irq handler gets installed + */ +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + serial_buffered_init(); +#endif + +#ifdef CONFIG_STATUS_LED + status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); +#endif + + udelay(20); + + set_timer (0); + + /* Initialize from environment */ + if ((s = getenv ("loadaddr")) != NULL) { + load_addr = simple_strtoul (s, NULL, 16); + } +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif /* CFG_CMD_NET */ + + WATCHDOG_RESET(); + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + WATCHDOG_RESET(); + puts("IDE: "); + ide_init(); +#endif /* CFG_CMD_IDE */ + +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + WATCHDOG_RESET(); + puts("SCSI: "); + scsi_init(); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) + WATCHDOG_RESET(); + puts("DOC: "); + doc_init(); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + WATCHDOG_RESET(); + puts("Net: "); +#endif + eth_initialize(gd->bd); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && (0) + WATCHDOG_RESET(); +# ifdef DEBUG + puts ("Reset Ethernet PHY\n"); +# endif + reset_phy(); +#endif + +#ifdef CONFIG_LAST_STAGE_INIT + WATCHDOG_RESET(); + /* + * Some parts can be only initialized if all others (like + * Interrupts) are up and running (i.e. the PC-style ISA + * keyboard). + */ + last_stage_init(); +#endif + + +#ifdef CONFIG_POST + post_run (NULL, POST_RAM | post_bootmode_get(0)); +#endif + + + show_boot_progress(0x29); + + /* main_loop() can return to retry autoboot, if so just run it again. */ + for (;;) { + main_loop(); + } + + /* NOTREACHED - no way out of command loop except booting */ +} + +void hang (void) +{ + puts ("### ERROR ### Please RESET the board ###\n"); + for (;;); +} diff --git a/lib_i386/i386_linux.c b/lib_i386/i386_linux.c new file mode 100644 index 0000000..e5d8eea --- /dev/null +++ b/lib_i386/i386_linux.c @@ -0,0 +1,173 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +/*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +extern image_header_t header; /* from cmd_bootm.c */ + + +image_header_t *fake_header(image_header_t *hdr, void *ptr, int size) +{ + /* try each supported image type in order */ + if (NULL != fake_zimage_header(hdr, ptr, size)) { + return hdr; + } + + return NULL; +} + + +void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + void *base_ptr; + + ulong len = 0, checksum; + ulong initrd_start, initrd_end; + ulong data; + image_header_t *hdr = &header; + + /* + * Check if there is an initrd image + */ + if (argc >= 3) { + addr = simple_strtoul(argv[2], NULL, 16); + + printf ("## Loading Ramdisk Image at %08lx ...\n", addr); + + /* Copy header so we can blank CRC field for re-calculation */ + memcpy (&header, (char *)addr, sizeof(image_header_t)); + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + printf ("Bad Magic Number\n"); + do_reset (cmdtp, flag, argc, argv); + } + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (char *)data, len) != checksum) { + printf ("Bad Header Checksum\n"); + do_reset (cmdtp, flag, argc, argv); + } + + print_image_hdr (hdr); + + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + if (verify) { + ulong csum = 0; + + printf (" Verifying Checksum ... "); + csum = crc32 (0, (char *)data, len); + if (csum != ntohl(hdr->ih_dcrc)) { + printf ("Bad Data CRC\n"); + do_reset (cmdtp, flag, argc, argv); + } + printf ("OK\n"); + } + + if ((hdr->ih_os != IH_OS_LINUX) || + (hdr->ih_arch != IH_CPU_I386) || + (hdr->ih_type != IH_TYPE_RAMDISK) ) { + printf ("No Linux i386 Ramdisk Image\n"); + do_reset (cmdtp, flag, argc, argv); + } + + /* + * Now check if we have a multifile image + */ + } else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) { + ulong tail = ntohl(len_ptr[0]) % 4; + int i; + + /* skip kernel length and terminator */ + data = (ulong)(&len_ptr[2]); + /* skip any additional image length fields */ + for (i=1; len_ptr[i]; ++i) + data += 4; + /* add kernel length, and align */ + data += ntohl(len_ptr[0]); + if (tail) { + data += 4 - tail; + } + + len = ntohl(len_ptr[1]); + + } else { + /* + * no initrd image + */ + data = 0; + } + +#ifdef DEBUG + if (!data) { + printf ("No initrd\n"); + } +#endif + + if (data) { + initrd_start = data; + initrd_end = initrd_start + len; + printf (" Loading Ramdisk to %08lx, end %08lx ... ", + initrd_start, initrd_end); + memmove ((void *)initrd_start, (void *)data, len); + printf ("OK\n"); + } else { + initrd_start = 0; + initrd_end = 0; + } + + base_ptr = load_zimage((void*)addr + sizeof(image_header_t), ntohl(hdr->ih_size), + initrd_start, initrd_end-initrd_start, 0); + + if (NULL == base_ptr) { + printf ("## Kernel loading failed ...\n"); + do_reset(cmdtp, flag, argc, argv); + + } + +#ifdef DEBUG + printf ("## Transferring control to Linux (at address %08x) ...\n", + (u32)base_ptr); +#endif + + /* we assume that the kernel is in place */ + printf("\nStarting kernel ...\n\n"); + + boot_zimage(base_ptr); + +} diff --git a/lib_i386/pci.c b/lib_i386/pci.c new file mode 100644 index 0000000..a7f16aa --- /dev/null +++ b/lib_i386/pci.c @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CONFIG_PCI +#undef PCI_ROM_SCAN_VERBOSE + +int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) +{ + struct pci_controller *hose; + int res = -1; + int i; + + u32 rom_addr; + u32 addr_reg; + u32 size; + + u16 vendor; + u16 device; + u32 class_code; + + hose = pci_bus_to_hose(PCI_BUS(dev)); +#if 0 + printf("pci_shadow_rom() asked to shadow device %x to %x\n", + dev, (u32)dest); +#endif + pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); + pci_read_config_word(dev, PCI_DEVICE_ID, &device); + pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_code); + + class_code &= 0xffffff00; + class_code >>= 8; + +#if 0 + printf("PCI Header Vendor %04x device %04x class %06x\n", + vendor, device, class_code); +#endif + /* Enable the rom addess decoder */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK); + pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr_reg); + + if (!addr_reg) { + /* register unimplemented */ + printf("pci_chadow_rom: device do not seem to have a rom\n"); + return -1; + } + + size = (~(addr_reg&PCI_ROM_ADDRESS_MASK))+1; + +#if 0 + printf("ROM is %d bytes\n", size); +#endif + rom_addr = pci_get_rom_window(hose, size); +#if 0 + printf("ROM mapped at %x \n", rom_addr); +#endif + pci_write_config_dword(dev, PCI_ROM_ADDRESS, + pci_phys_to_mem(dev, rom_addr) + |PCI_ROM_ADDRESS_ENABLE); + + + for (i=rom_addr;i + +#ifdef CONFIG_PCI + +#include +#include + +#define cfg_read(val, addr, op) *val = op((int)(addr)) +#define cfg_write(val, addr, op) op((val), (int)(addr)) + +#define TYPE1_PCI_OP(rw, size, type, op, mask) \ +static int \ +type1_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), op); \ + return 0; \ +} + + +TYPE1_PCI_OP(read, byte, u8 *, inb, 3) +TYPE1_PCI_OP(read, word, u16 *, inw, 2) +TYPE1_PCI_OP(read, dword, u32 *, inl, 0) + +TYPE1_PCI_OP(write, byte, u8, outb, 3) +TYPE1_PCI_OP(write, word, u16, outw, 2) +TYPE1_PCI_OP(write, dword, u32, outl, 0) + +void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) +{ + pci_set_ops(hose, + type1_read_config_byte, + type1_read_config_word, + type1_read_config_dword, + type1_write_config_byte, + type1_write_config_word, + type1_write_config_dword); + + hose->cfg_addr = (unsigned int *) cfg_addr; + hose->cfg_data = (unsigned char *) cfg_data; +} + +#endif diff --git a/lib_i386/realmode.c b/lib_i386/realmode.c new file mode 100644 index 0000000..6cf2738 --- /dev/null +++ b/lib_i386/realmode.c @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +#define REALMODE_BASE ((char*)0x7c0) +#define REALMODE_MAILBOX ((char*)0xe00) + + +extern char realmode_enter; + +int realmode_setup(void) +{ + /* copy the realmode switch code */ + if (i386boot_realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) { + printf("realmode switch too large (%ld bytes, max is %d)\n", + i386boot_realmode_size, (REALMODE_MAILBOX-REALMODE_BASE)); + return -1; + } + + memcpy(REALMODE_BASE, (void*)i386boot_realmode, i386boot_realmode_size); + asm("wbinvd\n"); + + return 0; +} + +int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out) +{ + + /* setup out thin bios emulation */ + if (bios_setup()) { + return -1; + } + + if (realmode_setup()) { + return -1; + } + + in->eip = off; + in->xcs = seg; + if (3>(in->esp & 0xffff)) { + printf("Warning: entering realmode with sp < 4 will fail\n"); + } + + memcpy(REALMODE_MAILBOX, in, sizeof(struct pt_regs)); + asm("wbinvd\n"); + + __asm__ volatile ( + "lcall $0x20,%0\n" : : "i" (&realmode_enter) ); + + asm("wbinvd\n"); + memcpy(out, REALMODE_MAILBOX, sizeof(struct pt_regs)); + + return out->eax; +} + + +/* This code is supposed to access a realmode interrupt + * it does currently not work for me */ +int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out) +{ + /* place two instructions at 0x700 */ + writeb(0xcd, 0x700); /* int $lvl */ + writeb(lvl, 0x701); + writeb(0xcb, 0x702); /* lret */ + asm("wbinvd\n"); + + enter_realmode(0x00, 0x700, in, out); + + return out->eflags&1; +} diff --git a/lib_i386/realmode_switch.S b/lib_i386/realmode_switch.S new file mode 100644 index 0000000..0433cd4 --- /dev/null +++ b/lib_i386/realmode_switch.S @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +/* 32bit -> 16bit -> 32bit mode switch code */ + +/* + * Stack frame at 0xe00 + * e00 ebx; + * e04 ecx; + * e08 edx; + * e0c esi; + * e10 edi; + * e14 ebp; + * e18 eax; + * e1c ds; + * e20 es; + * e24 fs; + * e28 gs; + * e2c orig_eax; + * e30 eip; + * e34 cs; + * e38 eflags; + * e3c esp; + * e40 ss; + */ + +#define a32 .byte 0x67; /* address size prefix 32 */ +#define o32 .byte 0x66; /* operand size prefix 32 */ + +.section .realmode, "ax" +.code16 + /* 16bit protected mode code here */ +.globl realmode_enter +realmode_enter: +o32 pusha +o32 pushf + cli + sidt saved_idt + sgdt saved_gdt + movl %esp, %eax + movl %eax, saved_protected_mode_esp + + movl $0x10, %eax + movl %eax, %esp + movw $0x28, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %fs + movw %ax, %gs + + lidt realmode_idt_ptr + movl %cr0, %eax /* Go back into real mode by */ + andl $0x7ffffffe, %eax /* clearing PE to 0 */ + movl %eax, %cr0 + ljmp $0x0,$do_realmode /* switch to real mode */ + +do_realmode: /* realmode code from here */ + movw %cs,%ax + movw %ax,%ds + movw %ax,%es + movw %ax,%fs + movw %ax,%gs + + /* create a temporary stack */ + + movw $0xc0, %ax + movw %ax, %ss + movw $0x200, %ax + movw %ax, %sp + + popl %ebx + popl %ecx + popl %edx + popl %esi + popl %edi + popl %ebp + popl %eax + movl %eax, temp_eax + popl %eax + movw %ax, %ds + popl %eax + movw %ax, %es + popl %eax + movw %ax, %fs + popl %eax + movw %ax, %gs + popl %eax /* orig_eax */ + popl %eax +cs movw %ax, temp_ip + popl %eax +cs movw %ax, temp_cs +o32 popf + popl %eax + popw %ss + movl %eax, %esp +cs movl temp_eax, %eax + wbinvd /* self-modifying code, + * better flush the cache */ + + .byte 0x9a /* lcall */ +temp_ip: + .word 0 /* new ip */ +temp_cs: + .word 0 /* new cs */ +realmode_ret: + /* save eax, esp and ss */ +cs movl %eax, saved_eax + movl %esp, %eax +cs movl %eax, saved_esp + movw %ss, %ax +cs movw %ax, saved_ss + + /* restore the stack, note that we set sp to 0x244; + * pt_regs is 0x44 bytes long and we push the structure + * backwards on to the stack, bottom first */ + + movw $0xc0, %ax + movw %ax, %ss + movw $0x244, %ax + movw %ax, %sp + + xorl %eax,%eax +cs movw saved_ss, %ax + pushl %eax +cs movl saved_esp, %eax + pushl %eax +o32 pushf + xorl %eax,%eax +cs movw temp_cs, %ax + pushl %eax +cs movw temp_ip, %ax + pushl %eax + pushl $0 + movw %gs, %ax + pushl %eax + movw %fs, %ax + pushl %eax + movw %es, %ax + pushl %eax + movw %ds, %ax + pushl %eax + movl saved_eax, %eax + pushl %eax + pushl %ebp + pushl %edi + pushl %esi + pushl %edx + pushl %ecx + pushl %ebx + +o32 cs lidt saved_idt +o32 cs lgdt saved_gdt /* Set GDTR */ + + movl %cr0, %eax /* Go back into protected mode */ + orl $1,%eax /* reset PE to 1 */ + movl %eax, %cr0 + jmp next_line /* flush prefetch queue */ +next_line: + movw $return_ptr, %ax + movw %ax,%bp +o32 cs ljmp *(%bp) + +.code32 +protected_mode: + movl $0x18,%eax /* reload GDT[3] */ + movw %ax,%fs /* reset FS */ + movw %ax,%ds /* reset DS */ + movw %ax,%gs /* reset GS */ + movw %ax,%es /* reset ES */ + movw %ax,%ss /* reset SS */ + movl saved_protected_mode_esp, %eax + movl %eax, %esp + popf + popa + ret + +temp_eax: + .long 0 + +saved_ss: + .word 0 +saved_esp: + .long 0 +saved_eax: + .long 0 + +realmode_idt_ptr: + .word 0x400 + .word 0x0, 0x0 + +saved_gdt: + .word 0, 0, 0, 0 +saved_idt: + .word 0, 0, 0, 0 + +saved_protected_mode_esp: + .long 0 + +return_ptr: + .long protected_mode + .word 0x10 diff --git a/lib_i386/video.c b/lib_i386/video.c new file mode 100644 index 0000000..cd89457 --- /dev/null +++ b/lib_i386/video.c @@ -0,0 +1,237 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* basic textmode I/O from linux kernel */ +static char *vidmem = (char *)0xb8000; +static int vidport; +static int lines, cols; +static int orig_x, orig_y; + +static void beep(int dur) +{ + int i; + + outb_p(3, 0x61); + for (i=0;i<10*dur;i++) { + udelay(1000); + } + outb_p(0, 0x61); +} + +static void scroll(void) +{ + int i; + + memcpy ( vidmem, vidmem + cols * 2, ( lines - 1 ) * cols * 2 ); + for ( i = ( lines - 1 ) * cols * 2; i < lines * cols * 2; i += 2 ) + vidmem[i] = ' '; +} + +static void __video_putc(const char c, int *x, int *y) +{ + if (c == '\n') { + (*x) = 0; + if ( ++(*y) >= lines ) { + scroll(); + (*y)--; + } + } else if (c == '\b') { + if ((*x) != 0) { + --(*x); + vidmem [ ( (*x) + cols * (*y) ) * 2 ] = ' '; + } + } else if (c == '\r') { + (*x) = 0; + + } else if (c == '\a') { + beep(3); + + } else if (c == '\t') { + __video_putc(' ', x, y); + __video_putc(' ', x, y); + __video_putc(' ', x, y); + __video_putc(' ', x, y); + __video_putc(' ', x, y); + __video_putc(' ', x, y); + __video_putc(' ', x, y); + __video_putc(' ', x, y); + } else if (c == '\v') { + switch ((*x) % 8) { + case 0: + __video_putc(' ', x, y); + case 7: + __video_putc(' ', x, y); + case 6: + __video_putc(' ', x, y); + case 5: + __video_putc(' ', x, y); + case 4: + __video_putc(' ', x, y); + case 3: + __video_putc(' ', x, y); + case 2: + __video_putc(' ', x, y); + case 1: + __video_putc(' ', x, y); + } + } else if (c == '\f') { + int i; + for (i=0;i= cols ) { + (*x) = 0; + if ( ++(*y) >= lines ) { + scroll(); + (*y)--; + } + } + } +} + +static void video_putc(const char c) +{ + int x,y,pos; + + x = orig_x; + y = orig_y; + + __video_putc(c, &x, &y); + + orig_x = x; + orig_y = y; + + pos = (x + cols * y) * 2; /* Update cursor position */ + outb_p(14, vidport); + outb_p(0xff & (pos >> 9), vidport+1); + outb_p(15, vidport); + outb_p(0xff & (pos >> 1), vidport+1); +} + +static void video_puts(const char *s) +{ + int x,y,pos; + char c; + + x = orig_x; + y = orig_y; + + while ( ( c = *s++ ) != '\0' ) { + __video_putc(c, &x, &y); + } + + orig_x = x; + orig_y = y; + + pos = (x + cols * y) * 2; /* Update cursor position */ + outb_p(14, vidport); + outb_p(0xff & (pos >> 9), vidport+1); + outb_p(15, vidport); + outb_p(0xff & (pos >> 1), vidport+1); +} + +int video_init(void) +{ + u16 pos; + + static device_t vga_dev; + static device_t kbd_dev; + + vidmem = (char *) 0xb8000; + vidport = 0x3d4; + + lines = 25; + cols = 80; + + outb_p(14, vidport); + pos = inb_p(vidport+1); + pos <<= 8; + outb_p(15, vidport); + pos |= inb_p(vidport+1); + + orig_x = pos%cols; + orig_y = pos/cols; + +#if 0 + printf("pos %x %d %d\n", pos, orig_x, orig_y); +#endif + if (orig_y > lines) { + orig_x = orig_y =0; + } + + + memset(&vga_dev, 0, sizeof(vga_dev)); + strcpy(vga_dev.name, "vga"); + vga_dev.ext = 0; + vga_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; + vga_dev.putc = video_putc; /* 'putc' function */ + vga_dev.puts = video_puts; /* 'puts' function */ + vga_dev.tstc = NULL; /* 'tstc' function */ + vga_dev.getc = NULL; /* 'getc' function */ + + if (device_register(&vga_dev) == 0) { + return 1; + } + + if (i8042_kbd_init()) { + return 1; + } + + memset(&kbd_dev, 0, sizeof(kbd_dev)); + strcpy(kbd_dev.name, "kbd"); + kbd_dev.ext = 0; + kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbd_dev.putc = NULL; /* 'putc' function */ + kbd_dev.puts = NULL; /* 'puts' function */ + kbd_dev.tstc = i8042_tstc; /* 'tstc' function */ + kbd_dev.getc = i8042_getc; /* 'getc' function */ + + if (device_register(&kbd_dev) == 0) { + return 1; + } + return 0; +} + + +int drv_video_init(void) +{ + if (video_bios_init()) { + return 1; + } + + return video_init(); +} diff --git a/lib_i386/video_bios.c b/lib_i386/video_bios.c new file mode 100644 index 0000000..45f78e2 --- /dev/null +++ b/lib_i386/video_bios.c @@ -0,0 +1,219 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#undef PCI_BIOS_DEBUG +#undef VGA_BIOS_DEBUG + +#ifdef VGA_BIOS_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#ifdef CONFIG_PCI + +#ifdef PCI_BIOS_DEBUG +#define RELOC_16(seg, off) *(u32*)(seg << 4 | (u32)&off) +extern u32 num_pci_bios_present; +extern u32 num_pci_bios_find_device; +extern u32 num_pci_bios_find_class; +extern u32 num_pci_bios_generate_special_cycle; +extern u32 num_pci_bios_read_cfg_byte; +extern u32 num_pci_bios_read_cfg_word; +extern u32 num_pci_bios_read_cfg_dword; +extern u32 num_pci_bios_write_cfg_byte; +extern u32 num_pci_bios_write_cfg_word; +extern u32 num_pci_bios_write_cfg_dword; +extern u32 num_pci_bios_get_irq_routing; +extern u32 num_pci_bios_set_irq; +extern u32 num_pci_bios_unknown_function; + +void print_bios_bios_stat(void) +{ + printf("16 bit functions:\n"); + printf("pci_bios_present: %d\n", RELOC_16(0xf000, num_pci_bios_present)); + printf("pci_bios_find_device: %d\n", RELOC_16(0xf000, num_pci_bios_find_device)); + printf("pci_bios_find_class: %d\n", RELOC_16(0xf000, num_pci_bios_find_class)); + printf("pci_bios_generate_special_cycle: %d\n", RELOC_16(0xf000, num_pci_bios_generate_special_cycle)); + printf("pci_bios_read_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_byte)); + printf("pci_bios_read_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_word)); + printf("pci_bios_read_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_dword)); + printf("pci_bios_write_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_byte)); + printf("pci_bios_write_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_word)); + printf("pci_bios_write_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_dword)); + printf("pci_bios_get_irq_routing: %d\n", RELOC_16(0xf000, num_pci_bios_get_irq_routing)); + printf("pci_bios_set_irq: %d\n", RELOC_16(0xf000, num_pci_bios_set_irq)); + printf("pci_bios_unknown_function: %d\n", RELOC_16(0xf000, num_pci_bios_unknown_function)); + +} +#endif + +#define PCI_CLASS_VIDEO 3 +#define PCI_CLASS_VIDEO_STD 0 +#define PCI_CLASS_VIDEO_PROG_IF_VGA 0 + + +static u32 probe_pci_video(void) +{ + pci_dev_t devbusfn; + + if ((devbusfn = pci_find_class(PCI_CLASS_VIDEO, + PCI_CLASS_VIDEO_STD, + PCI_CLASS_VIDEO_PROG_IF_VGA, 0)) != -1) { + u32 old; + u32 addr; + + /* PCI video device detected */ + printf("Found PCI VGA device at %02x.%02x.%x\n", + PCI_BUS(devbusfn), PCI_DEV(devbusfn), PCI_FUNC(devbusfn)); + + /* Enable I/O decoding as well, PCI viudeo boards + * support I/O accesses, but they provide no + * bar register for this since the ports are fixed. + */ + pci_write_config_word(devbusfn, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER); + + /* Test the ROM decoder, do the device support a rom? */ + pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old); + pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK); + pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr); + pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old); + + if (!addr) { + printf("PCI VGA have no ROM?\n"); + return 0; + } + + /* device have a rom */ + if (pci_shadow_rom(devbusfn, (void*)0xc0000)) { + printf("Shadowing of PCI VGA BIOS failed\n"); + return 0; + } + + /* Now enable lagacy VGA port access */ + if (pci_enable_legacy_video_ports(pci_bus_to_hose(PCI_BUS(devbusfn)))) { + printf("PCI VGA enable failed\n"); + return 0; + } + + + /* return the pci device info, that we'll need later */ + return PCI_BUS(devbusfn) << 8 | + PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn)&7); + } + + return 0; +} + + +#endif + +static int probe_isa_video(void) +{ + u32 ptr; + char *buf; + + if (0 == (ptr = isa_map_rom(0xc0000, 0x8000))) { + return -1; + } + if (NULL == (buf=malloc(0x8000))) { + isa_unmap_rom(ptr); + return -1; + } + if (readw(ptr) != 0xaa55) { + free(buf); + isa_unmap_rom(ptr); + return -1; + } + + /* shadow the rom */ + memcpy(buf, (void*)ptr, 0x8000); + isa_unmap_rom(ptr); + memcpy((void*)0xc0000, buf, 0x8000); + + free(buf); + + return 0; +} + +int video_bios_init(void) +{ + struct pt_regs regs; + + /* clear the video bios area in case we warmbooted */ + memset((void*)0xc0000, 0, 0x8000); + memset(®s, 0, sizeof(struct pt_regs)); + + if (probe_isa_video()) { + /* No ISA board found, try the PCI bus */ + regs.eax = probe_pci_video(); + } + + /* Did we succeed in mapping any video bios */ + if (readw(0xc0000) == 0xaa55) { + int size; + int i; + u8 sum; + + PRINTF("Found video bios signature\n"); + size = 512*readb(0xc0002); + PRINTF("size %d\n", size); + sum=0; + for (i=0;i +#include +#include +#include +#include +#include + +/* + * Memory lay-out: + * + * relative to setup_base (which is 0x90000 currently) + * + * 0x0000-0x7FFF Real mode kernel + * 0x8000-0x8FFF Stack and heap + * 0x9000-0x90FF Kernel command line + */ +#define DEFAULT_SETUP_BASE 0x90000 +#define COMMAND_LINE_OFFSET 0x9000 +#define HEAP_END_OFFSET 0x8e00 + +#define COMMAND_LINE_SIZE 2048 + +static void build_command_line(char *command_line, int auto_boot) +{ + char *env_command_line; + + command_line[0] = '\0'; + + env_command_line = getenv("bootargs"); + + /* set console= argument if we use a serial console */ + if (NULL == strstr(env_command_line, "console=")) { + if (0==strcmp(getenv("stdout"), "serial")) { + + /* We seem to use serial console */ + sprintf(command_line, "console=ttyS0,%s ", + getenv("baudrate")); + } + } + + if (auto_boot) { + strcat(command_line, "auto "); + } + + if (NULL != env_command_line) { + strcat(command_line, env_command_line); + } + + + printf("Kernel command line: \"%s\"\n", command_line); +} + +void *load_zimage(char *image, unsigned long kernel_size, + unsigned long initrd_addr, unsigned long initrd_size, + int auto_boot) +{ + void *setup_base; + int setup_size; + int bootproto; + int big_image; + void *load_address; + + + setup_base = (void*)DEFAULT_SETUP_BASE; /* base address for real-mode segment */ + + if (KERNEL_MAGIC != *(u16*)(image + BOOT_FLAG_OFF)) { + printf("Error: Invalid kernel magic (found 0x%04x, expected 0xaa55)\n", + *(u16*)(image + BOOT_FLAG_OFF)); + return 0; + } + + + /* determine boot protocol version */ + if (KERNEL_V2_MAGIC == *(u32*)(image+HEADER_OFF)) { + bootproto = *(u16*)(image+VERSION_OFF); + } else { + /* Very old kernel */ + bootproto = 0x0100; + } + + /* determine size of setup */ + if (0 == *(u8*)(image + SETUP_SECTS_OFF)) { + setup_size = 5 * 512; + } else { + setup_size = (*(u8*)(image + SETUP_SECTS_OFF) + 1) * 512; + } + + if (setup_size > SETUP_MAX_SIZE) { + printf("Error: Setup is too large (%d bytes)\n", setup_size); + } + + /* Determine image type */ + big_image = (bootproto >= 0x0200) && (*(u8*)(image + LOADFLAGS_OFF) & BIG_KERNEL_FLAG); + + /* Derermine load address */ + load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR:ZIMAGE_LOAD_ADDR); + + /* load setup */ + memmove(setup_base, image, setup_size); + + printf("Using boot protocol version %x.%02x\n", + (bootproto & 0xff00) >> 8, bootproto & 0xff); + + + if (bootproto == 0x0100) { + + *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; + *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; + + /* A very old kernel MUST have its real-mode code + * loaded at 0x90000 */ + + if ((u32)setup_base != 0x90000) { + /* Copy the real-mode kernel */ + memmove((void*)0x90000, setup_base, setup_size); + /* Copy the command line */ + memmove((void*)0x99000, setup_base+COMMAND_LINE_OFFSET, + COMMAND_LINE_SIZE); + + setup_base = (void*)0x90000; /* Relocated */ + } + + /* It is recommended to clear memory up to the 32K mark */ + memset((void*)0x90000 + setup_size, 0, SETUP_MAX_SIZE-setup_size); + } + + if (bootproto >= 0x0200) { + *(u8*)(setup_base + TYPE_OF_LOADER_OFF) = 0xff; + printf("Linux kernel version %s\n", + (char*)(setup_base + SETUP_START_OFFSET + + *(u16*)(setup_base + START_SYS_OFF + 2))); + + if (initrd_addr) { + printf("Initial RAM disk at linear address 0x%08lx, size %ld bytes\n", + initrd_addr, initrd_size); + + *(u32*)(setup_base + RAMDISK_IMAGE_OFF) = initrd_addr; + *(u32*)(setup_base + RAMDISK_SIZE_OFF)=initrd_size; + } + } + + if (bootproto >= 0x0201) { + *(u16*)(setup_base + HEAP_END_PTR_OFF) = HEAP_END_OFFSET; + + /* CAN_USE_HEAP */ + *(u8*)(setup_base + LOADFLAGS_OFF) = + *(u8*)(setup_base + LOADFLAGS_OFF) | HEAP_FLAG; + } + + if (bootproto >= 0x0202) { + *(u32*)(setup_base + CMD_LINE_PTR_OFF) = (u32)setup_base + COMMAND_LINE_OFFSET; + } else if (bootproto >= 0x0200) { + *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; + *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; + *(u16*)(setup_base + SETUP_MOVE_SIZE_OFF) = 0x9100; + } + + + if (big_image) { + if ((kernel_size - setup_size) > BZIMAGE_MAX_SIZE) { + printf("Error: bzImage kernel too big! (size: %ld, max: %d)\n", + kernel_size - setup_size, BZIMAGE_MAX_SIZE); + return 0; + } + + } else if ((kernel_size - setup_size) > ZIMAGE_MAX_SIZE) { + printf("Error: zImage kernel too big! (size: %ld, max: %d)\n", + kernel_size - setup_size, ZIMAGE_MAX_SIZE); + return 0; + } + + /* build command line at COMMAND_LINE_OFFSET */ + build_command_line(setup_base + COMMAND_LINE_OFFSET, auto_boot); + + printf("Loading %czImage at address 0x%08x (%ld bytes)\n", big_image ? 'b' : ' ', + (u32)load_address, kernel_size - setup_size); + + + memmove(load_address, image + setup_size, kernel_size - setup_size); + + /* ready for booting */ + return setup_base; +} + + +void boot_zimage(void *setup_base) +{ + struct pt_regs regs; + + memset(®s, 0, sizeof(struct pt_regs)); + regs.xds = (u32)setup_base >> 4; + regs.xss = 0x9000; + regs.esp = 0x9000; + regs.eflags = 0; + enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s, ®s); +} + + +image_header_t *fake_zimage_header(image_header_t *hdr, void *ptr, int size) +{ + /* There is no way to know the size of a zImage ... * + * so we assume that 2MB will be enough for now */ +#define ZIMAGE_SIZE 0x200000 + + /* load a 1MB, the loaded will have to be moved to its final + * position again later... */ +#define ZIMAGE_LOAD 0x100000 + + ulong checksum; + + if (KERNEL_MAGIC != *(u16*)(ptr + BOOT_FLAG_OFF)) { + /* not a zImage or bzImage */ + return NULL; + } + + if (-1 == size) { + size = ZIMAGE_SIZE; + } +#if 0 + checksum = crc32 (0, ptr, size); +#else + checksum = 0; +#endif + memset(hdr, 0, sizeof(image_header_t)); + + /* Build new header */ + hdr->ih_magic = htonl(IH_MAGIC); + hdr->ih_time = 0; + hdr->ih_size = htonl(size); + hdr->ih_load = htonl(ZIMAGE_LOAD); + hdr->ih_ep = 0; + hdr->ih_dcrc = htonl(checksum); + hdr->ih_os = IH_OS_LINUX; + hdr->ih_arch = IH_CPU_I386; + hdr->ih_type = IH_TYPE_KERNEL; + hdr->ih_comp = IH_COMP_NONE; + + strncpy((char *)hdr->ih_name, "(none)", IH_NMLEN); + + checksum = crc32(0,(const char *)hdr,sizeof(image_header_t)); + + hdr->ih_hcrc = htonl(checksum); + + return hdr; +} diff --git a/lib_m68k/Makefile b/lib_m68k/Makefile new file mode 100644 index 0000000..698da36 --- /dev/null +++ b/lib_m68k/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = +COBJS = cache.o traps.o time.o board.o m68k_linux.o +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_m68k/board.c b/lib_m68k/board.c new file mode 100644 index 0000000..6b3edd6 --- /dev/null +++ b/lib_m68k/board.c @@ -0,0 +1,730 @@ +/* + * (C) Copyright 2003 + * Josef Baumgartner + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_M5272 +#include +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#include +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) +#include +#endif +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#include +#endif +#ifdef CONFIG_STATUS_LED +#include +#endif +#include +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#include +#endif +#ifdef CFG_ALLOC_DPRAM +#include +#endif +#include + +#if defined(CONFIG_HARD_I2C) || \ + defined(CONFIG_SOFT_I2C) +#include +#endif + +static char *failed = "*** failed ***\n"; + +#ifdef CONFIG_PCU_E +extern flash_info_t flash_info[]; +#endif + +#include + +#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ + (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ + defined(CFG_ENV_IS_IN_NVRAM) +#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) +#else +#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN +#endif + +extern ulong __init_end; +extern ulong _end; + +extern void timer_init(void); + +#if defined(CONFIG_WATCHDOG) +# define INIT_FUNC_WATCHDOG_INIT watchdog_init, +# define WATCHDOG_DISABLE watchdog_disable + +extern int watchdog_init(void); +extern int watchdog_disable(void); +#else +# define INIT_FUNC_WATCHDOG_INIT /* undef */ +# define WATCHDOG_DISABLE /* undef */ +#endif /* CONFIG_WATCHDOG */ + +ulong monitor_flash_len; + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start = 0; +static ulong mem_malloc_end = 0; +static ulong mem_malloc_brk = 0; + +/************************************************************************ + * Utilities * + ************************************************************************ + */ + +/* + * The Malloc area is immediately below the monitor copy in DRAM + */ +static void mem_malloc_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off; + + mem_malloc_end = dest_addr; + mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + + memset ((void *) mem_malloc_start, + 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk (ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || + (new > mem_malloc_end) ) { + return (NULL); + } + mem_malloc_brk = new; + return ((void *)old); +} + +char *strmhz(char *buf, long hz) +{ + long l, n; + long m; + + n = hz / 1000000L; + + l = sprintf (buf, "%ld", n); + + m = (hz % 1000000L) / 1000L; + + if (m != 0) + sprintf (buf+l, ".%03ld", m); + + return (buf); +} + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ +typedef int (init_fnc_t) (void); + +/************************************************************************ + * Init Utilities * + ************************************************************************ + * Some of this code should be moved into the core functions, + * but let's get it working (again) first... + */ + +static int init_baudrate (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uchar tmp[64]; /* long enough for environment variables */ + int i = getenv_r ("baudrate", tmp, sizeof (tmp)); + + gd->baudrate = (i > 0) + ? (int) simple_strtoul (tmp, NULL, 10) + : CONFIG_BAUDRATE; + return (0); +} + +/***********************************************************************/ + +static int init_func_ram (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int board_type = 0; /* use dummy arg */ + puts ("DRAM: "); + + if ((gd->ram_size = initdram (board_type)) > 0) { + print_size (gd->ram_size, "\n"); + return (0); + } + puts (failed); + return (1); +} + +/***********************************************************************/ + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +static int init_func_i2c (void) +{ + puts ("I2C: "); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + puts ("ready\n"); + return (0); +} +#endif + +/***********************************************************************/ + +/************************************************************************ + * Initialization sequence * + ************************************************************************ + */ + +init_fnc_t *init_sequence[] = { + env_init, + init_baudrate, + serial_init, + console_init_f, + display_options, + checkcpu, + checkboard, +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + init_func_i2c, +#endif + init_func_ram, +#if defined(CFG_DRAM_TEST) + testdram, +#endif /* CFG_DRAM_TEST */ + INIT_FUNC_WATCHDOG_INIT + NULL, /* Terminate this list */ +}; + + +/************************************************************************ + * + * This is the first part of the initialization sequence that is + * implemented in C, but still running from ROM. + * + * The main purpose is to provide a (serial) console interface as + * soon as possible (so we can see any error messages), and to + * initialize the RAM so that we can relocate the monitor code to + * RAM. + * + * Be aware of the restrictions: global data is read-only, BSS is not + * initialized, and stack space is limited to a few kB. + * + ************************************************************************ + */ + +void +board_init_f (ulong bootflag) +{ + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd; + ulong len, addr, addr_sp; + gd_t *id; + init_fnc_t **init_fnc_ptr; +#ifdef CONFIG_PRAM + int i; + ulong reg; + uchar tmp[64]; /* long enough for environment variables */ +#endif + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) { + hang (); + } + } + + /* + * Now that we have DRAM mapped and working, we can + * relocate the code and continue running from DRAM. + * + * Reserve memory at end of RAM for (top down in that order): + * - protected RAM + * - LCD framebuffer + * - monitor code + * - board info struct + */ + len = (ulong)&_end - CFG_MONITOR_BASE; + + addr = CFG_SDRAM_BASE + gd->ram_size; + +#ifdef CONFIG_LOGBUFFER + /* reserve kernel log buffer */ + addr -= (LOGBUFF_RESERVE); + debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); +#endif + +#ifdef CONFIG_PRAM + /* + * reserve protected RAM + */ + i = getenv_r ("pram", tmp, sizeof (tmp)); + reg = (i > 0) ? simple_strtoul (tmp, NULL, 10) : CONFIG_PRAM; + addr -= (reg << 10); /* size is in kB */ + debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); +#endif /* CONFIG_PRAM */ + + /* + * reserve memory for U-Boot code, data & bss + * round down to next 4 kB limit + */ + addr -= len; + addr &= ~(4096 - 1); + + debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); + + /* + * reserve memory for malloc() arena + */ + addr_sp = addr - TOTAL_MALLOC_LEN; + debug ("Reserving %dk for malloc() at: %08lx\n", + TOTAL_MALLOC_LEN >> 10, addr_sp); + + /* + * (permanently) allocate a Board Info struct + * and a permanent copy of the "global" data + */ + addr_sp -= sizeof (bd_t); + bd = (bd_t *) addr_sp; + gd->bd = bd; + debug ("Reserving %d Bytes for Board Info at: %08lx\n", + sizeof (bd_t), addr_sp); + addr_sp -= sizeof (gd_t); + id = (gd_t *) addr_sp; + debug ("Reserving %d Bytes for Global Data at: %08lx\n", + sizeof (gd_t), addr_sp); + + /* Reserve memory for boot params. */ + addr_sp -= CFG_BOOTPARAMS_LEN; + bd->bi_boot_params = addr_sp; + debug ("Reserving %dk for boot parameters at: %08lx\n", + CFG_BOOTPARAMS_LEN >> 10, addr_sp); + + /* + * Finally, we set up a new (bigger) stack. + * + * Leave some safety gap for SP, force alignment on 16 byte boundary + * Clear initial stack frame + */ + addr_sp -= 16; + addr_sp &= ~0xF; + *((ulong *) addr_sp)-- = 0; + *((ulong *) addr_sp)-- = 0; + debug ("Stack Pointer at: %08lx\n", addr_sp); + + /* + * Save local variables to board info struct + */ + bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ + bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ + bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ + + bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ + + WATCHDOG_RESET (); + bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ + bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ + bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ + +#ifdef CFG_EXTBDINFO + strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); + strncpy (bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version)); +#endif + + WATCHDOG_RESET (); + +#ifdef CONFIG_POST + post_bootmode_init(); + post_run (NULL, POST_ROM | post_bootmode_get(0)); +#endif + + WATCHDOG_RESET(); + + memcpy (id, (void *)gd, sizeof (gd_t)); + + debug ("Start relocate of code from %08x to %08lx\n", CFG_MONITOR_BASE, addr); + relocate_code (addr_sp, id, addr); + + /* NOTREACHED - jump_to_ram() does not return */ +} + +/************************************************************************ + * + * This is the next part if the initialization sequence: we are now + * running from RAM and have a "normal" C environment, i. e. global + * data can be written, BSS has been cleared, the stack size in not + * that critical any more, etc. + * + ************************************************************************ + */ +void board_init_r (gd_t *id, ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + cmd_tbl_t *cmdtp; + char *s, *e; + bd_t *bd; + int i; + extern void malloc_bin_reloc (void); + +#ifndef CFG_ENV_IS_NOWHERE + extern char * env_name_spec; +#endif +#ifndef CFG_NO_FLASH + ulong flash_size; +#endif + gd = id; /* initialize RAM version of global data */ + bd = gd->bd; + + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + + debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); + + WATCHDOG_RESET (); + + gd->reloc_off = dest_addr - CFG_MONITOR_BASE; + + monitor_flash_len = (ulong)&__init_end - dest_addr; + + /* + * We have to relocate the command table manually + */ + for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + ulong addr; + addr = (ulong) (cmdtp->cmd) + gd->reloc_off; +#if 0 + printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", + cmdtp->name, (ulong) (cmdtp->cmd), addr); +#endif + cmdtp->cmd = + (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; + + addr = (ulong)(cmdtp->name) + gd->reloc_off; + cmdtp->name = (char *)addr; + + if (cmdtp->usage) { + addr = (ulong)(cmdtp->usage) + gd->reloc_off; + cmdtp->usage = (char *)addr; + } +#ifdef CFG_LONGHELP + if (cmdtp->help) { + addr = (ulong)(cmdtp->help) + gd->reloc_off; + cmdtp->help = (char *)addr; + } +#endif + } + /* there are some other pointer constants we must deal with */ +#ifndef CFG_ENV_IS_NOWHERE + env_name_spec += gd->reloc_off; +#endif + + WATCHDOG_RESET (); + +#ifdef CONFIG_LOGBUFFER + logbuff_init_ptrs (); +#endif +#ifdef CONFIG_POST + post_output_backlog (); + post_reloc (); +#endif + WATCHDOG_RESET(); + +#if 0 + /* instruction cache enabled in cpu_init_f() for faster relocation */ + icache_enable (); /* it's time to enable the instruction cache */ +#endif + + /* + * Setup trap handlers + */ + trap_init (0); + +#if !defined(CFG_NO_FLASH) + puts ("FLASH: "); + + if ((flash_size = flash_init ()) > 0) { +# ifdef CFG_FLASH_CHECKSUM + print_size (flash_size, ""); + /* + * Compute and print flash CRC if flashchecksum is set to 'y' + * + * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX + */ + s = getenv ("flashchecksum"); + if (s && (*s == 'y')) { + printf (" CRC: %08lX", + crc32 (0, + (const unsigned char *) CFG_FLASH_BASE, + flash_size) + ); + } + putc ('\n'); +# else /* !CFG_FLASH_CHECKSUM */ + print_size (flash_size, "\n"); +# endif /* CFG_FLASH_CHECKSUM */ + } else { + puts (failed); + hang (); + } + + bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */ + bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ + bd->bi_flashoffset = 0; +#else /* CFG_NO_FLASH */ + bd->bi_flashsize = 0; + bd->bi_flashstart = 0; + bd->bi_flashoffset = 0; +#endif /* !CFG_NO_FLASH */ + + WATCHDOG_RESET (); + + /* initialize higher level parts of CPU like time base and timers */ + cpu_init_r (); + + WATCHDOG_RESET (); + + /* initialize malloc() area */ + mem_malloc_init (); + malloc_bin_reloc (); + +#ifdef CONFIG_SPI +# if !defined(CFG_ENV_IS_IN_EEPROM) + spi_init_f (); +# endif + spi_init_r (); +#endif + + /* relocate environment function pointers etc. */ + env_relocate (); + + /* + * Fill in missing fields of bd_info. + * We do this here, where we have "normal" access to the + * environment; we used to do this still running from ROM, + * where had to use getenv_r(), which can be pretty slow when + * the environment is in EEPROM. + */ + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + /* IP Address */ + bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + + WATCHDOG_RESET (); + + + /** leave this here (after malloc(), environment and PCI are working) **/ + /* Initialize devices */ + devices_init (); + + /* Initialize the jump table for applications */ + jumptable_init (); + + /* Initialize the console (after the relocation and devices init) */ + console_init_r (); + +#if defined(CONFIG_MISC_INIT_R) + /* miscellaneous platform dependent initialisations */ + misc_init_r (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + WATCHDOG_RESET (); + puts ("KGDB: "); + kgdb_init (); +#endif + + debug ("U-Boot relocated to %08lx\n", dest_addr); + + /* + * Enable Interrupts + */ + interrupt_init (); + + /* Must happen after interrupts are initialized since + * an irq handler gets installed + */ + timer_init(); + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + serial_buffered_init(); +#endif + +#ifdef CONFIG_STATUS_LED + status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); +#endif + + udelay (20); + + set_timer (0); + + /* Insert function pointers now that we have relocated the code */ + + /* Initialize from environment */ + if ((s = getenv ("loadaddr")) != NULL) { + load_addr = simple_strtoul (s, NULL, 16); + } +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif /* CFG_CMD_NET */ + + WATCHDOG_RESET (); + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) + WATCHDOG_RESET (); + puts ("DOC: "); + doc_init (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + WATCHDOG_RESET (); + puts ("NAND:"); + nand_init(); /* go init the NAND */ +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) + WATCHDOG_RESET(); + eth_init(bd); +#endif + +#ifdef CONFIG_POST + post_run (NULL, POST_RAM | post_bootmode_get(0)); +#endif + +#ifdef CONFIG_LAST_STAGE_INIT + WATCHDOG_RESET (); + /* + * Some parts can be only initialized if all others (like + * Interrupts) are up and running (i.e. the PC-style ISA + * keyboard). + */ + last_stage_init (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + WATCHDOG_RESET (); + bedbug_init (); +#endif + +#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) + /* + * Export available size of memory for Linux, + * taking into account the protected RAM at top of memory + */ + { + ulong pram; + uchar memsz[32]; +#ifdef CONFIG_PRAM + char *s; + + if ((s = getenv ("pram")) != NULL) { + pram = simple_strtoul (s, NULL, 10); + } else { + pram = CONFIG_PRAM; + } +#else + pram=0; +#endif +#ifdef CONFIG_LOGBUFFER + /* Also take the logbuffer into account (pram is in kB) */ + pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; +#endif + sprintf (memsz, "%ldk", (bd->bi_memsize / 1024) - pram); + setenv ("mem", memsz); + } +#endif + +#ifdef CONFIG_MODEM_SUPPORT + { + extern int do_mdm_init; + do_mdm_init = gd->do_mdm_init; + } +#endif + +#ifdef CONFIG_WATCHDOG + /* disable watchdog if environment is set */ + if ((s = getenv ("watchdog")) != NULL) { + if (strncmp (s, "off", 3) == 0) { + WATCHDOG_DISABLE (); + } + } +#endif /* CONFIG_WATCHDOG*/ + + + /* Initialization complete - start the monitor */ + + /* main_loop() can return to retry autoboot, if so just run it again. */ + for (;;) { + WATCHDOG_RESET (); + main_loop (); + } + + /* NOTREACHED - no way out of command loop except booting */ +} + + +void hang(void) +{ + puts ("### ERROR ### Please RESET the board ###\n"); + for (;;); +} diff --git a/lib_m68k/cache.c b/lib_m68k/cache.c new file mode 100644 index 0000000..84fb6c2 --- /dev/null +++ b/lib_m68k/cache.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +void flush_cache (ulong start_addr, ulong size) +{ + /* Must be implemented for all M68k processors with copy-back data cache */ +} diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c new file mode 100644 index 0000000..a32de1a --- /dev/null +++ b/lib_m68k/m68k_linux.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +#define PHYSADDR(x) x + +#define LINUX_MAX_ENVS 256 +#define LINUX_MAX_ARGS 256 + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +extern image_header_t header; /* from cmd_bootm.c */ + +extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); + +static int linux_argc; +static char **linux_argv; + +static char **linux_env; +static char *linux_env_p; +static int linux_env_idx; + +static void linux_params_init (ulong start, char *commandline); +static void linux_env_set (char *env_name, char *env_val); + +void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong * len_ptr, int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong len = 0, checksum; + ulong initrd_start, initrd_end; + ulong data; + void (*theKernel) (int, char **, char **, int *); + image_header_t *hdr = &header; + char *commandline = getenv ("bootargs"); + char env_buf[12]; + + theKernel = + (void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep); + + /* + * Check if there is an initrd image + */ + if (argc >= 3) { + SHOW_BOOT_PROGRESS (9); + + addr = simple_strtoul (argv[2], NULL, 16); + + printf ("## Loading Ramdisk Image at %08lx ...\n", addr); + + /* Copy header so we can blank CRC field for re-calculation */ + memcpy (&header, (char *) addr, sizeof (image_header_t)); + + if (ntohl (hdr->ih_magic) != IH_MAGIC) { + printf ("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS (-10); + do_reset (cmdtp, flag, argc, argv); + } + + data = (ulong) & header; + len = sizeof (image_header_t); + + checksum = ntohl (hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (char *) data, len) != checksum) { + printf ("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS (-11); + do_reset (cmdtp, flag, argc, argv); + } + + SHOW_BOOT_PROGRESS (10); + + print_image_hdr (hdr); + + data = addr + sizeof (image_header_t); + len = ntohl (hdr->ih_size); + + if (verify) { + ulong csum = 0; + + printf (" Verifying Checksum ... "); + csum = crc32 (0, (char *) data, len); + if (csum != ntohl (hdr->ih_dcrc)) { + printf ("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS (-12); + do_reset (cmdtp, flag, argc, argv); + } + printf ("OK\n"); + } + + SHOW_BOOT_PROGRESS (11); + + if ((hdr->ih_os != IH_OS_LINUX) || + (hdr->ih_arch != IH_CPU_M68K) || + (hdr->ih_type != IH_TYPE_RAMDISK)) { + printf ("No Linux M68K Ramdisk Image\n"); + SHOW_BOOT_PROGRESS (-13); + do_reset (cmdtp, flag, argc, argv); + } + + /* + * Now check if we have a multifile image + */ + } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { + ulong tail = ntohl (len_ptr[0]) % 4; + int i; + + SHOW_BOOT_PROGRESS (13); + + /* skip kernel length and terminator */ + data = (ulong) (&len_ptr[2]); + /* skip any additional image length fields */ + for (i = 1; len_ptr[i]; ++i) + data += 4; + /* add kernel length, and align */ + data += ntohl (len_ptr[0]); + if (tail) { + data += 4 - tail; + } + + len = ntohl (len_ptr[1]); + + } else { + /* + * no initrd image + */ + SHOW_BOOT_PROGRESS (14); + + data = 0; + } + +#ifdef DEBUG + if (!data) { + printf ("No initrd\n"); + } +#endif + + if (data) { + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = 0; + initrd_end = 0; + } + + SHOW_BOOT_PROGRESS (15); + +#ifdef DEBUG + printf ("## Transferring control to Linux (at address %08lx) ...\n", + (ulong) theKernel); +#endif + + linux_params_init (PHYSADDR (gd->bd->bi_boot_params), commandline); + + sprintf (env_buf, "%lu", gd->ram_size >> 20); + linux_env_set ("memsize", env_buf); + + sprintf (env_buf, "0x%08X", (uint) PHYSADDR (initrd_start)); + linux_env_set ("initrd_start", env_buf); + + sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start)); + linux_env_set ("initrd_size", env_buf); + + sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart)); + linux_env_set ("flash_start", env_buf); + + sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); + linux_env_set ("flash_size", env_buf); + + /* we assume that the kernel is in place */ + printf ("\nStarting kernel ...\n\n"); + + theKernel (linux_argc, linux_argv, linux_env, 0); +} + +static void linux_params_init (ulong start, char *line) +{ + char *next, *quote, *argp; + + linux_argc = 1; + linux_argv = (char **) start; + linux_argv[0] = 0; + argp = (char *) (linux_argv + LINUX_MAX_ARGS); + + next = line; + + while (line && *line && linux_argc < LINUX_MAX_ARGS) { + quote = strchr (line, '"'); + next = strchr (line, ' '); + + while (next != NULL && quote != NULL && quote < next) { + /* we found a left quote before the next blank + * now we have to find the matching right quote + */ + next = strchr (quote + 1, '"'); + if (next != NULL) { + quote = strchr (next + 1, '"'); + next = strchr (next + 1, ' '); + } + } + + if (next == NULL) { + next = line + strlen (line); + } + + linux_argv[linux_argc] = argp; + memcpy (argp, line, next - line); + argp[next - line] = 0; + + argp += next - line + 1; + linux_argc++; + + if (*next) + next++; + + line = next; + } + + linux_env = (char **) (((ulong) argp + 15) & ~15); + linux_env[0] = 0; + linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS); + linux_env_idx = 0; +} + +static void linux_env_set (char *env_name, char *env_val) +{ + if (linux_env_idx < LINUX_MAX_ENVS - 1) { + linux_env[linux_env_idx] = linux_env_p; + + strcpy (linux_env_p, env_name); + linux_env_p += strlen (env_name); + + strcpy (linux_env_p, "="); + linux_env_p += 1; + + strcpy (linux_env_p, env_val); + linux_env_p += strlen (env_val); + + linux_env_p++; + linux_env[++linux_env_idx] = 0; + } +} diff --git a/lib_m68k/time.c b/lib_m68k/time.c new file mode 100644 index 0000000..1d6d297 --- /dev/null +++ b/lib_m68k/time.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2003 Josef Baumgartner + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +#ifdef CONFIG_M5272 +#include +#include +#endif + +#ifdef CONFIG_M5282 +#include +#endif + +#ifdef CONFIG_M5249 +#include +#include +#endif + + +static ulong timestamp; +#ifdef CONFIG_M5282 +static unsigned short lastinc; +#endif + + +#if defined(CONFIG_M5272) +/* + * We use timer 3 which is running with a period of 1 us + */ +void udelay(unsigned long usec) +{ + volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3); + uint start, now, tmp; + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 3 as timebase clock */ + timerp->timer_tmr = MCFTIMER_TMR_DISABLE; + timerp->timer_tcn = 0; + /* set period to 1 us */ + timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | + MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE; + + start = now = timerp->timer_tcn; + while (now < start + tmp) + now = timerp->timer_tcn; + } +} + +void mcf_timer_interrupt (void * not_used){ + volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); + + /* check for timer 4 interrupts */ + if ((intp->int_isr & 0x01000000) != 0) { + return; + } + + /* reset timer */ + timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; + timestamp ++; +} + +void timer_init (void) { + volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); + + timestamp = 0; + + /* Set up TIMER 4 as clock */ + timerp->timer_tmr = MCFTIMER_TMR_DISABLE; + + /* initialize and enable timer 4 interrupt */ + irq_install_handler (72, mcf_timer_interrupt, 0); + intp->int_icr1 |= 0x0000000d; + + timerp->timer_tcn = 0; + timerp->timer_trr = 1000; /* Interrupt every ms */ + /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ + timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | + MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; +} + +void reset_timer (void) +{ + timestamp = 0; +} + +ulong get_timer (ulong base) +{ + return (timestamp - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} +#endif + +#if defined(CONFIG_M5282) + +void udelay(unsigned long usec) +{ + volatile unsigned short *timerp; + uint tmp; + + timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3); + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 3 as timebase clock */ + timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; + timerp[MCFTIMER_PMR] = 0; + /* set period to 1 us */ + timerp[MCFTIMER_PCSR] = + (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; + + timerp[MCFTIMER_PMR] = tmp; + while (timerp[MCFTIMER_PCNTR] > 0); + } +} + +void timer_init (void) +{ + volatile unsigned short *timerp; + + timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); + timestamp = 0; + + /* Set up TIMER 4 as poll clock */ + timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; + timerp[MCFTIMER_PMR] = lastinc = 0; + timerp[MCFTIMER_PCSR] = + (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; +} + +void set_timer (ulong t) +{ + volatile unsigned short *timerp; + + timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); + timestamp = 0; + timerp[MCFTIMER_PMR] = lastinc = 0; +} + +ulong get_timer (ulong base) +{ + unsigned short now, diff; + volatile unsigned short *timerp; + + timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); + now = timerp[MCFTIMER_PCNTR]; + diff = -(now - lastinc); + + timestamp += diff; + lastinc = now; + return timestamp - base; +} + +void wait_ticks (unsigned long ticks) +{ + set_timer (0); + while (get_timer (0) < ticks); +} +#endif + + +#if defined(CONFIG_M5249) +/* + * We use timer 1 which is running with a period of 1 us + */ +void udelay(unsigned long usec) +{ + volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1); + uint start, now, tmp; + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 1 as timebase clock */ + timerp->timer_tmr = MCFTIMER_TMR_DISABLE; + timerp->timer_tcn = 0; + /* set period to 1 us */ + /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ + timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | + MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE; + + start = now = timerp->timer_tcn; + while (now < start + tmp) + now = timerp->timer_tcn; + } +} + +void mcf_timer_interrupt (void * not_used){ + volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); + + /* check for timer 2 interrupts */ + if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) { + return; + } + + /* reset timer */ + timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; + timestamp ++; +} + +void timer_init (void) { + volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); + + timestamp = 0; + + /* Set up TIMER 2 as clock */ + timerp->timer_tmr = MCFTIMER_TMR_DISABLE; + + /* initialize and enable timer 2 interrupt */ + irq_install_handler (31, mcf_timer_interrupt, 0); + mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); + mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3); + + timerp->timer_tcn = 0; + timerp->timer_trr = 1000; /* Interrupt every ms */ + /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ + /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ + timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | + MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; +} + +void reset_timer (void) +{ + timestamp = 0; +} + +ulong get_timer (ulong base) +{ + return (timestamp - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} +#endif + + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On M68K it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On M68K it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} diff --git a/lib_m68k/traps.c b/lib_m68k/traps.c new file mode 100644 index 0000000..1ca94dc --- /dev/null +++ b/lib_m68k/traps.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2003 + * Josef Baumgartner + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +extern void _exc_handler(void); +extern void _int_handler(void); + +static void show_frame(struct pt_regs *fp) +{ + printf ("Vector Number: %d Format: %02x Fault Status: %01x\n\n", (fp->vector & 0x3fc) >> 2, + fp->format, (fp->vector & 0x3) | ((fp->vector & 0xc00) >> 8)); + printf ("PC: %08lx SR: %08lx SP: %08lx\n", fp->pc, (long) fp->sr, (long) fp); + printf ("D0: %08lx D1: %08lx D2: %08lx D3: %08lx\n", + fp->d0, fp->d1, fp->d2, fp->d3); + printf ("D4: %08lx D5: %08lx D6: %08lx D7: %08lx\n", + fp->d4, fp->d5, fp->d6, fp->d7); + printf ("A0: %08lx A1: %08lx A2: %08lx A3: %08lx\n", + fp->a0, fp->a1, fp->a2, fp->a3); + printf ("A4: %08lx A5: %08lx A6: %08lx\n", + fp->a4, fp->a5, fp->a6); +} + +void exc_handler(struct pt_regs *fp) { + printf("\n\n*** Unexpected exception ***\n"); + show_frame (fp); + printf("\n*** Please Reset Board! ***\n"); + for(;;); +} + +void trap_init(ulong value) { + unsigned long *vec = (ulong *)value; + int i; + + for(i = 2; i < 25; i++) { + vec[i] = (unsigned long)_exc_handler; + } + for(i = 25; i < 32; i++) { + vec[i] = (unsigned long)_int_handler; + } + for(i = 32; i < 64; i++) { + vec[i] = (unsigned long)_exc_handler; + } + for(i = 64; i < 256; i++) { + vec[i] = (unsigned long)_int_handler; + } + + setvbr(value); /* set vector base register to new table */ +} diff --git a/lib_microblaze/Makefile b/lib_microblaze/Makefile new file mode 100644 index 0000000..ec01722 --- /dev/null +++ b/lib_microblaze/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = + +COBJS = board.o microblaze_linux.o time.o cache.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c new file mode 100644 index 0000000..bc987a3 --- /dev/null +++ b/lib_microblaze/board.c @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +const char version_string[] = + U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"; + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start; +static ulong mem_malloc_end; +static ulong mem_malloc_brk; + + +void *sbrk (ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) { + return (NULL); + } + mem_malloc_brk = new; + return ((void *) old); +} + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ +typedef int (init_fnc_t) (void); + +init_fnc_t *init_sequence[] = { + serial_init, /* serial communications setup */ + NULL, +}; + +void board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd; + init_fnc_t **init_fnc_ptr; + + /* Pointer is writable since we allocated a register for it. */ + gd = (gd_t *)CFG_GBL_DATA_OFFSET; + memset((void *)gd, 0, CFG_GBL_DATA_SIZE); + + gd->bd = (bd_t *)(gd+1); /* At end of global data */ + gd->baudrate = CONFIG_BAUDRATE; + + bd = gd->bd; + bd->bi_baudrate = CONFIG_BAUDRATE; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + WATCHDOG_RESET (); + if ((*init_fnc_ptr) () != 0) { + hang (); + } + } + + /* main_loop */ + for (;;) { + WATCHDOG_RESET (); + main_loop (); + } +} + +void hang (void) +{ + puts ("### ERROR ### Please RESET the board ###\n"); + for (;;); +} diff --git a/lib_microblaze/cache.c b/lib_microblaze/cache.c new file mode 100644 index 0000000..a2f7493 --- /dev/null +++ b/lib_microblaze/cache.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +void flush_cache (ulong addr, ulong size) +{ + /* MicroBlaze have write thruough cache. nothing to do. */ + return; +} diff --git a/lib_microblaze/microblaze_linux.c b/lib_microblaze/microblaze_linux.c new file mode 100644 index 0000000..b3a0815 --- /dev/null +++ b/lib_microblaze/microblaze_linux.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ +} diff --git a/lib_microblaze/time.c b/lib_microblaze/time.c new file mode 100644 index 0000000..12e8488 --- /dev/null +++ b/lib_microblaze/time.c @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +void udelay(unsigned long usec) +{ +} diff --git a/lib_mips/Makefile b/lib_mips/Makefile new file mode 100644 index 0000000..d5980e6 --- /dev/null +++ b/lib_mips/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = + +COBJS = board.o time.o mips_linux.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_mips/board.c b/lib_mips/board.c new file mode 100644 index 0000000..b7d3356 --- /dev/null +++ b/lib_mips/board.c @@ -0,0 +1,432 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ + (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ + defined(CFG_ENV_IS_IN_NVRAM) +#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) +#else +#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN +#endif + +#undef DEBUG + +extern int timer_init(void); + +extern int incaip_set_cpuclk(void); + +extern ulong uboot_end_data; +extern ulong uboot_end; + +ulong monitor_flash_len; + +const char version_string[] = + U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"; + +static char *failed = "*** failed ***\n"; + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start; +static ulong mem_malloc_end; +static ulong mem_malloc_brk; + + +/* + * The Malloc area is immediately below the monitor copy in DRAM + */ +static void mem_malloc_init (void) +{ + ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off; + + mem_malloc_end = dest_addr; + mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + + memset ((void *) mem_malloc_start, + 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk (ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) { + return (NULL); + } + mem_malloc_brk = new; + return ((void *) old); +} + + +static int init_func_ram (void) +{ +#ifdef CONFIG_BOARD_TYPES + int board_type = gd->board_type; +#else + int board_type = 0; /* use dummy arg */ +#endif + puts ("DRAM: "); + + if ((gd->ram_size = initdram (board_type)) > 0) { + print_size (gd->ram_size, "\n"); + return (0); + } + puts (failed); + return (1); +} + +static int display_banner(void) +{ + + printf ("\n\n%s\n\n", version_string); + return (0); +} + +static void display_flash_config(ulong size) +{ + puts ("Flash: "); + print_size (size, "\n"); +} + + +static int init_baudrate (void) +{ + char tmp[64]; /* long enough for environment variables */ + int i = getenv_r ("baudrate", tmp, sizeof (tmp)); + + gd->baudrate = (i > 0) + ? (int) simple_strtoul (tmp, NULL, 10) + : CONFIG_BAUDRATE; + + return (0); +} + + +/* + * Breath some life into the board... + * + * The first part of initialization is running from Flash memory; + * its main purpose is to initialize the RAM so that we + * can relocate the monitor code to RAM. + */ + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ +typedef int (init_fnc_t) (void); + +init_fnc_t *init_sequence[] = { + timer_init, + env_init, /* initialize environment */ +#ifdef CONFIG_INCA_IP + incaip_set_cpuclk, /* set cpu clock according to environment variable */ +#endif + init_baudrate, /* initialze baudrate settings */ + serial_init, /* serial communications setup */ + console_init_f, + display_banner, /* say that we are here */ + checkboard, + init_func_ram, + NULL, +}; + + +void board_init_f(ulong bootflag) +{ + gd_t gd_data, *id; + bd_t *bd; + init_fnc_t **init_fnc_ptr; + ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_MONITOR_BASE; + ulong *s; +#ifdef CONFIG_PURPLE + void copy_code (ulong); +#endif + + /* Pointer is writable since we allocated a register for it. + */ + gd = &gd_data; + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset ((void *)gd, 0, sizeof (gd_t)); + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) { + hang (); + } + } + + /* + * Now that we have DRAM mapped and working, we can + * relocate the code and continue running from DRAM. + */ + addr = CFG_SDRAM_BASE + gd->ram_size; + + /* We can reserve some RAM "on top" here. + */ + + /* round down to next 4 kB limit. + */ + addr &= ~(4096 - 1); + debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); + + /* Reserve memory for U-Boot code, data & bss + * round down to next 16 kB limit + */ + addr -= len; + addr &= ~(16 * 1024 - 1); + + debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); + + /* Reserve memory for malloc() arena. + */ + addr_sp = addr - TOTAL_MALLOC_LEN; + debug ("Reserving %dk for malloc() at: %08lx\n", + TOTAL_MALLOC_LEN >> 10, addr_sp); + + /* + * (permanently) allocate a Board Info struct + * and a permanent copy of the "global" data + */ + addr_sp -= sizeof(bd_t); + bd = (bd_t *)addr_sp; + gd->bd = bd; + debug ("Reserving %d Bytes for Board Info at: %08lx\n", + sizeof(bd_t), addr_sp); + + addr_sp -= sizeof(gd_t); + id = (gd_t *)addr_sp; + debug ("Reserving %d Bytes for Global Data at: %08lx\n", + sizeof (gd_t), addr_sp); + + /* Reserve memory for boot params. + */ + addr_sp -= CFG_BOOTPARAMS_LEN; + bd->bi_boot_params = addr_sp; + debug ("Reserving %dk for boot params() at: %08lx\n", + CFG_BOOTPARAMS_LEN >> 10, addr_sp); + + /* + * Finally, we set up a new (bigger) stack. + * + * Leave some safety gap for SP, force alignment on 16 byte boundary + * Clear initial stack frame + */ + addr_sp -= 16; + addr_sp &= ~0xF; + s = (ulong *)addr_sp; + *s-- = 0; + *s-- = 0; + addr_sp = (ulong)s; + debug ("Stack Pointer at: %08lx\n", addr_sp); + + /* + * Save local variables to board info struct + */ + bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ + bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ + bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ + + memcpy (id, (void *)gd, sizeof (gd_t)); + + /* On the purple board we copy the code in a special way + * in order to solve flash problems + */ +#ifdef CONFIG_PURPLE + copy_code(addr); +#endif + + relocate_code (addr_sp, id, addr); + + /* NOTREACHED - relocate_code() does not return */ +} +/************************************************************************ + * + * This is the next part if the initialization sequence: we are now + * running from RAM and have a "normal" C environment, i. e. global + * data can be written, BSS has been cleared, the stack size in not + * that critical any more, etc. + * + ************************************************************************ + */ + +void board_init_r (gd_t *id, ulong dest_addr) +{ + cmd_tbl_t *cmdtp; + ulong size; + extern void malloc_bin_reloc (void); +#ifndef CFG_ENV_IS_NOWHERE + extern char * env_name_spec; +#endif + char *s, *e; + bd_t *bd; + int i; + + gd = id; + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + + debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); + + gd->reloc_off = dest_addr - CFG_MONITOR_BASE; + + monitor_flash_len = (ulong)&uboot_end_data - dest_addr; + + /* + * We have to relocate the command table manually + */ + for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + ulong addr; + + addr = (ulong) (cmdtp->cmd) + gd->reloc_off; +#if 0 + printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", + cmdtp->name, (ulong) (cmdtp->cmd), addr); +#endif + cmdtp->cmd = + (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; + + addr = (ulong)(cmdtp->name) + gd->reloc_off; + cmdtp->name = (char *)addr; + + if (cmdtp->usage) { + addr = (ulong)(cmdtp->usage) + gd->reloc_off; + cmdtp->usage = (char *)addr; + } +#ifdef CFG_LONGHELP + if (cmdtp->help) { + addr = (ulong)(cmdtp->help) + gd->reloc_off; + cmdtp->help = (char *)addr; + } +#endif + } + /* there are some other pointer constants we must deal with */ +#ifndef CFG_ENV_IS_NOWHERE + env_name_spec += gd->reloc_off; +#endif + + /* configure available FLASH banks */ + size = flash_init(); + display_flash_config (size); + + bd = gd->bd; + bd->bi_flashstart = CFG_FLASH_BASE; + bd->bi_flashsize = size; +#if CFG_MONITOR_BASE == CFG_FLASH_BASE + bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */ +#else + bd->bi_flashoffset = 0; +#endif + + /* initialize malloc() area */ + mem_malloc_init(); + malloc_bin_reloc(); + + /* relocate environment function pointers etc. */ + env_relocate(); + + /* board MAC address */ + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + /* IP Address */ + bd->bi_ip_addr = getenv_IPaddr("ipaddr"); + +#if defined(CONFIG_PCI) + /* + * Do pci configuration + */ + pci_init(); +#endif + +/** leave this here (after malloc(), environment and PCI are working) **/ + /* Initialize devices */ + devices_init (); + + jumptable_init (); + + /* Initialize the console (after the relocation and devices init) */ + console_init_r (); +/** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/ + + /* Initialize from environment */ + if ((s = getenv ("loadaddr")) != NULL) { + load_addr = simple_strtoul (s, NULL, 16); + } +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif /* CFG_CMD_NET */ + +#if defined(CONFIG_MISC_INIT_R) + /* miscellaneous platform dependent initialisations */ + misc_init_r (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); +#endif + eth_initialize(gd->bd); +#endif + + /* main_loop() can return to retry autoboot, if so just run it again. */ + for (;;) { + main_loop (); + } + + /* NOTREACHED - no way out of command loop except booting */ +} + +void hang (void) +{ + puts ("### ERROR ### Please RESET the board ###\n"); + for (;;); +} diff --git a/lib_mips/mips_linux.c b/lib_mips/mips_linux.c new file mode 100644 index 0000000..12e8435 --- /dev/null +++ b/lib_mips/mips_linux.c @@ -0,0 +1,285 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +#define LINUX_MAX_ENVS 256 +#define LINUX_MAX_ARGS 256 + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +extern image_header_t header; /* from cmd_bootm.c */ + +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +static int linux_argc; +static char ** linux_argv; + +static char ** linux_env; +static char * linux_env_p; +static int linux_env_idx; + +static void linux_params_init (ulong start, char * commandline); +static void linux_env_set (char * env_name, char * env_val); + + +void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong * len_ptr, int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + + ulong len = 0, checksum; + ulong initrd_start, initrd_end; + ulong data; + void (*theKernel) (int, char **, char **, int *); + image_header_t *hdr = &header; + char *commandline = getenv ("bootargs"); + char env_buf[12]; + + theKernel = + (void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep); + + /* + * Check if there is an initrd image + */ + if (argc >= 3) { + SHOW_BOOT_PROGRESS (9); + + addr = simple_strtoul (argv[2], NULL, 16); + + printf ("## Loading Ramdisk Image at %08lx ...\n", addr); + + /* Copy header so we can blank CRC field for re-calculation */ + memcpy (&header, (char *) addr, sizeof (image_header_t)); + + if (ntohl (hdr->ih_magic) != IH_MAGIC) { + printf ("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS (-10); + do_reset (cmdtp, flag, argc, argv); + } + + data = (ulong) & header; + len = sizeof (image_header_t); + + checksum = ntohl (hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *) data, len) != checksum) { + printf ("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS (-11); + do_reset (cmdtp, flag, argc, argv); + } + + SHOW_BOOT_PROGRESS (10); + + print_image_hdr (hdr); + + data = addr + sizeof (image_header_t); + len = ntohl (hdr->ih_size); + + if (verify) { + ulong csum = 0; + + printf (" Verifying Checksum ... "); + csum = crc32 (0, (uchar *) data, len); + if (csum != ntohl (hdr->ih_dcrc)) { + printf ("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS (-12); + do_reset (cmdtp, flag, argc, argv); + } + printf ("OK\n"); + } + + SHOW_BOOT_PROGRESS (11); + + if ((hdr->ih_os != IH_OS_LINUX) || + (hdr->ih_arch != IH_CPU_MIPS) || + (hdr->ih_type != IH_TYPE_RAMDISK)) { + printf ("No Linux MIPS Ramdisk Image\n"); + SHOW_BOOT_PROGRESS (-13); + do_reset (cmdtp, flag, argc, argv); + } + + /* + * Now check if we have a multifile image + */ + } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { + ulong tail = ntohl (len_ptr[0]) % 4; + int i; + + SHOW_BOOT_PROGRESS (13); + + /* skip kernel length and terminator */ + data = (ulong) (&len_ptr[2]); + /* skip any additional image length fields */ + for (i = 1; len_ptr[i]; ++i) + data += 4; + /* add kernel length, and align */ + data += ntohl (len_ptr[0]); + if (tail) { + data += 4 - tail; + } + + len = ntohl (len_ptr[1]); + + } else { + /* + * no initrd image + */ + SHOW_BOOT_PROGRESS (14); + + data = 0; + } + +#ifdef DEBUG + if (!data) { + printf ("No initrd\n"); + } +#endif + + if (data) { + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = 0; + initrd_end = 0; + } + + SHOW_BOOT_PROGRESS (15); + +#ifdef DEBUG + printf ("## Transferring control to Linux (at address %08lx) ...\n", + (ulong) theKernel); +#endif + + linux_params_init (UNCACHED_SDRAM (gd->bd->bi_boot_params), commandline); + +#ifdef CONFIG_MEMSIZE_IN_BYTES + sprintf (env_buf, "%lu", gd->ram_size); +#ifdef DEBUG + printf ("## Giving linux memsize in bytes, %lu\n", gd->ram_size); +#endif +#else + sprintf (env_buf, "%lu", gd->ram_size >> 20); +#ifdef DEBUG + printf ("## Giving linux memsize in MB, %lu\n", gd->ram_size >> 20); +#endif +#endif /* CONFIG_MEMSIZE_IN_BYTES */ + + linux_env_set ("memsize", env_buf); + + sprintf (env_buf, "0x%08X", (uint) UNCACHED_SDRAM (initrd_start)); + linux_env_set ("initrd_start", env_buf); + + sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start)); + linux_env_set ("initrd_size", env_buf); + + sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart)); + linux_env_set ("flash_start", env_buf); + + sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); + linux_env_set ("flash_size", env_buf); + + /* we assume that the kernel is in place */ + printf ("\nStarting kernel ...\n\n"); + + theKernel (linux_argc, linux_argv, linux_env, 0); +} + +static void linux_params_init (ulong start, char *line) +{ + char *next, *quote, *argp; + + linux_argc = 1; + linux_argv = (char **) start; + linux_argv[0] = 0; + argp = (char *) (linux_argv + LINUX_MAX_ARGS); + + next = line; + + while (line && *line && linux_argc < LINUX_MAX_ARGS) { + quote = strchr (line, '"'); + next = strchr (line, ' '); + + while (next != NULL && quote != NULL && quote < next) { + /* we found a left quote before the next blank + * now we have to find the matching right quote + */ + next = strchr (quote + 1, '"'); + if (next != NULL) { + quote = strchr (next + 1, '"'); + next = strchr (next + 1, ' '); + } + } + + if (next == NULL) { + next = line + strlen (line); + } + + linux_argv[linux_argc] = argp; + memcpy (argp, line, next - line); + argp[next - line] = 0; + + argp += next - line + 1; + linux_argc++; + + if (*next) + next++; + + line = next; + } + + linux_env = (char **) (((ulong) argp + 15) & ~15); + linux_env[0] = 0; + linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS); + linux_env_idx = 0; +} + +static void linux_env_set (char *env_name, char *env_val) +{ + if (linux_env_idx < LINUX_MAX_ENVS - 1) { + linux_env[linux_env_idx] = linux_env_p; + + strcpy (linux_env_p, env_name); + linux_env_p += strlen (env_name); + + strcpy (linux_env_p, "="); + linux_env_p += 1; + + strcpy (linux_env_p, env_val); + linux_env_p += strlen (env_val); + + linux_env_p++; + linux_env[++linux_env_idx] = 0; + } +} diff --git a/lib_mips/time.c b/lib_mips/time.c new file mode 100644 index 0000000..cd8dc72 --- /dev/null +++ b/lib_mips/time.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + +static inline void mips_compare_set(u32 v) +{ + asm volatile ("mtc0 %0, $11" : : "r" (v)); +} + +static inline void mips_count_set(u32 v) +{ + asm volatile ("mtc0 %0, $9" : : "r" (v)); +} + + +static inline u32 mips_count_get(void) +{ + u32 count; + + asm volatile ("mfc0 %0, $9" : "=r" (count) :); + return count; +} + +/* + * timer without interrupts + */ + +int timer_init(void) +{ + mips_compare_set(0); + mips_count_set(0); + + return 0; +} + +void reset_timer(void) +{ + mips_count_set(0); +} + +ulong get_timer(ulong base) +{ + return mips_count_get() - base; +} + +void set_timer(ulong t) +{ + mips_count_set(t); +} + +void udelay (unsigned long usec) +{ + ulong tmo; + ulong start = get_timer(0); + + tmo = usec * (CFG_HZ / 1000000); + while ((ulong)((mips_count_get() - start)) < tmo) + /*NOP*/; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On MIPS it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return mips_count_get(); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On MIPS it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CFG_HZ; +} diff --git a/lib_nios/Makefile b/lib_nios/Makefile new file mode 100644 index 0000000..eff46db --- /dev/null +++ b/lib_nios/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = + +COBJS = board.o cache.o divmod.o nios_linux.o mult.o time.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_nios/board.c b/lib_nios/board.c new file mode 100644 index 0000000..e6cda52 --- /dev/null +++ b/lib_nios/board.c @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#ifdef CONFIG_STATUS_LED +#include +#endif + + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ + + +extern void malloc_bin_reloc (void); +typedef int (init_fnc_t) (void); + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start = 0; +static ulong mem_malloc_end = 0; +static ulong mem_malloc_brk = 0; + +/* + * The Malloc area is immediately below the monitor copy in RAM + */ +static void mem_malloc_init (void) +{ + mem_malloc_start = CFG_MALLOC_BASE; + mem_malloc_end = mem_malloc_start + CFG_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + memset ((void *) mem_malloc_start, + 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk (ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) { + return (NULL); + } + mem_malloc_brk = new; + return ((void *) old); +} + + +/************************************************************************ + * Initialization sequence * + ***********************************************************************/ + +init_fnc_t *init_sequence[] = { + +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, /* Call board-specific init code early.*/ +#endif + + env_init, + serial_init, + console_init_f, + display_options, + checkcpu, + checkboard, + NULL, /* Terminate this list */ +}; + + +/***********************************************************************/ +void board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd; + init_fnc_t **init_fnc_ptr; + char *s, *e; + int i; + + /* Pointer is writable since we allocated a register for it. + * Nios treats CFG_GBL_DATA_OFFSET as an address. + */ + gd = (gd_t *)CFG_GBL_DATA_OFFSET; + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset( gd, 0, CFG_GBL_DATA_SIZE ); + + gd->bd = (bd_t *)(gd+1); /* At end of global data */ + gd->baudrate = CONFIG_BAUDRATE; + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + + bd = gd->bd; + bd->bi_memstart = CFG_SDRAM_BASE; + bd->bi_memsize = CFG_SDRAM_SIZE; + bd->bi_flashstart = CFG_FLASH_BASE; +#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE) + bd->bi_sramstart= CFG_SRAM_BASE; + bd->bi_sramsize = CFG_SRAM_SIZE; +#endif + bd->bi_baudrate = CONFIG_BAUDRATE; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + WATCHDOG_RESET (); + if ((*init_fnc_ptr) () != 0) { + hang (); + } + } + + WATCHDOG_RESET (); + bd->bi_flashsize = flash_init(); + + WATCHDOG_RESET (); + mem_malloc_init(); + malloc_bin_reloc(); + env_relocate(); + + bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) s = (*e) ? e + 1 : e; + } + + WATCHDOG_RESET (); + devices_init(); + jumptable_init(); + console_init_r(); + /* + */ + + WATCHDOG_RESET (); + interrupt_init (); + +#ifdef CONFIG_STATUS_LED + status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); +#endif + + /* main_loop */ + for (;;) { + WATCHDOG_RESET (); + main_loop (); + } +} + + +/***********************************************************************/ + +void hang (void) +{ +#ifdef CONFIG_STATUS_LED + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); + status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING); +#endif + puts("### ERROR ### Please reset board ###\n"); + for (;;); +} diff --git a/lib_nios/cache.c b/lib_nios/cache.c new file mode 100644 index 0000000..87dbab1 --- /dev/null +++ b/lib_nios/cache.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + +void flush_cache (ulong addr, ulong size) +{ + /* Nios cache is write-thru -- nothing to do here. + */ + return; +} diff --git a/lib_nios/divmod.c b/lib_nios/divmod.c new file mode 100644 index 0000000..3c7e71e --- /dev/null +++ b/lib_nios/divmod.c @@ -0,0 +1,101 @@ +/* + * This file is part of GNU CC. + * + * GNU CC is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published + * by the Free Software Foundation; either version 2, or (at your + * option) any later version. + * + * GNU CC is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with GNU CC; see the file COPYING. If not, write + * to the Free Software Foundation, 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + */ + + +#include "math.h" + +USItype udivmodsi4 (USItype num, USItype den, word_type modwanted) +{ + USItype bit = 1; + USItype res = 0; + + while (den < num && bit && !(den & (1L << 31))) { + den <<= 1; + bit <<= 1; + } + while (bit) { + if (num >= den) { + num -= den; + res |= bit; + } + bit >>= 1; + den >>= 1; + } + if (modwanted) + return num; + return res; +} + + +SItype __divsi3 (SItype a, SItype b) +{ + word_type neg = 0; + SItype res; + + if (a < 0) { + a = -a; + neg = !neg; + } + + if (b < 0) { + b = -b; + neg = !neg; + } + + res = udivmodsi4 (a, b, 0); + + if (neg) + res = -res; + + return res; +} + + +SItype __modsi3 (SItype a, SItype b) +{ + word_type neg = 0; + SItype res; + + if (a < 0) { + a = -a; + neg = 1; + } + + if (b < 0) + b = -b; + + res = udivmodsi4 (a, b, 1); + + if (neg) + res = -res; + + return res; +} + + +SItype __udivsi3 (SItype a, SItype b) +{ + return udivmodsi4 (a, b, 0); +} + + +SItype __umodsi3 (SItype a, SItype b) +{ + return udivmodsi4 (a, b, 1); +} diff --git a/lib_nios/math.h b/lib_nios/math.h new file mode 100644 index 0000000..ccffbbc --- /dev/null +++ b/lib_nios/math.h @@ -0,0 +1,16 @@ +#define BITS_PER_UNIT 8 + +typedef int HItype __attribute__ ((mode (HI))); +typedef unsigned int UHItype __attribute__ ((mode (HI))); + +typedef int SItype __attribute__ ((mode (SI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); + +typedef int word_type __attribute__ ((mode (__word__))); + +struct SIstruct {HItype low, high;}; + +typedef union { + struct SIstruct s; + SItype ll; +} SIunion; diff --git a/lib_nios/mult.c b/lib_nios/mult.c new file mode 100644 index 0000000..66bb64d --- /dev/null +++ b/lib_nios/mult.c @@ -0,0 +1,56 @@ +/* + * This file is part of GNU CC. + * + * GNU CC is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published + * by the Free Software Foundation; either version 2, or (at your + * option) any later version. + * + * GNU CC is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with GNU CC; see the file COPYING. If not, write + * to the Free Software Foundation, 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + */ + + +#include + +#if !defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) + +#include "math.h" + +USItype __mulsi3 (USItype a, USItype b) +{ + USItype c = 0; + + while (a != 0) { + if (a & 1) + c += b; + a >>= 1; + b <<= 1; + } + + return c; +} + + +UHItype __mulhi3 (UHItype a, UHItype b) +{ + UHItype c = 0; + + while (a != 0) { + if (a & 1) + c += b; + a >>= 1; + b <<= 1; + } + + return c; +} + +#endif /*!defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) */ diff --git a/lib_nios/nios_linux.c b/lib_nios/nios_linux.c new file mode 100644 index 0000000..eef1757 --- /dev/null +++ b/lib_nios/nios_linux.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* FIXME: Once we find a stable version of uC-linux for nios + * we can get this working. ;-) + * + */ +void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ +} diff --git a/lib_nios/time.c b/lib_nios/time.c new file mode 100644 index 0000000..25a233e --- /dev/null +++ b/lib_nios/time.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +extern void dly_clks( unsigned long ticks ); + +void udelay(unsigned long usec) +{ + /* The Nios core doesn't have a timebase, so we do our + * best for now and call a low-level loop that counts + * cpu clocks. + */ + unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec; + WATCHDOG_RESET (); /* trigger watchdog if needed */ + dly_clks (cnt); +} diff --git a/lib_nios2/Makefile b/lib_nios2/Makefile new file mode 100644 index 0000000..44b893c --- /dev/null +++ b/lib_nios2/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = cache.o + +COBJS = board.o divmod.o nios_linux.o mult.o time.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_nios2/board.c b/lib_nios2/board.c new file mode 100644 index 0000000..0e0b042 --- /dev/null +++ b/lib_nios2/board.c @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#ifdef CONFIG_STATUS_LED +#include +#endif + + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ + + +extern void malloc_bin_reloc (void); +typedef int (init_fnc_t) (void); + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start = 0; +static ulong mem_malloc_end = 0; +static ulong mem_malloc_brk = 0; + +/* + * The Malloc area is immediately below the monitor copy in RAM + */ +static void mem_malloc_init (void) +{ + mem_malloc_start = CFG_MALLOC_BASE; + mem_malloc_end = mem_malloc_start + CFG_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + memset ((void *) mem_malloc_start, + 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk (ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) { + return (NULL); + } + mem_malloc_brk = new; + return ((void *) old); +} + + +/************************************************************************ + * Initialization sequence * + ***********************************************************************/ + +init_fnc_t *init_sequence[] = { + +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, /* Call board-specific init code early.*/ +#endif + + env_init, + serial_init, + console_init_f, + display_options, + checkcpu, + checkboard, + NULL, /* Terminate this list */ +}; + + +/***********************************************************************/ +void board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd; + init_fnc_t **init_fnc_ptr; + char *s, *e; + int i; + + /* Pointer is writable since we allocated a register for it. + * Nios treats CFG_GBL_DATA_OFFSET as an address. + */ + gd = (gd_t *)CFG_GBL_DATA_OFFSET; + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset( gd, 0, CFG_GBL_DATA_SIZE ); + + gd->bd = (bd_t *)(gd+1); /* At end of global data */ + gd->baudrate = CONFIG_BAUDRATE; + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + + bd = gd->bd; + bd->bi_memstart = CFG_SDRAM_BASE; + bd->bi_memsize = CFG_SDRAM_SIZE; + bd->bi_flashstart = CFG_FLASH_BASE; +#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE) + bd->bi_sramstart= CFG_SRAM_BASE; + bd->bi_sramsize = CFG_SRAM_SIZE; +#endif + bd->bi_baudrate = CONFIG_BAUDRATE; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + WATCHDOG_RESET (); + if ((*init_fnc_ptr) () != 0) { + hang (); + } + } + + WATCHDOG_RESET (); + bd->bi_flashsize = flash_init(); + + WATCHDOG_RESET (); + mem_malloc_init(); + malloc_bin_reloc(); + env_relocate(); + + bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) s = (*e) ? e + 1 : e; + } + + WATCHDOG_RESET (); + devices_init(); + jumptable_init(); + console_init_r(); + + WATCHDOG_RESET (); + interrupt_init (); + + /* main_loop */ + for (;;) { + WATCHDOG_RESET (); + main_loop (); + } +} + + +/***********************************************************************/ + +void hang (void) +{ + disable_interrupts (); + puts("### ERROR ### Please reset board ###\n"); + for (;;); +} diff --git a/lib_nios2/cache.S b/lib_nios2/cache.S new file mode 100644 index 0000000..eb7735a --- /dev/null +++ b/lib_nios2/cache.S @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2004, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + .text + + .global flush_dcache + +flush_dcache: + add r5, r5, r4 + movhi r8, %hi(CFG_DCACHELINE_SIZE) + ori r8, r8, %lo(CFG_DCACHELINE_SIZE) +0: flushd 0(r4) + add r4, r4, r8 + bltu r4, r5, 0b + ret + + + .global flush_icache + +flush_icache: + add r5, r5, r4 + movhi r8, %hi(CFG_ICACHELINE_SIZE) + ori r8, r8, %lo(CFG_ICACHELINE_SIZE) +1: flushi r4 + add r4, r4, r8 + bltu r4, r5, 1b + ret + + .global flush_cache + +flush_cache: + add r5, r5, r4 + mov r9, r4 + mov r10, r5 + + movhi r8, %hi(CFG_DCACHELINE_SIZE) + ori r8, r8, %lo(CFG_DCACHELINE_SIZE) +0: flushd 0(r4) + add r4, r4, r8 + bltu r4, r5, 0b + + mov r4, r9 + mov r5, r10 + movhi r8, %hi(CFG_ICACHELINE_SIZE) + ori r8, r8, %lo(CFG_ICACHELINE_SIZE) +1: flushi r4 + add r4, r4, r8 + bltu r4, r5, 1b + + sync + flushp + ret diff --git a/lib_nios2/divmod.c b/lib_nios2/divmod.c new file mode 100644 index 0000000..3c7e71e --- /dev/null +++ b/lib_nios2/divmod.c @@ -0,0 +1,101 @@ +/* + * This file is part of GNU CC. + * + * GNU CC is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published + * by the Free Software Foundation; either version 2, or (at your + * option) any later version. + * + * GNU CC is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with GNU CC; see the file COPYING. If not, write + * to the Free Software Foundation, 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + */ + + +#include "math.h" + +USItype udivmodsi4 (USItype num, USItype den, word_type modwanted) +{ + USItype bit = 1; + USItype res = 0; + + while (den < num && bit && !(den & (1L << 31))) { + den <<= 1; + bit <<= 1; + } + while (bit) { + if (num >= den) { + num -= den; + res |= bit; + } + bit >>= 1; + den >>= 1; + } + if (modwanted) + return num; + return res; +} + + +SItype __divsi3 (SItype a, SItype b) +{ + word_type neg = 0; + SItype res; + + if (a < 0) { + a = -a; + neg = !neg; + } + + if (b < 0) { + b = -b; + neg = !neg; + } + + res = udivmodsi4 (a, b, 0); + + if (neg) + res = -res; + + return res; +} + + +SItype __modsi3 (SItype a, SItype b) +{ + word_type neg = 0; + SItype res; + + if (a < 0) { + a = -a; + neg = 1; + } + + if (b < 0) + b = -b; + + res = udivmodsi4 (a, b, 1); + + if (neg) + res = -res; + + return res; +} + + +SItype __udivsi3 (SItype a, SItype b) +{ + return udivmodsi4 (a, b, 0); +} + + +SItype __umodsi3 (SItype a, SItype b) +{ + return udivmodsi4 (a, b, 1); +} diff --git a/lib_nios2/math.h b/lib_nios2/math.h new file mode 100644 index 0000000..ccffbbc --- /dev/null +++ b/lib_nios2/math.h @@ -0,0 +1,16 @@ +#define BITS_PER_UNIT 8 + +typedef int HItype __attribute__ ((mode (HI))); +typedef unsigned int UHItype __attribute__ ((mode (HI))); + +typedef int SItype __attribute__ ((mode (SI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); + +typedef int word_type __attribute__ ((mode (__word__))); + +struct SIstruct {HItype low, high;}; + +typedef union { + struct SIstruct s; + SItype ll; +} SIunion; diff --git a/lib_nios2/mult.c b/lib_nios2/mult.c new file mode 100644 index 0000000..66bb64d --- /dev/null +++ b/lib_nios2/mult.c @@ -0,0 +1,56 @@ +/* + * This file is part of GNU CC. + * + * GNU CC is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published + * by the Free Software Foundation; either version 2, or (at your + * option) any later version. + * + * GNU CC is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with GNU CC; see the file COPYING. If not, write + * to the Free Software Foundation, 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + */ + + +#include + +#if !defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) + +#include "math.h" + +USItype __mulsi3 (USItype a, USItype b) +{ + USItype c = 0; + + while (a != 0) { + if (a & 1) + c += b; + a >>= 1; + b <<= 1; + } + + return c; +} + + +UHItype __mulhi3 (UHItype a, UHItype b) +{ + UHItype c = 0; + + while (a != 0) { + if (a & 1) + c += b; + a >>= 1; + b <<= 1; + } + + return c; +} + +#endif /*!defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) */ diff --git a/lib_nios2/nios_linux.c b/lib_nios2/nios_linux.c new file mode 100644 index 0000000..9eb3426 --- /dev/null +++ b/lib_nios2/nios_linux.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +extern image_header_t header; /* common/cmd_bootm.c */ + +void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + image_header_t *hdr = &header; + void (*kernel)(void) = (void (*)(void))ntohl (hdr->ih_ep); + + /* For now we assume the Microtronix linux ... which only + * needs to be called ;-) + */ + kernel (); +} diff --git a/lib_nios2/time.c b/lib_nios2/time.c new file mode 100644 index 0000000..25a233e --- /dev/null +++ b/lib_nios2/time.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2003, Psyent Corporation + * Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + + +extern void dly_clks( unsigned long ticks ); + +void udelay(unsigned long usec) +{ + /* The Nios core doesn't have a timebase, so we do our + * best for now and call a low-level loop that counts + * cpu clocks. + */ + unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec; + WATCHDOG_RESET (); /* trigger watchdog if needed */ + dly_clks (cnt); +} diff --git a/lib_ppc/Makefile b/lib_ppc/Makefile new file mode 100644 index 0000000..652a419 --- /dev/null +++ b/lib_ppc/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = ppcstring.o ticks.o + +COBJS = board.o \ + bat_rw.o cache.o extable.o kgdb.o time.o interrupts.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c new file mode 100644 index 0000000..912efa7 --- /dev/null +++ b/lib_ppc/bat_rw.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) +{ + switch (bat) { + case IBAT0: + mtspr (IBAT0L, lower); + mtspr (IBAT0U, upper); + break; + + case IBAT1: + mtspr (IBAT1L, lower); + mtspr (IBAT1U, upper); + break; + + case IBAT2: + mtspr (IBAT2L, lower); + mtspr (IBAT2U, upper); + break; + + case IBAT3: + mtspr (IBAT3L, lower); + mtspr (IBAT3U, upper); + break; + + case DBAT0: + mtspr (DBAT0L, lower); + mtspr (DBAT0U, upper); + break; + + case DBAT1: + mtspr (DBAT1L, lower); + mtspr (DBAT1U, upper); + break; + + case DBAT2: + mtspr (DBAT2L, lower); + mtspr (DBAT2U, upper); + break; + + case DBAT3: + mtspr (DBAT3L, lower); + mtspr (DBAT3U, upper); + break; + + default: + return (-1); + } + + return (0); +} + +int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) +{ + unsigned long register u; + unsigned long register l; + + switch (bat) { + case IBAT0: + l = mfspr (IBAT0L); + u = mfspr (IBAT0U); + break; + + case IBAT1: + l = mfspr (IBAT1L); + u = mfspr (IBAT1U); + break; + + case IBAT2: + l = mfspr (IBAT2L); + u = mfspr (IBAT2U); + break; + + case IBAT3: + l = mfspr (IBAT3L); + u = mfspr (IBAT3U); + break; + + case DBAT0: + l = mfspr (DBAT0L); + u = mfspr (DBAT0U); + break; + + case DBAT1: + l = mfspr (DBAT1L); + u = mfspr (DBAT1U); + break; + + case DBAT2: + l = mfspr (DBAT2L); + u = mfspr (DBAT2U); + break; + + case DBAT3: + l = mfspr (DBAT3L); + u = mfspr (DBAT3U); + break; + + default: + return (-1); + } + + *upper = u; + *lower = l; + + return (0); +} diff --git a/lib_ppc/board.c b/lib_ppc/board.c new file mode 100644 index 0000000..f40bb25 --- /dev/null +++ b/lib_ppc/board.c @@ -0,0 +1,1199 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_8xx +#include +#endif +#ifdef CONFIG_5xx +#include +#endif +#ifdef CONFIG_MPC5xxx +#include +#endif +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#include +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) +#include +#endif +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#include +#endif +#ifdef CONFIG_STATUS_LED +#include +#endif +#include +#include +#ifdef CFG_ALLOC_DPRAM +#if !defined(CONFIG_CPM2) +#include +#endif +#endif +#include +#if defined(CONFIG_BAB7xx) +#include +#endif +#include +#if defined(CONFIG_POST) +#include +#endif +#if defined(CONFIG_LOGBUFFER) +#include +#endif +#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) +#include +#endif +#ifdef CONFIG_PS2KBD +#include +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +void doc_init (void); +#endif +#if defined(CONFIG_HARD_I2C) || \ + defined(CONFIG_SOFT_I2C) +#include +#endif +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +void nand_init (void); +#endif + +static char *failed = "*** failed ***\n"; + +#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU) +extern flash_info_t flash_info[]; +#endif + +#include +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CFG_ENV_IS_EMBEDDED) +#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN +#elif ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ + (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ + defined(CFG_ENV_IS_IN_NVRAM) +#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) +#else +#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN +#endif + +extern ulong __init_end; +extern ulong _end; +ulong monitor_flash_len; + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +#include +#endif + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start = 0; +static ulong mem_malloc_end = 0; +static ulong mem_malloc_brk = 0; + +/************************************************************************ + * Utilities * + ************************************************************************ + */ + +/* + * The Malloc area is immediately below the monitor copy in DRAM + */ +static void mem_malloc_init (void) +{ + ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off; + + mem_malloc_end = dest_addr; + mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + + memset ((void *) mem_malloc_start, + 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk (ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) { + return (NULL); + } + mem_malloc_brk = new; + return ((void *) old); +} + +char *strmhz (char *buf, long hz) +{ + long l, n; + long m; + + n = hz / 1000000L; + l = sprintf (buf, "%ld", n); + m = (hz % 1000000L) / 1000L; + if (m != 0) + sprintf (buf + l, ".%03ld", m); + return (buf); +} + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ +typedef int (init_fnc_t) (void); + +/************************************************************************ + * Init Utilities * + ************************************************************************ + * Some of this code should be moved into the core functions, + * but let's get it working (again) first... + */ + +static int init_baudrate (void) +{ + char tmp[64]; /* long enough for environment variables */ + int i = getenv_r ("baudrate", tmp, sizeof (tmp)); + + gd->baudrate = (i > 0) + ? (int) simple_strtoul (tmp, NULL, 10) + : CONFIG_BAUDRATE; + return (0); +} + +/***********************************************************************/ + +#ifdef CONFIG_ADD_RAM_INFO +void board_add_ram_info(int); +#endif + +static int init_func_ram (void) +{ +#ifdef CONFIG_BOARD_TYPES + int board_type = gd->board_type; +#else + int board_type = 0; /* use dummy arg */ +#endif + puts ("DRAM: "); + + if ((gd->ram_size = initdram (board_type)) > 0) { + print_size (gd->ram_size, ""); +#ifdef CONFIG_ADD_RAM_INFO + board_add_ram_info(0); +#endif + putc('\n'); + return (0); + } + puts (failed); + return (1); +} + +/***********************************************************************/ + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +static int init_func_i2c (void) +{ + puts ("I2C: "); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + puts ("ready\n"); + return (0); +} +#endif + +/***********************************************************************/ + +#if defined(CONFIG_WATCHDOG) +static int init_func_watchdog_init (void) +{ + puts (" Watchdog enabled\n"); + WATCHDOG_RESET (); + return (0); +} +# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, + +static int init_func_watchdog_reset (void) +{ + WATCHDOG_RESET (); + return (0); +} +# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, +#else +# define INIT_FUNC_WATCHDOG_INIT /* undef */ +# define INIT_FUNC_WATCHDOG_RESET /* undef */ +#endif /* CONFIG_WATCHDOG */ + +/************************************************************************ + * Initialization sequence * + ************************************************************************ + */ + +init_fnc_t *init_sequence[] = { + +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, +#endif + +#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) + get_clocks, /* get CPU and bus clocks (etc.) */ +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) + adjust_sdram_tbs_8xx, +#endif + init_timebase, +#endif +#ifdef CFG_ALLOC_DPRAM +#if !defined(CONFIG_CPM2) + dpram_init, +#endif +#endif +#if defined(CONFIG_BOARD_POSTCLK_INIT) + board_postclk_init, +#endif + env_init, +#if defined(CONFIG_8xx_CPUCLK_DEFAULT) + get_clocks_866, /* get CPU and bus clocks according to the environment variable */ + sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */ + init_timebase, +#endif + init_baudrate, + serial_init, + console_init_f, + display_options, +#if defined(CONFIG_8260) + prt_8260_rsr, + prt_8260_clks, +#endif /* CONFIG_8260 */ + +#if defined(CONFIG_MPC83XX) + print_clock_conf, +#endif + + checkcpu, +#if defined(CONFIG_MPC5xxx) + prt_mpc5xxx_clks, +#endif /* CONFIG_MPC5xxx */ +#if defined(CONFIG_MPC8220) + prt_mpc8220_clks, +#endif + checkboard, + INIT_FUNC_WATCHDOG_INIT +#if defined(CONFIG_MISC_INIT_F) + misc_init_f, +#endif + INIT_FUNC_WATCHDOG_RESET +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + init_func_i2c, +#endif +#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */ + dtt_init, +#endif +#ifdef CONFIG_POST + post_init_f, +#endif + INIT_FUNC_WATCHDOG_RESET + init_func_ram, +#if defined(CFG_DRAM_TEST) + testdram, +#endif /* CFG_DRAM_TEST */ + INIT_FUNC_WATCHDOG_RESET + + NULL, /* Terminate this list */ +}; + +/************************************************************************ + * + * This is the first part of the initialization sequence that is + * implemented in C, but still running from ROM. + * + * The main purpose is to provide a (serial) console interface as + * soon as possible (so we can see any error messages), and to + * initialize the RAM so that we can relocate the monitor code to + * RAM. + * + * Be aware of the restrictions: global data is read-only, BSS is not + * initialized, and stack space is limited to a few kB. + * + ************************************************************************ + */ + +void board_init_f (ulong bootflag) +{ + bd_t *bd; + ulong len, addr, addr_sp; + ulong *s; + gd_t *id; + init_fnc_t **init_fnc_ptr; +#ifdef CONFIG_PRAM + int i; + ulong reg; + uchar tmp[64]; /* long enough for environment variables */ +#endif + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + +#if !defined(CONFIG_CPM2) + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); +#endif + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr) () != 0) { + hang (); + } + } + + /* + * Now that we have DRAM mapped and working, we can + * relocate the code and continue running from DRAM. + * + * Reserve memory at end of RAM for (top down in that order): + * - kernel log buffer + * - protected RAM + * - LCD framebuffer + * - monitor code + * - board info struct + */ + len = (ulong)&_end - CFG_MONITOR_BASE; + +#ifndef CONFIG_VERY_BIG_RAM + addr = CFG_SDRAM_BASE + gd->ram_size; +#else + /* only allow stack below 256M */ + addr = CFG_SDRAM_BASE + + (gd->ram_size > 256 << 20) ? 256 << 20 : gd->ram_size; +#endif + +#ifdef CONFIG_LOGBUFFER + /* reserve kernel log buffer */ + addr -= (LOGBUFF_RESERVE); + debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); +#endif + +#ifdef CONFIG_PRAM + /* + * reserve protected RAM + */ + i = getenv_r ("pram", (char *)tmp, sizeof (tmp)); + reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM; + addr -= (reg << 10); /* size is in kB */ + debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); +#endif /* CONFIG_PRAM */ + + /* round down to next 4 kB limit */ + addr &= ~(4096 - 1); + debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); + +#ifdef CONFIG_LCD + /* reserve memory for LCD display (always full pages) */ + addr = lcd_setmem (addr); + gd->fb_base = addr; +#endif /* CONFIG_LCD */ + +#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) + /* reserve memory for video display (always full pages) */ + addr = video_setmem (addr); + gd->fb_base = addr; +#endif /* CONFIG_VIDEO */ + + /* + * reserve memory for U-Boot code, data & bss + * round down to next 4 kB limit + */ + addr -= len; + addr &= ~(4096 - 1); +#ifdef CONFIG_E500 + /* round down to next 64 kB limit so that IVPR stays aligned */ + addr &= ~(65536 - 1); +#endif + + debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); + +#ifdef CONFIG_AMIGAONEG3SE + gd->relocaddr = addr; +#endif + + /* + * reserve memory for malloc() arena + */ + addr_sp = addr - TOTAL_MALLOC_LEN; + debug ("Reserving %dk for malloc() at: %08lx\n", + TOTAL_MALLOC_LEN >> 10, addr_sp); + + /* + * (permanently) allocate a Board Info struct + * and a permanent copy of the "global" data + */ + addr_sp -= sizeof (bd_t); + bd = (bd_t *) addr_sp; + gd->bd = bd; + debug ("Reserving %d Bytes for Board Info at: %08lx\n", + sizeof (bd_t), addr_sp); + addr_sp -= sizeof (gd_t); + id = (gd_t *) addr_sp; + debug ("Reserving %d Bytes for Global Data at: %08lx\n", + sizeof (gd_t), addr_sp); + + /* + * Finally, we set up a new (bigger) stack. + * + * Leave some safety gap for SP, force alignment on 16 byte boundary + * Clear initial stack frame + */ + addr_sp -= 16; + addr_sp &= ~0xF; + s = (ulong *)addr_sp; + *s-- = 0; + *s-- = 0; + addr_sp = (ulong)s; + debug ("Stack Pointer at: %08lx\n", addr_sp); + + /* + * Save local variables to board info struct + */ + + bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ + bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ + +#ifdef CONFIG_IP860 + bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */ + bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */ +#elif defined CONFIG_MPC8220 + bd->bi_sramstart = CFG_SRAM_BASE; /* start of SRAM memory */ + bd->bi_sramsize = CFG_SRAM_SIZE; /* size of SRAM memory */ +#else + bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */ + bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */ +#endif + +#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ + defined(CONFIG_E500) + bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */ +#endif +#if defined(CONFIG_MPC5xxx) + bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ +#endif +#if defined(CONFIG_MPC83XX) + bd->bi_immrbar = CFG_IMMRBAR; +#endif +#if defined(CONFIG_MPC8220) + bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ + bd->bi_inpfreq = gd->inp_clk; + bd->bi_pcifreq = gd->pci_clk; + bd->bi_vcofreq = gd->vco_clk; + bd->bi_pevfreq = gd->pev_clk; + bd->bi_flbfreq = gd->flb_clk; + + /* store bootparam to sram (backward compatible), here? */ + { + u32 *sram = (u32 *)CFG_SRAM_BASE; + *sram++ = gd->ram_size; + *sram++ = gd->bus_clk; + *sram++ = gd->inp_clk; + *sram++ = gd->cpu_clk; + *sram++ = gd->vco_clk; + *sram++ = gd->flb_clk; + *sram++ = 0xb8c3ba11; /* boot signature */ + } +#endif + + bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ + + WATCHDOG_RESET (); + bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ + bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ +#if defined(CONFIG_CPM2) + bd->bi_cpmfreq = gd->cpm_clk; + bd->bi_brgfreq = gd->brg_clk; + bd->bi_sccfreq = gd->scc_clk; + bd->bi_vco = gd->vco_out; +#endif /* CONFIG_CPM2 */ +#if defined(CONFIG_MPC5xxx) + bd->bi_ipbfreq = gd->ipb_clk; + bd->bi_pcifreq = gd->pci_clk; +#endif /* CONFIG_MPC5xxx */ + bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ + +#ifdef CFG_EXTBDINFO + strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); + strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version)); + + bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ + bd->bi_plb_busfreq = gd->bus_clk; +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + bd->bi_pci_busfreq = get_PCI_freq (); + bd->bi_opbfreq = get_OPB_freq (); +#elif defined(CONFIG_XILINX_ML300) + bd->bi_pci_busfreq = get_PCI_freq (); +#endif +#endif + + debug ("New Stack Pointer is: %08lx\n", addr_sp); + + WATCHDOG_RESET (); + +#ifdef CONFIG_POST + post_bootmode_init(); + post_run (NULL, POST_ROM | post_bootmode_get(0)); +#endif + + WATCHDOG_RESET(); + + memcpy (id, (void *)gd, sizeof (gd_t)); + + relocate_code (addr_sp, id, addr); + + /* NOTREACHED - relocate_code() does not return */ +} + +/************************************************************************ + * + * This is the next part if the initialization sequence: we are now + * running from RAM and have a "normal" C environment, i. e. global + * data can be written, BSS has been cleared, the stack size in not + * that critical any more, etc. + * + ************************************************************************ + */ +void board_init_r (gd_t *id, ulong dest_addr) +{ + cmd_tbl_t *cmdtp; + char *s, *e; + bd_t *bd; + int i; + extern void malloc_bin_reloc (void); +#ifndef CFG_ENV_IS_NOWHERE + extern char * env_name_spec; +#endif + +#ifndef CFG_NO_FLASH + ulong flash_size; +#endif + + gd = id; /* initialize RAM version of global data */ + bd = gd->bd; + + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + + debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); + + WATCHDOG_RESET (); + +#if defined(CONFIG_BOARD_EARLY_INIT_R) + board_early_init_r (); +#endif + + gd->reloc_off = dest_addr - CFG_MONITOR_BASE; + + monitor_flash_len = (ulong)&__init_end - dest_addr; + +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif + + /* + * We have to relocate the command table manually + */ + for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + ulong addr; + addr = (ulong) (cmdtp->cmd) + gd->reloc_off; +#if 0 + printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", + cmdtp->name, (ulong) (cmdtp->cmd), addr); +#endif + cmdtp->cmd = + (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; + + addr = (ulong)(cmdtp->name) + gd->reloc_off; + cmdtp->name = (char *)addr; + + if (cmdtp->usage) { + addr = (ulong)(cmdtp->usage) + gd->reloc_off; + cmdtp->usage = (char *)addr; + } +#ifdef CFG_LONGHELP + if (cmdtp->help) { + addr = (ulong)(cmdtp->help) + gd->reloc_off; + cmdtp->help = (char *)addr; + } +#endif + } + /* there are some other pointer constants we must deal with */ +#ifndef CFG_ENV_IS_NOWHERE + env_name_spec += gd->reloc_off; +#endif + + WATCHDOG_RESET (); + +#ifdef CONFIG_LOGBUFFER + logbuff_init_ptrs (); +#endif +#ifdef CONFIG_POST + post_output_backlog (); + post_reloc (); +#endif + + WATCHDOG_RESET(); + +#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM) + icache_enable (); /* it's time to enable the instruction cache */ +#endif + +#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) + unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ +#endif + +#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45) + /* + * Do PCI configuration on BAB7xx and CPC45 _before_ the flash + * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus + * bridge there. + */ + pci_init (); +#endif +#if defined(CONFIG_BAB7xx) + /* + * Initialise the ISA bridge + */ + initialise_w83c553f (); +#endif + + asm ("sync ; isync"); + + /* + * Setup trap handlers + */ + trap_init (dest_addr); + +#if !defined(CFG_NO_FLASH) + puts ("FLASH: "); + + if ((flash_size = flash_init ()) > 0) { +# ifdef CFG_FLASH_CHECKSUM + print_size (flash_size, ""); + /* + * Compute and print flash CRC if flashchecksum is set to 'y' + * + * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX + */ + s = getenv ("flashchecksum"); + if (s && (*s == 'y')) { + printf (" CRC: %08lX", + crc32 (0, (const unsigned char *) CFG_FLASH_BASE, flash_size) + ); + } + putc ('\n'); +# else /* !CFG_FLASH_CHECKSUM */ + print_size (flash_size, "\n"); +# endif /* CFG_FLASH_CHECKSUM */ + } else { + puts (failed); + hang (); + } + + bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */ + bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ +# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU) + /* flash mapped at end of memory map */ + bd->bi_flashoffset = TEXT_BASE + flash_size; +# elif CFG_MONITOR_BASE == CFG_FLASH_BASE + bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */ +# else + bd->bi_flashoffset = 0; +# endif +#else /* CFG_NO_FLASH */ + + bd->bi_flashsize = 0; + bd->bi_flashstart = 0; + bd->bi_flashoffset = 0; +#endif /* !CFG_NO_FLASH */ + + WATCHDOG_RESET (); + + /* initialize higher level parts of CPU like time base and timers */ + cpu_init_r (); + + WATCHDOG_RESET (); + + /* initialize malloc() area */ + mem_malloc_init (); + malloc_bin_reloc (); + +#ifdef CONFIG_SPI +# if !defined(CFG_ENV_IS_IN_EEPROM) + spi_init_f (); +# endif + spi_init_r (); +#endif + + /* relocate environment function pointers etc. */ + env_relocate (); + + /* + * Fill in missing fields of bd_info. + * We do this here, where we have "normal" access to the + * environment; we used to do this still running from ROM, + * where had to use getenv_r(), which can be pretty slow when + * the environment is in EEPROM. + */ + +#if defined(CFG_EXTBDINFO) +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) +#if defined(CONFIG_I2CFAST) + /* + * set bi_iic_fast for linux taking environment variable + * "i2cfast" into account + */ + { + char *s = getenv ("i2cfast"); + if (s && ((*s == 'y') || (*s == 'Y'))) { + bd->bi_iic_fast[0] = 1; + bd->bi_iic_fast[1] = 1; + } else { + bd->bi_iic_fast[0] = 0; + bd->bi_iic_fast[1] = 0; + } + } +#else + bd->bi_iic_fast[0] = 0; + bd->bi_iic_fast[1] = 0; +#endif /* CONFIG_I2CFAST */ +#endif /* CONFIG_405GP, CONFIG_405EP */ +#endif /* CFG_EXTBDINFO */ + + s = getenv ("ethaddr"); +#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) || defined(CONFIG_IAD210) + if (s == NULL) + board_get_enetaddr (bd->bi_enetaddr); + else +#endif + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#ifdef CONFIG_HERMES + if ((gd->board_type >> 16) == 2) + bd->bi_ethspeed = gd->board_type & 0xFFFF; + else + bd->bi_ethspeed = 0xFFFF; +#endif + +#ifdef CONFIG_NX823 + load_sernum_ethaddr (); +#endif + +#ifdef CONFIG_HAS_ETH1 + /* handle the 2nd ethernet address */ + + s = getenv ("eth1addr"); + + for (i = 0; i < 6; ++i) { + bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif +#ifdef CONFIG_HAS_ETH2 + /* handle the 3rd ethernet address */ + + s = getenv ("eth2addr"); +#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) + if (s == NULL) + board_get_enetaddr(bd->bi_enet2addr); + else +#endif + for (i = 0; i < 6; ++i) { + bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif + +#ifdef CONFIG_HAS_ETH3 + /* handle 4th ethernet address */ + s = getenv("eth3addr"); +#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) + if (s == NULL) + board_get_enetaddr(bd->bi_enet3addr); + else +#endif + for (i = 0; i < 6; ++i) { + bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif + +#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \ + defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) + load_sernum_ethaddr (); +#endif + /* IP Address */ + bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + + WATCHDOG_RESET (); + +#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45) + /* + * Do pci configuration + */ + pci_init (); +#endif + +/** leave this here (after malloc(), environment and PCI are working) **/ + /* Initialize devices */ + devices_init (); + + /* Initialize the jump table for applications */ + jumptable_init (); + + /* Initialize the console (after the relocation and devices init) */ + console_init_r (); + +#if defined(CONFIG_CCM) || \ + defined(CONFIG_COGENT) || \ + defined(CONFIG_CPCI405) || \ + defined(CONFIG_EVB64260) || \ + defined(CONFIG_KUP4K) || \ + defined(CONFIG_KUP4X) || \ + defined(CONFIG_LWMON) || \ + defined(CONFIG_PCU_E) || \ + defined(CONFIG_W7O) || \ + defined(CONFIG_MISC_INIT_R) + /* miscellaneous platform dependent initialisations */ + misc_init_r (); +#endif + +#ifdef CONFIG_HERMES + if (bd->bi_ethspeed != 0xFFFF) + hermes_start_lxt980 ((int) bd->bi_ethspeed); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + WATCHDOG_RESET (); + puts ("KGDB: "); + kgdb_init (); +#endif + + debug ("U-Boot relocated to %08lx\n", dest_addr); + + /* + * Enable Interrupts + */ + interrupt_init (); + + /* Must happen after interrupts are initialized since + * an irq handler gets installed + */ +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + serial_buffered_init(); +#endif + +#ifdef CONFIG_STATUS_LED + status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); +#endif + + udelay (20); + + set_timer (0); + + /* Initialize from environment */ + if ((s = getenv ("loadaddr")) != NULL) { + load_addr = simple_strtoul (s, NULL, 16); + } +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif /* CFG_CMD_NET */ + + WATCHDOG_RESET (); + +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + WATCHDOG_RESET (); + puts ("SCSI: "); + scsi_init (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) + WATCHDOG_RESET (); + puts ("DOC: "); + doc_init (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + WATCHDOG_RESET (); + puts ("NAND: "); + nand_init(); /* go init the NAND */ +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + WATCHDOG_RESET (); + puts ("Net: "); +#endif + eth_initialize (bd); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \ + defined(CONFIG_CCM) || \ + defined(CONFIG_ELPT860) || \ + defined(CONFIG_EP8260) || \ + defined(CONFIG_IP860) || \ + defined(CONFIG_IVML24) || \ + defined(CONFIG_IVMS8) || \ + defined(CONFIG_MPC8260ADS) || \ + defined(CONFIG_MPC8266ADS) || \ + defined(CONFIG_MPC8560ADS) || \ + defined(CONFIG_PCU_E) || \ + defined(CONFIG_RPXSUPER) || \ + defined(CONFIG_STXGP3) || \ + defined(CONFIG_SPD823TS) || \ + defined(CONFIG_RESET_PHY_R) ) + + WATCHDOG_RESET (); + debug ("Reset Ethernet PHY\n"); + reset_phy (); +#endif + +#ifdef CONFIG_POST + post_run (NULL, POST_RAM | post_bootmode_get(0)); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE) + WATCHDOG_RESET (); + puts ("PCMCIA:"); + pcmcia_init (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + WATCHDOG_RESET (); +# ifdef CONFIG_IDE_8xx_PCCARD + puts ("PCMCIA:"); +# else + puts ("IDE: "); +#endif + ide_init (); +#endif /* CFG_CMD_IDE */ + +#ifdef CONFIG_LAST_STAGE_INIT + WATCHDOG_RESET (); + /* + * Some parts can be only initialized if all others (like + * Interrupts) are up and running (i.e. the PC-style ISA + * keyboard). + */ + last_stage_init (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + WATCHDOG_RESET (); + bedbug_init (); +#endif + +#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) + /* + * Export available size of memory for Linux, + * taking into account the protected RAM at top of memory + */ + { + ulong pram; + uchar memsz[32]; +#ifdef CONFIG_PRAM + char *s; + + if ((s = getenv ("pram")) != NULL) { + pram = simple_strtoul (s, NULL, 10); + } else { + pram = CONFIG_PRAM; + } +#else + pram=0; +#endif +#ifdef CONFIG_LOGBUFFER + /* Also take the logbuffer into account (pram is in kB) */ + pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; +#endif + sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram); + setenv ("mem", (char *)memsz); + } +#endif + +#ifdef CONFIG_PS2KBD + puts ("PS/2: "); + kbd_init(); +#endif + +#ifdef CONFIG_MODEM_SUPPORT + { + extern int do_mdm_init; + do_mdm_init = gd->do_mdm_init; + } +#endif + + /* Initialization complete - start the monitor */ + + /* main_loop() can return to retry autoboot, if so just run it again. */ + for (;;) { + WATCHDOG_RESET (); + main_loop (); + } + + /* NOTREACHED - no way out of command loop except booting */ +} + +void hang (void) +{ + puts ("### ERROR ### Please RESET the board ###\n"); +#ifdef CONFIG_SHOW_BOOT_PROGRESS + show_boot_progress(-30); +#endif + for (;;); +} + +#ifdef CONFIG_MODEM_SUPPORT +/* called from main loop (common/main.c) */ +/* 'inline' - We have to do it fast */ +static inline void mdm_readline(char *buf, int bufsiz) +{ + char c; + char *p; + int n; + + n = 0; + p = buf; + for(;;) { + c = serial_getc(); + + /* dbg("(%c)", c); */ + + switch(c) { + case '\r': + break; + case '\n': + *p = '\0'; + return; + + default: + if(n++ > bufsiz) { + *p = '\0'; + return; /* sanity check */ + } + *p = c; + p++; + break; + } + } +} + +extern void dbg(const char *fmt, ...); +int mdm_init (void) +{ + char env_str[16]; + char *init_str; + int i; + extern char console_buffer[]; + extern void enable_putc(void); + extern int hwflow_onoff(int); + + enable_putc(); /* enable serial_putc() */ + +#ifdef CONFIG_HWFLOW + init_str = getenv("mdm_flow_control"); + if (init_str && (strcmp(init_str, "rts/cts") == 0)) + hwflow_onoff (1); + else + hwflow_onoff(-1); +#endif + + for (i = 1;;i++) { + sprintf(env_str, "mdm_init%d", i); + if ((init_str = getenv(env_str)) != NULL) { + serial_puts(init_str); + serial_puts("\n"); + for(;;) { + mdm_readline(console_buffer, CFG_CBSIZE); + dbg("ini%d: [%s]", i, console_buffer); + + if ((strcmp(console_buffer, "OK") == 0) || + (strcmp(console_buffer, "ERROR") == 0)) { + dbg("ini%d: cmd done", i); + break; + } else /* in case we are originating call ... */ + if (strncmp(console_buffer, "CONNECT", 7) == 0) { + dbg("ini%d: connect", i); + return 0; + } + } + } else + break; /* no init string - stop modem init */ + + udelay(100000); + } + + udelay(100000); + + /* final stage - wait for connect */ + for(;i > 1;) { /* if 'i' > 1 - wait for connection + message from modem */ + mdm_readline(console_buffer, CFG_CBSIZE); + dbg("ini_f: [%s]", console_buffer); + if (strncmp(console_buffer, "CONNECT", 7) == 0) { + dbg("ini_f: connected"); + return 0; + } + } + + return 0; +} + +#endif + +#if 0 /* We could use plain global data, but the resulting code is bigger */ +/* + * Pointer to initial global data area + * + * Here we initialize it. + */ +#undef XTRN_DECLARE_GLOBAL_DATA_PTR +#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ +DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); +#endif /* 0 */ + +/************************************************************************/ diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c new file mode 100644 index 0000000..a81ab5e --- /dev/null +++ b/lib_ppc/cache.c @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + +void flush_cache (ulong start_addr, ulong size) +{ +#ifndef CONFIG_5xx + ulong addr, end_addr = start_addr + size; + + if (CFG_CACHELINE_SIZE) { + addr = start_addr & (CFG_CACHELINE_SIZE - 1); + for (addr = start_addr; + addr < end_addr; + addr += CFG_CACHELINE_SIZE) { + asm ("dcbst 0,%0": :"r" (addr)); + } + asm ("sync"); /* Wait for all dcbst to complete on bus */ + + for (addr = start_addr; + addr < end_addr; + addr += CFG_CACHELINE_SIZE) { + asm ("icbi 0,%0": :"r" (addr)); + } + } + asm ("sync"); /* Always flush prefetch queue in any case */ + asm ("isync"); +#endif +} diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c new file mode 100644 index 0000000..d92f142 --- /dev/null +++ b/lib_ppc/extable.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 1999 Magnus Damm + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry +{ + unsigned long insn, fixup; +}; + +extern const struct exception_table_entry __start___ex_table[]; +extern const struct exception_table_entry __stop___ex_table[]; + +static inline unsigned long +search_one_table(const struct exception_table_entry *first, + const struct exception_table_entry *last, + unsigned long value) +{ + while (first <= last) { + const struct exception_table_entry *mid; + long diff; + + mid = (last - first) / 2 + first; + diff = mid->insn - value; + if (diff == 0) + return mid->fixup; + else if (diff < 0) + first = mid+1; + else + last = mid-1; + } + return 0; +} + +int ex_tab_message = 1; + +unsigned long +search_exception_table(unsigned long addr) +{ + unsigned long ret; + + /* There is only the kernel to search. */ + ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); + if (ex_tab_message) + printf("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret); + if (ret) return ret; + + return 0; +} diff --git a/lib_ppc/interrupts.c b/lib_ppc/interrupts.c new file mode 100644 index 0000000..b803952 --- /dev/null +++ b/lib_ppc/interrupts.c @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Gleb Natapov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#ifdef CONFIG_STATUS_LED +#include +#endif + +#ifdef CONFIG_SHOW_ACTIVITY + extern void board_show_activity (ulong); +#endif /* CONFIG_SHOW_ACTIVITY */ + +#ifndef CFG_WATCHDOG_FREQ +#define CFG_WATCHDOG_FREQ (CFG_HZ / 2) +#endif + +extern int interrupt_init_cpu (unsigned *); +extern void timer_interrupt_cpu (struct pt_regs *); + +static unsigned decrementer_count; /* count value for 1e6/HZ microseconds */ + +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + + asm volatile ("mfmsr %0":"=r" (msr):); + + return msr; +} + +static __inline__ void set_msr (unsigned long msr) +{ + asm volatile ("mtmsr %0"::"r" (msr)); +} + +static __inline__ unsigned long get_dec (void) +{ + unsigned long val; + + asm volatile ("mfdec %0":"=r" (val):); + + return val; +} + + +static __inline__ void set_dec (unsigned long val) +{ + if (val) + asm volatile ("mtdec %0"::"r" (val)); +} + + +void enable_interrupts (void) +{ + set_msr (get_msr () | MSR_EE); +} + +/* returns flag if MSR_EE was set before */ +int disable_interrupts (void) +{ + ulong msr = get_msr (); + + set_msr (msr & ~MSR_EE); + return ((msr & MSR_EE) != 0); +} + +int interrupt_init (void) +{ + int ret; + + /* call cpu specific function from $(CPU)/interrupts.c */ + ret = interrupt_init_cpu (&decrementer_count); + + if (ret) + return ret; + + set_dec (decrementer_count); + + set_msr (get_msr () | MSR_EE); + + return (0); +} + +static volatile ulong timestamp = 0; + +void timer_interrupt (struct pt_regs *regs) +{ + /* call cpu specific function from $(CPU)/interrupts.c */ + timer_interrupt_cpu (regs); + + /* Restore Decrementer Count */ + set_dec (decrementer_count); + + timestamp++; + +#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) + if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) + WATCHDOG_RESET (); +#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ + +#ifdef CONFIG_STATUS_LED + status_led_tick (timestamp); +#endif /* CONFIG_STATUS_LED */ + +#ifdef CONFIG_SHOW_ACTIVITY + board_show_activity (timestamp); +#endif /* CONFIG_SHOW_ACTIVITY */ +} + +void reset_timer (void) +{ + timestamp = 0; +} + +ulong get_timer (ulong base) +{ + return (timestamp - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} diff --git a/lib_ppc/kgdb.c b/lib_ppc/kgdb.c new file mode 100644 index 0000000..4c5d79a --- /dev/null +++ b/lib_ppc/kgdb.c @@ -0,0 +1,326 @@ +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + +#include +#include +#include + +#define PC_REGNUM 64 +#define SP_REGNUM 1 + +void breakinst(void); + +int +kgdb_setjmp(long *buf) +{ + asm ("mflr 0; stw 0,0(%0);" + "stw 1,4(%0); stw 2,8(%0);" + "mfcr 0; stw 0,12(%0);" + "stmw 13,16(%0)" + : : "r" (buf)); + /* XXX should save fp regs as well */ + return 0; +} + +void +kgdb_longjmp(long *buf, int val) +{ + if (val == 0) + val = 1; + asm ("lmw 13,16(%0);" + "lwz 0,12(%0); mtcrf 0x38,0;" + "lwz 0,0(%0); lwz 1,4(%0); lwz 2,8(%0);" + "mtlr 0; mr 3,%1" + : : "r" (buf), "r" (val)); +} + +static inline unsigned long +get_msr(void) +{ + unsigned long msr; + asm volatile("mfmsr %0" : "=r" (msr):); + return msr; +} + +static inline void +set_msr(unsigned long msr) +{ + asm volatile("mtmsr %0" : : "r" (msr)); +} + +/* Convert the SPARC hardware trap type code to a unix signal number. */ +/* + * This table contains the mapping between PowerPC hardware trap types, and + * signals, which are primarily what GDB understands. + */ +static struct hard_trap_info +{ + unsigned int tt; /* Trap type code for powerpc */ + unsigned char signo; /* Signal that we map this trap into */ +} hard_trap_info[] = { + { 0x200, SIGSEGV }, /* machine check */ + { 0x300, SIGSEGV }, /* address error (store) */ + { 0x400, SIGBUS }, /* instruction bus error */ + { 0x500, SIGINT }, /* interrupt */ + { 0x600, SIGBUS }, /* alingment */ + { 0x700, SIGTRAP }, /* breakpoint trap */ + { 0x800, SIGFPE }, /* fpu unavail */ + { 0x900, SIGALRM }, /* decrementer */ + { 0xa00, SIGILL }, /* reserved */ + { 0xb00, SIGILL }, /* reserved */ + { 0xc00, SIGCHLD }, /* syscall */ + { 0xd00, SIGTRAP }, /* single-step/watch */ + { 0xe00, SIGFPE }, /* fp assist */ + { 0, 0} /* Must be last */ +}; + +static int +computeSignal(unsigned int tt) +{ + struct hard_trap_info *ht; + + for (ht = hard_trap_info; ht->tt && ht->signo; ht++) + if (ht->tt == tt) + return ht->signo; + + return SIGHUP; /* default for things we don't know about */ +} + +void +kgdb_enter(struct pt_regs *regs, kgdb_data *kdp) +{ + unsigned long msr; + + kdp->private[0] = msr = get_msr(); + set_msr(msr & ~MSR_EE); /* disable interrupts */ + + if (regs->nip == (unsigned long)breakinst) { + /* Skip over breakpoint trap insn */ + regs->nip += 4; + } + regs->msr &= ~MSR_SE; + + /* reply to host that an exception has occurred */ + kdp->sigval = computeSignal(regs->trap); + + kdp->nregs = 2; + + kdp->regs[0].num = PC_REGNUM; + kdp->regs[0].val = regs->nip; + + kdp->regs[1].num = SP_REGNUM; + kdp->regs[1].val = regs->gpr[SP_REGNUM]; +} + +void +kgdb_exit(struct pt_regs *regs, kgdb_data *kdp) +{ + unsigned long msr = kdp->private[0]; + + if (kdp->extype & KGDBEXIT_WITHADDR) + regs->nip = kdp->exaddr; + + switch (kdp->extype & KGDBEXIT_TYPEMASK) { + + case KGDBEXIT_KILL: + case KGDBEXIT_CONTINUE: + set_msr(msr); + break; + + case KGDBEXIT_SINGLE: + regs->msr |= MSR_SE; +#if 0 + set_msr(msr | MSR_SE); +#endif + break; + } +} + +int +kgdb_trap(struct pt_regs *regs) +{ + return (regs->trap); +} + +/* return the value of the CPU registers. + * some of them are non-PowerPC names :( + * they are stored in gdb like: + * struct { + * u32 gpr[32]; + * f64 fpr[32]; + * u32 pc, ps, cnd, lr; (ps=msr) + * u32 cnt, xer, mq; + * } + */ + +#define SPACE_REQUIRED ((32*4)+(32*8)+(6*4)) + +#ifdef CONFIG_8260 +/* store floating double indexed */ +#define STFDI(n,p) __asm__ __volatile__ ("stfd " #n ",%0" : "=o"(p[2*n])) +/* store floating double multiple */ +#define STFDM(p) { STFDI( 0,p); STFDI( 1,p); STFDI( 2,p); STFDI( 3,p); \ + STFDI( 4,p); STFDI( 5,p); STFDI( 6,p); STFDI( 7,p); \ + STFDI( 8,p); STFDI( 9,p); STFDI(10,p); STFDI(11,p); \ + STFDI(12,p); STFDI(13,p); STFDI(14,p); STFDI(15,p); \ + STFDI(16,p); STFDI(17,p); STFDI(18,p); STFDI(19,p); \ + STFDI(20,p); STFDI(21,p); STFDI(22,p); STFDI(23,p); \ + STFDI(24,p); STFDI(25,p); STFDI(26,p); STFDI(27,p); \ + STFDI(28,p); STFDI(29,p); STFDI(30,p); STFDI(31,p); } +#endif + +int +kgdb_getregs(struct pt_regs *regs, char *buf, int max) +{ + int i; + unsigned long *ptr = (unsigned long *)buf; + + if (max < SPACE_REQUIRED) + kgdb_error(KGDBERR_NOSPACE); + + if ((unsigned long)ptr & 3) + kgdb_error(KGDBERR_ALIGNFAULT); + + /* General Purpose Regs */ + for (i = 0; i < 32; i++) + *ptr++ = regs->gpr[i]; + + /* Floating Point Regs */ +#ifdef CONFIG_8260 + STFDM(ptr); + ptr += 32*2; +#else + for (i = 0; i < 32; i++) { + *ptr++ = 0; + *ptr++ = 0; + } +#endif + + /* pc, msr, cr, lr, ctr, xer, (mq is unused) */ + *ptr++ = regs->nip; + *ptr++ = regs->msr; + *ptr++ = regs->ccr; + *ptr++ = regs->link; + *ptr++ = regs->ctr; + *ptr++ = regs->xer; + + return (SPACE_REQUIRED); +} + +/* set the value of the CPU registers */ + +#ifdef CONFIG_8260 +/* load floating double */ +#define LFD(n,v) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"(v)) +/* load floating double indexed */ +#define LFDI(n,p) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"((p)[2*n])) +/* load floating double multiple */ +#define LFDM(p) { LFDI( 0,p); LFDI( 1,p); LFDI( 2,p); LFDI( 3,p); \ + LFDI( 4,p); LFDI( 5,p); LFDI( 6,p); LFDI( 7,p); \ + LFDI( 8,p); LFDI( 9,p); LFDI(10,p); LFDI(11,p); \ + LFDI(12,p); LFDI(13,p); LFDI(14,p); LFDI(15,p); \ + LFDI(16,p); LFDI(17,p); LFDI(18,p); LFDI(19,p); \ + LFDI(20,p); LFDI(21,p); LFDI(22,p); LFDI(23,p); \ + LFDI(24,p); LFDI(25,p); LFDI(26,p); LFDI(27,p); \ + LFDI(28,p); LFDI(29,p); LFDI(30,p); LFDI(31,p); } +#endif + +void +kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length) +{ + unsigned long *ptr = (unsigned long *)buf; + + if (regno < 0 || regno >= 70) + kgdb_error(KGDBERR_BADPARAMS); + else if (regno >= 32 && regno < 64) { + if (length < 8) + kgdb_error(KGDBERR_NOSPACE); + } + else { + if (length < 4) + kgdb_error(KGDBERR_NOSPACE); + } + + if ((unsigned long)ptr & 3) + kgdb_error(KGDBERR_ALIGNFAULT); + + if (regno >= 0 && regno < 32) + regs->gpr[regno] = *ptr; + else switch (regno) { + +#ifdef CONFIG_8260 +#define caseF(n) \ + case (n) + 32: LFD(n, *ptr); break; + +caseF( 0) caseF( 1) caseF( 2) caseF( 3) caseF( 4) caseF( 5) caseF( 6) caseF( 7) +caseF( 8) caseF( 9) caseF(10) caseF(11) caseF(12) caseF(13) caseF(14) caseF(15) +caseF(16) caseF(17) caseF(18) caseF(19) caseF(20) caseF(21) caseF(22) caseF(23) +caseF(24) caseF(25) caseF(26) caseF(27) caseF(28) caseF(29) caseF(30) caseF(31) + +#undef caseF +#endif + + case 64: regs->nip = *ptr; break; + case 65: regs->msr = *ptr; break; + case 66: regs->ccr = *ptr; break; + case 67: regs->link = *ptr; break; + case 68: regs->ctr = *ptr; break; + case 69: regs->ctr = *ptr; break; + + default: + kgdb_error(KGDBERR_BADPARAMS); + } +} + +void +kgdb_putregs(struct pt_regs *regs, char *buf, int length) +{ + int i; + unsigned long *ptr = (unsigned long *)buf; + + if (length < SPACE_REQUIRED) + kgdb_error(KGDBERR_NOSPACE); + + if ((unsigned long)ptr & 3) + kgdb_error(KGDBERR_ALIGNFAULT); + + /* + * If the stack pointer has moved, you should pray. + * (cause only god can help you). + */ + + /* General Purpose Regs */ + for (i = 0; i < 32; i++) + regs->gpr[i] = *ptr++; + + /* Floating Point Regs */ +#ifdef CONFIG_8260 + LFDM(ptr); +#endif + ptr += 32*2; + + /* pc, msr, cr, lr, ctr, xer, (mq is unused) */ + regs->nip = *ptr++; + regs->msr = *ptr++; + regs->ccr = *ptr++; + regs->link = *ptr++; + regs->ctr = *ptr++; + regs->xer = *ptr++; +} + +/* This function will generate a breakpoint exception. It is used at the + beginning of a program to sync up with a debugger and can be used + otherwise as a quick means to stop program execution and "break" into + the debugger. */ + +void +kgdb_breakpoint(int argc, char *argv[]) +{ + asm(" .globl breakinst\n\ + breakinst: .long 0x7d821008\n\ + "); +} + +#endif /* CFG_CMD_KGDB */ diff --git a/lib_ppc/ppcstring.S b/lib_ppc/ppcstring.S new file mode 100644 index 0000000..97023a0 --- /dev/null +++ b/lib_ppc/ppcstring.S @@ -0,0 +1,216 @@ +/* + * String handling functions for PowerPC. + * + * Copyright (C) 1996 Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + + .globl strcpy +strcpy: + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r5) + bne 1b + blr + + .globl strncpy +strncpy: + cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r6,r3,-1 + addi r4,r4,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r6) + bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */ + blr + + .globl strcat +strcat: + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r0,1(r5) + cmpwi 0,r0,0 + bne 1b + addi r5,r5,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r5) + bne 1b + blr + + .globl strcmp +strcmp: + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r3,1(r5) + cmpwi 1,r3,0 + lbzu r0,1(r4) + subf. r3,r0,r3 + beqlr 1 + beq 1b + blr + + .globl strlen +strlen: + addi r4,r3,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + bne 1b + subf r3,r3,r4 + blr + + .globl memset +memset: + rlwimi r4,r4,8,16,23 + rlwimi r4,r4,16,0,15 + addi r6,r3,-4 + cmplwi 0,r5,4 + blt 7f + stwu r4,4(r6) + beqlr + andi. r0,r6,3 + add r5,r0,r5 + subf r6,r0,r6 + rlwinm r0,r5,32-2,2,31 + mtctr r0 + bdz 6f +1: stwu r4,4(r6) + bdnz 1b +6: andi. r5,r5,3 +7: cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r6,r6,3 +8: stbu r4,1(r6) + bdnz 8b + blr + + .globl bcopy +bcopy: + mr r6,r3 + mr r3,r4 + mr r4,r6 + b memcpy + + .globl memmove +memmove: + cmplw 0,r3,r4 + bgt backwards_memcpy + /* fall through */ + + .globl memcpy +memcpy: + rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ + addi r6,r3,-4 + addi r4,r4,-4 + beq 2f /* if less than 8 bytes to do */ + andi. r0,r6,3 /* get dest word aligned */ + mtctr r7 + bne 5f +1: lwz r7,4(r4) + lwzu r8,8(r4) + stw r7,4(r6) + stwu r8,8(r6) + bdnz 1b + andi. r5,r5,7 +2: cmplwi 0,r5,4 + blt 3f + lwzu r0,4(r4) + addi r5,r5,-4 + stwu r0,4(r6) +3: cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r4,r4,3 + addi r6,r6,3 +4: lbzu r0,1(r4) + stbu r0,1(r6) + bdnz 4b + blr +5: subfic r0,r0,4 + mtctr r0 +6: lbz r7,4(r4) + addi r4,r4,1 + stb r7,4(r6) + addi r6,r6,1 + bdnz 6b + subf r5,r0,r5 + rlwinm. r7,r5,32-3,3,31 + beq 2b + mtctr r7 + b 1b + + .globl backwards_memcpy +backwards_memcpy: + rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ + add r6,r3,r5 + add r4,r4,r5 + beq 2f + andi. r0,r6,3 + mtctr r7 + bne 5f +1: lwz r7,-4(r4) + lwzu r8,-8(r4) + stw r7,-4(r6) + stwu r8,-8(r6) + bdnz 1b + andi. r5,r5,7 +2: cmplwi 0,r5,4 + blt 3f + lwzu r0,-4(r4) + subi r5,r5,4 + stwu r0,-4(r6) +3: cmpwi 0,r5,0 + beqlr + mtctr r5 +4: lbzu r0,-1(r4) + stbu r0,-1(r6) + bdnz 4b + blr +5: mtctr r0 +6: lbzu r7,-1(r4) + stbu r7,-1(r6) + bdnz 6b + subf r5,r0,r5 + rlwinm. r7,r5,32-3,3,31 + beq 2b + mtctr r7 + b 1b + + .globl memcmp +memcmp: + cmpwi 0,r5,0 + ble- 2f + mtctr r5 + addi r6,r3,-1 + addi r4,r4,-1 +1: lbzu r3,1(r6) + lbzu r0,1(r4) + subf. r3,r0,r3 + bdnzt 2,1b + blr +2: li r3,0 + blr + + .global memchr +memchr: + cmpwi 0,r5,0 + ble- 2f + mtctr r5 + addi r3,r3,-1 +1: lbzu r0,1(r3) + cmpw 0,r0,r4 + bdnzf 2,1b + beqlr +2: li r3,0 + blr diff --git a/lib_ppc/ticks.S b/lib_ppc/ticks.S new file mode 100644 index 0000000..b8d25b7 --- /dev/null +++ b/lib_ppc/ticks.S @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2000, 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * base on code by + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * unsigned long long get_ticks(void); + * + * read timebase as "long long" + */ + .globl get_ticks +get_ticks: +1: mftbu r3 + mftb r4 + mftbu r5 + cmp 0,r3,r5 + bne 1b + blr + +/* + * Delay for a number of ticks + */ + .globl wait_ticks +wait_ticks: + mflr r8 /* save link register */ + mr r7, r3 /* save tick count */ + bl get_ticks /* Get start time */ + + /* Calculate end time */ + addc r7, r4, r7 /* Compute end time lower */ + addze r6, r3 /* and end time upper */ + + WATCHDOG_RESET /* Trigger watchdog, if needed */ +1: bl get_ticks /* Get current time */ + subfc r4, r4, r7 /* Subtract current time from end time */ + subfe. r3, r3, r6 + bge 1b /* Loop until time expired */ + + mtlr r8 /* restore link register */ + blr diff --git a/lib_ppc/time.c b/lib_ppc/time.c new file mode 100644 index 0000000..51e8e840 --- /dev/null +++ b/lib_ppc/time.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + +/* ------------------------------------------------------------------------- */ + +/* + * This function is intended for SHORT delays only. + * It will overflow at around 10 seconds @ 400MHz, + * or 20 seconds @ 200MHz. + */ +unsigned long usec2ticks(unsigned long usec) +{ + ulong ticks; + + if (usec < 1000) { + ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + } else { + ticks = ((usec / 10) * (get_tbclk() / 100000)); + } + + return (ticks); +} + +/* ------------------------------------------------------------------------- */ + +/* + * We implement the delay by converting the delay (the number of + * microseconds to wait) into a number of time base ticks; then we + * watch the time base until it has incremented by that amount. + */ +void udelay(unsigned long usec) +{ + ulong ticks = usec2ticks (usec); + + wait_ticks (ticks); +} + +/* ------------------------------------------------------------------------- */ + +unsigned long ticks2usec(unsigned long ticks) +{ + ulong tbclk = get_tbclk(); + + /* usec = ticks * 1000000 / tbclk + * Multiplication would overflow at ~4.2e3 ticks, + * so we break it up into + * usec = ( ( ticks * 1000) / tbclk ) * 1000; + */ + ticks *= 1000L; + ticks /= tbclk; + ticks *= 1000L; + + return ((ulong)ticks); +} + +/* ------------------------------------------------------------------------- */ + +int init_timebase (void) +{ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* unlock */ + immap->im_sitk.sitk_tbk = KAPWR_KEY; +#endif + + /* reset */ + asm ("li 3,0 ; mttbu 3 ; mttbl 3 ;"); + +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) + /* enable */ + immap->im_sit.sit_tbscr |= TBSCR_TBE; +#endif + return (0); +} +/* ------------------------------------------------------------------------- */ diff --git a/m68k_config.mk b/m68k_config.mk new file mode 100644 index 0000000..12bd27c --- /dev/null +++ b/m68k_config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ +PLATFORM_LDFLAGS += -n diff --git a/microblaze_config.mk b/microblaze_config.mk new file mode 100644 index 0000000..b3ac8e0 --- /dev/null +++ b/microblaze_config.mk @@ -0,0 +1,37 @@ +# +# (C) Copyright 2004 Atmark Techno, Inc. +# +# Yasushi SHOJI +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -ffixed-r31 + +ifdef CONFIG_MICROBLAZE_HARD_MULT +PLATFORM_CPPFLAGS += -mno-xl-soft-mul +endif + +ifdef CONFIG_MICROBLAZE_HARD_DIV +PLATFORM_CPPFLAGS += -mno-xl-soft-div +endif + +ifdef CONFIG_MICROBLAZE_HARD_BARREL +PLATFORM_CPPFLAGS += -mxl-barrel-shift +endif diff --git a/mips_config.mk b/mips_config.mk new file mode 100644 index 0000000..d8aa5fa --- /dev/null +++ b/mips_config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ diff --git a/mkconfig b/mkconfig new file mode 100755 index 0000000..54775d3 --- /dev/null +++ b/mkconfig @@ -0,0 +1,69 @@ +#!/bin/sh -e + +# Script to create header files and links to configure +# U-Boot for a specific board. +# +# Parameters: Target Architecture CPU Board [VENDOR] [SOC] +# +# (C) 2002 DENX Software Engineering, Wolfgang Denk +# + +APPEND=no # Default: Create new config file + +while [ $# -gt 0 ] ; do + case "$1" in + --) shift ; break ;; + -a) shift ; APPEND=yes ;; + *) break ;; + esac +done + +[ $# -lt 4 ] && exit 1 +[ $# -gt 6 ] && exit 1 + +echo "Configuring for $1 board..." + +cd ./include + +# +# Create link to architecture specific headers +# +rm -f asm +ln -s asm-$2 asm +rm -f asm-$2/arch + +if [ -z "$6" -o "$6" = "NULL" ] ; then + ln -s arch-$3 asm-$2/arch +else + ln -s arch-$6 asm-$2/arch +fi + +if [ "$2" = "arm" ] ; then + rm -f asm-$2/proc + ln -s proc-armv asm-$2/proc +fi + +# +# Create include file for Make +# +echo "ARCH = $2" > config.mk +echo "CPU = $3" >> config.mk +echo "BOARD = $4" >> config.mk + +[ "$5" ] && [ "$5" != "NULL" ] && echo "VENDOR = $5" >> config.mk + +[ "$6" ] && [ "$6" != "NULL" ] && echo "SOC = $6" >> config.mk + +# +# Create board specific header file +# +if [ "$APPEND" = "yes" ] # Append to existing config file +then + echo >> config.h +else + > config.h # Create new config file +fi +echo "/* Automatically generated - do not edit */" >>config.h +echo "#include " >>config.h + +exit 0 diff --git a/net/Makefile b/net/Makefile new file mode 100644 index 0000000..7a70489 --- /dev/null +++ b/net/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG -DDEBUG + +LIB = libnet.a + +OBJS = net.o tftp.o bootp.o rarp.o eth.o nfs.o sntp.o +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/net/bootp.c b/net/bootp.c new file mode 100644 index 0000000..8c56c08 --- /dev/null +++ b/net/bootp.c @@ -0,0 +1,947 @@ +/* + * Based on LiMon - BOOTP. + * + * Copyright 1994, 1995, 2000 Neil Russell. + * (See License) + * Copyright 2000 Roland Borde + * Copyright 2000 Paolo Scaffardi + * Copyright 2000-2004 Wolfgang Denk, wd@denx.de + */ + +#if 0 +#define DEBUG 1 /* general debug */ +#define DEBUG_BOOTP_EXT 1 /* Debug received vendor fields */ +#endif + +#ifdef DEBUG_BOOTP_EXT +#define debug_ext(fmt,args...) printf (fmt ,##args) +#else +#define debug_ext(fmt,args...) +#endif + +#include +#include +#include +#include "bootp.h" +#include "tftp.h" +#include "nfs.h" +#ifdef CONFIG_STATUS_LED +#include +#endif + +#define BOOTP_VENDOR_MAGIC 0x63825363 /* RFC1048 Magic Cookie */ + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +#define TIMEOUT 5 /* Seconds before trying BOOTP again */ +#ifndef CONFIG_NET_RETRY_COUNT +# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */ +#else +# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT) +#endif + +#define PORT_BOOTPS 67 /* BOOTP server UDP port */ +#define PORT_BOOTPC 68 /* BOOTP client UDP port */ + +#ifndef CONFIG_DHCP_MIN_EXT_LEN /* minimal length of extension list */ +#define CONFIG_DHCP_MIN_EXT_LEN 64 +#endif + +ulong BootpID; +int BootpTry; +#ifdef CONFIG_BOOTP_RANDOM_DELAY +ulong seed1, seed2; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +dhcp_state_t dhcp_state = INIT; +unsigned long dhcp_leasetime = 0; +IPaddr_t NetDHCPServerIP = 0; +static void DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len); + +/* For Debug */ +#if 0 +static char *dhcpmsg2str(int type) +{ + switch (type) { + case 1: return "DHCPDISCOVER"; break; + case 2: return "DHCPOFFER"; break; + case 3: return "DHCPREQUEST"; break; + case 4: return "DHCPDECLINE"; break; + case 5: return "DHCPACK"; break; + case 6: return "DHCPNACK"; break; + case 7: return "DHCPRELEASE"; break; + default: return "UNKNOWN/INVALID MSG TYPE"; break; + } +} +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) +extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ +extern u8 *dhcp_vendorex_proc (u8 *e); /*rtn next e if mine,else NULL */ +#endif + +#endif /* CFG_CMD_DHCP */ + +static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) +{ + Bootp_t *bp = (Bootp_t *) pkt; + int retval = 0; + + if (dest != PORT_BOOTPC || src != PORT_BOOTPS) + retval = -1; + else if (len < sizeof (Bootp_t) - OPT_SIZE) + retval = -2; + else if (bp->bp_op != OP_BOOTREQUEST && + bp->bp_op != OP_BOOTREPLY && + bp->bp_op != DHCP_OFFER && + bp->bp_op != DHCP_ACK && + bp->bp_op != DHCP_NAK ) { + retval = -3; + } + else if (bp->bp_htype != HWT_ETHER) + retval = -4; + else if (bp->bp_hlen != HWL_ETHER) + retval = -5; + else if (NetReadLong((ulong*)&bp->bp_id) != BootpID) { + retval = -6; + } + + debug ("Filtering pkt = %d\n", retval); + + return retval; +} + +/* + * Copy parameters of interest from BOOTP_REPLY/DHCP_OFFER packet + */ +static void BootpCopyNetParams(Bootp_t *bp) +{ + IPaddr_t tmp_ip; + + NetCopyIP(&NetOurIP, &bp->bp_yiaddr); + NetCopyIP(&tmp_ip, &bp->bp_siaddr); + if (tmp_ip != 0) + NetCopyIP(&NetServerIP, &bp->bp_siaddr); + memcpy (NetServerEther, ((Ethernet_t *)NetRxPkt)->et_src, 6); + if (strlen(bp->bp_file) > 0) + copy_filename (BootFile, bp->bp_file, sizeof(BootFile)); + + debug ("Bootfile: %s\n", BootFile); + + /* Propagate to environment: + * don't delete exising entry when BOOTP / DHCP reply does + * not contain a new value + */ + if (*BootFile) { + setenv ("bootfile", BootFile); + } +} + +static int truncate_sz (const char *name, int maxlen, int curlen) +{ + if (curlen >= maxlen) { + printf("*** WARNING: %s is too long (%d - max: %d) - truncated\n", + name, curlen, maxlen); + curlen = maxlen - 1; + } + return (curlen); +} + +#if !(CONFIG_COMMANDS & CFG_CMD_DHCP) + +static void BootpVendorFieldProcess (u8 * ext) +{ + int size = *(ext + 1); + + debug_ext ("[BOOTP] Processing extension %d... (%d bytes)\n", *ext, + *(ext + 1)); + + NetBootFileSize = 0; + + switch (*ext) { + /* Fixed length fields */ + case 1: /* Subnet mask */ + if (NetOurSubnetMask == 0) + NetCopyIP (&NetOurSubnetMask, (IPaddr_t *) (ext + 2)); + break; + case 2: /* Time offset - Not yet supported */ + break; + /* Variable length fields */ + case 3: /* Gateways list */ + if (NetOurGatewayIP == 0) { + NetCopyIP (&NetOurGatewayIP, (IPaddr_t *) (ext + 2)); + } + break; + case 4: /* Time server - Not yet supported */ + break; + case 5: /* IEN-116 name server - Not yet supported */ + break; + case 6: + if (NetOurDNSIP == 0) { + NetCopyIP (&NetOurDNSIP, (IPaddr_t *) (ext + 2)); + } +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) + if ((NetOurDNS2IP == 0) && (size > 4)) { + NetCopyIP (&NetOurDNS2IP, (IPaddr_t *) (ext + 2 + 4)); + } +#endif + break; + case 7: /* Log server - Not yet supported */ + break; + case 8: /* Cookie/Quote server - Not yet supported */ + break; + case 9: /* LPR server - Not yet supported */ + break; + case 10: /* Impress server - Not yet supported */ + break; + case 11: /* RPL server - Not yet supported */ + break; + case 12: /* Host name */ + if (NetOurHostName[0] == 0) { + size = truncate_sz ("Host Name", sizeof (NetOurHostName), size); + memcpy (&NetOurHostName, ext + 2, size); + NetOurHostName[size] = 0; + } + break; + case 13: /* Boot file size */ + if (size == 2) + NetBootFileSize = ntohs (*(ushort *) (ext + 2)); + else if (size == 4) + NetBootFileSize = ntohl (*(ulong *) (ext + 2)); + break; + case 14: /* Merit dump file - Not yet supported */ + break; + case 15: /* Domain name - Not yet supported */ + break; + case 16: /* Swap server - Not yet supported */ + break; + case 17: /* Root path */ + if (NetOurRootPath[0] == 0) { + size = truncate_sz ("Root Path", sizeof (NetOurRootPath), size); + memcpy (&NetOurRootPath, ext + 2, size); + NetOurRootPath[size] = 0; + } + break; + case 18: /* Extension path - Not yet supported */ + /* + * This can be used to send the information of the + * vendor area in another file that the client can + * access via TFTP. + */ + break; + /* IP host layer fields */ + case 40: /* NIS Domain name */ + if (NetOurNISDomain[0] == 0) { + size = truncate_sz ("NIS Domain Name", sizeof (NetOurNISDomain), size); + memcpy (&NetOurNISDomain, ext + 2, size); + NetOurNISDomain[size] = 0; + } + break; + /* Application layer fields */ + case 43: /* Vendor specific info - Not yet supported */ + /* + * Binary information to exchange specific + * product information. + */ + break; + /* Reserved (custom) fields (128..254) */ + } +} + +static void BootpVendorProcess (u8 * ext, int size) +{ + u8 *end = ext + size; + + debug_ext ("[BOOTP] Checking extension (%d bytes)...\n", size); + + while ((ext < end) && (*ext != 0xff)) { + if (*ext == 0) { + ext++; + } else { + u8 *opt = ext; + + ext += ext[1] + 2; + if (ext <= end) + BootpVendorFieldProcess (opt); + } + } + +#ifdef DEBUG_BOOTP_EXT + puts ("[BOOTP] Received fields: \n"); + if (NetOurSubnetMask) { + puts ("NetOurSubnetMask : "); + print_IPaddr (NetOurSubnetMask); + putc ('\n'); + } + + if (NetOurGatewayIP) { + puts ("NetOurGatewayIP : "); + print_IPaddr (NetOurGatewayIP); + putc ('\n'); + } + + if (NetBootFileSize) { + printf ("NetBootFileSize : %d\n", NetBootFileSize); + } + + if (NetOurHostName[0]) { + printf ("NetOurHostName : %s\n", NetOurHostName); + } + + if (NetOurRootPath[0]) { + printf ("NetOurRootPath : %s\n", NetOurRootPath); + } + + if (NetOurNISDomain[0]) { + printf ("NetOurNISDomain : %s\n", NetOurNISDomain); + } + + if (NetBootFileSize) { + printf ("NetBootFileSize: %d\n", NetBootFileSize); + } +#endif /* DEBUG_BOOTP_EXT */ +} +/* + * Handle a BOOTP received packet. + */ +static void +BootpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + Bootp_t *bp; + char *s; + + debug ("got BOOTP packet (src=%d, dst=%d, len=%d want_len=%d)\n", + src, dest, len, sizeof (Bootp_t)); + + bp = (Bootp_t *)pkt; + + if (BootpCheckPkt(pkt, dest, src, len)) /* Filter out pkts we don't want */ + return; + + /* + * Got a good BOOTP reply. Copy the data into our variables. + */ +#ifdef CONFIG_STATUS_LED + status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF); +#endif + + BootpCopyNetParams(bp); /* Store net parameters from reply */ + + /* Retrieve extended information (we must parse the vendor area) */ + if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)) + BootpVendorProcess((uchar *)&bp->bp_vend[4], len); + + NetSetTimeout(0, (thand_f *)0); + + debug ("Got good BOOTP\n"); + + if ((s = getenv("autoload")) != NULL) { + if (*s == 'n') { + /* + * Just use BOOTP to configure system; + * Do not use TFTP to load the bootfile. + */ + NetState = NETLOOP_SUCCESS; + return; +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + } else if (strcmp(s, "NFS") == 0) { + /* + * Use NFS to load the bootfile. + */ + NfsStart(); + return; +#endif + } + } + + TftpStart(); +} +#endif /* !CFG_CMD_DHCP */ + +/* + * Timeout on BOOTP/DHCP request. + */ +static void +BootpTimeout(void) +{ + if (BootpTry >= TIMEOUT_COUNT) { + puts ("\nRetry count exceeded; starting again\n"); + NetStartAgain (); + } else { + NetSetTimeout (TIMEOUT * CFG_HZ, BootpTimeout); + BootpRequest (); + } +} + +/* + * Initialize BOOTP extension fields in the request. + */ +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t RequestedIP) +{ + u8 *start = e; + u8 *cnt; + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) + u8 *x; +#endif +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME) + char *hostname; +#endif + + *e++ = 99; /* RFC1048 Magic Cookie */ + *e++ = 130; + *e++ = 83; + *e++ = 99; + + *e++ = 53; /* DHCP Message Type */ + *e++ = 1; + *e++ = message_type; + + *e++ = 57; /* Maximum DHCP Message Size */ + *e++ = 2; + *e++ = (576 - 312 + OPT_SIZE) >> 8; + *e++ = (576 - 312 + OPT_SIZE) & 0xff; + + if (ServerID) { + int tmp = ntohl (ServerID); + + *e++ = 54; /* ServerID */ + *e++ = 4; + *e++ = tmp >> 24; + *e++ = tmp >> 16; + *e++ = tmp >> 8; + *e++ = tmp & 0xff; + } + + if (RequestedIP) { + int tmp = ntohl (RequestedIP); + + *e++ = 50; /* Requested IP */ + *e++ = 4; + *e++ = tmp >> 24; + *e++ = tmp >> 16; + *e++ = tmp >> 8; + *e++ = tmp & 0xff; + } +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME) + if ((hostname = getenv ("hostname"))) { + int hostnamelen = strlen (hostname); + + *e++ = 12; /* Hostname */ + *e++ = hostnamelen; + memcpy (e, hostname, hostnamelen); + e += hostnamelen; + } +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) + if ((x = dhcp_vendorex_prep (e))) + return x - start; +#endif + + *e++ = 55; /* Parameter Request List */ + cnt = e++; /* Pointer to count of requested items */ + *cnt = 0; +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SUBNETMASK) + *e++ = 1; /* Subnet Mask */ + *cnt += 1; +#endif +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) + *e++ = 2; + *cnt += 1; +#endif +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_GATEWAY) + *e++ = 3; /* Router Option */ + *cnt += 1; +#endif +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS) + *e++ = 6; /* DNS Server(s) */ + *cnt += 1; +#endif +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_HOSTNAME) + *e++ = 12; /* Hostname */ + *cnt += 1; +#endif +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTFILESIZE) + *e++ = 13; /* Boot File Size */ + *cnt += 1; +#endif +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTPATH) + *e++ = 17; /* Boot path */ + *cnt += 1; +#endif +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NISDOMAIN) + *e++ = 40; /* NIS Domain name request */ + *cnt += 1; +#endif +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) + *e++ = 42; + *cnt += 1; +#endif + *e++ = 255; /* End of the list */ + + /* Pad to minimal length */ +#ifdef CONFIG_DHCP_MIN_EXT_LEN + while ((e - start) <= CONFIG_DHCP_MIN_EXT_LEN) + *e++ = 0; +#endif + + return e - start; +} + +#else /* CFG_CMD_DHCP */ +/* + * Warning: no field size check - change CONFIG_BOOTP_MASK at your own risk! + */ +static int BootpExtended (u8 * e) +{ + u8 *start = e; + + *e++ = 99; /* RFC1048 Magic Cookie */ + *e++ = 130; + *e++ = 83; + *e++ = 99; + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + *e++ = 53; /* DHCP Message Type */ + *e++ = 1; + *e++ = DHCP_DISCOVER; + + *e++ = 57; /* Maximum DHCP Message Size */ + *e++ = 2; + *e++ = (576 - 312 + OPT_SIZE) >> 16; + *e++ = (576 - 312 + OPT_SIZE) & 0xff; +#endif /* CFG_CMD_DHCP */ + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SUBNETMASK) + *e++ = 1; /* Subnet mask request */ + *e++ = 4; + e += 4; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_GATEWAY) + *e++ = 3; /* Default gateway request */ + *e++ = 4; + e += 4; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS) + *e++ = 6; /* Domain Name Server */ + *e++ = 4; + e += 4; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_HOSTNAME) + *e++ = 12; /* Host name request */ + *e++ = 32; + e += 32; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTFILESIZE) + *e++ = 13; /* Boot file size */ + *e++ = 2; + e += 2; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTPATH) + *e++ = 17; /* Boot path */ + *e++ = 32; + e += 32; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NISDOMAIN) + *e++ = 40; /* NIS Domain name request */ + *e++ = 32; + e += 32; +#endif + + *e++ = 255; /* End of the list */ + + return e - start; +} +#endif /* CFG_CMD_DHCP */ + +void +BootpRequest (void) +{ + volatile uchar *pkt, *iphdr; + Bootp_t *bp; + int ext_len, pktlen, iplen; + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + dhcp_state = INIT; +#endif + +#ifdef CONFIG_BOOTP_RANDOM_DELAY /* Random BOOTP delay */ + unsigned char bi_enetaddr[6]; + int reg; + char *e,*s; + char tmp[64]; + ulong tst1, tst2, sum, m_mask, m_value = 0; + + if (BootpTry ==0) { + /* get our mac */ + reg = getenv_r ("ethaddr", tmp, sizeof(tmp)); + s = (reg > 0) ? tmp : NULL; + + for (reg=0; reg<6; ++reg) { + bi_enetaddr[reg] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) { + s = (*e) ? e+1 : e; + } + } +#ifdef DEBUG + puts ("BootpRequest => Our Mac: "); + for (reg=0; reg<6; reg++) { + printf ("%x%c", + bi_enetaddr[reg], + reg==5 ? '\n' : ':'); + } +#endif /* DEBUG */ + + /* Mac-Manipulation 2 get seed1 */ + tst1=0; + tst2=0; + for (reg=2; reg<6; reg++) { + tst1 = tst1 << 8; + tst1 = tst1 | bi_enetaddr[reg]; + } + for (reg=0; reg<2; reg++) { + tst2 = tst2 | bi_enetaddr[reg]; + tst2 = tst2 << 8; + } + + seed1 = tst1^tst2; + + /* Mirror seed1*/ + m_mask=0x1; + for (reg=1;reg<=32;reg++) { + m_value |= (m_mask & seed1); + seed1 = seed1 >> 1; + m_value = m_value << 1; + } + seed1 = m_value; + seed2 = 0xB78D0945; + } + + /* Random Number Generator */ + + for (reg=0;reg<=0;reg++) { + sum = seed1 + seed2; + if (sum < seed1 || sum < seed2) + sum++; + seed2 = seed1; + seed1 = sum; + + if (BootpTry<=2) { /* Start with max 1024 * 1ms */ + sum = sum >> (22-BootpTry); + } else { /*After 3rd BOOTP request max 8192 * 1ms */ + sum = sum >> 19; + } + } + + printf ("Random delay: %ld ms...\n", sum); + for (reg=0; reg bp_op = OP_BOOTREQUEST; + bp->bp_htype = HWT_ETHER; + bp->bp_hlen = HWL_ETHER; + bp->bp_hops = 0; + bp->bp_secs = htons(get_timer(0) / CFG_HZ); + NetWriteIP(&bp->bp_ciaddr, 0); + NetWriteIP(&bp->bp_yiaddr, 0); + NetWriteIP(&bp->bp_siaddr, 0); + NetWriteIP(&bp->bp_giaddr, 0); + memcpy (bp->bp_chaddr, NetOurEther, 6); + copy_filename (bp->bp_file, BootFile, sizeof(bp->bp_file)); + + /* Request additional information from the BOOTP/DHCP server */ +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + ext_len = DhcpExtended((u8 *)bp->bp_vend, DHCP_DISCOVER, 0, 0); +#else + ext_len = BootpExtended((u8 *)bp->bp_vend); +#endif /* CFG_CMD_DHCP */ + + /* + * Bootp ID is the lower 4 bytes of our ethernet address + * plus the current time in HZ. + */ + BootpID = ((ulong)NetOurEther[2] << 24) + | ((ulong)NetOurEther[3] << 16) + | ((ulong)NetOurEther[4] << 8) + | (ulong)NetOurEther[5]; + BootpID += get_timer(0); + BootpID = htonl(BootpID); + NetCopyLong(&bp->bp_id, &BootpID); + + /* + * Calculate proper packet lengths taking into account the + * variable size of the options field + */ + pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + ext_len; + iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + ext_len; + NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen); + NetSetTimeout(SELECT_TIMEOUT * CFG_HZ, BootpTimeout); + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + dhcp_state = SELECTING; + NetSetHandler(DhcpHandler); +#else + NetSetHandler(BootpHandler); +#endif /* CFG_CMD_DHCP */ + NetSendPacket(NetTxPacket, pktlen); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +static void DhcpOptionsProcess (uchar * popt) +{ + uchar *end = popt + BOOTP_HDR_SIZE; + int oplen, size; + + while (popt < end && *popt != 0xff) { + oplen = *(popt + 1); + switch (*popt) { + case 1: + NetCopyIP (&NetOurSubnetMask, (popt + 2)); + break; +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) + case 2: /* Time offset */ + NetCopyLong (&NetTimeOffset, (ulong *) (popt + 2)); + NetTimeOffset = ntohl (NetTimeOffset); + break; +#endif + case 3: + NetCopyIP (&NetOurGatewayIP, (popt + 2)); + break; + case 6: + NetCopyIP (&NetOurDNSIP, (popt + 2)); +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) + if (*(popt + 1) > 4) { + NetCopyIP (&NetOurDNS2IP, (popt + 2 + 4)); + } +#endif + break; + case 12: + size = truncate_sz ("Host Name", sizeof (NetOurHostName), oplen); + memcpy (&NetOurHostName, popt + 2, size); + NetOurHostName[size] = 0; + break; + case 15: /* Ignore Domain Name Option */ + break; + case 17: + size = truncate_sz ("Root Path", sizeof (NetOurRootPath), oplen); + memcpy (&NetOurRootPath, popt + 2, size); + NetOurRootPath[size] = 0; + break; +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) + case 42: /* NTP server IP */ + NetCopyIP (&NetNtpServerIP, (popt + 2)); + break; +#endif + case 51: + NetCopyLong (&dhcp_leasetime, (ulong *) (popt + 2)); + break; + case 53: /* Ignore Message Type Option */ + break; + case 54: + NetCopyIP (&NetDHCPServerIP, (popt + 2)); + break; + case 58: /* Ignore Renewal Time Option */ + break; + case 59: /* Ignore Rebinding Time Option */ + break; + default: +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) + if (dhcp_vendorex_proc (popt)) + break; +#endif + printf ("*** Unhandled DHCP Option in OFFER/ACK: %d\n", *popt); + break; + } + popt += oplen + 2; /* Process next option */ + } +} + +static int DhcpMessageType(unsigned char *popt) +{ + if (NetReadLong((ulong*)popt) != htonl(BOOTP_VENDOR_MAGIC)) + return -1; + + popt += 4; + while ( *popt != 0xff ) { + if ( *popt == 53 ) /* DHCP Message Type */ + return *(popt + 2); + popt += *(popt + 1) + 2; /* Scan through all options */ + } + return -1; +} + +static void DhcpSendRequestPkt(Bootp_t *bp_offer) +{ + volatile uchar *pkt, *iphdr; + Bootp_t *bp; + int pktlen, iplen, extlen; + IPaddr_t OfferedIP; + + debug ("DhcpSendRequestPkt: Sending DHCPREQUEST\n"); + pkt = NetTxPacket; + memset ((void*)pkt, 0, PKTSIZE); + + pkt += NetSetEther(pkt, NetBcastAddr, PROT_IP); + + iphdr = pkt; /* We'll need this later to set proper pkt size */ + pkt += IP_HDR_SIZE; + + bp = (Bootp_t *)pkt; + bp->bp_op = OP_BOOTREQUEST; + bp->bp_htype = HWT_ETHER; + bp->bp_hlen = HWL_ETHER; + bp->bp_hops = 0; + bp->bp_secs = htons(get_timer(0) / CFG_HZ); + NetCopyIP(&bp->bp_ciaddr, &bp_offer->bp_ciaddr); /* both in network byte order */ + NetCopyIP(&bp->bp_yiaddr, &bp_offer->bp_yiaddr); + NetCopyIP(&bp->bp_siaddr, &bp_offer->bp_siaddr); + NetCopyIP(&bp->bp_giaddr, &bp_offer->bp_giaddr); + memcpy (bp->bp_chaddr, NetOurEther, 6); + + /* + * ID is the id of the OFFER packet + */ + + NetCopyLong(&bp->bp_id, &bp_offer->bp_id); + + /* + * Copy options from OFFER packet if present + */ + NetCopyIP(&OfferedIP, &bp->bp_yiaddr); + extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP); + + pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen; + iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen; + NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen); + + debug ("Transmitting DHCPREQUEST packet: len = %d\n", pktlen); + NetSendPacket(NetTxPacket, pktlen); +} + +/* + * Handle DHCP received packets. + */ +static void +DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + Bootp_t *bp = (Bootp_t *)pkt; + + debug ("DHCPHandler: got packet: (src=%d, dst=%d, len=%d) state: %d\n", + src, dest, len, dhcp_state); + + if (BootpCheckPkt(pkt, dest, src, len)) /* Filter out pkts we don't want */ + return; + + debug ("DHCPHandler: got DHCP packet: (src=%d, dst=%d, len=%d) state: %d\n", + src, dest, len, dhcp_state); + + switch (dhcp_state) { + case SELECTING: + /* + * Wait an appropriate time for any potential DHCPOFFER packets + * to arrive. Then select one, and generate DHCPREQUEST response. + * If filename is in format we recognize, assume it is a valid + * OFFER from a server we want. + */ + debug ("DHCP: state=SELECTING bp_file: \"%s\"\n", bp->bp_file); +#ifdef CFG_BOOTFILE_PREFIX + if (strncmp(bp->bp_file, + CFG_BOOTFILE_PREFIX, + strlen(CFG_BOOTFILE_PREFIX)) == 0 ) { +#endif /* CFG_BOOTFILE_PREFIX */ + + debug ("TRANSITIONING TO REQUESTING STATE\n"); + dhcp_state = REQUESTING; + + if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)) + DhcpOptionsProcess((u8 *)&bp->bp_vend[4]); + + BootpCopyNetParams(bp); /* Store net params from reply */ + + NetSetTimeout(TIMEOUT * CFG_HZ, BootpTimeout); + DhcpSendRequestPkt(bp); +#ifdef CFG_BOOTFILE_PREFIX + } +#endif /* CFG_BOOTFILE_PREFIX */ + + return; + break; + case REQUESTING: + debug ("DHCP State: REQUESTING\n"); + + if ( DhcpMessageType((u8 *)bp->bp_vend) == DHCP_ACK ) { + char *s; + + if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)) + DhcpOptionsProcess((u8 *)&bp->bp_vend[4]); + BootpCopyNetParams(bp); /* Store net params from reply */ + dhcp_state = BOUND; + puts ("DHCP client bound to address "); + print_IPaddr(NetOurIP); + putc ('\n'); + + /* Obey the 'autoload' setting */ + if ((s = getenv("autoload")) != NULL) { + if (*s == 'n') { + /* + * Just use BOOTP to configure system; + * Do not use TFTP to load the bootfile. + */ + NetState = NETLOOP_SUCCESS; + return; +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + } else if (strcmp(s, "NFS") == 0) { + /* + * Use NFS to load the bootfile. + */ + NfsStart(); + return; +#endif + } + } + TftpStart(); + return; + } + break; + default: + puts ("DHCP: INVALID STATE\n"); + break; + } + +} + +void DhcpRequest(void) +{ + BootpRequest(); +} +#endif /* CFG_CMD_DHCP */ + +#endif /* CFG_CMD_NET */ diff --git a/net/bootp.h b/net/bootp.h new file mode 100644 index 0000000..0b31639 --- /dev/null +++ b/net/bootp.h @@ -0,0 +1,95 @@ +/* + * Copied from LiMon - BOOTP. + * + * Copyright 1994, 1995, 2000 Neil Russell. + * (See License) + * Copyright 2000 Paolo Scaffardi + */ + +#ifndef __BOOTP_H__ +#define __BOOTP_H__ + +#ifndef __NET_H__ +#include +#endif /* __NET_H__ */ + +/**********************************************************************/ + +/* + * BOOTP header. + */ +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +#define OPT_SIZE 312 /* Minimum DHCP Options size per RFC2131 - results in 576 byte pkt */ +#else +#define OPT_SIZE 64 +#endif + +typedef struct +{ + uchar bp_op; /* Operation */ +# define OP_BOOTREQUEST 1 +# define OP_BOOTREPLY 2 + uchar bp_htype; /* Hardware type */ +# define HWT_ETHER 1 + uchar bp_hlen; /* Hardware address length */ +# define HWL_ETHER 6 + uchar bp_hops; /* Hop count (gateway thing) */ + ulong bp_id; /* Transaction ID */ + ushort bp_secs; /* Seconds since boot */ + ushort bp_spare1; /* Alignment */ + IPaddr_t bp_ciaddr; /* Client IP address */ + IPaddr_t bp_yiaddr; /* Your (client) IP address */ + IPaddr_t bp_siaddr; /* Server IP address */ + IPaddr_t bp_giaddr; /* Gateway IP address */ + uchar bp_chaddr[16]; /* Client hardware address */ + char bp_sname[64]; /* Server host name */ + char bp_file[128]; /* Boot file name */ + char bp_vend[OPT_SIZE]; /* Vendor information */ +} Bootp_t; + +#define BOOTP_HDR_SIZE sizeof (Bootp_t) +#define BOOTP_SIZE (ETHER_HDR_SIZE + IP_HDR_SIZE + BOOTP_HDR_SIZE) + +/**********************************************************************/ +/* + * Global functions and variables. + */ + +/* bootp.c */ +extern ulong BootpID; /* ID of cur BOOTP request */ +extern char BootFile[128]; /* Boot file name */ +extern int BootpTry; +#ifdef CONFIG_BOOTP_RANDOM_DELAY +ulong seed1, seed2; /* seed for random BOOTP delay */ +#endif + + +/* Send a BOOTP request */ +extern void BootpRequest (void); + +/****************** DHCP Support *********************/ +extern void DhcpRequest(void); + +/* DHCP States */ +typedef enum { INIT, + INIT_REBOOT, + REBOOTING, + SELECTING, + REQUESTING, + REBINDING, + BOUND, + RENEWING } dhcp_state_t; + +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 + +#define SELECT_TIMEOUT 3 /* Seconds to wait for offers */ + +/**********************************************************************/ + +#endif /* __BOOTP_H__ */ diff --git a/net/eth.c b/net/eth.c new file mode 100644 index 0000000..9341e20 --- /dev/null +++ b/net/eth.c @@ -0,0 +1,469 @@ +/* + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) + +#ifdef CFG_GT_6426x +extern int gt6426x_eth_initialize(bd_t *bis); +#endif + +extern int au1x00_enet_initialize(bd_t*); +extern int dc21x4x_initialize(bd_t*); +extern int e1000_initialize(bd_t*); +extern int eepro100_initialize(bd_t*); +extern int eth_3com_initialize(bd_t*); +extern int fec_initialize(bd_t*); +extern int inca_switch_initialize(bd_t*); +extern int mpc5xxx_fec_initialize(bd_t*); +extern int mpc8220_fec_initialize(bd_t*); +extern int mv6436x_eth_initialize(bd_t *); +extern int mv6446x_eth_initialize(bd_t *); +extern int natsemi_initialize(bd_t*); +extern int ns8382x_initialize(bd_t*); +extern int pcnet_initialize(bd_t*); +extern int plb2800_eth_initialize(bd_t*); +extern int ppc_4xx_eth_initialize(bd_t *); +extern int rtl8139_initialize(bd_t*); +extern int rtl8169_initialize(bd_t*); +extern int scc_initialize(bd_t*); +extern int skge_initialize(bd_t*); +extern int tsec_initialize(bd_t*, int, char *); + +static struct eth_device *eth_devices, *eth_current; + +struct eth_device *eth_get_dev(void) +{ + return eth_current; +} + +struct eth_device *eth_get_dev_by_name(char *devname) +{ + struct eth_device *dev, *target_dev; + + if (!eth_devices) + return NULL; + + dev = eth_devices; + target_dev = NULL; + do { + if (strcmp(devname, dev->name) == 0) { + target_dev = dev; + break; + } + dev = dev->next; + } while (dev != eth_devices); + + return target_dev; +} + +int eth_get_dev_index (void) +{ + struct eth_device *dev; + int num = 0; + + if (!eth_devices) { + return (-1); + } + + for (dev = eth_devices; dev; dev = dev->next) { + if (dev == eth_current) + break; + ++num; + } + + if (dev) { + return (num); + } + + return (0); +} + +int eth_register(struct eth_device* dev) +{ + struct eth_device *d; + + if (!eth_devices) { + eth_current = eth_devices = dev; +#ifdef CONFIG_NET_MULTI + /* update current ethernet name */ + { + char *act = getenv("ethact"); + if (act == NULL || strcmp(act, eth_current->name) != 0) + setenv("ethact", eth_current->name); + } +#endif + } else { + for (d=eth_devices; d->next!=eth_devices; d=d->next); + d->next = dev; + } + + dev->state = ETH_STATE_INIT; + dev->next = eth_devices; + + return 0; +} + +int eth_initialize(bd_t *bis) +{ + char enetvar[32], env_enetaddr[6]; + int i, eth_number = 0; + char *tmp, *end; + + eth_devices = NULL; + eth_current = NULL; + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_init(); +#endif + +#ifdef CONFIG_DB64360 + mv6436x_eth_initialize(bis); +#endif +#ifdef CONFIG_CPCI750 + mv6436x_eth_initialize(bis); +#endif +#ifdef CONFIG_DB64460 + mv6446x_eth_initialize(bis); +#endif +#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) && !defined(CONFIG_AP1000) + ppc_4xx_eth_initialize(bis); +#endif +#ifdef CONFIG_INCA_IP_SWITCH + inca_switch_initialize(bis); +#endif +#ifdef CONFIG_PLB2800_ETHER + plb2800_eth_initialize(bis); +#endif +#ifdef SCC_ENET + scc_initialize(bis); +#endif +#if defined(CONFIG_MPC5xxx_FEC) + mpc5xxx_fec_initialize(bis); +#endif +#if defined(CONFIG_MPC8220_FEC) + mpc8220_fec_initialize(bis); +#endif +#if defined(CONFIG_SK98) + skge_initialize(bis); +#endif +#if defined(CONFIG_MPC85XX_TSEC1) + tsec_initialize(bis, 0, CONFIG_MPC85XX_TSEC1_NAME); +#elif defined(CONFIG_MPC83XX_TSEC1) + tsec_initialize(bis, 0, CONFIG_MPC83XX_TSEC1_NAME); +#endif +#if defined(CONFIG_MPC85XX_TSEC2) + tsec_initialize(bis, 1, CONFIG_MPC85XX_TSEC2_NAME); +#elif defined(CONFIG_MPC83XX_TSEC2) + tsec_initialize(bis, 1, CONFIG_MPC83XX_TSEC2_NAME); +#endif +#if defined(CONFIG_MPC85XX_FEC) + tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); +#else +# if defined(CONFIG_MPC85XX_TSEC3) + tsec_initialize(bis, 2, CONFIG_MPC85XX_TSEC3_NAME); +# elif defined(CONFIG_MPC83XX_TSEC3) + tsec_initialize(bis, 2, CONFIG_MPC83XX_TSEC3_NAME); +# endif +# if defined(CONFIG_MPC85XX_TSEC4) + tsec_initialize(bis, 3, CONFIG_MPC85XX_TSEC4_NAME); +# elif defined(CONFIG_MPC83XX_TSEC4) + tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME); +# endif +#endif +#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC) + fec_initialize(bis); +#endif +#if defined(CONFIG_AU1X00) + au1x00_enet_initialize(bis); +#endif +#ifdef CONFIG_E1000 + e1000_initialize(bis); +#endif +#ifdef CONFIG_EEPRO100 + eepro100_initialize(bis); +#endif +#ifdef CONFIG_TULIP + dc21x4x_initialize(bis); +#endif +#ifdef CONFIG_3COM + eth_3com_initialize(bis); +#endif +#ifdef CONFIG_PCNET + pcnet_initialize(bis); +#endif +#ifdef CFG_GT_6426x + gt6426x_eth_initialize(bis); +#endif +#ifdef CONFIG_NATSEMI + natsemi_initialize(bis); +#endif +#ifdef CONFIG_NS8382X + ns8382x_initialize(bis); +#endif +#if defined(CONFIG_RTL8139) + rtl8139_initialize(bis); +#endif +#if defined(CONFIG_RTL8169) + rtl8169_initialize(bis); +#endif + + if (!eth_devices) { + puts ("No ethernet found.\n"); + } else { + struct eth_device *dev = eth_devices; + char *ethprime = getenv ("ethprime"); + + do { + if (eth_number) + puts (", "); + + printf("%s", dev->name); + + if (ethprime && strcmp (dev->name, ethprime) == 0) { + eth_current = dev; + puts (" [PRIME]"); + } + + sprintf(enetvar, eth_number ? "eth%daddr" : "ethaddr", eth_number); + tmp = getenv (enetvar); + + for (i=0; i<6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + + if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { + if (memcmp(dev->enetaddr, "\0\0\0\0\0\0", 6) && + memcmp(dev->enetaddr, env_enetaddr, 6)) + { + printf ("\nWarning: %s MAC addresses don't match:\n", + dev->name); + printf ("Address in SROM is " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + dev->enetaddr[0], dev->enetaddr[1], + dev->enetaddr[2], dev->enetaddr[3], + dev->enetaddr[4], dev->enetaddr[5]); + printf ("Address in environment is " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + env_enetaddr[0], env_enetaddr[1], + env_enetaddr[2], env_enetaddr[3], + env_enetaddr[4], env_enetaddr[5]); + } + + memcpy(dev->enetaddr, env_enetaddr, 6); + } + + eth_number++; + dev = dev->next; + } while(dev != eth_devices); + +#ifdef CONFIG_NET_MULTI + /* update current ethernet name */ + if (eth_current) { + char *act = getenv("ethact"); + if (act == NULL || strcmp(act, eth_current->name) != 0) + setenv("ethact", eth_current->name); + } else + setenv("ethact", NULL); +#endif + + putc ('\n'); + } + + return eth_number; +} + +void eth_set_enetaddr(int num, char *addr) { + struct eth_device *dev; + unsigned char enetaddr[6]; + char *end; + int i; + + debug ("eth_set_enetaddr(num=%d, addr=%s)\n", num, addr); + + if (!eth_devices) + return; + + for (i=0; i<6; i++) { + enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0; + if (addr) + addr = (*end) ? end+1 : end; + } + + dev = eth_devices; + while(num-- > 0) { + dev = dev->next; + + if (dev == eth_devices) + return; + } + + debug ( "Setting new HW address on %s\n" + "New Address is %02X:%02X:%02X:%02X:%02X:%02X\n", + dev->name, + enetaddr[0], enetaddr[1], + enetaddr[2], enetaddr[3], + enetaddr[4], enetaddr[5]); + + memcpy(dev->enetaddr, enetaddr, 6); +} + +int eth_init(bd_t *bis) +{ + struct eth_device* old_current; + + if (!eth_current) + return 0; + + old_current = eth_current; + do { + debug ("Trying %s\n", eth_current->name); + + if (eth_current->init(eth_current, bis)) { + eth_current->state = ETH_STATE_ACTIVE; + + return 1; + } + debug ("FAIL\n"); + + eth_try_another(0); + } while (old_current != eth_current); + + return 0; +} + +void eth_halt(void) +{ + if (!eth_current) + return; + + eth_current->halt(eth_current); + + eth_current->state = ETH_STATE_PASSIVE; +} + +int eth_send(volatile void *packet, int length) +{ + if (!eth_current) + return -1; + + return eth_current->send(eth_current, packet, length); +} + +int eth_rx(void) +{ + if (!eth_current) + return -1; + + return eth_current->recv(eth_current); +} + +void eth_try_another(int first_restart) +{ + static struct eth_device *first_failed = NULL; + + if (!eth_current) + return; + + if (first_restart) { + first_failed = eth_current; + } + + eth_current = eth_current->next; + +#ifdef CONFIG_NET_MULTI + /* update current ethernet name */ + { + char *act = getenv("ethact"); + if (act == NULL || strcmp(act, eth_current->name) != 0) + setenv("ethact", eth_current->name); + } +#endif + + if (first_failed == eth_current) { + NetRestartWrap = 1; + } +} + +#ifdef CONFIG_NET_MULTI +void eth_set_current(void) +{ + char *act; + struct eth_device* old_current; + + if (!eth_current) /* XXX no current */ + return; + + act = getenv("ethact"); + if (act != NULL) { + old_current = eth_current; + do { + if (strcmp(eth_current->name, act) == 0) + return; + eth_current = eth_current->next; + } while (old_current != eth_current); + } + + setenv("ethact", eth_current->name); +} +#endif + +char *eth_get_name (void) +{ + return (eth_current ? eth_current->name : "unknown"); +} +#elif (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI) + +extern int at91rm9200_miiphy_initialize(bd_t *bis); +extern int emac4xx_miiphy_initialize(bd_t *bis); +extern int mcf52x2_miiphy_initialize(bd_t *bis); +extern int ns7520_miiphy_initialize(bd_t *bis); + +int eth_initialize(bd_t *bis) +{ +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_init(); +#endif + +#if defined(CONFIG_AT91RM9200) + at91rm9200_miiphy_initialize(bis); +#endif +#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) \ + && !defined(CONFIG_AP1000) && !defined(CONFIG_405) + emac4xx_miiphy_initialize(bis); +#endif +#if defined(CONFIG_MCF52x2) + mcf52x2_miiphy_initialize(bis); +#endif +#if defined(CONFIG_NETARM) + ns7520_miiphy_initialize(bis); +#endif + return 0; +} +#endif diff --git a/net/net.c b/net/net.c new file mode 100644 index 0000000..37c5fb6 --- /dev/null +++ b/net/net.c @@ -0,0 +1,1755 @@ +/* + * Copied from Linux Monitor (LiMon) - Networking. + * + * Copyright 1994 - 2000 Neil Russell. + * (See License) + * Copyright 2000 Roland Borde + * Copyright 2000 Paolo Scaffardi + * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + */ + +/* + * General Desription: + * + * The user interface supports commands for BOOTP, RARP, and TFTP. + * Also, we support ARP internally. Depending on available data, + * these interact as follows: + * + * BOOTP: + * + * Prerequisites: - own ethernet address + * We want: - own IP address + * - TFTP server IP address + * - name of bootfile + * Next step: ARP + * + * RARP: + * + * Prerequisites: - own ethernet address + * We want: - own IP address + * - TFTP server IP address + * Next step: ARP + * + * ARP: + * + * Prerequisites: - own ethernet address + * - own IP address + * - TFTP server IP address + * We want: - TFTP server ethernet address + * Next step: TFTP + * + * DHCP: + * + * Prerequisites: - own ethernet address + * We want: - IP, Netmask, ServerIP, Gateway IP + * - bootfilename, lease time + * Next step: - TFTP + * + * TFTP: + * + * Prerequisites: - own ethernet address + * - own IP address + * - TFTP server IP address + * - TFTP server ethernet address + * - name of bootfile (if unknown, we use a default name + * derived from our own IP address) + * We want: - load the boot file + * Next step: none + * + * NFS: + * + * Prerequisites: - own ethernet address + * - own IP address + * - name of bootfile (if unknown, we use a default name + * derived from our own IP address) + * We want: - load the boot file + * Next step: none + * + * SNTP: + * + * Prerequisites: - own ethernet address + * - own IP address + * We want: - network time + * Next step: none + */ + + +#include +#include +#include +#include +#include "bootp.h" +#include "tftp.h" +#include "rarp.h" +#include "nfs.h" +#ifdef CONFIG_STATUS_LED +#include +#include +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) +#include "sntp.h" +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +#define ARP_TIMEOUT 5 /* Seconds before trying ARP again */ +#ifndef CONFIG_NET_RETRY_COUNT +# define ARP_TIMEOUT_COUNT 5 /* # of timeouts before giving up */ +#else +# define ARP_TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT) +#endif + +#if 0 +#define ET_DEBUG +#endif + +/** BOOTP EXTENTIONS **/ + +IPaddr_t NetOurSubnetMask=0; /* Our subnet mask (0=unknown) */ +IPaddr_t NetOurGatewayIP=0; /* Our gateways IP address */ +IPaddr_t NetOurDNSIP=0; /* Our DNS IP address */ +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) +IPaddr_t NetOurDNS2IP=0; /* Our 2nd DNS IP address */ +#endif +char NetOurNISDomain[32]={0,}; /* Our NIS domain */ +char NetOurHostName[32]={0,}; /* Our hostname */ +char NetOurRootPath[64]={0,}; /* Our bootpath */ +ushort NetBootFileSize=0; /* Our bootfile size in blocks */ + +/** END OF BOOTP EXTENTIONS **/ + +ulong NetBootFileXferSize; /* The actual transferred size of the bootfile (in bytes) */ +uchar NetOurEther[6]; /* Our ethernet address */ +uchar NetServerEther[6] = /* Boot server enet address */ + { 0, 0, 0, 0, 0, 0 }; +IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */ +IPaddr_t NetServerIP; /* Our IP addr (0 = unknown) */ +volatile uchar *NetRxPkt; /* Current receive packet */ +int NetRxPktLen; /* Current rx packet length */ +unsigned NetIPID; /* IP packet ID */ +uchar NetBcastAddr[6] = /* Ethernet bcast address */ + { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +uchar NetEtherNullAddr[6] = + { 0, 0, 0, 0, 0, 0 }; +#if (CONFIG_COMMANDS & CFG_CMD_CDP) +uchar NetCDPAddr[6] = /* Ethernet bcast address */ + { 0x01, 0x00, 0x0c, 0xcc, 0xcc, 0xcc }; +#endif +int NetState; /* Network loop state */ +#ifdef CONFIG_NET_MULTI +int NetRestartWrap = 0; /* Tried all network devices */ +static int NetRestarted = 0; /* Network loop restarted */ +static int NetDevExists = 0; /* At least one device configured */ +#endif + +/* XXX in both little & big endian machines 0xFFFF == ntohs(-1) */ +ushort NetOurVLAN = 0xFFFF; /* default is without VLAN */ +ushort NetOurNativeVLAN = 0xFFFF; /* ditto */ + +char BootFile[128]; /* Boot File name */ + +#if (CONFIG_COMMANDS & CFG_CMD_PING) +IPaddr_t NetPingIP; /* the ip address to ping */ + +static void PingStart(void); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_CDP) +static void CDPStart(void); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) +IPaddr_t NetNtpServerIP; /* NTP server IP address */ +int NetTimeOffset=0; /* offset time from UTC */ +#endif + +#ifdef CONFIG_NETCONSOLE +void NcStart(void); +int nc_input_packet(uchar *pkt, unsigned dest, unsigned src, unsigned len); +#endif + +volatile uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN]; + +volatile uchar *NetRxPackets[PKTBUFSRX]; /* Receive packets */ + +static rxhand_f *packetHandler; /* Current RX packet handler */ +static thand_f *timeHandler; /* Current timeout handler */ +static ulong timeStart; /* Time base value */ +static ulong timeDelta; /* Current timeout value */ +volatile uchar *NetTxPacket = 0; /* THE transmit packet */ + +static int net_check_prereq (proto_t protocol); + +/**********************************************************************/ + +IPaddr_t NetArpWaitPacketIP; +IPaddr_t NetArpWaitReplyIP; +uchar *NetArpWaitPacketMAC; /* MAC address of waiting packet's destination */ +uchar *NetArpWaitTxPacket; /* THE transmit packet */ +int NetArpWaitTxPacketSize; +uchar NetArpWaitPacketBuf[PKTSIZE_ALIGN + PKTALIGN]; +ulong NetArpWaitTimerStart; +int NetArpWaitTry; + +void ArpRequest (void) +{ + int i; + volatile uchar *pkt; + ARP_t *arp; + +#ifdef ET_DEBUG + printf ("ARP broadcast %d\n", NetArpWaitTry); +#endif + pkt = NetTxPacket; + + pkt += NetSetEther (pkt, NetBcastAddr, PROT_ARP); + + arp = (ARP_t *) pkt; + + arp->ar_hrd = htons (ARP_ETHER); + arp->ar_pro = htons (PROT_IP); + arp->ar_hln = 6; + arp->ar_pln = 4; + arp->ar_op = htons (ARPOP_REQUEST); + + memcpy (&arp->ar_data[0], NetOurEther, 6); /* source ET addr */ + NetWriteIP ((uchar *) & arp->ar_data[6], NetOurIP); /* source IP addr */ + for (i = 10; i < 16; ++i) { + arp->ar_data[i] = 0; /* dest ET addr = 0 */ + } + + if ((NetArpWaitPacketIP & NetOurSubnetMask) != + (NetOurIP & NetOurSubnetMask)) { + if (NetOurGatewayIP == 0) { + puts ("## Warning: gatewayip needed but not set\n"); + } + NetArpWaitReplyIP = NetOurGatewayIP; + } else { + NetArpWaitReplyIP = NetArpWaitPacketIP; + } + + NetWriteIP ((uchar *) & arp->ar_data[16], NetArpWaitReplyIP); + (void) eth_send (NetTxPacket, (pkt - NetTxPacket) + ARP_HDR_SIZE); +} + +void ArpTimeoutCheck(void) +{ + ulong t; + + if (!NetArpWaitPacketIP) + return; + + t = get_timer(0); + + /* check for arp timeout */ + if ((t - NetArpWaitTimerStart) > ARP_TIMEOUT * CFG_HZ) { + NetArpWaitTry++; + + if (NetArpWaitTry >= ARP_TIMEOUT_COUNT) { + puts ("\nARP Retry count exceeded; starting again\n"); + NetArpWaitTry = 0; + NetStartAgain(); + } else { + NetArpWaitTimerStart = t; + ArpRequest(); + } + } +} + +/**********************************************************************/ +/* + * Main network processing loop. + */ + +int +NetLoop(proto_t protocol) +{ + DECLARE_GLOBAL_DATA_PTR; + + bd_t *bd = gd->bd; + +#ifdef CONFIG_NET_MULTI + NetRestarted = 0; + NetDevExists = 0; +#endif + + /* XXX problem with bss workaround */ + NetArpWaitPacketMAC = NULL; + NetArpWaitTxPacket = NULL; + NetArpWaitPacketIP = 0; + NetArpWaitReplyIP = 0; + NetArpWaitTxPacket = NULL; + NetTxPacket = NULL; + + if (!NetTxPacket) { + int i; + /* + * Setup packet buffers, aligned correctly. + */ + NetTxPacket = &PktBuf[0] + (PKTALIGN - 1); + NetTxPacket -= (ulong)NetTxPacket % PKTALIGN; + for (i = 0; i < PKTBUFSRX; i++) { + NetRxPackets[i] = NetTxPacket + (i+1)*PKTSIZE_ALIGN; + } + } + + if (!NetArpWaitTxPacket) { + NetArpWaitTxPacket = &NetArpWaitPacketBuf[0] + (PKTALIGN - 1); + NetArpWaitTxPacket -= (ulong)NetArpWaitTxPacket % PKTALIGN; + NetArpWaitTxPacketSize = 0; + } + + eth_halt(); +#ifdef CONFIG_NET_MULTI + eth_set_current(); +#endif + if (eth_init(bd) < 0) { + eth_halt(); + return(-1); + } + +restart: +#ifdef CONFIG_NET_MULTI + memcpy (NetOurEther, eth_get_dev()->enetaddr, 6); +#else + memcpy (NetOurEther, bd->bi_enetaddr, 6); +#endif + + NetState = NETLOOP_CONTINUE; + + /* + * Start the ball rolling with the given start function. From + * here on, this code is a state machine driven by received + * packets and timer events. + */ + + switch (protocol) { +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + case NFS: +#endif +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case PING: +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) + case SNTP: +#endif + case NETCONS: + case TFTP: + NetCopyIP(&NetOurIP, &bd->bi_ip_addr); + NetOurGatewayIP = getenv_IPaddr ("gatewayip"); + NetOurSubnetMask= getenv_IPaddr ("netmask"); + NetOurVLAN = getenv_VLAN("vlan"); + NetOurNativeVLAN = getenv_VLAN("nvlan"); + + switch (protocol) { +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + case NFS: +#endif + case NETCONS: + case TFTP: + NetServerIP = getenv_IPaddr ("serverip"); + break; +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case PING: + /* nothing */ + break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) + case SNTP: + /* nothing */ + break; +#endif + default: + break; + } + + break; + case BOOTP: + case RARP: + /* + * initialize our IP addr to 0 in order to accept ANY + * IP addr assigned to us by the BOOTP / RARP server + */ + NetOurIP = 0; + NetServerIP = getenv_IPaddr ("serverip"); + NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */ + NetOurNativeVLAN = getenv_VLAN("nvlan"); + case CDP: + NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */ + NetOurNativeVLAN = getenv_VLAN("nvlan"); + break; + default: + break; + } + + switch (net_check_prereq (protocol)) { + case 1: + /* network not configured */ + eth_halt(); + return (-1); + +#ifdef CONFIG_NET_MULTI + case 2: + /* network device not configured */ + break; +#endif /* CONFIG_NET_MULTI */ + + case 0: +#ifdef CONFIG_NET_MULTI + NetDevExists = 1; +#endif + switch (protocol) { + case TFTP: + /* always use ARP to get server ethernet address */ + TftpStart(); + break; + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + case DHCP: + /* Start with a clean slate... */ + BootpTry = 0; + NetOurIP = 0; + NetServerIP = getenv_IPaddr ("serverip"); + DhcpRequest(); /* Basically same as BOOTP */ + break; +#endif /* CFG_CMD_DHCP */ + + case BOOTP: + BootpTry = 0; + BootpRequest (); + break; + + case RARP: + RarpTry = 0; + RarpRequest (); + break; +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case PING: + PingStart(); + break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + case NFS: + NfsStart(); + break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + case CDP: + CDPStart(); + break; +#endif +#ifdef CONFIG_NETCONSOLE + case NETCONS: + NcStart(); + break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) + case SNTP: + SntpStart(); + break; +#endif + default: + break; + } + + NetBootFileXferSize = 0; + break; + } + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CFG_FAULT_ECHO_LINK_DOWN) && defined(CONFIG_STATUS_LED) && defined(STATUS_LED_RED) + /* + * Echo the inverted link state to the fault LED. + */ + if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) { + status_led_set (STATUS_LED_RED, STATUS_LED_OFF); + } else { + status_led_set (STATUS_LED_RED, STATUS_LED_ON); + } +#endif /* CFG_FAULT_ECHO_LINK_DOWN, ... */ +#endif /* CONFIG_MII, ... */ + + /* + * Main packet reception loop. Loop receiving packets until + * someone sets `NetState' to a state that terminates. + */ + for (;;) { + WATCHDOG_RESET(); +#ifdef CONFIG_SHOW_ACTIVITY + { + extern void show_activity(int arg); + show_activity(1); + } +#endif + /* + * Check the ethernet for a new packet. The ethernet + * receive routine will process it. + */ + eth_rx(); + + /* + * Abort if ctrl-c was pressed. + */ + if (ctrlc()) { + eth_halt(); + puts ("\nAbort\n"); + return (-1); + } + + ArpTimeoutCheck(); + + /* + * Check for a timeout, and run the timeout handler + * if we have one. + */ + if (timeHandler && ((get_timer(0) - timeStart) > timeDelta)) { + thand_f *x; + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +# if defined(CFG_FAULT_ECHO_LINK_DOWN) && \ + defined(CONFIG_STATUS_LED) && \ + defined(STATUS_LED_RED) + /* + * Echo the inverted link state to the fault LED. + */ + if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) { + status_led_set (STATUS_LED_RED, STATUS_LED_OFF); + } else { + status_led_set (STATUS_LED_RED, STATUS_LED_ON); + } +# endif /* CFG_FAULT_ECHO_LINK_DOWN, ... */ +#endif /* CONFIG_MII, ... */ + x = timeHandler; + timeHandler = (thand_f *)0; + (*x)(); + } + + + switch (NetState) { + + case NETLOOP_RESTART: +#ifdef CONFIG_NET_MULTI + NetRestarted = 1; +#endif + goto restart; + + case NETLOOP_SUCCESS: + if (NetBootFileXferSize > 0) { + char buf[10]; + printf("Bytes transferred = %ld (%lx hex)\n", + NetBootFileXferSize, + NetBootFileXferSize); + sprintf(buf, "%lx", NetBootFileXferSize); + setenv("filesize", buf); + + sprintf(buf, "%lX", (unsigned long)load_addr); + setenv("fileaddr", buf); + } + eth_halt(); + return NetBootFileXferSize; + + case NETLOOP_FAIL: + return (-1); + } + } +} + +/**********************************************************************/ + +static void +startAgainTimeout(void) +{ + NetState = NETLOOP_RESTART; +} + +static void +startAgainHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + /* Totally ignore the packet */ +} + +void NetStartAgain (void) +{ +#ifdef CONFIG_NET_MULTI + DECLARE_GLOBAL_DATA_PTR; +#endif + char *nretry; + int noretry = 0, once = 0; + + if ((nretry = getenv ("netretry")) != NULL) { + noretry = (strcmp (nretry, "no") == 0); + once = (strcmp (nretry, "once") == 0); + } + if (noretry) { + eth_halt (); + NetState = NETLOOP_FAIL; + return; + } +#ifndef CONFIG_NET_MULTI + NetSetTimeout (10 * CFG_HZ, startAgainTimeout); + NetSetHandler (startAgainHandler); +#else /* !CONFIG_NET_MULTI*/ + eth_halt (); + eth_try_another (!NetRestarted); + eth_init (gd->bd); + if (NetRestartWrap) { + NetRestartWrap = 0; + if (NetDevExists && !once) { + NetSetTimeout (10 * CFG_HZ, startAgainTimeout); + NetSetHandler (startAgainHandler); + } else { + NetState = NETLOOP_FAIL; + } + } else { + NetState = NETLOOP_RESTART; + } +#endif /* CONFIG_NET_MULTI */ +} + +/**********************************************************************/ +/* + * Miscelaneous bits. + */ + +void +NetSetHandler(rxhand_f * f) +{ + packetHandler = f; +} + + +void +NetSetTimeout(ulong iv, thand_f * f) +{ + if (iv == 0) { + timeHandler = (thand_f *)0; + } else { + timeHandler = f; + timeStart = get_timer(0); + timeDelta = iv; + } +} + + +void +NetSendPacket(volatile uchar * pkt, int len) +{ + (void) eth_send(pkt, len); +} + +int +NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len) +{ + uchar *pkt; + + /* convert to new style broadcast */ + if (dest == 0) + dest = 0xFFFFFFFF; + + /* if broadcast, make the ether address a broadcast and don't do ARP */ + if (dest == 0xFFFFFFFF) + ether = NetBcastAddr; + + /* if MAC address was not discovered yet, save the packet and do an ARP request */ + if (memcmp(ether, NetEtherNullAddr, 6) == 0) { + +#ifdef ET_DEBUG + printf("sending ARP for %08lx\n", dest); +#endif + NetArpWaitPacketIP = dest; + NetArpWaitPacketMAC = ether; + + pkt = NetArpWaitTxPacket; + pkt += NetSetEther (pkt, NetArpWaitPacketMAC, PROT_IP); + + NetSetIP (pkt, dest, dport, sport, len); + memcpy(pkt + IP_HDR_SIZE, (uchar *)NetTxPacket + (pkt - (uchar *)NetArpWaitTxPacket) + IP_HDR_SIZE, len); + + /* size of the waiting packet */ + NetArpWaitTxPacketSize = (pkt - NetArpWaitTxPacket) + IP_HDR_SIZE + len; + + /* and do the ARP request */ + NetArpWaitTry = 1; + NetArpWaitTimerStart = get_timer(0); + ArpRequest(); + return 1; /* waiting */ + } + +#ifdef ET_DEBUG + printf("sending UDP to %08lx/%02x:%02x:%02x:%02x:%02x:%02x\n", + dest, ether[0], ether[1], ether[2], ether[3], ether[4], ether[5]); +#endif + + pkt = (uchar *)NetTxPacket; + pkt += NetSetEther (pkt, ether, PROT_IP); + NetSetIP (pkt, dest, dport, sport, len); + (void) eth_send(NetTxPacket, (pkt - NetTxPacket) + IP_HDR_SIZE + len); + + return 0; /* transmitted */ +} + +#if (CONFIG_COMMANDS & CFG_CMD_PING) +static ushort PingSeqNo; + +int PingSend(void) +{ + static uchar mac[6]; + volatile IP_t *ip; + volatile ushort *s; + uchar *pkt; + + /* XXX always send arp request */ + + memcpy(mac, NetEtherNullAddr, 6); + +#ifdef ET_DEBUG + printf("sending ARP for %08lx\n", NetPingIP); +#endif + + NetArpWaitPacketIP = NetPingIP; + NetArpWaitPacketMAC = mac; + + pkt = NetArpWaitTxPacket; + pkt += NetSetEther(pkt, mac, PROT_IP); + + ip = (volatile IP_t *)pkt; + + /* + * Construct an IP and ICMP header. (need to set no fragment bit - XXX) + */ + ip->ip_hl_v = 0x45; /* IP_HDR_SIZE / 4 (not including UDP) */ + ip->ip_tos = 0; + ip->ip_len = htons(IP_HDR_SIZE_NO_UDP + 8); + ip->ip_id = htons(NetIPID++); + ip->ip_off = htons(0x4000); /* No fragmentation */ + ip->ip_ttl = 255; + ip->ip_p = 0x01; /* ICMP */ + ip->ip_sum = 0; + NetCopyIP((void*)&ip->ip_src, &NetOurIP); /* already in network byte order */ + NetCopyIP((void*)&ip->ip_dst, &NetPingIP); /* - "" - */ + ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2); + + s = &ip->udp_src; /* XXX ICMP starts here */ + s[0] = htons(0x0800); /* echo-request, code */ + s[1] = 0; /* checksum */ + s[2] = 0; /* identifier */ + s[3] = htons(PingSeqNo++); /* sequence number */ + s[1] = ~NetCksum((uchar *)s, 8/2); + + /* size of the waiting packet */ + NetArpWaitTxPacketSize = (pkt - NetArpWaitTxPacket) + IP_HDR_SIZE_NO_UDP + 8; + + /* and do the ARP request */ + NetArpWaitTry = 1; + NetArpWaitTimerStart = get_timer(0); + ArpRequest(); + return 1; /* waiting */ +} + +static void +PingTimeout (void) +{ + eth_halt(); + NetState = NETLOOP_FAIL; /* we did not get the reply */ +} + +static void +PingHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + IPaddr_t tmp; + volatile IP_t *ip = (volatile IP_t *)pkt; + + tmp = NetReadIP((void *)&ip->ip_src); + if (tmp != NetPingIP) + return; + + NetState = NETLOOP_SUCCESS; +} + +static void PingStart(void) +{ +#if defined(CONFIG_NET_MULTI) + printf ("Using %s device\n", eth_get_name()); +#endif /* CONFIG_NET_MULTI */ + NetSetTimeout (10 * CFG_HZ, PingTimeout); + NetSetHandler (PingHandler); + + PingSend(); +} +#endif /* CFG_CMD_PING */ + +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + +#define CDP_DEVICE_ID_TLV 0x0001 +#define CDP_ADDRESS_TLV 0x0002 +#define CDP_PORT_ID_TLV 0x0003 +#define CDP_CAPABILITIES_TLV 0x0004 +#define CDP_VERSION_TLV 0x0005 +#define CDP_PLATFORM_TLV 0x0006 +#define CDP_NATIVE_VLAN_TLV 0x000a +#define CDP_APPLIANCE_VLAN_TLV 0x000e +#define CDP_TRIGGER_TLV 0x000f +#define CDP_POWER_CONSUMPTION_TLV 0x0010 +#define CDP_SYSNAME_TLV 0x0014 +#define CDP_SYSOBJECT_TLV 0x0015 +#define CDP_MANAGEMENT_ADDRESS_TLV 0x0016 + +#define CDP_TIMEOUT (CFG_HZ/4) /* one packet every 250ms */ + +static int CDPSeq; +static int CDPOK; + +ushort CDPNativeVLAN; +ushort CDPApplianceVLAN; + +static const uchar CDP_SNAP_hdr[8] = { 0xAA, 0xAA, 0x03, 0x00, 0x00, 0x0C, 0x20, 0x00 }; + +static ushort CDP_compute_csum(const uchar *buff, ushort len) +{ + ushort csum; + int odd; + ulong result = 0; + ushort leftover; + ushort *p; + + if (len > 0) { + odd = 1 & (ulong)buff; + if (odd) { + result = *buff << 8; + len--; + buff++; + } + while (len > 1) { + p = (ushort *)buff; + result += *p++; + buff = (uchar *)p; + if (result & 0x80000000) + result = (result & 0xFFFF) + (result >> 16); + len -= 2; + } + if (len) { + leftover = (signed short)(*(const signed char *)buff); + /* CISCO SUCKS big time! (and blows too): + * CDP uses the IP checksum algorithm with a twist; + * for the last byte it *sign* extends and sums. + */ + result = (result & 0xffff0000) | ((result + leftover) & 0x0000ffff); + } + while (result >> 16) + result = (result & 0xFFFF) + (result >> 16); + + if (odd) + result = ((result >> 8) & 0xff) | ((result & 0xff) << 8); + } + + /* add up 16-bit and 17-bit words for 17+c bits */ + result = (result & 0xffff) + (result >> 16); + /* add up 16-bit and 2-bit for 16+c bit */ + result = (result & 0xffff) + (result >> 16); + /* add up carry.. */ + result = (result & 0xffff) + (result >> 16); + + /* negate */ + csum = ~(ushort)result; + + /* run time endian detection */ + if (csum != htons(csum)) /* little endian */ + csum = htons(csum); + + return csum; +} + +int CDPSendTrigger(void) +{ + volatile uchar *pkt; + volatile ushort *s; + volatile ushort *cp; + Ethernet_t *et; + int len; + ushort chksum; +#if defined(CONFIG_CDP_DEVICE_ID) || defined(CONFIG_CDP_PORT_ID) || \ + defined(CONFIG_CDP_VERSION) || defined(CONFIG_CDP_PLATFORM) + char buf[32]; +#endif + + pkt = NetTxPacket; + et = (Ethernet_t *)pkt; + + /* NOTE: trigger sent not on any VLAN */ + + /* form ethernet header */ + memcpy(et->et_dest, NetCDPAddr, 6); + memcpy(et->et_src, NetOurEther, 6); + + pkt += ETHER_HDR_SIZE; + + /* SNAP header */ + memcpy((uchar *)pkt, CDP_SNAP_hdr, sizeof(CDP_SNAP_hdr)); + pkt += sizeof(CDP_SNAP_hdr); + + /* CDP header */ + *pkt++ = 0x02; /* CDP version 2 */ + *pkt++ = 180; /* TTL */ + s = (volatile ushort *)pkt; + cp = s; + *s++ = htons(0); /* checksum (0 for later calculation) */ + + /* CDP fields */ +#ifdef CONFIG_CDP_DEVICE_ID + *s++ = htons(CDP_DEVICE_ID_TLV); + *s++ = htons(CONFIG_CDP_DEVICE_ID); + memset(buf, 0, sizeof(buf)); + sprintf(buf, CONFIG_CDP_DEVICE_ID_PREFIX "%02X%02X%02X%02X%02X%02X", + NetOurEther[0] & 0xff, NetOurEther[1] & 0xff, + NetOurEther[2] & 0xff, NetOurEther[3] & 0xff, + NetOurEther[4] & 0xff, NetOurEther[5] & 0xff); + memcpy((uchar *)s, buf, 16); + s += 16 / 2; +#endif + +#ifdef CONFIG_CDP_PORT_ID + *s++ = htons(CDP_PORT_ID_TLV); + memset(buf, 0, sizeof(buf)); + sprintf(buf, CONFIG_CDP_PORT_ID, eth_get_dev_index()); + len = strlen(buf); + if (len & 1) /* make it even */ + len++; + *s++ = htons(len + 4); + memcpy((uchar *)s, buf, len); + s += len / 2; +#endif + +#ifdef CONFIG_CDP_CAPABILITIES + *s++ = htons(CDP_CAPABILITIES_TLV); + *s++ = htons(8); + *(ulong *)s = htonl(CONFIG_CDP_CAPABILITIES); + s += 2; +#endif + +#ifdef CONFIG_CDP_VERSION + *s++ = htons(CDP_VERSION_TLV); + memset(buf, 0, sizeof(buf)); + strcpy(buf, CONFIG_CDP_VERSION); + len = strlen(buf); + if (len & 1) /* make it even */ + len++; + *s++ = htons(len + 4); + memcpy((uchar *)s, buf, len); + s += len / 2; +#endif + +#ifdef CONFIG_CDP_PLATFORM + *s++ = htons(CDP_PLATFORM_TLV); + memset(buf, 0, sizeof(buf)); + strcpy(buf, CONFIG_CDP_PLATFORM); + len = strlen(buf); + if (len & 1) /* make it even */ + len++; + *s++ = htons(len + 4); + memcpy((uchar *)s, buf, len); + s += len / 2; +#endif + +#ifdef CONFIG_CDP_TRIGGER + *s++ = htons(CDP_TRIGGER_TLV); + *s++ = htons(8); + *(ulong *)s = htonl(CONFIG_CDP_TRIGGER); + s += 2; +#endif + +#ifdef CONFIG_CDP_POWER_CONSUMPTION + *s++ = htons(CDP_POWER_CONSUMPTION_TLV); + *s++ = htons(6); + *s++ = htons(CONFIG_CDP_POWER_CONSUMPTION); +#endif + + /* length of ethernet packet */ + len = (uchar *)s - ((uchar *)NetTxPacket + ETHER_HDR_SIZE); + et->et_protlen = htons(len); + + len = ETHER_HDR_SIZE + sizeof(CDP_SNAP_hdr); + chksum = CDP_compute_csum((uchar *)NetTxPacket + len, (uchar *)s - (NetTxPacket + len)); + if (chksum == 0) + chksum = 0xFFFF; + *cp = htons(chksum); + + (void) eth_send(NetTxPacket, (uchar *)s - NetTxPacket); + return 0; +} + +static void +CDPTimeout (void) +{ + CDPSeq++; + + if (CDPSeq < 3) { + NetSetTimeout (CDP_TIMEOUT, CDPTimeout); + CDPSendTrigger(); + return; + } + + /* if not OK try again */ + if (!CDPOK) + NetStartAgain(); + else + NetState = NETLOOP_SUCCESS; +} + +static void +CDPDummyHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + /* nothing */ +} + +static void +CDPHandler(const uchar * pkt, unsigned len) +{ + const uchar *t; + const ushort *ss; + ushort type, tlen; + uchar applid; + ushort vlan, nvlan; + + /* minimum size? */ + if (len < sizeof(CDP_SNAP_hdr) + 4) + goto pkt_short; + + /* check for valid CDP SNAP header */ + if (memcmp(pkt, CDP_SNAP_hdr, sizeof(CDP_SNAP_hdr)) != 0) + return; + + pkt += sizeof(CDP_SNAP_hdr); + len -= sizeof(CDP_SNAP_hdr); + + /* Version of CDP protocol must be >= 2 and TTL != 0 */ + if (pkt[0] < 0x02 || pkt[1] == 0) + return; + + /* if version is greater than 0x02 maybe we'll have a problem; output a warning */ + if (pkt[0] != 0x02) + printf("** WARNING: CDP packet received with a protocol version %d > 2\n", + pkt[0] & 0xff); + + if (CDP_compute_csum(pkt, len) != 0) + return; + + pkt += 4; + len -= 4; + + vlan = htons(-1); + nvlan = htons(-1); + while (len > 0) { + if (len < 4) + goto pkt_short; + + ss = (const ushort *)pkt; + type = ntohs(ss[0]); + tlen = ntohs(ss[1]); + if (tlen > len) { + goto pkt_short; + } + + pkt += tlen; + len -= tlen; + + ss += 2; /* point ss to the data of the TLV */ + tlen -= 4; + + switch (type) { + case CDP_DEVICE_ID_TLV: + break; + case CDP_ADDRESS_TLV: + break; + case CDP_PORT_ID_TLV: + break; + case CDP_CAPABILITIES_TLV: + break; + case CDP_VERSION_TLV: + break; + case CDP_PLATFORM_TLV: + break; + case CDP_NATIVE_VLAN_TLV: + nvlan = *ss; + break; + case CDP_APPLIANCE_VLAN_TLV: + t = (const uchar *)ss; + while (tlen > 0) { + if (tlen < 3) + goto pkt_short; + + applid = t[0]; + ss = (const ushort *)(t + 1); + +#ifdef CONFIG_CDP_APPLIANCE_VLAN_TYPE + if (applid == CONFIG_CDP_APPLIANCE_VLAN_TYPE) + vlan = *ss; +#else + vlan = ntohs(*ss); /* XXX will this work; dunno */ +#endif + t += 3; tlen -= 3; + } + break; + case CDP_TRIGGER_TLV: + break; + case CDP_POWER_CONSUMPTION_TLV: + break; + case CDP_SYSNAME_TLV: + break; + case CDP_SYSOBJECT_TLV: + break; + case CDP_MANAGEMENT_ADDRESS_TLV: + break; + } + } + + CDPApplianceVLAN = vlan; + CDPNativeVLAN = nvlan; + + CDPOK = 1; + return; + + pkt_short: + printf("** CDP packet is too short\n"); + return; +} + +static void CDPStart(void) +{ +#if defined(CONFIG_NET_MULTI) + printf ("Using %s device\n", eth_get_name()); +#endif + CDPSeq = 0; + CDPOK = 0; + + CDPNativeVLAN = htons(-1); + CDPApplianceVLAN = htons(-1); + + NetSetTimeout (CDP_TIMEOUT, CDPTimeout); + NetSetHandler (CDPDummyHandler); + + CDPSendTrigger(); +} +#endif /* CFG_CMD_CDP */ + + +void +NetReceive(volatile uchar * inpkt, int len) +{ + Ethernet_t *et; + IP_t *ip; + ARP_t *arp; + IPaddr_t tmp; + int x; + uchar *pkt; +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + int iscdp; +#endif + ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid; + +#ifdef ET_DEBUG + printf("packet received\n"); +#endif + + NetRxPkt = inpkt; + NetRxPktLen = len; + et = (Ethernet_t *)inpkt; + + /* too small packet? */ + if (len < ETHER_HDR_SIZE) + return; + +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + /* keep track if packet is CDP */ + iscdp = memcmp(et->et_dest, NetCDPAddr, 6) == 0; +#endif + + myvlanid = ntohs(NetOurVLAN); + if (myvlanid == (ushort)-1) + myvlanid = VLAN_NONE; + mynvlanid = ntohs(NetOurNativeVLAN); + if (mynvlanid == (ushort)-1) + mynvlanid = VLAN_NONE; + + x = ntohs(et->et_protlen); + +#ifdef ET_DEBUG + printf("packet received\n"); +#endif + + if (x < 1514) { + /* + * Got a 802 packet. Check the other protocol field. + */ + x = ntohs(et->et_prot); + + ip = (IP_t *)(inpkt + E802_HDR_SIZE); + len -= E802_HDR_SIZE; + + } else if (x != PROT_VLAN) { /* normal packet */ + ip = (IP_t *)(inpkt + ETHER_HDR_SIZE); + len -= ETHER_HDR_SIZE; + + } else { /* VLAN packet */ + VLAN_Ethernet_t *vet = (VLAN_Ethernet_t *)et; + +#ifdef ET_DEBUG + printf("VLAN packet received\n"); +#endif + /* too small packet? */ + if (len < VLAN_ETHER_HDR_SIZE) + return; + + /* if no VLAN active */ + if ((ntohs(NetOurVLAN) & VLAN_IDMASK) == VLAN_NONE +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + && iscdp == 0 +#endif + ) + return; + + cti = ntohs(vet->vet_tag); + vlanid = cti & VLAN_IDMASK; + x = ntohs(vet->vet_type); + + ip = (IP_t *)(inpkt + VLAN_ETHER_HDR_SIZE); + len -= VLAN_ETHER_HDR_SIZE; + } + +#ifdef ET_DEBUG + printf("Receive from protocol 0x%x\n", x); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_CDP) + if (iscdp) { + CDPHandler((uchar *)ip, len); + return; + } +#endif + + if ((myvlanid & VLAN_IDMASK) != VLAN_NONE) { + if (vlanid == VLAN_NONE) + vlanid = (mynvlanid & VLAN_IDMASK); + /* not matched? */ + if (vlanid != (myvlanid & VLAN_IDMASK)) + return; + } + + switch (x) { + + case PROT_ARP: + /* + * We have to deal with two types of ARP packets: + * - REQUEST packets will be answered by sending our + * IP address - if we know it. + * - REPLY packates are expected only after we asked + * for the TFTP server's or the gateway's ethernet + * address; so if we receive such a packet, we set + * the server ethernet address + */ +#ifdef ET_DEBUG + puts ("Got ARP\n"); +#endif + arp = (ARP_t *)ip; + if (len < ARP_HDR_SIZE) { + printf("bad length %d < %d\n", len, ARP_HDR_SIZE); + return; + } + if (ntohs(arp->ar_hrd) != ARP_ETHER) { + return; + } + if (ntohs(arp->ar_pro) != PROT_IP) { + return; + } + if (arp->ar_hln != 6) { + return; + } + if (arp->ar_pln != 4) { + return; + } + + if (NetOurIP == 0) { + return; + } + + if (NetReadIP(&arp->ar_data[16]) != NetOurIP) { + return; + } + + switch (ntohs(arp->ar_op)) { + case ARPOP_REQUEST: /* reply with our IP address */ +#ifdef ET_DEBUG + puts ("Got ARP REQUEST, return our IP\n"); +#endif + pkt = (uchar *)et; + pkt += NetSetEther(pkt, et->et_src, PROT_ARP); + arp->ar_op = htons(ARPOP_REPLY); + memcpy (&arp->ar_data[10], &arp->ar_data[0], 6); + NetCopyIP(&arp->ar_data[16], &arp->ar_data[6]); + memcpy (&arp->ar_data[ 0], NetOurEther, 6); + NetCopyIP(&arp->ar_data[ 6], &NetOurIP); + (void) eth_send((uchar *)et, (pkt - (uchar *)et) + ARP_HDR_SIZE); + return; + + case ARPOP_REPLY: /* arp reply */ + /* are we waiting for a reply */ + if (!NetArpWaitPacketIP || !NetArpWaitPacketMAC) + break; +#ifdef ET_DEBUG + printf("Got ARP REPLY, set server/gtwy eth addr (%02x:%02x:%02x:%02x:%02x:%02x)\n", + arp->ar_data[0], arp->ar_data[1], + arp->ar_data[2], arp->ar_data[3], + arp->ar_data[4], arp->ar_data[5]); +#endif + + tmp = NetReadIP(&arp->ar_data[6]); + + /* matched waiting packet's address */ + if (tmp == NetArpWaitReplyIP) { +#ifdef ET_DEBUG + puts ("Got it\n"); +#endif + /* save address for later use */ + memcpy(NetArpWaitPacketMAC, &arp->ar_data[0], 6); + +#ifdef CONFIG_NETCONSOLE + (*packetHandler)(0,0,0,0); +#endif + /* modify header, and transmit it */ + memcpy(((Ethernet_t *)NetArpWaitTxPacket)->et_dest, NetArpWaitPacketMAC, 6); + (void) eth_send(NetArpWaitTxPacket, NetArpWaitTxPacketSize); + + /* no arp request pending now */ + NetArpWaitPacketIP = 0; + NetArpWaitTxPacketSize = 0; + NetArpWaitPacketMAC = NULL; + + } + return; + default: +#ifdef ET_DEBUG + printf("Unexpected ARP opcode 0x%x\n", ntohs(arp->ar_op)); +#endif + return; + } + break; + + case PROT_RARP: +#ifdef ET_DEBUG + puts ("Got RARP\n"); +#endif + arp = (ARP_t *)ip; + if (len < ARP_HDR_SIZE) { + printf("bad length %d < %d\n", len, ARP_HDR_SIZE); + return; + } + + if ((ntohs(arp->ar_op) != RARPOP_REPLY) || + (ntohs(arp->ar_hrd) != ARP_ETHER) || + (ntohs(arp->ar_pro) != PROT_IP) || + (arp->ar_hln != 6) || (arp->ar_pln != 4)) { + + puts ("invalid RARP header\n"); + } else { + NetCopyIP(&NetOurIP, &arp->ar_data[16]); + if (NetServerIP == 0) + NetCopyIP(&NetServerIP, &arp->ar_data[ 6]); + memcpy (NetServerEther, &arp->ar_data[ 0], 6); + + (*packetHandler)(0,0,0,0); + } + break; + + case PROT_IP: +#ifdef ET_DEBUG + puts ("Got IP\n"); +#endif + if (len < IP_HDR_SIZE) { + debug ("len bad %d < %d\n", len, IP_HDR_SIZE); + return; + } + if (len < ntohs(ip->ip_len)) { + printf("len bad %d < %d\n", len, ntohs(ip->ip_len)); + return; + } + len = ntohs(ip->ip_len); +#ifdef ET_DEBUG + printf("len=%d, v=%02x\n", len, ip->ip_hl_v & 0xff); +#endif + if ((ip->ip_hl_v & 0xf0) != 0x40) { + return; + } + if (ip->ip_off & htons(0x1fff)) { /* Can't deal w/ fragments */ + return; + } + if (!NetCksumOk((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2)) { + puts ("checksum bad\n"); + return; + } + tmp = NetReadIP(&ip->ip_dst); + if (NetOurIP && tmp != NetOurIP && tmp != 0xFFFFFFFF) { + return; + } + /* + * watch for ICMP host redirects + * + * There is no real handler code (yet). We just watch + * for ICMP host redirect messages. In case anybody + * sees these messages: please contact me + * (wd@denx.de), or - even better - send me the + * necessary fixes :-) + * + * Note: in all cases where I have seen this so far + * it was a problem with the router configuration, + * for instance when a router was configured in the + * BOOTP reply, but the TFTP server was on the same + * subnet. So this is probably a warning that your + * configuration might be wrong. But I'm not really + * sure if there aren't any other situations. + */ + if (ip->ip_p == IPPROTO_ICMP) { + ICMP_t *icmph = (ICMP_t *)&(ip->udp_src); + + switch (icmph->type) { + case ICMP_REDIRECT: + if (icmph->code != ICMP_REDIR_HOST) + return; + puts (" ICMP Host Redirect to "); + print_IPaddr(icmph->un.gateway); + putc(' '); + return; +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case ICMP_ECHO_REPLY: + /* + * IP header OK. Pass the packet to the current handler. + */ + /* XXX point to ip packet */ + (*packetHandler)((uchar *)ip, 0, 0, 0); + return; +#endif + default: + return; + } + } else if (ip->ip_p != IPPROTO_UDP) { /* Only UDP packets */ + return; + } + +#ifdef CONFIG_UDP_CHECKSUM + if (ip->udp_xsum != 0) { + ulong xsum; + ushort *sumptr; + ushort sumlen; + + xsum = ip->ip_p; + xsum += (ntohs(ip->udp_len)); + xsum += (ntohl(ip->ip_src) >> 16) & 0x0000ffff; + xsum += (ntohl(ip->ip_src) >> 0) & 0x0000ffff; + xsum += (ntohl(ip->ip_dst) >> 16) & 0x0000ffff; + xsum += (ntohl(ip->ip_dst) >> 0) & 0x0000ffff; + + sumlen = ntohs(ip->udp_len); + sumptr = (ushort *) &(ip->udp_src); + + while (sumlen > 1) { + ushort sumdata; + + sumdata = *sumptr++; + xsum += ntohs(sumdata); + sumlen -= 2; + } + if (sumlen > 0) { + ushort sumdata; + + sumdata = *(unsigned char *) sumptr; + sumdata = (sumdata << 8) & 0xff00; + xsum += sumdata; + } + while ((xsum >> 16) != 0) { + xsum = (xsum & 0x0000ffff) + ((xsum >> 16) & 0x0000ffff); + } + if ((xsum != 0x00000000) && (xsum != 0x0000ffff)) { + printf(" UDP wrong checksum %08x %08x\n", xsum, ntohs(ip->udp_xsum)); + return; + } + } +#endif + +#ifdef CONFIG_NETCONSOLE + nc_input_packet((uchar *)ip +IP_HDR_SIZE, + ntohs(ip->udp_dst), + ntohs(ip->udp_src), + ntohs(ip->udp_len) - 8); +#endif + /* + * IP header OK. Pass the packet to the current handler. + */ + (*packetHandler)((uchar *)ip +IP_HDR_SIZE, + ntohs(ip->udp_dst), + ntohs(ip->udp_src), + ntohs(ip->udp_len) - 8); + break; + } +} + + +/**********************************************************************/ + +static int net_check_prereq (proto_t protocol) +{ + switch (protocol) { + /* Fall through */ +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case PING: + if (NetPingIP == 0) { + puts ("*** ERROR: ping address not given\n"); + return (1); + } + goto common; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) + case SNTP: + if (NetNtpServerIP == 0) { + puts ("*** ERROR: NTP server address not given\n"); + return (1); + } + goto common; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + case NFS: +#endif + case NETCONS: + case TFTP: + if (NetServerIP == 0) { + puts ("*** ERROR: `serverip' not set\n"); + return (1); + } +#if (CONFIG_COMMANDS & (CFG_CMD_PING | CFG_CMD_SNTP)) + common: +#endif + + if (NetOurIP == 0) { + puts ("*** ERROR: `ipaddr' not set\n"); + return (1); + } + /* Fall through */ + + case DHCP: + case RARP: + case BOOTP: + case CDP: + if (memcmp (NetOurEther, "\0\0\0\0\0\0", 6) == 0) { +#ifdef CONFIG_NET_MULTI + extern int eth_get_dev_index (void); + int num = eth_get_dev_index (); + + switch (num) { + case -1: + puts ("*** ERROR: No ethernet found.\n"); + return (1); + case 0: + puts ("*** ERROR: `ethaddr' not set\n"); + break; + default: + printf ("*** ERROR: `eth%daddr' not set\n", + num); + break; + } + + NetStartAgain (); + return (2); +#else + puts ("*** ERROR: `ethaddr' not set\n"); + return (1); +#endif + } + /* Fall through */ + default: + return (0); + } + return (0); /* OK */ +} +/**********************************************************************/ + +int +NetCksumOk(uchar * ptr, int len) +{ + return !((NetCksum(ptr, len) + 1) & 0xfffe); +} + + +unsigned +NetCksum(uchar * ptr, int len) +{ + ulong xsum; + ushort *p = (ushort *)ptr; + + xsum = 0; + while (len-- > 0) + xsum += *p++; + xsum = (xsum & 0xffff) + (xsum >> 16); + xsum = (xsum & 0xffff) + (xsum >> 16); + return (xsum & 0xffff); +} + +int +NetEthHdrSize(void) +{ + ushort myvlanid; + + myvlanid = ntohs(NetOurVLAN); + if (myvlanid == (ushort)-1) + myvlanid = VLAN_NONE; + + return ((myvlanid & VLAN_IDMASK) == VLAN_NONE) ? ETHER_HDR_SIZE : VLAN_ETHER_HDR_SIZE; +} + +int +NetSetEther(volatile uchar * xet, uchar * addr, uint prot) +{ + Ethernet_t *et = (Ethernet_t *)xet; + ushort myvlanid; + + myvlanid = ntohs(NetOurVLAN); + if (myvlanid == (ushort)-1) + myvlanid = VLAN_NONE; + + memcpy (et->et_dest, addr, 6); + memcpy (et->et_src, NetOurEther, 6); + if ((myvlanid & VLAN_IDMASK) == VLAN_NONE) { + et->et_protlen = htons(prot); + return ETHER_HDR_SIZE; + } else { + VLAN_Ethernet_t *vet = (VLAN_Ethernet_t *)xet; + + vet->vet_vlan_type = htons(PROT_VLAN); + vet->vet_tag = htons((0 << 5) | (myvlanid & VLAN_IDMASK)); + vet->vet_type = htons(prot); + return VLAN_ETHER_HDR_SIZE; + } +} + +void +NetSetIP(volatile uchar * xip, IPaddr_t dest, int dport, int sport, int len) +{ + volatile IP_t *ip = (IP_t *)xip; + + /* + * If the data is an odd number of bytes, zero the + * byte after the last byte so that the checksum + * will work. + */ + if (len & 1) + xip[IP_HDR_SIZE + len] = 0; + + /* + * Construct an IP and UDP header. + * (need to set no fragment bit - XXX) + */ + ip->ip_hl_v = 0x45; /* IP_HDR_SIZE / 4 (not including UDP) */ + ip->ip_tos = 0; + ip->ip_len = htons(IP_HDR_SIZE + len); + ip->ip_id = htons(NetIPID++); + ip->ip_off = htons(0x4000); /* No fragmentation */ + ip->ip_ttl = 255; + ip->ip_p = 17; /* UDP */ + ip->ip_sum = 0; + NetCopyIP((void*)&ip->ip_src, &NetOurIP); /* already in network byte order */ + NetCopyIP((void*)&ip->ip_dst, &dest); /* - "" - */ + ip->udp_src = htons(sport); + ip->udp_dst = htons(dport); + ip->udp_len = htons(8 + len); + ip->udp_xsum = 0; + ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2); +} + +void copy_filename (char *dst, char *src, int size) +{ + if (*src && (*src == '"')) { + ++src; + --size; + } + + while ((--size > 0) && *src && (*src != '"')) { + *dst++ = *src++; + } + *dst = '\0'; +} + +#endif /* CFG_CMD_NET */ + +void ip_to_string (IPaddr_t x, char *s) +{ + x = ntohl (x); + sprintf (s, "%d.%d.%d.%d", + (int) ((x >> 24) & 0xff), + (int) ((x >> 16) & 0xff), + (int) ((x >> 8) & 0xff), (int) ((x >> 0) & 0xff) + ); +} + +IPaddr_t string_to_ip(char *s) +{ + IPaddr_t addr; + char *e; + int i; + + if (s == NULL) + return(0); + + for (addr=0, i=0; i<4; ++i) { + ulong val = s ? simple_strtoul(s, &e, 10) : 0; + addr <<= 8; + addr |= (val & 0xFF); + if (s) { + s = (*e) ? e+1 : e; + } + } + + return (htonl(addr)); +} + +void VLAN_to_string(ushort x, char *s) +{ + x = ntohs(x); + + if (x == (ushort)-1) + x = VLAN_NONE; + + if (x == VLAN_NONE) + strcpy(s, "none"); + else + sprintf(s, "%d", x & VLAN_IDMASK); +} + +ushort string_to_VLAN(char *s) +{ + ushort id; + + if (s == NULL) + return htons(VLAN_NONE); + + if (*s < '0' || *s > '9') + id = VLAN_NONE; + else + id = (ushort)simple_strtoul(s, NULL, 10); + + return htons(id); +} + +void print_IPaddr (IPaddr_t x) +{ + char tmp[16]; + + ip_to_string (x, tmp); + + puts (tmp); +} + +IPaddr_t getenv_IPaddr (char *var) +{ + return (string_to_ip(getenv(var))); +} + +ushort getenv_VLAN(char *var) +{ + return (string_to_VLAN(getenv(var))); +} diff --git a/net/nfs.c b/net/nfs.c new file mode 100644 index 0000000..de789e1 --- /dev/null +++ b/net/nfs.c @@ -0,0 +1,778 @@ +/* + * NFS support driver - based on etherboot and U-BOOT's tftp.c + * + * Masami Komiya 2004 + * + */ + +/* NOTE: the NFS code is heavily inspired by the NetBSD netboot code (read: + * large portions are copied verbatim) as distributed in OSKit 0.97. A few + * changes were necessary to adapt the code to Etherboot and to fix several + * inconsistencies. Also the RPC message preparation is done "by hand" to + * avoid adding netsprintf() which I find hard to understand and use. */ + +/* NOTE 2: Etherboot does not care about things beyond the kernel image, so + * it loads the kernel image off the boot server (ARP_SERVER) and does not + * access the client root disk (root-path in dhcpd.conf), which would use + * ARP_ROOTSERVER. The root disk is something the operating system we are + * about to load needs to use. This is different from the OSKit 0.97 logic. */ + +/* NOTE 3: Symlink handling introduced by Anselm M Hoffmeister, 2003-July-14 + * If a symlink is encountered, it is followed as far as possible (recursion + * possible, maximum 16 steps). There is no clearing of ".."'s inside the + * path, so please DON'T DO THAT. thx. */ + +#include +#include +#include +#include +#include "nfs.h" +#include "bootp.h" + +/*#define NFS_DEBUG*/ + +#if ((CONFIG_COMMANDS & CFG_CMD_NET) && (CONFIG_COMMANDS & CFG_CMD_NFS)) + +#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */ +#define NFS_TIMEOUT 60 + +static int fs_mounted = 0; +static unsigned long rpc_id = 0; +static int nfs_offset = -1; +static int nfs_len; + +static char dirfh[NFS_FHSIZE]; /* file handle of directory */ +static char filefh[NFS_FHSIZE]; /* file handle of kernel image */ + +static int NfsDownloadState; +static IPaddr_t NfsServerIP; +static int NfsSrvMountPort; +static int NfsSrvNfsPort; +static int NfsOurPort; +static int NfsTimeoutCount; +static int NfsState; +#define STATE_PRCLOOKUP_PROG_MOUNT_REQ 1 +#define STATE_PRCLOOKUP_PROG_NFS_REQ 2 +#define STATE_MOUNT_REQ 3 +#define STATE_UMOUNT_REQ 4 +#define STATE_LOOKUP_REQ 5 +#define STATE_READ_REQ 6 +#define STATE_READLINK_REQ 7 + +static char default_filename[64]; +static char *nfs_filename; +static char *nfs_path; +static char nfs_path_buff[2048]; + +static __inline__ int +store_block (uchar * src, unsigned offset, unsigned len) +{ + ulong newsize = offset + len; +#ifdef CFG_DIRECT_FLASH_NFS + int i, rc = 0; + + for (i=0; i= flash_info[i].start[0]) { + rc = 1; + break; + } + } + + if (rc) { /* Flash is destination for this packet */ + rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len); + if (rc) { + flash_perror (rc); + return -1; + } + } else +#endif /* CFG_DIRECT_FLASH_NFS */ + { + (void)memcpy ((void *)(load_addr + offset), src, len); + } + + if (NetBootFileXferSize < (offset+len)) + NetBootFileXferSize = newsize; + return 0; +} + +static char* +basename (char *path) +{ + char *fname; + + fname = path + strlen(path) - 1; + while (fname >= path) { + if (*fname == '/') { + fname++; + break; + } + fname--; + } + return fname; +} + +static char* +dirname (char *path) +{ + char *fname; + + fname = basename (path); + --fname; + *fname = '\0'; + return path; +} + +/************************************************************************** +RPC_ADD_CREDENTIALS - Add RPC authentication/verifier entries +**************************************************************************/ +static long *rpc_add_credentials (long *p) +{ + int hl; + int hostnamelen; + char hostname[256]; + + strcpy (hostname, ""); + hostnamelen=strlen (hostname); + + /* Here's the executive summary on authentication requirements of the + * various NFS server implementations: Linux accepts both AUTH_NONE + * and AUTH_UNIX authentication (also accepts an empty hostname field + * in the AUTH_UNIX scheme). *BSD refuses AUTH_NONE, but accepts + * AUTH_UNIX (also accepts an empty hostname field in the AUTH_UNIX + * scheme). To be safe, use AUTH_UNIX and pass the hostname if we have + * it (if the BOOTP/DHCP reply didn't give one, just use an empty + * hostname). */ + + hl = (hostnamelen + 3) & ~3; + + /* Provide an AUTH_UNIX credential. */ + *p++ = htonl(1); /* AUTH_UNIX */ + *p++ = htonl(hl+20); /* auth length */ + *p++ = htonl(0); /* stamp */ + *p++ = htonl(hostnamelen); /* hostname string */ + if (hostnamelen & 3) { + *(p + hostnamelen / 4) = 0; /* add zero padding */ + } + memcpy (p, hostname, hostnamelen); + p += hl / 4; + *p++ = 0; /* uid */ + *p++ = 0; /* gid */ + *p++ = 0; /* auxiliary gid list */ + + /* Provide an AUTH_NONE verifier. */ + *p++ = 0; /* AUTH_NONE */ + *p++ = 0; /* auth length */ + + return p; +} + +/************************************************************************** +RPC_LOOKUP - Lookup RPC Port numbers +**************************************************************************/ +static void +rpc_req (int rpc_prog, int rpc_proc, uint32_t *data, int datalen) +{ + struct rpc_t pkt; + unsigned long id; + uint32_t *p; + int pktlen; + int sport; + + id = ++rpc_id; + pkt.u.call.id = htonl(id); + pkt.u.call.type = htonl(MSG_CALL); + pkt.u.call.rpcvers = htonl(2); /* use RPC version 2 */ + pkt.u.call.prog = htonl(rpc_prog); + pkt.u.call.vers = htonl(2); /* portmapper is version 2 */ + pkt.u.call.proc = htonl(rpc_proc); + p = (uint32_t *)&(pkt.u.call.data); + + if (datalen) + memcpy ((char *)p, (char *)data, datalen*sizeof(uint32_t)); + + pktlen = (char *)p + datalen*sizeof(uint32_t) - (char *)&pkt; + + memcpy ((char *)NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE, (char *)&pkt, pktlen); + + if (rpc_prog == PROG_PORTMAP) + sport = SUNRPC_PORT; + else if (rpc_prog == PROG_MOUNT) + sport = NfsSrvMountPort; + else + sport = NfsSrvNfsPort; + + NetSendUDPPacket (NetServerEther, NfsServerIP, sport, NfsOurPort, pktlen); +} + +/************************************************************************** +RPC_LOOKUP - Lookup RPC Port numbers +**************************************************************************/ +static void +rpc_lookup_req (int prog, int ver) +{ + uint32_t data[16]; + + data[0] = 0; data[1] = 0; /* auth credential */ + data[2] = 0; data[3] = 0; /* auth verifier */ + data[4] = htonl(prog); + data[5] = htonl(ver); + data[6] = htonl(17); /* IP_UDP */ + data[7] = 0; + + rpc_req (PROG_PORTMAP, PORTMAP_GETPORT, data, 8); +} + +/************************************************************************** +NFS_MOUNT - Mount an NFS Filesystem +**************************************************************************/ +static void +nfs_mount_req (char *path) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + int pathlen; + + pathlen = strlen (path); + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials((long *)p); + + *p++ = htonl(pathlen); + if (pathlen & 3) *(p + pathlen / 4) = 0; + memcpy (p, path, pathlen); + p += (pathlen + 3) / 4; + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_MOUNT, MOUNT_ADDENTRY, data, len); +} + +/************************************************************************** +NFS_UMOUNTALL - Unmount all our NFS Filesystems on the Server +**************************************************************************/ +static void +nfs_umountall_req (void) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + + if ((NfsSrvMountPort == -1) || (!fs_mounted)) { + /* Nothing mounted, nothing to umount */ + return; + } + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_MOUNT, MOUNT_UMOUNTALL, data, len); +} + +/*************************************************************************** + * NFS_READLINK (AH 2003-07-14) + * This procedure is called when read of the first block fails - + * this probably happens when it's a directory or a symlink + * In case of successful readlink(), the dirname is manipulated, + * so that inside the nfs() function a recursion can be done. + **************************************************************************/ +static void +nfs_readlink_req (void) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + + memcpy (p, filefh, NFS_FHSIZE); + p += (NFS_FHSIZE / 4); + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_NFS, NFS_READLINK, data, len); +} + +/************************************************************************** +NFS_LOOKUP - Lookup Pathname +**************************************************************************/ +static void +nfs_lookup_req (char *fname) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + int fnamelen; + + fnamelen = strlen (fname); + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + + memcpy (p, dirfh, NFS_FHSIZE); + p += (NFS_FHSIZE / 4); + *p++ = htonl(fnamelen); + if (fnamelen & 3) *(p + fnamelen / 4) = 0; + memcpy (p, fname, fnamelen); + p += (fnamelen + 3) / 4; + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_NFS, NFS_LOOKUP, data, len); +} + +/************************************************************************** +NFS_READ - Read File on NFS Server +**************************************************************************/ +static void +nfs_read_req (int offset, int readlen) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + + memcpy (p, filefh, NFS_FHSIZE); + p += (NFS_FHSIZE / 4); + *p++ = htonl(offset); + *p++ = htonl(readlen); + *p++ = 0; + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_NFS, NFS_READ, data, len); +} + +/************************************************************************** +RPC request dispatcher +**************************************************************************/ + +static void +NfsSend (void) +{ +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + switch (NfsState) { + case STATE_PRCLOOKUP_PROG_MOUNT_REQ: + rpc_lookup_req (PROG_MOUNT, 1); + break; + case STATE_PRCLOOKUP_PROG_NFS_REQ: + rpc_lookup_req (PROG_NFS, 2); + break; + case STATE_MOUNT_REQ: + nfs_mount_req (nfs_path); + break; + case STATE_UMOUNT_REQ: + nfs_umountall_req (); + break; + case STATE_LOOKUP_REQ: + nfs_lookup_req (nfs_filename); + break; + case STATE_READ_REQ: + nfs_read_req (nfs_offset, nfs_len); + break; + case STATE_READLINK_REQ: + nfs_readlink_req (); + break; + } +} + +/************************************************************************** +Handlers for the reply from server +**************************************************************************/ + +static int +rpc_lookup_reply (int prog, uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.astatus) { + return -1; + } + + switch (prog) { + case PROG_MOUNT: + NfsSrvMountPort = ntohl(rpc_pkt.u.reply.data[0]); + break; + case PROG_NFS: + NfsSrvNfsPort = ntohl(rpc_pkt.u.reply.data[0]); + break; + } + + return 0; +} + +static int +nfs_mount_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.data[0]) { + return -1; + } + + fs_mounted = 1; + memcpy (dirfh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE); + + return 0; +} + +static int +nfs_umountall_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus) { + return -1; + } + + fs_mounted = 0; + memset (dirfh, 0, sizeof(dirfh)); + + return 0; +} + +static int +nfs_lookup_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.data[0]) { + return -1; + } + + memcpy (filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE); + + return 0; +} + +static int +nfs_readlink_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + int rlen; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.data[0]) { + return -1; + } + + rlen = ntohl (rpc_pkt.u.reply.data[1]); /* new path length */ + + if (*((char *)&(rpc_pkt.u.reply.data[2])) != '/') { + int pathlen; + strcat (nfs_path, "/"); + pathlen = strlen(nfs_path); + memcpy (nfs_path+pathlen, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen); + nfs_path[pathlen+rlen+1] = 0; + } else { + memcpy (nfs_path, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen); + nfs_path[rlen] = 0; + } + return 0; +} + +static int +nfs_read_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + int rlen; + +#ifdef NFS_DEBUG_nop + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((uchar *)&rpc_pkt, pkt, sizeof(rpc_pkt.u.reply)); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.data[0]) { + if (rpc_pkt.u.reply.rstatus) { + return -9999; + } + if (rpc_pkt.u.reply.astatus) { + return -9999; + } + return -ntohl(rpc_pkt.u.reply.data[0]);; + } + + if ((nfs_offset!=0) && !((nfs_offset) % (NFS_READ_SIZE/2*10*HASHES_PER_LINE))) { + puts ("\n\t "); + } + if (!(nfs_offset % ((NFS_READ_SIZE/2)*10))) { + putc ('#'); + } + + rlen = ntohl(rpc_pkt.u.reply.data[18]); + if ( store_block ((uchar *)pkt+sizeof(rpc_pkt.u.reply), nfs_offset, rlen) ) + return -9999; + + return rlen; +} + +/************************************************************************** +Interfaces of U-BOOT +**************************************************************************/ + +static void +NfsTimeout (void) +{ + puts ("Timeout\n"); + NetState = NETLOOP_FAIL; + return; +} + +static void +NfsHandler (uchar *pkt, unsigned dest, unsigned src, unsigned len) +{ + int rlen; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + if (dest != NfsOurPort) return; + + switch (NfsState) { + case STATE_PRCLOOKUP_PROG_MOUNT_REQ: + rpc_lookup_reply (PROG_MOUNT, pkt, len); + NfsState = STATE_PRCLOOKUP_PROG_NFS_REQ; + NfsSend (); + break; + + case STATE_PRCLOOKUP_PROG_NFS_REQ: + rpc_lookup_reply (PROG_NFS, pkt, len); + NfsState = STATE_MOUNT_REQ; + NfsSend (); + break; + + case STATE_MOUNT_REQ: + if (nfs_mount_reply(pkt, len)) { + puts ("*** ERROR: Cannot mount\n"); + /* just to be sure... */ + NfsState = STATE_UMOUNT_REQ; + NfsSend (); + } else { + NfsState = STATE_LOOKUP_REQ; + NfsSend (); + } + break; + + case STATE_UMOUNT_REQ: + if (nfs_umountall_reply(pkt, len)) { + puts ("*** ERROR: Cannot umount\n"); + NetState = NETLOOP_FAIL; + } else { + puts ("\ndone\n"); + NetState = NfsDownloadState; + } + break; + + case STATE_LOOKUP_REQ: + if (nfs_lookup_reply(pkt, len)) { + puts ("*** ERROR: File lookup fail\n"); + NfsState = STATE_UMOUNT_REQ; + NfsSend (); + } else { + NfsState = STATE_READ_REQ; + nfs_offset = 0; + nfs_len = NFS_READ_SIZE; + NfsSend (); + } + break; + + case STATE_READLINK_REQ: + if (nfs_readlink_reply(pkt, len)) { + puts ("*** ERROR: Symlink fail\n"); + NfsState = STATE_UMOUNT_REQ; + NfsSend (); + } else { +#ifdef NFS_DEBUG + printf ("Symlink --> %s\n", nfs_path); +#endif + nfs_filename = basename (nfs_path); + nfs_path = dirname (nfs_path); + + NfsState = STATE_MOUNT_REQ; + NfsSend (); + } + break; + + case STATE_READ_REQ: + rlen = nfs_read_reply (pkt, len); + NetSetTimeout (NFS_TIMEOUT * CFG_HZ, NfsTimeout); + if (rlen > 0) { + nfs_offset += rlen; + NfsSend (); + } + else if ((rlen == -NFSERR_ISDIR)||(rlen == -NFSERR_INVAL)) { + /* symbolic link */ + NfsState = STATE_READLINK_REQ; + NfsSend (); + } else { + if ( ! rlen ) NfsDownloadState = NETLOOP_SUCCESS; + NfsState = STATE_UMOUNT_REQ; + NfsSend (); + } + break; + } +} + + +void +NfsStart (void) +{ +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + NfsDownloadState = NETLOOP_FAIL; + + NfsServerIP = NetServerIP; + nfs_path = (char *)nfs_path_buff; + + if (nfs_path == NULL) { + NetState = NETLOOP_FAIL; + puts ("*** ERROR: Fail allocate memory\n"); + return; + } + + if (BootFile[0] == '\0') { + sprintf (default_filename, "/nfsroot/%02lX%02lX%02lX%02lX.img", + NetOurIP & 0xFF, + (NetOurIP >> 8) & 0xFF, + (NetOurIP >> 16) & 0xFF, + (NetOurIP >> 24) & 0xFF ); + strcpy (nfs_path, default_filename); + + printf ("*** Warning: no boot file name; using '%s'\n", + nfs_path); + } else { + char *p=BootFile; + + p = strchr (p, ':'); + + if (p != NULL) { + NfsServerIP = string_to_ip (BootFile); + ++p; + strcpy (nfs_path, p); + } else { + strcpy (nfs_path, BootFile); + } + } + + nfs_filename = basename (nfs_path); + nfs_path = dirname (nfs_path); + +#if defined(CONFIG_NET_MULTI) + printf ("Using %s device\n", eth_get_name()); +#endif + + puts ("File transfer via NFS from server "); print_IPaddr (NfsServerIP); + puts ("; our IP address is "); print_IPaddr (NetOurIP); + + /* Check if we need to send across this subnet */ + if (NetOurGatewayIP && NetOurSubnetMask) { + IPaddr_t OurNet = NetOurIP & NetOurSubnetMask; + IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask; + + if (OurNet != ServerNet) { + puts ("; sending through gateway "); + print_IPaddr (NetOurGatewayIP) ; + } + } + printf ("\nFilename '%s/%s'.", nfs_path, nfs_filename); + + if (NetBootFileSize) { + printf (" Size is 0x%x Bytes = ", NetBootFileSize<<9); + print_size (NetBootFileSize<<9, ""); + } + printf ("\nLoad address: 0x%lx\n" + "Loading: *\b", load_addr); + + NetSetTimeout (NFS_TIMEOUT * CFG_HZ, NfsTimeout); + NetSetHandler (NfsHandler); + + NfsTimeoutCount = 0; + NfsState = STATE_PRCLOOKUP_PROG_MOUNT_REQ; + + /*NfsOurPort = 4096 + (get_ticks() % 3072);*/ + /*FIX ME !!!*/ + NfsOurPort = 1000; + + /* zero out server ether in case the server ip has changed */ + memset (NetServerEther, 0, 6); + + NfsSend (); +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NFS */ diff --git a/net/nfs.h b/net/nfs.h new file mode 100644 index 0000000..712afa0 --- /dev/null +++ b/net/nfs.h @@ -0,0 +1,74 @@ +/* + * (C) Masami Komiya 2004 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +#ifndef __NFS_H__ +#define __NFS_H__ + +#define SUNRPC_PORT 111 + +#define PROG_PORTMAP 100000 +#define PROG_NFS 100003 +#define PROG_MOUNT 100005 + +#define MSG_CALL 0 +#define MSG_REPLY 1 + +#define PORTMAP_GETPORT 3 + +#define MOUNT_ADDENTRY 1 +#define MOUNT_UMOUNTALL 4 + +#define NFS_LOOKUP 4 +#define NFS_READLINK 5 +#define NFS_READ 6 + +#define NFS_FHSIZE 32 + +#define NFSERR_PERM 1 +#define NFSERR_NOENT 2 +#define NFSERR_ACCES 13 +#define NFSERR_ISDIR 21 +#define NFSERR_INVAL 22 + +/* Block size used for NFS read accesses. A RPC reply packet (including all + * headers) must fit within a single Ethernet frame to avoid fragmentation. + * Chosen to be a power of two, as most NFS servers are optimized for this. */ +#define NFS_READ_SIZE 1024 + +#define NFS_MAXLINKDEPTH 16 + +struct rpc_t { + union { + uint8_t data[2048]; + struct { + uint32_t id; + uint32_t type; + uint32_t rpcvers; + uint32_t prog; + uint32_t vers; + uint32_t proc; + uint32_t data[1]; + } call; + struct { + uint32_t id; + uint32_t type; + uint32_t rstatus; + uint32_t verifier; + uint32_t v2; + uint32_t astatus; + uint32_t data[19]; + } reply; + } u; +}; +extern void NfsStart (void); /* Begin NFS */ + + +/**********************************************************************/ + +#endif /* __NFS_H__ */ diff --git a/net/rarp.c b/net/rarp.c new file mode 100644 index 0000000..1ba60e8 --- /dev/null +++ b/net/rarp.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "nfs.h" +#include "bootp.h" +#include "rarp.h" +#include "tftp.h" + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +#define TIMEOUT 5 /* Seconds before trying BOOTP again */ +#ifndef CONFIG_NET_RETRY_COUNT +# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */ +#else +# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT) +#endif + + +int RarpTry; + +/* + * Handle a RARP received packet. + */ +static void +RarpHandler(uchar * dummi0, unsigned dummi1, unsigned dummi2, unsigned dummi3) +{ + char *s; +#ifdef DEBUG + puts ("Got good RARP\n"); +#endif + if ((s = getenv("autoload")) != NULL) { + if (*s == 'n') { + /* + * Just use RARP to configure system; + * Do not use TFTP/NFS to to load the bootfile. + */ + NetState = NETLOOP_SUCCESS; + return; +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + } else if ((s != NULL) && !strcmp(s, "NFS")) { + NfsStart(); + return; +#endif + } + } + TftpStart (); +} + + +/* + * Timeout on BOOTP request. + */ +static void +RarpTimeout(void) +{ + if (RarpTry >= TIMEOUT_COUNT) { + puts ("\nRetry count exceeded; starting again\n"); + NetStartAgain (); + } else { + NetSetTimeout (TIMEOUT * CFG_HZ, RarpTimeout); + RarpRequest (); + } +} + + +void +RarpRequest (void) +{ + int i; + volatile uchar *pkt; + ARP_t * rarp; + + printf("RARP broadcast %d\n", ++RarpTry); + pkt = NetTxPacket; + + pkt += NetSetEther(pkt, NetBcastAddr, PROT_RARP); + + rarp = (ARP_t *)pkt; + + rarp->ar_hrd = htons (ARP_ETHER); + rarp->ar_pro = htons (PROT_IP); + rarp->ar_hln = 6; + rarp->ar_pln = 4; + rarp->ar_op = htons (RARPOP_REQUEST); + memcpy (&rarp->ar_data[0], NetOurEther, 6); /* source ET addr */ + memcpy (&rarp->ar_data[6], &NetOurIP, 4); /* source IP addr */ + memcpy (&rarp->ar_data[10], NetOurEther, 6); /* dest ET addr = source ET addr ??*/ + /* dest. IP addr set to broadcast */ + for (i = 0; i <= 3; i++) { + rarp->ar_data[16 + i] = 0xff; + } + + NetSendPacket(NetTxPacket, (pkt - NetTxPacket) + ARP_HDR_SIZE); + + NetSetTimeout(TIMEOUT * CFG_HZ, RarpTimeout); + NetSetHandler(RarpHandler); +} + +#endif /* CFG_CMD_NET */ diff --git a/net/rarp.h b/net/rarp.h new file mode 100644 index 0000000..0c16d46 --- /dev/null +++ b/net/rarp.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __RARP_H__ +#define __RARP_H__ + +#ifndef __NET_H__ +#include +#endif /* __NET_H__ */ + + +/**********************************************************************/ +/* + * Global functions and variables. + */ + +extern int RarpTry; + +extern void RarpRequest (void); /* Send a RARP request */ + +/**********************************************************************/ + +#endif /* __RARP_H__ */ diff --git a/net/sntp.c b/net/sntp.c new file mode 100644 index 0000000..db8c2c2 --- /dev/null +++ b/net/sntp.c @@ -0,0 +1,92 @@ +/* + * SNTP support driver + * + * Masami Komiya 2005 + * + */ + +#include +#include +#include +#include + +#include "sntp.h" + +#if ((CONFIG_COMMANDS & CFG_CMD_NET) && (CONFIG_COMMANDS & CFG_CMD_SNTP)) + +#define SNTP_TIMEOUT 10 + +static int SntpOurPort; + +static void +SntpSend (void) +{ + struct sntp_pkt_t pkt; + int pktlen = SNTP_PACKET_LEN; + int sport; + + debug ("%s\n", __FUNCTION__); + + memset (&pkt, 0, sizeof(pkt)); + + pkt.li = NTP_LI_NOLEAP; + pkt.vn = NTP_VERSION; + pkt.mode = NTP_MODE_CLIENT; + + memcpy ((char *)NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE, (char *)&pkt, pktlen); + + SntpOurPort = 10000 + (get_timer(0) % 4096); + sport = NTP_SERVICE_PORT; + + NetSendUDPPacket (NetServerEther, NetNtpServerIP, sport, SntpOurPort, pktlen); +} + +static void +SntpTimeout (void) +{ + puts ("Timeout\n"); + NetState = NETLOOP_FAIL; + return; +} + +static void +SntpHandler (uchar *pkt, unsigned dest, unsigned src, unsigned len) +{ + struct sntp_pkt_t *rpktp = (struct sntp_pkt_t *)pkt; + struct rtc_time tm; + ulong seconds; + + debug ("%s\n", __FUNCTION__); + + if (dest != SntpOurPort) return; + + /* + * As the RTC's used in U-Boot sepport second resolution only + * we simply ignore the sub-second field. + */ + memcpy (&seconds, &rpktp->transmit_timestamp, sizeof(ulong)); + + to_tm(ntohl(seconds) - 2208988800UL + NetTimeOffset, &tm); +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + rtc_set (&tm); +#endif + printf ("Date: %4d-%02d-%02d Time: %2d:%02d:%02d\n", + tm.tm_year, tm.tm_mon, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec); + + NetState = NETLOOP_SUCCESS; +} + +void +SntpStart (void) +{ + debug ("%s\n", __FUNCTION__); + + NetSetTimeout (SNTP_TIMEOUT * CFG_HZ, SntpTimeout); + NetSetHandler(SntpHandler); + memset (NetServerEther, 0, 6); + + SntpSend (); +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_SNTP */ diff --git a/net/sntp.h b/net/sntp.h new file mode 100644 index 0000000..8a097bf --- /dev/null +++ b/net/sntp.h @@ -0,0 +1,61 @@ +/* + * (C) Masami Komiya 2005 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +#ifndef __SNTP_H__ +#define __SNTP_H__ + +#define NTP_SERVICE_PORT 123 +#define SNTP_PACKET_LEN 48 + + +/* Leap Indicator */ +#define NTP_LI_NOLEAP 0x0 +#define NTP_LI_61SECS 0x1 +#define NTP_LI_59SECS 0x2 +#define NTP_LI_ALARM 0x3 + +/* Version */ + +#define NTP_VERSION 4 + +/* Mode */ +#define NTP_MODE_RESERVED 0 +#define NTP_MODE_SYMACTIVE 1 /* Symmetric Active */ +#define NTP_MODE_SYMPASSIVE 2 /* Symmetric Passive */ +#define NTP_MODE_CLIENT 3 +#define NTP_MODE_SERVER 4 +#define NTP_MODE_BROADCAST 5 +#define NTP_MODE_NTPCTRL 6 /* Reserved for NTP control message */ +#define NTP_MODE_PRIVATE 7 /* Reserved for private use */ + +struct sntp_pkt_t { +#if __LITTLE_ENDIAN + uchar mode:3; + uchar vn:3; + uchar li:2; +#else + uchar li:2; + uchar vn:3; + uchar mode:3; +#endif + uchar stratum; + uchar poll; + uchar precision; + uint root_delay; + uint root_dispersion; + uint reference_id; + unsigned long long reference_timestamp; + unsigned long long originate_timestamp; + unsigned long long receive_timestamp; + unsigned long long transmit_timestamp; +}; + +extern void SntpStart (void); /* Begin SNTP */ + +#endif /* __SNTP_H__ */ diff --git a/net/tftp.c b/net/tftp.c new file mode 100644 index 0000000..eca21d2 --- /dev/null +++ b/net/tftp.c @@ -0,0 +1,389 @@ +/* + * Copyright 1994, 1995, 2000 Neil Russell. + * (See License) + * Copyright 2000, 2001 DENX Software Engineering, Wolfgang Denk, wd@denx.de + */ + +#include +#include +#include +#include "tftp.h" +#include "bootp.h" + +#undef ET_DEBUG + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */ +#define TIMEOUT 5 /* Seconds to timeout for a lost pkt */ +#ifndef CONFIG_NET_RETRY_COUNT +# define TIMEOUT_COUNT 10 /* # of timeouts before giving up */ +#else +# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT * 2) +#endif + /* (for checking the image size) */ +#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */ + +/* + * TFTP operations. + */ +#define TFTP_RRQ 1 +#define TFTP_WRQ 2 +#define TFTP_DATA 3 +#define TFTP_ACK 4 +#define TFTP_ERROR 5 +#define TFTP_OACK 6 + + +static int TftpServerPort; /* The UDP port at their end */ +static int TftpOurPort; /* The UDP port at our end */ +static int TftpTimeoutCount; +static ulong TftpBlock; /* packet sequence number */ +static ulong TftpLastBlock; /* last packet sequence number received */ +static ulong TftpBlockWrap; /* count of sequence number wraparounds */ +static ulong TftpBlockWrapOffset; /* memory offset due to wrapping */ +static int TftpState; + +#define STATE_RRQ 1 +#define STATE_DATA 2 +#define STATE_TOO_LARGE 3 +#define STATE_BAD_MAGIC 4 +#define STATE_OACK 5 + +#define TFTP_BLOCK_SIZE 512 /* default TFTP block size */ +#define TFTP_SEQUENCE_SIZE ((ulong)(1<<16)) /* sequence number is 16 bit */ + +#define DEFAULT_NAME_LEN (8 + 4 + 1) +static char default_filename[DEFAULT_NAME_LEN]; +static char *tftp_filename; + +#ifdef CFG_DIRECT_FLASH_TFTP +extern flash_info_t flash_info[]; +#endif + +static __inline__ void +store_block (unsigned block, uchar * src, unsigned len) +{ + ulong offset = block * TFTP_BLOCK_SIZE + TftpBlockWrapOffset; + ulong newsize = offset + len; +#ifdef CFG_DIRECT_FLASH_TFTP + int i, rc = 0; + + for (i=0; i= flash_info[i].start[0]) { + rc = 1; + break; + } + } + + if (rc) { /* Flash is destination for this packet */ + rc = flash_write ((char *)src, (ulong)(load_addr+offset), len); + if (rc) { + flash_perror (rc); + NetState = NETLOOP_FAIL; + return; + } + } + else +#endif /* CFG_DIRECT_FLASH_TFTP */ + { + (void)memcpy((void *)(load_addr + offset), src, len); + } + + if (NetBootFileXferSize < newsize) + NetBootFileXferSize = newsize; +} + +static void TftpSend (void); +static void TftpTimeout (void); + +/**********************************************************************/ + +static void +TftpSend (void) +{ + volatile uchar * pkt; + volatile uchar * xp; + int len = 0; + volatile ushort *s; + + /* + * We will always be sending some sort of packet, so + * cobble together the packet headers now. + */ + pkt = NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE; + + switch (TftpState) { + + case STATE_RRQ: + xp = pkt; + s = (ushort *)pkt; + *s++ = htons(TFTP_RRQ); + pkt = (uchar *)s; + strcpy ((char *)pkt, tftp_filename); + pkt += strlen(tftp_filename) + 1; + strcpy ((char *)pkt, "octet"); + pkt += 5 /*strlen("octet")*/ + 1; + strcpy ((char *)pkt, "timeout"); + pkt += 7 /*strlen("timeout")*/ + 1; + sprintf((char *)pkt, "%d", TIMEOUT); +#ifdef ET_DEBUG + printf("send option \"timeout %s\"\n", (char *)pkt); +#endif + pkt += strlen((char *)pkt) + 1; + len = pkt - xp; + break; + + case STATE_DATA: + case STATE_OACK: + xp = pkt; + s = (ushort *)pkt; + *s++ = htons(TFTP_ACK); + *s++ = htons(TftpBlock); + pkt = (uchar *)s; + len = pkt - xp; + break; + + case STATE_TOO_LARGE: + xp = pkt; + s = (ushort *)pkt; + *s++ = htons(TFTP_ERROR); + *s++ = htons(3); + pkt = (uchar *)s; + strcpy ((char *)pkt, "File too large"); + pkt += 14 /*strlen("File too large")*/ + 1; + len = pkt - xp; + break; + + case STATE_BAD_MAGIC: + xp = pkt; + s = (ushort *)pkt; + *s++ = htons(TFTP_ERROR); + *s++ = htons(2); + pkt = (uchar *)s; + strcpy ((char *)pkt, "File has bad magic"); + pkt += 18 /*strlen("File has bad magic")*/ + 1; + len = pkt - xp; + break; + } + + NetSendUDPPacket(NetServerEther, NetServerIP, TftpServerPort, TftpOurPort, len); +} + + +static void +TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + ushort proto; + ushort *s; + + if (dest != TftpOurPort) { + return; + } + if (TftpState != STATE_RRQ && src != TftpServerPort) { + return; + } + + if (len < 2) { + return; + } + len -= 2; + /* warning: don't use increment (++) in ntohs() macros!! */ + s = (ushort *)pkt; + proto = *s++; + pkt = (uchar *)s; + switch (ntohs(proto)) { + + case TFTP_RRQ: + case TFTP_WRQ: + case TFTP_ACK: + break; + default: + break; + + case TFTP_OACK: +#ifdef ET_DEBUG + printf("Got OACK: %s %s\n", pkt, pkt+strlen(pkt)+1); +#endif + TftpState = STATE_OACK; + TftpServerPort = src; + TftpSend (); /* Send ACK */ + break; + case TFTP_DATA: + if (len < 2) + return; + len -= 2; + TftpBlock = ntohs(*(ushort *)pkt); + + /* + * RFC1350 specifies that the first data packet will + * have sequence number 1. If we receive a sequence + * number of 0 this means that there was a wrap + * around of the (16 bit) counter. + */ + if (TftpBlock == 0) { + TftpBlockWrap++; + TftpBlockWrapOffset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE; + printf ("\n\t %lu MB reveived\n\t ", TftpBlockWrapOffset>>20); + } else { + if (((TftpBlock - 1) % 10) == 0) { + putc ('#'); + } else if ((TftpBlock % (10 * HASHES_PER_LINE)) == 0) { + puts ("\n\t "); + } + } + +#ifdef ET_DEBUG + if (TftpState == STATE_RRQ) { + puts ("Server did not acknowledge timeout option!\n"); + } +#endif + + if (TftpState == STATE_RRQ || TftpState == STATE_OACK) { + /* first block received */ + TftpState = STATE_DATA; + TftpServerPort = src; + TftpLastBlock = 0; + TftpBlockWrap = 0; + TftpBlockWrapOffset = 0; + + if (TftpBlock != 1) { /* Assertion */ + printf ("\nTFTP error: " + "First block is not block 1 (%ld)\n" + "Starting again\n\n", + TftpBlock); + NetStartAgain (); + break; + } + } + + if (TftpBlock == TftpLastBlock) { + /* + * Same block again; ignore it. + */ + break; + } + + TftpLastBlock = TftpBlock; + NetSetTimeout (TIMEOUT * CFG_HZ, TftpTimeout); + + store_block (TftpBlock - 1, pkt + 2, len); + + /* + * Acknoledge the block just received, which will prompt + * the server for the next one. + */ + TftpSend (); + + if (len < TFTP_BLOCK_SIZE) { + /* + * We received the whole thing. Try to + * run it. + */ + puts ("\ndone\n"); + NetState = NETLOOP_SUCCESS; + } + break; + + case TFTP_ERROR: + printf ("\nTFTP error: '%s' (%d)\n", + pkt + 2, ntohs(*(ushort *)pkt)); + puts ("Starting again\n\n"); + NetStartAgain (); + break; + } +} + + +static void +TftpTimeout (void) +{ + if (++TftpTimeoutCount > TIMEOUT_COUNT) { + puts ("\nRetry count exceeded; starting again\n"); + NetStartAgain (); + } else { + puts ("T "); + NetSetTimeout (TIMEOUT * CFG_HZ, TftpTimeout); + TftpSend (); + } +} + + +void +TftpStart (void) +{ +#ifdef CONFIG_TFTP_PORT + char *ep; /* Environment pointer */ +#endif + + if (BootFile[0] == '\0') { + sprintf(default_filename, "%02lX%02lX%02lX%02lX.img", + NetOurIP & 0xFF, + (NetOurIP >> 8) & 0xFF, + (NetOurIP >> 16) & 0xFF, + (NetOurIP >> 24) & 0xFF ); + tftp_filename = default_filename; + + printf ("*** Warning: no boot file name; using '%s'\n", + tftp_filename); + } else { + tftp_filename = BootFile; + } + +#if defined(CONFIG_NET_MULTI) + printf ("Using %s device\n", eth_get_name()); +#endif + puts ("TFTP from server "); print_IPaddr (NetServerIP); + puts ("; our IP address is "); print_IPaddr (NetOurIP); + + /* Check if we need to send across this subnet */ + if (NetOurGatewayIP && NetOurSubnetMask) { + IPaddr_t OurNet = NetOurIP & NetOurSubnetMask; + IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask; + + if (OurNet != ServerNet) { + puts ("; sending through gateway "); + print_IPaddr (NetOurGatewayIP) ; + } + } + putc ('\n'); + + printf ("Filename '%s'.", tftp_filename); + + if (NetBootFileSize) { + printf (" Size is 0x%x Bytes = ", NetBootFileSize<<9); + print_size (NetBootFileSize<<9, ""); + } + + putc ('\n'); + + printf ("Load address: 0x%lx\n", load_addr); + + puts ("Loading: *\b"); + + NetSetTimeout (TIMEOUT * CFG_HZ, TftpTimeout); + NetSetHandler (TftpHandler); + + TftpServerPort = WELL_KNOWN_PORT; + TftpTimeoutCount = 0; + TftpState = STATE_RRQ; + /* Use a pseudo-random port unless a specific port is set */ + TftpOurPort = 1024 + (get_timer(0) % 3072); +#ifdef CONFIG_TFTP_PORT + if ((ep = getenv("tftpdstp")) != NULL) { + TftpServerPort = simple_strtol(ep, NULL, 10); + } + if ((ep = getenv("tftpsrcp")) != NULL) { + TftpOurPort= simple_strtol(ep, NULL, 10); + } +#endif + TftpBlock = 0; + + /* zero out server ether in case the server ip has changed */ + memset(NetServerEther, 0, 6); + + TftpSend (); +} + +#endif /* CFG_CMD_NET */ diff --git a/net/tftp.h b/net/tftp.h new file mode 100644 index 0000000..e3dfb26 --- /dev/null +++ b/net/tftp.h @@ -0,0 +1,21 @@ +/* + * LiMon - BOOTP/TFTP. + * + * Copyright 1994, 1995, 2000 Neil Russell. + * (See License) + */ + +#ifndef __TFTP_H__ +#define __TFTP_H__ + +/**********************************************************************/ +/* + * Global functions and variables. + */ + +/* tftp.c */ +extern void TftpStart (void); /* Begin TFTP get */ + +/**********************************************************************/ + +#endif /* __TFTP_H__ */ diff --git a/nios2_config.mk b/nios2_config.mk new file mode 100644 index 0000000..03253a3 --- /dev/null +++ b/nios2_config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2004 +# Psyent Corporation +# Scott McNutt +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ +PLATFORM_CPPFLAGS += -ffixed-r15 diff --git a/nios_config.mk b/nios_config.mk new file mode 100644 index 0000000..1cf0f32 --- /dev/null +++ b/nios_config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2003 +# Psyent Corporation +# Scott McNutt +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs diff --git a/post/Makefile b/post/Makefile new file mode 100644 index 0000000..4ee429d --- /dev/null +++ b/post/Makefile @@ -0,0 +1,35 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +SUBDIRS = cpu + +LIB = libpost.a + +AOBJS = cache_8xx.o +COBJS = cache.o codec.o cpu.o dsp.o ether.o +COBJS += i2c.o memory.o post.o rtc.o +COBJS += spr.o sysmon.o tests.o uart.o +COBJS += usb.o watchdog.o + +include $(TOPDIR)/post/rules.mk diff --git a/post/cache.c b/post/cache.c new file mode 100644 index 0000000..501465c --- /dev/null +++ b/post/cache.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* Cache test + * + * This test verifies the CPU data and instruction cache using + * several test scenarios. + */ + +#ifdef CONFIG_POST + +#include +#include + +#if CONFIG_POST & CFG_POST_CACHE + +#define CACHE_POST_SIZE 1024 + +extern int cache_post_test1 (char *, unsigned int); +extern int cache_post_test2 (char *, unsigned int); +extern int cache_post_test3 (char *, unsigned int); +extern int cache_post_test4 (char *, unsigned int); +extern int cache_post_test5 (void); +extern int cache_post_test6 (void); + +int cache_post_test (int flags) +{ + int ints = disable_interrupts (); + int res = 0; + static char ta[CACHE_POST_SIZE + 0xf]; + char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf); + + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test1 (testarea, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test2 (testarea, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test3 (testarea, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test4 (testarea, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test5 (); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test6 (); + + WATCHDOG_RESET (); + if (ints) + enable_interrupts (); + return res; +} + +#endif /* CONFIG_POST & CFG_POST_CACHE */ +#endif /* CONFIG_POST */ diff --git a/post/cache_8xx.S b/post/cache_8xx.S new file mode 100644 index 0000000..2d41b55 --- /dev/null +++ b/post/cache_8xx.S @@ -0,0 +1,495 @@ +/* + * Copyright (C) 2002 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_POST +#if defined(CONFIG_MPC823) || \ + defined(CONFIG_MPC850) || \ + defined(CONFIG_MPC855) || \ + defined(CONFIG_MPC860) || \ + defined(CONFIG_MPC862) + +#include +#include +#include +#include + +#if CONFIG_POST & CFG_POST_CACHE + + .text + +cache_post_dinvalidate: + lis r10, IDC_INVALL@h + mtspr DC_CST, r10 + blr + +cache_post_iinvalidate: + lis r10, IDC_INVALL@h + mtspr IC_CST, r10 + isync + blr + +cache_post_ddisable: + lis r10, IDC_DISABLE@h + mtspr DC_CST, r10 + blr + +cache_post_dwb: + lis r10, IDC_ENABLE@h + mtspr DC_CST, r10 + lis r10, DC_CFWT@h + mtspr DC_CST, r10 + blr + +cache_post_dwt: + lis r10, IDC_ENABLE@h + mtspr DC_CST, r10 + lis r10, DC_SFWT@h + mtspr DC_CST, r10 + blr + +cache_post_idisable: + lis r10, IDC_DISABLE@h + mtspr IC_CST, r10 + isync + blr + +cache_post_ienable: + lis r10, IDC_ENABLE@h + mtspr IC_CST, r10 + isync + blr + +cache_post_iunlock: + lis r10, IDC_UNALL@h + mtspr IC_CST, r10 + isync + blr + +cache_post_ilock: + mtspr IC_ADR, r3 + lis r10, IDC_LDLCK@h + mtspr IC_CST, r10 + isync + blr + +/* + * turn on the data cache + * switch the data cache to write-back or write-through mode + * invalidate the data cache + * write the negative pattern to a cached area + * read the area + * + * The negative pattern must be read at the last step + */ + .global cache_post_test1 +cache_post_test1: + mflr r0 + stw r0, 4(r1) + + stwu r3, -4(r1) + stwu r4, -4(r1) + + bl cache_post_dwb + bl cache_post_dinvalidate + + /* Write the negative pattern to the test area */ + lwz r0, 0(r1) + mtctr r0 + li r0, 0xff + lwz r3, 4(r1) + subi r3, r3, 1 +1: + stbu r0, 1(r3) + bdnz 1b + + /* Read the test area */ + lwz r0, 0(r1) + mtctr r0 + lwz r4, 4(r1) + subi r4, r4, 1 + li r3, 0 +1: + lbzu r0, 1(r4) + cmpli cr0, r0, 0xff + beq 2f + li r3, -1 + b 3f +2: + bdnz 1b +3: + + bl cache_post_ddisable + bl cache_post_dinvalidate + + addi r1, r1, 8 + + lwz r0, 4(r1) + mtlr r0 + blr + +/* + * turn on the data cache + * switch the data cache to write-back or write-through mode + * invalidate the data cache + * write the zero pattern to a cached area + * turn off the data cache + * write the negative pattern to the area + * turn on the data cache + * read the area + * + * The negative pattern must be read at the last step + */ + .global cache_post_test2 +cache_post_test2: + mflr r0 + stw r0, 4(r1) + + stwu r3, -4(r1) + stwu r4, -4(r1) + + bl cache_post_dwb + bl cache_post_dinvalidate + + /* Write the zero pattern to the test area */ + lwz r0, 0(r1) + mtctr r0 + li r0, 0 + lwz r3, 4(r1) + subi r3, r3, 1 +1: + stbu r0, 1(r3) + bdnz 1b + + bl cache_post_ddisable + + /* Write the negative pattern to the test area */ + lwz r0, 0(r1) + mtctr r0 + li r0, 0xff + lwz r3, 4(r1) + subi r3, r3, 1 +1: + stbu r0, 1(r3) + bdnz 1b + + bl cache_post_dwb + + /* Read the test area */ + lwz r0, 0(r1) + mtctr r0 + lwz r4, 4(r1) + subi r4, r4, 1 + li r3, 0 +1: + lbzu r0, 1(r4) + cmpli cr0, r0, 0xff + beq 2f + li r3, -1 + b 3f +2: + bdnz 1b +3: + + bl cache_post_ddisable + bl cache_post_dinvalidate + + addi r1, r1, 8 + + lwz r0, 4(r1) + mtlr r0 + blr + +/* + * turn on the data cache + * switch the data cache to write-through mode + * invalidate the data cache + * write the zero pattern to a cached area + * flush the data cache + * write the negative pattern to the area + * turn off the data cache + * read the area + * + * The negative pattern must be read at the last step + */ + .global cache_post_test3 +cache_post_test3: + mflr r0 + stw r0, 4(r1) + + stwu r3, -4(r1) + stwu r4, -4(r1) + + bl cache_post_ddisable + bl cache_post_dinvalidate + + /* Write the zero pattern to the test area */ + lwz r0, 0(r1) + mtctr r0 + li r0, 0 + lwz r3, 4(r1) + subi r3, r3, 1 +1: + stbu r0, 1(r3) + bdnz 1b + + bl cache_post_dwt + bl cache_post_dinvalidate + + /* Write the negative pattern to the test area */ + lwz r0, 0(r1) + mtctr r0 + li r0, 0xff + lwz r3, 4(r1) + subi r3, r3, 1 +1: + stbu r0, 1(r3) + bdnz 1b + + bl cache_post_ddisable + bl cache_post_dinvalidate + + /* Read the test area */ + lwz r0, 0(r1) + mtctr r0 + lwz r4, 4(r1) + subi r4, r4, 1 + li r3, 0 +1: + lbzu r0, 1(r4) + cmpli cr0, r0, 0xff + beq 2f + li r3, -1 + b 3f +2: + bdnz 1b +3: + + addi r1, r1, 8 + + lwz r0, 4(r1) + mtlr r0 + blr + +/* + * turn on the data cache + * switch the data cache to write-back mode + * invalidate the data cache + * write the negative pattern to a cached area + * flush the data cache + * write the zero pattern to the area + * invalidate the data cache + * read the area + * + * The negative pattern must be read at the last step + */ + .global cache_post_test4 +cache_post_test4: + mflr r0 + stw r0, 4(r1) + + stwu r3, -4(r1) + stwu r4, -4(r1) + + bl cache_post_ddisable + bl cache_post_dinvalidate + + /* Write the negative pattern to the test area */ + lwz r0, 0(r1) + mtctr r0 + li r0, 0xff + lwz r3, 4(r1) + subi r3, r3, 1 +1: + stbu r0, 1(r3) + bdnz 1b + + bl cache_post_dwb + bl cache_post_dinvalidate + + /* Write the zero pattern to the test area */ + lwz r0, 0(r1) + mtctr r0 + li r0, 0 + lwz r3, 4(r1) + subi r3, r3, 1 +1: + stbu r0, 1(r3) + bdnz 1b + + bl cache_post_ddisable + bl cache_post_dinvalidate + + /* Read the test area */ + lwz r0, 0(r1) + mtctr r0 + lwz r4, 4(r1) + subi r4, r4, 1 + li r3, 0 +1: + lbzu r0, 1(r4) + cmpli cr0, r0, 0xff + beq 2f + li r3, -1 + b 3f +2: + bdnz 1b +3: + + addi r1, r1, 8 + + lwz r0, 4(r1) + mtlr r0 + blr + +cache_post_test5_1: + li r3, 0 +cache_post_test5_2: + li r3, -1 + +/* + * turn on the instruction cache + * unlock the entire instruction cache + * invalidate the instruction cache + * lock a branch instruction in the instruction cache + * replace the branch instruction with "nop" + * jump to the branch instruction + * check that the branch instruction was executed +*/ + .global cache_post_test5 +cache_post_test5: + mflr r0 + stw r0, 4(r1) + + bl cache_post_ienable + bl cache_post_iunlock + bl cache_post_iinvalidate + + /* Compute r9 = cache_post_test5_reloc */ + bl cache_post_test5_reloc +cache_post_test5_reloc: + mflr r9 + + /* Copy the test instruction to cache_post_test5_data */ + lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h + ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l + add r3, r3, r9 + lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h + ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l + add r4, r4, r9 + lwz r0, 0(r3) + stw r0, 0(r4) + + bl cache_post_iinvalidate + + /* Lock the branch instruction */ + lis r3, (cache_post_test5_data - cache_post_test5_reloc)@h + ori r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l + add r3, r3, r9 + bl cache_post_ilock + + /* Replace the test instruction */ + lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h + ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l + add r3, r3, r9 + lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h + ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l + add r4, r4, r9 + lwz r0, 0(r3) + stw r0, 0(r4) + + bl cache_post_iinvalidate + + /* Execute to the test instruction */ +cache_post_test5_data: + nop + + bl cache_post_iunlock + + lwz r0, 4(r1) + mtlr r0 + blr + +cache_post_test6_1: + li r3, -1 +cache_post_test6_2: + li r3, 0 + +/* + * turn on the instruction cache + * unlock the entire instruction cache + * invalidate the instruction cache + * lock a branch instruction in the instruction cache + * replace the branch instruction with "nop" + * jump to the branch instruction + * check that the branch instruction was executed + */ + .global cache_post_test6 +cache_post_test6: + mflr r0 + stw r0, 4(r1) + + bl cache_post_ienable + bl cache_post_iunlock + bl cache_post_iinvalidate + + /* Compute r9 = cache_post_test6_reloc */ + bl cache_post_test6_reloc +cache_post_test6_reloc: + mflr r9 + + /* Copy the test instruction to cache_post_test6_data */ + lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h + ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l + add r3, r3, r9 + lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h + ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l + add r4, r4, r9 + lwz r0, 0(r3) + stw r0, 0(r4) + + bl cache_post_iinvalidate + + /* Replace the test instruction */ + lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h + ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l + add r3, r3, r9 + lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h + ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l + add r4, r4, r9 + lwz r0, 0(r3) + stw r0, 0(r4) + + bl cache_post_iinvalidate + + /* Execute to the test instruction */ +cache_post_test6_data: + nop + + lwz r0, 4(r1) + mtlr r0 + blr + +#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */ +#endif /* CONFIG_POST & CFG_POST_CACHE */ +#endif /* CONFIG_POST */ diff --git a/post/codec.c b/post/codec.c new file mode 100644 index 0000000..e881752 --- /dev/null +++ b/post/codec.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2004 + * Pantelis Antoniou, Intracom S.A. , panto@intracom.gr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CODEC test + * + * This test verifies the connection and performs a memory test + * on any connected codec(s). The meat of the work is done + * in the board specific function. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_CODEC + +extern int board_post_codec(int flags); + +int codec_post_test (int flags) +{ + return board_post_codec(flags); +} + +#endif /* CONFIG_POST & CFG_POST_CODEC */ +#endif /* CONFIG_POST */ diff --git a/post/cpu.c b/post/cpu.c new file mode 100644 index 0000000..1f2ded2 --- /dev/null +++ b/post/cpu.c @@ -0,0 +1,139 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * + * This test checks the arithmetic logic unit (ALU) of CPU. + * It tests independently various groups of instructions using + * run-time modification of the code to reduce the memory footprint. + * For more details refer to post/cpu/ *.c files. + */ + +#ifdef CONFIG_POST + +#include +#include + +#if CONFIG_POST & CFG_POST_CPU + +extern int cpu_post_test_cmp (void); +extern int cpu_post_test_cmpi (void); +extern int cpu_post_test_two (void); +extern int cpu_post_test_twox (void); +extern int cpu_post_test_three (void); +extern int cpu_post_test_threex (void); +extern int cpu_post_test_threei (void); +extern int cpu_post_test_andi (void); +extern int cpu_post_test_srawi (void); +extern int cpu_post_test_rlwnm (void); +extern int cpu_post_test_rlwinm (void); +extern int cpu_post_test_rlwimi (void); +extern int cpu_post_test_store (void); +extern int cpu_post_test_load (void); +extern int cpu_post_test_cr (void); +extern int cpu_post_test_b (void); +extern int cpu_post_test_multi (void); +extern int cpu_post_test_string (void); +extern int cpu_post_test_complex (void); + +ulong cpu_post_makecr (long v) +{ + ulong cr = 0; + + if (v < 0) + cr |= 0x80000000; + if (v > 0) + cr |= 0x40000000; + if (v == 0) + cr |= 0x20000000; + + return cr; +} + +int cpu_post_test (int flags) +{ + int ic = icache_status (); + int ret = 0; + + WATCHDOG_RESET(); + if (ic) + icache_disable (); + + if (ret == 0) + ret = cpu_post_test_cmp (); + if (ret == 0) + ret = cpu_post_test_cmpi (); + if (ret == 0) + ret = cpu_post_test_two (); + if (ret == 0) + ret = cpu_post_test_twox (); + WATCHDOG_RESET(); + if (ret == 0) + ret = cpu_post_test_three (); + if (ret == 0) + ret = cpu_post_test_threex (); + if (ret == 0) + ret = cpu_post_test_threei (); + if (ret == 0) + ret = cpu_post_test_andi (); + WATCHDOG_RESET(); + if (ret == 0) + ret = cpu_post_test_srawi (); + if (ret == 0) + ret = cpu_post_test_rlwnm (); + if (ret == 0) + ret = cpu_post_test_rlwinm (); + if (ret == 0) + ret = cpu_post_test_rlwimi (); + WATCHDOG_RESET(); + if (ret == 0) + ret = cpu_post_test_store (); + if (ret == 0) + ret = cpu_post_test_load (); + if (ret == 0) + ret = cpu_post_test_cr (); + if (ret == 0) + ret = cpu_post_test_b (); + WATCHDOG_RESET(); + if (ret == 0) + ret = cpu_post_test_multi (); + WATCHDOG_RESET(); + if (ret == 0) + ret = cpu_post_test_string (); + if (ret == 0) + ret = cpu_post_test_complex (); + WATCHDOG_RESET(); + + if (ic) + icache_enable (); + + WATCHDOG_RESET(); + + return ret; +} + +#endif /* CONFIG_POST & CFG_POST_CPU */ +#endif /* CONFIG_POST */ diff --git a/post/cpu/Makefile b/post/cpu/Makefile new file mode 100644 index 0000000..43fc044 --- /dev/null +++ b/post/cpu/Makefile @@ -0,0 +1,33 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +SUBDIRS = + +LIB = libcpu.a + +AOBJS = asm.o +COBJS = cmp.o cmpi.o two.o twox.o three.o threex.o +COBJS += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o +COBJS += store.o load.o cr.o b.o multi.o string.o complex.o + +include $(TOPDIR)/post/rules.mk diff --git a/post/cpu/andi.c b/post/cpu/andi.c new file mode 100644 index 0000000..7ddf2ab --- /dev/null +++ b/post/cpu/andi.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Logic instructions: andi., andis. + * + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_andi_s +{ + ulong cmd; + ulong op1; + ushort op2; + ulong res; +} cpu_post_andi_table[] = +{ + { + OP_ANDI_, + 0x80008000, + 0xffff, + 0x00008000 + }, + { + OP_ANDIS_, + 0x80008000, + 0xffff, + 0x80000000 + }, +}; +static unsigned int cpu_post_andi_size = + sizeof (cpu_post_andi_table) / sizeof (struct cpu_post_andi_s); + +int cpu_post_test_andi (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_andi_size && ret == 0; i++) + { + struct cpu_post_andi_s *test = cpu_post_andi_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long codecr[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_11IX(test->cmd, reg1, reg0, test->op2), + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + cpu_post_exec_21 (codecr, & cr, & res, test->op1); + + ret = res == test->res && + (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at andi test %d !\n", i); + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/asm.S b/post/cpu/asm.S new file mode 100644 index 0000000..a0815a4 --- /dev/null +++ b/post/cpu/asm.S @@ -0,0 +1,346 @@ +/* + * Copyright (C) 2002 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_POST + +#include +#include +#include +#include + +#if CONFIG_POST & CFG_POST_CPU + +/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ + .global cpu_post_exec_02 +cpu_post_exec_02: + mflr r0 + stwu r0, -4(r1) + + subi r1, r1, 104 + stmw r6, 0(r1) + + mtlr r3 + mr r3, r4 + mr r4, r5 + blrl + + lmw r6, 0(r1) + addi r1, r1, 104 + + lwz r0, 0(r1) + addi r1, r1, 4 + mtlr r0 + blr + +/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */ + .global cpu_post_exec_04 +cpu_post_exec_04: + mflr r0 + stwu r0, -4(r1) + + subi r1, r1, 96 + stmw r8, 0(r1) + + mtlr r3 + mr r3, r4 + mr r4, r5 + mr r5, r6 + mtxer r7 + blrl + + lmw r8, 0(r1) + addi r1, r1, 96 + + lwz r0, 0(r1) + addi r1, r1, 4 + mtlr r0 + blr + +/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */ + .global cpu_post_exec_12 +cpu_post_exec_12: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + + mtlr r3 + mr r3, r5 + mr r4, r6 + blrl + + lwz r4, 0(r1) + stw r3, 0(r4) + + lwz r0, 4(r1) + addi r1, r1, 8 + mtlr r0 + blr + +/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */ + .global cpu_post_exec_11 +cpu_post_exec_11: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + + mtlr r3 + mr r3, r5 + blrl + + lwz r4, 0(r1) + stw r3, 0(r4) + + lwz r0, 4(r1) + addi r1, r1, 8 + mtlr r0 + blr + +/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */ + .global cpu_post_exec_21 +cpu_post_exec_21: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + stwu r5, -4(r1) + + li r0, 0 + mtxer r0 + lwz r0, 0(r4) + mtcr r0 + + mtlr r3 + mr r3, r6 + blrl + + mfcr r0 + lwz r4, 4(r1) + stw r0, 0(r4) + lwz r4, 0(r1) + stw r3, 0(r4) + + lwz r0, 8(r1) + addi r1, r1, 12 + mtlr r0 + blr + +/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, + ulong op2); */ + .global cpu_post_exec_22 +cpu_post_exec_22: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + stwu r5, -4(r1) + + li r0, 0 + mtxer r0 + lwz r0, 0(r4) + mtcr r0 + + mtlr r3 + mr r3, r6 + mr r4, r7 + blrl + + mfcr r0 + lwz r4, 4(r1) + stw r0, 0(r4) + lwz r4, 0(r1) + stw r3, 0(r4) + + lwz r0, 8(r1) + addi r1, r1, 12 + mtlr r0 + blr + +/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */ + .global cpu_post_exec_12w +cpu_post_exec_12w: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + + mtlr r3 + lwz r3, 0(r4) + mr r4, r5 + mr r5, r6 + blrl + + lwz r4, 0(r1) + stw r3, 0(r4) + + lwz r0, 4(r1) + addi r1, r1, 8 + mtlr r0 + blr + +/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */ + .global cpu_post_exec_11w +cpu_post_exec_11w: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + + mtlr r3 + lwz r3, 0(r4) + mr r4, r5 + blrl + + lwz r4, 0(r1) + stw r3, 0(r4) + + lwz r0, 4(r1) + addi r1, r1, 8 + mtlr r0 + blr + +/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */ + .global cpu_post_exec_22w +cpu_post_exec_22w: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + stwu r6, -4(r1) + + mtlr r3 + lwz r3, 0(r4) + mr r4, r5 + blrl + + lwz r4, 4(r1) + stw r3, 0(r4) + lwz r4, 0(r1) + stw r5, 0(r4) + + lwz r0, 8(r1) + addi r1, r1, 12 + mtlr r0 + blr + +/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */ + .global cpu_post_exec_21w +cpu_post_exec_21w: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + stwu r5, -4(r1) + + mtlr r3 + lwz r3, 0(r4) + blrl + + lwz r5, 4(r1) + stw r3, 0(r5) + lwz r5, 0(r1) + stw r4, 0(r5) + + lwz r0, 8(r1) + addi r1, r1, 12 + mtlr r0 + blr + +/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */ + .global cpu_post_exec_21x +cpu_post_exec_21x: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + stwu r5, -4(r1) + + mtlr r3 + mr r3, r6 + blrl + + lwz r5, 4(r1) + stw r3, 0(r5) + lwz r5, 0(r1) + stw r4, 0(r5) + + lwz r0, 8(r1) + addi r1, r1, 12 + mtlr r0 + blr + +/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, + ulong cr); */ + .global cpu_post_exec_31 +cpu_post_exec_31: + mflr r0 + stwu r0, -4(r1) + stwu r4, -4(r1) + stwu r5, -4(r1) + stwu r6, -4(r1) + + mtlr r3 + lwz r3, 0(r4) + lwz r4, 0(r5) + mr r6, r7 + blrl + + lwz r7, 8(r1) + stw r3, 0(r7) + lwz r7, 4(r1) + stw r4, 0(r7) + lwz r7, 0(r1) + stw r5, 0(r7) + + lwz r0, 12(r1) + addi r1, r1, 16 + mtlr r0 + blr + +/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */ + .global cpu_post_complex_1_asm +cpu_post_complex_1_asm: + li r9,0 + cmpw r9,r7 + bge cpu_post_complex_1_done + mtctr r7 +cpu_post_complex_1_loop: + mullw r0,r3,r4 + subf r0,r5,r0 + divw r0,r0,r6 + add r9,r9,r0 + bdnz cpu_post_complex_1_loop +cpu_post_complex_1_done: + mr r3,r9 + blr + +/* int cpu_post_complex_2_asm (int x, int n); */ + .global cpu_post_complex_2_asm +cpu_post_complex_2_asm: + mr. r0,r4 + mtctr r0 + mr r0,r3 + li r3,1 + li r4,1 + blelr +cpu_post_complex_2_loop: + mullw r3,r3,r0 + add r3,r3,r4 + bdnz cpu_post_complex_2_loop +blr + +#endif +#endif diff --git a/post/cpu/b.c b/post/cpu/b.c new file mode 100644 index 0000000..b4b17c8 --- /dev/null +++ b/post/cpu/b.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Branch instructions: b, bl, bc + * + * The first 2 instructions (b, bl) are verified by jumping + * to a fixed address and checking whether control was transfered + * to that very point. For the bl instruction the value of the + * link register is checked as well (using mfspr). + * To verify the bc instruction various combinations of the BI/BO + * fields, the CTR and the condition register values are + * checked. The list of such combinations is pre-built and + * linked in U-Boot at build time. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); +extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, + ulong cr); + +static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi, + int pjump, int dec, int link, ulong pctr, ulong cr) +{ + int ret = 0; + ulong lr = 0; + ulong ctr = pctr; + ulong jump; + + unsigned long code[] = + { + ASM_MTCR(6), + ASM_MFLR(6), + ASM_MTCTR(3), + ASM_MTLR(4), + ASM_LI(5, 1), + ASM_3O(cmd, bo, bi, 8), + ASM_LI(5, 0), + ASM_MFCTR(3), + ASM_MFLR(4), + ASM_MTLR(6), + ASM_BLR, + }; + + cpu_post_exec_31 (code, &ctr, &lr, &jump, cr); + + if (ret == 0) + ret = pjump == jump ? 0 : -1; + if (ret == 0) + { + if (dec) + ret = pctr == ctr + 1 ? 0 : -1; + else + ret = pctr == ctr ? 0 : -1; + } + if (ret == 0) + { + if (link) + ret = lr == (ulong) code + 24 ? 0 : -1; + else + ret = lr == 0 ? 0 : -1; + } + + return ret; +} + +int cpu_post_test_b (void) +{ + int ret = 0; + unsigned int i; + + if (ret == 0) + { + ulong code[] = + { + ASM_MFLR(4), + ASM_MTLR(3), + ASM_B(4), + ASM_MFLR(3), + ASM_MTLR(4), + ASM_BLR, + }; + ulong res; + + cpu_post_exec_11 (code, &res, 0); + + ret = res == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at b1 test !\n"); + } + } + + if (ret == 0) + { + ulong code[] = + { + ASM_MFLR(4), + ASM_MTLR(3), + ASM_BL(4), + ASM_MFLR(3), + ASM_MTLR(4), + ASM_BLR, + }; + ulong res; + + cpu_post_exec_11 (code, &res, 0); + + ret = res == (ulong)code + 12 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at b2 test !\n"); + } + } + + if (ret == 0) + { + ulong cc, cd; + int cond; + ulong ctr; + int link; + + i = 0; + + for (cc = 0; cc < 4 && ret == 0; cc++) + { + for (cd = 0; cd < 4 && ret == 0; cd++) + { + for (link = 0; link <= 1 && ret == 0; link++) + { + for (cond = 0; cond <= 1 && ret == 0; cond++) + { + for (ctr = 1; ctr <= 2 && ret == 0; ctr++) + { + int dec = cd < 2; + int cr = cond ? 0x80000000 : 0x00000000; + int jumpc = cc >= 2 || + (cc == 0 && !cond) || + (cc == 1 && cond); + int jumpd = cd >= 2 || + (cd == 0 && ctr != 1) || + (cd == 1 && ctr == 1); + int jump = jumpc && jumpd; + + ret = cpu_post_test_bc (link ? OP_BCL : OP_BC, + (cc << 3) + (cd << 1), 0, jump, dec, link, + ctr, cr); + + if (ret != 0) + { + post_log ("Error at b3 test %d !\n", i); + } + + i++; + } + } + } + } + } + } + + return ret; +} + +#endif +#endif diff --git a/post/cpu/cmp.c b/post/cpu/cmp.c new file mode 100644 index 0000000..789a24c --- /dev/null +++ b/post/cpu/cmp.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Integer compare instructions: cmpw, cmplw + * + * To verify these instructions the test runs them with + * different combinations of operands, reads the condition + * register value and compares it with the expected one. + * The test contains a pre-built table + * containing the description of each test case: the instruction, + * the values of the operands, the condition field to save + * the result in and the expected result. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); + +static struct cpu_post_cmp_s +{ + ulong cmd; + ulong op1; + ulong op2; + ulong cr; + ulong res; +} cpu_post_cmp_table[] = +{ + { + OP_CMPW, + 123, + 123, + 2, + 0x02 + }, + { + OP_CMPW, + 123, + 133, + 3, + 0x08 + }, + { + OP_CMPW, + 123, + -133, + 4, + 0x04 + }, + { + OP_CMPLW, + 123, + 123, + 2, + 0x02 + }, + { + OP_CMPLW, + 123, + -133, + 3, + 0x08 + }, + { + OP_CMPLW, + 123, + 113, + 4, + 0x04 + }, +}; +static unsigned int cpu_post_cmp_size = + sizeof (cpu_post_cmp_table) / sizeof (struct cpu_post_cmp_s); + +int cpu_post_test_cmp (void) +{ + int ret = 0; + unsigned int i; + + for (i = 0; i < cpu_post_cmp_size && ret == 0; i++) + { + struct cpu_post_cmp_s *test = cpu_post_cmp_table + i; + unsigned long code[] = + { + ASM_2C(test->cmd, test->cr, 3, 4), + ASM_MFCR(3), + ASM_BLR + }; + ulong res; + + cpu_post_exec_12 (code, & res, test->op1, test->op2); + + ret = ((res >> (28 - 4 * test->cr)) & 0xe) == test->res ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at cmp test %d !\n", i); + } + } + + return ret; +} + +#endif +#endif diff --git a/post/cpu/cmpi.c b/post/cpu/cmpi.c new file mode 100644 index 0000000..e0c2aaf --- /dev/null +++ b/post/cpu/cmpi.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Integer compare instructions: cmpwi, cmplwi + * + * To verify these instructions the test runs them with + * different combinations of operands, reads the condition + * register value and compares it with the expected one. + * The test contains a pre-built table + * containing the description of each test case: the instruction, + * the values of the operands, the condition field to save + * the result in and the expected result. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); + +static struct cpu_post_cmpi_s +{ + ulong cmd; + ulong op1; + ushort op2; + ulong cr; + ulong res; +} cpu_post_cmpi_table[] = +{ + { + OP_CMPWI, + 123, + 123, + 2, + 0x02 + }, + { + OP_CMPWI, + 123, + 133, + 3, + 0x08 + }, + { + OP_CMPWI, + 123, + -133, + 4, + 0x04 + }, + { + OP_CMPLWI, + 123, + 123, + 2, + 0x02 + }, + { + OP_CMPLWI, + 123, + -133, + 3, + 0x08 + }, + { + OP_CMPLWI, + 123, + 113, + 4, + 0x04 + }, +}; +static unsigned int cpu_post_cmpi_size = + sizeof (cpu_post_cmpi_table) / sizeof (struct cpu_post_cmpi_s); + +int cpu_post_test_cmpi (void) +{ + int ret = 0; + unsigned int i; + + for (i = 0; i < cpu_post_cmpi_size && ret == 0; i++) + { + struct cpu_post_cmpi_s *test = cpu_post_cmpi_table + i; + unsigned long code[] = + { + ASM_1IC(test->cmd, test->cr, 3, test->op2), + ASM_MFCR(3), + ASM_BLR + }; + ulong res; + + cpu_post_exec_11 (code, & res, test->op1); + + ret = ((res >> (28 - 4 * test->cr)) & 0xe) == test->res ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at cmpi test %d !\n", i); + } + } + + return ret; +} + +#endif +#endif diff --git a/post/cpu/complex.c b/post/cpu/complex.c new file mode 100644 index 0000000..033584b --- /dev/null +++ b/post/cpu/complex.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Complex calculations + * + * The calculations in this test are just a combination of simpler + * calculations, but probably under different timing conditions, etc. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); +extern int cpu_post_complex_2_asm (int x, int n); + + /* + * n + * SUM (a1 * a2 - a3) / a4 = n * result + * i=1 + */ +static int cpu_post_test_complex_1 (void) +{ + int a1 = 666; + int a2 = 667; + int a3 = 668; + int a4 = 66; + int n = 100; + int result = 6720; /* (a1 * a2 - a3) / a4 */ + + if (cpu_post_complex_1_asm(a1, a2, a3, a4, n) != n * result) + { + return -1; + } + + return 0; +} + + /* (1 + x + x^2 + ... + x^n) * (1 - x) = 1 - x^(n+1) + */ +static int cpu_post_test_complex_2 (void) +{ + int ret = -1; + int x; + int n; + int k; + int left; + int right; + + for (x = -8; x <= 8; x ++) + { + n = 9; + + left = cpu_post_complex_2_asm(x, n); + left *= 1 - x; + + right = 1; + for (k = 0; k <= n; k ++) + { + right *= x; + } + right = 1 - right; + + if (left != right) + { + goto Done; + } + } + + ret = 0; + Done: + + return ret; +} + +int cpu_post_test_complex (void) +{ + int ret = 0; + + if (ret == 0) + { + ret = cpu_post_test_complex_1(); + } + + if (ret == 0) + { + ret = cpu_post_test_complex_2(); + } + + if (ret != 0) + { + post_log ("Error at complex test !\n"); + } + + return ret; +} + +#endif +#endif diff --git a/post/cpu/cpu_asm.h b/post/cpu/cpu_asm.h new file mode 100644 index 0000000..1cbaf41 --- /dev/null +++ b/post/cpu/cpu_asm.h @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CPU_ASM_H +#define _CPU_ASM_H + +#define BIT_C 0x00000001 + +#define OP_BLR 0x4e800020 +#define OP_EXTSB 0x7c000774 +#define OP_EXTSH 0x7c000734 +#define OP_NEG 0x7c0000d0 +#define OP_CNTLZW 0x7c000034 +#define OP_ADD 0x7c000214 +#define OP_ADDC 0x7c000014 +#define OP_ADDME 0x7c0001d4 +#define OP_ADDZE 0x7c000194 +#define OP_ADDE 0x7c000114 +#define OP_ADDI 0x38000000 +#define OP_SUBF 0x7c000050 +#define OP_SUBFC 0x7c000010 +#define OP_SUBFE 0x7c000110 +#define OP_SUBFME 0x7c0001d0 +#define OP_SUBFZE 0x7c000190 +#define OP_MFCR 0x7c000026 +#define OP_MTCR 0x7c0ff120 +#define OP_MFXER 0x7c0102a6 +#define OP_MTXER 0x7c0103a6 +#define OP_MCRXR 0x7c000400 +#define OP_MCRF 0x4c000000 +#define OP_CRAND 0x4c000202 +#define OP_CRANDC 0x4c000102 +#define OP_CROR 0x4c000382 +#define OP_CRORC 0x4c000342 +#define OP_CRXOR 0x4c000182 +#define OP_CRNAND 0x4c0001c2 +#define OP_CRNOR 0x4c000042 +#define OP_CREQV 0x4c000242 +#define OP_CMPW 0x7c000000 +#define OP_CMPLW 0x7c000040 +#define OP_CMPWI 0x2c000000 +#define OP_CMPLWI 0x28000000 +#define OP_MULLW 0x7c0001d6 +#define OP_MULHW 0x7c000096 +#define OP_MULHWU 0x7c000016 +#define OP_DIVW 0x7c0003d6 +#define OP_DIVWU 0x7c000396 +#define OP_OR 0x7c000378 +#define OP_ORC 0x7c000338 +#define OP_XOR 0x7c000278 +#define OP_NAND 0x7c0003b8 +#define OP_NOR 0x7c0000f8 +#define OP_EQV 0x7c000238 +#define OP_SLW 0x7c000030 +#define OP_SRW 0x7c000430 +#define OP_SRAW 0x7c000630 +#define OP_ORI 0x60000000 +#define OP_ORIS 0x64000000 +#define OP_XORI 0x68000000 +#define OP_XORIS 0x6c000000 +#define OP_ANDI_ 0x70000000 +#define OP_ANDIS_ 0x74000000 +#define OP_SRAWI 0x7c000670 +#define OP_RLWINM 0x54000000 +#define OP_RLWNM 0x5c000000 +#define OP_RLWIMI 0x50000000 +#define OP_LWZ 0x80000000 +#define OP_LHZ 0xa0000000 +#define OP_LHA 0xa8000000 +#define OP_LBZ 0x88000000 +#define OP_LWZU 0x84000000 +#define OP_LHZU 0xa4000000 +#define OP_LHAU 0xac000000 +#define OP_LBZU 0x8c000000 +#define OP_LWZX 0x7c00002e +#define OP_LHZX 0x7c00022e +#define OP_LHAX 0x7c0002ae +#define OP_LBZX 0x7c0000ae +#define OP_LWZUX 0x7c00006e +#define OP_LHZUX 0x7c00026e +#define OP_LHAUX 0x7c0002ee +#define OP_LBZUX 0x7c0000ee +#define OP_STW 0x90000000 +#define OP_STH 0xb0000000 +#define OP_STB 0x98000000 +#define OP_STWU 0x94000000 +#define OP_STHU 0xb4000000 +#define OP_STBU 0x9c000000 +#define OP_STWX 0x7c00012e +#define OP_STHX 0x7c00032e +#define OP_STBX 0x7c0001ae +#define OP_STWUX 0x7c00016e +#define OP_STHUX 0x7c00036e +#define OP_STBUX 0x7c0001ee +#define OP_B 0x48000000 +#define OP_BL 0x48000001 +#define OP_BC 0x40000000 +#define OP_BCL 0x40000001 +#define OP_MTLR 0x7c0803a6 +#define OP_MFLR 0x7c0802a6 +#define OP_MTCTR 0x7c0903a6 +#define OP_MFCTR 0x7c0902a6 +#define OP_LMW 0xb8000000 +#define OP_STMW 0xbc000000 +#define OP_LSWI 0x7c0004aa +#define OP_LSWX 0x7c00042a +#define OP_STSWI 0x7c0005aa +#define OP_STSWX 0x7c00052a + +#define ASM_0(opcode) (opcode) +#define ASM_1(opcode, rd) ((opcode) + \ + ((rd) << 21)) +#define ASM_1C(opcode, cr) ((opcode) + \ + ((cr) << 23)) +#define ASM_11(opcode, rd, rs) ((opcode) + \ + ((rd) << 21) + \ + ((rs) << 16)) +#define ASM_11C(opcode, cd, cs) ((opcode) + \ + ((cd) << 23) + \ + ((cs) << 18)) +#define ASM_11X(opcode, rd, rs) ((opcode) + \ + ((rs) << 21) + \ + ((rd) << 16)) +#define ASM_11I(opcode, rd, rs, simm) ((opcode) + \ + ((rd) << 21) + \ + ((rs) << 16) + \ + ((simm) & 0xffff)) +#define ASM_11IF(opcode, rd, rs, simm) ((opcode) + \ + ((rd) << 21) + \ + ((rs) << 16) + \ + ((simm) << 11)) +#define ASM_11S(opcode, rd, rs, sh) ((opcode) + \ + ((rs) << 21) + \ + ((rd) << 16) + \ + ((sh) << 11)) +#define ASM_11IX(opcode, rd, rs, imm) ((opcode) + \ + ((rs) << 21) + \ + ((rd) << 16) + \ + ((imm) & 0xffff)) +#define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \ + ((rd) << 21) + \ + ((rs1) << 16) + \ + ((rs2) << 11)) +#define ASM_12F(opcode, fd, fs1, fs2) ((opcode) + \ + ((fd) << 21) + \ + ((fs1) << 16) + \ + ((fs2) << 11)) +#define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \ + ((rs1) << 21) + \ + ((rd) << 16) + \ + ((rs2) << 11)) +#define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \ + ((cr) << 23) + \ + ((rs1) << 16) + \ + ((rs2) << 11)) +#define ASM_1IC(opcode, cr, rs, imm) ((opcode) + \ + ((cr) << 23) + \ + ((rs) << 16) + \ + ((imm) & 0xffff)) +#define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ + ((opcode) + \ + ((rs1) << 21) + \ + ((rd) << 16) + \ + ((rs2) << 11) + \ + ((imm1) << 6) + \ + ((imm2) << 1)) +#define ASM_113(opcode, rd, rs, imm1, imm2, imm3) \ + ((opcode) + \ + ((rs) << 21) + \ + ((rd) << 16) + \ + ((imm1) << 11) + \ + ((imm2) << 6) + \ + ((imm3) << 1)) +#define ASM_1O(opcode, off) ((opcode) + (off)) +#define ASM_3O(opcode, bo, bi, off) ((opcode) + \ + ((bo) << 21) + \ + ((bi) << 16) + \ + (off)) + +#define ASM_ADDI(rd, rs, simm) ASM_11I(OP_ADDI, rd, rs, simm) +#define ASM_BLR ASM_0(OP_BLR) +#define ASM_STW(rd, rs, simm) ASM_11I(OP_STW, rd, rs, simm) +#define ASM_LWZ(rd, rs, simm) ASM_11I(OP_LWZ, rd, rs, simm) +#define ASM_MFCR(rd) ASM_1(OP_MFCR, rd) +#define ASM_MTCR(rd) ASM_1(OP_MTCR, rd) +#define ASM_MFXER(rd) ASM_1(OP_MFXER, rd) +#define ASM_MTXER(rd) ASM_1(OP_MTXER, rd) +#define ASM_MFCTR(rd) ASM_1(OP_MFCTR, rd) +#define ASM_MTCTR(rd) ASM_1(OP_MTCTR, rd) +#define ASM_MCRXR(cr) ASM_1C(OP_MCRXR, cr) +#define ASM_MCRF(cd, cs) ASM_11C(OP_MCRF, cd, cs) +#define ASM_B(off) ASM_1O(OP_B, off) +#define ASM_BL(off) ASM_1O(OP_BL, off) +#define ASM_MFLR(rd) ASM_1(OP_MFLR, rd) +#define ASM_MTLR(rd) ASM_1(OP_MTLR, rd) +#define ASM_LI(rd, imm) ASM_ADDI(rd, 0, imm) +#define ASM_LMW(rd, rs, simm) ASM_11I(OP_LMW, rd, rs, simm) +#define ASM_STMW(rd, rs, simm) ASM_11I(OP_STMW, rd, rs, simm) +#define ASM_LSWI(rd, rs, simm) ASM_11IF(OP_LSWI, rd, rs, simm) +#define ASM_LSWX(rd, rs1, rs2) ASM_12(OP_LSWX, rd, rs1, rs2) +#define ASM_STSWI(rd, rs, simm) ASM_11IF(OP_STSWI, rd, rs, simm) +#define ASM_STSWX(rd, rs1, rs2) ASM_12(OP_STSWX, rd, rs1, rs2) + + +#endif /* _CPU_ASM_H */ diff --git a/post/cpu/cr.c b/post/cpu/cr.c new file mode 100644 index 0000000..da6ef37 --- /dev/null +++ b/post/cpu/cr.c @@ -0,0 +1,356 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Condition register istructions: mtcr, mfcr, mcrxr, + * crand, crandc, cror, crorc, crxor, + * crnand, crnor, creqv, mcrf + * + * The mtcrf/mfcr instructions is tested by loading different + * values into the condition register (mtcrf), moving its value + * to a general-purpose register (mfcr) and comparing this value + * with the expected one. + * The mcrxr instruction is tested by loading a fixed value + * into the XER register (mtspr), moving XER value to the + * condition register (mcrxr), moving it to a general-purpose + * register (mfcr) and comparing the value of this register with + * the expected one. + * The rest of instructions is tested by loading a fixed + * value into the condition register (mtcrf), executing each + * instruction several times to modify all 4-bit condition + * fields, moving the value of the conditional register to a + * general-purpose register (mfcr) and comparing it with the + * expected one. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); +extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); + +static ulong cpu_post_cr_table1[] = +{ + 0xaaaaaaaa, + 0x55555555, +}; +static unsigned int cpu_post_cr_size1 = + sizeof (cpu_post_cr_table1) / sizeof (ulong); + +static struct cpu_post_cr_s2 { + ulong xer; + ulong cr; +} cpu_post_cr_table2[] = +{ + { + 0xa0000000, + 1 + }, + { + 0x40000000, + 5 + }, +}; +static unsigned int cpu_post_cr_size2 = + sizeof (cpu_post_cr_table2) / sizeof (struct cpu_post_cr_s2); + +static struct cpu_post_cr_s3 { + ulong cr; + ulong cs; + ulong cd; + ulong res; +} cpu_post_cr_table3[] = +{ + { + 0x01234567, + 0, + 4, + 0x01230567 + }, + { + 0x01234567, + 7, + 0, + 0x71234567 + }, +}; +static unsigned int cpu_post_cr_size3 = + sizeof (cpu_post_cr_table3) / sizeof (struct cpu_post_cr_s3); + +static struct cpu_post_cr_s4 { + ulong cmd; + ulong cr; + ulong op1; + ulong op2; + ulong op3; + ulong res; +} cpu_post_cr_table4[] = +{ + { + OP_CRAND, + 0x0000ffff, + 0, + 16, + 0, + 0x0000ffff + }, + { + OP_CRAND, + 0x0000ffff, + 16, + 17, + 0, + 0x8000ffff + }, + { + OP_CRANDC, + 0x0000ffff, + 0, + 16, + 0, + 0x0000ffff + }, + { + OP_CRANDC, + 0x0000ffff, + 16, + 0, + 0, + 0x8000ffff + }, + { + OP_CROR, + 0x0000ffff, + 0, + 16, + 0, + 0x8000ffff + }, + { + OP_CROR, + 0x0000ffff, + 0, + 1, + 0, + 0x0000ffff + }, + { + OP_CRORC, + 0x0000ffff, + 0, + 16, + 0, + 0x0000ffff + }, + { + OP_CRORC, + 0x0000ffff, + 0, + 0, + 0, + 0x8000ffff + }, + { + OP_CRXOR, + 0x0000ffff, + 0, + 0, + 0, + 0x0000ffff + }, + { + OP_CRXOR, + 0x0000ffff, + 0, + 16, + 0, + 0x8000ffff + }, + { + OP_CRNAND, + 0x0000ffff, + 0, + 16, + 0, + 0x8000ffff + }, + { + OP_CRNAND, + 0x0000ffff, + 16, + 17, + 0, + 0x0000ffff + }, + { + OP_CRNOR, + 0x0000ffff, + 0, + 16, + 0, + 0x0000ffff + }, + { + OP_CRNOR, + 0x0000ffff, + 0, + 1, + 0, + 0x8000ffff + }, + { + OP_CREQV, + 0x0000ffff, + 0, + 0, + 0, + 0x8000ffff + }, + { + OP_CREQV, + 0x0000ffff, + 0, + 16, + 0, + 0x0000ffff + }, +}; +static unsigned int cpu_post_cr_size4 = + sizeof (cpu_post_cr_table4) / sizeof (struct cpu_post_cr_s4); + +int cpu_post_test_cr (void) +{ + int ret = 0; + unsigned int i; + unsigned long cr_sav; + + asm ( "mfcr %0" : "=r" (cr_sav) : ); + + for (i = 0; i < cpu_post_cr_size1 && ret == 0; i++) + { + ulong cr = cpu_post_cr_table1[i]; + ulong res; + + unsigned long code[] = + { + ASM_MTCR(3), + ASM_MFCR(3), + ASM_BLR, + }; + + cpu_post_exec_11 (code, &res, cr); + + ret = res == cr ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at cr1 test %d !\n", i); + } + } + + for (i = 0; i < cpu_post_cr_size2 && ret == 0; i++) + { + struct cpu_post_cr_s2 *test = cpu_post_cr_table2 + i; + ulong res; + ulong xer; + + unsigned long code[] = + { + ASM_MTXER(3), + ASM_MCRXR(test->cr), + ASM_MFCR(3), + ASM_MFXER(4), + ASM_BLR, + }; + + cpu_post_exec_21x (code, &res, &xer, test->xer); + + ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ? + 0 : -1; + + if (ret != 0) + { + post_log ("Error at cr2 test %d !\n", i); + } + } + + for (i = 0; i < cpu_post_cr_size3 && ret == 0; i++) + { + struct cpu_post_cr_s3 *test = cpu_post_cr_table3 + i; + ulong res; + + unsigned long code[] = + { + ASM_MTCR(3), + ASM_MCRF(test->cd, test->cs), + ASM_MFCR(3), + ASM_BLR, + }; + + cpu_post_exec_11 (code, &res, test->cr); + + ret = res == test->res ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at cr3 test %d !\n", i); + } + } + + for (i = 0; i < cpu_post_cr_size4 && ret == 0; i++) + { + struct cpu_post_cr_s4 *test = cpu_post_cr_table4 + i; + ulong res; + + unsigned long code[] = + { + ASM_MTCR(3), + ASM_12F(test->cmd, test->op3, test->op1, test->op2), + ASM_MFCR(3), + ASM_BLR, + }; + + cpu_post_exec_11 (code, &res, test->cr); + + ret = res == test->res ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at cr4 test %d !\n", i); + } + } + + asm ( "mtcr %0" : : "r" (cr_sav)); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/load.c b/post/cpu/load.c new file mode 100644 index 0000000..393c568 --- /dev/null +++ b/post/cpu/load.c @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Load instructions: lbz(x)(u), lhz(x)(u), lha(x)(u), lwz(x)(u) + * + * All operations are performed on a 16-byte array. The array + * is 4-byte aligned. The base register points to offset 8. + * The immediate offset (index register) ranges in [-8 ... +7]. + * The test cases are composed so that they do not + * cause alignment exceptions. + * The test contains a pre-built table describing all test cases. + * The table entry contains: + * the instruction opcode, the array contents, the value of the index + * register and the expected value of the destination register. + * After executing the instruction, the test verifies the + * value of the destination register and the value of the base + * register (it must change for "load with update" instructions). + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); +extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); + +static struct cpu_post_load_s +{ + ulong cmd; + uint width; + int update; + int index; + ulong offset; +} cpu_post_load_table[] = +{ + { + OP_LWZ, + 4, + 0, + 0, + 4 + }, + { + OP_LHA, + 3, + 0, + 0, + 2 + }, + { + OP_LHZ, + 2, + 0, + 0, + 2 + }, + { + OP_LBZ, + 1, + 0, + 0, + 1 + }, + { + OP_LWZU, + 4, + 1, + 0, + 4 + }, + { + OP_LHAU, + 3, + 1, + 0, + 2 + }, + { + OP_LHZU, + 2, + 1, + 0, + 2 + }, + { + OP_LBZU, + 1, + 1, + 0, + 1 + }, + { + OP_LWZX, + 4, + 0, + 1, + 4 + }, + { + OP_LHAX, + 3, + 0, + 1, + 2 + }, + { + OP_LHZX, + 2, + 0, + 1, + 2 + }, + { + OP_LBZX, + 1, + 0, + 1, + 1 + }, + { + OP_LWZUX, + 4, + 1, + 1, + 4 + }, + { + OP_LHAUX, + 3, + 1, + 1, + 2 + }, + { + OP_LHZUX, + 2, + 1, + 1, + 2 + }, + { + OP_LBZUX, + 1, + 1, + 1, + 1 + }, +}; +static unsigned int cpu_post_load_size = + sizeof (cpu_post_load_table) / sizeof (struct cpu_post_load_s); + +int cpu_post_test_load (void) +{ + int ret = 0; + unsigned int i; + + for (i = 0; i < cpu_post_load_size && ret == 0; i++) + { + struct cpu_post_load_s *test = cpu_post_load_table + i; + uchar data[16] = + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; + ulong base0 = (ulong) (data + 8); + ulong base = base0; + ulong value; + + if (test->index) + { + ulong code[] = + { + ASM_12(test->cmd, 5, 3, 4), + ASM_BLR, + }; + + cpu_post_exec_22w (code, &base, test->offset, &value); + } + else + { + ulong code[] = + { + ASM_11I(test->cmd, 4, 3, test->offset), + ASM_BLR, + }; + + cpu_post_exec_21w (code, &base, &value); + } + + if (ret == 0) + { + if (test->update) + ret = base == base0 + test->offset ? 0 : -1; + else + ret = base == base0 ? 0 : -1; + } + + if (ret == 0) + { + switch (test->width) + { + case 1: + ret = *(uchar *)(base0 + test->offset) == value ? + 0 : -1; + break; + case 2: + ret = *(ushort *)(base0 + test->offset) == value ? + 0 : -1; + break; + case 3: + ret = *(short *)(base0 + test->offset) == value ? + 0 : -1; + break; + case 4: + ret = *(ulong *)(base0 + test->offset) == value ? + 0 : -1; + break; + } + } + + if (ret != 0) + { + post_log ("Error at load test %d !\n", i); + } + } + + return ret; +} + +#endif +#endif diff --git a/post/cpu/multi.c b/post/cpu/multi.c new file mode 100644 index 0000000..8724384 --- /dev/null +++ b/post/cpu/multi.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Load/store multiple word instructions: lmw, stmw + * + * 26 consecutive words are loaded from a source memory buffer + * into GPRs r6 through r31. After that, 26 consecutive words are stored + * from the GPRs r6 through r31 into a target memory buffer. The contents + * of the source and target buffers are then compared. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); + +int cpu_post_test_multi (void) +{ + int ret = 0; + unsigned int i; + + if (ret == 0) + { + ulong src [26], dst [26]; + + ulong code[] = + { + ASM_LMW(5, 3, 0), + ASM_STMW(5, 4, 0), + ASM_BLR, + }; + + for (i = 0; i < sizeof(src) / sizeof(src[0]); i ++) + { + src[i] = i; + dst[i] = 0; + } + + cpu_post_exec_02(code, (ulong)src, (ulong)dst); + + ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1; + } + + if (ret != 0) + { + post_log ("Error at multi test !\n"); + } + + return ret; +} + +#endif +#endif diff --git a/post/cpu/rlwimi.c b/post/cpu/rlwimi.c new file mode 100644 index 0000000..f65f79a --- /dev/null +++ b/post/cpu/rlwimi.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Shift instructions: rlwimi + * + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, + ulong op2); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_rlwimi_s +{ + ulong cmd; + ulong op0; + ulong op1; + uchar op2; + uchar mb; + uchar me; + ulong res; +} cpu_post_rlwimi_table[] = +{ + { + OP_RLWIMI, + 0xff00ffff, + 0x0000aa00, + 8, + 8, + 15, + 0xffaaffff + }, +}; +static unsigned int cpu_post_rlwimi_size = + sizeof (cpu_post_rlwimi_table) / sizeof (struct cpu_post_rlwimi_s); + +int cpu_post_test_rlwimi (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_rlwimi_size && ret == 0; i++) + { + struct cpu_post_rlwimi_s *test = cpu_post_rlwimi_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long code[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -20), + ASM_STW(3, stk, 8), + ASM_STW(4, stk, 12), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg1, stk, 8), + ASM_LWZ(reg0, stk, 12), + ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 20), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + unsigned long codecr[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -20), + ASM_STW(3, stk, 8), + ASM_STW(4, stk, 12), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg1, stk, 8), + ASM_LWZ(reg0, stk, 12), + ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) | + BIT_C, + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 20), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + if (ret == 0) + { + cr = 0; + cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1); + + ret = res == test->res && cr == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at rlwimi test %d !\n", i); + } + } + + if (ret == 0) + { + cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1); + + ret = res == test->res && + (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at rlwimi test %d !\n", i); + } + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/rlwinm.c b/post/cpu/rlwinm.c new file mode 100644 index 0000000..e240c41 --- /dev/null +++ b/post/cpu/rlwinm.c @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Shift instructions: rlwinm + * + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_rlwinm_s +{ + ulong cmd; + ulong op1; + uchar op2; + uchar mb; + uchar me; + ulong res; +} cpu_post_rlwinm_table[] = +{ + { + OP_RLWINM, + 0xffff0000, + 24, + 16, + 23, + 0x0000ff00 + }, +}; +static unsigned int cpu_post_rlwinm_size = + sizeof (cpu_post_rlwinm_table) / sizeof (struct cpu_post_rlwinm_s); + +int cpu_post_test_rlwinm (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++) + { + struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long code[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + unsigned long codecr[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, + test->me) | BIT_C, + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + if (ret == 0) + { + cr = 0; + cpu_post_exec_21 (code, & cr, & res, test->op1); + + ret = res == test->res && cr == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at rlwinm test %d !\n", i); + } + } + + if (ret == 0) + { + cpu_post_exec_21 (codecr, & cr, & res, test->op1); + + ret = res == test->res && + (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at rlwinm test %d !\n", i); + } + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/rlwnm.c b/post/cpu/rlwnm.c new file mode 100644 index 0000000..523cf4d --- /dev/null +++ b/post/cpu/rlwnm.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Shift instructions: rlwnm + * + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, + ulong op2); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_rlwnm_s +{ + ulong cmd; + ulong op1; + ulong op2; + uchar mb; + uchar me; + ulong res; +} cpu_post_rlwnm_table[] = +{ + { + OP_RLWNM, + 0xffff0000, + 24, + 16, + 23, + 0x0000ff00 + }, +}; +static unsigned int cpu_post_rlwnm_size = + sizeof (cpu_post_rlwnm_table) / sizeof (struct cpu_post_rlwnm_s); + +int cpu_post_test_rlwnm (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++) + { + struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int reg2 = (reg + 2) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long code[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -24), + ASM_STW(3, stk, 12), + ASM_STW(4, stk, 16), + ASM_STW(reg0, stk, 8), + ASM_STW(reg1, stk, 4), + ASM_STW(reg2, stk, 0), + ASM_LWZ(reg1, stk, 12), + ASM_LWZ(reg0, stk, 16), + ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), + ASM_STW(reg2, stk, 12), + ASM_LWZ(reg2, stk, 0), + ASM_LWZ(reg1, stk, 4), + ASM_LWZ(reg0, stk, 8), + ASM_LWZ(3, stk, 12), + ASM_ADDI(1, stk, 24), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + unsigned long codecr[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -24), + ASM_STW(3, stk, 12), + ASM_STW(4, stk, 16), + ASM_STW(reg0, stk, 8), + ASM_STW(reg1, stk, 4), + ASM_STW(reg2, stk, 0), + ASM_LWZ(reg1, stk, 12), + ASM_LWZ(reg0, stk, 16), + ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | + BIT_C, + ASM_STW(reg2, stk, 12), + ASM_LWZ(reg2, stk, 0), + ASM_LWZ(reg1, stk, 4), + ASM_LWZ(reg0, stk, 8), + ASM_LWZ(3, stk, 12), + ASM_ADDI(1, stk, 24), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + if (ret == 0) + { + cr = 0; + cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); + + ret = res == test->res && cr == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at rlwnm test %d !\n", i); + } + } + + if (ret == 0) + { + cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); + + ret = res == test->res && + (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at rlwnm test %d !\n", i); + } + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/srawi.c b/post/cpu/srawi.c new file mode 100644 index 0000000..91c82c9 --- /dev/null +++ b/post/cpu/srawi.c @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Shift instructions: srawi + * + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_srawi_s +{ + ulong cmd; + ulong op1; + uchar op2; + ulong res; +} cpu_post_srawi_table[] = +{ + { + OP_SRAWI, + 0x8000, + 3, + 0x1000 + }, + { + OP_SRAWI, + 0x80000000, + 3, + 0xf0000000 + }, +}; +static unsigned int cpu_post_srawi_size = + sizeof (cpu_post_srawi_table) / sizeof (struct cpu_post_srawi_s); + +int cpu_post_test_srawi (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_srawi_size && ret == 0; i++) + { + struct cpu_post_srawi_s *test = cpu_post_srawi_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long code[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_11S(test->cmd, reg1, reg0, test->op2), + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + unsigned long codecr[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + if (ret == 0) + { + cr = 0; + cpu_post_exec_21 (code, & cr, & res, test->op1); + + ret = res == test->res && cr == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at srawi test %d !\n", i); + } + } + + if (ret == 0) + { + cpu_post_exec_21 (codecr, & cr, & res, test->op1); + + ret = res == test->res && + (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at srawi test %d !\n", i); + } + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/store.c b/post/cpu/store.c new file mode 100644 index 0000000..f495bf2 --- /dev/null +++ b/post/cpu/store.c @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Store instructions: stb(x)(u), sth(x)(u), stw(x)(u) + * + * All operations are performed on a 16-byte array. The array + * is 4-byte aligned. The base register points to offset 8. + * The immediate offset (index register) ranges in [-8 ... +7]. + * The test cases are composed so that they do not + * cause alignment exceptions. + * The test contains a pre-built table describing all test cases. + * The table entry contains: + * the instruction opcode, the value of the index register and + * the value of the source register. After executing the + * instruction, the test verifies the contents of the array + * and the value of the base register (it must change for "store + * with update" instructions). + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); +extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); + +static struct cpu_post_store_s +{ + ulong cmd; + uint width; + int update; + int index; + ulong offset; + ulong value; +} cpu_post_store_table[] = +{ + { + OP_STW, + 4, + 0, + 0, + -4, + 0xff00ff00 + }, + { + OP_STH, + 2, + 0, + 0, + -2, + 0xff00 + }, + { + OP_STB, + 1, + 0, + 0, + -1, + 0xff + }, + { + OP_STWU, + 4, + 1, + 0, + -4, + 0xff00ff00 + }, + { + OP_STHU, + 2, + 1, + 0, + -2, + 0xff00 + }, + { + OP_STBU, + 1, + 1, + 0, + -1, + 0xff + }, + { + OP_STWX, + 4, + 0, + 1, + -4, + 0xff00ff00 + }, + { + OP_STHX, + 2, + 0, + 1, + -2, + 0xff00 + }, + { + OP_STBX, + 1, + 0, + 1, + -1, + 0xff + }, + { + OP_STWUX, + 4, + 1, + 1, + -4, + 0xff00ff00 + }, + { + OP_STHUX, + 2, + 1, + 1, + -2, + 0xff00 + }, + { + OP_STBUX, + 1, + 1, + 1, + -1, + 0xff + }, +}; +static unsigned int cpu_post_store_size = + sizeof (cpu_post_store_table) / sizeof (struct cpu_post_store_s); + +int cpu_post_test_store (void) +{ + int ret = 0; + unsigned int i; + + for (i = 0; i < cpu_post_store_size && ret == 0; i++) + { + struct cpu_post_store_s *test = cpu_post_store_table + i; + uchar data[16] = + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; + ulong base0 = (ulong) (data + 8); + ulong base = base0; + + if (test->index) + { + ulong code[] = + { + ASM_12(test->cmd, 5, 3, 4), + ASM_BLR, + }; + + cpu_post_exec_12w (code, &base, test->offset, test->value); + } + else + { + ulong code[] = + { + ASM_11I(test->cmd, 4, 3, test->offset), + ASM_BLR, + }; + + cpu_post_exec_11w (code, &base, test->value); + } + + if (ret == 0) + { + if (test->update) + ret = base == base0 + test->offset ? 0 : -1; + else + ret = base == base0 ? 0 : -1; + } + + if (ret == 0) + { + switch (test->width) + { + case 1: + ret = *(uchar *)(base0 + test->offset) == test->value ? + 0 : -1; + break; + case 2: + ret = *(ushort *)(base0 + test->offset) == test->value ? + 0 : -1; + break; + case 4: + ret = *(ulong *)(base0 + test->offset) == test->value ? + 0 : -1; + break; + } + } + + if (ret != 0) + { + post_log ("Error at store test %d !\n", i); + } + } + + return ret; +} + +#endif +#endif diff --git a/post/cpu/string.c b/post/cpu/string.c new file mode 100644 index 0000000..bd83bd1 --- /dev/null +++ b/post/cpu/string.c @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Load/store string instructions: lswi, stswi, lswx, stswx + * + * Several consecutive bytes from a source memory buffer are loaded + * left to right into GPRs. After that, the bytes are stored + * from the GPRs into a target memory buffer. The contents + * of the source and target buffers are then compared. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); +extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, + ulong op4); + +#include +int cpu_post_test_string (void) +{ + int ret = 0; + unsigned int i; + + if (ret == 0) + { + char src [31], dst [31]; + + ulong code[] = + { + ASM_LSWI(5, 3, 31), + ASM_STSWI(5, 4, 31), + ASM_BLR, + }; + + for (i = 0; i < sizeof(src); i ++) + { + src[i] = (char) i; + dst[i] = 0; + } + + cpu_post_exec_02(code, (ulong)src, (ulong)dst); + + ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1; + } + + if (ret == 0) + { + char src [95], dst [95]; + + ulong code[] = + { + ASM_LSWX(8, 3, 5), + ASM_STSWX(8, 4, 5), + ASM_BLR, + }; + + for (i = 0; i < sizeof(src); i ++) + { + src[i] = (char) i; + dst[i] = 0; + } + + cpu_post_exec_04(code, (ulong)src, (ulong)dst, 0, sizeof(src)); + + ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1; + } + + if (ret != 0) + { + post_log ("Error at string test !\n"); + } + + return ret; +} + +#endif +#endif diff --git a/post/cpu/three.c b/post/cpu/three.c new file mode 100644 index 0000000..c2d7476 --- /dev/null +++ b/post/cpu/three.c @@ -0,0 +1,259 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Ternary instructions instr rD,rA,rB + * + * Arithmetic instructions: add, addc, adde, subf, subfc, subfe, + * mullw, mulhw, mulhwu, divw, divwu + * + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, + ulong op2); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_three_s +{ + ulong cmd; + ulong op1; + ulong op2; + ulong res; +} cpu_post_three_table[] = +{ + { + OP_ADD, + 100, + 200, + 300 + }, + { + OP_ADD, + 100, + -200, + -100 + }, + { + OP_ADDC, + 100, + 200, + 300 + }, + { + OP_ADDC, + 100, + -200, + -100 + }, + { + OP_ADDE, + 100, + 200, + 300 + }, + { + OP_ADDE, + 100, + -200, + -100 + }, + { + OP_SUBF, + 100, + 200, + 100 + }, + { + OP_SUBF, + 300, + 200, + -100 + }, + { + OP_SUBFC, + 100, + 200, + 100 + }, + { + OP_SUBFC, + 300, + 200, + -100 + }, + { + OP_SUBFE, + 100, + 200, + 200 + ~100 + }, + { + OP_SUBFE, + 300, + 200, + 200 + ~300 + }, + { + OP_MULLW, + 200, + 300, + 200 * 300 + }, + { + OP_MULHW, + 0x10000000, + 0x10000000, + 0x1000000 + }, + { + OP_MULHWU, + 0x80000000, + 0x80000000, + 0x40000000 + }, + { + OP_DIVW, + -20, + 5, + -4 + }, + { + OP_DIVWU, + 0x8000, + 0x200, + 0x40 + }, +}; +static unsigned int cpu_post_three_size = + sizeof (cpu_post_three_table) / sizeof (struct cpu_post_three_s); + +int cpu_post_test_three (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_three_size && ret == 0; i++) + { + struct cpu_post_three_s *test = cpu_post_three_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int reg2 = (reg + 2) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long code[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -24), + ASM_STW(3, stk, 12), + ASM_STW(4, stk, 16), + ASM_STW(reg0, stk, 8), + ASM_STW(reg1, stk, 4), + ASM_STW(reg2, stk, 0), + ASM_LWZ(reg1, stk, 12), + ASM_LWZ(reg0, stk, 16), + ASM_12(test->cmd, reg2, reg1, reg0), + ASM_STW(reg2, stk, 12), + ASM_LWZ(reg2, stk, 0), + ASM_LWZ(reg1, stk, 4), + ASM_LWZ(reg0, stk, 8), + ASM_LWZ(3, stk, 12), + ASM_ADDI(1, stk, 24), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + unsigned long codecr[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -24), + ASM_STW(3, stk, 12), + ASM_STW(4, stk, 16), + ASM_STW(reg0, stk, 8), + ASM_STW(reg1, stk, 4), + ASM_STW(reg2, stk, 0), + ASM_LWZ(reg1, stk, 12), + ASM_LWZ(reg0, stk, 16), + ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, + ASM_STW(reg2, stk, 12), + ASM_LWZ(reg2, stk, 0), + ASM_LWZ(reg1, stk, 4), + ASM_LWZ(reg0, stk, 8), + ASM_LWZ(3, stk, 12), + ASM_ADDI(1, stk, 24), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + if (ret == 0) + { + cr = 0; + cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); + + ret = res == test->res && cr == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at three test %d !\n", i); + } + } + + if (ret == 0) + { + cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); + + ret = res == test->res && + (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at three test %d !\n", i); + } + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/threei.c b/post/cpu/threei.c new file mode 100644 index 0000000..79f0178 --- /dev/null +++ b/post/cpu/threei.c @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Ternary instructions instr rA,rS,UIMM + * + * Logic instructions: ori, oris, xori, xoris + * + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_threei_s +{ + ulong cmd; + ulong op1; + ushort op2; + ulong res; +} cpu_post_threei_table[] = +{ + { + OP_ORI, + 0x80000000, + 0xffff, + 0x8000ffff + }, + { + OP_ORIS, + 0x00008000, + 0xffff, + 0xffff8000 + }, + { + OP_XORI, + 0x8000ffff, + 0xffff, + 0x80000000 + }, + { + OP_XORIS, + 0x00008000, + 0xffff, + 0xffff8000 + }, +}; +static unsigned int cpu_post_threei_size = + sizeof (cpu_post_threei_table) / sizeof (struct cpu_post_threei_s); + +int cpu_post_test_threei (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_threei_size && ret == 0; i++) + { + struct cpu_post_threei_s *test = cpu_post_threei_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long code[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_11IX(test->cmd, reg1, reg0, test->op2), + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + cr = 0; + cpu_post_exec_21 (code, & cr, & res, test->op1); + + ret = res == test->res && cr == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at threei test %d !\n", i); + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/threex.c b/post/cpu/threex.c new file mode 100644 index 0000000..2c72063 --- /dev/null +++ b/post/cpu/threex.c @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Ternary instructions instr rA,rS,rB + * + * Logic instructions: or, orc, xor, nand, nor, eqv + * Shift instructions: slw, srw, sraw + * + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, + ulong op2); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_threex_s +{ + ulong cmd; + ulong op1; + ulong op2; + ulong res; +} cpu_post_threex_table[] = +{ + { + OP_OR, + 0x1234, + 0x5678, + 0x1234 | 0x5678 + }, + { + OP_ORC, + 0x1234, + 0x5678, + 0x1234 | ~0x5678 + }, + { + OP_XOR, + 0x1234, + 0x5678, + 0x1234 ^ 0x5678 + }, + { + OP_NAND, + 0x1234, + 0x5678, + ~(0x1234 & 0x5678) + }, + { + OP_NOR, + 0x1234, + 0x5678, + ~(0x1234 | 0x5678) + }, + { + OP_EQV, + 0x1234, + 0x5678, + ~(0x1234 ^ 0x5678) + }, + { + OP_SLW, + 0x80, + 16, + 0x800000 + }, + { + OP_SLW, + 0x80, + 32, + 0 + }, + { + OP_SRW, + 0x800000, + 16, + 0x80 + }, + { + OP_SRW, + 0x800000, + 32, + 0 + }, + { + OP_SRAW, + 0x80000000, + 3, + 0xf0000000 + }, + { + OP_SRAW, + 0x8000, + 3, + 0x1000 + }, +}; +static unsigned int cpu_post_threex_size = + sizeof (cpu_post_threex_table) / sizeof (struct cpu_post_threex_s); + +int cpu_post_test_threex (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_threex_size && ret == 0; i++) + { + struct cpu_post_threex_s *test = cpu_post_threex_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int reg2 = (reg + 2) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long code[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -24), + ASM_STW(3, stk, 12), + ASM_STW(4, stk, 16), + ASM_STW(reg0, stk, 8), + ASM_STW(reg1, stk, 4), + ASM_STW(reg2, stk, 0), + ASM_LWZ(reg1, stk, 12), + ASM_LWZ(reg0, stk, 16), + ASM_12X(test->cmd, reg2, reg1, reg0), + ASM_STW(reg2, stk, 12), + ASM_LWZ(reg2, stk, 0), + ASM_LWZ(reg1, stk, 4), + ASM_LWZ(reg0, stk, 8), + ASM_LWZ(3, stk, 12), + ASM_ADDI(1, stk, 24), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + unsigned long codecr[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -24), + ASM_STW(3, stk, 12), + ASM_STW(4, stk, 16), + ASM_STW(reg0, stk, 8), + ASM_STW(reg1, stk, 4), + ASM_STW(reg2, stk, 0), + ASM_LWZ(reg1, stk, 12), + ASM_LWZ(reg0, stk, 16), + ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C, + ASM_STW(reg2, stk, 12), + ASM_LWZ(reg2, stk, 0), + ASM_LWZ(reg1, stk, 4), + ASM_LWZ(reg0, stk, 8), + ASM_LWZ(3, stk, 12), + ASM_ADDI(1, stk, 24), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + if (ret == 0) + { + cr = 0; + cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); + + ret = res == test->res && cr == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at threex test %d !\n", i); + } + } + + if (ret == 0) + { + cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); + + ret = res == test->res && + (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at threex test %d !\n", i); + } + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/two.c b/post/cpu/two.c new file mode 100644 index 0000000..cfbac5e --- /dev/null +++ b/post/cpu/two.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Binary instructions instr rD,rA + * + * Logic instructions: neg + * Arithmetic instructions: addme, addze, subfme, subfze + + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_two_s +{ + ulong cmd; + ulong op; + ulong res; +} cpu_post_two_table[] = +{ + { + OP_NEG, + 3, + -3 + }, + { + OP_NEG, + 5, + -5 + }, + { + OP_ADDME, + 6, + 5 + }, + { + OP_ADDZE, + 5, + 5 + }, + { + OP_SUBFME, + 6, + ~6 - 1 + }, + { + OP_SUBFZE, + 5, + ~5 + }, +}; +static unsigned int cpu_post_two_size = + sizeof (cpu_post_two_table) / sizeof (struct cpu_post_two_s); + +int cpu_post_test_two (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_two_size && ret == 0; i++) + { + struct cpu_post_two_s *test = cpu_post_two_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long code[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_11(test->cmd, reg1, reg0), + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + unsigned long codecr[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_11(test->cmd, reg1, reg0) | BIT_C, + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + if (ret == 0) + { + cr = 0; + cpu_post_exec_21 (code, & cr, & res, test->op); + + ret = res == test->res && cr == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at two test %d !\n", i); + } + } + + if (ret == 0) + { + cpu_post_exec_21 (codecr, & cr, & res, test->op); + + ret = res == test->res && + (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at two test %d !\n", i); + } + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/cpu/twox.c b/post/cpu/twox.c new file mode 100644 index 0000000..48d9954 --- /dev/null +++ b/post/cpu/twox.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * CPU test + * Binary instructions instr rA,rS + * + * Logic instructions: cntlzw + * Arithmetic instructions: extsb, extsh + + * The test contains a pre-built table of instructions, operands and + * expected results. For each table entry, the test will cyclically use + * different sets of operand registers and result registers. + */ + +#ifdef CONFIG_POST + +#include +#include "cpu_asm.h" + +#if CONFIG_POST & CFG_POST_CPU + +extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); +extern ulong cpu_post_makecr (long v); + +static struct cpu_post_twox_s +{ + ulong cmd; + ulong op; + ulong res; +} cpu_post_twox_table[] = +{ + { + OP_EXTSB, + 3, + 3 + }, + { + OP_EXTSB, + 0xff, + -1 + }, + { + OP_EXTSH, + 3, + 3 + }, + { + OP_EXTSH, + 0xff, + 0xff + }, + { + OP_EXTSH, + 0xffff, + -1 + }, + { + OP_CNTLZW, + 0x000fffff, + 12 + }, +}; +static unsigned int cpu_post_twox_size = + sizeof (cpu_post_twox_table) / sizeof (struct cpu_post_twox_s); + +int cpu_post_test_twox (void) +{ + int ret = 0; + unsigned int i, reg; + int flag = disable_interrupts(); + + for (i = 0; i < cpu_post_twox_size && ret == 0; i++) + { + struct cpu_post_twox_s *test = cpu_post_twox_table + i; + + for (reg = 0; reg < 32 && ret == 0; reg++) + { + unsigned int reg0 = (reg + 0) % 32; + unsigned int reg1 = (reg + 1) % 32; + unsigned int stk = reg < 16 ? 31 : 15; + unsigned long code[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_11X(test->cmd, reg1, reg0), + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + unsigned long codecr[] = + { + ASM_STW(stk, 1, -4), + ASM_ADDI(stk, 1, -16), + ASM_STW(3, stk, 8), + ASM_STW(reg0, stk, 4), + ASM_STW(reg1, stk, 0), + ASM_LWZ(reg0, stk, 8), + ASM_11X(test->cmd, reg1, reg0) | BIT_C, + ASM_STW(reg1, stk, 8), + ASM_LWZ(reg1, stk, 0), + ASM_LWZ(reg0, stk, 4), + ASM_LWZ(3, stk, 8), + ASM_ADDI(1, stk, 16), + ASM_LWZ(stk, 1, -4), + ASM_BLR, + }; + ulong res; + ulong cr; + + if (ret == 0) + { + cr = 0; + cpu_post_exec_21 (code, & cr, & res, test->op); + + ret = res == test->res && cr == 0 ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at twox test %d !\n", i); + } + } + + if (ret == 0) + { + cpu_post_exec_21 (codecr, & cr, & res, test->op); + + ret = res == test->res && + (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; + + if (ret != 0) + { + post_log ("Error at twox test %d !\n", i); + } + } + } + } + + if (flag) + enable_interrupts(); + + return ret; +} + +#endif +#endif diff --git a/post/dsp.c b/post/dsp.c new file mode 100644 index 0000000..63531a2 --- /dev/null +++ b/post/dsp.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2004 + * Pantelis Antoniou, Intracom S.A. , panto@intracom.gr + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * DSP test + * + * This test verifies the connection and performs a memory test + * on any connected DSP(s). The meat of the work is done + * in the board specific function. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_DSP + +extern int board_post_dsp(int flags); + +int dsp_post_test (int flags) +{ + return board_post_dsp(flags); +} + +#endif /* CONFIG_POST & CFG_POST_DSP */ +#endif /* CONFIG_POST */ diff --git a/post/ether.c b/post/ether.c new file mode 100644 index 0000000..660620e --- /dev/null +++ b/post/ether.c @@ -0,0 +1,630 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * Ethernet test + * + * The Serial Communication Controllers (SCC) listed in ctlr_list array below + * are tested in the loopback ethernet mode. + * The controllers are configured accordingly and several packets + * are transmitted. The configurable test parameters are: + * MIN_PACKET_LENGTH - minimum size of packet to transmit + * MAX_PACKET_LENGTH - maximum size of packet to transmit + * TEST_NUM - number of tests + */ + +#ifdef CONFIG_POST + +#include +#if CONFIG_POST & CFG_POST_ETHER +#if defined(CONFIG_8xx) +#include +#elif defined(CONFIG_MPC8260) +#include +#else +#error "Apparently a bad configuration, please fix." +#endif + +#include +#include +#include + +#define MIN_PACKET_LENGTH 64 +#define MAX_PACKET_LENGTH 256 +#define TEST_NUM 1 + +#define CTLR_SCC 0 + +extern void spi_init_f (void); +extern void spi_init_r (void); + +/* The list of controllers to test */ +#if defined(CONFIG_MPC823) +static int ctlr_list[][2] = { {CTLR_SCC, 1} }; +#else +static int ctlr_list[][2] = { }; +#endif + +#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0])) + +static struct { + void (*init) (int index); + void (*halt) (int index); + int (*send) (int index, volatile void *packet, int length); + int (*recv) (int index, void *packet, int length); +} ctlr_proc[1]; + +static char *ctlr_name[1] = { "SCC" }; + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +#define TOUT_LOOP 100 + +static char txbuf[DBUF_LENGTH]; + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * SCC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +typedef volatile struct CommonBufferDescriptor { + cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ + cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ +} RTXBD; + +static RTXBD *rtx; + + /* + * SCC callbacks + */ + +static void scc_init (int scc_index) +{ + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; + + static int proff[] = + { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 }; + static unsigned int cpm_cr[] = + { CPM_CR_CH_SCC1, CPM_CR_CH_SCC2, CPM_CR_CH_SCC3, +CPM_CR_CH_SCC4 }; + + int i; + scc_enet_t *pram_ptr; + + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + immr->im_cpm.cp_scc[scc_index].scc_gsmrl &= + ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + +#if defined(CONFIG_FADS) +#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS) + /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */ + *((uint *) BCSR4) &= ~BCSR4_ETHLOOP; + *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL; + *((uint *) BCSR1) &= ~BCSR1_ETHEN; +#else + *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN); + *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE; + *((uint *) BCSR1) &= ~BCSR1_ETHEN; +#endif +#endif + + pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]); + + rxIdx = 0; + txIdx = 0; + +#ifdef CFG_ALLOC_DPRAM + rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + + dpram_alloc_align (sizeof (RTXBD), 8)); +#else + rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); +#endif + +#if 0 + +#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) + /* Configure port A pins for Txd and Rxd. + */ + immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); + immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); + immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; +#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) + /* Configure port B pins for Txd and Rxd. + */ + immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); + immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); + immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; +#else +#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined +#endif + +#if defined(PC_ENET_LBK) + /* Configure port C pins to disable External Loopback + */ + immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; + immr->im_ioport.iop_pcdir |= PC_ENET_LBK; + immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; + immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ +#endif /* PC_ENET_LBK */ + + /* Configure port C pins to enable CLSN and RENA. + */ + immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); + immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); + immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); + + /* Configure port A for TCLK and RCLK. + */ + immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); + immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); + + /* + * Configure Serial Interface clock routing -- see section 16.7.5.3 + * First, clear all SCC bits to zero, then set the ones we want. + */ + + immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; + immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; +#else + /* + * SCC2 receive clock is BRG2 + * SCC2 transmit clock is BRG3 + */ + immr->im_cpm.cp_brgc2 = 0x0001000C; + immr->im_cpm.cp_brgc3 = 0x0001000C; + + immr->im_cpm.cp_sicr &= ~0x00003F00; + immr->im_cpm.cp_sicr |= 0x00000a00; +#endif /* 0 */ + + + /* + * Initialize SDCR -- see section 16.9.23.7 + * SDMA configuration register + */ + immr->im_siu_conf.sc_sdcr = 0x01; + + + /* + * Setup SCC Ethernet Parameter RAM + */ + + pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ + pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ + + pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ + + pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ + pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ + + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + + for (i = 0; i < PKTBUFSRX; i++) { + rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx->rxbd[i].cbd_datlen = 0; /* Reset */ + rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + + rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Add PADs to Short FRAMES, Wrap, Last, Tx CRC + */ + + for (i = 0; i < TX_BUF_CNT; i++) { + rtx->txbd[i].cbd_sc = + (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); + rtx->txbd[i].cbd_datlen = 0; /* Reset */ + rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); + } + + rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* + * Enter Command: Initialize Rx Params for SCC + */ + + do { /* Spin until ready to issue command */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + /* Issue command */ + immr->im_cpm.cp_cpcr = + ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) | + CPM_CR_FLG); + do { /* Spin until command processed */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + + /* + * Ethernet Specific Parameter RAM + * see table 13-16, pg. 660, + * pg. 681 (example with suggested settings) + */ + + pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ + pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ + pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ + pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ + pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ + pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ + + pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ + pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ + pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ + + pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ + pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ + + pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ + pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ + pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ + pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ + +#define ea bd->bi_enetaddr + pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; + pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; + pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; +#undef ea + + pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ + pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ + pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ + pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ + pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ + pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ + pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ + pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ + + /* + * Enter Command: Initialize Tx Params for SCC + */ + + do { /* Spin until ready to issue command */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + /* Issue command */ + immr->im_cpm.cp_cpcr = + ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) | + CPM_CR_FLG); + do { /* Spin until command processed */ + __asm__ ("eieio"); + } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); + + /* + * Mask all Events in SCCM - we use polling mode + */ + immr->im_cpm.cp_scc[scc_index].scc_sccm = 0; + + /* + * Clear Events in SCCE -- Clear bits by writing 1's + */ + + immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0); + + + /* + * Initialize GSMR High 32-Bits + * Settings: Normal Mode + */ + + immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0; + + /* + * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive + * Settings: + * TCI = Invert + * TPL = 48 bits + * TPP = Repeating 10's + * LOOP = Loopback + * MODE = Ethernet + */ + + immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI | + SCC_GSMRL_TPL_48 | + SCC_GSMRL_TPP_10 | + SCC_GSMRL_DIAG_LOOP | + SCC_GSMRL_MODE_ENET); + + /* + * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 + */ + + immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555; + + /* + * Initialize the PSMR + * Settings: + * CRC = 32-Bit CCITT + * NIB = Begin searching for SFD 22 bits after RENA + * LPB = Loopback Enable (Needed when FDE is set) + */ + immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC | + SCC_PSMR_NIB22 | SCC_PSMR_LPB; + +#if 0 + /* + * Configure Ethernet TENA Signal + */ + +#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) + immr->im_ioport.iop_pcpar |= PC_ENET_TENA; + immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; +#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) + immr->im_cpm.cp_pbpar |= PB_ENET_TENA; + immr->im_cpm.cp_pbdir |= PB_ENET_TENA; +#else +#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined +#endif + +#if defined(CONFIG_ADS) && defined(CONFIG_MPC860) + /* + * Port C is used to control the PHY,MC68160. + */ + immr->im_ioport.iop_pcdir |= + (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); + + immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; + immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); + *((uint *) BCSR1) &= ~BCSR1_ETHEN; +#endif /* MPC860ADS */ + +#if defined(CONFIG_AMX860) + /* + * Port B is used to control the PHY,MC68160. + */ + immr->im_cpm.cp_pbdir |= + (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL); + + immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL; + immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL); + + immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN; + immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN; +#endif /* AMX860 */ + +#endif /* 0 */ + +#ifdef CONFIG_RPXCLASSIC + *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; + *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); +#endif + +#ifdef CONFIG_RPXLITE + *((uchar *) BCSR0) |= BCSR0_ETHEN; +#endif + +#ifdef CONFIG_MBX + board_ether_init (); +#endif + + /* + * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive + */ + + immr->im_cpm.cp_scc[scc_index].scc_gsmrl |= + (SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + /* + * Work around transmit problem with first eth packet + */ +#if defined (CONFIG_FADS) + udelay (10000); /* wait 10 ms */ +#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC) + udelay (100000); /* wait 100 ms */ +#endif +} + +static void scc_halt (int scc_index) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + immr->im_cpm.cp_scc[scc_index].scc_gsmrl &= + ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); +} + +static int scc_send (int index, volatile void *packet, int length) +{ + int i, j = 0; + + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) { + udelay (1); /* will also trigger Wd if needed */ + j++; + } + if (j >= TOUT_LOOP) + printf ("TX not ready\n"); + rtx->txbd[txIdx].cbd_bufaddr = (uint) packet; + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= + (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP); + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) { + udelay (1); /* will also trigger Wd if needed */ + j++; + } + if (j >= TOUT_LOOP) + printf ("TX timeout\n"); + i = (rtx->txbd[txIdx]. + cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ; + return i; +} + +static int scc_recv (int index, void *packet, int max_length) +{ + int length = -1; + + if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + goto Done; /* nothing received */ + } + + if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) { + length = rtx->rxbd[rxIdx].cbd_datlen - 4; + memcpy (packet, + (void *) (NetRxPackets[rxIdx]), + length < max_length ? length : max_length); + } + + /* Give the buffer back to the SCC. */ + rtx->rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx->rxbd[PKTBUFSRX - 1].cbd_sc = + (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } else { + rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + +Done: + return length; +} + + /* + * Test routines + */ + +static void packet_fill (char *packet, int length) +{ + char c = (char) length; + int i; + + packet[0] = 0xFF; + packet[1] = 0xFF; + packet[2] = 0xFF; + packet[3] = 0xFF; + packet[4] = 0xFF; + packet[5] = 0xFF; + + for (i = 6; i < length; i++) { + packet[i] = c++; + } +} + +static int packet_check (char *packet, int length) +{ + char c = (char) length; + int i; + + for (i = 6; i < length; i++) { + if (packet[i] != c++) + return -1; + } + + return 0; +} + +static int test_ctlr (int ctlr, int index) +{ + int res = -1; + char packet_send[MAX_PACKET_LENGTH]; + char packet_recv[MAX_PACKET_LENGTH]; + int length; + int i; + int l; + + ctlr_proc[ctlr].init (index); + + for (i = 0; i < TEST_NUM; i++) { + for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) { + packet_fill (packet_send, l); + + ctlr_proc[ctlr].send (index, packet_send, l); + + length = ctlr_proc[ctlr].recv (index, packet_recv, + MAX_PACKET_LENGTH); + + if (length != l || packet_check (packet_recv, length) < 0) { + goto Done; + } + } + } + + res = 0; + +Done: + + ctlr_proc[ctlr].halt (index); + + /* + * SCC2 Ethernet parameter RAM space overlaps + * the SPI parameter RAM space. So we need to restore + * the SPI configuration after SCC2 ethernet test. + */ +#if defined(CONFIG_SPI) + if (ctlr == CTLR_SCC && index == 1) { + spi_init_f (); + spi_init_r (); + } +#endif + + if (res != 0) { + post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr], + index + 1); + } + + return res; +} + +int ether_post_test (int flags) +{ + int res = 0; + int i; + + ctlr_proc[CTLR_SCC].init = scc_init; + ctlr_proc[CTLR_SCC].halt = scc_halt; + ctlr_proc[CTLR_SCC].send = scc_send; + ctlr_proc[CTLR_SCC].recv = scc_recv; + + for (i = 0; i < CTRL_LIST_SIZE; i++) { + if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { + res = -1; + } + } + +#if !defined(CONFIG_8xx_CONS_NONE) + serial_reinit_all (); +#endif + return res; +} + +#endif /* CONFIG_POST & CFG_POST_ETHER */ + +#endif /* CONFIG_POST */ diff --git a/post/i2c.c b/post/i2c.c new file mode 100644 index 0000000..1b2e644 --- /dev/null +++ b/post/i2c.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_POST + +/* + * I2C test + * + * For verifying the I2C bus, a full I2C bus scanning is performed. + * + * #ifdef I2C_ADDR_LIST + * The test is considered as passed if all the devices and + * only the devices in the list are found. + * #else [ ! I2C_ADDR_LIST ] + * The test is considered as passed if any I2C device is found. + * #endif + */ + +#include +#include + +#if CONFIG_POST & CFG_POST_I2C + +int i2c_post_test (int flags) +{ + unsigned int i; + unsigned int good = 0; +#ifdef I2C_ADDR_LIST + unsigned int bad = 0; + int j; + unsigned char i2c_addr_list[] = I2C_ADDR_LIST; + unsigned char i2c_miss_list[] = I2C_ADDR_LIST; +#endif + + for (i = 0; i < 128; i++) { + if (i2c_probe (i) == 0) { +#ifndef I2C_ADDR_LIST + good++; +#else /* I2C_ADDR_LIST */ + for (j=0; j 0 ? 0 : -1; +#else /* I2C_ADDR_LIST */ + if (good != sizeof(i2c_addr_list)) { + for (j=0; j + +/* Memory test + * + * General observations: + * o The recommended test sequence is to test the data lines: if they are + * broken, nothing else will work properly. Then test the address + * lines. Finally, test the cells in the memory now that the test + * program knows that the address and data lines work properly. + * This sequence also helps isolate and identify what is faulty. + * + * o For the address line test, it is a good idea to use the base + * address of the lowest memory location, which causes a '1' bit to + * walk through a field of zeros on the address lines and the highest + * memory location, which causes a '0' bit to walk through a field of + * '1's on the address line. + * + * o Floating buses can fool memory tests if the test routine writes + * a value and then reads it back immediately. The problem is, the + * write will charge the residual capacitance on the data bus so the + * bus retains its state briefely. When the test program reads the + * value back immediately, the capacitance of the bus can allow it + * to read back what was written, even though the memory circuitry + * is broken. To avoid this, the test program should write a test + * pattern to the target location, write a different pattern elsewhere + * to charge the residual capacitance in a differnt manner, then read + * the target location back. + * + * o Always read the target location EXACTLY ONCE and save it in a local + * variable. The problem with reading the target location more than + * once is that the second and subsequent reads may work properly, + * resulting in a failed test that tells the poor technician that + * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which + * doesn't help him one bit and causes puzzled phone calls. Been there, + * done that. + * + * Data line test: + * --------------- + * This tests data lines for shorts and opens by forcing adjacent data + * to opposite states. Because the data lines could be routed in an + * arbitrary manner the must ensure test patterns ensure that every case + * is tested. By using the following series of binary patterns every + * combination of adjacent bits is test regardless of routing. + * + * ...101010101010101010101010 + * ...110011001100110011001100 + * ...111100001111000011110000 + * ...111111110000000011111111 + * + * Carrying this out, gives us six hex patterns as follows: + * + * 0xaaaaaaaaaaaaaaaa + * 0xcccccccccccccccc + * 0xf0f0f0f0f0f0f0f0 + * 0xff00ff00ff00ff00 + * 0xffff0000ffff0000 + * 0xffffffff00000000 + * + * To test for short and opens to other signals on our boards, we + * simply test with the 1's complemnt of the paterns as well, resulting + * in twelve patterns total. + * + * After writing a test pattern. a special pattern 0x0123456789ABCDEF is + * written to a different address in case the data lines are floating. + * Thus, if a byte lane fails, you will see part of the special + * pattern in that byte lane when the test runs. For example, if the + * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa + * (for the 'a' test pattern). + * + * Address line test: + * ------------------ + * This function performs a test to verify that all the address lines + * hooked up to the RAM work properly. If there is an address line + * fault, it usually shows up as two different locations in the address + * map (related by the faulty address line) mapping to one physical + * memory storage location. The artifact that shows up is writing to + * the first location "changes" the second location. + * + * To test all address lines, we start with the given base address and + * xor the address with a '1' bit to flip one address line. For each + * test, we shift the '1' bit left to test the next address line. + * + * In the actual code, we start with address sizeof(ulong) since our + * test pattern we use is a ulong and thus, if we tried to test lower + * order address bits, it wouldn't work because our pattern would + * overwrite itself. + * + * Example for a 4 bit address space with the base at 0000: + * 0000 <- base + * 0001 <- test 1 + * 0010 <- test 2 + * 0100 <- test 3 + * 1000 <- test 4 + * Example for a 4 bit address space with the base at 0010: + * 0010 <- base + * 0011 <- test 1 + * 0000 <- (below the base address, skipped) + * 0110 <- test 2 + * 1010 <- test 3 + * + * The test locations are successively tested to make sure that they are + * not "mirrored" onto the base address due to a faulty address line. + * Note that the base and each test location are related by one address + * line flipped. Note that the base address need not be all zeros. + * + * Memory tests 1-4: + * ----------------- + * These tests verify RAM using sequential writes and reads + * to/from RAM. There are several test cases that use different patterns to + * verify RAM. Each test case fills a region of RAM with one pattern and + * then reads the region back and compares its contents with the pattern. + * The following patterns are used: + * + * 1a) zero pattern (0x00000000) + * 1b) negative pattern (0xffffffff) + * 1c) checkerboard pattern (0x55555555) + * 1d) checkerboard pattern (0xaaaaaaaa) + * 2) bit-flip pattern ((1 << (offset % 32)) + * 3) address pattern (offset) + * 4) address pattern (~offset) + * + * Being run in normal mode, the test verifies only small 4Kb + * regions of RAM around each 1Mb boundary. For example, for 64Mb + * RAM the following areas are verified: 0x00000000-0x00000800, + * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- + * 0x04000000. If the test is run in slow-test mode, it verifies + * the whole RAM. + */ + +#ifdef CONFIG_POST + +#include +#include + +#if CONFIG_POST & CFG_POST_MEMORY + +/* + * Define INJECT_*_ERRORS for testing error detection in the presence of + * _good_ hardware. + */ +#undef INJECT_DATA_ERRORS +#undef INJECT_ADDRESS_ERRORS + +#ifdef INJECT_DATA_ERRORS +#warning "Injecting data line errors for testing purposes" +#endif + +#ifdef INJECT_ADDRESS_ERRORS +#warning "Injecting address line errors for testing purposes" +#endif + + +/* + * This function performs a double word move from the data at + * the source pointer to the location at the destination pointer. + * This is helpful for testing memory on processors which have a 64 bit + * wide data bus. + * + * On those PowerPC with FPU, use assembly and a floating point move: + * this does a 64 bit move. + * + * For other processors, let the compiler generate the best code it can. + */ +static void move64(unsigned long long *src, unsigned long long *dest) +{ +#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) + asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : : "fr0" ); /* Clobbers fr0 */ + return; +#else + *dest = *src; +#endif +} + +/* + * This is 64 bit wide test patterns. Note that they reside in ROM + * (which presumably works) and the tests write them to RAM which may + * not work. + * + * The "otherpattern" is written to drive the data bus to values other + * than the test pattern. This is for detecting floating bus lines. + * + */ +const static unsigned long long pattern[] = { + 0xaaaaaaaaaaaaaaaaULL, + 0xccccccccccccccccULL, + 0xf0f0f0f0f0f0f0f0ULL, + 0xff00ff00ff00ff00ULL, + 0xffff0000ffff0000ULL, + 0xffffffff00000000ULL, + 0x00000000ffffffffULL, + 0x0000ffff0000ffffULL, + 0x00ff00ff00ff00ffULL, + 0x0f0f0f0f0f0f0f0fULL, + 0x3333333333333333ULL, + 0x5555555555555555ULL +}; +const unsigned long long otherpattern = 0x0123456789abcdefULL; + + +static int memory_post_dataline(unsigned long long * pmem) +{ + unsigned long long temp64 = 0; + int num_patterns = sizeof(pattern)/ sizeof(pattern[0]); + int i; + unsigned int hi, lo, pathi, patlo; + int ret = 0; + + for ( i = 0; i < num_patterns; i++) { + move64((unsigned long long *)&(pattern[i]), pmem++); + /* + * Put a different pattern on the data lines: otherwise they + * may float long enough to read back what we wrote. + */ + move64((unsigned long long *)&otherpattern, pmem--); + move64(pmem, &temp64); + +#ifdef INJECT_DATA_ERRORS + temp64 ^= 0x00008000; +#endif + + if (temp64 != pattern[i]){ + pathi = (pattern[i]>>32) & 0xffffffff; + patlo = pattern[i] & 0xffffffff; + + hi = (temp64>>32) & 0xffffffff; + lo = temp64 & 0xffffffff; + + post_log ("Memory (date line) error at %08x, " + "wrote %08x%08x, read %08x%08x !\n", + pmem, pathi, patlo, hi, lo); + ret = -1; + } + } + return ret; +} + +static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) +{ + ulong *target; + ulong *end; + ulong readback; + ulong xor; + int ret = 0; + + end = (ulong *)((ulong)base + size); /* pointer arith! */ + xor = 0; + for(xor = sizeof(ulong); xor > 0; xor <<= 1) { + target = (ulong *)((ulong)testaddr ^ xor); + if((target >= base) && (target < end)) { + *testaddr = ~*target; + readback = *target; + +#ifdef INJECT_ADDRESS_ERRORS + if(xor == 0x00008000) { + readback = *testaddr; + } +#endif + if(readback == *testaddr) { + post_log ("Memory (address line) error at %08x<->%08x, " + "XOR value %08x !\n", + testaddr, target, xor); + ret = -1; + } + } + } + return ret; +} + +static int memory_post_test1 (unsigned long start, + unsigned long size, + unsigned long val) +{ + unsigned long i; + ulong *mem = (ulong *) start; + ulong readback; + int ret = 0; + + for (i = 0; i < size / sizeof (ulong); i++) { + mem[i] = val; + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { + readback = mem[i]; + if (readback != val) { + post_log ("Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, val, readback); + + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + return ret; +} + +static int memory_post_test2 (unsigned long start, unsigned long size) +{ + unsigned long i; + ulong *mem = (ulong *) start; + ulong readback; + int ret = 0; + + for (i = 0; i < size / sizeof (ulong); i++) { + mem[i] = 1 << (i % 32); + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { + readback = mem[i]; + if (readback != (1 << (i % 32))) { + post_log ("Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, 1 << (i % 32), readback); + + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + return ret; +} + +static int memory_post_test3 (unsigned long start, unsigned long size) +{ + unsigned long i; + ulong *mem = (ulong *) start; + ulong readback; + int ret = 0; + + for (i = 0; i < size / sizeof (ulong); i++) { + mem[i] = i; + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { + readback = mem[i]; + if (readback != i) { + post_log ("Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, i, readback); + + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + return ret; +} + +static int memory_post_test4 (unsigned long start, unsigned long size) +{ + unsigned long i; + ulong *mem = (ulong *) start; + ulong readback; + int ret = 0; + + for (i = 0; i < size / sizeof (ulong); i++) { + mem[i] = ~i; + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { + readback = mem[i]; + if (readback != ~i) { + post_log ("Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, ~i, readback); + + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET (); + } + + return ret; +} + +static int memory_post_tests (unsigned long start, unsigned long size) +{ + int ret = 0; + + if (ret == 0) + ret = memory_post_dataline ((unsigned long long *)start); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_addrline ((ulong *)start, (ulong *)start, size); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_addrline ((ulong *)(start + size - 8), + (ulong *)start, size); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test1 (start, size, 0x00000000); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test1 (start, size, 0xffffffff); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test1 (start, size, 0x55555555); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test1 (start, size, 0xaaaaaaaa); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test2 (start, size); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test3 (start, size); + WATCHDOG_RESET (); + if (ret == 0) + ret = memory_post_test4 (start, size); + WATCHDOG_RESET (); + + return ret; +} + +int memory_post_test (int flags) +{ + int ret = 0; + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; + unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? + 256 << 20 : bd->bi_memsize) - (1 << 20); + + + if (flags & POST_SLOWTEST) { + ret = memory_post_tests (CFG_SDRAM_BASE, memsize); + } else { /* POST_NORMAL */ + + unsigned long i; + + for (i = 0; i < (memsize >> 20) && ret == 0; i++) { + if (ret == 0) + ret = memory_post_tests (i << 20, 0x800); + if (ret == 0) + ret = memory_post_tests ((i << 20) + 0xff800, 0x800); + } + } + + return ret; +} + +#endif /* CONFIG_POST & CFG_POST_MEMORY */ +#endif /* CONFIG_POST */ diff --git a/post/post.c b/post/post.c new file mode 100644 index 0000000..b3df91a --- /dev/null +++ b/post/post.c @@ -0,0 +1,443 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CONFIG_LOGBUFFER +#include +#endif + +#ifdef CONFIG_POST + +#define POST_MAX_NUMBER 32 + +#define BOOTMODE_MAGIC 0xDEAD0000 + +int post_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int res = 0; + unsigned int i; + + for (i = 0; i < post_list_size; i++) { + struct post_test *test = post_list + i; + + if (test->init_f && test->init_f()) { + res = -1; + } + } + + gd->post_init_f_time = post_time_ms(0); + if (!gd->post_init_f_time) + { + printf("post/post.c: post_time_ms seems not to be implemented\n"); + } + + return res; +} + +void post_bootmode_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + int bootmode = post_bootmode_get (0); + int newword; + + if (post_hotkeys_pressed() && !(bootmode & POST_POWERTEST)) { + newword = BOOTMODE_MAGIC | POST_SLOWTEST; + } else if (bootmode == 0) { + newword = BOOTMODE_MAGIC | POST_POWERON; + } else if (bootmode == POST_POWERON || bootmode == POST_SLOWTEST) { + newword = BOOTMODE_MAGIC | POST_NORMAL; + } else { + /* Use old value */ + newword = post_word_load () & ~POST_COLDBOOT; + } + + if (bootmode == 0) + { + /* We are booting after power-on */ + newword |= POST_COLDBOOT; + } + + post_word_store (newword); + + /* Reset activity record */ + gd->post_log_word = 0; +} + +int post_bootmode_get (unsigned int *last_test) +{ + unsigned long word = post_word_load (); + int bootmode; + + if ((word & 0xFFFF0000) != BOOTMODE_MAGIC) { + return 0; + } + + bootmode = word & 0x7F; + + if (last_test && (bootmode & POST_POWERTEST)) { + *last_test = (word >> 8) & 0xFF; + } + + return bootmode; +} + +/* POST tests run before relocation only mark status bits .... */ +static void post_log_mark_start ( unsigned long testid ) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->post_log_word |= (testid)<<16; +} + +static void post_log_mark_succ ( unsigned long testid ) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->post_log_word |= testid; +} + +/* ... and the messages are output once we are relocated */ +void post_output_backlog ( void ) +{ + DECLARE_GLOBAL_DATA_PTR; + int j; + + for (j = 0; j < post_list_size; j++) { + if (gd->post_log_word & (post_list[j].testid<<16)) { + post_log ("POST %s ", post_list[j].cmd); + if (gd->post_log_word & post_list[j].testid) + post_log ("PASSED\n"); + else { + post_log ("FAILED\n"); +#ifdef CONFIG_SHOW_BOOT_PROGRESS + show_boot_progress(-31); +#endif + } + } + } +} + +static void post_bootmode_test_on (unsigned int last_test) +{ + unsigned long word = post_word_load (); + + word |= POST_POWERTEST; + + word |= (last_test & 0xFF) << 8; + + post_word_store (word); +} + +static void post_bootmode_test_off (void) +{ + unsigned long word = post_word_load (); + + word &= ~POST_POWERTEST; + + post_word_store (word); +} + +static void post_get_flags (int *test_flags) +{ + int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST }; + char *var[] = { "post_poweron", "post_normal", "post_slowtest" }; + int varnum = sizeof (var) / sizeof (var[0]); + char list[128]; /* long enough for POST list */ + char *name; + char *s; + int last; + int i, j; + + for (j = 0; j < post_list_size; j++) { + test_flags[j] = post_list[j].flags; + } + + for (i = 0; i < varnum; i++) { + if (getenv_r (var[i], list, sizeof (list)) <= 0) + continue; + + for (j = 0; j < post_list_size; j++) { + test_flags[j] &= ~flag[i]; + } + + last = 0; + name = list; + while (!last) { + while (*name && *name == ' ') + name++; + if (*name == 0) + break; + s = name + 1; + while (*s && *s != ' ') + s++; + if (*s == 0) + last = 1; + else + *s = 0; + + for (j = 0; j < post_list_size; j++) { + if (strcmp (post_list[j].cmd, name) == 0) { + test_flags[j] |= flag[i]; + break; + } + } + + if (j == post_list_size) { + printf ("No such test: %s\n", name); + } + + name = s + 1; + } + } + + for (j = 0; j < post_list_size; j++) { + if (test_flags[j] & POST_POWERON) { + test_flags[j] |= POST_SLOWTEST; + } + } +} + +static int post_run_single (struct post_test *test, + int test_flags, int flags, unsigned int i) +{ + if ((flags & test_flags & POST_ALWAYS) && + (flags & test_flags & POST_MEM)) { + WATCHDOG_RESET (); + + if (!(flags & POST_REBOOT)) { + if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) { + post_bootmode_test_on (i); + } + + if (test_flags & POST_PREREL) + post_log_mark_start ( test->testid ); + else + post_log ("POST %s ", test->cmd); + } + + if (test_flags & POST_PREREL) { + if ((*test->test) (flags) == 0) + post_log_mark_succ ( test->testid ); + } else { + if ((*test->test) (flags) != 0) { + post_log ("FAILED\n"); +#ifdef CONFIG_SHOW_BOOT_PROGRESS + show_boot_progress(-32); +#endif + } + else + post_log ("PASSED\n"); + } + + if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) { + post_bootmode_test_off (); + } + + return 0; + } else { + return -1; + } +} + +int post_run (char *name, int flags) +{ + unsigned int i; + int test_flags[POST_MAX_NUMBER]; + + post_get_flags (test_flags); + + if (name == NULL) { + unsigned int last; + + if (post_bootmode_get (&last) & POST_POWERTEST) { + if (last < post_list_size && + (flags & test_flags[last] & POST_ALWAYS) && + (flags & test_flags[last] & POST_MEM)) { + + post_run_single (post_list + last, + test_flags[last], + flags | POST_REBOOT, last); + + for (i = last + 1; i < post_list_size; i++) { + post_run_single (post_list + i, + test_flags[i], + flags, i); + } + } + } else { + for (i = 0; i < post_list_size; i++) { + post_run_single (post_list + i, + test_flags[i], + flags, i); + } + } + + return 0; + } else { + for (i = 0; i < post_list_size; i++) { + if (strcmp (post_list[i].cmd, name) == 0) + break; + } + + if (i < post_list_size) { + return post_run_single (post_list + i, + test_flags[i], + flags, i); + } else { + return -1; + } + } +} + +static int post_info_single (struct post_test *test, int full) +{ + if (test->flags & POST_MANUAL) { + if (full) + printf ("%s - %s\n" + " %s\n", test->cmd, test->name, test->desc); + else + printf (" %-15s - %s\n", test->cmd, test->name); + + return 0; + } else { + return -1; + } +} + +int post_info (char *name) +{ + unsigned int i; + + if (name == NULL) { + for (i = 0; i < post_list_size; i++) { + post_info_single (post_list + i, 0); + } + + return 0; + } else { + for (i = 0; i < post_list_size; i++) { + if (strcmp (post_list[i].cmd, name) == 0) + break; + } + + if (i < post_list_size) { + return post_info_single (post_list + i, 1); + } else { + return -1; + } + } +} + +int post_log (char *format, ...) +{ + va_list args; + uint i; + char printbuffer[CFG_PBSIZE]; + + va_start (args, format); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vsprintf (printbuffer, format, args); + va_end (args); + +#ifdef CONFIG_LOGBUFFER + /* Send to the logbuffer */ + logbuff_log (printbuffer); +#else + /* Send to the stdout file */ + puts (printbuffer); +#endif + + return 0; +} + +void post_reloc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned int i; + + /* + * We have to relocate the test table manually + */ + for (i = 0; i < post_list_size; i++) { + ulong addr; + struct post_test *test = post_list + i; + + if (test->name) { + addr = (ulong) (test->name) + gd->reloc_off; + test->name = (char *) addr; + } + + if (test->cmd) { + addr = (ulong) (test->cmd) + gd->reloc_off; + test->cmd = (char *) addr; + } + + if (test->desc) { + addr = (ulong) (test->desc) + gd->reloc_off; + test->desc = (char *) addr; + } + + if (test->test) { + addr = (ulong) (test->test) + gd->reloc_off; + test->test = (int (*)(int flags)) addr; + } + + if (test->init_f) { + addr = (ulong) (test->init_f) + gd->reloc_off; + test->init_f = (int (*)(void)) addr; + } + + if (test->reloc) { + addr = (ulong) (test->reloc) + gd->reloc_off; + test->reloc = (void (*)(void)) addr; + + test->reloc(); + } + } +} + + +/* + * Some tests (e.g. SYSMON) need the time when post_init_f started, + * but we cannot use get_timer() at this point. + * + * On PowerPC we implement it using the timebase register. + */ +unsigned long post_time_ms (unsigned long base) +{ +#ifdef CONFIG_PPC + return (unsigned long)get_ticks () / (get_tbclk () / CFG_HZ) - base; +#else + return 0; /* Not implemented yet */ +#endif +} + +#endif /* CONFIG_POST */ diff --git a/post/rtc.c b/post/rtc.c new file mode 100644 index 0000000..7d4f9b8 --- /dev/null +++ b/post/rtc.c @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * RTC test + * + * The Real Time Clock (RTC) operation is verified by this test. + * The following features are verified: + * o) Time uniformity + * This is verified by reading RTC in polling within + * a short period of time. + * o) Passing month boundaries + * This is checked by setting RTC to a second before + * a month boundary and reading it after its passing the + * boundary. The test is performed for both leap- and + * nonleap-years. + */ + +#ifdef CONFIG_POST + +#include +#include + +#if CONFIG_POST & CFG_POST_RTC + +static int rtc_post_skip (ulong * diff) +{ + struct rtc_time tm1; + struct rtc_time tm2; + ulong start1; + ulong start2; + + rtc_get (&tm1); + start1 = get_timer (0); + + while (1) { + rtc_get (&tm2); + start2 = get_timer (0); + if (tm1.tm_sec != tm2.tm_sec) + break; + if (start2 - start1 > 1500) + break; + } + + if (tm1.tm_sec != tm2.tm_sec) { + *diff = start2 - start1; + + return 0; + } else { + return -1; + } +} + +static void rtc_post_restore (struct rtc_time *tm, unsigned int sec) +{ + time_t t = mktime (tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, + tm->tm_min, tm->tm_sec) + sec; + struct rtc_time ntm; + + to_tm (t, &ntm); + + rtc_set (&ntm); +} + +int rtc_post_test (int flags) +{ + ulong diff; + unsigned int i; + struct rtc_time svtm; + static unsigned int daysnl[] = + { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + static unsigned int daysl[] = + { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + unsigned int ynl = 1999; + unsigned int yl = 2000; + unsigned int skipped = 0; + + /* Time uniformity */ + if (rtc_post_skip (&diff) != 0) { + post_log ("Timeout while waiting for a new second !\n"); + + return -1; + } + + for (i = 0; i < 5; i++) { + if (rtc_post_skip (&diff) != 0) { + post_log ("Timeout while waiting for a new second !\n"); + + return -1; + } + + if (diff < 950 || diff > 1050) { + post_log ("Invalid second duration !\n"); + + return -1; + } + } + + /* Passing month boundaries */ + + if (rtc_post_skip (&diff) != 0) { + post_log ("Timeout while waiting for a new second !\n"); + + return -1; + } + rtc_get (&svtm); + + for (i = 0; i < 12; i++) { + time_t t = mktime (ynl, i + 1, daysnl[i], 23, 59, 59); + struct rtc_time tm; + + to_tm (t, &tm); + rtc_set (&tm); + + skipped++; + if (rtc_post_skip (&diff) != 0) { + rtc_post_restore (&svtm, skipped); + post_log ("Timeout while waiting for a new second !\n"); + + return -1; + } + + rtc_get (&tm); + if (tm.tm_mon == i + 1) { + rtc_post_restore (&svtm, skipped); + post_log ("Month %d boundary is not passed !\n", i + 1); + + return -1; + } + } + + for (i = 0; i < 12; i++) { + time_t t = mktime (yl, i + 1, daysl[i], 23, 59, 59); + struct rtc_time tm; + + to_tm (t, &tm); + rtc_set (&tm); + + skipped++; + if (rtc_post_skip (&diff) != 0) { + rtc_post_restore (&svtm, skipped); + post_log ("Timeout while waiting for a new second !\n"); + + return -1; + } + + rtc_get (&tm); + if (tm.tm_mon == i + 1) { + rtc_post_restore (&svtm, skipped); + post_log ("Month %d boundary is not passed !\n", i + 1); + + return -1; + } + } + rtc_post_restore (&svtm, skipped); + + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_RTC */ +#endif /* CONFIG_POST */ diff --git a/post/rules.mk b/post/rules.mk new file mode 100644 index 0000000..1ad6959 --- /dev/null +++ b/post/rules.mk @@ -0,0 +1,42 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +OBJS = $(AOBJS) $(COBJS) + +CPPFLAGS += -I$(TOPDIR) + +all: $(LIB) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > .depend + +sinclude .depend + +######################################################################### diff --git a/post/spr.c b/post/spr.c new file mode 100644 index 0000000..330b977 --- /dev/null +++ b/post/spr.c @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * SPR test + * + * The test checks the contents of Special Purpose Registers (SPR) listed + * in the spr_test_list array below. + * Each SPR value is read using mfspr instruction, some bits are masked + * according to the table and the resulting value is compared to the + * corresponding table value. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_SPR + +static struct +{ + int number; + char * name; + unsigned long mask; + unsigned long value; +} spr_test_list [] = { + /* Standard Special-Purpose Registers */ + + {1, "XER", 0x00000000, 0x00000000}, + {8, "LR", 0x00000000, 0x00000000}, + {9, "CTR", 0x00000000, 0x00000000}, + {18, "DSISR", 0x00000000, 0x00000000}, + {19, "DAR", 0x00000000, 0x00000000}, + {22, "DEC", 0x00000000, 0x00000000}, + {26, "SRR0", 0x00000000, 0x00000000}, + {27, "SRR1", 0x00000000, 0x00000000}, + {272, "SPRG0", 0x00000000, 0x00000000}, + {273, "SPRG1", 0x00000000, 0x00000000}, + {274, "SPRG2", 0x00000000, 0x00000000}, + {275, "SPRG3", 0x00000000, 0x00000000}, + {287, "PVR", 0xFFFF0000, 0x00500000}, + + /* Additional Special-Purpose Registers */ + + {144, "CMPA", 0x00000000, 0x00000000}, + {145, "CMPB", 0x00000000, 0x00000000}, + {146, "CMPC", 0x00000000, 0x00000000}, + {147, "CMPD", 0x00000000, 0x00000000}, + {148, "ICR", 0xFFFFFFFF, 0x00000000}, + {149, "DER", 0x00000000, 0x00000000}, + {150, "COUNTA", 0xFFFFFFFF, 0x00000000}, + {151, "COUNTB", 0xFFFFFFFF, 0x00000000}, + {152, "CMPE", 0x00000000, 0x00000000}, + {153, "CMPF", 0x00000000, 0x00000000}, + {154, "CMPG", 0x00000000, 0x00000000}, + {155, "CMPH", 0x00000000, 0x00000000}, + {156, "LCTRL1", 0xFFFFFFFF, 0x00000000}, + {157, "LCTRL2", 0xFFFFFFFF, 0x00000000}, + {158, "ICTRL", 0xFFFFFFFF, 0x00000007}, + {159, "BAR", 0x00000000, 0x00000000}, + {630, "DPDR", 0x00000000, 0x00000000}, + {631, "DPIR", 0x00000000, 0x00000000}, + {638, "IMMR", 0xFFFF0000, CFG_IMMR }, + {560, "IC_CST", 0x8E380000, 0x00000000}, + {561, "IC_ADR", 0x00000000, 0x00000000}, + {562, "IC_DAT", 0x00000000, 0x00000000}, + {568, "DC_CST", 0xEF380000, 0x00000000}, + {569, "DC_ADR", 0x00000000, 0x00000000}, + {570, "DC_DAT", 0x00000000, 0x00000000}, + {784, "MI_CTR", 0xFFFFFFFF, 0x00000000}, + {786, "MI_AP", 0x00000000, 0x00000000}, + {787, "MI_EPN", 0x00000000, 0x00000000}, + {789, "MI_TWC", 0xFFFFFE02, 0x00000000}, + {790, "MI_RPN", 0x00000000, 0x00000000}, + {816, "MI_DBCAM", 0x00000000, 0x00000000}, + {817, "MI_DBRAM0", 0x00000000, 0x00000000}, + {818, "MI_DBRAM1", 0x00000000, 0x00000000}, + {792, "MD_CTR", 0xFFFFFFFF, 0x04000000}, + {793, "M_CASID", 0xFFFFFFF0, 0x00000000}, + {794, "MD_AP", 0x00000000, 0x00000000}, + {795, "MD_EPN", 0x00000000, 0x00000000}, + {796, "M_TWB", 0x00000003, 0x00000000}, + {797, "MD_TWC", 0x00000003, 0x00000000}, + {798, "MD_RPN", 0x00000000, 0x00000000}, + {799, "M_TW", 0x00000000, 0x00000000}, + {824, "MD_DBCAM", 0x00000000, 0x00000000}, + {825, "MD_DBRAM0", 0x00000000, 0x00000000}, + {826, "MD_DBRAM1", 0x00000000, 0x00000000}, +}; + +static int spr_test_list_size = + sizeof (spr_test_list) / sizeof (spr_test_list[0]); + +int spr_post_test (int flags) +{ + int ret = 0; + int ic = icache_status (); + int i; + + unsigned long code[] = { + 0x7c6002a6, /* mfspr r3,SPR */ + 0x4e800020 /* blr */ + }; + unsigned long (*get_spr) (void) = (void *) code; + + if (ic) + icache_disable (); + + for (i = 0; i < spr_test_list_size; i++) { + int num = spr_test_list[i].number; + + /* mfspr r3,num */ + code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6); + + if ((get_spr () & spr_test_list[i].mask) != + (spr_test_list[i].value & spr_test_list[i].mask)) { + post_log ("The value of %s special register " + "is incorrect: 0x%08X\n", + spr_test_list[i].name, get_spr ()); + ret = -1; + } + } + + if (ic) + icache_enable (); + + return ret; +} +#endif /* CONFIG_POST & CFG_POST_SPR */ +#endif /* CONFIG_POST */ diff --git a/post/sysmon.c b/post/sysmon.c new file mode 100644 index 0000000..72fcac3 --- /dev/null +++ b/post/sysmon.c @@ -0,0 +1,333 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_POST + +/* + * SYSMON test + * + * This test performs the system hardware monitoring. + * The test passes when all the following voltages and temperatures + * are within allowed ranges: + * + * Board temperature + * Front temperature + * +3.3V CPU logic + * +5V logic + * +12V PCMCIA + * +12V CCFL + * +5V standby + * + * CCFL is not enabled if temperature values are not within allowed ranges + * + * See the list off all parameters in the sysmon_table below + */ + +#include +#include +#include + +#if CONFIG_POST & CFG_POST_SYSMON + +static int sysmon_temp_invalid = 0; + +/* #define DEBUG */ + +#define RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off) + +typedef struct sysmon_s sysmon_t; +typedef struct sysmon_table_s sysmon_table_t; + +static void sysmon_lm87_init (sysmon_t * this); +static void sysmon_pic_init (sysmon_t * this); +static uint sysmon_i2c_read (sysmon_t * this, uint addr); +static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr); +static void sysmon_ccfl_disable (sysmon_table_t * this); +static void sysmon_ccfl_enable (sysmon_table_t * this); + +struct sysmon_s +{ + uchar chip; + void (*init)(sysmon_t *); + uint (*read)(sysmon_t *, uint); +}; + +static sysmon_t sysmon_lm87 = + {CFG_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read}; +static sysmon_t sysmon_lm87_sgn = + {CFG_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read_sgn}; +static sysmon_t sysmon_pic = + {CFG_I2C_PICIO_ADDR, sysmon_pic_init, sysmon_i2c_read}; + +static sysmon_t * sysmon_list[] = +{ + &sysmon_lm87, + &sysmon_lm87_sgn, + &sysmon_pic, + NULL +}; + +struct sysmon_table_s +{ + char * name; + char * unit_name; + sysmon_t * sysmon; + void (*exec_before)(sysmon_table_t *); + void (*exec_after)(sysmon_table_t *); + + int unit_precision; + int unit_div; + int unit_min; + int unit_max; + uint val_mask; + uint val_min; + uint val_max; + int val_valid; + uint val_min_alt; + uint val_max_alt; + int val_valid_alt; + uint addr; +}; + +static sysmon_table_t sysmon_table[] = +{ + {"Board temperature", " C", &sysmon_lm87_sgn, NULL, sysmon_ccfl_disable, + 1, 1, -128, 127, 0xFF, 0x58, 0xD5, 0, 0x6C, 0xC6, 0, 0x27}, + + {"Front temperature", " C", &sysmon_lm87, NULL, sysmon_ccfl_disable, + 1, 100, -27316, 8984, 0xFF, 0xA4, 0xFC, 0, 0xB2, 0xF1, 0, 0x29}, + + {"+3.3V CPU logic", "V", &sysmon_lm87, NULL, NULL, + 100, 1000, 0, 4386, 0xFF, 0xB6, 0xC9, 0, 0xB6, 0xC9, 0, 0x22}, + + {"+ 5 V logic", "V", &sysmon_lm87, NULL, NULL, + 100, 1000, 0, 6630, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x23}, + + {"+12 V PCMCIA", "V", &sysmon_lm87, NULL, NULL, + 100, 1000, 0, 15460, 0xFF, 0xBC, 0xD0, 0, 0xBC, 0xD0, 0, 0x21}, + + {"+12 V CCFL", "V", &sysmon_lm87, NULL, sysmon_ccfl_enable, + 100, 1000, 0, 15900, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x24}, + + {"+ 5 V standby", "V", &sysmon_pic, NULL, NULL, + 100, 1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0xC8, 0xDE, 0, 0x7C}, +}; +static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]); + +static int conversion_done = 0; + + +int sysmon_init_f (void) +{ + sysmon_t ** l; + ulong reg; + + /* Power on CCFL, PCMCIA */ + reg = pic_read (0x60); + reg |= 0x09; + pic_write (0x60, reg); + + for (l = sysmon_list; *l; l++) { + (*l)->init(*l); + } + + return 0; +} + +void sysmon_reloc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + sysmon_t ** l; + sysmon_table_t * t; + + for (l = sysmon_list; *l; l++) { + RELOC(*l); + RELOC((*l)->init); + RELOC((*l)->read); + } + + for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { + RELOC(t->exec_before); + RELOC(t->exec_after); + RELOC(t->sysmon); + } +} + +static char *sysmon_unit_value (sysmon_table_t *s, uint val) +{ + static char buf[32]; + int unit_val = + s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask; + char *p, sign; + int dec, frac; + + if (val == -1) { + return "I/O ERROR"; + } + + if (unit_val < 0) { + sign = '-'; + unit_val = -unit_val; + } else { + sign = '+'; + } + + p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div); + + + frac = unit_val % s->unit_div; + + frac /= (s->unit_div / s->unit_precision); + + dec = s->unit_precision; + + if (dec != 1) { + *p++ = '.'; + } + for (dec /= 10; dec != 0; dec /= 10) { + *p++ = '0' + (frac / dec) % 10; + } + strcpy(p, s->unit_name); + + return buf; +} + +static void sysmon_lm87_init (sysmon_t * this) +{ + uchar val; + + /* Detect LM87 chip */ + if (i2c_read(this->chip, 0x40, 1, &val, 1) || (val & 0x80) != 0 || + i2c_read(this->chip, 0x3E, 1, &val, 1) || val != 0x02) { + printf("Error: LM87 not found at 0x%02X\n", this->chip); + return; + } + + /* Configure pins 5,6 as AIN */ + val = 0x03; + if (i2c_write(this->chip, 0x16, 1, &val, 1)) { + printf("Error: can't write LM87 config register\n"); + return; + } + + /* Start monitoring */ + val = 0x01; + if (i2c_write(this->chip, 0x40, 1, &val, 1)) { + printf("Error: can't write LM87 config register\n"); + return; + } +} + +static void sysmon_pic_init (sysmon_t * this) +{ +} + +static uint sysmon_i2c_read (sysmon_t * this, uint addr) +{ + uchar val; + uint res = i2c_read(this->chip, addr, 1, &val, 1); + + return res == 0 ? val : -1; +} + +static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr) +{ + uchar val; + return i2c_read(this->chip, addr, 1, &val, 1) == 0 ? + 128 + (signed char)val : -1; +} + +static void sysmon_ccfl_disable (sysmon_table_t * this) +{ + if (!this->val_valid_alt) { + sysmon_temp_invalid = 1; + } +} + +static void sysmon_ccfl_enable (sysmon_table_t * this) +{ + ulong reg; + + if (!sysmon_temp_invalid) { + reg = pic_read (0x60); + reg |= 0x06; + pic_write (0x60, reg); + } +} + +int sysmon_post_test (int flags) +{ + DECLARE_GLOBAL_DATA_PTR; + + int res = 0; + sysmon_table_t * t; + uint val; + + /* + * The A/D conversion on the LM87 sensor takes 300 ms. + */ + if (! conversion_done) { + while (post_time_ms(gd->post_init_f_time) < 300) WATCHDOG_RESET (); + conversion_done = 1; + } + + for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { + if (t->exec_before) { + t->exec_before(t); + } + + val = t->sysmon->read(t->sysmon, t->addr); + if (val != -1) { + t->val_valid = val >= t->val_min && val <= t->val_max; + t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt; + } else { + t->val_valid = 0; + t->val_valid_alt = 0; + } + + if (t->exec_after) { + t->exec_after(t); + } + + if ((!t->val_valid) || (flags & POST_MANUAL)) { + printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val)); + printf("allowed range"); + printf(" %-8s ..", sysmon_unit_value(t, t->val_min)); + printf(" %-8s", sysmon_unit_value(t, t->val_max)); + printf(" %s\n", t->val_valid ? "OK" : "FAIL"); + } + + if (!t->val_valid) { + res = -1; + } + } + + return res; +} + +#endif /* CONFIG_POST & CFG_POST_SYSMON */ +#endif /* CONFIG_POST */ diff --git a/post/tests.c b/post/tests.c new file mode 100644 index 0000000..3bccd1a --- /dev/null +++ b/post/tests.c @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Be sure to mark tests to be run before relocation as such with the + * CFG_POST_PREREL flag so that logging is done correctly if the + * logbuffer support is enabled. + */ + +#include + +#ifdef CONFIG_POST + +#include + +extern int cache_post_test (int flags); +extern int watchdog_post_test (int flags); +extern int i2c_post_test (int flags); +extern int rtc_post_test (int flags); +extern int memory_post_test (int flags); +extern int cpu_post_test (int flags); +extern int uart_post_test (int flags); +extern int ether_post_test (int flags); +extern int spi_post_test (int flags); +extern int usb_post_test (int flags); +extern int spr_post_test (int flags); +extern int sysmon_post_test (int flags); +extern int dsp_post_test (int flags); +extern int codec_post_test (int flags); + +extern int sysmon_init_f (void); + +extern void sysmon_reloc (void); + + +struct post_test post_list[] = +{ +#if CONFIG_POST & CFG_POST_CACHE + { + "Cache test", + "cache", + "This test verifies the CPU cache operation.", + POST_RAM | POST_ALWAYS, + &cache_post_test, + NULL, + NULL, + CFG_POST_CACHE + }, +#endif +#if CONFIG_POST & CFG_POST_WATCHDOG + { + "Watchdog timer test", + "watchdog", + "This test checks the watchdog timer.", + POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, + &watchdog_post_test, + NULL, + NULL, + CFG_POST_WATCHDOG + }, +#endif +#if CONFIG_POST & CFG_POST_I2C + { + "I2C test", + "i2c", + "This test verifies the I2C operation.", + POST_RAM | POST_ALWAYS, + &i2c_post_test, + NULL, + NULL, + CFG_POST_I2C + }, +#endif +#if CONFIG_POST & CFG_POST_RTC + { + "RTC test", + "rtc", + "This test verifies the RTC operation.", + POST_RAM | POST_SLOWTEST | POST_MANUAL, + &rtc_post_test, + NULL, + NULL, + CFG_POST_RTC + }, +#endif +#if CONFIG_POST & CFG_POST_MEMORY + { + "Memory test", + "memory", + "This test checks RAM.", + POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL, + &memory_post_test, + NULL, + NULL, + CFG_POST_MEMORY + }, +#endif +#if CONFIG_POST & CFG_POST_CPU + { + "CPU test", + "cpu", + "This test verifies the arithmetic logic unit of" + " CPU.", + POST_RAM | POST_ALWAYS, + &cpu_post_test, + NULL, + NULL, + CFG_POST_CPU + }, +#endif +#if CONFIG_POST & CFG_POST_UART + { + "UART test", + "uart", + "This test verifies the UART operation.", + POST_RAM | POST_SLOWTEST | POST_MANUAL, + &uart_post_test, + NULL, + NULL, + CFG_POST_UART + }, +#endif +#if CONFIG_POST & CFG_POST_ETHER + { + "ETHERNET test", + "ethernet", + "This test verifies the ETHERNET operation.", + POST_RAM | POST_ALWAYS | POST_MANUAL, + ðer_post_test, + NULL, + NULL, + CFG_POST_ETHER + }, +#endif +#if CONFIG_POST & CFG_POST_SPI + { + "SPI test", + "spi", + "This test verifies the SPI operation.", + POST_RAM | POST_ALWAYS | POST_MANUAL, + &spi_post_test, + NULL, + NULL, + CFG_POST_SPI + }, +#endif +#if CONFIG_POST & CFG_POST_USB + { + "USB test", + "usb", + "This test verifies the USB operation.", + POST_RAM | POST_ALWAYS | POST_MANUAL, + &usb_post_test, + NULL, + NULL, + CFG_POST_USB + }, +#endif +#if CONFIG_POST & CFG_POST_SPR + { + "SPR test", + "spr", + "This test checks SPR contents.", + POST_ROM | POST_ALWAYS | POST_PREREL, + &spr_post_test, + NULL, + NULL, + CFG_POST_SPR + }, +#endif +#if CONFIG_POST & CFG_POST_SYSMON + { + "SYSMON test", + "sysmon", + "This test monitors system hardware.", + POST_RAM | POST_ALWAYS, + &sysmon_post_test, + &sysmon_init_f, + &sysmon_reloc, + CFG_POST_SYSMON + }, +#endif +#if CONFIG_POST & CFG_POST_DSP + { + "DSP test", + "dsp", + "This test checks any connected DSP(s).", + POST_RAM | POST_MANUAL, + &dsp_post_test, + NULL, + NULL, + CFG_POST_DSP + }, +#endif +#if CONFIG_POST & CFG_POST_DSP + { + "CODEC test", + "codec", + "This test checks any connected codec(s).", + POST_RAM | POST_MANUAL, + &codec_post_test, + NULL, + NULL, + CFG_POST_CODEC + }, +#endif +}; + +unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test); + +#endif /* CONFIG_POST */ diff --git a/post/uart.c b/post/uart.c new file mode 100644 index 0000000..23bf036 --- /dev/null +++ b/post/uart.c @@ -0,0 +1,562 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * UART test + * + * The Serial Management Controllers (SMC) and the Serial Communication + * Controllers (SCC) listed in ctlr_list array below are tested in + * the loopback UART mode. + * The controllers are configured accordingly and several characters + * are transmitted. The configurable test parameters are: + * MIN_PACKET_LENGTH - minimum size of packet to transmit + * MAX_PACKET_LENGTH - maximum size of packet to transmit + * TEST_NUM - number of tests + */ + +#ifdef CONFIG_POST + +#include +#if CONFIG_POST & CFG_POST_UART +#if defined(CONFIG_8xx) +#include +#elif defined(CONFIG_MPC8260) +#include +#else +#error "Apparently a bad configuration, please fix." +#endif +#include +#include + +#define CTLR_SMC 0 +#define CTLR_SCC 1 + +/* The list of controllers to test */ +#if defined(CONFIG_MPC823) +static int ctlr_list[][2] = + { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} }; +#else +static int ctlr_list[][2] = { }; +#endif + +#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0])) + +static struct { + void (*init) (int index); + void (*halt) (int index); + void (*putc) (int index, const char c); + int (*getc) (int index); +} ctlr_proc[2]; + +static char *ctlr_name[2] = { "SMC", "SCC" }; + +static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 }; +static int proff_scc[] = + { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 }; + +/* + * SMC callbacks + */ + +static void smc_init (int smc_index) +{ + DECLARE_GLOBAL_DATA_PTR; + + static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 }; + + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile smc_t *sp; + volatile smc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile cpm8xx_t *cp = &(im->im_cpm); + uint dpaddr; + + /* initialize pointers to SMC */ + + sp = (smc_t *) & (cp->cp_smc[smc_index]); + up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]]; + + /* Disable transmitter/receiver. + */ + sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); + + /* Enable SDMA. + */ + im->im_siu_conf.sc_sdcr = 1; + + /* clear error conditions */ +#ifdef CFG_SDSR + im->im_sdma.sdma_sdsr = CFG_SDSR; +#else + im->im_sdma.sdma_sdsr = 0x83; +#endif + + /* clear SDMA interrupt mask */ +#ifdef CFG_SDMR + im->im_sdma.sdma_sdmr = CFG_SDMR; +#else + im->im_sdma.sdma_sdmr = 0x00; +#endif + +#if defined(CONFIG_FADS) + /* Enable RS232 */ + *((uint *) BCSR1) &= + ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2); +#endif + +#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) + /* Enable Monitor Port Transceiver */ + *((uchar *) BCSR0) |= BCSR0_ENMONXCVR; +#endif + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + +#ifdef CFG_ALLOC_DPRAM + dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8); +#else + dpaddr = CPM_POST_BASE; +#endif + + /* Allocate space for two buffer descriptors in the DP ram. + * For now, this address seems OK, but it may have to + * change with newer versions of the firmware. + * damm: allocating space after the two buffers for rx/tx data + */ + + rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr]; + rbdf->cbd_bufaddr = (uint) (rbdf + 2); + rbdf->cbd_sc = 0; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1; + tbdf->cbd_sc = 0; + + /* Set up the uart parameters in the parameter ram. + */ + up->smc_rbase = dpaddr; + up->smc_tbase = dpaddr + sizeof (cbd_t); + up->smc_rfcr = SMC_EB; + up->smc_tfcr = SMC_EB; + +#if defined(CONFIG_MBX) + board_serial_init (); +#endif + + /* Set UART mode, 8 bit, no parity, one stop. + * Enable receive and transmit. + * Set local loopback mode. + */ + sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004; + + /* Mask all interrupts and remove anything pending. + */ + sp->smc_smcm = 0; + sp->smc_smce = 0xff; + + /* Set up the baud rate generator. + */ + cp->cp_simode = 0x00000000; + + cp->cp_brgc1 = + (((gd->cpu_clk / 16 / gd->baudrate) - + 1) << 1) | CPM_BRG_EN; + + /* Make the first buffer the only buffer. + */ + tbdf->cbd_sc |= BD_SC_WRAP; + rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + + /* Single character receive. + */ + up->smc_mrblr = 1; + up->smc_maxidl = 0; + + /* Initialize Tx/Rx parameters. + */ + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cp_cpcr = + mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. + */ + sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; +} + +static void smc_halt(int smc_index) +{ +} + +static void smc_putc (int smc_index, const char c) +{ + volatile cbd_t *tbdf; + volatile char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + + up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]]; + + tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase]; + + /* Wait for last character to go. + */ + + buf = (char *) tbdf->cbd_bufaddr; +#if 0 + __asm__ ("eieio"); + while (tbdf->cbd_sc & BD_SC_READY) + __asm__ ("eieio"); +#endif + + *buf = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; + __asm__ ("eieio"); +#if 1 + while (tbdf->cbd_sc & BD_SC_READY) + __asm__ ("eieio"); +#endif +} + +static int smc_getc (int smc_index) +{ + volatile cbd_t *rbdf; + volatile unsigned char *buf; + volatile smc_uart_t *up; + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + unsigned char c; + int i; + + up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]]; + + rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase]; + + /* Wait for character to show up. + */ + buf = (unsigned char *) rbdf->cbd_bufaddr; +#if 0 + while (rbdf->cbd_sc & BD_SC_EMPTY); +#else + for (i = 100; i > 0; i--) { + if (!(rbdf->cbd_sc & BD_SC_EMPTY)) + break; + udelay (1000); + } + + if (i == 0) + return -1; +#endif + c = *buf; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return (c); +} + + /* + * SCC callbacks + */ + +static void scc_init (int scc_index) +{ + DECLARE_GLOBAL_DATA_PTR; + + static int cpm_cr_ch[] = { + CPM_CR_CH_SCC1, + CPM_CR_CH_SCC2, + CPM_CR_CH_SCC3, + CPM_CR_CH_SCC4, + }; + + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile scc_t *sp; + volatile scc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile cpm8xx_t *cp = &(im->im_cpm); + uint dpaddr; + + /* initialize pointers to SCC */ + + sp = (scc_t *) & (cp->cp_scc[scc_index]); + up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]]; + + /* Disable transmitter/receiver. + */ + sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + + /* Allocate space for two buffer descriptors in the DP ram. + */ + +#ifdef CFG_ALLOC_DPRAM + dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8); +#else + dpaddr = CPM_POST_BASE; +#endif + + /* Enable SDMA. + */ + im->im_siu_conf.sc_sdcr = 0x0001; + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + + rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr]; + rbdf->cbd_bufaddr = (uint) (rbdf + 2); + rbdf->cbd_sc = 0; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1; + tbdf->cbd_sc = 0; + + /* Set up the baud rate generator. + */ + cp->cp_sicr &= ~(0x000000FF << (8 * scc_index)); + /* no |= needed, since BRG1 is 000 */ + + cp->cp_brgc1 = + (((gd->cpu_clk / 16 / gd->baudrate) - + 1) << 1) | CPM_BRG_EN; + + /* Set up the uart parameters in the parameter ram. + */ + up->scc_genscc.scc_rbase = dpaddr; + up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t); + + /* Initialize Tx/Rx parameters. + */ + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + cp->cp_cpcr = + mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + up->scc_genscc.scc_rfcr = SCC_EB | 0x05; + up->scc_genscc.scc_tfcr = SCC_EB | 0x05; + + up->scc_genscc.scc_mrblr = 1; /* Single character receive */ + up->scc_maxidl = 0; /* disable max idle */ + up->scc_brkcr = 1; /* send one break character on stop TX */ + up->scc_parec = 0; + up->scc_frmec = 0; + up->scc_nosec = 0; + up->scc_brkec = 0; + up->scc_uaddr1 = 0; + up->scc_uaddr2 = 0; + up->scc_toseq = 0; + up->scc_char1 = 0x8000; + up->scc_char2 = 0x8000; + up->scc_char3 = 0x8000; + up->scc_char4 = 0x8000; + up->scc_char5 = 0x8000; + up->scc_char6 = 0x8000; + up->scc_char7 = 0x8000; + up->scc_char8 = 0x8000; + up->scc_rccm = 0xc0ff; + + /* Set low latency / small fifo. + */ + sp->scc_gsmrh = SCC_GSMRH_RFW; + + /* Set UART mode + */ + sp->scc_gsmrl &= ~0xF; + sp->scc_gsmrl |= SCC_GSMRL_MODE_UART; + + /* Set local loopback mode. + */ + sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE; + sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP; + + /* Set clock divider 16 on Tx and Rx + */ + sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); + + sp->scc_psmr |= SCU_PSMR_CL; + + /* Mask all interrupts and remove anything pending. + */ + sp->scc_sccm = 0; + sp->scc_scce = 0xffff; + sp->scc_dsr = 0x7e7e; + sp->scc_psmr = 0x3000; + + /* Make the first buffer the only buffer. + */ + tbdf->cbd_sc |= BD_SC_WRAP; + rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + + /* Enable transmitter/receiver. + */ + sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); +} + +static void scc_halt(int scc_index) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]); + + sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE); +} + +static void scc_putc (int scc_index, const char c) +{ + volatile cbd_t *tbdf; + volatile char *buf; + volatile scc_uart_t *up; + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + + up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]]; + + tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; + + /* Wait for last character to go. + */ + + buf = (char *) tbdf->cbd_bufaddr; +#if 0 + __asm__ ("eieio"); + while (tbdf->cbd_sc & BD_SC_READY) + __asm__ ("eieio"); +#endif + + *buf = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; + __asm__ ("eieio"); +#if 1 + while (tbdf->cbd_sc & BD_SC_READY) + __asm__ ("eieio"); +#endif +} + +static int scc_getc (int scc_index) +{ + volatile cbd_t *rbdf; + volatile unsigned char *buf; + volatile scc_uart_t *up; + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cpmp = &(im->im_cpm); + unsigned char c; + int i; + + up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]]; + + rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; + + /* Wait for character to show up. + */ + buf = (unsigned char *) rbdf->cbd_bufaddr; +#if 0 + while (rbdf->cbd_sc & BD_SC_EMPTY); +#else + for (i = 100; i > 0; i--) { + if (!(rbdf->cbd_sc & BD_SC_EMPTY)) + break; + udelay (1000); + } + + if (i == 0) + return -1; +#endif + c = *buf; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return (c); +} + + /* + * Test routines + */ + +static int test_ctlr (int ctlr, int index) +{ + int res = -1; + char test_str[] = "*** UART Test String ***\r\n"; + int i; + + ctlr_proc[ctlr].init (index); + + for (i = 0; i < sizeof (test_str) - 1; i++) { + ctlr_proc[ctlr].putc (index, test_str[i]); + if (ctlr_proc[ctlr].getc (index) != test_str[i]) + goto Done; + } + + res = 0; + +Done: + ctlr_proc[ctlr].halt (index); + + if (res != 0) { + post_log ("uart %s%d test failed\n", + ctlr_name[ctlr], index + 1); + } + + return res; +} + +int uart_post_test (int flags) +{ + int res = 0; + int i; + + ctlr_proc[CTLR_SMC].init = smc_init; + ctlr_proc[CTLR_SMC].halt = smc_halt; + ctlr_proc[CTLR_SMC].putc = smc_putc; + ctlr_proc[CTLR_SMC].getc = smc_getc; + + ctlr_proc[CTLR_SCC].init = scc_init; + ctlr_proc[CTLR_SCC].halt = scc_halt; + ctlr_proc[CTLR_SCC].putc = scc_putc; + ctlr_proc[CTLR_SCC].getc = scc_getc; + + for (i = 0; i < CTRL_LIST_SIZE; i++) { + if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { + res = -1; + } + } + +#if !defined(CONFIG_8xx_CONS_NONE) + serial_reinit_all (); +#endif + + return res; +} + +#endif /* CONFIG_POST & CFG_POST_UART */ + +#endif /* CONFIG_POST */ diff --git a/post/usb.c b/post/usb.c new file mode 100644 index 0000000..0c74cfa --- /dev/null +++ b/post/usb.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * USB test + * + * The USB controller is tested in the local loopback mode. + * It is configured so that endpoint 0 operates as host and endpoint 1 + * operates as function endpoint. After that an IN token transaction + * is performed. + * Refer to MPC850 User Manual, Section 32.11.1 USB Host Controller + * Initialization Example. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_USB + +#include +#include + +#define TOUT_LOOP 100 + +#define PROFF_USB ((uint)0x0000) + +#define CPM_USB_EP0_BASE 0x0a00 +#define CPM_USB_EP1_BASE 0x0a20 + +#define CPM_USB_DT0_BASE 0x0a80 +#define CPM_USB_DT1_BASE 0x0a90 +#define CPM_USB_DR0_BASE 0x0aa0 +#define CPM_USB_DR1_BASE 0x0ab0 + +#define CPM_USB_RX0_BASE 0x0b00 +#define CPM_USB_RX1_BASE 0x0b08 +#define CPM_USB_TX0_BASE 0x0b20 +#define CPM_USB_TX1_BASE 0x0b28 + +#define USB_EXPECT(x) if (!(x)) goto Done; + +typedef struct usb_param { + ushort ep0ptr; + ushort ep1ptr; + ushort ep2ptr; + ushort ep3ptr; + uint rstate; + uint rptr; + ushort frame_n; + ushort rbcnt; + ushort rtemp; +} usb_param_t; + +typedef struct usb_param_block { + ushort rbase; + ushort tbase; + uchar rfcr; + uchar tfcr; + ushort mrblr; + ushort rbptr; + ushort tbptr; + uint tstate; + uint tptr; + ushort tcrc; + ushort tbcnt; + uint res[2]; +} usb_param_block_t; + +typedef struct usb { + uchar usmod; + uchar usadr; + uchar uscom; + uchar res1; + ushort usep[4]; + uchar res2[4]; + ushort usber; + uchar res3[2]; + ushort usbmr; + uchar res4; + uchar usbs; + uchar res5[8]; +} usb_t; + +int usb_post_test (int flags) +{ + int res = -1; + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + volatile usb_param_t *pram_ptr; + uint dpram; + ushort DPRAM; + volatile cbd_t *tx; + volatile cbd_t *rx; + volatile usb_t *usbr; + volatile usb_param_block_t *ep0; + volatile usb_param_block_t *ep1; + int j; + + pram_ptr = (usb_param_t *) & (im->im_cpm.cp_dparam[PROFF_USB]); + dpram = (uint) im->im_cpm.cp_dpmem; + DPRAM = dpram; + tx = (cbd_t *) (dpram + CPM_USB_TX0_BASE); + rx = (cbd_t *) (dpram + CPM_USB_RX0_BASE); + ep0 = (usb_param_block_t *) (dpram + CPM_USB_EP0_BASE); + ep1 = (usb_param_block_t *) (dpram + CPM_USB_EP1_BASE); + usbr = (usb_t *) & (im->im_cpm.cp_scc[0]); + + /* 01 */ + im->im_ioport.iop_padir &= ~(ushort) 0x0200; + im->im_ioport.iop_papar |= (ushort) 0x0200; + + cp->cp_sicr &= ~0x000000FF; + cp->cp_sicr |= 0x00000018; + + cp->cp_brgc4 = 0x00010001; + + /* 02 */ + im->im_ioport.iop_padir &= ~(ushort) 0x0002; + im->im_ioport.iop_padir &= ~(ushort) 0x0001; + + im->im_ioport.iop_papar |= (ushort) 0x0002; + im->im_ioport.iop_papar |= (ushort) 0x0001; + + /* 03 */ + im->im_ioport.iop_pcdir &= ~(ushort) 0x0020; + im->im_ioport.iop_pcdir &= ~(ushort) 0x0010; + + im->im_ioport.iop_pcpar &= ~(ushort) 0x0020; + im->im_ioport.iop_pcpar &= ~(ushort) 0x0010; + + im->im_ioport.iop_pcso |= (ushort) 0x0020; + im->im_ioport.iop_pcso |= (ushort) 0x0010; + + /* 04 */ + im->im_ioport.iop_pcdir |= (ushort) 0x0200; + im->im_ioport.iop_pcdir |= (ushort) 0x0100; + + im->im_ioport.iop_pcpar |= (ushort) 0x0200; + im->im_ioport.iop_pcpar |= (ushort) 0x0100; + + /* 05 */ + pram_ptr->frame_n = 0; + + /* 06 */ + pram_ptr->ep0ptr = DPRAM + CPM_USB_EP0_BASE; + pram_ptr->ep1ptr = DPRAM + CPM_USB_EP1_BASE; + + /* 07-10 */ + tx[0].cbd_sc = 0xB800; + tx[0].cbd_datlen = 3; + tx[0].cbd_bufaddr = dpram + CPM_USB_DT0_BASE; + + tx[1].cbd_sc = 0xBC80; + tx[1].cbd_datlen = 3; + tx[1].cbd_bufaddr = dpram + CPM_USB_DT1_BASE; + + rx[0].cbd_sc = 0xA000; + rx[0].cbd_datlen = 0; + rx[0].cbd_bufaddr = dpram + CPM_USB_DR0_BASE; + + rx[1].cbd_sc = 0xA000; + rx[1].cbd_datlen = 0; + rx[1].cbd_bufaddr = dpram + CPM_USB_DR1_BASE; + + /* 11-12 */ + *(volatile int *) (dpram + CPM_USB_DT0_BASE) = 0x69856000; + *(volatile int *) (dpram + CPM_USB_DT1_BASE) = 0xABCD1234; + + *(volatile int *) (dpram + CPM_USB_DR0_BASE) = 0; + *(volatile int *) (dpram + CPM_USB_DR1_BASE) = 0; + + /* 13-16 */ + ep0->rbase = DPRAM + CPM_USB_RX0_BASE; + ep0->tbase = DPRAM + CPM_USB_TX0_BASE; + ep0->rfcr = 0x18; + ep0->tfcr = 0x18; + ep0->mrblr = 0x100; + ep0->rbptr = DPRAM + CPM_USB_RX0_BASE; + ep0->tbptr = DPRAM + CPM_USB_TX0_BASE; + ep0->tstate = 0; + + /* 17-20 */ + ep1->rbase = DPRAM + CPM_USB_RX1_BASE; + ep1->tbase = DPRAM + CPM_USB_TX1_BASE; + ep1->rfcr = 0x18; + ep1->tfcr = 0x18; + ep1->mrblr = 0x100; + ep1->rbptr = DPRAM + CPM_USB_RX1_BASE; + ep1->tbptr = DPRAM + CPM_USB_TX1_BASE; + ep1->tstate = 0; + + /* 21-24 */ + usbr->usep[0] = 0x0000; + usbr->usep[1] = 0x1100; + usbr->usep[2] = 0x2200; + usbr->usep[3] = 0x3300; + + /* 25 */ + usbr->usmod = 0x06; + + /* 26 */ + usbr->usadr = 0x05; + + /* 27 */ + usbr->uscom = 0; + + /* 28 */ + usbr->usmod |= 0x01; + udelay (1); + + /* 29-30 */ + usbr->uscom = 0x80; + usbr->uscom = 0x81; + + /* Wait for the data packet to be transmitted */ + for (j = 0; j < TOUT_LOOP; j++) { + if (tx[1].cbd_sc & (ushort) 0x8000) + udelay (1); + else + break; + } + + USB_EXPECT (j < TOUT_LOOP); + + USB_EXPECT (tx[0].cbd_sc == 0x3800); + USB_EXPECT (tx[0].cbd_datlen == 3); + + USB_EXPECT (tx[1].cbd_sc == 0x3C80); + USB_EXPECT (tx[1].cbd_datlen == 3); + + USB_EXPECT (rx[0].cbd_sc == 0x2C00); + USB_EXPECT (rx[0].cbd_datlen == 5); + + USB_EXPECT (*(volatile int *) (dpram + CPM_USB_DR0_BASE) == + 0xABCD122B); + USB_EXPECT (*(volatile char *) (dpram + CPM_USB_DR0_BASE + 4) == 0x42); + + res = 0; + Done: + + return res; +} + +#endif /* CONFIG_POST & CFG_POST_USB */ + +#endif /* CONFIG_POST */ diff --git a/post/watchdog.c b/post/watchdog.c new file mode 100644 index 0000000..48c4282 --- /dev/null +++ b/post/watchdog.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * Watchdog test + * + * The test verifies the watchdog timer operation. + * On the first iteration, the test routine disables interrupts and + * makes a 10-second delay. If the system does not reboot during this delay, + * the watchdog timer is not operational and the test fails. If the system + * reboots, on the second iteration the test routine reports a success. + */ + +#ifdef CONFIG_POST + +#include +#include + +#if CONFIG_POST & CFG_POST_WATCHDOG + +static ulong gettbl (void) +{ + ulong r; + + asm ("mftbl %0":"=r" (r)); + + return r; +} + +int watchdog_post_test (int flags) +{ + if (flags & POST_REBOOT) { + /* Test passed */ + + return 0; + } else { + /* 10-second delay */ + int ints = disable_interrupts (); + ulong base = gettbl (); + ulong clk = get_tbclk (); + + while ((gettbl () - base) / 10 < clk); + + if (ints) + enable_interrupts (); + + /* + * If we have reached this point, the watchdog timer + * does not work + */ + return -1; + } +} + +#endif /* CONFIG_POST & CFG_POST_WATCHDOG */ +#endif /* CONFIG_POST */ diff --git a/ppc_config.mk b/ppc_config.mk new file mode 100644 index 0000000..31993bd --- /dev/null +++ b/ppc_config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ +PLATFORM_LDFLAGS += -n diff --git a/rtc/Makefile b/rtc/Makefile new file mode 100644 index 0000000..4ceac76 --- /dev/null +++ b/rtc/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +#CFLAGS += -DDEBUG + +LIB = librtc.a + +OBJS = date.o \ + ds12887.o ds1302.o ds1306.o ds1307.o ds1337.o \ + ds1556.o ds164x.o ds174x.o \ + m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \ + mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o + +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/rtc/date.c b/rtc/date.c new file mode 100644 index 0000000..b5f8c48 --- /dev/null +++ b/rtc/date.c @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for Philips PCF8563 RTC + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) + +#define FEBRUARY 2 +#define STARTOFTIME 1970 +#define SECDAY 86400L +#define SECYR (SECDAY * 365) +#define leapyear(year) ((year) % 4 == 0) +#define days_in_year(a) (leapyear(a) ? 366 : 365) +#define days_in_month(a) (month_days[(a) - 1]) + +static int month_days[12] = { + 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 +}; + +/* + * This only works for the Gregorian calendar - i.e. after 1752 (in the UK) + */ +void GregorianDay(struct rtc_time * tm) +{ + int leapsToDate; + int lastYear; + int day; + int MonthOffset[] = { 0,31,59,90,120,151,181,212,243,273,304,334 }; + + lastYear=tm->tm_year-1; + + /* + * Number of leap corrections to apply up to end of last year + */ + leapsToDate = lastYear/4 - lastYear/100 + lastYear/400; + + /* + * This year is a leap year if it is divisible by 4 except when it is + * divisible by 100 unless it is divisible by 400 + * + * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 will be + */ + if((tm->tm_year%4==0) && + ((tm->tm_year%100!=0) || (tm->tm_year%400==0)) && + (tm->tm_mon>2)) { + /* + * We are past Feb. 29 in a leap year + */ + day=1; + } else { + day=0; + } + + day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] + tm->tm_mday; + + tm->tm_wday=day%7; +} + +void to_tm(int tim, struct rtc_time * tm) +{ + register int i; + register long hms, day; + + day = tim / SECDAY; + hms = tim % SECDAY; + + /* Hours, minutes, seconds are easy */ + tm->tm_hour = hms / 3600; + tm->tm_min = (hms % 3600) / 60; + tm->tm_sec = (hms % 3600) % 60; + + /* Number of years in days */ + for (i = STARTOFTIME; day >= days_in_year(i); i++) { + day -= days_in_year(i); + } + tm->tm_year = i; + + /* Number of months in days left */ + if (leapyear(tm->tm_year)) { + days_in_month(FEBRUARY) = 29; + } + for (i = 1; day >= days_in_month(i); i++) { + day -= days_in_month(i); + } + days_in_month(FEBRUARY) = 28; + tm->tm_mon = i; + + /* Days are what is left over (+1) from all that. */ + tm->tm_mday = day + 1; + + /* + * Determine the day of week + */ + GregorianDay(tm); +} + +/* Converts Gregorian date to seconds since 1970-01-01 00:00:00. + * Assumes input in normal date format, i.e. 1980-12-31 23:59:59 + * => year=1980, mon=12, day=31, hour=23, min=59, sec=59. + * + * [For the Julian calendar (which was used in Russia before 1917, + * Britain & colonies before 1752, anywhere else before 1582, + * and is still in use by some communities) leave out the + * -year/100+year/400 terms, and add 10.] + * + * This algorithm was first published by Gauss (I think). + * + * WARNING: this function will overflow on 2106-02-07 06:28:16 on + * machines were long is 32-bit! (However, as time_t is signed, we + * will already get problems at other places on 2038-01-19 03:14:08) + */ +unsigned long +mktime (unsigned int year, unsigned int mon, + unsigned int day, unsigned int hour, + unsigned int min, unsigned int sec) +{ + if (0 >= (int) (mon -= 2)) { /* 1..12 -> 11,12,1..10 */ + mon += 12; /* Puts Feb last since it has leap day */ + year -= 1; + } + + return ((( + (unsigned long) (year/4 - year/100 + year/400 + 367*mon/12 + day) + + year*365 - 719499 + )*24 + hour /* now have hours */ + )*60 + min /* now have minutes */ + )*60 + sec; /* finally seconds */ +} + +#endif /* CFG_CMD_DATE */ diff --git a/rtc/ds12887.c b/rtc/ds12887.c new file mode 100644 index 0000000..8b12893 --- /dev/null +++ b/rtc/ds12887.c @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2003 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the DS12887 RTC + */ + +#undef RTC_DEBUG + +#include +#include +#include +#include + +#if defined(CONFIG_RTC_DS12887) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +#define RTC_SECONDS 0x00 +#define RTC_SECONDS_ALARM 0x01 +#define RTC_MINUTES 0x02 +#define RTC_MINUTES_ALARM 0x03 +#define RTC_HOURS 0x04 +#define RTC_HOURS_ALARM 0x05 +#define RTC_DAY_OF_WEEK 0x06 +#define RTC_DATE_OF_MONTH 0x07 +#define RTC_MONTH 0x08 +#define RTC_YEAR 0x09 +#define RTC_CONTROL_A 0x0A +#define RTC_CONTROL_B 0x0B +#define RTC_CONTROL_C 0x0C +#define RTC_CONTROL_D 0x0D + +#define RTC_CA_UIP 0x80 +#define RTC_CB_DM 0x04 +#define RTC_CB_24_12 0x02 +#define RTC_CB_SET 0x80 + +#if defined(CONFIG_ATC) + +static uchar rtc_read (uchar reg) +{ + uchar val; + + *(volatile unsigned char*)(RTC_PORT_ADDR) = reg; + __asm__ __volatile__ ("sync"); + + val = *(volatile unsigned char*)(RTC_PORT_DATA); + return (val); +} + +static void rtc_write (uchar reg, uchar val) +{ + *(volatile unsigned char*)(RTC_PORT_ADDR) = reg; + __asm__ __volatile__ ("sync"); + + *(volatile unsigned char*)(RTC_PORT_DATA) = val; + __asm__ __volatile__ ("sync"); +} + +#else +# error Board specific rtc access functions should be supplied +#endif + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon, year; + + /* check if rtc is available for access */ + while( rtc_read(RTC_CONTROL_A) & RTC_CA_UIP) + ; + + sec = rtc_read(RTC_SECONDS); + min = rtc_read(RTC_MINUTES); + hour = rtc_read(RTC_HOURS); + mday = rtc_read(RTC_DATE_OF_MONTH); + wday = rtc_read(RTC_DAY_OF_WEEK); + mon = rtc_read(RTC_MONTH); + year = rtc_read(RTC_YEAR); + +#ifdef RTC_DEBUG + printf( "Get RTC year: %d; mon: %d; mday: %d; wday: %d; " + "hr: %d; min: %d; sec: %d\n", + year, mon, mday, wday, hour, min, sec ); + + printf ( "Alarms: hour: %02x min: %02x sec: %02x\n", + rtc_read (RTC_HOURS_ALARM), + rtc_read (RTC_MINUTES_ALARM), + rtc_read (RTC_SECONDS_ALARM) ); +#endif + + if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM)) + { /* Information is in BCD format */ +printf(" Get: Convert BSD to BIN\n"); + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon & 0x1F); + tmp->tm_year = bcd2bin (year); + tmp->tm_wday = bcd2bin (wday & 0x07); + } +else + { + tmp->tm_sec = sec & 0x7F; + tmp->tm_min = min & 0x7F; + tmp->tm_hour = hour & 0x3F; + tmp->tm_mday = mday & 0x3F; + tmp->tm_mon = mon & 0x1F; + tmp->tm_year = year; + tmp->tm_wday = wday & 0x07; + } + + + if(tmp->tm_year<70) + tmp->tm_year+=2000; + else + tmp->tm_year+=1900; + + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif +} + +void rtc_set (struct rtc_time *tmp) +{ + uchar save_ctrl_b; + uchar sec, min, hour, mday, wday, mon, year; + +#ifdef RTC_DEBUG + printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + + if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM)) + { /* Information is in BCD format */ + year = bin2bcd(tmp->tm_year % 100); + mon = bin2bcd(tmp->tm_mon); + wday = bin2bcd(tmp->tm_wday); + mday = bin2bcd(tmp->tm_mday); + hour = bin2bcd(tmp->tm_hour); + min = bin2bcd(tmp->tm_min); + sec = bin2bcd(tmp->tm_sec); + } + else + { + year = tmp->tm_year % 100; + mon = tmp->tm_mon; + wday = tmp->tm_wday; + mday = tmp->tm_mday; + hour = tmp->tm_hour; + min = tmp->tm_min; + sec = tmp->tm_sec; + } + + /* disables the RTC to update the regs */ + save_ctrl_b = rtc_read(RTC_CONTROL_B); + save_ctrl_b |= RTC_CB_SET; + rtc_write(RTC_CONTROL_B, save_ctrl_b); + + rtc_write (RTC_YEAR, year); + rtc_write (RTC_MONTH, mon); + rtc_write (RTC_DAY_OF_WEEK, wday); + rtc_write (RTC_DATE_OF_MONTH, mday); + rtc_write (RTC_HOURS, hour); + rtc_write (RTC_MINUTES, min); + rtc_write (RTC_SECONDS, sec); + + /* enables the RTC to update the regs */ + save_ctrl_b &= ~RTC_CB_SET; + rtc_write(RTC_CONTROL_B, save_ctrl_b); +} + +void rtc_reset (void) +{ + struct rtc_time tmp; + uchar ctrl_rg; + + ctrl_rg = RTC_CB_SET; + rtc_write(RTC_CONTROL_B,ctrl_rg); + + tmp.tm_year = 1970 % 100; + tmp.tm_mon = 1; + tmp.tm_mday= 1; + tmp.tm_hour = 0; + tmp.tm_min = 0; + tmp.tm_sec = 0; + +#ifdef RTC_DEBUG + printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", + tmp.tm_year, tmp.tm_mon, tmp.tm_mday, + tmp.tm_hour, tmp.tm_min, tmp.tm_sec); +#endif + + ctrl_rg = RTC_CB_SET | RTC_CB_24_12 | RTC_CB_DM; + rtc_write(RTC_CONTROL_B,ctrl_rg); + rtc_set(&tmp); + + rtc_write(RTC_HOURS_ALARM, 0), + rtc_write(RTC_MINUTES_ALARM, 0), + rtc_write(RTC_SECONDS_ALARM, 0); + + ctrl_rg = RTC_CB_24_12 | RTC_CB_DM; + rtc_write(RTC_CONTROL_B,ctrl_rg); +} + +#endif /* (CONFIG_RTC_DS12887) && (CONFIG_COMMANDS & CFG_CMD_DATE) */ diff --git a/rtc/ds1302.c b/rtc/ds1302.c new file mode 100644 index 0000000..98dce89 --- /dev/null +++ b/rtc/ds1302.c @@ -0,0 +1,327 @@ +/* + * ds1302.c - Support for the Dallas Semiconductor DS1302 Timekeeping Chip + * + * Rex G. Feany + * + */ + +#include +#include +#include + +#if defined(CONFIG_RTC_DS1302) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +/* GPP Pins */ +#define DATA 0x200 +#define SCLK 0x400 +#define RST 0x800 + +/* Happy Fun Defines(tm) */ +#define RESET rtc_go_low(RST), rtc_go_low(SCLK) +#define N_RESET rtc_go_high(RST), rtc_go_low(SCLK) + +#define CLOCK_HIGH rtc_go_high(SCLK) +#define CLOCK_LOW rtc_go_low(SCLK) + +#define DATA_HIGH rtc_go_high(DATA) +#define DATA_LOW rtc_go_low(DATA) +#define DATA_READ (GTREGREAD(GPP_VALUE) & DATA) + +#undef RTC_DEBUG + +#ifdef RTC_DEBUG +# define DPRINTF(x,args...) printf("ds1302: " x , ##args) +static inline void DUMP(const char *ptr, int num) +{ + while (num--) printf("%x ", *ptr++); + printf("]\n"); +} +#else +# define DPRINTF(x,args...) +# define DUMP(ptr, num) +#endif + +/* time data format for DS1302 */ +struct ds1302_st +{ + unsigned char CH:1; /* clock halt 1=stop 0=start */ + unsigned char sec10:3; + unsigned char sec:4; + + unsigned char zero0:1; + unsigned char min10:3; + unsigned char min:4; + + unsigned char fmt:1; /* 1=12 hour 0=24 hour */ + unsigned char zero1:1; + unsigned char hr10:2; /* 10 (0-2) or am/pm (am/pm, 0-1) */ + unsigned char hr:4; + + unsigned char zero2:2; + unsigned char date10:2; + unsigned char date:4; + + unsigned char zero3:3; + unsigned char month10:1; + unsigned char month:4; + + unsigned char zero4:5; + unsigned char day:3; /* day of week */ + + unsigned char year10:4; + unsigned char year:4; + + unsigned char WP:1; /* write protect 1=protect 0=unprot */ + unsigned char zero5:7; +}; + +static int ds1302_initted=0; + +/* Pin control */ +static inline void +rtc_go_high(unsigned int mask) +{ + unsigned int f = GTREGREAD(GPP_VALUE) | mask; + + GT_REG_WRITE(GPP_VALUE, f); +} + +static inline void +rtc_go_low(unsigned int mask) +{ + unsigned int f = GTREGREAD(GPP_VALUE) & ~mask; + + GT_REG_WRITE(GPP_VALUE, f); +} + +static inline void +rtc_go_input(unsigned int mask) +{ + unsigned int f = GTREGREAD(GPP_IO_CONTROL) & ~mask; + + GT_REG_WRITE(GPP_IO_CONTROL, f); +} + +static inline void +rtc_go_output(unsigned int mask) +{ + unsigned int f = GTREGREAD(GPP_IO_CONTROL) | mask; + + GT_REG_WRITE(GPP_IO_CONTROL, f); +} + +/* Access data in RTC */ + +static void +write_byte(unsigned char b) +{ + int i; + unsigned char mask=1; + + for(i=0;i<8;i++) { + CLOCK_LOW; /* Lower clock */ + (b&mask)?DATA_HIGH:DATA_LOW; /* set data */ + udelay(1); + CLOCK_HIGH; /* latch data with rising clock */ + udelay(1); + mask=mask<<1; + } +} + +static unsigned char +read_byte(void) +{ + int i; + unsigned char mask=1; + unsigned char b=0; + + for(i=0;i<8;i++) { + CLOCK_LOW; + udelay(1); + if (DATA_READ) b|=mask; /* if this bit is high, set in b */ + CLOCK_HIGH; /* clock out next bit */ + udelay(1); + mask=mask<<1; + } + return b; +} + +static void +read_ser_drv(unsigned char addr, unsigned char *buf, int count) +{ + int i; +#ifdef RTC_DEBUG + char *foo = buf; +#endif + + DPRINTF("READ 0x%x bytes @ 0x%x [ ", count, addr); + + addr|=1; /* READ */ + N_RESET; + udelay(4); + write_byte(addr); + rtc_go_input(DATA); /* Put gpp pin into input mode */ + udelay(1); + for(i=0;i9) { + printf("ds1302: Year was corrupted, fixing\n"); + bbclk.year10=100/10; /* 2000 - why not? ;) */ + bbclk.year=0; + mod=1; + } + + /* Write out the changes if needed */ + if (mod) { + /* enable write protect */ + bbclk.WP = 1; + write_ser_drv(0xbe,(unsigned char *)&bbclk,8); + } else { + /* Else just turn write protect on */ + b = 0x80; + write_ser_drv(0x8e,&b,1); + } + DPRINTF("init done\n"); + + ds1302_initted=1; +} + +void +rtc_reset(void) +{ + if(!ds1302_initted) rtc_init(); + /* TODO */ +} + +void +rtc_get(struct rtc_time *tmp) +{ + struct ds1302_st bbclk; + + if(!ds1302_initted) rtc_init(); + + read_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* read burst */ + + if (bbclk.CH) { + printf("ds1302: rtc_get: Clock was halted, clock probably " + "corrupt\n"); + } + + tmp->tm_sec=10*bbclk.sec10+bbclk.sec; + tmp->tm_min=10*bbclk.min10+bbclk.min; + tmp->tm_hour=10*bbclk.hr10+bbclk.hr; + tmp->tm_wday=bbclk.day; + tmp->tm_mday=10*bbclk.date10+bbclk.date; + tmp->tm_mon=10*bbclk.month10+bbclk.month; + tmp->tm_year=10*bbclk.year10+bbclk.year + 1900; + + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + DPRINTF("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); +} + +void +rtc_set(struct rtc_time *tmp) +{ + struct ds1302_st bbclk; + unsigned char b=0; + + if(!ds1302_initted) rtc_init(); + + DPRINTF("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + memset(&bbclk,0,sizeof(bbclk)); + bbclk.CH=0; /* dont halt */ + bbclk.WP=1; /* write protect when we're done */ + + bbclk.sec10=tmp->tm_sec/10; + bbclk.sec=tmp->tm_sec%10; + + bbclk.min10=tmp->tm_min/10; + bbclk.min=tmp->tm_min%10; + + bbclk.hr10=tmp->tm_hour/10; + bbclk.hr=tmp->tm_hour%10; + + bbclk.day=tmp->tm_wday; + + bbclk.date10=tmp->tm_mday/10; + bbclk.date=tmp->tm_mday%10; + + bbclk.month10=tmp->tm_mon/10; + bbclk.month=tmp->tm_mon%10; + + tmp->tm_year -= 1900; + bbclk.year10=tmp->tm_year/10; + bbclk.year=tmp->tm_year%10; + + write_ser_drv(0x8e,&b,1); /* disable write protect */ + write_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* write burst */ +} + +#endif diff --git a/rtc/ds1306.c b/rtc/ds1306.c new file mode 100644 index 0000000..e143bf7 --- /dev/null +++ b/rtc/ds1306.c @@ -0,0 +1,438 @@ +/* + * (C) Copyright 2002 SIXNET, dge@sixnetio.com. + * + * (C) Copyright 2004, Li-Pro.Net + * Stephan Linz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for DS1306 RTC using SPI: + * + * - SXNI855T: it uses its own soft SPI here in this file + * - all other: use the external spi_xfer() function + * (see include/spi.h) + */ + +#include +#include +#include +#include + +#if defined(CONFIG_RTC_DS1306) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +#define RTC_SECONDS 0x00 +#define RTC_MINUTES 0x01 +#define RTC_HOURS 0x02 +#define RTC_DAY_OF_WEEK 0x03 +#define RTC_DATE_OF_MONTH 0x04 +#define RTC_MONTH 0x05 +#define RTC_YEAR 0x06 + +#define RTC_SECONDS_ALARM0 0x07 +#define RTC_MINUTES_ALARM0 0x08 +#define RTC_HOURS_ALARM0 0x09 +#define RTC_DAY_OF_WEEK_ALARM0 0x0a + +#define RTC_SECONDS_ALARM1 0x0b +#define RTC_MINUTES_ALARM1 0x0c +#define RTC_HOURS_ALARM1 0x0d +#define RTC_DAY_OF_WEEK_ALARM1 0x0e + +#define RTC_CONTROL 0x0f +#define RTC_STATUS 0x10 +#define RTC_TRICKLE_CHARGER 0x11 + +#define RTC_USER_RAM_BASE 0x20 + +/* + * External table of chip select functions (see the appropriate board + * support for the actual definition of the table). + */ +extern spi_chipsel_type spi_chipsel[]; +extern int spi_chipsel_cnt; + +static unsigned int bin2bcd (unsigned int n); +static unsigned char bcd2bin (unsigned char c); + +/* ************************************************************************* */ +#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */ + +static void soft_spi_send (unsigned char n); +static unsigned char soft_spi_read (void); +static void init_spi (void); + +/*----------------------------------------------------------------------- + * Definitions + */ + +#define PB_SPISCK 0x00000002 /* PB 30 */ +#define PB_SPIMOSI 0x00000004 /* PB 29 */ +#define PB_SPIMISO 0x00000008 /* PB 28 */ +#define PB_SPI_CE 0x00010000 /* PB 15 */ + +/* ------------------------------------------------------------------------- */ + +/* read clock time from DS1306 and return it in *tmp */ +void rtc_get (struct rtc_time *tmp) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + unsigned char spi_byte; /* Data Byte */ + + init_spi (); /* set port B for software SPI */ + + /* Now we can enable the DS1306 RTC */ + immap->im_cpm.cp_pbdat |= PB_SPI_CE; + udelay (10); + + /* Shift out the address (0) of the time in the Clock Chip */ + soft_spi_send (0); + + /* Put the clock readings into the rtc_time structure */ + tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */ + tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */ + + /* Hours are trickier */ + spi_byte = soft_spi_read (); /* Read Hours into temporary value */ + if (spi_byte & 0x40) { + /* 12 hour mode bit is set (time is in 1-12 format) */ + if (spi_byte & 0x20) { + /* since PM we add 11 to get 0-23 for hours */ + tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11; + } else { + /* since AM we subtract 1 to get 0-23 for hours */ + tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1; + } + } else { + /* Otherwise, 0-23 hour format */ + tmp->tm_hour = (bcd2bin (spi_byte & 0x3F)); + } + + soft_spi_read (); /* Read and discard Day of week */ + tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */ + tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */ + + /* Read Year and convert to this century */ + tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000; + + /* Now we can disable the DS1306 RTC */ + immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ + udelay (10); + + GregorianDay (tmp); /* Determine the day of week */ + + debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +/* ------------------------------------------------------------------------- */ + +/* set clock time in DS1306 RTC and in MPC8xx RTC */ +void rtc_set (struct rtc_time *tmp) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + init_spi (); /* set port B for software SPI */ + + /* Now we can enable the DS1306 RTC */ + immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ + udelay (10); + + /* First disable write protect in the clock chip control register */ + soft_spi_send (0x8F); /* send address of the control register */ + soft_spi_send (0x00); /* send control register contents */ + + /* Now disable the DS1306 to terminate the write */ + immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; + udelay (10); + + /* Now enable the DS1306 to initiate a new write */ + immap->im_cpm.cp_pbdat |= PB_SPI_CE; + udelay (10); + + /* Next, send the address of the clock time write registers */ + soft_spi_send (0x80); /* send address of the first time register */ + + /* Use Burst Mode to send all of the time data to the clock */ + bin2bcd (tmp->tm_sec); + soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */ + soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */ + soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */ + soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */ + soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */ + soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */ + soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */ + + /* Now we can disable the Clock chip to terminate the burst write */ + immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ + udelay (10); + + /* Now we can enable the Clock chip to initiate a new write */ + immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ + udelay (10); + + /* First we Enable write protect in the clock chip control register */ + soft_spi_send (0x8F); /* send address of the control register */ + soft_spi_send (0x40); /* send out Control Register contents */ + + /* Now disable the DS1306 */ + immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ + udelay (10); + + /* Set standard MPC8xx clock to the same time so Linux will + * see the time even if it doesn't have a DS1306 clock driver. + * This helps with experimenting with standard kernels. + */ + { + ulong tim; + + tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + immap->im_sitk.sitk_rtck = KAPWR_KEY; + immap->im_sit.sit_rtc = tim; + } + + debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +/* ------------------------------------------------------------------------- */ + +/* Initialize Port B for software SPI */ +static void init_spi (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* Force output pins to begin at logic 0 */ + immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK); + + /* Set these 3 signals as outputs */ + immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK); + + immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */ + udelay (10); +} + +/* ------------------------------------------------------------------------- */ + +/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */ +static void soft_spi_send (unsigned char n) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + unsigned char bitpos; /* bit position to receive */ + unsigned char i; /* Loop Control */ + + /* bit position to send, start with most significant bit */ + bitpos = 0x80; + + /* Send 8 bits to software SPI */ + for (i = 0; i < 8; i++) { /* Loop for 8 bits */ + immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ + + if (n & bitpos) + immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */ + else + immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */ + udelay (10); + + immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ + udelay (10); + + bitpos >>= 1; /* Shift for next bit position */ + } +} + +/* ------------------------------------------------------------------------- */ + +/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */ +static unsigned char soft_spi_read (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + unsigned char spi_byte = 0; /* Return value, assume success */ + unsigned char bitpos; /* bit position to receive */ + unsigned char i; /* Loop Control */ + + /* bit position to receive, start with most significant bit */ + bitpos = 0x80; + + /* Read 8 bits here */ + for (i = 0; i < 8; i++) { /* Do 8 bits in loop */ + immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ + udelay (10); + if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */ + spi_byte |= bitpos; /* Set data accordingly */ + immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ + udelay (10); + bitpos >>= 1; /* Shift for next bit position */ + } + + return spi_byte; /* Return the byte read */ +} + +/* ------------------------------------------------------------------------- */ + +void rtc_reset (void) +{ + return; /* nothing to do */ +} + +#else /* not CONFIG_SXNI855T */ +/* ************************************************************************* */ + +static unsigned char rtc_read (unsigned char reg); +static void rtc_write (unsigned char reg, unsigned char val); + +/* read clock time from DS1306 and return it in *tmp */ +void rtc_get (struct rtc_time *tmp) +{ + unsigned char sec, min, hour, mday, wday, mon, year; + + sec = rtc_read (RTC_SECONDS); + min = rtc_read (RTC_MINUTES); + hour = rtc_read (RTC_HOURS); + mday = rtc_read (RTC_DATE_OF_MONTH); + wday = rtc_read (RTC_DAY_OF_WEEK); + mon = rtc_read (RTC_MONTH); + year = rtc_read (RTC_YEAR); + + debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, hour, min, sec); + debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n", + rtc_read (RTC_DAY_OF_WEEK_ALARM0), + rtc_read (RTC_HOURS_ALARM0), + rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0)); + debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n", + rtc_read (RTC_DAY_OF_WEEK_ALARM1), + rtc_read (RTC_HOURS_ALARM1), + rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1)); + + tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */ + tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */ + + /* convert Hours */ + tmp->tm_hour = (hour & 0x40) + ? ((hour & 0x20) /* 12 hour mode */ + ? bcd2bin (hour & 0x1F) + 11 /* PM */ + : bcd2bin (hour & 0x1F) - 1 /* AM */ + ) + : bcd2bin (hour & 0x3F); /* 24 hour mode */ + + tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */ + tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */ + tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */ + tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */ + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + + debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +/* ------------------------------------------------------------------------- */ + +/* set clock time from *tmp in DS1306 RTC */ +void rtc_set (struct rtc_time *tmp) +{ + debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); + rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); + rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); + rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1)); + rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour)); + rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min)); + rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec)); +} + +/* ------------------------------------------------------------------------- */ + +/* reset the DS1306 */ +void rtc_reset (void) +{ + /* clear the control register */ + rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */ + rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */ + + /* reset all alarms */ + rtc_write (RTC_SECONDS_ALARM0, 0x00); + rtc_write (RTC_SECONDS_ALARM1, 0x00); + rtc_write (RTC_MINUTES_ALARM0, 0x00); + rtc_write (RTC_MINUTES_ALARM1, 0x00); + rtc_write (RTC_HOURS_ALARM0, 0x00); + rtc_write (RTC_HOURS_ALARM1, 0x00); + rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00); + rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00); +} + +/* ------------------------------------------------------------------------- */ + +static unsigned char rtc_read (unsigned char reg) +{ + unsigned char dout[2]; /* SPI Output Data Bytes */ + unsigned char din[2]; /* SPI Input Data Bytes */ + + dout[0] = reg; + + if (spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din) != 0) { + return 0; + } else { + return din[1]; + } +} + +/* ------------------------------------------------------------------------- */ + +static void rtc_write (unsigned char reg, unsigned char val) +{ + unsigned char dout[2]; /* SPI Output Data Bytes */ + unsigned char din[2]; /* SPI Input Data Bytes */ + + dout[0] = 0x80 | reg; + dout[1] = val; + + spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din); +} + +#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */ + +/* ------------------------------------------------------------------------- */ + +static unsigned char bcd2bin (unsigned char n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +/* ------------------------------------------------------------------------- */ + +static unsigned int bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/rtc/ds1307.c b/rtc/ds1307.c new file mode 100644 index 0000000..3b26a0a --- /dev/null +++ b/rtc/ds1307.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2001, 2002, 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Keith Outwater, keith_outwater@mvis.com` + * Steven Scholz, steven.scholz@imc-berlin.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) + * DS1307 and DS1338 Real Time Clock (RTC). + * + * based on ds1337.c + */ + +#include +#include +#include +#include + +#if (defined(CONFIG_RTC_DS1307) || defined(CONFIG_RTC_DS1338) ) && \ + (CONFIG_COMMANDS & CFG_CMD_DATE) + +/*---------------------------------------------------------------------*/ +#undef DEBUG_RTC + +#ifdef DEBUG_RTC +#define DEBUGR(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGR(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +#ifndef CFG_I2C_RTC_ADDR +# define CFG_I2C_RTC_ADDR 0x68 +#endif + +#if defined(CONFIG_RTC_DS1307) && (CFG_I2C_SPEED > 100000) +# error The DS1307 is specified only up to 100kHz! +#endif + +/* + * RTC register addresses + */ +#define RTC_SEC_REG_ADDR 0x00 +#define RTC_MIN_REG_ADDR 0x01 +#define RTC_HR_REG_ADDR 0x02 +#define RTC_DAY_REG_ADDR 0x03 +#define RTC_DATE_REG_ADDR 0x04 +#define RTC_MON_REG_ADDR 0x05 +#define RTC_YR_REG_ADDR 0x06 +#define RTC_CTL_REG_ADDR 0x07 + +#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ + +#define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */ +#define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */ +#define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ +#define RTC_CTL_BIT_OUT 0x80 /* Output Control */ + +static uchar rtc_read (uchar reg); +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin (uchar c); + +/* + * Get the current time from the RTC + */ +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon, year; + + sec = rtc_read (RTC_SEC_REG_ADDR); + min = rtc_read (RTC_MIN_REG_ADDR); + hour = rtc_read (RTC_HR_REG_ADDR); + wday = rtc_read (RTC_DAY_REG_ADDR); + mday = rtc_read (RTC_DATE_REG_ADDR); + mon = rtc_read (RTC_MON_REG_ADDR); + year = rtc_read (RTC_YR_REG_ADDR); + + DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, hour, min, sec); + + if (sec & RTC_SEC_BIT_CH) { + printf ("### Warning: RTC oscillator has stopped\n"); + /* clear the CH flag */ + rtc_write (RTC_SEC_REG_ADDR, + rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH); + } + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon & 0x1F); + tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000); + tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + + +/* + * Set the RTC + */ +void rtc_set (struct rtc_time *tmp) +{ + DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + if (tmp->tm_year < 1970 || tmp->tm_year > 2069) + printf("WARNING: year should be between 1970 and 2069!\n"); + + rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); + rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); + rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); + rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); + rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); + rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); +} + + +/* + * Reset the RTC. We setting the date back to 1970-01-01. + * We also enable the oscillator output on the SQW/OUT pin and program + * it for 32,768 Hz output. Note that according to the datasheet, turning + * on the square wave output increases the current drain on the backup + * battery to something between 480nA and 800nA. + */ +void rtc_reset (void) +{ + struct rtc_time tmp; + + rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */ + rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0); + + tmp.tm_year = 1970; + tmp.tm_mon = 1; + tmp.tm_mday= 1; + tmp.tm_hour = 0; + tmp.tm_min = 0; + tmp.tm_sec = 0; + + rtc_set(&tmp); + + printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", + tmp.tm_year, tmp.tm_mon, tmp.tm_mday, + tmp.tm_hour, tmp.tm_min, tmp.tm_sec); + + return; +} + + +/* + * Helper functions + */ + +static +uchar rtc_read (uchar reg) +{ + return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); +} + + +static void rtc_write (uchar reg, uchar val) +{ + i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* (CONFIG_RTC_DS1307 || CONFIG_RTC_DS1338) && (CFG_COMMANDS & CFG_CMD_DATE) */ diff --git a/rtc/ds1337.c b/rtc/ds1337.c new file mode 100644 index 0000000..9f0c8c0 --- /dev/null +++ b/rtc/ds1337.c @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Keith Outwater, keith_outwater@mvis.com` + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) + * DS1337 Real Time Clock (RTC). + */ + +#include +#include +#include +#include + +#if defined(CONFIG_RTC_DS1337) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +/*---------------------------------------------------------------------*/ +#undef DEBUG_RTC + +#ifdef DEBUG_RTC +#define DEBUGR(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGR(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +/* + * RTC register addresses + */ +#define RTC_SEC_REG_ADDR 0x0 +#define RTC_MIN_REG_ADDR 0x1 +#define RTC_HR_REG_ADDR 0x2 +#define RTC_DAY_REG_ADDR 0x3 +#define RTC_DATE_REG_ADDR 0x4 +#define RTC_MON_REG_ADDR 0x5 +#define RTC_YR_REG_ADDR 0x6 +#define RTC_CTL_REG_ADDR 0x0e +#define RTC_STAT_REG_ADDR 0x0f + +/* + * RTC control register bits + */ +#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */ +#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */ +#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */ +#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */ +#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */ +#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */ + +/* + * RTC status register bits + */ +#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */ +#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ +#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ + + +static uchar rtc_read (uchar reg); +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin (uchar c); + + +/* + * Get the current time from the RTC + */ +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon_cent, year, control, status; + + control = rtc_read (RTC_CTL_REG_ADDR); + status = rtc_read (RTC_STAT_REG_ADDR); + sec = rtc_read (RTC_SEC_REG_ADDR); + min = rtc_read (RTC_MIN_REG_ADDR); + hour = rtc_read (RTC_HR_REG_ADDR); + wday = rtc_read (RTC_DAY_REG_ADDR); + mday = rtc_read (RTC_DATE_REG_ADDR); + mon_cent = rtc_read (RTC_MON_REG_ADDR); + year = rtc_read (RTC_YR_REG_ADDR); + + DEBUGR ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", + year, mon_cent, mday, wday, hour, min, sec, control, status); + + if (status & RTC_STAT_BIT_OSF) { + printf ("### Warning: RTC oscillator has stopped\n"); + /* clear the OSF flag */ + rtc_write (RTC_STAT_REG_ADDR, + rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); + } + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon_cent & 0x1F); + tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); + tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + + +/* + * Set the RTC + */ +void rtc_set (struct rtc_time *tmp) +{ + uchar century; + + DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); + + century = (tmp->tm_year >= 2000) ? 0x80 : 0; + rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century); + + rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); + rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); + rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); + rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); +} + + +/* + * Reset the RTC. We also enable the oscillator output on the + * SQW/INTB* pin and program it for 32,768 Hz output. Note that + * according to the datasheet, turning on the square wave output + * increases the current drain on the backup battery from about + * 600 nA to 2uA. + */ +void rtc_reset (void) +{ + rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2); +} + + +/* + * Helper functions + */ + +static +uchar rtc_read (uchar reg) +{ + return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); +} + + +static void rtc_write (uchar reg, uchar val) +{ + i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* CONFIG_RTC_DS1337 && (CFG_COMMANDS & CFG_CMD_DATE) */ diff --git a/rtc/ds1556.c b/rtc/ds1556.c new file mode 100644 index 0000000..dd9ea5e --- /dev/null +++ b/rtc/ds1556.c @@ -0,0 +1,206 @@ +/* + * (C) Copyright 2002 + * ARIO Data Networks, Inc. dchiu@ariodata.com + * + * modified for DS1556: + * Frank Panno , Delphin Technology AG + * + * Based on MontaVista DS1743 code and U-Boot mc146818 code + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the DS1556 RTC + */ + +/*#define RTC_DEBUG */ + +#include +#include +#include + + +#if defined(CONFIG_RTC_DS1556) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +static uchar rtc_read( unsigned int addr ); +static void rtc_write( unsigned int addr, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin(uchar c); + +#define RTC_BASE ( CFG_NVRAM_SIZE + CFG_NVRAM_BASE_ADDR ) + +#define RTC_YEAR ( RTC_BASE + 0xf ) +#define RTC_MONTH ( RTC_BASE + 0xe ) +#define RTC_DAY_OF_MONTH ( RTC_BASE + 0xd ) +#define RTC_DAY_OF_WEEK ( RTC_BASE + 0xc ) +#define RTC_HOURS ( RTC_BASE + 0xb ) +#define RTC_MINUTES ( RTC_BASE + 0xa ) +#define RTC_SECONDS ( RTC_BASE + 0x9 ) +#define RTC_CENTURY ( RTC_BASE + 0x8 ) + +#define RTC_CONTROLA RTC_CENTURY +#define RTC_CONTROLB RTC_SECONDS +#define RTC_CONTROLC RTC_BASE + +#define RTC_CA_WRITE 0x80 +#define RTC_CA_READ 0x40 + +#define RTC_CB_OSC_DISABLE 0x80 + +#define RTC_CC_BATTERY_FLAG 0x10 +#define RTC_CC_FREQ_TEST 0x40 + +/* ------------------------------------------------------------------------- */ + +void rtc_get( struct rtc_time *tmp ) +{ + uchar sec, min, hour; + uchar mday, wday, mon, year; + + int century; + + uchar reg_a; + + reg_a = rtc_read( RTC_CONTROLA ); + /* lock clock registers for read */ + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); + + sec = rtc_read( RTC_SECONDS ); + min = rtc_read( RTC_MINUTES ); + hour = rtc_read( RTC_HOURS ); + mday = rtc_read( RTC_DAY_OF_MONTH ); + wday = rtc_read( RTC_DAY_OF_WEEK ); + mon = rtc_read( RTC_MONTH ); + year = rtc_read( RTC_YEAR ); + century = rtc_read( RTC_CENTURY ); + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); + +#ifdef RTC_DEBUG + printf( "Get RTC year: %02x mon/cent: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, century, mon, mday, wday, + hour, min, sec ); +#endif + tmp->tm_sec = bcd2bin( sec & 0x7F ); + tmp->tm_min = bcd2bin( min & 0x7F ); + tmp->tm_hour = bcd2bin( hour & 0x3F ); + tmp->tm_mday = bcd2bin( mday & 0x3F ); + tmp->tm_mon = bcd2bin( mon & 0x1F ); + tmp->tm_wday = bcd2bin( wday & 0x07 ); + + /* glue year from century and year in century */ + tmp->tm_year = bcd2bin( year ) + + ( bcd2bin( century & 0x3F ) * 100 ); + + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); +#endif +} + +void rtc_set( struct rtc_time *tmp ) +{ + uchar reg_a; +#ifdef RTC_DEBUG + printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + /* lock clock registers for write */ + reg_a = rtc_read( RTC_CONTROLA ); + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); + + rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); + + rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); + rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); + rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); + rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); + rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); + + /* break year up into century and year in century */ + rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); + rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); +} + +void rtc_reset (void) +{ + uchar reg_a, reg_b, reg_c; + + reg_a = rtc_read( RTC_CONTROLA ); + reg_b = rtc_read( RTC_CONTROLB ); + + if ( reg_b & RTC_CB_OSC_DISABLE ) + { + printf( "real-time-clock was stopped. Now starting...\n" ); + reg_a |= RTC_CA_WRITE; + reg_b &= ~RTC_CB_OSC_DISABLE; + + rtc_write( RTC_CONTROLA, reg_a ); + rtc_write( RTC_CONTROLB, reg_b ); + } + + /* make sure read/write clock register bits are cleared */ + reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); + rtc_write( RTC_CONTROLA, reg_a ); + + reg_c = rtc_read( RTC_CONTROLC ); + if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) + printf( "RTC battery low. Clock setting may not be reliable.\n" ); +} + +/* ------------------------------------------------------------------------- */ + +static uchar rtc_read( unsigned int addr ) +{ + uchar val = *(volatile unsigned char*)(addr); +#ifdef RTC_DEBUG + printf( "rtc_read: %x:%x\n", addr, val ); +#endif + return( val ); +} + +static void rtc_write( unsigned int addr, uchar val ) +{ +#ifdef RTC_DEBUG + printf( "rtc_write: %x:%x\n", addr, val ); +#endif + *(volatile unsigned char*)(addr) = val; +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* CONFIG_RTC_DS1556 && CFG_CMD_DATE */ diff --git a/rtc/ds164x.c b/rtc/ds164x.c new file mode 100644 index 0000000..3cc76ab --- /dev/null +++ b/rtc/ds164x.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2002 + * ARIO Data Networks, Inc. dchiu@ariodata.com + * + * modified for DS164x: + * The LEOX team , http://www.leox.org + * + * Based on MontaVista DS1743 code and U-Boot mc146818 code + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the DS164x RTC + */ + +/* #define RTC_DEBUG */ + +#include +#include +#include + + +#if defined(CONFIG_RTC_DS164x) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +static uchar rtc_read(unsigned int addr ); +static void rtc_write(unsigned int addr, uchar val); +static uchar bin2bcd(unsigned int n); +static unsigned bcd2bin(uchar c); + +#define RTC_EPOCH 2000 /* century */ + +/* + * DS164x registers layout + */ +#define RTC_BASE ( CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE ) + +#define RTC_YEAR ( RTC_BASE + 0x07 ) +#define RTC_MONTH ( RTC_BASE + 0x06 ) +#define RTC_DAY_OF_MONTH ( RTC_BASE + 0x05 ) +#define RTC_DAY_OF_WEEK ( RTC_BASE + 0x04 ) +#define RTC_HOURS ( RTC_BASE + 0x03 ) +#define RTC_MINUTES ( RTC_BASE + 0x02 ) +#define RTC_SECONDS ( RTC_BASE + 0x01 ) +#define RTC_CONTROL ( RTC_BASE + 0x00 ) + +#define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */ +#define RTC_CA_WRITE 0x80 +#define RTC_CA_READ 0x40 +#define RTC_CONTROLB RTC_SECONDS /* OSC=bit7 */ +#define RTC_CB_OSC_DISABLE 0x80 +#define RTC_CONTROLC RTC_DAY_OF_WEEK /* FT=bit6 */ +#define RTC_CC_FREQ_TEST 0x40 + +/* ------------------------------------------------------------------------- */ + +void rtc_get( struct rtc_time *tmp ) +{ + uchar sec, min, hour; + uchar mday, wday, mon, year; + + uchar reg_a; + + reg_a = rtc_read( RTC_CONTROLA ); + /* lock clock registers for read */ + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); + + sec = rtc_read( RTC_SECONDS ); + min = rtc_read( RTC_MINUTES ); + hour = rtc_read( RTC_HOURS ); + mday = rtc_read( RTC_DAY_OF_MONTH ); + wday = rtc_read( RTC_DAY_OF_WEEK ); + mon = rtc_read( RTC_MONTH ); + year = rtc_read( RTC_YEAR ); + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); + +#ifdef RTC_DEBUG + printf( "Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, + hour, min, sec ); +#endif + tmp->tm_sec = bcd2bin( sec & 0x7F ); + tmp->tm_min = bcd2bin( min & 0x7F ); + tmp->tm_hour = bcd2bin( hour & 0x3F ); + tmp->tm_mday = bcd2bin( mday & 0x3F ); + tmp->tm_mon = bcd2bin( mon & 0x1F ); + tmp->tm_wday = bcd2bin( wday & 0x07 ); + + /* glue year in century (2000) */ + tmp->tm_year = bcd2bin( year ) + RTC_EPOCH; + + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); +#endif +} + +void rtc_set( struct rtc_time *tmp ) +{ + uchar reg_a; + +#ifdef RTC_DEBUG + printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + /* lock clock registers for write */ + reg_a = rtc_read( RTC_CONTROLA ); + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); + + rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); + + rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); + rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); + rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); + rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); + rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); + + /* break year in century */ + rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); +} + +void rtc_reset (void) +{ + uchar reg_a, reg_b; + + reg_a = rtc_read( RTC_CONTROLA ); + reg_b = rtc_read( RTC_CONTROLB ); + + if ( reg_b & RTC_CB_OSC_DISABLE ) + { + printf( "real-time-clock was stopped. Now starting...\n" ); + reg_a |= RTC_CA_WRITE; + reg_b &= ~RTC_CB_OSC_DISABLE; + + rtc_write( RTC_CONTROLA, reg_a ); + rtc_write( RTC_CONTROLB, reg_b ); + } + + /* make sure read/write clock register bits are cleared */ + reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); + rtc_write( RTC_CONTROLA, reg_a ); +} + +/* ------------------------------------------------------------------------- */ + +static uchar rtc_read( unsigned int addr ) +{ + uchar val = *(volatile unsigned char*)(addr); + +#ifdef RTC_DEBUG + printf( "rtc_read: %x:%x\n", addr, val ); +#endif + return( val ); +} + +static void rtc_write( unsigned int addr, uchar val ) +{ +#ifdef RTC_DEBUG + printf( "rtc_write: %x:%x\n", addr, val ); +#endif + *(volatile unsigned char*)(addr) = val; +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* CONFIG_RTC_DS164x && CFG_CMD_DATE */ diff --git a/rtc/ds174x.c b/rtc/ds174x.c new file mode 100644 index 0000000..58b13e9 --- /dev/null +++ b/rtc/ds174x.c @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2001 + * ARIO Data Networks, Inc. dchiu@ariodata.com + * + * Based on MontaVista DS1743 code and U-Boot mc146818 code + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the DS174x RTC + */ + +/*#define DEBUG*/ + +#include +#include +#include + +#if defined(CONFIG_RTC_DS174x) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +static uchar rtc_read( unsigned int addr ); +static void rtc_write( unsigned int addr, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin(uchar c); + +#define RTC_BASE ( CFG_NVRAM_SIZE + CFG_NVRAM_BASE_ADDR ) + +#define RTC_YEAR ( RTC_BASE + 7 ) +#define RTC_MONTH ( RTC_BASE + 6 ) +#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 ) +#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 ) +#define RTC_HOURS ( RTC_BASE + 3 ) +#define RTC_MINUTES ( RTC_BASE + 2 ) +#define RTC_SECONDS ( RTC_BASE + 1 ) +#define RTC_CENTURY ( RTC_BASE + 0 ) + +#define RTC_CONTROLA RTC_CENTURY +#define RTC_CONTROLB RTC_SECONDS +#define RTC_CONTROLC RTC_DAY_OF_WEEK + +#define RTC_CA_WRITE 0x80 +#define RTC_CA_READ 0x40 + +#define RTC_CB_OSC_DISABLE 0x80 + +#define RTC_CC_BATTERY_FLAG 0x80 +#define RTC_CC_FREQ_TEST 0x40 + +/* ------------------------------------------------------------------------- */ + +void rtc_get( struct rtc_time *tmp ) +{ + uchar sec, min, hour; + uchar mday, wday, mon, year; + + int century; + + uchar reg_a; + + reg_a = rtc_read( RTC_CONTROLA ); + /* lock clock registers for read */ + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); + + sec = rtc_read( RTC_SECONDS ); + min = rtc_read( RTC_MINUTES ); + hour = rtc_read( RTC_HOURS ); + mday = rtc_read( RTC_DAY_OF_MONTH ); + wday = rtc_read( RTC_DAY_OF_WEEK ); + mon = rtc_read( RTC_MONTH ); + year = rtc_read( RTC_YEAR ); + century = rtc_read( RTC_CENTURY ); + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); + +#ifdef RTC_DEBUG + printf( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon_cent, mday, wday, + hour, min, sec ); +#endif + tmp->tm_sec = bcd2bin( sec & 0x7F ); + tmp->tm_min = bcd2bin( min & 0x7F ); + tmp->tm_hour = bcd2bin( hour & 0x3F ); + tmp->tm_mday = bcd2bin( mday & 0x3F ); + tmp->tm_mon = bcd2bin( mon & 0x1F ); + tmp->tm_wday = bcd2bin( wday & 0x07 ); + + /* glue year from century and year in century */ + tmp->tm_year = bcd2bin( year ) + + ( bcd2bin( century & 0x3F ) * 100 ); + + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); +#endif +} + +void rtc_set( struct rtc_time *tmp ) +{ + uchar reg_a; +#ifdef RTC_DEBUG + printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + /* lock clock registers for write */ + reg_a = rtc_read( RTC_CONTROLA ); + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); + + rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); + + rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); + rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); + rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); + rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); + rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); + + /* break year up into century and year in century */ + rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); + rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); +} + +void rtc_reset (void) +{ + uchar reg_a, reg_b, reg_c; + + reg_a = rtc_read( RTC_CONTROLA ); + reg_b = rtc_read( RTC_CONTROLB ); + + if ( reg_b & RTC_CB_OSC_DISABLE ) + { + printf( "real-time-clock was stopped. Now starting...\n" ); + reg_a |= RTC_CA_WRITE; + reg_b &= ~RTC_CB_OSC_DISABLE; + + rtc_write( RTC_CONTROLA, reg_a ); + rtc_write( RTC_CONTROLB, reg_b ); + } + + /* make sure read/write clock register bits are cleared */ + reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); + rtc_write( RTC_CONTROLA, reg_a ); + + reg_c = rtc_read( RTC_CONTROLC ); + if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) + printf( "RTC battery low. Clock setting may not be reliable.\n" ); +} + +/* ------------------------------------------------------------------------- */ + +static uchar rtc_read( unsigned int addr ) +{ + uchar val = in8( addr ); +#ifdef RTC_DEBUG + printf( "rtc_read: %x:%x\n", addr, val ); +#endif + return( val ); +} + +static void rtc_write( unsigned int addr, uchar val ) +{ +#ifdef RTC_DEBUG + printf( "rtc_write: %x:%x\n", addr, val ); +#endif + out8( addr, val ); +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* CONFIG_RTC_MC146818 && CFG_CMD_DATE */ diff --git a/rtc/m41t11.c b/rtc/m41t11.c new file mode 100644 index 0000000..c725cc9 --- /dev/null +++ b/rtc/m41t11.c @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2002 + * Andrew May, Viasat Inc, amay@viasat.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * M41T11 Serial Access Timekeeper(R) SRAM + * can you believe a trademark on that? + */ + +/* #define DEBUG 1 */ + +#include +#include +#include +#include + +/* + I Don't have an example config file but this + is what should be done. + +#define CONFIG_RTC_M41T11 1 +#define CFG_I2C_RTC_ADDR 0x68 +#if 0 +#define CFG_M41T11_EXT_CENTURY_DATA +#else +#define CFG_M41T11_BASE_YEAR 2000 +#endif +*/ + +#if defined(CONFIG_RTC_M41T11) && defined(CFG_I2C_RTC_ADDR) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + + +/* ------------------------------------------------------------------------- */ +/* + these are simple defines for the chip local to here so they aren't too + verbose + DAY/DATE aren't nice but that is how they are on the data sheet +*/ +#define RTC_SEC_ADDR 0x0 +#define RTC_MIN_ADDR 0x1 +#define RTC_HOUR_ADDR 0x2 +#define RTC_DAY_ADDR 0x3 +#define RTC_DATE_ADDR 0x4 +#define RTC_MONTH_ADDR 0x5 +#define RTC_YEARS_ADDR 0x6 + +#define RTC_REG_CNT 7 + +#define RTC_CONTROL_ADDR 0x7 + + +#ifndef CFG_M41T11_EXT_CENTURY_DATA + +#define REG_CNT (RTC_REG_CNT+1) + +/* + you only get 00-99 for the year we will asume you + want from the year 2000 if you don't set the config +*/ +#ifndef CFG_M41T11_BASE_YEAR +#define CFG_M41T11_BASE_YEAR 2000 +#endif + +#else +/* we will store extra year info in byte 9*/ +#define M41T11_YEAR_DATA 0x8 +#define M41T11_YEAR_SIZE 1 +#define REG_CNT (RTC_REG_CNT+1+M41T11_YEAR_SIZE) +#endif + +#define M41T11_STORAGE_SZ (64-REG_CNT) + +void rtc_get (struct rtc_time *tmp) +{ + uchar data[RTC_REG_CNT]; + + i2c_read(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); + + if( data[RTC_SEC_ADDR] & 0x80 ){ + printf( "m41t11 RTC Clock stopped!!!\n" ); + } + tmp->tm_sec = bcd2bin (data[RTC_SEC_ADDR] & 0x7F); + tmp->tm_min = bcd2bin (data[RTC_MIN_ADDR] & 0x7F); + tmp->tm_hour = bcd2bin (data[RTC_HOUR_ADDR] & 0x3F); + tmp->tm_mday = bcd2bin (data[RTC_DATE_ADDR] & 0x3F); + tmp->tm_mon = bcd2bin (data[RTC_MONTH_ADDR]& 0x1F); +#ifndef CFG_M41T11_EXT_CENTURY_DATA + tmp->tm_year = CFG_M41T11_BASE_YEAR + + bcd2bin(data[RTC_YEARS_ADDR]) + + ((data[RTC_HOUR_ADDR]&0x40) ? 100 : 0); +#else + { + unsigned char cent; + i2c_read(CFG_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); + if( !(data[RTC_HOUR_ADDR] & 0x80) ){ + printf( "m41t11 RTC: cann't keep track of years without CEB set\n" ); + } + if( (cent & 0x1) != ((data[RTC_HOUR_ADDR]&0x40)>>7) ){ + /*century flip store off new year*/ + cent += 1; + i2c_write(CFG_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); + } + tmp->tm_year =((int)cent*100)+bcd2bin(data[RTC_YEARS_ADDR]); + } +#endif + tmp->tm_wday = bcd2bin (data[RTC_DAY_ADDR] & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +void rtc_set (struct rtc_time *tmp) +{ + uchar data[RTC_REG_CNT]; + + debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + data[RTC_SEC_ADDR] = bin2bcd(tmp->tm_sec) & 0x7F;/*just in case*/ + data[RTC_MIN_ADDR] = bin2bcd(tmp->tm_min); + data[RTC_HOUR_ADDR] = bin2bcd(tmp->tm_hour) & 0x3F;/*handle cent stuff later*/ + data[RTC_DATE_ADDR] = bin2bcd(tmp->tm_mday) & 0x3F; + data[RTC_MONTH_ADDR] = bin2bcd(tmp->tm_mon); + data[RTC_DAY_ADDR] = bin2bcd(tmp->tm_wday) & 0x07; + + data[RTC_HOUR_ADDR] |= 0x80;/*we will always use CEB*/ + + data[RTC_YEARS_ADDR] = bin2bcd(tmp->tm_year%100);/*same thing either way*/ +#ifndef CFG_M41T11_EXT_CENTURY_DATA + if( ((tmp->tm_year - CFG_M41T11_BASE_YEAR) > 200) || + (tmp->tm_year < CFG_M41T11_BASE_YEAR) ){ + printf( "m41t11 RTC setting year out of range!!need recompile\n" ); + } + data[RTC_HOUR_ADDR] |= (tmp->tm_year - CFG_M41T11_BASE_YEAR) > 100 ? 0x40 : 0; +#else + { + unsigned char cent; + cent = tmp->tm_year ? tmp->tm_year / 100 : 0; + data[RTC_HOUR_ADDR] |= (cent & 0x1) ? 0x40 : 0; + i2c_write(CFG_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); + } +#endif + i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); +} + +void rtc_reset (void) +{ + unsigned char val; + /* clear all control & status registers */ + i2c_read(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, 1); + val = val & 0x7F;/*make sure we are running*/ + i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, RTC_REG_CNT); + + i2c_read(CFG_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); + val = val & 0x3F;/*turn off freq test keep calibration*/ + i2c_write(CFG_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); +} + +int rtc_store(int addr, unsigned char* data, int size) +{ + /*don't let things wrap onto the time on a write*/ + if( (addr+size) >= M41T11_STORAGE_SZ ) + return 1; + return i2c_write( CFG_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); +} + +int rtc_recall(int addr, unsigned char* data, int size) +{ + return i2c_read( CFG_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); +} + +#endif /* CONFIG_RTC_M41T11 && CFG_I2C_RTC_ADDR && CFG_CMD_DATE */ diff --git a/rtc/m48t35ax.c b/rtc/m48t35ax.c new file mode 100644 index 0000000..6c38a53 --- /dev/null +++ b/rtc/m48t35ax.c @@ -0,0 +1,166 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for ST Electronics M48T35Ax RTC + */ + +/*#define DEBUG */ + + +#include +#include +#include +#include + +#if defined(CONFIG_RTC_M48T35A) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +static uchar rtc_read (uchar reg); +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin(uchar c); + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, cent_day, date, month, year; + uchar ccr; /* Clock control register */ + + /* Lock RTC for read using clock control register */ + ccr = rtc_read(0); + ccr = ccr | 0x40; + rtc_write(0, ccr); + + sec = rtc_read (0x1); + min = rtc_read (0x2); + hour = rtc_read (0x3); + cent_day= rtc_read (0x4); + date = rtc_read (0x5); + month = rtc_read (0x6); + year = rtc_read (0x7); + + /* UNLock RTC */ + ccr = rtc_read(0); + ccr = ccr & 0xBF; + rtc_write(0, ccr); + + debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, month, date, cent_day, + hour, min, sec ); + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (date & 0x3F); + tmp->tm_mon = bcd2bin (month & 0x1F); + tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900); + tmp->tm_wday = bcd2bin (cent_day & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +void rtc_set (struct rtc_time *tmp) +{ + uchar ccr; /* Clock control register */ + uchar century; + + debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + /* Lock RTC for write using clock control register */ + ccr = rtc_read(0); + ccr = ccr | 0x80; + rtc_write(0, ccr); + + rtc_write (0x07, bin2bcd(tmp->tm_year % 100)); + rtc_write (0x06, bin2bcd(tmp->tm_mon)); + rtc_write (0x05, bin2bcd(tmp->tm_mday)); + + century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20; + rtc_write (0x04, bin2bcd(tmp->tm_wday) | century); + + rtc_write (0x03, bin2bcd(tmp->tm_hour)); + rtc_write (0x02, bin2bcd(tmp->tm_min )); + rtc_write (0x01, bin2bcd(tmp->tm_sec )); + + /* UNLock RTC */ + ccr = rtc_read(0); + ccr = ccr & 0x7F; + rtc_write(0, ccr); +} + +void rtc_reset (void) +{ + uchar val; + + /* Clear all clock control registers */ + rtc_write (0x0, 0x80); /* No Read Lock or calibration */ + + /* Clear stop bit */ + val = rtc_read (0x1); + val &= 0x7f; + rtc_write(0x1, val); + + /* Enable century / disable frequency test */ + val = rtc_read (0x4); + val = (val & 0xBF) | 0x20; + rtc_write(0x4, val); + + /* Clear write lock */ + rtc_write(0x0, 0); +} + +/* ------------------------------------------------------------------------- */ + +static uchar rtc_read (uchar reg) +{ + uchar val; + val = *(unsigned char *) + ((CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 8) + reg); + return val; +} + +static void rtc_write (uchar reg, uchar val) +{ + *(unsigned char *) + ((CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 8) + reg) = val; +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* CONFIG_RTC_M48T35A && CFG_CMD_DATE */ diff --git a/rtc/max6900.c b/rtc/max6900.c new file mode 100644 index 0000000..73919cd --- /dev/null +++ b/rtc/max6900.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for MAXIM MAX6900 RTC + */ + +/* #define DEBUG */ + +#include +#include +#include +#include + +#if defined(CONFIG_RTC_MAX6900) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +#ifndef CFG_I2C_RTC_ADDR +#define CFG_I2C_RTC_ADDR 0x50 +#endif + +/* ------------------------------------------------------------------------- */ + +static uchar rtc_read (uchar reg) +{ + return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); +} + +static void rtc_write (uchar reg, uchar val) +{ + i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + udelay(2500); +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon, cent, year; + int retry = 1; + + do { + sec = rtc_read (0x80); + min = rtc_read (0x82); + hour = rtc_read (0x84); + mday = rtc_read (0x86); + mon = rtc_read (0x88); + wday = rtc_read (0x8a); + year = rtc_read (0x8c); + cent = rtc_read (0x92); + /* + * Check for seconds rollover + */ + if ((sec != 59) || (rtc_read(0x80) == sec)){ + retry = 0; + } + } while (retry); + + debug ( "Get RTC year: %02x mon: %02x cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, cent, mday, wday, + hour, min, sec ); + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon & 0x1F); + tmp->tm_year = bcd2bin (year) + bcd2bin(cent) * 100; + tmp->tm_wday = bcd2bin (wday & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +void rtc_set (struct rtc_time *tmp) +{ + + debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + rtc_write (0x9E, 0x00); + rtc_write (0x80, 0); /* Clear seconds to ensure no rollover */ + rtc_write (0x92, bin2bcd(tmp->tm_year / 100)); + rtc_write (0x8c, bin2bcd(tmp->tm_year % 100)); + rtc_write (0x8a, bin2bcd(tmp->tm_wday)); + rtc_write (0x88, bin2bcd(tmp->tm_mon)); + rtc_write (0x86, bin2bcd(tmp->tm_mday)); + rtc_write (0x84, bin2bcd(tmp->tm_hour)); + rtc_write (0x82, bin2bcd(tmp->tm_min )); + rtc_write (0x80, bin2bcd(tmp->tm_sec )); +} + +void rtc_reset (void) +{ +} + +#endif /* CONFIG_RTC_MAX6900 && CFG_CMD_DATE */ diff --git a/rtc/mc146818.c b/rtc/mc146818.c new file mode 100644 index 0000000..20b1b3e --- /dev/null +++ b/rtc/mc146818.c @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2001 + * Denis Peter MPL AG Switzerland. d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the MC146818 (PIXX4) RTC + */ + +/*#define DEBUG*/ + +#include +#include +#include + +#if defined(CONFIG_RTC_MC146818) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +static uchar rtc_read (uchar reg); +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin(uchar c); + +#define RTC_PORT_MC146818 CFG_ISA_IO_BASE_ADDRESS + 0x70 +#define RTC_SECONDS 0x00 +#define RTC_SECONDS_ALARM 0x01 +#define RTC_MINUTES 0x02 +#define RTC_MINUTES_ALARM 0x03 +#define RTC_HOURS 0x04 +#define RTC_HOURS_ALARM 0x05 +#define RTC_DAY_OF_WEEK 0x06 +#define RTC_DATE_OF_MONTH 0x07 +#define RTC_MONTH 0x08 +#define RTC_YEAR 0x09 +#define RTC_CONFIG_A 0x0A +#define RTC_CONFIG_B 0x0B +#define RTC_CONFIG_C 0x0C +#define RTC_CONFIG_D 0x0D + + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon, year; + /* here check if rtc can be accessed */ + while((rtc_read(RTC_CONFIG_A)&0x80)==0x80); + sec = rtc_read (RTC_SECONDS); + min = rtc_read (RTC_MINUTES); + hour = rtc_read (RTC_HOURS); + mday = rtc_read (RTC_DATE_OF_MONTH); + wday = rtc_read (RTC_DAY_OF_WEEK); + mon = rtc_read (RTC_MONTH); + year = rtc_read (RTC_YEAR); +#ifdef CONFIG_AMIGAONEG3SE + wday -= 1; /* VIA 686 stores Sunday = 1, Monday = 2, ... */ +#endif +#ifdef RTC_DEBUG + printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, + hour, min, sec ); + printf ( "Alarms: month: %02x hour: %02x min: %02x sec: %02x\n", + rtc_read (RTC_CONFIG_D) & 0x3F, + rtc_read (RTC_HOURS_ALARM), + rtc_read (RTC_MINUTES_ALARM), + rtc_read (RTC_SECONDS_ALARM) ); +#endif + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon & 0x1F); + tmp->tm_year = bcd2bin (year); + tmp->tm_wday = bcd2bin (wday & 0x07); + if(tmp->tm_year<70) + tmp->tm_year+=2000; + else + tmp->tm_year+=1900; + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif +} + +void rtc_set (struct rtc_time *tmp) +{ +#ifdef RTC_DEBUG + printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + rtc_write(RTC_CONFIG_B,0x82); /* disables the RTC to update the regs */ + + rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100)); + rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon)); +#ifdef CONFIG_AMIGAONEG3SE + rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)+1); +#else + rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); +#endif + rtc_write (RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday)); + rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour)); + rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min )); + rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec )); + rtc_write(RTC_CONFIG_B,0x02); /* enables the RTC to update the regs */ + +} + +void rtc_reset (void) +{ + rtc_write(RTC_CONFIG_B,0x82); /* disables the RTC to update the regs */ + rtc_write(RTC_CONFIG_A,0x20); /* Normal OP */ + rtc_write(RTC_CONFIG_B,0x00); + rtc_write(RTC_CONFIG_B,0x00); + rtc_write(RTC_CONFIG_B,0x02); /* enables the RTC to update the regs */ +} + +/* ------------------------------------------------------------------------- */ + +#ifdef CFG_RTC_REG_BASE_ADDR +/* + * use direct memory access + */ +static uchar rtc_read (uchar reg) +{ + return(in8(CFG_RTC_REG_BASE_ADDR+reg)); +} + +static void rtc_write (uchar reg, uchar val) +{ + out8(CFG_RTC_REG_BASE_ADDR+reg, val); +} +#else +static uchar rtc_read (uchar reg) +{ + out8(RTC_PORT_MC146818,reg); + return(in8(RTC_PORT_MC146818+1)); +} + +static void rtc_write (uchar reg, uchar val) +{ + out8(RTC_PORT_MC146818,reg); + out8(RTC_PORT_MC146818+1,val); +} +#endif + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* CONFIG_RTC_MC146818 && CFG_CMD_DATE */ diff --git a/rtc/mk48t59.c b/rtc/mk48t59.c new file mode 100644 index 0000000..64f751f --- /dev/null +++ b/rtc/mk48t59.c @@ -0,0 +1,237 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the MK48T59 RTC + */ + +#undef RTC_DEBUG + +#include +#include +#include +#include +#include + +#if defined(CONFIG_RTC_MK48T59) + +#if defined(CONFIG_BAB7xx) + +static uchar rtc_read (short reg) +{ + out8(RTC_PORT_ADDR0, reg & 0xFF); + out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF); + return in8(RTC_PORT_DATA); +} + +static void rtc_write (short reg, uchar val) +{ + out8(RTC_PORT_ADDR0, reg & 0xFF); + out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF); + out8(RTC_PORT_DATA, val); +} + +#elif defined(CONFIG_PCIPPC2) + +#include "../board/pcippc2/pcippc2.h" + +static uchar rtc_read (short reg) +{ + return in8(RTC(reg)); +} + +static void rtc_write (short reg, uchar val) +{ + out8(RTC(reg),val); +} + +#elif defined(CONFIG_AMIGAONEG3SE) + +#include "../board/MAI/AmigaOneG3SE/via686.h" +#include "../board/MAI/AmigaOneG3SE/memio.h" + + +static uchar rtc_read (short reg) +{ + out_byte(CMOS_ADDR, (uint8)reg); + return in_byte(CMOS_DATA); +} + +static void rtc_write (short reg, uchar val) +{ + out_byte(CMOS_ADDR, (uint8)reg); + out_byte(CMOS_DATA, (uint8)val); +} + +#elif defined(CONFIG_EVAL5200) + +static uchar rtc_read (short reg) +{ + return in8(RTC(reg)); +} + +static void rtc_write (short reg, uchar val) +{ + out8(RTC(reg),val); +} + +#else +# error Board specific rtc access functions should be supplied +#endif + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +/* ------------------------------------------------------------------------- */ + +void *nvram_read(void *dest, const short src, size_t count) +{ + uchar *d = (uchar *) dest; + short s = src; + + while (count--) + *d++ = rtc_read(s++); + + return dest; +} + +void nvram_write(short dest, const void *src, size_t count) +{ + short d = dest; + uchar *s = (uchar *) src; + + while (count--) + rtc_write(d++, *s++); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar save_ctrl_a; + uchar sec, min, hour, mday, wday, mon, year; + + /* Simple: freeze the clock, read it and allow updates again */ + save_ctrl_a = rtc_read(RTC_CONTROLA); + + /* Set the register to read the value. */ + save_ctrl_a |= RTC_CA_READ; + rtc_write(RTC_CONTROLA, save_ctrl_a); + + sec = rtc_read (RTC_SECONDS); + min = rtc_read (RTC_MINUTES); + hour = rtc_read (RTC_HOURS); + mday = rtc_read (RTC_DAY_OF_MONTH); + wday = rtc_read (RTC_DAY_OF_WEEK); + mon = rtc_read (RTC_MONTH); + year = rtc_read (RTC_YEAR); + + /* re-enable update */ + save_ctrl_a &= ~RTC_CA_READ; + rtc_write(RTC_CONTROLA, save_ctrl_a); + +#ifdef RTC_DEBUG + printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, + hour, min, sec ); +#endif + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon & 0x1F); + tmp->tm_year = bcd2bin (year); + tmp->tm_wday = bcd2bin (wday & 0x07); + if(tmp->tm_year<70) + tmp->tm_year+=2000; + else + tmp->tm_year+=1900; + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif +} + +void rtc_set (struct rtc_time *tmp) +{ + uchar save_ctrl_a; + +#ifdef RTC_DEBUG + printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + save_ctrl_a = rtc_read(RTC_CONTROLA); + + save_ctrl_a |= RTC_CA_WRITE; + rtc_write(RTC_CONTROLA, save_ctrl_a); /* disables the RTC to update the regs */ + + rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100)); + rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon)); + + rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); + rtc_write (RTC_DAY_OF_MONTH, bin2bcd(tmp->tm_mday)); + rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour)); + rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min )); + rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec )); + + save_ctrl_a &= ~RTC_CA_WRITE; + rtc_write(RTC_CONTROLA, save_ctrl_a); /* enables the RTC to update the regs */ +} + +void rtc_reset (void) +{ + uchar control_b; + + /* + * Start oscillator here. + */ + control_b = rtc_read(RTC_CONTROLB); + + control_b &= ~RTC_CB_STOP; + rtc_write(RTC_CONTROLB, control_b); +} + +void rtc_set_watchdog(short multi, short res) +{ + uchar wd_value; + + wd_value = RTC_WDS | ((multi & 0x1F) << 2) | (res & 0x3); + rtc_write(RTC_WATCHDOG, wd_value); +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_DATE) */ +#endif /* CONFIG_RTC_MK48T59 */ diff --git a/rtc/mpc5xxx.c b/rtc/mpc5xxx.c new file mode 100644 index 0000000..2053df1 --- /dev/null +++ b/rtc/mpc5xxx.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2004 + * Reinhard Meyer, EMK Elektronik GmbH + * r.meyer@emk-elektronik.de + * www.emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/***************************************************************************** + * Date & Time support for internal RTC of MPC52xx + *****************************************************************************/ +/*#define DEBUG*/ + +#include +#include +#include + +#if defined(CONFIG_RTC_MPC5200) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +/***************************************************************************** + * this structure should be defined in mpc5200.h ... + *****************************************************************************/ +typedef struct rtc5200 { + volatile ulong tsr; /* MBAR+0x800: time set register */ + volatile ulong dsr; /* MBAR+0x804: data set register */ + volatile ulong nysr; /* MBAR+0x808: new year and stopwatch register */ + volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */ + volatile ulong ctr; /* MBAR+0x810: current time register */ + volatile ulong cdr; /* MBAR+0x814: current data register */ + volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interupt register */ + volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */ + volatile ulong trdr; /* MBAR+0x820: test register/divides register */ +} RTC5200; + +#define RTC_SET 0x02000000 +#define RTC_PAUSE 0x01000000 + +/***************************************************************************** + * get time + *****************************************************************************/ +void rtc_get (struct rtc_time *tmp) +{ + RTC5200 *rtc = (RTC5200 *) (CFG_MBAR+0x800); + ulong time, date, time2; + + /* read twice to avoid getting a funny time when the second is just changing */ + do { + time = rtc->ctr; + date = rtc->cdr; + time2 = rtc->ctr; + } while (time != time2); + + tmp->tm_year = date & 0xfff; + tmp->tm_mon = (date >> 24) & 0xf; + tmp->tm_mday = (date >> 16) & 0x1f; + tmp->tm_wday = (date >> 21) & 7; + /* sunday is 7 in 5200 but 0 in rtc_time */ + if (tmp->tm_wday == 7) + tmp->tm_wday = 0; + tmp->tm_hour = (time >> 16) & 0x1f; + tmp->tm_min = (time >> 8) & 0x3f; + tmp->tm_sec = time & 0x3f; + + debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +/***************************************************************************** + * set time + *****************************************************************************/ +void rtc_set (struct rtc_time *tmp) +{ + RTC5200 *rtc = (RTC5200 *) (CFG_MBAR+0x800); + ulong time, date, year; + + debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + time = (tmp->tm_hour << 16) | (tmp->tm_min << 8) | tmp->tm_sec; + date = (tmp->tm_mon << 16) | tmp->tm_mday; + if (tmp->tm_wday == 0) + date |= (7 << 8); + else + date |= (tmp->tm_wday << 8); + year = tmp->tm_year; + + /* mask unwanted bits that might show up when rtc_time is corrupt */ + time &= 0x001f3f3f; + date &= 0x001f071f; + year &= 0x00000fff; + + /* pause and set the RTC */ + rtc->nysr = year; + rtc->dsr = date | RTC_PAUSE; + udelay (1000); + rtc->dsr = date | RTC_PAUSE | RTC_SET; + udelay (1000); + rtc->dsr = date | RTC_PAUSE; + udelay (1000); + rtc->dsr = date; + udelay (1000); + + rtc->tsr = time | RTC_PAUSE; + udelay (1000); + rtc->tsr = time | RTC_PAUSE | RTC_SET; + udelay (1000); + rtc->tsr = time | RTC_PAUSE; + udelay (1000); + rtc->tsr = time; + udelay (1000); +} + +/***************************************************************************** + * reset rtc circuit + *****************************************************************************/ +void rtc_reset (void) +{ + return; /* nothing to do */ +} + +#endif /* CONFIG_RTC_MPC5200 && CFG_CMD_DATE */ diff --git a/rtc/mpc8xx.c b/rtc/mpc8xx.c new file mode 100644 index 0000000..830e56e --- /dev/null +++ b/rtc/mpc8xx.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for internal RTC of MPC8xx + */ + +/*#define DEBUG*/ + +#include +#include +#include + +#if defined(CONFIG_RTC_MPC8xx) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + ulong tim; + + tim = immr->im_sit.sit_rtc; + + to_tm (tim, tmp); + + debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +void rtc_set (struct rtc_time *tmp) +{ + volatile immap_t *immr = (immap_t *)CFG_IMMR; + ulong tim; + + debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + immr->im_sitk.sitk_rtck = KAPWR_KEY; + immr->im_sit.sit_rtc = tim; +} + +void rtc_reset (void) +{ + return; /* nothing to do */ +} + +/* ------------------------------------------------------------------------- */ + +#endif /* CONFIG_RTC_MPC8xx && CFG_CMD_DATE */ diff --git a/rtc/pcf8563.c b/rtc/pcf8563.c new file mode 100644 index 0000000..05ae97e --- /dev/null +++ b/rtc/pcf8563.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for Philips PCF8563 RTC + */ + +/* #define DEBUG */ + +#include +#include +#include +#include + +#if defined(CONFIG_RTC_PCF8563) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +static uchar rtc_read (uchar reg); +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin(uchar c); + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon_cent, year; + + sec = rtc_read (0x02); + min = rtc_read (0x03); + hour = rtc_read (0x04); + mday = rtc_read (0x05); + wday = rtc_read (0x06); + mon_cent= rtc_read (0x07); + year = rtc_read (0x08); + + debug ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon_cent, mday, wday, + hour, min, sec ); + debug ( "Alarms: wday: %02x day: %02x hour: %02x min: %02x\n", + rtc_read (0x0C), + rtc_read (0x0B), + rtc_read (0x0A), + rtc_read (0x09) ); + + if (sec & 0x80) { + puts ("### Warning: RTC Low Voltage - date/time not reliable\n"); + } + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon_cent & 0x1F); + tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); + tmp->tm_wday = bcd2bin (wday & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +void rtc_set (struct rtc_time *tmp) +{ + uchar century; + + debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + rtc_write (0x08, bin2bcd(tmp->tm_year % 100)); + + century = (tmp->tm_year >= 2000) ? 0x80 : 0; + rtc_write (0x07, bin2bcd(tmp->tm_mon) | century); + + rtc_write (0x06, bin2bcd(tmp->tm_wday)); + rtc_write (0x05, bin2bcd(tmp->tm_mday)); + rtc_write (0x04, bin2bcd(tmp->tm_hour)); + rtc_write (0x03, bin2bcd(tmp->tm_min )); + rtc_write (0x02, bin2bcd(tmp->tm_sec )); +} + +void rtc_reset (void) +{ + /* clear all control & status registers */ + rtc_write (0x00, 0x00); + rtc_write (0x01, 0x00); + rtc_write (0x0D, 0x00); + + /* clear Voltage Low bit */ + rtc_write (0x02, rtc_read (0x02) & 0x7F); + + /* reset all alarms */ + rtc_write (0x09, 0x00); + rtc_write (0x0A, 0x00); + rtc_write (0x0B, 0x00); + rtc_write (0x0C, 0x00); +} + +/* ------------------------------------------------------------------------- */ + +static uchar rtc_read (uchar reg) +{ + return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); +} + +static void rtc_write (uchar reg, uchar val) +{ + i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* CONFIG_RTC_PCF8563 && CFG_CMD_DATE */ diff --git a/rtc/rs5c372.c b/rtc/rs5c372.c new file mode 100644 index 0000000..87f38c4 --- /dev/null +++ b/rtc/rs5c372.c @@ -0,0 +1,302 @@ +/* + * rs5c372.c + * + * Device driver for Ricoh's Real Time Controller RS5C372A. + * + * Copyright (C) 2004 Gary Jennejohn garyj@denx.de + * + * Based in part in ds1307.c - + * (C) Copyright 2001, 2002, 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Keith Outwater, keith_outwater@mvis.com` + * Steven Scholz, steven.scholz@imc-berlin.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if defined(CONFIG_RTC_RS5C372A) && (CONFIG_COMMANDS & CFG_CMD_DATE) +/* + * Reads are always done starting with register 15, which requires some + * jumping-through-hoops to access the data correctly. + * + * Writes are always done starting with register 0. + */ + +#define DEBUG 0 + +#if DEBUG +static unsigned int rtc_debug = DEBUG; +#else +#define rtc_debug 0 /* gcc will remove all the debug code for us */ +#endif + +#ifndef CFG_I2C_RTC_ADDR +#define CFG_I2C_RTC_ADDR 0x32 +#endif + +#define RS5C372_RAM_SIZE 0x10 +#define RATE_32000HZ 0x80 /* Rate Select 32.000KHz */ +#define RATE_32768HZ 0x00 /* Rate Select 32.768KHz */ + +#define STATUS_XPT 0x10 /* data invalid because voltage was 0 */ + +#define USE_24HOUR_MODE 0x20 +#define TWELVE_HOUR_MODE(n) ((((n) >> 5) & 1) == 0) +#define HOURS_AP(n) (((n) >> 5) & 1) +#define HOURS_12(n) bcd2bin((n) & 0x1F) +#define HOURS_24(n) bcd2bin((n) & 0x3F) + + +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin (uchar c); + +static int setup_done = 0; + +static int +rs5c372_readram(char *buf, int len) +{ + int ret; + + ret = i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, len); + if (ret != 0) { + printf("%s: failed to read\n", __FUNCTION__); + return ret; + } + + if (buf[0] & STATUS_XPT) + printf("### Warning: RTC lost power\n"); + + return ret; +} + +static void +rs5c372_enable(void) +{ + unsigned char buf[RS5C372_RAM_SIZE + 1]; + int ret; + + /* note that this returns reg. 15 in buf[1] */ + ret = rs5c372_readram(&buf[1], RS5C372_RAM_SIZE); + if (ret != 0) { + printf("%s: failed\n", __FUNCTION__); + return; + } + + buf[0] = 0; + /* we want to start writing at register 0 so we have to copy the */ + /* register contents up one slot */ + for (ret = 2; ret < 9; ret++) + buf[ret - 1] = buf[ret]; + /* registers 0 to 6 (time values) are not touched */ + buf[8] = RATE_32768HZ; /* reg. 7 */ + buf[9] = 0; /* reg. 8 */ + buf[10] = 0; /* reg. 9 */ + buf[11] = 0; /* reg. 10 */ + buf[12] = 0; /* reg. 11 */ + buf[13] = 0; /* reg. 12 */ + buf[14] = 0; /* reg. 13 */ + buf[15] = 0; /* reg. 14 */ + buf[16] = USE_24HOUR_MODE; /* reg. 15 */ + ret = i2c_write(CFG_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); + if (ret != 0) { + printf("%s: failed\n", __FUNCTION__); + return; + } + setup_done = 1; + + return; +} + +static void +rs5c372_convert_to_time(struct rtc_time *dt, char *buf) +{ + /* buf[0] is register 15 */ + dt->tm_sec = bcd2bin(buf[1]); + dt->tm_min = bcd2bin(buf[2]); + + if (TWELVE_HOUR_MODE(buf[0])) { + dt->tm_hour = HOURS_12(buf[3]); + if (HOURS_AP(buf[3])) /* PM */ + dt->tm_hour += 12; + } else /* 24-hour-mode */ + dt->tm_hour = HOURS_24(buf[3]); + + dt->tm_mday = bcd2bin(buf[5]); + dt->tm_mon = bcd2bin(buf[6]); + dt->tm_year = bcd2bin(buf[7]); + if (dt->tm_year >= 70) + dt->tm_year += 1900; + else + dt->tm_year += 2000; + /* 0 is Sunday */ + dt->tm_wday = bcd2bin(buf[4] & 0x07); + dt->tm_yday = 0; + dt->tm_isdst= 0; + + if(rtc_debug > 2) { + printf("rs5c372_convert_to_time: year = %d\n", dt->tm_year); + printf("rs5c372_convert_to_time: mon = %d\n", dt->tm_mon); + printf("rs5c372_convert_to_time: mday = %d\n", dt->tm_mday); + printf("rs5c372_convert_to_time: hour = %d\n", dt->tm_hour); + printf("rs5c372_convert_to_time: min = %d\n", dt->tm_min); + printf("rs5c372_convert_to_time: sec = %d\n", dt->tm_sec); + } +} + +/* + * Get the current time from the RTC + */ +void +rtc_get (struct rtc_time *tmp) +{ + unsigned char buf[RS5C372_RAM_SIZE]; + int ret; + + if (!setup_done) + rs5c372_enable(); + + if (!setup_done) + return; + + memset(buf, 0, sizeof(buf)); + + /* note that this returns reg. 15 in buf[0] */ + ret = rs5c372_readram(buf, RS5C372_RAM_SIZE); + if (ret != 0) { + printf("%s: failed\n", __FUNCTION__); + return; + } + + rs5c372_convert_to_time(tmp, buf); + + return; +} + +/* + * Set the RTC + */ +void +rtc_set (struct rtc_time *tmp) +{ + unsigned char buf[8], reg15; + int ret; + + if (!setup_done) + rs5c372_enable(); + + if (!setup_done) + return; + + if(rtc_debug > 2) { + printf("rtc_set: tm_year = %d\n", tmp->tm_year); + printf("rtc_set: tm_mon = %d\n", tmp->tm_mon); + printf("rtc_set: tm_mday = %d\n", tmp->tm_mday); + printf("rtc_set: tm_hour = %d\n", tmp->tm_hour); + printf("rtc_set: tm_min = %d\n", tmp->tm_min); + printf("rtc_set: tm_sec = %d\n", tmp->tm_sec); + } + + memset(buf, 0, sizeof(buf)); + + /* only read register 15 */ + ret = i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, 1); + + if (ret == 0) { + /* need to save register 15 */ + reg15 = buf[0]; + buf[0] = 0; /* register address on RS5C372 */ + buf[1] = bin2bcd(tmp->tm_sec); + buf[2] = bin2bcd(tmp->tm_min); + /* need to handle 12 hour mode */ + if (TWELVE_HOUR_MODE(reg15)) { + if (tmp->tm_hour >= 12) { /* PM */ + /* 12 PM is a special case */ + if (tmp->tm_hour == 12) + buf[3] = bin2bcd(tmp->tm_hour); + else + buf[3] = bin2bcd(tmp->tm_hour - 12); + buf[3] |= 0x20; + } + } else { + buf[3] = bin2bcd(tmp->tm_hour); + } + + buf[4] = bin2bcd(tmp->tm_wday); + buf[5] = bin2bcd(tmp->tm_mday); + buf[6] = bin2bcd(tmp->tm_mon); + if (tmp->tm_year < 1970 || tmp->tm_year > 2069) + printf("WARNING: year should be between 1970 and 2069!\n"); + buf[7] = bin2bcd(tmp->tm_year % 100); + + ret = i2c_write(CFG_I2C_RTC_ADDR, 0, 0, buf, 8); + if (ret != 0) + printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret); + } + + return; +} + +/* + * Reset the RTC. We set the date back to 1970-01-01. + */ +void +rtc_reset (void) +{ + struct rtc_time tmp; + + if (!setup_done) + rs5c372_enable(); + + if (!setup_done) + return; + + tmp.tm_year = 1970; + tmp.tm_mon = 1; + /* Jan. 1, 1970 was a Thursday */ + tmp.tm_wday= 4; + tmp.tm_mday= 1; + tmp.tm_hour = 0; + tmp.tm_min = 0; + tmp.tm_sec = 0; + + rtc_set(&tmp); + + printf ("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", + tmp.tm_year, tmp.tm_mon, tmp.tm_mday, + tmp.tm_hour, tmp.tm_min, tmp.tm_sec); + + return; +} + +static unsigned int +bcd2bin (unsigned char n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char +bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} +#endif /* defined(CONFIG_RTC_RS5C372A) && (CONFIG_COMMANDS & CFG_CMD_DATE) */ diff --git a/rtc/s3c24x0_rtc.c b/rtc/s3c24x0_rtc.c new file mode 100644 index 0000000..9e2191e --- /dev/null +++ b/rtc/s3c24x0_rtc.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the built-in Samsung S3C24X0 RTC + */ + +#include +#include + +#if defined(CONFIG_RTC_S3C24X0) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +#if defined(CONFIG_S3C2400) +#include +#elif defined(CONFIG_S3C2410) +#include +#endif + +#include + +/*#define DEBUG*/ + +typedef enum { + RTC_ENABLE, + RTC_DISABLE +} RTC_ACCESS; + + +static inline void SetRTC_Access(RTC_ACCESS a) +{ + S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC(); + switch (a) { + case RTC_ENABLE: + rtc->RTCCON |= 0x01; break; + + case RTC_DISABLE: + rtc->RTCCON &= ~0x01; break; + } +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +/* ------------------------------------------------------------------------- */ + +void rtc_get (struct rtc_time *tmp) +{ + S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC(); + uchar sec, min, hour, mday, wday, mon, year; + uchar a_sec,a_min, a_hour, a_date, a_mon, a_year, a_armed; + + /* enable access to RTC registers */ + SetRTC_Access(RTC_ENABLE); + + /* read RTC registers */ + do { + sec = rtc->BCDSEC; + min = rtc->BCDMIN; + hour = rtc->BCDHOUR; + mday = rtc->BCDDATE; + wday = rtc->BCDDAY; + mon = rtc->BCDMON; + year = rtc->BCDYEAR; + } while (sec != rtc->BCDSEC); + + /* read ALARM registers */ + a_sec = rtc->ALMSEC; + a_min = rtc->ALMMIN; + a_hour = rtc->ALMHOUR; + a_date = rtc->ALMDATE; + a_mon = rtc->ALMMON; + a_year = rtc->ALMYEAR; + a_armed = rtc->RTCALM; + + /* disable access to RTC registers */ + SetRTC_Access(RTC_DISABLE); + +#ifdef RTC_DEBUG + printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, + hour, min, sec); + printf ( "Alarms: %02x: year: %02x month: %02x date: %02x hour: %02x min: %02x sec: %02x\n", + a_armed, + a_year, a_mon, a_date, + a_hour, a_min, a_sec); +#endif + + tmp->tm_sec = bcd2bin(sec & 0x7F); + tmp->tm_min = bcd2bin(min & 0x7F); + tmp->tm_hour = bcd2bin(hour & 0x3F); + tmp->tm_mday = bcd2bin(mday & 0x3F); + tmp->tm_mon = bcd2bin(mon & 0x1F); + tmp->tm_year = bcd2bin(year); + tmp->tm_wday = bcd2bin(wday & 0x07); + if(tmp->tm_year<70) + tmp->tm_year+=2000; + else + tmp->tm_year+=1900; + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif +} + +void rtc_set (struct rtc_time *tmp) +{ + S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC(); + uchar sec, min, hour, mday, wday, mon, year; + +#ifdef RTC_DEBUG + printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + year = bin2bcd(tmp->tm_year % 100); + mon = bin2bcd(tmp->tm_mon); + wday = bin2bcd(tmp->tm_wday); + mday = bin2bcd(tmp->tm_mday); + hour = bin2bcd(tmp->tm_hour); + min = bin2bcd(tmp->tm_min); + sec = bin2bcd(tmp->tm_sec); + + /* enable access to RTC registers */ + SetRTC_Access(RTC_ENABLE); + + /* write RTC registers */ + rtc->BCDSEC = sec; + rtc->BCDMIN = min; + rtc->BCDHOUR = hour; + rtc->BCDDATE = mday; + rtc->BCDDAY = wday; + rtc->BCDMON = mon; + rtc->BCDYEAR = year; + + /* disable access to RTC registers */ + SetRTC_Access(RTC_DISABLE); +} + +void rtc_reset (void) +{ + S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC(); + + rtc->RTCCON = (rtc->RTCCON & ~0x06) | 0x08; + rtc->RTCCON &= ~(0x08|0x01); +} + +/* ------------------------------------------------------------------------- */ + +#endif /* CONFIG_RTC_S3C24X0 && CFG_CMD_DATE */ diff --git a/tools/Makefile b/tools/Makefile new file mode 100644 index 0000000..d3dcc7d --- /dev/null +++ b/tools/Makefile @@ -0,0 +1,208 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +BINS = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) + +OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o + +ifeq ($(ARCH),mips) +BINS += inca-swap-bytes$(SFX) +OBJS += inca-swap-bytes.o +endif + +# Don't build by default +#ifeq ($(ARCH),ppc) +#BINS += mpc86x_clk$(SFX) +#OBJS += mpc86x_clk.o +#endif + +LOGO_H = $(TOPDIR)/include/bmp_logo.h + +ifeq ($(LOGO_BMP),) +LOGO_BMP= logos/denx.bmp +endif + +#------------------------------------------------------------------------- + +HOSTARCH := $(shell uname -m | \ + sed -e s/i.86/i386/ \ + -e s/sun4u/sparc64/ \ + -e s/arm.*/arm/ \ + -e s/sa110/arm/ \ + -e s/powerpc/ppc/ \ + -e s/Power\ Macintosh/ppc/ \ + -e s/macppc/ppc/) + +HOSTOS := $(shell uname -s | tr A-Z a-z | \ + sed -e 's/\(cygwin\).*/cygwin/') + +TOOLSUBDIRS = + +# +# Mac OS X / Darwin's C preprocessor is Apple specific. It +# generates numerous errors and warnings. We want to bypass it +# and use GNU C's cpp. To do this we pass the -traditional-cpp +# option to the compiler. Note that the -traditional-cpp flag +# DOES NOT have the same semantics as GNU C's flag, all it does +# is invoke the GNU preprocessor in stock ANSI/ISO C fashion. +# +# Apple's linker is similar, thanks to the new 2 stage linking +# multiple symbol definitions are treated as errors, hence the +# -multiply_defined suppress option to turn off this error. +# +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +HOST_CFLAGS = -traditional-cpp -Wall +HOST_LDFLAGS =-multiply_defined suppress +HOST_ENVIRO_CFLAGS = -traditional-cpp + +else +ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc) +HOST_CFLAGS = -Wall -pedantic +HOST_LDFLAGS = +HOST_ENVIRO_CFLAGS = + +# +# Everyone else +# +else +HOST_CFLAGS = -Wall -pedantic +HOST_LDFLAGS = +HOST_ENVIRO_CFLAGS = +endif +endif + +# +# Cygwin needs .exe files :-( +# +ifeq ($(HOSTOS),cygwin) +SFX = .exe +else +SFX = +endif + +# +# Include this after HOSTOS HOSTARCH check +# so that we can act intelligently. +# +include $(TOPDIR)/config.mk + +# +# Use native tools and options +# +CPPFLAGS = -idirafter ../include -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC +CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O +AFLAGS = -D__ASSEMBLY__ $(CPPFLAGS) +CC = $(HOSTCC) +STRIP = $(HOSTSTRIP) +MAKEDEPEND = makedepend + +all: .depend $(BINS) $(LOGO_H) subdirs + +envcrc$(SFX): envcrc.o crc32.o environment.o + $(CC) $(CFLAGS) -o $@ $^ + +img2srec$(SFX): img2srec.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + +mkimage$(SFX): mkimage.o crc32.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + +ncb$(SFX): ncb.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + +gen_eth_addr$(SFX): gen_eth_addr.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + +bmp_logo$(SFX): bmp_logo.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + +inca-swap-bytes$(SFX): inca-swap-bytes.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + +mpc86x_clk$(SFX): mpc86x_clk.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + +envcrc.o: envcrc.c + $(CC) -g $(CFLAGS) -c $< + +crc32.o: crc32.c + $(CC) -g $(CFLAGS) -c $< + +mkimage.o: mkimage.c + $(CC) -g $(CFLAGS) -c $< + +ncb.o: ncb.c + $(CC) -g $(CFLAGS) -c $< + +gen_eth_addr.o: gen_eth_addr.c + $(CC) -g $(CFLAGS) -c $< + +inca-swap-bytes.o: inca-swap-bytes.c + $(CC) -g $(CFLAGS) -c $< + +mpc86x_clk.o: mpc86x_clk.c + $(CC) -g $(CFLAGS) -c $< + +subdirs: +ifeq ($(TOOLSUBDIRS),) + @: +else + @for dir in $(TOOLSUBDIRS) ; do \ + $(MAKE) \ + HOSTOS=$(HOSTOS) \ + HOSTARCH=$(HOSTARCH) \ + HOST_CFLAGS="$(HOST_CFLAGS)" \ + HOST_LDFLAGS="$(HOST_LDFLAGS)" \ + -C $$dir || exit 1 ; \ + done +endif + +environment.c: + @rm -f environment.c + ln -s ../common/environment.c environment.c + +environment.o: environment.c + $(CC) -g $(HOST_ENVIRO_CFLAGS) $(CPPFLAGS) -c $< + +crc32.c: + @rm -f crc32.c + ln -s ../lib_generic/crc32.c crc32.c + +$(LOGO_H): bmp_logo $(LOGO_BMP) + ./bmp_logo $(LOGO_BMP) >$@ + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/tools/Makefile.win32 b/tools/Makefile.win32 new file mode 100644 index 0000000..69dc44c --- /dev/null +++ b/tools/Makefile.win32 @@ -0,0 +1,37 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CPPFLAGS = -Wall -pedantic -I../include -I.. -D__WIN32__ +CFLAGS = $(CPPFLAGS) -O + +all: mkimage.exe + +mkimage.exe: mkimage.o crc32.o + $(CC) -g $(CFLAGS) -o $@ $^ + +crc32.o: crc32.c + $(CC) -g $(CFLAGS) -c $< + +mkimage.o: mkimage.c + $(CC) -g $(CFLAGS) -c $< + diff --git a/tools/bddb/README b/tools/bddb/README new file mode 100644 index 0000000..9bee59a --- /dev/null +++ b/tools/bddb/README @@ -0,0 +1,116 @@ +Hymod Board Database + +(C) Copyright 2001 +Murray Jensen +CSIRO Manufacturing Science and Technology, Preston Lab + +25-Jun-01 + +This stuff is a set of PHP/MySQL scripts to implement a custom board +database. It will need *extensive* hacking to modify it to keep the +information about your custom boards that you want, however it is a good +starting point. + +How it is used: + + 1. a board has gone through all the hardware testing etc and is + ready to have the flash programmed for the first time - first you + go to a web page and fill in information about the board in a form + to register it in a database + + 2. the web stuff allocates a (unique) serial number and (optionally) + a (locally administered) ethernet address and stores the information + in a database using the serial number as the key (can do whole + batches of boards in one go and/or use a previously registered board + as defaults for the new board(s)) + + 3. it then creates a file in the tftp area of a server somewhere + containing the board information in a simple text format (one + per serial number) + + 4. all hymod boards have an i2c eeprom, and when U-Boot sees that + the eeprom is unitialised, it prompts for a serial number and + ethernet address (if not set), then transfers the file created + in step 3 from the server and initialises the eeprom from its + contents + +What this means is you can't boot the board until you have allocated a serial +number, but you don't have to type it all twice - you do it once on the web +and the board then finds the info it needs to initialise its eeprom. The +other side of the coin is the reading of the eeprom and how it gets passed +to Linux (or another O/S). + +To see how this is all done for the hymod boards look at the code in the +"board/hymod" directory and in the file "include/asm/hymod.h". Hymod boards +can have a mezzanine card which also have an eeprom that needs allocating, +the same process is used for these as well - just a different i2c address. + +Other forms provide the following functions: + + - browsing the board database + - editing board information (one at a time) + - maintaining/browsing a (simple) per board event log + +You will need: MySQL (I use version 3.23.7-alpha), PHP4 (with MySQL +support enabled) and a web server (I use Apache 1.3.x). + +I originally started by using phpMyBuilder (http://kyber.dk/phpMyBuilder) +but it soon got far more complicated than that could handle (but I left +the copyright messages in there anyway). Most of the code resides in the +common defs.php file, which shouldn't need much alteration - all the work +will be in shaping the front-end php files to your liking. + +Here's a quick summary of what needs doing to use it for your boards: + +1. get phpMyAdmin (http://phpwizard.net/projects/phpMyAdmin/) - it's an + invaluable tool for this sort of stuff (this step is optional of course) + +2. edit "bddb.css" to your taste, if you could be bothered - I have no + idea what is in there or what it does - I copied it from somewhere else + ("user.css" from the phpMyEdit (http://phpmyedit.sourcerforge.net) package, + I think) - I figure one day I'll see what sort of things I can change + in there. + +3. create a mysql database - call it whatever you like + +4. edit "create_tables.sql" and modify the "boards" table schema to + reflect the information you want to keep about your boards. It may or + may not be easier to do this and the next step in phpMyAdmin. Check out + the MySQL documentation at http://www.mysql.com/doc/ in particular the + column types at http://www.mysql.com/doc/C/o/Column_types.html - Note + there is only support for a few data types: + + int - presented as an html text input + char/text - presented as an html text input + date - presented as an html text input + enum - presented as an html radio input + + I also have what I call "enum_multi" which is a set of enums with the + same name, but suffixed with a number e.g. fred0, fred1, fred2. These + are presented as a number of html select's with a single label "fred" + this is useful for board characteristics that have multiple items of + the same type e.g. multiple banks of sdram. + +5. use the "create_tables.sql" file to create the "boards" table in the + database e.g. mysql dbname < create_tables.sql + +6. create a user and password for the web server to log into the MySQL + database with; give this user select, insert and update privileges + to the database created in 3 (and delete, if you want the "delete" + functions in the edit forms to work- I have this turned off). phpMyAdmin + helps in this step. + +7. edit "config.php" and set the variables: $mysql_user, $mysql_pw, $mysql_db, + $bddb_cfgdir and $bddb_label - keep the contents of this file secret - it + contains the web servers username and password (the three $mysql_* vars + are set from the previous step) + +8. edit "defs.php" and a. adjust the various enum value arrays and b. edit + the function "pg_foot()" to remove my email address :-) + +9. do major hacking on the following files: browse.php, doedit.php, donew.php, + edit.php and new.php to reflect your database schema - fortunately the + hacking is fairly straight-forward, but it is boring and time-consuming. + +These notes were written rather hastily - if you find any obvious problems +please let me know. diff --git a/tools/bddb/badsubmit.php b/tools/bddb/badsubmit.php new file mode 100644 index 0000000..5092a31 --- /dev/null +++ b/tools/bddb/badsubmit.php @@ -0,0 +1,23 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + require("defs.php"); + pg_head("$bddb_label - Unknown Submit Type"); +?> +
+ + + The form was submitted with an + unknown SUBMIT type . +

+ Perhaps you typed the URL in directly? Click here to go to the + home page of the . + + +
+ diff --git a/tools/bddb/bddb.css b/tools/bddb/bddb.css new file mode 100644 index 0000000..dee2b2e --- /dev/null +++ b/tools/bddb/bddb.css @@ -0,0 +1,207 @@ +BODY { + background: #e0ffff; + color: #000000; + font-family: Arial, Verdana, Helvetica; +} +H1 { + font-family: "Copperplate Gothic Bold"; + background: transparent; + color: #993300; + text-align: center; +} +H2, H3, H4, H5 { + background: transparent; + color: #993300; + margin-top: 4%; + text-align: center; +} +Body.Plain Div.Abstract, Body.Plain P.Abstract { + background: #cccc99; + color: #333300; + border: white; + padding: 3%; + font-family: Times, Verdana; +} +TH.Nav { + background: #0000cc; + color: #ff9900; +} +TH.Menu { + background: #3366cc; + color: #ff9900; +} +A:hover { + color: #ff6600; +} +A.Menu:hover { + color: #ff6600; +} +A.HoMe:hover { + color: #ff6600; +} +A.Menu { + background: transparent; + color: #ffcc33; + font-family: Verdana, Helvetica, Arial; + font-size: smaller; + text-decoration: none; +} +A.Menu:visited { + background: transparent; + color: #ffcc99; +} +A.HoMe { + background: transparent; + color: #ffcc33; + font-family: Verdana, Helvetica, Arial; + text-decoration:none; +} +A.HoMe:visited { + background: transparent; + color: #ffcc99; +} +TH.Xmp { + background: #eeeeee; + color: #330066; + font-family: courier; + font-weight: normal; +} +TH.LuT { + background: #cccccc; + color: #000000; +} +TD.LuT { + background: #ffffcc; + color: #000000; + font-size: 85%; +} +TH.Info, TD.Info { + background: #ffffcc; + color: #660000; + font-family: "Comic Sans MS", Cursive, Verdana; + font-size: smaller; +} +Div.Info, P.Info { + background: #ffff99; + color: #990033; + text-align: left; + padding: 2%; + font-family: "Comic Sans MS", Cursive, Verdana; + font-size: 85%; + } +Div.Info A { + background: transparent; + color: #ff6600; +} +.HL { + background: #ffff99; + color: #000000; +} +TD.HL { + background: #ccffff; + color: #000000; +} +Div.Margins { + width: 512px; + text-align: center; +} +TD.Plain { + background: #ffffcc; + color: #000033; +} +.Type { + background: #cccccc; + color: #660000; +} +.Name { + background: #eeeeee; + color: #660000; + vertical-align: top; + text-align: right; +} +.Value { + background: #ffffee; + color: #000066; +} +.Drop { + background: #333366; + color: #ffcc33; + font-family: "Copperplate Gothic Light", Helvetica, Verdana, Arial; +} +A.Button:hover { + color: #ff6600; +} +A.Button { + text-decoration:none; + color: #003366; + background: #ffcc66; +} +.Button { + font-size: 9pt; + text-align: center; + text-decoration:none; + color: #003366; + background: #ffcc66; + margin-bottom: 2pt; + border-top: 2px solid #ffff99; + border-left: 2px solid #ffff99; + border-right: 2px solid #cc9933; + border-bottom: 2px solid #cc9933; + font-family: Verdana, Arial, "Comic Sans MS"; +} +.Banner { + width: 468; + font-size: 12pt; + text-align: center; + text-decoration:none; + color: #003366; + background: #ffcc66; + border-top: 4px solid #ffff99; + border-left: 4px solid #ffff99; + border-right: 4px solid #cc9933; + border-bottom: 4px solid #cc9933; + font-family: Verdana, Arial, "Comic Sans MS"; +} +TD.Nova, Body.Nova { + background: #000000; + font-family: "Times New Roman"; + font-weight: light; + color: #ffcc00; +} +Body.Nova A.Button { + background: gold; + color: #003366; +} +Body.Nova A.Banner { + background: transparent; + color: #003366; +} +Body.Nova A { + background: transparent; + text-decoration:none; + color: #ffd766; +} +Body.Nova H1, Body.Nova H2, Body.Nova H3, Body.Nova H4 { + background: transparent; + color: white; + margin-top: 4%; + text-align: center; + filter: Blur(Add=1, Direction=0, Strength=8); +} +Body.Nova Div.Abstract { + background: #000000; + color: #ffffff; + font-family: Times, Verdana; +} +Body.Nova A.Abstract { + background: transparent; + color: #ffeedd; +} +Body.Nova TH.LuT { + background: black; + color: #ffff99; +} +Body.Nova TD.LuT { + background: navy; + color: #ffff99; +} diff --git a/tools/bddb/brlog.php b/tools/bddb/brlog.php new file mode 100644 index 0000000..fccfbd0 --- /dev/null +++ b/tools/bddb/brlog.php @@ -0,0 +1,109 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // list page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - Browse Board Log"); + + $serno=intval($serno); + if ($serno == 0) + die("serial number not specified or invalid!"); + + function print_cell($str) { + if ($str == '') + $str = ' '; + echo "\t$str\n"; + } +?> + + + + + + + + + + +\n"; + print_cell("$row[serno]"); + print_cell($row['ethaddr']); + print_cell($row['date']); + print_cell($row['batch']); + print_cell($row['type']); + print_cell($row['rev']); + print_cell($row['location']); + echo "\n"; + } + + mysql_free_result($r); +?> +
serno / editethaddrdatebatchtyperevlocation
+
+

+$limit){ + $preoffset=max(0,$offset-$limit); + $postoffset=$offset+$limit; + echo "\n\n"; + printf("\n", $offset>0?"":"no", $PHP_SELF, $preoffset); + printf("\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset); + echo "\n
<%sa href=\"%s?submit=Log&serno=$serno&offset=%d\">\"<\"<%sa href=\"%s?submit=Log&serno=$serno&offset=%d\">\">\"
\n"; + } + mysql_free_result($lr); +?> + + + + + + + +\n"; + print_cell("$row[logno]"); + print_cell($row['date']); + print_cell($row['who']); + print_cell("
" . urldecode($row['details']) . "
"); + echo "\n"; + } + + mysql_free_result($r); +?> +
logno / editdatewhodetails
+
+

+ + + + + +
+ ">Add to Log + + Back to Start +
+ diff --git a/tools/bddb/browse.php b/tools/bddb/browse.php new file mode 100644 index 0000000..675dfab --- /dev/null +++ b/tools/bddb/browse.php @@ -0,0 +1,147 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // list page (hymod_bddb / boards) + + require("defs.php"); + + $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:''; + + $verbose=isset($_REQUEST['verbose'])?intval($_REQUEST['verbose']):0; + + pg_head("$bddb_label - Browse database" . ($verbose?" (verbose)":"")); +?> +

+$limit){ + $preoffset=max(0,$offset-$limit); + $postoffset=$offset+$limit; + echo "\n\n"; + printf("\n", $offset>0?"":"no", $PHP_SELF, $preoffset, $verbose); + printf("\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset, $offset); + echo "\n
<%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\">\"<\"<%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\">\">\"
\n"; + } + + mysql_free_result($lr); + } +?> + + + + + + + + + + +comments\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + echo "\n"; + } +?> + +=$m[1] and serno<=$m[2])"; + } + else + die("illegal serial number ($s)"); + $pre = " or "; + } + } + $query .= " order by serno"; + if ($serno == '') + $query .= " limit $offset,$limit"; + + $r = mysql_query($query); + + function print_cell($str) { + if ($str == '') + $str = ' '; + echo "\t\n"; + } + + while($row=mysql_fetch_array($r)){ + foreach ($columns as $key) { + if (!key_in_array($key, $row)) + $row[$key] = ''; + } + + echo "\n"; + print_cell("Log"); + print_cell("$row[serno]"); + print_cell($row['ethaddr']); + print_cell($row['date']); + print_cell($row['batch']); + print_cell($row['type']); + print_cell($row['rev']); + print_cell($row['location']); + if ($verbose) { + print_cell("
\n" . urldecode($row['comments']) .
+				"\n\t
"); + print_cell(gather_enum_multi_print("sdram", 4, $row)); + print_cell(gather_enum_multi_print("flash", 4, $row)); + print_cell(gather_enum_multi_print("zbt", 16, $row)); + print_cell(gather_enum_multi_print("xlxtyp", 4, $row)); + print_cell(gather_enum_multi_print("xlxspd", 4, $row)); + print_cell(gather_enum_multi_print("xlxtmp", 4, $row)); + print_cell(gather_enum_multi_print("xlxgrd", 4, $row)); + print_cell($row['cputyp']); + print_cell($row['cpuspd']); + print_cell($row['cpmspd']); + print_cell($row['busspd']); + print_cell($row['hstype']); + print_cell($row['hschin']); + print_cell($row['hschout']); + } + echo "\n"; + } +?> +
serno / editethaddrdatebatchtyperevlocationsdramflashzbtxlxtypxlxspdxlxtmpxlxgrdcputypcpuspdcpmspdbusspdhstypehschinhschout
$str
+

+ + + + + +
%s Listing\n", $PHP_SELF, $offset, $verbose?0:1, $serno!=''?"&serno=$serno":'', $verbose?"Terse":"Verbose"); + ?>Back to Start
+ diff --git a/tools/bddb/config.php b/tools/bddb/config.php new file mode 100644 index 0000000..6725757 --- /dev/null +++ b/tools/bddb/config.php @@ -0,0 +1,16 @@ + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // mysql database access info + $mysql_user="fred"; + $mysql_pw="apassword"; + $mysql_db="mydbname"; + + // where to put the eeprom config files + $bddb_cfgdir = '/tftpboot/bddb'; + + // what this database is called + $bddb_label = 'Hymod Board Database'; +?> diff --git a/tools/bddb/create_tables.sql b/tools/bddb/create_tables.sql new file mode 100644 index 0000000..a2a5788 --- /dev/null +++ b/tools/bddb/create_tables.sql @@ -0,0 +1,90 @@ +# phpMyAdmin MySQL-Dump +# http://phpwizard.net/phpMyAdmin/ +# +# Host: localhost Database : hymod_bddb + +# (C) Copyright 2001 +# Murray Jensen +# CSIRO Manufacturing and Infrastructure Technology, Preston Lab + +# -------------------------------------------------------- +# +# Table structure for table 'boards' +# + +DROP TABLE IF EXISTS boards; +CREATE TABLE boards ( + serno int(10) unsigned zerofill NOT NULL auto_increment, + ethaddr char(17), + date date NOT NULL, + batch char(32), + type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') NOT NULL, + rev tinyint(3) unsigned zerofill NOT NULL, + location char(64), + comments text, + sdram0 enum('32M','64M','128M','256M','512M','1G','2G','4G'), + sdram1 enum('32M','64M','128M','256M','512M','1G','2G','4G'), + sdram2 enum('32M','64M','128M','256M','512M','1G','2G','4G'), + sdram3 enum('32M','64M','128M','256M','512M','1G','2G','4G'), + flash0 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), + flash1 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), + flash2 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), + flash3 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), + zbt0 enum('512K','1M','2M','4M','8M','16M'), + zbt1 enum('512K','1M','2M','4M','8M','16M'), + zbt2 enum('512K','1M','2M','4M','8M','16M'), + zbt3 enum('512K','1M','2M','4M','8M','16M'), + zbt4 enum('512K','1M','2M','4M','8M','16M'), + zbt5 enum('512K','1M','2M','4M','8M','16M'), + zbt6 enum('512K','1M','2M','4M','8M','16M'), + zbt7 enum('512K','1M','2M','4M','8M','16M'), + zbt8 enum('512K','1M','2M','4M','8M','16M'), + zbt9 enum('512K','1M','2M','4M','8M','16M'), + zbta enum('512K','1M','2M','4M','8M','16M'), + zbtb enum('512K','1M','2M','4M','8M','16M'), + zbtc enum('512K','1M','2M','4M','8M','16M'), + zbtd enum('512K','1M','2M','4M','8M','16M'), + zbte enum('512K','1M','2M','4M','8M','16M'), + zbtf enum('512K','1M','2M','4M','8M','16M'), + xlxtyp0 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), + xlxtyp1 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), + xlxtyp2 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), + xlxtyp3 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), + xlxspd0 enum('6','7','8','4','5','9','10','11','12'), + xlxspd1 enum('6','7','8','4','5','9','10','11','12'), + xlxspd2 enum('6','7','8','4','5','9','10','11','12'), + xlxspd3 enum('6','7','8','4','5','9','10','11','12'), + xlxtmp0 enum('COM','IND'), + xlxtmp1 enum('COM','IND'), + xlxtmp2 enum('COM','IND'), + xlxtmp3 enum('COM','IND'), + xlxgrd0 enum('NORMAL','ENGSAMP'), + xlxgrd1 enum('NORMAL','ENGSAMP'), + xlxgrd2 enum('NORMAL','ENGSAMP'), + xlxgrd3 enum('NORMAL','ENGSAMP'), + cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'), + cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), + cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), + busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), + hstype enum('AMCC-S2064A','Xilinx-Rockets'), + hschin enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'), + hschout enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'), + PRIMARY KEY (serno), + KEY serno (serno), + UNIQUE serno_2 (serno) +); + +# +# Table structure for table 'log' +# + +DROP TABLE IF EXISTS log; +CREATE TABLE log ( + logno int(10) unsigned zerofill NOT NULL auto_increment, + serno int(10) unsigned zerofill NOT NULL, + date date NOT NULL, + details text NOT NULL, + PRIMARY KEY (logno), + KEY logno (logno, serno, date), + UNIQUE logno_2 (logno) +); diff --git a/tools/bddb/defs.php b/tools/bddb/defs.php new file mode 100644 index 0000000..b7518e3 --- /dev/null +++ b/tools/bddb/defs.php @@ -0,0 +1,710 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // contains mysql user id and password - keep secret + require("config.php"); + + if (isset($_REQUEST['logout'])) { + Header("status: 401 Unauthorized"); + Header("HTTP/1.0 401 Unauthorized"); + Header("WWW-authenticate: basic realm=\"$bddb_label\""); + + echo "" . + "Access to '$bddb_label' Denied" . + "\n"; + echo "



" . + "You must be an Authorised User " . + "to access the '$bddb_label'" . + "

\n
\n"; + exit; + } + + // contents of the various enumerated types - if first item is + // empty ('') then the enum is allowed to be null (ie "not null" + // is not set on the column) + + // all column names in the database table + $columns = array( + 'serno','ethaddr','date','batch', + 'type','rev','location','comments', + 'sdram0','sdram1','sdram2','sdram3', + 'flash0','flash1','flash2','flash3', + 'zbt0','zbt1','zbt2','zbt3','zbt4','zbt5','zbt6','zbt7', + 'zbt8','zbt9','zbta','zbtb','zbtc','zbtd','zbte','zbtf', + 'xlxtyp0','xlxtyp1','xlxtyp2','xlxtyp3', + 'xlxspd0','xlxspd1','xlxspd2','xlxspd3', + 'xlxtmp0','xlxtmp1','xlxtmp2','xlxtmp3', + 'xlxgrd0','xlxgrd1','xlxgrd2','xlxgrd3', + 'cputyp','cpuspd','cpmspd','busspd', + 'hstype','hschin','hschout' + ); + + // board type + $type_vals = array('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY'); + + // Xilinx fpga types + $xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'); + + // Xilinx fpga speeds + $xlxspd_vals = array('','6','7','8','4','5','9','10','11','12'); + + // Xilinx fpga temperatures (commercial or industrial) + $xlxtmp_vals = array('','COM','IND'); + + // Xilinx fpga grades (normal or engineering sample) + $xlxgrd_vals = array('','NORMAL','ENGSAMP'); + + // CPU types + $cputyp_vals = array('','MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'); + + // CPU/BUS/CPM clock speeds + $clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'); + + // sdram sizes (nbits array is for eeprom config file) + $sdram_vals = array('','32M','64M','128M','256M','512M','1G','2G','4G'); + $sdram_nbits = array(0,25,26,27,28,29,30,31,32); + + // flash sizes (nbits array is for eeprom config file) + $flash_vals = array('','4M','8M','16M','32M','64M','128M','256M','512M','1G'); + $flash_nbits = array(0,22,23,24,25,26,27,28,29,30); + + // zbt ram sizes (nbits array is for write into eeprom config file) + $zbt_vals = array('','512K','1M','2M','4M','8M','16M'); + $zbt_nbits = array(0,19,20,21,22,23,24); + + // high-speed serial attributes + $hstype_vals = array('','AMCC-S2064A','Xilinx-Rockets'); + $hschin_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'); + $hschout_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'); + + // value filters - used when outputting html + function rev_filter($num) { + if ($num == 0) + return "001"; + else + return sprintf("%03d", $num); + } + + function text_filter($str) { + return urldecode($str); + } + + mt_srand(time() | getmypid()); + + // set up MySQL connection + mysql_connect("", $mysql_user, $mysql_pw) || die("cannot connect"); + mysql_select_db($mysql_db) || die("cannot select db"); + + // page header + function pg_head($title) + { + echo "\n\n"; + echo "\n"; + echo "$title\n"; + echo "\n"; + echo "\n"; + echo "

$title

\n"; + echo "
\n"; + } + + // page footer + function pg_foot() + { + echo "
\n"; + echo "
\n
" . + "If you have any problems, email " . + "" . + "Murray Jensen" . + "
\n" . + "		\n" . + "logout\n" . + "
\n"; + echo "

Made with " . + "" . + "Kyber phpMyBuilder

\n"; + echo "\n"; + echo "\n"; + } + + // some support functions + + if (!function_exists('array_search')) { + + function array_search($needle, $haystack, $strict = false) { + + if (is_array($haystack) && count($haystack)) { + + $ntype = gettype($needle); + + foreach ($haystack as $key => $value) { + + if ($value == $needle && (!$strict || + gettype($value) == $ntype)) + return $key; + } + } + + return false; + } + } + + if (!function_exists('in_array')) { + + function in_array($needle, $haystack, $strict = false) { + + if (is_array($haystack) && count($haystack)) { + + $ntype = gettype($needle); + + foreach ($haystack as $key => $value) { + + if ($value == $needle && (!$strict || + gettype($value) == $ntype)) + return true; + } + } + + return false; + } + } + + function key_in_array($key, $array) { + return in_array($key, array_keys($array), true); + } + + function enum_to_index($name, $vals) { + $index = array_search($GLOBALS[$name], $vals); + if ($vals[0] != '') + $index++; + return $index; + } + + // fetch a value from an array - return empty string is not present + function get_key_value($key, $array) { + if (key_in_array($key, $array)) + return $array[$key]; + else + return ''; + } + + function fprintf() { + $n = func_num_args(); + if ($n < 2) + return FALSE; + $a = func_get_args(); + $fp = array_shift($a); + $x = "\$s = sprintf"; + $sep = '('; + foreach ($a as $z) { + $x .= "$sep'$z'"; + $sep = ','; + } + $x .= ');'; + eval($x); + $l = strlen($s); + $r = fwrite($fp, $s, $l); + if ($r != $l) + return FALSE; + else + return TRUE; + } + + // functions to display (print) a database table and its columns + + function begin_table($ncols) { + global $table_ncols; + $table_ncols = $ncols; + echo "\n"; + } + + function begin_field($name, $span = 0) { + global $table_ncols; + echo "\n"; + echo "\t\n"; + if ($span <= 0) + $span = $table_ncols - 1; + if ($span > 1) + echo "\t\n"; + if ($span > 1) + echo "\t\n"; + echo "\n"; + } + + function end_table() { + echo "
$name\n"; + else + echo "\t\n"; + } + + function cont_field($span = 1) { + echo "\t\n"; + else + echo "\t\n"; + } + + function end_field() { + echo "\t
\n"; + } + + function print_field($name, $array, $size = 0, $filt='') { + + begin_field($name); + + if (key_in_array($name, $array)) + $value = $array[$name]; + else + $value = ''; + + if ($filt != '') + $value = $filt($value); + + echo "\t\t 0) + echo " size=$size maxlength=$size"; + echo ">\n"; + + end_field(); + } + + function print_field_multiline($name, $array, $cols, $rows, $filt='') { + + begin_field($name); + + if (key_in_array($name, $array)) + $value = $array[$name]; + else + $value = ''; + + if ($filt != '') + $value = $filt($value); + + echo "\t\t\n"; + + end_field(); + } + + // print a mysql ENUM as an html RADIO INPUT + function print_enum($name, $array, $vals, $def = -1) { + + begin_field($name); + + if (key_in_array($name, $array)) + $chk = array_search($array[$name], $vals, FALSE); + else + $chk = $def; + + $nval = count($vals); + + for ($i = 0; $i < $nval; $i++) { + + $val = $vals[$i]; + if ($val == '') + $pval = "none"; + else + $pval = "$val"; + + printf("\t\t$pval\n", + $i == $chk ? " checked" : ""); + } + + end_field(); + } + + // print a mysql ENUM as an html SELECT INPUT + function print_enum_select($name, $array, $vals, $def = -1) { + + begin_field($name); + + echo "\t\t\n"; + + end_field(); + } + + // print a group of mysql ENUMs (e.g. name0,name1,...) as an html SELECT + function print_enum_multi($base, $array, $vals, $cnt, $defs, $grp = 0) { + + global $table_ncols; + + if ($grp <= 0) + $grp = $cnt; + $ncell = $cnt / $grp; + $span = ($table_ncols - 1) / $ncell; + + begin_field($base, $span); + + $nval = count($vals); + + for ($i = 0; $i < $cnt; $i++) { + + if ($i > 0 && ($i % $grp) == 0) + cont_field($span); + + $name = sprintf("%s%x", $base, $i); + + echo "\t\t\n"; + } + + end_field(); + } + + // functions to handle the form input + + // fetch all the parts of an "enum_multi" into a string suitable + // for a MySQL query + function gather_enum_multi_query($base, $cnt) { + + $retval = ''; + + for ($i = 0; $i < $cnt; $i++) { + + $name = sprintf("%s%x", $base, $i); + + if (isset($_REQUEST[$name])) { + $retval .= sprintf(", %s='%s'", + $name, $_REQUEST[$name]); + } + } + + return $retval; + } + + // fetch all the parts of an "enum_multi" into a string suitable + // for a display e.g. in an html table cell + function gather_enum_multi_print($base, $cnt, $array) { + + $retval = ''; + + for ($i = 0; $i < $cnt; $i++) { + + $name = sprintf("%s%x", $base, $i); + + if ($array[$name] != '') { + if ($retval != '') + $retval .= ','; + $retval .= $array[$name]; + } + } + + return $retval; + } + + // fetch all the parts of an "enum_multi" into a string suitable + // for writing to the eeprom data file + function gather_enum_multi_write($base, $cnt, $vals, $xfrm = array()) { + + $retval = ''; + + for ($i = 0; $i < $cnt; $i++) { + + $name = sprintf("%s%x", $base, $i); + + if ($GLOBALS[$name] != '') { + if ($retval != '') + $retval .= ','; + $index = enum_to_index($name, $vals); + if ($xfrm != array()) + $retval .= $xfrm[$index]; + else + $retval .= $index; + } + } + + return $retval; + } + + // count how many parts of an "enum_multi" are actually set + function count_enum_multi($base, $cnt) { + + $retval = 0; + + for ($i = 0; $i < $cnt; $i++) { + + $name = sprintf("%s%x", $base, $i); + + if (isset($_REQUEST[$name])) + $retval++; + } + + return $retval; + } + + // ethernet address functions + + // generate a (possibly not unique) random vendor ethernet address + // (setting bit 6 in the ethernet address - motorola wise i.e. bit 0 + // is the most significant bit - means it is not an assigned ethernet + // address - it is a "locally administered" address). Also, make sure + // it is NOT a multicast ethernet address (by setting bit 7 to 0). + // e.g. the first byte of all ethernet addresses generated here will + // have 2 in the bottom two bits (incidentally, these are the first + // two bits transmitted on the wire, since the octets in ethernet + // addresses are transmitted LSB first). + + function gen_eth_addr($serno) { + + $ethaddr_hgh = (mt_rand(0, 65535) & 0xfeff) | 0x0200; + $ethaddr_mid = mt_rand(0, 65535); + $ethaddr_low = mt_rand(0, 65535); + + return sprintf("%02lx:%02lx:%02lx:%02lx:%02lx:%02lx", + $ethaddr_hgh >> 8, $ethaddr_hgh & 0xff, + $ethaddr_mid >> 8, $ethaddr_mid & 0xff, + $ethaddr_low >> 8, $ethaddr_low & 0xff); + } + + // check that an ethernet address is valid + function eth_addr_is_valid($ethaddr) { + + $ethbytes = split(':', $ethaddr); + + if (count($ethbytes) != 6) + return FALSE; + + for ($i = 0; $i < 6; $i++) { + $ethbyte = $ethbytes[$i]; + if (!ereg('^[0-9a-f][0-9a-f]$', $ethbyte)) + return FALSE; + } + + return TRUE; + } + + // write a simple eeprom configuration file + function write_eeprom_cfg_file() { + + global $sernos, $nsernos, $bddb_cfgdir, $numerrs, $cfgerrs; + global $date, $batch, $type_vals, $rev; + global $sdram_vals, $sdram_nbits; + global $flash_vals, $flash_nbits; + global $zbt_vals, $zbt_nbits; + global $xlxtyp_vals, $xlxspd_vals, $xlxtmp_vals, $xlxgrd_vals; + global $cputyp, $cputyp_vals, $clk_vals; + global $hstype, $hstype_vals, $hschin, $hschout; + + $numerrs = 0; + $cfgerrs = array(); + + for ($i = 0; $i < $nsernos; $i++) { + + $serno = sprintf("%010d", $sernos[$i]); + + $wfp = @fopen($bddb_cfgdir . "/$serno.cfg", "w"); + if (!$wfp) { + $cfgerrs[$i] = 'file create fail'; + $numerrs++; + continue; + } + set_file_buffer($wfp, 0); + + if (!fprintf($wfp, "serno=%d\n", $sernos[$i])) { + $cfgerrs[$i] = 'cfg wr fail (serno)'; + fclose($wfp); + $numerrs++; + continue; + } + + if (!fprintf($wfp, "date=%s\n", $date)) { + $cfgerrs[$i] = 'cfg wr fail (date)'; + fclose($wfp); + $numerrs++; + continue; + } + + if ($batch != '') { + if (!fprintf($wfp, "batch=%s\n", $batch)) { + $cfgerrs[$i] = 'cfg wr fail (batch)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + $typei = enum_to_index("type", $type_vals); + if (!fprintf($wfp, "type=%d\n", $typei)) { + $cfgerrs[$i] = 'cfg wr fail (type)'; + fclose($wfp); + $numerrs++; + continue; + } + + if (!fprintf($wfp, "rev=%d\n", $rev)) { + $cfgerrs[$i] = 'cfg wr fail (rev)'; + fclose($wfp); + $numerrs++; + continue; + } + + $s = gather_enum_multi_write("sdram", 4, + $sdram_vals, $sdram_nbits); + if ($s != '') { + $b = fprintf($wfp, "sdram=%s\n", $s); + if (!$b) { + $cfgerrs[$i] = 'cfg wr fail (sdram)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + $s = gather_enum_multi_write("flash", 4, + $flash_vals, $flash_nbits); + if ($s != '') { + $b = fprintf($wfp, "flash=%s\n", $s); + if (!$b) { + $cfgerrs[$i] = 'cfg wr fail (flash)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + $s = gather_enum_multi_write("zbt", 16, + $zbt_vals, $zbt_nbits); + if ($s != '') { + $b = fprintf($wfp, "zbt=%s\n", $s); + if (!$b) { + $cfgerrs[$i] = 'cfg wr fail (zbt)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + $s = gather_enum_multi_write("xlxtyp", 4, $xlxtyp_vals); + if ($s != '') { + $b = fprintf($wfp, "xlxtyp=%s\n", $s); + if (!$b) { + $cfgerrs[$i] = 'cfg wr fail (xlxtyp)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + $s = gather_enum_multi_write("xlxspd", 4, $xlxspd_vals); + if ($s != '') { + $b = fprintf($wfp, "xlxspd=%s\n", $s); + if (!$b) { + $cfgerrs[$i] = 'cfg wr fail (xlxspd)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + $s = gather_enum_multi_write("xlxtmp", 4, $xlxtmp_vals); + if ($s != '') { + $b = fprintf($wfp, "xlxtmp=%s\n", $s); + if (!$b) { + $cfgerrs[$i] = 'cfg wr fail (xlxtmp)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + $s = gather_enum_multi_write("xlxgrd", 4, $xlxgrd_vals); + if ($s != '') { + $b = fprintf($wfp, "xlxgrd=%s\n", $s); + if (!$b) { + $cfgerrs[$i] = 'cfg wr fail (xlxgrd)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + if ($cputyp != '') { + $cputypi = enum_to_index("cputyp",$cputyp_vals); + $cpuspdi = enum_to_index("cpuspd", $clk_vals); + $busspdi = enum_to_index("busspd", $clk_vals); + $cpmspdi = enum_to_index("cpmspd", $clk_vals); + $b = fprintf($wfp, "cputyp=%d\ncpuspd=%d\n" . + "busspd=%d\ncpmspd=%d\n", + $cputypi, $cpuspdi, $busspdi, $cpmspdi); + if (!$b) { + $cfgerrs[$i] = 'cfg wr fail (cputyp)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + if ($hstype != '') { + $hstypei = enum_to_index("hstype",$hstype_vals); + $b = fprintf($wfp, "hstype=%d\n" . + "hschin=%s\nhschout=%s\n", + $hstypei, $hschin, $hschout); + if (!$b) { + $cfgerrs[$i] = 'cfg wr fail (hstype)'; + fclose($wfp); + $numerrs++; + continue; + } + } + + if (!fclose($wfp)) { + $cfgerrs[$i] = 'file cls fail'; + $numerrs++; + } + } + + return $numerrs; + } +?> diff --git a/tools/bddb/dodelete.php b/tools/bddb/dodelete.php new file mode 100644 index 0000000..4839e36 --- /dev/null +++ b/tools/bddb/dodelete.php @@ -0,0 +1,65 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // dodelete page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - Delete Board Results"); + + if (!isset($_REQUEST['serno'])) + die("the board serial number was not specified"); + $serno=intval($_REQUEST['serno']); + + mysql_query("delete from boards where serno=$serno"); + + if(mysql_errno()) { + $errstr = mysql_error(); + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe following error was encountered:\n"; + echo "\t\t

\n"; + echo "\t\t
\n"; + printf("\t\t\t%s\n", $errstr); + echo "\t\t
\n"; + echo "\t\n"; + } + else { + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe board with serial number $serno was" + . " successfully deleted\n"; + mysql_query("delete from log where serno=$serno"); + if (mysql_errno()) { + $errstr = mysql_error(); + echo "\t\t\t\n"; + echo "\t\t\t\t

\n"; + echo "\t\t\t\t\tBut the following error occurred " . + "when deleting the log entries:\n"; + echo "\t\t\t\t

\n"; + echo "\t\t\t\t
\n"; + printf("\t\t\t\t\t%s\n", $errstr); + echo "\t\t\t\t
\n"; + echo "\t\t\t\n"; + } + echo "\t\t

\n"; + echo "\t\n"; + } +?> +

+ + + + + +
+ Back to Browse + + Back to Start +
+ diff --git a/tools/bddb/dodellog.php b/tools/bddb/dodellog.php new file mode 100644 index 0000000..9dd78c1 --- /dev/null +++ b/tools/bddb/dodellog.php @@ -0,0 +1,57 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // dodelete page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - Delete Log Entry Results"); + + if (!isset($_REQUEST['serno'])) + die("the board serial number was not specified"); + $serno=intval($_REQUEST['serno']); + + if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == 0) + die("the log entry number not specified!"); + $logno=$_REQUEST['logno']; + + mysql_query("delete from log where serno=$serno and logno=$logno"); + + if(mysql_errno()) { + $errstr = mysql_error(); + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe following error was encountered:\n"; + echo "\t\t

\n"; + echo "\t\t
\n"; + printf("\t\t\t%s\n", $errstr); + echo "\t\t
\n"; + echo "\t\n"; + } + else { + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe log entry with log number $logno\n"; + echo "\t\t\tand serial number $serno "; + echo "was successfully deleted\n"; + echo "\t\t

\n"; + echo "\t\n"; + } +?> +

+ + + + + +
+ ">Back to Log + + Back to Start +
+ diff --git a/tools/bddb/doedit.php b/tools/bddb/doedit.php new file mode 100644 index 0000000..13fbb69 --- /dev/null +++ b/tools/bddb/doedit.php @@ -0,0 +1,186 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // doedit page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - Edit Board Results"); + + if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') + die("the board serial number was not specified"); + $serno=intval($_REQUEST['serno']); + + $query="update boards set"; + + if (isset($_REQUEST['ethaddr'])) { + $ethaddr=$_REQUEST['ethaddr']; + if (!eth_addr_is_valid($ethaddr)) + die("ethaddr is invalid ('$ethaddr')"); + $query.=" ethaddr='$ethaddr',"; + } + + if (isset($_REQUEST['date'])) { + $date=$_REQUEST['date']; + list($y, $m, $d) = split("-", $date); + if (!checkdate($m, $d, $y) || $y < 1999) + die("date is invalid (input '$date', " . + "yyyy-mm-dd '$y-$m-$d')"); + $query.=" date='$date'"; + } + + if (isset($_REQUEST['batch'])) { + $batch=$_REQUEST['batch']; + if (strlen($batch) > 32) + die("batch field too long (>32)"); + $query.=", batch='$batch'"; + } + + if (isset($_REQUEST['type'])) { + $type=$_REQUEST['type']; + if (!in_array($type, $type_vals)) + die("Invalid type ($type) specified"); + $query.=", type='$type'"; + } + + if (isset($_REQUEST['rev'])) { + $rev=$_REQUEST['rev']; + if (($rev = intval($rev)) <= 0 || $rev > 255) + die("Revision number is invalid ($rev)"); + $query.=sprintf(", rev=%d", $rev); + } + + if (isset($_REQUEST['location'])) { + $location=$_REQUEST['location']; + if (strlen($location) > 64) + die("location field too long (>64)"); + $query.=", location='$location'"; + } + + if (isset($_REQUEST['comments'])) + $comments=$_REQUEST['comments']; + $query.=", comments='" . rawurlencode($comments) . "'"; + + $query.=gather_enum_multi_query("sdram", 4); + + $query.=gather_enum_multi_query("flash", 4); + + $query.=gather_enum_multi_query("zbt", 16); + + $query.=gather_enum_multi_query("xlxtyp", 4); + $nxlx = count_enum_multi("xlxtyp", 4); + + $query.=gather_enum_multi_query("xlxspd", 4); + if (count_enum_multi("xlxspd", 4) != $nxlx) + die("number of xilinx speeds not same as number of types"); + + $query.=gather_enum_multi_query("xlxtmp", 4); + if (count_enum_multi("xlxtmp", 4) != $nxlx) + die("number of xilinx temps. not same as number of types"); + + $query.=gather_enum_multi_query("xlxgrd", 4); + if (count_enum_multi("xlxgrd", 4) != $nxlx) + die("number of xilinx grades not same as number of types"); + + if (isset($_REQUEST['cputyp'])) { + $cputyp=$_REQUEST['cputyp']; + $query.=", cputyp='$cputyp'"; + if (!isset($_REQUEST['cpuspd']) || $_REQUEST['cpuspd'] == '') + die("must specify cpu speed if cpu type is defined"); + $cpuspd=$_REQUEST['cpuspd']; + $query.=", cpuspd='$cpuspd'"; + if (!isset($_REQUEST['cpmspd']) || $_REQUEST['cpmspd'] == '') + die("must specify cpm speed if cpu type is defined"); + $cpmspd=$_REQUEST['cpmspd']; + $query.=", cpmspd='$cpmspd'"; + if (!isset($_REQUEST['busspd']) || $_REQUEST['busspd'] == '') + die("must specify bus speed if cpu type is defined"); + $busspd=$_REQUEST['busspd']; + $query.=", busspd='$busspd'"; + } + else { + if (isset($_REQUEST['cpuspd'])) + die("can't specify cpu speed if there is no cpu"); + if (isset($_REQUEST['cpmspd'])) + die("can't specify cpm speed if there is no cpu"); + if (isset($_REQUEST['busspd'])) + die("can't specify bus speed if there is no cpu"); + } + + if (isset($_REQUEST['hschin'])) { + $hschin=$_REQUEST['hschin']; + if (($hschin = intval($hschin)) < 0 || $hschin > 4) + die("Invalid number of hs input chans ($hschin)"); + } + else + $hschin = 0; + if (isset($_REQUEST['hschout'])) { + $hschout=$_REQUEST['hschout']; + if (($hschout = intval($hschout)) < 0 || $hschout > 4) + die("Invalid number of hs output chans ($hschout)"); + } + else + $hschout = 0; + if (isset($_REQUEST['hstype'])) { + $hstype=$_REQUEST['hstype']; + $query.=", hstype='$hstype'"; + } + else { + if ($_REQUEST['hschin'] != 0) + die("number of high-speed input channels must be zero" + . " if high-speed chip is not present"); + if ($_REQUEST['hschout'] != 0) + die("number of high-speed output channels must be zero" + . " if high-speed chip is not present"); + } + $query.=", hschin='$hschin'"; + $query.=", hschout='$hschout'"; + + $query.=" where serno=$serno"; + + mysql_query($query); + if(mysql_errno()) { + $errstr = mysql_error(); + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe following error was encountered:\n"; + echo "\t\t

\n"; + echo "\t\t
\n"; + printf("\t\t\t%s\n", $errstr); + echo "\t\t
\n"; + echo "\t\n"; + } + else { + $sernos = array($serno); + $nsernos = 1; + + write_eeprom_cfg_file(); + + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe board with serial number $serno was" + . " successfully updated"; + if ($numerrs > 0) { + $errstr = $cfgerrs[0]; + echo "
\n\t\t\t"; + echo "(but the cfg file update failed: $errstr)"; + } + echo "\n"; + echo "\t\t

\n"; + echo "\t\n"; + } + +?> +

+ + + + + +
Back to BrowseBack to Start
+ diff --git a/tools/bddb/doedlog.php b/tools/bddb/doedlog.php new file mode 100644 index 0000000..7009aa7 --- /dev/null +++ b/tools/bddb/doedlog.php @@ -0,0 +1,76 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // doedit page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - Edit Log Entry Results"); + + if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') + die("the board serial number was not specified"); + $serno=intval($_REQUEST['serno']); + + if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '') + die("log number not specified!"); + $logno=intval($_REQUEST['logno']); + + $query="update log set"; + + if (isset($_REQUEST['date'])) { + $date=$_REQUEST['date']; + list($y, $m, $d) = split("-", $date); + if (!checkdate($m, $d, $y) || $y < 1999) + die("date is invalid (input '$date', " . + "yyyy-mm-dd '$y-$m-$d')"); + $query.=" date='$date'"; + } + + if (isset($_REQUEST['who'])) { + $who=$_REQUEST['who']; + $query.=", who='" . $who . "'"; + } + + if (isset($_REQUEST['details'])) { + $details=$_REQUEST['details']; + $query.=", details='" . rawurlencode($details) . "'"; + } + + $query.=" where serno=$serno and logno=$logno"; + + mysql_query($query); + if(mysql_errno()) { + $errstr = mysql_error(); + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe following error was encountered:\n"; + echo "\t\t

\n"; + echo "\t\t
\n"; + printf("\t\t\t%s\n", $errstr); + echo "\t\t
\n"; + echo "\t\n"; + } + else { + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe log entry with log number $logno and\n"; + echo "\t\t\tserial number $serno "; + echo "was successfully updated\n"; + echo "\t\t

\n"; + echo "\t\n"; + } + +?> +

+ + + + + +
">Back to LogBack to Start
+ diff --git a/tools/bddb/donew.php b/tools/bddb/donew.php new file mode 100644 index 0000000..39b2c78 --- /dev/null +++ b/tools/bddb/donew.php @@ -0,0 +1,230 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // doedit page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - Board Registration Results"); + + if (isset($_REQUEST['serno'])) { + $serno=$_REQUEST['serno']; + die("serial number must not be set ($serno) when Creating!"); + } + + $query="update boards set"; + + list($y, $m, $d) = split("-", $date); + if (!checkdate($m, $d, $y) || $y < 1999) + die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')"); + $query.=" date='$date'"; + + if ($batch != '') { + if (strlen($batch) > 32) + die("batch field too long (>32)"); + $query.=", batch='$batch'"; + } + + if (!in_array($type, $type_vals)) + die("Invalid type ($type) specified"); + $query.=", type='$type'"; + + if (($rev = intval($rev)) <= 0 || $rev > 255) + die("Revision number is invalid ($rev)"); + $query.=sprintf(", rev=%d", $rev); + + $query.=gather_enum_multi_query("sdram", 4); + + $query.=gather_enum_multi_query("flash", 4); + + $query.=gather_enum_multi_query("zbt", 16); + + $query.=gather_enum_multi_query("xlxtyp", 4); + $nxlx = count_enum_multi("xlxtyp", 4); + + $query.=gather_enum_multi_query("xlxspd", 4); + if (count_enum_multi("xlxspd", 4) != $nxlx) + die("number of xilinx speeds not same as number of types"); + + $query.=gather_enum_multi_query("xlxtmp", 4); + if (count_enum_multi("xlxtmp", 4) != $nxlx) + die("number of xilinx temps. not same as number of types"); + + $query.=gather_enum_multi_query("xlxgrd", 4); + if (count_enum_multi("xlxgrd", 4) != $nxlx) + die("number of xilinx grades not same as number of types"); + + if ($cputyp == '') { + if ($cpuspd != '') + die("can't specify cpu speed if there is no cpu"); + if ($cpmspd != '') + die("can't specify cpm speed if there is no cpu"); + if ($busspd != '') + die("can't specify bus speed if there is no cpu"); + } + else { + $query.=", cputyp='$cputyp'"; + if ($cpuspd == '') + die("must specify cpu speed if cpu type is defined"); + $query.=", cpuspd='$cpuspd'"; + if ($cpmspd == '') + die("must specify cpm speed if cpu type is defined"); + $query.=", cpmspd='$cpmspd'"; + if ($busspd == '') + die("must specify bus speed if cpu type is defined"); + $query.=", busspd='$busspd'"; + } + + if (($hschin = intval($hschin)) < 0 || $hschin > 4) + die("Invalid number of hs input chans ($hschin)"); + if (($hschout = intval($hschout)) < 0 || $hschout > 4) + die("Invalid number of hs output chans ($hschout)"); + if ($hstype == '') { + if ($hschin != 0) + die("number of high-speed input channels must be zero" + . " if high-speed chip is not present"); + if ($hschout != 0) + die("number of high-speed output channels must be zero" + . " if high-speed chip is not present"); + } + else + $query.=", hstype='$hstype'"; + $query.=", hschin='$hschin'"; + $query.=", hschout='$hschout'"; + + // echo "final query = '$query'
\n"; + + $quant = intval($quant); + if ($quant <= 0) $quant = 1; + + $sernos = array(); + if ($geneths) + $ethaddrs = array(); + + $sqlerr = ''; + + while ($quant-- > 0) { + + mysql_query("insert into boards (serno) values (null)"); + if (mysql_errno()) { + $sqlerr = mysql_error(); + break; + } + + $serno = mysql_insert_id(); + if (!$serno) { + $sqlerr = "couldn't allocate new serial number"; + break; + } + + mysql_query($query . " where serno=$serno"); + if (mysql_errno()) { + $sqlerr = mysql_error(); + break; + } + + array_push($sernos, $serno); + + if ($geneths) { + + $ethaddr = gen_eth_addr($serno); + + mysql_query("update boards set ethaddr='$ethaddr'" . + " where serno=$serno"); + if (mysql_errno()) { + $sqlerr = mysql_error(); + + array_push($ethaddrs, + "" . + "db save fail" . + ""); + break; + } + + array_push($ethaddrs, $ethaddr); + } + } + + $nsernos = count($sernos); + + if ($nsernos > 0) { + + write_eeprom_cfg_file(); + + echo "\n"; + echo "\t

\n"; + echo "\t\tThe following board serial numbers were" + . " successfully allocated"; + if ($numerrs > 0) + echo " (but with $numerrs cfg file error" . + ($numerrs > 1 ? "s" : "") . ")"; + echo ":\n"; + echo "\t

\n"; + + echo "\n"; + + echo "\n"; + echo "\n"; + echo "\t\n"; + if ($numerrs > 0) + echo "\t\n"; + if ($geneths) + echo "\t\n"; + echo "\n"; + + for ($i = 0; $i < $nsernos; $i++) { + + $serno = sprintf("%010d", $sernos[$i]); + + echo "\n"; + + echo "\t\n"; + + if ($numerrs > 0) { + if (($errstr = $cfgerrs[$i]) == '') + $errstr = ' '; + echo "\t\n"; + } + + if ($geneths) { + echo "\t\n"; + } + + echo "\n"; + } + + echo "
Serial NumberCfg File ErrsEthernet Address
" . + "$serno" . + "" . + $errstr . + "" . + "" . + $ethaddrs[$i] . + "
\n"; + } + + if ($sqlerr != '') { + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe following SQL error was encountered:\n"; + echo "\t\t

\n"; + echo "\t\t
\n"; + printf("\t\t\t%s\n", $sqlerr); + echo "\t\t
\n"; + echo "\t\n"; + } + +?> +

+ + + + + +
Go to BrowseBack to Start
+ diff --git a/tools/bddb/donewlog.php b/tools/bddb/donewlog.php new file mode 100644 index 0000000..7635d29 --- /dev/null +++ b/tools/bddb/donewlog.php @@ -0,0 +1,86 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // doedit page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - Add Log Entry Results"); + + if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') + die("serial number not specified!"); + $serno=intval($_REQUEST['serno']); + + if (isset($_REQUEST['logno'])) { + $logno=$_REQUEST['logno']; + die("log number must not be set ($logno) when Creating!"); + } + + $query="update log set serno=$serno"; + + list($y, $m, $d) = split("-", $date); + if (!checkdate($m, $d, $y) || $y < 1999) + die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')"); + $query.=", date='$date'"; + + if (isset($_REQUEST['who'])) { + $who=$_REQUEST['who']; + $query.=", who='" . $who . "'"; + } + + if (isset($_REQUEST['details'])) { + $details=$_REQUEST['details']; + $query.=", details='" . rawurlencode($details) . "'"; + } + + // echo "final query = '$query'
\n"; + + $sqlerr = ''; + + mysql_query("insert into log (logno) values (null)"); + if (mysql_errno()) + $sqlerr = mysql_error(); + else { + $logno = mysql_insert_id(); + if (!$logno) + $sqlerr = "couldn't allocate new serial number"; + else { + mysql_query($query . " where logno=$logno"); + if (mysql_errno()) + $sqlerr = mysql_error(); + } + } + + if ($sqlerr == '') { + echo "\n"; + echo "\t

\n"; + echo "\t\tA log entry with log number '$logno' was " . + "added to the board with serial number '$serno'\n"; + echo "\t

\n"; + echo "\n"; + } + else { + echo "\t\n"; + echo "\t\t

\n"; + echo "\t\t\tThe following SQL error was encountered:\n"; + echo "\t\t

\n"; + echo "\t\t
\n"; + printf("\t\t\t%s\n", $sqlerr); + echo "\t\t
\n"; + echo "\t\n"; + } + +?> +

+ + + + + +
">Go to BrowseBack to Start
+ diff --git a/tools/bddb/edit.php b/tools/bddb/edit.php new file mode 100644 index 0000000..dd8c26c --- /dev/null +++ b/tools/bddb/edit.php @@ -0,0 +1,131 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // edit page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - Edit Board Registration"); + + if ($serno == 0) + die("serial number not specified or invalid!"); + + $pserno = sprintf("%010d", $serno); + + echo "
"; + echo "Board Serial Number: $pserno"; + echo "
\n"; + +?> +

+

+\n"; + + $r=mysql_query("select * from boards where serno=$serno"); + $row=mysql_fetch_array($r); + if(!$row) die("no record of serial number '$serno' in database"); + + begin_table(5); + + // ethaddr char(17) + print_field("ethaddr", $row, 17); + + // date date + print_field("date", $row); + + // batch char(32) + print_field("batch", $row, 32); + + // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') + print_enum("type", $row, $type_vals); + + // rev tinyint(3) unsigned zerofill + print_field("rev", $row, 3, 'rev_filter'); + + // location char(64) + print_field("location", $row, 64); + + // comments text + print_field_multiline("comments", $row, 60, 10, 'text_filter'); + + // sdram[0-3] enum('32M','64M','128M','256M') + print_enum_multi("sdram", $row, $sdram_vals, 4, array()); + + // flash[0-3] enum('4M','8M','16M','32M','64M') + print_enum_multi("flash", $row, $flash_vals, 4, array()); + + // zbt[0-f] enum('512K','1M','2M','4M') + print_enum_multi("zbt", $row, $zbt_vals, 16, array()); + + // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E') + print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(), 1); + + // xlxspd[0-3] enum('6','7','8') + print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(), 1); + + // xlxtmp[0-3] enum('COM','IND') + print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(), 1); + + // xlxgrd[0-3] enum('NORMAL','ENGSAMP') + print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(), 1); + + // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)') + print_enum("cputyp", $row, $cputyp_vals); + + // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') + print_enum_select("cpuspd", $row, $clk_vals); + + // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') + print_enum_select("cpmspd", $row, $clk_vals); + + // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') + print_enum_select("busspd", $row, $clk_vals); + + // hstype enum('AMCC-S2064A') + print_enum("hstype", $row, $hstype_vals); + + // hschin enum('0','1','2','3','4') + print_enum("hschin", $row, $hschin_vals); + + // hschout enum('0','1','2','3','4') + print_enum("hschout", $row, $hschout_vals); + + end_table(); + + echo "

\n"; + echo "

"; + echo "WARNING: NO UNDO ON DELETE!"; + echo "

\n"; + echo "[ delete ]"; + echo "
\n"; + echo "

\n"; +?> +

+ + + + + + + + +
+ + +   + + + +   + + Back to Start +
+

+
+ diff --git a/tools/bddb/edlog.php b/tools/bddb/edlog.php new file mode 100644 index 0000000..8befd35 --- /dev/null +++ b/tools/bddb/edlog.php @@ -0,0 +1,86 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // edit page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - Edit Board Log Entry"); + + if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') + die("serial number not specified!"); + $serno=intval($_REQUEST['serno']); + + if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '') + die("log number not specified!"); + $logno=intval($_REQUEST['logno']); + + $pserno = sprintf("%010d", $serno); + $plogno = sprintf("%010d", $logno); + + echo "
"; + echo "Board Serial Number: $pserno, Log Number: $plogno"; + echo "
\n"; + +?> +

+

+\n"; + echo "\n"; + + $r=mysql_query("select * from log where serno=$serno and logno=$logno"); + $row=mysql_fetch_array($r); + if(!$row) + die("no record of log entry with serial number '$serno' " . + "and log number '$logno' in database"); + + begin_table(3); + + // date date + print_field("date", $row); + + // who char(20) + print_field("who", $row); + + // details text + print_field_multiline("details", $row, 60, 10, 'text_filter'); + + end_table(); + + echo "

\n"; + echo "

"; + echo "WARNING: NO UNDO ON DELETE!"; + echo "

\n"; + echo "[ delete ]"; + echo "
\n"; + echo "

\n"; +?> +

+ + + + + + + + +
+ + +   + + + +   + + Back to Start +
+

+
+ diff --git a/tools/bddb/execute.php b/tools/bddb/execute.php new file mode 100644 index 0000000..0b62882 --- /dev/null +++ b/tools/bddb/execute.php @@ -0,0 +1,33 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:''; + + $submit=isset($_REQUEST['submit'])?$_REQUEST['submit']:"[NOT SET]"; + + switch ($submit) { + + case "New": + require("new.php"); + break; + + case "Edit": + require("edit.php"); + break; + + case "Browse": + require("browse.php"); + break; + + case "Log": + require("brlog.php"); + break; + + default: + require("badsubmit.php"); + break; + } +?> diff --git a/tools/bddb/index.php b/tools/bddb/index.php new file mode 100644 index 0000000..842aed5 --- /dev/null +++ b/tools/bddb/index.php @@ -0,0 +1,38 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + require("defs.php"); + pg_head("$bddb_label"); +?> + +
+ + + + + + + + + + +
+ + + + + + + +
+ Serial Number: + +
+
+ + diff --git a/tools/bddb/new.php b/tools/bddb/new.php new file mode 100644 index 0000000..30323ff --- /dev/null +++ b/tools/bddb/new.php @@ -0,0 +1,120 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // edit page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - New Board Registration"); +?> +
+

+ date("Y-m-d"))); + + // batch char(32) + print_field("batch", $row, 32); + + // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') + print_enum("type", $row, $type_vals, 0); + + // rev tinyint(3) unsigned zerofill + print_field("rev", $row, 3, 'rev_filter'); + + // sdram[0-3] enum('32M','64M','128M','256M') + print_enum_multi("sdram", $row, $sdram_vals, 4, array(2)); + + // flash[0-3] enum('4M','8M','16M','32M','64M') + print_enum_multi("flash", $row, $flash_vals, 4, array(2)); + + // zbt[0-f] enum('512K','1M','2M','4M') + print_enum_multi("zbt", $row, $zbt_vals, 16, array(2, 2)); + + // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E') + print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(1), 1); + + // xlxspd[0-3] enum('6','7','8') + print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(1), 1); + + // xlxtmp[0-3] enum('COM','IND') + print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(1), 1); + + // xlxgrd[0-3] enum('NORMAL','ENGSAMP') + print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(1), 1); + + // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)') + print_enum("cputyp", $row, $cputyp_vals, 1); + + // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') + print_enum_select("cpuspd", $row, $clk_vals, 4); + + // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') + print_enum_select("cpmspd", $row, $clk_vals, 4); + + // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') + print_enum_select("busspd", $row, $clk_vals, 2); + + // hstype enum('AMCC-S2064A') + print_enum("hstype", $row, $hstype_vals, 1); + + // hschin enum('0','1','2','3','4') + print_enum("hschin", $row, $hschin_vals, 4); + + // hschout enum('0','1','2','3','4') + print_enum("hschout", $row, $hschout_vals, 4); + + end_table(); +?> +

+ + + + + + + + + + + + + + + +
+ Allocate + + board serial number(s) +
+ + Generate Ethernet Address(es) +
+   +
+ + +   + + +
+
+ diff --git a/tools/bddb/newlog.php b/tools/bddb/newlog.php new file mode 100644 index 0000000..609bb85 --- /dev/null +++ b/tools/bddb/newlog.php @@ -0,0 +1,54 @@ + ?> + + // CSIRO Manufacturing Science and Technology, Preston Lab + + // edit page (hymod_bddb / boards) + + require("defs.php"); + + pg_head("$bddb_label - New Log Entry"); + + if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') + die("serial number not specified or invalid!"); + $serno=intval($_REQUEST['serno']); + + if (isset($_REQUEST['logno'])) { + $logno=$_REQUEST['logno']; + die("log number must not be specified when adding! ($logno)"); + } +?> +
+

+\n"; + + begin_table(3); + + // date date + print_field("date", array('date' => date("Y-m-d"))); + + // who char(20) + print_field("who", array()); + + // details text + print_field_multiline("details", array(), 60, 10, 'text_filter'); + + end_table(); +?> +

+ + + + + +
+ + + +
+
+ diff --git a/tools/bmp_logo.c b/tools/bmp_logo.c new file mode 100644 index 0000000..98be617 --- /dev/null +++ b/tools/bmp_logo.c @@ -0,0 +1,165 @@ +#include +#include + +#if defined(__linux__) +#include +#else +#ifdef __CYGWIN__ +#include "elf.h" +#else +#include +#endif +#endif + +typedef struct bitmap_s { /* bitmap description */ + uint16_t width; + uint16_t height; + uint8_t palette[256*3]; + uint8_t *data; +} bitmap_t; + +#define DEFAULT_CMAP_SIZE 16 /* size of default color map */ + +/* + * Neutralize little endians. + */ +uint16_t le_short(uint16_t x) +{ + uint16_t val; + uint8_t *p = (uint8_t *)(&x); + + val = (*p++ & 0xff) << 0; + val |= (*p & 0xff) << 8; + + return val; +} + +void skip_bytes (FILE *fp, int n) +{ + while (n-- > 0) + fgetc (fp); +} + +int main (int argc, char *argv[]) +{ + int i, x; + FILE *fp; + bitmap_t bmp; + bitmap_t *b = &bmp; + uint16_t data_offset, n_colors; + + if (argc < 2) { + fprintf (stderr, "Usage: %s file\n", argv[0]); + exit (EXIT_FAILURE); + } + + if ((fp = fopen (argv[1], "rb")) == NULL) { + perror (argv[1]); + exit (EXIT_FAILURE); + } + + if (fgetc (fp) != 'B' || fgetc (fp) != 'M') { + fprintf (stderr, "%s is not a bitmap file.\n", argv[1]); + exit (EXIT_FAILURE); + } + + /* + * read width and height of the image, and the number of colors used; + * ignore the rest + */ + skip_bytes (fp, 8); + fread (&data_offset, sizeof (uint16_t), 1, fp); + skip_bytes (fp, 6); + fread (&b->width, sizeof (uint16_t), 1, fp); + skip_bytes (fp, 2); + fread (&b->height, sizeof (uint16_t), 1, fp); + skip_bytes (fp, 22); + fread (&n_colors, sizeof (uint16_t), 1, fp); + skip_bytes (fp, 6); + + /* + * Repair endianess. + */ + data_offset = le_short(data_offset); + b->width = le_short(b->width); + b->height = le_short(b->height); + n_colors = le_short(n_colors); + + /* assume we are working with an 8-bit file */ + if ((n_colors == 0) || (n_colors > 256 - DEFAULT_CMAP_SIZE)) { + /* reserve DEFAULT_CMAP_SIZE color map entries for default map */ + n_colors = 256 - DEFAULT_CMAP_SIZE; + } + + printf ("/*\n" + " * Automatically generated by \"tools/bmp_logo\"\n" + " *\n" + " * DO NOT EDIT\n" + " *\n" + " */\n\n\n" + "#ifndef __BMP_LOGO_H__\n" + "#define __BMP_LOGO_H__\n\n" + "#define BMP_LOGO_WIDTH\t\t%d\n" + "#define BMP_LOGO_HEIGHT\t\t%d\n" + "#define BMP_LOGO_COLORS\t\t%d\n" + "#define BMP_LOGO_OFFSET\t\t%d\n" + "\n", + b->width, b->height, n_colors, + DEFAULT_CMAP_SIZE); + + /* allocate memory */ + if ((b->data = (uint8_t *)malloc(b->width * b->height)) == NULL) { + fclose (fp); + printf ("Error allocating memory for file %s.\n", argv[1]); + exit (EXIT_FAILURE); + } + + /* read and print the palette information */ + printf ("unsigned short bmp_logo_palette[] = {\n"); + + for (i=0; ipalette[(int)(i*3+2)] = fgetc(fp); + b->palette[(int)(i*3+1)] = fgetc(fp); + b->palette[(int)(i*3+0)] = fgetc(fp); + x=fgetc(fp); + + printf ("%s0x0%X%X%X,%s", + ((i%8) == 0) ? "\t" : " ", + (b->palette[(int)(i*3+0)] >> 4) & 0x0F, + (b->palette[(int)(i*3+1)] >> 4) & 0x0F, + (b->palette[(int)(i*3+2)] >> 4) & 0x0F, + ((i%8) == 7) ? "\n" : "" + ); + } + + /* seek to offset indicated by file header */ + fseek(fp, (long)data_offset, SEEK_SET); + + /* read the bitmap; leave room for default color map */ + printf ("\n"); + printf ("};\n"); + printf ("\n"); + printf ("unsigned char bmp_logo_bitmap[] = {\n"); + for (i=(b->height-1)*b->width; i>=0; i-=b->width) { + for (x = 0; x < b->width; x++) { + b->data[(uint16_t) i + x] = (uint8_t) fgetc (fp) \ + + DEFAULT_CMAP_SIZE; + } + } + fclose (fp); + + for (i=0; i<(b->height*b->width); ++i) { + if ((i%8) == 0) + putchar ('\t'); + printf ("0x%02X,%c", + b->data[i], + ((i%8) == 7) ? '\n' : ' ' + ); + } + printf ("\n" + "};\n\n" + "#endif /* __BMP_LOGO_H__ */\n" + ); + + return (0); +} diff --git a/tools/easylogo/Makefile b/tools/easylogo/Makefile new file mode 100644 index 0000000..292344a --- /dev/null +++ b/tools/easylogo/Makefile @@ -0,0 +1,2 @@ +all: easylogo.c + gcc easylogo.c -o easylogo diff --git a/tools/easylogo/easylogo.c b/tools/easylogo/easylogo.c new file mode 100644 index 0000000..cbec70b --- /dev/null +++ b/tools/easylogo/easylogo.c @@ -0,0 +1,422 @@ +/* +** Easylogo TGA->header converter +** ============================== +** (C) 2000 by Paolo Scaffardi (arsenio@tin.it) +** AIRVENT SAM s.p.a - RIMINI(ITALY) +** +** This is still under construction! +*/ + +#include + +#pragma pack(1) + +/*#define ENABLE_ASCII_BANNERS */ + +typedef struct { + unsigned char id; + unsigned char ColorMapType; + unsigned char ImageTypeCode; + unsigned short ColorMapOrigin; + unsigned short ColorMapLenght; + unsigned char ColorMapEntrySize; + unsigned short ImageXOrigin; + unsigned short ImageYOrigin; + unsigned short ImageWidth; + unsigned short ImageHeight; + unsigned char ImagePixelSize; + unsigned char ImageDescriptorByte; +} tga_header_t; + +typedef struct { + unsigned char r,g,b ; +} rgb_t ; + +typedef struct { + unsigned char b,g,r ; +} bgr_t ; + +typedef struct { + unsigned char Cb,y1,Cr,y2; +} yuyv_t ; + +typedef struct { + unsigned char *data, + *palette ; + int width, + height, + pixels, + bpp, + pixel_size, + size, + palette_size, + yuyv; +} image_t ; + +void StringUpperCase (char *str) +{ + int count = strlen(str); + char c ; + + while(count--) + { + c=*str; + if ((c >= 'a')&&(c<='z')) + *str = 'A' + (c-'a'); + str++ ; + } +} + +void StringLowerCase (char *str) +{ + int count = strlen(str); + char c ; + + while(count--) + { + c=*str; + if ((c >= 'A')&&(c<='Z')) + *str = 'a' + (c-'A'); + str++ ; + } +} +void pixel_rgb_to_yuyv (rgb_t *rgb_pixel, yuyv_t *yuyv_pixel) +{ + unsigned int pR, pG, pB ; + + /* Transform (0-255) components to (0-100) */ + pR = rgb_pixel->r * 100 / 255 ; + pG = rgb_pixel->g * 100 / 255 ; + pB = rgb_pixel->b * 100 / 255 ; + + /* Calculate YUV values (0-255) from RGB beetween 0-100 */ + yuyv_pixel->y1 = yuyv_pixel->y2 = 209 * (pR + pG + pB) / 300 + 16 ; + yuyv_pixel->Cb = pB - (pR/4) - (pG*3/4) + 128 ; + yuyv_pixel->Cr = pR - (pG*3/4) - (pB/4) + 128 ; + + return ; +} + +void printlogo_rgb (rgb_t *data, int w, int h) +{ + int x,y; + for (y=0; yr < 30)/*&&(data->g == 0)&&(data->b == 0)*/) + printf(" "); + else + printf("X"); + printf("\n"); + } +} + +void printlogo_yuyv (unsigned short *data, int w, int h) +{ + int x,y; + for (y=0; ywidth = header.ImageWidth ; + image->height = header.ImageHeight ; + + switch (header.ImageTypeCode){ + case 2: /* Uncompressed RGB */ + image->yuyv = 0 ; + image->palette_size = 0 ; + image->palette = NULL ; + break; + + default: + printf("Format not supported!\n"); + return -1 ; + } + + image->bpp = header.ImagePixelSize ; + image->pixel_size = ((image->bpp-1) / 8) + 1 ; + image->pixels = image->width * image->height; + image->size = image->pixels * image->pixel_size ; + image->data = malloc(image->size) ; + + if (image->bpp != 24) + { + printf("Bpp not supported: %d!\n", image->bpp); + return -1 ; + } + + fread(image->data, image->size, 1, file); + +/* Swapping R and B values */ + + p = image->data ; + for(i=0; i < image->pixels; i++, p++) + { + app = p->r ; + p->r = p->b ; + p->b = app ; + } + +/* Swapping image */ + + if(!(header.ImageDescriptorByte & 0x20)) + { + unsigned char *temp = malloc(image->size); + int linesize = image->pixel_size * image->width ; + void *dest = image->data, + *source = temp + image->size - linesize ; + + printf("S"); + if (temp == NULL) + { + printf("Cannot alloc temp buffer!\n"); + return -1; + } + + memcpy(temp, image->data, image->size); + for(i = 0; iheight; i++, dest+=linesize, source-=linesize) + memcpy(dest, source, linesize); + + free( temp ); + } + +#ifdef ENABLE_ASCII_BANNERS + printlogo_rgb (image->data,image->width, image->height); +#endif + + fclose (file); + return 0; +} + +int image_free (image_t *image) +{ + if(image->data != NULL) + free(image->data); + + if(image->palette != NULL) + free(image->palette); + + return 0; +} + +int image_rgb_to_yuyv (image_t *rgb_image, image_t *yuyv_image) +{ + rgb_t *rgb_ptr = (rgb_t *) rgb_image->data ; + yuyv_t yuyv ; + unsigned short *dest ; + int count = 0 ; + + yuyv_image->pixel_size = 2 ; + yuyv_image->bpp = 16 ; + yuyv_image->yuyv = 1 ; + yuyv_image->width = rgb_image->width ; + yuyv_image->height = rgb_image->height ; + yuyv_image->pixels = yuyv_image->width * yuyv_image->height ; + yuyv_image->size = yuyv_image->pixels * yuyv_image->pixel_size ; + dest = (unsigned short *) (yuyv_image->data = malloc(yuyv_image->size)) ; + yuyv_image->palette = 0 ; + yuyv_image->palette_size= 0 ; + + while((count++) < rgb_image->pixels) + { + pixel_rgb_to_yuyv (rgb_ptr++, &yuyv); + + if ((count & 1)==0) /* Was == 0 */ + memcpy (dest, ((void *)&yuyv) + 2, sizeof(short)); + else + memcpy (dest, (void *)&yuyv, sizeof(short)); + + dest ++ ; + } + +#ifdef ENABLE_ASCII_BANNERS + printlogo_yuyv (yuyv_image->data, yuyv_image->width, yuyv_image->height); +#endif + return 0 ; +} + +int image_save_header (image_t *image, char *filename, char *varname) +{ + FILE *file = fopen (filename, "w"); + char app[256], str[256]="", def_name[64] ; + int count = image->size, col=0; + unsigned char *dataptr = image->data ; + if (file==NULL) + return -1 ; + +/* Author information */ + fprintf(file, "/*\n * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi\n/*\n"); */ + fprintf(file, " * To use this, include it and call: easylogo_plot(screen,&%s, width,x,y)\n *\n", varname); + fprintf(file, " * Where:\t'screen'\tis the pointer to the frame buffer\n"); + fprintf(file, " *\t\t'width'\tis the screen width\n"); + fprintf(file, " *\t\t'x'\t\tis the horizontal position\n"); + fprintf(file, " *\t\t'y'\t\tis the vertical position\n */\n\n"); + +/* Headers */ + fprintf(file, "#include \n\n"); +/* Macros */ + strcpy(def_name, varname); + StringUpperCase (def_name); + fprintf(file, "#define DEF_%s_WIDTH\t\t%d\n", def_name, image->width); + fprintf(file, "#define DEF_%s_HEIGHT\t\t%d\n", def_name, image->height); + fprintf(file, "#define DEF_%s_PIXELS\t\t%d\n", def_name, image->pixels); + fprintf(file, "#define DEF_%s_BPP\t\t%d\n", def_name, image->bpp); + fprintf(file, "#define DEF_%s_PIXEL_SIZE\t%d\n", def_name, image->pixel_size); + fprintf(file, "#define DEF_%s_SIZE\t\t%d\n\n", def_name, image->size); +/* Declaration */ + fprintf(file, "unsigned char DEF_%s_DATA[DEF_%s_SIZE] = {\n", def_name, def_name); + +/* Data */ + while(count) + switch (col){ + case 0: + sprintf(str, " 0x%02x", *dataptr++); + col++; + count-- ; + break; + + case 16: + fprintf(file, "%s", str); + if (count > 0) + fprintf(file,","); + fprintf(file, "\n"); + + col = 0 ; + break; + + default: + strcpy(app, str); + sprintf(str, "%s, 0x%02x", app, *dataptr++); + col++ ; + count-- ; + break; + } + + if (col) + fprintf(file, "%s\n", str); + +/* End of declaration */ + fprintf(file, "};\n\n"); +/* Variable */ + fprintf(file, "fastimage_t %s = {\n", varname); + fprintf(file, " DEF_%s_DATA,\n", def_name); + fprintf(file, " DEF_%s_WIDTH,\n", def_name); + fprintf(file, " DEF_%s_HEIGHT,\n", def_name); + fprintf(file, " DEF_%s_BPP,\n", def_name); + fprintf(file, " DEF_%s_PIXEL_SIZE,\n", def_name); + fprintf(file, " DEF_%s_SIZE\n};\n", def_name); + + fclose (file); + + return 0 ; +} + +#define DEF_FILELEN 256 + +int main (int argc, char *argv[]) +{ + char + inputfile[DEF_FILELEN], + outputfile[DEF_FILELEN], + varname[DEF_FILELEN]; + + image_t rgb_logo, yuyv_logo ; + + switch (argc){ + case 2: + case 3: + case 4: + strcpy (inputfile, argv[1]); + + if (argc > 2) + strcpy (varname, argv[2]); + else + { + int pos = strchr(inputfile, '.'); + + if (pos >= 0) + { + strncpy (varname, inputfile, pos); + varname[pos] = 0 ; + } + } + + if (argc > 3) + strcpy (outputfile, argv[3]); + else + { + int pos = strchr (varname, '.'); + + if (pos > 0) + { + char app[DEF_FILELEN] ; + + strncpy(app, varname, pos); + sprintf(outputfile, "%s.h", app); + } + } + break; + + default: + printf("EasyLogo 1.0 (C) 2000 by Paolo Scaffardi\n\n"); + + printf("Syntax: easylogo inputfile [outputvar {outputfile}] \n"); + printf("\n"); + printf("Where: 'inputfile' is the TGA image to load\n"); + printf(" 'outputvar' is the variable name to create\n"); + printf(" 'outputfile' is the output header file (default is 'inputfile.h')\n"); + + return -1 ; + } + + printf("Doing '%s' (%s) from '%s'...", + outputfile, varname, inputfile); + +/* Import TGA logo */ + + printf("L"); + if (image_load_tga (&rgb_logo, inputfile)<0) + { + printf("input file not found!\n"); + exit(1); + } + +/* Convert it to YUYV format */ + + printf("C"); + image_rgb_to_yuyv (&rgb_logo, &yuyv_logo) ; + +/* Save it into a header format */ + + printf("S"); + image_save_header (&yuyv_logo, outputfile, varname) ; + +/* Free original image and copy */ + + image_free (&rgb_logo); + image_free (&yuyv_logo); + + printf("\n"); + + return 0 ; +} diff --git a/tools/easylogo/linux_logo.tga b/tools/easylogo/linux_logo.tga new file mode 100644 index 0000000..ac53def Binary files /dev/null and b/tools/easylogo/linux_logo.tga differ diff --git a/tools/easylogo/runme.sh b/tools/easylogo/runme.sh new file mode 100644 index 0000000..625ebaa --- /dev/null +++ b/tools/easylogo/runme.sh @@ -0,0 +1,4 @@ +#!/bin/sh +make +./easylogo linux_logo.tga u_boot_logo video_logo.h +mv video_logo.h ../../include diff --git a/tools/env/Makefile b/tools/env/Makefile new file mode 100644 index 0000000..9ce477c --- /dev/null +++ b/tools/env/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +SOURCES := crc32.c fw_env.c fw_env_main.c +HEADERS := fw_env.h + +all: fw_printenv + +fw_printenv: $(SOURCES) $(HEADERS) + $(CROSS_COMPILE)gcc -Wall -DUSE_HOSTCC $(SOURCES) -o fw_printenv + +clean: + rm -f fw_printenv crc32.c + +crc32.c: + ln -s ../../lib_generic/crc32.c crc32.c + +######################################################################### + +.depend: Makefile $(SOURCES) + $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -DUSE_HOSTCC $(SOURCES) > $@ + +sinclude .depend + +######################################################################### diff --git a/tools/env/README b/tools/env/README new file mode 100644 index 0000000..d8386f7 --- /dev/null +++ b/tools/env/README @@ -0,0 +1,44 @@ + +This is a demo implementation of a Linux command line tool to access +the U-Boot's environment variables. + +For the run-time utiltity configuration uncomment the line +#define CONFIG_FILE "/etc/fw_env.config" +in fw_env.h. + +See comments in the fw_env.config file for definitions for the +particular board. + +Configuration can also be done via #defines in the fw_env.h file. The +following lines are relevant: + +#define HAVE_REDUND /* For systems with 2 env sectors */ +#define DEVICE1_NAME "/dev/mtd1" +#define DEVICE2_NAME "/dev/mtd2" +#define DEVICE1_OFFSET 0x0000 +#define ENV1_SIZE 0x4000 +#define DEVICE1_ESIZE 0x4000 +#define DEVICE2_OFFSET 0x0000 +#define ENV2_SIZE 0x4000 +#define DEVICE2_ESIZE 0x4000 + +Current configuration matches the environment layout of the TRAB +board. + +Un-define HAVE_REDUND, if you want to use the utlities on a system +that does not have support for redundant environment enabled. +If HAVE_REDUND is undefined, DEVICE2_NAME is ignored, +as is ENV2_SIZE and DEVICE2_ESIZE. + +The DEVICEx_NAME constants define which MTD character devices are to +be used to access the environment. + +The DEVICEx_OFFSET constants define the environment offset within the +MTD character device. + +ENVx_SIZE defines the size in bytes taken by the environment, which +may be less then flash sector size, if the environment takes less +then 1 sector. + +DEVICEx_ESIZE defines the size of the first sector in the flash +partition where the environment resides. diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c new file mode 100644 index 0000000..74c0498 --- /dev/null +++ b/tools/env/fw_env.c @@ -0,0 +1,770 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fw_env.h" + +typedef unsigned char uchar; + +#define CMD_GETENV "fw_printenv" +#define CMD_SETENV "fw_setenv" + +typedef struct envdev_s { + uchar devname[16]; /* Device name */ + ulong devoff; /* Device offset */ + ulong env_size; /* environment size */ + ulong erase_size; /* device erase size */ +} envdev_t; + +static envdev_t envdevices[2]; +static int curdev; + +#define DEVNAME(i) envdevices[(i)].devname +#define DEVOFFSET(i) envdevices[(i)].devoff +#define ENVSIZE(i) envdevices[(i)].env_size +#define DEVESIZE(i) envdevices[(i)].erase_size + +#define CFG_ENV_SIZE ENVSIZE(curdev) + +#define ENV_SIZE getenvsize() + +typedef struct environment_s { + ulong crc; /* CRC32 over data bytes */ + uchar flags; /* active or obsolete */ + uchar *data; +} env_t; + +static env_t environment; + +static int HaveRedundEnv = 0; + +static uchar active_flag = 1; +static uchar obsolete_flag = 0; + + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +static uchar default_environment[] = { +#if defined(CONFIG_BOOTARGS) + "bootargs=" CONFIG_BOOTARGS "\0" +#endif +#if defined(CONFIG_BOOTCOMMAND) + "bootcmd=" CONFIG_BOOTCOMMAND "\0" +#endif +#if defined(CONFIG_RAMBOOTCOMMAND) + "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_NFSBOOTCOMMAND) + "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + "bootdelay=" MK_STR (CONFIG_BOOTDELAY) "\0" +#endif +#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) + "baudrate=" MK_STR (CONFIG_BAUDRATE) "\0" +#endif +#ifdef CONFIG_LOADS_ECHO + "loads_echo=" MK_STR (CONFIG_LOADS_ECHO) "\0" +#endif +#ifdef CONFIG_ETHADDR + "ethaddr=" MK_STR (CONFIG_ETHADDR) "\0" +#endif +#ifdef CONFIG_ETH1ADDR + "eth1addr=" MK_STR (CONFIG_ETH1ADDR) "\0" +#endif +#ifdef CONFIG_ETH2ADDR + "eth2addr=" MK_STR (CONFIG_ETH2ADDR) "\0" +#endif +#ifdef CONFIG_ETH3ADDR + "eth3addr=" MK_STR (CONFIG_ETH3ADDR) "\0" +#endif +#ifdef CONFIG_ETHPRIME + "ethprime=" CONFIG_ETHPRIME "\0" +#endif +#ifdef CONFIG_IPADDR + "ipaddr=" MK_STR (CONFIG_IPADDR) "\0" +#endif +#ifdef CONFIG_SERVERIP + "serverip=" MK_STR (CONFIG_SERVERIP) "\0" +#endif +#ifdef CFG_AUTOLOAD + "autoload=" CFG_AUTOLOAD "\0" +#endif +#ifdef CONFIG_ROOTPATH + "rootpath=" MK_STR (CONFIG_ROOTPATH) "\0" +#endif +#ifdef CONFIG_GATEWAYIP + "gatewayip=" MK_STR (CONFIG_GATEWAYIP) "\0" +#endif +#ifdef CONFIG_NETMASK + "netmask=" MK_STR (CONFIG_NETMASK) "\0" +#endif +#ifdef CONFIG_HOSTNAME + "hostname=" MK_STR (CONFIG_HOSTNAME) "\0" +#endif +#ifdef CONFIG_BOOTFILE + "bootfile=" MK_STR (CONFIG_BOOTFILE) "\0" +#endif +#ifdef CONFIG_LOADADDR + "loadaddr=" MK_STR (CONFIG_LOADADDR) "\0" +#endif +#ifdef CONFIG_PREBOOT + "preboot=" CONFIG_PREBOOT "\0" +#endif +#ifdef CONFIG_CLOCKS_IN_MHZ + "clocks_in_mhz=" "1" "\0" +#endif +#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) + "pcidelay=" MK_STR (CONFIG_PCI_BOOTDELAY) "\0" +#endif +#ifdef CONFIG_EXTRA_ENV_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS +#endif + "\0" /* Termimate env_t data with 2 NULs */ +}; + +static int flash_io (int mode); +static uchar *envmatch (uchar * s1, uchar * s2); +static int env_init (void); +static int parse_config (void); + +#if defined(CONFIG_FILE) +static int get_config (char *); +#endif +static inline ulong getenvsize (void) +{ + ulong rc = CFG_ENV_SIZE - sizeof (long); + + if (HaveRedundEnv) + rc -= sizeof (char); + return rc; +} + +/* + * Search the environment for a variable. + * Return the value, if found, or NULL, if not found. + */ +unsigned char *fw_getenv (unsigned char *name) +{ + uchar *env, *nxt; + + if (env_init ()) + return (NULL); + + for (env = environment.data; *env; env = nxt + 1) { + uchar *val; + + for (nxt = env; *nxt; ++nxt) { + if (nxt >= &environment.data[ENV_SIZE]) { + fprintf (stderr, "## Error: " + "environment not terminated\n"); + return (NULL); + } + } + val = envmatch (name, env); + if (!val) + continue; + return (val); + } + return (NULL); +} + +/* + * Print the current definition of one, or more, or all + * environment variables + */ +void fw_printenv (int argc, char *argv[]) +{ + uchar *env, *nxt; + int i, n_flag; + + if (env_init ()) + return; + + if (argc == 1) { /* Print all env variables */ + for (env = environment.data; *env; env = nxt + 1) { + for (nxt = env; *nxt; ++nxt) { + if (nxt >= &environment.data[ENV_SIZE]) { + fprintf (stderr, "## Error: " + "environment not terminated\n"); + return; + } + } + + printf ("%s\n", env); + } + return; + } + + if (strcmp (argv[1], "-n") == 0) { + n_flag = 1; + ++argv; + --argc; + if (argc != 2) { + fprintf (stderr, "## Error: " + "`-n' option requires exactly one argument\n"); + return; + } + } else { + n_flag = 0; + } + + for (i = 1; i < argc; ++i) { /* print single env variables */ + uchar *name = argv[i]; + uchar *val = NULL; + + for (env = environment.data; *env; env = nxt + 1) { + + for (nxt = env; *nxt; ++nxt) { + if (nxt >= &environment.data[ENV_SIZE]) { + fprintf (stderr, "## Error: " + "environment not terminated\n"); + return; + } + } + val = envmatch (name, env); + if (val) { + if (!n_flag) { + fputs (name, stdout); + putc ('=', stdout); + } + puts (val); + break; + } + } + if (!val) + fprintf (stderr, "## Error: \"%s\" not defined\n", name); + } +} + +/* + * Deletes or sets environment variables. Returns errno style error codes: + * 0 - OK + * EINVAL - need at least 1 argument + * EROFS - certain variables ("ethaddr", "serial#") cannot be + * modified or deleted + * + */ +int fw_setenv (int argc, char *argv[]) +{ + int i, len; + uchar *env, *nxt; + uchar *oldval = NULL; + uchar *name; + + if (argc < 2) { + return (EINVAL); + } + + if (env_init ()) + return (errno); + + name = argv[1]; + + /* + * search if variable with this name already exists + */ + for (nxt = env = environment.data; *env; env = nxt + 1) { + for (nxt = env; *nxt; ++nxt) { + if (nxt >= &environment.data[ENV_SIZE]) { + fprintf (stderr, "## Error: " + "environment not terminated\n"); + return (EINVAL); + } + } + if ((oldval = envmatch (name, env)) != NULL) + break; + } + + /* + * Delete any existing definition + */ + if (oldval) { + /* + * Ethernet Address and serial# can be set only once + */ + if ((strcmp (name, "ethaddr") == 0) || + (strcmp (name, "serial#") == 0)) { + fprintf (stderr, "Can't overwrite \"%s\"\n", name); + return (EROFS); + } + + if (*++nxt == '\0') { + *env = '\0'; + } else { + for (;;) { + *env = *nxt++; + if ((*env == '\0') && (*nxt == '\0')) + break; + ++env; + } + } + *++env = '\0'; + } + + /* Delete only ? */ + if (argc < 3) + goto WRITE_FLASH; + + /* + * Append new definition at the end + */ + for (env = environment.data; *env || *(env + 1); ++env); + if (env > environment.data) + ++env; + /* + * Overflow when: + * "name" + "=" + "val" +"\0\0" > CFG_ENV_SIZE - (env-environment) + */ + len = strlen (name) + 2; + /* add '=' for first arg, ' ' for all others */ + for (i = 2; i < argc; ++i) { + len += strlen (argv[i]) + 1; + } + if (len > (&environment.data[ENV_SIZE] - env)) { + fprintf (stderr, + "Error: environment overflow, \"%s\" deleted\n", + name); + return (-1); + } + while ((*env = *name++) != '\0') + env++; + for (i = 2; i < argc; ++i) { + uchar *val = argv[i]; + + *env = (i == 2) ? '=' : ' '; + while ((*++env = *val++) != '\0'); + } + + /* end is marked with double '\0' */ + *++env = '\0'; + + WRITE_FLASH: + + /* Update CRC */ + environment.crc = crc32 (0, environment.data, ENV_SIZE); + + /* write environment back to flash */ + if (flash_io (O_RDWR)) { + fprintf (stderr, "Error: can't write fw_env to flash\n"); + return (-1); + } + + return (0); +} + +static int flash_io (int mode) +{ + int fd, fdr, rc, otherdev, len, resid; + erase_info_t erase; + char *data = NULL; + + if ((fd = open (DEVNAME (curdev), mode)) < 0) { + fprintf (stderr, + "Can't open %s: %s\n", + DEVNAME (curdev), strerror (errno)); + return (-1); + } + + len = sizeof (environment.crc); + if (HaveRedundEnv) { + len += sizeof (environment.flags); + } + + if (mode == O_RDWR) { + if (HaveRedundEnv) { + /* switch to next partition for writing */ + otherdev = !curdev; + if ((fdr = open (DEVNAME (otherdev), mode)) < 0) { + fprintf (stderr, + "Can't open %s: %s\n", + DEVNAME (otherdev), + strerror (errno)); + return (-1); + } + } else { + otherdev = curdev; + fdr = fd; + } + printf ("Unlocking flash...\n"); + erase.length = DEVESIZE (otherdev); + erase.start = DEVOFFSET (otherdev); + ioctl (fdr, MEMUNLOCK, &erase); + + if (HaveRedundEnv) { + erase.length = DEVESIZE (curdev); + erase.start = DEVOFFSET (curdev); + ioctl (fd, MEMUNLOCK, &erase); + environment.flags = active_flag; + } + + printf ("Done\n"); + resid = DEVESIZE (otherdev) - CFG_ENV_SIZE; + if (resid) { + if ((data = malloc (resid)) == NULL) { + fprintf (stderr, + "Cannot malloc %d bytes: %s\n", + resid, + strerror (errno)); + return (-1); + } + if (lseek (fdr, DEVOFFSET (otherdev) + CFG_ENV_SIZE, SEEK_SET) + == -1) { + fprintf (stderr, "seek error on %s: %s\n", + DEVNAME (otherdev), + strerror (errno)); + return (-1); + } + if ((rc = read (fdr, data, resid)) != resid) { + fprintf (stderr, + "read error on %s: %s\n", + DEVNAME (otherdev), + strerror (errno)); + return (-1); + } + } + + printf ("Erasing old environment...\n"); + + erase.length = DEVESIZE (otherdev); + erase.start = DEVOFFSET (otherdev); + if (ioctl (fdr, MEMERASE, &erase) != 0) { + fprintf (stderr, "MTD erase error on %s: %s\n", + DEVNAME (otherdev), + strerror (errno)); + return (-1); + } + + printf ("Done\n"); + + printf ("Writing environment to %s...\n", DEVNAME (otherdev)); + if (lseek (fdr, DEVOFFSET (otherdev), SEEK_SET) == -1) { + fprintf (stderr, + "seek error on %s: %s\n", + DEVNAME (otherdev), strerror (errno)); + return (-1); + } + if (write (fdr, &environment, len) != len) { + fprintf (stderr, + "CRC write error on %s: %s\n", + DEVNAME (otherdev), strerror (errno)); + return (-1); + } + if (write (fdr, environment.data, ENV_SIZE) != ENV_SIZE) { + fprintf (stderr, + "Write error on %s: %s\n", + DEVNAME (otherdev), strerror (errno)); + return (-1); + } + if (resid) { + if (write (fdr, data, resid) != resid) { + fprintf (stderr, + "write error on %s: %s\n", + DEVNAME (curdev), strerror (errno)); + return (-1); + } + free (data); + } + if (HaveRedundEnv) { + /* change flag on current active env partition */ + if (lseek (fd, DEVOFFSET (curdev) + sizeof (ulong), SEEK_SET) + == -1) { + fprintf (stderr, "seek error on %s: %s\n", + DEVNAME (curdev), strerror (errno)); + return (-1); + } + if (write (fd, &obsolete_flag, sizeof (obsolete_flag)) != + sizeof (obsolete_flag)) { + fprintf (stderr, + "Write error on %s: %s\n", + DEVNAME (curdev), strerror (errno)); + return (-1); + } + } + printf ("Done\n"); + printf ("Locking ...\n"); + erase.length = DEVESIZE (otherdev); + erase.start = DEVOFFSET (otherdev); + ioctl (fdr, MEMLOCK, &erase); + if (HaveRedundEnv) { + erase.length = DEVESIZE (curdev); + erase.start = DEVOFFSET (curdev); + ioctl (fd, MEMLOCK, &erase); + if (close (fdr)) { + fprintf (stderr, + "I/O error on %s: %s\n", + DEVNAME (otherdev), + strerror (errno)); + return (-1); + } + } + printf ("Done\n"); + } else { + + if (lseek (fd, DEVOFFSET (curdev), SEEK_SET) == -1) { + fprintf (stderr, + "seek error on %s: %s\n", + DEVNAME (curdev), strerror (errno)); + return (-1); + } + if (read (fd, &environment, len) != len) { + fprintf (stderr, + "CRC read error on %s: %s\n", + DEVNAME (curdev), strerror (errno)); + return (-1); + } + if ((rc = read (fd, environment.data, ENV_SIZE)) != ENV_SIZE) { + fprintf (stderr, + "Read error on %s: %s\n", + DEVNAME (curdev), strerror (errno)); + return (-1); + } + } + + if (close (fd)) { + fprintf (stderr, + "I/O error on %s: %s\n", + DEVNAME (curdev), strerror (errno)); + return (-1); + } + + /* everything ok */ + return (0); +} + +/* + * s1 is either a simple 'name', or a 'name=value' pair. + * s2 is a 'name=value' pair. + * If the names match, return the value of s2, else NULL. + */ + +static uchar *envmatch (uchar * s1, uchar * s2) +{ + + while (*s1 == *s2++) + if (*s1++ == '=') + return (s2); + if (*s1 == '\0' && *(s2 - 1) == '=') + return (s2); + return (NULL); +} + +/* + * Prevent confusion if running from erased flash memory + */ +static int env_init (void) +{ + int crc1, crc1_ok; + uchar *addr1; + + int crc2, crc2_ok; + uchar flag1, flag2, *addr2; + + if (parse_config ()) /* should fill envdevices */ + return 1; + + if ((addr1 = calloc (1, ENV_SIZE)) == NULL) { + fprintf (stderr, + "Not enough memory for environment (%ld bytes)\n", + ENV_SIZE); + return (errno); + } + + /* read environment from FLASH to local buffer */ + environment.data = addr1; + curdev = 0; + if (flash_io (O_RDONLY)) { + return (errno); + } + + crc1_ok = ((crc1 = crc32 (0, environment.data, ENV_SIZE)) + == environment.crc); + if (!HaveRedundEnv) { + if (!crc1_ok) { + fprintf (stderr, + "Warning: Bad CRC, using default environment\n"); + environment.data = default_environment; + free (addr1); + } + } else { + flag1 = environment.flags; + + curdev = 1; + if ((addr2 = calloc (1, ENV_SIZE)) == NULL) { + fprintf (stderr, + "Not enough memory for environment (%ld bytes)\n", + ENV_SIZE); + return (errno); + } + environment.data = addr2; + + if (flash_io (O_RDONLY)) { + return (errno); + } + + crc2_ok = ((crc2 = crc32 (0, environment.data, ENV_SIZE)) + == environment.crc); + flag2 = environment.flags; + + if (crc1_ok && !crc2_ok) { + environment.data = addr1; + environment.flags = flag1; + environment.crc = crc1; + curdev = 0; + free (addr2); + } else if (!crc1_ok && crc2_ok) { + environment.data = addr2; + environment.flags = flag2; + environment.crc = crc2; + curdev = 1; + free (addr1); + } else if (!crc1_ok && !crc2_ok) { + fprintf (stderr, + "Warning: Bad CRC, using default environment\n"); + environment.data = default_environment; + curdev = 0; + free (addr2); + free (addr1); + } else if (flag1 == active_flag && flag2 == obsolete_flag) { + environment.data = addr1; + environment.flags = flag1; + environment.crc = crc1; + curdev = 0; + free (addr2); + } else if (flag1 == obsolete_flag && flag2 == active_flag) { + environment.data = addr2; + environment.flags = flag2; + environment.crc = crc2; + curdev = 1; + free (addr1); + } else if (flag1 == flag2) { + environment.data = addr1; + environment.flags = flag1; + environment.crc = crc1; + curdev = 0; + free (addr2); + } else if (flag1 == 0xFF) { + environment.data = addr1; + environment.flags = flag1; + environment.crc = crc1; + curdev = 0; + free (addr2); + } else if (flag2 == 0xFF) { + environment.data = addr2; + environment.flags = flag2; + environment.crc = crc2; + curdev = 1; + free (addr1); + } + } + return (0); +} + + +static int parse_config () +{ + struct stat st; + +#if defined(CONFIG_FILE) + /* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */ + if (get_config (CONFIG_FILE)) { + fprintf (stderr, + "Cannot parse config file: %s\n", strerror (errno)); + return 1; + } +#else + strcpy (DEVNAME (0), DEVICE1_NAME); + DEVOFFSET (0) = DEVICE1_OFFSET; + ENVSIZE (0) = ENV1_SIZE; + DEVESIZE (0) = DEVICE1_ESIZE; +#ifdef HAVE_REDUND + strcpy (DEVNAME (1), DEVICE2_NAME); + DEVOFFSET (1) = DEVICE2_OFFSET; + ENVSIZE (1) = ENV2_SIZE; + DEVESIZE (1) = DEVICE2_ESIZE; + HaveRedundEnv = 1; +#endif +#endif + if (stat (DEVNAME (0), &st)) { + fprintf (stderr, + "Cannot access MTD device %s: %s\n", + DEVNAME (0), strerror (errno)); + return 1; + } + + if (HaveRedundEnv && stat (DEVNAME (1), &st)) { + fprintf (stderr, + "Cannot access MTD device %s: %s\n", + DEVNAME (1), strerror (errno)); + return 1; + } + return 0; +} + +#if defined(CONFIG_FILE) +static int get_config (char *fname) +{ + FILE *fp; + int i = 0; + int rc; + char dump[128]; + + if ((fp = fopen (fname, "r")) == NULL) { + return 1; + } + + while ((i < 2) && ((rc = fscanf (fp, "%s %lx %lx %lx", + DEVNAME (i), + &DEVOFFSET (i), + &ENVSIZE (i), + &DEVESIZE (i) )) != EOF)) { + + /* Skip incomplete conversions and comment strings */ + if ((rc < 3) || (*DEVNAME (i) == '#')) { + fgets (dump, sizeof (dump), fp); /* Consume till end */ + continue; + } + + i++; + } + fclose (fp); + + HaveRedundEnv = i - 1; + if (!i) { /* No valid entries found */ + errno = EINVAL; + return 1; + } else + return 0; +} +#endif diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config new file mode 100644 index 0000000..2432bd8 --- /dev/null +++ b/tools/env/fw_env.config @@ -0,0 +1,7 @@ +# Configuration file for fw_(printenv/saveenv) utility. +# Up to two entries are valid, in this case the redundand +# environment sector is assumed present. + +# MTD device name Device offset Env. size Flash sector size +/dev/mtd1 0x0000 0x4000 0x4000 +/dev/mtd2 0x0000 0x4000 0x4000 diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h new file mode 100644 index 0000000..13c45a2 --- /dev/null +++ b/tools/env/fw_env.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * To build the utility with the run-time configuration + * uncomment the next line. + * See included "fw_env.config" sample file (TRAB board) + * for notes on configuration. + */ +#define CONFIG_FILE "/etc/fw_env.config" + +#define HAVE_REDUND /* For systems with 2 env sectors */ +#define DEVICE1_NAME "/dev/mtd1" +#define DEVICE2_NAME "/dev/mtd2" +#define DEVICE1_OFFSET 0x0000 +#define ENV1_SIZE 0x4000 +#define DEVICE1_ESIZE 0x4000 +#define DEVICE2_OFFSET 0x0000 +#define ENV2_SIZE 0x4000 +#define DEVICE2_ESIZE 0x4000 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" + +extern void fw_printenv(int argc, char *argv[]); +extern unsigned char *fw_getenv (unsigned char *name); +extern int fw_setenv (int argc, char *argv[]); + +extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned); diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c new file mode 100644 index 0000000..696e30e --- /dev/null +++ b/tools/env/fw_env_main.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Command line user interface to firmware (=U-Boot) environment. + * + * Implements: + * fw_printenv [ name ... ] + * - prints the values of the environment variables + * "name", or the whole environment if no names are + * specified + * fw_setenv name [ value ... ] + * - If a name without any values is given, the variable + * with this name is deleted from the environment; + * otherwise, all "value" arguments are concatenated, + * separated by sinlge blank characters, and the + * resulting string is assigned to the environment + * variable "name" + */ + +#include +#include +#include +#include "fw_env.h" + +#define CMD_PRINTENV "fw_printenv" +#define CMD_SETENV "fw_setenv" + +int +main(int argc, char *argv[]) +{ + char *p; + char *cmdname = *argv; + + if ((p = strrchr (cmdname, '/')) != NULL) { + cmdname = p + 1; + } + + if (strcmp(cmdname, CMD_PRINTENV) == 0) { + + fw_printenv (argc, argv); + + return (EXIT_SUCCESS); + + } else if (strcmp(cmdname, CMD_SETENV) == 0) { + + if (fw_setenv (argc, argv) != 0) + return (EXIT_FAILURE); + + return (EXIT_SUCCESS); + } + + fprintf (stderr, + "Identity crisis - may be called as `" CMD_PRINTENV + "' or as `" CMD_SETENV "' but not as `%s'\n", + cmdname); + return (EXIT_FAILURE); +} diff --git a/tools/envcrc.c b/tools/envcrc.c new file mode 100644 index 0000000..7b77183 --- /dev/null +++ b/tools/envcrc.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2001 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ /* Dirty trick to get only #defines */ +#endif +#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */ +#include +#undef __ASSEMBLY__ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_OFFSET +# define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +# endif +# if !defined(CFG_ENV_ADDR_REDUND) && defined(CFG_ENV_OFFSET_REDUND) +# define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + CFG_ENV_OFFSET_REDUND) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# if defined(CFG_ENV_ADDR_REDUND) && !defined(CFG_ENV_SIZE_REDUND) +# define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE +# endif +# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \ + ((CFG_ENV_ADDR + CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) +# define ENV_IS_EMBEDDED 1 +# endif +# if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND) +# define CFG_REDUNDAND_ENVIRONMENT 1 +# endif +#endif /* CFG_ENV_IS_IN_FLASH */ + +#ifdef CFG_REDUNDAND_ENVIRONMENT +# define ENV_HEADER_SIZE (sizeof(unsigned long) + 1) +#else +# define ENV_HEADER_SIZE (sizeof(unsigned long)) +#endif + +#define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE) + + +extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); + +#ifdef ENV_IS_EMBEDDED +extern unsigned int env_size; +extern unsigned char environment; +#endif /* ENV_IS_EMBEDDED */ + +int main (int argc, char **argv) +{ +#ifdef ENV_IS_EMBEDDED + int crc; + unsigned char *envptr = &environment, + *dataptr = envptr + ENV_HEADER_SIZE; + unsigned int datasize = ENV_SIZE; + + crc = crc32 (0, dataptr, datasize); + + /* Check if verbose mode is activated passing a parameter to the program */ + if (argc > 1) { + printf ("CRC32 from offset %08X to %08X of environment = %08X\n", + (unsigned int) (dataptr - envptr), + (unsigned int) (dataptr - envptr) + datasize, + crc); + } else { + printf ("0x%08X\n", crc); + } +#else + printf ("0\n"); +#endif + return EXIT_SUCCESS; +} diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile new file mode 100644 index 0000000..e7618b7 --- /dev/null +++ b/tools/gdb/Makefile @@ -0,0 +1,70 @@ +# +# (C) Copyright 2000 +# Murray Jensen +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +BINS = gdbsend gdbcont + +OBJS = gdbsend.o gdbcont.o error.o remote.o serial.o + +# +# Use native tools and options +# +CPPFLAGS = -I$(BFD_ROOT_DIR)/include +CFLAGS = $(HOST_CFLAGS) -O $(CPPFLAGS) +CC = $(HOSTCC) +MAKEDEPEND = makedepend + +HOSTOS := $(shell uname -s | sed -e 's/\([Cc][Yy][Gg][Ww][Ii][Nn]\).*/cygwin/') + +ifeq ($(HOSTOS),cygwin) + +all: +.depend: + +else # ! CYGWIN + +all: $(BINS) + +gdbsend: gdbsend.o error.o remote.o serial.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + +gdbcont: gdbcont.o error.o remote.o serial.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(BINS) core *.bak .depend + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) -I../include $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### + +endif # cygwin diff --git a/tools/gdb/error.c b/tools/gdb/error.c new file mode 100644 index 0000000..276a00a --- /dev/null +++ b/tools/gdb/error.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "error.h" + +char *pname; + +void +Warning(char *fmt, ...) +{ + va_list args; + + fprintf(stderr, "%s: WARNING: ", pname); + + va_start(args, fmt); + vfprintf(stderr, fmt, args); + va_end(args); + + fprintf(stderr, "\n"); +} + +void +Error(char *fmt, ...) +{ + va_list args; + + fprintf(stderr, "%s: ERROR: ", pname); + + va_start(args, fmt); + vfprintf(stderr, fmt, args); + va_end(args); + + fprintf(stderr, "\n"); + + exit(1); +} + +void +Perror(char *fmt, ...) +{ + va_list args; + int e = errno; + char *p; + + fprintf(stderr, "%s: ERROR: ", pname); + + va_start(args, fmt); + vfprintf(stderr, fmt, args); + va_end(args); + + if ((p = strerror(e)) == NULL || *p == '\0') + fprintf(stderr, ": Unknown Error (%d)\n", e); + else + fprintf(stderr, ": %s\n", p); + + exit(1); +} diff --git a/tools/gdb/error.h b/tools/gdb/error.h new file mode 100644 index 0000000..0698213 --- /dev/null +++ b/tools/gdb/error.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +extern char *pname; + +extern void Warning(char *, ...); +extern void Error(char *, ...); +extern void Perror(char *, ...); diff --git a/tools/gdb/gdbcont.c b/tools/gdb/gdbcont.c new file mode 100644 index 0000000..300545d --- /dev/null +++ b/tools/gdb/gdbcont.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "serial.h" +#include "error.h" +#include "remote.h" + +char *serialdev = "/dev/term/b"; +speed_t speed = B230400; +int verbose = 0; + +int +main(int ac, char **av) +{ + int c, sfd; + + if ((pname = strrchr(av[0], '/')) == NULL) + pname = av[0]; + else + pname++; + + while ((c = getopt(ac, av, "b:p:v")) != EOF) + switch (c) { + + case 'b': + if ((speed = cvtspeed(optarg)) == B0) + Error("can't decode baud rate specified in -b option"); + break; + + case 'p': + serialdev = optarg; + break; + + case 'v': + verbose = 1; + break; + + default: + usage: + fprintf(stderr, "Usage: %s [-b bps] [-p dev] [-v]\n", pname); + exit(1); + } + if (optind != ac) + goto usage; + + if (verbose) + fprintf(stderr, "Opening serial port and sending continue...\n"); + + if ((sfd = serialopen(serialdev, speed)) < 0) + Perror("open of serial device '%s' failed", serialdev); + + remote_desc = sfd; + remote_reset(); + remote_continue(); + + if (serialclose(sfd) < 0) + Perror("close of serial device '%s' failed", serialdev); + + if (verbose) + fprintf(stderr, "Done.\n"); + + return (0); +} diff --git a/tools/gdb/gdbsend.c b/tools/gdb/gdbsend.c new file mode 100644 index 0000000..8cd8347 --- /dev/null +++ b/tools/gdb/gdbsend.c @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "serial.h" +#include "error.h" +#include "remote.h" + +char *serialdev = "/dev/term/b"; +speed_t speed = B230400; +int verbose = 0, docont = 0; +unsigned long addr = 0x10000UL; + +int +main(int ac, char **av) +{ + int c, sfd, ifd; + char *ifn, *image; + struct stat ist; + + if ((pname = strrchr(av[0], '/')) == NULL) + pname = av[0]; + else + pname++; + + while ((c = getopt(ac, av, "a:b:cp:v")) != EOF) + switch (c) { + + case 'a': { + char *ep; + + addr = strtol(optarg, &ep, 0); + if (ep == optarg || *ep != '\0') + Error("can't decode address specified in -a option"); + break; + } + + case 'b': + if ((speed = cvtspeed(optarg)) == B0) + Error("can't decode baud rate specified in -b option"); + break; + + case 'c': + docont = 1; + break; + + case 'p': + serialdev = optarg; + break; + + case 'v': + verbose = 1; + break; + + default: + usage: + fprintf(stderr, + "Usage: %s [-a addr] [-b bps] [-c] [-p dev] [-v] imagefile\n", + pname); + exit(1); + } + + if (optind != ac - 1) + goto usage; + ifn = av[optind++]; + + if (verbose) + fprintf(stderr, "Opening file and reading image...\n"); + + if ((ifd = open(ifn, O_RDONLY)) < 0) + Perror("can't open kernel image file '%s'", ifn); + + if (fstat(ifd, &ist) < 0) + Perror("fstat '%s' failed", ifn); + + if ((image = (char *)malloc(ist.st_size)) == NULL) + Perror("can't allocate %ld bytes for image", ist.st_size); + + if ((c = read(ifd, image, ist.st_size)) < 0) + Perror("read of %d bytes from '%s' failed", ist.st_size, ifn); + + if (c != ist.st_size) + Error("read of %ld bytes from '%s' failed (%d)", ist.st_size, ifn, c); + + if (close(ifd) < 0) + Perror("close of '%s' failed", ifn); + + if (verbose) + fprintf(stderr, "Opening serial port and sending image...\n"); + + if ((sfd = serialopen(serialdev, speed)) < 0) + Perror("open of serial device '%s' failed", serialdev); + + remote_desc = sfd; + remote_reset(); + remote_write_bytes(addr, image, ist.st_size); + + if (docont) { + if (verbose) + fprintf(stderr, "[continue]"); + remote_continue(); + } + + if (serialclose(sfd) < 0) + Perror("close of serial device '%s' failed", serialdev); + + if (verbose) + fprintf(stderr, "Done.\n"); + + return (0); +} diff --git a/tools/gdb/remote.c b/tools/gdb/remote.c new file mode 100644 index 0000000..f40b6c6 --- /dev/null +++ b/tools/gdb/remote.c @@ -0,0 +1,928 @@ +/* + * taken from gdb/remote.c + * + * I am only interested in the write to memory stuff - everything else + * has been ripped out + * + * all the copyright notices etc have been left in + */ + +/* enough so that it will compile */ +#include +#include +#include +#include + +/*nicked from gcc..*/ + +#ifndef alloca +#ifdef __GNUC__ +#define alloca __builtin_alloca +#else /* not GNU C. */ +#if (!defined (__STDC__) && defined (sparc)) || defined (__sparc__) || defined (__sparc) || defined (__sgi) +#include +#else /* not sparc */ +#if defined (MSDOS) && !defined (__TURBOC__) +#include +#else /* not MSDOS, or __TURBOC__ */ +#if defined(_AIX) +#include + #pragma alloca +#else /* not MSDOS, __TURBOC__, or _AIX */ +#ifdef __hpux +#endif /* __hpux */ +#endif /* not _AIX */ +#endif /* not MSDOS, or __TURBOC__ */ +#endif /* not sparc. */ +#endif /* not GNU C. */ +#ifdef __cplusplus +extern "C" { +#endif + void* alloca(size_t); +#ifdef __cplusplus +} +#endif +#endif /* alloca not defined. */ + + +#include "serial.h" +#include "error.h" +#include "remote.h" +#define REGISTER_BYTES 0 +#define fprintf_unfiltered fprintf +#define fprintf_filtered fprintf +#define fputs_unfiltered fputs +#define fputs_filtered fputs +#define fputc_unfiltered fputc +#define fputc_filtered fputc +#define printf_unfiltered printf +#define printf_filtered printf +#define puts_unfiltered puts +#define puts_filtered puts +#define putchar_unfiltered putchar +#define putchar_filtered putchar +#define fputstr_unfiltered(a,b,c) fputs((a), (c)) +#define gdb_stdlog stderr +#define SERIAL_READCHAR(fd,timo) serialreadchar((fd), (timo)) +#define SERIAL_WRITE(fd, addr, len) serialwrite((fd), (addr), (len)) +#define error Error +#define perror_with_name Perror +#define gdb_flush fflush +#define max(a,b) (((a)>(b))?(a):(b)) +#define min(a,b) (((a)<(b))?(a):(b)) +#define target_mourn_inferior() {} +#define ULONGEST unsigned long +#define CORE_ADDR unsigned long + +static int putpkt (char *); +static int putpkt_binary(char *, int); +static void getpkt (char *, int); + +static int remote_debug = 0, remote_register_buf_size = 0, watchdog = 0; + +int remote_desc = -1, remote_timeout = 10; + +static void +fputstrn_unfiltered(char *s, int n, int x, FILE *fp) +{ + while (n-- > 0) + fputc(*s++, fp); +} + +void +remote_reset(void) +{ + SERIAL_WRITE(remote_desc, "+", 1); +} + +void +remote_continue(void) +{ + putpkt("c"); +} + +/* Remote target communications for serial-line targets in custom GDB protocol + Copyright 1988, 91, 92, 93, 94, 95, 96, 97, 98, 1999 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ +/* *INDENT-OFF* */ +/* Remote communication protocol. + + A debug packet whose contents are + is encapsulated for transmission in the form: + + $ # CSUM1 CSUM2 + + must be ASCII alphanumeric and cannot include characters + '$' or '#'. If starts with two characters followed by + ':', then the existing stubs interpret this as a sequence number. + + CSUM1 and CSUM2 are ascii hex representation of an 8-bit + checksum of , the most significant nibble is sent first. + the hex digits 0-9,a-f are used. + + Receiver responds with: + + + - if CSUM is correct and ready for next packet + - - if CSUM is incorrect + + is as follows: + Most values are encoded in ascii hex digits. Signal numbers are according + to the numbering in target.h. + + Request Packet + + set thread Hct... Set thread for subsequent operations. + c = 'c' for thread used in step and + continue; t... can be -1 for all + threads. + c = 'g' for thread used in other + operations. If zero, pick a thread, + any thread. + reply OK for success + ENN for an error. + + read registers g + reply XX....X Each byte of register data + is described by two hex digits. + Registers are in the internal order + for GDB, and the bytes in a register + are in the same order the machine uses. + or ENN for an error. + + write regs GXX..XX Each byte of register data + is described by two hex digits. + reply OK for success + ENN for an error + + write reg Pn...=r... Write register n... with value r..., + which contains two hex digits for each + byte in the register (target byte + order). + reply OK for success + ENN for an error + (not supported by all stubs). + + read mem mAA..AA,LLLL AA..AA is address, LLLL is length. + reply XX..XX XX..XX is mem contents + Can be fewer bytes than requested + if able to read only part of the data. + or ENN NN is errno + + write mem MAA..AA,LLLL:XX..XX + AA..AA is address, + LLLL is number of bytes, + XX..XX is data + reply OK for success + ENN for an error (this includes the case + where only part of the data was + written). + + write mem XAA..AA,LLLL:XX..XX + (binary) AA..AA is address, + LLLL is number of bytes, + XX..XX is binary data + reply OK for success + ENN for an error + + continue cAA..AA AA..AA is address to resume + If AA..AA is omitted, + resume at same address. + + step sAA..AA AA..AA is address to resume + If AA..AA is omitted, + resume at same address. + + continue with Csig;AA..AA Continue with signal sig (hex signal + signal number). If ;AA..AA is omitted, + resume at same address. + + step with Ssig;AA..AA Like 'C' but step not continue. + signal + + last signal ? Reply the current reason for stopping. + This is the same reply as is generated + for step or cont : SAA where AA is the + signal number. + + detach D Reply OK. + + There is no immediate reply to step or cont. + The reply comes when the machine stops. + It is SAA AA is the signal number. + + or... TAAn...:r...;n...:r...;n...:r...; + AA = signal number + n... = register number (hex) + r... = register contents + n... = `thread' + r... = thread process ID. This is + a hex integer. + n... = other string not starting + with valid hex digit. + gdb should ignore this n,r pair + and go on to the next. This way + we can extend the protocol. + or... WAA The process exited, and AA is + the exit status. This is only + applicable for certains sorts of + targets. + or... XAA The process terminated with signal + AA. + or (obsolete) NAA;tttttttt;dddddddd;bbbbbbbb + AA = signal number + tttttttt = address of symbol "_start" + dddddddd = base of data section + bbbbbbbb = base of bss section. + Note: only used by Cisco Systems + targets. The difference between this + reply and the "qOffsets" query is that + the 'N' packet may arrive spontaneously + whereas the 'qOffsets' is a query + initiated by the host debugger. + or... OXX..XX XX..XX is hex encoding of ASCII data. This + can happen at any time while the + program is running and the debugger + should continue to wait for + 'W', 'T', etc. + + thread alive TXX Find out if the thread XX is alive. + reply OK thread is still alive + ENN thread is dead + + remote restart RXX Restart the remote server + + extended ops ! Use the extended remote protocol. + Sticky -- only needs to be set once. + + kill request k + + toggle debug d toggle debug flag (see 386 & 68k stubs) + reset r reset -- see sparc stub. + reserved On other requests, the stub should + ignore the request and send an empty + response ($#). This way + we can extend the protocol and GDB + can tell whether the stub it is + talking to uses the old or the new. + search tAA:PP,MM Search backwards starting at address + AA for a match with pattern PP and + mask MM. PP and MM are 4 bytes. + Not supported by all stubs. + + general query qXXXX Request info about XXXX. + general set QXXXX=yyyy Set value of XXXX to yyyy. + query sect offs qOffsets Get section offsets. Reply is + Text=xxx;Data=yyy;Bss=zzz + + Responses can be run-length encoded to save space. A '*' means that + the next character is an ASCII encoding giving a repeat count which + stands for that many repititions of the character preceding the '*'. + The encoding is n+29, yielding a printable character where n >=3 + (which is where rle starts to win). Don't use an n > 126. + + So + "0* " means the same as "0000". */ +/* *INDENT-ON* */ + +/* This variable (available to the user via "set remotebinarydownload") + dictates whether downloads are sent in binary (via the 'X' packet). + We assume that the stub can, and attempt to do it. This will be cleared if + the stub does not understand it. This switch is still needed, though + in cases when the packet is supported in the stub, but the connection + does not allow it (i.e., 7-bit serial connection only). */ +static int remote_binary_download = 1; + +/* Have we already checked whether binary downloads work? */ +static int remote_binary_checked; + +/* Maximum number of bytes to read/write at once. The value here + is chosen to fill up a packet (the headers account for the 32). */ +#define MAXBUFBYTES(N) (((N)-32)/2) + +/* Having this larger than 400 causes us to be incompatible with m68k-stub.c + and i386-stub.c. Normally, no one would notice because it only matters + for writing large chunks of memory (e.g. in downloads). Also, this needs + to be more than 400 if required to hold the registers (see below, where + we round it up based on REGISTER_BYTES). */ +/* Round up PBUFSIZ to hold all the registers, at least. */ +#define PBUFSIZ ((REGISTER_BYTES > MAXBUFBYTES (400)) \ + ? (REGISTER_BYTES * 2 + 32) \ + : 400) + + +/* This variable sets the number of bytes to be written to the target + in a single packet. Normally PBUFSIZ is satisfactory, but some + targets need smaller values (perhaps because the receiving end + is slow). */ + +static int remote_write_size = 0x7fffffff; + +/* This variable sets the number of bits in an address that are to be + sent in a memory ("M" or "m") packet. Normally, after stripping + leading zeros, the entire address would be sent. This variable + restricts the address to REMOTE_ADDRESS_SIZE bits. HISTORY: The + initial implementation of remote.c restricted the address sent in + memory packets to ``host::sizeof long'' bytes - (typically 32 + bits). Consequently, for 64 bit targets, the upper 32 bits of an + address was never sent. Since fixing this bug may cause a break in + some remote targets this variable is principly provided to + facilitate backward compatibility. */ + +static int remote_address_size; + +/* Convert hex digit A to a number. */ + +static int +fromhex (int a) +{ + if (a >= '0' && a <= '9') + return a - '0'; + else if (a >= 'a' && a <= 'f') + return a - 'a' + 10; + else if (a >= 'A' && a <= 'F') + return a - 'A' + 10; + else { + error ("Reply contains invalid hex digit %d", a); + return -1; + } +} + +/* Convert number NIB to a hex digit. */ + +static int +tohex (int nib) +{ + if (nib < 10) + return '0' + nib; + else + return 'a' + nib - 10; +} + +/* Return the number of hex digits in num. */ + +static int +hexnumlen (ULONGEST num) +{ + int i; + + for (i = 0; num != 0; i++) + num >>= 4; + + return max (i, 1); +} + +/* Set BUF to the hex digits representing NUM. */ + +static int +hexnumstr (char *buf, ULONGEST num) +{ + int i; + int len = hexnumlen (num); + + buf[len] = '\0'; + + for (i = len - 1; i >= 0; i--) + { + buf[i] = "0123456789abcdef"[(num & 0xf)]; + num >>= 4; + } + + return len; +} + +/* Mask all but the least significant REMOTE_ADDRESS_SIZE bits. */ + +static CORE_ADDR +remote_address_masked (CORE_ADDR addr) +{ + if (remote_address_size > 0 + && remote_address_size < (sizeof (ULONGEST) * 8)) + { + /* Only create a mask when that mask can safely be constructed + in a ULONGEST variable. */ + ULONGEST mask = 1; + mask = (mask << remote_address_size) - 1; + addr &= mask; + } + return addr; +} + +/* Determine whether the remote target supports binary downloading. + This is accomplished by sending a no-op memory write of zero length + to the target at the specified address. It does not suffice to send + the whole packet, since many stubs strip the eighth bit and subsequently + compute a wrong checksum, which causes real havoc with remote_write_bytes. + + NOTE: This can still lose if the serial line is not eight-bit clean. In + cases like this, the user should clear "remotebinarydownload". */ +static void +check_binary_download (CORE_ADDR addr) +{ + if (remote_binary_download && !remote_binary_checked) + { + char *buf = alloca (PBUFSIZ); + char *p; + remote_binary_checked = 1; + + p = buf; + *p++ = 'X'; + p += hexnumstr (p, (ULONGEST) addr); + *p++ = ','; + p += hexnumstr (p, (ULONGEST) 0); + *p++ = ':'; + *p = '\0'; + + putpkt_binary (buf, (int) (p - buf)); + getpkt (buf, 0); + + if (buf[0] == '\0') + remote_binary_download = 0; + } + + if (remote_debug) + { + if (remote_binary_download) + fprintf_unfiltered (gdb_stdlog, + "binary downloading suppported by target\n"); + else + fprintf_unfiltered (gdb_stdlog, + "binary downloading NOT suppported by target\n"); + } +} + +/* Write memory data directly to the remote machine. + This does not inform the data cache; the data cache uses this. + MEMADDR is the address in the remote memory space. + MYADDR is the address of the buffer in our space. + LEN is the number of bytes. + + Returns number of bytes transferred, or 0 for error. */ + +int +remote_write_bytes (memaddr, myaddr, len) + CORE_ADDR memaddr; + char *myaddr; + int len; +{ + unsigned char *buf = alloca (PBUFSIZ); + int max_buf_size; /* Max size of packet output buffer */ + int origlen; + extern int verbose; + + /* Verify that the target can support a binary download */ + check_binary_download (memaddr); + + /* Chop the transfer down if necessary */ + + max_buf_size = min (remote_write_size, PBUFSIZ); + if (remote_register_buf_size != 0) + max_buf_size = min (max_buf_size, remote_register_buf_size); + + /* Subtract header overhead from max payload size - $M,:#nn */ + max_buf_size -= 2 + hexnumlen (memaddr + len - 1) + 1 + hexnumlen (len) + 4; + + origlen = len; + while (len > 0) + { + unsigned char *p, *plen; + int todo; + int i; + + /* construct "M"","":" */ + /* sprintf (buf, "M%lx,%x:", (unsigned long) memaddr, todo); */ + memaddr = remote_address_masked (memaddr); + p = buf; + if (remote_binary_download) + { + *p++ = 'X'; + todo = min (len, max_buf_size); + } + else + { + *p++ = 'M'; + todo = min (len, max_buf_size / 2); /* num bytes that will fit */ + } + + p += hexnumstr ((char *)p, (ULONGEST) memaddr); + *p++ = ','; + + plen = p; /* remember where len field goes */ + p += hexnumstr ((char *)p, (ULONGEST) todo); + *p++ = ':'; + *p = '\0'; + + /* We send target system values byte by byte, in increasing byte + addresses, each byte encoded as two hex characters (or one + binary character). */ + if (remote_binary_download) + { + int escaped = 0; + for (i = 0; + (i < todo) && (i + escaped) < (max_buf_size - 2); + i++) + { + switch (myaddr[i] & 0xff) + { + case '$': + case '#': + case 0x7d: + /* These must be escaped */ + escaped++; + *p++ = 0x7d; + *p++ = (myaddr[i] & 0xff) ^ 0x20; + break; + default: + *p++ = myaddr[i] & 0xff; + break; + } + } + + if (i < todo) + { + /* Escape chars have filled up the buffer prematurely, + and we have actually sent fewer bytes than planned. + Fix-up the length field of the packet. */ + + /* FIXME: will fail if new len is a shorter string than + old len. */ + + plen += hexnumstr ((char *)plen, (ULONGEST) i); + *plen++ = ':'; + } + } + else + { + for (i = 0; i < todo; i++) + { + *p++ = tohex ((myaddr[i] >> 4) & 0xf); + *p++ = tohex (myaddr[i] & 0xf); + } + *p = '\0'; + } + + putpkt_binary ((char *)buf, (int) (p - buf)); + getpkt ((char *)buf, 0); + + if (buf[0] == 'E') + { + /* There is no correspondance between what the remote protocol uses + for errors and errno codes. We would like a cleaner way of + representing errors (big enough to include errno codes, bfd_error + codes, and others). But for now just return EIO. */ + errno = EIO; + return 0; + } + + /* Increment by i, not by todo, in case escape chars + caused us to send fewer bytes than we'd planned. */ + myaddr += i; + memaddr += i; + len -= i; + + if (verbose) + putc('.', stderr); + } + return origlen; +} + +/* Stuff for dealing with the packets which are part of this protocol. + See comment at top of file for details. */ + +/* Read a single character from the remote end, masking it down to 7 bits. */ + +static int +readchar (int timeout) +{ + int ch; + + ch = SERIAL_READCHAR (remote_desc, timeout); + + switch (ch) + { + case SERIAL_EOF: + error ("Remote connection closed"); + case SERIAL_ERROR: + perror_with_name ("Remote communication error"); + case SERIAL_TIMEOUT: + return ch; + default: + return ch & 0x7f; + } +} + +static int +putpkt (buf) + char *buf; +{ + return putpkt_binary (buf, strlen (buf)); +} + +/* Send a packet to the remote machine, with error checking. The data + of the packet is in BUF. The string in BUF can be at most PBUFSIZ - 5 + to account for the $, # and checksum, and for a possible /0 if we are + debugging (remote_debug) and want to print the sent packet as a string */ + +static int +putpkt_binary (buf, cnt) + char *buf; + int cnt; +{ + int i; + unsigned char csum = 0; + char *buf2 = alloca (PBUFSIZ); + char *junkbuf = alloca (PBUFSIZ); + + int ch; + int tcount = 0; + char *p; + + /* Copy the packet into buffer BUF2, encapsulating it + and giving it a checksum. */ + + if (cnt > BUFSIZ - 5) /* Prosanity check */ + abort (); + + p = buf2; + *p++ = '$'; + + for (i = 0; i < cnt; i++) + { + csum += buf[i]; + *p++ = buf[i]; + } + *p++ = '#'; + *p++ = tohex ((csum >> 4) & 0xf); + *p++ = tohex (csum & 0xf); + + /* Send it over and over until we get a positive ack. */ + + while (1) + { + int started_error_output = 0; + + if (remote_debug) + { + *p = '\0'; + fprintf_unfiltered (gdb_stdlog, "Sending packet: "); + fputstrn_unfiltered (buf2, p - buf2, 0, gdb_stdlog); + fprintf_unfiltered (gdb_stdlog, "..."); + gdb_flush (gdb_stdlog); + } + if (SERIAL_WRITE (remote_desc, buf2, p - buf2)) + perror_with_name ("putpkt: write failed"); + + /* read until either a timeout occurs (-2) or '+' is read */ + while (1) + { + ch = readchar (remote_timeout); + + if (remote_debug) + { + switch (ch) + { + case '+': + case SERIAL_TIMEOUT: + case '$': + if (started_error_output) + { + putchar_unfiltered ('\n'); + started_error_output = 0; + } + } + } + + switch (ch) + { + case '+': + if (remote_debug) + fprintf_unfiltered (gdb_stdlog, "Ack\n"); + return 1; + case SERIAL_TIMEOUT: + tcount++; + if (tcount > 3) + return 0; + break; /* Retransmit buffer */ + case '$': + { + /* It's probably an old response, and we're out of sync. + Just gobble up the packet and ignore it. */ + getpkt (junkbuf, 0); + continue; /* Now, go look for + */ + } + default: + if (remote_debug) + { + if (!started_error_output) + { + started_error_output = 1; + fprintf_unfiltered (gdb_stdlog, "putpkt: Junk: "); + } + fputc_unfiltered (ch & 0177, gdb_stdlog); + } + continue; + } + break; /* Here to retransmit */ + } + +#if 0 + /* This is wrong. If doing a long backtrace, the user should be + able to get out next time we call QUIT, without anything as + violent as interrupt_query. If we want to provide a way out of + here without getting to the next QUIT, it should be based on + hitting ^C twice as in remote_wait. */ + if (quit_flag) + { + quit_flag = 0; + interrupt_query (); + } +#endif + } +} + +/* Come here after finding the start of the frame. Collect the rest + into BUF, verifying the checksum, length, and handling run-length + compression. Returns 0 on any error, 1 on success. */ + +static int +read_frame (char *buf) +{ + unsigned char csum; + char *bp; + int c; + + csum = 0; + bp = buf; + + while (1) + { + c = readchar (remote_timeout); + + switch (c) + { + case SERIAL_TIMEOUT: + if (remote_debug) + fputs_filtered ("Timeout in mid-packet, retrying\n", gdb_stdlog); + return 0; + case '$': + if (remote_debug) + fputs_filtered ("Saw new packet start in middle of old one\n", + gdb_stdlog); + return 0; /* Start a new packet, count retries */ + case '#': + { + unsigned char pktcsum; + + *bp = '\000'; + + pktcsum = fromhex (readchar (remote_timeout)) << 4; + pktcsum |= fromhex (readchar (remote_timeout)); + + if (csum == pktcsum) + { + return 1; + } + + if (remote_debug) + { + fprintf_filtered (gdb_stdlog, + "Bad checksum, sentsum=0x%x, csum=0x%x, buf=", + pktcsum, csum); + fputs_filtered (buf, gdb_stdlog); + fputs_filtered ("\n", gdb_stdlog); + } + return 0; + } + case '*': /* Run length encoding */ + csum += c; + c = readchar (remote_timeout); + csum += c; + c = c - ' ' + 3; /* Compute repeat count */ + + if (c > 0 && c < 255 && bp + c - 1 < buf + PBUFSIZ - 1) + { + memset (bp, *(bp - 1), c); + bp += c; + continue; + } + + *bp = '\0'; + printf_filtered ("Repeat count %d too large for buffer: ", c); + puts_filtered (buf); + puts_filtered ("\n"); + return 0; + default: + if (bp < buf + PBUFSIZ - 1) + { + *bp++ = c; + csum += c; + continue; + } + + *bp = '\0'; + puts_filtered ("Remote packet too long: "); + puts_filtered (buf); + puts_filtered ("\n"); + + return 0; + } + } +} + +/* Read a packet from the remote machine, with error checking, and + store it in BUF. BUF is expected to be of size PBUFSIZ. If + FOREVER, wait forever rather than timing out; this is used while + the target is executing user code. */ + +static void +getpkt (buf, forever) + char *buf; + int forever; +{ + int c; + int tries; + int timeout; + int val; + + strcpy (buf, "timeout"); + + if (forever) + { + timeout = watchdog > 0 ? watchdog : -1; + } + + else + timeout = remote_timeout; + +#define MAX_TRIES 3 + + for (tries = 1; tries <= MAX_TRIES; tries++) + { + /* This can loop forever if the remote side sends us characters + continuously, but if it pauses, we'll get a zero from readchar + because of timeout. Then we'll count that as a retry. */ + + /* Note that we will only wait forever prior to the start of a packet. + After that, we expect characters to arrive at a brisk pace. They + should show up within remote_timeout intervals. */ + + do + { + c = readchar (timeout); + + if (c == SERIAL_TIMEOUT) + { + if (forever) /* Watchdog went off. Kill the target. */ + { + target_mourn_inferior (); + error ("Watchdog has expired. Target detached.\n"); + } + if (remote_debug) + fputs_filtered ("Timed out.\n", gdb_stdlog); + goto retry; + } + } + while (c != '$'); + + /* We've found the start of a packet, now collect the data. */ + + val = read_frame (buf); + + if (val == 1) + { + if (remote_debug) + { + fprintf_unfiltered (gdb_stdlog, "Packet received: "); + fputstr_unfiltered (buf, 0, gdb_stdlog); + fprintf_unfiltered (gdb_stdlog, "\n"); + } + SERIAL_WRITE (remote_desc, "+", 1); + return; + } + + /* Try the whole thing again. */ + retry: + SERIAL_WRITE (remote_desc, "-", 1); + } + + /* We have tried hard enough, and just can't receive the packet. Give up. */ + + printf_unfiltered ("Ignoring packet error, continuing...\n"); + SERIAL_WRITE (remote_desc, "+", 1); +} diff --git a/tools/gdb/remote.h b/tools/gdb/remote.h new file mode 100644 index 0000000..f14dacb --- /dev/null +++ b/tools/gdb/remote.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +extern int remote_desc, remote_timeout; + +extern void remote_reset(void); +extern void remote_continue(void); +extern int remote_write_bytes(unsigned long, char *, int); diff --git a/tools/gdb/serial.c b/tools/gdb/serial.c new file mode 100644 index 0000000..2f2e529 --- /dev/null +++ b/tools/gdb/serial.c @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "serial.h" + +#if defined(__sun__) || \ + defined(__OpenBSD__) || \ + defined(__FreeBSD__) || \ + defined(__NetBSD__) || \ + defined(__APPLE__) +static struct termios tios = { BRKINT, 0, B115200|CS8|CREAD, 0, { 0 } }; +#else +static struct termios tios = { BRKINT, 0, B115200|CS8|CREAD, 0, 0 }; +#endif + +static struct speedmap { + char *str; + speed_t val; +} speedmap[] = { + { "50", B50 }, { "75", B75 }, { "110", B110 }, + { "134", B134 }, { "150", B150 }, { "200", B200 }, + { "300", B300 }, { "600", B600 }, { "1200", B1200 }, + { "1800", B1800 }, { "2400", B2400 }, { "4800", B4800 }, + { "9600", B9600 }, { "19200", B19200 }, { "38400", B38400 }, + { "57600", B57600 }, +#ifdef B76800 + { "76800", B76800 }, +#endif + { "115200", B115200 }, +#ifdef B153600 + { "153600", B153600 }, +#endif + { "230400", B230400 }, +#ifdef B307200 + { "307200", B307200 }, +#endif +#ifdef B460800 + { "460800", B460800 } +#endif +}; +static int nspeeds = sizeof speedmap / sizeof speedmap[0]; + +speed_t +cvtspeed(char *str) +{ + struct speedmap *smp = speedmap, *esmp = &speedmap[nspeeds]; + + while (smp < esmp) { + if (strcmp(str, smp->str) == 0) + return (smp->val); + smp++; + } + return B0; +} + +int +serialopen(char *device, speed_t speed) +{ + int fd; + + if (cfsetospeed(&tios, speed) < 0) + return -1; + + if ((fd = open(device, O_RDWR)) < 0) + return -1; + + if (tcsetattr(fd, TCSAFLUSH, &tios) < 0) { + (void)close(fd); + return -1; + } + + return fd; +} + +int +serialreadchar(int fd, int timeout) +{ + fd_set fds; + struct timeval tv; + int n; + char ch; + + tv.tv_sec = timeout; + tv.tv_usec = 0; + + FD_ZERO(&fds); + FD_SET(fd, &fds); + + /* this is a fucking horrible quick hack - fix this */ + + if ((n = select(fd + 1, &fds, 0, 0, &tv)) < 0) + return SERIAL_ERROR; + + if (n == 0) + return SERIAL_TIMEOUT; + + if ((n = read(fd, &ch, 1)) < 0) + return SERIAL_ERROR; + + if (n == 0) + return SERIAL_EOF; + + return ch; +} + +int +serialwrite(int fd, char *buf, int len) +{ + int n; + + do { + n = write(fd, buf, len); + if (n < 0) + return 1; + len -= n; + buf += n; + } while (len > 0); + return 0; +} + +int +serialclose(int fd) +{ + return close(fd); +} diff --git a/tools/gdb/serial.h b/tools/gdb/serial.h new file mode 100644 index 0000000..3ed509e --- /dev/null +++ b/tools/gdb/serial.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2000 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define SERIAL_ERROR -1 /* General error, see errno for details */ +#define SERIAL_TIMEOUT -2 +#define SERIAL_EOF -3 + +extern speed_t cvtspeed(char *); +extern int serialopen(char *, speed_t); +extern int serialreadchar(int, int); +extern int serialwrite(int, char *, int); +extern int serialclose(int); diff --git a/tools/gen_eth_addr.c b/tools/gen_eth_addr.c new file mode 100644 index 0000000..75be385 --- /dev/null +++ b/tools/gen_eth_addr.c @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2001 + * Murray Jensen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +int +main(int argc, char *argv[]) +{ + unsigned long ethaddr_low, ethaddr_high; + + srandom(time(0) | getpid()); + + /* + * setting the 2nd LSB in the most significant byte of + * the address makes it a locally administered ethernet + * address + */ + ethaddr_high = (random() & 0xfeff) | 0x0200; + ethaddr_low = random(); + + printf("%02lx:%02lx:%02lx:%02lx:%02lx:%02lx\n", + ethaddr_high >> 8, ethaddr_high & 0xff, + ethaddr_low >> 24, (ethaddr_low >> 16) & 0xff, + (ethaddr_low >> 8) & 0xff, ethaddr_low & 0xff); + + return (0); +} diff --git a/tools/img2brec.sh b/tools/img2brec.sh new file mode 100755 index 0000000..0fcdba2 --- /dev/null +++ b/tools/img2brec.sh @@ -0,0 +1,388 @@ +#!/bin/sh + +# This script converts binary files (u-boot.bin) into so called +# bootstrap records that are accepted by Motorola's MC9328MX1/L +# (a.k.a. DragaonBall i.MX) in "Bootstrap Mode" +# +# The code for the SynchFlash programming routines is taken from +# Bootloader\Bin\SyncFlash\programBoot_b.txt contained in +# Motorolas LINUX_BSP_0_3_8.tar.gz +# +# The script could easily extended for AMD flash routines. +# +# 2004-06-23 - steven.scholz@imc-berlin.de + +################################################################################# +# From the posting to the U-Boot-Users mailing list, 23 Jun 2004: +# =============================================================== +# I just hacked a simple script that converts u-boot.bin into a text file +# containg processor init code, SynchFlash programming code and U-Boot data in +# form of so called b-records. +# +# This can be used to programm U-Boot into (Synch)Flash using the Bootstrap +# Mode of the MC9328MX1/L +# +# 0AFE1F3410202E2E2E000000002073756363656564/ +# 0AFE1F44102E0A0000206661696C656420210A0000/ +# 0AFE100000 +# ... +# MX1ADS Sync-flash Programming Utility v0.5 2002/08/21 +# +# Source address (stored in 0x0AFE0000): 0x0A000000 +# Target address (stored in 0x0AFE0004): 0x0C000000 +# Size (stored in 0x0AFE0008): 0x0001A320 +# +# Press any key to start programming ... +# Erasing ... +# Blank checking ... +# Programming ... +# Verifying flash ... succeed. +# +# Programming finished. +# +# So no need for a BDI2000 anymore... ;-) +# +# This is working on my MX1ADS eval board. Hope this could be useful for +# someone. +################################################################################# + +if [ "$#" -lt 1 -o "$#" -gt 2 ] ; then + echo "Usage: $0 infile [outfile]" >&2 + echo " $0 u-boot.bin [u-boot.brec]" >&2 + exit 1 +fi + +if [ "$#" -ge 1 ] ; then + INFILE=$1 +fi + +if [ ! -f $INFILE ] ; then + echo "Error: file '$INFILE' does not exist." >&2 + exit 1 +fi + +FILESIZE=`filesize $INFILE` + +output_init() +{ +echo "\ +******************************************** +* Initialize I/O Pad Driving Strength * +******************************************** +0021B80CC4000003AB +******************************************** +* Initialize SDRAM * +******************************************** +00221000C492120200 ; pre-charge command +08200000E4 ; special read + +00221000C4A2120200 ; auto-refresh command +08000000E4 ; 8 special read +08000000E4 ; 8 special read +08000000E4 ; 8 special read +08000000E4 ; 8 special read +08000000E4 ; 8 special read +08000000E4 ; 8 special read +08000000E4 ; 8 special read +08000000E4 ; 8 special read + +00221000C4B2120200 ; set mode register +08111800E4 ; special read + +00221000C482124200 ; set normal mode + " +} + +output_uboot() +{ +echo "\ +******************************************** +* U-Boot image as bootstrap records * +* will be stored in SDRAM at 0x0A000000 * +******************************************** + " + +cat $INFILE | \ +hexdump -v -e "\"0A0%05.5_ax10\" 16/1 \"%02x\"\"\r\n\"" | \ +tr [:lower:] [:upper:] +} + +output_flashprog() +{ +echo "\ +******************************************** +* Address of arguments to flashProg * +* ---------------------------------------- * +* Source : 0x0A000000 * +* Destination : 0x0C000000 * " + +# get the real size of the U-Boot image +printf "* Size : 0x%08X *\r\n" $FILESIZE +printf "********************************************\r\n" +printf "0AFE0000CC0A0000000C000000%08X\r\n" $FILESIZE + +#;0AFE0000CC0A0000000C00000000006000 + +echo "\ +******************************************** +* Flash Program * +******************************************** +0AFE10001008D09FE5AC0000EA00F0A0E1A42DFE0A +0AFE1010100080FE0A0DC0A0E100D82DE904B04CE2 +0AFE1020109820A0E318309FE5003093E5033082E0 +0AFE103010003093E5013003E2FF3003E20300A0E1 +0AFE10401000A81BE9A01DFE0A0DC0A0E100D82DE9 +0AFE10501004B04CE204D04DE20030A0E10D304BE5 +0AFE1060109820A0E330309FE5003093E5033082E0 +0AFE107010003093E5013903E2000053E3F7FFFF0A +0AFE1080104020A0E310309FE5003093E5032082E0 +0AFE1090100D305BE5003082E500A81BE9A01DFE0A +0AFE10A0100DC0A0E100D82DE904B04CE20000A0E1 +0AFE10B010D7FFFFEB0030A0E1FF3003E2000053E3 +0AFE10C010FAFFFF0A10309FE5003093E5003093E5 +0AFE10D010FF3003E20300A0E100A81BE9A01DFE0A +0AFE10E0100DC0A0E100D82DE904B04CE204D04DE2 +0AFE10F0100030A0E10D304BE50D305BE52332A0E1 +0AFE1100100E304BE50E305BE5090053E30300009A +0AFE1110100E305BE5373083E20E304BE5020000EA +0AFE1120100E305BE5303083E20E304BE50E305BE5 +0AFE1130100300A0E1C3FFFFEB0D305BE50F3003E2 +0AFE1140100E304BE50E305BE5090053E30300009A +0AFE1150100E305BE5373083E20E304BE5020000EA +0AFE1160100E305BE5303083E20E304BE50E305BE5 +0AFE1170100300A0E1B3FFFFEB00A81BE90DC0A0E1 +0AFE11801000D82DE904B04CE21CD04DE210000BE5 +0AFE11901014100BE518200BE588009FE5E50200EB +0AFE11A01010301BE51C300BE514301BE520300BE5 +0AFE11B0100030A0E324300BE524201BE518301BE5 +0AFE11C010030052E10000003A120000EA1C004BE2 +0AFE11D010002090E520104BE2003091E500C093E5 +0AFE11E010043083E2003081E5003092E5042082E2 +0AFE11F010002080E50C0053E10200000A0030A0E3 +0AFE12001028300BE5050000EA24301BE5043083E2 +0AFE12101024300BE5E7FFFFEA0130A0E328300BE5 +0AFE12201028001BE500A81BE9E81EFE0A0DC0A0E1 +0AFE12301000D82DE904B04CE214D04DE210000BE5 +0AFE12401014100BE56C009FE5BA0200EB10301BE5 +0AFE12501018300BE50030A0E31C300BE51C201BE5 +0AFE12601014301BE5030052E10000003A0D0000EA +0AFE12701018304BE2002093E5001092E5042082E2 +0AFE128010002083E5010071E30200000A0030A0E3 +0AFE12901020300BE5050000EA1C301BE5043083E2 +0AFE12A0101C300BE5ECFFFFEA0130A0E320300BE5 +0AFE12B01020001BE500A81BE9001FFE0A0DC0A0E1 +0AFE12C01000D82DE904B04CE224D04DE20130A0E3 +0AFE12D01024300BE5A4229FE58139A0E3023A83E2 +0AFE12E010003082E59820A0E390329FE5003093E5 +0AFE12F010033082E0003093E5023903E2000053E3 +0AFE1300100300001A74229FE58139A0E3033A83E2 +0AFE131010003082E568029FE5860200EBAF36A0E3 +0AFE1320100E3883E2003093E510300BE554029FE5 +0AFE133010800200EB10301BE5233CA0E1FF3003E2 +0AFE1340100300A0E165FFFFEB10301BE52338A0E1 +0AFE135010FF3003E20300A0E160FFFFEB10301BE5 +0AFE1360102334A0E1FF3003E20300A0E15BFFFFEB +0AFE13701010305BE50300A0E158FFFFEB0A00A0E3 +0AFE13801030FFFFEB0D00A0E32EFFFFEBAF36A0E3 +0AFE1390100E3883E2043083E2003093E514300BE5 +0AFE13A010E4019FE5630200EB14301BE5233CA0E1 +0AFE13B010FF3003E20300A0E148FFFFEB14301BE5 +0AFE13C0102338A0E1FF3003E20300A0E143FFFFEB +0AFE13D01014301BE52334A0E1FF3003E20300A0E1 +0AFE13E0103EFFFFEB14305BE50300A0E13BFFFFEB +0AFE13F0100A00A0E313FFFFEB0D00A0E311FFFFEB +0AFE140010AF36A0E30E3883E2083083E2003093E5 +0AFE14101018300BE574019FE5460200EB18301BE5 +0AFE142010233CA0E1FF3003E20300A0E12BFFFFEB +0AFE14301018301BE52338A0E1FF3003E20300A0E1 +0AFE14401026FFFFEB18301BE52334A0E1FF3003E2 +0AFE1450100300A0E121FFFFEB18305BE50300A0E1 +0AFE1460101EFFFFEB0A00A0E3F6FEFFEB0D00A0E3 +0AFE147010F4FEFFEBE6FEFFEB0030A0E1FF3003E2 +0AFE148010000053E30000001A020000EA03FFFFEB +0AFE1490102D004BE5F6FFFFEAF4009FE5250200EB +0AFE14A010FEFEFFEB2D004BE5CD0000EBC00000EB +0AFE14B010E0009FE51F0200EB18301BE528300BE5 +0AFE14C01014301BE52C300BE52C001BE5100100EB +0AFE14D01028301BE5013643E228300BE52C301BE5 +0AFE14E010013683E22C300BE528301BE5000053E3 +0AFE14F010F4FFFFCAAE0000EB14001BE518101BE5 +0AFE15001049FFFFEB0030A0E1FF3003E2000053E3 +0AFE151010E6FFFF0A80009FE5060200EB10001BE5 +0AFE15201014101BE518201BE5D00000EB10001BE5 +0AFE15301014101BE518201BE50FFFFFEB0030A0E1 +0AFE154010FF3003E2000053E30200000A4C009FE5 +0AFE155010F80100EB010000EA44009FE5F50100EB +0AFE156010930000EB3C009FE5F20100EB0000A0E3 +0AFE157010A4FEFFEB0030A0E30300A0E100A81BE9 +0AFE158010A01DFE0AA41DFE0AE01DFE0A0C1EFE0A +0AFE159010381EFE0A641EFE0A181FFE0A281FFE0A +0AFE15A0103C1FFE0A481FFE0AB41EFE0A0DC0A0E1 +0AFE15B01000D82DE904B04CE204D04DE210000BE5 +0AFE15C01010301BE5013043E210300BE5010073E3 +0AFE15D010FAFFFF1A00A81BE90DC0A0E100D82DE9 +0AFE15E01004B04CE208D04DE210000BE510301BE5 +0AFE15F01014300BE514301BE50300A0E100A81BE9 +0AFE1600100DC0A0E100D82DE904B04CE204D04DE2 +0AFE1610102228A0E3012A82E2042082E2E134A0E3 +0AFE162010023883E2033C83E2003082E50333A0E3 +0AFE163010053983E2003093E510300BE500A81BE9 +0AFE1640100DC0A0E100D82DE904B04CE204D04DE2 +0AFE1650102228A0E3012A82E2042082E29134A0E3 +0AFE166010023883E2033C83E2003082E5C136A0E3 +0AFE167010003093E510300BE52228A0E3012A82E2 +0AFE168010042082E2E134A0E3023883E2033C83E2 +0AFE169010003082E50333A0E3073983E20020A0E3 +0AFE16A010002083E52228A0E3012A82E2042082E2 +0AFE16B0108134A0E3023883E2033C83E2003082E5 +0AFE16C0100333A0E3003093E510300BE5CBFFFFEB +0AFE16D01010301BE50300A0E100A81BE90DC0A0E1 +0AFE16E01000D82DE904B04CE208D04DE2D3FFFFEB +0AFE16F0100030A0E110300BE510301BE5023503E2 +0AFE170010000053E30500000A10301BE5073703E2 +0AFE171010000053E30100000A10001BE5ADFFFFEB +0AFE17201010301BE5803003E2000053E30500000A +0AFE17301010301BE51C3003E2000053E30100000A +0AFE17401010001BE5A3FFFFEB10201BE50235A0E3 +0AFE175010803083E2030052E10200001A0130A0E3 +0AFE17601014300BE5010000EA0030A0E314300BE5 +0AFE17701014001BE500A81BE90DC0A0E100D82DE9 +0AFE17801004B04CE204D04DE22228A0E3012A82E2 +0AFE179010042082E29134A0E3023883E2033C83E2 +0AFE17A010003082E5C136A0E3003093E510300BE5 +0AFE17B01000A81BE90DC0A0E100D82DE904B04CE2 +0AFE17C010ECFFFFEB2228A0E3012A82E2042082E2 +0AFE17D0108134A0E3023883E2033C83E2003082E5 +0AFE17E01000A81BE90DC0A0E100D82DE904B04CE2 +0AFE17F01004D04DE22228A0E3012A82E2042082E2 +0AFE1800102238A0E3013A83E2043083E2003093E5 +0AFE181010023183E3003082E52228A0E3012A82E2 +0AFE1820102238A0E3013A83E2003093E5023183E3 +0AFE183010003082E5FA0FA0E35BFFFFEB2228A0E3 +0AFE184010012A82E2042082E2B134A0E3023883E2 +0AFE185010033C83E2003082E50333A0E3233983E2 +0AFE186010033B83E2003093E510300BE500A81BE9 +0AFE1870100DC0A0E100D82DE904B04CE21CD04DE2 +0AFE18801010000BE514100BE518200BE50030A0E3 +0AFE1890101C300BE51C201BE518301BE5030052E1 +0AFE18A0100000003A190000EAB2FFFFEB2228A0E3 +0AFE18B010012A82E2042082E2F134A0E3023883E2 +0AFE18C010033C83E2003082E514201BE51C301BE5 +0AFE18D010031082E010201BE51C301BE5033082E0 +0AFE18E010003093E5003081E57BFFFFEB0030A0E1 +0AFE18F010FF3003E2000053E3FAFFFF0AACFFFFEB +0AFE1900101C301BE5043083E21C300BE5E0FFFFEA +0AFE19101000A81BE90DC0A0E100D82DE904B04CE2 +0AFE1920100CD04DE210000BE52228A0E3012A82E2 +0AFE193010042082E28134A0E3023883E2033C83E2 +0AFE194010003082E510301BE5003093E514300BE5 +0AFE1950102228A0E3012A82E2042082E29134A0E3 +0AFE196010023883E2033C83E2003082E510301BE5 +0AFE197010003093E518300BE52228A0E3012A82E2 +0AFE198010042082E2E134A0E3023883E2033C83E2 +0AFE199010003082E50229A0E310301BE5032082E0 +0AFE19A0100030A0E3003082E52228A0E3012A82E2 +0AFE19B010042082E28134A0E3023883E2033C83E2 +0AFE19C010003082E510201BE50D3AA0E3D03083E2 +0AFE19D010033883E1003082E53FFFFFEB0030A0E1 +0AFE19E010FF3003E2000053E3FAFFFF0A70FFFFEB +0AFE19F01000A81BE90DC0A0E100D82DE904B04CE2 +0AFE1A00105CFFFFEB2228A0E3012A82E2042082E2 +0AFE1A1010E134A0E3023883E2033C83E2003082E5 +0AFE1A20100333A0E3033983E20020A0E3002083E5 +0AFE1A30102228A0E3012A82E2042082E28134A0E3 +0AFE1A4010023883E2033C83E2003082E50323A0E3 +0AFE1A5010032982E20339A0E3C03083E2033883E1 +0AFE1A6010003082E500A81BE90DC0A0E100D82DE9 +0AFE1A701004B04CE23FFFFFEB2228A0E3012A82E2 +0AFE1A8010042082E2E134A0E3023883E2033C83E2 +0AFE1A9010003082E50333A0E30A3983E20020A0E3 +0AFE1AA010002083E52228A0E3012A82E2042082E2 +0AFE1AB0108134A0E3023883E2033C83E2003082E5 +0AFE1AC0100323A0E30A2982E20339A0E3C03083E2 +0AFE1AD010033883E1003082E500A81BE90DC0A0E1 +0AFE1AE01000D82DE904B04CE28729A0E3222E82E2 +0AFE1AF0108739A0E3223E83E2003093E51E3CC3E3 +0AFE1B0010003082E58729A0E38E2F82E28739A0E3 +0AFE1B10108E3F83E2003093E51E3CC3E3003082E5 +0AFE1B20108139A0E3823D83E20520A0E3002083E5 +0AFE1B30108129A0E3822D82E2042082E20139A0E3 +0AFE1B4010273083E2003082E58139A0E3823D83E2 +0AFE1B50100C3083E20120A0E3002083E58129A0E3 +0AFE1B6010822D82E2102082E22A3DA0E3013083E2 +0AFE1B7010003082E58139A0E3823D83E2243083E2 +0AFE1B80100F20A0E3002083E58139A0E3823D83E2 +0AFE1B9010283083E28A20A0E3002083E58139A0E3 +0AFE1BA010823D83E22C3083E20820A0E3002083E5 +0AFE1BB01000A81BE90DC0A0E100D82DE904B04CE2 +0AFE1BC0108139A0E3823D83E2183083E2003093E5 +0AFE1BD010013003E2FF3003E20300A0E100A81BE9 +0AFE1BE0100DC0A0E100D82DE904B04CE204D04DE2 +0AFE1BF0100030A0E10D304BE58139A0E3823D83E2 +0AFE1C0010183083E2003093E5013903E2000053E3 +0AFE1C1010F8FFFF0A8139A0E3813D83E20D205BE5 +0AFE1C2010002083E50D305BE50A0053E30A00001A +0AFE1C30108139A0E3823D83E2183083E2003093E5 +0AFE1C4010013903E2000053E3F8FFFF0A8139A0E3 +0AFE1C5010813D83E20D20A0E3002083E500A81BE9 +0AFE1C60100DC0A0E100D82DE904B04CE20000A0E1 +0AFE1C7010CFFFFFEB0030A0E1FF3003E2000053E3 +0AFE1C8010FAFFFF0A8139A0E3023A83E2003093E5 +0AFE1C9010FF3003E20300A0E100A81BE90DC0A0E1 +0AFE1CA01000D82DE904B04CE204D04DE20030A0E1 +0AFE1CB0100D304BE50D305BE52332A0E10E304BE5 +0AFE1CC0100E305BE5090053E30300009A0E305BE5 +0AFE1CD010373083E20E304BE5020000EA0E305BE5 +0AFE1CE010303083E20E304BE50E305BE50300A0E1 +0AFE1CF010BAFFFFEB0D305BE50F3003E20E304BE5 +0AFE1D00100E305BE5090053E30300009A0E305BE5 +0AFE1D1010373083E20E304BE5020000EA0E305BE5 +0AFE1D2010303083E20E304BE50E305BE50300A0E1 +0AFE1D3010AAFFFFEB00A81BE90DC0A0E100D82DE9 +0AFE1D401004B04CE204D04DE210000BE510301BE5 +0AFE1D50100030D3E5000053E30000001A080000EA +0AFE1D601010104BE2003091E50320A0E10020D2E5 +0AFE1D7010013083E2003081E50200A0E197FFFFEB +0AFE1D8008F1FFFFEA00A81BE9 +0AFE1DA4100A0D4D58314144532053796E632D666C +0AFE1DB4106173682050726F6772616D6D696E6720 +0AFE1DC4105574696C6974792076302E3520323030 +0AFE1DD410322F30382F32310A0D000000536F7572 +0AFE1DE41063652061646472657373202873746F72 +0AFE1DF410656420696E2030783041464530303030 +0AFE1E0410293A2030780000005461726765742061 +0AFE1E1410646472657373202873746F7265642069 +0AFE1E24106E2030783041464530303034293A2030 +0AFE1E34107800000053697A652020202020202020 +0AFE1E44102020202873746F72656420696E203078 +0AFE1E54103041464530303038293A203078000000 +0AFE1E6410507265737320616E79206B657920746F +0AFE1E74102073746172742070726F6772616D6D69 +0AFE1E84106E67202E2E2E00000A0D45726173696E +0AFE1E94106720666C617368202E2E2E000A0D5072 +0AFE1EA4106F6772616D6D696E67202E2E2E000000 +0AFE1EB4100A0D50726F6772616D6D696E67206669 +0AFE1EC4106E69736865642E0A0D50726573732027 +0AFE1ED410612720746F20636F6E74696E7565202E +0AFE1EE4102E2E2E000A0D566572696679696E6720 +0AFE1EF410666C617368202E2E2E0000000A0D426C +0AFE1F0410616E6B20636865636B696E67202E2E2E +0AFE1F1410000000000A45726173696E67202E2E2E +0AFE1F2410000000000A50726F6772616D6D696E67 +0AFE1F3410202E2E2E000000002073756363656564 +0AFE1F44102E0A0000206661696C656420210A0000 +0AFE100000 + " +} + +######################################################### + +if [ "$#" -eq 2 ] ; then + output_init > $2 + output_uboot >> $2 + output_flashprog >> $2 +else + output_init; + output_uboot; + output_flashprog; +fi diff --git a/tools/img2srec.c b/tools/img2srec.c new file mode 100644 index 0000000..b04abbd --- /dev/null +++ b/tools/img2srec.c @@ -0,0 +1,413 @@ +/************************************************************************* +| COPYRIGHT (c) 2000 BY ABATRON AG +|************************************************************************* +| +| PROJECT NAME: Linux Image to S-record Conversion Utility +| FILENAME : img2srec.c +| +| COMPILER : GCC +| +| TARGET OS : LINUX / UNIX +| TARGET HW : - +| +| PROGRAMMER : Abatron / RD +| CREATION : 07.07.00 +| +|************************************************************************* +| +| DESCRIPTION : +| +| Utility to convert a Linux Boot Image to S-record: +| ================================================== +| +| This command line utility can be used to convert a Linux boot image +| (zimage.initrd) to S-Record format used for flash programming. +| This conversion takes care of the special sections "IMAGE" and INITRD". +| +| img2srec [-o offset] image > image.srec +| +| +| Build the utility: +| ================== +| +| To build the utility use GCC as follows: +| +| gcc img2srec.c -o img2srec +| +| +|************************************************************************* +| +| +| UPDATES : +| +| DATE NAME CHANGES +| ----------------------------------------------------------- +| Latest update +| +| 07.07.00 aba Initial release +| +|*************************************************************************/ + +/************************************************************************* +| INCLUDES +|*************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +extern int errno; + +/************************************************************************* +| DEFINES +|*************************************************************************/ + +#define FALSE 0 +#define TRUE 1 + +/************************************************************************* +| MACROS +|*************************************************************************/ + +/************************************************************************* +| TYPEDEFS +|*************************************************************************/ + +typedef uint8_t CHAR; +typedef uint8_t BYTE; +typedef uint16_t WORD; +typedef uint32_t DWORD; +typedef int BOOL; + +/************************************************************************* +| LOCALS +|*************************************************************************/ + +/************************************************************************* +| PROTOTYPES +|*************************************************************************/ + +static char *ExtractHex(DWORD *value, char *getPtr); +static char *ExtractDecimal(DWORD *value, char *getPtr); +static void ExtractNumber(DWORD *value, char *getPtr); +static BYTE *ExtractWord(WORD *value, BYTE *buffer); +static BYTE *ExtractLong(DWORD *value, BYTE *buffer); +static BYTE *ExtractBlock(WORD count, BYTE *data, BYTE *buffer); +static char *WriteHex(char *pa, BYTE value, WORD *pCheckSum); +static char *BuildSRecord(char *pa, WORD sType, DWORD addr, + const BYTE *data, int nCount); +static void ConvertELF(char *fileName, DWORD loadOffset); +int main(int argc, char *argv[]); + +/************************************************************************* +| FUNCTIONS +|*************************************************************************/ + +static char* ExtractHex (DWORD* value, char* getPtr) +{ + DWORD num; + DWORD digit; + BYTE c; + + while (*getPtr == ' ') getPtr++; + num = 0; + for (;;) { + c = *getPtr; + if ((c >= '0') && (c <= '9')) digit = (DWORD)(c - '0'); + else if ((c >= 'A') && (c <= 'F')) digit = (DWORD)(c - 'A' + 10); + else if ((c >= 'a') && (c <= 'f')) digit = (DWORD)(c - 'a' + 10); + else break; + num <<= 4; + num += digit; + getPtr++; + } /* for */ + *value = num; + return getPtr; +} /* ExtractHex */ + +static char* ExtractDecimal (DWORD* value, char* getPtr) +{ + DWORD num; + DWORD digit; + BYTE c; + + while (*getPtr == ' ') getPtr++; + num = 0; + for (;;) { + c = *getPtr; + if ((c >= '0') && (c <= '9')) digit = (DWORD)(c - '0'); + else break; + num *= 10; + num += digit; + getPtr++; + } /* for */ + *value = num; + return getPtr; +} /* ExtractDecimal */ + + +static void ExtractNumber (DWORD* value, char* getPtr) +{ + BOOL neg = FALSE;; + + while (*getPtr == ' ') getPtr++; + if (*getPtr == '-') { + neg = TRUE; + getPtr++; + } /* if */ + if ((*getPtr == '0') && ((*(getPtr+1) == 'x') || (*(getPtr+1) == 'X'))) { + getPtr +=2; + (void)ExtractHex(value, getPtr); + } /* if */ + else { + (void)ExtractDecimal(value, getPtr); + } /* else */ + if (neg) *value = -(*value); +} /* ExtractNumber */ + + +static BYTE* ExtractWord(WORD* value, BYTE* buffer) +{ + WORD x; + x = (WORD)*buffer++; + x = (x<<8) + (WORD)*buffer++; + *value = x; + return buffer; +} /* ExtractWord */ + + +static BYTE* ExtractLong(DWORD* value, BYTE* buffer) +{ + DWORD x; + x = (DWORD)*buffer++; + x = (x<<8) + (DWORD)*buffer++; + x = (x<<8) + (DWORD)*buffer++; + x = (x<<8) + (DWORD)*buffer++; + *value = x; + return buffer; +} /* ExtractLong */ + + +static BYTE* ExtractBlock(WORD count, BYTE* data, BYTE* buffer) +{ + while (count--) *data++ = *buffer++; + return buffer; +} /* ExtractBlock */ + + +static char* WriteHex(char* pa, BYTE value, WORD* pCheckSum) +{ + WORD temp; + + static char ByteToHex[] = "0123456789ABCDEF"; + + *pCheckSum += value; + temp = value / 16; + *pa++ = ByteToHex[temp]; + temp = value % 16; + *pa++ = ByteToHex[temp]; + return pa; +} + + +static char* BuildSRecord(char* pa, WORD sType, DWORD addr, + const BYTE* data, int nCount) +{ + WORD addrLen; + WORD sRLen; + WORD checkSum; + WORD i; + + switch (sType) { + case 0: + case 1: + case 9: + addrLen = 2; + break; + case 2: + case 8: + addrLen = 3; + break; + case 3: + case 7: + addrLen = 4; + break; + default: + return pa; + } /* switch */ + + *pa++ = 'S'; + *pa++ = (char)(sType + '0'); + sRLen = addrLen + nCount + 1; + checkSum = 0; + pa = WriteHex(pa, (BYTE)sRLen, &checkSum); + + /* Write address field */ + for (i = 1; i <= addrLen; i++) { + pa = WriteHex(pa, (BYTE)(addr >> (8 * (addrLen - i))), &checkSum); + } /* for */ + + /* Write code/data fields */ + for (i = 0; i < nCount; i++) { + pa = WriteHex(pa, *data++, &checkSum); + } /* for */ + + /* Write checksum field */ + checkSum = ~checkSum; + pa = WriteHex(pa, (BYTE)checkSum, &checkSum); + *pa++ = '\0'; + return pa; +} + + +static void ConvertELF(char* fileName, DWORD loadOffset) +{ + FILE* file; + int i; + int rxCount; + BYTE rxBlock[1024]; + DWORD loadSize; + DWORD firstAddr; + DWORD loadAddr; + DWORD loadDiff = 0; + Elf32_Ehdr elfHeader; + Elf32_Shdr sectHeader[32]; + BYTE* getPtr; + char srecLine[128]; + char *hdr_name; + + + /* open file */ + if ((file = fopen(fileName,"rb")) == NULL) { + fprintf (stderr, "Can't open %s: %s\n", fileName, strerror(errno)); + return; + } /* if */ + + /* read ELF header */ + rxCount = fread(rxBlock, 1, sizeof elfHeader, file); + getPtr = ExtractBlock(sizeof elfHeader.e_ident, elfHeader.e_ident, rxBlock); + getPtr = ExtractWord(&elfHeader.e_type, getPtr); + getPtr = ExtractWord(&elfHeader.e_machine, getPtr); + getPtr = ExtractLong((DWORD *)&elfHeader.e_version, getPtr); + getPtr = ExtractLong((DWORD *)&elfHeader.e_entry, getPtr); + getPtr = ExtractLong((DWORD *)&elfHeader.e_phoff, getPtr); + getPtr = ExtractLong((DWORD *)&elfHeader.e_shoff, getPtr); + getPtr = ExtractLong((DWORD *)&elfHeader.e_flags, getPtr); + getPtr = ExtractWord(&elfHeader.e_ehsize, getPtr); + getPtr = ExtractWord(&elfHeader.e_phentsize, getPtr); + getPtr = ExtractWord(&elfHeader.e_phnum, getPtr); + getPtr = ExtractWord(&elfHeader.e_shentsize, getPtr); + getPtr = ExtractWord(&elfHeader.e_shnum, getPtr); + getPtr = ExtractWord(&elfHeader.e_shstrndx, getPtr); + if ( (rxCount != sizeof elfHeader) + || (elfHeader.e_ident[0] != ELFMAG0) + || (elfHeader.e_ident[1] != ELFMAG1) + || (elfHeader.e_ident[2] != ELFMAG2) + || (elfHeader.e_ident[3] != ELFMAG3) + || (elfHeader.e_type != ET_EXEC) + ) { + fclose(file); + fprintf (stderr, "*** illegal file format\n"); + return; + } /* if */ + + /* read all section headers */ + fseek(file, elfHeader.e_shoff, SEEK_SET); + for (i = 0; i < elfHeader.e_shnum; i++) { + rxCount = fread(rxBlock, 1, sizeof sectHeader[0], file); + getPtr = ExtractLong((DWORD *)§Header[i].sh_name, rxBlock); + getPtr = ExtractLong((DWORD *)§Header[i].sh_type, getPtr); + getPtr = ExtractLong((DWORD *)§Header[i].sh_flags, getPtr); + getPtr = ExtractLong((DWORD *)§Header[i].sh_addr, getPtr); + getPtr = ExtractLong((DWORD *)§Header[i].sh_offset, getPtr); + getPtr = ExtractLong((DWORD *)§Header[i].sh_size, getPtr); + getPtr = ExtractLong((DWORD *)§Header[i].sh_link, getPtr); + getPtr = ExtractLong((DWORD *)§Header[i].sh_info, getPtr); + getPtr = ExtractLong((DWORD *)§Header[i].sh_addralign, getPtr); + getPtr = ExtractLong((DWORD *)§Header[i].sh_entsize, getPtr); + if (rxCount != sizeof sectHeader[0]) { + fclose(file); + fprintf (stderr, "*** illegal file format\n"); + return; + } /* if */ + } /* for */ + + if ((hdr_name = strrchr(fileName, '/')) == NULL) { + hdr_name = fileName; + } else { + ++hdr_name; + } + /* write start record */ + (void)BuildSRecord(srecLine, 0, 0, (BYTE *)hdr_name, strlen(hdr_name)); + printf("%s\r\n",srecLine); + + /* write data records */ + firstAddr = ~0; + loadAddr = 0; + for (i = 0; i < elfHeader.e_shnum; i++) { + if ( (sectHeader[i].sh_type == SHT_PROGBITS) + && (sectHeader[i].sh_size != 0) + ) { + loadSize = sectHeader[i].sh_size; + if (sectHeader[i].sh_flags != 0) { + loadAddr = sectHeader[i].sh_addr; + loadDiff = loadAddr - sectHeader[i].sh_offset; + } /* if */ + else { + loadAddr = sectHeader[i].sh_offset + loadDiff; + } /* else */ + + if (loadAddr < firstAddr) + firstAddr = loadAddr; + + /* build s-records */ + loadSize = sectHeader[i].sh_size; + fseek(file, sectHeader[i].sh_offset, SEEK_SET); + while (loadSize) { + rxCount = fread(rxBlock, 1, (loadSize > 32) ? 32 : loadSize, file); + if (rxCount < 0) { + fclose(file); + fprintf (stderr, "*** illegal file format\n"); + return; + } /* if */ + (void)BuildSRecord(srecLine, 3, loadAddr + loadOffset, rxBlock, rxCount); + loadSize -= rxCount; + loadAddr += rxCount; + printf("%s\r\n",srecLine); + } /* while */ + } /* if */ + } /* for */ + + /* add end record */ + (void)BuildSRecord(srecLine, 7, firstAddr + loadOffset, 0, 0); + printf("%s\r\n",srecLine); + fclose(file); +} /* ConvertELF */ + + +/************************************************************************* +| MAIN +|*************************************************************************/ + +int main( int argc, char *argv[ ]) +{ + DWORD offset; + + if (argc == 2) { + ConvertELF(argv[1], 0); + } /* if */ + else if ((argc == 4) && (strcmp(argv[1], "-o") == 0)) { + ExtractNumber(&offset, argv[2]); + ConvertELF(argv[3], offset); + } /* if */ + else { + fprintf (stderr, "Usage: img2srec [-o offset] \n"); + } /* if */ + + return 0; +} /* main */ diff --git a/tools/inca-swap-bytes.c b/tools/inca-swap-bytes.c new file mode 100644 index 0000000..3a6d82d --- /dev/null +++ b/tools/inca-swap-bytes.c @@ -0,0 +1,38 @@ +#include +#include +#include +#include + +#ifndef BUFSIZ +# define BUFSIZ 4096 +#endif + +#undef BUFSIZ +# define BUFSIZ 64 +int main (void) +{ + short ibuff[BUFSIZ], obuff[BUFSIZ]; + int rc, i, len; + + while ((rc = read (0, ibuff, sizeof (ibuff))) > 0) { + memset (obuff, 0, sizeof (obuff)); + for (i = 0; i < (rc + 1) / 2; i++) { + obuff[i] = ibuff[i ^ 1]; + } + + len = (rc + 1) & ~1; + + if (write (1, obuff, len) != len) { + perror ("read error"); + return (EXIT_FAILURE); + } + + memset (ibuff, 0, sizeof (ibuff)); + } + + if (rc < 0) { + perror ("read error"); + return (EXIT_FAILURE); + } + return (EXIT_SUCCESS); +} diff --git a/tools/logos/denx.bmp b/tools/logos/denx.bmp new file mode 100644 index 0000000..c4cde09 Binary files /dev/null and b/tools/logos/denx.bmp differ diff --git a/tools/mkimage.c b/tools/mkimage.c new file mode 100644 index 0000000..fbc1a12 --- /dev/null +++ b/tools/mkimage.c @@ -0,0 +1,745 @@ +/* + * (C) Copyright 2000-2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#ifndef __WIN32__ +#include /* for host / network byte order conversions */ +#endif +#include +#include +#include +#include + +#if defined(__BEOS__) || defined(__NetBSD__) || defined(__APPLE__) +#include +#endif + +#ifdef __WIN32__ +typedef unsigned int __u32; + +#define SWAP_LONG(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; + +#define ntohl(a) SWAP_LONG(a) +#define htonl(a) SWAP_LONG(a) +#endif /* __WIN32__ */ + +#ifndef O_BINARY /* should be define'd on __WIN32__ */ +#define O_BINARY 0 +#endif + +#include + +extern int errno; + +#ifndef MAP_FAILED +#define MAP_FAILED (-1) +#endif + +char *cmdname; + +extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len); + +typedef struct table_entry { + int val; /* as defined in image.h */ + char *sname; /* short (input) name */ + char *lname; /* long (output) name */ +} table_entry_t; + +table_entry_t arch_name[] = { + { IH_CPU_INVALID, NULL, "Invalid CPU", }, + { IH_CPU_ALPHA, "alpha", "Alpha", }, + { IH_CPU_ARM, "arm", "ARM", }, + { IH_CPU_I386, "x86", "Intel x86", }, + { IH_CPU_IA64, "ia64", "IA64", }, + { IH_CPU_M68K, "m68k", "MC68000", }, + { IH_CPU_MICROBLAZE, "microblaze", "MicroBlaze", }, + { IH_CPU_MIPS, "mips", "MIPS", }, + { IH_CPU_MIPS64, "mips64", "MIPS 64 Bit", }, + { IH_CPU_NIOS, "nios", "NIOS", }, + { IH_CPU_NIOS2, "nios2", "NIOS II", }, + { IH_CPU_PPC, "ppc", "PowerPC", }, + { IH_CPU_S390, "s390", "IBM S390", }, + { IH_CPU_SH, "sh", "SuperH", }, + { IH_CPU_SPARC, "sparc", "SPARC", }, + { IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", }, + { -1, "", "", }, +}; + +table_entry_t os_name[] = { + { IH_OS_INVALID, NULL, "Invalid OS", }, + { IH_OS_4_4BSD, "4_4bsd", "4_4BSD", }, + { IH_OS_ARTOS, "artos", "ARTOS", }, + { IH_OS_DELL, "dell", "Dell", }, + { IH_OS_ESIX, "esix", "Esix", }, + { IH_OS_FREEBSD, "freebsd", "FreeBSD", }, + { IH_OS_IRIX, "irix", "Irix", }, + { IH_OS_LINUX, "linux", "Linux", }, + { IH_OS_LYNXOS, "lynxos", "LynxOS", }, + { IH_OS_NCR, "ncr", "NCR", }, + { IH_OS_NETBSD, "netbsd", "NetBSD", }, + { IH_OS_OPENBSD, "openbsd", "OpenBSD", }, + { IH_OS_PSOS, "psos", "pSOS", }, + { IH_OS_QNX, "qnx", "QNX", }, + { IH_OS_RTEMS, "rtems", "RTEMS", }, + { IH_OS_SCO, "sco", "SCO", }, + { IH_OS_SOLARIS, "solaris", "Solaris", }, + { IH_OS_SVR4, "svr4", "SVR4", }, + { IH_OS_U_BOOT, "u-boot", "U-Boot", }, + { IH_OS_VXWORKS, "vxworks", "VxWorks", }, + { -1, "", "", }, +}; + +table_entry_t type_name[] = { + { IH_TYPE_INVALID, NULL, "Invalid Image", }, + { IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image", }, + { IH_TYPE_FIRMWARE, "firmware", "Firmware", }, + { IH_TYPE_KERNEL, "kernel", "Kernel Image", }, + { IH_TYPE_MULTI, "multi", "Multi-File Image", }, + { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, + { IH_TYPE_SCRIPT, "script", "Script", }, + { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, + { -1, "", "", }, +}; + +table_entry_t comp_name[] = { + { IH_COMP_NONE, "none", "uncompressed", }, + { IH_COMP_BZIP2, "bzip2", "bzip2 compressed", }, + { IH_COMP_GZIP, "gzip", "gzip compressed", }, + { -1, "", "", }, +}; + +static void copy_file (int, const char *, int); +static void usage (void); +static void print_header (image_header_t *); +static void print_type (image_header_t *); +static char *put_table_entry (table_entry_t *, char *, int); +static char *put_arch (int); +static char *put_type (int); +static char *put_os (int); +static char *put_comp (int); +static int get_table_entry (table_entry_t *, char *, char *); +static int get_arch(char *); +static int get_comp(char *); +static int get_os (char *); +static int get_type(char *); + + +char *datafile; +char *imagefile; + +int dflag = 0; +int eflag = 0; +int lflag = 0; +int vflag = 0; +int xflag = 0; +int opt_os = IH_OS_LINUX; +int opt_arch = IH_CPU_PPC; +int opt_type = IH_TYPE_KERNEL; +int opt_comp = IH_COMP_GZIP; + +image_header_t header; +image_header_t *hdr = &header; + +int +main (int argc, char **argv) +{ + int ifd; + uint32_t checksum; + uint32_t addr; + uint32_t ep; + struct stat sbuf; + unsigned char *ptr; + char *name = ""; + + cmdname = *argv; + + addr = ep = 0; + + while (--argc > 0 && **++argv == '-') { + while (*++*argv) { + switch (**argv) { + case 'l': + lflag = 1; + break; + case 'A': + if ((--argc <= 0) || + (opt_arch = get_arch(*++argv)) < 0) + usage (); + goto NXTARG; + case 'C': + if ((--argc <= 0) || + (opt_comp = get_comp(*++argv)) < 0) + usage (); + goto NXTARG; + case 'O': + if ((--argc <= 0) || + (opt_os = get_os(*++argv)) < 0) + usage (); + goto NXTARG; + case 'T': + if ((--argc <= 0) || + (opt_type = get_type(*++argv)) < 0) + usage (); + goto NXTARG; + + case 'a': + if (--argc <= 0) + usage (); + addr = strtoul (*++argv, (char **)&ptr, 16); + if (*ptr) { + fprintf (stderr, + "%s: invalid load address %s\n", + cmdname, *argv); + exit (EXIT_FAILURE); + } + goto NXTARG; + case 'd': + if (--argc <= 0) + usage (); + datafile = *++argv; + dflag = 1; + goto NXTARG; + case 'e': + if (--argc <= 0) + usage (); + ep = strtoul (*++argv, (char **)&ptr, 16); + if (*ptr) { + fprintf (stderr, + "%s: invalid entry point %s\n", + cmdname, *argv); + exit (EXIT_FAILURE); + } + eflag = 1; + goto NXTARG; + case 'n': + if (--argc <= 0) + usage (); + name = *++argv; + goto NXTARG; + case 'v': + vflag++; + break; + case 'x': + xflag++; + break; + default: + usage (); + } + } +NXTARG: ; + } + + if ((argc != 1) || ((lflag ^ dflag) == 0)) + usage(); + + if (!eflag) { + ep = addr; + /* If XIP, entry point must be after the U-Boot header */ + if (xflag) + ep += sizeof(image_header_t); + } + + /* + * If XIP, ensure the entry point is equal to the load address plus + * the size of the U-Boot header. + */ + if (xflag) { + if (ep != addr + sizeof(image_header_t)) { + fprintf (stderr, "%s: For XIP, the entry point must be the load addr + %lu\n", + cmdname, + (unsigned long)sizeof(image_header_t)); + exit (EXIT_FAILURE); + } + } + + imagefile = *argv; + + if (lflag) { + ifd = open(imagefile, O_RDONLY|O_BINARY); + } else { + ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666); + } + + if (ifd < 0) { + fprintf (stderr, "%s: Can't open %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (lflag) { + int len; + char *data; + /* + * list header information of existing image + */ + if (fstat(ifd, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if ((unsigned)sbuf.st_size < sizeof(image_header_t)) { + fprintf (stderr, + "%s: Bad size: \"%s\" is no valid image\n", + cmdname, imagefile); + exit (EXIT_FAILURE); + } + + ptr = (unsigned char *)mmap(0, sbuf.st_size, + PROT_READ, MAP_SHARED, ifd, 0); + if ((caddr_t)ptr == (caddr_t)-1) { + fprintf (stderr, "%s: Can't read %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + /* + * create copy of header so that we can blank out the + * checksum field for checking - this can't be done + * on the PROT_READ mapped data. + */ + memcpy (hdr, ptr, sizeof(image_header_t)); + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + fprintf (stderr, + "%s: Bad Magic Number: \"%s\" is no valid image\n", + cmdname, imagefile); + exit (EXIT_FAILURE); + } + + data = (char *)hdr; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = htonl(0); /* clear for re-calculation */ + + if (crc32 (0, data, len) != checksum) { + fprintf (stderr, + "*** Warning: \"%s\" has bad header checksum!\n", + imagefile); + } + + data = (char *)(ptr + sizeof(image_header_t)); + len = sbuf.st_size - sizeof(image_header_t) ; + + if (crc32 (0, data, len) != ntohl(hdr->ih_dcrc)) { + fprintf (stderr, + "*** Warning: \"%s\" has corrupted data!\n", + imagefile); + } + + /* for multi-file images we need the data part, too */ + print_header ((image_header_t *)ptr); + + (void) munmap((void *)ptr, sbuf.st_size); + (void) close (ifd); + + exit (EXIT_SUCCESS); + } + + /* + * Must be -w then: + * + * write dummy header, to be fixed later + */ + memset (hdr, 0, sizeof(image_header_t)); + + if (write(ifd, hdr, sizeof(image_header_t)) != sizeof(image_header_t)) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (opt_type == IH_TYPE_MULTI || opt_type == IH_TYPE_SCRIPT) { + char *file = datafile; + unsigned long size; + + for (;;) { + char *sep = NULL; + + if (file) { + if ((sep = strchr(file, ':')) != NULL) { + *sep = '\0'; + } + + if (stat (file, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + cmdname, file, strerror(errno)); + exit (EXIT_FAILURE); + } + size = htonl(sbuf.st_size); + } else { + size = 0; + } + + if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (!file) { + break; + } + + if (sep) { + *sep = ':'; + file = sep + 1; + } else { + file = NULL; + } + } + + file = datafile; + + for (;;) { + char *sep = strchr(file, ':'); + if (sep) { + *sep = '\0'; + copy_file (ifd, file, 1); + *sep++ = ':'; + file = sep; + } else { + copy_file (ifd, file, 0); + break; + } + } + } else { + copy_file (ifd, datafile, 0); + } + + /* We're a bit of paranoid */ +#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) + (void) fdatasync (ifd); +#else + (void) fsync (ifd); +#endif + + if (fstat(ifd, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + ptr = (unsigned char *)mmap(0, sbuf.st_size, + PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0); + if (ptr == (unsigned char *)MAP_FAILED) { + fprintf (stderr, "%s: Can't map %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + hdr = (image_header_t *)ptr; + + checksum = crc32 (0, + (const char *)(ptr + sizeof(image_header_t)), + sbuf.st_size - sizeof(image_header_t) + ); + + /* Build new header */ + hdr->ih_magic = htonl(IH_MAGIC); + hdr->ih_time = htonl(sbuf.st_mtime); + hdr->ih_size = htonl(sbuf.st_size - sizeof(image_header_t)); + hdr->ih_load = htonl(addr); + hdr->ih_ep = htonl(ep); + hdr->ih_dcrc = htonl(checksum); + hdr->ih_os = opt_os; + hdr->ih_arch = opt_arch; + hdr->ih_type = opt_type; + hdr->ih_comp = opt_comp; + + strncpy((char *)hdr->ih_name, name, IH_NMLEN); + + checksum = crc32(0,(const char *)hdr,sizeof(image_header_t)); + + hdr->ih_hcrc = htonl(checksum); + + print_header (hdr); + + (void) munmap((void *)ptr, sbuf.st_size); + + /* We're a bit of paranoid */ +#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) + (void) fdatasync (ifd); +#else + (void) fsync (ifd); +#endif + + if (close(ifd)) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + exit (EXIT_SUCCESS); +} + +static void +copy_file (int ifd, const char *datafile, int pad) +{ + int dfd; + struct stat sbuf; + unsigned char *ptr; + int tail; + int zero = 0; + int offset = 0; + int size; + + if (vflag) { + fprintf (stderr, "Adding Image %s\n", datafile); + } + + if ((dfd = open(datafile, O_RDONLY|O_BINARY)) < 0) { + fprintf (stderr, "%s: Can't open %s: %s\n", + cmdname, datafile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (fstat(dfd, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + cmdname, datafile, strerror(errno)); + exit (EXIT_FAILURE); + } + + ptr = (unsigned char *)mmap(0, sbuf.st_size, + PROT_READ, MAP_SHARED, dfd, 0); + if (ptr == (unsigned char *)MAP_FAILED) { + fprintf (stderr, "%s: Can't read %s: %s\n", + cmdname, datafile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (xflag) { + unsigned char *p = NULL; + /* + * XIP: do not append the image_header_t at the + * beginning of the file, but consume the space + * reserved for it. + */ + + if ((unsigned)sbuf.st_size < sizeof(image_header_t)) { + fprintf (stderr, + "%s: Bad size: \"%s\" is too small for XIP\n", + cmdname, datafile); + exit (EXIT_FAILURE); + } + + for (p=ptr; p < ptr+sizeof(image_header_t); p++) { + if ( *p != 0xff ) { + fprintf (stderr, + "%s: Bad file: \"%s\" has invalid buffer for XIP\n", + cmdname, datafile); + exit (EXIT_FAILURE); + } + } + + offset = sizeof(image_header_t); + } + + size = sbuf.st_size - offset; + if (write(ifd, ptr + offset, size) != size) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (pad && ((tail = size % 4) != 0)) { + + if (write(ifd, (char *)&zero, 4-tail) != 4-tail) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + } + + (void) munmap((void *)ptr, sbuf.st_size); + (void) close (dfd); +} + +void +usage () +{ + fprintf (stderr, "Usage: %s -l image\n" + " -l ==> list image header information\n" + " %s [-x] -A arch -O os -T type -C comp " + "-a addr -e ep -n name -d data_file[:data_file...] image\n", + cmdname, cmdname); + fprintf (stderr, " -A ==> set architecture to 'arch'\n" + " -O ==> set operating system to 'os'\n" + " -T ==> set image type to 'type'\n" + " -C ==> set compression type 'comp'\n" + " -a ==> set load address to 'addr' (hex)\n" + " -e ==> set entry point to 'ep' (hex)\n" + " -n ==> set image name to 'name'\n" + " -d ==> use image data from 'datafile'\n" + " -x ==> set XIP (execute in place)\n" + ); + exit (EXIT_FAILURE); +} + +static void +print_header (image_header_t *hdr) +{ + time_t timestamp; + uint32_t size; + + timestamp = (time_t)ntohl(hdr->ih_time); + size = ntohl(hdr->ih_size); + + printf ("Image Name: %.*s\n", IH_NMLEN, hdr->ih_name); + printf ("Created: %s", ctime(×tamp)); + printf ("Image Type: "); print_type(hdr); + printf ("Data Size: %d Bytes = %.2f kB = %.2f MB\n", + size, (double)size / 1.024e3, (double)size / 1.048576e6 ); + printf ("Load Address: 0x%08X\n", ntohl(hdr->ih_load)); + printf ("Entry Point: 0x%08X\n", ntohl(hdr->ih_ep)); + + if (hdr->ih_type == IH_TYPE_MULTI || hdr->ih_type == IH_TYPE_SCRIPT) { + int i, ptrs; + uint32_t pos; + unsigned long *len_ptr = (unsigned long *) ( + (unsigned long)hdr + sizeof(image_header_t) + ); + + /* determine number of images first (to calculate image offsets) */ + for (i=0; len_ptr[i]; ++i) /* null pointer terminates list */ + ; + ptrs = i; /* null pointer terminates list */ + + pos = sizeof(image_header_t) + ptrs * sizeof(long); + printf ("Contents:\n"); + for (i=0; len_ptr[i]; ++i) { + size = ntohl(len_ptr[i]); + + printf (" Image %d: %8d Bytes = %4d kB = %d MB\n", + i, size, size>>10, size>>20); + if (hdr->ih_type == IH_TYPE_SCRIPT && i > 0) { + /* + * the user may need to know offsets + * if planning to do something with + * multiple files + */ + printf (" Offset = %08X\n", pos); + } + /* copy_file() will pad the first files to even word align */ + size += 3; + size &= ~3; + pos += size; + } + } +} + + +static void +print_type (image_header_t *hdr) +{ + printf ("%s %s %s (%s)\n", + put_arch (hdr->ih_arch), + put_os (hdr->ih_os ), + put_type (hdr->ih_type), + put_comp (hdr->ih_comp) + ); +} + +static char *put_arch (int arch) +{ + return (put_table_entry(arch_name, "Unknown Architecture", arch)); +} + +static char *put_os (int os) +{ + return (put_table_entry(os_name, "Unknown OS", os)); +} + +static char *put_type (int type) +{ + return (put_table_entry(type_name, "Unknown Image", type)); +} + +static char *put_comp (int comp) +{ + return (put_table_entry(comp_name, "Unknown Compression", comp)); +} + +static char *put_table_entry (table_entry_t *table, char *msg, int type) +{ + for (; table->val>=0; ++table) { + if (table->val == type) + return (table->lname); + } + return (msg); +} + +static int get_arch(char *name) +{ + return (get_table_entry(arch_name, "CPU", name)); +} + + +static int get_comp(char *name) +{ + return (get_table_entry(comp_name, "Compression", name)); +} + + +static int get_os (char *name) +{ + return (get_table_entry(os_name, "OS", name)); +} + + +static int get_type(char *name) +{ + return (get_table_entry(type_name, "Image", name)); +} + +static int get_table_entry (table_entry_t *table, char *msg, char *name) +{ + table_entry_t *t; + int first = 1; + + for (t=table; t->val>=0; ++t) { + if (t->sname && strcasecmp(t->sname, name)==0) + return (t->val); + } + fprintf (stderr, "\nInvalid %s Type - valid names are", msg); + for (t=table; t->val>=0; ++t) { + if (t->sname == NULL) + continue; + fprintf (stderr, "%c %s", (first) ? ':' : ',', t->sname); + first = 0; + } + fprintf (stderr, "\n"); + return (-1); +} diff --git a/tools/mpc86x_clk.c b/tools/mpc86x_clk.c new file mode 100644 index 0000000..8dfbd4e --- /dev/null +++ b/tools/mpc86x_clk.c @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2003 Intracom S.A. + * Pantelis Antoniou + * + * This little program makes an exhaustive search for the + * correct terms of pdf, mfi, mfn, mfd, s, dbrmo, in PLPRCR. + * The goal is to produce a gclk2 from a xin input, while respecting + * all the restrictions on their combination. + * + * Generaly you select the first row of the produced table. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#define DPREF_MIN 10000000 +#define DPREF_MAX 32000000 + +#define DPGDCK_MAX 320000000 +#define DPGDCK_MIN 160000000 + +#define S_MIN 0 +#define S_MAX 2 + +#define MFI_MIN 5 +#define MFI_MAX 15 + +#define MFN_MIN 0 +#define MFN_MAX 15 + +#define MFD_MIN 0 +#define MFD_MAX 31 + +#define MF_MIN 5 +#define MF_MAX 15 + +#define PDF_MIN 0 +#define PDF_MAX 15 + +#define GCLK2_MAX 150000000 + +static int calculate (int xin, int target_clock, + int ppm, int pdf, int mfi, int mfn, int mfd, int s, + int *dprefp, int *dpgdckp, int *jdbckp, + int *gclk2p, int *dbrmop) +{ + unsigned int dpref, dpgdck, jdbck, gclk2, t1, t2, dbrmo; + + /* valid MFI? */ + if (mfi < MFI_MIN) + return -1; + + /* valid num, denum? */ + if (mfn > 0 && mfn >= mfd) + return -1; + + dpref = xin / (pdf + 1); + + /* valid dpef? */ + if (dpref < DPREF_MIN || dpref > DPREF_MAX) + return -1; + + if (mfn == 0) { + dpgdck = (2 * mfi * xin) / (pdf + 1) ; + dbrmo = 0; + } else { + /* 5 <= mfi + (mfn / mfd + 1) <= 15 */ + t1 = mfd + 1; + t2 = mfi * t1 + mfn; + if ( MF_MIN * t1 > t2 || MF_MAX * t1 < t2) + return -1; + + dpgdck = (unsigned int)(2 * (mfi * mfd + mfi + mfn) * + (unsigned int)xin) / + ((mfd + 1) * (pdf + 1)); + + dbrmo = 10 * mfn < (mfd + 1); + } + + /* valid dpgclk? */ + if (dpgdck < DPGDCK_MIN || dpgdck > DPGDCK_MAX) + return -1; + + jdbck = dpgdck >> s; + gclk2 = jdbck / 2; + + /* valid gclk2 */ + if (gclk2 > GCLK2_MAX) + return -1; + + t1 = abs(gclk2 - target_clock); + + /* XXX max 1MHz dev. in clock */ + if (t1 > 1000000) + return -1; + + /* dev within range (XXX gclk2 scaled to avoid overflow) */ + if (t1 * 1000 > (unsigned int)ppm * (gclk2 / 1000)) + return -1; + + *dprefp = dpref; + *dpgdckp = dpgdck; + *jdbckp = jdbck; + *gclk2p = gclk2; + *dbrmop = dbrmo; + + return gclk2; +} + +int conf_clock(int xin, int target_clock, int ppm) +{ + int pdf, s, mfn, mfd, mfi; + int dpref, dpgdck, jdbck, gclk2, xout, dbrmo; + int found = 0; + + /* integer multipliers */ + for (pdf = PDF_MIN; pdf <= PDF_MAX; pdf++) { + for (mfi = MFI_MIN; mfi <= MFI_MAX; mfi++) { + for (s = 0; s <= S_MAX; s++) { + xout = calculate(xin, target_clock, + ppm, pdf, mfi, 0, 0, s, + &dpref, &dpgdck, &jdbck, + &gclk2, &dbrmo); + if (xout < 0) + continue; + + if (found == 0) { + printf("pdf mfi mfn mfd s dbrmo dpref dpgdck jdbck gclk2 exact?\n"); + printf("--- --- --- --- - ----- ----- ------ ----- ----- ------\n"); + } + + printf("%3d %3d --- --- %1d %5d %9d %9d %9d %9d%s\n", + pdf, mfi, s, dbrmo, + dpref, dpgdck, jdbck, gclk2, + gclk2 == target_clock ? " YES" : ""); + + found++; + } + } + } + + /* fractional multipliers */ + for (pdf = PDF_MIN; pdf <= PDF_MAX; pdf++) { + for (mfi = MFI_MIN; mfi <= MFI_MAX; mfi++) { + for (mfn = 1; mfn <= MFN_MAX; mfn++) { + for (mfd = 1; mfd <= MFD_MAX; mfd++) { + for (s = 0; s <= S_MAX; s++) { + xout = calculate(xin, target_clock, + ppm, pdf, mfi, mfn, mfd, s, + &dpref, &dpgdck, &jdbck, + &gclk2, &dbrmo); + if (xout < 0) + continue; + + if (found == 0) { + printf("pdf mfi mfn mfd s dbrmo dpref dpgdck jdbck gclk2 exact?\n"); + printf("--- --- --- --- - ----- ----- ------ ----- ----- ------\n"); + } + + printf("%3d %3d %3d %3d %1d %5d %9d %9d %9d %9d%s\n", + pdf, mfi, mfn, mfd, s, + dbrmo, dpref, dpgdck, jdbck, gclk2, + gclk2 == target_clock ? " YES" : ""); + + found++; + } + } + } + + } + } + + return found; +} + +int main(int argc, char *argv[]) +{ + int xin, want_gclk2, found, ppm = 100; + + if (argc < 3) { + fprintf(stderr, "usage: mpc86x_clk [ppm]\n"); + fprintf(stderr, " default ppm is 100\n"); + return 10; + } + + xin = atoi(argv[1]); + want_gclk2 = atoi(argv[2]); + if (argc >= 4) + ppm = atoi(argv[3]); + + found = conf_clock(xin, want_gclk2, ppm); + if (found <= 0) { + fprintf(stderr, "cannot produce gclk2 %d from xin %d\n", + want_gclk2, xin); + return EXIT_FAILURE; + } + + return EXIT_SUCCESS; +} diff --git a/tools/ncb.c b/tools/ncb.c new file mode 100644 index 0000000..74deebb --- /dev/null +++ b/tools/ncb.c @@ -0,0 +1,36 @@ +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int s, len, o, port = 6666; + char buf[512]; + struct sockaddr_in addr; + int addr_len = sizeof addr; + + if (argc > 1) + port = atoi (argv[1]); + + s = socket (PF_INET, SOCK_DGRAM, IPPROTO_UDP); + + o = 1; + len = 4; + setsockopt (3, SOL_SOCKET, SO_REUSEADDR, &o, len); + + addr.sin_family = AF_INET; + addr.sin_port = htons (port); + addr.sin_addr.s_addr = INADDR_ANY; /* receive broadcasts */ + + bind (s, (struct sockaddr *) &addr, sizeof addr); + + for (;;) { + len = recvfrom (s, buf, sizeof buf, 0, (struct sockaddr *) &addr, &addr_len); + if (len < 0) + break; + write (1, buf, len); + } + + return 0; +} diff --git a/tools/scripts/README b/tools/scripts/README new file mode 100644 index 0000000..046c1d4 --- /dev/null +++ b/tools/scripts/README @@ -0,0 +1,67 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# The files in this directory are free software; you can redistribute +# them and/or modify them under the terms of the GNU General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# These files are distributed in the hope that they will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +This directory contains scripts that help to perform certain actions +that need to be done frequently when working with U-Boot. + +They are meant as EXAMPLE code, so it is very likely that you will +have to modify them before use. + + +Short description: +================== + +dot.kermrc: + + Example for "~/.kermrc" Kermit init file for use with U-Boot + + by Wolfgang Denk, 24 Jun 2001 + +flash_param: + + "kermit" script to automatically initialize the environment + variables on your target. This is most useful during + development when your environment variables are stored in an + embedded flash sector which is erased whenever you install a + new U-Boot image. + + by Swen Anderson, 10 May 2001 + +send_cmd: + + send_cmd U_BOOT_COMMAND + + "kermit" script to send a U-Boot command and print the + results. When used from a shell with history (like the bash) + this indirectly adds kind of history to U-Boot ;-) + + by Swen Anderson, 10 May 2001 + +send_image: + + send_image FILE_NAME OFFSET + + "kermit" script to automatically download a file to the + target using the "loadb" command (kermit binary protocol) + + by Swen Anderson, 10 May 2001 diff --git a/tools/scripts/dot.kermrc b/tools/scripts/dot.kermrc new file mode 100644 index 0000000..0fc6c15 --- /dev/null +++ b/tools/scripts/dot.kermrc @@ -0,0 +1,16 @@ +set line /dev/ttyS0 +set speed 115200 +set carrier-watch off +set handshake none +set flow-control none +robust +set file type bin +set file name lit +set rec pack 1000 +set send pack 1000 +set window 5 +set prompt Kermit> +define sz !sz \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line) +define rz !rz \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line) +define sx !sx \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line) +define rx !rx \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line) diff --git a/tools/scripts/flash_param b/tools/scripts/flash_param new file mode 100644 index 0000000..847f99e --- /dev/null +++ b/tools/scripts/flash_param @@ -0,0 +1,60 @@ +#!/usr/bin/kermit + +# usage: ./flash_param parameters +# Parameters: IP Address ETH Address ERIC Number +# Format: xxx.xxx.xxx.xxx xx:xx:xx:xx:xx:xx xxxx + +set line /dev/ttyS0 +set speed 115200 +set serial 8N1 +set carrier-watch off +set handshake none +#set flow-control none +set flow-control xon/xoff +#robust +set file type bin +set file name lit +set rec pack 1000 +set send pack 1000 +set window 5 +set prompt Kermit> +#robust +# Milliseconds to pause between each OUTPUT character +set output pacing 1 + +out \13 +in 10 => +#first erase the environment memory within NVRAM +out mw f0000000 0 200\13 +in 10 => +out reset\13 +in 5 autoboot +out \13\13 +in 10 => +#set additional env parameter +out setenv ethaddr \%2\13 +in 10 => +out setenv serial# ERIC 1.0 \%3\13 +in 10 => +out setenv eric_id \%3\13 +in 10 => +#out setenv prec_videocard_bus unknown\13 +#in 10 => +#out setenv prec_bios_type unknown\13 +#in 10 => +out setenv eric_passwd .eRIC.\13 +in 10 => +#out setenv bootargs root=/dev/ram ramdisk_size=8192 init=/sbin/init ip=\%1:192.168.1.100:192.168.1.254:255.255.255.0\13 +#out setenv bootargs root=/dev/ram ramdisk_size=8192 init=/sbin/init ip=\%1:192.168.0.1\13 +#out setenv bootargs root=/dev/ram ramdisk_size=8192 init=/sbin/init ip=\%1\13 +out setenv bootargs console=/dev/ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.26:/eric_root_devel ip=\%1:192.168.1.26\13 +in 10 => +out setenv bootcmd bootm FFC00000\13 +in 10 => +out saveenv\13 +in 10 => +out reset\13 +in 5 autoboot +out \13\13 +in 10 => +quit +exit 0 diff --git a/tools/scripts/send_cmd b/tools/scripts/send_cmd new file mode 100644 index 0000000..4131331 --- /dev/null +++ b/tools/scripts/send_cmd @@ -0,0 +1,21 @@ +#!/usr/bin/kermit + +set line /dev/ttyS0 +set speed 115200 +set serial 8N1 +set carrier-watch off +set handshake none +set flow-control none +robust +set file type bin +set file name lit +set rec pack 1000 +set send pack 1000 +set window 5 +set prompt Kermit> + +#out \13 +#in 10 => +out \%1 \%2 \%3 \%4 \%5 \%6 \%7\13 +in 10 => +quit +exit 0 diff --git a/tools/scripts/send_image b/tools/scripts/send_image new file mode 100644 index 0000000..9b89d6b --- /dev/null +++ b/tools/scripts/send_image @@ -0,0 +1,26 @@ +#!/usr/bin/kermit + +# usage: send_image FILE_NAME OFFSET +# e.g. send_image output.bin 1F00000 +set line /dev/ttyS0 +set speed 115200 +set serial 8N1 +set carrier-watch off +set handshake none +set flow-control none +robust +set file type bin +set file name lit +set rec pack 1000 +set send pack 1000 +set window 5 +set prompt Kermit> + +out \13 +in 10 => +out loadb \%2 \13 +in 10 download ... +send \%1 +out \13 +in 10 ## Start Addr +quit +exit 0 diff --git a/tools/updater/Makefile b/tools/updater/Makefile new file mode 100644 index 0000000..3fa1912 --- /dev/null +++ b/tools/updater/Makefile @@ -0,0 +1,86 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +LOAD_ADDR = 0x40000 + +include $(TOPDIR)/config.mk + +PROG = updater +IMAGE = updater.image +SRC = update.c flash.c flash_hw.c utils.c cmd_flash.c string.c ctype.c dummy.c +ASRC = ppcstring.S +OBJS = $(SRC:.c=.o) $(ASRC:.S=.o) + +LIB = $(TOPDIR)/examples/libstubs.a +LIBAOBJS= +LIBCOBJS= $(TOPDIR)/examples/stubs.o +LIBOBJS = $(LIBAOBJS) $(LIBCOBJS) + +CPPFLAGS += -I$(TOPDIR) -I$(TOPDIR)/board/MAI/AmigaOneG3SE +CFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE + +all: .depend $(LIB) $(PROG) + +######################################################################### +$(LIB): .depend $(LIBOBJS) + $(AR) crv $@ $(LIBOBJS) + +%.srec: %.o $(LIB) + $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $< $(LIB) + $(OBJCOPY) -O srec $(<:.o=) $@ + +%.o: %.c + $(CC) $(CPPFLAGS) -c $< + +%.o: %.S + $(CC) $(CPPFLAGS) -c $< + +######################################################################### + +updater: $(OBJS) $(LIB) $(TOPDIR)/board/MAI/AmigaOneG3SE/memio.o + $(LD) -g -Ttext $(LOAD_ADDR) -o updater -e _main $(OBJS) $(LIB) \ + $(TOPDIR)/board/MAI/AmigaOneG3SE/memio.o + $(OBJCOPY) -O binary updater updater.bin + +updater.image: updater $(TOPDIR)/u-boot.bin + cat >/tmp/tempimage updater.bin junk $(TOPDIR)/u-boot.bin + $(TOPDIR)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \ + -e `ppc-elf32-nm updater | grep _main | cut --bytes=0-8` \ + -n "Firmware Updater" -d /tmp/tempimage updater.image + rm /tmp/tempimage + cp updater.image /tftpboot + +updater.image2: updater $(TOPDIR)/u-boot.bin + cat >/tmp/tempimage updater.bin junk ../../create_image/image + $(TOPDIR)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \ + -e `ppc-elf32-nm updater | grep _main | cut --bytes=0-8` \ + -n "Firmware Updater" -d /tmp/tempimage updater.image + rm /tmp/tempimage + cp updater.image /tftpboot + +.depend: Makefile $(SRC) $(ASRC) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(SRC) $(ASRC) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) > $@ + +sinclude .depend + +######################################################################### diff --git a/tools/updater/cmd_flash.c b/tools/updater/cmd_flash.c new file mode 100644 index 0000000..c0e5772 --- /dev/null +++ b/tools/updater/cmd_flash.c @@ -0,0 +1,430 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * FLASH support + */ +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +/* + * The user interface starts numbering for Flash banks with 1 + * for historical reasons. + */ + +/* + * this routine looks for an abbreviated flash range specification. + * the syntax is B:SF[-SL], where B is the bank number, SF is the first + * sector to erase, and SL is the last sector to erase (defaults to SF). + * bank numbers start at 1 to be consistent with other specs, sector numbers + * start at zero. + * + * returns: 1 - correct spec; *pinfo, *psf and *psl are + * set appropriately + * 0 - doesn't look like an abbreviated spec + * -1 - looks like an abbreviated spec, but got + * a parsing error, a number out of range, + * or an invalid flash bank. + */ +static int +abbrev_spec(char *str, flash_info_t **pinfo, int *psf, int *psl) +{ + flash_info_t *fp; + int bank, first, last; + char *p, *ep; + + if ((p = strchr(str, ':')) == NULL) + return 0; + *p++ = '\0'; + + bank = simple_strtoul(str, &ep, 10); + if (ep == str || *ep != '\0' || + bank < 1 || bank > CFG_MAX_FLASH_BANKS || + (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN) + return -1; + + str = p; + if ((p = strchr(str, '-')) != NULL) + *p++ = '\0'; + + first = simple_strtoul(str, &ep, 10); + if (ep == str || *ep != '\0' || first >= fp->sector_count) + return -1; + + if (p != NULL) { + last = simple_strtoul(p, &ep, 10); + if (ep == p || *ep != '\0' || + last < first || last >= fp->sector_count) + return -1; + } + else + last = first; + + *pinfo = fp; + *psf = first; + *psl = last; + + return 1; +} +int do_flinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + ulong bank; + + if (argc == 1) { /* print info for all FLASH banks */ + for (bank=0; bank CFG_MAX_FLASH_BANKS)) { + printf ("Only FLASH Banks # 1 ... # %d supported\n", + CFG_MAX_FLASH_BANKS); + return 1; + } + printf ("\nBank # %ld: ", bank); + flash_print_info (&flash_info[bank-1]); + return 0; +} +int do_flerase(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + flash_info_t *info; + ulong bank, addr_first, addr_last; + int n, sect_first, sect_last; + int rcode = 0; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "all") == 0) { + for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) { + printf ("Erase Flash Bank # %ld ", bank); + info = &flash_info[bank-1]; + rcode = flash_erase (info, 0, info->sector_count-1); + } + return rcode; + } + + if ((n = abbrev_spec(argv[1], &info, §_first, §_last)) != 0) { + if (n < 0) { + printf("Bad sector specification\n"); + return 1; + } + printf ("Erase Flash Sectors %d-%d in Bank # %d ", + sect_first, sect_last, (info-flash_info)+1); + rcode = flash_erase(info, sect_first, sect_last); + return rcode; + } + + if (argc != 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "bank") == 0) { + bank = simple_strtoul(argv[2], NULL, 16); + if ((bank < 1) || (bank > CFG_MAX_FLASH_BANKS)) { + printf ("Only FLASH Banks # 1 ... # %d supported\n", + CFG_MAX_FLASH_BANKS); + return 1; + } + printf ("Erase Flash Bank # %ld ", bank); + info = &flash_info[bank-1]; + rcode = flash_erase (info, 0, info->sector_count-1); + return rcode; + } + + addr_first = simple_strtoul(argv[1], NULL, 16); + addr_last = simple_strtoul(argv[2], NULL, 16); + + if (addr_first >= addr_last) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + printf ("Erase Flash from 0x%08lx to 0x%08lx ", addr_first, addr_last); + rcode = flash_sect_erase(addr_first, addr_last); + return rcode; +} + +int flash_sect_erase (ulong addr_first, ulong addr_last) +{ + flash_info_t *info; + ulong bank; + int s_first, s_last; + int erased; + int rcode = 0; + + erased = 0; + + for (bank=0,info=&flash_info[0]; bank < CFG_MAX_FLASH_BANKS; ++bank, ++info) { + ulong b_end; + int sect; + + if (info->flash_id == FLASH_UNKNOWN) { + continue; + } + + b_end = info->start[0] + info->size - 1; /* bank end addr */ + + s_first = -1; /* first sector to erase */ + s_last = -1; /* last sector to erase */ + + for (sect=0; sect < info->sector_count; ++sect) { + ulong end; /* last address in current sect */ + short s_end; + + s_end = info->sector_count - 1; + + end = (sect == s_end) ? b_end : info->start[sect + 1] - 1; + + if (addr_first > end) + continue; + if (addr_last < info->start[sect]) + continue; + + if (addr_first == info->start[sect]) { + s_first = sect; + } + if (addr_last == end) { + s_last = sect; + } + } + if (s_first>=0 && s_first<=s_last) { + erased += s_last - s_first + 1; + rcode = flash_erase (info, s_first, s_last); + } + } + if (erased) { + /* printf ("Erased %d sectors\n", erased); */ + } else { + printf ("Error: start and/or end address" + " not on sector boundary\n"); + rcode = 1; + } + return rcode; +} + + +int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + flash_info_t *info; + ulong bank, addr_first, addr_last; + int i, p, n, sect_first, sect_last; + int rcode = 0; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "off") == 0) + p = 0; + else if (strcmp(argv[1], "on") == 0) + p = 1; + else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[2], "all") == 0) { + for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) { + info = &flash_info[bank-1]; + if (info->flash_id == FLASH_UNKNOWN) { + continue; + } + /*printf ("%sProtect Flash Bank # %ld\n", */ + /* p ? "" : "Un-", bank); */ + + for (i=0; isector_count; ++i) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, i, p)) + rcode = 1; + putc ('.'); +#else + info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ + } + } + +#if defined(CFG_FLASH_PROTECTION) + if (!rcode) puts (" done\n"); +#endif /* CFG_FLASH_PROTECTION */ + + return rcode; + } + + if ((n = abbrev_spec(argv[2], &info, §_first, §_last)) != 0) { + if (n < 0) { + printf("Bad sector specification\n"); + return 1; + } + /*printf("%sProtect Flash Sectors %d-%d in Bank # %d\n", */ + /* p ? "" : "Un-", sect_first, sect_last, */ + /* (info-flash_info)+1); */ + for (i = sect_first; i <= sect_last; i++) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, i, p)) + rcode = 1; + putc ('.'); +#else + info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ + } + +#if defined(CFG_FLASH_PROTECTION) + if (!rcode) puts (" done\n"); +#endif /* CFG_FLASH_PROTECTION */ + + return rcode; + } + + if (argc != 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[2], "bank") == 0) { + bank = simple_strtoul(argv[3], NULL, 16); + if ((bank < 1) || (bank > CFG_MAX_FLASH_BANKS)) { + printf ("Only FLASH Banks # 1 ... # %d supported\n", + CFG_MAX_FLASH_BANKS); + return 1; + } + printf ("%sProtect Flash Bank # %ld\n", + p ? "" : "Un-", bank); + info = &flash_info[bank-1]; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return 1; + } + for (i=0; isector_count; ++i) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, i, p)) + rcode = 1; + putc ('.'); +#else + info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ + } + +#if defined(CFG_FLASH_PROTECTION) + if (!rcode) puts (" done\n"); +#endif /* CFG_FLASH_PROTECTION */ + + return rcode; + } + + addr_first = simple_strtoul(argv[2], NULL, 16); + addr_last = simple_strtoul(argv[3], NULL, 16); + + if (addr_first >= addr_last) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + rcode = flash_sect_protect (p, addr_first, addr_last); + return rcode; +} +int flash_sect_protect (int p, ulong addr_first, ulong addr_last) +{ + flash_info_t *info; + ulong bank; + int s_first, s_last; + int protected, i; + int rcode = 0; + + protected = 0; + + for (bank=0,info=&flash_info[0]; bank < CFG_MAX_FLASH_BANKS; ++bank, ++info) { + ulong b_end; + int sect; + + if (info->flash_id == FLASH_UNKNOWN) { + continue; + } + + b_end = info->start[0] + info->size - 1; /* bank end addr */ + + s_first = -1; /* first sector to erase */ + s_last = -1; /* last sector to erase */ + + for (sect=0; sect < info->sector_count; ++sect) { + ulong end; /* last address in current sect */ + short s_end; + + s_end = info->sector_count - 1; + + end = (sect == s_end) ? b_end : info->start[sect + 1] - 1; + + if (addr_first > end) + continue; + if (addr_last < info->start[sect]) + continue; + + if (addr_first == info->start[sect]) { + s_first = sect; + } + if (addr_last == end) { + s_last = sect; + } + } + if (s_first>=0 && s_first<=s_last) { + protected += s_last - s_first + 1; + for (i=s_first; i<=s_last; ++i) { +#if defined(CFG_FLASH_PROTECTION) + if (flash_real_protect(info, i, p)) + rcode = 1; + putc ('.'); +#else + info->protect[i] = p; +#endif /* CFG_FLASH_PROTECTION */ + } + } +#if defined(CFG_FLASH_PROTECTION) + if (!rcode) putc ('\n'); +#endif /* CFG_FLASH_PROTECTION */ + + } + if (protected) { + /* printf ("%sProtected %d sectors\n", */ + /* p ? "" : "Un-", protected); */ + } else { + printf ("Error: start and/or end address" + " not on sector boundary\n"); + rcode = 1; + } + return rcode; +} + +#endif /* CFG_CMD_FLASH */ diff --git a/tools/updater/ctype.c b/tools/updater/ctype.c new file mode 100644 index 0000000..6ed0468 --- /dev/null +++ b/tools/updater/ctype.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * linux/lib/ctype.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +#include + +unsigned char _ctype[] = { +_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ +_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ +_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ +_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ +_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ +_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ +_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ +_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ +_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ +_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ +_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */ +_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */ +_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */ +_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */ +_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */ +_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */ diff --git a/tools/updater/dummy.c b/tools/updater/dummy.c new file mode 100644 index 0000000..9fe5ac1 --- /dev/null +++ b/tools/updater/dummy.c @@ -0,0 +1 @@ +volatile int __dummy = 0xDEADBEEF; diff --git a/tools/updater/flash.c b/tools/updater/flash.c new file mode 100644 index 0000000..32a1767 --- /dev/null +++ b/tools/updater/flash.c @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +/*----------------------------------------------------------------------- + * Set protection status for monitor sectors + * + * The monitor is always located in the _first_ Flash bank. + * If necessary you have to map the second bank at lower addresses. + */ +void +flash_protect (int flag, ulong from, ulong to, flash_info_t *info) +{ + ulong b_end = info->start[0] + info->size - 1; /* bank end address */ + short s_end = info->sector_count - 1; /* index of last sector */ + int i; + + /* Do nothing if input data is bad. */ + if (info->sector_count == 0 || info->size == 0 || to < from) { + return; + } + + /* There is nothing to do if we have no data about the flash + * or the protect range and flash range don't overlap. + */ + if (info->flash_id == FLASH_UNKNOWN || + to < info->start[0] || from > b_end) { + return; + } + + for (i=0; isector_count; ++i) { + ulong end; /* last address in current sect */ + + end = (i == s_end) ? b_end : info->start[i + 1] - 1; + + /* Update protection if any part of the sector + * is in the specified range. + */ + if (from <= end && to >= info->start[i]) { + if (flag & FLAG_PROTECT_CLEAR) { +#if defined(CFG_FLASH_PROTECTION) + flash_real_protect(info, i, 0); +#else + info->protect[i] = 0; +#endif /* CFG_FLASH_PROTECTION */ + } + else if (flag & FLAG_PROTECT_SET) { +#if defined(CFG_FLASH_PROTECTION) + flash_real_protect(info, i, 1); +#else + info->protect[i] = 1; +#endif /* CFG_FLASH_PROTECTION */ + } + } + } +} + +/*----------------------------------------------------------------------- + */ + +flash_info_t * +addr2info (ulong addr) +{ +#ifndef CONFIG_SPD823TS + flash_info_t *info; + int i; + + for (i=0, info=&flash_info[0]; iflash_id != FLASH_UNKNOWN && + addr >= info->start[0] && + /* WARNING - The '- 1' is needed if the flash + * is at the end of the address space, since + * info->start[0] + info->size wraps back to 0. + * Please don't change this unless you understand this. + */ + addr <= info->start[0] + info->size - 1) { + return (info); + } + } +#endif /* CONFIG_SPD823TS */ + + return (NULL); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + * Make sure all target addresses are within Flash bounds, + * and no protected sectors are hit. + * Returns: + * ERR_OK 0 - OK + * ERR_TIMOUT 1 - write timeout + * ERR_NOT_ERASED 2 - Flash not erased + * ERR_PROTECTED 4 - target range includes protected sectors + * ERR_INVAL 8 - target address not in Flash memory + * ERR_ALIGN 16 - target address not aligned on boundary + * (only some targets require alignment) + */ +int +flash_write (uchar *src, ulong addr, ulong cnt) +{ +#ifdef CONFIG_SPD823TS + return (ERR_TIMOUT); /* any other error codes are possible as well */ +#else + int i; + ulong end = addr + cnt - 1; + flash_info_t *info_first = addr2info (addr); + flash_info_t *info_last = addr2info (end ); + flash_info_t *info; + int j; + + if (cnt == 0) { + return (ERR_OK); + } + + if (!info_first || !info_last) { + return (ERR_INVAL); + } + + for (info = info_first; info <= info_last; ++info) { + ulong b_end = info->start[0] + info->size; /* bank end addr */ + short s_end = info->sector_count - 1; + for (i=0; isector_count; ++i) { + ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; + + if ((end >= info->start[i]) && (addr < e_addr) && + (info->protect[i] != 0) ) { + return (ERR_PROTECTED); + } + } + } + + printf("\rWriting "); + for (j=0; j<20; j++) putc(177); + printf("\rWriting "); + + /* finally write data to flash */ + for (info = info_first; info <= info_last && cnt>0; ++info) { + ulong len; + + len = info->start[0] + info->size - addr; + if (len > cnt) + len = cnt; + + if ((i = write_buff(info, src, addr, len)) != 0) { + return (i); + } + cnt -= len; + addr += len; + src += len; + } + return (ERR_OK); +#endif /* CONFIG_SPD823TS */ +} + +/*----------------------------------------------------------------------- + */ diff --git a/tools/updater/flash_hw.c b/tools/updater/flash_hw.c new file mode 100644 index 0000000..2d9b8c8 --- /dev/null +++ b/tools/updater/flash_hw.c @@ -0,0 +1,659 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +flash_info_t flash_info[]; + +static ulong flash_get_size (ulong addr, flash_info_t *info); +static int flash_get_offsets (ulong base, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_reset (ulong addr); + +int flash_xd_nest; + +static void flash_to_xd(void) +{ + unsigned char x; + + flash_xd_nest ++; + + if (flash_xd_nest == 1) + { + DEBUGF("Flash on XD\n"); + x = pci_read_cfg_byte(0, 0, 0x74); + pci_write_cfg_byte(0, 0, 0x74, x|1); + } +} + +static void flash_to_mem(void) +{ + unsigned char x; + + flash_xd_nest --; + + if (flash_xd_nest == 0) + { + DEBUGF("Flash on memory bus\n"); + x = pci_read_cfg_byte(0, 0, 0x74); + pci_write_cfg_byte(0, 0, 0x74, x&0xFE); + } +} + +unsigned long flash_init_old(void) +{ + int i; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = 0; + flash_info[i].size = 0; + } + + + return 1; +} + +unsigned long flash_init (void) +{ + unsigned int i; + unsigned long flash_size = 0; + + flash_xd_nest = 0; + + flash_to_xd(); + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE && \ + CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + } else { + printf ("Warning: the BOOT Flash is not initialised !"); + } + + flash_to_mem(); + + return flash_size; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (ulong addr, flash_info_t *info) +{ + short i; + uchar value; + uchar *x = (uchar *)addr; + + flash_to_xd(); + + /* Write auto select command: read Manufacturer ID */ + x[0x0555] = 0xAA; + __asm volatile ("sync\n eieio"); + x[0x02AA] = 0x55; + __asm volatile ("sync\n eieio"); + x[0x0555] = 0x90; + __asm volatile ("sync\n eieio"); + + value = x[0]; + __asm volatile ("sync\n eieio"); + + DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); + + switch (value | (value << 16)) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + + case STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + flash_reset (addr); + return 0; + } + + value = x[1]; + __asm volatile ("sync\n eieio"); + + DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value); + + switch (value) { + case AMD_ID_F040B: + DEBUGF("Am29F040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + + case AMD_ID_LV040B: + DEBUGF("Am29LV040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + + case AMD_ID_LV400T: + DEBUGF("Am29LV400T\n"); + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + DEBUGF("Am29LV400B\n"); + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + DEBUGF("Am29LV800T\n"); + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + DEBUGF("Am29LV400B\n"); + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV160T: + DEBUGF("Am29LV160T\n"); + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + DEBUGF("Am29LV160B\n"); + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV320T: + DEBUGF("Am29LV320T\n"); + info->flash_id += FLASH_AM320T; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ + +#if 0 + /* Has the same ID as AMD_ID_LV320T, to be fixed */ + case AMD_ID_LV320B: + DEBUGF("Am29LV320B\n"); + info->flash_id += FLASH_AM320B; + info->sector_count = 67; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif + + case AMD_ID_LV033C: + DEBUGF("Am29LV033C\n"); + info->flash_id += FLASH_AM033C; + info->sector_count = 64; + info->size = 0x01000000; + break; /* => 16Mb */ + + case STM_ID_F040B: + DEBUGF("M29F040B\n"); + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512 kB */ + + default: + info->flash_id = FLASH_UNKNOWN; + flash_reset (addr); + flash_to_mem(); + return (0); /* => no or unknown flash */ + + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + if (! flash_get_offsets (addr, info)) { + flash_reset (addr); + flash_to_mem(); + return 0; + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + value = in8(info->start[i] + 2); + iobarrier_rw(); + info->protect[i] = (value & 1) != 0; + } + + /* + * Reset bank to read mode + */ + flash_reset (addr); + + flash_to_mem(); + + return (info->size); +} + +static int flash_get_offsets (ulong base, flash_info_t *info) +{ + unsigned int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + /* set sector offsets for uniform sector type */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + i * info->size / + info->sector_count; + } + break; + default: + return 0; + } + + return 1; +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile ulong addr = info->start[0]; + int flag, prot, sect, l_sect; + ulong start, now, last; + + flash_to_xd(); + + if (s_first < 0 || s_first > s_last) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + flash_to_mem(); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + flash_to_mem(); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf (""); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + out8(addr + 0x555, 0x80); + iobarrier_rw(); + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = info->start[sect]; + out8(addr, 0x30); + iobarrier_rw(); + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = info->start[l_sect]; + + DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT); + + while ((in8(addr) & 0x80) != 0x80) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + flash_reset (info->start[0]); + flash_to_mem(); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + iobarrier_rw(); + } + +DONE: + /* reset to read mode */ + flash_reset (info->start[0]); + flash_to_mem(); + + printf (" done\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + ulong out_cnt = 0; + + flash_to_xd(); + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + flash_to_mem(); + return (rc); + } + wp += 4; + } + + putc(219); + + /* + * handle word aligned part + */ + while (cnt >= 4) { + if (out_cnt>26214) + { + putc(219); + out_cnt = 0; + } + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + flash_to_mem(); + return (rc); + } + wp += 4; + cnt -= 4; + out_cnt += 4; + } + + if (cnt == 0) { + flash_to_mem(); + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + flash_to_mem(); + return (write_word(info, wp, data)); +} + +/* + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile ulong addr = info->start[0]; + ulong start; + int i; + + flash_to_xd(); + + /* Check if Flash is (sufficiently) erased */ + if ((in32(dest) & data) != data) { + flash_to_mem(); + return (2); + } + + /* write each byte out */ + for (i = 0; i < 4; i++) { + char *data_ch = (char *)&data; + int flag = disable_interrupts(); + + out8(addr + 0x555, 0xAA); + iobarrier_rw(); + out8(addr + 0x2AA, 0x55); + iobarrier_rw(); + out8(addr + 0x555, 0xA0); + iobarrier_rw(); + out8(dest+i, data_ch[i]); + iobarrier_rw(); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flash_reset (addr); + flash_to_mem(); + return (1); + } + iobarrier_rw(); + } + } + + flash_reset (addr); + flash_to_mem(); + return (0); +} + +/* + * Reset bank to read mode + */ +static void flash_reset (ulong addr) +{ + flash_to_xd(); + out8(addr, 0xF0); /* reset bank */ + iobarrier_rw(); + flash_to_mem(); +} + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_STM: printf ("SGS THOMSON "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + if (info->size % 0x100000 == 0) { + printf (" Size: %ld MB in %d Sectors\n", + info->size / 0x100000, info->sector_count); + } else if (info->size % 0x400 == 0) { + printf (" Size: %ld KB in %d Sectors\n", + info->size / 0x400, info->sector_count); + } else { + printf (" Size: %ld B in %d Sectors\n", + info->size, info->sector_count); + } + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} diff --git a/tools/updater/junk b/tools/updater/junk new file mode 100644 index 0000000..f73285a --- /dev/null +++ b/tools/updater/junk @@ -0,0 +1 @@ +................................................................................................................................................................................................................................................................ \ No newline at end of file diff --git a/tools/updater/ppcstring.S b/tools/updater/ppcstring.S new file mode 100644 index 0000000..97023a0 --- /dev/null +++ b/tools/updater/ppcstring.S @@ -0,0 +1,216 @@ +/* + * String handling functions for PowerPC. + * + * Copyright (C) 1996 Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + + .globl strcpy +strcpy: + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r5) + bne 1b + blr + + .globl strncpy +strncpy: + cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r6,r3,-1 + addi r4,r4,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r6) + bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */ + blr + + .globl strcat +strcat: + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r0,1(r5) + cmpwi 0,r0,0 + bne 1b + addi r5,r5,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r5) + bne 1b + blr + + .globl strcmp +strcmp: + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r3,1(r5) + cmpwi 1,r3,0 + lbzu r0,1(r4) + subf. r3,r0,r3 + beqlr 1 + beq 1b + blr + + .globl strlen +strlen: + addi r4,r3,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + bne 1b + subf r3,r3,r4 + blr + + .globl memset +memset: + rlwimi r4,r4,8,16,23 + rlwimi r4,r4,16,0,15 + addi r6,r3,-4 + cmplwi 0,r5,4 + blt 7f + stwu r4,4(r6) + beqlr + andi. r0,r6,3 + add r5,r0,r5 + subf r6,r0,r6 + rlwinm r0,r5,32-2,2,31 + mtctr r0 + bdz 6f +1: stwu r4,4(r6) + bdnz 1b +6: andi. r5,r5,3 +7: cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r6,r6,3 +8: stbu r4,1(r6) + bdnz 8b + blr + + .globl bcopy +bcopy: + mr r6,r3 + mr r3,r4 + mr r4,r6 + b memcpy + + .globl memmove +memmove: + cmplw 0,r3,r4 + bgt backwards_memcpy + /* fall through */ + + .globl memcpy +memcpy: + rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ + addi r6,r3,-4 + addi r4,r4,-4 + beq 2f /* if less than 8 bytes to do */ + andi. r0,r6,3 /* get dest word aligned */ + mtctr r7 + bne 5f +1: lwz r7,4(r4) + lwzu r8,8(r4) + stw r7,4(r6) + stwu r8,8(r6) + bdnz 1b + andi. r5,r5,7 +2: cmplwi 0,r5,4 + blt 3f + lwzu r0,4(r4) + addi r5,r5,-4 + stwu r0,4(r6) +3: cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r4,r4,3 + addi r6,r6,3 +4: lbzu r0,1(r4) + stbu r0,1(r6) + bdnz 4b + blr +5: subfic r0,r0,4 + mtctr r0 +6: lbz r7,4(r4) + addi r4,r4,1 + stb r7,4(r6) + addi r6,r6,1 + bdnz 6b + subf r5,r0,r5 + rlwinm. r7,r5,32-3,3,31 + beq 2b + mtctr r7 + b 1b + + .globl backwards_memcpy +backwards_memcpy: + rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ + add r6,r3,r5 + add r4,r4,r5 + beq 2f + andi. r0,r6,3 + mtctr r7 + bne 5f +1: lwz r7,-4(r4) + lwzu r8,-8(r4) + stw r7,-4(r6) + stwu r8,-8(r6) + bdnz 1b + andi. r5,r5,7 +2: cmplwi 0,r5,4 + blt 3f + lwzu r0,-4(r4) + subi r5,r5,4 + stwu r0,-4(r6) +3: cmpwi 0,r5,0 + beqlr + mtctr r5 +4: lbzu r0,-1(r4) + stbu r0,-1(r6) + bdnz 4b + blr +5: mtctr r0 +6: lbzu r7,-1(r4) + stbu r7,-1(r6) + bdnz 6b + subf r5,r0,r5 + rlwinm. r7,r5,32-3,3,31 + beq 2b + mtctr r7 + b 1b + + .globl memcmp +memcmp: + cmpwi 0,r5,0 + ble- 2f + mtctr r5 + addi r6,r3,-1 + addi r4,r4,-1 +1: lbzu r3,1(r6) + lbzu r0,1(r4) + subf. r3,r0,r3 + bdnzt 2,1b + blr +2: li r3,0 + blr + + .global memchr +memchr: + cmpwi 0,r5,0 + ble- 2f + mtctr r5 + addi r3,r3,-1 +1: lbzu r0,1(r3) + cmpw 0,r0,r4 + bdnzf 2,1b + beqlr +2: li r3,0 + blr diff --git a/tools/updater/string.c b/tools/updater/string.c new file mode 100644 index 0000000..954fb01 --- /dev/null +++ b/tools/updater/string.c @@ -0,0 +1,340 @@ +/* + * linux/lib/string.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* + * stupid library routines.. The optimized versions should generally be found + * as inline code in + * + * These are buggy as well.. + */ + +#include +#include +#include + +#define __HAVE_ARCH_BCOPY +#define __HAVE_ARCH_MEMCMP +#define __HAVE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMMOVE +#define __HAVE_ARCH_MEMSET +#define __HAVE_ARCH_STRCAT +#define __HAVE_ARCH_STRCMP +#define __HAVE_ARCH_STRCPY +#define __HAVE_ARCH_STRLEN +#define __HAVE_ARCH_STRNCPY + +char * ___strtok = NULL; + +#ifndef __HAVE_ARCH_STRCPY +char * strcpy(char * dest,const char *src) +{ + char *tmp = dest; + + while ((*dest++ = *src++) != '\0') + /* nothing */; + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRNCPY +char * strncpy(char * dest,const char *src,size_t count) +{ + char *tmp = dest; + + while (count-- && (*dest++ = *src++) != '\0') + /* nothing */; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCAT +char * strcat(char * dest, const char * src) +{ + char *tmp = dest; + + while (*dest) + dest++; + while ((*dest++ = *src++) != '\0') + ; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRNCAT +char * strncat(char *dest, const char *src, size_t count) +{ + char *tmp = dest; + + if (count) { + while (*dest) + dest++; + while ((*dest++ = *src++)) { + if (--count == 0) { + *dest = '\0'; + break; + } + } + } + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCMP +int strcmp(const char * cs,const char * ct) +{ + register signed char __res; + + while (1) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRNCMP +int strncmp(const char * cs,const char * ct,size_t count) +{ + register signed char __res = 0; + + while (count) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + count--; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRCHR +char * strchr(const char * s, int c) +{ + for(; *s != (char) c; ++s) + if (*s == '\0') + return NULL; + return (char *) s; +} +#endif + +#ifndef __HAVE_ARCH_STRRCHR +char * strrchr(const char * s, int c) +{ + const char *p = s + strlen(s); + do { + if (*p == (char)c) + return (char *)p; + } while (--p >= s); + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_STRLEN +size_t strlen(const char * s) +{ + const char *sc; + + for (sc = s; *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRNLEN +size_t strnlen(const char * s, size_t count) +{ + const char *sc; + + for (sc = s; count-- && *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRDUP +char * strdup(const char *s) +{ + char *new; + + if ((s == NULL) || + ((new = malloc (strlen(s) + 1)) == NULL) ) { + return NULL; + } + + strcpy (new, s); + return new; +} +#endif + +#ifndef __HAVE_ARCH_STRSPN +size_t strspn(const char *s, const char *accept) +{ + const char *p; + const char *a; + size_t count = 0; + + for (p = s; *p != '\0'; ++p) { + for (a = accept; *a != '\0'; ++a) { + if (*p == *a) + break; + } + if (*a == '\0') + return count; + ++count; + } + + return count; +} +#endif + +#ifndef __HAVE_ARCH_STRPBRK +char * strpbrk(const char * cs,const char * ct) +{ + const char *sc1,*sc2; + + for( sc1 = cs; *sc1 != '\0'; ++sc1) { + for( sc2 = ct; *sc2 != '\0'; ++sc2) { + if (*sc1 == *sc2) + return (char *) sc1; + } + } + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_STRTOK +char * strtok(char * s,const char * ct) +{ + char *sbegin, *send; + + sbegin = s ? s : ___strtok; + if (!sbegin) { + return NULL; + } + sbegin += strspn(sbegin,ct); + if (*sbegin == '\0') { + ___strtok = NULL; + return( NULL ); + } + send = strpbrk( sbegin, ct); + if (send && *send != '\0') + *send++ = '\0'; + ___strtok = send; + return (sbegin); +} +#endif + +#ifndef __HAVE_ARCH_MEMSET +void * memset(void * s,char c,size_t count) +{ + char *xs = (char *) s; + + while (count--) + *xs++ = c; + + return s; +} +#endif + +#ifndef __HAVE_ARCH_BCOPY +char * bcopy(const char * src, char * dest, int count) +{ + char *tmp = dest; + + while (count--) + *tmp++ = *src++; + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMCPY +void * memcpy(void * dest,const void *src,size_t count) +{ + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMMOVE +void * memmove(void * dest,const void *src,size_t count) +{ + char *tmp, *s; + + if (dest <= src) { + tmp = (char *) dest; + s = (char *) src; + while (count--) + *tmp++ = *s++; + } + else { + tmp = (char *) dest + count; + s = (char *) src + count; + while (count--) + *--tmp = *--s; + } + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMCMP +int memcmp(const void * cs,const void * ct,size_t count) +{ + const unsigned char *su1, *su2; + signed char res = 0; + + for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) + if ((res = *su1 - *su2) != 0) + break; + return res; +} +#endif + +/* + * find the first occurrence of byte 'c', or 1 past the area if none + */ +#ifndef __HAVE_ARCH_MEMSCAN +void * memscan(void * addr, int c, size_t size) +{ + unsigned char * p = (unsigned char *) addr; + + while (size) { + if (*p == c) + return (void *) p; + p++; + size--; + } + return (void *) p; +} +#endif + +#ifndef __HAVE_ARCH_STRSTR +char * strstr(const char * s1,const char * s2) +{ + int l1, l2; + + l2 = strlen(s2); + if (!l2) + return (char *) s1; + l1 = strlen(s1); + while (l1 >= l2) { + l1--; + if (!memcmp(s1,s2,l2)) + return (char *) s1; + s1++; + } + return NULL; +} +#endif diff --git a/tools/updater/update.c b/tools/updater/update.c new file mode 100644 index 0000000..b6d50d5 --- /dev/null +++ b/tools/updater/update.c @@ -0,0 +1,67 @@ +#include +#include + +extern unsigned long __dummy; +void do_reset (void); +void do_updater(void); + +void _main(void) +{ + int i; + printf("U-Boot Firmware Updater\n\n\n"); + printf("****************************************************\n" + "* ATTENTION!! PLEASE READ THIS NOTICE CAREFULLY! *\n" + "****************************************************\n\n" + "This program will update your computer's firmware.\n" + "Do NOT remove the disk, reset the machine, or do\n" + "anything that might disrupt functionality. If this\n"); + printf("Program fails, your computer might be unusable, and\n" + "you will need to return your board for reflashing.\n" + "If you find this too risky, remove the diskette and\n" + "switch off your machine now. Otherwise press the \n" + "SPACE key now to start the process\n\n"); + do + { + char x; + while (!tstc()); + x = getc(); + if (x == ' ') break; + } while (1); + + do_updater(); + + i = 5; + + printf("\nUpdate done. Please remove diskette.\n"); + printf("The machine will automatically reset in %d seconds\n", i); + printf("You can switch off/reset now when the floppy is removed\n\n"); + + while (i) + { + printf("Resetting in %d\r", i); + udelay(1000000); + i--; + } + do_reset(); + while (1); +} + +int flash_sect_protect (int p, ulong addr_first, ulong addr_last); +int flash_sect_erase (ulong addr_first, ulong addr_last); +int flash_write (uchar *src, ulong addr, ulong cnt); + +void do_updater(void) +{ + unsigned long *addr = &__dummy + 65; + unsigned long flash_size = flash_init(); + int rc; + + flash_sect_protect(0, 0xFFF00000, 0xFFF7FFFF); + printf("Erasing "); + flash_sect_erase(0xFFF00000, 0xFFF7FFFF); + printf("Writing "); + rc = flash_write((uchar *)addr, 0xFFF00000, 0x7FFFF); + if (rc != 0) printf("\nFlashing failed due to error %d\n", rc); + else printf("\ndone\n"); + flash_sect_protect(1, 0xFFF00000, 0xFFF7FFFF); +} diff --git a/tools/updater/utils.c b/tools/updater/utils.c new file mode 100644 index 0000000..0304f94 --- /dev/null +++ b/tools/updater/utils.c @@ -0,0 +1,148 @@ +#include +#include +#include +#include + +static __inline__ unsigned long +get_msr(void) +{ + unsigned long msr; + + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void +set_msr(unsigned long msr) +{ + asm volatile("mtmsr %0" : : "r" (msr)); +} + +static __inline__ unsigned long +get_dec(void) +{ + unsigned long val; + + asm volatile("mfdec %0" : "=r" (val) :); + return val; +} + + +static __inline__ void +set_dec(unsigned long val) +{ + asm volatile("mtdec %0" : : "r" (val)); +} + + +void +enable_interrupts(void) +{ + set_msr (get_msr() | MSR_EE); +} + +/* returns flag if MSR_EE was set before */ +int +disable_interrupts(void) +{ + ulong msr; + + msr = get_msr(); + set_msr (msr & ~MSR_EE); + return ((msr & MSR_EE) != 0); +} + +u8 in8(u32 port) +{ + return in_byte(port); +} + +void out8(u32 port, u8 val) +{ + out_byte(port, val); +} + +unsigned long in32(u32 port) +{ + return in_long(port); +} + +unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) +{ + unsigned long result = 0,value; + + if (*cp == '0') { + cp++; + if ((*cp == 'x') && isxdigit(cp[1])) { + base = 16; + cp++; + } + if (!base) { + base = 8; + } + } + if (!base) { + base = 10; + } + while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) + ? toupper(*cp) : *cp)-'A'+10) < base) { + result = result*base + value; + cp++; + } + if (endp) + *endp = (char *)cp; + return result; +} + +long simple_strtol(const char *cp,char **endp,unsigned int base) +{ + if(*cp=='-') + return -simple_strtoul(cp+1,endp,base); + return simple_strtoul(cp,endp,base); +} + +static inline void +soft_restart(unsigned long addr) +{ + /* SRR0 has system reset vector, SRR1 has default MSR value */ + /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ + + __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); + __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); + __asm__ __volatile__ ("mtspr 27, 4"); + __asm__ __volatile__ ("rfi"); + + while(1); /* not reached */ +} + +void +do_reset (void) +{ + ulong addr; + /* flush and disable I/D cache */ + __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); + __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); + __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); + __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 4"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 5"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + +#ifdef CFG_RESET_ADDRESS + addr = CFG_RESET_ADDRESS; +#else + /* + * note: when CFG_MONITOR_BASE points to a RAM address, + * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid + * address. Better pick an address known to be invalid on your + * system and assign it to CFG_RESET_ADDRESS. + */ + addr = CFG_MONITOR_BASE - sizeof (ulong); +#endif + soft_restart(addr); + while(1); /* not reached */ +}